Merge the Cavium Octeon SDK 2.3.0 Simple Executive code and update FreeBSD to

make use of it where possible. This primarily brings in support for newer hardware, and FreeBSD is not yet able to support the abundance of IRQs on new hardware and many features in the Ethernet driver. Because of the changes to IRQs in the Simple Executive, we have to maintain our own list of Octeon IRQs now, which probably can be pared-down and be specific to the CIU interrupt unit soon, and when other interrupt mechanisms are added they can maintain their own definitions. Remove unmasking of interrupts from within the UART device now that the function used is no longer present in the Simple Executive. The unmasking seems to have been gratuitous as this is more properly handled by the buses above the UART device, and seems to work on that basis.
author: jmallett <jmallett@FreeBSD.org> 2012-03-11 06:17:49 +0000
committer: jmallett <jmallett@FreeBSD.org> 2012-03-11 06:17:49 +0000
commit: 56248d9da883404c78cefac055d0e0e1ae17dbc3 (patch)
tree: af4d9dcf90392eaadc4a3c38e945d006122e33c9
parent: 8bd1c57ee7ce29a7f3647cdc3e0c0d52ce1e223f (diff)
parent: 74539243c8f2e35e30bcbed4f81f61738ba9a0e2 (diff)
download: FreeBSD-src-56248d9da883404c78cefac055d0e0e1ae17dbc3.zip
FreeBSD-src-56248d9da883404c78cefac055d0e0e1ae17dbc3.tar.gz
303 files changed, 294164 insertions, 31860 deletions
diff --git a/sys/contrib/octeon-sdk/README.txt b/sys/contrib/octeon-sdk/README.txt
new file mode 100644
index 0000000..fc83b72
--- /dev/null
+++ b/sys/contrib/octeon-sdk/README.txt
@@ -0,0 +1,43 @@
+Readme for the OCTEON Executive Library
+
+
+The OCTEON Executive Library provides runtime support and hardware 
+abstraction for the OCTEON processor.  The executive is composed of the 
+libcvmx.a library as well as header files that provide  
+functionality with inline functions.
+
+
+Usage:
+
+The libcvmx.a library is built for every application as part of the
+application build. (Please refer to the 'related pages' section of the 
+HTML documentation for more information on the build system.)  
+Applications using the executive should include the header files from
+$OCTEON_ROOT/target/include and link against the library that is built in 
+the local obj directory. Each file using the executive 
+should include the following two header files in order:
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+
+The cvmx-config.h file contains configuration information for the 
+executive and is generated by the cvmx-config script from an 
+'executive-config.h' file. A sample version of this file is provided 
+in the executive directory as 'executive-config.h.template'.  
+
+Copy this file to 'executive-config.h' into the 'config' subdirectory 
+of the application directory and customize as required by the application. 
+Applications that don't use any simple executive functionality can omit 
+the cvmx-config.h header file. Please refer to the examples for a 
+demonstration of where to put the executive-config.h file and for an
+example of generated cvmx-config.h.
+
+For file specific information please see the documentation within the 
+source files or the HTML documentation provided in docs/html/index.html.
+The HTML documentation is automatically generated by Doxygen from the 
+source files.
+
+
+
+==========================================================================
+Please see the release notes for version specific information.
diff --git a/sys/contrib/octeon-sdk/cvmip.h b/sys/contrib/octeon-sdk/cvmip.h
index b3aa6b0..4bcaaa6 100644
--- a/sys/contrib/octeon-sdk/cvmip.h
+++ b/sys/contrib/octeon-sdk/cvmip.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -46,11 +46,11 @@
 /**
  * @file
  *
- * Cavium Networks Internet Protocol (IP)
+ * Cavium Inc. Internet Protocol (IP)
  *
  * Definitions for the Internet Protocol (IP) support.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-abi.h b/sys/contrib/octeon-sdk/cvmx-abi.h
index 93d71b3..f727e99 100644
--- a/sys/contrib/octeon-sdk/cvmx-abi.h
+++ b/sys/contrib/octeon-sdk/cvmx-abi.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -39,21 +39,25 @@
 
 
 
-
-
-
-
 /**
  * @file
  *
  * This file defines macros for use in determining the current calling ABI.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
 */
 
 #ifndef __CVMX_ABI_H__
 #define __CVMX_ABI_H__
 
+#if defined(__FreeBSD__) && defined(_KERNEL)
+#include <machine/endian.h>
+#else
+#ifndef __U_BOOT__
+#include <endian.h>
+#endif
+#endif
+
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -87,6 +91,20 @@ extern "C" {
     #endif
 #endif
 
+/* For compatibility with Linux definitions... */
+#if __BYTE_ORDER == __BIG_ENDIAN
+# ifndef __BIG_ENDIAN_BITFIELD
+#  define __BIG_ENDIAN_BITFIELD
+# endif
+#else
+# ifndef __LITTLE_ENDIAN_BITFIELD
+#  define __LITTLE_ENDIAN_BITFIELD
+# endif
+#endif
+#if defined(__BIG_ENDIAN_BITFIELD) && defined(__LITTLE_ENDIAN_BITFIELD)
+# error Cannot define both __BIG_ENDIAN_BITFIELD and __LITTLE_ENDIAN_BITFIELD
+#endif
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-access-native.h b/sys/contrib/octeon-sdk/cvmx-access-native.h
index 962671c..78d8029 100644
--- a/sys/contrib/octeon-sdk/cvmx-access-native.h
+++ b/sys/contrib/octeon-sdk/cvmx-access-native.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -183,12 +183,6 @@ static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
         cvmx_warn_if(physical_address==0, "cvmx_phys_to_ptr() passed a zero address\n");
 
 #ifdef CVMX_BUILD_FOR_UBOOT
-#if !CONFIG_OCTEON_UBOOT_TLB
-    if (physical_address >= 0x80000000)
-        return NULL;
-    else
-        return CASTPTR(void, (physical_address & 0x7FFFFFFF));
-#endif
 
     /* U-boot is a special case, as it is running in 32 bit mode, using the TLB to map code/data
     ** which can have a physical address above the 32 bit address space.  1-1 mappings are used
@@ -251,8 +245,9 @@ static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
         2nd 256MB is mapped at 0x10000000 and the rest of memory is 1:1 */
     if ((physical_address >= 0x10000000) && (physical_address < 0x20000000))
         return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
-    else if (!OCTEON_IS_MODEL(OCTEON_CN6XXX) && (physical_address >= 0x410000000ull) &&
-                                                       (physical_address < 0x420000000ull))
+    else if ((OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
+              && (physical_address >= 0x410000000ull)
+              && (physical_address < 0x420000000ull))
         return CASTPTR(void, physical_address - 0x400000000ull);
     else
         return CASTPTR(void, physical_address);
diff --git a/sys/contrib/octeon-sdk/cvmx-access.h b/sys/contrib/octeon-sdk/cvmx-access.h
index c1206dd..43190f6 100644
--- a/sys/contrib/octeon-sdk/cvmx-access.h
+++ b/sys/contrib/octeon-sdk/cvmx-access.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-address.h b/sys/contrib/octeon-sdk/cvmx-address.h
index daaf6a4..d59c41d 100644
--- a/sys/contrib/octeon-sdk/cvmx-address.h
+++ b/sys/contrib/octeon-sdk/cvmx-address.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -47,6 +47,10 @@
 #ifndef __CVMX_ADDRESS_H__
 #define __CVMX_ADDRESS_H__
 
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+#include "cvmx-abi.h"
+#endif
+
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -233,6 +237,7 @@ typedef union {
 #define CVMX_OCT_DID_TAG_TAG2       CVMX_FULL_DID(CVMX_OCT_DID_TAG,2ULL)
 #define CVMX_OCT_DID_TAG_TAG3       CVMX_FULL_DID(CVMX_OCT_DID_TAG,3ULL)
 #define CVMX_OCT_DID_TAG_NULL_RD    CVMX_FULL_DID(CVMX_OCT_DID_TAG,4ULL)
+#define CVMX_OCT_DID_TAG_TAG5       CVMX_FULL_DID(CVMX_OCT_DID_TAG,5ULL)
 #define CVMX_OCT_DID_TAG_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TAG,7ULL)
 #define CVMX_OCT_DID_FAU_FAI        CVMX_FULL_DID(CVMX_OCT_DID_IOB,0ULL)
 #define CVMX_OCT_DID_TIM_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TIM,0ULL)
@@ -245,6 +250,14 @@ typedef union {
 #define CVMX_OCT_DID_MIS_CSR        CVMX_FULL_DID(CVMX_OCT_DID_MIS,7ULL)
 #define CVMX_OCT_DID_ZIP_CSR        CVMX_FULL_DID(CVMX_OCT_DID_ZIP,0ULL)
 
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+#ifdef CVMX_ABI_N32
+#define UNMAPPED_PTR(x) ( (1U << 31) | x )
+#else
+#define UNMAPPED_PTR(x) ( (1ULL << 63) | x )
+#endif
+#endif
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-agl-defs.h b/sys/contrib/octeon-sdk/cvmx-agl-defs.h
index 2138f90..13afef3 100644
--- a/sys/contrib/octeon-sdk/cvmx-agl-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-agl-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,14 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_AGL_TYPEDEFS_H__
-#define __CVMX_AGL_TYPEDEFS_H__
+#ifndef __CVMX_AGL_DEFS_H__
+#define __CVMX_AGL_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_AGL_GMX_BAD_REG CVMX_AGL_GMX_BAD_REG_FUNC()
 static inline uint64_t CVMX_AGL_GMX_BAD_REG_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_BAD_REG not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E0000518ull);
 }
@@ -67,7 +67,7 @@ static inline uint64_t CVMX_AGL_GMX_BAD_REG_FUNC(void)
 #define CVMX_AGL_GMX_BIST CVMX_AGL_GMX_BIST_FUNC()
 static inline uint64_t CVMX_AGL_GMX_BIST_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_BIST not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E0000400ull);
 }
@@ -102,7 +102,10 @@ static inline uint64_t CVMX_AGL_GMX_PRTX_CFG(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_PRTX_CFG(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048;
 }
@@ -115,7 +118,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM0(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM0(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048;
 }
@@ -128,7 +134,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM1(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM1(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048;
 }
@@ -141,7 +150,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM2(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM2(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048;
 }
@@ -154,7 +166,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM3(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM3(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048;
 }
@@ -167,7 +182,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM4(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM4(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048;
 }
@@ -180,7 +198,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM5(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM5(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048;
 }
@@ -193,7 +214,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM_EN(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM_EN(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048;
 }
@@ -206,7 +230,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CTL(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CTL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048;
 }
@@ -219,7 +246,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_DECISION(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_DECISION(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048;
 }
@@ -232,7 +262,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_FRM_CHK(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CHK(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048;
 }
@@ -245,7 +278,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_FRM_CTL(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CTL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048;
 }
@@ -258,7 +294,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_FRM_MAX(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MAX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048;
 }
@@ -271,7 +310,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_FRM_MIN(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MIN(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048;
 }
@@ -284,7 +326,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_IFG(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_IFG(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048;
 }
@@ -297,7 +342,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_INT_EN(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_INT_EN(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048;
 }
@@ -310,7 +358,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_INT_REG(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_INT_REG(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048;
 }
@@ -323,7 +374,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_JABBER(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_JABBER(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048;
 }
@@ -336,7 +390,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048;
 }
@@ -347,7 +404,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(unsigned long offset)
 static inline uint64_t CVMX_AGL_GMX_RXX_RX_INBND(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_RX_INBND(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048;
 }
@@ -360,7 +420,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_CTL(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_CTL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048;
 }
@@ -373,7 +436,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048;
 }
@@ -386,7 +452,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048;
 }
@@ -399,7 +468,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048;
 }
@@ -412,7 +484,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048;
 }
@@ -425,7 +500,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048;
 }
@@ -438,7 +516,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048;
 }
@@ -451,7 +532,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048;
 }
@@ -464,7 +548,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048;
 }
@@ -477,7 +564,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048;
 }
@@ -490,7 +580,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_UDD_SKP(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_UDD_SKP(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048;
 }
@@ -503,7 +596,10 @@ static inline uint64_t CVMX_AGL_GMX_RX_BP_DROPX(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RX_BP_DROPX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8;
 }
@@ -516,7 +612,10 @@ static inline uint64_t CVMX_AGL_GMX_RX_BP_OFFX(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RX_BP_OFFX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8;
 }
@@ -529,7 +628,10 @@ static inline uint64_t CVMX_AGL_GMX_RX_BP_ONX(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RX_BP_ONX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8;
 }
@@ -540,7 +642,7 @@ static inline uint64_t CVMX_AGL_GMX_RX_BP_ONX(unsigned long offset)
 #define CVMX_AGL_GMX_RX_PRT_INFO CVMX_AGL_GMX_RX_PRT_INFO_FUNC()
 static inline uint64_t CVMX_AGL_GMX_RX_PRT_INFO_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_RX_PRT_INFO not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E00004E8ull);
 }
@@ -551,7 +653,7 @@ static inline uint64_t CVMX_AGL_GMX_RX_PRT_INFO_FUNC(void)
 #define CVMX_AGL_GMX_RX_TX_STATUS CVMX_AGL_GMX_RX_TX_STATUS_FUNC()
 static inline uint64_t CVMX_AGL_GMX_RX_TX_STATUS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_RX_TX_STATUS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E00007E8ull);
 }
@@ -564,7 +666,10 @@ static inline uint64_t CVMX_AGL_GMX_SMACX(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_SMACX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048;
 }
@@ -575,7 +680,7 @@ static inline uint64_t CVMX_AGL_GMX_SMACX(unsigned long offset)
 #define CVMX_AGL_GMX_STAT_BP CVMX_AGL_GMX_STAT_BP_FUNC()
 static inline uint64_t CVMX_AGL_GMX_STAT_BP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_STAT_BP not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E0000520ull);
 }
@@ -588,7 +693,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_APPEND(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_APPEND(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048;
 }
@@ -599,7 +707,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_APPEND(unsigned long offset)
 static inline uint64_t CVMX_AGL_GMX_TXX_CLK(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_CLK(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048;
 }
@@ -612,7 +723,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_CTL(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_CTL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048;
 }
@@ -625,7 +739,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_MIN_PKT(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_MIN_PKT(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048;
 }
@@ -638,7 +755,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048;
 }
@@ -651,7 +771,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048;
 }
@@ -664,7 +787,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_TOGO(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_TOGO(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048;
 }
@@ -677,7 +803,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_ZERO(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_ZERO(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048;
 }
@@ -690,7 +819,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_SOFT_PAUSE(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_SOFT_PAUSE(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048;
 }
@@ -703,7 +835,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT0(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_STAT0(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048;
 }
@@ -716,7 +851,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT1(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_STAT1(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048;
 }
@@ -729,7 +867,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT2(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_STAT2(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048;
 }
@@ -742,7 +883,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT3(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_STAT3(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048;
 }
@@ -755,7 +899,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT4(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_STAT4(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048;
 }
@@ -768,7 +915,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT5(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_STAT5(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048;
 }
@@ -781,7 +931,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT6(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_STAT6(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048;
 }
@@ -794,7 +947,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT7(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_STAT7(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048;
 }
@@ -807,7 +963,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT8(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_STAT8(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048;
 }
@@ -820,7 +979,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT9(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_STAT9(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048;
 }
@@ -833,7 +995,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STATS_CTL(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_STATS_CTL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048;
 }
@@ -846,7 +1011,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_THRESH(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_THRESH(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048;
 }
@@ -857,7 +1025,7 @@ static inline uint64_t CVMX_AGL_GMX_TXX_THRESH(unsigned long offset)
 #define CVMX_AGL_GMX_TX_BP CVMX_AGL_GMX_TX_BP_FUNC()
 static inline uint64_t CVMX_AGL_GMX_TX_BP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_TX_BP not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E00004D0ull);
 }
@@ -868,7 +1036,7 @@ static inline uint64_t CVMX_AGL_GMX_TX_BP_FUNC(void)
 #define CVMX_AGL_GMX_TX_COL_ATTEMPT CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC()
 static inline uint64_t CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_TX_COL_ATTEMPT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E0000498ull);
 }
@@ -879,7 +1047,7 @@ static inline uint64_t CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC(void)
 #define CVMX_AGL_GMX_TX_IFG CVMX_AGL_GMX_TX_IFG_FUNC()
 static inline uint64_t CVMX_AGL_GMX_TX_IFG_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_TX_IFG not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E0000488ull);
 }
@@ -890,7 +1058,7 @@ static inline uint64_t CVMX_AGL_GMX_TX_IFG_FUNC(void)
 #define CVMX_AGL_GMX_TX_INT_EN CVMX_AGL_GMX_TX_INT_EN_FUNC()
 static inline uint64_t CVMX_AGL_GMX_TX_INT_EN_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_TX_INT_EN not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E0000508ull);
 }
@@ -901,7 +1069,7 @@ static inline uint64_t CVMX_AGL_GMX_TX_INT_EN_FUNC(void)
 #define CVMX_AGL_GMX_TX_INT_REG CVMX_AGL_GMX_TX_INT_REG_FUNC()
 static inline uint64_t CVMX_AGL_GMX_TX_INT_REG_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_TX_INT_REG not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E0000500ull);
 }
@@ -912,7 +1080,7 @@ static inline uint64_t CVMX_AGL_GMX_TX_INT_REG_FUNC(void)
 #define CVMX_AGL_GMX_TX_JAM CVMX_AGL_GMX_TX_JAM_FUNC()
 static inline uint64_t CVMX_AGL_GMX_TX_JAM_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_TX_JAM not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E0000490ull);
 }
@@ -923,7 +1091,7 @@ static inline uint64_t CVMX_AGL_GMX_TX_JAM_FUNC(void)
 #define CVMX_AGL_GMX_TX_LFSR CVMX_AGL_GMX_TX_LFSR_FUNC()
 static inline uint64_t CVMX_AGL_GMX_TX_LFSR_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_TX_LFSR not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E00004F8ull);
 }
@@ -934,7 +1102,7 @@ static inline uint64_t CVMX_AGL_GMX_TX_LFSR_FUNC(void)
 #define CVMX_AGL_GMX_TX_OVR_BP CVMX_AGL_GMX_TX_OVR_BP_FUNC()
 static inline uint64_t CVMX_AGL_GMX_TX_OVR_BP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_TX_OVR_BP not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E00004C8ull);
 }
@@ -945,7 +1113,7 @@ static inline uint64_t CVMX_AGL_GMX_TX_OVR_BP_FUNC(void)
 #define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC()
 static inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E00004A0ull);
 }
@@ -956,7 +1124,7 @@ static inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC(void)
 #define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC()
 static inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E00004A8ull);
 }
@@ -967,7 +1135,10 @@ static inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC(void)
 static inline uint64_t CVMX_AGL_PRTX_CTL(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_PRTX_CTL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8;
 }
@@ -986,12 +1157,10 @@ static inline uint64_t CVMX_AGL_PRTX_CTL(unsigned long offset)
  * OUT_OVR[1], LOSTSTAT[1], OVRFLW1, TXPOP1, TXPSH1 will be reset when MIX1_CTL[RESET] is set to 1.
  * STATOVR will be reset when both MIX0/1_CTL[RESET] are set to 1.
  */
-union cvmx_agl_gmx_bad_reg
-{
+union cvmx_agl_gmx_bad_reg {
 	uint64_t u64;
-	struct cvmx_agl_gmx_bad_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_bad_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_38_63               : 26;
 	uint64_t txpsh1                       : 1;  /**< TX FIFO overflow (MII1) */
 	uint64_t txpop1                       : 1;  /**< TX FIFO underflow (MII1) */
@@ -1025,9 +1194,8 @@ union cvmx_agl_gmx_bad_reg
 	uint64_t reserved_38_63               : 26;
 #endif
 	} s;
-	struct cvmx_agl_gmx_bad_reg_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_bad_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_38_63               : 26;
 	uint64_t txpsh1                       : 1;  /**< TX FIFO overflow (MII1) */
 	uint64_t txpop1                       : 1;  /**< TX FIFO underflow (MII1) */
@@ -1061,9 +1229,8 @@ union cvmx_agl_gmx_bad_reg
 #endif
 	} cn52xx;
 	struct cvmx_agl_gmx_bad_reg_cn52xx    cn52xxp1;
-	struct cvmx_agl_gmx_bad_reg_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_bad_reg_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_35_63               : 29;
 	uint64_t txpsh                        : 1;  /**< TX FIFO overflow */
 	uint64_t txpop                        : 1;  /**< TX FIFO underflow */
@@ -1091,8 +1258,12 @@ union cvmx_agl_gmx_bad_reg
 #endif
 	} cn56xx;
 	struct cvmx_agl_gmx_bad_reg_cn56xx    cn56xxp1;
+	struct cvmx_agl_gmx_bad_reg_s         cn61xx;
 	struct cvmx_agl_gmx_bad_reg_s         cn63xx;
 	struct cvmx_agl_gmx_bad_reg_s         cn63xxp1;
+	struct cvmx_agl_gmx_bad_reg_s         cn66xx;
+	struct cvmx_agl_gmx_bad_reg_s         cn68xx;
+	struct cvmx_agl_gmx_bad_reg_s         cn68xxp1;
 };
 typedef union cvmx_agl_gmx_bad_reg cvmx_agl_gmx_bad_reg_t;
 
@@ -1106,12 +1277,10 @@ typedef union cvmx_agl_gmx_bad_reg cvmx_agl_gmx_bad_reg_t;
  * Not reset when MIX*_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_bist
-{
+union cvmx_agl_gmx_bist {
 	uint64_t u64;
-	struct cvmx_agl_gmx_bist_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_bist_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_25_63               : 39;
 	uint64_t status                       : 25; /**< BIST Results.
                                                          HW sets a bit in BIST for for memory that fails
@@ -1131,8 +1300,8 @@ union cvmx_agl_gmx_bist
                                                          - 13: gmx#.outb.fif.fif_bnk_ext1
                                                          - 14: RAZ
                                                          - 15: RAZ
-                                                         - 16: gmx#.csr.gmi0.srf8x64m1_bist
-                                                         - 17: gmx#.csr.gmi1.srf8x64m1_bist
+                                                         - 16: RAZ
+                                                         - 17: RAZ
                                                          - 18: RAZ
                                                          - 19: RAZ
                                                          - 20: gmx#.csr.drf20x32m2_bist
@@ -1145,9 +1314,8 @@ union cvmx_agl_gmx_bist
 	uint64_t reserved_25_63               : 39;
 #endif
 	} s;
-	struct cvmx_agl_gmx_bist_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_bist_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t status                       : 10; /**< BIST Results.
                                                           HW sets a bit in BIST for for memory that fails
@@ -1169,8 +1337,12 @@ union cvmx_agl_gmx_bist
 	struct cvmx_agl_gmx_bist_cn52xx       cn52xxp1;
 	struct cvmx_agl_gmx_bist_cn52xx       cn56xx;
 	struct cvmx_agl_gmx_bist_cn52xx       cn56xxp1;
+	struct cvmx_agl_gmx_bist_s            cn61xx;
 	struct cvmx_agl_gmx_bist_s            cn63xx;
 	struct cvmx_agl_gmx_bist_s            cn63xxp1;
+	struct cvmx_agl_gmx_bist_s            cn66xx;
+	struct cvmx_agl_gmx_bist_s            cn68xx;
+	struct cvmx_agl_gmx_bist_s            cn68xxp1;
 };
 typedef union cvmx_agl_gmx_bist cvmx_agl_gmx_bist_t;
 
@@ -1184,12 +1356,10 @@ typedef union cvmx_agl_gmx_bist cvmx_agl_gmx_bist_t;
  * NCTL, PCTL, BYP_EN    will be reset when MIX0_CTL[RESET] is set to 1.
  * NCTL1, PCTL1, BYP_EN1 will be reset when MIX1_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_drv_ctl
-{
+union cvmx_agl_gmx_drv_ctl {
 	uint64_t u64;
-	struct cvmx_agl_gmx_drv_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_drv_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_49_63               : 15;
 	uint64_t byp_en1                      : 1;  /**< Compensation Controller Bypass Enable (MII1) */
 	uint64_t reserved_45_47               : 3;
@@ -1219,9 +1389,8 @@ union cvmx_agl_gmx_drv_ctl
 	} s;
 	struct cvmx_agl_gmx_drv_ctl_s         cn52xx;
 	struct cvmx_agl_gmx_drv_ctl_s         cn52xxp1;
-	struct cvmx_agl_gmx_drv_ctl_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_drv_ctl_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t byp_en                       : 1;  /**< Compensation Controller Bypass Enable */
 	uint64_t reserved_13_15               : 3;
@@ -1251,12 +1420,10 @@ typedef union cvmx_agl_gmx_drv_ctl cvmx_agl_gmx_drv_ctl_t;
  * Not reset when MIX*_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_inf_mode
-{
+union cvmx_agl_gmx_inf_mode {
 	uint64_t u64;
-	struct cvmx_agl_gmx_inf_mode_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_inf_mode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t en                           : 1;  /**< Interface Enable */
 	uint64_t reserved_0_0                 : 1;
@@ -1283,12 +1450,10 @@ typedef union cvmx_agl_gmx_inf_mode cvmx_agl_gmx_inf_mode_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_prtx_cfg
-{
+union cvmx_agl_gmx_prtx_cfg {
 	uint64_t u64;
-	struct cvmx_agl_gmx_prtx_cfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_prtx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t tx_idle                      : 1;  /**< TX Machine is idle */
 	uint64_t rx_idle                      : 1;  /**< RX Machine is idle */
@@ -1346,9 +1511,8 @@ union cvmx_agl_gmx_prtx_cfg
 	uint64_t reserved_14_63               : 50;
 #endif
 	} s;
-	struct cvmx_agl_gmx_prtx_cfg_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_prtx_cfg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t tx_en                        : 1;  /**< Port enable.  Must be set for Octane to send
                                                          RMGII traffic.   When this bit clear on a given
@@ -1388,8 +1552,12 @@ union cvmx_agl_gmx_prtx_cfg
 	struct cvmx_agl_gmx_prtx_cfg_cn52xx   cn52xxp1;
 	struct cvmx_agl_gmx_prtx_cfg_cn52xx   cn56xx;
 	struct cvmx_agl_gmx_prtx_cfg_cn52xx   cn56xxp1;
+	struct cvmx_agl_gmx_prtx_cfg_s        cn61xx;
 	struct cvmx_agl_gmx_prtx_cfg_s        cn63xx;
 	struct cvmx_agl_gmx_prtx_cfg_s        cn63xxp1;
+	struct cvmx_agl_gmx_prtx_cfg_s        cn66xx;
+	struct cvmx_agl_gmx_prtx_cfg_s        cn68xx;
+	struct cvmx_agl_gmx_prtx_cfg_s        cn68xxp1;
 };
 typedef union cvmx_agl_gmx_prtx_cfg cvmx_agl_gmx_prtx_cfg_t;
 
@@ -1403,16 +1571,12 @@ typedef union cvmx_agl_gmx_prtx_cfg cvmx_agl_gmx_prtx_cfg_t;
  * Not reset when MIX*_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_rxx_adr_cam0
-{
+union cvmx_agl_gmx_rxx_adr_cam0 {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_adr_cam0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_adr_cam0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t adr                          : 64; /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
-                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+                                                         Each entry contributes 8bits to one of 8 matchers.
                                                          The CAM matches against unicst or multicst DMAC
                                                          addresses. */
 #else
@@ -1423,8 +1587,12 @@ union cvmx_agl_gmx_rxx_adr_cam0
 	struct cvmx_agl_gmx_rxx_adr_cam0_s    cn52xxp1;
 	struct cvmx_agl_gmx_rxx_adr_cam0_s    cn56xx;
 	struct cvmx_agl_gmx_rxx_adr_cam0_s    cn56xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam0_s    cn61xx;
 	struct cvmx_agl_gmx_rxx_adr_cam0_s    cn63xx;
 	struct cvmx_agl_gmx_rxx_adr_cam0_s    cn63xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam0_s    cn66xx;
+	struct cvmx_agl_gmx_rxx_adr_cam0_s    cn68xx;
+	struct cvmx_agl_gmx_rxx_adr_cam0_s    cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_adr_cam0 cvmx_agl_gmx_rxx_adr_cam0_t;
 
@@ -1438,16 +1606,12 @@ typedef union cvmx_agl_gmx_rxx_adr_cam0 cvmx_agl_gmx_rxx_adr_cam0_t;
  * Not reset when MIX*_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_rxx_adr_cam1
-{
+union cvmx_agl_gmx_rxx_adr_cam1 {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_adr_cam1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_adr_cam1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t adr                          : 64; /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
-                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+                                                         Each entry contributes 8bits to one of 8 matchers.
                                                          The CAM matches against unicst or multicst DMAC
                                                          addresses. */
 #else
@@ -1458,8 +1622,12 @@ union cvmx_agl_gmx_rxx_adr_cam1
 	struct cvmx_agl_gmx_rxx_adr_cam1_s    cn52xxp1;
 	struct cvmx_agl_gmx_rxx_adr_cam1_s    cn56xx;
 	struct cvmx_agl_gmx_rxx_adr_cam1_s    cn56xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam1_s    cn61xx;
 	struct cvmx_agl_gmx_rxx_adr_cam1_s    cn63xx;
 	struct cvmx_agl_gmx_rxx_adr_cam1_s    cn63xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam1_s    cn66xx;
+	struct cvmx_agl_gmx_rxx_adr_cam1_s    cn68xx;
+	struct cvmx_agl_gmx_rxx_adr_cam1_s    cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_adr_cam1 cvmx_agl_gmx_rxx_adr_cam1_t;
 
@@ -1473,16 +1641,12 @@ typedef union cvmx_agl_gmx_rxx_adr_cam1 cvmx_agl_gmx_rxx_adr_cam1_t;
  * Not reset when MIX*_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_rxx_adr_cam2
-{
+union cvmx_agl_gmx_rxx_adr_cam2 {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_adr_cam2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_adr_cam2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t adr                          : 64; /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
-                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+                                                         Each entry contributes 8bits to one of 8 matchers.
                                                          The CAM matches against unicst or multicst DMAC
                                                          addresses. */
 #else
@@ -1493,8 +1657,12 @@ union cvmx_agl_gmx_rxx_adr_cam2
 	struct cvmx_agl_gmx_rxx_adr_cam2_s    cn52xxp1;
 	struct cvmx_agl_gmx_rxx_adr_cam2_s    cn56xx;
 	struct cvmx_agl_gmx_rxx_adr_cam2_s    cn56xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam2_s    cn61xx;
 	struct cvmx_agl_gmx_rxx_adr_cam2_s    cn63xx;
 	struct cvmx_agl_gmx_rxx_adr_cam2_s    cn63xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam2_s    cn66xx;
+	struct cvmx_agl_gmx_rxx_adr_cam2_s    cn68xx;
+	struct cvmx_agl_gmx_rxx_adr_cam2_s    cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_adr_cam2 cvmx_agl_gmx_rxx_adr_cam2_t;
 
@@ -1508,16 +1676,12 @@ typedef union cvmx_agl_gmx_rxx_adr_cam2 cvmx_agl_gmx_rxx_adr_cam2_t;
  * Not reset when MIX*_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_rxx_adr_cam3
-{
+union cvmx_agl_gmx_rxx_adr_cam3 {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_adr_cam3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_adr_cam3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t adr                          : 64; /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
-                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+                                                         Each entry contributes 8bits to one of 8 matchers.
                                                          The CAM matches against unicst or multicst DMAC
                                                          addresses. */
 #else
@@ -1528,8 +1692,12 @@ union cvmx_agl_gmx_rxx_adr_cam3
 	struct cvmx_agl_gmx_rxx_adr_cam3_s    cn52xxp1;
 	struct cvmx_agl_gmx_rxx_adr_cam3_s    cn56xx;
 	struct cvmx_agl_gmx_rxx_adr_cam3_s    cn56xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam3_s    cn61xx;
 	struct cvmx_agl_gmx_rxx_adr_cam3_s    cn63xx;
 	struct cvmx_agl_gmx_rxx_adr_cam3_s    cn63xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam3_s    cn66xx;
+	struct cvmx_agl_gmx_rxx_adr_cam3_s    cn68xx;
+	struct cvmx_agl_gmx_rxx_adr_cam3_s    cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_adr_cam3 cvmx_agl_gmx_rxx_adr_cam3_t;
 
@@ -1543,16 +1711,12 @@ typedef union cvmx_agl_gmx_rxx_adr_cam3 cvmx_agl_gmx_rxx_adr_cam3_t;
  * Not reset when MIX*_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_rxx_adr_cam4
-{
+union cvmx_agl_gmx_rxx_adr_cam4 {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_adr_cam4_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_adr_cam4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t adr                          : 64; /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
-                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+                                                         Each entry contributes 8bits to one of 8 matchers.
                                                          The CAM matches against unicst or multicst DMAC
                                                          addresses. */
 #else
@@ -1563,8 +1727,12 @@ union cvmx_agl_gmx_rxx_adr_cam4
 	struct cvmx_agl_gmx_rxx_adr_cam4_s    cn52xxp1;
 	struct cvmx_agl_gmx_rxx_adr_cam4_s    cn56xx;
 	struct cvmx_agl_gmx_rxx_adr_cam4_s    cn56xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam4_s    cn61xx;
 	struct cvmx_agl_gmx_rxx_adr_cam4_s    cn63xx;
 	struct cvmx_agl_gmx_rxx_adr_cam4_s    cn63xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam4_s    cn66xx;
+	struct cvmx_agl_gmx_rxx_adr_cam4_s    cn68xx;
+	struct cvmx_agl_gmx_rxx_adr_cam4_s    cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_adr_cam4 cvmx_agl_gmx_rxx_adr_cam4_t;
 
@@ -1578,16 +1746,12 @@ typedef union cvmx_agl_gmx_rxx_adr_cam4 cvmx_agl_gmx_rxx_adr_cam4_t;
  * Not reset when MIX*_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_rxx_adr_cam5
-{
+union cvmx_agl_gmx_rxx_adr_cam5 {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_adr_cam5_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_adr_cam5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t adr                          : 64; /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
-                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+                                                         Each entry contributes 8bits to one of 8 matchers.
                                                          The CAM matches against unicst or multicst DMAC
                                                          addresses. */
 #else
@@ -1598,8 +1762,12 @@ union cvmx_agl_gmx_rxx_adr_cam5
 	struct cvmx_agl_gmx_rxx_adr_cam5_s    cn52xxp1;
 	struct cvmx_agl_gmx_rxx_adr_cam5_s    cn56xx;
 	struct cvmx_agl_gmx_rxx_adr_cam5_s    cn56xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam5_s    cn61xx;
 	struct cvmx_agl_gmx_rxx_adr_cam5_s    cn63xx;
 	struct cvmx_agl_gmx_rxx_adr_cam5_s    cn63xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam5_s    cn66xx;
+	struct cvmx_agl_gmx_rxx_adr_cam5_s    cn68xx;
+	struct cvmx_agl_gmx_rxx_adr_cam5_s    cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_adr_cam5 cvmx_agl_gmx_rxx_adr_cam5_t;
 
@@ -1613,12 +1781,10 @@ typedef union cvmx_agl_gmx_rxx_adr_cam5 cvmx_agl_gmx_rxx_adr_cam5_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_rxx_adr_cam_en
-{
+union cvmx_agl_gmx_rxx_adr_cam_en {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_adr_cam_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_adr_cam_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t en                           : 8;  /**< CAM Entry Enables */
 #else
@@ -1630,8 +1796,12 @@ union cvmx_agl_gmx_rxx_adr_cam_en
 	struct cvmx_agl_gmx_rxx_adr_cam_en_s  cn52xxp1;
 	struct cvmx_agl_gmx_rxx_adr_cam_en_s  cn56xx;
 	struct cvmx_agl_gmx_rxx_adr_cam_en_s  cn56xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam_en_s  cn61xx;
 	struct cvmx_agl_gmx_rxx_adr_cam_en_s  cn63xx;
 	struct cvmx_agl_gmx_rxx_adr_cam_en_s  cn63xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam_en_s  cn66xx;
+	struct cvmx_agl_gmx_rxx_adr_cam_en_s  cn68xx;
+	struct cvmx_agl_gmx_rxx_adr_cam_en_s  cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_adr_cam_en cvmx_agl_gmx_rxx_adr_cam_en_t;
 
@@ -1679,12 +1849,10 @@ typedef union cvmx_agl_gmx_rxx_adr_cam_en cvmx_agl_gmx_rxx_adr_cam_en_t;
  *
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rxx_adr_ctl
-{
+union cvmx_agl_gmx_rxx_adr_ctl {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_adr_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_adr_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t cam_mode                     : 1;  /**< Allow or deny DMAC address filter
                                                          0 = reject the packet on DMAC address match
@@ -1706,8 +1874,12 @@ union cvmx_agl_gmx_rxx_adr_ctl
 	struct cvmx_agl_gmx_rxx_adr_ctl_s     cn52xxp1;
 	struct cvmx_agl_gmx_rxx_adr_ctl_s     cn56xx;
 	struct cvmx_agl_gmx_rxx_adr_ctl_s     cn56xxp1;
+	struct cvmx_agl_gmx_rxx_adr_ctl_s     cn61xx;
 	struct cvmx_agl_gmx_rxx_adr_ctl_s     cn63xx;
 	struct cvmx_agl_gmx_rxx_adr_ctl_s     cn63xxp1;
+	struct cvmx_agl_gmx_rxx_adr_ctl_s     cn66xx;
+	struct cvmx_agl_gmx_rxx_adr_ctl_s     cn68xx;
+	struct cvmx_agl_gmx_rxx_adr_ctl_s     cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_adr_ctl cvmx_agl_gmx_rxx_adr_ctl_t;
 
@@ -1740,12 +1912,10 @@ typedef union cvmx_agl_gmx_rxx_adr_ctl cvmx_agl_gmx_rxx_adr_ctl_t;
  *
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rxx_decision
-{
+union cvmx_agl_gmx_rxx_decision {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_decision_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_decision_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t cnt                          : 5;  /**< The byte count to decide when to accept or filter
                                                          a packet. */
@@ -1758,8 +1928,12 @@ union cvmx_agl_gmx_rxx_decision
 	struct cvmx_agl_gmx_rxx_decision_s    cn52xxp1;
 	struct cvmx_agl_gmx_rxx_decision_s    cn56xx;
 	struct cvmx_agl_gmx_rxx_decision_s    cn56xxp1;
+	struct cvmx_agl_gmx_rxx_decision_s    cn61xx;
 	struct cvmx_agl_gmx_rxx_decision_s    cn63xx;
 	struct cvmx_agl_gmx_rxx_decision_s    cn63xxp1;
+	struct cvmx_agl_gmx_rxx_decision_s    cn66xx;
+	struct cvmx_agl_gmx_rxx_decision_s    cn68xx;
+	struct cvmx_agl_gmx_rxx_decision_s    cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_decision cvmx_agl_gmx_rxx_decision_t;
 
@@ -1774,12 +1948,10 @@ typedef union cvmx_agl_gmx_rxx_decision cvmx_agl_gmx_rxx_decision_t;
  *
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rxx_frm_chk
-{
+union cvmx_agl_gmx_rxx_frm_chk {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_frm_chk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_frm_chk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t niberr                       : 1;  /**< Nibble error */
 	uint64_t skperr                       : 1;  /**< Skipper error */
@@ -1805,9 +1977,8 @@ union cvmx_agl_gmx_rxx_frm_chk
 	uint64_t reserved_10_63               : 54;
 #endif
 	} s;
-	struct cvmx_agl_gmx_rxx_frm_chk_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_frm_chk_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t skperr                       : 1;  /**< Skipper error */
 	uint64_t rcverr                       : 1;  /**< Frame was received with MII Data reception error */
@@ -1834,8 +2005,12 @@ union cvmx_agl_gmx_rxx_frm_chk
 	struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1;
 	struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx;
 	struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1;
+	struct cvmx_agl_gmx_rxx_frm_chk_s     cn61xx;
 	struct cvmx_agl_gmx_rxx_frm_chk_s     cn63xx;
 	struct cvmx_agl_gmx_rxx_frm_chk_s     cn63xxp1;
+	struct cvmx_agl_gmx_rxx_frm_chk_s     cn66xx;
+	struct cvmx_agl_gmx_rxx_frm_chk_s     cn68xx;
+	struct cvmx_agl_gmx_rxx_frm_chk_s     cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_frm_chk cvmx_agl_gmx_rxx_frm_chk_t;
 
@@ -1870,12 +2045,10 @@ typedef union cvmx_agl_gmx_rxx_frm_chk cvmx_agl_gmx_rxx_frm_chk_t;
  *
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rxx_frm_ctl
-{
+union cvmx_agl_gmx_rxx_frm_ctl {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_frm_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_frm_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t ptp_mode                     : 1;  /**< Timestamp mode
                                                          When PTP_MODE is set, a 64-bit timestamp will be
@@ -1940,9 +2113,8 @@ union cvmx_agl_gmx_rxx_frm_ctl
 	uint64_t reserved_13_63               : 51;
 #endif
 	} s;
-	struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t pre_align                    : 1;  /**< When set, PREAMBLE parser aligns the the SFD byte
                                                          regardless of the number of previous PREAMBLE
@@ -1990,8 +2162,12 @@ union cvmx_agl_gmx_rxx_frm_ctl
 	struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1;
 	struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx;
 	struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1;
+	struct cvmx_agl_gmx_rxx_frm_ctl_s     cn61xx;
 	struct cvmx_agl_gmx_rxx_frm_ctl_s     cn63xx;
 	struct cvmx_agl_gmx_rxx_frm_ctl_s     cn63xxp1;
+	struct cvmx_agl_gmx_rxx_frm_ctl_s     cn66xx;
+	struct cvmx_agl_gmx_rxx_frm_ctl_s     cn68xx;
+	struct cvmx_agl_gmx_rxx_frm_ctl_s     cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_frm_ctl cvmx_agl_gmx_rxx_frm_ctl_t;
 
@@ -2011,12 +2187,10 @@ typedef union cvmx_agl_gmx_rxx_frm_ctl cvmx_agl_gmx_rxx_frm_ctl_t;
  *
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rxx_frm_max
-{
+union cvmx_agl_gmx_rxx_frm_max {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_frm_max_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_frm_max_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t len                          : 16; /**< Byte count for Max-sized frame check
                                                          AGL_GMX_RXn_FRM_CHK[MAXERR] enables the check
@@ -2035,8 +2209,12 @@ union cvmx_agl_gmx_rxx_frm_max
 	struct cvmx_agl_gmx_rxx_frm_max_s     cn52xxp1;
 	struct cvmx_agl_gmx_rxx_frm_max_s     cn56xx;
 	struct cvmx_agl_gmx_rxx_frm_max_s     cn56xxp1;
+	struct cvmx_agl_gmx_rxx_frm_max_s     cn61xx;
 	struct cvmx_agl_gmx_rxx_frm_max_s     cn63xx;
 	struct cvmx_agl_gmx_rxx_frm_max_s     cn63xxp1;
+	struct cvmx_agl_gmx_rxx_frm_max_s     cn66xx;
+	struct cvmx_agl_gmx_rxx_frm_max_s     cn68xx;
+	struct cvmx_agl_gmx_rxx_frm_max_s     cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_frm_max cvmx_agl_gmx_rxx_frm_max_t;
 
@@ -2050,12 +2228,10 @@ typedef union cvmx_agl_gmx_rxx_frm_max cvmx_agl_gmx_rxx_frm_max_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_rxx_frm_min
-{
+union cvmx_agl_gmx_rxx_frm_min {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_frm_min_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_frm_min_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t len                          : 16; /**< Byte count for Min-sized frame check
                                                          AGL_GMX_RXn_FRM_CHK[MINERR] enables the check
@@ -2073,8 +2249,12 @@ union cvmx_agl_gmx_rxx_frm_min
 	struct cvmx_agl_gmx_rxx_frm_min_s     cn52xxp1;
 	struct cvmx_agl_gmx_rxx_frm_min_s     cn56xx;
 	struct cvmx_agl_gmx_rxx_frm_min_s     cn56xxp1;
+	struct cvmx_agl_gmx_rxx_frm_min_s     cn61xx;
 	struct cvmx_agl_gmx_rxx_frm_min_s     cn63xx;
 	struct cvmx_agl_gmx_rxx_frm_min_s     cn63xxp1;
+	struct cvmx_agl_gmx_rxx_frm_min_s     cn66xx;
+	struct cvmx_agl_gmx_rxx_frm_min_s     cn68xx;
+	struct cvmx_agl_gmx_rxx_frm_min_s     cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_frm_min cvmx_agl_gmx_rxx_frm_min_t;
 
@@ -2088,12 +2268,10 @@ typedef union cvmx_agl_gmx_rxx_frm_min cvmx_agl_gmx_rxx_frm_min_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_rxx_ifg
-{
+union cvmx_agl_gmx_rxx_ifg {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_ifg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_ifg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t ifg                          : 4;  /**< Min IFG (in IFG*8 bits) between packets used to
                                                          determine IFGERR. Normally IFG is 96 bits.
@@ -2111,8 +2289,12 @@ union cvmx_agl_gmx_rxx_ifg
 	struct cvmx_agl_gmx_rxx_ifg_s         cn52xxp1;
 	struct cvmx_agl_gmx_rxx_ifg_s         cn56xx;
 	struct cvmx_agl_gmx_rxx_ifg_s         cn56xxp1;
+	struct cvmx_agl_gmx_rxx_ifg_s         cn61xx;
 	struct cvmx_agl_gmx_rxx_ifg_s         cn63xx;
 	struct cvmx_agl_gmx_rxx_ifg_s         cn63xxp1;
+	struct cvmx_agl_gmx_rxx_ifg_s         cn66xx;
+	struct cvmx_agl_gmx_rxx_ifg_s         cn68xx;
+	struct cvmx_agl_gmx_rxx_ifg_s         cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_ifg cvmx_agl_gmx_rxx_ifg_t;
 
@@ -2126,12 +2308,10 @@ typedef union cvmx_agl_gmx_rxx_ifg cvmx_agl_gmx_rxx_ifg_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_rxx_int_en
-{
+union cvmx_agl_gmx_rxx_int_en {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_int_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
 	uint64_t phy_dupx                     : 1;  /**< Change in the RMGII inbound LinkDuplex             |             NS */
@@ -2177,9 +2357,8 @@ union cvmx_agl_gmx_rxx_int_en
 	uint64_t reserved_20_63               : 44;
 #endif
 	} s;
-	struct cvmx_agl_gmx_rxx_int_en_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_int_en_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
 	uint64_t reserved_16_18               : 3;
@@ -2224,8 +2403,12 @@ union cvmx_agl_gmx_rxx_int_en
 	struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1;
 	struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx;
 	struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1;
+	struct cvmx_agl_gmx_rxx_int_en_s      cn61xx;
 	struct cvmx_agl_gmx_rxx_int_en_s      cn63xx;
 	struct cvmx_agl_gmx_rxx_int_en_s      cn63xxp1;
+	struct cvmx_agl_gmx_rxx_int_en_s      cn66xx;
+	struct cvmx_agl_gmx_rxx_int_en_s      cn68xx;
+	struct cvmx_agl_gmx_rxx_int_en_s      cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_int_en cvmx_agl_gmx_rxx_int_en_t;
 
@@ -2274,7 +2457,7 @@ typedef union cvmx_agl_gmx_rxx_int_en cvmx_agl_gmx_rxx_int_en_t;
  * (B) PCTERR - checks that the frame begins with a valid PREAMBLE sequence.
  *              Does not check the number of PREAMBLE cycles.
  *
- * (C) OVRERR - Not to be included in the HRM
+ * (C) OVRERR -
  *
  *              OVRERR is an architectural assertion check internal to GMX to
  *              make sure no assumption was violated.  In a correctly operating
@@ -2291,12 +2474,10 @@ typedef union cvmx_agl_gmx_rxx_int_en cvmx_agl_gmx_rxx_int_en_t;
  *
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rxx_int_reg
-{
+union cvmx_agl_gmx_rxx_int_reg {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_int_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
 	uint64_t phy_dupx                     : 1;  /**< Change in the RGMII inbound LinkDuplex             |             NS */
@@ -2344,9 +2525,8 @@ union cvmx_agl_gmx_rxx_int_reg
 	uint64_t reserved_20_63               : 44;
 #endif
 	} s;
-	struct cvmx_agl_gmx_rxx_int_reg_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
 	uint64_t reserved_16_18               : 3;
@@ -2393,8 +2573,12 @@ union cvmx_agl_gmx_rxx_int_reg
 	struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1;
 	struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx;
 	struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1;
+	struct cvmx_agl_gmx_rxx_int_reg_s     cn61xx;
 	struct cvmx_agl_gmx_rxx_int_reg_s     cn63xx;
 	struct cvmx_agl_gmx_rxx_int_reg_s     cn63xxp1;
+	struct cvmx_agl_gmx_rxx_int_reg_s     cn66xx;
+	struct cvmx_agl_gmx_rxx_int_reg_s     cn68xx;
+	struct cvmx_agl_gmx_rxx_int_reg_s     cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_int_reg cvmx_agl_gmx_rxx_int_reg_t;
 
@@ -2421,12 +2605,10 @@ typedef union cvmx_agl_gmx_rxx_int_reg cvmx_agl_gmx_rxx_int_reg_t;
  *
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rxx_jabber
-{
+union cvmx_agl_gmx_rxx_jabber {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_jabber_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_jabber_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t cnt                          : 16; /**< Byte count for jabber check
                                                          Failing packets set the JABBER interrupt and are
@@ -2442,8 +2624,12 @@ union cvmx_agl_gmx_rxx_jabber
 	struct cvmx_agl_gmx_rxx_jabber_s      cn52xxp1;
 	struct cvmx_agl_gmx_rxx_jabber_s      cn56xx;
 	struct cvmx_agl_gmx_rxx_jabber_s      cn56xxp1;
+	struct cvmx_agl_gmx_rxx_jabber_s      cn61xx;
 	struct cvmx_agl_gmx_rxx_jabber_s      cn63xx;
 	struct cvmx_agl_gmx_rxx_jabber_s      cn63xxp1;
+	struct cvmx_agl_gmx_rxx_jabber_s      cn66xx;
+	struct cvmx_agl_gmx_rxx_jabber_s      cn68xx;
+	struct cvmx_agl_gmx_rxx_jabber_s      cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_jabber cvmx_agl_gmx_rxx_jabber_t;
 
@@ -2457,12 +2643,10 @@ typedef union cvmx_agl_gmx_rxx_jabber cvmx_agl_gmx_rxx_jabber_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_rxx_pause_drop_time
-{
+union cvmx_agl_gmx_rxx_pause_drop_time {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_pause_drop_time_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_pause_drop_time_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t status                       : 16; /**< Time extracted from the dropped PAUSE packet */
 #else
@@ -2474,8 +2658,12 @@ union cvmx_agl_gmx_rxx_pause_drop_time
 	struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
 	struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
 	struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
+	struct cvmx_agl_gmx_rxx_pause_drop_time_s cn61xx;
 	struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx;
 	struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1;
+	struct cvmx_agl_gmx_rxx_pause_drop_time_s cn66xx;
+	struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xx;
+	struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_pause_drop_time cvmx_agl_gmx_rxx_pause_drop_time_t;
 
@@ -2492,12 +2680,10 @@ typedef union cvmx_agl_gmx_rxx_pause_drop_time cvmx_agl_gmx_rxx_pause_drop_time_
  *
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rxx_rx_inbnd
-{
+union cvmx_agl_gmx_rxx_rx_inbnd {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_rx_inbnd_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_rx_inbnd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t duplex                       : 1;  /**< RGMII Inbound LinkDuplex                           |             NS
                                                          0=half-duplex
@@ -2517,8 +2703,12 @@ union cvmx_agl_gmx_rxx_rx_inbnd
 	uint64_t reserved_4_63                : 60;
 #endif
 	} s;
+	struct cvmx_agl_gmx_rxx_rx_inbnd_s    cn61xx;
 	struct cvmx_agl_gmx_rxx_rx_inbnd_s    cn63xx;
 	struct cvmx_agl_gmx_rxx_rx_inbnd_s    cn63xxp1;
+	struct cvmx_agl_gmx_rxx_rx_inbnd_s    cn66xx;
+	struct cvmx_agl_gmx_rxx_rx_inbnd_s    cn68xx;
+	struct cvmx_agl_gmx_rxx_rx_inbnd_s    cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_rx_inbnd cvmx_agl_gmx_rxx_rx_inbnd_t;
 
@@ -2532,12 +2722,10 @@ typedef union cvmx_agl_gmx_rxx_rx_inbnd cvmx_agl_gmx_rxx_rx_inbnd_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_rxx_stats_ctl
-{
+union cvmx_agl_gmx_rxx_stats_ctl {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_stats_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_stats_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t rd_clr                       : 1;  /**< RX Stats registers will clear on reads */
 #else
@@ -2549,8 +2737,12 @@ union cvmx_agl_gmx_rxx_stats_ctl
 	struct cvmx_agl_gmx_rxx_stats_ctl_s   cn52xxp1;
 	struct cvmx_agl_gmx_rxx_stats_ctl_s   cn56xx;
 	struct cvmx_agl_gmx_rxx_stats_ctl_s   cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_ctl_s   cn61xx;
 	struct cvmx_agl_gmx_rxx_stats_ctl_s   cn63xx;
 	struct cvmx_agl_gmx_rxx_stats_ctl_s   cn63xxp1;
+	struct cvmx_agl_gmx_rxx_stats_ctl_s   cn66xx;
+	struct cvmx_agl_gmx_rxx_stats_ctl_s   cn68xx;
+	struct cvmx_agl_gmx_rxx_stats_ctl_s   cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_stats_ctl cvmx_agl_gmx_rxx_stats_ctl_t;
 
@@ -2562,12 +2754,10 @@ typedef union cvmx_agl_gmx_rxx_stats_ctl cvmx_agl_gmx_rxx_stats_ctl_t;
  * - Counters will wrap
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rxx_stats_octs
-{
+union cvmx_agl_gmx_rxx_stats_octs {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_stats_octs_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_stats_octs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t cnt                          : 48; /**< Octet count of received good packets */
 #else
@@ -2579,8 +2769,12 @@ union cvmx_agl_gmx_rxx_stats_octs
 	struct cvmx_agl_gmx_rxx_stats_octs_s  cn52xxp1;
 	struct cvmx_agl_gmx_rxx_stats_octs_s  cn56xx;
 	struct cvmx_agl_gmx_rxx_stats_octs_s  cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_octs_s  cn61xx;
 	struct cvmx_agl_gmx_rxx_stats_octs_s  cn63xx;
 	struct cvmx_agl_gmx_rxx_stats_octs_s  cn63xxp1;
+	struct cvmx_agl_gmx_rxx_stats_octs_s  cn66xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_s  cn68xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_s  cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_stats_octs cvmx_agl_gmx_rxx_stats_octs_t;
 
@@ -2592,12 +2786,10 @@ typedef union cvmx_agl_gmx_rxx_stats_octs cvmx_agl_gmx_rxx_stats_octs_t;
  * - Counters will wrap
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rxx_stats_octs_ctl
-{
+union cvmx_agl_gmx_rxx_stats_octs_ctl {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_stats_octs_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t cnt                          : 48; /**< Octet count of received pause packets */
 #else
@@ -2609,8 +2801,12 @@ union cvmx_agl_gmx_rxx_stats_octs_ctl
 	struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
 	struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
 	struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn61xx;
 	struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx;
 	struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1;
+	struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn66xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_stats_octs_ctl cvmx_agl_gmx_rxx_stats_octs_ctl_t;
 
@@ -2622,12 +2818,10 @@ typedef union cvmx_agl_gmx_rxx_stats_octs_ctl cvmx_agl_gmx_rxx_stats_octs_ctl_t;
  * - Counters will wrap
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rxx_stats_octs_dmac
-{
+union cvmx_agl_gmx_rxx_stats_octs_dmac {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_stats_octs_dmac_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t cnt                          : 48; /**< Octet count of filtered dmac packets */
 #else
@@ -2639,8 +2833,12 @@ union cvmx_agl_gmx_rxx_stats_octs_dmac
 	struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
 	struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
 	struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn61xx;
 	struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx;
 	struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1;
+	struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn66xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_stats_octs_dmac cvmx_agl_gmx_rxx_stats_octs_dmac_t;
 
@@ -2652,12 +2850,10 @@ typedef union cvmx_agl_gmx_rxx_stats_octs_dmac cvmx_agl_gmx_rxx_stats_octs_dmac_
  * - Counters will wrap
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rxx_stats_octs_drp
-{
+union cvmx_agl_gmx_rxx_stats_octs_drp {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_stats_octs_drp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t cnt                          : 48; /**< Octet count of dropped packets */
 #else
@@ -2669,8 +2865,12 @@ union cvmx_agl_gmx_rxx_stats_octs_drp
 	struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
 	struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
 	struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn61xx;
 	struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx;
 	struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1;
+	struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn66xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_stats_octs_drp cvmx_agl_gmx_rxx_stats_octs_drp_t;
 
@@ -2688,12 +2888,10 @@ typedef union cvmx_agl_gmx_rxx_stats_octs_drp cvmx_agl_gmx_rxx_stats_octs_drp_t;
  * - Counters will wrap
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rxx_stats_pkts
-{
+union cvmx_agl_gmx_rxx_stats_pkts {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_stats_pkts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_stats_pkts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< Count of received good packets */
 #else
@@ -2705,8 +2903,12 @@ union cvmx_agl_gmx_rxx_stats_pkts
 	struct cvmx_agl_gmx_rxx_stats_pkts_s  cn52xxp1;
 	struct cvmx_agl_gmx_rxx_stats_pkts_s  cn56xx;
 	struct cvmx_agl_gmx_rxx_stats_pkts_s  cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_s  cn61xx;
 	struct cvmx_agl_gmx_rxx_stats_pkts_s  cn63xx;
 	struct cvmx_agl_gmx_rxx_stats_pkts_s  cn63xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_s  cn66xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_s  cn68xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_s  cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_stats_pkts cvmx_agl_gmx_rxx_stats_pkts_t;
 
@@ -2723,12 +2925,10 @@ typedef union cvmx_agl_gmx_rxx_stats_pkts cvmx_agl_gmx_rxx_stats_pkts_t;
  * - Counters will wrap
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rxx_stats_pkts_bad
-{
+union cvmx_agl_gmx_rxx_stats_pkts_bad {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_stats_pkts_bad_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< Count of bad packets */
 #else
@@ -2740,8 +2940,12 @@ union cvmx_agl_gmx_rxx_stats_pkts_bad
 	struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
 	struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
 	struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn61xx;
 	struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx;
 	struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn66xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_stats_pkts_bad cvmx_agl_gmx_rxx_stats_pkts_bad_t;
 
@@ -2763,12 +2967,10 @@ typedef union cvmx_agl_gmx_rxx_stats_pkts_bad cvmx_agl_gmx_rxx_stats_pkts_bad_t;
  * - Counters will wrap
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rxx_stats_pkts_ctl
-{
+union cvmx_agl_gmx_rxx_stats_pkts_ctl {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< Count of received pause packets */
 #else
@@ -2780,8 +2982,12 @@ union cvmx_agl_gmx_rxx_stats_pkts_ctl
 	struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
 	struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
 	struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn61xx;
 	struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx;
 	struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn66xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_stats_pkts_ctl cvmx_agl_gmx_rxx_stats_pkts_ctl_t;
 
@@ -2804,12 +3010,10 @@ typedef union cvmx_agl_gmx_rxx_stats_pkts_ctl cvmx_agl_gmx_rxx_stats_pkts_ctl_t;
  * - Counters will wrap
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rxx_stats_pkts_dmac
-{
+union cvmx_agl_gmx_rxx_stats_pkts_dmac {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< Count of filtered dmac packets */
 #else
@@ -2821,8 +3025,12 @@ union cvmx_agl_gmx_rxx_stats_pkts_dmac
 	struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
 	struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
 	struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn61xx;
 	struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx;
 	struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn66xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_stats_pkts_dmac cvmx_agl_gmx_rxx_stats_pkts_dmac_t;
 
@@ -2841,12 +3049,10 @@ typedef union cvmx_agl_gmx_rxx_stats_pkts_dmac cvmx_agl_gmx_rxx_stats_pkts_dmac_
  * - Counters will wrap
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rxx_stats_pkts_drp
-{
+union cvmx_agl_gmx_rxx_stats_pkts_drp {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_stats_pkts_drp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< Count of dropped packets */
 #else
@@ -2858,8 +3064,12 @@ union cvmx_agl_gmx_rxx_stats_pkts_drp
 	struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
 	struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
 	struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn61xx;
 	struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx;
 	struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn66xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_stats_pkts_drp cvmx_agl_gmx_rxx_stats_pkts_drp_t;
 
@@ -2896,12 +3106,10 @@ typedef union cvmx_agl_gmx_rxx_stats_pkts_drp cvmx_agl_gmx_rxx_stats_pkts_drp_t;
  *
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rxx_udd_skp
-{
+union cvmx_agl_gmx_rxx_udd_skp {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rxx_udd_skp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rxx_udd_skp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t fcssel                       : 1;  /**< Include the skip bytes in the FCS calculation
                                                          0 = all skip bytes are included in FCS
@@ -2921,8 +3129,12 @@ union cvmx_agl_gmx_rxx_udd_skp
 	struct cvmx_agl_gmx_rxx_udd_skp_s     cn52xxp1;
 	struct cvmx_agl_gmx_rxx_udd_skp_s     cn56xx;
 	struct cvmx_agl_gmx_rxx_udd_skp_s     cn56xxp1;
+	struct cvmx_agl_gmx_rxx_udd_skp_s     cn61xx;
 	struct cvmx_agl_gmx_rxx_udd_skp_s     cn63xx;
 	struct cvmx_agl_gmx_rxx_udd_skp_s     cn63xxp1;
+	struct cvmx_agl_gmx_rxx_udd_skp_s     cn66xx;
+	struct cvmx_agl_gmx_rxx_udd_skp_s     cn68xx;
+	struct cvmx_agl_gmx_rxx_udd_skp_s     cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rxx_udd_skp cvmx_agl_gmx_rxx_udd_skp_t;
 
@@ -2936,12 +3148,10 @@ typedef union cvmx_agl_gmx_rxx_udd_skp cvmx_agl_gmx_rxx_udd_skp_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_rx_bp_dropx
-{
+union cvmx_agl_gmx_rx_bp_dropx {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rx_bp_dropx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rx_bp_dropx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t mark                         : 6;  /**< Number of 8B ticks to reserve in the RX FIFO.
                                                          When the FIFO exceeds this count, packets will
@@ -2958,8 +3168,12 @@ union cvmx_agl_gmx_rx_bp_dropx
 	struct cvmx_agl_gmx_rx_bp_dropx_s     cn52xxp1;
 	struct cvmx_agl_gmx_rx_bp_dropx_s     cn56xx;
 	struct cvmx_agl_gmx_rx_bp_dropx_s     cn56xxp1;
+	struct cvmx_agl_gmx_rx_bp_dropx_s     cn61xx;
 	struct cvmx_agl_gmx_rx_bp_dropx_s     cn63xx;
 	struct cvmx_agl_gmx_rx_bp_dropx_s     cn63xxp1;
+	struct cvmx_agl_gmx_rx_bp_dropx_s     cn66xx;
+	struct cvmx_agl_gmx_rx_bp_dropx_s     cn68xx;
+	struct cvmx_agl_gmx_rx_bp_dropx_s     cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rx_bp_dropx cvmx_agl_gmx_rx_bp_dropx_t;
 
@@ -2973,12 +3187,10 @@ typedef union cvmx_agl_gmx_rx_bp_dropx cvmx_agl_gmx_rx_bp_dropx_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_rx_bp_offx
-{
+union cvmx_agl_gmx_rx_bp_offx {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rx_bp_offx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rx_bp_offx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t mark                         : 6;  /**< Water mark (8B ticks) to deassert backpressure */
 #else
@@ -2990,8 +3202,12 @@ union cvmx_agl_gmx_rx_bp_offx
 	struct cvmx_agl_gmx_rx_bp_offx_s      cn52xxp1;
 	struct cvmx_agl_gmx_rx_bp_offx_s      cn56xx;
 	struct cvmx_agl_gmx_rx_bp_offx_s      cn56xxp1;
+	struct cvmx_agl_gmx_rx_bp_offx_s      cn61xx;
 	struct cvmx_agl_gmx_rx_bp_offx_s      cn63xx;
 	struct cvmx_agl_gmx_rx_bp_offx_s      cn63xxp1;
+	struct cvmx_agl_gmx_rx_bp_offx_s      cn66xx;
+	struct cvmx_agl_gmx_rx_bp_offx_s      cn68xx;
+	struct cvmx_agl_gmx_rx_bp_offx_s      cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rx_bp_offx cvmx_agl_gmx_rx_bp_offx_t;
 
@@ -3005,12 +3221,10 @@ typedef union cvmx_agl_gmx_rx_bp_offx cvmx_agl_gmx_rx_bp_offx_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_rx_bp_onx
-{
+union cvmx_agl_gmx_rx_bp_onx {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rx_bp_onx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rx_bp_onx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t mark                         : 9;  /**< Hiwater mark (8B ticks) for backpressure. */
 #else
@@ -3022,8 +3236,12 @@ union cvmx_agl_gmx_rx_bp_onx
 	struct cvmx_agl_gmx_rx_bp_onx_s       cn52xxp1;
 	struct cvmx_agl_gmx_rx_bp_onx_s       cn56xx;
 	struct cvmx_agl_gmx_rx_bp_onx_s       cn56xxp1;
+	struct cvmx_agl_gmx_rx_bp_onx_s       cn61xx;
 	struct cvmx_agl_gmx_rx_bp_onx_s       cn63xx;
 	struct cvmx_agl_gmx_rx_bp_onx_s       cn63xxp1;
+	struct cvmx_agl_gmx_rx_bp_onx_s       cn66xx;
+	struct cvmx_agl_gmx_rx_bp_onx_s       cn68xx;
+	struct cvmx_agl_gmx_rx_bp_onx_s       cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rx_bp_onx cvmx_agl_gmx_rx_bp_onx_t;
 
@@ -3037,12 +3255,10 @@ typedef union cvmx_agl_gmx_rx_bp_onx cvmx_agl_gmx_rx_bp_onx_t;
  * COMMIT[0], DROP[0] will be reset when MIX0_CTL[RESET] is set to 1.
  * COMMIT[1], DROP[1] will be reset when MIX1_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rx_prt_info
-{
+union cvmx_agl_gmx_rx_prt_info {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rx_prt_info_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rx_prt_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t drop                         : 2;  /**< Port indication that data was dropped */
 	uint64_t reserved_2_15                : 14;
@@ -3056,9 +3272,8 @@ union cvmx_agl_gmx_rx_prt_info
 	} s;
 	struct cvmx_agl_gmx_rx_prt_info_s     cn52xx;
 	struct cvmx_agl_gmx_rx_prt_info_s     cn52xxp1;
-	struct cvmx_agl_gmx_rx_prt_info_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rx_prt_info_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t drop                         : 1;  /**< Port indication that data was dropped */
 	uint64_t reserved_1_15                : 15;
@@ -3071,8 +3286,12 @@ union cvmx_agl_gmx_rx_prt_info
 #endif
 	} cn56xx;
 	struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
+	struct cvmx_agl_gmx_rx_prt_info_s     cn61xx;
 	struct cvmx_agl_gmx_rx_prt_info_s     cn63xx;
 	struct cvmx_agl_gmx_rx_prt_info_s     cn63xxp1;
+	struct cvmx_agl_gmx_rx_prt_info_s     cn66xx;
+	struct cvmx_agl_gmx_rx_prt_info_s     cn68xx;
+	struct cvmx_agl_gmx_rx_prt_info_s     cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rx_prt_info cvmx_agl_gmx_rx_prt_info_t;
 
@@ -3086,12 +3305,10 @@ typedef union cvmx_agl_gmx_rx_prt_info cvmx_agl_gmx_rx_prt_info_t;
  * RX[0], TX[0] will be reset when MIX0_CTL[RESET] is set to 1.
  * RX[1], TX[1] will be reset when MIX1_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_rx_tx_status
-{
+union cvmx_agl_gmx_rx_tx_status {
 	uint64_t u64;
-	struct cvmx_agl_gmx_rx_tx_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rx_tx_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t tx                           : 2;  /**< Transmit data since last read */
 	uint64_t reserved_2_3                 : 2;
@@ -3105,9 +3322,8 @@ union cvmx_agl_gmx_rx_tx_status
 	} s;
 	struct cvmx_agl_gmx_rx_tx_status_s    cn52xx;
 	struct cvmx_agl_gmx_rx_tx_status_s    cn52xxp1;
-	struct cvmx_agl_gmx_rx_tx_status_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_rx_tx_status_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t tx                           : 1;  /**< Transmit data since last read */
 	uint64_t reserved_1_3                 : 3;
@@ -3120,8 +3336,12 @@ union cvmx_agl_gmx_rx_tx_status
 #endif
 	} cn56xx;
 	struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
+	struct cvmx_agl_gmx_rx_tx_status_s    cn61xx;
 	struct cvmx_agl_gmx_rx_tx_status_s    cn63xx;
 	struct cvmx_agl_gmx_rx_tx_status_s    cn63xxp1;
+	struct cvmx_agl_gmx_rx_tx_status_s    cn66xx;
+	struct cvmx_agl_gmx_rx_tx_status_s    cn68xx;
+	struct cvmx_agl_gmx_rx_tx_status_s    cn68xxp1;
 };
 typedef union cvmx_agl_gmx_rx_tx_status cvmx_agl_gmx_rx_tx_status_t;
 
@@ -3135,12 +3355,10 @@ typedef union cvmx_agl_gmx_rx_tx_status cvmx_agl_gmx_rx_tx_status_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_smacx
-{
+union cvmx_agl_gmx_smacx {
 	uint64_t u64;
-	struct cvmx_agl_gmx_smacx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_smacx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t smac                         : 48; /**< The SMAC field is used for generating and
                                                          accepting Control Pause packets */
@@ -3153,8 +3371,12 @@ union cvmx_agl_gmx_smacx
 	struct cvmx_agl_gmx_smacx_s           cn52xxp1;
 	struct cvmx_agl_gmx_smacx_s           cn56xx;
 	struct cvmx_agl_gmx_smacx_s           cn56xxp1;
+	struct cvmx_agl_gmx_smacx_s           cn61xx;
 	struct cvmx_agl_gmx_smacx_s           cn63xx;
 	struct cvmx_agl_gmx_smacx_s           cn63xxp1;
+	struct cvmx_agl_gmx_smacx_s           cn66xx;
+	struct cvmx_agl_gmx_smacx_s           cn68xx;
+	struct cvmx_agl_gmx_smacx_s           cn68xxp1;
 };
 typedef union cvmx_agl_gmx_smacx cvmx_agl_gmx_smacx_t;
 
@@ -3167,15 +3389,34 @@ typedef union cvmx_agl_gmx_smacx cvmx_agl_gmx_smacx_t;
  * Notes:
  * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
  *
+ *
+ *
+ * It has no relationship with the TX FIFO per se.  The TX engine sends packets
+ * from PKO and upon completion, sends a command to the TX stats block for an
+ * update based on the packet size.  The stats operation can take a few cycles -
+ * normally not enough to be visible considering the 64B min packet size that is
+ * ethernet convention.
+ *
+ * In the rare case in which SW attempted to schedule really, really, small packets
+ * or the sclk (6xxx) is running ass-slow, then the stats updates may not happen in
+ * real time and can back up the TX engine.
+ *
+ * This counter is the number of cycles in which the TX engine was stalled.  In
+ * normal operation, it should always be zeros.
  */
-union cvmx_agl_gmx_stat_bp
-{
+union cvmx_agl_gmx_stat_bp {
 	uint64_t u64;
-	struct cvmx_agl_gmx_stat_bp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_stat_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
-	uint64_t bp                           : 1;  /**< Current BP state */
+	uint64_t bp                           : 1;  /**< Current TX stats BP state
+                                                         When the TX stats machine cannot update the stats
+                                                         registers quickly enough, the machine has the
+                                                         ability to BP TX datapath.  This is a rare event
+                                                         and will not occur in normal operation.
+                                                         0 = no backpressure is applied
+                                                         1 = backpressure is applied to TX datapath to
+                                                             allow stat update operations to complete */
 	uint64_t cnt                          : 16; /**< Number of cycles that BP has been asserted
                                                          Saturating counter */
 #else
@@ -3188,8 +3429,12 @@ union cvmx_agl_gmx_stat_bp
 	struct cvmx_agl_gmx_stat_bp_s         cn52xxp1;
 	struct cvmx_agl_gmx_stat_bp_s         cn56xx;
 	struct cvmx_agl_gmx_stat_bp_s         cn56xxp1;
+	struct cvmx_agl_gmx_stat_bp_s         cn61xx;
 	struct cvmx_agl_gmx_stat_bp_s         cn63xx;
 	struct cvmx_agl_gmx_stat_bp_s         cn63xxp1;
+	struct cvmx_agl_gmx_stat_bp_s         cn66xx;
+	struct cvmx_agl_gmx_stat_bp_s         cn68xx;
+	struct cvmx_agl_gmx_stat_bp_s         cn68xxp1;
 };
 typedef union cvmx_agl_gmx_stat_bp cvmx_agl_gmx_stat_bp_t;
 
@@ -3203,12 +3448,10 @@ typedef union cvmx_agl_gmx_stat_bp cvmx_agl_gmx_stat_bp_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_txx_append
-{
+union cvmx_agl_gmx_txx_append {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_append_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_append_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t force_fcs                    : 1;  /**< Append the Ethernet FCS on each pause packet
                                                          when FCS is clear.  Pause packets are normally
@@ -3230,8 +3473,12 @@ union cvmx_agl_gmx_txx_append
 	struct cvmx_agl_gmx_txx_append_s      cn52xxp1;
 	struct cvmx_agl_gmx_txx_append_s      cn56xx;
 	struct cvmx_agl_gmx_txx_append_s      cn56xxp1;
+	struct cvmx_agl_gmx_txx_append_s      cn61xx;
 	struct cvmx_agl_gmx_txx_append_s      cn63xx;
 	struct cvmx_agl_gmx_txx_append_s      cn63xxp1;
+	struct cvmx_agl_gmx_txx_append_s      cn66xx;
+	struct cvmx_agl_gmx_txx_append_s      cn68xx;
+	struct cvmx_agl_gmx_txx_append_s      cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_append cvmx_agl_gmx_txx_append_t;
 
@@ -3255,12 +3502,10 @@ typedef union cvmx_agl_gmx_txx_append cvmx_agl_gmx_txx_append_t;
  *
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_txx_clk
-{
+union cvmx_agl_gmx_txx_clk {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_clk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_clk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t clk_cnt                      : 6;  /**< Controls the RGMII TXC frequency                   |             NS
                                                          TXC(period) =
@@ -3270,8 +3515,12 @@ union cvmx_agl_gmx_txx_clk
 	uint64_t reserved_6_63                : 58;
 #endif
 	} s;
+	struct cvmx_agl_gmx_txx_clk_s         cn61xx;
 	struct cvmx_agl_gmx_txx_clk_s         cn63xx;
 	struct cvmx_agl_gmx_txx_clk_s         cn63xxp1;
+	struct cvmx_agl_gmx_txx_clk_s         cn66xx;
+	struct cvmx_agl_gmx_txx_clk_s         cn68xx;
+	struct cvmx_agl_gmx_txx_clk_s         cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_clk cvmx_agl_gmx_txx_clk_t;
 
@@ -3285,12 +3534,10 @@ typedef union cvmx_agl_gmx_txx_clk cvmx_agl_gmx_txx_clk_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_txx_ctl
-{
+union cvmx_agl_gmx_txx_ctl {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t xsdef_en                     : 1;  /**< Enables the excessive deferral check for stats
                                                          and interrupts */
@@ -3306,8 +3553,12 @@ union cvmx_agl_gmx_txx_ctl
 	struct cvmx_agl_gmx_txx_ctl_s         cn52xxp1;
 	struct cvmx_agl_gmx_txx_ctl_s         cn56xx;
 	struct cvmx_agl_gmx_txx_ctl_s         cn56xxp1;
+	struct cvmx_agl_gmx_txx_ctl_s         cn61xx;
 	struct cvmx_agl_gmx_txx_ctl_s         cn63xx;
 	struct cvmx_agl_gmx_txx_ctl_s         cn63xxp1;
+	struct cvmx_agl_gmx_txx_ctl_s         cn66xx;
+	struct cvmx_agl_gmx_txx_ctl_s         cn68xx;
+	struct cvmx_agl_gmx_txx_ctl_s         cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_ctl cvmx_agl_gmx_txx_ctl_t;
 
@@ -3321,12 +3572,10 @@ typedef union cvmx_agl_gmx_txx_ctl cvmx_agl_gmx_txx_ctl_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_txx_min_pkt
-{
+union cvmx_agl_gmx_txx_min_pkt {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_min_pkt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_min_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t min_size                     : 8;  /**< Min frame in bytes before the FCS is applied
                                                          Padding is only appened when
@@ -3342,8 +3591,12 @@ union cvmx_agl_gmx_txx_min_pkt
 	struct cvmx_agl_gmx_txx_min_pkt_s     cn52xxp1;
 	struct cvmx_agl_gmx_txx_min_pkt_s     cn56xx;
 	struct cvmx_agl_gmx_txx_min_pkt_s     cn56xxp1;
+	struct cvmx_agl_gmx_txx_min_pkt_s     cn61xx;
 	struct cvmx_agl_gmx_txx_min_pkt_s     cn63xx;
 	struct cvmx_agl_gmx_txx_min_pkt_s     cn63xxp1;
+	struct cvmx_agl_gmx_txx_min_pkt_s     cn66xx;
+	struct cvmx_agl_gmx_txx_min_pkt_s     cn68xx;
+	struct cvmx_agl_gmx_txx_min_pkt_s     cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_min_pkt cvmx_agl_gmx_txx_min_pkt_t;
 
@@ -3374,12 +3627,10 @@ typedef union cvmx_agl_gmx_txx_min_pkt cvmx_agl_gmx_txx_min_pkt_t;
  *
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_txx_pause_pkt_interval
-{
+union cvmx_agl_gmx_txx_pause_pkt_interval {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_pause_pkt_interval_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t interval                     : 16; /**< Arbitrate for a pause packet every (INTERVAL*512)
                                                          bit-times.
@@ -3395,8 +3646,12 @@ union cvmx_agl_gmx_txx_pause_pkt_interval
 	struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
 	struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
 	struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
+	struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn61xx;
 	struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx;
 	struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1;
+	struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn66xx;
+	struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xx;
+	struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_pause_pkt_interval cvmx_agl_gmx_txx_pause_pkt_interval_t;
 
@@ -3427,12 +3682,10 @@ typedef union cvmx_agl_gmx_txx_pause_pkt_interval cvmx_agl_gmx_txx_pause_pkt_int
  *
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_txx_pause_pkt_time
-{
+union cvmx_agl_gmx_txx_pause_pkt_time {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_pause_pkt_time_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_pause_pkt_time_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t time                         : 16; /**< The pause_time field placed is outbnd pause pkts
                                                          pause_time is in 512 bit-times
@@ -3446,8 +3699,12 @@ union cvmx_agl_gmx_txx_pause_pkt_time
 	struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
 	struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
 	struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
+	struct cvmx_agl_gmx_txx_pause_pkt_time_s cn61xx;
 	struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx;
 	struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1;
+	struct cvmx_agl_gmx_txx_pause_pkt_time_s cn66xx;
+	struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xx;
+	struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_pause_pkt_time cvmx_agl_gmx_txx_pause_pkt_time_t;
 
@@ -3461,12 +3718,10 @@ typedef union cvmx_agl_gmx_txx_pause_pkt_time cvmx_agl_gmx_txx_pause_pkt_time_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_txx_pause_togo
-{
+union cvmx_agl_gmx_txx_pause_togo {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_pause_togo_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_pause_togo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t time                         : 16; /**< Amount of time remaining to backpressure */
 #else
@@ -3478,8 +3733,12 @@ union cvmx_agl_gmx_txx_pause_togo
 	struct cvmx_agl_gmx_txx_pause_togo_s  cn52xxp1;
 	struct cvmx_agl_gmx_txx_pause_togo_s  cn56xx;
 	struct cvmx_agl_gmx_txx_pause_togo_s  cn56xxp1;
+	struct cvmx_agl_gmx_txx_pause_togo_s  cn61xx;
 	struct cvmx_agl_gmx_txx_pause_togo_s  cn63xx;
 	struct cvmx_agl_gmx_txx_pause_togo_s  cn63xxp1;
+	struct cvmx_agl_gmx_txx_pause_togo_s  cn66xx;
+	struct cvmx_agl_gmx_txx_pause_togo_s  cn68xx;
+	struct cvmx_agl_gmx_txx_pause_togo_s  cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_pause_togo cvmx_agl_gmx_txx_pause_togo_t;
 
@@ -3493,12 +3752,10 @@ typedef union cvmx_agl_gmx_txx_pause_togo cvmx_agl_gmx_txx_pause_togo_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_txx_pause_zero
-{
+union cvmx_agl_gmx_txx_pause_zero {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_pause_zero_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_pause_zero_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t send                         : 1;  /**< When backpressure condition clear, send PAUSE
                                                          packet with pause_time of zero to enable the
@@ -3512,8 +3769,12 @@ union cvmx_agl_gmx_txx_pause_zero
 	struct cvmx_agl_gmx_txx_pause_zero_s  cn52xxp1;
 	struct cvmx_agl_gmx_txx_pause_zero_s  cn56xx;
 	struct cvmx_agl_gmx_txx_pause_zero_s  cn56xxp1;
+	struct cvmx_agl_gmx_txx_pause_zero_s  cn61xx;
 	struct cvmx_agl_gmx_txx_pause_zero_s  cn63xx;
 	struct cvmx_agl_gmx_txx_pause_zero_s  cn63xxp1;
+	struct cvmx_agl_gmx_txx_pause_zero_s  cn66xx;
+	struct cvmx_agl_gmx_txx_pause_zero_s  cn68xx;
+	struct cvmx_agl_gmx_txx_pause_zero_s  cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_pause_zero cvmx_agl_gmx_txx_pause_zero_t;
 
@@ -3527,12 +3788,10 @@ typedef union cvmx_agl_gmx_txx_pause_zero cvmx_agl_gmx_txx_pause_zero_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_txx_soft_pause
-{
+union cvmx_agl_gmx_txx_soft_pause {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_soft_pause_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_soft_pause_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t time                         : 16; /**< Back off the TX bus for (TIME*512) bit-times
                                                          for full-duplex operation only */
@@ -3545,8 +3804,12 @@ union cvmx_agl_gmx_txx_soft_pause
 	struct cvmx_agl_gmx_txx_soft_pause_s  cn52xxp1;
 	struct cvmx_agl_gmx_txx_soft_pause_s  cn56xx;
 	struct cvmx_agl_gmx_txx_soft_pause_s  cn56xxp1;
+	struct cvmx_agl_gmx_txx_soft_pause_s  cn61xx;
 	struct cvmx_agl_gmx_txx_soft_pause_s  cn63xx;
 	struct cvmx_agl_gmx_txx_soft_pause_s  cn63xxp1;
+	struct cvmx_agl_gmx_txx_soft_pause_s  cn66xx;
+	struct cvmx_agl_gmx_txx_soft_pause_s  cn68xx;
+	struct cvmx_agl_gmx_txx_soft_pause_s  cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_soft_pause cvmx_agl_gmx_txx_soft_pause_t;
 
@@ -3561,12 +3824,10 @@ typedef union cvmx_agl_gmx_txx_soft_pause cvmx_agl_gmx_txx_soft_pause_t;
  * - Counters will wrap
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_txx_stat0
-{
+union cvmx_agl_gmx_txx_stat0 {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_stat0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_stat0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t xsdef                        : 32; /**< Number of packets dropped (never successfully
                                                          sent) due to excessive deferal */
 	uint64_t xscol                        : 32; /**< Number of packets dropped (never successfully
@@ -3581,8 +3842,12 @@ union cvmx_agl_gmx_txx_stat0
 	struct cvmx_agl_gmx_txx_stat0_s       cn52xxp1;
 	struct cvmx_agl_gmx_txx_stat0_s       cn56xx;
 	struct cvmx_agl_gmx_txx_stat0_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat0_s       cn61xx;
 	struct cvmx_agl_gmx_txx_stat0_s       cn63xx;
 	struct cvmx_agl_gmx_txx_stat0_s       cn63xxp1;
+	struct cvmx_agl_gmx_txx_stat0_s       cn66xx;
+	struct cvmx_agl_gmx_txx_stat0_s       cn68xx;
+	struct cvmx_agl_gmx_txx_stat0_s       cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_stat0 cvmx_agl_gmx_txx_stat0_t;
 
@@ -3597,12 +3862,10 @@ typedef union cvmx_agl_gmx_txx_stat0 cvmx_agl_gmx_txx_stat0_t;
  * - Counters will wrap
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_txx_stat1
-{
+union cvmx_agl_gmx_txx_stat1 {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_stat1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_stat1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t scol                         : 32; /**< Number of packets sent with a single collision */
 	uint64_t mcol                         : 32; /**< Number of packets sent with multiple collisions
                                                          but < AGL_GMX_TX_COL_ATTEMPT[LIMIT]. */
@@ -3615,8 +3878,12 @@ union cvmx_agl_gmx_txx_stat1
 	struct cvmx_agl_gmx_txx_stat1_s       cn52xxp1;
 	struct cvmx_agl_gmx_txx_stat1_s       cn56xx;
 	struct cvmx_agl_gmx_txx_stat1_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat1_s       cn61xx;
 	struct cvmx_agl_gmx_txx_stat1_s       cn63xx;
 	struct cvmx_agl_gmx_txx_stat1_s       cn63xxp1;
+	struct cvmx_agl_gmx_txx_stat1_s       cn66xx;
+	struct cvmx_agl_gmx_txx_stat1_s       cn68xx;
+	struct cvmx_agl_gmx_txx_stat1_s       cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_stat1 cvmx_agl_gmx_txx_stat1_t;
 
@@ -3634,12 +3901,10 @@ typedef union cvmx_agl_gmx_txx_stat1 cvmx_agl_gmx_txx_stat1_t;
  * - Counters will wrap
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_txx_stat2
-{
+union cvmx_agl_gmx_txx_stat2 {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_stat2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_stat2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t octs                         : 48; /**< Number of total octets sent on the interface.
                                                          Does not count octets from frames that were
@@ -3653,8 +3918,12 @@ union cvmx_agl_gmx_txx_stat2
 	struct cvmx_agl_gmx_txx_stat2_s       cn52xxp1;
 	struct cvmx_agl_gmx_txx_stat2_s       cn56xx;
 	struct cvmx_agl_gmx_txx_stat2_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat2_s       cn61xx;
 	struct cvmx_agl_gmx_txx_stat2_s       cn63xx;
 	struct cvmx_agl_gmx_txx_stat2_s       cn63xxp1;
+	struct cvmx_agl_gmx_txx_stat2_s       cn66xx;
+	struct cvmx_agl_gmx_txx_stat2_s       cn68xx;
+	struct cvmx_agl_gmx_txx_stat2_s       cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_stat2 cvmx_agl_gmx_txx_stat2_t;
 
@@ -3669,12 +3938,10 @@ typedef union cvmx_agl_gmx_txx_stat2 cvmx_agl_gmx_txx_stat2_t;
  * - Counters will wrap
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_txx_stat3
-{
+union cvmx_agl_gmx_txx_stat3 {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_stat3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_stat3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t pkts                         : 32; /**< Number of total frames sent on the interface.
                                                          Does not count frames that were truncated due to
@@ -3688,8 +3955,12 @@ union cvmx_agl_gmx_txx_stat3
 	struct cvmx_agl_gmx_txx_stat3_s       cn52xxp1;
 	struct cvmx_agl_gmx_txx_stat3_s       cn56xx;
 	struct cvmx_agl_gmx_txx_stat3_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat3_s       cn61xx;
 	struct cvmx_agl_gmx_txx_stat3_s       cn63xx;
 	struct cvmx_agl_gmx_txx_stat3_s       cn63xxp1;
+	struct cvmx_agl_gmx_txx_stat3_s       cn66xx;
+	struct cvmx_agl_gmx_txx_stat3_s       cn68xx;
+	struct cvmx_agl_gmx_txx_stat3_s       cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_stat3 cvmx_agl_gmx_txx_stat3_t;
 
@@ -3707,12 +3978,10 @@ typedef union cvmx_agl_gmx_txx_stat3 cvmx_agl_gmx_txx_stat3_t;
  * - Counters will wrap
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_txx_stat4
-{
+union cvmx_agl_gmx_txx_stat4 {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_stat4_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_stat4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t hist1                        : 32; /**< Number of packets sent with an octet count of 64. */
 	uint64_t hist0                        : 32; /**< Number of packets sent with an octet count
                                                          of < 64. */
@@ -3725,8 +3994,12 @@ union cvmx_agl_gmx_txx_stat4
 	struct cvmx_agl_gmx_txx_stat4_s       cn52xxp1;
 	struct cvmx_agl_gmx_txx_stat4_s       cn56xx;
 	struct cvmx_agl_gmx_txx_stat4_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat4_s       cn61xx;
 	struct cvmx_agl_gmx_txx_stat4_s       cn63xx;
 	struct cvmx_agl_gmx_txx_stat4_s       cn63xxp1;
+	struct cvmx_agl_gmx_txx_stat4_s       cn66xx;
+	struct cvmx_agl_gmx_txx_stat4_s       cn68xx;
+	struct cvmx_agl_gmx_txx_stat4_s       cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_stat4 cvmx_agl_gmx_txx_stat4_t;
 
@@ -3744,12 +4017,10 @@ typedef union cvmx_agl_gmx_txx_stat4 cvmx_agl_gmx_txx_stat4_t;
  * - Counters will wrap
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_txx_stat5
-{
+union cvmx_agl_gmx_txx_stat5 {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_stat5_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_stat5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t hist3                        : 32; /**< Number of packets sent with an octet count of
                                                          128 - 255. */
 	uint64_t hist2                        : 32; /**< Number of packets sent with an octet count of
@@ -3763,8 +4034,12 @@ union cvmx_agl_gmx_txx_stat5
 	struct cvmx_agl_gmx_txx_stat5_s       cn52xxp1;
 	struct cvmx_agl_gmx_txx_stat5_s       cn56xx;
 	struct cvmx_agl_gmx_txx_stat5_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat5_s       cn61xx;
 	struct cvmx_agl_gmx_txx_stat5_s       cn63xx;
 	struct cvmx_agl_gmx_txx_stat5_s       cn63xxp1;
+	struct cvmx_agl_gmx_txx_stat5_s       cn66xx;
+	struct cvmx_agl_gmx_txx_stat5_s       cn68xx;
+	struct cvmx_agl_gmx_txx_stat5_s       cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_stat5 cvmx_agl_gmx_txx_stat5_t;
 
@@ -3782,12 +4057,10 @@ typedef union cvmx_agl_gmx_txx_stat5 cvmx_agl_gmx_txx_stat5_t;
  * - Counters will wrap
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_txx_stat6
-{
+union cvmx_agl_gmx_txx_stat6 {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_stat6_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_stat6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t hist5                        : 32; /**< Number of packets sent with an octet count of
                                                          512 - 1023. */
 	uint64_t hist4                        : 32; /**< Number of packets sent with an octet count of
@@ -3801,8 +4074,12 @@ union cvmx_agl_gmx_txx_stat6
 	struct cvmx_agl_gmx_txx_stat6_s       cn52xxp1;
 	struct cvmx_agl_gmx_txx_stat6_s       cn56xx;
 	struct cvmx_agl_gmx_txx_stat6_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat6_s       cn61xx;
 	struct cvmx_agl_gmx_txx_stat6_s       cn63xx;
 	struct cvmx_agl_gmx_txx_stat6_s       cn63xxp1;
+	struct cvmx_agl_gmx_txx_stat6_s       cn66xx;
+	struct cvmx_agl_gmx_txx_stat6_s       cn68xx;
+	struct cvmx_agl_gmx_txx_stat6_s       cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_stat6 cvmx_agl_gmx_txx_stat6_t;
 
@@ -3820,12 +4097,10 @@ typedef union cvmx_agl_gmx_txx_stat6 cvmx_agl_gmx_txx_stat6_t;
  * - Counters will wrap
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_txx_stat7
-{
+union cvmx_agl_gmx_txx_stat7 {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_stat7_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_stat7_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t hist7                        : 32; /**< Number of packets sent with an octet count
                                                          of > 1518. */
 	uint64_t hist6                        : 32; /**< Number of packets sent with an octet count of
@@ -3839,8 +4114,12 @@ union cvmx_agl_gmx_txx_stat7
 	struct cvmx_agl_gmx_txx_stat7_s       cn52xxp1;
 	struct cvmx_agl_gmx_txx_stat7_s       cn56xx;
 	struct cvmx_agl_gmx_txx_stat7_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat7_s       cn61xx;
 	struct cvmx_agl_gmx_txx_stat7_s       cn63xx;
 	struct cvmx_agl_gmx_txx_stat7_s       cn63xxp1;
+	struct cvmx_agl_gmx_txx_stat7_s       cn66xx;
+	struct cvmx_agl_gmx_txx_stat7_s       cn68xx;
+	struct cvmx_agl_gmx_txx_stat7_s       cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_stat7 cvmx_agl_gmx_txx_stat7_t;
 
@@ -3860,12 +4139,10 @@ typedef union cvmx_agl_gmx_txx_stat7 cvmx_agl_gmx_txx_stat7_t;
  *   reality and should be ignored by software.
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_txx_stat8
-{
+union cvmx_agl_gmx_txx_stat8 {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_stat8_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_stat8_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t mcst                         : 32; /**< Number of packets sent to multicast DMAC.
                                                          Does not include BCST packets. */
 	uint64_t bcst                         : 32; /**< Number of packets sent to broadcast DMAC.
@@ -3879,8 +4156,12 @@ union cvmx_agl_gmx_txx_stat8
 	struct cvmx_agl_gmx_txx_stat8_s       cn52xxp1;
 	struct cvmx_agl_gmx_txx_stat8_s       cn56xx;
 	struct cvmx_agl_gmx_txx_stat8_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat8_s       cn61xx;
 	struct cvmx_agl_gmx_txx_stat8_s       cn63xx;
 	struct cvmx_agl_gmx_txx_stat8_s       cn63xxp1;
+	struct cvmx_agl_gmx_txx_stat8_s       cn66xx;
+	struct cvmx_agl_gmx_txx_stat8_s       cn68xx;
+	struct cvmx_agl_gmx_txx_stat8_s       cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_stat8 cvmx_agl_gmx_txx_stat8_t;
 
@@ -3895,12 +4176,10 @@ typedef union cvmx_agl_gmx_txx_stat8 cvmx_agl_gmx_txx_stat8_t;
  * - Counters will wrap
  * - Not reset when MIX*_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_txx_stat9
-{
+union cvmx_agl_gmx_txx_stat9 {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_stat9_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_stat9_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t undflw                       : 32; /**< Number of underflow packets */
 	uint64_t ctl                          : 32; /**< Number of Control packets (PAUSE flow control)
                                                          generated by GMX.  It does not include control
@@ -3914,8 +4193,12 @@ union cvmx_agl_gmx_txx_stat9
 	struct cvmx_agl_gmx_txx_stat9_s       cn52xxp1;
 	struct cvmx_agl_gmx_txx_stat9_s       cn56xx;
 	struct cvmx_agl_gmx_txx_stat9_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat9_s       cn61xx;
 	struct cvmx_agl_gmx_txx_stat9_s       cn63xx;
 	struct cvmx_agl_gmx_txx_stat9_s       cn63xxp1;
+	struct cvmx_agl_gmx_txx_stat9_s       cn66xx;
+	struct cvmx_agl_gmx_txx_stat9_s       cn68xx;
+	struct cvmx_agl_gmx_txx_stat9_s       cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_stat9 cvmx_agl_gmx_txx_stat9_t;
 
@@ -3929,12 +4212,10 @@ typedef union cvmx_agl_gmx_txx_stat9 cvmx_agl_gmx_txx_stat9_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_txx_stats_ctl
-{
+union cvmx_agl_gmx_txx_stats_ctl {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_stats_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_stats_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t rd_clr                       : 1;  /**< Stats registers will clear on reads */
 #else
@@ -3946,8 +4227,12 @@ union cvmx_agl_gmx_txx_stats_ctl
 	struct cvmx_agl_gmx_txx_stats_ctl_s   cn52xxp1;
 	struct cvmx_agl_gmx_txx_stats_ctl_s   cn56xx;
 	struct cvmx_agl_gmx_txx_stats_ctl_s   cn56xxp1;
+	struct cvmx_agl_gmx_txx_stats_ctl_s   cn61xx;
 	struct cvmx_agl_gmx_txx_stats_ctl_s   cn63xx;
 	struct cvmx_agl_gmx_txx_stats_ctl_s   cn63xxp1;
+	struct cvmx_agl_gmx_txx_stats_ctl_s   cn66xx;
+	struct cvmx_agl_gmx_txx_stats_ctl_s   cn68xx;
+	struct cvmx_agl_gmx_txx_stats_ctl_s   cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_stats_ctl cvmx_agl_gmx_txx_stats_ctl_t;
 
@@ -3961,12 +4246,10 @@ typedef union cvmx_agl_gmx_txx_stats_ctl cvmx_agl_gmx_txx_stats_ctl_t;
  * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
  *
  */
-union cvmx_agl_gmx_txx_thresh
-{
+union cvmx_agl_gmx_txx_thresh {
 	uint64_t u64;
-	struct cvmx_agl_gmx_txx_thresh_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_txx_thresh_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t cnt                          : 6;  /**< Number of 16B ticks to accumulate in the TX FIFO
                                                          before sending on the packet interface
@@ -3983,8 +4266,12 @@ union cvmx_agl_gmx_txx_thresh
 	struct cvmx_agl_gmx_txx_thresh_s      cn52xxp1;
 	struct cvmx_agl_gmx_txx_thresh_s      cn56xx;
 	struct cvmx_agl_gmx_txx_thresh_s      cn56xxp1;
+	struct cvmx_agl_gmx_txx_thresh_s      cn61xx;
 	struct cvmx_agl_gmx_txx_thresh_s      cn63xx;
 	struct cvmx_agl_gmx_txx_thresh_s      cn63xxp1;
+	struct cvmx_agl_gmx_txx_thresh_s      cn66xx;
+	struct cvmx_agl_gmx_txx_thresh_s      cn68xx;
+	struct cvmx_agl_gmx_txx_thresh_s      cn68xxp1;
 };
 typedef union cvmx_agl_gmx_txx_thresh cvmx_agl_gmx_txx_thresh_t;
 
@@ -3998,12 +4285,10 @@ typedef union cvmx_agl_gmx_txx_thresh cvmx_agl_gmx_txx_thresh_t;
  * BP[0] will be reset when MIX0_CTL[RESET] is set to 1.
  * BP[1] will be reset when MIX1_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_tx_bp
-{
+union cvmx_agl_gmx_tx_bp {
 	uint64_t u64;
-	struct cvmx_agl_gmx_tx_bp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_tx_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t bp                           : 2;  /**< Port BackPressure status
                                                          0=Port is available
@@ -4015,9 +4300,8 @@ union cvmx_agl_gmx_tx_bp
 	} s;
 	struct cvmx_agl_gmx_tx_bp_s           cn52xx;
 	struct cvmx_agl_gmx_tx_bp_s           cn52xxp1;
-	struct cvmx_agl_gmx_tx_bp_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_tx_bp_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t bp                           : 1;  /**< Port BackPressure status
                                                          0=Port is available
@@ -4028,8 +4312,12 @@ union cvmx_agl_gmx_tx_bp
 #endif
 	} cn56xx;
 	struct cvmx_agl_gmx_tx_bp_cn56xx      cn56xxp1;
+	struct cvmx_agl_gmx_tx_bp_s           cn61xx;
 	struct cvmx_agl_gmx_tx_bp_s           cn63xx;
 	struct cvmx_agl_gmx_tx_bp_s           cn63xxp1;
+	struct cvmx_agl_gmx_tx_bp_s           cn66xx;
+	struct cvmx_agl_gmx_tx_bp_s           cn68xx;
+	struct cvmx_agl_gmx_tx_bp_s           cn68xxp1;
 };
 typedef union cvmx_agl_gmx_tx_bp cvmx_agl_gmx_tx_bp_t;
 
@@ -4043,12 +4331,10 @@ typedef union cvmx_agl_gmx_tx_bp cvmx_agl_gmx_tx_bp_t;
  * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
  *
  */
-union cvmx_agl_gmx_tx_col_attempt
-{
+union cvmx_agl_gmx_tx_col_attempt {
 	uint64_t u64;
-	struct cvmx_agl_gmx_tx_col_attempt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_tx_col_attempt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t limit                        : 5;  /**< Collision Attempts */
 #else
@@ -4060,8 +4346,12 @@ union cvmx_agl_gmx_tx_col_attempt
 	struct cvmx_agl_gmx_tx_col_attempt_s  cn52xxp1;
 	struct cvmx_agl_gmx_tx_col_attempt_s  cn56xx;
 	struct cvmx_agl_gmx_tx_col_attempt_s  cn56xxp1;
+	struct cvmx_agl_gmx_tx_col_attempt_s  cn61xx;
 	struct cvmx_agl_gmx_tx_col_attempt_s  cn63xx;
 	struct cvmx_agl_gmx_tx_col_attempt_s  cn63xxp1;
+	struct cvmx_agl_gmx_tx_col_attempt_s  cn66xx;
+	struct cvmx_agl_gmx_tx_col_attempt_s  cn68xx;
+	struct cvmx_agl_gmx_tx_col_attempt_s  cn68xxp1;
 };
 typedef union cvmx_agl_gmx_tx_col_attempt cvmx_agl_gmx_tx_col_attempt_t;
 
@@ -4090,12 +4380,10 @@ typedef union cvmx_agl_gmx_tx_col_attempt cvmx_agl_gmx_tx_col_attempt_t;
  *
  * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
  */
-union cvmx_agl_gmx_tx_ifg
-{
+union cvmx_agl_gmx_tx_ifg {
 	uint64_t u64;
-	struct cvmx_agl_gmx_tx_ifg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_tx_ifg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t ifg2                         : 4;  /**< 1/3 of the interframe gap timing
                                                          If CRS is detected during IFG2, then the
@@ -4115,8 +4403,12 @@ union cvmx_agl_gmx_tx_ifg
 	struct cvmx_agl_gmx_tx_ifg_s          cn52xxp1;
 	struct cvmx_agl_gmx_tx_ifg_s          cn56xx;
 	struct cvmx_agl_gmx_tx_ifg_s          cn56xxp1;
+	struct cvmx_agl_gmx_tx_ifg_s          cn61xx;
 	struct cvmx_agl_gmx_tx_ifg_s          cn63xx;
 	struct cvmx_agl_gmx_tx_ifg_s          cn63xxp1;
+	struct cvmx_agl_gmx_tx_ifg_s          cn66xx;
+	struct cvmx_agl_gmx_tx_ifg_s          cn68xx;
+	struct cvmx_agl_gmx_tx_ifg_s          cn68xxp1;
 };
 typedef union cvmx_agl_gmx_tx_ifg cvmx_agl_gmx_tx_ifg_t;
 
@@ -4131,12 +4423,10 @@ typedef union cvmx_agl_gmx_tx_ifg cvmx_agl_gmx_tx_ifg_t;
  * UNDFLW[1], XSCOL[1], XSDEF[1], LATE_COL[1], PTP_LOST[1] will be reset when MIX1_CTL[RESET] is set to 1.
  * PKO_NXA will bee reset when both MIX0/1_CTL[RESET] are set to 1.
  */
-union cvmx_agl_gmx_tx_int_en
-{
+union cvmx_agl_gmx_tx_int_en {
 	uint64_t u64;
-	struct cvmx_agl_gmx_tx_int_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_tx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_22_63               : 42;
 	uint64_t ptp_lost                     : 2;  /**< A packet with a PTP request was not able to be
                                                          sent due to XSCOL */
@@ -4165,9 +4455,8 @@ union cvmx_agl_gmx_tx_int_en
 	uint64_t reserved_22_63               : 42;
 #endif
 	} s;
-	struct cvmx_agl_gmx_tx_int_en_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_tx_int_en_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t late_col                     : 2;  /**< TX Late Collision */
 	uint64_t reserved_14_15               : 2;
@@ -4192,9 +4481,8 @@ union cvmx_agl_gmx_tx_int_en
 #endif
 	} cn52xx;
 	struct cvmx_agl_gmx_tx_int_en_cn52xx  cn52xxp1;
-	struct cvmx_agl_gmx_tx_int_en_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_tx_int_en_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t late_col                     : 1;  /**< TX Late Collision */
 	uint64_t reserved_13_15               : 3;
@@ -4219,8 +4507,12 @@ union cvmx_agl_gmx_tx_int_en
 #endif
 	} cn56xx;
 	struct cvmx_agl_gmx_tx_int_en_cn56xx  cn56xxp1;
+	struct cvmx_agl_gmx_tx_int_en_s       cn61xx;
 	struct cvmx_agl_gmx_tx_int_en_s       cn63xx;
 	struct cvmx_agl_gmx_tx_int_en_s       cn63xxp1;
+	struct cvmx_agl_gmx_tx_int_en_s       cn66xx;
+	struct cvmx_agl_gmx_tx_int_en_s       cn68xx;
+	struct cvmx_agl_gmx_tx_int_en_s       cn68xxp1;
 };
 typedef union cvmx_agl_gmx_tx_int_en cvmx_agl_gmx_tx_int_en_t;
 
@@ -4235,12 +4527,10 @@ typedef union cvmx_agl_gmx_tx_int_en cvmx_agl_gmx_tx_int_en_t;
  * UNDFLW[1], XSCOL[1], XSDEF[1], LATE_COL[1], PTP_LOST[1] will be reset when MIX1_CTL[RESET] is set to 1.
  * PKO_NXA will bee reset when both MIX0/1_CTL[RESET] are set to 1.
  */
-union cvmx_agl_gmx_tx_int_reg
-{
+union cvmx_agl_gmx_tx_int_reg {
 	uint64_t u64;
-	struct cvmx_agl_gmx_tx_int_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_tx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_22_63               : 42;
 	uint64_t ptp_lost                     : 2;  /**< A packet with a PTP request was not able to be
                                                          sent due to XSCOL */
@@ -4269,9 +4559,8 @@ union cvmx_agl_gmx_tx_int_reg
 	uint64_t reserved_22_63               : 42;
 #endif
 	} s;
-	struct cvmx_agl_gmx_tx_int_reg_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_tx_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t late_col                     : 2;  /**< TX Late Collision */
 	uint64_t reserved_14_15               : 2;
@@ -4296,9 +4585,8 @@ union cvmx_agl_gmx_tx_int_reg
 #endif
 	} cn52xx;
 	struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1;
-	struct cvmx_agl_gmx_tx_int_reg_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_tx_int_reg_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t late_col                     : 1;  /**< TX Late Collision */
 	uint64_t reserved_13_15               : 3;
@@ -4323,8 +4611,12 @@ union cvmx_agl_gmx_tx_int_reg
 #endif
 	} cn56xx;
 	struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
+	struct cvmx_agl_gmx_tx_int_reg_s      cn61xx;
 	struct cvmx_agl_gmx_tx_int_reg_s      cn63xx;
 	struct cvmx_agl_gmx_tx_int_reg_s      cn63xxp1;
+	struct cvmx_agl_gmx_tx_int_reg_s      cn66xx;
+	struct cvmx_agl_gmx_tx_int_reg_s      cn68xx;
+	struct cvmx_agl_gmx_tx_int_reg_s      cn68xxp1;
 };
 typedef union cvmx_agl_gmx_tx_int_reg cvmx_agl_gmx_tx_int_reg_t;
 
@@ -4338,12 +4630,10 @@ typedef union cvmx_agl_gmx_tx_int_reg cvmx_agl_gmx_tx_int_reg_t;
  * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
  *
  */
-union cvmx_agl_gmx_tx_jam
-{
+union cvmx_agl_gmx_tx_jam {
 	uint64_t u64;
-	struct cvmx_agl_gmx_tx_jam_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_tx_jam_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t jam                          : 8;  /**< Jam pattern */
 #else
@@ -4355,8 +4645,12 @@ union cvmx_agl_gmx_tx_jam
 	struct cvmx_agl_gmx_tx_jam_s          cn52xxp1;
 	struct cvmx_agl_gmx_tx_jam_s          cn56xx;
 	struct cvmx_agl_gmx_tx_jam_s          cn56xxp1;
+	struct cvmx_agl_gmx_tx_jam_s          cn61xx;
 	struct cvmx_agl_gmx_tx_jam_s          cn63xx;
 	struct cvmx_agl_gmx_tx_jam_s          cn63xxp1;
+	struct cvmx_agl_gmx_tx_jam_s          cn66xx;
+	struct cvmx_agl_gmx_tx_jam_s          cn68xx;
+	struct cvmx_agl_gmx_tx_jam_s          cn68xxp1;
 };
 typedef union cvmx_agl_gmx_tx_jam cvmx_agl_gmx_tx_jam_t;
 
@@ -4370,12 +4664,10 @@ typedef union cvmx_agl_gmx_tx_jam cvmx_agl_gmx_tx_jam_t;
  * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
  *
  */
-union cvmx_agl_gmx_tx_lfsr
-{
+union cvmx_agl_gmx_tx_lfsr {
 	uint64_t u64;
-	struct cvmx_agl_gmx_tx_lfsr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_tx_lfsr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t lfsr                         : 16; /**< The current state of the LFSR used to feed random
                                                          numbers to compute truncated binary exponential
@@ -4389,8 +4681,12 @@ union cvmx_agl_gmx_tx_lfsr
 	struct cvmx_agl_gmx_tx_lfsr_s         cn52xxp1;
 	struct cvmx_agl_gmx_tx_lfsr_s         cn56xx;
 	struct cvmx_agl_gmx_tx_lfsr_s         cn56xxp1;
+	struct cvmx_agl_gmx_tx_lfsr_s         cn61xx;
 	struct cvmx_agl_gmx_tx_lfsr_s         cn63xx;
 	struct cvmx_agl_gmx_tx_lfsr_s         cn63xxp1;
+	struct cvmx_agl_gmx_tx_lfsr_s         cn66xx;
+	struct cvmx_agl_gmx_tx_lfsr_s         cn68xx;
+	struct cvmx_agl_gmx_tx_lfsr_s         cn68xxp1;
 };
 typedef union cvmx_agl_gmx_tx_lfsr cvmx_agl_gmx_tx_lfsr_t;
 
@@ -4404,12 +4700,10 @@ typedef union cvmx_agl_gmx_tx_lfsr cvmx_agl_gmx_tx_lfsr_t;
  * IGN_FULL[0], BP[0], EN[0] will be reset when MIX0_CTL[RESET] is set to 1.
  * IGN_FULL[1], BP[1], EN[1] will be reset when MIX1_CTL[RESET] is set to 1.
  */
-union cvmx_agl_gmx_tx_ovr_bp
-{
+union cvmx_agl_gmx_tx_ovr_bp {
 	uint64_t u64;
-	struct cvmx_agl_gmx_tx_ovr_bp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_tx_ovr_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t en                           : 2;  /**< Per port Enable back pressure override */
 	uint64_t reserved_6_7                 : 2;
@@ -4429,9 +4723,8 @@ union cvmx_agl_gmx_tx_ovr_bp
 	} s;
 	struct cvmx_agl_gmx_tx_ovr_bp_s       cn52xx;
 	struct cvmx_agl_gmx_tx_ovr_bp_s       cn52xxp1;
-	struct cvmx_agl_gmx_tx_ovr_bp_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t en                           : 1;  /**< Per port Enable back pressure override */
 	uint64_t reserved_5_7                 : 3;
@@ -4450,8 +4743,12 @@ union cvmx_agl_gmx_tx_ovr_bp
 #endif
 	} cn56xx;
 	struct cvmx_agl_gmx_tx_ovr_bp_cn56xx  cn56xxp1;
+	struct cvmx_agl_gmx_tx_ovr_bp_s       cn61xx;
 	struct cvmx_agl_gmx_tx_ovr_bp_s       cn63xx;
 	struct cvmx_agl_gmx_tx_ovr_bp_s       cn63xxp1;
+	struct cvmx_agl_gmx_tx_ovr_bp_s       cn66xx;
+	struct cvmx_agl_gmx_tx_ovr_bp_s       cn68xx;
+	struct cvmx_agl_gmx_tx_ovr_bp_s       cn68xxp1;
 };
 typedef union cvmx_agl_gmx_tx_ovr_bp cvmx_agl_gmx_tx_ovr_bp_t;
 
@@ -4465,12 +4762,10 @@ typedef union cvmx_agl_gmx_tx_ovr_bp cvmx_agl_gmx_tx_ovr_bp_t;
  * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
  *
  */
-union cvmx_agl_gmx_tx_pause_pkt_dmac
-{
+union cvmx_agl_gmx_tx_pause_pkt_dmac {
 	uint64_t u64;
-	struct cvmx_agl_gmx_tx_pause_pkt_dmac_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t dmac                         : 48; /**< The DMAC field placed is outbnd pause pkts */
 #else
@@ -4482,8 +4777,12 @@ union cvmx_agl_gmx_tx_pause_pkt_dmac
 	struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
 	struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
 	struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
+	struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn61xx;
 	struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx;
 	struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1;
+	struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn66xx;
+	struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xx;
+	struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xxp1;
 };
 typedef union cvmx_agl_gmx_tx_pause_pkt_dmac cvmx_agl_gmx_tx_pause_pkt_dmac_t;
 
@@ -4497,12 +4796,10 @@ typedef union cvmx_agl_gmx_tx_pause_pkt_dmac cvmx_agl_gmx_tx_pause_pkt_dmac_t;
  * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
  *
  */
-union cvmx_agl_gmx_tx_pause_pkt_type
-{
+union cvmx_agl_gmx_tx_pause_pkt_type {
 	uint64_t u64;
-	struct cvmx_agl_gmx_tx_pause_pkt_type_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_gmx_tx_pause_pkt_type_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t type                         : 16; /**< The TYPE field placed is outbnd pause pkts */
 #else
@@ -4514,8 +4811,12 @@ union cvmx_agl_gmx_tx_pause_pkt_type
 	struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
 	struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
 	struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
+	struct cvmx_agl_gmx_tx_pause_pkt_type_s cn61xx;
 	struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx;
 	struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1;
+	struct cvmx_agl_gmx_tx_pause_pkt_type_s cn66xx;
+	struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xx;
+	struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xxp1;
 };
 typedef union cvmx_agl_gmx_tx_pause_pkt_type cvmx_agl_gmx_tx_pause_pkt_type_t;
 
@@ -4526,19 +4827,49 @@ typedef union cvmx_agl_gmx_tx_pause_pkt_type cvmx_agl_gmx_tx_pause_pkt_type_t;
  *
  *
  * Notes:
+ * The RGMII timing specification requires that devices transmit clock and
+ * data synchronously. The specification requires external sources (namely
+ * the PC board trace routes) to introduce the appropriate 1.5 to 2.0 ns of
+ * delay.
+ *
+ * To eliminate the need for the PC board delays, the MIX RGMII interface
+ * has optional onboard DLL's for both transmit and receive. For correct
+ * operation, at most one of the transmitter, board, or receiver involved
+ * in an RGMII link should introduce delay. By default/reset,
+ * the MIX RGMII receivers delay the received clock, and the MIX
+ * RGMII transmitters do not delay the transmitted clock. Whether this
+ * default works as-is with a given link partner depends on the behavior
+ * of the link partner and the PC board.
+ *
+ * These are the possible modes of MIX RGMII receive operation:
+ *  o AGL_PRTx_CTL[CLKRX_BYP] = 0 (reset value) - The OCTEON MIX RGMII
+ *    receive interface introduces clock delay using its internal DLL.
+ *    This mode is appropriate if neither the remote
+ *    transmitter nor the PC board delays the clock.
+ *  o AGL_PRTx_CTL[CLKRX_BYP] = 1, [CLKRX_SET] = 0x0 - The OCTEON MIX
+ *    RGMII receive interface introduces no clock delay. This mode
+ *    is appropriate if either the remote transmitter or the PC board
+ *    delays the clock.
+ *
+ * These are the possible modes of MIX RGMII transmit operation:
+ *  o AGL_PRTx_CTL[CLKTX_BYP] = 1, [CLKTX_SET] = 0x0 (reset value) -
+ *    The OCTEON MIX RGMII transmit interface introduces no clock
+ *    delay. This mode is appropriate is either the remote receiver
+ *    or the PC board delays the clock.
+ *  o AGL_PRTx_CTL[CLKTX_BYP] = 0 - The OCTEON MIX RGMII transmit
+ *    interface introduces clock delay using its internal DLL.
+ *    This mode is appropriate if neither the remote receiver
+ *    nor the PC board delays the clock.
+ *
  * AGL_PRT0_CTL will be reset when MIX0_CTL[RESET] is set to 1.
  * AGL_PRT1_CTL will be reset when MIX1_CTL[RESET] is set to 1.
  */
-union cvmx_agl_prtx_ctl
-{
+union cvmx_agl_prtx_ctl {
 	uint64_t u64;
-	struct cvmx_agl_prtx_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_agl_prtx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t drv_byp                      : 1;  /**< Bypass the compensation controller and use
-                                                         DRV_NCTL and DRV_PCTL
-                                                         Note: the reset value was changed from pass1
-                                                         to pass2. */
+                                                         DRV_NCTL and DRV_PCTL */
 	uint64_t reserved_62_62               : 1;
 	uint64_t cmp_pctl                     : 6;  /**< PCTL drive strength from the compensation ctl */
 	uint64_t reserved_54_55               : 2;
@@ -4562,7 +4893,6 @@ union cvmx_agl_prtx_ctl
                                                          Skews RXC from RXD in RGMII mode */
 	uint64_t clktx_byp                    : 1;  /**< Bypass the TX clock delay setting
                                                          Skews TXC from TXD,TXCTL in RGMII mode
-                                                         Skews RXC from RXD,RXCTL in RGMII mode
                                                          By default, clock and data and sourced
                                                          synchronously.
                                                          In MII mode, the CLKRX_BYP is forced to 1. */
@@ -4572,9 +4902,7 @@ union cvmx_agl_prtx_ctl
 	uint64_t reserved_5_7                 : 3;
 	uint64_t dllrst                       : 1;  /**< DLL Reset */
 	uint64_t comp                         : 1;  /**< Compensation Enable */
-	uint64_t enable                       : 1;  /**< Port Enable
-                                                         Note: the reset value was changed from pass1
-                                                         to pass2. */
+	uint64_t enable                       : 1;  /**< Port Enable */
 	uint64_t clkrst                       : 1;  /**< Clock Tree Reset */
 	uint64_t mode                         : 1;  /**< Port Mode
                                                          MODE must be set the same for all ports in which
@@ -4607,8 +4935,12 @@ union cvmx_agl_prtx_ctl
 	uint64_t drv_byp                      : 1;
 #endif
 	} s;
+	struct cvmx_agl_prtx_ctl_s            cn61xx;
 	struct cvmx_agl_prtx_ctl_s            cn63xx;
 	struct cvmx_agl_prtx_ctl_s            cn63xxp1;
+	struct cvmx_agl_prtx_ctl_s            cn66xx;
+	struct cvmx_agl_prtx_ctl_s            cn68xx;
+	struct cvmx_agl_prtx_ctl_s            cn68xxp1;
 };
 typedef union cvmx_agl_prtx_ctl cvmx_agl_prtx_ctl_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-app-hotplug.c b/sys/contrib/octeon-sdk/cvmx-app-hotplug.c
index 6145134..a2c54d2 100644
--- a/sys/contrib/octeon-sdk/cvmx-app-hotplug.c
+++ b/sys/contrib/octeon-sdk/cvmx-app-hotplug.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,9 +48,12 @@
 
 #include "cvmx-app-hotplug.h"
 #include "cvmx-spinlock.h"
+#include "cvmx-debug.h"
 
 //#define DEBUG 1
 
+static cvmx_app_hotplug_global_t *hotplug_global_ptr = 0;
+
 #ifndef CVMX_BUILD_FOR_LINUX_USER
 
 static CVMX_SHARED cvmx_spinlock_t cvmx_app_hotplug_sync_lock = { CVMX_SPINLOCK_UNLOCKED_VAL };
@@ -61,6 +64,11 @@ static void __cvmx_app_hotplug_shutdown(int irq_number, uint64_t registers[32],
 static void __cvmx_app_hotplug_sync(void);
 static void __cvmx_app_hotplug_reset(void);
 
+/* Declaring this array here is a compile time check to ensure that the
+   size of  cvmx_app_hotplug_info_t is 1024. If the size is not 1024
+   the size of the array will be -1 and this results in a compilation
+   error */
+char __hotplug_info_check[(sizeof(cvmx_app_hotplug_info_t) == 1024) ? 1 : -1];
 /**
  * This routine registers an application for hotplug. It installs a handler for
  * any incoming shutdown request. It also registers a callback routine from the
@@ -90,7 +98,7 @@ int cvmx_app_hotplug_register(void(*fn)(void*), void* arg)
     cvmx_app_hotplug_info_ptr->shutdown_callback = CAST64(fn);
 
 #ifdef DEBUG
-    cvmx_dprintf("cvmx_app_hotplug_register(): coremask 0x%x valid %d\n", 
+    printf("cvmx_app_hotplug_register(): coremask 0x%x valid %d\n", 
                   cvmx_app_hotplug_info_ptr->coremask, cvmx_app_hotplug_info_ptr->valid);
 #endif
 
@@ -100,7 +108,82 @@ int cvmx_app_hotplug_register(void(*fn)(void*), void* arg)
 }
 
 /**
- * Activate the current application core for receiving hotplug shutdown requests. 
+ * This routine deprecates the the cvmx_app_hotplug_register method. This
+ * registers application for hotplug and the application will have CPU
+ * hotplug callbacks. Various callbacks are specified in cb.
+ * cvmx_app_hotplug_callbacks_t documents the callbacks
+ *
+ * This routine only needs to be called once per application.
+ *
+ * @param cb      Callback routine from the application.
+ * @param arg     Argument to the application callback routins
+ * @param app_shutdown   When set to 1 the application will invoke core_shutdown
+                         on each core. When set to 0 core shutdown will be
+                         called invoked automatically after invoking the
+                         application callback.
+ * @return        Return index of app on success, -1 on failure
+ *
+ */
+int cvmx_app_hotplug_register_cb(cvmx_app_hotplug_callbacks_t *cb, void* arg,
+                                 int app_shutdown)
+{
+    cvmx_app_hotplug_info_t *app_info;
+
+    /* Find the list of applications launched by bootoct utility. */
+    app_info = cvmx_app_hotplug_get_info(cvmx_sysinfo_get()->core_mask);
+    cvmx_app_hotplug_info_ptr = app_info;
+    if (!app_info)
+    {
+        /* Application not launched by bootoct? */
+        printf("ERROR: cmvx_app_hotplug_register() failed\n");
+        return -1;
+    }
+    /* Register the callback */
+    app_info->data = CAST64(arg);
+    app_info->shutdown_callback  = CAST64(cb->shutdown_callback);
+    app_info->cores_added_callback = CAST64(cb->cores_added_callback);
+    app_info->cores_removed_callback = CAST64(cb->cores_removed_callback);
+    app_info->unplug_callback = CAST64(cb->unplug_core_callback);
+    app_info->hotplug_start = CAST64(cb->hotplug_start);
+    app_info->app_shutdown = app_shutdown;
+#ifdef DEBUG
+    printf("cvmx_app_hotplug_register(): coremask 0x%x valid %d\n",
+           app_info->coremask, app_info->valid);
+#endif
+
+    cvmx_interrupt_register(CVMX_IRQ_MBOX0, __cvmx_app_hotplug_shutdown, NULL);
+    return 0;
+
+}
+
+void cvmx_app_hotplug_remove_self_from_core_mask(void)
+{
+    int core = cvmx_get_core_num();
+    uint32_t core_mask = 1ull << core;
+
+    cvmx_spinlock_lock(&cvmx_app_hotplug_lock);
+    cvmx_app_hotplug_info_ptr->coremask = cvmx_app_hotplug_info_ptr->coremask & ~core_mask ;
+    cvmx_app_hotplug_info_ptr->hotplug_activated_coremask =
+        cvmx_app_hotplug_info_ptr->hotplug_activated_coremask & ~core_mask ;
+    cvmx_spinlock_unlock(&cvmx_app_hotplug_lock);
+}
+
+
+
+/**
+*  Returns 1 if the running core is being unplugged, else it returns 0.
+*/
+int is_core_being_unplugged(void)
+{
+    if (cvmx_app_hotplug_info_ptr->unplug_cores &
+        (1ull << cvmx_get_core_num()))
+        return 1;
+    return 0;
+}
+
+
+/**
+ * Activate the current application core for receiving hotplug shutdown requests.
  *
  * This routine makes sure that each core belonging to the application is enabled 
  * to receive the shutdown notification and also provides a barrier sync to make
@@ -108,25 +191,41 @@ int cvmx_app_hotplug_register(void(*fn)(void*), void* arg)
  */
 int cvmx_app_hotplug_activate(void)
 {
-    /* Make sure all application cores are activating */
-    __cvmx_app_hotplug_sync();
+    uint64_t cnt = 0;
+    uint64_t cnt_interval = 10000000;
 
-    cvmx_spinlock_lock(&cvmx_app_hotplug_lock);
+    while (!cvmx_app_hotplug_info_ptr) 
+    {
+        cnt++;
+        if ((cnt % cnt_interval) == 0)
+            printf("waiting for cnt=%lld\n", (unsigned long long)cnt);
+    }
 
+    if (cvmx_app_hotplug_info_ptr->hplugged_cores & (1ull << cvmx_get_core_num()))
+    {
+#ifdef DEBUG
+        printf("core=%d : is being hotplugged \n", cvmx_get_core_num());
+#endif
+        cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
+        sys_info_ptr->core_mask |= 1ull << cvmx_get_core_num();
+    }
+    else
+    {
+        __cvmx_app_hotplug_sync();
+    }
+    cvmx_spinlock_lock(&cvmx_app_hotplug_lock);
     if (!cvmx_app_hotplug_info_ptr)
     {
         cvmx_spinlock_unlock(&cvmx_app_hotplug_lock);
         printf("ERROR: This application is not registered for hotplug\n");
-	return -1;
+        return -1;
     }
-
     /* Enable the interrupt before we mark the core as activated */
     cvmx_interrupt_unmask_irq(CVMX_IRQ_MBOX0);
-
-    cvmx_app_hotplug_info_ptr->hotplug_activated_coremask |= (1<<cvmx_get_core_num());
+    cvmx_app_hotplug_info_ptr->hotplug_activated_coremask |= (1ull<<cvmx_get_core_num());
 
 #ifdef DEBUG
-    cvmx_dprintf("cvmx_app_hotplug_activate(): coremask 0x%x valid %d sizeof %d\n", 
+    printf("cvmx_app_hotplug_activate(): coremask 0x%x valid %d sizeof %d\n", 
                  cvmx_app_hotplug_info_ptr->coremask, cvmx_app_hotplug_info_ptr->valid, 
                  sizeof(*cvmx_app_hotplug_info_ptr));
 #endif
@@ -180,75 +279,196 @@ void cvmx_app_hotplug_shutdown_enable(void)
     cvmx_interrupt_unmask_irq(CVMX_IRQ_MBOX0);
 }
 
+/**
+*  Request shutdown of the currently running core. Should be
+*  called by the application when it has been registered with
+*  app_shutdown option set to 1.
+*/
+void cvmx_app_hotplug_core_shutdown(void)
+{
+    uint32_t flags;
+    if (cvmx_app_hotplug_info_ptr->shutdown_cores)
+    {
+        cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
+       __cvmx_app_hotplug_sync();
+        if (cvmx_coremask_first_core(sys_info_ptr->core_mask))
+        {
+            bzero(cvmx_app_hotplug_info_ptr,
+                  sizeof(*cvmx_app_hotplug_info_ptr));
+            #ifdef DEBUG
+            printf("__cvmx_app_hotplug_shutdown(): setting shutdown done! \n");
+            #endif
+            cvmx_app_hotplug_info_ptr->shutdown_done = 1;
+        }
+        /* Tell the debugger that this application is finishing.  */
+        cvmx_debug_finish ();
+        flags = cvmx_interrupt_disable_save();
+        __cvmx_app_hotplug_sync();
+        /* Reset the core */
+        __cvmx_app_hotplug_reset();
+    }
+    else
+    {
+        cvmx_sysinfo_remove_self_from_core_mask();
+        cvmx_app_hotplug_remove_self_from_core_mask();
+        flags = cvmx_interrupt_disable_save();
+        __cvmx_app_hotplug_reset();
+    }
+}
+
 /*
- * ISR for the incoming shutdown request interrupt. 
+ * ISR for the incoming shutdown request interrupt.
  */
-static void __cvmx_app_hotplug_shutdown(int irq_number, uint64_t registers[32], void *user_arg)
+static void __cvmx_app_hotplug_shutdown(int irq_number, uint64_t registers[32],
+                                        void *user_arg)
 {
     cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
-    uint32_t flags;
+    uint64_t mbox;
+    cvmx_app_hotplug_info_t *ai = cvmx_app_hotplug_info_ptr;
+    int dbg = 0;
 
+#ifdef DEBUG
+    dbg = 1;
+#endif
     cvmx_interrupt_mask_irq(CVMX_IRQ_MBOX0);
 
+    mbox = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()));
     /* Clear the interrupt */
-    cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 1);
+    cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), mbox);
 
     /* Make sure the write above completes */
     cvmx_read_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()));
 
+
     if (!cvmx_app_hotplug_info_ptr)
     {
         printf("ERROR: Application is not registered for hotplug!\n");
         return;
     }
 
-    if (cvmx_app_hotplug_info_ptr->hotplug_activated_coremask != sys_info_ptr->core_mask)
+    if (ai->hotplug_activated_coremask != sys_info_ptr->core_mask)
     {
-        printf("ERROR: Shutdown requested when not all app cores have activated hotplug\n"
-	       "Application coremask: 0x%x Hotplug coremask: 0x%x\n", (unsigned int)sys_info_ptr->core_mask, 
-	       (unsigned int)cvmx_app_hotplug_info_ptr->hotplug_activated_coremask);
-	return;
+        printf("ERROR: Shutdown requested when not all app cores have "
+               "activated hotplug\n" "Application coremask: 0x%x Hotplug "
+               "coremask: 0x%x\n", (unsigned int)sys_info_ptr->core_mask,
+               (unsigned int)ai->hotplug_activated_coremask);
+        return;
     }
 
-    /* Call the application's own callback function */
-    ((void(*)(void*))(long)cvmx_app_hotplug_info_ptr->shutdown_callback)(CASTPTR(void *, cvmx_app_hotplug_info_ptr->data));
-
-    __cvmx_app_hotplug_sync();
-
-    if (cvmx_coremask_first_core(sys_info_ptr->core_mask))
+    if (mbox & 1ull)
     {
-        bzero(cvmx_app_hotplug_info_ptr, sizeof(*cvmx_app_hotplug_info_ptr));
-#ifdef DEBUG
-        cvmx_dprintf("__cvmx_app_hotplug_shutdown(): setting shutdown done! \n");
-#endif
-        cvmx_app_hotplug_info_ptr->shutdown_done = 1;
+        int core = cvmx_get_core_num();
+        if (dbg)
+            printf("Shutting down application .\n");
+        /* Call the application's own callback function */
+        if (ai->shutdown_callback)
+        {
+            ((void(*)(void*))(long)ai->shutdown_callback)(CASTPTR(void *, ai->data));
+        }
+        else
+        {
+            printf("ERROR : Shutdown callback has not been registered\n");
+        }
+        if (!ai->app_shutdown)
+        {
+            if (dbg) 
+                printf("%s : core = %d Invoking app shutdown\n", __FUNCTION__, core);
+            cvmx_app_hotplug_core_shutdown();
+        }
     }
+    else if (mbox & 2ull)
+    {
+        int core = cvmx_get_core_num();
+        int unplug = is_core_being_unplugged();
+        if (dbg) printf("%s : core=%d Unplug event \n", __FUNCTION__, core);
 
-    flags = cvmx_interrupt_disable_save();
+        if (unplug)
+        {
+            /* Call the application's own callback function */
+            if (ai->unplug_callback)
+            {
+                if (dbg) printf("%s : core=%d Calling unplug callback\n",
+                                __FUNCTION__, core);
+                ((void(*)(void*))(long)ai->unplug_callback)(CASTPTR(void *,
+                                                           ai->data));
+            }
+            if (!ai->app_shutdown)
+            {
+                if (dbg) printf("%s : core = %d Invoking app shutdown\n",
+                                __FUNCTION__, core);
+                cvmx_app_hotplug_core_shutdown();
+            }
+        }
+        else
+        {
+            if (ai->cores_removed_callback)
+            {
+                if (dbg) printf("%s : core=%d Calling cores removed callback\n",
+                                __FUNCTION__, core);
+                ((void(*)(uint32_t, void*))(long)ai->cores_removed_callback)
+                    (ai->unplug_cores, CASTPTR(void *, ai->data));
+            }
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_MBOX0);
+        }
+    }
+    else if (mbox & 4ull)
+    {
+        int core = cvmx_get_core_num();
+        if (dbg) printf("%s : core=%d Add cores event \n", __FUNCTION__, core);
 
-    __cvmx_app_hotplug_sync();
+        if (ai->cores_added_callback)
+        {
+            if (dbg) printf("%s : core=%d Calling cores added callback\n",
+                            __FUNCTION__, core);
+            ((void(*)(uint32_t, void*))(long)ai->cores_added_callback)
+                (ai->hplugged_cores, CASTPTR(void *, ai->data));
+        }
+        cvmx_interrupt_unmask_irq(CVMX_IRQ_MBOX0);
+    }
+    else
+    {
+        printf("ERROR: unexpected mbox=%llx\n", (unsigned long long)mbox);
+    }
 
-    /* Reset the core */
-    __cvmx_app_hotplug_reset();
 }
 
-/*
- * Reset the core. We just jump back to the reset vector for now. 
- */
 void __cvmx_app_hotplug_reset(void)
 {
-    /* Code from SecondaryCoreLoop from bootloader, sleep until we recieve
-       a NMI. */
-    __asm__ volatile (
-        ".set noreorder      \n"
-	"\tsync               \n"
-	"\tnop               \n"
-        "1:\twait            \n"
-        "\tb 1b              \n"
-	"\tnop               \n"             
-	".set reorder        \n"
-	:: 
-    );
+#define IDLE_CORE_BLOCK_NAME    "idle-core-loop"
+#define HPLUG_MAKE_XKPHYS(x)       ((1ULL << 63) | (x))
+    uint64_t reset_addr;
+    const cvmx_bootmem_named_block_desc_t *block_desc;
+
+    block_desc = cvmx_bootmem_find_named_block(IDLE_CORE_BLOCK_NAME);
+    if (!block_desc) {
+        cvmx_dprintf("Named block(%s) is not created\n", IDLE_CORE_BLOCK_NAME);
+        /* loop here, should not happen */
+        __asm__ volatile (
+                          ".set noreorder      \n"
+                          "\tsync               \n"
+                          "\tnop               \n"
+                          "1:\twait            \n"
+                          "\tb 1b              \n"
+                          "\tnop               \n"
+                          ".set reorder        \n"
+                          ::
+                          );
+    }
+
+    reset_addr = HPLUG_MAKE_XKPHYS(block_desc->base_addr);
+    asm volatile ("       .set push                \n"
+                  "       .set mips64              \n"
+                  "       .set noreorder           \n"
+                  "       move  $2, %[addr]        \n"
+                  "       jr    $2                 \n"
+                  "       nop                      \n"
+                  "       .set pop "
+                  :: [addr] "r"(reset_addr)
+                  : "$2");
+
+    /*Should never reach here*/
+    while (1) ;
+
 }
 
 /* 
@@ -268,34 +488,47 @@ static void __cvmx_app_hotplug_sync(void)
     cvmx_spinlock_unlock(&cvmx_app_hotplug_sync_lock);
 
     while (sync_coremask != sys_info_ptr->core_mask);
+
+    cvmx_spinlock_lock(&cvmx_app_hotplug_sync_lock);
+    sync_coremask = 0;
+    cvmx_spinlock_unlock(&cvmx_app_hotplug_sync_lock);
+
+
 }
 
 #endif /* CVMX_BUILD_FOR_LINUX_USER */
 
 /**
- * Return the hotplug info structure (cvmx_app_hotplug_info_t) pointer for the 
- * application running on the given coremask. 
- *
- * @param coremask     Coremask of application. 
- * @return             Returns hotplug info struct on success, NULL on failure
- *
- */
-cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info(uint32_t coremask)
+*  Returns 1 if the running core is being hotplugged, else it returns 0.
+*/
+int is_core_being_hot_plugged(void)
+{
+
+#ifndef CVMX_BUILD_FOR_LINUX_USER
+    if (!cvmx_app_hotplug_info_ptr) return 0;
+    if (cvmx_app_hotplug_info_ptr->hplugged_cores &
+        (1ull << cvmx_get_core_num()))
+        return 1;
+    return 0;
+#else
+    return 0;
+#endif
+}
+
+static cvmx_app_hotplug_global_t *cvmx_app_get_hotplug_global_ptr(void)
 {
     const struct cvmx_bootmem_named_block_desc *block_desc;
-    cvmx_app_hotplug_info_t *hip;
     cvmx_app_hotplug_global_t *hgp;
-    int i;
 
-    block_desc = cvmx_bootmem_find_named_block(CVMX_APP_HOTPLUG_INFO_REGION_NAME);
+    if(hotplug_global_ptr != 0) return hotplug_global_ptr;
 
+    block_desc = cvmx_bootmem_find_named_block(CVMX_APP_HOTPLUG_INFO_REGION_NAME);
     if (!block_desc)
     {
         printf("ERROR: Hotplug info region is not setup\n");
         return NULL;
     }
     else
-
 #ifdef CVMX_BUILD_FOR_LINUX_USER
     {
         size_t pg_sz = sysconf(_SC_PAGESIZE), size;
@@ -314,7 +547,8 @@ cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info(uint32_t coremask)
          */
         size = CVMX_APP_HOTPLUG_INFO_REGION_SIZE + pg_sz-1;
         offset = block_desc->base_addr & ~(pg_sz-1);
-        if ((vaddr = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, offset)) == MAP_FAILED) 
+        if ((vaddr = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, offset)) 
+	    == MAP_FAILED) 
         {
             perror("mmap");
             return NULL;
@@ -323,35 +557,143 @@ cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info(uint32_t coremask)
         hgp = (cvmx_app_hotplug_global_t *)(vaddr + ( block_desc->base_addr & (pg_sz-1)));
     }
 #else
-    hgp = cvmx_phys_to_ptr(block_desc->base_addr);
+    hgp = CASTPTR(void, CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, block_desc->base_addr));
 #endif
+    hotplug_global_ptr = hgp;
+    return hgp;
 
-    hip = hgp->hotplug_info_array;
+}
+
+/**
+ * Return the hotplug info structure (cvmx_app_hotplug_info_t) pointer for the 
+ * application running on the given coremask. 
+ *
+ * @param coremask     Coremask of application. 
+ * @return             Returns hotplug info struct on success, NULL on failure
+ *
+ */
+cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info(uint32_t coremask)
+{
+    cvmx_app_hotplug_info_t *hip;
+    cvmx_app_hotplug_global_t *hgp;
+    int i;
+    int dbg = 0;
 
 #ifdef DEBUG
-    cvmx_dprintf("cvmx_app_hotplug_get_info(): hotplug_info phy addr 0x%llx ptr %p\n", 
-                  block_desc->base_addr, hgp);
+    dbg = 1;
 #endif
+    hgp = cvmx_app_get_hotplug_global_ptr();
+    if (!hgp) return NULL;
+    hip = hgp->hotplug_info_array;
 
     /* Look for the current app's info */
-
     for (i=0; i<CVMX_APP_HOTPLUG_MAX_APPS; i++)
     {
         if (hip[i].coremask == coremask)
-	{
+        {
+	    if (dbg)
+                printf("cvmx_app_hotplug_get_info(): coremask match %d -- coremask 0x%x, valid %d\n", i, (unsigned int)hip[i].coremask, (unsigned int)hip[i].valid);
+            return &hip[i];
+        }
+    }
+    return NULL;
+}
+
+/**
+ * Return the hotplug application index structure for the application running on the 
+ * given coremask. 
+ *
+ * @param coremask     Coremask of application. 
+ * @return             Returns hotplug application index on success. -1 on failure
+ *                     
+ */
+int cvmx_app_hotplug_get_index(uint32_t coremask)
+{
+    cvmx_app_hotplug_info_t *hip;
+    cvmx_app_hotplug_global_t *hgp;
+    int i;
+    int dbg = 0;
+
 #ifdef DEBUG
-	    cvmx_dprintf("cvmx_app_hotplug_get_info(): coremask match %d -- coremask 0x%x valid %d\n", 
-	                 i, hip[i].coremask, hip[i].valid);
+    dbg = 1;
 #endif
+    hgp = cvmx_app_get_hotplug_global_ptr();
+    if (!hgp) return -1;
+    hip = hgp->hotplug_info_array;
 
-	    return &hip[i];
-	}
+    /* Look for the current app's info */
+    for (i=0; i<CVMX_APP_HOTPLUG_MAX_APPS; i++)
+    {
+        if (hip[i].coremask == coremask)
+        {
+	    if (dbg)
+                printf("cvmx_app_hotplug_get_info(): coremask match %d -- coremask 0x%x valid %d\n", i, (unsigned int)hip[i].coremask, (unsigned int)hip[i].valid);
+	    return i;
+        }
     }
+    return -1;
+}
+
+void print_hot_plug_info(cvmx_app_hotplug_info_t* hpinfo)
+{
+    printf("name=%s coremask=%08x hotplugged coremask=%08x valid=%d\n", hpinfo->app_name,
+           (unsigned int)hpinfo->coremask, (unsigned int)hpinfo->hotplug_activated_coremask, (unsigned int)hpinfo->valid);
+}
 
+/**
+ * Return the hotplug info structure (cvmx_app_hotplug_info_t) pointer for the 
+ * application with the specified index.
+ *
+ * @param index        index of application. 
+ * @return             Returns hotplug info struct on success, NULL on failure
+ *
+ */
+cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info_at_index(int index)
+{
+    cvmx_app_hotplug_info_t *hip;
+    cvmx_app_hotplug_global_t *hgp;
+
+    hgp = cvmx_app_get_hotplug_global_ptr();
+    if (!hgp) return NULL;
+    hip = hgp->hotplug_info_array;
+
+#ifdef DEBUG
+    printf("cvmx_app_hotplug_get_info(): hotplug_info phy addr 0x%llx ptr %p\n", 
+                  block_desc->base_addr, hgp);
+#endif
+    if (index < CVMX_APP_HOTPLUG_MAX_APPS)
+    {
+        if (hip[index].valid) 
+        {
+            //print_hot_plug_info( &hip[index] );
+            return &hip[index];
+        }
+    }
     return NULL;
 }
 
 /**
+ * Determines if SE application at the index specified is hotpluggable.
+ *
+ * @param index        index of application.
+ * @return             Returns -1  on error.
+ *                     0 -> The application is not hotpluggable
+ *                     1 -> The application is hotpluggable
+*/
+int is_app_hotpluggable(int index)
+{
+    cvmx_app_hotplug_info_t *ai;
+
+    if (!(ai = cvmx_app_hotplug_get_info_at_index(index)))
+    {
+        printf("\nERROR: Failed to get hotplug info for app at index=%d\n", index);
+        return -1;
+    }
+    if (ai->hotplug_activated_coremask) return 1;
+    return 0;
+}
+
+/**
  * This routine sends a shutdown request to a running target application. 
  *
  * @param coremask     Coremask the application is running on. 
@@ -371,7 +713,7 @@ int cvmx_app_hotplug_shutdown_request(uint32_t coremask, int wait)
         printf("\nERROR: Failed to get hotplug info for coremask: 0x%x\n", (unsigned int)coremask);
         return -1;
     }
-
+    hotplug_info_ptr->shutdown_cores = coremask;
     if (!hotplug_info_ptr->shutdown_callback)
     {
         printf("\nERROR: Target application has not registered for hotplug!\n");
@@ -386,8 +728,8 @@ int cvmx_app_hotplug_shutdown_request(uint32_t coremask, int wait)
 
     /* Send IPIs to all application cores to request shutdown */
     for (i=0; i<CVMX_MAX_CORES; i++) {
-    	if (coremask & (1<<i))
-		cvmx_write_csr(CVMX_CIU_MBOX_SETX(i), 1);
+            if (coremask & (1ull<<i))
+                cvmx_write_csr(CVMX_CIU_MBOX_SETX(i), 1);
     }
 
     if (wait)
@@ -400,3 +742,144 @@ int cvmx_app_hotplug_shutdown_request(uint32_t coremask, int wait)
 
     return 0;
 }
+
+
+
+/**
+ * This routine invokes the invoked the cores_added callbacks.
+ */
+int cvmx_app_hotplug_call_add_cores_callback(int index)
+{
+    cvmx_app_hotplug_info_t *ai;
+    int i;
+    if (!(ai = cvmx_app_hotplug_get_info_at_index(index)))
+    {
+        printf("\nERROR: Failed to get hotplug info for app at index=%d\n", index);
+        return -1;
+    }
+   /* Send IPIs to all application cores to request add_cores callback*/
+    for (i=0; i<CVMX_MAX_CORES; i++) {
+            if (ai->coremask & (1ull<<i))
+                cvmx_write_csr(CVMX_CIU_MBOX_SETX(i), 4);
+    }
+    return 0;
+}
+
+/**
+ * This routine sends a request to a running target application
+ * to unplug a specified set cores
+ * @param index        is the index of the target application
+ * @param coremask     Coremask of the cores to be unplugged from the app.
+ * @param wait         1 - Wait for shutdown completion
+ *                     0 - Do not wait
+ * @return             0 on success, -1 on error
+ *
+ */ 
+int cvmx_app_hotplug_unplug_cores(int index, uint32_t coremask, int wait) 
+{
+    cvmx_app_hotplug_info_t *ai;
+    int i;
+
+    if (!(ai = cvmx_app_hotplug_get_info_at_index(index)))
+    {
+        printf("\nERROR: Failed to get hotplug info for app at index=%d\n", index);
+        return -1;
+    }
+    ai->unplug_cores = coremask;
+#if 0
+    if (!ai->shutdown_callback)
+    {
+        printf("\nERROR: Target application has not registered for hotplug!\n");
+        return -1;
+    }
+#endif
+    if ( (ai->coremask | coremask ) != ai->coremask)
+    {
+        printf("\nERROR: Not all cores requested are a part of the app "
+               "r=%08x:%08x\n", (unsigned int)coremask, (unsigned int)ai->coremask);
+        return -1;
+    }
+    if (ai->coremask == coremask)
+    {
+        printf("\nERROR: Trying to remove all cores in app. "
+               "r=%08x:%08x\n", (unsigned int)coremask, (unsigned int)ai->coremask);
+        return -1;
+    }
+    /* Send IPIs to all application cores to request unplug/remove_cores
+       callback */
+    for (i=0; i<CVMX_MAX_CORES; i++) {
+            if (ai->coremask & (1ull<<i))
+                cvmx_write_csr(CVMX_CIU_MBOX_SETX(i), 2);
+    }
+
+#if 0
+    if (wait)
+    {
+        while (!ai->shutdown_done);    
+
+        /* Clean up the hotplug info region for this application */
+        bzero(ai, sizeof(*ai));
+    }
+#endif
+    return 0;
+}
+
+/**
+ * Returns 1 if any app is currently being currently booted , hotplugged or
+ * shutdown. Only one app can be under a boot, hotplug or shutdown condition.
+ * Before booting an app this methods should be used to check whether boot or
+ * shutdown activity is in progress and proceed with the boot or shutdown only
+ * when there is no other activity.
+ *
+ */
+int is_app_under_boot_or_shutdown(void)
+{
+    int ret=0;
+    cvmx_app_hotplug_global_t *hgp;
+
+    hgp = cvmx_app_get_hotplug_global_ptr();
+    cvmx_spinlock_lock(&hgp->hotplug_global_lock);
+    if (hgp->app_under_boot || hgp->app_under_shutdown) ret=1;
+    cvmx_spinlock_unlock(&hgp->hotplug_global_lock);
+    return ret;
+
+}
+
+/**
+ * Sets or clear the app_under_boot value. This when set signifies that an app
+ * is being currently booted or hotplugged with a new core.
+ *
+ *
+ * @param val     sets the app_under_boot to the specified value. This should be
+ *                set to 1 while app any is being booted and cleared after the
+ *                application has booted up.
+ *
+ */
+void set_app_unber_boot(int val)
+{
+    cvmx_app_hotplug_global_t *hgp;
+
+    hgp = cvmx_app_get_hotplug_global_ptr();
+    cvmx_spinlock_lock(&hgp->hotplug_global_lock);
+    hgp->app_under_boot = val;
+    cvmx_spinlock_unlock(&hgp->hotplug_global_lock);
+}
+
+/**
+ * Sets or clear the app_under_shutdown value. This when set signifies that an
+ * app is being currently shutdown or some cores of an app are being shutdown.
+ *
+ * @param val     sets the app_under_shutdown to the specified value. This
+ *                should be set to 1 while any app is being shutdown and cleared
+ *                after the shutdown of the app is complete.
+ *
+ */
+void set_app_under_shutdown(int val)
+{
+    cvmx_app_hotplug_global_t *hgp;
+
+    hgp = cvmx_app_get_hotplug_global_ptr();
+    cvmx_spinlock_lock(&hgp->hotplug_global_lock);
+    hgp->app_under_shutdown = val;
+    cvmx_spinlock_unlock(&hgp->hotplug_global_lock);
+}
diff --git a/sys/contrib/octeon-sdk/cvmx-app-hotplug.h b/sys/contrib/octeon-sdk/cvmx-app-hotplug.h
index bfa62f8..4e251bb 100644
--- a/sys/contrib/octeon-sdk/cvmx-app-hotplug.h
+++ b/sys/contrib/octeon-sdk/cvmx-app-hotplug.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,47 +48,99 @@
 #ifndef __CVMX_APP_HOTPLUG_H__
 #define __CVMX_APP_HOTPLUG_H__
 
-#ifdef	__cplusplus
+#ifdef    __cplusplus
 extern "C" {
 #endif
 
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <asm/octeon/cvmx.h>
 #include <asm/octeon/cvmx-bootmem.h>
+#include <asm/octeon/cvmx-spinlock.h>
 #else
 #include "cvmx.h"
 #include "cvmx-coremask.h"
 #include "cvmx-interrupt.h"
 #include "cvmx-bootmem.h"
+#include "cvmx-spinlock.h"
 #endif
 
 #define CVMX_APP_HOTPLUG_MAX_APPS 32
 #define CVMX_APP_HOTPLUG_MAX_APPNAME_LEN 256
 
+/**
+* hotplug_start          is the entry  point for hot plugged cores.
+* cores_added_callback   is callback which in invoked when new cores are added
+*                        to the application. This is invoked on all the old core
+*                        that existed before the current set of cores were
+*                        added.
+* cores_removed_callback is callback which in invoked when cores are removed
+*                        an application. This is invoked on  all the cores that
+*                        exist after the set of cores being requesed are
+*                        removed.
+* shutdown_done_callback before the application is shutdown this callback is
+*                        invoked on all the cores that are part of the app.
+* unplug_callback        before the cores are unplugged this callback is invoked
+*                        only on the cores that are being unlpuuged.
+*/
+typedef struct cvmx_app_hotplug_callbacks
+{
+    void (*hotplug_start)(void *ptr);
+    void (*cores_added_callback) (uint32_t  ,void *ptr);
+    void (*cores_removed_callback) (uint32_t,void *ptr);
+    void (*shutdown_callback) (void *ptr);
+    void (*unplug_core_callback) (void *ptr);
+} cvmx_app_hotplug_callbacks_t;
+
+/* The size of this struct should be a fixed size of 1024 bytes.
+   Additional members should be added towards the end of the
+   strcuture by adjusting the size of padding */
 typedef struct cvmx_app_hotplug_info
 {
-   char app_name[CVMX_APP_HOTPLUG_MAX_APPNAME_LEN];
-   uint32_t coremask;
-   uint32_t volatile hotplug_activated_coremask;
-   int32_t  valid;
-   int32_t volatile shutdown_done;
-   uint64_t shutdown_callback;
-   uint64_t data;
+    char app_name[CVMX_APP_HOTPLUG_MAX_APPNAME_LEN];
+    uint32_t coremask;
+    uint32_t volatile hotplug_activated_coremask;
+    int32_t  valid;
+    int32_t volatile shutdown_done;
+    uint64_t shutdown_callback;
+    uint64_t unplug_callback;
+    uint64_t cores_added_callback;
+    uint64_t cores_removed_callback;
+    uint64_t hotplug_start;
+    uint64_t data;
+    uint32_t volatile hplugged_cores;
+    uint32_t shutdown_cores;
+    uint32_t app_shutdown;
+    uint32_t unplug_cores;
+    uint32_t padding[172];
 } cvmx_app_hotplug_info_t;
 
 struct cvmx_app_hotplug_global
 {
    uint32_t avail_coremask;
    cvmx_app_hotplug_info_t hotplug_info_array[CVMX_APP_HOTPLUG_MAX_APPS];
+   uint32_t version;
+   cvmx_spinlock_t hotplug_global_lock;
+   int app_under_boot;
+   int app_under_shutdown;
 };
-
 typedef struct cvmx_app_hotplug_global cvmx_app_hotplug_global_t;
 
+int is_core_being_hot_plugged(void);
+int is_app_being_booted_or_shutdown(void);
+void set_app_unber_boot(int val);
+void set_app_under_shutdown(int val);
 int cvmx_app_hotplug_shutdown_request(uint32_t, int);
+int cvmx_app_hotplug_unplug_cores(int index, uint32_t coremask, int wait);
 cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info(uint32_t);
+int cvmx_app_hotplug_get_index(uint32_t coremask);
+cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info_at_index(int index);
+int is_app_hotpluggable(int index);
+int cvmx_app_hotplug_call_add_cores_callback(int index);
 #ifndef CVMX_BUILD_FOR_LINUX_USER
 int cvmx_app_hotplug_register(void(*)(void*), void*);
+int cvmx_app_hotplug_register_cb(cvmx_app_hotplug_callbacks_t *, void*, int);
 int cvmx_app_hotplug_activate(void);
+void cvmx_app_hotplug_core_shutdown(void);
 void cvmx_app_hotplug_shutdown_disable(void);
 void cvmx_app_hotplug_shutdown_enable(void);
 #endif
@@ -96,7 +148,7 @@ void cvmx_app_hotplug_shutdown_enable(void);
 #define CVMX_APP_HOTPLUG_INFO_REGION_SIZE  sizeof(cvmx_app_hotplug_global_t)
 #define CVMX_APP_HOTPLUG_INFO_REGION_NAME  "cvmx-app-hotplug-block"
 
-#ifdef	__cplusplus
+#ifdef  __cplusplus
 }
 #endif
 
diff --git a/sys/contrib/octeon-sdk/cvmx-app-init-linux.c b/sys/contrib/octeon-sdk/cvmx-app-init-linux.c
index 73726df..aeb42cb 100644
--- a/sys/contrib/octeon-sdk/cvmx-app-init-linux.c
+++ b/sys/contrib/octeon-sdk/cvmx-app-init-linux.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -61,7 +61,7 @@
  * -# Most hardware can only be initialized once. Unless you're very careful,
  *      this also means you Linux application can only run once.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70129 $<hr>
  *
  */
 #define _GNU_SOURCE
@@ -88,6 +88,7 @@
 #include "cvmx-coremask.h"
 #include "cvmx-spinlock.h"
 #include "cvmx-bootmem.h"
+#include "cvmx-helper-cfg.h"
 
 int octeon_model_version_check(uint32_t chip_id);
 
@@ -326,7 +327,6 @@ int main(int argc, const char *argv[])
     int firstcore = 0;
 
     cvmx_linux_enable_xkphys_access(0);
-
     cvmx_sysinfo_linux_userspace_initialize();
 
     if (sizeof(void*) == 4)
@@ -349,6 +349,10 @@ int main(int argc, const char *argv[])
     /* Check to make sure the Chip version matches the configured version */
     octeon_model_version_check(cvmx_get_proc_id());
 
+    /* Initialize configuration to set bpid, pkind, pko_port for all the 
+       available ports connected. */
+    __cvmx_helper_cfg_init();
+
     /* Get the list of logical cpus we should run on */
     if (sched_getaffinity(0, sizeof(cpumask), (cpu_set_t*)&cpumask))
     {
@@ -362,7 +366,7 @@ int main(int argc, const char *argv[])
 
     /* Get the lowest logical cpu */
     firstcore = ffsl(cpumask) - 1;
-    cpumask ^= (1<<(firstcore));
+    cpumask ^= (1ull<<(firstcore));
     while (1)
     {
         if (cpumask == 0)
@@ -373,9 +377,9 @@ int main(int argc, const char *argv[])
         }
         cpu = ffsl(cpumask) - 1;
         /* Turn off the bit for this CPU number. We've counted him */
-        cpumask ^= (1<<cpu);
+        cpumask ^= (1ull<<cpu);
         /* Increment the number of CPUs running this app */
-         cvmx_atomic_add32(&pending_fork, 1);
+        cvmx_atomic_add32(&pending_fork, 1);
         /* Flush all IO streams before the fork. Otherwise any buffered
            data in the C library will be duplicated. This results in
            duplicate output from a single print */
@@ -406,7 +410,9 @@ int main(int argc, const char *argv[])
     system_info->core_mask |= 1<<cvmx_get_core_num();
     cvmx_atomic_add32(&pending_fork, -1);
     if (cvmx_atomic_get32(&pending_fork) == 0)
+    {
         cvmx_dprintf("Active coremask = 0x%x\n", system_info->core_mask);
+    }
     if (firstcpu)
         system_info->init_core = cvmx_get_core_num();
     cvmx_spinlock_unlock(&mask_lock);
diff --git a/sys/contrib/octeon-sdk/cvmx-app-init.c b/sys/contrib/octeon-sdk/cvmx-app-init.c
index 885e36e..75e5156 100644
--- a/sys/contrib/octeon-sdk/cvmx-app-init.c
+++ b/sys/contrib/octeon-sdk/cvmx-app-init.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -47,6 +47,7 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
+#include "executive-config.h"
 #include "cvmx-config.h"
 #include "cvmx.h"
 #include "cvmx-spinlock.h"
@@ -60,8 +61,12 @@
 #include "cvmx-ebt3000.h"
 #include "cvmx-sim-magic.h"
 #include "cvmx-debug.h"
-#include "../../bootloader/u-boot/include/octeon_mem_map.h"
-
+#include "cvmx-qlm.h"
+#include "cvmx-scratch.h"
+#include "cvmx-helper-cfg.h"
+#include "cvmx-helper-jtag.h"
+#include <octeon_mem_map.h>
+#include "libfdt.h"
 int cvmx_debug_uart = -1;
 
 /**
@@ -184,6 +189,20 @@ static void process_boot_desc_ver_6(octeon_boot_descriptor_t *app_desc_ptr, cvmx
                (int)cvmx_bootinfo_ptr->major_version, (int)cvmx_bootinfo_ptr->minor_version);
         exit(-1);
     }
+    if ((cvmx_bootinfo_ptr->minor_version >= 3) && (cvmx_bootinfo_ptr->fdt_addr != 0))
+    {
+        sys_info_ptr->fdt_addr = UNMAPPED_PTR(cvmx_bootinfo_ptr->fdt_addr);
+        if (fdt_check_header((const void *)sys_info_ptr->fdt_addr))
+        {
+            printf("ERROR : Corrupt Device Tree.\n");
+            exit(-1);
+        }
+        printf("Using device tree\n");
+    }
+    else
+    {
+        sys_info_ptr->fdt_addr = 0;
+    }
 }
 
 
@@ -211,18 +230,18 @@ static void process_break_interrupt(int irq_number, uint64_t registers[32], void
         {
             register uint64_t tmp;
 
-	    /* Wait for an another Control-C if right now we have no
-	       access to the console.  After this point we hold the
-	       lock and use a different lock to synchronize between
-	       the memfile dumps from different cores.  As a
-	       consequence regular printfs *don't* work after this
-	       point! */
-	    if (__octeon_uart_trylock () == 1)
-		return;
+            /* Wait for an another Control-C if right now we have no
+               access to the console.  After this point we hold the
+               lock and use a different lock to synchronize between
+               the memfile dumps from different cores.  As a
+               consequence regular printfs *don't* work after this
+               point! */
+            if (__octeon_uart_trylock () == 1)
+                return;
 
             /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also
-	       set the MCD0 to be not masked by this core so we know
-	       the signal is received by someone */
+               set the MCD0 to be not masked by this core so we know
+               the signal is received by someone */
             asm volatile (
                 "dmfc0 %0, $22\n"
                 "ori   %0, %0, 0x1110\n"
@@ -270,6 +289,7 @@ char octeon_rev_signature[] =
     "Compiled for Octeon processor id: "OMS;
 #endif
 
+#define OCTEON_BL_FLAG_HPLUG_CORES (1 << 6)
 void __cvmx_app_init(uint64_t app_desc_addr)
 {
     /* App descriptor used by bootloader */
@@ -279,8 +299,16 @@ void __cvmx_app_init(uint64_t app_desc_addr)
     cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
     int breakflag = 0;
 
+    //printf("coremask=%08x flags=%08x \n", app_desc_ptr->core_mask, app_desc_ptr->flags);
     if (cvmx_coremask_first_core(app_desc_ptr->core_mask))
     {
+        /* Intialize the bootmem allocator with the descriptor that was provided by
+        * the bootloader
+        * IMPORTANT:  All printfs must happen after this since PCI console uses named
+        * blocks.
+        */
+        cvmx_bootmem_init(CASTPTR(cvmx_bootinfo_t, app_desc_ptr->cvmx_desc_vaddr)->phy_mem_desc_addr);
+
         /* do once per application setup  */
         if (app_desc_ptr->desc_version < 6)
         {
@@ -297,8 +325,34 @@ void __cvmx_app_init(uint64_t app_desc_addr)
             process_boot_desc_ver_6(app_desc_ptr,sys_info_ptr);
 
         }
+
+        /*
+         * set up the feature map and config.
+         */
+        octeon_feature_init();
+
+        __cvmx_helper_cfg_init();
     }
-    cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
+    /* The flags varibale get copied over at some places and tracing the origins
+       found that
+       ** In octeon_setup_boot_desc_block
+         . cvmx_bootinfo_array[core].flags is initialized and the various bits are set
+         . cvmx_bootinfo_array[core].flags gets copied to  boot_desc[core].flags
+         . Then boot_desc then get copied over to the end of the application heap and
+            boot_info_block_array[core].boot_descr_addr is set to point to the boot_desc
+            in heap.
+       ** In start_app boot_vect->boot_info_addr->boot_desc_addr is referenced and passed on
+       to octeon_setup_crt0_tlb() and this puts it into r16
+       ** In ctr0.S of the toolchain r16 is picked up and passed on as a parameter to
+       __cvmx_app_init
+
+       Note : boot_vect->boot_info_addr points to  boot_info_block_array[core] and this
+       pointer is setup in octeon_setup_boot_vector()
+    */
+
+    if (!(app_desc_ptr->flags & OCTEON_BL_FLAG_HPLUG_CORES))
+        cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
+
 
     breakflag = sys_info_ptr->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_BREAK;
 
@@ -311,20 +365,12 @@ void __cvmx_app_init(uint64_t app_desc_addr)
         /* Make sure we can properly run on this chip */
         octeon_model_version_check(chip_id);
     }
-
     cvmx_interrupt_initialize();
-
     if (cvmx_coremask_first_core(sys_info_ptr->core_mask))
     {
         int break_uart = 0;
         unsigned int i;
 
-        /* Intialize the bootmem allocator with the descriptor that was provided by
-         * the bootloader
-         * IMPORTANT:  All printfs must happen after this since PCI console uses named
-         * blocks.
-         */
-        cvmx_bootmem_init(sys_info_ptr->phy_mem_desc_addr);
         if (breakflag && cvmx_debug_booted())
         {
             printf("ERROR: Using debug and break together in not supported.\n");
@@ -350,8 +396,8 @@ void __cvmx_app_init(uint64_t app_desc_addr)
             cvmx_uart_enable_intr(break_uart, process_break_interrupt);
         }
     }
-
-    cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
+    if ( !(app_desc_ptr->flags & OCTEON_BL_FLAG_HPLUG_CORES))
+         cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
 
     /* Clear BEV now that we have installed exception handlers. */
     uint64_t tmp;
@@ -375,13 +421,13 @@ void __cvmx_app_init(uint64_t app_desc_addr)
         "dmtc0 %0, $22, 0\n" : "=r" (tmp));
 
     CVMX_SYNC;
-
     /* Now intialize the debug exception handler as BEV is cleared. */
-    if (!breakflag)
+    if ((!breakflag) && (!(app_desc_ptr->flags & OCTEON_BL_FLAG_HPLUG_CORES)))
         cvmx_debug_init();
 
     /* Synchronise all cores at this point */
-    cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
+     if ( !(app_desc_ptr->flags & OCTEON_BL_FLAG_HPLUG_CORES))
+         cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
 
 }
 
@@ -396,11 +442,11 @@ int cvmx_user_app_init(void)
 
     /* Put message on LED display */
     if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)
-      ebt3000_str_write("CVMX    ");
+        ebt3000_str_write("CVMX    ");
 
     /* Check BIST results for COP0 registers, some values only meaningful in pass 2 */
     CVMX_MF_CACHE_ERR(bist_val);
-    mask = (1ULL<<32) | (1ULL<<33) | (1ULL<<34) | (1ULL<<35) | (1ULL<<36);
+    mask = (0x3fULL<<32); // Icache;BHT;AES;HSH/GFM;LRU;register file
     bist_val &= mask;
     if (bist_val)
     {
@@ -429,6 +475,17 @@ int cvmx_user_app_init(void)
     }
     CVMX_MT_CVM_MEM_CTL(tmp);
 
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_X))
+    {
+        /* Clear the lines of scratch memory configured, for
+        ** 63XX pass 2 errata Core-15169. */
+        uint64_t addr;
+        unsigned  num_lines;
+        CVMX_MF_CVM_MEM_CTL(tmp);
+        num_lines = tmp & 0x3f;
+        for (addr = 0; addr < CVMX_CACHE_LINE_SIZE * num_lines; addr += 8)
+            cvmx_scratch_write64(addr, 0);
+    }
 
 #if CVMX_USE_1_TO_1_TLB_MAPPINGS
 
@@ -475,7 +532,7 @@ int cvmx_user_app_init(void)
                 printf("ERROR adding 1-1 TLB mapping for address 0x%llx\n", (unsigned long long)base_addr);
                 /* Exit from here, as expected memory mappings aren't set
                    up if this fails */
-		exit(-1);
+                exit(-1);
             }
         }
     }
@@ -507,6 +564,10 @@ int cvmx_user_app_init(void)
     cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
     cvmx_bootmem_init(sys_info_ptr->phy_mem_desc_addr);
 
+    /* Initialize QLM and JTAG settings. Also apply any erratas. */
+    if (cvmx_coremask_first_core(cvmx_sysinfo_get()->core_mask))
+        cvmx_qlm_init();
+
     return(0);
 }
 
@@ -516,7 +577,7 @@ void __cvmx_app_exit(void)
 
     if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
     {
-	CVMX_BREAK;
+        CVMX_BREAK;
     }
     /* Hang forever, until more appropriate stand alone simple executive
        exit() is implemented */
diff --git a/sys/contrib/octeon-sdk/cvmx-app-init.h b/sys/contrib/octeon-sdk/cvmx-app-init.h
index 2912cfd..e570b45 100644
--- a/sys/contrib/octeon-sdk/cvmx-app-init.h
+++ b/sys/contrib/octeon-sdk/cvmx-app-init.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -46,7 +46,7 @@
  * @file
  * Header file for simple executive application initialization.  This defines
  * part of the ABI between the bootloader and the application.
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70327 $<hr>
  *
  */
 
@@ -62,7 +62,7 @@ extern "C" {
 ** from the bootloader to the application.  This is versioned so that applications
 ** can properly handle multiple bootloader versions. */
 #define CVMX_BOOTINFO_MAJ_VER 1
-#define CVMX_BOOTINFO_MIN_VER 2
+#define CVMX_BOOTINFO_MIN_VER 3
 
 
 #if (CVMX_BOOTINFO_MAJ_VER == 1)
@@ -76,6 +76,7 @@ extern "C" {
 ** to 0.
 */
 struct cvmx_bootinfo {
+#ifdef __BIG_ENDIAN_BITFIELD
     uint32_t major_version;
     uint32_t minor_version;
 
@@ -120,8 +121,70 @@ struct cvmx_bootinfo {
     uint32_t config_flags;  /**< flags indicating various configuration options.  These flags supercede
                             ** the 'flags' variable and should be used instead if available */
 #endif
+#if (CVMX_BOOTINFO_MIN_VER >= 3)
+    uint64_t fdt_addr;  /**< Address of the OF Flattened Device Tree structure describing the board. */
+#endif
+#else /* __BIG_ENDIAN */
+	/*
+	 * Little-Endian: When the CPU mode is switched to
+	 * little-endian, the view of the structure has some of the
+	 * fields swapped.
+	 */
+	uint32_t minor_version;
+	uint32_t major_version;
+
+	uint64_t stack_top;
+	uint64_t heap_base;
+	uint64_t heap_end;
+	uint64_t desc_vaddr;
+
+	uint32_t stack_size;
+	uint32_t exception_base_addr;
+
+	uint32_t core_mask;
+	uint32_t flags;
+
+	uint32_t phy_mem_desc_addr;
+	uint32_t dram_size;
+
+	uint32_t eclock_hz;
+	uint32_t debugger_flags_base_addr;
+
+	uint32_t reserved0;
+	uint32_t dclock_hz;
+
+	uint8_t reserved3;
+	uint8_t reserved2;
+	uint16_t reserved1;
+	uint8_t board_rev_minor;
+	uint8_t board_rev_major;
+	uint16_t board_type;
+
+	union cvmx_bootinfo_scramble {
+		/* Must byteswap these four words so that...*/
+		uint64_t s[4];
+		/* ... this strucure has the proper data arrangement. */
+		struct {
+			char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN];
+			uint8_t mac_addr_base[6];
+			uint8_t mac_addr_count;
+			uint8_t pad[5];
+		} le;
+	} scramble1;
 
-
+#if (CVMX_BOOTINFO_MIN_VER >= 1)
+	uint64_t compact_flash_common_base_addr;
+	uint64_t compact_flash_attribute_base_addr;
+	uint64_t led_display_base_addr;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 2)
+	uint32_t config_flags;
+	uint32_t dfa_ref_clock_hz;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 3)
+	uint64_t fdt_addr;
+#endif
+#endif
 };
 
 typedef struct cvmx_bootinfo cvmx_bootinfo_t;
@@ -145,7 +208,7 @@ enum cvmx_board_types_enum {
     CVMX_BOARD_TYPE_EBT3000        =  2,
     CVMX_BOARD_TYPE_KODAMA         =  3,
     CVMX_BOARD_TYPE_NIAGARA        =  4,	/* Obsolete, no longer supported */
-    CVMX_BOARD_TYPE_NAC38          =  5,	/* formerly NAO38 */
+    CVMX_BOARD_TYPE_NAC38          =  5,	/* Obsolete, no longer supported */
     CVMX_BOARD_TYPE_THUNDER        =  6,
     CVMX_BOARD_TYPE_TRANTOR        =  7,	/* Obsolete, no longer supported */
     CVMX_BOARD_TYPE_EBH3000        =  8,
@@ -178,7 +241,18 @@ enum cvmx_board_types_enum {
     CVMX_BOARD_TYPE_LANAI2_G       = 35,
     CVMX_BOARD_TYPE_EBT5810        = 36,
     CVMX_BOARD_TYPE_NIC10E         = 37,
+    CVMX_BOARD_TYPE_EP6300C        = 38,
+    CVMX_BOARD_TYPE_EBB6800        = 39,
+    CVMX_BOARD_TYPE_NIC4E          = 40,
+    CVMX_BOARD_TYPE_NIC2E          = 41,
+    CVMX_BOARD_TYPE_EBB6600        = 42,
+    CVMX_BOARD_TYPE_REDWING        = 43,
+    CVMX_BOARD_TYPE_NIC68_4        = 44,
+    CVMX_BOARD_TYPE_NIC10E_66      = 45,
+    CVMX_BOARD_TYPE_EBB6100        = 46,
+    CVMX_BOARD_TYPE_EVB7100        = 47,
     CVMX_BOARD_TYPE_MAX,
+    /* NOTE:  256-257 are being used by a customer. */
 
     /* The range from CVMX_BOARD_TYPE_MAX to CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved
     ** for future SDK use. */
@@ -239,7 +313,7 @@ enum cvmx_board_types_enum {
     CVMX_BOARD_TYPE_MODULE_EBB5600_QLM1 = 30008,
     CVMX_BOARD_TYPE_MODULE_EBB5600_QLM2 = 30009,
     CVMX_BOARD_TYPE_MODULE_EBB5600_QLM3 = 30010,
-    CVMX_BOARD_TYPE_MODULE_MAX          = 31000,
+    CVMX_BOARD_TYPE_MODULE_MAX          = 31000
 
     /* The remaining range is reserved for future use. */
 };
@@ -247,7 +321,7 @@ enum cvmx_chip_types_enum {
     CVMX_CHIP_TYPE_NULL = 0,
     CVMX_CHIP_SIM_TYPE_DEPRECATED = 1,
     CVMX_CHIP_TYPE_OCTEON_SAMPLE = 2,
-    CVMX_CHIP_TYPE_MAX,
+    CVMX_CHIP_TYPE_MAX
 };
 
 /* Compatability alias for NAC38 name change, planned to be removed from SDK 1.7 */
@@ -297,6 +371,16 @@ static inline const char *cvmx_board_type_to_string(enum cvmx_board_types_enum t
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_G)
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5810)
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EP6300C)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6800)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC4E)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC2E)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6600)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_REDWING)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC68_4)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E_66)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6100)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EVB7100)
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
 
         /* Customer boards listed here */
diff --git a/sys/contrib/octeon-sdk/cvmx-asm.h b/sys/contrib/octeon-sdk/cvmx-asm.h
index 2377bb7..a30e1c0 100644
--- a/sys/contrib/octeon-sdk/cvmx-asm.h
+++ b/sys/contrib/octeon-sdk/cvmx-asm.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,13 +48,15 @@
  *
  * This is file defines ASM primitives for the executive.
 
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  *
  */
 #ifndef __CVMX_ASM_H__
 #define __CVMX_ASM_H__
 
+#define CVMX_MAX_CORES  (32)
+
 #define COP0_INDEX	$0,0	/* TLB read/write index */
 #define COP0_RANDOM	$1,0	/* TLB random index */
 #define COP0_ENTRYLO0	$2,0	/* TLB entryLo0 */
@@ -111,8 +113,6 @@
    things under !__ASSEMBLER__.  */
 #ifndef __ASSEMBLER__
 
-#include "octeon-model.h"
-
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -121,10 +121,9 @@ extern "C" {
 #define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
 #define CVMX_TMP_STR2(x) #x
 
-#if !OCTEON_IS_COMMON_BINARY()
- #if CVMX_COMPILED_FOR(OCTEON_CN63XX)
-   #define CVMX_CAVIUM_OCTEON2
- #endif
+/* Since sync is required for Octeon2. */
+#ifdef _MIPS_ARCH_OCTEON2
+#define CVMX_CAVIUM_OCTEON2   1
 #endif
 
 /* other useful stuff */
@@ -139,9 +138,7 @@ extern "C" {
 #endif /* CVMX_CAVIUM_OCTEON2 */
 
 #ifdef __OCTEON__
-    #define CVMX_SYNCIO asm volatile ("nop")   /* Deprecated, will be removed in future release */
     #define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : :"memory")
-    #define CVMX_SYNCIOALL asm volatile ("nop")   /* Deprecated, will be removed in future release */
     /* We actually use two syncw instructions in a row when we need a write
         memory barrier. This is because the CN3XXX series of Octeons have
         errata Core-401. This can cause a single syncw to not enforce
@@ -187,9 +184,7 @@ extern "C" {
 #endif
 #else /* !__OCTEON__ */
     /* Not using a Cavium compiler, always use the slower sync so the assembler stays happy */
-    #define CVMX_SYNCIO asm volatile ("nop")   /* Deprecated, will be removed in future release */
     #define CVMX_SYNCIOBDMA asm volatile ("sync" : : :"memory")
-    #define CVMX_SYNCIOALL asm volatile ("nop")   /* Deprecated, will be removed in future release */
     #define CVMX_SYNCW asm volatile ("sync" : : :"memory")
     #define CVMX_SYNCWS CVMX_SYNCW
     #define CVMX_SYNCS  CVMX_SYNC
diff --git a/sys/contrib/octeon-sdk/cvmx-asx0-defs.h b/sys/contrib/octeon-sdk/cvmx-asx0-defs.h
index 42115db..f87c2fd 100644
--- a/sys/contrib/octeon-sdk/cvmx-asx0-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-asx0-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_ASX0_TYPEDEFS_H__
-#define __CVMX_ASX0_TYPEDEFS_H__
+#ifndef __CVMX_ASX0_DEFS_H__
+#define __CVMX_ASX0_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_ASX0_DBG_DATA_DRV CVMX_ASX0_DBG_DATA_DRV_FUNC()
@@ -81,12 +81,10 @@ static inline uint64_t CVMX_ASX0_DBG_DATA_ENABLE_FUNC(void)
  * ASX_DBG_DATA_DRV
  *
  */
-union cvmx_asx0_dbg_data_drv
-{
+union cvmx_asx0_dbg_data_drv {
 	uint64_t u64;
-	struct cvmx_asx0_dbg_data_drv_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asx0_dbg_data_drv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t pctl                         : 5;  /**< These bits control the driving strength of the dbg
                                                          interface. */
@@ -98,9 +96,8 @@ union cvmx_asx0_dbg_data_drv
 	uint64_t reserved_9_63                : 55;
 #endif
 	} s;
-	struct cvmx_asx0_dbg_data_drv_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asx0_dbg_data_drv_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t pctl                         : 4;  /**< These bits control the driving strength of the dbg
                                                          interface. */
@@ -124,12 +121,10 @@ typedef union cvmx_asx0_dbg_data_drv cvmx_asx0_dbg_data_drv_t;
  * ASX_DBG_DATA_ENABLE
  *
  */
-union cvmx_asx0_dbg_data_enable
-{
+union cvmx_asx0_dbg_data_enable {
 	uint64_t u64;
-	struct cvmx_asx0_dbg_data_enable_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asx0_dbg_data_enable_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t en                           : 1;  /**< A 1->0 transistion, turns the dbg interface OFF. */
 #else
diff --git a/sys/contrib/octeon-sdk/cvmx-asxx-defs.h b/sys/contrib/octeon-sdk/cvmx-asxx-defs.h
index 0791d1b..29c0de3 100644
--- a/sys/contrib/octeon-sdk/cvmx-asxx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-asxx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_ASXX_TYPEDEFS_H__
-#define __CVMX_ASXX_TYPEDEFS_H__
+#ifndef __CVMX_ASXX_DEFS_H__
+#define __CVMX_ASXX_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_ASXX_GMII_RX_CLK_SET(unsigned long block_id)
@@ -395,12 +395,10 @@ static inline uint64_t CVMX_ASXX_TX_PRT_EN(unsigned long block_id)
  * ASX_GMII_RX_CLK_SET = GMII Clock delay setting
  *
  */
-union cvmx_asxx_gmii_rx_clk_set
-{
+union cvmx_asxx_gmii_rx_clk_set {
 	uint64_t u64;
-	struct cvmx_asxx_gmii_rx_clk_set_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_gmii_rx_clk_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t setting                      : 5;  /**< Setting to place on the RXCLK (GMII receive clk)
                                                          delay line.  The intrinsic delay can range from
@@ -422,12 +420,10 @@ typedef union cvmx_asxx_gmii_rx_clk_set cvmx_asxx_gmii_rx_clk_set_t;
  * ASX_GMII_RX_DAT_SET = GMII Clock delay setting
  *
  */
-union cvmx_asxx_gmii_rx_dat_set
-{
+union cvmx_asxx_gmii_rx_dat_set {
 	uint64_t u64;
-	struct cvmx_asxx_gmii_rx_dat_set_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_gmii_rx_dat_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t setting                      : 5;  /**< Setting to place on the RXD (GMII receive data)
                                                          delay lines.  The intrinsic delay can range from
@@ -449,12 +445,10 @@ typedef union cvmx_asxx_gmii_rx_dat_set cvmx_asxx_gmii_rx_dat_set_t;
  * ASX_INT_EN = Interrupt Enable
  *
  */
-union cvmx_asxx_int_en
-{
+union cvmx_asxx_int_en {
 	uint64_t u64;
-	struct cvmx_asxx_int_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t txpsh                        : 4;  /**< TX FIFO overflow on RMGII port */
 	uint64_t txpop                        : 4;  /**< TX FIFO underflow on RMGII port */
@@ -466,9 +460,8 @@ union cvmx_asxx_int_en
 	uint64_t reserved_12_63               : 52;
 #endif
 	} s;
-	struct cvmx_asxx_int_en_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_int_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t txpsh                        : 3;  /**< TX FIFO overflow on RMGII port */
 	uint64_t reserved_7_7                 : 1;
@@ -499,12 +492,10 @@ typedef union cvmx_asxx_int_en cvmx_asxx_int_en_t;
  * ASX_INT_REG = Interrupt Register
  *
  */
-union cvmx_asxx_int_reg
-{
+union cvmx_asxx_int_reg {
 	uint64_t u64;
-	struct cvmx_asxx_int_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t txpsh                        : 4;  /**< TX FIFO overflow on RMGII port */
 	uint64_t txpop                        : 4;  /**< TX FIFO underflow on RMGII port */
@@ -516,9 +507,8 @@ union cvmx_asxx_int_reg
 	uint64_t reserved_12_63               : 52;
 #endif
 	} s;
-	struct cvmx_asxx_int_reg_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_int_reg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t txpsh                        : 3;  /**< TX FIFO overflow on RMGII port */
 	uint64_t reserved_7_7                 : 1;
@@ -549,12 +539,10 @@ typedef union cvmx_asxx_int_reg cvmx_asxx_int_reg_t;
  * ASX_MII_RX_DAT_SET = GMII Clock delay setting
  *
  */
-union cvmx_asxx_mii_rx_dat_set
-{
+union cvmx_asxx_mii_rx_dat_set {
 	uint64_t u64;
-	struct cvmx_asxx_mii_rx_dat_set_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_mii_rx_dat_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t setting                      : 5;  /**< Setting to place on the RXD (MII receive data)
                                                          delay lines.  The intrinsic delay can range from
@@ -575,12 +563,10 @@ typedef union cvmx_asxx_mii_rx_dat_set cvmx_asxx_mii_rx_dat_set_t;
  * ASX_PRT_LOOP = Internal Loopback mode - TX FIFO output goes into RX FIFO (and maybe pins)
  *
  */
-union cvmx_asxx_prt_loop
-{
+union cvmx_asxx_prt_loop {
 	uint64_t u64;
-	struct cvmx_asxx_prt_loop_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_prt_loop_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t ext_loop                     : 4;  /**< External Loopback Enable
                                                          0 = No Loopback (TX FIFO is filled by RMGII)
@@ -602,9 +588,8 @@ union cvmx_asxx_prt_loop
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
-	struct cvmx_asxx_prt_loop_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_prt_loop_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t ext_loop                     : 3;  /**< External Loopback Enable
                                                          0 = No Loopback (TX FIFO is filled by RMGII)
@@ -646,12 +631,10 @@ typedef union cvmx_asxx_prt_loop cvmx_asxx_prt_loop_t;
  * ASX_RLD_BYPASS
  *
  */
-union cvmx_asxx_rld_bypass
-{
+union cvmx_asxx_rld_bypass {
 	uint64_t u64;
-	struct cvmx_asxx_rld_bypass_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_bypass_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t bypass                       : 1;  /**< When set, the rld_dll setting is bypassed with
                                                          ASX_RLD_BYPASS_SETTING */
@@ -673,12 +656,10 @@ typedef union cvmx_asxx_rld_bypass cvmx_asxx_rld_bypass_t;
  * ASX_RLD_BYPASS_SETTING
  *
  */
-union cvmx_asxx_rld_bypass_setting
-{
+union cvmx_asxx_rld_bypass_setting {
 	uint64_t u64;
-	struct cvmx_asxx_rld_bypass_setting_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_bypass_setting_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t setting                      : 5;  /**< The rld_dll setting bypass value */
 #else
@@ -699,12 +680,10 @@ typedef union cvmx_asxx_rld_bypass_setting cvmx_asxx_rld_bypass_setting_t;
  * ASX_RLD_COMP
  *
  */
-union cvmx_asxx_rld_comp
-{
+union cvmx_asxx_rld_comp {
 	uint64_t u64;
-	struct cvmx_asxx_rld_comp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_comp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t pctl                         : 5;  /**< PCTL Compensation Value
                                                          These bits reflect the computed compensation
@@ -717,9 +696,8 @@ union cvmx_asxx_rld_comp
 	uint64_t reserved_9_63                : 55;
 #endif
 	} s;
-	struct cvmx_asxx_rld_comp_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_comp_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t pctl                         : 4;  /**< These bits reflect the computed compensation
                                                          values from the built-in compensation circuit. */
@@ -743,12 +721,10 @@ typedef union cvmx_asxx_rld_comp cvmx_asxx_rld_comp_t;
  * ASX_RLD_DATA_DRV
  *
  */
-union cvmx_asxx_rld_data_drv
-{
+union cvmx_asxx_rld_data_drv {
 	uint64_t u64;
-	struct cvmx_asxx_rld_data_drv_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_data_drv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t pctl                         : 4;  /**< These bits specify a driving strength (positive
                                                          integer) for the RLD I/Os when the built-in
@@ -775,12 +751,10 @@ typedef union cvmx_asxx_rld_data_drv cvmx_asxx_rld_data_drv_t;
  * ASX_RLD_FCRAM_MODE
  *
  */
-union cvmx_asxx_rld_fcram_mode
-{
+union cvmx_asxx_rld_fcram_mode {
 	uint64_t u64;
-	struct cvmx_asxx_rld_fcram_mode_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_fcram_mode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t mode                         : 1;  /**< Memory Mode
                                                          - 0: RLDRAM
@@ -801,12 +775,10 @@ typedef union cvmx_asxx_rld_fcram_mode cvmx_asxx_rld_fcram_mode_t;
  * ASX_RLD_NCTL_STRONG
  *
  */
-union cvmx_asxx_rld_nctl_strong
-{
+union cvmx_asxx_rld_nctl_strong {
 	uint64_t u64;
-	struct cvmx_asxx_rld_nctl_strong_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_nctl_strong_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t nctl                         : 5;  /**< Duke's drive control */
 #else
@@ -827,12 +799,10 @@ typedef union cvmx_asxx_rld_nctl_strong cvmx_asxx_rld_nctl_strong_t;
  * ASX_RLD_NCTL_WEAK
  *
  */
-union cvmx_asxx_rld_nctl_weak
-{
+union cvmx_asxx_rld_nctl_weak {
 	uint64_t u64;
-	struct cvmx_asxx_rld_nctl_weak_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_nctl_weak_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t nctl                         : 5;  /**< UNUSED (not needed for CN58XX) */
 #else
@@ -853,12 +823,10 @@ typedef union cvmx_asxx_rld_nctl_weak cvmx_asxx_rld_nctl_weak_t;
  * ASX_RLD_PCTL_STRONG
  *
  */
-union cvmx_asxx_rld_pctl_strong
-{
+union cvmx_asxx_rld_pctl_strong {
 	uint64_t u64;
-	struct cvmx_asxx_rld_pctl_strong_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_pctl_strong_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t pctl                         : 5;  /**< Duke's drive control */
 #else
@@ -879,12 +847,10 @@ typedef union cvmx_asxx_rld_pctl_strong cvmx_asxx_rld_pctl_strong_t;
  * ASX_RLD_PCTL_WEAK
  *
  */
-union cvmx_asxx_rld_pctl_weak
-{
+union cvmx_asxx_rld_pctl_weak {
 	uint64_t u64;
-	struct cvmx_asxx_rld_pctl_weak_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_pctl_weak_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t pctl                         : 5;  /**< UNUSED (not needed for CN58XX) */
 #else
@@ -905,12 +871,10 @@ typedef union cvmx_asxx_rld_pctl_weak cvmx_asxx_rld_pctl_weak_t;
  * ASX_RLD_SETTING
  *
  */
-union cvmx_asxx_rld_setting
-{
+union cvmx_asxx_rld_setting {
 	uint64_t u64;
-	struct cvmx_asxx_rld_setting_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_setting_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t dfaset                       : 5;  /**< RLD ClkGen DLL Setting(debug) */
 	uint64_t dfalag                       : 1;  /**< RLD ClkGen DLL Lag Error(debug) */
@@ -926,9 +890,8 @@ union cvmx_asxx_rld_setting
 	uint64_t reserved_13_63               : 51;
 #endif
 	} s;
-	struct cvmx_asxx_rld_setting_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_setting_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t setting                      : 5;  /**< This is the read-only true rld dll_setting. */
 #else
@@ -982,12 +945,10 @@ typedef union cvmx_asxx_rld_setting cvmx_asxx_rld_setting_t;
  *    1.25            24
  *    1.3             25
  */
-union cvmx_asxx_rx_clk_setx
-{
+union cvmx_asxx_rx_clk_setx {
 	uint64_t u64;
-	struct cvmx_asxx_rx_clk_setx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rx_clk_setx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t setting                      : 5;  /**< Setting to place on the open-loop RXC delay line */
 #else
@@ -1011,12 +972,10 @@ typedef union cvmx_asxx_rx_clk_setx cvmx_asxx_rx_clk_setx_t;
  * ASX_RX_PRT_EN = RGMII Port Enable
  *
  */
-union cvmx_asxx_rx_prt_en
-{
+union cvmx_asxx_rx_prt_en {
 	uint64_t u64;
-	struct cvmx_asxx_rx_prt_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rx_prt_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t prt_en                       : 4;  /**< Port enable.  Must be set for Octane to receive
                                                          RMGII traffic.  When this bit clear on a given
@@ -1027,9 +986,8 @@ union cvmx_asxx_rx_prt_en
 	uint64_t reserved_4_63                : 60;
 #endif
 	} s;
-	struct cvmx_asxx_rx_prt_en_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rx_prt_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t prt_en                       : 3;  /**< Port enable.  Must be set for Octane to receive
                                                          RMGII traffic.  When this bit clear on a given
@@ -1055,12 +1013,10 @@ typedef union cvmx_asxx_rx_prt_en cvmx_asxx_rx_prt_en_t;
  * ASX_RX_WOL = RGMII RX Wake on LAN status register
  *
  */
-union cvmx_asxx_rx_wol
-{
+union cvmx_asxx_rx_wol {
 	uint64_t u64;
-	struct cvmx_asxx_rx_wol_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rx_wol_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t status                       : 1;  /**< Copy of PMCSR[15] - PME_status */
 	uint64_t enable                       : 1;  /**< Copy of PMCSR[8]  - PME_enable */
@@ -1081,12 +1037,10 @@ typedef union cvmx_asxx_rx_wol cvmx_asxx_rx_wol_t;
  * ASX_RX_WOL_MSK = RGMII RX Wake on LAN byte mask
  *
  */
-union cvmx_asxx_rx_wol_msk
-{
+union cvmx_asxx_rx_wol_msk {
 	uint64_t u64;
-	struct cvmx_asxx_rx_wol_msk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rx_wol_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t msk                          : 64; /**< Bytes to include in the CRC signature */
 #else
 	uint64_t msk                          : 64;
@@ -1103,12 +1057,10 @@ typedef union cvmx_asxx_rx_wol_msk cvmx_asxx_rx_wol_msk_t;
  * ASX_RX_WOL_POWOK = RGMII RX Wake on LAN Power OK
  *
  */
-union cvmx_asxx_rx_wol_powok
-{
+union cvmx_asxx_rx_wol_powok {
 	uint64_t u64;
-	struct cvmx_asxx_rx_wol_powok_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rx_wol_powok_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t powerok                      : 1;  /**< Power OK */
 #else
@@ -1127,12 +1079,10 @@ typedef union cvmx_asxx_rx_wol_powok cvmx_asxx_rx_wol_powok_t;
  * ASX_RX_WOL_SIG = RGMII RX Wake on LAN CRC signature
  *
  */
-union cvmx_asxx_rx_wol_sig
-{
+union cvmx_asxx_rx_wol_sig {
 	uint64_t u64;
-	struct cvmx_asxx_rx_wol_sig_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rx_wol_sig_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t sig                          : 32; /**< CRC signature */
 #else
@@ -1185,12 +1135,10 @@ typedef union cvmx_asxx_rx_wol_sig cvmx_asxx_rx_wol_sig_t;
  *    1.25            24
  *    1.3             25
  */
-union cvmx_asxx_tx_clk_setx
-{
+union cvmx_asxx_tx_clk_setx {
 	uint64_t u64;
-	struct cvmx_asxx_tx_clk_setx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_clk_setx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t setting                      : 5;  /**< Setting to place on the open-loop TXC delay line */
 #else
@@ -1214,20 +1162,17 @@ typedef union cvmx_asxx_tx_clk_setx cvmx_asxx_tx_clk_setx_t;
  * ASX_TX_COMP_BYP = RGMII Clock delay setting
  *
  */
-union cvmx_asxx_tx_comp_byp
-{
+union cvmx_asxx_tx_comp_byp {
 	uint64_t u64;
-	struct cvmx_asxx_tx_comp_byp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_comp_byp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_0_63                : 64;
 #else
 	uint64_t reserved_0_63                : 64;
 #endif
 	} s;
-	struct cvmx_asxx_tx_comp_byp_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_comp_byp_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t bypass                       : 1;  /**< Compensation bypass */
 	uint64_t pctl                         : 4;  /**< PCTL Compensation Value (see Duke) */
@@ -1240,9 +1185,8 @@ union cvmx_asxx_tx_comp_byp
 #endif
 	} cn30xx;
 	struct cvmx_asxx_tx_comp_byp_cn30xx   cn31xx;
-	struct cvmx_asxx_tx_comp_byp_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_comp_byp_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t pctl                         : 4;  /**< PCTL Compensation Value (see Duke) */
 	uint64_t nctl                         : 4;  /**< NCTL Compensation Value (see Duke) */
@@ -1253,9 +1197,8 @@ union cvmx_asxx_tx_comp_byp
 #endif
 	} cn38xx;
 	struct cvmx_asxx_tx_comp_byp_cn38xx   cn38xxp2;
-	struct cvmx_asxx_tx_comp_byp_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_comp_byp_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t bypass                       : 1;  /**< Compensation bypass */
 	uint64_t reserved_13_15               : 3;
@@ -1271,9 +1214,8 @@ union cvmx_asxx_tx_comp_byp
 	uint64_t reserved_17_63               : 47;
 #endif
 	} cn50xx;
-	struct cvmx_asxx_tx_comp_byp_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_comp_byp_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t pctl                         : 5;  /**< PCTL Compensation Value (see Duke) */
 	uint64_t reserved_5_7                 : 3;
@@ -1295,12 +1237,10 @@ typedef union cvmx_asxx_tx_comp_byp cvmx_asxx_tx_comp_byp_t;
  * ASX_TX_HI_WATER = RGMII TX FIFO Hi WaterMark
  *
  */
-union cvmx_asxx_tx_hi_waterx
-{
+union cvmx_asxx_tx_hi_waterx {
 	uint64_t u64;
-	struct cvmx_asxx_tx_hi_waterx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_hi_waterx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t mark                         : 4;  /**< TX FIFO HiWatermark to stall GMX
                                                          Value of 0 maps to 16
@@ -1315,9 +1255,8 @@ union cvmx_asxx_tx_hi_waterx
 	uint64_t reserved_4_63                : 60;
 #endif
 	} s;
-	struct cvmx_asxx_tx_hi_waterx_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_hi_waterx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t mark                         : 3;  /**< TX FIFO HiWatermark to stall GMX
                                                          Value 0 maps to 8. */
@@ -1341,12 +1280,10 @@ typedef union cvmx_asxx_tx_hi_waterx cvmx_asxx_tx_hi_waterx_t;
  * ASX_TX_PRT_EN = RGMII Port Enable
  *
  */
-union cvmx_asxx_tx_prt_en
-{
+union cvmx_asxx_tx_prt_en {
 	uint64_t u64;
-	struct cvmx_asxx_tx_prt_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_prt_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t prt_en                       : 4;  /**< Port enable.  Must be set for Octane to send
                                                          RMGII traffic.   When this bit clear on a given
@@ -1357,9 +1294,8 @@ union cvmx_asxx_tx_prt_en
 	uint64_t reserved_4_63                : 60;
 #endif
 	} s;
-	struct cvmx_asxx_tx_prt_en_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_prt_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t prt_en                       : 3;  /**< Port enable.  Must be set for Octane to send
                                                          RMGII traffic.   When this bit clear on a given
diff --git a/sys/contrib/octeon-sdk/cvmx-atomic.h b/sys/contrib/octeon-sdk/cvmx-atomic.h
index 7ec5c23..39b5944 100644
--- a/sys/contrib/octeon-sdk/cvmx-atomic.h
+++ b/sys/contrib/octeon-sdk/cvmx-atomic.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * This file provides atomic operations
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  *
  */
@@ -356,7 +356,7 @@ static inline int64_t cvmx_atomic_fetch_and_add64_nosync(int64_t *ptr, int64_t i
     uint64_t tmp, ret;
 
 #if !defined(__FreeBSD__) || !defined(_KERNEL)
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
     {
 	CVMX_PUSH_OCTEON2;
 	if (__builtin_constant_p(incr) && incr == 1)
@@ -441,7 +441,7 @@ static inline int32_t cvmx_atomic_fetch_and_add32_nosync(int32_t *ptr, int32_t i
     uint32_t tmp, ret;
 
 #if !defined(__FreeBSD__) || !defined(_KERNEL)
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
     {
 	CVMX_PUSH_OCTEON2;
 	if (__builtin_constant_p(incr) && incr == 1)
@@ -657,7 +657,7 @@ static inline uint64_t cvmx_atomic_swap64_nosync(uint64_t *ptr, uint64_t new_val
     uint64_t tmp, ret;
 
 #if !defined(__FreeBSD__) || !defined(_KERNEL)
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
     {
 	CVMX_PUSH_OCTEON2;
 	if (__builtin_constant_p(new_val) && new_val == 0)
@@ -719,7 +719,7 @@ static inline uint32_t cvmx_atomic_swap32_nosync(uint32_t *ptr, uint32_t new_val
     uint32_t tmp, ret;
 
 #if !defined(__FreeBSD__) || !defined(_KERNEL)
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
     {
 	CVMX_PUSH_OCTEON2;
 	if (__builtin_constant_p(new_val) && new_val == 0)
@@ -763,22 +763,6 @@ static inline uint32_t cvmx_atomic_swap32_nosync(uint32_t *ptr, uint32_t new_val
     return (ret);
 }
 
-/**
- * This atomic operation is now named cvmx_atomic_compare_and_store32_nosync
- * and the (deprecated) macro is provided for backward compatibility.
- * @deprecated
- */
-#define cvmx_atomic_compare_and_store_nosync32 cvmx_atomic_compare_and_store32_nosync
-
-/**
- * This atomic operation is now named cvmx_atomic_compare_and_store64_nosync
- * and the (deprecated) macro is provided for backward compatibility.
- * @deprecated
- */
-#define cvmx_atomic_compare_and_store_nosync64 cvmx_atomic_compare_and_store64_nosync
-
-
-
 #ifdef	__cplusplus
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-bootloader.h b/sys/contrib/octeon-sdk/cvmx-bootloader.h
index caf4609..6529df1 100644
--- a/sys/contrib/octeon-sdk/cvmx-bootloader.h
+++ b/sys/contrib/octeon-sdk/cvmx-bootloader.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -50,7 +50,7 @@
  *
  * Bootloader definitions that are shared with other programs
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 
@@ -127,9 +127,9 @@ typedef enum
     BL_HEADER_IMAGE_PCIBOOT,     /* Binary bootloader for PCI boot */
     BL_HEADER_IMAGE_UBOOT_ENV,  /* Environment for u-boot */
     BL_HEADER_IMAGE_MAX,
-    /* Range for customer private use.  Will not be used by Cavium Networks */
+    /* Range for customer private use.  Will not be used by Cavium Inc. */
     BL_HEADER_IMAGE_CUST_RESERVED_MIN = 0x1000,
-    BL_HEADER_IMAGE_CUST_RESERVED_MAX = 0x1fff,
+    BL_HEADER_IMAGE_CUST_RESERVED_MAX = 0x1fff
 } bootloader_image_t;
 
 #endif /* __ASSEMBLY__ */
@@ -139,7 +139,7 @@ typedef enum
 #define MAX_NAND_SEARCH_ADDR   0x400000
 
 /* Maximum address to look for start of normal bootloader */
-#define MAX_NOR_SEARCH_ADDR   0x100000
+#define MAX_NOR_SEARCH_ADDR   0x200000
 
 /* Defines for RAM based environment set by the host or the previous bootloader
 ** in a chain boot configuration. */
@@ -147,5 +147,6 @@ typedef enum
 #define U_BOOT_RAM_ENV_ADDR     (0x1000)
 #define U_BOOT_RAM_ENV_SIZE     (0x1000)
 #define U_BOOT_RAM_ENV_CRC_SIZE (0x4)
+#define U_BOOT_RAM_ENV_ADDR_2	(U_BOOT_RAM_ENV_ADDR + U_BOOT_RAM_ENV_SIZE)
 
 #endif /* __CVMX_BOOTLOADER__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-bootmem.c b/sys/contrib/octeon-sdk/cvmx-bootmem.c
index 2873bc0..bb111d2 100644
--- a/sys/contrib/octeon-sdk/cvmx-bootmem.c
+++ b/sys/contrib/octeon-sdk/cvmx-bootmem.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -47,7 +47,7 @@
  * Simple allocate only memory allocator.  Used to allocate memory at application
  * start time.
  *
- * <hr>$Revision: 52119 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
@@ -302,7 +302,7 @@ static int __cvmx_bootmem_check_version(int exact_match)
     int major_version;
 #ifdef CVMX_BUILD_FOR_LINUX_HOST
     if (!cvmx_bootmem_desc_addr)
-        cvmx_bootmem_desc_addr = cvmx_read64_uint64(0x24100);
+        cvmx_bootmem_desc_addr = cvmx_read64_uint64(0x48100);
 #endif
     major_version = CVMX_BOOTMEM_DESC_GET_FIELD(major_version);
     if ((major_version > 3) || (exact_match && major_version != exact_match))
@@ -459,27 +459,70 @@ void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment)
 EXPORT_SYMBOL(cvmx_bootmem_alloc);
 #endif
 
-void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name)
+void *cvmx_bootmem_alloc_named_range_once(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name, void (*init)(void*))
 {
     int64_t addr;
+    void *ptr;
+    uint64_t named_block_desc_addr;
+
+    __cvmx_bootmem_lock(0);
 
     __cvmx_validate_mem_range(&min_addr, &max_addr);
-    addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr, align, name, 0);
-    if (addr >= 0)
+    named_block_desc_addr = cvmx_bootmem_phy_named_block_find(name, CVMX_BOOTMEM_FLAG_NO_LOCKING);
+
+    if (named_block_desc_addr)
+    {
+        addr = CVMX_BOOTMEM_NAMED_GET_FIELD(named_block_desc_addr, base_addr);
+        __cvmx_bootmem_unlock(0);
         return cvmx_phys_to_ptr(addr);
-    else
+    }
+
+    addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr, align, name, CVMX_BOOTMEM_FLAG_NO_LOCKING);
+
+    if (addr < 0)
+    {
+        __cvmx_bootmem_unlock(0);
         return NULL;
+    }
+    ptr = cvmx_phys_to_ptr(addr);
+    init(ptr);
+    __cvmx_bootmem_unlock(0);
+    return ptr;
+}
+
+static void *cvmx_bootmem_alloc_named_range_flags(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name, uint32_t flags)
+{
+	int64_t addr;
+
+	__cvmx_validate_mem_range(&min_addr, &max_addr);
+	addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr, align, name, flags);
+	if (addr >= 0)
+		return cvmx_phys_to_ptr(addr);
+	else
+		return NULL;
+
+}
 
+void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name)
+{
+    return cvmx_bootmem_alloc_named_range_flags(size, min_addr, max_addr, align, name, 0);
 }
+
 void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address, const char *name)
 {
     return(cvmx_bootmem_alloc_named_range(size, address, address + size, 0, name));
 }
+
 void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, const char *name)
 {
     return(cvmx_bootmem_alloc_named_range(size, 0, 0, alignment, name));
 }
 
+void *cvmx_bootmem_alloc_named_flags(uint64_t size, uint64_t alignment, const char *name, uint32_t flags)
+{
+    return cvmx_bootmem_alloc_named_range_flags(size, 0, 0, alignment, name, flags);
+}
+
 int cvmx_bootmem_free_named(const char *name)
 {
     return(cvmx_bootmem_phy_named_block_free(name, 0));
@@ -571,16 +614,7 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, uint64_t
     /* Round req_size up to mult of minimum alignment bytes */
     req_size = (req_size + (CVMX_BOOTMEM_ALIGNMENT_SIZE - 1)) & ~(CVMX_BOOTMEM_ALIGNMENT_SIZE - 1);
 
-    /* Convert !0 address_min and 0 address_max to special case of range that specifies an exact
-    ** memory block to allocate.  Do this before other checks and adjustments so that this tranformation will be validated */
-    if (address_min && !address_max)
-        address_max = address_min + req_size;
-    else if (!address_min && !address_max)
-        address_max = ~0ull;   /* If no limits given, use max limits */
-
-
-
-
+    
     /* Enforce minimum alignment (this also keeps the minimum free block
     ** req_size the same as the alignment req_size */
     if (alignment < CVMX_BOOTMEM_ALIGNMENT_SIZE)
@@ -594,6 +628,12 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, uint64_t
     if (alignment)
         address_min = (address_min + (alignment - 1)) & ~(alignment - 1);
 
+    /* Convert !0 address_min and 0 address_max to special case of range that specifies an exact
+     ** memory block to allocate.  Do this before other checks and adjustments so that this tranformation will be validated */
+    if (address_min && !address_max)
+        address_max = address_min + req_size;
+    else if (!address_min && !address_max)
+        address_max = ~0ull;   /* If no limits given, use max limits */
 
     /* Reject inconsistent args.  We have adjusted these, so this may fail due to our internal changes
     ** even if this check would pass for the values the user supplied. */
@@ -827,7 +867,7 @@ void cvmx_bootmem_phy_list_print(void)
     }
     while (addr)
     {
-        cvmx_dprintf("Block address: 0x%08qx, size: 0x%08qx, next: 0x%08qx\n",
+        cvmx_dprintf("Block address: 0x%08llx, size: 0x%08llx, next: 0x%08llx\n",
                (ULL)addr,
                (ULL)cvmx_bootmem_phy_get_size(addr),
                (ULL)cvmx_bootmem_phy_get_next(addr));
@@ -1016,7 +1056,7 @@ void cvmx_bootmem_phy_named_block_print(void)
             uint64_t named_addr = CVMX_BOOTMEM_NAMED_GET_FIELD(named_block_addr, base_addr);
             CVMX_BOOTMEM_NAMED_GET_NAME(named_block_addr, name_tmp, name_length);
             printed++;
-            cvmx_dprintf("Name: %s, address: 0x%08qx, size: 0x%08qx, index: %d\n",
+            cvmx_dprintf("Name: %s, address: 0x%08llx, size: 0x%08llx, index: %d\n",
                    name_tmp, (ULL)named_addr, (ULL)named_size, i);
         }
         named_block_addr += sizeof(cvmx_bootmem_named_block_desc_t);
@@ -1029,14 +1069,6 @@ void cvmx_bootmem_phy_named_block_print(void)
 }
 
 
-/* Real physical addresses of memory regions */
-#define OCTEON_DDR0_BASE    (0x0ULL)
-#define OCTEON_DDR0_SIZE    (0x010000000ULL)
-#define OCTEON_DDR1_BASE    (OCTEON_IS_MODEL(OCTEON_CN6XXX) ? 0x20000000ULL : 0x410000000ULL)
-#define OCTEON_DDR1_SIZE    (0x010000000ULL)
-#define OCTEON_DDR2_BASE    (OCTEON_IS_MODEL(OCTEON_CN6XXX) ? 0x30000000ULL : 0x20000000ULL)
-#define OCTEON_DDR2_SIZE    (OCTEON_IS_MODEL(OCTEON_CN6XXX) ? 0x7d0000000ULL : 0x3e0000000ULL)
-#define OCTEON_MAX_PHY_MEM_SIZE (OCTEON_IS_MODEL(OCTEON_CN63XX) ? 32*1024*1024*1024ULL : 16*1024*1024*1024ULL)
 int64_t cvmx_bootmem_phy_mem_list_init(uint64_t mem_size, uint32_t low_reserved_bytes, cvmx_bootmem_desc_t *desc_buffer)
 {
     uint64_t cur_block_addr;
diff --git a/sys/contrib/octeon-sdk/cvmx-bootmem.h b/sys/contrib/octeon-sdk/cvmx-bootmem.h
index 2f07990..319b2c9 100644
--- a/sys/contrib/octeon-sdk/cvmx-bootmem.h
+++ b/sys/contrib/octeon-sdk/cvmx-bootmem.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -47,7 +47,7 @@
  * Simple allocate only memory allocator.  Used to allocate memory at application
  * start time.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
@@ -66,6 +66,14 @@ extern "C" {
 #define CVMX_BOOTMEM_FLAG_END_ALLOC    (1 << 0)     /* Allocate from end of block instead of beginning */
 #define CVMX_BOOTMEM_FLAG_NO_LOCKING   (1 << 1)     /* Don't do any locking. */
 
+/* Real physical addresses of memory regions */
+#define OCTEON_DDR0_BASE    (0x0ULL)
+#define OCTEON_DDR0_SIZE    (0x010000000ULL)
+#define OCTEON_DDR1_BASE    ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) ? 0x20000000ULL : 0x410000000ULL)
+#define OCTEON_DDR1_SIZE    (0x010000000ULL)
+#define OCTEON_DDR2_BASE    ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) ? 0x30000000ULL : 0x20000000ULL)
+#define OCTEON_DDR2_SIZE    ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) ? 0x7d0000000ULL : 0x3e0000000ULL)
+#define OCTEON_MAX_PHY_MEM_SIZE ((OCTEON_IS_MODEL(OCTEON_CN68XX)) ? 128*1024*1024*1024ULL : (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) ? 32*1024*1024*1024ull : 16*1024*1024*1024ULL)
 
 /* First bytes of each free physical block of memory contain this structure,
  * which is used to maintain the free memory list.  Since the bootloader is
@@ -162,6 +170,21 @@ extern void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment);
  */
 extern void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address, uint64_t alignment);
 
+/**
+ * Allocate a block of memory from the free list that was
+ * passed to the application by the bootloader within a specified
+ * address range. This is an allocate-only algorithm, so
+ * freeing memory is not possible. Allocation will fail if
+ * memory cannot be allocated in the requested range.
+ *
+ * @param size      Size in bytes of block to allocate
+ * @param min_addr  defines the minimum address of the range
+ * @param max_addr  defines the maximum address of the range
+ * @param alignment Alignment required - must be power of 2
+ * @param flags     Flags to control options for the allocation.
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_range_flags(uint64_t size, uint64_t alignment, uint64_t min_addr, uint64_t max_addr, uint32_t flags);
 
 
 /**
@@ -194,6 +217,21 @@ extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment, uint64_
  */
 extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, const char *name);
 
+/**
+ * Allocate a block of memory from the free list that was passed
+ * to the application by the bootloader, and assign it a name in the
+ * global named block table.  (part of the cvmx_bootmem_descriptor_t structure)
+ * Named blocks can later be freed.
+ *
+ * @param size      Size in bytes of block to allocate
+ * @param alignment Alignment required - must be power of 2
+ * @param name      name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ * @param flags     Flags to control options for the allocation.
+ *
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named_flags(uint64_t size, uint64_t alignment, const char *name, uint32_t flags);
+
 
 
 /**
@@ -231,6 +269,25 @@ extern void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address, c
 extern void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name);
 
 /**
+ * Allocate if needed a block of memory from a specific range of the free list that was passed
+ * to the application by the bootloader, and assign it a name in the
+ * global named block table.  (part of the cvmx_bootmem_descriptor_t structure)
+ * Named blocks can later be freed.
+ * If the requested name block is already allocated, return the pointer to block of memory.
+ * If request cannot be satisfied within the address range specified, NULL is returned
+ *
+ * @param size      Size in bytes of block to allocate
+ * @param min_addr  minimum address of range
+ * @param max_addr  maximum address of range
+ * @param align     Alignment of memory to be allocated. (must be a power of 2)
+ * @param name      name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ * @param init      Initialization function
+ *
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named_range_once(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name, void (*init)(void*));
+
+/**
  * Frees a previously allocated named bootmem block.
  *
  * @param name   name of block to free
diff --git a/sys/contrib/octeon-sdk/cvmx-ciu-defs.h b/sys/contrib/octeon-sdk/cvmx-ciu-defs.h
index 05c03ff..2411d13 100644
--- a/sys/contrib/octeon-sdk/cvmx-ciu-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-ciu-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,15 +49,15 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_CIU_TYPEDEFS_H__
-#define __CVMX_CIU_TYPEDEFS_H__
+#ifndef __CVMX_CIU_DEFS_H__
+#define __CVMX_CIU_DEFS_H__
 
 #define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_CIU_BLOCK_INT CVMX_CIU_BLOCK_INT_FUNC()
 static inline uint64_t CVMX_CIU_BLOCK_INT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_CIU_BLOCK_INT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00010700000007C0ull);
 }
@@ -65,13 +65,169 @@ static inline uint64_t CVMX_CIU_BLOCK_INT_FUNC(void)
 #define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull))
 #endif
 #define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_IOX_INT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_CIU_EN2_IOX_INT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x000107000000A600ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_CIU_EN2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x000107000000A600ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_IOX_INT_W1C(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_CIU_EN2_IOX_INT_W1C(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x000107000000CE00ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_CIU_EN2_IOX_INT_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CE00ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_IOX_INT_W1S(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_CIU_EN2_IOX_INT_W1S(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x000107000000AE00ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_CIU_EN2_IOX_INT_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AE00ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_PPX_IP2(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_CIU_EN2_PPX_IP2(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x000107000000A000ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_EN2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x000107000000A000ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_PPX_IP2_W1C(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_CIU_EN2_PPX_IP2_W1C(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x000107000000C800ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_EN2_PPX_IP2_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000C800ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_PPX_IP2_W1S(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_CIU_EN2_PPX_IP2_W1S(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x000107000000A800ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_EN2_PPX_IP2_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000A800ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_PPX_IP3(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_CIU_EN2_PPX_IP3(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x000107000000A200ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_EN2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x000107000000A200ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_PPX_IP3_W1C(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_CIU_EN2_PPX_IP3_W1C(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x000107000000CA00ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_EN2_PPX_IP3_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CA00ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_PPX_IP3_W1S(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_CIU_EN2_PPX_IP3_W1S(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x000107000000AA00ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_EN2_PPX_IP3_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AA00ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_PPX_IP4(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_CIU_EN2_PPX_IP4(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x000107000000A400ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_EN2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x000107000000A400ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_PPX_IP4_W1C(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_CIU_EN2_PPX_IP4_W1C(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_EN2_PPX_IP4_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_PPX_IP4_W1S(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_CIU_EN2_PPX_IP4_W1S(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_EN2_PPX_IP4_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8)
+#endif
 #define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull))
 #define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_CIU_INT33_SUM0 CVMX_CIU_INT33_SUM0_FUNC()
 static inline uint64_t CVMX_CIU_INT33_SUM0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_CIU_INT33_SUM0 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070000000110ull);
 }
@@ -89,7 +245,10 @@ static inline uint64_t CVMX_CIU_INTX_EN0(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33))))))
 		cvmx_warn("CVMX_CIU_INTX_EN0(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16;
 }
@@ -103,7 +262,10 @@ static inline uint64_t CVMX_CIU_INTX_EN0_W1C(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33))))))
 		cvmx_warn("CVMX_CIU_INTX_EN0_W1C(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16;
 }
@@ -117,7 +279,10 @@ static inline uint64_t CVMX_CIU_INTX_EN0_W1S(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33))))))
 		cvmx_warn("CVMX_CIU_INTX_EN0_W1S(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16;
 }
@@ -135,7 +300,10 @@ static inline uint64_t CVMX_CIU_INTX_EN1(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33))))))
 		cvmx_warn("CVMX_CIU_INTX_EN1(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16;
 }
@@ -149,7 +317,10 @@ static inline uint64_t CVMX_CIU_INTX_EN1_W1C(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33))))))
 		cvmx_warn("CVMX_CIU_INTX_EN1_W1C(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16;
 }
@@ -163,7 +334,10 @@ static inline uint64_t CVMX_CIU_INTX_EN1_W1S(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33))))))
 		cvmx_warn("CVMX_CIU_INTX_EN1_W1S(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16;
 }
@@ -178,7 +352,10 @@ static inline uint64_t CVMX_CIU_INTX_EN4_0(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_CIU_INTX_EN4_0(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16;
 }
@@ -192,7 +369,10 @@ static inline uint64_t CVMX_CIU_INTX_EN4_0_W1C(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_CIU_INTX_EN4_0_W1C(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16;
 }
@@ -206,7 +386,10 @@ static inline uint64_t CVMX_CIU_INTX_EN4_0_W1S(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_CIU_INTX_EN4_0_W1S(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16;
 }
@@ -221,7 +404,10 @@ static inline uint64_t CVMX_CIU_INTX_EN4_1(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_CIU_INTX_EN4_1(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16;
 }
@@ -235,7 +421,10 @@ static inline uint64_t CVMX_CIU_INTX_EN4_1_W1C(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_CIU_INTX_EN4_1_W1C(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16;
 }
@@ -249,7 +438,10 @@ static inline uint64_t CVMX_CIU_INTX_EN4_1_W1S(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_CIU_INTX_EN4_1_W1S(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16;
 }
@@ -267,7 +459,10 @@ static inline uint64_t CVMX_CIU_INTX_SUM0(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || (offset == 32)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || (offset == 32)))))
 		cvmx_warn("CVMX_CIU_INTX_SUM0(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8;
 }
@@ -282,7 +477,10 @@ static inline uint64_t CVMX_CIU_INTX_SUM4(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_CIU_INTX_SUM4(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8;
 }
@@ -293,77 +491,173 @@ static inline uint64_t CVMX_CIU_INTX_SUM4(unsigned long offset)
 #define CVMX_CIU_INT_DBG_SEL CVMX_CIU_INT_DBG_SEL_FUNC()
 static inline uint64_t CVMX_CIU_INT_DBG_SEL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_CIU_INT_DBG_SEL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00010700000007D0ull);
 }
 #else
 #define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull))
 #endif
-#define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset)
+#define CVMX_CIU_INT_SUM1 CVMX_CIU_INT_SUM1_FUNC()
+static inline uint64_t CVMX_CIU_INT_SUM1_FUNC(void)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
-		cvmx_warn("CVMX_CIU_MBOX_CLRX(%lu) is invalid on this chip\n", offset);
-	return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8;
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_CIU_INT_SUM1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000108ull);
 }
 #else
-#define CVMX_CIU_MBOX_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull))
 #endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset)
+{
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+			if ((offset == 0))
+				return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 0) * 8;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 3))
+				return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 3) * 8;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 1))
+				return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 1) * 8;
+			break;
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 15))
+				return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 11))
+				return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8;
+			break;
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 9))
+				return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 5))
+				return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 7) * 8;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 31))
+				return CVMX_ADD_IO_SEG(0x0001070100100600ull) + ((offset) & 31) * 8;
+			break;
+	}
+	cvmx_warn("CVMX_CIU_MBOX_CLRX (offset = %lu) not supported on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 3) * 8;
+}
 static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
-		cvmx_warn("CVMX_CIU_MBOX_SETX(%lu) is invalid on this chip\n", offset);
-	return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+			if ((offset == 0))
+				return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 0) * 8;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 3))
+				return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 3) * 8;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 1))
+				return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 1) * 8;
+			break;
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 15))
+				return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 11))
+				return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8;
+			break;
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 9))
+				return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 5))
+				return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 7) * 8;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 31))
+				return CVMX_ADD_IO_SEG(0x0001070100100400ull) + ((offset) & 31) * 8;
+			break;
+	}
+	cvmx_warn("CVMX_CIU_MBOX_SETX (offset = %lu) not supported on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 3) * 8;
 }
-#else
-#define CVMX_CIU_MBOX_SETX(offset) (CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8)
-#endif
 #define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull))
 #define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull))
-#define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
+#define CVMX_CIU_PP_BIST_STAT CVMX_CIU_PP_BIST_STAT_FUNC()
+static inline uint64_t CVMX_CIU_PP_BIST_STAT_FUNC(void)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
-		cvmx_warn("CVMX_CIU_PP_POKEX(%lu) is invalid on this chip\n", offset);
-	return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8;
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_CIU_PP_BIST_STAT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010700000007E0ull);
 }
 #else
-#define CVMX_CIU_PP_POKEX(offset) (CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_PP_BIST_STAT (CVMX_ADD_IO_SEG(0x00010700000007E0ull))
 #endif
+#define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull))
+static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
+{
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+			if ((offset == 0))
+				return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 0) * 8;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 3))
+				return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 3) * 8;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 1))
+				return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 1) * 8;
+			break;
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 15))
+				return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 11))
+				return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8;
+			break;
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 9))
+				return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 5))
+				return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 7) * 8;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 31))
+				return CVMX_ADD_IO_SEG(0x0001070100100200ull) + ((offset) & 31) * 8;
+			break;
+	}
+	cvmx_warn("CVMX_CIU_PP_POKEX (offset = %lu) not supported on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 3) * 8;
+}
 #define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_CIU_QLM0 CVMX_CIU_QLM0_FUNC()
 static inline uint64_t CVMX_CIU_QLM0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_CIU_QLM0 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070000000780ull);
 }
@@ -374,7 +668,7 @@ static inline uint64_t CVMX_CIU_QLM0_FUNC(void)
 #define CVMX_CIU_QLM1 CVMX_CIU_QLM1_FUNC()
 static inline uint64_t CVMX_CIU_QLM1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_CIU_QLM1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070000000788ull);
 }
@@ -385,7 +679,7 @@ static inline uint64_t CVMX_CIU_QLM1_FUNC(void)
 #define CVMX_CIU_QLM2 CVMX_CIU_QLM2_FUNC()
 static inline uint64_t CVMX_CIU_QLM2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_CIU_QLM2 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070000000790ull);
 }
@@ -393,6 +687,28 @@ static inline uint64_t CVMX_CIU_QLM2_FUNC(void)
 #define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU_QLM3 CVMX_CIU_QLM3_FUNC()
+static inline uint64_t CVMX_CIU_QLM3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_CIU_QLM3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000798ull);
+}
+#else
+#define CVMX_CIU_QLM3 (CVMX_ADD_IO_SEG(0x0001070000000798ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU_QLM4 CVMX_CIU_QLM4_FUNC()
+static inline uint64_t CVMX_CIU_QLM4_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_CIU_QLM4 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010700000007A0ull);
+}
+#else
+#define CVMX_CIU_QLM4 (CVMX_ADD_IO_SEG(0x00010700000007A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_CIU_QLM_DCOK CVMX_CIU_QLM_DCOK_FUNC()
 static inline uint64_t CVMX_CIU_QLM_DCOK_FUNC(void)
 {
@@ -407,7 +723,7 @@ static inline uint64_t CVMX_CIU_QLM_DCOK_FUNC(void)
 #define CVMX_CIU_QLM_JTGC CVMX_CIU_QLM_JTGC_FUNC()
 static inline uint64_t CVMX_CIU_QLM_JTGC_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_CIU_QLM_JTGC not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070000000768ull);
 }
@@ -418,7 +734,7 @@ static inline uint64_t CVMX_CIU_QLM_JTGC_FUNC(void)
 #define CVMX_CIU_QLM_JTGD CVMX_CIU_QLM_JTGD_FUNC()
 static inline uint64_t CVMX_CIU_QLM_JTGD_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_CIU_QLM_JTGD not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070000000770ull);
 }
@@ -431,15 +747,141 @@ static inline uint64_t CVMX_CIU_QLM_JTGD_FUNC(void)
 #define CVMX_CIU_SOFT_PRST1 CVMX_CIU_SOFT_PRST1_FUNC()
 static inline uint64_t CVMX_CIU_SOFT_PRST1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_CIU_SOFT_PRST1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070000000758ull);
 }
 #else
 #define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull))
 #endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU_SOFT_PRST2 CVMX_CIU_SOFT_PRST2_FUNC()
+static inline uint64_t CVMX_CIU_SOFT_PRST2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN66XX)))
+		cvmx_warn("CVMX_CIU_SOFT_PRST2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010700000007D8ull);
+}
+#else
+#define CVMX_CIU_SOFT_PRST2 (CVMX_ADD_IO_SEG(0x00010700000007D8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU_SOFT_PRST3 CVMX_CIU_SOFT_PRST3_FUNC()
+static inline uint64_t CVMX_CIU_SOFT_PRST3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN66XX)))
+		cvmx_warn("CVMX_CIU_SOFT_PRST3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010700000007E0ull);
+}
+#else
+#define CVMX_CIU_SOFT_PRST3 (CVMX_ADD_IO_SEG(0x00010700000007E0ull))
+#endif
 #define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_SUM1_IOX_INT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_CIU_SUM1_IOX_INT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000008600ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_CIU_SUM1_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008600ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_SUM1_PPX_IP2(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_CIU_SUM1_PPX_IP2(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000008000ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_SUM1_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008000ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_SUM1_PPX_IP3(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_CIU_SUM1_PPX_IP3(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000008200ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_SUM1_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008200ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_SUM1_PPX_IP4(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_CIU_SUM1_PPX_IP4(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000008400ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_SUM1_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008400ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_SUM2_IOX_INT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_CIU_SUM2_IOX_INT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000008E00ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_CIU_SUM2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008E00ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_SUM2_PPX_IP2(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_CIU_SUM2_PPX_IP2(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000008800ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_SUM2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008800ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_SUM2_PPX_IP3(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_CIU_SUM2_PPX_IP3(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000008A00ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_SUM2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008A00ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_SUM2_PPX_IP4(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_CIU_SUM2_PPX_IP4(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000008C00ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_SUM2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008C00ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_CIU_TIMX(unsigned long offset)
 {
 	if (!(
@@ -450,53 +892,90 @@ static inline uint64_t CVMX_CIU_TIMX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 9)))))
 		cvmx_warn("CVMX_CIU_TIMX(%lu) is invalid on this chip\n", offset);
-	return CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 3) * 8;
+	return CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 15) * 8;
 }
 #else
-#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 3) * 8)
+#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 15) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
+#define CVMX_CIU_TIM_MULTI_CAST CVMX_CIU_TIM_MULTI_CAST_FUNC()
+static inline uint64_t CVMX_CIU_TIM_MULTI_CAST_FUNC(void)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
-		cvmx_warn("CVMX_CIU_WDOGX(%lu) is invalid on this chip\n", offset);
-	return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8;
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_CIU_TIM_MULTI_CAST not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x000107000000C200ull);
 }
 #else
-#define CVMX_CIU_WDOGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_TIM_MULTI_CAST (CVMX_ADD_IO_SEG(0x000107000000C200ull))
 #endif
+static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
+{
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+			if ((offset == 0))
+				return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 0) * 8;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 3))
+				return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 3) * 8;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 1))
+				return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 1) * 8;
+			break;
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 15))
+				return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 11))
+				return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8;
+			break;
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 9))
+				return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 5))
+				return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 7) * 8;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 31))
+				return CVMX_ADD_IO_SEG(0x0001070100100000ull) + ((offset) & 31) * 8;
+			break;
+	}
+	cvmx_warn("CVMX_CIU_WDOGX (offset = %lu) not supported on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 3) * 8;
+}
 
 /**
  * cvmx_ciu_bist
  */
-union cvmx_ciu_bist
-{
+union cvmx_ciu_bist {
 	uint64_t u64;
-	struct cvmx_ciu_bist_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_5_63                : 59;
-	uint64_t bist                         : 5;  /**< BIST Results.
+	struct cvmx_ciu_bist_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t bist                         : 7;  /**< BIST Results.
                                                          HW sets a bit in BIST for for memory that fails
                                                          BIST. */
 #else
-	uint64_t bist                         : 5;
-	uint64_t reserved_5_63                : 59;
+	uint64_t bist                         : 7;
+	uint64_t reserved_7_63                : 57;
 #endif
 	} s;
-	struct cvmx_ciu_bist_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_bist_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t bist                         : 4;  /**< BIST Results.
                                                          HW sets a bit in BIST for for memory that fails
@@ -509,9 +988,8 @@ union cvmx_ciu_bist
 	struct cvmx_ciu_bist_cn30xx           cn31xx;
 	struct cvmx_ciu_bist_cn30xx           cn38xx;
 	struct cvmx_ciu_bist_cn30xx           cn38xxp2;
-	struct cvmx_ciu_bist_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_bist_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t bist                         : 2;  /**< BIST Results.
                                                          HW sets a bit in BIST for for memory that fails
@@ -521,9 +999,8 @@ union cvmx_ciu_bist
 	uint64_t reserved_2_63                : 62;
 #endif
 	} cn50xx;
-	struct cvmx_ciu_bist_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_bist_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t bist                         : 3;  /**< BIST Results.
                                                          HW sets a bit in BIST for for memory that fails
@@ -538,8 +1015,33 @@ union cvmx_ciu_bist
 	struct cvmx_ciu_bist_cn30xx           cn56xxp1;
 	struct cvmx_ciu_bist_cn30xx           cn58xx;
 	struct cvmx_ciu_bist_cn30xx           cn58xxp1;
-	struct cvmx_ciu_bist_s                cn63xx;
-	struct cvmx_ciu_bist_s                cn63xxp1;
+	struct cvmx_ciu_bist_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_6_63                : 58;
+	uint64_t bist                         : 6;  /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         BIST. */
+#else
+	uint64_t bist                         : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_bist_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_5_63                : 59;
+	uint64_t bist                         : 5;  /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         BIST. */
+#else
+	uint64_t bist                         : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} cn63xx;
+	struct cvmx_ciu_bist_cn63xx           cn63xxp1;
+	struct cvmx_ciu_bist_cn61xx           cn66xx;
+	struct cvmx_ciu_bist_s                cn68xx;
+	struct cvmx_ciu_bist_s                cn68xxp1;
+	struct cvmx_ciu_bist_cn61xx           cnf71xx;
 };
 typedef union cvmx_ciu_bist cvmx_ciu_bist_t;
 
@@ -550,13 +1052,16 @@ typedef union cvmx_ciu_bist cvmx_ciu_bist_t;
  *
  * The interrupt lines from the various chip blocks.
  */
-union cvmx_ciu_block_int
-{
+union cvmx_ciu_block_int {
 	uint64_t u64;
-	struct cvmx_ciu_block_int_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_43_63               : 21;
+	struct cvmx_ciu_block_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_62_63               : 2;
+	uint64_t srio3                        : 1;  /**< SRIO3 interrupt
+                                                         See SRIO3_INT_REG, SRIO3_INT2_REG */
+	uint64_t srio2                        : 1;  /**< SRIO2 interrupt
+                                                         See SRIO2_INT_REG, SRIO2_INT2_REG */
+	uint64_t reserved_43_59               : 17;
 	uint64_t ptp                          : 1;  /**< PTP interrupt
                                                          See CIU_INT_SUM1[PTP] */
 	uint64_t dpi                          : 1;  /**< DPI interrupt
@@ -567,7 +1072,213 @@ union cvmx_ciu_block_int
 	uint64_t srio1                        : 1;  /**< SRIO1 interrupt
                                                          See SRIO1_INT_REG */
 	uint64_t srio0                        : 1;  /**< SRIO0 interrupt
-                                                         See SRIO0_INT_REG */
+                                                         See SRIO0_INT_REG, SRIO0_INT2_REG */
+	uint64_t reserved_31_31               : 1;
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t reserved_29_29               : 1;
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_27_27               : 1;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t reserved_24_24               : 1;
+	uint64_t asxpcs1                      : 1;  /**< See PCS1_INT*_REG, PCSX1_INT_REG */
+	uint64_t asxpcs0                      : 1;  /**< See PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t reserved_21_21               : 1;
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t reserved_18_19               : 2;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t reserved_15_15               : 1;
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t reserved_8_8                 : 1;
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t gmx1                         : 1;  /**< GMX1 interrupt
+                                                         See GMX1_RX*_INT_REG, GMX1_TX_INT_REG */
+	uint64_t gmx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+#else
+	uint64_t mio                          : 1;
+	uint64_t gmx0                         : 1;
+	uint64_t gmx1                         : 1;
+	uint64_t sli                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t reserved_8_8                 : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t reserved_15_15               : 1;
+	uint64_t l2c                          : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_18_19               : 2;
+	uint64_t pip                          : 1;
+	uint64_t reserved_21_21               : 1;
+	uint64_t asxpcs0                      : 1;
+	uint64_t asxpcs1                      : 1;
+	uint64_t reserved_24_24               : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t agl                          : 1;
+	uint64_t reserved_29_29               : 1;
+	uint64_t iob                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t srio0                        : 1;
+	uint64_t srio1                        : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfm                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_43_59               : 17;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} s;
+	struct cvmx_ciu_block_int_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_43_63               : 21;
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         See CIU_INT_SUM1[PTP] */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t reserved_31_40               : 10;
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t reserved_29_29               : 1;
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_27_27               : 1;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t reserved_24_24               : 1;
+	uint64_t asxpcs1                      : 1;  /**< See PCS1_INT*_REG, PCSX1_INT_REG */
+	uint64_t asxpcs0                      : 1;  /**< See PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t reserved_21_21               : 1;
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t reserved_18_19               : 2;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t reserved_15_15               : 1;
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t reserved_8_8                 : 1;
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t gmx1                         : 1;  /**< GMX1 interrupt
+                                                         See GMX1_RX*_INT_REG, GMX1_TX_INT_REG */
+	uint64_t gmx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+#else
+	uint64_t mio                          : 1;
+	uint64_t gmx0                         : 1;
+	uint64_t gmx1                         : 1;
+	uint64_t sli                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t reserved_8_8                 : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t reserved_15_15               : 1;
+	uint64_t l2c                          : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_18_19               : 2;
+	uint64_t pip                          : 1;
+	uint64_t reserved_21_21               : 1;
+	uint64_t asxpcs0                      : 1;
+	uint64_t asxpcs1                      : 1;
+	uint64_t reserved_24_24               : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t agl                          : 1;
+	uint64_t reserved_29_29               : 1;
+	uint64_t iob                          : 1;
+	uint64_t reserved_31_40               : 10;
+	uint64_t dpi                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_43_63               : 21;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_block_int_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_43_63               : 21;
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         See CIU_INT_SUM1[PTP] */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t dfm                          : 1;  /**< DFM interrupt
+                                                         See DFM_FNT_STAT */
+	uint64_t reserved_34_39               : 6;
+	uint64_t srio1                        : 1;  /**< SRIO1 interrupt
+                                                         See SRIO1_INT_REG, SRIO1_INT2_REG */
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt
+                                                         See SRIO0_INT_REG, SRIO0_INT2_REG */
 	uint64_t reserved_31_31               : 1;
 	uint64_t iob                          : 1;  /**< IOB interrupt
                                                          See IOB_INT_SUM */
@@ -657,31 +1368,221 @@ union cvmx_ciu_block_int
 	uint64_t ptp                          : 1;
 	uint64_t reserved_43_63               : 21;
 #endif
-	} s;
-	struct cvmx_ciu_block_int_s           cn63xx;
-	struct cvmx_ciu_block_int_s           cn63xxp1;
+	} cn63xx;
+	struct cvmx_ciu_block_int_cn63xx      cn63xxp1;
+	struct cvmx_ciu_block_int_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_62_63               : 2;
+	uint64_t srio3                        : 1;  /**< SRIO3 interrupt
+                                                         See SRIO3_INT_REG, SRIO3_INT2_REG */
+	uint64_t srio2                        : 1;  /**< SRIO2 interrupt
+                                                         See SRIO2_INT_REG, SRIO2_INT2_REG */
+	uint64_t reserved_43_59               : 17;
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         See CIU_INT_SUM1[PTP] */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t dfm                          : 1;  /**< DFM interrupt
+                                                         See DFM_FNT_STAT */
+	uint64_t reserved_33_39               : 7;
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt
+                                                         See SRIO0_INT_REG, SRIO0_INT2_REG */
+	uint64_t reserved_31_31               : 1;
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t reserved_29_29               : 1;
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_27_27               : 1;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t reserved_24_24               : 1;
+	uint64_t asxpcs1                      : 1;  /**< See PCS1_INT*_REG, PCSX1_INT_REG */
+	uint64_t asxpcs0                      : 1;  /**< See PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t reserved_21_21               : 1;
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t reserved_18_19               : 2;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t reserved_15_15               : 1;
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t reserved_8_8                 : 1;
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t gmx1                         : 1;  /**< GMX1 interrupt
+                                                         See GMX1_RX*_INT_REG, GMX1_TX_INT_REG */
+	uint64_t gmx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+#else
+	uint64_t mio                          : 1;
+	uint64_t gmx0                         : 1;
+	uint64_t gmx1                         : 1;
+	uint64_t sli                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t reserved_8_8                 : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t reserved_15_15               : 1;
+	uint64_t l2c                          : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_18_19               : 2;
+	uint64_t pip                          : 1;
+	uint64_t reserved_21_21               : 1;
+	uint64_t asxpcs0                      : 1;
+	uint64_t asxpcs1                      : 1;
+	uint64_t reserved_24_24               : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t agl                          : 1;
+	uint64_t reserved_29_29               : 1;
+	uint64_t iob                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t srio0                        : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t dfm                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_43_59               : 17;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_block_int_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_43_63               : 21;
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         See CIU_INT_SUM1[PTP] */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t reserved_31_40               : 10;
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t reserved_27_29               : 3;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t reserved_23_24               : 2;
+	uint64_t asxpcs0                      : 1;  /**< See PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t reserved_21_21               : 1;
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t reserved_18_19               : 2;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t reserved_15_15               : 1;
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t reserved_6_8                 : 3;
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t gmx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+#else
+	uint64_t mio                          : 1;
+	uint64_t gmx0                         : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t sli                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t reserved_6_8                 : 3;
+	uint64_t ipd                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t reserved_15_15               : 1;
+	uint64_t l2c                          : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_18_19               : 2;
+	uint64_t pip                          : 1;
+	uint64_t reserved_21_21               : 1;
+	uint64_t asxpcs0                      : 1;
+	uint64_t reserved_23_24               : 2;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_27_29               : 3;
+	uint64_t iob                          : 1;
+	uint64_t reserved_31_40               : 10;
+	uint64_t dpi                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_43_63               : 21;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_ciu_block_int cvmx_ciu_block_int_t;
 
 /**
  * cvmx_ciu_dint
  */
-union cvmx_ciu_dint
-{
+union cvmx_ciu_dint {
 	uint64_t u64;
-	struct cvmx_ciu_dint_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_16_63               : 48;
-	uint64_t dint                         : 16; /**< Send DINT pulse to PP vector */
+	struct cvmx_ciu_dint_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t dint                         : 32; /**< Send DINT pulse to PP vector */
 #else
-	uint64_t dint                         : 16;
-	uint64_t reserved_16_63               : 48;
+	uint64_t dint                         : 32;
+	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
-	struct cvmx_ciu_dint_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_dint_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t dint                         : 1;  /**< Send DINT pulse to PP vector */
 #else
@@ -689,9 +1590,8 @@ union cvmx_ciu_dint
 	uint64_t reserved_1_63                : 63;
 #endif
 	} cn30xx;
-	struct cvmx_ciu_dint_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_dint_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t dint                         : 2;  /**< Send DINT pulse to PP vector */
 #else
@@ -699,12 +1599,19 @@ union cvmx_ciu_dint
 	uint64_t reserved_2_63                : 62;
 #endif
 	} cn31xx;
-	struct cvmx_ciu_dint_s                cn38xx;
-	struct cvmx_ciu_dint_s                cn38xxp2;
+	struct cvmx_ciu_dint_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t dint                         : 16; /**< Send DINT pulse to PP vector */
+#else
+	uint64_t dint                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn38xx;
+	struct cvmx_ciu_dint_cn38xx           cn38xxp2;
 	struct cvmx_ciu_dint_cn31xx           cn50xx;
-	struct cvmx_ciu_dint_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_dint_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t dint                         : 4;  /**< Send DINT pulse to PP vector */
 #else
@@ -713,9 +1620,8 @@ union cvmx_ciu_dint
 #endif
 	} cn52xx;
 	struct cvmx_ciu_dint_cn52xx           cn52xxp1;
-	struct cvmx_ciu_dint_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_dint_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t dint                         : 12; /**< Send DINT pulse to PP vector */
 #else
@@ -724,11 +1630,11 @@ union cvmx_ciu_dint
 #endif
 	} cn56xx;
 	struct cvmx_ciu_dint_cn56xx           cn56xxp1;
-	struct cvmx_ciu_dint_s                cn58xx;
-	struct cvmx_ciu_dint_s                cn58xxp1;
-	struct cvmx_ciu_dint_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_dint_cn38xx           cn58xx;
+	struct cvmx_ciu_dint_cn38xx           cn58xxp1;
+	struct cvmx_ciu_dint_cn52xx           cn61xx;
+	struct cvmx_ciu_dint_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t dint                         : 6;  /**< Send DINT pulse to PP vector */
 #else
@@ -737,28 +1643,541 @@ union cvmx_ciu_dint
 #endif
 	} cn63xx;
 	struct cvmx_ciu_dint_cn63xx           cn63xxp1;
+	struct cvmx_ciu_dint_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t dint                         : 10; /**< Send DINT pulse to PP vector */
+#else
+	uint64_t dint                         : 10;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_dint_s                cn68xx;
+	struct cvmx_ciu_dint_s                cn68xxp1;
+	struct cvmx_ciu_dint_cn52xx           cnf71xx;
 };
 typedef union cvmx_ciu_dint cvmx_ciu_dint_t;
 
 /**
+ * cvmx_ciu_en2_io#_int
+ *
+ * Notes:
+ * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
+ *
+ */
+union cvmx_ciu_en2_iox_int {
+	uint64_t u64;
+	struct cvmx_ciu_en2_iox_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t endor                        : 2;  /**< ENDOR PHY interrupts enable */
+	uint64_t eoi                          : 1;  /**< EOI rsl interrupt enable */
+	uint64_t reserved_10_11               : 2;
+	uint64_t timer                        : 6;  /**< General timer 4-9 interrupt enable */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_11               : 2;
+	uint64_t eoi                          : 1;
+	uint64_t endor                        : 2;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_ciu_en2_iox_int_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t timer                        : 6;  /**< General timer 4-9 interrupt enable */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_en2_iox_int_cn61xx    cn66xx;
+	struct cvmx_ciu_en2_iox_int_s         cnf71xx;
+};
+typedef union cvmx_ciu_en2_iox_int cvmx_ciu_en2_iox_int_t;
+
+/**
+ * cvmx_ciu_en2_io#_int_w1c
+ *
+ * Notes:
+ * Write-1-to-clear version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
+ * CIU_EN2_PP(IO)X_IPx(INT) value.
+ */
+union cvmx_ciu_en2_iox_int_w1c {
+	uint64_t u64;
+	struct cvmx_ciu_en2_iox_int_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t endor                        : 2;  /**< Write 1 to clear ENDOR PHY interrupts enable */
+	uint64_t eoi                          : 1;  /**< Write 1 to clear EOI rsl interrupt enable */
+	uint64_t reserved_10_11               : 2;
+	uint64_t timer                        : 6;  /**< Write 1 to clear General timer 4-9 interrupt enable */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_11               : 2;
+	uint64_t eoi                          : 1;
+	uint64_t endor                        : 2;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_ciu_en2_iox_int_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t timer                        : 6;  /**< Write 1 to clear General timer 4-9 interrupt enable */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_en2_iox_int_w1c_cn61xx cn66xx;
+	struct cvmx_ciu_en2_iox_int_w1c_s     cnf71xx;
+};
+typedef union cvmx_ciu_en2_iox_int_w1c cvmx_ciu_en2_iox_int_w1c_t;
+
+/**
+ * cvmx_ciu_en2_io#_int_w1s
+ *
+ * Notes:
+ * Write-1-to-set version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
+ * CIU_EN2_PP(IO)X_IPx(INT) value.
+ */
+union cvmx_ciu_en2_iox_int_w1s {
+	uint64_t u64;
+	struct cvmx_ciu_en2_iox_int_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t endor                        : 2;  /**< Write 1 to set ENDOR PHY interrupts enable */
+	uint64_t eoi                          : 1;  /**< Write 1 to set EOI rsl interrupt enable */
+	uint64_t reserved_10_11               : 2;
+	uint64_t timer                        : 6;  /**< Write 1 to set General timer 4-9 interrupt enables */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_11               : 2;
+	uint64_t eoi                          : 1;
+	uint64_t endor                        : 2;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_ciu_en2_iox_int_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t timer                        : 6;  /**< Write 1 to set General timer 4-9 interrupt enables */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_en2_iox_int_w1s_cn61xx cn66xx;
+	struct cvmx_ciu_en2_iox_int_w1s_s     cnf71xx;
+};
+typedef union cvmx_ciu_en2_iox_int_w1s cvmx_ciu_en2_iox_int_w1s_t;
+
+/**
+ * cvmx_ciu_en2_pp#_ip2
+ *
+ * Notes:
+ * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
+ *
+ */
+union cvmx_ciu_en2_ppx_ip2 {
+	uint64_t u64;
+	struct cvmx_ciu_en2_ppx_ip2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t endor                        : 2;  /**< ENDOR PHY interrupts enable */
+	uint64_t eoi                          : 1;  /**< EOI rsl interrupt enable */
+	uint64_t reserved_10_11               : 2;
+	uint64_t timer                        : 6;  /**< General timer 4-9 interrupt enable */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_11               : 2;
+	uint64_t eoi                          : 1;
+	uint64_t endor                        : 2;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_ciu_en2_ppx_ip2_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t timer                        : 6;  /**< General timer 4-9 interrupt enable */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_en2_ppx_ip2_cn61xx    cn66xx;
+	struct cvmx_ciu_en2_ppx_ip2_s         cnf71xx;
+};
+typedef union cvmx_ciu_en2_ppx_ip2 cvmx_ciu_en2_ppx_ip2_t;
+
+/**
+ * cvmx_ciu_en2_pp#_ip2_w1c
+ *
+ * Notes:
+ * Write-1-to-clear version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
+ * CIU_EN2_PP(IO)X_IPx(INT) value.
+ */
+union cvmx_ciu_en2_ppx_ip2_w1c {
+	uint64_t u64;
+	struct cvmx_ciu_en2_ppx_ip2_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t endor                        : 2;  /**< Write 1 to clear ENDOR PHY interrupts enable */
+	uint64_t eoi                          : 1;  /**< Write 1 to clear EOI rsl interrupt enable */
+	uint64_t reserved_10_11               : 2;
+	uint64_t timer                        : 6;  /**< Write 1 to clear General timer 4-9 interrupt enable */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_11               : 2;
+	uint64_t eoi                          : 1;
+	uint64_t endor                        : 2;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t timer                        : 6;  /**< Write 1 to clear General timer 4-9 interrupt enable */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx cn66xx;
+	struct cvmx_ciu_en2_ppx_ip2_w1c_s     cnf71xx;
+};
+typedef union cvmx_ciu_en2_ppx_ip2_w1c cvmx_ciu_en2_ppx_ip2_w1c_t;
+
+/**
+ * cvmx_ciu_en2_pp#_ip2_w1s
+ *
+ * Notes:
+ * Write-1-to-set version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
+ * CIU_EN2_PP(IO)X_IPx(INT) value.
+ */
+union cvmx_ciu_en2_ppx_ip2_w1s {
+	uint64_t u64;
+	struct cvmx_ciu_en2_ppx_ip2_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t endor                        : 2;  /**< Write 1 to set ENDOR PHY interrupts enable */
+	uint64_t eoi                          : 1;  /**< Write 1 to set EOI rsl interrupt enable */
+	uint64_t reserved_10_11               : 2;
+	uint64_t timer                        : 6;  /**< Write 1 to set General timer 4-9 interrupt enables */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_11               : 2;
+	uint64_t eoi                          : 1;
+	uint64_t endor                        : 2;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t timer                        : 6;  /**< Write 1 to set General timer 4-9 interrupt enables */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx cn66xx;
+	struct cvmx_ciu_en2_ppx_ip2_w1s_s     cnf71xx;
+};
+typedef union cvmx_ciu_en2_ppx_ip2_w1s cvmx_ciu_en2_ppx_ip2_w1s_t;
+
+/**
+ * cvmx_ciu_en2_pp#_ip3
+ *
+ * Notes:
+ * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
+ *
+ */
+union cvmx_ciu_en2_ppx_ip3 {
+	uint64_t u64;
+	struct cvmx_ciu_en2_ppx_ip3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t endor                        : 2;  /**< ENDOR PHY interrupts enable */
+	uint64_t eoi                          : 1;  /**< EOI rsl interrupt enable */
+	uint64_t reserved_10_11               : 2;
+	uint64_t timer                        : 6;  /**< General timer 4-9 interrupt enable */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_11               : 2;
+	uint64_t eoi                          : 1;
+	uint64_t endor                        : 2;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_ciu_en2_ppx_ip3_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t timer                        : 6;  /**< General timer 4-9 interrupt enable */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_en2_ppx_ip3_cn61xx    cn66xx;
+	struct cvmx_ciu_en2_ppx_ip3_s         cnf71xx;
+};
+typedef union cvmx_ciu_en2_ppx_ip3 cvmx_ciu_en2_ppx_ip3_t;
+
+/**
+ * cvmx_ciu_en2_pp#_ip3_w1c
+ *
+ * Notes:
+ * Write-1-to-clear version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
+ * CIU_EN2_PP(IO)X_IPx(INT) value.
+ */
+union cvmx_ciu_en2_ppx_ip3_w1c {
+	uint64_t u64;
+	struct cvmx_ciu_en2_ppx_ip3_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t endor                        : 2;  /**< Write 1 to clear ENDOR PHY interrupts enable */
+	uint64_t eoi                          : 1;  /**< Write 1 to clear EOI rsl interrupt enable */
+	uint64_t reserved_10_11               : 2;
+	uint64_t timer                        : 6;  /**< Write 1 to clear General timer 4-9 interrupt enable */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_11               : 2;
+	uint64_t eoi                          : 1;
+	uint64_t endor                        : 2;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t timer                        : 6;  /**< Write 1 to clear General timer 4-9 interrupt enable */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx cn66xx;
+	struct cvmx_ciu_en2_ppx_ip3_w1c_s     cnf71xx;
+};
+typedef union cvmx_ciu_en2_ppx_ip3_w1c cvmx_ciu_en2_ppx_ip3_w1c_t;
+
+/**
+ * cvmx_ciu_en2_pp#_ip3_w1s
+ *
+ * Notes:
+ * Write-1-to-set version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
+ * CIU_EN2_PP(IO)X_IPx(INT) value.
+ */
+union cvmx_ciu_en2_ppx_ip3_w1s {
+	uint64_t u64;
+	struct cvmx_ciu_en2_ppx_ip3_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t endor                        : 2;  /**< Write 1 to set ENDOR PHY interrupts enable */
+	uint64_t eoi                          : 1;  /**< Write 1 to set EOI rsl interrupt enable */
+	uint64_t reserved_10_11               : 2;
+	uint64_t timer                        : 6;  /**< Write 1 to set General timer 4-9 interrupt enables */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_11               : 2;
+	uint64_t eoi                          : 1;
+	uint64_t endor                        : 2;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t timer                        : 6;  /**< Write 1 to set General timer 4-9 interrupt enables */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx cn66xx;
+	struct cvmx_ciu_en2_ppx_ip3_w1s_s     cnf71xx;
+};
+typedef union cvmx_ciu_en2_ppx_ip3_w1s cvmx_ciu_en2_ppx_ip3_w1s_t;
+
+/**
+ * cvmx_ciu_en2_pp#_ip4
+ *
+ * Notes:
+ * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
+ *
+ */
+union cvmx_ciu_en2_ppx_ip4 {
+	uint64_t u64;
+	struct cvmx_ciu_en2_ppx_ip4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t endor                        : 2;  /**< ENDOR PHY interrupts enable */
+	uint64_t eoi                          : 1;  /**< EOI rsl interrupt enable */
+	uint64_t reserved_10_11               : 2;
+	uint64_t timer                        : 6;  /**< General timer 4-9 interrupt enable */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_11               : 2;
+	uint64_t eoi                          : 1;
+	uint64_t endor                        : 2;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_ciu_en2_ppx_ip4_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t timer                        : 6;  /**< General timer 4-9 interrupt enable */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_en2_ppx_ip4_cn61xx    cn66xx;
+	struct cvmx_ciu_en2_ppx_ip4_s         cnf71xx;
+};
+typedef union cvmx_ciu_en2_ppx_ip4 cvmx_ciu_en2_ppx_ip4_t;
+
+/**
+ * cvmx_ciu_en2_pp#_ip4_w1c
+ *
+ * Notes:
+ * Write-1-to-clear version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
+ * CIU_EN2_PP(IO)X_IPx(INT) value.
+ */
+union cvmx_ciu_en2_ppx_ip4_w1c {
+	uint64_t u64;
+	struct cvmx_ciu_en2_ppx_ip4_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t endor                        : 2;  /**< Write 1 to clear ENDOR PHY interrupts enable */
+	uint64_t eoi                          : 1;  /**< Write 1 to clear EOI rsl interrupt enable */
+	uint64_t reserved_10_11               : 2;
+	uint64_t timer                        : 6;  /**< Write 1 to clear General timer 4-9 interrupt enable */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_11               : 2;
+	uint64_t eoi                          : 1;
+	uint64_t endor                        : 2;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t timer                        : 6;  /**< Write 1 to clear General timer 4-9 interrupt enable */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx cn66xx;
+	struct cvmx_ciu_en2_ppx_ip4_w1c_s     cnf71xx;
+};
+typedef union cvmx_ciu_en2_ppx_ip4_w1c cvmx_ciu_en2_ppx_ip4_w1c_t;
+
+/**
+ * cvmx_ciu_en2_pp#_ip4_w1s
+ *
+ * Notes:
+ * Write-1-to-set version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
+ * CIU_EN2_PP(IO)X_IPx(INT) value.
+ */
+union cvmx_ciu_en2_ppx_ip4_w1s {
+	uint64_t u64;
+	struct cvmx_ciu_en2_ppx_ip4_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t endor                        : 2;  /**< Write 1 to set ENDOR PHY interrupts enable */
+	uint64_t eoi                          : 1;  /**< Write 1 to set EOI rsl interrupt enable */
+	uint64_t reserved_10_11               : 2;
+	uint64_t timer                        : 6;  /**< Write 1 to set General timer 4-9 interrupt enables */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_11               : 2;
+	uint64_t eoi                          : 1;
+	uint64_t endor                        : 2;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t timer                        : 6;  /**< Write 1 to set General timer 4-9 interrupt enables */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx cn66xx;
+	struct cvmx_ciu_en2_ppx_ip4_w1s_s     cnf71xx;
+};
+typedef union cvmx_ciu_en2_ppx_ip4_w1s cvmx_ciu_en2_ppx_ip4_w1s_t;
+
+/**
  * cvmx_ciu_fuse
  */
-union cvmx_ciu_fuse
-{
+union cvmx_ciu_fuse {
 	uint64_t u64;
-	struct cvmx_ciu_fuse_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_16_63               : 48;
-	uint64_t fuse                         : 16; /**< Physical PP is present */
+	struct cvmx_ciu_fuse_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t fuse                         : 32; /**< Physical PP is present */
 #else
-	uint64_t fuse                         : 16;
-	uint64_t reserved_16_63               : 48;
+	uint64_t fuse                         : 32;
+	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
-	struct cvmx_ciu_fuse_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_fuse_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t fuse                         : 1;  /**< Physical PP is present */
 #else
@@ -766,9 +2185,8 @@ union cvmx_ciu_fuse
 	uint64_t reserved_1_63                : 63;
 #endif
 	} cn30xx;
-	struct cvmx_ciu_fuse_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_fuse_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t fuse                         : 2;  /**< Physical PP is present */
 #else
@@ -776,12 +2194,19 @@ union cvmx_ciu_fuse
 	uint64_t reserved_2_63                : 62;
 #endif
 	} cn31xx;
-	struct cvmx_ciu_fuse_s                cn38xx;
-	struct cvmx_ciu_fuse_s                cn38xxp2;
+	struct cvmx_ciu_fuse_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t fuse                         : 16; /**< Physical PP is present */
+#else
+	uint64_t fuse                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn38xx;
+	struct cvmx_ciu_fuse_cn38xx           cn38xxp2;
 	struct cvmx_ciu_fuse_cn31xx           cn50xx;
-	struct cvmx_ciu_fuse_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_fuse_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t fuse                         : 4;  /**< Physical PP is present */
 #else
@@ -790,9 +2215,8 @@ union cvmx_ciu_fuse
 #endif
 	} cn52xx;
 	struct cvmx_ciu_fuse_cn52xx           cn52xxp1;
-	struct cvmx_ciu_fuse_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_fuse_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t fuse                         : 12; /**< Physical PP is present */
 #else
@@ -801,11 +2225,11 @@ union cvmx_ciu_fuse
 #endif
 	} cn56xx;
 	struct cvmx_ciu_fuse_cn56xx           cn56xxp1;
-	struct cvmx_ciu_fuse_s                cn58xx;
-	struct cvmx_ciu_fuse_s                cn58xxp1;
-	struct cvmx_ciu_fuse_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_fuse_cn38xx           cn58xx;
+	struct cvmx_ciu_fuse_cn38xx           cn58xxp1;
+	struct cvmx_ciu_fuse_cn52xx           cn61xx;
+	struct cvmx_ciu_fuse_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t fuse                         : 6;  /**< Physical PP is present */
 #else
@@ -814,18 +2238,28 @@ union cvmx_ciu_fuse
 #endif
 	} cn63xx;
 	struct cvmx_ciu_fuse_cn63xx           cn63xxp1;
+	struct cvmx_ciu_fuse_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t fuse                         : 10; /**< Physical PP is present */
+#else
+	uint64_t fuse                         : 10;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_fuse_s                cn68xx;
+	struct cvmx_ciu_fuse_s                cn68xxp1;
+	struct cvmx_ciu_fuse_cn52xx           cnf71xx;
 };
 typedef union cvmx_ciu_fuse cvmx_ciu_fuse_t;
 
 /**
  * cvmx_ciu_gstop
  */
-union cvmx_ciu_gstop
-{
+union cvmx_ciu_gstop {
 	uint64_t u64;
-	struct cvmx_ciu_gstop_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_gstop_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t gstop                        : 1;  /**< GSTOP bit */
 #else
@@ -844,8 +2278,13 @@ union cvmx_ciu_gstop
 	struct cvmx_ciu_gstop_s               cn56xxp1;
 	struct cvmx_ciu_gstop_s               cn58xx;
 	struct cvmx_ciu_gstop_s               cn58xxp1;
+	struct cvmx_ciu_gstop_s               cn61xx;
 	struct cvmx_ciu_gstop_s               cn63xx;
 	struct cvmx_ciu_gstop_s               cn63xxp1;
+	struct cvmx_ciu_gstop_s               cn66xx;
+	struct cvmx_ciu_gstop_s               cn68xx;
+	struct cvmx_ciu_gstop_s               cn68xxp1;
+	struct cvmx_ciu_gstop_s               cnf71xx;
 };
 typedef union cvmx_ciu_gstop cvmx_ciu_gstop_t;
 
@@ -853,27 +2292,31 @@ typedef union cvmx_ciu_gstop cvmx_ciu_gstop_t;
  * cvmx_ciu_int#_en0
  *
  * Notes:
- * CIU_INT0_EN0:  PP0 /IP2
- * CIU_INT1_EN0:  PP0 /IP3
- * ...
+ * CIU_INT0_EN0:  PP0/IP2
+ * CIU_INT1_EN0:  PP0/IP3
+ * CIU_INT2_EN0:  PP1/IP2
+ * CIU_INT3_EN0:  PP1/IP3
+ * CIU_INT4_EN0:  PP2/IP2
+ * CIU_INT5_EN0:  PP2/IP3
  * CIU_INT6_EN0:  PP3/IP2
  * CIU_INT7_EN0:  PP3/IP3
+ * .....
+ *
  * (hole)
- * CIU_INT32_EN0: PCI /IP
+ * CIU_INT32_EN0: IO 0
+ * CIU_INT33_EN0: IO 1
  */
-union cvmx_ciu_intx_en0
-{
+union cvmx_ciu_intx_en0 {
 	uint64_t u64;
-	struct cvmx_ciu_intx_en0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt enable */
 	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface 0 Interrupt enable */
 	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt enable */
 	uint64_t powiq                        : 1;  /**< POW IQ interrupt enable */
 	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt enable */
-	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
-	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt enable */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt enable */
 	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt enable */
 	uint64_t timer                        : 4;  /**< General timer interrupt enables */
 	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
@@ -883,10 +2326,10 @@ union cvmx_ciu_intx_en0
 	uint64_t rml                          : 1;  /**< RML Interrupt enable */
 	uint64_t twsi                         : 1;  /**< TWSI Interrupt enable */
 	uint64_t reserved_44_44               : 1;
-	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI enables */
+	uint64_t pci_msi                      : 4;  /**< PCIe MSI enables */
 	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D enables */
 	uint64_t uart                         : 2;  /**< Two UART interrupt enables */
-	uint64_t mbox                         : 2;  /**< Two mailbox/PCIe/sRIO interrupt enables */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCIe interrupt enables */
 	uint64_t gpio                         : 16; /**< 16 GPIO interrupt enables */
 	uint64_t workq                        : 16; /**< 16 work queue interrupt enables */
 #else
@@ -914,9 +2357,8 @@ union cvmx_ciu_intx_en0
 	uint64_t bootdma                      : 1;
 #endif
 	} s;
-	struct cvmx_ciu_intx_en0_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en0_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_59_63               : 5;
 	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
 	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
@@ -958,9 +2400,8 @@ union cvmx_ciu_intx_en0
 	uint64_t reserved_59_63               : 5;
 #endif
 	} cn30xx;
-	struct cvmx_ciu_intx_en0_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en0_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_59_63               : 5;
 	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
 	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
@@ -1002,9 +2443,8 @@ union cvmx_ciu_intx_en0
 	uint64_t reserved_59_63               : 5;
 #endif
 	} cn31xx;
-	struct cvmx_ciu_intx_en0_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en0_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_56_63               : 8;
 	uint64_t timer                        : 4;  /**< General timer interrupts */
 	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
@@ -1040,9 +2480,8 @@ union cvmx_ciu_intx_en0
 	} cn38xx;
 	struct cvmx_ciu_intx_en0_cn38xx       cn38xxp2;
 	struct cvmx_ciu_intx_en0_cn30xx       cn50xx;
-	struct cvmx_ciu_intx_en0_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en0_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
 	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
 	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
@@ -1091,9 +2530,8 @@ union cvmx_ciu_intx_en0
 #endif
 	} cn52xx;
 	struct cvmx_ciu_intx_en0_cn52xx       cn52xxp1;
-	struct cvmx_ciu_intx_en0_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en0_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
 	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
 	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
@@ -1142,8 +2580,157 @@ union cvmx_ciu_intx_en0
 	struct cvmx_ciu_intx_en0_cn56xx       cn56xxp1;
 	struct cvmx_ciu_intx_en0_cn38xx       cn58xx;
 	struct cvmx_ciu_intx_en0_cn38xx       cn58xxp1;
+	struct cvmx_ciu_intx_en0_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt enable */
+	uint64_t mii                          : 1;  /**< RGMII/MIX Interface 0 Interrupt enable */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt enable */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt enable */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt enable */
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< General timer interrupt enables */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt enable */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCIe MSI enables */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Two UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCIe interrupt enables */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< 16 work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn61xx;
 	struct cvmx_ciu_intx_en0_cn52xx       cn63xx;
 	struct cvmx_ciu_intx_en0_cn52xx       cn63xxp1;
+	struct cvmx_ciu_intx_en0_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt enable */
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface 0 Interrupt enable */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt enable */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt enable */
+	uint64_t reserved_57_57               : 1;
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< General timer interrupt enables */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt enable */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI enables */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Two UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCIe/sRIO interrupt enables */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< 16 work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_57               : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_intx_en0_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt enable */
+	uint64_t reserved_62_62               : 1;
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt enable */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt enable */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt enable */
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< General timer interrupt enables */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt enable */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCIe MSI enables */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Two UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCIe interrupt enables */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< 16 work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_ciu_intx_en0 cvmx_ciu_intx_en0_t;
 
@@ -1151,26 +2738,25 @@ typedef union cvmx_ciu_intx_en0 cvmx_ciu_intx_en0_t;
  * cvmx_ciu_int#_en0_w1c
  *
  * Notes:
- * Write-1-to-clear version of the CIU_INTx_EN0 register
+ * Write-1-to-clear version of the CIU_INTx_EN0 register, read back corresponding CIU_INTx_EN0 value.
  *
  */
-union cvmx_ciu_intx_en0_w1c
-{
+union cvmx_ciu_intx_en0_w1c {
 	uint64_t u64;
-	struct cvmx_ciu_intx_en0_w1c_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en0_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Write 1 to clear Boot bus DMA engines Interrupt
                                                          enable */
 	uint64_t mii                          : 1;  /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt
                                                          enable */
 	uint64_t ipdppthr                     : 1;  /**< Write 1 to clear IPD per-port counter threshold
                                                          interrupt enable */
-	uint64_t powiq                        : 1;  /**< Write 1 to clear POW IQ interrupt */
-	uint64_t twsi2                        : 1;  /**< Write 1 to clear 2nd TWSI Interrupt */
-	uint64_t reserved_57_58               : 2;
-	uint64_t usb                          : 1;  /**< Write 1 to clear USB EHCI or OHCI Interrupt */
-	uint64_t timer                        : 4;  /**< Write 1 to clear General timer interrupts */
+	uint64_t powiq                        : 1;  /**< Write 1 to clear POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< Write 1 to clear 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< Write 1 to clear MPI/SPI interrupt enable */
+	uint64_t pcm                          : 1;  /**< Write 1 to clear PCM/TDM interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< Write 1 to clear General timer interrupt enables */
 	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
 	uint64_t ipd_drp                      : 1;  /**< Write 1 to clear IPD QOS packet drop interrupt
                                                          enable */
@@ -1179,10 +2765,10 @@ union cvmx_ciu_intx_en0_w1c
 	uint64_t rml                          : 1;  /**< Write 1 to clear RML Interrupt enable */
 	uint64_t twsi                         : 1;  /**< Write 1 to clear TWSI Interrupt enable */
 	uint64_t reserved_44_44               : 1;
-	uint64_t pci_msi                      : 4;  /**< Write 1s to clear PCIe/sRIO MSI enables */
+	uint64_t pci_msi                      : 4;  /**< Write 1s to clear PCIe MSI enables */
 	uint64_t pci_int                      : 4;  /**< Write 1s to clear PCIe INTA/B/C/D enables */
 	uint64_t uart                         : 2;  /**< Write 1s to clear UART interrupt enables */
-	uint64_t mbox                         : 2;  /**< Write 1s to clear mailbox/PCIe/sRIO interrupt
+	uint64_t mbox                         : 2;  /**< Write 1s to clear mailbox/PCIe interrupt
                                                          enables */
 	uint64_t gpio                         : 16; /**< Write 1s to clear GPIO interrupt enables */
 	uint64_t workq                        : 16; /**< Write 1s to clear work queue interrupt enables */
@@ -1202,7 +2788,8 @@ union cvmx_ciu_intx_en0_w1c
 	uint64_t key_zero                     : 1;
 	uint64_t timer                        : 4;
 	uint64_t usb                          : 1;
-	uint64_t reserved_57_58               : 2;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
 	uint64_t twsi2                        : 1;
 	uint64_t powiq                        : 1;
 	uint64_t ipdppthr                     : 1;
@@ -1210,9 +2797,8 @@ union cvmx_ciu_intx_en0_w1c
 	uint64_t bootdma                      : 1;
 #endif
 	} s;
-	struct cvmx_ciu_intx_en0_w1c_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en0_w1c_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
 	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
 	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
@@ -1260,10 +2846,55 @@ union cvmx_ciu_intx_en0_w1c
 	uint64_t bootdma                      : 1;
 #endif
 	} cn52xx;
-	struct cvmx_ciu_intx_en0_w1c_s        cn56xx;
-	struct cvmx_ciu_intx_en0_w1c_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en0_w1c_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
+	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< USB Interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_intx_en0_w1c_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_56_63               : 8;
 	uint64_t timer                        : 4;  /**< General timer interrupts */
 	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
@@ -1297,8 +2928,171 @@ union cvmx_ciu_intx_en0_w1c
 	uint64_t reserved_56_63               : 8;
 #endif
 	} cn58xx;
+	struct cvmx_ciu_intx_en0_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Write 1 to clear Boot bus DMA engines Interrupt
+                                                         enable */
+	uint64_t mii                          : 1;  /**< Write 1 to clr RGMII/MIX Interface 0 Interrupt
+                                                         enable */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to clear IPD per-port counter threshold
+                                                         interrupt enable */
+	uint64_t powiq                        : 1;  /**< Write 1 to clear POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< Write 1 to clear 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< Write 1 to clear MPI/SPI interrupt enable */
+	uint64_t pcm                          : 1;  /**< Write 1 to clear PCM/TDM interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< Write 1 to clear General timer interrupt enables */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to clear IPD QOS packet drop interrupt
+                                                         enable */
+	uint64_t gmx_drp                      : 2;  /**< Write 1 to clear GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Write 1 to clear Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< Write 1 to clear RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< Write 1 to clear TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< Write 1s to clear PCIe MSI enables */
+	uint64_t pci_int                      : 4;  /**< Write 1s to clear PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Write 1s to clear UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Write 1s to clear mailbox/PCIe interrupt
+                                                         enables */
+	uint64_t gpio                         : 16; /**< Write 1s to clear GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< Write 1s to clear work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn61xx;
 	struct cvmx_ciu_intx_en0_w1c_cn52xx   cn63xx;
 	struct cvmx_ciu_intx_en0_w1c_cn52xx   cn63xxp1;
+	struct cvmx_ciu_intx_en0_w1c_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Write 1 to clear Boot bus DMA engines Interrupt
+                                                         enable */
+	uint64_t mii                          : 1;  /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt
+                                                         enable */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to clear IPD per-port counter threshold
+                                                         interrupt enable */
+	uint64_t powiq                        : 1;  /**< Write 1 to clear POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< Write 1 to clear 2nd TWSI Interrupt */
+	uint64_t mpi                          : 1;  /**< Write 1 to clear MPI/SPI interrupt */
+	uint64_t reserved_57_57               : 1;
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB EHCI or OHCI Interrupt */
+	uint64_t timer                        : 4;  /**< Write 1 to clear General timer interrupts */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to clear IPD QOS packet drop interrupt
+                                                         enable */
+	uint64_t gmx_drp                      : 2;  /**< Write 1 to clear GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Write 1 to clear Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< Write 1 to clear RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< Write 1 to clear TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< Write 1s to clear PCIe/sRIO MSI enables */
+	uint64_t pci_int                      : 4;  /**< Write 1s to clear PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Write 1s to clear UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Write 1s to clear mailbox/PCIe/sRIO interrupt
+                                                         enables */
+	uint64_t gpio                         : 16; /**< Write 1s to clear GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< Write 1s to clear work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_57               : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_intx_en0_w1c_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Write 1 to clear Boot bus DMA engines Interrupt
+                                                         enable */
+	uint64_t reserved_62_62               : 1;
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to clear IPD per-port counter threshold
+                                                         interrupt enable */
+	uint64_t powiq                        : 1;  /**< Write 1 to clear POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< Write 1 to clear 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< Write 1 to clear MPI/SPI interrupt enable */
+	uint64_t pcm                          : 1;  /**< Write 1 to clear PCM/TDM interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< Write 1 to clear General timer interrupt enables */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to clear IPD QOS packet drop interrupt
+                                                         enable */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< Write 1 to clear GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Write 1 to clear Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< Write 1 to clear RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< Write 1 to clear TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< Write 1s to clear PCIe MSI enables */
+	uint64_t pci_int                      : 4;  /**< Write 1s to clear PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Write 1s to clear UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Write 1s to clear mailbox/PCIe interrupt
+                                                         enables */
+	uint64_t gpio                         : 16; /**< Write 1s to clear GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< Write 1s to clear work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_ciu_intx_en0_w1c cvmx_ciu_intx_en0_w1c_t;
 
@@ -1306,26 +3100,25 @@ typedef union cvmx_ciu_intx_en0_w1c cvmx_ciu_intx_en0_w1c_t;
  * cvmx_ciu_int#_en0_w1s
  *
  * Notes:
- * Write-1-to-set version of the CIU_INTx_EN0 register
+ * Write-1-to-set version of the CIU_INTx_EN0 register, read back corresponding CIU_INTx_EN0 value.
  *
  */
-union cvmx_ciu_intx_en0_w1s
-{
+union cvmx_ciu_intx_en0_w1s {
 	uint64_t u64;
-	struct cvmx_ciu_intx_en0_w1s_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en0_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Write 1 to set Boot bus DMA engines Interrupt
                                                          enable */
 	uint64_t mii                          : 1;  /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt
                                                          enable */
 	uint64_t ipdppthr                     : 1;  /**< Write 1 to set IPD per-port counter threshold
                                                          interrupt enable */
-	uint64_t powiq                        : 1;  /**< Write 1 to set POW IQ interrupt */
-	uint64_t twsi2                        : 1;  /**< Write 1 to set 2nd TWSI Interrupt */
-	uint64_t reserved_57_58               : 2;
-	uint64_t usb                          : 1;  /**< Write 1 to set USB EHCI or OHCI Interrupt */
-	uint64_t timer                        : 4;  /**< Write 1 to set General timer interrupts */
+	uint64_t powiq                        : 1;  /**< Write 1 to set POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< Write 1 to set 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< Write 1 to set MPI/SPI interrupt enable */
+	uint64_t pcm                          : 1;  /**< Write 1 to set PCM/TDM interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to set USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< Write 1 to set General timer interrupt enables */
 	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
 	uint64_t ipd_drp                      : 1;  /**< Write 1 to set IPD QOS packet drop interrupt
                                                          enable */
@@ -1334,10 +3127,10 @@ union cvmx_ciu_intx_en0_w1s
 	uint64_t rml                          : 1;  /**< Write 1 to set RML Interrupt enable */
 	uint64_t twsi                         : 1;  /**< Write 1 to set TWSI Interrupt enable */
 	uint64_t reserved_44_44               : 1;
-	uint64_t pci_msi                      : 4;  /**< Write 1s to set PCIe/sRIO MSI enables */
+	uint64_t pci_msi                      : 4;  /**< Write 1s to set PCIe MSI enables */
 	uint64_t pci_int                      : 4;  /**< Write 1s to set PCIe INTA/B/C/D enables */
 	uint64_t uart                         : 2;  /**< Write 1s to set UART interrupt enables */
-	uint64_t mbox                         : 2;  /**< Write 1s to set mailbox/PCIe/sRIO interrupt
+	uint64_t mbox                         : 2;  /**< Write 1s to set mailbox/PCIe interrupt
                                                          enables */
 	uint64_t gpio                         : 16; /**< Write 1s to set GPIO interrupt enables */
 	uint64_t workq                        : 16; /**< Write 1s to set work queue interrupt enables */
@@ -1357,7 +3150,8 @@ union cvmx_ciu_intx_en0_w1s
 	uint64_t key_zero                     : 1;
 	uint64_t timer                        : 4;
 	uint64_t usb                          : 1;
-	uint64_t reserved_57_58               : 2;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
 	uint64_t twsi2                        : 1;
 	uint64_t powiq                        : 1;
 	uint64_t ipdppthr                     : 1;
@@ -1365,9 +3159,8 @@ union cvmx_ciu_intx_en0_w1s
 	uint64_t bootdma                      : 1;
 #endif
 	} s;
-	struct cvmx_ciu_intx_en0_w1s_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en0_w1s_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
 	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
 	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
@@ -1415,10 +3208,55 @@ union cvmx_ciu_intx_en0_w1s
 	uint64_t bootdma                      : 1;
 #endif
 	} cn52xx;
-	struct cvmx_ciu_intx_en0_w1s_s        cn56xx;
-	struct cvmx_ciu_intx_en0_w1s_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en0_w1s_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
+	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< USB Interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_intx_en0_w1s_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_56_63               : 8;
 	uint64_t timer                        : 4;  /**< General timer interrupts */
 	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
@@ -1452,8 +3290,171 @@ union cvmx_ciu_intx_en0_w1s
 	uint64_t reserved_56_63               : 8;
 #endif
 	} cn58xx;
+	struct cvmx_ciu_intx_en0_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Write 1 to set Boot bus DMA engines Interrupt
+                                                         enable */
+	uint64_t mii                          : 1;  /**< Write 1 to set RGMII/MIX Interface 0 Interrupt
+                                                         enable */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to set IPD per-port counter threshold
+                                                         interrupt enable */
+	uint64_t powiq                        : 1;  /**< Write 1 to set POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< Write 1 to set 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< Write 1 to set MPI/SPI interrupt enable */
+	uint64_t pcm                          : 1;  /**< Write 1 to set PCM/TDM interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to set USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< Write 1 to set General timer interrupt enables */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to set IPD QOS packet drop interrupt
+                                                         enable */
+	uint64_t gmx_drp                      : 2;  /**< Write 1 to set GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Write 1 to set Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< Write 1 to set RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< Write 1 to set TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< Write 1s to set PCIe MSI enables */
+	uint64_t pci_int                      : 4;  /**< Write 1s to set PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Write 1s to set UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Write 1s to set mailbox/PCIe interrupt
+                                                         enables */
+	uint64_t gpio                         : 16; /**< Write 1s to set GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< Write 1s to set work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn61xx;
 	struct cvmx_ciu_intx_en0_w1s_cn52xx   cn63xx;
 	struct cvmx_ciu_intx_en0_w1s_cn52xx   cn63xxp1;
+	struct cvmx_ciu_intx_en0_w1s_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Write 1 to set Boot bus DMA engines Interrupt
+                                                         enable */
+	uint64_t mii                          : 1;  /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt
+                                                         enable */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to set IPD per-port counter threshold
+                                                         interrupt enable */
+	uint64_t powiq                        : 1;  /**< Write 1 to set POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< Write 1 to set 2nd TWSI Interrupt */
+	uint64_t mpi                          : 1;  /**< Write 1 to set MPI/SPI interrupt */
+	uint64_t reserved_57_57               : 1;
+	uint64_t usb                          : 1;  /**< Write 1 to set USB EHCI or OHCI Interrupt */
+	uint64_t timer                        : 4;  /**< Write 1 to set General timer interrupts */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to set IPD QOS packet drop interrupt
+                                                         enable */
+	uint64_t gmx_drp                      : 2;  /**< Write 1 to set GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Write 1 to set Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< Write 1 to set RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< Write 1 to set TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< Write 1s to set PCIe/sRIO MSI enables */
+	uint64_t pci_int                      : 4;  /**< Write 1s to set PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Write 1s to set UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Write 1s to set mailbox/PCIe/sRIO interrupt
+                                                         enables */
+	uint64_t gpio                         : 16; /**< Write 1s to set GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< Write 1s to set work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_57               : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_intx_en0_w1s_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Write 1 to set Boot bus DMA engines Interrupt
+                                                         enable */
+	uint64_t reserved_62_62               : 1;
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to set IPD per-port counter threshold
+                                                         interrupt enable */
+	uint64_t powiq                        : 1;  /**< Write 1 to set POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< Write 1 to set 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< Write 1 to set MPI/SPI interrupt enable */
+	uint64_t pcm                          : 1;  /**< Write 1 to set PCM/TDM interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to set USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< Write 1 to set General timer interrupt enables */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to set IPD QOS packet drop interrupt
+                                                         enable */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< Write 1 to set GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Write 1 to set Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< Write 1 to set RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< Write 1 to set TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< Write 1s to set PCIe MSI enables */
+	uint64_t pci_int                      : 4;  /**< Write 1s to set PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Write 1s to set UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Write 1s to set mailbox/PCIe interrupt
+                                                         enables */
+	uint64_t gpio                         : 16; /**< Write 1s to set GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< Write 1s to set work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_ciu_intx_en0_w1s cvmx_ciu_intx_en0_w1s_t;
 
@@ -1461,30 +3462,47 @@ typedef union cvmx_ciu_intx_en0_w1s cvmx_ciu_intx_en0_w1s_t;
  * cvmx_ciu_int#_en1
  *
  * Notes:
+ * Enables for CIU_SUM1_PPX_IPx  or CIU_SUM1_IOX_INT
+ * CIU_INT0_EN1:  PP0/IP2
+ * CIU_INT1_EN1:  PP0/IP3
+ * CIU_INT2_EN1:  PP1/IP2
+ * CIU_INT3_EN1:  PP1/IP3
+ * CIU_INT4_EN1:  PP2/IP2
+ * CIU_INT5_EN1:  PP2/IP3
+ * CIU_INT6_EN1:  PP3/IP2
+ * CIU_INT7_EN1:  PP3/IP3
+ * .....
+ *
+ * (hole)
+ * CIU_INT32_EN1: IO0
+ * CIU_INT33_EN1: IO1
+ *
  * @verbatim
  * PPx/IP2 will be raised when...
  *
  *    n = x*2
- *    PPx/IP2 = |([CIU_INT_SUM1, CIU_INTn_SUM0] & [CIU_INTn_EN1, CIU_INTn_EN0])
+ *    PPx/IP2 = |([CIU_SUM2_PPx_IP2,CIU_SUM1_PPx_IP2, CIU_INTn_SUM0] & [CIU_EN2_PPx_IP2,CIU_INTn_EN1, CIU_INTn_EN0])
  *
  * PPx/IP3 will be raised when...
  *
  *    n = x*2 + 1
- *    PPx/IP3 =  |([CIU_INT_SUM1, CIU_INTn_SUM0] & [CIU_INTn_EN1, CIU_INTn_EN0])
+ *    PPx/IP3 =  |([CIU_SUM2_PPx_IP3,CIU_SUM1_PPx_IP3, CIU_INTn_SUM0] & [CIU_EN2_PPx_IP3,CIU_INTn_EN1, CIU_INTn_EN0])
  *
  * PCI/INT will be raised when...
  *
- *    PCI/INT = |([CIU_INT_SUM1, CIU_INT32_SUM0] & [CIU_INT32_EN1, CIU_INT32_EN0])
+ *    PCI/INT = |([CIU_SUM2_IO0_INT,CIU_SUM1_IO0_INT, CIU_INT32_SUM0] & [CIU_EN2_IO0_INT,CIU_INT32_EN1, CIU_INT32_EN0])
+ *    PCI/INT = |([CIU_SUM2_IO1_INT,CIU_SUM1_IO1_INT, CIU_INT33_SUM0] & [CIU_EN2_IO1_INT,CIU_INT33_EN1, CIU_INT33_EN0])
  * @endverbatim
  */
-union cvmx_ciu_intx_en1
-{
+union cvmx_ciu_intx_en1 {
 	uint64_t u64;
-	struct cvmx_ciu_intx_en1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rst                          : 1;  /**< MIO RST interrupt enable */
-	uint64_t reserved_57_62               : 6;
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< SRIO3 interrupt enable */
+	uint64_t srio2                        : 1;  /**< SRIO2 interrupt enable */
+	uint64_t reserved_57_59               : 3;
 	uint64_t dfm                          : 1;  /**< DFM interrupt enable */
 	uint64_t reserved_53_55               : 3;
 	uint64_t lmc0                         : 1;  /**< LMC0 interrupt enable */
@@ -1494,7 +3512,10 @@ union cvmx_ciu_intx_en1
 	uint64_t pem0                         : 1;  /**< PEM0 interrupt enable */
 	uint64_t ptp                          : 1;  /**< PTP interrupt enable */
 	uint64_t agl                          : 1;  /**< AGL interrupt enable */
-	uint64_t reserved_37_45               : 9;
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< DPI_DMA interrupt enable */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt enable */
 	uint64_t agx0                         : 1;  /**< GMX0 interrupt enable */
 	uint64_t dpi                          : 1;  /**< DPI interrupt enable */
 	uint64_t sli                          : 1;  /**< SLI interrupt enable */
@@ -1512,7 +3533,7 @@ union cvmx_ciu_intx_en1
 	uint64_t fpa                          : 1;  /**< FPA interrupt enable */
 	uint64_t iob                          : 1;  /**< IOB interrupt enable */
 	uint64_t mio                          : 1;  /**< MIO boot interrupt enable */
-	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt enable */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt enable */
 	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt enable */
 	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
 	uint64_t uart2                        : 1;  /**< Third UART interrupt */
@@ -1540,7 +3561,10 @@ union cvmx_ciu_intx_en1
 	uint64_t sli                          : 1;
 	uint64_t dpi                          : 1;
 	uint64_t agx0                         : 1;
-	uint64_t reserved_37_45               : 9;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
 	uint64_t agl                          : 1;
 	uint64_t ptp                          : 1;
 	uint64_t pem0                         : 1;
@@ -1550,13 +3574,15 @@ union cvmx_ciu_intx_en1
 	uint64_t lmc0                         : 1;
 	uint64_t reserved_53_55               : 3;
 	uint64_t dfm                          : 1;
-	uint64_t reserved_57_62               : 6;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
 	uint64_t rst                          : 1;
 #endif
 	} s;
-	struct cvmx_ciu_intx_en1_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en1_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t wdog                         : 1;  /**< Watchdog summary interrupt enable vector */
 #else
@@ -1564,9 +3590,8 @@ union cvmx_ciu_intx_en1
 	uint64_t reserved_1_63                : 63;
 #endif
 	} cn30xx;
-	struct cvmx_ciu_intx_en1_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en1_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t wdog                         : 2;  /**< Watchdog summary interrupt enable vectory */
 #else
@@ -1574,9 +3599,8 @@ union cvmx_ciu_intx_en1
 	uint64_t reserved_2_63                : 62;
 #endif
 	} cn31xx;
-	struct cvmx_ciu_intx_en1_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en1_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t wdog                         : 16; /**< Watchdog summary interrupt enable vectory */
 #else
@@ -1586,9 +3610,8 @@ union cvmx_ciu_intx_en1
 	} cn38xx;
 	struct cvmx_ciu_intx_en1_cn38xx       cn38xxp2;
 	struct cvmx_ciu_intx_en1_cn31xx       cn50xx;
-	struct cvmx_ciu_intx_en1_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en1_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t nand                         : 1;  /**< NAND Flash Controller */
 	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
@@ -1606,9 +3629,8 @@ union cvmx_ciu_intx_en1
 	uint64_t reserved_20_63               : 44;
 #endif
 	} cn52xx;
-	struct cvmx_ciu_intx_en1_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en1_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
 	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
@@ -1624,9 +3646,8 @@ union cvmx_ciu_intx_en1
 	uint64_t reserved_19_63               : 45;
 #endif
 	} cn52xxp1;
-	struct cvmx_ciu_intx_en1_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en1_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t wdog                         : 12; /**< Watchdog summary interrupt enable vectory */
 #else
@@ -1637,9 +3658,79 @@ union cvmx_ciu_intx_en1
 	struct cvmx_ciu_intx_en1_cn56xx       cn56xxp1;
 	struct cvmx_ciu_intx_en1_cn38xx       cn58xx;
 	struct cvmx_ciu_intx_en1_cn38xx       cn58xxp1;
-	struct cvmx_ciu_intx_en1_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en1_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt enable */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt enable */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< AGL interrupt enable */
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< DPI_DMA interrupt enable */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt enable */
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< DFA interrupt enable */
+	uint64_t key                          : 1;  /**< KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt enable */
+	uint64_t mii1                         : 1;  /**< RGMII/MIX Interface 1 Interrupt enable */
+	uint64_t reserved_4_17                : 14;
+	uint64_t wdog                         : 4;  /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_17                : 14;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_intx_en1_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rst                          : 1;  /**< MIO RST interrupt enable */
 	uint64_t reserved_57_62               : 6;
 	uint64_t dfm                          : 1;  /**< DFM interrupt enable */
@@ -1710,6 +3801,150 @@ union cvmx_ciu_intx_en1
 #endif
 	} cn63xx;
 	struct cvmx_ciu_intx_en1_cn63xx       cn63xxp1;
+	struct cvmx_ciu_intx_en1_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt enable */
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< SRIO3 interrupt enable */
+	uint64_t srio2                        : 1;  /**< SRIO2 interrupt enable */
+	uint64_t reserved_57_59               : 3;
+	uint64_t dfm                          : 1;  /**< DFM interrupt enable */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt enable */
+	uint64_t reserved_51_51               : 1;
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt enable */
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< AGL interrupt enable */
+	uint64_t reserved_38_45               : 8;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt enable */
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< DFA interrupt enable */
+	uint64_t key                          : 1;  /**< KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt enable */
+	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt enable */
+	uint64_t reserved_10_17               : 8;
+	uint64_t wdog                         : 10; /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 10;
+	uint64_t reserved_10_17               : 8;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_45               : 8;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t rst                          : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_intx_en1_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt enable */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt enable */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< PTP interrupt enable */
+	uint64_t reserved_41_46               : 6;
+	uint64_t dpi_dma                      : 1;  /**< DPI_DMA interrupt enable */
+	uint64_t reserved_37_39               : 3;
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt enable */
+	uint64_t reserved_32_32               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< TIM interrupt enable */
+	uint64_t reserved_28_28               : 1;
+	uint64_t pko                          : 1;  /**< PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt enable */
+	uint64_t reserved_4_18                : 15;
+	uint64_t wdog                         : 4;  /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_18                : 15;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_28_28               : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_32_32               : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_46               : 6;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_ciu_intx_en1 cvmx_ciu_intx_en1_t;
 
@@ -1717,17 +3952,18 @@ typedef union cvmx_ciu_intx_en1 cvmx_ciu_intx_en1_t;
  * cvmx_ciu_int#_en1_w1c
  *
  * Notes:
- * Write-1-to-clear version of the CIU_INTx_EN1 register
+ * Write-1-to-clear version of the CIU_INTX_EN1 register, read back corresponding CIU_INTX_EN1 value.
  *
  */
-union cvmx_ciu_intx_en1_w1c
-{
+union cvmx_ciu_intx_en1_w1c {
 	uint64_t u64;
-	struct cvmx_ciu_intx_en1_w1c_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en1_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rst                          : 1;  /**< Write 1 to clear MIO RST interrupt enable */
-	uint64_t reserved_57_62               : 6;
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< Write 1 to clear SRIO3 interrupt enable */
+	uint64_t srio2                        : 1;  /**< Write 1 to clear SRIO2 interrupt enable */
+	uint64_t reserved_57_59               : 3;
 	uint64_t dfm                          : 1;  /**< Write 1 to clear DFM interrupt enable */
 	uint64_t reserved_53_55               : 3;
 	uint64_t lmc0                         : 1;  /**< Write 1 to clear LMC0 interrupt enable */
@@ -1737,7 +3973,10 @@ union cvmx_ciu_intx_en1_w1c
 	uint64_t pem0                         : 1;  /**< Write 1 to clear PEM0 interrupt enable */
 	uint64_t ptp                          : 1;  /**< Write 1 to clear PTP interrupt enable */
 	uint64_t agl                          : 1;  /**< Write 1 to clear AGL interrupt enable */
-	uint64_t reserved_37_45               : 9;
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to clear DPI_DMA interrupt enable */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< Write 1 to clear GMX1 interrupt enable */
 	uint64_t agx0                         : 1;  /**< Write 1 to clear GMX0 interrupt enable */
 	uint64_t dpi                          : 1;  /**< Write 1 to clear DPI interrupt enable */
 	uint64_t sli                          : 1;  /**< Write 1 to clear SLI interrupt enable */
@@ -1755,7 +3994,7 @@ union cvmx_ciu_intx_en1_w1c
 	uint64_t fpa                          : 1;  /**< Write 1 to clear FPA interrupt enable */
 	uint64_t iob                          : 1;  /**< Write 1 to clear IOB interrupt enable */
 	uint64_t mio                          : 1;  /**< Write 1 to clear MIO boot interrupt enable */
-	uint64_t nand                         : 1;  /**< Write 1 to clear NAND Flash Controller interrupt
+	uint64_t nand                         : 1;  /**< Write 1 to clear EMMC Flash Controller interrupt
                                                          enable */
 	uint64_t mii1                         : 1;  /**< Write 1 to clear RGMII/MII/MIX Interface 1
                                                          Interrupt enable */
@@ -1785,7 +4024,10 @@ union cvmx_ciu_intx_en1_w1c
 	uint64_t sli                          : 1;
 	uint64_t dpi                          : 1;
 	uint64_t agx0                         : 1;
-	uint64_t reserved_37_45               : 9;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
 	uint64_t agl                          : 1;
 	uint64_t ptp                          : 1;
 	uint64_t pem0                         : 1;
@@ -1795,13 +4037,15 @@ union cvmx_ciu_intx_en1_w1c
 	uint64_t lmc0                         : 1;
 	uint64_t reserved_53_55               : 3;
 	uint64_t dfm                          : 1;
-	uint64_t reserved_57_62               : 6;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
 	uint64_t rst                          : 1;
 #endif
 	} s;
-	struct cvmx_ciu_intx_en1_w1c_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en1_w1c_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t nand                         : 1;  /**< NAND Flash Controller */
 	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
@@ -1819,9 +4063,8 @@ union cvmx_ciu_intx_en1_w1c
 	uint64_t reserved_20_63               : 44;
 #endif
 	} cn52xx;
-	struct cvmx_ciu_intx_en1_w1c_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en1_w1c_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t wdog                         : 12; /**< Watchdog summary interrupt enable vectory */
 #else
@@ -1829,9 +4072,8 @@ union cvmx_ciu_intx_en1_w1c
 	uint64_t reserved_12_63               : 52;
 #endif
 	} cn56xx;
-	struct cvmx_ciu_intx_en1_w1c_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en1_w1c_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t wdog                         : 16; /**< Watchdog summary interrupt enable vectory */
 #else
@@ -1839,9 +4081,81 @@ union cvmx_ciu_intx_en1_w1c
 	uint64_t reserved_16_63               : 48;
 #endif
 	} cn58xx;
-	struct cvmx_ciu_intx_en1_w1c_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en1_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to clear MIO RST interrupt enable */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< Write 1 to clear LMC0 interrupt enable */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< Write 1 to clear PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to clear PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to clear PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< Write 1 to clear AGL interrupt enable */
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to clear DPI_DMA interrupt enable */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< Write 1 to clear GMX1 interrupt enable */
+	uint64_t agx0                         : 1;  /**< Write 1 to clear GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to clear DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to clear SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< Write 1 to clear DFA interrupt enable */
+	uint64_t key                          : 1;  /**< Write 1 to clear KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to clear RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to clear TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< Write 1 to clear ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< Write 1 to clear PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to clear PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to clear IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to clear L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to clear POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to clear FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to clear IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to clear MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to clear EMMC Flash Controller interrupt
+                                                         enable */
+	uint64_t mii1                         : 1;  /**< Write 1 to clear RGMII/MIX Interface 1
+                                                         Interrupt enable */
+	uint64_t reserved_4_17                : 14;
+	uint64_t wdog                         : 4;  /**< Write 1s to clear Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_17                : 14;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_intx_en1_w1c_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rst                          : 1;  /**< Write 1 to clear MIO RST interrupt enable */
 	uint64_t reserved_57_62               : 6;
 	uint64_t dfm                          : 1;  /**< Write 1 to clear DFM interrupt enable */
@@ -1914,6 +4228,153 @@ union cvmx_ciu_intx_en1_w1c
 #endif
 	} cn63xx;
 	struct cvmx_ciu_intx_en1_w1c_cn63xx   cn63xxp1;
+	struct cvmx_ciu_intx_en1_w1c_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to clear MIO RST interrupt enable */
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< Write 1 to clear SRIO3 interrupt enable */
+	uint64_t srio2                        : 1;  /**< Write 1 to clear SRIO2 interrupt enable */
+	uint64_t reserved_57_59               : 3;
+	uint64_t dfm                          : 1;  /**< Write 1 to clear DFM interrupt enable */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< Write 1 to clear LMC0 interrupt enable */
+	uint64_t reserved_51_51               : 1;
+	uint64_t srio0                        : 1;  /**< Write 1 to clear SRIO0 interrupt enable */
+	uint64_t pem1                         : 1;  /**< Write 1 to clear PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to clear PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to clear PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< Write 1 to clear AGL interrupt enable */
+	uint64_t reserved_38_45               : 8;
+	uint64_t agx1                         : 1;  /**< Write 1 to clear GMX1 interrupt enable */
+	uint64_t agx0                         : 1;  /**< Write 1 to clear GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to clear DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to clear SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< Write 1 to clear DFA interrupt enable */
+	uint64_t key                          : 1;  /**< Write 1 to clear KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to clear RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to clear TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< Write 1 to clear ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< Write 1 to clear PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to clear PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to clear IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to clear L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to clear POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to clear FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to clear IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to clear MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to clear NAND Flash Controller interrupt
+                                                         enable */
+	uint64_t mii1                         : 1;  /**< Write 1 to clear RGMII/MII/MIX Interface 1
+                                                         Interrupt enable */
+	uint64_t reserved_10_17               : 8;
+	uint64_t wdog                         : 10; /**< Write 1s to clear Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 10;
+	uint64_t reserved_10_17               : 8;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_45               : 8;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t rst                          : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_intx_en1_w1c_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to clear MIO RST interrupt enable */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< Write 1 to clear LMC0 interrupt enable */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< Write 1 to clear PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to clear PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to clear PTP interrupt enable */
+	uint64_t reserved_41_46               : 6;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to clear DPI_DMA interrupt enable */
+	uint64_t reserved_37_39               : 3;
+	uint64_t agx0                         : 1;  /**< Write 1 to clear GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to clear DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to clear SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB UCTL0 interrupt enable */
+	uint64_t reserved_32_32               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to clear KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to clear RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to clear TIM interrupt enable */
+	uint64_t reserved_28_28               : 1;
+	uint64_t pko                          : 1;  /**< Write 1 to clear PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to clear PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to clear IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to clear L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to clear POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to clear FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to clear IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to clear MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to clear EMMC Flash Controller interrupt
+                                                         enable */
+	uint64_t reserved_4_18                : 15;
+	uint64_t wdog                         : 4;  /**< Write 1s to clear Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_18                : 15;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_28_28               : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_32_32               : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_46               : 6;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_ciu_intx_en1_w1c cvmx_ciu_intx_en1_w1c_t;
 
@@ -1921,17 +4382,18 @@ typedef union cvmx_ciu_intx_en1_w1c cvmx_ciu_intx_en1_w1c_t;
  * cvmx_ciu_int#_en1_w1s
  *
  * Notes:
- * Write-1-to-set version of the CIU_INTx_EN1 register
+ * Write-1-to-set version of the CIU_INTX_EN1 register, read back corresponding CIU_INTX_EN1 value.
  *
  */
-union cvmx_ciu_intx_en1_w1s
-{
+union cvmx_ciu_intx_en1_w1s {
 	uint64_t u64;
-	struct cvmx_ciu_intx_en1_w1s_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en1_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rst                          : 1;  /**< Write 1 to set MIO RST interrupt enable */
-	uint64_t reserved_57_62               : 6;
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< Write 1 to set SRIO3 interrupt enable */
+	uint64_t srio2                        : 1;  /**< Write 1 to set SRIO2 interrupt enable */
+	uint64_t reserved_57_59               : 3;
 	uint64_t dfm                          : 1;  /**< Write 1 to set DFM interrupt enable */
 	uint64_t reserved_53_55               : 3;
 	uint64_t lmc0                         : 1;  /**< Write 1 to set LMC0 interrupt enable */
@@ -1941,7 +4403,10 @@ union cvmx_ciu_intx_en1_w1s
 	uint64_t pem0                         : 1;  /**< Write 1 to set PEM0 interrupt enable */
 	uint64_t ptp                          : 1;  /**< Write 1 to set PTP interrupt enable */
 	uint64_t agl                          : 1;  /**< Write 1 to set AGL interrupt enable */
-	uint64_t reserved_37_45               : 9;
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to set DPI_DMA interrupt enable */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< Write 1 to set GMX1 interrupt enable */
 	uint64_t agx0                         : 1;  /**< Write 1 to set GMX0 interrupt enable */
 	uint64_t dpi                          : 1;  /**< Write 1 to set DPI interrupt enable */
 	uint64_t sli                          : 1;  /**< Write 1 to set SLI interrupt enable */
@@ -1959,7 +4424,7 @@ union cvmx_ciu_intx_en1_w1s
 	uint64_t fpa                          : 1;  /**< Write 1 to set FPA interrupt enable */
 	uint64_t iob                          : 1;  /**< Write 1 to set IOB interrupt enable */
 	uint64_t mio                          : 1;  /**< Write 1 to set MIO boot interrupt enable */
-	uint64_t nand                         : 1;  /**< Write 1 to set NAND Flash Controller interrupt
+	uint64_t nand                         : 1;  /**< Write 1 to set EMMC Flash Controller interrupt
                                                          enable */
 	uint64_t mii1                         : 1;  /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt
                                                          enable */
@@ -1989,7 +4454,10 @@ union cvmx_ciu_intx_en1_w1s
 	uint64_t sli                          : 1;
 	uint64_t dpi                          : 1;
 	uint64_t agx0                         : 1;
-	uint64_t reserved_37_45               : 9;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
 	uint64_t agl                          : 1;
 	uint64_t ptp                          : 1;
 	uint64_t pem0                         : 1;
@@ -1999,13 +4467,15 @@ union cvmx_ciu_intx_en1_w1s
 	uint64_t lmc0                         : 1;
 	uint64_t reserved_53_55               : 3;
 	uint64_t dfm                          : 1;
-	uint64_t reserved_57_62               : 6;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
 	uint64_t rst                          : 1;
 #endif
 	} s;
-	struct cvmx_ciu_intx_en1_w1s_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en1_w1s_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t nand                         : 1;  /**< NAND Flash Controller */
 	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
@@ -2023,9 +4493,8 @@ union cvmx_ciu_intx_en1_w1s
 	uint64_t reserved_20_63               : 44;
 #endif
 	} cn52xx;
-	struct cvmx_ciu_intx_en1_w1s_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en1_w1s_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t wdog                         : 12; /**< Watchdog summary interrupt enable vectory */
 #else
@@ -2033,9 +4502,8 @@ union cvmx_ciu_intx_en1_w1s
 	uint64_t reserved_12_63               : 52;
 #endif
 	} cn56xx;
-	struct cvmx_ciu_intx_en1_w1s_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en1_w1s_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t wdog                         : 16; /**< Watchdog summary interrupt enable vectory */
 #else
@@ -2043,9 +4511,81 @@ union cvmx_ciu_intx_en1_w1s
 	uint64_t reserved_16_63               : 48;
 #endif
 	} cn58xx;
-	struct cvmx_ciu_intx_en1_w1s_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en1_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to set MIO RST interrupt enable */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< Write 1 to set LMC0 interrupt enable */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< Write 1 to set PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to set PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to set PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< Write 1 to set AGL interrupt enable */
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to set DPI_DMA interrupt enable */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< Write 1 to set GMX1 interrupt enable */
+	uint64_t agx0                         : 1;  /**< Write 1 to set GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to set DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to set SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to set USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< Write 1 to set DFA interrupt enable */
+	uint64_t key                          : 1;  /**< Write 1 to set KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to set RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to set TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< Write 1 to set ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< Write 1 to set PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to set PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to set IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to set L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to set POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to set FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to set IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to set MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to set EMMC Flash Controller interrupt
+                                                         enable */
+	uint64_t mii1                         : 1;  /**< Write 1 to set RGMII/MIX Interface 1 Interrupt
+                                                         enable */
+	uint64_t reserved_4_17                : 14;
+	uint64_t wdog                         : 4;  /**< Write 1s to set Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_17                : 14;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_intx_en1_w1s_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rst                          : 1;  /**< Write 1 to set MIO RST interrupt enable */
 	uint64_t reserved_57_62               : 6;
 	uint64_t dfm                          : 1;  /**< Write 1 to set DFM interrupt enable */
@@ -2118,6 +4658,153 @@ union cvmx_ciu_intx_en1_w1s
 #endif
 	} cn63xx;
 	struct cvmx_ciu_intx_en1_w1s_cn63xx   cn63xxp1;
+	struct cvmx_ciu_intx_en1_w1s_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to set MIO RST interrupt enable */
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< Write 1 to set SRIO3 interrupt enable */
+	uint64_t srio2                        : 1;  /**< Write 1 to set SRIO2 interrupt enable */
+	uint64_t reserved_57_59               : 3;
+	uint64_t dfm                          : 1;  /**< Write 1 to set DFM interrupt enable */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< Write 1 to set LMC0 interrupt enable */
+	uint64_t reserved_51_51               : 1;
+	uint64_t srio0                        : 1;  /**< Write 1 to set SRIO0 interrupt enable */
+	uint64_t pem1                         : 1;  /**< Write 1 to set PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to set PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to set PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< Write 1 to set AGL interrupt enable */
+	uint64_t reserved_38_45               : 8;
+	uint64_t agx1                         : 1;  /**< Write 1 to set GMX1 interrupt enable */
+	uint64_t agx0                         : 1;  /**< Write 1 to set GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to set DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to set SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to set USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< Write 1 to set DFA interrupt enable */
+	uint64_t key                          : 1;  /**< Write 1 to set KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to set RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to set TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< Write 1 to set ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< Write 1 to set PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to set PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to set IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to set L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to set POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to set FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to set IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to set MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to set NAND Flash Controller interrupt
+                                                         enable */
+	uint64_t mii1                         : 1;  /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt
+                                                         enable */
+	uint64_t reserved_10_17               : 8;
+	uint64_t wdog                         : 10; /**< Write 1s to set Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 10;
+	uint64_t reserved_10_17               : 8;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_45               : 8;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t rst                          : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_intx_en1_w1s_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to set MIO RST interrupt enable */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< Write 1 to set LMC0 interrupt enable */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< Write 1 to set PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to set PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to set PTP interrupt enable */
+	uint64_t reserved_41_46               : 6;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to set DPI_DMA interrupt enable */
+	uint64_t reserved_37_39               : 3;
+	uint64_t agx0                         : 1;  /**< Write 1 to set GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to set DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to set SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to set USB UCTL0 interrupt enable */
+	uint64_t reserved_32_32               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to set KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to set RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to set TIM interrupt enable */
+	uint64_t reserved_28_28               : 1;
+	uint64_t pko                          : 1;  /**< Write 1 to set PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to set PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to set IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to set L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to set POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to set FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to set IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to set MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to set EMMC Flash Controller interrupt
+                                                         enable */
+	uint64_t reserved_4_18                : 15;
+	uint64_t wdog                         : 4;  /**< Write 1s to set Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_18                : 15;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_28_28               : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_32_32               : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_46               : 6;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_ciu_intx_en1_w1s cvmx_ciu_intx_en1_w1s_t;
 
@@ -2128,21 +4815,19 @@ typedef union cvmx_ciu_intx_en1_w1s cvmx_ciu_intx_en1_w1s_t;
  * CIU_INT0_EN4_0:   PP0  /IP4
  * CIU_INT1_EN4_0:   PP1  /IP4
  * ...
- * CIU_INT11_EN4_0:  PP11 /IP4
+ * CIU_INT3_EN4_0:   PP3  /IP4
  */
-union cvmx_ciu_intx_en4_0
-{
+union cvmx_ciu_intx_en4_0 {
 	uint64_t u64;
-	struct cvmx_ciu_intx_en4_0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt enable */
 	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface 0 Interrupt enable */
 	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt enable */
 	uint64_t powiq                        : 1;  /**< POW IQ interrupt enable */
 	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt enable */
-	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
-	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt enable */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt enable */
 	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt enable */
 	uint64_t timer                        : 4;  /**< General timer interrupt enables */
 	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
@@ -2152,7 +4837,7 @@ union cvmx_ciu_intx_en4_0
 	uint64_t rml                          : 1;  /**< RML Interrupt enable */
 	uint64_t twsi                         : 1;  /**< TWSI Interrupt enable */
 	uint64_t reserved_44_44               : 1;
-	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI enables */
+	uint64_t pci_msi                      : 4;  /**< PCIe MSI enables */
 	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D enables */
 	uint64_t uart                         : 2;  /**< Two UART interrupt enables */
 	uint64_t mbox                         : 2;  /**< Two mailbox interrupt enables */
@@ -2183,9 +4868,8 @@ union cvmx_ciu_intx_en4_0
 	uint64_t bootdma                      : 1;
 #endif
 	} s;
-	struct cvmx_ciu_intx_en4_0_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_0_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_59_63               : 5;
 	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
 	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
@@ -2227,9 +4911,8 @@ union cvmx_ciu_intx_en4_0
 	uint64_t reserved_59_63               : 5;
 #endif
 	} cn50xx;
-	struct cvmx_ciu_intx_en4_0_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_0_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
 	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
 	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
@@ -2278,9 +4961,8 @@ union cvmx_ciu_intx_en4_0
 #endif
 	} cn52xx;
 	struct cvmx_ciu_intx_en4_0_cn52xx     cn52xxp1;
-	struct cvmx_ciu_intx_en4_0_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_0_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
 	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
 	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
@@ -2327,9 +5009,8 @@ union cvmx_ciu_intx_en4_0
 #endif
 	} cn56xx;
 	struct cvmx_ciu_intx_en4_0_cn56xx     cn56xxp1;
-	struct cvmx_ciu_intx_en4_0_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_0_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_56_63               : 8;
 	uint64_t timer                        : 4;  /**< General timer interrupts */
 	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
@@ -2364,8 +5045,157 @@ union cvmx_ciu_intx_en4_0
 #endif
 	} cn58xx;
 	struct cvmx_ciu_intx_en4_0_cn58xx     cn58xxp1;
+	struct cvmx_ciu_intx_en4_0_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt enable */
+	uint64_t mii                          : 1;  /**< RGMII/MIX Interface 0 Interrupt enable */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt enable */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt enable */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt enable */
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< General timer interrupt enables */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt enable */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCIe MSI enables */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Two UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupt enables */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< 16 work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn61xx;
 	struct cvmx_ciu_intx_en4_0_cn52xx     cn63xx;
 	struct cvmx_ciu_intx_en4_0_cn52xx     cn63xxp1;
+	struct cvmx_ciu_intx_en4_0_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt enable */
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface 0 Interrupt enable */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt enable */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt enable */
+	uint64_t reserved_57_57               : 1;
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< General timer interrupt enables */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt enable */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI enables */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Two UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupt enables */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< 16 work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_57               : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_intx_en4_0_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt enable */
+	uint64_t reserved_62_62               : 1;
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt enable */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt enable */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt enable */
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< General timer interrupt enables */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt enable */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCIe MSI enables */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Two UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupt enables */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< 16 work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_ciu_intx_en4_0 cvmx_ciu_intx_en4_0_t;
 
@@ -2373,26 +5203,25 @@ typedef union cvmx_ciu_intx_en4_0 cvmx_ciu_intx_en4_0_t;
  * cvmx_ciu_int#_en4_0_w1c
  *
  * Notes:
- * Write-1-to-clear version of the CIU_INTx_EN4_0 register
+ * Write-1-to-clear version of the CIU_INTx_EN4_0 register, read back corresponding CIU_INTx_EN4_0 value.
  *
  */
-union cvmx_ciu_intx_en4_0_w1c
-{
+union cvmx_ciu_intx_en4_0_w1c {
 	uint64_t u64;
-	struct cvmx_ciu_intx_en4_0_w1c_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_0_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Write 1 to clear Boot bus DMA engines Interrupt
                                                          enable */
 	uint64_t mii                          : 1;  /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt
                                                          enable */
 	uint64_t ipdppthr                     : 1;  /**< Write 1 to clear IPD per-port counter threshold
                                                          interrupt enable */
-	uint64_t powiq                        : 1;  /**< Write 1 to clear POW IQ interrupt */
-	uint64_t twsi2                        : 1;  /**< Write 1 to clear 2nd TWSI Interrupt */
-	uint64_t reserved_57_58               : 2;
-	uint64_t usb                          : 1;  /**< Write 1 to clear USB EHCI or OHCI Interrupt */
-	uint64_t timer                        : 4;  /**< Write 1 to clear General timer interrupts */
+	uint64_t powiq                        : 1;  /**< Write 1 to clear POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< Write 1 to clear 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< Write 1 to clear MPI/SPI interrupt enable */
+	uint64_t pcm                          : 1;  /**< Write 1 to clear PCM/TDM interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< Write 1 to clear General timer interrupt enables */
 	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
 	uint64_t ipd_drp                      : 1;  /**< Write 1 to clear IPD QOS packet drop interrupt
                                                          enable */
@@ -2401,7 +5230,7 @@ union cvmx_ciu_intx_en4_0_w1c
 	uint64_t rml                          : 1;  /**< Write 1 to clear RML Interrupt enable */
 	uint64_t twsi                         : 1;  /**< Write 1 to clear TWSI Interrupt enable */
 	uint64_t reserved_44_44               : 1;
-	uint64_t pci_msi                      : 4;  /**< Write 1s to clear PCIe/sRIO MSI enables */
+	uint64_t pci_msi                      : 4;  /**< Write 1s to clear PCIe MSI enables */
 	uint64_t pci_int                      : 4;  /**< Write 1s to clear PCIe INTA/B/C/D enables */
 	uint64_t uart                         : 2;  /**< Write 1s to clear UART interrupt enables */
 	uint64_t mbox                         : 2;  /**< Write 1s to clear mailbox interrupt enables */
@@ -2423,7 +5252,8 @@ union cvmx_ciu_intx_en4_0_w1c
 	uint64_t key_zero                     : 1;
 	uint64_t timer                        : 4;
 	uint64_t usb                          : 1;
-	uint64_t reserved_57_58               : 2;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
 	uint64_t twsi2                        : 1;
 	uint64_t powiq                        : 1;
 	uint64_t ipdppthr                     : 1;
@@ -2431,9 +5261,8 @@ union cvmx_ciu_intx_en4_0_w1c
 	uint64_t bootdma                      : 1;
 #endif
 	} s;
-	struct cvmx_ciu_intx_en4_0_w1c_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_0_w1c_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
 	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
 	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
@@ -2481,10 +5310,55 @@ union cvmx_ciu_intx_en4_0_w1c
 	uint64_t bootdma                      : 1;
 #endif
 	} cn52xx;
-	struct cvmx_ciu_intx_en4_0_w1c_s      cn56xx;
-	struct cvmx_ciu_intx_en4_0_w1c_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_0_w1c_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
+	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< USB Interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_intx_en4_0_w1c_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_56_63               : 8;
 	uint64_t timer                        : 4;  /**< General timer interrupts */
 	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
@@ -2518,8 +5392,168 @@ union cvmx_ciu_intx_en4_0_w1c
 	uint64_t reserved_56_63               : 8;
 #endif
 	} cn58xx;
+	struct cvmx_ciu_intx_en4_0_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Write 1 to clear Boot bus DMA engines Interrupt
+                                                         enable */
+	uint64_t mii                          : 1;  /**< Write 1 to clr RGMII/MIX Interface 0 Interrupt
+                                                         enable */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to clear IPD per-port counter threshold
+                                                         interrupt enable */
+	uint64_t powiq                        : 1;  /**< Write 1 to clear POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< Write 1 to clear 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< Write 1 to clear MPI/SPI interrupt enable */
+	uint64_t pcm                          : 1;  /**< Write 1 to clear PCM/TDM interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< Write 1 to clear General timer interrupt enables */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to clear IPD QOS packet drop interrupt
+                                                         enable */
+	uint64_t gmx_drp                      : 2;  /**< Write 1 to clear GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Write 1 to clear Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< Write 1 to clear RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< Write 1 to clear TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< Write 1s to clear PCIe MSI enables */
+	uint64_t pci_int                      : 4;  /**< Write 1s to clear PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Write 1s to clear UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Write 1s to clear mailbox interrupt enables */
+	uint64_t gpio                         : 16; /**< Write 1s to clear GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< Write 1s to clear work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn61xx;
 	struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx;
 	struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1;
+	struct cvmx_ciu_intx_en4_0_w1c_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Write 1 to clear Boot bus DMA engines Interrupt
+                                                         enable */
+	uint64_t mii                          : 1;  /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt
+                                                         enable */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to clear IPD per-port counter threshold
+                                                         interrupt enable */
+	uint64_t powiq                        : 1;  /**< Write 1 to clear POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< Write 1 to clear 2nd TWSI Interrupt */
+	uint64_t mpi                          : 1;  /**< Write 1 to clear MPI/SPI interrupt */
+	uint64_t reserved_57_57               : 1;
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB EHCI or OHCI Interrupt */
+	uint64_t timer                        : 4;  /**< Write 1 to clear General timer interrupts */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to clear IPD QOS packet drop interrupt
+                                                         enable */
+	uint64_t gmx_drp                      : 2;  /**< Write 1 to clear GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Write 1 to clear Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< Write 1 to clear RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< Write 1 to clear TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< Write 1s to clear PCIe/sRIO MSI enables */
+	uint64_t pci_int                      : 4;  /**< Write 1s to clear PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Write 1s to clear UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Write 1s to clear mailbox interrupt enables */
+	uint64_t gpio                         : 16; /**< Write 1s to clear GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< Write 1s to clear work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_57               : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_intx_en4_0_w1c_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Write 1 to clear Boot bus DMA engines Interrupt
+                                                         enable */
+	uint64_t reserved_62_62               : 1;
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to clear IPD per-port counter threshold
+                                                         interrupt enable */
+	uint64_t powiq                        : 1;  /**< Write 1 to clear POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< Write 1 to clear 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< Write 1 to clear MPI/SPI interrupt enable */
+	uint64_t pcm                          : 1;  /**< Write 1 to clear PCM/TDM interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< Write 1 to clear General timer interrupt enables */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to clear IPD QOS packet drop interrupt
+                                                         enable */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< Write 1 to clear GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Write 1 to clear Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< Write 1 to clear RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< Write 1 to clear TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< Write 1s to clear PCIe MSI enables */
+	uint64_t pci_int                      : 4;  /**< Write 1s to clear PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Write 1s to clear UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Write 1s to clear mailbox interrupt enables */
+	uint64_t gpio                         : 16; /**< Write 1s to clear GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< Write 1s to clear work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_ciu_intx_en4_0_w1c cvmx_ciu_intx_en4_0_w1c_t;
 
@@ -2527,26 +5561,25 @@ typedef union cvmx_ciu_intx_en4_0_w1c cvmx_ciu_intx_en4_0_w1c_t;
  * cvmx_ciu_int#_en4_0_w1s
  *
  * Notes:
- * Write-1-to-set version of the CIU_INTx_EN4_0 register
+ * Write-1-to-set version of the CIU_INTX_EN4_0 register, read back corresponding CIU_INTX_EN4_0 value.
  *
  */
-union cvmx_ciu_intx_en4_0_w1s
-{
+union cvmx_ciu_intx_en4_0_w1s {
 	uint64_t u64;
-	struct cvmx_ciu_intx_en4_0_w1s_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_0_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Write 1 to set Boot bus DMA engines Interrupt
                                                          enable */
 	uint64_t mii                          : 1;  /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt
                                                          enable */
 	uint64_t ipdppthr                     : 1;  /**< Write 1 to set IPD per-port counter threshold
                                                          interrupt enable */
-	uint64_t powiq                        : 1;  /**< Write 1 to set POW IQ interrupt */
-	uint64_t twsi2                        : 1;  /**< Write 1 to set 2nd TWSI Interrupt */
-	uint64_t reserved_57_58               : 2;
-	uint64_t usb                          : 1;  /**< Write 1 to set USB EHCI or OHCI Interrupt */
-	uint64_t timer                        : 4;  /**< Write 1 to set General timer interrupts */
+	uint64_t powiq                        : 1;  /**< Write 1 to set POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< Write 1 to set 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< Write 1 to set MPI/SPI interrupt enable */
+	uint64_t pcm                          : 1;  /**< Write 1 to set PCM/TDM interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to set USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< Write 1 to set General timer interrupt enables */
 	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
 	uint64_t ipd_drp                      : 1;  /**< Write 1 to set IPD QOS packet drop interrupt
                                                          enable */
@@ -2555,7 +5588,7 @@ union cvmx_ciu_intx_en4_0_w1s
 	uint64_t rml                          : 1;  /**< Write 1 to set RML Interrupt enable */
 	uint64_t twsi                         : 1;  /**< Write 1 to set TWSI Interrupt enable */
 	uint64_t reserved_44_44               : 1;
-	uint64_t pci_msi                      : 4;  /**< Write 1s to set PCIe/sRIO MSI enables */
+	uint64_t pci_msi                      : 4;  /**< Write 1s to set PCIe MSI enables */
 	uint64_t pci_int                      : 4;  /**< Write 1s to set PCIe INTA/B/C/D enables */
 	uint64_t uart                         : 2;  /**< Write 1s to set UART interrupt enables */
 	uint64_t mbox                         : 2;  /**< Write 1s to set mailbox interrupt enables */
@@ -2577,7 +5610,8 @@ union cvmx_ciu_intx_en4_0_w1s
 	uint64_t key_zero                     : 1;
 	uint64_t timer                        : 4;
 	uint64_t usb                          : 1;
-	uint64_t reserved_57_58               : 2;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
 	uint64_t twsi2                        : 1;
 	uint64_t powiq                        : 1;
 	uint64_t ipdppthr                     : 1;
@@ -2585,9 +5619,8 @@ union cvmx_ciu_intx_en4_0_w1s
 	uint64_t bootdma                      : 1;
 #endif
 	} s;
-	struct cvmx_ciu_intx_en4_0_w1s_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_0_w1s_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
 	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
 	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
@@ -2635,10 +5668,55 @@ union cvmx_ciu_intx_en4_0_w1s
 	uint64_t bootdma                      : 1;
 #endif
 	} cn52xx;
-	struct cvmx_ciu_intx_en4_0_w1s_s      cn56xx;
-	struct cvmx_ciu_intx_en4_0_w1s_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_0_w1s_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
+	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< USB Interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_intx_en4_0_w1s_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_56_63               : 8;
 	uint64_t timer                        : 4;  /**< General timer interrupts */
 	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
@@ -2672,8 +5750,168 @@ union cvmx_ciu_intx_en4_0_w1s
 	uint64_t reserved_56_63               : 8;
 #endif
 	} cn58xx;
+	struct cvmx_ciu_intx_en4_0_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Write 1 to set Boot bus DMA engines Interrupt
+                                                         enable */
+	uint64_t mii                          : 1;  /**< Write 1 to set RGMII/MIX Interface 0 Interrupt
+                                                         enable */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to set IPD per-port counter threshold
+                                                         interrupt enable */
+	uint64_t powiq                        : 1;  /**< Write 1 to set POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< Write 1 to set 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< Write 1 to set MPI/SPI interrupt enable */
+	uint64_t pcm                          : 1;  /**< Write 1 to set PCM/TDM interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to set USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< Write 1 to set General timer interrupt enables */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to set IPD QOS packet drop interrupt
+                                                         enable */
+	uint64_t gmx_drp                      : 2;  /**< Write 1 to set GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Write 1 to set Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< Write 1 to set RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< Write 1 to set TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< Write 1s to set PCIe MSI enables */
+	uint64_t pci_int                      : 4;  /**< Write 1s to set PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Write 1s to set UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Write 1s to set mailbox interrupt enables */
+	uint64_t gpio                         : 16; /**< Write 1s to set GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< Write 1s to set work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn61xx;
 	struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx;
 	struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1;
+	struct cvmx_ciu_intx_en4_0_w1s_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Write 1 to set Boot bus DMA engines Interrupt
+                                                         enable */
+	uint64_t mii                          : 1;  /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt
+                                                         enable */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to set IPD per-port counter threshold
+                                                         interrupt enable */
+	uint64_t powiq                        : 1;  /**< Write 1 to set POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< Write 1 to set 2nd TWSI Interrupt */
+	uint64_t mpi                          : 1;  /**< Write 1 to set MPI/SPI interrupt */
+	uint64_t reserved_57_57               : 1;
+	uint64_t usb                          : 1;  /**< Write 1 to set USB EHCI or OHCI Interrupt */
+	uint64_t timer                        : 4;  /**< Write 1 to set General timer interrupts */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to set IPD QOS packet drop interrupt
+                                                         enable */
+	uint64_t gmx_drp                      : 2;  /**< Write 1 to set GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Write 1 to set Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< Write 1 to set RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< Write 1 to set TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< Write 1s to set PCIe/sRIO MSI enables */
+	uint64_t pci_int                      : 4;  /**< Write 1s to set PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Write 1s to set UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Write 1s to set mailbox interrupt enables */
+	uint64_t gpio                         : 16; /**< Write 1s to set GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< Write 1s to set work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_57               : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_intx_en4_0_w1s_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Write 1 to set Boot bus DMA engines Interrupt
+                                                         enable */
+	uint64_t reserved_62_62               : 1;
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to set IPD per-port counter threshold
+                                                         interrupt enable */
+	uint64_t powiq                        : 1;  /**< Write 1 to set POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< Write 1 to set 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< Write 1 to set MPI/SPI interrupt enable */
+	uint64_t pcm                          : 1;  /**< Write 1 to set PCM/TDM interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to set USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< Write 1 to set General timer interrupt enables */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to set IPD QOS packet drop interrupt
+                                                         enable */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< Write 1 to set GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Write 1 to set Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< Write 1 to set RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< Write 1 to set TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< Write 1s to set PCIe MSI enables */
+	uint64_t pci_int                      : 4;  /**< Write 1s to set PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Write 1s to set UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Write 1s to set mailbox interrupt enables */
+	uint64_t gpio                         : 16; /**< Write 1s to set GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< Write 1s to set work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_ciu_intx_en4_0_w1s cvmx_ciu_intx_en4_0_w1s_t;
 
@@ -2682,16 +5920,17 @@ typedef union cvmx_ciu_intx_en4_0_w1s cvmx_ciu_intx_en4_0_w1s_t;
  *
  * Notes:
  * PPx/IP4 will be raised when...
- * PPx/IP4 = |([CIU_INT_SUM1, CIU_INTx_SUM4] & [CIU_INTx_EN4_1, CIU_INTx_EN4_0])
+ * PPx/IP4 = |([CIU_SUM1_PPx_IP4, CIU_INTx_SUM4] & [CIU_INTx_EN4_1, CIU_INTx_EN4_0])
  */
-union cvmx_ciu_intx_en4_1
-{
+union cvmx_ciu_intx_en4_1 {
 	uint64_t u64;
-	struct cvmx_ciu_intx_en4_1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rst                          : 1;  /**< MIO RST interrupt enable */
-	uint64_t reserved_57_62               : 6;
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< SRIO3 interrupt enable */
+	uint64_t srio2                        : 1;  /**< SRIO2 interrupt enable */
+	uint64_t reserved_57_59               : 3;
 	uint64_t dfm                          : 1;  /**< DFM interrupt enable */
 	uint64_t reserved_53_55               : 3;
 	uint64_t lmc0                         : 1;  /**< LMC0 interrupt enable */
@@ -2701,7 +5940,10 @@ union cvmx_ciu_intx_en4_1
 	uint64_t pem0                         : 1;  /**< PEM0 interrupt enable */
 	uint64_t ptp                          : 1;  /**< PTP interrupt enable */
 	uint64_t agl                          : 1;  /**< AGL interrupt enable */
-	uint64_t reserved_37_45               : 9;
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< DPI_DMA interrupt enable */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt enable */
 	uint64_t agx0                         : 1;  /**< GMX0 interrupt enable */
 	uint64_t dpi                          : 1;  /**< DPI interrupt enable */
 	uint64_t sli                          : 1;  /**< SLI interrupt enable */
@@ -2719,7 +5961,7 @@ union cvmx_ciu_intx_en4_1
 	uint64_t fpa                          : 1;  /**< FPA interrupt enable */
 	uint64_t iob                          : 1;  /**< IOB interrupt enable */
 	uint64_t mio                          : 1;  /**< MIO boot interrupt enable */
-	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt enable */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt enable */
 	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt enable */
 	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
 	uint64_t uart2                        : 1;  /**< Third UART interrupt */
@@ -2747,7 +5989,10 @@ union cvmx_ciu_intx_en4_1
 	uint64_t sli                          : 1;
 	uint64_t dpi                          : 1;
 	uint64_t agx0                         : 1;
-	uint64_t reserved_37_45               : 9;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
 	uint64_t agl                          : 1;
 	uint64_t ptp                          : 1;
 	uint64_t pem0                         : 1;
@@ -2757,13 +6002,15 @@ union cvmx_ciu_intx_en4_1
 	uint64_t lmc0                         : 1;
 	uint64_t reserved_53_55               : 3;
 	uint64_t dfm                          : 1;
-	uint64_t reserved_57_62               : 6;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
 	uint64_t rst                          : 1;
 #endif
 	} s;
-	struct cvmx_ciu_intx_en4_1_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_1_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t wdog                         : 2;  /**< Watchdog summary interrupt enable vectory */
 #else
@@ -2771,9 +6018,8 @@ union cvmx_ciu_intx_en4_1
 	uint64_t reserved_2_63                : 62;
 #endif
 	} cn50xx;
-	struct cvmx_ciu_intx_en4_1_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_1_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t nand                         : 1;  /**< NAND Flash Controller */
 	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
@@ -2791,9 +6037,8 @@ union cvmx_ciu_intx_en4_1
 	uint64_t reserved_20_63               : 44;
 #endif
 	} cn52xx;
-	struct cvmx_ciu_intx_en4_1_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_1_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
 	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
@@ -2809,9 +6054,8 @@ union cvmx_ciu_intx_en4_1
 	uint64_t reserved_19_63               : 45;
 #endif
 	} cn52xxp1;
-	struct cvmx_ciu_intx_en4_1_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_1_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t wdog                         : 12; /**< Watchdog summary interrupt enable vectory */
 #else
@@ -2820,9 +6064,8 @@ union cvmx_ciu_intx_en4_1
 #endif
 	} cn56xx;
 	struct cvmx_ciu_intx_en4_1_cn56xx     cn56xxp1;
-	struct cvmx_ciu_intx_en4_1_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_1_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t wdog                         : 16; /**< Watchdog summary interrupt enable vectory */
 #else
@@ -2831,9 +6074,79 @@ union cvmx_ciu_intx_en4_1
 #endif
 	} cn58xx;
 	struct cvmx_ciu_intx_en4_1_cn58xx     cn58xxp1;
-	struct cvmx_ciu_intx_en4_1_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_1_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt enable */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt enable */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< AGL interrupt enable */
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< DPI_DMA interrupt enable */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt enable */
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< DFA interrupt enable */
+	uint64_t key                          : 1;  /**< KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt enable */
+	uint64_t mii1                         : 1;  /**< RGMII/MIX Interface 1 Interrupt enable */
+	uint64_t reserved_4_17                : 14;
+	uint64_t wdog                         : 4;  /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_17                : 14;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_intx_en4_1_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rst                          : 1;  /**< MIO RST interrupt enable */
 	uint64_t reserved_57_62               : 6;
 	uint64_t dfm                          : 1;  /**< DFM interrupt enable */
@@ -2904,6 +6217,150 @@ union cvmx_ciu_intx_en4_1
 #endif
 	} cn63xx;
 	struct cvmx_ciu_intx_en4_1_cn63xx     cn63xxp1;
+	struct cvmx_ciu_intx_en4_1_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt enable */
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< SRIO3 interrupt enable */
+	uint64_t srio2                        : 1;  /**< SRIO2 interrupt enable */
+	uint64_t reserved_57_59               : 3;
+	uint64_t dfm                          : 1;  /**< DFM interrupt enable */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt enable */
+	uint64_t reserved_51_51               : 1;
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt enable */
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< AGL interrupt enable */
+	uint64_t reserved_38_45               : 8;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt enable */
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< DFA interrupt enable */
+	uint64_t key                          : 1;  /**< KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt enable */
+	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt enable */
+	uint64_t reserved_10_17               : 8;
+	uint64_t wdog                         : 10; /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 10;
+	uint64_t reserved_10_17               : 8;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_45               : 8;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t rst                          : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_intx_en4_1_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt enable */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt enable */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< PTP interrupt enable */
+	uint64_t reserved_41_46               : 6;
+	uint64_t dpi_dma                      : 1;  /**< DPI_DMA interrupt enable */
+	uint64_t reserved_37_39               : 3;
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt enable */
+	uint64_t reserved_32_32               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< TIM interrupt enable */
+	uint64_t reserved_28_28               : 1;
+	uint64_t pko                          : 1;  /**< PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt enable */
+	uint64_t reserved_4_18                : 15;
+	uint64_t wdog                         : 4;  /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_18                : 15;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_28_28               : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_32_32               : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_46               : 6;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_ciu_intx_en4_1 cvmx_ciu_intx_en4_1_t;
 
@@ -2911,17 +6368,18 @@ typedef union cvmx_ciu_intx_en4_1 cvmx_ciu_intx_en4_1_t;
  * cvmx_ciu_int#_en4_1_w1c
  *
  * Notes:
- * Write-1-to-clear version of the CIU_INTx_EN4_1 register
+ * Write-1-to-clear version of the CIU_INTX_EN4_1 register, read back corresponding CIU_INTX_EN4_1 value.
  *
  */
-union cvmx_ciu_intx_en4_1_w1c
-{
+union cvmx_ciu_intx_en4_1_w1c {
 	uint64_t u64;
-	struct cvmx_ciu_intx_en4_1_w1c_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_1_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rst                          : 1;  /**< Write 1 to clear MIO RST interrupt enable */
-	uint64_t reserved_57_62               : 6;
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< Write 1 to clear SRIO3 interrupt enable */
+	uint64_t srio2                        : 1;  /**< Write 1 to clear SRIO2 interrupt enable */
+	uint64_t reserved_57_59               : 3;
 	uint64_t dfm                          : 1;  /**< Write 1 to clear DFM interrupt enable */
 	uint64_t reserved_53_55               : 3;
 	uint64_t lmc0                         : 1;  /**< Write 1 to clear LMC0 interrupt enable */
@@ -2931,7 +6389,10 @@ union cvmx_ciu_intx_en4_1_w1c
 	uint64_t pem0                         : 1;  /**< Write 1 to clear PEM0 interrupt enable */
 	uint64_t ptp                          : 1;  /**< Write 1 to clear PTP interrupt enable */
 	uint64_t agl                          : 1;  /**< Write 1 to clear AGL interrupt enable */
-	uint64_t reserved_37_45               : 9;
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to clear DPI_DMA interrupt enable */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< Write 1 to clear GMX1 interrupt enable */
 	uint64_t agx0                         : 1;  /**< Write 1 to clear GMX0 interrupt enable */
 	uint64_t dpi                          : 1;  /**< Write 1 to clear DPI interrupt enable */
 	uint64_t sli                          : 1;  /**< Write 1 to clear SLI interrupt enable */
@@ -2949,7 +6410,7 @@ union cvmx_ciu_intx_en4_1_w1c
 	uint64_t fpa                          : 1;  /**< Write 1 to clear FPA interrupt enable */
 	uint64_t iob                          : 1;  /**< Write 1 to clear IOB interrupt enable */
 	uint64_t mio                          : 1;  /**< Write 1 to clear MIO boot interrupt enable */
-	uint64_t nand                         : 1;  /**< Write 1 to clear NAND Flash Controller interrupt
+	uint64_t nand                         : 1;  /**< Write 1 to clear EMMC Flash Controller interrupt
                                                          enable */
 	uint64_t mii1                         : 1;  /**< Write 1 to clear RGMII/MII/MIX Interface 1
                                                          Interrupt enable */
@@ -2979,7 +6440,10 @@ union cvmx_ciu_intx_en4_1_w1c
 	uint64_t sli                          : 1;
 	uint64_t dpi                          : 1;
 	uint64_t agx0                         : 1;
-	uint64_t reserved_37_45               : 9;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
 	uint64_t agl                          : 1;
 	uint64_t ptp                          : 1;
 	uint64_t pem0                         : 1;
@@ -2989,13 +6453,15 @@ union cvmx_ciu_intx_en4_1_w1c
 	uint64_t lmc0                         : 1;
 	uint64_t reserved_53_55               : 3;
 	uint64_t dfm                          : 1;
-	uint64_t reserved_57_62               : 6;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
 	uint64_t rst                          : 1;
 #endif
 	} s;
-	struct cvmx_ciu_intx_en4_1_w1c_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_1_w1c_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t nand                         : 1;  /**< NAND Flash Controller */
 	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
@@ -3013,9 +6479,8 @@ union cvmx_ciu_intx_en4_1_w1c
 	uint64_t reserved_20_63               : 44;
 #endif
 	} cn52xx;
-	struct cvmx_ciu_intx_en4_1_w1c_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_1_w1c_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t wdog                         : 12; /**< Watchdog summary interrupt enable vectory */
 #else
@@ -3023,9 +6488,8 @@ union cvmx_ciu_intx_en4_1_w1c
 	uint64_t reserved_12_63               : 52;
 #endif
 	} cn56xx;
-	struct cvmx_ciu_intx_en4_1_w1c_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_1_w1c_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t wdog                         : 16; /**< Watchdog summary interrupt enable vectory */
 #else
@@ -3033,9 +6497,81 @@ union cvmx_ciu_intx_en4_1_w1c
 	uint64_t reserved_16_63               : 48;
 #endif
 	} cn58xx;
-	struct cvmx_ciu_intx_en4_1_w1c_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_1_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to clear MIO RST interrupt enable */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< Write 1 to clear LMC0 interrupt enable */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< Write 1 to clear PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to clear PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to clear PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< Write 1 to clear AGL interrupt enable */
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to clear DPI_DMA interrupt enable */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< Write 1 to clear GMX1 interrupt enable */
+	uint64_t agx0                         : 1;  /**< Write 1 to clear GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to clear DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to clear SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< Write 1 to clear DFA interrupt enable */
+	uint64_t key                          : 1;  /**< Write 1 to clear KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to clear RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to clear TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< Write 1 to clear ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< Write 1 to clear PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to clear PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to clear IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to clear L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to clear POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to clear FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to clear IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to clear MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to clear EMMC Flash Controller interrupt
+                                                         enable */
+	uint64_t mii1                         : 1;  /**< Write 1 to clear RGMII/MIX Interface 1
+                                                         Interrupt enable */
+	uint64_t reserved_4_17                : 14;
+	uint64_t wdog                         : 4;  /**< Write 1s to clear Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_17                : 14;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_intx_en4_1_w1c_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rst                          : 1;  /**< Write 1 to clear MIO RST interrupt enable */
 	uint64_t reserved_57_62               : 6;
 	uint64_t dfm                          : 1;  /**< Write 1 to clear DFM interrupt enable */
@@ -3108,6 +6644,153 @@ union cvmx_ciu_intx_en4_1_w1c
 #endif
 	} cn63xx;
 	struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1;
+	struct cvmx_ciu_intx_en4_1_w1c_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to clear MIO RST interrupt enable */
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< Write 1 to clear SRIO3 interrupt enable */
+	uint64_t srio2                        : 1;  /**< Write 1 to clear SRIO2 interrupt enable */
+	uint64_t reserved_57_59               : 3;
+	uint64_t dfm                          : 1;  /**< Write 1 to clear DFM interrupt enable */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< Write 1 to clear LMC0 interrupt enable */
+	uint64_t reserved_51_51               : 1;
+	uint64_t srio0                        : 1;  /**< Write 1 to clear SRIO0 interrupt enable */
+	uint64_t pem1                         : 1;  /**< Write 1 to clear PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to clear PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to clear PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< Write 1 to clear AGL interrupt enable */
+	uint64_t reserved_38_45               : 8;
+	uint64_t agx1                         : 1;  /**< Write 1 to clear GMX1 interrupt enable */
+	uint64_t agx0                         : 1;  /**< Write 1 to clear GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to clear DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to clear SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< Write 1 to clear DFA interrupt enable */
+	uint64_t key                          : 1;  /**< Write 1 to clear KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to clear RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to clear TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< Write 1 to clear ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< Write 1 to clear PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to clear PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to clear IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to clear L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to clear POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to clear FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to clear IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to clear MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to clear NAND Flash Controller interrupt
+                                                         enable */
+	uint64_t mii1                         : 1;  /**< Write 1 to clear RGMII/MII/MIX Interface 1
+                                                         Interrupt enable */
+	uint64_t reserved_10_17               : 8;
+	uint64_t wdog                         : 10; /**< Write 1s to clear Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 10;
+	uint64_t reserved_10_17               : 8;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_45               : 8;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t rst                          : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_intx_en4_1_w1c_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to clear MIO RST interrupt enable */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< Write 1 to clear LMC0 interrupt enable */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< Write 1 to clear PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to clear PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to clear PTP interrupt enable */
+	uint64_t reserved_41_46               : 6;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to clear DPI_DMA interrupt enable */
+	uint64_t reserved_37_39               : 3;
+	uint64_t agx0                         : 1;  /**< Write 1 to clear GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to clear DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to clear SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB UCTL0 interrupt enable */
+	uint64_t reserved_32_32               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to clear KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to clear RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to clear TIM interrupt enable */
+	uint64_t reserved_28_28               : 1;
+	uint64_t pko                          : 1;  /**< Write 1 to clear PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to clear PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to clear IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to clear L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to clear POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to clear FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to clear IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to clear MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to clear EMMC Flash Controller interrupt
+                                                         enable */
+	uint64_t reserved_4_18                : 15;
+	uint64_t wdog                         : 4;  /**< Write 1s to clear Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_18                : 15;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_28_28               : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_32_32               : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_46               : 6;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_ciu_intx_en4_1_w1c cvmx_ciu_intx_en4_1_w1c_t;
 
@@ -3115,17 +6798,18 @@ typedef union cvmx_ciu_intx_en4_1_w1c cvmx_ciu_intx_en4_1_w1c_t;
  * cvmx_ciu_int#_en4_1_w1s
  *
  * Notes:
- * Write-1-to-set version of the CIU_INTx_EN4_1 register
+ * Write-1-to-set version of the CIU_INTX_EN4_1 register, read back corresponding CIU_INTX_EN4_1 value.
  *
  */
-union cvmx_ciu_intx_en4_1_w1s
-{
+union cvmx_ciu_intx_en4_1_w1s {
 	uint64_t u64;
-	struct cvmx_ciu_intx_en4_1_w1s_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_1_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rst                          : 1;  /**< Write 1 to set MIO RST interrupt enable */
-	uint64_t reserved_57_62               : 6;
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< Write 1 to set SRIO3 interrupt enable */
+	uint64_t srio2                        : 1;  /**< Write 1 to set SRIO2 interrupt enable */
+	uint64_t reserved_57_59               : 3;
 	uint64_t dfm                          : 1;  /**< Write 1 to set DFM interrupt enable */
 	uint64_t reserved_53_55               : 3;
 	uint64_t lmc0                         : 1;  /**< Write 1 to set LMC0 interrupt enable */
@@ -3135,7 +6819,10 @@ union cvmx_ciu_intx_en4_1_w1s
 	uint64_t pem0                         : 1;  /**< Write 1 to set PEM0 interrupt enable */
 	uint64_t ptp                          : 1;  /**< Write 1 to set PTP interrupt enable */
 	uint64_t agl                          : 1;  /**< Write 1 to set AGL interrupt enable */
-	uint64_t reserved_37_45               : 9;
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to set DPI_DMA interrupt enable */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< Write 1 to set GMX1 interrupt enable */
 	uint64_t agx0                         : 1;  /**< Write 1 to set GMX0 interrupt enable */
 	uint64_t dpi                          : 1;  /**< Write 1 to set DPI interrupt enable */
 	uint64_t sli                          : 1;  /**< Write 1 to set SLI interrupt enable */
@@ -3153,7 +6840,7 @@ union cvmx_ciu_intx_en4_1_w1s
 	uint64_t fpa                          : 1;  /**< Write 1 to set FPA interrupt enable */
 	uint64_t iob                          : 1;  /**< Write 1 to set IOB interrupt enable */
 	uint64_t mio                          : 1;  /**< Write 1 to set MIO boot interrupt enable */
-	uint64_t nand                         : 1;  /**< Write 1 to set NAND Flash Controller interrupt
+	uint64_t nand                         : 1;  /**< Write 1 to set EMMC Flash Controller interrupt
                                                          enable */
 	uint64_t mii1                         : 1;  /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt
                                                          enable */
@@ -3183,7 +6870,10 @@ union cvmx_ciu_intx_en4_1_w1s
 	uint64_t sli                          : 1;
 	uint64_t dpi                          : 1;
 	uint64_t agx0                         : 1;
-	uint64_t reserved_37_45               : 9;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
 	uint64_t agl                          : 1;
 	uint64_t ptp                          : 1;
 	uint64_t pem0                         : 1;
@@ -3193,13 +6883,15 @@ union cvmx_ciu_intx_en4_1_w1s
 	uint64_t lmc0                         : 1;
 	uint64_t reserved_53_55               : 3;
 	uint64_t dfm                          : 1;
-	uint64_t reserved_57_62               : 6;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
 	uint64_t rst                          : 1;
 #endif
 	} s;
-	struct cvmx_ciu_intx_en4_1_w1s_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_1_w1s_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t nand                         : 1;  /**< NAND Flash Controller */
 	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
@@ -3217,9 +6909,8 @@ union cvmx_ciu_intx_en4_1_w1s
 	uint64_t reserved_20_63               : 44;
 #endif
 	} cn52xx;
-	struct cvmx_ciu_intx_en4_1_w1s_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_1_w1s_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t wdog                         : 12; /**< Watchdog summary interrupt enable vectory */
 #else
@@ -3227,9 +6918,8 @@ union cvmx_ciu_intx_en4_1_w1s
 	uint64_t reserved_12_63               : 52;
 #endif
 	} cn56xx;
-	struct cvmx_ciu_intx_en4_1_w1s_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_1_w1s_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t wdog                         : 16; /**< Watchdog summary interrupt enable vectory */
 #else
@@ -3237,9 +6927,81 @@ union cvmx_ciu_intx_en4_1_w1s
 	uint64_t reserved_16_63               : 48;
 #endif
 	} cn58xx;
-	struct cvmx_ciu_intx_en4_1_w1s_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_en4_1_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to set MIO RST interrupt enable */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< Write 1 to set LMC0 interrupt enable */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< Write 1 to set PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to set PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to set PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< Write 1 to set AGL interrupt enable */
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to set DPI_DMA interrupt enable */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< Write 1 to set GMX1 interrupt enable */
+	uint64_t agx0                         : 1;  /**< Write 1 to set GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to set DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to set SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to set USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< Write 1 to set DFA interrupt enable */
+	uint64_t key                          : 1;  /**< Write 1 to set KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to set RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to set TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< Write 1 to set ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< Write 1 to set PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to set PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to set IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to set L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to set POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to set FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to set IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to set MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to set EMMC Flash Controller interrupt
+                                                         enable */
+	uint64_t mii1                         : 1;  /**< Write 1 to set RGMII/MIX Interface 1 Interrupt
+                                                         enable */
+	uint64_t reserved_4_17                : 14;
+	uint64_t wdog                         : 4;  /**< Write 1s to set Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_17                : 14;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_intx_en4_1_w1s_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rst                          : 1;  /**< Write 1 to set MIO RST interrupt enable */
 	uint64_t reserved_57_62               : 6;
 	uint64_t dfm                          : 1;  /**< Write 1 to set DFM interrupt enable */
@@ -3312,18 +7074,163 @@ union cvmx_ciu_intx_en4_1_w1s
 #endif
 	} cn63xx;
 	struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1;
+	struct cvmx_ciu_intx_en4_1_w1s_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to set MIO RST interrupt enable */
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< Write 1 to set SRIO3 interrupt enable */
+	uint64_t srio2                        : 1;  /**< Write 1 to set SRIO2 interrupt enable */
+	uint64_t reserved_57_59               : 3;
+	uint64_t dfm                          : 1;  /**< Write 1 to set DFM interrupt enable */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< Write 1 to set LMC0 interrupt enable */
+	uint64_t reserved_51_51               : 1;
+	uint64_t srio0                        : 1;  /**< Write 1 to set SRIO0 interrupt enable */
+	uint64_t pem1                         : 1;  /**< Write 1 to set PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to set PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to set PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< Write 1 to set AGL interrupt enable */
+	uint64_t reserved_38_45               : 8;
+	uint64_t agx1                         : 1;  /**< Write 1 to set GMX1 interrupt enable */
+	uint64_t agx0                         : 1;  /**< Write 1 to set GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to set DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to set SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to set USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< Write 1 to set DFA interrupt enable */
+	uint64_t key                          : 1;  /**< Write 1 to set KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to set RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to set TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< Write 1 to set ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< Write 1 to set PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to set PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to set IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to set L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to set POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to set FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to set IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to set MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to set NAND Flash Controller interrupt
+                                                         enable */
+	uint64_t mii1                         : 1;  /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt
+                                                         enable */
+	uint64_t reserved_10_17               : 8;
+	uint64_t wdog                         : 10; /**< Write 1s to set Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 10;
+	uint64_t reserved_10_17               : 8;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_45               : 8;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t rst                          : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_intx_en4_1_w1s_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to set MIO RST interrupt enable */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< Write 1 to set LMC0 interrupt enable */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< Write 1 to set PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to set PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to set PTP interrupt enable */
+	uint64_t reserved_41_46               : 6;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to set DPI_DMA interrupt enable */
+	uint64_t reserved_37_39               : 3;
+	uint64_t agx0                         : 1;  /**< Write 1 to set GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to set DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to set SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to set USB UCTL0 interrupt enable */
+	uint64_t reserved_32_32               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to set KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to set RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to set TIM interrupt enable */
+	uint64_t reserved_28_28               : 1;
+	uint64_t pko                          : 1;  /**< Write 1 to set PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to set PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to set IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to set L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to set POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to set FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to set IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to set MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to set EMMC Flash Controller interrupt
+                                                         enable */
+	uint64_t reserved_4_18                : 15;
+	uint64_t wdog                         : 4;  /**< Write 1s to set Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_18                : 15;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_28_28               : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_32_32               : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_46               : 6;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_ciu_intx_en4_1_w1s cvmx_ciu_intx_en4_1_w1s_t;
 
 /**
  * cvmx_ciu_int#_sum0
  */
-union cvmx_ciu_intx_sum0
-{
+union cvmx_ciu_intx_sum0 {
 	uint64_t u64;
-	struct cvmx_ciu_intx_sum0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_sum0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
                                                          See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
 	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface 0 Interrupt
@@ -3334,19 +7241,26 @@ union cvmx_ciu_intx_sum0
                                                          See POW_IQ_INT */
 	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt
                                                          See MIO_TWS1_INT */
-	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt, Set when MPI transaction
+                                                         finished, see MPI_CFG[INT_ENA] and MPI_STS[BUSY] */
 	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
 	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt
                                                          See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
-	uint64_t timer                        : 4;  /**< General timer interrupts
-                                                         Set any time the corresponding CIU timer expires */
-	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt
-                                                         KEY_ZERO will be set when the external ZERO_KEYS
-                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
+	uint64_t timer                        : 4;  /**< General timer 0-3 interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
+                                                         common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                         will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                         are set at the same time, but clearing are based on
+                                                         per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
+                                                         interrupts. */
+	uint64_t reserved_51_51               : 1;
 	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt
                                                          Set any time PIP/IPD drops a packet */
-	uint64_t gmx_drp                      : 2;  /**< GMX packet drop interrupt
-                                                         Set any time corresponding GMX drops a packet */
+	uint64_t gmx_drp                      : 2;  /**< GMX0/1 packet drop interrupt
+                                                         Set any time corresponding GMX0/1 drops a packet */
 	uint64_t trace                        : 1;  /**< Trace buffer interrupt
                                                          See TRA_INT_STATUS */
 	uint64_t rml                          : 1;  /**< RML Interrupt
@@ -3356,30 +7270,37 @@ union cvmx_ciu_intx_sum0
                                                          See MIO_TWS0_INT */
 	uint64_t wdog_sum                     : 1;  /**< SUM1&EN1 summary bit
                                                          This read-only bit reads as a one whenever any
-                                                         CIU_INT_SUM1 bit is set and corresponding
-                                                         enable bit in CIU_INTx_EN is set, where x
-                                                         is the same as x in this CIU_INTx_SUM0.
-                                                         PPs use CIU_INTx_SUM0 where x=0-11
-                                                         PCIe/sRIO uses the CIU_INTx_SUM0 where x=32-33.
-                                                         Even INTx registers report WDOG to IP2
-                                                         Odd INTx registers report WDOG to IP3
-                                                         Note that WDOG_SUM only summarizes the SUM/EN1
+                                                         CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT)  bit is set
+                                                         and corresponding enable bit in CIU_INTx_EN is set
+                                                         PPs use CIU_INTx_SUM0 where x=0-7
+                                                         PCIe uses the CIU_INTx_SUM0 where x=32-33.
+                                                         Note that WDOG_SUM only summarizes the SUM1/EN1
                                                          result and does not have a corresponding enable
                                                          bit, so does not directly contribute to
                                                          interrupts. */
-	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI
+	uint64_t pci_msi                      : 4;  /**< PCIe MSI
                                                          See SLI_MSI_RCVn for bit <40+n> */
 	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D
                                                          Refer to "Receiving Emulated INTA/INTB/
-                                                         INTC/INTD" in the SLI chapter of the spec */
+                                                         INTC/INTD" in the SLI chapter of the spec
+                                                         PCI_INT<3> = INTD
+                                                         PCI_INT<2> = INTC
+                                                         PCI_INT<1> = INTB
+                                                         PCI_INT<0> = INTA */
 	uint64_t uart                         : 2;  /**< Two UART interrupts
                                                          See MIO_UARTn_IIR[IID] for bit <34+n> */
 	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-11
                                                           [33] is the or of <31:16>
                                                           [32] is the or of <15:0>
-                                                         Two PCIe/sRIO internal interrupts for entries 32-33
+                                                         Two PCIe internal interrupts for entries 32-33
                                                           which equal CIU_PCI_INTA[INT] */
-	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts
+                                                         When GPIO_MULTI_CAST[EN] == 1
+                                                         Write 1 to clear either the per PP or common GPIO
+                                                         edge-triggered interrupts,depending on mode.
+                                                         See GPIO_MULTI_CAST for all details.
+                                                         When GPIO_MULTI_CAST[EN] == 0
+                                                         Read Only, retain the same behavior as o63. */
 	uint64_t workq                        : 16; /**< 16 work queue interrupts
                                                          See POW_WQ_INT[WQ_INT]
                                                           1 bit/group. A copy of the R/W1C bit in the POW. */
@@ -3396,7 +7317,7 @@ union cvmx_ciu_intx_sum0
 	uint64_t trace                        : 1;
 	uint64_t gmx_drp                      : 2;
 	uint64_t ipd_drp                      : 1;
-	uint64_t key_zero                     : 1;
+	uint64_t reserved_51_51               : 1;
 	uint64_t timer                        : 4;
 	uint64_t usb                          : 1;
 	uint64_t pcm                          : 1;
@@ -3408,9 +7329,8 @@ union cvmx_ciu_intx_sum0
 	uint64_t bootdma                      : 1;
 #endif
 	} s;
-	struct cvmx_ciu_intx_sum0_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_sum0_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_59_63               : 5;
 	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
 	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
@@ -3465,9 +7385,8 @@ union cvmx_ciu_intx_sum0
 	uint64_t reserved_59_63               : 5;
 #endif
 	} cn30xx;
-	struct cvmx_ciu_intx_sum0_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_sum0_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_59_63               : 5;
 	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
 	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
@@ -3522,9 +7441,8 @@ union cvmx_ciu_intx_sum0
 	uint64_t reserved_59_63               : 5;
 #endif
 	} cn31xx;
-	struct cvmx_ciu_intx_sum0_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_sum0_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_56_63               : 8;
 	uint64_t timer                        : 4;  /**< General timer interrupts */
 	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt
@@ -3575,9 +7493,8 @@ union cvmx_ciu_intx_sum0
 	} cn38xx;
 	struct cvmx_ciu_intx_sum0_cn38xx      cn38xxp2;
 	struct cvmx_ciu_intx_sum0_cn30xx      cn50xx;
-	struct cvmx_ciu_intx_sum0_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_sum0_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
 	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
 	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
@@ -3647,9 +7564,8 @@ union cvmx_ciu_intx_sum0
 #endif
 	} cn52xx;
 	struct cvmx_ciu_intx_sum0_cn52xx      cn52xxp1;
-	struct cvmx_ciu_intx_sum0_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_sum0_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
 	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
 	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
@@ -3713,20 +7629,341 @@ union cvmx_ciu_intx_sum0
 	struct cvmx_ciu_intx_sum0_cn56xx      cn56xxp1;
 	struct cvmx_ciu_intx_sum0_cn38xx      cn58xx;
 	struct cvmx_ciu_intx_sum0_cn38xx      cn58xxp1;
+	struct cvmx_ciu_intx_sum0_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
+                                                         See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
+	uint64_t mii                          : 1;  /**< RGMII/MIX Interface 0 Interrupt
+                                                         See MIX0_ISR */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt
+                                                         See IPD_PORT_QOS_INT* */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt
+                                                         See POW_IQ_INT */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt
+                                                         See MIO_TWS1_INT */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt, Set when MPI transaction
+                                                         finished, see MPI_CFG[INT_ENA] and MPI_STS[BUSY] */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt
+                                                         See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
+	uint64_t timer                        : 4;  /**< General timer 0-3 interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
+                                                         common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                         will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                         are set at the same time, but clearing are based on
+                                                         per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
+                                                         interrupts. */
+	uint64_t sum2                         : 1;  /**< SUM2&EN2 SUMMARY bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT)  bit is set
+                                                         and corresponding enable bit in CIU_EN2_PPX_IPx
+                                                         (CIU_EN2_IOX_INT) is set.
+                                                         Note that SUM2 only summarizes the SUM2/EN2
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt
+                                                         Set any time PIP/IPD drops a packet */
+	uint64_t gmx_drp                      : 2;  /**< GMX0/1 packet drop interrupt
+                                                         Set any time corresponding GMX0/1 drops a packet */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t rml                          : 1;  /**< RML Interrupt
+                                                         This interrupt will assert if any bit within
+                                                         CIU_BLOCK_INT is asserted. */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt
+                                                         See MIO_TWS0_INT */
+	uint64_t wdog_sum                     : 1;  /**< SUM1&EN1 summary bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT)  bit is set
+                                                         and corresponding enable bit in CIU_INTx_EN is set
+                                                         PPs use CIU_INTx_SUM0 where x=0-7
+                                                         PCIe uses the CIU_INTx_SUM0 where x=32-33.
+                                                         Note that WDOG_SUM only summarizes the SUM1/EN1
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t pci_msi                      : 4;  /**< PCIe MSI
+                                                         See SLI_MSI_RCVn for bit <40+n> */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the SLI chapter of the spec
+                                                         PCI_INT<3> = INTD
+                                                         PCI_INT<2> = INTC
+                                                         PCI_INT<1> = INTB
+                                                         PCI_INT<0> = INTA */
+	uint64_t uart                         : 2;  /**< Two UART interrupts
+                                                         See MIO_UARTn_IIR[IID] for bit <34+n> */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-11
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCIe internal interrupts for entries 32-33
+                                                          which equal CIU_PCI_INTA[INT] */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts
+                                                         When GPIO_MULTI_CAST[EN] == 1
+                                                         Write 1 to clear either the per PP or common GPIO
+                                                         edge-triggered interrupts,depending on mode.
+                                                         See GPIO_MULTI_CAST for all details.
+                                                         When GPIO_MULTI_CAST[EN] == 0
+                                                         Read Only, retain the same behavior as o63. */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         See POW_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t sum2                         : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn61xx;
 	struct cvmx_ciu_intx_sum0_cn52xx      cn63xx;
 	struct cvmx_ciu_intx_sum0_cn52xx      cn63xxp1;
+	struct cvmx_ciu_intx_sum0_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
+                                                         See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface 0 Interrupt
+                                                         See MIX0_ISR */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt
+                                                         See IPD_PORT_QOS_INT* */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt
+                                                         See POW_IQ_INT */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt
+                                                         See MIO_TWS1_INT */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt, Set when MPI transaction
+                                                         finished, see MPI_CFG[INT_ENA] and MPI_STS[BUSY] */
+	uint64_t reserved_57_57               : 1;
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt
+                                                         See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
+	uint64_t timer                        : 4;  /**< General timer 0-3 interrupts.
+                                                         Prior to pass 1.2 or
+                                                          when CIU_TIM_MULTI_CAST[EN]==0, this interrupt is
+                                                          common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                          will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                          are set at the same time, but clearing is per
+                                                          cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
+                                                         interrupts. */
+	uint64_t sum2                         : 1;  /**< SUM2&EN2 SUMMARY bit
+                                                          In pass 1.2 and subsequent passes,
+                                                          this read-only bit reads as a one whenever any
+                                                          CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT)  bit is set
+                                                          and corresponding enable bit in CIU_EN2_PPX_IPx
+                                                          (CIU_EN2_IOX_INT) is set.
+                                                          Note that SUM2 only summarizes the SUM2/EN2
+                                                          result and does not have a corresponding enable
+                                                          bit, so does not directly contribute to
+                                                          interrupts.
+                                                         Prior to pass 1.2, SUM2 did not exist and this
+                                                          bit reads as zero. */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt
+                                                         Set any time PIP/IPD drops a packet */
+	uint64_t gmx_drp                      : 2;  /**< GMX0/1 packet drop interrupt
+                                                         Set any time corresponding GMX0/1 drops a packet */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t rml                          : 1;  /**< RML Interrupt
+                                                         This interrupt will assert if any bit within
+                                                         CIU_BLOCK_INT is asserted. */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt
+                                                         See MIO_TWS0_INT */
+	uint64_t wdog_sum                     : 1;  /**< SUM1&EN1 summary bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT)  bit is set
+                                                         and corresponding enable bit in CIU_INTx_EN is set
+                                                         PPs use CIU_INTx_SUM0 where x=0-19
+                                                         PCIe/sRIO uses the CIU_INTx_SUM0 where x=32-33.
+                                                         Note that WDOG_SUM only summarizes the SUM1/EN1
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI
+                                                         See SLI_MSI_RCVn for bit <40+n> */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the SLI chapter of the spec
+                                                         PCI_INT<3> = INTD
+                                                         PCI_INT<2> = INTC
+                                                         PCI_INT<1> = INTB
+                                                         PCI_INT<0> = INTA */
+	uint64_t uart                         : 2;  /**< Two UART interrupts
+                                                         See MIO_UARTn_IIR[IID] for bit <34+n> */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-11
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCIe/sRIO internal interrupts for entries 32-33
+                                                          which equal CIU_PCI_INTA[INT] */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         See POW_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t sum2                         : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_57               : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_intx_sum0_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
+                                                         See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
+	uint64_t reserved_62_62               : 1;
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt
+                                                         See IPD_PORT_QOS_INT* */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt
+                                                         See POW_IQ_INT */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt
+                                                         See MIO_TWS1_INT */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt, Set when MPI transaction
+                                                         finished, see MPI_CFG[INT_ENA] and MPI_STS[BUSY] */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt
+                                                         See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
+	uint64_t timer                        : 4;  /**< General timer 0-3 interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
+                                                         common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                         will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                         are set at the same time, but clearing are based on
+                                                         per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
+                                                         interrupts. */
+	uint64_t sum2                         : 1;  /**< SUM2&EN2 SUMMARY bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT)  bit is set
+                                                         and corresponding enable bit in CIU_EN2_PPX_IPx
+                                                         (CIU_EN2_IOX_INT) is set.
+                                                         Note that SUM2 only summarizes the SUM2/EN2
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt
+                                                         Set any time PIP/IPD drops a packet */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX0/1 packet drop interrupt
+                                                         Set any time corresponding GMX0/1 drops a packet */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t rml                          : 1;  /**< RML Interrupt
+                                                         This interrupt will assert if any bit within
+                                                         CIU_BLOCK_INT is asserted. */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt
+                                                         See MIO_TWS0_INT */
+	uint64_t wdog_sum                     : 1;  /**< SUM1&EN1 summary bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT)  bit is set
+                                                         and corresponding enable bit in CIU_INTx_EN is set
+                                                         PPs use CIU_INTx_SUM0 where x=0-7
+                                                         PCIe uses the CIU_INTx_SUM0 where x=32-33.
+                                                         Note that WDOG_SUM only summarizes the SUM1/EN1
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t pci_msi                      : 4;  /**< PCIe MSI
+                                                         See SLI_MSI_RCVn for bit <40+n> */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the SLI chapter of the spec
+                                                         PCI_INT<3> = INTD
+                                                         PCI_INT<2> = INTC
+                                                         PCI_INT<1> = INTB
+                                                         PCI_INT<0> = INTA */
+	uint64_t uart                         : 2;  /**< Two UART interrupts
+                                                         See MIO_UARTn_IIR[IID] for bit <34+n> */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-11
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCIe internal interrupts for entries 32-33
+                                                          which equal CIU_PCI_INTA[INT] */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts
+                                                         When GPIO_MULTI_CAST[EN] == 1
+                                                         Write 1 to clear either the per PP or common GPIO
+                                                         edge-triggered interrupts,depending on mode.
+                                                         See GPIO_MULTI_CAST for all details.
+                                                         When GPIO_MULTI_CAST[EN] == 0
+                                                         Read Only, retain the same behavior as o63. */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         See POW_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t sum2                         : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_ciu_intx_sum0 cvmx_ciu_intx_sum0_t;
 
 /**
  * cvmx_ciu_int#_sum4
  */
-union cvmx_ciu_intx_sum4
-{
+union cvmx_ciu_intx_sum4 {
 	uint64_t u64;
-	struct cvmx_ciu_intx_sum4_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_sum4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
                                                          See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
 	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface 0 Interrupt
@@ -3741,11 +7978,17 @@ union cvmx_ciu_intx_sum4
 	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
 	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt
                                                          See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
-	uint64_t timer                        : 4;  /**< General timer interrupts
-                                                         Set any time the corresponding CIU timer expires */
-	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt
-                                                         KEY_ZERO will be set when the external ZERO_KEYS
-                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
+	uint64_t timer                        : 4;  /**< General timer 0-3 interrupts
+                                                         When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
+                                                         common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                         will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                         are set at the same time, but clearing are based on
+                                                         per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
+                                                         interrupts. */
+	uint64_t reserved_51_51               : 1;
 	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt
                                                          Set any time PIP/IPD drops a packet */
 	uint64_t gmx_drp                      : 2;  /**< GMX packet drop interrupt
@@ -3757,27 +8000,38 @@ union cvmx_ciu_intx_sum4
                                                          CIU_BLOCK_INT. */
 	uint64_t twsi                         : 1;  /**< TWSI Interrupt
                                                          See MIO_TWS0_INT */
-	uint64_t wdog_sum                     : 1;  /**< SUM1&EN4_1 summary bit
+	uint64_t wdog_sum                     : 1;  /**< SUM1&EN1 summary bit
                                                          This read-only bit reads as a one whenever any
-                                                         CIU_INT_SUM1 bit is set and corresponding
-                                                         enable bit in CIU_INTx_EN4_1 is set, where x
-                                                         is the same as x in this CIU_INTx_SUM4.
-                                                         PPs use CIU_INTx_SUM4 for IP4, where x=PPid.
-                                                         Note that WDOG_SUM only summarizes the SUM/EN4_1
+                                                         CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT)  bit is set
+                                                         and corresponding enable bit in CIU_INTx_EN is set
+                                                         PPs use CIU_INTx_SUM0 where x=0-19
+                                                         PCIe uses the CIU_INTx_SUM0 where x=32-33.
+                                                         Note that WDOG_SUM only summarizes the SUM1/EN1
                                                          result and does not have a corresponding enable
                                                          bit, so does not directly contribute to
                                                          interrupts. */
-	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI
+	uint64_t pci_msi                      : 4;  /**< PCIe MSI
                                                          See SLI_MSI_RCVn for bit <40+n> */
 	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D
                                                          Refer to "Receiving Emulated INTA/INTB/
-                                                         INTC/INTD" in the SLI chapter of the spec */
+                                                         INTC/INTD" in the SLI chapter of the spec
+                                                         PCI_INT<3> = INTD
+                                                         PCI_INT<2> = INTC
+                                                         PCI_INT<1> = INTB
+                                                         PCI_INT<0> = INTA */
 	uint64_t uart                         : 2;  /**< Two UART interrupts
                                                          See MIO_UARTn_IIR[IID] for bit <34+n> */
 	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-5
                                                          [33] is the or of <31:16>
                                                          [32] is the or of <15:0> */
-	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts
+                                                         When GPIO_MULTI_CAST[EN] == 1
+                                                         Write 1 to clear either the per PP interrupt or
+                                                         common GPIO interrupt for all PP/IOs,depending
+                                                         on mode setting. This will apply to all 16 GPIOs.
+                                                         See GPIO_MULTI_CAST for all details
+                                                         When GPIO_MULTI_CAST[EN] == 0
+                                                         Read Only, retain the same behavior as o63. */
 	uint64_t workq                        : 16; /**< 16 work queue interrupts
                                                          See POW_WQ_INT[WQ_INT]
                                                           1 bit/group. A copy of the R/W1C bit in the POW. */
@@ -3794,7 +8048,7 @@ union cvmx_ciu_intx_sum4
 	uint64_t trace                        : 1;
 	uint64_t gmx_drp                      : 2;
 	uint64_t ipd_drp                      : 1;
-	uint64_t key_zero                     : 1;
+	uint64_t reserved_51_51               : 1;
 	uint64_t timer                        : 4;
 	uint64_t usb                          : 1;
 	uint64_t pcm                          : 1;
@@ -3806,9 +8060,8 @@ union cvmx_ciu_intx_sum4
 	uint64_t bootdma                      : 1;
 #endif
 	} s;
-	struct cvmx_ciu_intx_sum4_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_sum4_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_59_63               : 5;
 	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
 	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
@@ -3860,9 +8113,8 @@ union cvmx_ciu_intx_sum4
 	uint64_t reserved_59_63               : 5;
 #endif
 	} cn50xx;
-	struct cvmx_ciu_intx_sum4_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_sum4_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
 	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
 	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
@@ -3927,9 +8179,8 @@ union cvmx_ciu_intx_sum4
 #endif
 	} cn52xx;
 	struct cvmx_ciu_intx_sum4_cn52xx      cn52xxp1;
-	struct cvmx_ciu_intx_sum4_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_sum4_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
 	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
 	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
@@ -3986,9 +8237,8 @@ union cvmx_ciu_intx_sum4
 #endif
 	} cn56xx;
 	struct cvmx_ciu_intx_sum4_cn56xx      cn56xxp1;
-	struct cvmx_ciu_intx_sum4_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_intx_sum4_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_56_63               : 8;
 	uint64_t timer                        : 4;  /**< General timer interrupts */
 	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt
@@ -4035,20 +8285,439 @@ union cvmx_ciu_intx_sum4
 #endif
 	} cn58xx;
 	struct cvmx_ciu_intx_sum4_cn58xx      cn58xxp1;
+	struct cvmx_ciu_intx_sum4_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
+                                                         See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
+	uint64_t mii                          : 1;  /**< RGMII/MIX Interface 0 Interrupt
+                                                         See MIX0_ISR */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt
+                                                         See IPD_PORT_QOS_INT* */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt
+                                                         See POW_IQ_INT */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt
+                                                         See MIO_TWS1_INT */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt
+                                                         See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
+	uint64_t timer                        : 4;  /**< General timer 0-3 interrupts
+                                                         When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
+                                                         common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                         will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                         are set at the same time, but clearing are based on
+                                                         per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
+                                                         interrupts. */
+	uint64_t sum2                         : 1;  /**< SUM2&EN2 SUMMARY bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT)  bit is set
+                                                         and corresponding enable bit in CIU_EN2_PPX_IPx
+                                                         (CIU_EN2_IOX_INT) is set.
+                                                         Note that WDOG_SUM only summarizes the SUM2/EN2
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt
+                                                         Set any time PIP/IPD drops a packet */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop interrupt
+                                                         Set any time corresponding GMX drops a packet */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t rml                          : 1;  /**< RML Interrupt
+                                                         This bit is set when any bit is set in
+                                                         CIU_BLOCK_INT. */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt
+                                                         See MIO_TWS0_INT */
+	uint64_t wdog_sum                     : 1;  /**< SUM1&EN1 summary bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT)  bit is set
+                                                         and corresponding enable bit in CIU_INTx_EN is set
+                                                         PPs use CIU_INTx_SUM0 where x=0-19
+                                                         PCIe uses the CIU_INTx_SUM0 where x=32-33.
+                                                         Note that WDOG_SUM only summarizes the SUM1/EN1
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t pci_msi                      : 4;  /**< PCIe MSI
+                                                         See SLI_MSI_RCVn for bit <40+n> */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the SLI chapter of the spec
+                                                         PCI_INT<3> = INTD
+                                                         PCI_INT<2> = INTC
+                                                         PCI_INT<1> = INTB
+                                                         PCI_INT<0> = INTA */
+	uint64_t uart                         : 2;  /**< Two UART interrupts
+                                                         See MIO_UARTn_IIR[IID] for bit <34+n> */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-5
+                                                         [33] is the or of <31:16>
+                                                         [32] is the or of <15:0> */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts
+                                                         When GPIO_MULTI_CAST[EN] == 1
+                                                         Write 1 to clear either the per PP interrupt or
+                                                         common GPIO interrupt for all PP/IOs,depending
+                                                         on mode setting. This will apply to all 16 GPIOs.
+                                                         See GPIO_MULTI_CAST for all details
+                                                         When GPIO_MULTI_CAST[EN] == 0
+                                                         Read Only, retain the same behavior as o63. */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         See POW_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t sum2                         : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn61xx;
 	struct cvmx_ciu_intx_sum4_cn52xx      cn63xx;
 	struct cvmx_ciu_intx_sum4_cn52xx      cn63xxp1;
+	struct cvmx_ciu_intx_sum4_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
+                                                         See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface 0 Interrupt
+                                                         See MIX0_ISR */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt
+                                                         See IPD_PORT_QOS_INT* */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt
+                                                         See POW_IQ_INT */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt
+                                                         See MIO_TWS1_INT */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
+	uint64_t reserved_57_57               : 1;
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt
+                                                         See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
+	uint64_t timer                        : 4;  /**< General timer 0-3 interrupts.
+                                                         Prior to pass 1.2 or
+                                                          when CIU_TIM_MULTI_CAST[EN]==0, this interrupt is
+                                                          common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                          will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                          are set at the same time, but clearing is per
+                                                          cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
+                                                         interrupts. */
+	uint64_t sum2                         : 1;  /**< SUM2&EN2 SUMMARY bit
+                                                          In pass 1.2 and subsequent passes,
+                                                          this read-only bit reads as a one whenever any
+                                                          CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT)  bit is set
+                                                          and corresponding enable bit in CIU_EN2_PPX_IPx
+                                                          (CIU_EN2_IOX_INT) is set.
+                                                          Note that WDOG_SUM only summarizes the SUM2/EN2
+                                                          result and does not have a corresponding enable
+                                                          bit, so does not directly contribute to
+                                                          interrupts.
+                                                         Prior to pass 1.2, SUM2 did not exist and this
+                                                          bit reads as zero. */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt
+                                                         Set any time PIP/IPD drops a packet */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop interrupt
+                                                         Set any time corresponding GMX drops a packet */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t rml                          : 1;  /**< RML Interrupt
+                                                         This bit is set when any bit is set in
+                                                         CIU_BLOCK_INT. */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt
+                                                         See MIO_TWS0_INT */
+	uint64_t wdog_sum                     : 1;  /**< SUM1&EN1 summary bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT)  bit is set
+                                                         and corresponding enable bit in CIU_INTx_EN is set
+                                                         PPs use CIU_INTx_SUM0 where x=0-19
+                                                         PCIe/sRIO uses the CIU_INTx_SUM0 where x=32-33.
+                                                         Note that WDOG_SUM only summarizes the SUM1/EN1
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI
+                                                         See SLI_MSI_RCVn for bit <40+n> */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the SLI chapter of the spec
+                                                         PCI_INT<3> = INTD
+                                                         PCI_INT<2> = INTC
+                                                         PCI_INT<1> = INTB
+                                                         PCI_INT<0> = INTA */
+	uint64_t uart                         : 2;  /**< Two UART interrupts
+                                                         See MIO_UARTn_IIR[IID] for bit <34+n> */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-5
+                                                         [33] is the or of <31:16>
+                                                         [32] is the or of <15:0> */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         See POW_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t sum2                         : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_57               : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_intx_sum4_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
+                                                         See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
+	uint64_t reserved_62_62               : 1;
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt
+                                                         See IPD_PORT_QOS_INT* */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt
+                                                         See POW_IQ_INT */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt
+                                                         See MIO_TWS1_INT */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt
+                                                         See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
+	uint64_t timer                        : 4;  /**< General timer 0-3 interrupts
+                                                         When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
+                                                         common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                         will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                         are set at the same time, but clearing are based on
+                                                         per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
+                                                         interrupts. */
+	uint64_t sum2                         : 1;  /**< SUM2&EN2 SUMMARY bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT)  bit is set
+                                                         and corresponding enable bit in CIU_EN2_PPX_IPx
+                                                         (CIU_EN2_IOX_INT) is set.
+                                                         Note that WDOG_SUM only summarizes the SUM2/EN2
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt
+                                                         Set any time PIP/IPD drops a packet */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop interrupt
+                                                         Set any time corresponding GMX drops a packet */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t rml                          : 1;  /**< RML Interrupt
+                                                         This bit is set when any bit is set in
+                                                         CIU_BLOCK_INT. */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt
+                                                         See MIO_TWS0_INT */
+	uint64_t wdog_sum                     : 1;  /**< SUM1&EN1 summary bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT)  bit is set
+                                                         and corresponding enable bit in CIU_INTx_EN is set
+                                                         PPs use CIU_INTx_SUM0 where x=0-19
+                                                         PCIe uses the CIU_INTx_SUM0 where x=32-33.
+                                                         Note that WDOG_SUM only summarizes the SUM1/EN1
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t pci_msi                      : 4;  /**< PCIe MSI
+                                                         See SLI_MSI_RCVn for bit <40+n> */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the SLI chapter of the spec
+                                                         PCI_INT<3> = INTD
+                                                         PCI_INT<2> = INTC
+                                                         PCI_INT<1> = INTB
+                                                         PCI_INT<0> = INTA */
+	uint64_t uart                         : 2;  /**< Two UART interrupts
+                                                         See MIO_UARTn_IIR[IID] for bit <34+n> */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-5
+                                                         [33] is the or of <31:16>
+                                                         [32] is the or of <15:0> */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts
+                                                         When GPIO_MULTI_CAST[EN] == 1
+                                                         Write 1 to clear either the per PP interrupt or
+                                                         common GPIO interrupt for all PP/IOs,depending
+                                                         on mode setting. This will apply to all 16 GPIOs.
+                                                         See GPIO_MULTI_CAST for all details
+                                                         When GPIO_MULTI_CAST[EN] == 0
+                                                         Read Only, retain the same behavior as o63. */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         See POW_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t sum2                         : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_ciu_intx_sum4 cvmx_ciu_intx_sum4_t;
 
 /**
  * cvmx_ciu_int33_sum0
  */
-union cvmx_ciu_int33_sum0
-{
+union cvmx_ciu_int33_sum0 {
 	uint64_t u64;
-	struct cvmx_ciu_int33_sum0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_int33_sum0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
+                                                         See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface 0 Interrupt
+                                                         See MIX0_ISR */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt
+                                                         See IPD_PORT_QOS_INT* */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt
+                                                         See POW_IQ_INT */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt
+                                                         See MIO_TWS1_INT */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt
+                                                         See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
+	uint64_t timer                        : 4;  /**< General timer 0-3 interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
+                                                         common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                         will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                         are set at the same time, but clearing are based on
+                                                         per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
+                                                         interrupts. */
+	uint64_t sum2                         : 1;  /**< SUM2&EN2 SUMMARY bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT)  bit is set
+                                                         and corresponding enable bit in CIU_EN2_PPX_IPx
+                                                         (CIU_EN2_IOX_INT) is set.
+                                                         Note that SUM2 only summarizes the SUM2/EN2
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt
+                                                         Set any time PIP/IPD drops a packet */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop interrupt
+                                                         Set any time corresponding GMX drops a packet */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t rml                          : 1;  /**< RML Interrupt
+                                                         This interrupt will assert if any bit within
+                                                         CIU_BLOCK_INT is asserted. */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt
+                                                         See MIO_TWS0_INT */
+	uint64_t wdog_sum                     : 1;  /**< SUM1&EN1 summary bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_SUM1_PPX_IPx bit is set and corresponding
+                                                         enable bit in CIU_INTx_EN is set, where x
+                                                         is the same as x in this CIU_INTx_SUM0.
+                                                         PPs use CIU_INTx_SUM0 where x=0-7.
+                                                         PCIe uses the CIU_INTx_SUM0 where x=32-33.
+                                                         Note that WDOG_SUM only summarizes the SUM1/EN1
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t pci_msi                      : 4;  /**< PCIe MSI
+                                                         See SLI_MSI_RCVn for bit <40+n> */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the SLI chapter of the spec
+                                                         PCI_INT<3> = INTD
+                                                         PCI_INT<2> = INTC
+                                                         PCI_INT<1> = INTB
+                                                         PCI_INT<0> = INTA */
+	uint64_t uart                         : 2;  /**< Two UART interrupts
+                                                         See MIO_UARTn_IIR[IID] for bit <34+n> */
+	uint64_t mbox                         : 2;  /**< A read-only copy of CIU_PCI_INTA[INT] */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts
+                                                         When GPIO_MULTI_CAST[EN] == 1
+                                                         Write 1 to clear either the per PP or common GPIO
+                                                         edge-triggered interrupts,depending on mode.
+                                                         See GPIO_MULTI_CAST for all details.
+                                                         When GPIO_MULTI_CAST[EN] == 0
+                                                         Read Only, retain the same behavior as o63. */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         See POW_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t sum2                         : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} s;
+	struct cvmx_ciu_int33_sum0_s          cn61xx;
+	struct cvmx_ciu_int33_sum0_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
                                                          See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
 	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface 0 Interrupt
@@ -4094,7 +8763,11 @@ union cvmx_ciu_int33_sum0
                                                          See SLI_MSI_RCVn for bit <40+n> */
 	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D
                                                          Refer to "Receiving Emulated INTA/INTB/
-                                                         INTC/INTD" in the SLI chapter of the spec */
+                                                         INTC/INTD" in the SLI chapter of the spec
+                                                         PCI_INT<3> = INTD
+                                                         PCI_INT<2> = INTC
+                                                         PCI_INT<1> = INTB
+                                                         PCI_INT<0> = INTA */
 	uint64_t uart                         : 2;  /**< Two UART interrupts
                                                          See MIO_UARTn_IIR[IID] for bit <34+n> */
 	uint64_t mbox                         : 2;  /**< A read-only copy of CIU_PCI_INTA[INT] */
@@ -4126,21 +8799,276 @@ union cvmx_ciu_int33_sum0
 	uint64_t mii                          : 1;
 	uint64_t bootdma                      : 1;
 #endif
-	} s;
-	struct cvmx_ciu_int33_sum0_s          cn63xx;
-	struct cvmx_ciu_int33_sum0_s          cn63xxp1;
+	} cn63xx;
+	struct cvmx_ciu_int33_sum0_cn63xx     cn63xxp1;
+	struct cvmx_ciu_int33_sum0_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
+                                                         See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface 0 Interrupt
+                                                         See MIX0_ISR */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt
+                                                         See IPD_PORT_QOS_INT* */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt
+                                                         See POW_IQ_INT */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt
+                                                         See MIO_TWS1_INT */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
+	uint64_t reserved_57_57               : 1;
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt
+                                                         See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
+	uint64_t timer                        : 4;  /**< General timer 0-3 interrupts.
+                                                         Prior to pass 1.2 or
+                                                          when CIU_TIM_MULTI_CAST[EN]==0, this interrupt is
+                                                          common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                          will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                          are set at the same time, but clearing is per
+                                                          cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
+                                                         interrupts. */
+	uint64_t sum2                         : 1;  /**< SUM2&EN2 SUMMARY bit
+                                                          In pass 1.2 and subsequent passes,
+                                                          this read-only bit reads as a one whenever any
+                                                          CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT)  bit is set
+                                                          and corresponding enable bit in CIU_EN2_PPX_IPx
+                                                          (CIU_EN2_IOX_INT) is set.
+                                                          Note that SUM2 only summarizes the SUM2/EN2
+                                                          result and does not have a corresponding enable
+                                                          bit, so does not directly contribute to
+                                                          interrupts.
+                                                         Prior to pass 1.2, SUM2 did not exist and this
+                                                          bit reads as zero. */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt
+                                                         Set any time PIP/IPD drops a packet */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop interrupt
+                                                         Set any time corresponding GMX drops a packet */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t rml                          : 1;  /**< RML Interrupt
+                                                         This interrupt will assert if any bit within
+                                                         CIU_BLOCK_INT is asserted. */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt
+                                                         See MIO_TWS0_INT */
+	uint64_t wdog_sum                     : 1;  /**< SUM1&EN1 summary bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT)  bit is set
+                                                         and corresponding enable bit in CIU_INTx_EN is set
+                                                         PPs use CIU_INTx_SUM0 where x=0-19
+                                                         PCIe/sRIO uses the CIU_INTx_SUM0 where x=32-33.
+                                                         Note that WDOG_SUM only summarizes the SUM1/EN1
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI
+                                                         See SLI_MSI_RCVn for bit <40+n> */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the SLI chapter of the spec
+                                                         PCI_INT<3> = INTD
+                                                         PCI_INT<2> = INTC
+                                                         PCI_INT<1> = INTB
+                                                         PCI_INT<0> = INTA */
+	uint64_t uart                         : 2;  /**< Two UART interrupts
+                                                         See MIO_UARTn_IIR[IID] for bit <34+n> */
+	uint64_t mbox                         : 2;  /**< A read-only copy of CIU_PCI_INTA[INT] */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         See POW_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t sum2                         : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_57               : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_int33_sum0_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
+                                                         See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
+	uint64_t reserved_62_62               : 1;
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt
+                                                         See IPD_PORT_QOS_INT* */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt
+                                                         See POW_IQ_INT */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt
+                                                         See MIO_TWS1_INT */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt
+                                                         See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
+	uint64_t timer                        : 4;  /**< General timer 0-3 interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
+                                                         common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                         will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                         are set at the same time, but clearing are based on
+                                                         per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
+                                                         interrupts. */
+	uint64_t sum2                         : 1;  /**< SUM2&EN2 SUMMARY bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT)  bit is set
+                                                         and corresponding enable bit in CIU_EN2_PPX_IPx
+                                                         (CIU_EN2_IOX_INT) is set.
+                                                         Note that SUM2 only summarizes the SUM2/EN2
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt
+                                                         Set any time PIP/IPD drops a packet */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop interrupt
+                                                         Set any time corresponding GMX drops a packet */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t rml                          : 1;  /**< RML Interrupt
+                                                         This interrupt will assert if any bit within
+                                                         CIU_BLOCK_INT is asserted. */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt
+                                                         See MIO_TWS0_INT */
+	uint64_t wdog_sum                     : 1;  /**< SUM1&EN1 summary bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_SUM1_PPX_IPx bit is set and corresponding
+                                                         enable bit in CIU_INTx_EN is set, where x
+                                                         is the same as x in this CIU_INTx_SUM0.
+                                                         PPs use CIU_INTx_SUM0 where x=0-7.
+                                                         PCIe uses the CIU_INTx_SUM0 where x=32-33.
+                                                         Note that WDOG_SUM only summarizes the SUM1/EN1
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t pci_msi                      : 4;  /**< PCIe MSI
+                                                         See SLI_MSI_RCVn for bit <40+n> */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the SLI chapter of the spec
+                                                         PCI_INT<3> = INTD
+                                                         PCI_INT<2> = INTC
+                                                         PCI_INT<1> = INTB
+                                                         PCI_INT<0> = INTA */
+	uint64_t uart                         : 2;  /**< Two UART interrupts
+                                                         See MIO_UARTn_IIR[IID] for bit <34+n> */
+	uint64_t mbox                         : 2;  /**< A read-only copy of CIU_PCI_INTA[INT] */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts
+                                                         When GPIO_MULTI_CAST[EN] == 1
+                                                         Write 1 to clear either the per PP or common GPIO
+                                                         edge-triggered interrupts,depending on mode.
+                                                         See GPIO_MULTI_CAST for all details.
+                                                         When GPIO_MULTI_CAST[EN] == 0
+                                                         Read Only, retain the same behavior as o63. */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         See POW_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t sum2                         : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_ciu_int33_sum0 cvmx_ciu_int33_sum0_t;
 
 /**
  * cvmx_ciu_int_dbg_sel
  */
-union cvmx_ciu_int_dbg_sel
-{
+union cvmx_ciu_int_dbg_sel {
 	uint64_t u64;
-	struct cvmx_ciu_int_dbg_sel_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_int_dbg_sel_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_19_63               : 45;
+	uint64_t sel                          : 3;  /**< Selects if all or the specific interrupt is
+                                                         presented on the debug port.
+                                                         0=erst_n
+                                                         1=start_bist
+                                                         2=toggle at sclk/2 freq
+                                                         3=All PP interrupt bits are ORed together
+                                                         4=Only the selected virtual  PP/IRQ is selected */
+	uint64_t reserved_10_15               : 6;
+	uint64_t irq                          : 2;  /**< Which IRQ to select
+                                                         0=IRQ2
+                                                         1=IRQ3
+                                                         2=IRQ4 */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t pp                           : 5;  /**< Which PP to select */
+#else
+	uint64_t pp                           : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t irq                          : 2;
+	uint64_t reserved_10_15               : 6;
+	uint64_t sel                          : 3;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} s;
+	struct cvmx_ciu_int_dbg_sel_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_19_63               : 45;
+	uint64_t sel                          : 3;  /**< Selects if all or the specific interrupt is
+                                                         presented on the debug port.
+                                                         0=erst_n
+                                                         1=start_bist
+                                                         2=toggle at sclk/2 freq
+                                                         3=All PP interrupt bits are ORed together
+                                                         4=Only the selected virtual  PP/IRQ is selected */
+	uint64_t reserved_10_15               : 6;
+	uint64_t irq                          : 2;  /**< Which IRQ to select
+                                                         0=IRQ2
+                                                         1=IRQ3
+                                                         2=IRQ4 */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pp                           : 4;  /**< Which PP to select */
+#else
+	uint64_t pp                           : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t irq                          : 2;
+	uint64_t reserved_10_15               : 6;
+	uint64_t sel                          : 3;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_int_dbg_sel_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t sel                          : 3;  /**< Selects if all or the specific interrupt is
                                                          presented on the debug port.
@@ -4148,7 +9076,7 @@ union cvmx_ciu_int_dbg_sel
                                                          1=start_bist
                                                          2=toggle at sclk/2 freq
                                                          3=All PP interrupt bits are ORed together
-                                                         4=Only the selected PP/IRQ is selected */
+                                                         4=Only the selected physical PP/IRQ is selected */
 	uint64_t reserved_10_15               : 6;
 	uint64_t irq                          : 2;  /**< Which IRQ to select
                                                          0=IRQ2
@@ -4164,23 +9092,29 @@ union cvmx_ciu_int_dbg_sel
 	uint64_t sel                          : 3;
 	uint64_t reserved_19_63               : 45;
 #endif
-	} s;
-	struct cvmx_ciu_int_dbg_sel_s         cn63xx;
+	} cn63xx;
+	struct cvmx_ciu_int_dbg_sel_cn61xx    cn66xx;
+	struct cvmx_ciu_int_dbg_sel_s         cn68xx;
+	struct cvmx_ciu_int_dbg_sel_s         cn68xxp1;
+	struct cvmx_ciu_int_dbg_sel_cn61xx    cnf71xx;
 };
 typedef union cvmx_ciu_int_dbg_sel cvmx_ciu_int_dbg_sel_t;
 
 /**
  * cvmx_ciu_int_sum1
  */
-union cvmx_ciu_int_sum1
-{
+union cvmx_ciu_int_sum1 {
 	uint64_t u64;
-	struct cvmx_ciu_int_sum1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_int_sum1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rst                          : 1;  /**< MIO RST interrupt
                                                          See MIO_RST_INT */
-	uint64_t reserved_57_62               : 6;
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< SRIO3 interrupt
+                                                         See SRIO3_INT_REG, SRIO3_INT2_REG */
+	uint64_t srio2                        : 1;  /**< SRIO2 interrupt
+                                                         See SRIO2_INT_REG, SRIO2_INT2_REG */
+	uint64_t reserved_57_59               : 3;
 	uint64_t dfm                          : 1;  /**< DFM Interrupt
                                                          See DFM_FNT_STAT */
 	uint64_t reserved_53_55               : 3;
@@ -4189,7 +9123,7 @@ union cvmx_ciu_int_sum1
 	uint64_t srio1                        : 1;  /**< SRIO1 interrupt
                                                          See SRIO1_INT_REG */
 	uint64_t srio0                        : 1;  /**< SRIO0 interrupt
-                                                         See SRIO0_INT_REG */
+                                                         See SRIO0_INT_REG, SRIO0_INT2_REG */
 	uint64_t pem1                         : 1;  /**< PEM1 interrupt
                                                          See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
 	uint64_t pem0                         : 1;  /**< PEM0 interrupt
@@ -4198,7 +9132,10 @@ union cvmx_ciu_int_sum1
                                                          Set when HW decrements MIO_PTP_EVT_CNT to zero */
 	uint64_t agl                          : 1;  /**< AGL interrupt
                                                          See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
-	uint64_t reserved_37_45               : 9;
+	uint64_t reserved_38_45               : 8;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt
+                                                         See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
+                                                         PCS1_INT*_REG, PCSX1_INT_REG */
 	uint64_t agx0                         : 1;  /**< GMX0 interrupt
                                                          See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
                                                          PCS0_INT*_REG, PCSX0_INT_REG */
@@ -4234,13 +9171,13 @@ union cvmx_ciu_int_sum1
                                                          See IOB_INT_SUM */
 	uint64_t mio                          : 1;  /**< MIO boot interrupt
                                                          See MIO_BOOT_ERR */
-	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt
-                                                         See NDF_INT */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt
+                                                         See  EMMC interrupt */
 	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt
                                                          See MIX1_ISR */
 	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
 	uint64_t uart2                        : 1;  /**< Third UART interrupt */
-	uint64_t wdog                         : 16; /**< 6 watchdog interrupts */
+	uint64_t wdog                         : 16; /**< Per PP watchdog interrupts */
 #else
 	uint64_t wdog                         : 16;
 	uint64_t uart2                        : 1;
@@ -4264,7 +9201,8 @@ union cvmx_ciu_int_sum1
 	uint64_t sli                          : 1;
 	uint64_t dpi                          : 1;
 	uint64_t agx0                         : 1;
-	uint64_t reserved_37_45               : 9;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_45               : 8;
 	uint64_t agl                          : 1;
 	uint64_t ptp                          : 1;
 	uint64_t pem0                         : 1;
@@ -4274,13 +9212,15 @@ union cvmx_ciu_int_sum1
 	uint64_t lmc0                         : 1;
 	uint64_t reserved_53_55               : 3;
 	uint64_t dfm                          : 1;
-	uint64_t reserved_57_62               : 6;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
 	uint64_t rst                          : 1;
 #endif
 	} s;
-	struct cvmx_ciu_int_sum1_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_int_sum1_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t wdog                         : 1;  /**< 1 watchdog interrupt */
 #else
@@ -4288,9 +9228,8 @@ union cvmx_ciu_int_sum1
 	uint64_t reserved_1_63                : 63;
 #endif
 	} cn30xx;
-	struct cvmx_ciu_int_sum1_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_int_sum1_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t wdog                         : 2;  /**< 2 watchdog interrupts */
 #else
@@ -4298,9 +9237,8 @@ union cvmx_ciu_int_sum1
 	uint64_t reserved_2_63                : 62;
 #endif
 	} cn31xx;
-	struct cvmx_ciu_int_sum1_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_int_sum1_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t wdog                         : 16; /**< 16 watchdog interrupts */
 #else
@@ -4310,9 +9248,8 @@ union cvmx_ciu_int_sum1
 	} cn38xx;
 	struct cvmx_ciu_int_sum1_cn38xx       cn38xxp2;
 	struct cvmx_ciu_int_sum1_cn31xx       cn50xx;
-	struct cvmx_ciu_int_sum1_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_int_sum1_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t nand                         : 1;  /**< NAND Flash Controller */
 	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
@@ -4330,9 +9267,8 @@ union cvmx_ciu_int_sum1
 	uint64_t reserved_20_63               : 44;
 #endif
 	} cn52xx;
-	struct cvmx_ciu_int_sum1_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_int_sum1_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
 	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
@@ -4348,9 +9284,8 @@ union cvmx_ciu_int_sum1
 	uint64_t reserved_19_63               : 45;
 #endif
 	} cn52xxp1;
-	struct cvmx_ciu_int_sum1_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_int_sum1_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t wdog                         : 12; /**< 12 watchdog interrupts */
 #else
@@ -4361,9 +9296,103 @@ union cvmx_ciu_int_sum1
 	struct cvmx_ciu_int_sum1_cn56xx       cn56xxp1;
 	struct cvmx_ciu_int_sum1_cn38xx       cn58xx;
 	struct cvmx_ciu_int_sum1_cn38xx       cn58xxp1;
-	struct cvmx_ciu_int_sum1_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_int_sum1_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_38_45               : 8;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt
+                                                         See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
+                                                         PCS1_INT*_REG, PCSX1_INT_REG */
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt
+                                                         See  EMMC interrupt */
+	uint64_t mii1                         : 1;  /**< RGMII/MIX Interface 1 Interrupt
+                                                         See MIX1_ISR */
+	uint64_t reserved_4_17                : 14;
+	uint64_t wdog                         : 4;  /**< Per PP watchdog interrupts */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_17                : 14;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_45               : 8;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_int_sum1_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rst                          : 1;  /**< MIO RST interrupt
                                                          See MIO_RST_INT */
 	uint64_t reserved_57_62               : 6;
@@ -4463,18 +9492,210 @@ union cvmx_ciu_int_sum1
 #endif
 	} cn63xx;
 	struct cvmx_ciu_int_sum1_cn63xx       cn63xxp1;
+	struct cvmx_ciu_int_sum1_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< SRIO3 interrupt
+                                                         See SRIO3_INT_REG, SRIO3_INT2_REG */
+	uint64_t srio2                        : 1;  /**< SRIO2 interrupt
+                                                         See SRIO2_INT_REG, SRIO2_INT2_REG */
+	uint64_t reserved_57_59               : 3;
+	uint64_t dfm                          : 1;  /**< DFM Interrupt
+                                                         See DFM_FNT_STAT */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_51_51               : 1;
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt
+                                                         See SRIO0_INT_REG, SRIO0_INT2_REG */
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_38_45               : 8;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt
+                                                         See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
+                                                         PCS1_INT*_REG, PCSX1_INT_REG */
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt
+                                                         See NDF_INT */
+	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt
+                                                         See MIX1_ISR */
+	uint64_t reserved_10_17               : 8;
+	uint64_t wdog                         : 10; /**< 10 watchdog interrupts */
+#else
+	uint64_t wdog                         : 10;
+	uint64_t reserved_10_17               : 8;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_45               : 8;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t rst                          : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_int_sum1_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t reserved_37_46               : 10;
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t reserved_32_32               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t reserved_28_28               : 1;
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt
+                                                         See  EMMC interrupt */
+	uint64_t reserved_4_18                : 15;
+	uint64_t wdog                         : 4;  /**< Per PP watchdog interrupts */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_18                : 15;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_28_28               : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_32_32               : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_46               : 10;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_ciu_int_sum1 cvmx_ciu_int_sum1_t;
 
 /**
  * cvmx_ciu_mbox_clr#
  */
-union cvmx_ciu_mbox_clrx
-{
+union cvmx_ciu_mbox_clrx {
 	uint64_t u64;
-	struct cvmx_ciu_mbox_clrx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_mbox_clrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t bits                         : 32; /**< On writes, clr corresponding bit in MBOX register
                                                          on reads, return the MBOX register */
@@ -4494,20 +9715,23 @@ union cvmx_ciu_mbox_clrx
 	struct cvmx_ciu_mbox_clrx_s           cn56xxp1;
 	struct cvmx_ciu_mbox_clrx_s           cn58xx;
 	struct cvmx_ciu_mbox_clrx_s           cn58xxp1;
+	struct cvmx_ciu_mbox_clrx_s           cn61xx;
 	struct cvmx_ciu_mbox_clrx_s           cn63xx;
 	struct cvmx_ciu_mbox_clrx_s           cn63xxp1;
+	struct cvmx_ciu_mbox_clrx_s           cn66xx;
+	struct cvmx_ciu_mbox_clrx_s           cn68xx;
+	struct cvmx_ciu_mbox_clrx_s           cn68xxp1;
+	struct cvmx_ciu_mbox_clrx_s           cnf71xx;
 };
 typedef union cvmx_ciu_mbox_clrx cvmx_ciu_mbox_clrx_t;
 
 /**
  * cvmx_ciu_mbox_set#
  */
-union cvmx_ciu_mbox_setx
-{
+union cvmx_ciu_mbox_setx {
 	uint64_t u64;
-	struct cvmx_ciu_mbox_setx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_mbox_setx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t bits                         : 32; /**< On writes, set corresponding bit in MBOX register
                                                          on reads, return the MBOX register */
@@ -4527,30 +9751,32 @@ union cvmx_ciu_mbox_setx
 	struct cvmx_ciu_mbox_setx_s           cn56xxp1;
 	struct cvmx_ciu_mbox_setx_s           cn58xx;
 	struct cvmx_ciu_mbox_setx_s           cn58xxp1;
+	struct cvmx_ciu_mbox_setx_s           cn61xx;
 	struct cvmx_ciu_mbox_setx_s           cn63xx;
 	struct cvmx_ciu_mbox_setx_s           cn63xxp1;
+	struct cvmx_ciu_mbox_setx_s           cn66xx;
+	struct cvmx_ciu_mbox_setx_s           cn68xx;
+	struct cvmx_ciu_mbox_setx_s           cn68xxp1;
+	struct cvmx_ciu_mbox_setx_s           cnf71xx;
 };
 typedef union cvmx_ciu_mbox_setx cvmx_ciu_mbox_setx_t;
 
 /**
  * cvmx_ciu_nmi
  */
-union cvmx_ciu_nmi
-{
+union cvmx_ciu_nmi {
 	uint64_t u64;
-	struct cvmx_ciu_nmi_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_16_63               : 48;
-	uint64_t nmi                          : 16; /**< Send NMI pulse to PP vector */
+	struct cvmx_ciu_nmi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t nmi                          : 32; /**< Send NMI pulse to PP vector */
 #else
-	uint64_t nmi                          : 16;
-	uint64_t reserved_16_63               : 48;
+	uint64_t nmi                          : 32;
+	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
-	struct cvmx_ciu_nmi_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_nmi_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t nmi                          : 1;  /**< Send NMI pulse to PP vector */
 #else
@@ -4558,9 +9784,8 @@ union cvmx_ciu_nmi
 	uint64_t reserved_1_63                : 63;
 #endif
 	} cn30xx;
-	struct cvmx_ciu_nmi_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_nmi_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t nmi                          : 2;  /**< Send NMI pulse to PP vector */
 #else
@@ -4568,12 +9793,19 @@ union cvmx_ciu_nmi
 	uint64_t reserved_2_63                : 62;
 #endif
 	} cn31xx;
-	struct cvmx_ciu_nmi_s                 cn38xx;
-	struct cvmx_ciu_nmi_s                 cn38xxp2;
+	struct cvmx_ciu_nmi_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t nmi                          : 16; /**< Send NMI pulse to PP vector */
+#else
+	uint64_t nmi                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn38xx;
+	struct cvmx_ciu_nmi_cn38xx            cn38xxp2;
 	struct cvmx_ciu_nmi_cn31xx            cn50xx;
-	struct cvmx_ciu_nmi_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_nmi_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t nmi                          : 4;  /**< Send NMI pulse to PP vector */
 #else
@@ -4582,9 +9814,8 @@ union cvmx_ciu_nmi
 #endif
 	} cn52xx;
 	struct cvmx_ciu_nmi_cn52xx            cn52xxp1;
-	struct cvmx_ciu_nmi_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_nmi_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t nmi                          : 12; /**< Send NMI pulse to PP vector */
 #else
@@ -4593,11 +9824,11 @@ union cvmx_ciu_nmi
 #endif
 	} cn56xx;
 	struct cvmx_ciu_nmi_cn56xx            cn56xxp1;
-	struct cvmx_ciu_nmi_s                 cn58xx;
-	struct cvmx_ciu_nmi_s                 cn58xxp1;
-	struct cvmx_ciu_nmi_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_nmi_cn38xx            cn58xx;
+	struct cvmx_ciu_nmi_cn38xx            cn58xxp1;
+	struct cvmx_ciu_nmi_cn52xx            cn61xx;
+	struct cvmx_ciu_nmi_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t nmi                          : 6;  /**< Send NMI pulse to PP vector */
 #else
@@ -4606,20 +9837,30 @@ union cvmx_ciu_nmi
 #endif
 	} cn63xx;
 	struct cvmx_ciu_nmi_cn63xx            cn63xxp1;
+	struct cvmx_ciu_nmi_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t nmi                          : 10; /**< Send NMI pulse to PP vector */
+#else
+	uint64_t nmi                          : 10;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_nmi_s                 cn68xx;
+	struct cvmx_ciu_nmi_s                 cn68xxp1;
+	struct cvmx_ciu_nmi_cn52xx            cnf71xx;
 };
 typedef union cvmx_ciu_nmi cvmx_ciu_nmi_t;
 
 /**
  * cvmx_ciu_pci_inta
  */
-union cvmx_ciu_pci_inta
-{
+union cvmx_ciu_pci_inta {
 	uint64_t u64;
-	struct cvmx_ciu_pci_inta_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_pci_inta_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
-	uint64_t intr                         : 2;  /**< PCIe/sRIO interrupt
+	uint64_t intr                         : 2;  /**< PCIe interrupt
                                                          These bits are observed in CIU_INTX_SUM0<33:32>
                                                          where X=32-33 */
 #else
@@ -4638,31 +9879,52 @@ union cvmx_ciu_pci_inta
 	struct cvmx_ciu_pci_inta_s            cn56xxp1;
 	struct cvmx_ciu_pci_inta_s            cn58xx;
 	struct cvmx_ciu_pci_inta_s            cn58xxp1;
+	struct cvmx_ciu_pci_inta_s            cn61xx;
 	struct cvmx_ciu_pci_inta_s            cn63xx;
 	struct cvmx_ciu_pci_inta_s            cn63xxp1;
+	struct cvmx_ciu_pci_inta_s            cn66xx;
+	struct cvmx_ciu_pci_inta_s            cn68xx;
+	struct cvmx_ciu_pci_inta_s            cn68xxp1;
+	struct cvmx_ciu_pci_inta_s            cnf71xx;
 };
 typedef union cvmx_ciu_pci_inta cvmx_ciu_pci_inta_t;
 
 /**
+ * cvmx_ciu_pp_bist_stat
+ */
+union cvmx_ciu_pp_bist_stat {
+	uint64_t u64;
+	struct cvmx_ciu_pp_bist_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t pp_bist                      : 32; /**< Physical PP BIST status */
+#else
+	uint64_t pp_bist                      : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu_pp_bist_stat_s        cn68xx;
+	struct cvmx_ciu_pp_bist_stat_s        cn68xxp1;
+};
+typedef union cvmx_ciu_pp_bist_stat cvmx_ciu_pp_bist_stat_t;
+
+/**
  * cvmx_ciu_pp_dbg
  */
-union cvmx_ciu_pp_dbg
-{
+union cvmx_ciu_pp_dbg {
 	uint64_t u64;
-	struct cvmx_ciu_pp_dbg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_16_63               : 48;
-	uint64_t ppdbg                        : 16; /**< Debug[DM] value for each PP
+	struct cvmx_ciu_pp_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t ppdbg                        : 32; /**< Debug[DM] value for each PP
                                                          whether the PP's are in debug mode or not */
 #else
-	uint64_t ppdbg                        : 16;
-	uint64_t reserved_16_63               : 48;
+	uint64_t ppdbg                        : 32;
+	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
-	struct cvmx_ciu_pp_dbg_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_pp_dbg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t ppdbg                        : 1;  /**< Debug[DM] value for each PP
                                                          whether the PP's are in debug mode or not */
@@ -4671,9 +9933,8 @@ union cvmx_ciu_pp_dbg
 	uint64_t reserved_1_63                : 63;
 #endif
 	} cn30xx;
-	struct cvmx_ciu_pp_dbg_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_pp_dbg_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t ppdbg                        : 2;  /**< Debug[DM] value for each PP
                                                          whether the PP's are in debug mode or not */
@@ -4682,12 +9943,20 @@ union cvmx_ciu_pp_dbg
 	uint64_t reserved_2_63                : 62;
 #endif
 	} cn31xx;
-	struct cvmx_ciu_pp_dbg_s              cn38xx;
-	struct cvmx_ciu_pp_dbg_s              cn38xxp2;
+	struct cvmx_ciu_pp_dbg_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t ppdbg                        : 16; /**< Debug[DM] value for each PP
+                                                         whether the PP's are in debug mode or not */
+#else
+	uint64_t ppdbg                        : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn38xx;
+	struct cvmx_ciu_pp_dbg_cn38xx         cn38xxp2;
 	struct cvmx_ciu_pp_dbg_cn31xx         cn50xx;
-	struct cvmx_ciu_pp_dbg_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_pp_dbg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t ppdbg                        : 4;  /**< Debug[DM] value for each PP
                                                          whether the PP's are in debug mode or not */
@@ -4697,9 +9966,8 @@ union cvmx_ciu_pp_dbg
 #endif
 	} cn52xx;
 	struct cvmx_ciu_pp_dbg_cn52xx         cn52xxp1;
-	struct cvmx_ciu_pp_dbg_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_pp_dbg_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t ppdbg                        : 12; /**< Debug[DM] value for each PP
                                                          whether the PP's are in debug mode or not */
@@ -4709,11 +9977,11 @@ union cvmx_ciu_pp_dbg
 #endif
 	} cn56xx;
 	struct cvmx_ciu_pp_dbg_cn56xx         cn56xxp1;
-	struct cvmx_ciu_pp_dbg_s              cn58xx;
-	struct cvmx_ciu_pp_dbg_s              cn58xxp1;
-	struct cvmx_ciu_pp_dbg_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_pp_dbg_cn38xx         cn58xx;
+	struct cvmx_ciu_pp_dbg_cn38xx         cn58xxp1;
+	struct cvmx_ciu_pp_dbg_cn52xx         cn61xx;
+	struct cvmx_ciu_pp_dbg_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t ppdbg                        : 6;  /**< Debug[DM] value for each PP
                                                          whether the PP's are in debug mode or not */
@@ -4723,6 +9991,19 @@ union cvmx_ciu_pp_dbg
 #endif
 	} cn63xx;
 	struct cvmx_ciu_pp_dbg_cn63xx         cn63xxp1;
+	struct cvmx_ciu_pp_dbg_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t ppdbg                        : 10; /**< Debug[DM] value for each PP
+                                                         whether the PP's are in debug mode or not */
+#else
+	uint64_t ppdbg                        : 10;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_pp_dbg_s              cn68xx;
+	struct cvmx_ciu_pp_dbg_s              cn68xxp1;
+	struct cvmx_ciu_pp_dbg_cn52xx         cnf71xx;
 };
 typedef union cvmx_ciu_pp_dbg cvmx_ciu_pp_dbg_t;
 
@@ -4736,12 +10017,10 @@ typedef union cvmx_ciu_pp_dbg cvmx_ciu_pp_dbg_t;
  *
  * Reads to this register will return the associated CIU_WDOG register.
  */
-union cvmx_ciu_pp_pokex
-{
+union cvmx_ciu_pp_pokex {
 	uint64_t u64;
-	struct cvmx_ciu_pp_pokex_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_pp_pokex_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t poke                         : 64; /**< Reserved */
 #else
 	uint64_t poke                         : 64;
@@ -4758,8 +10037,13 @@ union cvmx_ciu_pp_pokex
 	struct cvmx_ciu_pp_pokex_s            cn56xxp1;
 	struct cvmx_ciu_pp_pokex_s            cn58xx;
 	struct cvmx_ciu_pp_pokex_s            cn58xxp1;
+	struct cvmx_ciu_pp_pokex_s            cn61xx;
 	struct cvmx_ciu_pp_pokex_s            cn63xx;
 	struct cvmx_ciu_pp_pokex_s            cn63xxp1;
+	struct cvmx_ciu_pp_pokex_s            cn66xx;
+	struct cvmx_ciu_pp_pokex_s            cn68xx;
+	struct cvmx_ciu_pp_pokex_s            cn68xxp1;
+	struct cvmx_ciu_pp_pokex_s            cnf71xx;
 };
 typedef union cvmx_ciu_pp_pokex cvmx_ciu_pp_pokex_t;
 
@@ -4767,27 +10051,24 @@ typedef union cvmx_ciu_pp_pokex cvmx_ciu_pp_pokex_t;
  * cvmx_ciu_pp_rst
  *
  * Contains the reset control for each PP.  Value of '1' will hold a PP in reset, '0' will release.
- * Resets to 0xffff when PCI boot is enabled, 0xfffe otherwise.
+ * Resets to 0xf when PCI boot is enabled, 0xe otherwise.
  */
-union cvmx_ciu_pp_rst
-{
+union cvmx_ciu_pp_rst {
 	uint64_t u64;
-	struct cvmx_ciu_pp_rst_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_16_63               : 48;
-	uint64_t rst                          : 15; /**< PP Rst for PP's 5-1 */
+	struct cvmx_ciu_pp_rst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t rst                          : 31; /**< PP Rst for PP's 3-1 */
 	uint64_t rst0                         : 1;  /**< PP Rst for PP0
                                                          depends on standalone mode */
 #else
 	uint64_t rst0                         : 1;
-	uint64_t rst                          : 15;
-	uint64_t reserved_16_63               : 48;
+	uint64_t rst                          : 31;
+	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
-	struct cvmx_ciu_pp_rst_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_pp_rst_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t rst0                         : 1;  /**< PP Rst for PP0
                                                          depends on standalone mode */
@@ -4796,9 +10077,8 @@ union cvmx_ciu_pp_rst
 	uint64_t reserved_1_63                : 63;
 #endif
 	} cn30xx;
-	struct cvmx_ciu_pp_rst_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_pp_rst_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t rst                          : 1;  /**< PP Rst for PP1 */
 	uint64_t rst0                         : 1;  /**< PP Rst for PP0
@@ -4809,12 +10089,22 @@ union cvmx_ciu_pp_rst
 	uint64_t reserved_2_63                : 62;
 #endif
 	} cn31xx;
-	struct cvmx_ciu_pp_rst_s              cn38xx;
-	struct cvmx_ciu_pp_rst_s              cn38xxp2;
+	struct cvmx_ciu_pp_rst_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t rst                          : 15; /**< PP Rst for PP's 15-1 */
+	uint64_t rst0                         : 1;  /**< PP Rst for PP0
+                                                         depends on standalone mode */
+#else
+	uint64_t rst0                         : 1;
+	uint64_t rst                          : 15;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn38xx;
+	struct cvmx_ciu_pp_rst_cn38xx         cn38xxp2;
 	struct cvmx_ciu_pp_rst_cn31xx         cn50xx;
-	struct cvmx_ciu_pp_rst_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_pp_rst_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t rst                          : 3;  /**< PP Rst for PP's 11-1 */
 	uint64_t rst0                         : 1;  /**< PP Rst for PP0
@@ -4826,9 +10116,8 @@ union cvmx_ciu_pp_rst
 #endif
 	} cn52xx;
 	struct cvmx_ciu_pp_rst_cn52xx         cn52xxp1;
-	struct cvmx_ciu_pp_rst_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_pp_rst_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t rst                          : 11; /**< PP Rst for PP's 11-1 */
 	uint64_t rst0                         : 1;  /**< PP Rst for PP0
@@ -4840,11 +10129,11 @@ union cvmx_ciu_pp_rst
 #endif
 	} cn56xx;
 	struct cvmx_ciu_pp_rst_cn56xx         cn56xxp1;
-	struct cvmx_ciu_pp_rst_s              cn58xx;
-	struct cvmx_ciu_pp_rst_s              cn58xxp1;
-	struct cvmx_ciu_pp_rst_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_pp_rst_cn38xx         cn58xx;
+	struct cvmx_ciu_pp_rst_cn38xx         cn58xxp1;
+	struct cvmx_ciu_pp_rst_cn52xx         cn61xx;
+	struct cvmx_ciu_pp_rst_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t rst                          : 5;  /**< PP Rst for PP's 5-1 */
 	uint64_t rst0                         : 1;  /**< PP Rst for PP0
@@ -4856,6 +10145,21 @@ union cvmx_ciu_pp_rst
 #endif
 	} cn63xx;
 	struct cvmx_ciu_pp_rst_cn63xx         cn63xxp1;
+	struct cvmx_ciu_pp_rst_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t rst                          : 9;  /**< PP Rst for PP's 9-1 */
+	uint64_t rst0                         : 1;  /**< PP Rst for PP0
+                                                         depends on standalone mode */
+#else
+	uint64_t rst0                         : 1;
+	uint64_t rst                          : 9;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_pp_rst_s              cn68xx;
+	struct cvmx_ciu_pp_rst_s              cn68xxp1;
+	struct cvmx_ciu_pp_rst_cn52xx         cnf71xx;
 };
 typedef union cvmx_ciu_pp_rst cvmx_ciu_pp_rst_t;
 
@@ -4866,12 +10170,10 @@ typedef union cvmx_ciu_pp_rst cvmx_ciu_pp_rst_t;
  * This register is only reset by cold reset.
  *
  */
-union cvmx_ciu_qlm0
-{
+union cvmx_ciu_qlm0 {
 	uint64_t u64;
-	struct cvmx_ciu_qlm0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_qlm0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t g2bypass                     : 1;  /**< QLM0 PCIE Gen2 tx bypass enable */
 	uint64_t reserved_53_62               : 10;
 	uint64_t g2deemph                     : 5;  /**< QLM0 PCIE Gen2 tx bypass de-emphasis value */
@@ -4901,10 +10203,10 @@ union cvmx_ciu_qlm0
 	uint64_t g2bypass                     : 1;
 #endif
 	} s;
+	struct cvmx_ciu_qlm0_s                cn61xx;
 	struct cvmx_ciu_qlm0_s                cn63xx;
-	struct cvmx_ciu_qlm0_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_qlm0_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t txbypass                     : 1;  /**< QLM0 transmitter bypass enable */
 	uint64_t reserved_20_30               : 11;
@@ -4924,6 +10226,30 @@ union cvmx_ciu_qlm0
 	uint64_t reserved_32_63               : 32;
 #endif
 	} cn63xxp1;
+	struct cvmx_ciu_qlm0_s                cn66xx;
+	struct cvmx_ciu_qlm0_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t txbypass                     : 1;  /**< QLMx transmitter bypass enable */
+	uint64_t reserved_21_30               : 10;
+	uint64_t txdeemph                     : 5;  /**< QLMx transmitter bypass de-emphasis value */
+	uint64_t reserved_13_15               : 3;
+	uint64_t txmargin                     : 5;  /**< QLMx transmitter bypass margin (amplitude) value */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t lane_en                      : 4;  /**< QLMx lane enable mask */
+#else
+	uint64_t lane_en                      : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t txmargin                     : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t txdeemph                     : 5;
+	uint64_t reserved_21_30               : 10;
+	uint64_t txbypass                     : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn68xx;
+	struct cvmx_ciu_qlm0_cn68xx           cn68xxp1;
+	struct cvmx_ciu_qlm0_s                cnf71xx;
 };
 typedef union cvmx_ciu_qlm0 cvmx_ciu_qlm0_t;
 
@@ -4934,12 +10260,10 @@ typedef union cvmx_ciu_qlm0 cvmx_ciu_qlm0_t;
  * This register is only reset by cold reset.
  *
  */
-union cvmx_ciu_qlm1
-{
+union cvmx_ciu_qlm1 {
 	uint64_t u64;
-	struct cvmx_ciu_qlm1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_qlm1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t g2bypass                     : 1;  /**< QLM1 PCIE Gen2 tx bypass enable */
 	uint64_t reserved_53_62               : 10;
 	uint64_t g2deemph                     : 5;  /**< QLM1 PCIE Gen2 tx bypass de-emphasis value */
@@ -4969,10 +10293,10 @@ union cvmx_ciu_qlm1
 	uint64_t g2bypass                     : 1;
 #endif
 	} s;
+	struct cvmx_ciu_qlm1_s                cn61xx;
 	struct cvmx_ciu_qlm1_s                cn63xx;
-	struct cvmx_ciu_qlm1_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_qlm1_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t txbypass                     : 1;  /**< QLM1 transmitter bypass enable */
 	uint64_t reserved_20_30               : 11;
@@ -4992,6 +10316,10 @@ union cvmx_ciu_qlm1
 	uint64_t reserved_32_63               : 32;
 #endif
 	} cn63xxp1;
+	struct cvmx_ciu_qlm1_s                cn66xx;
+	struct cvmx_ciu_qlm1_s                cn68xx;
+	struct cvmx_ciu_qlm1_s                cn68xxp1;
+	struct cvmx_ciu_qlm1_s                cnf71xx;
 };
 typedef union cvmx_ciu_qlm1 cvmx_ciu_qlm1_t;
 
@@ -5002,12 +10330,41 @@ typedef union cvmx_ciu_qlm1 cvmx_ciu_qlm1_t;
  * This register is only reset by cold reset.
  *
  */
-union cvmx_ciu_qlm2
-{
+union cvmx_ciu_qlm2 {
 	uint64_t u64;
-	struct cvmx_ciu_qlm2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_qlm2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t g2bypass                     : 1;  /**< QLMx PCIE Gen2 tx bypass enable */
+	uint64_t reserved_53_62               : 10;
+	uint64_t g2deemph                     : 5;  /**< QLMx PCIE Gen2 tx bypass de-emphasis value */
+	uint64_t reserved_45_47               : 3;
+	uint64_t g2margin                     : 5;  /**< QLMx PCIE Gen2 tx bypass margin (amplitude) value */
+	uint64_t reserved_32_39               : 8;
+	uint64_t txbypass                     : 1;  /**< QLM2 transmitter bypass enable */
+	uint64_t reserved_21_30               : 10;
+	uint64_t txdeemph                     : 5;  /**< QLM2 transmitter bypass de-emphasis value */
+	uint64_t reserved_13_15               : 3;
+	uint64_t txmargin                     : 5;  /**< QLM2 transmitter bypass margin (amplitude) value */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t lane_en                      : 4;  /**< QLM2 lane enable mask */
+#else
+	uint64_t lane_en                      : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t txmargin                     : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t txdeemph                     : 5;
+	uint64_t reserved_21_30               : 10;
+	uint64_t txbypass                     : 1;
+	uint64_t reserved_32_39               : 8;
+	uint64_t g2margin                     : 5;
+	uint64_t reserved_45_47               : 3;
+	uint64_t g2deemph                     : 5;
+	uint64_t reserved_53_62               : 10;
+	uint64_t g2bypass                     : 1;
+#endif
+	} s;
+	struct cvmx_ciu_qlm2_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t txbypass                     : 1;  /**< QLM2 transmitter bypass enable */
 	uint64_t reserved_21_30               : 10;
@@ -5026,11 +10383,10 @@ union cvmx_ciu_qlm2
 	uint64_t txbypass                     : 1;
 	uint64_t reserved_32_63               : 32;
 #endif
-	} s;
-	struct cvmx_ciu_qlm2_s                cn63xx;
-	struct cvmx_ciu_qlm2_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	} cn61xx;
+	struct cvmx_ciu_qlm2_cn61xx           cn63xx;
+	struct cvmx_ciu_qlm2_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t txbypass                     : 1;  /**< QLM2 transmitter bypass enable */
 	uint64_t reserved_20_30               : 11;
@@ -5050,18 +10406,110 @@ union cvmx_ciu_qlm2
 	uint64_t reserved_32_63               : 32;
 #endif
 	} cn63xxp1;
+	struct cvmx_ciu_qlm2_cn61xx           cn66xx;
+	struct cvmx_ciu_qlm2_s                cn68xx;
+	struct cvmx_ciu_qlm2_s                cn68xxp1;
+	struct cvmx_ciu_qlm2_cn61xx           cnf71xx;
 };
 typedef union cvmx_ciu_qlm2 cvmx_ciu_qlm2_t;
 
 /**
+ * cvmx_ciu_qlm3
+ *
+ * Notes:
+ * This register is only reset by cold reset.
+ *
+ */
+union cvmx_ciu_qlm3 {
+	uint64_t u64;
+	struct cvmx_ciu_qlm3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t g2bypass                     : 1;  /**< QLMx PCIE Gen2 tx bypass enable */
+	uint64_t reserved_53_62               : 10;
+	uint64_t g2deemph                     : 5;  /**< QLMx PCIE Gen2 tx bypass de-emphasis value */
+	uint64_t reserved_45_47               : 3;
+	uint64_t g2margin                     : 5;  /**< QLMx PCIE Gen2 tx bypass margin (amplitude) value */
+	uint64_t reserved_32_39               : 8;
+	uint64_t txbypass                     : 1;  /**< QLMx transmitter bypass enable */
+	uint64_t reserved_21_30               : 10;
+	uint64_t txdeemph                     : 5;  /**< QLMx transmitter bypass de-emphasis value */
+	uint64_t reserved_13_15               : 3;
+	uint64_t txmargin                     : 5;  /**< QLMx transmitter bypass margin (amplitude) value */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t lane_en                      : 4;  /**< QLMx lane enable mask */
+#else
+	uint64_t lane_en                      : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t txmargin                     : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t txdeemph                     : 5;
+	uint64_t reserved_21_30               : 10;
+	uint64_t txbypass                     : 1;
+	uint64_t reserved_32_39               : 8;
+	uint64_t g2margin                     : 5;
+	uint64_t reserved_45_47               : 3;
+	uint64_t g2deemph                     : 5;
+	uint64_t reserved_53_62               : 10;
+	uint64_t g2bypass                     : 1;
+#endif
+	} s;
+	struct cvmx_ciu_qlm3_s                cn68xx;
+	struct cvmx_ciu_qlm3_s                cn68xxp1;
+};
+typedef union cvmx_ciu_qlm3 cvmx_ciu_qlm3_t;
+
+/**
+ * cvmx_ciu_qlm4
+ *
+ * Notes:
+ * This register is only reset by cold reset.
+ *
+ */
+union cvmx_ciu_qlm4 {
+	uint64_t u64;
+	struct cvmx_ciu_qlm4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t g2bypass                     : 1;  /**< QLMx PCIE Gen2 tx bypass enable */
+	uint64_t reserved_53_62               : 10;
+	uint64_t g2deemph                     : 5;  /**< QLMx PCIE Gen2 tx bypass de-emphasis value */
+	uint64_t reserved_45_47               : 3;
+	uint64_t g2margin                     : 5;  /**< QLMx PCIE Gen2 tx bypass margin (amplitude) value */
+	uint64_t reserved_32_39               : 8;
+	uint64_t txbypass                     : 1;  /**< QLMx transmitter bypass enable */
+	uint64_t reserved_21_30               : 10;
+	uint64_t txdeemph                     : 5;  /**< QLMx transmitter bypass de-emphasis value */
+	uint64_t reserved_13_15               : 3;
+	uint64_t txmargin                     : 5;  /**< QLMx transmitter bypass margin (amplitude) value */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t lane_en                      : 4;  /**< QLMx lane enable mask */
+#else
+	uint64_t lane_en                      : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t txmargin                     : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t txdeemph                     : 5;
+	uint64_t reserved_21_30               : 10;
+	uint64_t txbypass                     : 1;
+	uint64_t reserved_32_39               : 8;
+	uint64_t g2margin                     : 5;
+	uint64_t reserved_45_47               : 3;
+	uint64_t g2deemph                     : 5;
+	uint64_t reserved_53_62               : 10;
+	uint64_t g2bypass                     : 1;
+#endif
+	} s;
+	struct cvmx_ciu_qlm4_s                cn68xx;
+	struct cvmx_ciu_qlm4_s                cn68xxp1;
+};
+typedef union cvmx_ciu_qlm4 cvmx_ciu_qlm4_t;
+
+/**
  * cvmx_ciu_qlm_dcok
  */
-union cvmx_ciu_qlm_dcok
-{
+union cvmx_ciu_qlm_dcok {
 	uint64_t u64;
-	struct cvmx_ciu_qlm_dcok_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_qlm_dcok_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t qlm_dcok                     : 4;  /**< Re-assert dcok for each QLM. The value in this
                                                          field is "anded" with the pll_dcok pin and then
@@ -5071,9 +10519,8 @@ union cvmx_ciu_qlm_dcok
 	uint64_t reserved_4_63                : 60;
 #endif
 	} s;
-	struct cvmx_ciu_qlm_dcok_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_qlm_dcok_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t qlm_dcok                     : 2;  /**< Re-assert dcok for each QLM. The value in this
                                                          field is "anded" with the pll_dcok pin and then
@@ -5092,32 +10539,36 @@ typedef union cvmx_ciu_qlm_dcok cvmx_ciu_qlm_dcok_t;
 /**
  * cvmx_ciu_qlm_jtgc
  */
-union cvmx_ciu_qlm_jtgc
-{
+union cvmx_ciu_qlm_jtgc {
 	uint64_t u64;
-	struct cvmx_ciu_qlm_jtgc_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_11_63               : 53;
+	struct cvmx_ciu_qlm_jtgc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_17_63               : 47;
+	uint64_t bypass_ext                   : 1;  /**< BYPASS Field extension to select QLM 4
+                                                         Selects which QLM JTAG shift chains are bypassed
+                                                         by the QLM JTAG data register (CIU_QLM_JTGD) (one
+                                                         bit per QLM) */
+	uint64_t reserved_11_15               : 5;
 	uint64_t clk_div                      : 3;  /**< Clock divider for QLM JTAG operations.  eclk is
                                                          divided by 2^(CLK_DIV + 2) */
-	uint64_t reserved_6_7                 : 2;
-	uint64_t mux_sel                      : 2;  /**< Selects which QLM JTAG shift out is shifted into
+	uint64_t reserved_7_7                 : 1;
+	uint64_t mux_sel                      : 3;  /**< Selects which QLM JTAG shift out is shifted into
                                                          the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */
 	uint64_t bypass                       : 4;  /**< Selects which QLM JTAG shift chains are bypassed
                                                          by the QLM JTAG data register (CIU_QLM_JTGD) (one
                                                          bit per QLM) */
 #else
 	uint64_t bypass                       : 4;
-	uint64_t mux_sel                      : 2;
-	uint64_t reserved_6_7                 : 2;
+	uint64_t mux_sel                      : 3;
+	uint64_t reserved_7_7                 : 1;
 	uint64_t clk_div                      : 3;
-	uint64_t reserved_11_63               : 53;
+	uint64_t reserved_11_15               : 5;
+	uint64_t bypass_ext                   : 1;
+	uint64_t reserved_17_63               : 47;
 #endif
 	} s;
-	struct cvmx_ciu_qlm_jtgc_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_qlm_jtgc_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t clk_div                      : 3;  /**< Clock divider for QLM JTAG operations.  eclk is
                                                          divided by 2^(CLK_DIV + 2) */
@@ -5138,11 +10589,28 @@ union cvmx_ciu_qlm_jtgc
 #endif
 	} cn52xx;
 	struct cvmx_ciu_qlm_jtgc_cn52xx       cn52xxp1;
-	struct cvmx_ciu_qlm_jtgc_s            cn56xx;
-	struct cvmx_ciu_qlm_jtgc_s            cn56xxp1;
-	struct cvmx_ciu_qlm_jtgc_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_qlm_jtgc_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_11_63               : 53;
+	uint64_t clk_div                      : 3;  /**< Clock divider for QLM JTAG operations.  eclk is
+                                                         divided by 2^(CLK_DIV + 2) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t mux_sel                      : 2;  /**< Selects which QLM JTAG shift out is shifted into
+                                                         the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */
+	uint64_t bypass                       : 4;  /**< Selects which QLM JTAG shift chains are bypassed
+                                                         by the QLM JTAG data register (CIU_QLM_JTGD) (one
+                                                         bit per QLM) */
+#else
+	uint64_t bypass                       : 4;
+	uint64_t mux_sel                      : 2;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t clk_div                      : 3;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_qlm_jtgc_cn56xx       cn56xxp1;
+	struct cvmx_ciu_qlm_jtgc_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t clk_div                      : 3;  /**< Clock divider for QLM JTAG operations.  eclk is
                                                          divided by 2^(CLK_DIV + 2) */
@@ -5161,28 +10629,31 @@ union cvmx_ciu_qlm_jtgc
 	uint64_t clk_div                      : 3;
 	uint64_t reserved_11_63               : 53;
 #endif
-	} cn63xx;
-	struct cvmx_ciu_qlm_jtgc_cn63xx       cn63xxp1;
+	} cn61xx;
+	struct cvmx_ciu_qlm_jtgc_cn61xx       cn63xx;
+	struct cvmx_ciu_qlm_jtgc_cn61xx       cn63xxp1;
+	struct cvmx_ciu_qlm_jtgc_cn61xx       cn66xx;
+	struct cvmx_ciu_qlm_jtgc_s            cn68xx;
+	struct cvmx_ciu_qlm_jtgc_s            cn68xxp1;
+	struct cvmx_ciu_qlm_jtgc_cn61xx       cnf71xx;
 };
 typedef union cvmx_ciu_qlm_jtgc cvmx_ciu_qlm_jtgc_t;
 
 /**
  * cvmx_ciu_qlm_jtgd
  */
-union cvmx_ciu_qlm_jtgd
-{
+union cvmx_ciu_qlm_jtgd {
 	uint64_t u64;
-	struct cvmx_ciu_qlm_jtgd_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_qlm_jtgd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t capture                      : 1;  /**< Perform JTAG capture operation (self-clearing when
                                                          op completes) */
 	uint64_t shift                        : 1;  /**< Perform JTAG shift operation (self-clearing when
                                                          op completes) */
 	uint64_t update                       : 1;  /**< Perform JTAG update operation (self-clearing when
                                                          op completes) */
-	uint64_t reserved_44_60               : 17;
-	uint64_t select                       : 4;  /**< Selects which QLM JTAG shift chains the JTAG
+	uint64_t reserved_45_60               : 16;
+	uint64_t select                       : 5;  /**< Selects which QLM JTAG shift chains the JTAG
                                                          operations are performed on */
 	uint64_t reserved_37_39               : 3;
 	uint64_t shft_cnt                     : 5;  /**< QLM JTAG shift count (encoded in -1 notation) */
@@ -5191,16 +10662,15 @@ union cvmx_ciu_qlm_jtgd
 	uint64_t shft_reg                     : 32;
 	uint64_t shft_cnt                     : 5;
 	uint64_t reserved_37_39               : 3;
-	uint64_t select                       : 4;
-	uint64_t reserved_44_60               : 17;
+	uint64_t select                       : 5;
+	uint64_t reserved_45_60               : 16;
 	uint64_t update                       : 1;
 	uint64_t shift                        : 1;
 	uint64_t capture                      : 1;
 #endif
 	} s;
-	struct cvmx_ciu_qlm_jtgd_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_qlm_jtgd_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t capture                      : 1;  /**< Perform JTAG capture operation (self-clearing when
                                                          op completes) */
 	uint64_t shift                        : 1;  /**< Perform JTAG shift operation (self-clearing when
@@ -5225,10 +10695,33 @@ union cvmx_ciu_qlm_jtgd
 #endif
 	} cn52xx;
 	struct cvmx_ciu_qlm_jtgd_cn52xx       cn52xxp1;
-	struct cvmx_ciu_qlm_jtgd_s            cn56xx;
-	struct cvmx_ciu_qlm_jtgd_cn56xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_qlm_jtgd_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t capture                      : 1;  /**< Perform JTAG capture operation (self-clearing when
+                                                         op completes) */
+	uint64_t shift                        : 1;  /**< Perform JTAG shift operation (self-clearing when
+                                                         op completes) */
+	uint64_t update                       : 1;  /**< Perform JTAG update operation (self-clearing when
+                                                         op completes) */
+	uint64_t reserved_44_60               : 17;
+	uint64_t select                       : 4;  /**< Selects which QLM JTAG shift chains the JTAG
+                                                         operations are performed on */
+	uint64_t reserved_37_39               : 3;
+	uint64_t shft_cnt                     : 5;  /**< QLM JTAG shift count (encoded in -1 notation) */
+	uint64_t shft_reg                     : 32; /**< QLM JTAG shift register */
+#else
+	uint64_t shft_reg                     : 32;
+	uint64_t shft_cnt                     : 5;
+	uint64_t reserved_37_39               : 3;
+	uint64_t select                       : 4;
+	uint64_t reserved_44_60               : 17;
+	uint64_t update                       : 1;
+	uint64_t shift                        : 1;
+	uint64_t capture                      : 1;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_qlm_jtgd_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t capture                      : 1;  /**< Perform JTAG capture operation (self-clearing when
                                                          op completes) */
 	uint64_t shift                        : 1;  /**< Perform JTAG shift operation (self-clearing when
@@ -5247,9 +10740,8 @@ union cvmx_ciu_qlm_jtgd
 	uint64_t capture                      : 1;
 #endif
 	} cn56xxp1;
-	struct cvmx_ciu_qlm_jtgd_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_qlm_jtgd_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t capture                      : 1;  /**< Perform JTAG capture operation (self-clearing when
                                                          op completes) */
 	uint64_t shift                        : 1;  /**< Perform JTAG shift operation (self-clearing when
@@ -5272,20 +10764,23 @@ union cvmx_ciu_qlm_jtgd
 	uint64_t shift                        : 1;
 	uint64_t capture                      : 1;
 #endif
-	} cn63xx;
-	struct cvmx_ciu_qlm_jtgd_cn63xx       cn63xxp1;
+	} cn61xx;
+	struct cvmx_ciu_qlm_jtgd_cn61xx       cn63xx;
+	struct cvmx_ciu_qlm_jtgd_cn61xx       cn63xxp1;
+	struct cvmx_ciu_qlm_jtgd_cn61xx       cn66xx;
+	struct cvmx_ciu_qlm_jtgd_s            cn68xx;
+	struct cvmx_ciu_qlm_jtgd_s            cn68xxp1;
+	struct cvmx_ciu_qlm_jtgd_cn61xx       cnf71xx;
 };
 typedef union cvmx_ciu_qlm_jtgd cvmx_ciu_qlm_jtgd_t;
 
 /**
  * cvmx_ciu_soft_bist
  */
-union cvmx_ciu_soft_bist
-{
+union cvmx_ciu_soft_bist {
 	uint64_t u64;
-	struct cvmx_ciu_soft_bist_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_soft_bist_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t soft_bist                    : 1;  /**< Reserved */
 #else
@@ -5304,25 +10799,28 @@ union cvmx_ciu_soft_bist
 	struct cvmx_ciu_soft_bist_s           cn56xxp1;
 	struct cvmx_ciu_soft_bist_s           cn58xx;
 	struct cvmx_ciu_soft_bist_s           cn58xxp1;
+	struct cvmx_ciu_soft_bist_s           cn61xx;
 	struct cvmx_ciu_soft_bist_s           cn63xx;
 	struct cvmx_ciu_soft_bist_s           cn63xxp1;
+	struct cvmx_ciu_soft_bist_s           cn66xx;
+	struct cvmx_ciu_soft_bist_s           cn68xx;
+	struct cvmx_ciu_soft_bist_s           cn68xxp1;
+	struct cvmx_ciu_soft_bist_s           cnf71xx;
 };
 typedef union cvmx_ciu_soft_bist cvmx_ciu_soft_bist_t;
 
 /**
  * cvmx_ciu_soft_prst
  */
-union cvmx_ciu_soft_prst
-{
+union cvmx_ciu_soft_prst {
 	uint64_t u64;
-	struct cvmx_ciu_soft_prst_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_soft_prst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t host64                       : 1;  /**< PCX Host Mode Device Capability (0=32b/1=64b) */
 	uint64_t npi                          : 1;  /**< When PCI soft reset is asserted, also reset the
                                                          NPI and PNI logic */
-	uint64_t soft_prst                    : 1;  /**< Resets the PCIe/sRIO logic in all modes, not just
+	uint64_t soft_prst                    : 1;  /**< Resets the PCIe logic in all modes, not just
                                                          RC mode. The reset value is based on the
                                                          corresponding MIO_RST_CTL[PRTMODE] CSR field:
                                                           If PRTMODE == 0, then SOFT_PRST resets to 0
@@ -5342,9 +10840,8 @@ union cvmx_ciu_soft_prst
 	struct cvmx_ciu_soft_prst_s           cn38xx;
 	struct cvmx_ciu_soft_prst_s           cn38xxp2;
 	struct cvmx_ciu_soft_prst_s           cn50xx;
-	struct cvmx_ciu_soft_prst_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_soft_prst_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t soft_prst                    : 1;  /**< Reset the PCI bus.  Only works when Octane is
                                                          configured as a HOST. When OCTEON is a PCI host
@@ -5360,29 +10857,31 @@ union cvmx_ciu_soft_prst
 	struct cvmx_ciu_soft_prst_cn52xx      cn56xxp1;
 	struct cvmx_ciu_soft_prst_s           cn58xx;
 	struct cvmx_ciu_soft_prst_s           cn58xxp1;
+	struct cvmx_ciu_soft_prst_cn52xx      cn61xx;
 	struct cvmx_ciu_soft_prst_cn52xx      cn63xx;
 	struct cvmx_ciu_soft_prst_cn52xx      cn63xxp1;
+	struct cvmx_ciu_soft_prst_cn52xx      cn66xx;
+	struct cvmx_ciu_soft_prst_cn52xx      cn68xx;
+	struct cvmx_ciu_soft_prst_cn52xx      cn68xxp1;
+	struct cvmx_ciu_soft_prst_cn52xx      cnf71xx;
 };
 typedef union cvmx_ciu_soft_prst cvmx_ciu_soft_prst_t;
 
 /**
  * cvmx_ciu_soft_prst1
  */
-union cvmx_ciu_soft_prst1
-{
+union cvmx_ciu_soft_prst1 {
 	uint64_t u64;
-	struct cvmx_ciu_soft_prst1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_soft_prst1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
-	uint64_t soft_prst                    : 1;  /**< Resets the PCIe/sRIO logic in all modes, not just
+	uint64_t soft_prst                    : 1;  /**< Resets the PCIe logic in all modes, not just
                                                          RC mode. The reset value is based on the
                                                          corresponding MIO_RST_CTL[PRTMODE] CSR field:
                                                           If PRTMODE == 0, then SOFT_PRST resets to 0
                                                           If PRTMODE != 0, then SOFT_PRST resets to 1
-                                                         When OCTEON is configured to drive the PERST*_L
-                                                         chip pin (ie. MIO_RST_CTL1[RST_DRV] is set), this
-                                                         controls the PERST*_L chip pin. */
+                                                         In o61, this PRST initial value is always '1' as
+                                                         PEM1 always running on host mode. */
 #else
 	uint64_t soft_prst                    : 1;
 	uint64_t reserved_1_63                : 63;
@@ -5392,23 +10891,70 @@ union cvmx_ciu_soft_prst1
 	struct cvmx_ciu_soft_prst1_s          cn52xxp1;
 	struct cvmx_ciu_soft_prst1_s          cn56xx;
 	struct cvmx_ciu_soft_prst1_s          cn56xxp1;
+	struct cvmx_ciu_soft_prst1_s          cn61xx;
 	struct cvmx_ciu_soft_prst1_s          cn63xx;
 	struct cvmx_ciu_soft_prst1_s          cn63xxp1;
+	struct cvmx_ciu_soft_prst1_s          cn66xx;
+	struct cvmx_ciu_soft_prst1_s          cn68xx;
+	struct cvmx_ciu_soft_prst1_s          cn68xxp1;
+	struct cvmx_ciu_soft_prst1_s          cnf71xx;
 };
 typedef union cvmx_ciu_soft_prst1 cvmx_ciu_soft_prst1_t;
 
 /**
+ * cvmx_ciu_soft_prst2
+ */
+union cvmx_ciu_soft_prst2 {
+	uint64_t u64;
+	struct cvmx_ciu_soft_prst2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_1_63                : 63;
+	uint64_t soft_prst                    : 1;  /**< Resets the      sRIO logic in all modes, not just
+                                                         RC mode. The reset value is based on the
+                                                         corresponding MIO_RST_CNTL[PRTMODE] CSR field:
+                                                          If PRTMODE == 0, then SOFT_PRST resets to 0
+                                                          If PRTMODE != 0, then SOFT_PRST resets to 1 */
+#else
+	uint64_t soft_prst                    : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_ciu_soft_prst2_s          cn66xx;
+};
+typedef union cvmx_ciu_soft_prst2 cvmx_ciu_soft_prst2_t;
+
+/**
+ * cvmx_ciu_soft_prst3
+ */
+union cvmx_ciu_soft_prst3 {
+	uint64_t u64;
+	struct cvmx_ciu_soft_prst3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_1_63                : 63;
+	uint64_t soft_prst                    : 1;  /**< Resets the      sRIO logic in all modes, not just
+                                                         RC mode. The reset value is based on the
+                                                         corresponding MIO_RST_CNTL[PRTMODE] CSR field:
+                                                          If PRTMODE == 0, then SOFT_PRST resets to 0
+                                                          If PRTMODE != 0, then SOFT_PRST resets to 1 */
+#else
+	uint64_t soft_prst                    : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_ciu_soft_prst3_s          cn66xx;
+};
+typedef union cvmx_ciu_soft_prst3 cvmx_ciu_soft_prst3_t;
+
+/**
  * cvmx_ciu_soft_rst
  */
-union cvmx_ciu_soft_rst
-{
+union cvmx_ciu_soft_rst {
 	uint64_t u64;
-	struct cvmx_ciu_soft_rst_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_soft_rst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t soft_rst                     : 1;  /**< Resets Octeon
-                                                         When soft reseting Octeon from a remote PCIe/sRIO
+                                                         When soft reseting Octeon from a remote PCIe
                                                          host, always read CIU_SOFT_RST (and wait for
                                                          result) before writing SOFT_RST to '1'. */
 #else
@@ -5427,20 +10973,1991 @@ union cvmx_ciu_soft_rst
 	struct cvmx_ciu_soft_rst_s            cn56xxp1;
 	struct cvmx_ciu_soft_rst_s            cn58xx;
 	struct cvmx_ciu_soft_rst_s            cn58xxp1;
+	struct cvmx_ciu_soft_rst_s            cn61xx;
 	struct cvmx_ciu_soft_rst_s            cn63xx;
 	struct cvmx_ciu_soft_rst_s            cn63xxp1;
+	struct cvmx_ciu_soft_rst_s            cn66xx;
+	struct cvmx_ciu_soft_rst_s            cn68xx;
+	struct cvmx_ciu_soft_rst_s            cn68xxp1;
+	struct cvmx_ciu_soft_rst_s            cnf71xx;
 };
 typedef union cvmx_ciu_soft_rst cvmx_ciu_soft_rst_t;
 
 /**
+ * cvmx_ciu_sum1_io#_int
+ *
+ * Notes:
+ * SUM1 becomes per IPx in o65/6 and afterwards. Only Field <40> DPI_DMA will have
+ * different value per PP(IP) for  $CIU_SUM1_PPx_IPy, and <40> DPI_DMA will always
+ * be zero for  $CIU_SUM1_IOX_INT. All other fields ([63:41] and [39:0]) values  are idential for
+ * different PPs, same value as $CIU_INT_SUM1.
+ * Write to any IRQ's PTP fields will clear PTP for all IRQ's PTP field.
+ */
+union cvmx_ciu_sum1_iox_int {
+	uint64_t u64;
+	struct cvmx_ciu_sum1_iox_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< SRIO3 interrupt
+                                                         See SRIO3_INT_REG, SRIO3_INT2_REG */
+	uint64_t srio2                        : 1;  /**< SRIO2 interrupt
+                                                         See SRIO2_INT_REG, SRIO2_INT2_REG */
+	uint64_t reserved_57_59               : 3;
+	uint64_t dfm                          : 1;  /**< DFM Interrupt
+                                                         See DFM_FNT_STAT */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_51_51               : 1;
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt
+                                                         See SRIO0_INT_REG, SRIO0_INT2_REG */
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         TBD, See DPI DMA instruction completion */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt
+                                                         See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
+                                                         PCS1_INT*_REG, PCSX1_INT_REG */
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt
+                                                         See EMMC interrupt */
+	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt
+                                                         See MIX1_ISR */
+	uint64_t reserved_10_17               : 8;
+	uint64_t wdog                         : 10; /**< Per PP watchdog interrupts */
+#else
+	uint64_t wdog                         : 10;
+	uint64_t reserved_10_17               : 8;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu_sum1_iox_int_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         TBD, See DPI DMA instruction completion */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt
+                                                         See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
+                                                         PCS1_INT*_REG, PCSX1_INT_REG */
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt
+                                                         See EMMC interrupt */
+	uint64_t mii1                         : 1;  /**< RGMII/MIX Interface 1 Interrupt
+                                                         See MIX1_ISR */
+	uint64_t reserved_4_17                : 14;
+	uint64_t wdog                         : 4;  /**< Per PP watchdog interrupts */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_17                : 14;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_sum1_iox_int_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< SRIO3 interrupt
+                                                         See SRIO3_INT_REG, SRIO3_INT2_REG */
+	uint64_t srio2                        : 1;  /**< SRIO2 interrupt
+                                                         See SRIO2_INT_REG, SRIO2_INT2_REG */
+	uint64_t reserved_57_59               : 3;
+	uint64_t dfm                          : 1;  /**< DFM Interrupt
+                                                         See DFM_FNT_STAT */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_51_51               : 1;
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt
+                                                         See SRIO0_INT_REG, SRIO0_INT2_REG */
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_38_45               : 8;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt
+                                                         See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
+                                                         PCS1_INT*_REG, PCSX1_INT_REG */
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt
+                                                         See NDF_INT */
+	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt
+                                                         See MIX1_ISR */
+	uint64_t reserved_10_17               : 8;
+	uint64_t wdog                         : 10; /**< 10 watchdog interrupts */
+#else
+	uint64_t wdog                         : 10;
+	uint64_t reserved_10_17               : 8;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_45               : 8;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t rst                          : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_sum1_iox_int_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t reserved_41_46               : 6;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         TBD, See DPI DMA instruction completion */
+	uint64_t reserved_37_39               : 3;
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t reserved_32_32               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t reserved_28_28               : 1;
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt
+                                                         See EMMC interrupt */
+	uint64_t reserved_4_18                : 15;
+	uint64_t wdog                         : 4;  /**< Per PP watchdog interrupts */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_18                : 15;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_28_28               : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_32_32               : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_46               : 6;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cnf71xx;
+};
+typedef union cvmx_ciu_sum1_iox_int cvmx_ciu_sum1_iox_int_t;
+
+/**
+ * cvmx_ciu_sum1_pp#_ip2
+ *
+ * Notes:
+ * SUM1 becomes per IPx in o65/6 and afterwards. Only Field <40> DPI_DMA will have
+ * different value per PP(IP) for  $CIU_SUM1_PPx_IPy, and <40> DPI_DMA will always
+ * be zero for  $CIU_SUM1_IOX_INT. All other fields ([63:41] and [39:0]) values  are idential for
+ * different PPs, same value as $CIU_INT_SUM1.
+ * Write to any IRQ's PTP fields will clear PTP for all IRQ's PTP field.
+ */
+union cvmx_ciu_sum1_ppx_ip2 {
+	uint64_t u64;
+	struct cvmx_ciu_sum1_ppx_ip2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< SRIO3 interrupt
+                                                         See SRIO3_INT_REG, SRIO3_INT2_REG */
+	uint64_t srio2                        : 1;  /**< SRIO2 interrupt
+                                                         See SRIO2_INT_REG, SRIO2_INT2_REG */
+	uint64_t reserved_57_59               : 3;
+	uint64_t dfm                          : 1;  /**< DFM Interrupt
+                                                         See DFM_FNT_STAT */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_51_51               : 1;
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt
+                                                         See SRIO0_INT_REG, SRIO0_INT2_REG */
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         TBD, See DPI DMA instruction completion */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt
+                                                         See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
+                                                         PCS1_INT*_REG, PCSX1_INT_REG */
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt
+                                                         See EMMC interrupt */
+	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt
+                                                         See MIX1_ISR */
+	uint64_t reserved_10_17               : 8;
+	uint64_t wdog                         : 10; /**< Per PP watchdog interrupts */
+#else
+	uint64_t wdog                         : 10;
+	uint64_t reserved_10_17               : 8;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu_sum1_ppx_ip2_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         TBD, See DPI DMA instruction completion */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt
+                                                         See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
+                                                         PCS1_INT*_REG, PCSX1_INT_REG */
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt
+                                                         See EMMC interrupt */
+	uint64_t mii1                         : 1;  /**< RGMII/MIX Interface 1 Interrupt
+                                                         See MIX1_ISR */
+	uint64_t reserved_4_17                : 14;
+	uint64_t wdog                         : 4;  /**< Per PP watchdog interrupts */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_17                : 14;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_sum1_ppx_ip2_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< SRIO3 interrupt
+                                                         See SRIO3_INT_REG, SRIO3_INT2_REG */
+	uint64_t srio2                        : 1;  /**< SRIO2 interrupt
+                                                         See SRIO2_INT_REG, SRIO2_INT2_REG */
+	uint64_t reserved_57_59               : 3;
+	uint64_t dfm                          : 1;  /**< DFM Interrupt
+                                                         See DFM_FNT_STAT */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_51_51               : 1;
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt
+                                                         See SRIO0_INT_REG, SRIO0_INT2_REG */
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_38_45               : 8;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt
+                                                         See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
+                                                         PCS1_INT*_REG, PCSX1_INT_REG */
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt
+                                                         See NDF_INT */
+	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt
+                                                         See MIX1_ISR */
+	uint64_t reserved_10_17               : 8;
+	uint64_t wdog                         : 10; /**< 10 watchdog interrupts */
+#else
+	uint64_t wdog                         : 10;
+	uint64_t reserved_10_17               : 8;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_45               : 8;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t rst                          : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_sum1_ppx_ip2_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t reserved_41_46               : 6;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         TBD, See DPI DMA instruction completion */
+	uint64_t reserved_37_39               : 3;
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t reserved_32_32               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t reserved_28_28               : 1;
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt
+                                                         See EMMC interrupt */
+	uint64_t reserved_4_18                : 15;
+	uint64_t wdog                         : 4;  /**< Per PP watchdog interrupts */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_18                : 15;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_28_28               : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_32_32               : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_46               : 6;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cnf71xx;
+};
+typedef union cvmx_ciu_sum1_ppx_ip2 cvmx_ciu_sum1_ppx_ip2_t;
+
+/**
+ * cvmx_ciu_sum1_pp#_ip3
+ *
+ * Notes:
+ * SUM1 becomes per IPx in o65/6 and afterwards. Only Field <40> DPI_DMA will have
+ * different value per PP(IP) for  $CIU_SUM1_PPx_IPy, and <40> DPI_DMA will always
+ * be zero for  $CIU_SUM1_IOX_INT. All other fields ([63:41] and [39:0]) values  are idential for
+ * different PPs, same value as $CIU_INT_SUM1.
+ * Write to any IRQ's PTP fields will clear PTP for all IRQ's PTP field.
+ */
+union cvmx_ciu_sum1_ppx_ip3 {
+	uint64_t u64;
+	struct cvmx_ciu_sum1_ppx_ip3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< SRIO3 interrupt
+                                                         See SRIO3_INT_REG, SRIO3_INT2_REG */
+	uint64_t srio2                        : 1;  /**< SRIO2 interrupt
+                                                         See SRIO2_INT_REG, SRIO2_INT2_REG */
+	uint64_t reserved_57_59               : 3;
+	uint64_t dfm                          : 1;  /**< DFM Interrupt
+                                                         See DFM_FNT_STAT */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_51_51               : 1;
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt
+                                                         See SRIO0_INT_REG, SRIO0_INT2_REG */
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         TBD, See DPI DMA instruction completion */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt
+                                                         See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
+                                                         PCS1_INT*_REG, PCSX1_INT_REG */
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt
+                                                         See EMMC interrupt */
+	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt
+                                                         See MIX1_ISR */
+	uint64_t reserved_10_17               : 8;
+	uint64_t wdog                         : 10; /**< Per PP watchdog interrupts */
+#else
+	uint64_t wdog                         : 10;
+	uint64_t reserved_10_17               : 8;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu_sum1_ppx_ip3_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         TBD, See DPI DMA instruction completion */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt
+                                                         See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
+                                                         PCS1_INT*_REG, PCSX1_INT_REG */
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt
+                                                         See EMMC interrupt */
+	uint64_t mii1                         : 1;  /**< RGMII/MIX Interface 1 Interrupt
+                                                         See MIX1_ISR */
+	uint64_t reserved_4_17                : 14;
+	uint64_t wdog                         : 4;  /**< Per PP watchdog interrupts */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_17                : 14;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_sum1_ppx_ip3_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< SRIO3 interrupt
+                                                         See SRIO3_INT_REG, SRIO3_INT2_REG */
+	uint64_t srio2                        : 1;  /**< SRIO2 interrupt
+                                                         See SRIO2_INT_REG, SRIO2_INT2_REG */
+	uint64_t reserved_57_59               : 3;
+	uint64_t dfm                          : 1;  /**< DFM Interrupt
+                                                         See DFM_FNT_STAT */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_51_51               : 1;
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt
+                                                         See SRIO0_INT_REG, SRIO0_INT2_REG */
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_38_45               : 8;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt
+                                                         See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
+                                                         PCS1_INT*_REG, PCSX1_INT_REG */
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt
+                                                         See NDF_INT */
+	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt
+                                                         See MIX1_ISR */
+	uint64_t reserved_10_17               : 8;
+	uint64_t wdog                         : 10; /**< 10 watchdog interrupts */
+#else
+	uint64_t wdog                         : 10;
+	uint64_t reserved_10_17               : 8;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_45               : 8;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t rst                          : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_sum1_ppx_ip3_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t reserved_41_46               : 6;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         TBD, See DPI DMA instruction completion */
+	uint64_t reserved_37_39               : 3;
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t reserved_32_32               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t reserved_28_28               : 1;
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt
+                                                         See EMMC interrupt */
+	uint64_t reserved_4_18                : 15;
+	uint64_t wdog                         : 4;  /**< Per PP watchdog interrupts */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_18                : 15;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_28_28               : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_32_32               : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_46               : 6;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cnf71xx;
+};
+typedef union cvmx_ciu_sum1_ppx_ip3 cvmx_ciu_sum1_ppx_ip3_t;
+
+/**
+ * cvmx_ciu_sum1_pp#_ip4
+ *
+ * Notes:
+ * SUM1 becomes per IPx in o65/6 and afterwards. Only Field <40> DPI_DMA will have
+ * different value per PP(IP) for  $CIU_SUM1_PPx_IPy, and <40> DPI_DMA will always
+ * be zero for  $CIU_SUM1_IOX_INT. All other fields ([63:41] and [39:0]) values  are idential for
+ * different PPs, same value as $CIU_INT_SUM1.
+ * Write to any IRQ's PTP fields will clear PTP for all IRQ's PTP field.
+ */
+union cvmx_ciu_sum1_ppx_ip4 {
+	uint64_t u64;
+	struct cvmx_ciu_sum1_ppx_ip4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< SRIO3 interrupt
+                                                         See SRIO3_INT_REG, SRIO3_INT2_REG */
+	uint64_t srio2                        : 1;  /**< SRIO2 interrupt
+                                                         See SRIO2_INT_REG, SRIO2_INT2_REG */
+	uint64_t reserved_57_59               : 3;
+	uint64_t dfm                          : 1;  /**< DFM Interrupt
+                                                         See DFM_FNT_STAT */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_51_51               : 1;
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt
+                                                         See SRIO0_INT_REG, SRIO0_INT2_REG */
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         TBD, See DPI DMA instruction completion */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt
+                                                         See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
+                                                         PCS1_INT*_REG, PCSX1_INT_REG */
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt
+                                                         See EMMC interrupt */
+	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt
+                                                         See MIX1_ISR */
+	uint64_t reserved_10_17               : 8;
+	uint64_t wdog                         : 10; /**< Per PP watchdog interrupts */
+#else
+	uint64_t wdog                         : 10;
+	uint64_t reserved_10_17               : 8;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu_sum1_ppx_ip4_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_41_45               : 5;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         TBD, See DPI DMA instruction completion */
+	uint64_t reserved_38_39               : 2;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt
+                                                         See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
+                                                         PCS1_INT*_REG, PCSX1_INT_REG */
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt
+                                                         See EMMC interrupt */
+	uint64_t mii1                         : 1;  /**< RGMII/MIX Interface 1 Interrupt
+                                                         See MIX1_ISR */
+	uint64_t reserved_4_17                : 14;
+	uint64_t wdog                         : 4;  /**< Per PP watchdog interrupts */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_17                : 14;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_39               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_45               : 5;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_sum1_ppx_ip4_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_62_62               : 1;
+	uint64_t srio3                        : 1;  /**< SRIO3 interrupt
+                                                         See SRIO3_INT_REG, SRIO3_INT2_REG */
+	uint64_t srio2                        : 1;  /**< SRIO2 interrupt
+                                                         See SRIO2_INT_REG, SRIO2_INT2_REG */
+	uint64_t reserved_57_59               : 3;
+	uint64_t dfm                          : 1;  /**< DFM Interrupt
+                                                         See DFM_FNT_STAT */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_51_51               : 1;
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt
+                                                         See SRIO0_INT_REG, SRIO0_INT2_REG */
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_38_45               : 8;
+	uint64_t agx1                         : 1;  /**< GMX1 interrupt
+                                                         See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
+                                                         PCS1_INT*_REG, PCSX1_INT_REG */
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt
+                                                         See NDF_INT */
+	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt
+                                                         See MIX1_ISR */
+	uint64_t reserved_10_17               : 8;
+	uint64_t wdog                         : 10; /**< 10 watchdog interrupts */
+#else
+	uint64_t wdog                         : 10;
+	uint64_t reserved_10_17               : 8;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t agx1                         : 1;
+	uint64_t reserved_38_45               : 8;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_59               : 3;
+	uint64_t srio2                        : 1;
+	uint64_t srio3                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t rst                          : 1;
+#endif
+	} cn66xx;
+	struct cvmx_ciu_sum1_ppx_ip4_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_53_62               : 10;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t reserved_50_51               : 2;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t reserved_41_46               : 6;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         TBD, See DPI DMA instruction completion */
+	uint64_t reserved_37_39               : 3;
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t reserved_32_32               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t reserved_28_28               : 1;
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< EMMC Flash Controller interrupt
+                                                         See EMMC interrupt */
+	uint64_t reserved_4_18                : 15;
+	uint64_t wdog                         : 4;  /**< Per PP watchdog interrupts */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_18                : 15;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_28_28               : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_32_32               : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_41_46               : 6;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_50_51               : 2;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_62               : 10;
+	uint64_t rst                          : 1;
+#endif
+	} cnf71xx;
+};
+typedef union cvmx_ciu_sum1_ppx_ip4 cvmx_ciu_sum1_ppx_ip4_t;
+
+/**
+ * cvmx_ciu_sum2_io#_int
+ *
+ * Notes:
+ * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
+ *
+ */
+union cvmx_ciu_sum2_iox_int {
+	uint64_t u64;
+	struct cvmx_ciu_sum2_iox_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t endor                        : 2;  /**< ENDOR PHY interrupts, see ENDOR interrupt status
+                                                         register ENDOR_RSTCLK_INTR0(1)_STATUS for details */
+	uint64_t eoi                          : 1;  /**< EOI rsl interrupt, see EOI_INT_STA */
+	uint64_t reserved_10_11               : 2;
+	uint64_t timer                        : 6;  /**< General timer 4-9 interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
+                                                         common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                         will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                         are set at the same time, but clearing are based on
+                                                         per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_INT*_SUM0/4[TIMER] field implement all 10
+                                                         CIU_TIM* interrupts. */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_11               : 2;
+	uint64_t eoi                          : 1;
+	uint64_t endor                        : 2;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_ciu_sum2_iox_int_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t timer                        : 6;  /**< General timer 4-9 interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
+                                                         common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                         will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                         are set at the same time, but clearing are based on
+                                                         per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_INT*_SUM0/4[TIMER] field implement all 10
+                                                         CIU_TIM* interrupts. */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_sum2_iox_int_cn61xx   cn66xx;
+	struct cvmx_ciu_sum2_iox_int_s        cnf71xx;
+};
+typedef union cvmx_ciu_sum2_iox_int cvmx_ciu_sum2_iox_int_t;
+
+/**
+ * cvmx_ciu_sum2_pp#_ip2
+ *
+ * Notes:
+ * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
+ *
+ */
+union cvmx_ciu_sum2_ppx_ip2 {
+	uint64_t u64;
+	struct cvmx_ciu_sum2_ppx_ip2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t endor                        : 2;  /**< ENDOR PHY interrupts, see ENDOR interrupt status
+                                                         register ENDOR_RSTCLK_INTR0(1)_STATUS for details */
+	uint64_t eoi                          : 1;  /**< EOI rsl interrupt, see EOI_INT_STA */
+	uint64_t reserved_10_11               : 2;
+	uint64_t timer                        : 6;  /**< General timer 4-9 interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
+                                                         common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                         will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                         are set at the same time, but clearing are based on
+                                                         per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_INT*_SUM0/4[TIMER] field implement all 10
+                                                         CIU_TIM* interrupts. */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_11               : 2;
+	uint64_t eoi                          : 1;
+	uint64_t endor                        : 2;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_ciu_sum2_ppx_ip2_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t timer                        : 6;  /**< General timer 4-9 interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
+                                                         common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                         will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                         are set at the same time, but clearing are based on
+                                                         per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_INT*_SUM0/4[TIMER] field implement all 10
+                                                         CIU_TIM* interrupts. */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_sum2_ppx_ip2_cn61xx   cn66xx;
+	struct cvmx_ciu_sum2_ppx_ip2_s        cnf71xx;
+};
+typedef union cvmx_ciu_sum2_ppx_ip2 cvmx_ciu_sum2_ppx_ip2_t;
+
+/**
+ * cvmx_ciu_sum2_pp#_ip3
+ *
+ * Notes:
+ * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
+ *
+ */
+union cvmx_ciu_sum2_ppx_ip3 {
+	uint64_t u64;
+	struct cvmx_ciu_sum2_ppx_ip3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t endor                        : 2;  /**< ENDOR PHY interrupts, see ENDOR interrupt status
+                                                         register ENDOR_RSTCLK_INTR0(1)_STATUS for details */
+	uint64_t eoi                          : 1;  /**< EOI rsl interrupt, see EOI_INT_STA */
+	uint64_t reserved_10_11               : 2;
+	uint64_t timer                        : 6;  /**< General timer 4-9 interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
+                                                         common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                         will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                         are set at the same time, but clearing are based on
+                                                         per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_INT*_SUM0/4[TIMER] field implement all 10
+                                                         CIU_TIM* interrupts. */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_11               : 2;
+	uint64_t eoi                          : 1;
+	uint64_t endor                        : 2;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_ciu_sum2_ppx_ip3_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t timer                        : 6;  /**< General timer 4-9 interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
+                                                         common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                         will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                         are set at the same time, but clearing are based on
+                                                         per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_INT*_SUM0/4[TIMER] field implement all 10
+                                                         CIU_TIM* interrupts. */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_sum2_ppx_ip3_cn61xx   cn66xx;
+	struct cvmx_ciu_sum2_ppx_ip3_s        cnf71xx;
+};
+typedef union cvmx_ciu_sum2_ppx_ip3 cvmx_ciu_sum2_ppx_ip3_t;
+
+/**
+ * cvmx_ciu_sum2_pp#_ip4
+ *
+ * Notes:
+ * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
+ *
+ */
+union cvmx_ciu_sum2_ppx_ip4 {
+	uint64_t u64;
+	struct cvmx_ciu_sum2_ppx_ip4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t endor                        : 2;  /**< ENDOR PHY interrupts, see ENDOR interrupt status
+                                                         register ENDOR_RSTCLK_INTR0(1)_STATUS for details */
+	uint64_t eoi                          : 1;  /**< EOI rsl interrupt, see EOI_INT_STA */
+	uint64_t reserved_10_11               : 2;
+	uint64_t timer                        : 6;  /**< General timer 4-9 interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
+                                                         common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                         will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                         are set at the same time, but clearing are based on
+                                                         per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_INT*_SUM0/4[TIMER] field implement all 10
+                                                         CIU_TIM* interrupts. */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_11               : 2;
+	uint64_t eoi                          : 1;
+	uint64_t endor                        : 2;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_ciu_sum2_ppx_ip4_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t timer                        : 6;  /**< General timer 4-9 interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
+                                                         common for all PP/IRQs, writing '1' to any PP/IRQ
+                                                         will clear all TIMERx(x=0..9) interrupts.
+                                                         When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+                                                         are set at the same time, but clearing are based on
+                                                         per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+                                                         The combination of this field and the
+                                                         CIU_INT*_SUM0/4[TIMER] field implement all 10
+                                                         CIU_TIM* interrupts. */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t timer                        : 6;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn61xx;
+	struct cvmx_ciu_sum2_ppx_ip4_cn61xx   cn66xx;
+	struct cvmx_ciu_sum2_ppx_ip4_s        cnf71xx;
+};
+typedef union cvmx_ciu_sum2_ppx_ip4 cvmx_ciu_sum2_ppx_ip4_t;
+
+/**
  * cvmx_ciu_tim#
+ *
+ * Notes:
+ * CIU_TIM4-9 did not exist prior to pass 1.2
+ *
  */
-union cvmx_ciu_timx
-{
+union cvmx_ciu_timx {
 	uint64_t u64;
-	struct cvmx_ciu_timx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_timx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_37_63               : 27;
 	uint64_t one_shot                     : 1;  /**< One-shot mode */
 	uint64_t len                          : 36; /**< Timeout length in core clock cycles
@@ -5464,20 +12981,54 @@ union cvmx_ciu_timx
 	struct cvmx_ciu_timx_s                cn56xxp1;
 	struct cvmx_ciu_timx_s                cn58xx;
 	struct cvmx_ciu_timx_s                cn58xxp1;
+	struct cvmx_ciu_timx_s                cn61xx;
 	struct cvmx_ciu_timx_s                cn63xx;
 	struct cvmx_ciu_timx_s                cn63xxp1;
+	struct cvmx_ciu_timx_s                cn66xx;
+	struct cvmx_ciu_timx_s                cn68xx;
+	struct cvmx_ciu_timx_s                cn68xxp1;
+	struct cvmx_ciu_timx_s                cnf71xx;
 };
 typedef union cvmx_ciu_timx cvmx_ciu_timx_t;
 
 /**
+ * cvmx_ciu_tim_multi_cast
+ *
+ * Notes:
+ * This register does not exist prior to pass 1.2 silicon. Those earlier chip passes operate as if
+ * EN==0.
+ */
+union cvmx_ciu_tim_multi_cast {
+	uint64_t u64;
+	struct cvmx_ciu_tim_multi_cast_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_1_63                : 63;
+	uint64_t en                           : 1;  /**< General Timer Interrupt Mutli-Cast mode:
+                                                         - 0: Timer interrupt is common for all PP/IRQs.
+                                                         - 1: Timer interrupts are set at the same time for
+                                                            all PP/IRQs, but interrupt clearings can/need
+                                                            to be done Individually based on per cnMIPS core.
+                                                          Timer interrupts for IOs (X=32,33) will always use
+                                                          common interrupts. Clear any of the I/O interrupts
+                                                          will clear the common interrupt. */
+#else
+	uint64_t en                           : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_ciu_tim_multi_cast_s      cn61xx;
+	struct cvmx_ciu_tim_multi_cast_s      cn66xx;
+	struct cvmx_ciu_tim_multi_cast_s      cnf71xx;
+};
+typedef union cvmx_ciu_tim_multi_cast cvmx_ciu_tim_multi_cast_t;
+
+/**
  * cvmx_ciu_wdog#
  */
-union cvmx_ciu_wdogx
-{
+union cvmx_ciu_wdogx {
 	uint64_t u64;
-	struct cvmx_ciu_wdogx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ciu_wdogx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_46_63               : 18;
 	uint64_t gstopen                      : 1;  /**< GSTOPEN */
 	uint64_t dstop                        : 1;  /**< DSTOP */
@@ -5519,8 +13070,13 @@ union cvmx_ciu_wdogx
 	struct cvmx_ciu_wdogx_s               cn56xxp1;
 	struct cvmx_ciu_wdogx_s               cn58xx;
 	struct cvmx_ciu_wdogx_s               cn58xxp1;
+	struct cvmx_ciu_wdogx_s               cn61xx;
 	struct cvmx_ciu_wdogx_s               cn63xx;
 	struct cvmx_ciu_wdogx_s               cn63xxp1;
+	struct cvmx_ciu_wdogx_s               cn66xx;
+	struct cvmx_ciu_wdogx_s               cn68xx;
+	struct cvmx_ciu_wdogx_s               cn68xxp1;
+	struct cvmx_ciu_wdogx_s               cnf71xx;
 };
 typedef union cvmx_ciu_wdogx cvmx_ciu_wdogx_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-ciu2-defs.h b/sys/contrib/octeon-sdk/cvmx-ciu2-defs.h
new file mode 100644
index 0000000..a28f404
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-ciu2-defs.h
@@ -0,0 +1,10670 @@
+/***********************license start***************
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-ciu2-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon ciu2.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_CIU2_DEFS_H__
+#define __CVMX_CIU2_DEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_ACK_IOX_INT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_ACK_IOX_INT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_ACK_IOX_INT(block_id) (CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_ACK_PPX_IP2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_ACK_PPX_IP2(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_ACK_PPX_IP3(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_ACK_PPX_IP3(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_ACK_PPX_IP4(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_ACK_PPX_IP4(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000C0400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_ACK_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_GPIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_GPIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108097800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108097800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_GPIO_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_GPIO_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080B7800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B7800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_GPIO_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_GPIO_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080A7800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A7800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_IO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_IO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108094800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108094800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_IO_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_IO_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080B4800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B4800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_IO_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_IO_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080A4800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A4800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_MBOX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_MBOX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108098800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070108098800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_MBOX_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_MBOX_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080B8800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B8800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_MBOX_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_MBOX_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080A8800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A8800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_MEM(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_MEM(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108095800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108095800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_MEM_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_MEM_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080B5800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B5800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_MEM_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_MEM_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080A5800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A5800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_MIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_MIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108093800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108093800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_MIO_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_MIO_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080B3800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B3800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_MIO_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_MIO_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080A3800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A3800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_PKT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_PKT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108096800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108096800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_PKT_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_PKT_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080B6800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B6800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_PKT_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_PKT_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080A6800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A6800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_RML(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_RML(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108092800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108092800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_RML_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_RML_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080B2800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B2800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_RML_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_RML_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080A2800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A2800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_WDOG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_WDOG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108091800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108091800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_WDOG_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_WDOG_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080B1800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B1800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_WDOG_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_WDOG_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080A1800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A1800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_WRKQ(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_WRKQ(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108090800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108090800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_WRKQ_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_WRKQ_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080B0800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B0800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_IOX_INT_WRKQ_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_EN_IOX_INT_WRKQ_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701080A0800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A0800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_GPIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_GPIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100097000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_GPIO_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_GPIO_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B7000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_GPIO_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_GPIO_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A7000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_IO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_IO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100094000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_IO_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_IO_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B4000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_IO_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_IO_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A4000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_MBOX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MBOX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100098000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B8000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_MBOX_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MBOX_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A8000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_MEM(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MEM(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100095000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_MEM_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MEM_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B5000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_MEM_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MEM_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A5000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_MIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100093000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_MIO_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MIO_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B3000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_MIO_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MIO_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A3000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_PKT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_PKT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100096000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_PKT_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_PKT_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B6000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_PKT_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_PKT_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A6000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_RML(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_RML(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_RML_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_RML_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B2000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_RML_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_RML_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A2000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_WDOG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_WDOG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_WDOG_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_WDOG_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B1000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_WDOG_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_WDOG_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A1000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_WRKQ(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_WRKQ(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_GPIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_GPIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100097200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_GPIO_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_GPIO_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B7200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_GPIO_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_GPIO_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A7200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_IO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_IO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100094200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_IO_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_IO_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B4200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_IO_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_IO_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A4200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_MBOX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MBOX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100098200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_MEM(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MEM(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100095200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_MEM_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MEM_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B5200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_MEM_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MEM_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A5200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_MIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100093200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_MIO_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MIO_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B3200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_MIO_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MIO_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A3200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_PKT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_PKT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100096200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_PKT_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_PKT_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B6200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_PKT_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_PKT_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A6200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_RML(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_RML(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100092200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_RML_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_RML_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B2200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_RML_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_RML_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A2200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_WDOG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_WDOG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100091200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_WDOG_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_WDOG_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B1200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_WDOG_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_WDOG_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A1200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_WRKQ(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_WRKQ(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100090200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_WRKQ_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_WRKQ_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B0200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP3_WRKQ_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP3_WRKQ_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A0200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_GPIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_GPIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100097400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_GPIO_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_GPIO_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B7400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_GPIO_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_GPIO_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A7400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_IO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_IO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100094400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_IO_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_IO_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B4400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_IO_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_IO_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A4400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_MBOX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MBOX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100098400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_MBOX_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MBOX_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B8400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_MBOX_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MBOX_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A8400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_MEM(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MEM(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100095400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_MEM_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MEM_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B5400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_MEM_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MEM_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A5400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_MIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100093400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_MIO_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MIO_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B3400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_MIO_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MIO_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A3400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_PKT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_PKT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100096400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_PKT_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_PKT_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B6400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_PKT_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_PKT_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A6400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_RML(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_RML(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100092400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_RML_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_RML_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B2400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_RML_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_RML_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A2400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_WDOG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_WDOG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100091400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_WDOG_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_WDOG_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B1400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_WDOG_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_WDOG_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A1400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_WRKQ(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_WRKQ(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100090400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_WRKQ_W1C(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_WRKQ_W1C(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000B0400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_EN_PPX_IP4_WRKQ_W1S(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_EN_PPX_IP4_WRKQ_W1S(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000A0400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU2_INTR_CIU_READY CVMX_CIU2_INTR_CIU_READY_FUNC()
+static inline uint64_t CVMX_CIU2_INTR_CIU_READY_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_CIU2_INTR_CIU_READY not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070100102008ull);
+}
+#else
+#define CVMX_CIU2_INTR_CIU_READY (CVMX_ADD_IO_SEG(0x0001070100102008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU2_INTR_RAM_ECC_CTL CVMX_CIU2_INTR_RAM_ECC_CTL_FUNC()
+static inline uint64_t CVMX_CIU2_INTR_RAM_ECC_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_CIU2_INTR_RAM_ECC_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070100102010ull);
+}
+#else
+#define CVMX_CIU2_INTR_RAM_ECC_CTL (CVMX_ADD_IO_SEG(0x0001070100102010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU2_INTR_RAM_ECC_ST CVMX_CIU2_INTR_RAM_ECC_ST_FUNC()
+static inline uint64_t CVMX_CIU2_INTR_RAM_ECC_ST_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_CIU2_INTR_RAM_ECC_ST not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070100102018ull);
+}
+#else
+#define CVMX_CIU2_INTR_RAM_ECC_ST (CVMX_ADD_IO_SEG(0x0001070100102018ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU2_INTR_SLOWDOWN CVMX_CIU2_INTR_SLOWDOWN_FUNC()
+static inline uint64_t CVMX_CIU2_INTR_SLOWDOWN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_CIU2_INTR_SLOWDOWN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070100102000ull);
+}
+#else
+#define CVMX_CIU2_INTR_SLOWDOWN (CVMX_ADD_IO_SEG(0x0001070100102000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_MSIRED_PPX_IP2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_MSIRED_PPX_IP2(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000C1000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_MSIRED_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_MSIRED_PPX_IP3(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_MSIRED_PPX_IP3(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000C1200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_MSIRED_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_MSIRED_PPX_IP4(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_MSIRED_PPX_IP4(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00010701000C1400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_MSIRED_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_MSI_RCVX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 255)))))
+		cvmx_warn("CVMX_CIU2_MSI_RCVX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010701000C2000ull) + ((offset) & 255) * 8;
+}
+#else
+#define CVMX_CIU2_MSI_RCVX(offset) (CVMX_ADD_IO_SEG(0x00010701000C2000ull) + ((offset) & 255) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_MSI_SELX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 255)))))
+		cvmx_warn("CVMX_CIU2_MSI_SELX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010701000C3000ull) + ((offset) & 255) * 8;
+}
+#else
+#define CVMX_CIU2_MSI_SELX(offset) (CVMX_ADD_IO_SEG(0x00010701000C3000ull) + ((offset) & 255) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_IOX_INT_GPIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_RAW_IOX_INT_GPIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108047800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108047800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_IOX_INT_IO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_RAW_IOX_INT_IO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108044800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108044800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_IOX_INT_MEM(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_RAW_IOX_INT_MEM(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108045800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108045800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_IOX_INT_MIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_RAW_IOX_INT_MIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108043800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108043800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_IOX_INT_PKT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_RAW_IOX_INT_PKT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108046800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108046800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_IOX_INT_RML(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_RAW_IOX_INT_RML(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108042800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108042800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_IOX_INT_WDOG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_RAW_IOX_INT_WDOG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108041800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108041800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_IOX_INT_WRKQ(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_RAW_IOX_INT_WRKQ(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108040800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108040800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP2_GPIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_GPIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100047000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP2_IO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_IO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100044000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP2_MEM(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_MEM(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100045000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP2_MIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_MIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100043000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP2_PKT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_PKT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100046000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP2_RML(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_RML(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100042000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP2_WDOG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_WDOG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100041000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP2_WRKQ(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_WRKQ(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP3_GPIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_GPIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100047200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP3_IO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_IO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100044200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP3_MEM(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_MEM(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100045200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP3_MIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_MIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100043200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP3_PKT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_PKT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100046200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP3_RML(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_RML(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100042200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP3_WDOG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_WDOG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100041200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP3_WRKQ(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_WRKQ(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100040200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP4_GPIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_GPIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100047400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP4_IO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_IO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100044400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP4_MEM(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_MEM(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100045400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP4_MIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_MIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100043400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP4_PKT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_PKT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100046400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP4_RML(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_RML(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100042400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP4_WDOG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_WDOG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100041400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_RAW_PPX_IP4_WRKQ(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_WRKQ(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100040400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_RAW_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_IOX_INT_GPIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_SRC_IOX_INT_GPIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108087800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108087800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_IOX_INT_IO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_SRC_IOX_INT_IO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108084800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108084800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_IOX_INT_MBOX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_SRC_IOX_INT_MBOX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108088800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_IOX_INT_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070108088800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_IOX_INT_MEM(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_SRC_IOX_INT_MEM(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108085800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108085800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_IOX_INT_MIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_SRC_IOX_INT_MIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108083800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108083800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_IOX_INT_PKT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_SRC_IOX_INT_PKT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108086800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108086800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_IOX_INT_RML(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_SRC_IOX_INT_RML(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108082800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108082800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_IOX_INT_WDOG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_SRC_IOX_INT_WDOG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108081800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108081800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_IOX_INT_WRKQ(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_CIU2_SRC_IOX_INT_WRKQ(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070108080800ull) + ((block_id) & 1) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108080800ull) + ((block_id) & 1) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP2_GPIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_GPIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100087000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP2_IO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_IO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100084000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP2_MBOX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_MBOX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100088000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP2_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP2_MEM(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_MEM(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100085000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP2_MIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_MIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100083000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP2_PKT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_PKT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100086000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP2_RML(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_RML(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100082000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP2_WDOG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_WDOG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100081000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP2_WRKQ(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_WRKQ(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100080000ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080000ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP3_GPIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_GPIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100087200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP3_IO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_IO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100084200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP3_MBOX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_MBOX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100088200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP3_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP3_MEM(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_MEM(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100085200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP3_MIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_MIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100083200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP3_PKT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_PKT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100086200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP3_RML(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_RML(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100082200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP3_WDOG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_WDOG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100081200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP3_WRKQ(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_WRKQ(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100080200ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080200ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP4_GPIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_GPIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100087400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP4_IO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_IO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100084400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP4_MBOX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_MBOX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100088400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP4_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP4_MEM(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_MEM(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100085400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP4_MIO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_MIO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100083400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP4_PKT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_PKT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100086400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP4_RML(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_RML(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100082400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP4_WDOG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_WDOG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100081400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SRC_PPX_IP4_WRKQ(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
+		cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_WRKQ(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001070100080400ull) + ((block_id) & 31) * 0x200000ull;
+}
+#else
+#define CVMX_CIU2_SRC_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080400ull) + ((block_id) & 31) * 0x200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SUM_IOX_INT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_CIU2_SUM_IOX_INT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070100000800ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_CIU2_SUM_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070100000800ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SUM_PPX_IP2(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_CIU2_SUM_PPX_IP2(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070100000000ull) + ((offset) & 31) * 8;
+}
+#else
+#define CVMX_CIU2_SUM_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070100000000ull) + ((offset) & 31) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SUM_PPX_IP3(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_CIU2_SUM_PPX_IP3(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070100000200ull) + ((offset) & 31) * 8;
+}
+#else
+#define CVMX_CIU2_SUM_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070100000200ull) + ((offset) & 31) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU2_SUM_PPX_IP4(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_CIU2_SUM_PPX_IP4(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070100000400ull) + ((offset) & 31) * 8;
+}
+#else
+#define CVMX_CIU2_SUM_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070100000400ull) + ((offset) & 31) * 8)
+#endif
+
+/**
+ * cvmx_ciu2_ack_io#_int
+ */
+union cvmx_ciu2_ack_iox_int {
+	uint64_t u64;
+	struct cvmx_ciu2_ack_iox_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_1_63                : 63;
+	uint64_t ack                          : 1;  /**< Read to clear the corresponding interrupt to
+                                                         PP/IO.  Without this read the interrupt will not
+                                                         deassert until the next CIU interrupt scan, up to
+                                                         200 cycles away. */
+#else
+	uint64_t ack                          : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_ciu2_ack_iox_int_s        cn68xx;
+	struct cvmx_ciu2_ack_iox_int_s        cn68xxp1;
+};
+typedef union cvmx_ciu2_ack_iox_int cvmx_ciu2_ack_iox_int_t;
+
+/**
+ * cvmx_ciu2_ack_pp#_ip2
+ *
+ * CIU2_ACK_PPX_IPx      (Pass 2)
+ *
+ */
+union cvmx_ciu2_ack_ppx_ip2 {
+	uint64_t u64;
+	struct cvmx_ciu2_ack_ppx_ip2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_1_63                : 63;
+	uint64_t ack                          : 1;  /**< Read to clear the corresponding interrupt to
+                                                         PP/IO.  Without this read the interrupt will not
+                                                         deassert until the next CIU interrupt scan, up to
+                                                         200 cycles away. */
+#else
+	uint64_t ack                          : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_ciu2_ack_ppx_ip2_s        cn68xx;
+	struct cvmx_ciu2_ack_ppx_ip2_s        cn68xxp1;
+};
+typedef union cvmx_ciu2_ack_ppx_ip2 cvmx_ciu2_ack_ppx_ip2_t;
+
+/**
+ * cvmx_ciu2_ack_pp#_ip3
+ */
+union cvmx_ciu2_ack_ppx_ip3 {
+	uint64_t u64;
+	struct cvmx_ciu2_ack_ppx_ip3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_1_63                : 63;
+	uint64_t ack                          : 1;  /**< Read to clear the corresponding interrupt to
+                                                         PP/IO.  Without this read the interrupt will not
+                                                         deassert until the next CIU interrupt scan, up to
+                                                         200 cycles away. */
+#else
+	uint64_t ack                          : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_ciu2_ack_ppx_ip3_s        cn68xx;
+	struct cvmx_ciu2_ack_ppx_ip3_s        cn68xxp1;
+};
+typedef union cvmx_ciu2_ack_ppx_ip3 cvmx_ciu2_ack_ppx_ip3_t;
+
+/**
+ * cvmx_ciu2_ack_pp#_ip4
+ */
+union cvmx_ciu2_ack_ppx_ip4 {
+	uint64_t u64;
+	struct cvmx_ciu2_ack_ppx_ip4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_1_63                : 63;
+	uint64_t ack                          : 1;  /**< Read to clear the corresponding interrupt to
+                                                         PP/IO.  Without this read the interrupt will not
+                                                         deassert until the next CIU interrupt scan, up to
+                                                         200 cycles away. */
+#else
+	uint64_t ack                          : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_ciu2_ack_ppx_ip4_s        cn68xx;
+	struct cvmx_ciu2_ack_ppx_ip4_s        cn68xxp1;
+};
+typedef union cvmx_ciu2_ack_ppx_ip4 cvmx_ciu2_ack_ppx_ip4_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_gpio
+ */
+union cvmx_ciu2_en_iox_int_gpio {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupt-enable */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_gpio_s    cn68xx;
+	struct cvmx_ciu2_en_iox_int_gpio_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_gpio cvmx_ciu2_en_iox_int_gpio_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_gpio_w1c
+ */
+union cvmx_ciu2_en_iox_int_gpio_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_gpio_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< Write 1 to clear CIU2_EN_xx_yy_GPIO[GPIO] */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xx;
+	struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_gpio_w1c cvmx_ciu2_en_iox_int_gpio_w1c_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_gpio_w1s
+ */
+union cvmx_ciu2_en_iox_int_gpio_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_gpio_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupt enable,write 1 to enable CIU2_EN */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xx;
+	struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_gpio_w1s cvmx_ciu2_en_iox_int_gpio_w1s_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_io
+ */
+union cvmx_ciu2_en_iox_int_io {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< PEMx interrupt-enable */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< PCI_INTA interrupt-enable */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< MSI summary bit interrupt-enable
+                                                         This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI  interrupt-enable */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< PCIe INTA/B/C/D interrupt-enable */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_io_s      cn68xx;
+	struct cvmx_ciu2_en_iox_int_io_s      cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_io cvmx_ciu2_en_iox_int_io_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_io_w1c
+ */
+union cvmx_ciu2_en_iox_int_io_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_io_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[PEM] */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTA] */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[MSIRED]
+                                                         This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_MSI] */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTR] */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_io_w1c_s  cn68xx;
+	struct cvmx_ciu2_en_iox_int_io_w1c_s  cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_io_w1c cvmx_ciu2_en_iox_int_io_w1c_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_io_w1s
+ */
+union cvmx_ciu2_en_iox_int_io_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_io_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[PEM] */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTA] */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[MSIRED]
+                                                         This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_MSI] */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTR] */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_io_w1s_s  cn68xx;
+	struct cvmx_ciu2_en_iox_int_io_w1s_s  cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_io_w1s cvmx_ciu2_en_iox_int_io_w1s_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_mbox
+ */
+union cvmx_ciu2_en_iox_int_mbox {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_mbox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t mbox                         : 4;  /**< Mailbox interrupt-enable, use with CIU2_MBOX
+                                                         to generate CIU2_SRC_xx_yy_MBOX */
+#else
+	uint64_t mbox                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_mbox_s    cn68xx;
+	struct cvmx_ciu2_en_iox_int_mbox_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_mbox cvmx_ciu2_en_iox_int_mbox_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_mbox_w1c
+ */
+union cvmx_ciu2_en_iox_int_mbox_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_mbox_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t mbox                         : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_MBOX[MBOX] */
+#else
+	uint64_t mbox                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xx;
+	struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_mbox_w1c cvmx_ciu2_en_iox_int_mbox_w1c_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_mbox_w1s
+ */
+union cvmx_ciu2_en_iox_int_mbox_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_mbox_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t mbox                         : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_MBOX[MBOX] */
+#else
+	uint64_t mbox                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xx;
+	struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_mbox_w1s cvmx_ciu2_en_iox_int_mbox_w1s_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_mem
+ */
+union cvmx_ciu2_en_iox_int_mem {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< LMC* interrupt-enable */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_mem_s     cn68xx;
+	struct cvmx_ciu2_en_iox_int_mem_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_mem cvmx_ciu2_en_iox_int_mem_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_mem_w1c
+ */
+union cvmx_ciu2_en_iox_int_mem_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_mem_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_MEM[LMC] */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xx;
+	struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_mem_w1c cvmx_ciu2_en_iox_int_mem_w1c_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_mem_w1s
+ */
+union cvmx_ciu2_en_iox_int_mem_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_mem_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_MEM[LMC] */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xx;
+	struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_mem_w1s cvmx_ciu2_en_iox_int_mem_w1s_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_mio
+ */
+union cvmx_ciu2_en_iox_int_mio {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt-enable */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< PTP interrupt-enable */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< USB HCI Interrupt-enable */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< USB UCTL* interrupt-enable */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Two UART interrupt-enable */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< TWSI x interrupt-enable */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines interrupt-enable */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt-enable */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt-enable */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< General timer interrupt-enable */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt-enable */
+	uint64_t ssoiq                        : 1;  /**< SSO IQ interrupt-enable */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt-enable */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_mio_s     cn68xx;
+	struct cvmx_ciu2_en_iox_int_mio_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_mio cvmx_ciu2_en_iox_int_mio_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_mio_w1c
+ */
+union cvmx_ciu2_en_iox_int_mio_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_mio_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[RST] */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[PTP] */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_HCI] */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_UCTL] */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[UART] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TWSI] */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[BOOTDMA] */
+	uint64_t mio                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[MIO] */
+	uint64_t nand                         : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[NAND] */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TIMER] */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPD_DRP] */
+	uint64_t ssoiq                        : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[SSQIQ] */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPDPPTHR] */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xx;
+	struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_mio_w1c cvmx_ciu2_en_iox_int_mio_w1c_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_mio_w1s
+ */
+union cvmx_ciu2_en_iox_int_mio_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_mio_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[RST] */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[PTP] */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_HCI] */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_UCTL] */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[UART] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TWSI] */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[BOOTDMA] */
+	uint64_t mio                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[MIO] */
+	uint64_t nand                         : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[NAND] */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TIMER] */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPD_DRP] */
+	uint64_t ssoiq                        : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[SSQIQ] */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPDPPTHR] */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xx;
+	struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_mio_w1s cvmx_ciu2_en_iox_int_mio_w1s_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_pkt
+ */
+union cvmx_ciu2_en_iox_int_pkt {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< ILK Packet Drop interrupt-enable */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupt-enable */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x interrupt-enable */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt-enable */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX packet drop interrupt-enable */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX interrupt-enable */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_pkt_s     cn68xx;
+	struct cvmx_ciu2_en_iox_int_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupt-enable */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x interrupt-enable */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt-enable */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX packet drop interrupt-enable */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX interrupt-enable */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_pkt cvmx_ciu2_en_iox_int_pkt_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_pkt_w1c
+ */
+union cvmx_ciu2_en_iox_int_pkt_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_pkt_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK_DRP] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_pkt_w1c_s cn68xx;
+	struct cvmx_ciu2_en_iox_int_pkt_w1c_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_pkt_w1c cvmx_ciu2_en_iox_int_pkt_w1c_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_pkt_w1s
+ */
+union cvmx_ciu2_en_iox_int_pkt_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_pkt_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK_DRP] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_pkt_w1s_s cn68xx;
+	struct cvmx_ciu2_en_iox_int_pkt_w1s_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_pkt_w1s cvmx_ciu2_en_iox_int_pkt_w1s_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_rml
+ */
+union cvmx_ciu2_en_iox_int_rml {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt-enable */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt-enable */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt-enable */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA interrupt-enable */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< DPI interrupt-enable */
+	uint64_t sli                          : 1;  /**< SLI interrupt-enable */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt-enable */
+	uint64_t rad                          : 1;  /**< RAD interrupt-enable */
+	uint64_t tim                          : 1;  /**< TIM interrupt-enable */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt-enable */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt-enable */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt-enable */
+	uint64_t pip                          : 1;  /**< PIP interrupt-enable */
+	uint64_t ipd                          : 1;  /**< IPD interrupt-enable */
+	uint64_t fpa                          : 1;  /**< FPA interrupt-enable */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt-enable */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_rml_s     cn68xx;
+	struct cvmx_ciu2_en_iox_int_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt-enable */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt-enable */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt-enable */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< DPI interrupt-enable */
+	uint64_t sli                          : 1;  /**< SLI interrupt-enable */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt-enable */
+	uint64_t rad                          : 1;  /**< RAD interrupt-enable */
+	uint64_t tim                          : 1;  /**< TIM interrupt-enable */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt-enable */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt-enable */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt-enable */
+	uint64_t pip                          : 1;  /**< PIP interrupt-enable */
+	uint64_t ipd                          : 1;  /**< IPD interrupt-enable */
+	uint64_t fpa                          : 1;  /**< FPA interrupt-enable */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt-enable */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_rml cvmx_ciu2_en_iox_int_rml_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_rml_w1c
+ */
+union cvmx_ciu2_en_iox_int_rml_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_rml_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI_DMA] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_rml_w1c_s cn68xx;
+	struct cvmx_ciu2_en_iox_int_rml_w1c_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_rml_w1c cvmx_ciu2_en_iox_int_rml_w1c_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_rml_w1s
+ */
+union cvmx_ciu2_en_iox_int_rml_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_rml_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI_DMA] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_rml_w1s_s cn68xx;
+	struct cvmx_ciu2_en_iox_int_rml_w1s_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_rml_w1s cvmx_ciu2_en_iox_int_rml_w1s_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_wdog
+ */
+union cvmx_ciu2_en_iox_int_wdog {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< 32 watchdog interrupt-enable */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_wdog_s    cn68xx;
+	struct cvmx_ciu2_en_iox_int_wdog_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_wdog cvmx_ciu2_en_iox_int_wdog_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_wdog_w1c
+ */
+union cvmx_ciu2_en_iox_int_wdog_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_wdog_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< write 1 to clear CIU2_EN_xx_yy_WDOG */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xx;
+	struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_wdog_w1c cvmx_ciu2_en_iox_int_wdog_w1c_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_wdog_w1s
+ */
+union cvmx_ciu2_en_iox_int_wdog_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_wdog_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< Write 1 to enable CIU2_EN_xx_yy_WDOG[WDOG] */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xx;
+	struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_wdog_w1s cvmx_ciu2_en_iox_int_wdog_w1s_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_wrkq
+ */
+union cvmx_ciu2_en_iox_int_wrkq {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< 64 work queue interrupt-enable */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_wrkq_s    cn68xx;
+	struct cvmx_ciu2_en_iox_int_wrkq_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_wrkq cvmx_ciu2_en_iox_int_wrkq_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_wrkq_w1c
+ */
+union cvmx_ciu2_en_iox_int_wrkq_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_wrkq_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< Write 1 to clear CIU2_EN_xx_yy_WRKQ[WORKQ]
+                                                         For W1C bits, write 1 to clear the corresponding
+                                                         CIU2_EN_xx_yy_WRKQ,write 0 to retain previous value */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xx;
+	struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_wrkq_w1c cvmx_ciu2_en_iox_int_wrkq_w1c_t;
+
+/**
+ * cvmx_ciu2_en_io#_int_wrkq_w1s
+ */
+union cvmx_ciu2_en_iox_int_wrkq_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_iox_int_wrkq_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< Write 1 to enable CIU2_EN_xx_yy_WRKQ[WORKQ]
+                                                         1 bit/group. For all W1S bits, write 1 to enable
+                                                         corresponding CIU2_EN_xx_yy_WRKQ[WORKQ] bit,
+                                                         writing 0 to retain previous value. */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xx;
+	struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_iox_int_wrkq_w1s cvmx_ciu2_en_iox_int_wrkq_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_gpio
+ */
+union cvmx_ciu2_en_ppx_ip2_gpio {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupt-enable */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_gpio_s    cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_gpio_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_gpio cvmx_ciu2_en_ppx_ip2_gpio_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_gpio_w1c
+ */
+union cvmx_ciu2_en_ppx_ip2_gpio_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< Write 1 to clear CIU2_EN_xx_yy_GPIO[GPIO] */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_gpio_w1c cvmx_ciu2_en_ppx_ip2_gpio_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_gpio_w1s
+ */
+union cvmx_ciu2_en_ppx_ip2_gpio_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupt enable,write 1 to enable CIU2_EN */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_gpio_w1s cvmx_ciu2_en_ppx_ip2_gpio_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_io
+ */
+union cvmx_ciu2_en_ppx_ip2_io {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< PEMx interrupt-enable */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< PCI_INTA interrupt-enable */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< MSI summary bit interrupt-enable
+                                                         This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI  interrupt-enable */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< PCIe INTA/B/C/D interrupt-enable */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_io_s      cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_io_s      cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_io cvmx_ciu2_en_ppx_ip2_io_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_io_w1c
+ */
+union cvmx_ciu2_en_ppx_ip2_io_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_io_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[PEM] */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTA] */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[MSIRED]
+                                                         This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_MSI] */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTR] */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_io_w1c_s  cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_io_w1c_s  cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_io_w1c cvmx_ciu2_en_ppx_ip2_io_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_io_w1s
+ */
+union cvmx_ciu2_en_ppx_ip2_io_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_io_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[PEM] */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTA] */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[MSIRED]
+                                                         This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_MSI] */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTR] */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_io_w1s_s  cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_io_w1s_s  cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_io_w1s cvmx_ciu2_en_ppx_ip2_io_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_mbox
+ */
+union cvmx_ciu2_en_ppx_ip2_mbox {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_mbox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t mbox                         : 4;  /**< Mailbox interrupt-enable, use with CIU2_MBOX
+                                                         to generate CIU2_SRC_xx_yy_MBOX */
+#else
+	uint64_t mbox                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_mbox_s    cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_mbox_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_mbox cvmx_ciu2_en_ppx_ip2_mbox_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_mbox_w1c
+ */
+union cvmx_ciu2_en_ppx_ip2_mbox_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t mbox                         : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_MBOX[MBOX] */
+#else
+	uint64_t mbox                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_mbox_w1c cvmx_ciu2_en_ppx_ip2_mbox_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_mbox_w1s
+ */
+union cvmx_ciu2_en_ppx_ip2_mbox_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t mbox                         : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_MBOX[MBOX] */
+#else
+	uint64_t mbox                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_mbox_w1s cvmx_ciu2_en_ppx_ip2_mbox_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_mem
+ */
+union cvmx_ciu2_en_ppx_ip2_mem {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< LMC* interrupt-enable */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_mem_s     cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_mem_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_mem cvmx_ciu2_en_ppx_ip2_mem_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_mem_w1c
+ */
+union cvmx_ciu2_en_ppx_ip2_mem_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_MEM[LMC] */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_mem_w1c cvmx_ciu2_en_ppx_ip2_mem_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_mem_w1s
+ */
+union cvmx_ciu2_en_ppx_ip2_mem_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_MEM[LMC] */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_mem_w1s cvmx_ciu2_en_ppx_ip2_mem_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_mio
+ */
+union cvmx_ciu2_en_ppx_ip2_mio {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt-enable */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< PTP interrupt-enable */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< USB HCI Interrupt-enable */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< USB UCTL* interrupt-enable */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Two UART interrupt-enable */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< TWSI x interrupt-enable */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines interrupt-enable */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt-enable */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt-enable */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< General timer interrupt-enable */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt-enable */
+	uint64_t ssoiq                        : 1;  /**< SSO IQ interrupt-enable */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt-enable */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_mio_s     cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_mio_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_mio cvmx_ciu2_en_ppx_ip2_mio_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_mio_w1c
+ */
+union cvmx_ciu2_en_ppx_ip2_mio_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[RST] */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[PTP] */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_HCI] */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_UCTL] */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[UART] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TWSI] */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[BOOTDMA] */
+	uint64_t mio                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[MIO] */
+	uint64_t nand                         : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[NAND] */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TIMER] */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPD_DRP] */
+	uint64_t ssoiq                        : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[SSQIQ] */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPDPPTHR] */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_mio_w1c cvmx_ciu2_en_ppx_ip2_mio_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_mio_w1s
+ */
+union cvmx_ciu2_en_ppx_ip2_mio_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[RST] */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[PTP] */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_HCI] */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_UCTL] */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[UART] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TWSI] */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[BOOTDMA] */
+	uint64_t mio                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[MIO] */
+	uint64_t nand                         : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[NAND] */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TIMER] */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPD_DRP] */
+	uint64_t ssoiq                        : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[SSQIQ] */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPDPPTHR] */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_mio_w1s cvmx_ciu2_en_ppx_ip2_mio_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_pkt
+ */
+union cvmx_ciu2_en_ppx_ip2_pkt {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< ILK Packet Drop interrupt-enable */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupt-enable */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x interrupt-enable */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt-enable */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX packet drop interrupt-enable */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX interrupt-enable */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_pkt_s     cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupt-enable */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x interrupt-enable */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt-enable */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX packet drop interrupt-enable */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX interrupt-enable */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_pkt cvmx_ciu2_en_ppx_ip2_pkt_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_pkt_w1c
+ */
+union cvmx_ciu2_en_ppx_ip2_pkt_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK_DRP] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_pkt_w1c cvmx_ciu2_en_ppx_ip2_pkt_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_pkt_w1s
+ */
+union cvmx_ciu2_en_ppx_ip2_pkt_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK_DRP] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_pkt_w1s cvmx_ciu2_en_ppx_ip2_pkt_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_rml
+ */
+union cvmx_ciu2_en_ppx_ip2_rml {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt-enable */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt-enable */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt-enable */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA interrupt-enable */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< DPI interrupt-enable */
+	uint64_t sli                          : 1;  /**< SLI interrupt-enable */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt-enable */
+	uint64_t rad                          : 1;  /**< RAD interrupt-enable */
+	uint64_t tim                          : 1;  /**< TIM interrupt-enable */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt-enable */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt-enable */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt-enable */
+	uint64_t pip                          : 1;  /**< PIP interrupt-enable */
+	uint64_t ipd                          : 1;  /**< IPD interrupt-enable */
+	uint64_t fpa                          : 1;  /**< FPA interrupt-enable */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt-enable */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_rml_s     cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt-enable */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt-enable */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt-enable */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< DPI interrupt-enable */
+	uint64_t sli                          : 1;  /**< SLI interrupt-enable */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt-enable */
+	uint64_t rad                          : 1;  /**< RAD interrupt-enable */
+	uint64_t tim                          : 1;  /**< TIM interrupt-enable */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt-enable */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt-enable */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt-enable */
+	uint64_t pip                          : 1;  /**< PIP interrupt-enable */
+	uint64_t ipd                          : 1;  /**< IPD interrupt-enable */
+	uint64_t fpa                          : 1;  /**< FPA interrupt-enable */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt-enable */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_rml cvmx_ciu2_en_ppx_ip2_rml_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_rml_w1c
+ */
+union cvmx_ciu2_en_ppx_ip2_rml_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI_DMA] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_rml_w1c_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_rml_w1c cvmx_ciu2_en_ppx_ip2_rml_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_rml_w1s
+ */
+union cvmx_ciu2_en_ppx_ip2_rml_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI_DMA] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_rml_w1s_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_rml_w1s cvmx_ciu2_en_ppx_ip2_rml_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_wdog
+ */
+union cvmx_ciu2_en_ppx_ip2_wdog {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< 32 watchdog interrupt-enable */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_wdog_s    cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_wdog_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_wdog cvmx_ciu2_en_ppx_ip2_wdog_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_wdog_w1c
+ */
+union cvmx_ciu2_en_ppx_ip2_wdog_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< write 1 to clear CIU2_EN_xx_yy_WDOG */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_wdog_w1c cvmx_ciu2_en_ppx_ip2_wdog_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_wdog_w1s
+ */
+union cvmx_ciu2_en_ppx_ip2_wdog_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< Write 1 to enable CIU2_EN_xx_yy_WDOG[WDOG] */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_wdog_w1s cvmx_ciu2_en_ppx_ip2_wdog_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_wrkq
+ */
+union cvmx_ciu2_en_ppx_ip2_wrkq {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< 64 work queue interrupt-enable */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_wrkq_s    cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_wrkq_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_wrkq cvmx_ciu2_en_ppx_ip2_wrkq_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_wrkq_w1c
+ */
+union cvmx_ciu2_en_ppx_ip2_wrkq_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< Write 1 to clear CIU2_EN_xx_yy_WRKQ[WORKQ]
+                                                         For W1C bits, write 1 to clear the corresponding
+                                                         CIU2_EN_xx_yy_WRKQ,write 0 to retain previous value */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_wrkq_w1c cvmx_ciu2_en_ppx_ip2_wrkq_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip2_wrkq_w1s
+ */
+union cvmx_ciu2_en_ppx_ip2_wrkq_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< Write 1 to enable CIU2_EN_xx_yy_WRKQ[WORKQ]
+                                                         1 bit/group. For all W1S bits, write 1 to enable
+                                                         corresponding CIU2_EN_xx_yy_WRKQ[WORKQ] bit,
+                                                         writing 0 to retain previous value. */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip2_wrkq_w1s cvmx_ciu2_en_ppx_ip2_wrkq_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_gpio
+ */
+union cvmx_ciu2_en_ppx_ip3_gpio {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupt-enable */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_gpio_s    cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_gpio_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_gpio cvmx_ciu2_en_ppx_ip3_gpio_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_gpio_w1c
+ */
+union cvmx_ciu2_en_ppx_ip3_gpio_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< Write 1 to clear CIU2_EN_xx_yy_GPIO[GPIO] */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_gpio_w1c cvmx_ciu2_en_ppx_ip3_gpio_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_gpio_w1s
+ */
+union cvmx_ciu2_en_ppx_ip3_gpio_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupt enable,write 1 to enable CIU2_EN */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_gpio_w1s cvmx_ciu2_en_ppx_ip3_gpio_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_io
+ */
+union cvmx_ciu2_en_ppx_ip3_io {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< PEMx interrupt-enable */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< PCI_INTA interrupt-enable */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< MSI summary bit interrupt-enable
+                                                         This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI  interrupt-enable */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< PCIe INTA/B/C/D interrupt-enable */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_io_s      cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_io_s      cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_io cvmx_ciu2_en_ppx_ip3_io_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_io_w1c
+ */
+union cvmx_ciu2_en_ppx_ip3_io_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_io_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[PEM] */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTA] */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[MSIRED]
+                                                         This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_MSI] */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTR] */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_io_w1c_s  cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_io_w1c_s  cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_io_w1c cvmx_ciu2_en_ppx_ip3_io_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_io_w1s
+ */
+union cvmx_ciu2_en_ppx_ip3_io_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_io_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[PEM] */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTA] */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[MSIRED]
+                                                         This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_MSI] */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTR] */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_io_w1s_s  cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_io_w1s_s  cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_io_w1s cvmx_ciu2_en_ppx_ip3_io_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_mbox
+ */
+union cvmx_ciu2_en_ppx_ip3_mbox {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_mbox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t mbox                         : 4;  /**< Mailbox interrupt-enable, use with CIU2_MBOX
+                                                         to generate CIU2_SRC_xx_yy_MBOX */
+#else
+	uint64_t mbox                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_mbox_s    cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_mbox_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_mbox cvmx_ciu2_en_ppx_ip3_mbox_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_mbox_w1c
+ */
+union cvmx_ciu2_en_ppx_ip3_mbox_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t mbox                         : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_MBOX[MBOX] */
+#else
+	uint64_t mbox                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_mbox_w1c cvmx_ciu2_en_ppx_ip3_mbox_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_mbox_w1s
+ */
+union cvmx_ciu2_en_ppx_ip3_mbox_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t mbox                         : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_MBOX[MBOX] */
+#else
+	uint64_t mbox                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_mbox_w1s cvmx_ciu2_en_ppx_ip3_mbox_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_mem
+ */
+union cvmx_ciu2_en_ppx_ip3_mem {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< LMC* interrupt-enable */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_mem_s     cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_mem_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_mem cvmx_ciu2_en_ppx_ip3_mem_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_mem_w1c
+ */
+union cvmx_ciu2_en_ppx_ip3_mem_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_MEM[LMC] */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_mem_w1c cvmx_ciu2_en_ppx_ip3_mem_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_mem_w1s
+ */
+union cvmx_ciu2_en_ppx_ip3_mem_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_MEM[LMC] */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_mem_w1s cvmx_ciu2_en_ppx_ip3_mem_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_mio
+ */
+union cvmx_ciu2_en_ppx_ip3_mio {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt-enable */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< PTP interrupt-enable */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< USB HCI Interrupt-enable */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< USB UCTL* interrupt-enable */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Two UART interrupt-enable */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< TWSI x interrupt-enable */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines interrupt-enable */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt-enable */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt-enable */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< General timer interrupt-enable */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt-enable */
+	uint64_t ssoiq                        : 1;  /**< SSO IQ interrupt-enable */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt-enable */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_mio_s     cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_mio_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_mio cvmx_ciu2_en_ppx_ip3_mio_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_mio_w1c
+ */
+union cvmx_ciu2_en_ppx_ip3_mio_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[RST] */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[PTP] */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_HCI] */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_UCTL] */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[UART] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TWSI] */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[BOOTDMA] */
+	uint64_t mio                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[MIO] */
+	uint64_t nand                         : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[NAND] */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TIMER] */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPD_DRP] */
+	uint64_t ssoiq                        : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[SSQIQ] */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPDPPTHR] */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_mio_w1c cvmx_ciu2_en_ppx_ip3_mio_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_mio_w1s
+ */
+union cvmx_ciu2_en_ppx_ip3_mio_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[RST] */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[PTP] */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_HCI] */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_UCTL] */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[UART] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TWSI] */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[BOOTDMA] */
+	uint64_t mio                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[MIO] */
+	uint64_t nand                         : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[NAND] */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TIMER] */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPD_DRP] */
+	uint64_t ssoiq                        : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[SSQIQ] */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPDPPTHR] */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_mio_w1s cvmx_ciu2_en_ppx_ip3_mio_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_pkt
+ */
+union cvmx_ciu2_en_ppx_ip3_pkt {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< ILK Packet Drop interrupt-enable */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupt-enable */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x interrupt-enable */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt-enable */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX packet drop interrupt-enable */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX interrupt-enable */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_pkt_s     cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupt-enable */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x interrupt-enable */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt-enable */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX packet drop interrupt-enable */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX interrupt-enable */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_pkt cvmx_ciu2_en_ppx_ip3_pkt_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_pkt_w1c
+ */
+union cvmx_ciu2_en_ppx_ip3_pkt_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK_DRP] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_pkt_w1c cvmx_ciu2_en_ppx_ip3_pkt_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_pkt_w1s
+ */
+union cvmx_ciu2_en_ppx_ip3_pkt_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK_DRP] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_pkt_w1s cvmx_ciu2_en_ppx_ip3_pkt_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_rml
+ */
+union cvmx_ciu2_en_ppx_ip3_rml {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt-enable */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt-enable */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt-enable */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA interrupt-enable */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< DPI interrupt-enable */
+	uint64_t sli                          : 1;  /**< SLI interrupt-enable */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt-enable */
+	uint64_t rad                          : 1;  /**< RAD interrupt-enable */
+	uint64_t tim                          : 1;  /**< TIM interrupt-enable */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt-enable */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt-enable */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt-enable */
+	uint64_t pip                          : 1;  /**< PIP interrupt-enable */
+	uint64_t ipd                          : 1;  /**< IPD interrupt-enable */
+	uint64_t fpa                          : 1;  /**< FPA interrupt-enable */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt-enable */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_rml_s     cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt-enable */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt-enable */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt-enable */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< DPI interrupt-enable */
+	uint64_t sli                          : 1;  /**< SLI interrupt-enable */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt-enable */
+	uint64_t rad                          : 1;  /**< RAD interrupt-enable */
+	uint64_t tim                          : 1;  /**< TIM interrupt-enable */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt-enable */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt-enable */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt-enable */
+	uint64_t pip                          : 1;  /**< PIP interrupt-enable */
+	uint64_t ipd                          : 1;  /**< IPD interrupt-enable */
+	uint64_t fpa                          : 1;  /**< FPA interrupt-enable */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt-enable */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_rml cvmx_ciu2_en_ppx_ip3_rml_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_rml_w1c
+ */
+union cvmx_ciu2_en_ppx_ip3_rml_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI_DMA] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_rml_w1c_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_rml_w1c cvmx_ciu2_en_ppx_ip3_rml_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_rml_w1s
+ */
+union cvmx_ciu2_en_ppx_ip3_rml_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI_DMA] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_rml_w1s_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_rml_w1s cvmx_ciu2_en_ppx_ip3_rml_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_wdog
+ */
+union cvmx_ciu2_en_ppx_ip3_wdog {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< 32 watchdog interrupt-enable */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_wdog_s    cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_wdog_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_wdog cvmx_ciu2_en_ppx_ip3_wdog_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_wdog_w1c
+ */
+union cvmx_ciu2_en_ppx_ip3_wdog_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< write 1 to clear CIU2_EN_xx_yy_WDOG */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_wdog_w1c cvmx_ciu2_en_ppx_ip3_wdog_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_wdog_w1s
+ */
+union cvmx_ciu2_en_ppx_ip3_wdog_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< Write 1 to enable CIU2_EN_xx_yy_WDOG[WDOG] */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_wdog_w1s cvmx_ciu2_en_ppx_ip3_wdog_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_wrkq
+ */
+union cvmx_ciu2_en_ppx_ip3_wrkq {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< 64 work queue interrupt-enable */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_wrkq_s    cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_wrkq_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_wrkq cvmx_ciu2_en_ppx_ip3_wrkq_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_wrkq_w1c
+ */
+union cvmx_ciu2_en_ppx_ip3_wrkq_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< Write 1 to clear CIU2_EN_xx_yy_WRKQ[WORKQ]
+                                                         For W1C bits, write 1 to clear the corresponding
+                                                         CIU2_EN_xx_yy_WRKQ,write 0 to retain previous value */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_wrkq_w1c cvmx_ciu2_en_ppx_ip3_wrkq_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip3_wrkq_w1s
+ */
+union cvmx_ciu2_en_ppx_ip3_wrkq_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< Write 1 to enable CIU2_EN_xx_yy_WRKQ[WORKQ]
+                                                         1 bit/group. For all W1S bits, write 1 to enable
+                                                         corresponding CIU2_EN_xx_yy_WRKQ[WORKQ] bit,
+                                                         writing 0 to retain previous value. */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip3_wrkq_w1s cvmx_ciu2_en_ppx_ip3_wrkq_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_gpio
+ */
+union cvmx_ciu2_en_ppx_ip4_gpio {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupt-enable */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_gpio_s    cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_gpio_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_gpio cvmx_ciu2_en_ppx_ip4_gpio_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_gpio_w1c
+ */
+union cvmx_ciu2_en_ppx_ip4_gpio_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< Write 1 to clear CIU2_EN_xx_yy_GPIO[GPIO] */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_gpio_w1c cvmx_ciu2_en_ppx_ip4_gpio_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_gpio_w1s
+ */
+union cvmx_ciu2_en_ppx_ip4_gpio_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupt enable,write 1 to enable CIU2_EN */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_gpio_w1s cvmx_ciu2_en_ppx_ip4_gpio_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_io
+ */
+union cvmx_ciu2_en_ppx_ip4_io {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< PEMx interrupt-enable */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< PCI_INTA interrupt-enable */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< MSI summary bit interrupt-enable
+                                                         This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI  interrupt-enable */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< PCIe INTA/B/C/D interrupt-enable */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_io_s      cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_io_s      cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_io cvmx_ciu2_en_ppx_ip4_io_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_io_w1c
+ */
+union cvmx_ciu2_en_ppx_ip4_io_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_io_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[PEM] */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTA] */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[MSIRED]
+                                                         This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_MSI] */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTR] */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_io_w1c_s  cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_io_w1c_s  cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_io_w1c cvmx_ciu2_en_ppx_ip4_io_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_io_w1s
+ */
+union cvmx_ciu2_en_ppx_ip4_io_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_io_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[PEM] */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTA] */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[MSIRED]
+                                                         This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_MSI] */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTR] */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_io_w1s_s  cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_io_w1s_s  cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_io_w1s cvmx_ciu2_en_ppx_ip4_io_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_mbox
+ */
+union cvmx_ciu2_en_ppx_ip4_mbox {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_mbox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t mbox                         : 4;  /**< Mailbox interrupt-enable, use with CIU2_MBOX
+                                                         to generate CIU2_SRC_xx_yy_MBOX */
+#else
+	uint64_t mbox                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_mbox_s    cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_mbox_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_mbox cvmx_ciu2_en_ppx_ip4_mbox_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_mbox_w1c
+ */
+union cvmx_ciu2_en_ppx_ip4_mbox_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t mbox                         : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_MBOX[MBOX] */
+#else
+	uint64_t mbox                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_mbox_w1c cvmx_ciu2_en_ppx_ip4_mbox_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_mbox_w1s
+ */
+union cvmx_ciu2_en_ppx_ip4_mbox_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t mbox                         : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_MBOX[MBOX] */
+#else
+	uint64_t mbox                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_mbox_w1s cvmx_ciu2_en_ppx_ip4_mbox_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_mem
+ */
+union cvmx_ciu2_en_ppx_ip4_mem {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< LMC* interrupt-enable */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_mem_s     cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_mem_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_mem cvmx_ciu2_en_ppx_ip4_mem_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_mem_w1c
+ */
+union cvmx_ciu2_en_ppx_ip4_mem_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_MEM[LMC] */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_mem_w1c cvmx_ciu2_en_ppx_ip4_mem_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_mem_w1s
+ */
+union cvmx_ciu2_en_ppx_ip4_mem_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_MEM[LMC] */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_mem_w1s cvmx_ciu2_en_ppx_ip4_mem_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_mio
+ */
+union cvmx_ciu2_en_ppx_ip4_mio {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt-enable */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< PTP interrupt-enable */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< USB HCI Interrupt-enable */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< USB UCTL* interrupt-enable */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Two UART interrupt-enable */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< TWSI x interrupt-enable */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines interrupt-enable */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt-enable */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt-enable */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< General timer interrupt-enable */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt-enable */
+	uint64_t ssoiq                        : 1;  /**< SSO IQ interrupt-enable */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt-enable */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_mio_s     cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_mio_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_mio cvmx_ciu2_en_ppx_ip4_mio_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_mio_w1c
+ */
+union cvmx_ciu2_en_ppx_ip4_mio_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[RST] */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[PTP] */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_HCI] */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_UCTL] */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[UART] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TWSI] */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[BOOTDMA] */
+	uint64_t mio                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[MIO] */
+	uint64_t nand                         : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[NAND] */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TIMER] */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPD_DRP] */
+	uint64_t ssoiq                        : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[SSQIQ] */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPDPPTHR] */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_mio_w1c cvmx_ciu2_en_ppx_ip4_mio_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_mio_w1s
+ */
+union cvmx_ciu2_en_ppx_ip4_mio_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[RST] */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[PTP] */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_HCI] */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_UCTL] */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[UART] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TWSI] */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[BOOTDMA] */
+	uint64_t mio                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[MIO] */
+	uint64_t nand                         : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[NAND] */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TIMER] */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPD_DRP] */
+	uint64_t ssoiq                        : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[SSQIQ] */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPDPPTHR] */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_mio_w1s cvmx_ciu2_en_ppx_ip4_mio_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_pkt
+ */
+union cvmx_ciu2_en_ppx_ip4_pkt {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< ILK Packet Drop interrupt-enable */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupt-enable */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x interrupt-enable */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt-enable */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX packet drop interrupt-enable */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX interrupt-enable */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_pkt_s     cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupt-enable */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x interrupt-enable */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt-enable */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX packet drop interrupt-enable */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX interrupt-enable */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_pkt cvmx_ciu2_en_ppx_ip4_pkt_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_pkt_w1c
+ */
+union cvmx_ciu2_en_ppx_ip4_pkt_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK_DRP] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_pkt_w1c cvmx_ciu2_en_ppx_ip4_pkt_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_pkt_w1s
+ */
+union cvmx_ciu2_en_ppx_ip4_pkt_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK_DRP] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_pkt_w1s cvmx_ciu2_en_ppx_ip4_pkt_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_rml
+ */
+union cvmx_ciu2_en_ppx_ip4_rml {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt-enable */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt-enable */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt-enable */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA interrupt-enable */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< DPI interrupt-enable */
+	uint64_t sli                          : 1;  /**< SLI interrupt-enable */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt-enable */
+	uint64_t rad                          : 1;  /**< RAD interrupt-enable */
+	uint64_t tim                          : 1;  /**< TIM interrupt-enable */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt-enable */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt-enable */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt-enable */
+	uint64_t pip                          : 1;  /**< PIP interrupt-enable */
+	uint64_t ipd                          : 1;  /**< IPD interrupt-enable */
+	uint64_t fpa                          : 1;  /**< FPA interrupt-enable */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt-enable */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_rml_s     cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt-enable */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt-enable */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt-enable */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< DPI interrupt-enable */
+	uint64_t sli                          : 1;  /**< SLI interrupt-enable */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt-enable */
+	uint64_t rad                          : 1;  /**< RAD interrupt-enable */
+	uint64_t tim                          : 1;  /**< TIM interrupt-enable */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt-enable */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt-enable */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt-enable */
+	uint64_t pip                          : 1;  /**< PIP interrupt-enable */
+	uint64_t ipd                          : 1;  /**< IPD interrupt-enable */
+	uint64_t fpa                          : 1;  /**< FPA interrupt-enable */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt-enable */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_rml cvmx_ciu2_en_ppx_ip4_rml_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_rml_w1c
+ */
+union cvmx_ciu2_en_ppx_ip4_rml_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI_DMA] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_rml_w1c_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_rml_w1c cvmx_ciu2_en_ppx_ip4_rml_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_rml_w1s
+ */
+union cvmx_ciu2_en_ppx_ip4_rml_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI_DMA] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_rml_w1s_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_rml_w1s cvmx_ciu2_en_ppx_ip4_rml_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_wdog
+ */
+union cvmx_ciu2_en_ppx_ip4_wdog {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< 32 watchdog interrupt-enable */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_wdog_s    cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_wdog_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_wdog cvmx_ciu2_en_ppx_ip4_wdog_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_wdog_w1c
+ */
+union cvmx_ciu2_en_ppx_ip4_wdog_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< write 1 to clear CIU2_EN_xx_yy_WDOG */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_wdog_w1c cvmx_ciu2_en_ppx_ip4_wdog_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_wdog_w1s
+ */
+union cvmx_ciu2_en_ppx_ip4_wdog_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< Write 1 to enable CIU2_EN_xx_yy_WDOG[WDOG] */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_wdog_w1s cvmx_ciu2_en_ppx_ip4_wdog_w1s_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_wrkq
+ */
+union cvmx_ciu2_en_ppx_ip4_wrkq {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< 64 work queue interrupt-enable */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_wrkq_s    cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_wrkq_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_wrkq cvmx_ciu2_en_ppx_ip4_wrkq_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_wrkq_w1c
+ */
+union cvmx_ciu2_en_ppx_ip4_wrkq_w1c {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< Write 1 to clear CIU2_EN_xx_yy_WRKQ[WORKQ]
+                                                         For W1C bits, write 1 to clear the corresponding
+                                                         CIU2_EN_xx_yy_WRKQ,write 0 to retain previous value */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_wrkq_w1c cvmx_ciu2_en_ppx_ip4_wrkq_w1c_t;
+
+/**
+ * cvmx_ciu2_en_pp#_ip4_wrkq_w1s
+ */
+union cvmx_ciu2_en_ppx_ip4_wrkq_w1s {
+	uint64_t u64;
+	struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< Write 1 to enable CIU2_EN_xx_yy_WRKQ[WORKQ]
+                                                         1 bit/group. For all W1S bits, write 1 to enable
+                                                         corresponding CIU2_EN_xx_yy_WRKQ[WORKQ] bit,
+                                                         writing 0 to retain previous value. */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xx;
+	struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xxp1;
+};
+typedef union cvmx_ciu2_en_ppx_ip4_wrkq_w1s cvmx_ciu2_en_ppx_ip4_wrkq_w1s_t;
+
+/**
+ * cvmx_ciu2_intr_ciu_ready
+ */
+union cvmx_ciu2_intr_ciu_ready {
+	uint64_t u64;
+	struct cvmx_ciu2_intr_ciu_ready_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_1_63                : 63;
+	uint64_t ready                        : 1;  /**< Because of the delay of the IRQ updates which may
+                                                         take about 200 sclk cycles, software should read
+                                                         this register after servicing interrupts and wait
+                                                         for response before enabling interrupt watching.
+                                                         Or, the outdated interrupt will show up again.
+                                                         The read back data return when all interrupts have
+                                                         been serviced, and read back data is always zero.
+                                                         In o68 pass2, CIU_READY gets replaced by CIU2_ACK
+                                                         This becomes an internal debug feature. */
+#else
+	uint64_t ready                        : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_ciu2_intr_ciu_ready_s     cn68xx;
+	struct cvmx_ciu2_intr_ciu_ready_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_intr_ciu_ready cvmx_ciu2_intr_ciu_ready_t;
+
+/**
+ * cvmx_ciu2_intr_ram_ecc_ctl
+ */
+union cvmx_ciu2_intr_ram_ecc_ctl {
+	uint64_t u64;
+	struct cvmx_ciu2_intr_ram_ecc_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_3_63                : 61;
+	uint64_t flip_synd                    : 2;  /**< Testing feature. Flip Syndrom to generate single or
+                                                         double bit error. FLIP_SYND[0] generate even number
+                                                         -ed bits error,FLIP_SYND[1] generate odd bits error */
+	uint64_t ecc_ena                      : 1;  /**< ECC Enable: When set will enable the 9bit ECC
+                                                         check/correct logic for CIU interrupt enable RAM.
+                                                         With ECC enabled, the ECC code will be generated
+                                                         and written in the memory and then later on reads,
+                                                         used to check and correct Single bit error and
+                                                         detect Double Bit error. */
+#else
+	uint64_t ecc_ena                      : 1;
+	uint64_t flip_synd                    : 2;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_ciu2_intr_ram_ecc_ctl_s   cn68xx;
+	struct cvmx_ciu2_intr_ram_ecc_ctl_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_intr_ram_ecc_ctl cvmx_ciu2_intr_ram_ecc_ctl_t;
+
+/**
+ * cvmx_ciu2_intr_ram_ecc_st
+ */
+union cvmx_ciu2_intr_ram_ecc_st {
+	uint64_t u64;
+	struct cvmx_ciu2_intr_ram_ecc_st_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_23_63               : 41;
+	uint64_t addr                         : 7;  /**< Latch the address for latest sde/dde occured
+                                                         The value only 0-98 indicates the different 98 IRQs
+                                                         Software can read all corresponding corrected value
+                                                         from CIU2_EN_PPX_IPx_*** or CIU2_EN_IOX_INT_*** and
+                                                         rewite to the same address to corrected the bit err */
+	uint64_t reserved_13_15               : 3;
+	uint64_t syndrom                      : 9;  /**< Report the latest error syndrom */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t dbe                          : 1;  /**< Double bit error observed. Write '1' to clear */
+	uint64_t sbe                          : 1;  /**< Single bit error observed. Write '1' to clear */
+#else
+	uint64_t sbe                          : 1;
+	uint64_t dbe                          : 1;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t syndrom                      : 9;
+	uint64_t reserved_13_15               : 3;
+	uint64_t addr                         : 7;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} s;
+	struct cvmx_ciu2_intr_ram_ecc_st_s    cn68xx;
+	struct cvmx_ciu2_intr_ram_ecc_st_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_intr_ram_ecc_st cvmx_ciu2_intr_ram_ecc_st_t;
+
+/**
+ * cvmx_ciu2_intr_slowdown
+ */
+union cvmx_ciu2_intr_slowdown {
+	uint64_t u64;
+	struct cvmx_ciu2_intr_slowdown_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_3_63                : 61;
+	uint64_t ctl                          : 3;  /**< Slowdown CIU interrupt walker processing time.
+                                                         IRQ2/3/4 for all 32 PPs are sent to PP (MRC) in
+                                                         a serial bus to reduce global routing. There is
+                                                         no backpressure mechanism designed for this scheme.
+                                                         It will be only a problem when sclk is faster, this
+                                                         Control will process 1 interrupt in 2^(CTL) sclks
+                                                         With different setting, clock rate ratio can handle
+                                                         SLOWDOWN       sclk_freq/aclk_freq ratio
+                                                          0                      3
+                                                          1                      6
+                                                          n                      3*2^(n) */
+#else
+	uint64_t ctl                          : 3;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_ciu2_intr_slowdown_s      cn68xx;
+	struct cvmx_ciu2_intr_slowdown_s      cn68xxp1;
+};
+typedef union cvmx_ciu2_intr_slowdown cvmx_ciu2_intr_slowdown_t;
+
+/**
+ * cvmx_ciu2_msi_rcv#
+ *
+ * CIU2_MSI_RCV  Received MSI state bits    (Pass 2)
+ *
+ */
+union cvmx_ciu2_msi_rcvx {
+	uint64_t u64;
+	struct cvmx_ciu2_msi_rcvx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_1_63                : 63;
+	uint64_t msi_rcv                      : 1;  /**< MSI state bit, set on MSI delivery or by software
+                                                         "write 1" to set or "write 0" to clear.
+                                                         This register is used to create the
+                                                         CIU2_RAW_xx_yy_IO[MSIRED] interrupt.  See also
+                                                         SLI_MSI_RCV. */
+#else
+	uint64_t msi_rcv                      : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_ciu2_msi_rcvx_s           cn68xx;
+	struct cvmx_ciu2_msi_rcvx_s           cn68xxp1;
+};
+typedef union cvmx_ciu2_msi_rcvx cvmx_ciu2_msi_rcvx_t;
+
+/**
+ * cvmx_ciu2_msi_sel#
+ *
+ * CIU2_MSI_SEL  Received MSI SEL enable    (Pass 2)
+ *
+ */
+union cvmx_ciu2_msi_selx {
+	uint64_t u64;
+	struct cvmx_ciu2_msi_selx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_13_63               : 51;
+	uint64_t pp_num                       : 5;  /**< Processor number to receive this MSI interrupt */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ip_num                       : 2;  /**< Interrupt priority level to receive this MSI
+                                                         interrupt (00=IP2, 01=IP3, 10=IP4, 11=rsvd) */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t en                           : 1;  /**< Enable interrupt delivery.
+                                                         Must be set for PP_NUM and IP_NUM to have effect. */
+#else
+	uint64_t en                           : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t ip_num                       : 2;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t pp_num                       : 5;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_ciu2_msi_selx_s           cn68xx;
+	struct cvmx_ciu2_msi_selx_s           cn68xxp1;
+};
+typedef union cvmx_ciu2_msi_selx cvmx_ciu2_msi_selx_t;
+
+/**
+ * cvmx_ciu2_msired_pp#_ip2
+ *
+ * CIU2_MSIRED_PPX_IPx      (Pass 2)
+ * Contains reduced MSI interrupt numbers for delivery to software.
+ * Note MSIRED delivery can only be made to PPs, not to IO; thus there are no CIU2_MSIRED_IO registers.
+ */
+union cvmx_ciu2_msired_ppx_ip2 {
+	uint64_t u64;
+	struct cvmx_ciu2_msired_ppx_ip2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_21_63               : 43;
+	uint64_t intr                         : 1;  /**< Interrupt pending */
+	uint64_t reserved_17_19               : 3;
+	uint64_t newint                       : 1;  /**< New interrupt to be delivered.
+                                                         Internal state, for diagnostic use only.          |   $PR */
+	uint64_t reserved_8_15                : 8;
+	uint64_t msi_num                      : 8;  /**< MSI number causing this interrupt.
+                                                         If multiple MSIs are pending to the same PP and IP,
+                                                         then this contains the numerically lowest MSI number */
+#else
+	uint64_t msi_num                      : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t newint                       : 1;
+	uint64_t reserved_17_19               : 3;
+	uint64_t intr                         : 1;
+	uint64_t reserved_21_63               : 43;
+#endif
+	} s;
+	struct cvmx_ciu2_msired_ppx_ip2_s     cn68xx;
+	struct cvmx_ciu2_msired_ppx_ip2_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_msired_ppx_ip2 cvmx_ciu2_msired_ppx_ip2_t;
+
+/**
+ * cvmx_ciu2_msired_pp#_ip3
+ */
+union cvmx_ciu2_msired_ppx_ip3 {
+	uint64_t u64;
+	struct cvmx_ciu2_msired_ppx_ip3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_21_63               : 43;
+	uint64_t intr                         : 1;  /**< Interrupt pending */
+	uint64_t reserved_17_19               : 3;
+	uint64_t newint                       : 1;  /**< New interrupt to be delivered.
+                                                         Internal state, for diagnostic use only.          |   $PR */
+	uint64_t reserved_8_15                : 8;
+	uint64_t msi_num                      : 8;  /**< MSI number causing this interrupt.
+                                                         If multiple MSIs are pending to the same PP and IP,
+                                                         then this contains the numerically lowest MSI number */
+#else
+	uint64_t msi_num                      : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t newint                       : 1;
+	uint64_t reserved_17_19               : 3;
+	uint64_t intr                         : 1;
+	uint64_t reserved_21_63               : 43;
+#endif
+	} s;
+	struct cvmx_ciu2_msired_ppx_ip3_s     cn68xx;
+	struct cvmx_ciu2_msired_ppx_ip3_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_msired_ppx_ip3 cvmx_ciu2_msired_ppx_ip3_t;
+
+/**
+ * cvmx_ciu2_msired_pp#_ip4
+ */
+union cvmx_ciu2_msired_ppx_ip4 {
+	uint64_t u64;
+	struct cvmx_ciu2_msired_ppx_ip4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_21_63               : 43;
+	uint64_t intr                         : 1;  /**< Interrupt pending */
+	uint64_t reserved_17_19               : 3;
+	uint64_t newint                       : 1;  /**< New interrupt to be delivered.
+                                                         Internal state, for diagnostic use only.          |   $PR */
+	uint64_t reserved_8_15                : 8;
+	uint64_t msi_num                      : 8;  /**< MSI number causing this interrupt.
+                                                         If multiple MSIs are pending to the same PP and IP,
+                                                         then this contains the numerically lowest MSI number */
+#else
+	uint64_t msi_num                      : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t newint                       : 1;
+	uint64_t reserved_17_19               : 3;
+	uint64_t intr                         : 1;
+	uint64_t reserved_21_63               : 43;
+#endif
+	} s;
+	struct cvmx_ciu2_msired_ppx_ip4_s     cn68xx;
+	struct cvmx_ciu2_msired_ppx_ip4_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_msired_ppx_ip4 cvmx_ciu2_msired_ppx_ip4_t;
+
+/**
+ * cvmx_ciu2_raw_io#_int_gpio
+ */
+union cvmx_ciu2_raw_iox_int_gpio {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_iox_int_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts
+                                                         For GPIO, all 98 RAW readout will be same value */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_iox_int_gpio_s   cn68xx;
+	struct cvmx_ciu2_raw_iox_int_gpio_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_iox_int_gpio cvmx_ciu2_raw_iox_int_gpio_t;
+
+/**
+ * cvmx_ciu2_raw_io#_int_io
+ */
+union cvmx_ciu2_raw_iox_int_io {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_iox_int_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< PEMx interrupt
+                                                         See PEMx_INT_SUM (enabled by PEMx_INT_ENB) */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< PCI_INTA software enable
+                                                         See CIU_PCI_INTA */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< MSI summary bit, copy of
+                                                         CIU2_MSIRED_PPx_IPy.INT, all IO interrupts
+                                                         CIU2_RAW_IOX_INT_IO[MSIRED] always zero.
+                                                         This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI
+                                                         See SLI_MSI_RCVn for bit <40+n> */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< PCIe INTA/B/C/D
+                                                         PCI_INTR[3] = INTD
+                                                         PCI_INTR[2] = INTC
+                                                         PCI_INTR[1] = INTB
+                                                         PCI_INTR[0] = INTA
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the SLI chapter of the spec
+                                                         For IO, all 98 RAW readout will be different */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_iox_int_io_s     cn68xx;
+	struct cvmx_ciu2_raw_iox_int_io_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_iox_int_io cvmx_ciu2_raw_iox_int_io_t;
+
+/**
+ * cvmx_ciu2_raw_io#_int_mem
+ */
+union cvmx_ciu2_raw_iox_int_mem {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_iox_int_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< LMC* interrupt
+                                                         See LMC*_INT
+                                                         For MEM, all 98 RAW readout will be same value */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_iox_int_mem_s    cn68xx;
+	struct cvmx_ciu2_raw_iox_int_mem_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_iox_int_mem cvmx_ciu2_raw_iox_int_mem_t;
+
+/**
+ * cvmx_ciu2_raw_io#_int_mio
+ */
+union cvmx_ciu2_raw_iox_int_mio {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_iox_int_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< USB EHCI or OHCI Interrupt
+                                                         See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< USB UCTL* interrupt
+                                                         See UCTL*_INT_REG */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Two UART interrupts
+                                                         See MIO_UARTn_IIR[IID] for bit <34+n> */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< TWSI x Interrupt
+                                                         See MIO_TWSx_INT */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
+                                                         See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt
+                                                         See NDF_INT */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< General timer interrupts
+                                                         Set any time the corresponding CIU timer expires */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt
+                                                         Set any time PIP/IPD drops a packet */
+	uint64_t ssoiq                        : 1;  /**< SSO IQ interrupt
+                                                         See SSO_IQ_INT */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt
+                                                         See IPD_PORT_QOS_INT*
+                                                         For MIO, all 98 RAW readout will be same value */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_iox_int_mio_s    cn68xx;
+	struct cvmx_ciu2_raw_iox_int_mio_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_iox_int_mio cvmx_ciu2_raw_iox_int_mio_t;
+
+/**
+ * cvmx_ciu2_raw_io#_int_pkt
+ */
+union cvmx_ciu2_raw_iox_int_pkt {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_iox_int_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< ILK Packet Drop interrupt pulse */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupts */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x Interrupts
+                                                         See MIX*_ISR */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX 0-4 packet drop interrupt pulse
+                                                         Set any time corresponding GMX drops a packet */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX 0-4 interrupt
+                                                         See GMX*_RX*_INT_REG, GMX*_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX*_INT_REG
+                                                         For PKT, all 98 RAW readout will be same value */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_iox_int_pkt_s    cn68xx;
+	struct cvmx_ciu2_raw_iox_int_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupts */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x Interrupts
+                                                         See MIX*_ISR */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX 0-4 packet drop interrupt pulse
+                                                         Set any time corresponding GMX drops a packet */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX 0-4 interrupt
+                                                         See GMX*_RX*_INT_REG, GMX*_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX*_INT_REG
+                                                         For PKT, all 98 RAW readout will be same value */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_iox_int_pkt cvmx_ciu2_raw_iox_int_pkt_t;
+
+/**
+ * cvmx_ciu2_raw_io#_int_rml
+ */
+union cvmx_ciu2_raw_iox_int_rml {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_iox_int_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         See DPI DMA instruction completion */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_INT_ECCERR, TIM_INT0 */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_INT_REG */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt
+                                                         See SSO_ERR */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM
+                                                         For RML, all 98 RAW readout will be same value */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_iox_int_rml_s    cn68xx;
+	struct cvmx_ciu2_raw_iox_int_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_INT_ECCERR, TIM_INT0 */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_INT_REG */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt
+                                                         See SSO_ERR */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM
+                                                         For RML, all 98 RAW readout will be same value */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_iox_int_rml cvmx_ciu2_raw_iox_int_rml_t;
+
+/**
+ * cvmx_ciu2_raw_io#_int_wdog
+ */
+union cvmx_ciu2_raw_iox_int_wdog {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_iox_int_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< 32 watchdog interrupts
+                                                         For WDOG, all 98 RAW readout will be same value */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_iox_int_wdog_s   cn68xx;
+	struct cvmx_ciu2_raw_iox_int_wdog_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_iox_int_wdog cvmx_ciu2_raw_iox_int_wdog_t;
+
+/**
+ * cvmx_ciu2_raw_io#_int_wrkq
+ */
+union cvmx_ciu2_raw_iox_int_wrkq {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_iox_int_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< 64 work queue interrupts
+                                                         See SSO_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the SSO.
+                                                          For WRKQ, all 98 RAW readout will be same value */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_iox_int_wrkq_s   cn68xx;
+	struct cvmx_ciu2_raw_iox_int_wrkq_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_iox_int_wrkq cvmx_ciu2_raw_iox_int_wrkq_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip2_gpio
+ */
+union cvmx_ciu2_raw_ppx_ip2_gpio {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip2_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts
+                                                         For GPIO, all 98 RAW readout will be same value */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip2_gpio_s   cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip2_gpio_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip2_gpio cvmx_ciu2_raw_ppx_ip2_gpio_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip2_io
+ */
+union cvmx_ciu2_raw_ppx_ip2_io {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip2_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< PEMx interrupt
+                                                         See PEMx_INT_SUM (enabled by PEMx_INT_ENB) */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< PCI_INTA software enable
+                                                         See CIU_PCI_INTA */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< MSI summary bit, copy of
+                                                         CIU2_MSIRED_PPx_IPy.INT, all IO interrupts
+                                                         CIU2_RAW_IOX_INT_IO[MSIRED] always zero.
+                                                         This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI
+                                                         See SLI_MSI_RCVn for bit <40+n> */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< PCIe INTA/B/C/D
+                                                         PCI_INTR[3] = INTD
+                                                         PCI_INTR[2] = INTC
+                                                         PCI_INTR[1] = INTB
+                                                         PCI_INTR[0] = INTA
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the SLI chapter of the spec
+                                                         For IO, all 98 RAW readout will be different */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip2_io_s     cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip2_io_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip2_io cvmx_ciu2_raw_ppx_ip2_io_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip2_mem
+ */
+union cvmx_ciu2_raw_ppx_ip2_mem {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip2_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< LMC* interrupt
+                                                         See LMC*_INT
+                                                         For MEM, all 98 RAW readout will be same value */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip2_mem_s    cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip2_mem_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip2_mem cvmx_ciu2_raw_ppx_ip2_mem_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip2_mio
+ */
+union cvmx_ciu2_raw_ppx_ip2_mio {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip2_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< USB EHCI or OHCI Interrupt
+                                                         See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< USB UCTL* interrupt
+                                                         See UCTL*_INT_REG */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Two UART interrupts
+                                                         See MIO_UARTn_IIR[IID] for bit <34+n> */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< TWSI x Interrupt
+                                                         See MIO_TWSx_INT */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
+                                                         See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt
+                                                         See NDF_INT */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< General timer interrupts
+                                                         Set any time the corresponding CIU timer expires */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt
+                                                         Set any time PIP/IPD drops a packet */
+	uint64_t ssoiq                        : 1;  /**< SSO IQ interrupt
+                                                         See SSO_IQ_INT */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt
+                                                         See IPD_PORT_QOS_INT*
+                                                         For MIO, all 98 RAW readout will be same value */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip2_mio_s    cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip2_mio_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip2_mio cvmx_ciu2_raw_ppx_ip2_mio_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip2_pkt
+ */
+union cvmx_ciu2_raw_ppx_ip2_pkt {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip2_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< ILK Packet Drop interrupt pulse */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupts */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x Interrupts
+                                                         See MIX*_ISR */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX 0-4 packet drop interrupt pulse
+                                                         Set any time corresponding GMX drops a packet */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX 0-4 interrupt
+                                                         See GMX*_RX*_INT_REG, GMX*_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX*_INT_REG
+                                                         For PKT, all 98 RAW readout will be same value */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip2_pkt_s    cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip2_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupts */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x Interrupts
+                                                         See MIX*_ISR */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX 0-4 packet drop interrupt pulse
+                                                         Set any time corresponding GMX drops a packet */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX 0-4 interrupt
+                                                         See GMX*_RX*_INT_REG, GMX*_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX*_INT_REG
+                                                         For PKT, all 98 RAW readout will be same value */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip2_pkt cvmx_ciu2_raw_ppx_ip2_pkt_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip2_rml
+ */
+union cvmx_ciu2_raw_ppx_ip2_rml {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip2_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         See DPI DMA instruction completion */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_INT_ECCERR, TIM_INT0 */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_INT_REG */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt
+                                                         See SSO_ERR */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM
+                                                         For RML, all 98 RAW readout will be same value */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip2_rml_s    cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip2_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_INT_ECCERR, TIM_INT0 */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_INT_REG */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt
+                                                         See SSO_ERR */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM
+                                                         For RML, all 98 RAW readout will be same value */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip2_rml cvmx_ciu2_raw_ppx_ip2_rml_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip2_wdog
+ */
+union cvmx_ciu2_raw_ppx_ip2_wdog {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip2_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< 32 watchdog interrupts
+                                                         For WDOG, all 98 RAW readout will be same value */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip2_wdog_s   cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip2_wdog_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip2_wdog cvmx_ciu2_raw_ppx_ip2_wdog_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip2_wrkq
+ */
+union cvmx_ciu2_raw_ppx_ip2_wrkq {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip2_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< 64 work queue interrupts
+                                                         See SSO_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the SSO.
+                                                          For WRKQ, all 98 RAW readout will be same value */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip2_wrkq_s   cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip2_wrkq_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip2_wrkq cvmx_ciu2_raw_ppx_ip2_wrkq_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip3_gpio
+ */
+union cvmx_ciu2_raw_ppx_ip3_gpio {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip3_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts
+                                                         For GPIO, all 98 RAW readout will be same value */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip3_gpio_s   cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip3_gpio_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip3_gpio cvmx_ciu2_raw_ppx_ip3_gpio_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip3_io
+ */
+union cvmx_ciu2_raw_ppx_ip3_io {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip3_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< PEMx interrupt
+                                                         See PEMx_INT_SUM (enabled by PEMx_INT_ENB) */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< PCI_INTA software enable
+                                                         See CIU_PCI_INTA */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< MSI summary bit, copy of
+                                                         CIU2_MSIRED_PPx_IPy.INT, all IO interrupts
+                                                         CIU2_RAW_IOX_INT_IO[MSIRED] always zero.
+                                                         This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI
+                                                         See SLI_MSI_RCVn for bit <40+n> */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< PCIe INTA/B/C/D
+                                                         PCI_INTR[3] = INTD
+                                                         PCI_INTR[2] = INTC
+                                                         PCI_INTR[1] = INTB
+                                                         PCI_INTR[0] = INTA
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the SLI chapter of the spec
+                                                         For IO, all 98 RAW readout will be different */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip3_io_s     cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip3_io_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip3_io cvmx_ciu2_raw_ppx_ip3_io_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip3_mem
+ */
+union cvmx_ciu2_raw_ppx_ip3_mem {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip3_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< LMC* interrupt
+                                                         See LMC*_INT
+                                                         For MEM, all 98 RAW readout will be same value */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip3_mem_s    cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip3_mem_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip3_mem cvmx_ciu2_raw_ppx_ip3_mem_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip3_mio
+ */
+union cvmx_ciu2_raw_ppx_ip3_mio {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip3_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< USB EHCI or OHCI Interrupt
+                                                         See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< USB UCTL* interrupt
+                                                         See UCTL*_INT_REG */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Two UART interrupts
+                                                         See MIO_UARTn_IIR[IID] for bit <34+n> */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< TWSI x Interrupt
+                                                         See MIO_TWSx_INT */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
+                                                         See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt
+                                                         See NDF_INT */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< General timer interrupts
+                                                         Set any time the corresponding CIU timer expires */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt
+                                                         Set any time PIP/IPD drops a packet */
+	uint64_t ssoiq                        : 1;  /**< SSO IQ interrupt
+                                                         See SSO_IQ_INT */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt
+                                                         See IPD_PORT_QOS_INT*
+                                                         For MIO, all 98 RAW readout will be same value */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip3_mio_s    cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip3_mio_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip3_mio cvmx_ciu2_raw_ppx_ip3_mio_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip3_pkt
+ */
+union cvmx_ciu2_raw_ppx_ip3_pkt {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip3_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< ILK Packet Drop interrupt pulse */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupts */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x Interrupts
+                                                         See MIX*_ISR */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX 0-4 packet drop interrupt pulse
+                                                         Set any time corresponding GMX drops a packet */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX 0-4 interrupt
+                                                         See GMX*_RX*_INT_REG, GMX*_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX*_INT_REG
+                                                         For PKT, all 98 RAW readout will be same value */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip3_pkt_s    cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip3_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupts */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x Interrupts
+                                                         See MIX*_ISR */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX 0-4 packet drop interrupt pulse
+                                                         Set any time corresponding GMX drops a packet */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX 0-4 interrupt
+                                                         See GMX*_RX*_INT_REG, GMX*_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX*_INT_REG
+                                                         For PKT, all 98 RAW readout will be same value */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip3_pkt cvmx_ciu2_raw_ppx_ip3_pkt_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip3_rml
+ */
+union cvmx_ciu2_raw_ppx_ip3_rml {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip3_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         See DPI DMA instruction completion */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_INT_ECCERR, TIM_INT0 */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_INT_REG */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt
+                                                         See SSO_ERR */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM
+                                                         For RML, all 98 RAW readout will be same value */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip3_rml_s    cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip3_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_INT_ECCERR, TIM_INT0 */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_INT_REG */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt
+                                                         See SSO_ERR */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM
+                                                         For RML, all 98 RAW readout will be same value */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip3_rml cvmx_ciu2_raw_ppx_ip3_rml_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip3_wdog
+ */
+union cvmx_ciu2_raw_ppx_ip3_wdog {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip3_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< 32 watchdog interrupts
+                                                         For WDOG, all 98 RAW readout will be same value */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip3_wdog_s   cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip3_wdog_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip3_wdog cvmx_ciu2_raw_ppx_ip3_wdog_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip3_wrkq
+ */
+union cvmx_ciu2_raw_ppx_ip3_wrkq {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip3_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< 64 work queue interrupts
+                                                         See SSO_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the SSO.
+                                                          For WRKQ, all 98 RAW readout will be same value */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip3_wrkq_s   cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip3_wrkq_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip3_wrkq cvmx_ciu2_raw_ppx_ip3_wrkq_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip4_gpio
+ */
+union cvmx_ciu2_raw_ppx_ip4_gpio {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip4_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts
+                                                         For GPIO, all 98 RAW readout will be same value */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip4_gpio_s   cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip4_gpio_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip4_gpio cvmx_ciu2_raw_ppx_ip4_gpio_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip4_io
+ */
+union cvmx_ciu2_raw_ppx_ip4_io {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip4_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< PEMx interrupt
+                                                         See PEMx_INT_SUM (enabled by PEMx_INT_ENB) */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< PCI_INTA software enable
+                                                         See CIU_PCI_INTA */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< MSI summary bit, copy of
+                                                         CIU2_MSIRED_PPx_IPy.INT, all IO interrupts
+                                                         CIU2_RAW_IOX_INT_IO[MSIRED] always zero.
+                                                         This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI
+                                                         See SLI_MSI_RCVn for bit <40+n> */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< PCIe INTA/B/C/D
+                                                         PCI_INTR[3] = INTD
+                                                         PCI_INTR[2] = INTC
+                                                         PCI_INTR[1] = INTB
+                                                         PCI_INTR[0] = INTA
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the SLI chapter of the spec
+                                                         For IO, all 98 RAW readout will be different */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip4_io_s     cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip4_io_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip4_io cvmx_ciu2_raw_ppx_ip4_io_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip4_mem
+ */
+union cvmx_ciu2_raw_ppx_ip4_mem {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip4_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< LMC* interrupt
+                                                         See LMC*_INT
+                                                         For MEM, all 98 RAW readout will be same value */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip4_mem_s    cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip4_mem_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip4_mem cvmx_ciu2_raw_ppx_ip4_mem_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip4_mio
+ */
+union cvmx_ciu2_raw_ppx_ip4_mio {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip4_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< USB EHCI or OHCI Interrupt
+                                                         See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< USB UCTL* interrupt
+                                                         See UCTL*_INT_REG */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Two UART interrupts
+                                                         See MIO_UARTn_IIR[IID] for bit <34+n> */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< TWSI x Interrupt
+                                                         See MIO_TWSx_INT */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
+                                                         See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt
+                                                         See NDF_INT */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< General timer interrupts
+                                                         Set any time the corresponding CIU timer expires */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt
+                                                         Set any time PIP/IPD drops a packet */
+	uint64_t ssoiq                        : 1;  /**< SSO IQ interrupt
+                                                         See SSO_IQ_INT */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt
+                                                         See IPD_PORT_QOS_INT*
+                                                         For MIO, all 98 RAW readout will be same value */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip4_mio_s    cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip4_mio_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip4_mio cvmx_ciu2_raw_ppx_ip4_mio_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip4_pkt
+ */
+union cvmx_ciu2_raw_ppx_ip4_pkt {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip4_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< ILK Packet Drop interrupt pulse */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupts */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x Interrupts
+                                                         See MIX*_ISR */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX 0-4 packet drop interrupt pulse
+                                                         Set any time corresponding GMX drops a packet */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX 0-4 interrupt
+                                                         See GMX*_RX*_INT_REG, GMX*_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX*_INT_REG
+                                                         For PKT, all 98 RAW readout will be same value */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip4_pkt_s    cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip4_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupts */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x Interrupts
+                                                         See MIX*_ISR */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX 0-4 packet drop interrupt pulse
+                                                         Set any time corresponding GMX drops a packet */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX 0-4 interrupt
+                                                         See GMX*_RX*_INT_REG, GMX*_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX*_INT_REG
+                                                         For PKT, all 98 RAW readout will be same value */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip4_pkt cvmx_ciu2_raw_ppx_ip4_pkt_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip4_rml
+ */
+union cvmx_ciu2_raw_ppx_ip4_rml {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip4_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         See DPI DMA instruction completion */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_INT_ECCERR, TIM_INT0 */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_INT_REG */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt
+                                                         See SSO_ERR */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM
+                                                         For RML, all 98 RAW readout will be same value */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip4_rml_s    cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip4_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_INT_ECCERR, TIM_INT0 */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_INT_REG */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt
+                                                         See SSO_ERR */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM
+                                                         For RML, all 98 RAW readout will be same value */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip4_rml cvmx_ciu2_raw_ppx_ip4_rml_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip4_wdog
+ */
+union cvmx_ciu2_raw_ppx_ip4_wdog {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip4_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< 32 watchdog interrupts
+                                                         For WDOG, all 98 RAW readout will be same value */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip4_wdog_s   cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip4_wdog_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip4_wdog cvmx_ciu2_raw_ppx_ip4_wdog_t;
+
+/**
+ * cvmx_ciu2_raw_pp#_ip4_wrkq
+ */
+union cvmx_ciu2_raw_ppx_ip4_wrkq {
+	uint64_t u64;
+	struct cvmx_ciu2_raw_ppx_ip4_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< 64 work queue interrupts
+                                                         See SSO_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the SSO.
+                                                          For WRKQ, all 98 RAW readout will be same value */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_raw_ppx_ip4_wrkq_s   cn68xx;
+	struct cvmx_ciu2_raw_ppx_ip4_wrkq_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_raw_ppx_ip4_wrkq cvmx_ciu2_raw_ppx_ip4_wrkq_t;
+
+/**
+ * cvmx_ciu2_src_io#_int_gpio
+ */
+union cvmx_ciu2_src_iox_int_gpio {
+	uint64_t u64;
+	struct cvmx_ciu2_src_iox_int_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts source */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_src_iox_int_gpio_s   cn68xx;
+	struct cvmx_ciu2_src_iox_int_gpio_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_src_iox_int_gpio cvmx_ciu2_src_iox_int_gpio_t;
+
+/**
+ * cvmx_ciu2_src_io#_int_io
+ */
+union cvmx_ciu2_src_iox_int_io {
+	uint64_t u64;
+	struct cvmx_ciu2_src_iox_int_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< PEMx interrupt source
+                                                         CIU2_RAW_IO[PEM] & CIU2_EN_xx_yy_IO[PEM] */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< PCI_INTA source
+                                                         CIU2_RAW_IO[PCI_INTA] & CIU2_EN_xx_yy_IO[PCI_INTA] */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< MSI summary bit source
+                                                         CIU2_RAW_IO[MSIRED] & CIU2_EN_xx_yy_IO[MSIRED]
+                                                          This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI source
+                                                         CIU2_RAW_IO[PCI_MSI] & CIU2_EN_xx_yy_IO[PCI_MSI] */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< PCIe INTA/B/C/D interrupt source
+                                                         CIU2_RAW_IO[PCI_INTR] &CIU2_EN_xx_yy_IO[PCI_INTR] */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_src_iox_int_io_s     cn68xx;
+	struct cvmx_ciu2_src_iox_int_io_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_src_iox_int_io cvmx_ciu2_src_iox_int_io_t;
+
+/**
+ * cvmx_ciu2_src_io#_int_mbox
+ */
+union cvmx_ciu2_src_iox_int_mbox {
+	uint64_t u64;
+	struct cvmx_ciu2_src_iox_int_mbox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t mbox                         : 4;  /**< Mailbox interrupt Source (RAW & ENABLE)
+                                                         For CIU2_SRC_PPX_IPx_MBOX:
+                                                         Four mailbox interrupts for entries 0-31
+                                                         RAW & ENABLE
+                                                          [3]  is the or of <31:24> of CIU2_MBOX
+                                                          [2]  is the or of <23:16> of CIU2_MBOX
+                                                          [1]  is the or of <15:8> of CIU2_MBOX
+                                                          [0]  is the or of <7:0> of CIU2_MBOX
+                                                          CIU2_MBOX value can be read out via CSR address
+                                                          CIU_MBOX_SET/CLR
+                                                         For CIU2_SRC_IOX_INT_MBOX:
+                                                           always zero */
+#else
+	uint64_t mbox                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_src_iox_int_mbox_s   cn68xx;
+	struct cvmx_ciu2_src_iox_int_mbox_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_src_iox_int_mbox cvmx_ciu2_src_iox_int_mbox_t;
+
+/**
+ * cvmx_ciu2_src_io#_int_mem
+ */
+union cvmx_ciu2_src_iox_int_mem {
+	uint64_t u64;
+	struct cvmx_ciu2_src_iox_int_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< LMC* interrupt source
+                                                         CIU2_RAW_MEM[LMC] & CIU2_EN_xx_yy_MEM[LMC] */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_src_iox_int_mem_s    cn68xx;
+	struct cvmx_ciu2_src_iox_int_mem_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_src_iox_int_mem cvmx_ciu2_src_iox_int_mem_t;
+
+/**
+ * cvmx_ciu2_src_io#_int_mio
+ */
+union cvmx_ciu2_src_iox_int_mio {
+	uint64_t u64;
+	struct cvmx_ciu2_src_iox_int_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt source
+                                                         CIU2_RAW_MIO[RST] & CIU2_EN_xx_yy_MIO[RST] */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< PTP interrupt source
+                                                         CIU2_RAW_MIO[PTP] & CIU2_EN_xx_yy_MIO[PTP] */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< USB HCI Interrupt source
+                                                         CIU2_RAW_MIO[USB_HCI] & CIU2_EN_xx_yy_MIO[USB_HCI] */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< USB UCTL* interrupt source
+                                                         CIU2_RAW_MIO[USB_UCTL] &CIU2_EN_xx_yy_MIO[USB_UCTL] */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Two UART interrupts source
+                                                         CIU2_RAW_MIO[UART] & CIU2_EN_xx_yy_MIO[UART] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< TWSI x Interrupt source
+                                                         CIU2_RAW_MIO[TWSI] & CIU2_EN_xx_yy_MIO[TWSI] */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt source
+                                                         CIU2_RAW_MIO[BOOTDMA] & CIU2_EN_xx_yy_MIO[BOOTDMA] */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt source
+                                                         CIU2_RAW_MIO[MIO] & CIU2_EN_xx_yy_MIO[MIO] */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt source
+                                                         CIU2_RAW_MIO[NAND] & CIU2_EN_xx_yy_MIO[NANAD] */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< General timer interrupts source
+                                                         CIU2_RAW_MIO[TIMER] & CIU2_EN_xx_yy_MIO[TIMER] */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt source
+                                                         CIU2_RAW_MIO[IPD_DRP] & CIU2_EN_xx_yy_MIO[IPD_DRP] */
+	uint64_t ssoiq                        : 1;  /**< SSO IQ interrupt source
+                                                         CIU2_RAW_MIO[SSOIQ] & CIU2_EN_xx_yy_MIO[SSOIQ] */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port cnt threshold interrupt source
+                                                         CIU2_RAW_MIO[IPDPPTHR] &CIU2_EN_xx_yy_MIO[IPDPPTHR] */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_src_iox_int_mio_s    cn68xx;
+	struct cvmx_ciu2_src_iox_int_mio_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_src_iox_int_mio cvmx_ciu2_src_iox_int_mio_t;
+
+/**
+ * cvmx_ciu2_src_io#_int_pkt
+ */
+union cvmx_ciu2_src_iox_int_pkt {
+	uint64_t u64;
+	struct cvmx_ciu2_src_iox_int_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< ILK Packet Drop interrupts source
+                                                         CIU2_RAW_PKT[ILK_DRP] & CIU2_EN_xx_yy_PKT[ILK_DRP] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupts source
+                                                         CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x Interrupts source
+                                                         CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt source
+                                                         CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX packet drop interrupt, RAW & ENABLE
+                                                         CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX interrupt source
+                                                         CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_src_iox_int_pkt_s    cn68xx;
+	struct cvmx_ciu2_src_iox_int_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupts source
+                                                         CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x Interrupts source
+                                                         CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt source
+                                                         CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX packet drop interrupt, RAW & ENABLE
+                                                         CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX interrupt source
+                                                         CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_src_iox_int_pkt cvmx_ciu2_src_iox_int_pkt_t;
+
+/**
+ * cvmx_ciu2_src_io#_int_rml
+ */
+union cvmx_ciu2_src_iox_int_rml {
+	uint64_t u64;
+	struct cvmx_ciu2_src_iox_int_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt source
+                                                         CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt source
+                                                         CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt source
+                                                         CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         See DPI DMA instruction completion */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< DPI interrupt source
+                                                         CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< SLI interrupt source
+                                                         CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt source
+                                                         CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< RAD interrupt source
+                                                         CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< TIM interrupt source
+                                                         CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt source
+                                                         CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt source
+                                                         CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt source
+                                                         CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< PIP interrupt source
+                                                         CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< IPD interrupt source
+                                                         CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< FPA interrupt source
+                                                         CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt source
+                                                         CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_src_iox_int_rml_s    cn68xx;
+	struct cvmx_ciu2_src_iox_int_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt source
+                                                         CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt source
+                                                         CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt source
+                                                         CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< DPI interrupt source
+                                                         CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< SLI interrupt source
+                                                         CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt source
+                                                         CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< RAD interrupt source
+                                                         CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< TIM interrupt source
+                                                         CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt source
+                                                         CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt source
+                                                         CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt source
+                                                         CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< PIP interrupt source
+                                                         CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< IPD interrupt source
+                                                         CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< FPA interrupt source
+                                                         CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt source
+                                                         CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_src_iox_int_rml cvmx_ciu2_src_iox_int_rml_t;
+
+/**
+ * cvmx_ciu2_src_io#_int_wdog
+ */
+union cvmx_ciu2_src_iox_int_wdog {
+	uint64_t u64;
+	struct cvmx_ciu2_src_iox_int_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< 32 watchdog interrupts source
+                                                         CIU2_RAW_WDOG & CIU2_EN_xx_yy_WDOG */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_src_iox_int_wdog_s   cn68xx;
+	struct cvmx_ciu2_src_iox_int_wdog_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_src_iox_int_wdog cvmx_ciu2_src_iox_int_wdog_t;
+
+/**
+ * cvmx_ciu2_src_io#_int_wrkq
+ */
+union cvmx_ciu2_src_iox_int_wrkq {
+	uint64_t u64;
+	struct cvmx_ciu2_src_iox_int_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< 64 work queue intr source,
+                                                         CIU2_RAW_WRKQ & CIU2_EN_xx_yy_WRKQ */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_src_iox_int_wrkq_s   cn68xx;
+	struct cvmx_ciu2_src_iox_int_wrkq_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_src_iox_int_wrkq cvmx_ciu2_src_iox_int_wrkq_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip2_gpio
+ */
+union cvmx_ciu2_src_ppx_ip2_gpio {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip2_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts source */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip2_gpio_s   cn68xx;
+	struct cvmx_ciu2_src_ppx_ip2_gpio_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip2_gpio cvmx_ciu2_src_ppx_ip2_gpio_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip2_io
+ */
+union cvmx_ciu2_src_ppx_ip2_io {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip2_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< PEMx interrupt source
+                                                         CIU2_RAW_IO[PEM] & CIU2_EN_xx_yy_IO[PEM] */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< PCI_INTA source
+                                                         CIU2_RAW_IO[PCI_INTA] & CIU2_EN_xx_yy_IO[PCI_INTA] */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< MSI summary bit source
+                                                         CIU2_RAW_IO[MSIRED] & CIU2_EN_xx_yy_IO[MSIRED]
+                                                          This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI source
+                                                         CIU2_RAW_IO[PCI_MSI] & CIU2_EN_xx_yy_IO[PCI_MSI] */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< PCIe INTA/B/C/D interrupt source
+                                                         CIU2_RAW_IO[PCI_INTR] &CIU2_EN_xx_yy_IO[PCI_INTR] */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip2_io_s     cn68xx;
+	struct cvmx_ciu2_src_ppx_ip2_io_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip2_io cvmx_ciu2_src_ppx_ip2_io_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip2_mbox
+ */
+union cvmx_ciu2_src_ppx_ip2_mbox {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip2_mbox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t mbox                         : 4;  /**< Mailbox interrupt Source (RAW & ENABLE)
+                                                         For CIU2_SRC_PPX_IPx_MBOX:
+                                                         Four mailbox interrupts for entries 0-31
+                                                         RAW & ENABLE
+                                                          [3]  is the or of <31:24> of CIU2_MBOX
+                                                          [2]  is the or of <23:16> of CIU2_MBOX
+                                                          [1]  is the or of <15:8> of CIU2_MBOX
+                                                          [0]  is the or of <7:0> of CIU2_MBOX
+                                                          CIU2_MBOX value can be read out via CSR address
+                                                          CIU_MBOX_SET/CLR
+                                                         For CIU2_SRC_IOX_INT_MBOX:
+                                                           always zero */
+#else
+	uint64_t mbox                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip2_mbox_s   cn68xx;
+	struct cvmx_ciu2_src_ppx_ip2_mbox_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip2_mbox cvmx_ciu2_src_ppx_ip2_mbox_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip2_mem
+ */
+union cvmx_ciu2_src_ppx_ip2_mem {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip2_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< LMC* interrupt source
+                                                         CIU2_RAW_MEM[LMC] & CIU2_EN_xx_yy_MEM[LMC] */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip2_mem_s    cn68xx;
+	struct cvmx_ciu2_src_ppx_ip2_mem_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip2_mem cvmx_ciu2_src_ppx_ip2_mem_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip2_mio
+ */
+union cvmx_ciu2_src_ppx_ip2_mio {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip2_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt source
+                                                         CIU2_RAW_MIO[RST] & CIU2_EN_xx_yy_MIO[RST] */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< PTP interrupt source
+                                                         CIU2_RAW_MIO[PTP] & CIU2_EN_xx_yy_MIO[PTP] */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< USB HCI Interrupt source
+                                                         CIU2_RAW_MIO[USB_HCI] & CIU2_EN_xx_yy_MIO[USB_HCI] */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< USB UCTL* interrupt source
+                                                         CIU2_RAW_MIO[USB_UCTL] &CIU2_EN_xx_yy_MIO[USB_UCTL] */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Two UART interrupts source
+                                                         CIU2_RAW_MIO[UART] & CIU2_EN_xx_yy_MIO[UART] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< TWSI x Interrupt source
+                                                         CIU2_RAW_MIO[TWSI] & CIU2_EN_xx_yy_MIO[TWSI] */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt source
+                                                         CIU2_RAW_MIO[BOOTDMA] & CIU2_EN_xx_yy_MIO[BOOTDMA] */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt source
+                                                         CIU2_RAW_MIO[MIO] & CIU2_EN_xx_yy_MIO[MIO] */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt source
+                                                         CIU2_RAW_MIO[NAND] & CIU2_EN_xx_yy_MIO[NANAD] */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< General timer interrupts source
+                                                         CIU2_RAW_MIO[TIMER] & CIU2_EN_xx_yy_MIO[TIMER] */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt source
+                                                         CIU2_RAW_MIO[IPD_DRP] & CIU2_EN_xx_yy_MIO[IPD_DRP] */
+	uint64_t ssoiq                        : 1;  /**< SSO IQ interrupt source
+                                                         CIU2_RAW_MIO[SSOIQ] & CIU2_EN_xx_yy_MIO[SSOIQ] */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port cnt threshold interrupt source
+                                                         CIU2_RAW_MIO[IPDPPTHR] &CIU2_EN_xx_yy_MIO[IPDPPTHR] */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip2_mio_s    cn68xx;
+	struct cvmx_ciu2_src_ppx_ip2_mio_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip2_mio cvmx_ciu2_src_ppx_ip2_mio_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip2_pkt
+ */
+union cvmx_ciu2_src_ppx_ip2_pkt {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip2_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< ILK Packet Drop interrupts source
+                                                         CIU2_RAW_PKT[ILK_DRP] & CIU2_EN_xx_yy_PKT[ILK_DRP] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupts source
+                                                         CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x Interrupts source
+                                                         CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt source
+                                                         CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX packet drop interrupt, RAW & ENABLE
+                                                         CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX interrupt source
+                                                         CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip2_pkt_s    cn68xx;
+	struct cvmx_ciu2_src_ppx_ip2_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupts source
+                                                         CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x Interrupts source
+                                                         CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt source
+                                                         CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX packet drop interrupt, RAW & ENABLE
+                                                         CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX interrupt source
+                                                         CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip2_pkt cvmx_ciu2_src_ppx_ip2_pkt_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip2_rml
+ */
+union cvmx_ciu2_src_ppx_ip2_rml {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip2_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt source
+                                                         CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt source
+                                                         CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt source
+                                                         CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         See DPI DMA instruction completion */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< DPI interrupt source
+                                                         CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< SLI interrupt source
+                                                         CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt source
+                                                         CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< RAD interrupt source
+                                                         CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< TIM interrupt source
+                                                         CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt source
+                                                         CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt source
+                                                         CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt source
+                                                         CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< PIP interrupt source
+                                                         CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< IPD interrupt source
+                                                         CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< FPA interrupt source
+                                                         CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt source
+                                                         CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip2_rml_s    cn68xx;
+	struct cvmx_ciu2_src_ppx_ip2_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt source
+                                                         CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt source
+                                                         CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt source
+                                                         CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< DPI interrupt source
+                                                         CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< SLI interrupt source
+                                                         CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt source
+                                                         CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< RAD interrupt source
+                                                         CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< TIM interrupt source
+                                                         CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt source
+                                                         CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt source
+                                                         CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt source
+                                                         CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< PIP interrupt source
+                                                         CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< IPD interrupt source
+                                                         CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< FPA interrupt source
+                                                         CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt source
+                                                         CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip2_rml cvmx_ciu2_src_ppx_ip2_rml_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip2_wdog
+ */
+union cvmx_ciu2_src_ppx_ip2_wdog {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip2_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< 32 watchdog interrupts source
+                                                         CIU2_RAW_WDOG & CIU2_EN_xx_yy_WDOG */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip2_wdog_s   cn68xx;
+	struct cvmx_ciu2_src_ppx_ip2_wdog_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip2_wdog cvmx_ciu2_src_ppx_ip2_wdog_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip2_wrkq
+ *
+ * All SRC values is generated by AND Raw value (CIU2_RAW_XXX) with CIU2_EN_PPX_IPx_XXX
+ *
+ */
+union cvmx_ciu2_src_ppx_ip2_wrkq {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip2_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< 64 work queue intr source,
+                                                         CIU2_RAW_WRKQ & CIU2_EN_xx_yy_WRKQ */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip2_wrkq_s   cn68xx;
+	struct cvmx_ciu2_src_ppx_ip2_wrkq_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip2_wrkq cvmx_ciu2_src_ppx_ip2_wrkq_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip3_gpio
+ */
+union cvmx_ciu2_src_ppx_ip3_gpio {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip3_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts source */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip3_gpio_s   cn68xx;
+	struct cvmx_ciu2_src_ppx_ip3_gpio_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip3_gpio cvmx_ciu2_src_ppx_ip3_gpio_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip3_io
+ */
+union cvmx_ciu2_src_ppx_ip3_io {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip3_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< PEMx interrupt source
+                                                         CIU2_RAW_IO[PEM] & CIU2_EN_xx_yy_IO[PEM] */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< PCI_INTA source
+                                                         CIU2_RAW_IO[PCI_INTA] & CIU2_EN_xx_yy_IO[PCI_INTA] */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< MSI summary bit source
+                                                         CIU2_RAW_IO[MSIRED] & CIU2_EN_xx_yy_IO[MSIRED]
+                                                          This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI source
+                                                         CIU2_RAW_IO[PCI_MSI] & CIU2_EN_xx_yy_IO[PCI_MSI] */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< PCIe INTA/B/C/D interrupt source
+                                                         CIU2_RAW_IO[PCI_INTR] &CIU2_EN_xx_yy_IO[PCI_INTR] */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip3_io_s     cn68xx;
+	struct cvmx_ciu2_src_ppx_ip3_io_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip3_io cvmx_ciu2_src_ppx_ip3_io_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip3_mbox
+ */
+union cvmx_ciu2_src_ppx_ip3_mbox {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip3_mbox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t mbox                         : 4;  /**< Mailbox interrupt Source (RAW & ENABLE)
+                                                         For CIU2_SRC_PPX_IPx_MBOX:
+                                                         Four mailbox interrupts for entries 0-31
+                                                         RAW & ENABLE
+                                                          [3]  is the or of <31:24> of CIU2_MBOX
+                                                          [2]  is the or of <23:16> of CIU2_MBOX
+                                                          [1]  is the or of <15:8> of CIU2_MBOX
+                                                          [0]  is the or of <7:0> of CIU2_MBOX
+                                                          CIU2_MBOX value can be read out via CSR address
+                                                          CIU_MBOX_SET/CLR
+                                                         For CIU2_SRC_IOX_INT_MBOX:
+                                                           always zero */
+#else
+	uint64_t mbox                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip3_mbox_s   cn68xx;
+	struct cvmx_ciu2_src_ppx_ip3_mbox_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip3_mbox cvmx_ciu2_src_ppx_ip3_mbox_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip3_mem
+ */
+union cvmx_ciu2_src_ppx_ip3_mem {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip3_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< LMC* interrupt source
+                                                         CIU2_RAW_MEM[LMC] & CIU2_EN_xx_yy_MEM[LMC] */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip3_mem_s    cn68xx;
+	struct cvmx_ciu2_src_ppx_ip3_mem_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip3_mem cvmx_ciu2_src_ppx_ip3_mem_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip3_mio
+ */
+union cvmx_ciu2_src_ppx_ip3_mio {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip3_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt source
+                                                         CIU2_RAW_MIO[RST] & CIU2_EN_xx_yy_MIO[RST] */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< PTP interrupt source
+                                                         CIU2_RAW_MIO[PTP] & CIU2_EN_xx_yy_MIO[PTP] */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< USB HCI Interrupt source
+                                                         CIU2_RAW_MIO[USB_HCI] & CIU2_EN_xx_yy_MIO[USB_HCI] */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< USB UCTL* interrupt source
+                                                         CIU2_RAW_MIO[USB_UCTL] &CIU2_EN_xx_yy_MIO[USB_UCTL] */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Two UART interrupts source
+                                                         CIU2_RAW_MIO[UART] & CIU2_EN_xx_yy_MIO[UART] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< TWSI x Interrupt source
+                                                         CIU2_RAW_MIO[TWSI] & CIU2_EN_xx_yy_MIO[TWSI] */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt source
+                                                         CIU2_RAW_MIO[BOOTDMA] & CIU2_EN_xx_yy_MIO[BOOTDMA] */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt source
+                                                         CIU2_RAW_MIO[MIO] & CIU2_EN_xx_yy_MIO[MIO] */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt source
+                                                         CIU2_RAW_MIO[NAND] & CIU2_EN_xx_yy_MIO[NANAD] */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< General timer interrupts source
+                                                         CIU2_RAW_MIO[TIMER] & CIU2_EN_xx_yy_MIO[TIMER] */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt source
+                                                         CIU2_RAW_MIO[IPD_DRP] & CIU2_EN_xx_yy_MIO[IPD_DRP] */
+	uint64_t ssoiq                        : 1;  /**< SSO IQ interrupt source
+                                                         CIU2_RAW_MIO[SSOIQ] & CIU2_EN_xx_yy_MIO[SSOIQ] */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port cnt threshold interrupt source
+                                                         CIU2_RAW_MIO[IPDPPTHR] &CIU2_EN_xx_yy_MIO[IPDPPTHR] */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip3_mio_s    cn68xx;
+	struct cvmx_ciu2_src_ppx_ip3_mio_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip3_mio cvmx_ciu2_src_ppx_ip3_mio_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip3_pkt
+ */
+union cvmx_ciu2_src_ppx_ip3_pkt {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip3_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< ILK Packet Drop interrupts source
+                                                         CIU2_RAW_PKT[ILK_DRP] & CIU2_EN_xx_yy_PKT[ILK_DRP] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupts source
+                                                         CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x Interrupts source
+                                                         CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt source
+                                                         CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX packet drop interrupt, RAW & ENABLE
+                                                         CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX interrupt source
+                                                         CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip3_pkt_s    cn68xx;
+	struct cvmx_ciu2_src_ppx_ip3_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupts source
+                                                         CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x Interrupts source
+                                                         CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt source
+                                                         CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX packet drop interrupt, RAW & ENABLE
+                                                         CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX interrupt source
+                                                         CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip3_pkt cvmx_ciu2_src_ppx_ip3_pkt_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip3_rml
+ */
+union cvmx_ciu2_src_ppx_ip3_rml {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip3_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt source
+                                                         CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt source
+                                                         CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt source
+                                                         CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         See DPI DMA instruction completion */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< DPI interrupt source
+                                                         CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< SLI interrupt source
+                                                         CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt source
+                                                         CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< RAD interrupt source
+                                                         CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< TIM interrupt source
+                                                         CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt source
+                                                         CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt source
+                                                         CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt source
+                                                         CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< PIP interrupt source
+                                                         CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< IPD interrupt source
+                                                         CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< FPA interrupt source
+                                                         CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt source
+                                                         CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip3_rml_s    cn68xx;
+	struct cvmx_ciu2_src_ppx_ip3_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt source
+                                                         CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt source
+                                                         CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt source
+                                                         CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< DPI interrupt source
+                                                         CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< SLI interrupt source
+                                                         CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt source
+                                                         CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< RAD interrupt source
+                                                         CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< TIM interrupt source
+                                                         CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt source
+                                                         CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt source
+                                                         CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt source
+                                                         CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< PIP interrupt source
+                                                         CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< IPD interrupt source
+                                                         CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< FPA interrupt source
+                                                         CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt source
+                                                         CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip3_rml cvmx_ciu2_src_ppx_ip3_rml_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip3_wdog
+ */
+union cvmx_ciu2_src_ppx_ip3_wdog {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip3_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< 32 watchdog interrupts source
+                                                         CIU2_RAW_WDOG & CIU2_EN_xx_yy_WDOG */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip3_wdog_s   cn68xx;
+	struct cvmx_ciu2_src_ppx_ip3_wdog_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip3_wdog cvmx_ciu2_src_ppx_ip3_wdog_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip3_wrkq
+ */
+union cvmx_ciu2_src_ppx_ip3_wrkq {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip3_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< 64 work queue intr source,
+                                                         CIU2_RAW_WRKQ & CIU2_EN_xx_yy_WRKQ */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip3_wrkq_s   cn68xx;
+	struct cvmx_ciu2_src_ppx_ip3_wrkq_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip3_wrkq cvmx_ciu2_src_ppx_ip3_wrkq_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip4_gpio
+ */
+union cvmx_ciu2_src_ppx_ip4_gpio {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip4_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts source */
+#else
+	uint64_t gpio                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip4_gpio_s   cn68xx;
+	struct cvmx_ciu2_src_ppx_ip4_gpio_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip4_gpio cvmx_ciu2_src_ppx_ip4_gpio_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip4_io
+ */
+union cvmx_ciu2_src_ppx_ip4_io {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip4_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t pem                          : 2;  /**< PEMx interrupt source
+                                                         CIU2_RAW_IO[PEM] & CIU2_EN_xx_yy_IO[PEM] */
+	uint64_t reserved_18_31               : 14;
+	uint64_t pci_inta                     : 2;  /**< PCI_INTA source
+                                                         CIU2_RAW_IO[PCI_INTA] & CIU2_EN_xx_yy_IO[PCI_INTA] */
+	uint64_t reserved_13_15               : 3;
+	uint64_t msired                       : 1;  /**< MSI summary bit source
+                                                         CIU2_RAW_IO[MSIRED] & CIU2_EN_xx_yy_IO[MSIRED]
+                                                          This bit may not be functional in pass 1. */
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI source
+                                                         CIU2_RAW_IO[PCI_MSI] & CIU2_EN_xx_yy_IO[PCI_MSI] */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_intr                     : 4;  /**< PCIe INTA/B/C/D interrupt source
+                                                         CIU2_RAW_IO[PCI_INTR] &CIU2_EN_xx_yy_IO[PCI_INTR] */
+#else
+	uint64_t pci_intr                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t msired                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t pci_inta                     : 2;
+	uint64_t reserved_18_31               : 14;
+	uint64_t pem                          : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip4_io_s     cn68xx;
+	struct cvmx_ciu2_src_ppx_ip4_io_s     cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip4_io cvmx_ciu2_src_ppx_ip4_io_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip4_mbox
+ */
+union cvmx_ciu2_src_ppx_ip4_mbox {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip4_mbox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t mbox                         : 4;  /**< Mailbox interrupt Source (RAW & ENABLE)
+                                                         For CIU2_SRC_PPX_IPx_MBOX:
+                                                         Four mailbox interrupts for entries 0-31
+                                                         RAW & ENABLE
+                                                          [3]  is the or of <31:24> of CIU2_MBOX
+                                                          [2]  is the or of <23:16> of CIU2_MBOX
+                                                          [1]  is the or of <15:8> of CIU2_MBOX
+                                                          [0]  is the or of <7:0> of CIU2_MBOX
+                                                          CIU2_MBOX value can be read out via CSR address
+                                                          CIU_MBOX_SET/CLR
+                                                         For CIU2_SRC_IOX_INT_MBOX:
+                                                           always zero */
+#else
+	uint64_t mbox                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip4_mbox_s   cn68xx;
+	struct cvmx_ciu2_src_ppx_ip4_mbox_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip4_mbox cvmx_ciu2_src_ppx_ip4_mbox_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip4_mem
+ */
+union cvmx_ciu2_src_ppx_ip4_mem {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip4_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t lmc                          : 4;  /**< LMC* interrupt source
+                                                         CIU2_RAW_MEM[LMC] & CIU2_EN_xx_yy_MEM[LMC] */
+#else
+	uint64_t lmc                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip4_mem_s    cn68xx;
+	struct cvmx_ciu2_src_ppx_ip4_mem_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip4_mem cvmx_ciu2_src_ppx_ip4_mem_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip4_mio
+ */
+union cvmx_ciu2_src_ppx_ip4_mio {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip4_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rst                          : 1;  /**< MIO RST interrupt source
+                                                         CIU2_RAW_MIO[RST] & CIU2_EN_xx_yy_MIO[RST] */
+	uint64_t reserved_49_62               : 14;
+	uint64_t ptp                          : 1;  /**< PTP interrupt source
+                                                         CIU2_RAW_MIO[PTP] & CIU2_EN_xx_yy_MIO[PTP] */
+	uint64_t reserved_45_47               : 3;
+	uint64_t usb_hci                      : 1;  /**< USB HCI Interrupt source
+                                                         CIU2_RAW_MIO[USB_HCI] & CIU2_EN_xx_yy_MIO[USB_HCI] */
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_uctl                     : 1;  /**< USB UCTL* interrupt source
+                                                         CIU2_RAW_MIO[USB_UCTL] &CIU2_EN_xx_yy_MIO[USB_UCTL] */
+	uint64_t reserved_38_39               : 2;
+	uint64_t uart                         : 2;  /**< Two UART interrupts source
+                                                         CIU2_RAW_MIO[UART] & CIU2_EN_xx_yy_MIO[UART] */
+	uint64_t reserved_34_35               : 2;
+	uint64_t twsi                         : 2;  /**< TWSI x Interrupt source
+                                                         CIU2_RAW_MIO[TWSI] & CIU2_EN_xx_yy_MIO[TWSI] */
+	uint64_t reserved_19_31               : 13;
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt source
+                                                         CIU2_RAW_MIO[BOOTDMA] & CIU2_EN_xx_yy_MIO[BOOTDMA] */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt source
+                                                         CIU2_RAW_MIO[MIO] & CIU2_EN_xx_yy_MIO[MIO] */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt source
+                                                         CIU2_RAW_MIO[NAND] & CIU2_EN_xx_yy_MIO[NANAD] */
+	uint64_t reserved_12_15               : 4;
+	uint64_t timer                        : 4;  /**< General timer interrupts source
+                                                         CIU2_RAW_MIO[TIMER] & CIU2_EN_xx_yy_MIO[TIMER] */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt source
+                                                         CIU2_RAW_MIO[IPD_DRP] & CIU2_EN_xx_yy_MIO[IPD_DRP] */
+	uint64_t ssoiq                        : 1;  /**< SSO IQ interrupt source
+                                                         CIU2_RAW_MIO[SSOIQ] & CIU2_EN_xx_yy_MIO[SSOIQ] */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port cnt threshold interrupt source
+                                                         CIU2_RAW_MIO[IPDPPTHR] &CIU2_EN_xx_yy_MIO[IPDPPTHR] */
+#else
+	uint64_t ipdppthr                     : 1;
+	uint64_t ssoiq                        : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t timer                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t bootdma                      : 1;
+	uint64_t reserved_19_31               : 13;
+	uint64_t twsi                         : 2;
+	uint64_t reserved_34_35               : 2;
+	uint64_t uart                         : 2;
+	uint64_t reserved_38_39               : 2;
+	uint64_t usb_uctl                     : 1;
+	uint64_t reserved_41_43               : 3;
+	uint64_t usb_hci                      : 1;
+	uint64_t reserved_45_47               : 3;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_49_62               : 14;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip4_mio_s    cn68xx;
+	struct cvmx_ciu2_src_ppx_ip4_mio_s    cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip4_mio cvmx_ciu2_src_ppx_ip4_mio_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip4_pkt
+ */
+union cvmx_ciu2_src_ppx_ip4_pkt {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip4_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t ilk_drp                      : 2;  /**< ILK Packet Drop interrupts source
+                                                         CIU2_RAW_PKT[ILK_DRP] & CIU2_EN_xx_yy_PKT[ILK_DRP] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupts source
+                                                         CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x Interrupts source
+                                                         CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt source
+                                                         CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX packet drop interrupt, RAW & ENABLE
+                                                         CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX interrupt source
+                                                         CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t ilk_drp                      : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip4_pkt_s    cn68xx;
+	struct cvmx_ciu2_src_ppx_ip4_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t ilk                          : 1;  /**< ILK interface interrupts source
+                                                         CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface x Interrupts source
+                                                         CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */
+	uint64_t reserved_33_39               : 7;
+	uint64_t agl                          : 1;  /**< AGL interrupt source
+                                                         CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */
+	uint64_t reserved_13_31               : 19;
+	uint64_t gmx_drp                      : 5;  /**< GMX packet drop interrupt, RAW & ENABLE
+                                                         CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t agx                          : 5;  /**< GMX interrupt source
+                                                         CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */
+#else
+	uint64_t agx                          : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gmx_drp                      : 5;
+	uint64_t reserved_13_31               : 19;
+	uint64_t agl                          : 1;
+	uint64_t reserved_33_39               : 7;
+	uint64_t mii                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t ilk                          : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip4_pkt cvmx_ciu2_src_ppx_ip4_pkt_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip4_rml
+ */
+union cvmx_ciu2_src_ppx_ip4_rml {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip4_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt source
+                                                         CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt source
+                                                         CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt source
+                                                         CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dpi_dma                      : 1;  /**< DPI DMA instruction completion  interrupt
+                                                         See DPI DMA instruction completion */
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi                          : 1;  /**< DPI interrupt source
+                                                         CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< SLI interrupt source
+                                                         CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt source
+                                                         CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< RAD interrupt source
+                                                         CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< TIM interrupt source
+                                                         CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt source
+                                                         CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt source
+                                                         CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt source
+                                                         CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< PIP interrupt source
+                                                         CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< IPD interrupt source
+                                                         CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< FPA interrupt source
+                                                         CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt source
+                                                         CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_35               : 2;
+	uint64_t dpi_dma                      : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip4_rml_s    cn68xx;
+	struct cvmx_ciu2_src_ppx_ip4_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t trace                        : 4;  /**< Trace buffer interrupt source
+                                                         CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */
+	uint64_t reserved_49_51               : 3;
+	uint64_t l2c                          : 1;  /**< L2C interrupt source
+                                                         CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */
+	uint64_t reserved_41_47               : 7;
+	uint64_t dfa                          : 1;  /**< DFA interrupt source
+                                                         CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */
+	uint64_t reserved_34_39               : 6;
+	uint64_t dpi                          : 1;  /**< DPI interrupt source
+                                                         CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */
+	uint64_t sli                          : 1;  /**< SLI interrupt source
+                                                         CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */
+	uint64_t reserved_31_31               : 1;
+	uint64_t key                          : 1;  /**< KEY interrupt source
+                                                         CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */
+	uint64_t rad                          : 1;  /**< RAD interrupt source
+                                                         CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */
+	uint64_t tim                          : 1;  /**< TIM interrupt source
+                                                         CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */
+	uint64_t reserved_25_27               : 3;
+	uint64_t zip                          : 1;  /**< ZIP interrupt source
+                                                         CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */
+	uint64_t reserved_17_23               : 7;
+	uint64_t sso                          : 1;  /**< SSO err interrupt source
+                                                         CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pko                          : 1;  /**< PKO interrupt source
+                                                         CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */
+	uint64_t pip                          : 1;  /**< PIP interrupt source
+                                                         CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */
+	uint64_t ipd                          : 1;  /**< IPD interrupt source
+                                                         CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */
+	uint64_t fpa                          : 1;  /**< FPA interrupt source
+                                                         CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t iob                          : 1;  /**< IOB interrupt source
+                                                         CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */
+#else
+	uint64_t iob                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t fpa                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t sso                          : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t zip                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfa                          : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t l2c                          : 1;
+	uint64_t reserved_49_51               : 3;
+	uint64_t trace                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip4_rml cvmx_ciu2_src_ppx_ip4_rml_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip4_wdog
+ */
+union cvmx_ciu2_src_ppx_ip4_wdog {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip4_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t wdog                         : 32; /**< 32 watchdog interrupts source
+                                                         CIU2_RAW_WDOG & CIU2_EN_xx_yy_WDOG */
+#else
+	uint64_t wdog                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip4_wdog_s   cn68xx;
+	struct cvmx_ciu2_src_ppx_ip4_wdog_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip4_wdog cvmx_ciu2_src_ppx_ip4_wdog_t;
+
+/**
+ * cvmx_ciu2_src_pp#_ip4_wrkq
+ */
+union cvmx_ciu2_src_ppx_ip4_wrkq {
+	uint64_t u64;
+	struct cvmx_ciu2_src_ppx_ip4_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t workq                        : 64; /**< 64 work queue intr source,
+                                                         CIU2_RAW_WRKQ & CIU2_EN_xx_yy_WRKQ */
+#else
+	uint64_t workq                        : 64;
+#endif
+	} s;
+	struct cvmx_ciu2_src_ppx_ip4_wrkq_s   cn68xx;
+	struct cvmx_ciu2_src_ppx_ip4_wrkq_s   cn68xxp1;
+};
+typedef union cvmx_ciu2_src_ppx_ip4_wrkq cvmx_ciu2_src_ppx_ip4_wrkq_t;
+
+/**
+ * cvmx_ciu2_sum_io#_int
+ */
+union cvmx_ciu2_sum_iox_int {
+	uint64_t u64;
+	struct cvmx_ciu2_sum_iox_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mbox                         : 4;  /**< MBOX interrupt summary
+                                                         Direct connect to CIU2_SRC_*_MBOX[MBOX]
+                                                         See CIU_MBOX_SET/CLR / CIU2_SRC_*_MBOX */
+	uint64_t reserved_8_59                : 52;
+	uint64_t gpio                         : 1;  /**< GPIO interrupt summary,
+                                                         Report ORed result of CIU2_SRC_*_GPIO[63:0]
+                                                         See CIU2_RAW_GPIO / CIU2_SRC_*_GPIO */
+	uint64_t pkt                          : 1;  /**< Packet I/O interrupt summary
+                                                         Report ORed result of CIU2_SRC_*_PKT[63:0]
+                                                         See CIU2_RAW_PKT / CIU2_SRC_*_PKT */
+	uint64_t mem                          : 1;  /**< MEM  interrupt Summary
+                                                         Report ORed result of CIU2_SRC_*_MEM[63:0]
+                                                         See CIU2_RAW_MEM / CIU2_SRC_*_MEM */
+	uint64_t io                           : 1;  /**< I/O  interrupt summary
+                                                         Report ORed result of CIU2_SRC_*_IO[63:0]
+                                                         See CIU2_RAW_IO / CIU2_SRC_*_IO */
+	uint64_t mio                          : 1;  /**< MIO  interrupt summary
+                                                         Report ORed result of CIU2_SRC_*_MIO[63:0]
+                                                         See CIU2_RAW_MIO / CIU2_SRC_*_MIO */
+	uint64_t rml                          : 1;  /**< RML Interrupt
+                                                         Report ORed result of CIU2_SRC_*_RML[63:0]
+                                                         See CIU2_RAW_RML / CIU2_SRC_*_RML */
+	uint64_t wdog                         : 1;  /**< WDOG summary bit
+                                                         Report ORed result of CIU2_SRC_*_WDOG[63:0]
+                                                         See CIU2_RAW_WDOG / CIU2_SRC_*_WDOG
+                                                          This read-only bit reads as a one whenever
+                                                          CIU2_RAW_WDOG bit is set and corresponding
+                                                          enable bit in CIU2_EN_PPx_IPy_WDOG or
+                                                          CIU2_EN_IOx_INT_WDOG is set, where x and y are
+                                                          the same x and y in the CIU2_SUM_PPx_IPy or
+                                                          CIU2_SUM_IOx_INT registers.
+                                                          Alternatively, the CIU2_SRC_PPx_IPy_WDOG and
+                                                          CIU2_SRC_IOx_INT_WDOG registers can be used. */
+	uint64_t workq                        : 1;  /**< 64 work queue interrupts
+                                                         Report ORed result of CIU2_SRC_*_WRKQ[63:0]
+                                                         See CIU2_RAW_WRKQ / CIU2_SRC_*_WRKQ
+                                                         See SSO_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the SSO. */
+#else
+	uint64_t workq                        : 1;
+	uint64_t wdog                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t mio                          : 1;
+	uint64_t io                           : 1;
+	uint64_t mem                          : 1;
+	uint64_t pkt                          : 1;
+	uint64_t gpio                         : 1;
+	uint64_t reserved_8_59                : 52;
+	uint64_t mbox                         : 4;
+#endif
+	} s;
+	struct cvmx_ciu2_sum_iox_int_s        cn68xx;
+	struct cvmx_ciu2_sum_iox_int_s        cn68xxp1;
+};
+typedef union cvmx_ciu2_sum_iox_int cvmx_ciu2_sum_iox_int_t;
+
+/**
+ * cvmx_ciu2_sum_pp#_ip2
+ */
+union cvmx_ciu2_sum_ppx_ip2 {
+	uint64_t u64;
+	struct cvmx_ciu2_sum_ppx_ip2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mbox                         : 4;  /**< MBOX interrupt summary
+                                                         Direct connect to CIU2_SRC_*_MBOX[MBOX]
+                                                         See CIU_MBOX_SET/CLR / CIU2_SRC_*_MBOX */
+	uint64_t reserved_8_59                : 52;
+	uint64_t gpio                         : 1;  /**< GPIO interrupt summary,
+                                                         Report ORed result of CIU2_SRC_*_GPIO[63:0]
+                                                         See CIU2_RAW_GPIO / CIU2_SRC_*_GPIO */
+	uint64_t pkt                          : 1;  /**< Packet I/O interrupt summary
+                                                         Report ORed result of CIU2_SRC_*_PKT[63:0]
+                                                         See CIU2_RAW_PKT / CIU2_SRC_*_PKT */
+	uint64_t mem                          : 1;  /**< MEM  interrupt Summary
+                                                         Report ORed result of CIU2_SRC_*_MEM[63:0]
+                                                         See CIU2_RAW_MEM / CIU2_SRC_*_MEM */
+	uint64_t io                           : 1;  /**< I/O  interrupt summary
+                                                         Report ORed result of CIU2_SRC_*_IO[63:0]
+                                                         See CIU2_RAW_IO / CIU2_SRC_*_IO */
+	uint64_t mio                          : 1;  /**< MIO  interrupt summary
+                                                         Report ORed result of CIU2_SRC_*_MIO[63:0]
+                                                         See CIU2_RAW_MIO / CIU2_SRC_*_MIO */
+	uint64_t rml                          : 1;  /**< RML Interrupt
+                                                         Report ORed result of CIU2_SRC_*_RML[63:0]
+                                                         See CIU2_RAW_RML / CIU2_SRC_*_RML */
+	uint64_t wdog                         : 1;  /**< WDOG summary bit
+                                                         Report ORed result of CIU2_SRC_*_WDOG[63:0]
+                                                         See CIU2_RAW_WDOG / CIU2_SRC_*_WDOG
+                                                          This read-only bit reads as a one whenever
+                                                          CIU2_RAW_WDOG bit is set and corresponding
+                                                          enable bit in CIU2_EN_PPx_IPy_WDOG or
+                                                          CIU2_EN_IOx_INT_WDOG is set, where x and y are
+                                                          the same x and y in the CIU2_SUM_PPx_IPy or
+                                                          CIU2_SUM_IOx_INT registers.
+                                                          Alternatively, the CIU2_SRC_PPx_IPy_WDOG and
+                                                          CIU2_SRC_IOx_INT_WDOG registers can be used. */
+	uint64_t workq                        : 1;  /**< 64 work queue interrupts
+                                                         Report ORed result of CIU2_SRC_*_WRKQ[63:0]
+                                                         See CIU2_RAW_WRKQ / CIU2_SRC_*_WRKQ
+                                                         See SSO_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the SSO. */
+#else
+	uint64_t workq                        : 1;
+	uint64_t wdog                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t mio                          : 1;
+	uint64_t io                           : 1;
+	uint64_t mem                          : 1;
+	uint64_t pkt                          : 1;
+	uint64_t gpio                         : 1;
+	uint64_t reserved_8_59                : 52;
+	uint64_t mbox                         : 4;
+#endif
+	} s;
+	struct cvmx_ciu2_sum_ppx_ip2_s        cn68xx;
+	struct cvmx_ciu2_sum_ppx_ip2_s        cn68xxp1;
+};
+typedef union cvmx_ciu2_sum_ppx_ip2 cvmx_ciu2_sum_ppx_ip2_t;
+
+/**
+ * cvmx_ciu2_sum_pp#_ip3
+ */
+union cvmx_ciu2_sum_ppx_ip3 {
+	uint64_t u64;
+	struct cvmx_ciu2_sum_ppx_ip3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mbox                         : 4;  /**< MBOX interrupt summary
+                                                         Direct connect to CIU2_SRC_*_MBOX[MBOX]
+                                                         See CIU_MBOX_SET/CLR / CIU2_SRC_*_MBOX */
+	uint64_t reserved_8_59                : 52;
+	uint64_t gpio                         : 1;  /**< GPIO interrupt summary,
+                                                         Report ORed result of CIU2_SRC_*_GPIO[63:0]
+                                                         See CIU2_RAW_GPIO / CIU2_SRC_*_GPIO */
+	uint64_t pkt                          : 1;  /**< Packet I/O interrupt summary
+                                                         Report ORed result of CIU2_SRC_*_PKT[63:0]
+                                                         See CIU2_RAW_PKT / CIU2_SRC_*_PKT */
+	uint64_t mem                          : 1;  /**< MEM  interrupt Summary
+                                                         Report ORed result of CIU2_SRC_*_MEM[63:0]
+                                                         See CIU2_RAW_MEM / CIU2_SRC_*_MEM */
+	uint64_t io                           : 1;  /**< I/O  interrupt summary
+                                                         Report ORed result of CIU2_SRC_*_IO[63:0]
+                                                         See CIU2_RAW_IO / CIU2_SRC_*_IO */
+	uint64_t mio                          : 1;  /**< MIO  interrupt summary
+                                                         Report ORed result of CIU2_SRC_*_MIO[63:0]
+                                                         See CIU2_RAW_MIO / CIU2_SRC_*_MIO */
+	uint64_t rml                          : 1;  /**< RML Interrupt
+                                                         Report ORed result of CIU2_SRC_*_RML[63:0]
+                                                         See CIU2_RAW_RML / CIU2_SRC_*_RML */
+	uint64_t wdog                         : 1;  /**< WDOG summary bit
+                                                         Report ORed result of CIU2_SRC_*_WDOG[63:0]
+                                                         See CIU2_RAW_WDOG / CIU2_SRC_*_WDOG
+                                                          This read-only bit reads as a one whenever
+                                                          CIU2_RAW_WDOG bit is set and corresponding
+                                                          enable bit in CIU2_EN_PPx_IPy_WDOG or
+                                                          CIU2_EN_IOx_INT_WDOG is set, where x and y are
+                                                          the same x and y in the CIU2_SUM_PPx_IPy or
+                                                          CIU2_SUM_IOx_INT registers.
+                                                          Alternatively, the CIU2_SRC_PPx_IPy_WDOG and
+                                                          CIU2_SRC_IOx_INT_WDOG registers can be used. */
+	uint64_t workq                        : 1;  /**< 64 work queue interrupts
+                                                         Report ORed result of CIU2_SRC_*_WRKQ[63:0]
+                                                         See CIU2_RAW_WRKQ / CIU2_SRC_*_WRKQ
+                                                         See SSO_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the SSO. */
+#else
+	uint64_t workq                        : 1;
+	uint64_t wdog                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t mio                          : 1;
+	uint64_t io                           : 1;
+	uint64_t mem                          : 1;
+	uint64_t pkt                          : 1;
+	uint64_t gpio                         : 1;
+	uint64_t reserved_8_59                : 52;
+	uint64_t mbox                         : 4;
+#endif
+	} s;
+	struct cvmx_ciu2_sum_ppx_ip3_s        cn68xx;
+	struct cvmx_ciu2_sum_ppx_ip3_s        cn68xxp1;
+};
+typedef union cvmx_ciu2_sum_ppx_ip3 cvmx_ciu2_sum_ppx_ip3_t;
+
+/**
+ * cvmx_ciu2_sum_pp#_ip4
+ */
+union cvmx_ciu2_sum_ppx_ip4 {
+	uint64_t u64;
+	struct cvmx_ciu2_sum_ppx_ip4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mbox                         : 4;  /**< MBOX interrupt summary
+                                                         Direct connect to CIU2_SRC_*_MBOX[MBOX]
+                                                         See CIU_MBOX_SET/CLR / CIU2_SRC_*_MBOX */
+	uint64_t reserved_8_59                : 52;
+	uint64_t gpio                         : 1;  /**< GPIO interrupt summary,
+                                                         Report ORed result of CIU2_SRC_*_GPIO[63:0]
+                                                         See CIU2_RAW_GPIO / CIU2_SRC_*_GPIO */
+	uint64_t pkt                          : 1;  /**< Packet I/O interrupt summary
+                                                         Report ORed result of CIU2_SRC_*_PKT[63:0]
+                                                         See CIU2_RAW_PKT / CIU2_SRC_*_PKT */
+	uint64_t mem                          : 1;  /**< MEM  interrupt Summary
+                                                         Report ORed result of CIU2_SRC_*_MEM[63:0]
+                                                         See CIU2_RAW_MEM / CIU2_SRC_*_MEM */
+	uint64_t io                           : 1;  /**< I/O  interrupt summary
+                                                         Report ORed result of CIU2_SRC_*_IO[63:0]
+                                                         See CIU2_RAW_IO / CIU2_SRC_*_IO */
+	uint64_t mio                          : 1;  /**< MIO  interrupt summary
+                                                         Report ORed result of CIU2_SRC_*_MIO[63:0]
+                                                         See CIU2_RAW_MIO / CIU2_SRC_*_MIO */
+	uint64_t rml                          : 1;  /**< RML Interrupt
+                                                         Report ORed result of CIU2_SRC_*_RML[63:0]
+                                                         See CIU2_RAW_RML / CIU2_SRC_*_RML */
+	uint64_t wdog                         : 1;  /**< WDOG summary bit
+                                                         Report ORed result of CIU2_SRC_*_WDOG[63:0]
+                                                         See CIU2_RAW_WDOG / CIU2_SRC_*_WDOG
+                                                          This read-only bit reads as a one whenever
+                                                          CIU2_RAW_WDOG bit is set and corresponding
+                                                          enable bit in CIU2_EN_PPx_IPy_WDOG or
+                                                          CIU2_EN_IOx_INT_WDOG is set, where x and y are
+                                                          the same x and y in the CIU2_SUM_PPx_IPy or
+                                                          CIU2_SUM_IOx_INT registers.
+                                                          Alternatively, the CIU2_SRC_PPx_IPy_WDOG and
+                                                          CIU2_SRC_IOx_INT_WDOG registers can be used. */
+	uint64_t workq                        : 1;  /**< 64 work queue interrupts
+                                                         Report ORed result of CIU2_SRC_*_WRKQ[63:0]
+                                                         See CIU2_RAW_WRKQ / CIU2_SRC_*_WRKQ
+                                                         See SSO_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the SSO. */
+#else
+	uint64_t workq                        : 1;
+	uint64_t wdog                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t mio                          : 1;
+	uint64_t io                           : 1;
+	uint64_t mem                          : 1;
+	uint64_t pkt                          : 1;
+	uint64_t gpio                         : 1;
+	uint64_t reserved_8_59                : 52;
+	uint64_t mbox                         : 4;
+#endif
+	} s;
+	struct cvmx_ciu2_sum_ppx_ip4_s        cn68xx;
+	struct cvmx_ciu2_sum_ppx_ip4_s        cn68xxp1;
+};
+typedef union cvmx_ciu2_sum_ppx_ip4 cvmx_ciu2_sum_ppx_ip4_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-clock.c b/sys/contrib/octeon-sdk/cvmx-clock.c
index dfc17c3..a261c5d 100644
--- a/sys/contrib/octeon-sdk/cvmx-clock.c
+++ b/sys/contrib/octeon-sdk/cvmx-clock.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -89,6 +89,9 @@ uint64_t cvmx_clock_get_rate(cvmx_clock_t clock)
 
     if (cvmx_unlikely(!rate_eclk))
     {
+	/* Note: The order of these checks is important.
+	** octeon_has_feature(OCTEON_FEATURE_PCIE) is true for both 6XXX
+	** and 52XX/56XX, so OCTEON_FEATURE_NPEI _must_ be checked first */
         if (octeon_has_feature(OCTEON_FEATURE_NPEI))
         {
             cvmx_npei_dbg_data_t npei_dbg_data;
@@ -124,7 +127,7 @@ uint64_t cvmx_clock_get_rate(cvmx_clock_t clock)
             return rate_eclk;
 
         case CVMX_CLOCK_DDR:
-#if !defined(CVMX_BUILD_FOR_LINUX_HOST) && !defined(__OCTEON_NEWLIB__)
+#if !defined(CVMX_BUILD_FOR_LINUX_HOST) && !defined(CVMX_BUILD_FOR_TOOLCHAIN)
             if (cvmx_unlikely(!rate_dclk))
                 rate_dclk = cvmx_sysinfo_get()->dram_data_rate_hz;
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-clock.h b/sys/contrib/octeon-sdk/cvmx-clock.h
index 8d74731..645969c 100644
--- a/sys/contrib/octeon-sdk/cvmx-clock.h
+++ b/sys/contrib/octeon-sdk/cvmx-clock.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -120,7 +120,7 @@ static inline uint64_t cvmx_clock_get_count(cvmx_clock_t clock)
             return cvmx_read_csr(CVMX_IPD_CLK_COUNT);
 
         case CVMX_CLOCK_DDR:
-            if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+            if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
                 return cvmx_read_csr(CVMX_LMCX_DCLK_CNT(0));
             else
                 return ((cvmx_read_csr(CVMX_LMCX_DCLK_CNT_HI(0)) << 32) | cvmx_read_csr(CVMX_LMCX_DCLK_CNT_LO(0)));
diff --git a/sys/contrib/octeon-sdk/cvmx-cmd-queue.c b/sys/contrib/octeon-sdk/cvmx-cmd-queue.c
index 23617b8..b7ac55f 100644
--- a/sys/contrib/octeon-sdk/cvmx-cmd-queue.c
+++ b/sys/contrib/octeon-sdk/cvmx-cmd-queue.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * Support functions for managing command queues used for
  * various hardware blocks.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <linux/module.h>
@@ -288,7 +288,10 @@ int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id)
             {
                 cvmx_pko_mem_debug8_t debug8;
                 debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
-                return debug8.cn58xx.doorbell;
+                if (octeon_has_feature(OCTEON_FEATURE_PKND))
+                    return debug8.cn68xx.doorbell;
+                else
+                    return debug8.cn58xx.doorbell;
             }
         case CVMX_CMD_QUEUE_ZIP:
         case CVMX_CMD_QUEUE_DFA:
diff --git a/sys/contrib/octeon-sdk/cvmx-cmd-queue.h b/sys/contrib/octeon-sdk/cvmx-cmd-queue.h
index 29c0d256..5a7a543 100644
--- a/sys/contrib/octeon-sdk/cvmx-cmd-queue.h
+++ b/sys/contrib/octeon-sdk/cvmx-cmd-queue.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -88,7 +88,7 @@
  * internal cycle counter to completely eliminate any causes of
  * bus traffic.
  *
- * <hr> $Revision: 50049 $ <hr>
+ * <hr> $Revision: 70030 $ <hr>
  */
 
 #ifndef __CVMX_CMD_QUEUE_H__
@@ -125,6 +125,7 @@ typedef enum
     CVMX_CMD_QUEUE_PKO_BASE = 0x00000,
 #define CVMX_CMD_QUEUE_PKO(queue) ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_PKO_BASE + (0xffff&(queue))))
     CVMX_CMD_QUEUE_ZIP      = 0x10000,
+#define CVMX_CMD_QUEUE_ZIP_QUE(queue) ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_ZIP + (0xffff&(queue))))
     CVMX_CMD_QUEUE_DFA      = 0x20000,
     CVMX_CMD_QUEUE_RAID     = 0x30000,
     CVMX_CMD_QUEUE_DMA_BASE = 0x40000,
@@ -233,7 +234,7 @@ void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id);
 static inline int __cvmx_cmd_queue_get_index(cvmx_cmd_queue_id_t queue_id)
 {
     /* Warning: This code currently only works with devices that have 256 queues
-        or less. Devices with more than 16 queues are layed out in memory to allow
+        or less. Devices with more than 16 queues are laid out in memory to allow
         cores quick access to every 16th queue. This reduces cache thrashing
         when you are running 16 queues per port to support lockless operation */
     int unit = queue_id>>16;
diff --git a/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c b/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c
index 0b03655..1f2f049 100644
--- a/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c
+++ b/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Interface to the EBH-30xx specific devices
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.h b/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.h
index ecd8b5a..6bf18c3 100644
--- a/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.h
+++ b/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -51,7 +51,7 @@
  *
  * Interface to the EBH-30xx specific devices
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-compactflash.c b/sys/contrib/octeon-sdk/cvmx-compactflash.c
index c5123fb..ff19066 100644
--- a/sys/contrib/octeon-sdk/cvmx-compactflash.c
+++ b/sys/contrib/octeon-sdk/cvmx-compactflash.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-compactflash.h b/sys/contrib/octeon-sdk/cvmx-compactflash.h
index b07512b..07eb17b 100644
--- a/sys/contrib/octeon-sdk/cvmx-compactflash.h
+++ b/sys/contrib/octeon-sdk/cvmx-compactflash.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-core.c b/sys/contrib/octeon-sdk/cvmx-core.c
index 6afbad2..cc1ee25 100644
--- a/sys/contrib/octeon-sdk/cvmx-core.c
+++ b/sys/contrib/octeon-sdk/cvmx-core.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Module to support operations on core such as TLB config, etc.
  *
- * <hr>$Revision: 49862 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-core.h b/sys/contrib/octeon-sdk/cvmx-core.h
index 3f59761..4ee5963 100644
--- a/sys/contrib/octeon-sdk/cvmx-core.h
+++ b/sys/contrib/octeon-sdk/cvmx-core.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Module to support operations on core such as TLB config, etc.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
@@ -134,12 +134,12 @@ typedef union
     uint32_t u32;
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint32_t m              : 1; /**< Set to 1 for sel 0 and 0 for sel 2, indicating there are two performance counters */
-        uint32_t w              : 1; /**< Set to 1 indicating coutners are 64 bit */
+        uint32_t w              : 1; /**< Set to 1 indicating counters are 64 bit */
         uint32_t reserved_11_29 :15;
         cvmx_core_perf_t event  :10; /**< Selects the event to be counted by the corresponding Counter Register */
-        uint32_t ie             : 1; /**< Count in interrupt context */
+        uint32_t ie             : 1; /**< Interrupt Enable */
         uint32_t u              : 1; /**< Count in user mode */
         uint32_t s              : 1; /**< Count in supervisor mode */
         uint32_t k              : 1; /**< Count in kernel mode */
diff --git a/sys/contrib/octeon-sdk/cvmx-coremask.c b/sys/contrib/octeon-sdk/cvmx-coremask.c
index 8c59075..66ccc16 100644
--- a/sys/contrib/octeon-sdk/cvmx-coremask.c
+++ b/sys/contrib/octeon-sdk/cvmx-coremask.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -51,7 +51,7 @@
  * initialization and differentiation of roles within a single shared binary
  * executable image.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-coremask.h b/sys/contrib/octeon-sdk/cvmx-coremask.h
index d0c5825..7f19659 100644
--- a/sys/contrib/octeon-sdk/cvmx-coremask.h
+++ b/sys/contrib/octeon-sdk/cvmx-coremask.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -51,7 +51,7 @@
  * initialization and differentiation of roles within a single shared binary
  * executable image.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
@@ -65,6 +65,162 @@
 extern "C" {
 #endif
 
+typedef uint64_t cvmx_coremask_holder_t;	/* basic type to hold the
+						   coremask bits */
+
+#define CVMX_COREMASK_HLDRSZ ((int)(sizeof(cvmx_coremask_holder_t) * 8))
+						/* bits per holder */
+
+#define CVMX_COREMASK_BMPSZ ((int)(CVMX_MAX_CORES / CVMX_COREMASK_HLDRSZ + 1))
+						/* bit map size */
+
+/*
+ * The macro pair implement a way to iterate active cores in the mask.
+ * @param fec_pcm points to the coremask.
+ * @param fec_ppid is the active core's id.
+ */
+#define CVMX_COREMASK_FOR_EACH_CORE_BEGIN(fec_pcm, fec_ppid)		\
+    do {								\
+    	int fec_i, fec_j;						\
+    				 					\
+	for (fec_i = 0; fec_i < CVMX_COREMASK_BMPSZ; fec_i++)		\
+	{								\
+	    for (fec_j = 0; fec_j < CVMX_COREMASK_HLDRSZ; fec_j++)	\
+	    { 								\
+		if (((cvmx_coremask_holder_t)1 << fec_j) & 		\
+		    (fec_pcm)->coremask_bitmap[fec_i])			\
+		{							\
+	            fec_ppid = fec_i * CVMX_COREMASK_HLDRSZ + fec_j;
+
+
+#define CVMX_COREMASK_FOR_EACH_CORE_END					\
+		}							\
+	    }								\
+	}								\
+   } while (0)
+
+struct cvmx_coremask {
+    /*
+     * Big-endian. Array elems of larger indices represent cores of
+     * bigger ids. So do MSBs within a cvmx_coremask_holder_t. Ditto
+     * MSbs within a byte.
+     */
+    cvmx_coremask_holder_t coremask_bitmap[CVMX_COREMASK_BMPSZ];
+};
+
+/*
+ * Is ``core'' set in the coremask?
+ *
+ * @param pcm is the pointer to the coremask.
+ * @param core
+ * @return 1 if core is set and 0 if not.
+ */
+static inline int cvmx_coremask_is_set_core(struct cvmx_coremask *pcm,
+    int core)
+{
+    int n, i;
+
+    n = core % CVMX_COREMASK_HLDRSZ;
+    i = core / CVMX_COREMASK_HLDRSZ;
+
+    return (int)((pcm->coremask_bitmap[i] & (1ull << n)) != 0);
+}
+
+/*
+ * Set ``core'' in the coremask.
+ *
+ * @param pcm is the pointer to the coremask.
+ * @param core
+ * @return 0.
+ */
+static inline int cvmx_coremask_set_core(struct cvmx_coremask *pcm,
+    int core)
+{
+    int n, i;
+
+    n = core % CVMX_COREMASK_HLDRSZ;
+    i = core / CVMX_COREMASK_HLDRSZ;
+    pcm->coremask_bitmap[i] |= (1ull << n);
+
+    return 0;
+}
+
+/*
+ * Clear ``core'' from the coremask.
+ *
+ * @param pcm is the pointer to the coremask.
+ * @param core
+ * @return 0.
+ */
+static inline int cvmx_coremask_clear_core(struct cvmx_coremask *pcm,
+    int core)
+{
+    int n, i;
+
+    n = core % CVMX_COREMASK_HLDRSZ;
+    i = core / CVMX_COREMASK_HLDRSZ;
+    pcm->coremask_bitmap[i] &= ~(1ull << n);
+
+    return 0;
+}
+
+/*
+ * Clear the coremask.
+ *
+ * @param pcm is the pointer to the coremask.
+ * @return 0.
+ */
+static inline int cvmx_coremask_clear_all(struct cvmx_coremask *pcm)
+{
+    int i;
+
+    for (i = 0; i < CVMX_COREMASK_BMPSZ; i++)
+        pcm->coremask_bitmap[i] = 0;
+
+    return 0;
+}
+
+/*
+ * Is the current core the first in the coremask?
+ *
+ * @param pcm is the pointer to the coremask.
+ * @return 1 for yes and 0 for no.
+ */
+static inline int cvmx_coremask_first_core_bmp(struct cvmx_coremask *pcm)
+{
+     int n, i;
+
+     n = (int) cvmx_get_core_num();
+     for (i = 0; i < CVMX_COREMASK_BMPSZ; i++)
+     {
+         if (pcm->coremask_bitmap[i])
+         {
+             if (n == 0 && pcm->coremask_bitmap[i] & 1)
+                 return 1;
+
+             if (n >= CVMX_COREMASK_HLDRSZ)
+                 return 0;
+
+             return ((((1ull << n) - 1) & pcm->coremask_bitmap[i]) == 0);
+         }
+         else
+             n -= CVMX_COREMASK_HLDRSZ;
+     }
+
+     return 0;
+}
+
+/*
+ * Is the current core a member of the coremask?
+ *
+ * @param pcm is the pointer to the coremask.
+ * @return 1 for yes and 0 for no.
+ */
+static inline int cvmx_coremask_is_member_bmp(struct cvmx_coremask *pcm)
+{
+    return cvmx_coremask_is_set_core(pcm, (int)cvmx_get_core_num());
+}
+
 /*
  * coremask is simply unsigned int (32 bits).
  *
@@ -101,7 +257,7 @@ static inline unsigned int cvmx_coremask_core(unsigned int core_id)
  */
 static inline unsigned int cvmx_coremask_numcores(unsigned int num_cores)
 {
-    return (CVMX_COREMASK_MAX >> (32 - num_cores));
+    return (CVMX_COREMASK_MAX >> (CVMX_MAX_CORES - num_cores));
 }
 
 /**
@@ -115,7 +271,7 @@ static inline unsigned int cvmx_coremask_numcores(unsigned int num_cores)
  */
 static inline unsigned int cvmx_coremask_range(unsigned int low, unsigned int high)
 {
-    return ((CVMX_COREMASK_MAX >> (31 - high + low)) << low);
+    return ((CVMX_COREMASK_MAX >> (CVMX_MAX_CORES - 1 - high + low)) << low);
 }
 
 
diff --git a/sys/contrib/octeon-sdk/cvmx-crypto.c b/sys/contrib/octeon-sdk/cvmx-crypto.c
index 46223fb..a2aff7f 100644
--- a/sys/contrib/octeon-sdk/cvmx-crypto.c
+++ b/sys/contrib/octeon-sdk/cvmx-crypto.c
@@ -1,6 +1,6 @@
 
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -16,7 +16,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -27,7 +27,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-crypto.h b/sys/contrib/octeon-sdk/cvmx-crypto.h
index c601431..20759d8 100644
--- a/sys/contrib/octeon-sdk/cvmx-crypto.h
+++ b/sys/contrib/octeon-sdk/cvmx-crypto.h
@@ -1,6 +1,6 @@
 
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -16,7 +16,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -27,7 +27,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-csr-db-support.c b/sys/contrib/octeon-sdk/cvmx-csr-db-support.c
index 6850c31..2638d09 100644
--- a/sys/contrib/octeon-sdk/cvmx-csr-db-support.c
+++ b/sys/contrib/octeon-sdk/cvmx-csr-db-support.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Utility functions for working with the CSR database
  *
- * <hr>$Revision: 49507 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #define PRINTF printk
@@ -87,8 +87,16 @@ int cvmx_db_get_chipindex(int identifier)
             return 2;
         case 0x000d0700: /* CN52XX */
             return 10;
-        case 0x000d9000: /* CN63XX */
+        case 0x000d9300: /* CN61XX */
             return 11;
+        case 0x000d9000: /* CN63XX */
+            return 13;
+        case 0x000d9200: /* CN66XX */
+            return 14;
+        case 0x000d9100: /* CN68XX */
+            return 16;
+        case 0x000d9400: /* CNF71XX */
+            return 17;
     }
 
     /* Next try PCI device IDs */
@@ -114,8 +122,16 @@ int cvmx_db_get_chipindex(int identifier)
             return 8;
         case 0x0080177d: /* CN52XX Pass 2 */
             return 10;
-        case 0x0090177d: /* CN63XX Pass 1 */
+        case 0x0093177d: /* CN61XX Pass 2 */
             return 11;
+        case 0x0090177d: /* CN63XX Pass 2 */
+            return 13;
+        case 0x0092177d: /* CN66XX Pass 1 */
+            return 14;
+        case 0x0091177d: /* CN68XX Pass 2 */
+            return 16;
+        case 0x0094177d: /* CNF71XX Pass 1 */
+            return 17;
     }
 
     /* Default to Pass 3 if we don't know */
diff --git a/sys/contrib/octeon-sdk/cvmx-csr-db.c b/sys/contrib/octeon-sdk/cvmx-csr-db.c
index 48316e3..3a83e22 100644
--- a/sys/contrib/octeon-sdk/cvmx-csr-db.c
+++ b/sys/contrib/octeon-sdk/cvmx-csr-db.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -46,7 +46,7 @@
  *
  * This file is auto generated. Do not edit.
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 69515 $<hr>
  *
  */
 
@@ -608,26 +608,26 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn38xxp2[] = {
 	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2375,	4,	2640},
 	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2376,	2,	2644},
 	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2377,	3,	2646},
-	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2378,	4,	2649},
-	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2379,	12,	2653},
-	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2380,	3,	2665},
-	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2381,	2,	2668},
-	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2382,	2,	2670},
-	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2383,	17,	2672},
-	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2384,	12,	2689},
-	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2385,	6,	2701},
-	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2386,	5,	2707},
-	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2387,	1,	2712},
-	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2388,	2,	2713},
-	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2389,	2,	2715},
-	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2390,	17,	2717},
-	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2391,	12,	2734},
-	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2392,	6,	2746},
-	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2393,	2,	2752},
-	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2394,	2,	2754},
-	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2395,	17,	2756},
-	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2396,	12,	2773},
-	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2397,	6,	2785},
+	{"cvmx_tra#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2378,	4,	2649},
+	{"cvmx_tra#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2379,	12,	2653},
+	{"cvmx_tra#_cycles_since"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2380,	3,	2665},
+	{"cvmx_tra#_filt_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2381,	2,	2668},
+	{"cvmx_tra#_filt_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2382,	2,	2670},
+	{"cvmx_tra#_filt_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2383,	17,	2672},
+	{"cvmx_tra#_filt_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2384,	12,	2689},
+	{"cvmx_tra#_filt_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2385,	6,	2701},
+	{"cvmx_tra#_int_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2386,	5,	2707},
+	{"cvmx_tra#_read_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2387,	1,	2712},
+	{"cvmx_tra#_trig0_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2388,	2,	2713},
+	{"cvmx_tra#_trig0_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2389,	2,	2715},
+	{"cvmx_tra#_trig0_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2390,	17,	2717},
+	{"cvmx_tra#_trig0_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2391,	12,	2734},
+	{"cvmx_tra#_trig0_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2392,	6,	2746},
+	{"cvmx_tra#_trig1_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2393,	2,	2752},
+	{"cvmx_tra#_trig1_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2394,	2,	2754},
+	{"cvmx_tra#_trig1_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2395,	17,	2756},
+	{"cvmx_tra#_trig1_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2396,	12,	2773},
+	{"cvmx_tra#_trig1_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2397,	6,	2785},
 	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2398,	3,	2791},
 	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2399,	5,	2794},
 	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2400,	3,	2799},
@@ -3017,26 +3017,26 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	548},
-	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	549},
-	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	550},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	551},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	552},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
-	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
-	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
-	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
-	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
-	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
-	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
-	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
-	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
-	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
-	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"TRA0_BIST_STATUS"            ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	549},
+	{"TRA0_CTL"                    ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	550},
+	{"TRA0_CYCLES_SINCE"           ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	551},
+	{"TRA0_FILT_ADR_ADR"           ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	552},
+	{"TRA0_FILT_ADR_MSK"           ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
+	{"TRA0_FILT_CMD"               ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
+	{"TRA0_FILT_DID"               ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"TRA0_FILT_SID"               ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
+	{"TRA0_INT_STATUS"             ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
+	{"TRA0_READ_DAT"               ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"TRA0_TRIG0_ADR_ADR"          ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
+	{"TRA0_TRIG0_ADR_MSK"          ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
+	{"TRA0_TRIG0_CMD"              ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
+	{"TRA0_TRIG0_DID"              ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
+	{"TRA0_TRIG0_SID"              ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
+	{"TRA0_TRIG1_ADR_ADR"          ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
+	{"TRA0_TRIG1_ADR_MSK"          ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
+	{"TRA0_TRIG1_CMD"              ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
+	{"TRA0_TRIG1_DID"              ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
+	{"TRA0_TRIG1_SID"              ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
 	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	569},
 	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	570},
 	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	571},
@@ -6373,26 +6373,26 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn31xx[] = {
 	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1161,	4,	2500},
 	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1162,	2,	2504},
 	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1163,	3,	2506},
-	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1164,	4,	2509},
-	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1165,	12,	2513},
-	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1166,	3,	2525},
-	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1167,	2,	2528},
-	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1168,	2,	2530},
-	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1169,	17,	2532},
-	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1170,	12,	2549},
-	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1171,	6,	2561},
-	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1172,	5,	2567},
-	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1173,	1,	2572},
-	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1174,	2,	2573},
-	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1175,	2,	2575},
-	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1176,	17,	2577},
-	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1177,	12,	2594},
-	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1178,	6,	2606},
-	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1179,	2,	2612},
-	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1180,	2,	2614},
-	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1181,	17,	2616},
-	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1182,	12,	2633},
-	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1183,	6,	2645},
+	{"cvmx_tra#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1164,	4,	2509},
+	{"cvmx_tra#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1165,	12,	2513},
+	{"cvmx_tra#_cycles_since"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1166,	3,	2525},
+	{"cvmx_tra#_filt_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1167,	2,	2528},
+	{"cvmx_tra#_filt_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1168,	2,	2530},
+	{"cvmx_tra#_filt_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1169,	17,	2532},
+	{"cvmx_tra#_filt_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1170,	12,	2549},
+	{"cvmx_tra#_filt_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1171,	6,	2561},
+	{"cvmx_tra#_int_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1172,	5,	2567},
+	{"cvmx_tra#_read_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1173,	1,	2572},
+	{"cvmx_tra#_trig0_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1174,	2,	2573},
+	{"cvmx_tra#_trig0_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1175,	2,	2575},
+	{"cvmx_tra#_trig0_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1176,	17,	2577},
+	{"cvmx_tra#_trig0_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1177,	12,	2594},
+	{"cvmx_tra#_trig0_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1178,	6,	2606},
+	{"cvmx_tra#_trig1_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1179,	2,	2612},
+	{"cvmx_tra#_trig1_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1180,	2,	2614},
+	{"cvmx_tra#_trig1_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1181,	17,	2616},
+	{"cvmx_tra#_trig1_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1182,	12,	2633},
+	{"cvmx_tra#_trig1_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1183,	6,	2645},
 	{"cvmx_usbc#_daint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	1184,	2,	2651},
 	{"cvmx_usbc#_daintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1185,	2,	2653},
 	{"cvmx_usbc#_dcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1186,	8,	2655},
@@ -7643,26 +7643,26 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
-	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
-	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
-	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
-	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
-	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
-	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
-	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	516},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	517},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	518},
-	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
-	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
-	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
-	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
-	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
-	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
+	{"TRA0_BIST_STATUS"            ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"TRA0_CTL"                    ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"TRA0_CYCLES_SINCE"           ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"TRA0_FILT_ADR_ADR"           ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"TRA0_FILT_ADR_MSK"           ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"TRA0_FILT_CMD"               ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"TRA0_FILT_DID"               ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"TRA0_FILT_SID"               ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"TRA0_INT_STATUS"             ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
+	{"TRA0_READ_DAT"               ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	516},
+	{"TRA0_TRIG0_ADR_ADR"          ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	517},
+	{"TRA0_TRIG0_ADR_MSK"          ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	518},
+	{"TRA0_TRIG0_CMD"              ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
+	{"TRA0_TRIG0_DID"              ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
+	{"TRA0_TRIG0_SID"              ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"TRA0_TRIG1_ADR_ADR"          ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
+	{"TRA0_TRIG1_ADR_MSK"          ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
+	{"TRA0_TRIG1_CMD"              ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
+	{"TRA0_TRIG1_DID"              ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
+	{"TRA0_TRIG1_SID"              ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
 	{"USBC0_DAINT"                 ,	   0x16f0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
 	{"USBC0_DAINTMSK"              ,	   0x16f001000081cull,	CVMX_CSR_DB_TYPE_NCB,	32,	528},
 	{"USBC0_DCFG"                  ,	   0x16f0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
@@ -16307,26 +16307,26 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn38xx[] = {
 	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2392,	4,	2766},
 	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2393,	2,	2770},
 	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2394,	3,	2772},
-	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2395,	4,	2775},
-	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2396,	12,	2779},
-	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2397,	3,	2791},
-	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2398,	2,	2794},
-	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2399,	2,	2796},
-	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2400,	17,	2798},
-	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2401,	12,	2815},
-	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2402,	6,	2827},
-	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2403,	5,	2833},
-	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2404,	1,	2838},
-	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2405,	2,	2839},
-	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2406,	2,	2841},
-	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2407,	17,	2843},
-	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2408,	12,	2860},
-	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2409,	6,	2872},
-	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2410,	2,	2878},
-	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2411,	2,	2880},
-	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2412,	17,	2882},
-	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2413,	12,	2899},
-	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2414,	6,	2911},
+	{"cvmx_tra#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2395,	4,	2775},
+	{"cvmx_tra#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2396,	12,	2779},
+	{"cvmx_tra#_cycles_since"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2397,	3,	2791},
+	{"cvmx_tra#_filt_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2398,	2,	2794},
+	{"cvmx_tra#_filt_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2399,	2,	2796},
+	{"cvmx_tra#_filt_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2400,	17,	2798},
+	{"cvmx_tra#_filt_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2401,	12,	2815},
+	{"cvmx_tra#_filt_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2402,	6,	2827},
+	{"cvmx_tra#_int_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2403,	5,	2833},
+	{"cvmx_tra#_read_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2404,	1,	2838},
+	{"cvmx_tra#_trig0_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2405,	2,	2839},
+	{"cvmx_tra#_trig0_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2406,	2,	2841},
+	{"cvmx_tra#_trig0_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2407,	17,	2843},
+	{"cvmx_tra#_trig0_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2408,	12,	2860},
+	{"cvmx_tra#_trig0_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2409,	6,	2872},
+	{"cvmx_tra#_trig1_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2410,	2,	2878},
+	{"cvmx_tra#_trig1_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2411,	2,	2880},
+	{"cvmx_tra#_trig1_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2412,	17,	2882},
+	{"cvmx_tra#_trig1_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2413,	12,	2899},
+	{"cvmx_tra#_trig1_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2414,	6,	2911},
 	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2415,	3,	2917},
 	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2416,	5,	2920},
 	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2417,	3,	2925},
@@ -18733,26 +18733,26 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
-	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
-	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
-	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
-	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	569},
-	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	570},
-	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	571},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	572},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	573},
-	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	574},
-	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
-	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	577},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	578},
-	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	579},
-	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	580},
-	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	581},
+	{"TRA0_BIST_STATUS"            ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
+	{"TRA0_CTL"                    ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
+	{"TRA0_CYCLES_SINCE"           ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
+	{"TRA0_FILT_ADR_ADR"           ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
+	{"TRA0_FILT_ADR_MSK"           ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
+	{"TRA0_FILT_CMD"               ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
+	{"TRA0_FILT_DID"               ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"TRA0_FILT_SID"               ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	569},
+	{"TRA0_INT_STATUS"             ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	570},
+	{"TRA0_READ_DAT"               ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	571},
+	{"TRA0_TRIG0_ADR_ADR"          ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	572},
+	{"TRA0_TRIG0_ADR_MSK"          ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	573},
+	{"TRA0_TRIG0_CMD"              ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	574},
+	{"TRA0_TRIG0_DID"              ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
+	{"TRA0_TRIG0_SID"              ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
+	{"TRA0_TRIG1_ADR_ADR"          ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	577},
+	{"TRA0_TRIG1_ADR_MSK"          ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	578},
+	{"TRA0_TRIG1_CMD"              ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	579},
+	{"TRA0_TRIG1_DID"              ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	580},
+	{"TRA0_TRIG1_SID"              ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	581},
 	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	582},
 	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	583},
 	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	584},
@@ -22283,27 +22283,27 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn58xxp1[] = {
 	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2518,	4,	2892},
 	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2519,	2,	2896},
 	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2520,	3,	2898},
-	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2521,	4,	2901},
-	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2522,	12,	2905},
-	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2523,	3,	2917},
-	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2524,	5,	2920},
-	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2525,	2,	2925},
-	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2526,	2,	2927},
-	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2527,	18,	2929},
-	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2528,	12,	2947},
-	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2529,	6,	2959},
-	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2530,	5,	2965},
-	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2531,	1,	2970},
-	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2532,	2,	2971},
-	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2533,	2,	2973},
-	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2534,	18,	2975},
-	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2535,	12,	2993},
-	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2536,	6,	3005},
-	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2537,	2,	3011},
-	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2538,	2,	3013},
-	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2539,	18,	3015},
-	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2540,	12,	3033},
-	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2541,	6,	3045},
+	{"cvmx_tra#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2521,	4,	2901},
+	{"cvmx_tra#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2522,	12,	2905},
+	{"cvmx_tra#_cycles_since"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2523,	3,	2917},
+	{"cvmx_tra#_cycles_since1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2524,	5,	2920},
+	{"cvmx_tra#_filt_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2525,	2,	2925},
+	{"cvmx_tra#_filt_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2526,	2,	2927},
+	{"cvmx_tra#_filt_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2527,	18,	2929},
+	{"cvmx_tra#_filt_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2528,	12,	2947},
+	{"cvmx_tra#_filt_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2529,	6,	2959},
+	{"cvmx_tra#_int_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2530,	5,	2965},
+	{"cvmx_tra#_read_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2531,	1,	2970},
+	{"cvmx_tra#_trig0_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2532,	2,	2971},
+	{"cvmx_tra#_trig0_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2533,	2,	2973},
+	{"cvmx_tra#_trig0_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2534,	18,	2975},
+	{"cvmx_tra#_trig0_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2535,	12,	2993},
+	{"cvmx_tra#_trig0_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2536,	6,	3005},
+	{"cvmx_tra#_trig1_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2537,	2,	3011},
+	{"cvmx_tra#_trig1_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2538,	2,	3013},
+	{"cvmx_tra#_trig1_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2539,	18,	3015},
+	{"cvmx_tra#_trig1_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2540,	12,	3033},
+	{"cvmx_tra#_trig1_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2541,	6,	3045},
 	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2542,	3,	3051},
 	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2543,	5,	3054},
 	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2544,	3,	3059},
@@ -24836,27 +24836,27 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	572},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	573},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	574},
-	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
-	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	577},
-	{"TRA_CYCLES_SINCE1"           ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	578},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	579},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	580},
-	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	581},
-	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	582},
-	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	583},
-	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	584},
-	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	585},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	586},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	587},
-	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	588},
-	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	589},
-	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	590},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	591},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	592},
-	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	593},
-	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	594},
-	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	595},
+	{"TRA0_BIST_STATUS"            ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
+	{"TRA0_CTL"                    ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
+	{"TRA0_CYCLES_SINCE"           ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	577},
+	{"TRA0_CYCLES_SINCE1"          ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	578},
+	{"TRA0_FILT_ADR_ADR"           ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	579},
+	{"TRA0_FILT_ADR_MSK"           ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	580},
+	{"TRA0_FILT_CMD"               ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	581},
+	{"TRA0_FILT_DID"               ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	582},
+	{"TRA0_FILT_SID"               ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	583},
+	{"TRA0_INT_STATUS"             ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	584},
+	{"TRA0_READ_DAT"               ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	585},
+	{"TRA0_TRIG0_ADR_ADR"          ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	586},
+	{"TRA0_TRIG0_ADR_MSK"          ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	587},
+	{"TRA0_TRIG0_CMD"              ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	588},
+	{"TRA0_TRIG0_DID"              ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	589},
+	{"TRA0_TRIG0_SID"              ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	590},
+	{"TRA0_TRIG1_ADR_ADR"          ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	591},
+	{"TRA0_TRIG1_ADR_MSK"          ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	592},
+	{"TRA0_TRIG1_CMD"              ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	593},
+	{"TRA0_TRIG1_DID"              ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	594},
+	{"TRA0_TRIG1_SID"              ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	595},
 	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	596},
 	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	597},
 	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	598},
@@ -27434,7 +27434,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
 	{"RESERVED_32_63"              ,	32,	32,	505,	"RAZ",	1,	1,	0,	0},
 	{"NOS_CNT"                     ,	0,	12,	506,	"RO",	0,	1,	0ull,	0},
 	{"RESERVED_12_63"              ,	12,	52,	506,	"RAZ",	1,	1,	0,	0},
-	{"NW_TIM"                      ,	0,	10,	507,	"R/W",	0,	0,	0ull,	1023ull},
+	{"NW_TIM"                      ,	0,	10,	507,	"R/W",	0,	0,	0ull,	4ull},
 	{"RESERVED_10_63"              ,	10,	54,	507,	"RAZ",	1,	1,	0,	0},
 	{"RST_MSK"                     ,	0,	8,	508,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_8_63"               ,	8,	56,	508,	"RAZ",	1,	1,	0,	0},
@@ -27571,8 +27571,8 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
 	{"RESERVED_9_63"               ,	9,	55,	532,	"RAZ",	0,	0,	0ull,	0ull},
 	{"SRX4CMP"                     ,	0,	10,	533,	"R/W",	0,	0,	239ull,	239ull},
 	{"RESERVED_10_15"              ,	10,	6,	533,	"RAZ",	0,	0,	0ull,	0ull},
-	{"STX4PCMP"                    ,	16,	4,	533,	"R/W",	0,	0,	3ull,	3ull},
-	{"STX4NCMP"                    ,	20,	4,	533,	"R/W",	0,	0,	12ull,	12ull},
+	{"STX4PCMP"                    ,	16,	4,	533,	"R/W",	0,	1,	3ull,	0},
+	{"STX4NCMP"                    ,	20,	4,	533,	"R/W",	0,	1,	12ull,	0},
 	{"RESERVED_24_63"              ,	24,	40,	533,	"RAZ",	0,	0,	0ull,	0ull},
 	{"ERRCNT"                      ,	0,	4,	534,	"R/W",	0,	0,	0ull,	3ull},
 	{"RESERVED_4_5"                ,	4,	2,	534,	"RAZ",	0,	0,	0ull,	0ull},
@@ -28531,27 +28531,27 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn58xx[] = {
 	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2716,	4,	2975},
 	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2717,	2,	2979},
 	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2718,	3,	2981},
-	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2719,	4,	2984},
-	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2720,	12,	2988},
-	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2721,	3,	3000},
-	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2722,	5,	3003},
-	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2723,	2,	3008},
-	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2724,	2,	3010},
-	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2725,	18,	3012},
-	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2726,	12,	3030},
-	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2727,	6,	3042},
-	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2728,	5,	3048},
-	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2729,	1,	3053},
-	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2730,	2,	3054},
-	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2731,	2,	3056},
-	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2732,	18,	3058},
-	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2733,	12,	3076},
-	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2734,	6,	3088},
-	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2735,	2,	3094},
-	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2736,	2,	3096},
-	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2737,	18,	3098},
-	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2738,	12,	3116},
-	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2739,	6,	3128},
+	{"cvmx_tra#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2719,	4,	2984},
+	{"cvmx_tra#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2720,	12,	2988},
+	{"cvmx_tra#_cycles_since"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2721,	3,	3000},
+	{"cvmx_tra#_cycles_since1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2722,	5,	3003},
+	{"cvmx_tra#_filt_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2723,	2,	3008},
+	{"cvmx_tra#_filt_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2724,	2,	3010},
+	{"cvmx_tra#_filt_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2725,	18,	3012},
+	{"cvmx_tra#_filt_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2726,	12,	3030},
+	{"cvmx_tra#_filt_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2727,	6,	3042},
+	{"cvmx_tra#_int_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2728,	5,	3048},
+	{"cvmx_tra#_read_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2729,	1,	3053},
+	{"cvmx_tra#_trig0_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2730,	2,	3054},
+	{"cvmx_tra#_trig0_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2731,	2,	3056},
+	{"cvmx_tra#_trig0_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2732,	18,	3058},
+	{"cvmx_tra#_trig0_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2733,	12,	3076},
+	{"cvmx_tra#_trig0_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2734,	6,	3088},
+	{"cvmx_tra#_trig1_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2735,	2,	3094},
+	{"cvmx_tra#_trig1_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2736,	2,	3096},
+	{"cvmx_tra#_trig1_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2737,	18,	3098},
+	{"cvmx_tra#_trig1_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2738,	12,	3116},
+	{"cvmx_tra#_trig1_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2739,	6,	3128},
 	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2740,	3,	3134},
 	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2741,	5,	3137},
 	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2742,	3,	3142},
@@ -31282,27 +31282,27 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	582},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	583},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	584},
-	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	585},
-	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	586},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	587},
-	{"TRA_CYCLES_SINCE1"           ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	588},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	589},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	590},
-	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	591},
-	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	592},
-	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	593},
-	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	594},
-	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	595},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	596},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	597},
-	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	598},
-	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	599},
-	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	600},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	601},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	602},
-	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	603},
-	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	604},
-	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"TRA0_BIST_STATUS"            ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	585},
+	{"TRA0_CTL"                    ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	586},
+	{"TRA0_CYCLES_SINCE"           ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	587},
+	{"TRA0_CYCLES_SINCE1"          ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	588},
+	{"TRA0_FILT_ADR_ADR"           ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	589},
+	{"TRA0_FILT_ADR_MSK"           ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	590},
+	{"TRA0_FILT_CMD"               ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	591},
+	{"TRA0_FILT_DID"               ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	592},
+	{"TRA0_FILT_SID"               ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	593},
+	{"TRA0_INT_STATUS"             ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	594},
+	{"TRA0_READ_DAT"               ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	595},
+	{"TRA0_TRIG0_ADR_ADR"          ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	596},
+	{"TRA0_TRIG0_ADR_MSK"          ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	597},
+	{"TRA0_TRIG0_CMD"              ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	598},
+	{"TRA0_TRIG0_DID"              ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	599},
+	{"TRA0_TRIG0_SID"              ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	600},
+	{"TRA0_TRIG1_ADR_ADR"          ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	601},
+	{"TRA0_TRIG1_ADR_MSK"          ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	602},
+	{"TRA0_TRIG1_CMD"              ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	603},
+	{"TRA0_TRIG1_DID"              ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	604},
+	{"TRA0_TRIG1_SID"              ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
 	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	606},
 	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
 	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	608},
@@ -34100,8 +34100,8 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xx[] = {
 	{"RESERVED_9_63"               ,	9,	55,	542,	"RAZ",	0,	0,	0ull,	0ull},
 	{"SRX4CMP"                     ,	0,	10,	543,	"R/W",	0,	0,	239ull,	239ull},
 	{"RESERVED_10_15"              ,	10,	6,	543,	"RAZ",	0,	0,	0ull,	0ull},
-	{"STX4PCMP"                    ,	16,	4,	543,	"R/W",	0,	0,	3ull,	3ull},
-	{"STX4NCMP"                    ,	20,	4,	543,	"R/W",	0,	0,	12ull,	12ull},
+	{"STX4PCMP"                    ,	16,	4,	543,	"R/W",	0,	1,	3ull,	0},
+	{"STX4NCMP"                    ,	20,	4,	543,	"R/W",	0,	1,	12ull,	0},
 	{"RESERVED_24_63"              ,	24,	40,	543,	"RAZ",	0,	0,	0ull,	0ull},
 	{"ERRCNT"                      ,	0,	4,	544,	"R/W",	0,	0,	0ull,	3ull},
 	{"RESERVED_4_5"                ,	4,	2,	544,	"RAZ",	0,	0,	0ull,	0ull},
@@ -35274,27 +35274,27 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn56xxp1[] = {
 	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2343,	4,	4124},
 	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2344,	2,	4128},
 	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2345,	3,	4130},
-	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2346,	4,	4133},
-	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2347,	12,	4137},
-	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2348,	3,	4149},
-	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2349,	5,	4152},
-	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2350,	2,	4157},
-	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2351,	2,	4159},
-	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2352,	18,	4161},
-	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2353,	12,	4179},
-	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2354,	6,	4191},
-	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2355,	5,	4197},
-	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2356,	1,	4202},
-	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2357,	2,	4203},
-	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2358,	2,	4205},
-	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2359,	18,	4207},
-	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2360,	12,	4225},
-	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2361,	6,	4237},
-	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2362,	2,	4243},
-	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2363,	2,	4245},
-	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2364,	18,	4247},
-	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2365,	12,	4265},
-	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2366,	6,	4277},
+	{"cvmx_tra#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2346,	4,	4133},
+	{"cvmx_tra#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2347,	12,	4137},
+	{"cvmx_tra#_cycles_since"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2348,	3,	4149},
+	{"cvmx_tra#_cycles_since1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2349,	5,	4152},
+	{"cvmx_tra#_filt_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2350,	2,	4157},
+	{"cvmx_tra#_filt_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2351,	2,	4159},
+	{"cvmx_tra#_filt_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2352,	18,	4161},
+	{"cvmx_tra#_filt_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2353,	12,	4179},
+	{"cvmx_tra#_filt_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2354,	6,	4191},
+	{"cvmx_tra#_int_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2355,	5,	4197},
+	{"cvmx_tra#_read_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2356,	1,	4202},
+	{"cvmx_tra#_trig0_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2357,	2,	4203},
+	{"cvmx_tra#_trig0_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2358,	2,	4205},
+	{"cvmx_tra#_trig0_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2359,	18,	4207},
+	{"cvmx_tra#_trig0_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2360,	12,	4225},
+	{"cvmx_tra#_trig0_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2361,	6,	4237},
+	{"cvmx_tra#_trig1_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2362,	2,	4243},
+	{"cvmx_tra#_trig1_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2363,	2,	4245},
+	{"cvmx_tra#_trig1_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2364,	18,	4247},
+	{"cvmx_tra#_trig1_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2365,	12,	4265},
+	{"cvmx_tra#_trig1_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2366,	6,	4277},
 	{"cvmx_usbc#_daint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2367,	2,	4283},
 	{"cvmx_usbc#_daintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2368,	2,	4285},
 	{"cvmx_usbc#_dcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2369,	8,	4287},
@@ -37727,27 +37727,27 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
-	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
-	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
-	{"TRA_CYCLES_SINCE1"           ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
-	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
-	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
-	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
-	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
-	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
-	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
-	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
-	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
-	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	817},
-	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
-	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	819},
+	{"TRA0_BIST_STATUS"            ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"TRA0_CTL"                    ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"TRA0_CYCLES_SINCE"           ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"TRA0_CYCLES_SINCE1"          ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"TRA0_FILT_ADR_ADR"           ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"TRA0_FILT_ADR_MSK"           ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"TRA0_FILT_CMD"               ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"TRA0_FILT_DID"               ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
+	{"TRA0_FILT_SID"               ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"TRA0_INT_STATUS"             ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"TRA0_READ_DAT"               ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
+	{"TRA0_TRIG0_ADR_ADR"          ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
+	{"TRA0_TRIG0_ADR_MSK"          ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
+	{"TRA0_TRIG0_CMD"              ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
+	{"TRA0_TRIG0_DID"              ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
+	{"TRA0_TRIG0_SID"              ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"TRA0_TRIG1_ADR_ADR"          ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
+	{"TRA0_TRIG1_ADR_MSK"          ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"TRA0_TRIG1_CMD"              ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	817},
+	{"TRA0_TRIG1_DID"              ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
+	{"TRA0_TRIG1_SID"              ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	819},
 	{"USBC0_DAINT"                 ,	   0x16f0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	820},
 	{"USBC0_DAINTMSK"              ,	   0x16f001000081cull,	CVMX_CSR_DB_TYPE_NCB,	32,	821},
 	{"USBC0_DCFG"                  ,	   0x16f0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	822},
@@ -39660,7 +39660,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"IPFDAT"                      ,	2,	1,	395,	"RO",	0,	0,	0ull,	0ull},
 	{"MRQDAT"                      ,	3,	1,	395,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_4_63"               ,	4,	60,	395,	"RAZ",	0,	0,	0ull,	0ull},
-	{"MRQ_HWM"                     ,	0,	2,	396,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRQ_HWM"                     ,	0,	2,	396,	"R/W",	0,	0,	0ull,	1ull},
 	{"NBTARB"                      ,	2,	1,	396,	"R/W",	0,	0,	0ull,	0ull},
 	{"LENDIAN"                     ,	3,	1,	396,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	4,	1,	396,	"RAZ",	0,	0,	0ull,	0ull},
@@ -40488,8 +40488,8 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"DWORD2"                      ,	0,	32,	512,	"RO",	0,	0,	0ull,	0ull},
 	{"DWORD3"                      ,	0,	32,	513,	"RO",	0,	0,	0ull,	0ull},
 	{"DWORD4"                      ,	0,	32,	514,	"RO",	0,	0,	0ull,	0ull},
-	{"RTLTL"                       ,	0,	16,	515,	"R/W",	0,	0,	4143ull,	4143ull},
-	{"RTL"                         ,	16,	16,	515,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"RTLTL"                       ,	0,	16,	515,	"R/W",	0,	1,	4143ull,	0},
+	{"RTL"                         ,	16,	16,	515,	"R/W",	0,	1,	12429ull,	0},
 	{"OMR"                         ,	0,	32,	516,	"R/W",	0,	1,	4294967295ull,	0},
 	{"LINK_NUM"                    ,	0,	8,	517,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_8_14"               ,	8,	7,	517,	"RAZ",	1,	1,	0,	0},
@@ -40941,8 +40941,8 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"AEIMN"                       ,	27,	5,	589,	"R/W",	0,	0,	0ull,	0ull},
 	{"ECSI"                        ,	0,	16,	590,	"RO",	0,	0,	0ull,	0ull},
 	{"EFNFSI"                      ,	16,	16,	590,	"RO",	0,	0,	0ull,	0ull},
-	{"RTLTL"                       ,	0,	16,	591,	"R/W",	0,	0,	4143ull,	4143ull},
-	{"RTL"                         ,	16,	16,	591,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"RTLTL"                       ,	0,	16,	591,	"R/W",	0,	1,	4143ull,	0},
+	{"RTL"                         ,	16,	16,	591,	"R/W",	0,	1,	12429ull,	0},
 	{"OMR"                         ,	0,	32,	592,	"R/W",	0,	1,	4294967295ull,	0},
 	{"LINK_NUM"                    ,	0,	8,	593,	"R/W",	0,	0,	4ull,	4ull},
 	{"RESERVED_8_14"               ,	8,	7,	593,	"RAZ",	1,	1,	0,	0},
@@ -43623,27 +43623,27 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn56xx[] = {
 	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2967,	4,	4524},
 	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2968,	2,	4528},
 	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2969,	3,	4530},
-	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2970,	4,	4533},
-	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2971,	12,	4537},
-	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2972,	3,	4549},
-	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2973,	5,	4552},
-	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2974,	2,	4557},
-	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2975,	2,	4559},
-	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2976,	18,	4561},
-	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2977,	12,	4579},
-	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2978,	6,	4591},
-	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2979,	5,	4597},
-	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2980,	1,	4602},
-	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2981,	2,	4603},
-	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2982,	2,	4605},
-	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2983,	18,	4607},
-	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2984,	12,	4625},
-	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2985,	6,	4637},
-	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2986,	2,	4643},
-	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2987,	2,	4645},
-	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2988,	18,	4647},
-	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2989,	12,	4665},
-	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2990,	6,	4677},
+	{"cvmx_tra#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2970,	4,	4533},
+	{"cvmx_tra#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2971,	12,	4537},
+	{"cvmx_tra#_cycles_since"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2972,	3,	4549},
+	{"cvmx_tra#_cycles_since1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2973,	5,	4552},
+	{"cvmx_tra#_filt_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2974,	2,	4557},
+	{"cvmx_tra#_filt_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2975,	2,	4559},
+	{"cvmx_tra#_filt_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2976,	18,	4561},
+	{"cvmx_tra#_filt_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2977,	12,	4579},
+	{"cvmx_tra#_filt_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2978,	6,	4591},
+	{"cvmx_tra#_int_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2979,	5,	4597},
+	{"cvmx_tra#_read_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2980,	1,	4602},
+	{"cvmx_tra#_trig0_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2981,	2,	4603},
+	{"cvmx_tra#_trig0_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2982,	2,	4605},
+	{"cvmx_tra#_trig0_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2983,	18,	4607},
+	{"cvmx_tra#_trig0_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2984,	12,	4625},
+	{"cvmx_tra#_trig0_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2985,	6,	4637},
+	{"cvmx_tra#_trig1_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2986,	2,	4643},
+	{"cvmx_tra#_trig1_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2987,	2,	4645},
+	{"cvmx_tra#_trig1_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2988,	18,	4647},
+	{"cvmx_tra#_trig1_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2989,	12,	4665},
+	{"cvmx_tra#_trig1_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2990,	6,	4677},
 	{"cvmx_usbc#_daint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2991,	2,	4683},
 	{"cvmx_usbc#_daintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2992,	2,	4685},
 	{"cvmx_usbc#_dcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2993,	8,	4687},
@@ -46700,27 +46700,27 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	862},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	863},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	864},
-	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	865},
-	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	866},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	867},
-	{"TRA_CYCLES_SINCE1"           ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	868},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	869},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	870},
-	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	871},
-	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
-	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	873},
-	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	874},
-	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	875},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	876},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	877},
-	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	878},
-	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
-	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
-	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
-	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
-	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
+	{"TRA0_BIST_STATUS"            ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	865},
+	{"TRA0_CTL"                    ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	866},
+	{"TRA0_CYCLES_SINCE"           ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	867},
+	{"TRA0_CYCLES_SINCE1"          ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	868},
+	{"TRA0_FILT_ADR_ADR"           ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	869},
+	{"TRA0_FILT_ADR_MSK"           ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	870},
+	{"TRA0_FILT_CMD"               ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	871},
+	{"TRA0_FILT_DID"               ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"TRA0_FILT_SID"               ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	873},
+	{"TRA0_INT_STATUS"             ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	874},
+	{"TRA0_READ_DAT"               ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	875},
+	{"TRA0_TRIG0_ADR_ADR"          ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	876},
+	{"TRA0_TRIG0_ADR_MSK"          ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	877},
+	{"TRA0_TRIG0_CMD"              ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	878},
+	{"TRA0_TRIG0_DID"              ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
+	{"TRA0_TRIG0_SID"              ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
+	{"TRA0_TRIG1_ADR_ADR"          ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
+	{"TRA0_TRIG1_ADR_MSK"          ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
+	{"TRA0_TRIG1_CMD"              ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
+	{"TRA0_TRIG1_DID"              ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
+	{"TRA0_TRIG1_SID"              ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
 	{"USBC0_DAINT"                 ,	   0x16f0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	886},
 	{"USBC0_DAINTMSK"              ,	   0x16f001000081cull,	CVMX_CSR_DB_TYPE_NCB,	32,	887},
 	{"USBC0_DCFG"                  ,	   0x16f0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	888},
@@ -47662,7 +47662,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"RESERVED_32_63"              ,	32,	32,	173,	"RAZ",	1,	1,	0,	0},
 	{"SEND"                        ,	0,	1,	174,	"R/W",	0,	0,	1ull,	1ull},
 	{"RESERVED_1_63"               ,	1,	63,	174,	"RAZ",	1,	1,	0,	0},
-	{"ALIGN"                       ,	0,	1,	175,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALIGN"                       ,	0,	1,	175,	"R/W",	0,	0,	1ull,	0ull},
 	{"RESERVED_1_63"               ,	1,	63,	175,	"RAZ",	1,	1,	0,	0},
 	{"SLOT"                        ,	0,	10,	176,	"R/W",	0,	0,	512ull,	512ull},
 	{"RESERVED_10_63"              ,	10,	54,	176,	"RAZ",	1,	1,	0,	0},
@@ -48769,7 +48769,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"IPFDAT"                      ,	2,	1,	412,	"RO",	0,	0,	0ull,	0ull},
 	{"MRQDAT"                      ,	3,	1,	412,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_4_63"               ,	4,	60,	412,	"RAZ",	0,	0,	0ull,	0ull},
-	{"MRQ_HWM"                     ,	0,	2,	413,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRQ_HWM"                     ,	0,	2,	413,	"R/W",	0,	0,	0ull,	1ull},
 	{"NBTARB"                      ,	2,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
 	{"LENDIAN"                     ,	3,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	4,	1,	413,	"RAZ",	0,	0,	0ull,	0ull},
@@ -49809,8 +49809,8 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"DWORD2"                      ,	0,	32,	575,	"RO",	0,	0,	0ull,	0ull},
 	{"DWORD3"                      ,	0,	32,	576,	"RO",	0,	0,	0ull,	0ull},
 	{"DWORD4"                      ,	0,	32,	577,	"RO",	0,	0,	0ull,	0ull},
-	{"RTLTL"                       ,	0,	16,	578,	"R/W",	0,	0,	4143ull,	4143ull},
-	{"RTL"                         ,	16,	16,	578,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"RTLTL"                       ,	0,	16,	578,	"R/W",	0,	1,	4143ull,	0},
+	{"RTL"                         ,	16,	16,	578,	"R/W",	0,	1,	12429ull,	0},
 	{"OMR"                         ,	0,	32,	579,	"R/W",	0,	1,	4294967295ull,	0},
 	{"LINK_NUM"                    ,	0,	8,	580,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_8_14"               ,	8,	7,	580,	"RAZ",	1,	1,	0,	0},
@@ -50262,8 +50262,8 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"AEIMN"                       ,	27,	5,	652,	"R/W",	0,	0,	0ull,	0ull},
 	{"ECSI"                        ,	0,	16,	653,	"RO",	0,	0,	0ull,	0ull},
 	{"EFNFSI"                      ,	16,	16,	653,	"RO",	0,	0,	0ull,	0ull},
-	{"RTLTL"                       ,	0,	16,	654,	"R/W",	0,	0,	4143ull,	4143ull},
-	{"RTL"                         ,	16,	16,	654,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"RTLTL"                       ,	0,	16,	654,	"R/W",	0,	1,	4143ull,	0},
+	{"RTL"                         ,	16,	16,	654,	"R/W",	0,	1,	12429ull,	0},
 	{"OMR"                         ,	0,	32,	655,	"R/W",	0,	1,	4294967295ull,	0},
 	{"LINK_NUM"                    ,	0,	8,	656,	"R/W",	0,	0,	4ull,	4ull},
 	{"RESERVED_8_14"               ,	8,	7,	656,	"RAZ",	1,	1,	0,	0},
@@ -51195,7 +51195,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"RESERVED_32_63"              ,	32,	32,	810,	"RAZ",	1,	1,	0,	0},
 	{"NOS_CNT"                     ,	0,	12,	811,	"RO",	0,	1,	0ull,	0},
 	{"RESERVED_12_63"              ,	12,	52,	811,	"RAZ",	1,	1,	0,	0},
-	{"NW_TIM"                      ,	0,	10,	812,	"R/W",	0,	0,	0ull,	1023ull},
+	{"NW_TIM"                      ,	0,	10,	812,	"R/W",	0,	0,	0ull,	4ull},
 	{"RESERVED_10_63"              ,	10,	54,	812,	"RAZ",	1,	1,	0,	0},
 	{"RST_MSK"                     ,	0,	8,	813,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_8_63"               ,	8,	56,	813,	"RAZ",	1,	1,	0,	0},
@@ -56481,7 +56481,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn50xx[] = {
 	{"RESERVED_32_63"              ,	32,	32,	474,	"RAZ",	1,	1,	0,	0},
 	{"NOS_CNT"                     ,	0,	9,	475,	"RO",	0,	1,	0ull,	0},
 	{"RESERVED_9_63"               ,	9,	55,	475,	"RAZ",	1,	1,	0,	0},
-	{"NW_TIM"                      ,	0,	10,	476,	"R/W",	0,	0,	0ull,	1023ull},
+	{"NW_TIM"                      ,	0,	10,	476,	"R/W",	0,	0,	0ull,	4ull},
 	{"RESERVED_10_63"              ,	10,	54,	476,	"RAZ",	1,	1,	0,	0},
 	{"RST_MSK"                     ,	0,	8,	477,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_8_63"               ,	8,	56,	477,	"RAZ",	1,	1,	0,	0},
@@ -57971,27 +57971,27 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn52xxp1[] = {
 	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1815,	4,	4295},
 	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1816,	2,	4299},
 	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1817,	3,	4301},
-	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1818,	4,	4304},
-	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1819,	12,	4308},
-	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1820,	3,	4320},
-	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1821,	5,	4323},
-	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1822,	2,	4328},
-	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1823,	2,	4330},
-	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1824,	18,	4332},
-	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1825,	12,	4350},
-	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1826,	6,	4362},
-	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1827,	5,	4368},
-	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1828,	1,	4373},
-	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1829,	2,	4374},
-	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1830,	2,	4376},
-	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1831,	18,	4378},
-	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1832,	12,	4396},
-	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1833,	6,	4408},
-	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1834,	2,	4414},
-	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1835,	2,	4416},
-	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1836,	18,	4418},
-	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1837,	12,	4436},
-	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1838,	6,	4448},
+	{"cvmx_tra#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1818,	4,	4304},
+	{"cvmx_tra#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1819,	12,	4308},
+	{"cvmx_tra#_cycles_since"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1820,	3,	4320},
+	{"cvmx_tra#_cycles_since1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1821,	5,	4323},
+	{"cvmx_tra#_filt_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1822,	2,	4328},
+	{"cvmx_tra#_filt_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1823,	2,	4330},
+	{"cvmx_tra#_filt_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1824,	18,	4332},
+	{"cvmx_tra#_filt_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1825,	12,	4350},
+	{"cvmx_tra#_filt_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1826,	6,	4362},
+	{"cvmx_tra#_int_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1827,	5,	4368},
+	{"cvmx_tra#_read_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1828,	1,	4373},
+	{"cvmx_tra#_trig0_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1829,	2,	4374},
+	{"cvmx_tra#_trig0_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1830,	2,	4376},
+	{"cvmx_tra#_trig0_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1831,	18,	4378},
+	{"cvmx_tra#_trig0_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1832,	12,	4396},
+	{"cvmx_tra#_trig0_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1833,	6,	4408},
+	{"cvmx_tra#_trig1_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1834,	2,	4414},
+	{"cvmx_tra#_trig1_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1835,	2,	4416},
+	{"cvmx_tra#_trig1_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1836,	18,	4418},
+	{"cvmx_tra#_trig1_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1837,	12,	4436},
+	{"cvmx_tra#_trig1_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1838,	6,	4448},
 	{"cvmx_usbc#_daint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	1839,	2,	4454},
 	{"cvmx_usbc#_daintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1841,	2,	4456},
 	{"cvmx_usbc#_dcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1843,	8,	4458},
@@ -59889,27 +59889,27 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
-	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
-	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
-	{"TRA_CYCLES_SINCE1"           ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
-	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
-	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
-	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
-	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	817},
-	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	819},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	820},
-	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	821},
-	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	822},
-	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	823},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
-	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
-	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
-	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"TRA0_BIST_STATUS"            ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"TRA0_CTL"                    ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
+	{"TRA0_CYCLES_SINCE"           ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
+	{"TRA0_CYCLES_SINCE1"          ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
+	{"TRA0_FILT_ADR_ADR"           ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
+	{"TRA0_FILT_ADR_MSK"           ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
+	{"TRA0_FILT_CMD"               ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"TRA0_FILT_DID"               ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
+	{"TRA0_FILT_SID"               ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"TRA0_INT_STATUS"             ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	817},
+	{"TRA0_READ_DAT"               ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
+	{"TRA0_TRIG0_ADR_ADR"          ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	819},
+	{"TRA0_TRIG0_ADR_MSK"          ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	820},
+	{"TRA0_TRIG0_CMD"              ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	821},
+	{"TRA0_TRIG0_DID"              ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	822},
+	{"TRA0_TRIG0_SID"              ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	823},
+	{"TRA0_TRIG1_ADR_ADR"          ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"TRA0_TRIG1_ADR_MSK"          ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"TRA0_TRIG1_CMD"              ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"TRA0_TRIG1_DID"              ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"TRA0_TRIG1_SID"              ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
 	{"USBC0_DAINT"                 ,	   0x16f0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
 	{"USBC1_DAINT"                 ,	   0x17f0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
 	{"USBC0_DAINTMSK"              ,	   0x16f001000081cull,	CVMX_CSR_DB_TYPE_NCB,	32,	830},
@@ -60900,7 +60900,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"RESERVED_32_63"              ,	32,	32,	158,	"RAZ",	1,	1,	0,	0},
 	{"SEND"                        ,	0,	1,	159,	"R/W",	0,	0,	1ull,	1ull},
 	{"RESERVED_1_63"               ,	1,	63,	159,	"RAZ",	1,	1,	0,	0},
-	{"ALIGN"                       ,	0,	1,	160,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALIGN"                       ,	0,	1,	160,	"R/W",	0,	0,	1ull,	0ull},
 	{"RESERVED_1_63"               ,	1,	63,	160,	"RAZ",	1,	1,	0,	0},
 	{"SLOT"                        ,	0,	10,	161,	"R/W",	0,	0,	512ull,	512ull},
 	{"RESERVED_10_63"              ,	10,	54,	161,	"RAZ",	1,	1,	0,	0},
@@ -62027,7 +62027,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"IPFDAT"                      ,	2,	1,	400,	"RO",	0,	0,	0ull,	0ull},
 	{"MRQDAT"                      ,	3,	1,	400,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_4_63"               ,	4,	60,	400,	"RAZ",	0,	0,	0ull,	0ull},
-	{"MRQ_HWM"                     ,	0,	2,	401,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRQ_HWM"                     ,	0,	2,	401,	"R/W",	0,	0,	0ull,	1ull},
 	{"NBTARB"                      ,	2,	1,	401,	"R/W",	0,	0,	0ull,	0ull},
 	{"LENDIAN"                     ,	3,	1,	401,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	4,	1,	401,	"R/W",	0,	0,	1ull,	0ull},
@@ -64288,7 +64288,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"RESERVED_32_63"              ,	32,	32,	753,	"RAZ",	1,	1,	0,	0},
 	{"NOS_CNT"                     ,	0,	10,	754,	"RO",	0,	1,	0ull,	0},
 	{"RESERVED_10_63"              ,	10,	54,	754,	"RAZ",	1,	1,	0,	0},
-	{"NW_TIM"                      ,	0,	10,	755,	"R/W",	0,	0,	0ull,	1023ull},
+	{"NW_TIM"                      ,	0,	10,	755,	"R/W",	0,	0,	0ull,	4ull},
 	{"RESERVED_10_63"              ,	10,	54,	755,	"RAZ",	1,	1,	0,	0},
 	{"RST_MSK"                     ,	0,	8,	756,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_8_63"               ,	8,	56,	756,	"RAZ",	1,	1,	0,	0},
@@ -66084,27 +66084,27 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn52xx[] = {
 	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2344,	4,	4673},
 	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2345,	2,	4677},
 	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2346,	3,	4679},
-	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2347,	4,	4682},
-	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2348,	12,	4686},
-	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2349,	3,	4698},
-	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2350,	5,	4701},
-	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2351,	2,	4706},
-	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2352,	2,	4708},
-	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2353,	18,	4710},
-	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2354,	12,	4728},
-	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2355,	6,	4740},
-	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2356,	5,	4746},
-	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2357,	1,	4751},
-	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2358,	2,	4752},
-	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2359,	2,	4754},
-	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2360,	18,	4756},
-	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2361,	12,	4774},
-	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2362,	6,	4786},
-	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2363,	2,	4792},
-	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2364,	2,	4794},
-	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2365,	18,	4796},
-	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2366,	12,	4814},
-	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2367,	6,	4826},
+	{"cvmx_tra#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2347,	4,	4682},
+	{"cvmx_tra#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2348,	12,	4686},
+	{"cvmx_tra#_cycles_since"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2349,	3,	4698},
+	{"cvmx_tra#_cycles_since1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2350,	5,	4701},
+	{"cvmx_tra#_filt_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2351,	2,	4706},
+	{"cvmx_tra#_filt_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2352,	2,	4708},
+	{"cvmx_tra#_filt_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2353,	18,	4710},
+	{"cvmx_tra#_filt_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2354,	12,	4728},
+	{"cvmx_tra#_filt_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2355,	6,	4740},
+	{"cvmx_tra#_int_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2356,	5,	4746},
+	{"cvmx_tra#_read_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2357,	1,	4751},
+	{"cvmx_tra#_trig0_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2358,	2,	4752},
+	{"cvmx_tra#_trig0_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2359,	2,	4754},
+	{"cvmx_tra#_trig0_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2360,	18,	4756},
+	{"cvmx_tra#_trig0_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2361,	12,	4774},
+	{"cvmx_tra#_trig0_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2362,	6,	4786},
+	{"cvmx_tra#_trig1_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2363,	2,	4792},
+	{"cvmx_tra#_trig1_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2364,	2,	4794},
+	{"cvmx_tra#_trig1_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2365,	18,	4796},
+	{"cvmx_tra#_trig1_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2366,	12,	4814},
+	{"cvmx_tra#_trig1_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2367,	6,	4826},
 	{"cvmx_usbc#_daint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2368,	2,	4832},
 	{"cvmx_usbc#_daintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2370,	2,	4834},
 	{"cvmx_usbc#_dcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2372,	8,	4836},
@@ -68531,27 +68531,27 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	876},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	877},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	878},
-	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
-	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
-	{"TRA_CYCLES_SINCE1"           ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
-	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
-	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	886},
-	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	887},
-	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	888},
-	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	889},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	890},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	891},
-	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	892},
-	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	893},
-	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	894},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	895},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	896},
-	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
-	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	898},
-	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	899},
+	{"TRA0_BIST_STATUS"            ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
+	{"TRA0_CTL"                    ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
+	{"TRA0_CYCLES_SINCE"           ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
+	{"TRA0_CYCLES_SINCE1"          ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
+	{"TRA0_FILT_ADR_ADR"           ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
+	{"TRA0_FILT_ADR_MSK"           ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
+	{"TRA0_FILT_CMD"               ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
+	{"TRA0_FILT_DID"               ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	886},
+	{"TRA0_FILT_SID"               ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	887},
+	{"TRA0_INT_STATUS"             ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	888},
+	{"TRA0_READ_DAT"               ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	889},
+	{"TRA0_TRIG0_ADR_ADR"          ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	890},
+	{"TRA0_TRIG0_ADR_MSK"          ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	891},
+	{"TRA0_TRIG0_CMD"              ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	892},
+	{"TRA0_TRIG0_DID"              ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	893},
+	{"TRA0_TRIG0_SID"              ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	894},
+	{"TRA0_TRIG1_ADR_ADR"          ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	895},
+	{"TRA0_TRIG1_ADR_MSK"          ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	896},
+	{"TRA0_TRIG1_CMD"              ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"TRA0_TRIG1_DID"              ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	898},
+	{"TRA0_TRIG1_SID"              ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	899},
 	{"USBC0_DAINT"                 ,	   0x16f0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	900},
 	{"USBC1_DAINT"                 ,	   0x17f0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	900},
 	{"USBC0_DAINTMSK"              ,	   0x16f001000081cull,	CVMX_CSR_DB_TYPE_NCB,	32,	901},
@@ -70831,7 +70831,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"IPFDAT"                      ,	2,	1,	417,	"RO",	0,	0,	0ull,	0ull},
 	{"MRQDAT"                      ,	3,	1,	417,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_4_63"               ,	4,	60,	417,	"RAZ",	0,	0,	0ull,	0ull},
-	{"MRQ_HWM"                     ,	0,	2,	418,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRQ_HWM"                     ,	0,	2,	418,	"R/W",	0,	0,	0ull,	1ull},
 	{"NBTARB"                      ,	2,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
 	{"LENDIAN"                     ,	3,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	4,	1,	418,	"R/W",	0,	0,	1ull,	0ull},
@@ -74223,6 +74223,15016 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"TXRISETUNE"                  ,	63,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
 	{NULL,0,0,0,0,0,0,0,0}
 };
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn61xx[] = {
+	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
+	{"cvmx_agl_gmx_bad_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	0,	14,	0},
+	{"cvmx_agl_gmx_bist"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1,	2,	14},
+	{"cvmx_agl_gmx_prt#_cfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2,	13,	16},
+	{"cvmx_agl_gmx_rx#_adr_cam0"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	4,	1,	29},
+	{"cvmx_agl_gmx_rx#_adr_cam1"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	6,	1,	30},
+	{"cvmx_agl_gmx_rx#_adr_cam2"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8,	1,	31},
+	{"cvmx_agl_gmx_rx#_adr_cam3"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	10,	1,	32},
+	{"cvmx_agl_gmx_rx#_adr_cam4"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	12,	1,	33},
+	{"cvmx_agl_gmx_rx#_adr_cam5"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	14,	1,	34},
+	{"cvmx_agl_gmx_rx#_adr_cam_en" ,	CVMX_CSR_DB_TYPE_RSL,	64,	16,	2,	35},
+	{"cvmx_agl_gmx_rx#_adr_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	18,	4,	37},
+	{"cvmx_agl_gmx_rx#_decision"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	20,	2,	41},
+	{"cvmx_agl_gmx_rx#_frm_chk"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	22,	11,	43},
+	{"cvmx_agl_gmx_rx#_frm_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	24,	14,	54},
+	{"cvmx_agl_gmx_rx#_frm_max"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26,	2,	68},
+	{"cvmx_agl_gmx_rx#_frm_min"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	28,	2,	70},
+	{"cvmx_agl_gmx_rx#_ifg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	30,	2,	72},
+	{"cvmx_agl_gmx_rx#_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	32,	21,	74},
+	{"cvmx_agl_gmx_rx#_int_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	34,	21,	95},
+	{"cvmx_agl_gmx_rx#_jabber"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	36,	2,	116},
+	{"cvmx_agl_gmx_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	38,	2,	118},
+	{"cvmx_agl_gmx_rx#_rx_inbnd"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	40,	4,	120},
+	{"cvmx_agl_gmx_rx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	42,	2,	124},
+	{"cvmx_agl_gmx_rx#_stats_octs" ,	CVMX_CSR_DB_TYPE_RSL,	64,	44,	2,	126},
+	{"cvmx_agl_gmx_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	46,	2,	128},
+	{"cvmx_agl_gmx_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	48,	2,	130},
+	{"cvmx_agl_gmx_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	50,	2,	132},
+	{"cvmx_agl_gmx_rx#_stats_pkts" ,	CVMX_CSR_DB_TYPE_RSL,	64,	52,	2,	134},
+	{"cvmx_agl_gmx_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	54,	2,	136},
+	{"cvmx_agl_gmx_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	56,	2,	138},
+	{"cvmx_agl_gmx_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	58,	2,	140},
+	{"cvmx_agl_gmx_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	60,	2,	142},
+	{"cvmx_agl_gmx_rx#_udd_skp"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	62,	4,	144},
+	{"cvmx_agl_gmx_rx_bp_drop#"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	64,	2,	148},
+	{"cvmx_agl_gmx_rx_bp_off#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	66,	2,	150},
+	{"cvmx_agl_gmx_rx_bp_on#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	68,	2,	152},
+	{"cvmx_agl_gmx_rx_prt_info"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	70,	4,	154},
+	{"cvmx_agl_gmx_rx_tx_status"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	71,	4,	158},
+	{"cvmx_agl_gmx_smac#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	72,	2,	162},
+	{"cvmx_agl_gmx_stat_bp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	74,	3,	164},
+	{"cvmx_agl_gmx_tx#_append"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	75,	5,	167},
+	{"cvmx_agl_gmx_tx#_clk"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	77,	2,	172},
+	{"cvmx_agl_gmx_tx#_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	79,	3,	174},
+	{"cvmx_agl_gmx_tx#_min_pkt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	81,	2,	177},
+	{"cvmx_agl_gmx_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	83,	2,	179},
+	{"cvmx_agl_gmx_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	85,	2,	181},
+	{"cvmx_agl_gmx_tx#_pause_togo" ,	CVMX_CSR_DB_TYPE_RSL,	64,	87,	2,	183},
+	{"cvmx_agl_gmx_tx#_pause_zero" ,	CVMX_CSR_DB_TYPE_RSL,	64,	89,	2,	185},
+	{"cvmx_agl_gmx_tx#_soft_pause" ,	CVMX_CSR_DB_TYPE_RSL,	64,	91,	2,	187},
+	{"cvmx_agl_gmx_tx#_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	93,	2,	189},
+	{"cvmx_agl_gmx_tx#_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	95,	2,	191},
+	{"cvmx_agl_gmx_tx#_stat2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	97,	2,	193},
+	{"cvmx_agl_gmx_tx#_stat3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	99,	2,	195},
+	{"cvmx_agl_gmx_tx#_stat4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	101,	2,	197},
+	{"cvmx_agl_gmx_tx#_stat5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	103,	2,	199},
+	{"cvmx_agl_gmx_tx#_stat6"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	105,	2,	201},
+	{"cvmx_agl_gmx_tx#_stat7"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	107,	2,	203},
+	{"cvmx_agl_gmx_tx#_stat8"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	109,	2,	205},
+	{"cvmx_agl_gmx_tx#_stat9"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	111,	2,	207},
+	{"cvmx_agl_gmx_tx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	113,	2,	209},
+	{"cvmx_agl_gmx_tx#_thresh"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	115,	2,	211},
+	{"cvmx_agl_gmx_tx_bp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	117,	2,	213},
+	{"cvmx_agl_gmx_tx_col_attempt" ,	CVMX_CSR_DB_TYPE_RSL,	64,	118,	2,	215},
+	{"cvmx_agl_gmx_tx_ifg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	119,	3,	217},
+	{"cvmx_agl_gmx_tx_int_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	120,	12,	220},
+	{"cvmx_agl_gmx_tx_int_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	121,	12,	232},
+	{"cvmx_agl_gmx_tx_jam"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	122,	2,	244},
+	{"cvmx_agl_gmx_tx_lfsr"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	123,	2,	246},
+	{"cvmx_agl_gmx_tx_ovr_bp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	124,	6,	248},
+	{"cvmx_agl_gmx_tx_pause_pkt_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	125,	2,	254},
+	{"cvmx_agl_gmx_tx_pause_pkt_type",	CVMX_CSR_DB_TYPE_RSL,	64,	126,	2,	256},
+	{"cvmx_agl_prt#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	127,	23,	258},
+	{"cvmx_ciu_bist"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	129,	2,	281},
+	{"cvmx_ciu_block_int"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	130,	34,	283},
+	{"cvmx_ciu_dint"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	131,	2,	317},
+	{"cvmx_ciu_en2_io#_int"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	132,	3,	319},
+	{"cvmx_ciu_en2_io#_int_w1c"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	134,	3,	322},
+	{"cvmx_ciu_en2_io#_int_w1s"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	136,	3,	325},
+	{"cvmx_ciu_en2_pp#_ip2"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	138,	3,	328},
+	{"cvmx_ciu_en2_pp#_ip2_w1c"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	142,	3,	331},
+	{"cvmx_ciu_en2_pp#_ip2_w1s"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	146,	3,	334},
+	{"cvmx_ciu_en2_pp#_ip3"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	150,	3,	337},
+	{"cvmx_ciu_en2_pp#_ip3_w1c"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	154,	3,	340},
+	{"cvmx_ciu_en2_pp#_ip3_w1s"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	158,	3,	343},
+	{"cvmx_ciu_en2_pp#_ip4"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	162,	3,	346},
+	{"cvmx_ciu_en2_pp#_ip4_w1c"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	166,	3,	349},
+	{"cvmx_ciu_en2_pp#_ip4_w1s"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	170,	3,	352},
+	{"cvmx_ciu_fuse"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	174,	2,	355},
+	{"cvmx_ciu_gstop"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	175,	2,	357},
+	{"cvmx_ciu_int#_en0"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	176,	22,	359},
+	{"cvmx_ciu_int#_en0_w1c"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	186,	22,	381},
+	{"cvmx_ciu_int#_en0_w1s"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	196,	22,	403},
+	{"cvmx_ciu_int#_en1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	206,	33,	425},
+	{"cvmx_ciu_int#_en1_w1c"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	216,	33,	458},
+	{"cvmx_ciu_int#_en1_w1s"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	226,	33,	491},
+	{"cvmx_ciu_int#_en4_0"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	236,	22,	524},
+	{"cvmx_ciu_int#_en4_0_w1c"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	240,	22,	546},
+	{"cvmx_ciu_int#_en4_0_w1s"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	244,	22,	568},
+	{"cvmx_ciu_int#_en4_1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	248,	33,	590},
+	{"cvmx_ciu_int#_en4_1_w1c"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	252,	33,	623},
+	{"cvmx_ciu_int#_en4_1_w1s"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	256,	33,	656},
+	{"cvmx_ciu_int#_sum0"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	260,	22,	689},
+	{"cvmx_ciu_int#_sum4"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	269,	22,	711},
+	{"cvmx_ciu_int33_sum0"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	273,	22,	733},
+	{"cvmx_ciu_int_dbg_sel"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	274,	6,	755},
+	{"cvmx_ciu_int_sum1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	275,	31,	761},
+	{"cvmx_ciu_mbox_clr#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	276,	2,	792},
+	{"cvmx_ciu_mbox_set#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	280,	2,	794},
+	{"cvmx_ciu_nmi"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	284,	2,	796},
+	{"cvmx_ciu_pci_inta"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	285,	2,	798},
+	{"cvmx_ciu_pp_dbg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	286,	2,	800},
+	{"cvmx_ciu_pp_poke#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	287,	1,	802},
+	{"cvmx_ciu_pp_rst"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	291,	3,	803},
+	{"cvmx_ciu_qlm0"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	292,	13,	806},
+	{"cvmx_ciu_qlm1"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	293,	13,	819},
+	{"cvmx_ciu_qlm2"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	294,	8,	832},
+	{"cvmx_ciu_qlm_jtgc"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	295,	6,	840},
+	{"cvmx_ciu_qlm_jtgd"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	296,	8,	846},
+	{"cvmx_ciu_soft_bist"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	297,	2,	854},
+	{"cvmx_ciu_soft_prst"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	298,	2,	856},
+	{"cvmx_ciu_soft_prst1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	299,	2,	858},
+	{"cvmx_ciu_soft_rst"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	300,	2,	860},
+	{"cvmx_ciu_sum1_io#_int"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	301,	33,	862},
+	{"cvmx_ciu_sum1_pp#_ip2"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	303,	33,	895},
+	{"cvmx_ciu_sum1_pp#_ip3"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	307,	33,	928},
+	{"cvmx_ciu_sum1_pp#_ip4"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	311,	33,	961},
+	{"cvmx_ciu_sum2_io#_int"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	315,	3,	994},
+	{"cvmx_ciu_sum2_pp#_ip2"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	317,	3,	997},
+	{"cvmx_ciu_sum2_pp#_ip3"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	321,	3,	1000},
+	{"cvmx_ciu_sum2_pp#_ip4"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	325,	3,	1003},
+	{"cvmx_ciu_tim#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	329,	3,	1006},
+	{"cvmx_ciu_tim_multi_cast"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	339,	2,	1009},
+	{"cvmx_ciu_wdog#"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	340,	7,	1011},
+	{"cvmx_dfa_bist0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	344,	10,	1018},
+	{"cvmx_dfa_bist1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	345,	14,	1028},
+	{"cvmx_dfa_config"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	346,	7,	1042},
+	{"cvmx_dfa_control"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	347,	7,	1049},
+	{"cvmx_dfa_dbell"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	348,	2,	1056},
+	{"cvmx_dfa_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	349,	1,	1058},
+	{"cvmx_dfa_debug1"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	350,	1,	1059},
+	{"cvmx_dfa_debug2"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	351,	1,	1060},
+	{"cvmx_dfa_debug3"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	352,	1,	1061},
+	{"cvmx_dfa_difctl"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	353,	5,	1062},
+	{"cvmx_dfa_difrdptr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	354,	3,	1067},
+	{"cvmx_dfa_dtcfadr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	355,	6,	1070},
+	{"cvmx_dfa_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	356,	9,	1076},
+	{"cvmx_dfa_intmsk"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	357,	8,	1085},
+	{"cvmx_dfa_memhidat"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	358,	1,	1093},
+	{"cvmx_dfa_pfc0_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	359,	1,	1094},
+	{"cvmx_dfa_pfc0_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	360,	5,	1095},
+	{"cvmx_dfa_pfc1_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	361,	1,	1100},
+	{"cvmx_dfa_pfc1_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	362,	5,	1101},
+	{"cvmx_dfa_pfc2_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	363,	1,	1106},
+	{"cvmx_dfa_pfc2_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	364,	5,	1107},
+	{"cvmx_dfa_pfc3_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	365,	1,	1112},
+	{"cvmx_dfa_pfc3_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	366,	5,	1113},
+	{"cvmx_dfa_pfc_gctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	367,	18,	1118},
+	{"cvmx_dpi_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	368,	2,	1136},
+	{"cvmx_dpi_ctl"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	369,	2,	1138},
+	{"cvmx_dpi_dma#_counts"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	370,	3,	1140},
+	{"cvmx_dpi_dma#_dbell"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	378,	2,	1143},
+	{"cvmx_dpi_dma#_err_rsp_status",	CVMX_CSR_DB_TYPE_NCB,	64,	386,	2,	1145},
+	{"cvmx_dpi_dma#_ibuff_saddr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	394,	7,	1147},
+	{"cvmx_dpi_dma#_iflight"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	402,	2,	1154},
+	{"cvmx_dpi_dma#_naddr"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	410,	2,	1156},
+	{"cvmx_dpi_dma#_reqbnk0"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	418,	1,	1158},
+	{"cvmx_dpi_dma#_reqbnk1"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	426,	1,	1159},
+	{"cvmx_dpi_dma_control"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	434,	20,	1160},
+	{"cvmx_dpi_dma_eng#_en"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	435,	2,	1180},
+	{"cvmx_dpi_dma_pp#_cnt"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	441,	2,	1182},
+	{"cvmx_dpi_eng#_buf"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	445,	5,	1184},
+	{"cvmx_dpi_info_reg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	451,	5,	1189},
+	{"cvmx_dpi_int_en"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	452,	17,	1194},
+	{"cvmx_dpi_int_reg"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	453,	17,	1211},
+	{"cvmx_dpi_ncb#_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	454,	2,	1228},
+	{"cvmx_dpi_pint_info"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	455,	4,	1230},
+	{"cvmx_dpi_pkt_err_rsp"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	456,	2,	1234},
+	{"cvmx_dpi_req_err_rsp"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	457,	2,	1236},
+	{"cvmx_dpi_req_err_rsp_en"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	458,	2,	1238},
+	{"cvmx_dpi_req_err_rst"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	459,	2,	1240},
+	{"cvmx_dpi_req_err_rst_en"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	460,	2,	1242},
+	{"cvmx_dpi_req_err_skip_comp"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	461,	4,	1244},
+	{"cvmx_dpi_req_gbl_en"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	462,	2,	1248},
+	{"cvmx_dpi_sli_prt#_cfg"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	463,	13,	1250},
+	{"cvmx_dpi_sli_prt#_err"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	465,	2,	1263},
+	{"cvmx_dpi_sli_prt#_err_info"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	467,	6,	1265},
+	{"cvmx_fpa_addr_range_error"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	469,	3,	1271},
+	{"cvmx_fpa_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	470,	6,	1274},
+	{"cvmx_fpa_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	471,	10,	1280},
+	{"cvmx_fpa_fpf#_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	472,	3,	1290},
+	{"cvmx_fpa_fpf#_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	479,	2,	1293},
+	{"cvmx_fpa_fpf0_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	486,	3,	1295},
+	{"cvmx_fpa_fpf0_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	487,	2,	1298},
+	{"cvmx_fpa_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	488,	47,	1300},
+	{"cvmx_fpa_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	489,	47,	1347},
+	{"cvmx_fpa_packet_threshold"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	490,	2,	1394},
+	{"cvmx_fpa_pool#_end_addr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	491,	2,	1396},
+	{"cvmx_fpa_pool#_start_addr"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	499,	2,	1398},
+	{"cvmx_fpa_pool#_threshold"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	507,	2,	1400},
+	{"cvmx_fpa_que#_available"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	515,	2,	1402},
+	{"cvmx_fpa_que#_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	523,	2,	1404},
+	{"cvmx_fpa_que_act"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	531,	3,	1406},
+	{"cvmx_fpa_que_exp"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	532,	3,	1409},
+	{"cvmx_fpa_wqe_threshold"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	533,	2,	1412},
+	{"cvmx_gmx#_bad_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	534,	7,	1414},
+	{"cvmx_gmx#_bist"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	536,	2,	1421},
+	{"cvmx_gmx#_clk_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	538,	2,	1423},
+	{"cvmx_gmx#_hg2_control"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	540,	5,	1425},
+	{"cvmx_gmx#_inf_mode"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	542,	7,	1430},
+	{"cvmx_gmx#_nxa_adr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	544,	2,	1437},
+	{"cvmx_gmx#_prt#_cbfc_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	546,	8,	1439},
+	{"cvmx_gmx#_prt#_cfg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	548,	10,	1447},
+	{"cvmx_gmx#_rx#_adr_cam0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	556,	1,	1457},
+	{"cvmx_gmx#_rx#_adr_cam1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	564,	1,	1458},
+	{"cvmx_gmx#_rx#_adr_cam2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	572,	1,	1459},
+	{"cvmx_gmx#_rx#_adr_cam3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	580,	1,	1460},
+	{"cvmx_gmx#_rx#_adr_cam4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	588,	1,	1461},
+	{"cvmx_gmx#_rx#_adr_cam5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	596,	1,	1462},
+	{"cvmx_gmx#_rx#_adr_cam_all_en",	CVMX_CSR_DB_TYPE_RSL,	64,	604,	2,	1463},
+	{"cvmx_gmx#_rx#_adr_cam_en"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	612,	2,	1465},
+	{"cvmx_gmx#_rx#_adr_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	620,	4,	1467},
+	{"cvmx_gmx#_rx#_decision"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	628,	2,	1471},
+	{"cvmx_gmx#_rx#_frm_chk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	636,	9,	1473},
+	{"cvmx_gmx#_rx#_frm_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	644,	13,	1482},
+	{"cvmx_gmx#_rx#_ifg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	652,	2,	1495},
+	{"cvmx_gmx#_rx#_int_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	660,	27,	1497},
+	{"cvmx_gmx#_rx#_int_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	668,	27,	1524},
+	{"cvmx_gmx#_rx#_jabber"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	676,	2,	1551},
+	{"cvmx_gmx#_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	684,	2,	1553},
+	{"cvmx_gmx#_rx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	692,	2,	1555},
+	{"cvmx_gmx#_rx#_stats_octs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	700,	2,	1557},
+	{"cvmx_gmx#_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	708,	2,	1559},
+	{"cvmx_gmx#_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	716,	2,	1561},
+	{"cvmx_gmx#_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	724,	2,	1563},
+	{"cvmx_gmx#_rx#_stats_pkts"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	732,	2,	1565},
+	{"cvmx_gmx#_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	740,	2,	1567},
+	{"cvmx_gmx#_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	748,	2,	1569},
+	{"cvmx_gmx#_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	756,	2,	1571},
+	{"cvmx_gmx#_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	764,	2,	1573},
+	{"cvmx_gmx#_rx#_udd_skp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	772,	4,	1575},
+	{"cvmx_gmx#_rx_bp_drop#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	780,	2,	1579},
+	{"cvmx_gmx#_rx_bp_off#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	788,	2,	1581},
+	{"cvmx_gmx#_rx_bp_on#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	796,	2,	1583},
+	{"cvmx_gmx#_rx_hg2_status"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	804,	4,	1585},
+	{"cvmx_gmx#_rx_prt_info"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	806,	4,	1589},
+	{"cvmx_gmx#_rx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	808,	2,	1593},
+	{"cvmx_gmx#_rx_xaui_bad_col"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	810,	5,	1595},
+	{"cvmx_gmx#_rx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	812,	2,	1600},
+	{"cvmx_gmx#_smac#"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	814,	2,	1602},
+	{"cvmx_gmx#_stat_bp"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	822,	3,	1604},
+	{"cvmx_gmx#_tb_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	824,	2,	1607},
+	{"cvmx_gmx#_tx#_append"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	826,	5,	1609},
+	{"cvmx_gmx#_tx#_burst"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	834,	2,	1614},
+	{"cvmx_gmx#_tx#_cbfc_xoff"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	842,	2,	1616},
+	{"cvmx_gmx#_tx#_cbfc_xon"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	844,	2,	1618},
+	{"cvmx_gmx#_tx#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	846,	3,	1620},
+	{"cvmx_gmx#_tx#_min_pkt"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	854,	2,	1623},
+	{"cvmx_gmx#_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	862,	2,	1625},
+	{"cvmx_gmx#_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	870,	2,	1627},
+	{"cvmx_gmx#_tx#_pause_togo"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	878,	3,	1629},
+	{"cvmx_gmx#_tx#_pause_zero"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	886,	2,	1632},
+	{"cvmx_gmx#_tx#_sgmii_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	894,	2,	1634},
+	{"cvmx_gmx#_tx#_slot"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	902,	2,	1636},
+	{"cvmx_gmx#_tx#_soft_pause"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	910,	2,	1638},
+	{"cvmx_gmx#_tx#_stat0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	918,	2,	1640},
+	{"cvmx_gmx#_tx#_stat1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	926,	2,	1642},
+	{"cvmx_gmx#_tx#_stat2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	934,	2,	1644},
+	{"cvmx_gmx#_tx#_stat3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	942,	2,	1646},
+	{"cvmx_gmx#_tx#_stat4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	950,	2,	1648},
+	{"cvmx_gmx#_tx#_stat5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	958,	2,	1650},
+	{"cvmx_gmx#_tx#_stat6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	966,	2,	1652},
+	{"cvmx_gmx#_tx#_stat7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	974,	2,	1654},
+	{"cvmx_gmx#_tx#_stat8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	982,	2,	1656},
+	{"cvmx_gmx#_tx#_stat9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	990,	2,	1658},
+	{"cvmx_gmx#_tx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	998,	2,	1660},
+	{"cvmx_gmx#_tx#_thresh"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1006,	2,	1662},
+	{"cvmx_gmx#_tx_bp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1014,	2,	1664},
+	{"cvmx_gmx#_tx_col_attempt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1016,	2,	1666},
+	{"cvmx_gmx#_tx_corrupt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1018,	2,	1668},
+	{"cvmx_gmx#_tx_hg2_reg1"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1020,	2,	1670},
+	{"cvmx_gmx#_tx_hg2_reg2"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1022,	2,	1672},
+	{"cvmx_gmx#_tx_ifg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1024,	3,	1674},
+	{"cvmx_gmx#_tx_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1026,	10,	1677},
+	{"cvmx_gmx#_tx_int_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1028,	10,	1687},
+	{"cvmx_gmx#_tx_jam"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1030,	2,	1697},
+	{"cvmx_gmx#_tx_lfsr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1032,	2,	1699},
+	{"cvmx_gmx#_tx_ovr_bp"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1034,	6,	1701},
+	{"cvmx_gmx#_tx_pause_pkt_dmac" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1036,	2,	1707},
+	{"cvmx_gmx#_tx_pause_pkt_type" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1038,	2,	1709},
+	{"cvmx_gmx#_tx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1040,	2,	1711},
+	{"cvmx_gmx#_tx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1042,	9,	1713},
+	{"cvmx_gmx#_xaui_ext_loopback" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1044,	3,	1722},
+	{"cvmx_gpio_bit_cfg#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1046,	10,	1725},
+	{"cvmx_gpio_clk_gen#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1062,	2,	1735},
+	{"cvmx_gpio_clk_qlm#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1066,	5,	1737},
+	{"cvmx_gpio_int_clr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1068,	2,	1742},
+	{"cvmx_gpio_multi_cast"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1069,	2,	1744},
+	{"cvmx_gpio_rx_dat"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1070,	2,	1746},
+	{"cvmx_gpio_tx_clr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1071,	2,	1748},
+	{"cvmx_gpio_tx_set"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1072,	2,	1750},
+	{"cvmx_gpio_xbit_cfg#"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1073,	10,	1752},
+	{"cvmx_iob_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1077,	24,	1762},
+	{"cvmx_iob_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1078,	9,	1786},
+	{"cvmx_iob_dwb_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1079,	3,	1795},
+	{"cvmx_iob_fau_timeout"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1080,	3,	1798},
+	{"cvmx_iob_i2c_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1081,	3,	1801},
+	{"cvmx_iob_inb_control_match"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1082,	5,	1804},
+	{"cvmx_iob_inb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	1083,	5,	1809},
+	{"cvmx_iob_inb_data_match"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1084,	1,	1814},
+	{"cvmx_iob_inb_data_match_enb" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1085,	1,	1815},
+	{"cvmx_iob_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1086,	7,	1816},
+	{"cvmx_iob_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1087,	7,	1823},
+	{"cvmx_iob_n2c_l2c_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1088,	3,	1830},
+	{"cvmx_iob_n2c_rsp_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1089,	3,	1833},
+	{"cvmx_iob_outb_com_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1090,	3,	1836},
+	{"cvmx_iob_outb_control_match" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1091,	5,	1839},
+	{"cvmx_iob_outb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	1092,	5,	1844},
+	{"cvmx_iob_outb_data_match"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1093,	1,	1849},
+	{"cvmx_iob_outb_data_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	1094,	1,	1850},
+	{"cvmx_iob_outb_fpa_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1095,	3,	1851},
+	{"cvmx_iob_outb_req_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1096,	3,	1854},
+	{"cvmx_iob_p2c_req_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1097,	3,	1857},
+	{"cvmx_iob_pkt_err"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1098,	3,	1860},
+	{"cvmx_iob_to_cmb_credits"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1099,	4,	1863},
+	{"cvmx_ipd_1st_mbuff_skip"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1100,	2,	1867},
+	{"cvmx_ipd_1st_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1101,	2,	1869},
+	{"cvmx_ipd_2nd_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1102,	2,	1871},
+	{"cvmx_ipd_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1103,	19,	1873},
+	{"cvmx_ipd_bp_prt_red_end"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1104,	2,	1892},
+	{"cvmx_ipd_clk_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1105,	1,	1894},
+	{"cvmx_ipd_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1106,	18,	1895},
+	{"cvmx_ipd_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1107,	13,	1913},
+	{"cvmx_ipd_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1108,	13,	1926},
+	{"cvmx_ipd_not_1st_mbuff_skip" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1109,	2,	1939},
+	{"cvmx_ipd_packet_mbuff_size"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1110,	2,	1941},
+	{"cvmx_ipd_pkt_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1111,	2,	1943},
+	{"cvmx_ipd_port#_bp_page_cnt"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1112,	3,	1945},
+	{"cvmx_ipd_port#_bp_page_cnt2" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1124,	3,	1948},
+	{"cvmx_ipd_port#_bp_page_cnt3" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1128,	3,	1951},
+	{"cvmx_ipd_port_bp_counters2_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	1136,	2,	1954},
+	{"cvmx_ipd_port_bp_counters3_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	1140,	2,	1956},
+	{"cvmx_ipd_port_bp_counters4_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	1144,	2,	1958},
+	{"cvmx_ipd_port_bp_counters_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	1148,	2,	1960},
+	{"cvmx_ipd_port_qos_#_cnt"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1160,	2,	1962},
+	{"cvmx_ipd_port_qos_int#"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1352,	1,	1964},
+	{"cvmx_ipd_port_qos_int_enb#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1356,	1,	1965},
+	{"cvmx_ipd_prc_hold_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	1360,	6,	1966},
+	{"cvmx_ipd_prc_port_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	1361,	5,	1972},
+	{"cvmx_ipd_ptr_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1362,	6,	1977},
+	{"cvmx_ipd_pwp_ptr_fifo_ctl"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1363,	7,	1983},
+	{"cvmx_ipd_qos#_red_marks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1364,	2,	1990},
+	{"cvmx_ipd_que0_free_page_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1372,	2,	1992},
+	{"cvmx_ipd_red_port_enable"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1373,	3,	1994},
+	{"cvmx_ipd_red_port_enable2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1374,	2,	1997},
+	{"cvmx_ipd_red_que#_param"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1375,	5,	1999},
+	{"cvmx_ipd_sub_port_bp_page_cnt",	CVMX_CSR_DB_TYPE_NCB,	64,	1383,	3,	2004},
+	{"cvmx_ipd_sub_port_fcs"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1384,	4,	2007},
+	{"cvmx_ipd_sub_port_qos_cnt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1385,	3,	2011},
+	{"cvmx_ipd_wqe_fpa_queue"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1386,	2,	2014},
+	{"cvmx_ipd_wqe_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1387,	2,	2016},
+	{"cvmx_key_bist_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1388,	4,	2018},
+	{"cvmx_key_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1389,	3,	2022},
+	{"cvmx_key_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1390,	5,	2025},
+	{"cvmx_key_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1391,	5,	2030},
+	{"cvmx_l2c_big_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1392,	4,	2035},
+	{"cvmx_l2c_bst"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1393,	12,	2039},
+	{"cvmx_l2c_bst_mem#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1394,	5,	2051},
+	{"cvmx_l2c_bst_tdt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1395,	5,	2056},
+	{"cvmx_l2c_bst_ttg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1396,	3,	2061},
+	{"cvmx_l2c_cop0_map#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1397,	1,	2064},
+	{"cvmx_l2c_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2677,	15,	2065},
+	{"cvmx_l2c_dut_map#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2678,	4,	2080},
+	{"cvmx_l2c_err_tdt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3702,	9,	2084},
+	{"cvmx_l2c_err_ttg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3703,	9,	2093},
+	{"cvmx_l2c_err_vbf#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3704,	6,	2102},
+	{"cvmx_l2c_err_xmc"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	3705,	5,	2108},
+	{"cvmx_l2c_int_ena"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	3706,	9,	2113},
+	{"cvmx_l2c_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	3707,	11,	2122},
+	{"cvmx_l2c_ioc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3708,	1,	2133},
+	{"cvmx_l2c_ior#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3709,	1,	2134},
+	{"cvmx_l2c_qos_iob#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3710,	4,	2135},
+	{"cvmx_l2c_qos_pp#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	3711,	2,	2139},
+	{"cvmx_l2c_qos_wgt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	3715,	5,	2141},
+	{"cvmx_l2c_rsc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3716,	1,	2146},
+	{"cvmx_l2c_rsd#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3717,	1,	2147},
+	{"cvmx_l2c_tad#_ecc0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	3718,	8,	2148},
+	{"cvmx_l2c_tad#_ecc1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	3719,	8,	2156},
+	{"cvmx_l2c_tad#_ien"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3720,	10,	2164},
+	{"cvmx_l2c_tad#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3721,	10,	2174},
+	{"cvmx_l2c_tad#_pfc0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	3722,	1,	2184},
+	{"cvmx_l2c_tad#_pfc1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	3723,	1,	2185},
+	{"cvmx_l2c_tad#_pfc2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	3724,	1,	2186},
+	{"cvmx_l2c_tad#_pfc3"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	3725,	1,	2187},
+	{"cvmx_l2c_tad#_prf"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3726,	5,	2188},
+	{"cvmx_l2c_tad#_tag"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3727,	9,	2193},
+	{"cvmx_l2c_ver_id"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	3728,	1,	2202},
+	{"cvmx_l2c_ver_iob"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	3729,	2,	2203},
+	{"cvmx_l2c_ver_msc"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	3730,	3,	2205},
+	{"cvmx_l2c_ver_pp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	3731,	2,	2208},
+	{"cvmx_l2c_virtid_iob#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	3732,	4,	2210},
+	{"cvmx_l2c_virtid_pp#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	3733,	2,	2214},
+	{"cvmx_l2c_vrt_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	3737,	6,	2216},
+	{"cvmx_l2c_vrt_mem#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3738,	3,	2222},
+	{"cvmx_l2c_wpar_iob#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4762,	2,	2225},
+	{"cvmx_l2c_wpar_pp#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4763,	2,	2227},
+	{"cvmx_l2c_xmc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4767,	1,	2229},
+	{"cvmx_l2c_xmc_cmd"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4768,	4,	2230},
+	{"cvmx_l2c_xmd#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4769,	1,	2234},
+	{"cvmx_lmc#_char_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4770,	7,	2235},
+	{"cvmx_lmc#_char_mask0"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4771,	1,	2242},
+	{"cvmx_lmc#_char_mask1"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4772,	2,	2243},
+	{"cvmx_lmc#_char_mask2"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4773,	1,	2245},
+	{"cvmx_lmc#_char_mask3"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4774,	2,	2246},
+	{"cvmx_lmc#_char_mask4"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4775,	12,	2248},
+	{"cvmx_lmc#_comp_ctl2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4776,	11,	2260},
+	{"cvmx_lmc#_config"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4777,	23,	2271},
+	{"cvmx_lmc#_control"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4778,	26,	2294},
+	{"cvmx_lmc#_dclk_cnt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4779,	1,	2320},
+	{"cvmx_lmc#_ddr_pll_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4780,	11,	2321},
+	{"cvmx_lmc#_dimm#_params"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4781,	16,	2332},
+	{"cvmx_lmc#_dimm_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4783,	5,	2348},
+	{"cvmx_lmc#_dll_ctl2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4784,	7,	2353},
+	{"cvmx_lmc#_dll_ctl3"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4785,	16,	2360},
+	{"cvmx_lmc#_dual_memcfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4786,	4,	2376},
+	{"cvmx_lmc#_ecc_synd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4787,	5,	2380},
+	{"cvmx_lmc#_fadr"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	4788,	6,	2385},
+	{"cvmx_lmc#_ifb_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4789,	1,	2391},
+	{"cvmx_lmc#_int"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	4790,	4,	2392},
+	{"cvmx_lmc#_int_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4791,	4,	2396},
+	{"cvmx_lmc#_modereg_params0"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	4792,	16,	2400},
+	{"cvmx_lmc#_modereg_params1"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	4793,	25,	2416},
+	{"cvmx_lmc#_nxm"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	4794,	10,	2441},
+	{"cvmx_lmc#_ops_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4795,	1,	2451},
+	{"cvmx_lmc#_phy_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4796,	10,	2452},
+	{"cvmx_lmc#_reset_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4797,	5,	2462},
+	{"cvmx_lmc#_rlevel_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4798,	10,	2467},
+	{"cvmx_lmc#_rlevel_dbg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4799,	1,	2477},
+	{"cvmx_lmc#_rlevel_rank#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4800,	11,	2478},
+	{"cvmx_lmc#_rodt_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4804,	8,	2489},
+	{"cvmx_lmc#_scramble_cfg0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	4805,	1,	2497},
+	{"cvmx_lmc#_scramble_cfg1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	4806,	1,	2498},
+	{"cvmx_lmc#_scrambled_fadr"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	4807,	6,	2499},
+	{"cvmx_lmc#_slot_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4808,	5,	2505},
+	{"cvmx_lmc#_slot_ctl1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4809,	5,	2510},
+	{"cvmx_lmc#_slot_ctl2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4810,	5,	2515},
+	{"cvmx_lmc#_timing_params0"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	4811,	12,	2520},
+	{"cvmx_lmc#_timing_params1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	4812,	13,	2532},
+	{"cvmx_lmc#_tro_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4813,	3,	2545},
+	{"cvmx_lmc#_tro_stat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4814,	2,	2548},
+	{"cvmx_lmc#_wlevel_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4815,	6,	2550},
+	{"cvmx_lmc#_wlevel_dbg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4816,	3,	2556},
+	{"cvmx_lmc#_wlevel_rank#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4817,	11,	2559},
+	{"cvmx_lmc#_wodt_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4821,	8,	2570},
+	{"cvmx_mio_boot_bist_stat"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	4822,	2,	2578},
+	{"cvmx_mio_boot_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4823,	3,	2580},
+	{"cvmx_mio_boot_dma_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4824,	10,	2583},
+	{"cvmx_mio_boot_dma_int#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4826,	3,	2593},
+	{"cvmx_mio_boot_dma_int_en#"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	4828,	3,	2596},
+	{"cvmx_mio_boot_dma_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4830,	15,	2599},
+	{"cvmx_mio_boot_err"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4832,	3,	2614},
+	{"cvmx_mio_boot_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4833,	3,	2617},
+	{"cvmx_mio_boot_loc_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4834,	3,	2620},
+	{"cvmx_mio_boot_loc_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4835,	5,	2623},
+	{"cvmx_mio_boot_loc_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4837,	1,	2628},
+	{"cvmx_mio_boot_pin_defs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4838,	10,	2629},
+	{"cvmx_mio_boot_reg_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4839,	13,	2639},
+	{"cvmx_mio_boot_reg_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4847,	13,	2652},
+	{"cvmx_mio_boot_thr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4855,	6,	2665},
+	{"cvmx_mio_emm_buf_dat"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4856,	1,	2671},
+	{"cvmx_mio_emm_buf_idx"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4857,	5,	2672},
+	{"cvmx_mio_emm_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4858,	4,	2677},
+	{"cvmx_mio_emm_cmd"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4859,	11,	2681},
+	{"cvmx_mio_emm_dma"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4860,	11,	2692},
+	{"cvmx_mio_emm_int"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4861,	8,	2703},
+	{"cvmx_mio_emm_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4862,	8,	2711},
+	{"cvmx_mio_emm_mode#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4863,	8,	2719},
+	{"cvmx_mio_emm_rca"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4867,	2,	2727},
+	{"cvmx_mio_emm_rsp_hi"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4868,	1,	2729},
+	{"cvmx_mio_emm_rsp_lo"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4869,	1,	2730},
+	{"cvmx_mio_emm_rsp_sts"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4870,	25,	2731},
+	{"cvmx_mio_emm_sample"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4871,	4,	2756},
+	{"cvmx_mio_emm_sts_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4872,	2,	2760},
+	{"cvmx_mio_emm_switch"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4873,	14,	2762},
+	{"cvmx_mio_emm_wdog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4874,	2,	2776},
+	{"cvmx_mio_fus_bnk_dat#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4875,	1,	2778},
+	{"cvmx_mio_fus_dat0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4877,	2,	2779},
+	{"cvmx_mio_fus_dat1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4878,	2,	2781},
+	{"cvmx_mio_fus_dat2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4879,	15,	2783},
+	{"cvmx_mio_fus_dat3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4880,	18,	2798},
+	{"cvmx_mio_fus_ema"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4881,	4,	2816},
+	{"cvmx_mio_fus_pdf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4882,	1,	2820},
+	{"cvmx_mio_fus_pll"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4883,	7,	2821},
+	{"cvmx_mio_fus_prog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4884,	3,	2828},
+	{"cvmx_mio_fus_prog_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	4885,	8,	2831},
+	{"cvmx_mio_fus_rcmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4886,	7,	2839},
+	{"cvmx_mio_fus_read_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	4887,	6,	2846},
+	{"cvmx_mio_fus_repair_res0"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	4888,	5,	2852},
+	{"cvmx_mio_fus_repair_res1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	4889,	4,	2857},
+	{"cvmx_mio_fus_repair_res2"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	4890,	2,	2861},
+	{"cvmx_mio_fus_spr_repair_res" ,	CVMX_CSR_DB_TYPE_RSL,	64,	4891,	4,	2863},
+	{"cvmx_mio_fus_spr_repair_sum" ,	CVMX_CSR_DB_TYPE_RSL,	64,	4892,	2,	2867},
+	{"cvmx_mio_fus_tgg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4893,	2,	2869},
+	{"cvmx_mio_fus_wadr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4894,	2,	2871},
+	{"cvmx_mio_gpio_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4895,	3,	2873},
+	{"cvmx_mio_ndf_dma_cfg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4896,	10,	2876},
+	{"cvmx_mio_ndf_dma_int"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4897,	2,	2886},
+	{"cvmx_mio_ndf_dma_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	4898,	2,	2888},
+	{"cvmx_mio_ptp_ckout_hi_incr"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4899,	2,	2890},
+	{"cvmx_mio_ptp_ckout_lo_incr"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4900,	2,	2892},
+	{"cvmx_mio_ptp_ckout_thresh_hi",	CVMX_CSR_DB_TYPE_NCB,	64,	4901,	1,	2894},
+	{"cvmx_mio_ptp_ckout_thresh_lo",	CVMX_CSR_DB_TYPE_NCB,	64,	4902,	2,	2895},
+	{"cvmx_mio_ptp_clock_cfg"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	4903,	20,	2897},
+	{"cvmx_mio_ptp_clock_comp"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	4904,	2,	2917},
+	{"cvmx_mio_ptp_clock_hi"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	4905,	1,	2919},
+	{"cvmx_mio_ptp_clock_lo"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	4906,	2,	2920},
+	{"cvmx_mio_ptp_evt_cnt"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	4907,	1,	2922},
+	{"cvmx_mio_ptp_pps_hi_incr"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	4908,	2,	2923},
+	{"cvmx_mio_ptp_pps_lo_incr"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	4909,	2,	2925},
+	{"cvmx_mio_ptp_pps_thresh_hi"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4910,	1,	2927},
+	{"cvmx_mio_ptp_pps_thresh_lo"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4911,	2,	2928},
+	{"cvmx_mio_ptp_timestamp"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	4912,	1,	2930},
+	{"cvmx_mio_qlm#_cfg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4913,	6,	2931},
+	{"cvmx_mio_rst_boot"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4916,	17,	2937},
+	{"cvmx_mio_rst_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4917,	5,	2954},
+	{"cvmx_mio_rst_ckill"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4918,	2,	2959},
+	{"cvmx_mio_rst_cntl#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4919,	13,	2961},
+	{"cvmx_mio_rst_ctl#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4921,	13,	2974},
+	{"cvmx_mio_rst_delay"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4923,	3,	2987},
+	{"cvmx_mio_rst_int"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4924,	6,	2990},
+	{"cvmx_mio_rst_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4925,	6,	2996},
+	{"cvmx_mio_tws#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4926,	13,	3002},
+	{"cvmx_mio_tws#_sw_twsi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4928,	12,	3015},
+	{"cvmx_mio_tws#_sw_twsi_ext"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	4930,	3,	3027},
+	{"cvmx_mio_tws#_twsi_sw"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4932,	3,	3030},
+	{"cvmx_mio_uart#_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4934,	2,	3033},
+	{"cvmx_mio_uart#_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4936,	2,	3035},
+	{"cvmx_mio_uart#_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4938,	2,	3037},
+	{"cvmx_mio_uart#_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4940,	7,	3039},
+	{"cvmx_mio_uart#_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4942,	2,	3046},
+	{"cvmx_mio_uart#_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4944,	7,	3048},
+	{"cvmx_mio_uart#_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4946,	4,	3055},
+	{"cvmx_mio_uart#_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4948,	8,	3059},
+	{"cvmx_mio_uart#_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4950,	9,	3067},
+	{"cvmx_mio_uart#_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4952,	7,	3076},
+	{"cvmx_mio_uart#_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4954,	9,	3083},
+	{"cvmx_mio_uart#_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4956,	2,	3092},
+	{"cvmx_mio_uart#_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4958,	2,	3094},
+	{"cvmx_mio_uart#_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4960,	4,	3096},
+	{"cvmx_mio_uart#_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4962,	2,	3100},
+	{"cvmx_mio_uart#_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4964,	2,	3102},
+	{"cvmx_mio_uart#_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4966,	2,	3104},
+	{"cvmx_mio_uart#_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4968,	4,	3106},
+	{"cvmx_mio_uart#_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4970,	2,	3110},
+	{"cvmx_mio_uart#_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4972,	2,	3112},
+	{"cvmx_mio_uart#_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4974,	2,	3114},
+	{"cvmx_mio_uart#_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4976,	2,	3116},
+	{"cvmx_mio_uart#_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4978,	2,	3118},
+	{"cvmx_mio_uart#_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4980,	2,	3120},
+	{"cvmx_mio_uart#_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4982,	6,	3122},
+	{"cvmx_mix#_bist"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	4984,	7,	3128},
+	{"cvmx_mix#_ctl"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	4986,	9,	3135},
+	{"cvmx_mix#_intena"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	4988,	9,	3144},
+	{"cvmx_mix#_ircnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	4990,	2,	3153},
+	{"cvmx_mix#_irhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	4992,	3,	3155},
+	{"cvmx_mix#_iring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	4994,	4,	3158},
+	{"cvmx_mix#_iring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	4996,	4,	3162},
+	{"cvmx_mix#_isr"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	4998,	9,	3166},
+	{"cvmx_mix#_orcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5000,	2,	3175},
+	{"cvmx_mix#_orhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5002,	2,	3177},
+	{"cvmx_mix#_oring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5004,	4,	3179},
+	{"cvmx_mix#_oring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5006,	4,	3183},
+	{"cvmx_mix#_remcnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5008,	4,	3187},
+	{"cvmx_mix#_tsctl"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5010,	6,	3191},
+	{"cvmx_mix#_tstamp"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5012,	1,	3197},
+	{"cvmx_mpi_cfg"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	5014,	16,	3198},
+	{"cvmx_mpi_dat#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5015,	2,	3214},
+	{"cvmx_mpi_sts"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	5024,	4,	3216},
+	{"cvmx_mpi_tx"                 ,	CVMX_CSR_DB_TYPE_NCB,	64,	5025,	8,	3220},
+	{"cvmx_pcieep#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5026,	2,	3228},
+	{"cvmx_pcieep#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5028,	24,	3230},
+	{"cvmx_pcieep#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5030,	4,	3254},
+	{"cvmx_pcieep#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5032,	5,	3258},
+	{"cvmx_pcieep#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5034,	5,	3263},
+	{"cvmx_pcieep#_cfg004_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5036,	2,	3268},
+	{"cvmx_pcieep#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5038,	1,	3270},
+	{"cvmx_pcieep#_cfg005_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5040,	1,	3271},
+	{"cvmx_pcieep#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5042,	5,	3272},
+	{"cvmx_pcieep#_cfg006_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5044,	2,	3277},
+	{"cvmx_pcieep#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5046,	1,	3279},
+	{"cvmx_pcieep#_cfg007_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5048,	1,	3280},
+	{"cvmx_pcieep#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5050,	4,	3281},
+	{"cvmx_pcieep#_cfg008_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5052,	2,	3285},
+	{"cvmx_pcieep#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5054,	2,	3287},
+	{"cvmx_pcieep#_cfg009_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5056,	1,	3289},
+	{"cvmx_pcieep#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5058,	1,	3290},
+	{"cvmx_pcieep#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5060,	2,	3291},
+	{"cvmx_pcieep#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5062,	3,	3293},
+	{"cvmx_pcieep#_cfg012_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5064,	2,	3296},
+	{"cvmx_pcieep#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5066,	2,	3298},
+	{"cvmx_pcieep#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5068,	4,	3300},
+	{"cvmx_pcieep#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5070,	10,	3304},
+	{"cvmx_pcieep#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5072,	12,	3314},
+	{"cvmx_pcieep#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5074,	8,	3326},
+	{"cvmx_pcieep#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5076,	2,	3334},
+	{"cvmx_pcieep#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5078,	1,	3336},
+	{"cvmx_pcieep#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5080,	2,	3337},
+	{"cvmx_pcieep#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5082,	7,	3339},
+	{"cvmx_pcieep#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5084,	12,	3346},
+	{"cvmx_pcieep#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5086,	19,	3358},
+	{"cvmx_pcieep#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5088,	12,	3377},
+	{"cvmx_pcieep#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5090,	20,	3389},
+	{"cvmx_pcieep#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5092,	11,	3409},
+	{"cvmx_pcieep#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5094,	8,	3420},
+	{"cvmx_pcieep#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5096,	4,	3428},
+	{"cvmx_pcieep#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5098,	11,	3432},
+	{"cvmx_pcieep#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5100,	3,	3443},
+	{"cvmx_pcieep#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5102,	16,	3446},
+	{"cvmx_pcieep#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5104,	16,	3462},
+	{"cvmx_pcieep#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5106,	16,	3478},
+	{"cvmx_pcieep#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5108,	9,	3494},
+	{"cvmx_pcieep#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5110,	9,	3503},
+	{"cvmx_pcieep#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5112,	6,	3512},
+	{"cvmx_pcieep#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5114,	1,	3518},
+	{"cvmx_pcieep#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5116,	1,	3519},
+	{"cvmx_pcieep#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5118,	1,	3520},
+	{"cvmx_pcieep#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5120,	1,	3521},
+	{"cvmx_pcieep#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5122,	2,	3522},
+	{"cvmx_pcieep#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5124,	1,	3524},
+	{"cvmx_pcieep#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5126,	6,	3525},
+	{"cvmx_pcieep#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5128,	7,	3531},
+	{"cvmx_pcieep#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5130,	11,	3538},
+	{"cvmx_pcieep#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5132,	5,	3549},
+	{"cvmx_pcieep#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5134,	6,	3554},
+	{"cvmx_pcieep#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5136,	19,	3560},
+	{"cvmx_pcieep#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5138,	5,	3579},
+	{"cvmx_pcieep#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5140,	1,	3584},
+	{"cvmx_pcieep#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5142,	1,	3585},
+	{"cvmx_pcieep#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5144,	3,	3586},
+	{"cvmx_pcieep#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5146,	3,	3589},
+	{"cvmx_pcieep#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5148,	3,	3592},
+	{"cvmx_pcieep#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5150,	4,	3595},
+	{"cvmx_pcieep#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5152,	4,	3599},
+	{"cvmx_pcieep#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5154,	4,	3603},
+	{"cvmx_pcieep#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5156,	7,	3607},
+	{"cvmx_pcieep#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5158,	5,	3614},
+	{"cvmx_pcieep#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5160,	5,	3619},
+	{"cvmx_pcieep#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5162,	4,	3624},
+	{"cvmx_pcieep#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5164,	4,	3628},
+	{"cvmx_pcieep#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5166,	4,	3632},
+	{"cvmx_pcieep#_cfg515"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5168,	7,	3636},
+	{"cvmx_pcieep#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5170,	1,	3643},
+	{"cvmx_pcieep#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5172,	1,	3644},
+	{"cvmx_pcierc#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5174,	2,	3645},
+	{"cvmx_pcierc#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5176,	24,	3647},
+	{"cvmx_pcierc#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5178,	4,	3671},
+	{"cvmx_pcierc#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5180,	5,	3675},
+	{"cvmx_pcierc#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5182,	1,	3680},
+	{"cvmx_pcierc#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5184,	1,	3681},
+	{"cvmx_pcierc#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5186,	4,	3682},
+	{"cvmx_pcierc#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5188,	17,	3686},
+	{"cvmx_pcierc#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5190,	4,	3703},
+	{"cvmx_pcierc#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5192,	6,	3707},
+	{"cvmx_pcierc#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5194,	1,	3713},
+	{"cvmx_pcierc#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5196,	1,	3714},
+	{"cvmx_pcierc#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5198,	2,	3715},
+	{"cvmx_pcierc#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5200,	2,	3717},
+	{"cvmx_pcierc#_cfg014"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5202,	1,	3719},
+	{"cvmx_pcierc#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5204,	15,	3720},
+	{"cvmx_pcierc#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5206,	10,	3735},
+	{"cvmx_pcierc#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5208,	12,	3745},
+	{"cvmx_pcierc#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5210,	8,	3757},
+	{"cvmx_pcierc#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5212,	2,	3765},
+	{"cvmx_pcierc#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5214,	1,	3767},
+	{"cvmx_pcierc#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5216,	2,	3768},
+	{"cvmx_pcierc#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5218,	7,	3770},
+	{"cvmx_pcierc#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5220,	11,	3777},
+	{"cvmx_pcierc#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5222,	19,	3788},
+	{"cvmx_pcierc#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5224,	12,	3807},
+	{"cvmx_pcierc#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5226,	20,	3819},
+	{"cvmx_pcierc#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5228,	12,	3839},
+	{"cvmx_pcierc#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5230,	22,	3851},
+	{"cvmx_pcierc#_cfg035"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5232,	8,	3873},
+	{"cvmx_pcierc#_cfg036"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5234,	4,	3881},
+	{"cvmx_pcierc#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5236,	11,	3885},
+	{"cvmx_pcierc#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5238,	8,	3896},
+	{"cvmx_pcierc#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5240,	4,	3904},
+	{"cvmx_pcierc#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5242,	11,	3908},
+	{"cvmx_pcierc#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5244,	1,	3919},
+	{"cvmx_pcierc#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5246,	1,	3920},
+	{"cvmx_pcierc#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5248,	3,	3921},
+	{"cvmx_pcierc#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5250,	16,	3924},
+	{"cvmx_pcierc#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5252,	16,	3940},
+	{"cvmx_pcierc#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5254,	16,	3956},
+	{"cvmx_pcierc#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5256,	9,	3972},
+	{"cvmx_pcierc#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5258,	9,	3981},
+	{"cvmx_pcierc#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5260,	6,	3990},
+	{"cvmx_pcierc#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5262,	1,	3996},
+	{"cvmx_pcierc#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5264,	1,	3997},
+	{"cvmx_pcierc#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5266,	1,	3998},
+	{"cvmx_pcierc#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5268,	1,	3999},
+	{"cvmx_pcierc#_cfg075"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5270,	4,	4000},
+	{"cvmx_pcierc#_cfg076"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5272,	9,	4004},
+	{"cvmx_pcierc#_cfg077"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5274,	2,	4013},
+	{"cvmx_pcierc#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5276,	2,	4015},
+	{"cvmx_pcierc#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5278,	1,	4017},
+	{"cvmx_pcierc#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5280,	6,	4018},
+	{"cvmx_pcierc#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5282,	7,	4024},
+	{"cvmx_pcierc#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5284,	11,	4031},
+	{"cvmx_pcierc#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5286,	5,	4042},
+	{"cvmx_pcierc#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5288,	6,	4047},
+	{"cvmx_pcierc#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5290,	19,	4053},
+	{"cvmx_pcierc#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5292,	5,	4072},
+	{"cvmx_pcierc#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5294,	1,	4077},
+	{"cvmx_pcierc#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5296,	1,	4078},
+	{"cvmx_pcierc#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5298,	3,	4079},
+	{"cvmx_pcierc#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5300,	3,	4082},
+	{"cvmx_pcierc#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5302,	3,	4085},
+	{"cvmx_pcierc#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5304,	4,	4088},
+	{"cvmx_pcierc#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5306,	4,	4092},
+	{"cvmx_pcierc#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5308,	4,	4096},
+	{"cvmx_pcierc#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5310,	7,	4100},
+	{"cvmx_pcierc#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5312,	5,	4107},
+	{"cvmx_pcierc#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5314,	5,	4112},
+	{"cvmx_pcierc#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5316,	4,	4117},
+	{"cvmx_pcierc#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5318,	4,	4121},
+	{"cvmx_pcierc#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5320,	4,	4125},
+	{"cvmx_pcierc#_cfg515"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5322,	7,	4129},
+	{"cvmx_pcierc#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5324,	1,	4136},
+	{"cvmx_pcierc#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5326,	1,	4137},
+	{"cvmx_pcm#_dma_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5328,	12,	4138},
+	{"cvmx_pcm#_int_ena"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5332,	9,	4150},
+	{"cvmx_pcm#_int_sum"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5336,	9,	4159},
+	{"cvmx_pcm#_rxaddr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5340,	2,	4168},
+	{"cvmx_pcm#_rxcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5344,	2,	4170},
+	{"cvmx_pcm#_rxmsk0"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5348,	1,	4172},
+	{"cvmx_pcm#_rxmsk1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5352,	1,	4173},
+	{"cvmx_pcm#_rxmsk2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5356,	1,	4174},
+	{"cvmx_pcm#_rxmsk3"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5360,	1,	4175},
+	{"cvmx_pcm#_rxmsk4"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5364,	1,	4176},
+	{"cvmx_pcm#_rxmsk5"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5368,	1,	4177},
+	{"cvmx_pcm#_rxmsk6"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5372,	1,	4178},
+	{"cvmx_pcm#_rxmsk7"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5376,	1,	4179},
+	{"cvmx_pcm#_rxstart"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5380,	3,	4180},
+	{"cvmx_pcm#_tdm_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5384,	6,	4183},
+	{"cvmx_pcm#_tdm_dbg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5388,	1,	4189},
+	{"cvmx_pcm#_txaddr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5392,	3,	4190},
+	{"cvmx_pcm#_txcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5396,	2,	4193},
+	{"cvmx_pcm#_txmsk0"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5400,	1,	4195},
+	{"cvmx_pcm#_txmsk1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5404,	1,	4196},
+	{"cvmx_pcm#_txmsk2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5408,	1,	4197},
+	{"cvmx_pcm#_txmsk3"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5412,	1,	4198},
+	{"cvmx_pcm#_txmsk4"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5416,	1,	4199},
+	{"cvmx_pcm#_txmsk5"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5420,	1,	4200},
+	{"cvmx_pcm#_txmsk6"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5424,	1,	4201},
+	{"cvmx_pcm#_txmsk7"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5428,	1,	4202},
+	{"cvmx_pcm#_txstart"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5432,	3,	4203},
+	{"cvmx_pcm_clk#_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5436,	12,	4206},
+	{"cvmx_pcm_clk#_dbg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5438,	1,	4218},
+	{"cvmx_pcm_clk#_gen"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5440,	3,	4219},
+	{"cvmx_pcs#_an#_adv_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5442,	9,	4222},
+	{"cvmx_pcs#_an#_ext_st_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5450,	6,	4231},
+	{"cvmx_pcs#_an#_lp_abil_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5458,	9,	4237},
+	{"cvmx_pcs#_an#_results_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5466,	6,	4246},
+	{"cvmx_pcs#_int#_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5474,	14,	4252},
+	{"cvmx_pcs#_int#_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5482,	14,	4266},
+	{"cvmx_pcs#_link#_timer_count_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	5490,	2,	4280},
+	{"cvmx_pcs#_log_anl#_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5498,	4,	4282},
+	{"cvmx_pcs#_misc#_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5506,	8,	4286},
+	{"cvmx_pcs#_mr#_control_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5514,	13,	4294},
+	{"cvmx_pcs#_mr#_status_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5522,	17,	4307},
+	{"cvmx_pcs#_rx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5530,	7,	4324},
+	{"cvmx_pcs#_rx#_sync_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5538,	3,	4331},
+	{"cvmx_pcs#_sgm#_an_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5546,	8,	4334},
+	{"cvmx_pcs#_sgm#_lp_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5554,	7,	4342},
+	{"cvmx_pcs#_tx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5562,	4,	4349},
+	{"cvmx_pcs#_tx_rx#_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	5570,	5,	4353},
+	{"cvmx_pcsx#_10gbx_status_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	5578,	8,	4358},
+	{"cvmx_pcsx#_bist_status_reg"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	5580,	2,	4366},
+	{"cvmx_pcsx#_bit_lock_status_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	5582,	5,	4368},
+	{"cvmx_pcsx#_control1_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5584,	10,	4373},
+	{"cvmx_pcsx#_control2_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5586,	2,	4383},
+	{"cvmx_pcsx#_int_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5588,	8,	4385},
+	{"cvmx_pcsx#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5590,	8,	4393},
+	{"cvmx_pcsx#_log_anl_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5592,	6,	4401},
+	{"cvmx_pcsx#_misc_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5594,	5,	4407},
+	{"cvmx_pcsx#_rx_sync_states_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	5596,	5,	4412},
+	{"cvmx_pcsx#_spd_abil_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5598,	3,	4417},
+	{"cvmx_pcsx#_status1_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5600,	6,	4420},
+	{"cvmx_pcsx#_status2_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5602,	9,	4426},
+	{"cvmx_pcsx#_tx_rx_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	5604,	5,	4435},
+	{"cvmx_pcsx#_tx_rx_states_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	5606,	10,	4440},
+	{"cvmx_pem#_bar1_index#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5608,	5,	4450},
+	{"cvmx_pem#_bar2_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5640,	3,	4455},
+	{"cvmx_pem#_bar_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5642,	5,	4458},
+	{"cvmx_pem#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5644,	9,	4463},
+	{"cvmx_pem#_bist_status2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5646,	11,	4472},
+	{"cvmx_pem#_cfg_rd"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5648,	2,	4483},
+	{"cvmx_pem#_cfg_wr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5650,	2,	4485},
+	{"cvmx_pem#_cpl_lut_valid"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5652,	2,	4487},
+	{"cvmx_pem#_ctl_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5654,	18,	4489},
+	{"cvmx_pem#_dbg_info"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5656,	32,	4507},
+	{"cvmx_pem#_dbg_info_en"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5658,	32,	4539},
+	{"cvmx_pem#_diag_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5660,	5,	4571},
+	{"cvmx_pem#_inb_read_credits"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	5662,	2,	4576},
+	{"cvmx_pem#_int_enb"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5664,	15,	4578},
+	{"cvmx_pem#_int_enb_int"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5666,	15,	4593},
+	{"cvmx_pem#_int_sum"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5668,	15,	4608},
+	{"cvmx_pem#_p2n_bar0_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5670,	2,	4623},
+	{"cvmx_pem#_p2n_bar1_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5672,	2,	4625},
+	{"cvmx_pem#_p2n_bar2_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5674,	2,	4627},
+	{"cvmx_pem#_tlp_credits"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5676,	6,	4629},
+	{"cvmx_pip_alt_skip_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5678,	12,	4635},
+	{"cvmx_pip_bck_prs"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5682,	5,	4647},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5683,	2,	4652},
+	{"cvmx_pip_bsel_ext_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5684,	7,	4654},
+	{"cvmx_pip_bsel_ext_pos#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5688,	16,	4661},
+	{"cvmx_pip_bsel_tbl_ent#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5692,	12,	4677},
+	{"cvmx_pip_clken"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	6204,	2,	4689},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6205,	4,	4691},
+	{"cvmx_pip_dsa_src_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6209,	16,	4695},
+	{"cvmx_pip_dsa_vid_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6210,	16,	4711},
+	{"cvmx_pip_frm_len_chk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6211,	3,	4727},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6212,	8,	4730},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6213,	23,	4738},
+	{"cvmx_pip_hg_pri_qos"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6214,	6,	4761},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	6215,	14,	4767},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6216,	14,	4781},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6217,	2,	4795},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6218,	28,	4797},
+	{"cvmx_pip_prt_cfgb#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6234,	7,	4825},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6250,	25,	4832},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6266,	2,	4857},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6330,	4,	4859},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6338,	9,	4863},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6346,	2,	4872},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6347,	2,	4874},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6348,	2,	4876},
+	{"cvmx_pip_stat10_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6364,	2,	4878},
+	{"cvmx_pip_stat11_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6380,	2,	4880},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6396,	2,	4882},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6412,	2,	4884},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6428,	2,	4886},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6444,	2,	4888},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6460,	2,	4890},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6476,	2,	4892},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6492,	2,	4894},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6508,	2,	4896},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6524,	2,	4898},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6540,	2,	4900},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6541,	2,	4902},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6557,	2,	4904},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6573,	2,	4906},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6589,	2,	4908},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6653,	2,	4910},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6654,	3,	4912},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6655,	3,	4915},
+	{"cvmx_pip_vlan_etypes#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6656,	4,	4918},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6658,	2,	4922},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6659,	2,	4924},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6660,	4,	4926},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6661,	5,	4930},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6662,	4,	4935},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6663,	8,	4939},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6664,	4,	4947},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6665,	5,	4951},
+	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6666,	1,	4956},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6667,	5,	4957},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6668,	1,	4962},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6669,	13,	4963},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6670,	6,	4976},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6671,	13,	4982},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6672,	6,	4995},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6673,	12,	5001},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6674,	4,	5013},
+	{"cvmx_pko_mem_port_ptrs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6675,	7,	5017},
+	{"cvmx_pko_mem_port_qos"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6676,	5,	5024},
+	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6677,	5,	5029},
+	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6678,	4,	5034},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6679,	9,	5038},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6680,	5,	5047},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6681,	16,	5052},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6682,	4,	5068},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6683,	1,	5072},
+	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6684,	1,	5073},
+	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6685,	1,	5074},
+	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6686,	1,	5075},
+	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	6687,	15,	5076},
+	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6688,	2,	5091},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6689,	4,	5093},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6690,	8,	5097},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6691,	3,	5105},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6692,	4,	5108},
+	{"cvmx_pko_reg_preempt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6693,	2,	5112},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6694,	2,	5114},
+	{"cvmx_pko_reg_queue_preempt"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6695,	3,	5116},
+	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6696,	3,	5119},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6697,	3,	5122},
+	{"cvmx_pko_reg_timestamp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6698,	2,	5125},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6699,	10,	5127},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	6700,	2,	5137},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6701,	13,	5139},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6702,	3,	5152},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6703,	2,	5155},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	6711,	2,	5157},
+	{"cvmx_pow_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6712,	2,	5159},
+	{"cvmx_pow_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6713,	2,	5161},
+	{"cvmx_pow_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6714,	2,	5163},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6722,	2,	5165},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6723,	2,	5167},
+	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	6724,	2,	5169},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6725,	10,	5171},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	6729,	5,	5181},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	6737,	10,	5186},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	6745,	2,	5196},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6746,	2,	5198},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6747,	2,	5200},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6755,	3,	5202},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6756,	6,	5205},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6772,	5,	5211},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6773,	7,	5216},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6789,	2,	5223},
+	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6805,	1,	5225},
+	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6806,	1,	5226},
+	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6807,	1,	5227},
+	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6808,	5,	5228},
+	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6809,	5,	5233},
+	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6810,	4,	5238},
+	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6811,	10,	5242},
+	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6812,	1,	5252},
+	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6813,	3,	5253},
+	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6814,	7,	5256},
+	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6815,	2,	5263},
+	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6816,	1,	5265},
+	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6817,	1,	5266},
+	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6818,	1,	5267},
+	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6819,	18,	5268},
+	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6820,	3,	5286},
+	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6821,	2,	5289},
+	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6822,	3,	5291},
+	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6823,	7,	5294},
+	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6824,	2,	5301},
+	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6825,	2,	5303},
+	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6826,	2,	5305},
+	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6827,	3,	5307},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6828,	3,	5310},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6829,	10,	5313},
+	{"cvmx_rnm_eer_dbg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6830,	1,	5323},
+	{"cvmx_rnm_eer_key"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6831,	1,	5324},
+	{"cvmx_rnm_serial_num"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6832,	1,	5325},
+	{"cvmx_sli_bist_status"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6833,	24,	5326},
+	{"cvmx_sli_ctl_port#"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6834,	16,	5350},
+	{"cvmx_sli_ctl_status"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6836,	3,	5366},
+	{"cvmx_sli_data_out_cnt"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6837,	5,	5369},
+	{"cvmx_sli_dbg_data"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6838,	3,	5374},
+	{"cvmx_sli_dbg_select"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6839,	3,	5377},
+	{"cvmx_sli_dma#_cnt"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6840,	2,	5380},
+	{"cvmx_sli_dma#_int_level"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6842,	2,	5382},
+	{"cvmx_sli_dma#_tim"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6844,	2,	5384},
+	{"cvmx_sli_int_enb_ciu"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6846,	45,	5386},
+	{"cvmx_sli_int_enb_port#"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6847,	46,	5431},
+	{"cvmx_sli_int_sum"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6849,	46,	5477},
+	{"cvmx_sli_last_win_rdata0"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6850,	1,	5523},
+	{"cvmx_sli_last_win_rdata1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6851,	1,	5524},
+	{"cvmx_sli_last_win_rdata2"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6852,	1,	5525},
+	{"cvmx_sli_last_win_rdata3"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6853,	1,	5526},
+	{"cvmx_sli_mac_credit_cnt"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6854,	13,	5527},
+	{"cvmx_sli_mac_credit_cnt2"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6855,	13,	5540},
+	{"cvmx_sli_mac_number"         ,	CVMX_CSR_DB_TYPE_PEXP,	64,	6856,	3,	5553},
+	{"cvmx_sli_mem_access_ctl"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6857,	3,	5556},
+	{"cvmx_sli_mem_access_subid#"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6858,	9,	5559},
+	{"cvmx_sli_msi_enb0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6874,	1,	5568},
+	{"cvmx_sli_msi_enb1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6875,	1,	5569},
+	{"cvmx_sli_msi_enb2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6876,	1,	5570},
+	{"cvmx_sli_msi_enb3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6877,	1,	5571},
+	{"cvmx_sli_msi_rcv0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6878,	1,	5572},
+	{"cvmx_sli_msi_rcv1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6879,	1,	5573},
+	{"cvmx_sli_msi_rcv2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6880,	1,	5574},
+	{"cvmx_sli_msi_rcv3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6881,	1,	5575},
+	{"cvmx_sli_msi_rd_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6882,	3,	5576},
+	{"cvmx_sli_msi_w1c_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6883,	1,	5579},
+	{"cvmx_sli_msi_w1c_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6884,	1,	5580},
+	{"cvmx_sli_msi_w1c_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6885,	1,	5581},
+	{"cvmx_sli_msi_w1c_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6886,	1,	5582},
+	{"cvmx_sli_msi_w1s_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6887,	1,	5583},
+	{"cvmx_sli_msi_w1s_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6888,	1,	5584},
+	{"cvmx_sli_msi_w1s_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6889,	1,	5585},
+	{"cvmx_sli_msi_w1s_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6890,	1,	5586},
+	{"cvmx_sli_msi_wr_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6891,	3,	5587},
+	{"cvmx_sli_pcie_msi_rcv"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6892,	2,	5590},
+	{"cvmx_sli_pcie_msi_rcv_b1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6893,	3,	5592},
+	{"cvmx_sli_pcie_msi_rcv_b2"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6894,	3,	5595},
+	{"cvmx_sli_pcie_msi_rcv_b3"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6895,	3,	5598},
+	{"cvmx_sli_pkt#_cnts"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6896,	3,	5601},
+	{"cvmx_sli_pkt#_in_bp"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6928,	2,	5604},
+	{"cvmx_sli_pkt#_instr_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6960,	2,	5606},
+	{"cvmx_sli_pkt#_instr_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6992,	2,	5608},
+	{"cvmx_sli_pkt#_instr_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7024,	5,	5610},
+	{"cvmx_sli_pkt#_instr_header"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7056,	21,	5615},
+	{"cvmx_sli_pkt#_out_size"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7088,	3,	5636},
+	{"cvmx_sli_pkt#_slist_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7120,	2,	5639},
+	{"cvmx_sli_pkt#_slist_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7152,	2,	5641},
+	{"cvmx_sli_pkt#_slist_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7184,	2,	5643},
+	{"cvmx_sli_pkt_cnt_int"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7216,	2,	5645},
+	{"cvmx_sli_pkt_cnt_int_enb"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7217,	2,	5647},
+	{"cvmx_sli_pkt_ctl"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7218,	3,	5649},
+	{"cvmx_sli_pkt_data_out_es"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7219,	1,	5652},
+	{"cvmx_sli_pkt_data_out_ns"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7220,	2,	5653},
+	{"cvmx_sli_pkt_data_out_ror"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7221,	2,	5655},
+	{"cvmx_sli_pkt_dpaddr"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7222,	2,	5657},
+	{"cvmx_sli_pkt_in_bp"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7223,	2,	5659},
+	{"cvmx_sli_pkt_in_done#_cnts"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7224,	2,	5661},
+	{"cvmx_sli_pkt_in_instr_counts",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7256,	2,	5663},
+	{"cvmx_sli_pkt_in_pcie_port"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7257,	1,	5665},
+	{"cvmx_sli_pkt_input_control"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7258,	17,	5666},
+	{"cvmx_sli_pkt_instr_enb"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7259,	2,	5683},
+	{"cvmx_sli_pkt_instr_rd_size"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7260,	1,	5685},
+	{"cvmx_sli_pkt_instr_size"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7261,	2,	5686},
+	{"cvmx_sli_pkt_int_levels"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7262,	3,	5688},
+	{"cvmx_sli_pkt_iptr"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7263,	2,	5691},
+	{"cvmx_sli_pkt_out_bmode"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7264,	2,	5693},
+	{"cvmx_sli_pkt_out_enb"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7265,	2,	5695},
+	{"cvmx_sli_pkt_output_wmark"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7266,	2,	5697},
+	{"cvmx_sli_pkt_pcie_port"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7267,	1,	5699},
+	{"cvmx_sli_pkt_port_in_rst"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7268,	2,	5700},
+	{"cvmx_sli_pkt_slist_es"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7269,	1,	5702},
+	{"cvmx_sli_pkt_slist_ns"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7270,	2,	5703},
+	{"cvmx_sli_pkt_slist_ror"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7271,	2,	5705},
+	{"cvmx_sli_pkt_time_int"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7272,	2,	5707},
+	{"cvmx_sli_pkt_time_int_enb"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7273,	2,	5709},
+	{"cvmx_sli_s2m_port#_ctl"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7274,	4,	5711},
+	{"cvmx_sli_scratch_1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7276,	1,	5715},
+	{"cvmx_sli_scratch_2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7277,	1,	5716},
+	{"cvmx_sli_state1"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7278,	4,	5717},
+	{"cvmx_sli_state2"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7279,	8,	5721},
+	{"cvmx_sli_state3"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7280,	5,	5729},
+	{"cvmx_sli_win_rd_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7281,	4,	5734},
+	{"cvmx_sli_win_rd_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7282,	1,	5738},
+	{"cvmx_sli_win_wr_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7283,	4,	5739},
+	{"cvmx_sli_win_wr_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7284,	1,	5743},
+	{"cvmx_sli_win_wr_mask"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7285,	2,	5744},
+	{"cvmx_sli_window_ctl"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7286,	2,	5746},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7287,	10,	5748},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7289,	6,	5758},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	7291,	2,	5764},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7293,	4,	5766},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7295,	4,	5770},
+	{"cvmx_smi_drv_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7297,	4,	5774},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7298,	6,	5778},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7299,	3,	5784},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7300,	5,	5787},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7301,	4,	5792},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7302,	6,	5796},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7303,	4,	5802},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7304,	2,	5806},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7305,	4,	5808},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7306,	2,	5812},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7307,	3,	5814},
+	{"cvmx_tra#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7308,	2,	5817},
+	{"cvmx_tra#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7309,	14,	5819},
+	{"cvmx_tra#_cycles_since"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7310,	3,	5833},
+	{"cvmx_tra#_cycles_since1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7311,	5,	5836},
+	{"cvmx_tra#_filt_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7312,	2,	5841},
+	{"cvmx_tra#_filt_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7313,	2,	5843},
+	{"cvmx_tra#_filt_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7314,	57,	5845},
+	{"cvmx_tra#_filt_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7315,	20,	5902},
+	{"cvmx_tra#_filt_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7316,	7,	5922},
+	{"cvmx_tra#_int_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7317,	5,	5929},
+	{"cvmx_tra#_read_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7318,	1,	5934},
+	{"cvmx_tra#_read_dat_hi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7319,	2,	5935},
+	{"cvmx_tra#_trig0_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7320,	2,	5937},
+	{"cvmx_tra#_trig0_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7321,	2,	5939},
+	{"cvmx_tra#_trig0_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7322,	57,	5941},
+	{"cvmx_tra#_trig0_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7323,	20,	5998},
+	{"cvmx_tra#_trig0_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7324,	7,	6018},
+	{"cvmx_tra#_trig1_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7325,	2,	6025},
+	{"cvmx_tra#_trig1_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7326,	2,	6027},
+	{"cvmx_tra#_trig1_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7327,	57,	6029},
+	{"cvmx_tra#_trig1_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7328,	20,	6086},
+	{"cvmx_tra#_trig1_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7329,	7,	6106},
+	{"cvmx_uahc#_ehci_asynclistaddr",	CVMX_CSR_DB_TYPE_NCB,	32,	7330,	2,	6113},
+	{"cvmx_uahc#_ehci_configflag"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7331,	2,	6115},
+	{"cvmx_uahc#_ehci_ctrldssegment",	CVMX_CSR_DB_TYPE_NCB,	32,	7332,	1,	6117},
+	{"cvmx_uahc#_ehci_frindex"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7333,	2,	6118},
+	{"cvmx_uahc#_ehci_hccapbase"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7334,	3,	6120},
+	{"cvmx_uahc#_ehci_hccparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7335,	7,	6123},
+	{"cvmx_uahc#_ehci_hcsparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7336,	10,	6130},
+	{"cvmx_uahc#_ehci_insnreg00"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7337,	3,	6140},
+	{"cvmx_uahc#_ehci_insnreg03"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7338,	5,	6143},
+	{"cvmx_uahc#_ehci_insnreg04"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7339,	7,	6148},
+	{"cvmx_uahc#_ehci_insnreg06"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7340,	2,	6155},
+	{"cvmx_uahc#_ehci_insnreg07"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7341,	1,	6157},
+	{"cvmx_uahc#_ehci_periodiclistbase",	CVMX_CSR_DB_TYPE_NCB,	32,	7342,	2,	6158},
+	{"cvmx_uahc#_ehci_portsc#"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7343,	19,	6160},
+	{"cvmx_uahc#_ehci_usbcmd"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	7345,	13,	6179},
+	{"cvmx_uahc#_ehci_usbintr"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7346,	7,	6192},
+	{"cvmx_uahc#_ehci_usbsts"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	7347,	12,	6199},
+	{"cvmx_uahc#_ohci0_hcbulkcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7348,	2,	6211},
+	{"cvmx_uahc#_ohci0_hcbulkheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	7349,	2,	6213},
+	{"cvmx_uahc#_ohci0_hccommandstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	7350,	7,	6215},
+	{"cvmx_uahc#_ohci0_hccontrol"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7351,	10,	6222},
+	{"cvmx_uahc#_ohci0_hccontrolcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7352,	2,	6232},
+	{"cvmx_uahc#_ohci0_hccontrolheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	7353,	2,	6234},
+	{"cvmx_uahc#_ohci0_hcdonehead" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7354,	2,	6236},
+	{"cvmx_uahc#_ohci0_hcfminterval",	CVMX_CSR_DB_TYPE_NCB,	32,	7355,	4,	6238},
+	{"cvmx_uahc#_ohci0_hcfmnumber" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7356,	2,	6242},
+	{"cvmx_uahc#_ohci0_hcfmremaining",	CVMX_CSR_DB_TYPE_NCB,	32,	7357,	3,	6244},
+	{"cvmx_uahc#_ohci0_hchcca"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7358,	2,	6247},
+	{"cvmx_uahc#_ohci0_hcinterruptdisable",	CVMX_CSR_DB_TYPE_NCB,	32,	7359,	10,	6249},
+	{"cvmx_uahc#_ohci0_hcinterruptenable",	CVMX_CSR_DB_TYPE_NCB,	32,	7360,	10,	6259},
+	{"cvmx_uahc#_ohci0_hcinterruptstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	7361,	10,	6269},
+	{"cvmx_uahc#_ohci0_hclsthreshold",	CVMX_CSR_DB_TYPE_NCB,	32,	7362,	2,	6279},
+	{"cvmx_uahc#_ohci0_hcperiodcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7363,	2,	6281},
+	{"cvmx_uahc#_ohci0_hcperiodicstart",	CVMX_CSR_DB_TYPE_NCB,	32,	7364,	2,	6283},
+	{"cvmx_uahc#_ohci0_hcrevision" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7365,	2,	6285},
+	{"cvmx_uahc#_ohci0_hcrhdescriptora",	CVMX_CSR_DB_TYPE_NCB,	32,	7366,	8,	6287},
+	{"cvmx_uahc#_ohci0_hcrhdescriptorb",	CVMX_CSR_DB_TYPE_NCB,	32,	7367,	2,	6295},
+	{"cvmx_uahc#_ohci0_hcrhportstatus#",	CVMX_CSR_DB_TYPE_NCB,	32,	7368,	15,	6297},
+	{"cvmx_uahc#_ohci0_hcrhstatus" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7370,	8,	6312},
+	{"cvmx_uahc#_ohci0_insnreg06"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7371,	2,	6320},
+	{"cvmx_uahc#_ohci0_insnreg07"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7372,	1,	6322},
+	{"cvmx_uctl#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7373,	7,	6323},
+	{"cvmx_uctl#_clk_rst_ctl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7374,	21,	6330},
+	{"cvmx_uctl#_ehci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7375,	12,	6351},
+	{"cvmx_uctl#_ehci_fla"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7376,	2,	6363},
+	{"cvmx_uctl#_erto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7377,	3,	6365},
+	{"cvmx_uctl#_if_ena"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7378,	2,	6368},
+	{"cvmx_uctl#_int_ena"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7379,	9,	6370},
+	{"cvmx_uctl#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7380,	9,	6379},
+	{"cvmx_uctl#_ohci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7381,	11,	6388},
+	{"cvmx_uctl#_orto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7382,	3,	6399},
+	{"cvmx_uctl#_ppaf_wm"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7383,	2,	6402},
+	{"cvmx_uctl#_uphy_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	7384,	11,	6404},
+	{"cvmx_uctl#_uphy_port#_ctl_status",	CVMX_CSR_DB_TYPE_RSL,	64,	7385,	20,	6415},
+	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7387,	3,	6435},
+	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7388,	5,	6438},
+	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7389,	3,	6443},
+	{"cvmx_zip_constants"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7390,	8,	6446},
+	{"cvmx_zip_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	7391,	2,	6454},
+	{"cvmx_zip_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	7392,	2,	6456},
+	{"cvmx_zip_int_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7393,	2,	6458},
+	{"cvmx_zip_throttle"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7394,	2,	6460},
+	{NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn61xx[] = {
+	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
+	{"AGL_GMX_BAD_REG"             ,	   0x11800e0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"AGL_GMX_BIST"                ,	   0x11800e0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"AGL_GMX_PRT0_CFG"            ,	   0x11800e0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"AGL_GMX_PRT1_CFG"            ,	   0x11800e0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"AGL_GMX_RX0_ADR_CAM0"        ,	   0x11800e0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"AGL_GMX_RX1_ADR_CAM0"        ,	   0x11800e0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"AGL_GMX_RX0_ADR_CAM1"        ,	   0x11800e0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_RX1_ADR_CAM1"        ,	   0x11800e0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_RX0_ADR_CAM2"        ,	   0x11800e0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX1_ADR_CAM2"        ,	   0x11800e0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX0_ADR_CAM3"        ,	   0x11800e0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX1_ADR_CAM3"        ,	   0x11800e0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX0_ADR_CAM4"        ,	   0x11800e00001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX1_ADR_CAM4"        ,	   0x11800e00009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX0_ADR_CAM5"        ,	   0x11800e00001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX1_ADR_CAM5"        ,	   0x11800e00009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX0_ADR_CAM_EN"      ,	   0x11800e0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX1_ADR_CAM_EN"      ,	   0x11800e0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX0_ADR_CTL"         ,	   0x11800e0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX1_ADR_CTL"         ,	   0x11800e0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX0_DECISION"        ,	   0x11800e0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX1_DECISION"        ,	   0x11800e0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX0_FRM_CHK"         ,	   0x11800e0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX1_FRM_CHK"         ,	   0x11800e0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX0_FRM_CTL"         ,	   0x11800e0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX1_FRM_CTL"         ,	   0x11800e0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX0_FRM_MAX"         ,	   0x11800e0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX1_FRM_MAX"         ,	   0x11800e0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX0_FRM_MIN"         ,	   0x11800e0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX1_FRM_MIN"         ,	   0x11800e0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX0_IFG"             ,	   0x11800e0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX1_IFG"             ,	   0x11800e0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX0_INT_EN"          ,	   0x11800e0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX1_INT_EN"          ,	   0x11800e0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX0_INT_REG"         ,	   0x11800e0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX1_INT_REG"         ,	   0x11800e0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX0_JABBER"          ,	   0x11800e0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX1_JABBER"          ,	   0x11800e0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX0_PAUSE_DROP_TIME" ,	   0x11800e0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX1_PAUSE_DROP_TIME" ,	   0x11800e0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX0_RX_INBND"        ,	   0x11800e0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX1_RX_INBND"        ,	   0x11800e0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX0_STATS_CTL"       ,	   0x11800e0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX1_STATS_CTL"       ,	   0x11800e0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX0_STATS_OCTS"      ,	   0x11800e0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX1_STATS_OCTS"      ,	   0x11800e0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX0_STATS_OCTS_CTL"  ,	   0x11800e0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX1_STATS_OCTS_CTL"  ,	   0x11800e0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX0_STATS_OCTS_DMAC" ,	   0x11800e00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX1_STATS_OCTS_DMAC" ,	   0x11800e00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX0_STATS_OCTS_DRP"  ,	   0x11800e00000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX1_STATS_OCTS_DRP"  ,	   0x11800e00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX0_STATS_PKTS"      ,	   0x11800e0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX1_STATS_PKTS"      ,	   0x11800e0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX0_STATS_PKTS_BAD"  ,	   0x11800e00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX1_STATS_PKTS_BAD"  ,	   0x11800e00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX0_STATS_PKTS_CTL"  ,	   0x11800e0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX1_STATS_PKTS_CTL"  ,	   0x11800e0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX0_STATS_PKTS_DMAC" ,	   0x11800e00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX1_STATS_PKTS_DMAC" ,	   0x11800e00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX0_STATS_PKTS_DRP"  ,	   0x11800e00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX1_STATS_PKTS_DRP"  ,	   0x11800e00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX0_UDD_SKP"         ,	   0x11800e0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX1_UDD_SKP"         ,	   0x11800e0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX_BP_DROP0"         ,	   0x11800e0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX_BP_DROP1"         ,	   0x11800e0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX_BP_OFF0"          ,	   0x11800e0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_OFF1"          ,	   0x11800e0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_ON0"           ,	   0x11800e0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_BP_ON1"           ,	   0x11800e0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_PRT_INFO"         ,	   0x11800e00004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"AGL_GMX_RX_TX_STATUS"        ,	   0x11800e00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"AGL_GMX_SMAC0"               ,	   0x11800e0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"AGL_GMX_SMAC1"               ,	   0x11800e0000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"AGL_GMX_STAT_BP"             ,	   0x11800e0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"AGL_GMX_TX0_APPEND"          ,	   0x11800e0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"AGL_GMX_TX1_APPEND"          ,	   0x11800e0000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"AGL_GMX_TX0_CLK"             ,	   0x11800e0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX1_CLK"             ,	   0x11800e0000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX0_CTL"             ,	   0x11800e0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX1_CTL"             ,	   0x11800e0000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX0_MIN_PKT"         ,	   0x11800e0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX1_MIN_PKT"         ,	   0x11800e0000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",	   0x11800e0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX1_PAUSE_PKT_INTERVAL",	   0x11800e0000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,	   0x11800e0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX1_PAUSE_PKT_TIME"  ,	   0x11800e0000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX0_PAUSE_TOGO"      ,	   0x11800e0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX1_PAUSE_TOGO"      ,	   0x11800e0000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX0_PAUSE_ZERO"      ,	   0x11800e0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX1_PAUSE_ZERO"      ,	   0x11800e0000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX0_SOFT_PAUSE"      ,	   0x11800e0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX1_SOFT_PAUSE"      ,	   0x11800e0000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX0_STAT0"           ,	   0x11800e0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX1_STAT0"           ,	   0x11800e0000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX0_STAT1"           ,	   0x11800e0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX1_STAT1"           ,	   0x11800e0000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX0_STAT2"           ,	   0x11800e0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX1_STAT2"           ,	   0x11800e0000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX0_STAT3"           ,	   0x11800e0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX1_STAT3"           ,	   0x11800e0000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX0_STAT4"           ,	   0x11800e00002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX1_STAT4"           ,	   0x11800e0000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX0_STAT5"           ,	   0x11800e00002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX1_STAT5"           ,	   0x11800e0000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX0_STAT6"           ,	   0x11800e00002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX1_STAT6"           ,	   0x11800e0000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX0_STAT7"           ,	   0x11800e00002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX1_STAT7"           ,	   0x11800e0000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX0_STAT8"           ,	   0x11800e00002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX1_STAT8"           ,	   0x11800e0000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX0_STAT9"           ,	   0x11800e00002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX1_STAT9"           ,	   0x11800e0000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX0_STATS_CTL"       ,	   0x11800e0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX1_STATS_CTL"       ,	   0x11800e0000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX0_THRESH"          ,	   0x11800e0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX1_THRESH"          ,	   0x11800e0000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX_BP"               ,	   0x11800e00004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"AGL_GMX_TX_COL_ATTEMPT"      ,	   0x11800e0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"AGL_GMX_TX_IFG"              ,	   0x11800e0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"AGL_GMX_TX_INT_EN"           ,	   0x11800e0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"AGL_GMX_TX_INT_REG"          ,	   0x11800e0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"AGL_GMX_TX_JAM"              ,	   0x11800e0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"AGL_GMX_TX_LFSR"             ,	   0x11800e00004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"AGL_GMX_TX_OVR_BP"           ,	   0x11800e00004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,	   0x11800e00004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,	   0x11800e00004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"AGL_PRT0_CTL"                ,	   0x11800e0002000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"AGL_PRT1_CTL"                ,	   0x11800e0002008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
+	{"CIU_BLOCK_INT"               ,	   0x10700000007c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU_EN2_IO0_INT"             ,	   0x107000000a600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_EN2_IO1_INT"             ,	   0x107000000a608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_EN2_IO0_INT_W1C"         ,	   0x107000000ce00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_EN2_IO1_INT_W1C"         ,	   0x107000000ce08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_EN2_IO0_INT_W1S"         ,	   0x107000000ae00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_EN2_IO1_INT_W1S"         ,	   0x107000000ae08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_EN2_PP0_IP2"             ,	   0x107000000a000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_EN2_PP1_IP2"             ,	   0x107000000a008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_EN2_PP2_IP2"             ,	   0x107000000a010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_EN2_PP3_IP2"             ,	   0x107000000a018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_EN2_PP0_IP2_W1C"         ,	   0x107000000c800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_EN2_PP1_IP2_W1C"         ,	   0x107000000c808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_EN2_PP2_IP2_W1C"         ,	   0x107000000c810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_EN2_PP3_IP2_W1C"         ,	   0x107000000c818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_EN2_PP0_IP2_W1S"         ,	   0x107000000a800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_EN2_PP1_IP2_W1S"         ,	   0x107000000a808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_EN2_PP2_IP2_W1S"         ,	   0x107000000a810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_EN2_PP3_IP2_W1S"         ,	   0x107000000a818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_EN2_PP0_IP3"             ,	   0x107000000a200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_EN2_PP1_IP3"             ,	   0x107000000a208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_EN2_PP2_IP3"             ,	   0x107000000a210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_EN2_PP3_IP3"             ,	   0x107000000a218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_EN2_PP0_IP3_W1C"         ,	   0x107000000ca00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_EN2_PP1_IP3_W1C"         ,	   0x107000000ca08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_EN2_PP2_IP3_W1C"         ,	   0x107000000ca10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_EN2_PP3_IP3_W1C"         ,	   0x107000000ca18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_EN2_PP0_IP3_W1S"         ,	   0x107000000aa00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_EN2_PP1_IP3_W1S"         ,	   0x107000000aa08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_EN2_PP2_IP3_W1S"         ,	   0x107000000aa10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_EN2_PP3_IP3_W1S"         ,	   0x107000000aa18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_EN2_PP0_IP4"             ,	   0x107000000a400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_EN2_PP1_IP4"             ,	   0x107000000a408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_EN2_PP2_IP4"             ,	   0x107000000a410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_EN2_PP3_IP4"             ,	   0x107000000a418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_EN2_PP0_IP4_W1C"         ,	   0x107000000cc00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_EN2_PP1_IP4_W1C"         ,	   0x107000000cc08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_EN2_PP2_IP4_W1C"         ,	   0x107000000cc10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_EN2_PP3_IP4_W1C"         ,	   0x107000000cc18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_EN2_PP0_IP4_W1S"         ,	   0x107000000ac00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_EN2_PP1_IP4_W1S"         ,	   0x107000000ac08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_EN2_PP2_IP4_W1S"         ,	   0x107000000ac10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_EN2_PP3_IP4_W1S"         ,	   0x107000000ac18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_GSTOP"                   ,	   0x1070000000710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT0_EN0"                ,	   0x1070000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT1_EN0"                ,	   0x1070000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT2_EN0"                ,	   0x1070000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT3_EN0"                ,	   0x1070000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT4_EN0"                ,	   0x1070000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT5_EN0"                ,	   0x1070000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT6_EN0"                ,	   0x1070000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT33_EN0"               ,	   0x1070000000410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT0_EN0_W1C"            ,	   0x1070000002200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT1_EN0_W1C"            ,	   0x1070000002210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT2_EN0_W1C"            ,	   0x1070000002220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT3_EN0_W1C"            ,	   0x1070000002230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT4_EN0_W1C"            ,	   0x1070000002240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT5_EN0_W1C"            ,	   0x1070000002250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT6_EN0_W1C"            ,	   0x1070000002260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT7_EN0_W1C"            ,	   0x1070000002270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT32_EN0_W1C"           ,	   0x1070000002400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT33_EN0_W1C"           ,	   0x1070000002410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT0_EN0_W1S"            ,	   0x1070000006200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT1_EN0_W1S"            ,	   0x1070000006210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT2_EN0_W1S"            ,	   0x1070000006220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT3_EN0_W1S"            ,	   0x1070000006230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT4_EN0_W1S"            ,	   0x1070000006240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT5_EN0_W1S"            ,	   0x1070000006250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT6_EN0_W1S"            ,	   0x1070000006260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT7_EN0_W1S"            ,	   0x1070000006270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT32_EN0_W1S"           ,	   0x1070000006400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT33_EN0_W1S"           ,	   0x1070000006410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT2_EN1"                ,	   0x1070000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT3_EN1"                ,	   0x1070000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT4_EN1"                ,	   0x1070000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT5_EN1"                ,	   0x1070000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT6_EN1"                ,	   0x1070000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT33_EN1"               ,	   0x1070000000418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT0_EN1_W1C"            ,	   0x1070000002208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT1_EN1_W1C"            ,	   0x1070000002218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT2_EN1_W1C"            ,	   0x1070000002228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT3_EN1_W1C"            ,	   0x1070000002238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT4_EN1_W1C"            ,	   0x1070000002248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT5_EN1_W1C"            ,	   0x1070000002258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT6_EN1_W1C"            ,	   0x1070000002268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT7_EN1_W1C"            ,	   0x1070000002278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT32_EN1_W1C"           ,	   0x1070000002408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT33_EN1_W1C"           ,	   0x1070000002418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT0_EN1_W1S"            ,	   0x1070000006208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT1_EN1_W1S"            ,	   0x1070000006218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT2_EN1_W1S"            ,	   0x1070000006228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT3_EN1_W1S"            ,	   0x1070000006238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT4_EN1_W1S"            ,	   0x1070000006248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT5_EN1_W1S"            ,	   0x1070000006258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT6_EN1_W1S"            ,	   0x1070000006268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT7_EN1_W1S"            ,	   0x1070000006278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT32_EN1_W1S"           ,	   0x1070000006408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT33_EN1_W1S"           ,	   0x1070000006418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_INT2_EN4_0"              ,	   0x1070000000ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_INT3_EN4_0"              ,	   0x1070000000cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_INT0_EN4_0_W1C"          ,	   0x1070000002c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_INT1_EN4_0_W1C"          ,	   0x1070000002c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_INT2_EN4_0_W1C"          ,	   0x1070000002ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_INT3_EN4_0_W1C"          ,	   0x1070000002cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_INT0_EN4_0_W1S"          ,	   0x1070000006c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_INT1_EN4_0_W1S"          ,	   0x1070000006c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_INT2_EN4_0_W1S"          ,	   0x1070000006ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_INT3_EN4_0_W1S"          ,	   0x1070000006cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_INT2_EN4_1"              ,	   0x1070000000ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_INT3_EN4_1"              ,	   0x1070000000cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_INT0_EN4_1_W1C"          ,	   0x1070000002c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_INT1_EN4_1_W1C"          ,	   0x1070000002c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_INT2_EN4_1_W1C"          ,	   0x1070000002ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_INT3_EN4_1_W1C"          ,	   0x1070000002cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_INT0_EN4_1_W1S"          ,	   0x1070000006c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU_INT1_EN4_1_W1S"          ,	   0x1070000006c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU_INT2_EN4_1_W1S"          ,	   0x1070000006ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU_INT3_EN4_1_W1S"          ,	   0x1070000006cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT3_SUM0"               ,	   0x1070000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT4_SUM0"               ,	   0x1070000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT5_SUM0"               ,	   0x1070000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT6_SUM0"               ,	   0x1070000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT7_SUM0"               ,	   0x1070000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000c00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000c08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU_INT2_SUM4"               ,	   0x1070000000c10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU_INT3_SUM4"               ,	   0x1070000000c18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU_INT33_SUM0"              ,	   0x1070000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU_INT_DBG_SEL"             ,	   0x10700000007d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU_MBOX_SET3"               ,	   0x1070000000618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU_NMI"                     ,	   0x1070000000718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU_PCI_INTA"                ,	   0x1070000000750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU_PP_DBG"                  ,	   0x1070000000708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU_PP_POKE0"                ,	   0x1070000000580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU_QLM0"                    ,	   0x1070000000780ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU_QLM1"                    ,	   0x1070000000788ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU_QLM2"                    ,	   0x1070000000790ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU_QLM_JTGC"                ,	   0x1070000000768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU_QLM_JTGD"                ,	   0x1070000000770ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU_SOFT_PRST1"              ,	   0x1070000000758ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU_SOFT_RST"                ,	   0x1070000000740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU_SUM1_IO0_INT"            ,	   0x1070000008600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU_SUM1_IO1_INT"            ,	   0x1070000008608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU_SUM1_PP0_IP2"            ,	   0x1070000008000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU_SUM1_PP1_IP2"            ,	   0x1070000008008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU_SUM1_PP2_IP2"            ,	   0x1070000008010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU_SUM1_PP3_IP2"            ,	   0x1070000008018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU_SUM1_PP0_IP3"            ,	   0x1070000008200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU_SUM1_PP1_IP3"            ,	   0x1070000008208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU_SUM1_PP2_IP3"            ,	   0x1070000008210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU_SUM1_PP3_IP3"            ,	   0x1070000008218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU_SUM1_PP0_IP4"            ,	   0x1070000008400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU_SUM1_PP1_IP4"            ,	   0x1070000008408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU_SUM1_PP2_IP4"            ,	   0x1070000008410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU_SUM1_PP3_IP4"            ,	   0x1070000008418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU_SUM2_IO0_INT"            ,	   0x1070000008e00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU_SUM2_IO1_INT"            ,	   0x1070000008e08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU_SUM2_PP0_IP2"            ,	   0x1070000008800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU_SUM2_PP1_IP2"            ,	   0x1070000008808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU_SUM2_PP2_IP2"            ,	   0x1070000008810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU_SUM2_PP3_IP2"            ,	   0x1070000008818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU_SUM2_PP0_IP3"            ,	   0x1070000008a00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU_SUM2_PP1_IP3"            ,	   0x1070000008a08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU_SUM2_PP2_IP3"            ,	   0x1070000008a10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU_SUM2_PP3_IP3"            ,	   0x1070000008a18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU_SUM2_PP0_IP4"            ,	   0x1070000008c00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU_SUM2_PP1_IP4"            ,	   0x1070000008c08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU_SUM2_PP2_IP4"            ,	   0x1070000008c10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU_SUM2_PP3_IP4"            ,	   0x1070000008c18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU_TIM0"                    ,	   0x1070000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_TIM1"                    ,	   0x1070000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_TIM4"                    ,	   0x10700000004a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_TIM5"                    ,	   0x10700000004a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_TIM6"                    ,	   0x10700000004b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_TIM7"                    ,	   0x10700000004b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_TIM8"                    ,	   0x10700000004c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_TIM9"                    ,	   0x10700000004c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_TIM_MULTI_CAST"          ,	   0x107000000c200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU_WDOG2"                   ,	   0x1070000000510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU_WDOG3"                   ,	   0x1070000000518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"DFA_BIST0"                   ,	   0x11800370007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"DFA_BIST1"                   ,	   0x11800370007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"DFA_CONFIG"                  ,	   0x1180037000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"DFA_CONTROL"                 ,	   0x1180037000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"DFA_DBELL"                   ,	   0x1370000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"DFA_DEBUG0"                  ,	   0x1180037000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"DFA_DEBUG1"                  ,	   0x1180037000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"DFA_DEBUG2"                  ,	   0x1180037000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"DFA_DEBUG3"                  ,	   0x1180037000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"DFA_DIFCTL"                  ,	   0x1370600000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"DFA_DIFRDPTR"                ,	   0x1370200000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"DFA_DTCFADR"                 ,	   0x1180037000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"DFA_ERROR"                   ,	   0x1180037000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"DFA_INTMSK"                  ,	   0x1180037000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"DFA_MEMHIDAT"                ,	   0x1370700000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"DFA_PFC0_CNT"                ,	   0x1180037000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"DFA_PFC0_CTL"                ,	   0x1180037000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"DFA_PFC1_CNT"                ,	   0x11800370000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"DFA_PFC1_CTL"                ,	   0x1180037000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"DFA_PFC2_CNT"                ,	   0x11800370000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"DFA_PFC2_CTL"                ,	   0x11800370000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"DFA_PFC3_CNT"                ,	   0x11800370000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"DFA_PFC3_CTL"                ,	   0x11800370000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"DFA_PFC_GCTL"                ,	   0x1180037000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"DPI_BIST_STATUS"             ,	   0x1df0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"DPI_CTL"                     ,	   0x1df0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"DPI_DMA0_COUNTS"             ,	   0x1df0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"DPI_DMA1_COUNTS"             ,	   0x1df0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"DPI_DMA2_COUNTS"             ,	   0x1df0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"DPI_DMA3_COUNTS"             ,	   0x1df0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"DPI_DMA4_COUNTS"             ,	   0x1df0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"DPI_DMA5_COUNTS"             ,	   0x1df0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"DPI_DMA6_COUNTS"             ,	   0x1df0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"DPI_DMA7_COUNTS"             ,	   0x1df0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"DPI_DMA0_DBELL"              ,	   0x1df0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"DPI_DMA1_DBELL"              ,	   0x1df0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"DPI_DMA2_DBELL"              ,	   0x1df0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"DPI_DMA3_DBELL"              ,	   0x1df0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"DPI_DMA4_DBELL"              ,	   0x1df0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"DPI_DMA5_DBELL"              ,	   0x1df0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"DPI_DMA6_DBELL"              ,	   0x1df0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"DPI_DMA7_DBELL"              ,	   0x1df0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"DPI_DMA0_ERR_RSP_STATUS"     ,	   0x1df0000000a80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"DPI_DMA1_ERR_RSP_STATUS"     ,	   0x1df0000000a88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"DPI_DMA2_ERR_RSP_STATUS"     ,	   0x1df0000000a90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"DPI_DMA3_ERR_RSP_STATUS"     ,	   0x1df0000000a98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"DPI_DMA4_ERR_RSP_STATUS"     ,	   0x1df0000000aa0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"DPI_DMA5_ERR_RSP_STATUS"     ,	   0x1df0000000aa8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"DPI_DMA6_ERR_RSP_STATUS"     ,	   0x1df0000000ab0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"DPI_DMA7_ERR_RSP_STATUS"     ,	   0x1df0000000ab8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"DPI_DMA0_IBUFF_SADDR"        ,	   0x1df0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"DPI_DMA1_IBUFF_SADDR"        ,	   0x1df0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"DPI_DMA2_IBUFF_SADDR"        ,	   0x1df0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"DPI_DMA3_IBUFF_SADDR"        ,	   0x1df0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"DPI_DMA4_IBUFF_SADDR"        ,	   0x1df00000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"DPI_DMA5_IBUFF_SADDR"        ,	   0x1df00000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"DPI_DMA6_IBUFF_SADDR"        ,	   0x1df00000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"DPI_DMA7_IBUFF_SADDR"        ,	   0x1df00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"DPI_DMA0_IFLIGHT"            ,	   0x1df0000000a00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"DPI_DMA1_IFLIGHT"            ,	   0x1df0000000a08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"DPI_DMA2_IFLIGHT"            ,	   0x1df0000000a10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"DPI_DMA3_IFLIGHT"            ,	   0x1df0000000a18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"DPI_DMA4_IFLIGHT"            ,	   0x1df0000000a20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"DPI_DMA5_IFLIGHT"            ,	   0x1df0000000a28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"DPI_DMA6_IFLIGHT"            ,	   0x1df0000000a30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"DPI_DMA7_IFLIGHT"            ,	   0x1df0000000a38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"DPI_DMA0_NADDR"              ,	   0x1df0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"DPI_DMA1_NADDR"              ,	   0x1df0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"DPI_DMA2_NADDR"              ,	   0x1df0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"DPI_DMA3_NADDR"              ,	   0x1df0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"DPI_DMA4_NADDR"              ,	   0x1df00000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"DPI_DMA5_NADDR"              ,	   0x1df00000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"DPI_DMA6_NADDR"              ,	   0x1df00000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"DPI_DMA7_NADDR"              ,	   0x1df00000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"DPI_DMA0_REQBNK0"            ,	   0x1df0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"DPI_DMA1_REQBNK0"            ,	   0x1df0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"DPI_DMA2_REQBNK0"            ,	   0x1df0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"DPI_DMA3_REQBNK0"            ,	   0x1df0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"DPI_DMA4_REQBNK0"            ,	   0x1df0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"DPI_DMA5_REQBNK0"            ,	   0x1df0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"DPI_DMA6_REQBNK0"            ,	   0x1df0000000430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"DPI_DMA7_REQBNK0"            ,	   0x1df0000000438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"DPI_DMA0_REQBNK1"            ,	   0x1df0000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"DPI_DMA1_REQBNK1"            ,	   0x1df0000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"DPI_DMA2_REQBNK1"            ,	   0x1df0000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"DPI_DMA3_REQBNK1"            ,	   0x1df0000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"DPI_DMA4_REQBNK1"            ,	   0x1df00000004a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"DPI_DMA5_REQBNK1"            ,	   0x1df00000004a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"DPI_DMA6_REQBNK1"            ,	   0x1df00000004b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"DPI_DMA7_REQBNK1"            ,	   0x1df00000004b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"DPI_DMA_CONTROL"             ,	   0x1df0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"DPI_DMA_ENG0_EN"             ,	   0x1df0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"DPI_DMA_ENG1_EN"             ,	   0x1df0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"DPI_DMA_ENG2_EN"             ,	   0x1df0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"DPI_DMA_ENG3_EN"             ,	   0x1df0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"DPI_DMA_ENG4_EN"             ,	   0x1df00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"DPI_DMA_ENG5_EN"             ,	   0x1df00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"DPI_DMA_PP0_CNT"             ,	   0x1df0000000b00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"DPI_DMA_PP1_CNT"             ,	   0x1df0000000b08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"DPI_DMA_PP2_CNT"             ,	   0x1df0000000b10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"DPI_DMA_PP3_CNT"             ,	   0x1df0000000b18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"DPI_ENG0_BUF"                ,	   0x1df0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"DPI_ENG1_BUF"                ,	   0x1df0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"DPI_ENG2_BUF"                ,	   0x1df0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"DPI_ENG3_BUF"                ,	   0x1df0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"DPI_ENG4_BUF"                ,	   0x1df00000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"DPI_ENG5_BUF"                ,	   0x1df00000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"DPI_INFO_REG"                ,	   0x1df0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"DPI_INT_EN"                  ,	   0x1df0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"DPI_INT_REG"                 ,	   0x1df0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"DPI_NCB0_CFG"                ,	   0x1df0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"DPI_PINT_INFO"               ,	   0x1df0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"DPI_PKT_ERR_RSP"             ,	   0x1df0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"DPI_REQ_ERR_RSP"             ,	   0x1df0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"DPI_REQ_ERR_RSP_EN"          ,	   0x1df0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"DPI_REQ_ERR_RST"             ,	   0x1df0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"DPI_REQ_ERR_RST_EN"          ,	   0x1df0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"DPI_REQ_ERR_SKIP_COMP"       ,	   0x1df0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"DPI_REQ_GBL_EN"              ,	   0x1df0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"DPI_SLI_PRT0_CFG"            ,	   0x1df0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"DPI_SLI_PRT1_CFG"            ,	   0x1df0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"DPI_SLI_PRT0_ERR"            ,	   0x1df0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"DPI_SLI_PRT1_ERR"            ,	   0x1df0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"DPI_SLI_PRT0_ERR_INFO"       ,	   0x1df0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	185},
+	{"DPI_SLI_PRT1_ERR_INFO"       ,	   0x1df0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	185},
+	{"FPA_ADDR_RANGE_ERROR"        ,	   0x1180028000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"FPA_FPF3_MARKS"              ,	   0x1180028000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"FPA_FPF4_MARKS"              ,	   0x1180028000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"FPA_FPF5_MARKS"              ,	   0x1180028000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"FPA_FPF6_MARKS"              ,	   0x1180028000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"FPA_FPF7_MARKS"              ,	   0x1180028000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"FPA_FPF1_SIZE"               ,	   0x1180028000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"FPA_FPF2_SIZE"               ,	   0x1180028000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"FPA_FPF3_SIZE"               ,	   0x1180028000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"FPA_FPF4_SIZE"               ,	   0x1180028000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"FPA_FPF5_SIZE"               ,	   0x1180028000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"FPA_FPF6_SIZE"               ,	   0x1180028000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"FPA_FPF7_SIZE"               ,	   0x1180028000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"FPA_FPF0_MARKS"              ,	   0x1180028000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
+	{"FPA_FPF0_SIZE"               ,	   0x1180028000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
+	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
+	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
+	{"FPA_PACKET_THRESHOLD"        ,	   0x1180028000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"FPA_POOL0_END_ADDR"          ,	   0x1180028000358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"FPA_POOL1_END_ADDR"          ,	   0x1180028000360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"FPA_POOL2_END_ADDR"          ,	   0x1180028000368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"FPA_POOL3_END_ADDR"          ,	   0x1180028000370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"FPA_POOL4_END_ADDR"          ,	   0x1180028000378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"FPA_POOL5_END_ADDR"          ,	   0x1180028000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"FPA_POOL6_END_ADDR"          ,	   0x1180028000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"FPA_POOL7_END_ADDR"          ,	   0x1180028000390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"FPA_POOL0_START_ADDR"        ,	   0x1180028000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"FPA_POOL1_START_ADDR"        ,	   0x1180028000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"FPA_POOL2_START_ADDR"        ,	   0x1180028000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"FPA_POOL3_START_ADDR"        ,	   0x1180028000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"FPA_POOL4_START_ADDR"        ,	   0x1180028000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"FPA_POOL5_START_ADDR"        ,	   0x1180028000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"FPA_POOL6_START_ADDR"        ,	   0x1180028000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"FPA_POOL7_START_ADDR"        ,	   0x1180028000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"FPA_POOL0_THRESHOLD"         ,	   0x1180028000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"FPA_POOL1_THRESHOLD"         ,	   0x1180028000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"FPA_POOL2_THRESHOLD"         ,	   0x1180028000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"FPA_POOL3_THRESHOLD"         ,	   0x1180028000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"FPA_POOL4_THRESHOLD"         ,	   0x1180028000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"FPA_POOL5_THRESHOLD"         ,	   0x1180028000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"FPA_POOL6_THRESHOLD"         ,	   0x1180028000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"FPA_POOL7_THRESHOLD"         ,	   0x1180028000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"FPA_QUE5_PAGE_INDEX"         ,	   0x1180028000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"FPA_QUE6_PAGE_INDEX"         ,	   0x1180028000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"FPA_WQE_THRESHOLD"           ,	   0x1180028000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"GMX1_BAD_REG"                ,	   0x1180010000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	205},
+	{"GMX1_BIST"                   ,	   0x1180010000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	205},
+	{"GMX0_CLK_EN"                 ,	   0x11800080007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	206},
+	{"GMX1_CLK_EN"                 ,	   0x11800100007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	206},
+	{"GMX0_HG2_CONTROL"            ,	   0x1180008000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	207},
+	{"GMX1_HG2_CONTROL"            ,	   0x1180010000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	207},
+	{"GMX0_INF_MODE"               ,	   0x11800080007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	208},
+	{"GMX1_INF_MODE"               ,	   0x11800100007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	208},
+	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	209},
+	{"GMX1_NXA_ADR"                ,	   0x1180010000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	209},
+	{"GMX0_PRT000_CBFC_CTL"        ,	   0x1180008000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
+	{"GMX1_PRT000_CBFC_CTL"        ,	   0x1180010000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
+	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"GMX0_PRT002_CFG"             ,	   0x1180008001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"GMX0_PRT003_CFG"             ,	   0x1180008001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"GMX1_PRT000_CFG"             ,	   0x1180010000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"GMX1_PRT001_CFG"             ,	   0x1180010000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"GMX1_PRT002_CFG"             ,	   0x1180010001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"GMX1_PRT003_CFG"             ,	   0x1180010001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"GMX0_RX000_ADR_CAM0"         ,	   0x1180008000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"GMX0_RX001_ADR_CAM0"         ,	   0x1180008000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"GMX0_RX002_ADR_CAM0"         ,	   0x1180008001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"GMX0_RX003_ADR_CAM0"         ,	   0x1180008001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"GMX1_RX000_ADR_CAM0"         ,	   0x1180010000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"GMX1_RX001_ADR_CAM0"         ,	   0x1180010000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"GMX1_RX002_ADR_CAM0"         ,	   0x1180010001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"GMX1_RX003_ADR_CAM0"         ,	   0x1180010001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"GMX0_RX000_ADR_CAM1"         ,	   0x1180008000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"GMX0_RX001_ADR_CAM1"         ,	   0x1180008000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"GMX0_RX002_ADR_CAM1"         ,	   0x1180008001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"GMX0_RX003_ADR_CAM1"         ,	   0x1180008001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"GMX1_RX000_ADR_CAM1"         ,	   0x1180010000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"GMX1_RX001_ADR_CAM1"         ,	   0x1180010000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"GMX1_RX002_ADR_CAM1"         ,	   0x1180010001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"GMX1_RX003_ADR_CAM1"         ,	   0x1180010001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"GMX0_RX000_ADR_CAM2"         ,	   0x1180008000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"GMX0_RX001_ADR_CAM2"         ,	   0x1180008000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"GMX0_RX002_ADR_CAM2"         ,	   0x1180008001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"GMX0_RX003_ADR_CAM2"         ,	   0x1180008001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"GMX1_RX000_ADR_CAM2"         ,	   0x1180010000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"GMX1_RX001_ADR_CAM2"         ,	   0x1180010000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"GMX1_RX002_ADR_CAM2"         ,	   0x1180010001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"GMX1_RX003_ADR_CAM2"         ,	   0x1180010001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"GMX0_RX003_ADR_CAM3"         ,	   0x1180008001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"GMX1_RX000_ADR_CAM3"         ,	   0x1180010000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"GMX1_RX001_ADR_CAM3"         ,	   0x1180010000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"GMX1_RX002_ADR_CAM3"         ,	   0x1180010001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"GMX1_RX003_ADR_CAM3"         ,	   0x1180010001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"GMX0_RX000_ADR_CAM_ALL_EN"   ,	   0x1180008000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"GMX0_RX001_ADR_CAM_ALL_EN"   ,	   0x1180008000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"GMX0_RX002_ADR_CAM_ALL_EN"   ,	   0x1180008001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"GMX0_RX003_ADR_CAM_ALL_EN"   ,	   0x1180008001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"GMX1_RX000_ADR_CAM_ALL_EN"   ,	   0x1180010000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"GMX1_RX001_ADR_CAM_ALL_EN"   ,	   0x1180010000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"GMX1_RX002_ADR_CAM_ALL_EN"   ,	   0x1180010001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"GMX1_RX003_ADR_CAM_ALL_EN"   ,	   0x1180010001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"GMX0_RX003_ADR_CAM_EN"       ,	   0x1180008001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"GMX1_RX000_ADR_CAM_EN"       ,	   0x1180010000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"GMX1_RX001_ADR_CAM_EN"       ,	   0x1180010000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"GMX1_RX002_ADR_CAM_EN"       ,	   0x1180010001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"GMX1_RX003_ADR_CAM_EN"       ,	   0x1180010001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"GMX0_RX000_ADR_CTL"          ,	   0x1180008000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"GMX0_RX001_ADR_CTL"          ,	   0x1180008000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"GMX0_RX002_ADR_CTL"          ,	   0x1180008001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"GMX0_RX003_ADR_CTL"          ,	   0x1180008001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"GMX1_RX000_ADR_CTL"          ,	   0x1180010000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"GMX1_RX001_ADR_CTL"          ,	   0x1180010000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"GMX1_RX002_ADR_CTL"          ,	   0x1180010001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"GMX1_RX003_ADR_CTL"          ,	   0x1180010001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"GMX0_RX000_DECISION"         ,	   0x1180008000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"GMX0_RX001_DECISION"         ,	   0x1180008000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"GMX0_RX002_DECISION"         ,	   0x1180008001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"GMX0_RX003_DECISION"         ,	   0x1180008001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"GMX1_RX000_DECISION"         ,	   0x1180010000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"GMX1_RX001_DECISION"         ,	   0x1180010000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"GMX1_RX002_DECISION"         ,	   0x1180010001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"GMX1_RX003_DECISION"         ,	   0x1180010001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"GMX0_RX000_FRM_CHK"          ,	   0x1180008000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"GMX0_RX001_FRM_CHK"          ,	   0x1180008000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"GMX0_RX002_FRM_CHK"          ,	   0x1180008001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"GMX0_RX003_FRM_CHK"          ,	   0x1180008001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"GMX1_RX000_FRM_CHK"          ,	   0x1180010000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"GMX1_RX001_FRM_CHK"          ,	   0x1180010000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"GMX1_RX002_FRM_CHK"          ,	   0x1180010001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"GMX1_RX003_FRM_CHK"          ,	   0x1180010001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"GMX0_RX000_FRM_CTL"          ,	   0x1180008000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"GMX0_RX001_FRM_CTL"          ,	   0x1180008000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"GMX0_RX002_FRM_CTL"          ,	   0x1180008001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"GMX0_RX003_FRM_CTL"          ,	   0x1180008001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"GMX1_RX000_FRM_CTL"          ,	   0x1180010000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"GMX1_RX001_FRM_CTL"          ,	   0x1180010000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"GMX1_RX002_FRM_CTL"          ,	   0x1180010001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"GMX1_RX003_FRM_CTL"          ,	   0x1180010001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"GMX0_RX000_IFG"              ,	   0x1180008000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"GMX0_RX001_IFG"              ,	   0x1180008000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"GMX0_RX002_IFG"              ,	   0x1180008001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"GMX0_RX003_IFG"              ,	   0x1180008001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"GMX1_RX000_IFG"              ,	   0x1180010000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"GMX1_RX001_IFG"              ,	   0x1180010000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"GMX1_RX002_IFG"              ,	   0x1180010001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"GMX1_RX003_IFG"              ,	   0x1180010001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"GMX0_RX000_INT_EN"           ,	   0x1180008000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"GMX0_RX001_INT_EN"           ,	   0x1180008000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"GMX0_RX002_INT_EN"           ,	   0x1180008001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"GMX0_RX003_INT_EN"           ,	   0x1180008001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"GMX1_RX000_INT_EN"           ,	   0x1180010000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"GMX1_RX001_INT_EN"           ,	   0x1180010000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"GMX1_RX002_INT_EN"           ,	   0x1180010001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"GMX1_RX003_INT_EN"           ,	   0x1180010001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"GMX0_RX000_INT_REG"          ,	   0x1180008000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"GMX0_RX001_INT_REG"          ,	   0x1180008000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"GMX0_RX002_INT_REG"          ,	   0x1180008001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"GMX0_RX003_INT_REG"          ,	   0x1180008001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"GMX1_RX000_INT_REG"          ,	   0x1180010000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"GMX1_RX001_INT_REG"          ,	   0x1180010000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"GMX1_RX002_INT_REG"          ,	   0x1180010001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"GMX1_RX003_INT_REG"          ,	   0x1180010001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"GMX0_RX000_JABBER"           ,	   0x1180008000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"GMX0_RX001_JABBER"           ,	   0x1180008000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"GMX0_RX002_JABBER"           ,	   0x1180008001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"GMX0_RX003_JABBER"           ,	   0x1180008001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"GMX1_RX000_JABBER"           ,	   0x1180010000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"GMX1_RX001_JABBER"           ,	   0x1180010000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"GMX1_RX002_JABBER"           ,	   0x1180010001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"GMX1_RX003_JABBER"           ,	   0x1180010001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"GMX0_RX000_PAUSE_DROP_TIME"  ,	   0x1180008000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"GMX0_RX001_PAUSE_DROP_TIME"  ,	   0x1180008000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"GMX0_RX002_PAUSE_DROP_TIME"  ,	   0x1180008001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"GMX0_RX003_PAUSE_DROP_TIME"  ,	   0x1180008001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"GMX1_RX000_PAUSE_DROP_TIME"  ,	   0x1180010000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"GMX1_RX001_PAUSE_DROP_TIME"  ,	   0x1180010000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"GMX1_RX002_PAUSE_DROP_TIME"  ,	   0x1180010001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"GMX1_RX003_PAUSE_DROP_TIME"  ,	   0x1180010001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"GMX0_RX000_STATS_CTL"        ,	   0x1180008000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"GMX0_RX001_STATS_CTL"        ,	   0x1180008000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"GMX0_RX002_STATS_CTL"        ,	   0x1180008001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"GMX0_RX003_STATS_CTL"        ,	   0x1180008001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"GMX1_RX000_STATS_CTL"        ,	   0x1180010000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"GMX1_RX001_STATS_CTL"        ,	   0x1180010000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"GMX1_RX002_STATS_CTL"        ,	   0x1180010001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"GMX1_RX003_STATS_CTL"        ,	   0x1180010001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"GMX0_RX000_STATS_OCTS"       ,	   0x1180008000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"GMX0_RX001_STATS_OCTS"       ,	   0x1180008000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"GMX0_RX002_STATS_OCTS"       ,	   0x1180008001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"GMX0_RX003_STATS_OCTS"       ,	   0x1180008001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"GMX1_RX000_STATS_OCTS"       ,	   0x1180010000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"GMX1_RX001_STATS_OCTS"       ,	   0x1180010000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"GMX1_RX002_STATS_OCTS"       ,	   0x1180010001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"GMX1_RX003_STATS_OCTS"       ,	   0x1180010001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"GMX0_RX003_STATS_OCTS_CTL"   ,	   0x1180008001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"GMX1_RX000_STATS_OCTS_CTL"   ,	   0x1180010000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"GMX1_RX001_STATS_OCTS_CTL"   ,	   0x1180010000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"GMX1_RX002_STATS_OCTS_CTL"   ,	   0x1180010001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"GMX1_RX003_STATS_OCTS_CTL"   ,	   0x1180010001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"GMX0_RX003_STATS_PKTS"       ,	   0x1180008001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"GMX1_RX000_STATS_PKTS"       ,	   0x1180010000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"GMX1_RX001_STATS_PKTS"       ,	   0x1180010000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"GMX1_RX002_STATS_PKTS"       ,	   0x1180010001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"GMX1_RX003_STATS_PKTS"       ,	   0x1180010001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"GMX0_RX003_STATS_PKTS_CTL"   ,	   0x1180008001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"GMX1_RX000_STATS_PKTS_CTL"   ,	   0x1180010000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"GMX1_RX001_STATS_PKTS_CTL"   ,	   0x1180010000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"GMX1_RX002_STATS_PKTS_CTL"   ,	   0x1180010001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"GMX1_RX003_STATS_PKTS_CTL"   ,	   0x1180010001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"GMX0_RX003_UDD_SKP"          ,	   0x1180008001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"GMX1_RX000_UDD_SKP"          ,	   0x1180010000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"GMX1_RX001_UDD_SKP"          ,	   0x1180010000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"GMX1_RX002_UDD_SKP"          ,	   0x1180010001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"GMX1_RX003_UDD_SKP"          ,	   0x1180010001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"GMX0_RX_BP_DROP000"          ,	   0x1180008000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"GMX0_RX_BP_DROP001"          ,	   0x1180008000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"GMX0_RX_BP_DROP002"          ,	   0x1180008000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"GMX0_RX_BP_DROP003"          ,	   0x1180008000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"GMX1_RX_BP_DROP000"          ,	   0x1180010000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"GMX1_RX_BP_DROP001"          ,	   0x1180010000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"GMX1_RX_BP_DROP002"          ,	   0x1180010000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"GMX1_RX_BP_DROP003"          ,	   0x1180010000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"GMX0_RX_BP_OFF000"           ,	   0x1180008000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"GMX0_RX_BP_OFF001"           ,	   0x1180008000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"GMX0_RX_BP_OFF002"           ,	   0x1180008000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"GMX0_RX_BP_OFF003"           ,	   0x1180008000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"GMX1_RX_BP_OFF000"           ,	   0x1180010000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"GMX1_RX_BP_OFF001"           ,	   0x1180010000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"GMX1_RX_BP_OFF002"           ,	   0x1180010000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"GMX1_RX_BP_OFF003"           ,	   0x1180010000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"GMX0_RX_BP_ON003"            ,	   0x1180008000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"GMX1_RX_BP_ON000"            ,	   0x1180010000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"GMX1_RX_BP_ON001"            ,	   0x1180010000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"GMX1_RX_BP_ON002"            ,	   0x1180010000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"GMX1_RX_BP_ON003"            ,	   0x1180010000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"GMX0_RX_HG2_STATUS"          ,	   0x1180008000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"GMX1_RX_HG2_STATUS"          ,	   0x1180010000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"GMX1_RX_PRT_INFO"            ,	   0x11800100004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"GMX1_RX_PRTS"                ,	   0x1180010000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"GMX0_RX_XAUI_BAD_COL"        ,	   0x1180008000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"GMX1_RX_XAUI_BAD_COL"        ,	   0x1180010000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"GMX0_RX_XAUI_CTL"            ,	   0x1180008000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"GMX1_RX_XAUI_CTL"            ,	   0x1180010000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"GMX0_SMAC001"                ,	   0x1180008000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"GMX0_SMAC003"                ,	   0x1180008001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"GMX1_SMAC000"                ,	   0x1180010000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"GMX1_SMAC001"                ,	   0x1180010000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"GMX1_SMAC002"                ,	   0x1180010001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"GMX1_SMAC003"                ,	   0x1180010001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"GMX1_STAT_BP"                ,	   0x1180010000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"GMX0_TB_REG"                 ,	   0x11800080007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"GMX1_TB_REG"                 ,	   0x11800100007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX1_TX000_APPEND"           ,	   0x1180010000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX1_TX001_APPEND"           ,	   0x1180010000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX1_TX002_APPEND"           ,	   0x1180010001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX1_TX003_APPEND"           ,	   0x1180010001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"GMX1_TX000_BURST"            ,	   0x1180010000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"GMX1_TX001_BURST"            ,	   0x1180010000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"GMX1_TX002_BURST"            ,	   0x1180010001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"GMX1_TX003_BURST"            ,	   0x1180010001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"GMX0_TX000_CBFC_XOFF"        ,	   0x11800080005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"GMX1_TX000_CBFC_XOFF"        ,	   0x11800100005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"GMX0_TX000_CBFC_XON"         ,	   0x11800080005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"GMX1_TX000_CBFC_XON"         ,	   0x11800100005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX1_TX000_CTL"              ,	   0x1180010000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX1_TX001_CTL"              ,	   0x1180010000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX1_TX002_CTL"              ,	   0x1180010001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX1_TX003_CTL"              ,	   0x1180010001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX1_TX000_MIN_PKT"          ,	   0x1180010000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX1_TX002_MIN_PKT"          ,	   0x1180010001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX1_TX000_PAUSE_PKT_INTERVAL",	   0x1180010000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX1_TX002_PAUSE_PKT_INTERVAL",	   0x1180010001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX1_TX000_PAUSE_PKT_TIME"   ,	   0x1180010000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX1_TX002_PAUSE_PKT_TIME"   ,	   0x1180010001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX1_TX000_PAUSE_TOGO"       ,	   0x1180010000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX1_TX002_PAUSE_TOGO"       ,	   0x1180010001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX1_TX000_PAUSE_ZERO"       ,	   0x1180010000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX1_TX002_PAUSE_ZERO"       ,	   0x1180010001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX0_TX000_SGMII_CTL"        ,	   0x1180008000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX0_TX002_SGMII_CTL"        ,	   0x1180008001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX0_TX003_SGMII_CTL"        ,	   0x1180008001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX1_TX000_SGMII_CTL"        ,	   0x1180010000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX1_TX001_SGMII_CTL"        ,	   0x1180010000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX1_TX002_SGMII_CTL"        ,	   0x1180010001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX1_TX003_SGMII_CTL"        ,	   0x1180010001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX1_TX000_SLOT"             ,	   0x1180010000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX1_TX001_SLOT"             ,	   0x1180010000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX1_TX002_SLOT"             ,	   0x1180010001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX1_TX003_SLOT"             ,	   0x1180010001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX1_TX000_SOFT_PAUSE"       ,	   0x1180010000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX1_TX002_SOFT_PAUSE"       ,	   0x1180010001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX1_TX000_STAT0"            ,	   0x1180010000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX1_TX001_STAT0"            ,	   0x1180010000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX1_TX002_STAT0"            ,	   0x1180010001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX1_TX003_STAT0"            ,	   0x1180010001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX1_TX000_STAT1"            ,	   0x1180010000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX1_TX001_STAT1"            ,	   0x1180010000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX1_TX002_STAT1"            ,	   0x1180010001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX1_TX003_STAT1"            ,	   0x1180010001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX1_TX000_STAT2"            ,	   0x1180010000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX1_TX001_STAT2"            ,	   0x1180010000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX1_TX002_STAT2"            ,	   0x1180010001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX1_TX003_STAT2"            ,	   0x1180010001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX1_TX000_STAT3"            ,	   0x1180010000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX1_TX001_STAT3"            ,	   0x1180010000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX1_TX002_STAT3"            ,	   0x1180010001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX1_TX003_STAT3"            ,	   0x1180010001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX1_TX000_STAT4"            ,	   0x11800100002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX1_TX001_STAT4"            ,	   0x1180010000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX1_TX002_STAT4"            ,	   0x11800100012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX1_TX003_STAT4"            ,	   0x1180010001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX1_TX000_STAT5"            ,	   0x11800100002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX1_TX001_STAT5"            ,	   0x1180010000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX1_TX002_STAT5"            ,	   0x11800100012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX1_TX003_STAT5"            ,	   0x1180010001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX1_TX000_STAT6"            ,	   0x11800100002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX1_TX001_STAT6"            ,	   0x1180010000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX1_TX002_STAT6"            ,	   0x11800100012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX1_TX003_STAT6"            ,	   0x1180010001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX1_TX000_STAT7"            ,	   0x11800100002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX1_TX001_STAT7"            ,	   0x1180010000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX1_TX002_STAT7"            ,	   0x11800100012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX1_TX003_STAT7"            ,	   0x1180010001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX1_TX000_STAT8"            ,	   0x11800100002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX1_TX001_STAT8"            ,	   0x1180010000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX1_TX002_STAT8"            ,	   0x11800100012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX1_TX003_STAT8"            ,	   0x1180010001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX1_TX000_STAT9"            ,	   0x11800100002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX1_TX001_STAT9"            ,	   0x1180010000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX1_TX002_STAT9"            ,	   0x11800100012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX1_TX003_STAT9"            ,	   0x1180010001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX1_TX000_STATS_CTL"        ,	   0x1180010000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX1_TX002_STATS_CTL"        ,	   0x1180010001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX1_TX000_THRESH"           ,	   0x1180010000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX1_TX001_THRESH"           ,	   0x1180010000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX1_TX002_THRESH"           ,	   0x1180010001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX1_TX003_THRESH"           ,	   0x1180010001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX0_TX_BP"                  ,	   0x11800080004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"GMX1_TX_BP"                  ,	   0x11800100004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"GMX1_TX_COL_ATTEMPT"         ,	   0x1180010000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"GMX1_TX_CORRUPT"             ,	   0x11800100004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"GMX0_TX_HG2_REG1"            ,	   0x1180008000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"GMX1_TX_HG2_REG1"            ,	   0x1180010000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"GMX0_TX_HG2_REG2"            ,	   0x1180008000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"GMX1_TX_HG2_REG2"            ,	   0x1180010000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"GMX1_TX_IFG"                 ,	   0x1180010000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"GMX1_TX_INT_EN"              ,	   0x1180010000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"GMX1_TX_INT_REG"             ,	   0x1180010000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"GMX1_TX_JAM"                 ,	   0x1180010000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"GMX1_TX_LFSR"                ,	   0x11800100004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"GMX1_TX_OVR_BP"              ,	   0x11800100004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
+	{"GMX1_TX_PRTS"                ,	   0x1180010000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
+	{"GMX0_TX_XAUI_CTL"            ,	   0x1180008000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"GMX1_TX_XAUI_CTL"            ,	   0x1180010000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"GMX0_XAUI_EXT_LOOPBACK"      ,	   0x1180008000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"GMX1_XAUI_EXT_LOOPBACK"      ,	   0x1180010000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"GPIO_BIT_CFG3"               ,	   0x1070000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"GPIO_BIT_CFG4"               ,	   0x1070000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"GPIO_BIT_CFG5"               ,	   0x1070000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"GPIO_BIT_CFG6"               ,	   0x1070000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"GPIO_BIT_CFG7"               ,	   0x1070000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"GPIO_BIT_CFG8"               ,	   0x1070000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"GPIO_BIT_CFG9"               ,	   0x1070000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"GPIO_BIT_CFG10"              ,	   0x1070000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"GPIO_BIT_CFG11"              ,	   0x1070000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"GPIO_BIT_CFG12"              ,	   0x1070000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"GPIO_CLK_GEN0"               ,	   0x10700000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	293},
+	{"GPIO_CLK_GEN1"               ,	   0x10700000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	293},
+	{"GPIO_CLK_GEN2"               ,	   0x10700000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	293},
+	{"GPIO_CLK_GEN3"               ,	   0x10700000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	293},
+	{"GPIO_CLK_QLM0"               ,	   0x10700000008e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	294},
+	{"GPIO_CLK_QLM1"               ,	   0x10700000008e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	294},
+	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"GPIO_MULTI_CAST"             ,	   0x10700000008b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	296},
+	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	297},
+	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	298},
+	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
+	{"GPIO_XBIT_CFG16"             ,	   0x1070000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	300},
+	{"GPIO_XBIT_CFG17"             ,	   0x1070000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	300},
+	{"GPIO_XBIT_CFG18"             ,	   0x1070000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	300},
+	{"GPIO_XBIT_CFG19"             ,	   0x1070000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	300},
+	{"IOB_BIST_STATUS"             ,	   0x11800f00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"IOB_CTL_STATUS"              ,	   0x11800f0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800f0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800f0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800f0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800f0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800f0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800f0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800f0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"IOB_INT_ENB"                 ,	   0x11800f0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"IOB_INT_SUM"                 ,	   0x11800f0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800f0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800f0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800f0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800f0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800f00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800f0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800f00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800f0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800f0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800f0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"IOB_PKT_ERR"                 ,	   0x11800f0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"IOB_TO_CMB_CREDITS"          ,	   0x11800f00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	325},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"IPD_BIST_STATUS"             ,	   0x14f00000007f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14f0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
+	{"IPD_CLK_COUNT"               ,	   0x14f0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
+	{"IPD_CTL_STATUS"              ,	   0x14f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	330},
+	{"IPD_INT_ENB"                 ,	   0x14f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	331},
+	{"IPD_INT_SUM"                 ,	   0x14f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	333},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14f0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14f00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14f00000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14f00000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14f00000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14f0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14f0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"IPD_PORT36_BP_PAGE_CNT2"     ,	   0x14f0000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT37_BP_PAGE_CNT2"     ,	   0x14f0000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT38_BP_PAGE_CNT2"     ,	   0x14f0000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT39_BP_PAGE_CNT2"     ,	   0x14f0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT40_BP_PAGE_CNT3"     ,	   0x14f00000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT41_BP_PAGE_CNT3"     ,	   0x14f00000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT42_BP_PAGE_CNT3"     ,	   0x14f00000003e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT43_BP_PAGE_CNT3"     ,	   0x14f00000003e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT44_BP_PAGE_CNT3"     ,	   0x14f00000003f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT45_BP_PAGE_CNT3"     ,	   0x14f00000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT46_BP_PAGE_CNT3"     ,	   0x14f0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT47_BP_PAGE_CNT3"     ,	   0x14f0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_BP_COUNTERS2_PAIR36",	   0x14f0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"IPD_PORT_BP_COUNTERS2_PAIR37",	   0x14f0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"IPD_PORT_BP_COUNTERS2_PAIR38",	   0x14f0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"IPD_PORT_BP_COUNTERS2_PAIR39",	   0x14f00000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"IPD_PORT_BP_COUNTERS3_PAIR40",	   0x14f00000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"IPD_PORT_BP_COUNTERS3_PAIR41",	   0x14f00000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"IPD_PORT_BP_COUNTERS3_PAIR42",	   0x14f00000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"IPD_PORT_BP_COUNTERS3_PAIR43",	   0x14f00000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"IPD_PORT_BP_COUNTERS4_PAIR44",	   0x14f0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"IPD_PORT_BP_COUNTERS4_PAIR45",	   0x14f0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"IPD_PORT_BP_COUNTERS4_PAIR46",	   0x14f0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"IPD_PORT_BP_COUNTERS4_PAIR47",	   0x14f0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14f00000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14f0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14f0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14f0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14f0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14f00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14f00000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14f00000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14f00000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_QOS_0_CNT"          ,	   0x14f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_1_CNT"          ,	   0x14f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_2_CNT"          ,	   0x14f0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_3_CNT"          ,	   0x14f00000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_4_CNT"          ,	   0x14f00000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_5_CNT"          ,	   0x14f00000008b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_6_CNT"          ,	   0x14f00000008b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_7_CNT"          ,	   0x14f00000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_8_CNT"          ,	   0x14f00000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_9_CNT"          ,	   0x14f00000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_10_CNT"         ,	   0x14f00000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_11_CNT"         ,	   0x14f00000008e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_12_CNT"         ,	   0x14f00000008e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_13_CNT"         ,	   0x14f00000008f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_14_CNT"         ,	   0x14f00000008f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_15_CNT"         ,	   0x14f0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_16_CNT"         ,	   0x14f0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_17_CNT"         ,	   0x14f0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_18_CNT"         ,	   0x14f0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_19_CNT"         ,	   0x14f0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_20_CNT"         ,	   0x14f0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_21_CNT"         ,	   0x14f0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_22_CNT"         ,	   0x14f0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_23_CNT"         ,	   0x14f0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_24_CNT"         ,	   0x14f0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_25_CNT"         ,	   0x14f0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_26_CNT"         ,	   0x14f0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_27_CNT"         ,	   0x14f0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_28_CNT"         ,	   0x14f0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_29_CNT"         ,	   0x14f0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_30_CNT"         ,	   0x14f0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_31_CNT"         ,	   0x14f0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_128_CNT"        ,	   0x14f0000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_129_CNT"        ,	   0x14f0000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_130_CNT"        ,	   0x14f0000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_131_CNT"        ,	   0x14f0000000ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_132_CNT"        ,	   0x14f0000000ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_133_CNT"        ,	   0x14f0000000cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_134_CNT"        ,	   0x14f0000000cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_135_CNT"        ,	   0x14f0000000cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_136_CNT"        ,	   0x14f0000000cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_137_CNT"        ,	   0x14f0000000cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_138_CNT"        ,	   0x14f0000000cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_139_CNT"        ,	   0x14f0000000ce0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_140_CNT"        ,	   0x14f0000000ce8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_141_CNT"        ,	   0x14f0000000cf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_142_CNT"        ,	   0x14f0000000cf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_143_CNT"        ,	   0x14f0000000d00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_144_CNT"        ,	   0x14f0000000d08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_145_CNT"        ,	   0x14f0000000d10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_146_CNT"        ,	   0x14f0000000d18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_147_CNT"        ,	   0x14f0000000d20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_148_CNT"        ,	   0x14f0000000d28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_149_CNT"        ,	   0x14f0000000d30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_150_CNT"        ,	   0x14f0000000d38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_151_CNT"        ,	   0x14f0000000d40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_152_CNT"        ,	   0x14f0000000d48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_153_CNT"        ,	   0x14f0000000d50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_154_CNT"        ,	   0x14f0000000d58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_155_CNT"        ,	   0x14f0000000d60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_156_CNT"        ,	   0x14f0000000d68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_157_CNT"        ,	   0x14f0000000d70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_158_CNT"        ,	   0x14f0000000d78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_159_CNT"        ,	   0x14f0000000d80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_256_CNT"        ,	   0x14f0000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_257_CNT"        ,	   0x14f0000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_258_CNT"        ,	   0x14f0000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_259_CNT"        ,	   0x14f00000010a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_260_CNT"        ,	   0x14f00000010a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_261_CNT"        ,	   0x14f00000010b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_262_CNT"        ,	   0x14f00000010b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_263_CNT"        ,	   0x14f00000010c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_264_CNT"        ,	   0x14f00000010c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_265_CNT"        ,	   0x14f00000010d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_266_CNT"        ,	   0x14f00000010d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_267_CNT"        ,	   0x14f00000010e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_268_CNT"        ,	   0x14f00000010e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_269_CNT"        ,	   0x14f00000010f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_270_CNT"        ,	   0x14f00000010f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_271_CNT"        ,	   0x14f0000001100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_272_CNT"        ,	   0x14f0000001108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_273_CNT"        ,	   0x14f0000001110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_274_CNT"        ,	   0x14f0000001118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_275_CNT"        ,	   0x14f0000001120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_276_CNT"        ,	   0x14f0000001128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_277_CNT"        ,	   0x14f0000001130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_278_CNT"        ,	   0x14f0000001138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_279_CNT"        ,	   0x14f0000001140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_280_CNT"        ,	   0x14f0000001148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_281_CNT"        ,	   0x14f0000001150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_282_CNT"        ,	   0x14f0000001158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_283_CNT"        ,	   0x14f0000001160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_284_CNT"        ,	   0x14f0000001168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_285_CNT"        ,	   0x14f0000001170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_286_CNT"        ,	   0x14f0000001178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_287_CNT"        ,	   0x14f0000001180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_288_CNT"        ,	   0x14f0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_289_CNT"        ,	   0x14f0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_290_CNT"        ,	   0x14f0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_291_CNT"        ,	   0x14f00000011a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_292_CNT"        ,	   0x14f00000011a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_293_CNT"        ,	   0x14f00000011b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_294_CNT"        ,	   0x14f00000011b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_295_CNT"        ,	   0x14f00000011c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_296_CNT"        ,	   0x14f00000011c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_297_CNT"        ,	   0x14f00000011d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_298_CNT"        ,	   0x14f00000011d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_299_CNT"        ,	   0x14f00000011e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_300_CNT"        ,	   0x14f00000011e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_301_CNT"        ,	   0x14f00000011f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_302_CNT"        ,	   0x14f00000011f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_303_CNT"        ,	   0x14f0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_304_CNT"        ,	   0x14f0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_305_CNT"        ,	   0x14f0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_306_CNT"        ,	   0x14f0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_307_CNT"        ,	   0x14f0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_308_CNT"        ,	   0x14f0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_309_CNT"        ,	   0x14f0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_310_CNT"        ,	   0x14f0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_311_CNT"        ,	   0x14f0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_312_CNT"        ,	   0x14f0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_313_CNT"        ,	   0x14f0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_314_CNT"        ,	   0x14f0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_315_CNT"        ,	   0x14f0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_316_CNT"        ,	   0x14f0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_317_CNT"        ,	   0x14f0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_318_CNT"        ,	   0x14f0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_319_CNT"        ,	   0x14f0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_320_CNT"        ,	   0x14f0000001288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_321_CNT"        ,	   0x14f0000001290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_322_CNT"        ,	   0x14f0000001298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_323_CNT"        ,	   0x14f00000012a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_324_CNT"        ,	   0x14f00000012a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_325_CNT"        ,	   0x14f00000012b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_326_CNT"        ,	   0x14f00000012b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_327_CNT"        ,	   0x14f00000012c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_328_CNT"        ,	   0x14f00000012c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_329_CNT"        ,	   0x14f00000012d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_330_CNT"        ,	   0x14f00000012d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_331_CNT"        ,	   0x14f00000012e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_332_CNT"        ,	   0x14f00000012e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_333_CNT"        ,	   0x14f00000012f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_334_CNT"        ,	   0x14f00000012f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_335_CNT"        ,	   0x14f0000001300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_336_CNT"        ,	   0x14f0000001308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_337_CNT"        ,	   0x14f0000001310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_338_CNT"        ,	   0x14f0000001318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_339_CNT"        ,	   0x14f0000001320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_340_CNT"        ,	   0x14f0000001328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_341_CNT"        ,	   0x14f0000001330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_342_CNT"        ,	   0x14f0000001338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_343_CNT"        ,	   0x14f0000001340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_344_CNT"        ,	   0x14f0000001348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_345_CNT"        ,	   0x14f0000001350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_346_CNT"        ,	   0x14f0000001358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_347_CNT"        ,	   0x14f0000001360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_348_CNT"        ,	   0x14f0000001368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_349_CNT"        ,	   0x14f0000001370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_350_CNT"        ,	   0x14f0000001378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_351_CNT"        ,	   0x14f0000001380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_352_CNT"        ,	   0x14f0000001388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_353_CNT"        ,	   0x14f0000001390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_354_CNT"        ,	   0x14f0000001398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_355_CNT"        ,	   0x14f00000013a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_356_CNT"        ,	   0x14f00000013a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_357_CNT"        ,	   0x14f00000013b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_358_CNT"        ,	   0x14f00000013b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_359_CNT"        ,	   0x14f00000013c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_360_CNT"        ,	   0x14f00000013c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_361_CNT"        ,	   0x14f00000013d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_362_CNT"        ,	   0x14f00000013d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_363_CNT"        ,	   0x14f00000013e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_364_CNT"        ,	   0x14f00000013e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_365_CNT"        ,	   0x14f00000013f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_366_CNT"        ,	   0x14f00000013f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_367_CNT"        ,	   0x14f0000001400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_368_CNT"        ,	   0x14f0000001408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_369_CNT"        ,	   0x14f0000001410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_370_CNT"        ,	   0x14f0000001418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_371_CNT"        ,	   0x14f0000001420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_372_CNT"        ,	   0x14f0000001428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_373_CNT"        ,	   0x14f0000001430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_374_CNT"        ,	   0x14f0000001438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_375_CNT"        ,	   0x14f0000001440ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_376_CNT"        ,	   0x14f0000001448ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_377_CNT"        ,	   0x14f0000001450ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_378_CNT"        ,	   0x14f0000001458ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_379_CNT"        ,	   0x14f0000001460ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_380_CNT"        ,	   0x14f0000001468ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_381_CNT"        ,	   0x14f0000001470ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_382_CNT"        ,	   0x14f0000001478ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_383_CNT"        ,	   0x14f0000001480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_INT0"           ,	   0x14f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"IPD_PORT_QOS_INT2"           ,	   0x14f0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"IPD_PORT_QOS_INT4"           ,	   0x14f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"IPD_PORT_QOS_INT5"           ,	   0x14f0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"IPD_PORT_QOS_INT_ENB2"       ,	   0x14f0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"IPD_PORT_QOS_INT_ENB5"       ,	   0x14f0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14f0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14f0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	347},
+	{"IPD_PTR_COUNT"               ,	   0x14f0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14f0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14f0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14f00000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	352},
+	{"IPD_RED_PORT_ENABLE2"        ,	   0x14f00000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	353},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14f00000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14f00000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14f00000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14f00000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14f0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14f0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14f0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14f0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	355},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
+	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	357},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14f0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
+	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	361},
+	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	362},
+	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_BIG_CTL"                 ,	   0x1180080800030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
+	{"L2C_BST"                     ,	   0x11800808007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_BST_MEM0"                ,	   0x1180080c007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"L2C_BST_TDT0"                ,	   0x1180080a007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"L2C_BST_TTG0"                ,	   0x1180080a007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"L2C_COP0_MAP0"               ,	   0x1180080940000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1"               ,	   0x1180080940008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP2"               ,	   0x1180080940010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP3"               ,	   0x1180080940018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP4"               ,	   0x1180080940020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP5"               ,	   0x1180080940028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP6"               ,	   0x1180080940030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP7"               ,	   0x1180080940038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP8"               ,	   0x1180080940040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP9"               ,	   0x1180080940048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP10"              ,	   0x1180080940050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP11"              ,	   0x1180080940058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP12"              ,	   0x1180080940060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP13"              ,	   0x1180080940068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP14"              ,	   0x1180080940070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP15"              ,	   0x1180080940078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16"              ,	   0x1180080940080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP17"              ,	   0x1180080940088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP18"              ,	   0x1180080940090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP19"              ,	   0x1180080940098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP20"              ,	   0x11800809400a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP21"              ,	   0x11800809400a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP22"              ,	   0x11800809400b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP23"              ,	   0x11800809400b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP24"              ,	   0x11800809400c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP25"              ,	   0x11800809400c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP26"              ,	   0x11800809400d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP27"              ,	   0x11800809400d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP28"              ,	   0x11800809400e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP29"              ,	   0x11800809400e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP30"              ,	   0x11800809400f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP31"              ,	   0x11800809400f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP32"              ,	   0x1180080940100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP33"              ,	   0x1180080940108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP34"              ,	   0x1180080940110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP35"              ,	   0x1180080940118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP36"              ,	   0x1180080940120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP37"              ,	   0x1180080940128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP38"              ,	   0x1180080940130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP39"              ,	   0x1180080940138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP40"              ,	   0x1180080940140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP41"              ,	   0x1180080940148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP42"              ,	   0x1180080940150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP43"              ,	   0x1180080940158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP44"              ,	   0x1180080940160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP45"              ,	   0x1180080940168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP46"              ,	   0x1180080940170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP47"              ,	   0x1180080940178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP48"              ,	   0x1180080940180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP49"              ,	   0x1180080940188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP50"              ,	   0x1180080940190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP51"              ,	   0x1180080940198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP52"              ,	   0x11800809401a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP53"              ,	   0x11800809401a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP54"              ,	   0x11800809401b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP55"              ,	   0x11800809401b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP56"              ,	   0x11800809401c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP57"              ,	   0x11800809401c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP58"              ,	   0x11800809401d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP59"              ,	   0x11800809401d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP60"              ,	   0x11800809401e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP61"              ,	   0x11800809401e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP62"              ,	   0x11800809401f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP63"              ,	   0x11800809401f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP64"              ,	   0x1180080940200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP65"              ,	   0x1180080940208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP66"              ,	   0x1180080940210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP67"              ,	   0x1180080940218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP68"              ,	   0x1180080940220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP69"              ,	   0x1180080940228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP70"              ,	   0x1180080940230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP71"              ,	   0x1180080940238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP72"              ,	   0x1180080940240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP73"              ,	   0x1180080940248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP74"              ,	   0x1180080940250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP75"              ,	   0x1180080940258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP76"              ,	   0x1180080940260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP77"              ,	   0x1180080940268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP78"              ,	   0x1180080940270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP79"              ,	   0x1180080940278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP80"              ,	   0x1180080940280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP81"              ,	   0x1180080940288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP82"              ,	   0x1180080940290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP83"              ,	   0x1180080940298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP84"              ,	   0x11800809402a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP85"              ,	   0x11800809402a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP86"              ,	   0x11800809402b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP87"              ,	   0x11800809402b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP88"              ,	   0x11800809402c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP89"              ,	   0x11800809402c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP90"              ,	   0x11800809402d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP91"              ,	   0x11800809402d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP92"              ,	   0x11800809402e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP93"              ,	   0x11800809402e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP94"              ,	   0x11800809402f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP95"              ,	   0x11800809402f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP96"              ,	   0x1180080940300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP97"              ,	   0x1180080940308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP98"              ,	   0x1180080940310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP99"              ,	   0x1180080940318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP100"             ,	   0x1180080940320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP101"             ,	   0x1180080940328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP102"             ,	   0x1180080940330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP103"             ,	   0x1180080940338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP104"             ,	   0x1180080940340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP105"             ,	   0x1180080940348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP106"             ,	   0x1180080940350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP107"             ,	   0x1180080940358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP108"             ,	   0x1180080940360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP109"             ,	   0x1180080940368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP110"             ,	   0x1180080940370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP111"             ,	   0x1180080940378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP112"             ,	   0x1180080940380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP113"             ,	   0x1180080940388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP114"             ,	   0x1180080940390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP115"             ,	   0x1180080940398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP116"             ,	   0x11800809403a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP117"             ,	   0x11800809403a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP118"             ,	   0x11800809403b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP119"             ,	   0x11800809403b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP120"             ,	   0x11800809403c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP121"             ,	   0x11800809403c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP122"             ,	   0x11800809403d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP123"             ,	   0x11800809403d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP124"             ,	   0x11800809403e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP125"             ,	   0x11800809403e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP126"             ,	   0x11800809403f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP127"             ,	   0x11800809403f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP128"             ,	   0x1180080940400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP129"             ,	   0x1180080940408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP130"             ,	   0x1180080940410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP131"             ,	   0x1180080940418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP132"             ,	   0x1180080940420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP133"             ,	   0x1180080940428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP134"             ,	   0x1180080940430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP135"             ,	   0x1180080940438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP136"             ,	   0x1180080940440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP137"             ,	   0x1180080940448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP138"             ,	   0x1180080940450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP139"             ,	   0x1180080940458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP140"             ,	   0x1180080940460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP141"             ,	   0x1180080940468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP142"             ,	   0x1180080940470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP143"             ,	   0x1180080940478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP144"             ,	   0x1180080940480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP145"             ,	   0x1180080940488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP146"             ,	   0x1180080940490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP147"             ,	   0x1180080940498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP148"             ,	   0x11800809404a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP149"             ,	   0x11800809404a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP150"             ,	   0x11800809404b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP151"             ,	   0x11800809404b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP152"             ,	   0x11800809404c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP153"             ,	   0x11800809404c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP154"             ,	   0x11800809404d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP155"             ,	   0x11800809404d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP156"             ,	   0x11800809404e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP157"             ,	   0x11800809404e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP158"             ,	   0x11800809404f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP159"             ,	   0x11800809404f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP160"             ,	   0x1180080940500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP161"             ,	   0x1180080940508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP162"             ,	   0x1180080940510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP163"             ,	   0x1180080940518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP164"             ,	   0x1180080940520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP165"             ,	   0x1180080940528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP166"             ,	   0x1180080940530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP167"             ,	   0x1180080940538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP168"             ,	   0x1180080940540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP169"             ,	   0x1180080940548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP170"             ,	   0x1180080940550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP171"             ,	   0x1180080940558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP172"             ,	   0x1180080940560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP173"             ,	   0x1180080940568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP174"             ,	   0x1180080940570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP175"             ,	   0x1180080940578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP176"             ,	   0x1180080940580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP177"             ,	   0x1180080940588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP178"             ,	   0x1180080940590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP179"             ,	   0x1180080940598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP180"             ,	   0x11800809405a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP181"             ,	   0x11800809405a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP182"             ,	   0x11800809405b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP183"             ,	   0x11800809405b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP184"             ,	   0x11800809405c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP185"             ,	   0x11800809405c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP186"             ,	   0x11800809405d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP187"             ,	   0x11800809405d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP188"             ,	   0x11800809405e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP189"             ,	   0x11800809405e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP190"             ,	   0x11800809405f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP191"             ,	   0x11800809405f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP192"             ,	   0x1180080940600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP193"             ,	   0x1180080940608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP194"             ,	   0x1180080940610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP195"             ,	   0x1180080940618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP196"             ,	   0x1180080940620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP197"             ,	   0x1180080940628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP198"             ,	   0x1180080940630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP199"             ,	   0x1180080940638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP200"             ,	   0x1180080940640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP201"             ,	   0x1180080940648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP202"             ,	   0x1180080940650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP203"             ,	   0x1180080940658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP204"             ,	   0x1180080940660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP205"             ,	   0x1180080940668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP206"             ,	   0x1180080940670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP207"             ,	   0x1180080940678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP208"             ,	   0x1180080940680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP209"             ,	   0x1180080940688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP210"             ,	   0x1180080940690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP211"             ,	   0x1180080940698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP212"             ,	   0x11800809406a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP213"             ,	   0x11800809406a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP214"             ,	   0x11800809406b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP215"             ,	   0x11800809406b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP216"             ,	   0x11800809406c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP217"             ,	   0x11800809406c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP218"             ,	   0x11800809406d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP219"             ,	   0x11800809406d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP220"             ,	   0x11800809406e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP221"             ,	   0x11800809406e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP222"             ,	   0x11800809406f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP223"             ,	   0x11800809406f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP224"             ,	   0x1180080940700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP225"             ,	   0x1180080940708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP226"             ,	   0x1180080940710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP227"             ,	   0x1180080940718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP228"             ,	   0x1180080940720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP229"             ,	   0x1180080940728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP230"             ,	   0x1180080940730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP231"             ,	   0x1180080940738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP232"             ,	   0x1180080940740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP233"             ,	   0x1180080940748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP234"             ,	   0x1180080940750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP235"             ,	   0x1180080940758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP236"             ,	   0x1180080940760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP237"             ,	   0x1180080940768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP238"             ,	   0x1180080940770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP239"             ,	   0x1180080940778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP240"             ,	   0x1180080940780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP241"             ,	   0x1180080940788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP242"             ,	   0x1180080940790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP243"             ,	   0x1180080940798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP244"             ,	   0x11800809407a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP245"             ,	   0x11800809407a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP246"             ,	   0x11800809407b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP247"             ,	   0x11800809407b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP248"             ,	   0x11800809407c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP249"             ,	   0x11800809407c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP250"             ,	   0x11800809407d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP251"             ,	   0x11800809407d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP252"             ,	   0x11800809407e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP253"             ,	   0x11800809407e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP254"             ,	   0x11800809407f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP255"             ,	   0x11800809407f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP256"             ,	   0x1180080940800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP257"             ,	   0x1180080940808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP258"             ,	   0x1180080940810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP259"             ,	   0x1180080940818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP260"             ,	   0x1180080940820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP261"             ,	   0x1180080940828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP262"             ,	   0x1180080940830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP263"             ,	   0x1180080940838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP264"             ,	   0x1180080940840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP265"             ,	   0x1180080940848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP266"             ,	   0x1180080940850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP267"             ,	   0x1180080940858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP268"             ,	   0x1180080940860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP269"             ,	   0x1180080940868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP270"             ,	   0x1180080940870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP271"             ,	   0x1180080940878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP272"             ,	   0x1180080940880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP273"             ,	   0x1180080940888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP274"             ,	   0x1180080940890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP275"             ,	   0x1180080940898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP276"             ,	   0x11800809408a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP277"             ,	   0x11800809408a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP278"             ,	   0x11800809408b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP279"             ,	   0x11800809408b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP280"             ,	   0x11800809408c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP281"             ,	   0x11800809408c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP282"             ,	   0x11800809408d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP283"             ,	   0x11800809408d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP284"             ,	   0x11800809408e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP285"             ,	   0x11800809408e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP286"             ,	   0x11800809408f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP287"             ,	   0x11800809408f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP288"             ,	   0x1180080940900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP289"             ,	   0x1180080940908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP290"             ,	   0x1180080940910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP291"             ,	   0x1180080940918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP292"             ,	   0x1180080940920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP293"             ,	   0x1180080940928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP294"             ,	   0x1180080940930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP295"             ,	   0x1180080940938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP296"             ,	   0x1180080940940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP297"             ,	   0x1180080940948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP298"             ,	   0x1180080940950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP299"             ,	   0x1180080940958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP300"             ,	   0x1180080940960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP301"             ,	   0x1180080940968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP302"             ,	   0x1180080940970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP303"             ,	   0x1180080940978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP304"             ,	   0x1180080940980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP305"             ,	   0x1180080940988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP306"             ,	   0x1180080940990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP307"             ,	   0x1180080940998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP308"             ,	   0x11800809409a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP309"             ,	   0x11800809409a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP310"             ,	   0x11800809409b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP311"             ,	   0x11800809409b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP312"             ,	   0x11800809409c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP313"             ,	   0x11800809409c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP314"             ,	   0x11800809409d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP315"             ,	   0x11800809409d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP316"             ,	   0x11800809409e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP317"             ,	   0x11800809409e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP318"             ,	   0x11800809409f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP319"             ,	   0x11800809409f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP320"             ,	   0x1180080940a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP321"             ,	   0x1180080940a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP322"             ,	   0x1180080940a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP323"             ,	   0x1180080940a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP324"             ,	   0x1180080940a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP325"             ,	   0x1180080940a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP326"             ,	   0x1180080940a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP327"             ,	   0x1180080940a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP328"             ,	   0x1180080940a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP329"             ,	   0x1180080940a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP330"             ,	   0x1180080940a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP331"             ,	   0x1180080940a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP332"             ,	   0x1180080940a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP333"             ,	   0x1180080940a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP334"             ,	   0x1180080940a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP335"             ,	   0x1180080940a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP336"             ,	   0x1180080940a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP337"             ,	   0x1180080940a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP338"             ,	   0x1180080940a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP339"             ,	   0x1180080940a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP340"             ,	   0x1180080940aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP341"             ,	   0x1180080940aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP342"             ,	   0x1180080940ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP343"             ,	   0x1180080940ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP344"             ,	   0x1180080940ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP345"             ,	   0x1180080940ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP346"             ,	   0x1180080940ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP347"             ,	   0x1180080940ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP348"             ,	   0x1180080940ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP349"             ,	   0x1180080940ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP350"             ,	   0x1180080940af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP351"             ,	   0x1180080940af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP352"             ,	   0x1180080940b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP353"             ,	   0x1180080940b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP354"             ,	   0x1180080940b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP355"             ,	   0x1180080940b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP356"             ,	   0x1180080940b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP357"             ,	   0x1180080940b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP358"             ,	   0x1180080940b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP359"             ,	   0x1180080940b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP360"             ,	   0x1180080940b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP361"             ,	   0x1180080940b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP362"             ,	   0x1180080940b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP363"             ,	   0x1180080940b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP364"             ,	   0x1180080940b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP365"             ,	   0x1180080940b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP366"             ,	   0x1180080940b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP367"             ,	   0x1180080940b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP368"             ,	   0x1180080940b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP369"             ,	   0x1180080940b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP370"             ,	   0x1180080940b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP371"             ,	   0x1180080940b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP372"             ,	   0x1180080940ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP373"             ,	   0x1180080940ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP374"             ,	   0x1180080940bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP375"             ,	   0x1180080940bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP376"             ,	   0x1180080940bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP377"             ,	   0x1180080940bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP378"             ,	   0x1180080940bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP379"             ,	   0x1180080940bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP380"             ,	   0x1180080940be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP381"             ,	   0x1180080940be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP382"             ,	   0x1180080940bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP383"             ,	   0x1180080940bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP384"             ,	   0x1180080940c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP385"             ,	   0x1180080940c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP386"             ,	   0x1180080940c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP387"             ,	   0x1180080940c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP388"             ,	   0x1180080940c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP389"             ,	   0x1180080940c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP390"             ,	   0x1180080940c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP391"             ,	   0x1180080940c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP392"             ,	   0x1180080940c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP393"             ,	   0x1180080940c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP394"             ,	   0x1180080940c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP395"             ,	   0x1180080940c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP396"             ,	   0x1180080940c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP397"             ,	   0x1180080940c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP398"             ,	   0x1180080940c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP399"             ,	   0x1180080940c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP400"             ,	   0x1180080940c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP401"             ,	   0x1180080940c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP402"             ,	   0x1180080940c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP403"             ,	   0x1180080940c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP404"             ,	   0x1180080940ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP405"             ,	   0x1180080940ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP406"             ,	   0x1180080940cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP407"             ,	   0x1180080940cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP408"             ,	   0x1180080940cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP409"             ,	   0x1180080940cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP410"             ,	   0x1180080940cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP411"             ,	   0x1180080940cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP412"             ,	   0x1180080940ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP413"             ,	   0x1180080940ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP414"             ,	   0x1180080940cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP415"             ,	   0x1180080940cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP416"             ,	   0x1180080940d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP417"             ,	   0x1180080940d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP418"             ,	   0x1180080940d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP419"             ,	   0x1180080940d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP420"             ,	   0x1180080940d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP421"             ,	   0x1180080940d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP422"             ,	   0x1180080940d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP423"             ,	   0x1180080940d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP424"             ,	   0x1180080940d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP425"             ,	   0x1180080940d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP426"             ,	   0x1180080940d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP427"             ,	   0x1180080940d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP428"             ,	   0x1180080940d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP429"             ,	   0x1180080940d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP430"             ,	   0x1180080940d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP431"             ,	   0x1180080940d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP432"             ,	   0x1180080940d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP433"             ,	   0x1180080940d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP434"             ,	   0x1180080940d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP435"             ,	   0x1180080940d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP436"             ,	   0x1180080940da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP437"             ,	   0x1180080940da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP438"             ,	   0x1180080940db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP439"             ,	   0x1180080940db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP440"             ,	   0x1180080940dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP441"             ,	   0x1180080940dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP442"             ,	   0x1180080940dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP443"             ,	   0x1180080940dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP444"             ,	   0x1180080940de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP445"             ,	   0x1180080940de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP446"             ,	   0x1180080940df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP447"             ,	   0x1180080940df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP448"             ,	   0x1180080940e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP449"             ,	   0x1180080940e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP450"             ,	   0x1180080940e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP451"             ,	   0x1180080940e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP452"             ,	   0x1180080940e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP453"             ,	   0x1180080940e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP454"             ,	   0x1180080940e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP455"             ,	   0x1180080940e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP456"             ,	   0x1180080940e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP457"             ,	   0x1180080940e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP458"             ,	   0x1180080940e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP459"             ,	   0x1180080940e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP460"             ,	   0x1180080940e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP461"             ,	   0x1180080940e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP462"             ,	   0x1180080940e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP463"             ,	   0x1180080940e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP464"             ,	   0x1180080940e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP465"             ,	   0x1180080940e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP466"             ,	   0x1180080940e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP467"             ,	   0x1180080940e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP468"             ,	   0x1180080940ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP469"             ,	   0x1180080940ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP470"             ,	   0x1180080940eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP471"             ,	   0x1180080940eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP472"             ,	   0x1180080940ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP473"             ,	   0x1180080940ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP474"             ,	   0x1180080940ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP475"             ,	   0x1180080940ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP476"             ,	   0x1180080940ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP477"             ,	   0x1180080940ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP478"             ,	   0x1180080940ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP479"             ,	   0x1180080940ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP480"             ,	   0x1180080940f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP481"             ,	   0x1180080940f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP482"             ,	   0x1180080940f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP483"             ,	   0x1180080940f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP484"             ,	   0x1180080940f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP485"             ,	   0x1180080940f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP486"             ,	   0x1180080940f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP487"             ,	   0x1180080940f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP488"             ,	   0x1180080940f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP489"             ,	   0x1180080940f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP490"             ,	   0x1180080940f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP491"             ,	   0x1180080940f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP492"             ,	   0x1180080940f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP493"             ,	   0x1180080940f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP494"             ,	   0x1180080940f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP495"             ,	   0x1180080940f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP496"             ,	   0x1180080940f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP497"             ,	   0x1180080940f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP498"             ,	   0x1180080940f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP499"             ,	   0x1180080940f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP500"             ,	   0x1180080940fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP501"             ,	   0x1180080940fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP502"             ,	   0x1180080940fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP503"             ,	   0x1180080940fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP504"             ,	   0x1180080940fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP505"             ,	   0x1180080940fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP506"             ,	   0x1180080940fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP507"             ,	   0x1180080940fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP508"             ,	   0x1180080940fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP509"             ,	   0x1180080940fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP510"             ,	   0x1180080940ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP511"             ,	   0x1180080940ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP512"             ,	   0x1180080941000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP513"             ,	   0x1180080941008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP514"             ,	   0x1180080941010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP515"             ,	   0x1180080941018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP516"             ,	   0x1180080941020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP517"             ,	   0x1180080941028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP518"             ,	   0x1180080941030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP519"             ,	   0x1180080941038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP520"             ,	   0x1180080941040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP521"             ,	   0x1180080941048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP522"             ,	   0x1180080941050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP523"             ,	   0x1180080941058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP524"             ,	   0x1180080941060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP525"             ,	   0x1180080941068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP526"             ,	   0x1180080941070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP527"             ,	   0x1180080941078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP528"             ,	   0x1180080941080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP529"             ,	   0x1180080941088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP530"             ,	   0x1180080941090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP531"             ,	   0x1180080941098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP532"             ,	   0x11800809410a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP533"             ,	   0x11800809410a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP534"             ,	   0x11800809410b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP535"             ,	   0x11800809410b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP536"             ,	   0x11800809410c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP537"             ,	   0x11800809410c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP538"             ,	   0x11800809410d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP539"             ,	   0x11800809410d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP540"             ,	   0x11800809410e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP541"             ,	   0x11800809410e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP542"             ,	   0x11800809410f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP543"             ,	   0x11800809410f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP544"             ,	   0x1180080941100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP545"             ,	   0x1180080941108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP546"             ,	   0x1180080941110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP547"             ,	   0x1180080941118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP548"             ,	   0x1180080941120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP549"             ,	   0x1180080941128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP550"             ,	   0x1180080941130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP551"             ,	   0x1180080941138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP552"             ,	   0x1180080941140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP553"             ,	   0x1180080941148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP554"             ,	   0x1180080941150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP555"             ,	   0x1180080941158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP556"             ,	   0x1180080941160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP557"             ,	   0x1180080941168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP558"             ,	   0x1180080941170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP559"             ,	   0x1180080941178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP560"             ,	   0x1180080941180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP561"             ,	   0x1180080941188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP562"             ,	   0x1180080941190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP563"             ,	   0x1180080941198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP564"             ,	   0x11800809411a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP565"             ,	   0x11800809411a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP566"             ,	   0x11800809411b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP567"             ,	   0x11800809411b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP568"             ,	   0x11800809411c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP569"             ,	   0x11800809411c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP570"             ,	   0x11800809411d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP571"             ,	   0x11800809411d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP572"             ,	   0x11800809411e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP573"             ,	   0x11800809411e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP574"             ,	   0x11800809411f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP575"             ,	   0x11800809411f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP576"             ,	   0x1180080941200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP577"             ,	   0x1180080941208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP578"             ,	   0x1180080941210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP579"             ,	   0x1180080941218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP580"             ,	   0x1180080941220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP581"             ,	   0x1180080941228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP582"             ,	   0x1180080941230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP583"             ,	   0x1180080941238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP584"             ,	   0x1180080941240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP585"             ,	   0x1180080941248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP586"             ,	   0x1180080941250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP587"             ,	   0x1180080941258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP588"             ,	   0x1180080941260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP589"             ,	   0x1180080941268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP590"             ,	   0x1180080941270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP591"             ,	   0x1180080941278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP592"             ,	   0x1180080941280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP593"             ,	   0x1180080941288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP594"             ,	   0x1180080941290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP595"             ,	   0x1180080941298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP596"             ,	   0x11800809412a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP597"             ,	   0x11800809412a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP598"             ,	   0x11800809412b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP599"             ,	   0x11800809412b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP600"             ,	   0x11800809412c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP601"             ,	   0x11800809412c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP602"             ,	   0x11800809412d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP603"             ,	   0x11800809412d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP604"             ,	   0x11800809412e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP605"             ,	   0x11800809412e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP606"             ,	   0x11800809412f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP607"             ,	   0x11800809412f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP608"             ,	   0x1180080941300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP609"             ,	   0x1180080941308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP610"             ,	   0x1180080941310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP611"             ,	   0x1180080941318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP612"             ,	   0x1180080941320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP613"             ,	   0x1180080941328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP614"             ,	   0x1180080941330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP615"             ,	   0x1180080941338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP616"             ,	   0x1180080941340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP617"             ,	   0x1180080941348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP618"             ,	   0x1180080941350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP619"             ,	   0x1180080941358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP620"             ,	   0x1180080941360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP621"             ,	   0x1180080941368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP622"             ,	   0x1180080941370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP623"             ,	   0x1180080941378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP624"             ,	   0x1180080941380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP625"             ,	   0x1180080941388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP626"             ,	   0x1180080941390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP627"             ,	   0x1180080941398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP628"             ,	   0x11800809413a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP629"             ,	   0x11800809413a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP630"             ,	   0x11800809413b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP631"             ,	   0x11800809413b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP632"             ,	   0x11800809413c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP633"             ,	   0x11800809413c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP634"             ,	   0x11800809413d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP635"             ,	   0x11800809413d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP636"             ,	   0x11800809413e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP637"             ,	   0x11800809413e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP638"             ,	   0x11800809413f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP639"             ,	   0x11800809413f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP640"             ,	   0x1180080941400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP641"             ,	   0x1180080941408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP642"             ,	   0x1180080941410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP643"             ,	   0x1180080941418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP644"             ,	   0x1180080941420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP645"             ,	   0x1180080941428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP646"             ,	   0x1180080941430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP647"             ,	   0x1180080941438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP648"             ,	   0x1180080941440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP649"             ,	   0x1180080941448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP650"             ,	   0x1180080941450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP651"             ,	   0x1180080941458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP652"             ,	   0x1180080941460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP653"             ,	   0x1180080941468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP654"             ,	   0x1180080941470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP655"             ,	   0x1180080941478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP656"             ,	   0x1180080941480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP657"             ,	   0x1180080941488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP658"             ,	   0x1180080941490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP659"             ,	   0x1180080941498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP660"             ,	   0x11800809414a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP661"             ,	   0x11800809414a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP662"             ,	   0x11800809414b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP663"             ,	   0x11800809414b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP664"             ,	   0x11800809414c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP665"             ,	   0x11800809414c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP666"             ,	   0x11800809414d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP667"             ,	   0x11800809414d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP668"             ,	   0x11800809414e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP669"             ,	   0x11800809414e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP670"             ,	   0x11800809414f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP671"             ,	   0x11800809414f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP672"             ,	   0x1180080941500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP673"             ,	   0x1180080941508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP674"             ,	   0x1180080941510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP675"             ,	   0x1180080941518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP676"             ,	   0x1180080941520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP677"             ,	   0x1180080941528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP678"             ,	   0x1180080941530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP679"             ,	   0x1180080941538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP680"             ,	   0x1180080941540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP681"             ,	   0x1180080941548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP682"             ,	   0x1180080941550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP683"             ,	   0x1180080941558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP684"             ,	   0x1180080941560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP685"             ,	   0x1180080941568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP686"             ,	   0x1180080941570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP687"             ,	   0x1180080941578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP688"             ,	   0x1180080941580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP689"             ,	   0x1180080941588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP690"             ,	   0x1180080941590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP691"             ,	   0x1180080941598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP692"             ,	   0x11800809415a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP693"             ,	   0x11800809415a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP694"             ,	   0x11800809415b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP695"             ,	   0x11800809415b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP696"             ,	   0x11800809415c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP697"             ,	   0x11800809415c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP698"             ,	   0x11800809415d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP699"             ,	   0x11800809415d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP700"             ,	   0x11800809415e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP701"             ,	   0x11800809415e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP702"             ,	   0x11800809415f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP703"             ,	   0x11800809415f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP704"             ,	   0x1180080941600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP705"             ,	   0x1180080941608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP706"             ,	   0x1180080941610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP707"             ,	   0x1180080941618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP708"             ,	   0x1180080941620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP709"             ,	   0x1180080941628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP710"             ,	   0x1180080941630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP711"             ,	   0x1180080941638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP712"             ,	   0x1180080941640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP713"             ,	   0x1180080941648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP714"             ,	   0x1180080941650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP715"             ,	   0x1180080941658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP716"             ,	   0x1180080941660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP717"             ,	   0x1180080941668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP718"             ,	   0x1180080941670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP719"             ,	   0x1180080941678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP720"             ,	   0x1180080941680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP721"             ,	   0x1180080941688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP722"             ,	   0x1180080941690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP723"             ,	   0x1180080941698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP724"             ,	   0x11800809416a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP725"             ,	   0x11800809416a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP726"             ,	   0x11800809416b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP727"             ,	   0x11800809416b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP728"             ,	   0x11800809416c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP729"             ,	   0x11800809416c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP730"             ,	   0x11800809416d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP731"             ,	   0x11800809416d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP732"             ,	   0x11800809416e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP733"             ,	   0x11800809416e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP734"             ,	   0x11800809416f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP735"             ,	   0x11800809416f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP736"             ,	   0x1180080941700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP737"             ,	   0x1180080941708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP738"             ,	   0x1180080941710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP739"             ,	   0x1180080941718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP740"             ,	   0x1180080941720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP741"             ,	   0x1180080941728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP742"             ,	   0x1180080941730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP743"             ,	   0x1180080941738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP744"             ,	   0x1180080941740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP745"             ,	   0x1180080941748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP746"             ,	   0x1180080941750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP747"             ,	   0x1180080941758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP748"             ,	   0x1180080941760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP749"             ,	   0x1180080941768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP750"             ,	   0x1180080941770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP751"             ,	   0x1180080941778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP752"             ,	   0x1180080941780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP753"             ,	   0x1180080941788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP754"             ,	   0x1180080941790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP755"             ,	   0x1180080941798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP756"             ,	   0x11800809417a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP757"             ,	   0x11800809417a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP758"             ,	   0x11800809417b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP759"             ,	   0x11800809417b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP760"             ,	   0x11800809417c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP761"             ,	   0x11800809417c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP762"             ,	   0x11800809417d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP763"             ,	   0x11800809417d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP764"             ,	   0x11800809417e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP765"             ,	   0x11800809417e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP766"             ,	   0x11800809417f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP767"             ,	   0x11800809417f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP768"             ,	   0x1180080941800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP769"             ,	   0x1180080941808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP770"             ,	   0x1180080941810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP771"             ,	   0x1180080941818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP772"             ,	   0x1180080941820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP773"             ,	   0x1180080941828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP774"             ,	   0x1180080941830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP775"             ,	   0x1180080941838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP776"             ,	   0x1180080941840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP777"             ,	   0x1180080941848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP778"             ,	   0x1180080941850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP779"             ,	   0x1180080941858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP780"             ,	   0x1180080941860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP781"             ,	   0x1180080941868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP782"             ,	   0x1180080941870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP783"             ,	   0x1180080941878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP784"             ,	   0x1180080941880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP785"             ,	   0x1180080941888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP786"             ,	   0x1180080941890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP787"             ,	   0x1180080941898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP788"             ,	   0x11800809418a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP789"             ,	   0x11800809418a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP790"             ,	   0x11800809418b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP791"             ,	   0x11800809418b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP792"             ,	   0x11800809418c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP793"             ,	   0x11800809418c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP794"             ,	   0x11800809418d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP795"             ,	   0x11800809418d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP796"             ,	   0x11800809418e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP797"             ,	   0x11800809418e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP798"             ,	   0x11800809418f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP799"             ,	   0x11800809418f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP800"             ,	   0x1180080941900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP801"             ,	   0x1180080941908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP802"             ,	   0x1180080941910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP803"             ,	   0x1180080941918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP804"             ,	   0x1180080941920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP805"             ,	   0x1180080941928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP806"             ,	   0x1180080941930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP807"             ,	   0x1180080941938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP808"             ,	   0x1180080941940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP809"             ,	   0x1180080941948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP810"             ,	   0x1180080941950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP811"             ,	   0x1180080941958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP812"             ,	   0x1180080941960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP813"             ,	   0x1180080941968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP814"             ,	   0x1180080941970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP815"             ,	   0x1180080941978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP816"             ,	   0x1180080941980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP817"             ,	   0x1180080941988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP818"             ,	   0x1180080941990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP819"             ,	   0x1180080941998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP820"             ,	   0x11800809419a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP821"             ,	   0x11800809419a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP822"             ,	   0x11800809419b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP823"             ,	   0x11800809419b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP824"             ,	   0x11800809419c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP825"             ,	   0x11800809419c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP826"             ,	   0x11800809419d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP827"             ,	   0x11800809419d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP828"             ,	   0x11800809419e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP829"             ,	   0x11800809419e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP830"             ,	   0x11800809419f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP831"             ,	   0x11800809419f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP832"             ,	   0x1180080941a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP833"             ,	   0x1180080941a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP834"             ,	   0x1180080941a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP835"             ,	   0x1180080941a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP836"             ,	   0x1180080941a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP837"             ,	   0x1180080941a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP838"             ,	   0x1180080941a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP839"             ,	   0x1180080941a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP840"             ,	   0x1180080941a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP841"             ,	   0x1180080941a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP842"             ,	   0x1180080941a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP843"             ,	   0x1180080941a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP844"             ,	   0x1180080941a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP845"             ,	   0x1180080941a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP846"             ,	   0x1180080941a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP847"             ,	   0x1180080941a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP848"             ,	   0x1180080941a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP849"             ,	   0x1180080941a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP850"             ,	   0x1180080941a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP851"             ,	   0x1180080941a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP852"             ,	   0x1180080941aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP853"             ,	   0x1180080941aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP854"             ,	   0x1180080941ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP855"             ,	   0x1180080941ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP856"             ,	   0x1180080941ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP857"             ,	   0x1180080941ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP858"             ,	   0x1180080941ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP859"             ,	   0x1180080941ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP860"             ,	   0x1180080941ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP861"             ,	   0x1180080941ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP862"             ,	   0x1180080941af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP863"             ,	   0x1180080941af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP864"             ,	   0x1180080941b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP865"             ,	   0x1180080941b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP866"             ,	   0x1180080941b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP867"             ,	   0x1180080941b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP868"             ,	   0x1180080941b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP869"             ,	   0x1180080941b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP870"             ,	   0x1180080941b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP871"             ,	   0x1180080941b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP872"             ,	   0x1180080941b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP873"             ,	   0x1180080941b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP874"             ,	   0x1180080941b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP875"             ,	   0x1180080941b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP876"             ,	   0x1180080941b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP877"             ,	   0x1180080941b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP878"             ,	   0x1180080941b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP879"             ,	   0x1180080941b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP880"             ,	   0x1180080941b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP881"             ,	   0x1180080941b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP882"             ,	   0x1180080941b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP883"             ,	   0x1180080941b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP884"             ,	   0x1180080941ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP885"             ,	   0x1180080941ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP886"             ,	   0x1180080941bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP887"             ,	   0x1180080941bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP888"             ,	   0x1180080941bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP889"             ,	   0x1180080941bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP890"             ,	   0x1180080941bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP891"             ,	   0x1180080941bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP892"             ,	   0x1180080941be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP893"             ,	   0x1180080941be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP894"             ,	   0x1180080941bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP895"             ,	   0x1180080941bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP896"             ,	   0x1180080941c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP897"             ,	   0x1180080941c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP898"             ,	   0x1180080941c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP899"             ,	   0x1180080941c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP900"             ,	   0x1180080941c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP901"             ,	   0x1180080941c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP902"             ,	   0x1180080941c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP903"             ,	   0x1180080941c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP904"             ,	   0x1180080941c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP905"             ,	   0x1180080941c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP906"             ,	   0x1180080941c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP907"             ,	   0x1180080941c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP908"             ,	   0x1180080941c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP909"             ,	   0x1180080941c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP910"             ,	   0x1180080941c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP911"             ,	   0x1180080941c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP912"             ,	   0x1180080941c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP913"             ,	   0x1180080941c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP914"             ,	   0x1180080941c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP915"             ,	   0x1180080941c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP916"             ,	   0x1180080941ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP917"             ,	   0x1180080941ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP918"             ,	   0x1180080941cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP919"             ,	   0x1180080941cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP920"             ,	   0x1180080941cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP921"             ,	   0x1180080941cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP922"             ,	   0x1180080941cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP923"             ,	   0x1180080941cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP924"             ,	   0x1180080941ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP925"             ,	   0x1180080941ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP926"             ,	   0x1180080941cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP927"             ,	   0x1180080941cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP928"             ,	   0x1180080941d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP929"             ,	   0x1180080941d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP930"             ,	   0x1180080941d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP931"             ,	   0x1180080941d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP932"             ,	   0x1180080941d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP933"             ,	   0x1180080941d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP934"             ,	   0x1180080941d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP935"             ,	   0x1180080941d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP936"             ,	   0x1180080941d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP937"             ,	   0x1180080941d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP938"             ,	   0x1180080941d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP939"             ,	   0x1180080941d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP940"             ,	   0x1180080941d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP941"             ,	   0x1180080941d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP942"             ,	   0x1180080941d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP943"             ,	   0x1180080941d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP944"             ,	   0x1180080941d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP945"             ,	   0x1180080941d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP946"             ,	   0x1180080941d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP947"             ,	   0x1180080941d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP948"             ,	   0x1180080941da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP949"             ,	   0x1180080941da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP950"             ,	   0x1180080941db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP951"             ,	   0x1180080941db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP952"             ,	   0x1180080941dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP953"             ,	   0x1180080941dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP954"             ,	   0x1180080941dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP955"             ,	   0x1180080941dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP956"             ,	   0x1180080941de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP957"             ,	   0x1180080941de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP958"             ,	   0x1180080941df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP959"             ,	   0x1180080941df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP960"             ,	   0x1180080941e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP961"             ,	   0x1180080941e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP962"             ,	   0x1180080941e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP963"             ,	   0x1180080941e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP964"             ,	   0x1180080941e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP965"             ,	   0x1180080941e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP966"             ,	   0x1180080941e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP967"             ,	   0x1180080941e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP968"             ,	   0x1180080941e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP969"             ,	   0x1180080941e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP970"             ,	   0x1180080941e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP971"             ,	   0x1180080941e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP972"             ,	   0x1180080941e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP973"             ,	   0x1180080941e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP974"             ,	   0x1180080941e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP975"             ,	   0x1180080941e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP976"             ,	   0x1180080941e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP977"             ,	   0x1180080941e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP978"             ,	   0x1180080941e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP979"             ,	   0x1180080941e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP980"             ,	   0x1180080941ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP981"             ,	   0x1180080941ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP982"             ,	   0x1180080941eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP983"             ,	   0x1180080941eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP984"             ,	   0x1180080941ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP985"             ,	   0x1180080941ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP986"             ,	   0x1180080941ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP987"             ,	   0x1180080941ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP988"             ,	   0x1180080941ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP989"             ,	   0x1180080941ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP990"             ,	   0x1180080941ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP991"             ,	   0x1180080941ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP992"             ,	   0x1180080941f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP993"             ,	   0x1180080941f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP994"             ,	   0x1180080941f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP995"             ,	   0x1180080941f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP996"             ,	   0x1180080941f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP997"             ,	   0x1180080941f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP998"             ,	   0x1180080941f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP999"             ,	   0x1180080941f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1000"            ,	   0x1180080941f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1001"            ,	   0x1180080941f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1002"            ,	   0x1180080941f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1003"            ,	   0x1180080941f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1004"            ,	   0x1180080941f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1005"            ,	   0x1180080941f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1006"            ,	   0x1180080941f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1007"            ,	   0x1180080941f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1008"            ,	   0x1180080941f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1009"            ,	   0x1180080941f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1010"            ,	   0x1180080941f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1011"            ,	   0x1180080941f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1012"            ,	   0x1180080941fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1013"            ,	   0x1180080941fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1014"            ,	   0x1180080941fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1015"            ,	   0x1180080941fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1016"            ,	   0x1180080941fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1017"            ,	   0x1180080941fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1018"            ,	   0x1180080941fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1019"            ,	   0x1180080941fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1020"            ,	   0x1180080941fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1021"            ,	   0x1180080941fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1022"            ,	   0x1180080941ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1023"            ,	   0x1180080941ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16128"           ,	   0x118008095f800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16129"           ,	   0x118008095f808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16130"           ,	   0x118008095f810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16131"           ,	   0x118008095f818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16132"           ,	   0x118008095f820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16133"           ,	   0x118008095f828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16134"           ,	   0x118008095f830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16135"           ,	   0x118008095f838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16136"           ,	   0x118008095f840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16137"           ,	   0x118008095f848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16138"           ,	   0x118008095f850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16139"           ,	   0x118008095f858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16140"           ,	   0x118008095f860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16141"           ,	   0x118008095f868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16142"           ,	   0x118008095f870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16143"           ,	   0x118008095f878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16144"           ,	   0x118008095f880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16145"           ,	   0x118008095f888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16146"           ,	   0x118008095f890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16147"           ,	   0x118008095f898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16148"           ,	   0x118008095f8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16149"           ,	   0x118008095f8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16150"           ,	   0x118008095f8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16151"           ,	   0x118008095f8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16152"           ,	   0x118008095f8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16153"           ,	   0x118008095f8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16154"           ,	   0x118008095f8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16155"           ,	   0x118008095f8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16156"           ,	   0x118008095f8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16157"           ,	   0x118008095f8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16158"           ,	   0x118008095f8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16159"           ,	   0x118008095f8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16160"           ,	   0x118008095f900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16161"           ,	   0x118008095f908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16162"           ,	   0x118008095f910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16163"           ,	   0x118008095f918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16164"           ,	   0x118008095f920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16165"           ,	   0x118008095f928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16166"           ,	   0x118008095f930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16167"           ,	   0x118008095f938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16168"           ,	   0x118008095f940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16169"           ,	   0x118008095f948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16170"           ,	   0x118008095f950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16171"           ,	   0x118008095f958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16172"           ,	   0x118008095f960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16173"           ,	   0x118008095f968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16174"           ,	   0x118008095f970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16175"           ,	   0x118008095f978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16176"           ,	   0x118008095f980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16177"           ,	   0x118008095f988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16178"           ,	   0x118008095f990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16179"           ,	   0x118008095f998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16180"           ,	   0x118008095f9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16181"           ,	   0x118008095f9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16182"           ,	   0x118008095f9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16183"           ,	   0x118008095f9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16184"           ,	   0x118008095f9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16185"           ,	   0x118008095f9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16186"           ,	   0x118008095f9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16187"           ,	   0x118008095f9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16188"           ,	   0x118008095f9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16189"           ,	   0x118008095f9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16190"           ,	   0x118008095f9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16191"           ,	   0x118008095f9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16192"           ,	   0x118008095fa00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16193"           ,	   0x118008095fa08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16194"           ,	   0x118008095fa10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16195"           ,	   0x118008095fa18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16196"           ,	   0x118008095fa20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16197"           ,	   0x118008095fa28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16198"           ,	   0x118008095fa30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16199"           ,	   0x118008095fa38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16200"           ,	   0x118008095fa40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16201"           ,	   0x118008095fa48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16202"           ,	   0x118008095fa50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16203"           ,	   0x118008095fa58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16204"           ,	   0x118008095fa60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16205"           ,	   0x118008095fa68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16206"           ,	   0x118008095fa70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16207"           ,	   0x118008095fa78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16208"           ,	   0x118008095fa80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16209"           ,	   0x118008095fa88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16210"           ,	   0x118008095fa90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16211"           ,	   0x118008095fa98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16212"           ,	   0x118008095faa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16213"           ,	   0x118008095faa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16214"           ,	   0x118008095fab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16215"           ,	   0x118008095fab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16216"           ,	   0x118008095fac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16217"           ,	   0x118008095fac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16218"           ,	   0x118008095fad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16219"           ,	   0x118008095fad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16220"           ,	   0x118008095fae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16221"           ,	   0x118008095fae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16222"           ,	   0x118008095faf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16223"           ,	   0x118008095faf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16224"           ,	   0x118008095fb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16225"           ,	   0x118008095fb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16226"           ,	   0x118008095fb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16227"           ,	   0x118008095fb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16228"           ,	   0x118008095fb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16229"           ,	   0x118008095fb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16230"           ,	   0x118008095fb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16231"           ,	   0x118008095fb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16232"           ,	   0x118008095fb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16233"           ,	   0x118008095fb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16234"           ,	   0x118008095fb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16235"           ,	   0x118008095fb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16236"           ,	   0x118008095fb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16237"           ,	   0x118008095fb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16238"           ,	   0x118008095fb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16239"           ,	   0x118008095fb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16240"           ,	   0x118008095fb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16241"           ,	   0x118008095fb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16242"           ,	   0x118008095fb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16243"           ,	   0x118008095fb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16244"           ,	   0x118008095fba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16245"           ,	   0x118008095fba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16246"           ,	   0x118008095fbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16247"           ,	   0x118008095fbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16248"           ,	   0x118008095fbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16249"           ,	   0x118008095fbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16250"           ,	   0x118008095fbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16251"           ,	   0x118008095fbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16252"           ,	   0x118008095fbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16253"           ,	   0x118008095fbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16254"           ,	   0x118008095fbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16255"           ,	   0x118008095fbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16256"           ,	   0x118008095fc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16257"           ,	   0x118008095fc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16258"           ,	   0x118008095fc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16259"           ,	   0x118008095fc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16260"           ,	   0x118008095fc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16261"           ,	   0x118008095fc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16262"           ,	   0x118008095fc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16263"           ,	   0x118008095fc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16264"           ,	   0x118008095fc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16265"           ,	   0x118008095fc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16266"           ,	   0x118008095fc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16267"           ,	   0x118008095fc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16268"           ,	   0x118008095fc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16269"           ,	   0x118008095fc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16270"           ,	   0x118008095fc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16271"           ,	   0x118008095fc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16272"           ,	   0x118008095fc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16273"           ,	   0x118008095fc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16274"           ,	   0x118008095fc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16275"           ,	   0x118008095fc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16276"           ,	   0x118008095fca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16277"           ,	   0x118008095fca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16278"           ,	   0x118008095fcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16279"           ,	   0x118008095fcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16280"           ,	   0x118008095fcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16281"           ,	   0x118008095fcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16282"           ,	   0x118008095fcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16283"           ,	   0x118008095fcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16284"           ,	   0x118008095fce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16285"           ,	   0x118008095fce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16286"           ,	   0x118008095fcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16287"           ,	   0x118008095fcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16288"           ,	   0x118008095fd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16289"           ,	   0x118008095fd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16290"           ,	   0x118008095fd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16291"           ,	   0x118008095fd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16292"           ,	   0x118008095fd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16293"           ,	   0x118008095fd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16294"           ,	   0x118008095fd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16295"           ,	   0x118008095fd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16296"           ,	   0x118008095fd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16297"           ,	   0x118008095fd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16298"           ,	   0x118008095fd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16299"           ,	   0x118008095fd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16300"           ,	   0x118008095fd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16301"           ,	   0x118008095fd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16302"           ,	   0x118008095fd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16303"           ,	   0x118008095fd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16304"           ,	   0x118008095fd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16305"           ,	   0x118008095fd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16306"           ,	   0x118008095fd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16307"           ,	   0x118008095fd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16308"           ,	   0x118008095fda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16309"           ,	   0x118008095fda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16310"           ,	   0x118008095fdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16311"           ,	   0x118008095fdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16312"           ,	   0x118008095fdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16313"           ,	   0x118008095fdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16314"           ,	   0x118008095fdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16315"           ,	   0x118008095fdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16316"           ,	   0x118008095fde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16317"           ,	   0x118008095fde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16318"           ,	   0x118008095fdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16319"           ,	   0x118008095fdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16320"           ,	   0x118008095fe00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16321"           ,	   0x118008095fe08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16322"           ,	   0x118008095fe10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16323"           ,	   0x118008095fe18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16324"           ,	   0x118008095fe20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16325"           ,	   0x118008095fe28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16326"           ,	   0x118008095fe30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16327"           ,	   0x118008095fe38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16328"           ,	   0x118008095fe40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16329"           ,	   0x118008095fe48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16330"           ,	   0x118008095fe50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16331"           ,	   0x118008095fe58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16332"           ,	   0x118008095fe60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16333"           ,	   0x118008095fe68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16334"           ,	   0x118008095fe70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16335"           ,	   0x118008095fe78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16336"           ,	   0x118008095fe80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16337"           ,	   0x118008095fe88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16338"           ,	   0x118008095fe90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16339"           ,	   0x118008095fe98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16340"           ,	   0x118008095fea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16341"           ,	   0x118008095fea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16342"           ,	   0x118008095feb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16343"           ,	   0x118008095feb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16344"           ,	   0x118008095fec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16345"           ,	   0x118008095fec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16346"           ,	   0x118008095fed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16347"           ,	   0x118008095fed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16348"           ,	   0x118008095fee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16349"           ,	   0x118008095fee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16350"           ,	   0x118008095fef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16351"           ,	   0x118008095fef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16352"           ,	   0x118008095ff00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16353"           ,	   0x118008095ff08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16354"           ,	   0x118008095ff10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16355"           ,	   0x118008095ff18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16356"           ,	   0x118008095ff20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16357"           ,	   0x118008095ff28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16358"           ,	   0x118008095ff30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16359"           ,	   0x118008095ff38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16360"           ,	   0x118008095ff40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16361"           ,	   0x118008095ff48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16362"           ,	   0x118008095ff50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16363"           ,	   0x118008095ff58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16364"           ,	   0x118008095ff60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16365"           ,	   0x118008095ff68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16366"           ,	   0x118008095ff70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16367"           ,	   0x118008095ff78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16368"           ,	   0x118008095ff80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16369"           ,	   0x118008095ff88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16370"           ,	   0x118008095ff90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16371"           ,	   0x118008095ff98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16372"           ,	   0x118008095ffa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16373"           ,	   0x118008095ffa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16374"           ,	   0x118008095ffb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16375"           ,	   0x118008095ffb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16376"           ,	   0x118008095ffc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16377"           ,	   0x118008095ffc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16378"           ,	   0x118008095ffd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16379"           ,	   0x118008095ffd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16380"           ,	   0x118008095ffe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16381"           ,	   0x118008095ffe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16382"           ,	   0x118008095fff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16383"           ,	   0x118008095fff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_CTL"                     ,	   0x1180080800000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"L2C_DUT_MAP0"                ,	   0x1180080e00000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1"                ,	   0x1180080e00008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP2"                ,	   0x1180080e00010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP3"                ,	   0x1180080e00018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP4"                ,	   0x1180080e00020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP5"                ,	   0x1180080e00028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP6"                ,	   0x1180080e00030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP7"                ,	   0x1180080e00038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP8"                ,	   0x1180080e00040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP9"                ,	   0x1180080e00048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP10"               ,	   0x1180080e00050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP11"               ,	   0x1180080e00058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP12"               ,	   0x1180080e00060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP13"               ,	   0x1180080e00068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP14"               ,	   0x1180080e00070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP15"               ,	   0x1180080e00078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP16"               ,	   0x1180080e00080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP17"               ,	   0x1180080e00088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP18"               ,	   0x1180080e00090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP19"               ,	   0x1180080e00098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP20"               ,	   0x1180080e000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP21"               ,	   0x1180080e000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP22"               ,	   0x1180080e000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP23"               ,	   0x1180080e000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP24"               ,	   0x1180080e000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP25"               ,	   0x1180080e000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP26"               ,	   0x1180080e000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP27"               ,	   0x1180080e000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP28"               ,	   0x1180080e000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP29"               ,	   0x1180080e000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP30"               ,	   0x1180080e000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP31"               ,	   0x1180080e000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP32"               ,	   0x1180080e00100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP33"               ,	   0x1180080e00108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP34"               ,	   0x1180080e00110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP35"               ,	   0x1180080e00118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP36"               ,	   0x1180080e00120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP37"               ,	   0x1180080e00128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP38"               ,	   0x1180080e00130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP39"               ,	   0x1180080e00138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP40"               ,	   0x1180080e00140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP41"               ,	   0x1180080e00148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP42"               ,	   0x1180080e00150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP43"               ,	   0x1180080e00158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP44"               ,	   0x1180080e00160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP45"               ,	   0x1180080e00168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP46"               ,	   0x1180080e00170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP47"               ,	   0x1180080e00178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP48"               ,	   0x1180080e00180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP49"               ,	   0x1180080e00188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP50"               ,	   0x1180080e00190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP51"               ,	   0x1180080e00198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP52"               ,	   0x1180080e001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP53"               ,	   0x1180080e001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP54"               ,	   0x1180080e001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP55"               ,	   0x1180080e001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP56"               ,	   0x1180080e001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP57"               ,	   0x1180080e001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP58"               ,	   0x1180080e001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP59"               ,	   0x1180080e001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP60"               ,	   0x1180080e001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP61"               ,	   0x1180080e001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP62"               ,	   0x1180080e001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP63"               ,	   0x1180080e001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP64"               ,	   0x1180080e00200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP65"               ,	   0x1180080e00208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP66"               ,	   0x1180080e00210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP67"               ,	   0x1180080e00218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP68"               ,	   0x1180080e00220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP69"               ,	   0x1180080e00228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP70"               ,	   0x1180080e00230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP71"               ,	   0x1180080e00238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP72"               ,	   0x1180080e00240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP73"               ,	   0x1180080e00248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP74"               ,	   0x1180080e00250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP75"               ,	   0x1180080e00258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP76"               ,	   0x1180080e00260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP77"               ,	   0x1180080e00268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP78"               ,	   0x1180080e00270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP79"               ,	   0x1180080e00278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP80"               ,	   0x1180080e00280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP81"               ,	   0x1180080e00288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP82"               ,	   0x1180080e00290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP83"               ,	   0x1180080e00298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP84"               ,	   0x1180080e002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP85"               ,	   0x1180080e002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP86"               ,	   0x1180080e002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP87"               ,	   0x1180080e002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP88"               ,	   0x1180080e002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP89"               ,	   0x1180080e002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP90"               ,	   0x1180080e002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP91"               ,	   0x1180080e002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP92"               ,	   0x1180080e002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP93"               ,	   0x1180080e002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP94"               ,	   0x1180080e002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP95"               ,	   0x1180080e002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP96"               ,	   0x1180080e00300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP97"               ,	   0x1180080e00308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP98"               ,	   0x1180080e00310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP99"               ,	   0x1180080e00318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP100"              ,	   0x1180080e00320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP101"              ,	   0x1180080e00328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP102"              ,	   0x1180080e00330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP103"              ,	   0x1180080e00338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP104"              ,	   0x1180080e00340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP105"              ,	   0x1180080e00348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP106"              ,	   0x1180080e00350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP107"              ,	   0x1180080e00358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP108"              ,	   0x1180080e00360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP109"              ,	   0x1180080e00368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP110"              ,	   0x1180080e00370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP111"              ,	   0x1180080e00378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP112"              ,	   0x1180080e00380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP113"              ,	   0x1180080e00388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP114"              ,	   0x1180080e00390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP115"              ,	   0x1180080e00398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP116"              ,	   0x1180080e003a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP117"              ,	   0x1180080e003a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP118"              ,	   0x1180080e003b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP119"              ,	   0x1180080e003b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP120"              ,	   0x1180080e003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP121"              ,	   0x1180080e003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP122"              ,	   0x1180080e003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP123"              ,	   0x1180080e003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP124"              ,	   0x1180080e003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP125"              ,	   0x1180080e003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP126"              ,	   0x1180080e003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP127"              ,	   0x1180080e003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP128"              ,	   0x1180080e00400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP129"              ,	   0x1180080e00408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP130"              ,	   0x1180080e00410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP131"              ,	   0x1180080e00418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP132"              ,	   0x1180080e00420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP133"              ,	   0x1180080e00428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP134"              ,	   0x1180080e00430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP135"              ,	   0x1180080e00438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP136"              ,	   0x1180080e00440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP137"              ,	   0x1180080e00448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP138"              ,	   0x1180080e00450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP139"              ,	   0x1180080e00458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP140"              ,	   0x1180080e00460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP141"              ,	   0x1180080e00468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP142"              ,	   0x1180080e00470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP143"              ,	   0x1180080e00478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP144"              ,	   0x1180080e00480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP145"              ,	   0x1180080e00488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP146"              ,	   0x1180080e00490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP147"              ,	   0x1180080e00498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP148"              ,	   0x1180080e004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP149"              ,	   0x1180080e004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP150"              ,	   0x1180080e004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP151"              ,	   0x1180080e004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP152"              ,	   0x1180080e004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP153"              ,	   0x1180080e004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP154"              ,	   0x1180080e004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP155"              ,	   0x1180080e004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP156"              ,	   0x1180080e004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP157"              ,	   0x1180080e004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP158"              ,	   0x1180080e004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP159"              ,	   0x1180080e004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP160"              ,	   0x1180080e00500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP161"              ,	   0x1180080e00508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP162"              ,	   0x1180080e00510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP163"              ,	   0x1180080e00518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP164"              ,	   0x1180080e00520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP165"              ,	   0x1180080e00528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP166"              ,	   0x1180080e00530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP167"              ,	   0x1180080e00538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP168"              ,	   0x1180080e00540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP169"              ,	   0x1180080e00548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP170"              ,	   0x1180080e00550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP171"              ,	   0x1180080e00558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP172"              ,	   0x1180080e00560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP173"              ,	   0x1180080e00568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP174"              ,	   0x1180080e00570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP175"              ,	   0x1180080e00578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP176"              ,	   0x1180080e00580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP177"              ,	   0x1180080e00588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP178"              ,	   0x1180080e00590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP179"              ,	   0x1180080e00598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP180"              ,	   0x1180080e005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP181"              ,	   0x1180080e005a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP182"              ,	   0x1180080e005b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP183"              ,	   0x1180080e005b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP184"              ,	   0x1180080e005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP185"              ,	   0x1180080e005c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP186"              ,	   0x1180080e005d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP187"              ,	   0x1180080e005d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP188"              ,	   0x1180080e005e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP189"              ,	   0x1180080e005e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP190"              ,	   0x1180080e005f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP191"              ,	   0x1180080e005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP192"              ,	   0x1180080e00600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP193"              ,	   0x1180080e00608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP194"              ,	   0x1180080e00610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP195"              ,	   0x1180080e00618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP196"              ,	   0x1180080e00620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP197"              ,	   0x1180080e00628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP198"              ,	   0x1180080e00630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP199"              ,	   0x1180080e00638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP200"              ,	   0x1180080e00640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP201"              ,	   0x1180080e00648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP202"              ,	   0x1180080e00650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP203"              ,	   0x1180080e00658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP204"              ,	   0x1180080e00660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP205"              ,	   0x1180080e00668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP206"              ,	   0x1180080e00670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP207"              ,	   0x1180080e00678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP208"              ,	   0x1180080e00680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP209"              ,	   0x1180080e00688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP210"              ,	   0x1180080e00690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP211"              ,	   0x1180080e00698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP212"              ,	   0x1180080e006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP213"              ,	   0x1180080e006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP214"              ,	   0x1180080e006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP215"              ,	   0x1180080e006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP216"              ,	   0x1180080e006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP217"              ,	   0x1180080e006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP218"              ,	   0x1180080e006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP219"              ,	   0x1180080e006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP220"              ,	   0x1180080e006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP221"              ,	   0x1180080e006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP222"              ,	   0x1180080e006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP223"              ,	   0x1180080e006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP224"              ,	   0x1180080e00700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP225"              ,	   0x1180080e00708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP226"              ,	   0x1180080e00710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP227"              ,	   0x1180080e00718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP228"              ,	   0x1180080e00720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP229"              ,	   0x1180080e00728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP230"              ,	   0x1180080e00730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP231"              ,	   0x1180080e00738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP232"              ,	   0x1180080e00740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP233"              ,	   0x1180080e00748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP234"              ,	   0x1180080e00750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP235"              ,	   0x1180080e00758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP236"              ,	   0x1180080e00760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP237"              ,	   0x1180080e00768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP238"              ,	   0x1180080e00770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP239"              ,	   0x1180080e00778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP240"              ,	   0x1180080e00780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP241"              ,	   0x1180080e00788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP242"              ,	   0x1180080e00790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP243"              ,	   0x1180080e00798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP244"              ,	   0x1180080e007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP245"              ,	   0x1180080e007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP246"              ,	   0x1180080e007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP247"              ,	   0x1180080e007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP248"              ,	   0x1180080e007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP249"              ,	   0x1180080e007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP250"              ,	   0x1180080e007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP251"              ,	   0x1180080e007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP252"              ,	   0x1180080e007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP253"              ,	   0x1180080e007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP254"              ,	   0x1180080e007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP255"              ,	   0x1180080e007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP256"              ,	   0x1180080e00800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP257"              ,	   0x1180080e00808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP258"              ,	   0x1180080e00810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP259"              ,	   0x1180080e00818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP260"              ,	   0x1180080e00820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP261"              ,	   0x1180080e00828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP262"              ,	   0x1180080e00830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP263"              ,	   0x1180080e00838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP264"              ,	   0x1180080e00840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP265"              ,	   0x1180080e00848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP266"              ,	   0x1180080e00850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP267"              ,	   0x1180080e00858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP268"              ,	   0x1180080e00860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP269"              ,	   0x1180080e00868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP270"              ,	   0x1180080e00870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP271"              ,	   0x1180080e00878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP272"              ,	   0x1180080e00880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP273"              ,	   0x1180080e00888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP274"              ,	   0x1180080e00890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP275"              ,	   0x1180080e00898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP276"              ,	   0x1180080e008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP277"              ,	   0x1180080e008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP278"              ,	   0x1180080e008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP279"              ,	   0x1180080e008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP280"              ,	   0x1180080e008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP281"              ,	   0x1180080e008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP282"              ,	   0x1180080e008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP283"              ,	   0x1180080e008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP284"              ,	   0x1180080e008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP285"              ,	   0x1180080e008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP286"              ,	   0x1180080e008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP287"              ,	   0x1180080e008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP288"              ,	   0x1180080e00900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP289"              ,	   0x1180080e00908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP290"              ,	   0x1180080e00910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP291"              ,	   0x1180080e00918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP292"              ,	   0x1180080e00920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP293"              ,	   0x1180080e00928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP294"              ,	   0x1180080e00930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP295"              ,	   0x1180080e00938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP296"              ,	   0x1180080e00940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP297"              ,	   0x1180080e00948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP298"              ,	   0x1180080e00950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP299"              ,	   0x1180080e00958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP300"              ,	   0x1180080e00960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP301"              ,	   0x1180080e00968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP302"              ,	   0x1180080e00970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP303"              ,	   0x1180080e00978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP304"              ,	   0x1180080e00980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP305"              ,	   0x1180080e00988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP306"              ,	   0x1180080e00990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP307"              ,	   0x1180080e00998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP308"              ,	   0x1180080e009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP309"              ,	   0x1180080e009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP310"              ,	   0x1180080e009b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP311"              ,	   0x1180080e009b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP312"              ,	   0x1180080e009c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP313"              ,	   0x1180080e009c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP314"              ,	   0x1180080e009d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP315"              ,	   0x1180080e009d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP316"              ,	   0x1180080e009e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP317"              ,	   0x1180080e009e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP318"              ,	   0x1180080e009f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP319"              ,	   0x1180080e009f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP320"              ,	   0x1180080e00a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP321"              ,	   0x1180080e00a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP322"              ,	   0x1180080e00a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP323"              ,	   0x1180080e00a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP324"              ,	   0x1180080e00a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP325"              ,	   0x1180080e00a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP326"              ,	   0x1180080e00a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP327"              ,	   0x1180080e00a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP328"              ,	   0x1180080e00a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP329"              ,	   0x1180080e00a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP330"              ,	   0x1180080e00a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP331"              ,	   0x1180080e00a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP332"              ,	   0x1180080e00a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP333"              ,	   0x1180080e00a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP334"              ,	   0x1180080e00a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP335"              ,	   0x1180080e00a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP336"              ,	   0x1180080e00a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP337"              ,	   0x1180080e00a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP338"              ,	   0x1180080e00a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP339"              ,	   0x1180080e00a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP340"              ,	   0x1180080e00aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP341"              ,	   0x1180080e00aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP342"              ,	   0x1180080e00ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP343"              ,	   0x1180080e00ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP344"              ,	   0x1180080e00ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP345"              ,	   0x1180080e00ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP346"              ,	   0x1180080e00ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP347"              ,	   0x1180080e00ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP348"              ,	   0x1180080e00ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP349"              ,	   0x1180080e00ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP350"              ,	   0x1180080e00af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP351"              ,	   0x1180080e00af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP352"              ,	   0x1180080e00b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP353"              ,	   0x1180080e00b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP354"              ,	   0x1180080e00b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP355"              ,	   0x1180080e00b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP356"              ,	   0x1180080e00b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP357"              ,	   0x1180080e00b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP358"              ,	   0x1180080e00b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP359"              ,	   0x1180080e00b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP360"              ,	   0x1180080e00b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP361"              ,	   0x1180080e00b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP362"              ,	   0x1180080e00b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP363"              ,	   0x1180080e00b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP364"              ,	   0x1180080e00b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP365"              ,	   0x1180080e00b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP366"              ,	   0x1180080e00b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP367"              ,	   0x1180080e00b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP368"              ,	   0x1180080e00b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP369"              ,	   0x1180080e00b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP370"              ,	   0x1180080e00b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP371"              ,	   0x1180080e00b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP372"              ,	   0x1180080e00ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP373"              ,	   0x1180080e00ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP374"              ,	   0x1180080e00bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP375"              ,	   0x1180080e00bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP376"              ,	   0x1180080e00bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP377"              ,	   0x1180080e00bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP378"              ,	   0x1180080e00bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP379"              ,	   0x1180080e00bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP380"              ,	   0x1180080e00be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP381"              ,	   0x1180080e00be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP382"              ,	   0x1180080e00bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP383"              ,	   0x1180080e00bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP384"              ,	   0x1180080e00c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP385"              ,	   0x1180080e00c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP386"              ,	   0x1180080e00c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP387"              ,	   0x1180080e00c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP388"              ,	   0x1180080e00c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP389"              ,	   0x1180080e00c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP390"              ,	   0x1180080e00c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP391"              ,	   0x1180080e00c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP392"              ,	   0x1180080e00c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP393"              ,	   0x1180080e00c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP394"              ,	   0x1180080e00c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP395"              ,	   0x1180080e00c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP396"              ,	   0x1180080e00c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP397"              ,	   0x1180080e00c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP398"              ,	   0x1180080e00c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP399"              ,	   0x1180080e00c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP400"              ,	   0x1180080e00c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP401"              ,	   0x1180080e00c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP402"              ,	   0x1180080e00c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP403"              ,	   0x1180080e00c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP404"              ,	   0x1180080e00ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP405"              ,	   0x1180080e00ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP406"              ,	   0x1180080e00cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP407"              ,	   0x1180080e00cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP408"              ,	   0x1180080e00cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP409"              ,	   0x1180080e00cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP410"              ,	   0x1180080e00cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP411"              ,	   0x1180080e00cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP412"              ,	   0x1180080e00ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP413"              ,	   0x1180080e00ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP414"              ,	   0x1180080e00cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP415"              ,	   0x1180080e00cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP416"              ,	   0x1180080e00d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP417"              ,	   0x1180080e00d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP418"              ,	   0x1180080e00d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP419"              ,	   0x1180080e00d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP420"              ,	   0x1180080e00d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP421"              ,	   0x1180080e00d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP422"              ,	   0x1180080e00d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP423"              ,	   0x1180080e00d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP424"              ,	   0x1180080e00d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP425"              ,	   0x1180080e00d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP426"              ,	   0x1180080e00d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP427"              ,	   0x1180080e00d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP428"              ,	   0x1180080e00d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP429"              ,	   0x1180080e00d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP430"              ,	   0x1180080e00d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP431"              ,	   0x1180080e00d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP432"              ,	   0x1180080e00d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP433"              ,	   0x1180080e00d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP434"              ,	   0x1180080e00d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP435"              ,	   0x1180080e00d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP436"              ,	   0x1180080e00da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP437"              ,	   0x1180080e00da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP438"              ,	   0x1180080e00db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP439"              ,	   0x1180080e00db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP440"              ,	   0x1180080e00dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP441"              ,	   0x1180080e00dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP442"              ,	   0x1180080e00dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP443"              ,	   0x1180080e00dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP444"              ,	   0x1180080e00de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP445"              ,	   0x1180080e00de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP446"              ,	   0x1180080e00df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP447"              ,	   0x1180080e00df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP448"              ,	   0x1180080e00e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP449"              ,	   0x1180080e00e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP450"              ,	   0x1180080e00e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP451"              ,	   0x1180080e00e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP452"              ,	   0x1180080e00e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP453"              ,	   0x1180080e00e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP454"              ,	   0x1180080e00e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP455"              ,	   0x1180080e00e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP456"              ,	   0x1180080e00e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP457"              ,	   0x1180080e00e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP458"              ,	   0x1180080e00e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP459"              ,	   0x1180080e00e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP460"              ,	   0x1180080e00e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP461"              ,	   0x1180080e00e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP462"              ,	   0x1180080e00e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP463"              ,	   0x1180080e00e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP464"              ,	   0x1180080e00e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP465"              ,	   0x1180080e00e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP466"              ,	   0x1180080e00e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP467"              ,	   0x1180080e00e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP468"              ,	   0x1180080e00ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP469"              ,	   0x1180080e00ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP470"              ,	   0x1180080e00eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP471"              ,	   0x1180080e00eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP472"              ,	   0x1180080e00ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP473"              ,	   0x1180080e00ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP474"              ,	   0x1180080e00ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP475"              ,	   0x1180080e00ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP476"              ,	   0x1180080e00ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP477"              ,	   0x1180080e00ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP478"              ,	   0x1180080e00ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP479"              ,	   0x1180080e00ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP480"              ,	   0x1180080e00f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP481"              ,	   0x1180080e00f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP482"              ,	   0x1180080e00f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP483"              ,	   0x1180080e00f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP484"              ,	   0x1180080e00f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP485"              ,	   0x1180080e00f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP486"              ,	   0x1180080e00f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP487"              ,	   0x1180080e00f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP488"              ,	   0x1180080e00f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP489"              ,	   0x1180080e00f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP490"              ,	   0x1180080e00f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP491"              ,	   0x1180080e00f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP492"              ,	   0x1180080e00f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP493"              ,	   0x1180080e00f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP494"              ,	   0x1180080e00f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP495"              ,	   0x1180080e00f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP496"              ,	   0x1180080e00f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP497"              ,	   0x1180080e00f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP498"              ,	   0x1180080e00f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP499"              ,	   0x1180080e00f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP500"              ,	   0x1180080e00fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP501"              ,	   0x1180080e00fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP502"              ,	   0x1180080e00fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP503"              ,	   0x1180080e00fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP504"              ,	   0x1180080e00fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP505"              ,	   0x1180080e00fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP506"              ,	   0x1180080e00fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP507"              ,	   0x1180080e00fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP508"              ,	   0x1180080e00fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP509"              ,	   0x1180080e00fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP510"              ,	   0x1180080e00ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP511"              ,	   0x1180080e00ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP512"              ,	   0x1180080e01000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP513"              ,	   0x1180080e01008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP514"              ,	   0x1180080e01010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP515"              ,	   0x1180080e01018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP516"              ,	   0x1180080e01020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP517"              ,	   0x1180080e01028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP518"              ,	   0x1180080e01030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP519"              ,	   0x1180080e01038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP520"              ,	   0x1180080e01040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP521"              ,	   0x1180080e01048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP522"              ,	   0x1180080e01050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP523"              ,	   0x1180080e01058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP524"              ,	   0x1180080e01060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP525"              ,	   0x1180080e01068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP526"              ,	   0x1180080e01070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP527"              ,	   0x1180080e01078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP528"              ,	   0x1180080e01080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP529"              ,	   0x1180080e01088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP530"              ,	   0x1180080e01090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP531"              ,	   0x1180080e01098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP532"              ,	   0x1180080e010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP533"              ,	   0x1180080e010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP534"              ,	   0x1180080e010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP535"              ,	   0x1180080e010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP536"              ,	   0x1180080e010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP537"              ,	   0x1180080e010c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP538"              ,	   0x1180080e010d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP539"              ,	   0x1180080e010d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP540"              ,	   0x1180080e010e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP541"              ,	   0x1180080e010e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP542"              ,	   0x1180080e010f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP543"              ,	   0x1180080e010f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP544"              ,	   0x1180080e01100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP545"              ,	   0x1180080e01108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP546"              ,	   0x1180080e01110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP547"              ,	   0x1180080e01118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP548"              ,	   0x1180080e01120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP549"              ,	   0x1180080e01128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP550"              ,	   0x1180080e01130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP551"              ,	   0x1180080e01138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP552"              ,	   0x1180080e01140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP553"              ,	   0x1180080e01148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP554"              ,	   0x1180080e01150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP555"              ,	   0x1180080e01158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP556"              ,	   0x1180080e01160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP557"              ,	   0x1180080e01168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP558"              ,	   0x1180080e01170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP559"              ,	   0x1180080e01178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP560"              ,	   0x1180080e01180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP561"              ,	   0x1180080e01188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP562"              ,	   0x1180080e01190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP563"              ,	   0x1180080e01198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP564"              ,	   0x1180080e011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP565"              ,	   0x1180080e011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP566"              ,	   0x1180080e011b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP567"              ,	   0x1180080e011b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP568"              ,	   0x1180080e011c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP569"              ,	   0x1180080e011c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP570"              ,	   0x1180080e011d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP571"              ,	   0x1180080e011d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP572"              ,	   0x1180080e011e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP573"              ,	   0x1180080e011e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP574"              ,	   0x1180080e011f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP575"              ,	   0x1180080e011f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP576"              ,	   0x1180080e01200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP577"              ,	   0x1180080e01208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP578"              ,	   0x1180080e01210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP579"              ,	   0x1180080e01218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP580"              ,	   0x1180080e01220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP581"              ,	   0x1180080e01228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP582"              ,	   0x1180080e01230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP583"              ,	   0x1180080e01238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP584"              ,	   0x1180080e01240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP585"              ,	   0x1180080e01248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP586"              ,	   0x1180080e01250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP587"              ,	   0x1180080e01258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP588"              ,	   0x1180080e01260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP589"              ,	   0x1180080e01268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP590"              ,	   0x1180080e01270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP591"              ,	   0x1180080e01278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP592"              ,	   0x1180080e01280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP593"              ,	   0x1180080e01288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP594"              ,	   0x1180080e01290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP595"              ,	   0x1180080e01298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP596"              ,	   0x1180080e012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP597"              ,	   0x1180080e012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP598"              ,	   0x1180080e012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP599"              ,	   0x1180080e012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP600"              ,	   0x1180080e012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP601"              ,	   0x1180080e012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP602"              ,	   0x1180080e012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP603"              ,	   0x1180080e012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP604"              ,	   0x1180080e012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP605"              ,	   0x1180080e012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP606"              ,	   0x1180080e012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP607"              ,	   0x1180080e012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP608"              ,	   0x1180080e01300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP609"              ,	   0x1180080e01308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP610"              ,	   0x1180080e01310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP611"              ,	   0x1180080e01318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP612"              ,	   0x1180080e01320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP613"              ,	   0x1180080e01328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP614"              ,	   0x1180080e01330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP615"              ,	   0x1180080e01338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP616"              ,	   0x1180080e01340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP617"              ,	   0x1180080e01348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP618"              ,	   0x1180080e01350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP619"              ,	   0x1180080e01358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP620"              ,	   0x1180080e01360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP621"              ,	   0x1180080e01368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP622"              ,	   0x1180080e01370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP623"              ,	   0x1180080e01378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP624"              ,	   0x1180080e01380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP625"              ,	   0x1180080e01388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP626"              ,	   0x1180080e01390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP627"              ,	   0x1180080e01398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP628"              ,	   0x1180080e013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP629"              ,	   0x1180080e013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP630"              ,	   0x1180080e013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP631"              ,	   0x1180080e013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP632"              ,	   0x1180080e013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP633"              ,	   0x1180080e013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP634"              ,	   0x1180080e013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP635"              ,	   0x1180080e013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP636"              ,	   0x1180080e013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP637"              ,	   0x1180080e013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP638"              ,	   0x1180080e013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP639"              ,	   0x1180080e013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP640"              ,	   0x1180080e01400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP641"              ,	   0x1180080e01408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP642"              ,	   0x1180080e01410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP643"              ,	   0x1180080e01418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP644"              ,	   0x1180080e01420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP645"              ,	   0x1180080e01428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP646"              ,	   0x1180080e01430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP647"              ,	   0x1180080e01438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP648"              ,	   0x1180080e01440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP649"              ,	   0x1180080e01448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP650"              ,	   0x1180080e01450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP651"              ,	   0x1180080e01458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP652"              ,	   0x1180080e01460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP653"              ,	   0x1180080e01468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP654"              ,	   0x1180080e01470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP655"              ,	   0x1180080e01478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP656"              ,	   0x1180080e01480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP657"              ,	   0x1180080e01488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP658"              ,	   0x1180080e01490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP659"              ,	   0x1180080e01498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP660"              ,	   0x1180080e014a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP661"              ,	   0x1180080e014a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP662"              ,	   0x1180080e014b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP663"              ,	   0x1180080e014b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP664"              ,	   0x1180080e014c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP665"              ,	   0x1180080e014c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP666"              ,	   0x1180080e014d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP667"              ,	   0x1180080e014d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP668"              ,	   0x1180080e014e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP669"              ,	   0x1180080e014e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP670"              ,	   0x1180080e014f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP671"              ,	   0x1180080e014f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP672"              ,	   0x1180080e01500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP673"              ,	   0x1180080e01508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP674"              ,	   0x1180080e01510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP675"              ,	   0x1180080e01518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP676"              ,	   0x1180080e01520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP677"              ,	   0x1180080e01528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP678"              ,	   0x1180080e01530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP679"              ,	   0x1180080e01538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP680"              ,	   0x1180080e01540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP681"              ,	   0x1180080e01548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP682"              ,	   0x1180080e01550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP683"              ,	   0x1180080e01558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP684"              ,	   0x1180080e01560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP685"              ,	   0x1180080e01568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP686"              ,	   0x1180080e01570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP687"              ,	   0x1180080e01578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP688"              ,	   0x1180080e01580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP689"              ,	   0x1180080e01588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP690"              ,	   0x1180080e01590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP691"              ,	   0x1180080e01598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP692"              ,	   0x1180080e015a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP693"              ,	   0x1180080e015a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP694"              ,	   0x1180080e015b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP695"              ,	   0x1180080e015b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP696"              ,	   0x1180080e015c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP697"              ,	   0x1180080e015c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP698"              ,	   0x1180080e015d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP699"              ,	   0x1180080e015d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP700"              ,	   0x1180080e015e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP701"              ,	   0x1180080e015e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP702"              ,	   0x1180080e015f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP703"              ,	   0x1180080e015f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP704"              ,	   0x1180080e01600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP705"              ,	   0x1180080e01608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP706"              ,	   0x1180080e01610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP707"              ,	   0x1180080e01618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP708"              ,	   0x1180080e01620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP709"              ,	   0x1180080e01628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP710"              ,	   0x1180080e01630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP711"              ,	   0x1180080e01638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP712"              ,	   0x1180080e01640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP713"              ,	   0x1180080e01648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP714"              ,	   0x1180080e01650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP715"              ,	   0x1180080e01658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP716"              ,	   0x1180080e01660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP717"              ,	   0x1180080e01668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP718"              ,	   0x1180080e01670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP719"              ,	   0x1180080e01678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP720"              ,	   0x1180080e01680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP721"              ,	   0x1180080e01688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP722"              ,	   0x1180080e01690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP723"              ,	   0x1180080e01698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP724"              ,	   0x1180080e016a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP725"              ,	   0x1180080e016a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP726"              ,	   0x1180080e016b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP727"              ,	   0x1180080e016b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP728"              ,	   0x1180080e016c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP729"              ,	   0x1180080e016c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP730"              ,	   0x1180080e016d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP731"              ,	   0x1180080e016d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP732"              ,	   0x1180080e016e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP733"              ,	   0x1180080e016e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP734"              ,	   0x1180080e016f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP735"              ,	   0x1180080e016f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP736"              ,	   0x1180080e01700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP737"              ,	   0x1180080e01708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP738"              ,	   0x1180080e01710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP739"              ,	   0x1180080e01718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP740"              ,	   0x1180080e01720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP741"              ,	   0x1180080e01728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP742"              ,	   0x1180080e01730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP743"              ,	   0x1180080e01738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP744"              ,	   0x1180080e01740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP745"              ,	   0x1180080e01748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP746"              ,	   0x1180080e01750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP747"              ,	   0x1180080e01758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP748"              ,	   0x1180080e01760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP749"              ,	   0x1180080e01768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP750"              ,	   0x1180080e01770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP751"              ,	   0x1180080e01778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP752"              ,	   0x1180080e01780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP753"              ,	   0x1180080e01788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP754"              ,	   0x1180080e01790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP755"              ,	   0x1180080e01798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP756"              ,	   0x1180080e017a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP757"              ,	   0x1180080e017a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP758"              ,	   0x1180080e017b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP759"              ,	   0x1180080e017b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP760"              ,	   0x1180080e017c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP761"              ,	   0x1180080e017c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP762"              ,	   0x1180080e017d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP763"              ,	   0x1180080e017d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP764"              ,	   0x1180080e017e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP765"              ,	   0x1180080e017e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP766"              ,	   0x1180080e017f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP767"              ,	   0x1180080e017f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP768"              ,	   0x1180080e01800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP769"              ,	   0x1180080e01808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP770"              ,	   0x1180080e01810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP771"              ,	   0x1180080e01818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP772"              ,	   0x1180080e01820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP773"              ,	   0x1180080e01828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP774"              ,	   0x1180080e01830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP775"              ,	   0x1180080e01838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP776"              ,	   0x1180080e01840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP777"              ,	   0x1180080e01848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP778"              ,	   0x1180080e01850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP779"              ,	   0x1180080e01858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP780"              ,	   0x1180080e01860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP781"              ,	   0x1180080e01868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP782"              ,	   0x1180080e01870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP783"              ,	   0x1180080e01878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP784"              ,	   0x1180080e01880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP785"              ,	   0x1180080e01888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP786"              ,	   0x1180080e01890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP787"              ,	   0x1180080e01898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP788"              ,	   0x1180080e018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP789"              ,	   0x1180080e018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP790"              ,	   0x1180080e018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP791"              ,	   0x1180080e018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP792"              ,	   0x1180080e018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP793"              ,	   0x1180080e018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP794"              ,	   0x1180080e018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP795"              ,	   0x1180080e018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP796"              ,	   0x1180080e018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP797"              ,	   0x1180080e018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP798"              ,	   0x1180080e018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP799"              ,	   0x1180080e018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP800"              ,	   0x1180080e01900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP801"              ,	   0x1180080e01908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP802"              ,	   0x1180080e01910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP803"              ,	   0x1180080e01918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP804"              ,	   0x1180080e01920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP805"              ,	   0x1180080e01928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP806"              ,	   0x1180080e01930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP807"              ,	   0x1180080e01938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP808"              ,	   0x1180080e01940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP809"              ,	   0x1180080e01948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP810"              ,	   0x1180080e01950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP811"              ,	   0x1180080e01958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP812"              ,	   0x1180080e01960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP813"              ,	   0x1180080e01968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP814"              ,	   0x1180080e01970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP815"              ,	   0x1180080e01978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP816"              ,	   0x1180080e01980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP817"              ,	   0x1180080e01988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP818"              ,	   0x1180080e01990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP819"              ,	   0x1180080e01998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP820"              ,	   0x1180080e019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP821"              ,	   0x1180080e019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP822"              ,	   0x1180080e019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP823"              ,	   0x1180080e019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP824"              ,	   0x1180080e019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP825"              ,	   0x1180080e019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP826"              ,	   0x1180080e019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP827"              ,	   0x1180080e019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP828"              ,	   0x1180080e019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP829"              ,	   0x1180080e019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP830"              ,	   0x1180080e019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP831"              ,	   0x1180080e019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP832"              ,	   0x1180080e01a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP833"              ,	   0x1180080e01a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP834"              ,	   0x1180080e01a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP835"              ,	   0x1180080e01a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP836"              ,	   0x1180080e01a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP837"              ,	   0x1180080e01a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP838"              ,	   0x1180080e01a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP839"              ,	   0x1180080e01a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP840"              ,	   0x1180080e01a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP841"              ,	   0x1180080e01a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP842"              ,	   0x1180080e01a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP843"              ,	   0x1180080e01a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP844"              ,	   0x1180080e01a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP845"              ,	   0x1180080e01a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP846"              ,	   0x1180080e01a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP847"              ,	   0x1180080e01a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP848"              ,	   0x1180080e01a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP849"              ,	   0x1180080e01a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP850"              ,	   0x1180080e01a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP851"              ,	   0x1180080e01a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP852"              ,	   0x1180080e01aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP853"              ,	   0x1180080e01aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP854"              ,	   0x1180080e01ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP855"              ,	   0x1180080e01ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP856"              ,	   0x1180080e01ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP857"              ,	   0x1180080e01ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP858"              ,	   0x1180080e01ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP859"              ,	   0x1180080e01ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP860"              ,	   0x1180080e01ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP861"              ,	   0x1180080e01ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP862"              ,	   0x1180080e01af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP863"              ,	   0x1180080e01af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP864"              ,	   0x1180080e01b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP865"              ,	   0x1180080e01b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP866"              ,	   0x1180080e01b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP867"              ,	   0x1180080e01b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP868"              ,	   0x1180080e01b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP869"              ,	   0x1180080e01b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP870"              ,	   0x1180080e01b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP871"              ,	   0x1180080e01b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP872"              ,	   0x1180080e01b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP873"              ,	   0x1180080e01b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP874"              ,	   0x1180080e01b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP875"              ,	   0x1180080e01b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP876"              ,	   0x1180080e01b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP877"              ,	   0x1180080e01b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP878"              ,	   0x1180080e01b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP879"              ,	   0x1180080e01b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP880"              ,	   0x1180080e01b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP881"              ,	   0x1180080e01b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP882"              ,	   0x1180080e01b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP883"              ,	   0x1180080e01b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP884"              ,	   0x1180080e01ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP885"              ,	   0x1180080e01ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP886"              ,	   0x1180080e01bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP887"              ,	   0x1180080e01bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP888"              ,	   0x1180080e01bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP889"              ,	   0x1180080e01bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP890"              ,	   0x1180080e01bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP891"              ,	   0x1180080e01bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP892"              ,	   0x1180080e01be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP893"              ,	   0x1180080e01be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP894"              ,	   0x1180080e01bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP895"              ,	   0x1180080e01bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP896"              ,	   0x1180080e01c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP897"              ,	   0x1180080e01c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP898"              ,	   0x1180080e01c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP899"              ,	   0x1180080e01c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP900"              ,	   0x1180080e01c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP901"              ,	   0x1180080e01c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP902"              ,	   0x1180080e01c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP903"              ,	   0x1180080e01c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP904"              ,	   0x1180080e01c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP905"              ,	   0x1180080e01c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP906"              ,	   0x1180080e01c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP907"              ,	   0x1180080e01c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP908"              ,	   0x1180080e01c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP909"              ,	   0x1180080e01c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP910"              ,	   0x1180080e01c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP911"              ,	   0x1180080e01c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP912"              ,	   0x1180080e01c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP913"              ,	   0x1180080e01c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP914"              ,	   0x1180080e01c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP915"              ,	   0x1180080e01c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP916"              ,	   0x1180080e01ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP917"              ,	   0x1180080e01ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP918"              ,	   0x1180080e01cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP919"              ,	   0x1180080e01cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP920"              ,	   0x1180080e01cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP921"              ,	   0x1180080e01cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP922"              ,	   0x1180080e01cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP923"              ,	   0x1180080e01cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP924"              ,	   0x1180080e01ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP925"              ,	   0x1180080e01ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP926"              ,	   0x1180080e01cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP927"              ,	   0x1180080e01cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP928"              ,	   0x1180080e01d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP929"              ,	   0x1180080e01d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP930"              ,	   0x1180080e01d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP931"              ,	   0x1180080e01d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP932"              ,	   0x1180080e01d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP933"              ,	   0x1180080e01d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP934"              ,	   0x1180080e01d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP935"              ,	   0x1180080e01d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP936"              ,	   0x1180080e01d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP937"              ,	   0x1180080e01d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP938"              ,	   0x1180080e01d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP939"              ,	   0x1180080e01d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP940"              ,	   0x1180080e01d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP941"              ,	   0x1180080e01d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP942"              ,	   0x1180080e01d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP943"              ,	   0x1180080e01d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP944"              ,	   0x1180080e01d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP945"              ,	   0x1180080e01d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP946"              ,	   0x1180080e01d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP947"              ,	   0x1180080e01d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP948"              ,	   0x1180080e01da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP949"              ,	   0x1180080e01da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP950"              ,	   0x1180080e01db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP951"              ,	   0x1180080e01db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP952"              ,	   0x1180080e01dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP953"              ,	   0x1180080e01dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP954"              ,	   0x1180080e01dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP955"              ,	   0x1180080e01dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP956"              ,	   0x1180080e01de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP957"              ,	   0x1180080e01de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP958"              ,	   0x1180080e01df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP959"              ,	   0x1180080e01df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP960"              ,	   0x1180080e01e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP961"              ,	   0x1180080e01e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP962"              ,	   0x1180080e01e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP963"              ,	   0x1180080e01e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP964"              ,	   0x1180080e01e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP965"              ,	   0x1180080e01e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP966"              ,	   0x1180080e01e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP967"              ,	   0x1180080e01e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP968"              ,	   0x1180080e01e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP969"              ,	   0x1180080e01e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP970"              ,	   0x1180080e01e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP971"              ,	   0x1180080e01e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP972"              ,	   0x1180080e01e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP973"              ,	   0x1180080e01e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP974"              ,	   0x1180080e01e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP975"              ,	   0x1180080e01e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP976"              ,	   0x1180080e01e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP977"              ,	   0x1180080e01e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP978"              ,	   0x1180080e01e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP979"              ,	   0x1180080e01e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP980"              ,	   0x1180080e01ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP981"              ,	   0x1180080e01ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP982"              ,	   0x1180080e01eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP983"              ,	   0x1180080e01eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP984"              ,	   0x1180080e01ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP985"              ,	   0x1180080e01ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP986"              ,	   0x1180080e01ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP987"              ,	   0x1180080e01ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP988"              ,	   0x1180080e01ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP989"              ,	   0x1180080e01ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP990"              ,	   0x1180080e01ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP991"              ,	   0x1180080e01ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP992"              ,	   0x1180080e01f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP993"              ,	   0x1180080e01f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP994"              ,	   0x1180080e01f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP995"              ,	   0x1180080e01f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP996"              ,	   0x1180080e01f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP997"              ,	   0x1180080e01f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP998"              ,	   0x1180080e01f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP999"              ,	   0x1180080e01f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1000"             ,	   0x1180080e01f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1001"             ,	   0x1180080e01f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1002"             ,	   0x1180080e01f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1003"             ,	   0x1180080e01f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1004"             ,	   0x1180080e01f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1005"             ,	   0x1180080e01f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1006"             ,	   0x1180080e01f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1007"             ,	   0x1180080e01f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1008"             ,	   0x1180080e01f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1009"             ,	   0x1180080e01f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1010"             ,	   0x1180080e01f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1011"             ,	   0x1180080e01f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1012"             ,	   0x1180080e01fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1013"             ,	   0x1180080e01fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1014"             ,	   0x1180080e01fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1015"             ,	   0x1180080e01fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1016"             ,	   0x1180080e01fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1017"             ,	   0x1180080e01fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1018"             ,	   0x1180080e01fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1019"             ,	   0x1180080e01fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1020"             ,	   0x1180080e01fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1021"             ,	   0x1180080e01fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1022"             ,	   0x1180080e01ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1023"             ,	   0x1180080e01ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_ERR_TDT0"                ,	   0x1180080a007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"L2C_ERR_TTG0"                ,	   0x1180080a007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"L2C_ERR_VBF0"                ,	   0x1180080c007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"L2C_ERR_XMC"                 ,	   0x11800808007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"L2C_INT_ENA"                 ,	   0x1180080800020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"L2C_INT_REG"                 ,	   0x1180080800018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"L2C_IOC0_PFC"                ,	   0x1180080800420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"L2C_IOR0_PFC"                ,	   0x1180080800428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"L2C_QOS_IOB0"                ,	   0x1180080880200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"L2C_QOS_PP0"                 ,	   0x1180080880000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"L2C_QOS_PP1"                 ,	   0x1180080880008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"L2C_QOS_PP2"                 ,	   0x1180080880010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"L2C_QOS_PP3"                 ,	   0x1180080880018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"L2C_QOS_WGT"                 ,	   0x1180080800008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"L2C_RSC0_PFC"                ,	   0x1180080800410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"L2C_RSD0_PFC"                ,	   0x1180080800418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"L2C_TAD0_ECC0"               ,	   0x1180080a00018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"L2C_TAD0_ECC1"               ,	   0x1180080a00020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"L2C_TAD0_IEN"                ,	   0x1180080a00000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"L2C_TAD0_INT"                ,	   0x1180080a00028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"L2C_TAD0_PFC0"               ,	   0x1180080a00400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"L2C_TAD0_PFC1"               ,	   0x1180080a00408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"L2C_TAD0_PFC2"               ,	   0x1180080a00410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"L2C_TAD0_PFC3"               ,	   0x1180080a00418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"L2C_TAD0_PRF"                ,	   0x1180080a00008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"L2C_TAD0_TAG"                ,	   0x1180080a00010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VER_ID"                  ,	   0x11800808007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"L2C_VER_IOB"                 ,	   0x11800808007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"L2C_VER_MSC"                 ,	   0x11800808007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"L2C_VER_PP"                  ,	   0x11800808007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"L2C_VIRTID_IOB0"             ,	   0x11800808c0200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"L2C_VIRTID_PP0"              ,	   0x11800808c0000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"L2C_VIRTID_PP1"              ,	   0x11800808c0008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"L2C_VIRTID_PP2"              ,	   0x11800808c0010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"L2C_VIRTID_PP3"              ,	   0x11800808c0018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"L2C_VRT_CTL"                 ,	   0x1180080800010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"L2C_VRT_MEM0"                ,	   0x1180080900000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1"                ,	   0x1180080900008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM2"                ,	   0x1180080900010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM3"                ,	   0x1180080900018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM4"                ,	   0x1180080900020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM5"                ,	   0x1180080900028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM6"                ,	   0x1180080900030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM7"                ,	   0x1180080900038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM8"                ,	   0x1180080900040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM9"                ,	   0x1180080900048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM10"               ,	   0x1180080900050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM11"               ,	   0x1180080900058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM12"               ,	   0x1180080900060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM13"               ,	   0x1180080900068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM14"               ,	   0x1180080900070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM15"               ,	   0x1180080900078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM16"               ,	   0x1180080900080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM17"               ,	   0x1180080900088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM18"               ,	   0x1180080900090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM19"               ,	   0x1180080900098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM20"               ,	   0x11800809000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM21"               ,	   0x11800809000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM22"               ,	   0x11800809000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM23"               ,	   0x11800809000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM24"               ,	   0x11800809000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM25"               ,	   0x11800809000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM26"               ,	   0x11800809000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM27"               ,	   0x11800809000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM28"               ,	   0x11800809000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM29"               ,	   0x11800809000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM30"               ,	   0x11800809000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM31"               ,	   0x11800809000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM32"               ,	   0x1180080900100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM33"               ,	   0x1180080900108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM34"               ,	   0x1180080900110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM35"               ,	   0x1180080900118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM36"               ,	   0x1180080900120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM37"               ,	   0x1180080900128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM38"               ,	   0x1180080900130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM39"               ,	   0x1180080900138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM40"               ,	   0x1180080900140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM41"               ,	   0x1180080900148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM42"               ,	   0x1180080900150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM43"               ,	   0x1180080900158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM44"               ,	   0x1180080900160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM45"               ,	   0x1180080900168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM46"               ,	   0x1180080900170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM47"               ,	   0x1180080900178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM48"               ,	   0x1180080900180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM49"               ,	   0x1180080900188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM50"               ,	   0x1180080900190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM51"               ,	   0x1180080900198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM52"               ,	   0x11800809001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM53"               ,	   0x11800809001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM54"               ,	   0x11800809001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM55"               ,	   0x11800809001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM56"               ,	   0x11800809001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM57"               ,	   0x11800809001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM58"               ,	   0x11800809001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM59"               ,	   0x11800809001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM60"               ,	   0x11800809001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM61"               ,	   0x11800809001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM62"               ,	   0x11800809001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM63"               ,	   0x11800809001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM64"               ,	   0x1180080900200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM65"               ,	   0x1180080900208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM66"               ,	   0x1180080900210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM67"               ,	   0x1180080900218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM68"               ,	   0x1180080900220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM69"               ,	   0x1180080900228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM70"               ,	   0x1180080900230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM71"               ,	   0x1180080900238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM72"               ,	   0x1180080900240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM73"               ,	   0x1180080900248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM74"               ,	   0x1180080900250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM75"               ,	   0x1180080900258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM76"               ,	   0x1180080900260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM77"               ,	   0x1180080900268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM78"               ,	   0x1180080900270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM79"               ,	   0x1180080900278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM80"               ,	   0x1180080900280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM81"               ,	   0x1180080900288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM82"               ,	   0x1180080900290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM83"               ,	   0x1180080900298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM84"               ,	   0x11800809002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM85"               ,	   0x11800809002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM86"               ,	   0x11800809002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM87"               ,	   0x11800809002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM88"               ,	   0x11800809002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM89"               ,	   0x11800809002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM90"               ,	   0x11800809002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM91"               ,	   0x11800809002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM92"               ,	   0x11800809002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM93"               ,	   0x11800809002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM94"               ,	   0x11800809002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM95"               ,	   0x11800809002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM96"               ,	   0x1180080900300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM97"               ,	   0x1180080900308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM98"               ,	   0x1180080900310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM99"               ,	   0x1180080900318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM100"              ,	   0x1180080900320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM101"              ,	   0x1180080900328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM102"              ,	   0x1180080900330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM103"              ,	   0x1180080900338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM104"              ,	   0x1180080900340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM105"              ,	   0x1180080900348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM106"              ,	   0x1180080900350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM107"              ,	   0x1180080900358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM108"              ,	   0x1180080900360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM109"              ,	   0x1180080900368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM110"              ,	   0x1180080900370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM111"              ,	   0x1180080900378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM112"              ,	   0x1180080900380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM113"              ,	   0x1180080900388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM114"              ,	   0x1180080900390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM115"              ,	   0x1180080900398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM116"              ,	   0x11800809003a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM117"              ,	   0x11800809003a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM118"              ,	   0x11800809003b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM119"              ,	   0x11800809003b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM120"              ,	   0x11800809003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM121"              ,	   0x11800809003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM122"              ,	   0x11800809003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM123"              ,	   0x11800809003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM124"              ,	   0x11800809003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM125"              ,	   0x11800809003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM126"              ,	   0x11800809003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM127"              ,	   0x11800809003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM128"              ,	   0x1180080900400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM129"              ,	   0x1180080900408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM130"              ,	   0x1180080900410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM131"              ,	   0x1180080900418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM132"              ,	   0x1180080900420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM133"              ,	   0x1180080900428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM134"              ,	   0x1180080900430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM135"              ,	   0x1180080900438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM136"              ,	   0x1180080900440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM137"              ,	   0x1180080900448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM138"              ,	   0x1180080900450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM139"              ,	   0x1180080900458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM140"              ,	   0x1180080900460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM141"              ,	   0x1180080900468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM142"              ,	   0x1180080900470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM143"              ,	   0x1180080900478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM144"              ,	   0x1180080900480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM145"              ,	   0x1180080900488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM146"              ,	   0x1180080900490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM147"              ,	   0x1180080900498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM148"              ,	   0x11800809004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM149"              ,	   0x11800809004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM150"              ,	   0x11800809004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM151"              ,	   0x11800809004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM152"              ,	   0x11800809004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM153"              ,	   0x11800809004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM154"              ,	   0x11800809004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM155"              ,	   0x11800809004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM156"              ,	   0x11800809004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM157"              ,	   0x11800809004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM158"              ,	   0x11800809004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM159"              ,	   0x11800809004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM160"              ,	   0x1180080900500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM161"              ,	   0x1180080900508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM162"              ,	   0x1180080900510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM163"              ,	   0x1180080900518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM164"              ,	   0x1180080900520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM165"              ,	   0x1180080900528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM166"              ,	   0x1180080900530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM167"              ,	   0x1180080900538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM168"              ,	   0x1180080900540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM169"              ,	   0x1180080900548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM170"              ,	   0x1180080900550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM171"              ,	   0x1180080900558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM172"              ,	   0x1180080900560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM173"              ,	   0x1180080900568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM174"              ,	   0x1180080900570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM175"              ,	   0x1180080900578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM176"              ,	   0x1180080900580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM177"              ,	   0x1180080900588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM178"              ,	   0x1180080900590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM179"              ,	   0x1180080900598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM180"              ,	   0x11800809005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM181"              ,	   0x11800809005a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM182"              ,	   0x11800809005b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM183"              ,	   0x11800809005b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM184"              ,	   0x11800809005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM185"              ,	   0x11800809005c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM186"              ,	   0x11800809005d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM187"              ,	   0x11800809005d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM188"              ,	   0x11800809005e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM189"              ,	   0x11800809005e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM190"              ,	   0x11800809005f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM191"              ,	   0x11800809005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM192"              ,	   0x1180080900600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM193"              ,	   0x1180080900608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM194"              ,	   0x1180080900610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM195"              ,	   0x1180080900618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM196"              ,	   0x1180080900620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM197"              ,	   0x1180080900628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM198"              ,	   0x1180080900630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM199"              ,	   0x1180080900638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM200"              ,	   0x1180080900640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM201"              ,	   0x1180080900648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM202"              ,	   0x1180080900650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM203"              ,	   0x1180080900658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM204"              ,	   0x1180080900660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM205"              ,	   0x1180080900668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM206"              ,	   0x1180080900670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM207"              ,	   0x1180080900678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM208"              ,	   0x1180080900680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM209"              ,	   0x1180080900688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM210"              ,	   0x1180080900690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM211"              ,	   0x1180080900698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM212"              ,	   0x11800809006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM213"              ,	   0x11800809006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM214"              ,	   0x11800809006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM215"              ,	   0x11800809006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM216"              ,	   0x11800809006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM217"              ,	   0x11800809006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM218"              ,	   0x11800809006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM219"              ,	   0x11800809006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM220"              ,	   0x11800809006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM221"              ,	   0x11800809006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM222"              ,	   0x11800809006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM223"              ,	   0x11800809006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM224"              ,	   0x1180080900700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM225"              ,	   0x1180080900708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM226"              ,	   0x1180080900710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM227"              ,	   0x1180080900718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM228"              ,	   0x1180080900720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM229"              ,	   0x1180080900728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM230"              ,	   0x1180080900730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM231"              ,	   0x1180080900738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM232"              ,	   0x1180080900740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM233"              ,	   0x1180080900748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM234"              ,	   0x1180080900750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM235"              ,	   0x1180080900758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM236"              ,	   0x1180080900760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM237"              ,	   0x1180080900768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM238"              ,	   0x1180080900770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM239"              ,	   0x1180080900778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM240"              ,	   0x1180080900780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM241"              ,	   0x1180080900788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM242"              ,	   0x1180080900790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM243"              ,	   0x1180080900798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM244"              ,	   0x11800809007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM245"              ,	   0x11800809007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM246"              ,	   0x11800809007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM247"              ,	   0x11800809007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM248"              ,	   0x11800809007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM249"              ,	   0x11800809007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM250"              ,	   0x11800809007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM251"              ,	   0x11800809007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM252"              ,	   0x11800809007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM253"              ,	   0x11800809007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM254"              ,	   0x11800809007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM255"              ,	   0x11800809007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM256"              ,	   0x1180080900800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM257"              ,	   0x1180080900808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM258"              ,	   0x1180080900810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM259"              ,	   0x1180080900818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM260"              ,	   0x1180080900820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM261"              ,	   0x1180080900828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM262"              ,	   0x1180080900830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM263"              ,	   0x1180080900838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM264"              ,	   0x1180080900840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM265"              ,	   0x1180080900848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM266"              ,	   0x1180080900850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM267"              ,	   0x1180080900858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM268"              ,	   0x1180080900860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM269"              ,	   0x1180080900868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM270"              ,	   0x1180080900870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM271"              ,	   0x1180080900878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM272"              ,	   0x1180080900880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM273"              ,	   0x1180080900888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM274"              ,	   0x1180080900890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM275"              ,	   0x1180080900898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM276"              ,	   0x11800809008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM277"              ,	   0x11800809008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM278"              ,	   0x11800809008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM279"              ,	   0x11800809008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM280"              ,	   0x11800809008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM281"              ,	   0x11800809008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM282"              ,	   0x11800809008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM283"              ,	   0x11800809008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM284"              ,	   0x11800809008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM285"              ,	   0x11800809008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM286"              ,	   0x11800809008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM287"              ,	   0x11800809008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM288"              ,	   0x1180080900900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM289"              ,	   0x1180080900908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM290"              ,	   0x1180080900910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM291"              ,	   0x1180080900918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM292"              ,	   0x1180080900920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM293"              ,	   0x1180080900928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM294"              ,	   0x1180080900930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM295"              ,	   0x1180080900938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM296"              ,	   0x1180080900940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM297"              ,	   0x1180080900948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM298"              ,	   0x1180080900950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM299"              ,	   0x1180080900958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM300"              ,	   0x1180080900960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM301"              ,	   0x1180080900968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM302"              ,	   0x1180080900970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM303"              ,	   0x1180080900978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM304"              ,	   0x1180080900980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM305"              ,	   0x1180080900988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM306"              ,	   0x1180080900990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM307"              ,	   0x1180080900998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM308"              ,	   0x11800809009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM309"              ,	   0x11800809009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM310"              ,	   0x11800809009b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM311"              ,	   0x11800809009b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM312"              ,	   0x11800809009c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM313"              ,	   0x11800809009c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM314"              ,	   0x11800809009d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM315"              ,	   0x11800809009d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM316"              ,	   0x11800809009e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM317"              ,	   0x11800809009e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM318"              ,	   0x11800809009f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM319"              ,	   0x11800809009f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM320"              ,	   0x1180080900a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM321"              ,	   0x1180080900a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM322"              ,	   0x1180080900a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM323"              ,	   0x1180080900a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM324"              ,	   0x1180080900a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM325"              ,	   0x1180080900a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM326"              ,	   0x1180080900a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM327"              ,	   0x1180080900a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM328"              ,	   0x1180080900a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM329"              ,	   0x1180080900a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM330"              ,	   0x1180080900a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM331"              ,	   0x1180080900a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM332"              ,	   0x1180080900a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM333"              ,	   0x1180080900a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM334"              ,	   0x1180080900a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM335"              ,	   0x1180080900a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM336"              ,	   0x1180080900a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM337"              ,	   0x1180080900a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM338"              ,	   0x1180080900a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM339"              ,	   0x1180080900a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM340"              ,	   0x1180080900aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM341"              ,	   0x1180080900aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM342"              ,	   0x1180080900ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM343"              ,	   0x1180080900ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM344"              ,	   0x1180080900ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM345"              ,	   0x1180080900ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM346"              ,	   0x1180080900ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM347"              ,	   0x1180080900ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM348"              ,	   0x1180080900ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM349"              ,	   0x1180080900ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM350"              ,	   0x1180080900af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM351"              ,	   0x1180080900af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM352"              ,	   0x1180080900b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM353"              ,	   0x1180080900b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM354"              ,	   0x1180080900b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM355"              ,	   0x1180080900b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM356"              ,	   0x1180080900b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM357"              ,	   0x1180080900b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM358"              ,	   0x1180080900b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM359"              ,	   0x1180080900b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM360"              ,	   0x1180080900b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM361"              ,	   0x1180080900b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM362"              ,	   0x1180080900b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM363"              ,	   0x1180080900b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM364"              ,	   0x1180080900b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM365"              ,	   0x1180080900b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM366"              ,	   0x1180080900b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM367"              ,	   0x1180080900b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM368"              ,	   0x1180080900b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM369"              ,	   0x1180080900b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM370"              ,	   0x1180080900b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM371"              ,	   0x1180080900b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM372"              ,	   0x1180080900ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM373"              ,	   0x1180080900ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM374"              ,	   0x1180080900bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM375"              ,	   0x1180080900bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM376"              ,	   0x1180080900bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM377"              ,	   0x1180080900bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM378"              ,	   0x1180080900bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM379"              ,	   0x1180080900bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM380"              ,	   0x1180080900be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM381"              ,	   0x1180080900be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM382"              ,	   0x1180080900bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM383"              ,	   0x1180080900bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM384"              ,	   0x1180080900c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM385"              ,	   0x1180080900c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM386"              ,	   0x1180080900c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM387"              ,	   0x1180080900c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM388"              ,	   0x1180080900c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM389"              ,	   0x1180080900c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM390"              ,	   0x1180080900c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM391"              ,	   0x1180080900c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM392"              ,	   0x1180080900c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM393"              ,	   0x1180080900c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM394"              ,	   0x1180080900c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM395"              ,	   0x1180080900c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM396"              ,	   0x1180080900c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM397"              ,	   0x1180080900c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM398"              ,	   0x1180080900c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM399"              ,	   0x1180080900c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM400"              ,	   0x1180080900c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM401"              ,	   0x1180080900c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM402"              ,	   0x1180080900c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM403"              ,	   0x1180080900c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM404"              ,	   0x1180080900ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM405"              ,	   0x1180080900ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM406"              ,	   0x1180080900cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM407"              ,	   0x1180080900cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM408"              ,	   0x1180080900cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM409"              ,	   0x1180080900cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM410"              ,	   0x1180080900cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM411"              ,	   0x1180080900cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM412"              ,	   0x1180080900ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM413"              ,	   0x1180080900ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM414"              ,	   0x1180080900cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM415"              ,	   0x1180080900cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM416"              ,	   0x1180080900d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM417"              ,	   0x1180080900d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM418"              ,	   0x1180080900d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM419"              ,	   0x1180080900d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM420"              ,	   0x1180080900d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM421"              ,	   0x1180080900d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM422"              ,	   0x1180080900d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM423"              ,	   0x1180080900d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM424"              ,	   0x1180080900d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM425"              ,	   0x1180080900d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM426"              ,	   0x1180080900d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM427"              ,	   0x1180080900d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM428"              ,	   0x1180080900d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM429"              ,	   0x1180080900d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM430"              ,	   0x1180080900d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM431"              ,	   0x1180080900d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM432"              ,	   0x1180080900d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM433"              ,	   0x1180080900d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM434"              ,	   0x1180080900d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM435"              ,	   0x1180080900d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM436"              ,	   0x1180080900da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM437"              ,	   0x1180080900da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM438"              ,	   0x1180080900db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM439"              ,	   0x1180080900db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM440"              ,	   0x1180080900dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM441"              ,	   0x1180080900dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM442"              ,	   0x1180080900dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM443"              ,	   0x1180080900dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM444"              ,	   0x1180080900de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM445"              ,	   0x1180080900de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM446"              ,	   0x1180080900df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM447"              ,	   0x1180080900df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM448"              ,	   0x1180080900e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM449"              ,	   0x1180080900e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM450"              ,	   0x1180080900e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM451"              ,	   0x1180080900e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM452"              ,	   0x1180080900e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM453"              ,	   0x1180080900e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM454"              ,	   0x1180080900e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM455"              ,	   0x1180080900e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM456"              ,	   0x1180080900e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM457"              ,	   0x1180080900e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM458"              ,	   0x1180080900e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM459"              ,	   0x1180080900e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM460"              ,	   0x1180080900e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM461"              ,	   0x1180080900e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM462"              ,	   0x1180080900e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM463"              ,	   0x1180080900e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM464"              ,	   0x1180080900e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM465"              ,	   0x1180080900e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM466"              ,	   0x1180080900e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM467"              ,	   0x1180080900e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM468"              ,	   0x1180080900ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM469"              ,	   0x1180080900ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM470"              ,	   0x1180080900eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM471"              ,	   0x1180080900eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM472"              ,	   0x1180080900ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM473"              ,	   0x1180080900ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM474"              ,	   0x1180080900ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM475"              ,	   0x1180080900ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM476"              ,	   0x1180080900ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM477"              ,	   0x1180080900ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM478"              ,	   0x1180080900ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM479"              ,	   0x1180080900ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM480"              ,	   0x1180080900f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM481"              ,	   0x1180080900f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM482"              ,	   0x1180080900f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM483"              ,	   0x1180080900f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM484"              ,	   0x1180080900f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM485"              ,	   0x1180080900f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM486"              ,	   0x1180080900f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM487"              ,	   0x1180080900f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM488"              ,	   0x1180080900f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM489"              ,	   0x1180080900f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM490"              ,	   0x1180080900f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM491"              ,	   0x1180080900f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM492"              ,	   0x1180080900f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM493"              ,	   0x1180080900f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM494"              ,	   0x1180080900f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM495"              ,	   0x1180080900f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM496"              ,	   0x1180080900f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM497"              ,	   0x1180080900f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM498"              ,	   0x1180080900f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM499"              ,	   0x1180080900f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM500"              ,	   0x1180080900fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM501"              ,	   0x1180080900fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM502"              ,	   0x1180080900fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM503"              ,	   0x1180080900fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM504"              ,	   0x1180080900fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM505"              ,	   0x1180080900fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM506"              ,	   0x1180080900fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM507"              ,	   0x1180080900fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM508"              ,	   0x1180080900fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM509"              ,	   0x1180080900fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM510"              ,	   0x1180080900ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM511"              ,	   0x1180080900ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM512"              ,	   0x1180080901000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM513"              ,	   0x1180080901008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM514"              ,	   0x1180080901010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM515"              ,	   0x1180080901018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM516"              ,	   0x1180080901020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM517"              ,	   0x1180080901028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM518"              ,	   0x1180080901030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM519"              ,	   0x1180080901038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM520"              ,	   0x1180080901040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM521"              ,	   0x1180080901048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM522"              ,	   0x1180080901050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM523"              ,	   0x1180080901058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM524"              ,	   0x1180080901060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM525"              ,	   0x1180080901068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM526"              ,	   0x1180080901070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM527"              ,	   0x1180080901078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM528"              ,	   0x1180080901080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM529"              ,	   0x1180080901088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM530"              ,	   0x1180080901090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM531"              ,	   0x1180080901098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM532"              ,	   0x11800809010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM533"              ,	   0x11800809010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM534"              ,	   0x11800809010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM535"              ,	   0x11800809010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM536"              ,	   0x11800809010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM537"              ,	   0x11800809010c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM538"              ,	   0x11800809010d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM539"              ,	   0x11800809010d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM540"              ,	   0x11800809010e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM541"              ,	   0x11800809010e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM542"              ,	   0x11800809010f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM543"              ,	   0x11800809010f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM544"              ,	   0x1180080901100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM545"              ,	   0x1180080901108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM546"              ,	   0x1180080901110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM547"              ,	   0x1180080901118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM548"              ,	   0x1180080901120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM549"              ,	   0x1180080901128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM550"              ,	   0x1180080901130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM551"              ,	   0x1180080901138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM552"              ,	   0x1180080901140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM553"              ,	   0x1180080901148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM554"              ,	   0x1180080901150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM555"              ,	   0x1180080901158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM556"              ,	   0x1180080901160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM557"              ,	   0x1180080901168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM558"              ,	   0x1180080901170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM559"              ,	   0x1180080901178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM560"              ,	   0x1180080901180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM561"              ,	   0x1180080901188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM562"              ,	   0x1180080901190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM563"              ,	   0x1180080901198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM564"              ,	   0x11800809011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM565"              ,	   0x11800809011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM566"              ,	   0x11800809011b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM567"              ,	   0x11800809011b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM568"              ,	   0x11800809011c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM569"              ,	   0x11800809011c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM570"              ,	   0x11800809011d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM571"              ,	   0x11800809011d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM572"              ,	   0x11800809011e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM573"              ,	   0x11800809011e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM574"              ,	   0x11800809011f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM575"              ,	   0x11800809011f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM576"              ,	   0x1180080901200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM577"              ,	   0x1180080901208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM578"              ,	   0x1180080901210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM579"              ,	   0x1180080901218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM580"              ,	   0x1180080901220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM581"              ,	   0x1180080901228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM582"              ,	   0x1180080901230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM583"              ,	   0x1180080901238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM584"              ,	   0x1180080901240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM585"              ,	   0x1180080901248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM586"              ,	   0x1180080901250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM587"              ,	   0x1180080901258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM588"              ,	   0x1180080901260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM589"              ,	   0x1180080901268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM590"              ,	   0x1180080901270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM591"              ,	   0x1180080901278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM592"              ,	   0x1180080901280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM593"              ,	   0x1180080901288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM594"              ,	   0x1180080901290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM595"              ,	   0x1180080901298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM596"              ,	   0x11800809012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM597"              ,	   0x11800809012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM598"              ,	   0x11800809012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM599"              ,	   0x11800809012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM600"              ,	   0x11800809012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM601"              ,	   0x11800809012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM602"              ,	   0x11800809012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM603"              ,	   0x11800809012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM604"              ,	   0x11800809012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM605"              ,	   0x11800809012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM606"              ,	   0x11800809012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM607"              ,	   0x11800809012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM608"              ,	   0x1180080901300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM609"              ,	   0x1180080901308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM610"              ,	   0x1180080901310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM611"              ,	   0x1180080901318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM612"              ,	   0x1180080901320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM613"              ,	   0x1180080901328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM614"              ,	   0x1180080901330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM615"              ,	   0x1180080901338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM616"              ,	   0x1180080901340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM617"              ,	   0x1180080901348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM618"              ,	   0x1180080901350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM619"              ,	   0x1180080901358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM620"              ,	   0x1180080901360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM621"              ,	   0x1180080901368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM622"              ,	   0x1180080901370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM623"              ,	   0x1180080901378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM624"              ,	   0x1180080901380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM625"              ,	   0x1180080901388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM626"              ,	   0x1180080901390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM627"              ,	   0x1180080901398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM628"              ,	   0x11800809013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM629"              ,	   0x11800809013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM630"              ,	   0x11800809013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM631"              ,	   0x11800809013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM632"              ,	   0x11800809013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM633"              ,	   0x11800809013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM634"              ,	   0x11800809013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM635"              ,	   0x11800809013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM636"              ,	   0x11800809013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM637"              ,	   0x11800809013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM638"              ,	   0x11800809013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM639"              ,	   0x11800809013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM640"              ,	   0x1180080901400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM641"              ,	   0x1180080901408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM642"              ,	   0x1180080901410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM643"              ,	   0x1180080901418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM644"              ,	   0x1180080901420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM645"              ,	   0x1180080901428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM646"              ,	   0x1180080901430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM647"              ,	   0x1180080901438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM648"              ,	   0x1180080901440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM649"              ,	   0x1180080901448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM650"              ,	   0x1180080901450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM651"              ,	   0x1180080901458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM652"              ,	   0x1180080901460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM653"              ,	   0x1180080901468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM654"              ,	   0x1180080901470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM655"              ,	   0x1180080901478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM656"              ,	   0x1180080901480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM657"              ,	   0x1180080901488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM658"              ,	   0x1180080901490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM659"              ,	   0x1180080901498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM660"              ,	   0x11800809014a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM661"              ,	   0x11800809014a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM662"              ,	   0x11800809014b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM663"              ,	   0x11800809014b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM664"              ,	   0x11800809014c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM665"              ,	   0x11800809014c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM666"              ,	   0x11800809014d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM667"              ,	   0x11800809014d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM668"              ,	   0x11800809014e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM669"              ,	   0x11800809014e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM670"              ,	   0x11800809014f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM671"              ,	   0x11800809014f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM672"              ,	   0x1180080901500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM673"              ,	   0x1180080901508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM674"              ,	   0x1180080901510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM675"              ,	   0x1180080901518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM676"              ,	   0x1180080901520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM677"              ,	   0x1180080901528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM678"              ,	   0x1180080901530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM679"              ,	   0x1180080901538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM680"              ,	   0x1180080901540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM681"              ,	   0x1180080901548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM682"              ,	   0x1180080901550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM683"              ,	   0x1180080901558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM684"              ,	   0x1180080901560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM685"              ,	   0x1180080901568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM686"              ,	   0x1180080901570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM687"              ,	   0x1180080901578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM688"              ,	   0x1180080901580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM689"              ,	   0x1180080901588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM690"              ,	   0x1180080901590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM691"              ,	   0x1180080901598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM692"              ,	   0x11800809015a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM693"              ,	   0x11800809015a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM694"              ,	   0x11800809015b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM695"              ,	   0x11800809015b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM696"              ,	   0x11800809015c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM697"              ,	   0x11800809015c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM698"              ,	   0x11800809015d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM699"              ,	   0x11800809015d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM700"              ,	   0x11800809015e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM701"              ,	   0x11800809015e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM702"              ,	   0x11800809015f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM703"              ,	   0x11800809015f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM704"              ,	   0x1180080901600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM705"              ,	   0x1180080901608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM706"              ,	   0x1180080901610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM707"              ,	   0x1180080901618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM708"              ,	   0x1180080901620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM709"              ,	   0x1180080901628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM710"              ,	   0x1180080901630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM711"              ,	   0x1180080901638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM712"              ,	   0x1180080901640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM713"              ,	   0x1180080901648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM714"              ,	   0x1180080901650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM715"              ,	   0x1180080901658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM716"              ,	   0x1180080901660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM717"              ,	   0x1180080901668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM718"              ,	   0x1180080901670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM719"              ,	   0x1180080901678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM720"              ,	   0x1180080901680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM721"              ,	   0x1180080901688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM722"              ,	   0x1180080901690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM723"              ,	   0x1180080901698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM724"              ,	   0x11800809016a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM725"              ,	   0x11800809016a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM726"              ,	   0x11800809016b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM727"              ,	   0x11800809016b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM728"              ,	   0x11800809016c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM729"              ,	   0x11800809016c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM730"              ,	   0x11800809016d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM731"              ,	   0x11800809016d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM732"              ,	   0x11800809016e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM733"              ,	   0x11800809016e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM734"              ,	   0x11800809016f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM735"              ,	   0x11800809016f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM736"              ,	   0x1180080901700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM737"              ,	   0x1180080901708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM738"              ,	   0x1180080901710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM739"              ,	   0x1180080901718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM740"              ,	   0x1180080901720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM741"              ,	   0x1180080901728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM742"              ,	   0x1180080901730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM743"              ,	   0x1180080901738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM744"              ,	   0x1180080901740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM745"              ,	   0x1180080901748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM746"              ,	   0x1180080901750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM747"              ,	   0x1180080901758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM748"              ,	   0x1180080901760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM749"              ,	   0x1180080901768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM750"              ,	   0x1180080901770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM751"              ,	   0x1180080901778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM752"              ,	   0x1180080901780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM753"              ,	   0x1180080901788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM754"              ,	   0x1180080901790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM755"              ,	   0x1180080901798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM756"              ,	   0x11800809017a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM757"              ,	   0x11800809017a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM758"              ,	   0x11800809017b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM759"              ,	   0x11800809017b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM760"              ,	   0x11800809017c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM761"              ,	   0x11800809017c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM762"              ,	   0x11800809017d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM763"              ,	   0x11800809017d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM764"              ,	   0x11800809017e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM765"              ,	   0x11800809017e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM766"              ,	   0x11800809017f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM767"              ,	   0x11800809017f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM768"              ,	   0x1180080901800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM769"              ,	   0x1180080901808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM770"              ,	   0x1180080901810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM771"              ,	   0x1180080901818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM772"              ,	   0x1180080901820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM773"              ,	   0x1180080901828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM774"              ,	   0x1180080901830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM775"              ,	   0x1180080901838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM776"              ,	   0x1180080901840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM777"              ,	   0x1180080901848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM778"              ,	   0x1180080901850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM779"              ,	   0x1180080901858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM780"              ,	   0x1180080901860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM781"              ,	   0x1180080901868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM782"              ,	   0x1180080901870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM783"              ,	   0x1180080901878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM784"              ,	   0x1180080901880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM785"              ,	   0x1180080901888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM786"              ,	   0x1180080901890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM787"              ,	   0x1180080901898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM788"              ,	   0x11800809018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM789"              ,	   0x11800809018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM790"              ,	   0x11800809018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM791"              ,	   0x11800809018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM792"              ,	   0x11800809018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM793"              ,	   0x11800809018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM794"              ,	   0x11800809018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM795"              ,	   0x11800809018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM796"              ,	   0x11800809018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM797"              ,	   0x11800809018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM798"              ,	   0x11800809018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM799"              ,	   0x11800809018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM800"              ,	   0x1180080901900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM801"              ,	   0x1180080901908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM802"              ,	   0x1180080901910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM803"              ,	   0x1180080901918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM804"              ,	   0x1180080901920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM805"              ,	   0x1180080901928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM806"              ,	   0x1180080901930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM807"              ,	   0x1180080901938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM808"              ,	   0x1180080901940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM809"              ,	   0x1180080901948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM810"              ,	   0x1180080901950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM811"              ,	   0x1180080901958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM812"              ,	   0x1180080901960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM813"              ,	   0x1180080901968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM814"              ,	   0x1180080901970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM815"              ,	   0x1180080901978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM816"              ,	   0x1180080901980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM817"              ,	   0x1180080901988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM818"              ,	   0x1180080901990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM819"              ,	   0x1180080901998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM820"              ,	   0x11800809019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM821"              ,	   0x11800809019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM822"              ,	   0x11800809019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM823"              ,	   0x11800809019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM824"              ,	   0x11800809019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM825"              ,	   0x11800809019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM826"              ,	   0x11800809019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM827"              ,	   0x11800809019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM828"              ,	   0x11800809019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM829"              ,	   0x11800809019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM830"              ,	   0x11800809019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM831"              ,	   0x11800809019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM832"              ,	   0x1180080901a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM833"              ,	   0x1180080901a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM834"              ,	   0x1180080901a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM835"              ,	   0x1180080901a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM836"              ,	   0x1180080901a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM837"              ,	   0x1180080901a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM838"              ,	   0x1180080901a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM839"              ,	   0x1180080901a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM840"              ,	   0x1180080901a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM841"              ,	   0x1180080901a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM842"              ,	   0x1180080901a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM843"              ,	   0x1180080901a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM844"              ,	   0x1180080901a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM845"              ,	   0x1180080901a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM846"              ,	   0x1180080901a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM847"              ,	   0x1180080901a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM848"              ,	   0x1180080901a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM849"              ,	   0x1180080901a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM850"              ,	   0x1180080901a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM851"              ,	   0x1180080901a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM852"              ,	   0x1180080901aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM853"              ,	   0x1180080901aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM854"              ,	   0x1180080901ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM855"              ,	   0x1180080901ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM856"              ,	   0x1180080901ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM857"              ,	   0x1180080901ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM858"              ,	   0x1180080901ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM859"              ,	   0x1180080901ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM860"              ,	   0x1180080901ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM861"              ,	   0x1180080901ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM862"              ,	   0x1180080901af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM863"              ,	   0x1180080901af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM864"              ,	   0x1180080901b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM865"              ,	   0x1180080901b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM866"              ,	   0x1180080901b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM867"              ,	   0x1180080901b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM868"              ,	   0x1180080901b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM869"              ,	   0x1180080901b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM870"              ,	   0x1180080901b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM871"              ,	   0x1180080901b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM872"              ,	   0x1180080901b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM873"              ,	   0x1180080901b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM874"              ,	   0x1180080901b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM875"              ,	   0x1180080901b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM876"              ,	   0x1180080901b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM877"              ,	   0x1180080901b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM878"              ,	   0x1180080901b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM879"              ,	   0x1180080901b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM880"              ,	   0x1180080901b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM881"              ,	   0x1180080901b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM882"              ,	   0x1180080901b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM883"              ,	   0x1180080901b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM884"              ,	   0x1180080901ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM885"              ,	   0x1180080901ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM886"              ,	   0x1180080901bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM887"              ,	   0x1180080901bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM888"              ,	   0x1180080901bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM889"              ,	   0x1180080901bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM890"              ,	   0x1180080901bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM891"              ,	   0x1180080901bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM892"              ,	   0x1180080901be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM893"              ,	   0x1180080901be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM894"              ,	   0x1180080901bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM895"              ,	   0x1180080901bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM896"              ,	   0x1180080901c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM897"              ,	   0x1180080901c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM898"              ,	   0x1180080901c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM899"              ,	   0x1180080901c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM900"              ,	   0x1180080901c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM901"              ,	   0x1180080901c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM902"              ,	   0x1180080901c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM903"              ,	   0x1180080901c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM904"              ,	   0x1180080901c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM905"              ,	   0x1180080901c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM906"              ,	   0x1180080901c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM907"              ,	   0x1180080901c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM908"              ,	   0x1180080901c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM909"              ,	   0x1180080901c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM910"              ,	   0x1180080901c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM911"              ,	   0x1180080901c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM912"              ,	   0x1180080901c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM913"              ,	   0x1180080901c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM914"              ,	   0x1180080901c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM915"              ,	   0x1180080901c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM916"              ,	   0x1180080901ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM917"              ,	   0x1180080901ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM918"              ,	   0x1180080901cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM919"              ,	   0x1180080901cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM920"              ,	   0x1180080901cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM921"              ,	   0x1180080901cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM922"              ,	   0x1180080901cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM923"              ,	   0x1180080901cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM924"              ,	   0x1180080901ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM925"              ,	   0x1180080901ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM926"              ,	   0x1180080901cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM927"              ,	   0x1180080901cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM928"              ,	   0x1180080901d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM929"              ,	   0x1180080901d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM930"              ,	   0x1180080901d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM931"              ,	   0x1180080901d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM932"              ,	   0x1180080901d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM933"              ,	   0x1180080901d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM934"              ,	   0x1180080901d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM935"              ,	   0x1180080901d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM936"              ,	   0x1180080901d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM937"              ,	   0x1180080901d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM938"              ,	   0x1180080901d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM939"              ,	   0x1180080901d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM940"              ,	   0x1180080901d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM941"              ,	   0x1180080901d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM942"              ,	   0x1180080901d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM943"              ,	   0x1180080901d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM944"              ,	   0x1180080901d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM945"              ,	   0x1180080901d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM946"              ,	   0x1180080901d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM947"              ,	   0x1180080901d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM948"              ,	   0x1180080901da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM949"              ,	   0x1180080901da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM950"              ,	   0x1180080901db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM951"              ,	   0x1180080901db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM952"              ,	   0x1180080901dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM953"              ,	   0x1180080901dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM954"              ,	   0x1180080901dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM955"              ,	   0x1180080901dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM956"              ,	   0x1180080901de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM957"              ,	   0x1180080901de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM958"              ,	   0x1180080901df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM959"              ,	   0x1180080901df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM960"              ,	   0x1180080901e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM961"              ,	   0x1180080901e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM962"              ,	   0x1180080901e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM963"              ,	   0x1180080901e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM964"              ,	   0x1180080901e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM965"              ,	   0x1180080901e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM966"              ,	   0x1180080901e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM967"              ,	   0x1180080901e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM968"              ,	   0x1180080901e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM969"              ,	   0x1180080901e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM970"              ,	   0x1180080901e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM971"              ,	   0x1180080901e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM972"              ,	   0x1180080901e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM973"              ,	   0x1180080901e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM974"              ,	   0x1180080901e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM975"              ,	   0x1180080901e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM976"              ,	   0x1180080901e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM977"              ,	   0x1180080901e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM978"              ,	   0x1180080901e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM979"              ,	   0x1180080901e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM980"              ,	   0x1180080901ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM981"              ,	   0x1180080901ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM982"              ,	   0x1180080901eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM983"              ,	   0x1180080901eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM984"              ,	   0x1180080901ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM985"              ,	   0x1180080901ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM986"              ,	   0x1180080901ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM987"              ,	   0x1180080901ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM988"              ,	   0x1180080901ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM989"              ,	   0x1180080901ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM990"              ,	   0x1180080901ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM991"              ,	   0x1180080901ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM992"              ,	   0x1180080901f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM993"              ,	   0x1180080901f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM994"              ,	   0x1180080901f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM995"              ,	   0x1180080901f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM996"              ,	   0x1180080901f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM997"              ,	   0x1180080901f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM998"              ,	   0x1180080901f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM999"              ,	   0x1180080901f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1000"             ,	   0x1180080901f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1001"             ,	   0x1180080901f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1002"             ,	   0x1180080901f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1003"             ,	   0x1180080901f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1004"             ,	   0x1180080901f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1005"             ,	   0x1180080901f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1006"             ,	   0x1180080901f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1007"             ,	   0x1180080901f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1008"             ,	   0x1180080901f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1009"             ,	   0x1180080901f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1010"             ,	   0x1180080901f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1011"             ,	   0x1180080901f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1012"             ,	   0x1180080901fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1013"             ,	   0x1180080901fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1014"             ,	   0x1180080901fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1015"             ,	   0x1180080901fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1016"             ,	   0x1180080901fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1017"             ,	   0x1180080901fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1018"             ,	   0x1180080901fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1019"             ,	   0x1180080901fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1020"             ,	   0x1180080901fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1021"             ,	   0x1180080901fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1022"             ,	   0x1180080901ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1023"             ,	   0x1180080901ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_WPAR_IOB0"               ,	   0x1180080840200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"L2C_WPAR_PP0"                ,	   0x1180080840000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_WPAR_PP1"                ,	   0x1180080840008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_WPAR_PP2"                ,	   0x1180080840010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_WPAR_PP3"                ,	   0x1180080840018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_XMC0_PFC"                ,	   0x1180080800400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"L2C_XMC_CMD"                 ,	   0x1180080800028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_XMD0_PFC"                ,	   0x1180080800408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"LMC0_CHAR_CTL"               ,	   0x1180088000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"LMC0_CHAR_MASK0"             ,	   0x1180088000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"LMC0_CHAR_MASK1"             ,	   0x1180088000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"LMC0_CHAR_MASK2"             ,	   0x1180088000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"LMC0_CHAR_MASK3"             ,	   0x1180088000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"LMC0_CHAR_MASK4"             ,	   0x1180088000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"LMC0_COMP_CTL2"              ,	   0x11800880001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"LMC0_CONFIG"                 ,	   0x1180088000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"LMC0_CONTROL"                ,	   0x1180088000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"LMC0_DCLK_CNT"               ,	   0x11800880001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"LMC0_DDR_PLL_CTL"            ,	   0x1180088000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"LMC0_DIMM000_PARAMS"         ,	   0x1180088000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"LMC0_DIMM001_PARAMS"         ,	   0x1180088000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"LMC0_DIMM_CTL"               ,	   0x1180088000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"LMC0_DLL_CTL2"               ,	   0x11800880001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"LMC0_DLL_CTL3"               ,	   0x1180088000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"LMC0_DUAL_MEMCFG"            ,	   0x1180088000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"LMC0_IFB_CNT"                ,	   0x11800880001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"LMC0_INT"                    ,	   0x11800880001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"LMC0_INT_EN"                 ,	   0x11800880001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"LMC0_MODEREG_PARAMS0"        ,	   0x11800880001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"LMC0_MODEREG_PARAMS1"        ,	   0x1180088000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"LMC0_NXM"                    ,	   0x11800880000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"LMC0_OPS_CNT"                ,	   0x11800880001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"LMC0_PHY_CTL"                ,	   0x1180088000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"LMC0_RESET_CTL"              ,	   0x1180088000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"LMC0_RLEVEL_CTL"             ,	   0x11800880002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"LMC0_RLEVEL_DBG"             ,	   0x11800880002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"LMC0_RLEVEL_RANK000"         ,	   0x1180088000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"LMC0_RLEVEL_RANK001"         ,	   0x1180088000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"LMC0_RLEVEL_RANK002"         ,	   0x1180088000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"LMC0_RLEVEL_RANK003"         ,	   0x1180088000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"LMC0_RODT_MASK"              ,	   0x1180088000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"LMC0_SCRAMBLE_CFG0"          ,	   0x1180088000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"LMC0_SCRAMBLE_CFG1"          ,	   0x1180088000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"LMC0_SCRAMBLED_FADR"         ,	   0x1180088000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"LMC0_SLOT_CTL0"              ,	   0x11800880001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"LMC0_SLOT_CTL1"              ,	   0x1180088000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"LMC0_SLOT_CTL2"              ,	   0x1180088000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"LMC0_TIMING_PARAMS0"         ,	   0x1180088000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"LMC0_TIMING_PARAMS1"         ,	   0x11800880001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"LMC0_TRO_CTL"                ,	   0x1180088000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"LMC0_TRO_STAT"               ,	   0x1180088000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"LMC0_WLEVEL_CTL"             ,	   0x1180088000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"LMC0_WLEVEL_DBG"             ,	   0x1180088000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"LMC0_WLEVEL_RANK000"         ,	   0x11800880002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"LMC0_WLEVEL_RANK001"         ,	   0x11800880002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"LMC0_WLEVEL_RANK002"         ,	   0x11800880002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"LMC0_WLEVEL_RANK003"         ,	   0x11800880002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"LMC0_WODT_MASK"              ,	   0x11800880001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"MIO_BOOT_COMP"               ,	   0x11800000000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"MIO_BOOT_DMA_CFG0"           ,	   0x1180000000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"MIO_BOOT_DMA_CFG1"           ,	   0x1180000000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"MIO_BOOT_DMA_INT0"           ,	   0x1180000000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"MIO_BOOT_DMA_INT1"           ,	   0x1180000000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"MIO_BOOT_DMA_INT_EN0"        ,	   0x1180000000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"MIO_BOOT_DMA_INT_EN1"        ,	   0x1180000000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"MIO_BOOT_DMA_TIM0"           ,	   0x1180000000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"MIO_BOOT_DMA_TIM1"           ,	   0x1180000000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"MIO_BOOT_INT"                ,	   0x11800000000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"MIO_BOOT_PIN_DEFS"           ,	   0x11800000000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"MIO_BOOT_REG_CFG3"           ,	   0x1180000000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"MIO_BOOT_REG_CFG4"           ,	   0x1180000000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"MIO_BOOT_REG_CFG5"           ,	   0x1180000000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"MIO_BOOT_REG_CFG6"           ,	   0x1180000000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"MIO_BOOT_REG_CFG7"           ,	   0x1180000000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"MIO_BOOT_REG_TIM0"           ,	   0x1180000000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"MIO_BOOT_REG_TIM1"           ,	   0x1180000000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"MIO_BOOT_REG_TIM2"           ,	   0x1180000000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"MIO_BOOT_REG_TIM3"           ,	   0x1180000000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"MIO_BOOT_REG_TIM4"           ,	   0x1180000000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"MIO_BOOT_THR"                ,	   0x11800000000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"MIO_EMM_BUF_DAT"             ,	   0x11800000020e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	468},
+	{"MIO_EMM_BUF_IDX"             ,	   0x11800000020e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"MIO_EMM_CFG"                 ,	   0x1180000002000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"MIO_EMM_CMD"                 ,	   0x1180000002058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"MIO_EMM_DMA"                 ,	   0x1180000002050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"MIO_EMM_INT"                 ,	   0x1180000002078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	473},
+	{"MIO_EMM_INT_EN"              ,	   0x1180000002080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	474},
+	{"MIO_EMM_MODE0"               ,	   0x1180000002008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	475},
+	{"MIO_EMM_MODE1"               ,	   0x1180000002010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	475},
+	{"MIO_EMM_MODE2"               ,	   0x1180000002018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	475},
+	{"MIO_EMM_MODE3"               ,	   0x1180000002020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	475},
+	{"MIO_EMM_RCA"                 ,	   0x11800000020a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	476},
+	{"MIO_EMM_RSP_HI"              ,	   0x1180000002070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	477},
+	{"MIO_EMM_RSP_LO"              ,	   0x1180000002068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	478},
+	{"MIO_EMM_RSP_STS"             ,	   0x1180000002060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"MIO_EMM_SAMPLE"              ,	   0x1180000002090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	480},
+	{"MIO_EMM_STS_MASK"            ,	   0x1180000002098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"MIO_EMM_SWITCH"              ,	   0x1180000002048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	482},
+	{"MIO_EMM_WDOG"                ,	   0x1180000002088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	483},
+	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	484},
+	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	484},
+	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	485},
+	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	486},
+	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	487},
+	{"MIO_FUS_DAT3"                ,	   0x1180000001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	488},
+	{"MIO_FUS_EMA"                 ,	   0x1180000001550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	489},
+	{"MIO_FUS_PDF"                 ,	   0x1180000001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	490},
+	{"MIO_FUS_PLL"                 ,	   0x1180000001580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
+	{"MIO_FUS_PROG"                ,	   0x1180000001510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	492},
+	{"MIO_FUS_PROG_TIMES"          ,	   0x1180000001518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	493},
+	{"MIO_FUS_RCMD"                ,	   0x1180000001500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	494},
+	{"MIO_FUS_READ_TIMES"          ,	   0x1180000001570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	495},
+	{"MIO_FUS_REPAIR_RES0"         ,	   0x1180000001558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"MIO_FUS_REPAIR_RES1"         ,	   0x1180000001560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"MIO_FUS_REPAIR_RES2"         ,	   0x1180000001568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"MIO_FUS_SPR_REPAIR_RES"      ,	   0x1180000001548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"MIO_FUS_SPR_REPAIR_SUM"      ,	   0x1180000001540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"MIO_FUS_TGG"                 ,	   0x1180000001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"MIO_FUS_WADR"                ,	   0x1180000001508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"MIO_GPIO_COMP"               ,	   0x11800000000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"MIO_NDF_DMA_CFG"             ,	   0x1180000000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"MIO_NDF_DMA_INT"             ,	   0x1180000000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"MIO_NDF_DMA_INT_EN"          ,	   0x1180000000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"MIO_PTP_CKOUT_HI_INCR"       ,	   0x1070000000f40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	507},
+	{"MIO_PTP_CKOUT_LO_INCR"       ,	   0x1070000000f48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	508},
+	{"MIO_PTP_CKOUT_THRESH_HI"     ,	   0x1070000000f38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
+	{"MIO_PTP_CKOUT_THRESH_LO"     ,	   0x1070000000f30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"MIO_PTP_CLOCK_CFG"           ,	   0x1070000000f00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
+	{"MIO_PTP_CLOCK_COMP"          ,	   0x1070000000f18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	512},
+	{"MIO_PTP_CLOCK_HI"            ,	   0x1070000000f10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	513},
+	{"MIO_PTP_CLOCK_LO"            ,	   0x1070000000f08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	514},
+	{"MIO_PTP_EVT_CNT"             ,	   0x1070000000f28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	515},
+	{"MIO_PTP_PPS_HI_INCR"         ,	   0x1070000000f60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	516},
+	{"MIO_PTP_PPS_LO_INCR"         ,	   0x1070000000f68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	517},
+	{"MIO_PTP_PPS_THRESH_HI"       ,	   0x1070000000f58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"MIO_PTP_PPS_THRESH_LO"       ,	   0x1070000000f50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"MIO_PTP_TIMESTAMP"           ,	   0x1070000000f20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"MIO_QLM0_CFG"                ,	   0x1180000001590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"MIO_QLM1_CFG"                ,	   0x1180000001598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"MIO_QLM2_CFG"                ,	   0x11800000015a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"MIO_RST_BOOT"                ,	   0x1180000001600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
+	{"MIO_RST_CFG"                 ,	   0x1180000001610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
+	{"MIO_RST_CKILL"               ,	   0x1180000001638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
+	{"MIO_RST_CNTL0"               ,	   0x1180000001648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
+	{"MIO_RST_CNTL1"               ,	   0x1180000001650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
+	{"MIO_RST_CTL0"                ,	   0x1180000001618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
+	{"MIO_RST_CTL1"                ,	   0x1180000001620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
+	{"MIO_RST_DELAY"               ,	   0x1180000001608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	527},
+	{"MIO_RST_INT"                 ,	   0x1180000001628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
+	{"MIO_RST_INT_EN"              ,	   0x1180000001630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	529},
+	{"MIO_TWS0_INT"                ,	   0x1180000001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
+	{"MIO_TWS1_INT"                ,	   0x1180000001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
+	{"MIO_TWS0_SW_TWSI"            ,	   0x1180000001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	531},
+	{"MIO_TWS1_SW_TWSI"            ,	   0x1180000001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	531},
+	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"MIO_TWS1_SW_TWSI_EXT"        ,	   0x1180000001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	533},
+	{"MIO_TWS1_TWSI_SW"            ,	   0x1180000001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	533},
+	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	534},
+	{"MIO_UART1_DLH"               ,	   0x1180000000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	534},
+	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	535},
+	{"MIO_UART1_DLL"               ,	   0x1180000000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	535},
+	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	536},
+	{"MIO_UART1_FAR"               ,	   0x1180000000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	536},
+	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	537},
+	{"MIO_UART1_FCR"               ,	   0x1180000000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	537},
+	{"MIO_UART0_HTX"               ,	   0x1180000000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	538},
+	{"MIO_UART1_HTX"               ,	   0x1180000000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	538},
+	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	539},
+	{"MIO_UART1_IER"               ,	   0x1180000000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	539},
+	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
+	{"MIO_UART1_IIR"               ,	   0x1180000000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
+	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
+	{"MIO_UART1_LCR"               ,	   0x1180000000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
+	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	542},
+	{"MIO_UART1_LSR"               ,	   0x1180000000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	542},
+	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	543},
+	{"MIO_UART1_MCR"               ,	   0x1180000000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	543},
+	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	544},
+	{"MIO_UART1_MSR"               ,	   0x1180000000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	544},
+	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"MIO_UART1_RBR"               ,	   0x1180000000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"MIO_UART0_RFL"               ,	   0x1180000000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
+	{"MIO_UART1_RFL"               ,	   0x1180000000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
+	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
+	{"MIO_UART1_RFW"               ,	   0x1180000000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	548},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	548},
+	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	549},
+	{"MIO_UART1_SCR"               ,	   0x1180000000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	549},
+	{"MIO_UART0_SFE"               ,	   0x1180000000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	550},
+	{"MIO_UART1_SFE"               ,	   0x1180000000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	550},
+	{"MIO_UART0_SRR"               ,	   0x1180000000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	551},
+	{"MIO_UART1_SRR"               ,	   0x1180000000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	551},
+	{"MIO_UART0_SRT"               ,	   0x1180000000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	552},
+	{"MIO_UART1_SRT"               ,	   0x1180000000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	552},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
+	{"MIO_UART0_STT"               ,	   0x1180000000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
+	{"MIO_UART1_STT"               ,	   0x1180000000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
+	{"MIO_UART0_TFL"               ,	   0x1180000000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"MIO_UART1_TFL"               ,	   0x1180000000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
+	{"MIO_UART1_TFR"               ,	   0x1180000000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
+	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
+	{"MIO_UART1_THR"               ,	   0x1180000000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
+	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"MIO_UART1_USR"               ,	   0x1180000000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"MIX0_BIST"                   ,	   0x1070000100078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	559},
+	{"MIX1_BIST"                   ,	   0x1070000100878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	559},
+	{"MIX0_CTL"                    ,	   0x1070000100020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	560},
+	{"MIX1_CTL"                    ,	   0x1070000100820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	560},
+	{"MIX0_INTENA"                 ,	   0x1070000100050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	561},
+	{"MIX1_INTENA"                 ,	   0x1070000100850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	561},
+	{"MIX0_IRCNT"                  ,	   0x1070000100030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	562},
+	{"MIX1_IRCNT"                  ,	   0x1070000100830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	562},
+	{"MIX0_IRHWM"                  ,	   0x1070000100028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	563},
+	{"MIX1_IRHWM"                  ,	   0x1070000100828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	563},
+	{"MIX0_IRING1"                 ,	   0x1070000100010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	564},
+	{"MIX1_IRING1"                 ,	   0x1070000100810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	564},
+	{"MIX0_IRING2"                 ,	   0x1070000100018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"MIX1_IRING2"                 ,	   0x1070000100818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"MIX0_ISR"                    ,	   0x1070000100048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"MIX1_ISR"                    ,	   0x1070000100848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"MIX0_ORCNT"                  ,	   0x1070000100040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	567},
+	{"MIX1_ORCNT"                  ,	   0x1070000100840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	567},
+	{"MIX0_ORHWM"                  ,	   0x1070000100038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	568},
+	{"MIX1_ORHWM"                  ,	   0x1070000100838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	568},
+	{"MIX0_ORING1"                 ,	   0x1070000100000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	569},
+	{"MIX1_ORING1"                 ,	   0x1070000100800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	569},
+	{"MIX0_ORING2"                 ,	   0x1070000100008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"MIX1_ORING2"                 ,	   0x1070000100808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"MIX0_REMCNT"                 ,	   0x1070000100058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"MIX1_REMCNT"                 ,	   0x1070000100858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"MIX0_TSCTL"                  ,	   0x1070000100068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	572},
+	{"MIX1_TSCTL"                  ,	   0x1070000100868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	572},
+	{"MIX0_TSTAMP"                 ,	   0x1070000100060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	573},
+	{"MIX1_TSTAMP"                 ,	   0x1070000100860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	573},
+	{"MPI_CFG"                     ,	   0x1070000001000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	574},
+	{"MPI_DAT0"                    ,	   0x1070000001080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	575},
+	{"MPI_DAT1"                    ,	   0x1070000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	575},
+	{"MPI_DAT2"                    ,	   0x1070000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	575},
+	{"MPI_DAT3"                    ,	   0x1070000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	575},
+	{"MPI_DAT4"                    ,	   0x10700000010a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	575},
+	{"MPI_DAT5"                    ,	   0x10700000010a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	575},
+	{"MPI_DAT6"                    ,	   0x10700000010b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	575},
+	{"MPI_DAT7"                    ,	   0x10700000010b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	575},
+	{"MPI_DAT8"                    ,	   0x10700000010c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	575},
+	{"MPI_STS"                     ,	   0x1070000001008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	576},
+	{"MPI_TX"                      ,	   0x1070000001010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	577},
+	{"PCIEEP0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	578},
+	{"PCIEEP1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	578},
+	{"PCIEEP0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	579},
+	{"PCIEEP1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	579},
+	{"PCIEEP0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	580},
+	{"PCIEEP1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	580},
+	{"PCIEEP0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	581},
+	{"PCIEEP1_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	581},
+	{"PCIEEP0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	582},
+	{"PCIEEP1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	582},
+	{"PCIEEP0_CFG004_MASK"         ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	583},
+	{"PCIEEP1_CFG004_MASK"         ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	583},
+	{"PCIEEP0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	584},
+	{"PCIEEP1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	584},
+	{"PCIEEP0_CFG005_MASK"         ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	585},
+	{"PCIEEP1_CFG005_MASK"         ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	585},
+	{"PCIEEP0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	586},
+	{"PCIEEP1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	586},
+	{"PCIEEP0_CFG006_MASK"         ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	587},
+	{"PCIEEP1_CFG006_MASK"         ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	587},
+	{"PCIEEP0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	588},
+	{"PCIEEP1_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	588},
+	{"PCIEEP0_CFG007_MASK"         ,	        0x8000001cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	589},
+	{"PCIEEP1_CFG007_MASK"         ,	        0x8000001cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	589},
+	{"PCIEEP0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	590},
+	{"PCIEEP1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	590},
+	{"PCIEEP0_CFG008_MASK"         ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	591},
+	{"PCIEEP1_CFG008_MASK"         ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	591},
+	{"PCIEEP0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	592},
+	{"PCIEEP1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	592},
+	{"PCIEEP0_CFG009_MASK"         ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	593},
+	{"PCIEEP1_CFG009_MASK"         ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	593},
+	{"PCIEEP0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	594},
+	{"PCIEEP1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	594},
+	{"PCIEEP0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	595},
+	{"PCIEEP1_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	595},
+	{"PCIEEP0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	596},
+	{"PCIEEP1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	596},
+	{"PCIEEP0_CFG012_MASK"         ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	597},
+	{"PCIEEP1_CFG012_MASK"         ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	597},
+	{"PCIEEP0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	598},
+	{"PCIEEP1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	598},
+	{"PCIEEP0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	599},
+	{"PCIEEP1_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	599},
+	{"PCIEEP0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	600},
+	{"PCIEEP1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	600},
+	{"PCIEEP0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	601},
+	{"PCIEEP1_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	601},
+	{"PCIEEP0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	602},
+	{"PCIEEP1_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	602},
+	{"PCIEEP0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	603},
+	{"PCIEEP1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	603},
+	{"PCIEEP0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	604},
+	{"PCIEEP1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	604},
+	{"PCIEEP0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	605},
+	{"PCIEEP1_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	605},
+	{"PCIEEP0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	606},
+	{"PCIEEP1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	606},
+	{"PCIEEP0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	607},
+	{"PCIEEP1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	607},
+	{"PCIEEP0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	608},
+	{"PCIEEP1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	608},
+	{"PCIEEP0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	609},
+	{"PCIEEP1_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	609},
+	{"PCIEEP0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	610},
+	{"PCIEEP1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	610},
+	{"PCIEEP0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	611},
+	{"PCIEEP1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	611},
+	{"PCIEEP0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	612},
+	{"PCIEEP1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	612},
+	{"PCIEEP0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	613},
+	{"PCIEEP1_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	613},
+	{"PCIEEP0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	614},
+	{"PCIEEP1_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	614},
+	{"PCIEEP0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	615},
+	{"PCIEEP1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	615},
+	{"PCIEEP0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	616},
+	{"PCIEEP1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	616},
+	{"PCIEEP0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	617},
+	{"PCIEEP1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	617},
+	{"PCIEEP0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	618},
+	{"PCIEEP1_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	618},
+	{"PCIEEP0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	619},
+	{"PCIEEP1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	619},
+	{"PCIEEP0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	620},
+	{"PCIEEP1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	620},
+	{"PCIEEP0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	621},
+	{"PCIEEP1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	621},
+	{"PCIEEP0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	622},
+	{"PCIEEP1_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	622},
+	{"PCIEEP0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	623},
+	{"PCIEEP1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	623},
+	{"PCIEEP0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	624},
+	{"PCIEEP1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	624},
+	{"PCIEEP0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	625},
+	{"PCIEEP1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	625},
+	{"PCIEEP0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	626},
+	{"PCIEEP1_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	626},
+	{"PCIEEP0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	627},
+	{"PCIEEP1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	627},
+	{"PCIEEP0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	628},
+	{"PCIEEP1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	628},
+	{"PCIEEP0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	629},
+	{"PCIEEP1_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	629},
+	{"PCIEEP0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	630},
+	{"PCIEEP1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	630},
+	{"PCIEEP0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	631},
+	{"PCIEEP1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	631},
+	{"PCIEEP0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	632},
+	{"PCIEEP1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	632},
+	{"PCIEEP0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	633},
+	{"PCIEEP1_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	633},
+	{"PCIEEP0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	634},
+	{"PCIEEP1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	634},
+	{"PCIEEP0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	635},
+	{"PCIEEP1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	635},
+	{"PCIEEP0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	636},
+	{"PCIEEP1_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	636},
+	{"PCIEEP0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	637},
+	{"PCIEEP1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	637},
+	{"PCIEEP0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	638},
+	{"PCIEEP1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	638},
+	{"PCIEEP0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	639},
+	{"PCIEEP1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	639},
+	{"PCIEEP0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	640},
+	{"PCIEEP1_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	640},
+	{"PCIEEP0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	641},
+	{"PCIEEP1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	641},
+	{"PCIEEP0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	642},
+	{"PCIEEP1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	642},
+	{"PCIEEP0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	643},
+	{"PCIEEP1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	643},
+	{"PCIEEP0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	644},
+	{"PCIEEP1_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	644},
+	{"PCIEEP0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	645},
+	{"PCIEEP1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	645},
+	{"PCIEEP0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	646},
+	{"PCIEEP1_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	646},
+	{"PCIEEP0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	647},
+	{"PCIEEP1_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	647},
+	{"PCIEEP0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	648},
+	{"PCIEEP1_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	648},
+	{"PCIEEP0_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	649},
+	{"PCIEEP1_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	649},
+	{"PCIEEP0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	650},
+	{"PCIEEP1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	650},
+	{"PCIEEP0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	651},
+	{"PCIEEP1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	651},
+	{"PCIERC0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	652},
+	{"PCIERC1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	652},
+	{"PCIERC0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	653},
+	{"PCIERC1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	653},
+	{"PCIERC0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	654},
+	{"PCIERC1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	654},
+	{"PCIERC0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	655},
+	{"PCIERC1_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	655},
+	{"PCIERC0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	656},
+	{"PCIERC1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	656},
+	{"PCIERC0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	657},
+	{"PCIERC1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	657},
+	{"PCIERC0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	658},
+	{"PCIERC1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	658},
+	{"PCIERC0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	659},
+	{"PCIERC1_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	659},
+	{"PCIERC0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	660},
+	{"PCIERC1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	660},
+	{"PCIERC0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	661},
+	{"PCIERC1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	661},
+	{"PCIERC0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	662},
+	{"PCIERC1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	662},
+	{"PCIERC0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	663},
+	{"PCIERC1_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	663},
+	{"PCIERC0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	664},
+	{"PCIERC1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	664},
+	{"PCIERC0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	665},
+	{"PCIERC1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	665},
+	{"PCIERC0_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	666},
+	{"PCIERC1_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	666},
+	{"PCIERC0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	667},
+	{"PCIERC1_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	667},
+	{"PCIERC0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	668},
+	{"PCIERC1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	668},
+	{"PCIERC0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	669},
+	{"PCIERC1_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	669},
+	{"PCIERC0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	670},
+	{"PCIERC1_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	670},
+	{"PCIERC0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	671},
+	{"PCIERC1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	671},
+	{"PCIERC0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	672},
+	{"PCIERC1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	672},
+	{"PCIERC0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	673},
+	{"PCIERC1_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	673},
+	{"PCIERC0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	674},
+	{"PCIERC1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	674},
+	{"PCIERC0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	675},
+	{"PCIERC1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	675},
+	{"PCIERC0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	676},
+	{"PCIERC1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	676},
+	{"PCIERC0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	677},
+	{"PCIERC1_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	677},
+	{"PCIERC0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	678},
+	{"PCIERC1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	678},
+	{"PCIERC0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	679},
+	{"PCIERC1_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	679},
+	{"PCIERC0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	680},
+	{"PCIERC1_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	680},
+	{"PCIERC0_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	681},
+	{"PCIERC1_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	681},
+	{"PCIERC0_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	682},
+	{"PCIERC1_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	682},
+	{"PCIERC0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	683},
+	{"PCIERC1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	683},
+	{"PCIERC0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	684},
+	{"PCIERC1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	684},
+	{"PCIERC0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	685},
+	{"PCIERC1_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	685},
+	{"PCIERC0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	686},
+	{"PCIERC1_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	686},
+	{"PCIERC0_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	687},
+	{"PCIERC1_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	687},
+	{"PCIERC0_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	688},
+	{"PCIERC1_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	688},
+	{"PCIERC0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	689},
+	{"PCIERC1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	689},
+	{"PCIERC0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	690},
+	{"PCIERC1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	690},
+	{"PCIERC0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	691},
+	{"PCIERC1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	691},
+	{"PCIERC0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	692},
+	{"PCIERC1_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	692},
+	{"PCIERC0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	693},
+	{"PCIERC1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	693},
+	{"PCIERC0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	694},
+	{"PCIERC1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	694},
+	{"PCIERC0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	695},
+	{"PCIERC1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	695},
+	{"PCIERC0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	696},
+	{"PCIERC1_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	696},
+	{"PCIERC0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	697},
+	{"PCIERC1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	697},
+	{"PCIERC0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	698},
+	{"PCIERC1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	698},
+	{"PCIERC0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	699},
+	{"PCIERC1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	699},
+	{"PCIERC0_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	700},
+	{"PCIERC1_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	700},
+	{"PCIERC0_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	701},
+	{"PCIERC1_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	701},
+	{"PCIERC0_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	702},
+	{"PCIERC1_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	702},
+	{"PCIERC0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	703},
+	{"PCIERC1_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	703},
+	{"PCIERC0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	704},
+	{"PCIERC1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	704},
+	{"PCIERC0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	705},
+	{"PCIERC1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	705},
+	{"PCIERC0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	706},
+	{"PCIERC1_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	706},
+	{"PCIERC0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	707},
+	{"PCIERC1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	707},
+	{"PCIERC0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	708},
+	{"PCIERC1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	708},
+	{"PCIERC0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	709},
+	{"PCIERC1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	709},
+	{"PCIERC0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	710},
+	{"PCIERC1_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	710},
+	{"PCIERC0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	711},
+	{"PCIERC1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	711},
+	{"PCIERC0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	712},
+	{"PCIERC1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	712},
+	{"PCIERC0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	713},
+	{"PCIERC1_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	713},
+	{"PCIERC0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	714},
+	{"PCIERC1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	714},
+	{"PCIERC0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	715},
+	{"PCIERC1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	715},
+	{"PCIERC0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	716},
+	{"PCIERC1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	716},
+	{"PCIERC0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	717},
+	{"PCIERC1_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	717},
+	{"PCIERC0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	718},
+	{"PCIERC1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	718},
+	{"PCIERC0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	719},
+	{"PCIERC1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	719},
+	{"PCIERC0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	720},
+	{"PCIERC1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	720},
+	{"PCIERC0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	721},
+	{"PCIERC1_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	721},
+	{"PCIERC0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	722},
+	{"PCIERC1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	722},
+	{"PCIERC0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	723},
+	{"PCIERC1_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	723},
+	{"PCIERC0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	724},
+	{"PCIERC1_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	724},
+	{"PCIERC0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	725},
+	{"PCIERC1_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	725},
+	{"PCIERC0_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	726},
+	{"PCIERC1_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	726},
+	{"PCIERC0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	727},
+	{"PCIERC1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	727},
+	{"PCIERC0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	728},
+	{"PCIERC1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	728},
+	{"PCM0_DMA_CFG"                ,	   0x1070000010018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	729},
+	{"PCM1_DMA_CFG"                ,	   0x1070000014018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	729},
+	{"PCM2_DMA_CFG"                ,	   0x1070000018018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	729},
+	{"PCM3_DMA_CFG"                ,	   0x107000001c018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	729},
+	{"PCM0_INT_ENA"                ,	   0x1070000010020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	730},
+	{"PCM1_INT_ENA"                ,	   0x1070000014020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	730},
+	{"PCM2_INT_ENA"                ,	   0x1070000018020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	730},
+	{"PCM3_INT_ENA"                ,	   0x107000001c020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	730},
+	{"PCM0_INT_SUM"                ,	   0x1070000010028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	731},
+	{"PCM1_INT_SUM"                ,	   0x1070000014028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	731},
+	{"PCM2_INT_SUM"                ,	   0x1070000018028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	731},
+	{"PCM3_INT_SUM"                ,	   0x107000001c028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	731},
+	{"PCM0_RXADDR"                 ,	   0x1070000010068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	732},
+	{"PCM1_RXADDR"                 ,	   0x1070000014068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	732},
+	{"PCM2_RXADDR"                 ,	   0x1070000018068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	732},
+	{"PCM3_RXADDR"                 ,	   0x107000001c068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	732},
+	{"PCM0_RXCNT"                  ,	   0x1070000010060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	733},
+	{"PCM1_RXCNT"                  ,	   0x1070000014060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	733},
+	{"PCM2_RXCNT"                  ,	   0x1070000018060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	733},
+	{"PCM3_RXCNT"                  ,	   0x107000001c060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	733},
+	{"PCM0_RXMSK0"                 ,	   0x10700000100c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	734},
+	{"PCM1_RXMSK0"                 ,	   0x10700000140c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	734},
+	{"PCM2_RXMSK0"                 ,	   0x10700000180c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	734},
+	{"PCM3_RXMSK0"                 ,	   0x107000001c0c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	734},
+	{"PCM0_RXMSK1"                 ,	   0x10700000100c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	735},
+	{"PCM1_RXMSK1"                 ,	   0x10700000140c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	735},
+	{"PCM2_RXMSK1"                 ,	   0x10700000180c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	735},
+	{"PCM3_RXMSK1"                 ,	   0x107000001c0c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	735},
+	{"PCM0_RXMSK2"                 ,	   0x10700000100d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	736},
+	{"PCM1_RXMSK2"                 ,	   0x10700000140d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	736},
+	{"PCM2_RXMSK2"                 ,	   0x10700000180d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	736},
+	{"PCM3_RXMSK2"                 ,	   0x107000001c0d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	736},
+	{"PCM0_RXMSK3"                 ,	   0x10700000100d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	737},
+	{"PCM1_RXMSK3"                 ,	   0x10700000140d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	737},
+	{"PCM2_RXMSK3"                 ,	   0x10700000180d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	737},
+	{"PCM3_RXMSK3"                 ,	   0x107000001c0d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	737},
+	{"PCM0_RXMSK4"                 ,	   0x10700000100e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	738},
+	{"PCM1_RXMSK4"                 ,	   0x10700000140e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	738},
+	{"PCM2_RXMSK4"                 ,	   0x10700000180e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	738},
+	{"PCM3_RXMSK4"                 ,	   0x107000001c0e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	738},
+	{"PCM0_RXMSK5"                 ,	   0x10700000100e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	739},
+	{"PCM1_RXMSK5"                 ,	   0x10700000140e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	739},
+	{"PCM2_RXMSK5"                 ,	   0x10700000180e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	739},
+	{"PCM3_RXMSK5"                 ,	   0x107000001c0e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	739},
+	{"PCM0_RXMSK6"                 ,	   0x10700000100f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	740},
+	{"PCM1_RXMSK6"                 ,	   0x10700000140f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	740},
+	{"PCM2_RXMSK6"                 ,	   0x10700000180f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	740},
+	{"PCM3_RXMSK6"                 ,	   0x107000001c0f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	740},
+	{"PCM0_RXMSK7"                 ,	   0x10700000100f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	741},
+	{"PCM1_RXMSK7"                 ,	   0x10700000140f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	741},
+	{"PCM2_RXMSK7"                 ,	   0x10700000180f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	741},
+	{"PCM3_RXMSK7"                 ,	   0x107000001c0f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	741},
+	{"PCM0_RXSTART"                ,	   0x1070000010058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	742},
+	{"PCM1_RXSTART"                ,	   0x1070000014058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	742},
+	{"PCM2_RXSTART"                ,	   0x1070000018058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	742},
+	{"PCM3_RXSTART"                ,	   0x107000001c058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	742},
+	{"PCM0_TDM_CFG"                ,	   0x1070000010010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	743},
+	{"PCM1_TDM_CFG"                ,	   0x1070000014010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	743},
+	{"PCM2_TDM_CFG"                ,	   0x1070000018010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	743},
+	{"PCM3_TDM_CFG"                ,	   0x107000001c010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	743},
+	{"PCM0_TDM_DBG"                ,	   0x1070000010030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"PCM1_TDM_DBG"                ,	   0x1070000014030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"PCM2_TDM_DBG"                ,	   0x1070000018030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"PCM3_TDM_DBG"                ,	   0x107000001c030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"PCM0_TXADDR"                 ,	   0x1070000010050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	745},
+	{"PCM1_TXADDR"                 ,	   0x1070000014050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	745},
+	{"PCM2_TXADDR"                 ,	   0x1070000018050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	745},
+	{"PCM3_TXADDR"                 ,	   0x107000001c050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	745},
+	{"PCM0_TXCNT"                  ,	   0x1070000010048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	746},
+	{"PCM1_TXCNT"                  ,	   0x1070000014048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	746},
+	{"PCM2_TXCNT"                  ,	   0x1070000018048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	746},
+	{"PCM3_TXCNT"                  ,	   0x107000001c048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	746},
+	{"PCM0_TXMSK0"                 ,	   0x1070000010080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	747},
+	{"PCM1_TXMSK0"                 ,	   0x1070000014080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	747},
+	{"PCM2_TXMSK0"                 ,	   0x1070000018080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	747},
+	{"PCM3_TXMSK0"                 ,	   0x107000001c080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	747},
+	{"PCM0_TXMSK1"                 ,	   0x1070000010088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
+	{"PCM1_TXMSK1"                 ,	   0x1070000014088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
+	{"PCM2_TXMSK1"                 ,	   0x1070000018088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
+	{"PCM3_TXMSK1"                 ,	   0x107000001c088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
+	{"PCM0_TXMSK2"                 ,	   0x1070000010090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"PCM1_TXMSK2"                 ,	   0x1070000014090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"PCM2_TXMSK2"                 ,	   0x1070000018090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"PCM3_TXMSK2"                 ,	   0x107000001c090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"PCM0_TXMSK3"                 ,	   0x1070000010098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
+	{"PCM1_TXMSK3"                 ,	   0x1070000014098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
+	{"PCM2_TXMSK3"                 ,	   0x1070000018098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
+	{"PCM3_TXMSK3"                 ,	   0x107000001c098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
+	{"PCM0_TXMSK4"                 ,	   0x10700000100a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	751},
+	{"PCM1_TXMSK4"                 ,	   0x10700000140a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	751},
+	{"PCM2_TXMSK4"                 ,	   0x10700000180a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	751},
+	{"PCM3_TXMSK4"                 ,	   0x107000001c0a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	751},
+	{"PCM0_TXMSK5"                 ,	   0x10700000100a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	752},
+	{"PCM1_TXMSK5"                 ,	   0x10700000140a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	752},
+	{"PCM2_TXMSK5"                 ,	   0x10700000180a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	752},
+	{"PCM3_TXMSK5"                 ,	   0x107000001c0a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	752},
+	{"PCM0_TXMSK6"                 ,	   0x10700000100b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"PCM1_TXMSK6"                 ,	   0x10700000140b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"PCM2_TXMSK6"                 ,	   0x10700000180b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"PCM3_TXMSK6"                 ,	   0x107000001c0b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"PCM0_TXMSK7"                 ,	   0x10700000100b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	754},
+	{"PCM1_TXMSK7"                 ,	   0x10700000140b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	754},
+	{"PCM2_TXMSK7"                 ,	   0x10700000180b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	754},
+	{"PCM3_TXMSK7"                 ,	   0x107000001c0b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	754},
+	{"PCM0_TXSTART"                ,	   0x1070000010040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"PCM1_TXSTART"                ,	   0x1070000014040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"PCM2_TXSTART"                ,	   0x1070000018040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"PCM3_TXSTART"                ,	   0x107000001c040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"PCM_CLK0_CFG"                ,	   0x1070000010000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	756},
+	{"PCM_CLK1_CFG"                ,	   0x1070000014000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	756},
+	{"PCM_CLK0_DBG"                ,	   0x1070000010038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"PCM_CLK1_DBG"                ,	   0x1070000014038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"PCM_CLK0_GEN"                ,	   0x1070000010008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"PCM_CLK1_GEN"                ,	   0x1070000014008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"PCS0_AN000_ADV_REG"          ,	   0x11800b0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PCS0_AN001_ADV_REG"          ,	   0x11800b0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PCS0_AN002_ADV_REG"          ,	   0x11800b0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PCS0_AN003_ADV_REG"          ,	   0x11800b0001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PCS1_AN000_ADV_REG"          ,	   0x11800b8001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PCS1_AN001_ADV_REG"          ,	   0x11800b8001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PCS1_AN002_ADV_REG"          ,	   0x11800b8001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PCS1_AN003_ADV_REG"          ,	   0x11800b8001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800b0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800b0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PCS0_AN002_EXT_ST_REG"       ,	   0x11800b0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PCS0_AN003_EXT_ST_REG"       ,	   0x11800b0001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PCS1_AN000_EXT_ST_REG"       ,	   0x11800b8001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PCS1_AN001_EXT_ST_REG"       ,	   0x11800b8001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PCS1_AN002_EXT_ST_REG"       ,	   0x11800b8001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PCS1_AN003_EXT_ST_REG"       ,	   0x11800b8001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800b0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800b0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PCS0_AN002_LP_ABIL_REG"      ,	   0x11800b0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PCS0_AN003_LP_ABIL_REG"      ,	   0x11800b0001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PCS1_AN000_LP_ABIL_REG"      ,	   0x11800b8001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PCS1_AN001_LP_ABIL_REG"      ,	   0x11800b8001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PCS1_AN002_LP_ABIL_REG"      ,	   0x11800b8001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PCS1_AN003_LP_ABIL_REG"      ,	   0x11800b8001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800b0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800b0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PCS0_AN002_RESULTS_REG"      ,	   0x11800b0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PCS0_AN003_RESULTS_REG"      ,	   0x11800b0001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PCS1_AN000_RESULTS_REG"      ,	   0x11800b8001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PCS1_AN001_RESULTS_REG"      ,	   0x11800b8001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PCS1_AN002_RESULTS_REG"      ,	   0x11800b8001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PCS1_AN003_RESULTS_REG"      ,	   0x11800b8001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PCS0_INT000_EN_REG"          ,	   0x11800b0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PCS0_INT001_EN_REG"          ,	   0x11800b0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PCS0_INT002_EN_REG"          ,	   0x11800b0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PCS0_INT003_EN_REG"          ,	   0x11800b0001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PCS1_INT000_EN_REG"          ,	   0x11800b8001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PCS1_INT001_EN_REG"          ,	   0x11800b8001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PCS1_INT002_EN_REG"          ,	   0x11800b8001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PCS1_INT003_EN_REG"          ,	   0x11800b8001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PCS0_INT000_REG"             ,	   0x11800b0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PCS0_INT001_REG"             ,	   0x11800b0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PCS0_INT002_REG"             ,	   0x11800b0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PCS0_INT003_REG"             ,	   0x11800b0001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PCS1_INT000_REG"             ,	   0x11800b8001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PCS1_INT001_REG"             ,	   0x11800b8001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PCS1_INT002_REG"             ,	   0x11800b8001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PCS1_INT003_REG"             ,	   0x11800b8001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800b0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800b0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PCS0_LINK002_TIMER_COUNT_REG",	   0x11800b0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PCS0_LINK003_TIMER_COUNT_REG",	   0x11800b0001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PCS1_LINK000_TIMER_COUNT_REG",	   0x11800b8001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PCS1_LINK001_TIMER_COUNT_REG",	   0x11800b8001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PCS1_LINK002_TIMER_COUNT_REG",	   0x11800b8001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PCS1_LINK003_TIMER_COUNT_REG",	   0x11800b8001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PCS0_LOG_ANL000_REG"         ,	   0x11800b0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PCS0_LOG_ANL001_REG"         ,	   0x11800b0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PCS0_LOG_ANL002_REG"         ,	   0x11800b0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PCS0_LOG_ANL003_REG"         ,	   0x11800b0001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PCS1_LOG_ANL000_REG"         ,	   0x11800b8001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PCS1_LOG_ANL001_REG"         ,	   0x11800b8001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PCS1_LOG_ANL002_REG"         ,	   0x11800b8001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PCS1_LOG_ANL003_REG"         ,	   0x11800b8001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PCS0_MISC000_CTL_REG"        ,	   0x11800b0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PCS0_MISC001_CTL_REG"        ,	   0x11800b0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PCS0_MISC002_CTL_REG"        ,	   0x11800b0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PCS0_MISC003_CTL_REG"        ,	   0x11800b0001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PCS1_MISC000_CTL_REG"        ,	   0x11800b8001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PCS1_MISC001_CTL_REG"        ,	   0x11800b8001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PCS1_MISC002_CTL_REG"        ,	   0x11800b8001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PCS1_MISC003_CTL_REG"        ,	   0x11800b8001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800b0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800b0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PCS0_MR002_CONTROL_REG"      ,	   0x11800b0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PCS0_MR003_CONTROL_REG"      ,	   0x11800b0001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PCS1_MR000_CONTROL_REG"      ,	   0x11800b8001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PCS1_MR001_CONTROL_REG"      ,	   0x11800b8001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PCS1_MR002_CONTROL_REG"      ,	   0x11800b8001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PCS1_MR003_CONTROL_REG"      ,	   0x11800b8001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PCS0_MR000_STATUS_REG"       ,	   0x11800b0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PCS0_MR001_STATUS_REG"       ,	   0x11800b0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PCS0_MR002_STATUS_REG"       ,	   0x11800b0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PCS0_MR003_STATUS_REG"       ,	   0x11800b0001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PCS1_MR000_STATUS_REG"       ,	   0x11800b8001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PCS1_MR001_STATUS_REG"       ,	   0x11800b8001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PCS1_MR002_STATUS_REG"       ,	   0x11800b8001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PCS1_MR003_STATUS_REG"       ,	   0x11800b8001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PCS0_RX000_STATES_REG"       ,	   0x11800b0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PCS0_RX001_STATES_REG"       ,	   0x11800b0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PCS0_RX002_STATES_REG"       ,	   0x11800b0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PCS0_RX003_STATES_REG"       ,	   0x11800b0001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PCS1_RX000_STATES_REG"       ,	   0x11800b8001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PCS1_RX001_STATES_REG"       ,	   0x11800b8001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PCS1_RX002_STATES_REG"       ,	   0x11800b8001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PCS1_RX003_STATES_REG"       ,	   0x11800b8001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PCS0_RX000_SYNC_REG"         ,	   0x11800b0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PCS0_RX001_SYNC_REG"         ,	   0x11800b0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PCS0_RX002_SYNC_REG"         ,	   0x11800b0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PCS0_RX003_SYNC_REG"         ,	   0x11800b0001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PCS1_RX000_SYNC_REG"         ,	   0x11800b8001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PCS1_RX001_SYNC_REG"         ,	   0x11800b8001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PCS1_RX002_SYNC_REG"         ,	   0x11800b8001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PCS1_RX003_SYNC_REG"         ,	   0x11800b8001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800b0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800b0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PCS0_SGM002_AN_ADV_REG"      ,	   0x11800b0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PCS0_SGM003_AN_ADV_REG"      ,	   0x11800b0001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PCS1_SGM000_AN_ADV_REG"      ,	   0x11800b8001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PCS1_SGM001_AN_ADV_REG"      ,	   0x11800b8001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PCS1_SGM002_AN_ADV_REG"      ,	   0x11800b8001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PCS1_SGM003_AN_ADV_REG"      ,	   0x11800b8001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800b0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800b0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PCS0_SGM002_LP_ADV_REG"      ,	   0x11800b0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PCS0_SGM003_LP_ADV_REG"      ,	   0x11800b0001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PCS1_SGM000_LP_ADV_REG"      ,	   0x11800b8001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PCS1_SGM001_LP_ADV_REG"      ,	   0x11800b8001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PCS1_SGM002_LP_ADV_REG"      ,	   0x11800b8001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PCS1_SGM003_LP_ADV_REG"      ,	   0x11800b8001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PCS0_TX000_STATES_REG"       ,	   0x11800b0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PCS0_TX001_STATES_REG"       ,	   0x11800b0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PCS0_TX002_STATES_REG"       ,	   0x11800b0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PCS0_TX003_STATES_REG"       ,	   0x11800b0001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PCS1_TX000_STATES_REG"       ,	   0x11800b8001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PCS1_TX001_STATES_REG"       ,	   0x11800b8001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PCS1_TX002_STATES_REG"       ,	   0x11800b8001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PCS1_TX003_STATES_REG"       ,	   0x11800b8001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800b0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800b0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PCS0_TX_RX002_POLARITY_REG"  ,	   0x11800b0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PCS0_TX_RX003_POLARITY_REG"  ,	   0x11800b0001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PCS1_TX_RX000_POLARITY_REG"  ,	   0x11800b8001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PCS1_TX_RX001_POLARITY_REG"  ,	   0x11800b8001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PCS1_TX_RX002_POLARITY_REG"  ,	   0x11800b8001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PCS1_TX_RX003_POLARITY_REG"  ,	   0x11800b8001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PCSX0_10GBX_STATUS_REG"      ,	   0x11800b0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PCSX1_10GBX_STATUS_REG"      ,	   0x11800b8000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PCSX0_BIST_STATUS_REG"       ,	   0x11800b0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PCSX1_BIST_STATUS_REG"       ,	   0x11800b8000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PCSX0_BIT_LOCK_STATUS_REG"   ,	   0x11800b0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PCSX1_BIT_LOCK_STATUS_REG"   ,	   0x11800b8000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PCSX0_CONTROL1_REG"          ,	   0x11800b0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PCSX1_CONTROL1_REG"          ,	   0x11800b8000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PCSX0_CONTROL2_REG"          ,	   0x11800b0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PCSX1_CONTROL2_REG"          ,	   0x11800b8000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PCSX0_INT_EN_REG"            ,	   0x11800b0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PCSX1_INT_EN_REG"            ,	   0x11800b8000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PCSX0_INT_REG"               ,	   0x11800b0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PCSX1_INT_REG"               ,	   0x11800b8000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PCSX0_LOG_ANL_REG"           ,	   0x11800b0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PCSX1_LOG_ANL_REG"           ,	   0x11800b8000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PCSX0_MISC_CTL_REG"          ,	   0x11800b0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PCSX1_MISC_CTL_REG"          ,	   0x11800b8000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PCSX0_RX_SYNC_STATES_REG"    ,	   0x11800b0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PCSX1_RX_SYNC_STATES_REG"    ,	   0x11800b8000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PCSX0_SPD_ABIL_REG"          ,	   0x11800b0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PCSX1_SPD_ABIL_REG"          ,	   0x11800b8000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PCSX0_STATUS1_REG"           ,	   0x11800b0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PCSX1_STATUS1_REG"           ,	   0x11800b8000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PCSX0_STATUS2_REG"           ,	   0x11800b0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PCSX1_STATUS2_REG"           ,	   0x11800b8000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PCSX0_TX_RX_POLARITY_REG"    ,	   0x11800b0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PCSX1_TX_RX_POLARITY_REG"    ,	   0x11800b8000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PCSX0_TX_RX_STATES_REG"      ,	   0x11800b0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PCSX1_TX_RX_STATES_REG"      ,	   0x11800b8000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PEM0_BAR1_INDEX000"          ,	   0x11800c00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM0_BAR1_INDEX001"          ,	   0x11800c00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM0_BAR1_INDEX002"          ,	   0x11800c00000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM0_BAR1_INDEX003"          ,	   0x11800c00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM0_BAR1_INDEX004"          ,	   0x11800c00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM0_BAR1_INDEX005"          ,	   0x11800c00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM0_BAR1_INDEX006"          ,	   0x11800c00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM0_BAR1_INDEX007"          ,	   0x11800c00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM0_BAR1_INDEX008"          ,	   0x11800c00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM0_BAR1_INDEX009"          ,	   0x11800c00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM0_BAR1_INDEX010"          ,	   0x11800c00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM0_BAR1_INDEX011"          ,	   0x11800c0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM0_BAR1_INDEX012"          ,	   0x11800c0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM0_BAR1_INDEX013"          ,	   0x11800c0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM0_BAR1_INDEX014"          ,	   0x11800c0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM0_BAR1_INDEX015"          ,	   0x11800c0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM1_BAR1_INDEX000"          ,	   0x11800c10000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM1_BAR1_INDEX001"          ,	   0x11800c10000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM1_BAR1_INDEX002"          ,	   0x11800c10000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM1_BAR1_INDEX003"          ,	   0x11800c10000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM1_BAR1_INDEX004"          ,	   0x11800c10000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM1_BAR1_INDEX005"          ,	   0x11800c10000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM1_BAR1_INDEX006"          ,	   0x11800c10000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM1_BAR1_INDEX007"          ,	   0x11800c10000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM1_BAR1_INDEX008"          ,	   0x11800c10000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM1_BAR1_INDEX009"          ,	   0x11800c10000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM1_BAR1_INDEX010"          ,	   0x11800c10000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM1_BAR1_INDEX011"          ,	   0x11800c1000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM1_BAR1_INDEX012"          ,	   0x11800c1000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM1_BAR1_INDEX013"          ,	   0x11800c1000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM1_BAR1_INDEX014"          ,	   0x11800c1000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM1_BAR1_INDEX015"          ,	   0x11800c1000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM0_BAR2_MASK"              ,	   0x11800c0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PEM1_BAR2_MASK"              ,	   0x11800c1000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PEM0_BAR_CTL"                ,	   0x11800c0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PEM1_BAR_CTL"                ,	   0x11800c1000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PEM0_BIST_STATUS"            ,	   0x11800c0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PEM1_BIST_STATUS"            ,	   0x11800c1000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PEM0_BIST_STATUS2"           ,	   0x11800c0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"PEM1_BIST_STATUS2"           ,	   0x11800c1000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"PEM0_CFG_RD"                 ,	   0x11800c0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PEM1_CFG_RD"                 ,	   0x11800c1000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PEM0_CFG_WR"                 ,	   0x11800c0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PEM1_CFG_WR"                 ,	   0x11800c1000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PEM0_CPL_LUT_VALID"          ,	   0x11800c0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PEM1_CPL_LUT_VALID"          ,	   0x11800c1000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PEM0_CTL_STATUS"             ,	   0x11800c0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PEM1_CTL_STATUS"             ,	   0x11800c1000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PEM0_DBG_INFO"               ,	   0x11800c0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PEM1_DBG_INFO"               ,	   0x11800c1000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PEM0_DBG_INFO_EN"            ,	   0x11800c00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"PEM1_DBG_INFO_EN"            ,	   0x11800c10000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"PEM0_DIAG_STATUS"            ,	   0x11800c0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"PEM1_DIAG_STATUS"            ,	   0x11800c1000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"PEM0_INB_READ_CREDITS"       ,	   0x11800c0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"PEM1_INB_READ_CREDITS"       ,	   0x11800c1000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"PEM0_INT_ENB"                ,	   0x11800c0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"PEM1_INT_ENB"                ,	   0x11800c1000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"PEM0_INT_ENB_INT"            ,	   0x11800c0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"PEM1_INT_ENB_INT"            ,	   0x11800c1000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"PEM0_INT_SUM"                ,	   0x11800c0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
+	{"PEM1_INT_SUM"                ,	   0x11800c1000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
+	{"PEM0_P2N_BAR0_START"         ,	   0x11800c0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"PEM1_P2N_BAR0_START"         ,	   0x11800c1000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"PEM0_P2N_BAR1_START"         ,	   0x11800c0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"PEM1_P2N_BAR1_START"         ,	   0x11800c1000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"PEM0_P2N_BAR2_START"         ,	   0x11800c0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
+	{"PEM1_P2N_BAR2_START"         ,	   0x11800c1000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
+	{"PEM0_TLP_CREDITS"            ,	   0x11800c0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
+	{"PEM1_TLP_CREDITS"            ,	   0x11800c1000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
+	{"PIP_ALT_SKIP_CFG0"           ,	   0x11800a0002a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
+	{"PIP_ALT_SKIP_CFG1"           ,	   0x11800a0002a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
+	{"PIP_ALT_SKIP_CFG2"           ,	   0x11800a0002a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
+	{"PIP_ALT_SKIP_CFG3"           ,	   0x11800a0002a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
+	{"PIP_BCK_PRS"                 ,	   0x11800a0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
+	{"PIP_BIST_STATUS"             ,	   0x11800a0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
+	{"PIP_BSEL_EXT_CFG0"           ,	   0x11800a0002800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"PIP_BSEL_EXT_CFG1"           ,	   0x11800a0002810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"PIP_BSEL_EXT_CFG2"           ,	   0x11800a0002820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"PIP_BSEL_EXT_CFG3"           ,	   0x11800a0002830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"PIP_BSEL_EXT_POS0"           ,	   0x11800a0002808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
+	{"PIP_BSEL_EXT_POS1"           ,	   0x11800a0002818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
+	{"PIP_BSEL_EXT_POS2"           ,	   0x11800a0002828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
+	{"PIP_BSEL_EXT_POS3"           ,	   0x11800a0002838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
+	{"PIP_BSEL_TBL_ENT0"           ,	   0x11800a0003000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT1"           ,	   0x11800a0003008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT2"           ,	   0x11800a0003010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT3"           ,	   0x11800a0003018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT4"           ,	   0x11800a0003020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT5"           ,	   0x11800a0003028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT6"           ,	   0x11800a0003030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT7"           ,	   0x11800a0003038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT8"           ,	   0x11800a0003040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT9"           ,	   0x11800a0003048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT10"          ,	   0x11800a0003050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT11"          ,	   0x11800a0003058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT12"          ,	   0x11800a0003060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT13"          ,	   0x11800a0003068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT14"          ,	   0x11800a0003070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT15"          ,	   0x11800a0003078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT16"          ,	   0x11800a0003080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT17"          ,	   0x11800a0003088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT18"          ,	   0x11800a0003090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT19"          ,	   0x11800a0003098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT20"          ,	   0x11800a00030a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT21"          ,	   0x11800a00030a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT22"          ,	   0x11800a00030b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT23"          ,	   0x11800a00030b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT24"          ,	   0x11800a00030c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT25"          ,	   0x11800a00030c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT26"          ,	   0x11800a00030d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT27"          ,	   0x11800a00030d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT28"          ,	   0x11800a00030e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT29"          ,	   0x11800a00030e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT30"          ,	   0x11800a00030f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT31"          ,	   0x11800a00030f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT32"          ,	   0x11800a0003100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT33"          ,	   0x11800a0003108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT34"          ,	   0x11800a0003110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT35"          ,	   0x11800a0003118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT36"          ,	   0x11800a0003120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT37"          ,	   0x11800a0003128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT38"          ,	   0x11800a0003130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT39"          ,	   0x11800a0003138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT40"          ,	   0x11800a0003140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT41"          ,	   0x11800a0003148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT42"          ,	   0x11800a0003150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT43"          ,	   0x11800a0003158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT44"          ,	   0x11800a0003160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT45"          ,	   0x11800a0003168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT46"          ,	   0x11800a0003170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT47"          ,	   0x11800a0003178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT48"          ,	   0x11800a0003180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT49"          ,	   0x11800a0003188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT50"          ,	   0x11800a0003190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT51"          ,	   0x11800a0003198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT52"          ,	   0x11800a00031a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT53"          ,	   0x11800a00031a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT54"          ,	   0x11800a00031b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT55"          ,	   0x11800a00031b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT56"          ,	   0x11800a00031c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT57"          ,	   0x11800a00031c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT58"          ,	   0x11800a00031d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT59"          ,	   0x11800a00031d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT60"          ,	   0x11800a00031e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT61"          ,	   0x11800a00031e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT62"          ,	   0x11800a00031f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT63"          ,	   0x11800a00031f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT64"          ,	   0x11800a0003200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT65"          ,	   0x11800a0003208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT66"          ,	   0x11800a0003210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT67"          ,	   0x11800a0003218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT68"          ,	   0x11800a0003220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT69"          ,	   0x11800a0003228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT70"          ,	   0x11800a0003230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT71"          ,	   0x11800a0003238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT72"          ,	   0x11800a0003240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT73"          ,	   0x11800a0003248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT74"          ,	   0x11800a0003250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT75"          ,	   0x11800a0003258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT76"          ,	   0x11800a0003260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT77"          ,	   0x11800a0003268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT78"          ,	   0x11800a0003270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT79"          ,	   0x11800a0003278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT80"          ,	   0x11800a0003280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT81"          ,	   0x11800a0003288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT82"          ,	   0x11800a0003290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT83"          ,	   0x11800a0003298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT84"          ,	   0x11800a00032a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT85"          ,	   0x11800a00032a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT86"          ,	   0x11800a00032b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT87"          ,	   0x11800a00032b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT88"          ,	   0x11800a00032c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT89"          ,	   0x11800a00032c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT90"          ,	   0x11800a00032d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT91"          ,	   0x11800a00032d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT92"          ,	   0x11800a00032e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT93"          ,	   0x11800a00032e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT94"          ,	   0x11800a00032f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT95"          ,	   0x11800a00032f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT96"          ,	   0x11800a0003300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT97"          ,	   0x11800a0003308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT98"          ,	   0x11800a0003310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT99"          ,	   0x11800a0003318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT100"         ,	   0x11800a0003320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT101"         ,	   0x11800a0003328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT102"         ,	   0x11800a0003330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT103"         ,	   0x11800a0003338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT104"         ,	   0x11800a0003340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT105"         ,	   0x11800a0003348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT106"         ,	   0x11800a0003350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT107"         ,	   0x11800a0003358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT108"         ,	   0x11800a0003360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT109"         ,	   0x11800a0003368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT110"         ,	   0x11800a0003370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT111"         ,	   0x11800a0003378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT112"         ,	   0x11800a0003380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT113"         ,	   0x11800a0003388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT114"         ,	   0x11800a0003390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT115"         ,	   0x11800a0003398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT116"         ,	   0x11800a00033a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT117"         ,	   0x11800a00033a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT118"         ,	   0x11800a00033b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT119"         ,	   0x11800a00033b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT120"         ,	   0x11800a00033c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT121"         ,	   0x11800a00033c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT122"         ,	   0x11800a00033d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT123"         ,	   0x11800a00033d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT124"         ,	   0x11800a00033e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT125"         ,	   0x11800a00033e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT126"         ,	   0x11800a00033f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT127"         ,	   0x11800a00033f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT128"         ,	   0x11800a0003400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT129"         ,	   0x11800a0003408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT130"         ,	   0x11800a0003410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT131"         ,	   0x11800a0003418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT132"         ,	   0x11800a0003420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT133"         ,	   0x11800a0003428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT134"         ,	   0x11800a0003430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT135"         ,	   0x11800a0003438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT136"         ,	   0x11800a0003440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT137"         ,	   0x11800a0003448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT138"         ,	   0x11800a0003450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT139"         ,	   0x11800a0003458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT140"         ,	   0x11800a0003460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT141"         ,	   0x11800a0003468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT142"         ,	   0x11800a0003470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT143"         ,	   0x11800a0003478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT144"         ,	   0x11800a0003480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT145"         ,	   0x11800a0003488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT146"         ,	   0x11800a0003490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT147"         ,	   0x11800a0003498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT148"         ,	   0x11800a00034a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT149"         ,	   0x11800a00034a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT150"         ,	   0x11800a00034b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT151"         ,	   0x11800a00034b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT152"         ,	   0x11800a00034c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT153"         ,	   0x11800a00034c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT154"         ,	   0x11800a00034d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT155"         ,	   0x11800a00034d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT156"         ,	   0x11800a00034e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT157"         ,	   0x11800a00034e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT158"         ,	   0x11800a00034f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT159"         ,	   0x11800a00034f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT160"         ,	   0x11800a0003500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT161"         ,	   0x11800a0003508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT162"         ,	   0x11800a0003510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT163"         ,	   0x11800a0003518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT164"         ,	   0x11800a0003520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT165"         ,	   0x11800a0003528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT166"         ,	   0x11800a0003530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT167"         ,	   0x11800a0003538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT168"         ,	   0x11800a0003540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT169"         ,	   0x11800a0003548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT170"         ,	   0x11800a0003550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT171"         ,	   0x11800a0003558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT172"         ,	   0x11800a0003560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT173"         ,	   0x11800a0003568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT174"         ,	   0x11800a0003570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT175"         ,	   0x11800a0003578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT176"         ,	   0x11800a0003580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT177"         ,	   0x11800a0003588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT178"         ,	   0x11800a0003590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT179"         ,	   0x11800a0003598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT180"         ,	   0x11800a00035a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT181"         ,	   0x11800a00035a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT182"         ,	   0x11800a00035b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT183"         ,	   0x11800a00035b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT184"         ,	   0x11800a00035c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT185"         ,	   0x11800a00035c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT186"         ,	   0x11800a00035d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT187"         ,	   0x11800a00035d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT188"         ,	   0x11800a00035e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT189"         ,	   0x11800a00035e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT190"         ,	   0x11800a00035f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT191"         ,	   0x11800a00035f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT192"         ,	   0x11800a0003600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT193"         ,	   0x11800a0003608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT194"         ,	   0x11800a0003610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT195"         ,	   0x11800a0003618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT196"         ,	   0x11800a0003620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT197"         ,	   0x11800a0003628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT198"         ,	   0x11800a0003630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT199"         ,	   0x11800a0003638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT200"         ,	   0x11800a0003640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT201"         ,	   0x11800a0003648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT202"         ,	   0x11800a0003650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT203"         ,	   0x11800a0003658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT204"         ,	   0x11800a0003660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT205"         ,	   0x11800a0003668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT206"         ,	   0x11800a0003670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT207"         ,	   0x11800a0003678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT208"         ,	   0x11800a0003680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT209"         ,	   0x11800a0003688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT210"         ,	   0x11800a0003690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT211"         ,	   0x11800a0003698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT212"         ,	   0x11800a00036a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT213"         ,	   0x11800a00036a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT214"         ,	   0x11800a00036b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT215"         ,	   0x11800a00036b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT216"         ,	   0x11800a00036c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT217"         ,	   0x11800a00036c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT218"         ,	   0x11800a00036d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT219"         ,	   0x11800a00036d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT220"         ,	   0x11800a00036e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT221"         ,	   0x11800a00036e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT222"         ,	   0x11800a00036f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT223"         ,	   0x11800a00036f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT224"         ,	   0x11800a0003700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT225"         ,	   0x11800a0003708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT226"         ,	   0x11800a0003710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT227"         ,	   0x11800a0003718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT228"         ,	   0x11800a0003720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT229"         ,	   0x11800a0003728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT230"         ,	   0x11800a0003730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT231"         ,	   0x11800a0003738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT232"         ,	   0x11800a0003740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT233"         ,	   0x11800a0003748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT234"         ,	   0x11800a0003750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT235"         ,	   0x11800a0003758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT236"         ,	   0x11800a0003760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT237"         ,	   0x11800a0003768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT238"         ,	   0x11800a0003770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT239"         ,	   0x11800a0003778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT240"         ,	   0x11800a0003780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT241"         ,	   0x11800a0003788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT242"         ,	   0x11800a0003790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT243"         ,	   0x11800a0003798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT244"         ,	   0x11800a00037a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT245"         ,	   0x11800a00037a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT246"         ,	   0x11800a00037b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT247"         ,	   0x11800a00037b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT248"         ,	   0x11800a00037c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT249"         ,	   0x11800a00037c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT250"         ,	   0x11800a00037d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT251"         ,	   0x11800a00037d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT252"         ,	   0x11800a00037e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT253"         ,	   0x11800a00037e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT254"         ,	   0x11800a00037f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT255"         ,	   0x11800a00037f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT256"         ,	   0x11800a0003800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT257"         ,	   0x11800a0003808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT258"         ,	   0x11800a0003810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT259"         ,	   0x11800a0003818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT260"         ,	   0x11800a0003820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT261"         ,	   0x11800a0003828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT262"         ,	   0x11800a0003830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT263"         ,	   0x11800a0003838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT264"         ,	   0x11800a0003840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT265"         ,	   0x11800a0003848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT266"         ,	   0x11800a0003850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT267"         ,	   0x11800a0003858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT268"         ,	   0x11800a0003860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT269"         ,	   0x11800a0003868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT270"         ,	   0x11800a0003870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT271"         ,	   0x11800a0003878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT272"         ,	   0x11800a0003880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT273"         ,	   0x11800a0003888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT274"         ,	   0x11800a0003890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT275"         ,	   0x11800a0003898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT276"         ,	   0x11800a00038a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT277"         ,	   0x11800a00038a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT278"         ,	   0x11800a00038b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT279"         ,	   0x11800a00038b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT280"         ,	   0x11800a00038c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT281"         ,	   0x11800a00038c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT282"         ,	   0x11800a00038d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT283"         ,	   0x11800a00038d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT284"         ,	   0x11800a00038e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT285"         ,	   0x11800a00038e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT286"         ,	   0x11800a00038f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT287"         ,	   0x11800a00038f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT288"         ,	   0x11800a0003900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT289"         ,	   0x11800a0003908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT290"         ,	   0x11800a0003910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT291"         ,	   0x11800a0003918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT292"         ,	   0x11800a0003920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT293"         ,	   0x11800a0003928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT294"         ,	   0x11800a0003930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT295"         ,	   0x11800a0003938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT296"         ,	   0x11800a0003940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT297"         ,	   0x11800a0003948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT298"         ,	   0x11800a0003950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT299"         ,	   0x11800a0003958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT300"         ,	   0x11800a0003960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT301"         ,	   0x11800a0003968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT302"         ,	   0x11800a0003970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT303"         ,	   0x11800a0003978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT304"         ,	   0x11800a0003980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT305"         ,	   0x11800a0003988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT306"         ,	   0x11800a0003990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT307"         ,	   0x11800a0003998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT308"         ,	   0x11800a00039a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT309"         ,	   0x11800a00039a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT310"         ,	   0x11800a00039b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT311"         ,	   0x11800a00039b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT312"         ,	   0x11800a00039c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT313"         ,	   0x11800a00039c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT314"         ,	   0x11800a00039d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT315"         ,	   0x11800a00039d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT316"         ,	   0x11800a00039e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT317"         ,	   0x11800a00039e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT318"         ,	   0x11800a00039f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT319"         ,	   0x11800a00039f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT320"         ,	   0x11800a0003a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT321"         ,	   0x11800a0003a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT322"         ,	   0x11800a0003a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT323"         ,	   0x11800a0003a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT324"         ,	   0x11800a0003a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT325"         ,	   0x11800a0003a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT326"         ,	   0x11800a0003a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT327"         ,	   0x11800a0003a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT328"         ,	   0x11800a0003a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT329"         ,	   0x11800a0003a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT330"         ,	   0x11800a0003a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT331"         ,	   0x11800a0003a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT332"         ,	   0x11800a0003a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT333"         ,	   0x11800a0003a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT334"         ,	   0x11800a0003a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT335"         ,	   0x11800a0003a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT336"         ,	   0x11800a0003a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT337"         ,	   0x11800a0003a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT338"         ,	   0x11800a0003a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT339"         ,	   0x11800a0003a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT340"         ,	   0x11800a0003aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT341"         ,	   0x11800a0003aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT342"         ,	   0x11800a0003ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT343"         ,	   0x11800a0003ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT344"         ,	   0x11800a0003ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT345"         ,	   0x11800a0003ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT346"         ,	   0x11800a0003ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT347"         ,	   0x11800a0003ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT348"         ,	   0x11800a0003ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT349"         ,	   0x11800a0003ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT350"         ,	   0x11800a0003af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT351"         ,	   0x11800a0003af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT352"         ,	   0x11800a0003b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT353"         ,	   0x11800a0003b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT354"         ,	   0x11800a0003b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT355"         ,	   0x11800a0003b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT356"         ,	   0x11800a0003b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT357"         ,	   0x11800a0003b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT358"         ,	   0x11800a0003b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT359"         ,	   0x11800a0003b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT360"         ,	   0x11800a0003b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT361"         ,	   0x11800a0003b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT362"         ,	   0x11800a0003b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT363"         ,	   0x11800a0003b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT364"         ,	   0x11800a0003b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT365"         ,	   0x11800a0003b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT366"         ,	   0x11800a0003b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT367"         ,	   0x11800a0003b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT368"         ,	   0x11800a0003b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT369"         ,	   0x11800a0003b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT370"         ,	   0x11800a0003b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT371"         ,	   0x11800a0003b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT372"         ,	   0x11800a0003ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT373"         ,	   0x11800a0003ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT374"         ,	   0x11800a0003bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT375"         ,	   0x11800a0003bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT376"         ,	   0x11800a0003bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT377"         ,	   0x11800a0003bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT378"         ,	   0x11800a0003bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT379"         ,	   0x11800a0003bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT380"         ,	   0x11800a0003be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT381"         ,	   0x11800a0003be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT382"         ,	   0x11800a0003bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT383"         ,	   0x11800a0003bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT384"         ,	   0x11800a0003c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT385"         ,	   0x11800a0003c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT386"         ,	   0x11800a0003c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT387"         ,	   0x11800a0003c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT388"         ,	   0x11800a0003c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT389"         ,	   0x11800a0003c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT390"         ,	   0x11800a0003c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT391"         ,	   0x11800a0003c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT392"         ,	   0x11800a0003c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT393"         ,	   0x11800a0003c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT394"         ,	   0x11800a0003c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT395"         ,	   0x11800a0003c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT396"         ,	   0x11800a0003c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT397"         ,	   0x11800a0003c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT398"         ,	   0x11800a0003c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT399"         ,	   0x11800a0003c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT400"         ,	   0x11800a0003c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT401"         ,	   0x11800a0003c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT402"         ,	   0x11800a0003c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT403"         ,	   0x11800a0003c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT404"         ,	   0x11800a0003ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT405"         ,	   0x11800a0003ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT406"         ,	   0x11800a0003cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT407"         ,	   0x11800a0003cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT408"         ,	   0x11800a0003cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT409"         ,	   0x11800a0003cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT410"         ,	   0x11800a0003cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT411"         ,	   0x11800a0003cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT412"         ,	   0x11800a0003ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT413"         ,	   0x11800a0003ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT414"         ,	   0x11800a0003cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT415"         ,	   0x11800a0003cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT416"         ,	   0x11800a0003d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT417"         ,	   0x11800a0003d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT418"         ,	   0x11800a0003d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT419"         ,	   0x11800a0003d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT420"         ,	   0x11800a0003d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT421"         ,	   0x11800a0003d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT422"         ,	   0x11800a0003d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT423"         ,	   0x11800a0003d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT424"         ,	   0x11800a0003d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT425"         ,	   0x11800a0003d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT426"         ,	   0x11800a0003d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT427"         ,	   0x11800a0003d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT428"         ,	   0x11800a0003d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT429"         ,	   0x11800a0003d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT430"         ,	   0x11800a0003d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT431"         ,	   0x11800a0003d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT432"         ,	   0x11800a0003d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT433"         ,	   0x11800a0003d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT434"         ,	   0x11800a0003d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT435"         ,	   0x11800a0003d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT436"         ,	   0x11800a0003da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT437"         ,	   0x11800a0003da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT438"         ,	   0x11800a0003db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT439"         ,	   0x11800a0003db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT440"         ,	   0x11800a0003dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT441"         ,	   0x11800a0003dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT442"         ,	   0x11800a0003dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT443"         ,	   0x11800a0003dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT444"         ,	   0x11800a0003de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT445"         ,	   0x11800a0003de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT446"         ,	   0x11800a0003df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT447"         ,	   0x11800a0003df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT448"         ,	   0x11800a0003e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT449"         ,	   0x11800a0003e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT450"         ,	   0x11800a0003e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT451"         ,	   0x11800a0003e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT452"         ,	   0x11800a0003e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT453"         ,	   0x11800a0003e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT454"         ,	   0x11800a0003e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT455"         ,	   0x11800a0003e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT456"         ,	   0x11800a0003e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT457"         ,	   0x11800a0003e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT458"         ,	   0x11800a0003e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT459"         ,	   0x11800a0003e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT460"         ,	   0x11800a0003e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT461"         ,	   0x11800a0003e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT462"         ,	   0x11800a0003e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT463"         ,	   0x11800a0003e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT464"         ,	   0x11800a0003e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT465"         ,	   0x11800a0003e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT466"         ,	   0x11800a0003e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT467"         ,	   0x11800a0003e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT468"         ,	   0x11800a0003ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT469"         ,	   0x11800a0003ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT470"         ,	   0x11800a0003eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT471"         ,	   0x11800a0003eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT472"         ,	   0x11800a0003ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT473"         ,	   0x11800a0003ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT474"         ,	   0x11800a0003ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT475"         ,	   0x11800a0003ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT476"         ,	   0x11800a0003ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT477"         ,	   0x11800a0003ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT478"         ,	   0x11800a0003ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT479"         ,	   0x11800a0003ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT480"         ,	   0x11800a0003f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT481"         ,	   0x11800a0003f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT482"         ,	   0x11800a0003f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT483"         ,	   0x11800a0003f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT484"         ,	   0x11800a0003f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT485"         ,	   0x11800a0003f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT486"         ,	   0x11800a0003f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT487"         ,	   0x11800a0003f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT488"         ,	   0x11800a0003f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT489"         ,	   0x11800a0003f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT490"         ,	   0x11800a0003f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT491"         ,	   0x11800a0003f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT492"         ,	   0x11800a0003f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT493"         ,	   0x11800a0003f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT494"         ,	   0x11800a0003f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT495"         ,	   0x11800a0003f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT496"         ,	   0x11800a0003f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT497"         ,	   0x11800a0003f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT498"         ,	   0x11800a0003f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT499"         ,	   0x11800a0003f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT500"         ,	   0x11800a0003fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT501"         ,	   0x11800a0003fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT502"         ,	   0x11800a0003fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT503"         ,	   0x11800a0003fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT504"         ,	   0x11800a0003fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT505"         ,	   0x11800a0003fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT506"         ,	   0x11800a0003fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT507"         ,	   0x11800a0003fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT508"         ,	   0x11800a0003fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT509"         ,	   0x11800a0003fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT510"         ,	   0x11800a0003ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_BSEL_TBL_ENT511"         ,	   0x11800a0003ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_CLKEN"                   ,	   0x11800a0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	817},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800a0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800a0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800a0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800a0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
+	{"PIP_DSA_SRC_GRP"             ,	   0x11800a0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	819},
+	{"PIP_DSA_VID_GRP"             ,	   0x11800a0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	820},
+	{"PIP_FRM_LEN_CHK0"            ,	   0x11800a0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	821},
+	{"PIP_GBL_CFG"                 ,	   0x11800a0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	822},
+	{"PIP_GBL_CTL"                 ,	   0x11800a0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	823},
+	{"PIP_HG_PRI_QOS"              ,	   0x11800a00001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_INT_EN"                  ,	   0x11800a0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_INT_REG"                 ,	   0x11800a0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_IP_OFFSET"               ,	   0x11800a0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_PRT_CFG0"                ,	   0x11800a0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_PRT_CFG1"                ,	   0x11800a0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_PRT_CFG2"                ,	   0x11800a0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_PRT_CFG3"                ,	   0x11800a0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_PRT_CFG16"               ,	   0x11800a0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_PRT_CFG17"               ,	   0x11800a0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_PRT_CFG18"               ,	   0x11800a0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_PRT_CFG19"               ,	   0x11800a0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_PRT_CFG32"               ,	   0x11800a0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_PRT_CFG33"               ,	   0x11800a0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_PRT_CFG34"               ,	   0x11800a0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_PRT_CFG35"               ,	   0x11800a0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_PRT_CFG36"               ,	   0x11800a0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_PRT_CFG37"               ,	   0x11800a0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_PRT_CFG38"               ,	   0x11800a0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_PRT_CFG39"               ,	   0x11800a0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_PRT_CFGB0"               ,	   0x11800a0008000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_PRT_CFGB1"               ,	   0x11800a0008008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_PRT_CFGB2"               ,	   0x11800a0008010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_PRT_CFGB3"               ,	   0x11800a0008018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_PRT_CFGB16"              ,	   0x11800a0008080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_PRT_CFGB17"              ,	   0x11800a0008088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_PRT_CFGB18"              ,	   0x11800a0008090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_PRT_CFGB19"              ,	   0x11800a0008098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_PRT_CFGB32"              ,	   0x11800a0008100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_PRT_CFGB33"              ,	   0x11800a0008108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_PRT_CFGB34"              ,	   0x11800a0008110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_PRT_CFGB35"              ,	   0x11800a0008118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_PRT_CFGB36"              ,	   0x11800a0008120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_PRT_CFGB37"              ,	   0x11800a0008128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_PRT_CFGB38"              ,	   0x11800a0008130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_PRT_CFGB39"              ,	   0x11800a0008138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_PRT_TAG0"                ,	   0x11800a0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PIP_PRT_TAG1"                ,	   0x11800a0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PIP_PRT_TAG2"                ,	   0x11800a0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PIP_PRT_TAG3"                ,	   0x11800a0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PIP_PRT_TAG16"               ,	   0x11800a0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PIP_PRT_TAG17"               ,	   0x11800a0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PIP_PRT_TAG18"               ,	   0x11800a0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PIP_PRT_TAG19"               ,	   0x11800a0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PIP_PRT_TAG32"               ,	   0x11800a0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PIP_PRT_TAG33"               ,	   0x11800a0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PIP_PRT_TAG34"               ,	   0x11800a0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PIP_PRT_TAG35"               ,	   0x11800a0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PIP_PRT_TAG36"               ,	   0x11800a0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PIP_PRT_TAG37"               ,	   0x11800a0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PIP_PRT_TAG38"               ,	   0x11800a0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PIP_PRT_TAG39"               ,	   0x11800a0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PIP_QOS_DIFF0"               ,	   0x11800a0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF1"               ,	   0x11800a0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF2"               ,	   0x11800a0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF3"               ,	   0x11800a0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF4"               ,	   0x11800a0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF5"               ,	   0x11800a0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF6"               ,	   0x11800a0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF7"               ,	   0x11800a0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF8"               ,	   0x11800a0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF9"               ,	   0x11800a0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF10"              ,	   0x11800a0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF11"              ,	   0x11800a0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF12"              ,	   0x11800a0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF13"              ,	   0x11800a0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF14"              ,	   0x11800a0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF15"              ,	   0x11800a0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF16"              ,	   0x11800a0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF17"              ,	   0x11800a0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF18"              ,	   0x11800a0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF19"              ,	   0x11800a0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF20"              ,	   0x11800a00006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF21"              ,	   0x11800a00006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF22"              ,	   0x11800a00006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF23"              ,	   0x11800a00006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF24"              ,	   0x11800a00006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF25"              ,	   0x11800a00006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF26"              ,	   0x11800a00006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF27"              ,	   0x11800a00006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF28"              ,	   0x11800a00006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF29"              ,	   0x11800a00006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF30"              ,	   0x11800a00006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF31"              ,	   0x11800a00006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF32"              ,	   0x11800a0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF33"              ,	   0x11800a0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF34"              ,	   0x11800a0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF35"              ,	   0x11800a0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF36"              ,	   0x11800a0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF37"              ,	   0x11800a0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF38"              ,	   0x11800a0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF39"              ,	   0x11800a0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF40"              ,	   0x11800a0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF41"              ,	   0x11800a0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF42"              ,	   0x11800a0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF43"              ,	   0x11800a0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF44"              ,	   0x11800a0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF45"              ,	   0x11800a0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF46"              ,	   0x11800a0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF47"              ,	   0x11800a0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF48"              ,	   0x11800a0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF49"              ,	   0x11800a0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF50"              ,	   0x11800a0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF51"              ,	   0x11800a0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF52"              ,	   0x11800a00007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF53"              ,	   0x11800a00007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF54"              ,	   0x11800a00007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF55"              ,	   0x11800a00007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF56"              ,	   0x11800a00007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF57"              ,	   0x11800a00007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF58"              ,	   0x11800a00007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF59"              ,	   0x11800a00007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF60"              ,	   0x11800a00007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF61"              ,	   0x11800a00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF62"              ,	   0x11800a00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_DIFF63"              ,	   0x11800a00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_QOS_VLAN0"               ,	   0x11800a00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_QOS_VLAN1"               ,	   0x11800a00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_QOS_VLAN2"               ,	   0x11800a00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_QOS_VLAN3"               ,	   0x11800a00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_QOS_VLAN4"               ,	   0x11800a00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_QOS_VLAN5"               ,	   0x11800a00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_QOS_VLAN6"               ,	   0x11800a00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_QOS_VLAN7"               ,	   0x11800a00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_QOS_WATCH0"              ,	   0x11800a0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_QOS_WATCH1"              ,	   0x11800a0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_QOS_WATCH2"              ,	   0x11800a0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_QOS_WATCH3"              ,	   0x11800a0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_QOS_WATCH4"              ,	   0x11800a0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_QOS_WATCH5"              ,	   0x11800a0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_QOS_WATCH6"              ,	   0x11800a0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_QOS_WATCH7"              ,	   0x11800a0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_RAW_WORD"                ,	   0x11800a00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PIP_SFT_RST"                 ,	   0x11800a0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PIP_STAT0_PRT0"              ,	   0x11800a0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT0_PRT1"              ,	   0x11800a0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT0_PRT2"              ,	   0x11800a00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT0_PRT3"              ,	   0x11800a00008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT0_PRT16"             ,	   0x11800a0000d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT0_PRT17"             ,	   0x11800a0000d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT0_PRT18"             ,	   0x11800a0000da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT0_PRT19"             ,	   0x11800a0000df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT0_PRT32"             ,	   0x11800a0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT0_PRT33"             ,	   0x11800a0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT0_PRT34"             ,	   0x11800a00012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT0_PRT35"             ,	   0x11800a00012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT0_PRT36"             ,	   0x11800a0001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT0_PRT37"             ,	   0x11800a0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT0_PRT38"             ,	   0x11800a00013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT0_PRT39"             ,	   0x11800a0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT10_PRT0"             ,	   0x11800a0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT10_PRT1"             ,	   0x11800a0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT10_PRT2"             ,	   0x11800a00014a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT10_PRT3"             ,	   0x11800a00014b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT10_PRT16"            ,	   0x11800a0001580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT10_PRT17"            ,	   0x11800a0001590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT10_PRT18"            ,	   0x11800a00015a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT10_PRT19"            ,	   0x11800a00015b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT10_PRT32"            ,	   0x11800a0001680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT10_PRT33"            ,	   0x11800a0001690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT10_PRT34"            ,	   0x11800a00016a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT10_PRT35"            ,	   0x11800a00016b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT10_PRT36"            ,	   0x11800a00016c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT10_PRT37"            ,	   0x11800a00016d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT10_PRT38"            ,	   0x11800a00016e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT10_PRT39"            ,	   0x11800a00016f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT11_PRT0"             ,	   0x11800a0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT11_PRT1"             ,	   0x11800a0001498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT11_PRT2"             ,	   0x11800a00014a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT11_PRT3"             ,	   0x11800a00014b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT11_PRT16"            ,	   0x11800a0001588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT11_PRT17"            ,	   0x11800a0001598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT11_PRT18"            ,	   0x11800a00015a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT11_PRT19"            ,	   0x11800a00015b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT11_PRT32"            ,	   0x11800a0001688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT11_PRT33"            ,	   0x11800a0001698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT11_PRT34"            ,	   0x11800a00016a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT11_PRT35"            ,	   0x11800a00016b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT11_PRT36"            ,	   0x11800a00016c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT11_PRT37"            ,	   0x11800a00016d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT11_PRT38"            ,	   0x11800a00016e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT11_PRT39"            ,	   0x11800a00016f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT1_PRT3"              ,	   0x11800a00008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT1_PRT16"             ,	   0x11800a0000d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT1_PRT17"             ,	   0x11800a0000d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT1_PRT18"             ,	   0x11800a0000da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT1_PRT19"             ,	   0x11800a0000df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT1_PRT32"             ,	   0x11800a0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT1_PRT33"             ,	   0x11800a0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT1_PRT34"             ,	   0x11800a00012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT1_PRT35"             ,	   0x11800a00012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT1_PRT36"             ,	   0x11800a0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT1_PRT37"             ,	   0x11800a0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT1_PRT38"             ,	   0x11800a00013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT1_PRT39"             ,	   0x11800a0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT2_PRT3"              ,	   0x11800a0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT2_PRT16"             ,	   0x11800a0000d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT2_PRT17"             ,	   0x11800a0000d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT2_PRT18"             ,	   0x11800a0000db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT2_PRT19"             ,	   0x11800a0000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT2_PRT32"             ,	   0x11800a0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT2_PRT33"             ,	   0x11800a0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT2_PRT34"             ,	   0x11800a00012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT2_PRT35"             ,	   0x11800a0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT2_PRT36"             ,	   0x11800a0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT2_PRT37"             ,	   0x11800a00013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT2_PRT38"             ,	   0x11800a00013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT2_PRT39"             ,	   0x11800a0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT3_PRT3"              ,	   0x11800a0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT3_PRT16"             ,	   0x11800a0000d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT3_PRT17"             ,	   0x11800a0000d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT3_PRT18"             ,	   0x11800a0000db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT3_PRT19"             ,	   0x11800a0000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT3_PRT32"             ,	   0x11800a0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT3_PRT33"             ,	   0x11800a0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT3_PRT34"             ,	   0x11800a00012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT3_PRT35"             ,	   0x11800a0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT3_PRT36"             ,	   0x11800a0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT3_PRT37"             ,	   0x11800a00013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT3_PRT38"             ,	   0x11800a00013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT3_PRT39"             ,	   0x11800a0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT4_PRT3"              ,	   0x11800a0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT4_PRT16"             ,	   0x11800a0000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT4_PRT17"             ,	   0x11800a0000d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT4_PRT18"             ,	   0x11800a0000dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT4_PRT19"             ,	   0x11800a0000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT4_PRT32"             ,	   0x11800a0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT4_PRT33"             ,	   0x11800a0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT4_PRT34"             ,	   0x11800a00012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT4_PRT35"             ,	   0x11800a0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT4_PRT36"             ,	   0x11800a0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT4_PRT37"             ,	   0x11800a00013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT4_PRT38"             ,	   0x11800a0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT4_PRT39"             ,	   0x11800a0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT5_PRT3"              ,	   0x11800a0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT5_PRT16"             ,	   0x11800a0000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT5_PRT17"             ,	   0x11800a0000d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT5_PRT18"             ,	   0x11800a0000dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT5_PRT19"             ,	   0x11800a0000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT5_PRT32"             ,	   0x11800a0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT5_PRT33"             ,	   0x11800a0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT5_PRT34"             ,	   0x11800a00012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT5_PRT35"             ,	   0x11800a0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT5_PRT36"             ,	   0x11800a0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT5_PRT37"             ,	   0x11800a00013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT5_PRT38"             ,	   0x11800a0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT5_PRT39"             ,	   0x11800a0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"PIP_STAT6_PRT3"              ,	   0x11800a0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"PIP_STAT6_PRT16"             ,	   0x11800a0000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"PIP_STAT6_PRT17"             ,	   0x11800a0000d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"PIP_STAT6_PRT18"             ,	   0x11800a0000dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"PIP_STAT6_PRT19"             ,	   0x11800a0000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"PIP_STAT6_PRT32"             ,	   0x11800a0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"PIP_STAT6_PRT33"             ,	   0x11800a0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"PIP_STAT6_PRT34"             ,	   0x11800a00012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"PIP_STAT6_PRT35"             ,	   0x11800a0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"PIP_STAT6_PRT36"             ,	   0x11800a0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"PIP_STAT6_PRT37"             ,	   0x11800a00013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"PIP_STAT6_PRT38"             ,	   0x11800a0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"PIP_STAT6_PRT39"             ,	   0x11800a0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT7_PRT3"              ,	   0x11800a0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT7_PRT16"             ,	   0x11800a0000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT7_PRT17"             ,	   0x11800a0000d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT7_PRT18"             ,	   0x11800a0000dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT7_PRT19"             ,	   0x11800a0000e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT7_PRT32"             ,	   0x11800a0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT7_PRT33"             ,	   0x11800a0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT7_PRT34"             ,	   0x11800a00012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT7_PRT35"             ,	   0x11800a0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT7_PRT36"             ,	   0x11800a0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT7_PRT37"             ,	   0x11800a00013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT7_PRT38"             ,	   0x11800a0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT7_PRT39"             ,	   0x11800a0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT8_PRT3"              ,	   0x11800a0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT8_PRT16"             ,	   0x11800a0000d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT8_PRT17"             ,	   0x11800a0000d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT8_PRT18"             ,	   0x11800a0000de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT8_PRT19"             ,	   0x11800a0000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT8_PRT32"             ,	   0x11800a0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT8_PRT33"             ,	   0x11800a0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT8_PRT34"             ,	   0x11800a00012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT8_PRT35"             ,	   0x11800a0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT8_PRT36"             ,	   0x11800a0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT8_PRT37"             ,	   0x11800a00013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT8_PRT38"             ,	   0x11800a0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT8_PRT39"             ,	   0x11800a0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT9_PRT3"              ,	   0x11800a0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT9_PRT16"             ,	   0x11800a0000d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT9_PRT17"             ,	   0x11800a0000d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT9_PRT18"             ,	   0x11800a0000de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT9_PRT19"             ,	   0x11800a0000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT9_PRT32"             ,	   0x11800a0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT9_PRT33"             ,	   0x11800a0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT9_PRT34"             ,	   0x11800a00012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT9_PRT35"             ,	   0x11800a0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT9_PRT36"             ,	   0x11800a0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT9_PRT37"             ,	   0x11800a00013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT9_PRT38"             ,	   0x11800a0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT9_PRT39"             ,	   0x11800a0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800a0001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"PIP_STAT_INB_ERRS16"         ,	   0x11800a0001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"PIP_STAT_INB_ERRS17"         ,	   0x11800a0001c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"PIP_STAT_INB_ERRS18"         ,	   0x11800a0001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"PIP_STAT_INB_ERRS19"         ,	   0x11800a0001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800a0001e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800a0001e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800a0001e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800a0001e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"PIP_STAT_INB_ERRS36"         ,	   0x11800a0001e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"PIP_STAT_INB_ERRS37"         ,	   0x11800a0001eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"PIP_STAT_INB_ERRS38"         ,	   0x11800a0001ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"PIP_STAT_INB_ERRS39"         ,	   0x11800a0001ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800a0001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"PIP_STAT_INB_OCTS16"         ,	   0x11800a0001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"PIP_STAT_INB_OCTS17"         ,	   0x11800a0001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"PIP_STAT_INB_OCTS18"         ,	   0x11800a0001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"PIP_STAT_INB_OCTS19"         ,	   0x11800a0001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800a0001e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800a0001e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800a0001e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800a0001e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"PIP_STAT_INB_OCTS36"         ,	   0x11800a0001e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"PIP_STAT_INB_OCTS37"         ,	   0x11800a0001ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"PIP_STAT_INB_OCTS38"         ,	   0x11800a0001ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"PIP_STAT_INB_OCTS39"         ,	   0x11800a0001ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800a0001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"PIP_STAT_INB_PKTS16"         ,	   0x11800a0001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"PIP_STAT_INB_PKTS17"         ,	   0x11800a0001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"PIP_STAT_INB_PKTS18"         ,	   0x11800a0001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"PIP_STAT_INB_PKTS19"         ,	   0x11800a0001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800a0001e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800a0001e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800a0001e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800a0001e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"PIP_STAT_INB_PKTS36"         ,	   0x11800a0001e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"PIP_STAT_INB_PKTS37"         ,	   0x11800a0001ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"PIP_STAT_INB_PKTS38"         ,	   0x11800a0001ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"PIP_STAT_INB_PKTS39"         ,	   0x11800a0001ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	853},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	854},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	855},
+	{"PIP_VLAN_ETYPES0"            ,	   0x11800a00001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	856},
+	{"PIP_VLAN_ETYPES1"            ,	   0x11800a00001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	856},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	857},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	858},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	859},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	860},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	861},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	862},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	863},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	864},
+	{"PKO_MEM_DEBUG14"             ,	   0x1180050001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	865},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	866},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	867},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	868},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	869},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	870},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	871},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	873},
+	{"PKO_MEM_PORT_PTRS"           ,	   0x1180050001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	874},
+	{"PKO_MEM_PORT_QOS"            ,	   0x1180050001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	875},
+	{"PKO_MEM_PORT_RATE0"          ,	   0x1180050001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	876},
+	{"PKO_MEM_PORT_RATE1"          ,	   0x1180050001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	877},
+	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	878},
+	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
+	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	886},
+	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	887},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	888},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	889},
+	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	890},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	891},
+	{"PKO_REG_PREEMPT"             ,	   0x1180050000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	892},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	893},
+	{"PKO_REG_QUEUE_PREEMPT"       ,	   0x1180050000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	894},
+	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	895},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	896},
+	{"PKO_REG_TIMESTAMP"           ,	   0x1180050000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	898},
+	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	899},
+	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	900},
+	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	901},
+	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	902},
+	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	902},
+	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	902},
+	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	902},
+	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	902},
+	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	902},
+	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	902},
+	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	902},
+	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	903},
+	{"POW_IQ_INT"                  ,	   0x1670000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	904},
+	{"POW_IQ_INT_EN"               ,	   0x1670000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	905},
+	{"POW_IQ_THR0"                 ,	   0x16700000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	906},
+	{"POW_IQ_THR1"                 ,	   0x16700000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	906},
+	{"POW_IQ_THR2"                 ,	   0x16700000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	906},
+	{"POW_IQ_THR3"                 ,	   0x16700000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	906},
+	{"POW_IQ_THR4"                 ,	   0x16700000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	906},
+	{"POW_IQ_THR5"                 ,	   0x16700000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	906},
+	{"POW_IQ_THR6"                 ,	   0x16700000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	906},
+	{"POW_IQ_THR7"                 ,	   0x16700000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	906},
+	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	907},
+	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	908},
+	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	909},
+	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	910},
+	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	910},
+	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	910},
+	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	910},
+	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	911},
+	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	911},
+	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	911},
+	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	911},
+	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	911},
+	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	911},
+	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	911},
+	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	911},
+	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	912},
+	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	912},
+	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	912},
+	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	912},
+	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	912},
+	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	912},
+	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	912},
+	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	912},
+	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	913},
+	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	914},
+	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	915},
+	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	915},
+	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	915},
+	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	915},
+	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	915},
+	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	915},
+	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	915},
+	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	915},
+	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	916},
+	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	917},
+	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	917},
+	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	917},
+	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	917},
+	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	917},
+	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	917},
+	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	917},
+	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	917},
+	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	917},
+	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	917},
+	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	917},
+	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	917},
+	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	917},
+	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	917},
+	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	917},
+	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	917},
+	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	918},
+	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	921},
+	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	922},
+	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	923},
+	{"RAD_REG_BIST_RESULT"         ,	   0x1180070000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	924},
+	{"RAD_REG_CMD_BUF"             ,	   0x1180070000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	925},
+	{"RAD_REG_CTL"                 ,	   0x1180070000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	926},
+	{"RAD_REG_DEBUG0"              ,	   0x1180070000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	927},
+	{"RAD_REG_DEBUG1"              ,	   0x1180070000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	928},
+	{"RAD_REG_DEBUG10"             ,	   0x1180070000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	929},
+	{"RAD_REG_DEBUG11"             ,	   0x1180070000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	930},
+	{"RAD_REG_DEBUG12"             ,	   0x1180070000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	931},
+	{"RAD_REG_DEBUG2"              ,	   0x1180070000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	932},
+	{"RAD_REG_DEBUG3"              ,	   0x1180070000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"RAD_REG_DEBUG4"              ,	   0x1180070000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	934},
+	{"RAD_REG_DEBUG5"              ,	   0x1180070000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	935},
+	{"RAD_REG_DEBUG6"              ,	   0x1180070000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	936},
+	{"RAD_REG_DEBUG7"              ,	   0x1180070000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	937},
+	{"RAD_REG_DEBUG8"              ,	   0x1180070000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	938},
+	{"RAD_REG_DEBUG9"              ,	   0x1180070000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"RAD_REG_ERROR"               ,	   0x1180070000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"RAD_REG_INT_MASK"            ,	   0x1180070000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"RAD_REG_POLYNOMIAL"          ,	   0x1180070000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"RAD_REG_READ_IDX"            ,	   0x1180070000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"RNM_EER_DBG"                 ,	   0x1180040000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"RNM_EER_KEY"                 ,	   0x1180040000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"RNM_SERIAL_NUM"              ,	   0x1180040000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"SLI_BIST_STATUS"             ,	   0x11f0000010580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_CTL_PORT0"               ,	   0x11f0000010050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_CTL_PORT1"               ,	   0x11f0000010060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_CTL_STATUS"              ,	   0x11f0000010570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_DATA_OUT_CNT"            ,	   0x11f00000105f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	952},
+	{"SLI_DBG_DATA"                ,	   0x11f0000010310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	953},
+	{"SLI_DBG_SELECT"              ,	   0x11f0000010300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_DMA0_CNT"                ,	   0x11f0000010400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	955},
+	{"SLI_DMA1_CNT"                ,	   0x11f0000010410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	955},
+	{"SLI_DMA0_INT_LEVEL"          ,	   0x11f00000103e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	956},
+	{"SLI_DMA1_INT_LEVEL"          ,	   0x11f00000103f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	956},
+	{"SLI_DMA0_TIM"                ,	   0x11f0000010420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	957},
+	{"SLI_DMA1_TIM"                ,	   0x11f0000010430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	957},
+	{"SLI_INT_ENB_CIU"             ,	   0x11f0000013cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	958},
+	{"SLI_INT_ENB_PORT0"           ,	   0x11f0000010340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	959},
+	{"SLI_INT_ENB_PORT1"           ,	   0x11f0000010350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	959},
+	{"SLI_INT_SUM"                 ,	   0x11f0000010330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_LAST_WIN_RDATA0"         ,	   0x11f0000010600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	961},
+	{"SLI_LAST_WIN_RDATA1"         ,	   0x11f0000010610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	962},
+	{"SLI_LAST_WIN_RDATA2"         ,	   0x11f00000106c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	963},
+	{"SLI_LAST_WIN_RDATA3"         ,	   0x11f00000106d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	964},
+	{"SLI_MAC_CREDIT_CNT"          ,	   0x11f0000013d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	965},
+	{"SLI_MAC_CREDIT_CNT2"         ,	   0x11f0000013e10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	966},
+	{"SLI_MAC_NUMBER"              ,	            0x3e00ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	967},
+	{"SLI_MEM_ACCESS_CTL"          ,	   0x11f00000102f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	968},
+	{"SLI_MEM_ACCESS_SUBID12"      ,	   0x11f00000100e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_MEM_ACCESS_SUBID13"      ,	   0x11f00000100f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_MEM_ACCESS_SUBID14"      ,	   0x11f0000010100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_MEM_ACCESS_SUBID15"      ,	   0x11f0000010110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_MEM_ACCESS_SUBID16"      ,	   0x11f0000010120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_MEM_ACCESS_SUBID17"      ,	   0x11f0000010130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_MEM_ACCESS_SUBID18"      ,	   0x11f0000010140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_MEM_ACCESS_SUBID19"      ,	   0x11f0000010150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_MEM_ACCESS_SUBID20"      ,	   0x11f0000010160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_MEM_ACCESS_SUBID21"      ,	   0x11f0000010170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_MEM_ACCESS_SUBID22"      ,	   0x11f0000010180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_MEM_ACCESS_SUBID23"      ,	   0x11f0000010190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_MEM_ACCESS_SUBID24"      ,	   0x11f00000101a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_MEM_ACCESS_SUBID25"      ,	   0x11f00000101b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_MEM_ACCESS_SUBID26"      ,	   0x11f00000101c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_MEM_ACCESS_SUBID27"      ,	   0x11f00000101d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_MSI_ENB0"                ,	   0x11f0000013c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	970},
+	{"SLI_MSI_ENB1"                ,	   0x11f0000013c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	971},
+	{"SLI_MSI_ENB2"                ,	   0x11f0000013c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	972},
+	{"SLI_MSI_ENB3"                ,	   0x11f0000013c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	973},
+	{"SLI_MSI_RCV0"                ,	   0x11f0000013c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	974},
+	{"SLI_MSI_RCV1"                ,	   0x11f0000013c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	975},
+	{"SLI_MSI_RCV2"                ,	   0x11f0000013c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	976},
+	{"SLI_MSI_RCV3"                ,	   0x11f0000013c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_MSI_RD_MAP"              ,	   0x11f0000013ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	978},
+	{"SLI_MSI_W1C_ENB0"            ,	   0x11f0000013cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	979},
+	{"SLI_MSI_W1C_ENB1"            ,	   0x11f0000013d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	980},
+	{"SLI_MSI_W1C_ENB2"            ,	   0x11f0000013d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	981},
+	{"SLI_MSI_W1C_ENB3"            ,	   0x11f0000013d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	982},
+	{"SLI_MSI_W1S_ENB0"            ,	   0x11f0000013d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	983},
+	{"SLI_MSI_W1S_ENB1"            ,	   0x11f0000013d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	984},
+	{"SLI_MSI_W1S_ENB2"            ,	   0x11f0000013d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	985},
+	{"SLI_MSI_W1S_ENB3"            ,	   0x11f0000013d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	986},
+	{"SLI_MSI_WR_MAP"              ,	   0x11f0000013c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	987},
+	{"SLI_PCIE_MSI_RCV"            ,	   0x11f0000013cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	988},
+	{"SLI_PCIE_MSI_RCV_B1"         ,	   0x11f0000010650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	989},
+	{"SLI_PCIE_MSI_RCV_B2"         ,	   0x11f0000010660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	990},
+	{"SLI_PCIE_MSI_RCV_B3"         ,	   0x11f0000010670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	991},
+	{"SLI_PKT0_CNTS"               ,	   0x11f0000012400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT1_CNTS"               ,	   0x11f0000012410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT2_CNTS"               ,	   0x11f0000012420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT3_CNTS"               ,	   0x11f0000012430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT4_CNTS"               ,	   0x11f0000012440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT5_CNTS"               ,	   0x11f0000012450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT6_CNTS"               ,	   0x11f0000012460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT7_CNTS"               ,	   0x11f0000012470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT8_CNTS"               ,	   0x11f0000012480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT9_CNTS"               ,	   0x11f0000012490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT10_CNTS"              ,	   0x11f00000124a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT11_CNTS"              ,	   0x11f00000124b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT12_CNTS"              ,	   0x11f00000124c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT13_CNTS"              ,	   0x11f00000124d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT14_CNTS"              ,	   0x11f00000124e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT15_CNTS"              ,	   0x11f00000124f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT16_CNTS"              ,	   0x11f0000012500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT17_CNTS"              ,	   0x11f0000012510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT18_CNTS"              ,	   0x11f0000012520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT19_CNTS"              ,	   0x11f0000012530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT20_CNTS"              ,	   0x11f0000012540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT21_CNTS"              ,	   0x11f0000012550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT22_CNTS"              ,	   0x11f0000012560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT23_CNTS"              ,	   0x11f0000012570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT24_CNTS"              ,	   0x11f0000012580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT25_CNTS"              ,	   0x11f0000012590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT26_CNTS"              ,	   0x11f00000125a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT27_CNTS"              ,	   0x11f00000125b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT28_CNTS"              ,	   0x11f00000125c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT29_CNTS"              ,	   0x11f00000125d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT30_CNTS"              ,	   0x11f00000125e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT31_CNTS"              ,	   0x11f00000125f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_PKT0_IN_BP"              ,	   0x11f0000013800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT1_IN_BP"              ,	   0x11f0000013810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT2_IN_BP"              ,	   0x11f0000013820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT3_IN_BP"              ,	   0x11f0000013830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT4_IN_BP"              ,	   0x11f0000013840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT5_IN_BP"              ,	   0x11f0000013850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT6_IN_BP"              ,	   0x11f0000013860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT7_IN_BP"              ,	   0x11f0000013870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT8_IN_BP"              ,	   0x11f0000013880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT9_IN_BP"              ,	   0x11f0000013890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT10_IN_BP"             ,	   0x11f00000138a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT11_IN_BP"             ,	   0x11f00000138b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT12_IN_BP"             ,	   0x11f00000138c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT13_IN_BP"             ,	   0x11f00000138d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT14_IN_BP"             ,	   0x11f00000138e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT15_IN_BP"             ,	   0x11f00000138f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT16_IN_BP"             ,	   0x11f0000013900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT17_IN_BP"             ,	   0x11f0000013910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT18_IN_BP"             ,	   0x11f0000013920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT19_IN_BP"             ,	   0x11f0000013930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT20_IN_BP"             ,	   0x11f0000013940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT21_IN_BP"             ,	   0x11f0000013950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT22_IN_BP"             ,	   0x11f0000013960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT23_IN_BP"             ,	   0x11f0000013970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT24_IN_BP"             ,	   0x11f0000013980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT25_IN_BP"             ,	   0x11f0000013990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT26_IN_BP"             ,	   0x11f00000139a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT27_IN_BP"             ,	   0x11f00000139b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT28_IN_BP"             ,	   0x11f00000139c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT29_IN_BP"             ,	   0x11f00000139d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT30_IN_BP"             ,	   0x11f00000139e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT31_IN_BP"             ,	   0x11f00000139f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_PKT0_INSTR_BADDR"        ,	   0x11f0000012800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT1_INSTR_BADDR"        ,	   0x11f0000012810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT2_INSTR_BADDR"        ,	   0x11f0000012820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT3_INSTR_BADDR"        ,	   0x11f0000012830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT4_INSTR_BADDR"        ,	   0x11f0000012840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT5_INSTR_BADDR"        ,	   0x11f0000012850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT6_INSTR_BADDR"        ,	   0x11f0000012860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT7_INSTR_BADDR"        ,	   0x11f0000012870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT8_INSTR_BADDR"        ,	   0x11f0000012880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT9_INSTR_BADDR"        ,	   0x11f0000012890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT10_INSTR_BADDR"       ,	   0x11f00000128a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT11_INSTR_BADDR"       ,	   0x11f00000128b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT12_INSTR_BADDR"       ,	   0x11f00000128c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT13_INSTR_BADDR"       ,	   0x11f00000128d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT14_INSTR_BADDR"       ,	   0x11f00000128e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT15_INSTR_BADDR"       ,	   0x11f00000128f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT16_INSTR_BADDR"       ,	   0x11f0000012900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT17_INSTR_BADDR"       ,	   0x11f0000012910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT18_INSTR_BADDR"       ,	   0x11f0000012920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT19_INSTR_BADDR"       ,	   0x11f0000012930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT20_INSTR_BADDR"       ,	   0x11f0000012940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT21_INSTR_BADDR"       ,	   0x11f0000012950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT22_INSTR_BADDR"       ,	   0x11f0000012960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT23_INSTR_BADDR"       ,	   0x11f0000012970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT24_INSTR_BADDR"       ,	   0x11f0000012980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT25_INSTR_BADDR"       ,	   0x11f0000012990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT26_INSTR_BADDR"       ,	   0x11f00000129a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT27_INSTR_BADDR"       ,	   0x11f00000129b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT28_INSTR_BADDR"       ,	   0x11f00000129c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT29_INSTR_BADDR"       ,	   0x11f00000129d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT30_INSTR_BADDR"       ,	   0x11f00000129e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT31_INSTR_BADDR"       ,	   0x11f00000129f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_PKT0_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT1_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT2_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT3_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT4_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT5_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT6_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT7_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT8_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT9_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT10_INSTR_BAOFF_DBELL" ,	   0x11f0000012ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT11_INSTR_BAOFF_DBELL" ,	   0x11f0000012cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT12_INSTR_BAOFF_DBELL" ,	   0x11f0000012cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT13_INSTR_BAOFF_DBELL" ,	   0x11f0000012cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT14_INSTR_BAOFF_DBELL" ,	   0x11f0000012ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT15_INSTR_BAOFF_DBELL" ,	   0x11f0000012cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT16_INSTR_BAOFF_DBELL" ,	   0x11f0000012d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT17_INSTR_BAOFF_DBELL" ,	   0x11f0000012d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT18_INSTR_BAOFF_DBELL" ,	   0x11f0000012d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT19_INSTR_BAOFF_DBELL" ,	   0x11f0000012d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT20_INSTR_BAOFF_DBELL" ,	   0x11f0000012d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT21_INSTR_BAOFF_DBELL" ,	   0x11f0000012d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT22_INSTR_BAOFF_DBELL" ,	   0x11f0000012d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT23_INSTR_BAOFF_DBELL" ,	   0x11f0000012d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT24_INSTR_BAOFF_DBELL" ,	   0x11f0000012d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT25_INSTR_BAOFF_DBELL" ,	   0x11f0000012d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT26_INSTR_BAOFF_DBELL" ,	   0x11f0000012da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT27_INSTR_BAOFF_DBELL" ,	   0x11f0000012db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT28_INSTR_BAOFF_DBELL" ,	   0x11f0000012dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT29_INSTR_BAOFF_DBELL" ,	   0x11f0000012dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT30_INSTR_BAOFF_DBELL" ,	   0x11f0000012de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT31_INSTR_BAOFF_DBELL" ,	   0x11f0000012df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PKT0_INSTR_FIFO_RSIZE"   ,	   0x11f0000013000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT1_INSTR_FIFO_RSIZE"   ,	   0x11f0000013010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT2_INSTR_FIFO_RSIZE"   ,	   0x11f0000013020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT3_INSTR_FIFO_RSIZE"   ,	   0x11f0000013030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT4_INSTR_FIFO_RSIZE"   ,	   0x11f0000013040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT5_INSTR_FIFO_RSIZE"   ,	   0x11f0000013050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT6_INSTR_FIFO_RSIZE"   ,	   0x11f0000013060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT7_INSTR_FIFO_RSIZE"   ,	   0x11f0000013070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT8_INSTR_FIFO_RSIZE"   ,	   0x11f0000013080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT9_INSTR_FIFO_RSIZE"   ,	   0x11f0000013090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT10_INSTR_FIFO_RSIZE"  ,	   0x11f00000130a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT11_INSTR_FIFO_RSIZE"  ,	   0x11f00000130b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT12_INSTR_FIFO_RSIZE"  ,	   0x11f00000130c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT13_INSTR_FIFO_RSIZE"  ,	   0x11f00000130d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT14_INSTR_FIFO_RSIZE"  ,	   0x11f00000130e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT15_INSTR_FIFO_RSIZE"  ,	   0x11f00000130f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT16_INSTR_FIFO_RSIZE"  ,	   0x11f0000013100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT17_INSTR_FIFO_RSIZE"  ,	   0x11f0000013110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT18_INSTR_FIFO_RSIZE"  ,	   0x11f0000013120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT19_INSTR_FIFO_RSIZE"  ,	   0x11f0000013130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT20_INSTR_FIFO_RSIZE"  ,	   0x11f0000013140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT21_INSTR_FIFO_RSIZE"  ,	   0x11f0000013150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT22_INSTR_FIFO_RSIZE"  ,	   0x11f0000013160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT23_INSTR_FIFO_RSIZE"  ,	   0x11f0000013170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT24_INSTR_FIFO_RSIZE"  ,	   0x11f0000013180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT25_INSTR_FIFO_RSIZE"  ,	   0x11f0000013190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT26_INSTR_FIFO_RSIZE"  ,	   0x11f00000131a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT27_INSTR_FIFO_RSIZE"  ,	   0x11f00000131b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT28_INSTR_FIFO_RSIZE"  ,	   0x11f00000131c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT29_INSTR_FIFO_RSIZE"  ,	   0x11f00000131d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT30_INSTR_FIFO_RSIZE"  ,	   0x11f00000131e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT31_INSTR_FIFO_RSIZE"  ,	   0x11f00000131f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PKT0_INSTR_HEADER"       ,	   0x11f0000013400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT1_INSTR_HEADER"       ,	   0x11f0000013410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT2_INSTR_HEADER"       ,	   0x11f0000013420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT3_INSTR_HEADER"       ,	   0x11f0000013430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT4_INSTR_HEADER"       ,	   0x11f0000013440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT5_INSTR_HEADER"       ,	   0x11f0000013450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT6_INSTR_HEADER"       ,	   0x11f0000013460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT7_INSTR_HEADER"       ,	   0x11f0000013470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT8_INSTR_HEADER"       ,	   0x11f0000013480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT9_INSTR_HEADER"       ,	   0x11f0000013490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT10_INSTR_HEADER"      ,	   0x11f00000134a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT11_INSTR_HEADER"      ,	   0x11f00000134b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT12_INSTR_HEADER"      ,	   0x11f00000134c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT13_INSTR_HEADER"      ,	   0x11f00000134d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT14_INSTR_HEADER"      ,	   0x11f00000134e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT15_INSTR_HEADER"      ,	   0x11f00000134f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT16_INSTR_HEADER"      ,	   0x11f0000013500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT17_INSTR_HEADER"      ,	   0x11f0000013510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT18_INSTR_HEADER"      ,	   0x11f0000013520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT19_INSTR_HEADER"      ,	   0x11f0000013530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT20_INSTR_HEADER"      ,	   0x11f0000013540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT21_INSTR_HEADER"      ,	   0x11f0000013550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT22_INSTR_HEADER"      ,	   0x11f0000013560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT23_INSTR_HEADER"      ,	   0x11f0000013570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT24_INSTR_HEADER"      ,	   0x11f0000013580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT25_INSTR_HEADER"      ,	   0x11f0000013590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT26_INSTR_HEADER"      ,	   0x11f00000135a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT27_INSTR_HEADER"      ,	   0x11f00000135b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT28_INSTR_HEADER"      ,	   0x11f00000135c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT29_INSTR_HEADER"      ,	   0x11f00000135d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT30_INSTR_HEADER"      ,	   0x11f00000135e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT31_INSTR_HEADER"      ,	   0x11f00000135f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PKT0_OUT_SIZE"           ,	   0x11f0000010c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT1_OUT_SIZE"           ,	   0x11f0000010c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT2_OUT_SIZE"           ,	   0x11f0000010c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT3_OUT_SIZE"           ,	   0x11f0000010c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT4_OUT_SIZE"           ,	   0x11f0000010c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT5_OUT_SIZE"           ,	   0x11f0000010c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT6_OUT_SIZE"           ,	   0x11f0000010c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT7_OUT_SIZE"           ,	   0x11f0000010c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT8_OUT_SIZE"           ,	   0x11f0000010c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT9_OUT_SIZE"           ,	   0x11f0000010c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT10_OUT_SIZE"          ,	   0x11f0000010ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT11_OUT_SIZE"          ,	   0x11f0000010cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT12_OUT_SIZE"          ,	   0x11f0000010cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT13_OUT_SIZE"          ,	   0x11f0000010cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT14_OUT_SIZE"          ,	   0x11f0000010ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT15_OUT_SIZE"          ,	   0x11f0000010cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT16_OUT_SIZE"          ,	   0x11f0000010d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT17_OUT_SIZE"          ,	   0x11f0000010d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT18_OUT_SIZE"          ,	   0x11f0000010d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT19_OUT_SIZE"          ,	   0x11f0000010d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT20_OUT_SIZE"          ,	   0x11f0000010d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT21_OUT_SIZE"          ,	   0x11f0000010d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT22_OUT_SIZE"          ,	   0x11f0000010d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT23_OUT_SIZE"          ,	   0x11f0000010d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT24_OUT_SIZE"          ,	   0x11f0000010d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT25_OUT_SIZE"          ,	   0x11f0000010d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT26_OUT_SIZE"          ,	   0x11f0000010da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT27_OUT_SIZE"          ,	   0x11f0000010db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT28_OUT_SIZE"          ,	   0x11f0000010dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT29_OUT_SIZE"          ,	   0x11f0000010dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT30_OUT_SIZE"          ,	   0x11f0000010de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT31_OUT_SIZE"          ,	   0x11f0000010df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PKT0_SLIST_BADDR"        ,	   0x11f0000011400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT1_SLIST_BADDR"        ,	   0x11f0000011410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT2_SLIST_BADDR"        ,	   0x11f0000011420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT3_SLIST_BADDR"        ,	   0x11f0000011430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT4_SLIST_BADDR"        ,	   0x11f0000011440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT5_SLIST_BADDR"        ,	   0x11f0000011450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT6_SLIST_BADDR"        ,	   0x11f0000011460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT7_SLIST_BADDR"        ,	   0x11f0000011470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT8_SLIST_BADDR"        ,	   0x11f0000011480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT9_SLIST_BADDR"        ,	   0x11f0000011490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT10_SLIST_BADDR"       ,	   0x11f00000114a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT11_SLIST_BADDR"       ,	   0x11f00000114b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT12_SLIST_BADDR"       ,	   0x11f00000114c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT13_SLIST_BADDR"       ,	   0x11f00000114d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT14_SLIST_BADDR"       ,	   0x11f00000114e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT15_SLIST_BADDR"       ,	   0x11f00000114f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT16_SLIST_BADDR"       ,	   0x11f0000011500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT17_SLIST_BADDR"       ,	   0x11f0000011510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT18_SLIST_BADDR"       ,	   0x11f0000011520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT19_SLIST_BADDR"       ,	   0x11f0000011530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT20_SLIST_BADDR"       ,	   0x11f0000011540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT21_SLIST_BADDR"       ,	   0x11f0000011550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT22_SLIST_BADDR"       ,	   0x11f0000011560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT23_SLIST_BADDR"       ,	   0x11f0000011570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT24_SLIST_BADDR"       ,	   0x11f0000011580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT25_SLIST_BADDR"       ,	   0x11f0000011590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT26_SLIST_BADDR"       ,	   0x11f00000115a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT27_SLIST_BADDR"       ,	   0x11f00000115b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT28_SLIST_BADDR"       ,	   0x11f00000115c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT29_SLIST_BADDR"       ,	   0x11f00000115d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT30_SLIST_BADDR"       ,	   0x11f00000115e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT31_SLIST_BADDR"       ,	   0x11f00000115f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT0_SLIST_BAOFF_DBELL"  ,	   0x11f0000011800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT1_SLIST_BAOFF_DBELL"  ,	   0x11f0000011810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT2_SLIST_BAOFF_DBELL"  ,	   0x11f0000011820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT3_SLIST_BAOFF_DBELL"  ,	   0x11f0000011830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT4_SLIST_BAOFF_DBELL"  ,	   0x11f0000011840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT5_SLIST_BAOFF_DBELL"  ,	   0x11f0000011850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT6_SLIST_BAOFF_DBELL"  ,	   0x11f0000011860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT7_SLIST_BAOFF_DBELL"  ,	   0x11f0000011870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT8_SLIST_BAOFF_DBELL"  ,	   0x11f0000011880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT9_SLIST_BAOFF_DBELL"  ,	   0x11f0000011890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT10_SLIST_BAOFF_DBELL" ,	   0x11f00000118a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT11_SLIST_BAOFF_DBELL" ,	   0x11f00000118b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT12_SLIST_BAOFF_DBELL" ,	   0x11f00000118c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT13_SLIST_BAOFF_DBELL" ,	   0x11f00000118d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT14_SLIST_BAOFF_DBELL" ,	   0x11f00000118e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT15_SLIST_BAOFF_DBELL" ,	   0x11f00000118f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT16_SLIST_BAOFF_DBELL" ,	   0x11f0000011900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT17_SLIST_BAOFF_DBELL" ,	   0x11f0000011910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT18_SLIST_BAOFF_DBELL" ,	   0x11f0000011920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT19_SLIST_BAOFF_DBELL" ,	   0x11f0000011930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT20_SLIST_BAOFF_DBELL" ,	   0x11f0000011940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT21_SLIST_BAOFF_DBELL" ,	   0x11f0000011950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT22_SLIST_BAOFF_DBELL" ,	   0x11f0000011960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT23_SLIST_BAOFF_DBELL" ,	   0x11f0000011970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT24_SLIST_BAOFF_DBELL" ,	   0x11f0000011980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT25_SLIST_BAOFF_DBELL" ,	   0x11f0000011990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT26_SLIST_BAOFF_DBELL" ,	   0x11f00000119a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT27_SLIST_BAOFF_DBELL" ,	   0x11f00000119b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT28_SLIST_BAOFF_DBELL" ,	   0x11f00000119c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT29_SLIST_BAOFF_DBELL" ,	   0x11f00000119d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT30_SLIST_BAOFF_DBELL" ,	   0x11f00000119e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT31_SLIST_BAOFF_DBELL" ,	   0x11f00000119f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT0_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT1_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT2_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT3_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT4_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT5_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT6_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT7_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT8_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT9_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT10_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT11_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT12_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT13_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT14_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT15_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT16_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT17_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT18_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT19_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT20_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT21_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT22_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT23_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT24_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT25_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT26_SLIST_FIFO_RSIZE"  ,	   0x11f0000011da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT27_SLIST_FIFO_RSIZE"  ,	   0x11f0000011db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT28_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT29_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT30_SLIST_FIFO_RSIZE"  ,	   0x11f0000011de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT31_SLIST_FIFO_RSIZE"  ,	   0x11f0000011df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT_CNT_INT"             ,	   0x11f0000011130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT_CNT_INT_ENB"         ,	   0x11f0000011150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT_CTL"                 ,	   0x11f0000011220ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT_DATA_OUT_ES"         ,	   0x11f00000110b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT_DATA_OUT_NS"         ,	   0x11f00000110a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT_DATA_OUT_ROR"        ,	   0x11f0000011090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT_DPADDR"              ,	   0x11f0000011080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT_IN_BP"               ,	   0x11f0000011210ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT_IN_DONE0_CNTS"       ,	   0x11f0000012000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE1_CNTS"       ,	   0x11f0000012010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE2_CNTS"       ,	   0x11f0000012020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE3_CNTS"       ,	   0x11f0000012030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE4_CNTS"       ,	   0x11f0000012040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE5_CNTS"       ,	   0x11f0000012050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE6_CNTS"       ,	   0x11f0000012060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE7_CNTS"       ,	   0x11f0000012070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE8_CNTS"       ,	   0x11f0000012080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE9_CNTS"       ,	   0x11f0000012090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE10_CNTS"      ,	   0x11f00000120a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE11_CNTS"      ,	   0x11f00000120b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE12_CNTS"      ,	   0x11f00000120c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE13_CNTS"      ,	   0x11f00000120d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE14_CNTS"      ,	   0x11f00000120e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE15_CNTS"      ,	   0x11f00000120f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE16_CNTS"      ,	   0x11f0000012100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE17_CNTS"      ,	   0x11f0000012110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE18_CNTS"      ,	   0x11f0000012120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE19_CNTS"      ,	   0x11f0000012130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE20_CNTS"      ,	   0x11f0000012140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE21_CNTS"      ,	   0x11f0000012150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE22_CNTS"      ,	   0x11f0000012160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE23_CNTS"      ,	   0x11f0000012170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE24_CNTS"      ,	   0x11f0000012180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE25_CNTS"      ,	   0x11f0000012190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE26_CNTS"      ,	   0x11f00000121a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE27_CNTS"      ,	   0x11f00000121b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE28_CNTS"      ,	   0x11f00000121c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE29_CNTS"      ,	   0x11f00000121d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE30_CNTS"      ,	   0x11f00000121e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_DONE31_CNTS"      ,	   0x11f00000121f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_IN_INSTR_COUNTS"     ,	   0x11f0000011200ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1011},
+	{"SLI_PKT_IN_PCIE_PORT"        ,	   0x11f00000111b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1012},
+	{"SLI_PKT_INPUT_CONTROL"       ,	   0x11f0000011170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1013},
+	{"SLI_PKT_INSTR_ENB"           ,	   0x11f0000011000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1014},
+	{"SLI_PKT_INSTR_RD_SIZE"       ,	   0x11f00000111a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1015},
+	{"SLI_PKT_INSTR_SIZE"          ,	   0x11f0000011020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1016},
+	{"SLI_PKT_INT_LEVELS"          ,	   0x11f0000011120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1017},
+	{"SLI_PKT_IPTR"                ,	   0x11f0000011070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_OUT_BMODE"           ,	   0x11f00000110d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1019},
+	{"SLI_PKT_OUT_ENB"             ,	   0x11f0000011010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1020},
+	{"SLI_PKT_OUTPUT_WMARK"        ,	   0x11f0000011180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1021},
+	{"SLI_PKT_PCIE_PORT"           ,	   0x11f00000110e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1022},
+	{"SLI_PKT_PORT_IN_RST"         ,	   0x11f00000111f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1023},
+	{"SLI_PKT_SLIST_ES"            ,	   0x11f0000011050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1024},
+	{"SLI_PKT_SLIST_NS"            ,	   0x11f0000011040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1025},
+	{"SLI_PKT_SLIST_ROR"           ,	   0x11f0000011030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1026},
+	{"SLI_PKT_TIME_INT"            ,	   0x11f0000011140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1027},
+	{"SLI_PKT_TIME_INT_ENB"        ,	   0x11f0000011160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1028},
+	{"SLI_S2M_PORT0_CTL"           ,	   0x11f0000013d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1029},
+	{"SLI_S2M_PORT1_CTL"           ,	   0x11f0000013d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1029},
+	{"SLI_SCRATCH_1"               ,	   0x11f00000103c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1030},
+	{"SLI_SCRATCH_2"               ,	   0x11f00000103d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1031},
+	{"SLI_STATE1"                  ,	   0x11f0000010620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1032},
+	{"SLI_STATE2"                  ,	   0x11f0000010630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1033},
+	{"SLI_STATE3"                  ,	   0x11f0000010640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1034},
+	{"SLI_WIN_RD_ADDR"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1035},
+	{"SLI_WIN_RD_DATA"             ,	              0x40ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1036},
+	{"SLI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1037},
+	{"SLI_WIN_WR_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1038},
+	{"SLI_WIN_WR_MASK"             ,	              0x30ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1039},
+	{"SLI_WINDOW_CTL"              ,	   0x11f00000102e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1040},
+	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"SMI1_CLK"                    ,	   0x1180000001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"SMI1_CMD"                    ,	   0x1180000001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1043},
+	{"SMI1_EN"                     ,	   0x1180000001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1043},
+	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"SMI1_RD_DAT"                 ,	   0x1180000001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"SMI1_WR_DAT"                 ,	   0x1180000001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"SMI_DRV_CTL"                 ,	   0x1180000001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1047},
+	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1049},
+	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1050},
+	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1051},
+	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1052},
+	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1053},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1054},
+	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1055},
+	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1056},
+	{"TRA0_BIST_STATUS"            ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1057},
+	{"TRA0_CTL"                    ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1058},
+	{"TRA0_CYCLES_SINCE"           ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1059},
+	{"TRA0_CYCLES_SINCE1"          ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1060},
+	{"TRA0_FILT_ADR_ADR"           ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1061},
+	{"TRA0_FILT_ADR_MSK"           ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"TRA0_FILT_CMD"               ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"TRA0_FILT_DID"               ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1064},
+	{"TRA0_FILT_SID"               ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1065},
+	{"TRA0_INT_STATUS"             ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1066},
+	{"TRA0_READ_DAT"               ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1067},
+	{"TRA0_READ_DAT_HI"            ,	   0x11800a8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1068},
+	{"TRA0_TRIG0_ADR_ADR"          ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1069},
+	{"TRA0_TRIG0_ADR_MSK"          ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1070},
+	{"TRA0_TRIG0_CMD"              ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1071},
+	{"TRA0_TRIG0_DID"              ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1072},
+	{"TRA0_TRIG0_SID"              ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1073},
+	{"TRA0_TRIG1_ADR_ADR"          ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1074},
+	{"TRA0_TRIG1_ADR_MSK"          ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1075},
+	{"TRA0_TRIG1_CMD"              ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1076},
+	{"TRA0_TRIG1_DID"              ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1077},
+	{"TRA0_TRIG1_SID"              ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1078},
+	{"UAHC0_EHCI_ASYNCLISTADDR"    ,	   0x16f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1079},
+	{"UAHC0_EHCI_CONFIGFLAG"       ,	   0x16f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1080},
+	{"UAHC0_EHCI_CTRLDSSEGMENT"    ,	   0x16f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1081},
+	{"UAHC0_EHCI_FRINDEX"          ,	   0x16f000000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1082},
+	{"UAHC0_EHCI_HCCAPBASE"        ,	   0x16f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1083},
+	{"UAHC0_EHCI_HCCPARAMS"        ,	   0x16f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1084},
+	{"UAHC0_EHCI_HCSPARAMS"        ,	   0x16f0000000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1085},
+	{"UAHC0_EHCI_INSNREG00"        ,	   0x16f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1086},
+	{"UAHC0_EHCI_INSNREG03"        ,	   0x16f000000009cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1087},
+	{"UAHC0_EHCI_INSNREG04"        ,	   0x16f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1088},
+	{"UAHC0_EHCI_INSNREG06"        ,	   0x16f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1089},
+	{"UAHC0_EHCI_INSNREG07"        ,	   0x16f00000000ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	1090},
+	{"UAHC0_EHCI_PERIODICLISTBASE" ,	   0x16f0000000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1091},
+	{"UAHC0_EHCI_PORTSC001"        ,	   0x16f0000000054ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1092},
+	{"UAHC0_EHCI_PORTSC002"        ,	   0x16f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1092},
+	{"UAHC0_EHCI_USBCMD"           ,	   0x16f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1093},
+	{"UAHC0_EHCI_USBINTR"          ,	   0x16f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1094},
+	{"UAHC0_EHCI_USBSTS"           ,	   0x16f0000000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1095},
+	{"UAHC0_OHCI0_HCBULKCURRENTED" ,	   0x16f000000042cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1096},
+	{"UAHC0_OHCI0_HCBULKHEADED"    ,	   0x16f0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1097},
+	{"UAHC0_OHCI0_HCCOMMANDSTATUS" ,	   0x16f0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1098},
+	{"UAHC0_OHCI0_HCCONTROL"       ,	   0x16f0000000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1099},
+	{"UAHC0_OHCI0_HCCONTROLCURRENTED",	   0x16f0000000424ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1100},
+	{"UAHC0_OHCI0_HCCONTROLHEADED" ,	   0x16f0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1101},
+	{"UAHC0_OHCI0_HCDONEHEAD"      ,	   0x16f0000000430ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1102},
+	{"UAHC0_OHCI0_HCFMINTERVAL"    ,	   0x16f0000000434ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1103},
+	{"UAHC0_OHCI0_HCFMNUMBER"      ,	   0x16f000000043cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1104},
+	{"UAHC0_OHCI0_HCFMREMAINING"   ,	   0x16f0000000438ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1105},
+	{"UAHC0_OHCI0_HCHCCA"          ,	   0x16f0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1106},
+	{"UAHC0_OHCI0_HCINTERRUPTDISABLE",	   0x16f0000000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1107},
+	{"UAHC0_OHCI0_HCINTERRUPTENABLE",	   0x16f0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1108},
+	{"UAHC0_OHCI0_HCINTERRUPTSTATUS",	   0x16f000000040cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1109},
+	{"UAHC0_OHCI0_HCLSTHRESHOLD"   ,	   0x16f0000000444ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1110},
+	{"UAHC0_OHCI0_HCPERIODCURRENTED",	   0x16f000000041cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1111},
+	{"UAHC0_OHCI0_HCPERIODICSTART" ,	   0x16f0000000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1112},
+	{"UAHC0_OHCI0_HCREVISION"      ,	   0x16f0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1113},
+	{"UAHC0_OHCI0_HCRHDESCRIPTORA" ,	   0x16f0000000448ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1114},
+	{"UAHC0_OHCI0_HCRHDESCRIPTORB" ,	   0x16f000000044cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1115},
+	{"UAHC0_OHCI0_HCRHPORTSTATUS001",	   0x16f0000000454ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1116},
+	{"UAHC0_OHCI0_HCRHPORTSTATUS002",	   0x16f0000000458ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1116},
+	{"UAHC0_OHCI0_HCRHSTATUS"      ,	   0x16f0000000450ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1117},
+	{"UAHC0_OHCI0_INSNREG06"       ,	   0x16f0000000498ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1118},
+	{"UAHC0_OHCI0_INSNREG07"       ,	   0x16f000000049cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1119},
+	{"UCTL0_BIST_STATUS"           ,	   0x118006f0000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1120},
+	{"UCTL0_CLK_RST_CTL"           ,	   0x118006f000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1121},
+	{"UCTL0_EHCI_CTL"              ,	   0x118006f000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1122},
+	{"UCTL0_EHCI_FLA"              ,	   0x118006f0000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1123},
+	{"UCTL0_ERTO_CTL"              ,	   0x118006f000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1124},
+	{"UCTL0_IF_ENA"                ,	   0x118006f000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1125},
+	{"UCTL0_INT_ENA"               ,	   0x118006f000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1126},
+	{"UCTL0_INT_REG"               ,	   0x118006f000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1127},
+	{"UCTL0_OHCI_CTL"              ,	   0x118006f000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1128},
+	{"UCTL0_ORTO_CTL"              ,	   0x118006f000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1129},
+	{"UCTL0_PPAF_WM"               ,	   0x118006f000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1130},
+	{"UCTL0_UPHY_CTL_STATUS"       ,	   0x118006f000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1131},
+	{"UCTL0_UPHY_PORT000_CTL_STATUS",	   0x118006f000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1132},
+	{"UCTL0_UPHY_PORT001_CTL_STATUS",	   0x118006f000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1132},
+	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1133},
+	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1134},
+	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1135},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1136},
+	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1137},
+	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1138},
+	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1139},
+	{"ZIP_THROTTLE"                ,	   0x1180038000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1140},
+	{NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn61xx[] = {
+	/* name                        ,	bit,	width,	csr,	type,	rst un,	typ un,	reset,	typical */
+	{"RESERVED_0_1"                ,	0,	2,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OUT_OVR"                     ,	2,	2,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_21"               ,	4,	18,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LOSTSTAT"                    ,	22,	2,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_25"              ,	24,	2,	0,	"RAZ",	1,	1,	0,	0},
+	{"STATOVR"                     ,	26,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_31"              ,	27,	5,	0,	"RAZ",	1,	1,	0,	0},
+	{"OVRFLW"                      ,	32,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP"                       ,	33,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH"                       ,	34,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRFLW1"                     ,	35,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP1"                      ,	36,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH1"                      ,	37,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	0,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	25,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	2,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	2,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	2,	"R/W",	0,	1,	1ull,	0},
+	{"RX_EN"                       ,	4,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"TX_EN"                       ,	5,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"BURST"                       ,	6,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	2,	"RAZ",	1,	1,	0,	0},
+	{"SPEED_MSB"                   ,	8,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	2,	"RAZ",	1,	1,	0,	0},
+	{"RX_IDLE"                     ,	12,	1,	2,	"RO",	0,	1,	1ull,	0},
+	{"TX_IDLE"                     ,	13,	1,	2,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	2,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	3,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	4,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	5,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	6,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	7,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	8,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	9,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	9,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	10,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	10,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	10,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	10,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	11,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	11,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR"                      ,	2,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"JABBER"                      ,	3,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALNERR"                      ,	5,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR"                      ,	6,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"RCVERR"                      ,	7,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"NIBERR"                      ,	9,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	12,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	13,	"RO",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	7,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	8,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_ALIGN"                   ,	9,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"NULL_DIS"                    ,	10,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	13,	"RAZ",	1,	1,	0,	0},
+	{"PTP_MODE"                    ,	12,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	13,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	14,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_16_63"              ,	16,	48,	14,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	15,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_16_63"              ,	16,	48,	15,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	16,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	16,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	17,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	18,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	19,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	19,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	20,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	20,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	1,	21,	"RO",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	2,	21,	"RO",	0,	1,	0ull,	0},
+	{"DUPLEX"                      ,	3,	1,	21,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	21,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	22,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	22,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	23,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	23,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	24,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	24,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	25,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	25,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	26,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	26,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	27,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	27,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	28,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	28,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	29,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	29,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	30,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	30,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	31,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	31,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	32,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	32,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	32,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	32,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	33,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	33,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	34,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	34,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	35,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_9_63"               ,	9,	55,	35,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	2,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_15"               ,	2,	14,	36,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	2,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	36,	"RAZ",	1,	1,	0,	0},
+	{"RX"                          ,	0,	2,	37,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	37,	"RAZ",	1,	1,	0,	0},
+	{"TX"                          ,	4,	2,	37,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	37,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	38,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	38,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	39,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	39,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	40,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	6,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_63"               ,	6,	58,	41,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	42,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	43,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	43,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	44,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	44,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	45,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	45,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	46,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	46,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	47,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	47,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	48,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	48,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	51,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	51,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	52,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	52,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	59,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	6,	60,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	60,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	2,	61,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	61,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	62,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	62,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	63,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	63,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	63,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	64,	"RAZ",	1,	1,	0,	0},
+	{"UNDFLW"                      ,	2,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	64,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	8,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"XSDEF"                       ,	12,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"LATE_COL"                    ,	16,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"PTP_LOST"                    ,	20,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	64,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	65,	"RAZ",	1,	1,	0,	0},
+	{"UNDFLW"                      ,	2,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	65,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	8,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"XSDEF"                       ,	12,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"LATE_COL"                    ,	16,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"PTP_LOST"                    ,	20,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	65,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	66,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	66,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	67,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	67,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	68,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	4,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	68,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	8,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	68,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	69,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	69,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	70,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	70,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	1,	71,	"RO",	0,	0,	0ull,	0ull},
+	{"CLKRST"                      ,	1,	1,	71,	"R/W",	0,	0,	1ull,	0ull},
+	{"ENABLE"                      ,	2,	1,	71,	"R/W",	0,	0,	1ull,	1ull},
+	{"COMP"                        ,	3,	1,	71,	"R/W",	0,	0,	0ull,	1ull},
+	{"DLLRST"                      ,	4,	1,	71,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	71,	"RAZ",	1,	1,	0,	0},
+	{"CLKTX_SET"                   ,	8,	5,	71,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_14"              ,	13,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CLKTX_BYP"                   ,	15,	1,	71,	"R/W",	0,	1,	1ull,	0},
+	{"CLKRX_SET"                   ,	16,	5,	71,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_22"              ,	21,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CLKRX_BYP"                   ,	23,	1,	71,	"R/W",	0,	1,	0ull,	0},
+	{"CLK_SET"                     ,	24,	5,	71,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_31"              ,	29,	3,	71,	"RAZ",	1,	1,	0,	0},
+	{"DRV_NCTL"                    ,	32,	6,	71,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_38_39"              ,	38,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"DRV_PCTL"                    ,	40,	6,	71,	"R/W",	0,	1,	19ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CMP_NCTL"                    ,	48,	6,	71,	"RO",	1,	1,	0,	0},
+	{"RESERVED_54_55"              ,	54,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CMP_PCTL"                    ,	56,	6,	71,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	71,	"RAZ",	1,	1,	0,	0},
+	{"DRV_BYP"                     ,	63,	1,	71,	"R/W",	0,	0,	1ull,	0ull},
+	{"BIST"                        ,	0,	6,	72,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	72,	"RAZ",	1,	1,	0,	0},
+	{"MIO"                         ,	0,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX0"                        ,	1,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX1"                        ,	2,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	3,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	4,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	5,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	6,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	7,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_8"                ,	8,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"IPD"                         ,	9,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	10,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	11,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	12,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	13,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	14,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	16,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	17,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	73,	"RAZ",	1,	1,	0,	0},
+	{"PIP"                         ,	20,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_21"              ,	21,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"ASXPCS0"                     ,	22,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"ASXPCS1"                     ,	23,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_24"              ,	24,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"PEM0"                        ,	25,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	26,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	28,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_29"              ,	29,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	30,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_40"              ,	31,	10,	73,	"RAZ",	1,	1,	0,	0},
+	{"DPI"                         ,	41,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	42,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	73,	"RAZ",	1,	1,	0,	0},
+	{"DINT"                        ,	0,	4,	74,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	74,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	75,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	75,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	76,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	76,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	77,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	77,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	78,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	78,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	78,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	79,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	79,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	79,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	80,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	80,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	80,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	81,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	81,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	82,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	82,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	83,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	83,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	84,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	84,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	84,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	85,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	85,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	85,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	86,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	86,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	86,	"RAZ",	1,	1,	0,	0},
+	{"FUSE"                        ,	0,	4,	87,	"RO",	1,	1,	0,	0},
+	{"RESERVED_4_63"               ,	4,	60,	87,	"RAZ",	1,	1,	0,	0},
+	{"GSTOP"                       ,	0,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	88,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	89,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	89,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	90,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	90,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	91,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	91,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_17"               ,	4,	14,	92,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI_DMA"                     ,	40,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_45"              ,	41,	5,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_17"               ,	4,	14,	93,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI_DMA"                     ,	40,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_45"              ,	41,	5,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_17"               ,	4,	14,	94,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI_DMA"                     ,	40,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_45"              ,	41,	5,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	95,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	95,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	96,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	96,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	97,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	97,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_17"               ,	4,	14,	98,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI_DMA"                     ,	40,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_45"              ,	41,	5,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_17"               ,	4,	14,	99,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI_DMA"                     ,	40,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_45"              ,	41,	5,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_17"               ,	4,	14,	100,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI_DMA"                     ,	40,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_45"              ,	41,	5,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SUM2"                        ,	51,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	102,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	102,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	102,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SUM2"                        ,	51,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	102,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	102,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	103,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	103,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	103,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SUM2"                        ,	51,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	103,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	103,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	4,	104,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	104,	"RAZ",	1,	1,	0,	0},
+	{"IRQ"                         ,	8,	2,	104,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	104,	"RAZ",	1,	1,	0,	0},
+	{"SEL"                         ,	16,	3,	104,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_19_63"              ,	19,	45,	104,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	4,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_17"               ,	4,	14,	105,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_45"              ,	38,	8,	105,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	46,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	105,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	105,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"BITS"                        ,	0,	32,	106,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	106,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	107,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	107,	"RAZ",	1,	1,	0,	0},
+	{"NMI"                         ,	0,	4,	108,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	108,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	2,	109,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	109,	"RAZ",	1,	1,	0,	0},
+	{"PPDBG"                       ,	0,	4,	110,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	110,	"RAZ",	1,	1,	0,	0},
+	{"POKE"                        ,	0,	64,	111,	"RAZ",	1,	1,	0,	0},
+	{"RST0"                        ,	0,	1,	112,	"R/W",	1,	1,	0,	0},
+	{"RST"                         ,	1,	3,	112,	"R/W",	0,	0,	7ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	112,	"RAZ",	1,	1,	0,	0},
+	{"LANE_EN"                     ,	0,	4,	113,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	113,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	113,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	113,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	113,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	113,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	113,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_39"              ,	32,	8,	113,	"RAZ",	1,	1,	0,	0},
+	{"G2MARGIN"                    ,	40,	5,	113,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	113,	"RAZ",	1,	1,	0,	0},
+	{"G2DEEMPH"                    ,	48,	5,	113,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_53_62"              ,	53,	10,	113,	"RAZ",	1,	1,	0,	0},
+	{"G2BYPASS"                    ,	63,	1,	113,	"R/W",	0,	1,	0ull,	0},
+	{"LANE_EN"                     ,	0,	4,	114,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	114,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	114,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	114,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	114,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	114,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	114,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_39"              ,	32,	8,	114,	"RAZ",	1,	1,	0,	0},
+	{"G2MARGIN"                    ,	40,	5,	114,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	114,	"RAZ",	1,	1,	0,	0},
+	{"G2DEEMPH"                    ,	48,	5,	114,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_53_62"              ,	53,	10,	114,	"RAZ",	1,	1,	0,	0},
+	{"G2BYPASS"                    ,	63,	1,	114,	"R/W",	0,	1,	0ull,	0},
+	{"LANE_EN"                     ,	0,	4,	115,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	115,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	115,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	115,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	115,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	115,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	115,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	115,	"RAZ",	1,	1,	0,	0},
+	{"BYPASS"                      ,	0,	3,	116,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	116,	"RAZ",	1,	1,	0,	0},
+	{"MUX_SEL"                     ,	4,	2,	116,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	116,	"RAZ",	1,	1,	0,	0},
+	{"CLK_DIV"                     ,	8,	3,	116,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	116,	"RAZ",	1,	1,	0,	0},
+	{"SHFT_REG"                    ,	0,	32,	117,	"R/W",	0,	1,	0ull,	0},
+	{"SHFT_CNT"                    ,	32,	5,	117,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_37_39"              ,	37,	3,	117,	"RAZ",	1,	1,	0,	0},
+	{"SELECT"                      ,	40,	3,	117,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_43_60"              ,	43,	18,	117,	"RAZ",	1,	1,	0,	0},
+	{"UPDATE"                      ,	61,	1,	117,	"R/W",	0,	1,	0ull,	0},
+	{"SHIFT"                       ,	62,	1,	117,	"R/W",	0,	1,	0ull,	0},
+	{"CAPTURE"                     ,	63,	1,	117,	"R/W",	0,	1,	0ull,	0},
+	{"SOFT_BIST"                   ,	0,	1,	118,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	118,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	119,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	119,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	120,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	120,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST"                    ,	0,	1,	121,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	121,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	4,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_17"               ,	4,	14,	122,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	122,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	40,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_45"              ,	41,	5,	122,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	46,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	122,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	122,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_17"               ,	4,	14,	123,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	123,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	40,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_45"              ,	41,	5,	123,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	46,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	123,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	123,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	123,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_17"               ,	4,	14,	124,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	124,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	40,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_45"              ,	41,	5,	124,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	46,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	124,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	124,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	124,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_17"               ,	4,	14,	125,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	125,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	40,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_45"              ,	41,	5,	125,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	46,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	125,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	125,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	125,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	126,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	126,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	126,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	127,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	127,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	127,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	128,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	128,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	129,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	129,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	129,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	36,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"ONE_SHOT"                    ,	36,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	130,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	131,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	131,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	132,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	2,	2,	132,	"RO",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	4,	16,	132,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	20,	24,	132,	"RO",	0,	0,	0ull,	0ull},
+	{"DSTOP"                       ,	44,	1,	132,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSTOPEN"                     ,	45,	1,	132,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	132,	"RAZ",	1,	1,	0,	0},
+	{"PDB"                         ,	0,	1,	133,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	133,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RDF"                         ,	4,	1,	133,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	133,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTX"                         ,	8,	2,	133,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	133,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STX"                         ,	16,	2,	133,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_23"              ,	18,	6,	133,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GFB"                         ,	24,	1,	133,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	133,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GFU"                         ,	0,	1,	134,	"RO",	0,	0,	0ull,	0ull},
+	{"GIB"                         ,	1,	1,	134,	"RO",	0,	0,	0ull,	0ull},
+	{"GIF"                         ,	2,	1,	134,	"RO",	0,	0,	0ull,	0ull},
+	{"NCD"                         ,	3,	1,	134,	"RO",	0,	0,	0ull,	0ull},
+	{"GUTP"                        ,	4,	1,	134,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	134,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GUTV"                        ,	8,	1,	134,	"RO",	0,	0,	0ull,	0ull},
+	{"CRQ"                         ,	9,	1,	134,	"RO",	0,	0,	0ull,	0ull},
+	{"RAM1"                        ,	10,	1,	134,	"RO",	0,	0,	0ull,	0ull},
+	{"RAM2"                        ,	11,	1,	134,	"RO",	0,	0,	0ull,	0ull},
+	{"RAM3"                        ,	12,	1,	134,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_18"              ,	13,	6,	134,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DLC0RAM"                     ,	19,	1,	134,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	134,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTECLKDIS"                   ,	0,	1,	135,	"R/W",	0,	0,	1ull,	0ull},
+	{"CLDTECRIP"                   ,	1,	3,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLMSKCRIP"                   ,	4,	4,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"REPL_ENA"                    ,	8,	1,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLCSTART_BIST"               ,	9,	1,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLCCLEAR_BIST"               ,	10,	1,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	135,	"RAZ",	1,	1,	0,	0},
+	{"IMODE"                       ,	0,	1,	136,	"R/W",	0,	0,	1ull,	1ull},
+	{"QMODE"                       ,	1,	1,	136,	"R/W",	0,	0,	1ull,	1ull},
+	{"PMODE"                       ,	2,	1,	136,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_4"                ,	3,	2,	136,	"RAZ",	1,	1,	0,	0},
+	{"SBDLCK"                      ,	5,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBDNUM"                      ,	6,	4,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	136,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	20,	137,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	137,	"RAZ",	1,	1,	0,	0},
+	{"SBD0"                        ,	0,	64,	138,	"RO",	1,	1,	0,	0},
+	{"SBD1"                        ,	0,	64,	139,	"RO",	1,	1,	0,	0},
+	{"SBD2"                        ,	0,	64,	140,	"RO",	1,	1,	0,	0},
+	{"SBD3"                        ,	0,	64,	141,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	9,	142,	"R/W",	0,	1,	3ull,	0},
+	{"POOL"                        ,	9,	3,	142,	"R/W",	0,	1,	0ull,	0},
+	{"DWBCNT"                      ,	12,	8,	142,	"R/W",	0,	1,	1ull,	0},
+	{"MSEGBASE"                    ,	20,	6,	142,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	142,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	143,	"RAZ",	1,	1,	0,	0},
+	{"RDPTR"                       ,	5,	35,	143,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	143,	"RAZ",	1,	1,	0,	0},
+	{"RAM1FADR"                    ,	0,	14,	144,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	144,	"RAZ",	1,	1,	0,	0},
+	{"RAM2FADR"                    ,	16,	9,	144,	"RO",	1,	1,	0,	0},
+	{"RESERVED_25_31"              ,	25,	7,	144,	"RAZ",	1,	1,	0,	0},
+	{"RAM3FADR"                    ,	32,	12,	144,	"RO",	1,	1,	0,	0},
+	{"RESERVED_44_63"              ,	44,	20,	144,	"RAZ",	1,	1,	0,	0},
+	{"DBLOVF"                      ,	0,	1,	145,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC0PERR"                     ,	1,	3,	145,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_12"               ,	4,	9,	145,	"RAZ",	1,	1,	0,	0},
+	{"DLC0_OVFERR"                 ,	13,	1,	145,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	145,	"RAZ",	1,	1,	0,	0},
+	{"CNDRD"                       ,	16,	1,	145,	"RO",	0,	0,	0ull,	0ull},
+	{"DFANXM"                      ,	17,	1,	145,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REPLERR"                     ,	18,	1,	145,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	145,	"RAZ",	1,	1,	0,	0},
+	{"DBLINA"                      ,	0,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC0PENA"                     ,	1,	3,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_12"               ,	4,	9,	146,	"RAZ",	1,	1,	0,	0},
+	{"DLC0_OVFENA"                 ,	13,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_16"              ,	14,	3,	146,	"RAZ",	1,	1,	0,	0},
+	{"DFANXMENA"                   ,	17,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"REPLERRENA"                  ,	18,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	146,	"RAZ",	1,	1,	0,	0},
+	{"HIDAT"                       ,	0,	64,	147,	"R/W",	1,	1,	0,	0},
+	{"PFCNT0"                      ,	0,	64,	148,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	149,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	149,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	149,	"RAZ",	1,	1,	0,	0},
+	{"PFCNT1"                      ,	0,	64,	150,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	151,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	151,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	151,	"RAZ",	1,	1,	0,	0},
+	{"PFCNT2"                      ,	0,	64,	152,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	153,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	153,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	153,	"RAZ",	1,	1,	0,	0},
+	{"PFCNT3"                      ,	0,	64,	154,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	155,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	155,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	155,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	155,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	155,	"RAZ",	1,	1,	0,	0},
+	{"CNT0ENA"                     ,	0,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1ENA"                     ,	1,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2ENA"                     ,	2,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3ENA"                     ,	3,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0WCLR"                    ,	4,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1WCLR"                    ,	5,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2WCLR"                    ,	6,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3WCLR"                    ,	7,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0RCLR"                    ,	8,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1RCLR"                    ,	9,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2RCLR"                    ,	10,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3RCLR"                    ,	11,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"SNODE"                       ,	12,	3,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENODE"                       ,	15,	3,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"EDNODE"                      ,	18,	2,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMODE"                       ,	20,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGID"                        ,	21,	8,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	156,	"RAZ",	1,	1,	0,	0},
+	{"BIST"                        ,	0,	47,	157,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	157,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	158,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	158,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	159,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	159,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	159,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	160,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	160,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	6,	161,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	161,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_6"                ,	0,	7,	162,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	7,	29,	162,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	162,	"RAZ",	1,	1,	0,	0},
+	{"IDLE"                        ,	40,	1,	162,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_41_47"              ,	41,	7,	162,	"RAZ",	1,	1,	0,	0},
+	{"CSIZE"                       ,	48,	14,	162,	"R/W",	0,	1,	64ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	162,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	3,	163,	"R/W",	0,	0,	6ull,	6ull},
+	{"RESERVED_3_63"               ,	3,	61,	163,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	164,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	164,	"RAZ",	1,	1,	0,	0},
+	{"STATE"                       ,	0,	64,	165,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	0,	64,	166,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_13"               ,	0,	14,	167,	"RAZ",	1,	1,	0,	0},
+	{"O_MODE"                      ,	14,	1,	167,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ES"                        ,	15,	2,	167,	"R/W",	0,	1,	0ull,	0},
+	{"O_NS"                        ,	17,	1,	167,	"R/W",	0,	1,	0ull,	0},
+	{"O_RO"                        ,	18,	1,	167,	"R/W",	0,	1,	0ull,	0},
+	{"O_ADD1"                      ,	19,	1,	167,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA_QUE"                     ,	20,	3,	167,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_ICHK"                    ,	23,	9,	167,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_DENB"                    ,	32,	1,	167,	"R/W",	0,	0,	0ull,	1ull},
+	{"B0_LEND"                     ,	33,	1,	167,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_47"              ,	34,	14,	167,	"RAZ",	1,	1,	0,	0},
+	{"DMA_ENB"                     ,	48,	6,	167,	"R/W",	0,	0,	0ull,	63ull},
+	{"RESERVED_54_55"              ,	54,	2,	167,	"RAZ",	1,	1,	0,	0},
+	{"PKT_EN"                      ,	56,	1,	167,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_HP"                      ,	57,	1,	167,	"RO",	0,	0,	0ull,	0ull},
+	{"COMMIT_MODE"                 ,	58,	1,	167,	"R/W",	0,	0,	0ull,	1ull},
+	{"FFP_DIS"                     ,	59,	1,	167,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_EN1"                     ,	60,	1,	167,	"R/W",	0,	1,	0ull,	0},
+	{"DICI_MODE"                   ,	61,	1,	167,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	167,	"RAZ",	1,	1,	0,	0},
+	{"QEN"                         ,	0,	8,	168,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	168,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	169,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	169,	"RAZ",	1,	1,	0,	0},
+	{"BLKS"                        ,	0,	4,	170,	"R/W",	0,	1,	2ull,	0},
+	{"BASE"                        ,	4,	5,	170,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_31"               ,	9,	23,	170,	"RAZ",	1,	1,	0,	0},
+	{"COMPBLKS"                    ,	32,	5,	170,	"RO",	1,	1,	0,	0},
+	{"RESERVED_37_63"              ,	37,	27,	170,	"RAZ",	1,	1,	0,	0},
+	{"RSL"                         ,	0,	1,	171,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NCB"                         ,	1,	1,	171,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	171,	"RAZ",	1,	1,	0,	0},
+	{"FFP"                         ,	4,	4,	171,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	171,	"RAZ",	1,	1,	0,	0},
+	{"NDERR"                       ,	0,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFOVR"                       ,	1,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMADBO"                      ,	8,	8,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADADR"                  ,	16,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADLEN"                  ,	17,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_OVRFLW"                  ,	18,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_UNDFLW"                  ,	19,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_ANULL"                   ,	20,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_INULL"                   ,	21,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADFIL"                  ,	22,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	172,	"R/W",	1,	1,	0,	0},
+	{"SPRT0_RST"                   ,	24,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_RST"                   ,	25,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT2_RST"                   ,	26,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT3_RST"                   ,	27,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	172,	"RAZ",	1,	1,	0,	0},
+	{"NDERR"                       ,	0,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFOVR"                       ,	1,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	173,	"RAZ",	1,	1,	0,	0},
+	{"DMADBO"                      ,	8,	8,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADADR"                  ,	16,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADLEN"                  ,	17,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_OVRFLW"                  ,	18,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_UNDFLW"                  ,	19,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_ANULL"                   ,	20,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_INULL"                   ,	21,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADFIL"                  ,	22,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	173,	"RAZ",	1,	1,	0,	0},
+	{"SPRT0_RST"                   ,	24,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT1_RST"                   ,	25,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT2_RST"                   ,	26,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT3_RST"                   ,	27,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	173,	"RAZ",	1,	1,	0,	0},
+	{"MOLR"                        ,	0,	6,	174,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	174,	"RAZ",	1,	1,	0,	0},
+	{"SINFO"                       ,	0,	6,	175,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	175,	"RAZ",	1,	1,	0,	0},
+	{"IINFO"                       ,	8,	6,	175,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	175,	"RAZ",	1,	1,	0,	0},
+	{"PKTERR"                      ,	0,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	176,	"RAZ",	1,	1,	0,	0},
+	{"QERR"                        ,	0,	8,	177,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	177,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	178,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	178,	"RAZ",	1,	1,	0,	0},
+	{"QERR"                        ,	0,	8,	179,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	179,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	180,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	180,	"RAZ",	1,	1,	0,	0},
+	{"EN_RSP"                      ,	0,	8,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	181,	"RAZ",	1,	1,	0,	0},
+	{"EN_RST"                      ,	16,	8,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	181,	"RAZ",	1,	1,	0,	0},
+	{"QEN"                         ,	0,	8,	182,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	182,	"RAZ",	1,	1,	0,	0},
+	{"MRRS"                        ,	0,	2,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	183,	"RAZ",	1,	1,	0,	0},
+	{"MRRS_LIM"                    ,	3,	1,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPS"                         ,	4,	1,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	183,	"RAZ",	1,	1,	0,	0},
+	{"MPS_LIM"                     ,	7,	1,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"MOLR"                        ,	8,	6,	183,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	183,	"RAZ",	1,	1,	0,	0},
+	{"RD_MODE"                     ,	16,	1,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	183,	"RAZ",	1,	1,	0,	0},
+	{"QLM_CFG"                     ,	20,	4,	183,	"RO",	1,	1,	0,	0},
+	{"HALT"                        ,	24,	1,	183,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	183,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	184,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	61,	184,	"RO",	0,	1,	0ull,	0},
+	{"REQQ"                        ,	0,	3,	185,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	185,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	4,	1,	185,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	185,	"RAZ",	1,	1,	0,	0},
+	{"LOCK"                        ,	8,	1,	185,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	185,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	33,	186,	"RO",	0,	1,	0ull,	0},
+	{"POOL"                        ,	33,	5,	186,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	186,	"RAZ",	1,	1,	0,	0},
+	{"FDR"                         ,	0,	1,	187,	"RO",	0,	0,	0ull,	0ull},
+	{"FFR"                         ,	1,	1,	187,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF1"                        ,	2,	1,	187,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF0"                        ,	3,	1,	187,	"RO",	0,	0,	0ull,	0ull},
+	{"FRD"                         ,	4,	1,	187,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	187,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	14,	1,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_STT"                     ,	15,	1,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_LDT"                     ,	16,	1,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_OFF"                     ,	18,	1,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"RET_OFF"                     ,	19,	1,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE_EN"                     ,	20,	1,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	188,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	11,	189,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	11,	11,	189,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	189,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	11,	190,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	190,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	12,	191,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	12,	12,	191,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	191,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	12,	192,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	192,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL0TH"                     ,	28,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL1TH"                     ,	29,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL2TH"                     ,	30,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL3TH"                     ,	31,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL4TH"                     ,	32,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL5TH"                     ,	33,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL6TH"                     ,	34,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL7TH"                     ,	35,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE0"                       ,	36,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE1"                       ,	37,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE2"                       ,	38,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE3"                       ,	39,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE4"                       ,	40,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE5"                       ,	41,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE6"                       ,	42,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE7"                       ,	43,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"RES_44"                      ,	44,	5,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"PADDR_E"                     ,	49,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_63"              ,	50,	14,	193,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL0TH"                     ,	28,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL1TH"                     ,	29,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL2TH"                     ,	30,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL3TH"                     ,	31,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL4TH"                     ,	32,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL5TH"                     ,	33,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL6TH"                     ,	34,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL7TH"                     ,	35,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE0"                       ,	36,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE1"                       ,	37,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE2"                       ,	38,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE3"                       ,	39,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE4"                       ,	40,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE5"                       ,	41,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE6"                       ,	42,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE7"                       ,	43,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_48"              ,	44,	5,	194,	"RAZ",	1,	1,	0,	0},
+	{"PADDR_E"                     ,	49,	1,	194,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_63"              ,	50,	14,	194,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	32,	195,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	195,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	33,	196,	"R/W",	0,	1,	8589934591ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	196,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	33,	197,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	197,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	29,	198,	"R/W",	0,	0,	536870911ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	198,	"RAZ",	1,	1,	0,	0},
+	{"QUE_SIZ"                     ,	0,	29,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	199,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	200,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	200,	"RAZ",	1,	1,	0,	0},
+	{"ACT_INDX"                    ,	0,	26,	201,	"RO",	0,	1,	0ull,	0},
+	{"ACT_QUE"                     ,	26,	3,	201,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	201,	"RO",	0,	0,	0ull,	7ull},
+	{"EXP_INDX"                    ,	0,	26,	202,	"RO",	0,	1,	0ull,	0},
+	{"EXP_QUE"                     ,	26,	3,	202,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	202,	"RO",	0,	0,	0ull,	7ull},
+	{"THRESH"                      ,	0,	32,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	203,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	204,	"RAZ",	1,	1,	0,	0},
+	{"OUT_OVR"                     ,	2,	4,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_21"               ,	6,	16,	204,	"RAZ",	1,	1,	0,	0},
+	{"LOSTSTAT"                    ,	22,	4,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INB_NXA"                     ,	27,	4,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	204,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	25,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	205,	"RAZ",	1,	1,	0,	0},
+	{"CLK_EN"                      ,	0,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	206,	"RAZ",	1,	1,	0,	0},
+	{"LOGL_EN"                     ,	0,	16,	207,	"R/W",	0,	1,	65535ull,	0},
+	{"PHYS_EN"                     ,	16,	1,	207,	"R/W",	0,	1,	1ull,	0},
+	{"HG2RX_EN"                    ,	17,	1,	207,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2TX_EN"                    ,	18,	1,	207,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	207,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	1,	208,	"RO",	0,	1,	0ull,	0},
+	{"EN"                          ,	1,	1,	208,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_3"                ,	2,	2,	208,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	4,	1,	208,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	208,	"RAZ",	1,	1,	0,	0},
+	{"SPEED"                       ,	8,	4,	208,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	208,	"RAZ",	1,	1,	0,	0},
+	{"PRT"                         ,	0,	6,	209,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	209,	"RAZ",	1,	1,	0,	0},
+	{"RX_EN"                       ,	0,	1,	210,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_EN"                       ,	1,	1,	210,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRP_EN"                      ,	2,	1,	210,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCK_EN"                      ,	3,	1,	210,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	210,	"RAZ",	1,	1,	0,	0},
+	{"PHYS_BP"                     ,	16,	16,	210,	"R/W",	0,	1,	65535ull,	0},
+	{"LOGL_EN"                     ,	32,	16,	210,	"R/W",	0,	0,	255ull,	255ull},
+	{"PHYS_EN"                     ,	48,	16,	210,	"R/W",	0,	0,	255ull,	255ull},
+	{"EN"                          ,	0,	1,	211,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	211,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	211,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	211,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	211,	"RAZ",	1,	1,	0,	0},
+	{"SPEED_MSB"                   ,	8,	1,	211,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	211,	"RAZ",	1,	1,	0,	0},
+	{"RX_IDLE"                     ,	12,	1,	211,	"RO",	0,	1,	1ull,	0},
+	{"TX_IDLE"                     ,	13,	1,	211,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	211,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	212,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	213,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	214,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	215,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	216,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	217,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	32,	218,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	218,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	219,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	219,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	220,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	220,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	220,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	220,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	221,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	221,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	222,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	222,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_2"                ,	2,	1,	222,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	222,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	222,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_6"                ,	5,	2,	222,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	222,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	222,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	222,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	223,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	223,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	223,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	223,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	223,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	223,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_8"                ,	7,	2,	223,	"RAZ",	1,	1,	0,	0},
+	{"PRE_ALIGN"                   ,	9,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"NULL_DIS"                    ,	10,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	223,	"RAZ",	1,	1,	0,	0},
+	{"PTP_MODE"                    ,	12,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	223,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	224,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	224,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	225,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	225,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	225,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	225,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	225,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	226,	"R/W1C",	0,	1,	0ull,	0},
+	{"CAREXT"                      ,	1,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	226,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	226,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	226,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	226,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	226,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	226,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	227,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	227,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	228,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	228,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	229,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	229,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	230,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	230,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	231,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	231,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	232,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	232,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	233,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	233,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	234,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	234,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	235,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	235,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	236,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	236,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	237,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	237,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	238,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	238,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	239,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	239,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	240,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	240,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	241,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	241,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	242,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_9_63"               ,	9,	55,	242,	"RAZ",	1,	1,	0,	0},
+	{"LGTIM2GO"                    ,	0,	16,	243,	"RO",	0,	1,	0ull,	0},
+	{"XOF"                         ,	16,	16,	243,	"RO",	0,	0,	0ull,	0ull},
+	{"PHTIM2GO"                    ,	32,	16,	243,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	243,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	4,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	244,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	4,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	244,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	3,	245,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_3_63"               ,	3,	61,	245,	"RAZ",	1,	1,	0,	0},
+	{"LANE_RXD"                    ,	0,	32,	246,	"RO",	0,	1,	0ull,	0},
+	{"LANE_RXC"                    ,	32,	4,	246,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	3,	246,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	39,	1,	246,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	246,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	2,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	247,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	248,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	248,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	249,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	249,	"RAZ",	1,	1,	0,	0},
+	{"WR_MAGIC"                    ,	0,	1,	250,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	250,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	251,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	251,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	251,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	251,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	251,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	16,	252,	"R/W",	0,	0,	8192ull,	8192ull},
+	{"RESERVED_16_63"              ,	16,	48,	252,	"RAZ",	1,	1,	0,	0},
+	{"XOFF"                        ,	0,	16,	253,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	253,	"RAZ",	1,	1,	0,	0},
+	{"XON"                         ,	0,	16,	254,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	254,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	255,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	255,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	255,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	256,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	256,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	257,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	257,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	258,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	258,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	259,	"RO",	1,	1,	0,	0},
+	{"MSG_TIME"                    ,	16,	16,	259,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	259,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	260,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	260,	"RAZ",	1,	1,	0,	0},
+	{"ALIGN"                       ,	0,	1,	261,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	261,	"RAZ",	1,	1,	0,	0},
+	{"SLOT"                        ,	0,	10,	262,	"R/W",	0,	0,	512ull,	512ull},
+	{"RESERVED_10_63"              ,	10,	54,	262,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	263,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	263,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	264,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	264,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	265,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	265,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	266,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	266,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	267,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	267,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	268,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	268,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	269,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	269,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	270,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	270,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	271,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	271,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	272,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	272,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	273,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	273,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	274,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	274,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	9,	275,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_9_63"               ,	9,	55,	275,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	4,	276,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	276,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	277,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	277,	"RAZ",	1,	1,	0,	0},
+	{"CORRUPT"                     ,	0,	4,	278,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_4_63"               ,	4,	60,	278,	"RAZ",	1,	1,	0,	0},
+	{"TX_XOF"                      ,	0,	16,	279,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	279,	"RAZ",	1,	1,	0,	0},
+	{"TX_XON"                      ,	0,	16,	280,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	280,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	281,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	281,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	281,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	282,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	282,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	282,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	282,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	282,	"R/W",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	282,	"R/W",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	282,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTP_LOST"                    ,	20,	4,	282,	"R/W",	0,	0,	0ull,	0ull},
+	{"XCHANGE"                     ,	24,	1,	282,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	282,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	283,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	283,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	283,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	283,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	283,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	283,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	283,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTP_LOST"                    ,	20,	4,	283,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XCHANGE"                     ,	24,	1,	283,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	283,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	284,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	284,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	285,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	285,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	4,	286,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	4,	286,	"R/W",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	4,	286,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	286,	"RAZ",	1,	1,	0,	0},
+	{"TX_PRT_BP"                   ,	32,	16,	286,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	286,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	287,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	287,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	288,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	288,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	5,	289,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	289,	"RAZ",	1,	1,	0,	0},
+	{"DIC_EN"                      ,	0,	1,	290,	"R/W",	0,	0,	0ull,	1ull},
+	{"UNI_EN"                      ,	1,	1,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	290,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	4,	2,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"LS_BYP"                      ,	6,	1,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	290,	"RAZ",	1,	1,	0,	0},
+	{"HG_EN"                       ,	8,	1,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_PAUSE_HGI"                ,	9,	2,	290,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_11_63"              ,	11,	53,	290,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	4,	291,	"R/W",	0,	0,	6ull,	6ull},
+	{"EN"                          ,	4,	1,	291,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	291,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_SEL"                     ,	12,	2,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_GEN"                     ,	14,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"SYNCE_SEL"                   ,	15,	2,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	292,	"RAZ",	1,	1,	0,	0},
+	{"N"                           ,	0,	32,	293,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	293,	"RAZ",	1,	1,	0,	0},
+	{"LANE_SEL"                    ,	0,	2,	294,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIV"                         ,	2,	1,	294,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	294,	"RAZ",	1,	1,	0,	0},
+	{"QLM_SEL"                     ,	8,	2,	294,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	294,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	295,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	295,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	296,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	296,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	20,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	297,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	20,	298,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	298,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	20,	299,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	299,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	300,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	300,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	300,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	300,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	300,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	300,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_SEL"                     ,	12,	2,	300,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_GEN"                     ,	14,	1,	300,	"R/W",	0,	0,	0ull,	0ull},
+	{"SYNCE_SEL"                   ,	15,	2,	300,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	300,	"RAZ",	1,	1,	0,	0},
+	{"ICD"                         ,	0,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"IBD"                         ,	1,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP1"                       ,	2,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP0"                       ,	3,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN1"                       ,	4,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN0"                       ,	5,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ1"                       ,	6,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ0"                       ,	7,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRT"                       ,	8,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR1"                        ,	9,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR0"                        ,	10,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR1"                       ,	11,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR0"                       ,	12,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR0"                       ,	13,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR1"                       ,	14,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR1"                        ,	15,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR0"                        ,	16,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRCB"                      ,	17,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"IOCFIF"                      ,	18,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"RSDFIF"                      ,	19,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"IORFIF"                      ,	20,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"XMCFIF"                      ,	21,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"XMDFIF"                      ,	22,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	301,	"RAZ",	1,	1,	0,	0},
+	{"FAU_END"                     ,	0,	1,	302,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB_ENB"                     ,	1,	1,	302,	"R/W",	0,	0,	1ull,	1ull},
+	{"PKO_ENB"                     ,	2,	1,	302,	"R/W",	0,	0,	0ull,	0ull},
+	{"INB_MAT"                     ,	3,	1,	302,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTB_MAT"                    ,	4,	1,	302,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RR_MODE"                     ,	5,	1,	302,	"R/W",	0,	0,	0ull,	0ull},
+	{"XMC_PER"                     ,	6,	4,	302,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIF_DLY"                     ,	10,	1,	302,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	302,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	303,	"RAZ",	1,	1,	0,	0},
+	{"TOUT_VAL"                    ,	0,	12,	304,	"R/W",	0,	0,	4ull,	4ull},
+	{"TOUT_ENB"                    ,	12,	1,	304,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	304,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	305,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	305,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	305,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	306,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	306,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	306,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	306,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	306,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	307,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	307,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	307,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	307,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	307,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	308,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	309,	"R/W",	0,	1,	0ull,	0},
+	{"NP_SOP"                      ,	0,	1,	310,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	310,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	310,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	310,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	310,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	310,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	310,	"RAZ",	1,	1,	0,	0},
+	{"NP_SOP"                      ,	0,	1,	311,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	311,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	311,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	311,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	311,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	311,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	311,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	312,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	312,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	312,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	313,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	313,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	313,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	314,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	315,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	315,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	315,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	315,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	315,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	316,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	316,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	316,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	316,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	316,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	317,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	318,	"R/W",	0,	1,	0ull,	0},
+	{"CNT_VAL"                     ,	0,	15,	319,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	319,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	319,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	320,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	320,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	320,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	321,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	6,	322,	"RO",	0,	1,	0ull,	0},
+	{"VPORT"                       ,	6,	6,	322,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	322,	"RAZ",	1,	1,	0,	0},
+	{"NCB_WR"                      ,	0,	3,	323,	"R/W",	0,	1,	0ull,	0},
+	{"NCB_RD"                      ,	3,	3,	323,	"R/W",	0,	1,	0ull,	0},
+	{"PKO_RD"                      ,	6,	3,	323,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	323,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	324,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	324,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	325,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	325,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	326,	"RAZ",	1,	1,	0,	0},
+	{"PWP"                         ,	0,	1,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_NEW"                     ,	1,	1,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_OLD"                     ,	2,	1,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"PRC_OFF"                     ,	3,	1,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ0"                        ,	4,	1,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ1"                        ,	5,	1,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM_WORD"                    ,	6,	1,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM0"                        ,	7,	1,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM1"                        ,	8,	1,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM2"                        ,	9,	1,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM3"                        ,	10,	1,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE0"                    ,	11,	1,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE1"                    ,	12,	1,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_POW"                     ,	13,	1,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WP1"                     ,	14,	1,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WQED"                    ,	15,	1,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_NCMD"                    ,	16,	1,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_MEM"                     ,	17,	1,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	327,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	48,	328,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	328,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	64,	329,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_EN"                      ,	0,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC_MODE"                    ,	1,	2,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBP_EN"                      ,	3,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"WQE_LEND"                    ,	4,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_LEND"                    ,	5,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"NADDBUF"                     ,	6,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDPKT"                      ,	7,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	8,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_M8"                      ,	9,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKT_OFF"                     ,	10,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_FULL"                    ,	11,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_NABUF"                    ,	12,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_APKT"                     ,	13,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"NO_WPTR"                     ,	14,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKEN"                       ,	15,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"RST_DONE"                    ,	16,	1,	330,	"RO",	0,	0,	1ull,	0ull},
+	{"USE_SOP"                     ,	17,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	330,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	331,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	332,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	333,	"RAZ",	1,	1,	0,	0},
+	{"MB_SIZE"                     ,	0,	12,	334,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_12_63"              ,	12,	52,	334,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	335,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	335,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	336,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	336,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	336,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	337,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	337,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	337,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	338,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	338,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	338,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	339,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	339,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	340,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	340,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	341,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	341,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	342,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	342,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	343,	"RO",	0,	1,	0ull,	0},
+	{"WMARK"                       ,	32,	32,	343,	"R/W",	0,	1,	4294967295ull,	0},
+	{"INTR"                        ,	0,	64,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	64,	345,	"R/W",	0,	0,	0ull,	1ull},
+	{"RADDR"                       ,	0,	3,	346,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	3,	1,	346,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	4,	29,	346,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	33,	3,	346,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	36,	3,	346,	"RO",	0,	0,	5ull,	5ull},
+	{"RESERVED_39_63"              ,	39,	25,	346,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	7,	347,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	7,	1,	347,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	8,	29,	347,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	37,	7,	347,	"RO",	0,	0,	64ull,	64ull},
+	{"RESERVED_44_63"              ,	44,	20,	347,	"RAZ",	1,	1,	0,	0},
+	{"WQE_PCNT"                    ,	0,	7,	348,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PCNT"                    ,	7,	7,	348,	"RO",	0,	0,	0ull,	0ull},
+	{"PFIF_CNT"                    ,	14,	3,	348,	"RO",	0,	0,	0ull,	0ull},
+	{"WQEV_CNT"                    ,	17,	1,	348,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTV_CNT"                    ,	18,	1,	348,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	348,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	8,	349,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	8,	1,	349,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	9,	29,	349,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	38,	8,	349,	"RO",	1,	1,	0,	0},
+	{"WRADDR"                      ,	46,	8,	349,	"RO",	1,	1,	0,	0},
+	{"MAX_CNTS"                    ,	54,	7,	349,	"RO",	0,	0,	64ull,	64ull},
+	{"RESERVED_61_63"              ,	61,	3,	349,	"RAZ",	1,	1,	0,	0},
+	{"PASS"                        ,	0,	32,	350,	"R/W",	0,	1,	0ull,	0},
+	{"DROP"                        ,	32,	32,	350,	"R/W",	0,	1,	0ull,	0},
+	{"Q0_PCNT"                     ,	0,	32,	351,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	351,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	352,	"R/W",	0,	0,	0ull,	0ull},
+	{"AVG_DLY"                     ,	36,	14,	352,	"R/W",	0,	1,	0ull,	0},
+	{"PRB_DLY"                     ,	50,	14,	352,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRT_ENB"                     ,	0,	12,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	353,	"RAZ",	1,	1,	0,	0},
+	{"PRB_CON"                     ,	0,	32,	354,	"R/W",	0,	1,	0ull,	0},
+	{"AVG_CON"                     ,	32,	8,	354,	"R/W",	0,	1,	0ull,	0},
+	{"NEW_CON"                     ,	40,	8,	354,	"R/W",	0,	1,	0ull,	0},
+	{"USE_PCNT"                    ,	48,	1,	354,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	354,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	25,	355,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	25,	6,	355,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	355,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT"                    ,	0,	32,	356,	"R/W",	0,	0,	4294967295ull,	4294967295ull},
+	{"RESERVED_32_35"              ,	32,	4,	356,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT2"                   ,	36,	4,	356,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_40_63"              ,	40,	24,	356,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	357,	"R/W",	1,	0,	0,	0ull},
+	{"PORT_QOS"                    ,	32,	9,	357,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_41_63"              ,	41,	23,	357,	"RAZ",	1,	1,	0,	0},
+	{"WQE_POOL"                    ,	0,	3,	358,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	358,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	359,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	359,	"RAZ",	1,	1,	0,	0},
+	{"MEM0"                        ,	0,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM1"                        ,	1,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	2,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	360,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	361,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	361,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	361,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	362,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	362,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	362,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	362,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	362,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	363,	"RAZ",	1,	1,	0,	0},
+	{"DISABLE"                     ,	0,	1,	364,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	364,	"RAZ",	1,	1,	0,	0},
+	{"MAXDRAM"                     ,	4,	4,	364,	"R/W",	0,	0,	7ull,	7ull},
+	{"RESERVED_8_63"               ,	8,	56,	364,	"RAZ",	1,	1,	0,	0},
+	{"TDFFL"                       ,	0,	1,	365,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	365,	"RAZ",	1,	1,	0,	0},
+	{"VRTFL"                       ,	4,	1,	365,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	365,	"RAZ",	1,	1,	0,	0},
+	{"DUTRESFL"                    ,	8,	1,	365,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	365,	"RAZ",	1,	1,	0,	0},
+	{"IOCDATFL"                    ,	12,	1,	365,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	365,	"RAZ",	1,	1,	0,	0},
+	{"IOCCMDFL"                    ,	16,	1,	365,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	365,	"RAZ",	1,	1,	0,	0},
+	{"DUTFL"                       ,	32,	4,	365,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	365,	"RAZ",	1,	1,	0,	0},
+	{"VBFFL"                       ,	0,	4,	366,	"RO",	1,	0,	0,	0ull},
+	{"RDFFL"                       ,	4,	1,	366,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_5_61"               ,	5,	57,	366,	"RAZ",	1,	1,	0,	0},
+	{"CLEAR_BIST"                  ,	62,	1,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"START_BIST"                  ,	63,	1,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFL"                       ,	0,	8,	367,	"RO",	1,	0,	0,	0ull},
+	{"FBFFL"                       ,	8,	8,	367,	"RO",	1,	0,	0,	0ull},
+	{"SBFFL"                       ,	16,	8,	367,	"RO",	1,	0,	0,	0ull},
+	{"FBFRSPFL"                    ,	24,	8,	367,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	367,	"RAZ",	1,	1,	0,	0},
+	{"TAGFL"                       ,	0,	16,	368,	"RO",	1,	0,	0,	0ull},
+	{"LRUFL"                       ,	16,	1,	368,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	368,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	369,	"R/W",	1,	1,	0,	0},
+	{"DISIDXALIAS"                 ,	0,	1,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISECC"                      ,	1,	1,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"VAB_THRESH"                  ,	2,	4,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"EF_CNT"                      ,	6,	7,	370,	"R/W",	0,	0,	0ull,	4ull},
+	{"EF_ENA"                      ,	13,	1,	370,	"R/W",	0,	0,	0ull,	1ull},
+	{"XMC_ARB_MODE"                ,	14,	1,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSP_ARB_MODE"                ,	15,	1,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXLFB"                      ,	16,	4,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXVAB"                      ,	20,	4,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISCCLK"                     ,	24,	1,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFDBE"                     ,	25,	1,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFSBE"                     ,	26,	1,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISSTGL2I"                   ,	27,	1,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDF_FAST"                    ,	28,	1,	370,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_29_63"              ,	29,	35,	370,	"RAZ",	1,	1,	0,	0},
+	{"VALID"                       ,	0,	1,	371,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_9"                ,	1,	9,	371,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	10,	28,	371,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	371,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	2,	372,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	372,	"RAZ",	1,	1,	0,	0},
+	{"WAYIDX"                      ,	4,	16,	372,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_20_49"              ,	20,	30,	372,	"RAZ",	1,	1,	0,	0},
+	{"SYN"                         ,	50,	10,	372,	"RO",	0,	0,	0ull,	0ull},
+	{"VSBE"                        ,	60,	1,	372,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VDBE"                        ,	61,	1,	372,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE"                         ,	62,	1,	372,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	63,	1,	372,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TYPE"                        ,	0,	2,	373,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_6"                ,	2,	5,	373,	"RAZ",	1,	1,	0,	0},
+	{"WAYIDX"                      ,	7,	13,	373,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_20_49"              ,	20,	30,	373,	"RAZ",	1,	1,	0,	0},
+	{"SYN"                         ,	50,	6,	373,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_60"              ,	56,	5,	373,	"RAZ",	1,	1,	0,	0},
+	{"NOWAY"                       ,	61,	1,	373,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE"                         ,	62,	1,	373,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	63,	1,	373,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TYPE"                        ,	0,	2,	374,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_49"               ,	2,	48,	374,	"RAZ",	1,	1,	0,	0},
+	{"VSYN"                        ,	50,	10,	374,	"RO",	0,	0,	0ull,	0ull},
+	{"VSBE"                        ,	60,	1,	374,	"RO",	0,	0,	0ull,	0ull},
+	{"VDBE"                        ,	61,	1,	374,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	374,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	38,	375,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_47"              ,	38,	10,	375,	"RAZ",	1,	1,	0,	0},
+	{"SID"                         ,	48,	4,	375,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_57"              ,	52,	6,	375,	"RAZ",	1,	1,	0,	0},
+	{"CMD"                         ,	58,	6,	375,	"RO",	0,	1,	0ull,	0},
+	{"HOLERD"                      ,	0,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"HOLEWR"                      ,	1,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTWR"                       ,	2,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTIDRNG"                    ,	3,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTADRNG"                    ,	4,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTPE"                       ,	5,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"BIGWR"                       ,	6,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"BIGRD"                       ,	7,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_8_63"               ,	8,	56,	376,	"RAZ",	1,	1,	0,	0},
+	{"HOLERD"                      ,	0,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HOLEWR"                      ,	1,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTWR"                       ,	2,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTIDRNG"                    ,	3,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTADRNG"                    ,	4,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTPE"                       ,	5,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BIGWR"                       ,	6,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BIGRD"                       ,	7,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	377,	"RAZ",	1,	1,	0,	0},
+	{"TAD0"                        ,	16,	1,	377,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	377,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	378,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	379,	"R/W",	0,	1,	0ull,	0},
+	{"LVL"                         ,	0,	2,	380,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	380,	"RAZ",	1,	1,	0,	0},
+	{"DWBLVL"                      ,	4,	2,	380,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	380,	"RAZ",	1,	1,	0,	0},
+	{"LVL"                         ,	0,	2,	381,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	381,	"RAZ",	1,	1,	0,	0},
+	{"WGT0"                        ,	0,	8,	382,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT1"                        ,	8,	8,	382,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT2"                        ,	16,	8,	382,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT3"                        ,	24,	8,	382,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_32_63"              ,	32,	32,	382,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	383,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	384,	"R/W",	0,	1,	0ull,	0},
+	{"OW0ECC"                      ,	0,	10,	385,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	385,	"RAZ",	1,	1,	0,	0},
+	{"OW1ECC"                      ,	16,	10,	385,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_31"              ,	26,	6,	385,	"RAZ",	1,	1,	0,	0},
+	{"OW2ECC"                      ,	32,	10,	385,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	385,	"RAZ",	1,	1,	0,	0},
+	{"OW3ECC"                      ,	48,	10,	385,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	385,	"RAZ",	1,	1,	0,	0},
+	{"OW4ECC"                      ,	0,	10,	386,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	386,	"RAZ",	1,	1,	0,	0},
+	{"OW5ECC"                      ,	16,	10,	386,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_31"              ,	26,	6,	386,	"RAZ",	1,	1,	0,	0},
+	{"OW6ECC"                      ,	32,	10,	386,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	386,	"RAZ",	1,	1,	0,	0},
+	{"OW7ECC"                      ,	48,	10,	386,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	386,	"RAZ",	1,	1,	0,	0},
+	{"L2DSBE"                      ,	0,	1,	387,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2DDBE"                      ,	1,	1,	387,	"R/W",	0,	0,	0ull,	1ull},
+	{"TAGSBE"                      ,	2,	1,	387,	"R/W",	0,	0,	0ull,	1ull},
+	{"TAGDBE"                      ,	3,	1,	387,	"R/W",	0,	0,	0ull,	1ull},
+	{"VBFSBE"                      ,	4,	1,	387,	"R/W",	0,	0,	0ull,	1ull},
+	{"VBFDBE"                      ,	5,	1,	387,	"R/W",	0,	0,	0ull,	1ull},
+	{"NOWAY"                       ,	6,	1,	387,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDDISLMC"                    ,	7,	1,	387,	"R/W",	0,	0,	0ull,	1ull},
+	{"WRDISLMC"                    ,	8,	1,	387,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	387,	"RAZ",	1,	1,	0,	0},
+	{"L2DSBE"                      ,	0,	1,	388,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"L2DDBE"                      ,	1,	1,	388,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"TAGSBE"                      ,	2,	1,	388,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"TAGDBE"                      ,	3,	1,	388,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"VBFSBE"                      ,	4,	1,	388,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"VBFDBE"                      ,	5,	1,	388,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"NOWAY"                       ,	6,	1,	388,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDDISLMC"                    ,	7,	1,	388,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WRDISLMC"                    ,	8,	1,	388,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	388,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	389,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	390,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	391,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	392,	"R/W",	0,	1,	0ull,	0},
+	{"CNT0SEL"                     ,	0,	8,	393,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT1SEL"                     ,	8,	8,	393,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT2SEL"                     ,	16,	8,	393,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT3SEL"                     ,	24,	8,	393,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	393,	"RAZ",	1,	1,	0,	0},
+	{"LOCK"                        ,	0,	1,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIRTY"                       ,	1,	1,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"VALID"                       ,	2,	1,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE"                         ,	3,	1,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_16"               ,	4,	13,	394,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	17,	19,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_39"              ,	36,	4,	394,	"RAZ",	1,	1,	0,	0},
+	{"ECC"                         ,	40,	6,	394,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_46_63"              ,	46,	18,	394,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	395,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MASK"                        ,	0,	1,	396,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	396,	"RAZ",	1,	1,	0,	0},
+	{"DWB"                         ,	0,	1,	397,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	1,	1,	397,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	397,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	4,	398,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	398,	"RAZ",	1,	1,	0,	0},
+	{"ID"                          ,	0,	6,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	399,	"RAZ",	1,	1,	0,	0},
+	{"DWBID"                       ,	8,	6,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	399,	"RAZ",	1,	1,	0,	0},
+	{"ID"                          ,	0,	6,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	400,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	1,	401,	"R/W",	0,	0,	0ull,	1ull},
+	{"NUMID"                       ,	1,	3,	401,	"R/W",	0,	0,	5ull,	5ull},
+	{"MEMSZ"                       ,	4,	3,	401,	"R/W",	0,	0,	5ull,	5ull},
+	{"RESERVED_7_7"                ,	7,	1,	401,	"RAZ",	1,	1,	0,	0},
+	{"OOBERR"                      ,	8,	1,	401,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	401,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	32,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"PARITY"                      ,	32,	4,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	402,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	403,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	403,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	404,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	404,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	405,	"R/W",	0,	1,	0ull,	0},
+	{"ADDR"                        ,	0,	38,	406,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_38_56"              ,	38,	19,	406,	"RAZ",	1,	1,	0,	0},
+	{"CMD"                         ,	57,	6,	406,	"R/W",	1,	1,	0,	0},
+	{"INUSE"                       ,	63,	1,	406,	"RO",	0,	0,	0ull,	0ull},
+	{"COUNT"                       ,	0,	64,	407,	"R/W",	0,	1,	0ull,	0},
+	{"PRBS"                        ,	0,	32,	408,	"R/W",	1,	1,	0,	0},
+	{"PROG"                        ,	32,	8,	408,	"R/W",	1,	1,	0,	0},
+	{"SEL"                         ,	40,	1,	408,	"R/W",	1,	1,	0,	0},
+	{"EN"                          ,	41,	1,	408,	"R/W",	1,	1,	0,	0},
+	{"SKEW_ON"                     ,	42,	1,	408,	"R/W",	1,	1,	0,	0},
+	{"DR"                          ,	43,	1,	408,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_44_63"              ,	44,	20,	408,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	409,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	8,	410,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	410,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	411,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	8,	412,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	412,	"R/W",	1,	1,	0,	0},
+	{"CKE_MASK"                    ,	0,	2,	413,	"R/W",	1,	1,	0,	0},
+	{"CS0_N_MASK"                  ,	2,	2,	413,	"R/W",	1,	1,	0,	0},
+	{"CS1_N_MASK"                  ,	4,	2,	413,	"R/W",	1,	1,	0,	0},
+	{"ODT0_MASK"                   ,	6,	2,	413,	"R/W",	1,	1,	0,	0},
+	{"ODT1_MASK"                   ,	8,	2,	413,	"R/W",	1,	1,	0,	0},
+	{"RAS_N_MASK"                  ,	10,	1,	413,	"R/W",	1,	1,	0,	0},
+	{"CAS_N_MASK"                  ,	11,	1,	413,	"R/W",	1,	1,	0,	0},
+	{"WE_N_MASK"                   ,	12,	1,	413,	"R/W",	1,	1,	0,	0},
+	{"BA_MASK"                     ,	13,	3,	413,	"R/W",	1,	1,	0,	0},
+	{"A_MASK"                      ,	16,	16,	413,	"R/W",	1,	1,	0,	0},
+	{"RESET_N_MASK"                ,	32,	1,	413,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_33_63"              ,	33,	31,	413,	"R/W",	1,	1,	0,	0},
+	{"DQX_CTL"                     ,	0,	4,	414,	"R/W",	0,	1,	4ull,	0},
+	{"CK_CTL"                      ,	4,	4,	414,	"R/W",	0,	1,	4ull,	0},
+	{"CMD_CTL"                     ,	8,	4,	414,	"R/W",	0,	1,	4ull,	0},
+	{"RODT_CTL"                    ,	12,	4,	414,	"R/W",	0,	1,	0ull,	0},
+	{"NTUNE"                       ,	16,	4,	414,	"R/W",	0,	1,	0ull,	0},
+	{"PTUNE"                       ,	20,	4,	414,	"R/W",	0,	1,	0ull,	0},
+	{"BYP"                         ,	24,	1,	414,	"R/W",	0,	1,	0ull,	0},
+	{"M180"                        ,	25,	1,	414,	"R/W",	0,	1,	0ull,	0},
+	{"DDR__NTUNE"                  ,	26,	4,	414,	"RO",	1,	1,	0,	0},
+	{"DDR__PTUNE"                  ,	30,	4,	414,	"RO",	1,	1,	0,	0},
+	{"RESERVED_34_63"              ,	34,	30,	414,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	415,	"WR0",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	415,	"R/W",	0,	0,	0ull,	1ull},
+	{"ROW_LSB"                     ,	2,	3,	415,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	415,	"R/W",	0,	1,	5ull,	0},
+	{"IDLEPOWER"                   ,	9,	3,	415,	"R/W",	0,	0,	0ull,	6ull},
+	{"FORCEWRITE"                  ,	12,	4,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ADR"                     ,	16,	1,	415,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESET"                       ,	17,	1,	415,	"R/W",	0,	1,	0ull,	0},
+	{"REF_ZQCS_INT"                ,	18,	19,	415,	"R/W",	1,	1,	0,	0},
+	{"SEQUENCE"                    ,	37,	3,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"EARLY_DQX"                   ,	40,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"SREF_WITH_DLL"               ,	41,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"RANK_ENA"                    ,	42,	1,	415,	"R/W",	0,	1,	0ull,	0},
+	{"RANKMASK"                    ,	43,	4,	415,	"R/W",	0,	1,	0ull,	0},
+	{"MIRRMASK"                    ,	47,	4,	415,	"R/W",	0,	1,	0ull,	0},
+	{"INIT_STATUS"                 ,	51,	4,	415,	"R/W1",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D0_R0"          ,	55,	1,	415,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D0_R1"          ,	56,	1,	415,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D1_R0"          ,	57,	1,	415,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D1_R1"          ,	58,	1,	415,	"R/W",	0,	1,	0ull,	0},
+	{"SCRZ"                        ,	59,	1,	415,	"R/W1",	0,	1,	0ull,	0},
+	{"MODE32B"                     ,	60,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	415,	"RAZ",	1,	1,	0,	0},
+	{"RDIMM_ENA"                   ,	0,	1,	416,	"R/W",	0,	1,	0ull,	0},
+	{"BWCNT"                       ,	1,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	2,	1,	416,	"R/W",	0,	0,	0ull,	1ull},
+	{"POCAS"                       ,	3,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPRCH2"                      ,	4,	2,	416,	"R/W",	0,	0,	0ull,	1ull},
+	{"THROTTLE_RD"                 ,	6,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"THROTTLE_WR"                 ,	7,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_RD"                  ,	8,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_WR"                  ,	9,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"ELEV_PRIO_DIS"               ,	10,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"NXM_WRITE_EN"                ,	11,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	12,	4,	416,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	16,	1,	416,	"R/W",	0,	0,	0ull,	1ull},
+	{"AUTO_DCLKDIS"                ,	17,	1,	416,	"R/W",	0,	0,	0ull,	1ull},
+	{"INT_ZQCS_DIS"                ,	18,	1,	416,	"R/W",	0,	0,	1ull,	0ull},
+	{"EXT_ZQCS_DIS"                ,	19,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"BPRCH"                       ,	20,	2,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"WODT_BPRCH"                  ,	22,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_BPRCH"                  ,	23,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRM_MAX"                     ,	24,	5,	416,	"R/W",	0,	0,	31ull,	31ull},
+	{"CRM_THR"                     ,	29,	5,	416,	"R/W",	0,	0,	0ull,	8ull},
+	{"CRM_CNT"                     ,	34,	5,	416,	"RO",	0,	0,	0ull,	0ull},
+	{"THRMAX"                      ,	39,	4,	416,	"R/W",	0,	0,	15ull,	2ull},
+	{"PERSUB"                      ,	43,	8,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"THRCNT"                      ,	51,	12,	416,	"RO",	0,	0,	0ull,	0ull},
+	{"SCRAMBLE_ENA"                ,	63,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCLKCNT"                     ,	0,	64,	417,	"RO",	0,	1,	0ull,	0},
+	{"CLKF"                        ,	0,	7,	418,	"R/W",	0,	1,	48ull,	0},
+	{"RESET_N"                     ,	7,	1,	418,	"R/W",	0,	0,	0ull,	1ull},
+	{"CPB"                         ,	8,	3,	418,	"R/W",	0,	0,	0ull,	1ull},
+	{"CPS"                         ,	11,	3,	418,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIFFAMP"                     ,	14,	4,	418,	"R/W",	0,	0,	0ull,	1ull},
+	{"DDR_PS_EN"                   ,	18,	3,	418,	"R/W",	0,	1,	2ull,	0},
+	{"DDR_DIV_RESET"               ,	21,	1,	418,	"R/W",	0,	0,	1ull,	0ull},
+	{"DFM_PS_EN"                   ,	22,	3,	418,	"R/W",	0,	1,	2ull,	0},
+	{"DFM_DIV_RESET"               ,	25,	1,	418,	"R/W",	0,	0,	1ull,	0ull},
+	{"JTG_TEST_MODE"               ,	26,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	418,	"RAZ",	1,	1,	0,	0},
+	{"RC0"                         ,	0,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC1"                         ,	4,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC2"                         ,	8,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC3"                         ,	12,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC4"                         ,	16,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC5"                         ,	20,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC6"                         ,	24,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC7"                         ,	28,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC8"                         ,	32,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC9"                         ,	36,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC10"                        ,	40,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC11"                        ,	44,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC12"                        ,	48,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC13"                        ,	52,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC14"                        ,	56,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC15"                        ,	60,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIMM0_WMASK"                 ,	0,	16,	420,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"DIMM1_WMASK"                 ,	16,	16,	420,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"TCWS"                        ,	32,	13,	420,	"R/W",	0,	0,	1248ull,	1248ull},
+	{"PARITY"                      ,	45,	1,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	420,	"RAZ",	1,	1,	0,	0},
+	{"BYP_SETTING"                 ,	0,	8,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYP_SEL"                     ,	8,	4,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"QUAD_DLL_ENA"                ,	12,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	13,	1,	421,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLL_BRINGUP"                 ,	14,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTF_EN"                     ,	15,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	421,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	6,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYTE_SEL"                    ,	6,	4,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE_SEL"                    ,	10,	2,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOAD_OFFSET"                 ,	12,	1,	422,	"WR0",	0,	0,	0ull,	0ull},
+	{"OFFSET_ENA"                  ,	13,	1,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYTE_SEL"              ,	14,	4,	422,	"R/W",	0,	0,	1ull,	1ull},
+	{"DLL_MODE"                    ,	18,	1,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINE_TUNE_MODE"              ,	19,	1,	422,	"R/W",	0,	0,	0ull,	1ull},
+	{"DLL90_SETTING"               ,	20,	8,	422,	"RO",	1,	1,	0,	0},
+	{"DLL_FAST"                    ,	28,	1,	422,	"RO",	1,	1,	0,	0},
+	{"DCLK90_BYP_SETTING"          ,	29,	8,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCLK90_BYP_SEL"              ,	37,	1,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCLK90_RECAL_DIS"            ,	38,	1,	422,	"R/W",	0,	0,	0ull,	1ull},
+	{"DDR_90_DLY_BYP"              ,	39,	1,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCLK90_FWD"                  ,	40,	1,	422,	"WR0",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_63"              ,	41,	23,	422,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	423,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	423,	"RAZ",	1,	1,	0,	0},
+	{"ROW_LSB"                     ,	16,	3,	423,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_19_63"              ,	19,	45,	423,	"RAZ",	1,	1,	0,	0},
+	{"MRDSYN0"                     ,	0,	8,	424,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN1"                     ,	8,	8,	424,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN2"                     ,	16,	8,	424,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN3"                     ,	24,	8,	424,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	424,	"RAZ",	1,	1,	0,	0},
+	{"FCOL"                        ,	0,	14,	425,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	14,	16,	425,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	30,	3,	425,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	33,	1,	425,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	34,	2,	425,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	425,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT"                      ,	0,	64,	426,	"RO",	0,	1,	1ull,	0},
+	{"NXM_WR_ERR"                  ,	0,	1,	427,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SEC_ERR"                     ,	1,	4,	427,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	5,	4,	427,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	427,	"RAZ",	1,	1,	0,	0},
+	{"INTR_NXM_WR_ENA"             ,	0,	1,	428,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_SEC_ENA"                ,	1,	1,	428,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_DED_ENA"                ,	2,	1,	428,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	428,	"RAZ",	1,	1,	0,	0},
+	{"CWL"                         ,	0,	3,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPRLOC"                      ,	3,	2,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPR"                         ,	5,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL"                         ,	6,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"AL"                          ,	7,	2,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"WLEV"                        ,	9,	1,	429,	"RO",	0,	0,	0ull,	0ull},
+	{"TDQS"                        ,	10,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOFF"                        ,	11,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"BL"                          ,	12,	2,	429,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	14,	4,	429,	"R/W",	0,	0,	2ull,	2ull},
+	{"RBT"                         ,	18,	1,	429,	"RO",	0,	0,	1ull,	1ull},
+	{"TM"                          ,	19,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLR"                        ,	20,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRP"                         ,	21,	3,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPD"                         ,	24,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	429,	"RAZ",	1,	1,	0,	0},
+	{"PASR_00"                     ,	0,	3,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_00"                      ,	3,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_00"                      ,	4,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_00"                   ,	5,	2,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_00"                      ,	7,	2,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_00"                  ,	9,	3,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_01"                     ,	12,	3,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_01"                      ,	15,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_01"                      ,	16,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_01"                   ,	17,	2,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_01"                      ,	19,	2,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_01"                  ,	21,	3,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_10"                     ,	24,	3,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_10"                      ,	27,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_10"                      ,	28,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_10"                   ,	29,	2,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_10"                      ,	31,	2,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_10"                  ,	33,	3,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_11"                     ,	36,	3,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_11"                      ,	39,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_11"                      ,	40,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_11"                   ,	41,	2,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_11"                      ,	43,	2,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_11"                  ,	45,	3,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	430,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	431,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D0_R0"               ,	8,	4,	431,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D0_R1"               ,	12,	4,	431,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D1_R0"               ,	16,	4,	431,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D1_R1"               ,	20,	4,	431,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D2_R0"               ,	24,	4,	431,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D2_R1"               ,	28,	4,	431,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D3_R0"               ,	32,	4,	431,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D3_R1"               ,	36,	4,	431,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	431,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT"                      ,	0,	64,	432,	"RO",	0,	1,	1ull,	0},
+	{"TS_STAGGER"                  ,	0,	1,	433,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK_POS"                ,	1,	1,	433,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK"                    ,	2,	1,	433,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT0"                  ,	3,	4,	433,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE0"                    ,	7,	1,	433,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT1"                  ,	8,	4,	433,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE1"                    ,	12,	1,	433,	"R/W",	0,	1,	0ull,	0},
+	{"LV_MODE"                     ,	13,	1,	433,	"R/W",	0,	1,	0ull,	0},
+	{"RX_ALWAYS_ON"                ,	14,	1,	433,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	433,	"RAZ",	1,	1,	0,	0},
+	{"DDR3RST"                     ,	0,	1,	434,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PWARM"                   ,	1,	1,	434,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSOFT"                   ,	2,	1,	434,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSV"                     ,	3,	1,	434,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	434,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	435,	"R/W",	0,	1,	0ull,	0},
+	{"OFFSET"                      ,	4,	4,	435,	"R/W",	0,	0,	2ull,	2ull},
+	{"OFFSET_EN"                   ,	8,	1,	435,	"R/W",	0,	0,	1ull,	1ull},
+	{"OR_DIS"                      ,	9,	1,	435,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	10,	8,	435,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_0"              ,	18,	1,	435,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_1"              ,	19,	1,	435,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_2"              ,	20,	1,	435,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_3"              ,	21,	1,	435,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	435,	"RAZ",	1,	1,	0,	0},
+	{"BITMASK"                     ,	0,	64,	436,	"RO",	0,	0,	0ull,	0ull},
+	{"BYTE0"                       ,	0,	6,	437,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	6,	6,	437,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE2"                       ,	12,	6,	437,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE3"                       ,	18,	6,	437,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE4"                       ,	24,	6,	437,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE5"                       ,	30,	6,	437,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE6"                       ,	36,	6,	437,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE7"                       ,	42,	6,	437,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE8"                       ,	48,	6,	437,	"R/W",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	54,	2,	437,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	437,	"RAZ",	1,	1,	0,	0},
+	{"RODT_D0_R0"                  ,	0,	8,	438,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D0_R1"                  ,	8,	8,	438,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D1_R0"                  ,	16,	8,	438,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D1_R1"                  ,	24,	8,	438,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D2_R0"                  ,	32,	8,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D2_R1"                  ,	40,	8,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R0"                  ,	48,	8,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R1"                  ,	56,	8,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	0,	64,	439,	"R/W",	0,	1,	0ull,	0},
+	{"KEY"                         ,	0,	64,	440,	"R/W",	0,	1,	0ull,	0},
+	{"FCOL"                        ,	0,	14,	441,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	14,	16,	441,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	30,	3,	441,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	33,	1,	441,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	34,	2,	441,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	441,	"RAZ",	1,	1,	0,	0},
+	{"R2R_INIT"                    ,	0,	6,	442,	"R/W",	0,	1,	1ull,	0},
+	{"R2W_INIT"                    ,	6,	6,	442,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_INIT"                    ,	12,	6,	442,	"R/W",	0,	1,	9ull,	0},
+	{"W2W_INIT"                    ,	18,	6,	442,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	442,	"RAZ",	1,	1,	0,	0},
+	{"R2R_XRANK_INIT"              ,	0,	6,	443,	"R/W",	0,	1,	3ull,	0},
+	{"R2W_XRANK_INIT"              ,	6,	6,	443,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_XRANK_INIT"              ,	12,	6,	443,	"R/W",	0,	1,	4ull,	0},
+	{"W2W_XRANK_INIT"              ,	18,	6,	443,	"R/W",	0,	1,	5ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	443,	"RAZ",	1,	1,	0,	0},
+	{"R2R_XDIMM_INIT"              ,	0,	6,	444,	"R/W",	0,	1,	4ull,	0},
+	{"R2W_XDIMM_INIT"              ,	6,	6,	444,	"R/W",	0,	1,	7ull,	0},
+	{"W2R_XDIMM_INIT"              ,	12,	6,	444,	"R/W",	0,	1,	4ull,	0},
+	{"W2W_XDIMM_INIT"              ,	18,	6,	444,	"R/W",	0,	1,	6ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	444,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_9"                ,	0,	10,	445,	"RAZ",	1,	1,	0,	0},
+	{"TZQCS"                       ,	10,	4,	445,	"R/W",	0,	0,	4ull,	4ull},
+	{"TCKE"                        ,	14,	4,	445,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPR"                        ,	18,	4,	445,	"R/W",	0,	0,	5ull,	5ull},
+	{"TMRD"                        ,	22,	4,	445,	"R/W",	0,	0,	4ull,	4ull},
+	{"TMOD"                        ,	26,	4,	445,	"R/W",	0,	0,	12ull,	12ull},
+	{"TDLLK"                       ,	30,	4,	445,	"R/W",	0,	0,	2ull,	2ull},
+	{"TZQINIT"                     ,	34,	4,	445,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	38,	4,	445,	"R/W",	0,	0,	6ull,	6ull},
+	{"TCKSRE"                      ,	42,	4,	445,	"R/W",	0,	0,	5ull,	5ull},
+	{"TRP_EXT"                     ,	46,	1,	445,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	445,	"RAZ",	1,	1,	0,	0},
+	{"TMPRR"                       ,	0,	4,	446,	"R/W",	0,	0,	1ull,	1ull},
+	{"TRAS"                        ,	4,	5,	446,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	9,	4,	446,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	13,	4,	446,	"R/W",	0,	0,	2ull,	3ull},
+	{"TRFC"                        ,	17,	5,	446,	"R/W",	0,	0,	6ull,	7ull},
+	{"TRRD"                        ,	22,	3,	446,	"R/W",	0,	0,	2ull,	2ull},
+	{"TXP"                         ,	25,	3,	446,	"R/W",	0,	0,	3ull,	3ull},
+	{"TWLMRD"                      ,	28,	4,	446,	"R/W",	0,	0,	10ull,	10ull},
+	{"TWLDQSEN"                    ,	32,	4,	446,	"R/W",	0,	0,	7ull,	7ull},
+	{"TFAW"                        ,	36,	5,	446,	"R/W",	0,	0,	0ull,	9ull},
+	{"TXPDLL"                      ,	41,	5,	446,	"R/W",	0,	0,	0ull,	10ull},
+	{"TRAS_EXT"                    ,	46,	1,	446,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	446,	"RAZ",	1,	1,	0,	0},
+	{"TRESET"                      ,	0,	1,	447,	"R/W",	0,	1,	1ull,	0},
+	{"RCLK_CNT"                    ,	1,	32,	447,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	447,	"RAZ",	1,	1,	0,	0},
+	{"RING_CNT"                    ,	0,	32,	448,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	448,	"RAZ",	1,	1,	0,	0},
+	{"LANEMASK"                    ,	0,	9,	449,	"R/W",	0,	1,	0ull,	0},
+	{"SSET"                        ,	9,	1,	449,	"R/W",	0,	1,	0ull,	0},
+	{"OR_DIS"                      ,	10,	1,	449,	"R/W",	0,	1,	0ull,	0},
+	{"BITMASK"                     ,	11,	8,	449,	"R/W",	0,	1,	0ull,	0},
+	{"RTT_NOM"                     ,	19,	3,	449,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	449,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	450,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	4,	8,	450,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	450,	"RAZ",	1,	1,	0,	0},
+	{"BYTE0"                       ,	0,	5,	451,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	5,	5,	451,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE2"                       ,	10,	5,	451,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE3"                       ,	15,	5,	451,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE4"                       ,	20,	5,	451,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE5"                       ,	25,	5,	451,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE6"                       ,	30,	5,	451,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE7"                       ,	35,	5,	451,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE8"                       ,	40,	5,	451,	"R/W",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	45,	2,	451,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_47_63"              ,	47,	17,	451,	"RAZ",	1,	1,	0,	0},
+	{"WODT_D0_R0"                  ,	0,	8,	452,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D0_R1"                  ,	8,	8,	452,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D1_R0"                  ,	16,	8,	452,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D1_R1"                  ,	24,	8,	452,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D2_R0"                  ,	32,	8,	452,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D2_R1"                  ,	40,	8,	452,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D3_R0"                  ,	48,	8,	452,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D3_R1"                  ,	56,	8,	452,	"R/W",	0,	0,	255ull,	0ull},
+	{"STAT"                        ,	0,	12,	453,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	453,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	454,	"R/W",	1,	1,	0,	0},
+	{"PCTL"                        ,	6,	6,	454,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	454,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	455,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	455,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	455,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	456,	"R/W1C",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	456,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	456,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	457,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	457,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	457,	"RAZ",	1,	1,	0,	0},
+	{"DMARQ"                       ,	0,	6,	458,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_S"                     ,	6,	6,	458,	"R/W",	0,	1,	63ull,	0},
+	{"OE_A"                        ,	12,	6,	458,	"R/W",	0,	1,	63ull,	0},
+	{"OE_N"                        ,	18,	6,	458,	"R/W",	0,	1,	63ull,	0},
+	{"WE_A"                        ,	24,	6,	458,	"R/W",	0,	1,	63ull,	0},
+	{"WE_N"                        ,	30,	6,	458,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_H"                     ,	36,	6,	458,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	42,	6,	458,	"R/W",	0,	1,	63ull,	0},
+	{"RESERVED_48_54"              ,	48,	7,	458,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	55,	1,	458,	"R/W",	0,	1,	0ull,	0},
+	{"DDR"                         ,	56,	1,	458,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	57,	3,	458,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	60,	2,	458,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ_PI"                    ,	62,	1,	458,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK_PI"                    ,	63,	1,	458,	"R/W",	0,	1,	0ull,	0},
+	{"ADR_ERR"                     ,	0,	1,	459,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WAIT_ERR"                    ,	1,	1,	459,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	459,	"RAZ",	1,	1,	0,	0},
+	{"ADR_INT"                     ,	0,	1,	460,	"R/W",	0,	1,	0ull,	0},
+	{"WAIT_INT"                    ,	1,	1,	460,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	460,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	461,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	3,	5,	461,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	461,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	462,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	3,	25,	462,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_30"              ,	28,	3,	462,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	31,	1,	462,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	462,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	463,	"R/W",	1,	1,	0,	0},
+	{"USER0"                       ,	0,	8,	464,	"RO",	1,	1,	0,	0},
+	{"NAND"                        ,	8,	1,	464,	"RO",	1,	1,	0,	0},
+	{"TERM"                        ,	9,	2,	464,	"RO",	1,	1,	0,	0},
+	{"DMACK_P0"                    ,	11,	1,	464,	"RO",	1,	1,	0,	0},
+	{"DMACK_P1"                    ,	12,	1,	464,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_13"              ,	13,	1,	464,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	14,	1,	464,	"RO",	1,	1,	0,	0},
+	{"ALE"                         ,	15,	1,	464,	"RO",	1,	1,	0,	0},
+	{"USER1"                       ,	16,	16,	464,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	464,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	16,	465,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	16,	12,	465,	"R/W",	0,	1,	0ull,	0},
+	{"WIDTH"                       ,	28,	1,	465,	"R/W",	0,	1,	0ull,	0},
+	{"ALE"                         ,	29,	1,	465,	"R/W",	0,	1,	0ull,	0},
+	{"ORBIT"                       ,	30,	1,	465,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	31,	1,	465,	"R/W",	0,	1,	0ull,	0},
+	{"OE_EXT"                      ,	32,	2,	465,	"R/W",	0,	1,	0ull,	0},
+	{"WE_EXT"                      ,	34,	2,	465,	"R/W",	0,	1,	0ull,	0},
+	{"SAM"                         ,	36,	1,	465,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	37,	3,	465,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	40,	2,	465,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK"                       ,	42,	2,	465,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	465,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	6,	466,	"R/W",	0,	1,	63ull,	0},
+	{"CE"                          ,	6,	6,	466,	"R/W",	0,	1,	63ull,	0},
+	{"OE"                          ,	12,	6,	466,	"R/W",	0,	1,	63ull,	0},
+	{"WE"                          ,	18,	6,	466,	"R/W",	0,	1,	63ull,	0},
+	{"RD_HLD"                      ,	24,	6,	466,	"R/W",	0,	1,	63ull,	0},
+	{"WR_HLD"                      ,	30,	6,	466,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	36,	6,	466,	"R/W",	0,	1,	63ull,	0},
+	{"WAIT"                        ,	42,	6,	466,	"R/W",	0,	1,	63ull,	0},
+	{"PAGE"                        ,	48,	6,	466,	"R/W",	0,	1,	63ull,	0},
+	{"ALE"                         ,	54,	6,	466,	"R/W",	0,	1,	63ull,	0},
+	{"PAGES"                       ,	60,	2,	466,	"R/W",	0,	1,	0ull,	0},
+	{"WAITM"                       ,	62,	1,	466,	"R/W",	0,	1,	0ull,	0},
+	{"PAGEM"                       ,	63,	1,	466,	"R/W",	0,	1,	0ull,	0},
+	{"FIF_THR"                     ,	0,	6,	467,	"R/W",	0,	0,	25ull,	25ull},
+	{"RESERVED_6_7"                ,	6,	2,	467,	"RAZ",	1,	1,	0,	0},
+	{"FIF_CNT"                     ,	8,	6,	467,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	467,	"RAZ",	1,	1,	0,	0},
+	{"DMA_THR"                     ,	16,	6,	467,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_63"              ,	22,	42,	467,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	468,	"R/W",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	6,	469,	"R/W",	0,	1,	0ull,	0},
+	{"BUF_NUM"                     ,	6,	1,	469,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_15"               ,	7,	9,	469,	"RAZ",	0,	1,	0ull,	0},
+	{"INC"                         ,	16,	1,	469,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	469,	"RAZ",	0,	1,	0ull,	0},
+	{"BUS_ENA"                     ,	0,	4,	470,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_15"               ,	4,	12,	470,	"RAZ",	0,	1,	0ull,	0},
+	{"BOOT_FAIL"                   ,	16,	1,	470,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	470,	"RAZ",	0,	1,	0ull,	0},
+	{"ARG"                         ,	0,	32,	471,	"R/W",	0,	1,	0ull,	0},
+	{"CMD_IDX"                     ,	32,	6,	471,	"R/W",	0,	1,	0ull,	0},
+	{"RTYPE_XOR"                   ,	38,	3,	471,	"R/W",	0,	1,	0ull,	0},
+	{"CTYPE_XOR"                   ,	41,	2,	471,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_43_48"              ,	43,	6,	471,	"RAZ",	0,	1,	0ull,	0},
+	{"OFFSET"                      ,	49,	6,	471,	"R/W",	0,	1,	0ull,	0},
+	{"DBUF"                        ,	55,	1,	471,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_56_58"              ,	56,	3,	471,	"RAZ",	0,	1,	0ull,	0},
+	{"CMD_VAL"                     ,	59,	1,	471,	"R/W",	1,	1,	0,	0},
+	{"BUS_ID"                      ,	60,	2,	471,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	471,	"RAZ",	0,	1,	0ull,	0},
+	{"CARD_ADDR"                   ,	0,	32,	472,	"R/W",	0,	1,	0ull,	0},
+	{"BLOCK_CNT"                   ,	32,	16,	472,	"R/W",	0,	1,	0ull,	0},
+	{"MULTI"                       ,	48,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	49,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"REL_WR"                      ,	50,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"THRES"                       ,	51,	6,	472,	"R/W",	0,	1,	0ull,	0},
+	{"DAT_NULL"                    ,	57,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"SECTOR"                      ,	58,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"DMA_VAL"                     ,	59,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"BUS_ID"                      ,	60,	2,	472,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	472,	"RAZ",	0,	1,	0ull,	0},
+	{"BUF_DONE"                    ,	0,	1,	473,	"R/W1C",	1,	1,	0,	0},
+	{"CMD_DONE"                    ,	1,	1,	473,	"R/W1C",	1,	1,	0,	0},
+	{"DMA_DONE"                    ,	2,	1,	473,	"R/W1C",	1,	1,	0,	0},
+	{"CMD_ERR"                     ,	3,	1,	473,	"R/W1C",	1,	1,	0,	0},
+	{"DMA_ERR"                     ,	4,	1,	473,	"R/W1C",	1,	1,	0,	0},
+	{"SWITCH_DONE"                 ,	5,	1,	473,	"R/W1C",	1,	1,	0,	0},
+	{"SWITCH_ERR"                  ,	6,	1,	473,	"R/W1C",	1,	1,	0,	0},
+	{"RESERVED_7_63"               ,	7,	57,	473,	"RAZ",	0,	1,	0ull,	0},
+	{"BUF_DONE"                    ,	0,	1,	474,	"R/W",	1,	1,	0,	0},
+	{"CMD_DONE"                    ,	1,	1,	474,	"R/W",	1,	1,	0,	0},
+	{"DMA_DONE"                    ,	2,	1,	474,	"R/W",	1,	1,	0,	0},
+	{"CMD_ERR"                     ,	3,	1,	474,	"R/W",	1,	1,	0,	0},
+	{"DMA_ERR"                     ,	4,	1,	474,	"R/W",	1,	1,	0,	0},
+	{"SWITCH_DONE"                 ,	5,	1,	474,	"R/W",	1,	1,	0,	0},
+	{"SWITCH_ERR"                  ,	6,	1,	474,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_7_63"               ,	7,	57,	474,	"RAZ",	0,	1,	0ull,	0},
+	{"CLK_LO"                      ,	0,	16,	475,	"RO",	0,	1,	2500ull,	0},
+	{"CLK_HI"                      ,	16,	16,	475,	"RO",	0,	1,	2500ull,	0},
+	{"POWER_CLASS"                 ,	32,	4,	475,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	475,	"RAZ",	0,	1,	0ull,	0},
+	{"BUS_WIDTH"                   ,	40,	3,	475,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_43_47"              ,	43,	5,	475,	"RAZ",	0,	1,	0ull,	0},
+	{"HS_TIMING"                   ,	48,	1,	475,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_49_63"              ,	49,	15,	475,	"RAZ",	0,	1,	0ull,	0},
+	{"CARD_RCA"                    ,	0,	16,	476,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	476,	"RAZ",	0,	1,	0ull,	0},
+	{"DAT"                         ,	0,	64,	477,	"RO",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	478,	"RO",	1,	1,	0,	0},
+	{"CMD_DONE"                    ,	0,	1,	479,	"RO",	0,	1,	0ull,	0},
+	{"CMD_IDX"                     ,	1,	6,	479,	"RO",	0,	1,	0ull,	0},
+	{"CMD_TYPE"                    ,	7,	2,	479,	"RO",	0,	1,	0ull,	0},
+	{"RSP_TYPE"                    ,	9,	3,	479,	"RO",	0,	1,	0ull,	0},
+	{"RSP_VAL"                     ,	12,	1,	479,	"RO",	0,	1,	0ull,	0},
+	{"RSP_BAD_STS"                 ,	13,	1,	479,	"RO",	0,	1,	0ull,	0},
+	{"RSP_CRC_ERR"                 ,	14,	1,	479,	"RO",	0,	1,	0ull,	0},
+	{"RSP_TIMEOUT"                 ,	15,	1,	479,	"RO",	0,	1,	0ull,	0},
+	{"STP_VAL"                     ,	16,	1,	479,	"RO",	0,	1,	0ull,	0},
+	{"STP_BAD_STS"                 ,	17,	1,	479,	"RO",	0,	1,	0ull,	0},
+	{"STP_CRC_ERR"                 ,	18,	1,	479,	"RO",	0,	1,	0ull,	0},
+	{"STP_TIMEOUT"                 ,	19,	1,	479,	"RO",	0,	1,	0ull,	0},
+	{"RSP_BUSYBIT"                 ,	20,	1,	479,	"RO",	0,	1,	0ull,	0},
+	{"BLK_CRC_ERR"                 ,	21,	1,	479,	"RO",	0,	1,	0ull,	0},
+	{"BLK_TIMEOUT"                 ,	22,	1,	479,	"RO",	0,	1,	0ull,	0},
+	{"DBUF"                        ,	23,	1,	479,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_24_27"              ,	24,	4,	479,	"RAZ",	0,	1,	0ull,	0},
+	{"DBUF_ERR"                    ,	28,	1,	479,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_55"              ,	29,	27,	479,	"RAZ",	0,	1,	0ull,	0},
+	{"DMA_PEND"                    ,	56,	1,	479,	"RO",	0,	1,	0ull,	0},
+	{"DMA_VAL"                     ,	57,	1,	479,	"RO",	0,	1,	0ull,	0},
+	{"SWITCH_VAL"                  ,	58,	1,	479,	"RO",	0,	1,	0ull,	0},
+	{"CMD_VAL"                     ,	59,	1,	479,	"RO",	0,	1,	0ull,	0},
+	{"BUS_ID"                      ,	60,	2,	479,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	479,	"RAZ",	0,	1,	0ull,	0},
+	{"DAT_CNT"                     ,	0,	10,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	480,	"RAZ",	0,	1,	0ull,	0},
+	{"CMD_CNT"                     ,	16,	10,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_63"              ,	26,	38,	480,	"RAZ",	0,	1,	0ull,	0},
+	{"STS_MSK"                     ,	0,	32,	481,	"R/W",	0,	1,	3828940928ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	481,	"RAZ",	0,	1,	0ull,	0},
+	{"CLK_LO"                      ,	0,	16,	482,	"R/W",	0,	1,	2500ull,	0},
+	{"CLK_HI"                      ,	16,	16,	482,	"R/W",	0,	1,	2500ull,	0},
+	{"POWER_CLASS"                 ,	32,	4,	482,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	482,	"RAZ",	0,	1,	0ull,	0},
+	{"BUS_WIDTH"                   ,	40,	3,	482,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_43_47"              ,	43,	5,	482,	"RAZ",	0,	1,	0ull,	0},
+	{"HS_TIMING"                   ,	48,	1,	482,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_49_55"              ,	49,	7,	482,	"RAZ",	0,	1,	0ull,	0},
+	{"SWITCH_ERR2"                 ,	56,	1,	482,	"RO",	0,	1,	0ull,	0},
+	{"SWITCH_ERR1"                 ,	57,	1,	482,	"RO",	0,	1,	0ull,	0},
+	{"SWITCH_ERR0"                 ,	58,	1,	482,	"RO",	0,	1,	0ull,	0},
+	{"SWITCH_EXE"                  ,	59,	1,	482,	"R/W",	0,	1,	0ull,	0},
+	{"BUS_ID"                      ,	60,	2,	482,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	482,	"RAZ",	0,	1,	0ull,	0},
+	{"CLK_CNT"                     ,	0,	26,	483,	"R/W",	0,	1,	41855000ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	483,	"RAZ",	0,	1,	0ull,	0},
+	{"DAT"                         ,	0,	64,	484,	"R/W",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	485,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	485,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	486,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	486,	"RAZ",	1,	1,	0,	0},
+	{"PP_DIS"                      ,	0,	4,	487,	"RO",	1,	1,	0,	0},
+	{"RESERVED_4_15"               ,	4,	12,	487,	"RO",	1,	1,	0,	0},
+	{"CHIP_ID"                     ,	16,	8,	487,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_25"              ,	24,	2,	487,	"RO",	1,	1,	0,	0},
+	{"NOCRYPTO"                    ,	26,	1,	487,	"RO",	1,	1,	0,	0},
+	{"NOMUL"                       ,	27,	1,	487,	"RO",	1,	1,	0,	0},
+	{"NODFA_CP2"                   ,	28,	1,	487,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_31"              ,	29,	3,	487,	"RO",	1,	1,	0,	0},
+	{"RAID_EN"                     ,	32,	1,	487,	"RO",	1,	1,	0,	0},
+	{"FUS318"                      ,	33,	1,	487,	"RO",	1,	1,	0,	0},
+	{"DORM_CRYPTO"                 ,	34,	1,	487,	"RO",	1,	1,	0,	0},
+	{"POWER_LIMIT"                 ,	35,	2,	487,	"RO",	1,	1,	0,	0},
+	{"ROM_INFO"                    ,	37,	10,	487,	"RO",	1,	1,	0,	0},
+	{"FUS118"                      ,	47,	1,	487,	"RO",	1,	1,	0,	0},
+	{"RESERVED_48_63"              ,	48,	16,	487,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	488,	"RAZ",	1,	1,	0,	0},
+	{"NODFA_DTE"                   ,	24,	1,	488,	"RO",	1,	1,	0,	0},
+	{"NOZIP"                       ,	25,	1,	488,	"RO",	1,	1,	0,	0},
+	{"EFUS_IGN"                    ,	26,	1,	488,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK"                    ,	27,	1,	488,	"RO",	1,	1,	0,	0},
+	{"BAR2_EN"                     ,	28,	1,	488,	"RO",	1,	1,	0,	0},
+	{"ZIP_INFO"                    ,	29,	2,	488,	"RO",	1,	1,	0,	0},
+	{"RESERVED_31_31"              ,	31,	1,	488,	"RAZ",	1,	1,	0,	0},
+	{"L2C_CRIP"                    ,	32,	3,	488,	"RO",	1,	1,	0,	0},
+	{"PLL_HALF_DIS"                ,	35,	1,	488,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK_MAN"                ,	36,	1,	488,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK_RSV"                ,	37,	1,	488,	"RO",	1,	1,	0,	0},
+	{"EMA"                         ,	38,	2,	488,	"RO",	1,	1,	0,	0},
+	{"RESERVED_40_40"              ,	40,	1,	488,	"RAZ",	1,	1,	0,	0},
+	{"DFA_INFO_CLM"                ,	41,	4,	488,	"RO",	1,	1,	0,	0},
+	{"DFA_INFO_DTE"                ,	45,	3,	488,	"RO",	1,	1,	0,	0},
+	{"PLL_CTL"                     ,	48,	10,	488,	"RO",	1,	1,	0,	0},
+	{"RESERVED_58_63"              ,	58,	6,	488,	"RAZ",	1,	1,	0,	0},
+	{"EMA"                         ,	0,	3,	489,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_3_3"                ,	3,	1,	489,	"RAZ",	1,	1,	0,	0},
+	{"EFF_EMA"                     ,	4,	3,	489,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_7_63"               ,	7,	57,	489,	"RAZ",	1,	1,	0,	0},
+	{"PDF"                         ,	0,	64,	490,	"RO",	1,	1,	0,	0},
+	{"FBSLIP"                      ,	0,	1,	491,	"RAZ",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	491,	"RAZ",	0,	1,	0ull,	0},
+	{"PNR_COUT_SEL"                ,	2,	2,	491,	"R/W",	0,	1,	0ull,	0},
+	{"PNR_COUT_RST"                ,	4,	1,	491,	"R/W",	0,	1,	0ull,	0},
+	{"C_COUT_SEL"                  ,	5,	2,	491,	"R/W",	0,	1,	0ull,	0},
+	{"C_COUT_RST"                  ,	7,	1,	491,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	491,	"RAZ",	1,	1,	0,	0},
+	{"PROG"                        ,	0,	1,	492,	"R/W",	1,	1,	0,	0},
+	{"SOFT"                        ,	1,	1,	492,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	492,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	6,	493,	"R/W",	0,	1,	1ull,	0},
+	{"SCLK_HI"                     ,	6,	15,	493,	"R/W",	0,	1,	5000ull,	0},
+	{"SCLK_LO"                     ,	21,	4,	493,	"R/W",	0,	1,	1ull,	0},
+	{"OUT"                         ,	25,	7,	493,	"R/W",	0,	1,	1ull,	0},
+	{"PROG_PIN"                    ,	32,	1,	493,	"RO",	0,	0,	0ull,	0ull},
+	{"FSRC_PIN"                    ,	33,	1,	493,	"RO",	0,	0,	0ull,	0ull},
+	{"VGATE_PIN"                   ,	34,	1,	493,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	493,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	8,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"EFUSE"                       ,	8,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	494,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	12,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	494,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	16,	8,	494,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_63"              ,	24,	40,	494,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	10,	495,	"R/W",	0,	1,	999ull,	0},
+	{"SDH"                         ,	10,	4,	495,	"R/W",	0,	1,	0ull,	0},
+	{"PRH"                         ,	14,	4,	495,	"R/W",	0,	1,	6ull,	0},
+	{"FSH"                         ,	18,	4,	495,	"R/W",	0,	1,	15ull,	0},
+	{"SCH"                         ,	22,	4,	495,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	495,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	18,	496,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR1"                     ,	18,	18,	496,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR2"                     ,	36,	18,	496,	"RO",	0,	0,	0ull,	0ull},
+	{"TOO_MANY"                    ,	54,	1,	496,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	496,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR3"                     ,	0,	18,	497,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR4"                     ,	18,	18,	497,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR5"                     ,	36,	18,	497,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	497,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR6"                     ,	0,	18,	498,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	498,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	14,	499,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR1"                     ,	14,	14,	499,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR2"                     ,	28,	14,	499,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_42_63"              ,	42,	22,	499,	"RAZ",	1,	1,	0,	0},
+	{"TOO_MANY"                    ,	0,	1,	500,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	500,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	63,	501,	"RO",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	501,	"R/W",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	4,	502,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_4_63"               ,	4,	60,	502,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	503,	"R/W",	0,	1,	15ull,	0},
+	{"PCTL"                        ,	6,	6,	503,	"R/W",	0,	1,	19ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	503,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	504,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	504,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	504,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	504,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	504,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	504,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	504,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	504,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	504,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	504,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	505,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	505,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	506,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	506,	"RAZ",	1,	1,	0,	0},
+	{"FRNANOSEC"                   ,	0,	32,	507,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	507,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	0,	64,	509,	"R/W",	0,	0,	18446744073709551615ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	510,	"R/W",	0,	0,	4294967295ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	510,	"RAZ",	1,	1,	0,	0},
+	{"PTP_EN"                      ,	0,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_CLK_EN"                  ,	1,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_CLK_IN"                  ,	2,	6,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_EN"                    ,	8,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_EDGE"                  ,	9,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_IN"                    ,	10,	6,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_EN"                    ,	16,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_EDGE"                  ,	17,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_IN"                    ,	18,	6,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT_EN"                    ,	24,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT_INV"                   ,	25,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT_OUT"                   ,	26,	4,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS_EN"                      ,	30,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS_INV"                     ,	31,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS_OUT"                     ,	32,	5,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT_OUT4"                  ,	37,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_CLK_EDGE"                ,	38,	2,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT"                       ,	40,	1,	511,	"RO",	1,	0,	0,	0ull},
+	{"PPS"                         ,	41,	1,	511,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	511,	"RAZ",	1,	1,	0,	0},
+	{"FRNANOSEC"                   ,	0,	32,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	0,	64,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	514,	"RAZ",	1,	1,	0,	0},
+	{"CNTR"                        ,	0,	64,	515,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	517,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	517,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	0,	64,	518,	"R/W",	0,	0,	18446744073709551615ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	519,	"R/W",	0,	0,	4294967295ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	519,	"RAZ",	1,	1,	0,	0},
+	{"NANOSEC"                     ,	0,	64,	520,	"R/W",	0,	0,	0ull,	0ull},
+	{"QLM_CFG"                     ,	0,	2,	521,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_2_7"                ,	2,	6,	521,	"RAZ",	1,	1,	0,	0},
+	{"QLM_SPD"                     ,	8,	4,	521,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_12_13"              ,	12,	2,	521,	"RAZ",	1,	1,	0,	0},
+	{"PRTMODE"                     ,	14,	1,	521,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	521,	"RAZ",	1,	1,	0,	0},
+	{"RBOOT_PIN"                   ,	0,	1,	522,	"RO",	1,	1,	0,	0},
+	{"RBOOT"                       ,	1,	1,	522,	"R/W",	1,	1,	0,	0},
+	{"LBOOT"                       ,	2,	10,	522,	"R/W1C",	1,	1,	0,	0},
+	{"QLM0_SPD"                    ,	12,	4,	522,	"RO",	1,	1,	0,	0},
+	{"QLM1_SPD"                    ,	16,	4,	522,	"RO",	1,	1,	0,	0},
+	{"QLM2_SPD"                    ,	20,	4,	522,	"RO",	1,	1,	0,	0},
+	{"PNR_MUL"                     ,	24,	6,	522,	"RO",	1,	1,	0,	0},
+	{"C_MUL"                       ,	30,	6,	522,	"RO",	1,	1,	0,	0},
+	{"RESERVED_36_47"              ,	36,	12,	522,	"RAZ",	1,	1,	0,	0},
+	{"LBOOT_EXT"                   ,	48,	2,	522,	"R/W1C",	1,	1,	0,	0},
+	{"RESERVED_50_57"              ,	50,	8,	522,	"RAZ",	1,	1,	0,	0},
+	{"JT_TSTMODE"                  ,	58,	1,	522,	"RO",	1,	1,	0,	0},
+	{"CKILL_PPDIS"                 ,	59,	1,	522,	"R/W",	0,	1,	1ull,	0},
+	{"ROMEN"                       ,	60,	1,	522,	"R/W",	1,	1,	0,	0},
+	{"EJTAGDIS"                    ,	61,	1,	522,	"R/W",	1,	1,	0,	0},
+	{"JTCSRDIS"                    ,	62,	1,	522,	"R/W",	1,	1,	0,	0},
+	{"CHIPKILL"                    ,	63,	1,	522,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SOFT_CLR_BIST"               ,	0,	1,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"WARM_CLR_BIST"               ,	1,	1,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNTL_CLR_BIST"               ,	2,	1,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_5"                ,	3,	3,	523,	"RAZ",	1,	1,	0,	0},
+	{"BIST_DELAY"                  ,	6,	58,	523,	"RO",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	47,	524,	"R/W",	0,	1,	17179869183ull,	0},
+	{"RESERVED_47_63"              ,	47,	17,	524,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RST_VAL"                     ,	0,	1,	525,	"RO",	1,	1,	0,	0},
+	{"RST_CHIP"                    ,	1,	1,	525,	"R/W",	0,	1,	0ull,	0},
+	{"RST_RCV"                     ,	2,	1,	525,	"R/W",	1,	1,	0,	0},
+	{"RST_DRV"                     ,	3,	1,	525,	"R/W",	1,	1,	0,	0},
+	{"PRTMODE"                     ,	4,	2,	525,	"R/W",	1,	1,	0,	0},
+	{"HOST_MODE"                   ,	6,	1,	525,	"RO",	1,	1,	0,	0},
+	{"RST_LINK"                    ,	7,	1,	525,	"R/W",	1,	1,	0,	0},
+	{"RST_DONE"                    ,	8,	1,	525,	"RO",	1,	1,	0,	0},
+	{"PRST_LINK"                   ,	9,	1,	525,	"R/W",	0,	1,	0ull,	0},
+	{"GEN1_ONLY"                   ,	10,	1,	525,	"RO",	0,	1,	0ull,	0},
+	{"REV_LANES"                   ,	11,	1,	525,	"R/W",	1,	1,	0,	0},
+	{"IN_REV_LN"                   ,	12,	1,	525,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	525,	"RAZ",	1,	1,	0,	0},
+	{"RST_VAL"                     ,	0,	1,	526,	"RO",	1,	1,	0,	0},
+	{"RST_CHIP"                    ,	1,	1,	526,	"R/W",	0,	1,	0ull,	0},
+	{"RST_RCV"                     ,	2,	1,	526,	"R/W",	1,	1,	0,	0},
+	{"RST_DRV"                     ,	3,	1,	526,	"R/W",	1,	1,	0,	0},
+	{"PRTMODE"                     ,	4,	2,	526,	"R/W",	1,	1,	0,	0},
+	{"HOST_MODE"                   ,	6,	1,	526,	"RO",	1,	1,	0,	0},
+	{"RST_LINK"                    ,	7,	1,	526,	"R/W",	1,	1,	0,	0},
+	{"RST_DONE"                    ,	8,	1,	526,	"RO",	1,	1,	0,	0},
+	{"PRST_LINK"                   ,	9,	1,	526,	"R/W",	0,	1,	0ull,	0},
+	{"GEN1_ONLY"                   ,	10,	1,	526,	"RO",	0,	1,	0ull,	0},
+	{"REV_LANES"                   ,	11,	1,	526,	"R/W",	1,	1,	0,	0},
+	{"IN_REV_LN"                   ,	12,	1,	526,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	526,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST_DLY"                ,	0,	16,	527,	"R/W",	0,	1,	2047ull,	0},
+	{"WARM_RST_DLY"                ,	16,	16,	527,	"R/W",	0,	1,	2047ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	527,	"RAZ",	1,	1,	0,	0},
+	{"RST_LINK0"                   ,	0,	1,	528,	"R/W1C",	0,	1,	0ull,	0},
+	{"RST_LINK1"                   ,	1,	1,	528,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_7"                ,	2,	6,	528,	"RAZ",	1,	1,	0,	0},
+	{"PERST0"                      ,	8,	1,	528,	"R/W1C",	0,	1,	0ull,	0},
+	{"PERST1"                      ,	9,	1,	528,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	528,	"RAZ",	1,	1,	0,	0},
+	{"RST_LINK0"                   ,	0,	1,	529,	"R/W",	0,	1,	0ull,	0},
+	{"RST_LINK1"                   ,	1,	1,	529,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_7"                ,	2,	6,	529,	"RAZ",	1,	1,	0,	0},
+	{"PERST0"                      ,	8,	1,	529,	"R/W",	0,	1,	0ull,	0},
+	{"PERST1"                      ,	9,	1,	529,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	529,	"RAZ",	1,	1,	0,	0},
+	{"ST_INT"                      ,	0,	1,	530,	"R/W1C",	0,	1,	0ull,	0},
+	{"TS_INT"                      ,	1,	1,	530,	"R/W1C",	0,	1,	0ull,	0},
+	{"CORE_INT"                    ,	2,	1,	530,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	530,	"RAZ",	1,	1,	0,	0},
+	{"ST_EN"                       ,	4,	1,	530,	"R/W",	0,	1,	0ull,	0},
+	{"TS_EN"                       ,	5,	1,	530,	"R/W",	0,	1,	0ull,	0},
+	{"CORE_EN"                     ,	6,	1,	530,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	530,	"RAZ",	1,	1,	0,	0},
+	{"SDA_OVR"                     ,	8,	1,	530,	"R/W",	0,	1,	0ull,	0},
+	{"SCL_OVR"                     ,	9,	1,	530,	"R/W",	0,	1,	0ull,	0},
+	{"SDA"                         ,	10,	1,	530,	"RO",	1,	1,	0,	0},
+	{"SCL"                         ,	11,	1,	530,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	530,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	531,	"R/W",	0,	1,	0ull,	0},
+	{"EOP_IA"                      ,	32,	3,	531,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	35,	5,	531,	"R/W",	0,	1,	0ull,	0},
+	{"A"                           ,	40,	10,	531,	"R/W",	0,	1,	0ull,	0},
+	{"SCR"                         ,	50,	2,	531,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	52,	3,	531,	"R/W",	0,	1,	0ull,	0},
+	{"SOVR"                        ,	55,	1,	531,	"R/W",	0,	1,	0ull,	0},
+	{"R"                           ,	56,	1,	531,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	57,	4,	531,	"R/W",	0,	1,	0ull,	0},
+	{"EIA"                         ,	61,	1,	531,	"R/W",	0,	1,	0ull,	0},
+	{"SLONLY"                      ,	62,	1,	531,	"R/W",	0,	1,	0ull,	0},
+	{"V"                           ,	63,	1,	531,	"RC/W",	0,	1,	0ull,	0},
+	{"D"                           ,	0,	32,	532,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	32,	8,	532,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	532,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	533,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_32_61"              ,	32,	30,	533,	"RAZ",	1,	1,	0,	0},
+	{"V"                           ,	62,	2,	533,	"RC/W",	0,	1,	0ull,	0},
+	{"DLH"                         ,	0,	8,	534,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	534,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	535,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	535,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	536,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	536,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	537,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	537,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	537,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	537,	"RAZ",	1,	1,	0,	0},
+	{"TXTRIG"                      ,	4,	2,	537,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	537,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	537,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	538,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	538,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	539,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	539,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	539,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	539,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	539,	"RAZ",	1,	1,	0,	0},
+	{"PTIME"                       ,	7,	1,	539,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	539,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	540,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	540,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	540,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	540,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	541,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	541,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	541,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	541,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	541,	"RAZ",	1,	1,	0,	0},
+	{"BRK"                         ,	6,	1,	541,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	541,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	541,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	542,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	542,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	542,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	542,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	542,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	542,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	542,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	542,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	542,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	543,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	543,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	543,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	543,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	543,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	543,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	543,	"RAZ",	1,	1,	0,	0},
+	{"DCTS"                        ,	0,	1,	544,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	544,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	544,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	544,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	544,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	544,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	544,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	544,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	544,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	545,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	545,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	546,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	546,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	547,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	547,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	547,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	547,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	548,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	548,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	549,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	549,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	550,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	550,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	551,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	551,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	551,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	551,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	552,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	552,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	553,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	553,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	554,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	554,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	555,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	555,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	556,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	556,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	557,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	557,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	558,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	558,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	558,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	558,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	558,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	558,	"RAZ",	1,	1,	0,	0},
+	{"ORFDAT"                      ,	0,	1,	559,	"RO",	0,	0,	0ull,	0ull},
+	{"IRFDAT"                      ,	1,	1,	559,	"RO",	0,	0,	0ull,	0ull},
+	{"IPFDAT"                      ,	2,	1,	559,	"RO",	0,	0,	0ull,	0ull},
+	{"MRQDAT"                      ,	3,	1,	559,	"RO",	0,	0,	0ull,	0ull},
+	{"MRGDAT"                      ,	4,	1,	559,	"RO",	0,	0,	0ull,	0ull},
+	{"OPFDAT"                      ,	5,	1,	559,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	559,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MRQ_HWM"                     ,	0,	2,	560,	"R/W",	0,	0,	0ull,	1ull},
+	{"NBTARB"                      ,	2,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENDIAN"                     ,	3,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	4,	1,	560,	"R/W",	0,	0,	1ull,	0ull},
+	{"EN"                          ,	5,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"BUSY"                        ,	6,	1,	560,	"RO",	0,	0,	0ull,	0ull},
+	{"CRC_STRIP"                   ,	7,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"TS_THRESH"                   ,	8,	4,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	560,	"RAZ",	1,	1,	0,	0},
+	{"OVFENA"                      ,	0,	1,	561,	"R/W",	0,	0,	0ull,	0ull},
+	{"IVFENA"                      ,	1,	1,	561,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTHENA"                      ,	2,	1,	561,	"R/W",	0,	0,	0ull,	0ull},
+	{"ITHENA"                      ,	3,	1,	561,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_DRPENA"                 ,	4,	1,	561,	"R/W",	0,	0,	0ull,	0ull},
+	{"IRUNENA"                     ,	5,	1,	561,	"R/W",	0,	0,	0ull,	0ull},
+	{"ORUNENA"                     ,	6,	1,	561,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSENA"                       ,	7,	1,	561,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	561,	"RAZ",	1,	1,	0,	0},
+	{"IRCNT"                       ,	0,	20,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	562,	"RAZ",	1,	1,	0,	0},
+	{"IRHWM"                       ,	0,	20,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"IBPLWM"                      ,	20,	20,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	563,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	564,	"RAZ",	1,	1,	0,	0},
+	{"IBASE"                       ,	3,	37,	564,	"R/W",	0,	1,	0ull,	0},
+	{"ISIZE"                       ,	40,	20,	564,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	564,	"RAZ",	1,	1,	0,	0},
+	{"IDBELL"                      ,	0,	20,	565,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	565,	"RAZ",	1,	1,	0,	0},
+	{"ITLPTR"                      ,	32,	20,	565,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	565,	"RAZ",	1,	1,	0,	0},
+	{"ODBLOVF"                     ,	0,	1,	566,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IDBLOVF"                     ,	1,	1,	566,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORTHRESH"                    ,	2,	1,	566,	"RO",	0,	0,	0ull,	0ull},
+	{"IRTHRESH"                    ,	3,	1,	566,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_DRP"                    ,	4,	1,	566,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IRUN"                        ,	5,	1,	566,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORUN"                        ,	6,	1,	566,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TS"                          ,	7,	1,	566,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	566,	"RAZ",	1,	1,	0,	0},
+	{"ORCNT"                       ,	0,	20,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	567,	"RAZ",	1,	1,	0,	0},
+	{"ORHWM"                       ,	0,	20,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	568,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	569,	"RAZ",	1,	1,	0,	0},
+	{"OBASE"                       ,	3,	37,	569,	"R/W",	0,	1,	0ull,	0},
+	{"OSIZE"                       ,	40,	20,	569,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	569,	"RAZ",	1,	1,	0,	0},
+	{"ODBELL"                      ,	0,	20,	570,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	570,	"RAZ",	1,	1,	0,	0},
+	{"OTLPTR"                      ,	32,	20,	570,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	570,	"RAZ",	1,	1,	0,	0},
+	{"OREMCNT"                     ,	0,	20,	571,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	571,	"RAZ",	1,	1,	0,	0},
+	{"IREMCNT"                     ,	32,	20,	571,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_52_63"              ,	52,	12,	571,	"RAZ",	1,	1,	0,	0},
+	{"TSCNT"                       ,	0,	5,	572,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	572,	"RAZ",	1,	1,	0,	0},
+	{"TSTOT"                       ,	8,	5,	572,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	572,	"RAZ",	1,	1,	0,	0},
+	{"TSAVL"                       ,	16,	5,	572,	"RO",	0,	0,	4ull,	4ull},
+	{"RESERVED_21_63"              ,	21,	43,	572,	"RAZ",	1,	1,	0,	0},
+	{"TSTAMP"                      ,	0,	64,	573,	"RO",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDLELO"                      ,	1,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_CONT"                    ,	2,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"WIREOR"                      ,	3,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBFIRST"                    ,	4,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_ENA"                     ,	5,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	574,	"RAZ",	1,	1,	0,	0},
+	{"CSHI"                        ,	7,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDLECLKS"                    ,	8,	2,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRITX"                       ,	10,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSLATE"                      ,	11,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSENA0"                      ,	12,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSENA1"                      ,	13,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	574,	"RAZ",	1,	1,	0,	0},
+	{"CLKDIV"                      ,	16,	13,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	574,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	8,	575,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	575,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	576,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	576,	"RAZ",	1,	1,	0,	0},
+	{"RXNUM"                       ,	8,	5,	576,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	576,	"RAZ",	1,	1,	0,	0},
+	{"TOTNUM"                      ,	0,	5,	577,	"WO",	1,	0,	0,	2ull},
+	{"RESERVED_5_7"                ,	5,	3,	577,	"RAZ",	1,	1,	0,	0},
+	{"TXNUM"                       ,	8,	5,	577,	"WO",	1,	0,	0,	1ull},
+	{"RESERVED_13_15"              ,	13,	3,	577,	"RAZ",	1,	1,	0,	0},
+	{"LEAVECS"                     ,	16,	1,	577,	"WO",	1,	0,	0,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	577,	"RAZ",	1,	1,	0,	0},
+	{"CSID"                        ,	20,	1,	577,	"WO",	1,	0,	0,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	577,	"RAZ",	1,	1,	0,	0},
+	{"VENDID"                      ,	0,	16,	578,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	578,	"RO/WRSL",	0,	0,	147ull,	147ull},
+	{"ISAE"                        ,	0,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	579,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	579,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	579,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	579,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	579,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	579,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	579,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	579,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	579,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	579,	"RAZ",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	579,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	579,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	580,	"RO/WRSL",	0,	0,	8ull,	8ull},
+	{"PI"                          ,	8,	8,	580,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	580,	"RO/WRSL",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	580,	"RO/WRSL",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	581,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	581,	"RO",	0,	0,	0ull,	0ull},
+	{"MFD"                         ,	23,	1,	581,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	581,	"RO",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	582,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	582,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	582,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_13"               ,	4,	10,	582,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	14,	18,	582,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	583,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	583,	"WORSL",	0,	0,	8191ull,	8191ull},
+	{"UBAB"                        ,	0,	32,	584,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	585,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	586,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	586,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	586,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_25"               ,	4,	22,	586,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	26,	6,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	587,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	587,	"WORSL",	0,	0,	33554431ull,	33554431ull},
+	{"UBAB"                        ,	0,	32,	588,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	589,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	590,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	590,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	590,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_31"               ,	4,	28,	590,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	1,	591,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	591,	"WORSL",	0,	0,	2147483647ull,	2147483647ull},
+	{"RESERVED_0_8"                ,	0,	9,	592,	"RAZ",	1,	1,	0,	0},
+	{"UBAB"                        ,	9,	23,	592,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	593,	"WORSL",	0,	0,	511ull,	511ull},
+	{"CISP"                        ,	0,	32,	594,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SSVID"                       ,	0,	16,	595,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"SSID"                        ,	16,	16,	595,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"ER_EN"                       ,	0,	1,	596,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_15"               ,	1,	15,	596,	"RAZ",	1,	1,	0,	0},
+	{"ERADDR"                      ,	16,	16,	596,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	597,	"WORSL",	0,	0,	1ull,	1ull},
+	{"MASK"                        ,	1,	31,	597,	"WORSL",	0,	0,	32767ull,	32767ull},
+	{"CP"                          ,	0,	8,	598,	"RO/WRSL",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	598,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	599,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	599,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"MG"                          ,	16,	8,	599,	"RO",	0,	0,	0ull,	0ull},
+	{"ML"                          ,	24,	8,	599,	"RO",	0,	0,	0ull,	0ull},
+	{"PMCID"                       ,	0,	8,	600,	"RO",	0,	0,	1ull,	0ull},
+	{"NCP"                         ,	8,	8,	600,	"RO/WRSL",	0,	0,	80ull,	0ull},
+	{"PMSV"                        ,	16,	3,	600,	"RO/WRSL",	0,	0,	3ull,	0ull},
+	{"PME_CLOCK"                   ,	19,	1,	600,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	600,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	600,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	600,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	600,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	600,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	600,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	601,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	601,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	601,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	601,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	601,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	601,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	601,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	601,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	601,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	601,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	602,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	602,	"RO/WRSL",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	602,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	602,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"PVM"                         ,	24,	1,	602,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	602,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	603,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	603,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	604,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	605,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	606,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	606,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	606,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"SI"                          ,	24,	1,	606,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	606,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	606,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	607,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	607,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	607,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	607,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"EL1AL"                       ,	9,	3,	607,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"RESERVED_12_14"              ,	12,	3,	607,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	607,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	607,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	607,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	607,	"RO",	0,	0,	0ull,	0ull},
+	{"FLR_CAP"                     ,	28,	1,	607,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	607,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	608,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	608,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	608,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	608,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	608,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	608,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	608,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	608,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	608,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	608,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	608,	"R/W",	0,	0,	2ull,	2ull},
+	{"I_FLR"                       ,	15,	1,	608,	"RO",	0,	0,	0ull,	0ull},
+	{"CE_D"                        ,	16,	1,	608,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	608,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	608,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	608,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	608,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	608,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	608,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	609,	"RO/WRSL",	1,	1,	0,	0},
+	{"MLW"                         ,	4,	6,	609,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"ASLPMS"                      ,	10,	2,	609,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	609,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	609,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	609,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	609,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	609,	"RO",	0,	0,	0ull,	0ull},
+	{"LBNC"                        ,	21,	1,	609,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPM"                        ,	22,	1,	609,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_23_23"              ,	23,	1,	609,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	609,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	610,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"LD"                          ,	4,	1,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"LBM_INT_ENB"                 ,	10,	1,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"LAB_INT_ENB"                 ,	11,	1,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	610,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	610,	"RO",	0,	0,	1ull,	1ull},
+	{"NLW"                         ,	20,	6,	610,	"RO",	0,	0,	1ull,	4ull},
+	{"RESERVED_26_26"              ,	26,	1,	610,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	610,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"DLLA"                        ,	29,	1,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"LBM"                         ,	30,	1,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"LAB"                         ,	31,	1,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"CTRS"                        ,	0,	4,	611,	"RO",	0,	0,	15ull,	15ull},
+	{"CTDS"                        ,	4,	1,	611,	"RO",	0,	0,	1ull,	1ull},
+	{"ARI"                         ,	5,	1,	611,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OPS"                    ,	6,	1,	611,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM32S"                     ,	7,	1,	611,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM64S"                     ,	8,	1,	611,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM128S"                    ,	9,	1,	611,	"RO",	0,	0,	0ull,	0ull},
+	{"NOROPRPR"                    ,	10,	1,	611,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	611,	"RAZ",	1,	1,	0,	0},
+	{"TPH"                         ,	12,	2,	611,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	611,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	612,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	612,	"R/W",	0,	0,	0ull,	0ull},
+	{"ARI"                         ,	5,	1,	612,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP"                     ,	6,	1,	612,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP_EB"                  ,	7,	1,	612,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_RQ"                      ,	8,	1,	612,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_CP"                      ,	9,	1,	612,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_31"              ,	10,	22,	612,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	613,	"RAZ",	1,	1,	0,	0},
+	{"SLSV"                        ,	1,	7,	613,	"RO/WRSL",	1,	1,	0,	0},
+	{"CLS"                         ,	8,	1,	613,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	613,	"RAZ",	1,	1,	0,	0},
+	{"TLS"                         ,	0,	4,	614,	"R/W",	1,	0,	0,	2ull},
+	{"EC"                          ,	4,	1,	614,	"R/W",	0,	0,	0ull,	0ull},
+	{"HASD"                        ,	5,	1,	614,	"RO",	0,	0,	0ull,	0ull},
+	{"SDE"                         ,	6,	1,	614,	"RO",	0,	0,	0ull,	0ull},
+	{"TM"                          ,	7,	3,	614,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMC"                         ,	10,	1,	614,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSOS"                        ,	11,	1,	614,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDE"                         ,	12,	1,	614,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	614,	"RAZ",	1,	1,	0,	0},
+	{"CDL"                         ,	16,	1,	614,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	614,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	615,	"RO",	0,	0,	1ull,	1ull},
+	{"CV"                          ,	16,	4,	615,	"RO",	0,	0,	2ull,	2ull},
+	{"NCO"                         ,	20,	12,	615,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	616,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	616,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	616,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	616,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	616,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	616,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	616,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	616,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	616,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	616,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	616,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	616,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	616,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	616,	"RAZ",	1,	1,	0,	0},
+	{"UATOMBS"                     ,	24,	1,	616,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	616,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	617,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	617,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	617,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	617,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	617,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	617,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	617,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	617,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	617,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	617,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	617,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	617,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	617,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	617,	"RAZ",	1,	1,	0,	0},
+	{"UATOMBM"                     ,	24,	1,	617,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	617,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	618,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	618,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	618,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	618,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	618,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	618,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	618,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	618,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	618,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	618,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	618,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	618,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	618,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	618,	"RO",	0,	0,	2ull,	2ull},
+	{"UATOMBS"                     ,	24,	1,	618,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	618,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	619,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	619,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	619,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	620,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	620,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	620,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	620,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	620,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	620,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	620,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	620,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	620,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	621,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	621,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	621,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	621,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	622,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	623,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	624,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	625,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	626,	"R/W",	0,	1,	4143ull,	0},
+	{"RTL"                         ,	16,	16,	626,	"R/W",	0,	1,	12429ull,	0},
+	{"OMR"                         ,	0,	32,	627,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	628,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_14"               ,	8,	7,	628,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	628,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	628,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	628,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	628,	"R/W",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	629,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	629,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	629,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	629,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	629,	"R/W",	0,	0,	3ull,	3ull},
+	{"EASPML1"                     ,	30,	1,	629,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	629,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	630,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	630,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	630,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	630,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	630,	"R/W",	0,	0,	7ull,	7ull},
+	{"RESERVED_22_31"              ,	22,	10,	630,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	631,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"MFUNCN"                      ,	0,	8,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_13"               ,	8,	6,	632,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	632,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"CX_NFUNC"                    ,	29,	3,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPIV"                       ,	0,	11,	633,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	633,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	633,	"R/W",	0,	0,	1ull,	1ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	634,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	634,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_DABORT_4UCPL"              ,	2,	1,	634,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_HANDLE_FLUSH"              ,	3,	1,	634,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_31"               ,	4,	28,	634,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	635,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	636,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	637,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	637,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	637,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	638,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	638,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	638,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	639,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	639,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	639,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	640,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	640,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	640,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	640,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	641,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	641,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	641,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	641,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	642,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	642,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	642,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	642,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	643,	"RO/WRSL",	0,	0,	56ull,	56ull},
+	{"HEADER_CREDITS"              ,	12,	8,	643,	"RO/WRSL",	0,	0,	31ull,	31ull},
+	{"RESERVED_20_20"              ,	20,	1,	643,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	643,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	643,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	643,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	643,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	644,	"RO/WRSL",	0,	0,	13ull,	13ull},
+	{"HEADER_CREDITS"              ,	12,	8,	644,	"RO/WRSL",	0,	0,	31ull,	31ull},
+	{"RESERVED_20_20"              ,	20,	1,	644,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	644,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	644,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	645,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HEADER_CREDITS"              ,	12,	8,	645,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	645,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	645,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	645,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	646,	"RO/WRSL",	0,	0,	183ull,	183ull},
+	{"RESERVED_14_15"              ,	14,	2,	646,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	646,	"RO/WRSL",	0,	0,	37ull,	37ull},
+	{"RESERVED_26_31"              ,	26,	6,	646,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	647,	"RO/WRSL",	0,	0,	97ull,	97ull},
+	{"RESERVED_14_15"              ,	14,	2,	647,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	647,	"RO/WRSL",	0,	0,	37ull,	37ull},
+	{"RESERVED_26_31"              ,	26,	6,	647,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	648,	"RO/WRSL",	0,	0,	392ull,	392ull},
+	{"RESERVED_14_15"              ,	14,	2,	648,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	648,	"RO/WRSL",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	648,	"RAZ",	1,	1,	0,	0},
+	{"N_FTS"                       ,	0,	8,	649,	"R/W",	0,	0,	128ull,	128ull},
+	{"LE"                          ,	8,	9,	649,	"R/W",	0,	0,	8ull,	8ull},
+	{"DSC"                         ,	17,	1,	649,	"R/W",	0,	0,	0ull,	0ull},
+	{"CPYTS"                       ,	18,	1,	649,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTCRB"                       ,	19,	1,	649,	"R/W",	0,	0,	0ull,	0ull},
+	{"S_D_E"                       ,	20,	1,	649,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	649,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	650,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	651,	"R/W",	0,	0,	0ull,	0ull},
+	{"VENDID"                      ,	0,	16,	652,	"R/W",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	652,	"R/W",	0,	0,	147ull,	147ull},
+	{"ISAE"                        ,	0,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	653,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	653,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	653,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	653,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	653,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	653,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	653,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	653,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	653,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	653,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	653,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	653,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	653,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	653,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	653,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	653,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	653,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	653,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	654,	"R/W",	0,	0,	8ull,	8ull},
+	{"PI"                          ,	8,	8,	654,	"R/W",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	654,	"R/W",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	654,	"R/W",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	655,	"RO",	0,	0,	1ull,	1ull},
+	{"MFD"                         ,	23,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_31"               ,	0,	32,	656,	"RO",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	657,	"RO",	1,	1,	0,	0},
+	{"PBNUM"                       ,	0,	8,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBNUM"                       ,	8,	8,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUBBNUM"                     ,	16,	8,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLT"                         ,	24,	8,	658,	"RO",	0,	0,	0ull,	0ull},
+	{"IO32A"                       ,	0,	1,	659,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	659,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_BASE"                    ,	4,	4,	659,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO32B"                       ,	8,	1,	659,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_11"               ,	9,	3,	659,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_LIMI"                    ,	12,	4,	659,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_20"              ,	16,	5,	659,	"RAZ",	1,	1,	0,	0},
+	{"M66"                         ,	21,	1,	659,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	659,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	659,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	659,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	660,	"RO",	1,	1,	0,	0},
+	{"MB_ADDR"                     ,	4,	12,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_19"              ,	16,	4,	660,	"RO",	1,	1,	0,	0},
+	{"ML_ADDR"                     ,	20,	12,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64A"                      ,	0,	1,	661,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	661,	"RO",	1,	1,	0,	0},
+	{"LMEM_BASE"                   ,	4,	12,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64B"                      ,	16,	1,	661,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_17_19"              ,	17,	3,	661,	"RO",	1,	1,	0,	0},
+	{"LMEM_LIMIT"                  ,	20,	12,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_BASE"                   ,	0,	32,	662,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_LIMIT"                  ,	0,	32,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_BASE"                    ,	0,	16,	664,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_LIMIT"                   ,	16,	16,	664,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP"                          ,	0,	8,	665,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	665,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	666,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	667,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	667,	"R/W",	0,	0,	1ull,	1ull},
+	{"PERE"                        ,	16,	1,	667,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	17,	1,	667,	"R/W",	0,	0,	0ull,	0ull},
+	{"ISAE"                        ,	18,	1,	667,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGAE"                        ,	19,	1,	667,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGA16D"                      ,	20,	1,	667,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAM"                         ,	21,	1,	667,	"RO",	0,	0,	0ull,	0ull},
+	{"SBRST"                       ,	22,	1,	667,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	23,	1,	667,	"RO",	0,	0,	0ull,	0ull},
+	{"PDT"                         ,	24,	1,	667,	"RO",	0,	0,	0ull,	0ull},
+	{"SDT"                         ,	25,	1,	667,	"RO",	0,	0,	0ull,	0ull},
+	{"DTS"                         ,	26,	1,	667,	"RO",	0,	0,	0ull,	0ull},
+	{"DTSEES"                      ,	27,	1,	667,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	667,	"RO",	1,	1,	0,	0},
+	{"PMCID"                       ,	0,	8,	668,	"RO",	0,	0,	1ull,	1ull},
+	{"NCP"                         ,	8,	8,	668,	"R/W",	0,	0,	80ull,	80ull},
+	{"PMSV"                        ,	16,	3,	668,	"R/W",	0,	0,	3ull,	3ull},
+	{"PME_CLOCK"                   ,	19,	1,	668,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	668,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	669,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	669,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	669,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	669,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	669,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	669,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	669,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	669,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	669,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	669,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	669,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	669,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	670,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	670,	"R/W",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	670,	"R/W",	0,	0,	1ull,	1ull},
+	{"PVM"                         ,	24,	1,	670,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	670,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	671,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	673,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	674,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	674,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	674,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	674,	"RO",	0,	0,	4ull,	4ull},
+	{"SI"                          ,	24,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	674,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	675,	"R/W",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	675,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	675,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	675,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL1AL"                       ,	9,	3,	675,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_14"              ,	12,	3,	675,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	675,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	675,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	675,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	675,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	675,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	676,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	676,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	676,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_15_15"              ,	15,	1,	676,	"RAZ",	1,	1,	0,	0},
+	{"CE_D"                        ,	16,	1,	676,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	676,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	676,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	676,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	676,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	676,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	676,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	677,	"R/W",	1,	1,	0,	0},
+	{"MLW"                         ,	4,	6,	677,	"R/W",	0,	0,	4ull,	4ull},
+	{"ASLPMS"                      ,	10,	2,	677,	"R/W",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	677,	"R/W",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	677,	"R/W",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	677,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	677,	"RO",	0,	0,	1ull,	1ull},
+	{"LBNC"                        ,	21,	1,	677,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"ASPM"                        ,	22,	1,	677,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_23_23"              ,	23,	1,	677,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	677,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	678,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	678,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	678,	"R/W",	0,	0,	1ull,	1ull},
+	{"LD"                          ,	4,	1,	678,	"R/W",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	678,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	678,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	678,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	678,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	678,	"R/W",	0,	0,	0ull,	0ull},
+	{"LBM_INT_ENB"                 ,	10,	1,	678,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAB_INT_ENB"                 ,	11,	1,	678,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	678,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	678,	"RO",	1,	1,	0,	0},
+	{"NLW"                         ,	20,	6,	678,	"RO",	0,	0,	1ull,	4ull},
+	{"RESERVED_26_26"              ,	26,	1,	678,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	678,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	678,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLLA"                        ,	29,	1,	678,	"RO",	0,	0,	0ull,	1ull},
+	{"LBM"                         ,	30,	1,	678,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LAB"                         ,	31,	1,	678,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ABP"                         ,	0,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCP"                         ,	1,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLSP"                       ,	2,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIP"                         ,	3,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	4,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_S"                        ,	5,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_C"                        ,	6,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LV"                       ,	7,	8,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LS"                       ,	15,	2,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIP"                        ,	17,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"NCCS"                        ,	18,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS_NUM"                      ,	19,	13,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABP_EN"                      ,	0,	1,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	1,	1,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLS_EN"                     ,	2,	1,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"PD_EN"                       ,	3,	1,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCINT_EN"                    ,	4,	1,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"HPINT_EN"                    ,	5,	1,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIC"                         ,	6,	2,	680,	"R/W",	0,	0,	3ull,	3ull},
+	{"PIC"                         ,	8,	2,	680,	"R/W",	0,	0,	3ull,	3ull},
+	{"PCC"                         ,	10,	1,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIC"                        ,	11,	1,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLS_EN"                     ,	12,	1,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	680,	"RAZ",	1,	1,	0,	0},
+	{"ABP_D"                       ,	16,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PF_D"                        ,	17,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLS_C"                      ,	18,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PD_C"                        ,	19,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CCINT_D"                     ,	20,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLSS"                       ,	21,	1,	680,	"RO",	0,	0,	0ull,	0ull},
+	{"PDS"                         ,	22,	1,	680,	"RO",	0,	0,	1ull,	1ull},
+	{"EMIS"                        ,	23,	1,	680,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLS_C"                      ,	24,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	680,	"RAZ",	1,	1,	0,	0},
+	{"SECEE"                       ,	0,	1,	681,	"R/W",	0,	0,	0ull,	0ull},
+	{"SENFEE"                      ,	1,	1,	681,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEFEE"                       ,	2,	1,	681,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMEIE"                       ,	3,	1,	681,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRSSVE"                      ,	4,	1,	681,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_15"               ,	5,	11,	681,	"RAZ",	1,	1,	0,	0},
+	{"CRSSV"                       ,	16,	1,	681,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	681,	"RAZ",	1,	1,	0,	0},
+	{"PME_RID"                     ,	0,	16,	682,	"RO",	0,	0,	0ull,	0ull},
+	{"PME_STAT"                    ,	16,	1,	682,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PME_PEND"                    ,	17,	1,	682,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	682,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTRS"                        ,	0,	4,	683,	"RO",	0,	0,	15ull,	15ull},
+	{"CTDS"                        ,	4,	1,	683,	"RO",	0,	0,	1ull,	1ull},
+	{"ARI_FW"                      ,	5,	1,	683,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OPS"                    ,	6,	1,	683,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM32S"                     ,	7,	1,	683,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM64S"                     ,	8,	1,	683,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM128S"                    ,	9,	1,	683,	"RO",	0,	0,	0ull,	0ull},
+	{"NOROPRPR"                    ,	10,	1,	683,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_11_11"              ,	11,	1,	683,	"RAZ",	1,	1,	0,	0},
+	{"TPH"                         ,	12,	2,	683,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	683,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	684,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	684,	"R/W",	0,	0,	0ull,	0ull},
+	{"ARI"                         ,	5,	1,	684,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP"                     ,	6,	1,	684,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP_EB"                  ,	7,	1,	684,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_RQ"                      ,	8,	1,	684,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_CP"                      ,	9,	1,	684,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_31"              ,	10,	22,	684,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	685,	"RAZ",	1,	1,	0,	0},
+	{"SLSV"                        ,	1,	7,	685,	"RO/WRSL",	1,	1,	0,	0},
+	{"CLS"                         ,	8,	1,	685,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	685,	"RAZ",	1,	1,	0,	0},
+	{"TLS"                         ,	0,	4,	686,	"R/W",	1,	1,	0,	0},
+	{"EC"                          ,	4,	1,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"HASD"                        ,	5,	1,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDE"                         ,	6,	1,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"TM"                          ,	7,	3,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMC"                         ,	10,	1,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSOS"                        ,	11,	1,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDE"                         ,	12,	1,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	686,	"RAZ",	1,	1,	0,	0},
+	{"CDL"                         ,	16,	1,	686,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	686,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	687,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	688,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	689,	"RO",	0,	0,	1ull,	1ull},
+	{"CV"                          ,	16,	4,	689,	"RO",	0,	0,	2ull,	2ull},
+	{"NCO"                         ,	20,	12,	689,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	690,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	690,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	690,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	690,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	690,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	690,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	690,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	690,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	690,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	690,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	690,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	690,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	690,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	690,	"RAZ",	1,	1,	0,	0},
+	{"UATOMBS"                     ,	24,	1,	690,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	690,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	691,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	691,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	691,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	691,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	691,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	691,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	691,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	691,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	691,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	691,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	691,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	691,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	691,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	691,	"RAZ",	1,	1,	0,	0},
+	{"UATOMBM"                     ,	24,	1,	691,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	691,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	692,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	692,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	692,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	692,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	692,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	692,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	692,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	692,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	692,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	692,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	692,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	692,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	692,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	692,	"RO",	0,	0,	2ull,	2ull},
+	{"UATOMBS"                     ,	24,	1,	692,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	692,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	693,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	693,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	693,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	693,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	693,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	693,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	693,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	693,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	693,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	694,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	694,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	694,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	694,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	694,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	694,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	694,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	694,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	694,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	695,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	695,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	695,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	695,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	695,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	695,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	696,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	697,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	698,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	699,	"RO",	0,	0,	0ull,	0ull},
+	{"CERE"                        ,	0,	1,	700,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFERE"                       ,	1,	1,	700,	"R/W",	0,	0,	0ull,	0ull},
+	{"FERE"                        ,	2,	1,	700,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	700,	"RAZ",	1,	1,	0,	0},
+	{"ECR"                         ,	0,	1,	701,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_ECR"                   ,	1,	1,	701,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EFNFR"                       ,	2,	1,	701,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_EFNFR"                 ,	3,	1,	701,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FUF"                         ,	4,	1,	701,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFEMR"                       ,	5,	1,	701,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEMR"                        ,	6,	1,	701,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_26"               ,	7,	20,	701,	"RAZ",	1,	1,	0,	0},
+	{"AEIMN"                       ,	27,	5,	701,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECSI"                        ,	0,	16,	702,	"RO",	0,	0,	0ull,	0ull},
+	{"EFNFSI"                      ,	16,	16,	702,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	703,	"R/W",	0,	1,	4143ull,	0},
+	{"RTL"                         ,	16,	16,	703,	"R/W",	0,	1,	12429ull,	0},
+	{"OMR"                         ,	0,	32,	704,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	705,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_8_14"               ,	8,	7,	705,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	705,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	705,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	705,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	705,	"RO",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	706,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	706,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	706,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	706,	"R/W",	0,	0,	3ull,	3ull},
+	{"EASPML1"                     ,	30,	1,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	706,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	707,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	707,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	707,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	707,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	707,	"R/W",	0,	0,	15ull,	7ull},
+	{"RESERVED_22_31"              ,	22,	10,	707,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	708,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	708,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	708,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	708,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	708,	"R/W",	0,	0,	0ull,	0ull},
+	{"MFUNCN"                      ,	0,	8,	709,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_13"               ,	8,	6,	709,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	709,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	709,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	709,	"R/W",	0,	0,	0ull,	0ull},
+	{"CX_NFUNC"                    ,	29,	3,	709,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPIV"                       ,	0,	11,	710,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	710,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	710,	"R/W",	0,	0,	1ull,	1ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	711,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	711,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_DABORT_4UCPL"              ,	2,	1,	711,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_HANDLE_FLUSH"              ,	3,	1,	711,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_31"               ,	4,	28,	711,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	712,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	713,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	714,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	714,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	714,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	715,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	715,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	715,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	716,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	716,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	716,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	717,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	717,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	717,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	717,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	718,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	718,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	718,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	718,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	719,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	719,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	719,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	719,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	720,	"R/W",	0,	0,	56ull,	56ull},
+	{"HEADER_CREDITS"              ,	12,	8,	720,	"R/W",	0,	0,	31ull,	31ull},
+	{"RESERVED_20_20"              ,	20,	1,	720,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	720,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	720,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	720,	"R/W",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	720,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	721,	"R/W",	0,	0,	13ull,	13ull},
+	{"HEADER_CREDITS"              ,	12,	8,	721,	"R/W",	0,	0,	31ull,	31ull},
+	{"RESERVED_20_20"              ,	20,	1,	721,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	721,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	721,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	722,	"R/W",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	722,	"R/W",	0,	0,	96ull,	96ull},
+	{"RESERVED_20_20"              ,	20,	1,	722,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	722,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	722,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	723,	"R/W",	0,	0,	183ull,	183ull},
+	{"RESERVED_14_15"              ,	14,	2,	723,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	723,	"R/W",	0,	0,	37ull,	37ull},
+	{"RESERVED_26_31"              ,	26,	6,	723,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	724,	"R/W",	0,	0,	97ull,	97ull},
+	{"RESERVED_14_15"              ,	14,	2,	724,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	724,	"R/W",	0,	0,	37ull,	37ull},
+	{"RESERVED_26_31"              ,	26,	6,	724,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	725,	"R/W",	0,	0,	392ull,	392ull},
+	{"RESERVED_14_15"              ,	14,	2,	725,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	725,	"R/W",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	725,	"RAZ",	1,	1,	0,	0},
+	{"N_FTS"                       ,	0,	8,	726,	"R/W",	0,	0,	128ull,	128ull},
+	{"LE"                          ,	8,	9,	726,	"R/W",	0,	0,	8ull,	8ull},
+	{"DSC"                         ,	17,	1,	726,	"R/W",	0,	0,	0ull,	0ull},
+	{"CPYTS"                       ,	18,	1,	726,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTCRB"                       ,	19,	1,	726,	"R/W",	0,	0,	0ull,	0ull},
+	{"S_D_E"                       ,	20,	1,	726,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	726,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	727,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	728,	"R/W",	0,	0,	0ull,	0ull},
+	{"THRESH"                      ,	0,	4,	729,	"R/W",	0,	0,	0ull,	8ull},
+	{"FETCHSIZ"                    ,	4,	4,	729,	"R/W",	0,	0,	0ull,	7ull},
+	{"TXRD"                        ,	8,	10,	729,	"R/W",	0,	0,	0ull,	1ull},
+	{"USELDT"                      ,	18,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	729,	"RAZ",	1,	1,	0,	0},
+	{"RXST"                        ,	20,	10,	729,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_30_31"              ,	30,	2,	729,	"RAZ",	1,	1,	0,	0},
+	{"TXSLOTS"                     ,	32,	10,	729,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_42_43"              ,	42,	2,	729,	"RAZ",	1,	1,	0,	0},
+	{"RXSLOTS"                     ,	44,	10,	729,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_54_62"              ,	54,	9,	729,	"RAZ",	1,	1,	0,	0},
+	{"RDPEND"                      ,	63,	1,	729,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYNCMISSED"                 ,	0,	1,	730,	"R/W",	0,	0,	0ull,	1ull},
+	{"FSYNCEXTRA"                  ,	1,	1,	730,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXWRAP"                      ,	2,	1,	730,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXST"                        ,	3,	1,	730,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXWRAP"                      ,	4,	1,	730,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXRD"                        ,	5,	1,	730,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXEMPTY"                     ,	6,	1,	730,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXOVF"                       ,	7,	1,	730,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_8_63"               ,	8,	56,	730,	"RAZ",	1,	1,	0,	0},
+	{"FSYNCMISSED"                 ,	0,	1,	731,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FSYNCEXTRA"                  ,	1,	1,	731,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXWRAP"                      ,	2,	1,	731,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXST"                        ,	3,	1,	731,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXWRAP"                      ,	4,	1,	731,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXRD"                        ,	5,	1,	731,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXEMPTY"                     ,	6,	1,	731,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXOVF"                       ,	7,	1,	731,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	731,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	732,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	732,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	733,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	733,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	734,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	735,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	736,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	737,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	738,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	739,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	740,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	741,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	742,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	33,	742,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	742,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	1,	743,	"R/W",	0,	0,	0ull,	0ull},
+	{"USECLK1"                     ,	1,	1,	743,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBFIRST"                    ,	2,	1,	743,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	743,	"RAZ",	1,	1,	0,	0},
+	{"SAMPPT"                      ,	32,	16,	743,	"R/W",	0,	1,	0ull,	0},
+	{"DRVTIM"                      ,	48,	16,	743,	"R/W",	0,	1,	0ull,	0},
+	{"DEBUGINFO"                   ,	0,	64,	744,	"RO",	1,	1,	0,	0},
+	{"FRAM"                        ,	0,	3,	745,	"R/W",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	33,	745,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	745,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	746,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	746,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	747,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	748,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	749,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	750,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	751,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	752,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	753,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	754,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	755,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	33,	755,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	755,	"RAZ",	1,	1,	0,	0},
+	{"ENA"                         ,	0,	1,	756,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSYNCPOL"                    ,	1,	1,	756,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCLKPOL"                     ,	2,	1,	756,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITLEN"                      ,	3,	2,	756,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXTRABIT"                    ,	5,	1,	756,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUMSLOTS"                    ,	6,	10,	756,	"R/W",	0,	1,	0ull,	0},
+	{"FSYNCLOC"                    ,	16,	5,	756,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSYNCLEN"                    ,	21,	5,	756,	"R/W",	0,	0,	0ull,	2ull},
+	{"RESERVED_26_31"              ,	26,	6,	756,	"RAZ",	1,	1,	0,	0},
+	{"FSYNCSAMP"                   ,	32,	16,	756,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_62"              ,	48,	15,	756,	"RAZ",	1,	1,	0,	0},
+	{"FSYNCGOOD"                   ,	63,	1,	756,	"RO",	0,	0,	0ull,	1ull},
+	{"DEBUGINFO"                   ,	0,	64,	757,	"RO",	1,	1,	0,	0},
+	{"N"                           ,	0,	32,	758,	"R/W",	0,	1,	0ull,	0},
+	{"NUMSAMP"                     ,	32,	16,	758,	"R/W",	0,	1,	0ull,	0},
+	{"DELTASAMP"                   ,	48,	16,	758,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	759,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	759,	"R/W",	0,	0,	1ull,	1ull},
+	{"HFD"                         ,	6,	1,	759,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAUSE"                       ,	7,	2,	759,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	759,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	759,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	759,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NP"                          ,	15,	1,	759,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	759,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_11"               ,	0,	12,	760,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_THD"                    ,	12,	1,	760,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_TFD"                    ,	13,	1,	760,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_XHD"                    ,	14,	1,	760,	"RO",	0,	0,	1ull,	1ull},
+	{"THOU_XFD"                    ,	15,	1,	760,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	760,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	761,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	761,	"RO",	0,	0,	0ull,	0ull},
+	{"HFD"                         ,	6,	1,	761,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	7,	2,	761,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	761,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	761,	"RO",	0,	0,	0ull,	0ull},
+	{"ACK"                         ,	14,	1,	761,	"RO",	0,	1,	0ull,	0},
+	{"NP"                          ,	15,	1,	761,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	761,	"RAZ",	1,	1,	0,	0},
+	{"LINK_OK"                     ,	0,	1,	762,	"RO",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	1,	1,	762,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	2,	1,	762,	"RO",	0,	0,	0ull,	1ull},
+	{"SPD"                         ,	3,	2,	762,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	5,	2,	762,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	762,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD_EN"                   ,	0,	1,	763,	"R/W",	0,	0,	0ull,	1ull},
+	{"XMIT_EN"                     ,	1,	1,	763,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_ERR_EN"                   ,	2,	1,	763,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFU_EN"                   ,	3,	1,	763,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFO_EN"                   ,	4,	1,	763,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXBAD_EN"                    ,	5,	1,	763,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXERR_EN"                    ,	6,	1,	763,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	7,	1,	763,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXLOCK_EN"                   ,	8,	1,	763,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_BAD_EN"                   ,	9,	1,	763,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNC_BAD_EN"                 ,	10,	1,	763,	"R/W",	0,	0,	0ull,	1ull},
+	{"DUP"                         ,	11,	1,	763,	"R/W",	0,	0,	0ull,	1ull},
+	{"DBG_SYNC_EN"                 ,	12,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	763,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD"                      ,	0,	1,	764,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	1,	1,	764,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_ERR"                      ,	2,	1,	764,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFU"                      ,	3,	1,	764,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFO"                      ,	4,	1,	764,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXBAD"                       ,	5,	1,	764,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXERR"                       ,	6,	1,	764,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	7,	1,	764,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXLOCK"                      ,	8,	1,	764,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	9,	1,	764,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	10,	1,	764,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	11,	1,	764,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBG_SYNC"                    ,	12,	1,	764,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	764,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	16,	765,	"R/W",	0,	1,	1094ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	765,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	766,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	766,	"RAZ",	1,	1,	0,	0},
+	{"SAMP_PT"                     ,	0,	7,	767,	"R/W",	0,	1,	1ull,	0},
+	{"AN_OVRD"                     ,	7,	1,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE"                        ,	8,	1,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAC_PHY"                     ,	9,	1,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK2"                    ,	10,	1,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMXENO"                      ,	11,	1,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"SGMII"                       ,	12,	1,	767,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	767,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	768,	"RAZ",	1,	1,	0,	0},
+	{"UNI"                         ,	5,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDMSB"                      ,	6,	1,	768,	"R/W",	0,	0,	1ull,	1ull},
+	{"COLTST"                      ,	7,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	8,	1,	768,	"R/W",	0,	0,	1ull,	1ull},
+	{"RST_AN"                      ,	9,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	768,	"RAZ",	1,	1,	0,	0},
+	{"PWR_DN"                      ,	11,	1,	768,	"R/W",	0,	0,	1ull,	0ull},
+	{"AN_EN"                       ,	12,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDLSB"                      ,	13,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK1"                    ,	14,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	768,	"RAZ",	1,	1,	0,	0},
+	{"EXTND"                       ,	0,	1,	769,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	769,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LNK_ST"                      ,	2,	1,	769,	"RO",	0,	0,	0ull,	1ull},
+	{"AN_ABIL"                     ,	3,	1,	769,	"RO",	0,	0,	1ull,	1ull},
+	{"RM_FLT"                      ,	4,	1,	769,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	5,	1,	769,	"RO",	0,	0,	0ull,	0ull},
+	{"PRB_SUP"                     ,	6,	1,	769,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_7"                ,	7,	1,	769,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EXT_ST"                      ,	8,	1,	769,	"RO",	0,	0,	1ull,	1ull},
+	{"HUN_T2HD"                    ,	9,	1,	769,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T2FD"                    ,	10,	1,	769,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_HD"                      ,	11,	1,	769,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_FD"                      ,	12,	1,	769,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XHD"                     ,	13,	1,	769,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XFD"                     ,	14,	1,	769,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T4"                      ,	15,	1,	769,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	769,	"RAZ",	1,	1,	0,	0},
+	{"AN_ST"                       ,	0,	4,	770,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	4,	1,	770,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	5,	4,	770,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	9,	1,	770,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_ST"                       ,	10,	5,	770,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_BAD"                      ,	15,	1,	770,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	770,	"RAZ",	1,	1,	0,	0},
+	{"BIT_LOCK"                    ,	0,	1,	771,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	1,	1,	771,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	771,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	772,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	772,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	772,	"R/W",	0,	0,	2ull,	2ull},
+	{"DUP"                         ,	12,	1,	772,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_13"              ,	13,	1,	772,	"RAZ",	0,	1,	0ull,	0},
+	{"ACK"                         ,	14,	1,	772,	"RO",	0,	0,	0ull,	0ull},
+	{"LINK"                        ,	15,	1,	772,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	772,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	773,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	773,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	773,	"RO",	0,	0,	0ull,	2ull},
+	{"DUP"                         ,	12,	1,	773,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_14"              ,	13,	2,	773,	"RAZ",	0,	1,	0ull,	0},
+	{"LINK"                        ,	15,	1,	773,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	773,	"RAZ",	1,	1,	0,	0},
+	{"ORD_ST"                      ,	0,	4,	774,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_BAD"                      ,	4,	1,	774,	"RO",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	5,	2,	774,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	774,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTORXPL"                    ,	2,	1,	775,	"RO",	0,	0,	0ull,	0ull},
+	{"RXOVRD"                      ,	3,	1,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	775,	"RAZ",	1,	1,	0,	0},
+	{"L0SYNC"                      ,	0,	1,	776,	"RO",	0,	0,	0ull,	1ull},
+	{"L1SYNC"                      ,	1,	1,	776,	"RO",	0,	0,	0ull,	1ull},
+	{"L2SYNC"                      ,	2,	1,	776,	"RO",	0,	0,	0ull,	1ull},
+	{"L3SYNC"                      ,	3,	1,	776,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_10"               ,	4,	7,	776,	"RAZ",	1,	1,	0,	0},
+	{"PATTST"                      ,	11,	1,	776,	"RO",	0,	0,	0ull,	0ull},
+	{"ALIGND"                      ,	12,	1,	776,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_63"              ,	13,	51,	776,	"RAZ",	1,	1,	0,	0},
+	{"BIST_STATUS"                 ,	0,	1,	777,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	777,	"RAZ",	1,	1,	0,	0},
+	{"BITLCK0"                     ,	0,	1,	778,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK1"                     ,	1,	1,	778,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK2"                     ,	2,	1,	778,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK3"                     ,	3,	1,	778,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	778,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	779,	"RAZ",	1,	1,	0,	0},
+	{"SPD"                         ,	2,	4,	779,	"RO",	0,	0,	0ull,	0ull},
+	{"SPDSEL0"                     ,	6,	1,	779,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_10"               ,	7,	4,	779,	"RAZ",	1,	1,	0,	0},
+	{"LO_PWR"                      ,	11,	1,	779,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_12_12"              ,	12,	1,	779,	"RAZ",	1,	1,	0,	0},
+	{"SPDSEL1"                     ,	13,	1,	779,	"RO",	0,	0,	1ull,	1ull},
+	{"LOOPBCK1"                    ,	14,	1,	779,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	779,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	779,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	2,	780,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	780,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT_EN"                    ,	0,	1,	781,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	1,	1,	781,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXSYNBAD_EN"                 ,	2,	1,	781,	"R/W",	0,	0,	0ull,	1ull},
+	{"BITLCKLS_EN"                 ,	3,	1,	781,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNLOS_EN"                   ,	4,	1,	781,	"R/W",	0,	0,	0ull,	1ull},
+	{"ALGNLOS_EN"                  ,	5,	1,	781,	"R/W",	0,	0,	0ull,	1ull},
+	{"DBG_SYNC_EN"                 ,	6,	1,	781,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	781,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT"                       ,	0,	1,	782,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	1,	1,	782,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXSYNBAD"                    ,	2,	1,	782,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BITLCKLS"                    ,	3,	1,	782,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNLOS"                      ,	4,	1,	782,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALGNLOS"                     ,	5,	1,	782,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBG_SYNC"                    ,	6,	1,	782,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	782,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	783,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	783,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	783,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DROP_LN"                     ,	4,	2,	783,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENC_MODE"                    ,	6,	1,	783,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	783,	"RAZ",	1,	1,	0,	0},
+	{"GMXENO"                      ,	0,	1,	784,	"R/W",	0,	0,	0ull,	0ull},
+	{"XAUI"                        ,	1,	1,	784,	"RO",	1,	1,	0,	0},
+	{"RX_SWAP"                     ,	2,	1,	784,	"R/W",	0,	1,	0ull,	0},
+	{"TX_SWAP"                     ,	3,	1,	784,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	784,	"RAZ",	1,	1,	0,	0},
+	{"SYNC0ST"                     ,	0,	4,	785,	"RO",	0,	1,	0ull,	0},
+	{"SYNC1ST"                     ,	4,	4,	785,	"RO",	0,	1,	0ull,	0},
+	{"SYNC2ST"                     ,	8,	4,	785,	"RO",	0,	1,	0ull,	0},
+	{"SYNC3ST"                     ,	12,	4,	785,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	785,	"RAZ",	1,	1,	0,	0},
+	{"TENGB"                       ,	0,	1,	786,	"RO",	0,	0,	1ull,	1ull},
+	{"TENPASST"                    ,	1,	1,	786,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	786,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	787,	"RAZ",	1,	1,	0,	0},
+	{"LPABLE"                      ,	1,	1,	787,	"RO",	0,	0,	1ull,	1ull},
+	{"RCV_LNK"                     ,	2,	1,	787,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_6"                ,	3,	4,	787,	"RAZ",	1,	1,	0,	0},
+	{"FLT"                         ,	7,	1,	787,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	787,	"RAZ",	1,	1,	0,	0},
+	{"TENGB_R"                     ,	0,	1,	788,	"RO",	0,	0,	0ull,	0ull},
+	{"TENGB_X"                     ,	1,	1,	788,	"RO",	0,	0,	1ull,	1ull},
+	{"TENGB_W"                     ,	2,	1,	788,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_9"                ,	3,	7,	788,	"RAZ",	1,	1,	0,	0},
+	{"RCVFLT"                      ,	10,	1,	788,	"RC",	0,	0,	0ull,	0ull},
+	{"XMTFLT"                      ,	11,	1,	788,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_13"              ,	12,	2,	788,	"RAZ",	1,	1,	0,	0},
+	{"DEV"                         ,	14,	2,	788,	"RO",	0,	0,	2ull,	2ull},
+	{"RESERVED_16_63"              ,	16,	48,	788,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	789,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	789,	"R/W",	0,	0,	0ull,	0ull},
+	{"XOR_TXPLRT"                  ,	2,	4,	789,	"R/W",	0,	0,	0ull,	0ull},
+	{"XOR_RXPLRT"                  ,	6,	4,	789,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	789,	"RAZ",	1,	1,	0,	0},
+	{"TX_ST"                       ,	0,	3,	790,	"RO",	0,	1,	0ull,	0},
+	{"RX_ST"                       ,	3,	2,	790,	"RO",	0,	1,	0ull,	0},
+	{"ALGN_ST"                     ,	5,	3,	790,	"RO",	0,	1,	0ull,	0},
+	{"RXBAD"                       ,	8,	1,	790,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN0BAD"                     ,	9,	1,	790,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN1BAD"                     ,	10,	1,	790,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN2BAD"                     ,	11,	1,	790,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN3BAD"                     ,	12,	1,	790,	"RO",	0,	0,	0ull,	0ull},
+	{"TERM_ERR"                    ,	13,	1,	790,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	790,	"RAZ",	1,	1,	0,	0},
+	{"ADDR_V"                      ,	0,	1,	791,	"R/W",	0,	1,	0ull,	0},
+	{"END_SWP"                     ,	1,	2,	791,	"R/W",	0,	1,	0ull,	0},
+	{"CA"                          ,	3,	1,	791,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR_IDX"                    ,	4,	16,	791,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	791,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	792,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	3,	35,	792,	"R/W",	0,	0,	34359738367ull,	34359738367ull},
+	{"RESERVED_38_63"              ,	38,	26,	792,	"RAZ",	1,	1,	0,	0},
+	{"BAR2_CAX"                    ,	0,	1,	793,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	1,	2,	793,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	3,	1,	793,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR1_SIZ"                    ,	4,	3,	793,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_63"               ,	7,	57,	793,	"RAZ",	1,	1,	0,	0},
+	{"SOT"                         ,	0,	1,	794,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR0"                      ,	1,	1,	794,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR1"                      ,	2,	1,	794,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA3"                     ,	3,	1,	794,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA2"                     ,	4,	1,	794,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA1"                     ,	5,	1,	794,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA0"                     ,	6,	1,	794,	"RO",	0,	0,	0ull,	0ull},
+	{"RETRY"                       ,	7,	1,	794,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	794,	"RAZ",	1,	1,	0,	0},
+	{"PPF"                         ,	0,	1,	795,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TC0"                     ,	1,	1,	795,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TCF1"                    ,	2,	1,	795,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TNF"                     ,	3,	1,	795,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF0"                    ,	4,	1,	795,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF1"                    ,	5,	1,	795,	"RO",	0,	0,	0ull,	0ull},
+	{"PEAI_P2E"                    ,	6,	1,	795,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_P"                       ,	7,	1,	795,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_N"                       ,	8,	1,	795,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_CPL"                     ,	9,	1,	795,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	795,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	32,	796,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	796,	"R/W",	0,	1,	0ull,	0},
+	{"ADDR"                        ,	0,	32,	797,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	797,	"R/W",	0,	1,	0ull,	0},
+	{"TAG"                         ,	0,	32,	798,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	798,	"RAZ",	1,	1,	0,	0},
+	{"INV_LCRC"                    ,	0,	1,	799,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_ECRC"                    ,	1,	1,	799,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAST_LM"                     ,	2,	1,	799,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_CTLP"                     ,	3,	1,	799,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_ENB"                     ,	4,	1,	799,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLY_ONE"                     ,	5,	1,	799,	"R/W",	0,	0,	0ull,	0ull},
+	{"NF_ECRC"                     ,	6,	1,	799,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_8"                ,	7,	2,	799,	"R/W",	0,	0,	0ull,	0ull},
+	{"OB_P_CMD"                    ,	9,	1,	799,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XPME"                     ,	10,	1,	799,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XTOFF"                    ,	11,	1,	799,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	799,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CFG_RTRY"                    ,	16,	16,	799,	"R/W",	0,	0,	0ull,	32ull},
+	{"RESERVED_32_33"              ,	32,	2,	799,	"RAZ",	1,	1,	0,	0},
+	{"PBUS"                        ,	34,	8,	799,	"RO",	1,	1,	0,	0},
+	{"DNUM"                        ,	42,	5,	799,	"RO",	1,	1,	0,	0},
+	{"AUTO_SD"                     ,	47,	1,	799,	"RO",	1,	1,	0,	0},
+	{"RESERVED_48_63"              ,	48,	16,	799,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	800,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	800,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	801,	"RAZ",	1,	1,	0,	0},
+	{"AUX_EN"                      ,	0,	1,	802,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_EN"                       ,	1,	1,	802,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_STAT"                     ,	2,	1,	802,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_DST"                      ,	3,	1,	802,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	802,	"RO",	1,	1,	0,	0},
+	{"NUM"                         ,	0,	6,	803,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	803,	"RAZ",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	804,	"R/W",	0,	0,	0ull,	1ull},
+	{"SE"                          ,	1,	1,	804,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEI"                        ,	2,	1,	804,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEM"                        ,	3,	1,	804,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B1"                       ,	4,	1,	804,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B2"                       ,	5,	1,	804,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_BX"                       ,	6,	1,	804,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B1"                       ,	7,	1,	804,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B2"                       ,	8,	1,	804,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_BX"                       ,	9,	1,	804,	"R/W",	0,	0,	0ull,	1ull},
+	{"EXC"                         ,	10,	1,	804,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDLK"                        ,	11,	1,	804,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_ER"                      ,	12,	1,	804,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_DR"                      ,	13,	1,	804,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_14_63"              ,	14,	50,	804,	"RAZ",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	805,	"R/W",	0,	0,	0ull,	1ull},
+	{"SE"                          ,	1,	1,	805,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEI"                        ,	2,	1,	805,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEM"                        ,	3,	1,	805,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B1"                       ,	4,	1,	805,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B2"                       ,	5,	1,	805,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_BX"                       ,	6,	1,	805,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B1"                       ,	7,	1,	805,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B2"                       ,	8,	1,	805,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_BX"                       ,	9,	1,	805,	"R/W",	0,	0,	0ull,	1ull},
+	{"EXC"                         ,	10,	1,	805,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDLK"                        ,	11,	1,	805,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_ER"                      ,	12,	1,	805,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_DR"                      ,	13,	1,	805,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_14_63"              ,	14,	50,	805,	"RAZ",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	806,	"RO",	0,	0,	0ull,	0ull},
+	{"SE"                          ,	1,	1,	806,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PMEI"                        ,	2,	1,	806,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEM"                        ,	3,	1,	806,	"RO",	0,	0,	0ull,	0ull},
+	{"UP_B1"                       ,	4,	1,	806,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UP_B2"                       ,	5,	1,	806,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UP_BX"                       ,	6,	1,	806,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_B1"                       ,	7,	1,	806,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_B2"                       ,	8,	1,	806,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_BX"                       ,	9,	1,	806,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EXC"                         ,	10,	1,	806,	"RO",	0,	0,	0ull,	0ull},
+	{"RDLK"                        ,	11,	1,	806,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS_ER"                      ,	12,	1,	806,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS_DR"                      ,	13,	1,	806,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	806,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_13"               ,	0,	14,	807,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	14,	50,	807,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_25"               ,	0,	26,	808,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	26,	38,	808,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_40"               ,	0,	41,	809,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	41,	23,	809,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLI_P"                       ,	0,	8,	810,	"R/W",	0,	0,	128ull,	128ull},
+	{"SLI_NP"                      ,	8,	8,	810,	"R/W",	0,	0,	16ull,	16ull},
+	{"SLI_CPL"                     ,	16,	8,	810,	"R/W",	0,	0,	128ull,	128ull},
+	{"RESERVED_24_47"              ,	24,	24,	810,	"RAZ",	1,	1,	0,	0},
+	{"PEAI_PPF"                    ,	48,	8,	810,	"R/W",	0,	0,	128ull,	128ull},
+	{"RESERVED_56_63"              ,	56,	8,	810,	"RAZ",	1,	1,	0,	0},
+	{"SKIP1"                       ,	0,	7,	811,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	811,	"RAZ",	1,	1,	0,	0},
+	{"SKIP2"                       ,	8,	7,	811,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	811,	"RAZ",	1,	1,	0,	0},
+	{"SKIP3"                       ,	16,	7,	811,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_31"              ,	23,	9,	811,	"RAZ",	1,	1,	0,	0},
+	{"BIT0"                        ,	32,	6,	811,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_39"              ,	38,	2,	811,	"RAZ",	1,	1,	0,	0},
+	{"BIT1"                        ,	40,	6,	811,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_46_55"              ,	46,	10,	811,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	56,	1,	811,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_57_63"              ,	57,	7,	811,	"RAZ",	1,	1,	0,	0},
+	{"LOWATER"                     ,	0,	5,	812,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_5_7"                ,	5,	3,	812,	"RAZ",	0,	1,	0ull,	0},
+	{"HIWATER"                     ,	8,	5,	812,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_13_62"              ,	13,	50,	812,	"RAZ",	0,	1,	0ull,	0},
+	{"BCKPRS"                      ,	63,	1,	812,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	20,	813,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	813,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	814,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_15"               ,	7,	9,	814,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	16,	9,	814,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_25_31"              ,	25,	7,	814,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	32,	8,	814,	"R/W",	0,	1,	0ull,	0},
+	{"UPPER_TAG"                   ,	40,	16,	814,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	814,	"RAZ",	1,	1,	0,	0},
+	{"POS0"                        ,	0,	7,	815,	"R/W",	0,	1,	0ull,	0},
+	{"POS0_VAL"                    ,	7,	1,	815,	"R/W",	0,	1,	0ull,	0},
+	{"POS1"                        ,	8,	7,	815,	"R/W",	0,	1,	0ull,	0},
+	{"POS1_VAL"                    ,	15,	1,	815,	"R/W",	0,	1,	0ull,	0},
+	{"POS2"                        ,	16,	7,	815,	"R/W",	0,	1,	0ull,	0},
+	{"POS2_VAL"                    ,	23,	1,	815,	"R/W",	0,	1,	0ull,	0},
+	{"POS3"                        ,	24,	7,	815,	"R/W",	0,	1,	0ull,	0},
+	{"POS3_VAL"                    ,	31,	1,	815,	"R/W",	0,	1,	0ull,	0},
+	{"POS4"                        ,	32,	7,	815,	"R/W",	0,	1,	0ull,	0},
+	{"POS4_VAL"                    ,	39,	1,	815,	"R/W",	0,	1,	0ull,	0},
+	{"POS5"                        ,	40,	7,	815,	"R/W",	0,	1,	0ull,	0},
+	{"POS5_VAL"                    ,	47,	1,	815,	"R/W",	0,	1,	0ull,	0},
+	{"POS6"                        ,	48,	7,	815,	"R/W",	0,	1,	0ull,	0},
+	{"POS6_VAL"                    ,	55,	1,	815,	"R/W",	0,	1,	0ull,	0},
+	{"POS7"                        ,	56,	7,	815,	"R/W",	0,	1,	0ull,	0},
+	{"POS7_VAL"                    ,	63,	1,	815,	"R/W",	0,	1,	0ull,	0},
+	{"QOS"                         ,	0,	3,	816,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_7"                ,	3,	5,	816,	"RAZ",	1,	1,	0,	0},
+	{"TT"                          ,	8,	2,	816,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	816,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	16,	4,	816,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	816,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	32,	8,	816,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_59"              ,	40,	20,	816,	"RAZ",	1,	1,	0,	0},
+	{"QOS_EN"                      ,	60,	1,	816,	"R/W",	0,	1,	0ull,	0},
+	{"TT_EN"                       ,	61,	1,	816,	"R/W",	0,	1,	0ull,	0},
+	{"GRP_EN"                      ,	62,	1,	816,	"R/W",	0,	1,	0ull,	0},
+	{"TAG_EN"                      ,	63,	1,	816,	"R/W",	0,	1,	0ull,	0},
+	{"CLKEN"                       ,	0,	1,	817,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	817,	"RAZ",	0,	1,	0ull,	0},
+	{"DPRT"                        ,	0,	16,	818,	"R/W",	0,	0,	0ull,	0ull},
+	{"UDP"                         ,	16,	1,	818,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP"                         ,	17,	1,	818,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	818,	"RAZ",	1,	1,	0,	0},
+	{"MAP0"                        ,	0,	4,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP0"                        ,	0,	4,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINLEN"                      ,	0,	16,	821,	"R/W",	0,	0,	64ull,	64ull},
+	{"MAXLEN"                      ,	16,	16,	821,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_32_63"              ,	32,	32,	821,	"RAZ",	1,	1,	0,	0},
+	{"NIP_SHF"                     ,	0,	3,	822,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	822,	"RAZ",	1,	1,	0,	0},
+	{"RAW_SHF"                     ,	8,	3,	822,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	822,	"RAZ",	1,	1,	0,	0},
+	{"MAX_L2"                      ,	16,	1,	822,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_UDP"                     ,	17,	1,	822,	"R/W",	0,	0,	1ull,	1ull},
+	{"TAG_SYN"                     ,	18,	1,	822,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	822,	"RAZ",	1,	1,	0,	0},
+	{"IP_CHK"                      ,	0,	1,	823,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_MAL"                      ,	1,	1,	823,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_HOP"                      ,	2,	1,	823,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP4_OPTS"                    ,	3,	1,	823,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP6_EEXT"                    ,	4,	2,	823,	"R/W",	0,	0,	1ull,	3ull},
+	{"RESERVED_6_7"                ,	6,	2,	823,	"RAZ",	1,	1,	0,	0},
+	{"L4_MAL"                      ,	8,	1,	823,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_PRT"                      ,	9,	1,	823,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_CHK"                      ,	10,	1,	823,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_LEN"                      ,	11,	1,	823,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCP_FLAG"                    ,	12,	1,	823,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2_MAL"                      ,	13,	1,	823,	"R/W",	0,	0,	1ull,	1ull},
+	{"VS_QOS"                      ,	14,	1,	823,	"R/W",	0,	0,	0ull,	0ull},
+	{"VS_WQE"                      ,	15,	1,	823,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNRS"                       ,	16,	1,	823,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	823,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RING_EN"                     ,	20,	1,	823,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_21_23"              ,	21,	3,	823,	"RAZ",	1,	1,	0,	0},
+	{"DSA_GRP_SID"                 ,	24,	1,	823,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_SCMD"                ,	25,	1,	823,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_TVID"                ,	26,	1,	823,	"R/W",	0,	0,	0ull,	0ull},
+	{"IHMSK_DIS"                   ,	27,	1,	823,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	823,	"RAZ",	1,	1,	0,	0},
+	{"PRI"                         ,	0,	6,	824,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	824,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	8,	3,	824,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	824,	"RAZ",	1,	1,	0,	0},
+	{"UP_QOS"                      ,	12,	1,	824,	"RAZ",	0,	1,	0ull,	0},
+	{"RESERVED_13_63"              ,	13,	51,	824,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	825,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	825,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	825,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	825,	"R/W",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	825,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	825,	"R/W",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	825,	"R/W",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	825,	"R/W",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	825,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	825,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	825,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	825,	"R/W",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	825,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	825,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	826,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	3,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	827,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	828,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	2,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_EN"                      ,	10,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"HIGIG_EN"                    ,	11,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRC_EN"                      ,	12,	1,	828,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	828,	"RAZ",	1,	1,	0,	0},
+	{"QOS_VLAN"                    ,	16,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_DIFF"                    ,	17,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VOD"                     ,	18,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VSEL"                    ,	19,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_WAT"                     ,	20,	4,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS"                         ,	24,	3,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_QOS"                      ,	27,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT"                     ,	28,	4,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"INST_HDR"                    ,	32,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"DYN_RS"                      ,	33,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_INC"                     ,	34,	2,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWDRP"                      ,	36,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	828,	"RAZ",	1,	1,	0,	0},
+	{"QOS_WAT_47"                  ,	40,	4,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT_47"                  ,	44,	4,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR_EN"                   ,	48,	1,	828,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR_EN"                   ,	49,	1,	828,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR_EN"                   ,	50,	1,	828,	"R/W",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	51,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	52,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_63"              ,	53,	11,	828,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	829,	"RAZ",	1,	1,	0,	0},
+	{"BSEL_EN"                     ,	32,	1,	829,	"R/W",	0,	0,	0ull,	0ull},
+	{"BSEL_NUM"                    ,	33,	2,	829,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_35"              ,	35,	1,	829,	"RAZ",	1,	1,	0,	0},
+	{"ALT_SKP_EN"                  ,	36,	1,	829,	"R/W",	0,	1,	0ull,	0},
+	{"ALT_SKP_SEL"                 ,	37,	2,	829,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_39_63"              ,	39,	25,	829,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	0,	4,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"NON_TAG_TYPE"                ,	4,	2,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_TAG_TYPE"                ,	6,	2,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_TAG_TYPE"                ,	8,	2,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP4_TAG_TYPE"               ,	10,	2,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP6_TAG_TYPE"               ,	12,	2,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SRC_FLAG"                ,	14,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SRC_FLAG"                ,	15,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DST_FLAG"                ,	16,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DST_FLAG"                ,	17,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_PCTL_FLAG"               ,	18,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_NXTH_FLAG"               ,	19,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SPRT_FLAG"               ,	20,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SPRT_FLAG"               ,	21,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DPRT_FLAG"               ,	22,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DPRT_FLAG"               ,	23,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_PRT_FLAG"                ,	24,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VLAN"                    ,	25,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VS"                      ,	26,	2,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_MODE"                    ,	28,	2,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG_MSKIP"                ,	30,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG"                      ,	31,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGMASK"                  ,	32,	4,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGBASE"                  ,	36,	4,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	830,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	831,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	831,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	832,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	832,	"RAZ",	1,	1,	0,	0},
+	{"QOS1"                        ,	4,	3,	832,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	832,	"RAZ",	1,	1,	0,	0},
+	{"MATCH_VALUE"                 ,	0,	16,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"MATCH_TYPE"                  ,	16,	3,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	833,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	20,	3,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	833,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	24,	4,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	833,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	32,	16,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	833,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	0,	56,	834,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	834,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	0,	1,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	835,	"RAZ",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	836,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	836,	"R/W",	0,	1,	0ull,	0},
+	{"MCAST"                       ,	0,	32,	837,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	837,	"R/W",	0,	1,	0ull,	0},
+	{"MCAST"                       ,	0,	32,	838,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	838,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	839,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	839,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	840,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	840,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	841,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	841,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	842,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	842,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	843,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	843,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	844,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	844,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	845,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	845,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	846,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	846,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	847,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	847,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	848,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	848,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	849,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	849,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	850,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	850,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	851,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	851,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	852,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	853,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	853,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	854,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	854,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	854,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	855,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	855,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	855,	"RO",	1,	1,	0,	0},
+	{"TYPE0"                       ,	0,	16,	856,	"R/W",	0,	0,	33024ull,	33024ull},
+	{"TYPE1"                       ,	16,	16,	856,	"R/W",	0,	0,	33024ull,	33024ull},
+	{"TYPE2"                       ,	32,	16,	856,	"R/W",	0,	0,	33024ull,	33024ull},
+	{"TYPE3"                       ,	48,	16,	856,	"R/W",	0,	0,	33024ull,	33024ull},
+	{"COUNT"                       ,	0,	32,	857,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	857,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	858,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	858,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	859,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	859,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	859,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	859,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	860,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	860,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	860,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	860,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	860,	"RO",	1,	0,	0,	0ull},
+	{"PTRS2"                       ,	0,	17,	861,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	861,	"RAZ",	1,	1,	0,	0},
+	{"PTRS1"                       ,	32,	17,	861,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	861,	"RAZ",	1,	1,	0,	0},
+	{"MOD"                         ,	0,	3,	862,	"RO",	1,	0,	0,	0ull},
+	{"CNT"                         ,	3,	13,	862,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	16,	1,	862,	"RO",	1,	0,	0,	0ull},
+	{"LEN"                         ,	17,	1,	862,	"RO",	1,	0,	0,	0ull},
+	{"SOP"                         ,	18,	1,	862,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	19,	3,	862,	"RO",	1,	0,	0,	0ull},
+	{"MAJ"                         ,	22,	1,	862,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	862,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	863,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	863,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	863,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	863,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	864,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	864,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	864,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	864,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	864,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	865,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	866,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	866,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	866,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	866,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	866,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	867,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	3,	868,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	3,	2,	868,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	5,	1,	868,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	6,	1,	868,	"RO",	1,	0,	0,	0ull},
+	{"CHK_ONCE"                    ,	7,	1,	868,	"RO",	1,	0,	0,	0ull},
+	{"INIT_DWRITE"                 ,	8,	1,	868,	"RO",	1,	0,	0,	0ull},
+	{"DREAD_SOP"                   ,	9,	1,	868,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	10,	2,	868,	"RO",	1,	0,	0,	0ull},
+	{"CMND_OFF"                    ,	12,	6,	868,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	18,	16,	868,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	34,	6,	868,	"RO",	1,	0,	0,	0ull},
+	{"CURR_OFF"                    ,	40,	16,	868,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	56,	8,	868,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	0,	8,	869,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	8,	40,	869,	"RO",	1,	0,	0,	0ull},
+	{"NXT_INFLT"                   ,	48,	6,	869,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR_3"                     ,	54,	1,	869,	"RO",	1,	0,	0,	0ull},
+	{"PTP"                         ,	55,	1,	869,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	869,	"RAZ",	1,	1,	0,	0},
+	{"QID_BASE"                    ,	0,	8,	870,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	8,	4,	870,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFMAX"                  ,	12,	4,	870,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	16,	5,	870,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	21,	3,	870,	"RO",	1,	0,	0,	0ull},
+	{"STATC"                       ,	24,	1,	870,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	25,	1,	870,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTED"                   ,	26,	1,	870,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	27,	1,	870,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	870,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFTHS"                  ,	29,	4,	870,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFRES"                  ,	33,	4,	870,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	870,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	6,	871,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	6,	6,	871,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	12,	33,	871,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	45,	13,	871,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	58,	1,	871,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	59,	5,	871,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	3,	872,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	3,	1,	872,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	4,	1,	872,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	5,	1,	872,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	6,	1,	872,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	872,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	8,	20,	872,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	872,	"RO",	1,	0,	0,	0ull},
+	{"QID_IDX"                     ,	29,	4,	872,	"RO",	1,	1,	0,	0},
+	{"RESERVED_33_33"              ,	33,	1,	872,	"RAZ",	1,	1,	0,	0},
+	{"QID_QQOS"                    ,	34,	8,	872,	"RO",	1,	1,	0,	0},
+	{"RESERVED_42_63"              ,	42,	22,	872,	"RAZ",	1,	1,	0,	0},
+	{"PTRS3"                       ,	0,	17,	873,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	873,	"RAZ",	1,	1,	0,	0},
+	{"PTRS0"                       ,	32,	17,	873,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	873,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	874,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	874,	"R/W",	1,	0,	0,	0ull},
+	{"BP_PORT"                     ,	10,	6,	874,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_52"              ,	16,	37,	874,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	874,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	61,	1,	874,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	874,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	875,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	875,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_10_52"              ,	10,	43,	875,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	875,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	875,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	876,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	876,	"RAZ",	1,	1,	0,	0},
+	{"RATE_PKT"                    ,	8,	24,	876,	"R/W",	1,	0,	0,	0ull},
+	{"RATE_WORD"                   ,	32,	19,	876,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	876,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	877,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	877,	"RAZ",	1,	1,	0,	0},
+	{"RATE_LIM"                    ,	8,	24,	877,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	877,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE"                       ,	0,	7,	878,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	7,	6,	878,	"WR0",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	13,	3,	878,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	16,	1,	878,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	17,	36,	878,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	878,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	878,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	878,	"R/W",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	878,	"R/W",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	7,	879,	"R/W",	1,	0,	0,	0ull},
+	{"PID"                         ,	7,	6,	879,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	879,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	879,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	879,	"RAZ",	1,	1,	0,	0},
+	{"DAT_PTR"                     ,	0,	4,	880,	"RO",	1,	0,	0,	0ull},
+	{"DAT_DAT"                     ,	4,	2,	880,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CTL"                     ,	6,	2,	880,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QSB"                     ,	8,	3,	880,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QCB"                     ,	11,	2,	880,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	13,	2,	880,	"RO",	1,	0,	0,	0ull},
+	{"PRT_PSB"                     ,	15,	8,	880,	"RO",	1,	0,	0,	0ull},
+	{"PRT_NXT"                     ,	23,	1,	880,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CHK"                     ,	24,	3,	880,	"RO",	1,	0,	0,	0ull},
+	{"OUT_WIF"                     ,	27,	1,	880,	"RO",	1,	0,	0,	0ull},
+	{"OUT_STA"                     ,	28,	1,	880,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CTL"                     ,	29,	3,	880,	"RO",	1,	0,	0,	0ull},
+	{"OUT_DAT"                     ,	32,	1,	880,	"RO",	1,	0,	0,	0ull},
+	{"IOB"                         ,	33,	1,	880,	"RO",	1,	0,	0,	0ull},
+	{"CSR"                         ,	34,	1,	880,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	880,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	13,	881,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	881,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	881,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	881,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	64,	882,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	883,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	884,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	885,	"RO",	0,	0,	0ull,	0ull},
+	{"ENGINE0"                     ,	0,	4,	886,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE1"                     ,	4,	4,	886,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE2"                     ,	8,	4,	886,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE3"                     ,	12,	4,	886,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE4"                     ,	16,	4,	886,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE5"                     ,	20,	4,	886,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE6"                     ,	24,	4,	886,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE7"                     ,	28,	4,	886,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE8"                     ,	32,	4,	886,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE9"                     ,	36,	4,	886,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE10"                    ,	40,	4,	886,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE11"                    ,	44,	4,	886,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE12"                    ,	48,	4,	886,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE13"                    ,	52,	4,	886,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_56_63"              ,	56,	8,	886,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	14,	887,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	887,	"RAZ",	1,	1,	0,	0},
+	{"PARITY"                      ,	0,	1,	888,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	888,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	888,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	888,	"RAZ",	1,	1,	0,	0},
+	{"ENA_PKO"                     ,	0,	1,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	889,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_6"                ,	4,	3,	889,	"RAZ",	1,	1,	0,	0},
+	{"DIS_PERF2"                   ,	7,	1,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIS_PERF3"                   ,	8,	1,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	889,	"RAZ",	1,	1,	0,	0},
+	{"MODE0"                       ,	0,	3,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE1"                       ,	3,	3,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	890,	"RAZ",	1,	1,	0,	0},
+	{"PARITY"                      ,	0,	1,	891,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	891,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	891,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	891,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	16,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	892,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	893,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	893,	"RAZ",	1,	1,	0,	0},
+	{"PREEMPTER"                   ,	0,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"PREEMPTEE"                   ,	1,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	894,	"RAZ",	1,	1,	0,	0},
+	{"QID7"                        ,	0,	1,	895,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDX3"                        ,	1,	1,	895,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	895,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	896,	"RAZ",	1,	1,	0,	0},
+	{"WQE_WORD"                    ,	0,	4,	897,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_4_63"               ,	4,	60,	897,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	1,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND"                        ,	1,	1,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"FIDX"                        ,	2,	1,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	3,	1,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT"                         ,	4,	4,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR"                         ,	8,	3,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	11,	1,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	898,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	16,	4,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	898,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	32,	899,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	899,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	900,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	900,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE_IE"                      ,	2,	1,	900,	"R/W",	0,	1,	0ull,	0},
+	{"DBE_IE"                      ,	3,	1,	900,	"R/W",	0,	1,	0ull,	0},
+	{"SYN"                         ,	4,	5,	900,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_11"               ,	9,	3,	900,	"RAZ",	1,	1,	0,	0},
+	{"RPE"                         ,	12,	1,	900,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE_IE"                      ,	13,	1,	900,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	900,	"RAZ",	1,	1,	0,	0},
+	{"IOP"                         ,	16,	13,	900,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	900,	"RAZ",	1,	1,	0,	0},
+	{"IOP_IE"                      ,	32,	13,	900,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_63"              ,	45,	19,	900,	"RAZ",	1,	1,	0,	0},
+	{"NBR_THR"                     ,	0,	5,	901,	"R/W",	0,	0,	2ull,	2ull},
+	{"PFR_DIS"                     ,	5,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	901,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	902,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	902,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	903,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	903,	"RAZ",	1,	1,	0,	0},
+	{"IQ_INT"                      ,	0,	8,	904,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	904,	"RAZ",	1,	1,	0,	0},
+	{"INT_EN"                      ,	0,	8,	905,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	905,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	32,	906,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	906,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	10,	907,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	907,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	908,	"R/W",	0,	0,	0ull,	4ull},
+	{"RESERVED_10_63"              ,	10,	54,	908,	"RAZ",	1,	1,	0,	0},
+	{"RST_MSK"                     ,	0,	8,	909,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	909,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	16,	910,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"QOS0_PRI"                    ,	16,	4,	910,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1_PRI"                    ,	20,	4,	910,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2_PRI"                    ,	24,	4,	910,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3_PRI"                    ,	28,	4,	910,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4_PRI"                    ,	32,	4,	910,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5_PRI"                    ,	36,	4,	910,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6_PRI"                    ,	40,	4,	910,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7_PRI"                    ,	44,	4,	910,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	910,	"RAZ",	1,	1,	0,	0},
+	{"RND"                         ,	0,	8,	911,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P1"                      ,	8,	8,	911,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P2"                      ,	16,	8,	911,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P3"                      ,	24,	8,	911,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	911,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	9,	912,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	912,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	12,	9,	912,	"R/W",	0,	1,	511ull,	0},
+	{"RESERVED_21_23"              ,	21,	3,	912,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	24,	10,	912,	"RO",	0,	1,	503ull,	0},
+	{"RESERVED_34_35"              ,	34,	2,	912,	"RAZ",	1,	1,	0,	0},
+	{"BUF_CNT"                     ,	36,	10,	912,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	912,	"RAZ",	1,	1,	0,	0},
+	{"DES_CNT"                     ,	48,	10,	912,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	912,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	32,	913,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	913,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	914,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	914,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	915,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	915,	"RAZ",	1,	1,	0,	0},
+	{"WQ_INT"                      ,	0,	16,	916,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_DIS"                      ,	16,	16,	916,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	916,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	10,	917,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_11"              ,	10,	2,	917,	"RAZ",	1,	1,	0,	0},
+	{"DS_CNT"                      ,	12,	10,	917,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_22_23"              ,	22,	2,	917,	"RAZ",	1,	1,	0,	0},
+	{"TC_CNT"                      ,	24,	4,	917,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	917,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	918,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	918,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	918,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	918,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	918,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	9,	919,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	919,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	12,	9,	919,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_23"              ,	21,	3,	919,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	24,	4,	919,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	28,	1,	919,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	919,	"RAZ",	1,	1,	0,	0},
+	{"WS_PC"                       ,	0,	32,	920,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	920,	"RAZ",	1,	1,	0,	0},
+	{"IWORD"                       ,	0,	64,	921,	"RO",	1,	1,	0,	0},
+	{"P_DAT"                       ,	0,	64,	922,	"RO",	1,	1,	0,	0},
+	{"Q_DAT"                       ,	0,	64,	923,	"RO",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	2,	924,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	2,	2,	924,	"RO",	1,	0,	0,	0ull},
+	{"NCB_OUB"                     ,	4,	1,	924,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	5,	1,	924,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	924,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	925,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	33,	13,	925,	"R/W",	0,	1,	0ull,	0},
+	{"POOL"                        ,	46,	3,	925,	"R/W",	0,	1,	0ull,	0},
+	{"DWB"                         ,	49,	9,	925,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	925,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	926,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STORE_LE"                    ,	1,	1,	926,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_READ"                    ,	2,	4,	926,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_6_63"               ,	6,	58,	926,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	0,	5,	927,	"RO",	1,	1,	0,	0},
+	{"COMMIT"                      ,	5,	1,	927,	"RO",	1,	1,	0,	0},
+	{"OWORDPV"                     ,	6,	1,	927,	"RO",	1,	1,	0,	0},
+	{"OWORDQV"                     ,	7,	1,	927,	"RO",	1,	1,	0,	0},
+	{"IWIDX"                       ,	8,	6,	927,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	927,	"RO",	1,	1,	0,	0},
+	{"IRIDX"                       ,	16,	6,	927,	"RO",	1,	1,	0,	0},
+	{"RESERVED_22_31"              ,	22,	10,	927,	"RO",	1,	1,	0,	0},
+	{"LOOP"                        ,	32,	25,	927,	"RO",	1,	1,	0,	0},
+	{"RESERVED_57_63"              ,	57,	7,	927,	"RO",	1,	1,	0,	0},
+	{"CWORD"                       ,	0,	64,	928,	"RO",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	929,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	929,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	929,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	930,	"RO",	1,	1,	0,	0},
+	{"SOD"                         ,	8,	1,	930,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	9,	1,	930,	"RO",	1,	1,	0,	0},
+	{"WC"                          ,	10,	1,	930,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	11,	1,	930,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	12,	1,	930,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	930,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	15,	931,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	931,	"RAZ",	1,	1,	0,	0},
+	{"OWORDP"                      ,	0,	64,	932,	"RO",	1,	1,	0,	0},
+	{"OWORDQ"                      ,	0,	64,	933,	"RO",	1,	1,	0,	0},
+	{"RWORD"                       ,	0,	64,	934,	"RO",	1,	1,	0,	0},
+	{"N0CREDS"                     ,	0,	4,	935,	"RO",	0,	0,	8ull,	0ull},
+	{"N1CREDS"                     ,	4,	4,	935,	"RO",	0,	0,	8ull,	0ull},
+	{"POWCREDS"                    ,	8,	2,	935,	"RO",	0,	0,	2ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	935,	"RAZ",	1,	1,	0,	0},
+	{"FPACREDS"                    ,	12,	2,	935,	"RO",	0,	0,	1ull,	0ull},
+	{"WCCREDS"                     ,	14,	2,	935,	"RO",	0,	0,	0ull,	0ull},
+	{"NIWIDX0"                     ,	16,	4,	935,	"RO",	1,	1,	0,	0},
+	{"NIRIDX0"                     ,	20,	4,	935,	"RO",	1,	1,	0,	0},
+	{"NIWIDX1"                     ,	24,	4,	935,	"RO",	1,	1,	0,	0},
+	{"NIRIDX1"                     ,	28,	4,	935,	"RO",	1,	1,	0,	0},
+	{"NIRVAL6"                     ,	32,	5,	935,	"RO",	1,	1,	0,	0},
+	{"NIRARB6"                     ,	37,	1,	935,	"RO",	1,	1,	0,	0},
+	{"NIRQUE6"                     ,	38,	2,	935,	"RO",	1,	1,	0,	0},
+	{"NIROPC6"                     ,	40,	3,	935,	"RO",	1,	1,	0,	0},
+	{"NIRVAL7"                     ,	43,	5,	935,	"RO",	1,	1,	0,	0},
+	{"NIRQUE7"                     ,	48,	2,	935,	"RO",	1,	1,	0,	0},
+	{"NIROPC7"                     ,	50,	3,	935,	"RO",	1,	1,	0,	0},
+	{"RESERVED_53_63"              ,	53,	11,	935,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	936,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	936,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	56,	8,	936,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	15,	937,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	937,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	938,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	938,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	938,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	939,	"RO",	1,	1,	0,	0},
+	{"MUL"                         ,	8,	8,	939,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	16,	1,	939,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	17,	1,	939,	"RO",	1,	1,	0,	0},
+	{"INI"                         ,	18,	1,	939,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	19,	1,	939,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_63"              ,	20,	44,	939,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	940,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	940,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	941,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	941,	"RAZ",	1,	1,	0,	0},
+	{"COEFFS"                      ,	0,	8,	942,	"R/W",	0,	0,	29ull,	29ull},
+	{"RESERVED_8_63"               ,	8,	56,	942,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	0,	16,	943,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	16,	16,	943,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	943,	"RAZ",	1,	1,	0,	0},
+	{"MEM"                         ,	0,	1,	944,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	944,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	944,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	945,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	945,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	945,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	945,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXP_ENT"                     ,	4,	1,	945,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENT_SEL"                     ,	5,	4,	945,	"R/W",	0,	0,	0ull,	0ull},
+	{"EER_VAL"                     ,	9,	1,	945,	"RO",	0,	0,	0ull,	0ull},
+	{"EER_LCK"                     ,	10,	1,	945,	"RO",	0,	0,	0ull,	0ull},
+	{"DIS_MAK"                     ,	11,	1,	945,	"R/W1",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	945,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	946,	"RO",	1,	1,	0,	0},
+	{"KEY"                         ,	0,	64,	947,	"WO",	0,	0,	0ull,	0ull},
+	{"DAT"                         ,	0,	64,	948,	"RO",	1,	1,	0,	0},
+	{"NCB_CMD"                     ,	0,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"MSI"                         ,	1,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI0_0"                      ,	2,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI0_1"                      ,	3,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI1_0"                      ,	4,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI1_1"                      ,	5,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_8"                ,	6,	3,	949,	"RAZ",	1,	1,	0,	0},
+	{"P2N1_P1"                     ,	9,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_P0"                     ,	10,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_N"                      ,	11,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C1"                     ,	12,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C0"                     ,	13,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P1"                     ,	14,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P0"                     ,	15,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_N"                      ,	16,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C1"                     ,	17,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C0"                     ,	18,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_24"              ,	19,	6,	949,	"RAZ",	1,	1,	0,	0},
+	{"CPL_P1"                      ,	25,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"CPL_P0"                      ,	26,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_28"              ,	27,	2,	949,	"RAZ",	1,	1,	0,	0},
+	{"N2P0_O"                      ,	29,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_C"                      ,	30,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	949,	"RAZ",	1,	1,	0,	0},
+	{"WAIT_COM"                    ,	0,	1,	950,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_4"                ,	1,	4,	950,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTLP_RO"                     ,	5,	1,	950,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	950,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTLP_RO"                     ,	7,	1,	950,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTA_MAP"                    ,	8,	2,	950,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTB_MAP"                    ,	10,	2,	950,	"R/W",	0,	0,	1ull,	1ull},
+	{"INTC_MAP"                    ,	12,	2,	950,	"R/W",	0,	0,	2ull,	2ull},
+	{"INTD_MAP"                    ,	14,	2,	950,	"R/W",	0,	0,	3ull,	3ull},
+	{"WAITL_COM"                   ,	16,	1,	950,	"R/W",	0,	1,	0ull,	0},
+	{"DIS_PORT"                    ,	17,	1,	950,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTA"                        ,	18,	1,	950,	"RO",	0,	0,	1ull,	1ull},
+	{"INTB"                        ,	19,	1,	950,	"RO",	0,	0,	1ull,	1ull},
+	{"INTC"                        ,	20,	1,	950,	"RO",	0,	0,	1ull,	1ull},
+	{"INTD"                        ,	21,	1,	950,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	950,	"RAZ",	1,	1,	0,	0},
+	{"CHIP_REV"                    ,	0,	8,	951,	"RO",	1,	1,	0,	0},
+	{"P0_NTAGS"                    ,	8,	6,	951,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_14_63"              ,	14,	50,	951,	"R/W",	0,	0,	32ull,	32ull},
+	{"P0_FCNT"                     ,	0,	6,	952,	"RO",	0,	1,	0ull,	0},
+	{"P0_UCNT"                     ,	6,	16,	952,	"RO",	0,	1,	0ull,	0},
+	{"P1_FCNT"                     ,	22,	6,	952,	"RAZ",	0,	1,	0ull,	0},
+	{"P1_UCNT"                     ,	28,	16,	952,	"RAZ",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	952,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	953,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	953,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	953,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	32,	954,	"R/W",	0,	1,	0ull,	0},
+	{"ADBG_SEL"                    ,	32,	1,	954,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	954,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	955,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	955,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	956,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	32,	956,	"R/W",	0,	1,	0ull,	0},
+	{"TIM"                         ,	0,	32,	957,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	957,	"RAZ",	1,	1,	0,	0},
+	{"RML_TO"                      ,	0,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	4,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	5,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UP_WI"                    ,	9,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_B0"                    ,	10,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_WI"                    ,	11,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_B0"                    ,	12,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_WI"                    ,	13,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_B0"                    ,	14,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_WI"                    ,	15,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT0"                    ,	16,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO_INT1"                    ,	17,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"M2_UP_B0"                    ,	20,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"M2_UP_WI"                    ,	21,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"M2_UN_B0"                    ,	22,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"M2_UN_WI"                    ,	23,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"M3_UP_B0"                    ,	24,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"M3_UP_WI"                    ,	25,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"M3_UN_B0"                    ,	26,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"M3_UN_WI"                    ,	27,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAFI"                       ,	32,	2,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	48,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT2_ERR"                   ,	58,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT3_ERR"                   ,	59,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML_TO"                      ,	0,	1,	959,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	959,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	959,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	959,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	4,	1,	959,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	5,	1,	959,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	959,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UP_WI"                    ,	9,	1,	959,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_B0"                    ,	10,	1,	959,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_WI"                    ,	11,	1,	959,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_B0"                    ,	12,	1,	959,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_WI"                    ,	13,	1,	959,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_B0"                    ,	14,	1,	959,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_WI"                    ,	15,	1,	959,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT0"                    ,	16,	1,	959,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT1"                    ,	17,	1,	959,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC0_INT"                    ,	18,	1,	959,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC1_INT"                    ,	19,	1,	959,	"R/W",	0,	0,	0ull,	1ull},
+	{"M2_UP_B0"                    ,	20,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"M2_UP_WI"                    ,	21,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"M2_UN_B0"                    ,	22,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"M2_UN_WI"                    ,	23,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"M3_UP_B0"                    ,	24,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"M3_UP_WI"                    ,	25,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"M3_UN_B0"                    ,	26,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"M3_UN_WI"                    ,	27,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAFI"                       ,	32,	2,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	48,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT2_ERR"                   ,	58,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT3_ERR"                   ,	59,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML_TO"                      ,	0,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAR0_TO"                     ,	2,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB2BIG"                     ,	3,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT"                        ,	4,	1,	960,	"RO",	0,	0,	0ull,	0ull},
+	{"PTIME"                       ,	5,	1,	960,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UP_WI"                    ,	9,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UN_B0"                    ,	10,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UN_WI"                    ,	11,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UP_B0"                    ,	12,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UP_WI"                    ,	13,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UN_B0"                    ,	14,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UN_WI"                    ,	15,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO_INT0"                    ,	16,	1,	960,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO_INT1"                    ,	17,	1,	960,	"RO",	0,	0,	0ull,	0ull},
+	{"MAC0_INT"                    ,	18,	1,	960,	"RO",	0,	0,	0ull,	0ull},
+	{"MAC1_INT"                    ,	19,	1,	960,	"RO",	0,	0,	0ull,	0ull},
+	{"M2_UP_B0"                    ,	20,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M2_UP_WI"                    ,	21,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M2_UN_B0"                    ,	22,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M2_UN_WI"                    ,	23,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M3_UP_B0"                    ,	24,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M3_UP_WI"                    ,	25,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M3_UN_B0"                    ,	26,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M3_UN_WI"                    ,	27,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	960,	"RAZ",	1,	1,	0,	0},
+	{"DMAFI"                       ,	32,	2,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	960,	"RO",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	960,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	960,	"RAZ",	1,	1,	0,	0},
+	{"PIDBOF"                      ,	48,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT2_ERR"                   ,	58,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT3_ERR"                   ,	59,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	960,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	960,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	961,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	962,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	963,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	964,	"RO",	0,	1,	0ull,	0},
+	{"P0_PCNT"                     ,	0,	8,	965,	"R/W",	0,	0,	128ull,	128ull},
+	{"P0_NCNT"                     ,	8,	8,	965,	"R/W",	0,	0,	16ull,	16ull},
+	{"P0_CCNT"                     ,	16,	8,	965,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_PCNT"                     ,	24,	8,	965,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_NCNT"                     ,	32,	8,	965,	"R/W",	0,	0,	16ull,	16ull},
+	{"P1_CCNT"                     ,	40,	8,	965,	"R/W",	0,	0,	128ull,	128ull},
+	{"P0_P_D"                      ,	48,	1,	965,	"R/W",	0,	0,	1ull,	1ull},
+	{"P0_N_D"                      ,	49,	1,	965,	"R/W",	0,	0,	1ull,	1ull},
+	{"P0_C_D"                      ,	50,	1,	965,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_P_D"                      ,	51,	1,	965,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_N_D"                      ,	52,	1,	965,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_C_D"                      ,	53,	1,	965,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_54_63"              ,	54,	10,	965,	"RAZ",	1,	1,	0,	0},
+	{"P2_PCNT"                     ,	0,	8,	966,	"R/W",	0,	0,	128ull,	128ull},
+	{"P2_NCNT"                     ,	8,	8,	966,	"R/W",	0,	0,	16ull,	16ull},
+	{"P2_CCNT"                     ,	16,	8,	966,	"R/W",	0,	0,	128ull,	128ull},
+	{"P3_PCNT"                     ,	24,	8,	966,	"R/W",	0,	0,	128ull,	128ull},
+	{"P3_NCNT"                     ,	32,	8,	966,	"R/W",	0,	0,	16ull,	16ull},
+	{"P3_CCNT"                     ,	40,	8,	966,	"R/W",	0,	0,	128ull,	128ull},
+	{"P2_P_D"                      ,	48,	1,	966,	"R/W",	0,	0,	1ull,	1ull},
+	{"P2_N_D"                      ,	49,	1,	966,	"R/W",	0,	0,	1ull,	1ull},
+	{"P2_C_D"                      ,	50,	1,	966,	"R/W",	0,	0,	1ull,	1ull},
+	{"P3_P_D"                      ,	51,	1,	966,	"R/W",	0,	0,	1ull,	1ull},
+	{"P3_N_D"                      ,	52,	1,	966,	"R/W",	0,	0,	1ull,	1ull},
+	{"P3_C_D"                      ,	53,	1,	966,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_54_63"              ,	54,	10,	966,	"RAZ",	1,	1,	0,	0},
+	{"NUM"                         ,	0,	8,	967,	"RO",	1,	1,	0,	0},
+	{"A_MODE"                      ,	8,	1,	967,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_63"               ,	9,	55,	967,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	10,	968,	"R/W",	0,	0,	0ull,	50ull},
+	{"MAX_WORD"                    ,	10,	4,	968,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	968,	"RAZ",	1,	1,	0,	0},
+	{"BA"                          ,	0,	30,	969,	"R/W",	0,	1,	0ull,	0},
+	{"RTYPE"                       ,	30,	2,	969,	"R/W",	0,	1,	0ull,	0},
+	{"WTYPE"                       ,	32,	2,	969,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	34,	2,	969,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	36,	2,	969,	"R/W",	0,	1,	0ull,	0},
+	{"NMERGE"                      ,	38,	1,	969,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORT"                        ,	39,	3,	969,	"R/W",	0,	1,	0ull,	0},
+	{"ZERO"                        ,	42,	1,	969,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	969,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	64,	970,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	971,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	972,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	973,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"INTR"                        ,	0,	64,	974,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	975,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	976,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	977,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	978,	"R/W",	0,	1,	0ull,	0},
+	{"RD_INT"                      ,	8,	8,	978,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	978,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	64,	979,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	980,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	982,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	983,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	984,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	985,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	986,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	987,	"R/W",	0,	1,	0ull,	0},
+	{"CIU_INT"                     ,	8,	8,	987,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	987,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	8,	988,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	988,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	989,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	8,	8,	989,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	989,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	990,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	16,	8,	990,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	990,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	991,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	24,	8,	991,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	991,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	992,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	32,	22,	992,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	992,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	993,	"R/W",	0,	0,	0ull,	0ull},
+	{"WMARK"                       ,	32,	32,	993,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	994,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	61,	994,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	995,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	995,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	996,	"R/W",	0,	1,	0ull,	0},
+	{"FCNT"                        ,	32,	5,	996,	"RO",	0,	1,	0ull,	0},
+	{"WRP"                         ,	37,	9,	996,	"RO",	0,	1,	0ull,	0},
+	{"RRP"                         ,	46,	9,	996,	"RO",	0,	1,	0ull,	0},
+	{"MAX"                         ,	55,	9,	996,	"RO",	0,	1,	16ull,	0},
+	{"NTAG"                        ,	0,	1,	997,	"R/W",	0,	1,	0ull,	0},
+	{"NTT"                         ,	1,	1,	997,	"R/W",	0,	1,	0ull,	0},
+	{"NGRP"                        ,	2,	1,	997,	"R/W",	0,	1,	0ull,	0},
+	{"NQOS"                        ,	3,	1,	997,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	997,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	997,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_13"              ,	13,	1,	997,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	997,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_20"              ,	16,	5,	997,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	997,	"R/W",	0,	1,	0ull,	0},
+	{"RNTAG"                       ,	22,	1,	997,	"R/W",	0,	1,	0ull,	0},
+	{"RNTT"                        ,	23,	1,	997,	"R/W",	0,	1,	0ull,	0},
+	{"RNGRP"                       ,	24,	1,	997,	"R/W",	0,	1,	0ull,	0},
+	{"RNQOS"                       ,	25,	1,	997,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_27"              ,	26,	2,	997,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	997,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_35_35"              ,	35,	1,	997,	"RAZ",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	997,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_42"              ,	38,	5,	997,	"RAZ",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	997,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	997,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	16,	998,	"R/W",	0,	1,	0ull,	0},
+	{"ISIZE"                       ,	16,	7,	998,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	998,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	999,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	4,	60,	999,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	1000,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	1000,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	1001,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1001,	"RO",	0,	1,	0ull,	0},
+	{"PORT"                        ,	0,	32,	1002,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1002,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1003,	"RAZ",	1,	1,	0,	0},
+	{"PKT_BP"                      ,	0,	4,	1004,	"R/W",	0,	0,	15ull,	15ull},
+	{"RING_EN"                     ,	4,	1,	1004,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	1004,	"RAZ",	1,	1,	0,	0},
+	{"ES"                          ,	0,	64,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1006,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	1007,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1007,	"RAZ",	1,	1,	0,	0},
+	{"DPTR"                        ,	0,	32,	1008,	"R/W",	0,	0,	0ull,	4294967295ull},
+	{"RESERVED_32_63"              ,	32,	32,	1008,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	32,	1009,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1009,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1010,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1010,	"RO",	0,	1,	0ull,	0},
+	{"RD_CNT"                      ,	0,	32,	1011,	"RO",	0,	1,	0ull,	0},
+	{"WR_CNT"                      ,	32,	32,	1011,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	0,	64,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	0,	1,	1013,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	1,	2,	1013,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	3,	1,	1013,	"R/W",	0,	1,	0ull,	0},
+	{"USE_CSR"                     ,	4,	1,	1013,	"R/W",	0,	0,	0ull,	1ull},
+	{"D_ROR"                       ,	5,	1,	1013,	"R/W",	0,	1,	0ull,	0},
+	{"D_ESR"                       ,	6,	2,	1013,	"R/W",	0,	1,	0ull,	0},
+	{"D_NSR"                       ,	8,	1,	1013,	"R/W",	0,	1,	0ull,	0},
+	{"PBP_DHI"                     ,	9,	13,	1013,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_RR"                      ,	22,	1,	1013,	"R/W",	0,	0,	0ull,	1ull},
+	{"PIN_RST"                     ,	23,	1,	1013,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_39"              ,	24,	16,	1013,	"RAZ",	1,	1,	0,	0},
+	{"PRC_IDLE"                    ,	40,	1,	1013,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_41_47"              ,	41,	7,	1013,	"RAZ",	1,	1,	0,	0},
+	{"GII_RDS"                     ,	48,	7,	1013,	"RO",	0,	1,	0ull,	0},
+	{"GII_ERST"                    ,	55,	1,	1013,	"RO",	0,	1,	0ull,	0},
+	{"PRD_RDS"                     ,	56,	7,	1013,	"RO",	0,	1,	0ull,	0},
+	{"PRD_ERST"                    ,	63,	1,	1013,	"RO",	0,	1,	0ull,	0},
+	{"ENB"                         ,	0,	32,	1014,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1014,	"RAZ",	1,	1,	0,	0},
+	{"RDSIZE"                      ,	0,	64,	1015,	"R/W",	0,	1,	0ull,	0},
+	{"IS_64B"                      ,	0,	32,	1016,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1016,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	22,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_54_63"              ,	54,	10,	1017,	"RAZ",	1,	1,	0,	0},
+	{"IPTR"                        ,	0,	32,	1018,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1018,	"RAZ",	1,	1,	0,	0},
+	{"BMODE"                       ,	0,	32,	1019,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1019,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	32,	1020,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1020,	"RAZ",	1,	1,	0,	0},
+	{"WMARK"                       ,	0,	32,	1021,	"R/W",	0,	0,	0ull,	14ull},
+	{"RESERVED_32_63"              ,	32,	32,	1021,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	0,	64,	1022,	"R/W",	0,	1,	0ull,	0},
+	{"OUT_RST"                     ,	0,	32,	1023,	"RO",	0,	1,	0ull,	0},
+	{"IN_RST"                      ,	32,	32,	1023,	"RO",	0,	1,	0ull,	0},
+	{"ES"                          ,	0,	64,	1024,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	1025,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1025,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	1026,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1026,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	1027,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1027,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	1028,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1028,	"RAZ",	1,	1,	0,	0},
+	{"MRRS"                        ,	0,	3,	1029,	"R/W",	0,	0,	2ull,	2ull},
+	{"BAR0_D"                      ,	3,	1,	1029,	"R/W",	1,	1,	0,	0},
+	{"WIND_D"                      ,	4,	1,	1029,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_5_63"               ,	5,	59,	1029,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	1030,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	1031,	"R/W",	0,	1,	0ull,	0},
+	{"CSR"                         ,	0,	39,	1032,	"RO",	0,	1,	1ull,	0},
+	{"ARB"                         ,	39,	1,	1032,	"RO",	0,	1,	0ull,	0},
+	{"CPL0"                        ,	40,	12,	1032,	"RO",	0,	1,	1ull,	0},
+	{"CPL1"                        ,	52,	12,	1032,	"RO",	0,	1,	1ull,	0},
+	{"NND"                         ,	0,	8,	1033,	"RO",	0,	1,	1ull,	0},
+	{"NNP0"                        ,	8,	8,	1033,	"RO",	0,	1,	1ull,	0},
+	{"CSM0"                        ,	16,	15,	1033,	"RO",	0,	1,	1ull,	0},
+	{"CSM1"                        ,	31,	15,	1033,	"RO",	0,	1,	1ull,	0},
+	{"RAC"                         ,	46,	1,	1033,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	1033,	"RAZ",	1,	1,	0,	0},
+	{"NNP1"                        ,	48,	8,	1033,	"RAZ",	0,	1,	0ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	1033,	"RAZ",	1,	1,	0,	0},
+	{"NSM0"                        ,	0,	13,	1034,	"RO",	0,	1,	1ull,	0},
+	{"NSM1"                        ,	13,	13,	1034,	"RO",	0,	1,	1ull,	0},
+	{"PSM0"                        ,	26,	15,	1034,	"RO",	0,	1,	1ull,	0},
+	{"PSM1"                        ,	41,	15,	1034,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	1034,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	0,	48,	1035,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	1035,	"R/W",	0,	0,	0ull,	0ull},
+	{"LD_CMD"                      ,	49,	2,	1035,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_51_63"              ,	51,	13,	1035,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	1036,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	1037,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	3,	45,	1037,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	1037,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	1037,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	1038,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	1039,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1039,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	1040,	"R/W",	0,	0,	0ull,	2097152ull},
+	{"RESERVED_32_63"              ,	32,	32,	1040,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	1041,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	1041,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	1041,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	1041,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	1041,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	1041,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	1041,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	1041,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	24,	1,	1041,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1041,	"RAZ",	1,	1,	0,	0},
+	{"REG_ADR"                     ,	0,	5,	1042,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1042,	"RAZ",	1,	1,	0,	0},
+	{"PHY_ADR"                     ,	8,	5,	1042,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	1042,	"RAZ",	1,	1,	0,	0},
+	{"PHY_OP"                      ,	16,	2,	1042,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	1042,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	1043,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	1043,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	1044,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	1044,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	1044,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	1044,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	1045,	"R/W",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	1045,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	1045,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	1045,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	1046,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_6_7"                ,	6,	2,	1046,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	8,	6,	1046,	"R/W",	0,	0,	19ull,	19ull},
+	{"RESERVED_14_63"              ,	14,	50,	1046,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	22,	1047,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1047,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	24,	22,	1047,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	1047,	"RAZ",	1,	1,	0,	0},
+	{"ENA"                         ,	47,	1,	1047,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1047,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	20,	1048,	"RO",	1,	0,	0,	0ull},
+	{"BASE"                        ,	20,	31,	1048,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	51,	13,	1048,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	0,	7,	1049,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	1049,	"RO",	1,	0,	0,	0ull},
+	{"CSIZE"                       ,	8,	13,	1049,	"RO",	1,	0,	0,	0ull},
+	{"CPOOL"                       ,	21,	3,	1049,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	1049,	"RAZ",	1,	1,	0,	0},
+	{"RING"                        ,	0,	4,	1050,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_BUCKETS"                 ,	4,	20,	1050,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIRST_BUCKET"                ,	24,	31,	1050,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	1050,	"RAZ",	1,	1,	0,	0},
+	{"RING"                        ,	0,	4,	1051,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	4,	22,	1051,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORDS_PER_CHUNK"             ,	26,	13,	1051,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	39,	3,	1051,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	42,	1,	1051,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	1051,	"RAZ",	1,	1,	0,	0},
+	{"CTL"                         ,	0,	1,	1052,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	1,	1,	1052,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	2,	2,	1052,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1052,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	1053,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1053,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE_TIMERS"               ,	0,	1,	1054,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	1054,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	2,	1,	1054,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	1054,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1055,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	1056,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	1056,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1056,	"RAZ",	1,	1,	0,	0},
+	{"TDF"                         ,	0,	1,	1057,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1057,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRAP"                        ,	1,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRIG_CTL"                    ,	2,	2,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIME_GRN"                    ,	4,	3,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"FULL_THR"                    ,	7,	2,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	9,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	10,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	11,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	12,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_ENA"                    ,	13,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNORE_O"                    ,	14,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKALWAYS"                   ,	15,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDAT_MD"                     ,	16,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	1058,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	8,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"RPTR"                        ,	8,	8,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	16,	48,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	10,	1060,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	1060,	"RAZ",	1,	1,	0,	0},
+	{"RPTR"                        ,	12,	10,	1060,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1060,	"RAZ",	1,	1,	0,	0},
+	{"CYCLES"                      ,	24,	40,	1060,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1061,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1061,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1062,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1062,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1063,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1064,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1064,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1064,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1064,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1064,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1064,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1064,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1064,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1064,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1064,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1064,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1064,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1064,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1064,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1064,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1064,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1064,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1064,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1064,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1064,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	4,	1065,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	1065,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1065,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1065,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1065,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1065,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1065,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	0,	1,	1066,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	1,	1,	1066,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	2,	1,	1066,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	3,	1,	1066,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1066,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	1067,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	5,	1068,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	1068,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1069,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1069,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1070,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1071,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1071,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1071,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1071,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1071,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1071,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1072,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1072,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1072,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1072,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1072,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1072,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1072,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1072,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1072,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1072,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1072,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1072,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1072,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1072,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1072,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1072,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1072,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1072,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1072,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1072,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	4,	1073,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	1073,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1073,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1073,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1073,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1073,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1073,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1074,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1074,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1075,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1075,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1076,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1076,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1076,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1076,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1076,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1077,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1077,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1077,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1077,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1077,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1077,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1077,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1077,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1077,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1077,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1077,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1077,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1077,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1077,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1077,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1077,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1077,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1077,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1077,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1077,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	4,	1078,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	1078,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1078,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1078,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1078,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1078,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1078,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	1079,	"R/W",	0,	1,	0ull,	0},
+	{"LPL"                         ,	5,	27,	1079,	"R/W",	0,	1,	0ull,	0},
+	{"CF"                          ,	0,	1,	1080,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_31"               ,	1,	31,	1080,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTRLDSSEG"                   ,	0,	32,	1081,	"R/W",	0,	1,	0ull,	0},
+	{"FI"                          ,	0,	14,	1082,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_31"              ,	14,	18,	1082,	"RO",	0,	0,	0ull,	0ull},
+	{"CAPLENGTH"                   ,	0,	8,	1083,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_8_15"               ,	8,	8,	1083,	"RO",	0,	0,	0ull,	0ull},
+	{"HCIVERSION"                  ,	16,	16,	1083,	"RO",	0,	0,	256ull,	256ull},
+	{"AC64"                        ,	0,	1,	1084,	"RO",	0,	0,	1ull,	1ull},
+	{"PFLF"                        ,	1,	1,	1084,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPC"                        ,	2,	1,	1084,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1084,	"RO",	0,	0,	0ull,	0ull},
+	{"IST"                         ,	4,	4,	1084,	"RO",	0,	0,	2ull,	2ull},
+	{"EECP"                        ,	8,	8,	1084,	"RO",	0,	0,	160ull,	160ull},
+	{"RESERVED_16_31"              ,	16,	16,	1084,	"RO",	0,	0,	0ull,	0ull},
+	{"N_PORTS"                     ,	0,	4,	1085,	"RO",	0,	0,	2ull,	2ull},
+	{"PPC"                         ,	4,	1,	1085,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	1085,	"RO",	0,	0,	0ull,	0ull},
+	{"PRR"                         ,	7,	1,	1085,	"RO",	0,	0,	0ull,	0ull},
+	{"N_PCC"                       ,	8,	4,	1085,	"RO",	0,	0,	2ull,	2ull},
+	{"N_CC"                        ,	12,	4,	1085,	"RO",	0,	0,	1ull,	1ull},
+	{"P_INDICATOR"                 ,	16,	1,	1085,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	1085,	"RO",	0,	0,	0ull,	0ull},
+	{"DPN"                         ,	20,	4,	1085,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1085,	"RO",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	0,	1,	1086,	"R/W",	0,	0,	0ull,	0ull},
+	{"MFMC"                        ,	1,	13,	1086,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	1086,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_0"                ,	0,	1,	1087,	"R/W",	0,	0,	0ull,	0ull},
+	{"TA_OFF"                      ,	1,	8,	1087,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	1087,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXTX_TADAO"                  ,	10,	3,	1087,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	1087,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCP_RW"                      ,	0,	1,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCP_FW"                      ,	1,	1,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"PESD"                        ,	2,	1,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1088,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NAKRF_DIS"                   ,	4,	1,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTO_DIS"                    ,	5,	1,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_30"               ,	0,	31,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	31,	1,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_ADDR"                    ,	0,	32,	1090,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_11"               ,	0,	12,	1091,	"R/W",	0,	1,	0ull,	0},
+	{"BADDR"                       ,	12,	20,	1091,	"R/W",	0,	1,	0ull,	0},
+	{"CCS"                         ,	0,	1,	1092,	"RO",	0,	0,	0ull,	0ull},
+	{"CSC"                         ,	1,	1,	1092,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PED"                         ,	2,	1,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEDC"                        ,	3,	1,	1092,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OCA"                         ,	4,	1,	1092,	"RO",	0,	0,	0ull,	0ull},
+	{"OCC"                         ,	5,	1,	1092,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPR"                         ,	6,	1,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPD"                         ,	7,	1,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRST"                        ,	8,	1,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	1092,	"RO",	0,	0,	0ull,	0ull},
+	{"LSTS"                        ,	10,	2,	1092,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	12,	1,	1092,	"RO",	0,	0,	1ull,	1ull},
+	{"PO"                          ,	13,	1,	1092,	"R/W",	0,	0,	1ull,	0ull},
+	{"PIC"                         ,	14,	2,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTC"                         ,	16,	4,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKCNNT_E"                    ,	20,	1,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKDSCNNT_E"                  ,	21,	1,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKOC_E"                      ,	22,	1,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	1092,	"RO",	0,	0,	0ull,	0ull},
+	{"RS"                          ,	0,	1,	1093,	"R/W",	0,	0,	0ull,	1ull},
+	{"HCRESET"                     ,	1,	1,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"FLS"                         ,	2,	2,	1093,	"RO",	0,	0,	0ull,	0ull},
+	{"PS_EN"                       ,	4,	1,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"AS_EN"                       ,	5,	1,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"IAA_DB"                      ,	6,	1,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"LHCR"                        ,	7,	1,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASPMC"                       ,	8,	2,	1093,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	1093,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPM_EN"                     ,	11,	1,	1093,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	1093,	"RO",	0,	0,	0ull,	0ull},
+	{"ITC"                         ,	16,	8,	1093,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_24_31"              ,	24,	8,	1093,	"RO",	0,	0,	0ull,	0ull},
+	{"USBINT_EN"                   ,	0,	1,	1094,	"R/W",	0,	1,	0ull,	0},
+	{"USBERRINT_EN"                ,	1,	1,	1094,	"R/W",	0,	1,	0ull,	0},
+	{"PCI_EN"                      ,	2,	1,	1094,	"R/W",	0,	1,	0ull,	0},
+	{"FLRO_EN"                     ,	3,	1,	1094,	"R/W",	0,	1,	0ull,	0},
+	{"HSERR_EN"                    ,	4,	1,	1094,	"R/W",	0,	1,	0ull,	0},
+	{"IOAA_EN"                     ,	5,	1,	1094,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_31"               ,	6,	26,	1094,	"RO",	0,	0,	0ull,	0ull},
+	{"USBINT"                      ,	0,	1,	1095,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBERRINT"                   ,	1,	1,	1095,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCD"                         ,	2,	1,	1095,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FLRO"                        ,	3,	1,	1095,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HSYSERR"                     ,	4,	1,	1095,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOAA"                        ,	5,	1,	1095,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	1095,	"RO",	0,	0,	0ull,	0ull},
+	{"HCHTD"                       ,	12,	1,	1095,	"RO",	0,	0,	1ull,	0ull},
+	{"RECLM"                       ,	13,	1,	1095,	"RO",	0,	0,	0ull,	0ull},
+	{"PSS"                         ,	14,	1,	1095,	"RO",	0,	0,	0ull,	0ull},
+	{"ASS"                         ,	15,	1,	1095,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1095,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCED"                        ,	4,	28,	1096,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1097,	"R/W",	0,	0,	0ull,	0ull},
+	{"BHED"                        ,	4,	28,	1097,	"R/W",	0,	1,	0ull,	0},
+	{"HCR"                         ,	0,	1,	1098,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLF"                         ,	1,	1,	1098,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLF"                         ,	2,	1,	1098,	"R/W",	0,	0,	0ull,	0ull},
+	{"OCR"                         ,	3,	1,	1098,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	1098,	"RO",	0,	0,	0ull,	0ull},
+	{"SOC"                         ,	16,	2,	1098,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	1098,	"RO",	0,	0,	0ull,	0ull},
+	{"CBSR"                        ,	0,	2,	1099,	"R/W",	0,	1,	0ull,	0},
+	{"PLE"                         ,	2,	1,	1099,	"R/W",	0,	0,	0ull,	0ull},
+	{"IE"                          ,	3,	1,	1099,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLE"                         ,	4,	1,	1099,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLE"                         ,	5,	1,	1099,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCFS"                        ,	6,	2,	1099,	"R/W",	0,	0,	0ull,	0ull},
+	{"IR"                          ,	8,	1,	1099,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWC"                         ,	9,	1,	1099,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWE"                         ,	10,	1,	1099,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	1099,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1100,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCED"                        ,	4,	28,	1100,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1101,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHED"                        ,	4,	28,	1101,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1102,	"RO",	0,	0,	0ull,	0ull},
+	{"DH"                          ,	4,	28,	1102,	"RO",	0,	1,	0ull,	0},
+	{"FI"                          ,	0,	14,	1103,	"R/W",	0,	1,	11999ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	1103,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSMPS"                       ,	16,	15,	1103,	"R/W",	0,	1,	0ull,	0},
+	{"FIT"                         ,	31,	1,	1103,	"R/W",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	0,	16,	1104,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	1104,	"RO",	0,	0,	0ull,	0ull},
+	{"FR"                          ,	0,	14,	1105,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_30"              ,	14,	17,	1105,	"RO",	0,	0,	0ull,	0ull},
+	{"FRT"                         ,	31,	1,	1105,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	1106,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCCA"                        ,	8,	24,	1106,	"R/W",	0,	1,	0ull,	0},
+	{"SO"                          ,	0,	1,	1107,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1107,	"R/W",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1107,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1107,	"R/W",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1107,	"R/W",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1107,	"R/W",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1107,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1107,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIE"                         ,	31,	1,	1107,	"R/W",	0,	0,	0ull,	0ull},
+	{"SO"                          ,	0,	1,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1108,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIE"                         ,	31,	1,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"SO"                          ,	0,	1,	1109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1109,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1109,	"RO",	0,	0,	0ull,	0ull},
+	{"LST"                         ,	0,	12,	1110,	"R/W",	0,	1,	1576ull,	0},
+	{"RESERVED_12_31"              ,	12,	20,	1110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1111,	"RO",	0,	0,	0ull,	0ull},
+	{"PCED"                        ,	4,	28,	1111,	"RO",	0,	1,	0ull,	0},
+	{"PS"                          ,	0,	14,	1112,	"R/W",	0,	0,	0ull,	15975ull},
+	{"RESERVED_14_31"              ,	14,	18,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"REV"                         ,	0,	8,	1113,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_8_31"               ,	8,	24,	1113,	"RO",	0,	0,	0ull,	0ull},
+	{"NDP"                         ,	0,	8,	1114,	"RO",	0,	0,	2ull,	2ull},
+	{"NPS"                         ,	8,	1,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSM"                         ,	9,	1,	1114,	"R/W",	0,	0,	1ull,	1ull},
+	{"DT"                          ,	10,	1,	1114,	"RO",	0,	0,	0ull,	0ull},
+	{"OCPM"                        ,	11,	1,	1114,	"R/W",	1,	1,	0,	0},
+	{"NOCP"                        ,	12,	1,	1114,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_23"              ,	13,	11,	1114,	"RO",	0,	0,	0ull,	0ull},
+	{"POTPGT"                      ,	24,	8,	1114,	"R/W",	0,	0,	1ull,	1ull},
+	{"DR"                          ,	0,	16,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPCM"                        ,	16,	16,	1115,	"R/W",	0,	1,	0ull,	0},
+	{"CCS"                         ,	0,	1,	1116,	"R/W",	0,	1,	0ull,	0},
+	{"PES"                         ,	1,	1,	1116,	"R/W",	0,	1,	0ull,	0},
+	{"PSS"                         ,	2,	1,	1116,	"R/W",	0,	1,	0ull,	0},
+	{"POCI"                        ,	3,	1,	1116,	"R/W",	0,	1,	0ull,	0},
+	{"PRS"                         ,	4,	1,	1116,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS"                         ,	8,	1,	1116,	"R/W",	0,	1,	0ull,	0},
+	{"LSDA"                        ,	9,	1,	1116,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_10_15"              ,	10,	6,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSC"                         ,	16,	1,	1116,	"R/W",	0,	1,	0ull,	0},
+	{"PESC"                        ,	17,	1,	1116,	"R/W",	0,	1,	0ull,	0},
+	{"PSSC"                        ,	18,	1,	1116,	"R/W",	0,	1,	0ull,	0},
+	{"OCIC"                        ,	19,	1,	1116,	"R/W",	0,	1,	0ull,	0},
+	{"PRSC"                        ,	20,	1,	1116,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_31"              ,	21,	11,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"LPS"                         ,	0,	1,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"OCI"                         ,	1,	1,	1117,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_14"               ,	2,	13,	1117,	"RO",	0,	0,	0ull,	0ull},
+	{"DRWE"                        ,	15,	1,	1117,	"R/W",	0,	1,	0ull,	0},
+	{"LPSC"                        ,	16,	1,	1117,	"R/W",	0,	1,	0ull,	0},
+	{"CCIC"                        ,	17,	1,	1117,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_18_30"              ,	18,	13,	1117,	"RO",	0,	0,	0ull,	0ull},
+	{"CRWE"                        ,	31,	1,	1117,	"WO",	1,	1,	0,	0},
+	{"RESERVED_0_30"               ,	0,	31,	1118,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	31,	1,	1118,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_ADDR"                    ,	0,	32,	1119,	"RO",	0,	0,	0ull,	0ull},
+	{"PPAF_BIS"                    ,	0,	1,	1120,	"RO",	0,	0,	0ull,	0ull},
+	{"WRBM_BIS"                    ,	1,	1,	1120,	"RO",	0,	0,	0ull,	0ull},
+	{"ORBM_BIS"                    ,	2,	1,	1120,	"RO",	0,	0,	0ull,	0ull},
+	{"ERBM_BIS"                    ,	3,	1,	1120,	"RO",	0,	0,	0ull,	0ull},
+	{"DESC_BIS"                    ,	4,	1,	1120,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_BIS"                    ,	5,	1,	1120,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1120,	"RO",	1,	1,	0,	0},
+	{"HRST"                        ,	0,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_PRST"                      ,	1,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_POR"                       ,	2,	1,	1121,	"R/W",	0,	0,	1ull,	0ull},
+	{"P_COM_ON"                    ,	3,	1,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	1121,	"R/W",	0,	1,	0ull,	0},
+	{"P_REFCLK_DIV"                ,	5,	2,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_REFCLK_SEL"                ,	7,	2,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"H_DIV"                       ,	9,	4,	1121,	"R/W",	0,	0,	6ull,	6ull},
+	{"O_CLKDIV_EN"                 ,	13,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_EN"                 ,	14,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_RST"                ,	15,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_BYP"                ,	16,	1,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"O_CLKDIV_RST"                ,	17,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
+	{"APP_START_CLK"               ,	18,	1,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"OHCI_SUSP_LGCY"              ,	19,	1,	1121,	"R/W",	0,	0,	1ull,	1ull},
+	{"OHCI_SM"                     ,	20,	1,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"OHCI_CLKCKTRST"              ,	21,	1,	1121,	"R/W",	0,	0,	1ull,	1ull},
+	{"EHCI_SM"                     ,	22,	1,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"START_BIST"                  ,	23,	1,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLEAR_BIST"                  ,	24,	1,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1121,	"RAZ",	1,	1,	0,	0},
+	{"L2C_ADDR_MSB"                ,	0,	8,	1122,	"R/W",	0,	1,	0ull,	0},
+	{"EHCI_64B_ADDR_EN"            ,	8,	1,	1122,	"R/W",	0,	0,	1ull,	1ull},
+	{"INV_REG_A2"                  ,	9,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DESC_EMOD"               ,	10,	2,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BUFF_EMOD"               ,	12,	2,	1122,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2C_STT"                     ,	14,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_0PAG"                    ,	15,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BC"                      ,	16,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DC"                      ,	17,	1,	1122,	"R/W",	0,	0,	1ull,	1ull},
+	{"REG_NB"                      ,	18,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"DESC_RBM"                    ,	19,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1122,	"RAZ",	1,	1,	0,	0},
+	{"FLA"                         ,	0,	6,	1123,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	1123,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	1124,	"RAZ",	1,	1,	0,	0},
+	{"TO_VAL"                      ,	5,	27,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1124,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	1125,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	1125,	"RAZ",	1,	1,	0,	0},
+	{"PP_PSH_F"                    ,	0,	1,	1126,	"R/W",	0,	0,	0ull,	0ull},
+	{"ER_PSH_F"                    ,	1,	1,	1126,	"R/W",	0,	0,	0ull,	0ull},
+	{"OR_PSH_F"                    ,	2,	1,	1126,	"R/W",	0,	0,	0ull,	0ull},
+	{"CF_PSH_F"                    ,	3,	1,	1126,	"R/W",	0,	0,	0ull,	0ull},
+	{"WB_PSH_F"                    ,	4,	1,	1126,	"R/W",	0,	0,	0ull,	0ull},
+	{"WB_POP_E"                    ,	5,	1,	1126,	"R/W",	0,	0,	0ull,	0ull},
+	{"OC_OVF_E"                    ,	6,	1,	1126,	"R/W",	0,	0,	0ull,	0ull},
+	{"EC_OVF_E"                    ,	7,	1,	1126,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1126,	"RAZ",	1,	1,	0,	0},
+	{"PP_PSH_F"                    ,	0,	1,	1127,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ER_PSH_F"                    ,	1,	1,	1127,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OR_PSH_F"                    ,	2,	1,	1127,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CF_PSH_F"                    ,	3,	1,	1127,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WB_PSH_F"                    ,	4,	1,	1127,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WB_POP_E"                    ,	5,	1,	1127,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OC_OVF_E"                    ,	6,	1,	1127,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EC_OVF_E"                    ,	7,	1,	1127,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1127,	"RAZ",	1,	1,	0,	0},
+	{"L2C_ADDR_MSB"                ,	0,	8,	1128,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_8"                ,	8,	1,	1128,	"RAZ",	1,	1,	0,	0},
+	{"INV_REG_A2"                  ,	9,	1,	1128,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DESC_EMOD"               ,	10,	2,	1128,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BUFF_EMOD"               ,	12,	2,	1128,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2C_STT"                     ,	14,	1,	1128,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_0PAG"                    ,	15,	1,	1128,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BC"                      ,	16,	1,	1128,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DC"                      ,	17,	1,	1128,	"R/W",	0,	0,	1ull,	1ull},
+	{"REG_NB"                      ,	18,	1,	1128,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	1128,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1129,	"RAZ",	1,	1,	0,	0},
+	{"TO_VAL"                      ,	8,	24,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1129,	"RAZ",	1,	1,	0,	0},
+	{"WM"                          ,	0,	5,	1130,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_5_63"               ,	5,	59,	1130,	"RAZ",	1,	1,	0,	0},
+	{"ATE_RESET"                   ,	0,	1,	1131,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_EN"                     ,	1,	1,	1131,	"R/W",	0,	0,	0ull,	0ull},
+	{"UPHY_BIST"                   ,	2,	1,	1131,	"R/W",	0,	0,	0ull,	0ull},
+	{"VTEST_EN"                    ,	3,	1,	1131,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIDDQ"                       ,	4,	1,	1131,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBIST"                      ,	5,	1,	1131,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSBIST"                      ,	6,	1,	1131,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSBIST"                      ,	7,	1,	1131,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_ERR"                    ,	8,	1,	1131,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST_DONE"                   ,	9,	1,	1131,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1131,	"RAZ",	1,	1,	0,	0},
+	{"TDATA_IN"                    ,	0,	8,	1132,	"R/W",	0,	0,	0ull,	0ull},
+	{"TADDR_IN"                    ,	8,	4,	1132,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_SEL"                   ,	12,	1,	1132,	"R/W",	0,	0,	1ull,	0ull},
+	{"TCLK"                        ,	13,	1,	1132,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOP_EN"                     ,	14,	1,	1132,	"R/W",	0,	0,	0ull,	0ull},
+	{"COMPDISTUNE"                 ,	15,	3,	1132,	"R/W",	0,	0,	4ull,	4ull},
+	{"SQRXTUNE"                    ,	18,	3,	1132,	"R/W",	0,	0,	4ull,	4ull},
+	{"TXFSLSTUNE"                  ,	21,	4,	1132,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPREEMPHASISTUNE"           ,	25,	1,	1132,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXRISETUNE"                  ,	26,	1,	1132,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXVREFTUNE"                  ,	27,	4,	1132,	"R/W",	0,	0,	5ull,	15ull},
+	{"TXHSVXTUNE"                  ,	31,	2,	1132,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORTRESET"                   ,	33,	1,	1132,	"R/W",	0,	0,	0ull,	0ull},
+	{"VBUSVLDEXT"                  ,	34,	1,	1132,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPPULLDOWN"                  ,	35,	1,	1132,	"R/W",	0,	0,	1ull,	1ull},
+	{"DMPULLDOWN"                  ,	36,	1,	1132,	"R/W",	0,	0,	1ull,	1ull},
+	{"TXBISTSTUFFEN"               ,	37,	1,	1132,	"R/W",	0,	0,	1ull,	1ull},
+	{"TXBISTSTUFFENH"              ,	38,	1,	1132,	"R/W",	0,	0,	1ull,	1ull},
+	{"TDATA_OUT"                   ,	39,	4,	1132,	"RO",	1,	1,	0,	0},
+	{"RESERVED_43_63"              ,	43,	21,	1132,	"RAZ",	1,	1,	0,	0},
+	{"ZIP_CTL"                     ,	0,	4,	1133,	"RO",	1,	0,	0,	0ull},
+	{"ZIP_CORE"                    ,	4,	53,	1133,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_57_63"              ,	57,	7,	1133,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	1134,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	33,	13,	1134,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	46,	3,	1134,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	49,	9,	1134,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	1134,	"RAZ",	1,	1,	0,	0},
+	{"RESET"                       ,	0,	1,	1135,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FORCECLK"                    ,	1,	1,	1135,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1135,	"RAZ",	1,	1,	0,	0},
+	{"DISABLED"                    ,	0,	1,	1136,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	1136,	"RAZ",	1,	1,	0,	0},
+	{"CTXSIZE"                     ,	8,	12,	1136,	"RO",	0,	0,	1536ull,	1536ull},
+	{"ONFSIZE"                     ,	20,	12,	1136,	"RO",	0,	0,	512ull,	512ull},
+	{"DEPTH"                       ,	32,	16,	1136,	"RO",	0,	0,	31744ull,	31744ull},
+	{"SYNCFLUSH_CAPABLE"           ,	48,	1,	1136,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_49_55"              ,	49,	7,	1136,	"RAZ",	1,	1,	0,	0},
+	{"NEXEC"                       ,	56,	8,	1136,	"RO",	0,	0,	1ull,	1ull},
+	{"ASSERTS"                     ,	0,	17,	1137,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	1137,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1138,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1138,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1139,	"RAZ",	1,	1,	0,	0},
+	{"MAX_INFL"                    ,	0,	4,	1140,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	1140,	"RAZ",	1,	1,	0,	0},
+	{NULL,0,0,0,0,0,0,0,0}
+};
 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn63xxp1[] = {
 	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
 	{"cvmx_agl_gmx_bad_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	0,	14,	0},
@@ -74996,407 +90006,413 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn63xxp1[] = {
 	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6225,	2,	4420},
 	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6226,	2,	4422},
 	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6227,	2,	4424},
-	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6239,	2,	4426},
-	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6251,	2,	4428},
-	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6263,	2,	4430},
-	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6275,	2,	4432},
-	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6287,	2,	4434},
-	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6299,	2,	4436},
-	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6311,	2,	4438},
-	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6323,	2,	4440},
-	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6335,	2,	4442},
-	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6347,	2,	4444},
-	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6348,	2,	4446},
-	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6364,	2,	4448},
-	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6380,	2,	4450},
-	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6396,	2,	4452},
-	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6460,	2,	4454},
-	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6461,	3,	4456},
-	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6462,	3,	4459},
-	{"cvmx_pip_xstat0_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6463,	2,	4462},
-	{"cvmx_pip_xstat1_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6467,	2,	4464},
-	{"cvmx_pip_xstat2_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6471,	2,	4466},
-	{"cvmx_pip_xstat3_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6475,	2,	4468},
-	{"cvmx_pip_xstat4_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6479,	2,	4470},
-	{"cvmx_pip_xstat5_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6483,	2,	4472},
-	{"cvmx_pip_xstat6_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6487,	2,	4474},
-	{"cvmx_pip_xstat7_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6491,	2,	4476},
-	{"cvmx_pip_xstat8_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6495,	2,	4478},
-	{"cvmx_pip_xstat9_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6499,	2,	4480},
-	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6503,	2,	4482},
-	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6504,	2,	4484},
-	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6505,	4,	4486},
-	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6506,	5,	4490},
-	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6507,	4,	4495},
-	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6508,	8,	4499},
-	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6509,	4,	4507},
-	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6510,	5,	4511},
-	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6511,	1,	4516},
-	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6512,	5,	4517},
-	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6513,	1,	4522},
-	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6514,	13,	4523},
-	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6515,	6,	4536},
-	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6516,	13,	4542},
-	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6517,	6,	4555},
-	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6518,	9,	4561},
-	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6519,	4,	4570},
-	{"cvmx_pko_mem_port_ptrs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6520,	7,	4574},
-	{"cvmx_pko_mem_port_qos"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6521,	5,	4581},
-	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6522,	5,	4586},
-	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6523,	4,	4591},
-	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6524,	9,	4595},
-	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6525,	5,	4604},
-	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6526,	16,	4609},
-	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6527,	4,	4625},
-	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6528,	1,	4629},
-	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6529,	1,	4630},
-	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6530,	1,	4631},
-	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6531,	1,	4632},
-	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	6532,	13,	4633},
-	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6533,	2,	4646},
-	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6534,	4,	4648},
-	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6535,	5,	4652},
-	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6536,	3,	4657},
-	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6537,	4,	4660},
-	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6538,	2,	4664},
-	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6539,	3,	4666},
-	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6540,	3,	4669},
-	{"cvmx_pko_reg_timestamp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6541,	2,	4672},
-	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6542,	10,	4674},
-	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	6543,	2,	4684},
-	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6544,	13,	4686},
-	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6545,	3,	4699},
-	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6546,	2,	4702},
-	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	6554,	2,	4704},
-	{"cvmx_pow_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6555,	2,	4706},
-	{"cvmx_pow_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6556,	2,	4708},
-	{"cvmx_pow_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6557,	2,	4710},
-	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6565,	2,	4712},
-	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6566,	2,	4714},
-	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	6567,	2,	4716},
-	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6568,	10,	4718},
-	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	6574,	5,	4728},
-	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	6582,	10,	4733},
-	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	6590,	2,	4743},
-	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6591,	2,	4745},
-	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6592,	2,	4747},
-	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6600,	3,	4749},
-	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6601,	6,	4752},
-	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6617,	5,	4758},
-	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6618,	7,	4763},
-	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6634,	2,	4770},
-	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6650,	1,	4772},
-	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6651,	1,	4773},
-	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6652,	1,	4774},
-	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6653,	5,	4775},
-	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6654,	5,	4780},
-	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6655,	4,	4785},
-	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6656,	10,	4789},
-	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6657,	1,	4799},
-	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6658,	3,	4800},
-	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6659,	7,	4803},
-	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6660,	2,	4810},
-	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6661,	1,	4812},
-	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6662,	1,	4813},
-	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6663,	1,	4814},
-	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6664,	18,	4815},
-	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6665,	3,	4833},
-	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6666,	2,	4836},
-	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6667,	3,	4838},
-	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6668,	7,	4841},
-	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6669,	2,	4848},
-	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6670,	2,	4850},
-	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6671,	2,	4852},
-	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6672,	3,	4854},
-	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6673,	3,	4857},
-	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6674,	9,	4860},
-	{"cvmx_rnm_eer_dbg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6675,	1,	4869},
-	{"cvmx_rnm_eer_key"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6676,	1,	4870},
-	{"cvmx_sli_bist_status"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6677,	25,	4871},
-	{"cvmx_sli_ctl_port#"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6678,	16,	4896},
-	{"cvmx_sli_ctl_status"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6680,	4,	4912},
-	{"cvmx_sli_data_out_cnt"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6681,	5,	4916},
-	{"cvmx_sli_dbg_data"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6682,	3,	4921},
-	{"cvmx_sli_dbg_select"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6683,	3,	4924},
-	{"cvmx_sli_dma#_cnt"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6684,	2,	4927},
-	{"cvmx_sli_dma#_int_level"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6686,	2,	4929},
-	{"cvmx_sli_dma#_tim"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6688,	2,	4931},
-	{"cvmx_sli_int_enb_ciu"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6690,	35,	4933},
-	{"cvmx_sli_int_enb_port#"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6691,	37,	4968},
-	{"cvmx_sli_int_sum"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6693,	37,	5005},
-	{"cvmx_sli_last_win_rdata0"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6694,	1,	5042},
-	{"cvmx_sli_last_win_rdata1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6695,	1,	5043},
-	{"cvmx_sli_mac_credit_cnt"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6696,	7,	5044},
-	{"cvmx_sli_mem_access_ctl"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6697,	3,	5051},
-	{"cvmx_sli_mem_access_subid#"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6698,	9,	5054},
-	{"cvmx_sli_msi_enb0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6714,	1,	5063},
-	{"cvmx_sli_msi_enb1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6715,	1,	5064},
-	{"cvmx_sli_msi_enb2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6716,	1,	5065},
-	{"cvmx_sli_msi_enb3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6717,	1,	5066},
-	{"cvmx_sli_msi_rcv0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6718,	1,	5067},
-	{"cvmx_sli_msi_rcv1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6719,	1,	5068},
-	{"cvmx_sli_msi_rcv2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6720,	1,	5069},
-	{"cvmx_sli_msi_rcv3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6721,	1,	5070},
-	{"cvmx_sli_msi_rd_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6722,	3,	5071},
-	{"cvmx_sli_msi_w1c_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6723,	1,	5074},
-	{"cvmx_sli_msi_w1c_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6724,	1,	5075},
-	{"cvmx_sli_msi_w1c_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6725,	1,	5076},
-	{"cvmx_sli_msi_w1c_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6726,	1,	5077},
-	{"cvmx_sli_msi_w1s_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6727,	1,	5078},
-	{"cvmx_sli_msi_w1s_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6728,	1,	5079},
-	{"cvmx_sli_msi_w1s_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6729,	1,	5080},
-	{"cvmx_sli_msi_w1s_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6730,	1,	5081},
-	{"cvmx_sli_msi_wr_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6731,	3,	5082},
-	{"cvmx_sli_pcie_msi_rcv"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6732,	2,	5085},
-	{"cvmx_sli_pcie_msi_rcv_b1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6733,	3,	5087},
-	{"cvmx_sli_pcie_msi_rcv_b2"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6734,	3,	5090},
-	{"cvmx_sli_pcie_msi_rcv_b3"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6735,	3,	5093},
-	{"cvmx_sli_pkt#_cnts"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6736,	3,	5096},
-	{"cvmx_sli_pkt#_in_bp"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6768,	2,	5099},
-	{"cvmx_sli_pkt#_instr_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6800,	2,	5101},
-	{"cvmx_sli_pkt#_instr_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6832,	2,	5103},
-	{"cvmx_sli_pkt#_instr_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6864,	5,	5105},
-	{"cvmx_sli_pkt#_instr_header"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6896,	21,	5110},
-	{"cvmx_sli_pkt#_out_size"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6928,	3,	5131},
-	{"cvmx_sli_pkt#_slist_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6960,	2,	5134},
-	{"cvmx_sli_pkt#_slist_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6992,	2,	5136},
-	{"cvmx_sli_pkt#_slist_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7024,	2,	5138},
-	{"cvmx_sli_pkt_cnt_int"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7056,	2,	5140},
-	{"cvmx_sli_pkt_cnt_int_enb"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7057,	2,	5142},
-	{"cvmx_sli_pkt_ctl"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7058,	3,	5144},
-	{"cvmx_sli_pkt_data_out_es"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7059,	1,	5147},
-	{"cvmx_sli_pkt_data_out_ns"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7060,	2,	5148},
-	{"cvmx_sli_pkt_data_out_ror"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7061,	2,	5150},
-	{"cvmx_sli_pkt_dpaddr"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7062,	2,	5152},
-	{"cvmx_sli_pkt_in_bp"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7063,	2,	5154},
-	{"cvmx_sli_pkt_in_done#_cnts"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7064,	2,	5156},
-	{"cvmx_sli_pkt_in_instr_counts",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7096,	2,	5158},
-	{"cvmx_sli_pkt_in_pcie_port"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7097,	1,	5160},
-	{"cvmx_sli_pkt_input_control"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7098,	10,	5161},
-	{"cvmx_sli_pkt_instr_enb"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7099,	2,	5171},
-	{"cvmx_sli_pkt_instr_rd_size"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7100,	1,	5173},
-	{"cvmx_sli_pkt_instr_size"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7101,	2,	5174},
-	{"cvmx_sli_pkt_int_levels"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7102,	3,	5176},
-	{"cvmx_sli_pkt_iptr"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7103,	2,	5179},
-	{"cvmx_sli_pkt_out_bmode"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7104,	2,	5181},
-	{"cvmx_sli_pkt_out_enb"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7105,	2,	5183},
-	{"cvmx_sli_pkt_output_wmark"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7106,	2,	5185},
-	{"cvmx_sli_pkt_pcie_port"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7107,	1,	5187},
-	{"cvmx_sli_pkt_port_in_rst"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7108,	2,	5188},
-	{"cvmx_sli_pkt_slist_es"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7109,	1,	5190},
-	{"cvmx_sli_pkt_slist_ns"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7110,	2,	5191},
-	{"cvmx_sli_pkt_slist_ror"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7111,	2,	5193},
-	{"cvmx_sli_pkt_time_int"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7112,	2,	5195},
-	{"cvmx_sli_pkt_time_int_enb"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7113,	2,	5197},
-	{"cvmx_sli_s2m_port#_ctl"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7114,	4,	5199},
-	{"cvmx_sli_scratch_1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7116,	1,	5203},
-	{"cvmx_sli_scratch_2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7117,	1,	5204},
-	{"cvmx_sli_state1"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7118,	4,	5205},
-	{"cvmx_sli_state2"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7119,	8,	5209},
-	{"cvmx_sli_state3"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7120,	5,	5217},
-	{"cvmx_sli_win_rd_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7121,	4,	5222},
-	{"cvmx_sli_win_rd_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7122,	1,	5226},
-	{"cvmx_sli_win_wr_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7123,	4,	5227},
-	{"cvmx_sli_win_wr_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7124,	1,	5231},
-	{"cvmx_sli_win_wr_mask"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7125,	2,	5232},
-	{"cvmx_sli_window_ctl"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7126,	2,	5234},
-	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7127,	10,	5236},
-	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7129,	6,	5246},
-	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	7131,	2,	5252},
-	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7133,	4,	5254},
-	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7135,	4,	5258},
-	{"cvmx_smi_drv_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7137,	4,	5262},
-	{"cvmx_srio#_acc_ctrl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7138,	4,	5266},
-	{"cvmx_srio#_asmbly_id"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7140,	3,	5270},
-	{"cvmx_srio#_asmbly_info"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7142,	3,	5273},
-	{"cvmx_srio#_bell_resp_ctrl"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7144,	5,	5276},
-	{"cvmx_srio#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7146,	18,	5281},
-	{"cvmx_srio#_imsg_ctrl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7148,	14,	5299},
-	{"cvmx_srio#_imsg_inst_hdr#"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7150,	14,	5313},
-	{"cvmx_srio#_imsg_qos_grp#"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7154,	24,	5327},
-	{"cvmx_srio#_imsg_status#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7218,	24,	5351},
-	{"cvmx_srio#_imsg_vport_thr"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7266,	13,	5375},
-	{"cvmx_srio#_int_enable"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7268,	23,	5388},
-	{"cvmx_srio#_int_info0"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7270,	9,	5411},
-	{"cvmx_srio#_int_info1"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7272,	1,	5420},
-	{"cvmx_srio#_int_info2"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7274,	11,	5421},
-	{"cvmx_srio#_int_info3"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7276,	5,	5432},
-	{"cvmx_srio#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7278,	23,	5437},
-	{"cvmx_srio#_ip_feature"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7280,	9,	5460},
-	{"cvmx_srio#_maint_op"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7282,	6,	5469},
-	{"cvmx_srio#_maint_rd_data"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7284,	3,	5475},
-	{"cvmx_srio#_mce_tx_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7286,	2,	5478},
-	{"cvmx_srio#_mem_op_ctrl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7288,	8,	5480},
-	{"cvmx_srio#_omsg_ctrl#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7290,	10,	5488},
-	{"cvmx_srio#_omsg_fmp_mr#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7294,	16,	5498},
-	{"cvmx_srio#_omsg_nmp_mr#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7298,	16,	5514},
-	{"cvmx_srio#_omsg_port#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7302,	4,	5530},
-	{"cvmx_srio#_omsg_sp_mr#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7306,	17,	5534},
-	{"cvmx_srio#_rx_bell"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7310,	9,	5551},
-	{"cvmx_srio#_rx_bell_seq"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7312,	3,	5560},
-	{"cvmx_srio#_rx_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7314,	9,	5563},
-	{"cvmx_srio#_s2m_type#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7316,	11,	5572},
-	{"cvmx_srio#_seq"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	7348,	2,	5583},
-	{"cvmx_srio#_status_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7350,	3,	5585},
-	{"cvmx_srio#_tag_ctrl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7352,	6,	5588},
-	{"cvmx_srio#_tlp_credits"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7354,	6,	5594},
-	{"cvmx_srio#_tx_bell"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7356,	10,	5600},
-	{"cvmx_srio#_tx_bell_info"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7358,	11,	5610},
-	{"cvmx_srio#_tx_ctrl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7360,	12,	5621},
-	{"cvmx_srio#_tx_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7362,	5,	5633},
-	{"cvmx_sriomaint#_asmbly_id"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7364,	2,	5638},
-	{"cvmx_sriomaint#_asmbly_info" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7366,	2,	5640},
-	{"cvmx_sriomaint#_bar1_idx#"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7368,	7,	5642},
-	{"cvmx_sriomaint#_bell_status" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7400,	2,	5649},
-	{"cvmx_sriomaint#_comp_tag"    ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7402,	1,	5651},
-	{"cvmx_sriomaint#_core_enables",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7404,	6,	5652},
-	{"cvmx_sriomaint#_dev_id"      ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7406,	2,	5658},
-	{"cvmx_sriomaint#_dev_rev"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7408,	2,	5660},
-	{"cvmx_sriomaint#_dst_ops"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7410,	26,	5662},
-	{"cvmx_sriomaint#_erb_attr_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7412,	4,	5688},
-	{"cvmx_sriomaint#_erb_err_det" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7414,	14,	5692},
-	{"cvmx_sriomaint#_erb_err_rate",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7416,	5,	5706},
-	{"cvmx_sriomaint#_erb_err_rate_en",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7418,	14,	5711},
-	{"cvmx_sriomaint#_erb_err_rate_thr",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7420,	3,	5725},
-	{"cvmx_sriomaint#_erb_hdr"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7422,	2,	5728},
-	{"cvmx_sriomaint#_erb_lt_addr_capt_h",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7424,	1,	5730},
-	{"cvmx_sriomaint#_erb_lt_addr_capt_l",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7426,	3,	5731},
-	{"cvmx_sriomaint#_erb_lt_ctrl_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7428,	9,	5734},
-	{"cvmx_sriomaint#_erb_lt_dev_id",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7430,	4,	5743},
-	{"cvmx_sriomaint#_erb_lt_dev_id_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7432,	4,	5747},
-	{"cvmx_sriomaint#_erb_lt_err_det",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7434,	12,	5751},
-	{"cvmx_sriomaint#_erb_lt_err_en",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7436,	12,	5763},
-	{"cvmx_sriomaint#_erb_pack_capt_1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7438,	1,	5775},
-	{"cvmx_sriomaint#_erb_pack_capt_2",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7440,	1,	5776},
-	{"cvmx_sriomaint#_erb_pack_capt_3",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7442,	1,	5777},
-	{"cvmx_sriomaint#_erb_pack_sym_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7444,	1,	5778},
-	{"cvmx_sriomaint#_hb_dev_id_lock",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7446,	2,	5779},
-	{"cvmx_sriomaint#_ir_buffer_config",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7448,	7,	5781},
-	{"cvmx_sriomaint#_ir_pd_phy_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7450,	1,	5788},
-	{"cvmx_sriomaint#_ir_pd_phy_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7452,	9,	5789},
-	{"cvmx_sriomaint#_ir_pi_phy_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7454,	5,	5798},
-	{"cvmx_sriomaint#_ir_pi_phy_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7456,	2,	5803},
-	{"cvmx_sriomaint#_ir_sp_rx_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7458,	2,	5805},
-	{"cvmx_sriomaint#_ir_sp_rx_data",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7460,	1,	5807},
-	{"cvmx_sriomaint#_ir_sp_rx_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7462,	5,	5808},
-	{"cvmx_sriomaint#_ir_sp_tx_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7464,	2,	5813},
-	{"cvmx_sriomaint#_ir_sp_tx_data",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7466,	1,	5815},
-	{"cvmx_sriomaint#_ir_sp_tx_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7468,	5,	5816},
-	{"cvmx_sriomaint#_lane_#_status_0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7470,	15,	5821},
-	{"cvmx_sriomaint#_lcs_ba0"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7478,	2,	5836},
-	{"cvmx_sriomaint#_lcs_ba1"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7480,	2,	5838},
-	{"cvmx_sriomaint#_m2s_bar0_start0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7482,	2,	5840},
-	{"cvmx_sriomaint#_m2s_bar0_start1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7484,	4,	5842},
-	{"cvmx_sriomaint#_m2s_bar1_start0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7486,	2,	5846},
-	{"cvmx_sriomaint#_m2s_bar1_start1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7488,	5,	5848},
-	{"cvmx_sriomaint#_m2s_bar2_start",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7490,	7,	5853},
-	{"cvmx_sriomaint#_pe_feat"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7492,	11,	5860},
-	{"cvmx_sriomaint#_pe_llc"      ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7494,	2,	5871},
-	{"cvmx_sriomaint#_port_0_ctl"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7496,	18,	5873},
-	{"cvmx_sriomaint#_port_0_ctl2" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7498,	16,	5891},
-	{"cvmx_sriomaint#_port_0_err_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7500,	20,	5907},
-	{"cvmx_sriomaint#_port_gen_ctl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7502,	4,	5927},
-	{"cvmx_sriomaint#_port_lt_ctl" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7504,	2,	5931},
-	{"cvmx_sriomaint#_port_mbh0"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7506,	2,	5933},
-	{"cvmx_sriomaint#_port_rt_ctl" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7508,	2,	5935},
-	{"cvmx_sriomaint#_pri_dev_id"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7510,	3,	5937},
-	{"cvmx_sriomaint#_sec_dev_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7512,	3,	5940},
-	{"cvmx_sriomaint#_sec_dev_id"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7514,	3,	5943},
-	{"cvmx_sriomaint#_serial_lane_hdr",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7516,	2,	5946},
-	{"cvmx_sriomaint#_src_ops"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7518,	26,	5948},
-	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7520,	6,	5974},
-	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7521,	3,	5980},
-	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7522,	5,	5983},
-	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7523,	4,	5988},
-	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7524,	6,	5992},
-	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7525,	4,	5998},
-	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7526,	2,	6002},
-	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7527,	4,	6004},
-	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7528,	2,	6008},
-	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7529,	3,	6010},
-	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7530,	2,	6013},
-	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	7531,	13,	6015},
-	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7532,	3,	6028},
-	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7533,	5,	6031},
-	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7534,	2,	6036},
-	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7535,	2,	6038},
-	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7536,	57,	6040},
-	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7537,	20,	6097},
-	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7538,	7,	6117},
-	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7539,	5,	6124},
-	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7540,	1,	6129},
-	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7541,	2,	6130},
-	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7542,	2,	6132},
-	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7543,	57,	6134},
-	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7544,	20,	6191},
-	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7545,	7,	6211},
-	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7546,	2,	6218},
-	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7547,	2,	6220},
-	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7548,	57,	6222},
-	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7549,	20,	6279},
-	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7550,	7,	6299},
-	{"cvmx_uahc#_ehci_asynclistaddr",	CVMX_CSR_DB_TYPE_NCB,	32,	7551,	2,	6306},
-	{"cvmx_uahc#_ehci_configflag"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7552,	2,	6308},
-	{"cvmx_uahc#_ehci_ctrldssegment",	CVMX_CSR_DB_TYPE_NCB,	32,	7553,	1,	6310},
-	{"cvmx_uahc#_ehci_frindex"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7554,	2,	6311},
-	{"cvmx_uahc#_ehci_hccapbase"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7555,	3,	6313},
-	{"cvmx_uahc#_ehci_hccparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7556,	7,	6316},
-	{"cvmx_uahc#_ehci_hcsparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7557,	10,	6323},
-	{"cvmx_uahc#_ehci_insnreg00"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7558,	3,	6333},
-	{"cvmx_uahc#_ehci_insnreg03"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7559,	5,	6336},
-	{"cvmx_uahc#_ehci_insnreg04"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7560,	7,	6341},
-	{"cvmx_uahc#_ehci_insnreg06"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7561,	2,	6348},
-	{"cvmx_uahc#_ehci_insnreg07"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7562,	1,	6350},
-	{"cvmx_uahc#_ehci_periodiclistbase",	CVMX_CSR_DB_TYPE_NCB,	32,	7563,	2,	6351},
-	{"cvmx_uahc#_ehci_portsc#"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7564,	19,	6353},
-	{"cvmx_uahc#_ehci_usbcmd"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	7566,	13,	6372},
-	{"cvmx_uahc#_ehci_usbintr"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7567,	7,	6385},
-	{"cvmx_uahc#_ehci_usbsts"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	7568,	12,	6392},
-	{"cvmx_uahc#_ohci0_hcbulkcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7569,	2,	6404},
-	{"cvmx_uahc#_ohci0_hcbulkheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	7570,	2,	6406},
-	{"cvmx_uahc#_ohci0_hccommandstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	7571,	7,	6408},
-	{"cvmx_uahc#_ohci0_hccontrol"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7572,	10,	6415},
-	{"cvmx_uahc#_ohci0_hccontrolcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7573,	2,	6425},
-	{"cvmx_uahc#_ohci0_hccontrolheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	7574,	2,	6427},
-	{"cvmx_uahc#_ohci0_hcdonehead" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7575,	2,	6429},
-	{"cvmx_uahc#_ohci0_hcfminterval",	CVMX_CSR_DB_TYPE_NCB,	32,	7576,	4,	6431},
-	{"cvmx_uahc#_ohci0_hcfmnumber" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7577,	2,	6435},
-	{"cvmx_uahc#_ohci0_hcfmremaining",	CVMX_CSR_DB_TYPE_NCB,	32,	7578,	3,	6437},
-	{"cvmx_uahc#_ohci0_hchcca"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7579,	2,	6440},
-	{"cvmx_uahc#_ohci0_hcinterruptdisable",	CVMX_CSR_DB_TYPE_NCB,	32,	7580,	10,	6442},
-	{"cvmx_uahc#_ohci0_hcinterruptenable",	CVMX_CSR_DB_TYPE_NCB,	32,	7581,	10,	6452},
-	{"cvmx_uahc#_ohci0_hcinterruptstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	7582,	10,	6462},
-	{"cvmx_uahc#_ohci0_hclsthreshold",	CVMX_CSR_DB_TYPE_NCB,	32,	7583,	2,	6472},
-	{"cvmx_uahc#_ohci0_hcperiodcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7584,	2,	6474},
-	{"cvmx_uahc#_ohci0_hcperiodicstart",	CVMX_CSR_DB_TYPE_NCB,	32,	7585,	2,	6476},
-	{"cvmx_uahc#_ohci0_hcrevision" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7586,	2,	6478},
-	{"cvmx_uahc#_ohci0_hcrhdescriptora",	CVMX_CSR_DB_TYPE_NCB,	32,	7587,	8,	6480},
-	{"cvmx_uahc#_ohci0_hcrhdescriptorb",	CVMX_CSR_DB_TYPE_NCB,	32,	7588,	2,	6488},
-	{"cvmx_uahc#_ohci0_hcrhportstatus#",	CVMX_CSR_DB_TYPE_NCB,	32,	7589,	15,	6490},
-	{"cvmx_uahc#_ohci0_hcrhstatus" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7591,	8,	6505},
-	{"cvmx_uahc#_ohci0_insnreg06"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7592,	2,	6513},
-	{"cvmx_uahc#_ohci0_insnreg07"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7593,	1,	6515},
-	{"cvmx_uctl#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7594,	7,	6516},
-	{"cvmx_uctl#_clk_rst_ctl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7595,	21,	6523},
-	{"cvmx_uctl#_ehci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7596,	12,	6544},
-	{"cvmx_uctl#_ehci_fla"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7597,	2,	6556},
-	{"cvmx_uctl#_erto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7598,	3,	6558},
-	{"cvmx_uctl#_if_ena"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7599,	2,	6561},
-	{"cvmx_uctl#_int_ena"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7600,	9,	6563},
-	{"cvmx_uctl#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7601,	9,	6572},
-	{"cvmx_uctl#_ohci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7602,	11,	6581},
-	{"cvmx_uctl#_orto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7603,	3,	6592},
-	{"cvmx_uctl#_ppaf_wm"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7604,	2,	6595},
-	{"cvmx_uctl#_uphy_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	7605,	11,	6597},
-	{"cvmx_uctl#_uphy_port#_ctl_status",	CVMX_CSR_DB_TYPE_RSL,	64,	7606,	20,	6608},
-	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7608,	3,	6628},
-	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7609,	5,	6631},
-	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7610,	3,	6636},
-	{"cvmx_zip_constants"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7611,	6,	6639},
-	{"cvmx_zip_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	7612,	2,	6645},
-	{"cvmx_zip_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	7613,	2,	6647},
-	{"cvmx_zip_int_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7614,	2,	6649},
-	{"cvmx_zip_throttle"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7615,	2,	6651},
+	{"cvmx_pip_stat10_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6239,	2,	4426},
+	{"cvmx_pip_stat11_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6251,	2,	4428},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6263,	2,	4430},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6275,	2,	4432},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6287,	2,	4434},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6299,	2,	4436},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6311,	2,	4438},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6323,	2,	4440},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6335,	2,	4442},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6347,	2,	4444},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6359,	2,	4446},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6371,	2,	4448},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6372,	2,	4450},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6388,	2,	4452},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6404,	2,	4454},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6420,	2,	4456},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6484,	2,	4458},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6485,	3,	4460},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6486,	3,	4463},
+	{"cvmx_pip_xstat0_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6487,	2,	4466},
+	{"cvmx_pip_xstat10_prt#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6491,	2,	4468},
+	{"cvmx_pip_xstat11_prt#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6495,	2,	4470},
+	{"cvmx_pip_xstat1_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6499,	2,	4472},
+	{"cvmx_pip_xstat2_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6503,	2,	4474},
+	{"cvmx_pip_xstat3_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6507,	2,	4476},
+	{"cvmx_pip_xstat4_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6511,	2,	4478},
+	{"cvmx_pip_xstat5_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6515,	2,	4480},
+	{"cvmx_pip_xstat6_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6519,	2,	4482},
+	{"cvmx_pip_xstat7_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6523,	2,	4484},
+	{"cvmx_pip_xstat8_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6527,	2,	4486},
+	{"cvmx_pip_xstat9_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6531,	2,	4488},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6535,	2,	4490},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6536,	2,	4492},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6537,	4,	4494},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6538,	5,	4498},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6539,	4,	4503},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6540,	8,	4507},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6541,	4,	4515},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6542,	5,	4519},
+	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6543,	1,	4524},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6544,	5,	4525},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6545,	1,	4530},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6546,	13,	4531},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6547,	6,	4544},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6548,	13,	4550},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6549,	6,	4563},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6550,	9,	4569},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6551,	4,	4578},
+	{"cvmx_pko_mem_port_ptrs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6552,	7,	4582},
+	{"cvmx_pko_mem_port_qos"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6553,	5,	4589},
+	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6554,	5,	4594},
+	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6555,	4,	4599},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6556,	9,	4603},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6557,	5,	4612},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6558,	16,	4617},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6559,	4,	4633},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6560,	1,	4637},
+	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6561,	1,	4638},
+	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6562,	1,	4639},
+	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6563,	1,	4640},
+	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	6564,	13,	4641},
+	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6565,	2,	4654},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6566,	4,	4656},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6567,	5,	4660},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6568,	3,	4665},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6569,	4,	4668},
+	{"cvmx_pko_reg_preempt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6570,	2,	4672},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6571,	2,	4674},
+	{"cvmx_pko_reg_queue_preempt"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6572,	3,	4676},
+	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6573,	3,	4679},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6574,	3,	4682},
+	{"cvmx_pko_reg_timestamp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6575,	2,	4685},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6576,	10,	4687},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	6577,	2,	4697},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6578,	13,	4699},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6579,	3,	4712},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6580,	2,	4715},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	6588,	2,	4717},
+	{"cvmx_pow_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6589,	2,	4719},
+	{"cvmx_pow_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6590,	2,	4721},
+	{"cvmx_pow_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6591,	2,	4723},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6599,	2,	4725},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6600,	2,	4727},
+	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	6601,	2,	4729},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6602,	10,	4731},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	6608,	5,	4741},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	6616,	10,	4746},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	6624,	2,	4756},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6625,	2,	4758},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6626,	2,	4760},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6634,	3,	4762},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6635,	6,	4765},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6651,	5,	4771},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6652,	7,	4776},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6668,	2,	4783},
+	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6684,	1,	4785},
+	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6685,	1,	4786},
+	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6686,	1,	4787},
+	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6687,	5,	4788},
+	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6688,	5,	4793},
+	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6689,	4,	4798},
+	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6690,	10,	4802},
+	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6691,	1,	4812},
+	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6692,	3,	4813},
+	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6693,	7,	4816},
+	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6694,	2,	4823},
+	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6695,	1,	4825},
+	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6696,	1,	4826},
+	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6697,	1,	4827},
+	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6698,	18,	4828},
+	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6699,	3,	4846},
+	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6700,	2,	4849},
+	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6701,	3,	4851},
+	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6702,	7,	4854},
+	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6703,	2,	4861},
+	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6704,	2,	4863},
+	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6705,	2,	4865},
+	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6706,	3,	4867},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6707,	3,	4870},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6708,	9,	4873},
+	{"cvmx_rnm_eer_dbg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6709,	1,	4882},
+	{"cvmx_rnm_eer_key"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6710,	1,	4883},
+	{"cvmx_sli_bist_status"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6711,	25,	4884},
+	{"cvmx_sli_ctl_port#"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6712,	16,	4909},
+	{"cvmx_sli_ctl_status"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6714,	4,	4925},
+	{"cvmx_sli_data_out_cnt"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6715,	5,	4929},
+	{"cvmx_sli_dbg_data"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6716,	3,	4934},
+	{"cvmx_sli_dbg_select"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6717,	3,	4937},
+	{"cvmx_sli_dma#_cnt"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6718,	2,	4940},
+	{"cvmx_sli_dma#_int_level"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6720,	2,	4942},
+	{"cvmx_sli_dma#_tim"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6722,	2,	4944},
+	{"cvmx_sli_int_enb_ciu"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6724,	35,	4946},
+	{"cvmx_sli_int_enb_port#"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6725,	37,	4981},
+	{"cvmx_sli_int_sum"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6727,	37,	5018},
+	{"cvmx_sli_last_win_rdata0"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6728,	1,	5055},
+	{"cvmx_sli_last_win_rdata1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6729,	1,	5056},
+	{"cvmx_sli_mac_credit_cnt"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6730,	7,	5057},
+	{"cvmx_sli_mem_access_ctl"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6731,	3,	5064},
+	{"cvmx_sli_mem_access_subid#"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6732,	9,	5067},
+	{"cvmx_sli_msi_enb0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6748,	1,	5076},
+	{"cvmx_sli_msi_enb1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6749,	1,	5077},
+	{"cvmx_sli_msi_enb2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6750,	1,	5078},
+	{"cvmx_sli_msi_enb3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6751,	1,	5079},
+	{"cvmx_sli_msi_rcv0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6752,	1,	5080},
+	{"cvmx_sli_msi_rcv1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6753,	1,	5081},
+	{"cvmx_sli_msi_rcv2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6754,	1,	5082},
+	{"cvmx_sli_msi_rcv3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6755,	1,	5083},
+	{"cvmx_sli_msi_rd_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6756,	3,	5084},
+	{"cvmx_sli_msi_w1c_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6757,	1,	5087},
+	{"cvmx_sli_msi_w1c_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6758,	1,	5088},
+	{"cvmx_sli_msi_w1c_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6759,	1,	5089},
+	{"cvmx_sli_msi_w1c_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6760,	1,	5090},
+	{"cvmx_sli_msi_w1s_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6761,	1,	5091},
+	{"cvmx_sli_msi_w1s_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6762,	1,	5092},
+	{"cvmx_sli_msi_w1s_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6763,	1,	5093},
+	{"cvmx_sli_msi_w1s_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6764,	1,	5094},
+	{"cvmx_sli_msi_wr_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6765,	3,	5095},
+	{"cvmx_sli_pcie_msi_rcv"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6766,	2,	5098},
+	{"cvmx_sli_pcie_msi_rcv_b1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6767,	3,	5100},
+	{"cvmx_sli_pcie_msi_rcv_b2"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6768,	3,	5103},
+	{"cvmx_sli_pcie_msi_rcv_b3"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6769,	3,	5106},
+	{"cvmx_sli_pkt#_cnts"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6770,	3,	5109},
+	{"cvmx_sli_pkt#_in_bp"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6802,	2,	5112},
+	{"cvmx_sli_pkt#_instr_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6834,	2,	5114},
+	{"cvmx_sli_pkt#_instr_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6866,	2,	5116},
+	{"cvmx_sli_pkt#_instr_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6898,	5,	5118},
+	{"cvmx_sli_pkt#_instr_header"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6930,	21,	5123},
+	{"cvmx_sli_pkt#_out_size"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6962,	3,	5144},
+	{"cvmx_sli_pkt#_slist_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6994,	2,	5147},
+	{"cvmx_sli_pkt#_slist_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7026,	2,	5149},
+	{"cvmx_sli_pkt#_slist_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7058,	2,	5151},
+	{"cvmx_sli_pkt_cnt_int"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7090,	2,	5153},
+	{"cvmx_sli_pkt_cnt_int_enb"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7091,	2,	5155},
+	{"cvmx_sli_pkt_ctl"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7092,	3,	5157},
+	{"cvmx_sli_pkt_data_out_es"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7093,	1,	5160},
+	{"cvmx_sli_pkt_data_out_ns"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7094,	2,	5161},
+	{"cvmx_sli_pkt_data_out_ror"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7095,	2,	5163},
+	{"cvmx_sli_pkt_dpaddr"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7096,	2,	5165},
+	{"cvmx_sli_pkt_in_bp"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7097,	2,	5167},
+	{"cvmx_sli_pkt_in_done#_cnts"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7098,	2,	5169},
+	{"cvmx_sli_pkt_in_instr_counts",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7130,	2,	5171},
+	{"cvmx_sli_pkt_in_pcie_port"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7131,	1,	5173},
+	{"cvmx_sli_pkt_input_control"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7132,	10,	5174},
+	{"cvmx_sli_pkt_instr_enb"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7133,	2,	5184},
+	{"cvmx_sli_pkt_instr_rd_size"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7134,	1,	5186},
+	{"cvmx_sli_pkt_instr_size"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7135,	2,	5187},
+	{"cvmx_sli_pkt_int_levels"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7136,	3,	5189},
+	{"cvmx_sli_pkt_iptr"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7137,	2,	5192},
+	{"cvmx_sli_pkt_out_bmode"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7138,	2,	5194},
+	{"cvmx_sli_pkt_out_enb"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7139,	2,	5196},
+	{"cvmx_sli_pkt_output_wmark"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7140,	2,	5198},
+	{"cvmx_sli_pkt_pcie_port"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7141,	1,	5200},
+	{"cvmx_sli_pkt_port_in_rst"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7142,	2,	5201},
+	{"cvmx_sli_pkt_slist_es"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7143,	1,	5203},
+	{"cvmx_sli_pkt_slist_ns"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7144,	2,	5204},
+	{"cvmx_sli_pkt_slist_ror"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7145,	2,	5206},
+	{"cvmx_sli_pkt_time_int"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7146,	2,	5208},
+	{"cvmx_sli_pkt_time_int_enb"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7147,	2,	5210},
+	{"cvmx_sli_s2m_port#_ctl"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7148,	4,	5212},
+	{"cvmx_sli_scratch_1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7150,	1,	5216},
+	{"cvmx_sli_scratch_2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7151,	1,	5217},
+	{"cvmx_sli_state1"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7152,	4,	5218},
+	{"cvmx_sli_state2"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7153,	8,	5222},
+	{"cvmx_sli_state3"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7154,	5,	5230},
+	{"cvmx_sli_win_rd_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7155,	4,	5235},
+	{"cvmx_sli_win_rd_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7156,	1,	5239},
+	{"cvmx_sli_win_wr_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7157,	4,	5240},
+	{"cvmx_sli_win_wr_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7158,	1,	5244},
+	{"cvmx_sli_win_wr_mask"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7159,	2,	5245},
+	{"cvmx_sli_window_ctl"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7160,	2,	5247},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7161,	10,	5249},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7163,	6,	5259},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	7165,	2,	5265},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7167,	4,	5267},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7169,	4,	5271},
+	{"cvmx_smi_drv_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7171,	4,	5275},
+	{"cvmx_srio#_acc_ctrl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7172,	4,	5279},
+	{"cvmx_srio#_asmbly_id"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7174,	3,	5283},
+	{"cvmx_srio#_asmbly_info"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7176,	3,	5286},
+	{"cvmx_srio#_bell_resp_ctrl"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7178,	5,	5289},
+	{"cvmx_srio#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7180,	18,	5294},
+	{"cvmx_srio#_imsg_ctrl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7182,	14,	5312},
+	{"cvmx_srio#_imsg_inst_hdr#"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7184,	14,	5326},
+	{"cvmx_srio#_imsg_qos_grp#"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7188,	24,	5340},
+	{"cvmx_srio#_imsg_status#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7252,	24,	5364},
+	{"cvmx_srio#_imsg_vport_thr"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7300,	13,	5388},
+	{"cvmx_srio#_int_enable"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7302,	23,	5401},
+	{"cvmx_srio#_int_info0"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7304,	9,	5424},
+	{"cvmx_srio#_int_info1"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7306,	1,	5433},
+	{"cvmx_srio#_int_info2"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7308,	11,	5434},
+	{"cvmx_srio#_int_info3"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7310,	5,	5445},
+	{"cvmx_srio#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7312,	23,	5450},
+	{"cvmx_srio#_ip_feature"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7314,	9,	5473},
+	{"cvmx_srio#_maint_op"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7316,	6,	5482},
+	{"cvmx_srio#_maint_rd_data"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7318,	3,	5488},
+	{"cvmx_srio#_mce_tx_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7320,	2,	5491},
+	{"cvmx_srio#_mem_op_ctrl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7322,	8,	5493},
+	{"cvmx_srio#_omsg_ctrl#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7324,	10,	5501},
+	{"cvmx_srio#_omsg_fmp_mr#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7328,	16,	5511},
+	{"cvmx_srio#_omsg_nmp_mr#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7332,	16,	5527},
+	{"cvmx_srio#_omsg_port#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7336,	4,	5543},
+	{"cvmx_srio#_omsg_sp_mr#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7340,	17,	5547},
+	{"cvmx_srio#_rx_bell"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7344,	9,	5564},
+	{"cvmx_srio#_rx_bell_seq"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7346,	3,	5573},
+	{"cvmx_srio#_rx_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7348,	9,	5576},
+	{"cvmx_srio#_s2m_type#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7350,	11,	5585},
+	{"cvmx_srio#_seq"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	7382,	2,	5596},
+	{"cvmx_srio#_status_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7384,	3,	5598},
+	{"cvmx_srio#_tag_ctrl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7386,	6,	5601},
+	{"cvmx_srio#_tlp_credits"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7388,	6,	5607},
+	{"cvmx_srio#_tx_bell"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7390,	10,	5613},
+	{"cvmx_srio#_tx_bell_info"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7392,	11,	5623},
+	{"cvmx_srio#_tx_ctrl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7394,	12,	5634},
+	{"cvmx_srio#_tx_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7396,	5,	5646},
+	{"cvmx_sriomaint#_asmbly_id"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7398,	2,	5651},
+	{"cvmx_sriomaint#_asmbly_info" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7400,	2,	5653},
+	{"cvmx_sriomaint#_bar1_idx#"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7402,	7,	5655},
+	{"cvmx_sriomaint#_bell_status" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7434,	2,	5662},
+	{"cvmx_sriomaint#_comp_tag"    ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7436,	1,	5664},
+	{"cvmx_sriomaint#_core_enables",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7438,	6,	5665},
+	{"cvmx_sriomaint#_dev_id"      ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7440,	2,	5671},
+	{"cvmx_sriomaint#_dev_rev"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7442,	2,	5673},
+	{"cvmx_sriomaint#_dst_ops"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7444,	26,	5675},
+	{"cvmx_sriomaint#_erb_attr_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7446,	4,	5701},
+	{"cvmx_sriomaint#_erb_err_det" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7448,	14,	5705},
+	{"cvmx_sriomaint#_erb_err_rate",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7450,	5,	5719},
+	{"cvmx_sriomaint#_erb_err_rate_en",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7452,	14,	5724},
+	{"cvmx_sriomaint#_erb_err_rate_thr",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7454,	3,	5738},
+	{"cvmx_sriomaint#_erb_hdr"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7456,	2,	5741},
+	{"cvmx_sriomaint#_erb_lt_addr_capt_h",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7458,	1,	5743},
+	{"cvmx_sriomaint#_erb_lt_addr_capt_l",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7460,	3,	5744},
+	{"cvmx_sriomaint#_erb_lt_ctrl_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7462,	9,	5747},
+	{"cvmx_sriomaint#_erb_lt_dev_id",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7464,	4,	5756},
+	{"cvmx_sriomaint#_erb_lt_dev_id_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7466,	4,	5760},
+	{"cvmx_sriomaint#_erb_lt_err_det",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7468,	12,	5764},
+	{"cvmx_sriomaint#_erb_lt_err_en",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7470,	12,	5776},
+	{"cvmx_sriomaint#_erb_pack_capt_1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7472,	1,	5788},
+	{"cvmx_sriomaint#_erb_pack_capt_2",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7474,	1,	5789},
+	{"cvmx_sriomaint#_erb_pack_capt_3",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7476,	1,	5790},
+	{"cvmx_sriomaint#_erb_pack_sym_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7478,	1,	5791},
+	{"cvmx_sriomaint#_hb_dev_id_lock",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7480,	2,	5792},
+	{"cvmx_sriomaint#_ir_buffer_config",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7482,	7,	5794},
+	{"cvmx_sriomaint#_ir_pd_phy_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7484,	1,	5801},
+	{"cvmx_sriomaint#_ir_pd_phy_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7486,	9,	5802},
+	{"cvmx_sriomaint#_ir_pi_phy_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7488,	5,	5811},
+	{"cvmx_sriomaint#_ir_pi_phy_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7490,	2,	5816},
+	{"cvmx_sriomaint#_ir_sp_rx_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7492,	2,	5818},
+	{"cvmx_sriomaint#_ir_sp_rx_data",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7494,	1,	5820},
+	{"cvmx_sriomaint#_ir_sp_rx_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7496,	5,	5821},
+	{"cvmx_sriomaint#_ir_sp_tx_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7498,	2,	5826},
+	{"cvmx_sriomaint#_ir_sp_tx_data",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7500,	1,	5828},
+	{"cvmx_sriomaint#_ir_sp_tx_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7502,	5,	5829},
+	{"cvmx_sriomaint#_lane_#_status_0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7504,	15,	5834},
+	{"cvmx_sriomaint#_lcs_ba0"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7512,	2,	5849},
+	{"cvmx_sriomaint#_lcs_ba1"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7514,	2,	5851},
+	{"cvmx_sriomaint#_m2s_bar0_start0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7516,	2,	5853},
+	{"cvmx_sriomaint#_m2s_bar0_start1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7518,	4,	5855},
+	{"cvmx_sriomaint#_m2s_bar1_start0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7520,	2,	5859},
+	{"cvmx_sriomaint#_m2s_bar1_start1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7522,	5,	5861},
+	{"cvmx_sriomaint#_m2s_bar2_start",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7524,	7,	5866},
+	{"cvmx_sriomaint#_pe_feat"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7526,	11,	5873},
+	{"cvmx_sriomaint#_pe_llc"      ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7528,	2,	5884},
+	{"cvmx_sriomaint#_port_0_ctl"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7530,	18,	5886},
+	{"cvmx_sriomaint#_port_0_ctl2" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7532,	16,	5904},
+	{"cvmx_sriomaint#_port_0_err_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7534,	20,	5920},
+	{"cvmx_sriomaint#_port_gen_ctl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7536,	4,	5940},
+	{"cvmx_sriomaint#_port_lt_ctl" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7538,	2,	5944},
+	{"cvmx_sriomaint#_port_mbh0"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7540,	2,	5946},
+	{"cvmx_sriomaint#_port_rt_ctl" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7542,	2,	5948},
+	{"cvmx_sriomaint#_pri_dev_id"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7544,	3,	5950},
+	{"cvmx_sriomaint#_sec_dev_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7546,	3,	5953},
+	{"cvmx_sriomaint#_sec_dev_id"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7548,	3,	5956},
+	{"cvmx_sriomaint#_serial_lane_hdr",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7550,	2,	5959},
+	{"cvmx_sriomaint#_src_ops"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7552,	26,	5961},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7554,	6,	5987},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7555,	3,	5993},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7556,	5,	5996},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7557,	4,	6001},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7558,	6,	6005},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7559,	4,	6011},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7560,	2,	6015},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7561,	4,	6017},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7562,	2,	6021},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7563,	3,	6023},
+	{"cvmx_tra#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7564,	2,	6026},
+	{"cvmx_tra#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7565,	13,	6028},
+	{"cvmx_tra#_cycles_since"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7566,	3,	6041},
+	{"cvmx_tra#_cycles_since1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7567,	5,	6044},
+	{"cvmx_tra#_filt_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7568,	2,	6049},
+	{"cvmx_tra#_filt_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7569,	2,	6051},
+	{"cvmx_tra#_filt_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7570,	57,	6053},
+	{"cvmx_tra#_filt_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7571,	20,	6110},
+	{"cvmx_tra#_filt_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7572,	7,	6130},
+	{"cvmx_tra#_int_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7573,	5,	6137},
+	{"cvmx_tra#_read_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7574,	1,	6142},
+	{"cvmx_tra#_trig0_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7575,	2,	6143},
+	{"cvmx_tra#_trig0_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7576,	2,	6145},
+	{"cvmx_tra#_trig0_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7577,	57,	6147},
+	{"cvmx_tra#_trig0_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7578,	20,	6204},
+	{"cvmx_tra#_trig0_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7579,	7,	6224},
+	{"cvmx_tra#_trig1_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7580,	2,	6231},
+	{"cvmx_tra#_trig1_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7581,	2,	6233},
+	{"cvmx_tra#_trig1_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7582,	57,	6235},
+	{"cvmx_tra#_trig1_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7583,	20,	6292},
+	{"cvmx_tra#_trig1_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7584,	7,	6312},
+	{"cvmx_uahc#_ehci_asynclistaddr",	CVMX_CSR_DB_TYPE_NCB,	32,	7585,	2,	6319},
+	{"cvmx_uahc#_ehci_configflag"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7586,	2,	6321},
+	{"cvmx_uahc#_ehci_ctrldssegment",	CVMX_CSR_DB_TYPE_NCB,	32,	7587,	1,	6323},
+	{"cvmx_uahc#_ehci_frindex"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7588,	2,	6324},
+	{"cvmx_uahc#_ehci_hccapbase"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7589,	3,	6326},
+	{"cvmx_uahc#_ehci_hccparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7590,	7,	6329},
+	{"cvmx_uahc#_ehci_hcsparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7591,	10,	6336},
+	{"cvmx_uahc#_ehci_insnreg00"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7592,	3,	6346},
+	{"cvmx_uahc#_ehci_insnreg03"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7593,	5,	6349},
+	{"cvmx_uahc#_ehci_insnreg04"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7594,	7,	6354},
+	{"cvmx_uahc#_ehci_insnreg06"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7595,	2,	6361},
+	{"cvmx_uahc#_ehci_insnreg07"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7596,	1,	6363},
+	{"cvmx_uahc#_ehci_periodiclistbase",	CVMX_CSR_DB_TYPE_NCB,	32,	7597,	2,	6364},
+	{"cvmx_uahc#_ehci_portsc#"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7598,	19,	6366},
+	{"cvmx_uahc#_ehci_usbcmd"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	7600,	13,	6385},
+	{"cvmx_uahc#_ehci_usbintr"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7601,	7,	6398},
+	{"cvmx_uahc#_ehci_usbsts"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	7602,	12,	6405},
+	{"cvmx_uahc#_ohci0_hcbulkcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7603,	2,	6417},
+	{"cvmx_uahc#_ohci0_hcbulkheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	7604,	2,	6419},
+	{"cvmx_uahc#_ohci0_hccommandstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	7605,	7,	6421},
+	{"cvmx_uahc#_ohci0_hccontrol"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7606,	10,	6428},
+	{"cvmx_uahc#_ohci0_hccontrolcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7607,	2,	6438},
+	{"cvmx_uahc#_ohci0_hccontrolheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	7608,	2,	6440},
+	{"cvmx_uahc#_ohci0_hcdonehead" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7609,	2,	6442},
+	{"cvmx_uahc#_ohci0_hcfminterval",	CVMX_CSR_DB_TYPE_NCB,	32,	7610,	4,	6444},
+	{"cvmx_uahc#_ohci0_hcfmnumber" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7611,	2,	6448},
+	{"cvmx_uahc#_ohci0_hcfmremaining",	CVMX_CSR_DB_TYPE_NCB,	32,	7612,	3,	6450},
+	{"cvmx_uahc#_ohci0_hchcca"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7613,	2,	6453},
+	{"cvmx_uahc#_ohci0_hcinterruptdisable",	CVMX_CSR_DB_TYPE_NCB,	32,	7614,	10,	6455},
+	{"cvmx_uahc#_ohci0_hcinterruptenable",	CVMX_CSR_DB_TYPE_NCB,	32,	7615,	10,	6465},
+	{"cvmx_uahc#_ohci0_hcinterruptstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	7616,	10,	6475},
+	{"cvmx_uahc#_ohci0_hclsthreshold",	CVMX_CSR_DB_TYPE_NCB,	32,	7617,	2,	6485},
+	{"cvmx_uahc#_ohci0_hcperiodcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7618,	2,	6487},
+	{"cvmx_uahc#_ohci0_hcperiodicstart",	CVMX_CSR_DB_TYPE_NCB,	32,	7619,	2,	6489},
+	{"cvmx_uahc#_ohci0_hcrevision" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7620,	2,	6491},
+	{"cvmx_uahc#_ohci0_hcrhdescriptora",	CVMX_CSR_DB_TYPE_NCB,	32,	7621,	8,	6493},
+	{"cvmx_uahc#_ohci0_hcrhdescriptorb",	CVMX_CSR_DB_TYPE_NCB,	32,	7622,	2,	6501},
+	{"cvmx_uahc#_ohci0_hcrhportstatus#",	CVMX_CSR_DB_TYPE_NCB,	32,	7623,	15,	6503},
+	{"cvmx_uahc#_ohci0_hcrhstatus" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7625,	8,	6518},
+	{"cvmx_uahc#_ohci0_insnreg06"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7626,	2,	6526},
+	{"cvmx_uahc#_ohci0_insnreg07"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7627,	1,	6528},
+	{"cvmx_uctl#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7628,	7,	6529},
+	{"cvmx_uctl#_clk_rst_ctl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7629,	21,	6536},
+	{"cvmx_uctl#_ehci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7630,	12,	6557},
+	{"cvmx_uctl#_ehci_fla"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7631,	2,	6569},
+	{"cvmx_uctl#_erto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7632,	3,	6571},
+	{"cvmx_uctl#_if_ena"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7633,	2,	6574},
+	{"cvmx_uctl#_int_ena"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7634,	9,	6576},
+	{"cvmx_uctl#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7635,	9,	6585},
+	{"cvmx_uctl#_ohci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7636,	11,	6594},
+	{"cvmx_uctl#_orto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7637,	3,	6605},
+	{"cvmx_uctl#_ppaf_wm"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7638,	2,	6608},
+	{"cvmx_uctl#_uphy_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	7639,	11,	6610},
+	{"cvmx_uctl#_uphy_port#_ctl_status",	CVMX_CSR_DB_TYPE_RSL,	64,	7640,	20,	6621},
+	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7642,	3,	6641},
+	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7643,	5,	6644},
+	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7644,	3,	6649},
+	{"cvmx_zip_constants"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7645,	6,	6652},
+	{"cvmx_zip_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	7646,	2,	6658},
+	{"cvmx_zip_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	7647,	2,	6660},
+	{"cvmx_zip_int_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7648,	2,	6662},
+	{"cvmx_zip_throttle"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7649,	2,	6664},
 	{NULL,0,0,0,0,0}
 };
 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn63xxp1[] = {
@@ -75850,8 +90866,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn63xxp1[] = {
 	{"DPI_REQ_GBL_EN"              ,	   0x1df0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	187},
 	{"DPI_SLI_PRT0_CFG"            ,	   0x1df0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
 	{"DPI_SLI_PRT1_CFG"            ,	   0x1df0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
-	{"DPI_SLI_PRT0_ERR"            ,	   0x1df0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
-	{"DPI_SLI_PRT1_ERR"            ,	   0x1df0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"DPI_SLI_PRT0_ERR"            ,	   0x1df0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"DPI_SLI_PRT1_ERR"            ,	   0x1df0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
 	{"DPI_SLI_PRT0_ERR_INFO"       ,	   0x1df0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
 	{"DPI_SLI_PRT1_ERR_INFO"       ,	   0x1df0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
 	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
@@ -81640,1383 +96656,1417 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn63xxp1[] = {
 	{"PIP_STAT0_PRT37"             ,	   0x11800a0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
 	{"PIP_STAT0_PRT38"             ,	   0x11800a00013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
 	{"PIP_STAT0_PRT39"             ,	   0x11800a0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
-	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT1_PRT3"              ,	   0x11800a00008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT1_PRT32"             ,	   0x11800a0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT1_PRT33"             ,	   0x11800a0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT1_PRT34"             ,	   0x11800a00012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT1_PRT35"             ,	   0x11800a00012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT1_PRT36"             ,	   0x11800a0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT1_PRT37"             ,	   0x11800a0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT1_PRT38"             ,	   0x11800a00013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT1_PRT39"             ,	   0x11800a0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT2_PRT3"              ,	   0x11800a0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT2_PRT32"             ,	   0x11800a0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT2_PRT33"             ,	   0x11800a0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT2_PRT34"             ,	   0x11800a00012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT2_PRT35"             ,	   0x11800a0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT2_PRT36"             ,	   0x11800a0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT2_PRT37"             ,	   0x11800a00013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT2_PRT38"             ,	   0x11800a00013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT2_PRT39"             ,	   0x11800a0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT3_PRT3"              ,	   0x11800a0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT3_PRT32"             ,	   0x11800a0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT3_PRT33"             ,	   0x11800a0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT3_PRT34"             ,	   0x11800a00012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT3_PRT35"             ,	   0x11800a0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT3_PRT36"             ,	   0x11800a0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT3_PRT37"             ,	   0x11800a00013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT3_PRT38"             ,	   0x11800a00013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT3_PRT39"             ,	   0x11800a0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_STAT4_PRT3"              ,	   0x11800a0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_STAT4_PRT32"             ,	   0x11800a0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_STAT4_PRT33"             ,	   0x11800a0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_STAT4_PRT34"             ,	   0x11800a00012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_STAT4_PRT35"             ,	   0x11800a0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_STAT4_PRT36"             ,	   0x11800a0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_STAT4_PRT37"             ,	   0x11800a00013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_STAT4_PRT38"             ,	   0x11800a0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_STAT4_PRT39"             ,	   0x11800a0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
-	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
-	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
-	{"PIP_STAT5_PRT3"              ,	   0x11800a0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
-	{"PIP_STAT5_PRT32"             ,	   0x11800a0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
-	{"PIP_STAT5_PRT33"             ,	   0x11800a0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
-	{"PIP_STAT5_PRT34"             ,	   0x11800a00012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
-	{"PIP_STAT5_PRT35"             ,	   0x11800a0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
-	{"PIP_STAT5_PRT36"             ,	   0x11800a0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
-	{"PIP_STAT5_PRT37"             ,	   0x11800a00013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
-	{"PIP_STAT5_PRT38"             ,	   0x11800a0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
-	{"PIP_STAT5_PRT39"             ,	   0x11800a0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
-	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
-	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
-	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
-	{"PIP_STAT6_PRT3"              ,	   0x11800a0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
-	{"PIP_STAT6_PRT32"             ,	   0x11800a0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
-	{"PIP_STAT6_PRT33"             ,	   0x11800a0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
-	{"PIP_STAT6_PRT34"             ,	   0x11800a00012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
-	{"PIP_STAT6_PRT35"             ,	   0x11800a0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
-	{"PIP_STAT6_PRT36"             ,	   0x11800a0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
-	{"PIP_STAT6_PRT37"             ,	   0x11800a00013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
-	{"PIP_STAT6_PRT38"             ,	   0x11800a0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
-	{"PIP_STAT6_PRT39"             ,	   0x11800a0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
-	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
-	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
-	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
-	{"PIP_STAT7_PRT3"              ,	   0x11800a0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
-	{"PIP_STAT7_PRT32"             ,	   0x11800a0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
-	{"PIP_STAT7_PRT33"             ,	   0x11800a0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
-	{"PIP_STAT7_PRT34"             ,	   0x11800a00012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
-	{"PIP_STAT7_PRT35"             ,	   0x11800a0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
-	{"PIP_STAT7_PRT36"             ,	   0x11800a0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
-	{"PIP_STAT7_PRT37"             ,	   0x11800a00013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
-	{"PIP_STAT7_PRT38"             ,	   0x11800a0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
-	{"PIP_STAT7_PRT39"             ,	   0x11800a0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
-	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
-	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
-	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
-	{"PIP_STAT8_PRT3"              ,	   0x11800a0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
-	{"PIP_STAT8_PRT32"             ,	   0x11800a0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
-	{"PIP_STAT8_PRT33"             ,	   0x11800a0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
-	{"PIP_STAT8_PRT34"             ,	   0x11800a00012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
-	{"PIP_STAT8_PRT35"             ,	   0x11800a0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
-	{"PIP_STAT8_PRT36"             ,	   0x11800a0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
-	{"PIP_STAT8_PRT37"             ,	   0x11800a00013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
-	{"PIP_STAT8_PRT38"             ,	   0x11800a0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
-	{"PIP_STAT8_PRT39"             ,	   0x11800a0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
-	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT9_PRT3"              ,	   0x11800a0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT9_PRT32"             ,	   0x11800a0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT9_PRT33"             ,	   0x11800a0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT9_PRT34"             ,	   0x11800a00012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT9_PRT35"             ,	   0x11800a0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT9_PRT36"             ,	   0x11800a0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT9_PRT37"             ,	   0x11800a00013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT9_PRT38"             ,	   0x11800a0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT9_PRT39"             ,	   0x11800a0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
-	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT_INB_ERRS3"          ,	   0x11800a0001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT_INB_ERRS32"         ,	   0x11800a0001e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT_INB_ERRS33"         ,	   0x11800a0001e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT_INB_ERRS34"         ,	   0x11800a0001e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT_INB_ERRS35"         ,	   0x11800a0001e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT_INB_ERRS36"         ,	   0x11800a0001e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT_INB_ERRS37"         ,	   0x11800a0001eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT_INB_ERRS38"         ,	   0x11800a0001ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT_INB_ERRS39"         ,	   0x11800a0001ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT_INB_ERRS40"         ,	   0x11800a0001f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT_INB_ERRS41"         ,	   0x11800a0001f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT_INB_ERRS42"         ,	   0x11800a0001f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT_INB_ERRS43"         ,	   0x11800a0001f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT_INB_OCTS3"          ,	   0x11800a0001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT_INB_OCTS32"         ,	   0x11800a0001e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT_INB_OCTS33"         ,	   0x11800a0001e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT_INB_OCTS34"         ,	   0x11800a0001e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT_INB_OCTS35"         ,	   0x11800a0001e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT_INB_OCTS36"         ,	   0x11800a0001e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT_INB_OCTS37"         ,	   0x11800a0001ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT_INB_OCTS38"         ,	   0x11800a0001ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT_INB_OCTS39"         ,	   0x11800a0001ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT_INB_OCTS40"         ,	   0x11800a0001f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT_INB_OCTS41"         ,	   0x11800a0001f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT_INB_OCTS42"         ,	   0x11800a0001f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT_INB_OCTS43"         ,	   0x11800a0001f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT_INB_PKTS3"          ,	   0x11800a0001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT_INB_PKTS32"         ,	   0x11800a0001e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT_INB_PKTS33"         ,	   0x11800a0001e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT_INB_PKTS34"         ,	   0x11800a0001e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT_INB_PKTS35"         ,	   0x11800a0001e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT_INB_PKTS36"         ,	   0x11800a0001e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT_INB_PKTS37"         ,	   0x11800a0001ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT_INB_PKTS38"         ,	   0x11800a0001ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT_INB_PKTS39"         ,	   0x11800a0001ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT_INB_PKTS40"         ,	   0x11800a0001f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT_INB_PKTS41"         ,	   0x11800a0001f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT_INB_PKTS42"         ,	   0x11800a0001f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT_INB_PKTS43"         ,	   0x11800a0001f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
-	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
-	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
-	{"PIP_XSTAT0_PRT40"            ,	   0x11800a0002000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
-	{"PIP_XSTAT0_PRT41"            ,	   0x11800a0002050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
-	{"PIP_XSTAT0_PRT42"            ,	   0x11800a00020a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
-	{"PIP_XSTAT0_PRT43"            ,	   0x11800a00020f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
-	{"PIP_XSTAT1_PRT40"            ,	   0x11800a0002008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_XSTAT1_PRT41"            ,	   0x11800a0002058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_XSTAT1_PRT42"            ,	   0x11800a00020a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_XSTAT1_PRT43"            ,	   0x11800a00020f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_XSTAT2_PRT40"            ,	   0x11800a0002010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_XSTAT2_PRT41"            ,	   0x11800a0002060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_XSTAT2_PRT42"            ,	   0x11800a00020b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_XSTAT2_PRT43"            ,	   0x11800a0002100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_XSTAT3_PRT40"            ,	   0x11800a0002018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_XSTAT3_PRT41"            ,	   0x11800a0002068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_XSTAT3_PRT42"            ,	   0x11800a00020b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_XSTAT3_PRT43"            ,	   0x11800a0002108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_XSTAT4_PRT40"            ,	   0x11800a0002020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_XSTAT4_PRT41"            ,	   0x11800a0002070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_XSTAT4_PRT42"            ,	   0x11800a00020c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_XSTAT4_PRT43"            ,	   0x11800a0002110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_XSTAT5_PRT40"            ,	   0x11800a0002028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
-	{"PIP_XSTAT5_PRT41"            ,	   0x11800a0002078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
-	{"PIP_XSTAT5_PRT42"            ,	   0x11800a00020c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
-	{"PIP_XSTAT5_PRT43"            ,	   0x11800a0002118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
-	{"PIP_XSTAT6_PRT40"            ,	   0x11800a0002030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
-	{"PIP_XSTAT6_PRT41"            ,	   0x11800a0002080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
-	{"PIP_XSTAT6_PRT42"            ,	   0x11800a00020d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
-	{"PIP_XSTAT6_PRT43"            ,	   0x11800a0002120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
-	{"PIP_XSTAT7_PRT40"            ,	   0x11800a0002038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
-	{"PIP_XSTAT7_PRT41"            ,	   0x11800a0002088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
-	{"PIP_XSTAT7_PRT42"            ,	   0x11800a00020d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
-	{"PIP_XSTAT7_PRT43"            ,	   0x11800a0002128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
-	{"PIP_XSTAT8_PRT40"            ,	   0x11800a0002040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
-	{"PIP_XSTAT8_PRT41"            ,	   0x11800a0002090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
-	{"PIP_XSTAT8_PRT42"            ,	   0x11800a00020e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
-	{"PIP_XSTAT8_PRT43"            ,	   0x11800a0002130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
-	{"PIP_XSTAT9_PRT40"            ,	   0x11800a0002048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
-	{"PIP_XSTAT9_PRT41"            ,	   0x11800a0002098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
-	{"PIP_XSTAT9_PRT42"            ,	   0x11800a00020e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
-	{"PIP_XSTAT9_PRT43"            ,	   0x11800a0002138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
-	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
-	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
-	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
-	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
-	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
-	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
-	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
-	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
-	{"PKO_MEM_DEBUG14"             ,	   0x1180050001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
-	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
-	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
-	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
-	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
-	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
-	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
-	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
-	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
-	{"PKO_MEM_PORT_PTRS"           ,	   0x1180050001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
-	{"PKO_MEM_PORT_QOS"            ,	   0x1180050001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
-	{"PKO_MEM_PORT_RATE0"          ,	   0x1180050001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	817},
-	{"PKO_MEM_PORT_RATE1"          ,	   0x1180050001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
-	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	819},
-	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	820},
-	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	821},
-	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	822},
-	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	823},
-	{"PKO_REG_DEBUG1"              ,	   0x11800500000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
-	{"PKO_REG_DEBUG2"              ,	   0x11800500000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
-	{"PKO_REG_DEBUG3"              ,	   0x11800500000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
-	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
-	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
-	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
-	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
-	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
-	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
-	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
-	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
-	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
-	{"PKO_REG_TIMESTAMP"           ,	   0x1180050000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
-	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
-	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
-	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	839},
-	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	840},
-	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
-	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
-	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
-	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
-	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
-	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
-	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
-	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
-	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	842},
-	{"POW_IQ_INT"                  ,	   0x1670000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	843},
-	{"POW_IQ_INT_EN"               ,	   0x1670000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	844},
-	{"POW_IQ_THR0"                 ,	   0x16700000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
-	{"POW_IQ_THR1"                 ,	   0x16700000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
-	{"POW_IQ_THR2"                 ,	   0x16700000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
-	{"POW_IQ_THR3"                 ,	   0x16700000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
-	{"POW_IQ_THR4"                 ,	   0x16700000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
-	{"POW_IQ_THR5"                 ,	   0x16700000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
-	{"POW_IQ_THR6"                 ,	   0x16700000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
-	{"POW_IQ_THR7"                 ,	   0x16700000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
-	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	846},
-	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	847},
-	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	848},
-	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
-	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
-	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
-	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
-	{"POW_PP_GRP_MSK4"             ,	   0x1670000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
-	{"POW_PP_GRP_MSK5"             ,	   0x1670000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
-	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
-	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
-	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
-	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
-	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
-	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
-	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
-	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
-	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
-	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
-	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
-	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
-	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
-	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
-	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
-	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
-	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	852},
-	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
-	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
-	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
-	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
-	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
-	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
-	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
-	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
-	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
-	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	855},
-	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
-	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
-	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
-	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
-	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
-	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
-	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
-	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
-	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
-	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
-	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
-	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
-	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
-	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
-	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
-	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
-	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
-	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	860},
-	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	861},
-	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	862},
-	{"RAD_REG_BIST_RESULT"         ,	   0x1180070000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	863},
-	{"RAD_REG_CMD_BUF"             ,	   0x1180070000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	864},
-	{"RAD_REG_CTL"                 ,	   0x1180070000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	865},
-	{"RAD_REG_DEBUG0"              ,	   0x1180070000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	866},
-	{"RAD_REG_DEBUG1"              ,	   0x1180070000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	867},
-	{"RAD_REG_DEBUG10"             ,	   0x1180070000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	868},
-	{"RAD_REG_DEBUG11"             ,	   0x1180070000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	869},
-	{"RAD_REG_DEBUG12"             ,	   0x1180070000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	870},
-	{"RAD_REG_DEBUG2"              ,	   0x1180070000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	871},
-	{"RAD_REG_DEBUG3"              ,	   0x1180070000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
-	{"RAD_REG_DEBUG4"              ,	   0x1180070000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	873},
-	{"RAD_REG_DEBUG5"              ,	   0x1180070000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	874},
-	{"RAD_REG_DEBUG6"              ,	   0x1180070000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	875},
-	{"RAD_REG_DEBUG7"              ,	   0x1180070000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	876},
-	{"RAD_REG_DEBUG8"              ,	   0x1180070000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	877},
-	{"RAD_REG_DEBUG9"              ,	   0x1180070000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	878},
-	{"RAD_REG_ERROR"               ,	   0x1180070000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
-	{"RAD_REG_INT_MASK"            ,	   0x1180070000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
-	{"RAD_REG_POLYNOMIAL"          ,	   0x1180070000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
-	{"RAD_REG_READ_IDX"            ,	   0x1180070000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
-	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
-	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
-	{"RNM_EER_DBG"                 ,	   0x1180040000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
-	{"RNM_EER_KEY"                 ,	   0x1180040000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	886},
-	{"SLI_BIST_STATUS"             ,	   0x11f0000010580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	887},
-	{"SLI_CTL_PORT0"               ,	   0x11f0000010050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	888},
-	{"SLI_CTL_PORT1"               ,	   0x11f0000010060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	888},
-	{"SLI_CTL_STATUS"              ,	   0x11f0000010570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	889},
-	{"SLI_DATA_OUT_CNT"            ,	   0x11f00000105f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	890},
-	{"SLI_DBG_DATA"                ,	   0x11f0000010310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	891},
-	{"SLI_DBG_SELECT"              ,	   0x11f0000010300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	892},
-	{"SLI_DMA0_CNT"                ,	   0x11f0000010400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	893},
-	{"SLI_DMA1_CNT"                ,	   0x11f0000010410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	893},
-	{"SLI_DMA0_INT_LEVEL"          ,	   0x11f00000103e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	894},
-	{"SLI_DMA1_INT_LEVEL"          ,	   0x11f00000103f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	894},
-	{"SLI_DMA0_TIM"                ,	   0x11f0000010420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	895},
-	{"SLI_DMA1_TIM"                ,	   0x11f0000010430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	895},
-	{"SLI_INT_ENB_CIU"             ,	   0x11f0000013cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	896},
-	{"SLI_INT_ENB_PORT0"           ,	   0x11f0000010340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	897},
-	{"SLI_INT_ENB_PORT1"           ,	   0x11f0000010350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	897},
-	{"SLI_INT_SUM"                 ,	   0x11f0000010330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	898},
-	{"SLI_LAST_WIN_RDATA0"         ,	   0x11f0000010600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	899},
-	{"SLI_LAST_WIN_RDATA1"         ,	   0x11f0000010610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	900},
-	{"SLI_MAC_CREDIT_CNT"          ,	   0x11f0000013d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	901},
-	{"SLI_MEM_ACCESS_CTL"          ,	   0x11f00000102f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	902},
-	{"SLI_MEM_ACCESS_SUBID12"      ,	   0x11f00000100e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
-	{"SLI_MEM_ACCESS_SUBID13"      ,	   0x11f00000100f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
-	{"SLI_MEM_ACCESS_SUBID14"      ,	   0x11f0000010100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
-	{"SLI_MEM_ACCESS_SUBID15"      ,	   0x11f0000010110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
-	{"SLI_MEM_ACCESS_SUBID16"      ,	   0x11f0000010120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
-	{"SLI_MEM_ACCESS_SUBID17"      ,	   0x11f0000010130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
-	{"SLI_MEM_ACCESS_SUBID18"      ,	   0x11f0000010140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
-	{"SLI_MEM_ACCESS_SUBID19"      ,	   0x11f0000010150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
-	{"SLI_MEM_ACCESS_SUBID20"      ,	   0x11f0000010160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
-	{"SLI_MEM_ACCESS_SUBID21"      ,	   0x11f0000010170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
-	{"SLI_MEM_ACCESS_SUBID22"      ,	   0x11f0000010180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
-	{"SLI_MEM_ACCESS_SUBID23"      ,	   0x11f0000010190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
-	{"SLI_MEM_ACCESS_SUBID24"      ,	   0x11f00000101a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
-	{"SLI_MEM_ACCESS_SUBID25"      ,	   0x11f00000101b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
-	{"SLI_MEM_ACCESS_SUBID26"      ,	   0x11f00000101c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
-	{"SLI_MEM_ACCESS_SUBID27"      ,	   0x11f00000101d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
-	{"SLI_MSI_ENB0"                ,	   0x11f0000013c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	904},
-	{"SLI_MSI_ENB1"                ,	   0x11f0000013c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	905},
-	{"SLI_MSI_ENB2"                ,	   0x11f0000013c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	906},
-	{"SLI_MSI_ENB3"                ,	   0x11f0000013c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	907},
-	{"SLI_MSI_RCV0"                ,	   0x11f0000013c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	908},
-	{"SLI_MSI_RCV1"                ,	   0x11f0000013c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
-	{"SLI_MSI_RCV2"                ,	   0x11f0000013c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	910},
-	{"SLI_MSI_RCV3"                ,	   0x11f0000013c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	911},
-	{"SLI_MSI_RD_MAP"              ,	   0x11f0000013ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	912},
-	{"SLI_MSI_W1C_ENB0"            ,	   0x11f0000013cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
-	{"SLI_MSI_W1C_ENB1"            ,	   0x11f0000013d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	914},
-	{"SLI_MSI_W1C_ENB2"            ,	   0x11f0000013d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	915},
-	{"SLI_MSI_W1C_ENB3"            ,	   0x11f0000013d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	916},
-	{"SLI_MSI_W1S_ENB0"            ,	   0x11f0000013d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	917},
-	{"SLI_MSI_W1S_ENB1"            ,	   0x11f0000013d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	918},
-	{"SLI_MSI_W1S_ENB2"            ,	   0x11f0000013d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
-	{"SLI_MSI_W1S_ENB3"            ,	   0x11f0000013d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	920},
-	{"SLI_MSI_WR_MAP"              ,	   0x11f0000013c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	921},
-	{"SLI_PCIE_MSI_RCV"            ,	   0x11f0000013cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	922},
-	{"SLI_PCIE_MSI_RCV_B1"         ,	   0x11f0000010650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	923},
-	{"SLI_PCIE_MSI_RCV_B2"         ,	   0x11f0000010660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	924},
-	{"SLI_PCIE_MSI_RCV_B3"         ,	   0x11f0000010670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	925},
-	{"SLI_PKT0_CNTS"               ,	   0x11f0000012400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT1_CNTS"               ,	   0x11f0000012410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT2_CNTS"               ,	   0x11f0000012420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT3_CNTS"               ,	   0x11f0000012430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT4_CNTS"               ,	   0x11f0000012440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT5_CNTS"               ,	   0x11f0000012450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT6_CNTS"               ,	   0x11f0000012460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT7_CNTS"               ,	   0x11f0000012470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT8_CNTS"               ,	   0x11f0000012480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT9_CNTS"               ,	   0x11f0000012490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT10_CNTS"              ,	   0x11f00000124a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT11_CNTS"              ,	   0x11f00000124b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT12_CNTS"              ,	   0x11f00000124c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT13_CNTS"              ,	   0x11f00000124d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT14_CNTS"              ,	   0x11f00000124e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT15_CNTS"              ,	   0x11f00000124f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT16_CNTS"              ,	   0x11f0000012500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT17_CNTS"              ,	   0x11f0000012510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT18_CNTS"              ,	   0x11f0000012520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT19_CNTS"              ,	   0x11f0000012530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT20_CNTS"              ,	   0x11f0000012540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT21_CNTS"              ,	   0x11f0000012550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT22_CNTS"              ,	   0x11f0000012560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT23_CNTS"              ,	   0x11f0000012570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT24_CNTS"              ,	   0x11f0000012580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT25_CNTS"              ,	   0x11f0000012590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT26_CNTS"              ,	   0x11f00000125a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT27_CNTS"              ,	   0x11f00000125b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT28_CNTS"              ,	   0x11f00000125c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT29_CNTS"              ,	   0x11f00000125d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT30_CNTS"              ,	   0x11f00000125e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT31_CNTS"              ,	   0x11f00000125f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_PKT0_IN_BP"              ,	   0x11f0000013800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT1_IN_BP"              ,	   0x11f0000013810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT2_IN_BP"              ,	   0x11f0000013820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT3_IN_BP"              ,	   0x11f0000013830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT4_IN_BP"              ,	   0x11f0000013840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT5_IN_BP"              ,	   0x11f0000013850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT6_IN_BP"              ,	   0x11f0000013860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT7_IN_BP"              ,	   0x11f0000013870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT8_IN_BP"              ,	   0x11f0000013880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT9_IN_BP"              ,	   0x11f0000013890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT10_IN_BP"             ,	   0x11f00000138a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT11_IN_BP"             ,	   0x11f00000138b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT12_IN_BP"             ,	   0x11f00000138c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT13_IN_BP"             ,	   0x11f00000138d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT14_IN_BP"             ,	   0x11f00000138e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT15_IN_BP"             ,	   0x11f00000138f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT16_IN_BP"             ,	   0x11f0000013900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT17_IN_BP"             ,	   0x11f0000013910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT18_IN_BP"             ,	   0x11f0000013920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT19_IN_BP"             ,	   0x11f0000013930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT20_IN_BP"             ,	   0x11f0000013940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT21_IN_BP"             ,	   0x11f0000013950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT22_IN_BP"             ,	   0x11f0000013960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT23_IN_BP"             ,	   0x11f0000013970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT24_IN_BP"             ,	   0x11f0000013980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT25_IN_BP"             ,	   0x11f0000013990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT26_IN_BP"             ,	   0x11f00000139a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT27_IN_BP"             ,	   0x11f00000139b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT28_IN_BP"             ,	   0x11f00000139c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT29_IN_BP"             ,	   0x11f00000139d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT30_IN_BP"             ,	   0x11f00000139e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT31_IN_BP"             ,	   0x11f00000139f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_PKT0_INSTR_BADDR"        ,	   0x11f0000012800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT1_INSTR_BADDR"        ,	   0x11f0000012810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT2_INSTR_BADDR"        ,	   0x11f0000012820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT3_INSTR_BADDR"        ,	   0x11f0000012830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT4_INSTR_BADDR"        ,	   0x11f0000012840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT5_INSTR_BADDR"        ,	   0x11f0000012850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT6_INSTR_BADDR"        ,	   0x11f0000012860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT7_INSTR_BADDR"        ,	   0x11f0000012870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT8_INSTR_BADDR"        ,	   0x11f0000012880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT9_INSTR_BADDR"        ,	   0x11f0000012890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT10_INSTR_BADDR"       ,	   0x11f00000128a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT11_INSTR_BADDR"       ,	   0x11f00000128b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT12_INSTR_BADDR"       ,	   0x11f00000128c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT13_INSTR_BADDR"       ,	   0x11f00000128d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT14_INSTR_BADDR"       ,	   0x11f00000128e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT15_INSTR_BADDR"       ,	   0x11f00000128f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT16_INSTR_BADDR"       ,	   0x11f0000012900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT17_INSTR_BADDR"       ,	   0x11f0000012910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT18_INSTR_BADDR"       ,	   0x11f0000012920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT19_INSTR_BADDR"       ,	   0x11f0000012930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT20_INSTR_BADDR"       ,	   0x11f0000012940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT21_INSTR_BADDR"       ,	   0x11f0000012950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT22_INSTR_BADDR"       ,	   0x11f0000012960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT23_INSTR_BADDR"       ,	   0x11f0000012970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT24_INSTR_BADDR"       ,	   0x11f0000012980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT25_INSTR_BADDR"       ,	   0x11f0000012990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT26_INSTR_BADDR"       ,	   0x11f00000129a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT27_INSTR_BADDR"       ,	   0x11f00000129b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT28_INSTR_BADDR"       ,	   0x11f00000129c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT29_INSTR_BADDR"       ,	   0x11f00000129d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT30_INSTR_BADDR"       ,	   0x11f00000129e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT31_INSTR_BADDR"       ,	   0x11f00000129f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_PKT0_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT1_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT2_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT3_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT4_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT5_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT6_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT7_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT8_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT9_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT10_INSTR_BAOFF_DBELL" ,	   0x11f0000012ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT11_INSTR_BAOFF_DBELL" ,	   0x11f0000012cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT12_INSTR_BAOFF_DBELL" ,	   0x11f0000012cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT13_INSTR_BAOFF_DBELL" ,	   0x11f0000012cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT14_INSTR_BAOFF_DBELL" ,	   0x11f0000012ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT15_INSTR_BAOFF_DBELL" ,	   0x11f0000012cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT16_INSTR_BAOFF_DBELL" ,	   0x11f0000012d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT17_INSTR_BAOFF_DBELL" ,	   0x11f0000012d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT18_INSTR_BAOFF_DBELL" ,	   0x11f0000012d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT19_INSTR_BAOFF_DBELL" ,	   0x11f0000012d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT20_INSTR_BAOFF_DBELL" ,	   0x11f0000012d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT21_INSTR_BAOFF_DBELL" ,	   0x11f0000012d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT22_INSTR_BAOFF_DBELL" ,	   0x11f0000012d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT23_INSTR_BAOFF_DBELL" ,	   0x11f0000012d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT24_INSTR_BAOFF_DBELL" ,	   0x11f0000012d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT25_INSTR_BAOFF_DBELL" ,	   0x11f0000012d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT26_INSTR_BAOFF_DBELL" ,	   0x11f0000012da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT27_INSTR_BAOFF_DBELL" ,	   0x11f0000012db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT28_INSTR_BAOFF_DBELL" ,	   0x11f0000012dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT29_INSTR_BAOFF_DBELL" ,	   0x11f0000012dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT30_INSTR_BAOFF_DBELL" ,	   0x11f0000012de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT31_INSTR_BAOFF_DBELL" ,	   0x11f0000012df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_PKT0_INSTR_FIFO_RSIZE"   ,	   0x11f0000013000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT1_INSTR_FIFO_RSIZE"   ,	   0x11f0000013010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT2_INSTR_FIFO_RSIZE"   ,	   0x11f0000013020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT3_INSTR_FIFO_RSIZE"   ,	   0x11f0000013030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT4_INSTR_FIFO_RSIZE"   ,	   0x11f0000013040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT5_INSTR_FIFO_RSIZE"   ,	   0x11f0000013050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT6_INSTR_FIFO_RSIZE"   ,	   0x11f0000013060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT7_INSTR_FIFO_RSIZE"   ,	   0x11f0000013070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT8_INSTR_FIFO_RSIZE"   ,	   0x11f0000013080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT9_INSTR_FIFO_RSIZE"   ,	   0x11f0000013090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT10_INSTR_FIFO_RSIZE"  ,	   0x11f00000130a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT11_INSTR_FIFO_RSIZE"  ,	   0x11f00000130b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT12_INSTR_FIFO_RSIZE"  ,	   0x11f00000130c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT13_INSTR_FIFO_RSIZE"  ,	   0x11f00000130d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT14_INSTR_FIFO_RSIZE"  ,	   0x11f00000130e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT15_INSTR_FIFO_RSIZE"  ,	   0x11f00000130f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT16_INSTR_FIFO_RSIZE"  ,	   0x11f0000013100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT17_INSTR_FIFO_RSIZE"  ,	   0x11f0000013110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT18_INSTR_FIFO_RSIZE"  ,	   0x11f0000013120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT19_INSTR_FIFO_RSIZE"  ,	   0x11f0000013130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT20_INSTR_FIFO_RSIZE"  ,	   0x11f0000013140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT21_INSTR_FIFO_RSIZE"  ,	   0x11f0000013150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT22_INSTR_FIFO_RSIZE"  ,	   0x11f0000013160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT23_INSTR_FIFO_RSIZE"  ,	   0x11f0000013170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT24_INSTR_FIFO_RSIZE"  ,	   0x11f0000013180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT25_INSTR_FIFO_RSIZE"  ,	   0x11f0000013190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT26_INSTR_FIFO_RSIZE"  ,	   0x11f00000131a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT27_INSTR_FIFO_RSIZE"  ,	   0x11f00000131b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT28_INSTR_FIFO_RSIZE"  ,	   0x11f00000131c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT29_INSTR_FIFO_RSIZE"  ,	   0x11f00000131d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT30_INSTR_FIFO_RSIZE"  ,	   0x11f00000131e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT31_INSTR_FIFO_RSIZE"  ,	   0x11f00000131f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_PKT0_INSTR_HEADER"       ,	   0x11f0000013400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT1_INSTR_HEADER"       ,	   0x11f0000013410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT2_INSTR_HEADER"       ,	   0x11f0000013420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT3_INSTR_HEADER"       ,	   0x11f0000013430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT4_INSTR_HEADER"       ,	   0x11f0000013440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT5_INSTR_HEADER"       ,	   0x11f0000013450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT6_INSTR_HEADER"       ,	   0x11f0000013460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT7_INSTR_HEADER"       ,	   0x11f0000013470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT8_INSTR_HEADER"       ,	   0x11f0000013480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT9_INSTR_HEADER"       ,	   0x11f0000013490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT10_INSTR_HEADER"      ,	   0x11f00000134a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT11_INSTR_HEADER"      ,	   0x11f00000134b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT12_INSTR_HEADER"      ,	   0x11f00000134c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT13_INSTR_HEADER"      ,	   0x11f00000134d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT14_INSTR_HEADER"      ,	   0x11f00000134e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT15_INSTR_HEADER"      ,	   0x11f00000134f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT16_INSTR_HEADER"      ,	   0x11f0000013500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT17_INSTR_HEADER"      ,	   0x11f0000013510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT18_INSTR_HEADER"      ,	   0x11f0000013520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT19_INSTR_HEADER"      ,	   0x11f0000013530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT20_INSTR_HEADER"      ,	   0x11f0000013540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT21_INSTR_HEADER"      ,	   0x11f0000013550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT22_INSTR_HEADER"      ,	   0x11f0000013560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT23_INSTR_HEADER"      ,	   0x11f0000013570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT24_INSTR_HEADER"      ,	   0x11f0000013580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT25_INSTR_HEADER"      ,	   0x11f0000013590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT26_INSTR_HEADER"      ,	   0x11f00000135a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT27_INSTR_HEADER"      ,	   0x11f00000135b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT28_INSTR_HEADER"      ,	   0x11f00000135c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT29_INSTR_HEADER"      ,	   0x11f00000135d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT30_INSTR_HEADER"      ,	   0x11f00000135e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT31_INSTR_HEADER"      ,	   0x11f00000135f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PKT0_OUT_SIZE"           ,	   0x11f0000010c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT1_OUT_SIZE"           ,	   0x11f0000010c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT2_OUT_SIZE"           ,	   0x11f0000010c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT3_OUT_SIZE"           ,	   0x11f0000010c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT4_OUT_SIZE"           ,	   0x11f0000010c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT5_OUT_SIZE"           ,	   0x11f0000010c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT6_OUT_SIZE"           ,	   0x11f0000010c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT7_OUT_SIZE"           ,	   0x11f0000010c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT8_OUT_SIZE"           ,	   0x11f0000010c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT9_OUT_SIZE"           ,	   0x11f0000010c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT10_OUT_SIZE"          ,	   0x11f0000010ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT11_OUT_SIZE"          ,	   0x11f0000010cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT12_OUT_SIZE"          ,	   0x11f0000010cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT13_OUT_SIZE"          ,	   0x11f0000010cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT14_OUT_SIZE"          ,	   0x11f0000010ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT15_OUT_SIZE"          ,	   0x11f0000010cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT16_OUT_SIZE"          ,	   0x11f0000010d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT17_OUT_SIZE"          ,	   0x11f0000010d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT18_OUT_SIZE"          ,	   0x11f0000010d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT19_OUT_SIZE"          ,	   0x11f0000010d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT20_OUT_SIZE"          ,	   0x11f0000010d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT21_OUT_SIZE"          ,	   0x11f0000010d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT22_OUT_SIZE"          ,	   0x11f0000010d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT23_OUT_SIZE"          ,	   0x11f0000010d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT24_OUT_SIZE"          ,	   0x11f0000010d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT25_OUT_SIZE"          ,	   0x11f0000010d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT26_OUT_SIZE"          ,	   0x11f0000010da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT27_OUT_SIZE"          ,	   0x11f0000010db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT28_OUT_SIZE"          ,	   0x11f0000010dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT29_OUT_SIZE"          ,	   0x11f0000010dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT30_OUT_SIZE"          ,	   0x11f0000010de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT31_OUT_SIZE"          ,	   0x11f0000010df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PKT0_SLIST_BADDR"        ,	   0x11f0000011400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT1_SLIST_BADDR"        ,	   0x11f0000011410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT2_SLIST_BADDR"        ,	   0x11f0000011420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT3_SLIST_BADDR"        ,	   0x11f0000011430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT4_SLIST_BADDR"        ,	   0x11f0000011440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT5_SLIST_BADDR"        ,	   0x11f0000011450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT6_SLIST_BADDR"        ,	   0x11f0000011460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT7_SLIST_BADDR"        ,	   0x11f0000011470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT8_SLIST_BADDR"        ,	   0x11f0000011480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT9_SLIST_BADDR"        ,	   0x11f0000011490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT10_SLIST_BADDR"       ,	   0x11f00000114a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT11_SLIST_BADDR"       ,	   0x11f00000114b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT12_SLIST_BADDR"       ,	   0x11f00000114c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT13_SLIST_BADDR"       ,	   0x11f00000114d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT14_SLIST_BADDR"       ,	   0x11f00000114e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT15_SLIST_BADDR"       ,	   0x11f00000114f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT16_SLIST_BADDR"       ,	   0x11f0000011500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT17_SLIST_BADDR"       ,	   0x11f0000011510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT18_SLIST_BADDR"       ,	   0x11f0000011520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT19_SLIST_BADDR"       ,	   0x11f0000011530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT20_SLIST_BADDR"       ,	   0x11f0000011540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT21_SLIST_BADDR"       ,	   0x11f0000011550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT22_SLIST_BADDR"       ,	   0x11f0000011560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT23_SLIST_BADDR"       ,	   0x11f0000011570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT24_SLIST_BADDR"       ,	   0x11f0000011580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT25_SLIST_BADDR"       ,	   0x11f0000011590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT26_SLIST_BADDR"       ,	   0x11f00000115a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT27_SLIST_BADDR"       ,	   0x11f00000115b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT28_SLIST_BADDR"       ,	   0x11f00000115c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT29_SLIST_BADDR"       ,	   0x11f00000115d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT30_SLIST_BADDR"       ,	   0x11f00000115e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT31_SLIST_BADDR"       ,	   0x11f00000115f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PKT0_SLIST_BAOFF_DBELL"  ,	   0x11f0000011800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT1_SLIST_BAOFF_DBELL"  ,	   0x11f0000011810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT2_SLIST_BAOFF_DBELL"  ,	   0x11f0000011820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT3_SLIST_BAOFF_DBELL"  ,	   0x11f0000011830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT4_SLIST_BAOFF_DBELL"  ,	   0x11f0000011840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT5_SLIST_BAOFF_DBELL"  ,	   0x11f0000011850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT6_SLIST_BAOFF_DBELL"  ,	   0x11f0000011860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT7_SLIST_BAOFF_DBELL"  ,	   0x11f0000011870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT8_SLIST_BAOFF_DBELL"  ,	   0x11f0000011880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT9_SLIST_BAOFF_DBELL"  ,	   0x11f0000011890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT10_SLIST_BAOFF_DBELL" ,	   0x11f00000118a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT11_SLIST_BAOFF_DBELL" ,	   0x11f00000118b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT12_SLIST_BAOFF_DBELL" ,	   0x11f00000118c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT13_SLIST_BAOFF_DBELL" ,	   0x11f00000118d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT14_SLIST_BAOFF_DBELL" ,	   0x11f00000118e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT15_SLIST_BAOFF_DBELL" ,	   0x11f00000118f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT16_SLIST_BAOFF_DBELL" ,	   0x11f0000011900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT17_SLIST_BAOFF_DBELL" ,	   0x11f0000011910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT18_SLIST_BAOFF_DBELL" ,	   0x11f0000011920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT19_SLIST_BAOFF_DBELL" ,	   0x11f0000011930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT20_SLIST_BAOFF_DBELL" ,	   0x11f0000011940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT21_SLIST_BAOFF_DBELL" ,	   0x11f0000011950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT22_SLIST_BAOFF_DBELL" ,	   0x11f0000011960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT23_SLIST_BAOFF_DBELL" ,	   0x11f0000011970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT24_SLIST_BAOFF_DBELL" ,	   0x11f0000011980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT25_SLIST_BAOFF_DBELL" ,	   0x11f0000011990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT26_SLIST_BAOFF_DBELL" ,	   0x11f00000119a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT27_SLIST_BAOFF_DBELL" ,	   0x11f00000119b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT28_SLIST_BAOFF_DBELL" ,	   0x11f00000119c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT29_SLIST_BAOFF_DBELL" ,	   0x11f00000119d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT30_SLIST_BAOFF_DBELL" ,	   0x11f00000119e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT31_SLIST_BAOFF_DBELL" ,	   0x11f00000119f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PKT0_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT1_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT2_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT3_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT4_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT5_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT6_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT7_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT8_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT9_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT10_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT11_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT12_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT13_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT14_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT15_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT16_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT17_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT18_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT19_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT20_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT21_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT22_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT23_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT24_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT25_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT26_SLIST_FIFO_RSIZE"  ,	   0x11f0000011da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT27_SLIST_FIFO_RSIZE"  ,	   0x11f0000011db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT28_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT29_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT30_SLIST_FIFO_RSIZE"  ,	   0x11f0000011de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT31_SLIST_FIFO_RSIZE"  ,	   0x11f0000011df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT_CNT_INT"             ,	   0x11f0000011130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT_CNT_INT_ENB"         ,	   0x11f0000011150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT_CTL"                 ,	   0x11f0000011220ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT_DATA_OUT_ES"         ,	   0x11f00000110b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT_DATA_OUT_NS"         ,	   0x11f00000110a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT_DATA_OUT_ROR"        ,	   0x11f0000011090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT_DPADDR"              ,	   0x11f0000011080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT_IN_BP"               ,	   0x11f0000011210ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT_IN_DONE0_CNTS"       ,	   0x11f0000012000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE1_CNTS"       ,	   0x11f0000012010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE2_CNTS"       ,	   0x11f0000012020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE3_CNTS"       ,	   0x11f0000012030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE4_CNTS"       ,	   0x11f0000012040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE5_CNTS"       ,	   0x11f0000012050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE6_CNTS"       ,	   0x11f0000012060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE7_CNTS"       ,	   0x11f0000012070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE8_CNTS"       ,	   0x11f0000012080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE9_CNTS"       ,	   0x11f0000012090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE10_CNTS"      ,	   0x11f00000120a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE11_CNTS"      ,	   0x11f00000120b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE12_CNTS"      ,	   0x11f00000120c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE13_CNTS"      ,	   0x11f00000120d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE14_CNTS"      ,	   0x11f00000120e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE15_CNTS"      ,	   0x11f00000120f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE16_CNTS"      ,	   0x11f0000012100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE17_CNTS"      ,	   0x11f0000012110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE18_CNTS"      ,	   0x11f0000012120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE19_CNTS"      ,	   0x11f0000012130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE20_CNTS"      ,	   0x11f0000012140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE21_CNTS"      ,	   0x11f0000012150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE22_CNTS"      ,	   0x11f0000012160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE23_CNTS"      ,	   0x11f0000012170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE24_CNTS"      ,	   0x11f0000012180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE25_CNTS"      ,	   0x11f0000012190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE26_CNTS"      ,	   0x11f00000121a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE27_CNTS"      ,	   0x11f00000121b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE28_CNTS"      ,	   0x11f00000121c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE29_CNTS"      ,	   0x11f00000121d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE30_CNTS"      ,	   0x11f00000121e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_DONE31_CNTS"      ,	   0x11f00000121f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT_IN_INSTR_COUNTS"     ,	   0x11f0000011200ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT_IN_PCIE_PORT"        ,	   0x11f00000111b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
-	{"SLI_PKT_INPUT_CONTROL"       ,	   0x11f0000011170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
-	{"SLI_PKT_INSTR_ENB"           ,	   0x11f0000011000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
-	{"SLI_PKT_INSTR_RD_SIZE"       ,	   0x11f00000111a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
-	{"SLI_PKT_INSTR_SIZE"          ,	   0x11f0000011020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
-	{"SLI_PKT_INT_LEVELS"          ,	   0x11f0000011120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
-	{"SLI_PKT_IPTR"                ,	   0x11f0000011070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	952},
-	{"SLI_PKT_OUT_BMODE"           ,	   0x11f00000110d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	953},
-	{"SLI_PKT_OUT_ENB"             ,	   0x11f0000011010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_OUTPUT_WMARK"        ,	   0x11f0000011180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	955},
-	{"SLI_PKT_PCIE_PORT"           ,	   0x11f00000110e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	956},
-	{"SLI_PKT_PORT_IN_RST"         ,	   0x11f00000111f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	957},
-	{"SLI_PKT_SLIST_ES"            ,	   0x11f0000011050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	958},
-	{"SLI_PKT_SLIST_NS"            ,	   0x11f0000011040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	959},
-	{"SLI_PKT_SLIST_ROR"           ,	   0x11f0000011030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
-	{"SLI_PKT_TIME_INT"            ,	   0x11f0000011140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	961},
-	{"SLI_PKT_TIME_INT_ENB"        ,	   0x11f0000011160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	962},
-	{"SLI_S2M_PORT0_CTL"           ,	   0x11f0000013d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	963},
-	{"SLI_S2M_PORT1_CTL"           ,	   0x11f0000013d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	963},
-	{"SLI_SCRATCH_1"               ,	   0x11f00000103c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	964},
-	{"SLI_SCRATCH_2"               ,	   0x11f00000103d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	965},
-	{"SLI_STATE1"                  ,	   0x11f0000010620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	966},
-	{"SLI_STATE2"                  ,	   0x11f0000010630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	967},
-	{"SLI_STATE3"                  ,	   0x11f0000010640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	968},
-	{"SLI_WIN_RD_ADDR"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	969},
-	{"SLI_WIN_RD_DATA"             ,	              0x40ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	970},
-	{"SLI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	971},
-	{"SLI_WIN_WR_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	972},
-	{"SLI_WIN_WR_MASK"             ,	              0x30ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	973},
-	{"SLI_WINDOW_CTL"              ,	   0x11f00000102e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	974},
-	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	975},
-	{"SMI1_CLK"                    ,	   0x1180000001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	975},
-	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	976},
-	{"SMI1_CMD"                    ,	   0x1180000001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	976},
-	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	977},
-	{"SMI1_EN"                     ,	   0x1180000001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	977},
-	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	978},
-	{"SMI1_RD_DAT"                 ,	   0x1180000001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	978},
-	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	979},
-	{"SMI1_WR_DAT"                 ,	   0x1180000001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	979},
-	{"SMI_DRV_CTL"                 ,	   0x1180000001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	980},
-	{"SRIO0_ACC_CTRL"              ,	   0x11800c8000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	981},
-	{"SRIO1_ACC_CTRL"              ,	   0x11800c9000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	981},
-	{"SRIO0_ASMBLY_ID"             ,	   0x11800c8000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	982},
-	{"SRIO1_ASMBLY_ID"             ,	   0x11800c9000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	982},
-	{"SRIO0_ASMBLY_INFO"           ,	   0x11800c8000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	983},
-	{"SRIO1_ASMBLY_INFO"           ,	   0x11800c9000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	983},
-	{"SRIO0_BELL_RESP_CTRL"        ,	   0x11800c8000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	984},
-	{"SRIO1_BELL_RESP_CTRL"        ,	   0x11800c9000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	984},
-	{"SRIO0_BIST_STATUS"           ,	   0x11800c8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	985},
-	{"SRIO1_BIST_STATUS"           ,	   0x11800c9000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	985},
-	{"SRIO0_IMSG_CTRL"             ,	   0x11800c8000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
-	{"SRIO1_IMSG_CTRL"             ,	   0x11800c9000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
-	{"SRIO0_IMSG_INST_HDR000"      ,	   0x11800c8000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	987},
-	{"SRIO0_IMSG_INST_HDR001"      ,	   0x11800c8000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	987},
-	{"SRIO1_IMSG_INST_HDR000"      ,	   0x11800c9000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	987},
-	{"SRIO1_IMSG_INST_HDR001"      ,	   0x11800c9000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	987},
-	{"SRIO0_IMSG_QOS_GRP000"       ,	   0x11800c8000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP001"       ,	   0x11800c8000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP002"       ,	   0x11800c8000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP003"       ,	   0x11800c8000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP004"       ,	   0x11800c8000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP005"       ,	   0x11800c8000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP006"       ,	   0x11800c8000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP007"       ,	   0x11800c8000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP008"       ,	   0x11800c8000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP009"       ,	   0x11800c8000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP010"       ,	   0x11800c8000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP011"       ,	   0x11800c8000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP012"       ,	   0x11800c8000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP013"       ,	   0x11800c8000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP014"       ,	   0x11800c8000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP015"       ,	   0x11800c8000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP016"       ,	   0x11800c8000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP017"       ,	   0x11800c8000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP018"       ,	   0x11800c8000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP019"       ,	   0x11800c8000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP020"       ,	   0x11800c80006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP021"       ,	   0x11800c80006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP022"       ,	   0x11800c80006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP023"       ,	   0x11800c80006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP024"       ,	   0x11800c80006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP025"       ,	   0x11800c80006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP026"       ,	   0x11800c80006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP027"       ,	   0x11800c80006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP028"       ,	   0x11800c80006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP029"       ,	   0x11800c80006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP030"       ,	   0x11800c80006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_QOS_GRP031"       ,	   0x11800c80006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP000"       ,	   0x11800c9000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP001"       ,	   0x11800c9000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP002"       ,	   0x11800c9000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP003"       ,	   0x11800c9000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP004"       ,	   0x11800c9000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP005"       ,	   0x11800c9000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP006"       ,	   0x11800c9000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP007"       ,	   0x11800c9000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP008"       ,	   0x11800c9000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP009"       ,	   0x11800c9000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP010"       ,	   0x11800c9000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP011"       ,	   0x11800c9000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP012"       ,	   0x11800c9000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP013"       ,	   0x11800c9000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP014"       ,	   0x11800c9000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP015"       ,	   0x11800c9000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP016"       ,	   0x11800c9000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP017"       ,	   0x11800c9000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP018"       ,	   0x11800c9000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP019"       ,	   0x11800c9000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP020"       ,	   0x11800c90006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP021"       ,	   0x11800c90006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP022"       ,	   0x11800c90006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP023"       ,	   0x11800c90006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP024"       ,	   0x11800c90006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP025"       ,	   0x11800c90006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP026"       ,	   0x11800c90006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP027"       ,	   0x11800c90006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP028"       ,	   0x11800c90006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP029"       ,	   0x11800c90006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP030"       ,	   0x11800c90006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO1_IMSG_QOS_GRP031"       ,	   0x11800c90006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SRIO0_IMSG_STATUS000"        ,	   0x11800c8000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS001"        ,	   0x11800c8000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS002"        ,	   0x11800c8000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS003"        ,	   0x11800c8000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS004"        ,	   0x11800c8000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS005"        ,	   0x11800c8000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS006"        ,	   0x11800c8000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS007"        ,	   0x11800c8000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS008"        ,	   0x11800c8000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS009"        ,	   0x11800c8000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS010"        ,	   0x11800c8000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS011"        ,	   0x11800c8000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS012"        ,	   0x11800c8000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS013"        ,	   0x11800c8000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS014"        ,	   0x11800c8000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS015"        ,	   0x11800c8000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS016"        ,	   0x11800c8000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS017"        ,	   0x11800c8000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS018"        ,	   0x11800c8000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS019"        ,	   0x11800c8000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS020"        ,	   0x11800c80007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS021"        ,	   0x11800c80007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS022"        ,	   0x11800c80007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_STATUS023"        ,	   0x11800c80007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS000"        ,	   0x11800c9000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS001"        ,	   0x11800c9000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS002"        ,	   0x11800c9000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS003"        ,	   0x11800c9000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS004"        ,	   0x11800c9000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS005"        ,	   0x11800c9000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS006"        ,	   0x11800c9000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS007"        ,	   0x11800c9000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS008"        ,	   0x11800c9000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS009"        ,	   0x11800c9000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS010"        ,	   0x11800c9000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS011"        ,	   0x11800c9000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS012"        ,	   0x11800c9000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS013"        ,	   0x11800c9000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS014"        ,	   0x11800c9000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS015"        ,	   0x11800c9000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS016"        ,	   0x11800c9000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS017"        ,	   0x11800c9000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS018"        ,	   0x11800c9000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS019"        ,	   0x11800c9000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS020"        ,	   0x11800c90007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS021"        ,	   0x11800c90007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS022"        ,	   0x11800c90007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO1_IMSG_STATUS023"        ,	   0x11800c90007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SRIO0_IMSG_VPORT_THR"        ,	   0x11800c8000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	990},
-	{"SRIO1_IMSG_VPORT_THR"        ,	   0x11800c9000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	990},
-	{"SRIO0_INT_ENABLE"            ,	   0x11800c8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	991},
-	{"SRIO1_INT_ENABLE"            ,	   0x11800c9000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	991},
-	{"SRIO0_INT_INFO0"             ,	   0x11800c8000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	992},
-	{"SRIO1_INT_INFO0"             ,	   0x11800c9000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	992},
-	{"SRIO0_INT_INFO1"             ,	   0x11800c8000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	993},
-	{"SRIO1_INT_INFO1"             ,	   0x11800c9000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	993},
-	{"SRIO0_INT_INFO2"             ,	   0x11800c8000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
-	{"SRIO1_INT_INFO2"             ,	   0x11800c9000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
-	{"SRIO0_INT_INFO3"             ,	   0x11800c8000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
-	{"SRIO1_INT_INFO3"             ,	   0x11800c9000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
-	{"SRIO0_INT_REG"               ,	   0x11800c8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	996},
-	{"SRIO1_INT_REG"               ,	   0x11800c9000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	996},
-	{"SRIO0_IP_FEATURE"            ,	   0x11800c80003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
-	{"SRIO1_IP_FEATURE"            ,	   0x11800c90003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
-	{"SRIO0_MAINT_OP"              ,	   0x11800c8000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_MAINT_OP"              ,	   0x11800c9000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_MAINT_RD_DATA"         ,	   0x11800c8000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_MAINT_RD_DATA"         ,	   0x11800c9000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_MCE_TX_CTL"            ,	   0x11800c8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1000},
-	{"SRIO1_MCE_TX_CTL"            ,	   0x11800c9000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1000},
-	{"SRIO0_MEM_OP_CTRL"           ,	   0x11800c8000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1001},
-	{"SRIO1_MEM_OP_CTRL"           ,	   0x11800c9000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1001},
-	{"SRIO0_OMSG_CTRL000"          ,	   0x11800c8000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
-	{"SRIO0_OMSG_CTRL001"          ,	   0x11800c80004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
-	{"SRIO1_OMSG_CTRL000"          ,	   0x11800c9000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
-	{"SRIO1_OMSG_CTRL001"          ,	   0x11800c90004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
-	{"SRIO0_OMSG_FMP_MR000"        ,	   0x11800c8000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
-	{"SRIO0_OMSG_FMP_MR001"        ,	   0x11800c80004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
-	{"SRIO1_OMSG_FMP_MR000"        ,	   0x11800c9000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
-	{"SRIO1_OMSG_FMP_MR001"        ,	   0x11800c90004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
-	{"SRIO0_OMSG_NMP_MR000"        ,	   0x11800c80004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
-	{"SRIO0_OMSG_NMP_MR001"        ,	   0x11800c80004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
-	{"SRIO1_OMSG_NMP_MR000"        ,	   0x11800c90004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
-	{"SRIO1_OMSG_NMP_MR001"        ,	   0x11800c90004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
-	{"SRIO0_OMSG_PORT000"          ,	   0x11800c8000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
-	{"SRIO0_OMSG_PORT001"          ,	   0x11800c80004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
-	{"SRIO1_OMSG_PORT000"          ,	   0x11800c9000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
-	{"SRIO1_OMSG_PORT001"          ,	   0x11800c90004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
-	{"SRIO0_OMSG_SP_MR000"         ,	   0x11800c8000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
-	{"SRIO0_OMSG_SP_MR001"         ,	   0x11800c80004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
-	{"SRIO1_OMSG_SP_MR000"         ,	   0x11800c9000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
-	{"SRIO1_OMSG_SP_MR001"         ,	   0x11800c90004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
-	{"SRIO0_RX_BELL"               ,	   0x11800c8000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
-	{"SRIO1_RX_BELL"               ,	   0x11800c9000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
-	{"SRIO0_RX_BELL_SEQ"           ,	   0x11800c8000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
-	{"SRIO1_RX_BELL_SEQ"           ,	   0x11800c9000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
-	{"SRIO0_RX_STATUS"             ,	   0x11800c8000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1009},
-	{"SRIO1_RX_STATUS"             ,	   0x11800c9000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1009},
-	{"SRIO0_S2M_TYPE000"           ,	   0x11800c8000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO0_S2M_TYPE001"           ,	   0x11800c8000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO0_S2M_TYPE002"           ,	   0x11800c8000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO0_S2M_TYPE003"           ,	   0x11800c8000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO0_S2M_TYPE004"           ,	   0x11800c80001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO0_S2M_TYPE005"           ,	   0x11800c80001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO0_S2M_TYPE006"           ,	   0x11800c80001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO0_S2M_TYPE007"           ,	   0x11800c80001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO0_S2M_TYPE008"           ,	   0x11800c80001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO0_S2M_TYPE009"           ,	   0x11800c80001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO0_S2M_TYPE010"           ,	   0x11800c80001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO0_S2M_TYPE011"           ,	   0x11800c80001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO0_S2M_TYPE012"           ,	   0x11800c80001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO0_S2M_TYPE013"           ,	   0x11800c80001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO0_S2M_TYPE014"           ,	   0x11800c80001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO0_S2M_TYPE015"           ,	   0x11800c80001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO1_S2M_TYPE000"           ,	   0x11800c9000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO1_S2M_TYPE001"           ,	   0x11800c9000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO1_S2M_TYPE002"           ,	   0x11800c9000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO1_S2M_TYPE003"           ,	   0x11800c9000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO1_S2M_TYPE004"           ,	   0x11800c90001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO1_S2M_TYPE005"           ,	   0x11800c90001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO1_S2M_TYPE006"           ,	   0x11800c90001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO1_S2M_TYPE007"           ,	   0x11800c90001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO1_S2M_TYPE008"           ,	   0x11800c90001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO1_S2M_TYPE009"           ,	   0x11800c90001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO1_S2M_TYPE010"           ,	   0x11800c90001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO1_S2M_TYPE011"           ,	   0x11800c90001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO1_S2M_TYPE012"           ,	   0x11800c90001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO1_S2M_TYPE013"           ,	   0x11800c90001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO1_S2M_TYPE014"           ,	   0x11800c90001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO1_S2M_TYPE015"           ,	   0x11800c90001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO0_SEQ"                   ,	   0x11800c8000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
-	{"SRIO1_SEQ"                   ,	   0x11800c9000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
-	{"SRIO0_STATUS_REG"            ,	   0x11800c8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
-	{"SRIO1_STATUS_REG"            ,	   0x11800c9000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
-	{"SRIO0_TAG_CTRL"              ,	   0x11800c8000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
-	{"SRIO1_TAG_CTRL"              ,	   0x11800c9000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
-	{"SRIO0_TLP_CREDITS"           ,	   0x11800c8000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
-	{"SRIO1_TLP_CREDITS"           ,	   0x11800c9000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
-	{"SRIO0_TX_BELL"               ,	   0x11800c8000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
-	{"SRIO1_TX_BELL"               ,	   0x11800c9000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
-	{"SRIO0_TX_BELL_INFO"          ,	   0x11800c8000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
-	{"SRIO1_TX_BELL_INFO"          ,	   0x11800c9000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
-	{"SRIO0_TX_CTRL"               ,	   0x11800c8000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
-	{"SRIO1_TX_CTRL"               ,	   0x11800c9000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
-	{"SRIO0_TX_STATUS"             ,	   0x11800c8000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
-	{"SRIO1_TX_STATUS"             ,	   0x11800c9000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
-	{"SRIOMAINT0_ASMBLY_ID"        ,	               0x8ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1019},
-	{"SRIOMAINT1_ASMBLY_ID"        ,	               0x8ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1019},
-	{"SRIOMAINT0_ASMBLY_INFO"      ,	               0xcull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1020},
-	{"SRIOMAINT1_ASMBLY_INFO"      ,	               0xcull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1020},
-	{"SRIOMAINT0_BAR1_IDX000"      ,	          0x200010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT0_BAR1_IDX001"      ,	          0x200014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT0_BAR1_IDX002"      ,	          0x200018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT0_BAR1_IDX003"      ,	          0x20001cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT0_BAR1_IDX004"      ,	          0x200020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT0_BAR1_IDX005"      ,	          0x200024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT0_BAR1_IDX006"      ,	          0x200028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT0_BAR1_IDX007"      ,	          0x20002cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT0_BAR1_IDX008"      ,	          0x200030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT0_BAR1_IDX009"      ,	          0x200034ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT0_BAR1_IDX010"      ,	          0x200038ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT0_BAR1_IDX011"      ,	          0x20003cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT0_BAR1_IDX012"      ,	          0x200040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT0_BAR1_IDX013"      ,	          0x200044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT0_BAR1_IDX014"      ,	          0x200048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT0_BAR1_IDX015"      ,	          0x20004cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT1_BAR1_IDX000"      ,	          0x200010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT1_BAR1_IDX001"      ,	          0x200014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT1_BAR1_IDX002"      ,	          0x200018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT1_BAR1_IDX003"      ,	          0x20001cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT1_BAR1_IDX004"      ,	          0x200020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT1_BAR1_IDX005"      ,	          0x200024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT1_BAR1_IDX006"      ,	          0x200028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT1_BAR1_IDX007"      ,	          0x20002cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT1_BAR1_IDX008"      ,	          0x200030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT1_BAR1_IDX009"      ,	          0x200034ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT1_BAR1_IDX010"      ,	          0x200038ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT1_BAR1_IDX011"      ,	          0x20003cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT1_BAR1_IDX012"      ,	          0x200040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT1_BAR1_IDX013"      ,	          0x200044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT1_BAR1_IDX014"      ,	          0x200048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT1_BAR1_IDX015"      ,	          0x20004cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
-	{"SRIOMAINT0_BELL_STATUS"      ,	          0x200080ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1022},
-	{"SRIOMAINT1_BELL_STATUS"      ,	          0x200080ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1022},
-	{"SRIOMAINT0_COMP_TAG"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1023},
-	{"SRIOMAINT1_COMP_TAG"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1023},
-	{"SRIOMAINT0_CORE_ENABLES"     ,	          0x200070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1024},
-	{"SRIOMAINT1_CORE_ENABLES"     ,	          0x200070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1024},
-	{"SRIOMAINT0_DEV_ID"           ,	               0x0ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1025},
-	{"SRIOMAINT1_DEV_ID"           ,	               0x0ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1025},
-	{"SRIOMAINT0_DEV_REV"          ,	               0x4ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1026},
-	{"SRIOMAINT1_DEV_REV"          ,	               0x4ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1026},
-	{"SRIOMAINT0_DST_OPS"          ,	              0x1cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
-	{"SRIOMAINT1_DST_OPS"          ,	              0x1cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
-	{"SRIOMAINT0_ERB_ATTR_CAPT"    ,	            0x2048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1028},
-	{"SRIOMAINT1_ERB_ATTR_CAPT"    ,	            0x2048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1028},
-	{"SRIOMAINT0_ERB_ERR_DET"      ,	            0x2040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1029},
-	{"SRIOMAINT1_ERB_ERR_DET"      ,	            0x2040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1029},
-	{"SRIOMAINT0_ERB_ERR_RATE"     ,	            0x2068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1030},
-	{"SRIOMAINT1_ERB_ERR_RATE"     ,	            0x2068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1030},
-	{"SRIOMAINT0_ERB_ERR_RATE_EN"  ,	            0x2044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1031},
-	{"SRIOMAINT1_ERB_ERR_RATE_EN"  ,	            0x2044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1031},
-	{"SRIOMAINT0_ERB_ERR_RATE_THR" ,	            0x206cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1032},
-	{"SRIOMAINT1_ERB_ERR_RATE_THR" ,	            0x206cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1032},
-	{"SRIOMAINT0_ERB_HDR"          ,	            0x2000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1033},
-	{"SRIOMAINT1_ERB_HDR"          ,	            0x2000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1033},
-	{"SRIOMAINT0_ERB_LT_ADDR_CAPT_H",	            0x2010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1034},
-	{"SRIOMAINT1_ERB_LT_ADDR_CAPT_H",	            0x2010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1034},
-	{"SRIOMAINT0_ERB_LT_ADDR_CAPT_L",	            0x2014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1035},
-	{"SRIOMAINT1_ERB_LT_ADDR_CAPT_L",	            0x2014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1035},
-	{"SRIOMAINT0_ERB_LT_CTRL_CAPT" ,	            0x201cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1036},
-	{"SRIOMAINT1_ERB_LT_CTRL_CAPT" ,	            0x201cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1036},
-	{"SRIOMAINT0_ERB_LT_DEV_ID"    ,	            0x2028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1037},
-	{"SRIOMAINT1_ERB_LT_DEV_ID"    ,	            0x2028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1037},
-	{"SRIOMAINT0_ERB_LT_DEV_ID_CAPT",	            0x2018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1038},
-	{"SRIOMAINT1_ERB_LT_DEV_ID_CAPT",	            0x2018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1038},
-	{"SRIOMAINT0_ERB_LT_ERR_DET"   ,	            0x2008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT1_ERB_LT_ERR_DET"   ,	            0x2008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT0_ERB_LT_ERR_EN"    ,	            0x200cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1040},
-	{"SRIOMAINT1_ERB_LT_ERR_EN"    ,	            0x200cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1040},
-	{"SRIOMAINT0_ERB_PACK_CAPT_1"  ,	            0x2050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1041},
-	{"SRIOMAINT1_ERB_PACK_CAPT_1"  ,	            0x2050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1041},
-	{"SRIOMAINT0_ERB_PACK_CAPT_2"  ,	            0x2054ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1042},
-	{"SRIOMAINT1_ERB_PACK_CAPT_2"  ,	            0x2054ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1042},
-	{"SRIOMAINT0_ERB_PACK_CAPT_3"  ,	            0x2058ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1043},
-	{"SRIOMAINT1_ERB_PACK_CAPT_3"  ,	            0x2058ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1043},
-	{"SRIOMAINT0_ERB_PACK_SYM_CAPT",	            0x204cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1044},
-	{"SRIOMAINT1_ERB_PACK_SYM_CAPT",	            0x204cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1044},
-	{"SRIOMAINT0_HB_DEV_ID_LOCK"   ,	              0x68ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
-	{"SRIOMAINT1_HB_DEV_ID_LOCK"   ,	              0x68ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
-	{"SRIOMAINT0_IR_BUFFER_CONFIG" ,	          0x102000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1046},
-	{"SRIOMAINT1_IR_BUFFER_CONFIG" ,	          0x102000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1046},
-	{"SRIOMAINT0_IR_PD_PHY_CTRL"   ,	          0x107028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1047},
-	{"SRIOMAINT1_IR_PD_PHY_CTRL"   ,	          0x107028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1047},
-	{"SRIOMAINT0_IR_PD_PHY_STAT"   ,	          0x10702cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1048},
-	{"SRIOMAINT1_IR_PD_PHY_STAT"   ,	          0x10702cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1048},
-	{"SRIOMAINT0_IR_PI_PHY_CTRL"   ,	          0x107020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1049},
-	{"SRIOMAINT1_IR_PI_PHY_CTRL"   ,	          0x107020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1049},
-	{"SRIOMAINT0_IR_PI_PHY_STAT"   ,	          0x107024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1050},
-	{"SRIOMAINT1_IR_PI_PHY_STAT"   ,	          0x107024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1050},
-	{"SRIOMAINT0_IR_SP_RX_CTRL"    ,	          0x10700cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1051},
-	{"SRIOMAINT1_IR_SP_RX_CTRL"    ,	          0x10700cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1051},
-	{"SRIOMAINT0_IR_SP_RX_DATA"    ,	          0x107014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1052},
-	{"SRIOMAINT1_IR_SP_RX_DATA"    ,	          0x107014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1052},
-	{"SRIOMAINT0_IR_SP_RX_STAT"    ,	          0x107010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1053},
-	{"SRIOMAINT1_IR_SP_RX_STAT"    ,	          0x107010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1053},
-	{"SRIOMAINT0_IR_SP_TX_CTRL"    ,	          0x107000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1054},
-	{"SRIOMAINT1_IR_SP_TX_CTRL"    ,	          0x107000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1054},
-	{"SRIOMAINT0_IR_SP_TX_DATA"    ,	          0x107008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1055},
-	{"SRIOMAINT1_IR_SP_TX_DATA"    ,	          0x107008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1055},
-	{"SRIOMAINT0_IR_SP_TX_STAT"    ,	          0x107004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1056},
-	{"SRIOMAINT1_IR_SP_TX_STAT"    ,	          0x107004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1056},
-	{"SRIOMAINT0_LANE_000_STATUS_0",	            0x1010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
-	{"SRIOMAINT0_LANE_001_STATUS_0",	            0x1030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
-	{"SRIOMAINT0_LANE_002_STATUS_0",	            0x1050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
-	{"SRIOMAINT0_LANE_003_STATUS_0",	            0x1070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
-	{"SRIOMAINT1_LANE_000_STATUS_0",	            0x1010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
-	{"SRIOMAINT1_LANE_001_STATUS_0",	            0x1030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
-	{"SRIOMAINT1_LANE_002_STATUS_0",	            0x1050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
-	{"SRIOMAINT1_LANE_003_STATUS_0",	            0x1070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
-	{"SRIOMAINT0_LCS_BA0"          ,	              0x58ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1058},
-	{"SRIOMAINT1_LCS_BA0"          ,	              0x58ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1058},
-	{"SRIOMAINT0_LCS_BA1"          ,	              0x5cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1059},
-	{"SRIOMAINT1_LCS_BA1"          ,	              0x5cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1059},
-	{"SRIOMAINT0_M2S_BAR0_START0"  ,	          0x200000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1060},
-	{"SRIOMAINT1_M2S_BAR0_START0"  ,	          0x200000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1060},
-	{"SRIOMAINT0_M2S_BAR0_START1"  ,	          0x200004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1061},
-	{"SRIOMAINT1_M2S_BAR0_START1"  ,	          0x200004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1061},
-	{"SRIOMAINT0_M2S_BAR1_START0"  ,	          0x200008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1062},
-	{"SRIOMAINT1_M2S_BAR1_START0"  ,	          0x200008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1062},
-	{"SRIOMAINT0_M2S_BAR1_START1"  ,	          0x20000cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1063},
-	{"SRIOMAINT1_M2S_BAR1_START1"  ,	          0x20000cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1063},
-	{"SRIOMAINT0_M2S_BAR2_START"   ,	          0x200050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1064},
-	{"SRIOMAINT1_M2S_BAR2_START"   ,	          0x200050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1064},
-	{"SRIOMAINT0_PE_FEAT"          ,	              0x10ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1065},
-	{"SRIOMAINT1_PE_FEAT"          ,	              0x10ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1065},
-	{"SRIOMAINT0_PE_LLC"           ,	              0x4cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1066},
-	{"SRIOMAINT1_PE_LLC"           ,	              0x4cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1066},
-	{"SRIOMAINT0_PORT_0_CTL"       ,	             0x15cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1067},
-	{"SRIOMAINT1_PORT_0_CTL"       ,	             0x15cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1067},
-	{"SRIOMAINT0_PORT_0_CTL2"      ,	             0x154ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1068},
-	{"SRIOMAINT1_PORT_0_CTL2"      ,	             0x154ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1068},
-	{"SRIOMAINT0_PORT_0_ERR_STAT"  ,	             0x158ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1069},
-	{"SRIOMAINT1_PORT_0_ERR_STAT"  ,	             0x158ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1069},
-	{"SRIOMAINT0_PORT_GEN_CTL"     ,	             0x13cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1070},
-	{"SRIOMAINT1_PORT_GEN_CTL"     ,	             0x13cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1070},
-	{"SRIOMAINT0_PORT_LT_CTL"      ,	             0x120ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1071},
-	{"SRIOMAINT1_PORT_LT_CTL"      ,	             0x120ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1071},
-	{"SRIOMAINT0_PORT_MBH0"        ,	             0x100ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1072},
-	{"SRIOMAINT1_PORT_MBH0"        ,	             0x100ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1072},
-	{"SRIOMAINT0_PORT_RT_CTL"      ,	             0x124ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1073},
-	{"SRIOMAINT1_PORT_RT_CTL"      ,	             0x124ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1073},
-	{"SRIOMAINT0_PRI_DEV_ID"       ,	              0x60ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1074},
-	{"SRIOMAINT1_PRI_DEV_ID"       ,	              0x60ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1074},
-	{"SRIOMAINT0_SEC_DEV_CTRL"     ,	          0x200064ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1075},
-	{"SRIOMAINT1_SEC_DEV_CTRL"     ,	          0x200064ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1075},
-	{"SRIOMAINT0_SEC_DEV_ID"       ,	          0x200060ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
-	{"SRIOMAINT1_SEC_DEV_ID"       ,	          0x200060ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
-	{"SRIOMAINT0_SERIAL_LANE_HDR"  ,	            0x1000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1077},
-	{"SRIOMAINT1_SERIAL_LANE_HDR"  ,	            0x1000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1077},
-	{"SRIOMAINT0_SRC_OPS"          ,	              0x18ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1078},
-	{"SRIOMAINT1_SRC_OPS"          ,	              0x18ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1078},
-	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1079},
-	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1080},
-	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1081},
-	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1082},
-	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1083},
-	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1084},
-	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1085},
-	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1086},
-	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1087},
-	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1088},
-	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1089},
-	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1090},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
-	{"TRA_CYCLES_SINCE1"           ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1092},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1093},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1094},
-	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1095},
-	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1096},
-	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1097},
-	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1098},
-	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1099},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1100},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1101},
-	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1102},
-	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1103},
-	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1104},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1105},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1106},
-	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1107},
-	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1108},
-	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1109},
-	{"UAHC0_EHCI_ASYNCLISTADDR"    ,	   0x16f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1110},
-	{"UAHC0_EHCI_CONFIGFLAG"       ,	   0x16f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1111},
-	{"UAHC0_EHCI_CTRLDSSEGMENT"    ,	   0x16f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1112},
-	{"UAHC0_EHCI_FRINDEX"          ,	   0x16f000000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1113},
-	{"UAHC0_EHCI_HCCAPBASE"        ,	   0x16f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1114},
-	{"UAHC0_EHCI_HCCPARAMS"        ,	   0x16f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1115},
-	{"UAHC0_EHCI_HCSPARAMS"        ,	   0x16f0000000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1116},
-	{"UAHC0_EHCI_INSNREG00"        ,	   0x16f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1117},
-	{"UAHC0_EHCI_INSNREG03"        ,	   0x16f000000009cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1118},
-	{"UAHC0_EHCI_INSNREG04"        ,	   0x16f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1119},
-	{"UAHC0_EHCI_INSNREG06"        ,	   0x16f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1120},
-	{"UAHC0_EHCI_INSNREG07"        ,	   0x16f00000000ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	1121},
-	{"UAHC0_EHCI_PERIODICLISTBASE" ,	   0x16f0000000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1122},
-	{"UAHC0_EHCI_PORTSC001"        ,	   0x16f0000000054ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1123},
-	{"UAHC0_EHCI_PORTSC002"        ,	   0x16f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1123},
-	{"UAHC0_EHCI_USBCMD"           ,	   0x16f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1124},
-	{"UAHC0_EHCI_USBINTR"          ,	   0x16f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1125},
-	{"UAHC0_EHCI_USBSTS"           ,	   0x16f0000000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1126},
-	{"UAHC0_OHCI0_HCBULKCURRENTED" ,	   0x16f000000042cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1127},
-	{"UAHC0_OHCI0_HCBULKHEADED"    ,	   0x16f0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1128},
-	{"UAHC0_OHCI0_HCCOMMANDSTATUS" ,	   0x16f0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1129},
-	{"UAHC0_OHCI0_HCCONTROL"       ,	   0x16f0000000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1130},
-	{"UAHC0_OHCI0_HCCONTROLCURRENTED",	   0x16f0000000424ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1131},
-	{"UAHC0_OHCI0_HCCONTROLHEADED" ,	   0x16f0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1132},
-	{"UAHC0_OHCI0_HCDONEHEAD"      ,	   0x16f0000000430ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1133},
-	{"UAHC0_OHCI0_HCFMINTERVAL"    ,	   0x16f0000000434ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1134},
-	{"UAHC0_OHCI0_HCFMNUMBER"      ,	   0x16f000000043cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1135},
-	{"UAHC0_OHCI0_HCFMREMAINING"   ,	   0x16f0000000438ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1136},
-	{"UAHC0_OHCI0_HCHCCA"          ,	   0x16f0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1137},
-	{"UAHC0_OHCI0_HCINTERRUPTDISABLE",	   0x16f0000000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1138},
-	{"UAHC0_OHCI0_HCINTERRUPTENABLE",	   0x16f0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1139},
-	{"UAHC0_OHCI0_HCINTERRUPTSTATUS",	   0x16f000000040cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1140},
-	{"UAHC0_OHCI0_HCLSTHRESHOLD"   ,	   0x16f0000000444ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1141},
-	{"UAHC0_OHCI0_HCPERIODCURRENTED",	   0x16f000000041cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1142},
-	{"UAHC0_OHCI0_HCPERIODICSTART" ,	   0x16f0000000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1143},
-	{"UAHC0_OHCI0_HCREVISION"      ,	   0x16f0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1144},
-	{"UAHC0_OHCI0_HCRHDESCRIPTORA" ,	   0x16f0000000448ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1145},
-	{"UAHC0_OHCI0_HCRHDESCRIPTORB" ,	   0x16f000000044cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1146},
-	{"UAHC0_OHCI0_HCRHPORTSTATUS001",	   0x16f0000000454ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1147},
-	{"UAHC0_OHCI0_HCRHPORTSTATUS002",	   0x16f0000000458ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1147},
-	{"UAHC0_OHCI0_HCRHSTATUS"      ,	   0x16f0000000450ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1148},
-	{"UAHC0_OHCI0_INSNREG06"       ,	   0x16f0000000498ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1149},
-	{"UAHC0_OHCI0_INSNREG07"       ,	   0x16f000000049cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1150},
-	{"UCTL0_BIST_STATUS"           ,	   0x118006f0000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1151},
-	{"UCTL0_CLK_RST_CTL"           ,	   0x118006f000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1152},
-	{"UCTL0_EHCI_CTL"              ,	   0x118006f000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1153},
-	{"UCTL0_EHCI_FLA"              ,	   0x118006f0000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1154},
-	{"UCTL0_ERTO_CTL"              ,	   0x118006f000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1155},
-	{"UCTL0_IF_ENA"                ,	   0x118006f000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1156},
-	{"UCTL0_INT_ENA"               ,	   0x118006f000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1157},
-	{"UCTL0_INT_REG"               ,	   0x118006f000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1158},
-	{"UCTL0_OHCI_CTL"              ,	   0x118006f000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1159},
-	{"UCTL0_ORTO_CTL"              ,	   0x118006f000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1160},
-	{"UCTL0_PPAF_WM"               ,	   0x118006f000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1161},
-	{"UCTL0_UPHY_CTL_STATUS"       ,	   0x118006f000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1162},
-	{"UCTL0_UPHY_PORT000_CTL_STATUS",	   0x118006f000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1163},
-	{"UCTL0_UPHY_PORT001_CTL_STATUS",	   0x118006f000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1163},
-	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1164},
-	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1165},
-	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1166},
-	{"ZIP_CONSTANTS"               ,	   0x11800380000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1167},
-	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1168},
-	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1169},
-	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1170},
-	{"ZIP_THROTTLE"                ,	   0x1180038000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1171},
+	{"PIP_STAT10_PRT0"             ,	   0x11800a0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT10_PRT1"             ,	   0x11800a0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT10_PRT2"             ,	   0x11800a00014a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT10_PRT3"             ,	   0x11800a00014b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT10_PRT32"            ,	   0x11800a0001680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT10_PRT33"            ,	   0x11800a0001690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT10_PRT34"            ,	   0x11800a00016a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT10_PRT35"            ,	   0x11800a00016b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT10_PRT36"            ,	   0x11800a00016c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT10_PRT37"            ,	   0x11800a00016d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT10_PRT38"            ,	   0x11800a00016e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT10_PRT39"            ,	   0x11800a00016f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT11_PRT0"             ,	   0x11800a0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT11_PRT1"             ,	   0x11800a0001498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT11_PRT2"             ,	   0x11800a00014a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT11_PRT3"             ,	   0x11800a00014b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT11_PRT32"            ,	   0x11800a0001688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT11_PRT33"            ,	   0x11800a0001698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT11_PRT34"            ,	   0x11800a00016a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT11_PRT35"            ,	   0x11800a00016b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT11_PRT36"            ,	   0x11800a00016c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT11_PRT37"            ,	   0x11800a00016d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT11_PRT38"            ,	   0x11800a00016e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT11_PRT39"            ,	   0x11800a00016f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT1_PRT3"              ,	   0x11800a00008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT1_PRT32"             ,	   0x11800a0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT1_PRT33"             ,	   0x11800a0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT1_PRT34"             ,	   0x11800a00012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT1_PRT35"             ,	   0x11800a00012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT1_PRT36"             ,	   0x11800a0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT1_PRT37"             ,	   0x11800a0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT1_PRT38"             ,	   0x11800a00013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT1_PRT39"             ,	   0x11800a0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT2_PRT3"              ,	   0x11800a0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT2_PRT32"             ,	   0x11800a0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT2_PRT33"             ,	   0x11800a0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT2_PRT34"             ,	   0x11800a00012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT2_PRT35"             ,	   0x11800a0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT2_PRT36"             ,	   0x11800a0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT2_PRT37"             ,	   0x11800a00013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT2_PRT38"             ,	   0x11800a00013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT2_PRT39"             ,	   0x11800a0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT3_PRT3"              ,	   0x11800a0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT3_PRT32"             ,	   0x11800a0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT3_PRT33"             ,	   0x11800a0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT3_PRT34"             ,	   0x11800a00012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT3_PRT35"             ,	   0x11800a0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT3_PRT36"             ,	   0x11800a0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT3_PRT37"             ,	   0x11800a00013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT3_PRT38"             ,	   0x11800a00013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT3_PRT39"             ,	   0x11800a0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT4_PRT3"              ,	   0x11800a0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT4_PRT32"             ,	   0x11800a0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT4_PRT33"             ,	   0x11800a0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT4_PRT34"             ,	   0x11800a00012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT4_PRT35"             ,	   0x11800a0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT4_PRT36"             ,	   0x11800a0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT4_PRT37"             ,	   0x11800a00013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT4_PRT38"             ,	   0x11800a0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT4_PRT39"             ,	   0x11800a0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT5_PRT3"              ,	   0x11800a0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT5_PRT32"             ,	   0x11800a0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT5_PRT33"             ,	   0x11800a0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT5_PRT34"             ,	   0x11800a00012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT5_PRT35"             ,	   0x11800a0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT5_PRT36"             ,	   0x11800a0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT5_PRT37"             ,	   0x11800a00013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT5_PRT38"             ,	   0x11800a0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT5_PRT39"             ,	   0x11800a0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT6_PRT3"              ,	   0x11800a0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT6_PRT32"             ,	   0x11800a0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT6_PRT33"             ,	   0x11800a0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT6_PRT34"             ,	   0x11800a00012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT6_PRT35"             ,	   0x11800a0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT6_PRT36"             ,	   0x11800a0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT6_PRT37"             ,	   0x11800a00013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT6_PRT38"             ,	   0x11800a0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT6_PRT39"             ,	   0x11800a0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT7_PRT3"              ,	   0x11800a0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT7_PRT32"             ,	   0x11800a0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT7_PRT33"             ,	   0x11800a0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT7_PRT34"             ,	   0x11800a00012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT7_PRT35"             ,	   0x11800a0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT7_PRT36"             ,	   0x11800a0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT7_PRT37"             ,	   0x11800a00013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT7_PRT38"             ,	   0x11800a0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT7_PRT39"             ,	   0x11800a0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT8_PRT3"              ,	   0x11800a0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT8_PRT32"             ,	   0x11800a0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT8_PRT33"             ,	   0x11800a0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT8_PRT34"             ,	   0x11800a00012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT8_PRT35"             ,	   0x11800a0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT8_PRT36"             ,	   0x11800a0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT8_PRT37"             ,	   0x11800a00013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT8_PRT38"             ,	   0x11800a0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT8_PRT39"             ,	   0x11800a0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT9_PRT3"              ,	   0x11800a0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT9_PRT32"             ,	   0x11800a0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT9_PRT33"             ,	   0x11800a0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT9_PRT34"             ,	   0x11800a00012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT9_PRT35"             ,	   0x11800a0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT9_PRT36"             ,	   0x11800a0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT9_PRT37"             ,	   0x11800a00013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT9_PRT38"             ,	   0x11800a0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT9_PRT39"             ,	   0x11800a0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800a0001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800a0001e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800a0001e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800a0001e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800a0001e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_ERRS36"         ,	   0x11800a0001e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_ERRS37"         ,	   0x11800a0001eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_ERRS38"         ,	   0x11800a0001ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_ERRS39"         ,	   0x11800a0001ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_ERRS40"         ,	   0x11800a0001f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_ERRS41"         ,	   0x11800a0001f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_ERRS42"         ,	   0x11800a0001f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_ERRS43"         ,	   0x11800a0001f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800a0001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800a0001e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800a0001e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800a0001e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800a0001e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT_INB_OCTS36"         ,	   0x11800a0001e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT_INB_OCTS37"         ,	   0x11800a0001ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT_INB_OCTS38"         ,	   0x11800a0001ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT_INB_OCTS39"         ,	   0x11800a0001ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT_INB_OCTS40"         ,	   0x11800a0001f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT_INB_OCTS41"         ,	   0x11800a0001f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT_INB_OCTS42"         ,	   0x11800a0001f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT_INB_OCTS43"         ,	   0x11800a0001f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800a0001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800a0001e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800a0001e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800a0001e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800a0001e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT_INB_PKTS36"         ,	   0x11800a0001e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT_INB_PKTS37"         ,	   0x11800a0001ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT_INB_PKTS38"         ,	   0x11800a0001ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT_INB_PKTS39"         ,	   0x11800a0001ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT_INB_PKTS40"         ,	   0x11800a0001f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT_INB_PKTS41"         ,	   0x11800a0001f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT_INB_PKTS42"         ,	   0x11800a0001f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT_INB_PKTS43"         ,	   0x11800a0001f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_XSTAT0_PRT40"            ,	   0x11800a0002000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_XSTAT0_PRT41"            ,	   0x11800a0002050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_XSTAT0_PRT42"            ,	   0x11800a00020a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_XSTAT0_PRT43"            ,	   0x11800a00020f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_XSTAT10_PRT40"           ,	   0x11800a0001700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_XSTAT10_PRT41"           ,	   0x11800a0001710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_XSTAT10_PRT42"           ,	   0x11800a0001720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_XSTAT10_PRT43"           ,	   0x11800a0001730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_XSTAT11_PRT40"           ,	   0x11800a0001708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_XSTAT11_PRT41"           ,	   0x11800a0001718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_XSTAT11_PRT42"           ,	   0x11800a0001728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_XSTAT11_PRT43"           ,	   0x11800a0001738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_XSTAT1_PRT40"            ,	   0x11800a0002008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_XSTAT1_PRT41"            ,	   0x11800a0002058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_XSTAT1_PRT42"            ,	   0x11800a00020a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_XSTAT1_PRT43"            ,	   0x11800a00020f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_XSTAT2_PRT40"            ,	   0x11800a0002010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_XSTAT2_PRT41"            ,	   0x11800a0002060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_XSTAT2_PRT42"            ,	   0x11800a00020b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_XSTAT2_PRT43"            ,	   0x11800a0002100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_XSTAT3_PRT40"            ,	   0x11800a0002018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"PIP_XSTAT3_PRT41"            ,	   0x11800a0002068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"PIP_XSTAT3_PRT42"            ,	   0x11800a00020b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"PIP_XSTAT3_PRT43"            ,	   0x11800a0002108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"PIP_XSTAT4_PRT40"            ,	   0x11800a0002020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PIP_XSTAT4_PRT41"            ,	   0x11800a0002070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PIP_XSTAT4_PRT42"            ,	   0x11800a00020c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PIP_XSTAT4_PRT43"            ,	   0x11800a0002110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PIP_XSTAT5_PRT40"            ,	   0x11800a0002028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PIP_XSTAT5_PRT41"            ,	   0x11800a0002078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PIP_XSTAT5_PRT42"            ,	   0x11800a00020c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PIP_XSTAT5_PRT43"            ,	   0x11800a0002118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PIP_XSTAT6_PRT40"            ,	   0x11800a0002030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PIP_XSTAT6_PRT41"            ,	   0x11800a0002080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PIP_XSTAT6_PRT42"            ,	   0x11800a00020d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PIP_XSTAT6_PRT43"            ,	   0x11800a0002120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PIP_XSTAT7_PRT40"            ,	   0x11800a0002038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PIP_XSTAT7_PRT41"            ,	   0x11800a0002088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PIP_XSTAT7_PRT42"            ,	   0x11800a00020d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PIP_XSTAT7_PRT43"            ,	   0x11800a0002128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PIP_XSTAT8_PRT40"            ,	   0x11800a0002040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PIP_XSTAT8_PRT41"            ,	   0x11800a0002090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PIP_XSTAT8_PRT42"            ,	   0x11800a00020e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PIP_XSTAT8_PRT43"            ,	   0x11800a0002130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PIP_XSTAT9_PRT40"            ,	   0x11800a0002048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"PIP_XSTAT9_PRT41"            ,	   0x11800a0002098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"PIP_XSTAT9_PRT42"            ,	   0x11800a00020e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"PIP_XSTAT9_PRT43"            ,	   0x11800a0002138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
+	{"PKO_MEM_DEBUG14"             ,	   0x1180050001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	817},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
+	{"PKO_MEM_PORT_PTRS"           ,	   0x1180050001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	819},
+	{"PKO_MEM_PORT_QOS"            ,	   0x1180050001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	820},
+	{"PKO_MEM_PORT_RATE0"          ,	   0x1180050001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	821},
+	{"PKO_MEM_PORT_RATE1"          ,	   0x1180050001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	822},
+	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	823},
+	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PKO_REG_PREEMPT"             ,	   0x1180050000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PKO_REG_QUEUE_PREEMPT"       ,	   0x1180050000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PKO_REG_TIMESTAMP"           ,	   0x1180050000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	843},
+	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	844},
+	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
+	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	846},
+	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	847},
+	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	847},
+	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	847},
+	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	847},
+	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	847},
+	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	847},
+	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	847},
+	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	847},
+	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	848},
+	{"POW_IQ_INT"                  ,	   0x1670000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"POW_IQ_INT_EN"               ,	   0x1670000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
+	{"POW_IQ_THR0"                 ,	   0x16700000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"POW_IQ_THR1"                 ,	   0x16700000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"POW_IQ_THR2"                 ,	   0x16700000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"POW_IQ_THR3"                 ,	   0x16700000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"POW_IQ_THR4"                 ,	   0x16700000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"POW_IQ_THR5"                 ,	   0x16700000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"POW_IQ_THR6"                 ,	   0x16700000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"POW_IQ_THR7"                 ,	   0x16700000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	852},
+	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
+	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
+	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	855},
+	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	855},
+	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	855},
+	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	855},
+	{"POW_PP_GRP_MSK4"             ,	   0x1670000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	855},
+	{"POW_PP_GRP_MSK5"             ,	   0x1670000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	855},
+	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
+	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
+	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
+	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
+	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
+	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
+	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
+	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
+	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	860},
+	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	860},
+	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	860},
+	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	860},
+	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	860},
+	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	860},
+	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	860},
+	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	860},
+	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	861},
+	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	863},
+	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	866},
+	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	867},
+	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	868},
+	{"RAD_REG_BIST_RESULT"         ,	   0x1180070000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	869},
+	{"RAD_REG_CMD_BUF"             ,	   0x1180070000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	870},
+	{"RAD_REG_CTL"                 ,	   0x1180070000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	871},
+	{"RAD_REG_DEBUG0"              ,	   0x1180070000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"RAD_REG_DEBUG1"              ,	   0x1180070000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	873},
+	{"RAD_REG_DEBUG10"             ,	   0x1180070000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	874},
+	{"RAD_REG_DEBUG11"             ,	   0x1180070000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	875},
+	{"RAD_REG_DEBUG12"             ,	   0x1180070000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	876},
+	{"RAD_REG_DEBUG2"              ,	   0x1180070000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	877},
+	{"RAD_REG_DEBUG3"              ,	   0x1180070000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	878},
+	{"RAD_REG_DEBUG4"              ,	   0x1180070000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
+	{"RAD_REG_DEBUG5"              ,	   0x1180070000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
+	{"RAD_REG_DEBUG6"              ,	   0x1180070000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
+	{"RAD_REG_DEBUG7"              ,	   0x1180070000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
+	{"RAD_REG_DEBUG8"              ,	   0x1180070000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
+	{"RAD_REG_DEBUG9"              ,	   0x1180070000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
+	{"RAD_REG_ERROR"               ,	   0x1180070000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
+	{"RAD_REG_INT_MASK"            ,	   0x1180070000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	886},
+	{"RAD_REG_POLYNOMIAL"          ,	   0x1180070000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	887},
+	{"RAD_REG_READ_IDX"            ,	   0x1180070000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	888},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	889},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	890},
+	{"RNM_EER_DBG"                 ,	   0x1180040000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	891},
+	{"RNM_EER_KEY"                 ,	   0x1180040000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	892},
+	{"SLI_BIST_STATUS"             ,	   0x11f0000010580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	893},
+	{"SLI_CTL_PORT0"               ,	   0x11f0000010050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	894},
+	{"SLI_CTL_PORT1"               ,	   0x11f0000010060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	894},
+	{"SLI_CTL_STATUS"              ,	   0x11f0000010570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	895},
+	{"SLI_DATA_OUT_CNT"            ,	   0x11f00000105f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	896},
+	{"SLI_DBG_DATA"                ,	   0x11f0000010310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	897},
+	{"SLI_DBG_SELECT"              ,	   0x11f0000010300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	898},
+	{"SLI_DMA0_CNT"                ,	   0x11f0000010400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	899},
+	{"SLI_DMA1_CNT"                ,	   0x11f0000010410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	899},
+	{"SLI_DMA0_INT_LEVEL"          ,	   0x11f00000103e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	900},
+	{"SLI_DMA1_INT_LEVEL"          ,	   0x11f00000103f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	900},
+	{"SLI_DMA0_TIM"                ,	   0x11f0000010420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	901},
+	{"SLI_DMA1_TIM"                ,	   0x11f0000010430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	901},
+	{"SLI_INT_ENB_CIU"             ,	   0x11f0000013cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	902},
+	{"SLI_INT_ENB_PORT0"           ,	   0x11f0000010340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_INT_ENB_PORT1"           ,	   0x11f0000010350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_INT_SUM"                 ,	   0x11f0000010330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	904},
+	{"SLI_LAST_WIN_RDATA0"         ,	   0x11f0000010600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	905},
+	{"SLI_LAST_WIN_RDATA1"         ,	   0x11f0000010610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	906},
+	{"SLI_MAC_CREDIT_CNT"          ,	   0x11f0000013d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	907},
+	{"SLI_MEM_ACCESS_CTL"          ,	   0x11f00000102f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	908},
+	{"SLI_MEM_ACCESS_SUBID12"      ,	   0x11f00000100e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_MEM_ACCESS_SUBID13"      ,	   0x11f00000100f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_MEM_ACCESS_SUBID14"      ,	   0x11f0000010100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_MEM_ACCESS_SUBID15"      ,	   0x11f0000010110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_MEM_ACCESS_SUBID16"      ,	   0x11f0000010120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_MEM_ACCESS_SUBID17"      ,	   0x11f0000010130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_MEM_ACCESS_SUBID18"      ,	   0x11f0000010140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_MEM_ACCESS_SUBID19"      ,	   0x11f0000010150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_MEM_ACCESS_SUBID20"      ,	   0x11f0000010160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_MEM_ACCESS_SUBID21"      ,	   0x11f0000010170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_MEM_ACCESS_SUBID22"      ,	   0x11f0000010180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_MEM_ACCESS_SUBID23"      ,	   0x11f0000010190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_MEM_ACCESS_SUBID24"      ,	   0x11f00000101a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_MEM_ACCESS_SUBID25"      ,	   0x11f00000101b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_MEM_ACCESS_SUBID26"      ,	   0x11f00000101c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_MEM_ACCESS_SUBID27"      ,	   0x11f00000101d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_MSI_ENB0"                ,	   0x11f0000013c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	910},
+	{"SLI_MSI_ENB1"                ,	   0x11f0000013c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	911},
+	{"SLI_MSI_ENB2"                ,	   0x11f0000013c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	912},
+	{"SLI_MSI_ENB3"                ,	   0x11f0000013c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_MSI_RCV0"                ,	   0x11f0000013c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	914},
+	{"SLI_MSI_RCV1"                ,	   0x11f0000013c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	915},
+	{"SLI_MSI_RCV2"                ,	   0x11f0000013c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	916},
+	{"SLI_MSI_RCV3"                ,	   0x11f0000013c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	917},
+	{"SLI_MSI_RD_MAP"              ,	   0x11f0000013ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	918},
+	{"SLI_MSI_W1C_ENB0"            ,	   0x11f0000013cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MSI_W1C_ENB1"            ,	   0x11f0000013d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	920},
+	{"SLI_MSI_W1C_ENB2"            ,	   0x11f0000013d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	921},
+	{"SLI_MSI_W1C_ENB3"            ,	   0x11f0000013d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	922},
+	{"SLI_MSI_W1S_ENB0"            ,	   0x11f0000013d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	923},
+	{"SLI_MSI_W1S_ENB1"            ,	   0x11f0000013d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	924},
+	{"SLI_MSI_W1S_ENB2"            ,	   0x11f0000013d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	925},
+	{"SLI_MSI_W1S_ENB3"            ,	   0x11f0000013d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_MSI_WR_MAP"              ,	   0x11f0000013c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PCIE_MSI_RCV"            ,	   0x11f0000013cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PCIE_MSI_RCV_B1"         ,	   0x11f0000010650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PCIE_MSI_RCV_B2"         ,	   0x11f0000010660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PCIE_MSI_RCV_B3"         ,	   0x11f0000010670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT0_CNTS"               ,	   0x11f0000012400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT1_CNTS"               ,	   0x11f0000012410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT2_CNTS"               ,	   0x11f0000012420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT3_CNTS"               ,	   0x11f0000012430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT4_CNTS"               ,	   0x11f0000012440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT5_CNTS"               ,	   0x11f0000012450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT6_CNTS"               ,	   0x11f0000012460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT7_CNTS"               ,	   0x11f0000012470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT8_CNTS"               ,	   0x11f0000012480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT9_CNTS"               ,	   0x11f0000012490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT10_CNTS"              ,	   0x11f00000124a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT11_CNTS"              ,	   0x11f00000124b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT12_CNTS"              ,	   0x11f00000124c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT13_CNTS"              ,	   0x11f00000124d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT14_CNTS"              ,	   0x11f00000124e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT15_CNTS"              ,	   0x11f00000124f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT16_CNTS"              ,	   0x11f0000012500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT17_CNTS"              ,	   0x11f0000012510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT18_CNTS"              ,	   0x11f0000012520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT19_CNTS"              ,	   0x11f0000012530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT20_CNTS"              ,	   0x11f0000012540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT21_CNTS"              ,	   0x11f0000012550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT22_CNTS"              ,	   0x11f0000012560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT23_CNTS"              ,	   0x11f0000012570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT24_CNTS"              ,	   0x11f0000012580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT25_CNTS"              ,	   0x11f0000012590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT26_CNTS"              ,	   0x11f00000125a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT27_CNTS"              ,	   0x11f00000125b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT28_CNTS"              ,	   0x11f00000125c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT29_CNTS"              ,	   0x11f00000125d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT30_CNTS"              ,	   0x11f00000125e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT31_CNTS"              ,	   0x11f00000125f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT0_IN_BP"              ,	   0x11f0000013800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT1_IN_BP"              ,	   0x11f0000013810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT2_IN_BP"              ,	   0x11f0000013820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT3_IN_BP"              ,	   0x11f0000013830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT4_IN_BP"              ,	   0x11f0000013840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT5_IN_BP"              ,	   0x11f0000013850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT6_IN_BP"              ,	   0x11f0000013860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT7_IN_BP"              ,	   0x11f0000013870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT8_IN_BP"              ,	   0x11f0000013880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT9_IN_BP"              ,	   0x11f0000013890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT10_IN_BP"             ,	   0x11f00000138a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT11_IN_BP"             ,	   0x11f00000138b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT12_IN_BP"             ,	   0x11f00000138c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT13_IN_BP"             ,	   0x11f00000138d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT14_IN_BP"             ,	   0x11f00000138e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT15_IN_BP"             ,	   0x11f00000138f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT16_IN_BP"             ,	   0x11f0000013900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT17_IN_BP"             ,	   0x11f0000013910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT18_IN_BP"             ,	   0x11f0000013920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT19_IN_BP"             ,	   0x11f0000013930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT20_IN_BP"             ,	   0x11f0000013940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT21_IN_BP"             ,	   0x11f0000013950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT22_IN_BP"             ,	   0x11f0000013960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT23_IN_BP"             ,	   0x11f0000013970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT24_IN_BP"             ,	   0x11f0000013980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT25_IN_BP"             ,	   0x11f0000013990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT26_IN_BP"             ,	   0x11f00000139a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT27_IN_BP"             ,	   0x11f00000139b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT28_IN_BP"             ,	   0x11f00000139c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT29_IN_BP"             ,	   0x11f00000139d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT30_IN_BP"             ,	   0x11f00000139e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT31_IN_BP"             ,	   0x11f00000139f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT0_INSTR_BADDR"        ,	   0x11f0000012800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT1_INSTR_BADDR"        ,	   0x11f0000012810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT2_INSTR_BADDR"        ,	   0x11f0000012820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT3_INSTR_BADDR"        ,	   0x11f0000012830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT4_INSTR_BADDR"        ,	   0x11f0000012840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT5_INSTR_BADDR"        ,	   0x11f0000012850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT6_INSTR_BADDR"        ,	   0x11f0000012860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT7_INSTR_BADDR"        ,	   0x11f0000012870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT8_INSTR_BADDR"        ,	   0x11f0000012880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT9_INSTR_BADDR"        ,	   0x11f0000012890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT10_INSTR_BADDR"       ,	   0x11f00000128a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT11_INSTR_BADDR"       ,	   0x11f00000128b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT12_INSTR_BADDR"       ,	   0x11f00000128c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT13_INSTR_BADDR"       ,	   0x11f00000128d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT14_INSTR_BADDR"       ,	   0x11f00000128e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT15_INSTR_BADDR"       ,	   0x11f00000128f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT16_INSTR_BADDR"       ,	   0x11f0000012900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT17_INSTR_BADDR"       ,	   0x11f0000012910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT18_INSTR_BADDR"       ,	   0x11f0000012920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT19_INSTR_BADDR"       ,	   0x11f0000012930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT20_INSTR_BADDR"       ,	   0x11f0000012940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT21_INSTR_BADDR"       ,	   0x11f0000012950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT22_INSTR_BADDR"       ,	   0x11f0000012960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT23_INSTR_BADDR"       ,	   0x11f0000012970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT24_INSTR_BADDR"       ,	   0x11f0000012980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT25_INSTR_BADDR"       ,	   0x11f0000012990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT26_INSTR_BADDR"       ,	   0x11f00000129a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT27_INSTR_BADDR"       ,	   0x11f00000129b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT28_INSTR_BADDR"       ,	   0x11f00000129c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT29_INSTR_BADDR"       ,	   0x11f00000129d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT30_INSTR_BADDR"       ,	   0x11f00000129e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT31_INSTR_BADDR"       ,	   0x11f00000129f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT0_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT1_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT2_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT3_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT4_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT5_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT6_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT7_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT8_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT9_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT10_INSTR_BAOFF_DBELL" ,	   0x11f0000012ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT11_INSTR_BAOFF_DBELL" ,	   0x11f0000012cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT12_INSTR_BAOFF_DBELL" ,	   0x11f0000012cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT13_INSTR_BAOFF_DBELL" ,	   0x11f0000012cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT14_INSTR_BAOFF_DBELL" ,	   0x11f0000012ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT15_INSTR_BAOFF_DBELL" ,	   0x11f0000012cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT16_INSTR_BAOFF_DBELL" ,	   0x11f0000012d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT17_INSTR_BAOFF_DBELL" ,	   0x11f0000012d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT18_INSTR_BAOFF_DBELL" ,	   0x11f0000012d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT19_INSTR_BAOFF_DBELL" ,	   0x11f0000012d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT20_INSTR_BAOFF_DBELL" ,	   0x11f0000012d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT21_INSTR_BAOFF_DBELL" ,	   0x11f0000012d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT22_INSTR_BAOFF_DBELL" ,	   0x11f0000012d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT23_INSTR_BAOFF_DBELL" ,	   0x11f0000012d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT24_INSTR_BAOFF_DBELL" ,	   0x11f0000012d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT25_INSTR_BAOFF_DBELL" ,	   0x11f0000012d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT26_INSTR_BAOFF_DBELL" ,	   0x11f0000012da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT27_INSTR_BAOFF_DBELL" ,	   0x11f0000012db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT28_INSTR_BAOFF_DBELL" ,	   0x11f0000012dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT29_INSTR_BAOFF_DBELL" ,	   0x11f0000012dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT30_INSTR_BAOFF_DBELL" ,	   0x11f0000012de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT31_INSTR_BAOFF_DBELL" ,	   0x11f0000012df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT0_INSTR_FIFO_RSIZE"   ,	   0x11f0000013000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT1_INSTR_FIFO_RSIZE"   ,	   0x11f0000013010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT2_INSTR_FIFO_RSIZE"   ,	   0x11f0000013020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT3_INSTR_FIFO_RSIZE"   ,	   0x11f0000013030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT4_INSTR_FIFO_RSIZE"   ,	   0x11f0000013040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT5_INSTR_FIFO_RSIZE"   ,	   0x11f0000013050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT6_INSTR_FIFO_RSIZE"   ,	   0x11f0000013060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT7_INSTR_FIFO_RSIZE"   ,	   0x11f0000013070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT8_INSTR_FIFO_RSIZE"   ,	   0x11f0000013080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT9_INSTR_FIFO_RSIZE"   ,	   0x11f0000013090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT10_INSTR_FIFO_RSIZE"  ,	   0x11f00000130a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT11_INSTR_FIFO_RSIZE"  ,	   0x11f00000130b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT12_INSTR_FIFO_RSIZE"  ,	   0x11f00000130c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT13_INSTR_FIFO_RSIZE"  ,	   0x11f00000130d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT14_INSTR_FIFO_RSIZE"  ,	   0x11f00000130e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT15_INSTR_FIFO_RSIZE"  ,	   0x11f00000130f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT16_INSTR_FIFO_RSIZE"  ,	   0x11f0000013100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT17_INSTR_FIFO_RSIZE"  ,	   0x11f0000013110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT18_INSTR_FIFO_RSIZE"  ,	   0x11f0000013120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT19_INSTR_FIFO_RSIZE"  ,	   0x11f0000013130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT20_INSTR_FIFO_RSIZE"  ,	   0x11f0000013140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT21_INSTR_FIFO_RSIZE"  ,	   0x11f0000013150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT22_INSTR_FIFO_RSIZE"  ,	   0x11f0000013160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT23_INSTR_FIFO_RSIZE"  ,	   0x11f0000013170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT24_INSTR_FIFO_RSIZE"  ,	   0x11f0000013180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT25_INSTR_FIFO_RSIZE"  ,	   0x11f0000013190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT26_INSTR_FIFO_RSIZE"  ,	   0x11f00000131a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT27_INSTR_FIFO_RSIZE"  ,	   0x11f00000131b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT28_INSTR_FIFO_RSIZE"  ,	   0x11f00000131c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT29_INSTR_FIFO_RSIZE"  ,	   0x11f00000131d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT30_INSTR_FIFO_RSIZE"  ,	   0x11f00000131e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT31_INSTR_FIFO_RSIZE"  ,	   0x11f00000131f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT0_INSTR_HEADER"       ,	   0x11f0000013400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT1_INSTR_HEADER"       ,	   0x11f0000013410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT2_INSTR_HEADER"       ,	   0x11f0000013420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT3_INSTR_HEADER"       ,	   0x11f0000013430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT4_INSTR_HEADER"       ,	   0x11f0000013440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT5_INSTR_HEADER"       ,	   0x11f0000013450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT6_INSTR_HEADER"       ,	   0x11f0000013460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT7_INSTR_HEADER"       ,	   0x11f0000013470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT8_INSTR_HEADER"       ,	   0x11f0000013480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT9_INSTR_HEADER"       ,	   0x11f0000013490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT10_INSTR_HEADER"      ,	   0x11f00000134a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT11_INSTR_HEADER"      ,	   0x11f00000134b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT12_INSTR_HEADER"      ,	   0x11f00000134c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT13_INSTR_HEADER"      ,	   0x11f00000134d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT14_INSTR_HEADER"      ,	   0x11f00000134e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT15_INSTR_HEADER"      ,	   0x11f00000134f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT16_INSTR_HEADER"      ,	   0x11f0000013500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT17_INSTR_HEADER"      ,	   0x11f0000013510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT18_INSTR_HEADER"      ,	   0x11f0000013520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT19_INSTR_HEADER"      ,	   0x11f0000013530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT20_INSTR_HEADER"      ,	   0x11f0000013540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT21_INSTR_HEADER"      ,	   0x11f0000013550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT22_INSTR_HEADER"      ,	   0x11f0000013560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT23_INSTR_HEADER"      ,	   0x11f0000013570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT24_INSTR_HEADER"      ,	   0x11f0000013580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT25_INSTR_HEADER"      ,	   0x11f0000013590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT26_INSTR_HEADER"      ,	   0x11f00000135a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT27_INSTR_HEADER"      ,	   0x11f00000135b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT28_INSTR_HEADER"      ,	   0x11f00000135c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT29_INSTR_HEADER"      ,	   0x11f00000135d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT30_INSTR_HEADER"      ,	   0x11f00000135e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT31_INSTR_HEADER"      ,	   0x11f00000135f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT0_OUT_SIZE"           ,	   0x11f0000010c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT1_OUT_SIZE"           ,	   0x11f0000010c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT2_OUT_SIZE"           ,	   0x11f0000010c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT3_OUT_SIZE"           ,	   0x11f0000010c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT4_OUT_SIZE"           ,	   0x11f0000010c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT5_OUT_SIZE"           ,	   0x11f0000010c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT6_OUT_SIZE"           ,	   0x11f0000010c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT7_OUT_SIZE"           ,	   0x11f0000010c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT8_OUT_SIZE"           ,	   0x11f0000010c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT9_OUT_SIZE"           ,	   0x11f0000010c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT10_OUT_SIZE"          ,	   0x11f0000010ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT11_OUT_SIZE"          ,	   0x11f0000010cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT12_OUT_SIZE"          ,	   0x11f0000010cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT13_OUT_SIZE"          ,	   0x11f0000010cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT14_OUT_SIZE"          ,	   0x11f0000010ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT15_OUT_SIZE"          ,	   0x11f0000010cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT16_OUT_SIZE"          ,	   0x11f0000010d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT17_OUT_SIZE"          ,	   0x11f0000010d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT18_OUT_SIZE"          ,	   0x11f0000010d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT19_OUT_SIZE"          ,	   0x11f0000010d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT20_OUT_SIZE"          ,	   0x11f0000010d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT21_OUT_SIZE"          ,	   0x11f0000010d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT22_OUT_SIZE"          ,	   0x11f0000010d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT23_OUT_SIZE"          ,	   0x11f0000010d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT24_OUT_SIZE"          ,	   0x11f0000010d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT25_OUT_SIZE"          ,	   0x11f0000010d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT26_OUT_SIZE"          ,	   0x11f0000010da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT27_OUT_SIZE"          ,	   0x11f0000010db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT28_OUT_SIZE"          ,	   0x11f0000010dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT29_OUT_SIZE"          ,	   0x11f0000010dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT30_OUT_SIZE"          ,	   0x11f0000010de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT31_OUT_SIZE"          ,	   0x11f0000010df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT0_SLIST_BADDR"        ,	   0x11f0000011400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT1_SLIST_BADDR"        ,	   0x11f0000011410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT2_SLIST_BADDR"        ,	   0x11f0000011420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT3_SLIST_BADDR"        ,	   0x11f0000011430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT4_SLIST_BADDR"        ,	   0x11f0000011440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT5_SLIST_BADDR"        ,	   0x11f0000011450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT6_SLIST_BADDR"        ,	   0x11f0000011460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT7_SLIST_BADDR"        ,	   0x11f0000011470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT8_SLIST_BADDR"        ,	   0x11f0000011480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT9_SLIST_BADDR"        ,	   0x11f0000011490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT10_SLIST_BADDR"       ,	   0x11f00000114a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT11_SLIST_BADDR"       ,	   0x11f00000114b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT12_SLIST_BADDR"       ,	   0x11f00000114c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT13_SLIST_BADDR"       ,	   0x11f00000114d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT14_SLIST_BADDR"       ,	   0x11f00000114e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT15_SLIST_BADDR"       ,	   0x11f00000114f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT16_SLIST_BADDR"       ,	   0x11f0000011500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT17_SLIST_BADDR"       ,	   0x11f0000011510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT18_SLIST_BADDR"       ,	   0x11f0000011520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT19_SLIST_BADDR"       ,	   0x11f0000011530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT20_SLIST_BADDR"       ,	   0x11f0000011540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT21_SLIST_BADDR"       ,	   0x11f0000011550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT22_SLIST_BADDR"       ,	   0x11f0000011560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT23_SLIST_BADDR"       ,	   0x11f0000011570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT24_SLIST_BADDR"       ,	   0x11f0000011580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT25_SLIST_BADDR"       ,	   0x11f0000011590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT26_SLIST_BADDR"       ,	   0x11f00000115a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT27_SLIST_BADDR"       ,	   0x11f00000115b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT28_SLIST_BADDR"       ,	   0x11f00000115c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT29_SLIST_BADDR"       ,	   0x11f00000115d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT30_SLIST_BADDR"       ,	   0x11f00000115e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT31_SLIST_BADDR"       ,	   0x11f00000115f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT0_SLIST_BAOFF_DBELL"  ,	   0x11f0000011800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT1_SLIST_BAOFF_DBELL"  ,	   0x11f0000011810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT2_SLIST_BAOFF_DBELL"  ,	   0x11f0000011820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT3_SLIST_BAOFF_DBELL"  ,	   0x11f0000011830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT4_SLIST_BAOFF_DBELL"  ,	   0x11f0000011840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT5_SLIST_BAOFF_DBELL"  ,	   0x11f0000011850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT6_SLIST_BAOFF_DBELL"  ,	   0x11f0000011860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT7_SLIST_BAOFF_DBELL"  ,	   0x11f0000011870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT8_SLIST_BAOFF_DBELL"  ,	   0x11f0000011880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT9_SLIST_BAOFF_DBELL"  ,	   0x11f0000011890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT10_SLIST_BAOFF_DBELL" ,	   0x11f00000118a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT11_SLIST_BAOFF_DBELL" ,	   0x11f00000118b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT12_SLIST_BAOFF_DBELL" ,	   0x11f00000118c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT13_SLIST_BAOFF_DBELL" ,	   0x11f00000118d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT14_SLIST_BAOFF_DBELL" ,	   0x11f00000118e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT15_SLIST_BAOFF_DBELL" ,	   0x11f00000118f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT16_SLIST_BAOFF_DBELL" ,	   0x11f0000011900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT17_SLIST_BAOFF_DBELL" ,	   0x11f0000011910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT18_SLIST_BAOFF_DBELL" ,	   0x11f0000011920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT19_SLIST_BAOFF_DBELL" ,	   0x11f0000011930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT20_SLIST_BAOFF_DBELL" ,	   0x11f0000011940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT21_SLIST_BAOFF_DBELL" ,	   0x11f0000011950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT22_SLIST_BAOFF_DBELL" ,	   0x11f0000011960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT23_SLIST_BAOFF_DBELL" ,	   0x11f0000011970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT24_SLIST_BAOFF_DBELL" ,	   0x11f0000011980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT25_SLIST_BAOFF_DBELL" ,	   0x11f0000011990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT26_SLIST_BAOFF_DBELL" ,	   0x11f00000119a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT27_SLIST_BAOFF_DBELL" ,	   0x11f00000119b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT28_SLIST_BAOFF_DBELL" ,	   0x11f00000119c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT29_SLIST_BAOFF_DBELL" ,	   0x11f00000119d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT30_SLIST_BAOFF_DBELL" ,	   0x11f00000119e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT31_SLIST_BAOFF_DBELL" ,	   0x11f00000119f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT0_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT1_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT2_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT3_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT4_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT5_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT6_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT7_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT8_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT9_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT10_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT11_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT12_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT13_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT14_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT15_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT16_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT17_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT18_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT19_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT20_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT21_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT22_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT23_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT24_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT25_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT26_SLIST_FIFO_RSIZE"  ,	   0x11f0000011da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT27_SLIST_FIFO_RSIZE"  ,	   0x11f0000011db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT28_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT29_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT30_SLIST_FIFO_RSIZE"  ,	   0x11f0000011de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT31_SLIST_FIFO_RSIZE"  ,	   0x11f0000011df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT_CNT_INT"             ,	   0x11f0000011130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT_CNT_INT_ENB"         ,	   0x11f0000011150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT_CTL"                 ,	   0x11f0000011220ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_DATA_OUT_ES"         ,	   0x11f00000110b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT_DATA_OUT_NS"         ,	   0x11f00000110a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT_DATA_OUT_ROR"        ,	   0x11f0000011090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT_DPADDR"              ,	   0x11f0000011080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT_IN_BP"               ,	   0x11f0000011210ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT_IN_DONE0_CNTS"       ,	   0x11f0000012000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE1_CNTS"       ,	   0x11f0000012010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE2_CNTS"       ,	   0x11f0000012020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE3_CNTS"       ,	   0x11f0000012030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE4_CNTS"       ,	   0x11f0000012040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE5_CNTS"       ,	   0x11f0000012050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE6_CNTS"       ,	   0x11f0000012060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE7_CNTS"       ,	   0x11f0000012070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE8_CNTS"       ,	   0x11f0000012080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE9_CNTS"       ,	   0x11f0000012090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE10_CNTS"      ,	   0x11f00000120a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE11_CNTS"      ,	   0x11f00000120b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE12_CNTS"      ,	   0x11f00000120c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE13_CNTS"      ,	   0x11f00000120d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE14_CNTS"      ,	   0x11f00000120e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE15_CNTS"      ,	   0x11f00000120f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE16_CNTS"      ,	   0x11f0000012100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE17_CNTS"      ,	   0x11f0000012110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE18_CNTS"      ,	   0x11f0000012120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE19_CNTS"      ,	   0x11f0000012130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE20_CNTS"      ,	   0x11f0000012140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE21_CNTS"      ,	   0x11f0000012150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE22_CNTS"      ,	   0x11f0000012160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE23_CNTS"      ,	   0x11f0000012170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE24_CNTS"      ,	   0x11f0000012180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE25_CNTS"      ,	   0x11f0000012190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE26_CNTS"      ,	   0x11f00000121a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE27_CNTS"      ,	   0x11f00000121b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE28_CNTS"      ,	   0x11f00000121c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE29_CNTS"      ,	   0x11f00000121d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE30_CNTS"      ,	   0x11f00000121e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_DONE31_CNTS"      ,	   0x11f00000121f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_IN_INSTR_COUNTS"     ,	   0x11f0000011200ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT_IN_PCIE_PORT"        ,	   0x11f00000111b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	952},
+	{"SLI_PKT_INPUT_CONTROL"       ,	   0x11f0000011170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	953},
+	{"SLI_PKT_INSTR_ENB"           ,	   0x11f0000011000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_INSTR_RD_SIZE"       ,	   0x11f00000111a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	955},
+	{"SLI_PKT_INSTR_SIZE"          ,	   0x11f0000011020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	956},
+	{"SLI_PKT_INT_LEVELS"          ,	   0x11f0000011120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	957},
+	{"SLI_PKT_IPTR"                ,	   0x11f0000011070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	958},
+	{"SLI_PKT_OUT_BMODE"           ,	   0x11f00000110d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	959},
+	{"SLI_PKT_OUT_ENB"             ,	   0x11f0000011010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_OUTPUT_WMARK"        ,	   0x11f0000011180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	961},
+	{"SLI_PKT_PCIE_PORT"           ,	   0x11f00000110e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	962},
+	{"SLI_PKT_PORT_IN_RST"         ,	   0x11f00000111f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	963},
+	{"SLI_PKT_SLIST_ES"            ,	   0x11f0000011050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	964},
+	{"SLI_PKT_SLIST_NS"            ,	   0x11f0000011040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	965},
+	{"SLI_PKT_SLIST_ROR"           ,	   0x11f0000011030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	966},
+	{"SLI_PKT_TIME_INT"            ,	   0x11f0000011140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	967},
+	{"SLI_PKT_TIME_INT_ENB"        ,	   0x11f0000011160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	968},
+	{"SLI_S2M_PORT0_CTL"           ,	   0x11f0000013d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_S2M_PORT1_CTL"           ,	   0x11f0000013d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_SCRATCH_1"               ,	   0x11f00000103c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	970},
+	{"SLI_SCRATCH_2"               ,	   0x11f00000103d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	971},
+	{"SLI_STATE1"                  ,	   0x11f0000010620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	972},
+	{"SLI_STATE2"                  ,	   0x11f0000010630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	973},
+	{"SLI_STATE3"                  ,	   0x11f0000010640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	974},
+	{"SLI_WIN_RD_ADDR"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	975},
+	{"SLI_WIN_RD_DATA"             ,	              0x40ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	976},
+	{"SLI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	977},
+	{"SLI_WIN_WR_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	978},
+	{"SLI_WIN_WR_MASK"             ,	              0x30ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	979},
+	{"SLI_WINDOW_CTL"              ,	   0x11f00000102e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	980},
+	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	981},
+	{"SMI1_CLK"                    ,	   0x1180000001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	981},
+	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	982},
+	{"SMI1_CMD"                    ,	   0x1180000001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	982},
+	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	983},
+	{"SMI1_EN"                     ,	   0x1180000001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	983},
+	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	984},
+	{"SMI1_RD_DAT"                 ,	   0x1180000001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	984},
+	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	985},
+	{"SMI1_WR_DAT"                 ,	   0x1180000001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	985},
+	{"SMI_DRV_CTL"                 ,	   0x1180000001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"SRIO0_ACC_CTRL"              ,	   0x11800c8000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	987},
+	{"SRIO1_ACC_CTRL"              ,	   0x11800c9000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	987},
+	{"SRIO0_ASMBLY_ID"             ,	   0x11800c8000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_ASMBLY_ID"             ,	   0x11800c9000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_ASMBLY_INFO"           ,	   0x11800c8000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_ASMBLY_INFO"           ,	   0x11800c9000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_BELL_RESP_CTRL"        ,	   0x11800c8000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	990},
+	{"SRIO1_BELL_RESP_CTRL"        ,	   0x11800c9000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	990},
+	{"SRIO0_BIST_STATUS"           ,	   0x11800c8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	991},
+	{"SRIO1_BIST_STATUS"           ,	   0x11800c9000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	991},
+	{"SRIO0_IMSG_CTRL"             ,	   0x11800c8000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	992},
+	{"SRIO1_IMSG_CTRL"             ,	   0x11800c9000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	992},
+	{"SRIO0_IMSG_INST_HDR000"      ,	   0x11800c8000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	993},
+	{"SRIO0_IMSG_INST_HDR001"      ,	   0x11800c8000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	993},
+	{"SRIO1_IMSG_INST_HDR000"      ,	   0x11800c9000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	993},
+	{"SRIO1_IMSG_INST_HDR001"      ,	   0x11800c9000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	993},
+	{"SRIO0_IMSG_QOS_GRP000"       ,	   0x11800c8000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP001"       ,	   0x11800c8000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP002"       ,	   0x11800c8000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP003"       ,	   0x11800c8000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP004"       ,	   0x11800c8000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP005"       ,	   0x11800c8000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP006"       ,	   0x11800c8000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP007"       ,	   0x11800c8000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP008"       ,	   0x11800c8000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP009"       ,	   0x11800c8000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP010"       ,	   0x11800c8000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP011"       ,	   0x11800c8000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP012"       ,	   0x11800c8000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP013"       ,	   0x11800c8000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP014"       ,	   0x11800c8000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP015"       ,	   0x11800c8000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP016"       ,	   0x11800c8000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP017"       ,	   0x11800c8000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP018"       ,	   0x11800c8000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP019"       ,	   0x11800c8000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP020"       ,	   0x11800c80006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP021"       ,	   0x11800c80006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP022"       ,	   0x11800c80006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP023"       ,	   0x11800c80006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP024"       ,	   0x11800c80006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP025"       ,	   0x11800c80006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP026"       ,	   0x11800c80006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP027"       ,	   0x11800c80006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP028"       ,	   0x11800c80006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP029"       ,	   0x11800c80006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP030"       ,	   0x11800c80006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_QOS_GRP031"       ,	   0x11800c80006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP000"       ,	   0x11800c9000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP001"       ,	   0x11800c9000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP002"       ,	   0x11800c9000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP003"       ,	   0x11800c9000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP004"       ,	   0x11800c9000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP005"       ,	   0x11800c9000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP006"       ,	   0x11800c9000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP007"       ,	   0x11800c9000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP008"       ,	   0x11800c9000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP009"       ,	   0x11800c9000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP010"       ,	   0x11800c9000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP011"       ,	   0x11800c9000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP012"       ,	   0x11800c9000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP013"       ,	   0x11800c9000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP014"       ,	   0x11800c9000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP015"       ,	   0x11800c9000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP016"       ,	   0x11800c9000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP017"       ,	   0x11800c9000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP018"       ,	   0x11800c9000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP019"       ,	   0x11800c9000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP020"       ,	   0x11800c90006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP021"       ,	   0x11800c90006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP022"       ,	   0x11800c90006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP023"       ,	   0x11800c90006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP024"       ,	   0x11800c90006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP025"       ,	   0x11800c90006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP026"       ,	   0x11800c90006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP027"       ,	   0x11800c90006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP028"       ,	   0x11800c90006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP029"       ,	   0x11800c90006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP030"       ,	   0x11800c90006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_IMSG_QOS_GRP031"       ,	   0x11800c90006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_IMSG_STATUS000"        ,	   0x11800c8000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS001"        ,	   0x11800c8000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS002"        ,	   0x11800c8000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS003"        ,	   0x11800c8000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS004"        ,	   0x11800c8000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS005"        ,	   0x11800c8000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS006"        ,	   0x11800c8000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS007"        ,	   0x11800c8000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS008"        ,	   0x11800c8000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS009"        ,	   0x11800c8000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS010"        ,	   0x11800c8000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS011"        ,	   0x11800c8000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS012"        ,	   0x11800c8000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS013"        ,	   0x11800c8000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS014"        ,	   0x11800c8000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS015"        ,	   0x11800c8000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS016"        ,	   0x11800c8000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS017"        ,	   0x11800c8000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS018"        ,	   0x11800c8000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS019"        ,	   0x11800c8000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS020"        ,	   0x11800c80007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS021"        ,	   0x11800c80007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS022"        ,	   0x11800c80007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_STATUS023"        ,	   0x11800c80007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS000"        ,	   0x11800c9000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS001"        ,	   0x11800c9000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS002"        ,	   0x11800c9000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS003"        ,	   0x11800c9000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS004"        ,	   0x11800c9000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS005"        ,	   0x11800c9000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS006"        ,	   0x11800c9000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS007"        ,	   0x11800c9000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS008"        ,	   0x11800c9000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS009"        ,	   0x11800c9000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS010"        ,	   0x11800c9000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS011"        ,	   0x11800c9000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS012"        ,	   0x11800c9000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS013"        ,	   0x11800c9000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS014"        ,	   0x11800c9000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS015"        ,	   0x11800c9000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS016"        ,	   0x11800c9000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS017"        ,	   0x11800c9000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS018"        ,	   0x11800c9000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS019"        ,	   0x11800c9000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS020"        ,	   0x11800c90007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS021"        ,	   0x11800c90007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS022"        ,	   0x11800c90007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_IMSG_STATUS023"        ,	   0x11800c90007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_VPORT_THR"        ,	   0x11800c8000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	996},
+	{"SRIO1_IMSG_VPORT_THR"        ,	   0x11800c9000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	996},
+	{"SRIO0_INT_ENABLE"            ,	   0x11800c8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
+	{"SRIO1_INT_ENABLE"            ,	   0x11800c9000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
+	{"SRIO0_INT_INFO0"             ,	   0x11800c8000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_INT_INFO0"             ,	   0x11800c9000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_INT_INFO1"             ,	   0x11800c8000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_INT_INFO1"             ,	   0x11800c9000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_INT_INFO2"             ,	   0x11800c8000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1000},
+	{"SRIO1_INT_INFO2"             ,	   0x11800c9000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1000},
+	{"SRIO0_INT_INFO3"             ,	   0x11800c8000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1001},
+	{"SRIO1_INT_INFO3"             ,	   0x11800c9000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1001},
+	{"SRIO0_INT_REG"               ,	   0x11800c8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
+	{"SRIO1_INT_REG"               ,	   0x11800c9000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
+	{"SRIO0_IP_FEATURE"            ,	   0x11800c80003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
+	{"SRIO1_IP_FEATURE"            ,	   0x11800c90003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
+	{"SRIO0_MAINT_OP"              ,	   0x11800c8000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_MAINT_OP"              ,	   0x11800c9000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_MAINT_RD_DATA"         ,	   0x11800c8000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_MAINT_RD_DATA"         ,	   0x11800c9000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_MCE_TX_CTL"            ,	   0x11800c8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"SRIO1_MCE_TX_CTL"            ,	   0x11800c9000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"SRIO0_MEM_OP_CTRL"           ,	   0x11800c8000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"SRIO1_MEM_OP_CTRL"           ,	   0x11800c9000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"SRIO0_OMSG_CTRL000"          ,	   0x11800c8000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"SRIO0_OMSG_CTRL001"          ,	   0x11800c80004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"SRIO1_OMSG_CTRL000"          ,	   0x11800c9000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"SRIO1_OMSG_CTRL001"          ,	   0x11800c90004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"SRIO0_OMSG_FMP_MR000"        ,	   0x11800c8000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1009},
+	{"SRIO0_OMSG_FMP_MR001"        ,	   0x11800c80004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1009},
+	{"SRIO1_OMSG_FMP_MR000"        ,	   0x11800c9000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1009},
+	{"SRIO1_OMSG_FMP_MR001"        ,	   0x11800c90004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1009},
+	{"SRIO0_OMSG_NMP_MR000"        ,	   0x11800c80004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_OMSG_NMP_MR001"        ,	   0x11800c80004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_OMSG_NMP_MR000"        ,	   0x11800c90004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_OMSG_NMP_MR001"        ,	   0x11800c90004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_OMSG_PORT000"          ,	   0x11800c8000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"SRIO0_OMSG_PORT001"          ,	   0x11800c80004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"SRIO1_OMSG_PORT000"          ,	   0x11800c9000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"SRIO1_OMSG_PORT001"          ,	   0x11800c90004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"SRIO0_OMSG_SP_MR000"         ,	   0x11800c8000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"SRIO0_OMSG_SP_MR001"         ,	   0x11800c80004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"SRIO1_OMSG_SP_MR000"         ,	   0x11800c9000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"SRIO1_OMSG_SP_MR001"         ,	   0x11800c90004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"SRIO0_RX_BELL"               ,	   0x11800c8000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"SRIO1_RX_BELL"               ,	   0x11800c9000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"SRIO0_RX_BELL_SEQ"           ,	   0x11800c8000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"SRIO1_RX_BELL_SEQ"           ,	   0x11800c9000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"SRIO0_RX_STATUS"             ,	   0x11800c8000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"SRIO1_RX_STATUS"             ,	   0x11800c9000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"SRIO0_S2M_TYPE000"           ,	   0x11800c8000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_S2M_TYPE001"           ,	   0x11800c8000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_S2M_TYPE002"           ,	   0x11800c8000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_S2M_TYPE003"           ,	   0x11800c8000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_S2M_TYPE004"           ,	   0x11800c80001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_S2M_TYPE005"           ,	   0x11800c80001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_S2M_TYPE006"           ,	   0x11800c80001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_S2M_TYPE007"           ,	   0x11800c80001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_S2M_TYPE008"           ,	   0x11800c80001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_S2M_TYPE009"           ,	   0x11800c80001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_S2M_TYPE010"           ,	   0x11800c80001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_S2M_TYPE011"           ,	   0x11800c80001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_S2M_TYPE012"           ,	   0x11800c80001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_S2M_TYPE013"           ,	   0x11800c80001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_S2M_TYPE014"           ,	   0x11800c80001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_S2M_TYPE015"           ,	   0x11800c80001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_S2M_TYPE000"           ,	   0x11800c9000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_S2M_TYPE001"           ,	   0x11800c9000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_S2M_TYPE002"           ,	   0x11800c9000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_S2M_TYPE003"           ,	   0x11800c9000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_S2M_TYPE004"           ,	   0x11800c90001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_S2M_TYPE005"           ,	   0x11800c90001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_S2M_TYPE006"           ,	   0x11800c90001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_S2M_TYPE007"           ,	   0x11800c90001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_S2M_TYPE008"           ,	   0x11800c90001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_S2M_TYPE009"           ,	   0x11800c90001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_S2M_TYPE010"           ,	   0x11800c90001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_S2M_TYPE011"           ,	   0x11800c90001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_S2M_TYPE012"           ,	   0x11800c90001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_S2M_TYPE013"           ,	   0x11800c90001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_S2M_TYPE014"           ,	   0x11800c90001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_S2M_TYPE015"           ,	   0x11800c90001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_SEQ"                   ,	   0x11800c8000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"SRIO1_SEQ"                   ,	   0x11800c9000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"SRIO0_STATUS_REG"            ,	   0x11800c8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"SRIO1_STATUS_REG"            ,	   0x11800c9000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"SRIO0_TAG_CTRL"              ,	   0x11800c8000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"SRIO1_TAG_CTRL"              ,	   0x11800c9000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"SRIO0_TLP_CREDITS"           ,	   0x11800c8000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"SRIO1_TLP_CREDITS"           ,	   0x11800c9000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"SRIO0_TX_BELL"               ,	   0x11800c8000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"SRIO1_TX_BELL"               ,	   0x11800c9000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"SRIO0_TX_BELL_INFO"          ,	   0x11800c8000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"SRIO1_TX_BELL_INFO"          ,	   0x11800c9000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"SRIO0_TX_CTRL"               ,	   0x11800c8000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1023},
+	{"SRIO1_TX_CTRL"               ,	   0x11800c9000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1023},
+	{"SRIO0_TX_STATUS"             ,	   0x11800c8000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"SRIO1_TX_STATUS"             ,	   0x11800c9000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"SRIOMAINT0_ASMBLY_ID"        ,	               0x8ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1025},
+	{"SRIOMAINT1_ASMBLY_ID"        ,	               0x8ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1025},
+	{"SRIOMAINT0_ASMBLY_INFO"      ,	               0xcull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1026},
+	{"SRIOMAINT1_ASMBLY_INFO"      ,	               0xcull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1026},
+	{"SRIOMAINT0_BAR1_IDX000"      ,	          0x200010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT0_BAR1_IDX001"      ,	          0x200014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT0_BAR1_IDX002"      ,	          0x200018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT0_BAR1_IDX003"      ,	          0x20001cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT0_BAR1_IDX004"      ,	          0x200020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT0_BAR1_IDX005"      ,	          0x200024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT0_BAR1_IDX006"      ,	          0x200028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT0_BAR1_IDX007"      ,	          0x20002cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT0_BAR1_IDX008"      ,	          0x200030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT0_BAR1_IDX009"      ,	          0x200034ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT0_BAR1_IDX010"      ,	          0x200038ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT0_BAR1_IDX011"      ,	          0x20003cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT0_BAR1_IDX012"      ,	          0x200040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT0_BAR1_IDX013"      ,	          0x200044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT0_BAR1_IDX014"      ,	          0x200048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT0_BAR1_IDX015"      ,	          0x20004cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT1_BAR1_IDX000"      ,	          0x200010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT1_BAR1_IDX001"      ,	          0x200014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT1_BAR1_IDX002"      ,	          0x200018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT1_BAR1_IDX003"      ,	          0x20001cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT1_BAR1_IDX004"      ,	          0x200020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT1_BAR1_IDX005"      ,	          0x200024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT1_BAR1_IDX006"      ,	          0x200028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT1_BAR1_IDX007"      ,	          0x20002cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT1_BAR1_IDX008"      ,	          0x200030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT1_BAR1_IDX009"      ,	          0x200034ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT1_BAR1_IDX010"      ,	          0x200038ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT1_BAR1_IDX011"      ,	          0x20003cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT1_BAR1_IDX012"      ,	          0x200040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT1_BAR1_IDX013"      ,	          0x200044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT1_BAR1_IDX014"      ,	          0x200048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT1_BAR1_IDX015"      ,	          0x20004cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT0_BELL_STATUS"      ,	          0x200080ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1028},
+	{"SRIOMAINT1_BELL_STATUS"      ,	          0x200080ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1028},
+	{"SRIOMAINT0_COMP_TAG"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1029},
+	{"SRIOMAINT1_COMP_TAG"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1029},
+	{"SRIOMAINT0_CORE_ENABLES"     ,	          0x200070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1030},
+	{"SRIOMAINT1_CORE_ENABLES"     ,	          0x200070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1030},
+	{"SRIOMAINT0_DEV_ID"           ,	               0x0ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1031},
+	{"SRIOMAINT1_DEV_ID"           ,	               0x0ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1031},
+	{"SRIOMAINT0_DEV_REV"          ,	               0x4ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1032},
+	{"SRIOMAINT1_DEV_REV"          ,	               0x4ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1032},
+	{"SRIOMAINT0_DST_OPS"          ,	              0x1cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1033},
+	{"SRIOMAINT1_DST_OPS"          ,	              0x1cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1033},
+	{"SRIOMAINT0_ERB_ATTR_CAPT"    ,	            0x2048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1034},
+	{"SRIOMAINT1_ERB_ATTR_CAPT"    ,	            0x2048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1034},
+	{"SRIOMAINT0_ERB_ERR_DET"      ,	            0x2040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1035},
+	{"SRIOMAINT1_ERB_ERR_DET"      ,	            0x2040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1035},
+	{"SRIOMAINT0_ERB_ERR_RATE"     ,	            0x2068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1036},
+	{"SRIOMAINT1_ERB_ERR_RATE"     ,	            0x2068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1036},
+	{"SRIOMAINT0_ERB_ERR_RATE_EN"  ,	            0x2044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1037},
+	{"SRIOMAINT1_ERB_ERR_RATE_EN"  ,	            0x2044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1037},
+	{"SRIOMAINT0_ERB_ERR_RATE_THR" ,	            0x206cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1038},
+	{"SRIOMAINT1_ERB_ERR_RATE_THR" ,	            0x206cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1038},
+	{"SRIOMAINT0_ERB_HDR"          ,	            0x2000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT1_ERB_HDR"          ,	            0x2000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT0_ERB_LT_ADDR_CAPT_H",	            0x2010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1040},
+	{"SRIOMAINT1_ERB_LT_ADDR_CAPT_H",	            0x2010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1040},
+	{"SRIOMAINT0_ERB_LT_ADDR_CAPT_L",	            0x2014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1041},
+	{"SRIOMAINT1_ERB_LT_ADDR_CAPT_L",	            0x2014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1041},
+	{"SRIOMAINT0_ERB_LT_CTRL_CAPT" ,	            0x201cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1042},
+	{"SRIOMAINT1_ERB_LT_CTRL_CAPT" ,	            0x201cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1042},
+	{"SRIOMAINT0_ERB_LT_DEV_ID"    ,	            0x2028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1043},
+	{"SRIOMAINT1_ERB_LT_DEV_ID"    ,	            0x2028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1043},
+	{"SRIOMAINT0_ERB_LT_DEV_ID_CAPT",	            0x2018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1044},
+	{"SRIOMAINT1_ERB_LT_DEV_ID_CAPT",	            0x2018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1044},
+	{"SRIOMAINT0_ERB_LT_ERR_DET"   ,	            0x2008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_ERB_LT_ERR_DET"   ,	            0x2008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_ERB_LT_ERR_EN"    ,	            0x200cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1046},
+	{"SRIOMAINT1_ERB_LT_ERR_EN"    ,	            0x200cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1046},
+	{"SRIOMAINT0_ERB_PACK_CAPT_1"  ,	            0x2050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1047},
+	{"SRIOMAINT1_ERB_PACK_CAPT_1"  ,	            0x2050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1047},
+	{"SRIOMAINT0_ERB_PACK_CAPT_2"  ,	            0x2054ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1048},
+	{"SRIOMAINT1_ERB_PACK_CAPT_2"  ,	            0x2054ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1048},
+	{"SRIOMAINT0_ERB_PACK_CAPT_3"  ,	            0x2058ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1049},
+	{"SRIOMAINT1_ERB_PACK_CAPT_3"  ,	            0x2058ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1049},
+	{"SRIOMAINT0_ERB_PACK_SYM_CAPT",	            0x204cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1050},
+	{"SRIOMAINT1_ERB_PACK_SYM_CAPT",	            0x204cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1050},
+	{"SRIOMAINT0_HB_DEV_ID_LOCK"   ,	              0x68ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1051},
+	{"SRIOMAINT1_HB_DEV_ID_LOCK"   ,	              0x68ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1051},
+	{"SRIOMAINT0_IR_BUFFER_CONFIG" ,	          0x102000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1052},
+	{"SRIOMAINT1_IR_BUFFER_CONFIG" ,	          0x102000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1052},
+	{"SRIOMAINT0_IR_PD_PHY_CTRL"   ,	          0x107028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1053},
+	{"SRIOMAINT1_IR_PD_PHY_CTRL"   ,	          0x107028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1053},
+	{"SRIOMAINT0_IR_PD_PHY_STAT"   ,	          0x10702cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1054},
+	{"SRIOMAINT1_IR_PD_PHY_STAT"   ,	          0x10702cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1054},
+	{"SRIOMAINT0_IR_PI_PHY_CTRL"   ,	          0x107020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1055},
+	{"SRIOMAINT1_IR_PI_PHY_CTRL"   ,	          0x107020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1055},
+	{"SRIOMAINT0_IR_PI_PHY_STAT"   ,	          0x107024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1056},
+	{"SRIOMAINT1_IR_PI_PHY_STAT"   ,	          0x107024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1056},
+	{"SRIOMAINT0_IR_SP_RX_CTRL"    ,	          0x10700cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
+	{"SRIOMAINT1_IR_SP_RX_CTRL"    ,	          0x10700cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
+	{"SRIOMAINT0_IR_SP_RX_DATA"    ,	          0x107014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1058},
+	{"SRIOMAINT1_IR_SP_RX_DATA"    ,	          0x107014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1058},
+	{"SRIOMAINT0_IR_SP_RX_STAT"    ,	          0x107010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1059},
+	{"SRIOMAINT1_IR_SP_RX_STAT"    ,	          0x107010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1059},
+	{"SRIOMAINT0_IR_SP_TX_CTRL"    ,	          0x107000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1060},
+	{"SRIOMAINT1_IR_SP_TX_CTRL"    ,	          0x107000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1060},
+	{"SRIOMAINT0_IR_SP_TX_DATA"    ,	          0x107008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1061},
+	{"SRIOMAINT1_IR_SP_TX_DATA"    ,	          0x107008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1061},
+	{"SRIOMAINT0_IR_SP_TX_STAT"    ,	          0x107004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1062},
+	{"SRIOMAINT1_IR_SP_TX_STAT"    ,	          0x107004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1062},
+	{"SRIOMAINT0_LANE_000_STATUS_0",	            0x1010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1063},
+	{"SRIOMAINT0_LANE_001_STATUS_0",	            0x1030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1063},
+	{"SRIOMAINT0_LANE_002_STATUS_0",	            0x1050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1063},
+	{"SRIOMAINT0_LANE_003_STATUS_0",	            0x1070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1063},
+	{"SRIOMAINT1_LANE_000_STATUS_0",	            0x1010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1063},
+	{"SRIOMAINT1_LANE_001_STATUS_0",	            0x1030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1063},
+	{"SRIOMAINT1_LANE_002_STATUS_0",	            0x1050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1063},
+	{"SRIOMAINT1_LANE_003_STATUS_0",	            0x1070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1063},
+	{"SRIOMAINT0_LCS_BA0"          ,	              0x58ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1064},
+	{"SRIOMAINT1_LCS_BA0"          ,	              0x58ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1064},
+	{"SRIOMAINT0_LCS_BA1"          ,	              0x5cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1065},
+	{"SRIOMAINT1_LCS_BA1"          ,	              0x5cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1065},
+	{"SRIOMAINT0_M2S_BAR0_START0"  ,	          0x200000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1066},
+	{"SRIOMAINT1_M2S_BAR0_START0"  ,	          0x200000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1066},
+	{"SRIOMAINT0_M2S_BAR0_START1"  ,	          0x200004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1067},
+	{"SRIOMAINT1_M2S_BAR0_START1"  ,	          0x200004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1067},
+	{"SRIOMAINT0_M2S_BAR1_START0"  ,	          0x200008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1068},
+	{"SRIOMAINT1_M2S_BAR1_START0"  ,	          0x200008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1068},
+	{"SRIOMAINT0_M2S_BAR1_START1"  ,	          0x20000cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1069},
+	{"SRIOMAINT1_M2S_BAR1_START1"  ,	          0x20000cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1069},
+	{"SRIOMAINT0_M2S_BAR2_START"   ,	          0x200050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1070},
+	{"SRIOMAINT1_M2S_BAR2_START"   ,	          0x200050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1070},
+	{"SRIOMAINT0_PE_FEAT"          ,	              0x10ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1071},
+	{"SRIOMAINT1_PE_FEAT"          ,	              0x10ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1071},
+	{"SRIOMAINT0_PE_LLC"           ,	              0x4cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1072},
+	{"SRIOMAINT1_PE_LLC"           ,	              0x4cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1072},
+	{"SRIOMAINT0_PORT_0_CTL"       ,	             0x15cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1073},
+	{"SRIOMAINT1_PORT_0_CTL"       ,	             0x15cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1073},
+	{"SRIOMAINT0_PORT_0_CTL2"      ,	             0x154ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1074},
+	{"SRIOMAINT1_PORT_0_CTL2"      ,	             0x154ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1074},
+	{"SRIOMAINT0_PORT_0_ERR_STAT"  ,	             0x158ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1075},
+	{"SRIOMAINT1_PORT_0_ERR_STAT"  ,	             0x158ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1075},
+	{"SRIOMAINT0_PORT_GEN_CTL"     ,	             0x13cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
+	{"SRIOMAINT1_PORT_GEN_CTL"     ,	             0x13cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
+	{"SRIOMAINT0_PORT_LT_CTL"      ,	             0x120ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1077},
+	{"SRIOMAINT1_PORT_LT_CTL"      ,	             0x120ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1077},
+	{"SRIOMAINT0_PORT_MBH0"        ,	             0x100ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1078},
+	{"SRIOMAINT1_PORT_MBH0"        ,	             0x100ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1078},
+	{"SRIOMAINT0_PORT_RT_CTL"      ,	             0x124ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1079},
+	{"SRIOMAINT1_PORT_RT_CTL"      ,	             0x124ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1079},
+	{"SRIOMAINT0_PRI_DEV_ID"       ,	              0x60ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1080},
+	{"SRIOMAINT1_PRI_DEV_ID"       ,	              0x60ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1080},
+	{"SRIOMAINT0_SEC_DEV_CTRL"     ,	          0x200064ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1081},
+	{"SRIOMAINT1_SEC_DEV_CTRL"     ,	          0x200064ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1081},
+	{"SRIOMAINT0_SEC_DEV_ID"       ,	          0x200060ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1082},
+	{"SRIOMAINT1_SEC_DEV_ID"       ,	          0x200060ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1082},
+	{"SRIOMAINT0_SERIAL_LANE_HDR"  ,	            0x1000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1083},
+	{"SRIOMAINT1_SERIAL_LANE_HDR"  ,	            0x1000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1083},
+	{"SRIOMAINT0_SRC_OPS"          ,	              0x18ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1084},
+	{"SRIOMAINT1_SRC_OPS"          ,	              0x18ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1084},
+	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1085},
+	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1086},
+	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1087},
+	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1088},
+	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1089},
+	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1090},
+	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1092},
+	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1093},
+	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1094},
+	{"TRA0_BIST_STATUS"            ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1095},
+	{"TRA0_CTL"                    ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1096},
+	{"TRA0_CYCLES_SINCE"           ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1097},
+	{"TRA0_CYCLES_SINCE1"          ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1098},
+	{"TRA0_FILT_ADR_ADR"           ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1099},
+	{"TRA0_FILT_ADR_MSK"           ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1100},
+	{"TRA0_FILT_CMD"               ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1101},
+	{"TRA0_FILT_DID"               ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1102},
+	{"TRA0_FILT_SID"               ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1103},
+	{"TRA0_INT_STATUS"             ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1104},
+	{"TRA0_READ_DAT"               ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1105},
+	{"TRA0_TRIG0_ADR_ADR"          ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1106},
+	{"TRA0_TRIG0_ADR_MSK"          ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1107},
+	{"TRA0_TRIG0_CMD"              ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1108},
+	{"TRA0_TRIG0_DID"              ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1109},
+	{"TRA0_TRIG0_SID"              ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1110},
+	{"TRA0_TRIG1_ADR_ADR"          ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1111},
+	{"TRA0_TRIG1_ADR_MSK"          ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1112},
+	{"TRA0_TRIG1_CMD"              ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1113},
+	{"TRA0_TRIG1_DID"              ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1114},
+	{"TRA0_TRIG1_SID"              ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1115},
+	{"UAHC0_EHCI_ASYNCLISTADDR"    ,	   0x16f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1116},
+	{"UAHC0_EHCI_CONFIGFLAG"       ,	   0x16f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1117},
+	{"UAHC0_EHCI_CTRLDSSEGMENT"    ,	   0x16f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1118},
+	{"UAHC0_EHCI_FRINDEX"          ,	   0x16f000000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1119},
+	{"UAHC0_EHCI_HCCAPBASE"        ,	   0x16f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1120},
+	{"UAHC0_EHCI_HCCPARAMS"        ,	   0x16f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1121},
+	{"UAHC0_EHCI_HCSPARAMS"        ,	   0x16f0000000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1122},
+	{"UAHC0_EHCI_INSNREG00"        ,	   0x16f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1123},
+	{"UAHC0_EHCI_INSNREG03"        ,	   0x16f000000009cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1124},
+	{"UAHC0_EHCI_INSNREG04"        ,	   0x16f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1125},
+	{"UAHC0_EHCI_INSNREG06"        ,	   0x16f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1126},
+	{"UAHC0_EHCI_INSNREG07"        ,	   0x16f00000000ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	1127},
+	{"UAHC0_EHCI_PERIODICLISTBASE" ,	   0x16f0000000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1128},
+	{"UAHC0_EHCI_PORTSC001"        ,	   0x16f0000000054ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1129},
+	{"UAHC0_EHCI_PORTSC002"        ,	   0x16f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1129},
+	{"UAHC0_EHCI_USBCMD"           ,	   0x16f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1130},
+	{"UAHC0_EHCI_USBINTR"          ,	   0x16f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1131},
+	{"UAHC0_EHCI_USBSTS"           ,	   0x16f0000000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1132},
+	{"UAHC0_OHCI0_HCBULKCURRENTED" ,	   0x16f000000042cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1133},
+	{"UAHC0_OHCI0_HCBULKHEADED"    ,	   0x16f0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1134},
+	{"UAHC0_OHCI0_HCCOMMANDSTATUS" ,	   0x16f0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1135},
+	{"UAHC0_OHCI0_HCCONTROL"       ,	   0x16f0000000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1136},
+	{"UAHC0_OHCI0_HCCONTROLCURRENTED",	   0x16f0000000424ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1137},
+	{"UAHC0_OHCI0_HCCONTROLHEADED" ,	   0x16f0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1138},
+	{"UAHC0_OHCI0_HCDONEHEAD"      ,	   0x16f0000000430ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1139},
+	{"UAHC0_OHCI0_HCFMINTERVAL"    ,	   0x16f0000000434ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1140},
+	{"UAHC0_OHCI0_HCFMNUMBER"      ,	   0x16f000000043cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1141},
+	{"UAHC0_OHCI0_HCFMREMAINING"   ,	   0x16f0000000438ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1142},
+	{"UAHC0_OHCI0_HCHCCA"          ,	   0x16f0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1143},
+	{"UAHC0_OHCI0_HCINTERRUPTDISABLE",	   0x16f0000000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1144},
+	{"UAHC0_OHCI0_HCINTERRUPTENABLE",	   0x16f0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1145},
+	{"UAHC0_OHCI0_HCINTERRUPTSTATUS",	   0x16f000000040cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1146},
+	{"UAHC0_OHCI0_HCLSTHRESHOLD"   ,	   0x16f0000000444ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1147},
+	{"UAHC0_OHCI0_HCPERIODCURRENTED",	   0x16f000000041cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1148},
+	{"UAHC0_OHCI0_HCPERIODICSTART" ,	   0x16f0000000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1149},
+	{"UAHC0_OHCI0_HCREVISION"      ,	   0x16f0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1150},
+	{"UAHC0_OHCI0_HCRHDESCRIPTORA" ,	   0x16f0000000448ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1151},
+	{"UAHC0_OHCI0_HCRHDESCRIPTORB" ,	   0x16f000000044cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1152},
+	{"UAHC0_OHCI0_HCRHPORTSTATUS001",	   0x16f0000000454ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1153},
+	{"UAHC0_OHCI0_HCRHPORTSTATUS002",	   0x16f0000000458ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1153},
+	{"UAHC0_OHCI0_HCRHSTATUS"      ,	   0x16f0000000450ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1154},
+	{"UAHC0_OHCI0_INSNREG06"       ,	   0x16f0000000498ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1155},
+	{"UAHC0_OHCI0_INSNREG07"       ,	   0x16f000000049cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1156},
+	{"UCTL0_BIST_STATUS"           ,	   0x118006f0000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1157},
+	{"UCTL0_CLK_RST_CTL"           ,	   0x118006f000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1158},
+	{"UCTL0_EHCI_CTL"              ,	   0x118006f000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1159},
+	{"UCTL0_EHCI_FLA"              ,	   0x118006f0000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1160},
+	{"UCTL0_ERTO_CTL"              ,	   0x118006f000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1161},
+	{"UCTL0_IF_ENA"                ,	   0x118006f000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1162},
+	{"UCTL0_INT_ENA"               ,	   0x118006f000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1163},
+	{"UCTL0_INT_REG"               ,	   0x118006f000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1164},
+	{"UCTL0_OHCI_CTL"              ,	   0x118006f000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1165},
+	{"UCTL0_ORTO_CTL"              ,	   0x118006f000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1166},
+	{"UCTL0_PPAF_WM"               ,	   0x118006f000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1167},
+	{"UCTL0_UPHY_CTL_STATUS"       ,	   0x118006f000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1168},
+	{"UCTL0_UPHY_PORT000_CTL_STATUS",	   0x118006f000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1169},
+	{"UCTL0_UPHY_PORT001_CTL_STATUS",	   0x118006f000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1169},
+	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1170},
+	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1171},
+	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1172},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1173},
+	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1174},
+	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1175},
+	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1176},
+	{"ZIP_THROTTLE"                ,	   0x1180038000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1177},
 	{NULL,0,0,0,0}
 };
 static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
@@ -84023,7 +99073,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"DLL90_SETTING"               ,	20,	8,	142,	"RO",	1,	1,	0,	0},
 	{"DLL_FAST"                    ,	28,	1,	142,	"RO",	1,	1,	0,	0},
 	{"RESERVED_29_63"              ,	29,	35,	142,	"RAZ",	1,	1,	0,	0},
-	{"FCLKCNT"                     ,	0,	64,	143,	"RO",	0,	0,	0ull,	0ull},
+	{"FCLKCNT"                     ,	0,	64,	143,	"RO",	0,	1,	0ull,	0},
 	{"MWB"                         ,	0,	1,	144,	"RO",	0,	0,	0ull,	0ull},
 	{"RPB"                         ,	1,	1,	144,	"RO",	0,	0,	0ull,	0ull},
 	{"MFF"                         ,	2,	1,	144,	"RO",	0,	0,	0ull,	0ull},
@@ -84047,7 +99097,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"FADR"                        ,	4,	28,	148,	"RO",	0,	0,	0ull,	0ull},
 	{"FSYN"                        ,	32,	10,	148,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_42_63"              ,	42,	22,	148,	"RAZ",	1,	1,	0,	0},
-	{"IFBCNT"                      ,	0,	64,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"IFBCNT"                      ,	0,	64,	149,	"RO",	0,	1,	1ull,	0},
 	{"CWL"                         ,	0,	3,	150,	"R/W",	0,	0,	0ull,	0ull},
 	{"MPRLOC"                      ,	3,	2,	150,	"R/W",	0,	0,	0ull,	0ull},
 	{"MPR"                         ,	5,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
@@ -84061,7 +99111,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"RBT"                         ,	18,	1,	150,	"RO",	0,	0,	1ull,	1ull},
 	{"TM"                          ,	19,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
 	{"DLLR"                        ,	20,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
-	{"WRP"                         ,	21,	3,	150,	"R/W",	0,	0,	1ull,	1ull},
+	{"WRP"                         ,	21,	3,	150,	"R/W",	0,	0,	0ull,	0ull},
 	{"PPD"                         ,	24,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESERVED_25_63"              ,	25,	39,	150,	"RAZ",	1,	1,	0,	0},
 	{"PASR_00"                     ,	0,	3,	151,	"R/W",	0,	0,	0ull,	0ull},
@@ -84089,7 +99139,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"DIC_11"                      ,	43,	2,	151,	"R/W",	0,	0,	0ull,	0ull},
 	{"RTT_NOM_11"                  ,	45,	3,	151,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESERVED_48_63"              ,	48,	16,	151,	"RAZ",	1,	1,	0,	0},
-	{"OPSCNT"                      ,	0,	64,	152,	"RO",	0,	0,	0ull,	0ull},
+	{"OPSCNT"                      ,	0,	64,	152,	"RO",	0,	1,	1ull,	0},
 	{"TS_STAGGER"                  ,	0,	1,	153,	"R/W",	0,	1,	0ull,	0},
 	{"LOOPBACK_POS"                ,	1,	1,	153,	"R/W",	0,	1,	0ull,	0},
 	{"LOOPBACK"                    ,	2,	1,	153,	"R/W",	0,	1,	0ull,	0},
@@ -84153,7 +99203,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"TWLMRD"                      ,	28,	4,	162,	"R/W",	0,	0,	10ull,	10ull},
 	{"TWLDQSEN"                    ,	32,	4,	162,	"R/W",	0,	0,	7ull,	7ull},
 	{"TFAW"                        ,	36,	5,	162,	"R/W",	0,	0,	0ull,	9ull},
-	{"TXPDLL"                      ,	41,	5,	162,	"R/W",	0,	0,	10ull,	10ull},
+	{"TXPDLL"                      ,	41,	5,	162,	"R/W",	0,	0,	0ull,	10ull},
 	{"RESERVED_46_63"              ,	46,	18,	162,	"RAZ",	1,	1,	0,	0},
 	{"LANEMASK"                    ,	0,	9,	163,	"R/W",	0,	1,	0ull,	0},
 	{"SSET"                        ,	9,	1,	163,	"R/W",	0,	1,	0ull,	0},
@@ -84598,7 +99648,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"RESERVED_32_63"              ,	32,	32,	257,	"RAZ",	1,	1,	0,	0},
 	{"SEND"                        ,	0,	1,	258,	"R/W",	0,	0,	1ull,	1ull},
 	{"RESERVED_1_63"               ,	1,	63,	258,	"RAZ",	1,	1,	0,	0},
-	{"ALIGN"                       ,	0,	1,	259,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALIGN"                       ,	0,	1,	259,	"R/W",	0,	0,	1ull,	0ull},
 	{"RESERVED_1_63"               ,	1,	63,	259,	"RAZ",	1,	1,	0,	0},
 	{"SLOT"                        ,	0,	10,	260,	"R/W",	0,	0,	512ull,	512ull},
 	{"RESERVED_10_63"              ,	10,	54,	260,	"RAZ",	1,	1,	0,	0},
@@ -85221,7 +100271,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"WODT_BPRCH"                  ,	22,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
 	{"RODT_BPRCH"                  ,	23,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESERVED_24_63"              ,	24,	40,	408,	"RAZ",	1,	1,	0,	0},
-	{"DCLKCNT"                     ,	0,	64,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"DCLKCNT"                     ,	0,	64,	409,	"RO",	0,	1,	0ull,	0},
 	{"CLKF"                        ,	0,	7,	410,	"R/W",	0,	1,	48ull,	0},
 	{"RESET_N"                     ,	7,	1,	410,	"R/W",	0,	0,	0ull,	1ull},
 	{"CPB"                         ,	8,	3,	410,	"R/W",	0,	0,	0ull,	1ull},
@@ -85286,7 +100336,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"FBUNK"                       ,	33,	1,	417,	"RO",	0,	0,	0ull,	0ull},
 	{"FDIMM"                       ,	34,	2,	417,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_36_63"              ,	36,	28,	417,	"RAZ",	1,	1,	0,	0},
-	{"IFBCNT"                      ,	0,	64,	418,	"RO",	0,	0,	0ull,	0ull},
+	{"IFBCNT"                      ,	0,	64,	418,	"RO",	0,	1,	1ull,	0},
 	{"NXM_WR_ERR"                  ,	0,	1,	419,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"SEC_ERR"                     ,	1,	4,	419,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"DED_ERR"                     ,	5,	4,	419,	"R/W1C",	0,	0,	0ull,	0ull},
@@ -85308,7 +100358,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"RBT"                         ,	18,	1,	421,	"RO",	0,	0,	1ull,	1ull},
 	{"TM"                          ,	19,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
 	{"DLLR"                        ,	20,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
-	{"WRP"                         ,	21,	3,	421,	"R/W",	0,	0,	1ull,	1ull},
+	{"WRP"                         ,	21,	3,	421,	"R/W",	0,	0,	0ull,	0ull},
 	{"PPD"                         ,	24,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESERVED_25_63"              ,	25,	39,	421,	"RAZ",	1,	1,	0,	0},
 	{"PASR_00"                     ,	0,	3,	422,	"R/W",	0,	0,	0ull,	0ull},
@@ -85346,7 +100396,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"MEM_MSB_D3_R0"               ,	32,	4,	423,	"R/W",	0,	1,	0ull,	0},
 	{"MEM_MSB_D3_R1"               ,	36,	4,	423,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_40_63"              ,	40,	24,	423,	"RAZ",	1,	1,	0,	0},
-	{"OPSCNT"                      ,	0,	64,	424,	"RO",	0,	0,	0ull,	0ull},
+	{"OPSCNT"                      ,	0,	64,	424,	"RO",	0,	1,	1ull,	0},
 	{"TS_STAGGER"                  ,	0,	1,	425,	"R/W",	0,	1,	0ull,	0},
 	{"LOOPBACK_POS"                ,	1,	1,	425,	"R/W",	0,	1,	0ull,	0},
 	{"LOOPBACK"                    ,	2,	1,	425,	"R/W",	0,	1,	0ull,	0},
@@ -85421,7 +100471,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"TWLMRD"                      ,	28,	4,	435,	"R/W",	0,	0,	10ull,	10ull},
 	{"TWLDQSEN"                    ,	32,	4,	435,	"R/W",	0,	0,	7ull,	7ull},
 	{"TFAW"                        ,	36,	5,	435,	"R/W",	0,	0,	0ull,	9ull},
-	{"TXPDLL"                      ,	41,	5,	435,	"R/W",	0,	0,	10ull,	10ull},
+	{"TXPDLL"                      ,	41,	5,	435,	"R/W",	0,	0,	0ull,	10ull},
 	{"RESERVED_46_63"              ,	46,	18,	435,	"RAZ",	1,	1,	0,	0},
 	{"TRESET"                      ,	0,	1,	436,	"R/W",	0,	1,	1ull,	0},
 	{"RCLK_CNT"                    ,	1,	32,	436,	"R/W",	0,	1,	0ull,	0},
@@ -85691,8 +100741,8 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"RST_LINK"                    ,	7,	1,	487,	"R/W",	1,	1,	0,	0},
 	{"RST_DONE"                    ,	8,	1,	487,	"RO",	1,	1,	0,	0},
 	{"RESERVED_9_63"               ,	9,	55,	487,	"RAZ",	1,	1,	0,	0},
-	{"WARM_RST_DLY"                ,	0,	16,	488,	"R/W",	0,	1,	2047ull,	0},
-	{"SOFT_RST_DLY"                ,	16,	16,	488,	"R/W",	0,	1,	2047ull,	0},
+	{"SOFT_RST_DLY"                ,	0,	16,	488,	"R/W",	0,	1,	2047ull,	0},
+	{"WARM_RST_DLY"                ,	16,	16,	488,	"R/W",	0,	1,	2047ull,	0},
 	{"RESERVED_32_63"              ,	32,	32,	488,	"RAZ",	1,	1,	0,	0},
 	{"RST_LINK0"                   ,	0,	1,	489,	"R/W1C",	0,	1,	0ull,	0},
 	{"RST_LINK1"                   ,	1,	1,	489,	"R/W1C",	0,	1,	0ull,	0},
@@ -85839,7 +100889,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"MRGDAT"                      ,	4,	1,	520,	"RO",	0,	0,	0ull,	0ull},
 	{"OPFDAT"                      ,	5,	1,	520,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_6_63"               ,	6,	58,	520,	"RAZ",	0,	0,	0ull,	0ull},
-	{"MRQ_HWM"                     ,	0,	2,	521,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRQ_HWM"                     ,	0,	2,	521,	"R/W",	0,	0,	0ull,	1ull},
 	{"NBTARB"                      ,	2,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
 	{"LENDIAN"                     ,	3,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	4,	1,	521,	"R/W",	0,	0,	1ull,	0ull},
@@ -86095,7 +101145,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"AP_D"                        ,	20,	1,	573,	"RO",	0,	0,	0ull,	0ull},
 	{"TP"                          ,	21,	1,	573,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_22_31"              ,	22,	10,	573,	"RAZ",	1,	1,	0,	0},
-	{"MLS"                         ,	0,	4,	574,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"MLS"                         ,	0,	4,	574,	"RO/WRSL",	0,	1,	2ull,	0},
 	{"MLW"                         ,	4,	6,	574,	"RO/WRSL",	0,	0,	4ull,	4ull},
 	{"ASLPMS"                      ,	10,	2,	574,	"RO/WRSL",	0,	0,	3ull,	3ull},
 	{"L0EL"                        ,	12,	3,	574,	"RO/WRSL",	0,	0,	6ull,	6ull},
@@ -86164,7 +101214,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"CTD"                         ,	4,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESERVED_5_31"               ,	5,	27,	579,	"RAZ",	1,	1,	0,	0},
 	{"RESERVED_0_31"               ,	0,	32,	580,	"RAZ",	1,	1,	0,	0},
-	{"TLS"                         ,	0,	4,	581,	"R/W",	1,	0,	0,	2ull},
+	{"TLS"                         ,	0,	4,	581,	"R/W",	1,	1,	0,	0},
 	{"EC"                          ,	4,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
 	{"HASD"                        ,	5,	1,	581,	"RO",	0,	0,	0ull,	0ull},
 	{"SDE"                         ,	6,	1,	581,	"RO",	0,	0,	0ull,	0ull},
@@ -86250,8 +101300,8 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"DWORD2"                      ,	0,	32,	592,	"RO",	0,	0,	0ull,	0ull},
 	{"DWORD3"                      ,	0,	32,	593,	"RO",	0,	0,	0ull,	0ull},
 	{"DWORD4"                      ,	0,	32,	594,	"RO",	0,	0,	0ull,	0ull},
-	{"RTLTL"                       ,	0,	16,	595,	"R/W",	0,	0,	4143ull,	4143ull},
-	{"RTL"                         ,	16,	16,	595,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"RTLTL"                       ,	0,	16,	595,	"R/W",	0,	1,	4143ull,	0},
+	{"RTL"                         ,	16,	16,	595,	"R/W",	0,	1,	12429ull,	0},
 	{"OMR"                         ,	0,	32,	596,	"R/W",	0,	1,	4294967295ull,	0},
 	{"LINK_NUM"                    ,	0,	8,	597,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_8_14"               ,	8,	7,	597,	"RAZ",	1,	1,	0,	0},
@@ -86535,8 +101585,8 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"AP_D"                        ,	20,	1,	645,	"RO",	0,	0,	0ull,	0ull},
 	{"TP"                          ,	21,	1,	645,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_22_31"              ,	22,	10,	645,	"RAZ",	1,	1,	0,	0},
-	{"MLS"                         ,	0,	4,	646,	"R/W",	0,	0,	2ull,	2ull},
-	{"MLW"                         ,	4,	6,	646,	"R/W",	0,	0,	8ull,	8ull},
+	{"MLS"                         ,	0,	4,	646,	"R/W",	0,	1,	2ull,	0},
+	{"MLW"                         ,	4,	6,	646,	"R/W",	0,	0,	8ull,	4ull},
 	{"ASLPMS"                      ,	10,	2,	646,	"R/W",	0,	0,	3ull,	3ull},
 	{"L0EL"                        ,	12,	3,	646,	"R/W",	0,	0,	6ull,	6ull},
 	{"L1EL"                        ,	15,	3,	646,	"R/W",	0,	0,	6ull,	6ull},
@@ -86558,7 +101608,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"LBM_INT_ENB"                 ,	10,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
 	{"LAB_INT_ENB"                 ,	11,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESERVED_12_15"              ,	12,	4,	647,	"RAZ",	1,	1,	0,	0},
-	{"LS"                          ,	16,	4,	647,	"RO",	0,	0,	1ull,	1ull},
+	{"LS"                          ,	16,	4,	647,	"RO",	1,	1,	0,	0},
 	{"NLW"                         ,	20,	6,	647,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_26_26"              ,	26,	1,	647,	"RAZ",	1,	1,	0,	0},
 	{"LT"                          ,	27,	1,	647,	"RO",	0,	0,	0ull,	0ull},
@@ -86619,7 +101669,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"CTD"                         ,	4,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESERVED_5_31"               ,	5,	27,	653,	"RAZ",	1,	1,	0,	0},
 	{"RESERVED_0_31"               ,	0,	32,	654,	"RAZ",	1,	1,	0,	0},
-	{"TLS"                         ,	0,	4,	655,	"R/W",	1,	0,	0,	2ull},
+	{"TLS"                         ,	0,	4,	655,	"R/W",	1,	1,	0,	0},
 	{"EC"                          ,	4,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
 	{"HASD"                        ,	5,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
 	{"SDE"                         ,	6,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
@@ -86720,8 +101770,8 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"AEIMN"                       ,	27,	5,	670,	"R/W",	0,	0,	0ull,	0ull},
 	{"ECSI"                        ,	0,	16,	671,	"RO",	0,	0,	0ull,	0ull},
 	{"EFNFSI"                      ,	16,	16,	671,	"RO",	0,	0,	0ull,	0ull},
-	{"RTLTL"                       ,	0,	16,	672,	"R/W",	0,	0,	4143ull,	4143ull},
-	{"RTL"                         ,	16,	16,	672,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"RTLTL"                       ,	0,	16,	672,	"R/W",	0,	1,	4143ull,	0},
+	{"RTL"                         ,	16,	16,	672,	"R/W",	0,	1,	12429ull,	0},
 	{"OMR"                         ,	0,	32,	673,	"R/W",	0,	1,	4294967295ull,	0},
 	{"LINK_NUM"                    ,	0,	8,	674,	"R/W",	0,	0,	4ull,	4ull},
 	{"RESERVED_8_14"               ,	8,	7,	674,	"RAZ",	1,	1,	0,	0},
@@ -87447,87 +102497,74 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"RESERVED_1_63"               ,	1,	63,	769,	"RAZ",	1,	1,	0,	0},
 	{"DRP_OCTS"                    ,	0,	32,	770,	"R/W",	0,	1,	0ull,	0},
 	{"DRP_PKTS"                    ,	32,	32,	770,	"R/W",	0,	1,	0ull,	0},
-	{"OCTS"                        ,	0,	48,	771,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_48_63"              ,	48,	16,	771,	"RAZ",	1,	1,	0,	0},
-	{"RAW"                         ,	0,	32,	772,	"R/W",	0,	1,	0ull,	0},
-	{"PKTS"                        ,	32,	32,	772,	"R/W",	0,	1,	0ull,	0},
-	{"MCST"                        ,	0,	32,	773,	"R/W",	0,	1,	0ull,	0},
-	{"BCST"                        ,	32,	32,	773,	"R/W",	0,	1,	0ull,	0},
-	{"H64"                         ,	0,	32,	774,	"R/W",	0,	1,	0ull,	0},
-	{"H65TO127"                    ,	32,	32,	774,	"R/W",	0,	1,	0ull,	0},
-	{"H128TO255"                   ,	0,	32,	775,	"R/W",	0,	1,	0ull,	0},
-	{"H256TO511"                   ,	32,	32,	775,	"R/W",	0,	1,	0ull,	0},
-	{"H512TO1023"                  ,	0,	32,	776,	"R/W",	0,	1,	0ull,	0},
-	{"H1024TO1518"                 ,	32,	32,	776,	"R/W",	0,	1,	0ull,	0},
-	{"H1519"                       ,	0,	32,	777,	"R/W",	0,	1,	0ull,	0},
-	{"FCS"                         ,	32,	32,	777,	"R/W",	0,	1,	0ull,	0},
-	{"UNDERSZ"                     ,	0,	32,	778,	"R/W",	0,	1,	0ull,	0},
-	{"FRAG"                        ,	32,	32,	778,	"R/W",	0,	1,	0ull,	0},
-	{"OVERSZ"                      ,	0,	32,	779,	"R/W",	0,	1,	0ull,	0},
-	{"JABBER"                      ,	32,	32,	779,	"R/W",	0,	1,	0ull,	0},
-	{"RDCLR"                       ,	0,	1,	780,	"R/W",	0,	0,	1ull,	1ull},
-	{"RESERVED_1_63"               ,	1,	63,	780,	"RAZ",	1,	1,	0,	0},
-	{"ERRS"                        ,	0,	16,	781,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_16_63"              ,	16,	48,	781,	"RAZ",	1,	1,	0,	0},
-	{"OCTS"                        ,	0,	48,	782,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_48_63"              ,	48,	16,	782,	"RAZ",	1,	1,	0,	0},
-	{"PKTS"                        ,	0,	32,	783,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	783,	"RAZ",	1,	1,	0,	0},
-	{"EN"                          ,	0,	8,	784,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_8_63"               ,	8,	56,	784,	"RAZ",	1,	1,	0,	0},
-	{"MASK"                        ,	0,	16,	785,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	785,	"RAZ",	1,	1,	0,	0},
-	{"SRC"                         ,	0,	16,	786,	"R/W",	0,	0,	0ull,	0ull},
-	{"DST"                         ,	16,	16,	786,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	786,	"RAZ",	1,	1,	0,	0},
-	{"ENTRY"                       ,	0,	62,	787,	"RO",	1,	1,	0,	0},
-	{"RESERVED_62_62"              ,	62,	1,	787,	"RAZ",	1,	1,	0,	0},
-	{"VAL"                         ,	63,	1,	787,	"RO",	1,	1,	0,	0},
-	{"DRP_OCTS"                    ,	0,	32,	788,	"R/W",	0,	1,	0ull,	0},
-	{"DRP_PKTS"                    ,	32,	32,	788,	"R/W",	0,	1,	0ull,	0},
-	{"OCTS"                        ,	0,	48,	789,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_48_63"              ,	48,	16,	789,	"RAZ",	1,	1,	0,	0},
-	{"RAW"                         ,	0,	32,	790,	"R/W",	0,	1,	0ull,	0},
-	{"PKTS"                        ,	32,	32,	790,	"R/W",	0,	1,	0ull,	0},
-	{"MCST"                        ,	0,	32,	791,	"R/W",	0,	1,	0ull,	0},
-	{"BCST"                        ,	32,	32,	791,	"R/W",	0,	1,	0ull,	0},
-	{"H64"                         ,	0,	32,	792,	"R/W",	0,	1,	0ull,	0},
-	{"H65TO127"                    ,	32,	32,	792,	"R/W",	0,	1,	0ull,	0},
-	{"H128TO255"                   ,	0,	32,	793,	"R/W",	0,	1,	0ull,	0},
-	{"H256TO511"                   ,	32,	32,	793,	"R/W",	0,	1,	0ull,	0},
-	{"H512TO1023"                  ,	0,	32,	794,	"R/W",	0,	1,	0ull,	0},
-	{"H1024TO1518"                 ,	32,	32,	794,	"R/W",	0,	1,	0ull,	0},
-	{"H1519"                       ,	0,	32,	795,	"R/W",	0,	1,	0ull,	0},
-	{"FCS"                         ,	32,	32,	795,	"R/W",	0,	1,	0ull,	0},
-	{"UNDERSZ"                     ,	0,	32,	796,	"R/W",	0,	1,	0ull,	0},
-	{"FRAG"                        ,	32,	32,	796,	"R/W",	0,	1,	0ull,	0},
-	{"OVERSZ"                      ,	0,	32,	797,	"R/W",	0,	1,	0ull,	0},
-	{"JABBER"                      ,	32,	32,	797,	"R/W",	0,	1,	0ull,	0},
-	{"COUNT"                       ,	0,	32,	798,	"R/W1C",	1,	0,	0,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	798,	"RAZ",	1,	1,	0,	0},
-	{"COUNT"                       ,	0,	48,	799,	"R/W1C",	1,	0,	0,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	799,	"RAZ",	1,	1,	0,	0},
-	{"SIZE"                        ,	0,	16,	800,	"RO",	1,	0,	0,	0ull},
-	{"SEGS"                        ,	16,	6,	800,	"RO",	1,	0,	0,	0ull},
-	{"CMD"                         ,	22,	14,	800,	"RO",	1,	0,	0,	0ull},
-	{"FAU"                         ,	36,	28,	800,	"RO",	1,	0,	0,	0ull},
-	{"PTR"                         ,	0,	40,	801,	"RO",	1,	0,	0,	0ull},
-	{"SIZE"                        ,	40,	16,	801,	"RO",	1,	0,	0,	0ull},
-	{"POOL"                        ,	56,	3,	801,	"RO",	1,	0,	0,	0ull},
-	{"BACK"                        ,	59,	4,	801,	"RO",	1,	0,	0,	0ull},
-	{"I"                           ,	63,	1,	801,	"RO",	1,	0,	0,	0ull},
-	{"PTRS2"                       ,	0,	17,	802,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	802,	"RAZ",	1,	1,	0,	0},
-	{"PTRS1"                       ,	32,	17,	802,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	802,	"RAZ",	1,	1,	0,	0},
-	{"MOD"                         ,	0,	3,	803,	"RO",	1,	0,	0,	0ull},
-	{"CNT"                         ,	3,	13,	803,	"RO",	1,	0,	0,	0ull},
-	{"CHK"                         ,	16,	1,	803,	"RO",	1,	0,	0,	0ull},
-	{"LEN"                         ,	17,	1,	803,	"RO",	1,	0,	0,	0ull},
-	{"SOP"                         ,	18,	1,	803,	"RO",	1,	0,	0,	0ull},
-	{"UID"                         ,	19,	3,	803,	"RO",	1,	0,	0,	0ull},
-	{"MAJ"                         ,	22,	1,	803,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	803,	"RAZ",	1,	1,	0,	0},
+	{"MCAST"                       ,	0,	32,	771,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	771,	"R/W",	0,	1,	0ull,	0},
+	{"MCAST"                       ,	0,	32,	772,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	772,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	773,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	773,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	774,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	774,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	775,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	775,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	776,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	776,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	777,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	777,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	778,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	778,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	779,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	779,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	780,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	780,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	781,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	781,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	782,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	782,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	783,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	783,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	784,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	784,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	785,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	785,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	786,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	786,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	787,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	787,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	788,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	788,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	788,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	789,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	789,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	789,	"RO",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	790,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	790,	"R/W",	0,	1,	0ull,	0},
+	{"MCAST"                       ,	0,	32,	791,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	791,	"R/W",	0,	1,	0ull,	0},
+	{"MCAST"                       ,	0,	32,	792,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	792,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	793,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	793,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	794,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	794,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	795,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	795,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	796,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	796,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	797,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	797,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	798,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	798,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	799,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	799,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	800,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	800,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	801,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	801,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	32,	802,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	802,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	803,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	803,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	16,	804,	"RO",	1,	0,	0,	0ull},
 	{"SEGS"                        ,	16,	6,	804,	"RO",	1,	0,	0,	0ull},
 	{"CMD"                         ,	22,	14,	804,	"RO",	1,	0,	0,	0ull},
@@ -87537,2073 +102574,2062 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"POOL"                        ,	56,	3,	805,	"RO",	1,	0,	0,	0ull},
 	{"BACK"                        ,	59,	4,	805,	"RO",	1,	0,	0,	0ull},
 	{"I"                           ,	63,	1,	805,	"RO",	1,	0,	0,	0ull},
-	{"DATA"                        ,	0,	64,	806,	"RO",	1,	0,	0,	0ull},
-	{"PTR"                         ,	0,	40,	807,	"RO",	1,	0,	0,	0ull},
-	{"SIZE"                        ,	40,	16,	807,	"RO",	1,	0,	0,	0ull},
-	{"POOL"                        ,	56,	3,	807,	"RO",	1,	0,	0,	0ull},
-	{"BACK"                        ,	59,	4,	807,	"RO",	1,	0,	0,	0ull},
-	{"I"                           ,	63,	1,	807,	"RO",	1,	0,	0,	0ull},
-	{"DATA"                        ,	0,	64,	808,	"RO",	1,	0,	0,	0ull},
-	{"MAJOR"                       ,	0,	3,	809,	"RO",	1,	0,	0,	0ull},
-	{"MINOR"                       ,	3,	2,	809,	"RO",	1,	0,	0,	0ull},
-	{"WAIT"                        ,	5,	1,	809,	"RO",	1,	0,	0,	0ull},
-	{"CHK_MODE"                    ,	6,	1,	809,	"RO",	1,	0,	0,	0ull},
-	{"CHK_ONCE"                    ,	7,	1,	809,	"RO",	1,	0,	0,	0ull},
-	{"INIT_DWRITE"                 ,	8,	1,	809,	"RO",	1,	0,	0,	0ull},
-	{"DREAD_SOP"                   ,	9,	1,	809,	"RO",	1,	0,	0,	0ull},
-	{"UID"                         ,	10,	2,	809,	"RO",	1,	0,	0,	0ull},
-	{"CMND_OFF"                    ,	12,	6,	809,	"RO",	1,	0,	0,	0ull},
-	{"CMND_SIZ"                    ,	18,	16,	809,	"RO",	1,	0,	0,	0ull},
-	{"CMND_SEGS"                   ,	34,	6,	809,	"RO",	1,	0,	0,	0ull},
-	{"CURR_OFF"                    ,	40,	16,	809,	"RO",	1,	0,	0,	0ull},
-	{"CURR_SIZ"                    ,	56,	8,	809,	"RO",	1,	0,	0,	0ull},
-	{"CURR_SIZ"                    ,	0,	8,	810,	"RO",	1,	0,	0,	0ull},
-	{"CURR_PTR"                    ,	8,	40,	810,	"RO",	1,	0,	0,	0ull},
-	{"NXT_INFLT"                   ,	48,	6,	810,	"RO",	1,	0,	0,	0ull},
-	{"MAJOR_3"                     ,	54,	1,	810,	"RO",	1,	0,	0,	0ull},
-	{"PTP"                         ,	55,	1,	810,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_56_63"              ,	56,	8,	810,	"RAZ",	1,	1,	0,	0},
-	{"QID_BASE"                    ,	0,	8,	811,	"RO",	1,	0,	0,	0ull},
-	{"QID_OFF"                     ,	8,	4,	811,	"RO",	1,	0,	0,	0ull},
-	{"QID_OFFMAX"                  ,	12,	4,	811,	"RO",	1,	0,	0,	0ull},
-	{"QCB_RIDX"                    ,	16,	5,	811,	"RO",	1,	0,	0,	0ull},
-	{"QOS"                         ,	21,	3,	811,	"RO",	1,	0,	0,	0ull},
-	{"STATC"                       ,	24,	1,	811,	"RO",	1,	0,	0,	0ull},
-	{"ACTIVE"                      ,	25,	1,	811,	"RO",	1,	0,	0,	0ull},
-	{"PREEMPTED"                   ,	26,	1,	811,	"RO",	1,	0,	0,	0ull},
-	{"PREEMPTEE"                   ,	27,	1,	811,	"RO",	1,	0,	0,	0ull},
-	{"PREEMPTER"                   ,	28,	1,	811,	"RO",	1,	0,	0,	0ull},
-	{"QID_OFFTHS"                  ,	29,	4,	811,	"RO",	1,	0,	0,	0ull},
-	{"QID_OFFRES"                  ,	33,	4,	811,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_37_63"              ,	37,	27,	811,	"RO",	1,	0,	0,	0ull},
-	{"QCB_RIDX"                    ,	0,	6,	812,	"RO",	1,	0,	0,	0ull},
-	{"QCB_WIDX"                    ,	6,	6,	812,	"RO",	1,	0,	0,	0ull},
-	{"BUF_PTR"                     ,	12,	33,	812,	"RO",	1,	0,	0,	0ull},
-	{"BUF_SIZ"                     ,	45,	13,	812,	"RO",	1,	0,	0,	0ull},
-	{"TAIL"                        ,	58,	1,	812,	"RO",	1,	0,	0,	0ull},
-	{"QOS"                         ,	59,	5,	812,	"RO",	1,	0,	0,	0ull},
-	{"QOS"                         ,	0,	3,	813,	"RO",	1,	0,	0,	0ull},
-	{"STATIC_Q"                    ,	3,	1,	813,	"RO",	1,	0,	0,	0ull},
-	{"S_TAIL"                      ,	4,	1,	813,	"RO",	1,	0,	0,	0ull},
-	{"STATIC_P"                    ,	5,	1,	813,	"RO",	1,	0,	0,	0ull},
-	{"PREEMPTEE"                   ,	6,	1,	813,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_7_7"                ,	7,	1,	813,	"RAZ",	1,	1,	0,	0},
-	{"DOORBELL"                    ,	8,	20,	813,	"RO",	1,	0,	0,	0ull},
-	{"PREEMPTER"                   ,	28,	1,	813,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_29_63"              ,	29,	35,	813,	"RAZ",	1,	1,	0,	0},
-	{"PTRS3"                       ,	0,	17,	814,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	814,	"RAZ",	1,	1,	0,	0},
-	{"PTRS0"                       ,	32,	17,	814,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	814,	"RAZ",	1,	1,	0,	0},
-	{"PID"                         ,	0,	6,	815,	"R/W",	1,	0,	0,	0ull},
-	{"EID"                         ,	6,	4,	815,	"R/W",	1,	0,	0,	0ull},
-	{"BP_PORT"                     ,	10,	6,	815,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_16_52"              ,	16,	37,	815,	"RAZ",	1,	1,	0,	0},
-	{"QOS_MASK"                    ,	53,	8,	815,	"R/W",	1,	0,	0,	0ull},
-	{"STATIC_P"                    ,	61,	1,	815,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_62_63"              ,	62,	2,	815,	"RAZ",	1,	1,	0,	0},
-	{"PID"                         ,	0,	6,	816,	"R/W",	1,	0,	0,	0ull},
-	{"EID"                         ,	6,	4,	816,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_10_52"              ,	10,	43,	816,	"RAZ",	1,	1,	0,	0},
-	{"QOS_MASK"                    ,	53,	8,	816,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	816,	"RAZ",	1,	1,	0,	0},
-	{"PID"                         ,	0,	6,	817,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	817,	"RAZ",	1,	1,	0,	0},
-	{"RATE_PKT"                    ,	8,	24,	817,	"R/W",	1,	0,	0,	0ull},
-	{"RATE_WORD"                   ,	32,	19,	817,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_51_63"              ,	51,	13,	817,	"RAZ",	1,	1,	0,	0},
-	{"PID"                         ,	0,	6,	818,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	818,	"RAZ",	1,	1,	0,	0},
-	{"RATE_LIM"                    ,	8,	24,	818,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	818,	"RAZ",	1,	1,	0,	0},
-	{"QUEUE"                       ,	0,	7,	819,	"R/W",	1,	0,	0,	0ull},
-	{"PORT"                        ,	7,	6,	819,	"WR0",	1,	0,	0,	0ull},
-	{"INDEX"                       ,	13,	3,	819,	"WR0",	1,	0,	0,	0ull},
-	{"TAIL"                        ,	16,	1,	819,	"R/W",	1,	0,	0,	0ull},
-	{"BUF_PTR"                     ,	17,	36,	819,	"R/W",	1,	0,	0,	0ull},
+	{"PTRS2"                       ,	0,	17,	806,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	806,	"RAZ",	1,	1,	0,	0},
+	{"PTRS1"                       ,	32,	17,	806,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	806,	"RAZ",	1,	1,	0,	0},
+	{"MOD"                         ,	0,	3,	807,	"RO",	1,	0,	0,	0ull},
+	{"CNT"                         ,	3,	13,	807,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	16,	1,	807,	"RO",	1,	0,	0,	0ull},
+	{"LEN"                         ,	17,	1,	807,	"RO",	1,	0,	0,	0ull},
+	{"SOP"                         ,	18,	1,	807,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	19,	3,	807,	"RO",	1,	0,	0,	0ull},
+	{"MAJ"                         ,	22,	1,	807,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	807,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	808,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	808,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	808,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	808,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	809,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	809,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	809,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	809,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	809,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	810,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	811,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	811,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	811,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	811,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	811,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	812,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	3,	813,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	3,	2,	813,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	5,	1,	813,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	6,	1,	813,	"RO",	1,	0,	0,	0ull},
+	{"CHK_ONCE"                    ,	7,	1,	813,	"RO",	1,	0,	0,	0ull},
+	{"INIT_DWRITE"                 ,	8,	1,	813,	"RO",	1,	0,	0,	0ull},
+	{"DREAD_SOP"                   ,	9,	1,	813,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	10,	2,	813,	"RO",	1,	0,	0,	0ull},
+	{"CMND_OFF"                    ,	12,	6,	813,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	18,	16,	813,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	34,	6,	813,	"RO",	1,	0,	0,	0ull},
+	{"CURR_OFF"                    ,	40,	16,	813,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	56,	8,	813,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	0,	8,	814,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	8,	40,	814,	"RO",	1,	0,	0,	0ull},
+	{"NXT_INFLT"                   ,	48,	6,	814,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR_3"                     ,	54,	1,	814,	"RO",	1,	0,	0,	0ull},
+	{"PTP"                         ,	55,	1,	814,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	814,	"RAZ",	1,	1,	0,	0},
+	{"QID_BASE"                    ,	0,	8,	815,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	8,	4,	815,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFMAX"                  ,	12,	4,	815,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	16,	5,	815,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	21,	3,	815,	"RO",	1,	0,	0,	0ull},
+	{"STATC"                       ,	24,	1,	815,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	25,	1,	815,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTED"                   ,	26,	1,	815,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	27,	1,	815,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	815,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFTHS"                  ,	29,	4,	815,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFRES"                  ,	33,	4,	815,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	815,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	6,	816,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	6,	6,	816,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	12,	33,	816,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	45,	13,	816,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	58,	1,	816,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	59,	5,	816,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	3,	817,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	3,	1,	817,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	4,	1,	817,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	5,	1,	817,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	6,	1,	817,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	817,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	8,	20,	817,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	817,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	817,	"RAZ",	1,	1,	0,	0},
+	{"PTRS3"                       ,	0,	17,	818,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	818,	"RAZ",	1,	1,	0,	0},
+	{"PTRS0"                       ,	32,	17,	818,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	818,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	819,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	819,	"R/W",	1,	0,	0,	0ull},
+	{"BP_PORT"                     ,	10,	6,	819,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_52"              ,	16,	37,	819,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	819,	"R/W",	1,	0,	0,	0ull},
-	{"STATIC_Q"                    ,	61,	1,	819,	"R/W",	1,	0,	0,	0ull},
-	{"STATIC_P"                    ,	62,	1,	819,	"R/W",	1,	0,	0,	0ull},
-	{"S_TAIL"                      ,	63,	1,	819,	"R/W",	1,	0,	0,	0ull},
-	{"QID"                         ,	0,	7,	820,	"R/W",	1,	0,	0,	0ull},
-	{"PID"                         ,	7,	6,	820,	"WR0",	1,	0,	0,	0ull},
-	{"RESERVED_13_52"              ,	13,	40,	820,	"RAZ",	1,	1,	0,	0},
+	{"STATIC_P"                    ,	61,	1,	819,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	819,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	820,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	820,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_10_52"              ,	10,	43,	820,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	820,	"R/W",	1,	0,	0,	0ull},
 	{"RESERVED_61_63"              ,	61,	3,	820,	"RAZ",	1,	1,	0,	0},
-	{"DAT_PTR"                     ,	0,	4,	821,	"RO",	1,	0,	0,	0ull},
-	{"DAT_DAT"                     ,	4,	2,	821,	"RO",	1,	0,	0,	0ull},
-	{"PRT_CTL"                     ,	6,	2,	821,	"RO",	1,	0,	0,	0ull},
-	{"PRT_QSB"                     ,	8,	3,	821,	"RO",	1,	0,	0,	0ull},
-	{"PRT_QCB"                     ,	11,	2,	821,	"RO",	1,	0,	0,	0ull},
-	{"NCB_INB"                     ,	13,	2,	821,	"RO",	1,	0,	0,	0ull},
-	{"PRT_PSB"                     ,	15,	8,	821,	"RO",	1,	0,	0,	0ull},
-	{"PRT_NXT"                     ,	23,	1,	821,	"RO",	1,	0,	0,	0ull},
-	{"PRT_CHK"                     ,	24,	3,	821,	"RO",	1,	0,	0,	0ull},
-	{"OUT_WIF"                     ,	27,	1,	821,	"RO",	1,	0,	0,	0ull},
-	{"OUT_STA"                     ,	28,	1,	821,	"RO",	1,	0,	0,	0ull},
-	{"OUT_CTL"                     ,	29,	3,	821,	"RO",	1,	0,	0,	0ull},
-	{"OUT_DAT"                     ,	32,	1,	821,	"RO",	1,	0,	0,	0ull},
-	{"IOB"                         ,	33,	1,	821,	"RO",	1,	0,	0,	0ull},
-	{"CSR"                         ,	34,	1,	821,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_35_63"              ,	35,	29,	821,	"RAZ",	1,	1,	0,	0},
-	{"SIZE"                        ,	0,	13,	822,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_13_19"              ,	13,	7,	822,	"R/W",	0,	0,	0ull,	0ull},
-	{"POOL"                        ,	20,	3,	822,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	822,	"RAZ",	1,	1,	0,	0},
-	{"ASSERTS"                     ,	0,	64,	823,	"RO",	0,	0,	0ull,	0ull},
-	{"ASSERTS"                     ,	0,	64,	824,	"RO",	0,	0,	0ull,	0ull},
-	{"ASSERTS"                     ,	0,	64,	825,	"RO",	0,	0,	0ull,	0ull},
-	{"ASSERTS"                     ,	0,	64,	826,	"RO",	0,	0,	0ull,	0ull},
-	{"ENGINE0"                     ,	0,	4,	827,	"R/W",	0,	0,	4ull,	4ull},
-	{"ENGINE1"                     ,	4,	4,	827,	"R/W",	0,	0,	4ull,	4ull},
-	{"ENGINE2"                     ,	8,	4,	827,	"R/W",	0,	0,	4ull,	4ull},
-	{"ENGINE3"                     ,	12,	4,	827,	"R/W",	0,	0,	4ull,	4ull},
-	{"ENGINE4"                     ,	16,	4,	827,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENGINE5"                     ,	20,	4,	827,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENGINE6"                     ,	24,	4,	827,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENGINE7"                     ,	28,	4,	827,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENGINE8"                     ,	32,	4,	827,	"R/W",	0,	0,	4ull,	4ull},
-	{"ENGINE9"                     ,	36,	4,	827,	"R/W",	0,	0,	4ull,	4ull},
-	{"ENGINE10"                    ,	40,	4,	827,	"R/W",	0,	0,	4ull,	4ull},
-	{"ENGINE11"                    ,	44,	4,	827,	"R/W",	0,	0,	4ull,	4ull},
-	{"RESERVED_48_63"              ,	48,	16,	827,	"RAZ",	1,	1,	0,	0},
-	{"MASK"                        ,	0,	12,	828,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_12_63"              ,	12,	52,	828,	"RAZ",	1,	1,	0,	0},
-	{"PARITY"                      ,	0,	1,	829,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"DOORBELL"                    ,	1,	1,	829,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"CURRZERO"                    ,	2,	1,	829,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	829,	"RAZ",	1,	1,	0,	0},
-	{"ENA_PKO"                     ,	0,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENA_DWB"                     ,	1,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
-	{"STORE_BE"                    ,	2,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESET"                       ,	3,	1,	830,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	830,	"RAZ",	1,	1,	0,	0},
-	{"MODE0"                       ,	0,	3,	831,	"R/W",	0,	0,	2ull,	2ull},
-	{"MODE1"                       ,	3,	3,	831,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	831,	"RAZ",	1,	1,	0,	0},
-	{"PARITY"                      ,	0,	1,	832,	"R/W",	0,	0,	0ull,	0ull},
-	{"DOORBELL"                    ,	1,	1,	832,	"R/W",	0,	0,	0ull,	0ull},
-	{"CURRZERO"                    ,	2,	1,	832,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	832,	"RAZ",	1,	1,	0,	0},
-	{"MODE"                        ,	0,	2,	833,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	833,	"RAZ",	1,	1,	0,	0},
-	{"QID7"                        ,	0,	1,	834,	"R/W",	0,	0,	0ull,	0ull},
-	{"IDX3"                        ,	1,	1,	834,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	834,	"RAZ",	1,	1,	0,	0},
-	{"INDEX"                       ,	0,	8,	835,	"R/W",	0,	0,	0ull,	0ull},
-	{"INC"                         ,	8,	8,	835,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	835,	"RAZ",	1,	1,	0,	0},
-	{"WQE_WORD"                    ,	0,	4,	836,	"R/W",	0,	0,	2ull,	2ull},
-	{"RESERVED_4_63"               ,	4,	60,	836,	"RAZ",	1,	1,	0,	0},
-	{"ADR"                         ,	0,	1,	837,	"RO",	0,	0,	0ull,	0ull},
-	{"PEND"                        ,	1,	1,	837,	"RO",	0,	0,	0ull,	0ull},
-	{"FIDX"                        ,	2,	1,	837,	"RO",	0,	0,	0ull,	0ull},
-	{"INDEX"                       ,	3,	1,	837,	"RO",	0,	0,	0ull,	0ull},
-	{"NBT"                         ,	4,	4,	837,	"RO",	0,	0,	0ull,	0ull},
-	{"NBR"                         ,	8,	3,	837,	"RO",	0,	0,	0ull,	0ull},
-	{"CAM"                         ,	11,	1,	837,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_12_15"              ,	12,	4,	837,	"RAZ",	1,	1,	0,	0},
-	{"PP"                          ,	16,	6,	837,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_22_63"              ,	22,	42,	837,	"RAZ",	1,	1,	0,	0},
-	{"DS_PC"                       ,	0,	32,	838,	"R/W1C",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	838,	"RAZ",	1,	1,	0,	0},
-	{"SBE"                         ,	0,	1,	839,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"DBE"                         ,	1,	1,	839,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"SBE_IE"                      ,	2,	1,	839,	"R/W",	0,	1,	0ull,	0},
-	{"DBE_IE"                      ,	3,	1,	839,	"R/W",	0,	1,	0ull,	0},
-	{"SYN"                         ,	4,	5,	839,	"RO",	1,	1,	0,	0},
-	{"RESERVED_9_11"               ,	9,	3,	839,	"RAZ",	1,	1,	0,	0},
-	{"RPE"                         ,	12,	1,	839,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RPE_IE"                      ,	13,	1,	839,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_14_15"              ,	14,	2,	839,	"RAZ",	1,	1,	0,	0},
-	{"IOP"                         ,	16,	13,	839,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_29_31"              ,	29,	3,	839,	"RAZ",	1,	1,	0,	0},
-	{"IOP_IE"                      ,	32,	13,	839,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_45_63"              ,	45,	19,	839,	"RAZ",	1,	1,	0,	0},
-	{"NBR_THR"                     ,	0,	5,	840,	"R/W",	0,	0,	2ull,	2ull},
-	{"PFR_DIS"                     ,	5,	1,	840,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	840,	"RAZ",	1,	1,	0,	0},
-	{"IQ_CNT"                      ,	0,	32,	841,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	841,	"RAZ",	1,	1,	0,	0},
-	{"IQ_CNT"                      ,	0,	32,	842,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	842,	"RAZ",	1,	1,	0,	0},
-	{"IQ_INT"                      ,	0,	8,	843,	"R/W1C",	0,	1,	0ull,	0},
-	{"RESERVED_8_63"               ,	8,	56,	843,	"RAZ",	1,	1,	0,	0},
-	{"INT_EN"                      ,	0,	8,	844,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_8_63"               ,	8,	56,	844,	"RAZ",	1,	1,	0,	0},
-	{"IQ_THR"                      ,	0,	32,	845,	"R/W",	0,	1,	4294967295ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	845,	"RAZ",	1,	1,	0,	0},
-	{"NOS_CNT"                     ,	0,	11,	846,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_11_63"              ,	11,	53,	846,	"RAZ",	1,	1,	0,	0},
-	{"NW_TIM"                      ,	0,	10,	847,	"R/W",	0,	0,	0ull,	1023ull},
-	{"RESERVED_10_63"              ,	10,	54,	847,	"RAZ",	1,	1,	0,	0},
-	{"RST_MSK"                     ,	0,	8,	848,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_8_63"               ,	8,	56,	848,	"RAZ",	1,	1,	0,	0},
-	{"GRP_MSK"                     ,	0,	16,	849,	"R/W",	0,	0,	65535ull,	65535ull},
-	{"QOS0_PRI"                    ,	16,	4,	849,	"R/W",	0,	1,	0ull,	0},
-	{"QOS1_PRI"                    ,	20,	4,	849,	"R/W",	0,	1,	0ull,	0},
-	{"QOS2_PRI"                    ,	24,	4,	849,	"R/W",	0,	1,	0ull,	0},
-	{"QOS3_PRI"                    ,	28,	4,	849,	"R/W",	0,	1,	0ull,	0},
-	{"QOS4_PRI"                    ,	32,	4,	849,	"R/W",	0,	1,	0ull,	0},
-	{"QOS5_PRI"                    ,	36,	4,	849,	"R/W",	0,	1,	0ull,	0},
-	{"QOS6_PRI"                    ,	40,	4,	849,	"R/W",	0,	1,	0ull,	0},
-	{"QOS7_PRI"                    ,	44,	4,	849,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_48_63"              ,	48,	16,	849,	"RAZ",	1,	1,	0,	0},
-	{"RND"                         ,	0,	8,	850,	"R/W",	0,	1,	255ull,	0},
-	{"RND_P1"                      ,	8,	8,	850,	"R/W",	0,	1,	255ull,	0},
-	{"RND_P2"                      ,	16,	8,	850,	"R/W",	0,	1,	255ull,	0},
-	{"RND_P3"                      ,	24,	8,	850,	"R/W",	0,	1,	255ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	850,	"RAZ",	1,	1,	0,	0},
-	{"MIN_THR"                     ,	0,	10,	851,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_10_11"              ,	10,	2,	851,	"RAZ",	1,	1,	0,	0},
-	{"MAX_THR"                     ,	12,	10,	851,	"R/W",	0,	1,	1023ull,	0},
-	{"RESERVED_22_23"              ,	22,	2,	851,	"RAZ",	1,	1,	0,	0},
-	{"FREE_CNT"                    ,	24,	11,	851,	"RO",	0,	1,	1011ull,	0},
-	{"RESERVED_35_35"              ,	35,	1,	851,	"RAZ",	1,	1,	0,	0},
-	{"BUF_CNT"                     ,	36,	11,	851,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_47_47"              ,	47,	1,	851,	"RAZ",	1,	1,	0,	0},
-	{"DES_CNT"                     ,	48,	11,	851,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_59_63"              ,	59,	5,	851,	"RAZ",	1,	1,	0,	0},
-	{"TS_PC"                       ,	0,	32,	852,	"R/W1C",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	852,	"RAZ",	1,	1,	0,	0},
-	{"WA_PC"                       ,	0,	32,	853,	"R/W1C",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	853,	"RAZ",	1,	1,	0,	0},
-	{"WA_PC"                       ,	0,	32,	854,	"R/W1C",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	854,	"RAZ",	1,	1,	0,	0},
-	{"WQ_INT"                      ,	0,	16,	855,	"R/W1C",	0,	1,	0ull,	0},
-	{"IQ_DIS"                      ,	16,	16,	855,	"R/W1",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	855,	"RAZ",	1,	1,	0,	0},
-	{"IQ_CNT"                      ,	0,	11,	856,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_11_11"              ,	11,	1,	856,	"RAZ",	1,	1,	0,	0},
-	{"DS_CNT"                      ,	12,	11,	856,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_23_23"              ,	23,	1,	856,	"RAZ",	1,	1,	0,	0},
-	{"TC_CNT"                      ,	24,	4,	856,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_28_63"              ,	28,	36,	856,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_7"                ,	0,	8,	857,	"RAZ",	1,	1,	0,	0},
-	{"PC_THR"                      ,	8,	20,	857,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_28_31"              ,	28,	4,	857,	"RAZ",	1,	1,	0,	0},
-	{"PC"                          ,	32,	28,	857,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_60_63"              ,	60,	4,	857,	"RAZ",	1,	1,	0,	0},
-	{"IQ_THR"                      ,	0,	10,	858,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_10_11"              ,	10,	2,	858,	"RAZ",	1,	1,	0,	0},
-	{"DS_THR"                      ,	12,	10,	858,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_22_23"              ,	22,	2,	858,	"RAZ",	1,	1,	0,	0},
-	{"TC_THR"                      ,	24,	4,	858,	"R/W",	0,	1,	0ull,	0},
-	{"TC_EN"                       ,	28,	1,	858,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_29_63"              ,	29,	35,	858,	"RAZ",	1,	1,	0,	0},
-	{"WS_PC"                       ,	0,	32,	859,	"R/W1C",	0,	1,	0ull,	0},
+	{"PID"                         ,	0,	6,	821,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	821,	"RAZ",	1,	1,	0,	0},
+	{"RATE_PKT"                    ,	8,	24,	821,	"R/W",	1,	0,	0,	0ull},
+	{"RATE_WORD"                   ,	32,	19,	821,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	821,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	822,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	822,	"RAZ",	1,	1,	0,	0},
+	{"RATE_LIM"                    ,	8,	24,	822,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	822,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE"                       ,	0,	7,	823,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	7,	6,	823,	"WR0",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	13,	3,	823,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	16,	1,	823,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	17,	36,	823,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	823,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	823,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	823,	"R/W",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	823,	"R/W",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	7,	824,	"R/W",	1,	0,	0,	0ull},
+	{"PID"                         ,	7,	6,	824,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	824,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	824,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	824,	"RAZ",	1,	1,	0,	0},
+	{"DAT_PTR"                     ,	0,	4,	825,	"RO",	1,	0,	0,	0ull},
+	{"DAT_DAT"                     ,	4,	2,	825,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CTL"                     ,	6,	2,	825,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QSB"                     ,	8,	3,	825,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QCB"                     ,	11,	2,	825,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	13,	2,	825,	"RO",	1,	0,	0,	0ull},
+	{"PRT_PSB"                     ,	15,	8,	825,	"RO",	1,	0,	0,	0ull},
+	{"PRT_NXT"                     ,	23,	1,	825,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CHK"                     ,	24,	3,	825,	"RO",	1,	0,	0,	0ull},
+	{"OUT_WIF"                     ,	27,	1,	825,	"RO",	1,	0,	0,	0ull},
+	{"OUT_STA"                     ,	28,	1,	825,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CTL"                     ,	29,	3,	825,	"RO",	1,	0,	0,	0ull},
+	{"OUT_DAT"                     ,	32,	1,	825,	"RO",	1,	0,	0,	0ull},
+	{"IOB"                         ,	33,	1,	825,	"RO",	1,	0,	0,	0ull},
+	{"CSR"                         ,	34,	1,	825,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	825,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	13,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	826,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	64,	827,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	828,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	829,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	830,	"RO",	0,	0,	0ull,	0ull},
+	{"ENGINE0"                     ,	0,	4,	831,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE1"                     ,	4,	4,	831,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE2"                     ,	8,	4,	831,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE3"                     ,	12,	4,	831,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE4"                     ,	16,	4,	831,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE5"                     ,	20,	4,	831,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE6"                     ,	24,	4,	831,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE7"                     ,	28,	4,	831,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE8"                     ,	32,	4,	831,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE9"                     ,	36,	4,	831,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE10"                    ,	40,	4,	831,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE11"                    ,	44,	4,	831,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_48_63"              ,	48,	16,	831,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	12,	832,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	832,	"RAZ",	1,	1,	0,	0},
+	{"PARITY"                      ,	0,	1,	833,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	833,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	833,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	833,	"RAZ",	1,	1,	0,	0},
+	{"ENA_PKO"                     ,	0,	1,	834,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	834,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	834,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	834,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	834,	"RAZ",	1,	1,	0,	0},
+	{"MODE0"                       ,	0,	3,	835,	"R/W",	0,	0,	2ull,	2ull},
+	{"MODE1"                       ,	3,	3,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	835,	"RAZ",	1,	1,	0,	0},
+	{"PARITY"                      ,	0,	1,	836,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	836,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	836,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	836,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	16,	837,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	837,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	838,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	838,	"RAZ",	1,	1,	0,	0},
+	{"PREEMPTER"                   ,	0,	1,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"PREEMPTEE"                   ,	1,	1,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	839,	"RAZ",	1,	1,	0,	0},
+	{"QID7"                        ,	0,	1,	840,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDX3"                        ,	1,	1,	840,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	840,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	841,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	841,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	841,	"RAZ",	1,	1,	0,	0},
+	{"WQE_WORD"                    ,	0,	4,	842,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_4_63"               ,	4,	60,	842,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	1,	843,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND"                        ,	1,	1,	843,	"RO",	0,	0,	0ull,	0ull},
+	{"FIDX"                        ,	2,	1,	843,	"RO",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	3,	1,	843,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT"                         ,	4,	4,	843,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR"                         ,	8,	3,	843,	"RO",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	11,	1,	843,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	843,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	16,	6,	843,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	843,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	32,	844,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	844,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	845,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	845,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE_IE"                      ,	2,	1,	845,	"R/W",	0,	1,	0ull,	0},
+	{"DBE_IE"                      ,	3,	1,	845,	"R/W",	0,	1,	0ull,	0},
+	{"SYN"                         ,	4,	5,	845,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_11"               ,	9,	3,	845,	"RAZ",	1,	1,	0,	0},
+	{"RPE"                         ,	12,	1,	845,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE_IE"                      ,	13,	1,	845,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	845,	"RAZ",	1,	1,	0,	0},
+	{"IOP"                         ,	16,	13,	845,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	845,	"RAZ",	1,	1,	0,	0},
+	{"IOP_IE"                      ,	32,	13,	845,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_63"              ,	45,	19,	845,	"RAZ",	1,	1,	0,	0},
+	{"NBR_THR"                     ,	0,	5,	846,	"R/W",	0,	0,	2ull,	2ull},
+	{"PFR_DIS"                     ,	5,	1,	846,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	846,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	847,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	847,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	848,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	848,	"RAZ",	1,	1,	0,	0},
+	{"IQ_INT"                      ,	0,	8,	849,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	849,	"RAZ",	1,	1,	0,	0},
+	{"INT_EN"                      ,	0,	8,	850,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	850,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	32,	851,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	851,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	11,	852,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	852,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	853,	"R/W",	0,	0,	0ull,	4ull},
+	{"RESERVED_10_63"              ,	10,	54,	853,	"RAZ",	1,	1,	0,	0},
+	{"RST_MSK"                     ,	0,	8,	854,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	854,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	16,	855,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"QOS0_PRI"                    ,	16,	4,	855,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1_PRI"                    ,	20,	4,	855,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2_PRI"                    ,	24,	4,	855,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3_PRI"                    ,	28,	4,	855,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4_PRI"                    ,	32,	4,	855,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5_PRI"                    ,	36,	4,	855,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6_PRI"                    ,	40,	4,	855,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7_PRI"                    ,	44,	4,	855,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	855,	"RAZ",	1,	1,	0,	0},
+	{"RND"                         ,	0,	8,	856,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P1"                      ,	8,	8,	856,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P2"                      ,	16,	8,	856,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P3"                      ,	24,	8,	856,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	856,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	10,	857,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_11"              ,	10,	2,	857,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	12,	10,	857,	"R/W",	0,	1,	1023ull,	0},
+	{"RESERVED_22_23"              ,	22,	2,	857,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	24,	11,	857,	"RO",	0,	1,	1011ull,	0},
+	{"RESERVED_35_35"              ,	35,	1,	857,	"RAZ",	1,	1,	0,	0},
+	{"BUF_CNT"                     ,	36,	11,	857,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	857,	"RAZ",	1,	1,	0,	0},
+	{"DES_CNT"                     ,	48,	11,	857,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_59_63"              ,	59,	5,	857,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	32,	858,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	858,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	859,	"R/W1C",	0,	1,	0ull,	0},
 	{"RESERVED_32_63"              ,	32,	32,	859,	"RAZ",	1,	1,	0,	0},
-	{"IWORD"                       ,	0,	64,	860,	"RO",	1,	1,	0,	0},
-	{"P_DAT"                       ,	0,	64,	861,	"RO",	1,	1,	0,	0},
-	{"Q_DAT"                       ,	0,	64,	862,	"RO",	1,	1,	0,	0},
-	{"DAT"                         ,	0,	2,	863,	"RO",	1,	0,	0,	0ull},
-	{"NCB_INB"                     ,	2,	2,	863,	"RO",	1,	0,	0,	0ull},
-	{"NCB_OUB"                     ,	4,	1,	863,	"RO",	1,	0,	0,	0ull},
-	{"STA"                         ,	5,	1,	863,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	863,	"RAZ",	1,	1,	0,	0},
-	{"PTR"                         ,	0,	33,	864,	"R/W",	0,	1,	0ull,	0},
-	{"SIZE"                        ,	33,	13,	864,	"R/W",	0,	1,	0ull,	0},
-	{"POOL"                        ,	46,	3,	864,	"R/W",	0,	1,	0ull,	0},
-	{"DWB"                         ,	49,	9,	864,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_58_63"              ,	58,	6,	864,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESET"                       ,	0,	1,	865,	"RAZ",	0,	0,	0ull,	0ull},
-	{"STORE_LE"                    ,	1,	1,	865,	"R/W",	0,	0,	0ull,	0ull},
-	{"MAX_READ"                    ,	2,	4,	865,	"R/W",	0,	0,	8ull,	8ull},
-	{"RESERVED_6_63"               ,	6,	58,	865,	"RAZ",	0,	0,	0ull,	0ull},
-	{"STATE"                       ,	0,	5,	866,	"RO",	1,	1,	0,	0},
-	{"COMMIT"                      ,	5,	1,	866,	"RO",	1,	1,	0,	0},
-	{"OWORDPV"                     ,	6,	1,	866,	"RO",	1,	1,	0,	0},
-	{"OWORDQV"                     ,	7,	1,	866,	"RO",	1,	1,	0,	0},
-	{"IWIDX"                       ,	8,	6,	866,	"RO",	1,	1,	0,	0},
-	{"RESERVED_14_15"              ,	14,	2,	866,	"RO",	1,	1,	0,	0},
-	{"IRIDX"                       ,	16,	6,	866,	"RO",	1,	1,	0,	0},
-	{"RESERVED_22_31"              ,	22,	10,	866,	"RO",	1,	1,	0,	0},
-	{"LOOP"                        ,	32,	25,	866,	"RO",	1,	1,	0,	0},
-	{"RESERVED_57_63"              ,	57,	7,	866,	"RO",	1,	1,	0,	0},
-	{"CWORD"                       ,	0,	64,	867,	"RO",	1,	1,	0,	0},
-	{"PTR"                         ,	0,	40,	868,	"RO",	1,	1,	0,	0},
-	{"SIZE"                        ,	40,	16,	868,	"RO",	1,	1,	0,	0},
-	{"FLAGS"                       ,	56,	8,	868,	"RO",	1,	1,	0,	0},
-	{"INDEX"                       ,	0,	8,	869,	"RO",	1,	1,	0,	0},
-	{"SOD"                         ,	8,	1,	869,	"RO",	1,	1,	0,	0},
-	{"EOD"                         ,	9,	1,	869,	"RO",	1,	1,	0,	0},
-	{"WC"                          ,	10,	1,	869,	"RO",	1,	1,	0,	0},
-	{"P"                           ,	11,	1,	869,	"RO",	1,	1,	0,	0},
-	{"Q"                           ,	12,	1,	869,	"RO",	1,	1,	0,	0},
-	{"RESERVED_13_63"              ,	13,	51,	869,	"RAZ",	1,	1,	0,	0},
-	{"ASSERTS"                     ,	0,	15,	870,	"RO",	1,	1,	0,	0},
-	{"RESERVED_15_63"              ,	15,	49,	870,	"RAZ",	1,	1,	0,	0},
-	{"OWORDP"                      ,	0,	64,	871,	"RO",	1,	1,	0,	0},
-	{"OWORDQ"                      ,	0,	64,	872,	"RO",	1,	1,	0,	0},
-	{"RWORD"                       ,	0,	64,	873,	"RO",	1,	1,	0,	0},
-	{"N0CREDS"                     ,	0,	4,	874,	"RO",	0,	0,	8ull,	0ull},
-	{"N1CREDS"                     ,	4,	4,	874,	"RO",	0,	0,	8ull,	0ull},
-	{"POWCREDS"                    ,	8,	2,	874,	"RO",	0,	0,	2ull,	0ull},
-	{"RESERVED_10_11"              ,	10,	2,	874,	"RAZ",	1,	1,	0,	0},
-	{"FPACREDS"                    ,	12,	2,	874,	"RO",	0,	0,	1ull,	0ull},
-	{"WCCREDS"                     ,	14,	2,	874,	"RO",	0,	0,	0ull,	0ull},
-	{"NIWIDX0"                     ,	16,	4,	874,	"RO",	1,	1,	0,	0},
-	{"NIRIDX0"                     ,	20,	4,	874,	"RO",	1,	1,	0,	0},
-	{"NIWIDX1"                     ,	24,	4,	874,	"RO",	1,	1,	0,	0},
-	{"NIRIDX1"                     ,	28,	4,	874,	"RO",	1,	1,	0,	0},
-	{"NIRVAL6"                     ,	32,	5,	874,	"RO",	1,	1,	0,	0},
-	{"NIRARB6"                     ,	37,	1,	874,	"RO",	1,	1,	0,	0},
-	{"NIRQUE6"                     ,	38,	2,	874,	"RO",	1,	1,	0,	0},
-	{"NIROPC6"                     ,	40,	3,	874,	"RO",	1,	1,	0,	0},
-	{"NIRVAL7"                     ,	43,	5,	874,	"RO",	1,	1,	0,	0},
-	{"NIRQUE7"                     ,	48,	2,	874,	"RO",	1,	1,	0,	0},
-	{"NIROPC7"                     ,	50,	3,	874,	"RO",	1,	1,	0,	0},
-	{"RESERVED_53_63"              ,	53,	11,	874,	"RAZ",	1,	1,	0,	0},
-	{"PTR"                         ,	0,	40,	875,	"RO",	1,	1,	0,	0},
-	{"SIZE"                        ,	40,	16,	875,	"RO",	1,	1,	0,	0},
-	{"CNT"                         ,	56,	8,	875,	"RO",	1,	1,	0,	0},
-	{"CNT"                         ,	0,	15,	876,	"RO",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	860,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	860,	"RAZ",	1,	1,	0,	0},
+	{"WQ_INT"                      ,	0,	16,	861,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_DIS"                      ,	16,	16,	861,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	861,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	11,	862,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	862,	"RAZ",	1,	1,	0,	0},
+	{"DS_CNT"                      ,	12,	11,	862,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	862,	"RAZ",	1,	1,	0,	0},
+	{"TC_CNT"                      ,	24,	4,	862,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	862,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	863,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	863,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	863,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	863,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	863,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	10,	864,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_11"              ,	10,	2,	864,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	12,	10,	864,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_23"              ,	22,	2,	864,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	24,	4,	864,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	28,	1,	864,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	864,	"RAZ",	1,	1,	0,	0},
+	{"WS_PC"                       ,	0,	32,	865,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	865,	"RAZ",	1,	1,	0,	0},
+	{"IWORD"                       ,	0,	64,	866,	"RO",	1,	1,	0,	0},
+	{"P_DAT"                       ,	0,	64,	867,	"RO",	1,	1,	0,	0},
+	{"Q_DAT"                       ,	0,	64,	868,	"RO",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	2,	869,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	2,	2,	869,	"RO",	1,	0,	0,	0ull},
+	{"NCB_OUB"                     ,	4,	1,	869,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	5,	1,	869,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	869,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	870,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	33,	13,	870,	"R/W",	0,	1,	0ull,	0},
+	{"POOL"                        ,	46,	3,	870,	"R/W",	0,	1,	0ull,	0},
+	{"DWB"                         ,	49,	9,	870,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	870,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	871,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STORE_LE"                    ,	1,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_READ"                    ,	2,	4,	871,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_6_63"               ,	6,	58,	871,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	0,	5,	872,	"RO",	1,	1,	0,	0},
+	{"COMMIT"                      ,	5,	1,	872,	"RO",	1,	1,	0,	0},
+	{"OWORDPV"                     ,	6,	1,	872,	"RO",	1,	1,	0,	0},
+	{"OWORDQV"                     ,	7,	1,	872,	"RO",	1,	1,	0,	0},
+	{"IWIDX"                       ,	8,	6,	872,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	872,	"RO",	1,	1,	0,	0},
+	{"IRIDX"                       ,	16,	6,	872,	"RO",	1,	1,	0,	0},
+	{"RESERVED_22_31"              ,	22,	10,	872,	"RO",	1,	1,	0,	0},
+	{"LOOP"                        ,	32,	25,	872,	"RO",	1,	1,	0,	0},
+	{"RESERVED_57_63"              ,	57,	7,	872,	"RO",	1,	1,	0,	0},
+	{"CWORD"                       ,	0,	64,	873,	"RO",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	874,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	874,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	874,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	875,	"RO",	1,	1,	0,	0},
+	{"SOD"                         ,	8,	1,	875,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	9,	1,	875,	"RO",	1,	1,	0,	0},
+	{"WC"                          ,	10,	1,	875,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	11,	1,	875,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	12,	1,	875,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	875,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	15,	876,	"RO",	1,	1,	0,	0},
 	{"RESERVED_15_63"              ,	15,	49,	876,	"RAZ",	1,	1,	0,	0},
-	{"PTR"                         ,	0,	40,	877,	"RO",	1,	1,	0,	0},
-	{"SIZE"                        ,	40,	16,	877,	"RO",	1,	1,	0,	0},
-	{"FLAGS"                       ,	56,	8,	877,	"RO",	1,	1,	0,	0},
-	{"INDEX"                       ,	0,	8,	878,	"RO",	1,	1,	0,	0},
-	{"MUL"                         ,	8,	8,	878,	"RO",	1,	1,	0,	0},
-	{"P"                           ,	16,	1,	878,	"RO",	1,	1,	0,	0},
-	{"Q"                           ,	17,	1,	878,	"RO",	1,	1,	0,	0},
-	{"INI"                         ,	18,	1,	878,	"RO",	1,	1,	0,	0},
-	{"EOD"                         ,	19,	1,	878,	"RO",	1,	1,	0,	0},
-	{"RESERVED_20_63"              ,	20,	44,	878,	"RAZ",	1,	1,	0,	0},
-	{"DOORBELL"                    ,	0,	1,	879,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	879,	"RAZ",	1,	1,	0,	0},
-	{"DOORBELL"                    ,	0,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	880,	"RAZ",	1,	1,	0,	0},
-	{"COEFFS"                      ,	0,	8,	881,	"R/W",	0,	0,	29ull,	29ull},
-	{"RESERVED_8_63"               ,	8,	56,	881,	"RAZ",	0,	0,	0ull,	0ull},
-	{"INDEX"                       ,	0,	16,	882,	"R/W",	0,	0,	0ull,	0ull},
-	{"INC"                         ,	16,	16,	882,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	882,	"RAZ",	1,	1,	0,	0},
-	{"MEM"                         ,	0,	1,	883,	"RO",	0,	0,	0ull,	0ull},
-	{"RRC"                         ,	1,	1,	883,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	883,	"RAZ",	1,	1,	0,	0},
-	{"ENT_EN"                      ,	0,	1,	884,	"R/W",	0,	0,	0ull,	0ull},
-	{"RNG_EN"                      ,	1,	1,	884,	"R/W",	0,	0,	0ull,	0ull},
-	{"RNM_RST"                     ,	2,	1,	884,	"R/W",	0,	0,	0ull,	0ull},
-	{"RNG_RST"                     ,	3,	1,	884,	"R/W",	0,	0,	0ull,	0ull},
-	{"EXP_ENT"                     ,	4,	1,	884,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENT_SEL"                     ,	5,	4,	884,	"R/W",	0,	0,	0ull,	0ull},
-	{"EER_VAL"                     ,	9,	1,	884,	"RO",	0,	0,	0ull,	0ull},
-	{"EER_LCK"                     ,	10,	1,	884,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_11_63"              ,	11,	53,	884,	"RAZ",	1,	1,	0,	0},
-	{"DAT"                         ,	0,	64,	885,	"RO",	1,	1,	0,	0},
-	{"KEY"                         ,	0,	64,	886,	"WO",	0,	0,	0ull,	0ull},
-	{"NCB_CMD"                     ,	0,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"MSI"                         ,	1,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"DSI0_0"                      ,	2,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"DSI0_1"                      ,	3,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"DSI1_0"                      ,	4,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"DSI1_1"                      ,	5,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_8"                ,	6,	3,	887,	"RAZ",	1,	1,	0,	0},
-	{"P2N1_P1"                     ,	9,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"P2N1_P0"                     ,	10,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"P2N1_N"                      ,	11,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"P2N1_C1"                     ,	12,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"P2N1_C0"                     ,	13,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"P2N0_P1"                     ,	14,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"P2N0_P0"                     ,	15,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"P2N0_N"                      ,	16,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"P2N0_C1"                     ,	17,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"P2N0_C0"                     ,	18,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_19_24"              ,	19,	6,	887,	"RAZ",	1,	1,	0,	0},
-	{"CPL_P1"                      ,	25,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"CPL_P0"                      ,	26,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"N2P1_O"                      ,	27,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"N2P1_C"                      ,	28,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"N2P0_O"                      ,	29,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"N2P0_C"                      ,	30,	1,	887,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_31_63"              ,	31,	33,	887,	"RAZ",	1,	1,	0,	0},
-	{"WAIT_COM"                    ,	0,	1,	888,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_4"                ,	1,	4,	888,	"R/W",	0,	0,	0ull,	0ull},
-	{"PTLP_RO"                     ,	5,	1,	888,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_6"                ,	6,	1,	888,	"R/W",	0,	0,	0ull,	0ull},
-	{"CTLP_RO"                     ,	7,	1,	888,	"R/W",	0,	0,	0ull,	1ull},
-	{"INTA_MAP"                    ,	8,	2,	888,	"R/W",	0,	0,	0ull,	0ull},
-	{"INTB_MAP"                    ,	10,	2,	888,	"R/W",	0,	0,	1ull,	1ull},
-	{"INTC_MAP"                    ,	12,	2,	888,	"R/W",	0,	0,	2ull,	2ull},
-	{"INTD_MAP"                    ,	14,	2,	888,	"R/W",	0,	0,	3ull,	3ull},
-	{"WAITL_COM"                   ,	16,	1,	888,	"R/W",	0,	1,	0ull,	0},
-	{"DIS_PORT"                    ,	17,	1,	888,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"INTA"                        ,	18,	1,	888,	"RO",	0,	0,	1ull,	1ull},
-	{"INTB"                        ,	19,	1,	888,	"RO",	0,	0,	1ull,	1ull},
-	{"INTC"                        ,	20,	1,	888,	"RO",	0,	0,	1ull,	1ull},
-	{"INTD"                        ,	21,	1,	888,	"RO",	0,	0,	1ull,	1ull},
-	{"RESERVED_22_63"              ,	22,	42,	888,	"RAZ",	1,	1,	0,	0},
-	{"CHIP_REV"                    ,	0,	8,	889,	"RO",	1,	1,	0,	0},
-	{"P0_NTAGS"                    ,	8,	6,	889,	"R/W",	0,	0,	32ull,	32ull},
-	{"P1_NTAGS"                    ,	14,	6,	889,	"R/W",	0,	0,	32ull,	32ull},
-	{"RESERVED_20_63"              ,	20,	44,	889,	"RAZ",	1,	1,	0,	0},
-	{"P0_FCNT"                     ,	0,	6,	890,	"RO",	0,	1,	0ull,	0},
-	{"P0_UCNT"                     ,	6,	16,	890,	"RO",	0,	1,	0ull,	0},
-	{"P1_FCNT"                     ,	22,	6,	890,	"RO",	0,	1,	0ull,	0},
-	{"P1_UCNT"                     ,	28,	16,	890,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_44_63"              ,	44,	20,	890,	"RAZ",	1,	1,	0,	0},
-	{"DATA"                        ,	0,	17,	891,	"RO",	0,	1,	0ull,	0},
-	{"DSEL_EXT"                    ,	17,	1,	891,	"R/W",	0,	0,	1ull,	0ull},
-	{"RESERVED_18_63"              ,	18,	46,	891,	"RAZ",	1,	1,	0,	0},
-	{"DBG_SEL"                     ,	0,	32,	892,	"R/W",	0,	1,	0ull,	0},
-	{"ADBG_SEL"                    ,	32,	1,	892,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_33_63"              ,	33,	31,	892,	"RAZ",	1,	1,	0,	0},
-	{"CNT"                         ,	0,	32,	893,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	893,	"RAZ",	1,	1,	0,	0},
-	{"CNT"                         ,	0,	32,	894,	"R/W",	0,	1,	0ull,	0},
-	{"TIME"                        ,	32,	32,	894,	"R/W",	0,	1,	0ull,	0},
-	{"TIM"                         ,	0,	32,	895,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	895,	"RAZ",	1,	1,	0,	0},
-	{"RML_TO"                      ,	0,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_1_1"                ,	1,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
-	{"BAR0_TO"                     ,	2,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOB2BIG"                     ,	3,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
-	{"PCNT"                        ,	4,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
-	{"PTIME"                       ,	5,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_7"                ,	6,	2,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"M0_UP_B0"                    ,	8,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
-	{"M0_UP_WI"                    ,	9,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
-	{"M0_UN_B0"                    ,	10,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
-	{"M0_UN_WI"                    ,	11,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
-	{"M1_UP_B0"                    ,	12,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
-	{"M1_UP_WI"                    ,	13,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
-	{"M1_UN_B0"                    ,	14,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
-	{"M1_UN_WI"                    ,	15,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
-	{"MIO_INT0"                    ,	16,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"MIO_INT1"                    ,	17,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_18_31"              ,	18,	14,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"DMAFI"                       ,	32,	2,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"DCNT"                        ,	34,	2,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"DTIME"                       ,	36,	2,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_38_47"              ,	38,	10,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"PIDBOF"                      ,	48,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"PSLDBOF"                     ,	49,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"POUT_ERR"                    ,	50,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"PIN_BP"                      ,	51,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"PGL_ERR"                     ,	52,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"PDI_ERR"                     ,	53,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"POP_ERR"                     ,	54,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"PINS_ERR"                    ,	55,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"SPRT0_ERR"                   ,	56,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"SPRT1_ERR"                   ,	57,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_58_59"              ,	58,	2,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"ILL_PAD"                     ,	60,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"RML_TO"                      ,	0,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_1_1"                ,	1,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"BAR0_TO"                     ,	2,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOB2BIG"                     ,	3,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"PCNT"                        ,	4,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"PTIME"                       ,	5,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_7"                ,	6,	2,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"M0_UP_B0"                    ,	8,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"M0_UP_WI"                    ,	9,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"M0_UN_B0"                    ,	10,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"M0_UN_WI"                    ,	11,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"M1_UP_B0"                    ,	12,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"M1_UP_WI"                    ,	13,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"M1_UN_B0"                    ,	14,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"M1_UN_WI"                    ,	15,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"MIO_INT0"                    ,	16,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"MIO_INT1"                    ,	17,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"MAC0_INT"                    ,	18,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"MAC1_INT"                    ,	19,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_20_31"              ,	20,	12,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"DMAFI"                       ,	32,	2,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"DCNT"                        ,	34,	2,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"DTIME"                       ,	36,	2,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_38_47"              ,	38,	10,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"PIDBOF"                      ,	48,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"PSLDBOF"                     ,	49,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"POUT_ERR"                    ,	50,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"PIN_BP"                      ,	51,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"PGL_ERR"                     ,	52,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"PDI_ERR"                     ,	53,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"POP_ERR"                     ,	54,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"PINS_ERR"                    ,	55,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"SPRT0_ERR"                   ,	56,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"SPRT1_ERR"                   ,	57,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_58_59"              ,	58,	2,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"ILL_PAD"                     ,	60,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"RML_TO"                      ,	0,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_1"                ,	1,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"BAR0_TO"                     ,	2,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"IOB2BIG"                     ,	3,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PCNT"                        ,	4,	1,	898,	"RO",	0,	0,	0ull,	0ull},
-	{"PTIME"                       ,	5,	1,	898,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"M0_UP_B0"                    ,	8,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"M0_UP_WI"                    ,	9,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"M0_UN_B0"                    ,	10,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"M0_UN_WI"                    ,	11,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"M1_UP_B0"                    ,	12,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"M1_UP_WI"                    ,	13,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"M1_UN_B0"                    ,	14,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"M1_UN_WI"                    ,	15,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"MIO_INT0"                    ,	16,	1,	898,	"RO",	0,	0,	0ull,	0ull},
-	{"MIO_INT1"                    ,	17,	1,	898,	"RO",	0,	0,	0ull,	0ull},
-	{"MAC0_INT"                    ,	18,	1,	898,	"RO",	0,	0,	0ull,	0ull},
-	{"MAC1_INT"                    ,	19,	1,	898,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_20_31"              ,	20,	12,	898,	"RAZ",	1,	1,	0,	0},
-	{"DMAFI"                       ,	32,	2,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"DCNT"                        ,	34,	2,	898,	"RO",	0,	0,	0ull,	0ull},
-	{"DTIME"                       ,	36,	2,	898,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_38_47"              ,	38,	10,	898,	"RAZ",	1,	1,	0,	0},
-	{"PIDBOF"                      ,	48,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PSLDBOF"                     ,	49,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"POUT_ERR"                    ,	50,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PIN_BP"                      ,	51,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PGL_ERR"                     ,	52,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PDI_ERR"                     ,	53,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"POP_ERR"                     ,	54,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PINS_ERR"                    ,	55,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"SPRT0_ERR"                   ,	56,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"SPRT1_ERR"                   ,	57,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_58_59"              ,	58,	2,	898,	"RAZ",	1,	1,	0,	0},
-	{"ILL_PAD"                     ,	60,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	898,	"RAZ",	1,	1,	0,	0},
-	{"DATA"                        ,	0,	64,	899,	"RO",	0,	1,	0ull,	0},
-	{"DATA"                        ,	0,	64,	900,	"RO",	0,	1,	0ull,	0},
-	{"P0_PCNT"                     ,	0,	8,	901,	"R/W",	0,	0,	128ull,	128ull},
-	{"P0_NCNT"                     ,	8,	8,	901,	"R/W",	0,	0,	16ull,	16ull},
-	{"P0_CCNT"                     ,	16,	8,	901,	"R/W",	0,	0,	128ull,	128ull},
-	{"P1_PCNT"                     ,	24,	8,	901,	"R/W",	0,	0,	128ull,	128ull},
-	{"P1_NCNT"                     ,	32,	8,	901,	"R/W",	0,	0,	16ull,	16ull},
-	{"P1_CCNT"                     ,	40,	8,	901,	"R/W",	0,	0,	128ull,	128ull},
-	{"RESERVED_48_63"              ,	48,	16,	901,	"RAZ",	1,	1,	0,	0},
-	{"TIMER"                       ,	0,	10,	902,	"R/W",	0,	0,	0ull,	50ull},
-	{"MAX_WORD"                    ,	10,	4,	902,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_14_63"              ,	14,	50,	902,	"RAZ",	1,	1,	0,	0},
-	{"BA"                          ,	0,	30,	903,	"R/W",	0,	1,	0ull,	0},
-	{"RTYPE"                       ,	30,	2,	903,	"R/W",	0,	1,	0ull,	0},
-	{"WTYPE"                       ,	32,	2,	903,	"R/W",	0,	1,	0ull,	0},
-	{"ESW"                         ,	34,	2,	903,	"R/W",	0,	1,	0ull,	0},
-	{"ESR"                         ,	36,	2,	903,	"R/W",	0,	1,	0ull,	0},
-	{"NMERGE"                      ,	38,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
-	{"PORT"                        ,	39,	3,	903,	"R/W",	0,	1,	0ull,	0},
-	{"ZERO"                        ,	42,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_43_63"              ,	43,	21,	903,	"RAZ",	1,	1,	0,	0},
-	{"ENB"                         ,	0,	64,	904,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
-	{"ENB"                         ,	0,	64,	905,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
-	{"ENB"                         ,	0,	64,	906,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
-	{"ENB"                         ,	0,	64,	907,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
-	{"INTR"                        ,	0,	64,	908,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"INTR"                        ,	0,	64,	909,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"INTR"                        ,	0,	64,	910,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"INTR"                        ,	0,	64,	911,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"MSI_INT"                     ,	0,	8,	912,	"R/W",	0,	1,	0ull,	0},
-	{"RD_INT"                      ,	8,	8,	912,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_16_63"              ,	16,	48,	912,	"RAZ",	1,	1,	0,	0},
-	{"CLR"                         ,	0,	64,	913,	"R/W",	0,	0,	0ull,	0ull},
-	{"CLR"                         ,	0,	64,	914,	"R/W",	0,	0,	0ull,	0ull},
-	{"CLR"                         ,	0,	64,	915,	"R/W",	0,	0,	0ull,	0ull},
-	{"CLR"                         ,	0,	64,	916,	"R/W",	0,	0,	0ull,	0ull},
-	{"SET"                         ,	0,	64,	917,	"R/W",	0,	0,	0ull,	0ull},
-	{"SET"                         ,	0,	64,	918,	"R/W",	0,	0,	0ull,	0ull},
-	{"SET"                         ,	0,	64,	919,	"R/W",	0,	0,	0ull,	0ull},
-	{"SET"                         ,	0,	64,	920,	"R/W",	0,	0,	0ull,	0ull},
-	{"MSI_INT"                     ,	0,	8,	921,	"R/W",	0,	1,	0ull,	0},
-	{"CIU_INT"                     ,	8,	8,	921,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_16_63"              ,	16,	48,	921,	"RAZ",	1,	1,	0,	0},
-	{"INTR"                        ,	0,	8,	922,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_8_63"               ,	8,	56,	922,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_7"                ,	0,	8,	923,	"RAZ",	1,	1,	0,	0},
-	{"INTR"                        ,	8,	8,	923,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_16_63"              ,	16,	48,	923,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_15"               ,	0,	16,	924,	"RAZ",	1,	1,	0,	0},
-	{"INTR"                        ,	16,	8,	924,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_24_63"              ,	24,	40,	924,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_23"               ,	0,	24,	925,	"RAZ",	1,	1,	0,	0},
-	{"INTR"                        ,	24,	8,	925,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	925,	"RAZ",	1,	1,	0,	0},
-	{"CNT"                         ,	0,	32,	926,	"R/W",	0,	0,	0ull,	0ull},
-	{"TIMER"                       ,	32,	22,	926,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_54_63"              ,	54,	10,	926,	"RO",	1,	1,	0,	0},
-	{"CNT"                         ,	0,	32,	927,	"R/W",	0,	0,	0ull,	0ull},
-	{"WMARK"                       ,	32,	32,	927,	"R/W",	0,	1,	4294967295ull,	0},
-	{"RESERVED_0_2"                ,	0,	3,	928,	"RAZ",	1,	1,	0,	0},
-	{"ADDR"                        ,	3,	61,	928,	"R/W",	0,	1,	0ull,	0},
-	{"DBELL"                       ,	0,	32,	929,	"R/W",	0,	0,	0ull,	0ull},
-	{"AOFF"                        ,	32,	32,	929,	"RO",	0,	1,	0ull,	0},
-	{"RSIZE"                       ,	0,	32,	930,	"R/W",	0,	1,	0ull,	0},
-	{"FCNT"                        ,	32,	5,	930,	"RO",	0,	1,	0ull,	0},
-	{"WRP"                         ,	37,	9,	930,	"RO",	0,	1,	0ull,	0},
-	{"RRP"                         ,	46,	9,	930,	"RO",	0,	1,	0ull,	0},
-	{"MAX"                         ,	55,	9,	930,	"RO",	0,	1,	16ull,	0},
-	{"NTAG"                        ,	0,	1,	931,	"R/W",	0,	1,	0ull,	0},
-	{"NTT"                         ,	1,	1,	931,	"R/W",	0,	1,	0ull,	0},
-	{"NGRP"                        ,	2,	1,	931,	"R/W",	0,	1,	0ull,	0},
-	{"NQOS"                        ,	3,	1,	931,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_4_5"                ,	4,	2,	931,	"R/W",	0,	1,	0ull,	0},
-	{"SKP_LEN"                     ,	6,	7,	931,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_13_13"              ,	13,	1,	931,	"R/W",	0,	1,	0ull,	0},
-	{"PAR_MODE"                    ,	14,	2,	931,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_16_20"              ,	16,	5,	931,	"R/W",	0,	1,	0ull,	0},
-	{"USE_IHDR"                    ,	21,	1,	931,	"R/W",	0,	1,	0ull,	0},
-	{"RNTAG"                       ,	22,	1,	931,	"R/W",	0,	1,	0ull,	0},
-	{"RNTT"                        ,	23,	1,	931,	"R/W",	0,	1,	0ull,	0},
-	{"RNGRP"                       ,	24,	1,	931,	"R/W",	0,	1,	0ull,	0},
-	{"RNQOS"                       ,	25,	1,	931,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_26_27"              ,	26,	2,	931,	"R/W",	0,	1,	0ull,	0},
-	{"RSKP_LEN"                    ,	28,	7,	931,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_35_35"              ,	35,	1,	931,	"RAZ",	0,	1,	0ull,	0},
-	{"RPARMODE"                    ,	36,	2,	931,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_38_42"              ,	38,	5,	931,	"RAZ",	0,	1,	0ull,	0},
-	{"PBP"                         ,	43,	1,	931,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_44_63"              ,	44,	20,	931,	"RAZ",	1,	1,	0,	0},
-	{"BSIZE"                       ,	0,	16,	932,	"R/W",	0,	1,	0ull,	0},
-	{"ISIZE"                       ,	16,	7,	932,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_23_63"              ,	23,	41,	932,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_3"                ,	0,	4,	933,	"RAZ",	1,	1,	0,	0},
-	{"ADDR"                        ,	4,	60,	933,	"R/W",	0,	1,	0ull,	0},
-	{"DBELL"                       ,	0,	32,	934,	"R/W",	0,	0,	0ull,	0ull},
-	{"AOFF"                        ,	32,	32,	934,	"RO",	0,	1,	0ull,	0},
-	{"RSIZE"                       ,	0,	32,	935,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	935,	"RO",	0,	1,	0ull,	0},
-	{"PORT"                        ,	0,	32,	936,	"R/W1C",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	936,	"RAZ",	1,	1,	0,	0},
-	{"PORT"                        ,	0,	32,	937,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	937,	"RAZ",	1,	1,	0,	0},
-	{"PKT_BP"                      ,	0,	4,	938,	"R/W",	0,	0,	15ull,	15ull},
-	{"RING_EN"                     ,	4,	1,	938,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_63"               ,	5,	59,	938,	"RAZ",	1,	1,	0,	0},
-	{"ES"                          ,	0,	64,	939,	"R/W",	0,	1,	0ull,	0},
-	{"NSR"                         ,	0,	32,	940,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	940,	"RAZ",	1,	1,	0,	0},
-	{"ROR"                         ,	0,	32,	941,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	941,	"RAZ",	1,	1,	0,	0},
-	{"DPTR"                        ,	0,	32,	942,	"R/W",	0,	0,	0ull,	4294967295ull},
+	{"OWORDP"                      ,	0,	64,	877,	"RO",	1,	1,	0,	0},
+	{"OWORDQ"                      ,	0,	64,	878,	"RO",	1,	1,	0,	0},
+	{"RWORD"                       ,	0,	64,	879,	"RO",	1,	1,	0,	0},
+	{"N0CREDS"                     ,	0,	4,	880,	"RO",	0,	0,	8ull,	0ull},
+	{"N1CREDS"                     ,	4,	4,	880,	"RO",	0,	0,	8ull,	0ull},
+	{"POWCREDS"                    ,	8,	2,	880,	"RO",	0,	0,	2ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	880,	"RAZ",	1,	1,	0,	0},
+	{"FPACREDS"                    ,	12,	2,	880,	"RO",	0,	0,	1ull,	0ull},
+	{"WCCREDS"                     ,	14,	2,	880,	"RO",	0,	0,	0ull,	0ull},
+	{"NIWIDX0"                     ,	16,	4,	880,	"RO",	1,	1,	0,	0},
+	{"NIRIDX0"                     ,	20,	4,	880,	"RO",	1,	1,	0,	0},
+	{"NIWIDX1"                     ,	24,	4,	880,	"RO",	1,	1,	0,	0},
+	{"NIRIDX1"                     ,	28,	4,	880,	"RO",	1,	1,	0,	0},
+	{"NIRVAL6"                     ,	32,	5,	880,	"RO",	1,	1,	0,	0},
+	{"NIRARB6"                     ,	37,	1,	880,	"RO",	1,	1,	0,	0},
+	{"NIRQUE6"                     ,	38,	2,	880,	"RO",	1,	1,	0,	0},
+	{"NIROPC6"                     ,	40,	3,	880,	"RO",	1,	1,	0,	0},
+	{"NIRVAL7"                     ,	43,	5,	880,	"RO",	1,	1,	0,	0},
+	{"NIRQUE7"                     ,	48,	2,	880,	"RO",	1,	1,	0,	0},
+	{"NIROPC7"                     ,	50,	3,	880,	"RO",	1,	1,	0,	0},
+	{"RESERVED_53_63"              ,	53,	11,	880,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	881,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	881,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	56,	8,	881,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	15,	882,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	882,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	883,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	883,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	883,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	884,	"RO",	1,	1,	0,	0},
+	{"MUL"                         ,	8,	8,	884,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	16,	1,	884,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	17,	1,	884,	"RO",	1,	1,	0,	0},
+	{"INI"                         ,	18,	1,	884,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	19,	1,	884,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_63"              ,	20,	44,	884,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	885,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	885,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	886,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	886,	"RAZ",	1,	1,	0,	0},
+	{"COEFFS"                      ,	0,	8,	887,	"R/W",	0,	0,	29ull,	29ull},
+	{"RESERVED_8_63"               ,	8,	56,	887,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	0,	16,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	16,	16,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	888,	"RAZ",	1,	1,	0,	0},
+	{"MEM"                         ,	0,	1,	889,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	889,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	889,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXP_ENT"                     ,	4,	1,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENT_SEL"                     ,	5,	4,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"EER_VAL"                     ,	9,	1,	890,	"RO",	0,	0,	0ull,	0ull},
+	{"EER_LCK"                     ,	10,	1,	890,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	890,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	891,	"RO",	1,	1,	0,	0},
+	{"KEY"                         ,	0,	64,	892,	"WO",	0,	0,	0ull,	0ull},
+	{"NCB_CMD"                     ,	0,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"MSI"                         ,	1,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI0_0"                      ,	2,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI0_1"                      ,	3,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI1_0"                      ,	4,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI1_1"                      ,	5,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_8"                ,	6,	3,	893,	"RAZ",	1,	1,	0,	0},
+	{"P2N1_P1"                     ,	9,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_P0"                     ,	10,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_N"                      ,	11,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C1"                     ,	12,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C0"                     ,	13,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P1"                     ,	14,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P0"                     ,	15,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_N"                      ,	16,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C1"                     ,	17,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C0"                     ,	18,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_24"              ,	19,	6,	893,	"RAZ",	1,	1,	0,	0},
+	{"CPL_P1"                      ,	25,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"CPL_P0"                      ,	26,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_O"                      ,	27,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_C"                      ,	28,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_O"                      ,	29,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_C"                      ,	30,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	893,	"RAZ",	1,	1,	0,	0},
+	{"WAIT_COM"                    ,	0,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_4"                ,	1,	4,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTLP_RO"                     ,	5,	1,	894,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTLP_RO"                     ,	7,	1,	894,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTA_MAP"                    ,	8,	2,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTB_MAP"                    ,	10,	2,	894,	"R/W",	0,	0,	1ull,	1ull},
+	{"INTC_MAP"                    ,	12,	2,	894,	"R/W",	0,	0,	2ull,	2ull},
+	{"INTD_MAP"                    ,	14,	2,	894,	"R/W",	0,	0,	3ull,	3ull},
+	{"WAITL_COM"                   ,	16,	1,	894,	"R/W",	0,	1,	0ull,	0},
+	{"DIS_PORT"                    ,	17,	1,	894,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTA"                        ,	18,	1,	894,	"RO",	0,	0,	1ull,	1ull},
+	{"INTB"                        ,	19,	1,	894,	"RO",	0,	0,	1ull,	1ull},
+	{"INTC"                        ,	20,	1,	894,	"RO",	0,	0,	1ull,	1ull},
+	{"INTD"                        ,	21,	1,	894,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	894,	"RAZ",	1,	1,	0,	0},
+	{"CHIP_REV"                    ,	0,	8,	895,	"RO",	1,	1,	0,	0},
+	{"P0_NTAGS"                    ,	8,	6,	895,	"R/W",	0,	0,	32ull,	32ull},
+	{"P1_NTAGS"                    ,	14,	6,	895,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_63"              ,	20,	44,	895,	"RAZ",	1,	1,	0,	0},
+	{"P0_FCNT"                     ,	0,	6,	896,	"RO",	0,	1,	0ull,	0},
+	{"P0_UCNT"                     ,	6,	16,	896,	"RO",	0,	1,	0ull,	0},
+	{"P1_FCNT"                     ,	22,	6,	896,	"RO",	0,	1,	0ull,	0},
+	{"P1_UCNT"                     ,	28,	16,	896,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	896,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	897,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	897,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	897,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	32,	898,	"R/W",	0,	1,	0ull,	0},
+	{"ADBG_SEL"                    ,	32,	1,	898,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	898,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	899,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	899,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	900,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	32,	900,	"R/W",	0,	1,	0ull,	0},
+	{"TIM"                         ,	0,	32,	901,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	901,	"RAZ",	1,	1,	0,	0},
+	{"RML_TO"                      ,	0,	1,	902,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	902,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	902,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	902,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	4,	1,	902,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	5,	1,	902,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	902,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UP_WI"                    ,	9,	1,	902,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_B0"                    ,	10,	1,	902,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_WI"                    ,	11,	1,	902,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_B0"                    ,	12,	1,	902,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_WI"                    ,	13,	1,	902,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_B0"                    ,	14,	1,	902,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_WI"                    ,	15,	1,	902,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT0"                    ,	16,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO_INT1"                    ,	17,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAFI"                       ,	32,	2,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	48,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_59"              ,	58,	2,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML_TO"                      ,	0,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	4,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	5,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UP_WI"                    ,	9,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_B0"                    ,	10,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_WI"                    ,	11,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_B0"                    ,	12,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_WI"                    ,	13,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_B0"                    ,	14,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_WI"                    ,	15,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT0"                    ,	16,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT1"                    ,	17,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC0_INT"                    ,	18,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC1_INT"                    ,	19,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_31"              ,	20,	12,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAFI"                       ,	32,	2,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	48,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_59"              ,	58,	2,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML_TO"                      ,	0,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAR0_TO"                     ,	2,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB2BIG"                     ,	3,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT"                        ,	4,	1,	904,	"RO",	0,	0,	0ull,	0ull},
+	{"PTIME"                       ,	5,	1,	904,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UP_WI"                    ,	9,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UN_B0"                    ,	10,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UN_WI"                    ,	11,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UP_B0"                    ,	12,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UP_WI"                    ,	13,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UN_B0"                    ,	14,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UN_WI"                    ,	15,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO_INT0"                    ,	16,	1,	904,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO_INT1"                    ,	17,	1,	904,	"RO",	0,	0,	0ull,	0ull},
+	{"MAC0_INT"                    ,	18,	1,	904,	"RO",	0,	0,	0ull,	0ull},
+	{"MAC1_INT"                    ,	19,	1,	904,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	904,	"RAZ",	1,	1,	0,	0},
+	{"DMAFI"                       ,	32,	2,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	904,	"RO",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	904,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	904,	"RAZ",	1,	1,	0,	0},
+	{"PIDBOF"                      ,	48,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_59"              ,	58,	2,	904,	"RAZ",	1,	1,	0,	0},
+	{"ILL_PAD"                     ,	60,	1,	904,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	904,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	905,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	906,	"RO",	0,	1,	0ull,	0},
+	{"P0_PCNT"                     ,	0,	8,	907,	"R/W",	0,	0,	128ull,	128ull},
+	{"P0_NCNT"                     ,	8,	8,	907,	"R/W",	0,	0,	16ull,	16ull},
+	{"P0_CCNT"                     ,	16,	8,	907,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_PCNT"                     ,	24,	8,	907,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_NCNT"                     ,	32,	8,	907,	"R/W",	0,	0,	16ull,	16ull},
+	{"P1_CCNT"                     ,	40,	8,	907,	"R/W",	0,	0,	128ull,	128ull},
+	{"RESERVED_48_63"              ,	48,	16,	907,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	10,	908,	"R/W",	0,	0,	0ull,	50ull},
+	{"MAX_WORD"                    ,	10,	4,	908,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	908,	"RAZ",	1,	1,	0,	0},
+	{"BA"                          ,	0,	30,	909,	"R/W",	0,	1,	0ull,	0},
+	{"RTYPE"                       ,	30,	2,	909,	"R/W",	0,	1,	0ull,	0},
+	{"WTYPE"                       ,	32,	2,	909,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	34,	2,	909,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	36,	2,	909,	"R/W",	0,	1,	0ull,	0},
+	{"NMERGE"                      ,	38,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORT"                        ,	39,	3,	909,	"R/W",	0,	1,	0ull,	0},
+	{"ZERO"                        ,	42,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	909,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	64,	910,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	911,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	912,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	913,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"INTR"                        ,	0,	64,	914,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	915,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	916,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	917,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	918,	"R/W",	0,	1,	0ull,	0},
+	{"RD_INT"                      ,	8,	8,	918,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	918,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	64,	919,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	921,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	922,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	924,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	925,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	926,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	927,	"R/W",	0,	1,	0ull,	0},
+	{"CIU_INT"                     ,	8,	8,	927,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	927,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	8,	928,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	928,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	929,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	8,	8,	929,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	929,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	930,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	16,	8,	930,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	930,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	931,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	24,	8,	931,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	931,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	932,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	32,	22,	932,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	932,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	933,	"R/W",	0,	0,	0ull,	0ull},
+	{"WMARK"                       ,	32,	32,	933,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	934,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	61,	934,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	935,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	936,	"R/W",	0,	1,	0ull,	0},
+	{"FCNT"                        ,	32,	5,	936,	"RO",	0,	1,	0ull,	0},
+	{"WRP"                         ,	37,	9,	936,	"RO",	0,	1,	0ull,	0},
+	{"RRP"                         ,	46,	9,	936,	"RO",	0,	1,	0ull,	0},
+	{"MAX"                         ,	55,	9,	936,	"RO",	0,	1,	16ull,	0},
+	{"NTAG"                        ,	0,	1,	937,	"R/W",	0,	1,	0ull,	0},
+	{"NTT"                         ,	1,	1,	937,	"R/W",	0,	1,	0ull,	0},
+	{"NGRP"                        ,	2,	1,	937,	"R/W",	0,	1,	0ull,	0},
+	{"NQOS"                        ,	3,	1,	937,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	937,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	937,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_13"              ,	13,	1,	937,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	937,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_20"              ,	16,	5,	937,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	937,	"R/W",	0,	1,	0ull,	0},
+	{"RNTAG"                       ,	22,	1,	937,	"R/W",	0,	1,	0ull,	0},
+	{"RNTT"                        ,	23,	1,	937,	"R/W",	0,	1,	0ull,	0},
+	{"RNGRP"                       ,	24,	1,	937,	"R/W",	0,	1,	0ull,	0},
+	{"RNQOS"                       ,	25,	1,	937,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_27"              ,	26,	2,	937,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	937,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_35_35"              ,	35,	1,	937,	"RAZ",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	937,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_42"              ,	38,	5,	937,	"RAZ",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	937,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	937,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	16,	938,	"R/W",	0,	1,	0ull,	0},
+	{"ISIZE"                       ,	16,	7,	938,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	938,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	939,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	4,	60,	939,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	940,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	940,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	941,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	941,	"RO",	0,	1,	0ull,	0},
+	{"PORT"                        ,	0,	32,	942,	"R/W1C",	0,	1,	0ull,	0},
 	{"RESERVED_32_63"              ,	32,	32,	942,	"RAZ",	1,	1,	0,	0},
-	{"BP"                          ,	0,	32,	943,	"RO",	0,	1,	0ull,	0},
+	{"PORT"                        ,	0,	32,	943,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_32_63"              ,	32,	32,	943,	"RAZ",	1,	1,	0,	0},
-	{"CNT"                         ,	0,	32,	944,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	944,	"RO",	0,	1,	0ull,	0},
-	{"RD_CNT"                      ,	0,	32,	945,	"RO",	0,	1,	0ull,	0},
-	{"WR_CNT"                      ,	32,	32,	945,	"RO",	0,	1,	0ull,	0},
-	{"PP"                          ,	0,	64,	946,	"R/W",	0,	1,	0ull,	0},
-	{"ROR"                         ,	0,	1,	947,	"R/W",	0,	1,	0ull,	0},
-	{"ESR"                         ,	1,	2,	947,	"R/W",	0,	1,	0ull,	0},
-	{"NSR"                         ,	3,	1,	947,	"R/W",	0,	1,	0ull,	0},
-	{"USE_CSR"                     ,	4,	1,	947,	"R/W",	0,	0,	0ull,	1ull},
-	{"D_ROR"                       ,	5,	1,	947,	"R/W",	0,	1,	0ull,	0},
-	{"D_ESR"                       ,	6,	2,	947,	"R/W",	0,	1,	0ull,	0},
-	{"D_NSR"                       ,	8,	1,	947,	"R/W",	0,	1,	0ull,	0},
-	{"PBP_DHI"                     ,	9,	13,	947,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKT_RR"                      ,	22,	1,	947,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_23_63"              ,	23,	41,	947,	"RAZ",	1,	1,	0,	0},
-	{"ENB"                         ,	0,	32,	948,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_BP"                      ,	0,	4,	944,	"R/W",	0,	0,	15ull,	15ull},
+	{"RING_EN"                     ,	4,	1,	944,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	944,	"RAZ",	1,	1,	0,	0},
+	{"ES"                          ,	0,	64,	945,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	946,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	946,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	947,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	947,	"RAZ",	1,	1,	0,	0},
+	{"DPTR"                        ,	0,	32,	948,	"R/W",	0,	0,	0ull,	4294967295ull},
 	{"RESERVED_32_63"              ,	32,	32,	948,	"RAZ",	1,	1,	0,	0},
-	{"RDSIZE"                      ,	0,	64,	949,	"R/W",	0,	1,	0ull,	0},
-	{"IS_64B"                      ,	0,	32,	950,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	950,	"RAZ",	1,	1,	0,	0},
-	{"CNT"                         ,	0,	32,	951,	"R/W",	0,	1,	0ull,	0},
-	{"TIME"                        ,	32,	22,	951,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_54_63"              ,	54,	10,	951,	"RAZ",	1,	1,	0,	0},
-	{"IPTR"                        ,	0,	32,	952,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	952,	"RAZ",	1,	1,	0,	0},
-	{"BMODE"                       ,	0,	32,	953,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	953,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	32,	949,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	949,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	950,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	950,	"RO",	0,	1,	0ull,	0},
+	{"RD_CNT"                      ,	0,	32,	951,	"RO",	0,	1,	0ull,	0},
+	{"WR_CNT"                      ,	32,	32,	951,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	0,	64,	952,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	0,	1,	953,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	1,	2,	953,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	3,	1,	953,	"R/W",	0,	1,	0ull,	0},
+	{"USE_CSR"                     ,	4,	1,	953,	"R/W",	0,	0,	0ull,	1ull},
+	{"D_ROR"                       ,	5,	1,	953,	"R/W",	0,	1,	0ull,	0},
+	{"D_ESR"                       ,	6,	2,	953,	"R/W",	0,	1,	0ull,	0},
+	{"D_NSR"                       ,	8,	1,	953,	"R/W",	0,	1,	0ull,	0},
+	{"PBP_DHI"                     ,	9,	13,	953,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_RR"                      ,	22,	1,	953,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_23_63"              ,	23,	41,	953,	"RAZ",	1,	1,	0,	0},
 	{"ENB"                         ,	0,	32,	954,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_32_63"              ,	32,	32,	954,	"RAZ",	1,	1,	0,	0},
-	{"WMARK"                       ,	0,	32,	955,	"R/W",	0,	0,	0ull,	14ull},
-	{"RESERVED_32_63"              ,	32,	32,	955,	"RAZ",	1,	1,	0,	0},
-	{"PP"                          ,	0,	64,	956,	"R/W",	0,	1,	0ull,	0},
-	{"OUT_RST"                     ,	0,	32,	957,	"RO",	0,	1,	0ull,	0},
-	{"IN_RST"                      ,	32,	32,	957,	"RO",	0,	1,	0ull,	0},
-	{"ES"                          ,	0,	64,	958,	"R/W",	0,	1,	0ull,	0},
-	{"NSR"                         ,	0,	32,	959,	"R/W",	0,	1,	0ull,	0},
+	{"RDSIZE"                      ,	0,	64,	955,	"R/W",	0,	1,	0ull,	0},
+	{"IS_64B"                      ,	0,	32,	956,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	956,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	957,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	22,	957,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_54_63"              ,	54,	10,	957,	"RAZ",	1,	1,	0,	0},
+	{"IPTR"                        ,	0,	32,	958,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	958,	"RAZ",	1,	1,	0,	0},
+	{"BMODE"                       ,	0,	32,	959,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_32_63"              ,	32,	32,	959,	"RAZ",	1,	1,	0,	0},
-	{"ROR"                         ,	0,	32,	960,	"R/W",	0,	1,	0ull,	0},
+	{"ENB"                         ,	0,	32,	960,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_32_63"              ,	32,	32,	960,	"RAZ",	1,	1,	0,	0},
-	{"PORT"                        ,	0,	32,	961,	"R/W1C",	0,	1,	0ull,	0},
+	{"WMARK"                       ,	0,	32,	961,	"R/W",	0,	0,	0ull,	14ull},
 	{"RESERVED_32_63"              ,	32,	32,	961,	"RAZ",	1,	1,	0,	0},
-	{"PORT"                        ,	0,	32,	962,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	962,	"RAZ",	1,	1,	0,	0},
-	{"MRRS"                        ,	0,	3,	963,	"R/W",	0,	0,	2ull,	2ull},
-	{"BAR0_D"                      ,	3,	1,	963,	"R/W",	0,	0,	0ull,	0ull},
-	{"WIND_D"                      ,	4,	1,	963,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_63"               ,	5,	59,	963,	"RAZ",	1,	1,	0,	0},
-	{"DATA"                        ,	0,	64,	964,	"R/W",	0,	1,	0ull,	0},
-	{"DATA"                        ,	0,	64,	965,	"R/W",	0,	1,	0ull,	0},
-	{"CSR"                         ,	0,	39,	966,	"RO",	0,	1,	1ull,	0},
-	{"ARB"                         ,	39,	1,	966,	"RO",	0,	1,	0ull,	0},
-	{"CPL0"                        ,	40,	12,	966,	"RO",	0,	1,	1ull,	0},
-	{"CPL1"                        ,	52,	12,	966,	"RO",	0,	1,	1ull,	0},
-	{"NND"                         ,	0,	8,	967,	"RO",	0,	1,	1ull,	0},
-	{"NNP0"                        ,	8,	8,	967,	"RO",	0,	1,	1ull,	0},
-	{"CSM0"                        ,	16,	15,	967,	"RO",	0,	1,	1ull,	0},
-	{"CSM1"                        ,	31,	15,	967,	"RO",	0,	1,	1ull,	0},
-	{"RAC"                         ,	46,	1,	967,	"RO",	0,	1,	1ull,	0},
-	{"RESERVED_47_47"              ,	47,	1,	967,	"RAZ",	1,	1,	0,	0},
-	{"NNP1"                        ,	48,	8,	967,	"RO",	0,	1,	1ull,	0},
-	{"RESERVED_56_63"              ,	56,	8,	967,	"RAZ",	1,	1,	0,	0},
-	{"NSM0"                        ,	0,	13,	968,	"RO",	0,	1,	1ull,	0},
-	{"NSM1"                        ,	13,	13,	968,	"RO",	0,	1,	1ull,	0},
-	{"PSM0"                        ,	26,	15,	968,	"RO",	0,	1,	1ull,	0},
-	{"PSM1"                        ,	41,	15,	968,	"RO",	0,	1,	1ull,	0},
-	{"RESERVED_56_63"              ,	56,	8,	968,	"RAZ",	1,	1,	0,	0},
-	{"RD_ADDR"                     ,	0,	48,	969,	"R/W",	0,	1,	0ull,	0},
-	{"IOBIT"                       ,	48,	1,	969,	"R/W",	0,	0,	0ull,	0ull},
-	{"LD_CMD"                      ,	49,	2,	969,	"R/W",	0,	1,	3ull,	0},
-	{"RESERVED_51_63"              ,	51,	13,	969,	"RAZ",	1,	1,	0,	0},
-	{"RD_DATA"                     ,	0,	64,	970,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_0_2"                ,	0,	3,	971,	"RAZ",	1,	1,	0,	0},
-	{"WR_ADDR"                     ,	3,	45,	971,	"R/W",	0,	1,	0ull,	0},
-	{"IOBIT"                       ,	48,	1,	971,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	971,	"RAZ",	1,	1,	0,	0},
-	{"WR_DATA"                     ,	0,	64,	972,	"R/W",	0,	1,	0ull,	0},
-	{"WR_MASK"                     ,	0,	8,	973,	"R/W",	0,	0,	255ull,	0ull},
-	{"RESERVED_8_63"               ,	8,	56,	973,	"RAZ",	1,	1,	0,	0},
-	{"TIME"                        ,	0,	32,	974,	"R/W",	0,	0,	0ull,	2097152ull},
-	{"RESERVED_32_63"              ,	32,	32,	974,	"RAZ",	1,	1,	0,	0},
-	{"PHASE"                       ,	0,	8,	975,	"R/W",	0,	0,	100ull,	100ull},
-	{"SAMPLE"                      ,	8,	4,	975,	"R/W",	0,	0,	2ull,	2ull},
-	{"PREAMBLE"                    ,	12,	1,	975,	"R/W",	0,	0,	1ull,	1ull},
-	{"CLK_IDLE"                    ,	13,	1,	975,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_14_14"              ,	14,	1,	975,	"RAZ",	1,	1,	0,	0},
-	{"SAMPLE_MODE"                 ,	15,	1,	975,	"R/W",	0,	0,	0ull,	0ull},
-	{"SAMPLE_HI"                   ,	16,	5,	975,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_21_23"              ,	21,	3,	975,	"RAZ",	1,	1,	0,	0},
-	{"MODE"                        ,	24,	1,	975,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_25_63"              ,	25,	39,	975,	"RAZ",	1,	1,	0,	0},
-	{"REG_ADR"                     ,	0,	5,	976,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_5_7"                ,	5,	3,	976,	"RAZ",	1,	1,	0,	0},
-	{"PHY_ADR"                     ,	8,	5,	976,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_13_15"              ,	13,	3,	976,	"RAZ",	1,	1,	0,	0},
-	{"PHY_OP"                      ,	16,	2,	976,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_18_63"              ,	18,	46,	976,	"RAZ",	1,	1,	0,	0},
-	{"EN"                          ,	0,	1,	977,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_1_63"               ,	1,	63,	977,	"RAZ",	1,	1,	0,	0},
-	{"DAT"                         ,	0,	16,	978,	"RO",	0,	1,	0ull,	0},
-	{"VAL"                         ,	16,	1,	978,	"RO",	0,	1,	0ull,	0},
-	{"PENDING"                     ,	17,	1,	978,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_18_63"              ,	18,	46,	978,	"RAZ",	1,	1,	0,	0},
-	{"DAT"                         ,	0,	16,	979,	"R/W",	0,	1,	0ull,	0},
-	{"VAL"                         ,	16,	1,	979,	"RO",	0,	1,	0ull,	0},
-	{"PENDING"                     ,	17,	1,	979,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_18_63"              ,	18,	46,	979,	"RAZ",	1,	1,	0,	0},
-	{"NCTL"                        ,	0,	6,	980,	"R/W",	0,	0,	15ull,	15ull},
-	{"RESERVED_6_7"                ,	6,	2,	980,	"RAZ",	1,	1,	0,	0},
-	{"PCTL"                        ,	8,	6,	980,	"R/W",	0,	0,	19ull,	19ull},
-	{"RESERVED_14_63"              ,	14,	50,	980,	"RAZ",	1,	1,	0,	0},
-	{"DENY_BAR0"                   ,	0,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
-	{"DENY_BAR1"                   ,	1,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
-	{"DENY_BAR2"                   ,	2,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	981,	"RAZ",	1,	1,	0,	0},
-	{"ASSY_VEN"                    ,	0,	16,	982,	"R/W",	0,	0,	140ull,	0ull},
-	{"ASSY_ID"                     ,	16,	16,	982,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	982,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_15"               ,	0,	16,	983,	"RAZ",	1,	1,	0,	0},
-	{"ASSY_REV"                    ,	16,	16,	983,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	983,	"RAZ",	1,	1,	0,	0},
-	{"RP0_PID"                     ,	0,	2,	984,	"R/W",	0,	0,	0ull,	0ull},
-	{"RP1_PID"                     ,	2,	1,	984,	"R/W",	0,	0,	0ull,	0ull},
-	{"RP0_SID"                     ,	3,	2,	984,	"R/W",	0,	0,	0ull,	0ull},
-	{"RP1_SID"                     ,	5,	1,	984,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	984,	"RAZ",	1,	1,	0,	0},
-	{"OMSG"                        ,	0,	7,	985,	"RO",	0,	0,	0ull,	0ull},
-	{"IMSG"                        ,	7,	5,	985,	"RO",	0,	0,	0ull,	0ull},
-	{"RXBUF"                       ,	12,	2,	985,	"RO",	0,	0,	0ull,	0ull},
-	{"TXBUF"                       ,	14,	2,	985,	"RO",	0,	0,	0ull,	0ull},
-	{"OSPF"                        ,	16,	1,	985,	"RO",	0,	0,	0ull,	0ull},
-	{"ISPF"                        ,	17,	1,	985,	"RO",	0,	0,	0ull,	0ull},
-	{"OARB"                        ,	18,	2,	985,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_20_23"              ,	20,	4,	985,	"RAZ",	1,	1,	0,	0},
-	{"OPTRS"                       ,	24,	4,	985,	"RO",	0,	0,	0ull,	0ull},
-	{"OBULK"                       ,	28,	4,	985,	"RO",	0,	0,	0ull,	0ull},
-	{"RTN"                         ,	32,	2,	985,	"RO",	0,	0,	0ull,	0ull},
-	{"OFREE"                       ,	34,	1,	985,	"RO",	0,	0,	0ull,	0ull},
-	{"ITAG"                        ,	35,	1,	985,	"RO",	0,	0,	0ull,	0ull},
-	{"OTAG"                        ,	36,	2,	985,	"RO",	0,	0,	0ull,	0ull},
-	{"BELL"                        ,	38,	2,	985,	"RO",	0,	0,	0ull,	0ull},
-	{"CRAM"                        ,	40,	2,	985,	"RO",	0,	0,	0ull,	0ull},
-	{"MRAM"                        ,	42,	2,	985,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_44_63"              ,	44,	20,	985,	"RAZ",	1,	1,	0,	0},
-	{"MBOX"                        ,	0,	4,	986,	"R/W",	0,	1,	0ull,	0},
-	{"PRIO"                        ,	4,	4,	986,	"R/W",	0,	1,	0ull,	0},
-	{"LTTR"                        ,	8,	4,	986,	"R/W",	0,	1,	0ull,	0},
-	{"PRT_SEL"                     ,	12,	3,	986,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_15_15"              ,	15,	1,	986,	"RAZ",	1,	1,	0,	0},
-	{"RP0_PID"                     ,	16,	2,	986,	"R/W",	0,	0,	0ull,	0ull},
-	{"RP1_PID"                     ,	18,	1,	986,	"R/W",	0,	0,	0ull,	0ull},
-	{"RP0_SID"                     ,	19,	2,	986,	"R/W",	0,	0,	0ull,	0ull},
-	{"RP1_SID"                     ,	21,	1,	986,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	986,	"RAZ",	1,	1,	0,	0},
-	{"RSP_THR"                     ,	24,	6,	986,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_30_30"              ,	30,	1,	986,	"RAZ",	1,	1,	0,	0},
-	{"TO_MODE"                     ,	31,	1,	986,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	986,	"RAZ",	1,	1,	0,	0},
-	{"TAG"                         ,	0,	32,	987,	"R/W",	0,	1,	0ull,	0},
-	{"TT"                          ,	32,	2,	987,	"R/W",	0,	1,	0ull,	0},
-	{"RS"                          ,	34,	1,	987,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_35_41"              ,	35,	7,	987,	"RAZ",	1,	1,	0,	0},
-	{"NTAG"                        ,	42,	1,	987,	"R/W",	0,	1,	0ull,	0},
-	{"NTT"                         ,	43,	1,	987,	"R/W",	0,	1,	0ull,	0},
-	{"NGRP"                        ,	44,	1,	987,	"R/W",	0,	1,	0ull,	0},
-	{"NQOS"                        ,	45,	1,	987,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_46_47"              ,	46,	2,	987,	"RAZ",	1,	1,	0,	0},
-	{"SL"                          ,	48,	7,	987,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_55_55"              ,	55,	1,	987,	"RAZ",	1,	1,	0,	0},
-	{"PM"                          ,	56,	2,	987,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_58_62"              ,	58,	5,	987,	"RAZ",	1,	1,	0,	0},
-	{"R"                           ,	63,	1,	987,	"R/W",	0,	1,	0ull,	0},
-	{"GRP0"                        ,	0,	4,	988,	"R/W",	0,	1,	0ull,	0},
-	{"QOS0"                        ,	4,	3,	988,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_7_7"                ,	7,	1,	988,	"RAZ",	1,	1,	0,	0},
-	{"GRP1"                        ,	8,	4,	988,	"R/W",	0,	1,	0ull,	0},
-	{"QOS1"                        ,	12,	3,	988,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_15_15"              ,	15,	1,	988,	"RAZ",	1,	1,	0,	0},
-	{"GRP2"                        ,	16,	4,	988,	"R/W",	0,	1,	0ull,	0},
-	{"QOS2"                        ,	20,	3,	988,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_23_23"              ,	23,	1,	988,	"RAZ",	1,	1,	0,	0},
-	{"GRP3"                        ,	24,	4,	988,	"R/W",	0,	1,	0ull,	0},
-	{"QOS3"                        ,	28,	3,	988,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_31_31"              ,	31,	1,	988,	"RAZ",	1,	1,	0,	0},
-	{"GRP4"                        ,	32,	4,	988,	"R/W",	0,	1,	0ull,	0},
-	{"QOS4"                        ,	36,	3,	988,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_39_39"              ,	39,	1,	988,	"RAZ",	1,	1,	0,	0},
-	{"GRP5"                        ,	40,	4,	988,	"R/W",	0,	1,	0ull,	0},
-	{"QOS5"                        ,	44,	3,	988,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_47_47"              ,	47,	1,	988,	"RAZ",	1,	1,	0,	0},
-	{"GRP6"                        ,	48,	4,	988,	"R/W",	0,	1,	0ull,	0},
-	{"QOS6"                        ,	52,	3,	988,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_55_55"              ,	55,	1,	988,	"RAZ",	1,	1,	0,	0},
-	{"GRP7"                        ,	56,	4,	988,	"R/W",	0,	1,	0ull,	0},
-	{"QOS7"                        ,	60,	3,	988,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_63_63"              ,	63,	1,	988,	"RAZ",	1,	1,	0,	0},
-	{"SID0"                        ,	0,	16,	989,	"RO",	0,	1,	0ull,	0},
-	{"LTTR0"                       ,	16,	2,	989,	"RO",	0,	1,	0ull,	0},
-	{"MBOX0"                       ,	18,	2,	989,	"RO",	0,	1,	0ull,	0},
-	{"SEG0"                        ,	20,	4,	989,	"RO",	0,	1,	0ull,	0},
-	{"DIS0"                        ,	24,	1,	989,	"RO",	0,	1,	0ull,	0},
-	{"TT0"                         ,	25,	1,	989,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_26_26"              ,	26,	1,	989,	"RAZ",	1,	1,	0,	0},
-	{"PRT0"                        ,	27,	1,	989,	"RO",	0,	1,	0ull,	0},
-	{"TOC0"                        ,	28,	1,	989,	"RO",	0,	1,	0ull,	0},
-	{"TOE0"                        ,	29,	1,	989,	"RO",	0,	1,	0ull,	0},
-	{"ERR0"                        ,	30,	1,	989,	"RO",	0,	1,	0ull,	0},
-	{"VAL0"                        ,	31,	1,	989,	"RO",	0,	1,	0ull,	0},
-	{"SID1"                        ,	32,	16,	989,	"RO",	0,	1,	0ull,	0},
-	{"LTTR1"                       ,	48,	2,	989,	"RO",	0,	1,	0ull,	0},
-	{"MBOX1"                       ,	50,	2,	989,	"RO",	0,	1,	0ull,	0},
-	{"SEG1"                        ,	52,	4,	989,	"RO",	0,	1,	0ull,	0},
-	{"DIS1"                        ,	56,	1,	989,	"RO",	0,	1,	0ull,	0},
-	{"TT1"                         ,	57,	1,	989,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_58_58"              ,	58,	1,	989,	"RAZ",	1,	1,	0,	0},
-	{"PRT1"                        ,	59,	1,	989,	"RO",	0,	1,	0ull,	0},
-	{"TOC1"                        ,	60,	1,	989,	"RO",	0,	1,	0ull,	0},
-	{"TOE1"                        ,	61,	1,	989,	"RO",	0,	1,	0ull,	0},
-	{"ERR1"                        ,	62,	1,	989,	"RO",	0,	1,	0ull,	0},
-	{"VAL1"                        ,	63,	1,	989,	"RO",	0,	1,	0ull,	0},
-	{"MAX_P0"                      ,	0,	6,	990,	"R/W",	0,	1,	48ull,	0},
-	{"RESERVED_6_7"                ,	6,	2,	990,	"RAZ",	1,	1,	0,	0},
-	{"MAX_P1"                      ,	8,	6,	990,	"R/W",	0,	1,	48ull,	0},
-	{"RESERVED_14_15"              ,	14,	2,	990,	"RAZ",	1,	1,	0,	0},
-	{"BUF_THR"                     ,	16,	4,	990,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_20_30"              ,	20,	11,	990,	"RAZ",	1,	1,	0,	0},
-	{"SP_VPORT"                    ,	31,	1,	990,	"R/W",	0,	0,	1ull,	1ull},
-	{"MAX_S0"                      ,	32,	6,	990,	"R/W",	0,	1,	48ull,	0},
-	{"RESERVED_38_39"              ,	38,	2,	990,	"RAZ",	1,	1,	0,	0},
-	{"MAX_S1"                      ,	40,	6,	990,	"R/W",	0,	1,	48ull,	0},
-	{"RESERVED_46_47"              ,	46,	2,	990,	"RAZ",	1,	1,	0,	0},
-	{"MAX_TOT"                     ,	48,	6,	990,	"R/W",	0,	1,	48ull,	0},
-	{"RESERVED_54_63"              ,	54,	10,	990,	"RAZ",	1,	1,	0,	0},
-	{"TXBELL"                      ,	0,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"BELL_ERR"                    ,	1,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"RXBELL"                      ,	2,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"MAINT_OP"                    ,	3,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"BAR_ERR"                     ,	4,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"DENY_WR"                     ,	5,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"SLI_ERR"                     ,	6,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"WR_DONE"                     ,	7,	1,	991,	"R/W",	0,	0,	0ull,	0ull},
-	{"MCE_TX"                      ,	8,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"MCE_RX"                      ,	9,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"SOFT_TX"                     ,	10,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"SOFT_RX"                     ,	11,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"LOG_ERB"                     ,	12,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"PHY_ERB"                     ,	13,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"LINK_DWN"                    ,	14,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"LINK_UP"                     ,	15,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"OMSG0"                       ,	16,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"OMSG1"                       ,	17,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"OMSG_ERR"                    ,	18,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"PKO_ERR"                     ,	19,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"RTRY_ERR"                    ,	20,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"F_ERROR"                     ,	21,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_22_63"              ,	22,	42,	991,	"RAZ",	1,	1,	0,	0},
-	{"BE1"                         ,	0,	8,	992,	"RO",	0,	1,	0ull,	0},
-	{"BE0"                         ,	8,	8,	992,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_16_28"              ,	16,	13,	992,	"RO",	1,	1,	0,	0},
-	{"STATUS"                      ,	29,	3,	992,	"RO",	0,	1,	0ull,	0},
-	{"LENGTH"                      ,	32,	10,	992,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_42_47"              ,	42,	6,	992,	"RO",	1,	1,	0,	0},
-	{"TAG"                         ,	48,	8,	992,	"RO",	0,	1,	0ull,	0},
-	{"TYPE"                        ,	56,	4,	992,	"RO",	0,	1,	0ull,	0},
-	{"CMD"                         ,	60,	4,	992,	"RO",	0,	1,	0ull,	0},
-	{"INFO1"                       ,	0,	64,	993,	"RO",	0,	0,	0ull,	0ull},
-	{"INTR"                        ,	0,	1,	994,	"RO",	0,	1,	0ull,	0},
-	{"LNS"                         ,	1,	1,	994,	"RO",	0,	1,	0ull,	0},
-	{"RSRVD"                       ,	2,	30,	994,	"RO",	0,	1,	0ull,	0},
-	{"LETTER"                      ,	32,	2,	994,	"RO",	0,	1,	0ull,	0},
-	{"MBOX"                        ,	34,	2,	994,	"RO",	0,	1,	0ull,	0},
-	{"XMBOX"                       ,	36,	4,	994,	"RO",	0,	1,	0ull,	0},
-	{"DID"                         ,	40,	16,	994,	"RO",	0,	1,	0ull,	0},
-	{"SSIZE"                       ,	56,	4,	994,	"RO",	0,	1,	0ull,	0},
-	{"SIS"                         ,	60,	1,	994,	"RO",	0,	1,	0ull,	0},
-	{"TT"                          ,	61,	1,	994,	"RO",	0,	1,	0ull,	0},
-	{"PRIO"                        ,	62,	2,	994,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_0_7"                ,	0,	8,	995,	"RAZ",	1,	1,	0,	0},
-	{"OTHER"                       ,	8,	48,	995,	"RO",	0,	1,	0ull,	0},
-	{"TYPE"                        ,	56,	4,	995,	"RO",	0,	1,	0ull,	0},
-	{"TT"                          ,	60,	2,	995,	"RO",	0,	1,	0ull,	0},
-	{"PRIO"                        ,	62,	2,	995,	"RO",	0,	1,	0ull,	0},
-	{"TXBELL"                      ,	0,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"BELL_ERR"                    ,	1,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RXBELL"                      ,	2,	1,	996,	"RO",	0,	0,	0ull,	0ull},
-	{"MAINT_OP"                    ,	3,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"BAR_ERR"                     ,	4,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"DENY_WR"                     ,	5,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"SLI_ERR"                     ,	6,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"WR_DONE"                     ,	7,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"MCE_TX"                      ,	8,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"MCE_RX"                      ,	9,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"SOFT_TX"                     ,	10,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"SOFT_RX"                     ,	11,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"LOG_ERB"                     ,	12,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PHY_ERB"                     ,	13,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"LINK_DWN"                    ,	14,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"LINK_UP"                     ,	15,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"OMSG0"                       ,	16,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"OMSG1"                       ,	17,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"OMSG_ERR"                    ,	18,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PKO_ERR"                     ,	19,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RTRY_ERR"                    ,	20,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"F_ERROR"                     ,	21,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_22_63"              ,	22,	42,	996,	"RAZ",	1,	1,	0,	0},
-	{"RX_POL"                      ,	0,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
-	{"TX_POL"                      ,	4,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
-	{"PT_WIDTH"                    ,	8,	2,	997,	"R/W",	0,	0,	2ull,	2ull},
-	{"TX_FLOW"                     ,	10,	1,	997,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_11_11"              ,	11,	1,	997,	"RAZ",	1,	1,	0,	0},
-	{"A50"                         ,	12,	1,	997,	"R/W",	0,	0,	1ull,	1ull},
-	{"A66"                         ,	13,	1,	997,	"R/W",	0,	0,	1ull,	1ull},
-	{"RESERVED_14_31"              ,	14,	18,	997,	"RAZ",	1,	1,	0,	0},
-	{"OPS"                         ,	32,	32,	997,	"R/W",	0,	0,	64756ull,	64756ull},
-	{"ADDR"                        ,	0,	24,	998,	"R/W",	0,	1,	0ull,	0},
-	{"OP"                          ,	24,	1,	998,	"R/W",	0,	1,	0ull,	0},
-	{"PENDING"                     ,	25,	1,	998,	"RO",	0,	1,	0ull,	0},
-	{"FAIL"                        ,	26,	1,	998,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_27_31"              ,	27,	5,	998,	"RAZ",	1,	1,	0,	0},
-	{"WR_DATA"                     ,	32,	32,	998,	"R/W",	0,	1,	0ull,	0},
-	{"RD_DATA"                     ,	0,	32,	999,	"RO",	0,	1,	0ull,	0},
-	{"VALID"                       ,	32,	1,	999,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_33_63"              ,	33,	31,	999,	"RAZ",	1,	1,	0,	0},
-	{"MCE"                         ,	0,	1,	1000,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	1000,	"RAZ",	1,	1,	0,	0},
-	{"RP0_PID"                     ,	0,	2,	1001,	"R/W",	0,	0,	0ull,	0ull},
-	{"RP1_PID"                     ,	2,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
-	{"RP0_SID"                     ,	3,	2,	1001,	"R/W",	0,	0,	0ull,	0ull},
-	{"RP1_SID"                     ,	5,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	1001,	"RAZ",	1,	1,	0,	0},
-	{"W_RO"                        ,	8,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
-	{"RR_RO"                       ,	9,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_63"              ,	10,	54,	1001,	"RAZ",	1,	1,	0,	0},
-	{"LTTR_MP"                     ,	0,	4,	1002,	"R/W",	0,	1,	15ull,	0},
-	{"LTTR_SP"                     ,	4,	4,	1002,	"R/W",	0,	1,	15ull,	0},
-	{"IDM_DID"                     ,	8,	1,	1002,	"R/W",	0,	1,	1ull,	0},
-	{"IDM_SIS"                     ,	9,	1,	1002,	"R/W",	0,	1,	1ull,	0},
-	{"IDM_TT"                      ,	10,	1,	1002,	"R/W",	0,	1,	1ull,	0},
-	{"RESERVED_11_14"              ,	11,	4,	1002,	"RAZ",	1,	1,	0,	0},
-	{"RTRY_EN"                     ,	15,	1,	1002,	"R/W",	0,	1,	0ull,	0},
-	{"RTRY_THR"                    ,	16,	16,	1002,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_62"              ,	32,	31,	1002,	"RAZ",	1,	1,	0,	0},
-	{"TESTMODE"                    ,	63,	1,	1002,	"R/W",	0,	0,	0ull,	0ull},
-	{"ALL_PSD"                     ,	0,	1,	1003,	"R/W",	0,	1,	0ull,	0},
-	{"ALL_NMP"                     ,	1,	1,	1003,	"R/W",	0,	1,	0ull,	0},
-	{"ALL_FMP"                     ,	2,	1,	1003,	"R/W",	0,	1,	0ull,	0},
-	{"ALL_SP"                      ,	3,	1,	1003,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_PSD"                    ,	4,	1,	1003,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_NMP"                    ,	5,	1,	1003,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_FMP"                    ,	6,	1,	1003,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_SP"                     ,	7,	1,	1003,	"R/W",	0,	1,	0ull,	0},
-	{"ID_PSD"                      ,	8,	1,	1003,	"R/W",	0,	1,	0ull,	0},
-	{"ID_NMP"                      ,	9,	1,	1003,	"R/W",	0,	1,	0ull,	0},
-	{"ID_FMP"                      ,	10,	1,	1003,	"R/W",	0,	1,	0ull,	0},
-	{"ID_SP"                       ,	11,	1,	1003,	"R/W",	0,	1,	0ull,	0},
-	{"CTLR_NMP"                    ,	12,	1,	1003,	"R/W",	0,	1,	0ull,	0},
-	{"CTLR_FMP"                    ,	13,	1,	1003,	"R/W",	0,	1,	0ull,	0},
-	{"CTLR_SP"                     ,	14,	1,	1003,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_15_63"              ,	15,	49,	1003,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_0"                ,	0,	1,	1004,	"R/W",	0,	0,	0ull,	0ull},
-	{"ALL_NMP"                     ,	1,	1,	1004,	"R/W",	0,	1,	0ull,	0},
-	{"ALL_FMP"                     ,	2,	1,	1004,	"R/W",	0,	1,	0ull,	0},
-	{"ALL_SP"                      ,	3,	1,	1004,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_4_4"                ,	4,	1,	1004,	"R/W",	0,	0,	0ull,	0ull},
-	{"MBOX_NMP"                    ,	5,	1,	1004,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_FMP"                    ,	6,	1,	1004,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_SP"                     ,	7,	1,	1004,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_8_8"                ,	8,	1,	1004,	"R/W",	0,	0,	0ull,	0ull},
-	{"ID_NMP"                      ,	9,	1,	1004,	"R/W",	0,	1,	0ull,	0},
-	{"ID_FMP"                      ,	10,	1,	1004,	"R/W",	0,	1,	0ull,	0},
-	{"ID_SP"                       ,	11,	1,	1004,	"R/W",	0,	1,	0ull,	0},
-	{"CTLR_NMP"                    ,	12,	1,	1004,	"R/W",	0,	1,	0ull,	0},
-	{"CTLR_FMP"                    ,	13,	1,	1004,	"R/W",	0,	1,	0ull,	0},
-	{"CTLR_SP"                     ,	14,	1,	1004,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_15_63"              ,	15,	49,	1004,	"RAZ",	1,	1,	0,	0},
-	{"PORT"                        ,	0,	2,	1005,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_2_30"               ,	2,	29,	1005,	"RAZ",	1,	1,	0,	0},
-	{"ENABLE"                      ,	31,	1,	1005,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	1005,	"RAZ",	1,	1,	0,	0},
-	{"ALL_PSD"                     ,	0,	1,	1006,	"R/W",	0,	1,	0ull,	0},
-	{"ALL_NMP"                     ,	1,	1,	1006,	"R/W",	0,	1,	0ull,	0},
-	{"ALL_FMP"                     ,	2,	1,	1006,	"R/W",	0,	1,	0ull,	0},
-	{"ALL_SP"                      ,	3,	1,	1006,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_PSD"                    ,	4,	1,	1006,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_NMP"                    ,	5,	1,	1006,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_FMP"                    ,	6,	1,	1006,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_SP"                     ,	7,	1,	1006,	"R/W",	0,	1,	0ull,	0},
-	{"ID_PSD"                      ,	8,	1,	1006,	"R/W",	0,	1,	0ull,	0},
-	{"ID_NMP"                      ,	9,	1,	1006,	"R/W",	0,	1,	0ull,	0},
-	{"ID_FMP"                      ,	10,	1,	1006,	"R/W",	0,	1,	0ull,	0},
-	{"ID_SP"                       ,	11,	1,	1006,	"R/W",	0,	1,	0ull,	0},
-	{"CTLR_NMP"                    ,	12,	1,	1006,	"R/W",	0,	1,	0ull,	0},
-	{"CTLR_FMP"                    ,	13,	1,	1006,	"R/W",	0,	1,	0ull,	0},
-	{"CTLR_SP"                     ,	14,	1,	1006,	"R/W",	0,	1,	0ull,	0},
-	{"XMBOX_SP"                    ,	15,	1,	1006,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_16_63"              ,	16,	48,	1006,	"RAZ",	1,	1,	0,	0},
-	{"PRIORITY"                    ,	0,	2,	1007,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_2"                ,	2,	1,	1007,	"RAZ",	1,	1,	0,	0},
-	{"ID16"                        ,	3,	1,	1007,	"RO",	0,	0,	0ull,	0ull},
-	{"DEST_ID"                     ,	4,	1,	1007,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_7"                ,	5,	3,	1007,	"RAZ",	1,	1,	0,	0},
-	{"COUNT"                       ,	8,	8,	1007,	"RO",	0,	0,	0ull,	0ull},
-	{"SRC_ID"                      ,	16,	16,	1007,	"RO",	0,	0,	0ull,	0ull},
-	{"DATA"                        ,	32,	16,	1007,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	1007,	"RAZ",	1,	1,	0,	0},
-	{"SEQ"                         ,	0,	32,	1008,	"RO",	0,	1,	0ull,	0},
-	{"COUNT"                       ,	32,	8,	1008,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_40_63"              ,	40,	24,	1008,	"RAZ",	1,	1,	0,	0},
-	{"POST"                        ,	0,	8,	1009,	"RO",	0,	1,	128ull,	0},
-	{"N_POST"                      ,	8,	5,	1009,	"RO",	0,	1,	16ull,	0},
-	{"RESERVED_13_15"              ,	13,	3,	1009,	"RAZ",	1,	1,	0,	0},
-	{"COMP"                        ,	16,	8,	1009,	"RO",	0,	1,	128ull,	0},
-	{"MBOX"                        ,	24,	4,	1009,	"RO",	0,	1,	8ull,	0},
-	{"RESERVED_28_39"              ,	28,	12,	1009,	"RAZ",	1,	1,	0,	0},
-	{"RTN_PR1"                     ,	40,	8,	1009,	"RO",	0,	1,	0ull,	0},
-	{"RTN_PR2"                     ,	48,	8,	1009,	"RO",	0,	1,	0ull,	0},
-	{"RTN_PR3"                     ,	56,	8,	1009,	"RO",	0,	1,	0ull,	0},
-	{"IAOW_SEL"                    ,	0,	2,	1010,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_3"                ,	2,	2,	1010,	"RAZ",	1,	1,	0,	0},
-	{"ID16"                        ,	4,	1,	1010,	"R/W",	0,	0,	0ull,	0ull},
-	{"SRC_ID"                      ,	5,	1,	1010,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	1010,	"RAZ",	1,	1,	0,	0},
-	{"RD_PRIOR"                    ,	8,	2,	1010,	"R/W",	0,	0,	1ull,	1ull},
-	{"WR_PRIOR"                    ,	10,	2,	1010,	"R/W",	0,	0,	0ull,	0ull},
-	{"RD_OP"                       ,	12,	3,	1010,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_15_15"              ,	15,	1,	1010,	"RAZ",	1,	1,	0,	0},
-	{"WR_OP"                       ,	16,	3,	1010,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_19_63"              ,	19,	45,	1010,	"RAZ",	1,	1,	0,	0},
-	{"SEQ"                         ,	0,	32,	1011,	"RO",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	64,	962,	"R/W",	0,	1,	0ull,	0},
+	{"OUT_RST"                     ,	0,	32,	963,	"RO",	0,	1,	0ull,	0},
+	{"IN_RST"                      ,	32,	32,	963,	"RO",	0,	1,	0ull,	0},
+	{"ES"                          ,	0,	64,	964,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	965,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	965,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	966,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	966,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	967,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	967,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	968,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	968,	"RAZ",	1,	1,	0,	0},
+	{"MRRS"                        ,	0,	3,	969,	"R/W",	0,	0,	2ull,	2ull},
+	{"BAR0_D"                      ,	3,	1,	969,	"R/W",	0,	0,	0ull,	0ull},
+	{"WIND_D"                      ,	4,	1,	969,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	969,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	970,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	971,	"R/W",	0,	1,	0ull,	0},
+	{"CSR"                         ,	0,	39,	972,	"RO",	0,	1,	1ull,	0},
+	{"ARB"                         ,	39,	1,	972,	"RO",	0,	1,	0ull,	0},
+	{"CPL0"                        ,	40,	12,	972,	"RO",	0,	1,	1ull,	0},
+	{"CPL1"                        ,	52,	12,	972,	"RO",	0,	1,	1ull,	0},
+	{"NND"                         ,	0,	8,	973,	"RO",	0,	1,	1ull,	0},
+	{"NNP0"                        ,	8,	8,	973,	"RO",	0,	1,	1ull,	0},
+	{"CSM0"                        ,	16,	15,	973,	"RO",	0,	1,	1ull,	0},
+	{"CSM1"                        ,	31,	15,	973,	"RO",	0,	1,	1ull,	0},
+	{"RAC"                         ,	46,	1,	973,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	973,	"RAZ",	1,	1,	0,	0},
+	{"NNP1"                        ,	48,	8,	973,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	973,	"RAZ",	1,	1,	0,	0},
+	{"NSM0"                        ,	0,	13,	974,	"RO",	0,	1,	1ull,	0},
+	{"NSM1"                        ,	13,	13,	974,	"RO",	0,	1,	1ull,	0},
+	{"PSM0"                        ,	26,	15,	974,	"RO",	0,	1,	1ull,	0},
+	{"PSM1"                        ,	41,	15,	974,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	974,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	0,	48,	975,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	975,	"R/W",	0,	0,	0ull,	0ull},
+	{"LD_CMD"                      ,	49,	2,	975,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_51_63"              ,	51,	13,	975,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	976,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	977,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	3,	45,	977,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	977,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	977,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	978,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	979,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	979,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	980,	"R/W",	0,	0,	0ull,	2097152ull},
+	{"RESERVED_32_63"              ,	32,	32,	980,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	981,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	981,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	981,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	981,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	981,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	24,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	981,	"RAZ",	1,	1,	0,	0},
+	{"REG_ADR"                     ,	0,	5,	982,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	982,	"RAZ",	1,	1,	0,	0},
+	{"PHY_ADR"                     ,	8,	5,	982,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	982,	"RAZ",	1,	1,	0,	0},
+	{"PHY_OP"                      ,	16,	2,	982,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	982,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	983,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	983,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	984,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	984,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	984,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	984,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	985,	"R/W",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	985,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	985,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	985,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	986,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_6_7"                ,	6,	2,	986,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	8,	6,	986,	"R/W",	0,	0,	19ull,	19ull},
+	{"RESERVED_14_63"              ,	14,	50,	986,	"RAZ",	1,	1,	0,	0},
+	{"DENY_BAR0"                   ,	0,	1,	987,	"R/W",	0,	0,	0ull,	0ull},
+	{"DENY_BAR1"                   ,	1,	1,	987,	"R/W",	0,	0,	0ull,	0ull},
+	{"DENY_BAR2"                   ,	2,	1,	987,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	987,	"RAZ",	1,	1,	0,	0},
+	{"ASSY_VEN"                    ,	0,	16,	988,	"R/W",	0,	0,	140ull,	0ull},
+	{"ASSY_ID"                     ,	16,	16,	988,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	988,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	989,	"RAZ",	1,	1,	0,	0},
+	{"ASSY_REV"                    ,	16,	16,	989,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	989,	"RAZ",	1,	1,	0,	0},
+	{"RP0_PID"                     ,	0,	2,	990,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_PID"                     ,	2,	1,	990,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP0_SID"                     ,	3,	2,	990,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_SID"                     ,	5,	1,	990,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	990,	"RAZ",	1,	1,	0,	0},
+	{"OMSG"                        ,	0,	7,	991,	"RO",	0,	0,	0ull,	0ull},
+	{"IMSG"                        ,	7,	5,	991,	"RO",	0,	0,	0ull,	0ull},
+	{"RXBUF"                       ,	12,	2,	991,	"RO",	0,	0,	0ull,	0ull},
+	{"TXBUF"                       ,	14,	2,	991,	"RO",	0,	0,	0ull,	0ull},
+	{"OSPF"                        ,	16,	1,	991,	"RO",	0,	0,	0ull,	0ull},
+	{"ISPF"                        ,	17,	1,	991,	"RO",	0,	0,	0ull,	0ull},
+	{"OARB"                        ,	18,	2,	991,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_23"              ,	20,	4,	991,	"RAZ",	1,	1,	0,	0},
+	{"OPTRS"                       ,	24,	4,	991,	"RO",	0,	0,	0ull,	0ull},
+	{"OBULK"                       ,	28,	4,	991,	"RO",	0,	0,	0ull,	0ull},
+	{"RTN"                         ,	32,	2,	991,	"RO",	0,	0,	0ull,	0ull},
+	{"OFREE"                       ,	34,	1,	991,	"RO",	0,	0,	0ull,	0ull},
+	{"ITAG"                        ,	35,	1,	991,	"RO",	0,	0,	0ull,	0ull},
+	{"OTAG"                        ,	36,	2,	991,	"RO",	0,	0,	0ull,	0ull},
+	{"BELL"                        ,	38,	2,	991,	"RO",	0,	0,	0ull,	0ull},
+	{"CRAM"                        ,	40,	2,	991,	"RO",	0,	0,	0ull,	0ull},
+	{"MRAM"                        ,	42,	2,	991,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_63"              ,	44,	20,	991,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	992,	"R/W",	0,	1,	0ull,	0},
+	{"PRIO"                        ,	4,	4,	992,	"R/W",	0,	1,	0ull,	0},
+	{"LTTR"                        ,	8,	4,	992,	"R/W",	0,	1,	0ull,	0},
+	{"PRT_SEL"                     ,	12,	3,	992,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	992,	"RAZ",	1,	1,	0,	0},
+	{"RP0_PID"                     ,	16,	2,	992,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_PID"                     ,	18,	1,	992,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP0_SID"                     ,	19,	2,	992,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_SID"                     ,	21,	1,	992,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	992,	"RAZ",	1,	1,	0,	0},
+	{"RSP_THR"                     ,	24,	6,	992,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	992,	"RAZ",	1,	1,	0,	0},
+	{"TO_MODE"                     ,	31,	1,	992,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	992,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	0,	32,	993,	"R/W",	0,	1,	0ull,	0},
+	{"TT"                          ,	32,	2,	993,	"R/W",	0,	1,	0ull,	0},
+	{"RS"                          ,	34,	1,	993,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_35_41"              ,	35,	7,	993,	"RAZ",	1,	1,	0,	0},
+	{"NTAG"                        ,	42,	1,	993,	"R/W",	0,	1,	0ull,	0},
+	{"NTT"                         ,	43,	1,	993,	"R/W",	0,	1,	0ull,	0},
+	{"NGRP"                        ,	44,	1,	993,	"R/W",	0,	1,	0ull,	0},
+	{"NQOS"                        ,	45,	1,	993,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	993,	"RAZ",	1,	1,	0,	0},
+	{"SL"                          ,	48,	7,	993,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_55_55"              ,	55,	1,	993,	"RAZ",	1,	1,	0,	0},
+	{"PM"                          ,	56,	2,	993,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_58_62"              ,	58,	5,	993,	"RAZ",	1,	1,	0,	0},
+	{"R"                           ,	63,	1,	993,	"R/W",	0,	1,	0ull,	0},
+	{"GRP0"                        ,	0,	4,	994,	"R/W",	0,	1,	0ull,	0},
+	{"QOS0"                        ,	4,	3,	994,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	994,	"RAZ",	1,	1,	0,	0},
+	{"GRP1"                        ,	8,	4,	994,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1"                        ,	12,	3,	994,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	994,	"RAZ",	1,	1,	0,	0},
+	{"GRP2"                        ,	16,	4,	994,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2"                        ,	20,	3,	994,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	994,	"RAZ",	1,	1,	0,	0},
+	{"GRP3"                        ,	24,	4,	994,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3"                        ,	28,	3,	994,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_31_31"              ,	31,	1,	994,	"RAZ",	1,	1,	0,	0},
+	{"GRP4"                        ,	32,	4,	994,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4"                        ,	36,	3,	994,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_39_39"              ,	39,	1,	994,	"RAZ",	1,	1,	0,	0},
+	{"GRP5"                        ,	40,	4,	994,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5"                        ,	44,	3,	994,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	994,	"RAZ",	1,	1,	0,	0},
+	{"GRP6"                        ,	48,	4,	994,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6"                        ,	52,	3,	994,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_55_55"              ,	55,	1,	994,	"RAZ",	1,	1,	0,	0},
+	{"GRP7"                        ,	56,	4,	994,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7"                        ,	60,	3,	994,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_63_63"              ,	63,	1,	994,	"RAZ",	1,	1,	0,	0},
+	{"SID0"                        ,	0,	16,	995,	"RO",	0,	1,	0ull,	0},
+	{"LTTR0"                       ,	16,	2,	995,	"RO",	0,	1,	0ull,	0},
+	{"MBOX0"                       ,	18,	2,	995,	"RO",	0,	1,	0ull,	0},
+	{"SEG0"                        ,	20,	4,	995,	"RO",	0,	1,	0ull,	0},
+	{"DIS0"                        ,	24,	1,	995,	"RO",	0,	1,	0ull,	0},
+	{"TT0"                         ,	25,	1,	995,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_26"              ,	26,	1,	995,	"RAZ",	1,	1,	0,	0},
+	{"PRT0"                        ,	27,	1,	995,	"RO",	0,	1,	0ull,	0},
+	{"TOC0"                        ,	28,	1,	995,	"RO",	0,	1,	0ull,	0},
+	{"TOE0"                        ,	29,	1,	995,	"RO",	0,	1,	0ull,	0},
+	{"ERR0"                        ,	30,	1,	995,	"RO",	0,	1,	0ull,	0},
+	{"VAL0"                        ,	31,	1,	995,	"RO",	0,	1,	0ull,	0},
+	{"SID1"                        ,	32,	16,	995,	"RO",	0,	1,	0ull,	0},
+	{"LTTR1"                       ,	48,	2,	995,	"RO",	0,	1,	0ull,	0},
+	{"MBOX1"                       ,	50,	2,	995,	"RO",	0,	1,	0ull,	0},
+	{"SEG1"                        ,	52,	4,	995,	"RO",	0,	1,	0ull,	0},
+	{"DIS1"                        ,	56,	1,	995,	"RO",	0,	1,	0ull,	0},
+	{"TT1"                         ,	57,	1,	995,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_58"              ,	58,	1,	995,	"RAZ",	1,	1,	0,	0},
+	{"PRT1"                        ,	59,	1,	995,	"RO",	0,	1,	0ull,	0},
+	{"TOC1"                        ,	60,	1,	995,	"RO",	0,	1,	0ull,	0},
+	{"TOE1"                        ,	61,	1,	995,	"RO",	0,	1,	0ull,	0},
+	{"ERR1"                        ,	62,	1,	995,	"RO",	0,	1,	0ull,	0},
+	{"VAL1"                        ,	63,	1,	995,	"RO",	0,	1,	0ull,	0},
+	{"MAX_P0"                      ,	0,	6,	996,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	996,	"RAZ",	1,	1,	0,	0},
+	{"MAX_P1"                      ,	8,	6,	996,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	996,	"RAZ",	1,	1,	0,	0},
+	{"BUF_THR"                     ,	16,	4,	996,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_30"              ,	20,	11,	996,	"RAZ",	1,	1,	0,	0},
+	{"SP_VPORT"                    ,	31,	1,	996,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAX_S0"                      ,	32,	6,	996,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_38_39"              ,	38,	2,	996,	"RAZ",	1,	1,	0,	0},
+	{"MAX_S1"                      ,	40,	6,	996,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	996,	"RAZ",	1,	1,	0,	0},
+	{"MAX_TOT"                     ,	48,	6,	996,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_54_63"              ,	54,	10,	996,	"RAZ",	1,	1,	0,	0},
+	{"TXBELL"                      ,	0,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"BELL_ERR"                    ,	1,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBELL"                      ,	2,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAINT_OP"                    ,	3,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR_ERR"                     ,	4,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"DENY_WR"                     ,	5,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"SLI_ERR"                     ,	6,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"WR_DONE"                     ,	7,	1,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCE_TX"                      ,	8,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"MCE_RX"                      ,	9,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"SOFT_TX"                     ,	10,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"SOFT_RX"                     ,	11,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"LOG_ERB"                     ,	12,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"PHY_ERB"                     ,	13,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"LINK_DWN"                    ,	14,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"LINK_UP"                     ,	15,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"OMSG0"                       ,	16,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"OMSG1"                       ,	17,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"OMSG_ERR"                    ,	18,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO_ERR"                     ,	19,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"RTRY_ERR"                    ,	20,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"F_ERROR"                     ,	21,	1,	997,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	997,	"RAZ",	1,	1,	0,	0},
+	{"BE1"                         ,	0,	8,	998,	"RO",	0,	1,	0ull,	0},
+	{"BE0"                         ,	8,	8,	998,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_28"              ,	16,	13,	998,	"RO",	1,	1,	0,	0},
+	{"STATUS"                      ,	29,	3,	998,	"RO",	0,	1,	0ull,	0},
+	{"LENGTH"                      ,	32,	10,	998,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	998,	"RO",	1,	1,	0,	0},
+	{"TAG"                         ,	48,	8,	998,	"RO",	0,	1,	0ull,	0},
+	{"TYPE"                        ,	56,	4,	998,	"RO",	0,	1,	0ull,	0},
+	{"CMD"                         ,	60,	4,	998,	"RO",	0,	1,	0ull,	0},
+	{"INFO1"                       ,	0,	64,	999,	"RO",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	1,	1000,	"RO",	0,	1,	0ull,	0},
+	{"LNS"                         ,	1,	1,	1000,	"RO",	0,	1,	0ull,	0},
+	{"RSRVD"                       ,	2,	30,	1000,	"RO",	0,	1,	0ull,	0},
+	{"LETTER"                      ,	32,	2,	1000,	"RO",	0,	1,	0ull,	0},
+	{"MBOX"                        ,	34,	2,	1000,	"RO",	0,	1,	0ull,	0},
+	{"XMBOX"                       ,	36,	4,	1000,	"RO",	0,	1,	0ull,	0},
+	{"DID"                         ,	40,	16,	1000,	"RO",	0,	1,	0ull,	0},
+	{"SSIZE"                       ,	56,	4,	1000,	"RO",	0,	1,	0ull,	0},
+	{"SIS"                         ,	60,	1,	1000,	"RO",	0,	1,	0ull,	0},
+	{"TT"                          ,	61,	1,	1000,	"RO",	0,	1,	0ull,	0},
+	{"PRIO"                        ,	62,	2,	1000,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1001,	"RAZ",	1,	1,	0,	0},
+	{"OTHER"                       ,	8,	48,	1001,	"RO",	0,	1,	0ull,	0},
+	{"TYPE"                        ,	56,	4,	1001,	"RO",	0,	1,	0ull,	0},
+	{"TT"                          ,	60,	2,	1001,	"RO",	0,	1,	0ull,	0},
+	{"PRIO"                        ,	62,	2,	1001,	"RO",	0,	1,	0ull,	0},
+	{"TXBELL"                      ,	0,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BELL_ERR"                    ,	1,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBELL"                      ,	2,	1,	1002,	"RO",	0,	0,	0ull,	0ull},
+	{"MAINT_OP"                    ,	3,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAR_ERR"                     ,	4,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DENY_WR"                     ,	5,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SLI_ERR"                     ,	6,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WR_DONE"                     ,	7,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCE_TX"                      ,	8,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCE_RX"                      ,	9,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SOFT_TX"                     ,	10,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SOFT_RX"                     ,	11,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LOG_ERB"                     ,	12,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_ERB"                     ,	13,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LINK_DWN"                    ,	14,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LINK_UP"                     ,	15,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OMSG0"                       ,	16,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OMSG1"                       ,	17,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OMSG_ERR"                    ,	18,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO_ERR"                     ,	19,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTRY_ERR"                    ,	20,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"F_ERROR"                     ,	21,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	1002,	"RAZ",	1,	1,	0,	0},
+	{"RX_POL"                      ,	0,	4,	1003,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_POL"                      ,	4,	4,	1003,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_WIDTH"                    ,	8,	2,	1003,	"R/W",	0,	0,	2ull,	2ull},
+	{"TX_FLOW"                     ,	10,	1,	1003,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	1003,	"RAZ",	1,	1,	0,	0},
+	{"A50"                         ,	12,	1,	1003,	"R/W",	0,	0,	1ull,	1ull},
+	{"A66"                         ,	13,	1,	1003,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	1003,	"RAZ",	1,	1,	0,	0},
+	{"OPS"                         ,	32,	32,	1003,	"R/W",	0,	0,	64756ull,	64756ull},
+	{"ADDR"                        ,	0,	24,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	24,	1,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	25,	1,	1004,	"RO",	0,	1,	0ull,	0},
+	{"FAIL"                        ,	26,	1,	1004,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_27_31"              ,	27,	5,	1004,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	32,	32,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DATA"                     ,	0,	32,	1005,	"RO",	0,	1,	0ull,	0},
+	{"VALID"                       ,	32,	1,	1005,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	1005,	"RAZ",	1,	1,	0,	0},
+	{"MCE"                         ,	0,	1,	1006,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1006,	"RAZ",	1,	1,	0,	0},
+	{"RP0_PID"                     ,	0,	2,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_PID"                     ,	2,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP0_SID"                     ,	3,	2,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_SID"                     ,	5,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	1007,	"RAZ",	1,	1,	0,	0},
+	{"W_RO"                        ,	8,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"RR_RO"                       ,	9,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1007,	"RAZ",	1,	1,	0,	0},
+	{"LTTR_MP"                     ,	0,	4,	1008,	"R/W",	0,	1,	15ull,	0},
+	{"LTTR_SP"                     ,	4,	4,	1008,	"R/W",	0,	1,	15ull,	0},
+	{"IDM_DID"                     ,	8,	1,	1008,	"R/W",	0,	1,	1ull,	0},
+	{"IDM_SIS"                     ,	9,	1,	1008,	"R/W",	0,	1,	1ull,	0},
+	{"IDM_TT"                      ,	10,	1,	1008,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_11_14"              ,	11,	4,	1008,	"RAZ",	1,	1,	0,	0},
+	{"RTRY_EN"                     ,	15,	1,	1008,	"R/W",	0,	1,	0ull,	0},
+	{"RTRY_THR"                    ,	16,	16,	1008,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_62"              ,	32,	31,	1008,	"RAZ",	1,	1,	0,	0},
+	{"TESTMODE"                    ,	63,	1,	1008,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALL_PSD"                     ,	0,	1,	1009,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_NMP"                     ,	1,	1,	1009,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_FMP"                     ,	2,	1,	1009,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_SP"                      ,	3,	1,	1009,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_PSD"                    ,	4,	1,	1009,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_NMP"                    ,	5,	1,	1009,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_FMP"                    ,	6,	1,	1009,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_SP"                     ,	7,	1,	1009,	"R/W",	0,	1,	0ull,	0},
+	{"ID_PSD"                      ,	8,	1,	1009,	"R/W",	0,	1,	0ull,	0},
+	{"ID_NMP"                      ,	9,	1,	1009,	"R/W",	0,	1,	0ull,	0},
+	{"ID_FMP"                      ,	10,	1,	1009,	"R/W",	0,	1,	0ull,	0},
+	{"ID_SP"                       ,	11,	1,	1009,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_NMP"                    ,	12,	1,	1009,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_FMP"                    ,	13,	1,	1009,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_SP"                     ,	14,	1,	1009,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	1009,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	1010,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALL_NMP"                     ,	1,	1,	1010,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_FMP"                     ,	2,	1,	1010,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_SP"                      ,	3,	1,	1010,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_4"                ,	4,	1,	1010,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX_NMP"                    ,	5,	1,	1010,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_FMP"                    ,	6,	1,	1010,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_SP"                     ,	7,	1,	1010,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_8"                ,	8,	1,	1010,	"R/W",	0,	0,	0ull,	0ull},
+	{"ID_NMP"                      ,	9,	1,	1010,	"R/W",	0,	1,	0ull,	0},
+	{"ID_FMP"                      ,	10,	1,	1010,	"R/W",	0,	1,	0ull,	0},
+	{"ID_SP"                       ,	11,	1,	1010,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_NMP"                    ,	12,	1,	1010,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_FMP"                    ,	13,	1,	1010,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_SP"                     ,	14,	1,	1010,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	1010,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	2,	1011,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_30"               ,	2,	29,	1011,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	31,	1,	1011,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_32_63"              ,	32,	32,	1011,	"RAZ",	1,	1,	0,	0},
-	{"SRIO"                        ,	0,	1,	1012,	"RO",	1,	1,	0,	0},
-	{"ACCESS"                      ,	1,	1,	1012,	"RO",	1,	1,	0,	0},
-	{"RESERVED_2_63"               ,	2,	62,	1012,	"RAZ",	1,	1,	0,	0},
-	{"ITAG"                        ,	0,	5,	1013,	"RO",	0,	1,	16ull,	0},
+	{"ALL_PSD"                     ,	0,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_NMP"                     ,	1,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_FMP"                     ,	2,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_SP"                      ,	3,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_PSD"                    ,	4,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_NMP"                    ,	5,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_FMP"                    ,	6,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_SP"                     ,	7,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"ID_PSD"                      ,	8,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"ID_NMP"                      ,	9,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"ID_FMP"                      ,	10,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"ID_SP"                       ,	11,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_NMP"                    ,	12,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_FMP"                    ,	13,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_SP"                     ,	14,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"XMBOX_SP"                    ,	15,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	1012,	"RAZ",	1,	1,	0,	0},
+	{"PRIORITY"                    ,	0,	2,	1013,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1013,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	3,	1,	1013,	"RO",	0,	0,	0ull,	0ull},
+	{"DEST_ID"                     ,	4,	1,	1013,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_5_7"                ,	5,	3,	1013,	"RAZ",	1,	1,	0,	0},
-	{"OTAG"                        ,	8,	5,	1013,	"RO",	0,	1,	16ull,	0},
-	{"RESERVED_13_15"              ,	13,	3,	1013,	"RAZ",	1,	1,	0,	0},
-	{"O_CLR"                       ,	16,	1,	1013,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_17_63"              ,	17,	47,	1013,	"RAZ",	1,	1,	0,	0},
-	{"POST"                        ,	0,	8,	1014,	"R/W",	0,	0,	128ull,	128ull},
-	{"N_POST"                      ,	8,	5,	1014,	"R/W",	0,	0,	16ull,	16ull},
-	{"RESERVED_13_15"              ,	13,	3,	1014,	"RAZ",	1,	1,	0,	0},
-	{"COMP"                        ,	16,	8,	1014,	"R/W",	0,	0,	128ull,	128ull},
-	{"MBOX"                        ,	24,	4,	1014,	"R/W",	0,	0,	8ull,	8ull},
-	{"RESERVED_28_63"              ,	28,	36,	1014,	"RAZ",	1,	1,	0,	0},
-	{"PRIORITY"                    ,	0,	2,	1015,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_2"                ,	2,	1,	1015,	"RAZ",	1,	1,	0,	0},
-	{"ID16"                        ,	3,	1,	1015,	"R/W",	0,	0,	0ull,	0ull},
-	{"SRC_ID"                      ,	4,	1,	1015,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_7"                ,	5,	3,	1015,	"RAZ",	1,	1,	0,	0},
-	{"PENDING"                     ,	8,	1,	1015,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_9_15"               ,	9,	7,	1015,	"RAZ",	1,	1,	0,	0},
-	{"DEST_ID"                     ,	16,	16,	1015,	"R/W",	0,	0,	0ull,	0ull},
-	{"DATA"                        ,	32,	16,	1015,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	1015,	"RAZ",	1,	1,	0,	0},
-	{"PRIORITY"                    ,	0,	2,	1016,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_2"                ,	2,	1,	1016,	"RAZ",	1,	1,	0,	0},
-	{"ID16"                        ,	3,	1,	1016,	"RO",	0,	0,	0ull,	0ull},
-	{"SRC_ID"                      ,	4,	1,	1016,	"RO",	0,	0,	0ull,	0ull},
-	{"RETRY"                       ,	5,	1,	1016,	"RO",	0,	0,	0ull,	0ull},
-	{"ERROR"                       ,	6,	1,	1016,	"RO",	0,	0,	0ull,	0ull},
-	{"TIMEOUT"                     ,	7,	1,	1016,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_8_15"               ,	8,	8,	1016,	"RAZ",	1,	1,	0,	0},
-	{"DEST_ID"                     ,	16,	16,	1016,	"RO",	0,	0,	0ull,	0ull},
-	{"DATA"                        ,	32,	16,	1016,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	1016,	"RAZ",	1,	1,	0,	0},
-	{"TX_TH0"                      ,	0,	4,	1017,	"R/W",	0,	0,	6ull,	3ull},
-	{"RESERVED_4_7"                ,	4,	4,	1017,	"RAZ",	1,	1,	0,	0},
-	{"TX_TH1"                      ,	8,	4,	1017,	"R/W",	0,	0,	4ull,	2ull},
-	{"RESERVED_12_15"              ,	12,	4,	1017,	"RAZ",	1,	1,	0,	0},
-	{"TX_TH2"                      ,	16,	4,	1017,	"R/W",	0,	0,	2ull,	1ull},
-	{"RESERVED_20_31"              ,	20,	12,	1017,	"RAZ",	1,	1,	0,	0},
-	{"TAG_TH0"                     ,	32,	5,	1017,	"R/W",	0,	0,	3ull,	3ull},
-	{"RESERVED_37_39"              ,	37,	3,	1017,	"RAZ",	1,	1,	0,	0},
-	{"TAG_TH1"                     ,	40,	5,	1017,	"R/W",	0,	0,	2ull,	2ull},
-	{"RESERVED_45_47"              ,	45,	3,	1017,	"RAZ",	1,	1,	0,	0},
-	{"TAG_TH2"                     ,	48,	5,	1017,	"R/W",	0,	0,	1ull,	1ull},
-	{"RESERVED_53_63"              ,	53,	11,	1017,	"RAZ",	1,	1,	0,	0},
-	{"S2M_PR0"                     ,	0,	8,	1018,	"RO",	0,	1,	0ull,	0},
-	{"S2M_PR1"                     ,	8,	8,	1018,	"RO",	0,	1,	0ull,	0},
-	{"S2M_PR2"                     ,	16,	8,	1018,	"RO",	0,	1,	0ull,	0},
-	{"S2M_PR3"                     ,	24,	8,	1018,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	1018,	"RAZ",	1,	1,	0,	0},
-	{"ASSY_VEN"                    ,	0,	16,	1019,	"RO",	0,	0,	140ull,	0ull},
-	{"ASSY_ID"                     ,	16,	16,	1019,	"RO",	0,	0,	0ull,	0ull},
-	{"EXT_FPTR"                    ,	0,	16,	1020,	"RO",	0,	0,	256ull,	256ull},
-	{"ASSY_REV"                    ,	16,	16,	1020,	"RO",	0,	0,	0ull,	0ull},
-	{"ENABLE"                      ,	0,	1,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_1_2"                ,	1,	2,	1021,	"RAZ",	1,	1,	0,	0},
-	{"NCA"                         ,	3,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
-	{"ES"                          ,	4,	2,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_6_7"                ,	6,	2,	1021,	"RAZ",	1,	1,	0,	0},
-	{"LA"                          ,	8,	22,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_30_31"              ,	30,	2,	1021,	"RAZ",	1,	1,	0,	0},
-	{"FULL"                        ,	0,	1,	1022,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_31"               ,	1,	31,	1022,	"RAZ",	1,	1,	0,	0},
-	{"COMP_TAG"                    ,	0,	32,	1023,	"R/W",	0,	0,	0ull,	0ull},
-	{"MEMORY"                      ,	0,	1,	1024,	"R/W",	0,	0,	0ull,	1ull},
-	{"DOORBELL"                    ,	1,	1,	1024,	"R/W",	0,	0,	0ull,	1ull},
-	{"IMSG0"                       ,	2,	1,	1024,	"R/W",	0,	0,	0ull,	1ull},
-	{"IMSG1"                       ,	3,	1,	1024,	"R/W",	0,	0,	0ull,	1ull},
-	{"HALT"                        ,	4,	1,	1024,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_31"               ,	5,	27,	1024,	"RAZ",	1,	1,	0,	0},
-	{"VENDOR"                      ,	0,	16,	1025,	"RO",	0,	0,	140ull,	140ull},
-	{"DEVICE"                      ,	16,	16,	1025,	"RO",	0,	1,	144ull,	0},
-	{"REVISION"                    ,	0,	8,	1026,	"RO",	1,	1,	0,	0},
-	{"RESERVED_8_31"               ,	8,	24,	1026,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_1"                ,	0,	2,	1027,	"RAZ",	1,	1,	0,	0},
-	{"PORT_WR"                     ,	2,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
-	{"ATOM_SWP"                    ,	3,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
-	{"ATOM_CLR"                    ,	4,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
-	{"ATOM_SET"                    ,	5,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
-	{"ATOM_DEC"                    ,	6,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
-	{"ATOM_INC"                    ,	7,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
-	{"TESTSWAP"                    ,	8,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
-	{"COMPSWAP"                    ,	9,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
-	{"DOORBELL"                    ,	10,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
-	{"MSG"                         ,	11,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
-	{"WRITE_R"                     ,	12,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
-	{"SWRITE"                      ,	13,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
-	{"WRITE"                       ,	14,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
-	{"READ"                        ,	15,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
-	{"RESERVED_16_21"              ,	16,	6,	1027,	"RAZ",	1,	1,	0,	0},
-	{"TLB_INVS"                    ,	22,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
-	{"TLB_INV"                     ,	23,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
-	{"I_INVALD"                    ,	24,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
-	{"IO_READ"                     ,	25,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
-	{"D_FLUSH"                     ,	26,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
-	{"CASTOUT"                     ,	27,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
-	{"D_INVALD"                    ,	28,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
-	{"RD_OWN"                      ,	29,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
-	{"I_READ"                      ,	30,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
-	{"GSM_READ"                    ,	31,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
-	{"VALID"                       ,	0,	1,	1028,	"R/W0C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_23"               ,	1,	23,	1028,	"RAZ",	1,	1,	0,	0},
-	{"ERR_TYPE"                    ,	24,	5,	1028,	"R/W",	0,	0,	0ull,	0ull},
-	{"INF_TYPE"                    ,	29,	3,	1028,	"R/W",	0,	0,	0ull,	0ull},
-	{"LNK_TOUT"                    ,	0,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
-	{"UNS_ACK"                     ,	1,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
-	{"DEL_ERR"                     ,	2,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
-	{"F_TOGGLE"                    ,	3,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
-	{"PROTERR"                     ,	4,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
-	{"BAD_ACK"                     ,	5,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_16"               ,	6,	11,	1029,	"RAZ",	1,	1,	0,	0},
-	{"SIZE"                        ,	17,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKT_CRC"                     ,	18,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
-	{"OUT_ACK"                     ,	19,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
-	{"NACK"                        ,	20,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
-	{"UNS_ID"                      ,	21,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
-	{"CTL_CRC"                     ,	22,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_31"              ,	23,	9,	1029,	"R/W",	0,	0,	0ull,	0ull},
-	{"RATE_CNT"                    ,	0,	8,	1030,	"R/W",	0,	1,	0ull,	0},
-	{"PK_RATE"                     ,	8,	8,	1030,	"R/W",	0,	1,	0ull,	0},
-	{"RATE_LIM"                    ,	16,	2,	1030,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_18_23"              ,	18,	6,	1030,	"RAZ",	1,	1,	0,	0},
-	{"ERR_BIAS"                    ,	24,	8,	1030,	"R/W",	0,	0,	128ull,	128ull},
-	{"LNK_TOUT"                    ,	0,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
-	{"UNS_ACK"                     ,	1,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
-	{"DEL_ERR"                     ,	2,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
-	{"F_TOGGLE"                    ,	3,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
-	{"PROTERR"                     ,	4,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
-	{"BAD_ACK"                     ,	5,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_16"               ,	6,	11,	1031,	"RAZ",	1,	1,	0,	0},
-	{"SIZE"                        ,	17,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKT_CRC"                     ,	18,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
-	{"OUT_ACK"                     ,	19,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
-	{"NACK"                        ,	20,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
-	{"UNS_ID"                      ,	21,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
-	{"CTL_CRC"                     ,	22,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_31"              ,	23,	9,	1031,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_15"               ,	0,	16,	1032,	"RAZ",	1,	1,	0,	0},
-	{"DGRAD_TH"                    ,	16,	8,	1032,	"R/W",	0,	0,	255ull,	128ull},
-	{"FAIL_TH"                     ,	24,	8,	1032,	"R/W",	0,	0,	255ull,	255ull},
-	{"EF_ID"                       ,	0,	16,	1033,	"RO",	0,	0,	7ull,	7ull},
-	{"EF_PTR"                      ,	16,	16,	1033,	"RO",	0,	0,	0ull,	0ull},
-	{"ADDR"                        ,	0,	32,	1034,	"R/W",	0,	0,	0ull,	0ull},
-	{"XADDR"                       ,	0,	2,	1035,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_2"                ,	2,	1,	1035,	"RAZ",	1,	1,	0,	0},
-	{"ADDR"                        ,	3,	29,	1035,	"R/W",	0,	0,	0ull,	0ull},
-	{"CAPT_IDX"                    ,	0,	5,	1036,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_5"                ,	5,	1,	1036,	"R/W",	0,	0,	0ull,	0ull},
-	{"WDPTR"                       ,	6,	1,	1036,	"R/W",	0,	0,	0ull,	0ull},
-	{"TT"                          ,	7,	1,	1036,	"R/W",	0,	0,	0ull,	0ull},
-	{"SIZE"                        ,	8,	4,	1036,	"R/W",	0,	0,	0ull,	0ull},
-	{"STATUS"                      ,	12,	4,	1036,	"R/W",	0,	0,	0ull,	0ull},
-	{"EXTRA"                       ,	16,	8,	1036,	"R/W",	0,	0,	0ull,	0ull},
-	{"TTYPE"                       ,	24,	4,	1036,	"R/W",	0,	0,	0ull,	0ull},
-	{"FTYPE"                       ,	28,	4,	1036,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_14"               ,	0,	15,	1037,	"RAZ",	1,	1,	0,	0},
-	{"TT"                          ,	15,	1,	1037,	"R/W",	0,	0,	0ull,	0ull},
-	{"ID8"                         ,	16,	8,	1037,	"R/W",	0,	0,	0ull,	0ull},
-	{"ID16"                        ,	24,	8,	1037,	"R/W",	0,	0,	0ull,	0ull},
-	{"SRC_ID8"                     ,	0,	8,	1038,	"R/W",	0,	0,	0ull,	0ull},
-	{"SRC_ID16"                    ,	8,	8,	1038,	"R/W",	0,	0,	0ull,	0ull},
-	{"DST_ID8"                     ,	16,	8,	1038,	"R/W",	0,	0,	0ull,	0ull},
-	{"DST_ID16"                    ,	24,	8,	1038,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESP_SZ"                     ,	0,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_21"               ,	1,	21,	1039,	"R/W",	0,	0,	0ull,	0ull},
-	{"UNS_TRAN"                    ,	22,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
-	{"UNS_RESP"                    ,	23,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKT_TOUT"                    ,	24,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
-	{"MSG_TOUT"                    ,	25,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
-	{"ILL_TGT"                     ,	26,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
-	{"ILL_TRAN"                    ,	27,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
-	{"MSG_FMT"                     ,	28,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
-	{"GSM_ERR"                     ,	29,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
-	{"MSG_ERR"                     ,	30,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
-	{"IO_ERR"                      ,	31,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESP_SZ"                     ,	0,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_21"               ,	1,	21,	1040,	"R/W",	0,	0,	0ull,	0ull},
-	{"UNS_TRAN"                    ,	22,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
-	{"UNS_RESP"                    ,	23,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKT_TOUT"                    ,	24,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
-	{"MSG_TOUT"                    ,	25,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
-	{"ILL_TGT"                     ,	26,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
-	{"ILL_TRAN"                    ,	27,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
-	{"MSG_FMT"                     ,	28,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
-	{"GSM_ERR"                     ,	29,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
-	{"MSG_ERR"                     ,	30,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
-	{"IO_ERR"                      ,	31,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
-	{"CAPTURE"                     ,	0,	32,	1041,	"R/W",	0,	0,	0ull,	0ull},
-	{"CAPTURE"                     ,	0,	32,	1042,	"R/W",	0,	0,	0ull,	0ull},
-	{"CAPTURE"                     ,	0,	32,	1043,	"R/W",	0,	0,	0ull,	0ull},
-	{"CAPTURE"                     ,	0,	32,	1044,	"R/W",	0,	0,	0ull,	0ull},
-	{"HOSTID"                      ,	0,	16,	1045,	"R/W",	0,	0,	65535ull,	0ull},
-	{"RESERVED_16_31"              ,	16,	16,	1045,	"RAZ",	1,	1,	0,	0},
-	{"RX_SYNC"                     ,	0,	1,	1046,	"R/W",	0,	0,	0ull,	0ull},
-	{"TX_SYNC"                     ,	1,	1,	1046,	"R/W",	0,	0,	0ull,	0ull},
-	{"TX_FLOW"                     ,	2,	1,	1046,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_19"               ,	3,	17,	1046,	"R/W",	0,	0,	0ull,	0ull},
-	{"TX_WM2"                      ,	20,	4,	1046,	"R/W",	0,	0,	2ull,	1ull},
-	{"TX_WM1"                      ,	24,	4,	1046,	"R/W",	0,	0,	3ull,	2ull},
-	{"TX_WM0"                      ,	28,	4,	1046,	"R/W",	0,	0,	4ull,	3ull},
-	{"PD_CTRL"                     ,	0,	32,	1047,	"R/W",	0,	0,	0ull,	0ull},
-	{"LN0_DIS"                     ,	0,	1,	1048,	"RO",	0,	0,	0ull,	0ull},
-	{"LN0_RX"                      ,	1,	3,	1048,	"RO",	0,	0,	0ull,	0ull},
-	{"LN1_DIS"                     ,	4,	1,	1048,	"RO",	0,	0,	0ull,	0ull},
-	{"LN1_RX"                      ,	5,	3,	1048,	"RO",	0,	0,	0ull,	0ull},
-	{"LN2_DIS"                     ,	8,	1,	1048,	"RO",	0,	0,	0ull,	0ull},
-	{"LN2_RX"                      ,	9,	3,	1048,	"RO",	0,	0,	0ull,	0ull},
-	{"LN3_DIS"                     ,	12,	1,	1048,	"RO",	0,	0,	0ull,	0ull},
-	{"LN3_RX"                      ,	13,	3,	1048,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_31"              ,	16,	16,	1048,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_26"               ,	0,	27,	1049,	"RAZ",	1,	1,	0,	0},
-	{"LOOPBACK"                    ,	27,	2,	1049,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_29_29"              ,	29,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
-	{"RX_RESET"                    ,	30,	1,	1049,	"R/W",	0,	0,	1ull,	1ull},
-	{"TX_RESET"                    ,	31,	1,	1049,	"R/W",	0,	0,	1ull,	1ull},
-	{"INIT_SM"                     ,	0,	10,	1050,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_31"              ,	10,	22,	1050,	"RAZ",	1,	1,	0,	0},
-	{"OVERWRT"                     ,	0,	1,	1051,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_31"               ,	1,	31,	1051,	"RAZ",	1,	1,	0,	0},
-	{"PKT_DATA"                    ,	0,	32,	1052,	"RO",	0,	0,	0ull,	0ull},
-	{"FIFO_ST"                     ,	0,	4,	1053,	"RO",	0,	0,	0ull,	0ull},
-	{"FULL"                        ,	4,	1,	1053,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_11"               ,	5,	7,	1053,	"RAZ",	1,	1,	0,	0},
-	{"BUFFERS"                     ,	12,	4,	1053,	"RO",	0,	0,	0ull,	0ull},
-	{"OCTETS"                      ,	16,	16,	1053,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_15"               ,	0,	16,	1054,	"RAZ",	1,	1,	0,	0},
-	{"OCTETS"                      ,	16,	16,	1054,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKT_DATA"                    ,	0,	32,	1055,	"R/W",	0,	0,	0ull,	0ull},
-	{"FIFO_ST"                     ,	0,	4,	1056,	"RO",	0,	0,	0ull,	0ull},
-	{"FULL"                        ,	4,	1,	1056,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_11"               ,	5,	7,	1056,	"RAZ",	1,	1,	0,	0},
-	{"BUFFERS"                     ,	12,	4,	1056,	"RO",	0,	0,	0ull,	0ull},
-	{"OCTETS"                      ,	16,	16,	1056,	"RO",	0,	0,	0ull,	0ull},
-	{"STATUSN"                     ,	0,	3,	1057,	"RO",	0,	0,	0ull,	0ull},
-	{"STATUS1"                     ,	3,	1,	1057,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_5"                ,	4,	2,	1057,	"RAZ",	1,	1,	0,	0},
-	{"XTRAIN"                      ,	6,	1,	1057,	"RO",	0,	0,	0ull,	0ull},
-	{"XSYNC"                       ,	7,	1,	1057,	"RO",	0,	0,	0ull,	0ull},
-	{"DEC_ERR"                     ,	8,	4,	1057,	"RO",	0,	0,	0ull,	0ull},
-	{"RX_TRAIN"                    ,	12,	1,	1057,	"RO",	0,	0,	0ull,	0ull},
-	{"RX_SYNC"                     ,	13,	1,	1057,	"RO",	0,	0,	0ull,	0ull},
-	{"RX_ADAPT"                    ,	14,	1,	1057,	"RO",	0,	0,	1ull,	1ull},
-	{"RX_INV"                      ,	15,	1,	1057,	"RO",	0,	0,	0ull,	0ull},
-	{"RX_TYPE"                     ,	16,	2,	1057,	"RO",	0,	0,	0ull,	0ull},
-	{"TX_MODE"                     ,	18,	1,	1057,	"RO",	0,	0,	0ull,	0ull},
-	{"TX_TYPE"                     ,	19,	1,	1057,	"RO",	0,	0,	0ull,	0ull},
-	{"LANE"                        ,	20,	4,	1057,	"RO",	0,	0,	0ull,	0ull},
-	{"PORT"                        ,	24,	8,	1057,	"RO",	0,	0,	0ull,	0ull},
-	{"LCSBA"                       ,	0,	31,	1058,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_31_31"              ,	31,	1,	1058,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_20"               ,	0,	21,	1059,	"R/W",	0,	0,	0ull,	0ull},
-	{"LCSBA"                       ,	21,	11,	1059,	"R/W",	0,	0,	0ull,	0ull},
-	{"ADDR48"                      ,	0,	16,	1060,	"R/W",	0,	0,	0ull,	0ull},
-	{"ADDR64"                      ,	16,	16,	1060,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENABLE"                      ,	0,	1,	1061,	"R/W",	0,	0,	0ull,	0ull},
-	{"ADDR66"                      ,	1,	2,	1061,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_13"               ,	3,	11,	1061,	"RAZ",	1,	1,	0,	0},
-	{"ADDR32"                      ,	14,	18,	1061,	"R/W",	0,	0,	0ull,	0ull},
-	{"ADDR48"                      ,	0,	16,	1062,	"R/W",	0,	0,	0ull,	0ull},
-	{"ADDR64"                      ,	16,	16,	1062,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENABLE"                      ,	0,	1,	1063,	"R/W",	0,	0,	0ull,	0ull},
-	{"ADDR66"                      ,	1,	2,	1063,	"R/W",	0,	0,	0ull,	0ull},
-	{"BARSIZE"                     ,	3,	3,	1063,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_19"               ,	6,	14,	1063,	"RAZ",	1,	1,	0,	0},
-	{"ADDR32"                      ,	20,	12,	1063,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENABLE"                      ,	0,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
-	{"ADDR66"                      ,	1,	2,	1064,	"R/W",	0,	0,	0ull,	0ull},
-	{"CAX"                         ,	3,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
-	{"ESX"                         ,	4,	2,	1064,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_8"                ,	6,	3,	1064,	"RAZ",	1,	1,	0,	0},
-	{"ADDR48"                      ,	9,	7,	1064,	"R/W",	0,	0,	0ull,	0ull},
-	{"ADDR64"                      ,	16,	16,	1064,	"R/W",	0,	0,	0ull,	0ull},
-	{"EX_ADDR"                     ,	0,	3,	1065,	"RO",	0,	0,	7ull,	7ull},
-	{"EX_FEAT"                     ,	3,	1,	1065,	"RO",	0,	0,	1ull,	1ull},
-	{"LG_TRAN"                     ,	4,	1,	1065,	"RO",	0,	0,	1ull,	1ull},
-	{"CRF"                         ,	5,	1,	1065,	"RO",	0,	0,	0ull,	0ull},
-	{"SUPPRESS"                    ,	6,	1,	1065,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_7_26"               ,	7,	20,	1065,	"RAZ",	1,	1,	0,	0},
-	{"MULT_PRT"                    ,	27,	1,	1065,	"RO",	0,	0,	0ull,	0ull},
-	{"SWITCHF"                     ,	28,	1,	1065,	"RO",	0,	0,	0ull,	0ull},
-	{"PROC"                        ,	29,	1,	1065,	"RO",	0,	0,	1ull,	1ull},
-	{"MEMORY"                      ,	30,	1,	1065,	"RO",	0,	0,	1ull,	1ull},
-	{"BRIDGE"                      ,	31,	1,	1065,	"RO",	0,	0,	0ull,	0ull},
-	{"EX_ADDR"                     ,	0,	3,	1066,	"R/W",	0,	0,	1ull,	1ull},
-	{"RESERVED_3_31"               ,	3,	29,	1066,	"RAZ",	1,	1,	0,	0},
-	{"PT_TYPE"                     ,	0,	1,	1067,	"RO",	0,	0,	1ull,	1ull},
-	{"PRT_LOCK"                    ,	1,	1,	1067,	"R/W",	0,	0,	0ull,	0ull},
-	{"DROP_PKT"                    ,	2,	1,	1067,	"R/W",	0,	0,	0ull,	0ull},
-	{"STP_PORT"                    ,	3,	1,	1067,	"R/W",	0,	0,	0ull,	0ull},
-	{"SUPPRESS"                    ,	4,	8,	1067,	"RO",	0,	0,	0ull,	0ull},
-	{"EX_STAT"                     ,	12,	2,	1067,	"RO",	0,	0,	0ull,	0ull},
-	{"EX_WIDTH"                    ,	14,	2,	1067,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_16"              ,	16,	1,	1067,	"RAZ",	1,	1,	0,	0},
-	{"ENUMB"                       ,	17,	1,	1067,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_18_18"              ,	18,	1,	1067,	"RAZ",	1,	1,	0,	0},
-	{"MCAST"                       ,	19,	1,	1067,	"R/W",	0,	0,	0ull,	0ull},
-	{"DIS_ERR"                     ,	20,	1,	1067,	"R/W",	0,	0,	0ull,	0ull},
-	{"I_ENABLE"                    ,	21,	1,	1067,	"R/W",	0,	0,	0ull,	1ull},
-	{"O_ENABLE"                    ,	22,	1,	1067,	"R/W",	0,	0,	0ull,	1ull},
-	{"DISABLE"                     ,	23,	1,	1067,	"R/W",	0,	0,	0ull,	0ull},
-	{"OV_WIDTH"                    ,	24,	3,	1067,	"R/W",	0,	0,	0ull,	0ull},
-	{"IT_WIDTH"                    ,	27,	3,	1067,	"RO",	0,	1,	0ull,	0},
-	{"PT_WIDTH"                    ,	30,	2,	1067,	"RO",	0,	0,	2ull,	2ull},
-	{"EMPH_EN"                     ,	0,	1,	1068,	"R/W",	0,	0,	0ull,	0ull},
-	{"TX_EMPH"                     ,	1,	1,	1068,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_15"               ,	2,	14,	1068,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENB_625G"                    ,	16,	1,	1068,	"R/W",	0,	0,	0ull,	0ull},
-	{"SUP_625G"                    ,	17,	1,	1068,	"RO",	0,	0,	0ull,	0ull},
-	{"ENB_500G"                    ,	18,	1,	1068,	"R/W",	1,	1,	0,	0},
-	{"SUB_500G"                    ,	19,	1,	1068,	"RO",	1,	1,	0,	0},
-	{"ENB_312G"                    ,	20,	1,	1068,	"R/W",	1,	1,	0,	0},
-	{"SUP_312G"                    ,	21,	1,	1068,	"RO",	1,	1,	0,	0},
-	{"ENB_250G"                    ,	22,	1,	1068,	"R/W",	1,	1,	0,	0},
-	{"SUP_250G"                    ,	23,	1,	1068,	"RO",	1,	1,	0,	0},
-	{"ENB_125G"                    ,	24,	1,	1068,	"R/W",	1,	1,	0,	0},
-	{"SUP_125G"                    ,	25,	1,	1068,	"RO",	1,	1,	0,	0},
-	{"BAUD_ENB"                    ,	26,	1,	1068,	"R/W",	0,	0,	0ull,	0ull},
-	{"BAUD_SUP"                    ,	27,	1,	1068,	"RO",	0,	0,	0ull,	0ull},
-	{"SEL_BAUD"                    ,	28,	4,	1068,	"RO",	0,	1,	0ull,	0},
-	{"PT_UINIT"                    ,	0,	1,	1069,	"RO",	0,	0,	0ull,	0ull},
-	{"PT_OK"                       ,	1,	1,	1069,	"RO",	0,	0,	0ull,	0ull},
-	{"PT_ERROR"                    ,	2,	1,	1069,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_3"                ,	3,	1,	1069,	"RAZ",	1,	1,	0,	0},
-	{"PT_WRITE"                    ,	4,	1,	1069,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_7"                ,	5,	3,	1069,	"RAZ",	1,	1,	0,	0},
-	{"I_SM_ERR"                    ,	8,	1,	1069,	"RO",	0,	0,	0ull,	0ull},
-	{"I_ERROR"                     ,	9,	1,	1069,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"I_SM_RET"                    ,	10,	1,	1069,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_11_15"              ,	11,	5,	1069,	"RAZ",	1,	1,	0,	0},
-	{"O_SM_ERR"                    ,	16,	1,	1069,	"RO",	0,	0,	0ull,	0ull},
-	{"O_ERROR"                     ,	17,	1,	1069,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"O_SM_RET"                    ,	18,	1,	1069,	"RO",	0,	0,	0ull,	0ull},
-	{"O_RTRIED"                    ,	19,	1,	1069,	"RO",	0,	0,	0ull,	0ull},
-	{"O_RETRY"                     ,	20,	1,	1069,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_21_23"              ,	21,	3,	1069,	"RAZ",	1,	1,	0,	0},
-	{"O_DGRAD"                     ,	24,	1,	1069,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"O_FAIL"                      ,	25,	1,	1069,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PKT_DROP"                    ,	26,	1,	1069,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_27_31"              ,	27,	5,	1069,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_28"               ,	0,	29,	1070,	"RAZ",	1,	1,	0,	0},
-	{"DISCOVER"                    ,	29,	1,	1070,	"R/W",	0,	0,	0ull,	1ull},
-	{"MENABLE"                     ,	30,	1,	1070,	"R/W",	1,	0,	0,	1ull},
-	{"HOST"                        ,	31,	1,	1070,	"R/W",	1,	1,	0,	0},
-	{"RESERVED_0_7"                ,	0,	8,	1071,	"RAZ",	1,	1,	0,	0},
-	{"TIMEOUT"                     ,	8,	24,	1071,	"R/W",	0,	0,	16777215ull,	0ull},
-	{"EF_ID"                       ,	0,	16,	1072,	"RO",	0,	0,	1ull,	0ull},
-	{"EF_PTR"                      ,	16,	16,	1072,	"RO",	0,	0,	4096ull,	0ull},
-	{"RESERVED_0_7"                ,	0,	8,	1073,	"RAZ",	1,	1,	0,	0},
-	{"TIMEOUT"                     ,	8,	24,	1073,	"R/W",	0,	0,	16777215ull,	0ull},
-	{"ID16"                        ,	0,	16,	1074,	"R/W",	0,	0,	65535ull,	0ull},
-	{"ID8"                         ,	16,	8,	1074,	"R/W",	0,	0,	255ull,	0ull},
-	{"RESERVED_24_31"              ,	24,	8,	1074,	"RAZ",	1,	1,	0,	0},
-	{"ENABLE16"                    ,	0,	1,	1075,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENABLE8"                     ,	1,	1,	1075,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_31"               ,	2,	30,	1075,	"RAZ",	1,	1,	0,	0},
-	{"ID16"                        ,	0,	16,	1076,	"R/W",	0,	0,	65535ull,	0ull},
-	{"ID8"                         ,	16,	8,	1076,	"R/W",	0,	0,	255ull,	0ull},
-	{"RESERVED_24_31"              ,	24,	8,	1076,	"RAZ",	1,	1,	0,	0},
-	{"EF_ID"                       ,	0,	16,	1077,	"RO",	0,	0,	13ull,	13ull},
-	{"EF_PTR"                      ,	16,	16,	1077,	"RO",	0,	0,	8192ull,	0ull},
-	{"RESERVED_0_1"                ,	0,	2,	1078,	"RAZ",	1,	1,	0,	0},
-	{"PORT_WR"                     ,	2,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
-	{"ATOM_SWP"                    ,	3,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
-	{"ATOM_CLR"                    ,	4,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
-	{"ATOM_SET"                    ,	5,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
-	{"ATOM_DEC"                    ,	6,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
-	{"ATOM_INC"                    ,	7,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
-	{"TESTSWAP"                    ,	8,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
-	{"COMPSWAP"                    ,	9,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
-	{"DOORBELL"                    ,	10,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
-	{"MSG"                         ,	11,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
-	{"WRITE_R"                     ,	12,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
-	{"SWRITE"                      ,	13,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
-	{"WRITE"                       ,	14,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
-	{"READ"                        ,	15,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
-	{"RESERVED_16_21"              ,	16,	6,	1078,	"RAZ",	1,	1,	0,	0},
-	{"TLB_INVS"                    ,	22,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
-	{"TLB_INV"                     ,	23,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
-	{"I_INVALD"                    ,	24,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
-	{"IO_READ"                     ,	25,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
-	{"D_FLUSH"                     ,	26,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
-	{"CASTOUT"                     ,	27,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
-	{"D_INVALD"                    ,	28,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
-	{"RD_OWN"                      ,	29,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
-	{"I_READ"                      ,	30,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
-	{"GSM_READ"                    ,	31,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
-	{"INTERVAL"                    ,	0,	22,	1079,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	1079,	"RAZ",	1,	1,	0,	0},
-	{"COUNT"                       ,	24,	22,	1079,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_46_46"              ,	46,	1,	1079,	"RAZ",	1,	1,	0,	0},
-	{"ENA"                         ,	47,	1,	1079,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	1079,	"RAZ",	1,	1,	0,	0},
-	{"BSIZE"                       ,	0,	20,	1080,	"RO",	1,	0,	0,	0ull},
-	{"BASE"                        ,	20,	31,	1080,	"RO",	1,	0,	0,	0ull},
-	{"BUCKET"                      ,	51,	13,	1080,	"RO",	1,	0,	0,	0ull},
-	{"BUCKET"                      ,	0,	7,	1081,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_7_7"                ,	7,	1,	1081,	"RO",	1,	0,	0,	0ull},
-	{"CSIZE"                       ,	8,	13,	1081,	"RO",	1,	0,	0,	0ull},
-	{"CPOOL"                       ,	21,	3,	1081,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_24_63"              ,	24,	40,	1081,	"RAZ",	1,	1,	0,	0},
-	{"RING"                        ,	0,	4,	1082,	"R/W",	0,	0,	0ull,	0ull},
-	{"NUM_BUCKETS"                 ,	4,	20,	1082,	"R/W",	0,	0,	0ull,	0ull},
-	{"FIRST_BUCKET"                ,	24,	31,	1082,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_55_63"              ,	55,	9,	1082,	"RAZ",	1,	1,	0,	0},
-	{"RING"                        ,	0,	4,	1083,	"R/W",	0,	0,	0ull,	0ull},
-	{"INTERVAL"                    ,	4,	22,	1083,	"R/W",	0,	0,	0ull,	0ull},
-	{"WORDS_PER_CHUNK"             ,	26,	13,	1083,	"R/W",	0,	0,	0ull,	0ull},
-	{"POOL"                        ,	39,	3,	1083,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENABLE"                      ,	42,	1,	1083,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_43_63"              ,	43,	21,	1083,	"RAZ",	1,	1,	0,	0},
-	{"CTL"                         ,	0,	1,	1084,	"RO",	1,	0,	0,	0ull},
-	{"NCB"                         ,	1,	1,	1084,	"RO",	1,	0,	0,	0ull},
-	{"STA"                         ,	2,	2,	1084,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	1084,	"RAZ",	1,	1,	0,	0},
-	{"MASK"                        ,	0,	16,	1085,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	1085,	"RAZ",	1,	1,	0,	0},
-	{"ENABLE_TIMERS"               ,	0,	1,	1086,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENABLE_DWB"                  ,	1,	1,	1086,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESET"                       ,	2,	1,	1086,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	1086,	"RAZ",	1,	1,	0,	0},
-	{"MASK"                        ,	0,	16,	1087,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	1087,	"RAZ",	1,	1,	0,	0},
-	{"INDEX"                       ,	0,	8,	1088,	"R/W",	0,	0,	0ull,	0ull},
-	{"INC"                         ,	8,	8,	1088,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	1088,	"RAZ",	1,	1,	0,	0},
-	{"TDF"                         ,	0,	1,	1089,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	1089,	"RAZ",	0,	0,	0ull,	0ull},
-	{"ENA"                         ,	0,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
-	{"WRAP"                        ,	1,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
-	{"TRIG_CTL"                    ,	2,	2,	1090,	"R/W",	0,	0,	0ull,	0ull},
-	{"TIME_GRN"                    ,	4,	3,	1090,	"R/W",	0,	0,	0ull,	0ull},
-	{"FULL_THR"                    ,	7,	2,	1090,	"R/W",	0,	0,	0ull,	0ull},
-	{"CIU_TRG"                     ,	9,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
-	{"CIU_THR"                     ,	10,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
-	{"MCD0_TRG"                    ,	11,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
-	{"MCD0_THR"                    ,	12,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
-	{"MCD0_ENA"                    ,	13,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
-	{"IGNORE_O"                    ,	14,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
-	{"CLKALWAYS"                   ,	15,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	1090,	"RAZ",	0,	0,	0ull,	0ull},
-	{"WPTR"                        ,	0,	8,	1091,	"RO",	0,	0,	0ull,	0ull},
-	{"RPTR"                        ,	8,	8,	1091,	"RO",	0,	0,	0ull,	0ull},
-	{"CYCLES"                      ,	16,	48,	1091,	"RO",	0,	0,	0ull,	0ull},
-	{"WPTR"                        ,	0,	10,	1092,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_11"              ,	10,	2,	1092,	"RAZ",	1,	1,	0,	0},
-	{"RPTR"                        ,	12,	10,	1092,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	1092,	"RAZ",	1,	1,	0,	0},
-	{"CYCLES"                      ,	24,	40,	1092,	"RO",	0,	0,	0ull,	0ull},
-	{"ADR"                         ,	0,	38,	1093,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_38_63"              ,	38,	26,	1093,	"RAZ",	0,	0,	0ull,	0ull},
-	{"ADR"                         ,	0,	38,	1094,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_38_63"              ,	38,	26,	1094,	"RAZ",	0,	0,	0ull,	0ull},
-	{"NOP"                         ,	0,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"LDT"                         ,	1,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"LDI"                         ,	2,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"PL2"                         ,	3,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"RPL2"                        ,	4,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"DWB"                         ,	5,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_7"                ,	6,	2,	1095,	"R/W",	0,	0,	0ull,	0ull},
-	{"LDD"                         ,	8,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"PSL1"                        ,	9,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_10_14"              ,	10,	5,	1095,	"R/W",	0,	0,	0ull,	0ull},
-	{"IOBDMA"                      ,	15,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"STF"                         ,	16,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"STT"                         ,	17,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"STP"                         ,	18,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"STC"                         ,	19,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"STFIL1"                      ,	20,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"STTIL1"                      ,	21,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAS32"                       ,	22,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAS64"                       ,	23,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"WBIL2I"                      ,	24,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"LTGL2I"                      ,	25,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"STGL2I"                      ,	26,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_27_27"              ,	27,	1,	1095,	"R/W",	0,	0,	0ull,	0ull},
-	{"INVL2"                       ,	28,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"WBIL2"                       ,	29,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"WBL2"                        ,	30,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"LCKL2"                       ,	31,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD8"                      ,	32,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD16"                     ,	33,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD32"                     ,	34,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD64"                     ,	35,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST8"                      ,	36,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST16"                     ,	37,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST32"                     ,	38,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST64"                     ,	39,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET8"                        ,	40,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET16"                       ,	41,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET32"                       ,	42,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET64"                       ,	43,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR8"                        ,	44,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR16"                       ,	45,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR32"                       ,	46,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR64"                       ,	47,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR8"                       ,	48,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR16"                      ,	49,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR32"                      ,	50,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR64"                      ,	51,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR8"                       ,	52,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR16"                      ,	53,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR32"                      ,	54,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR64"                      ,	55,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_56_57"              ,	56,	2,	1095,	"R/W",	0,	0,	0ull,	0ull},
-	{"FAA32"                       ,	58,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAA64"                       ,	59,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_60_61"              ,	60,	2,	1095,	"R/W",	0,	0,	0ull,	0ull},
-	{"SAA32"                       ,	62,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"SAA64"                       ,	63,	1,	1095,	"R/W",	0,	0,	0ull,	1ull},
-	{"MIO"                         ,	0,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL3"                    ,	1,	2,	1096,	"R/W",	0,	0,	0ull,	3ull},
-	{"SLI"                         ,	3,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
-	{"KEY"                         ,	4,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
-	{"FPA"                         ,	5,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
-	{"DFA"                         ,	6,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
-	{"ZIP"                         ,	7,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
-	{"RNG"                         ,	8,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
-	{"IPD"                         ,	9,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
-	{"PKO"                         ,	10,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL2"                    ,	11,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
-	{"POW"                         ,	12,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
-	{"USB0"                        ,	13,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
-	{"RAD"                         ,	14,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL"                     ,	15,	12,	1096,	"R/W",	0,	0,	0ull,	4095ull},
-	{"DPI"                         ,	27,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL4"                    ,	28,	2,	1096,	"R/W",	0,	0,	0ull,	3ull},
-	{"FAU"                         ,	30,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL5"                    ,	31,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_32_63"              ,	32,	32,	1096,	"RAZ",	0,	0,	0ull,	0ull},
-	{"PP"                          ,	0,	8,	1097,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_8_15"               ,	8,	8,	1097,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKI"                         ,	16,	1,	1097,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKO"                         ,	17,	1,	1097,	"R/W",	0,	0,	0ull,	0ull},
-	{"IOBREQ"                      ,	18,	1,	1097,	"R/W",	0,	0,	0ull,	0ull},
-	{"DWB"                         ,	19,	1,	1097,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_20_63"              ,	20,	44,	1097,	"R/W",	0,	0,	0ull,	0ull},
-	{"CIU_TRG"                     ,	0,	1,	1098,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"CIU_THR"                     ,	1,	1,	1098,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"MCD0_TRG"                    ,	2,	1,	1098,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"MCD0_THR"                    ,	3,	1,	1098,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	1098,	"RAZ",	0,	0,	0ull,	0ull},
-	{"DATA"                        ,	0,	64,	1099,	"RO",	0,	0,	0ull,	0ull},
-	{"ADR"                         ,	0,	38,	1100,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	8,	8,	1013,	"RO",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	16,	16,	1013,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	32,	16,	1013,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1013,	"RAZ",	1,	1,	0,	0},
+	{"SEQ"                         ,	0,	32,	1014,	"RO",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	32,	8,	1014,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	1014,	"RAZ",	1,	1,	0,	0},
+	{"POST"                        ,	0,	8,	1015,	"RO",	0,	1,	128ull,	0},
+	{"N_POST"                      ,	8,	5,	1015,	"RO",	0,	1,	16ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	1015,	"RAZ",	1,	1,	0,	0},
+	{"COMP"                        ,	16,	8,	1015,	"RO",	0,	1,	128ull,	0},
+	{"MBOX"                        ,	24,	4,	1015,	"RO",	0,	1,	8ull,	0},
+	{"RESERVED_28_39"              ,	28,	12,	1015,	"RAZ",	1,	1,	0,	0},
+	{"RTN_PR1"                     ,	40,	8,	1015,	"RO",	0,	1,	0ull,	0},
+	{"RTN_PR2"                     ,	48,	8,	1015,	"RO",	0,	1,	0ull,	0},
+	{"RTN_PR3"                     ,	56,	8,	1015,	"RO",	0,	1,	0ull,	0},
+	{"IAOW_SEL"                    ,	0,	2,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	1016,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	4,	1,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	5,	1,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	1016,	"RAZ",	1,	1,	0,	0},
+	{"RD_PRIOR"                    ,	8,	2,	1016,	"R/W",	0,	0,	1ull,	1ull},
+	{"WR_PRIOR"                    ,	10,	2,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD_OP"                       ,	12,	3,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	1016,	"RAZ",	1,	1,	0,	0},
+	{"WR_OP"                       ,	16,	3,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	1016,	"RAZ",	1,	1,	0,	0},
+	{"SEQ"                         ,	0,	32,	1017,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1017,	"RAZ",	1,	1,	0,	0},
+	{"SRIO"                        ,	0,	1,	1018,	"RO",	1,	1,	0,	0},
+	{"ACCESS"                      ,	1,	1,	1018,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	1018,	"RAZ",	1,	1,	0,	0},
+	{"ITAG"                        ,	0,	5,	1019,	"RO",	0,	1,	16ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1019,	"RAZ",	1,	1,	0,	0},
+	{"OTAG"                        ,	8,	5,	1019,	"RO",	0,	1,	16ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	1019,	"RAZ",	1,	1,	0,	0},
+	{"O_CLR"                       ,	16,	1,	1019,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	1019,	"RAZ",	1,	1,	0,	0},
+	{"POST"                        ,	0,	8,	1020,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_POST"                      ,	8,	5,	1020,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_13_15"              ,	13,	3,	1020,	"RAZ",	1,	1,	0,	0},
+	{"COMP"                        ,	16,	8,	1020,	"R/W",	0,	0,	128ull,	128ull},
+	{"MBOX"                        ,	24,	4,	1020,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_28_63"              ,	28,	36,	1020,	"RAZ",	1,	1,	0,	0},
+	{"PRIORITY"                    ,	0,	2,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1021,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	3,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	4,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	1021,	"RAZ",	1,	1,	0,	0},
+	{"PENDING"                     ,	8,	1,	1021,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_15"               ,	9,	7,	1021,	"RAZ",	1,	1,	0,	0},
+	{"DEST_ID"                     ,	16,	16,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	32,	16,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1021,	"RAZ",	1,	1,	0,	0},
+	{"PRIORITY"                    ,	0,	2,	1022,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1022,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	3,	1,	1022,	"RO",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	4,	1,	1022,	"RO",	0,	0,	0ull,	0ull},
+	{"RETRY"                       ,	5,	1,	1022,	"RO",	0,	0,	0ull,	0ull},
+	{"ERROR"                       ,	6,	1,	1022,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMEOUT"                     ,	7,	1,	1022,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1022,	"RAZ",	1,	1,	0,	0},
+	{"DEST_ID"                     ,	16,	16,	1022,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	32,	16,	1022,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1022,	"RAZ",	1,	1,	0,	0},
+	{"TX_TH0"                      ,	0,	4,	1023,	"R/W",	0,	0,	6ull,	3ull},
+	{"RESERVED_4_7"                ,	4,	4,	1023,	"RAZ",	1,	1,	0,	0},
+	{"TX_TH1"                      ,	8,	4,	1023,	"R/W",	0,	0,	4ull,	2ull},
+	{"RESERVED_12_15"              ,	12,	4,	1023,	"RAZ",	1,	1,	0,	0},
+	{"TX_TH2"                      ,	16,	4,	1023,	"R/W",	0,	0,	2ull,	1ull},
+	{"RESERVED_20_31"              ,	20,	12,	1023,	"RAZ",	1,	1,	0,	0},
+	{"TAG_TH0"                     ,	32,	5,	1023,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_37_39"              ,	37,	3,	1023,	"RAZ",	1,	1,	0,	0},
+	{"TAG_TH1"                     ,	40,	5,	1023,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_45_47"              ,	45,	3,	1023,	"RAZ",	1,	1,	0,	0},
+	{"TAG_TH2"                     ,	48,	5,	1023,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_53_63"              ,	53,	11,	1023,	"RAZ",	1,	1,	0,	0},
+	{"S2M_PR0"                     ,	0,	8,	1024,	"RO",	0,	1,	0ull,	0},
+	{"S2M_PR1"                     ,	8,	8,	1024,	"RO",	0,	1,	0ull,	0},
+	{"S2M_PR2"                     ,	16,	8,	1024,	"RO",	0,	1,	0ull,	0},
+	{"S2M_PR3"                     ,	24,	8,	1024,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1024,	"RAZ",	1,	1,	0,	0},
+	{"ASSY_VEN"                    ,	0,	16,	1025,	"RO",	0,	0,	140ull,	0ull},
+	{"ASSY_ID"                     ,	16,	16,	1025,	"RO",	0,	0,	0ull,	0ull},
+	{"EXT_FPTR"                    ,	0,	16,	1026,	"RO",	0,	0,	256ull,	256ull},
+	{"ASSY_REV"                    ,	16,	16,	1026,	"RO",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_2"                ,	1,	2,	1027,	"RAZ",	1,	1,	0,	0},
+	{"NCA"                         ,	3,	1,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	4,	2,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	1027,	"RAZ",	1,	1,	0,	0},
+	{"LA"                          ,	8,	22,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_30_31"              ,	30,	2,	1027,	"RAZ",	1,	1,	0,	0},
+	{"FULL"                        ,	0,	1,	1028,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	1028,	"RAZ",	1,	1,	0,	0},
+	{"COMP_TAG"                    ,	0,	32,	1029,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEMORY"                      ,	0,	1,	1030,	"R/W",	0,	0,	0ull,	1ull},
+	{"DOORBELL"                    ,	1,	1,	1030,	"R/W",	0,	0,	0ull,	1ull},
+	{"IMSG0"                       ,	2,	1,	1030,	"R/W",	0,	0,	0ull,	1ull},
+	{"IMSG1"                       ,	3,	1,	1030,	"R/W",	0,	0,	0ull,	1ull},
+	{"HALT"                        ,	4,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	1030,	"RAZ",	1,	1,	0,	0},
+	{"VENDOR"                      ,	0,	16,	1031,	"RO",	0,	0,	140ull,	140ull},
+	{"DEVICE"                      ,	16,	16,	1031,	"RO",	0,	1,	144ull,	0},
+	{"REVISION"                    ,	0,	8,	1032,	"RO",	1,	1,	0,	0},
+	{"RESERVED_8_31"               ,	8,	24,	1032,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	1033,	"RAZ",	1,	1,	0,	0},
+	{"PORT_WR"                     ,	2,	1,	1033,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SWP"                    ,	3,	1,	1033,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_CLR"                    ,	4,	1,	1033,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SET"                    ,	5,	1,	1033,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_DEC"                    ,	6,	1,	1033,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_INC"                    ,	7,	1,	1033,	"RO",	0,	0,	1ull,	1ull},
+	{"TESTSWAP"                    ,	8,	1,	1033,	"RO",	0,	0,	0ull,	0ull},
+	{"COMPSWAP"                    ,	9,	1,	1033,	"RO",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	10,	1,	1033,	"RO",	0,	0,	1ull,	1ull},
+	{"MSG"                         ,	11,	1,	1033,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE_R"                     ,	12,	1,	1033,	"RO",	0,	0,	1ull,	1ull},
+	{"SWRITE"                      ,	13,	1,	1033,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE"                       ,	14,	1,	1033,	"RO",	0,	0,	1ull,	1ull},
+	{"READ"                        ,	15,	1,	1033,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_21"              ,	16,	6,	1033,	"RAZ",	1,	1,	0,	0},
+	{"TLB_INVS"                    ,	22,	1,	1033,	"RO",	0,	0,	0ull,	0ull},
+	{"TLB_INV"                     ,	23,	1,	1033,	"RO",	0,	0,	0ull,	0ull},
+	{"I_INVALD"                    ,	24,	1,	1033,	"RO",	0,	0,	0ull,	0ull},
+	{"IO_READ"                     ,	25,	1,	1033,	"RO",	0,	0,	0ull,	0ull},
+	{"D_FLUSH"                     ,	26,	1,	1033,	"RO",	0,	0,	0ull,	0ull},
+	{"CASTOUT"                     ,	27,	1,	1033,	"RO",	0,	0,	0ull,	0ull},
+	{"D_INVALD"                    ,	28,	1,	1033,	"RO",	0,	0,	0ull,	0ull},
+	{"RD_OWN"                      ,	29,	1,	1033,	"RO",	0,	0,	0ull,	0ull},
+	{"I_READ"                      ,	30,	1,	1033,	"RO",	0,	0,	0ull,	0ull},
+	{"GSM_READ"                    ,	31,	1,	1033,	"RO",	0,	0,	0ull,	0ull},
+	{"VALID"                       ,	0,	1,	1034,	"R/W0C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_23"               ,	1,	23,	1034,	"RAZ",	1,	1,	0,	0},
+	{"ERR_TYPE"                    ,	24,	5,	1034,	"R/W",	0,	0,	0ull,	0ull},
+	{"INF_TYPE"                    ,	29,	3,	1034,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_TOUT"                    ,	0,	1,	1035,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ACK"                     ,	1,	1,	1035,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEL_ERR"                     ,	2,	1,	1035,	"R/W",	0,	0,	0ull,	0ull},
+	{"F_TOGGLE"                    ,	3,	1,	1035,	"R/W",	0,	0,	0ull,	0ull},
+	{"PROTERR"                     ,	4,	1,	1035,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_ACK"                     ,	5,	1,	1035,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_16"               ,	6,	11,	1035,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	17,	1,	1035,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_CRC"                     ,	18,	1,	1035,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUT_ACK"                     ,	19,	1,	1035,	"R/W",	0,	0,	0ull,	0ull},
+	{"NACK"                        ,	20,	1,	1035,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ID"                      ,	21,	1,	1035,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTL_CRC"                     ,	22,	1,	1035,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	1035,	"R/W",	0,	0,	0ull,	0ull},
+	{"RATE_CNT"                    ,	0,	8,	1036,	"R/W",	0,	1,	0ull,	0},
+	{"PK_RATE"                     ,	8,	8,	1036,	"R/W",	0,	1,	0ull,	0},
+	{"RATE_LIM"                    ,	16,	2,	1036,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_23"              ,	18,	6,	1036,	"RAZ",	1,	1,	0,	0},
+	{"ERR_BIAS"                    ,	24,	8,	1036,	"R/W",	0,	0,	128ull,	128ull},
+	{"LNK_TOUT"                    ,	0,	1,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ACK"                     ,	1,	1,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEL_ERR"                     ,	2,	1,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"F_TOGGLE"                    ,	3,	1,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"PROTERR"                     ,	4,	1,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_ACK"                     ,	5,	1,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_16"               ,	6,	11,	1037,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	17,	1,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_CRC"                     ,	18,	1,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUT_ACK"                     ,	19,	1,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"NACK"                        ,	20,	1,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ID"                      ,	21,	1,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTL_CRC"                     ,	22,	1,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_15"               ,	0,	16,	1038,	"RAZ",	1,	1,	0,	0},
+	{"DGRAD_TH"                    ,	16,	8,	1038,	"R/W",	0,	0,	255ull,	128ull},
+	{"FAIL_TH"                     ,	24,	8,	1038,	"R/W",	0,	0,	255ull,	255ull},
+	{"EF_ID"                       ,	0,	16,	1039,	"RO",	0,	0,	7ull,	7ull},
+	{"EF_PTR"                      ,	16,	16,	1039,	"RO",	0,	0,	0ull,	0ull},
+	{"ADDR"                        ,	0,	32,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"XADDR"                       ,	0,	2,	1041,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1041,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	29,	1041,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPT_IDX"                    ,	0,	5,	1042,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_5"                ,	5,	1,	1042,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDPTR"                       ,	6,	1,	1042,	"R/W",	0,	0,	0ull,	0ull},
+	{"TT"                          ,	7,	1,	1042,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	8,	4,	1042,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATUS"                      ,	12,	4,	1042,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXTRA"                       ,	16,	8,	1042,	"R/W",	0,	0,	0ull,	0ull},
+	{"TTYPE"                       ,	24,	4,	1042,	"R/W",	0,	0,	0ull,	0ull},
+	{"FTYPE"                       ,	28,	4,	1042,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_14"               ,	0,	15,	1043,	"RAZ",	1,	1,	0,	0},
+	{"TT"                          ,	15,	1,	1043,	"R/W",	0,	0,	0ull,	0ull},
+	{"ID8"                         ,	16,	8,	1043,	"R/W",	0,	0,	0ull,	0ull},
+	{"ID16"                        ,	24,	8,	1043,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID8"                     ,	0,	8,	1044,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID16"                    ,	8,	8,	1044,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST_ID8"                     ,	16,	8,	1044,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST_ID16"                    ,	24,	8,	1044,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESP_SZ"                     ,	0,	1,	1045,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_21"               ,	1,	21,	1045,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_TRAN"                    ,	22,	1,	1045,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_RESP"                    ,	23,	1,	1045,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_TOUT"                    ,	24,	1,	1045,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_TOUT"                    ,	25,	1,	1045,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TGT"                     ,	26,	1,	1045,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TRAN"                    ,	27,	1,	1045,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_FMT"                     ,	28,	1,	1045,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSM_ERR"                     ,	29,	1,	1045,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_ERR"                     ,	30,	1,	1045,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO_ERR"                      ,	31,	1,	1045,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESP_SZ"                     ,	0,	1,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_21"               ,	1,	21,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_TRAN"                    ,	22,	1,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_RESP"                    ,	23,	1,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_TOUT"                    ,	24,	1,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_TOUT"                    ,	25,	1,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TGT"                     ,	26,	1,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TRAN"                    ,	27,	1,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_FMT"                     ,	28,	1,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSM_ERR"                     ,	29,	1,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_ERR"                     ,	30,	1,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO_ERR"                      ,	31,	1,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1048,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1050,	"R/W",	0,	0,	0ull,	0ull},
+	{"HOSTID"                      ,	0,	16,	1051,	"R/W",	0,	0,	65535ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1051,	"RAZ",	1,	1,	0,	0},
+	{"RX_SYNC"                     ,	0,	1,	1052,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_SYNC"                     ,	1,	1,	1052,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_FLOW"                     ,	2,	1,	1052,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_19"               ,	3,	17,	1052,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_WM2"                      ,	20,	4,	1052,	"R/W",	0,	0,	2ull,	1ull},
+	{"TX_WM1"                      ,	24,	4,	1052,	"R/W",	0,	0,	3ull,	2ull},
+	{"TX_WM0"                      ,	28,	4,	1052,	"R/W",	0,	0,	4ull,	3ull},
+	{"PD_CTRL"                     ,	0,	32,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"LN0_DIS"                     ,	0,	1,	1054,	"RO",	0,	0,	0ull,	0ull},
+	{"LN0_RX"                      ,	1,	3,	1054,	"RO",	0,	0,	0ull,	0ull},
+	{"LN1_DIS"                     ,	4,	1,	1054,	"RO",	0,	0,	0ull,	0ull},
+	{"LN1_RX"                      ,	5,	3,	1054,	"RO",	0,	0,	0ull,	0ull},
+	{"LN2_DIS"                     ,	8,	1,	1054,	"RO",	0,	0,	0ull,	0ull},
+	{"LN2_RX"                      ,	9,	3,	1054,	"RO",	0,	0,	0ull,	0ull},
+	{"LN3_DIS"                     ,	12,	1,	1054,	"RO",	0,	0,	0ull,	0ull},
+	{"LN3_RX"                      ,	13,	3,	1054,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1054,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_26"               ,	0,	27,	1055,	"RAZ",	1,	1,	0,	0},
+	{"LOOPBACK"                    ,	27,	2,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_29"              ,	29,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_RESET"                    ,	30,	1,	1055,	"R/W",	0,	0,	1ull,	1ull},
+	{"TX_RESET"                    ,	31,	1,	1055,	"R/W",	0,	0,	1ull,	1ull},
+	{"INIT_SM"                     ,	0,	10,	1056,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_31"              ,	10,	22,	1056,	"RAZ",	1,	1,	0,	0},
+	{"OVERWRT"                     ,	0,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	1057,	"RAZ",	1,	1,	0,	0},
+	{"PKT_DATA"                    ,	0,	32,	1058,	"RO",	0,	0,	0ull,	0ull},
+	{"FIFO_ST"                     ,	0,	4,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"FULL"                        ,	4,	1,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_11"               ,	5,	7,	1059,	"RAZ",	1,	1,	0,	0},
+	{"BUFFERS"                     ,	12,	4,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"OCTETS"                      ,	16,	16,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_15"               ,	0,	16,	1060,	"RAZ",	1,	1,	0,	0},
+	{"OCTETS"                      ,	16,	16,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_DATA"                    ,	0,	32,	1061,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIFO_ST"                     ,	0,	4,	1062,	"RO",	0,	0,	0ull,	0ull},
+	{"FULL"                        ,	4,	1,	1062,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_11"               ,	5,	7,	1062,	"RAZ",	1,	1,	0,	0},
+	{"BUFFERS"                     ,	12,	4,	1062,	"RO",	0,	0,	0ull,	0ull},
+	{"OCTETS"                      ,	16,	16,	1062,	"RO",	0,	0,	0ull,	0ull},
+	{"STATUSN"                     ,	0,	3,	1063,	"RO",	0,	0,	0ull,	0ull},
+	{"STATUS1"                     ,	3,	1,	1063,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_5"                ,	4,	2,	1063,	"RAZ",	1,	1,	0,	0},
+	{"XTRAIN"                      ,	6,	1,	1063,	"RO",	0,	0,	0ull,	0ull},
+	{"XSYNC"                       ,	7,	1,	1063,	"RO",	0,	0,	0ull,	0ull},
+	{"DEC_ERR"                     ,	8,	4,	1063,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_TRAIN"                    ,	12,	1,	1063,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_SYNC"                     ,	13,	1,	1063,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_ADAPT"                    ,	14,	1,	1063,	"RO",	0,	0,	1ull,	1ull},
+	{"RX_INV"                      ,	15,	1,	1063,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_TYPE"                     ,	16,	2,	1063,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_MODE"                     ,	18,	1,	1063,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_TYPE"                     ,	19,	1,	1063,	"RO",	0,	0,	0ull,	0ull},
+	{"LANE"                        ,	20,	4,	1063,	"RO",	0,	0,	0ull,	0ull},
+	{"PORT"                        ,	24,	8,	1063,	"RO",	0,	0,	0ull,	0ull},
+	{"LCSBA"                       ,	0,	31,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1064,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_20"               ,	0,	21,	1065,	"R/W",	0,	0,	0ull,	0ull},
+	{"LCSBA"                       ,	21,	11,	1065,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR48"                      ,	0,	16,	1066,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR64"                      ,	16,	16,	1066,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1067,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR66"                      ,	1,	2,	1067,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_13"               ,	3,	11,	1067,	"RAZ",	1,	1,	0,	0},
+	{"ADDR32"                      ,	14,	18,	1067,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR48"                      ,	0,	16,	1068,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR64"                      ,	16,	16,	1068,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1069,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR66"                      ,	1,	2,	1069,	"R/W",	0,	0,	0ull,	0ull},
+	{"BARSIZE"                     ,	3,	3,	1069,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_19"               ,	6,	14,	1069,	"RAZ",	1,	1,	0,	0},
+	{"ADDR32"                      ,	20,	12,	1069,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR66"                      ,	1,	2,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAX"                         ,	3,	1,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"ESX"                         ,	4,	2,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_8"                ,	6,	3,	1070,	"RAZ",	1,	1,	0,	0},
+	{"ADDR48"                      ,	9,	7,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR64"                      ,	16,	16,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"EX_ADDR"                     ,	0,	3,	1071,	"RO",	0,	0,	7ull,	7ull},
+	{"EX_FEAT"                     ,	3,	1,	1071,	"RO",	0,	0,	1ull,	1ull},
+	{"LG_TRAN"                     ,	4,	1,	1071,	"RO",	0,	0,	1ull,	1ull},
+	{"CRF"                         ,	5,	1,	1071,	"RO",	0,	0,	0ull,	0ull},
+	{"SUPPRESS"                    ,	6,	1,	1071,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_26"               ,	7,	20,	1071,	"RAZ",	1,	1,	0,	0},
+	{"MULT_PRT"                    ,	27,	1,	1071,	"RO",	0,	0,	0ull,	0ull},
+	{"SWITCHF"                     ,	28,	1,	1071,	"RO",	0,	0,	0ull,	0ull},
+	{"PROC"                        ,	29,	1,	1071,	"RO",	0,	0,	1ull,	1ull},
+	{"MEMORY"                      ,	30,	1,	1071,	"RO",	0,	0,	1ull,	1ull},
+	{"BRIDGE"                      ,	31,	1,	1071,	"RO",	0,	0,	0ull,	0ull},
+	{"EX_ADDR"                     ,	0,	3,	1072,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_31"               ,	3,	29,	1072,	"RAZ",	1,	1,	0,	0},
+	{"PT_TYPE"                     ,	0,	1,	1073,	"RO",	0,	0,	1ull,	1ull},
+	{"PRT_LOCK"                    ,	1,	1,	1073,	"R/W",	0,	0,	0ull,	0ull},
+	{"DROP_PKT"                    ,	2,	1,	1073,	"R/W",	0,	0,	0ull,	0ull},
+	{"STP_PORT"                    ,	3,	1,	1073,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUPPRESS"                    ,	4,	8,	1073,	"RO",	0,	0,	0ull,	0ull},
+	{"EX_STAT"                     ,	12,	2,	1073,	"RO",	0,	0,	0ull,	0ull},
+	{"EX_WIDTH"                    ,	14,	2,	1073,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	1073,	"RAZ",	1,	1,	0,	0},
+	{"ENUMB"                       ,	17,	1,	1073,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_18"              ,	18,	1,	1073,	"RAZ",	1,	1,	0,	0},
+	{"MCAST"                       ,	19,	1,	1073,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIS_ERR"                     ,	20,	1,	1073,	"R/W",	0,	0,	0ull,	0ull},
+	{"I_ENABLE"                    ,	21,	1,	1073,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ENABLE"                    ,	22,	1,	1073,	"R/W",	0,	0,	0ull,	1ull},
+	{"DISABLE"                     ,	23,	1,	1073,	"R/W",	0,	0,	0ull,	0ull},
+	{"OV_WIDTH"                    ,	24,	3,	1073,	"R/W",	0,	0,	0ull,	0ull},
+	{"IT_WIDTH"                    ,	27,	3,	1073,	"RO",	0,	1,	0ull,	0},
+	{"PT_WIDTH"                    ,	30,	2,	1073,	"RO",	0,	0,	2ull,	2ull},
+	{"EMPH_EN"                     ,	0,	1,	1074,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_EMPH"                     ,	1,	1,	1074,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_15"               ,	2,	14,	1074,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB_625G"                    ,	16,	1,	1074,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUP_625G"                    ,	17,	1,	1074,	"RO",	0,	0,	0ull,	0ull},
+	{"ENB_500G"                    ,	18,	1,	1074,	"R/W",	1,	1,	0,	0},
+	{"SUB_500G"                    ,	19,	1,	1074,	"RO",	1,	1,	0,	0},
+	{"ENB_312G"                    ,	20,	1,	1074,	"R/W",	1,	1,	0,	0},
+	{"SUP_312G"                    ,	21,	1,	1074,	"RO",	1,	1,	0,	0},
+	{"ENB_250G"                    ,	22,	1,	1074,	"R/W",	1,	1,	0,	0},
+	{"SUP_250G"                    ,	23,	1,	1074,	"RO",	1,	1,	0,	0},
+	{"ENB_125G"                    ,	24,	1,	1074,	"R/W",	1,	1,	0,	0},
+	{"SUP_125G"                    ,	25,	1,	1074,	"RO",	1,	1,	0,	0},
+	{"BAUD_ENB"                    ,	26,	1,	1074,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAUD_SUP"                    ,	27,	1,	1074,	"RO",	0,	0,	0ull,	0ull},
+	{"SEL_BAUD"                    ,	28,	4,	1074,	"RO",	0,	1,	0ull,	0},
+	{"PT_UINIT"                    ,	0,	1,	1075,	"RO",	0,	0,	1ull,	0ull},
+	{"PT_OK"                       ,	1,	1,	1075,	"RO",	0,	0,	0ull,	1ull},
+	{"PT_ERROR"                    ,	2,	1,	1075,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1075,	"RAZ",	1,	1,	0,	0},
+	{"PT_WRITE"                    ,	4,	1,	1075,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	1075,	"RAZ",	1,	1,	0,	0},
+	{"I_SM_ERR"                    ,	8,	1,	1075,	"RO",	0,	0,	0ull,	0ull},
+	{"I_ERROR"                     ,	9,	1,	1075,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I_SM_RET"                    ,	10,	1,	1075,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	1075,	"RAZ",	1,	1,	0,	0},
+	{"O_SM_ERR"                    ,	16,	1,	1075,	"RO",	0,	0,	0ull,	0ull},
+	{"O_ERROR"                     ,	17,	1,	1075,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"O_SM_RET"                    ,	18,	1,	1075,	"RO",	0,	0,	0ull,	0ull},
+	{"O_RTRIED"                    ,	19,	1,	1075,	"RO",	0,	0,	0ull,	0ull},
+	{"O_RETRY"                     ,	20,	1,	1075,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	1075,	"RAZ",	1,	1,	0,	0},
+	{"O_DGRAD"                     ,	24,	1,	1075,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"O_FAIL"                      ,	25,	1,	1075,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKT_DROP"                    ,	26,	1,	1075,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_31"              ,	27,	5,	1075,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_28"               ,	0,	29,	1076,	"RAZ",	1,	1,	0,	0},
+	{"DISCOVER"                    ,	29,	1,	1076,	"R/W",	0,	0,	0ull,	1ull},
+	{"MENABLE"                     ,	30,	1,	1076,	"R/W",	1,	0,	0,	1ull},
+	{"HOST"                        ,	31,	1,	1076,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1077,	"RAZ",	1,	1,	0,	0},
+	{"TIMEOUT"                     ,	8,	24,	1077,	"R/W",	0,	0,	16777215ull,	0ull},
+	{"EF_ID"                       ,	0,	16,	1078,	"RO",	0,	0,	1ull,	0ull},
+	{"EF_PTR"                      ,	16,	16,	1078,	"RO",	0,	0,	4096ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	1079,	"RAZ",	1,	1,	0,	0},
+	{"TIMEOUT"                     ,	8,	24,	1079,	"R/W",	0,	0,	16777215ull,	0ull},
+	{"ID16"                        ,	0,	16,	1080,	"R/W",	0,	0,	65535ull,	0ull},
+	{"ID8"                         ,	16,	8,	1080,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1080,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE16"                    ,	0,	1,	1081,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE8"                     ,	1,	1,	1081,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	1081,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	0,	16,	1082,	"R/W",	0,	0,	65535ull,	0ull},
+	{"ID8"                         ,	16,	8,	1082,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1082,	"RAZ",	1,	1,	0,	0},
+	{"EF_ID"                       ,	0,	16,	1083,	"RO",	0,	0,	13ull,	13ull},
+	{"EF_PTR"                      ,	16,	16,	1083,	"RO",	0,	0,	8192ull,	0ull},
+	{"RESERVED_0_1"                ,	0,	2,	1084,	"RAZ",	1,	1,	0,	0},
+	{"PORT_WR"                     ,	2,	1,	1084,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SWP"                    ,	3,	1,	1084,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_CLR"                    ,	4,	1,	1084,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SET"                    ,	5,	1,	1084,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_DEC"                    ,	6,	1,	1084,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_INC"                    ,	7,	1,	1084,	"RO",	0,	0,	1ull,	1ull},
+	{"TESTSWAP"                    ,	8,	1,	1084,	"RO",	0,	0,	0ull,	0ull},
+	{"COMPSWAP"                    ,	9,	1,	1084,	"RO",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	10,	1,	1084,	"RO",	0,	0,	1ull,	1ull},
+	{"MSG"                         ,	11,	1,	1084,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE_R"                     ,	12,	1,	1084,	"RO",	0,	0,	1ull,	1ull},
+	{"SWRITE"                      ,	13,	1,	1084,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE"                       ,	14,	1,	1084,	"RO",	0,	0,	1ull,	1ull},
+	{"READ"                        ,	15,	1,	1084,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_21"              ,	16,	6,	1084,	"RAZ",	1,	1,	0,	0},
+	{"TLB_INVS"                    ,	22,	1,	1084,	"RO",	0,	0,	0ull,	0ull},
+	{"TLB_INV"                     ,	23,	1,	1084,	"RO",	0,	0,	0ull,	0ull},
+	{"I_INVALD"                    ,	24,	1,	1084,	"RO",	0,	0,	0ull,	0ull},
+	{"IO_READ"                     ,	25,	1,	1084,	"RO",	0,	0,	0ull,	0ull},
+	{"D_FLUSH"                     ,	26,	1,	1084,	"RO",	0,	0,	0ull,	0ull},
+	{"CASTOUT"                     ,	27,	1,	1084,	"RO",	0,	0,	0ull,	0ull},
+	{"D_INVALD"                    ,	28,	1,	1084,	"RO",	0,	0,	0ull,	0ull},
+	{"RD_OWN"                      ,	29,	1,	1084,	"RO",	0,	0,	0ull,	0ull},
+	{"I_READ"                      ,	30,	1,	1084,	"RO",	0,	0,	0ull,	0ull},
+	{"GSM_READ"                    ,	31,	1,	1084,	"RO",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	0,	22,	1085,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1085,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	24,	22,	1085,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	1085,	"RAZ",	1,	1,	0,	0},
+	{"ENA"                         ,	47,	1,	1085,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1085,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	20,	1086,	"RO",	1,	0,	0,	0ull},
+	{"BASE"                        ,	20,	31,	1086,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	51,	13,	1086,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	0,	7,	1087,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	1087,	"RO",	1,	0,	0,	0ull},
+	{"CSIZE"                       ,	8,	13,	1087,	"RO",	1,	0,	0,	0ull},
+	{"CPOOL"                       ,	21,	3,	1087,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	1087,	"RAZ",	1,	1,	0,	0},
+	{"RING"                        ,	0,	4,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_BUCKETS"                 ,	4,	20,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIRST_BUCKET"                ,	24,	31,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	1088,	"RAZ",	1,	1,	0,	0},
+	{"RING"                        ,	0,	4,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	4,	22,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORDS_PER_CHUNK"             ,	26,	13,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	39,	3,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	42,	1,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	1089,	"RAZ",	1,	1,	0,	0},
+	{"CTL"                         ,	0,	1,	1090,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	1,	1,	1090,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	2,	2,	1090,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1090,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	1091,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1091,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE_TIMERS"               ,	0,	1,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	2,	1,	1092,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	1092,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1093,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	1094,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	1094,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1094,	"RAZ",	1,	1,	0,	0},
+	{"TDF"                         ,	0,	1,	1095,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1095,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRAP"                        ,	1,	1,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRIG_CTL"                    ,	2,	2,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIME_GRN"                    ,	4,	3,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"FULL_THR"                    ,	7,	2,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	9,	1,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	10,	1,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	11,	1,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	12,	1,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_ENA"                    ,	13,	1,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNORE_O"                    ,	14,	1,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKALWAYS"                   ,	15,	1,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1096,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	8,	1097,	"RO",	0,	0,	0ull,	0ull},
+	{"RPTR"                        ,	8,	8,	1097,	"RO",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	16,	48,	1097,	"RO",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	10,	1098,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	1098,	"RAZ",	1,	1,	0,	0},
+	{"RPTR"                        ,	12,	10,	1098,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1098,	"RAZ",	1,	1,	0,	0},
+	{"CYCLES"                      ,	24,	40,	1098,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1099,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1099,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1100,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESERVED_38_63"              ,	38,	26,	1100,	"RAZ",	0,	0,	0ull,	0ull},
-	{"ADR"                         ,	0,	38,	1101,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_38_63"              ,	38,	26,	1101,	"RAZ",	0,	0,	0ull,	0ull},
-	{"NOP"                         ,	0,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"LDT"                         ,	1,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"LDI"                         ,	2,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"PL2"                         ,	3,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"RPL2"                        ,	4,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"DWB"                         ,	5,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_7"                ,	6,	2,	1102,	"R/W",	0,	0,	0ull,	0ull},
-	{"LDD"                         ,	8,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"PSL1"                        ,	9,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_10_14"              ,	10,	5,	1102,	"R/W",	0,	0,	0ull,	0ull},
-	{"IOBDMA"                      ,	15,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"STF"                         ,	16,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"STT"                         ,	17,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"STP"                         ,	18,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"STC"                         ,	19,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"STFIL1"                      ,	20,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"STTIL1"                      ,	21,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAS32"                       ,	22,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAS64"                       ,	23,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"WBIL2I"                      ,	24,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"LTGL2I"                      ,	25,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"STGL2I"                      ,	26,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_27_27"              ,	27,	1,	1102,	"R/W",	0,	0,	0ull,	0ull},
-	{"INVL2"                       ,	28,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"WBIL2"                       ,	29,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"WBL2"                        ,	30,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"LCKL2"                       ,	31,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD8"                      ,	32,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD16"                     ,	33,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD32"                     ,	34,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD64"                     ,	35,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST8"                      ,	36,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST16"                     ,	37,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST32"                     ,	38,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST64"                     ,	39,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET8"                        ,	40,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET16"                       ,	41,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET32"                       ,	42,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET64"                       ,	43,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR8"                        ,	44,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR16"                       ,	45,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR32"                       ,	46,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR64"                       ,	47,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR8"                       ,	48,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR16"                      ,	49,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR32"                      ,	50,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR64"                      ,	51,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR8"                       ,	52,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR16"                      ,	53,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR32"                      ,	54,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR64"                      ,	55,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_56_57"              ,	56,	2,	1102,	"R/W",	0,	0,	0ull,	0ull},
-	{"FAA32"                       ,	58,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAA64"                       ,	59,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_60_61"              ,	60,	2,	1102,	"R/W",	0,	0,	0ull,	0ull},
-	{"SAA32"                       ,	62,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"SAA64"                       ,	63,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
-	{"MIO"                         ,	0,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL3"                    ,	1,	2,	1103,	"R/W",	0,	0,	0ull,	3ull},
-	{"SLI"                         ,	3,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
-	{"KEY"                         ,	4,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
-	{"FPA"                         ,	5,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
-	{"DFA"                         ,	6,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
-	{"ZIP"                         ,	7,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
-	{"RNG"                         ,	8,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
-	{"IPD"                         ,	9,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
-	{"PKO"                         ,	10,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL2"                    ,	11,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
-	{"POW"                         ,	12,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
-	{"USB0"                        ,	13,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
-	{"RAD"                         ,	14,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL"                     ,	15,	12,	1103,	"R/W",	0,	0,	0ull,	4095ull},
-	{"DPI"                         ,	27,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL4"                    ,	28,	2,	1103,	"R/W",	0,	0,	0ull,	3ull},
-	{"FAU"                         ,	30,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL5"                    ,	31,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_32_63"              ,	32,	32,	1103,	"RAZ",	0,	0,	0ull,	0ull},
-	{"PP"                          ,	0,	8,	1104,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_8_15"               ,	8,	8,	1104,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKI"                         ,	16,	1,	1104,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKO"                         ,	17,	1,	1104,	"R/W",	0,	0,	0ull,	0ull},
-	{"IOBREQ"                      ,	18,	1,	1104,	"R/W",	0,	0,	0ull,	0ull},
-	{"DWB"                         ,	19,	1,	1104,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_20_63"              ,	20,	44,	1104,	"R/W",	0,	0,	0ull,	0ull},
-	{"ADR"                         ,	0,	38,	1105,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_38_63"              ,	38,	26,	1105,	"RAZ",	0,	0,	0ull,	0ull},
-	{"ADR"                         ,	0,	38,	1106,	"R/W",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1101,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1101,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1101,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1101,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1101,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1101,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1102,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1102,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1102,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1102,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	6,	1103,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_15"               ,	6,	10,	1103,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1103,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1103,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1103,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1103,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1103,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	0,	1,	1104,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	1,	1,	1104,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	2,	1,	1104,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	3,	1,	1104,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1104,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	1105,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1106,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_38_63"              ,	38,	26,	1106,	"RAZ",	0,	0,	0ull,	0ull},
-	{"NOP"                         ,	0,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"LDT"                         ,	1,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"LDI"                         ,	2,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"PL2"                         ,	3,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"RPL2"                        ,	4,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"DWB"                         ,	5,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_7"                ,	6,	2,	1107,	"R/W",	0,	0,	0ull,	0ull},
-	{"LDD"                         ,	8,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"PSL1"                        ,	9,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_10_14"              ,	10,	5,	1107,	"R/W",	0,	0,	0ull,	0ull},
-	{"IOBDMA"                      ,	15,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"STF"                         ,	16,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"STT"                         ,	17,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"STP"                         ,	18,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"STC"                         ,	19,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"STFIL1"                      ,	20,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"STTIL1"                      ,	21,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAS32"                       ,	22,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAS64"                       ,	23,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"WBIL2I"                      ,	24,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"LTGL2I"                      ,	25,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"STGL2I"                      ,	26,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_27_27"              ,	27,	1,	1107,	"R/W",	0,	0,	0ull,	0ull},
-	{"INVL2"                       ,	28,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"WBIL2"                       ,	29,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"WBL2"                        ,	30,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"LCKL2"                       ,	31,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD8"                      ,	32,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD16"                     ,	33,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD32"                     ,	34,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD64"                     ,	35,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST8"                      ,	36,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST16"                     ,	37,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST32"                     ,	38,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST64"                     ,	39,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET8"                        ,	40,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET16"                       ,	41,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET32"                       ,	42,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET64"                       ,	43,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR8"                        ,	44,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR16"                       ,	45,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR32"                       ,	46,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR64"                       ,	47,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR8"                       ,	48,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR16"                      ,	49,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR32"                      ,	50,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR64"                      ,	51,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR8"                       ,	52,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR16"                      ,	53,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR32"                      ,	54,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR64"                      ,	55,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_56_57"              ,	56,	2,	1107,	"R/W",	0,	0,	0ull,	0ull},
-	{"FAA32"                       ,	58,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAA64"                       ,	59,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_60_61"              ,	60,	2,	1107,	"R/W",	0,	0,	0ull,	0ull},
-	{"SAA32"                       ,	62,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"SAA64"                       ,	63,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
-	{"MIO"                         ,	0,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL3"                    ,	1,	2,	1108,	"R/W",	0,	0,	0ull,	3ull},
-	{"SLI"                         ,	3,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
-	{"KEY"                         ,	4,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
-	{"FPA"                         ,	5,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
-	{"DFA"                         ,	6,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
-	{"ZIP"                         ,	7,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
-	{"RNG"                         ,	8,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
-	{"IPD"                         ,	9,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
-	{"PKO"                         ,	10,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL2"                    ,	11,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
-	{"POW"                         ,	12,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
-	{"USB0"                        ,	13,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
-	{"RAD"                         ,	14,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL"                     ,	15,	12,	1108,	"R/W",	0,	0,	0ull,	4095ull},
-	{"DPI"                         ,	27,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL4"                    ,	28,	2,	1108,	"R/W",	0,	0,	0ull,	3ull},
-	{"FAU"                         ,	30,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL5"                    ,	31,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_32_63"              ,	32,	32,	1108,	"RAZ",	0,	0,	0ull,	0ull},
-	{"PP"                          ,	0,	8,	1109,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_8_15"               ,	8,	8,	1109,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKI"                         ,	16,	1,	1109,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKO"                         ,	17,	1,	1109,	"R/W",	0,	0,	0ull,	0ull},
-	{"IOBREQ"                      ,	18,	1,	1109,	"R/W",	0,	0,	0ull,	0ull},
-	{"DWB"                         ,	19,	1,	1109,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_20_63"              ,	20,	44,	1109,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_4"                ,	0,	5,	1110,	"R/W",	0,	1,	0ull,	0},
-	{"LPL"                         ,	5,	27,	1110,	"R/W",	0,	1,	0ull,	0},
-	{"CF"                          ,	0,	1,	1111,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_1_31"               ,	1,	31,	1111,	"R/W",	0,	0,	0ull,	0ull},
-	{"CTRLDSSEG"                   ,	0,	32,	1112,	"R/W",	0,	1,	0ull,	0},
-	{"FI"                          ,	0,	14,	1113,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_14_31"              ,	14,	18,	1113,	"RO",	0,	0,	0ull,	0ull},
-	{"CAPLENGTH"                   ,	0,	8,	1114,	"RO",	0,	0,	16ull,	16ull},
-	{"RESERVED_8_15"               ,	8,	8,	1114,	"RO",	0,	0,	0ull,	0ull},
-	{"HCIVERSION"                  ,	16,	16,	1114,	"RO",	0,	0,	256ull,	256ull},
-	{"AC64"                        ,	0,	1,	1115,	"RO",	0,	0,	1ull,	1ull},
-	{"PFLF"                        ,	1,	1,	1115,	"RO",	0,	0,	0ull,	0ull},
-	{"ASPC"                        ,	2,	1,	1115,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_3"                ,	3,	1,	1115,	"RO",	0,	0,	0ull,	0ull},
-	{"IST"                         ,	4,	4,	1115,	"RO",	0,	0,	2ull,	2ull},
-	{"EECP"                        ,	8,	8,	1115,	"RO",	0,	0,	160ull,	160ull},
-	{"RESERVED_16_31"              ,	16,	16,	1115,	"RO",	0,	0,	0ull,	0ull},
-	{"N_PORTS"                     ,	0,	4,	1116,	"RO",	0,	0,	2ull,	2ull},
-	{"PPC"                         ,	4,	1,	1116,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_6"                ,	5,	2,	1116,	"RO",	0,	0,	0ull,	0ull},
-	{"PRR"                         ,	7,	1,	1116,	"RO",	0,	0,	0ull,	0ull},
-	{"N_PCC"                       ,	8,	4,	1116,	"RO",	0,	0,	2ull,	2ull},
-	{"N_CC"                        ,	12,	4,	1116,	"RO",	0,	0,	1ull,	1ull},
-	{"P_INDICATOR"                 ,	16,	1,	1116,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_17_19"              ,	17,	3,	1116,	"RO",	0,	0,	0ull,	0ull},
-	{"DPN"                         ,	20,	4,	1116,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_24_31"              ,	24,	8,	1116,	"RO",	0,	0,	0ull,	0ull},
-	{"EN"                          ,	0,	1,	1117,	"R/W",	0,	0,	0ull,	0ull},
-	{"MFMC"                        ,	1,	13,	1117,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_14_31"              ,	14,	18,	1117,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_0"                ,	0,	1,	1118,	"R/W",	0,	0,	0ull,	0ull},
-	{"TA_OFF"                      ,	1,	8,	1118,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_9_9"                ,	9,	1,	1118,	"R/W",	0,	0,	0ull,	0ull},
-	{"TXTX_TADAO"                  ,	10,	3,	1118,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_13_31"              ,	13,	19,	1118,	"R/W",	0,	0,	0ull,	0ull},
-	{"HCP_RW"                      ,	0,	1,	1119,	"R/W",	0,	0,	0ull,	0ull},
-	{"HCP_FW"                      ,	1,	1,	1119,	"R/W",	0,	0,	0ull,	0ull},
-	{"PESD"                        ,	2,	1,	1119,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_3"                ,	3,	1,	1119,	"RAZ",	0,	0,	0ull,	0ull},
-	{"NAKRF_DIS"                   ,	4,	1,	1119,	"R/W",	0,	0,	0ull,	0ull},
-	{"AUTO_DIS"                    ,	5,	1,	1119,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_31"               ,	6,	26,	1119,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_30"               ,	0,	31,	1120,	"R/W",	0,	0,	0ull,	0ull},
-	{"VLD"                         ,	31,	1,	1120,	"R/W",	0,	0,	0ull,	0ull},
-	{"ERR_ADDR"                    ,	0,	32,	1121,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_11"               ,	0,	12,	1122,	"R/W",	0,	1,	0ull,	0},
-	{"BADDR"                       ,	12,	20,	1122,	"R/W",	0,	1,	0ull,	0},
-	{"CCS"                         ,	0,	1,	1123,	"RO",	0,	0,	0ull,	0ull},
-	{"CSC"                         ,	1,	1,	1123,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PED"                         ,	2,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
-	{"PEDC"                        ,	3,	1,	1123,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"OCA"                         ,	4,	1,	1123,	"RO",	0,	0,	0ull,	0ull},
-	{"OCC"                         ,	5,	1,	1123,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"FPR"                         ,	6,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
-	{"SPD"                         ,	7,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
-	{"PRST"                        ,	8,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_9_9"                ,	9,	1,	1123,	"RO",	0,	0,	0ull,	0ull},
-	{"LSTS"                        ,	10,	2,	1123,	"RO",	0,	1,	0ull,	0},
-	{"PP"                          ,	12,	1,	1123,	"RO",	0,	0,	1ull,	1ull},
-	{"PO"                          ,	13,	1,	1123,	"R/W",	0,	0,	1ull,	0ull},
-	{"PIC"                         ,	14,	2,	1123,	"R/W",	0,	0,	0ull,	0ull},
-	{"PTC"                         ,	16,	4,	1123,	"R/W",	0,	0,	0ull,	0ull},
-	{"WKCNNT_E"                    ,	20,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
-	{"WKDSCNNT_E"                  ,	21,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
-	{"WKOC_E"                      ,	22,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_31"              ,	23,	9,	1123,	"RO",	0,	0,	0ull,	0ull},
-	{"RS"                          ,	0,	1,	1124,	"R/W",	0,	0,	0ull,	1ull},
-	{"HCRESET"                     ,	1,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
-	{"FLS"                         ,	2,	2,	1124,	"RO",	0,	0,	0ull,	0ull},
-	{"PS_EN"                       ,	4,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
-	{"AS_EN"                       ,	5,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
-	{"IAA_DB"                      ,	6,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
-	{"LHCR"                        ,	7,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
-	{"ASPMC"                       ,	8,	2,	1124,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_10"              ,	10,	1,	1124,	"RO",	0,	0,	0ull,	0ull},
-	{"ASPM_EN"                     ,	11,	1,	1124,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_12_15"              ,	12,	4,	1124,	"RO",	0,	0,	0ull,	0ull},
-	{"ITC"                         ,	16,	8,	1124,	"R/W",	0,	0,	8ull,	8ull},
-	{"RESERVED_24_31"              ,	24,	8,	1124,	"RO",	0,	0,	0ull,	0ull},
-	{"USBINT_EN"                   ,	0,	1,	1125,	"R/W",	0,	1,	0ull,	0},
-	{"USBERRINT_EN"                ,	1,	1,	1125,	"R/W",	0,	1,	0ull,	0},
-	{"PCI_EN"                      ,	2,	1,	1125,	"R/W",	0,	1,	0ull,	0},
-	{"FLRO_EN"                     ,	3,	1,	1125,	"R/W",	0,	1,	0ull,	0},
-	{"HSERR_EN"                    ,	4,	1,	1125,	"R/W",	0,	1,	0ull,	0},
-	{"IOAA_EN"                     ,	5,	1,	1125,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_6_31"               ,	6,	26,	1125,	"RO",	0,	0,	0ull,	0ull},
-	{"USBINT"                      ,	0,	1,	1126,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"USBERRINT"                   ,	1,	1,	1126,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PCD"                         ,	2,	1,	1126,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"FLRO"                        ,	3,	1,	1126,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"HSYSERR"                     ,	4,	1,	1126,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"IOAA"                        ,	5,	1,	1126,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_11"               ,	6,	6,	1126,	"RO",	0,	0,	0ull,	0ull},
-	{"HCHTD"                       ,	12,	1,	1126,	"RO",	0,	0,	1ull,	0ull},
-	{"RECLM"                       ,	13,	1,	1126,	"RO",	0,	0,	0ull,	0ull},
-	{"PSS"                         ,	14,	1,	1126,	"RO",	0,	0,	0ull,	0ull},
-	{"ASS"                         ,	15,	1,	1126,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_31"              ,	16,	16,	1126,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_3"                ,	0,	4,	1127,	"R/W",	0,	0,	0ull,	0ull},
-	{"BCED"                        ,	4,	28,	1127,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_0_3"                ,	0,	4,	1128,	"R/W",	0,	0,	0ull,	0ull},
-	{"BHED"                        ,	4,	28,	1128,	"R/W",	0,	1,	0ull,	0},
-	{"HCR"                         ,	0,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
-	{"CLF"                         ,	1,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
-	{"BLF"                         ,	2,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
-	{"OCR"                         ,	3,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_15"               ,	4,	12,	1129,	"RO",	0,	0,	0ull,	0ull},
-	{"SOC"                         ,	16,	2,	1129,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_18_31"              ,	18,	14,	1129,	"RO",	0,	0,	0ull,	0ull},
-	{"CBSR"                        ,	0,	2,	1130,	"R/W",	0,	1,	0ull,	0},
-	{"PLE"                         ,	2,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
-	{"IE"                          ,	3,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
-	{"CLE"                         ,	4,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
-	{"BLE"                         ,	5,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
-	{"HCFS"                        ,	6,	2,	1130,	"R/W",	0,	0,	0ull,	0ull},
-	{"IR"                          ,	8,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
-	{"RWC"                         ,	9,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
-	{"RWE"                         ,	10,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_11_31"              ,	11,	21,	1130,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_3"                ,	0,	4,	1131,	"R/W",	0,	0,	0ull,	0ull},
-	{"CCED"                        ,	4,	28,	1131,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_0_3"                ,	0,	4,	1132,	"R/W",	0,	0,	0ull,	0ull},
-	{"CHED"                        ,	4,	28,	1132,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_0_3"                ,	0,	4,	1133,	"RO",	0,	0,	0ull,	0ull},
-	{"DH"                          ,	4,	28,	1133,	"RO",	0,	1,	0ull,	0},
-	{"FI"                          ,	0,	14,	1134,	"R/W",	0,	1,	11999ull,	0},
-	{"RESERVED_14_15"              ,	14,	2,	1134,	"R/W",	0,	0,	0ull,	0ull},
-	{"FSMPS"                       ,	16,	15,	1134,	"R/W",	0,	1,	0ull,	0},
-	{"FIT"                         ,	31,	1,	1134,	"R/W",	0,	0,	0ull,	0ull},
-	{"FN"                          ,	0,	16,	1135,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_16_31"              ,	16,	16,	1135,	"RO",	0,	0,	0ull,	0ull},
-	{"FR"                          ,	0,	14,	1136,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_14_30"              ,	14,	17,	1136,	"RO",	0,	0,	0ull,	0ull},
-	{"FRT"                         ,	31,	1,	1136,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_7"                ,	0,	8,	1137,	"R/W",	0,	0,	0ull,	0ull},
-	{"HCCA"                        ,	8,	24,	1137,	"R/W",	0,	1,	0ull,	0},
-	{"SO"                          ,	0,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
-	{"WDH"                         ,	1,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
-	{"SF"                          ,	2,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
-	{"RD"                          ,	3,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
-	{"UE"                          ,	4,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
-	{"FNO"                         ,	5,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
-	{"RHSC"                        ,	6,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_7_29"               ,	7,	23,	1138,	"RO",	0,	0,	0ull,	0ull},
-	{"OC"                          ,	30,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
-	{"MIE"                         ,	31,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
-	{"SO"                          ,	0,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
-	{"WDH"                         ,	1,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
-	{"SF"                          ,	2,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
-	{"RD"                          ,	3,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
-	{"UE"                          ,	4,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
-	{"FNO"                         ,	5,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
-	{"RHSC"                        ,	6,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_7_29"               ,	7,	23,	1139,	"RO",	0,	0,	0ull,	0ull},
-	{"OC"                          ,	30,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
-	{"MIE"                         ,	31,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
-	{"SO"                          ,	0,	1,	1140,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"WDH"                         ,	1,	1,	1140,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"SF"                          ,	2,	1,	1140,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RD"                          ,	3,	1,	1140,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"UE"                          ,	4,	1,	1140,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"FNO"                         ,	5,	1,	1140,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RHSC"                        ,	6,	1,	1140,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_7_29"               ,	7,	23,	1140,	"RO",	0,	0,	0ull,	0ull},
-	{"OC"                          ,	30,	1,	1140,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_31_31"              ,	31,	1,	1140,	"RO",	0,	0,	0ull,	0ull},
-	{"LST"                         ,	0,	12,	1141,	"R/W",	0,	1,	1576ull,	0},
-	{"RESERVED_12_31"              ,	12,	20,	1141,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_3"                ,	0,	4,	1142,	"RO",	0,	0,	0ull,	0ull},
-	{"PCED"                        ,	4,	28,	1142,	"RO",	0,	1,	0ull,	0},
-	{"PS"                          ,	0,	14,	1143,	"R/W",	0,	0,	0ull,	15975ull},
-	{"RESERVED_14_31"              ,	14,	18,	1143,	"R/W",	0,	0,	0ull,	0ull},
-	{"REV"                         ,	0,	8,	1144,	"RO",	0,	0,	16ull,	16ull},
-	{"RESERVED_8_31"               ,	8,	24,	1144,	"RO",	0,	0,	0ull,	0ull},
-	{"NDP"                         ,	0,	8,	1145,	"RO",	0,	0,	2ull,	2ull},
-	{"NPS"                         ,	8,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
-	{"PSM"                         ,	9,	1,	1145,	"R/W",	0,	0,	1ull,	1ull},
-	{"DT"                          ,	10,	1,	1145,	"RO",	0,	0,	0ull,	0ull},
-	{"OCPM"                        ,	11,	1,	1145,	"R/W",	1,	1,	0,	0},
-	{"NOCP"                        ,	12,	1,	1145,	"R/W",	0,	0,	1ull,	1ull},
-	{"RESERVED_13_23"              ,	13,	11,	1145,	"RO",	0,	0,	0ull,	0ull},
-	{"POTPGT"                      ,	24,	8,	1145,	"R/W",	0,	0,	1ull,	1ull},
-	{"DR"                          ,	0,	16,	1146,	"R/W",	0,	0,	0ull,	0ull},
-	{"PPCM"                        ,	16,	16,	1146,	"R/W",	0,	1,	0ull,	0},
-	{"CCS"                         ,	0,	1,	1147,	"R/W",	0,	1,	0ull,	0},
-	{"PES"                         ,	1,	1,	1147,	"R/W",	0,	1,	0ull,	0},
-	{"PSS"                         ,	2,	1,	1147,	"R/W",	0,	1,	0ull,	0},
-	{"POCI"                        ,	3,	1,	1147,	"R/W",	0,	1,	0ull,	0},
-	{"PRS"                         ,	4,	1,	1147,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_5_7"                ,	5,	3,	1147,	"R/W",	0,	0,	0ull,	0ull},
-	{"PPS"                         ,	8,	1,	1147,	"R/W",	0,	1,	0ull,	0},
-	{"LSDA"                        ,	9,	1,	1147,	"R/W",	1,	1,	0,	0},
-	{"RESERVED_10_15"              ,	10,	6,	1147,	"R/W",	0,	0,	0ull,	0ull},
-	{"CSC"                         ,	16,	1,	1147,	"R/W",	0,	1,	0ull,	0},
-	{"PESC"                        ,	17,	1,	1147,	"R/W",	0,	1,	0ull,	0},
-	{"PSSC"                        ,	18,	1,	1147,	"R/W",	0,	1,	0ull,	0},
-	{"OCIC"                        ,	19,	1,	1147,	"R/W",	0,	1,	0ull,	0},
-	{"PRSC"                        ,	20,	1,	1147,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_21_31"              ,	21,	11,	1147,	"R/W",	0,	0,	0ull,	0ull},
-	{"LPS"                         ,	0,	1,	1148,	"R/W",	0,	0,	0ull,	0ull},
-	{"OCI"                         ,	1,	1,	1148,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_14"               ,	2,	13,	1148,	"RO",	0,	0,	0ull,	0ull},
-	{"DRWE"                        ,	15,	1,	1148,	"R/W",	0,	1,	0ull,	0},
-	{"LPSC"                        ,	16,	1,	1148,	"R/W",	0,	1,	0ull,	0},
-	{"CCIC"                        ,	17,	1,	1148,	"R/W1C",	0,	1,	0ull,	0},
-	{"RESERVED_18_30"              ,	18,	13,	1148,	"RO",	0,	0,	0ull,	0ull},
-	{"CRWE"                        ,	31,	1,	1148,	"WO",	1,	1,	0,	0},
-	{"RESERVED_0_30"               ,	0,	31,	1149,	"R/W",	0,	0,	0ull,	0ull},
-	{"VLD"                         ,	31,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
-	{"ERR_ADDR"                    ,	0,	32,	1150,	"RO",	0,	0,	0ull,	0ull},
-	{"PPAF_BIS"                    ,	0,	1,	1151,	"RO",	0,	0,	0ull,	0ull},
-	{"WRBM_BIS"                    ,	1,	1,	1151,	"RO",	0,	0,	0ull,	0ull},
-	{"ORBM_BIS"                    ,	2,	1,	1151,	"RO",	0,	0,	0ull,	0ull},
-	{"ERBM_BIS"                    ,	3,	1,	1151,	"RO",	0,	0,	0ull,	0ull},
-	{"DESC_BIS"                    ,	4,	1,	1151,	"RO",	0,	0,	0ull,	0ull},
-	{"DATA_BIS"                    ,	5,	1,	1151,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	1151,	"RO",	1,	1,	0,	0},
-	{"HRST"                        ,	0,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
-	{"P_PRST"                      ,	1,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
-	{"P_POR"                       ,	2,	1,	1152,	"R/W",	0,	0,	1ull,	0ull},
-	{"P_COM_ON"                    ,	3,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_4"                ,	4,	1,	1152,	"R/W",	0,	1,	0ull,	0},
-	{"P_REFCLK_DIV"                ,	5,	2,	1152,	"R/W",	0,	0,	0ull,	0ull},
-	{"P_REFCLK_SEL"                ,	7,	2,	1152,	"R/W",	0,	0,	0ull,	0ull},
-	{"H_DIV"                       ,	9,	4,	1152,	"R/W",	0,	0,	6ull,	6ull},
-	{"O_CLKDIV_EN"                 ,	13,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
-	{"H_CLKDIV_EN"                 ,	14,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
-	{"H_CLKDIV_RST"                ,	15,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
-	{"H_CLKDIV_BYP"                ,	16,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
-	{"O_CLKDIV_RST"                ,	17,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
-	{"APP_START_CLK"               ,	18,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
-	{"OHCI_SUSP_LGCY"              ,	19,	1,	1152,	"R/W",	0,	0,	1ull,	1ull},
-	{"OHCI_SM"                     ,	20,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
-	{"OHCI_CLKCKTRST"              ,	21,	1,	1152,	"R/W",	0,	0,	1ull,	1ull},
-	{"EHCI_SM"                     ,	22,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
-	{"START_BIST"                  ,	23,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
-	{"CLEAR_BIST"                  ,	24,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_25_63"              ,	25,	39,	1152,	"RAZ",	1,	1,	0,	0},
-	{"L2C_ADDR_MSB"                ,	0,	8,	1153,	"R/W",	0,	1,	0ull,	0},
-	{"EHCI_64B_ADDR_EN"            ,	8,	1,	1153,	"R/W",	0,	0,	1ull,	1ull},
-	{"INV_REG_A2"                  ,	9,	1,	1153,	"R/W",	0,	0,	0ull,	0ull},
-	{"L2C_DESC_EMOD"               ,	10,	2,	1153,	"R/W",	0,	0,	0ull,	0ull},
-	{"L2C_BUFF_EMOD"               ,	12,	2,	1153,	"R/W",	0,	0,	1ull,	1ull},
-	{"L2C_STT"                     ,	14,	1,	1153,	"R/W",	0,	0,	0ull,	0ull},
-	{"L2C_0PAG"                    ,	15,	1,	1153,	"R/W",	0,	0,	0ull,	0ull},
-	{"L2C_BC"                      ,	16,	1,	1153,	"R/W",	0,	0,	0ull,	0ull},
-	{"L2C_DC"                      ,	17,	1,	1153,	"R/W",	0,	0,	1ull,	1ull},
-	{"REG_NB"                      ,	18,	1,	1153,	"R/W",	0,	0,	0ull,	0ull},
-	{"DESC_RBM"                    ,	19,	1,	1153,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_20_63"              ,	20,	44,	1153,	"RAZ",	1,	1,	0,	0},
-	{"FLA"                         ,	0,	6,	1154,	"R/W",	0,	0,	32ull,	32ull},
-	{"RESERVED_6_63"               ,	6,	58,	1154,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_4"                ,	0,	5,	1155,	"RAZ",	1,	1,	0,	0},
-	{"TO_VAL"                      ,	5,	27,	1155,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	1155,	"RAZ",	1,	1,	0,	0},
-	{"EN"                          ,	0,	1,	1156,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_1_63"               ,	1,	63,	1156,	"RAZ",	1,	1,	0,	0},
-	{"PP_PSH_F"                    ,	0,	1,	1157,	"R/W",	0,	0,	0ull,	0ull},
-	{"ER_PSH_F"                    ,	1,	1,	1157,	"R/W",	0,	0,	0ull,	0ull},
-	{"OR_PSH_F"                    ,	2,	1,	1157,	"R/W",	0,	0,	0ull,	0ull},
-	{"CF_PSH_F"                    ,	3,	1,	1157,	"R/W",	0,	0,	0ull,	0ull},
-	{"WB_PSH_F"                    ,	4,	1,	1157,	"R/W",	0,	0,	0ull,	0ull},
-	{"WB_POP_E"                    ,	5,	1,	1157,	"R/W",	0,	0,	0ull,	0ull},
-	{"OC_OVF_E"                    ,	6,	1,	1157,	"R/W",	0,	0,	0ull,	0ull},
-	{"EC_OVF_E"                    ,	7,	1,	1157,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_8_63"               ,	8,	56,	1157,	"RAZ",	1,	1,	0,	0},
-	{"PP_PSH_F"                    ,	0,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"ER_PSH_F"                    ,	1,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"OR_PSH_F"                    ,	2,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"CF_PSH_F"                    ,	3,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"WB_PSH_F"                    ,	4,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"WB_POP_E"                    ,	5,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"OC_OVF_E"                    ,	6,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"EC_OVF_E"                    ,	7,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_8_63"               ,	8,	56,	1158,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	38,	1107,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1107,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1109,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1109,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1109,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1109,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1109,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1109,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1109,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1109,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1109,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1109,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1109,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1109,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1109,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1109,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1109,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1109,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1109,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1109,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1109,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1109,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	6,	1110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_15"               ,	6,	10,	1110,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1110,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1110,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1110,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1110,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1111,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1111,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1112,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1113,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1113,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1113,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1113,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1113,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1113,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1114,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1114,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1114,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1114,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1114,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1114,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1114,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1114,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1114,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1114,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1114,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1114,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1114,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1114,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1114,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1114,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1114,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1114,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1114,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1114,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	6,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_15"               ,	6,	10,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	1116,	"R/W",	0,	1,	0ull,	0},
+	{"LPL"                         ,	5,	27,	1116,	"R/W",	0,	1,	0ull,	0},
+	{"CF"                          ,	0,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_31"               ,	1,	31,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTRLDSSEG"                   ,	0,	32,	1118,	"R/W",	0,	1,	0ull,	0},
+	{"FI"                          ,	0,	14,	1119,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_31"              ,	14,	18,	1119,	"RO",	0,	0,	0ull,	0ull},
+	{"CAPLENGTH"                   ,	0,	8,	1120,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_8_15"               ,	8,	8,	1120,	"RO",	0,	0,	0ull,	0ull},
+	{"HCIVERSION"                  ,	16,	16,	1120,	"RO",	0,	0,	256ull,	256ull},
+	{"AC64"                        ,	0,	1,	1121,	"RO",	0,	0,	1ull,	1ull},
+	{"PFLF"                        ,	1,	1,	1121,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPC"                        ,	2,	1,	1121,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1121,	"RO",	0,	0,	0ull,	0ull},
+	{"IST"                         ,	4,	4,	1121,	"RO",	0,	0,	2ull,	2ull},
+	{"EECP"                        ,	8,	8,	1121,	"RO",	0,	0,	160ull,	160ull},
+	{"RESERVED_16_31"              ,	16,	16,	1121,	"RO",	0,	0,	0ull,	0ull},
+	{"N_PORTS"                     ,	0,	4,	1122,	"RO",	0,	0,	2ull,	2ull},
+	{"PPC"                         ,	4,	1,	1122,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	1122,	"RO",	0,	0,	0ull,	0ull},
+	{"PRR"                         ,	7,	1,	1122,	"RO",	0,	0,	0ull,	0ull},
+	{"N_PCC"                       ,	8,	4,	1122,	"RO",	0,	0,	2ull,	2ull},
+	{"N_CC"                        ,	12,	4,	1122,	"RO",	0,	0,	1ull,	1ull},
+	{"P_INDICATOR"                 ,	16,	1,	1122,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	1122,	"RO",	0,	0,	0ull,	0ull},
+	{"DPN"                         ,	20,	4,	1122,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1122,	"RO",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	0,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"MFMC"                        ,	1,	13,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_0"                ,	0,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"TA_OFF"                      ,	1,	8,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXTX_TADAO"                  ,	10,	3,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCP_RW"                      ,	0,	1,	1125,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCP_FW"                      ,	1,	1,	1125,	"R/W",	0,	0,	0ull,	0ull},
+	{"PESD"                        ,	2,	1,	1125,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1125,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NAKRF_DIS"                   ,	4,	1,	1125,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTO_DIS"                    ,	5,	1,	1125,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	1125,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_30"               ,	0,	31,	1126,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	31,	1,	1126,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_ADDR"                    ,	0,	32,	1127,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_11"               ,	0,	12,	1128,	"R/W",	0,	1,	0ull,	0},
+	{"BADDR"                       ,	12,	20,	1128,	"R/W",	0,	1,	0ull,	0},
+	{"CCS"                         ,	0,	1,	1129,	"RO",	0,	0,	0ull,	0ull},
+	{"CSC"                         ,	1,	1,	1129,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PED"                         ,	2,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEDC"                        ,	3,	1,	1129,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OCA"                         ,	4,	1,	1129,	"RO",	0,	0,	0ull,	0ull},
+	{"OCC"                         ,	5,	1,	1129,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPR"                         ,	6,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPD"                         ,	7,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRST"                        ,	8,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	1129,	"RO",	0,	0,	0ull,	0ull},
+	{"LSTS"                        ,	10,	2,	1129,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	12,	1,	1129,	"RO",	0,	0,	1ull,	1ull},
+	{"PO"                          ,	13,	1,	1129,	"R/W",	0,	0,	1ull,	0ull},
+	{"PIC"                         ,	14,	2,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTC"                         ,	16,	4,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKCNNT_E"                    ,	20,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKDSCNNT_E"                  ,	21,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKOC_E"                      ,	22,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	1129,	"RO",	0,	0,	0ull,	0ull},
+	{"RS"                          ,	0,	1,	1130,	"R/W",	0,	0,	0ull,	1ull},
+	{"HCRESET"                     ,	1,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"FLS"                         ,	2,	2,	1130,	"RO",	0,	0,	0ull,	0ull},
+	{"PS_EN"                       ,	4,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"AS_EN"                       ,	5,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"IAA_DB"                      ,	6,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"LHCR"                        ,	7,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASPMC"                       ,	8,	2,	1130,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	1130,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPM_EN"                     ,	11,	1,	1130,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	1130,	"RO",	0,	0,	0ull,	0ull},
+	{"ITC"                         ,	16,	8,	1130,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_24_31"              ,	24,	8,	1130,	"RO",	0,	0,	0ull,	0ull},
+	{"USBINT_EN"                   ,	0,	1,	1131,	"R/W",	0,	1,	0ull,	0},
+	{"USBERRINT_EN"                ,	1,	1,	1131,	"R/W",	0,	1,	0ull,	0},
+	{"PCI_EN"                      ,	2,	1,	1131,	"R/W",	0,	1,	0ull,	0},
+	{"FLRO_EN"                     ,	3,	1,	1131,	"R/W",	0,	1,	0ull,	0},
+	{"HSERR_EN"                    ,	4,	1,	1131,	"R/W",	0,	1,	0ull,	0},
+	{"IOAA_EN"                     ,	5,	1,	1131,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_31"               ,	6,	26,	1131,	"RO",	0,	0,	0ull,	0ull},
+	{"USBINT"                      ,	0,	1,	1132,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBERRINT"                   ,	1,	1,	1132,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCD"                         ,	2,	1,	1132,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FLRO"                        ,	3,	1,	1132,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HSYSERR"                     ,	4,	1,	1132,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOAA"                        ,	5,	1,	1132,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	1132,	"RO",	0,	0,	0ull,	0ull},
+	{"HCHTD"                       ,	12,	1,	1132,	"RO",	0,	0,	1ull,	0ull},
+	{"RECLM"                       ,	13,	1,	1132,	"RO",	0,	0,	0ull,	0ull},
+	{"PSS"                         ,	14,	1,	1132,	"RO",	0,	0,	0ull,	0ull},
+	{"ASS"                         ,	15,	1,	1132,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1132,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1133,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCED"                        ,	4,	28,	1133,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1134,	"R/W",	0,	0,	0ull,	0ull},
+	{"BHED"                        ,	4,	28,	1134,	"R/W",	0,	1,	0ull,	0},
+	{"HCR"                         ,	0,	1,	1135,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLF"                         ,	1,	1,	1135,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLF"                         ,	2,	1,	1135,	"R/W",	0,	0,	0ull,	0ull},
+	{"OCR"                         ,	3,	1,	1135,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	1135,	"RO",	0,	0,	0ull,	0ull},
+	{"SOC"                         ,	16,	2,	1135,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	1135,	"RO",	0,	0,	0ull,	0ull},
+	{"CBSR"                        ,	0,	2,	1136,	"R/W",	0,	1,	0ull,	0},
+	{"PLE"                         ,	2,	1,	1136,	"R/W",	0,	0,	0ull,	0ull},
+	{"IE"                          ,	3,	1,	1136,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLE"                         ,	4,	1,	1136,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLE"                         ,	5,	1,	1136,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCFS"                        ,	6,	2,	1136,	"R/W",	0,	0,	0ull,	0ull},
+	{"IR"                          ,	8,	1,	1136,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWC"                         ,	9,	1,	1136,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWE"                         ,	10,	1,	1136,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	1136,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCED"                        ,	4,	28,	1137,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHED"                        ,	4,	28,	1138,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1139,	"RO",	0,	0,	0ull,	0ull},
+	{"DH"                          ,	4,	28,	1139,	"RO",	0,	1,	0ull,	0},
+	{"FI"                          ,	0,	14,	1140,	"R/W",	0,	1,	11999ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	1140,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSMPS"                       ,	16,	15,	1140,	"R/W",	0,	1,	0ull,	0},
+	{"FIT"                         ,	31,	1,	1140,	"R/W",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	0,	16,	1141,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"FR"                          ,	0,	14,	1142,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_30"              ,	14,	17,	1142,	"RO",	0,	0,	0ull,	0ull},
+	{"FRT"                         ,	31,	1,	1142,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	1143,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCCA"                        ,	8,	24,	1143,	"R/W",	0,	1,	0ull,	0},
+	{"SO"                          ,	0,	1,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1144,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIE"                         ,	31,	1,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"SO"                          ,	0,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1145,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIE"                         ,	31,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"SO"                          ,	0,	1,	1146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1146,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1146,	"RO",	0,	0,	0ull,	0ull},
+	{"LST"                         ,	0,	12,	1147,	"R/W",	0,	1,	1576ull,	0},
+	{"RESERVED_12_31"              ,	12,	20,	1147,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1148,	"RO",	0,	0,	0ull,	0ull},
+	{"PCED"                        ,	4,	28,	1148,	"RO",	0,	1,	0ull,	0},
+	{"PS"                          ,	0,	14,	1149,	"R/W",	0,	0,	0ull,	15975ull},
+	{"RESERVED_14_31"              ,	14,	18,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"REV"                         ,	0,	8,	1150,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_8_31"               ,	8,	24,	1150,	"RO",	0,	0,	0ull,	0ull},
+	{"NDP"                         ,	0,	8,	1151,	"RO",	0,	0,	2ull,	2ull},
+	{"NPS"                         ,	8,	1,	1151,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSM"                         ,	9,	1,	1151,	"R/W",	0,	0,	1ull,	1ull},
+	{"DT"                          ,	10,	1,	1151,	"RO",	0,	0,	0ull,	0ull},
+	{"OCPM"                        ,	11,	1,	1151,	"R/W",	1,	1,	0,	0},
+	{"NOCP"                        ,	12,	1,	1151,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_23"              ,	13,	11,	1151,	"RO",	0,	0,	0ull,	0ull},
+	{"POTPGT"                      ,	24,	8,	1151,	"R/W",	0,	0,	1ull,	1ull},
+	{"DR"                          ,	0,	16,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPCM"                        ,	16,	16,	1152,	"R/W",	0,	1,	0ull,	0},
+	{"CCS"                         ,	0,	1,	1153,	"R/W",	0,	1,	0ull,	0},
+	{"PES"                         ,	1,	1,	1153,	"R/W",	0,	1,	0ull,	0},
+	{"PSS"                         ,	2,	1,	1153,	"R/W",	0,	1,	0ull,	0},
+	{"POCI"                        ,	3,	1,	1153,	"R/W",	0,	1,	0ull,	0},
+	{"PRS"                         ,	4,	1,	1153,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1153,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS"                         ,	8,	1,	1153,	"R/W",	0,	1,	0ull,	0},
+	{"LSDA"                        ,	9,	1,	1153,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_10_15"              ,	10,	6,	1153,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSC"                         ,	16,	1,	1153,	"R/W",	0,	1,	0ull,	0},
+	{"PESC"                        ,	17,	1,	1153,	"R/W",	0,	1,	0ull,	0},
+	{"PSSC"                        ,	18,	1,	1153,	"R/W",	0,	1,	0ull,	0},
+	{"OCIC"                        ,	19,	1,	1153,	"R/W",	0,	1,	0ull,	0},
+	{"PRSC"                        ,	20,	1,	1153,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_31"              ,	21,	11,	1153,	"R/W",	0,	0,	0ull,	0ull},
+	{"LPS"                         ,	0,	1,	1154,	"R/W",	0,	0,	0ull,	0ull},
+	{"OCI"                         ,	1,	1,	1154,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_14"               ,	2,	13,	1154,	"RO",	0,	0,	0ull,	0ull},
+	{"DRWE"                        ,	15,	1,	1154,	"R/W",	0,	1,	0ull,	0},
+	{"LPSC"                        ,	16,	1,	1154,	"R/W",	0,	1,	0ull,	0},
+	{"CCIC"                        ,	17,	1,	1154,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_18_30"              ,	18,	13,	1154,	"RO",	0,	0,	0ull,	0ull},
+	{"CRWE"                        ,	31,	1,	1154,	"WO",	1,	1,	0,	0},
+	{"RESERVED_0_30"               ,	0,	31,	1155,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	31,	1,	1155,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_ADDR"                    ,	0,	32,	1156,	"RO",	0,	0,	0ull,	0ull},
+	{"PPAF_BIS"                    ,	0,	1,	1157,	"RO",	0,	0,	0ull,	0ull},
+	{"WRBM_BIS"                    ,	1,	1,	1157,	"RO",	0,	0,	0ull,	0ull},
+	{"ORBM_BIS"                    ,	2,	1,	1157,	"RO",	0,	0,	0ull,	0ull},
+	{"ERBM_BIS"                    ,	3,	1,	1157,	"RO",	0,	0,	0ull,	0ull},
+	{"DESC_BIS"                    ,	4,	1,	1157,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_BIS"                    ,	5,	1,	1157,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1157,	"RO",	1,	1,	0,	0},
+	{"HRST"                        ,	0,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_PRST"                      ,	1,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_POR"                       ,	2,	1,	1158,	"R/W",	0,	0,	1ull,	0ull},
+	{"P_COM_ON"                    ,	3,	1,	1158,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	1158,	"R/W",	0,	1,	0ull,	0},
+	{"P_REFCLK_DIV"                ,	5,	2,	1158,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_REFCLK_SEL"                ,	7,	2,	1158,	"R/W",	0,	0,	0ull,	0ull},
+	{"H_DIV"                       ,	9,	4,	1158,	"R/W",	0,	0,	6ull,	6ull},
+	{"O_CLKDIV_EN"                 ,	13,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_EN"                 ,	14,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_RST"                ,	15,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_BYP"                ,	16,	1,	1158,	"R/W",	0,	0,	0ull,	0ull},
+	{"O_CLKDIV_RST"                ,	17,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"APP_START_CLK"               ,	18,	1,	1158,	"R/W",	0,	0,	0ull,	0ull},
+	{"OHCI_SUSP_LGCY"              ,	19,	1,	1158,	"R/W",	0,	0,	1ull,	1ull},
+	{"OHCI_SM"                     ,	20,	1,	1158,	"R/W",	0,	0,	0ull,	0ull},
+	{"OHCI_CLKCKTRST"              ,	21,	1,	1158,	"R/W",	0,	0,	1ull,	1ull},
+	{"EHCI_SM"                     ,	22,	1,	1158,	"R/W",	0,	0,	0ull,	0ull},
+	{"START_BIST"                  ,	23,	1,	1158,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLEAR_BIST"                  ,	24,	1,	1158,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1158,	"RAZ",	1,	1,	0,	0},
 	{"L2C_ADDR_MSB"                ,	0,	8,	1159,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_8_8"                ,	8,	1,	1159,	"RAZ",	1,	1,	0,	0},
+	{"EHCI_64B_ADDR_EN"            ,	8,	1,	1159,	"R/W",	0,	0,	1ull,	1ull},
 	{"INV_REG_A2"                  ,	9,	1,	1159,	"R/W",	0,	0,	0ull,	0ull},
 	{"L2C_DESC_EMOD"               ,	10,	2,	1159,	"R/W",	0,	0,	0ull,	0ull},
 	{"L2C_BUFF_EMOD"               ,	12,	2,	1159,	"R/W",	0,	0,	1ull,	1ull},
@@ -89612,68 +104638,105 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
 	{"L2C_BC"                      ,	16,	1,	1159,	"R/W",	0,	0,	0ull,	0ull},
 	{"L2C_DC"                      ,	17,	1,	1159,	"R/W",	0,	0,	1ull,	1ull},
 	{"REG_NB"                      ,	18,	1,	1159,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_19_63"              ,	19,	45,	1159,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_7"                ,	0,	8,	1160,	"RAZ",	1,	1,	0,	0},
-	{"TO_VAL"                      ,	8,	24,	1160,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	1160,	"RAZ",	1,	1,	0,	0},
-	{"WM"                          ,	0,	5,	1161,	"R/W",	0,	0,	8ull,	8ull},
-	{"RESERVED_5_63"               ,	5,	59,	1161,	"RAZ",	1,	1,	0,	0},
-	{"ATE_RESET"                   ,	0,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
-	{"BIST_EN"                     ,	1,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
-	{"UPHY_BIST"                   ,	2,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
-	{"VTEST_EN"                    ,	3,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
-	{"SIDDQ"                       ,	4,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
-	{"LSBIST"                      ,	5,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
-	{"FSBIST"                      ,	6,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
-	{"HSBIST"                      ,	7,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
-	{"BIST_ERR"                    ,	8,	1,	1162,	"RO",	0,	0,	0ull,	0ull},
-	{"BIST_DONE"                   ,	9,	1,	1162,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_63"              ,	10,	54,	1162,	"RAZ",	1,	1,	0,	0},
-	{"TDATA_IN"                    ,	0,	8,	1163,	"R/W",	0,	0,	0ull,	0ull},
-	{"TADDR_IN"                    ,	8,	4,	1163,	"R/W",	0,	0,	0ull,	0ull},
-	{"TDATA_SEL"                   ,	12,	1,	1163,	"R/W",	0,	0,	1ull,	0ull},
-	{"TCLK"                        ,	13,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
-	{"LOOP_EN"                     ,	14,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
-	{"COMPDISTUNE"                 ,	15,	3,	1163,	"R/W",	0,	0,	4ull,	4ull},
-	{"SQRXTUNE"                    ,	18,	3,	1163,	"R/W",	0,	0,	4ull,	4ull},
-	{"TXFSLSTUNE"                  ,	21,	4,	1163,	"R/W",	0,	0,	3ull,	3ull},
-	{"TXPREEMPHASISTUNE"           ,	25,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
-	{"TXRISETUNE"                  ,	26,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
-	{"TXVREFTUNE"                  ,	27,	4,	1163,	"R/W",	0,	0,	5ull,	5ull},
-	{"TXHSVXTUNE"                  ,	31,	2,	1163,	"R/W",	0,	0,	0ull,	0ull},
-	{"PORTRESET"                   ,	33,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
-	{"VBUSVLDEXT"                  ,	34,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
-	{"DPPULLDOWN"                  ,	35,	1,	1163,	"R/W",	0,	0,	1ull,	1ull},
-	{"DMPULLDOWN"                  ,	36,	1,	1163,	"R/W",	0,	0,	1ull,	1ull},
-	{"TXBISTSTUFFEN"               ,	37,	1,	1163,	"R/W",	0,	0,	1ull,	1ull},
-	{"TXBISTSTUFFENH"              ,	38,	1,	1163,	"R/W",	0,	0,	1ull,	1ull},
-	{"TDATA_OUT"                   ,	39,	4,	1163,	"RO",	1,	1,	0,	0},
-	{"RESERVED_43_63"              ,	43,	21,	1163,	"RAZ",	1,	1,	0,	0},
-	{"ZIP_CTL"                     ,	0,	4,	1164,	"RO",	1,	0,	0,	0ull},
-	{"ZIP_CORE"                    ,	4,	39,	1164,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_43_63"              ,	43,	21,	1164,	"RAZ",	1,	1,	0,	0},
-	{"PTR"                         ,	0,	33,	1165,	"R/W",	0,	0,	0ull,	0ull},
-	{"SIZE"                        ,	33,	13,	1165,	"R/W",	0,	0,	0ull,	0ull},
-	{"POOL"                        ,	46,	3,	1165,	"R/W",	0,	0,	0ull,	0ull},
-	{"DWB"                         ,	49,	9,	1165,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_58_63"              ,	58,	6,	1165,	"RAZ",	1,	1,	0,	0},
-	{"RESET"                       ,	0,	1,	1166,	"RAZ",	0,	0,	0ull,	0ull},
-	{"FORCECLK"                    ,	1,	1,	1166,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	1166,	"RAZ",	1,	1,	0,	0},
-	{"DISABLED"                    ,	0,	1,	1167,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_7"                ,	1,	7,	1167,	"RAZ",	1,	1,	0,	0},
-	{"CTXSIZE"                     ,	8,	12,	1167,	"RO",	0,	0,	1536ull,	1536ull},
-	{"ONFSIZE"                     ,	20,	12,	1167,	"RO",	0,	0,	512ull,	512ull},
-	{"DEPTH"                       ,	32,	16,	1167,	"RO",	0,	0,	31744ull,	31744ull},
-	{"RESERVED_48_63"              ,	48,	16,	1167,	"RAZ",	1,	1,	0,	0},
-	{"ASSERTS"                     ,	0,	17,	1168,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_17_63"              ,	17,	47,	1168,	"RAZ",	1,	1,	0,	0},
-	{"DOORBELL"                    ,	0,	1,	1169,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	1169,	"RAZ",	1,	1,	0,	0},
-	{"DOORBELL"                    ,	0,	1,	1170,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	1170,	"RAZ",	1,	1,	0,	0},
-	{"MAX_INFL"                    ,	0,	4,	1171,	"R/W",	0,	0,	8ull,	8ull},
-	{"RESERVED_4_63"               ,	4,	60,	1171,	"RAZ",	1,	1,	0,	0},
+	{"DESC_RBM"                    ,	19,	1,	1159,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1159,	"RAZ",	1,	1,	0,	0},
+	{"FLA"                         ,	0,	6,	1160,	"R/W",	0,	0,	0ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	1160,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	1161,	"RAZ",	1,	1,	0,	0},
+	{"TO_VAL"                      ,	5,	27,	1161,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1161,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	1162,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	1162,	"RAZ",	1,	1,	0,	0},
+	{"PP_PSH_F"                    ,	0,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"ER_PSH_F"                    ,	1,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"OR_PSH_F"                    ,	2,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"CF_PSH_F"                    ,	3,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"WB_PSH_F"                    ,	4,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"WB_POP_E"                    ,	5,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"OC_OVF_E"                    ,	6,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"EC_OVF_E"                    ,	7,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1163,	"RAZ",	1,	1,	0,	0},
+	{"PP_PSH_F"                    ,	0,	1,	1164,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ER_PSH_F"                    ,	1,	1,	1164,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OR_PSH_F"                    ,	2,	1,	1164,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CF_PSH_F"                    ,	3,	1,	1164,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WB_PSH_F"                    ,	4,	1,	1164,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WB_POP_E"                    ,	5,	1,	1164,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OC_OVF_E"                    ,	6,	1,	1164,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EC_OVF_E"                    ,	7,	1,	1164,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1164,	"RAZ",	1,	1,	0,	0},
+	{"L2C_ADDR_MSB"                ,	0,	8,	1165,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_8"                ,	8,	1,	1165,	"RAZ",	1,	1,	0,	0},
+	{"INV_REG_A2"                  ,	9,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DESC_EMOD"               ,	10,	2,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BUFF_EMOD"               ,	12,	2,	1165,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2C_STT"                     ,	14,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_0PAG"                    ,	15,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BC"                      ,	16,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DC"                      ,	17,	1,	1165,	"R/W",	0,	0,	1ull,	1ull},
+	{"REG_NB"                      ,	18,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	1165,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1166,	"RAZ",	1,	1,	0,	0},
+	{"TO_VAL"                      ,	8,	24,	1166,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1166,	"RAZ",	1,	1,	0,	0},
+	{"WM"                          ,	0,	5,	1167,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_5_63"               ,	5,	59,	1167,	"RAZ",	1,	1,	0,	0},
+	{"ATE_RESET"                   ,	0,	1,	1168,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_EN"                     ,	1,	1,	1168,	"R/W",	0,	0,	0ull,	0ull},
+	{"UPHY_BIST"                   ,	2,	1,	1168,	"R/W",	0,	0,	0ull,	0ull},
+	{"VTEST_EN"                    ,	3,	1,	1168,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIDDQ"                       ,	4,	1,	1168,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBIST"                      ,	5,	1,	1168,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSBIST"                      ,	6,	1,	1168,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSBIST"                      ,	7,	1,	1168,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_ERR"                    ,	8,	1,	1168,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST_DONE"                   ,	9,	1,	1168,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1168,	"RAZ",	1,	1,	0,	0},
+	{"TDATA_IN"                    ,	0,	8,	1169,	"R/W",	0,	0,	0ull,	0ull},
+	{"TADDR_IN"                    ,	8,	4,	1169,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_SEL"                   ,	12,	1,	1169,	"R/W",	0,	0,	1ull,	0ull},
+	{"TCLK"                        ,	13,	1,	1169,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOP_EN"                     ,	14,	1,	1169,	"R/W",	0,	0,	0ull,	0ull},
+	{"COMPDISTUNE"                 ,	15,	3,	1169,	"R/W",	0,	0,	4ull,	4ull},
+	{"SQRXTUNE"                    ,	18,	3,	1169,	"R/W",	0,	0,	4ull,	4ull},
+	{"TXFSLSTUNE"                  ,	21,	4,	1169,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPREEMPHASISTUNE"           ,	25,	1,	1169,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXRISETUNE"                  ,	26,	1,	1169,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXVREFTUNE"                  ,	27,	4,	1169,	"R/W",	0,	0,	5ull,	15ull},
+	{"TXHSVXTUNE"                  ,	31,	2,	1169,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORTRESET"                   ,	33,	1,	1169,	"R/W",	0,	0,	0ull,	0ull},
+	{"VBUSVLDEXT"                  ,	34,	1,	1169,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPPULLDOWN"                  ,	35,	1,	1169,	"R/W",	0,	0,	1ull,	1ull},
+	{"DMPULLDOWN"                  ,	36,	1,	1169,	"R/W",	0,	0,	1ull,	1ull},
+	{"TXBISTSTUFFEN"               ,	37,	1,	1169,	"R/W",	0,	0,	1ull,	1ull},
+	{"TXBISTSTUFFENH"              ,	38,	1,	1169,	"R/W",	0,	0,	1ull,	1ull},
+	{"TDATA_OUT"                   ,	39,	4,	1169,	"RO",	1,	1,	0,	0},
+	{"RESERVED_43_63"              ,	43,	21,	1169,	"RAZ",	1,	1,	0,	0},
+	{"ZIP_CTL"                     ,	0,	4,	1170,	"RO",	1,	0,	0,	0ull},
+	{"ZIP_CORE"                    ,	4,	39,	1170,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	1170,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	1171,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	33,	13,	1171,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	46,	3,	1171,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	49,	9,	1171,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	1171,	"RAZ",	1,	1,	0,	0},
+	{"RESET"                       ,	0,	1,	1172,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FORCECLK"                    ,	1,	1,	1172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1172,	"RAZ",	1,	1,	0,	0},
+	{"DISABLED"                    ,	0,	1,	1173,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	1173,	"RAZ",	1,	1,	0,	0},
+	{"CTXSIZE"                     ,	8,	12,	1173,	"RO",	0,	0,	1536ull,	1536ull},
+	{"ONFSIZE"                     ,	20,	12,	1173,	"RO",	0,	0,	512ull,	512ull},
+	{"DEPTH"                       ,	32,	16,	1173,	"RO",	0,	0,	31744ull,	31744ull},
+	{"RESERVED_48_63"              ,	48,	16,	1173,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	17,	1174,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	1174,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1175,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1175,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1176,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1176,	"RAZ",	1,	1,	0,	0},
+	{"MAX_INFL"                    ,	0,	4,	1177,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	1177,	"RAZ",	1,	1,	0,	0},
 	{NULL,0,0,0,0,0,0,0,0}
 };
 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn63xx[] = {
@@ -90266,616 +105329,622 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn63xx[] = {
 	{"cvmx_pcieep#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5705,	22,	3254},
 	{"cvmx_pcieep#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5707,	3,	3276},
 	{"cvmx_pcieep#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5709,	3,	3279},
-	{"cvmx_pcieep#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5711,	1,	3282},
-	{"cvmx_pcieep#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5713,	11,	3283},
-	{"cvmx_pcieep#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5715,	1,	3294},
-	{"cvmx_pcieep#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5717,	1,	3295},
-	{"cvmx_pcieep#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5719,	3,	3296},
-	{"cvmx_pcieep#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5721,	14,	3299},
-	{"cvmx_pcieep#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5723,	14,	3313},
-	{"cvmx_pcieep#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5725,	14,	3327},
-	{"cvmx_pcieep#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5727,	9,	3341},
-	{"cvmx_pcieep#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5729,	9,	3350},
-	{"cvmx_pcieep#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5731,	6,	3359},
-	{"cvmx_pcieep#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5733,	1,	3365},
-	{"cvmx_pcieep#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5735,	1,	3366},
-	{"cvmx_pcieep#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5737,	1,	3367},
-	{"cvmx_pcieep#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5739,	1,	3368},
-	{"cvmx_pcieep#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5741,	2,	3369},
-	{"cvmx_pcieep#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5743,	1,	3371},
-	{"cvmx_pcieep#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5745,	6,	3372},
-	{"cvmx_pcieep#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5747,	6,	3378},
-	{"cvmx_pcieep#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5749,	13,	3384},
-	{"cvmx_pcieep#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5751,	5,	3397},
-	{"cvmx_pcieep#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5753,	8,	3402},
-	{"cvmx_pcieep#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5755,	19,	3410},
-	{"cvmx_pcieep#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5757,	3,	3429},
-	{"cvmx_pcieep#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5759,	1,	3432},
-	{"cvmx_pcieep#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5761,	1,	3433},
-	{"cvmx_pcieep#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5763,	3,	3434},
-	{"cvmx_pcieep#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5765,	3,	3437},
-	{"cvmx_pcieep#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5767,	3,	3440},
-	{"cvmx_pcieep#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5769,	4,	3443},
-	{"cvmx_pcieep#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5771,	4,	3447},
-	{"cvmx_pcieep#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5773,	4,	3451},
-	{"cvmx_pcieep#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5775,	7,	3455},
-	{"cvmx_pcieep#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5777,	5,	3462},
-	{"cvmx_pcieep#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5779,	5,	3467},
-	{"cvmx_pcieep#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5781,	4,	3472},
-	{"cvmx_pcieep#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5783,	4,	3476},
-	{"cvmx_pcieep#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5785,	4,	3480},
-	{"cvmx_pcieep#_cfg515"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5787,	7,	3484},
-	{"cvmx_pcieep#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5789,	1,	3491},
-	{"cvmx_pcieep#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5791,	1,	3492},
-	{"cvmx_pcierc#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5793,	2,	3493},
-	{"cvmx_pcierc#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5795,	24,	3495},
-	{"cvmx_pcierc#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5797,	4,	3519},
-	{"cvmx_pcierc#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5799,	5,	3523},
-	{"cvmx_pcierc#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5801,	1,	3528},
-	{"cvmx_pcierc#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5803,	1,	3529},
-	{"cvmx_pcierc#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5805,	4,	3530},
-	{"cvmx_pcierc#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5807,	17,	3534},
-	{"cvmx_pcierc#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5809,	4,	3551},
-	{"cvmx_pcierc#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5811,	6,	3555},
-	{"cvmx_pcierc#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5813,	1,	3561},
-	{"cvmx_pcierc#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5815,	1,	3562},
-	{"cvmx_pcierc#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5817,	2,	3563},
-	{"cvmx_pcierc#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5819,	2,	3565},
-	{"cvmx_pcierc#_cfg014"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5821,	1,	3567},
-	{"cvmx_pcierc#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5823,	15,	3568},
-	{"cvmx_pcierc#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5825,	10,	3583},
-	{"cvmx_pcierc#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5827,	12,	3593},
-	{"cvmx_pcierc#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5829,	7,	3605},
-	{"cvmx_pcierc#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5831,	2,	3612},
-	{"cvmx_pcierc#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5833,	1,	3614},
-	{"cvmx_pcierc#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5835,	2,	3615},
-	{"cvmx_pcierc#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5837,	7,	3617},
-	{"cvmx_pcierc#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5839,	11,	3624},
-	{"cvmx_pcierc#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5841,	19,	3635},
-	{"cvmx_pcierc#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5843,	11,	3654},
-	{"cvmx_pcierc#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5845,	20,	3665},
-	{"cvmx_pcierc#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5847,	12,	3685},
-	{"cvmx_pcierc#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5849,	22,	3697},
-	{"cvmx_pcierc#_cfg035"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5851,	8,	3719},
-	{"cvmx_pcierc#_cfg036"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5853,	4,	3727},
-	{"cvmx_pcierc#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5855,	3,	3731},
-	{"cvmx_pcierc#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5857,	3,	3734},
-	{"cvmx_pcierc#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5859,	1,	3737},
-	{"cvmx_pcierc#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5861,	11,	3738},
-	{"cvmx_pcierc#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5863,	1,	3749},
-	{"cvmx_pcierc#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5865,	1,	3750},
-	{"cvmx_pcierc#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5867,	3,	3751},
-	{"cvmx_pcierc#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5869,	14,	3754},
-	{"cvmx_pcierc#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5871,	14,	3768},
-	{"cvmx_pcierc#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5873,	14,	3782},
-	{"cvmx_pcierc#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5875,	9,	3796},
-	{"cvmx_pcierc#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5877,	9,	3805},
-	{"cvmx_pcierc#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5879,	6,	3814},
-	{"cvmx_pcierc#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5881,	1,	3820},
-	{"cvmx_pcierc#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5883,	1,	3821},
-	{"cvmx_pcierc#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5885,	1,	3822},
-	{"cvmx_pcierc#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5887,	1,	3823},
-	{"cvmx_pcierc#_cfg075"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5889,	4,	3824},
-	{"cvmx_pcierc#_cfg076"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5891,	9,	3828},
-	{"cvmx_pcierc#_cfg077"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5893,	2,	3837},
-	{"cvmx_pcierc#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5895,	2,	3839},
-	{"cvmx_pcierc#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5897,	1,	3841},
-	{"cvmx_pcierc#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5899,	6,	3842},
-	{"cvmx_pcierc#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5901,	6,	3848},
-	{"cvmx_pcierc#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5903,	13,	3854},
-	{"cvmx_pcierc#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5905,	5,	3867},
-	{"cvmx_pcierc#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5907,	8,	3872},
-	{"cvmx_pcierc#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5909,	19,	3880},
-	{"cvmx_pcierc#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5911,	3,	3899},
-	{"cvmx_pcierc#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5913,	1,	3902},
-	{"cvmx_pcierc#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5915,	1,	3903},
-	{"cvmx_pcierc#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5917,	3,	3904},
-	{"cvmx_pcierc#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5919,	3,	3907},
-	{"cvmx_pcierc#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5921,	3,	3910},
-	{"cvmx_pcierc#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5923,	4,	3913},
-	{"cvmx_pcierc#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5925,	4,	3917},
-	{"cvmx_pcierc#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5927,	4,	3921},
-	{"cvmx_pcierc#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5929,	7,	3925},
-	{"cvmx_pcierc#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5931,	5,	3932},
-	{"cvmx_pcierc#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5933,	5,	3937},
-	{"cvmx_pcierc#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5935,	4,	3942},
-	{"cvmx_pcierc#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5937,	4,	3946},
-	{"cvmx_pcierc#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5939,	4,	3950},
-	{"cvmx_pcierc#_cfg515"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5941,	7,	3954},
-	{"cvmx_pcierc#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5943,	1,	3961},
-	{"cvmx_pcierc#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5945,	1,	3962},
-	{"cvmx_pcs#_an#_adv_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5947,	9,	3963},
-	{"cvmx_pcs#_an#_ext_st_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5951,	6,	3972},
-	{"cvmx_pcs#_an#_lp_abil_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5955,	9,	3978},
-	{"cvmx_pcs#_an#_results_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5959,	6,	3987},
-	{"cvmx_pcs#_int#_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5963,	14,	3993},
-	{"cvmx_pcs#_int#_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5967,	14,	4007},
-	{"cvmx_pcs#_link#_timer_count_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	5971,	2,	4021},
-	{"cvmx_pcs#_log_anl#_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5975,	4,	4023},
-	{"cvmx_pcs#_misc#_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5979,	8,	4027},
-	{"cvmx_pcs#_mr#_control_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5983,	13,	4035},
-	{"cvmx_pcs#_mr#_status_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5987,	17,	4048},
-	{"cvmx_pcs#_rx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5991,	7,	4065},
-	{"cvmx_pcs#_rx#_sync_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5995,	3,	4072},
-	{"cvmx_pcs#_sgm#_an_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5999,	8,	4075},
-	{"cvmx_pcs#_sgm#_lp_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	6003,	7,	4083},
-	{"cvmx_pcs#_tx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6007,	4,	4090},
-	{"cvmx_pcs#_tx_rx#_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	6011,	5,	4094},
-	{"cvmx_pcsx#_10gbx_status_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	6015,	8,	4099},
-	{"cvmx_pcsx#_bist_status_reg"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6016,	2,	4107},
-	{"cvmx_pcsx#_bit_lock_status_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	6017,	5,	4109},
-	{"cvmx_pcsx#_control1_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6018,	10,	4114},
-	{"cvmx_pcsx#_control2_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6019,	2,	4124},
-	{"cvmx_pcsx#_int_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6020,	8,	4126},
-	{"cvmx_pcsx#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6021,	8,	4134},
-	{"cvmx_pcsx#_log_anl_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6022,	6,	4142},
-	{"cvmx_pcsx#_misc_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6023,	5,	4148},
-	{"cvmx_pcsx#_rx_sync_states_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	6024,	5,	4153},
-	{"cvmx_pcsx#_spd_abil_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6025,	3,	4158},
-	{"cvmx_pcsx#_status1_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6026,	6,	4161},
-	{"cvmx_pcsx#_status2_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6027,	9,	4167},
-	{"cvmx_pcsx#_tx_rx_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	6028,	5,	4176},
-	{"cvmx_pcsx#_tx_rx_states_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	6029,	10,	4181},
-	{"cvmx_pem#_bar1_index#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6030,	5,	4191},
-	{"cvmx_pem#_bar_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6062,	5,	4196},
-	{"cvmx_pem#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6064,	9,	4201},
-	{"cvmx_pem#_bist_status2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6066,	11,	4210},
-	{"cvmx_pem#_cfg_rd"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6068,	2,	4221},
-	{"cvmx_pem#_cfg_wr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6070,	2,	4223},
-	{"cvmx_pem#_cpl_lut_valid"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6072,	2,	4225},
-	{"cvmx_pem#_ctl_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6074,	18,	4227},
-	{"cvmx_pem#_dbg_info"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6076,	32,	4245},
-	{"cvmx_pem#_dbg_info_en"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6078,	32,	4277},
-	{"cvmx_pem#_diag_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6080,	5,	4309},
-	{"cvmx_pem#_int_enb"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6082,	15,	4314},
-	{"cvmx_pem#_int_enb_int"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6084,	15,	4329},
-	{"cvmx_pem#_int_sum"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6086,	15,	4344},
-	{"cvmx_pem#_p2n_bar0_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6088,	2,	4359},
-	{"cvmx_pem#_p2n_bar1_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6090,	2,	4361},
-	{"cvmx_pem#_p2n_bar2_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6092,	2,	4363},
-	{"cvmx_pem#_p2p_bar#_end"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6094,	2,	4365},
-	{"cvmx_pem#_p2p_bar#_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6102,	2,	4367},
-	{"cvmx_pem#_tlp_credits"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6110,	8,	4369},
-	{"cvmx_pip_bck_prs"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6112,	5,	4377},
-	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6113,	2,	4382},
-	{"cvmx_pip_clken"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	6114,	2,	4384},
-	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6115,	4,	4386},
-	{"cvmx_pip_dsa_src_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6119,	16,	4390},
-	{"cvmx_pip_dsa_vid_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6120,	16,	4406},
-	{"cvmx_pip_frm_len_chk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6121,	3,	4422},
-	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6122,	8,	4425},
-	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6123,	23,	4433},
-	{"cvmx_pip_hg_pri_qos"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6124,	6,	4456},
-	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	6125,	14,	4462},
-	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6126,	14,	4476},
-	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6127,	2,	4490},
-	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6128,	28,	4492},
-	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6144,	25,	4520},
-	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6160,	2,	4545},
-	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6224,	4,	4547},
-	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6232,	9,	4551},
-	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6240,	2,	4560},
-	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6241,	2,	4562},
-	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6242,	2,	4564},
-	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6254,	2,	4566},
-	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6266,	2,	4568},
-	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6278,	2,	4570},
-	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6290,	2,	4572},
-	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6302,	2,	4574},
-	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6314,	2,	4576},
-	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6326,	2,	4578},
-	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6338,	2,	4580},
-	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6350,	2,	4582},
-	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6362,	2,	4584},
-	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6363,	2,	4586},
-	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6379,	2,	4588},
-	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6395,	2,	4590},
-	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6411,	2,	4592},
-	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6475,	2,	4594},
-	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6476,	3,	4596},
-	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6477,	3,	4599},
-	{"cvmx_pip_xstat0_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6478,	2,	4602},
-	{"cvmx_pip_xstat1_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6482,	2,	4604},
-	{"cvmx_pip_xstat2_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6486,	2,	4606},
-	{"cvmx_pip_xstat3_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6490,	2,	4608},
-	{"cvmx_pip_xstat4_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6494,	2,	4610},
-	{"cvmx_pip_xstat5_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6498,	2,	4612},
-	{"cvmx_pip_xstat6_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6502,	2,	4614},
-	{"cvmx_pip_xstat7_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6506,	2,	4616},
-	{"cvmx_pip_xstat8_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6510,	2,	4618},
-	{"cvmx_pip_xstat9_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6514,	2,	4620},
-	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6518,	2,	4622},
-	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6519,	2,	4624},
-	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6520,	4,	4626},
-	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6521,	5,	4630},
-	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6522,	4,	4635},
-	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6523,	8,	4639},
-	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6524,	4,	4647},
-	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6525,	5,	4651},
-	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6526,	1,	4656},
-	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6527,	5,	4657},
-	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6528,	1,	4662},
-	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6529,	13,	4663},
-	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6530,	6,	4676},
-	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6531,	13,	4682},
-	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6532,	6,	4695},
-	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6533,	9,	4701},
-	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6534,	4,	4710},
-	{"cvmx_pko_mem_port_ptrs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6535,	7,	4714},
-	{"cvmx_pko_mem_port_qos"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6536,	5,	4721},
-	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6537,	5,	4726},
-	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6538,	4,	4731},
-	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6539,	9,	4735},
-	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6540,	5,	4744},
-	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6541,	16,	4749},
-	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6542,	4,	4765},
-	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6543,	1,	4769},
-	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6544,	1,	4770},
-	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6545,	1,	4771},
-	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6546,	1,	4772},
-	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	6547,	13,	4773},
-	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6548,	2,	4786},
-	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6549,	4,	4788},
-	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6550,	5,	4792},
-	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6551,	3,	4797},
-	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6552,	4,	4800},
-	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6553,	2,	4804},
-	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6554,	3,	4806},
-	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6555,	3,	4809},
-	{"cvmx_pko_reg_timestamp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6556,	2,	4812},
-	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6557,	10,	4814},
-	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	6558,	2,	4824},
-	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6559,	13,	4826},
-	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6560,	3,	4839},
-	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6561,	2,	4842},
-	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	6569,	2,	4844},
-	{"cvmx_pow_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6570,	2,	4846},
-	{"cvmx_pow_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6571,	2,	4848},
-	{"cvmx_pow_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6572,	2,	4850},
-	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6580,	2,	4852},
-	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6581,	2,	4854},
-	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	6582,	2,	4856},
-	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6583,	10,	4858},
-	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	6589,	5,	4868},
-	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	6597,	10,	4873},
-	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	6605,	2,	4883},
-	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6606,	2,	4885},
-	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6607,	2,	4887},
-	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6615,	3,	4889},
-	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6616,	6,	4892},
-	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6632,	5,	4898},
-	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6633,	7,	4903},
-	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6649,	2,	4910},
-	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6665,	1,	4912},
-	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6666,	1,	4913},
-	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6667,	1,	4914},
-	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6668,	5,	4915},
-	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6669,	5,	4920},
-	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6670,	4,	4925},
-	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6671,	10,	4929},
-	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6672,	1,	4939},
-	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6673,	3,	4940},
-	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6674,	7,	4943},
-	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6675,	2,	4950},
-	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6676,	1,	4952},
-	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6677,	1,	4953},
-	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6678,	1,	4954},
-	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6679,	18,	4955},
-	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6680,	3,	4973},
-	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6681,	2,	4976},
-	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6682,	3,	4978},
-	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6683,	7,	4981},
-	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6684,	2,	4988},
-	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6685,	2,	4990},
-	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6686,	2,	4992},
-	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6687,	3,	4994},
-	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6688,	3,	4997},
-	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6689,	9,	5000},
-	{"cvmx_rnm_eer_dbg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6690,	1,	5009},
-	{"cvmx_rnm_eer_key"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6691,	1,	5010},
-	{"cvmx_rnm_serial_num"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6692,	1,	5011},
-	{"cvmx_sli_bist_status"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6693,	25,	5012},
-	{"cvmx_sli_ctl_port#"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6694,	16,	5037},
-	{"cvmx_sli_ctl_status"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6696,	4,	5053},
-	{"cvmx_sli_data_out_cnt"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6697,	5,	5057},
-	{"cvmx_sli_dbg_data"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6698,	3,	5062},
-	{"cvmx_sli_dbg_select"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6699,	3,	5065},
-	{"cvmx_sli_dma#_cnt"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6700,	2,	5068},
-	{"cvmx_sli_dma#_int_level"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6702,	2,	5070},
-	{"cvmx_sli_dma#_tim"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6704,	2,	5072},
-	{"cvmx_sli_int_enb_ciu"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6706,	35,	5074},
-	{"cvmx_sli_int_enb_port#"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6707,	37,	5109},
-	{"cvmx_sli_int_sum"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6709,	37,	5146},
-	{"cvmx_sli_last_win_rdata0"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6710,	1,	5183},
-	{"cvmx_sli_last_win_rdata1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6711,	1,	5184},
-	{"cvmx_sli_mac_credit_cnt"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6712,	13,	5185},
-	{"cvmx_sli_mac_number"         ,	CVMX_CSR_DB_TYPE_PEXP,	64,	6713,	2,	5198},
-	{"cvmx_sli_mem_access_ctl"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6714,	3,	5200},
-	{"cvmx_sli_mem_access_subid#"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6715,	9,	5203},
-	{"cvmx_sli_msi_enb0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6731,	1,	5212},
-	{"cvmx_sli_msi_enb1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6732,	1,	5213},
-	{"cvmx_sli_msi_enb2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6733,	1,	5214},
-	{"cvmx_sli_msi_enb3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6734,	1,	5215},
-	{"cvmx_sli_msi_rcv0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6735,	1,	5216},
-	{"cvmx_sli_msi_rcv1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6736,	1,	5217},
-	{"cvmx_sli_msi_rcv2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6737,	1,	5218},
-	{"cvmx_sli_msi_rcv3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6738,	1,	5219},
-	{"cvmx_sli_msi_rd_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6739,	3,	5220},
-	{"cvmx_sli_msi_w1c_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6740,	1,	5223},
-	{"cvmx_sli_msi_w1c_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6741,	1,	5224},
-	{"cvmx_sli_msi_w1c_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6742,	1,	5225},
-	{"cvmx_sli_msi_w1c_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6743,	1,	5226},
-	{"cvmx_sli_msi_w1s_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6744,	1,	5227},
-	{"cvmx_sli_msi_w1s_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6745,	1,	5228},
-	{"cvmx_sli_msi_w1s_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6746,	1,	5229},
-	{"cvmx_sli_msi_w1s_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6747,	1,	5230},
-	{"cvmx_sli_msi_wr_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6748,	3,	5231},
-	{"cvmx_sli_pcie_msi_rcv"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6749,	2,	5234},
-	{"cvmx_sli_pcie_msi_rcv_b1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6750,	3,	5236},
-	{"cvmx_sli_pcie_msi_rcv_b2"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6751,	3,	5239},
-	{"cvmx_sli_pcie_msi_rcv_b3"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6752,	3,	5242},
-	{"cvmx_sli_pkt#_cnts"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6753,	3,	5245},
-	{"cvmx_sli_pkt#_in_bp"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6785,	2,	5248},
-	{"cvmx_sli_pkt#_instr_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6817,	2,	5250},
-	{"cvmx_sli_pkt#_instr_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6849,	2,	5252},
-	{"cvmx_sli_pkt#_instr_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6881,	5,	5254},
-	{"cvmx_sli_pkt#_instr_header"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6913,	21,	5259},
-	{"cvmx_sli_pkt#_out_size"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6945,	3,	5280},
-	{"cvmx_sli_pkt#_slist_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6977,	2,	5283},
-	{"cvmx_sli_pkt#_slist_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7009,	2,	5285},
-	{"cvmx_sli_pkt#_slist_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7041,	2,	5287},
-	{"cvmx_sli_pkt_cnt_int"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7073,	2,	5289},
-	{"cvmx_sli_pkt_cnt_int_enb"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7074,	2,	5291},
-	{"cvmx_sli_pkt_ctl"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7075,	3,	5293},
-	{"cvmx_sli_pkt_data_out_es"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7076,	1,	5296},
-	{"cvmx_sli_pkt_data_out_ns"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7077,	2,	5297},
-	{"cvmx_sli_pkt_data_out_ror"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7078,	2,	5299},
-	{"cvmx_sli_pkt_dpaddr"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7079,	2,	5301},
-	{"cvmx_sli_pkt_in_bp"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7080,	2,	5303},
-	{"cvmx_sli_pkt_in_done#_cnts"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7081,	2,	5305},
-	{"cvmx_sli_pkt_in_instr_counts",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7113,	2,	5307},
-	{"cvmx_sli_pkt_in_pcie_port"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7114,	1,	5309},
-	{"cvmx_sli_pkt_input_control"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7115,	10,	5310},
-	{"cvmx_sli_pkt_instr_enb"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7116,	2,	5320},
-	{"cvmx_sli_pkt_instr_rd_size"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7117,	1,	5322},
-	{"cvmx_sli_pkt_instr_size"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7118,	2,	5323},
-	{"cvmx_sli_pkt_int_levels"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7119,	3,	5325},
-	{"cvmx_sli_pkt_iptr"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7120,	2,	5328},
-	{"cvmx_sli_pkt_out_bmode"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7121,	2,	5330},
-	{"cvmx_sli_pkt_out_enb"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7122,	2,	5332},
-	{"cvmx_sli_pkt_output_wmark"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7123,	2,	5334},
-	{"cvmx_sli_pkt_pcie_port"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7124,	1,	5336},
-	{"cvmx_sli_pkt_port_in_rst"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7125,	2,	5337},
-	{"cvmx_sli_pkt_slist_es"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7126,	1,	5339},
-	{"cvmx_sli_pkt_slist_ns"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7127,	2,	5340},
-	{"cvmx_sli_pkt_slist_ror"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7128,	2,	5342},
-	{"cvmx_sli_pkt_time_int"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7129,	2,	5344},
-	{"cvmx_sli_pkt_time_int_enb"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7130,	2,	5346},
-	{"cvmx_sli_s2m_port#_ctl"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7131,	4,	5348},
-	{"cvmx_sli_scratch_1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7133,	1,	5352},
-	{"cvmx_sli_scratch_2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7134,	1,	5353},
-	{"cvmx_sli_state1"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7135,	4,	5354},
-	{"cvmx_sli_state2"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7136,	8,	5358},
-	{"cvmx_sli_state3"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7137,	5,	5366},
-	{"cvmx_sli_win_rd_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7138,	4,	5371},
-	{"cvmx_sli_win_rd_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7139,	1,	5375},
-	{"cvmx_sli_win_wr_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7140,	4,	5376},
-	{"cvmx_sli_win_wr_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7141,	1,	5380},
-	{"cvmx_sli_win_wr_mask"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7142,	2,	5381},
-	{"cvmx_sli_window_ctl"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7143,	2,	5383},
-	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7144,	10,	5385},
-	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7146,	6,	5395},
-	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	7148,	2,	5401},
-	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7150,	4,	5403},
-	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7152,	4,	5407},
-	{"cvmx_smi_drv_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7154,	4,	5411},
-	{"cvmx_srio#_acc_ctrl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7155,	4,	5415},
-	{"cvmx_srio#_asmbly_id"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7157,	3,	5419},
-	{"cvmx_srio#_asmbly_info"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7159,	3,	5422},
-	{"cvmx_srio#_bell_resp_ctrl"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7161,	5,	5425},
-	{"cvmx_srio#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7163,	19,	5430},
-	{"cvmx_srio#_imsg_ctrl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7165,	14,	5449},
-	{"cvmx_srio#_imsg_inst_hdr#"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7167,	14,	5463},
-	{"cvmx_srio#_imsg_qos_grp#"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7171,	24,	5477},
-	{"cvmx_srio#_imsg_status#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7235,	24,	5501},
-	{"cvmx_srio#_imsg_vport_thr"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7283,	13,	5525},
-	{"cvmx_srio#_int2_enable"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7285,	2,	5538},
-	{"cvmx_srio#_int2_reg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7287,	4,	5540},
-	{"cvmx_srio#_int_enable"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7289,	27,	5544},
-	{"cvmx_srio#_int_info0"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7291,	9,	5571},
-	{"cvmx_srio#_int_info1"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7293,	1,	5580},
-	{"cvmx_srio#_int_info2"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7295,	11,	5581},
-	{"cvmx_srio#_int_info3"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7297,	5,	5592},
-	{"cvmx_srio#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7299,	29,	5597},
-	{"cvmx_srio#_ip_feature"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7301,	9,	5626},
-	{"cvmx_srio#_mac_buffers"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7303,	10,	5635},
-	{"cvmx_srio#_maint_op"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7305,	6,	5645},
-	{"cvmx_srio#_maint_rd_data"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7307,	3,	5651},
-	{"cvmx_srio#_mce_tx_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7309,	2,	5654},
-	{"cvmx_srio#_mem_op_ctrl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7311,	8,	5656},
-	{"cvmx_srio#_omsg_ctrl#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7313,	11,	5664},
-	{"cvmx_srio#_omsg_done_counts#",	CVMX_CSR_DB_TYPE_RSL,	64,	7317,	3,	5675},
-	{"cvmx_srio#_omsg_fmp_mr#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7321,	16,	5678},
-	{"cvmx_srio#_omsg_nmp_mr#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7325,	16,	5694},
-	{"cvmx_srio#_omsg_port#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7329,	4,	5710},
-	{"cvmx_srio#_omsg_silo_thr"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7333,	2,	5714},
-	{"cvmx_srio#_omsg_sp_mr#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7335,	17,	5716},
-	{"cvmx_srio#_prio#_in_use"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7339,	3,	5733},
-	{"cvmx_srio#_rx_bell"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7347,	9,	5736},
-	{"cvmx_srio#_rx_bell_seq"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7349,	3,	5745},
-	{"cvmx_srio#_rx_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7351,	9,	5748},
-	{"cvmx_srio#_s2m_type#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7353,	11,	5757},
-	{"cvmx_srio#_seq"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	7385,	2,	5768},
-	{"cvmx_srio#_status_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7387,	3,	5770},
-	{"cvmx_srio#_tag_ctrl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7389,	6,	5773},
-	{"cvmx_srio#_tlp_credits"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7391,	6,	5779},
-	{"cvmx_srio#_tx_bell"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7393,	10,	5785},
-	{"cvmx_srio#_tx_bell_info"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7395,	11,	5795},
-	{"cvmx_srio#_tx_ctrl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7397,	12,	5806},
-	{"cvmx_srio#_tx_emphasis"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7399,	2,	5818},
-	{"cvmx_srio#_tx_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7401,	5,	5820},
-	{"cvmx_srio#_wr_done_counts"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7403,	3,	5825},
-	{"cvmx_sriomaint#_asmbly_id"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7405,	2,	5828},
-	{"cvmx_sriomaint#_asmbly_info" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7407,	2,	5830},
-	{"cvmx_sriomaint#_bar1_idx#"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7409,	7,	5832},
-	{"cvmx_sriomaint#_bell_status" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7441,	2,	5839},
-	{"cvmx_sriomaint#_comp_tag"    ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7443,	1,	5841},
-	{"cvmx_sriomaint#_core_enables",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7445,	6,	5842},
-	{"cvmx_sriomaint#_dev_id"      ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7447,	2,	5848},
-	{"cvmx_sriomaint#_dev_rev"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7449,	2,	5850},
-	{"cvmx_sriomaint#_dst_ops"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7451,	26,	5852},
-	{"cvmx_sriomaint#_erb_attr_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7453,	5,	5878},
-	{"cvmx_sriomaint#_erb_err_det" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7455,	17,	5883},
-	{"cvmx_sriomaint#_erb_err_rate",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7457,	5,	5900},
-	{"cvmx_sriomaint#_erb_err_rate_en",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7459,	17,	5905},
-	{"cvmx_sriomaint#_erb_err_rate_thr",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7461,	3,	5922},
-	{"cvmx_sriomaint#_erb_hdr"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7463,	2,	5925},
-	{"cvmx_sriomaint#_erb_lt_addr_capt_h",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7465,	1,	5927},
-	{"cvmx_sriomaint#_erb_lt_addr_capt_l",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7467,	3,	5928},
-	{"cvmx_sriomaint#_erb_lt_ctrl_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7469,	9,	5931},
-	{"cvmx_sriomaint#_erb_lt_dev_id",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7471,	4,	5940},
-	{"cvmx_sriomaint#_erb_lt_dev_id_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7473,	4,	5944},
-	{"cvmx_sriomaint#_erb_lt_err_det",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7475,	12,	5948},
-	{"cvmx_sriomaint#_erb_lt_err_en",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7477,	12,	5960},
-	{"cvmx_sriomaint#_erb_pack_capt_1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7479,	1,	5972},
-	{"cvmx_sriomaint#_erb_pack_capt_2",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7481,	1,	5973},
-	{"cvmx_sriomaint#_erb_pack_capt_3",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7483,	1,	5974},
-	{"cvmx_sriomaint#_erb_pack_sym_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7485,	1,	5975},
-	{"cvmx_sriomaint#_hb_dev_id_lock",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7487,	2,	5976},
-	{"cvmx_sriomaint#_ir_buffer_config",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7489,	7,	5978},
-	{"cvmx_sriomaint#_ir_buffer_config2",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7491,	8,	5985},
-	{"cvmx_sriomaint#_ir_pd_phy_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7493,	1,	5993},
-	{"cvmx_sriomaint#_ir_pd_phy_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7495,	9,	5994},
-	{"cvmx_sriomaint#_ir_pi_phy_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7497,	5,	6003},
-	{"cvmx_sriomaint#_ir_pi_phy_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7499,	4,	6008},
-	{"cvmx_sriomaint#_ir_sp_rx_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7501,	2,	6012},
-	{"cvmx_sriomaint#_ir_sp_rx_data",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7503,	1,	6014},
-	{"cvmx_sriomaint#_ir_sp_rx_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7505,	5,	6015},
-	{"cvmx_sriomaint#_ir_sp_tx_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7507,	2,	6020},
-	{"cvmx_sriomaint#_ir_sp_tx_data",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7509,	1,	6022},
-	{"cvmx_sriomaint#_ir_sp_tx_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7511,	5,	6023},
-	{"cvmx_sriomaint#_lane_#_status_0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7513,	15,	6028},
-	{"cvmx_sriomaint#_lcs_ba0"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7521,	2,	6043},
-	{"cvmx_sriomaint#_lcs_ba1"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7523,	2,	6045},
-	{"cvmx_sriomaint#_m2s_bar0_start0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7525,	2,	6047},
-	{"cvmx_sriomaint#_m2s_bar0_start1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7527,	4,	6049},
-	{"cvmx_sriomaint#_m2s_bar1_start0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7529,	2,	6053},
-	{"cvmx_sriomaint#_m2s_bar1_start1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7531,	5,	6055},
-	{"cvmx_sriomaint#_m2s_bar2_start",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7533,	7,	6060},
-	{"cvmx_sriomaint#_mac_ctrl"    ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7535,	5,	6067},
-	{"cvmx_sriomaint#_pe_feat"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7537,	11,	6072},
-	{"cvmx_sriomaint#_pe_llc"      ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7539,	2,	6083},
-	{"cvmx_sriomaint#_port_0_ctl"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7541,	18,	6085},
-	{"cvmx_sriomaint#_port_0_ctl2" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7543,	16,	6103},
-	{"cvmx_sriomaint#_port_0_err_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7545,	20,	6119},
-	{"cvmx_sriomaint#_port_0_link_req",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7547,	2,	6139},
-	{"cvmx_sriomaint#_port_0_link_resp",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7549,	4,	6141},
-	{"cvmx_sriomaint#_port_0_local_ackid",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7551,	6,	6145},
-	{"cvmx_sriomaint#_port_gen_ctl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7553,	4,	6151},
-	{"cvmx_sriomaint#_port_lt_ctl" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7555,	2,	6155},
-	{"cvmx_sriomaint#_port_mbh0"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7557,	2,	6157},
-	{"cvmx_sriomaint#_port_rt_ctl" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7559,	2,	6159},
-	{"cvmx_sriomaint#_port_ttl_ctl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7561,	2,	6161},
-	{"cvmx_sriomaint#_pri_dev_id"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7563,	3,	6163},
-	{"cvmx_sriomaint#_sec_dev_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7565,	3,	6166},
-	{"cvmx_sriomaint#_sec_dev_id"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7567,	3,	6169},
-	{"cvmx_sriomaint#_serial_lane_hdr",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7569,	2,	6172},
-	{"cvmx_sriomaint#_src_ops"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7571,	26,	6174},
-	{"cvmx_sriomaint#_tx_drop"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7573,	3,	6200},
-	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7575,	6,	6203},
-	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7576,	3,	6209},
-	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7577,	5,	6212},
-	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7578,	4,	6217},
-	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7579,	6,	6221},
-	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7580,	4,	6227},
-	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7581,	2,	6231},
-	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7582,	4,	6233},
-	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7583,	2,	6237},
-	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7584,	3,	6239},
-	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7585,	2,	6242},
-	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	7586,	14,	6244},
-	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7587,	3,	6258},
-	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7588,	5,	6261},
-	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7589,	2,	6266},
-	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7590,	2,	6268},
-	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7591,	57,	6270},
-	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7592,	20,	6327},
-	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7593,	7,	6347},
-	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7594,	5,	6354},
-	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7595,	1,	6359},
-	{"cvmx_tra_read_dat_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7596,	2,	6360},
-	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7597,	2,	6362},
-	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7598,	2,	6364},
-	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7599,	57,	6366},
-	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7600,	20,	6423},
-	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7601,	7,	6443},
-	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7602,	2,	6450},
-	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7603,	2,	6452},
-	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7604,	57,	6454},
-	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7605,	20,	6511},
-	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7606,	7,	6531},
-	{"cvmx_uahc#_ehci_asynclistaddr",	CVMX_CSR_DB_TYPE_NCB,	32,	7607,	2,	6538},
-	{"cvmx_uahc#_ehci_configflag"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7608,	2,	6540},
-	{"cvmx_uahc#_ehci_ctrldssegment",	CVMX_CSR_DB_TYPE_NCB,	32,	7609,	1,	6542},
-	{"cvmx_uahc#_ehci_frindex"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7610,	2,	6543},
-	{"cvmx_uahc#_ehci_hccapbase"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7611,	3,	6545},
-	{"cvmx_uahc#_ehci_hccparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7612,	7,	6548},
-	{"cvmx_uahc#_ehci_hcsparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7613,	10,	6555},
-	{"cvmx_uahc#_ehci_insnreg00"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7614,	3,	6565},
-	{"cvmx_uahc#_ehci_insnreg03"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7615,	5,	6568},
-	{"cvmx_uahc#_ehci_insnreg04"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7616,	7,	6573},
-	{"cvmx_uahc#_ehci_insnreg06"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7617,	2,	6580},
-	{"cvmx_uahc#_ehci_insnreg07"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7618,	1,	6582},
-	{"cvmx_uahc#_ehci_periodiclistbase",	CVMX_CSR_DB_TYPE_NCB,	32,	7619,	2,	6583},
-	{"cvmx_uahc#_ehci_portsc#"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7620,	19,	6585},
-	{"cvmx_uahc#_ehci_usbcmd"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	7622,	13,	6604},
-	{"cvmx_uahc#_ehci_usbintr"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7623,	7,	6617},
-	{"cvmx_uahc#_ehci_usbsts"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	7624,	12,	6624},
-	{"cvmx_uahc#_ohci0_hcbulkcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7625,	2,	6636},
-	{"cvmx_uahc#_ohci0_hcbulkheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	7626,	2,	6638},
-	{"cvmx_uahc#_ohci0_hccommandstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	7627,	7,	6640},
-	{"cvmx_uahc#_ohci0_hccontrol"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7628,	10,	6647},
-	{"cvmx_uahc#_ohci0_hccontrolcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7629,	2,	6657},
-	{"cvmx_uahc#_ohci0_hccontrolheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	7630,	2,	6659},
-	{"cvmx_uahc#_ohci0_hcdonehead" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7631,	2,	6661},
-	{"cvmx_uahc#_ohci0_hcfminterval",	CVMX_CSR_DB_TYPE_NCB,	32,	7632,	4,	6663},
-	{"cvmx_uahc#_ohci0_hcfmnumber" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7633,	2,	6667},
-	{"cvmx_uahc#_ohci0_hcfmremaining",	CVMX_CSR_DB_TYPE_NCB,	32,	7634,	3,	6669},
-	{"cvmx_uahc#_ohci0_hchcca"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7635,	2,	6672},
-	{"cvmx_uahc#_ohci0_hcinterruptdisable",	CVMX_CSR_DB_TYPE_NCB,	32,	7636,	10,	6674},
-	{"cvmx_uahc#_ohci0_hcinterruptenable",	CVMX_CSR_DB_TYPE_NCB,	32,	7637,	10,	6684},
-	{"cvmx_uahc#_ohci0_hcinterruptstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	7638,	10,	6694},
-	{"cvmx_uahc#_ohci0_hclsthreshold",	CVMX_CSR_DB_TYPE_NCB,	32,	7639,	2,	6704},
-	{"cvmx_uahc#_ohci0_hcperiodcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7640,	2,	6706},
-	{"cvmx_uahc#_ohci0_hcperiodicstart",	CVMX_CSR_DB_TYPE_NCB,	32,	7641,	2,	6708},
-	{"cvmx_uahc#_ohci0_hcrevision" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7642,	2,	6710},
-	{"cvmx_uahc#_ohci0_hcrhdescriptora",	CVMX_CSR_DB_TYPE_NCB,	32,	7643,	8,	6712},
-	{"cvmx_uahc#_ohci0_hcrhdescriptorb",	CVMX_CSR_DB_TYPE_NCB,	32,	7644,	2,	6720},
-	{"cvmx_uahc#_ohci0_hcrhportstatus#",	CVMX_CSR_DB_TYPE_NCB,	32,	7645,	15,	6722},
-	{"cvmx_uahc#_ohci0_hcrhstatus" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7647,	8,	6737},
-	{"cvmx_uahc#_ohci0_insnreg06"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7648,	2,	6745},
-	{"cvmx_uahc#_ohci0_insnreg07"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7649,	1,	6747},
-	{"cvmx_uctl#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7650,	7,	6748},
-	{"cvmx_uctl#_clk_rst_ctl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7651,	21,	6755},
-	{"cvmx_uctl#_ehci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7652,	12,	6776},
-	{"cvmx_uctl#_ehci_fla"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7653,	2,	6788},
-	{"cvmx_uctl#_erto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7654,	3,	6790},
-	{"cvmx_uctl#_if_ena"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7655,	2,	6793},
-	{"cvmx_uctl#_int_ena"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7656,	9,	6795},
-	{"cvmx_uctl#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7657,	9,	6804},
-	{"cvmx_uctl#_ohci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7658,	11,	6813},
-	{"cvmx_uctl#_orto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7659,	3,	6824},
-	{"cvmx_uctl#_ppaf_wm"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7660,	2,	6827},
-	{"cvmx_uctl#_uphy_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	7661,	11,	6829},
-	{"cvmx_uctl#_uphy_port#_ctl_status",	CVMX_CSR_DB_TYPE_RSL,	64,	7662,	20,	6840},
-	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7664,	3,	6860},
-	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7665,	5,	6863},
-	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7666,	3,	6868},
-	{"cvmx_zip_constants"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7667,	6,	6871},
-	{"cvmx_zip_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	7668,	2,	6877},
-	{"cvmx_zip_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	7669,	2,	6879},
-	{"cvmx_zip_int_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7670,	2,	6881},
-	{"cvmx_zip_throttle"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7671,	2,	6883},
+	{"cvmx_pcieep#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5711,	4,	3282},
+	{"cvmx_pcieep#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5713,	11,	3286},
+	{"cvmx_pcieep#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5715,	1,	3297},
+	{"cvmx_pcieep#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5717,	1,	3298},
+	{"cvmx_pcieep#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5719,	3,	3299},
+	{"cvmx_pcieep#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5721,	14,	3302},
+	{"cvmx_pcieep#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5723,	14,	3316},
+	{"cvmx_pcieep#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5725,	14,	3330},
+	{"cvmx_pcieep#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5727,	9,	3344},
+	{"cvmx_pcieep#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5729,	9,	3353},
+	{"cvmx_pcieep#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5731,	6,	3362},
+	{"cvmx_pcieep#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5733,	1,	3368},
+	{"cvmx_pcieep#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5735,	1,	3369},
+	{"cvmx_pcieep#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5737,	1,	3370},
+	{"cvmx_pcieep#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5739,	1,	3371},
+	{"cvmx_pcieep#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5741,	2,	3372},
+	{"cvmx_pcieep#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5743,	1,	3374},
+	{"cvmx_pcieep#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5745,	6,	3375},
+	{"cvmx_pcieep#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5747,	6,	3381},
+	{"cvmx_pcieep#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5749,	13,	3387},
+	{"cvmx_pcieep#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5751,	5,	3400},
+	{"cvmx_pcieep#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5753,	8,	3405},
+	{"cvmx_pcieep#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5755,	19,	3413},
+	{"cvmx_pcieep#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5757,	3,	3432},
+	{"cvmx_pcieep#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5759,	1,	3435},
+	{"cvmx_pcieep#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5761,	1,	3436},
+	{"cvmx_pcieep#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5763,	3,	3437},
+	{"cvmx_pcieep#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5765,	3,	3440},
+	{"cvmx_pcieep#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5767,	3,	3443},
+	{"cvmx_pcieep#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5769,	4,	3446},
+	{"cvmx_pcieep#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5771,	4,	3450},
+	{"cvmx_pcieep#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5773,	4,	3454},
+	{"cvmx_pcieep#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5775,	7,	3458},
+	{"cvmx_pcieep#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5777,	5,	3465},
+	{"cvmx_pcieep#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5779,	5,	3470},
+	{"cvmx_pcieep#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5781,	4,	3475},
+	{"cvmx_pcieep#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5783,	4,	3479},
+	{"cvmx_pcieep#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5785,	4,	3483},
+	{"cvmx_pcieep#_cfg515"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5787,	7,	3487},
+	{"cvmx_pcieep#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5789,	1,	3494},
+	{"cvmx_pcieep#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5791,	1,	3495},
+	{"cvmx_pcierc#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5793,	2,	3496},
+	{"cvmx_pcierc#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5795,	24,	3498},
+	{"cvmx_pcierc#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5797,	4,	3522},
+	{"cvmx_pcierc#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5799,	5,	3526},
+	{"cvmx_pcierc#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5801,	1,	3531},
+	{"cvmx_pcierc#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5803,	1,	3532},
+	{"cvmx_pcierc#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5805,	4,	3533},
+	{"cvmx_pcierc#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5807,	17,	3537},
+	{"cvmx_pcierc#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5809,	4,	3554},
+	{"cvmx_pcierc#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5811,	6,	3558},
+	{"cvmx_pcierc#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5813,	1,	3564},
+	{"cvmx_pcierc#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5815,	1,	3565},
+	{"cvmx_pcierc#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5817,	2,	3566},
+	{"cvmx_pcierc#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5819,	2,	3568},
+	{"cvmx_pcierc#_cfg014"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5821,	1,	3570},
+	{"cvmx_pcierc#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5823,	15,	3571},
+	{"cvmx_pcierc#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5825,	10,	3586},
+	{"cvmx_pcierc#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5827,	12,	3596},
+	{"cvmx_pcierc#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5829,	7,	3608},
+	{"cvmx_pcierc#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5831,	2,	3615},
+	{"cvmx_pcierc#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5833,	1,	3617},
+	{"cvmx_pcierc#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5835,	2,	3618},
+	{"cvmx_pcierc#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5837,	7,	3620},
+	{"cvmx_pcierc#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5839,	11,	3627},
+	{"cvmx_pcierc#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5841,	19,	3638},
+	{"cvmx_pcierc#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5843,	11,	3657},
+	{"cvmx_pcierc#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5845,	20,	3668},
+	{"cvmx_pcierc#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5847,	12,	3688},
+	{"cvmx_pcierc#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5849,	22,	3700},
+	{"cvmx_pcierc#_cfg035"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5851,	8,	3722},
+	{"cvmx_pcierc#_cfg036"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5853,	4,	3730},
+	{"cvmx_pcierc#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5855,	3,	3734},
+	{"cvmx_pcierc#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5857,	3,	3737},
+	{"cvmx_pcierc#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5859,	4,	3740},
+	{"cvmx_pcierc#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5861,	11,	3744},
+	{"cvmx_pcierc#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5863,	1,	3755},
+	{"cvmx_pcierc#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5865,	1,	3756},
+	{"cvmx_pcierc#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5867,	3,	3757},
+	{"cvmx_pcierc#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5869,	14,	3760},
+	{"cvmx_pcierc#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5871,	14,	3774},
+	{"cvmx_pcierc#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5873,	14,	3788},
+	{"cvmx_pcierc#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5875,	9,	3802},
+	{"cvmx_pcierc#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5877,	9,	3811},
+	{"cvmx_pcierc#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5879,	6,	3820},
+	{"cvmx_pcierc#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5881,	1,	3826},
+	{"cvmx_pcierc#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5883,	1,	3827},
+	{"cvmx_pcierc#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5885,	1,	3828},
+	{"cvmx_pcierc#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5887,	1,	3829},
+	{"cvmx_pcierc#_cfg075"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5889,	4,	3830},
+	{"cvmx_pcierc#_cfg076"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5891,	9,	3834},
+	{"cvmx_pcierc#_cfg077"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5893,	2,	3843},
+	{"cvmx_pcierc#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5895,	2,	3845},
+	{"cvmx_pcierc#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5897,	1,	3847},
+	{"cvmx_pcierc#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5899,	6,	3848},
+	{"cvmx_pcierc#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5901,	6,	3854},
+	{"cvmx_pcierc#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5903,	13,	3860},
+	{"cvmx_pcierc#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5905,	5,	3873},
+	{"cvmx_pcierc#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5907,	8,	3878},
+	{"cvmx_pcierc#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5909,	19,	3886},
+	{"cvmx_pcierc#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5911,	3,	3905},
+	{"cvmx_pcierc#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5913,	1,	3908},
+	{"cvmx_pcierc#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5915,	1,	3909},
+	{"cvmx_pcierc#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5917,	3,	3910},
+	{"cvmx_pcierc#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5919,	3,	3913},
+	{"cvmx_pcierc#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5921,	3,	3916},
+	{"cvmx_pcierc#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5923,	4,	3919},
+	{"cvmx_pcierc#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5925,	4,	3923},
+	{"cvmx_pcierc#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5927,	4,	3927},
+	{"cvmx_pcierc#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5929,	7,	3931},
+	{"cvmx_pcierc#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5931,	5,	3938},
+	{"cvmx_pcierc#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5933,	5,	3943},
+	{"cvmx_pcierc#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5935,	4,	3948},
+	{"cvmx_pcierc#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5937,	4,	3952},
+	{"cvmx_pcierc#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5939,	4,	3956},
+	{"cvmx_pcierc#_cfg515"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5941,	7,	3960},
+	{"cvmx_pcierc#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5943,	1,	3967},
+	{"cvmx_pcierc#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5945,	1,	3968},
+	{"cvmx_pcs#_an#_adv_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5947,	9,	3969},
+	{"cvmx_pcs#_an#_ext_st_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5951,	6,	3978},
+	{"cvmx_pcs#_an#_lp_abil_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5955,	9,	3984},
+	{"cvmx_pcs#_an#_results_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5959,	6,	3993},
+	{"cvmx_pcs#_int#_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5963,	14,	3999},
+	{"cvmx_pcs#_int#_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5967,	14,	4013},
+	{"cvmx_pcs#_link#_timer_count_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	5971,	2,	4027},
+	{"cvmx_pcs#_log_anl#_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5975,	4,	4029},
+	{"cvmx_pcs#_misc#_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5979,	8,	4033},
+	{"cvmx_pcs#_mr#_control_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5983,	13,	4041},
+	{"cvmx_pcs#_mr#_status_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5987,	17,	4054},
+	{"cvmx_pcs#_rx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5991,	7,	4071},
+	{"cvmx_pcs#_rx#_sync_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5995,	3,	4078},
+	{"cvmx_pcs#_sgm#_an_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5999,	8,	4081},
+	{"cvmx_pcs#_sgm#_lp_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	6003,	7,	4089},
+	{"cvmx_pcs#_tx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6007,	4,	4096},
+	{"cvmx_pcs#_tx_rx#_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	6011,	5,	4100},
+	{"cvmx_pcsx#_10gbx_status_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	6015,	8,	4105},
+	{"cvmx_pcsx#_bist_status_reg"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6016,	2,	4113},
+	{"cvmx_pcsx#_bit_lock_status_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	6017,	5,	4115},
+	{"cvmx_pcsx#_control1_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6018,	10,	4120},
+	{"cvmx_pcsx#_control2_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6019,	2,	4130},
+	{"cvmx_pcsx#_int_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6020,	8,	4132},
+	{"cvmx_pcsx#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6021,	8,	4140},
+	{"cvmx_pcsx#_log_anl_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6022,	6,	4148},
+	{"cvmx_pcsx#_misc_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6023,	5,	4154},
+	{"cvmx_pcsx#_rx_sync_states_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	6024,	5,	4159},
+	{"cvmx_pcsx#_spd_abil_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6025,	3,	4164},
+	{"cvmx_pcsx#_status1_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6026,	6,	4167},
+	{"cvmx_pcsx#_status2_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6027,	9,	4173},
+	{"cvmx_pcsx#_tx_rx_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	6028,	5,	4182},
+	{"cvmx_pcsx#_tx_rx_states_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	6029,	10,	4187},
+	{"cvmx_pem#_bar1_index#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6030,	5,	4197},
+	{"cvmx_pem#_bar_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6062,	5,	4202},
+	{"cvmx_pem#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6064,	9,	4207},
+	{"cvmx_pem#_bist_status2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6066,	11,	4216},
+	{"cvmx_pem#_cfg_rd"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6068,	2,	4227},
+	{"cvmx_pem#_cfg_wr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6070,	2,	4229},
+	{"cvmx_pem#_cpl_lut_valid"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6072,	2,	4231},
+	{"cvmx_pem#_ctl_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6074,	18,	4233},
+	{"cvmx_pem#_dbg_info"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6076,	32,	4251},
+	{"cvmx_pem#_dbg_info_en"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6078,	32,	4283},
+	{"cvmx_pem#_diag_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6080,	5,	4315},
+	{"cvmx_pem#_int_enb"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6082,	15,	4320},
+	{"cvmx_pem#_int_enb_int"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6084,	15,	4335},
+	{"cvmx_pem#_int_sum"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6086,	15,	4350},
+	{"cvmx_pem#_p2n_bar0_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6088,	2,	4365},
+	{"cvmx_pem#_p2n_bar1_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6090,	2,	4367},
+	{"cvmx_pem#_p2n_bar2_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6092,	2,	4369},
+	{"cvmx_pem#_p2p_bar#_end"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6094,	2,	4371},
+	{"cvmx_pem#_p2p_bar#_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6102,	2,	4373},
+	{"cvmx_pem#_tlp_credits"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6110,	8,	4375},
+	{"cvmx_pip_bck_prs"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6112,	5,	4383},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6113,	2,	4388},
+	{"cvmx_pip_clken"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	6114,	2,	4390},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6115,	4,	4392},
+	{"cvmx_pip_dsa_src_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6119,	16,	4396},
+	{"cvmx_pip_dsa_vid_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6120,	16,	4412},
+	{"cvmx_pip_frm_len_chk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6121,	3,	4428},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6122,	8,	4431},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6123,	23,	4439},
+	{"cvmx_pip_hg_pri_qos"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6124,	6,	4462},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	6125,	14,	4468},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6126,	14,	4482},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6127,	2,	4496},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6128,	28,	4498},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6144,	25,	4526},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6160,	2,	4551},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6224,	4,	4553},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6232,	9,	4557},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6240,	2,	4566},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6241,	2,	4568},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6242,	2,	4570},
+	{"cvmx_pip_stat10_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6254,	2,	4572},
+	{"cvmx_pip_stat11_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6266,	2,	4574},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6278,	2,	4576},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6290,	2,	4578},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6302,	2,	4580},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6314,	2,	4582},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6326,	2,	4584},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6338,	2,	4586},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6350,	2,	4588},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6362,	2,	4590},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6374,	2,	4592},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6386,	2,	4594},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6387,	2,	4596},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6403,	2,	4598},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6419,	2,	4600},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6435,	2,	4602},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6499,	2,	4604},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6500,	3,	4606},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6501,	3,	4609},
+	{"cvmx_pip_xstat0_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6502,	2,	4612},
+	{"cvmx_pip_xstat10_prt#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6506,	2,	4614},
+	{"cvmx_pip_xstat11_prt#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6510,	2,	4616},
+	{"cvmx_pip_xstat1_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6514,	2,	4618},
+	{"cvmx_pip_xstat2_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6518,	2,	4620},
+	{"cvmx_pip_xstat3_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6522,	2,	4622},
+	{"cvmx_pip_xstat4_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6526,	2,	4624},
+	{"cvmx_pip_xstat5_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6530,	2,	4626},
+	{"cvmx_pip_xstat6_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6534,	2,	4628},
+	{"cvmx_pip_xstat7_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6538,	2,	4630},
+	{"cvmx_pip_xstat8_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6542,	2,	4632},
+	{"cvmx_pip_xstat9_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6546,	2,	4634},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6550,	2,	4636},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6551,	2,	4638},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6552,	4,	4640},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6553,	5,	4644},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6554,	4,	4649},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6555,	8,	4653},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6556,	4,	4661},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6557,	5,	4665},
+	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6558,	1,	4670},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6559,	5,	4671},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6560,	1,	4676},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6561,	13,	4677},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6562,	6,	4690},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6563,	13,	4696},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6564,	6,	4709},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6565,	9,	4715},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6566,	4,	4724},
+	{"cvmx_pko_mem_port_ptrs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6567,	7,	4728},
+	{"cvmx_pko_mem_port_qos"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6568,	5,	4735},
+	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6569,	5,	4740},
+	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6570,	4,	4745},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6571,	9,	4749},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6572,	5,	4758},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6573,	16,	4763},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6574,	4,	4779},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6575,	1,	4783},
+	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6576,	1,	4784},
+	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6577,	1,	4785},
+	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6578,	1,	4786},
+	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	6579,	13,	4787},
+	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6580,	2,	4800},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6581,	4,	4802},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6582,	5,	4806},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6583,	3,	4811},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6584,	4,	4814},
+	{"cvmx_pko_reg_preempt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6585,	2,	4818},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6586,	2,	4820},
+	{"cvmx_pko_reg_queue_preempt"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6587,	3,	4822},
+	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6588,	3,	4825},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6589,	3,	4828},
+	{"cvmx_pko_reg_timestamp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6590,	2,	4831},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6591,	10,	4833},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	6592,	2,	4843},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6593,	13,	4845},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6594,	3,	4858},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6595,	2,	4861},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	6603,	2,	4863},
+	{"cvmx_pow_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6604,	2,	4865},
+	{"cvmx_pow_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6605,	2,	4867},
+	{"cvmx_pow_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6606,	2,	4869},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6614,	2,	4871},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6615,	2,	4873},
+	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	6616,	2,	4875},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6617,	10,	4877},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	6623,	5,	4887},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	6631,	10,	4892},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	6639,	2,	4902},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6640,	2,	4904},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6641,	2,	4906},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6649,	3,	4908},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6650,	6,	4911},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6666,	5,	4917},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6667,	7,	4922},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6683,	2,	4929},
+	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6699,	1,	4931},
+	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6700,	1,	4932},
+	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6701,	1,	4933},
+	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6702,	5,	4934},
+	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6703,	5,	4939},
+	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6704,	4,	4944},
+	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6705,	10,	4948},
+	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6706,	1,	4958},
+	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6707,	3,	4959},
+	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6708,	7,	4962},
+	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6709,	2,	4969},
+	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6710,	1,	4971},
+	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6711,	1,	4972},
+	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6712,	1,	4973},
+	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6713,	18,	4974},
+	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6714,	3,	4992},
+	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6715,	2,	4995},
+	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6716,	3,	4997},
+	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6717,	7,	5000},
+	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6718,	2,	5007},
+	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6719,	2,	5009},
+	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6720,	2,	5011},
+	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6721,	3,	5013},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6722,	3,	5016},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6723,	9,	5019},
+	{"cvmx_rnm_eer_dbg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6724,	1,	5028},
+	{"cvmx_rnm_eer_key"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6725,	1,	5029},
+	{"cvmx_rnm_serial_num"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6726,	1,	5030},
+	{"cvmx_sli_bist_status"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6727,	25,	5031},
+	{"cvmx_sli_ctl_port#"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6728,	16,	5056},
+	{"cvmx_sli_ctl_status"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6730,	4,	5072},
+	{"cvmx_sli_data_out_cnt"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6731,	5,	5076},
+	{"cvmx_sli_dbg_data"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6732,	3,	5081},
+	{"cvmx_sli_dbg_select"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6733,	3,	5084},
+	{"cvmx_sli_dma#_cnt"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6734,	2,	5087},
+	{"cvmx_sli_dma#_int_level"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6736,	2,	5089},
+	{"cvmx_sli_dma#_tim"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6738,	2,	5091},
+	{"cvmx_sli_int_enb_ciu"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6740,	35,	5093},
+	{"cvmx_sli_int_enb_port#"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6741,	37,	5128},
+	{"cvmx_sli_int_sum"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6743,	37,	5165},
+	{"cvmx_sli_last_win_rdata0"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6744,	1,	5202},
+	{"cvmx_sli_last_win_rdata1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6745,	1,	5203},
+	{"cvmx_sli_mac_credit_cnt"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6746,	13,	5204},
+	{"cvmx_sli_mac_number"         ,	CVMX_CSR_DB_TYPE_PEXP,	64,	6747,	2,	5217},
+	{"cvmx_sli_mem_access_ctl"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6748,	3,	5219},
+	{"cvmx_sli_mem_access_subid#"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6749,	9,	5222},
+	{"cvmx_sli_msi_enb0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6765,	1,	5231},
+	{"cvmx_sli_msi_enb1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6766,	1,	5232},
+	{"cvmx_sli_msi_enb2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6767,	1,	5233},
+	{"cvmx_sli_msi_enb3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6768,	1,	5234},
+	{"cvmx_sli_msi_rcv0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6769,	1,	5235},
+	{"cvmx_sli_msi_rcv1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6770,	1,	5236},
+	{"cvmx_sli_msi_rcv2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6771,	1,	5237},
+	{"cvmx_sli_msi_rcv3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6772,	1,	5238},
+	{"cvmx_sli_msi_rd_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6773,	3,	5239},
+	{"cvmx_sli_msi_w1c_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6774,	1,	5242},
+	{"cvmx_sli_msi_w1c_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6775,	1,	5243},
+	{"cvmx_sli_msi_w1c_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6776,	1,	5244},
+	{"cvmx_sli_msi_w1c_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6777,	1,	5245},
+	{"cvmx_sli_msi_w1s_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6778,	1,	5246},
+	{"cvmx_sli_msi_w1s_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6779,	1,	5247},
+	{"cvmx_sli_msi_w1s_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6780,	1,	5248},
+	{"cvmx_sli_msi_w1s_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6781,	1,	5249},
+	{"cvmx_sli_msi_wr_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6782,	3,	5250},
+	{"cvmx_sli_pcie_msi_rcv"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6783,	2,	5253},
+	{"cvmx_sli_pcie_msi_rcv_b1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6784,	3,	5255},
+	{"cvmx_sli_pcie_msi_rcv_b2"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6785,	3,	5258},
+	{"cvmx_sli_pcie_msi_rcv_b3"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6786,	3,	5261},
+	{"cvmx_sli_pkt#_cnts"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6787,	3,	5264},
+	{"cvmx_sli_pkt#_in_bp"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6819,	2,	5267},
+	{"cvmx_sli_pkt#_instr_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6851,	2,	5269},
+	{"cvmx_sli_pkt#_instr_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6883,	2,	5271},
+	{"cvmx_sli_pkt#_instr_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6915,	5,	5273},
+	{"cvmx_sli_pkt#_instr_header"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6947,	21,	5278},
+	{"cvmx_sli_pkt#_out_size"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6979,	3,	5299},
+	{"cvmx_sli_pkt#_slist_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7011,	2,	5302},
+	{"cvmx_sli_pkt#_slist_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7043,	2,	5304},
+	{"cvmx_sli_pkt#_slist_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7075,	2,	5306},
+	{"cvmx_sli_pkt_cnt_int"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7107,	2,	5308},
+	{"cvmx_sli_pkt_cnt_int_enb"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7108,	2,	5310},
+	{"cvmx_sli_pkt_ctl"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7109,	3,	5312},
+	{"cvmx_sli_pkt_data_out_es"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7110,	1,	5315},
+	{"cvmx_sli_pkt_data_out_ns"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7111,	2,	5316},
+	{"cvmx_sli_pkt_data_out_ror"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7112,	2,	5318},
+	{"cvmx_sli_pkt_dpaddr"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7113,	2,	5320},
+	{"cvmx_sli_pkt_in_bp"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7114,	2,	5322},
+	{"cvmx_sli_pkt_in_done#_cnts"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7115,	2,	5324},
+	{"cvmx_sli_pkt_in_instr_counts",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7147,	2,	5326},
+	{"cvmx_sli_pkt_in_pcie_port"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7148,	1,	5328},
+	{"cvmx_sli_pkt_input_control"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7149,	10,	5329},
+	{"cvmx_sli_pkt_instr_enb"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7150,	2,	5339},
+	{"cvmx_sli_pkt_instr_rd_size"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7151,	1,	5341},
+	{"cvmx_sli_pkt_instr_size"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7152,	2,	5342},
+	{"cvmx_sli_pkt_int_levels"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7153,	3,	5344},
+	{"cvmx_sli_pkt_iptr"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7154,	2,	5347},
+	{"cvmx_sli_pkt_out_bmode"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7155,	2,	5349},
+	{"cvmx_sli_pkt_out_enb"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7156,	2,	5351},
+	{"cvmx_sli_pkt_output_wmark"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7157,	2,	5353},
+	{"cvmx_sli_pkt_pcie_port"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7158,	1,	5355},
+	{"cvmx_sli_pkt_port_in_rst"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7159,	2,	5356},
+	{"cvmx_sli_pkt_slist_es"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7160,	1,	5358},
+	{"cvmx_sli_pkt_slist_ns"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7161,	2,	5359},
+	{"cvmx_sli_pkt_slist_ror"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7162,	2,	5361},
+	{"cvmx_sli_pkt_time_int"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7163,	2,	5363},
+	{"cvmx_sli_pkt_time_int_enb"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7164,	2,	5365},
+	{"cvmx_sli_s2m_port#_ctl"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7165,	4,	5367},
+	{"cvmx_sli_scratch_1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7167,	1,	5371},
+	{"cvmx_sli_scratch_2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7168,	1,	5372},
+	{"cvmx_sli_state1"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7169,	4,	5373},
+	{"cvmx_sli_state2"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7170,	8,	5377},
+	{"cvmx_sli_state3"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7171,	5,	5385},
+	{"cvmx_sli_win_rd_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7172,	4,	5390},
+	{"cvmx_sli_win_rd_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7173,	1,	5394},
+	{"cvmx_sli_win_wr_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7174,	4,	5395},
+	{"cvmx_sli_win_wr_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7175,	1,	5399},
+	{"cvmx_sli_win_wr_mask"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7176,	2,	5400},
+	{"cvmx_sli_window_ctl"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7177,	2,	5402},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7178,	10,	5404},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7180,	6,	5414},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	7182,	2,	5420},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7184,	4,	5422},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7186,	4,	5426},
+	{"cvmx_smi_drv_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7188,	4,	5430},
+	{"cvmx_srio#_acc_ctrl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7189,	4,	5434},
+	{"cvmx_srio#_asmbly_id"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7191,	3,	5438},
+	{"cvmx_srio#_asmbly_info"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7193,	3,	5441},
+	{"cvmx_srio#_bell_resp_ctrl"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7195,	5,	5444},
+	{"cvmx_srio#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7197,	19,	5449},
+	{"cvmx_srio#_imsg_ctrl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7199,	14,	5468},
+	{"cvmx_srio#_imsg_inst_hdr#"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7201,	14,	5482},
+	{"cvmx_srio#_imsg_qos_grp#"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7205,	24,	5496},
+	{"cvmx_srio#_imsg_status#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7269,	24,	5520},
+	{"cvmx_srio#_imsg_vport_thr"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7317,	13,	5544},
+	{"cvmx_srio#_int2_enable"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7319,	2,	5557},
+	{"cvmx_srio#_int2_reg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7321,	4,	5559},
+	{"cvmx_srio#_int_enable"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7323,	28,	5563},
+	{"cvmx_srio#_int_info0"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7325,	9,	5591},
+	{"cvmx_srio#_int_info1"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7327,	1,	5600},
+	{"cvmx_srio#_int_info2"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7329,	11,	5601},
+	{"cvmx_srio#_int_info3"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7331,	5,	5612},
+	{"cvmx_srio#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7333,	30,	5617},
+	{"cvmx_srio#_ip_feature"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7335,	9,	5647},
+	{"cvmx_srio#_mac_buffers"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7337,	10,	5656},
+	{"cvmx_srio#_maint_op"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7339,	6,	5666},
+	{"cvmx_srio#_maint_rd_data"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7341,	3,	5672},
+	{"cvmx_srio#_mce_tx_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7343,	2,	5675},
+	{"cvmx_srio#_mem_op_ctrl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7345,	8,	5677},
+	{"cvmx_srio#_omsg_ctrl#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7347,	11,	5685},
+	{"cvmx_srio#_omsg_done_counts#",	CVMX_CSR_DB_TYPE_RSL,	64,	7351,	3,	5696},
+	{"cvmx_srio#_omsg_fmp_mr#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7355,	16,	5699},
+	{"cvmx_srio#_omsg_nmp_mr#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7359,	16,	5715},
+	{"cvmx_srio#_omsg_port#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7363,	4,	5731},
+	{"cvmx_srio#_omsg_silo_thr"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7367,	2,	5735},
+	{"cvmx_srio#_omsg_sp_mr#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7369,	17,	5737},
+	{"cvmx_srio#_prio#_in_use"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7373,	3,	5754},
+	{"cvmx_srio#_rx_bell"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7381,	9,	5757},
+	{"cvmx_srio#_rx_bell_seq"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7383,	3,	5766},
+	{"cvmx_srio#_rx_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7385,	9,	5769},
+	{"cvmx_srio#_s2m_type#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7387,	11,	5778},
+	{"cvmx_srio#_seq"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	7419,	2,	5789},
+	{"cvmx_srio#_status_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7421,	3,	5791},
+	{"cvmx_srio#_tag_ctrl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7423,	6,	5794},
+	{"cvmx_srio#_tlp_credits"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7425,	6,	5800},
+	{"cvmx_srio#_tx_bell"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7427,	10,	5806},
+	{"cvmx_srio#_tx_bell_info"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7429,	11,	5816},
+	{"cvmx_srio#_tx_ctrl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7431,	12,	5827},
+	{"cvmx_srio#_tx_emphasis"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7433,	2,	5839},
+	{"cvmx_srio#_tx_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7435,	5,	5841},
+	{"cvmx_srio#_wr_done_counts"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7437,	3,	5846},
+	{"cvmx_sriomaint#_asmbly_id"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7439,	2,	5849},
+	{"cvmx_sriomaint#_asmbly_info" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7441,	2,	5851},
+	{"cvmx_sriomaint#_bar1_idx#"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7443,	7,	5853},
+	{"cvmx_sriomaint#_bell_status" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7475,	2,	5860},
+	{"cvmx_sriomaint#_comp_tag"    ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7477,	1,	5862},
+	{"cvmx_sriomaint#_core_enables",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7479,	6,	5863},
+	{"cvmx_sriomaint#_dev_id"      ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7481,	2,	5869},
+	{"cvmx_sriomaint#_dev_rev"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7483,	2,	5871},
+	{"cvmx_sriomaint#_dst_ops"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7485,	26,	5873},
+	{"cvmx_sriomaint#_erb_attr_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7487,	5,	5899},
+	{"cvmx_sriomaint#_erb_err_det" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7489,	17,	5904},
+	{"cvmx_sriomaint#_erb_err_rate",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7491,	5,	5921},
+	{"cvmx_sriomaint#_erb_err_rate_en",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7493,	17,	5926},
+	{"cvmx_sriomaint#_erb_err_rate_thr",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7495,	3,	5943},
+	{"cvmx_sriomaint#_erb_hdr"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7497,	2,	5946},
+	{"cvmx_sriomaint#_erb_lt_addr_capt_h",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7499,	1,	5948},
+	{"cvmx_sriomaint#_erb_lt_addr_capt_l",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7501,	3,	5949},
+	{"cvmx_sriomaint#_erb_lt_ctrl_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7503,	9,	5952},
+	{"cvmx_sriomaint#_erb_lt_dev_id",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7505,	4,	5961},
+	{"cvmx_sriomaint#_erb_lt_dev_id_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7507,	4,	5965},
+	{"cvmx_sriomaint#_erb_lt_err_det",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7509,	12,	5969},
+	{"cvmx_sriomaint#_erb_lt_err_en",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7511,	12,	5981},
+	{"cvmx_sriomaint#_erb_pack_capt_1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7513,	1,	5993},
+	{"cvmx_sriomaint#_erb_pack_capt_2",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7515,	1,	5994},
+	{"cvmx_sriomaint#_erb_pack_capt_3",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7517,	1,	5995},
+	{"cvmx_sriomaint#_erb_pack_sym_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7519,	1,	5996},
+	{"cvmx_sriomaint#_hb_dev_id_lock",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7521,	2,	5997},
+	{"cvmx_sriomaint#_ir_buffer_config",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7523,	7,	5999},
+	{"cvmx_sriomaint#_ir_buffer_config2",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7525,	8,	6006},
+	{"cvmx_sriomaint#_ir_pd_phy_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7527,	1,	6014},
+	{"cvmx_sriomaint#_ir_pd_phy_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7529,	9,	6015},
+	{"cvmx_sriomaint#_ir_pi_phy_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7531,	5,	6024},
+	{"cvmx_sriomaint#_ir_pi_phy_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7533,	4,	6029},
+	{"cvmx_sriomaint#_ir_sp_rx_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7535,	2,	6033},
+	{"cvmx_sriomaint#_ir_sp_rx_data",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7537,	1,	6035},
+	{"cvmx_sriomaint#_ir_sp_rx_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7539,	5,	6036},
+	{"cvmx_sriomaint#_ir_sp_tx_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7541,	2,	6041},
+	{"cvmx_sriomaint#_ir_sp_tx_data",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7543,	1,	6043},
+	{"cvmx_sriomaint#_ir_sp_tx_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7545,	5,	6044},
+	{"cvmx_sriomaint#_lane_#_status_0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7547,	15,	6049},
+	{"cvmx_sriomaint#_lcs_ba0"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7555,	2,	6064},
+	{"cvmx_sriomaint#_lcs_ba1"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7557,	2,	6066},
+	{"cvmx_sriomaint#_m2s_bar0_start0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7559,	2,	6068},
+	{"cvmx_sriomaint#_m2s_bar0_start1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7561,	4,	6070},
+	{"cvmx_sriomaint#_m2s_bar1_start0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7563,	2,	6074},
+	{"cvmx_sriomaint#_m2s_bar1_start1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7565,	5,	6076},
+	{"cvmx_sriomaint#_m2s_bar2_start",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7567,	7,	6081},
+	{"cvmx_sriomaint#_mac_ctrl"    ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7569,	6,	6088},
+	{"cvmx_sriomaint#_pe_feat"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7571,	11,	6094},
+	{"cvmx_sriomaint#_pe_llc"      ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7573,	2,	6105},
+	{"cvmx_sriomaint#_port_0_ctl"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7575,	18,	6107},
+	{"cvmx_sriomaint#_port_0_ctl2" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7577,	16,	6125},
+	{"cvmx_sriomaint#_port_0_err_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7579,	20,	6141},
+	{"cvmx_sriomaint#_port_0_link_req",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7581,	2,	6161},
+	{"cvmx_sriomaint#_port_0_link_resp",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7583,	4,	6163},
+	{"cvmx_sriomaint#_port_0_local_ackid",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7585,	6,	6167},
+	{"cvmx_sriomaint#_port_gen_ctl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7587,	4,	6173},
+	{"cvmx_sriomaint#_port_lt_ctl" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7589,	2,	6177},
+	{"cvmx_sriomaint#_port_mbh0"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7591,	2,	6179},
+	{"cvmx_sriomaint#_port_rt_ctl" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7593,	2,	6181},
+	{"cvmx_sriomaint#_port_ttl_ctl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7595,	2,	6183},
+	{"cvmx_sriomaint#_pri_dev_id"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7597,	3,	6185},
+	{"cvmx_sriomaint#_sec_dev_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7599,	3,	6188},
+	{"cvmx_sriomaint#_sec_dev_id"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7601,	3,	6191},
+	{"cvmx_sriomaint#_serial_lane_hdr",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7603,	2,	6194},
+	{"cvmx_sriomaint#_src_ops"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7605,	26,	6196},
+	{"cvmx_sriomaint#_tx_drop"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7607,	3,	6222},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7609,	6,	6225},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7610,	3,	6231},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7611,	5,	6234},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7612,	4,	6239},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7613,	6,	6243},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7614,	4,	6249},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7615,	2,	6253},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7616,	4,	6255},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7617,	2,	6259},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7618,	3,	6261},
+	{"cvmx_tra#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7619,	2,	6264},
+	{"cvmx_tra#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7620,	14,	6266},
+	{"cvmx_tra#_cycles_since"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7621,	3,	6280},
+	{"cvmx_tra#_cycles_since1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7622,	5,	6283},
+	{"cvmx_tra#_filt_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7623,	2,	6288},
+	{"cvmx_tra#_filt_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7624,	2,	6290},
+	{"cvmx_tra#_filt_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7625,	57,	6292},
+	{"cvmx_tra#_filt_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7626,	20,	6349},
+	{"cvmx_tra#_filt_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7627,	7,	6369},
+	{"cvmx_tra#_int_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7628,	5,	6376},
+	{"cvmx_tra#_read_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7629,	1,	6381},
+	{"cvmx_tra#_read_dat_hi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7630,	2,	6382},
+	{"cvmx_tra#_trig0_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7631,	2,	6384},
+	{"cvmx_tra#_trig0_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7632,	2,	6386},
+	{"cvmx_tra#_trig0_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7633,	57,	6388},
+	{"cvmx_tra#_trig0_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7634,	20,	6445},
+	{"cvmx_tra#_trig0_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7635,	7,	6465},
+	{"cvmx_tra#_trig1_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7636,	2,	6472},
+	{"cvmx_tra#_trig1_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7637,	2,	6474},
+	{"cvmx_tra#_trig1_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7638,	57,	6476},
+	{"cvmx_tra#_trig1_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7639,	20,	6533},
+	{"cvmx_tra#_trig1_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7640,	7,	6553},
+	{"cvmx_uahc#_ehci_asynclistaddr",	CVMX_CSR_DB_TYPE_NCB,	32,	7641,	2,	6560},
+	{"cvmx_uahc#_ehci_configflag"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7642,	2,	6562},
+	{"cvmx_uahc#_ehci_ctrldssegment",	CVMX_CSR_DB_TYPE_NCB,	32,	7643,	1,	6564},
+	{"cvmx_uahc#_ehci_frindex"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7644,	2,	6565},
+	{"cvmx_uahc#_ehci_hccapbase"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7645,	3,	6567},
+	{"cvmx_uahc#_ehci_hccparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7646,	7,	6570},
+	{"cvmx_uahc#_ehci_hcsparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7647,	10,	6577},
+	{"cvmx_uahc#_ehci_insnreg00"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7648,	3,	6587},
+	{"cvmx_uahc#_ehci_insnreg03"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7649,	5,	6590},
+	{"cvmx_uahc#_ehci_insnreg04"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7650,	7,	6595},
+	{"cvmx_uahc#_ehci_insnreg06"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7651,	2,	6602},
+	{"cvmx_uahc#_ehci_insnreg07"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7652,	1,	6604},
+	{"cvmx_uahc#_ehci_periodiclistbase",	CVMX_CSR_DB_TYPE_NCB,	32,	7653,	2,	6605},
+	{"cvmx_uahc#_ehci_portsc#"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7654,	19,	6607},
+	{"cvmx_uahc#_ehci_usbcmd"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	7656,	13,	6626},
+	{"cvmx_uahc#_ehci_usbintr"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7657,	7,	6639},
+	{"cvmx_uahc#_ehci_usbsts"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	7658,	12,	6646},
+	{"cvmx_uahc#_ohci0_hcbulkcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7659,	2,	6658},
+	{"cvmx_uahc#_ohci0_hcbulkheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	7660,	2,	6660},
+	{"cvmx_uahc#_ohci0_hccommandstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	7661,	7,	6662},
+	{"cvmx_uahc#_ohci0_hccontrol"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7662,	10,	6669},
+	{"cvmx_uahc#_ohci0_hccontrolcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7663,	2,	6679},
+	{"cvmx_uahc#_ohci0_hccontrolheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	7664,	2,	6681},
+	{"cvmx_uahc#_ohci0_hcdonehead" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7665,	2,	6683},
+	{"cvmx_uahc#_ohci0_hcfminterval",	CVMX_CSR_DB_TYPE_NCB,	32,	7666,	4,	6685},
+	{"cvmx_uahc#_ohci0_hcfmnumber" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7667,	2,	6689},
+	{"cvmx_uahc#_ohci0_hcfmremaining",	CVMX_CSR_DB_TYPE_NCB,	32,	7668,	3,	6691},
+	{"cvmx_uahc#_ohci0_hchcca"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7669,	2,	6694},
+	{"cvmx_uahc#_ohci0_hcinterruptdisable",	CVMX_CSR_DB_TYPE_NCB,	32,	7670,	10,	6696},
+	{"cvmx_uahc#_ohci0_hcinterruptenable",	CVMX_CSR_DB_TYPE_NCB,	32,	7671,	10,	6706},
+	{"cvmx_uahc#_ohci0_hcinterruptstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	7672,	10,	6716},
+	{"cvmx_uahc#_ohci0_hclsthreshold",	CVMX_CSR_DB_TYPE_NCB,	32,	7673,	2,	6726},
+	{"cvmx_uahc#_ohci0_hcperiodcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7674,	2,	6728},
+	{"cvmx_uahc#_ohci0_hcperiodicstart",	CVMX_CSR_DB_TYPE_NCB,	32,	7675,	2,	6730},
+	{"cvmx_uahc#_ohci0_hcrevision" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7676,	2,	6732},
+	{"cvmx_uahc#_ohci0_hcrhdescriptora",	CVMX_CSR_DB_TYPE_NCB,	32,	7677,	8,	6734},
+	{"cvmx_uahc#_ohci0_hcrhdescriptorb",	CVMX_CSR_DB_TYPE_NCB,	32,	7678,	2,	6742},
+	{"cvmx_uahc#_ohci0_hcrhportstatus#",	CVMX_CSR_DB_TYPE_NCB,	32,	7679,	15,	6744},
+	{"cvmx_uahc#_ohci0_hcrhstatus" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7681,	8,	6759},
+	{"cvmx_uahc#_ohci0_insnreg06"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7682,	2,	6767},
+	{"cvmx_uahc#_ohci0_insnreg07"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7683,	1,	6769},
+	{"cvmx_uctl#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7684,	7,	6770},
+	{"cvmx_uctl#_clk_rst_ctl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7685,	21,	6777},
+	{"cvmx_uctl#_ehci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7686,	12,	6798},
+	{"cvmx_uctl#_ehci_fla"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7687,	2,	6810},
+	{"cvmx_uctl#_erto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7688,	3,	6812},
+	{"cvmx_uctl#_if_ena"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7689,	2,	6815},
+	{"cvmx_uctl#_int_ena"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7690,	9,	6817},
+	{"cvmx_uctl#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7691,	9,	6826},
+	{"cvmx_uctl#_ohci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7692,	11,	6835},
+	{"cvmx_uctl#_orto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7693,	3,	6846},
+	{"cvmx_uctl#_ppaf_wm"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7694,	2,	6849},
+	{"cvmx_uctl#_uphy_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	7695,	11,	6851},
+	{"cvmx_uctl#_uphy_port#_ctl_status",	CVMX_CSR_DB_TYPE_RSL,	64,	7696,	20,	6862},
+	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7698,	3,	6882},
+	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7699,	5,	6885},
+	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7700,	3,	6890},
+	{"cvmx_zip_constants"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7701,	6,	6893},
+	{"cvmx_zip_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	7702,	2,	6899},
+	{"cvmx_zip_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	7703,	2,	6901},
+	{"cvmx_zip_int_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7704,	2,	6903},
+	{"cvmx_zip_throttle"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7705,	2,	6905},
 	{NULL,0,0,0,0,0}
 };
 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn63xx[] = {
@@ -91331,8 +106400,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn63xx[] = {
 	{"DPI_REQ_GBL_EN"              ,	   0x1df0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
 	{"DPI_SLI_PRT0_CFG"            ,	   0x1df0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
 	{"DPI_SLI_PRT1_CFG"            ,	   0x1df0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
-	{"DPI_SLI_PRT0_ERR"            ,	   0x1df0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
-	{"DPI_SLI_PRT1_ERR"            ,	   0x1df0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"DPI_SLI_PRT0_ERR"            ,	   0x1df0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"DPI_SLI_PRT1_ERR"            ,	   0x1df0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
 	{"DPI_SLI_PRT0_ERR_INFO"       ,	   0x1df0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
 	{"DPI_SLI_PRT1_ERR_INFO"       ,	   0x1df0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
 	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
@@ -97134,1424 +112203,1458 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn63xx[] = {
 	{"PIP_STAT0_PRT37"             ,	   0x11800a0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
 	{"PIP_STAT0_PRT38"             ,	   0x11800a00013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
 	{"PIP_STAT0_PRT39"             ,	   0x11800a0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
-	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT1_PRT3"              ,	   0x11800a00008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT1_PRT32"             ,	   0x11800a0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT1_PRT33"             ,	   0x11800a0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT1_PRT34"             ,	   0x11800a00012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT1_PRT35"             ,	   0x11800a00012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT1_PRT36"             ,	   0x11800a0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT1_PRT37"             ,	   0x11800a0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT1_PRT38"             ,	   0x11800a00013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT1_PRT39"             ,	   0x11800a0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
-	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
-	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
-	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
-	{"PIP_STAT2_PRT3"              ,	   0x11800a0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
-	{"PIP_STAT2_PRT32"             ,	   0x11800a0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
-	{"PIP_STAT2_PRT33"             ,	   0x11800a0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
-	{"PIP_STAT2_PRT34"             ,	   0x11800a00012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
-	{"PIP_STAT2_PRT35"             ,	   0x11800a0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
-	{"PIP_STAT2_PRT36"             ,	   0x11800a0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
-	{"PIP_STAT2_PRT37"             ,	   0x11800a00013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
-	{"PIP_STAT2_PRT38"             ,	   0x11800a00013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
-	{"PIP_STAT2_PRT39"             ,	   0x11800a0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
-	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT3_PRT3"              ,	   0x11800a0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT3_PRT32"             ,	   0x11800a0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT3_PRT33"             ,	   0x11800a0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT3_PRT34"             ,	   0x11800a00012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT3_PRT35"             ,	   0x11800a0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT3_PRT36"             ,	   0x11800a0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT3_PRT37"             ,	   0x11800a00013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT3_PRT38"             ,	   0x11800a00013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT3_PRT39"             ,	   0x11800a0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
-	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT4_PRT3"              ,	   0x11800a0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT4_PRT32"             ,	   0x11800a0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT4_PRT33"             ,	   0x11800a0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT4_PRT34"             ,	   0x11800a00012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT4_PRT35"             ,	   0x11800a0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT4_PRT36"             ,	   0x11800a0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT4_PRT37"             ,	   0x11800a00013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT4_PRT38"             ,	   0x11800a0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT4_PRT39"             ,	   0x11800a0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
-	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT5_PRT3"              ,	   0x11800a0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT5_PRT32"             ,	   0x11800a0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT5_PRT33"             ,	   0x11800a0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT5_PRT34"             ,	   0x11800a00012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT5_PRT35"             ,	   0x11800a0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT5_PRT36"             ,	   0x11800a0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT5_PRT37"             ,	   0x11800a00013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT5_PRT38"             ,	   0x11800a0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT5_PRT39"             ,	   0x11800a0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
-	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_STAT6_PRT3"              ,	   0x11800a0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_STAT6_PRT32"             ,	   0x11800a0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_STAT6_PRT33"             ,	   0x11800a0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_STAT6_PRT34"             ,	   0x11800a00012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_STAT6_PRT35"             ,	   0x11800a0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_STAT6_PRT36"             ,	   0x11800a0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_STAT6_PRT37"             ,	   0x11800a00013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_STAT6_PRT38"             ,	   0x11800a0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_STAT6_PRT39"             ,	   0x11800a0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
-	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
-	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
-	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
-	{"PIP_STAT7_PRT3"              ,	   0x11800a0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
-	{"PIP_STAT7_PRT32"             ,	   0x11800a0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
-	{"PIP_STAT7_PRT33"             ,	   0x11800a0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
-	{"PIP_STAT7_PRT34"             ,	   0x11800a00012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
-	{"PIP_STAT7_PRT35"             ,	   0x11800a0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
-	{"PIP_STAT7_PRT36"             ,	   0x11800a0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
-	{"PIP_STAT7_PRT37"             ,	   0x11800a00013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
-	{"PIP_STAT7_PRT38"             ,	   0x11800a0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
-	{"PIP_STAT7_PRT39"             ,	   0x11800a0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
-	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
-	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
-	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
-	{"PIP_STAT8_PRT3"              ,	   0x11800a0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
-	{"PIP_STAT8_PRT32"             ,	   0x11800a0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
-	{"PIP_STAT8_PRT33"             ,	   0x11800a0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
-	{"PIP_STAT8_PRT34"             ,	   0x11800a00012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
-	{"PIP_STAT8_PRT35"             ,	   0x11800a0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
-	{"PIP_STAT8_PRT36"             ,	   0x11800a0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
-	{"PIP_STAT8_PRT37"             ,	   0x11800a00013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
-	{"PIP_STAT8_PRT38"             ,	   0x11800a0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
-	{"PIP_STAT8_PRT39"             ,	   0x11800a0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
-	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
-	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
-	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
-	{"PIP_STAT9_PRT3"              ,	   0x11800a0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
-	{"PIP_STAT9_PRT32"             ,	   0x11800a0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
-	{"PIP_STAT9_PRT33"             ,	   0x11800a0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
-	{"PIP_STAT9_PRT34"             ,	   0x11800a00012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
-	{"PIP_STAT9_PRT35"             ,	   0x11800a0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
-	{"PIP_STAT9_PRT36"             ,	   0x11800a0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
-	{"PIP_STAT9_PRT37"             ,	   0x11800a00013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
-	{"PIP_STAT9_PRT38"             ,	   0x11800a0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
-	{"PIP_STAT9_PRT39"             ,	   0x11800a0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
-	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
-	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_STAT_INB_ERRS3"          ,	   0x11800a0001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_STAT_INB_ERRS32"         ,	   0x11800a0001e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_STAT_INB_ERRS33"         ,	   0x11800a0001e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_STAT_INB_ERRS34"         ,	   0x11800a0001e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_STAT_INB_ERRS35"         ,	   0x11800a0001e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_STAT_INB_ERRS36"         ,	   0x11800a0001e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_STAT_INB_ERRS37"         ,	   0x11800a0001eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_STAT_INB_ERRS38"         ,	   0x11800a0001ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_STAT_INB_ERRS39"         ,	   0x11800a0001ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_STAT_INB_ERRS40"         ,	   0x11800a0001f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_STAT_INB_ERRS41"         ,	   0x11800a0001f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_STAT_INB_ERRS42"         ,	   0x11800a0001f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_STAT_INB_ERRS43"         ,	   0x11800a0001f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_STAT_INB_OCTS3"          ,	   0x11800a0001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_STAT_INB_OCTS32"         ,	   0x11800a0001e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_STAT_INB_OCTS33"         ,	   0x11800a0001e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_STAT_INB_OCTS34"         ,	   0x11800a0001e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_STAT_INB_OCTS35"         ,	   0x11800a0001e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_STAT_INB_OCTS36"         ,	   0x11800a0001e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_STAT_INB_OCTS37"         ,	   0x11800a0001ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_STAT_INB_OCTS38"         ,	   0x11800a0001ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_STAT_INB_OCTS39"         ,	   0x11800a0001ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_STAT_INB_OCTS40"         ,	   0x11800a0001f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_STAT_INB_OCTS41"         ,	   0x11800a0001f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_STAT_INB_OCTS42"         ,	   0x11800a0001f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_STAT_INB_OCTS43"         ,	   0x11800a0001f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_STAT_INB_PKTS3"          ,	   0x11800a0001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_STAT_INB_PKTS32"         ,	   0x11800a0001e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_STAT_INB_PKTS33"         ,	   0x11800a0001e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_STAT_INB_PKTS34"         ,	   0x11800a0001e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_STAT_INB_PKTS35"         ,	   0x11800a0001e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_STAT_INB_PKTS36"         ,	   0x11800a0001e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_STAT_INB_PKTS37"         ,	   0x11800a0001ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_STAT_INB_PKTS38"         ,	   0x11800a0001ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_STAT_INB_PKTS39"         ,	   0x11800a0001ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_STAT_INB_PKTS40"         ,	   0x11800a0001f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_STAT_INB_PKTS41"         ,	   0x11800a0001f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_STAT_INB_PKTS42"         ,	   0x11800a0001f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_STAT_INB_PKTS43"         ,	   0x11800a0001f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
-	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
-	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
-	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
-	{"PIP_XSTAT0_PRT40"            ,	   0x11800a0002000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
-	{"PIP_XSTAT0_PRT41"            ,	   0x11800a0002050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
-	{"PIP_XSTAT0_PRT42"            ,	   0x11800a00020a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
-	{"PIP_XSTAT0_PRT43"            ,	   0x11800a00020f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
-	{"PIP_XSTAT1_PRT40"            ,	   0x11800a0002008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
-	{"PIP_XSTAT1_PRT41"            ,	   0x11800a0002058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
-	{"PIP_XSTAT1_PRT42"            ,	   0x11800a00020a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
-	{"PIP_XSTAT1_PRT43"            ,	   0x11800a00020f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
-	{"PIP_XSTAT2_PRT40"            ,	   0x11800a0002010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
-	{"PIP_XSTAT2_PRT41"            ,	   0x11800a0002060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
-	{"PIP_XSTAT2_PRT42"            ,	   0x11800a00020b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
-	{"PIP_XSTAT2_PRT43"            ,	   0x11800a0002100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
-	{"PIP_XSTAT3_PRT40"            ,	   0x11800a0002018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
-	{"PIP_XSTAT3_PRT41"            ,	   0x11800a0002068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
-	{"PIP_XSTAT3_PRT42"            ,	   0x11800a00020b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
-	{"PIP_XSTAT3_PRT43"            ,	   0x11800a0002108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
-	{"PIP_XSTAT4_PRT40"            ,	   0x11800a0002020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
-	{"PIP_XSTAT4_PRT41"            ,	   0x11800a0002070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
-	{"PIP_XSTAT4_PRT42"            ,	   0x11800a00020c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
-	{"PIP_XSTAT4_PRT43"            ,	   0x11800a0002110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
-	{"PIP_XSTAT5_PRT40"            ,	   0x11800a0002028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
-	{"PIP_XSTAT5_PRT41"            ,	   0x11800a0002078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
-	{"PIP_XSTAT5_PRT42"            ,	   0x11800a00020c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
-	{"PIP_XSTAT5_PRT43"            ,	   0x11800a0002118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
-	{"PIP_XSTAT6_PRT40"            ,	   0x11800a0002030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
-	{"PIP_XSTAT6_PRT41"            ,	   0x11800a0002080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
-	{"PIP_XSTAT6_PRT42"            ,	   0x11800a00020d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
-	{"PIP_XSTAT6_PRT43"            ,	   0x11800a0002120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
-	{"PIP_XSTAT7_PRT40"            ,	   0x11800a0002038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
-	{"PIP_XSTAT7_PRT41"            ,	   0x11800a0002088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
-	{"PIP_XSTAT7_PRT42"            ,	   0x11800a00020d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
-	{"PIP_XSTAT7_PRT43"            ,	   0x11800a0002128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
-	{"PIP_XSTAT8_PRT40"            ,	   0x11800a0002040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
-	{"PIP_XSTAT8_PRT41"            ,	   0x11800a0002090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
-	{"PIP_XSTAT8_PRT42"            ,	   0x11800a00020e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
-	{"PIP_XSTAT8_PRT43"            ,	   0x11800a0002130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
-	{"PIP_XSTAT9_PRT40"            ,	   0x11800a0002048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
-	{"PIP_XSTAT9_PRT41"            ,	   0x11800a0002098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
-	{"PIP_XSTAT9_PRT42"            ,	   0x11800a00020e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
-	{"PIP_XSTAT9_PRT43"            ,	   0x11800a0002138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
-	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
-	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
-	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
-	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
-	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
-	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
-	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
-	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
-	{"PKO_MEM_DEBUG14"             ,	   0x1180050001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
-	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
-	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
-	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	817},
-	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
-	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	819},
-	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	820},
-	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	821},
-	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	822},
-	{"PKO_MEM_PORT_PTRS"           ,	   0x1180050001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	823},
-	{"PKO_MEM_PORT_QOS"            ,	   0x1180050001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
-	{"PKO_MEM_PORT_RATE0"          ,	   0x1180050001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
-	{"PKO_MEM_PORT_RATE1"          ,	   0x1180050001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
-	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
-	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
-	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
-	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
-	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
-	{"PKO_REG_DEBUG1"              ,	   0x11800500000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
-	{"PKO_REG_DEBUG2"              ,	   0x11800500000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
-	{"PKO_REG_DEBUG3"              ,	   0x11800500000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
-	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
-	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
-	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
-	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
-	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
-	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
-	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
-	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
-	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
-	{"PKO_REG_TIMESTAMP"           ,	   0x1180050000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
-	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
-	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	846},
-	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	847},
-	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	848},
-	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
-	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
-	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
-	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
-	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
-	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
-	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
-	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
-	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
-	{"POW_IQ_INT"                  ,	   0x1670000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
-	{"POW_IQ_INT_EN"               ,	   0x1670000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	852},
-	{"POW_IQ_THR0"                 ,	   0x16700000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
-	{"POW_IQ_THR1"                 ,	   0x16700000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
-	{"POW_IQ_THR2"                 ,	   0x16700000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
-	{"POW_IQ_THR3"                 ,	   0x16700000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
-	{"POW_IQ_THR4"                 ,	   0x16700000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
-	{"POW_IQ_THR5"                 ,	   0x16700000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
-	{"POW_IQ_THR6"                 ,	   0x16700000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
-	{"POW_IQ_THR7"                 ,	   0x16700000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
-	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
-	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	855},
-	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
-	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
-	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
-	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
-	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
-	{"POW_PP_GRP_MSK4"             ,	   0x1670000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
-	{"POW_PP_GRP_MSK5"             ,	   0x1670000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
-	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
-	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
-	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	860},
-	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	861},
-	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
-	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
-	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
-	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
-	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
-	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
-	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
-	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
-	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	863},
-	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
-	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
-	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
-	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
-	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
-	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
-	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
-	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
-	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
-	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
-	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
-	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
-	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
-	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
-	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
-	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
-	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
-	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
-	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
-	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
-	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
-	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
-	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
-	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
-	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
-	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
-	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
-	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
-	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
-	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
-	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
-	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
-	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
-	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
-	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
-	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
-	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
-	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
-	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
-	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
-	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
-	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
-	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
-	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
-	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
-	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
-	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
-	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
-	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
-	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	868},
-	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	869},
-	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	870},
-	{"RAD_REG_BIST_RESULT"         ,	   0x1180070000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	871},
-	{"RAD_REG_CMD_BUF"             ,	   0x1180070000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
-	{"RAD_REG_CTL"                 ,	   0x1180070000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	873},
-	{"RAD_REG_DEBUG0"              ,	   0x1180070000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	874},
-	{"RAD_REG_DEBUG1"              ,	   0x1180070000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	875},
-	{"RAD_REG_DEBUG10"             ,	   0x1180070000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	876},
-	{"RAD_REG_DEBUG11"             ,	   0x1180070000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	877},
-	{"RAD_REG_DEBUG12"             ,	   0x1180070000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	878},
-	{"RAD_REG_DEBUG2"              ,	   0x1180070000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
-	{"RAD_REG_DEBUG3"              ,	   0x1180070000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
-	{"RAD_REG_DEBUG4"              ,	   0x1180070000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
-	{"RAD_REG_DEBUG5"              ,	   0x1180070000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
-	{"RAD_REG_DEBUG6"              ,	   0x1180070000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
-	{"RAD_REG_DEBUG7"              ,	   0x1180070000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
-	{"RAD_REG_DEBUG8"              ,	   0x1180070000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
-	{"RAD_REG_DEBUG9"              ,	   0x1180070000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	886},
-	{"RAD_REG_ERROR"               ,	   0x1180070000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	887},
-	{"RAD_REG_INT_MASK"            ,	   0x1180070000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	888},
-	{"RAD_REG_POLYNOMIAL"          ,	   0x1180070000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	889},
-	{"RAD_REG_READ_IDX"            ,	   0x1180070000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	890},
-	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	891},
-	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	892},
-	{"RNM_EER_DBG"                 ,	   0x1180040000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	893},
-	{"RNM_EER_KEY"                 ,	   0x1180040000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	894},
-	{"RNM_SERIAL_NUM"              ,	   0x1180040000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	895},
-	{"SLI_BIST_STATUS"             ,	   0x11f0000010580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	896},
-	{"SLI_CTL_PORT0"               ,	   0x11f0000010050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	897},
-	{"SLI_CTL_PORT1"               ,	   0x11f0000010060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	897},
-	{"SLI_CTL_STATUS"              ,	   0x11f0000010570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	898},
-	{"SLI_DATA_OUT_CNT"            ,	   0x11f00000105f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	899},
-	{"SLI_DBG_DATA"                ,	   0x11f0000010310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	900},
-	{"SLI_DBG_SELECT"              ,	   0x11f0000010300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	901},
-	{"SLI_DMA0_CNT"                ,	   0x11f0000010400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	902},
-	{"SLI_DMA1_CNT"                ,	   0x11f0000010410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	902},
-	{"SLI_DMA0_INT_LEVEL"          ,	   0x11f00000103e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
-	{"SLI_DMA1_INT_LEVEL"          ,	   0x11f00000103f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
-	{"SLI_DMA0_TIM"                ,	   0x11f0000010420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	904},
-	{"SLI_DMA1_TIM"                ,	   0x11f0000010430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	904},
-	{"SLI_INT_ENB_CIU"             ,	   0x11f0000013cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	905},
-	{"SLI_INT_ENB_PORT0"           ,	   0x11f0000010340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	906},
-	{"SLI_INT_ENB_PORT1"           ,	   0x11f0000010350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	906},
-	{"SLI_INT_SUM"                 ,	   0x11f0000010330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	907},
-	{"SLI_LAST_WIN_RDATA0"         ,	   0x11f0000010600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	908},
-	{"SLI_LAST_WIN_RDATA1"         ,	   0x11f0000010610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
-	{"SLI_MAC_CREDIT_CNT"          ,	   0x11f0000013d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	910},
-	{"SLI_MAC_NUMBER"              ,	            0x3e00ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	911},
-	{"SLI_MEM_ACCESS_CTL"          ,	   0x11f00000102f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	912},
-	{"SLI_MEM_ACCESS_SUBID12"      ,	   0x11f00000100e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
-	{"SLI_MEM_ACCESS_SUBID13"      ,	   0x11f00000100f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
-	{"SLI_MEM_ACCESS_SUBID14"      ,	   0x11f0000010100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
-	{"SLI_MEM_ACCESS_SUBID15"      ,	   0x11f0000010110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
-	{"SLI_MEM_ACCESS_SUBID16"      ,	   0x11f0000010120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
-	{"SLI_MEM_ACCESS_SUBID17"      ,	   0x11f0000010130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
-	{"SLI_MEM_ACCESS_SUBID18"      ,	   0x11f0000010140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
-	{"SLI_MEM_ACCESS_SUBID19"      ,	   0x11f0000010150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
-	{"SLI_MEM_ACCESS_SUBID20"      ,	   0x11f0000010160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
-	{"SLI_MEM_ACCESS_SUBID21"      ,	   0x11f0000010170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
-	{"SLI_MEM_ACCESS_SUBID22"      ,	   0x11f0000010180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
-	{"SLI_MEM_ACCESS_SUBID23"      ,	   0x11f0000010190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
-	{"SLI_MEM_ACCESS_SUBID24"      ,	   0x11f00000101a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
-	{"SLI_MEM_ACCESS_SUBID25"      ,	   0x11f00000101b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
-	{"SLI_MEM_ACCESS_SUBID26"      ,	   0x11f00000101c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
-	{"SLI_MEM_ACCESS_SUBID27"      ,	   0x11f00000101d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
-	{"SLI_MSI_ENB0"                ,	   0x11f0000013c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	914},
-	{"SLI_MSI_ENB1"                ,	   0x11f0000013c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	915},
-	{"SLI_MSI_ENB2"                ,	   0x11f0000013c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	916},
-	{"SLI_MSI_ENB3"                ,	   0x11f0000013c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	917},
-	{"SLI_MSI_RCV0"                ,	   0x11f0000013c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	918},
-	{"SLI_MSI_RCV1"                ,	   0x11f0000013c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
-	{"SLI_MSI_RCV2"                ,	   0x11f0000013c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	920},
-	{"SLI_MSI_RCV3"                ,	   0x11f0000013c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	921},
-	{"SLI_MSI_RD_MAP"              ,	   0x11f0000013ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	922},
-	{"SLI_MSI_W1C_ENB0"            ,	   0x11f0000013cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	923},
-	{"SLI_MSI_W1C_ENB1"            ,	   0x11f0000013d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	924},
-	{"SLI_MSI_W1C_ENB2"            ,	   0x11f0000013d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	925},
-	{"SLI_MSI_W1C_ENB3"            ,	   0x11f0000013d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
-	{"SLI_MSI_W1S_ENB0"            ,	   0x11f0000013d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
-	{"SLI_MSI_W1S_ENB1"            ,	   0x11f0000013d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
-	{"SLI_MSI_W1S_ENB2"            ,	   0x11f0000013d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
-	{"SLI_MSI_W1S_ENB3"            ,	   0x11f0000013d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
-	{"SLI_MSI_WR_MAP"              ,	   0x11f0000013c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
-	{"SLI_PCIE_MSI_RCV"            ,	   0x11f0000013cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
-	{"SLI_PCIE_MSI_RCV_B1"         ,	   0x11f0000010650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
-	{"SLI_PCIE_MSI_RCV_B2"         ,	   0x11f0000010660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
-	{"SLI_PCIE_MSI_RCV_B3"         ,	   0x11f0000010670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
-	{"SLI_PKT0_CNTS"               ,	   0x11f0000012400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT1_CNTS"               ,	   0x11f0000012410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT2_CNTS"               ,	   0x11f0000012420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT3_CNTS"               ,	   0x11f0000012430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT4_CNTS"               ,	   0x11f0000012440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT5_CNTS"               ,	   0x11f0000012450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT6_CNTS"               ,	   0x11f0000012460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT7_CNTS"               ,	   0x11f0000012470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT8_CNTS"               ,	   0x11f0000012480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT9_CNTS"               ,	   0x11f0000012490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT10_CNTS"              ,	   0x11f00000124a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT11_CNTS"              ,	   0x11f00000124b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT12_CNTS"              ,	   0x11f00000124c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT13_CNTS"              ,	   0x11f00000124d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT14_CNTS"              ,	   0x11f00000124e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT15_CNTS"              ,	   0x11f00000124f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT16_CNTS"              ,	   0x11f0000012500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT17_CNTS"              ,	   0x11f0000012510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT18_CNTS"              ,	   0x11f0000012520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT19_CNTS"              ,	   0x11f0000012530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT20_CNTS"              ,	   0x11f0000012540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT21_CNTS"              ,	   0x11f0000012550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT22_CNTS"              ,	   0x11f0000012560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT23_CNTS"              ,	   0x11f0000012570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT24_CNTS"              ,	   0x11f0000012580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT25_CNTS"              ,	   0x11f0000012590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT26_CNTS"              ,	   0x11f00000125a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT27_CNTS"              ,	   0x11f00000125b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT28_CNTS"              ,	   0x11f00000125c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT29_CNTS"              ,	   0x11f00000125d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT30_CNTS"              ,	   0x11f00000125e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT31_CNTS"              ,	   0x11f00000125f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
-	{"SLI_PKT0_IN_BP"              ,	   0x11f0000013800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT1_IN_BP"              ,	   0x11f0000013810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT2_IN_BP"              ,	   0x11f0000013820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT3_IN_BP"              ,	   0x11f0000013830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT4_IN_BP"              ,	   0x11f0000013840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT5_IN_BP"              ,	   0x11f0000013850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT6_IN_BP"              ,	   0x11f0000013860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT7_IN_BP"              ,	   0x11f0000013870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT8_IN_BP"              ,	   0x11f0000013880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT9_IN_BP"              ,	   0x11f0000013890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT10_IN_BP"             ,	   0x11f00000138a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT11_IN_BP"             ,	   0x11f00000138b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT12_IN_BP"             ,	   0x11f00000138c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT13_IN_BP"             ,	   0x11f00000138d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT14_IN_BP"             ,	   0x11f00000138e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT15_IN_BP"             ,	   0x11f00000138f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT16_IN_BP"             ,	   0x11f0000013900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT17_IN_BP"             ,	   0x11f0000013910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT18_IN_BP"             ,	   0x11f0000013920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT19_IN_BP"             ,	   0x11f0000013930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT20_IN_BP"             ,	   0x11f0000013940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT21_IN_BP"             ,	   0x11f0000013950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT22_IN_BP"             ,	   0x11f0000013960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT23_IN_BP"             ,	   0x11f0000013970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT24_IN_BP"             ,	   0x11f0000013980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT25_IN_BP"             ,	   0x11f0000013990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT26_IN_BP"             ,	   0x11f00000139a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT27_IN_BP"             ,	   0x11f00000139b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT28_IN_BP"             ,	   0x11f00000139c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT29_IN_BP"             ,	   0x11f00000139d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT30_IN_BP"             ,	   0x11f00000139e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT31_IN_BP"             ,	   0x11f00000139f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
-	{"SLI_PKT0_INSTR_BADDR"        ,	   0x11f0000012800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT1_INSTR_BADDR"        ,	   0x11f0000012810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT2_INSTR_BADDR"        ,	   0x11f0000012820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT3_INSTR_BADDR"        ,	   0x11f0000012830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT4_INSTR_BADDR"        ,	   0x11f0000012840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT5_INSTR_BADDR"        ,	   0x11f0000012850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT6_INSTR_BADDR"        ,	   0x11f0000012860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT7_INSTR_BADDR"        ,	   0x11f0000012870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT8_INSTR_BADDR"        ,	   0x11f0000012880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT9_INSTR_BADDR"        ,	   0x11f0000012890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT10_INSTR_BADDR"       ,	   0x11f00000128a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT11_INSTR_BADDR"       ,	   0x11f00000128b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT12_INSTR_BADDR"       ,	   0x11f00000128c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT13_INSTR_BADDR"       ,	   0x11f00000128d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT14_INSTR_BADDR"       ,	   0x11f00000128e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT15_INSTR_BADDR"       ,	   0x11f00000128f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT16_INSTR_BADDR"       ,	   0x11f0000012900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT17_INSTR_BADDR"       ,	   0x11f0000012910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT18_INSTR_BADDR"       ,	   0x11f0000012920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT19_INSTR_BADDR"       ,	   0x11f0000012930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT20_INSTR_BADDR"       ,	   0x11f0000012940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT21_INSTR_BADDR"       ,	   0x11f0000012950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT22_INSTR_BADDR"       ,	   0x11f0000012960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT23_INSTR_BADDR"       ,	   0x11f0000012970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT24_INSTR_BADDR"       ,	   0x11f0000012980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT25_INSTR_BADDR"       ,	   0x11f0000012990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT26_INSTR_BADDR"       ,	   0x11f00000129a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT27_INSTR_BADDR"       ,	   0x11f00000129b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT28_INSTR_BADDR"       ,	   0x11f00000129c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT29_INSTR_BADDR"       ,	   0x11f00000129d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT30_INSTR_BADDR"       ,	   0x11f00000129e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT31_INSTR_BADDR"       ,	   0x11f00000129f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
-	{"SLI_PKT0_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT1_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT2_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT3_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT4_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT5_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT6_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT7_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT8_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT9_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT10_INSTR_BAOFF_DBELL" ,	   0x11f0000012ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT11_INSTR_BAOFF_DBELL" ,	   0x11f0000012cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT12_INSTR_BAOFF_DBELL" ,	   0x11f0000012cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT13_INSTR_BAOFF_DBELL" ,	   0x11f0000012cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT14_INSTR_BAOFF_DBELL" ,	   0x11f0000012ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT15_INSTR_BAOFF_DBELL" ,	   0x11f0000012cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT16_INSTR_BAOFF_DBELL" ,	   0x11f0000012d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT17_INSTR_BAOFF_DBELL" ,	   0x11f0000012d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT18_INSTR_BAOFF_DBELL" ,	   0x11f0000012d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT19_INSTR_BAOFF_DBELL" ,	   0x11f0000012d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT20_INSTR_BAOFF_DBELL" ,	   0x11f0000012d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT21_INSTR_BAOFF_DBELL" ,	   0x11f0000012d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT22_INSTR_BAOFF_DBELL" ,	   0x11f0000012d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT23_INSTR_BAOFF_DBELL" ,	   0x11f0000012d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT24_INSTR_BAOFF_DBELL" ,	   0x11f0000012d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT25_INSTR_BAOFF_DBELL" ,	   0x11f0000012d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT26_INSTR_BAOFF_DBELL" ,	   0x11f0000012da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT27_INSTR_BAOFF_DBELL" ,	   0x11f0000012db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT28_INSTR_BAOFF_DBELL" ,	   0x11f0000012dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT29_INSTR_BAOFF_DBELL" ,	   0x11f0000012dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT30_INSTR_BAOFF_DBELL" ,	   0x11f0000012de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT31_INSTR_BAOFF_DBELL" ,	   0x11f0000012df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
-	{"SLI_PKT0_INSTR_FIFO_RSIZE"   ,	   0x11f0000013000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT1_INSTR_FIFO_RSIZE"   ,	   0x11f0000013010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT2_INSTR_FIFO_RSIZE"   ,	   0x11f0000013020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT3_INSTR_FIFO_RSIZE"   ,	   0x11f0000013030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT4_INSTR_FIFO_RSIZE"   ,	   0x11f0000013040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT5_INSTR_FIFO_RSIZE"   ,	   0x11f0000013050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT6_INSTR_FIFO_RSIZE"   ,	   0x11f0000013060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT7_INSTR_FIFO_RSIZE"   ,	   0x11f0000013070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT8_INSTR_FIFO_RSIZE"   ,	   0x11f0000013080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT9_INSTR_FIFO_RSIZE"   ,	   0x11f0000013090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT10_INSTR_FIFO_RSIZE"  ,	   0x11f00000130a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT11_INSTR_FIFO_RSIZE"  ,	   0x11f00000130b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT12_INSTR_FIFO_RSIZE"  ,	   0x11f00000130c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT13_INSTR_FIFO_RSIZE"  ,	   0x11f00000130d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT14_INSTR_FIFO_RSIZE"  ,	   0x11f00000130e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT15_INSTR_FIFO_RSIZE"  ,	   0x11f00000130f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT16_INSTR_FIFO_RSIZE"  ,	   0x11f0000013100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT17_INSTR_FIFO_RSIZE"  ,	   0x11f0000013110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT18_INSTR_FIFO_RSIZE"  ,	   0x11f0000013120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT19_INSTR_FIFO_RSIZE"  ,	   0x11f0000013130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT20_INSTR_FIFO_RSIZE"  ,	   0x11f0000013140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT21_INSTR_FIFO_RSIZE"  ,	   0x11f0000013150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT22_INSTR_FIFO_RSIZE"  ,	   0x11f0000013160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT23_INSTR_FIFO_RSIZE"  ,	   0x11f0000013170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT24_INSTR_FIFO_RSIZE"  ,	   0x11f0000013180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT25_INSTR_FIFO_RSIZE"  ,	   0x11f0000013190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT26_INSTR_FIFO_RSIZE"  ,	   0x11f00000131a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT27_INSTR_FIFO_RSIZE"  ,	   0x11f00000131b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT28_INSTR_FIFO_RSIZE"  ,	   0x11f00000131c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT29_INSTR_FIFO_RSIZE"  ,	   0x11f00000131d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT30_INSTR_FIFO_RSIZE"  ,	   0x11f00000131e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT31_INSTR_FIFO_RSIZE"  ,	   0x11f00000131f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
-	{"SLI_PKT0_INSTR_HEADER"       ,	   0x11f0000013400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT1_INSTR_HEADER"       ,	   0x11f0000013410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT2_INSTR_HEADER"       ,	   0x11f0000013420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT3_INSTR_HEADER"       ,	   0x11f0000013430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT4_INSTR_HEADER"       ,	   0x11f0000013440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT5_INSTR_HEADER"       ,	   0x11f0000013450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT6_INSTR_HEADER"       ,	   0x11f0000013460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT7_INSTR_HEADER"       ,	   0x11f0000013470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT8_INSTR_HEADER"       ,	   0x11f0000013480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT9_INSTR_HEADER"       ,	   0x11f0000013490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT10_INSTR_HEADER"      ,	   0x11f00000134a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT11_INSTR_HEADER"      ,	   0x11f00000134b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT12_INSTR_HEADER"      ,	   0x11f00000134c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT13_INSTR_HEADER"      ,	   0x11f00000134d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT14_INSTR_HEADER"      ,	   0x11f00000134e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT15_INSTR_HEADER"      ,	   0x11f00000134f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT16_INSTR_HEADER"      ,	   0x11f0000013500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT17_INSTR_HEADER"      ,	   0x11f0000013510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT18_INSTR_HEADER"      ,	   0x11f0000013520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT19_INSTR_HEADER"      ,	   0x11f0000013530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT20_INSTR_HEADER"      ,	   0x11f0000013540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT21_INSTR_HEADER"      ,	   0x11f0000013550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT22_INSTR_HEADER"      ,	   0x11f0000013560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT23_INSTR_HEADER"      ,	   0x11f0000013570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT24_INSTR_HEADER"      ,	   0x11f0000013580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT25_INSTR_HEADER"      ,	   0x11f0000013590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT26_INSTR_HEADER"      ,	   0x11f00000135a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT27_INSTR_HEADER"      ,	   0x11f00000135b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT28_INSTR_HEADER"      ,	   0x11f00000135c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT29_INSTR_HEADER"      ,	   0x11f00000135d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT30_INSTR_HEADER"      ,	   0x11f00000135e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT31_INSTR_HEADER"      ,	   0x11f00000135f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
-	{"SLI_PKT0_OUT_SIZE"           ,	   0x11f0000010c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT1_OUT_SIZE"           ,	   0x11f0000010c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT2_OUT_SIZE"           ,	   0x11f0000010c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT3_OUT_SIZE"           ,	   0x11f0000010c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT4_OUT_SIZE"           ,	   0x11f0000010c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT5_OUT_SIZE"           ,	   0x11f0000010c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT6_OUT_SIZE"           ,	   0x11f0000010c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT7_OUT_SIZE"           ,	   0x11f0000010c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT8_OUT_SIZE"           ,	   0x11f0000010c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT9_OUT_SIZE"           ,	   0x11f0000010c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT10_OUT_SIZE"          ,	   0x11f0000010ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT11_OUT_SIZE"          ,	   0x11f0000010cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT12_OUT_SIZE"          ,	   0x11f0000010cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT13_OUT_SIZE"          ,	   0x11f0000010cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT14_OUT_SIZE"          ,	   0x11f0000010ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT15_OUT_SIZE"          ,	   0x11f0000010cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT16_OUT_SIZE"          ,	   0x11f0000010d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT17_OUT_SIZE"          ,	   0x11f0000010d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT18_OUT_SIZE"          ,	   0x11f0000010d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT19_OUT_SIZE"          ,	   0x11f0000010d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT20_OUT_SIZE"          ,	   0x11f0000010d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT21_OUT_SIZE"          ,	   0x11f0000010d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT22_OUT_SIZE"          ,	   0x11f0000010d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT23_OUT_SIZE"          ,	   0x11f0000010d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT24_OUT_SIZE"          ,	   0x11f0000010d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT25_OUT_SIZE"          ,	   0x11f0000010d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT26_OUT_SIZE"          ,	   0x11f0000010da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT27_OUT_SIZE"          ,	   0x11f0000010db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT28_OUT_SIZE"          ,	   0x11f0000010dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT29_OUT_SIZE"          ,	   0x11f0000010dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT30_OUT_SIZE"          ,	   0x11f0000010de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT31_OUT_SIZE"          ,	   0x11f0000010df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
-	{"SLI_PKT0_SLIST_BADDR"        ,	   0x11f0000011400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT1_SLIST_BADDR"        ,	   0x11f0000011410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT2_SLIST_BADDR"        ,	   0x11f0000011420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT3_SLIST_BADDR"        ,	   0x11f0000011430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT4_SLIST_BADDR"        ,	   0x11f0000011440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT5_SLIST_BADDR"        ,	   0x11f0000011450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT6_SLIST_BADDR"        ,	   0x11f0000011460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT7_SLIST_BADDR"        ,	   0x11f0000011470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT8_SLIST_BADDR"        ,	   0x11f0000011480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT9_SLIST_BADDR"        ,	   0x11f0000011490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT10_SLIST_BADDR"       ,	   0x11f00000114a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT11_SLIST_BADDR"       ,	   0x11f00000114b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT12_SLIST_BADDR"       ,	   0x11f00000114c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT13_SLIST_BADDR"       ,	   0x11f00000114d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT14_SLIST_BADDR"       ,	   0x11f00000114e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT15_SLIST_BADDR"       ,	   0x11f00000114f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT16_SLIST_BADDR"       ,	   0x11f0000011500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT17_SLIST_BADDR"       ,	   0x11f0000011510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT18_SLIST_BADDR"       ,	   0x11f0000011520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT19_SLIST_BADDR"       ,	   0x11f0000011530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT20_SLIST_BADDR"       ,	   0x11f0000011540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT21_SLIST_BADDR"       ,	   0x11f0000011550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT22_SLIST_BADDR"       ,	   0x11f0000011560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT23_SLIST_BADDR"       ,	   0x11f0000011570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT24_SLIST_BADDR"       ,	   0x11f0000011580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT25_SLIST_BADDR"       ,	   0x11f0000011590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT26_SLIST_BADDR"       ,	   0x11f00000115a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT27_SLIST_BADDR"       ,	   0x11f00000115b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT28_SLIST_BADDR"       ,	   0x11f00000115c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT29_SLIST_BADDR"       ,	   0x11f00000115d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT30_SLIST_BADDR"       ,	   0x11f00000115e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT31_SLIST_BADDR"       ,	   0x11f00000115f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
-	{"SLI_PKT0_SLIST_BAOFF_DBELL"  ,	   0x11f0000011800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT1_SLIST_BAOFF_DBELL"  ,	   0x11f0000011810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT2_SLIST_BAOFF_DBELL"  ,	   0x11f0000011820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT3_SLIST_BAOFF_DBELL"  ,	   0x11f0000011830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT4_SLIST_BAOFF_DBELL"  ,	   0x11f0000011840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT5_SLIST_BAOFF_DBELL"  ,	   0x11f0000011850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT6_SLIST_BAOFF_DBELL"  ,	   0x11f0000011860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT7_SLIST_BAOFF_DBELL"  ,	   0x11f0000011870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT8_SLIST_BAOFF_DBELL"  ,	   0x11f0000011880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT9_SLIST_BAOFF_DBELL"  ,	   0x11f0000011890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT10_SLIST_BAOFF_DBELL" ,	   0x11f00000118a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT11_SLIST_BAOFF_DBELL" ,	   0x11f00000118b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT12_SLIST_BAOFF_DBELL" ,	   0x11f00000118c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT13_SLIST_BAOFF_DBELL" ,	   0x11f00000118d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT14_SLIST_BAOFF_DBELL" ,	   0x11f00000118e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT15_SLIST_BAOFF_DBELL" ,	   0x11f00000118f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT16_SLIST_BAOFF_DBELL" ,	   0x11f0000011900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT17_SLIST_BAOFF_DBELL" ,	   0x11f0000011910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT18_SLIST_BAOFF_DBELL" ,	   0x11f0000011920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT19_SLIST_BAOFF_DBELL" ,	   0x11f0000011930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT20_SLIST_BAOFF_DBELL" ,	   0x11f0000011940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT21_SLIST_BAOFF_DBELL" ,	   0x11f0000011950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT22_SLIST_BAOFF_DBELL" ,	   0x11f0000011960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT23_SLIST_BAOFF_DBELL" ,	   0x11f0000011970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT24_SLIST_BAOFF_DBELL" ,	   0x11f0000011980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT25_SLIST_BAOFF_DBELL" ,	   0x11f0000011990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT26_SLIST_BAOFF_DBELL" ,	   0x11f00000119a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT27_SLIST_BAOFF_DBELL" ,	   0x11f00000119b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT28_SLIST_BAOFF_DBELL" ,	   0x11f00000119c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT29_SLIST_BAOFF_DBELL" ,	   0x11f00000119d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT30_SLIST_BAOFF_DBELL" ,	   0x11f00000119e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT31_SLIST_BAOFF_DBELL" ,	   0x11f00000119f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
-	{"SLI_PKT0_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT1_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT2_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT3_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT4_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT5_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT6_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT7_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT8_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT9_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT10_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT11_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT12_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT13_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT14_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT15_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT16_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT17_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT18_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT19_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT20_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT21_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT22_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT23_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT24_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT25_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT26_SLIST_FIFO_RSIZE"  ,	   0x11f0000011da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT27_SLIST_FIFO_RSIZE"  ,	   0x11f0000011db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT28_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT29_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT30_SLIST_FIFO_RSIZE"  ,	   0x11f0000011de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT31_SLIST_FIFO_RSIZE"  ,	   0x11f0000011df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
-	{"SLI_PKT_CNT_INT"             ,	   0x11f0000011130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
-	{"SLI_PKT_CNT_INT_ENB"         ,	   0x11f0000011150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
-	{"SLI_PKT_CTL"                 ,	   0x11f0000011220ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
-	{"SLI_PKT_DATA_OUT_ES"         ,	   0x11f00000110b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
-	{"SLI_PKT_DATA_OUT_NS"         ,	   0x11f00000110a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
-	{"SLI_PKT_DATA_OUT_ROR"        ,	   0x11f0000011090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
-	{"SLI_PKT_DPADDR"              ,	   0x11f0000011080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	952},
-	{"SLI_PKT_IN_BP"               ,	   0x11f0000011210ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	953},
-	{"SLI_PKT_IN_DONE0_CNTS"       ,	   0x11f0000012000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE1_CNTS"       ,	   0x11f0000012010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE2_CNTS"       ,	   0x11f0000012020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE3_CNTS"       ,	   0x11f0000012030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE4_CNTS"       ,	   0x11f0000012040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE5_CNTS"       ,	   0x11f0000012050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE6_CNTS"       ,	   0x11f0000012060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE7_CNTS"       ,	   0x11f0000012070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE8_CNTS"       ,	   0x11f0000012080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE9_CNTS"       ,	   0x11f0000012090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE10_CNTS"      ,	   0x11f00000120a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE11_CNTS"      ,	   0x11f00000120b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE12_CNTS"      ,	   0x11f00000120c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE13_CNTS"      ,	   0x11f00000120d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE14_CNTS"      ,	   0x11f00000120e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE15_CNTS"      ,	   0x11f00000120f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE16_CNTS"      ,	   0x11f0000012100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE17_CNTS"      ,	   0x11f0000012110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE18_CNTS"      ,	   0x11f0000012120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE19_CNTS"      ,	   0x11f0000012130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE20_CNTS"      ,	   0x11f0000012140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE21_CNTS"      ,	   0x11f0000012150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE22_CNTS"      ,	   0x11f0000012160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE23_CNTS"      ,	   0x11f0000012170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE24_CNTS"      ,	   0x11f0000012180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE25_CNTS"      ,	   0x11f0000012190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE26_CNTS"      ,	   0x11f00000121a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE27_CNTS"      ,	   0x11f00000121b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE28_CNTS"      ,	   0x11f00000121c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE29_CNTS"      ,	   0x11f00000121d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE30_CNTS"      ,	   0x11f00000121e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_DONE31_CNTS"      ,	   0x11f00000121f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
-	{"SLI_PKT_IN_INSTR_COUNTS"     ,	   0x11f0000011200ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	955},
-	{"SLI_PKT_IN_PCIE_PORT"        ,	   0x11f00000111b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	956},
-	{"SLI_PKT_INPUT_CONTROL"       ,	   0x11f0000011170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	957},
-	{"SLI_PKT_INSTR_ENB"           ,	   0x11f0000011000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	958},
-	{"SLI_PKT_INSTR_RD_SIZE"       ,	   0x11f00000111a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	959},
-	{"SLI_PKT_INSTR_SIZE"          ,	   0x11f0000011020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
-	{"SLI_PKT_INT_LEVELS"          ,	   0x11f0000011120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	961},
-	{"SLI_PKT_IPTR"                ,	   0x11f0000011070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	962},
-	{"SLI_PKT_OUT_BMODE"           ,	   0x11f00000110d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	963},
-	{"SLI_PKT_OUT_ENB"             ,	   0x11f0000011010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	964},
-	{"SLI_PKT_OUTPUT_WMARK"        ,	   0x11f0000011180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	965},
-	{"SLI_PKT_PCIE_PORT"           ,	   0x11f00000110e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	966},
-	{"SLI_PKT_PORT_IN_RST"         ,	   0x11f00000111f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	967},
-	{"SLI_PKT_SLIST_ES"            ,	   0x11f0000011050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	968},
-	{"SLI_PKT_SLIST_NS"            ,	   0x11f0000011040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
-	{"SLI_PKT_SLIST_ROR"           ,	   0x11f0000011030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	970},
-	{"SLI_PKT_TIME_INT"            ,	   0x11f0000011140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	971},
-	{"SLI_PKT_TIME_INT_ENB"        ,	   0x11f0000011160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	972},
-	{"SLI_S2M_PORT0_CTL"           ,	   0x11f0000013d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	973},
-	{"SLI_S2M_PORT1_CTL"           ,	   0x11f0000013d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	973},
-	{"SLI_SCRATCH_1"               ,	   0x11f00000103c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	974},
-	{"SLI_SCRATCH_2"               ,	   0x11f00000103d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	975},
-	{"SLI_STATE1"                  ,	   0x11f0000010620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	976},
-	{"SLI_STATE2"                  ,	   0x11f0000010630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
-	{"SLI_STATE3"                  ,	   0x11f0000010640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	978},
-	{"SLI_WIN_RD_ADDR"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	979},
-	{"SLI_WIN_RD_DATA"             ,	              0x40ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	980},
-	{"SLI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	981},
-	{"SLI_WIN_WR_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	982},
-	{"SLI_WIN_WR_MASK"             ,	              0x30ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	983},
-	{"SLI_WINDOW_CTL"              ,	   0x11f00000102e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	984},
-	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	985},
-	{"SMI1_CLK"                    ,	   0x1180000001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	985},
-	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
-	{"SMI1_CMD"                    ,	   0x1180000001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
-	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	987},
-	{"SMI1_EN"                     ,	   0x1180000001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	987},
-	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SMI1_RD_DAT"                 ,	   0x1180000001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
-	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SMI1_WR_DAT"                 ,	   0x1180000001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
-	{"SMI_DRV_CTL"                 ,	   0x1180000001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	990},
-	{"SRIO0_ACC_CTRL"              ,	   0x11800c8000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	991},
-	{"SRIO1_ACC_CTRL"              ,	   0x11800c9000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	991},
-	{"SRIO0_ASMBLY_ID"             ,	   0x11800c8000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	992},
-	{"SRIO1_ASMBLY_ID"             ,	   0x11800c9000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	992},
-	{"SRIO0_ASMBLY_INFO"           ,	   0x11800c8000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	993},
-	{"SRIO1_ASMBLY_INFO"           ,	   0x11800c9000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	993},
-	{"SRIO0_BELL_RESP_CTRL"        ,	   0x11800c8000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
-	{"SRIO1_BELL_RESP_CTRL"        ,	   0x11800c9000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
-	{"SRIO0_BIST_STATUS"           ,	   0x11800c8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
-	{"SRIO1_BIST_STATUS"           ,	   0x11800c9000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
-	{"SRIO0_IMSG_CTRL"             ,	   0x11800c8000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	996},
-	{"SRIO1_IMSG_CTRL"             ,	   0x11800c9000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	996},
-	{"SRIO0_IMSG_INST_HDR000"      ,	   0x11800c8000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
-	{"SRIO0_IMSG_INST_HDR001"      ,	   0x11800c8000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
-	{"SRIO1_IMSG_INST_HDR000"      ,	   0x11800c9000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
-	{"SRIO1_IMSG_INST_HDR001"      ,	   0x11800c9000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
-	{"SRIO0_IMSG_QOS_GRP000"       ,	   0x11800c8000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP001"       ,	   0x11800c8000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP002"       ,	   0x11800c8000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP003"       ,	   0x11800c8000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP004"       ,	   0x11800c8000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP005"       ,	   0x11800c8000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP006"       ,	   0x11800c8000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP007"       ,	   0x11800c8000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP008"       ,	   0x11800c8000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP009"       ,	   0x11800c8000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP010"       ,	   0x11800c8000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP011"       ,	   0x11800c8000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP012"       ,	   0x11800c8000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP013"       ,	   0x11800c8000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP014"       ,	   0x11800c8000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP015"       ,	   0x11800c8000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP016"       ,	   0x11800c8000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP017"       ,	   0x11800c8000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP018"       ,	   0x11800c8000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP019"       ,	   0x11800c8000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP020"       ,	   0x11800c80006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP021"       ,	   0x11800c80006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP022"       ,	   0x11800c80006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP023"       ,	   0x11800c80006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP024"       ,	   0x11800c80006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP025"       ,	   0x11800c80006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP026"       ,	   0x11800c80006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP027"       ,	   0x11800c80006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP028"       ,	   0x11800c80006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP029"       ,	   0x11800c80006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP030"       ,	   0x11800c80006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_QOS_GRP031"       ,	   0x11800c80006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP000"       ,	   0x11800c9000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP001"       ,	   0x11800c9000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP002"       ,	   0x11800c9000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP003"       ,	   0x11800c9000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP004"       ,	   0x11800c9000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP005"       ,	   0x11800c9000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP006"       ,	   0x11800c9000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP007"       ,	   0x11800c9000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP008"       ,	   0x11800c9000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP009"       ,	   0x11800c9000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP010"       ,	   0x11800c9000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP011"       ,	   0x11800c9000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP012"       ,	   0x11800c9000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP013"       ,	   0x11800c9000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP014"       ,	   0x11800c9000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP015"       ,	   0x11800c9000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP016"       ,	   0x11800c9000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP017"       ,	   0x11800c9000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP018"       ,	   0x11800c9000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP019"       ,	   0x11800c9000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP020"       ,	   0x11800c90006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP021"       ,	   0x11800c90006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP022"       ,	   0x11800c90006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP023"       ,	   0x11800c90006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP024"       ,	   0x11800c90006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP025"       ,	   0x11800c90006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP026"       ,	   0x11800c90006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP027"       ,	   0x11800c90006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP028"       ,	   0x11800c90006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP029"       ,	   0x11800c90006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP030"       ,	   0x11800c90006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO1_IMSG_QOS_GRP031"       ,	   0x11800c90006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
-	{"SRIO0_IMSG_STATUS000"        ,	   0x11800c8000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS001"        ,	   0x11800c8000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS002"        ,	   0x11800c8000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS003"        ,	   0x11800c8000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS004"        ,	   0x11800c8000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS005"        ,	   0x11800c8000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS006"        ,	   0x11800c8000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS007"        ,	   0x11800c8000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS008"        ,	   0x11800c8000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS009"        ,	   0x11800c8000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS010"        ,	   0x11800c8000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS011"        ,	   0x11800c8000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS012"        ,	   0x11800c8000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS013"        ,	   0x11800c8000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS014"        ,	   0x11800c8000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS015"        ,	   0x11800c8000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS016"        ,	   0x11800c8000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS017"        ,	   0x11800c8000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS018"        ,	   0x11800c8000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS019"        ,	   0x11800c8000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS020"        ,	   0x11800c80007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS021"        ,	   0x11800c80007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS022"        ,	   0x11800c80007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_STATUS023"        ,	   0x11800c80007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS000"        ,	   0x11800c9000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS001"        ,	   0x11800c9000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS002"        ,	   0x11800c9000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS003"        ,	   0x11800c9000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS004"        ,	   0x11800c9000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS005"        ,	   0x11800c9000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS006"        ,	   0x11800c9000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS007"        ,	   0x11800c9000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS008"        ,	   0x11800c9000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS009"        ,	   0x11800c9000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS010"        ,	   0x11800c9000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS011"        ,	   0x11800c9000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS012"        ,	   0x11800c9000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS013"        ,	   0x11800c9000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS014"        ,	   0x11800c9000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS015"        ,	   0x11800c9000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS016"        ,	   0x11800c9000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS017"        ,	   0x11800c9000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS018"        ,	   0x11800c9000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS019"        ,	   0x11800c9000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS020"        ,	   0x11800c90007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS021"        ,	   0x11800c90007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS022"        ,	   0x11800c90007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO1_IMSG_STATUS023"        ,	   0x11800c90007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
-	{"SRIO0_IMSG_VPORT_THR"        ,	   0x11800c8000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1000},
-	{"SRIO1_IMSG_VPORT_THR"        ,	   0x11800c9000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1000},
-	{"SRIO0_INT2_ENABLE"           ,	   0x11800c80003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1001},
-	{"SRIO1_INT2_ENABLE"           ,	   0x11800c90003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1001},
-	{"SRIO0_INT2_REG"              ,	   0x11800c80003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
-	{"SRIO1_INT2_REG"              ,	   0x11800c90003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
-	{"SRIO0_INT_ENABLE"            ,	   0x11800c8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
-	{"SRIO1_INT_ENABLE"            ,	   0x11800c9000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
-	{"SRIO0_INT_INFO0"             ,	   0x11800c8000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
-	{"SRIO1_INT_INFO0"             ,	   0x11800c9000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
-	{"SRIO0_INT_INFO1"             ,	   0x11800c8000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
-	{"SRIO1_INT_INFO1"             ,	   0x11800c9000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
-	{"SRIO0_INT_INFO2"             ,	   0x11800c8000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
-	{"SRIO1_INT_INFO2"             ,	   0x11800c9000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
-	{"SRIO0_INT_INFO3"             ,	   0x11800c8000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
-	{"SRIO1_INT_INFO3"             ,	   0x11800c9000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
-	{"SRIO0_INT_REG"               ,	   0x11800c8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
-	{"SRIO1_INT_REG"               ,	   0x11800c9000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
-	{"SRIO0_IP_FEATURE"            ,	   0x11800c80003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1009},
-	{"SRIO1_IP_FEATURE"            ,	   0x11800c90003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1009},
-	{"SRIO0_MAC_BUFFERS"           ,	   0x11800c8000390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO1_MAC_BUFFERS"           ,	   0x11800c9000390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
-	{"SRIO0_MAINT_OP"              ,	   0x11800c8000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
-	{"SRIO1_MAINT_OP"              ,	   0x11800c9000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
-	{"SRIO0_MAINT_RD_DATA"         ,	   0x11800c8000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
-	{"SRIO1_MAINT_RD_DATA"         ,	   0x11800c9000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
-	{"SRIO0_MCE_TX_CTL"            ,	   0x11800c8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
-	{"SRIO1_MCE_TX_CTL"            ,	   0x11800c9000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
-	{"SRIO0_MEM_OP_CTRL"           ,	   0x11800c8000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
-	{"SRIO1_MEM_OP_CTRL"           ,	   0x11800c9000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
-	{"SRIO0_OMSG_CTRL000"          ,	   0x11800c8000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
-	{"SRIO0_OMSG_CTRL001"          ,	   0x11800c80004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
-	{"SRIO1_OMSG_CTRL000"          ,	   0x11800c9000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
-	{"SRIO1_OMSG_CTRL001"          ,	   0x11800c90004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
-	{"SRIO0_OMSG_DONE_COUNTS000"   ,	   0x11800c80004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
-	{"SRIO0_OMSG_DONE_COUNTS001"   ,	   0x11800c80004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
-	{"SRIO1_OMSG_DONE_COUNTS000"   ,	   0x11800c90004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
-	{"SRIO1_OMSG_DONE_COUNTS001"   ,	   0x11800c90004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
-	{"SRIO0_OMSG_FMP_MR000"        ,	   0x11800c8000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
-	{"SRIO0_OMSG_FMP_MR001"        ,	   0x11800c80004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
-	{"SRIO1_OMSG_FMP_MR000"        ,	   0x11800c9000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
-	{"SRIO1_OMSG_FMP_MR001"        ,	   0x11800c90004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
-	{"SRIO0_OMSG_NMP_MR000"        ,	   0x11800c80004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
-	{"SRIO0_OMSG_NMP_MR001"        ,	   0x11800c80004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
-	{"SRIO1_OMSG_NMP_MR000"        ,	   0x11800c90004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
-	{"SRIO1_OMSG_NMP_MR001"        ,	   0x11800c90004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
-	{"SRIO0_OMSG_PORT000"          ,	   0x11800c8000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
-	{"SRIO0_OMSG_PORT001"          ,	   0x11800c80004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
-	{"SRIO1_OMSG_PORT000"          ,	   0x11800c9000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
-	{"SRIO1_OMSG_PORT001"          ,	   0x11800c90004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
-	{"SRIO0_OMSG_SILO_THR"         ,	   0x11800c80004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
-	{"SRIO1_OMSG_SILO_THR"         ,	   0x11800c90004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
-	{"SRIO0_OMSG_SP_MR000"         ,	   0x11800c8000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
-	{"SRIO0_OMSG_SP_MR001"         ,	   0x11800c80004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
-	{"SRIO1_OMSG_SP_MR000"         ,	   0x11800c9000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
-	{"SRIO1_OMSG_SP_MR001"         ,	   0x11800c90004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
-	{"SRIO0_PRIO000_IN_USE"        ,	   0x11800c80003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
-	{"SRIO0_PRIO001_IN_USE"        ,	   0x11800c80003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
-	{"SRIO0_PRIO002_IN_USE"        ,	   0x11800c80003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
-	{"SRIO0_PRIO003_IN_USE"        ,	   0x11800c80003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
-	{"SRIO1_PRIO000_IN_USE"        ,	   0x11800c90003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
-	{"SRIO1_PRIO001_IN_USE"        ,	   0x11800c90003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
-	{"SRIO1_PRIO002_IN_USE"        ,	   0x11800c90003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
-	{"SRIO1_PRIO003_IN_USE"        ,	   0x11800c90003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
-	{"SRIO0_RX_BELL"               ,	   0x11800c8000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1023},
-	{"SRIO1_RX_BELL"               ,	   0x11800c9000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1023},
-	{"SRIO0_RX_BELL_SEQ"           ,	   0x11800c8000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
-	{"SRIO1_RX_BELL_SEQ"           ,	   0x11800c9000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
-	{"SRIO0_RX_STATUS"             ,	   0x11800c8000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
-	{"SRIO1_RX_STATUS"             ,	   0x11800c9000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
-	{"SRIO0_S2M_TYPE000"           ,	   0x11800c8000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO0_S2M_TYPE001"           ,	   0x11800c8000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO0_S2M_TYPE002"           ,	   0x11800c8000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO0_S2M_TYPE003"           ,	   0x11800c8000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO0_S2M_TYPE004"           ,	   0x11800c80001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO0_S2M_TYPE005"           ,	   0x11800c80001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO0_S2M_TYPE006"           ,	   0x11800c80001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO0_S2M_TYPE007"           ,	   0x11800c80001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO0_S2M_TYPE008"           ,	   0x11800c80001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO0_S2M_TYPE009"           ,	   0x11800c80001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO0_S2M_TYPE010"           ,	   0x11800c80001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO0_S2M_TYPE011"           ,	   0x11800c80001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO0_S2M_TYPE012"           ,	   0x11800c80001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO0_S2M_TYPE013"           ,	   0x11800c80001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO0_S2M_TYPE014"           ,	   0x11800c80001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO0_S2M_TYPE015"           ,	   0x11800c80001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO1_S2M_TYPE000"           ,	   0x11800c9000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO1_S2M_TYPE001"           ,	   0x11800c9000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO1_S2M_TYPE002"           ,	   0x11800c9000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO1_S2M_TYPE003"           ,	   0x11800c9000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO1_S2M_TYPE004"           ,	   0x11800c90001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO1_S2M_TYPE005"           ,	   0x11800c90001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO1_S2M_TYPE006"           ,	   0x11800c90001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO1_S2M_TYPE007"           ,	   0x11800c90001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO1_S2M_TYPE008"           ,	   0x11800c90001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO1_S2M_TYPE009"           ,	   0x11800c90001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO1_S2M_TYPE010"           ,	   0x11800c90001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO1_S2M_TYPE011"           ,	   0x11800c90001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO1_S2M_TYPE012"           ,	   0x11800c90001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO1_S2M_TYPE013"           ,	   0x11800c90001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO1_S2M_TYPE014"           ,	   0x11800c90001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO1_S2M_TYPE015"           ,	   0x11800c90001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
-	{"SRIO0_SEQ"                   ,	   0x11800c8000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
-	{"SRIO1_SEQ"                   ,	   0x11800c9000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
-	{"SRIO0_STATUS_REG"            ,	   0x11800c8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
-	{"SRIO1_STATUS_REG"            ,	   0x11800c9000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
-	{"SRIO0_TAG_CTRL"              ,	   0x11800c8000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1029},
-	{"SRIO1_TAG_CTRL"              ,	   0x11800c9000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1029},
-	{"SRIO0_TLP_CREDITS"           ,	   0x11800c8000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1030},
-	{"SRIO1_TLP_CREDITS"           ,	   0x11800c9000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1030},
-	{"SRIO0_TX_BELL"               ,	   0x11800c8000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
-	{"SRIO1_TX_BELL"               ,	   0x11800c9000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
-	{"SRIO0_TX_BELL_INFO"          ,	   0x11800c8000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
-	{"SRIO1_TX_BELL_INFO"          ,	   0x11800c9000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
-	{"SRIO0_TX_CTRL"               ,	   0x11800c8000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
-	{"SRIO1_TX_CTRL"               ,	   0x11800c9000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
-	{"SRIO0_TX_EMPHASIS"           ,	   0x11800c80003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
-	{"SRIO1_TX_EMPHASIS"           ,	   0x11800c90003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
-	{"SRIO0_TX_STATUS"             ,	   0x11800c8000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
-	{"SRIO1_TX_STATUS"             ,	   0x11800c9000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
-	{"SRIO0_WR_DONE_COUNTS"        ,	   0x11800c8000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
-	{"SRIO1_WR_DONE_COUNTS"        ,	   0x11800c9000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
-	{"SRIOMAINT0_ASMBLY_ID"        ,	               0x8ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1037},
-	{"SRIOMAINT1_ASMBLY_ID"        ,	               0x8ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1037},
-	{"SRIOMAINT0_ASMBLY_INFO"      ,	               0xcull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1038},
-	{"SRIOMAINT1_ASMBLY_INFO"      ,	               0xcull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1038},
-	{"SRIOMAINT0_BAR1_IDX000"      ,	          0x200010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT0_BAR1_IDX001"      ,	          0x200014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT0_BAR1_IDX002"      ,	          0x200018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT0_BAR1_IDX003"      ,	          0x20001cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT0_BAR1_IDX004"      ,	          0x200020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT0_BAR1_IDX005"      ,	          0x200024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT0_BAR1_IDX006"      ,	          0x200028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT0_BAR1_IDX007"      ,	          0x20002cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT0_BAR1_IDX008"      ,	          0x200030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT0_BAR1_IDX009"      ,	          0x200034ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT0_BAR1_IDX010"      ,	          0x200038ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT0_BAR1_IDX011"      ,	          0x20003cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT0_BAR1_IDX012"      ,	          0x200040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT0_BAR1_IDX013"      ,	          0x200044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT0_BAR1_IDX014"      ,	          0x200048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT0_BAR1_IDX015"      ,	          0x20004cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT1_BAR1_IDX000"      ,	          0x200010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT1_BAR1_IDX001"      ,	          0x200014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT1_BAR1_IDX002"      ,	          0x200018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT1_BAR1_IDX003"      ,	          0x20001cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT1_BAR1_IDX004"      ,	          0x200020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT1_BAR1_IDX005"      ,	          0x200024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT1_BAR1_IDX006"      ,	          0x200028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT1_BAR1_IDX007"      ,	          0x20002cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT1_BAR1_IDX008"      ,	          0x200030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT1_BAR1_IDX009"      ,	          0x200034ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT1_BAR1_IDX010"      ,	          0x200038ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT1_BAR1_IDX011"      ,	          0x20003cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT1_BAR1_IDX012"      ,	          0x200040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT1_BAR1_IDX013"      ,	          0x200044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT1_BAR1_IDX014"      ,	          0x200048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT1_BAR1_IDX015"      ,	          0x20004cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
-	{"SRIOMAINT0_BELL_STATUS"      ,	          0x200080ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1040},
-	{"SRIOMAINT1_BELL_STATUS"      ,	          0x200080ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1040},
-	{"SRIOMAINT0_COMP_TAG"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1041},
-	{"SRIOMAINT1_COMP_TAG"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1041},
-	{"SRIOMAINT0_CORE_ENABLES"     ,	          0x200070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1042},
-	{"SRIOMAINT1_CORE_ENABLES"     ,	          0x200070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1042},
-	{"SRIOMAINT0_DEV_ID"           ,	               0x0ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1043},
-	{"SRIOMAINT1_DEV_ID"           ,	               0x0ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1043},
-	{"SRIOMAINT0_DEV_REV"          ,	               0x4ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1044},
-	{"SRIOMAINT1_DEV_REV"          ,	               0x4ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1044},
-	{"SRIOMAINT0_DST_OPS"          ,	              0x1cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
-	{"SRIOMAINT1_DST_OPS"          ,	              0x1cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
-	{"SRIOMAINT0_ERB_ATTR_CAPT"    ,	            0x2048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1046},
-	{"SRIOMAINT1_ERB_ATTR_CAPT"    ,	            0x2048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1046},
-	{"SRIOMAINT0_ERB_ERR_DET"      ,	            0x2040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1047},
-	{"SRIOMAINT1_ERB_ERR_DET"      ,	            0x2040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1047},
-	{"SRIOMAINT0_ERB_ERR_RATE"     ,	            0x2068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1048},
-	{"SRIOMAINT1_ERB_ERR_RATE"     ,	            0x2068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1048},
-	{"SRIOMAINT0_ERB_ERR_RATE_EN"  ,	            0x2044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1049},
-	{"SRIOMAINT1_ERB_ERR_RATE_EN"  ,	            0x2044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1049},
-	{"SRIOMAINT0_ERB_ERR_RATE_THR" ,	            0x206cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1050},
-	{"SRIOMAINT1_ERB_ERR_RATE_THR" ,	            0x206cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1050},
-	{"SRIOMAINT0_ERB_HDR"          ,	            0x2000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1051},
-	{"SRIOMAINT1_ERB_HDR"          ,	            0x2000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1051},
-	{"SRIOMAINT0_ERB_LT_ADDR_CAPT_H",	            0x2010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1052},
-	{"SRIOMAINT1_ERB_LT_ADDR_CAPT_H",	            0x2010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1052},
-	{"SRIOMAINT0_ERB_LT_ADDR_CAPT_L",	            0x2014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1053},
-	{"SRIOMAINT1_ERB_LT_ADDR_CAPT_L",	            0x2014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1053},
-	{"SRIOMAINT0_ERB_LT_CTRL_CAPT" ,	            0x201cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1054},
-	{"SRIOMAINT1_ERB_LT_CTRL_CAPT" ,	            0x201cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1054},
-	{"SRIOMAINT0_ERB_LT_DEV_ID"    ,	            0x2028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1055},
-	{"SRIOMAINT1_ERB_LT_DEV_ID"    ,	            0x2028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1055},
-	{"SRIOMAINT0_ERB_LT_DEV_ID_CAPT",	            0x2018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1056},
-	{"SRIOMAINT1_ERB_LT_DEV_ID_CAPT",	            0x2018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1056},
-	{"SRIOMAINT0_ERB_LT_ERR_DET"   ,	            0x2008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
-	{"SRIOMAINT1_ERB_LT_ERR_DET"   ,	            0x2008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
-	{"SRIOMAINT0_ERB_LT_ERR_EN"    ,	            0x200cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1058},
-	{"SRIOMAINT1_ERB_LT_ERR_EN"    ,	            0x200cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1058},
-	{"SRIOMAINT0_ERB_PACK_CAPT_1"  ,	            0x2050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1059},
-	{"SRIOMAINT1_ERB_PACK_CAPT_1"  ,	            0x2050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1059},
-	{"SRIOMAINT0_ERB_PACK_CAPT_2"  ,	            0x2054ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1060},
-	{"SRIOMAINT1_ERB_PACK_CAPT_2"  ,	            0x2054ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1060},
-	{"SRIOMAINT0_ERB_PACK_CAPT_3"  ,	            0x2058ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1061},
-	{"SRIOMAINT1_ERB_PACK_CAPT_3"  ,	            0x2058ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1061},
-	{"SRIOMAINT0_ERB_PACK_SYM_CAPT",	            0x204cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1062},
-	{"SRIOMAINT1_ERB_PACK_SYM_CAPT",	            0x204cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1062},
-	{"SRIOMAINT0_HB_DEV_ID_LOCK"   ,	              0x68ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1063},
-	{"SRIOMAINT1_HB_DEV_ID_LOCK"   ,	              0x68ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1063},
-	{"SRIOMAINT0_IR_BUFFER_CONFIG" ,	          0x102000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1064},
-	{"SRIOMAINT1_IR_BUFFER_CONFIG" ,	          0x102000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1064},
-	{"SRIOMAINT0_IR_BUFFER_CONFIG2",	          0x102004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1065},
-	{"SRIOMAINT1_IR_BUFFER_CONFIG2",	          0x102004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1065},
-	{"SRIOMAINT0_IR_PD_PHY_CTRL"   ,	          0x107028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1066},
-	{"SRIOMAINT1_IR_PD_PHY_CTRL"   ,	          0x107028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1066},
-	{"SRIOMAINT0_IR_PD_PHY_STAT"   ,	          0x10702cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1067},
-	{"SRIOMAINT1_IR_PD_PHY_STAT"   ,	          0x10702cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1067},
-	{"SRIOMAINT0_IR_PI_PHY_CTRL"   ,	          0x107020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1068},
-	{"SRIOMAINT1_IR_PI_PHY_CTRL"   ,	          0x107020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1068},
-	{"SRIOMAINT0_IR_PI_PHY_STAT"   ,	          0x107024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1069},
-	{"SRIOMAINT1_IR_PI_PHY_STAT"   ,	          0x107024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1069},
-	{"SRIOMAINT0_IR_SP_RX_CTRL"    ,	          0x10700cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1070},
-	{"SRIOMAINT1_IR_SP_RX_CTRL"    ,	          0x10700cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1070},
-	{"SRIOMAINT0_IR_SP_RX_DATA"    ,	          0x107014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1071},
-	{"SRIOMAINT1_IR_SP_RX_DATA"    ,	          0x107014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1071},
-	{"SRIOMAINT0_IR_SP_RX_STAT"    ,	          0x107010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1072},
-	{"SRIOMAINT1_IR_SP_RX_STAT"    ,	          0x107010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1072},
-	{"SRIOMAINT0_IR_SP_TX_CTRL"    ,	          0x107000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1073},
-	{"SRIOMAINT1_IR_SP_TX_CTRL"    ,	          0x107000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1073},
-	{"SRIOMAINT0_IR_SP_TX_DATA"    ,	          0x107008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1074},
-	{"SRIOMAINT1_IR_SP_TX_DATA"    ,	          0x107008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1074},
-	{"SRIOMAINT0_IR_SP_TX_STAT"    ,	          0x107004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1075},
-	{"SRIOMAINT1_IR_SP_TX_STAT"    ,	          0x107004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1075},
-	{"SRIOMAINT0_LANE_000_STATUS_0",	            0x1010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
-	{"SRIOMAINT0_LANE_001_STATUS_0",	            0x1030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
-	{"SRIOMAINT0_LANE_002_STATUS_0",	            0x1050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
-	{"SRIOMAINT0_LANE_003_STATUS_0",	            0x1070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
-	{"SRIOMAINT1_LANE_000_STATUS_0",	            0x1010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
-	{"SRIOMAINT1_LANE_001_STATUS_0",	            0x1030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
-	{"SRIOMAINT1_LANE_002_STATUS_0",	            0x1050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
-	{"SRIOMAINT1_LANE_003_STATUS_0",	            0x1070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
-	{"SRIOMAINT0_LCS_BA0"          ,	              0x58ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1077},
-	{"SRIOMAINT1_LCS_BA0"          ,	              0x58ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1077},
-	{"SRIOMAINT0_LCS_BA1"          ,	              0x5cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1078},
-	{"SRIOMAINT1_LCS_BA1"          ,	              0x5cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1078},
-	{"SRIOMAINT0_M2S_BAR0_START0"  ,	          0x200000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1079},
-	{"SRIOMAINT1_M2S_BAR0_START0"  ,	          0x200000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1079},
-	{"SRIOMAINT0_M2S_BAR0_START1"  ,	          0x200004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1080},
-	{"SRIOMAINT1_M2S_BAR0_START1"  ,	          0x200004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1080},
-	{"SRIOMAINT0_M2S_BAR1_START0"  ,	          0x200008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1081},
-	{"SRIOMAINT1_M2S_BAR1_START0"  ,	          0x200008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1081},
-	{"SRIOMAINT0_M2S_BAR1_START1"  ,	          0x20000cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1082},
-	{"SRIOMAINT1_M2S_BAR1_START1"  ,	          0x20000cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1082},
-	{"SRIOMAINT0_M2S_BAR2_START"   ,	          0x200050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1083},
-	{"SRIOMAINT1_M2S_BAR2_START"   ,	          0x200050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1083},
-	{"SRIOMAINT0_MAC_CTRL"         ,	          0x200068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1084},
-	{"SRIOMAINT1_MAC_CTRL"         ,	          0x200068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1084},
-	{"SRIOMAINT0_PE_FEAT"          ,	              0x10ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1085},
-	{"SRIOMAINT1_PE_FEAT"          ,	              0x10ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1085},
-	{"SRIOMAINT0_PE_LLC"           ,	              0x4cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1086},
-	{"SRIOMAINT1_PE_LLC"           ,	              0x4cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1086},
-	{"SRIOMAINT0_PORT_0_CTL"       ,	             0x15cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1087},
-	{"SRIOMAINT1_PORT_0_CTL"       ,	             0x15cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1087},
-	{"SRIOMAINT0_PORT_0_CTL2"      ,	             0x154ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1088},
-	{"SRIOMAINT1_PORT_0_CTL2"      ,	             0x154ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1088},
-	{"SRIOMAINT0_PORT_0_ERR_STAT"  ,	             0x158ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1089},
-	{"SRIOMAINT1_PORT_0_ERR_STAT"  ,	             0x158ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1089},
-	{"SRIOMAINT0_PORT_0_LINK_REQ"  ,	             0x140ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1090},
-	{"SRIOMAINT1_PORT_0_LINK_REQ"  ,	             0x140ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1090},
-	{"SRIOMAINT0_PORT_0_LINK_RESP" ,	             0x144ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1091},
-	{"SRIOMAINT1_PORT_0_LINK_RESP" ,	             0x144ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1091},
-	{"SRIOMAINT0_PORT_0_LOCAL_ACKID",	             0x148ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1092},
-	{"SRIOMAINT1_PORT_0_LOCAL_ACKID",	             0x148ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1092},
-	{"SRIOMAINT0_PORT_GEN_CTL"     ,	             0x13cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1093},
-	{"SRIOMAINT1_PORT_GEN_CTL"     ,	             0x13cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1093},
-	{"SRIOMAINT0_PORT_LT_CTL"      ,	             0x120ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1094},
-	{"SRIOMAINT1_PORT_LT_CTL"      ,	             0x120ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1094},
-	{"SRIOMAINT0_PORT_MBH0"        ,	             0x100ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1095},
-	{"SRIOMAINT1_PORT_MBH0"        ,	             0x100ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1095},
-	{"SRIOMAINT0_PORT_RT_CTL"      ,	             0x124ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1096},
-	{"SRIOMAINT1_PORT_RT_CTL"      ,	             0x124ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1096},
-	{"SRIOMAINT0_PORT_TTL_CTL"     ,	             0x12cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1097},
-	{"SRIOMAINT1_PORT_TTL_CTL"     ,	             0x12cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1097},
-	{"SRIOMAINT0_PRI_DEV_ID"       ,	              0x60ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1098},
-	{"SRIOMAINT1_PRI_DEV_ID"       ,	              0x60ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1098},
-	{"SRIOMAINT0_SEC_DEV_CTRL"     ,	          0x200064ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1099},
-	{"SRIOMAINT1_SEC_DEV_CTRL"     ,	          0x200064ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1099},
-	{"SRIOMAINT0_SEC_DEV_ID"       ,	          0x200060ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1100},
-	{"SRIOMAINT1_SEC_DEV_ID"       ,	          0x200060ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1100},
-	{"SRIOMAINT0_SERIAL_LANE_HDR"  ,	            0x1000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1101},
-	{"SRIOMAINT1_SERIAL_LANE_HDR"  ,	            0x1000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1101},
-	{"SRIOMAINT0_SRC_OPS"          ,	              0x18ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1102},
-	{"SRIOMAINT1_SRC_OPS"          ,	              0x18ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1102},
-	{"SRIOMAINT0_TX_DROP"          ,	          0x20006cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1103},
-	{"SRIOMAINT1_TX_DROP"          ,	          0x20006cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1103},
-	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1104},
-	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1105},
-	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1106},
-	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1107},
-	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1108},
-	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1109},
-	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1110},
-	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1111},
-	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1112},
-	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1113},
-	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1114},
-	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1115},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1116},
-	{"TRA_CYCLES_SINCE1"           ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1117},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1118},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1119},
-	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1120},
-	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1121},
-	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1122},
-	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1123},
-	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1124},
-	{"TRA_READ_DAT_HI"             ,	   0x11800a8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1125},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1126},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1127},
-	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1128},
-	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1129},
-	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1130},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1131},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1132},
-	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1133},
-	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1134},
-	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1135},
-	{"UAHC0_EHCI_ASYNCLISTADDR"    ,	   0x16f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1136},
-	{"UAHC0_EHCI_CONFIGFLAG"       ,	   0x16f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1137},
-	{"UAHC0_EHCI_CTRLDSSEGMENT"    ,	   0x16f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1138},
-	{"UAHC0_EHCI_FRINDEX"          ,	   0x16f000000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1139},
-	{"UAHC0_EHCI_HCCAPBASE"        ,	   0x16f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1140},
-	{"UAHC0_EHCI_HCCPARAMS"        ,	   0x16f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1141},
-	{"UAHC0_EHCI_HCSPARAMS"        ,	   0x16f0000000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1142},
-	{"UAHC0_EHCI_INSNREG00"        ,	   0x16f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1143},
-	{"UAHC0_EHCI_INSNREG03"        ,	   0x16f000000009cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1144},
-	{"UAHC0_EHCI_INSNREG04"        ,	   0x16f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1145},
-	{"UAHC0_EHCI_INSNREG06"        ,	   0x16f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1146},
-	{"UAHC0_EHCI_INSNREG07"        ,	   0x16f00000000ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	1147},
-	{"UAHC0_EHCI_PERIODICLISTBASE" ,	   0x16f0000000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1148},
-	{"UAHC0_EHCI_PORTSC001"        ,	   0x16f0000000054ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1149},
-	{"UAHC0_EHCI_PORTSC002"        ,	   0x16f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1149},
-	{"UAHC0_EHCI_USBCMD"           ,	   0x16f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1150},
-	{"UAHC0_EHCI_USBINTR"          ,	   0x16f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1151},
-	{"UAHC0_EHCI_USBSTS"           ,	   0x16f0000000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1152},
-	{"UAHC0_OHCI0_HCBULKCURRENTED" ,	   0x16f000000042cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1153},
-	{"UAHC0_OHCI0_HCBULKHEADED"    ,	   0x16f0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1154},
-	{"UAHC0_OHCI0_HCCOMMANDSTATUS" ,	   0x16f0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1155},
-	{"UAHC0_OHCI0_HCCONTROL"       ,	   0x16f0000000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1156},
-	{"UAHC0_OHCI0_HCCONTROLCURRENTED",	   0x16f0000000424ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1157},
-	{"UAHC0_OHCI0_HCCONTROLHEADED" ,	   0x16f0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1158},
-	{"UAHC0_OHCI0_HCDONEHEAD"      ,	   0x16f0000000430ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1159},
-	{"UAHC0_OHCI0_HCFMINTERVAL"    ,	   0x16f0000000434ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1160},
-	{"UAHC0_OHCI0_HCFMNUMBER"      ,	   0x16f000000043cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1161},
-	{"UAHC0_OHCI0_HCFMREMAINING"   ,	   0x16f0000000438ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1162},
-	{"UAHC0_OHCI0_HCHCCA"          ,	   0x16f0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1163},
-	{"UAHC0_OHCI0_HCINTERRUPTDISABLE",	   0x16f0000000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1164},
-	{"UAHC0_OHCI0_HCINTERRUPTENABLE",	   0x16f0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1165},
-	{"UAHC0_OHCI0_HCINTERRUPTSTATUS",	   0x16f000000040cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1166},
-	{"UAHC0_OHCI0_HCLSTHRESHOLD"   ,	   0x16f0000000444ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1167},
-	{"UAHC0_OHCI0_HCPERIODCURRENTED",	   0x16f000000041cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1168},
-	{"UAHC0_OHCI0_HCPERIODICSTART" ,	   0x16f0000000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1169},
-	{"UAHC0_OHCI0_HCREVISION"      ,	   0x16f0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1170},
-	{"UAHC0_OHCI0_HCRHDESCRIPTORA" ,	   0x16f0000000448ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1171},
-	{"UAHC0_OHCI0_HCRHDESCRIPTORB" ,	   0x16f000000044cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1172},
-	{"UAHC0_OHCI0_HCRHPORTSTATUS001",	   0x16f0000000454ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1173},
-	{"UAHC0_OHCI0_HCRHPORTSTATUS002",	   0x16f0000000458ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1173},
-	{"UAHC0_OHCI0_HCRHSTATUS"      ,	   0x16f0000000450ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1174},
-	{"UAHC0_OHCI0_INSNREG06"       ,	   0x16f0000000498ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1175},
-	{"UAHC0_OHCI0_INSNREG07"       ,	   0x16f000000049cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1176},
-	{"UCTL0_BIST_STATUS"           ,	   0x118006f0000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1177},
-	{"UCTL0_CLK_RST_CTL"           ,	   0x118006f000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1178},
-	{"UCTL0_EHCI_CTL"              ,	   0x118006f000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1179},
-	{"UCTL0_EHCI_FLA"              ,	   0x118006f0000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1180},
-	{"UCTL0_ERTO_CTL"              ,	   0x118006f000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1181},
-	{"UCTL0_IF_ENA"                ,	   0x118006f000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1182},
-	{"UCTL0_INT_ENA"               ,	   0x118006f000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1183},
-	{"UCTL0_INT_REG"               ,	   0x118006f000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1184},
-	{"UCTL0_OHCI_CTL"              ,	   0x118006f000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1185},
-	{"UCTL0_ORTO_CTL"              ,	   0x118006f000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1186},
-	{"UCTL0_PPAF_WM"               ,	   0x118006f000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1187},
-	{"UCTL0_UPHY_CTL_STATUS"       ,	   0x118006f000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1188},
-	{"UCTL0_UPHY_PORT000_CTL_STATUS",	   0x118006f000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1189},
-	{"UCTL0_UPHY_PORT001_CTL_STATUS",	   0x118006f000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1189},
-	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1190},
-	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1191},
-	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1192},
-	{"ZIP_CONSTANTS"               ,	   0x11800380000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1193},
-	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1194},
-	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1195},
-	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1196},
-	{"ZIP_THROTTLE"                ,	   0x1180038000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1197},
+	{"PIP_STAT10_PRT0"             ,	   0x11800a0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT10_PRT1"             ,	   0x11800a0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT10_PRT2"             ,	   0x11800a00014a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT10_PRT3"             ,	   0x11800a00014b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT10_PRT32"            ,	   0x11800a0001680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT10_PRT33"            ,	   0x11800a0001690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT10_PRT34"            ,	   0x11800a00016a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT10_PRT35"            ,	   0x11800a00016b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT10_PRT36"            ,	   0x11800a00016c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT10_PRT37"            ,	   0x11800a00016d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT10_PRT38"            ,	   0x11800a00016e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT10_PRT39"            ,	   0x11800a00016f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT11_PRT0"             ,	   0x11800a0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT11_PRT1"             ,	   0x11800a0001498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT11_PRT2"             ,	   0x11800a00014a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT11_PRT3"             ,	   0x11800a00014b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT11_PRT32"            ,	   0x11800a0001688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT11_PRT33"            ,	   0x11800a0001698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT11_PRT34"            ,	   0x11800a00016a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT11_PRT35"            ,	   0x11800a00016b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT11_PRT36"            ,	   0x11800a00016c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT11_PRT37"            ,	   0x11800a00016d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT11_PRT38"            ,	   0x11800a00016e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT11_PRT39"            ,	   0x11800a00016f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT1_PRT3"              ,	   0x11800a00008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT1_PRT32"             ,	   0x11800a0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT1_PRT33"             ,	   0x11800a0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT1_PRT34"             ,	   0x11800a00012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT1_PRT35"             ,	   0x11800a00012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT1_PRT36"             ,	   0x11800a0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT1_PRT37"             ,	   0x11800a0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT1_PRT38"             ,	   0x11800a00013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT1_PRT39"             ,	   0x11800a0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT2_PRT3"              ,	   0x11800a0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT2_PRT32"             ,	   0x11800a0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT2_PRT33"             ,	   0x11800a0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT2_PRT34"             ,	   0x11800a00012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT2_PRT35"             ,	   0x11800a0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT2_PRT36"             ,	   0x11800a0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT2_PRT37"             ,	   0x11800a00013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT2_PRT38"             ,	   0x11800a00013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT2_PRT39"             ,	   0x11800a0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT3_PRT3"              ,	   0x11800a0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT3_PRT32"             ,	   0x11800a0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT3_PRT33"             ,	   0x11800a0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT3_PRT34"             ,	   0x11800a00012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT3_PRT35"             ,	   0x11800a0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT3_PRT36"             ,	   0x11800a0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT3_PRT37"             ,	   0x11800a00013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT3_PRT38"             ,	   0x11800a00013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT3_PRT39"             ,	   0x11800a0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT4_PRT3"              ,	   0x11800a0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT4_PRT32"             ,	   0x11800a0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT4_PRT33"             ,	   0x11800a0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT4_PRT34"             ,	   0x11800a00012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT4_PRT35"             ,	   0x11800a0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT4_PRT36"             ,	   0x11800a0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT4_PRT37"             ,	   0x11800a00013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT4_PRT38"             ,	   0x11800a0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT4_PRT39"             ,	   0x11800a0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT5_PRT3"              ,	   0x11800a0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT5_PRT32"             ,	   0x11800a0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT5_PRT33"             ,	   0x11800a0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT5_PRT34"             ,	   0x11800a00012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT5_PRT35"             ,	   0x11800a0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT5_PRT36"             ,	   0x11800a0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT5_PRT37"             ,	   0x11800a00013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT5_PRT38"             ,	   0x11800a0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT5_PRT39"             ,	   0x11800a0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT6_PRT3"              ,	   0x11800a0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT6_PRT32"             ,	   0x11800a0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT6_PRT33"             ,	   0x11800a0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT6_PRT34"             ,	   0x11800a00012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT6_PRT35"             ,	   0x11800a0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT6_PRT36"             ,	   0x11800a0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT6_PRT37"             ,	   0x11800a00013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT6_PRT38"             ,	   0x11800a0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT6_PRT39"             ,	   0x11800a0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT7_PRT3"              ,	   0x11800a0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT7_PRT32"             ,	   0x11800a0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT7_PRT33"             ,	   0x11800a0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT7_PRT34"             ,	   0x11800a00012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT7_PRT35"             ,	   0x11800a0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT7_PRT36"             ,	   0x11800a0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT7_PRT37"             ,	   0x11800a00013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT7_PRT38"             ,	   0x11800a0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT7_PRT39"             ,	   0x11800a0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PIP_STAT8_PRT3"              ,	   0x11800a0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PIP_STAT8_PRT32"             ,	   0x11800a0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PIP_STAT8_PRT33"             ,	   0x11800a0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PIP_STAT8_PRT34"             ,	   0x11800a00012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PIP_STAT8_PRT35"             ,	   0x11800a0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PIP_STAT8_PRT36"             ,	   0x11800a0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PIP_STAT8_PRT37"             ,	   0x11800a00013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PIP_STAT8_PRT38"             ,	   0x11800a0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PIP_STAT8_PRT39"             ,	   0x11800a0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT9_PRT3"              ,	   0x11800a0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT9_PRT32"             ,	   0x11800a0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT9_PRT33"             ,	   0x11800a0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT9_PRT34"             ,	   0x11800a00012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT9_PRT35"             ,	   0x11800a0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT9_PRT36"             ,	   0x11800a0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT9_PRT37"             ,	   0x11800a00013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT9_PRT38"             ,	   0x11800a0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT9_PRT39"             ,	   0x11800a0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800a0001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800a0001e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800a0001e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800a0001e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800a0001e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_ERRS36"         ,	   0x11800a0001e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_ERRS37"         ,	   0x11800a0001eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_ERRS38"         ,	   0x11800a0001ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_ERRS39"         ,	   0x11800a0001ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_ERRS40"         ,	   0x11800a0001f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_ERRS41"         ,	   0x11800a0001f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_ERRS42"         ,	   0x11800a0001f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_ERRS43"         ,	   0x11800a0001f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800a0001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800a0001e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800a0001e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800a0001e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800a0001e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_STAT_INB_OCTS36"         ,	   0x11800a0001e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_STAT_INB_OCTS37"         ,	   0x11800a0001ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_STAT_INB_OCTS38"         ,	   0x11800a0001ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_STAT_INB_OCTS39"         ,	   0x11800a0001ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_STAT_INB_OCTS40"         ,	   0x11800a0001f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_STAT_INB_OCTS41"         ,	   0x11800a0001f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_STAT_INB_OCTS42"         ,	   0x11800a0001f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_STAT_INB_OCTS43"         ,	   0x11800a0001f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800a0001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800a0001e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800a0001e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800a0001e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800a0001e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_STAT_INB_PKTS36"         ,	   0x11800a0001e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_STAT_INB_PKTS37"         ,	   0x11800a0001ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_STAT_INB_PKTS38"         ,	   0x11800a0001ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_STAT_INB_PKTS39"         ,	   0x11800a0001ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_STAT_INB_PKTS40"         ,	   0x11800a0001f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_STAT_INB_PKTS41"         ,	   0x11800a0001f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_STAT_INB_PKTS42"         ,	   0x11800a0001f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_STAT_INB_PKTS43"         ,	   0x11800a0001f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PIP_XSTAT0_PRT40"            ,	   0x11800a0002000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PIP_XSTAT0_PRT41"            ,	   0x11800a0002050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PIP_XSTAT0_PRT42"            ,	   0x11800a00020a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PIP_XSTAT0_PRT43"            ,	   0x11800a00020f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PIP_XSTAT10_PRT40"           ,	   0x11800a0001700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PIP_XSTAT10_PRT41"           ,	   0x11800a0001710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PIP_XSTAT10_PRT42"           ,	   0x11800a0001720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PIP_XSTAT10_PRT43"           ,	   0x11800a0001730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PIP_XSTAT11_PRT40"           ,	   0x11800a0001708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PIP_XSTAT11_PRT41"           ,	   0x11800a0001718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PIP_XSTAT11_PRT42"           ,	   0x11800a0001728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PIP_XSTAT11_PRT43"           ,	   0x11800a0001738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PIP_XSTAT1_PRT40"            ,	   0x11800a0002008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"PIP_XSTAT1_PRT41"            ,	   0x11800a0002058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"PIP_XSTAT1_PRT42"            ,	   0x11800a00020a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"PIP_XSTAT1_PRT43"            ,	   0x11800a00020f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"PIP_XSTAT2_PRT40"            ,	   0x11800a0002010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"PIP_XSTAT2_PRT41"            ,	   0x11800a0002060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"PIP_XSTAT2_PRT42"            ,	   0x11800a00020b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"PIP_XSTAT2_PRT43"            ,	   0x11800a0002100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"PIP_XSTAT3_PRT40"            ,	   0x11800a0002018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"PIP_XSTAT3_PRT41"            ,	   0x11800a0002068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"PIP_XSTAT3_PRT42"            ,	   0x11800a00020b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"PIP_XSTAT3_PRT43"            ,	   0x11800a0002108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"PIP_XSTAT4_PRT40"            ,	   0x11800a0002020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"PIP_XSTAT4_PRT41"            ,	   0x11800a0002070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"PIP_XSTAT4_PRT42"            ,	   0x11800a00020c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"PIP_XSTAT4_PRT43"            ,	   0x11800a0002110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"PIP_XSTAT5_PRT40"            ,	   0x11800a0002028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"PIP_XSTAT5_PRT41"            ,	   0x11800a0002078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"PIP_XSTAT5_PRT42"            ,	   0x11800a00020c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"PIP_XSTAT5_PRT43"            ,	   0x11800a0002118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"PIP_XSTAT6_PRT40"            ,	   0x11800a0002030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
+	{"PIP_XSTAT6_PRT41"            ,	   0x11800a0002080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
+	{"PIP_XSTAT6_PRT42"            ,	   0x11800a00020d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
+	{"PIP_XSTAT6_PRT43"            ,	   0x11800a0002120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
+	{"PIP_XSTAT7_PRT40"            ,	   0x11800a0002038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"PIP_XSTAT7_PRT41"            ,	   0x11800a0002088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"PIP_XSTAT7_PRT42"            ,	   0x11800a00020d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"PIP_XSTAT7_PRT43"            ,	   0x11800a0002128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"PIP_XSTAT8_PRT40"            ,	   0x11800a0002040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"PIP_XSTAT8_PRT41"            ,	   0x11800a0002090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"PIP_XSTAT8_PRT42"            ,	   0x11800a00020e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"PIP_XSTAT8_PRT43"            ,	   0x11800a0002130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"PIP_XSTAT9_PRT40"            ,	   0x11800a0002048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
+	{"PIP_XSTAT9_PRT41"            ,	   0x11800a0002098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
+	{"PIP_XSTAT9_PRT42"            ,	   0x11800a00020e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
+	{"PIP_XSTAT9_PRT43"            ,	   0x11800a0002138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	817},
+	{"PKO_MEM_DEBUG14"             ,	   0x1180050001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	819},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	820},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	821},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	822},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	823},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PKO_MEM_PORT_PTRS"           ,	   0x1180050001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PKO_MEM_PORT_QOS"            ,	   0x1180050001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PKO_MEM_PORT_RATE0"          ,	   0x1180050001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PKO_MEM_PORT_RATE1"          ,	   0x1180050001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"PKO_REG_PREEMPT"             ,	   0x1180050000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PKO_REG_QUEUE_PREEMPT"       ,	   0x1180050000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"PKO_REG_TIMESTAMP"           ,	   0x1180050000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	852},
+	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
+	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
+	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	855},
+	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	855},
+	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	855},
+	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	855},
+	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	855},
+	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	855},
+	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	855},
+	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	855},
+	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_IQ_INT"                  ,	   0x1670000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
+	{"POW_IQ_INT_EN"               ,	   0x1670000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_IQ_THR0"                 ,	   0x16700000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_IQ_THR1"                 ,	   0x16700000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_IQ_THR2"                 ,	   0x16700000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_IQ_THR3"                 ,	   0x16700000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_IQ_THR4"                 ,	   0x16700000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_IQ_THR5"                 ,	   0x16700000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_IQ_THR6"                 ,	   0x16700000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_IQ_THR7"                 ,	   0x16700000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	860},
+	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	861},
+	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	863},
+	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	863},
+	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	863},
+	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	863},
+	{"POW_PP_GRP_MSK4"             ,	   0x1670000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	863},
+	{"POW_PP_GRP_MSK5"             ,	   0x1670000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	863},
+	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
+	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
+	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	868},
+	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	868},
+	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	868},
+	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	868},
+	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	868},
+	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	868},
+	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	868},
+	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	868},
+	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	869},
+	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	870},
+	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	870},
+	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	870},
+	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	870},
+	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	870},
+	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	870},
+	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	870},
+	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	870},
+	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	870},
+	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	870},
+	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	870},
+	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	870},
+	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	870},
+	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	870},
+	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	870},
+	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	870},
+	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	871},
+	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	872},
+	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	872},
+	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	872},
+	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	872},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	872},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	872},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	872},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	872},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	872},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	872},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	872},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	872},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	872},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	872},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	872},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	872},
+	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	873},
+	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	873},
+	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	873},
+	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	873},
+	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	873},
+	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	873},
+	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	873},
+	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	873},
+	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	873},
+	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	873},
+	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	873},
+	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	873},
+	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	873},
+	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	873},
+	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	873},
+	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	873},
+	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	874},
+	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	875},
+	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	876},
+	{"RAD_REG_BIST_RESULT"         ,	   0x1180070000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	877},
+	{"RAD_REG_CMD_BUF"             ,	   0x1180070000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	878},
+	{"RAD_REG_CTL"                 ,	   0x1180070000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
+	{"RAD_REG_DEBUG0"              ,	   0x1180070000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
+	{"RAD_REG_DEBUG1"              ,	   0x1180070000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
+	{"RAD_REG_DEBUG10"             ,	   0x1180070000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
+	{"RAD_REG_DEBUG11"             ,	   0x1180070000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
+	{"RAD_REG_DEBUG12"             ,	   0x1180070000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
+	{"RAD_REG_DEBUG2"              ,	   0x1180070000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
+	{"RAD_REG_DEBUG3"              ,	   0x1180070000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	886},
+	{"RAD_REG_DEBUG4"              ,	   0x1180070000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	887},
+	{"RAD_REG_DEBUG5"              ,	   0x1180070000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	888},
+	{"RAD_REG_DEBUG6"              ,	   0x1180070000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	889},
+	{"RAD_REG_DEBUG7"              ,	   0x1180070000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	890},
+	{"RAD_REG_DEBUG8"              ,	   0x1180070000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	891},
+	{"RAD_REG_DEBUG9"              ,	   0x1180070000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	892},
+	{"RAD_REG_ERROR"               ,	   0x1180070000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	893},
+	{"RAD_REG_INT_MASK"            ,	   0x1180070000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	894},
+	{"RAD_REG_POLYNOMIAL"          ,	   0x1180070000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	895},
+	{"RAD_REG_READ_IDX"            ,	   0x1180070000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	896},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	898},
+	{"RNM_EER_DBG"                 ,	   0x1180040000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	899},
+	{"RNM_EER_KEY"                 ,	   0x1180040000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	900},
+	{"RNM_SERIAL_NUM"              ,	   0x1180040000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	901},
+	{"SLI_BIST_STATUS"             ,	   0x11f0000010580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	902},
+	{"SLI_CTL_PORT0"               ,	   0x11f0000010050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_CTL_PORT1"               ,	   0x11f0000010060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_CTL_STATUS"              ,	   0x11f0000010570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	904},
+	{"SLI_DATA_OUT_CNT"            ,	   0x11f00000105f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	905},
+	{"SLI_DBG_DATA"                ,	   0x11f0000010310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	906},
+	{"SLI_DBG_SELECT"              ,	   0x11f0000010300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	907},
+	{"SLI_DMA0_CNT"                ,	   0x11f0000010400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	908},
+	{"SLI_DMA1_CNT"                ,	   0x11f0000010410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	908},
+	{"SLI_DMA0_INT_LEVEL"          ,	   0x11f00000103e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_DMA1_INT_LEVEL"          ,	   0x11f00000103f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_DMA0_TIM"                ,	   0x11f0000010420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	910},
+	{"SLI_DMA1_TIM"                ,	   0x11f0000010430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	910},
+	{"SLI_INT_ENB_CIU"             ,	   0x11f0000013cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	911},
+	{"SLI_INT_ENB_PORT0"           ,	   0x11f0000010340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	912},
+	{"SLI_INT_ENB_PORT1"           ,	   0x11f0000010350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	912},
+	{"SLI_INT_SUM"                 ,	   0x11f0000010330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_LAST_WIN_RDATA0"         ,	   0x11f0000010600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	914},
+	{"SLI_LAST_WIN_RDATA1"         ,	   0x11f0000010610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	915},
+	{"SLI_MAC_CREDIT_CNT"          ,	   0x11f0000013d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	916},
+	{"SLI_MAC_NUMBER"              ,	            0x3e00ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	917},
+	{"SLI_MEM_ACCESS_CTL"          ,	   0x11f00000102f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	918},
+	{"SLI_MEM_ACCESS_SUBID12"      ,	   0x11f00000100e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MEM_ACCESS_SUBID13"      ,	   0x11f00000100f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MEM_ACCESS_SUBID14"      ,	   0x11f0000010100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MEM_ACCESS_SUBID15"      ,	   0x11f0000010110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MEM_ACCESS_SUBID16"      ,	   0x11f0000010120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MEM_ACCESS_SUBID17"      ,	   0x11f0000010130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MEM_ACCESS_SUBID18"      ,	   0x11f0000010140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MEM_ACCESS_SUBID19"      ,	   0x11f0000010150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MEM_ACCESS_SUBID20"      ,	   0x11f0000010160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MEM_ACCESS_SUBID21"      ,	   0x11f0000010170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MEM_ACCESS_SUBID22"      ,	   0x11f0000010180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MEM_ACCESS_SUBID23"      ,	   0x11f0000010190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MEM_ACCESS_SUBID24"      ,	   0x11f00000101a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MEM_ACCESS_SUBID25"      ,	   0x11f00000101b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MEM_ACCESS_SUBID26"      ,	   0x11f00000101c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MEM_ACCESS_SUBID27"      ,	   0x11f00000101d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MSI_ENB0"                ,	   0x11f0000013c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	920},
+	{"SLI_MSI_ENB1"                ,	   0x11f0000013c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	921},
+	{"SLI_MSI_ENB2"                ,	   0x11f0000013c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	922},
+	{"SLI_MSI_ENB3"                ,	   0x11f0000013c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	923},
+	{"SLI_MSI_RCV0"                ,	   0x11f0000013c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	924},
+	{"SLI_MSI_RCV1"                ,	   0x11f0000013c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	925},
+	{"SLI_MSI_RCV2"                ,	   0x11f0000013c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_MSI_RCV3"                ,	   0x11f0000013c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_MSI_RD_MAP"              ,	   0x11f0000013ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_MSI_W1C_ENB0"            ,	   0x11f0000013cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_MSI_W1C_ENB1"            ,	   0x11f0000013d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_MSI_W1C_ENB2"            ,	   0x11f0000013d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_MSI_W1C_ENB3"            ,	   0x11f0000013d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_MSI_W1S_ENB0"            ,	   0x11f0000013d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_MSI_W1S_ENB1"            ,	   0x11f0000013d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_MSI_W1S_ENB2"            ,	   0x11f0000013d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_MSI_W1S_ENB3"            ,	   0x11f0000013d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_MSI_WR_MAP"              ,	   0x11f0000013c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PCIE_MSI_RCV"            ,	   0x11f0000013cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PCIE_MSI_RCV_B1"         ,	   0x11f0000010650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PCIE_MSI_RCV_B2"         ,	   0x11f0000010660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PCIE_MSI_RCV_B3"         ,	   0x11f0000010670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT0_CNTS"               ,	   0x11f0000012400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT1_CNTS"               ,	   0x11f0000012410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT2_CNTS"               ,	   0x11f0000012420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT3_CNTS"               ,	   0x11f0000012430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT4_CNTS"               ,	   0x11f0000012440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT5_CNTS"               ,	   0x11f0000012450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT6_CNTS"               ,	   0x11f0000012460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT7_CNTS"               ,	   0x11f0000012470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT8_CNTS"               ,	   0x11f0000012480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT9_CNTS"               ,	   0x11f0000012490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT10_CNTS"              ,	   0x11f00000124a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT11_CNTS"              ,	   0x11f00000124b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT12_CNTS"              ,	   0x11f00000124c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT13_CNTS"              ,	   0x11f00000124d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT14_CNTS"              ,	   0x11f00000124e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT15_CNTS"              ,	   0x11f00000124f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT16_CNTS"              ,	   0x11f0000012500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT17_CNTS"              ,	   0x11f0000012510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT18_CNTS"              ,	   0x11f0000012520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT19_CNTS"              ,	   0x11f0000012530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT20_CNTS"              ,	   0x11f0000012540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT21_CNTS"              ,	   0x11f0000012550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT22_CNTS"              ,	   0x11f0000012560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT23_CNTS"              ,	   0x11f0000012570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT24_CNTS"              ,	   0x11f0000012580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT25_CNTS"              ,	   0x11f0000012590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT26_CNTS"              ,	   0x11f00000125a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT27_CNTS"              ,	   0x11f00000125b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT28_CNTS"              ,	   0x11f00000125c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT29_CNTS"              ,	   0x11f00000125d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT30_CNTS"              ,	   0x11f00000125e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT31_CNTS"              ,	   0x11f00000125f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT0_IN_BP"              ,	   0x11f0000013800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT1_IN_BP"              ,	   0x11f0000013810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT2_IN_BP"              ,	   0x11f0000013820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT3_IN_BP"              ,	   0x11f0000013830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT4_IN_BP"              ,	   0x11f0000013840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT5_IN_BP"              ,	   0x11f0000013850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT6_IN_BP"              ,	   0x11f0000013860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT7_IN_BP"              ,	   0x11f0000013870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT8_IN_BP"              ,	   0x11f0000013880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT9_IN_BP"              ,	   0x11f0000013890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT10_IN_BP"             ,	   0x11f00000138a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT11_IN_BP"             ,	   0x11f00000138b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT12_IN_BP"             ,	   0x11f00000138c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT13_IN_BP"             ,	   0x11f00000138d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT14_IN_BP"             ,	   0x11f00000138e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT15_IN_BP"             ,	   0x11f00000138f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT16_IN_BP"             ,	   0x11f0000013900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT17_IN_BP"             ,	   0x11f0000013910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT18_IN_BP"             ,	   0x11f0000013920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT19_IN_BP"             ,	   0x11f0000013930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT20_IN_BP"             ,	   0x11f0000013940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT21_IN_BP"             ,	   0x11f0000013950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT22_IN_BP"             ,	   0x11f0000013960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT23_IN_BP"             ,	   0x11f0000013970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT24_IN_BP"             ,	   0x11f0000013980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT25_IN_BP"             ,	   0x11f0000013990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT26_IN_BP"             ,	   0x11f00000139a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT27_IN_BP"             ,	   0x11f00000139b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT28_IN_BP"             ,	   0x11f00000139c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT29_IN_BP"             ,	   0x11f00000139d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT30_IN_BP"             ,	   0x11f00000139e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT31_IN_BP"             ,	   0x11f00000139f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT0_INSTR_BADDR"        ,	   0x11f0000012800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT1_INSTR_BADDR"        ,	   0x11f0000012810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT2_INSTR_BADDR"        ,	   0x11f0000012820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT3_INSTR_BADDR"        ,	   0x11f0000012830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT4_INSTR_BADDR"        ,	   0x11f0000012840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT5_INSTR_BADDR"        ,	   0x11f0000012850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT6_INSTR_BADDR"        ,	   0x11f0000012860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT7_INSTR_BADDR"        ,	   0x11f0000012870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT8_INSTR_BADDR"        ,	   0x11f0000012880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT9_INSTR_BADDR"        ,	   0x11f0000012890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT10_INSTR_BADDR"       ,	   0x11f00000128a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT11_INSTR_BADDR"       ,	   0x11f00000128b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT12_INSTR_BADDR"       ,	   0x11f00000128c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT13_INSTR_BADDR"       ,	   0x11f00000128d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT14_INSTR_BADDR"       ,	   0x11f00000128e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT15_INSTR_BADDR"       ,	   0x11f00000128f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT16_INSTR_BADDR"       ,	   0x11f0000012900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT17_INSTR_BADDR"       ,	   0x11f0000012910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT18_INSTR_BADDR"       ,	   0x11f0000012920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT19_INSTR_BADDR"       ,	   0x11f0000012930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT20_INSTR_BADDR"       ,	   0x11f0000012940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT21_INSTR_BADDR"       ,	   0x11f0000012950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT22_INSTR_BADDR"       ,	   0x11f0000012960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT23_INSTR_BADDR"       ,	   0x11f0000012970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT24_INSTR_BADDR"       ,	   0x11f0000012980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT25_INSTR_BADDR"       ,	   0x11f0000012990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT26_INSTR_BADDR"       ,	   0x11f00000129a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT27_INSTR_BADDR"       ,	   0x11f00000129b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT28_INSTR_BADDR"       ,	   0x11f00000129c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT29_INSTR_BADDR"       ,	   0x11f00000129d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT30_INSTR_BADDR"       ,	   0x11f00000129e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT31_INSTR_BADDR"       ,	   0x11f00000129f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT0_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT1_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT2_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT3_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT4_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT5_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT6_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT7_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT8_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT9_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT10_INSTR_BAOFF_DBELL" ,	   0x11f0000012ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT11_INSTR_BAOFF_DBELL" ,	   0x11f0000012cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT12_INSTR_BAOFF_DBELL" ,	   0x11f0000012cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT13_INSTR_BAOFF_DBELL" ,	   0x11f0000012cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT14_INSTR_BAOFF_DBELL" ,	   0x11f0000012ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT15_INSTR_BAOFF_DBELL" ,	   0x11f0000012cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT16_INSTR_BAOFF_DBELL" ,	   0x11f0000012d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT17_INSTR_BAOFF_DBELL" ,	   0x11f0000012d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT18_INSTR_BAOFF_DBELL" ,	   0x11f0000012d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT19_INSTR_BAOFF_DBELL" ,	   0x11f0000012d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT20_INSTR_BAOFF_DBELL" ,	   0x11f0000012d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT21_INSTR_BAOFF_DBELL" ,	   0x11f0000012d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT22_INSTR_BAOFF_DBELL" ,	   0x11f0000012d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT23_INSTR_BAOFF_DBELL" ,	   0x11f0000012d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT24_INSTR_BAOFF_DBELL" ,	   0x11f0000012d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT25_INSTR_BAOFF_DBELL" ,	   0x11f0000012d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT26_INSTR_BAOFF_DBELL" ,	   0x11f0000012da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT27_INSTR_BAOFF_DBELL" ,	   0x11f0000012db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT28_INSTR_BAOFF_DBELL" ,	   0x11f0000012dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT29_INSTR_BAOFF_DBELL" ,	   0x11f0000012dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT30_INSTR_BAOFF_DBELL" ,	   0x11f0000012de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT31_INSTR_BAOFF_DBELL" ,	   0x11f0000012df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT0_INSTR_FIFO_RSIZE"   ,	   0x11f0000013000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT1_INSTR_FIFO_RSIZE"   ,	   0x11f0000013010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT2_INSTR_FIFO_RSIZE"   ,	   0x11f0000013020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT3_INSTR_FIFO_RSIZE"   ,	   0x11f0000013030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT4_INSTR_FIFO_RSIZE"   ,	   0x11f0000013040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT5_INSTR_FIFO_RSIZE"   ,	   0x11f0000013050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT6_INSTR_FIFO_RSIZE"   ,	   0x11f0000013060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT7_INSTR_FIFO_RSIZE"   ,	   0x11f0000013070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT8_INSTR_FIFO_RSIZE"   ,	   0x11f0000013080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT9_INSTR_FIFO_RSIZE"   ,	   0x11f0000013090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT10_INSTR_FIFO_RSIZE"  ,	   0x11f00000130a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT11_INSTR_FIFO_RSIZE"  ,	   0x11f00000130b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT12_INSTR_FIFO_RSIZE"  ,	   0x11f00000130c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT13_INSTR_FIFO_RSIZE"  ,	   0x11f00000130d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT14_INSTR_FIFO_RSIZE"  ,	   0x11f00000130e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT15_INSTR_FIFO_RSIZE"  ,	   0x11f00000130f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT16_INSTR_FIFO_RSIZE"  ,	   0x11f0000013100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT17_INSTR_FIFO_RSIZE"  ,	   0x11f0000013110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT18_INSTR_FIFO_RSIZE"  ,	   0x11f0000013120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT19_INSTR_FIFO_RSIZE"  ,	   0x11f0000013130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT20_INSTR_FIFO_RSIZE"  ,	   0x11f0000013140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT21_INSTR_FIFO_RSIZE"  ,	   0x11f0000013150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT22_INSTR_FIFO_RSIZE"  ,	   0x11f0000013160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT23_INSTR_FIFO_RSIZE"  ,	   0x11f0000013170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT24_INSTR_FIFO_RSIZE"  ,	   0x11f0000013180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT25_INSTR_FIFO_RSIZE"  ,	   0x11f0000013190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT26_INSTR_FIFO_RSIZE"  ,	   0x11f00000131a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT27_INSTR_FIFO_RSIZE"  ,	   0x11f00000131b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT28_INSTR_FIFO_RSIZE"  ,	   0x11f00000131c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT29_INSTR_FIFO_RSIZE"  ,	   0x11f00000131d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT30_INSTR_FIFO_RSIZE"  ,	   0x11f00000131e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT31_INSTR_FIFO_RSIZE"  ,	   0x11f00000131f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT0_INSTR_HEADER"       ,	   0x11f0000013400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT1_INSTR_HEADER"       ,	   0x11f0000013410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT2_INSTR_HEADER"       ,	   0x11f0000013420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT3_INSTR_HEADER"       ,	   0x11f0000013430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT4_INSTR_HEADER"       ,	   0x11f0000013440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT5_INSTR_HEADER"       ,	   0x11f0000013450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT6_INSTR_HEADER"       ,	   0x11f0000013460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT7_INSTR_HEADER"       ,	   0x11f0000013470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT8_INSTR_HEADER"       ,	   0x11f0000013480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT9_INSTR_HEADER"       ,	   0x11f0000013490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT10_INSTR_HEADER"      ,	   0x11f00000134a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT11_INSTR_HEADER"      ,	   0x11f00000134b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT12_INSTR_HEADER"      ,	   0x11f00000134c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT13_INSTR_HEADER"      ,	   0x11f00000134d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT14_INSTR_HEADER"      ,	   0x11f00000134e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT15_INSTR_HEADER"      ,	   0x11f00000134f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT16_INSTR_HEADER"      ,	   0x11f0000013500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT17_INSTR_HEADER"      ,	   0x11f0000013510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT18_INSTR_HEADER"      ,	   0x11f0000013520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT19_INSTR_HEADER"      ,	   0x11f0000013530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT20_INSTR_HEADER"      ,	   0x11f0000013540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT21_INSTR_HEADER"      ,	   0x11f0000013550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT22_INSTR_HEADER"      ,	   0x11f0000013560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT23_INSTR_HEADER"      ,	   0x11f0000013570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT24_INSTR_HEADER"      ,	   0x11f0000013580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT25_INSTR_HEADER"      ,	   0x11f0000013590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT26_INSTR_HEADER"      ,	   0x11f00000135a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT27_INSTR_HEADER"      ,	   0x11f00000135b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT28_INSTR_HEADER"      ,	   0x11f00000135c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT29_INSTR_HEADER"      ,	   0x11f00000135d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT30_INSTR_HEADER"      ,	   0x11f00000135e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT31_INSTR_HEADER"      ,	   0x11f00000135f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT0_OUT_SIZE"           ,	   0x11f0000010c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT1_OUT_SIZE"           ,	   0x11f0000010c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT2_OUT_SIZE"           ,	   0x11f0000010c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT3_OUT_SIZE"           ,	   0x11f0000010c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT4_OUT_SIZE"           ,	   0x11f0000010c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT5_OUT_SIZE"           ,	   0x11f0000010c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT6_OUT_SIZE"           ,	   0x11f0000010c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT7_OUT_SIZE"           ,	   0x11f0000010c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT8_OUT_SIZE"           ,	   0x11f0000010c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT9_OUT_SIZE"           ,	   0x11f0000010c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT10_OUT_SIZE"          ,	   0x11f0000010ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT11_OUT_SIZE"          ,	   0x11f0000010cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT12_OUT_SIZE"          ,	   0x11f0000010cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT13_OUT_SIZE"          ,	   0x11f0000010cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT14_OUT_SIZE"          ,	   0x11f0000010ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT15_OUT_SIZE"          ,	   0x11f0000010cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT16_OUT_SIZE"          ,	   0x11f0000010d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT17_OUT_SIZE"          ,	   0x11f0000010d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT18_OUT_SIZE"          ,	   0x11f0000010d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT19_OUT_SIZE"          ,	   0x11f0000010d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT20_OUT_SIZE"          ,	   0x11f0000010d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT21_OUT_SIZE"          ,	   0x11f0000010d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT22_OUT_SIZE"          ,	   0x11f0000010d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT23_OUT_SIZE"          ,	   0x11f0000010d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT24_OUT_SIZE"          ,	   0x11f0000010d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT25_OUT_SIZE"          ,	   0x11f0000010d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT26_OUT_SIZE"          ,	   0x11f0000010da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT27_OUT_SIZE"          ,	   0x11f0000010db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT28_OUT_SIZE"          ,	   0x11f0000010dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT29_OUT_SIZE"          ,	   0x11f0000010dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT30_OUT_SIZE"          ,	   0x11f0000010de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT31_OUT_SIZE"          ,	   0x11f0000010df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT0_SLIST_BADDR"        ,	   0x11f0000011400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT1_SLIST_BADDR"        ,	   0x11f0000011410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT2_SLIST_BADDR"        ,	   0x11f0000011420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT3_SLIST_BADDR"        ,	   0x11f0000011430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT4_SLIST_BADDR"        ,	   0x11f0000011440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT5_SLIST_BADDR"        ,	   0x11f0000011450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT6_SLIST_BADDR"        ,	   0x11f0000011460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT7_SLIST_BADDR"        ,	   0x11f0000011470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT8_SLIST_BADDR"        ,	   0x11f0000011480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT9_SLIST_BADDR"        ,	   0x11f0000011490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT10_SLIST_BADDR"       ,	   0x11f00000114a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT11_SLIST_BADDR"       ,	   0x11f00000114b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT12_SLIST_BADDR"       ,	   0x11f00000114c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT13_SLIST_BADDR"       ,	   0x11f00000114d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT14_SLIST_BADDR"       ,	   0x11f00000114e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT15_SLIST_BADDR"       ,	   0x11f00000114f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT16_SLIST_BADDR"       ,	   0x11f0000011500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT17_SLIST_BADDR"       ,	   0x11f0000011510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT18_SLIST_BADDR"       ,	   0x11f0000011520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT19_SLIST_BADDR"       ,	   0x11f0000011530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT20_SLIST_BADDR"       ,	   0x11f0000011540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT21_SLIST_BADDR"       ,	   0x11f0000011550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT22_SLIST_BADDR"       ,	   0x11f0000011560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT23_SLIST_BADDR"       ,	   0x11f0000011570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT24_SLIST_BADDR"       ,	   0x11f0000011580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT25_SLIST_BADDR"       ,	   0x11f0000011590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT26_SLIST_BADDR"       ,	   0x11f00000115a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT27_SLIST_BADDR"       ,	   0x11f00000115b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT28_SLIST_BADDR"       ,	   0x11f00000115c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT29_SLIST_BADDR"       ,	   0x11f00000115d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT30_SLIST_BADDR"       ,	   0x11f00000115e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT31_SLIST_BADDR"       ,	   0x11f00000115f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT0_SLIST_BAOFF_DBELL"  ,	   0x11f0000011800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT1_SLIST_BAOFF_DBELL"  ,	   0x11f0000011810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT2_SLIST_BAOFF_DBELL"  ,	   0x11f0000011820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT3_SLIST_BAOFF_DBELL"  ,	   0x11f0000011830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT4_SLIST_BAOFF_DBELL"  ,	   0x11f0000011840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT5_SLIST_BAOFF_DBELL"  ,	   0x11f0000011850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT6_SLIST_BAOFF_DBELL"  ,	   0x11f0000011860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT7_SLIST_BAOFF_DBELL"  ,	   0x11f0000011870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT8_SLIST_BAOFF_DBELL"  ,	   0x11f0000011880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT9_SLIST_BAOFF_DBELL"  ,	   0x11f0000011890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT10_SLIST_BAOFF_DBELL" ,	   0x11f00000118a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT11_SLIST_BAOFF_DBELL" ,	   0x11f00000118b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT12_SLIST_BAOFF_DBELL" ,	   0x11f00000118c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT13_SLIST_BAOFF_DBELL" ,	   0x11f00000118d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT14_SLIST_BAOFF_DBELL" ,	   0x11f00000118e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT15_SLIST_BAOFF_DBELL" ,	   0x11f00000118f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT16_SLIST_BAOFF_DBELL" ,	   0x11f0000011900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT17_SLIST_BAOFF_DBELL" ,	   0x11f0000011910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT18_SLIST_BAOFF_DBELL" ,	   0x11f0000011920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT19_SLIST_BAOFF_DBELL" ,	   0x11f0000011930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT20_SLIST_BAOFF_DBELL" ,	   0x11f0000011940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT21_SLIST_BAOFF_DBELL" ,	   0x11f0000011950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT22_SLIST_BAOFF_DBELL" ,	   0x11f0000011960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT23_SLIST_BAOFF_DBELL" ,	   0x11f0000011970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT24_SLIST_BAOFF_DBELL" ,	   0x11f0000011980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT25_SLIST_BAOFF_DBELL" ,	   0x11f0000011990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT26_SLIST_BAOFF_DBELL" ,	   0x11f00000119a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT27_SLIST_BAOFF_DBELL" ,	   0x11f00000119b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT28_SLIST_BAOFF_DBELL" ,	   0x11f00000119c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT29_SLIST_BAOFF_DBELL" ,	   0x11f00000119d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT30_SLIST_BAOFF_DBELL" ,	   0x11f00000119e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT31_SLIST_BAOFF_DBELL" ,	   0x11f00000119f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT0_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT1_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT2_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT3_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT4_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT5_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT6_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT7_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT8_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT9_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT10_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT11_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT12_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT13_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT14_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT15_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT16_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT17_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT18_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT19_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT20_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT21_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT22_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT23_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT24_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT25_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT26_SLIST_FIFO_RSIZE"  ,	   0x11f0000011da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT27_SLIST_FIFO_RSIZE"  ,	   0x11f0000011db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT28_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT29_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT30_SLIST_FIFO_RSIZE"  ,	   0x11f0000011de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT31_SLIST_FIFO_RSIZE"  ,	   0x11f0000011df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT_CNT_INT"             ,	   0x11f0000011130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	952},
+	{"SLI_PKT_CNT_INT_ENB"         ,	   0x11f0000011150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	953},
+	{"SLI_PKT_CTL"                 ,	   0x11f0000011220ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_DATA_OUT_ES"         ,	   0x11f00000110b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	955},
+	{"SLI_PKT_DATA_OUT_NS"         ,	   0x11f00000110a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	956},
+	{"SLI_PKT_DATA_OUT_ROR"        ,	   0x11f0000011090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	957},
+	{"SLI_PKT_DPADDR"              ,	   0x11f0000011080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	958},
+	{"SLI_PKT_IN_BP"               ,	   0x11f0000011210ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	959},
+	{"SLI_PKT_IN_DONE0_CNTS"       ,	   0x11f0000012000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE1_CNTS"       ,	   0x11f0000012010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE2_CNTS"       ,	   0x11f0000012020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE3_CNTS"       ,	   0x11f0000012030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE4_CNTS"       ,	   0x11f0000012040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE5_CNTS"       ,	   0x11f0000012050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE6_CNTS"       ,	   0x11f0000012060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE7_CNTS"       ,	   0x11f0000012070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE8_CNTS"       ,	   0x11f0000012080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE9_CNTS"       ,	   0x11f0000012090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE10_CNTS"      ,	   0x11f00000120a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE11_CNTS"      ,	   0x11f00000120b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE12_CNTS"      ,	   0x11f00000120c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE13_CNTS"      ,	   0x11f00000120d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE14_CNTS"      ,	   0x11f00000120e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE15_CNTS"      ,	   0x11f00000120f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE16_CNTS"      ,	   0x11f0000012100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE17_CNTS"      ,	   0x11f0000012110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE18_CNTS"      ,	   0x11f0000012120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE19_CNTS"      ,	   0x11f0000012130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE20_CNTS"      ,	   0x11f0000012140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE21_CNTS"      ,	   0x11f0000012150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE22_CNTS"      ,	   0x11f0000012160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE23_CNTS"      ,	   0x11f0000012170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE24_CNTS"      ,	   0x11f0000012180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE25_CNTS"      ,	   0x11f0000012190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE26_CNTS"      ,	   0x11f00000121a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE27_CNTS"      ,	   0x11f00000121b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE28_CNTS"      ,	   0x11f00000121c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE29_CNTS"      ,	   0x11f00000121d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE30_CNTS"      ,	   0x11f00000121e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_DONE31_CNTS"      ,	   0x11f00000121f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_IN_INSTR_COUNTS"     ,	   0x11f0000011200ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	961},
+	{"SLI_PKT_IN_PCIE_PORT"        ,	   0x11f00000111b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	962},
+	{"SLI_PKT_INPUT_CONTROL"       ,	   0x11f0000011170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	963},
+	{"SLI_PKT_INSTR_ENB"           ,	   0x11f0000011000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	964},
+	{"SLI_PKT_INSTR_RD_SIZE"       ,	   0x11f00000111a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	965},
+	{"SLI_PKT_INSTR_SIZE"          ,	   0x11f0000011020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	966},
+	{"SLI_PKT_INT_LEVELS"          ,	   0x11f0000011120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	967},
+	{"SLI_PKT_IPTR"                ,	   0x11f0000011070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	968},
+	{"SLI_PKT_OUT_BMODE"           ,	   0x11f00000110d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_PKT_OUT_ENB"             ,	   0x11f0000011010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	970},
+	{"SLI_PKT_OUTPUT_WMARK"        ,	   0x11f0000011180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	971},
+	{"SLI_PKT_PCIE_PORT"           ,	   0x11f00000110e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	972},
+	{"SLI_PKT_PORT_IN_RST"         ,	   0x11f00000111f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	973},
+	{"SLI_PKT_SLIST_ES"            ,	   0x11f0000011050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	974},
+	{"SLI_PKT_SLIST_NS"            ,	   0x11f0000011040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	975},
+	{"SLI_PKT_SLIST_ROR"           ,	   0x11f0000011030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	976},
+	{"SLI_PKT_TIME_INT"            ,	   0x11f0000011140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_PKT_TIME_INT_ENB"        ,	   0x11f0000011160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	978},
+	{"SLI_S2M_PORT0_CTL"           ,	   0x11f0000013d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	979},
+	{"SLI_S2M_PORT1_CTL"           ,	   0x11f0000013d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	979},
+	{"SLI_SCRATCH_1"               ,	   0x11f00000103c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	980},
+	{"SLI_SCRATCH_2"               ,	   0x11f00000103d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	981},
+	{"SLI_STATE1"                  ,	   0x11f0000010620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	982},
+	{"SLI_STATE2"                  ,	   0x11f0000010630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	983},
+	{"SLI_STATE3"                  ,	   0x11f0000010640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	984},
+	{"SLI_WIN_RD_ADDR"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	985},
+	{"SLI_WIN_RD_DATA"             ,	              0x40ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	986},
+	{"SLI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	987},
+	{"SLI_WIN_WR_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	988},
+	{"SLI_WIN_WR_MASK"             ,	              0x30ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	989},
+	{"SLI_WINDOW_CTL"              ,	   0x11f00000102e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	990},
+	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	991},
+	{"SMI1_CLK"                    ,	   0x1180000001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	991},
+	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	992},
+	{"SMI1_CMD"                    ,	   0x1180000001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	992},
+	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	993},
+	{"SMI1_EN"                     ,	   0x1180000001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	993},
+	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SMI1_RD_DAT"                 ,	   0x1180000001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SMI1_WR_DAT"                 ,	   0x1180000001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SMI_DRV_CTL"                 ,	   0x1180000001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	996},
+	{"SRIO0_ACC_CTRL"              ,	   0x11800c8000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
+	{"SRIO1_ACC_CTRL"              ,	   0x11800c9000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
+	{"SRIO0_ASMBLY_ID"             ,	   0x11800c8000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_ASMBLY_ID"             ,	   0x11800c9000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_ASMBLY_INFO"           ,	   0x11800c8000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_ASMBLY_INFO"           ,	   0x11800c9000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_BELL_RESP_CTRL"        ,	   0x11800c8000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1000},
+	{"SRIO1_BELL_RESP_CTRL"        ,	   0x11800c9000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1000},
+	{"SRIO0_BIST_STATUS"           ,	   0x11800c8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1001},
+	{"SRIO1_BIST_STATUS"           ,	   0x11800c9000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1001},
+	{"SRIO0_IMSG_CTRL"             ,	   0x11800c8000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
+	{"SRIO1_IMSG_CTRL"             ,	   0x11800c9000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
+	{"SRIO0_IMSG_INST_HDR000"      ,	   0x11800c8000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
+	{"SRIO0_IMSG_INST_HDR001"      ,	   0x11800c8000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
+	{"SRIO1_IMSG_INST_HDR000"      ,	   0x11800c9000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
+	{"SRIO1_IMSG_INST_HDR001"      ,	   0x11800c9000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
+	{"SRIO0_IMSG_QOS_GRP000"       ,	   0x11800c8000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP001"       ,	   0x11800c8000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP002"       ,	   0x11800c8000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP003"       ,	   0x11800c8000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP004"       ,	   0x11800c8000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP005"       ,	   0x11800c8000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP006"       ,	   0x11800c8000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP007"       ,	   0x11800c8000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP008"       ,	   0x11800c8000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP009"       ,	   0x11800c8000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP010"       ,	   0x11800c8000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP011"       ,	   0x11800c8000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP012"       ,	   0x11800c8000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP013"       ,	   0x11800c8000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP014"       ,	   0x11800c8000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP015"       ,	   0x11800c8000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP016"       ,	   0x11800c8000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP017"       ,	   0x11800c8000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP018"       ,	   0x11800c8000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP019"       ,	   0x11800c8000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP020"       ,	   0x11800c80006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP021"       ,	   0x11800c80006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP022"       ,	   0x11800c80006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP023"       ,	   0x11800c80006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP024"       ,	   0x11800c80006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP025"       ,	   0x11800c80006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP026"       ,	   0x11800c80006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP027"       ,	   0x11800c80006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP028"       ,	   0x11800c80006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP029"       ,	   0x11800c80006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP030"       ,	   0x11800c80006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_QOS_GRP031"       ,	   0x11800c80006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP000"       ,	   0x11800c9000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP001"       ,	   0x11800c9000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP002"       ,	   0x11800c9000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP003"       ,	   0x11800c9000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP004"       ,	   0x11800c9000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP005"       ,	   0x11800c9000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP006"       ,	   0x11800c9000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP007"       ,	   0x11800c9000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP008"       ,	   0x11800c9000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP009"       ,	   0x11800c9000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP010"       ,	   0x11800c9000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP011"       ,	   0x11800c9000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP012"       ,	   0x11800c9000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP013"       ,	   0x11800c9000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP014"       ,	   0x11800c9000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP015"       ,	   0x11800c9000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP016"       ,	   0x11800c9000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP017"       ,	   0x11800c9000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP018"       ,	   0x11800c9000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP019"       ,	   0x11800c9000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP020"       ,	   0x11800c90006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP021"       ,	   0x11800c90006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP022"       ,	   0x11800c90006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP023"       ,	   0x11800c90006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP024"       ,	   0x11800c90006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP025"       ,	   0x11800c90006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP026"       ,	   0x11800c90006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP027"       ,	   0x11800c90006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP028"       ,	   0x11800c90006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP029"       ,	   0x11800c90006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP030"       ,	   0x11800c90006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_IMSG_QOS_GRP031"       ,	   0x11800c90006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_IMSG_STATUS000"        ,	   0x11800c8000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS001"        ,	   0x11800c8000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS002"        ,	   0x11800c8000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS003"        ,	   0x11800c8000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS004"        ,	   0x11800c8000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS005"        ,	   0x11800c8000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS006"        ,	   0x11800c8000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS007"        ,	   0x11800c8000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS008"        ,	   0x11800c8000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS009"        ,	   0x11800c8000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS010"        ,	   0x11800c8000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS011"        ,	   0x11800c8000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS012"        ,	   0x11800c8000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS013"        ,	   0x11800c8000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS014"        ,	   0x11800c8000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS015"        ,	   0x11800c8000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS016"        ,	   0x11800c8000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS017"        ,	   0x11800c8000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS018"        ,	   0x11800c8000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS019"        ,	   0x11800c8000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS020"        ,	   0x11800c80007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS021"        ,	   0x11800c80007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS022"        ,	   0x11800c80007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_STATUS023"        ,	   0x11800c80007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS000"        ,	   0x11800c9000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS001"        ,	   0x11800c9000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS002"        ,	   0x11800c9000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS003"        ,	   0x11800c9000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS004"        ,	   0x11800c9000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS005"        ,	   0x11800c9000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS006"        ,	   0x11800c9000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS007"        ,	   0x11800c9000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS008"        ,	   0x11800c9000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS009"        ,	   0x11800c9000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS010"        ,	   0x11800c9000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS011"        ,	   0x11800c9000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS012"        ,	   0x11800c9000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS013"        ,	   0x11800c9000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS014"        ,	   0x11800c9000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS015"        ,	   0x11800c9000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS016"        ,	   0x11800c9000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS017"        ,	   0x11800c9000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS018"        ,	   0x11800c9000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS019"        ,	   0x11800c9000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS020"        ,	   0x11800c90007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS021"        ,	   0x11800c90007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS022"        ,	   0x11800c90007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_IMSG_STATUS023"        ,	   0x11800c90007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_IMSG_VPORT_THR"        ,	   0x11800c8000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"SRIO1_IMSG_VPORT_THR"        ,	   0x11800c9000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"SRIO0_INT2_ENABLE"           ,	   0x11800c80003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"SRIO1_INT2_ENABLE"           ,	   0x11800c90003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"SRIO0_INT2_REG"              ,	   0x11800c80003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"SRIO1_INT2_REG"              ,	   0x11800c90003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"SRIO0_INT_ENABLE"            ,	   0x11800c8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1009},
+	{"SRIO1_INT_ENABLE"            ,	   0x11800c9000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1009},
+	{"SRIO0_INT_INFO0"             ,	   0x11800c8000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_INT_INFO0"             ,	   0x11800c9000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_INT_INFO1"             ,	   0x11800c8000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"SRIO1_INT_INFO1"             ,	   0x11800c9000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"SRIO0_INT_INFO2"             ,	   0x11800c8000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"SRIO1_INT_INFO2"             ,	   0x11800c9000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"SRIO0_INT_INFO3"             ,	   0x11800c8000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"SRIO1_INT_INFO3"             ,	   0x11800c9000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"SRIO0_INT_REG"               ,	   0x11800c8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"SRIO1_INT_REG"               ,	   0x11800c9000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"SRIO0_IP_FEATURE"            ,	   0x11800c80003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"SRIO1_IP_FEATURE"            ,	   0x11800c90003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"SRIO0_MAC_BUFFERS"           ,	   0x11800c8000390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_MAC_BUFFERS"           ,	   0x11800c9000390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_MAINT_OP"              ,	   0x11800c8000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"SRIO1_MAINT_OP"              ,	   0x11800c9000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"SRIO0_MAINT_RD_DATA"         ,	   0x11800c8000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"SRIO1_MAINT_RD_DATA"         ,	   0x11800c9000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"SRIO0_MCE_TX_CTL"            ,	   0x11800c8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"SRIO1_MCE_TX_CTL"            ,	   0x11800c9000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"SRIO0_MEM_OP_CTRL"           ,	   0x11800c8000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"SRIO1_MEM_OP_CTRL"           ,	   0x11800c9000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"SRIO0_OMSG_CTRL000"          ,	   0x11800c8000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"SRIO0_OMSG_CTRL001"          ,	   0x11800c80004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"SRIO1_OMSG_CTRL000"          ,	   0x11800c9000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"SRIO1_OMSG_CTRL001"          ,	   0x11800c90004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"SRIO0_OMSG_DONE_COUNTS000"   ,	   0x11800c80004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"SRIO0_OMSG_DONE_COUNTS001"   ,	   0x11800c80004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"SRIO1_OMSG_DONE_COUNTS000"   ,	   0x11800c90004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"SRIO1_OMSG_DONE_COUNTS001"   ,	   0x11800c90004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"SRIO0_OMSG_FMP_MR000"        ,	   0x11800c8000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1023},
+	{"SRIO0_OMSG_FMP_MR001"        ,	   0x11800c80004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1023},
+	{"SRIO1_OMSG_FMP_MR000"        ,	   0x11800c9000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1023},
+	{"SRIO1_OMSG_FMP_MR001"        ,	   0x11800c90004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1023},
+	{"SRIO0_OMSG_NMP_MR000"        ,	   0x11800c80004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"SRIO0_OMSG_NMP_MR001"        ,	   0x11800c80004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"SRIO1_OMSG_NMP_MR000"        ,	   0x11800c90004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"SRIO1_OMSG_NMP_MR001"        ,	   0x11800c90004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"SRIO0_OMSG_PORT000"          ,	   0x11800c8000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"SRIO0_OMSG_PORT001"          ,	   0x11800c80004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"SRIO1_OMSG_PORT000"          ,	   0x11800c9000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"SRIO1_OMSG_PORT001"          ,	   0x11800c90004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"SRIO0_OMSG_SILO_THR"         ,	   0x11800c80004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO1_OMSG_SILO_THR"         ,	   0x11800c90004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO0_OMSG_SP_MR000"         ,	   0x11800c8000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"SRIO0_OMSG_SP_MR001"         ,	   0x11800c80004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"SRIO1_OMSG_SP_MR000"         ,	   0x11800c9000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"SRIO1_OMSG_SP_MR001"         ,	   0x11800c90004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"SRIO0_PRIO000_IN_USE"        ,	   0x11800c80003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"SRIO0_PRIO001_IN_USE"        ,	   0x11800c80003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"SRIO0_PRIO002_IN_USE"        ,	   0x11800c80003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"SRIO0_PRIO003_IN_USE"        ,	   0x11800c80003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"SRIO1_PRIO000_IN_USE"        ,	   0x11800c90003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"SRIO1_PRIO001_IN_USE"        ,	   0x11800c90003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"SRIO1_PRIO002_IN_USE"        ,	   0x11800c90003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"SRIO1_PRIO003_IN_USE"        ,	   0x11800c90003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"SRIO0_RX_BELL"               ,	   0x11800c8000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1029},
+	{"SRIO1_RX_BELL"               ,	   0x11800c9000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1029},
+	{"SRIO0_RX_BELL_SEQ"           ,	   0x11800c8000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1030},
+	{"SRIO1_RX_BELL_SEQ"           ,	   0x11800c9000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1030},
+	{"SRIO0_RX_STATUS"             ,	   0x11800c8000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"SRIO1_RX_STATUS"             ,	   0x11800c9000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"SRIO0_S2M_TYPE000"           ,	   0x11800c8000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO0_S2M_TYPE001"           ,	   0x11800c8000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO0_S2M_TYPE002"           ,	   0x11800c8000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO0_S2M_TYPE003"           ,	   0x11800c8000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO0_S2M_TYPE004"           ,	   0x11800c80001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO0_S2M_TYPE005"           ,	   0x11800c80001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO0_S2M_TYPE006"           ,	   0x11800c80001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO0_S2M_TYPE007"           ,	   0x11800c80001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO0_S2M_TYPE008"           ,	   0x11800c80001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO0_S2M_TYPE009"           ,	   0x11800c80001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO0_S2M_TYPE010"           ,	   0x11800c80001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO0_S2M_TYPE011"           ,	   0x11800c80001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO0_S2M_TYPE012"           ,	   0x11800c80001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO0_S2M_TYPE013"           ,	   0x11800c80001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO0_S2M_TYPE014"           ,	   0x11800c80001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO0_S2M_TYPE015"           ,	   0x11800c80001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO1_S2M_TYPE000"           ,	   0x11800c9000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO1_S2M_TYPE001"           ,	   0x11800c9000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO1_S2M_TYPE002"           ,	   0x11800c9000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO1_S2M_TYPE003"           ,	   0x11800c9000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO1_S2M_TYPE004"           ,	   0x11800c90001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO1_S2M_TYPE005"           ,	   0x11800c90001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO1_S2M_TYPE006"           ,	   0x11800c90001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO1_S2M_TYPE007"           ,	   0x11800c90001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO1_S2M_TYPE008"           ,	   0x11800c90001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO1_S2M_TYPE009"           ,	   0x11800c90001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO1_S2M_TYPE010"           ,	   0x11800c90001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO1_S2M_TYPE011"           ,	   0x11800c90001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO1_S2M_TYPE012"           ,	   0x11800c90001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO1_S2M_TYPE013"           ,	   0x11800c90001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO1_S2M_TYPE014"           ,	   0x11800c90001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO1_S2M_TYPE015"           ,	   0x11800c90001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO0_SEQ"                   ,	   0x11800c8000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"SRIO1_SEQ"                   ,	   0x11800c9000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"SRIO0_STATUS_REG"            ,	   0x11800c8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"SRIO1_STATUS_REG"            ,	   0x11800c9000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"SRIO0_TAG_CTRL"              ,	   0x11800c8000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"SRIO1_TAG_CTRL"              ,	   0x11800c9000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"SRIO0_TLP_CREDITS"           ,	   0x11800c8000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"SRIO1_TLP_CREDITS"           ,	   0x11800c9000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"SRIO0_TX_BELL"               ,	   0x11800c8000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"SRIO1_TX_BELL"               ,	   0x11800c9000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"SRIO0_TX_BELL_INFO"          ,	   0x11800c8000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"SRIO1_TX_BELL_INFO"          ,	   0x11800c9000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"SRIO0_TX_CTRL"               ,	   0x11800c8000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"SRIO1_TX_CTRL"               ,	   0x11800c9000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"SRIO0_TX_EMPHASIS"           ,	   0x11800c80003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"SRIO1_TX_EMPHASIS"           ,	   0x11800c90003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"SRIO0_TX_STATUS"             ,	   0x11800c8000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"SRIO1_TX_STATUS"             ,	   0x11800c9000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"SRIO0_WR_DONE_COUNTS"        ,	   0x11800c8000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"SRIO1_WR_DONE_COUNTS"        ,	   0x11800c9000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"SRIOMAINT0_ASMBLY_ID"        ,	               0x8ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1043},
+	{"SRIOMAINT1_ASMBLY_ID"        ,	               0x8ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1043},
+	{"SRIOMAINT0_ASMBLY_INFO"      ,	               0xcull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1044},
+	{"SRIOMAINT1_ASMBLY_INFO"      ,	               0xcull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1044},
+	{"SRIOMAINT0_BAR1_IDX000"      ,	          0x200010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_BAR1_IDX001"      ,	          0x200014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_BAR1_IDX002"      ,	          0x200018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_BAR1_IDX003"      ,	          0x20001cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_BAR1_IDX004"      ,	          0x200020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_BAR1_IDX005"      ,	          0x200024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_BAR1_IDX006"      ,	          0x200028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_BAR1_IDX007"      ,	          0x20002cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_BAR1_IDX008"      ,	          0x200030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_BAR1_IDX009"      ,	          0x200034ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_BAR1_IDX010"      ,	          0x200038ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_BAR1_IDX011"      ,	          0x20003cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_BAR1_IDX012"      ,	          0x200040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_BAR1_IDX013"      ,	          0x200044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_BAR1_IDX014"      ,	          0x200048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_BAR1_IDX015"      ,	          0x20004cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_BAR1_IDX000"      ,	          0x200010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_BAR1_IDX001"      ,	          0x200014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_BAR1_IDX002"      ,	          0x200018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_BAR1_IDX003"      ,	          0x20001cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_BAR1_IDX004"      ,	          0x200020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_BAR1_IDX005"      ,	          0x200024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_BAR1_IDX006"      ,	          0x200028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_BAR1_IDX007"      ,	          0x20002cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_BAR1_IDX008"      ,	          0x200030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_BAR1_IDX009"      ,	          0x200034ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_BAR1_IDX010"      ,	          0x200038ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_BAR1_IDX011"      ,	          0x20003cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_BAR1_IDX012"      ,	          0x200040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_BAR1_IDX013"      ,	          0x200044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_BAR1_IDX014"      ,	          0x200048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_BAR1_IDX015"      ,	          0x20004cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_BELL_STATUS"      ,	          0x200080ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1046},
+	{"SRIOMAINT1_BELL_STATUS"      ,	          0x200080ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1046},
+	{"SRIOMAINT0_COMP_TAG"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1047},
+	{"SRIOMAINT1_COMP_TAG"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1047},
+	{"SRIOMAINT0_CORE_ENABLES"     ,	          0x200070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1048},
+	{"SRIOMAINT1_CORE_ENABLES"     ,	          0x200070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1048},
+	{"SRIOMAINT0_DEV_ID"           ,	               0x0ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1049},
+	{"SRIOMAINT1_DEV_ID"           ,	               0x0ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1049},
+	{"SRIOMAINT0_DEV_REV"          ,	               0x4ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1050},
+	{"SRIOMAINT1_DEV_REV"          ,	               0x4ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1050},
+	{"SRIOMAINT0_DST_OPS"          ,	              0x1cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1051},
+	{"SRIOMAINT1_DST_OPS"          ,	              0x1cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1051},
+	{"SRIOMAINT0_ERB_ATTR_CAPT"    ,	            0x2048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1052},
+	{"SRIOMAINT1_ERB_ATTR_CAPT"    ,	            0x2048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1052},
+	{"SRIOMAINT0_ERB_ERR_DET"      ,	            0x2040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1053},
+	{"SRIOMAINT1_ERB_ERR_DET"      ,	            0x2040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1053},
+	{"SRIOMAINT0_ERB_ERR_RATE"     ,	            0x2068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1054},
+	{"SRIOMAINT1_ERB_ERR_RATE"     ,	            0x2068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1054},
+	{"SRIOMAINT0_ERB_ERR_RATE_EN"  ,	            0x2044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1055},
+	{"SRIOMAINT1_ERB_ERR_RATE_EN"  ,	            0x2044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1055},
+	{"SRIOMAINT0_ERB_ERR_RATE_THR" ,	            0x206cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1056},
+	{"SRIOMAINT1_ERB_ERR_RATE_THR" ,	            0x206cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1056},
+	{"SRIOMAINT0_ERB_HDR"          ,	            0x2000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
+	{"SRIOMAINT1_ERB_HDR"          ,	            0x2000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
+	{"SRIOMAINT0_ERB_LT_ADDR_CAPT_H",	            0x2010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1058},
+	{"SRIOMAINT1_ERB_LT_ADDR_CAPT_H",	            0x2010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1058},
+	{"SRIOMAINT0_ERB_LT_ADDR_CAPT_L",	            0x2014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1059},
+	{"SRIOMAINT1_ERB_LT_ADDR_CAPT_L",	            0x2014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1059},
+	{"SRIOMAINT0_ERB_LT_CTRL_CAPT" ,	            0x201cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1060},
+	{"SRIOMAINT1_ERB_LT_CTRL_CAPT" ,	            0x201cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1060},
+	{"SRIOMAINT0_ERB_LT_DEV_ID"    ,	            0x2028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1061},
+	{"SRIOMAINT1_ERB_LT_DEV_ID"    ,	            0x2028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1061},
+	{"SRIOMAINT0_ERB_LT_DEV_ID_CAPT",	            0x2018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1062},
+	{"SRIOMAINT1_ERB_LT_DEV_ID_CAPT",	            0x2018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1062},
+	{"SRIOMAINT0_ERB_LT_ERR_DET"   ,	            0x2008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1063},
+	{"SRIOMAINT1_ERB_LT_ERR_DET"   ,	            0x2008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1063},
+	{"SRIOMAINT0_ERB_LT_ERR_EN"    ,	            0x200cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1064},
+	{"SRIOMAINT1_ERB_LT_ERR_EN"    ,	            0x200cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1064},
+	{"SRIOMAINT0_ERB_PACK_CAPT_1"  ,	            0x2050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1065},
+	{"SRIOMAINT1_ERB_PACK_CAPT_1"  ,	            0x2050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1065},
+	{"SRIOMAINT0_ERB_PACK_CAPT_2"  ,	            0x2054ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1066},
+	{"SRIOMAINT1_ERB_PACK_CAPT_2"  ,	            0x2054ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1066},
+	{"SRIOMAINT0_ERB_PACK_CAPT_3"  ,	            0x2058ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1067},
+	{"SRIOMAINT1_ERB_PACK_CAPT_3"  ,	            0x2058ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1067},
+	{"SRIOMAINT0_ERB_PACK_SYM_CAPT",	            0x204cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1068},
+	{"SRIOMAINT1_ERB_PACK_SYM_CAPT",	            0x204cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1068},
+	{"SRIOMAINT0_HB_DEV_ID_LOCK"   ,	              0x68ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1069},
+	{"SRIOMAINT1_HB_DEV_ID_LOCK"   ,	              0x68ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1069},
+	{"SRIOMAINT0_IR_BUFFER_CONFIG" ,	          0x102000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1070},
+	{"SRIOMAINT1_IR_BUFFER_CONFIG" ,	          0x102000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1070},
+	{"SRIOMAINT0_IR_BUFFER_CONFIG2",	          0x102004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1071},
+	{"SRIOMAINT1_IR_BUFFER_CONFIG2",	          0x102004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1071},
+	{"SRIOMAINT0_IR_PD_PHY_CTRL"   ,	          0x107028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1072},
+	{"SRIOMAINT1_IR_PD_PHY_CTRL"   ,	          0x107028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1072},
+	{"SRIOMAINT0_IR_PD_PHY_STAT"   ,	          0x10702cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1073},
+	{"SRIOMAINT1_IR_PD_PHY_STAT"   ,	          0x10702cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1073},
+	{"SRIOMAINT0_IR_PI_PHY_CTRL"   ,	          0x107020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1074},
+	{"SRIOMAINT1_IR_PI_PHY_CTRL"   ,	          0x107020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1074},
+	{"SRIOMAINT0_IR_PI_PHY_STAT"   ,	          0x107024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1075},
+	{"SRIOMAINT1_IR_PI_PHY_STAT"   ,	          0x107024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1075},
+	{"SRIOMAINT0_IR_SP_RX_CTRL"    ,	          0x10700cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
+	{"SRIOMAINT1_IR_SP_RX_CTRL"    ,	          0x10700cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
+	{"SRIOMAINT0_IR_SP_RX_DATA"    ,	          0x107014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1077},
+	{"SRIOMAINT1_IR_SP_RX_DATA"    ,	          0x107014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1077},
+	{"SRIOMAINT0_IR_SP_RX_STAT"    ,	          0x107010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1078},
+	{"SRIOMAINT1_IR_SP_RX_STAT"    ,	          0x107010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1078},
+	{"SRIOMAINT0_IR_SP_TX_CTRL"    ,	          0x107000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1079},
+	{"SRIOMAINT1_IR_SP_TX_CTRL"    ,	          0x107000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1079},
+	{"SRIOMAINT0_IR_SP_TX_DATA"    ,	          0x107008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1080},
+	{"SRIOMAINT1_IR_SP_TX_DATA"    ,	          0x107008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1080},
+	{"SRIOMAINT0_IR_SP_TX_STAT"    ,	          0x107004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1081},
+	{"SRIOMAINT1_IR_SP_TX_STAT"    ,	          0x107004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1081},
+	{"SRIOMAINT0_LANE_000_STATUS_0",	            0x1010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1082},
+	{"SRIOMAINT0_LANE_001_STATUS_0",	            0x1030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1082},
+	{"SRIOMAINT0_LANE_002_STATUS_0",	            0x1050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1082},
+	{"SRIOMAINT0_LANE_003_STATUS_0",	            0x1070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1082},
+	{"SRIOMAINT1_LANE_000_STATUS_0",	            0x1010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1082},
+	{"SRIOMAINT1_LANE_001_STATUS_0",	            0x1030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1082},
+	{"SRIOMAINT1_LANE_002_STATUS_0",	            0x1050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1082},
+	{"SRIOMAINT1_LANE_003_STATUS_0",	            0x1070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1082},
+	{"SRIOMAINT0_LCS_BA0"          ,	              0x58ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1083},
+	{"SRIOMAINT1_LCS_BA0"          ,	              0x58ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1083},
+	{"SRIOMAINT0_LCS_BA1"          ,	              0x5cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1084},
+	{"SRIOMAINT1_LCS_BA1"          ,	              0x5cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1084},
+	{"SRIOMAINT0_M2S_BAR0_START0"  ,	          0x200000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1085},
+	{"SRIOMAINT1_M2S_BAR0_START0"  ,	          0x200000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1085},
+	{"SRIOMAINT0_M2S_BAR0_START1"  ,	          0x200004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1086},
+	{"SRIOMAINT1_M2S_BAR0_START1"  ,	          0x200004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1086},
+	{"SRIOMAINT0_M2S_BAR1_START0"  ,	          0x200008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1087},
+	{"SRIOMAINT1_M2S_BAR1_START0"  ,	          0x200008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1087},
+	{"SRIOMAINT0_M2S_BAR1_START1"  ,	          0x20000cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1088},
+	{"SRIOMAINT1_M2S_BAR1_START1"  ,	          0x20000cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1088},
+	{"SRIOMAINT0_M2S_BAR2_START"   ,	          0x200050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1089},
+	{"SRIOMAINT1_M2S_BAR2_START"   ,	          0x200050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1089},
+	{"SRIOMAINT0_MAC_CTRL"         ,	          0x200068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1090},
+	{"SRIOMAINT1_MAC_CTRL"         ,	          0x200068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1090},
+	{"SRIOMAINT0_PE_FEAT"          ,	              0x10ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1091},
+	{"SRIOMAINT1_PE_FEAT"          ,	              0x10ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1091},
+	{"SRIOMAINT0_PE_LLC"           ,	              0x4cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1092},
+	{"SRIOMAINT1_PE_LLC"           ,	              0x4cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1092},
+	{"SRIOMAINT0_PORT_0_CTL"       ,	             0x15cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1093},
+	{"SRIOMAINT1_PORT_0_CTL"       ,	             0x15cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1093},
+	{"SRIOMAINT0_PORT_0_CTL2"      ,	             0x154ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1094},
+	{"SRIOMAINT1_PORT_0_CTL2"      ,	             0x154ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1094},
+	{"SRIOMAINT0_PORT_0_ERR_STAT"  ,	             0x158ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1095},
+	{"SRIOMAINT1_PORT_0_ERR_STAT"  ,	             0x158ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1095},
+	{"SRIOMAINT0_PORT_0_LINK_REQ"  ,	             0x140ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1096},
+	{"SRIOMAINT1_PORT_0_LINK_REQ"  ,	             0x140ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1096},
+	{"SRIOMAINT0_PORT_0_LINK_RESP" ,	             0x144ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1097},
+	{"SRIOMAINT1_PORT_0_LINK_RESP" ,	             0x144ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1097},
+	{"SRIOMAINT0_PORT_0_LOCAL_ACKID",	             0x148ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1098},
+	{"SRIOMAINT1_PORT_0_LOCAL_ACKID",	             0x148ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1098},
+	{"SRIOMAINT0_PORT_GEN_CTL"     ,	             0x13cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1099},
+	{"SRIOMAINT1_PORT_GEN_CTL"     ,	             0x13cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1099},
+	{"SRIOMAINT0_PORT_LT_CTL"      ,	             0x120ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1100},
+	{"SRIOMAINT1_PORT_LT_CTL"      ,	             0x120ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1100},
+	{"SRIOMAINT0_PORT_MBH0"        ,	             0x100ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1101},
+	{"SRIOMAINT1_PORT_MBH0"        ,	             0x100ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1101},
+	{"SRIOMAINT0_PORT_RT_CTL"      ,	             0x124ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1102},
+	{"SRIOMAINT1_PORT_RT_CTL"      ,	             0x124ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1102},
+	{"SRIOMAINT0_PORT_TTL_CTL"     ,	             0x12cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1103},
+	{"SRIOMAINT1_PORT_TTL_CTL"     ,	             0x12cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1103},
+	{"SRIOMAINT0_PRI_DEV_ID"       ,	              0x60ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT1_PRI_DEV_ID"       ,	              0x60ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT0_SEC_DEV_CTRL"     ,	          0x200064ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1105},
+	{"SRIOMAINT1_SEC_DEV_CTRL"     ,	          0x200064ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1105},
+	{"SRIOMAINT0_SEC_DEV_ID"       ,	          0x200060ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1106},
+	{"SRIOMAINT1_SEC_DEV_ID"       ,	          0x200060ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1106},
+	{"SRIOMAINT0_SERIAL_LANE_HDR"  ,	            0x1000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1107},
+	{"SRIOMAINT1_SERIAL_LANE_HDR"  ,	            0x1000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1107},
+	{"SRIOMAINT0_SRC_OPS"          ,	              0x18ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1108},
+	{"SRIOMAINT1_SRC_OPS"          ,	              0x18ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1108},
+	{"SRIOMAINT0_TX_DROP"          ,	          0x20006cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1109},
+	{"SRIOMAINT1_TX_DROP"          ,	          0x20006cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1109},
+	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1110},
+	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1111},
+	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1112},
+	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1113},
+	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1114},
+	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1115},
+	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1116},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1117},
+	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1118},
+	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1119},
+	{"TRA0_BIST_STATUS"            ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1120},
+	{"TRA0_CTL"                    ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1121},
+	{"TRA0_CYCLES_SINCE"           ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1122},
+	{"TRA0_CYCLES_SINCE1"          ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1123},
+	{"TRA0_FILT_ADR_ADR"           ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1124},
+	{"TRA0_FILT_ADR_MSK"           ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1125},
+	{"TRA0_FILT_CMD"               ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1126},
+	{"TRA0_FILT_DID"               ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1127},
+	{"TRA0_FILT_SID"               ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1128},
+	{"TRA0_INT_STATUS"             ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1129},
+	{"TRA0_READ_DAT"               ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1130},
+	{"TRA0_READ_DAT_HI"            ,	   0x11800a8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1131},
+	{"TRA0_TRIG0_ADR_ADR"          ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1132},
+	{"TRA0_TRIG0_ADR_MSK"          ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1133},
+	{"TRA0_TRIG0_CMD"              ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1134},
+	{"TRA0_TRIG0_DID"              ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1135},
+	{"TRA0_TRIG0_SID"              ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1136},
+	{"TRA0_TRIG1_ADR_ADR"          ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1137},
+	{"TRA0_TRIG1_ADR_MSK"          ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1138},
+	{"TRA0_TRIG1_CMD"              ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1139},
+	{"TRA0_TRIG1_DID"              ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1140},
+	{"TRA0_TRIG1_SID"              ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1141},
+	{"UAHC0_EHCI_ASYNCLISTADDR"    ,	   0x16f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1142},
+	{"UAHC0_EHCI_CONFIGFLAG"       ,	   0x16f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1143},
+	{"UAHC0_EHCI_CTRLDSSEGMENT"    ,	   0x16f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1144},
+	{"UAHC0_EHCI_FRINDEX"          ,	   0x16f000000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1145},
+	{"UAHC0_EHCI_HCCAPBASE"        ,	   0x16f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1146},
+	{"UAHC0_EHCI_HCCPARAMS"        ,	   0x16f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1147},
+	{"UAHC0_EHCI_HCSPARAMS"        ,	   0x16f0000000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1148},
+	{"UAHC0_EHCI_INSNREG00"        ,	   0x16f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1149},
+	{"UAHC0_EHCI_INSNREG03"        ,	   0x16f000000009cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1150},
+	{"UAHC0_EHCI_INSNREG04"        ,	   0x16f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1151},
+	{"UAHC0_EHCI_INSNREG06"        ,	   0x16f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1152},
+	{"UAHC0_EHCI_INSNREG07"        ,	   0x16f00000000ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	1153},
+	{"UAHC0_EHCI_PERIODICLISTBASE" ,	   0x16f0000000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1154},
+	{"UAHC0_EHCI_PORTSC001"        ,	   0x16f0000000054ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1155},
+	{"UAHC0_EHCI_PORTSC002"        ,	   0x16f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1155},
+	{"UAHC0_EHCI_USBCMD"           ,	   0x16f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1156},
+	{"UAHC0_EHCI_USBINTR"          ,	   0x16f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1157},
+	{"UAHC0_EHCI_USBSTS"           ,	   0x16f0000000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1158},
+	{"UAHC0_OHCI0_HCBULKCURRENTED" ,	   0x16f000000042cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1159},
+	{"UAHC0_OHCI0_HCBULKHEADED"    ,	   0x16f0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1160},
+	{"UAHC0_OHCI0_HCCOMMANDSTATUS" ,	   0x16f0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1161},
+	{"UAHC0_OHCI0_HCCONTROL"       ,	   0x16f0000000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1162},
+	{"UAHC0_OHCI0_HCCONTROLCURRENTED",	   0x16f0000000424ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1163},
+	{"UAHC0_OHCI0_HCCONTROLHEADED" ,	   0x16f0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1164},
+	{"UAHC0_OHCI0_HCDONEHEAD"      ,	   0x16f0000000430ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1165},
+	{"UAHC0_OHCI0_HCFMINTERVAL"    ,	   0x16f0000000434ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1166},
+	{"UAHC0_OHCI0_HCFMNUMBER"      ,	   0x16f000000043cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1167},
+	{"UAHC0_OHCI0_HCFMREMAINING"   ,	   0x16f0000000438ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1168},
+	{"UAHC0_OHCI0_HCHCCA"          ,	   0x16f0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1169},
+	{"UAHC0_OHCI0_HCINTERRUPTDISABLE",	   0x16f0000000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1170},
+	{"UAHC0_OHCI0_HCINTERRUPTENABLE",	   0x16f0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1171},
+	{"UAHC0_OHCI0_HCINTERRUPTSTATUS",	   0x16f000000040cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1172},
+	{"UAHC0_OHCI0_HCLSTHRESHOLD"   ,	   0x16f0000000444ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1173},
+	{"UAHC0_OHCI0_HCPERIODCURRENTED",	   0x16f000000041cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1174},
+	{"UAHC0_OHCI0_HCPERIODICSTART" ,	   0x16f0000000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1175},
+	{"UAHC0_OHCI0_HCREVISION"      ,	   0x16f0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1176},
+	{"UAHC0_OHCI0_HCRHDESCRIPTORA" ,	   0x16f0000000448ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1177},
+	{"UAHC0_OHCI0_HCRHDESCRIPTORB" ,	   0x16f000000044cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1178},
+	{"UAHC0_OHCI0_HCRHPORTSTATUS001",	   0x16f0000000454ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1179},
+	{"UAHC0_OHCI0_HCRHPORTSTATUS002",	   0x16f0000000458ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1179},
+	{"UAHC0_OHCI0_HCRHSTATUS"      ,	   0x16f0000000450ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1180},
+	{"UAHC0_OHCI0_INSNREG06"       ,	   0x16f0000000498ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1181},
+	{"UAHC0_OHCI0_INSNREG07"       ,	   0x16f000000049cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1182},
+	{"UCTL0_BIST_STATUS"           ,	   0x118006f0000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1183},
+	{"UCTL0_CLK_RST_CTL"           ,	   0x118006f000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1184},
+	{"UCTL0_EHCI_CTL"              ,	   0x118006f000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1185},
+	{"UCTL0_EHCI_FLA"              ,	   0x118006f0000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1186},
+	{"UCTL0_ERTO_CTL"              ,	   0x118006f000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1187},
+	{"UCTL0_IF_ENA"                ,	   0x118006f000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1188},
+	{"UCTL0_INT_ENA"               ,	   0x118006f000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1189},
+	{"UCTL0_INT_REG"               ,	   0x118006f000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1190},
+	{"UCTL0_OHCI_CTL"              ,	   0x118006f000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1191},
+	{"UCTL0_ORTO_CTL"              ,	   0x118006f000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1192},
+	{"UCTL0_PPAF_WM"               ,	   0x118006f000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1193},
+	{"UCTL0_UPHY_CTL_STATUS"       ,	   0x118006f000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1194},
+	{"UCTL0_UPHY_PORT000_CTL_STATUS",	   0x118006f000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1195},
+	{"UCTL0_UPHY_PORT001_CTL_STATUS",	   0x118006f000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1195},
+	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1196},
+	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1197},
+	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1198},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1199},
+	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1200},
+	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1201},
+	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1202},
+	{"ZIP_THROTTLE"                ,	   0x1180038000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1203},
 	{NULL,0,0,0,0}
 };
 static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
@@ -99593,7 +114696,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"DLL90_SETTING"               ,	20,	8,	144,	"RO",	1,	1,	0,	0},
 	{"DLL_FAST"                    ,	28,	1,	144,	"RO",	1,	1,	0,	0},
 	{"RESERVED_29_63"              ,	29,	35,	144,	"RAZ",	1,	1,	0,	0},
-	{"FCLKCNT"                     ,	0,	64,	145,	"RO",	0,	0,	0ull,	0ull},
+	{"FCLKCNT"                     ,	0,	64,	145,	"RO",	0,	1,	0ull,	0},
 	{"MWB"                         ,	0,	1,	146,	"RO",	0,	0,	0ull,	0ull},
 	{"RPB"                         ,	1,	1,	146,	"RO",	0,	0,	0ull,	0ull},
 	{"MFF"                         ,	2,	1,	146,	"RO",	0,	0,	0ull,	0ull},
@@ -99618,7 +114721,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"FADR"                        ,	4,	28,	150,	"RO",	0,	0,	0ull,	0ull},
 	{"FSYN"                        ,	32,	10,	150,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_42_63"              ,	42,	22,	150,	"RAZ",	1,	1,	0,	0},
-	{"IFBCNT"                      ,	0,	64,	151,	"RO",	0,	0,	0ull,	0ull},
+	{"IFBCNT"                      ,	0,	64,	151,	"RO",	0,	1,	1ull,	0},
 	{"CWL"                         ,	0,	3,	152,	"R/W",	0,	0,	0ull,	0ull},
 	{"MPRLOC"                      ,	3,	2,	152,	"R/W",	0,	0,	0ull,	0ull},
 	{"MPR"                         ,	5,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
@@ -99632,7 +114735,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"RBT"                         ,	18,	1,	152,	"RO",	0,	0,	1ull,	1ull},
 	{"TM"                          ,	19,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
 	{"DLLR"                        ,	20,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
-	{"WRP"                         ,	21,	3,	152,	"R/W",	0,	0,	1ull,	1ull},
+	{"WRP"                         ,	21,	3,	152,	"R/W",	0,	0,	0ull,	0ull},
 	{"PPD"                         ,	24,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESERVED_25_63"              ,	25,	39,	152,	"RAZ",	1,	1,	0,	0},
 	{"PASR_00"                     ,	0,	3,	153,	"R/W",	0,	0,	0ull,	0ull},
@@ -99660,7 +114763,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"DIC_11"                      ,	43,	2,	153,	"R/W",	0,	0,	0ull,	0ull},
 	{"RTT_NOM_11"                  ,	45,	3,	153,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESERVED_48_63"              ,	48,	16,	153,	"RAZ",	1,	1,	0,	0},
-	{"OPSCNT"                      ,	0,	64,	154,	"RO",	0,	0,	0ull,	0ull},
+	{"OPSCNT"                      ,	0,	64,	154,	"RO",	0,	1,	1ull,	0},
 	{"TS_STAGGER"                  ,	0,	1,	155,	"R/W",	0,	1,	0ull,	0},
 	{"LOOPBACK_POS"                ,	1,	1,	155,	"R/W",	0,	1,	0ull,	0},
 	{"LOOPBACK"                    ,	2,	1,	155,	"R/W",	0,	1,	0ull,	0},
@@ -99732,7 +114835,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"TWLMRD"                      ,	28,	4,	164,	"R/W",	0,	0,	10ull,	10ull},
 	{"TWLDQSEN"                    ,	32,	4,	164,	"R/W",	0,	0,	7ull,	7ull},
 	{"TFAW"                        ,	36,	5,	164,	"R/W",	0,	0,	0ull,	9ull},
-	{"TXPDLL"                      ,	41,	5,	164,	"R/W",	0,	0,	10ull,	10ull},
+	{"TXPDLL"                      ,	41,	5,	164,	"R/W",	0,	0,	0ull,	10ull},
 	{"TRAS_EXT"                    ,	46,	1,	164,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESERVED_47_63"              ,	47,	17,	164,	"RAZ",	1,	1,	0,	0},
 	{"LANEMASK"                    ,	0,	9,	165,	"R/W",	0,	1,	0ull,	0},
@@ -99757,8 +114860,8 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"WODT_D2_R1"                  ,	40,	8,	168,	"R/W",	0,	0,	255ull,	255ull},
 	{"WODT_D3_R0"                  ,	48,	8,	168,	"R/W",	0,	0,	255ull,	255ull},
 	{"WODT_D3_R1"                  ,	56,	8,	168,	"R/W",	0,	0,	255ull,	255ull},
-	{"BIST"                        ,	0,	37,	169,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_37_63"              ,	37,	27,	169,	"RAZ",	1,	1,	0,	0},
+	{"BIST"                        ,	0,	45,	169,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_63"              ,	45,	19,	169,	"RAZ",	1,	1,	0,	0},
 	{"EN"                          ,	0,	1,	170,	"R/W",	0,	0,	0ull,	1ull},
 	{"CLK"                         ,	1,	1,	170,	"RO",	0,	0,	0ull,	1ull},
 	{"RESERVED_2_63"               ,	2,	62,	170,	"RAZ",	1,	1,	0,	0},
@@ -100882,7 +115985,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"WODT_BPRCH"                  ,	22,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
 	{"RODT_BPRCH"                  ,	23,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESERVED_24_63"              ,	24,	40,	416,	"RAZ",	1,	1,	0,	0},
-	{"DCLKCNT"                     ,	0,	64,	417,	"RO",	0,	0,	0ull,	0ull},
+	{"DCLKCNT"                     ,	0,	64,	417,	"RO",	0,	1,	0ull,	0},
 	{"CLKF"                        ,	0,	7,	418,	"R/W",	0,	1,	48ull,	0},
 	{"RESET_N"                     ,	7,	1,	418,	"R/W",	0,	0,	0ull,	1ull},
 	{"CPB"                         ,	8,	3,	418,	"R/W",	0,	0,	0ull,	1ull},
@@ -100947,7 +116050,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"FBUNK"                       ,	33,	1,	425,	"RO",	0,	0,	0ull,	0ull},
 	{"FDIMM"                       ,	34,	2,	425,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_36_63"              ,	36,	28,	425,	"RAZ",	1,	1,	0,	0},
-	{"IFBCNT"                      ,	0,	64,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"IFBCNT"                      ,	0,	64,	426,	"RO",	0,	1,	1ull,	0},
 	{"NXM_WR_ERR"                  ,	0,	1,	427,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"SEC_ERR"                     ,	1,	4,	427,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"DED_ERR"                     ,	5,	4,	427,	"R/W1C",	0,	0,	0ull,	0ull},
@@ -100969,7 +116072,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"RBT"                         ,	18,	1,	429,	"RO",	0,	0,	1ull,	1ull},
 	{"TM"                          ,	19,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
 	{"DLLR"                        ,	20,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
-	{"WRP"                         ,	21,	3,	429,	"R/W",	0,	0,	1ull,	1ull},
+	{"WRP"                         ,	21,	3,	429,	"R/W",	0,	0,	0ull,	0ull},
 	{"PPD"                         ,	24,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESERVED_25_63"              ,	25,	39,	429,	"RAZ",	1,	1,	0,	0},
 	{"PASR_00"                     ,	0,	3,	430,	"R/W",	0,	0,	0ull,	0ull},
@@ -101007,7 +116110,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"MEM_MSB_D3_R0"               ,	32,	4,	431,	"R/W",	0,	1,	0ull,	0},
 	{"MEM_MSB_D3_R1"               ,	36,	4,	431,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_40_63"              ,	40,	24,	431,	"RAZ",	1,	1,	0,	0},
-	{"OPSCNT"                      ,	0,	64,	432,	"RO",	0,	0,	0ull,	0ull},
+	{"OPSCNT"                      ,	0,	64,	432,	"RO",	0,	1,	1ull,	0},
 	{"TS_STAGGER"                  ,	0,	1,	433,	"R/W",	0,	1,	0ull,	0},
 	{"LOOPBACK_POS"                ,	1,	1,	433,	"R/W",	0,	1,	0ull,	0},
 	{"LOOPBACK"                    ,	2,	1,	433,	"R/W",	0,	1,	0ull,	0},
@@ -101090,7 +116193,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"TWLMRD"                      ,	28,	4,	443,	"R/W",	0,	0,	10ull,	10ull},
 	{"TWLDQSEN"                    ,	32,	4,	443,	"R/W",	0,	0,	7ull,	7ull},
 	{"TFAW"                        ,	36,	5,	443,	"R/W",	0,	0,	0ull,	9ull},
-	{"TXPDLL"                      ,	41,	5,	443,	"R/W",	0,	0,	10ull,	10ull},
+	{"TXPDLL"                      ,	41,	5,	443,	"R/W",	0,	0,	0ull,	10ull},
 	{"TRAS_EXT"                    ,	46,	1,	443,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESERVED_47_63"              ,	47,	17,	443,	"RAZ",	1,	1,	0,	0},
 	{"TRESET"                      ,	0,	1,	444,	"R/W",	0,	1,	1ull,	0},
@@ -101364,10 +116467,10 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"HOST_MODE"                   ,	6,	1,	495,	"RO",	1,	1,	0,	0},
 	{"RST_LINK"                    ,	7,	1,	495,	"R/W",	1,	1,	0,	0},
 	{"RST_DONE"                    ,	8,	1,	495,	"RO",	1,	1,	0,	0},
-	{"PRST_LINK"                   ,	9,	1,	495,	"R/W",	1,	1,	0,	0},
+	{"PRST_LINK"                   ,	9,	1,	495,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_10_63"              ,	10,	54,	495,	"RAZ",	1,	1,	0,	0},
-	{"WARM_RST_DLY"                ,	0,	16,	496,	"R/W",	0,	1,	2047ull,	0},
-	{"SOFT_RST_DLY"                ,	16,	16,	496,	"R/W",	0,	1,	2047ull,	0},
+	{"SOFT_RST_DLY"                ,	0,	16,	496,	"R/W",	0,	1,	2047ull,	0},
+	{"WARM_RST_DLY"                ,	16,	16,	496,	"R/W",	0,	1,	2047ull,	0},
 	{"RESERVED_32_63"              ,	32,	32,	496,	"RAZ",	1,	1,	0,	0},
 	{"RST_LINK0"                   ,	0,	1,	497,	"R/W1C",	0,	1,	0ull,	0},
 	{"RST_LINK1"                   ,	1,	1,	497,	"R/W1C",	0,	1,	0ull,	0},
@@ -101514,7 +116617,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"MRGDAT"                      ,	4,	1,	528,	"RO",	0,	0,	0ull,	0ull},
 	{"OPFDAT"                      ,	5,	1,	528,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_6_63"               ,	6,	58,	528,	"RAZ",	0,	0,	0ull,	0ull},
-	{"MRQ_HWM"                     ,	0,	2,	529,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRQ_HWM"                     ,	0,	2,	529,	"R/W",	0,	0,	0ull,	1ull},
 	{"NBTARB"                      ,	2,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
 	{"LENDIAN"                     ,	3,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	4,	1,	529,	"R/W",	0,	0,	1ull,	0ull},
@@ -101770,7 +116873,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"AP_D"                        ,	20,	1,	581,	"RO",	0,	0,	0ull,	0ull},
 	{"TP"                          ,	21,	1,	581,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_22_31"              ,	22,	10,	581,	"RAZ",	1,	1,	0,	0},
-	{"MLS"                         ,	0,	4,	582,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"MLS"                         ,	0,	4,	582,	"RO/WRSL",	1,	1,	0,	0},
 	{"MLW"                         ,	4,	6,	582,	"RO/WRSL",	0,	0,	4ull,	4ull},
 	{"ASLPMS"                      ,	10,	2,	582,	"RO/WRSL",	0,	0,	3ull,	3ull},
 	{"L0EL"                        ,	12,	3,	582,	"RO/WRSL",	0,	0,	6ull,	6ull},
@@ -101838,7 +116941,10 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"CTV"                         ,	0,	4,	587,	"RO",	0,	0,	0ull,	0ull},
 	{"CTD"                         ,	4,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESERVED_5_31"               ,	5,	27,	587,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_31"               ,	0,	32,	588,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	588,	"RAZ",	1,	1,	0,	0},
+	{"SLSV"                        ,	1,	7,	588,	"RO/WRSL",	1,	1,	0,	0},
+	{"CLS"                         ,	8,	1,	588,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	588,	"RAZ",	1,	1,	0,	0},
 	{"TLS"                         ,	0,	4,	589,	"R/W",	1,	0,	0,	2ull},
 	{"EC"                          ,	4,	1,	589,	"R/W",	0,	0,	0ull,	0ull},
 	{"HASD"                        ,	5,	1,	589,	"RO",	0,	0,	0ull,	0ull},
@@ -101925,8 +117031,8 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"DWORD2"                      ,	0,	32,	600,	"RO",	0,	0,	0ull,	0ull},
 	{"DWORD3"                      ,	0,	32,	601,	"RO",	0,	0,	0ull,	0ull},
 	{"DWORD4"                      ,	0,	32,	602,	"RO",	0,	0,	0ull,	0ull},
-	{"RTLTL"                       ,	0,	16,	603,	"R/W",	0,	0,	4143ull,	4143ull},
-	{"RTL"                         ,	16,	16,	603,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"RTLTL"                       ,	0,	16,	603,	"R/W",	0,	1,	4143ull,	0},
+	{"RTL"                         ,	16,	16,	603,	"R/W",	0,	1,	12429ull,	0},
 	{"OMR"                         ,	0,	32,	604,	"R/W",	0,	1,	4294967295ull,	0},
 	{"LINK_NUM"                    ,	0,	8,	605,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_8_14"               ,	8,	7,	605,	"RAZ",	1,	1,	0,	0},
@@ -102210,8 +117316,8 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"AP_D"                        ,	20,	1,	653,	"RO",	0,	0,	0ull,	0ull},
 	{"TP"                          ,	21,	1,	653,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_22_31"              ,	22,	10,	653,	"RAZ",	1,	1,	0,	0},
-	{"MLS"                         ,	0,	4,	654,	"R/W",	0,	0,	2ull,	2ull},
-	{"MLW"                         ,	4,	6,	654,	"R/W",	0,	0,	8ull,	8ull},
+	{"MLS"                         ,	0,	4,	654,	"R/W",	1,	1,	0,	0},
+	{"MLW"                         ,	4,	6,	654,	"R/W",	0,	0,	4ull,	4ull},
 	{"ASLPMS"                      ,	10,	2,	654,	"R/W",	0,	0,	3ull,	3ull},
 	{"L0EL"                        ,	12,	3,	654,	"R/W",	0,	0,	6ull,	6ull},
 	{"L1EL"                        ,	15,	3,	654,	"R/W",	0,	0,	6ull,	6ull},
@@ -102233,7 +117339,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"LBM_INT_ENB"                 ,	10,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
 	{"LAB_INT_ENB"                 ,	11,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESERVED_12_15"              ,	12,	4,	655,	"RAZ",	1,	1,	0,	0},
-	{"LS"                          ,	16,	4,	655,	"RO",	0,	0,	1ull,	1ull},
+	{"LS"                          ,	16,	4,	655,	"RO",	1,	1,	0,	0},
 	{"NLW"                         ,	20,	6,	655,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_26_26"              ,	26,	1,	655,	"RAZ",	1,	1,	0,	0},
 	{"LT"                          ,	27,	1,	655,	"RO",	0,	0,	0ull,	0ull},
@@ -102293,8 +117399,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"CTV"                         ,	0,	4,	661,	"RO",	0,	0,	0ull,	0ull},
 	{"CTD"                         ,	4,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESERVED_5_31"               ,	5,	27,	661,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_31"               ,	0,	32,	662,	"RAZ",	1,	1,	0,	0},
-	{"TLS"                         ,	0,	4,	663,	"R/W",	1,	0,	0,	2ull},
+	{"RESERVED_0_0"                ,	0,	1,	662,	"RAZ",	1,	1,	0,	0},
+	{"SLSV"                        ,	1,	7,	662,	"RO/WRSL",	1,	1,	0,	0},
+	{"CLS"                         ,	8,	1,	662,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	662,	"RAZ",	1,	1,	0,	0},
+	{"TLS"                         ,	0,	4,	663,	"R/W",	1,	1,	0,	0},
 	{"EC"                          ,	4,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
 	{"HASD"                        ,	5,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
 	{"SDE"                         ,	6,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
@@ -102395,8 +117504,8 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"AEIMN"                       ,	27,	5,	678,	"R/W",	0,	0,	0ull,	0ull},
 	{"ECSI"                        ,	0,	16,	679,	"RO",	0,	0,	0ull,	0ull},
 	{"EFNFSI"                      ,	16,	16,	679,	"RO",	0,	0,	0ull,	0ull},
-	{"RTLTL"                       ,	0,	16,	680,	"R/W",	0,	0,	4143ull,	4143ull},
-	{"RTL"                         ,	16,	16,	680,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"RTLTL"                       ,	0,	16,	680,	"R/W",	0,	1,	4143ull,	0},
+	{"RTL"                         ,	16,	16,	680,	"R/W",	0,	1,	12429ull,	0},
 	{"OMR"                         ,	0,	32,	681,	"R/W",	0,	1,	4294967295ull,	0},
 	{"LINK_NUM"                    ,	0,	8,	682,	"R/W",	0,	0,	4ull,	4ull},
 	{"RESERVED_8_14"               ,	8,	7,	682,	"RAZ",	1,	1,	0,	0},
@@ -103122,87 +118231,74 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"RESERVED_1_63"               ,	1,	63,	777,	"RAZ",	1,	1,	0,	0},
 	{"DRP_OCTS"                    ,	0,	32,	778,	"R/W",	0,	1,	0ull,	0},
 	{"DRP_PKTS"                    ,	32,	32,	778,	"R/W",	0,	1,	0ull,	0},
-	{"OCTS"                        ,	0,	48,	779,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_48_63"              ,	48,	16,	779,	"RAZ",	1,	1,	0,	0},
-	{"RAW"                         ,	0,	32,	780,	"R/W",	0,	1,	0ull,	0},
-	{"PKTS"                        ,	32,	32,	780,	"R/W",	0,	1,	0ull,	0},
-	{"MCST"                        ,	0,	32,	781,	"R/W",	0,	1,	0ull,	0},
-	{"BCST"                        ,	32,	32,	781,	"R/W",	0,	1,	0ull,	0},
-	{"H64"                         ,	0,	32,	782,	"R/W",	0,	1,	0ull,	0},
-	{"H65TO127"                    ,	32,	32,	782,	"R/W",	0,	1,	0ull,	0},
-	{"H128TO255"                   ,	0,	32,	783,	"R/W",	0,	1,	0ull,	0},
-	{"H256TO511"                   ,	32,	32,	783,	"R/W",	0,	1,	0ull,	0},
-	{"H512TO1023"                  ,	0,	32,	784,	"R/W",	0,	1,	0ull,	0},
-	{"H1024TO1518"                 ,	32,	32,	784,	"R/W",	0,	1,	0ull,	0},
-	{"H1519"                       ,	0,	32,	785,	"R/W",	0,	1,	0ull,	0},
-	{"FCS"                         ,	32,	32,	785,	"R/W",	0,	1,	0ull,	0},
-	{"UNDERSZ"                     ,	0,	32,	786,	"R/W",	0,	1,	0ull,	0},
-	{"FRAG"                        ,	32,	32,	786,	"R/W",	0,	1,	0ull,	0},
-	{"OVERSZ"                      ,	0,	32,	787,	"R/W",	0,	1,	0ull,	0},
-	{"JABBER"                      ,	32,	32,	787,	"R/W",	0,	1,	0ull,	0},
-	{"RDCLR"                       ,	0,	1,	788,	"R/W",	0,	0,	1ull,	1ull},
-	{"RESERVED_1_63"               ,	1,	63,	788,	"RAZ",	1,	1,	0,	0},
-	{"ERRS"                        ,	0,	16,	789,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_16_63"              ,	16,	48,	789,	"RAZ",	1,	1,	0,	0},
-	{"OCTS"                        ,	0,	48,	790,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_48_63"              ,	48,	16,	790,	"RAZ",	1,	1,	0,	0},
-	{"PKTS"                        ,	0,	32,	791,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	791,	"RAZ",	1,	1,	0,	0},
-	{"EN"                          ,	0,	8,	792,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_8_63"               ,	8,	56,	792,	"RAZ",	1,	1,	0,	0},
-	{"MASK"                        ,	0,	16,	793,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	793,	"RAZ",	1,	1,	0,	0},
-	{"SRC"                         ,	0,	16,	794,	"R/W",	0,	0,	0ull,	0ull},
-	{"DST"                         ,	16,	16,	794,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	794,	"RAZ",	1,	1,	0,	0},
-	{"ENTRY"                       ,	0,	62,	795,	"RO",	1,	1,	0,	0},
-	{"RESERVED_62_62"              ,	62,	1,	795,	"RAZ",	1,	1,	0,	0},
-	{"VAL"                         ,	63,	1,	795,	"RO",	1,	1,	0,	0},
-	{"DRP_OCTS"                    ,	0,	32,	796,	"R/W",	0,	1,	0ull,	0},
-	{"DRP_PKTS"                    ,	32,	32,	796,	"R/W",	0,	1,	0ull,	0},
-	{"OCTS"                        ,	0,	48,	797,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_48_63"              ,	48,	16,	797,	"RAZ",	1,	1,	0,	0},
-	{"RAW"                         ,	0,	32,	798,	"R/W",	0,	1,	0ull,	0},
-	{"PKTS"                        ,	32,	32,	798,	"R/W",	0,	1,	0ull,	0},
-	{"MCST"                        ,	0,	32,	799,	"R/W",	0,	1,	0ull,	0},
-	{"BCST"                        ,	32,	32,	799,	"R/W",	0,	1,	0ull,	0},
-	{"H64"                         ,	0,	32,	800,	"R/W",	0,	1,	0ull,	0},
-	{"H65TO127"                    ,	32,	32,	800,	"R/W",	0,	1,	0ull,	0},
-	{"H128TO255"                   ,	0,	32,	801,	"R/W",	0,	1,	0ull,	0},
-	{"H256TO511"                   ,	32,	32,	801,	"R/W",	0,	1,	0ull,	0},
-	{"H512TO1023"                  ,	0,	32,	802,	"R/W",	0,	1,	0ull,	0},
-	{"H1024TO1518"                 ,	32,	32,	802,	"R/W",	0,	1,	0ull,	0},
-	{"H1519"                       ,	0,	32,	803,	"R/W",	0,	1,	0ull,	0},
-	{"FCS"                         ,	32,	32,	803,	"R/W",	0,	1,	0ull,	0},
-	{"UNDERSZ"                     ,	0,	32,	804,	"R/W",	0,	1,	0ull,	0},
-	{"FRAG"                        ,	32,	32,	804,	"R/W",	0,	1,	0ull,	0},
-	{"OVERSZ"                      ,	0,	32,	805,	"R/W",	0,	1,	0ull,	0},
-	{"JABBER"                      ,	32,	32,	805,	"R/W",	0,	1,	0ull,	0},
-	{"COUNT"                       ,	0,	32,	806,	"R/W1C",	1,	0,	0,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	806,	"RAZ",	1,	1,	0,	0},
-	{"COUNT"                       ,	0,	48,	807,	"R/W1C",	1,	0,	0,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	807,	"RAZ",	1,	1,	0,	0},
-	{"SIZE"                        ,	0,	16,	808,	"RO",	1,	0,	0,	0ull},
-	{"SEGS"                        ,	16,	6,	808,	"RO",	1,	0,	0,	0ull},
-	{"CMD"                         ,	22,	14,	808,	"RO",	1,	0,	0,	0ull},
-	{"FAU"                         ,	36,	28,	808,	"RO",	1,	0,	0,	0ull},
-	{"PTR"                         ,	0,	40,	809,	"RO",	1,	0,	0,	0ull},
-	{"SIZE"                        ,	40,	16,	809,	"RO",	1,	0,	0,	0ull},
-	{"POOL"                        ,	56,	3,	809,	"RO",	1,	0,	0,	0ull},
-	{"BACK"                        ,	59,	4,	809,	"RO",	1,	0,	0,	0ull},
-	{"I"                           ,	63,	1,	809,	"RO",	1,	0,	0,	0ull},
-	{"PTRS2"                       ,	0,	17,	810,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	810,	"RAZ",	1,	1,	0,	0},
-	{"PTRS1"                       ,	32,	17,	810,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	810,	"RAZ",	1,	1,	0,	0},
-	{"MOD"                         ,	0,	3,	811,	"RO",	1,	0,	0,	0ull},
-	{"CNT"                         ,	3,	13,	811,	"RO",	1,	0,	0,	0ull},
-	{"CHK"                         ,	16,	1,	811,	"RO",	1,	0,	0,	0ull},
-	{"LEN"                         ,	17,	1,	811,	"RO",	1,	0,	0,	0ull},
-	{"SOP"                         ,	18,	1,	811,	"RO",	1,	0,	0,	0ull},
-	{"UID"                         ,	19,	3,	811,	"RO",	1,	0,	0,	0ull},
-	{"MAJ"                         ,	22,	1,	811,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	811,	"RAZ",	1,	1,	0,	0},
+	{"MCAST"                       ,	0,	32,	779,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	779,	"R/W",	0,	1,	0ull,	0},
+	{"MCAST"                       ,	0,	32,	780,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	780,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	781,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	781,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	782,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	782,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	783,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	783,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	784,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	784,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	785,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	785,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	786,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	786,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	787,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	787,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	788,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	788,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	789,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	789,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	790,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	790,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	791,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	791,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	792,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	792,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	793,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	793,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	794,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	794,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	795,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	795,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	796,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	797,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	797,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	797,	"RO",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	798,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	798,	"R/W",	0,	1,	0ull,	0},
+	{"MCAST"                       ,	0,	32,	799,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	799,	"R/W",	0,	1,	0ull,	0},
+	{"MCAST"                       ,	0,	32,	800,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	800,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	801,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	801,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	802,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	802,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	803,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	803,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	804,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	804,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	805,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	805,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	806,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	806,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	807,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	807,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	808,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	808,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	809,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	809,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	32,	810,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	810,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	811,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	811,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	16,	812,	"RO",	1,	0,	0,	0ull},
 	{"SEGS"                        ,	16,	6,	812,	"RO",	1,	0,	0,	0ull},
 	{"CMD"                         ,	22,	14,	812,	"RO",	1,	0,	0,	0ull},
@@ -103212,2165 +118308,2157 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"POOL"                        ,	56,	3,	813,	"RO",	1,	0,	0,	0ull},
 	{"BACK"                        ,	59,	4,	813,	"RO",	1,	0,	0,	0ull},
 	{"I"                           ,	63,	1,	813,	"RO",	1,	0,	0,	0ull},
-	{"DATA"                        ,	0,	64,	814,	"RO",	1,	0,	0,	0ull},
-	{"PTR"                         ,	0,	40,	815,	"RO",	1,	0,	0,	0ull},
-	{"SIZE"                        ,	40,	16,	815,	"RO",	1,	0,	0,	0ull},
-	{"POOL"                        ,	56,	3,	815,	"RO",	1,	0,	0,	0ull},
-	{"BACK"                        ,	59,	4,	815,	"RO",	1,	0,	0,	0ull},
-	{"I"                           ,	63,	1,	815,	"RO",	1,	0,	0,	0ull},
-	{"DATA"                        ,	0,	64,	816,	"RO",	1,	0,	0,	0ull},
-	{"MAJOR"                       ,	0,	3,	817,	"RO",	1,	0,	0,	0ull},
-	{"MINOR"                       ,	3,	2,	817,	"RO",	1,	0,	0,	0ull},
-	{"WAIT"                        ,	5,	1,	817,	"RO",	1,	0,	0,	0ull},
-	{"CHK_MODE"                    ,	6,	1,	817,	"RO",	1,	0,	0,	0ull},
-	{"CHK_ONCE"                    ,	7,	1,	817,	"RO",	1,	0,	0,	0ull},
-	{"INIT_DWRITE"                 ,	8,	1,	817,	"RO",	1,	0,	0,	0ull},
-	{"DREAD_SOP"                   ,	9,	1,	817,	"RO",	1,	0,	0,	0ull},
-	{"UID"                         ,	10,	2,	817,	"RO",	1,	0,	0,	0ull},
-	{"CMND_OFF"                    ,	12,	6,	817,	"RO",	1,	0,	0,	0ull},
-	{"CMND_SIZ"                    ,	18,	16,	817,	"RO",	1,	0,	0,	0ull},
-	{"CMND_SEGS"                   ,	34,	6,	817,	"RO",	1,	0,	0,	0ull},
-	{"CURR_OFF"                    ,	40,	16,	817,	"RO",	1,	0,	0,	0ull},
-	{"CURR_SIZ"                    ,	56,	8,	817,	"RO",	1,	0,	0,	0ull},
-	{"CURR_SIZ"                    ,	0,	8,	818,	"RO",	1,	0,	0,	0ull},
-	{"CURR_PTR"                    ,	8,	40,	818,	"RO",	1,	0,	0,	0ull},
-	{"NXT_INFLT"                   ,	48,	6,	818,	"RO",	1,	0,	0,	0ull},
-	{"MAJOR_3"                     ,	54,	1,	818,	"RO",	1,	0,	0,	0ull},
-	{"PTP"                         ,	55,	1,	818,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_56_63"              ,	56,	8,	818,	"RAZ",	1,	1,	0,	0},
-	{"QID_BASE"                    ,	0,	8,	819,	"RO",	1,	0,	0,	0ull},
-	{"QID_OFF"                     ,	8,	4,	819,	"RO",	1,	0,	0,	0ull},
-	{"QID_OFFMAX"                  ,	12,	4,	819,	"RO",	1,	0,	0,	0ull},
-	{"QCB_RIDX"                    ,	16,	5,	819,	"RO",	1,	0,	0,	0ull},
-	{"QOS"                         ,	21,	3,	819,	"RO",	1,	0,	0,	0ull},
-	{"STATC"                       ,	24,	1,	819,	"RO",	1,	0,	0,	0ull},
-	{"ACTIVE"                      ,	25,	1,	819,	"RO",	1,	0,	0,	0ull},
-	{"PREEMPTED"                   ,	26,	1,	819,	"RO",	1,	0,	0,	0ull},
-	{"PREEMPTEE"                   ,	27,	1,	819,	"RO",	1,	0,	0,	0ull},
-	{"PREEMPTER"                   ,	28,	1,	819,	"RO",	1,	0,	0,	0ull},
-	{"QID_OFFTHS"                  ,	29,	4,	819,	"RO",	1,	0,	0,	0ull},
-	{"QID_OFFRES"                  ,	33,	4,	819,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_37_63"              ,	37,	27,	819,	"RO",	1,	0,	0,	0ull},
-	{"QCB_RIDX"                    ,	0,	6,	820,	"RO",	1,	0,	0,	0ull},
-	{"QCB_WIDX"                    ,	6,	6,	820,	"RO",	1,	0,	0,	0ull},
-	{"BUF_PTR"                     ,	12,	33,	820,	"RO",	1,	0,	0,	0ull},
-	{"BUF_SIZ"                     ,	45,	13,	820,	"RO",	1,	0,	0,	0ull},
-	{"TAIL"                        ,	58,	1,	820,	"RO",	1,	0,	0,	0ull},
-	{"QOS"                         ,	59,	5,	820,	"RO",	1,	0,	0,	0ull},
-	{"QOS"                         ,	0,	3,	821,	"RO",	1,	0,	0,	0ull},
-	{"STATIC_Q"                    ,	3,	1,	821,	"RO",	1,	0,	0,	0ull},
-	{"S_TAIL"                      ,	4,	1,	821,	"RO",	1,	0,	0,	0ull},
-	{"STATIC_P"                    ,	5,	1,	821,	"RO",	1,	0,	0,	0ull},
-	{"PREEMPTEE"                   ,	6,	1,	821,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_7_7"                ,	7,	1,	821,	"RAZ",	1,	1,	0,	0},
-	{"DOORBELL"                    ,	8,	20,	821,	"RO",	1,	0,	0,	0ull},
-	{"PREEMPTER"                   ,	28,	1,	821,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_29_63"              ,	29,	35,	821,	"RAZ",	1,	1,	0,	0},
-	{"PTRS3"                       ,	0,	17,	822,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	822,	"RAZ",	1,	1,	0,	0},
-	{"PTRS0"                       ,	32,	17,	822,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	822,	"RAZ",	1,	1,	0,	0},
-	{"PID"                         ,	0,	6,	823,	"R/W",	1,	0,	0,	0ull},
-	{"EID"                         ,	6,	4,	823,	"R/W",	1,	0,	0,	0ull},
-	{"BP_PORT"                     ,	10,	6,	823,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_16_52"              ,	16,	37,	823,	"RAZ",	1,	1,	0,	0},
-	{"QOS_MASK"                    ,	53,	8,	823,	"R/W",	1,	0,	0,	0ull},
-	{"STATIC_P"                    ,	61,	1,	823,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_62_63"              ,	62,	2,	823,	"RAZ",	1,	1,	0,	0},
-	{"PID"                         ,	0,	6,	824,	"R/W",	1,	0,	0,	0ull},
-	{"EID"                         ,	6,	4,	824,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_10_52"              ,	10,	43,	824,	"RAZ",	1,	1,	0,	0},
-	{"QOS_MASK"                    ,	53,	8,	824,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	824,	"RAZ",	1,	1,	0,	0},
-	{"PID"                         ,	0,	6,	825,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	825,	"RAZ",	1,	1,	0,	0},
-	{"RATE_PKT"                    ,	8,	24,	825,	"R/W",	1,	0,	0,	0ull},
-	{"RATE_WORD"                   ,	32,	19,	825,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_51_63"              ,	51,	13,	825,	"RAZ",	1,	1,	0,	0},
-	{"PID"                         ,	0,	6,	826,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	826,	"RAZ",	1,	1,	0,	0},
-	{"RATE_LIM"                    ,	8,	24,	826,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	826,	"RAZ",	1,	1,	0,	0},
-	{"QUEUE"                       ,	0,	7,	827,	"R/W",	1,	0,	0,	0ull},
-	{"PORT"                        ,	7,	6,	827,	"WR0",	1,	0,	0,	0ull},
-	{"INDEX"                       ,	13,	3,	827,	"WR0",	1,	0,	0,	0ull},
-	{"TAIL"                        ,	16,	1,	827,	"R/W",	1,	0,	0,	0ull},
-	{"BUF_PTR"                     ,	17,	36,	827,	"R/W",	1,	0,	0,	0ull},
+	{"PTRS2"                       ,	0,	17,	814,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	814,	"RAZ",	1,	1,	0,	0},
+	{"PTRS1"                       ,	32,	17,	814,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	814,	"RAZ",	1,	1,	0,	0},
+	{"MOD"                         ,	0,	3,	815,	"RO",	1,	0,	0,	0ull},
+	{"CNT"                         ,	3,	13,	815,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	16,	1,	815,	"RO",	1,	0,	0,	0ull},
+	{"LEN"                         ,	17,	1,	815,	"RO",	1,	0,	0,	0ull},
+	{"SOP"                         ,	18,	1,	815,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	19,	3,	815,	"RO",	1,	0,	0,	0ull},
+	{"MAJ"                         ,	22,	1,	815,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	815,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	816,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	816,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	816,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	816,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	817,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	817,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	817,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	817,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	817,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	818,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	819,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	819,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	819,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	819,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	819,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	820,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	3,	821,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	3,	2,	821,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	5,	1,	821,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	6,	1,	821,	"RO",	1,	0,	0,	0ull},
+	{"CHK_ONCE"                    ,	7,	1,	821,	"RO",	1,	0,	0,	0ull},
+	{"INIT_DWRITE"                 ,	8,	1,	821,	"RO",	1,	0,	0,	0ull},
+	{"DREAD_SOP"                   ,	9,	1,	821,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	10,	2,	821,	"RO",	1,	0,	0,	0ull},
+	{"CMND_OFF"                    ,	12,	6,	821,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	18,	16,	821,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	34,	6,	821,	"RO",	1,	0,	0,	0ull},
+	{"CURR_OFF"                    ,	40,	16,	821,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	56,	8,	821,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	0,	8,	822,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	8,	40,	822,	"RO",	1,	0,	0,	0ull},
+	{"NXT_INFLT"                   ,	48,	6,	822,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR_3"                     ,	54,	1,	822,	"RO",	1,	0,	0,	0ull},
+	{"PTP"                         ,	55,	1,	822,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	822,	"RAZ",	1,	1,	0,	0},
+	{"QID_BASE"                    ,	0,	8,	823,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	8,	4,	823,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFMAX"                  ,	12,	4,	823,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	16,	5,	823,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	21,	3,	823,	"RO",	1,	0,	0,	0ull},
+	{"STATC"                       ,	24,	1,	823,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	25,	1,	823,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTED"                   ,	26,	1,	823,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	27,	1,	823,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	823,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFTHS"                  ,	29,	4,	823,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFRES"                  ,	33,	4,	823,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	823,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	6,	824,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	6,	6,	824,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	12,	33,	824,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	45,	13,	824,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	58,	1,	824,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	59,	5,	824,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	3,	825,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	3,	1,	825,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	4,	1,	825,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	5,	1,	825,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	6,	1,	825,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	825,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	8,	20,	825,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	825,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	825,	"RAZ",	1,	1,	0,	0},
+	{"PTRS3"                       ,	0,	17,	826,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	826,	"RAZ",	1,	1,	0,	0},
+	{"PTRS0"                       ,	32,	17,	826,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	826,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	827,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	827,	"R/W",	1,	0,	0,	0ull},
+	{"BP_PORT"                     ,	10,	6,	827,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_52"              ,	16,	37,	827,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	827,	"R/W",	1,	0,	0,	0ull},
-	{"STATIC_Q"                    ,	61,	1,	827,	"R/W",	1,	0,	0,	0ull},
-	{"STATIC_P"                    ,	62,	1,	827,	"R/W",	1,	0,	0,	0ull},
-	{"S_TAIL"                      ,	63,	1,	827,	"R/W",	1,	0,	0,	0ull},
-	{"QID"                         ,	0,	7,	828,	"R/W",	1,	0,	0,	0ull},
-	{"PID"                         ,	7,	6,	828,	"WR0",	1,	0,	0,	0ull},
-	{"RESERVED_13_52"              ,	13,	40,	828,	"RAZ",	1,	1,	0,	0},
+	{"STATIC_P"                    ,	61,	1,	827,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	827,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	828,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	828,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_10_52"              ,	10,	43,	828,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	828,	"R/W",	1,	0,	0,	0ull},
 	{"RESERVED_61_63"              ,	61,	3,	828,	"RAZ",	1,	1,	0,	0},
-	{"DAT_PTR"                     ,	0,	4,	829,	"RO",	1,	0,	0,	0ull},
-	{"DAT_DAT"                     ,	4,	2,	829,	"RO",	1,	0,	0,	0ull},
-	{"PRT_CTL"                     ,	6,	2,	829,	"RO",	1,	0,	0,	0ull},
-	{"PRT_QSB"                     ,	8,	3,	829,	"RO",	1,	0,	0,	0ull},
-	{"PRT_QCB"                     ,	11,	2,	829,	"RO",	1,	0,	0,	0ull},
-	{"NCB_INB"                     ,	13,	2,	829,	"RO",	1,	0,	0,	0ull},
-	{"PRT_PSB"                     ,	15,	8,	829,	"RO",	1,	0,	0,	0ull},
-	{"PRT_NXT"                     ,	23,	1,	829,	"RO",	1,	0,	0,	0ull},
-	{"PRT_CHK"                     ,	24,	3,	829,	"RO",	1,	0,	0,	0ull},
-	{"OUT_WIF"                     ,	27,	1,	829,	"RO",	1,	0,	0,	0ull},
-	{"OUT_STA"                     ,	28,	1,	829,	"RO",	1,	0,	0,	0ull},
-	{"OUT_CTL"                     ,	29,	3,	829,	"RO",	1,	0,	0,	0ull},
-	{"OUT_DAT"                     ,	32,	1,	829,	"RO",	1,	0,	0,	0ull},
-	{"IOB"                         ,	33,	1,	829,	"RO",	1,	0,	0,	0ull},
-	{"CSR"                         ,	34,	1,	829,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_35_63"              ,	35,	29,	829,	"RAZ",	1,	1,	0,	0},
-	{"SIZE"                        ,	0,	13,	830,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_13_19"              ,	13,	7,	830,	"R/W",	0,	0,	0ull,	0ull},
-	{"POOL"                        ,	20,	3,	830,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	830,	"RAZ",	1,	1,	0,	0},
-	{"ASSERTS"                     ,	0,	64,	831,	"RO",	0,	0,	0ull,	0ull},
-	{"ASSERTS"                     ,	0,	64,	832,	"RO",	0,	0,	0ull,	0ull},
-	{"ASSERTS"                     ,	0,	64,	833,	"RO",	0,	0,	0ull,	0ull},
-	{"ASSERTS"                     ,	0,	64,	834,	"RO",	0,	0,	0ull,	0ull},
-	{"ENGINE0"                     ,	0,	4,	835,	"R/W",	0,	0,	4ull,	4ull},
-	{"ENGINE1"                     ,	4,	4,	835,	"R/W",	0,	0,	4ull,	4ull},
-	{"ENGINE2"                     ,	8,	4,	835,	"R/W",	0,	0,	4ull,	4ull},
-	{"ENGINE3"                     ,	12,	4,	835,	"R/W",	0,	0,	4ull,	4ull},
-	{"ENGINE4"                     ,	16,	4,	835,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENGINE5"                     ,	20,	4,	835,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENGINE6"                     ,	24,	4,	835,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENGINE7"                     ,	28,	4,	835,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENGINE8"                     ,	32,	4,	835,	"R/W",	0,	0,	4ull,	4ull},
-	{"ENGINE9"                     ,	36,	4,	835,	"R/W",	0,	0,	4ull,	4ull},
-	{"ENGINE10"                    ,	40,	4,	835,	"R/W",	0,	0,	4ull,	4ull},
-	{"ENGINE11"                    ,	44,	4,	835,	"R/W",	0,	0,	4ull,	4ull},
-	{"RESERVED_48_63"              ,	48,	16,	835,	"RAZ",	1,	1,	0,	0},
-	{"MASK"                        ,	0,	12,	836,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_12_63"              ,	12,	52,	836,	"RAZ",	1,	1,	0,	0},
-	{"PARITY"                      ,	0,	1,	837,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"DOORBELL"                    ,	1,	1,	837,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"CURRZERO"                    ,	2,	1,	837,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	837,	"RAZ",	1,	1,	0,	0},
-	{"ENA_PKO"                     ,	0,	1,	838,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENA_DWB"                     ,	1,	1,	838,	"R/W",	0,	0,	0ull,	0ull},
-	{"STORE_BE"                    ,	2,	1,	838,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESET"                       ,	3,	1,	838,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	838,	"RAZ",	1,	1,	0,	0},
-	{"MODE0"                       ,	0,	3,	839,	"R/W",	0,	0,	2ull,	2ull},
-	{"MODE1"                       ,	3,	3,	839,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	839,	"RAZ",	1,	1,	0,	0},
-	{"PARITY"                      ,	0,	1,	840,	"R/W",	0,	0,	0ull,	0ull},
-	{"DOORBELL"                    ,	1,	1,	840,	"R/W",	0,	0,	0ull,	0ull},
-	{"CURRZERO"                    ,	2,	1,	840,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	840,	"RAZ",	1,	1,	0,	0},
-	{"MODE"                        ,	0,	2,	841,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	841,	"RAZ",	1,	1,	0,	0},
-	{"QID7"                        ,	0,	1,	842,	"R/W",	0,	0,	0ull,	0ull},
-	{"IDX3"                        ,	1,	1,	842,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	842,	"RAZ",	1,	1,	0,	0},
-	{"INDEX"                       ,	0,	8,	843,	"R/W",	0,	0,	0ull,	0ull},
-	{"INC"                         ,	8,	8,	843,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	843,	"RAZ",	1,	1,	0,	0},
-	{"WQE_WORD"                    ,	0,	4,	844,	"R/W",	0,	0,	2ull,	2ull},
-	{"RESERVED_4_63"               ,	4,	60,	844,	"RAZ",	1,	1,	0,	0},
-	{"ADR"                         ,	0,	1,	845,	"RO",	0,	0,	0ull,	0ull},
-	{"PEND"                        ,	1,	1,	845,	"RO",	0,	0,	0ull,	0ull},
-	{"FIDX"                        ,	2,	1,	845,	"RO",	0,	0,	0ull,	0ull},
-	{"INDEX"                       ,	3,	1,	845,	"RO",	0,	0,	0ull,	0ull},
-	{"NBT"                         ,	4,	4,	845,	"RO",	0,	0,	0ull,	0ull},
-	{"NBR"                         ,	8,	3,	845,	"RO",	0,	0,	0ull,	0ull},
-	{"CAM"                         ,	11,	1,	845,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_12_15"              ,	12,	4,	845,	"RAZ",	1,	1,	0,	0},
-	{"PP"                          ,	16,	6,	845,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_22_63"              ,	22,	42,	845,	"RAZ",	1,	1,	0,	0},
-	{"DS_PC"                       ,	0,	32,	846,	"R/W1C",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	846,	"RAZ",	1,	1,	0,	0},
-	{"SBE"                         ,	0,	1,	847,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"DBE"                         ,	1,	1,	847,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"SBE_IE"                      ,	2,	1,	847,	"R/W",	0,	1,	0ull,	0},
-	{"DBE_IE"                      ,	3,	1,	847,	"R/W",	0,	1,	0ull,	0},
-	{"SYN"                         ,	4,	5,	847,	"RO",	1,	1,	0,	0},
-	{"RESERVED_9_11"               ,	9,	3,	847,	"RAZ",	1,	1,	0,	0},
-	{"RPE"                         ,	12,	1,	847,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RPE_IE"                      ,	13,	1,	847,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_14_15"              ,	14,	2,	847,	"RAZ",	1,	1,	0,	0},
-	{"IOP"                         ,	16,	13,	847,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_29_31"              ,	29,	3,	847,	"RAZ",	1,	1,	0,	0},
-	{"IOP_IE"                      ,	32,	13,	847,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_45_63"              ,	45,	19,	847,	"RAZ",	1,	1,	0,	0},
-	{"NBR_THR"                     ,	0,	5,	848,	"R/W",	0,	0,	2ull,	2ull},
-	{"PFR_DIS"                     ,	5,	1,	848,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	848,	"RAZ",	1,	1,	0,	0},
-	{"IQ_CNT"                      ,	0,	32,	849,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	849,	"RAZ",	1,	1,	0,	0},
-	{"IQ_CNT"                      ,	0,	32,	850,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	850,	"RAZ",	1,	1,	0,	0},
-	{"IQ_INT"                      ,	0,	8,	851,	"R/W1C",	0,	1,	0ull,	0},
-	{"RESERVED_8_63"               ,	8,	56,	851,	"RAZ",	1,	1,	0,	0},
-	{"INT_EN"                      ,	0,	8,	852,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_8_63"               ,	8,	56,	852,	"RAZ",	1,	1,	0,	0},
-	{"IQ_THR"                      ,	0,	32,	853,	"R/W",	0,	1,	4294967295ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	853,	"RAZ",	1,	1,	0,	0},
-	{"NOS_CNT"                     ,	0,	11,	854,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_11_63"              ,	11,	53,	854,	"RAZ",	1,	1,	0,	0},
-	{"NW_TIM"                      ,	0,	10,	855,	"R/W",	0,	0,	0ull,	1023ull},
-	{"RESERVED_10_63"              ,	10,	54,	855,	"RAZ",	1,	1,	0,	0},
-	{"RST_MSK"                     ,	0,	8,	856,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_8_63"               ,	8,	56,	856,	"RAZ",	1,	1,	0,	0},
-	{"GRP_MSK"                     ,	0,	16,	857,	"R/W",	0,	0,	65535ull,	65535ull},
-	{"QOS0_PRI"                    ,	16,	4,	857,	"R/W",	0,	1,	0ull,	0},
-	{"QOS1_PRI"                    ,	20,	4,	857,	"R/W",	0,	1,	0ull,	0},
-	{"QOS2_PRI"                    ,	24,	4,	857,	"R/W",	0,	1,	0ull,	0},
-	{"QOS3_PRI"                    ,	28,	4,	857,	"R/W",	0,	1,	0ull,	0},
-	{"QOS4_PRI"                    ,	32,	4,	857,	"R/W",	0,	1,	0ull,	0},
-	{"QOS5_PRI"                    ,	36,	4,	857,	"R/W",	0,	1,	0ull,	0},
-	{"QOS6_PRI"                    ,	40,	4,	857,	"R/W",	0,	1,	0ull,	0},
-	{"QOS7_PRI"                    ,	44,	4,	857,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_48_63"              ,	48,	16,	857,	"RAZ",	1,	1,	0,	0},
-	{"RND"                         ,	0,	8,	858,	"R/W",	0,	1,	255ull,	0},
-	{"RND_P1"                      ,	8,	8,	858,	"R/W",	0,	1,	255ull,	0},
-	{"RND_P2"                      ,	16,	8,	858,	"R/W",	0,	1,	255ull,	0},
-	{"RND_P3"                      ,	24,	8,	858,	"R/W",	0,	1,	255ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	858,	"RAZ",	1,	1,	0,	0},
-	{"MIN_THR"                     ,	0,	10,	859,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_10_11"              ,	10,	2,	859,	"RAZ",	1,	1,	0,	0},
-	{"MAX_THR"                     ,	12,	10,	859,	"R/W",	0,	1,	1023ull,	0},
-	{"RESERVED_22_23"              ,	22,	2,	859,	"RAZ",	1,	1,	0,	0},
-	{"FREE_CNT"                    ,	24,	11,	859,	"RO",	0,	1,	1011ull,	0},
-	{"RESERVED_35_35"              ,	35,	1,	859,	"RAZ",	1,	1,	0,	0},
-	{"BUF_CNT"                     ,	36,	11,	859,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_47_47"              ,	47,	1,	859,	"RAZ",	1,	1,	0,	0},
-	{"DES_CNT"                     ,	48,	11,	859,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_59_63"              ,	59,	5,	859,	"RAZ",	1,	1,	0,	0},
-	{"TS_PC"                       ,	0,	32,	860,	"R/W1C",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	860,	"RAZ",	1,	1,	0,	0},
-	{"WA_PC"                       ,	0,	32,	861,	"R/W1C",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	861,	"RAZ",	1,	1,	0,	0},
-	{"WA_PC"                       ,	0,	32,	862,	"R/W1C",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	862,	"RAZ",	1,	1,	0,	0},
-	{"WQ_INT"                      ,	0,	16,	863,	"R/W1C",	0,	1,	0ull,	0},
-	{"IQ_DIS"                      ,	16,	16,	863,	"R/W1",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	863,	"RAZ",	1,	1,	0,	0},
-	{"IQ_CNT"                      ,	0,	11,	864,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_11_11"              ,	11,	1,	864,	"RAZ",	1,	1,	0,	0},
-	{"DS_CNT"                      ,	12,	11,	864,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_23_23"              ,	23,	1,	864,	"RAZ",	1,	1,	0,	0},
-	{"TC_CNT"                      ,	24,	4,	864,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_28_63"              ,	28,	36,	864,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_7"                ,	0,	8,	865,	"RAZ",	1,	1,	0,	0},
-	{"PC_THR"                      ,	8,	20,	865,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_28_31"              ,	28,	4,	865,	"RAZ",	1,	1,	0,	0},
-	{"PC"                          ,	32,	28,	865,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_60_63"              ,	60,	4,	865,	"RAZ",	1,	1,	0,	0},
-	{"IQ_THR"                      ,	0,	10,	866,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_10_11"              ,	10,	2,	866,	"RAZ",	1,	1,	0,	0},
-	{"DS_THR"                      ,	12,	10,	866,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_22_23"              ,	22,	2,	866,	"RAZ",	1,	1,	0,	0},
-	{"TC_THR"                      ,	24,	4,	866,	"R/W",	0,	1,	0ull,	0},
-	{"TC_EN"                       ,	28,	1,	866,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_29_63"              ,	29,	35,	866,	"RAZ",	1,	1,	0,	0},
-	{"WS_PC"                       ,	0,	32,	867,	"R/W1C",	0,	1,	0ull,	0},
+	{"PID"                         ,	0,	6,	829,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	829,	"RAZ",	1,	1,	0,	0},
+	{"RATE_PKT"                    ,	8,	24,	829,	"R/W",	1,	0,	0,	0ull},
+	{"RATE_WORD"                   ,	32,	19,	829,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	829,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	830,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	830,	"RAZ",	1,	1,	0,	0},
+	{"RATE_LIM"                    ,	8,	24,	830,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	830,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE"                       ,	0,	7,	831,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	7,	6,	831,	"WR0",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	13,	3,	831,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	16,	1,	831,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	17,	36,	831,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	831,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	831,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	831,	"R/W",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	831,	"R/W",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	7,	832,	"R/W",	1,	0,	0,	0ull},
+	{"PID"                         ,	7,	6,	832,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	832,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	832,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	832,	"RAZ",	1,	1,	0,	0},
+	{"DAT_PTR"                     ,	0,	4,	833,	"RO",	1,	0,	0,	0ull},
+	{"DAT_DAT"                     ,	4,	2,	833,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CTL"                     ,	6,	2,	833,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QSB"                     ,	8,	3,	833,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QCB"                     ,	11,	2,	833,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	13,	2,	833,	"RO",	1,	0,	0,	0ull},
+	{"PRT_PSB"                     ,	15,	8,	833,	"RO",	1,	0,	0,	0ull},
+	{"PRT_NXT"                     ,	23,	1,	833,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CHK"                     ,	24,	3,	833,	"RO",	1,	0,	0,	0ull},
+	{"OUT_WIF"                     ,	27,	1,	833,	"RO",	1,	0,	0,	0ull},
+	{"OUT_STA"                     ,	28,	1,	833,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CTL"                     ,	29,	3,	833,	"RO",	1,	0,	0,	0ull},
+	{"OUT_DAT"                     ,	32,	1,	833,	"RO",	1,	0,	0,	0ull},
+	{"IOB"                         ,	33,	1,	833,	"RO",	1,	0,	0,	0ull},
+	{"CSR"                         ,	34,	1,	833,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	833,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	13,	834,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	834,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	834,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	834,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	64,	835,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	836,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	837,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	838,	"RO",	0,	0,	0ull,	0ull},
+	{"ENGINE0"                     ,	0,	4,	839,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE1"                     ,	4,	4,	839,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE2"                     ,	8,	4,	839,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE3"                     ,	12,	4,	839,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE4"                     ,	16,	4,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE5"                     ,	20,	4,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE6"                     ,	24,	4,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE7"                     ,	28,	4,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE8"                     ,	32,	4,	839,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE9"                     ,	36,	4,	839,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE10"                    ,	40,	4,	839,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE11"                    ,	44,	4,	839,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_48_63"              ,	48,	16,	839,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	12,	840,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	840,	"RAZ",	1,	1,	0,	0},
+	{"PARITY"                      ,	0,	1,	841,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	841,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	841,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	841,	"RAZ",	1,	1,	0,	0},
+	{"ENA_PKO"                     ,	0,	1,	842,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	842,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	842,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	842,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	842,	"RAZ",	1,	1,	0,	0},
+	{"MODE0"                       ,	0,	3,	843,	"R/W",	0,	0,	2ull,	2ull},
+	{"MODE1"                       ,	3,	3,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	843,	"RAZ",	1,	1,	0,	0},
+	{"PARITY"                      ,	0,	1,	844,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	844,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	844,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	844,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	16,	845,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	845,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	846,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	846,	"RAZ",	1,	1,	0,	0},
+	{"PREEMPTER"                   ,	0,	1,	847,	"R/W",	0,	0,	0ull,	0ull},
+	{"PREEMPTEE"                   ,	1,	1,	847,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	847,	"RAZ",	1,	1,	0,	0},
+	{"QID7"                        ,	0,	1,	848,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDX3"                        ,	1,	1,	848,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	848,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	849,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	849,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	849,	"RAZ",	1,	1,	0,	0},
+	{"WQE_WORD"                    ,	0,	4,	850,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_4_63"               ,	4,	60,	850,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	1,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND"                        ,	1,	1,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"FIDX"                        ,	2,	1,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	3,	1,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT"                         ,	4,	4,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR"                         ,	8,	3,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	11,	1,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	851,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	16,	6,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	851,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	32,	852,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	852,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE_IE"                      ,	2,	1,	853,	"R/W",	0,	1,	0ull,	0},
+	{"DBE_IE"                      ,	3,	1,	853,	"R/W",	0,	1,	0ull,	0},
+	{"SYN"                         ,	4,	5,	853,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_11"               ,	9,	3,	853,	"RAZ",	1,	1,	0,	0},
+	{"RPE"                         ,	12,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE_IE"                      ,	13,	1,	853,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	853,	"RAZ",	1,	1,	0,	0},
+	{"IOP"                         ,	16,	13,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	853,	"RAZ",	1,	1,	0,	0},
+	{"IOP_IE"                      ,	32,	13,	853,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_63"              ,	45,	19,	853,	"RAZ",	1,	1,	0,	0},
+	{"NBR_THR"                     ,	0,	5,	854,	"R/W",	0,	0,	2ull,	2ull},
+	{"PFR_DIS"                     ,	5,	1,	854,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	854,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	855,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	855,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	856,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	856,	"RAZ",	1,	1,	0,	0},
+	{"IQ_INT"                      ,	0,	8,	857,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	857,	"RAZ",	1,	1,	0,	0},
+	{"INT_EN"                      ,	0,	8,	858,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	858,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	32,	859,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	859,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	11,	860,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	860,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	861,	"R/W",	0,	0,	0ull,	1023ull},
+	{"RESERVED_10_63"              ,	10,	54,	861,	"RAZ",	1,	1,	0,	0},
+	{"RST_MSK"                     ,	0,	8,	862,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	862,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	16,	863,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"QOS0_PRI"                    ,	16,	4,	863,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1_PRI"                    ,	20,	4,	863,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2_PRI"                    ,	24,	4,	863,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3_PRI"                    ,	28,	4,	863,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4_PRI"                    ,	32,	4,	863,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5_PRI"                    ,	36,	4,	863,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6_PRI"                    ,	40,	4,	863,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7_PRI"                    ,	44,	4,	863,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	863,	"RAZ",	1,	1,	0,	0},
+	{"RND"                         ,	0,	8,	864,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P1"                      ,	8,	8,	864,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P2"                      ,	16,	8,	864,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P3"                      ,	24,	8,	864,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	864,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	10,	865,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_11"              ,	10,	2,	865,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	12,	10,	865,	"R/W",	0,	1,	1023ull,	0},
+	{"RESERVED_22_23"              ,	22,	2,	865,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	24,	11,	865,	"RO",	0,	1,	1011ull,	0},
+	{"RESERVED_35_35"              ,	35,	1,	865,	"RAZ",	1,	1,	0,	0},
+	{"BUF_CNT"                     ,	36,	11,	865,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	865,	"RAZ",	1,	1,	0,	0},
+	{"DES_CNT"                     ,	48,	11,	865,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_59_63"              ,	59,	5,	865,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	32,	866,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	866,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	867,	"R/W1C",	0,	1,	0ull,	0},
 	{"RESERVED_32_63"              ,	32,	32,	867,	"RAZ",	1,	1,	0,	0},
-	{"IWORD"                       ,	0,	64,	868,	"RO",	1,	1,	0,	0},
-	{"P_DAT"                       ,	0,	64,	869,	"RO",	1,	1,	0,	0},
-	{"Q_DAT"                       ,	0,	64,	870,	"RO",	1,	1,	0,	0},
-	{"DAT"                         ,	0,	2,	871,	"RO",	1,	0,	0,	0ull},
-	{"NCB_INB"                     ,	2,	2,	871,	"RO",	1,	0,	0,	0ull},
-	{"NCB_OUB"                     ,	4,	1,	871,	"RO",	1,	0,	0,	0ull},
-	{"STA"                         ,	5,	1,	871,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	871,	"RAZ",	1,	1,	0,	0},
-	{"PTR"                         ,	0,	33,	872,	"R/W",	0,	1,	0ull,	0},
-	{"SIZE"                        ,	33,	13,	872,	"R/W",	0,	1,	0ull,	0},
-	{"POOL"                        ,	46,	3,	872,	"R/W",	0,	1,	0ull,	0},
-	{"DWB"                         ,	49,	9,	872,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_58_63"              ,	58,	6,	872,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESET"                       ,	0,	1,	873,	"RAZ",	0,	0,	0ull,	0ull},
-	{"STORE_LE"                    ,	1,	1,	873,	"R/W",	0,	0,	0ull,	0ull},
-	{"MAX_READ"                    ,	2,	4,	873,	"R/W",	0,	0,	8ull,	8ull},
-	{"RESERVED_6_63"               ,	6,	58,	873,	"RAZ",	0,	0,	0ull,	0ull},
-	{"STATE"                       ,	0,	5,	874,	"RO",	1,	1,	0,	0},
-	{"COMMIT"                      ,	5,	1,	874,	"RO",	1,	1,	0,	0},
-	{"OWORDPV"                     ,	6,	1,	874,	"RO",	1,	1,	0,	0},
-	{"OWORDQV"                     ,	7,	1,	874,	"RO",	1,	1,	0,	0},
-	{"IWIDX"                       ,	8,	6,	874,	"RO",	1,	1,	0,	0},
-	{"RESERVED_14_15"              ,	14,	2,	874,	"RO",	1,	1,	0,	0},
-	{"IRIDX"                       ,	16,	6,	874,	"RO",	1,	1,	0,	0},
-	{"RESERVED_22_31"              ,	22,	10,	874,	"RO",	1,	1,	0,	0},
-	{"LOOP"                        ,	32,	25,	874,	"RO",	1,	1,	0,	0},
-	{"RESERVED_57_63"              ,	57,	7,	874,	"RO",	1,	1,	0,	0},
-	{"CWORD"                       ,	0,	64,	875,	"RO",	1,	1,	0,	0},
-	{"PTR"                         ,	0,	40,	876,	"RO",	1,	1,	0,	0},
-	{"SIZE"                        ,	40,	16,	876,	"RO",	1,	1,	0,	0},
-	{"FLAGS"                       ,	56,	8,	876,	"RO",	1,	1,	0,	0},
-	{"INDEX"                       ,	0,	8,	877,	"RO",	1,	1,	0,	0},
-	{"SOD"                         ,	8,	1,	877,	"RO",	1,	1,	0,	0},
-	{"EOD"                         ,	9,	1,	877,	"RO",	1,	1,	0,	0},
-	{"WC"                          ,	10,	1,	877,	"RO",	1,	1,	0,	0},
-	{"P"                           ,	11,	1,	877,	"RO",	1,	1,	0,	0},
-	{"Q"                           ,	12,	1,	877,	"RO",	1,	1,	0,	0},
-	{"RESERVED_13_63"              ,	13,	51,	877,	"RAZ",	1,	1,	0,	0},
-	{"ASSERTS"                     ,	0,	15,	878,	"RO",	1,	1,	0,	0},
-	{"RESERVED_15_63"              ,	15,	49,	878,	"RAZ",	1,	1,	0,	0},
-	{"OWORDP"                      ,	0,	64,	879,	"RO",	1,	1,	0,	0},
-	{"OWORDQ"                      ,	0,	64,	880,	"RO",	1,	1,	0,	0},
-	{"RWORD"                       ,	0,	64,	881,	"RO",	1,	1,	0,	0},
-	{"N0CREDS"                     ,	0,	4,	882,	"RO",	0,	0,	8ull,	0ull},
-	{"N1CREDS"                     ,	4,	4,	882,	"RO",	0,	0,	8ull,	0ull},
-	{"POWCREDS"                    ,	8,	2,	882,	"RO",	0,	0,	2ull,	0ull},
-	{"RESERVED_10_11"              ,	10,	2,	882,	"RAZ",	1,	1,	0,	0},
-	{"FPACREDS"                    ,	12,	2,	882,	"RO",	0,	0,	1ull,	0ull},
-	{"WCCREDS"                     ,	14,	2,	882,	"RO",	0,	0,	0ull,	0ull},
-	{"NIWIDX0"                     ,	16,	4,	882,	"RO",	1,	1,	0,	0},
-	{"NIRIDX0"                     ,	20,	4,	882,	"RO",	1,	1,	0,	0},
-	{"NIWIDX1"                     ,	24,	4,	882,	"RO",	1,	1,	0,	0},
-	{"NIRIDX1"                     ,	28,	4,	882,	"RO",	1,	1,	0,	0},
-	{"NIRVAL6"                     ,	32,	5,	882,	"RO",	1,	1,	0,	0},
-	{"NIRARB6"                     ,	37,	1,	882,	"RO",	1,	1,	0,	0},
-	{"NIRQUE6"                     ,	38,	2,	882,	"RO",	1,	1,	0,	0},
-	{"NIROPC6"                     ,	40,	3,	882,	"RO",	1,	1,	0,	0},
-	{"NIRVAL7"                     ,	43,	5,	882,	"RO",	1,	1,	0,	0},
-	{"NIRQUE7"                     ,	48,	2,	882,	"RO",	1,	1,	0,	0},
-	{"NIROPC7"                     ,	50,	3,	882,	"RO",	1,	1,	0,	0},
-	{"RESERVED_53_63"              ,	53,	11,	882,	"RAZ",	1,	1,	0,	0},
-	{"PTR"                         ,	0,	40,	883,	"RO",	1,	1,	0,	0},
-	{"SIZE"                        ,	40,	16,	883,	"RO",	1,	1,	0,	0},
-	{"CNT"                         ,	56,	8,	883,	"RO",	1,	1,	0,	0},
-	{"CNT"                         ,	0,	15,	884,	"RO",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	868,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	868,	"RAZ",	1,	1,	0,	0},
+	{"WQ_INT"                      ,	0,	16,	869,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_DIS"                      ,	16,	16,	869,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	869,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	11,	870,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	870,	"RAZ",	1,	1,	0,	0},
+	{"DS_CNT"                      ,	12,	11,	870,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	870,	"RAZ",	1,	1,	0,	0},
+	{"TC_CNT"                      ,	24,	4,	870,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	870,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	871,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	871,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	871,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	871,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	871,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	10,	872,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_11"              ,	10,	2,	872,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	12,	10,	872,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_23"              ,	22,	2,	872,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	24,	4,	872,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	28,	1,	872,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	872,	"RAZ",	1,	1,	0,	0},
+	{"WS_PC"                       ,	0,	32,	873,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	873,	"RAZ",	1,	1,	0,	0},
+	{"IWORD"                       ,	0,	64,	874,	"RO",	1,	1,	0,	0},
+	{"P_DAT"                       ,	0,	64,	875,	"RO",	1,	1,	0,	0},
+	{"Q_DAT"                       ,	0,	64,	876,	"RO",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	2,	877,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	2,	2,	877,	"RO",	1,	0,	0,	0ull},
+	{"NCB_OUB"                     ,	4,	1,	877,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	5,	1,	877,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	877,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	878,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	33,	13,	878,	"R/W",	0,	1,	0ull,	0},
+	{"POOL"                        ,	46,	3,	878,	"R/W",	0,	1,	0ull,	0},
+	{"DWB"                         ,	49,	9,	878,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	878,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	879,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STORE_LE"                    ,	1,	1,	879,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_READ"                    ,	2,	4,	879,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_6_63"               ,	6,	58,	879,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	0,	5,	880,	"RO",	1,	1,	0,	0},
+	{"COMMIT"                      ,	5,	1,	880,	"RO",	1,	1,	0,	0},
+	{"OWORDPV"                     ,	6,	1,	880,	"RO",	1,	1,	0,	0},
+	{"OWORDQV"                     ,	7,	1,	880,	"RO",	1,	1,	0,	0},
+	{"IWIDX"                       ,	8,	6,	880,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	880,	"RO",	1,	1,	0,	0},
+	{"IRIDX"                       ,	16,	6,	880,	"RO",	1,	1,	0,	0},
+	{"RESERVED_22_31"              ,	22,	10,	880,	"RO",	1,	1,	0,	0},
+	{"LOOP"                        ,	32,	25,	880,	"RO",	1,	1,	0,	0},
+	{"RESERVED_57_63"              ,	57,	7,	880,	"RO",	1,	1,	0,	0},
+	{"CWORD"                       ,	0,	64,	881,	"RO",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	882,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	882,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	882,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	883,	"RO",	1,	1,	0,	0},
+	{"SOD"                         ,	8,	1,	883,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	9,	1,	883,	"RO",	1,	1,	0,	0},
+	{"WC"                          ,	10,	1,	883,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	11,	1,	883,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	12,	1,	883,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	883,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	15,	884,	"RO",	1,	1,	0,	0},
 	{"RESERVED_15_63"              ,	15,	49,	884,	"RAZ",	1,	1,	0,	0},
-	{"PTR"                         ,	0,	40,	885,	"RO",	1,	1,	0,	0},
-	{"SIZE"                        ,	40,	16,	885,	"RO",	1,	1,	0,	0},
-	{"FLAGS"                       ,	56,	8,	885,	"RO",	1,	1,	0,	0},
-	{"INDEX"                       ,	0,	8,	886,	"RO",	1,	1,	0,	0},
-	{"MUL"                         ,	8,	8,	886,	"RO",	1,	1,	0,	0},
-	{"P"                           ,	16,	1,	886,	"RO",	1,	1,	0,	0},
-	{"Q"                           ,	17,	1,	886,	"RO",	1,	1,	0,	0},
-	{"INI"                         ,	18,	1,	886,	"RO",	1,	1,	0,	0},
-	{"EOD"                         ,	19,	1,	886,	"RO",	1,	1,	0,	0},
-	{"RESERVED_20_63"              ,	20,	44,	886,	"RAZ",	1,	1,	0,	0},
-	{"DOORBELL"                    ,	0,	1,	887,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	887,	"RAZ",	1,	1,	0,	0},
-	{"DOORBELL"                    ,	0,	1,	888,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	888,	"RAZ",	1,	1,	0,	0},
-	{"COEFFS"                      ,	0,	8,	889,	"R/W",	0,	0,	29ull,	29ull},
-	{"RESERVED_8_63"               ,	8,	56,	889,	"RAZ",	0,	0,	0ull,	0ull},
-	{"INDEX"                       ,	0,	16,	890,	"R/W",	0,	0,	0ull,	0ull},
-	{"INC"                         ,	16,	16,	890,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	890,	"RAZ",	1,	1,	0,	0},
-	{"MEM"                         ,	0,	1,	891,	"RO",	0,	0,	0ull,	0ull},
-	{"RRC"                         ,	1,	1,	891,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	891,	"RAZ",	1,	1,	0,	0},
-	{"ENT_EN"                      ,	0,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
-	{"RNG_EN"                      ,	1,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
-	{"RNM_RST"                     ,	2,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
-	{"RNG_RST"                     ,	3,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
-	{"EXP_ENT"                     ,	4,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENT_SEL"                     ,	5,	4,	892,	"R/W",	0,	0,	0ull,	0ull},
-	{"EER_VAL"                     ,	9,	1,	892,	"RO",	0,	0,	0ull,	0ull},
-	{"EER_LCK"                     ,	10,	1,	892,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_11_63"              ,	11,	53,	892,	"RAZ",	1,	1,	0,	0},
-	{"DAT"                         ,	0,	64,	893,	"RO",	1,	1,	0,	0},
-	{"KEY"                         ,	0,	64,	894,	"WO",	0,	0,	0ull,	0ull},
-	{"DAT"                         ,	0,	64,	895,	"RO",	1,	1,	0,	0},
-	{"NCB_CMD"                     ,	0,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"MSI"                         ,	1,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"DSI0_0"                      ,	2,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"DSI0_1"                      ,	3,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"DSI1_0"                      ,	4,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"DSI1_1"                      ,	5,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_8"                ,	6,	3,	896,	"RAZ",	1,	1,	0,	0},
-	{"P2N1_P1"                     ,	9,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"P2N1_P0"                     ,	10,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"P2N1_N"                      ,	11,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"P2N1_C1"                     ,	12,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"P2N1_C0"                     ,	13,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"P2N0_P1"                     ,	14,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"P2N0_P0"                     ,	15,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"P2N0_N"                      ,	16,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"P2N0_C1"                     ,	17,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"P2N0_C0"                     ,	18,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_19_24"              ,	19,	6,	896,	"RAZ",	1,	1,	0,	0},
-	{"CPL_P1"                      ,	25,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"CPL_P0"                      ,	26,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"N2P1_O"                      ,	27,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"N2P1_C"                      ,	28,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"N2P0_O"                      ,	29,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"N2P0_C"                      ,	30,	1,	896,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_31_63"              ,	31,	33,	896,	"RAZ",	1,	1,	0,	0},
-	{"WAIT_COM"                    ,	0,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_4"                ,	1,	4,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"PTLP_RO"                     ,	5,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_6"                ,	6,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"CTLP_RO"                     ,	7,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
-	{"INTA_MAP"                    ,	8,	2,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"INTB_MAP"                    ,	10,	2,	897,	"R/W",	0,	0,	1ull,	1ull},
-	{"INTC_MAP"                    ,	12,	2,	897,	"R/W",	0,	0,	2ull,	2ull},
-	{"INTD_MAP"                    ,	14,	2,	897,	"R/W",	0,	0,	3ull,	3ull},
-	{"WAITL_COM"                   ,	16,	1,	897,	"R/W",	0,	1,	0ull,	0},
-	{"DIS_PORT"                    ,	17,	1,	897,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"INTA"                        ,	18,	1,	897,	"RO",	0,	0,	1ull,	1ull},
-	{"INTB"                        ,	19,	1,	897,	"RO",	0,	0,	1ull,	1ull},
-	{"INTC"                        ,	20,	1,	897,	"RO",	0,	0,	1ull,	1ull},
-	{"INTD"                        ,	21,	1,	897,	"RO",	0,	0,	1ull,	1ull},
-	{"RESERVED_22_63"              ,	22,	42,	897,	"RAZ",	1,	1,	0,	0},
-	{"CHIP_REV"                    ,	0,	8,	898,	"RO",	1,	1,	0,	0},
-	{"P0_NTAGS"                    ,	8,	6,	898,	"R/W",	0,	0,	32ull,	32ull},
-	{"P1_NTAGS"                    ,	14,	6,	898,	"R/W",	0,	0,	32ull,	32ull},
-	{"RESERVED_20_63"              ,	20,	44,	898,	"RAZ",	1,	1,	0,	0},
-	{"P0_FCNT"                     ,	0,	6,	899,	"RO",	0,	1,	0ull,	0},
-	{"P0_UCNT"                     ,	6,	16,	899,	"RO",	0,	1,	0ull,	0},
-	{"P1_FCNT"                     ,	22,	6,	899,	"RO",	0,	1,	0ull,	0},
-	{"P1_UCNT"                     ,	28,	16,	899,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_44_63"              ,	44,	20,	899,	"RAZ",	1,	1,	0,	0},
-	{"DATA"                        ,	0,	17,	900,	"RO",	0,	1,	0ull,	0},
-	{"DSEL_EXT"                    ,	17,	1,	900,	"R/W",	0,	0,	1ull,	0ull},
-	{"RESERVED_18_63"              ,	18,	46,	900,	"RAZ",	1,	1,	0,	0},
-	{"DBG_SEL"                     ,	0,	32,	901,	"R/W",	0,	1,	0ull,	0},
-	{"ADBG_SEL"                    ,	32,	1,	901,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_33_63"              ,	33,	31,	901,	"RAZ",	1,	1,	0,	0},
-	{"CNT"                         ,	0,	32,	902,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	902,	"RAZ",	1,	1,	0,	0},
-	{"CNT"                         ,	0,	32,	903,	"R/W",	0,	1,	0ull,	0},
-	{"TIME"                        ,	32,	32,	903,	"R/W",	0,	1,	0ull,	0},
-	{"TIM"                         ,	0,	32,	904,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	904,	"RAZ",	1,	1,	0,	0},
-	{"RML_TO"                      ,	0,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_1_1"                ,	1,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
-	{"BAR0_TO"                     ,	2,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOB2BIG"                     ,	3,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
-	{"PCNT"                        ,	4,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
-	{"PTIME"                       ,	5,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_7"                ,	6,	2,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"M0_UP_B0"                    ,	8,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
-	{"M0_UP_WI"                    ,	9,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
-	{"M0_UN_B0"                    ,	10,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
-	{"M0_UN_WI"                    ,	11,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
-	{"M1_UP_B0"                    ,	12,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
-	{"M1_UP_WI"                    ,	13,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
-	{"M1_UN_B0"                    ,	14,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
-	{"M1_UN_WI"                    ,	15,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
-	{"MIO_INT0"                    ,	16,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"MIO_INT1"                    ,	17,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_18_31"              ,	18,	14,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"DMAFI"                       ,	32,	2,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"DCNT"                        ,	34,	2,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"DTIME"                       ,	36,	2,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_38_47"              ,	38,	10,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"PIDBOF"                      ,	48,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"PSLDBOF"                     ,	49,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"POUT_ERR"                    ,	50,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"PIN_BP"                      ,	51,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"PGL_ERR"                     ,	52,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"PDI_ERR"                     ,	53,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"POP_ERR"                     ,	54,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"PINS_ERR"                    ,	55,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"SPRT0_ERR"                   ,	56,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"SPRT1_ERR"                   ,	57,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_58_59"              ,	58,	2,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"ILL_PAD"                     ,	60,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	905,	"R/W",	0,	0,	0ull,	0ull},
-	{"RML_TO"                      ,	0,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_1_1"                ,	1,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
-	{"BAR0_TO"                     ,	2,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOB2BIG"                     ,	3,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
-	{"PCNT"                        ,	4,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
-	{"PTIME"                       ,	5,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_7"                ,	6,	2,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"M0_UP_B0"                    ,	8,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
-	{"M0_UP_WI"                    ,	9,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
-	{"M0_UN_B0"                    ,	10,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
-	{"M0_UN_WI"                    ,	11,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
-	{"M1_UP_B0"                    ,	12,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
-	{"M1_UP_WI"                    ,	13,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
-	{"M1_UN_B0"                    ,	14,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
-	{"M1_UN_WI"                    ,	15,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
-	{"MIO_INT0"                    ,	16,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
-	{"MIO_INT1"                    ,	17,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
-	{"MAC0_INT"                    ,	18,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
-	{"MAC1_INT"                    ,	19,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_20_31"              ,	20,	12,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"DMAFI"                       ,	32,	2,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"DCNT"                        ,	34,	2,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"DTIME"                       ,	36,	2,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_38_47"              ,	38,	10,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"PIDBOF"                      ,	48,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"PSLDBOF"                     ,	49,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"POUT_ERR"                    ,	50,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"PIN_BP"                      ,	51,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"PGL_ERR"                     ,	52,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"PDI_ERR"                     ,	53,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"POP_ERR"                     ,	54,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"PINS_ERR"                    ,	55,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"SPRT0_ERR"                   ,	56,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"SPRT1_ERR"                   ,	57,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_58_59"              ,	58,	2,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"ILL_PAD"                     ,	60,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	906,	"R/W",	0,	0,	0ull,	0ull},
-	{"RML_TO"                      ,	0,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_1"                ,	1,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"BAR0_TO"                     ,	2,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"IOB2BIG"                     ,	3,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PCNT"                        ,	4,	1,	907,	"RO",	0,	0,	0ull,	0ull},
-	{"PTIME"                       ,	5,	1,	907,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"M0_UP_B0"                    ,	8,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"M0_UP_WI"                    ,	9,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"M0_UN_B0"                    ,	10,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"M0_UN_WI"                    ,	11,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"M1_UP_B0"                    ,	12,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"M1_UP_WI"                    ,	13,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"M1_UN_B0"                    ,	14,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"M1_UN_WI"                    ,	15,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"MIO_INT0"                    ,	16,	1,	907,	"RO",	0,	0,	0ull,	0ull},
-	{"MIO_INT1"                    ,	17,	1,	907,	"RO",	0,	0,	0ull,	0ull},
-	{"MAC0_INT"                    ,	18,	1,	907,	"RO",	0,	0,	0ull,	0ull},
-	{"MAC1_INT"                    ,	19,	1,	907,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_20_31"              ,	20,	12,	907,	"RAZ",	1,	1,	0,	0},
-	{"DMAFI"                       ,	32,	2,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"DCNT"                        ,	34,	2,	907,	"RO",	0,	0,	0ull,	0ull},
-	{"DTIME"                       ,	36,	2,	907,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_38_47"              ,	38,	10,	907,	"RAZ",	1,	1,	0,	0},
-	{"PIDBOF"                      ,	48,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PSLDBOF"                     ,	49,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"POUT_ERR"                    ,	50,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PIN_BP"                      ,	51,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PGL_ERR"                     ,	52,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PDI_ERR"                     ,	53,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"POP_ERR"                     ,	54,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PINS_ERR"                    ,	55,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"SPRT0_ERR"                   ,	56,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"SPRT1_ERR"                   ,	57,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_58_59"              ,	58,	2,	907,	"RAZ",	1,	1,	0,	0},
-	{"ILL_PAD"                     ,	60,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	907,	"RAZ",	1,	1,	0,	0},
-	{"DATA"                        ,	0,	64,	908,	"RO",	0,	1,	0ull,	0},
-	{"DATA"                        ,	0,	64,	909,	"RO",	0,	1,	0ull,	0},
-	{"P0_PCNT"                     ,	0,	8,	910,	"R/W",	0,	0,	128ull,	128ull},
-	{"P0_NCNT"                     ,	8,	8,	910,	"R/W",	0,	0,	16ull,	16ull},
-	{"P0_CCNT"                     ,	16,	8,	910,	"R/W",	0,	0,	128ull,	128ull},
-	{"P1_PCNT"                     ,	24,	8,	910,	"R/W",	0,	0,	128ull,	128ull},
-	{"P1_NCNT"                     ,	32,	8,	910,	"R/W",	0,	0,	16ull,	16ull},
-	{"P1_CCNT"                     ,	40,	8,	910,	"R/W",	0,	0,	128ull,	128ull},
-	{"P0_P_D"                      ,	48,	1,	910,	"R/W",	0,	0,	1ull,	1ull},
-	{"P0_N_D"                      ,	49,	1,	910,	"R/W",	0,	0,	1ull,	1ull},
-	{"P0_C_D"                      ,	50,	1,	910,	"R/W",	0,	0,	1ull,	1ull},
-	{"P1_P_D"                      ,	51,	1,	910,	"R/W",	0,	0,	1ull,	1ull},
-	{"P1_N_D"                      ,	52,	1,	910,	"R/W",	0,	0,	1ull,	1ull},
-	{"P1_C_D"                      ,	53,	1,	910,	"R/W",	0,	0,	1ull,	1ull},
-	{"RESERVED_54_63"              ,	54,	10,	910,	"RAZ",	1,	1,	0,	0},
-	{"NUM"                         ,	0,	8,	911,	"RO",	1,	1,	0,	0},
-	{"RESERVED_8_63"               ,	8,	56,	911,	"RAZ",	1,	1,	0,	0},
-	{"TIMER"                       ,	0,	10,	912,	"R/W",	0,	0,	0ull,	50ull},
-	{"MAX_WORD"                    ,	10,	4,	912,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_14_63"              ,	14,	50,	912,	"RAZ",	1,	1,	0,	0},
-	{"BA"                          ,	0,	30,	913,	"R/W",	0,	1,	0ull,	0},
-	{"RTYPE"                       ,	30,	2,	913,	"R/W",	0,	1,	0ull,	0},
-	{"WTYPE"                       ,	32,	2,	913,	"R/W",	0,	1,	0ull,	0},
-	{"ESW"                         ,	34,	2,	913,	"R/W",	0,	1,	0ull,	0},
-	{"ESR"                         ,	36,	2,	913,	"R/W",	0,	1,	0ull,	0},
-	{"NMERGE"                      ,	38,	1,	913,	"R/W",	0,	0,	0ull,	0ull},
-	{"PORT"                        ,	39,	3,	913,	"R/W",	0,	1,	0ull,	0},
-	{"ZERO"                        ,	42,	1,	913,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_43_63"              ,	43,	21,	913,	"RAZ",	1,	1,	0,	0},
-	{"ENB"                         ,	0,	64,	914,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
-	{"ENB"                         ,	0,	64,	915,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
-	{"ENB"                         ,	0,	64,	916,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
-	{"ENB"                         ,	0,	64,	917,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
-	{"INTR"                        ,	0,	64,	918,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"INTR"                        ,	0,	64,	919,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"INTR"                        ,	0,	64,	920,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"INTR"                        ,	0,	64,	921,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"MSI_INT"                     ,	0,	8,	922,	"R/W",	0,	1,	0ull,	0},
-	{"RD_INT"                      ,	8,	8,	922,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_16_63"              ,	16,	48,	922,	"RAZ",	1,	1,	0,	0},
-	{"CLR"                         ,	0,	64,	923,	"R/W",	0,	0,	0ull,	0ull},
-	{"CLR"                         ,	0,	64,	924,	"R/W",	0,	0,	0ull,	0ull},
-	{"CLR"                         ,	0,	64,	925,	"R/W",	0,	0,	0ull,	0ull},
-	{"CLR"                         ,	0,	64,	926,	"R/W",	0,	0,	0ull,	0ull},
-	{"SET"                         ,	0,	64,	927,	"R/W",	0,	0,	0ull,	0ull},
-	{"SET"                         ,	0,	64,	928,	"R/W",	0,	0,	0ull,	0ull},
-	{"SET"                         ,	0,	64,	929,	"R/W",	0,	0,	0ull,	0ull},
-	{"SET"                         ,	0,	64,	930,	"R/W",	0,	0,	0ull,	0ull},
-	{"MSI_INT"                     ,	0,	8,	931,	"R/W",	0,	1,	0ull,	0},
-	{"CIU_INT"                     ,	8,	8,	931,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_16_63"              ,	16,	48,	931,	"RAZ",	1,	1,	0,	0},
-	{"INTR"                        ,	0,	8,	932,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_8_63"               ,	8,	56,	932,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_7"                ,	0,	8,	933,	"RAZ",	1,	1,	0,	0},
-	{"INTR"                        ,	8,	8,	933,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_16_63"              ,	16,	48,	933,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_15"               ,	0,	16,	934,	"RAZ",	1,	1,	0,	0},
-	{"INTR"                        ,	16,	8,	934,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_24_63"              ,	24,	40,	934,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_23"               ,	0,	24,	935,	"RAZ",	1,	1,	0,	0},
-	{"INTR"                        ,	24,	8,	935,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	935,	"RAZ",	1,	1,	0,	0},
-	{"CNT"                         ,	0,	32,	936,	"R/W",	0,	0,	0ull,	0ull},
-	{"TIMER"                       ,	32,	22,	936,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_54_63"              ,	54,	10,	936,	"RO",	1,	1,	0,	0},
-	{"CNT"                         ,	0,	32,	937,	"R/W",	0,	0,	0ull,	0ull},
-	{"WMARK"                       ,	32,	32,	937,	"R/W",	0,	1,	4294967295ull,	0},
-	{"RESERVED_0_2"                ,	0,	3,	938,	"RAZ",	1,	1,	0,	0},
-	{"ADDR"                        ,	3,	61,	938,	"R/W",	0,	1,	0ull,	0},
-	{"DBELL"                       ,	0,	32,	939,	"R/W",	0,	0,	0ull,	0ull},
-	{"AOFF"                        ,	32,	32,	939,	"RO",	0,	1,	0ull,	0},
-	{"RSIZE"                       ,	0,	32,	940,	"R/W",	0,	1,	0ull,	0},
-	{"FCNT"                        ,	32,	5,	940,	"RO",	0,	1,	0ull,	0},
-	{"WRP"                         ,	37,	9,	940,	"RO",	0,	1,	0ull,	0},
-	{"RRP"                         ,	46,	9,	940,	"RO",	0,	1,	0ull,	0},
-	{"MAX"                         ,	55,	9,	940,	"RO",	0,	1,	16ull,	0},
-	{"NTAG"                        ,	0,	1,	941,	"R/W",	0,	1,	0ull,	0},
-	{"NTT"                         ,	1,	1,	941,	"R/W",	0,	1,	0ull,	0},
-	{"NGRP"                        ,	2,	1,	941,	"R/W",	0,	1,	0ull,	0},
-	{"NQOS"                        ,	3,	1,	941,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_4_5"                ,	4,	2,	941,	"R/W",	0,	1,	0ull,	0},
-	{"SKP_LEN"                     ,	6,	7,	941,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_13_13"              ,	13,	1,	941,	"R/W",	0,	1,	0ull,	0},
-	{"PAR_MODE"                    ,	14,	2,	941,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_16_20"              ,	16,	5,	941,	"R/W",	0,	1,	0ull,	0},
-	{"USE_IHDR"                    ,	21,	1,	941,	"R/W",	0,	1,	0ull,	0},
-	{"RNTAG"                       ,	22,	1,	941,	"R/W",	0,	1,	0ull,	0},
-	{"RNTT"                        ,	23,	1,	941,	"R/W",	0,	1,	0ull,	0},
-	{"RNGRP"                       ,	24,	1,	941,	"R/W",	0,	1,	0ull,	0},
-	{"RNQOS"                       ,	25,	1,	941,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_26_27"              ,	26,	2,	941,	"R/W",	0,	1,	0ull,	0},
-	{"RSKP_LEN"                    ,	28,	7,	941,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_35_35"              ,	35,	1,	941,	"RAZ",	0,	1,	0ull,	0},
-	{"RPARMODE"                    ,	36,	2,	941,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_38_42"              ,	38,	5,	941,	"RAZ",	0,	1,	0ull,	0},
-	{"PBP"                         ,	43,	1,	941,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_44_63"              ,	44,	20,	941,	"RAZ",	1,	1,	0,	0},
-	{"BSIZE"                       ,	0,	16,	942,	"R/W",	0,	1,	0ull,	0},
-	{"ISIZE"                       ,	16,	7,	942,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_23_63"              ,	23,	41,	942,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_3"                ,	0,	4,	943,	"RAZ",	1,	1,	0,	0},
-	{"ADDR"                        ,	4,	60,	943,	"R/W",	0,	1,	0ull,	0},
-	{"DBELL"                       ,	0,	32,	944,	"R/W",	0,	0,	0ull,	0ull},
-	{"AOFF"                        ,	32,	32,	944,	"RO",	0,	1,	0ull,	0},
-	{"RSIZE"                       ,	0,	32,	945,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	945,	"RO",	0,	1,	0ull,	0},
-	{"PORT"                        ,	0,	32,	946,	"R/W1C",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	946,	"RAZ",	1,	1,	0,	0},
-	{"PORT"                        ,	0,	32,	947,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	947,	"RAZ",	1,	1,	0,	0},
-	{"PKT_BP"                      ,	0,	4,	948,	"R/W",	0,	0,	15ull,	15ull},
-	{"RING_EN"                     ,	4,	1,	948,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_63"               ,	5,	59,	948,	"RAZ",	1,	1,	0,	0},
-	{"ES"                          ,	0,	64,	949,	"R/W",	0,	1,	0ull,	0},
-	{"NSR"                         ,	0,	32,	950,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	950,	"RAZ",	1,	1,	0,	0},
-	{"ROR"                         ,	0,	32,	951,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	951,	"RAZ",	1,	1,	0,	0},
-	{"DPTR"                        ,	0,	32,	952,	"R/W",	0,	0,	0ull,	4294967295ull},
+	{"OWORDP"                      ,	0,	64,	885,	"RO",	1,	1,	0,	0},
+	{"OWORDQ"                      ,	0,	64,	886,	"RO",	1,	1,	0,	0},
+	{"RWORD"                       ,	0,	64,	887,	"RO",	1,	1,	0,	0},
+	{"N0CREDS"                     ,	0,	4,	888,	"RO",	0,	0,	8ull,	0ull},
+	{"N1CREDS"                     ,	4,	4,	888,	"RO",	0,	0,	8ull,	0ull},
+	{"POWCREDS"                    ,	8,	2,	888,	"RO",	0,	0,	2ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	888,	"RAZ",	1,	1,	0,	0},
+	{"FPACREDS"                    ,	12,	2,	888,	"RO",	0,	0,	1ull,	0ull},
+	{"WCCREDS"                     ,	14,	2,	888,	"RO",	0,	0,	0ull,	0ull},
+	{"NIWIDX0"                     ,	16,	4,	888,	"RO",	1,	1,	0,	0},
+	{"NIRIDX0"                     ,	20,	4,	888,	"RO",	1,	1,	0,	0},
+	{"NIWIDX1"                     ,	24,	4,	888,	"RO",	1,	1,	0,	0},
+	{"NIRIDX1"                     ,	28,	4,	888,	"RO",	1,	1,	0,	0},
+	{"NIRVAL6"                     ,	32,	5,	888,	"RO",	1,	1,	0,	0},
+	{"NIRARB6"                     ,	37,	1,	888,	"RO",	1,	1,	0,	0},
+	{"NIRQUE6"                     ,	38,	2,	888,	"RO",	1,	1,	0,	0},
+	{"NIROPC6"                     ,	40,	3,	888,	"RO",	1,	1,	0,	0},
+	{"NIRVAL7"                     ,	43,	5,	888,	"RO",	1,	1,	0,	0},
+	{"NIRQUE7"                     ,	48,	2,	888,	"RO",	1,	1,	0,	0},
+	{"NIROPC7"                     ,	50,	3,	888,	"RO",	1,	1,	0,	0},
+	{"RESERVED_53_63"              ,	53,	11,	888,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	889,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	889,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	56,	8,	889,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	15,	890,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	890,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	891,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	891,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	891,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	892,	"RO",	1,	1,	0,	0},
+	{"MUL"                         ,	8,	8,	892,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	16,	1,	892,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	17,	1,	892,	"RO",	1,	1,	0,	0},
+	{"INI"                         ,	18,	1,	892,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	19,	1,	892,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_63"              ,	20,	44,	892,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	893,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	894,	"RAZ",	1,	1,	0,	0},
+	{"COEFFS"                      ,	0,	8,	895,	"R/W",	0,	0,	29ull,	29ull},
+	{"RESERVED_8_63"               ,	8,	56,	895,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	0,	16,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	16,	16,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	896,	"RAZ",	1,	1,	0,	0},
+	{"MEM"                         ,	0,	1,	897,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	897,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	897,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	898,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	898,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	898,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	898,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXP_ENT"                     ,	4,	1,	898,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENT_SEL"                     ,	5,	4,	898,	"R/W",	0,	0,	0ull,	0ull},
+	{"EER_VAL"                     ,	9,	1,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"EER_LCK"                     ,	10,	1,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	898,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	899,	"RO",	1,	1,	0,	0},
+	{"KEY"                         ,	0,	64,	900,	"WO",	0,	0,	0ull,	0ull},
+	{"DAT"                         ,	0,	64,	901,	"RO",	1,	1,	0,	0},
+	{"NCB_CMD"                     ,	0,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"MSI"                         ,	1,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI0_0"                      ,	2,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI0_1"                      ,	3,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI1_0"                      ,	4,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI1_1"                      ,	5,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_8"                ,	6,	3,	902,	"RAZ",	1,	1,	0,	0},
+	{"P2N1_P1"                     ,	9,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_P0"                     ,	10,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_N"                      ,	11,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C1"                     ,	12,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C0"                     ,	13,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P1"                     ,	14,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P0"                     ,	15,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_N"                      ,	16,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C1"                     ,	17,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C0"                     ,	18,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_24"              ,	19,	6,	902,	"RAZ",	1,	1,	0,	0},
+	{"CPL_P1"                      ,	25,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"CPL_P0"                      ,	26,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_O"                      ,	27,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_C"                      ,	28,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_O"                      ,	29,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_C"                      ,	30,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	902,	"RAZ",	1,	1,	0,	0},
+	{"WAIT_COM"                    ,	0,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_4"                ,	1,	4,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTLP_RO"                     ,	5,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTLP_RO"                     ,	7,	1,	903,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTA_MAP"                    ,	8,	2,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTB_MAP"                    ,	10,	2,	903,	"R/W",	0,	0,	1ull,	1ull},
+	{"INTC_MAP"                    ,	12,	2,	903,	"R/W",	0,	0,	2ull,	2ull},
+	{"INTD_MAP"                    ,	14,	2,	903,	"R/W",	0,	0,	3ull,	3ull},
+	{"WAITL_COM"                   ,	16,	1,	903,	"R/W",	0,	1,	0ull,	0},
+	{"DIS_PORT"                    ,	17,	1,	903,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTA"                        ,	18,	1,	903,	"RO",	0,	0,	1ull,	1ull},
+	{"INTB"                        ,	19,	1,	903,	"RO",	0,	0,	1ull,	1ull},
+	{"INTC"                        ,	20,	1,	903,	"RO",	0,	0,	1ull,	1ull},
+	{"INTD"                        ,	21,	1,	903,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	903,	"RAZ",	1,	1,	0,	0},
+	{"CHIP_REV"                    ,	0,	8,	904,	"RO",	1,	1,	0,	0},
+	{"P0_NTAGS"                    ,	8,	6,	904,	"R/W",	0,	0,	32ull,	32ull},
+	{"P1_NTAGS"                    ,	14,	6,	904,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_63"              ,	20,	44,	904,	"RAZ",	1,	1,	0,	0},
+	{"P0_FCNT"                     ,	0,	6,	905,	"RO",	0,	1,	0ull,	0},
+	{"P0_UCNT"                     ,	6,	16,	905,	"RO",	0,	1,	0ull,	0},
+	{"P1_FCNT"                     ,	22,	6,	905,	"RO",	0,	1,	0ull,	0},
+	{"P1_UCNT"                     ,	28,	16,	905,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	905,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	906,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	906,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	906,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	32,	907,	"R/W",	0,	1,	0ull,	0},
+	{"ADBG_SEL"                    ,	32,	1,	907,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	907,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	908,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	908,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	909,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	32,	909,	"R/W",	0,	1,	0ull,	0},
+	{"TIM"                         ,	0,	32,	910,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	910,	"RAZ",	1,	1,	0,	0},
+	{"RML_TO"                      ,	0,	1,	911,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	911,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	911,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	911,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	4,	1,	911,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	5,	1,	911,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	911,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UP_WI"                    ,	9,	1,	911,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_B0"                    ,	10,	1,	911,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_WI"                    ,	11,	1,	911,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_B0"                    ,	12,	1,	911,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_WI"                    ,	13,	1,	911,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_B0"                    ,	14,	1,	911,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_WI"                    ,	15,	1,	911,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT0"                    ,	16,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO_INT1"                    ,	17,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAFI"                       ,	32,	2,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	48,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_59"              ,	58,	2,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML_TO"                      ,	0,	1,	912,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	912,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	912,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	912,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	4,	1,	912,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	5,	1,	912,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	912,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UP_WI"                    ,	9,	1,	912,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_B0"                    ,	10,	1,	912,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_WI"                    ,	11,	1,	912,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_B0"                    ,	12,	1,	912,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_WI"                    ,	13,	1,	912,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_B0"                    ,	14,	1,	912,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_WI"                    ,	15,	1,	912,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT0"                    ,	16,	1,	912,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT1"                    ,	17,	1,	912,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC0_INT"                    ,	18,	1,	912,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC1_INT"                    ,	19,	1,	912,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_31"              ,	20,	12,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAFI"                       ,	32,	2,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	48,	1,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_59"              ,	58,	2,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML_TO"                      ,	0,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAR0_TO"                     ,	2,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB2BIG"                     ,	3,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT"                        ,	4,	1,	913,	"RO",	0,	0,	0ull,	0ull},
+	{"PTIME"                       ,	5,	1,	913,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UP_WI"                    ,	9,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UN_B0"                    ,	10,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UN_WI"                    ,	11,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UP_B0"                    ,	12,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UP_WI"                    ,	13,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UN_B0"                    ,	14,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UN_WI"                    ,	15,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO_INT0"                    ,	16,	1,	913,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO_INT1"                    ,	17,	1,	913,	"RO",	0,	0,	0ull,	0ull},
+	{"MAC0_INT"                    ,	18,	1,	913,	"RO",	0,	0,	0ull,	0ull},
+	{"MAC1_INT"                    ,	19,	1,	913,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	913,	"RAZ",	1,	1,	0,	0},
+	{"DMAFI"                       ,	32,	2,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	913,	"RO",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	913,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	913,	"RAZ",	1,	1,	0,	0},
+	{"PIDBOF"                      ,	48,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_59"              ,	58,	2,	913,	"RAZ",	1,	1,	0,	0},
+	{"ILL_PAD"                     ,	60,	1,	913,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	913,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	914,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	915,	"RO",	0,	1,	0ull,	0},
+	{"P0_PCNT"                     ,	0,	8,	916,	"R/W",	0,	0,	128ull,	128ull},
+	{"P0_NCNT"                     ,	8,	8,	916,	"R/W",	0,	0,	16ull,	16ull},
+	{"P0_CCNT"                     ,	16,	8,	916,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_PCNT"                     ,	24,	8,	916,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_NCNT"                     ,	32,	8,	916,	"R/W",	0,	0,	16ull,	16ull},
+	{"P1_CCNT"                     ,	40,	8,	916,	"R/W",	0,	0,	128ull,	128ull},
+	{"P0_P_D"                      ,	48,	1,	916,	"R/W",	0,	0,	1ull,	1ull},
+	{"P0_N_D"                      ,	49,	1,	916,	"R/W",	0,	0,	1ull,	1ull},
+	{"P0_C_D"                      ,	50,	1,	916,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_P_D"                      ,	51,	1,	916,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_N_D"                      ,	52,	1,	916,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_C_D"                      ,	53,	1,	916,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_54_63"              ,	54,	10,	916,	"RAZ",	1,	1,	0,	0},
+	{"NUM"                         ,	0,	8,	917,	"RO",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	917,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	10,	918,	"R/W",	0,	0,	0ull,	50ull},
+	{"MAX_WORD"                    ,	10,	4,	918,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	918,	"RAZ",	1,	1,	0,	0},
+	{"BA"                          ,	0,	30,	919,	"R/W",	0,	1,	0ull,	0},
+	{"RTYPE"                       ,	30,	2,	919,	"R/W",	0,	1,	0ull,	0},
+	{"WTYPE"                       ,	32,	2,	919,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	34,	2,	919,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	36,	2,	919,	"R/W",	0,	1,	0ull,	0},
+	{"NMERGE"                      ,	38,	1,	919,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORT"                        ,	39,	3,	919,	"R/W",	0,	1,	0ull,	0},
+	{"ZERO"                        ,	42,	1,	919,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	919,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	64,	920,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	921,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	922,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	923,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"INTR"                        ,	0,	64,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	925,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	926,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	927,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	928,	"R/W",	0,	1,	0ull,	0},
+	{"RD_INT"                      ,	8,	8,	928,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	928,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	64,	929,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	930,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	931,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	932,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	933,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	934,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	936,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	937,	"R/W",	0,	1,	0ull,	0},
+	{"CIU_INT"                     ,	8,	8,	937,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	937,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	8,	938,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	938,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	939,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	8,	8,	939,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	939,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	940,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	16,	8,	940,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	940,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	941,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	24,	8,	941,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	941,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	942,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	32,	22,	942,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	942,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	943,	"R/W",	0,	0,	0ull,	0ull},
+	{"WMARK"                       ,	32,	32,	943,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	944,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	61,	944,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	945,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	945,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	946,	"R/W",	0,	1,	0ull,	0},
+	{"FCNT"                        ,	32,	5,	946,	"RO",	0,	1,	0ull,	0},
+	{"WRP"                         ,	37,	9,	946,	"RO",	0,	1,	0ull,	0},
+	{"RRP"                         ,	46,	9,	946,	"RO",	0,	1,	0ull,	0},
+	{"MAX"                         ,	55,	9,	946,	"RO",	0,	1,	16ull,	0},
+	{"NTAG"                        ,	0,	1,	947,	"R/W",	0,	1,	0ull,	0},
+	{"NTT"                         ,	1,	1,	947,	"R/W",	0,	1,	0ull,	0},
+	{"NGRP"                        ,	2,	1,	947,	"R/W",	0,	1,	0ull,	0},
+	{"NQOS"                        ,	3,	1,	947,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	947,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	947,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_13"              ,	13,	1,	947,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	947,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_20"              ,	16,	5,	947,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	947,	"R/W",	0,	1,	0ull,	0},
+	{"RNTAG"                       ,	22,	1,	947,	"R/W",	0,	1,	0ull,	0},
+	{"RNTT"                        ,	23,	1,	947,	"R/W",	0,	1,	0ull,	0},
+	{"RNGRP"                       ,	24,	1,	947,	"R/W",	0,	1,	0ull,	0},
+	{"RNQOS"                       ,	25,	1,	947,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_27"              ,	26,	2,	947,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	947,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_35_35"              ,	35,	1,	947,	"RAZ",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	947,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_42"              ,	38,	5,	947,	"RAZ",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	947,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	947,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	16,	948,	"R/W",	0,	1,	0ull,	0},
+	{"ISIZE"                       ,	16,	7,	948,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	948,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	949,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	4,	60,	949,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	950,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	950,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	951,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	951,	"RO",	0,	1,	0ull,	0},
+	{"PORT"                        ,	0,	32,	952,	"R/W1C",	0,	1,	0ull,	0},
 	{"RESERVED_32_63"              ,	32,	32,	952,	"RAZ",	1,	1,	0,	0},
-	{"BP"                          ,	0,	32,	953,	"RO",	0,	1,	0ull,	0},
+	{"PORT"                        ,	0,	32,	953,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_32_63"              ,	32,	32,	953,	"RAZ",	1,	1,	0,	0},
-	{"CNT"                         ,	0,	32,	954,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	954,	"RO",	0,	1,	0ull,	0},
-	{"RD_CNT"                      ,	0,	32,	955,	"RO",	0,	1,	0ull,	0},
-	{"WR_CNT"                      ,	32,	32,	955,	"RO",	0,	1,	0ull,	0},
-	{"PP"                          ,	0,	64,	956,	"R/W",	0,	1,	0ull,	0},
-	{"ROR"                         ,	0,	1,	957,	"R/W",	0,	1,	0ull,	0},
-	{"ESR"                         ,	1,	2,	957,	"R/W",	0,	1,	0ull,	0},
-	{"NSR"                         ,	3,	1,	957,	"R/W",	0,	1,	0ull,	0},
-	{"USE_CSR"                     ,	4,	1,	957,	"R/W",	0,	0,	0ull,	1ull},
-	{"D_ROR"                       ,	5,	1,	957,	"R/W",	0,	1,	0ull,	0},
-	{"D_ESR"                       ,	6,	2,	957,	"R/W",	0,	1,	0ull,	0},
-	{"D_NSR"                       ,	8,	1,	957,	"R/W",	0,	1,	0ull,	0},
-	{"PBP_DHI"                     ,	9,	13,	957,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKT_RR"                      ,	22,	1,	957,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_23_63"              ,	23,	41,	957,	"RAZ",	1,	1,	0,	0},
-	{"ENB"                         ,	0,	32,	958,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_BP"                      ,	0,	4,	954,	"R/W",	0,	0,	15ull,	15ull},
+	{"RING_EN"                     ,	4,	1,	954,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	954,	"RAZ",	1,	1,	0,	0},
+	{"ES"                          ,	0,	64,	955,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	956,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	956,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	957,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	957,	"RAZ",	1,	1,	0,	0},
+	{"DPTR"                        ,	0,	32,	958,	"R/W",	0,	0,	0ull,	4294967295ull},
 	{"RESERVED_32_63"              ,	32,	32,	958,	"RAZ",	1,	1,	0,	0},
-	{"RDSIZE"                      ,	0,	64,	959,	"R/W",	0,	1,	0ull,	0},
-	{"IS_64B"                      ,	0,	32,	960,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	960,	"RAZ",	1,	1,	0,	0},
-	{"CNT"                         ,	0,	32,	961,	"R/W",	0,	1,	0ull,	0},
-	{"TIME"                        ,	32,	22,	961,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_54_63"              ,	54,	10,	961,	"RAZ",	1,	1,	0,	0},
-	{"IPTR"                        ,	0,	32,	962,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	962,	"RAZ",	1,	1,	0,	0},
-	{"BMODE"                       ,	0,	32,	963,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	963,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	32,	959,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	959,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	960,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	960,	"RO",	0,	1,	0ull,	0},
+	{"RD_CNT"                      ,	0,	32,	961,	"RO",	0,	1,	0ull,	0},
+	{"WR_CNT"                      ,	32,	32,	961,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	0,	64,	962,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	0,	1,	963,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	1,	2,	963,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	3,	1,	963,	"R/W",	0,	1,	0ull,	0},
+	{"USE_CSR"                     ,	4,	1,	963,	"R/W",	0,	0,	0ull,	1ull},
+	{"D_ROR"                       ,	5,	1,	963,	"R/W",	0,	1,	0ull,	0},
+	{"D_ESR"                       ,	6,	2,	963,	"R/W",	0,	1,	0ull,	0},
+	{"D_NSR"                       ,	8,	1,	963,	"R/W",	0,	1,	0ull,	0},
+	{"PBP_DHI"                     ,	9,	13,	963,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_RR"                      ,	22,	1,	963,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_23_63"              ,	23,	41,	963,	"RAZ",	1,	1,	0,	0},
 	{"ENB"                         ,	0,	32,	964,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_32_63"              ,	32,	32,	964,	"RAZ",	1,	1,	0,	0},
-	{"WMARK"                       ,	0,	32,	965,	"R/W",	0,	0,	0ull,	14ull},
-	{"RESERVED_32_63"              ,	32,	32,	965,	"RAZ",	1,	1,	0,	0},
-	{"PP"                          ,	0,	64,	966,	"R/W",	0,	1,	0ull,	0},
-	{"OUT_RST"                     ,	0,	32,	967,	"RO",	0,	1,	0ull,	0},
-	{"IN_RST"                      ,	32,	32,	967,	"RO",	0,	1,	0ull,	0},
-	{"ES"                          ,	0,	64,	968,	"R/W",	0,	1,	0ull,	0},
-	{"NSR"                         ,	0,	32,	969,	"R/W",	0,	1,	0ull,	0},
+	{"RDSIZE"                      ,	0,	64,	965,	"R/W",	0,	1,	0ull,	0},
+	{"IS_64B"                      ,	0,	32,	966,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	966,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	967,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	22,	967,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_54_63"              ,	54,	10,	967,	"RAZ",	1,	1,	0,	0},
+	{"IPTR"                        ,	0,	32,	968,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	968,	"RAZ",	1,	1,	0,	0},
+	{"BMODE"                       ,	0,	32,	969,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_32_63"              ,	32,	32,	969,	"RAZ",	1,	1,	0,	0},
-	{"ROR"                         ,	0,	32,	970,	"R/W",	0,	1,	0ull,	0},
+	{"ENB"                         ,	0,	32,	970,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_32_63"              ,	32,	32,	970,	"RAZ",	1,	1,	0,	0},
-	{"PORT"                        ,	0,	32,	971,	"R/W1C",	0,	1,	0ull,	0},
+	{"WMARK"                       ,	0,	32,	971,	"R/W",	0,	0,	0ull,	14ull},
 	{"RESERVED_32_63"              ,	32,	32,	971,	"RAZ",	1,	1,	0,	0},
-	{"PORT"                        ,	0,	32,	972,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	972,	"RAZ",	1,	1,	0,	0},
-	{"MRRS"                        ,	0,	3,	973,	"R/W",	0,	0,	2ull,	2ull},
-	{"BAR0_D"                      ,	3,	1,	973,	"R/W",	0,	0,	0ull,	0ull},
-	{"WIND_D"                      ,	4,	1,	973,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_63"               ,	5,	59,	973,	"RAZ",	1,	1,	0,	0},
-	{"DATA"                        ,	0,	64,	974,	"R/W",	0,	1,	0ull,	0},
-	{"DATA"                        ,	0,	64,	975,	"R/W",	0,	1,	0ull,	0},
-	{"CSR"                         ,	0,	39,	976,	"RO",	0,	1,	1ull,	0},
-	{"ARB"                         ,	39,	1,	976,	"RO",	0,	1,	0ull,	0},
-	{"CPL0"                        ,	40,	12,	976,	"RO",	0,	1,	1ull,	0},
-	{"CPL1"                        ,	52,	12,	976,	"RO",	0,	1,	1ull,	0},
-	{"NND"                         ,	0,	8,	977,	"RO",	0,	1,	1ull,	0},
-	{"NNP0"                        ,	8,	8,	977,	"RO",	0,	1,	1ull,	0},
-	{"CSM0"                        ,	16,	15,	977,	"RO",	0,	1,	1ull,	0},
-	{"CSM1"                        ,	31,	15,	977,	"RO",	0,	1,	1ull,	0},
-	{"RAC"                         ,	46,	1,	977,	"RO",	0,	1,	1ull,	0},
-	{"RESERVED_47_47"              ,	47,	1,	977,	"RAZ",	1,	1,	0,	0},
-	{"NNP1"                        ,	48,	8,	977,	"RO",	0,	1,	1ull,	0},
-	{"RESERVED_56_63"              ,	56,	8,	977,	"RAZ",	1,	1,	0,	0},
-	{"NSM0"                        ,	0,	13,	978,	"RO",	0,	1,	1ull,	0},
-	{"NSM1"                        ,	13,	13,	978,	"RO",	0,	1,	1ull,	0},
-	{"PSM0"                        ,	26,	15,	978,	"RO",	0,	1,	1ull,	0},
-	{"PSM1"                        ,	41,	15,	978,	"RO",	0,	1,	1ull,	0},
-	{"RESERVED_56_63"              ,	56,	8,	978,	"RAZ",	1,	1,	0,	0},
-	{"RD_ADDR"                     ,	0,	48,	979,	"R/W",	0,	1,	0ull,	0},
-	{"IOBIT"                       ,	48,	1,	979,	"R/W",	0,	0,	0ull,	0ull},
-	{"LD_CMD"                      ,	49,	2,	979,	"R/W",	0,	1,	3ull,	0},
-	{"RESERVED_51_63"              ,	51,	13,	979,	"RAZ",	1,	1,	0,	0},
-	{"RD_DATA"                     ,	0,	64,	980,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_0_2"                ,	0,	3,	981,	"RAZ",	1,	1,	0,	0},
-	{"WR_ADDR"                     ,	3,	45,	981,	"R/W",	0,	1,	0ull,	0},
-	{"IOBIT"                       ,	48,	1,	981,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	981,	"RAZ",	1,	1,	0,	0},
-	{"WR_DATA"                     ,	0,	64,	982,	"R/W",	0,	1,	0ull,	0},
-	{"WR_MASK"                     ,	0,	8,	983,	"R/W",	0,	0,	255ull,	0ull},
-	{"RESERVED_8_63"               ,	8,	56,	983,	"RAZ",	1,	1,	0,	0},
-	{"TIME"                        ,	0,	32,	984,	"R/W",	0,	0,	0ull,	2097152ull},
-	{"RESERVED_32_63"              ,	32,	32,	984,	"RAZ",	1,	1,	0,	0},
-	{"PHASE"                       ,	0,	8,	985,	"R/W",	0,	0,	100ull,	100ull},
-	{"SAMPLE"                      ,	8,	4,	985,	"R/W",	0,	0,	2ull,	2ull},
-	{"PREAMBLE"                    ,	12,	1,	985,	"R/W",	0,	0,	1ull,	1ull},
-	{"CLK_IDLE"                    ,	13,	1,	985,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_14_14"              ,	14,	1,	985,	"RAZ",	1,	1,	0,	0},
-	{"SAMPLE_MODE"                 ,	15,	1,	985,	"R/W",	0,	0,	0ull,	0ull},
-	{"SAMPLE_HI"                   ,	16,	5,	985,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_21_23"              ,	21,	3,	985,	"RAZ",	1,	1,	0,	0},
-	{"MODE"                        ,	24,	1,	985,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_25_63"              ,	25,	39,	985,	"RAZ",	1,	1,	0,	0},
-	{"REG_ADR"                     ,	0,	5,	986,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_5_7"                ,	5,	3,	986,	"RAZ",	1,	1,	0,	0},
-	{"PHY_ADR"                     ,	8,	5,	986,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_13_15"              ,	13,	3,	986,	"RAZ",	1,	1,	0,	0},
-	{"PHY_OP"                      ,	16,	2,	986,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_18_63"              ,	18,	46,	986,	"RAZ",	1,	1,	0,	0},
-	{"EN"                          ,	0,	1,	987,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_1_63"               ,	1,	63,	987,	"RAZ",	1,	1,	0,	0},
-	{"DAT"                         ,	0,	16,	988,	"RO",	0,	1,	0ull,	0},
-	{"VAL"                         ,	16,	1,	988,	"RO",	0,	1,	0ull,	0},
-	{"PENDING"                     ,	17,	1,	988,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_18_63"              ,	18,	46,	988,	"RAZ",	1,	1,	0,	0},
-	{"DAT"                         ,	0,	16,	989,	"R/W",	0,	1,	0ull,	0},
-	{"VAL"                         ,	16,	1,	989,	"RO",	0,	1,	0ull,	0},
-	{"PENDING"                     ,	17,	1,	989,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_18_63"              ,	18,	46,	989,	"RAZ",	1,	1,	0,	0},
-	{"NCTL"                        ,	0,	6,	990,	"R/W",	0,	0,	15ull,	15ull},
-	{"RESERVED_6_7"                ,	6,	2,	990,	"RAZ",	1,	1,	0,	0},
-	{"PCTL"                        ,	8,	6,	990,	"R/W",	0,	0,	19ull,	19ull},
-	{"RESERVED_14_63"              ,	14,	50,	990,	"RAZ",	1,	1,	0,	0},
-	{"DENY_BAR0"                   ,	0,	1,	991,	"R/W",	0,	0,	0ull,	0ull},
-	{"DENY_BAR1"                   ,	1,	1,	991,	"R/W",	0,	0,	0ull,	0ull},
-	{"DENY_BAR2"                   ,	2,	1,	991,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	991,	"RAZ",	1,	1,	0,	0},
-	{"ASSY_VEN"                    ,	0,	16,	992,	"R/W",	0,	0,	140ull,	0ull},
-	{"ASSY_ID"                     ,	16,	16,	992,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	992,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_15"               ,	0,	16,	993,	"RAZ",	1,	1,	0,	0},
-	{"ASSY_REV"                    ,	16,	16,	993,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	993,	"RAZ",	1,	1,	0,	0},
-	{"RP0_PID"                     ,	0,	2,	994,	"R/W",	0,	0,	0ull,	0ull},
-	{"RP1_PID"                     ,	2,	1,	994,	"R/W",	0,	0,	0ull,	0ull},
-	{"RP0_SID"                     ,	3,	2,	994,	"R/W",	0,	0,	0ull,	0ull},
-	{"RP1_SID"                     ,	5,	1,	994,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	994,	"RAZ",	1,	1,	0,	0},
-	{"OMSG"                        ,	0,	7,	995,	"RO",	0,	0,	0ull,	0ull},
-	{"IMSG"                        ,	7,	5,	995,	"RO",	0,	0,	0ull,	0ull},
-	{"RXBUF"                       ,	12,	2,	995,	"RO",	0,	0,	0ull,	0ull},
-	{"TXBUF"                       ,	14,	2,	995,	"RO",	0,	0,	0ull,	0ull},
-	{"OSPF"                        ,	16,	1,	995,	"RO",	0,	0,	0ull,	0ull},
-	{"ISPF"                        ,	17,	1,	995,	"RO",	0,	0,	0ull,	0ull},
-	{"OARB"                        ,	18,	2,	995,	"RO",	0,	0,	0ull,	0ull},
-	{"RXBUF2"                      ,	20,	2,	995,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	995,	"RAZ",	1,	1,	0,	0},
-	{"OPTRS"                       ,	24,	4,	995,	"RO",	0,	0,	0ull,	0ull},
-	{"OBULK"                       ,	28,	4,	995,	"RO",	0,	0,	0ull,	0ull},
-	{"RTN"                         ,	32,	2,	995,	"RO",	0,	0,	0ull,	0ull},
-	{"OFREE"                       ,	34,	1,	995,	"RO",	0,	0,	0ull,	0ull},
-	{"ITAG"                        ,	35,	1,	995,	"RO",	0,	0,	0ull,	0ull},
-	{"OTAG"                        ,	36,	2,	995,	"RO",	0,	0,	0ull,	0ull},
-	{"BELL"                        ,	38,	2,	995,	"RO",	0,	0,	0ull,	0ull},
-	{"CRAM"                        ,	40,	2,	995,	"RO",	0,	0,	0ull,	0ull},
-	{"MRAM"                        ,	42,	2,	995,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_44_63"              ,	44,	20,	995,	"RAZ",	1,	1,	0,	0},
-	{"MBOX"                        ,	0,	4,	996,	"R/W",	0,	1,	0ull,	0},
-	{"PRIO"                        ,	4,	4,	996,	"R/W",	0,	1,	0ull,	0},
-	{"LTTR"                        ,	8,	4,	996,	"R/W",	0,	1,	0ull,	0},
-	{"PRT_SEL"                     ,	12,	3,	996,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_15_15"              ,	15,	1,	996,	"RAZ",	1,	1,	0,	0},
-	{"RP0_PID"                     ,	16,	2,	996,	"R/W",	0,	0,	0ull,	0ull},
-	{"RP1_PID"                     ,	18,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
-	{"RP0_SID"                     ,	19,	2,	996,	"R/W",	0,	0,	0ull,	0ull},
-	{"RP1_SID"                     ,	21,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	996,	"RAZ",	1,	1,	0,	0},
-	{"RSP_THR"                     ,	24,	6,	996,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_30_30"              ,	30,	1,	996,	"RAZ",	1,	1,	0,	0},
-	{"TO_MODE"                     ,	31,	1,	996,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	996,	"RAZ",	1,	1,	0,	0},
-	{"TAG"                         ,	0,	32,	997,	"R/W",	0,	1,	0ull,	0},
-	{"TT"                          ,	32,	2,	997,	"R/W",	0,	1,	0ull,	0},
-	{"RS"                          ,	34,	1,	997,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_35_41"              ,	35,	7,	997,	"RAZ",	1,	1,	0,	0},
-	{"NTAG"                        ,	42,	1,	997,	"R/W",	0,	1,	0ull,	0},
-	{"NTT"                         ,	43,	1,	997,	"R/W",	0,	1,	0ull,	0},
-	{"NGRP"                        ,	44,	1,	997,	"R/W",	0,	1,	0ull,	0},
-	{"NQOS"                        ,	45,	1,	997,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_46_47"              ,	46,	2,	997,	"RAZ",	1,	1,	0,	0},
-	{"SL"                          ,	48,	7,	997,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_55_55"              ,	55,	1,	997,	"RAZ",	1,	1,	0,	0},
-	{"PM"                          ,	56,	2,	997,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_58_62"              ,	58,	5,	997,	"RAZ",	1,	1,	0,	0},
-	{"R"                           ,	63,	1,	997,	"R/W",	0,	1,	0ull,	0},
-	{"GRP0"                        ,	0,	4,	998,	"R/W",	0,	1,	0ull,	0},
-	{"QOS0"                        ,	4,	3,	998,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_7_7"                ,	7,	1,	998,	"RAZ",	1,	1,	0,	0},
-	{"GRP1"                        ,	8,	4,	998,	"R/W",	0,	1,	0ull,	0},
-	{"QOS1"                        ,	12,	3,	998,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_15_15"              ,	15,	1,	998,	"RAZ",	1,	1,	0,	0},
-	{"GRP2"                        ,	16,	4,	998,	"R/W",	0,	1,	0ull,	0},
-	{"QOS2"                        ,	20,	3,	998,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_23_23"              ,	23,	1,	998,	"RAZ",	1,	1,	0,	0},
-	{"GRP3"                        ,	24,	4,	998,	"R/W",	0,	1,	0ull,	0},
-	{"QOS3"                        ,	28,	3,	998,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_31_31"              ,	31,	1,	998,	"RAZ",	1,	1,	0,	0},
-	{"GRP4"                        ,	32,	4,	998,	"R/W",	0,	1,	0ull,	0},
-	{"QOS4"                        ,	36,	3,	998,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_39_39"              ,	39,	1,	998,	"RAZ",	1,	1,	0,	0},
-	{"GRP5"                        ,	40,	4,	998,	"R/W",	0,	1,	0ull,	0},
-	{"QOS5"                        ,	44,	3,	998,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_47_47"              ,	47,	1,	998,	"RAZ",	1,	1,	0,	0},
-	{"GRP6"                        ,	48,	4,	998,	"R/W",	0,	1,	0ull,	0},
-	{"QOS6"                        ,	52,	3,	998,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_55_55"              ,	55,	1,	998,	"RAZ",	1,	1,	0,	0},
-	{"GRP7"                        ,	56,	4,	998,	"R/W",	0,	1,	0ull,	0},
-	{"QOS7"                        ,	60,	3,	998,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_63_63"              ,	63,	1,	998,	"RAZ",	1,	1,	0,	0},
-	{"SID0"                        ,	0,	16,	999,	"RO",	0,	1,	0ull,	0},
-	{"LTTR0"                       ,	16,	2,	999,	"RO",	0,	1,	0ull,	0},
-	{"MBOX0"                       ,	18,	2,	999,	"RO",	0,	1,	0ull,	0},
-	{"SEG0"                        ,	20,	4,	999,	"RO",	0,	1,	0ull,	0},
-	{"DIS0"                        ,	24,	1,	999,	"RO",	0,	1,	0ull,	0},
-	{"TT0"                         ,	25,	1,	999,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_26_26"              ,	26,	1,	999,	"RAZ",	1,	1,	0,	0},
-	{"PRT0"                        ,	27,	1,	999,	"RO",	0,	1,	0ull,	0},
-	{"TOC0"                        ,	28,	1,	999,	"RO",	0,	1,	0ull,	0},
-	{"TOE0"                        ,	29,	1,	999,	"RO",	0,	1,	0ull,	0},
-	{"ERR0"                        ,	30,	1,	999,	"RO",	0,	1,	0ull,	0},
-	{"VAL0"                        ,	31,	1,	999,	"RO",	0,	1,	0ull,	0},
-	{"SID1"                        ,	32,	16,	999,	"RO",	0,	1,	0ull,	0},
-	{"LTTR1"                       ,	48,	2,	999,	"RO",	0,	1,	0ull,	0},
-	{"MBOX1"                       ,	50,	2,	999,	"RO",	0,	1,	0ull,	0},
-	{"SEG1"                        ,	52,	4,	999,	"RO",	0,	1,	0ull,	0},
-	{"DIS1"                        ,	56,	1,	999,	"RO",	0,	1,	0ull,	0},
-	{"TT1"                         ,	57,	1,	999,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_58_58"              ,	58,	1,	999,	"RAZ",	1,	1,	0,	0},
-	{"PRT1"                        ,	59,	1,	999,	"RO",	0,	1,	0ull,	0},
-	{"TOC1"                        ,	60,	1,	999,	"RO",	0,	1,	0ull,	0},
-	{"TOE1"                        ,	61,	1,	999,	"RO",	0,	1,	0ull,	0},
-	{"ERR1"                        ,	62,	1,	999,	"RO",	0,	1,	0ull,	0},
-	{"VAL1"                        ,	63,	1,	999,	"RO",	0,	1,	0ull,	0},
-	{"MAX_P0"                      ,	0,	6,	1000,	"R/W",	0,	1,	48ull,	0},
-	{"RESERVED_6_7"                ,	6,	2,	1000,	"RAZ",	1,	1,	0,	0},
-	{"MAX_P1"                      ,	8,	6,	1000,	"R/W",	0,	1,	48ull,	0},
-	{"RESERVED_14_15"              ,	14,	2,	1000,	"RAZ",	1,	1,	0,	0},
-	{"BUF_THR"                     ,	16,	4,	1000,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_20_30"              ,	20,	11,	1000,	"RAZ",	1,	1,	0,	0},
-	{"SP_VPORT"                    ,	31,	1,	1000,	"R/W",	0,	0,	1ull,	1ull},
-	{"MAX_S0"                      ,	32,	6,	1000,	"R/W",	0,	1,	48ull,	0},
-	{"RESERVED_38_39"              ,	38,	2,	1000,	"RAZ",	1,	1,	0,	0},
-	{"MAX_S1"                      ,	40,	6,	1000,	"R/W",	0,	1,	48ull,	0},
-	{"RESERVED_46_47"              ,	46,	2,	1000,	"RAZ",	1,	1,	0,	0},
-	{"MAX_TOT"                     ,	48,	6,	1000,	"R/W",	0,	1,	48ull,	0},
-	{"RESERVED_54_63"              ,	54,	10,	1000,	"RAZ",	1,	1,	0,	0},
-	{"PKO_RST"                     ,	0,	1,	1001,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_1_63"               ,	1,	63,	1001,	"RAZ",	1,	1,	0,	0},
-	{"PKO_RST"                     ,	0,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_30"               ,	1,	30,	1002,	"RAZ",	1,	1,	0,	0},
-	{"INT_SUM"                     ,	31,	1,	1002,	"RO",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	64,	972,	"R/W",	0,	1,	0ull,	0},
+	{"OUT_RST"                     ,	0,	32,	973,	"RO",	0,	1,	0ull,	0},
+	{"IN_RST"                      ,	32,	32,	973,	"RO",	0,	1,	0ull,	0},
+	{"ES"                          ,	0,	64,	974,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	975,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	975,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	976,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	976,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	977,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	977,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	978,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	978,	"RAZ",	1,	1,	0,	0},
+	{"MRRS"                        ,	0,	3,	979,	"R/W",	0,	0,	2ull,	2ull},
+	{"BAR0_D"                      ,	3,	1,	979,	"R/W",	0,	0,	0ull,	0ull},
+	{"WIND_D"                      ,	4,	1,	979,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	979,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	980,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	981,	"R/W",	0,	1,	0ull,	0},
+	{"CSR"                         ,	0,	39,	982,	"RO",	0,	1,	1ull,	0},
+	{"ARB"                         ,	39,	1,	982,	"RO",	0,	1,	0ull,	0},
+	{"CPL0"                        ,	40,	12,	982,	"RO",	0,	1,	1ull,	0},
+	{"CPL1"                        ,	52,	12,	982,	"RO",	0,	1,	1ull,	0},
+	{"NND"                         ,	0,	8,	983,	"RO",	0,	1,	1ull,	0},
+	{"NNP0"                        ,	8,	8,	983,	"RO",	0,	1,	1ull,	0},
+	{"CSM0"                        ,	16,	15,	983,	"RO",	0,	1,	1ull,	0},
+	{"CSM1"                        ,	31,	15,	983,	"RO",	0,	1,	1ull,	0},
+	{"RAC"                         ,	46,	1,	983,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	983,	"RAZ",	1,	1,	0,	0},
+	{"NNP1"                        ,	48,	8,	983,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	983,	"RAZ",	1,	1,	0,	0},
+	{"NSM0"                        ,	0,	13,	984,	"RO",	0,	1,	1ull,	0},
+	{"NSM1"                        ,	13,	13,	984,	"RO",	0,	1,	1ull,	0},
+	{"PSM0"                        ,	26,	15,	984,	"RO",	0,	1,	1ull,	0},
+	{"PSM1"                        ,	41,	15,	984,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	984,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	0,	48,	985,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	985,	"R/W",	0,	0,	0ull,	0ull},
+	{"LD_CMD"                      ,	49,	2,	985,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_51_63"              ,	51,	13,	985,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	986,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	987,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	3,	45,	987,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	987,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	987,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	988,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	989,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	989,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	990,	"R/W",	0,	0,	0ull,	2097152ull},
+	{"RESERVED_32_63"              ,	32,	32,	990,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	991,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	991,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	991,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	991,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	991,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	991,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	991,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	991,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	24,	1,	991,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	991,	"RAZ",	1,	1,	0,	0},
+	{"REG_ADR"                     ,	0,	5,	992,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	992,	"RAZ",	1,	1,	0,	0},
+	{"PHY_ADR"                     ,	8,	5,	992,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	992,	"RAZ",	1,	1,	0,	0},
+	{"PHY_OP"                      ,	16,	2,	992,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	992,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	993,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	993,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	994,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	994,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	994,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	994,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	995,	"R/W",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	995,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	995,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	995,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	996,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_6_7"                ,	6,	2,	996,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	8,	6,	996,	"R/W",	0,	0,	19ull,	19ull},
+	{"RESERVED_14_63"              ,	14,	50,	996,	"RAZ",	1,	1,	0,	0},
+	{"DENY_BAR0"                   ,	0,	1,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"DENY_BAR1"                   ,	1,	1,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"DENY_BAR2"                   ,	2,	1,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	997,	"RAZ",	1,	1,	0,	0},
+	{"ASSY_VEN"                    ,	0,	16,	998,	"R/W",	0,	0,	140ull,	0ull},
+	{"ASSY_ID"                     ,	16,	16,	998,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	998,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	999,	"RAZ",	1,	1,	0,	0},
+	{"ASSY_REV"                    ,	16,	16,	999,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	999,	"RAZ",	1,	1,	0,	0},
+	{"RP0_PID"                     ,	0,	2,	1000,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_PID"                     ,	2,	1,	1000,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP0_SID"                     ,	3,	2,	1000,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_SID"                     ,	5,	1,	1000,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1000,	"RAZ",	1,	1,	0,	0},
+	{"OMSG"                        ,	0,	7,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"IMSG"                        ,	7,	5,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"RXBUF"                       ,	12,	2,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"TXBUF"                       ,	14,	2,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"OSPF"                        ,	16,	1,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"ISPF"                        ,	17,	1,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"OARB"                        ,	18,	2,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"RXBUF2"                      ,	20,	2,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"OARB2"                       ,	22,	2,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"OPTRS"                       ,	24,	4,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"OBULK"                       ,	28,	4,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"RTN"                         ,	32,	2,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"OFREE"                       ,	34,	1,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"ITAG"                        ,	35,	1,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"OTAG"                        ,	36,	2,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"BELL"                        ,	38,	2,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"CRAM"                        ,	40,	2,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"MRAM"                        ,	42,	2,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_63"              ,	44,	20,	1001,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	1002,	"R/W",	0,	1,	0ull,	0},
+	{"PRIO"                        ,	4,	4,	1002,	"R/W",	0,	1,	0ull,	0},
+	{"LTTR"                        ,	8,	4,	1002,	"R/W",	0,	1,	0ull,	0},
+	{"PRT_SEL"                     ,	12,	3,	1002,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	1002,	"RAZ",	1,	1,	0,	0},
+	{"RP0_PID"                     ,	16,	2,	1002,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_PID"                     ,	18,	1,	1002,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP0_SID"                     ,	19,	2,	1002,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_SID"                     ,	21,	1,	1002,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1002,	"RAZ",	1,	1,	0,	0},
+	{"RSP_THR"                     ,	24,	6,	1002,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	1002,	"RAZ",	1,	1,	0,	0},
+	{"TO_MODE"                     ,	31,	1,	1002,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_32_63"              ,	32,	32,	1002,	"RAZ",	1,	1,	0,	0},
-	{"TXBELL"                      ,	0,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"BELL_ERR"                    ,	1,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"RXBELL"                      ,	2,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"MAINT_OP"                    ,	3,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"BAR_ERR"                     ,	4,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"DENY_WR"                     ,	5,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"SLI_ERR"                     ,	6,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"WR_DONE"                     ,	7,	1,	1003,	"R/W",	0,	0,	0ull,	0ull},
-	{"MCE_TX"                      ,	8,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"MCE_RX"                      ,	9,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"SOFT_TX"                     ,	10,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"SOFT_RX"                     ,	11,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"LOG_ERB"                     ,	12,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"PHY_ERB"                     ,	13,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"LINK_DWN"                    ,	14,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"LINK_UP"                     ,	15,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"OMSG0"                       ,	16,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"OMSG1"                       ,	17,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"OMSG_ERR"                    ,	18,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"PKO_ERR"                     ,	19,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"RTRY_ERR"                    ,	20,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"F_ERROR"                     ,	21,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"MAC_BUF"                     ,	22,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"DEGRADE"                     ,	23,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAIL"                        ,	24,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"TTL_TOUT"                    ,	25,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_26_63"              ,	26,	38,	1003,	"RAZ",	1,	1,	0,	0},
-	{"BE1"                         ,	0,	8,	1004,	"RO",	0,	1,	0ull,	0},
-	{"BE0"                         ,	8,	8,	1004,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_16_28"              ,	16,	13,	1004,	"RO",	1,	1,	0,	0},
-	{"STATUS"                      ,	29,	3,	1004,	"RO",	0,	1,	0ull,	0},
-	{"LENGTH"                      ,	32,	10,	1004,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_42_47"              ,	42,	6,	1004,	"RO",	1,	1,	0,	0},
-	{"TAG"                         ,	48,	8,	1004,	"RO",	0,	1,	0ull,	0},
-	{"TYPE"                        ,	56,	4,	1004,	"RO",	0,	1,	0ull,	0},
-	{"CMD"                         ,	60,	4,	1004,	"RO",	0,	1,	0ull,	0},
-	{"INFO1"                       ,	0,	64,	1005,	"RO",	0,	0,	0ull,	0ull},
-	{"INTR"                        ,	0,	1,	1006,	"RO",	0,	1,	0ull,	0},
-	{"LNS"                         ,	1,	1,	1006,	"RO",	0,	1,	0ull,	0},
-	{"RSRVD"                       ,	2,	30,	1006,	"RO",	0,	1,	0ull,	0},
-	{"LETTER"                      ,	32,	2,	1006,	"RO",	0,	1,	0ull,	0},
-	{"MBOX"                        ,	34,	2,	1006,	"RO",	0,	1,	0ull,	0},
-	{"XMBOX"                       ,	36,	4,	1006,	"RO",	0,	1,	0ull,	0},
-	{"DID"                         ,	40,	16,	1006,	"RO",	0,	1,	0ull,	0},
-	{"SSIZE"                       ,	56,	4,	1006,	"RO",	0,	1,	0ull,	0},
-	{"SIS"                         ,	60,	1,	1006,	"RO",	0,	1,	0ull,	0},
-	{"TT"                          ,	61,	1,	1006,	"RO",	0,	1,	0ull,	0},
-	{"PRIO"                        ,	62,	2,	1006,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_0_7"                ,	0,	8,	1007,	"RAZ",	1,	1,	0,	0},
-	{"OTHER"                       ,	8,	48,	1007,	"RO",	0,	1,	0ull,	0},
-	{"TYPE"                        ,	56,	4,	1007,	"RO",	0,	1,	0ull,	0},
-	{"TT"                          ,	60,	2,	1007,	"RO",	0,	1,	0ull,	0},
-	{"PRIO"                        ,	62,	2,	1007,	"RO",	0,	1,	0ull,	0},
-	{"TXBELL"                      ,	0,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"BELL_ERR"                    ,	1,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RXBELL"                      ,	2,	1,	1008,	"RO",	0,	0,	0ull,	0ull},
-	{"MAINT_OP"                    ,	3,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"BAR_ERR"                     ,	4,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"DENY_WR"                     ,	5,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"SLI_ERR"                     ,	6,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"WR_DONE"                     ,	7,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"MCE_TX"                      ,	8,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"MCE_RX"                      ,	9,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"SOFT_TX"                     ,	10,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"SOFT_RX"                     ,	11,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"LOG_ERB"                     ,	12,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PHY_ERB"                     ,	13,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"LINK_DWN"                    ,	14,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"LINK_UP"                     ,	15,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"OMSG0"                       ,	16,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"OMSG1"                       ,	17,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"OMSG_ERR"                    ,	18,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PKO_ERR"                     ,	19,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RTRY_ERR"                    ,	20,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"F_ERROR"                     ,	21,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"MAC_BUF"                     ,	22,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"DEGRAD"                      ,	23,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"FAIL"                        ,	24,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"TTL_TOUT"                    ,	25,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_26_30"              ,	26,	5,	1008,	"RAZ",	1,	1,	0,	0},
-	{"INT2_SUM"                    ,	31,	1,	1008,	"RO",	0,	0,	0ull,	0ull},
+	{"TAG"                         ,	0,	32,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"TT"                          ,	32,	2,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"RS"                          ,	34,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_35_41"              ,	35,	7,	1003,	"RAZ",	1,	1,	0,	0},
+	{"NTAG"                        ,	42,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"NTT"                         ,	43,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"NGRP"                        ,	44,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"NQOS"                        ,	45,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	1003,	"RAZ",	1,	1,	0,	0},
+	{"SL"                          ,	48,	7,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_55_55"              ,	55,	1,	1003,	"RAZ",	1,	1,	0,	0},
+	{"PM"                          ,	56,	2,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_58_62"              ,	58,	5,	1003,	"RAZ",	1,	1,	0,	0},
+	{"R"                           ,	63,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"GRP0"                        ,	0,	4,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"QOS0"                        ,	4,	3,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	1004,	"RAZ",	1,	1,	0,	0},
+	{"GRP1"                        ,	8,	4,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1"                        ,	12,	3,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	1004,	"RAZ",	1,	1,	0,	0},
+	{"GRP2"                        ,	16,	4,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2"                        ,	20,	3,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	1004,	"RAZ",	1,	1,	0,	0},
+	{"GRP3"                        ,	24,	4,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3"                        ,	28,	3,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_31_31"              ,	31,	1,	1004,	"RAZ",	1,	1,	0,	0},
+	{"GRP4"                        ,	32,	4,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4"                        ,	36,	3,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_39_39"              ,	39,	1,	1004,	"RAZ",	1,	1,	0,	0},
+	{"GRP5"                        ,	40,	4,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5"                        ,	44,	3,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	1004,	"RAZ",	1,	1,	0,	0},
+	{"GRP6"                        ,	48,	4,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6"                        ,	52,	3,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_55_55"              ,	55,	1,	1004,	"RAZ",	1,	1,	0,	0},
+	{"GRP7"                        ,	56,	4,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7"                        ,	60,	3,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_63_63"              ,	63,	1,	1004,	"RAZ",	1,	1,	0,	0},
+	{"SID0"                        ,	0,	16,	1005,	"RO",	0,	1,	0ull,	0},
+	{"LTTR0"                       ,	16,	2,	1005,	"RO",	0,	1,	0ull,	0},
+	{"MBOX0"                       ,	18,	2,	1005,	"RO",	0,	1,	0ull,	0},
+	{"SEG0"                        ,	20,	4,	1005,	"RO",	0,	1,	0ull,	0},
+	{"DIS0"                        ,	24,	1,	1005,	"RO",	0,	1,	0ull,	0},
+	{"TT0"                         ,	25,	1,	1005,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_26"              ,	26,	1,	1005,	"RAZ",	1,	1,	0,	0},
+	{"PRT0"                        ,	27,	1,	1005,	"RO",	0,	1,	0ull,	0},
+	{"TOC0"                        ,	28,	1,	1005,	"RO",	0,	1,	0ull,	0},
+	{"TOE0"                        ,	29,	1,	1005,	"RO",	0,	1,	0ull,	0},
+	{"ERR0"                        ,	30,	1,	1005,	"RO",	0,	1,	0ull,	0},
+	{"VAL0"                        ,	31,	1,	1005,	"RO",	0,	1,	0ull,	0},
+	{"SID1"                        ,	32,	16,	1005,	"RO",	0,	1,	0ull,	0},
+	{"LTTR1"                       ,	48,	2,	1005,	"RO",	0,	1,	0ull,	0},
+	{"MBOX1"                       ,	50,	2,	1005,	"RO",	0,	1,	0ull,	0},
+	{"SEG1"                        ,	52,	4,	1005,	"RO",	0,	1,	0ull,	0},
+	{"DIS1"                        ,	56,	1,	1005,	"RO",	0,	1,	0ull,	0},
+	{"TT1"                         ,	57,	1,	1005,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_58"              ,	58,	1,	1005,	"RAZ",	1,	1,	0,	0},
+	{"PRT1"                        ,	59,	1,	1005,	"RO",	0,	1,	0ull,	0},
+	{"TOC1"                        ,	60,	1,	1005,	"RO",	0,	1,	0ull,	0},
+	{"TOE1"                        ,	61,	1,	1005,	"RO",	0,	1,	0ull,	0},
+	{"ERR1"                        ,	62,	1,	1005,	"RO",	0,	1,	0ull,	0},
+	{"VAL1"                        ,	63,	1,	1005,	"RO",	0,	1,	0ull,	0},
+	{"MAX_P0"                      ,	0,	6,	1006,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	1006,	"RAZ",	1,	1,	0,	0},
+	{"MAX_P1"                      ,	8,	6,	1006,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	1006,	"RAZ",	1,	1,	0,	0},
+	{"BUF_THR"                     ,	16,	4,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_30"              ,	20,	11,	1006,	"RAZ",	1,	1,	0,	0},
+	{"SP_VPORT"                    ,	31,	1,	1006,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAX_S0"                      ,	32,	6,	1006,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_38_39"              ,	38,	2,	1006,	"RAZ",	1,	1,	0,	0},
+	{"MAX_S1"                      ,	40,	6,	1006,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	1006,	"RAZ",	1,	1,	0,	0},
+	{"MAX_TOT"                     ,	48,	6,	1006,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_54_63"              ,	54,	10,	1006,	"RAZ",	1,	1,	0,	0},
+	{"PKO_RST"                     ,	0,	1,	1007,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	1007,	"RAZ",	1,	1,	0,	0},
+	{"PKO_RST"                     ,	0,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_30"               ,	1,	30,	1008,	"RAZ",	1,	1,	0,	0},
+	{"INT_SUM"                     ,	31,	1,	1008,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_32_63"              ,	32,	32,	1008,	"RAZ",	1,	1,	0,	0},
-	{"RX_POL"                      ,	0,	4,	1009,	"R/W",	0,	0,	0ull,	0ull},
-	{"TX_POL"                      ,	4,	4,	1009,	"R/W",	0,	0,	0ull,	0ull},
-	{"PT_WIDTH"                    ,	8,	2,	1009,	"R/W",	0,	0,	3ull,	3ull},
-	{"TX_FLOW"                     ,	10,	1,	1009,	"R/W",	0,	0,	1ull,	1ull},
-	{"RESERVED_11_11"              ,	11,	1,	1009,	"RAZ",	1,	1,	0,	0},
-	{"A50"                         ,	12,	1,	1009,	"R/W",	0,	0,	1ull,	1ull},
-	{"A66"                         ,	13,	1,	1009,	"R/W",	0,	0,	1ull,	1ull},
-	{"RESERVED_14_31"              ,	14,	18,	1009,	"RAZ",	1,	1,	0,	0},
-	{"OPS"                         ,	32,	32,	1009,	"R/W",	0,	0,	64756ull,	64756ull},
-	{"RX_STAT"                     ,	0,	8,	1010,	"RO",	0,	0,	0ull,	0ull},
-	{"RX_INUSE"                    ,	8,	4,	1010,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_12_15"              ,	12,	4,	1010,	"RAZ",	1,	1,	0,	0},
-	{"RX_ENB"                      ,	16,	8,	1010,	"R/W",	0,	0,	255ull,	255ull},
-	{"RESERVED_24_31"              ,	24,	8,	1010,	"RAZ",	1,	1,	0,	0},
-	{"TX_STAT"                     ,	32,	8,	1010,	"RO",	0,	0,	0ull,	0ull},
-	{"TX_INUSE"                    ,	40,	4,	1010,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_44_47"              ,	44,	4,	1010,	"RAZ",	1,	1,	0,	0},
-	{"TX_ENB"                      ,	48,	8,	1010,	"R/W",	0,	0,	255ull,	255ull},
-	{"RESERVED_56_63"              ,	56,	8,	1010,	"RAZ",	1,	1,	0,	0},
-	{"ADDR"                        ,	0,	24,	1011,	"R/W",	0,	1,	0ull,	0},
-	{"OP"                          ,	24,	1,	1011,	"R/W",	0,	1,	0ull,	0},
-	{"PENDING"                     ,	25,	1,	1011,	"RO",	0,	1,	0ull,	0},
-	{"FAIL"                        ,	26,	1,	1011,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_27_31"              ,	27,	5,	1011,	"RAZ",	1,	1,	0,	0},
-	{"WR_DATA"                     ,	32,	32,	1011,	"R/W",	0,	1,	0ull,	0},
-	{"RD_DATA"                     ,	0,	32,	1012,	"RO",	0,	1,	0ull,	0},
-	{"VALID"                       ,	32,	1,	1012,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_33_63"              ,	33,	31,	1012,	"RAZ",	1,	1,	0,	0},
-	{"MCE"                         ,	0,	1,	1013,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	1013,	"RAZ",	1,	1,	0,	0},
-	{"RP0_PID"                     ,	0,	2,	1014,	"R/W",	0,	0,	0ull,	0ull},
-	{"RP1_PID"                     ,	2,	1,	1014,	"R/W",	0,	0,	0ull,	0ull},
-	{"RP0_SID"                     ,	3,	2,	1014,	"R/W",	0,	0,	0ull,	0ull},
-	{"RP1_SID"                     ,	5,	1,	1014,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	1014,	"RAZ",	1,	1,	0,	0},
-	{"W_RO"                        ,	8,	1,	1014,	"R/W",	0,	0,	0ull,	0ull},
-	{"RR_RO"                       ,	9,	1,	1014,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_63"              ,	10,	54,	1014,	"RAZ",	1,	1,	0,	0},
-	{"LTTR_MP"                     ,	0,	4,	1015,	"R/W",	0,	1,	15ull,	0},
-	{"LTTR_SP"                     ,	4,	4,	1015,	"R/W",	0,	1,	15ull,	0},
-	{"IDM_DID"                     ,	8,	1,	1015,	"R/W",	0,	1,	1ull,	0},
-	{"IDM_SIS"                     ,	9,	1,	1015,	"R/W",	0,	1,	1ull,	0},
-	{"IDM_TT"                      ,	10,	1,	1015,	"R/W",	0,	1,	1ull,	0},
-	{"RESERVED_11_14"              ,	11,	4,	1015,	"RAZ",	1,	1,	0,	0},
-	{"RTRY_EN"                     ,	15,	1,	1015,	"R/W",	0,	1,	0ull,	0},
-	{"RTRY_THR"                    ,	16,	16,	1015,	"R/W",	0,	1,	0ull,	0},
-	{"SILO_MAX"                    ,	32,	5,	1015,	"R/W",	0,	1,	16ull,	0},
-	{"RESERVED_37_62"              ,	37,	26,	1015,	"RAZ",	1,	1,	0,	0},
-	{"TESTMODE"                    ,	63,	1,	1015,	"R/W",	0,	0,	0ull,	0ull},
-	{"GOOD"                        ,	0,	16,	1016,	"R/W",	0,	1,	0ull,	0},
-	{"BAD"                         ,	16,	16,	1016,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	1016,	"RAZ",	1,	1,	0,	0},
-	{"ALL_PSD"                     ,	0,	1,	1017,	"R/W",	0,	1,	0ull,	0},
-	{"ALL_NMP"                     ,	1,	1,	1017,	"R/W",	0,	1,	0ull,	0},
-	{"ALL_FMP"                     ,	2,	1,	1017,	"R/W",	0,	1,	0ull,	0},
-	{"ALL_SP"                      ,	3,	1,	1017,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_PSD"                    ,	4,	1,	1017,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_NMP"                    ,	5,	1,	1017,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_FMP"                    ,	6,	1,	1017,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_SP"                     ,	7,	1,	1017,	"R/W",	0,	1,	0ull,	0},
-	{"ID_PSD"                      ,	8,	1,	1017,	"R/W",	0,	1,	0ull,	0},
-	{"ID_NMP"                      ,	9,	1,	1017,	"R/W",	0,	1,	0ull,	0},
-	{"ID_FMP"                      ,	10,	1,	1017,	"R/W",	0,	1,	0ull,	0},
-	{"ID_SP"                       ,	11,	1,	1017,	"R/W",	0,	1,	0ull,	0},
-	{"CTLR_NMP"                    ,	12,	1,	1017,	"R/W",	0,	1,	0ull,	0},
-	{"CTLR_FMP"                    ,	13,	1,	1017,	"R/W",	0,	1,	0ull,	0},
-	{"CTLR_SP"                     ,	14,	1,	1017,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_15_63"              ,	15,	49,	1017,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_0"                ,	0,	1,	1018,	"R/W",	0,	0,	0ull,	0ull},
-	{"ALL_NMP"                     ,	1,	1,	1018,	"R/W",	0,	1,	0ull,	0},
-	{"ALL_FMP"                     ,	2,	1,	1018,	"R/W",	0,	1,	0ull,	0},
-	{"ALL_SP"                      ,	3,	1,	1018,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_4_4"                ,	4,	1,	1018,	"R/W",	0,	0,	0ull,	0ull},
-	{"MBOX_NMP"                    ,	5,	1,	1018,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_FMP"                    ,	6,	1,	1018,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_SP"                     ,	7,	1,	1018,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_8_8"                ,	8,	1,	1018,	"R/W",	0,	0,	0ull,	0ull},
-	{"ID_NMP"                      ,	9,	1,	1018,	"R/W",	0,	1,	0ull,	0},
-	{"ID_FMP"                      ,	10,	1,	1018,	"R/W",	0,	1,	0ull,	0},
-	{"ID_SP"                       ,	11,	1,	1018,	"R/W",	0,	1,	0ull,	0},
-	{"CTLR_NMP"                    ,	12,	1,	1018,	"R/W",	0,	1,	0ull,	0},
-	{"CTLR_FMP"                    ,	13,	1,	1018,	"R/W",	0,	1,	0ull,	0},
-	{"CTLR_SP"                     ,	14,	1,	1018,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_15_63"              ,	15,	49,	1018,	"RAZ",	1,	1,	0,	0},
-	{"PORT"                        ,	0,	2,	1019,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_2_30"               ,	2,	29,	1019,	"RAZ",	1,	1,	0,	0},
-	{"ENABLE"                      ,	31,	1,	1019,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	1019,	"RAZ",	1,	1,	0,	0},
-	{"TOT_SILO"                    ,	0,	5,	1020,	"R/W",	0,	1,	16ull,	0},
-	{"RESERVED_5_63"               ,	5,	59,	1020,	"RAZ",	1,	1,	0,	0},
-	{"ALL_PSD"                     ,	0,	1,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"ALL_NMP"                     ,	1,	1,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"ALL_FMP"                     ,	2,	1,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"ALL_SP"                      ,	3,	1,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_PSD"                    ,	4,	1,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_NMP"                    ,	5,	1,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_FMP"                    ,	6,	1,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"MBOX_SP"                     ,	7,	1,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"ID_PSD"                      ,	8,	1,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"ID_NMP"                      ,	9,	1,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"ID_FMP"                      ,	10,	1,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"ID_SP"                       ,	11,	1,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"CTLR_NMP"                    ,	12,	1,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"CTLR_FMP"                    ,	13,	1,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"CTLR_SP"                     ,	14,	1,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"XMBOX_SP"                    ,	15,	1,	1021,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_16_63"              ,	16,	48,	1021,	"RAZ",	1,	1,	0,	0},
-	{"START_CNT"                   ,	0,	16,	1022,	"RO",	0,	1,	0ull,	0},
-	{"END_CNT"                     ,	16,	16,	1022,	"RO",	0,	1,	0ull,	0},
+	{"TXBELL"                      ,	0,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"BELL_ERR"                    ,	1,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBELL"                      ,	2,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAINT_OP"                    ,	3,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR_ERR"                     ,	4,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"DENY_WR"                     ,	5,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"SLI_ERR"                     ,	6,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"WR_DONE"                     ,	7,	1,	1009,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCE_TX"                      ,	8,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"MCE_RX"                      ,	9,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"SOFT_TX"                     ,	10,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"SOFT_RX"                     ,	11,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"LOG_ERB"                     ,	12,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"PHY_ERB"                     ,	13,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"LINK_DWN"                    ,	14,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"LINK_UP"                     ,	15,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"OMSG0"                       ,	16,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"OMSG1"                       ,	17,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"OMSG_ERR"                    ,	18,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO_ERR"                     ,	19,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"RTRY_ERR"                    ,	20,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"F_ERROR"                     ,	21,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC_BUF"                     ,	22,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"DEGRADE"                     ,	23,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAIL"                        ,	24,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"TTL_TOUT"                    ,	25,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZERO_PKT"                    ,	26,	1,	1009,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_63"              ,	27,	37,	1009,	"RAZ",	1,	1,	0,	0},
+	{"BE1"                         ,	0,	8,	1010,	"RO",	0,	1,	0ull,	0},
+	{"BE0"                         ,	8,	8,	1010,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_28"              ,	16,	13,	1010,	"RO",	1,	1,	0,	0},
+	{"STATUS"                      ,	29,	3,	1010,	"RO",	0,	1,	0ull,	0},
+	{"LENGTH"                      ,	32,	10,	1010,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	1010,	"RO",	1,	1,	0,	0},
+	{"TAG"                         ,	48,	8,	1010,	"RO",	0,	1,	0ull,	0},
+	{"TYPE"                        ,	56,	4,	1010,	"RO",	0,	1,	0ull,	0},
+	{"CMD"                         ,	60,	4,	1010,	"RO",	0,	1,	0ull,	0},
+	{"INFO1"                       ,	0,	64,	1011,	"RO",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	1,	1012,	"RO",	0,	1,	0ull,	0},
+	{"LNS"                         ,	1,	1,	1012,	"RO",	0,	1,	0ull,	0},
+	{"RSRVD"                       ,	2,	30,	1012,	"RO",	0,	1,	0ull,	0},
+	{"LETTER"                      ,	32,	2,	1012,	"RO",	0,	1,	0ull,	0},
+	{"MBOX"                        ,	34,	2,	1012,	"RO",	0,	1,	0ull,	0},
+	{"XMBOX"                       ,	36,	4,	1012,	"RO",	0,	1,	0ull,	0},
+	{"DID"                         ,	40,	16,	1012,	"RO",	0,	1,	0ull,	0},
+	{"SSIZE"                       ,	56,	4,	1012,	"RO",	0,	1,	0ull,	0},
+	{"SIS"                         ,	60,	1,	1012,	"RO",	0,	1,	0ull,	0},
+	{"TT"                          ,	61,	1,	1012,	"RO",	0,	1,	0ull,	0},
+	{"PRIO"                        ,	62,	2,	1012,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1013,	"RAZ",	1,	1,	0,	0},
+	{"OTHER"                       ,	8,	48,	1013,	"RO",	0,	1,	0ull,	0},
+	{"TYPE"                        ,	56,	4,	1013,	"RO",	0,	1,	0ull,	0},
+	{"TT"                          ,	60,	2,	1013,	"RO",	0,	1,	0ull,	0},
+	{"PRIO"                        ,	62,	2,	1013,	"RO",	0,	1,	0ull,	0},
+	{"TXBELL"                      ,	0,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BELL_ERR"                    ,	1,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBELL"                      ,	2,	1,	1014,	"RO",	0,	0,	0ull,	0ull},
+	{"MAINT_OP"                    ,	3,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAR_ERR"                     ,	4,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DENY_WR"                     ,	5,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SLI_ERR"                     ,	6,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WR_DONE"                     ,	7,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCE_TX"                      ,	8,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCE_RX"                      ,	9,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SOFT_TX"                     ,	10,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SOFT_RX"                     ,	11,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LOG_ERB"                     ,	12,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_ERB"                     ,	13,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LINK_DWN"                    ,	14,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LINK_UP"                     ,	15,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OMSG0"                       ,	16,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OMSG1"                       ,	17,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OMSG_ERR"                    ,	18,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO_ERR"                     ,	19,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTRY_ERR"                    ,	20,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"F_ERROR"                     ,	21,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAC_BUF"                     ,	22,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEGRAD"                      ,	23,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FAIL"                        ,	24,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TTL_TOUT"                    ,	25,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ZERO_PKT"                    ,	26,	1,	1014,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_30"              ,	27,	4,	1014,	"RAZ",	1,	1,	0,	0},
+	{"INT2_SUM"                    ,	31,	1,	1014,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1014,	"RAZ",	1,	1,	0,	0},
+	{"RX_POL"                      ,	0,	4,	1015,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_POL"                      ,	4,	4,	1015,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_WIDTH"                    ,	8,	2,	1015,	"R/W",	0,	0,	3ull,	3ull},
+	{"TX_FLOW"                     ,	10,	1,	1015,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_11_11"              ,	11,	1,	1015,	"RAZ",	1,	1,	0,	0},
+	{"A50"                         ,	12,	1,	1015,	"R/W",	0,	0,	1ull,	1ull},
+	{"A66"                         ,	13,	1,	1015,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	1015,	"RAZ",	1,	1,	0,	0},
+	{"OPS"                         ,	32,	32,	1015,	"R/W",	0,	0,	64756ull,	64756ull},
+	{"RX_STAT"                     ,	0,	8,	1016,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_INUSE"                    ,	8,	4,	1016,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_15"              ,	12,	4,	1016,	"RAZ",	1,	1,	0,	0},
+	{"RX_ENB"                      ,	16,	8,	1016,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_24_31"              ,	24,	8,	1016,	"RAZ",	1,	1,	0,	0},
+	{"TX_STAT"                     ,	32,	8,	1016,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_INUSE"                    ,	40,	4,	1016,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_44_47"              ,	44,	4,	1016,	"RAZ",	1,	1,	0,	0},
+	{"TX_ENB"                      ,	48,	8,	1016,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_56_63"              ,	56,	8,	1016,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	24,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	24,	1,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	25,	1,	1017,	"RO",	0,	1,	0ull,	0},
+	{"FAIL"                        ,	26,	1,	1017,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_27_31"              ,	27,	5,	1017,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	32,	32,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DATA"                     ,	0,	32,	1018,	"RO",	0,	1,	0ull,	0},
+	{"VALID"                       ,	32,	1,	1018,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	1018,	"RAZ",	1,	1,	0,	0},
+	{"MCE"                         ,	0,	1,	1019,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1019,	"RAZ",	1,	1,	0,	0},
+	{"RP0_PID"                     ,	0,	2,	1020,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_PID"                     ,	2,	1,	1020,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP0_SID"                     ,	3,	2,	1020,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_SID"                     ,	5,	1,	1020,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	1020,	"RAZ",	1,	1,	0,	0},
+	{"W_RO"                        ,	8,	1,	1020,	"R/W",	0,	0,	0ull,	0ull},
+	{"RR_RO"                       ,	9,	1,	1020,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1020,	"RAZ",	1,	1,	0,	0},
+	{"LTTR_MP"                     ,	0,	4,	1021,	"R/W",	0,	1,	15ull,	0},
+	{"LTTR_SP"                     ,	4,	4,	1021,	"R/W",	0,	1,	15ull,	0},
+	{"IDM_DID"                     ,	8,	1,	1021,	"R/W",	0,	1,	1ull,	0},
+	{"IDM_SIS"                     ,	9,	1,	1021,	"R/W",	0,	1,	1ull,	0},
+	{"IDM_TT"                      ,	10,	1,	1021,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_11_14"              ,	11,	4,	1021,	"RAZ",	1,	1,	0,	0},
+	{"RTRY_EN"                     ,	15,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"RTRY_THR"                    ,	16,	16,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"SILO_MAX"                    ,	32,	5,	1021,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_37_62"              ,	37,	26,	1021,	"RAZ",	1,	1,	0,	0},
+	{"TESTMODE"                    ,	63,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"GOOD"                        ,	0,	16,	1022,	"R/W",	0,	1,	0ull,	0},
+	{"BAD"                         ,	16,	16,	1022,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_32_63"              ,	32,	32,	1022,	"RAZ",	1,	1,	0,	0},
-	{"PRIORITY"                    ,	0,	2,	1023,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_2"                ,	2,	1,	1023,	"RAZ",	1,	1,	0,	0},
-	{"ID16"                        ,	3,	1,	1023,	"RO",	0,	0,	0ull,	0ull},
-	{"DEST_ID"                     ,	4,	1,	1023,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_7"                ,	5,	3,	1023,	"RAZ",	1,	1,	0,	0},
-	{"COUNT"                       ,	8,	8,	1023,	"RO",	0,	0,	0ull,	0ull},
-	{"SRC_ID"                      ,	16,	16,	1023,	"RO",	0,	0,	0ull,	0ull},
-	{"DATA"                        ,	32,	16,	1023,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	1023,	"RAZ",	1,	1,	0,	0},
-	{"SEQ"                         ,	0,	32,	1024,	"RO",	0,	1,	0ull,	0},
-	{"COUNT"                       ,	32,	8,	1024,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_40_63"              ,	40,	24,	1024,	"RAZ",	1,	1,	0,	0},
-	{"POST"                        ,	0,	8,	1025,	"RO",	0,	1,	128ull,	0},
-	{"N_POST"                      ,	8,	5,	1025,	"RO",	0,	1,	16ull,	0},
-	{"RESERVED_13_15"              ,	13,	3,	1025,	"RAZ",	1,	1,	0,	0},
-	{"COMP"                        ,	16,	8,	1025,	"RO",	0,	1,	128ull,	0},
-	{"MBOX"                        ,	24,	4,	1025,	"RO",	0,	1,	8ull,	0},
-	{"RESERVED_28_39"              ,	28,	12,	1025,	"RAZ",	1,	1,	0,	0},
-	{"RTN_PR1"                     ,	40,	8,	1025,	"RO",	0,	1,	0ull,	0},
-	{"RTN_PR2"                     ,	48,	8,	1025,	"RO",	0,	1,	0ull,	0},
-	{"RTN_PR3"                     ,	56,	8,	1025,	"RO",	0,	1,	0ull,	0},
-	{"IAOW_SEL"                    ,	0,	2,	1026,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_3"                ,	2,	2,	1026,	"RAZ",	1,	1,	0,	0},
-	{"ID16"                        ,	4,	1,	1026,	"R/W",	0,	0,	0ull,	0ull},
-	{"SRC_ID"                      ,	5,	1,	1026,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	1026,	"RAZ",	1,	1,	0,	0},
-	{"RD_PRIOR"                    ,	8,	2,	1026,	"R/W",	0,	0,	1ull,	1ull},
-	{"WR_PRIOR"                    ,	10,	2,	1026,	"R/W",	0,	0,	0ull,	0ull},
-	{"RD_OP"                       ,	12,	3,	1026,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_15_15"              ,	15,	1,	1026,	"RAZ",	1,	1,	0,	0},
-	{"WR_OP"                       ,	16,	3,	1026,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_19_63"              ,	19,	45,	1026,	"RAZ",	1,	1,	0,	0},
-	{"SEQ"                         ,	0,	32,	1027,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	1027,	"RAZ",	1,	1,	0,	0},
-	{"SRIO"                        ,	0,	1,	1028,	"RO",	1,	1,	0,	0},
-	{"ACCESS"                      ,	1,	1,	1028,	"RO",	1,	1,	0,	0},
-	{"RESERVED_2_63"               ,	2,	62,	1028,	"RAZ",	1,	1,	0,	0},
-	{"ITAG"                        ,	0,	5,	1029,	"RO",	0,	1,	16ull,	0},
+	{"ALL_PSD"                     ,	0,	1,	1023,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_NMP"                     ,	1,	1,	1023,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_FMP"                     ,	2,	1,	1023,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_SP"                      ,	3,	1,	1023,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_PSD"                    ,	4,	1,	1023,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_NMP"                    ,	5,	1,	1023,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_FMP"                    ,	6,	1,	1023,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_SP"                     ,	7,	1,	1023,	"R/W",	0,	1,	0ull,	0},
+	{"ID_PSD"                      ,	8,	1,	1023,	"R/W",	0,	1,	0ull,	0},
+	{"ID_NMP"                      ,	9,	1,	1023,	"R/W",	0,	1,	0ull,	0},
+	{"ID_FMP"                      ,	10,	1,	1023,	"R/W",	0,	1,	0ull,	0},
+	{"ID_SP"                       ,	11,	1,	1023,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_NMP"                    ,	12,	1,	1023,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_FMP"                    ,	13,	1,	1023,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_SP"                     ,	14,	1,	1023,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	1023,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	1024,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALL_NMP"                     ,	1,	1,	1024,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_FMP"                     ,	2,	1,	1024,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_SP"                      ,	3,	1,	1024,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_4"                ,	4,	1,	1024,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX_NMP"                    ,	5,	1,	1024,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_FMP"                    ,	6,	1,	1024,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_SP"                     ,	7,	1,	1024,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_8"                ,	8,	1,	1024,	"R/W",	0,	0,	0ull,	0ull},
+	{"ID_NMP"                      ,	9,	1,	1024,	"R/W",	0,	1,	0ull,	0},
+	{"ID_FMP"                      ,	10,	1,	1024,	"R/W",	0,	1,	0ull,	0},
+	{"ID_SP"                       ,	11,	1,	1024,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_NMP"                    ,	12,	1,	1024,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_FMP"                    ,	13,	1,	1024,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_SP"                     ,	14,	1,	1024,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	1024,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	2,	1025,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_30"               ,	2,	29,	1025,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	31,	1,	1025,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1025,	"RAZ",	1,	1,	0,	0},
+	{"TOT_SILO"                    ,	0,	5,	1026,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	1026,	"RAZ",	1,	1,	0,	0},
+	{"ALL_PSD"                     ,	0,	1,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_NMP"                     ,	1,	1,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_FMP"                     ,	2,	1,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_SP"                      ,	3,	1,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_PSD"                    ,	4,	1,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_NMP"                    ,	5,	1,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_FMP"                    ,	6,	1,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_SP"                     ,	7,	1,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"ID_PSD"                      ,	8,	1,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"ID_NMP"                      ,	9,	1,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"ID_FMP"                      ,	10,	1,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"ID_SP"                       ,	11,	1,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_NMP"                    ,	12,	1,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_FMP"                    ,	13,	1,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_SP"                     ,	14,	1,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"XMBOX_SP"                    ,	15,	1,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	1027,	"RAZ",	1,	1,	0,	0},
+	{"START_CNT"                   ,	0,	16,	1028,	"RO",	0,	1,	0ull,	0},
+	{"END_CNT"                     ,	16,	16,	1028,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1028,	"RAZ",	1,	1,	0,	0},
+	{"PRIORITY"                    ,	0,	2,	1029,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1029,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	3,	1,	1029,	"RO",	0,	0,	0ull,	0ull},
+	{"DEST_ID"                     ,	4,	1,	1029,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_5_7"                ,	5,	3,	1029,	"RAZ",	1,	1,	0,	0},
-	{"OTAG"                        ,	8,	5,	1029,	"RO",	0,	1,	16ull,	0},
-	{"RESERVED_13_15"              ,	13,	3,	1029,	"RAZ",	1,	1,	0,	0},
-	{"O_CLR"                       ,	16,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_17_63"              ,	17,	47,	1029,	"RAZ",	1,	1,	0,	0},
-	{"POST"                        ,	0,	8,	1030,	"R/W",	0,	0,	128ull,	128ull},
-	{"N_POST"                      ,	8,	5,	1030,	"R/W",	0,	0,	16ull,	16ull},
-	{"RESERVED_13_15"              ,	13,	3,	1030,	"RAZ",	1,	1,	0,	0},
-	{"COMP"                        ,	16,	8,	1030,	"R/W",	0,	0,	128ull,	128ull},
-	{"MBOX"                        ,	24,	4,	1030,	"R/W",	0,	0,	8ull,	8ull},
-	{"RESERVED_28_63"              ,	28,	36,	1030,	"RAZ",	1,	1,	0,	0},
-	{"PRIORITY"                    ,	0,	2,	1031,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_2"                ,	2,	1,	1031,	"RAZ",	1,	1,	0,	0},
-	{"ID16"                        ,	3,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
-	{"SRC_ID"                      ,	4,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_7"                ,	5,	3,	1031,	"RAZ",	1,	1,	0,	0},
-	{"PENDING"                     ,	8,	1,	1031,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_9_15"               ,	9,	7,	1031,	"RAZ",	1,	1,	0,	0},
-	{"DEST_ID"                     ,	16,	16,	1031,	"R/W",	0,	0,	0ull,	0ull},
-	{"DATA"                        ,	32,	16,	1031,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	1031,	"RAZ",	1,	1,	0,	0},
-	{"PRIORITY"                    ,	0,	2,	1032,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_2"                ,	2,	1,	1032,	"RAZ",	1,	1,	0,	0},
-	{"ID16"                        ,	3,	1,	1032,	"RO",	0,	0,	0ull,	0ull},
-	{"SRC_ID"                      ,	4,	1,	1032,	"RO",	0,	0,	0ull,	0ull},
-	{"RETRY"                       ,	5,	1,	1032,	"RO",	0,	0,	0ull,	0ull},
-	{"ERROR"                       ,	6,	1,	1032,	"RO",	0,	0,	0ull,	0ull},
-	{"TIMEOUT"                     ,	7,	1,	1032,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_8_15"               ,	8,	8,	1032,	"RAZ",	1,	1,	0,	0},
-	{"DEST_ID"                     ,	16,	16,	1032,	"RO",	0,	0,	0ull,	0ull},
-	{"DATA"                        ,	32,	16,	1032,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	1032,	"RAZ",	1,	1,	0,	0},
-	{"TX_TH0"                      ,	0,	4,	1033,	"R/W",	0,	0,	6ull,	3ull},
-	{"RESERVED_4_7"                ,	4,	4,	1033,	"RAZ",	1,	1,	0,	0},
-	{"TX_TH1"                      ,	8,	4,	1033,	"R/W",	0,	0,	4ull,	2ull},
-	{"RESERVED_12_15"              ,	12,	4,	1033,	"RAZ",	1,	1,	0,	0},
-	{"TX_TH2"                      ,	16,	4,	1033,	"R/W",	0,	0,	2ull,	1ull},
-	{"RESERVED_20_31"              ,	20,	12,	1033,	"RAZ",	1,	1,	0,	0},
-	{"TAG_TH0"                     ,	32,	5,	1033,	"R/W",	0,	0,	3ull,	3ull},
-	{"RESERVED_37_39"              ,	37,	3,	1033,	"RAZ",	1,	1,	0,	0},
-	{"TAG_TH1"                     ,	40,	5,	1033,	"R/W",	0,	0,	2ull,	2ull},
-	{"RESERVED_45_47"              ,	45,	3,	1033,	"RAZ",	1,	1,	0,	0},
-	{"TAG_TH2"                     ,	48,	5,	1033,	"R/W",	0,	0,	1ull,	1ull},
-	{"RESERVED_53_63"              ,	53,	11,	1033,	"RAZ",	1,	1,	0,	0},
-	{"EMPH"                        ,	0,	4,	1034,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	1034,	"RAZ",	1,	1,	0,	0},
-	{"S2M_PR0"                     ,	0,	8,	1035,	"RO",	0,	1,	0ull,	0},
-	{"S2M_PR1"                     ,	8,	8,	1035,	"RO",	0,	1,	0ull,	0},
-	{"S2M_PR2"                     ,	16,	8,	1035,	"RO",	0,	1,	0ull,	0},
-	{"S2M_PR3"                     ,	24,	8,	1035,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	1035,	"RAZ",	1,	1,	0,	0},
-	{"GOOD"                        ,	0,	16,	1036,	"R/W",	0,	1,	0ull,	0},
-	{"BAD"                         ,	16,	16,	1036,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_32_63"              ,	32,	32,	1036,	"RAZ",	1,	1,	0,	0},
-	{"ASSY_VEN"                    ,	0,	16,	1037,	"RO",	0,	0,	140ull,	0ull},
-	{"ASSY_ID"                     ,	16,	16,	1037,	"RO",	0,	0,	0ull,	0ull},
-	{"EXT_FPTR"                    ,	0,	16,	1038,	"RO",	0,	0,	256ull,	256ull},
-	{"ASSY_REV"                    ,	16,	16,	1038,	"RO",	0,	0,	0ull,	0ull},
-	{"ENABLE"                      ,	0,	1,	1039,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_1_2"                ,	1,	2,	1039,	"RAZ",	1,	1,	0,	0},
-	{"NCA"                         ,	3,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
-	{"ES"                          ,	4,	2,	1039,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_6_7"                ,	6,	2,	1039,	"RAZ",	1,	1,	0,	0},
-	{"LA"                          ,	8,	22,	1039,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_30_31"              ,	30,	2,	1039,	"RAZ",	1,	1,	0,	0},
-	{"FULL"                        ,	0,	1,	1040,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_31"               ,	1,	31,	1040,	"RAZ",	1,	1,	0,	0},
-	{"COMP_TAG"                    ,	0,	32,	1041,	"R/W",	0,	0,	0ull,	0ull},
-	{"MEMORY"                      ,	0,	1,	1042,	"R/W",	0,	0,	0ull,	1ull},
-	{"DOORBELL"                    ,	1,	1,	1042,	"R/W",	0,	0,	0ull,	1ull},
-	{"IMSG0"                       ,	2,	1,	1042,	"R/W",	0,	0,	0ull,	1ull},
-	{"IMSG1"                       ,	3,	1,	1042,	"R/W",	0,	0,	0ull,	1ull},
-	{"HALT"                        ,	4,	1,	1042,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_31"               ,	5,	27,	1042,	"RAZ",	1,	1,	0,	0},
-	{"VENDOR"                      ,	0,	16,	1043,	"RO",	0,	0,	140ull,	140ull},
-	{"DEVICE"                      ,	16,	16,	1043,	"RO",	0,	1,	144ull,	0},
-	{"REVISION"                    ,	0,	8,	1044,	"RO",	1,	1,	0,	0},
-	{"RESERVED_8_31"               ,	8,	24,	1044,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_1"                ,	0,	2,	1045,	"RAZ",	1,	1,	0,	0},
-	{"PORT_WR"                     ,	2,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
-	{"ATOM_SWP"                    ,	3,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
-	{"ATOM_CLR"                    ,	4,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
-	{"ATOM_SET"                    ,	5,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
-	{"ATOM_DEC"                    ,	6,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
-	{"ATOM_INC"                    ,	7,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
-	{"TESTSWAP"                    ,	8,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
-	{"COMPSWAP"                    ,	9,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
-	{"DOORBELL"                    ,	10,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
-	{"MSG"                         ,	11,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
-	{"WRITE_R"                     ,	12,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
-	{"SWRITE"                      ,	13,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
-	{"WRITE"                       ,	14,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
-	{"READ"                        ,	15,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
-	{"RESERVED_16_21"              ,	16,	6,	1045,	"RAZ",	1,	1,	0,	0},
-	{"TLB_INVS"                    ,	22,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
-	{"TLB_INV"                     ,	23,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
-	{"I_INVALD"                    ,	24,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
-	{"IO_READ"                     ,	25,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
-	{"D_FLUSH"                     ,	26,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
-	{"CASTOUT"                     ,	27,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
-	{"D_INVALD"                    ,	28,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
-	{"RD_OWN"                      ,	29,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
-	{"I_READ"                      ,	30,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
-	{"GSM_READ"                    ,	31,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
-	{"VALID"                       ,	0,	1,	1046,	"R/W0C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_3"                ,	1,	3,	1046,	"RAZ",	1,	1,	0,	0},
-	{"ERR_INFO"                    ,	4,	20,	1046,	"R/W",	0,	0,	0ull,	0ull},
-	{"ERR_TYPE"                    ,	24,	5,	1046,	"R/W",	0,	0,	0ull,	0ull},
-	{"INF_TYPE"                    ,	29,	3,	1046,	"R/W",	0,	0,	0ull,	0ull},
-	{"LNK_TOUT"                    ,	0,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
-	{"UNS_ACK"                     ,	1,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
-	{"DEL_ERR"                     ,	2,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
-	{"F_TOGGLE"                    ,	3,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
-	{"PROTERR"                     ,	4,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
-	{"BAD_ACK"                     ,	5,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_14"               ,	6,	9,	1047,	"RAZ",	1,	1,	0,	0},
-	{"INV_DATA"                    ,	15,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
-	{"INV_CHAR"                    ,	16,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
-	{"SIZE"                        ,	17,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKT_CRC"                     ,	18,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
-	{"OUT_ACK"                     ,	19,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
-	{"NACK"                        ,	20,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
-	{"UNS_ID"                      ,	21,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
-	{"CTL_CRC"                     ,	22,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_30"              ,	23,	8,	1047,	"R/W",	0,	0,	0ull,	0ull},
-	{"IMP_ERR"                     ,	31,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
-	{"RATE_CNT"                    ,	0,	8,	1048,	"R/W",	0,	1,	0ull,	0},
-	{"PK_RATE"                     ,	8,	8,	1048,	"R/W",	0,	1,	0ull,	0},
-	{"RATE_LIM"                    ,	16,	2,	1048,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_18_23"              ,	18,	6,	1048,	"RAZ",	1,	1,	0,	0},
-	{"ERR_BIAS"                    ,	24,	8,	1048,	"R/W",	0,	0,	128ull,	128ull},
-	{"LNK_TOUT"                    ,	0,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
-	{"UNS_ACK"                     ,	1,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
-	{"DEL_ERR"                     ,	2,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
-	{"F_TOGGLE"                    ,	3,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
-	{"PROTERR"                     ,	4,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
-	{"BAD_ACK"                     ,	5,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_14"               ,	6,	9,	1049,	"RAZ",	1,	1,	0,	0},
-	{"INV_DATA"                    ,	15,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
-	{"INV_CHAR"                    ,	16,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
-	{"SIZE"                        ,	17,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKT_CRC"                     ,	18,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
-	{"OUT_ACK"                     ,	19,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
-	{"NACK"                        ,	20,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
-	{"UNS_ID"                      ,	21,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
-	{"CTL_CRC"                     ,	22,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_30"              ,	23,	8,	1049,	"R/W",	0,	0,	0ull,	0ull},
-	{"IMP_ERR"                     ,	31,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_15"               ,	0,	16,	1050,	"RAZ",	1,	1,	0,	0},
-	{"DGRAD_TH"                    ,	16,	8,	1050,	"R/W",	0,	0,	255ull,	128ull},
-	{"FAIL_TH"                     ,	24,	8,	1050,	"R/W",	0,	0,	255ull,	255ull},
-	{"EF_ID"                       ,	0,	16,	1051,	"RO",	0,	0,	7ull,	7ull},
-	{"EF_PTR"                      ,	16,	16,	1051,	"RO",	0,	0,	0ull,	0ull},
-	{"ADDR"                        ,	0,	32,	1052,	"R/W",	0,	0,	0ull,	0ull},
-	{"XADDR"                       ,	0,	2,	1053,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_2"                ,	2,	1,	1053,	"RAZ",	1,	1,	0,	0},
-	{"ADDR"                        ,	3,	29,	1053,	"R/W",	0,	0,	0ull,	0ull},
-	{"CAPT_IDX"                    ,	0,	5,	1054,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_5"                ,	5,	1,	1054,	"R/W",	0,	0,	0ull,	0ull},
-	{"WDPTR"                       ,	6,	1,	1054,	"R/W",	0,	0,	0ull,	0ull},
-	{"TT"                          ,	7,	1,	1054,	"R/W",	0,	0,	0ull,	0ull},
-	{"SIZE"                        ,	8,	4,	1054,	"R/W",	0,	0,	0ull,	0ull},
-	{"STATUS"                      ,	12,	4,	1054,	"R/W",	0,	0,	0ull,	0ull},
-	{"EXTRA"                       ,	16,	8,	1054,	"R/W",	0,	0,	0ull,	0ull},
-	{"TTYPE"                       ,	24,	4,	1054,	"R/W",	0,	0,	0ull,	0ull},
-	{"FTYPE"                       ,	28,	4,	1054,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_14"               ,	0,	15,	1055,	"RAZ",	1,	1,	0,	0},
-	{"TT"                          ,	15,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
-	{"ID8"                         ,	16,	8,	1055,	"R/W",	0,	0,	0ull,	0ull},
-	{"ID16"                        ,	24,	8,	1055,	"R/W",	0,	0,	0ull,	0ull},
-	{"SRC_ID8"                     ,	0,	8,	1056,	"R/W",	0,	0,	0ull,	0ull},
-	{"SRC_ID16"                    ,	8,	8,	1056,	"R/W",	0,	0,	0ull,	0ull},
-	{"DST_ID8"                     ,	16,	8,	1056,	"R/W",	0,	0,	0ull,	0ull},
-	{"DST_ID16"                    ,	24,	8,	1056,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESP_SZ"                     ,	0,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_21"               ,	1,	21,	1057,	"R/W",	0,	0,	0ull,	0ull},
-	{"UNS_TRAN"                    ,	22,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
-	{"UNS_RESP"                    ,	23,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKT_TOUT"                    ,	24,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
-	{"MSG_TOUT"                    ,	25,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
-	{"ILL_TGT"                     ,	26,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
-	{"ILL_TRAN"                    ,	27,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
-	{"MSG_FMT"                     ,	28,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
-	{"GSM_ERR"                     ,	29,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
-	{"MSG_ERR"                     ,	30,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
-	{"IO_ERR"                      ,	31,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESP_SZ"                     ,	0,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_21"               ,	1,	21,	1058,	"R/W",	0,	0,	0ull,	0ull},
-	{"UNS_TRAN"                    ,	22,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
-	{"UNS_RESP"                    ,	23,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKT_TOUT"                    ,	24,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
-	{"MSG_TOUT"                    ,	25,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
-	{"ILL_TGT"                     ,	26,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
-	{"ILL_TRAN"                    ,	27,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
-	{"MSG_FMT"                     ,	28,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
-	{"GSM_ERR"                     ,	29,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
-	{"MSG_ERR"                     ,	30,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
-	{"IO_ERR"                      ,	31,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
-	{"CAPTURE"                     ,	0,	32,	1059,	"R/W",	0,	0,	0ull,	0ull},
-	{"CAPTURE"                     ,	0,	32,	1060,	"R/W",	0,	0,	0ull,	0ull},
-	{"CAPTURE"                     ,	0,	32,	1061,	"R/W",	0,	0,	0ull,	0ull},
-	{"CAPTURE"                     ,	0,	32,	1062,	"R/W",	0,	0,	0ull,	0ull},
-	{"HOSTID"                      ,	0,	16,	1063,	"R/W",	0,	0,	65535ull,	0ull},
-	{"RESERVED_16_31"              ,	16,	16,	1063,	"RAZ",	1,	1,	0,	0},
-	{"RX_SYNC"                     ,	0,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
-	{"TX_SYNC"                     ,	1,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
-	{"TX_FLOW"                     ,	2,	1,	1064,	"R/W",	0,	0,	1ull,	1ull},
-	{"RESERVED_3_19"               ,	3,	17,	1064,	"R/W",	0,	0,	0ull,	0ull},
-	{"TX_WM2"                      ,	20,	4,	1064,	"R/W",	0,	1,	2ull,	0},
-	{"TX_WM1"                      ,	24,	4,	1064,	"R/W",	0,	1,	3ull,	0},
-	{"TX_WM0"                      ,	28,	4,	1064,	"R/W",	0,	1,	4ull,	0},
-	{"RX_WM0"                      ,	0,	4,	1065,	"R/W",	0,	0,	4ull,	4ull},
-	{"RX_WM1"                      ,	4,	4,	1065,	"R/W",	0,	0,	3ull,	3ull},
-	{"RX_WM2"                      ,	8,	4,	1065,	"R/W",	0,	0,	2ull,	2ull},
-	{"RX_WM3"                      ,	12,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
-	{"TX_WM0"                      ,	16,	4,	1065,	"R/W",	0,	0,	4ull,	4ull},
-	{"TX_WM1"                      ,	20,	4,	1065,	"R/W",	0,	0,	3ull,	3ull},
-	{"TX_WM2"                      ,	24,	4,	1065,	"R/W",	0,	0,	2ull,	2ull},
-	{"TX_WM3"                      ,	28,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
-	{"PD_CTRL"                     ,	0,	32,	1066,	"R/W",	0,	0,	0ull,	0ull},
-	{"LN0_DIS"                     ,	0,	1,	1067,	"RO",	0,	0,	0ull,	0ull},
-	{"LN0_RX"                      ,	1,	3,	1067,	"RO",	0,	0,	0ull,	0ull},
-	{"LN1_DIS"                     ,	4,	1,	1067,	"RO",	0,	0,	0ull,	0ull},
-	{"LN1_RX"                      ,	5,	3,	1067,	"RO",	0,	0,	0ull,	0ull},
-	{"LN2_DIS"                     ,	8,	1,	1067,	"RO",	0,	0,	0ull,	0ull},
-	{"LN2_RX"                      ,	9,	3,	1067,	"RO",	0,	0,	0ull,	0ull},
-	{"LN3_DIS"                     ,	12,	1,	1067,	"RO",	0,	0,	0ull,	0ull},
-	{"LN3_RX"                      ,	13,	3,	1067,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_31"              ,	16,	16,	1067,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_26"               ,	0,	27,	1068,	"RAZ",	1,	1,	0,	0},
-	{"LOOPBACK"                    ,	27,	2,	1068,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_29_29"              ,	29,	1,	1068,	"R/W",	0,	0,	0ull,	0ull},
-	{"RX_RESET"                    ,	30,	1,	1068,	"R/W",	0,	0,	1ull,	1ull},
-	{"TX_RESET"                    ,	31,	1,	1068,	"R/W",	0,	0,	1ull,	1ull},
-	{"INIT_SM"                     ,	0,	10,	1069,	"RO",	0,	0,	0ull,	0ull},
-	{"RX_RDY"                      ,	10,	1,	1069,	"RO",	0,	0,	0ull,	0ull},
-	{"TX_RDY"                      ,	11,	1,	1069,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_12_31"              ,	12,	20,	1069,	"RAZ",	1,	1,	0,	0},
-	{"OVERWRT"                     ,	0,	1,	1070,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_31"               ,	1,	31,	1070,	"RAZ",	1,	1,	0,	0},
-	{"PKT_DATA"                    ,	0,	32,	1071,	"RO",	0,	0,	0ull,	0ull},
-	{"FIFO_ST"                     ,	0,	4,	1072,	"RO",	0,	0,	0ull,	0ull},
-	{"FULL"                        ,	4,	1,	1072,	"RO",	0,	0,	0ull,	0ull},
-	{"DROP_CNT"                    ,	5,	7,	1072,	"RO",	0,	1,	0ull,	0},
-	{"BUFFERS"                     ,	12,	4,	1072,	"RO",	0,	0,	0ull,	0ull},
-	{"OCTETS"                      ,	16,	16,	1072,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_15"               ,	0,	16,	1073,	"RAZ",	1,	1,	0,	0},
-	{"OCTETS"                      ,	16,	16,	1073,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKT_DATA"                    ,	0,	32,	1074,	"R/W",	0,	0,	0ull,	0ull},
-	{"FIFO_ST"                     ,	0,	4,	1075,	"RO",	0,	0,	0ull,	0ull},
-	{"FULL"                        ,	4,	1,	1075,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_11"               ,	5,	7,	1075,	"RAZ",	1,	1,	0,	0},
-	{"BUFFERS"                     ,	12,	4,	1075,	"RO",	0,	0,	0ull,	0ull},
-	{"OCTETS"                      ,	16,	16,	1075,	"RO",	0,	0,	0ull,	0ull},
-	{"STATUSN"                     ,	0,	3,	1076,	"RO",	0,	0,	0ull,	0ull},
-	{"STATUS1"                     ,	3,	1,	1076,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_5"                ,	4,	2,	1076,	"RAZ",	1,	1,	0,	0},
-	{"XTRAIN"                      ,	6,	1,	1076,	"RO",	0,	0,	0ull,	0ull},
-	{"XSYNC"                       ,	7,	1,	1076,	"RO",	0,	0,	0ull,	0ull},
-	{"DEC_ERR"                     ,	8,	4,	1076,	"RO",	0,	0,	0ull,	0ull},
-	{"RX_TRAIN"                    ,	12,	1,	1076,	"RO",	0,	0,	0ull,	0ull},
-	{"RX_SYNC"                     ,	13,	1,	1076,	"RO",	0,	0,	0ull,	0ull},
-	{"RX_ADAPT"                    ,	14,	1,	1076,	"RO",	0,	0,	1ull,	1ull},
-	{"RX_INV"                      ,	15,	1,	1076,	"RO",	0,	0,	0ull,	0ull},
-	{"RX_TYPE"                     ,	16,	2,	1076,	"RO",	0,	0,	0ull,	0ull},
-	{"TX_MODE"                     ,	18,	1,	1076,	"RO",	0,	0,	0ull,	0ull},
-	{"TX_TYPE"                     ,	19,	1,	1076,	"RO",	0,	0,	0ull,	0ull},
-	{"LANE"                        ,	20,	4,	1076,	"RO",	0,	0,	0ull,	0ull},
-	{"PORT"                        ,	24,	8,	1076,	"RO",	0,	0,	0ull,	0ull},
-	{"LCSBA"                       ,	0,	31,	1077,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_31_31"              ,	31,	1,	1077,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_20"               ,	0,	21,	1078,	"R/W",	0,	0,	0ull,	0ull},
-	{"LCSBA"                       ,	21,	11,	1078,	"R/W",	0,	0,	0ull,	0ull},
-	{"ADDR48"                      ,	0,	16,	1079,	"R/W",	0,	0,	0ull,	0ull},
-	{"ADDR64"                      ,	16,	16,	1079,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENABLE"                      ,	0,	1,	1080,	"R/W",	0,	0,	0ull,	0ull},
-	{"ADDR66"                      ,	1,	2,	1080,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_13"               ,	3,	11,	1080,	"RAZ",	1,	1,	0,	0},
-	{"ADDR32"                      ,	14,	18,	1080,	"R/W",	0,	0,	0ull,	0ull},
-	{"ADDR48"                      ,	0,	16,	1081,	"R/W",	0,	0,	0ull,	0ull},
-	{"ADDR64"                      ,	16,	16,	1081,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENABLE"                      ,	0,	1,	1082,	"R/W",	0,	0,	0ull,	0ull},
-	{"ADDR66"                      ,	1,	2,	1082,	"R/W",	0,	0,	0ull,	0ull},
-	{"BARSIZE"                     ,	3,	4,	1082,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_7_19"               ,	7,	13,	1082,	"RAZ",	1,	1,	0,	0},
-	{"ADDR32"                      ,	20,	12,	1082,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENABLE"                      ,	0,	1,	1083,	"R/W",	0,	0,	0ull,	0ull},
-	{"ADDR66"                      ,	1,	2,	1083,	"R/W",	0,	0,	0ull,	0ull},
-	{"CAX"                         ,	3,	1,	1083,	"R/W",	0,	0,	0ull,	0ull},
-	{"ESX"                         ,	4,	2,	1083,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_8"                ,	6,	3,	1083,	"RAZ",	1,	1,	0,	0},
-	{"ADDR48"                      ,	9,	7,	1083,	"R/W",	0,	0,	0ull,	0ull},
-	{"ADDR64"                      ,	16,	16,	1083,	"R/W",	0,	0,	0ull,	0ull},
-	{"LNK_RTRY"                    ,	0,	16,	1084,	"R/W",	0,	1,	0ull,	0},
-	{"TYPE_MRG"                    ,	16,	1,	1084,	"R/W",	0,	0,	1ull,	1ull},
-	{"EOP_MRG"                     ,	17,	1,	1084,	"R/W",	0,	0,	1ull,	1ull},
-	{"RX_SPF"                      ,	18,	1,	1084,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_19_31"              ,	19,	13,	1084,	"RAZ",	1,	1,	0,	0},
-	{"EX_ADDR"                     ,	0,	3,	1085,	"RO",	0,	0,	7ull,	7ull},
-	{"EX_FEAT"                     ,	3,	1,	1085,	"RO",	0,	0,	1ull,	1ull},
-	{"LG_TRAN"                     ,	4,	1,	1085,	"RO",	0,	0,	1ull,	1ull},
-	{"CRF"                         ,	5,	1,	1085,	"RO",	0,	0,	0ull,	0ull},
-	{"SUPPRESS"                    ,	6,	1,	1085,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_7_26"               ,	7,	20,	1085,	"RAZ",	1,	1,	0,	0},
-	{"MULT_PRT"                    ,	27,	1,	1085,	"RO",	0,	0,	0ull,	0ull},
-	{"SWITCHF"                     ,	28,	1,	1085,	"RO",	0,	0,	0ull,	0ull},
-	{"PROC"                        ,	29,	1,	1085,	"RO",	0,	0,	1ull,	1ull},
-	{"MEMORY"                      ,	30,	1,	1085,	"RO",	0,	0,	1ull,	1ull},
-	{"BRIDGE"                      ,	31,	1,	1085,	"RO",	0,	0,	0ull,	0ull},
-	{"EX_ADDR"                     ,	0,	3,	1086,	"R/W",	0,	0,	1ull,	1ull},
-	{"RESERVED_3_31"               ,	3,	29,	1086,	"RAZ",	1,	1,	0,	0},
-	{"PT_TYPE"                     ,	0,	1,	1087,	"RO",	0,	0,	1ull,	1ull},
-	{"PRT_LOCK"                    ,	1,	1,	1087,	"R/W",	0,	0,	0ull,	0ull},
-	{"DROP_PKT"                    ,	2,	1,	1087,	"R/W",	0,	0,	0ull,	0ull},
-	{"STP_PORT"                    ,	3,	1,	1087,	"R/W",	0,	0,	0ull,	0ull},
-	{"SUPPRESS"                    ,	4,	8,	1087,	"RO",	0,	0,	0ull,	0ull},
-	{"EX_STAT"                     ,	12,	2,	1087,	"RO",	0,	0,	0ull,	0ull},
-	{"EX_WIDTH"                    ,	14,	2,	1087,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_16"              ,	16,	1,	1087,	"RAZ",	1,	1,	0,	0},
-	{"ENUMB"                       ,	17,	1,	1087,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_18_18"              ,	18,	1,	1087,	"RAZ",	1,	1,	0,	0},
-	{"MCAST"                       ,	19,	1,	1087,	"R/W",	0,	0,	0ull,	0ull},
-	{"DIS_ERR"                     ,	20,	1,	1087,	"R/W",	0,	0,	0ull,	0ull},
-	{"I_ENABLE"                    ,	21,	1,	1087,	"R/W",	0,	0,	0ull,	1ull},
-	{"O_ENABLE"                    ,	22,	1,	1087,	"R/W",	0,	0,	0ull,	1ull},
-	{"DISABLE"                     ,	23,	1,	1087,	"R/W",	0,	0,	0ull,	0ull},
-	{"OV_WIDTH"                    ,	24,	3,	1087,	"R/W",	0,	0,	0ull,	0ull},
-	{"IT_WIDTH"                    ,	27,	3,	1087,	"RO",	0,	1,	0ull,	0},
-	{"PT_WIDTH"                    ,	30,	2,	1087,	"RO",	0,	0,	3ull,	3ull},
-	{"EMPH_EN"                     ,	0,	1,	1088,	"R/W",	0,	0,	0ull,	0ull},
-	{"TX_EMPH"                     ,	1,	1,	1088,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_15"               ,	2,	14,	1088,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENB_625G"                    ,	16,	1,	1088,	"R/W",	0,	0,	0ull,	0ull},
-	{"SUP_625G"                    ,	17,	1,	1088,	"RO",	0,	0,	0ull,	0ull},
-	{"ENB_500G"                    ,	18,	1,	1088,	"R/W",	1,	1,	0,	0},
-	{"SUB_500G"                    ,	19,	1,	1088,	"RO",	1,	1,	0,	0},
-	{"ENB_312G"                    ,	20,	1,	1088,	"R/W",	1,	1,	0,	0},
-	{"SUP_312G"                    ,	21,	1,	1088,	"RO",	1,	1,	0,	0},
-	{"ENB_250G"                    ,	22,	1,	1088,	"R/W",	1,	1,	0,	0},
-	{"SUP_250G"                    ,	23,	1,	1088,	"RO",	1,	1,	0,	0},
-	{"ENB_125G"                    ,	24,	1,	1088,	"R/W",	1,	1,	0,	0},
-	{"SUP_125G"                    ,	25,	1,	1088,	"RO",	1,	1,	0,	0},
-	{"BAUD_ENB"                    ,	26,	1,	1088,	"R/W",	0,	0,	0ull,	0ull},
-	{"BAUD_SUP"                    ,	27,	1,	1088,	"RO",	0,	0,	0ull,	0ull},
-	{"SEL_BAUD"                    ,	28,	4,	1088,	"RO",	0,	1,	0ull,	0},
-	{"PT_UINIT"                    ,	0,	1,	1089,	"RO",	0,	0,	0ull,	0ull},
-	{"PT_OK"                       ,	1,	1,	1089,	"RO",	0,	0,	0ull,	0ull},
-	{"PT_ERROR"                    ,	2,	1,	1089,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_3"                ,	3,	1,	1089,	"RAZ",	1,	1,	0,	0},
-	{"PT_WRITE"                    ,	4,	1,	1089,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_7"                ,	5,	3,	1089,	"RAZ",	1,	1,	0,	0},
-	{"I_SM_ERR"                    ,	8,	1,	1089,	"RO",	0,	0,	0ull,	0ull},
-	{"I_ERROR"                     ,	9,	1,	1089,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"I_SM_RET"                    ,	10,	1,	1089,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_11_15"              ,	11,	5,	1089,	"RAZ",	1,	1,	0,	0},
-	{"O_SM_ERR"                    ,	16,	1,	1089,	"RO",	0,	0,	0ull,	0ull},
-	{"O_ERROR"                     ,	17,	1,	1089,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"O_SM_RET"                    ,	18,	1,	1089,	"RO",	0,	0,	0ull,	0ull},
-	{"O_RTRIED"                    ,	19,	1,	1089,	"RO",	0,	0,	0ull,	0ull},
-	{"O_RETRY"                     ,	20,	1,	1089,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_21_23"              ,	21,	3,	1089,	"RAZ",	1,	1,	0,	0},
-	{"O_DGRAD"                     ,	24,	1,	1089,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"O_FAIL"                      ,	25,	1,	1089,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PKT_DROP"                    ,	26,	1,	1089,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_27_31"              ,	27,	5,	1089,	"RAZ",	1,	1,	0,	0},
-	{"CMD"                         ,	0,	3,	1090,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_3_31"               ,	3,	29,	1090,	"RAZ",	1,	1,	0,	0},
-	{"STATUS"                      ,	0,	5,	1091,	"RO",	0,	1,	0ull,	0},
-	{"ACKID"                       ,	5,	6,	1091,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_11_30"              ,	11,	20,	1091,	"RAZ",	1,	1,	0,	0},
-	{"VALID"                       ,	31,	1,	1091,	"RO",	0,	1,	0ull,	0},
-	{"O_ACKID"                     ,	0,	6,	1092,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_6_7"                ,	6,	2,	1092,	"RAZ",	1,	1,	0,	0},
-	{"E_ACKID"                     ,	8,	6,	1092,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_14_23"              ,	14,	10,	1092,	"RAZ",	1,	1,	0,	0},
-	{"I_ACKID"                     ,	24,	6,	1092,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_30_31"              ,	30,	2,	1092,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_28"               ,	0,	29,	1093,	"RAZ",	1,	1,	0,	0},
-	{"DISCOVER"                    ,	29,	1,	1093,	"R/W",	0,	0,	0ull,	1ull},
-	{"MENABLE"                     ,	30,	1,	1093,	"R/W",	1,	0,	0,	1ull},
-	{"HOST"                        ,	31,	1,	1093,	"R/W",	1,	1,	0,	0},
-	{"RESERVED_0_7"                ,	0,	8,	1094,	"RAZ",	1,	1,	0,	0},
-	{"TIMEOUT"                     ,	8,	24,	1094,	"R/W",	0,	0,	16777215ull,	0ull},
-	{"EF_ID"                       ,	0,	16,	1095,	"RO",	0,	0,	1ull,	0ull},
-	{"EF_PTR"                      ,	16,	16,	1095,	"RO",	0,	0,	4096ull,	0ull},
-	{"RESERVED_0_7"                ,	0,	8,	1096,	"RAZ",	1,	1,	0,	0},
-	{"TIMEOUT"                     ,	8,	24,	1096,	"R/W",	0,	0,	16777215ull,	0ull},
-	{"RESERVED_0_7"                ,	0,	8,	1097,	"RAZ",	1,	1,	0,	0},
-	{"TIMEOUT"                     ,	8,	24,	1097,	"R/W",	0,	0,	16777215ull,	0ull},
-	{"ID16"                        ,	0,	16,	1098,	"R/W",	0,	0,	65535ull,	0ull},
-	{"ID8"                         ,	16,	8,	1098,	"R/W",	0,	0,	255ull,	0ull},
-	{"RESERVED_24_31"              ,	24,	8,	1098,	"RAZ",	1,	1,	0,	0},
-	{"ENABLE16"                    ,	0,	1,	1099,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENABLE8"                     ,	1,	1,	1099,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_31"               ,	2,	30,	1099,	"RAZ",	1,	1,	0,	0},
-	{"ID16"                        ,	0,	16,	1100,	"R/W",	0,	0,	65535ull,	0ull},
-	{"ID8"                         ,	16,	8,	1100,	"R/W",	0,	0,	255ull,	0ull},
-	{"RESERVED_24_31"              ,	24,	8,	1100,	"RAZ",	1,	1,	0,	0},
-	{"EF_ID"                       ,	0,	16,	1101,	"RO",	0,	0,	13ull,	13ull},
-	{"EF_PTR"                      ,	16,	16,	1101,	"RO",	0,	0,	8192ull,	0ull},
-	{"RESERVED_0_1"                ,	0,	2,	1102,	"RAZ",	1,	1,	0,	0},
-	{"PORT_WR"                     ,	2,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
-	{"ATOM_SWP"                    ,	3,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
-	{"ATOM_CLR"                    ,	4,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
-	{"ATOM_SET"                    ,	5,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
-	{"ATOM_DEC"                    ,	6,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
-	{"ATOM_INC"                    ,	7,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
-	{"TESTSWAP"                    ,	8,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
-	{"COMPSWAP"                    ,	9,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
-	{"DOORBELL"                    ,	10,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
-	{"MSG"                         ,	11,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
-	{"WRITE_R"                     ,	12,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
-	{"SWRITE"                      ,	13,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
-	{"WRITE"                       ,	14,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
-	{"READ"                        ,	15,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
-	{"RESERVED_16_21"              ,	16,	6,	1102,	"RAZ",	1,	1,	0,	0},
-	{"TLB_INVS"                    ,	22,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
-	{"TLB_INV"                     ,	23,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
-	{"I_INVALD"                    ,	24,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
-	{"IO_READ"                     ,	25,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
-	{"D_FLUSH"                     ,	26,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
-	{"CASTOUT"                     ,	27,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
-	{"D_INVALD"                    ,	28,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
-	{"RD_OWN"                      ,	29,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
-	{"I_READ"                      ,	30,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
-	{"GSM_READ"                    ,	31,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
-	{"DROP_CNT"                    ,	0,	16,	1103,	"RO",	0,	1,	0ull,	0},
-	{"DROP"                        ,	16,	1,	1103,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	1103,	"RAZ",	1,	1,	0,	0},
-	{"INTERVAL"                    ,	0,	22,	1104,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	1104,	"RAZ",	1,	1,	0,	0},
-	{"COUNT"                       ,	24,	22,	1104,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_46_46"              ,	46,	1,	1104,	"RAZ",	1,	1,	0,	0},
-	{"ENA"                         ,	47,	1,	1104,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	1104,	"RAZ",	1,	1,	0,	0},
-	{"BSIZE"                       ,	0,	20,	1105,	"RO",	1,	0,	0,	0ull},
-	{"BASE"                        ,	20,	31,	1105,	"RO",	1,	0,	0,	0ull},
-	{"BUCKET"                      ,	51,	13,	1105,	"RO",	1,	0,	0,	0ull},
-	{"BUCKET"                      ,	0,	7,	1106,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_7_7"                ,	7,	1,	1106,	"RO",	1,	0,	0,	0ull},
-	{"CSIZE"                       ,	8,	13,	1106,	"RO",	1,	0,	0,	0ull},
-	{"CPOOL"                       ,	21,	3,	1106,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_24_63"              ,	24,	40,	1106,	"RAZ",	1,	1,	0,	0},
-	{"RING"                        ,	0,	4,	1107,	"R/W",	0,	0,	0ull,	0ull},
-	{"NUM_BUCKETS"                 ,	4,	20,	1107,	"R/W",	0,	0,	0ull,	0ull},
-	{"FIRST_BUCKET"                ,	24,	31,	1107,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_55_63"              ,	55,	9,	1107,	"RAZ",	1,	1,	0,	0},
-	{"RING"                        ,	0,	4,	1108,	"R/W",	0,	0,	0ull,	0ull},
-	{"INTERVAL"                    ,	4,	22,	1108,	"R/W",	0,	0,	0ull,	0ull},
-	{"WORDS_PER_CHUNK"             ,	26,	13,	1108,	"R/W",	0,	0,	0ull,	0ull},
-	{"POOL"                        ,	39,	3,	1108,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENABLE"                      ,	42,	1,	1108,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_43_63"              ,	43,	21,	1108,	"RAZ",	1,	1,	0,	0},
-	{"CTL"                         ,	0,	1,	1109,	"RO",	1,	0,	0,	0ull},
-	{"NCB"                         ,	1,	1,	1109,	"RO",	1,	0,	0,	0ull},
-	{"STA"                         ,	2,	2,	1109,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	1109,	"RAZ",	1,	1,	0,	0},
-	{"MASK"                        ,	0,	16,	1110,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	1110,	"RAZ",	1,	1,	0,	0},
-	{"ENABLE_TIMERS"               ,	0,	1,	1111,	"R/W",	0,	0,	0ull,	0ull},
-	{"ENABLE_DWB"                  ,	1,	1,	1111,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESET"                       ,	2,	1,	1111,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	1111,	"RAZ",	1,	1,	0,	0},
-	{"MASK"                        ,	0,	16,	1112,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	1112,	"RAZ",	1,	1,	0,	0},
-	{"INDEX"                       ,	0,	8,	1113,	"R/W",	0,	0,	0ull,	0ull},
-	{"INC"                         ,	8,	8,	1113,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	1113,	"RAZ",	1,	1,	0,	0},
-	{"TDF"                         ,	0,	1,	1114,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	1114,	"RAZ",	0,	0,	0ull,	0ull},
-	{"ENA"                         ,	0,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
-	{"WRAP"                        ,	1,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
-	{"TRIG_CTL"                    ,	2,	2,	1115,	"R/W",	0,	0,	0ull,	0ull},
-	{"TIME_GRN"                    ,	4,	3,	1115,	"R/W",	0,	0,	0ull,	0ull},
-	{"FULL_THR"                    ,	7,	2,	1115,	"R/W",	0,	0,	0ull,	0ull},
-	{"CIU_TRG"                     ,	9,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
-	{"CIU_THR"                     ,	10,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
-	{"MCD0_TRG"                    ,	11,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
-	{"MCD0_THR"                    ,	12,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
-	{"MCD0_ENA"                    ,	13,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
-	{"IGNORE_O"                    ,	14,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
-	{"CLKALWAYS"                   ,	15,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
-	{"RDAT_MD"                     ,	16,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_17_63"              ,	17,	47,	1115,	"RAZ",	0,	0,	0ull,	0ull},
-	{"WPTR"                        ,	0,	8,	1116,	"RO",	0,	0,	0ull,	0ull},
-	{"RPTR"                        ,	8,	8,	1116,	"RO",	0,	0,	0ull,	0ull},
-	{"CYCLES"                      ,	16,	48,	1116,	"RO",	0,	0,	0ull,	0ull},
-	{"WPTR"                        ,	0,	10,	1117,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_11"              ,	10,	2,	1117,	"RAZ",	1,	1,	0,	0},
-	{"RPTR"                        ,	12,	10,	1117,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	1117,	"RAZ",	1,	1,	0,	0},
-	{"CYCLES"                      ,	24,	40,	1117,	"RO",	0,	0,	0ull,	0ull},
-	{"ADR"                         ,	0,	38,	1118,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_38_63"              ,	38,	26,	1118,	"RAZ",	0,	0,	0ull,	0ull},
-	{"ADR"                         ,	0,	38,	1119,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_38_63"              ,	38,	26,	1119,	"RAZ",	0,	0,	0ull,	0ull},
-	{"NOP"                         ,	0,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"LDT"                         ,	1,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"LDI"                         ,	2,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"PL2"                         ,	3,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"RPL2"                        ,	4,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"DWB"                         ,	5,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_7"                ,	6,	2,	1120,	"R/W",	0,	0,	0ull,	0ull},
-	{"LDD"                         ,	8,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"PSL1"                        ,	9,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_10_14"              ,	10,	5,	1120,	"R/W",	0,	0,	0ull,	0ull},
-	{"IOBDMA"                      ,	15,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"STF"                         ,	16,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"STT"                         ,	17,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"STP"                         ,	18,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"STC"                         ,	19,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"STFIL1"                      ,	20,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"STTIL1"                      ,	21,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAS32"                       ,	22,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAS64"                       ,	23,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"WBIL2I"                      ,	24,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"LTGL2I"                      ,	25,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"STGL2I"                      ,	26,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_27_27"              ,	27,	1,	1120,	"R/W",	0,	0,	0ull,	0ull},
-	{"INVL2"                       ,	28,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"WBIL2"                       ,	29,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"WBL2"                        ,	30,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"LCKL2"                       ,	31,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD8"                      ,	32,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD16"                     ,	33,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD32"                     ,	34,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD64"                     ,	35,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST8"                      ,	36,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST16"                     ,	37,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST32"                     ,	38,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST64"                     ,	39,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET8"                        ,	40,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET16"                       ,	41,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET32"                       ,	42,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET64"                       ,	43,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR8"                        ,	44,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR16"                       ,	45,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR32"                       ,	46,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR64"                       ,	47,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR8"                       ,	48,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR16"                      ,	49,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR32"                      ,	50,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR64"                      ,	51,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR8"                       ,	52,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR16"                      ,	53,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR32"                      ,	54,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR64"                      ,	55,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_56_57"              ,	56,	2,	1120,	"R/W",	0,	0,	0ull,	0ull},
-	{"FAA32"                       ,	58,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAA64"                       ,	59,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_60_61"              ,	60,	2,	1120,	"R/W",	0,	0,	0ull,	0ull},
-	{"SAA32"                       ,	62,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"SAA64"                       ,	63,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
-	{"MIO"                         ,	0,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL3"                    ,	1,	2,	1121,	"R/W",	0,	0,	0ull,	3ull},
-	{"SLI"                         ,	3,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
-	{"KEY"                         ,	4,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
-	{"FPA"                         ,	5,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
-	{"DFA"                         ,	6,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
-	{"ZIP"                         ,	7,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
-	{"RNG"                         ,	8,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
-	{"IPD"                         ,	9,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
-	{"PKO"                         ,	10,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL2"                    ,	11,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
-	{"POW"                         ,	12,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
-	{"USB0"                        ,	13,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
-	{"RAD"                         ,	14,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL"                     ,	15,	12,	1121,	"R/W",	0,	0,	0ull,	4095ull},
-	{"DPI"                         ,	27,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL4"                    ,	28,	2,	1121,	"R/W",	0,	0,	0ull,	3ull},
-	{"FAU"                         ,	30,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL5"                    ,	31,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_32_63"              ,	32,	32,	1121,	"RAZ",	0,	0,	0ull,	0ull},
-	{"PP"                          ,	0,	8,	1122,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_8_15"               ,	8,	8,	1122,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKI"                         ,	16,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKO"                         ,	17,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
-	{"IOBREQ"                      ,	18,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
-	{"DWB"                         ,	19,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_20_63"              ,	20,	44,	1122,	"R/W",	0,	0,	0ull,	0ull},
-	{"CIU_TRG"                     ,	0,	1,	1123,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"CIU_THR"                     ,	1,	1,	1123,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"MCD0_TRG"                    ,	2,	1,	1123,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"MCD0_THR"                    ,	3,	1,	1123,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	1123,	"RAZ",	0,	0,	0ull,	0ull},
-	{"DATA"                        ,	0,	64,	1124,	"RO",	0,	0,	0ull,	0ull},
-	{"DATA"                        ,	0,	5,	1125,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_63"               ,	5,	59,	1125,	"RAZ",	0,	0,	0ull,	0ull},
-	{"ADR"                         ,	0,	38,	1126,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_38_63"              ,	38,	26,	1126,	"RAZ",	0,	0,	0ull,	0ull},
-	{"ADR"                         ,	0,	38,	1127,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_38_63"              ,	38,	26,	1127,	"RAZ",	0,	0,	0ull,	0ull},
-	{"NOP"                         ,	0,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"LDT"                         ,	1,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"LDI"                         ,	2,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"PL2"                         ,	3,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"RPL2"                        ,	4,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"DWB"                         ,	5,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_7"                ,	6,	2,	1128,	"R/W",	0,	0,	0ull,	0ull},
-	{"LDD"                         ,	8,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"PSL1"                        ,	9,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_10_14"              ,	10,	5,	1128,	"R/W",	0,	0,	0ull,	0ull},
-	{"IOBDMA"                      ,	15,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"STF"                         ,	16,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"STT"                         ,	17,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"STP"                         ,	18,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"STC"                         ,	19,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"STFIL1"                      ,	20,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"STTIL1"                      ,	21,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAS32"                       ,	22,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAS64"                       ,	23,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"WBIL2I"                      ,	24,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"LTGL2I"                      ,	25,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"STGL2I"                      ,	26,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_27_27"              ,	27,	1,	1128,	"R/W",	0,	0,	0ull,	0ull},
-	{"INVL2"                       ,	28,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"WBIL2"                       ,	29,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"WBL2"                        ,	30,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"LCKL2"                       ,	31,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD8"                      ,	32,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD16"                     ,	33,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD32"                     ,	34,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD64"                     ,	35,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST8"                      ,	36,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST16"                     ,	37,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST32"                     ,	38,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST64"                     ,	39,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET8"                        ,	40,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET16"                       ,	41,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET32"                       ,	42,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET64"                       ,	43,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR8"                        ,	44,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR16"                       ,	45,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR32"                       ,	46,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR64"                       ,	47,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR8"                       ,	48,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR16"                      ,	49,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR32"                      ,	50,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR64"                      ,	51,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR8"                       ,	52,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR16"                      ,	53,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR32"                      ,	54,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR64"                      ,	55,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_56_57"              ,	56,	2,	1128,	"R/W",	0,	0,	0ull,	0ull},
-	{"FAA32"                       ,	58,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAA64"                       ,	59,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_60_61"              ,	60,	2,	1128,	"R/W",	0,	0,	0ull,	0ull},
-	{"SAA32"                       ,	62,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"SAA64"                       ,	63,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
-	{"MIO"                         ,	0,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL3"                    ,	1,	2,	1129,	"R/W",	0,	0,	0ull,	3ull},
-	{"SLI"                         ,	3,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
-	{"KEY"                         ,	4,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
-	{"FPA"                         ,	5,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
-	{"DFA"                         ,	6,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
-	{"ZIP"                         ,	7,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
-	{"RNG"                         ,	8,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
-	{"IPD"                         ,	9,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
-	{"PKO"                         ,	10,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL2"                    ,	11,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
-	{"POW"                         ,	12,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
-	{"USB0"                        ,	13,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
-	{"RAD"                         ,	14,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL"                     ,	15,	12,	1129,	"R/W",	0,	0,	0ull,	4095ull},
-	{"DPI"                         ,	27,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL4"                    ,	28,	2,	1129,	"R/W",	0,	0,	0ull,	3ull},
-	{"FAU"                         ,	30,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL5"                    ,	31,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_32_63"              ,	32,	32,	1129,	"RAZ",	0,	0,	0ull,	0ull},
-	{"PP"                          ,	0,	8,	1130,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_8_15"               ,	8,	8,	1130,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKI"                         ,	16,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKO"                         ,	17,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
-	{"IOBREQ"                      ,	18,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
-	{"DWB"                         ,	19,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_20_63"              ,	20,	44,	1130,	"R/W",	0,	0,	0ull,	0ull},
-	{"ADR"                         ,	0,	38,	1131,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_38_63"              ,	38,	26,	1131,	"RAZ",	0,	0,	0ull,	0ull},
-	{"ADR"                         ,	0,	38,	1132,	"R/W",	0,	0,	0ull,	0ull},
+	{"COUNT"                       ,	8,	8,	1029,	"RO",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	16,	16,	1029,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	32,	16,	1029,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1029,	"RAZ",	1,	1,	0,	0},
+	{"SEQ"                         ,	0,	32,	1030,	"RO",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	32,	8,	1030,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	1030,	"RAZ",	1,	1,	0,	0},
+	{"POST"                        ,	0,	8,	1031,	"RO",	0,	1,	128ull,	0},
+	{"N_POST"                      ,	8,	5,	1031,	"RO",	0,	1,	16ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	1031,	"RAZ",	1,	1,	0,	0},
+	{"COMP"                        ,	16,	8,	1031,	"RO",	0,	1,	128ull,	0},
+	{"MBOX"                        ,	24,	4,	1031,	"RO",	0,	1,	8ull,	0},
+	{"RESERVED_28_39"              ,	28,	12,	1031,	"RAZ",	1,	1,	0,	0},
+	{"RTN_PR1"                     ,	40,	8,	1031,	"RO",	0,	1,	0ull,	0},
+	{"RTN_PR2"                     ,	48,	8,	1031,	"RO",	0,	1,	0ull,	0},
+	{"RTN_PR3"                     ,	56,	8,	1031,	"RO",	0,	1,	0ull,	0},
+	{"IAOW_SEL"                    ,	0,	2,	1032,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	1032,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	4,	1,	1032,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	5,	1,	1032,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	1032,	"RAZ",	1,	1,	0,	0},
+	{"RD_PRIOR"                    ,	8,	2,	1032,	"R/W",	0,	0,	1ull,	1ull},
+	{"WR_PRIOR"                    ,	10,	2,	1032,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD_OP"                       ,	12,	3,	1032,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	1032,	"RAZ",	1,	1,	0,	0},
+	{"WR_OP"                       ,	16,	3,	1032,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	1032,	"RAZ",	1,	1,	0,	0},
+	{"SEQ"                         ,	0,	32,	1033,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1033,	"RAZ",	1,	1,	0,	0},
+	{"SRIO"                        ,	0,	1,	1034,	"RO",	1,	1,	0,	0},
+	{"ACCESS"                      ,	1,	1,	1034,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	1034,	"RAZ",	1,	1,	0,	0},
+	{"ITAG"                        ,	0,	5,	1035,	"RO",	0,	1,	16ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1035,	"RAZ",	1,	1,	0,	0},
+	{"OTAG"                        ,	8,	5,	1035,	"RO",	0,	1,	16ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	1035,	"RAZ",	1,	1,	0,	0},
+	{"O_CLR"                       ,	16,	1,	1035,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	1035,	"RAZ",	1,	1,	0,	0},
+	{"POST"                        ,	0,	8,	1036,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_POST"                      ,	8,	5,	1036,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_13_15"              ,	13,	3,	1036,	"RAZ",	1,	1,	0,	0},
+	{"COMP"                        ,	16,	8,	1036,	"R/W",	0,	0,	128ull,	128ull},
+	{"MBOX"                        ,	24,	4,	1036,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_28_63"              ,	28,	36,	1036,	"RAZ",	1,	1,	0,	0},
+	{"PRIORITY"                    ,	0,	2,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1037,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	3,	1,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	4,	1,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	1037,	"RAZ",	1,	1,	0,	0},
+	{"PENDING"                     ,	8,	1,	1037,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_15"               ,	9,	7,	1037,	"RAZ",	1,	1,	0,	0},
+	{"DEST_ID"                     ,	16,	16,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	32,	16,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1037,	"RAZ",	1,	1,	0,	0},
+	{"PRIORITY"                    ,	0,	2,	1038,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1038,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	3,	1,	1038,	"RO",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	4,	1,	1038,	"RO",	0,	0,	0ull,	0ull},
+	{"RETRY"                       ,	5,	1,	1038,	"RO",	0,	0,	0ull,	0ull},
+	{"ERROR"                       ,	6,	1,	1038,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMEOUT"                     ,	7,	1,	1038,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1038,	"RAZ",	1,	1,	0,	0},
+	{"DEST_ID"                     ,	16,	16,	1038,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	32,	16,	1038,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1038,	"RAZ",	1,	1,	0,	0},
+	{"TX_TH0"                      ,	0,	4,	1039,	"R/W",	0,	0,	6ull,	3ull},
+	{"RESERVED_4_7"                ,	4,	4,	1039,	"RAZ",	1,	1,	0,	0},
+	{"TX_TH1"                      ,	8,	4,	1039,	"R/W",	0,	0,	4ull,	2ull},
+	{"RESERVED_12_15"              ,	12,	4,	1039,	"RAZ",	1,	1,	0,	0},
+	{"TX_TH2"                      ,	16,	4,	1039,	"R/W",	0,	0,	2ull,	1ull},
+	{"RESERVED_20_31"              ,	20,	12,	1039,	"RAZ",	1,	1,	0,	0},
+	{"TAG_TH0"                     ,	32,	5,	1039,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_37_39"              ,	37,	3,	1039,	"RAZ",	1,	1,	0,	0},
+	{"TAG_TH1"                     ,	40,	5,	1039,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_45_47"              ,	45,	3,	1039,	"RAZ",	1,	1,	0,	0},
+	{"TAG_TH2"                     ,	48,	5,	1039,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_53_63"              ,	53,	11,	1039,	"RAZ",	1,	1,	0,	0},
+	{"EMPH"                        ,	0,	4,	1040,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1040,	"RAZ",	1,	1,	0,	0},
+	{"S2M_PR0"                     ,	0,	8,	1041,	"RO",	0,	1,	0ull,	0},
+	{"S2M_PR1"                     ,	8,	8,	1041,	"RO",	0,	1,	0ull,	0},
+	{"S2M_PR2"                     ,	16,	8,	1041,	"RO",	0,	1,	0ull,	0},
+	{"S2M_PR3"                     ,	24,	8,	1041,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1041,	"RAZ",	1,	1,	0,	0},
+	{"GOOD"                        ,	0,	16,	1042,	"R/W",	0,	1,	0ull,	0},
+	{"BAD"                         ,	16,	16,	1042,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1042,	"RAZ",	1,	1,	0,	0},
+	{"ASSY_VEN"                    ,	0,	16,	1043,	"RO",	0,	0,	140ull,	0ull},
+	{"ASSY_ID"                     ,	16,	16,	1043,	"RO",	0,	0,	0ull,	0ull},
+	{"EXT_FPTR"                    ,	0,	16,	1044,	"RO",	0,	0,	256ull,	256ull},
+	{"ASSY_REV"                    ,	16,	16,	1044,	"RO",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1045,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_2"                ,	1,	2,	1045,	"RAZ",	1,	1,	0,	0},
+	{"NCA"                         ,	3,	1,	1045,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	4,	2,	1045,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	1045,	"RAZ",	1,	1,	0,	0},
+	{"LA"                          ,	8,	22,	1045,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_30_31"              ,	30,	2,	1045,	"RAZ",	1,	1,	0,	0},
+	{"FULL"                        ,	0,	1,	1046,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	1046,	"RAZ",	1,	1,	0,	0},
+	{"COMP_TAG"                    ,	0,	32,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEMORY"                      ,	0,	1,	1048,	"R/W",	0,	0,	0ull,	1ull},
+	{"DOORBELL"                    ,	1,	1,	1048,	"R/W",	0,	0,	0ull,	1ull},
+	{"IMSG0"                       ,	2,	1,	1048,	"R/W",	0,	0,	0ull,	1ull},
+	{"IMSG1"                       ,	3,	1,	1048,	"R/W",	0,	0,	0ull,	1ull},
+	{"HALT"                        ,	4,	1,	1048,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	1048,	"RAZ",	1,	1,	0,	0},
+	{"VENDOR"                      ,	0,	16,	1049,	"RO",	0,	0,	140ull,	140ull},
+	{"DEVICE"                      ,	16,	16,	1049,	"RO",	0,	1,	144ull,	0},
+	{"REVISION"                    ,	0,	8,	1050,	"RO",	1,	1,	0,	0},
+	{"RESERVED_8_31"               ,	8,	24,	1050,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	1051,	"RAZ",	1,	1,	0,	0},
+	{"PORT_WR"                     ,	2,	1,	1051,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SWP"                    ,	3,	1,	1051,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_CLR"                    ,	4,	1,	1051,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SET"                    ,	5,	1,	1051,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_DEC"                    ,	6,	1,	1051,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_INC"                    ,	7,	1,	1051,	"RO",	0,	0,	1ull,	1ull},
+	{"TESTSWAP"                    ,	8,	1,	1051,	"RO",	0,	0,	0ull,	0ull},
+	{"COMPSWAP"                    ,	9,	1,	1051,	"RO",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	10,	1,	1051,	"RO",	0,	0,	1ull,	1ull},
+	{"MSG"                         ,	11,	1,	1051,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE_R"                     ,	12,	1,	1051,	"RO",	0,	0,	1ull,	1ull},
+	{"SWRITE"                      ,	13,	1,	1051,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE"                       ,	14,	1,	1051,	"RO",	0,	0,	1ull,	1ull},
+	{"READ"                        ,	15,	1,	1051,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_21"              ,	16,	6,	1051,	"RAZ",	1,	1,	0,	0},
+	{"TLB_INVS"                    ,	22,	1,	1051,	"RO",	0,	0,	0ull,	0ull},
+	{"TLB_INV"                     ,	23,	1,	1051,	"RO",	0,	0,	0ull,	0ull},
+	{"I_INVALD"                    ,	24,	1,	1051,	"RO",	0,	0,	0ull,	0ull},
+	{"IO_READ"                     ,	25,	1,	1051,	"RO",	0,	0,	0ull,	0ull},
+	{"D_FLUSH"                     ,	26,	1,	1051,	"RO",	0,	0,	0ull,	0ull},
+	{"CASTOUT"                     ,	27,	1,	1051,	"RO",	0,	0,	0ull,	0ull},
+	{"D_INVALD"                    ,	28,	1,	1051,	"RO",	0,	0,	0ull,	0ull},
+	{"RD_OWN"                      ,	29,	1,	1051,	"RO",	0,	0,	0ull,	0ull},
+	{"I_READ"                      ,	30,	1,	1051,	"RO",	0,	0,	0ull,	0ull},
+	{"GSM_READ"                    ,	31,	1,	1051,	"RO",	0,	0,	0ull,	0ull},
+	{"VALID"                       ,	0,	1,	1052,	"R/W0C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	1052,	"RAZ",	1,	1,	0,	0},
+	{"ERR_INFO"                    ,	4,	20,	1052,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_TYPE"                    ,	24,	5,	1052,	"R/W",	0,	0,	0ull,	0ull},
+	{"INF_TYPE"                    ,	29,	3,	1052,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_TOUT"                    ,	0,	1,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ACK"                     ,	1,	1,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEL_ERR"                     ,	2,	1,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"F_TOGGLE"                    ,	3,	1,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"PROTERR"                     ,	4,	1,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_ACK"                     ,	5,	1,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_14"               ,	6,	9,	1053,	"RAZ",	1,	1,	0,	0},
+	{"INV_DATA"                    ,	15,	1,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_CHAR"                    ,	16,	1,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	17,	1,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_CRC"                     ,	18,	1,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUT_ACK"                     ,	19,	1,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"NACK"                        ,	20,	1,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ID"                      ,	21,	1,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTL_CRC"                     ,	22,	1,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_30"              ,	23,	8,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"IMP_ERR"                     ,	31,	1,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"RATE_CNT"                    ,	0,	8,	1054,	"R/W",	0,	1,	0ull,	0},
+	{"PK_RATE"                     ,	8,	8,	1054,	"R/W",	0,	1,	0ull,	0},
+	{"RATE_LIM"                    ,	16,	2,	1054,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_23"              ,	18,	6,	1054,	"RAZ",	1,	1,	0,	0},
+	{"ERR_BIAS"                    ,	24,	8,	1054,	"R/W",	0,	0,	128ull,	128ull},
+	{"LNK_TOUT"                    ,	0,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ACK"                     ,	1,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEL_ERR"                     ,	2,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"F_TOGGLE"                    ,	3,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"PROTERR"                     ,	4,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_ACK"                     ,	5,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_14"               ,	6,	9,	1055,	"RAZ",	1,	1,	0,	0},
+	{"INV_DATA"                    ,	15,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_CHAR"                    ,	16,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	17,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_CRC"                     ,	18,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUT_ACK"                     ,	19,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"NACK"                        ,	20,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ID"                      ,	21,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTL_CRC"                     ,	22,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_30"              ,	23,	8,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"IMP_ERR"                     ,	31,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_15"               ,	0,	16,	1056,	"RAZ",	1,	1,	0,	0},
+	{"DGRAD_TH"                    ,	16,	8,	1056,	"R/W",	0,	0,	255ull,	128ull},
+	{"FAIL_TH"                     ,	24,	8,	1056,	"R/W",	0,	0,	255ull,	255ull},
+	{"EF_ID"                       ,	0,	16,	1057,	"RO",	0,	0,	7ull,	7ull},
+	{"EF_PTR"                      ,	16,	16,	1057,	"RO",	0,	0,	0ull,	0ull},
+	{"ADDR"                        ,	0,	32,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"XADDR"                       ,	0,	2,	1059,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1059,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	29,	1059,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPT_IDX"                    ,	0,	5,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_5"                ,	5,	1,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDPTR"                       ,	6,	1,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"TT"                          ,	7,	1,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	8,	4,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATUS"                      ,	12,	4,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXTRA"                       ,	16,	8,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"TTYPE"                       ,	24,	4,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"FTYPE"                       ,	28,	4,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_14"               ,	0,	15,	1061,	"RAZ",	1,	1,	0,	0},
+	{"TT"                          ,	15,	1,	1061,	"R/W",	0,	0,	0ull,	0ull},
+	{"ID8"                         ,	16,	8,	1061,	"R/W",	0,	0,	0ull,	0ull},
+	{"ID16"                        ,	24,	8,	1061,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID8"                     ,	0,	8,	1062,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID16"                    ,	8,	8,	1062,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST_ID8"                     ,	16,	8,	1062,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST_ID16"                    ,	24,	8,	1062,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESP_SZ"                     ,	0,	1,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_21"               ,	1,	21,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_TRAN"                    ,	22,	1,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_RESP"                    ,	23,	1,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_TOUT"                    ,	24,	1,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_TOUT"                    ,	25,	1,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TGT"                     ,	26,	1,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TRAN"                    ,	27,	1,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_FMT"                     ,	28,	1,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSM_ERR"                     ,	29,	1,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_ERR"                     ,	30,	1,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO_ERR"                      ,	31,	1,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESP_SZ"                     ,	0,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_21"               ,	1,	21,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_TRAN"                    ,	22,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_RESP"                    ,	23,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_TOUT"                    ,	24,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_TOUT"                    ,	25,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TGT"                     ,	26,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TRAN"                    ,	27,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_FMT"                     ,	28,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSM_ERR"                     ,	29,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_ERR"                     ,	30,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO_ERR"                      ,	31,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1065,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1066,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1067,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1068,	"R/W",	0,	0,	0ull,	0ull},
+	{"HOSTID"                      ,	0,	16,	1069,	"R/W",	0,	0,	65535ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1069,	"RAZ",	1,	1,	0,	0},
+	{"RX_SYNC"                     ,	0,	1,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_SYNC"                     ,	1,	1,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_FLOW"                     ,	2,	1,	1070,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_19"               ,	3,	17,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_WM2"                      ,	20,	4,	1070,	"R/W",	0,	1,	2ull,	0},
+	{"TX_WM1"                      ,	24,	4,	1070,	"R/W",	0,	1,	3ull,	0},
+	{"TX_WM0"                      ,	28,	4,	1070,	"R/W",	0,	1,	4ull,	0},
+	{"RX_WM0"                      ,	0,	4,	1071,	"R/W",	0,	0,	4ull,	4ull},
+	{"RX_WM1"                      ,	4,	4,	1071,	"R/W",	0,	0,	3ull,	3ull},
+	{"RX_WM2"                      ,	8,	4,	1071,	"R/W",	0,	0,	2ull,	2ull},
+	{"RX_WM3"                      ,	12,	4,	1071,	"R/W",	0,	0,	1ull,	1ull},
+	{"TX_WM0"                      ,	16,	4,	1071,	"R/W",	0,	0,	4ull,	4ull},
+	{"TX_WM1"                      ,	20,	4,	1071,	"R/W",	0,	0,	3ull,	3ull},
+	{"TX_WM2"                      ,	24,	4,	1071,	"R/W",	0,	0,	2ull,	2ull},
+	{"TX_WM3"                      ,	28,	4,	1071,	"R/W",	0,	0,	1ull,	1ull},
+	{"PD_CTRL"                     ,	0,	32,	1072,	"R/W",	0,	0,	0ull,	0ull},
+	{"LN0_DIS"                     ,	0,	1,	1073,	"RO",	0,	0,	0ull,	0ull},
+	{"LN0_RX"                      ,	1,	3,	1073,	"RO",	0,	0,	0ull,	0ull},
+	{"LN1_DIS"                     ,	4,	1,	1073,	"RO",	0,	0,	0ull,	0ull},
+	{"LN1_RX"                      ,	5,	3,	1073,	"RO",	0,	0,	0ull,	0ull},
+	{"LN2_DIS"                     ,	8,	1,	1073,	"RO",	0,	0,	0ull,	0ull},
+	{"LN2_RX"                      ,	9,	3,	1073,	"RO",	0,	0,	0ull,	0ull},
+	{"LN3_DIS"                     ,	12,	1,	1073,	"RO",	0,	0,	0ull,	0ull},
+	{"LN3_RX"                      ,	13,	3,	1073,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1073,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_26"               ,	0,	27,	1074,	"RAZ",	1,	1,	0,	0},
+	{"LOOPBACK"                    ,	27,	2,	1074,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_29"              ,	29,	1,	1074,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_RESET"                    ,	30,	1,	1074,	"R/W",	0,	0,	1ull,	1ull},
+	{"TX_RESET"                    ,	31,	1,	1074,	"R/W",	0,	0,	1ull,	1ull},
+	{"INIT_SM"                     ,	0,	10,	1075,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_RDY"                      ,	10,	1,	1075,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_RDY"                      ,	11,	1,	1075,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	1075,	"RAZ",	1,	1,	0,	0},
+	{"OVERWRT"                     ,	0,	1,	1076,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	1076,	"RAZ",	1,	1,	0,	0},
+	{"PKT_DATA"                    ,	0,	32,	1077,	"RO",	0,	0,	0ull,	0ull},
+	{"FIFO_ST"                     ,	0,	4,	1078,	"RO",	0,	0,	0ull,	0ull},
+	{"FULL"                        ,	4,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
+	{"DROP_CNT"                    ,	5,	7,	1078,	"RO",	0,	1,	0ull,	0},
+	{"BUFFERS"                     ,	12,	4,	1078,	"RO",	0,	0,	0ull,	0ull},
+	{"OCTETS"                      ,	16,	16,	1078,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_15"               ,	0,	16,	1079,	"RAZ",	1,	1,	0,	0},
+	{"OCTETS"                      ,	16,	16,	1079,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_DATA"                    ,	0,	32,	1080,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIFO_ST"                     ,	0,	4,	1081,	"RO",	0,	0,	0ull,	0ull},
+	{"FULL"                        ,	4,	1,	1081,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_11"               ,	5,	7,	1081,	"RAZ",	1,	1,	0,	0},
+	{"BUFFERS"                     ,	12,	4,	1081,	"RO",	0,	0,	0ull,	0ull},
+	{"OCTETS"                      ,	16,	16,	1081,	"RO",	0,	0,	0ull,	0ull},
+	{"STATUSN"                     ,	0,	3,	1082,	"RO",	0,	0,	0ull,	0ull},
+	{"STATUS1"                     ,	3,	1,	1082,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_5"                ,	4,	2,	1082,	"RAZ",	1,	1,	0,	0},
+	{"XTRAIN"                      ,	6,	1,	1082,	"RO",	0,	0,	0ull,	0ull},
+	{"XSYNC"                       ,	7,	1,	1082,	"RO",	0,	0,	0ull,	0ull},
+	{"DEC_ERR"                     ,	8,	4,	1082,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_TRAIN"                    ,	12,	1,	1082,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_SYNC"                     ,	13,	1,	1082,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_ADAPT"                    ,	14,	1,	1082,	"RO",	0,	0,	1ull,	1ull},
+	{"RX_INV"                      ,	15,	1,	1082,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_TYPE"                     ,	16,	2,	1082,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_MODE"                     ,	18,	1,	1082,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_TYPE"                     ,	19,	1,	1082,	"RO",	0,	0,	0ull,	0ull},
+	{"LANE"                        ,	20,	4,	1082,	"RO",	0,	0,	0ull,	0ull},
+	{"PORT"                        ,	24,	8,	1082,	"RO",	0,	0,	0ull,	0ull},
+	{"LCSBA"                       ,	0,	31,	1083,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1083,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_20"               ,	0,	21,	1084,	"R/W",	0,	0,	0ull,	0ull},
+	{"LCSBA"                       ,	21,	11,	1084,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR48"                      ,	0,	16,	1085,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR64"                      ,	16,	16,	1085,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1086,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR66"                      ,	1,	2,	1086,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_13"               ,	3,	11,	1086,	"RAZ",	1,	1,	0,	0},
+	{"ADDR32"                      ,	14,	18,	1086,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR48"                      ,	0,	16,	1087,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR64"                      ,	16,	16,	1087,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR66"                      ,	1,	2,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"BARSIZE"                     ,	3,	4,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_19"               ,	7,	13,	1088,	"RAZ",	1,	1,	0,	0},
+	{"ADDR32"                      ,	20,	12,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR66"                      ,	1,	2,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAX"                         ,	3,	1,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"ESX"                         ,	4,	2,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_8"                ,	6,	3,	1089,	"RAZ",	1,	1,	0,	0},
+	{"ADDR48"                      ,	9,	7,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR64"                      ,	16,	16,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_RTRY"                    ,	0,	16,	1090,	"R/W",	0,	1,	0ull,	0},
+	{"TYPE_MRG"                    ,	16,	1,	1090,	"R/W",	0,	0,	1ull,	1ull},
+	{"EOP_MRG"                     ,	17,	1,	1090,	"R/W",	0,	0,	1ull,	1ull},
+	{"RX_SPF"                      ,	18,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_ZERO"                    ,	19,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	1090,	"RAZ",	1,	1,	0,	0},
+	{"EX_ADDR"                     ,	0,	3,	1091,	"RO",	0,	0,	7ull,	7ull},
+	{"EX_FEAT"                     ,	3,	1,	1091,	"RO",	0,	0,	1ull,	1ull},
+	{"LG_TRAN"                     ,	4,	1,	1091,	"RO",	0,	0,	1ull,	1ull},
+	{"CRF"                         ,	5,	1,	1091,	"RO",	0,	0,	0ull,	0ull},
+	{"SUPPRESS"                    ,	6,	1,	1091,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_26"               ,	7,	20,	1091,	"RAZ",	1,	1,	0,	0},
+	{"MULT_PRT"                    ,	27,	1,	1091,	"RO",	0,	0,	0ull,	0ull},
+	{"SWITCHF"                     ,	28,	1,	1091,	"RO",	0,	0,	0ull,	0ull},
+	{"PROC"                        ,	29,	1,	1091,	"RO",	0,	0,	1ull,	1ull},
+	{"MEMORY"                      ,	30,	1,	1091,	"RO",	0,	0,	1ull,	1ull},
+	{"BRIDGE"                      ,	31,	1,	1091,	"RO",	0,	0,	0ull,	0ull},
+	{"EX_ADDR"                     ,	0,	3,	1092,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_31"               ,	3,	29,	1092,	"RAZ",	1,	1,	0,	0},
+	{"PT_TYPE"                     ,	0,	1,	1093,	"RO",	0,	0,	1ull,	1ull},
+	{"PRT_LOCK"                    ,	1,	1,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"DROP_PKT"                    ,	2,	1,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"STP_PORT"                    ,	3,	1,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUPPRESS"                    ,	4,	8,	1093,	"RO",	0,	0,	0ull,	0ull},
+	{"EX_STAT"                     ,	12,	2,	1093,	"RO",	0,	0,	0ull,	0ull},
+	{"EX_WIDTH"                    ,	14,	2,	1093,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	1093,	"RAZ",	1,	1,	0,	0},
+	{"ENUMB"                       ,	17,	1,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_18"              ,	18,	1,	1093,	"RAZ",	1,	1,	0,	0},
+	{"MCAST"                       ,	19,	1,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIS_ERR"                     ,	20,	1,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"I_ENABLE"                    ,	21,	1,	1093,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ENABLE"                    ,	22,	1,	1093,	"R/W",	0,	0,	0ull,	1ull},
+	{"DISABLE"                     ,	23,	1,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"OV_WIDTH"                    ,	24,	3,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"IT_WIDTH"                    ,	27,	3,	1093,	"RO",	0,	1,	0ull,	0},
+	{"PT_WIDTH"                    ,	30,	2,	1093,	"RO",	0,	0,	3ull,	3ull},
+	{"EMPH_EN"                     ,	0,	1,	1094,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_EMPH"                     ,	1,	1,	1094,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_15"               ,	2,	14,	1094,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB_625G"                    ,	16,	1,	1094,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUP_625G"                    ,	17,	1,	1094,	"RO",	0,	0,	0ull,	0ull},
+	{"ENB_500G"                    ,	18,	1,	1094,	"R/W",	1,	1,	0,	0},
+	{"SUB_500G"                    ,	19,	1,	1094,	"RO",	1,	1,	0,	0},
+	{"ENB_312G"                    ,	20,	1,	1094,	"R/W",	1,	1,	0,	0},
+	{"SUP_312G"                    ,	21,	1,	1094,	"RO",	1,	1,	0,	0},
+	{"ENB_250G"                    ,	22,	1,	1094,	"R/W",	1,	1,	0,	0},
+	{"SUP_250G"                    ,	23,	1,	1094,	"RO",	1,	1,	0,	0},
+	{"ENB_125G"                    ,	24,	1,	1094,	"R/W",	1,	1,	0,	0},
+	{"SUP_125G"                    ,	25,	1,	1094,	"RO",	1,	1,	0,	0},
+	{"BAUD_ENB"                    ,	26,	1,	1094,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAUD_SUP"                    ,	27,	1,	1094,	"RO",	0,	0,	0ull,	0ull},
+	{"SEL_BAUD"                    ,	28,	4,	1094,	"RO",	0,	1,	0ull,	0},
+	{"PT_UINIT"                    ,	0,	1,	1095,	"RO",	0,	0,	1ull,	0ull},
+	{"PT_OK"                       ,	1,	1,	1095,	"RO",	0,	0,	0ull,	1ull},
+	{"PT_ERROR"                    ,	2,	1,	1095,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1095,	"RAZ",	1,	1,	0,	0},
+	{"PT_WRITE"                    ,	4,	1,	1095,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	1095,	"RAZ",	1,	1,	0,	0},
+	{"I_SM_ERR"                    ,	8,	1,	1095,	"RO",	0,	0,	0ull,	0ull},
+	{"I_ERROR"                     ,	9,	1,	1095,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I_SM_RET"                    ,	10,	1,	1095,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	1095,	"RAZ",	1,	1,	0,	0},
+	{"O_SM_ERR"                    ,	16,	1,	1095,	"RO",	0,	0,	0ull,	0ull},
+	{"O_ERROR"                     ,	17,	1,	1095,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"O_SM_RET"                    ,	18,	1,	1095,	"RO",	0,	0,	0ull,	0ull},
+	{"O_RTRIED"                    ,	19,	1,	1095,	"RO",	0,	0,	0ull,	0ull},
+	{"O_RETRY"                     ,	20,	1,	1095,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	1095,	"RAZ",	1,	1,	0,	0},
+	{"O_DGRAD"                     ,	24,	1,	1095,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"O_FAIL"                      ,	25,	1,	1095,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKT_DROP"                    ,	26,	1,	1095,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_31"              ,	27,	5,	1095,	"RAZ",	1,	1,	0,	0},
+	{"CMD"                         ,	0,	3,	1096,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_31"               ,	3,	29,	1096,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	5,	1097,	"RO",	0,	1,	0ull,	0},
+	{"ACKID"                       ,	5,	6,	1097,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_11_30"              ,	11,	20,	1097,	"RAZ",	1,	1,	0,	0},
+	{"VALID"                       ,	31,	1,	1097,	"RO",	0,	1,	0ull,	0},
+	{"O_ACKID"                     ,	0,	6,	1098,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	1098,	"RAZ",	1,	1,	0,	0},
+	{"E_ACKID"                     ,	8,	6,	1098,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_23"              ,	14,	10,	1098,	"RAZ",	1,	1,	0,	0},
+	{"I_ACKID"                     ,	24,	6,	1098,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_30_31"              ,	30,	2,	1098,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_28"               ,	0,	29,	1099,	"RAZ",	1,	1,	0,	0},
+	{"DISCOVER"                    ,	29,	1,	1099,	"R/W",	0,	0,	0ull,	1ull},
+	{"MENABLE"                     ,	30,	1,	1099,	"R/W",	1,	0,	0,	1ull},
+	{"HOST"                        ,	31,	1,	1099,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1100,	"RAZ",	1,	1,	0,	0},
+	{"TIMEOUT"                     ,	8,	24,	1100,	"R/W",	0,	0,	16777215ull,	0ull},
+	{"EF_ID"                       ,	0,	16,	1101,	"RO",	0,	0,	1ull,	0ull},
+	{"EF_PTR"                      ,	16,	16,	1101,	"RO",	0,	0,	4096ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	1102,	"RAZ",	1,	1,	0,	0},
+	{"TIMEOUT"                     ,	8,	24,	1102,	"R/W",	0,	0,	16777215ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	1103,	"RAZ",	1,	1,	0,	0},
+	{"TIMEOUT"                     ,	8,	24,	1103,	"R/W",	0,	1,	0ull,	0},
+	{"ID16"                        ,	0,	16,	1104,	"R/W",	0,	0,	65535ull,	0ull},
+	{"ID8"                         ,	16,	8,	1104,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1104,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE16"                    ,	0,	1,	1105,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE8"                     ,	1,	1,	1105,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	1105,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	0,	16,	1106,	"R/W",	0,	0,	65535ull,	0ull},
+	{"ID8"                         ,	16,	8,	1106,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1106,	"RAZ",	1,	1,	0,	0},
+	{"EF_ID"                       ,	0,	16,	1107,	"RO",	0,	0,	13ull,	13ull},
+	{"EF_PTR"                      ,	16,	16,	1107,	"RO",	0,	0,	8192ull,	0ull},
+	{"RESERVED_0_1"                ,	0,	2,	1108,	"RAZ",	1,	1,	0,	0},
+	{"PORT_WR"                     ,	2,	1,	1108,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SWP"                    ,	3,	1,	1108,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_CLR"                    ,	4,	1,	1108,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SET"                    ,	5,	1,	1108,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_DEC"                    ,	6,	1,	1108,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_INC"                    ,	7,	1,	1108,	"RO",	0,	0,	1ull,	1ull},
+	{"TESTSWAP"                    ,	8,	1,	1108,	"RO",	0,	0,	0ull,	0ull},
+	{"COMPSWAP"                    ,	9,	1,	1108,	"RO",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	10,	1,	1108,	"RO",	0,	0,	1ull,	1ull},
+	{"MSG"                         ,	11,	1,	1108,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE_R"                     ,	12,	1,	1108,	"RO",	0,	0,	1ull,	1ull},
+	{"SWRITE"                      ,	13,	1,	1108,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE"                       ,	14,	1,	1108,	"RO",	0,	0,	1ull,	1ull},
+	{"READ"                        ,	15,	1,	1108,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_21"              ,	16,	6,	1108,	"RAZ",	1,	1,	0,	0},
+	{"TLB_INVS"                    ,	22,	1,	1108,	"RO",	0,	0,	0ull,	0ull},
+	{"TLB_INV"                     ,	23,	1,	1108,	"RO",	0,	0,	0ull,	0ull},
+	{"I_INVALD"                    ,	24,	1,	1108,	"RO",	0,	0,	0ull,	0ull},
+	{"IO_READ"                     ,	25,	1,	1108,	"RO",	0,	0,	0ull,	0ull},
+	{"D_FLUSH"                     ,	26,	1,	1108,	"RO",	0,	0,	0ull,	0ull},
+	{"CASTOUT"                     ,	27,	1,	1108,	"RO",	0,	0,	0ull,	0ull},
+	{"D_INVALD"                    ,	28,	1,	1108,	"RO",	0,	0,	0ull,	0ull},
+	{"RD_OWN"                      ,	29,	1,	1108,	"RO",	0,	0,	0ull,	0ull},
+	{"I_READ"                      ,	30,	1,	1108,	"RO",	0,	0,	0ull,	0ull},
+	{"GSM_READ"                    ,	31,	1,	1108,	"RO",	0,	0,	0ull,	0ull},
+	{"DROP_CNT"                    ,	0,	16,	1109,	"RO",	0,	1,	0ull,	0},
+	{"DROP"                        ,	16,	1,	1109,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	1109,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	22,	1110,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1110,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	24,	22,	1110,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	1110,	"RAZ",	1,	1,	0,	0},
+	{"ENA"                         ,	47,	1,	1110,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1110,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	20,	1111,	"RO",	1,	0,	0,	0ull},
+	{"BASE"                        ,	20,	31,	1111,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	51,	13,	1111,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	0,	7,	1112,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	1112,	"RO",	1,	0,	0,	0ull},
+	{"CSIZE"                       ,	8,	13,	1112,	"RO",	1,	0,	0,	0ull},
+	{"CPOOL"                       ,	21,	3,	1112,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	1112,	"RAZ",	1,	1,	0,	0},
+	{"RING"                        ,	0,	4,	1113,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_BUCKETS"                 ,	4,	20,	1113,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIRST_BUCKET"                ,	24,	31,	1113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	1113,	"RAZ",	1,	1,	0,	0},
+	{"RING"                        ,	0,	4,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	4,	22,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORDS_PER_CHUNK"             ,	26,	13,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	39,	3,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	42,	1,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	1114,	"RAZ",	1,	1,	0,	0},
+	{"CTL"                         ,	0,	1,	1115,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	1,	1,	1115,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	2,	2,	1115,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1115,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	1116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1116,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE_TIMERS"               ,	0,	1,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	2,	1,	1117,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	1117,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	1118,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1118,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	1119,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	1119,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1119,	"RAZ",	1,	1,	0,	0},
+	{"TDF"                         ,	0,	1,	1120,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1120,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRAP"                        ,	1,	1,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRIG_CTL"                    ,	2,	2,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIME_GRN"                    ,	4,	3,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"FULL_THR"                    ,	7,	2,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	9,	1,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	10,	1,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	11,	1,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	12,	1,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_ENA"                    ,	13,	1,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNORE_O"                    ,	14,	1,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKALWAYS"                   ,	15,	1,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDAT_MD"                     ,	16,	1,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	1121,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	8,	1122,	"RO",	0,	0,	0ull,	0ull},
+	{"RPTR"                        ,	8,	8,	1122,	"RO",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	16,	48,	1122,	"RO",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	10,	1123,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	1123,	"RAZ",	1,	1,	0,	0},
+	{"RPTR"                        ,	12,	10,	1123,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1123,	"RAZ",	1,	1,	0,	0},
+	{"CYCLES"                      ,	24,	40,	1123,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1124,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1124,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1125,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1125,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1126,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1126,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1126,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1126,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1126,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1126,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1127,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1127,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1127,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1127,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1127,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1127,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1127,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1127,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1127,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1127,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1127,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1127,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1127,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1127,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1127,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1127,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1127,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1127,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1127,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1127,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	8,	1128,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1128,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1128,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1128,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1128,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1128,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1128,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	0,	1,	1129,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	1,	1,	1129,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	2,	1,	1129,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	3,	1,	1129,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1129,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	1130,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	5,	1131,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	1131,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1132,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_38_63"              ,	38,	26,	1132,	"RAZ",	0,	0,	0ull,	0ull},
-	{"NOP"                         ,	0,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"LDT"                         ,	1,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"LDI"                         ,	2,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"PL2"                         ,	3,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"RPL2"                        ,	4,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"DWB"                         ,	5,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_7"                ,	6,	2,	1133,	"R/W",	0,	0,	0ull,	0ull},
-	{"LDD"                         ,	8,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"PSL1"                        ,	9,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_10_14"              ,	10,	5,	1133,	"R/W",	0,	0,	0ull,	0ull},
-	{"IOBDMA"                      ,	15,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"STF"                         ,	16,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"STT"                         ,	17,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"STP"                         ,	18,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"STC"                         ,	19,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"STFIL1"                      ,	20,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"STTIL1"                      ,	21,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAS32"                       ,	22,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAS64"                       ,	23,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"WBIL2I"                      ,	24,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"LTGL2I"                      ,	25,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"STGL2I"                      ,	26,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_27_27"              ,	27,	1,	1133,	"R/W",	0,	0,	0ull,	0ull},
-	{"INVL2"                       ,	28,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"WBIL2"                       ,	29,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"WBL2"                        ,	30,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"LCKL2"                       ,	31,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD8"                      ,	32,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD16"                     ,	33,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD32"                     ,	34,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBLD64"                     ,	35,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST8"                      ,	36,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST16"                     ,	37,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST32"                     ,	38,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"IOBST64"                     ,	39,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET8"                        ,	40,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET16"                       ,	41,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET32"                       ,	42,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"SET64"                       ,	43,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR8"                        ,	44,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR16"                       ,	45,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR32"                       ,	46,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"CLR64"                       ,	47,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR8"                       ,	48,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR16"                      ,	49,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR32"                      ,	50,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"INCR64"                      ,	51,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR8"                       ,	52,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR16"                      ,	53,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR32"                      ,	54,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"DECR64"                      ,	55,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_56_57"              ,	56,	2,	1133,	"R/W",	0,	0,	0ull,	0ull},
-	{"FAA32"                       ,	58,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"FAA64"                       ,	59,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_60_61"              ,	60,	2,	1133,	"R/W",	0,	0,	0ull,	0ull},
-	{"SAA32"                       ,	62,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"SAA64"                       ,	63,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
-	{"MIO"                         ,	0,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL3"                    ,	1,	2,	1134,	"R/W",	0,	0,	0ull,	3ull},
-	{"SLI"                         ,	3,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
-	{"KEY"                         ,	4,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
-	{"FPA"                         ,	5,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
-	{"DFA"                         ,	6,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
-	{"ZIP"                         ,	7,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
-	{"RNG"                         ,	8,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
-	{"IPD"                         ,	9,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
-	{"PKO"                         ,	10,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL2"                    ,	11,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
-	{"POW"                         ,	12,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
-	{"USB0"                        ,	13,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
-	{"RAD"                         ,	14,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL"                     ,	15,	12,	1134,	"R/W",	0,	0,	0ull,	4095ull},
-	{"DPI"                         ,	27,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL4"                    ,	28,	2,	1134,	"R/W",	0,	0,	0ull,	3ull},
-	{"FAU"                         ,	30,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
-	{"ILLEGAL5"                    ,	31,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_32_63"              ,	32,	32,	1134,	"RAZ",	0,	0,	0ull,	0ull},
-	{"PP"                          ,	0,	8,	1135,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_8_15"               ,	8,	8,	1135,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKI"                         ,	16,	1,	1135,	"R/W",	0,	0,	0ull,	0ull},
-	{"PKO"                         ,	17,	1,	1135,	"R/W",	0,	0,	0ull,	0ull},
-	{"IOBREQ"                      ,	18,	1,	1135,	"R/W",	0,	0,	0ull,	0ull},
-	{"DWB"                         ,	19,	1,	1135,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_20_63"              ,	20,	44,	1135,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_4"                ,	0,	5,	1136,	"R/W",	0,	1,	0ull,	0},
-	{"LPL"                         ,	5,	27,	1136,	"R/W",	0,	1,	0ull,	0},
-	{"CF"                          ,	0,	1,	1137,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_1_31"               ,	1,	31,	1137,	"R/W",	0,	0,	0ull,	0ull},
-	{"CTRLDSSEG"                   ,	0,	32,	1138,	"R/W",	0,	1,	0ull,	0},
-	{"FI"                          ,	0,	14,	1139,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_14_31"              ,	14,	18,	1139,	"RO",	0,	0,	0ull,	0ull},
-	{"CAPLENGTH"                   ,	0,	8,	1140,	"RO",	0,	0,	16ull,	16ull},
-	{"RESERVED_8_15"               ,	8,	8,	1140,	"RO",	0,	0,	0ull,	0ull},
-	{"HCIVERSION"                  ,	16,	16,	1140,	"RO",	0,	0,	256ull,	256ull},
-	{"AC64"                        ,	0,	1,	1141,	"RO",	0,	0,	1ull,	1ull},
-	{"PFLF"                        ,	1,	1,	1141,	"RO",	0,	0,	0ull,	0ull},
-	{"ASPC"                        ,	2,	1,	1141,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_3"                ,	3,	1,	1141,	"RO",	0,	0,	0ull,	0ull},
-	{"IST"                         ,	4,	4,	1141,	"RO",	0,	0,	2ull,	2ull},
-	{"EECP"                        ,	8,	8,	1141,	"RO",	0,	0,	160ull,	160ull},
-	{"RESERVED_16_31"              ,	16,	16,	1141,	"RO",	0,	0,	0ull,	0ull},
-	{"N_PORTS"                     ,	0,	4,	1142,	"RO",	0,	0,	2ull,	2ull},
-	{"PPC"                         ,	4,	1,	1142,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_5_6"                ,	5,	2,	1142,	"RO",	0,	0,	0ull,	0ull},
-	{"PRR"                         ,	7,	1,	1142,	"RO",	0,	0,	0ull,	0ull},
-	{"N_PCC"                       ,	8,	4,	1142,	"RO",	0,	0,	2ull,	2ull},
-	{"N_CC"                        ,	12,	4,	1142,	"RO",	0,	0,	1ull,	1ull},
-	{"P_INDICATOR"                 ,	16,	1,	1142,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_17_19"              ,	17,	3,	1142,	"RO",	0,	0,	0ull,	0ull},
-	{"DPN"                         ,	20,	4,	1142,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_24_31"              ,	24,	8,	1142,	"RO",	0,	0,	0ull,	0ull},
-	{"EN"                          ,	0,	1,	1143,	"R/W",	0,	0,	0ull,	0ull},
-	{"MFMC"                        ,	1,	13,	1143,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_14_31"              ,	14,	18,	1143,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_0"                ,	0,	1,	1144,	"R/W",	0,	0,	0ull,	0ull},
-	{"TA_OFF"                      ,	1,	8,	1144,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_9_9"                ,	9,	1,	1144,	"R/W",	0,	0,	0ull,	0ull},
-	{"TXTX_TADAO"                  ,	10,	3,	1144,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_13_31"              ,	13,	19,	1144,	"R/W",	0,	0,	0ull,	0ull},
-	{"HCP_RW"                      ,	0,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
-	{"HCP_FW"                      ,	1,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
-	{"PESD"                        ,	2,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_3"                ,	3,	1,	1145,	"RAZ",	0,	0,	0ull,	0ull},
-	{"NAKRF_DIS"                   ,	4,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
-	{"AUTO_DIS"                    ,	5,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_31"               ,	6,	26,	1145,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_30"               ,	0,	31,	1146,	"R/W",	0,	0,	0ull,	0ull},
-	{"VLD"                         ,	31,	1,	1146,	"R/W",	0,	0,	0ull,	0ull},
-	{"ERR_ADDR"                    ,	0,	32,	1147,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_11"               ,	0,	12,	1148,	"R/W",	0,	1,	0ull,	0},
-	{"BADDR"                       ,	12,	20,	1148,	"R/W",	0,	1,	0ull,	0},
-	{"CCS"                         ,	0,	1,	1149,	"RO",	0,	0,	0ull,	0ull},
-	{"CSC"                         ,	1,	1,	1149,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PED"                         ,	2,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
-	{"PEDC"                        ,	3,	1,	1149,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"OCA"                         ,	4,	1,	1149,	"RO",	0,	0,	0ull,	0ull},
-	{"OCC"                         ,	5,	1,	1149,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"FPR"                         ,	6,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
-	{"SPD"                         ,	7,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
-	{"PRST"                        ,	8,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_9_9"                ,	9,	1,	1149,	"RO",	0,	0,	0ull,	0ull},
-	{"LSTS"                        ,	10,	2,	1149,	"RO",	0,	1,	0ull,	0},
-	{"PP"                          ,	12,	1,	1149,	"RO",	0,	0,	1ull,	1ull},
-	{"PO"                          ,	13,	1,	1149,	"R/W",	0,	0,	1ull,	0ull},
-	{"PIC"                         ,	14,	2,	1149,	"R/W",	0,	0,	0ull,	0ull},
-	{"PTC"                         ,	16,	4,	1149,	"R/W",	0,	0,	0ull,	0ull},
-	{"WKCNNT_E"                    ,	20,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
-	{"WKDSCNNT_E"                  ,	21,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
-	{"WKOC_E"                      ,	22,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_31"              ,	23,	9,	1149,	"RO",	0,	0,	0ull,	0ull},
-	{"RS"                          ,	0,	1,	1150,	"R/W",	0,	0,	0ull,	1ull},
-	{"HCRESET"                     ,	1,	1,	1150,	"R/W",	0,	0,	0ull,	0ull},
-	{"FLS"                         ,	2,	2,	1150,	"RO",	0,	0,	0ull,	0ull},
-	{"PS_EN"                       ,	4,	1,	1150,	"R/W",	0,	0,	0ull,	0ull},
-	{"AS_EN"                       ,	5,	1,	1150,	"R/W",	0,	0,	0ull,	0ull},
-	{"IAA_DB"                      ,	6,	1,	1150,	"R/W",	0,	0,	0ull,	0ull},
-	{"LHCR"                        ,	7,	1,	1150,	"R/W",	0,	0,	0ull,	0ull},
-	{"ASPMC"                       ,	8,	2,	1150,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_10"              ,	10,	1,	1150,	"RO",	0,	0,	0ull,	0ull},
-	{"ASPM_EN"                     ,	11,	1,	1150,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_12_15"              ,	12,	4,	1150,	"RO",	0,	0,	0ull,	0ull},
-	{"ITC"                         ,	16,	8,	1150,	"R/W",	0,	0,	8ull,	8ull},
-	{"RESERVED_24_31"              ,	24,	8,	1150,	"RO",	0,	0,	0ull,	0ull},
-	{"USBINT_EN"                   ,	0,	1,	1151,	"R/W",	0,	1,	0ull,	0},
-	{"USBERRINT_EN"                ,	1,	1,	1151,	"R/W",	0,	1,	0ull,	0},
-	{"PCI_EN"                      ,	2,	1,	1151,	"R/W",	0,	1,	0ull,	0},
-	{"FLRO_EN"                     ,	3,	1,	1151,	"R/W",	0,	1,	0ull,	0},
-	{"HSERR_EN"                    ,	4,	1,	1151,	"R/W",	0,	1,	0ull,	0},
-	{"IOAA_EN"                     ,	5,	1,	1151,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_6_31"               ,	6,	26,	1151,	"RO",	0,	0,	0ull,	0ull},
-	{"USBINT"                      ,	0,	1,	1152,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"USBERRINT"                   ,	1,	1,	1152,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"PCD"                         ,	2,	1,	1152,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"FLRO"                        ,	3,	1,	1152,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"HSYSERR"                     ,	4,	1,	1152,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"IOAA"                        ,	5,	1,	1152,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_11"               ,	6,	6,	1152,	"RO",	0,	0,	0ull,	0ull},
-	{"HCHTD"                       ,	12,	1,	1152,	"RO",	0,	0,	1ull,	0ull},
-	{"RECLM"                       ,	13,	1,	1152,	"RO",	0,	0,	0ull,	0ull},
-	{"PSS"                         ,	14,	1,	1152,	"RO",	0,	0,	0ull,	0ull},
-	{"ASS"                         ,	15,	1,	1152,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_31"              ,	16,	16,	1152,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_3"                ,	0,	4,	1153,	"R/W",	0,	0,	0ull,	0ull},
-	{"BCED"                        ,	4,	28,	1153,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_0_3"                ,	0,	4,	1154,	"R/W",	0,	0,	0ull,	0ull},
-	{"BHED"                        ,	4,	28,	1154,	"R/W",	0,	1,	0ull,	0},
-	{"HCR"                         ,	0,	1,	1155,	"R/W",	0,	0,	0ull,	0ull},
-	{"CLF"                         ,	1,	1,	1155,	"R/W",	0,	0,	0ull,	0ull},
-	{"BLF"                         ,	2,	1,	1155,	"R/W",	0,	0,	0ull,	0ull},
-	{"OCR"                         ,	3,	1,	1155,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_15"               ,	4,	12,	1155,	"RO",	0,	0,	0ull,	0ull},
-	{"SOC"                         ,	16,	2,	1155,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_18_31"              ,	18,	14,	1155,	"RO",	0,	0,	0ull,	0ull},
-	{"CBSR"                        ,	0,	2,	1156,	"R/W",	0,	1,	0ull,	0},
-	{"PLE"                         ,	2,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
-	{"IE"                          ,	3,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
-	{"CLE"                         ,	4,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
-	{"BLE"                         ,	5,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
-	{"HCFS"                        ,	6,	2,	1156,	"R/W",	0,	0,	0ull,	0ull},
-	{"IR"                          ,	8,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
-	{"RWC"                         ,	9,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
-	{"RWE"                         ,	10,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_11_31"              ,	11,	21,	1156,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_3"                ,	0,	4,	1157,	"R/W",	0,	0,	0ull,	0ull},
-	{"CCED"                        ,	4,	28,	1157,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_0_3"                ,	0,	4,	1158,	"R/W",	0,	0,	0ull,	0ull},
-	{"CHED"                        ,	4,	28,	1158,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_0_3"                ,	0,	4,	1159,	"RO",	0,	0,	0ull,	0ull},
-	{"DH"                          ,	4,	28,	1159,	"RO",	0,	1,	0ull,	0},
-	{"FI"                          ,	0,	14,	1160,	"R/W",	0,	1,	11999ull,	0},
-	{"RESERVED_14_15"              ,	14,	2,	1160,	"R/W",	0,	0,	0ull,	0ull},
-	{"FSMPS"                       ,	16,	15,	1160,	"R/W",	0,	1,	0ull,	0},
-	{"FIT"                         ,	31,	1,	1160,	"R/W",	0,	0,	0ull,	0ull},
-	{"FN"                          ,	0,	16,	1161,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_16_31"              ,	16,	16,	1161,	"RO",	0,	0,	0ull,	0ull},
-	{"FR"                          ,	0,	14,	1162,	"RO",	0,	1,	0ull,	0},
-	{"RESERVED_14_30"              ,	14,	17,	1162,	"RO",	0,	0,	0ull,	0ull},
-	{"FRT"                         ,	31,	1,	1162,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_7"                ,	0,	8,	1163,	"R/W",	0,	0,	0ull,	0ull},
-	{"HCCA"                        ,	8,	24,	1163,	"R/W",	0,	1,	0ull,	0},
-	{"SO"                          ,	0,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
-	{"WDH"                         ,	1,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
-	{"SF"                          ,	2,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
-	{"RD"                          ,	3,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
-	{"UE"                          ,	4,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
-	{"FNO"                         ,	5,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
-	{"RHSC"                        ,	6,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_7_29"               ,	7,	23,	1164,	"RO",	0,	0,	0ull,	0ull},
-	{"OC"                          ,	30,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
-	{"MIE"                         ,	31,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
-	{"SO"                          ,	0,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
-	{"WDH"                         ,	1,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
-	{"SF"                          ,	2,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
-	{"RD"                          ,	3,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
-	{"UE"                          ,	4,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
-	{"FNO"                         ,	5,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
-	{"RHSC"                        ,	6,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_7_29"               ,	7,	23,	1165,	"RO",	0,	0,	0ull,	0ull},
-	{"OC"                          ,	30,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
-	{"MIE"                         ,	31,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
-	{"SO"                          ,	0,	1,	1166,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"WDH"                         ,	1,	1,	1166,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"SF"                          ,	2,	1,	1166,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RD"                          ,	3,	1,	1166,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"UE"                          ,	4,	1,	1166,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"FNO"                         ,	5,	1,	1166,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RHSC"                        ,	6,	1,	1166,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_7_29"               ,	7,	23,	1166,	"RO",	0,	0,	0ull,	0ull},
-	{"OC"                          ,	30,	1,	1166,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_31_31"              ,	31,	1,	1166,	"RO",	0,	0,	0ull,	0ull},
-	{"LST"                         ,	0,	12,	1167,	"R/W",	0,	1,	1576ull,	0},
-	{"RESERVED_12_31"              ,	12,	20,	1167,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_0_3"                ,	0,	4,	1168,	"RO",	0,	0,	0ull,	0ull},
-	{"PCED"                        ,	4,	28,	1168,	"RO",	0,	1,	0ull,	0},
-	{"PS"                          ,	0,	14,	1169,	"R/W",	0,	0,	0ull,	15975ull},
-	{"RESERVED_14_31"              ,	14,	18,	1169,	"R/W",	0,	0,	0ull,	0ull},
-	{"REV"                         ,	0,	8,	1170,	"RO",	0,	0,	16ull,	16ull},
-	{"RESERVED_8_31"               ,	8,	24,	1170,	"RO",	0,	0,	0ull,	0ull},
-	{"NDP"                         ,	0,	8,	1171,	"RO",	0,	0,	2ull,	2ull},
-	{"NPS"                         ,	8,	1,	1171,	"R/W",	0,	0,	0ull,	0ull},
-	{"PSM"                         ,	9,	1,	1171,	"R/W",	0,	0,	1ull,	1ull},
-	{"DT"                          ,	10,	1,	1171,	"RO",	0,	0,	0ull,	0ull},
-	{"OCPM"                        ,	11,	1,	1171,	"R/W",	1,	1,	0,	0},
-	{"NOCP"                        ,	12,	1,	1171,	"R/W",	0,	0,	1ull,	1ull},
-	{"RESERVED_13_23"              ,	13,	11,	1171,	"RO",	0,	0,	0ull,	0ull},
-	{"POTPGT"                      ,	24,	8,	1171,	"R/W",	0,	0,	1ull,	1ull},
-	{"DR"                          ,	0,	16,	1172,	"R/W",	0,	0,	0ull,	0ull},
-	{"PPCM"                        ,	16,	16,	1172,	"R/W",	0,	1,	0ull,	0},
-	{"CCS"                         ,	0,	1,	1173,	"R/W",	0,	1,	0ull,	0},
-	{"PES"                         ,	1,	1,	1173,	"R/W",	0,	1,	0ull,	0},
-	{"PSS"                         ,	2,	1,	1173,	"R/W",	0,	1,	0ull,	0},
-	{"POCI"                        ,	3,	1,	1173,	"R/W",	0,	1,	0ull,	0},
-	{"PRS"                         ,	4,	1,	1173,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_5_7"                ,	5,	3,	1173,	"R/W",	0,	0,	0ull,	0ull},
-	{"PPS"                         ,	8,	1,	1173,	"R/W",	0,	1,	0ull,	0},
-	{"LSDA"                        ,	9,	1,	1173,	"R/W",	1,	1,	0,	0},
-	{"RESERVED_10_15"              ,	10,	6,	1173,	"R/W",	0,	0,	0ull,	0ull},
-	{"CSC"                         ,	16,	1,	1173,	"R/W",	0,	1,	0ull,	0},
-	{"PESC"                        ,	17,	1,	1173,	"R/W",	0,	1,	0ull,	0},
-	{"PSSC"                        ,	18,	1,	1173,	"R/W",	0,	1,	0ull,	0},
-	{"OCIC"                        ,	19,	1,	1173,	"R/W",	0,	1,	0ull,	0},
-	{"PRSC"                        ,	20,	1,	1173,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_21_31"              ,	21,	11,	1173,	"R/W",	0,	0,	0ull,	0ull},
-	{"LPS"                         ,	0,	1,	1174,	"R/W",	0,	0,	0ull,	0ull},
-	{"OCI"                         ,	1,	1,	1174,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_14"               ,	2,	13,	1174,	"RO",	0,	0,	0ull,	0ull},
-	{"DRWE"                        ,	15,	1,	1174,	"R/W",	0,	1,	0ull,	0},
-	{"LPSC"                        ,	16,	1,	1174,	"R/W",	0,	1,	0ull,	0},
-	{"CCIC"                        ,	17,	1,	1174,	"R/W1C",	0,	1,	0ull,	0},
-	{"RESERVED_18_30"              ,	18,	13,	1174,	"RO",	0,	0,	0ull,	0ull},
-	{"CRWE"                        ,	31,	1,	1174,	"WO",	1,	1,	0,	0},
-	{"RESERVED_0_30"               ,	0,	31,	1175,	"R/W",	0,	0,	0ull,	0ull},
-	{"VLD"                         ,	31,	1,	1175,	"R/W",	0,	0,	0ull,	0ull},
-	{"ERR_ADDR"                    ,	0,	32,	1176,	"RO",	0,	0,	0ull,	0ull},
-	{"PPAF_BIS"                    ,	0,	1,	1177,	"RO",	0,	0,	0ull,	0ull},
-	{"WRBM_BIS"                    ,	1,	1,	1177,	"RO",	0,	0,	0ull,	0ull},
-	{"ORBM_BIS"                    ,	2,	1,	1177,	"RO",	0,	0,	0ull,	0ull},
-	{"ERBM_BIS"                    ,	3,	1,	1177,	"RO",	0,	0,	0ull,	0ull},
-	{"DESC_BIS"                    ,	4,	1,	1177,	"RO",	0,	0,	0ull,	0ull},
-	{"DATA_BIS"                    ,	5,	1,	1177,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	1177,	"RO",	1,	1,	0,	0},
-	{"HRST"                        ,	0,	1,	1178,	"R/W",	0,	0,	0ull,	1ull},
-	{"P_PRST"                      ,	1,	1,	1178,	"R/W",	0,	0,	0ull,	1ull},
-	{"P_POR"                       ,	2,	1,	1178,	"R/W",	0,	0,	1ull,	0ull},
-	{"P_COM_ON"                    ,	3,	1,	1178,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_4"                ,	4,	1,	1178,	"R/W",	0,	1,	0ull,	0},
-	{"P_REFCLK_DIV"                ,	5,	2,	1178,	"R/W",	0,	0,	0ull,	0ull},
-	{"P_REFCLK_SEL"                ,	7,	2,	1178,	"R/W",	0,	0,	0ull,	0ull},
-	{"H_DIV"                       ,	9,	4,	1178,	"R/W",	0,	0,	6ull,	6ull},
-	{"O_CLKDIV_EN"                 ,	13,	1,	1178,	"R/W",	0,	0,	0ull,	1ull},
-	{"H_CLKDIV_EN"                 ,	14,	1,	1178,	"R/W",	0,	0,	0ull,	1ull},
-	{"H_CLKDIV_RST"                ,	15,	1,	1178,	"R/W",	0,	0,	0ull,	1ull},
-	{"H_CLKDIV_BYP"                ,	16,	1,	1178,	"R/W",	0,	0,	0ull,	0ull},
-	{"O_CLKDIV_RST"                ,	17,	1,	1178,	"R/W",	0,	0,	0ull,	1ull},
-	{"APP_START_CLK"               ,	18,	1,	1178,	"R/W",	0,	0,	0ull,	0ull},
-	{"OHCI_SUSP_LGCY"              ,	19,	1,	1178,	"R/W",	0,	0,	1ull,	1ull},
-	{"OHCI_SM"                     ,	20,	1,	1178,	"R/W",	0,	0,	0ull,	0ull},
-	{"OHCI_CLKCKTRST"              ,	21,	1,	1178,	"R/W",	0,	0,	1ull,	1ull},
-	{"EHCI_SM"                     ,	22,	1,	1178,	"R/W",	0,	0,	0ull,	0ull},
-	{"START_BIST"                  ,	23,	1,	1178,	"R/W",	0,	0,	0ull,	0ull},
-	{"CLEAR_BIST"                  ,	24,	1,	1178,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_25_63"              ,	25,	39,	1178,	"RAZ",	1,	1,	0,	0},
-	{"L2C_ADDR_MSB"                ,	0,	8,	1179,	"R/W",	0,	1,	0ull,	0},
-	{"EHCI_64B_ADDR_EN"            ,	8,	1,	1179,	"R/W",	0,	0,	1ull,	1ull},
-	{"INV_REG_A2"                  ,	9,	1,	1179,	"R/W",	0,	0,	0ull,	0ull},
-	{"L2C_DESC_EMOD"               ,	10,	2,	1179,	"R/W",	0,	0,	0ull,	0ull},
-	{"L2C_BUFF_EMOD"               ,	12,	2,	1179,	"R/W",	0,	0,	1ull,	1ull},
-	{"L2C_STT"                     ,	14,	1,	1179,	"R/W",	0,	0,	0ull,	0ull},
-	{"L2C_0PAG"                    ,	15,	1,	1179,	"R/W",	0,	0,	0ull,	0ull},
-	{"L2C_BC"                      ,	16,	1,	1179,	"R/W",	0,	0,	0ull,	0ull},
-	{"L2C_DC"                      ,	17,	1,	1179,	"R/W",	0,	0,	1ull,	1ull},
-	{"REG_NB"                      ,	18,	1,	1179,	"R/W",	0,	0,	0ull,	0ull},
-	{"DESC_RBM"                    ,	19,	1,	1179,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_20_63"              ,	20,	44,	1179,	"RAZ",	1,	1,	0,	0},
-	{"FLA"                         ,	0,	6,	1180,	"R/W",	0,	0,	32ull,	32ull},
-	{"RESERVED_6_63"               ,	6,	58,	1180,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_4"                ,	0,	5,	1181,	"RAZ",	1,	1,	0,	0},
-	{"TO_VAL"                      ,	5,	27,	1181,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	1181,	"RAZ",	1,	1,	0,	0},
-	{"EN"                          ,	0,	1,	1182,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_1_63"               ,	1,	63,	1182,	"RAZ",	1,	1,	0,	0},
-	{"PP_PSH_F"                    ,	0,	1,	1183,	"R/W",	0,	0,	0ull,	0ull},
-	{"ER_PSH_F"                    ,	1,	1,	1183,	"R/W",	0,	0,	0ull,	0ull},
-	{"OR_PSH_F"                    ,	2,	1,	1183,	"R/W",	0,	0,	0ull,	0ull},
-	{"CF_PSH_F"                    ,	3,	1,	1183,	"R/W",	0,	0,	0ull,	0ull},
-	{"WB_PSH_F"                    ,	4,	1,	1183,	"R/W",	0,	0,	0ull,	0ull},
-	{"WB_POP_E"                    ,	5,	1,	1183,	"R/W",	0,	0,	0ull,	0ull},
-	{"OC_OVF_E"                    ,	6,	1,	1183,	"R/W",	0,	0,	0ull,	0ull},
-	{"EC_OVF_E"                    ,	7,	1,	1183,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_8_63"               ,	8,	56,	1183,	"RAZ",	1,	1,	0,	0},
-	{"PP_PSH_F"                    ,	0,	1,	1184,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"ER_PSH_F"                    ,	1,	1,	1184,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"OR_PSH_F"                    ,	2,	1,	1184,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"CF_PSH_F"                    ,	3,	1,	1184,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"WB_PSH_F"                    ,	4,	1,	1184,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"WB_POP_E"                    ,	5,	1,	1184,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"OC_OVF_E"                    ,	6,	1,	1184,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"EC_OVF_E"                    ,	7,	1,	1184,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_8_63"               ,	8,	56,	1184,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	38,	1133,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1133,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1134,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1134,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1134,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1134,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1134,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1135,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1135,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1135,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1135,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1135,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1135,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1135,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1135,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1135,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1135,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1135,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1135,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1135,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1135,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1135,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1135,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1135,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1135,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1135,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1135,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	8,	1136,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1136,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1136,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1136,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1136,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1136,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1136,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1137,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1137,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1138,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1139,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1140,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1140,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1140,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1140,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1140,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1140,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1140,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1140,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1140,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1140,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1140,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1140,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1140,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1140,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1140,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1140,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1140,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1140,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1140,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1140,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	8,	1141,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1141,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1141,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1141,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1141,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1141,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1141,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	1142,	"R/W",	0,	1,	0ull,	0},
+	{"LPL"                         ,	5,	27,	1142,	"R/W",	0,	1,	0ull,	0},
+	{"CF"                          ,	0,	1,	1143,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_31"               ,	1,	31,	1143,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTRLDSSEG"                   ,	0,	32,	1144,	"R/W",	0,	1,	0ull,	0},
+	{"FI"                          ,	0,	14,	1145,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_31"              ,	14,	18,	1145,	"RO",	0,	0,	0ull,	0ull},
+	{"CAPLENGTH"                   ,	0,	8,	1146,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_8_15"               ,	8,	8,	1146,	"RO",	0,	0,	0ull,	0ull},
+	{"HCIVERSION"                  ,	16,	16,	1146,	"RO",	0,	0,	256ull,	256ull},
+	{"AC64"                        ,	0,	1,	1147,	"RO",	0,	0,	1ull,	1ull},
+	{"PFLF"                        ,	1,	1,	1147,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPC"                        ,	2,	1,	1147,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1147,	"RO",	0,	0,	0ull,	0ull},
+	{"IST"                         ,	4,	4,	1147,	"RO",	0,	0,	2ull,	2ull},
+	{"EECP"                        ,	8,	8,	1147,	"RO",	0,	0,	160ull,	160ull},
+	{"RESERVED_16_31"              ,	16,	16,	1147,	"RO",	0,	0,	0ull,	0ull},
+	{"N_PORTS"                     ,	0,	4,	1148,	"RO",	0,	0,	2ull,	2ull},
+	{"PPC"                         ,	4,	1,	1148,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	1148,	"RO",	0,	0,	0ull,	0ull},
+	{"PRR"                         ,	7,	1,	1148,	"RO",	0,	0,	0ull,	0ull},
+	{"N_PCC"                       ,	8,	4,	1148,	"RO",	0,	0,	2ull,	2ull},
+	{"N_CC"                        ,	12,	4,	1148,	"RO",	0,	0,	1ull,	1ull},
+	{"P_INDICATOR"                 ,	16,	1,	1148,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	1148,	"RO",	0,	0,	0ull,	0ull},
+	{"DPN"                         ,	20,	4,	1148,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1148,	"RO",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	0,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"MFMC"                        ,	1,	13,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_0"                ,	0,	1,	1150,	"R/W",	0,	0,	0ull,	0ull},
+	{"TA_OFF"                      ,	1,	8,	1150,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	1150,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXTX_TADAO"                  ,	10,	3,	1150,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	1150,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCP_RW"                      ,	0,	1,	1151,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCP_FW"                      ,	1,	1,	1151,	"R/W",	0,	0,	0ull,	0ull},
+	{"PESD"                        ,	2,	1,	1151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1151,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NAKRF_DIS"                   ,	4,	1,	1151,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTO_DIS"                    ,	5,	1,	1151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	1151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_30"               ,	0,	31,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	31,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_ADDR"                    ,	0,	32,	1153,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_11"               ,	0,	12,	1154,	"R/W",	0,	1,	0ull,	0},
+	{"BADDR"                       ,	12,	20,	1154,	"R/W",	0,	1,	0ull,	0},
+	{"CCS"                         ,	0,	1,	1155,	"RO",	0,	0,	0ull,	0ull},
+	{"CSC"                         ,	1,	1,	1155,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PED"                         ,	2,	1,	1155,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEDC"                        ,	3,	1,	1155,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OCA"                         ,	4,	1,	1155,	"RO",	0,	0,	0ull,	0ull},
+	{"OCC"                         ,	5,	1,	1155,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPR"                         ,	6,	1,	1155,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPD"                         ,	7,	1,	1155,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRST"                        ,	8,	1,	1155,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	1155,	"RO",	0,	0,	0ull,	0ull},
+	{"LSTS"                        ,	10,	2,	1155,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	12,	1,	1155,	"RO",	0,	0,	1ull,	1ull},
+	{"PO"                          ,	13,	1,	1155,	"R/W",	0,	0,	1ull,	0ull},
+	{"PIC"                         ,	14,	2,	1155,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTC"                         ,	16,	4,	1155,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKCNNT_E"                    ,	20,	1,	1155,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKDSCNNT_E"                  ,	21,	1,	1155,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKOC_E"                      ,	22,	1,	1155,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	1155,	"RO",	0,	0,	0ull,	0ull},
+	{"RS"                          ,	0,	1,	1156,	"R/W",	0,	0,	0ull,	1ull},
+	{"HCRESET"                     ,	1,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
+	{"FLS"                         ,	2,	2,	1156,	"RO",	0,	0,	0ull,	0ull},
+	{"PS_EN"                       ,	4,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
+	{"AS_EN"                       ,	5,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
+	{"IAA_DB"                      ,	6,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
+	{"LHCR"                        ,	7,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASPMC"                       ,	8,	2,	1156,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	1156,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPM_EN"                     ,	11,	1,	1156,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	1156,	"RO",	0,	0,	0ull,	0ull},
+	{"ITC"                         ,	16,	8,	1156,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_24_31"              ,	24,	8,	1156,	"RO",	0,	0,	0ull,	0ull},
+	{"USBINT_EN"                   ,	0,	1,	1157,	"R/W",	0,	1,	0ull,	0},
+	{"USBERRINT_EN"                ,	1,	1,	1157,	"R/W",	0,	1,	0ull,	0},
+	{"PCI_EN"                      ,	2,	1,	1157,	"R/W",	0,	1,	0ull,	0},
+	{"FLRO_EN"                     ,	3,	1,	1157,	"R/W",	0,	1,	0ull,	0},
+	{"HSERR_EN"                    ,	4,	1,	1157,	"R/W",	0,	1,	0ull,	0},
+	{"IOAA_EN"                     ,	5,	1,	1157,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_31"               ,	6,	26,	1157,	"RO",	0,	0,	0ull,	0ull},
+	{"USBINT"                      ,	0,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBERRINT"                   ,	1,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCD"                         ,	2,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FLRO"                        ,	3,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HSYSERR"                     ,	4,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOAA"                        ,	5,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	1158,	"RO",	0,	0,	0ull,	0ull},
+	{"HCHTD"                       ,	12,	1,	1158,	"RO",	0,	0,	1ull,	0ull},
+	{"RECLM"                       ,	13,	1,	1158,	"RO",	0,	0,	0ull,	0ull},
+	{"PSS"                         ,	14,	1,	1158,	"RO",	0,	0,	0ull,	0ull},
+	{"ASS"                         ,	15,	1,	1158,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1158,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1159,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCED"                        ,	4,	28,	1159,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1160,	"R/W",	0,	0,	0ull,	0ull},
+	{"BHED"                        ,	4,	28,	1160,	"R/W",	0,	1,	0ull,	0},
+	{"HCR"                         ,	0,	1,	1161,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLF"                         ,	1,	1,	1161,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLF"                         ,	2,	1,	1161,	"R/W",	0,	0,	0ull,	0ull},
+	{"OCR"                         ,	3,	1,	1161,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	1161,	"RO",	0,	0,	0ull,	0ull},
+	{"SOC"                         ,	16,	2,	1161,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	1161,	"RO",	0,	0,	0ull,	0ull},
+	{"CBSR"                        ,	0,	2,	1162,	"R/W",	0,	1,	0ull,	0},
+	{"PLE"                         ,	2,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
+	{"IE"                          ,	3,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLE"                         ,	4,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLE"                         ,	5,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCFS"                        ,	6,	2,	1162,	"R/W",	0,	0,	0ull,	0ull},
+	{"IR"                          ,	8,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWC"                         ,	9,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWE"                         ,	10,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	1162,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCED"                        ,	4,	28,	1163,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1164,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHED"                        ,	4,	28,	1164,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1165,	"RO",	0,	0,	0ull,	0ull},
+	{"DH"                          ,	4,	28,	1165,	"RO",	0,	1,	0ull,	0},
+	{"FI"                          ,	0,	14,	1166,	"R/W",	0,	1,	11999ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	1166,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSMPS"                       ,	16,	15,	1166,	"R/W",	0,	1,	0ull,	0},
+	{"FIT"                         ,	31,	1,	1166,	"R/W",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	0,	16,	1167,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	1167,	"RO",	0,	0,	0ull,	0ull},
+	{"FR"                          ,	0,	14,	1168,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_30"              ,	14,	17,	1168,	"RO",	0,	0,	0ull,	0ull},
+	{"FRT"                         ,	31,	1,	1168,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	1169,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCCA"                        ,	8,	24,	1169,	"R/W",	0,	1,	0ull,	0},
+	{"SO"                          ,	0,	1,	1170,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1170,	"R/W",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1170,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1170,	"R/W",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1170,	"R/W",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1170,	"R/W",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1170,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1170,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1170,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIE"                         ,	31,	1,	1170,	"R/W",	0,	0,	0ull,	0ull},
+	{"SO"                          ,	0,	1,	1171,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1171,	"R/W",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1171,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1171,	"R/W",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1171,	"R/W",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1171,	"R/W",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1171,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1171,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1171,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIE"                         ,	31,	1,	1171,	"R/W",	0,	0,	0ull,	0ull},
+	{"SO"                          ,	0,	1,	1172,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1172,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1172,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1172,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1172,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1172,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1172,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1172,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1172,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1172,	"RO",	0,	0,	0ull,	0ull},
+	{"LST"                         ,	0,	12,	1173,	"R/W",	0,	1,	1576ull,	0},
+	{"RESERVED_12_31"              ,	12,	20,	1173,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1174,	"RO",	0,	0,	0ull,	0ull},
+	{"PCED"                        ,	4,	28,	1174,	"RO",	0,	1,	0ull,	0},
+	{"PS"                          ,	0,	14,	1175,	"R/W",	0,	0,	0ull,	15975ull},
+	{"RESERVED_14_31"              ,	14,	18,	1175,	"R/W",	0,	0,	0ull,	0ull},
+	{"REV"                         ,	0,	8,	1176,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_8_31"               ,	8,	24,	1176,	"RO",	0,	0,	0ull,	0ull},
+	{"NDP"                         ,	0,	8,	1177,	"RO",	0,	0,	2ull,	2ull},
+	{"NPS"                         ,	8,	1,	1177,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSM"                         ,	9,	1,	1177,	"R/W",	0,	0,	1ull,	1ull},
+	{"DT"                          ,	10,	1,	1177,	"RO",	0,	0,	0ull,	0ull},
+	{"OCPM"                        ,	11,	1,	1177,	"R/W",	1,	1,	0,	0},
+	{"NOCP"                        ,	12,	1,	1177,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_23"              ,	13,	11,	1177,	"RO",	0,	0,	0ull,	0ull},
+	{"POTPGT"                      ,	24,	8,	1177,	"R/W",	0,	0,	1ull,	1ull},
+	{"DR"                          ,	0,	16,	1178,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPCM"                        ,	16,	16,	1178,	"R/W",	0,	1,	0ull,	0},
+	{"CCS"                         ,	0,	1,	1179,	"R/W",	0,	1,	0ull,	0},
+	{"PES"                         ,	1,	1,	1179,	"R/W",	0,	1,	0ull,	0},
+	{"PSS"                         ,	2,	1,	1179,	"R/W",	0,	1,	0ull,	0},
+	{"POCI"                        ,	3,	1,	1179,	"R/W",	0,	1,	0ull,	0},
+	{"PRS"                         ,	4,	1,	1179,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1179,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS"                         ,	8,	1,	1179,	"R/W",	0,	1,	0ull,	0},
+	{"LSDA"                        ,	9,	1,	1179,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_10_15"              ,	10,	6,	1179,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSC"                         ,	16,	1,	1179,	"R/W",	0,	1,	0ull,	0},
+	{"PESC"                        ,	17,	1,	1179,	"R/W",	0,	1,	0ull,	0},
+	{"PSSC"                        ,	18,	1,	1179,	"R/W",	0,	1,	0ull,	0},
+	{"OCIC"                        ,	19,	1,	1179,	"R/W",	0,	1,	0ull,	0},
+	{"PRSC"                        ,	20,	1,	1179,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_31"              ,	21,	11,	1179,	"R/W",	0,	0,	0ull,	0ull},
+	{"LPS"                         ,	0,	1,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"OCI"                         ,	1,	1,	1180,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_14"               ,	2,	13,	1180,	"RO",	0,	0,	0ull,	0ull},
+	{"DRWE"                        ,	15,	1,	1180,	"R/W",	0,	1,	0ull,	0},
+	{"LPSC"                        ,	16,	1,	1180,	"R/W",	0,	1,	0ull,	0},
+	{"CCIC"                        ,	17,	1,	1180,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_18_30"              ,	18,	13,	1180,	"RO",	0,	0,	0ull,	0ull},
+	{"CRWE"                        ,	31,	1,	1180,	"WO",	1,	1,	0,	0},
+	{"RESERVED_0_30"               ,	0,	31,	1181,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	31,	1,	1181,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_ADDR"                    ,	0,	32,	1182,	"RO",	0,	0,	0ull,	0ull},
+	{"PPAF_BIS"                    ,	0,	1,	1183,	"RO",	0,	0,	0ull,	0ull},
+	{"WRBM_BIS"                    ,	1,	1,	1183,	"RO",	0,	0,	0ull,	0ull},
+	{"ORBM_BIS"                    ,	2,	1,	1183,	"RO",	0,	0,	0ull,	0ull},
+	{"ERBM_BIS"                    ,	3,	1,	1183,	"RO",	0,	0,	0ull,	0ull},
+	{"DESC_BIS"                    ,	4,	1,	1183,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_BIS"                    ,	5,	1,	1183,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1183,	"RO",	1,	1,	0,	0},
+	{"HRST"                        ,	0,	1,	1184,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_PRST"                      ,	1,	1,	1184,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_POR"                       ,	2,	1,	1184,	"R/W",	0,	0,	1ull,	0ull},
+	{"P_COM_ON"                    ,	3,	1,	1184,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	1184,	"R/W",	0,	1,	0ull,	0},
+	{"P_REFCLK_DIV"                ,	5,	2,	1184,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_REFCLK_SEL"                ,	7,	2,	1184,	"R/W",	0,	0,	0ull,	0ull},
+	{"H_DIV"                       ,	9,	4,	1184,	"R/W",	0,	0,	6ull,	6ull},
+	{"O_CLKDIV_EN"                 ,	13,	1,	1184,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_EN"                 ,	14,	1,	1184,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_RST"                ,	15,	1,	1184,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_BYP"                ,	16,	1,	1184,	"R/W",	0,	0,	0ull,	0ull},
+	{"O_CLKDIV_RST"                ,	17,	1,	1184,	"R/W",	0,	0,	0ull,	1ull},
+	{"APP_START_CLK"               ,	18,	1,	1184,	"R/W",	0,	0,	0ull,	0ull},
+	{"OHCI_SUSP_LGCY"              ,	19,	1,	1184,	"R/W",	0,	0,	1ull,	1ull},
+	{"OHCI_SM"                     ,	20,	1,	1184,	"R/W",	0,	0,	0ull,	0ull},
+	{"OHCI_CLKCKTRST"              ,	21,	1,	1184,	"R/W",	0,	0,	1ull,	1ull},
+	{"EHCI_SM"                     ,	22,	1,	1184,	"R/W",	0,	0,	0ull,	0ull},
+	{"START_BIST"                  ,	23,	1,	1184,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLEAR_BIST"                  ,	24,	1,	1184,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1184,	"RAZ",	1,	1,	0,	0},
 	{"L2C_ADDR_MSB"                ,	0,	8,	1185,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_8_8"                ,	8,	1,	1185,	"RAZ",	1,	1,	0,	0},
+	{"EHCI_64B_ADDR_EN"            ,	8,	1,	1185,	"R/W",	0,	0,	1ull,	1ull},
 	{"INV_REG_A2"                  ,	9,	1,	1185,	"R/W",	0,	0,	0ull,	0ull},
 	{"L2C_DESC_EMOD"               ,	10,	2,	1185,	"R/W",	0,	0,	0ull,	0ull},
 	{"L2C_BUFF_EMOD"               ,	12,	2,	1185,	"R/W",	0,	0,	1ull,	1ull},
@@ -105379,68 +120467,113985 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
 	{"L2C_BC"                      ,	16,	1,	1185,	"R/W",	0,	0,	0ull,	0ull},
 	{"L2C_DC"                      ,	17,	1,	1185,	"R/W",	0,	0,	1ull,	1ull},
 	{"REG_NB"                      ,	18,	1,	1185,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_19_63"              ,	19,	45,	1185,	"RAZ",	1,	1,	0,	0},
-	{"RESERVED_0_7"                ,	0,	8,	1186,	"RAZ",	1,	1,	0,	0},
-	{"TO_VAL"                      ,	8,	24,	1186,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	1186,	"RAZ",	1,	1,	0,	0},
-	{"WM"                          ,	0,	5,	1187,	"R/W",	0,	0,	8ull,	8ull},
-	{"RESERVED_5_63"               ,	5,	59,	1187,	"RAZ",	1,	1,	0,	0},
-	{"ATE_RESET"                   ,	0,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
-	{"BIST_EN"                     ,	1,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
-	{"UPHY_BIST"                   ,	2,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
-	{"VTEST_EN"                    ,	3,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
-	{"SIDDQ"                       ,	4,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
-	{"LSBIST"                      ,	5,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
-	{"FSBIST"                      ,	6,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
-	{"HSBIST"                      ,	7,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
-	{"BIST_ERR"                    ,	8,	1,	1188,	"RO",	0,	0,	0ull,	0ull},
-	{"BIST_DONE"                   ,	9,	1,	1188,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_63"              ,	10,	54,	1188,	"RAZ",	1,	1,	0,	0},
-	{"TDATA_IN"                    ,	0,	8,	1189,	"R/W",	0,	0,	0ull,	0ull},
-	{"TADDR_IN"                    ,	8,	4,	1189,	"R/W",	0,	0,	0ull,	0ull},
-	{"TDATA_SEL"                   ,	12,	1,	1189,	"R/W",	0,	0,	1ull,	0ull},
-	{"TCLK"                        ,	13,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
-	{"LOOP_EN"                     ,	14,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
-	{"COMPDISTUNE"                 ,	15,	3,	1189,	"R/W",	0,	0,	4ull,	4ull},
-	{"SQRXTUNE"                    ,	18,	3,	1189,	"R/W",	0,	0,	4ull,	4ull},
-	{"TXFSLSTUNE"                  ,	21,	4,	1189,	"R/W",	0,	0,	3ull,	3ull},
-	{"TXPREEMPHASISTUNE"           ,	25,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
-	{"TXRISETUNE"                  ,	26,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
-	{"TXVREFTUNE"                  ,	27,	4,	1189,	"R/W",	0,	0,	5ull,	5ull},
-	{"TXHSVXTUNE"                  ,	31,	2,	1189,	"R/W",	0,	0,	0ull,	0ull},
-	{"PORTRESET"                   ,	33,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
-	{"VBUSVLDEXT"                  ,	34,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
-	{"DPPULLDOWN"                  ,	35,	1,	1189,	"R/W",	0,	0,	1ull,	1ull},
-	{"DMPULLDOWN"                  ,	36,	1,	1189,	"R/W",	0,	0,	1ull,	1ull},
-	{"TXBISTSTUFFEN"               ,	37,	1,	1189,	"R/W",	0,	0,	1ull,	1ull},
-	{"TXBISTSTUFFENH"              ,	38,	1,	1189,	"R/W",	0,	0,	1ull,	1ull},
-	{"TDATA_OUT"                   ,	39,	4,	1189,	"RO",	1,	1,	0,	0},
-	{"RESERVED_43_63"              ,	43,	21,	1189,	"RAZ",	1,	1,	0,	0},
-	{"ZIP_CTL"                     ,	0,	4,	1190,	"RO",	1,	0,	0,	0ull},
-	{"ZIP_CORE"                    ,	4,	39,	1190,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_43_63"              ,	43,	21,	1190,	"RAZ",	1,	1,	0,	0},
-	{"PTR"                         ,	0,	33,	1191,	"R/W",	0,	0,	0ull,	0ull},
-	{"SIZE"                        ,	33,	13,	1191,	"R/W",	0,	0,	0ull,	0ull},
-	{"POOL"                        ,	46,	3,	1191,	"R/W",	0,	0,	0ull,	0ull},
-	{"DWB"                         ,	49,	9,	1191,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_58_63"              ,	58,	6,	1191,	"RAZ",	1,	1,	0,	0},
-	{"RESET"                       ,	0,	1,	1192,	"RAZ",	0,	0,	0ull,	0ull},
-	{"FORCECLK"                    ,	1,	1,	1192,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	1192,	"RAZ",	1,	1,	0,	0},
-	{"DISABLED"                    ,	0,	1,	1193,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_7"                ,	1,	7,	1193,	"RAZ",	1,	1,	0,	0},
-	{"CTXSIZE"                     ,	8,	12,	1193,	"RO",	0,	0,	1536ull,	1536ull},
-	{"ONFSIZE"                     ,	20,	12,	1193,	"RO",	0,	0,	512ull,	512ull},
-	{"DEPTH"                       ,	32,	16,	1193,	"RO",	0,	0,	31744ull,	31744ull},
-	{"RESERVED_48_63"              ,	48,	16,	1193,	"RAZ",	1,	1,	0,	0},
-	{"ASSERTS"                     ,	0,	17,	1194,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_17_63"              ,	17,	47,	1194,	"RAZ",	1,	1,	0,	0},
-	{"DOORBELL"                    ,	0,	1,	1195,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	1195,	"RAZ",	1,	1,	0,	0},
-	{"DOORBELL"                    ,	0,	1,	1196,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	1196,	"RAZ",	1,	1,	0,	0},
-	{"MAX_INFL"                    ,	0,	4,	1197,	"R/W",	0,	0,	8ull,	8ull},
-	{"RESERVED_4_63"               ,	4,	60,	1197,	"RAZ",	1,	1,	0,	0},
+	{"DESC_RBM"                    ,	19,	1,	1185,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1185,	"RAZ",	1,	1,	0,	0},
+	{"FLA"                         ,	0,	6,	1186,	"R/W",	0,	0,	0ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	1186,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	1187,	"RAZ",	1,	1,	0,	0},
+	{"TO_VAL"                      ,	5,	27,	1187,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1187,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	1188,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	1188,	"RAZ",	1,	1,	0,	0},
+	{"PP_PSH_F"                    ,	0,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"ER_PSH_F"                    ,	1,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"OR_PSH_F"                    ,	2,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"CF_PSH_F"                    ,	3,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"WB_PSH_F"                    ,	4,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"WB_POP_E"                    ,	5,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"OC_OVF_E"                    ,	6,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"EC_OVF_E"                    ,	7,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1189,	"RAZ",	1,	1,	0,	0},
+	{"PP_PSH_F"                    ,	0,	1,	1190,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ER_PSH_F"                    ,	1,	1,	1190,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OR_PSH_F"                    ,	2,	1,	1190,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CF_PSH_F"                    ,	3,	1,	1190,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WB_PSH_F"                    ,	4,	1,	1190,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WB_POP_E"                    ,	5,	1,	1190,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OC_OVF_E"                    ,	6,	1,	1190,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EC_OVF_E"                    ,	7,	1,	1190,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1190,	"RAZ",	1,	1,	0,	0},
+	{"L2C_ADDR_MSB"                ,	0,	8,	1191,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_8"                ,	8,	1,	1191,	"RAZ",	1,	1,	0,	0},
+	{"INV_REG_A2"                  ,	9,	1,	1191,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DESC_EMOD"               ,	10,	2,	1191,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BUFF_EMOD"               ,	12,	2,	1191,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2C_STT"                     ,	14,	1,	1191,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_0PAG"                    ,	15,	1,	1191,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BC"                      ,	16,	1,	1191,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DC"                      ,	17,	1,	1191,	"R/W",	0,	0,	1ull,	1ull},
+	{"REG_NB"                      ,	18,	1,	1191,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	1191,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1192,	"RAZ",	1,	1,	0,	0},
+	{"TO_VAL"                      ,	8,	24,	1192,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1192,	"RAZ",	1,	1,	0,	0},
+	{"WM"                          ,	0,	5,	1193,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_5_63"               ,	5,	59,	1193,	"RAZ",	1,	1,	0,	0},
+	{"ATE_RESET"                   ,	0,	1,	1194,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_EN"                     ,	1,	1,	1194,	"R/W",	0,	0,	0ull,	0ull},
+	{"UPHY_BIST"                   ,	2,	1,	1194,	"R/W",	0,	0,	0ull,	0ull},
+	{"VTEST_EN"                    ,	3,	1,	1194,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIDDQ"                       ,	4,	1,	1194,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBIST"                      ,	5,	1,	1194,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSBIST"                      ,	6,	1,	1194,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSBIST"                      ,	7,	1,	1194,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_ERR"                    ,	8,	1,	1194,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST_DONE"                   ,	9,	1,	1194,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1194,	"RAZ",	1,	1,	0,	0},
+	{"TDATA_IN"                    ,	0,	8,	1195,	"R/W",	0,	0,	0ull,	0ull},
+	{"TADDR_IN"                    ,	8,	4,	1195,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_SEL"                   ,	12,	1,	1195,	"R/W",	0,	0,	1ull,	0ull},
+	{"TCLK"                        ,	13,	1,	1195,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOP_EN"                     ,	14,	1,	1195,	"R/W",	0,	0,	0ull,	0ull},
+	{"COMPDISTUNE"                 ,	15,	3,	1195,	"R/W",	0,	0,	4ull,	4ull},
+	{"SQRXTUNE"                    ,	18,	3,	1195,	"R/W",	0,	0,	4ull,	4ull},
+	{"TXFSLSTUNE"                  ,	21,	4,	1195,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPREEMPHASISTUNE"           ,	25,	1,	1195,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXRISETUNE"                  ,	26,	1,	1195,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXVREFTUNE"                  ,	27,	4,	1195,	"R/W",	0,	0,	5ull,	15ull},
+	{"TXHSVXTUNE"                  ,	31,	2,	1195,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORTRESET"                   ,	33,	1,	1195,	"R/W",	0,	0,	0ull,	0ull},
+	{"VBUSVLDEXT"                  ,	34,	1,	1195,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPPULLDOWN"                  ,	35,	1,	1195,	"R/W",	0,	0,	1ull,	1ull},
+	{"DMPULLDOWN"                  ,	36,	1,	1195,	"R/W",	0,	0,	1ull,	1ull},
+	{"TXBISTSTUFFEN"               ,	37,	1,	1195,	"R/W",	0,	0,	1ull,	1ull},
+	{"TXBISTSTUFFENH"              ,	38,	1,	1195,	"R/W",	0,	0,	1ull,	1ull},
+	{"TDATA_OUT"                   ,	39,	4,	1195,	"RO",	1,	1,	0,	0},
+	{"RESERVED_43_63"              ,	43,	21,	1195,	"RAZ",	1,	1,	0,	0},
+	{"ZIP_CTL"                     ,	0,	4,	1196,	"RO",	1,	0,	0,	0ull},
+	{"ZIP_CORE"                    ,	4,	53,	1196,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_57_63"              ,	57,	7,	1196,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	1197,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	33,	13,	1197,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	46,	3,	1197,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	49,	9,	1197,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	1197,	"RAZ",	1,	1,	0,	0},
+	{"RESET"                       ,	0,	1,	1198,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FORCECLK"                    ,	1,	1,	1198,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1198,	"RAZ",	1,	1,	0,	0},
+	{"DISABLED"                    ,	0,	1,	1199,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	1199,	"RAZ",	1,	1,	0,	0},
+	{"CTXSIZE"                     ,	8,	12,	1199,	"RO",	0,	0,	1536ull,	1536ull},
+	{"ONFSIZE"                     ,	20,	12,	1199,	"RO",	0,	0,	512ull,	512ull},
+	{"DEPTH"                       ,	32,	16,	1199,	"RO",	0,	0,	31744ull,	31744ull},
+	{"RESERVED_48_63"              ,	48,	16,	1199,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	17,	1200,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	1200,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1201,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1201,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1202,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1202,	"RAZ",	1,	1,	0,	0},
+	{"MAX_INFL"                    ,	0,	4,	1203,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	1203,	"RAZ",	1,	1,	0,	0},
+	{NULL,0,0,0,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn66xx[] = {
+	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
+	{"cvmx_agl_gmx_bad_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	0,	14,	0},
+	{"cvmx_agl_gmx_bist"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1,	2,	14},
+	{"cvmx_agl_gmx_prt#_cfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2,	13,	16},
+	{"cvmx_agl_gmx_rx#_adr_cam0"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	4,	1,	29},
+	{"cvmx_agl_gmx_rx#_adr_cam1"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	6,	1,	30},
+	{"cvmx_agl_gmx_rx#_adr_cam2"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8,	1,	31},
+	{"cvmx_agl_gmx_rx#_adr_cam3"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	10,	1,	32},
+	{"cvmx_agl_gmx_rx#_adr_cam4"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	12,	1,	33},
+	{"cvmx_agl_gmx_rx#_adr_cam5"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	14,	1,	34},
+	{"cvmx_agl_gmx_rx#_adr_cam_en" ,	CVMX_CSR_DB_TYPE_RSL,	64,	16,	2,	35},
+	{"cvmx_agl_gmx_rx#_adr_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	18,	4,	37},
+	{"cvmx_agl_gmx_rx#_decision"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	20,	2,	41},
+	{"cvmx_agl_gmx_rx#_frm_chk"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	22,	11,	43},
+	{"cvmx_agl_gmx_rx#_frm_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	24,	14,	54},
+	{"cvmx_agl_gmx_rx#_frm_max"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26,	2,	68},
+	{"cvmx_agl_gmx_rx#_frm_min"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	28,	2,	70},
+	{"cvmx_agl_gmx_rx#_ifg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	30,	2,	72},
+	{"cvmx_agl_gmx_rx#_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	32,	21,	74},
+	{"cvmx_agl_gmx_rx#_int_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	34,	21,	95},
+	{"cvmx_agl_gmx_rx#_jabber"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	36,	2,	116},
+	{"cvmx_agl_gmx_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	38,	2,	118},
+	{"cvmx_agl_gmx_rx#_rx_inbnd"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	40,	4,	120},
+	{"cvmx_agl_gmx_rx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	42,	2,	124},
+	{"cvmx_agl_gmx_rx#_stats_octs" ,	CVMX_CSR_DB_TYPE_RSL,	64,	44,	2,	126},
+	{"cvmx_agl_gmx_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	46,	2,	128},
+	{"cvmx_agl_gmx_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	48,	2,	130},
+	{"cvmx_agl_gmx_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	50,	2,	132},
+	{"cvmx_agl_gmx_rx#_stats_pkts" ,	CVMX_CSR_DB_TYPE_RSL,	64,	52,	2,	134},
+	{"cvmx_agl_gmx_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	54,	2,	136},
+	{"cvmx_agl_gmx_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	56,	2,	138},
+	{"cvmx_agl_gmx_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	58,	2,	140},
+	{"cvmx_agl_gmx_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	60,	2,	142},
+	{"cvmx_agl_gmx_rx#_udd_skp"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	62,	4,	144},
+	{"cvmx_agl_gmx_rx_bp_drop#"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	64,	2,	148},
+	{"cvmx_agl_gmx_rx_bp_off#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	66,	2,	150},
+	{"cvmx_agl_gmx_rx_bp_on#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	68,	2,	152},
+	{"cvmx_agl_gmx_rx_prt_info"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	70,	4,	154},
+	{"cvmx_agl_gmx_rx_tx_status"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	71,	4,	158},
+	{"cvmx_agl_gmx_smac#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	72,	2,	162},
+	{"cvmx_agl_gmx_stat_bp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	74,	3,	164},
+	{"cvmx_agl_gmx_tx#_append"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	75,	5,	167},
+	{"cvmx_agl_gmx_tx#_clk"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	77,	2,	172},
+	{"cvmx_agl_gmx_tx#_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	79,	3,	174},
+	{"cvmx_agl_gmx_tx#_min_pkt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	81,	2,	177},
+	{"cvmx_agl_gmx_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	83,	2,	179},
+	{"cvmx_agl_gmx_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	85,	2,	181},
+	{"cvmx_agl_gmx_tx#_pause_togo" ,	CVMX_CSR_DB_TYPE_RSL,	64,	87,	2,	183},
+	{"cvmx_agl_gmx_tx#_pause_zero" ,	CVMX_CSR_DB_TYPE_RSL,	64,	89,	2,	185},
+	{"cvmx_agl_gmx_tx#_soft_pause" ,	CVMX_CSR_DB_TYPE_RSL,	64,	91,	2,	187},
+	{"cvmx_agl_gmx_tx#_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	93,	2,	189},
+	{"cvmx_agl_gmx_tx#_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	95,	2,	191},
+	{"cvmx_agl_gmx_tx#_stat2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	97,	2,	193},
+	{"cvmx_agl_gmx_tx#_stat3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	99,	2,	195},
+	{"cvmx_agl_gmx_tx#_stat4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	101,	2,	197},
+	{"cvmx_agl_gmx_tx#_stat5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	103,	2,	199},
+	{"cvmx_agl_gmx_tx#_stat6"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	105,	2,	201},
+	{"cvmx_agl_gmx_tx#_stat7"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	107,	2,	203},
+	{"cvmx_agl_gmx_tx#_stat8"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	109,	2,	205},
+	{"cvmx_agl_gmx_tx#_stat9"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	111,	2,	207},
+	{"cvmx_agl_gmx_tx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	113,	2,	209},
+	{"cvmx_agl_gmx_tx#_thresh"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	115,	2,	211},
+	{"cvmx_agl_gmx_tx_bp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	117,	2,	213},
+	{"cvmx_agl_gmx_tx_col_attempt" ,	CVMX_CSR_DB_TYPE_RSL,	64,	118,	2,	215},
+	{"cvmx_agl_gmx_tx_ifg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	119,	3,	217},
+	{"cvmx_agl_gmx_tx_int_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	120,	12,	220},
+	{"cvmx_agl_gmx_tx_int_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	121,	12,	232},
+	{"cvmx_agl_gmx_tx_jam"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	122,	2,	244},
+	{"cvmx_agl_gmx_tx_lfsr"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	123,	2,	246},
+	{"cvmx_agl_gmx_tx_ovr_bp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	124,	6,	248},
+	{"cvmx_agl_gmx_tx_pause_pkt_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	125,	2,	254},
+	{"cvmx_agl_gmx_tx_pause_pkt_type",	CVMX_CSR_DB_TYPE_RSL,	64,	126,	2,	256},
+	{"cvmx_agl_prt#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	127,	23,	258},
+	{"cvmx_ciu_bist"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	129,	2,	281},
+	{"cvmx_ciu_block_int"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	130,	40,	283},
+	{"cvmx_ciu_dint"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	131,	2,	323},
+	{"cvmx_ciu_en2_io#_int"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	132,	3,	325},
+	{"cvmx_ciu_en2_io#_int_w1c"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	134,	3,	328},
+	{"cvmx_ciu_en2_io#_int_w1s"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	136,	3,	331},
+	{"cvmx_ciu_en2_pp#_ip2"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	138,	3,	334},
+	{"cvmx_ciu_en2_pp#_ip2_w1c"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	148,	3,	337},
+	{"cvmx_ciu_en2_pp#_ip2_w1s"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	158,	3,	340},
+	{"cvmx_ciu_en2_pp#_ip3"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	168,	3,	343},
+	{"cvmx_ciu_en2_pp#_ip3_w1c"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	178,	3,	346},
+	{"cvmx_ciu_en2_pp#_ip3_w1s"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	188,	3,	349},
+	{"cvmx_ciu_en2_pp#_ip4"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	198,	3,	352},
+	{"cvmx_ciu_en2_pp#_ip4_w1c"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	208,	3,	355},
+	{"cvmx_ciu_en2_pp#_ip4_w1s"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	218,	3,	358},
+	{"cvmx_ciu_fuse"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	228,	2,	361},
+	{"cvmx_ciu_gstop"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	229,	2,	363},
+	{"cvmx_ciu_int#_en0"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	230,	22,	365},
+	{"cvmx_ciu_int#_en0_w1c"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	252,	22,	387},
+	{"cvmx_ciu_int#_en0_w1s"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	274,	22,	409},
+	{"cvmx_ciu_int#_en1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	296,	37,	431},
+	{"cvmx_ciu_int#_en1_w1c"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	318,	37,	468},
+	{"cvmx_ciu_int#_en1_w1s"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	340,	37,	505},
+	{"cvmx_ciu_int#_en4_0"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	362,	22,	542},
+	{"cvmx_ciu_int#_en4_0_w1c"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	372,	22,	564},
+	{"cvmx_ciu_int#_en4_0_w1s"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	382,	22,	586},
+	{"cvmx_ciu_int#_en4_1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	392,	37,	608},
+	{"cvmx_ciu_int#_en4_1_w1c"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	402,	37,	645},
+	{"cvmx_ciu_int#_en4_1_w1s"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	412,	37,	682},
+	{"cvmx_ciu_int#_sum0"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	422,	22,	719},
+	{"cvmx_ciu_int#_sum4"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	443,	22,	741},
+	{"cvmx_ciu_int33_sum0"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	453,	22,	763},
+	{"cvmx_ciu_int_dbg_sel"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	454,	6,	785},
+	{"cvmx_ciu_int_sum1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	455,	37,	791},
+	{"cvmx_ciu_mbox_clr#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	456,	2,	828},
+	{"cvmx_ciu_mbox_set#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	466,	2,	830},
+	{"cvmx_ciu_nmi"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	476,	2,	832},
+	{"cvmx_ciu_pci_inta"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	477,	2,	834},
+	{"cvmx_ciu_pp_dbg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	478,	2,	836},
+	{"cvmx_ciu_pp_poke#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	479,	1,	838},
+	{"cvmx_ciu_pp_rst"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	489,	3,	839},
+	{"cvmx_ciu_qlm0"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	490,	13,	842},
+	{"cvmx_ciu_qlm1"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	491,	13,	855},
+	{"cvmx_ciu_qlm2"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	492,	8,	868},
+	{"cvmx_ciu_qlm_jtgc"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	493,	6,	876},
+	{"cvmx_ciu_qlm_jtgd"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	494,	8,	882},
+	{"cvmx_ciu_soft_bist"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	495,	2,	890},
+	{"cvmx_ciu_soft_prst"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	496,	2,	892},
+	{"cvmx_ciu_soft_prst1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	497,	2,	894},
+	{"cvmx_ciu_soft_prst2"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	498,	2,	896},
+	{"cvmx_ciu_soft_prst3"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	499,	2,	898},
+	{"cvmx_ciu_soft_rst"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	500,	2,	900},
+	{"cvmx_ciu_sum1_io#_int"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	501,	37,	902},
+	{"cvmx_ciu_sum1_pp#_ip2"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	503,	37,	939},
+	{"cvmx_ciu_sum1_pp#_ip3"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	513,	37,	976},
+	{"cvmx_ciu_sum1_pp#_ip4"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	523,	37,	1013},
+	{"cvmx_ciu_sum2_io#_int"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	533,	3,	1050},
+	{"cvmx_ciu_sum2_pp#_ip2"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	535,	3,	1053},
+	{"cvmx_ciu_sum2_pp#_ip3"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	545,	3,	1056},
+	{"cvmx_ciu_sum2_pp#_ip4"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	555,	3,	1059},
+	{"cvmx_ciu_tim#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	565,	3,	1062},
+	{"cvmx_ciu_tim_multi_cast"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	575,	2,	1065},
+	{"cvmx_ciu_wdog#"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	576,	7,	1067},
+	{"cvmx_dfa_bist0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	586,	12,	1074},
+	{"cvmx_dfa_bist1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	587,	12,	1086},
+	{"cvmx_dfa_config"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	588,	5,	1098},
+	{"cvmx_dfa_control"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	589,	7,	1103},
+	{"cvmx_dfa_dbell"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	590,	2,	1110},
+	{"cvmx_dfa_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	591,	1,	1112},
+	{"cvmx_dfa_debug1"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	592,	1,	1113},
+	{"cvmx_dfa_debug2"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	593,	1,	1114},
+	{"cvmx_dfa_debug3"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	594,	1,	1115},
+	{"cvmx_dfa_difctl"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	595,	4,	1116},
+	{"cvmx_dfa_difrdptr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	596,	3,	1120},
+	{"cvmx_dfa_dtcfadr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	597,	6,	1123},
+	{"cvmx_dfa_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	598,	5,	1129},
+	{"cvmx_dfa_intmsk"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	599,	3,	1134},
+	{"cvmx_dfa_memhidat"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	600,	1,	1137},
+	{"cvmx_dfa_pfc0_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	601,	1,	1138},
+	{"cvmx_dfa_pfc0_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	602,	5,	1139},
+	{"cvmx_dfa_pfc1_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	603,	1,	1144},
+	{"cvmx_dfa_pfc1_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	604,	5,	1145},
+	{"cvmx_dfa_pfc2_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	605,	1,	1150},
+	{"cvmx_dfa_pfc2_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	606,	5,	1151},
+	{"cvmx_dfa_pfc3_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	607,	1,	1156},
+	{"cvmx_dfa_pfc3_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	608,	5,	1157},
+	{"cvmx_dfa_pfc_gctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	609,	18,	1162},
+	{"cvmx_dfm_char_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	610,	7,	1180},
+	{"cvmx_dfm_char_mask0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	611,	2,	1187},
+	{"cvmx_dfm_char_mask2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	612,	2,	1189},
+	{"cvmx_dfm_char_mask4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	613,	12,	1191},
+	{"cvmx_dfm_comp_ctl2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	614,	11,	1203},
+	{"cvmx_dfm_config"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	615,	21,	1214},
+	{"cvmx_dfm_control"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	616,	20,	1235},
+	{"cvmx_dfm_dll_ctl2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	617,	6,	1255},
+	{"cvmx_dfm_dll_ctl3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	618,	11,	1261},
+	{"cvmx_dfm_fclk_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	619,	1,	1272},
+	{"cvmx_dfm_fnt_bist"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	620,	6,	1273},
+	{"cvmx_dfm_fnt_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	621,	5,	1279},
+	{"cvmx_dfm_fnt_iena"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	622,	3,	1284},
+	{"cvmx_dfm_fnt_sclk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	623,	4,	1287},
+	{"cvmx_dfm_fnt_stat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	624,	6,	1291},
+	{"cvmx_dfm_ifb_cnt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	625,	1,	1297},
+	{"cvmx_dfm_modereg_params0"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	626,	16,	1298},
+	{"cvmx_dfm_modereg_params1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	627,	25,	1314},
+	{"cvmx_dfm_ops_cnt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	628,	1,	1339},
+	{"cvmx_dfm_phy_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	629,	10,	1340},
+	{"cvmx_dfm_reset_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	630,	5,	1350},
+	{"cvmx_dfm_rlevel_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	631,	10,	1355},
+	{"cvmx_dfm_rlevel_dbg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	632,	1,	1365},
+	{"cvmx_dfm_rlevel_rank#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	633,	5,	1366},
+	{"cvmx_dfm_rodt_mask"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	635,	8,	1371},
+	{"cvmx_dfm_slot_ctl0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	636,	5,	1379},
+	{"cvmx_dfm_slot_ctl1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	637,	5,	1384},
+	{"cvmx_dfm_timing_params0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	638,	12,	1389},
+	{"cvmx_dfm_timing_params1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	639,	13,	1401},
+	{"cvmx_dfm_wlevel_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	640,	6,	1414},
+	{"cvmx_dfm_wlevel_dbg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	641,	3,	1420},
+	{"cvmx_dfm_wlevel_rank#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	642,	5,	1423},
+	{"cvmx_dfm_wodt_mask"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	644,	8,	1428},
+	{"cvmx_dpi_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	645,	2,	1436},
+	{"cvmx_dpi_ctl"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	646,	3,	1438},
+	{"cvmx_dpi_dma#_counts"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	647,	3,	1441},
+	{"cvmx_dpi_dma#_dbell"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	655,	2,	1444},
+	{"cvmx_dpi_dma#_err_rsp_status",	CVMX_CSR_DB_TYPE_NCB,	64,	663,	2,	1446},
+	{"cvmx_dpi_dma#_ibuff_saddr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	671,	7,	1448},
+	{"cvmx_dpi_dma#_iflight"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	679,	2,	1455},
+	{"cvmx_dpi_dma#_naddr"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	687,	2,	1457},
+	{"cvmx_dpi_dma#_reqbnk0"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	695,	1,	1459},
+	{"cvmx_dpi_dma#_reqbnk1"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	703,	1,	1460},
+	{"cvmx_dpi_dma_control"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	711,	19,	1461},
+	{"cvmx_dpi_dma_eng#_en"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	712,	2,	1480},
+	{"cvmx_dpi_eng#_buf"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	718,	5,	1482},
+	{"cvmx_dpi_info_reg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	724,	5,	1487},
+	{"cvmx_dpi_int_en"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	725,	17,	1492},
+	{"cvmx_dpi_int_reg"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	726,	17,	1509},
+	{"cvmx_dpi_ncb#_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	727,	2,	1526},
+	{"cvmx_dpi_pint_info"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	728,	4,	1528},
+	{"cvmx_dpi_pkt_err_rsp"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	729,	2,	1532},
+	{"cvmx_dpi_req_err_rsp"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	730,	2,	1534},
+	{"cvmx_dpi_req_err_rsp_en"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	731,	2,	1536},
+	{"cvmx_dpi_req_err_rst"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	732,	2,	1538},
+	{"cvmx_dpi_req_err_rst_en"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	733,	2,	1540},
+	{"cvmx_dpi_req_err_skip_comp"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	734,	4,	1542},
+	{"cvmx_dpi_req_gbl_en"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	735,	2,	1546},
+	{"cvmx_dpi_sli_prt#_cfg"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	736,	13,	1548},
+	{"cvmx_dpi_sli_prt#_err"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	740,	2,	1561},
+	{"cvmx_dpi_sli_prt#_err_info"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	744,	6,	1563},
+	{"cvmx_fpa_addr_range_error"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	748,	3,	1569},
+	{"cvmx_fpa_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	749,	6,	1572},
+	{"cvmx_fpa_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	750,	10,	1578},
+	{"cvmx_fpa_fpf#_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	751,	3,	1588},
+	{"cvmx_fpa_fpf#_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	758,	2,	1591},
+	{"cvmx_fpa_fpf0_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	765,	3,	1593},
+	{"cvmx_fpa_fpf0_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	766,	2,	1596},
+	{"cvmx_fpa_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	767,	47,	1598},
+	{"cvmx_fpa_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	768,	47,	1645},
+	{"cvmx_fpa_packet_threshold"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	769,	2,	1692},
+	{"cvmx_fpa_pool#_end_addr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	770,	2,	1694},
+	{"cvmx_fpa_pool#_start_addr"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	778,	2,	1696},
+	{"cvmx_fpa_pool#_threshold"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	786,	2,	1698},
+	{"cvmx_fpa_que#_available"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	794,	2,	1700},
+	{"cvmx_fpa_que#_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	802,	2,	1702},
+	{"cvmx_fpa_que_act"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	810,	3,	1704},
+	{"cvmx_fpa_que_exp"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	811,	3,	1707},
+	{"cvmx_fpa_wqe_threshold"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	812,	2,	1710},
+	{"cvmx_gmx#_bad_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	813,	7,	1712},
+	{"cvmx_gmx#_bist"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	815,	2,	1719},
+	{"cvmx_gmx#_clk_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	817,	2,	1721},
+	{"cvmx_gmx#_hg2_control"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	819,	5,	1723},
+	{"cvmx_gmx#_inf_mode"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	821,	9,	1728},
+	{"cvmx_gmx#_nxa_adr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	823,	2,	1737},
+	{"cvmx_gmx#_prt#_cbfc_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	825,	8,	1739},
+	{"cvmx_gmx#_prt#_cfg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	827,	10,	1747},
+	{"cvmx_gmx#_rx#_adr_cam0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	835,	1,	1757},
+	{"cvmx_gmx#_rx#_adr_cam1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	843,	1,	1758},
+	{"cvmx_gmx#_rx#_adr_cam2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	851,	1,	1759},
+	{"cvmx_gmx#_rx#_adr_cam3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	859,	1,	1760},
+	{"cvmx_gmx#_rx#_adr_cam4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	867,	1,	1761},
+	{"cvmx_gmx#_rx#_adr_cam5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	875,	1,	1762},
+	{"cvmx_gmx#_rx#_adr_cam_all_en",	CVMX_CSR_DB_TYPE_RSL,	64,	883,	2,	1763},
+	{"cvmx_gmx#_rx#_adr_cam_en"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	891,	2,	1765},
+	{"cvmx_gmx#_rx#_adr_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	899,	4,	1767},
+	{"cvmx_gmx#_rx#_decision"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	907,	2,	1771},
+	{"cvmx_gmx#_rx#_frm_chk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	915,	9,	1773},
+	{"cvmx_gmx#_rx#_frm_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	923,	13,	1782},
+	{"cvmx_gmx#_rx#_ifg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	931,	2,	1795},
+	{"cvmx_gmx#_rx#_int_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	939,	27,	1797},
+	{"cvmx_gmx#_rx#_int_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	947,	27,	1824},
+	{"cvmx_gmx#_rx#_jabber"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	955,	2,	1851},
+	{"cvmx_gmx#_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	963,	2,	1853},
+	{"cvmx_gmx#_rx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	971,	2,	1855},
+	{"cvmx_gmx#_rx#_stats_octs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	979,	2,	1857},
+	{"cvmx_gmx#_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	987,	2,	1859},
+	{"cvmx_gmx#_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	995,	2,	1861},
+	{"cvmx_gmx#_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	1003,	2,	1863},
+	{"cvmx_gmx#_rx#_stats_pkts"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1011,	2,	1865},
+	{"cvmx_gmx#_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	1019,	2,	1867},
+	{"cvmx_gmx#_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	1027,	2,	1869},
+	{"cvmx_gmx#_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	1035,	2,	1871},
+	{"cvmx_gmx#_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	1043,	2,	1873},
+	{"cvmx_gmx#_rx#_udd_skp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1051,	4,	1875},
+	{"cvmx_gmx#_rx_bp_drop#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1059,	2,	1879},
+	{"cvmx_gmx#_rx_bp_off#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1067,	2,	1881},
+	{"cvmx_gmx#_rx_bp_on#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1075,	2,	1883},
+	{"cvmx_gmx#_rx_hg2_status"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1083,	4,	1885},
+	{"cvmx_gmx#_rx_prt_info"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1085,	4,	1889},
+	{"cvmx_gmx#_rx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1087,	2,	1893},
+	{"cvmx_gmx#_rx_xaui_bad_col"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1089,	5,	1895},
+	{"cvmx_gmx#_rx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1091,	2,	1900},
+	{"cvmx_gmx#_smac#"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1093,	2,	1902},
+	{"cvmx_gmx#_soft_bist"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1101,	3,	1904},
+	{"cvmx_gmx#_stat_bp"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1103,	3,	1907},
+	{"cvmx_gmx#_tb_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1105,	2,	1910},
+	{"cvmx_gmx#_tx#_append"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1107,	5,	1912},
+	{"cvmx_gmx#_tx#_burst"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1115,	2,	1917},
+	{"cvmx_gmx#_tx#_cbfc_xoff"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1123,	2,	1919},
+	{"cvmx_gmx#_tx#_cbfc_xon"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1125,	2,	1921},
+	{"cvmx_gmx#_tx#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1127,	3,	1923},
+	{"cvmx_gmx#_tx#_min_pkt"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1135,	2,	1926},
+	{"cvmx_gmx#_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	1143,	2,	1928},
+	{"cvmx_gmx#_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	1151,	2,	1930},
+	{"cvmx_gmx#_tx#_pause_togo"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1159,	3,	1932},
+	{"cvmx_gmx#_tx#_pause_zero"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1167,	2,	1935},
+	{"cvmx_gmx#_tx#_sgmii_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1175,	2,	1937},
+	{"cvmx_gmx#_tx#_slot"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1183,	2,	1939},
+	{"cvmx_gmx#_tx#_soft_pause"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1191,	2,	1941},
+	{"cvmx_gmx#_tx#_stat0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1199,	2,	1943},
+	{"cvmx_gmx#_tx#_stat1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1207,	2,	1945},
+	{"cvmx_gmx#_tx#_stat2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1215,	2,	1947},
+	{"cvmx_gmx#_tx#_stat3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1223,	2,	1949},
+	{"cvmx_gmx#_tx#_stat4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1231,	2,	1951},
+	{"cvmx_gmx#_tx#_stat5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1239,	2,	1953},
+	{"cvmx_gmx#_tx#_stat6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1247,	2,	1955},
+	{"cvmx_gmx#_tx#_stat7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1255,	2,	1957},
+	{"cvmx_gmx#_tx#_stat8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1263,	2,	1959},
+	{"cvmx_gmx#_tx#_stat9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1271,	2,	1961},
+	{"cvmx_gmx#_tx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1279,	2,	1963},
+	{"cvmx_gmx#_tx#_thresh"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1287,	2,	1965},
+	{"cvmx_gmx#_tx_bp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1295,	2,	1967},
+	{"cvmx_gmx#_tx_col_attempt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1297,	2,	1969},
+	{"cvmx_gmx#_tx_corrupt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1299,	2,	1971},
+	{"cvmx_gmx#_tx_hg2_reg1"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1301,	2,	1973},
+	{"cvmx_gmx#_tx_hg2_reg2"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1303,	2,	1975},
+	{"cvmx_gmx#_tx_ifg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1305,	3,	1977},
+	{"cvmx_gmx#_tx_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1307,	10,	1980},
+	{"cvmx_gmx#_tx_int_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1309,	10,	1990},
+	{"cvmx_gmx#_tx_jam"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1311,	2,	2000},
+	{"cvmx_gmx#_tx_lfsr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1313,	2,	2002},
+	{"cvmx_gmx#_tx_ovr_bp"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1315,	6,	2004},
+	{"cvmx_gmx#_tx_pause_pkt_dmac" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1317,	2,	2010},
+	{"cvmx_gmx#_tx_pause_pkt_type" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1319,	2,	2012},
+	{"cvmx_gmx#_tx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1321,	2,	2014},
+	{"cvmx_gmx#_tx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1323,	9,	2016},
+	{"cvmx_gmx#_xaui_ext_loopback" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1325,	3,	2025},
+	{"cvmx_gpio_bit_cfg#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1327,	10,	2028},
+	{"cvmx_gpio_clk_gen#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1343,	2,	2038},
+	{"cvmx_gpio_clk_qlm#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1347,	5,	2040},
+	{"cvmx_gpio_int_clr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1349,	2,	2045},
+	{"cvmx_gpio_pin_ena"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1350,	4,	2047},
+	{"cvmx_gpio_rx_dat"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1351,	2,	2051},
+	{"cvmx_gpio_tx_clr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1352,	2,	2053},
+	{"cvmx_gpio_tx_set"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1353,	2,	2055},
+	{"cvmx_gpio_xbit_cfg#"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1354,	10,	2057},
+	{"cvmx_iob_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1358,	24,	2067},
+	{"cvmx_iob_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1359,	9,	2091},
+	{"cvmx_iob_dwb_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1360,	3,	2100},
+	{"cvmx_iob_fau_timeout"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1361,	3,	2103},
+	{"cvmx_iob_i2c_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1362,	3,	2106},
+	{"cvmx_iob_inb_control_match"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1363,	5,	2109},
+	{"cvmx_iob_inb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	1364,	5,	2114},
+	{"cvmx_iob_inb_data_match"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1365,	1,	2119},
+	{"cvmx_iob_inb_data_match_enb" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1366,	1,	2120},
+	{"cvmx_iob_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1367,	7,	2121},
+	{"cvmx_iob_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1368,	7,	2128},
+	{"cvmx_iob_n2c_l2c_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1369,	3,	2135},
+	{"cvmx_iob_n2c_rsp_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1370,	3,	2138},
+	{"cvmx_iob_outb_com_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1371,	3,	2141},
+	{"cvmx_iob_outb_control_match" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1372,	5,	2144},
+	{"cvmx_iob_outb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	1373,	5,	2149},
+	{"cvmx_iob_outb_data_match"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1374,	1,	2154},
+	{"cvmx_iob_outb_data_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	1375,	1,	2155},
+	{"cvmx_iob_outb_fpa_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1376,	3,	2156},
+	{"cvmx_iob_outb_req_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1377,	3,	2159},
+	{"cvmx_iob_p2c_req_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1378,	3,	2162},
+	{"cvmx_iob_pkt_err"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1379,	3,	2165},
+	{"cvmx_iob_to_cmb_credits"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1380,	4,	2168},
+	{"cvmx_ipd_1st_mbuff_skip"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1381,	2,	2172},
+	{"cvmx_ipd_1st_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1382,	2,	2174},
+	{"cvmx_ipd_2nd_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1383,	2,	2176},
+	{"cvmx_ipd_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1384,	19,	2178},
+	{"cvmx_ipd_bp_prt_red_end"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1385,	2,	2197},
+	{"cvmx_ipd_clk_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1386,	1,	2199},
+	{"cvmx_ipd_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1387,	18,	2200},
+	{"cvmx_ipd_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1388,	13,	2218},
+	{"cvmx_ipd_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1389,	13,	2231},
+	{"cvmx_ipd_not_1st_mbuff_skip" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1390,	2,	2244},
+	{"cvmx_ipd_packet_mbuff_size"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1391,	2,	2246},
+	{"cvmx_ipd_pkt_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1392,	2,	2248},
+	{"cvmx_ipd_port#_bp_page_cnt"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1393,	3,	2250},
+	{"cvmx_ipd_port#_bp_page_cnt2" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1405,	3,	2253},
+	{"cvmx_ipd_port#_bp_page_cnt3" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1409,	3,	2256},
+	{"cvmx_ipd_port_bp_counters2_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	1415,	2,	2259},
+	{"cvmx_ipd_port_bp_counters3_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	1419,	2,	2261},
+	{"cvmx_ipd_port_bp_counters4_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	1423,	2,	2263},
+	{"cvmx_ipd_port_bp_counters_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	1427,	2,	2265},
+	{"cvmx_ipd_port_qos_#_cnt"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1439,	2,	2267},
+	{"cvmx_ipd_port_qos_int#"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1615,	1,	2269},
+	{"cvmx_ipd_port_qos_int_enb#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1619,	1,	2270},
+	{"cvmx_ipd_prc_hold_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	1623,	6,	2271},
+	{"cvmx_ipd_prc_port_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	1624,	5,	2277},
+	{"cvmx_ipd_ptr_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1625,	6,	2282},
+	{"cvmx_ipd_pwp_ptr_fifo_ctl"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1626,	7,	2288},
+	{"cvmx_ipd_qos#_red_marks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1627,	2,	2295},
+	{"cvmx_ipd_que0_free_page_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1635,	2,	2297},
+	{"cvmx_ipd_red_port_enable"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1636,	3,	2299},
+	{"cvmx_ipd_red_port_enable2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1637,	2,	2302},
+	{"cvmx_ipd_red_que#_param"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1638,	5,	2304},
+	{"cvmx_ipd_sub_port_bp_page_cnt",	CVMX_CSR_DB_TYPE_NCB,	64,	1646,	3,	2309},
+	{"cvmx_ipd_sub_port_fcs"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1647,	4,	2312},
+	{"cvmx_ipd_sub_port_qos_cnt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1648,	3,	2316},
+	{"cvmx_ipd_wqe_fpa_queue"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1649,	2,	2319},
+	{"cvmx_ipd_wqe_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1650,	2,	2321},
+	{"cvmx_key_bist_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1651,	4,	2323},
+	{"cvmx_key_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1652,	3,	2327},
+	{"cvmx_key_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1653,	5,	2330},
+	{"cvmx_key_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1654,	5,	2335},
+	{"cvmx_l2c_big_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1655,	4,	2340},
+	{"cvmx_l2c_bst"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1656,	12,	2344},
+	{"cvmx_l2c_bst_mem#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1657,	5,	2356},
+	{"cvmx_l2c_bst_tdt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1658,	5,	2361},
+	{"cvmx_l2c_bst_ttg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1659,	3,	2366},
+	{"cvmx_l2c_cop0_map#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1660,	1,	2369},
+	{"cvmx_l2c_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	4476,	15,	2370},
+	{"cvmx_l2c_dut_map#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4477,	4,	2385},
+	{"cvmx_l2c_err_tdt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7037,	9,	2389},
+	{"cvmx_l2c_err_ttg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7038,	9,	2398},
+	{"cvmx_l2c_err_vbf#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7039,	6,	2407},
+	{"cvmx_l2c_err_xmc"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7040,	5,	2413},
+	{"cvmx_l2c_int_ena"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7041,	9,	2418},
+	{"cvmx_l2c_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7042,	11,	2427},
+	{"cvmx_l2c_ioc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7043,	1,	2438},
+	{"cvmx_l2c_ior#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7044,	1,	2439},
+	{"cvmx_l2c_qos_iob#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7045,	4,	2440},
+	{"cvmx_l2c_qos_pp#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7046,	2,	2444},
+	{"cvmx_l2c_qos_wgt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7056,	5,	2446},
+	{"cvmx_l2c_rsc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7057,	1,	2451},
+	{"cvmx_l2c_rsd#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7058,	1,	2452},
+	{"cvmx_l2c_tad#_ecc0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7059,	8,	2453},
+	{"cvmx_l2c_tad#_ecc1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7060,	8,	2461},
+	{"cvmx_l2c_tad#_ien"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7061,	10,	2469},
+	{"cvmx_l2c_tad#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7062,	10,	2479},
+	{"cvmx_l2c_tad#_pfc0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7063,	1,	2489},
+	{"cvmx_l2c_tad#_pfc1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7064,	1,	2490},
+	{"cvmx_l2c_tad#_pfc2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7065,	1,	2491},
+	{"cvmx_l2c_tad#_pfc3"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7066,	1,	2492},
+	{"cvmx_l2c_tad#_prf"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7067,	5,	2493},
+	{"cvmx_l2c_tad#_tag"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7068,	9,	2498},
+	{"cvmx_l2c_ver_id"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	7069,	1,	2507},
+	{"cvmx_l2c_ver_iob"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7070,	2,	2508},
+	{"cvmx_l2c_ver_msc"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7071,	3,	2510},
+	{"cvmx_l2c_ver_pp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	7072,	2,	2513},
+	{"cvmx_l2c_virtid_iob#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7073,	4,	2515},
+	{"cvmx_l2c_virtid_pp#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7074,	2,	2519},
+	{"cvmx_l2c_vrt_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7084,	6,	2521},
+	{"cvmx_l2c_vrt_mem#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7085,	3,	2527},
+	{"cvmx_l2c_wpar_iob#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8109,	2,	2530},
+	{"cvmx_l2c_wpar_pp#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8110,	2,	2532},
+	{"cvmx_l2c_xmc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8120,	1,	2534},
+	{"cvmx_l2c_xmc_cmd"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	8121,	4,	2535},
+	{"cvmx_l2c_xmd#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8122,	1,	2539},
+	{"cvmx_lmc#_char_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8123,	7,	2540},
+	{"cvmx_lmc#_char_mask0"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	8124,	1,	2547},
+	{"cvmx_lmc#_char_mask1"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	8125,	2,	2548},
+	{"cvmx_lmc#_char_mask2"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	8126,	1,	2550},
+	{"cvmx_lmc#_char_mask3"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	8127,	2,	2551},
+	{"cvmx_lmc#_char_mask4"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	8128,	12,	2553},
+	{"cvmx_lmc#_comp_ctl2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	8129,	11,	2565},
+	{"cvmx_lmc#_config"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	8130,	22,	2576},
+	{"cvmx_lmc#_control"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8131,	21,	2598},
+	{"cvmx_lmc#_dclk_cnt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8132,	1,	2619},
+	{"cvmx_lmc#_ddr_pll_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	8133,	11,	2620},
+	{"cvmx_lmc#_dimm#_params"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	8134,	16,	2631},
+	{"cvmx_lmc#_dimm_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8136,	5,	2647},
+	{"cvmx_lmc#_dll_ctl2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8137,	6,	2652},
+	{"cvmx_lmc#_dll_ctl3"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8138,	11,	2658},
+	{"cvmx_lmc#_dual_memcfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	8139,	4,	2669},
+	{"cvmx_lmc#_ecc_synd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8140,	5,	2673},
+	{"cvmx_lmc#_fadr"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	8141,	6,	2678},
+	{"cvmx_lmc#_ifb_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8142,	1,	2684},
+	{"cvmx_lmc#_int"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	8143,	4,	2685},
+	{"cvmx_lmc#_int_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	8144,	4,	2689},
+	{"cvmx_lmc#_modereg_params0"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8145,	16,	2693},
+	{"cvmx_lmc#_modereg_params1"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8146,	25,	2709},
+	{"cvmx_lmc#_nxm"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	8147,	10,	2734},
+	{"cvmx_lmc#_ops_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8148,	1,	2744},
+	{"cvmx_lmc#_phy_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8149,	10,	2745},
+	{"cvmx_lmc#_reset_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	8150,	5,	2755},
+	{"cvmx_lmc#_rlevel_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	8151,	10,	2760},
+	{"cvmx_lmc#_rlevel_dbg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	8152,	1,	2770},
+	{"cvmx_lmc#_rlevel_rank#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	8153,	11,	2771},
+	{"cvmx_lmc#_rodt_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	8157,	8,	2782},
+	{"cvmx_lmc#_scramble_cfg0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	8158,	1,	2790},
+	{"cvmx_lmc#_scramble_cfg1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	8159,	1,	2791},
+	{"cvmx_lmc#_scrambled_fadr"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	8160,	6,	2792},
+	{"cvmx_lmc#_slot_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	8161,	5,	2798},
+	{"cvmx_lmc#_slot_ctl1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	8162,	5,	2803},
+	{"cvmx_lmc#_slot_ctl2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	8163,	5,	2808},
+	{"cvmx_lmc#_timing_params0"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	8164,	12,	2813},
+	{"cvmx_lmc#_timing_params1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	8165,	13,	2825},
+	{"cvmx_lmc#_tro_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8166,	3,	2838},
+	{"cvmx_lmc#_tro_stat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8167,	2,	2841},
+	{"cvmx_lmc#_wlevel_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	8168,	6,	2843},
+	{"cvmx_lmc#_wlevel_dbg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	8169,	3,	2849},
+	{"cvmx_lmc#_wlevel_rank#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	8170,	11,	2852},
+	{"cvmx_lmc#_wodt_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	8174,	8,	2863},
+	{"cvmx_mio_boot_bist_stat"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	8175,	2,	2871},
+	{"cvmx_mio_boot_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8176,	3,	2873},
+	{"cvmx_mio_boot_dma_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	8177,	10,	2876},
+	{"cvmx_mio_boot_dma_int#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	8179,	3,	2886},
+	{"cvmx_mio_boot_dma_int_en#"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8181,	3,	2889},
+	{"cvmx_mio_boot_dma_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	8183,	15,	2892},
+	{"cvmx_mio_boot_err"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8185,	3,	2907},
+	{"cvmx_mio_boot_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8186,	3,	2910},
+	{"cvmx_mio_boot_loc_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	8187,	3,	2913},
+	{"cvmx_mio_boot_loc_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	8188,	5,	2916},
+	{"cvmx_mio_boot_loc_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	8190,	1,	2921},
+	{"cvmx_mio_boot_pin_defs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	8191,	9,	2922},
+	{"cvmx_mio_boot_reg_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	8192,	13,	2931},
+	{"cvmx_mio_boot_reg_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	8200,	13,	2944},
+	{"cvmx_mio_boot_thr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8208,	6,	2957},
+	{"cvmx_mio_fus_bnk_dat#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	8209,	1,	2963},
+	{"cvmx_mio_fus_dat0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8211,	2,	2964},
+	{"cvmx_mio_fus_dat1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8212,	2,	2966},
+	{"cvmx_mio_fus_dat2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8213,	15,	2968},
+	{"cvmx_mio_fus_dat3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8214,	18,	2983},
+	{"cvmx_mio_fus_ema"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	8215,	4,	3001},
+	{"cvmx_mio_fus_pdf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	8216,	1,	3005},
+	{"cvmx_mio_fus_pll"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	8217,	7,	3006},
+	{"cvmx_mio_fus_prog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8218,	3,	3013},
+	{"cvmx_mio_fus_prog_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	8219,	8,	3016},
+	{"cvmx_mio_fus_rcmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8220,	7,	3024},
+	{"cvmx_mio_fus_read_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	8221,	6,	3031},
+	{"cvmx_mio_fus_repair_res0"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	8222,	5,	3037},
+	{"cvmx_mio_fus_repair_res1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	8223,	4,	3042},
+	{"cvmx_mio_fus_repair_res2"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	8224,	2,	3046},
+	{"cvmx_mio_fus_spr_repair_res" ,	CVMX_CSR_DB_TYPE_RSL,	64,	8225,	4,	3048},
+	{"cvmx_mio_fus_spr_repair_sum" ,	CVMX_CSR_DB_TYPE_RSL,	64,	8226,	2,	3052},
+	{"cvmx_mio_fus_tgg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	8227,	2,	3054},
+	{"cvmx_mio_fus_wadr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8228,	2,	3056},
+	{"cvmx_mio_gpio_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8229,	3,	3058},
+	{"cvmx_mio_ndf_dma_cfg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	8230,	10,	3061},
+	{"cvmx_mio_ndf_dma_int"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	8231,	2,	3071},
+	{"cvmx_mio_ndf_dma_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	8232,	2,	3073},
+	{"cvmx_mio_ptp_ckout_hi_incr"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	8233,	2,	3075},
+	{"cvmx_mio_ptp_ckout_lo_incr"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	8234,	2,	3077},
+	{"cvmx_mio_ptp_ckout_thresh_hi",	CVMX_CSR_DB_TYPE_NCB,	64,	8235,	1,	3079},
+	{"cvmx_mio_ptp_ckout_thresh_lo",	CVMX_CSR_DB_TYPE_NCB,	64,	8236,	2,	3080},
+	{"cvmx_mio_ptp_clock_cfg"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	8237,	18,	3082},
+	{"cvmx_mio_ptp_clock_comp"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	8238,	2,	3100},
+	{"cvmx_mio_ptp_clock_hi"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	8239,	1,	3102},
+	{"cvmx_mio_ptp_clock_lo"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	8240,	2,	3103},
+	{"cvmx_mio_ptp_evt_cnt"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	8241,	1,	3105},
+	{"cvmx_mio_ptp_pps_hi_incr"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	8242,	2,	3106},
+	{"cvmx_mio_ptp_pps_lo_incr"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	8243,	2,	3108},
+	{"cvmx_mio_ptp_pps_thresh_hi"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	8244,	1,	3110},
+	{"cvmx_mio_ptp_pps_thresh_lo"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	8245,	2,	3111},
+	{"cvmx_mio_ptp_timestamp"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	8246,	1,	3113},
+	{"cvmx_mio_qlm#_cfg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8247,	4,	3114},
+	{"cvmx_mio_rst_boot"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8250,	16,	3118},
+	{"cvmx_mio_rst_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	8251,	5,	3134},
+	{"cvmx_mio_rst_ckill"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8252,	2,	3139},
+	{"cvmx_mio_rst_cntl#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8253,	10,	3141},
+	{"cvmx_mio_rst_ctl#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8257,	10,	3151},
+	{"cvmx_mio_rst_delay"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8259,	3,	3161},
+	{"cvmx_mio_rst_int"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	8260,	8,	3164},
+	{"cvmx_mio_rst_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	8261,	8,	3172},
+	{"cvmx_mio_tws#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8262,	13,	3180},
+	{"cvmx_mio_tws#_sw_twsi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	8264,	12,	3193},
+	{"cvmx_mio_tws#_sw_twsi_ext"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8266,	3,	3205},
+	{"cvmx_mio_tws#_twsi_sw"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	8268,	3,	3208},
+	{"cvmx_mio_uart#_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8270,	2,	3211},
+	{"cvmx_mio_uart#_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8272,	2,	3213},
+	{"cvmx_mio_uart#_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8274,	2,	3215},
+	{"cvmx_mio_uart#_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8276,	7,	3217},
+	{"cvmx_mio_uart#_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8278,	2,	3224},
+	{"cvmx_mio_uart#_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8280,	7,	3226},
+	{"cvmx_mio_uart#_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8282,	4,	3233},
+	{"cvmx_mio_uart#_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8284,	8,	3237},
+	{"cvmx_mio_uart#_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8286,	9,	3245},
+	{"cvmx_mio_uart#_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8288,	7,	3254},
+	{"cvmx_mio_uart#_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8290,	9,	3261},
+	{"cvmx_mio_uart#_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8292,	2,	3270},
+	{"cvmx_mio_uart#_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8294,	2,	3272},
+	{"cvmx_mio_uart#_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8296,	4,	3274},
+	{"cvmx_mio_uart#_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	8298,	2,	3278},
+	{"cvmx_mio_uart#_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8300,	2,	3280},
+	{"cvmx_mio_uart#_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8302,	2,	3282},
+	{"cvmx_mio_uart#_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8304,	4,	3284},
+	{"cvmx_mio_uart#_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8306,	2,	3288},
+	{"cvmx_mio_uart#_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	8308,	2,	3290},
+	{"cvmx_mio_uart#_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8310,	2,	3292},
+	{"cvmx_mio_uart#_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8312,	2,	3294},
+	{"cvmx_mio_uart#_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8314,	2,	3296},
+	{"cvmx_mio_uart#_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8316,	2,	3298},
+	{"cvmx_mio_uart#_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8318,	6,	3300},
+	{"cvmx_mix#_bist"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	8320,	7,	3306},
+	{"cvmx_mix#_ctl"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	8322,	9,	3313},
+	{"cvmx_mix#_intena"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	8324,	9,	3322},
+	{"cvmx_mix#_ircnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	8326,	2,	3331},
+	{"cvmx_mix#_irhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	8328,	3,	3333},
+	{"cvmx_mix#_iring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	8330,	4,	3336},
+	{"cvmx_mix#_iring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	8332,	4,	3340},
+	{"cvmx_mix#_isr"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	8334,	9,	3344},
+	{"cvmx_mix#_orcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	8336,	2,	3353},
+	{"cvmx_mix#_orhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	8338,	2,	3355},
+	{"cvmx_mix#_oring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	8340,	4,	3357},
+	{"cvmx_mix#_oring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	8342,	4,	3361},
+	{"cvmx_mix#_remcnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	8344,	4,	3365},
+	{"cvmx_mix#_tsctl"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	8346,	6,	3369},
+	{"cvmx_mix#_tstamp"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	8348,	1,	3375},
+	{"cvmx_mpi_cfg"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	8350,	16,	3376},
+	{"cvmx_mpi_dat#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	8351,	2,	3392},
+	{"cvmx_mpi_sts"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	8360,	4,	3394},
+	{"cvmx_mpi_tx"                 ,	CVMX_CSR_DB_TYPE_NCB,	64,	8361,	8,	3398},
+	{"cvmx_ndf_bt_pg_info"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	8362,	4,	3406},
+	{"cvmx_ndf_cmd"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	8363,	1,	3410},
+	{"cvmx_ndf_drbell"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	8364,	2,	3411},
+	{"cvmx_ndf_ecc_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	8365,	3,	3413},
+	{"cvmx_ndf_int"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	8366,	8,	3416},
+	{"cvmx_ndf_int_en"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	8367,	8,	3424},
+	{"cvmx_ndf_misc"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	8368,	12,	3432},
+	{"cvmx_ndf_st_reg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	8369,	8,	3444},
+	{"cvmx_pcieep#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8370,	2,	3452},
+	{"cvmx_pcieep#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8372,	24,	3454},
+	{"cvmx_pcieep#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8374,	4,	3478},
+	{"cvmx_pcieep#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8376,	5,	3482},
+	{"cvmx_pcieep#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8378,	5,	3487},
+	{"cvmx_pcieep#_cfg004_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8380,	2,	3492},
+	{"cvmx_pcieep#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8382,	1,	3494},
+	{"cvmx_pcieep#_cfg005_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8384,	1,	3495},
+	{"cvmx_pcieep#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8386,	5,	3496},
+	{"cvmx_pcieep#_cfg006_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8388,	2,	3501},
+	{"cvmx_pcieep#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8390,	1,	3503},
+	{"cvmx_pcieep#_cfg007_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8392,	1,	3504},
+	{"cvmx_pcieep#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8394,	4,	3505},
+	{"cvmx_pcieep#_cfg008_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8396,	2,	3509},
+	{"cvmx_pcieep#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8398,	2,	3511},
+	{"cvmx_pcieep#_cfg009_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8400,	1,	3513},
+	{"cvmx_pcieep#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8402,	1,	3514},
+	{"cvmx_pcieep#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8404,	2,	3515},
+	{"cvmx_pcieep#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8406,	3,	3517},
+	{"cvmx_pcieep#_cfg012_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8408,	2,	3520},
+	{"cvmx_pcieep#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8410,	2,	3522},
+	{"cvmx_pcieep#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8412,	4,	3524},
+	{"cvmx_pcieep#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8414,	10,	3528},
+	{"cvmx_pcieep#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8416,	12,	3538},
+	{"cvmx_pcieep#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8418,	8,	3550},
+	{"cvmx_pcieep#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8420,	2,	3558},
+	{"cvmx_pcieep#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8422,	1,	3560},
+	{"cvmx_pcieep#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8424,	2,	3561},
+	{"cvmx_pcieep#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8426,	7,	3563},
+	{"cvmx_pcieep#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8428,	12,	3570},
+	{"cvmx_pcieep#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8430,	19,	3582},
+	{"cvmx_pcieep#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8432,	12,	3601},
+	{"cvmx_pcieep#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8434,	20,	3613},
+	{"cvmx_pcieep#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8436,	11,	3633},
+	{"cvmx_pcieep#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8438,	8,	3644},
+	{"cvmx_pcieep#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8440,	4,	3652},
+	{"cvmx_pcieep#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8442,	11,	3656},
+	{"cvmx_pcieep#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8444,	3,	3667},
+	{"cvmx_pcieep#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8446,	16,	3670},
+	{"cvmx_pcieep#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8448,	16,	3686},
+	{"cvmx_pcieep#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8450,	16,	3702},
+	{"cvmx_pcieep#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8452,	9,	3718},
+	{"cvmx_pcieep#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8454,	9,	3727},
+	{"cvmx_pcieep#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8456,	6,	3736},
+	{"cvmx_pcieep#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8458,	1,	3742},
+	{"cvmx_pcieep#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8460,	1,	3743},
+	{"cvmx_pcieep#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8462,	1,	3744},
+	{"cvmx_pcieep#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8464,	1,	3745},
+	{"cvmx_pcieep#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8466,	2,	3746},
+	{"cvmx_pcieep#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8468,	1,	3748},
+	{"cvmx_pcieep#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8470,	6,	3749},
+	{"cvmx_pcieep#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8472,	7,	3755},
+	{"cvmx_pcieep#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8474,	11,	3762},
+	{"cvmx_pcieep#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8476,	5,	3773},
+	{"cvmx_pcieep#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8478,	6,	3778},
+	{"cvmx_pcieep#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8480,	19,	3784},
+	{"cvmx_pcieep#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8482,	5,	3803},
+	{"cvmx_pcieep#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8484,	1,	3808},
+	{"cvmx_pcieep#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8486,	1,	3809},
+	{"cvmx_pcieep#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8488,	3,	3810},
+	{"cvmx_pcieep#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8490,	3,	3813},
+	{"cvmx_pcieep#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8492,	3,	3816},
+	{"cvmx_pcieep#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8494,	4,	3819},
+	{"cvmx_pcieep#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8496,	4,	3823},
+	{"cvmx_pcieep#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8498,	4,	3827},
+	{"cvmx_pcieep#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8500,	7,	3831},
+	{"cvmx_pcieep#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8502,	5,	3838},
+	{"cvmx_pcieep#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8504,	5,	3843},
+	{"cvmx_pcieep#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8506,	4,	3848},
+	{"cvmx_pcieep#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8508,	4,	3852},
+	{"cvmx_pcieep#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8510,	4,	3856},
+	{"cvmx_pcieep#_cfg515"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8512,	7,	3860},
+	{"cvmx_pcieep#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8514,	1,	3867},
+	{"cvmx_pcieep#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	8516,	1,	3868},
+	{"cvmx_pcierc#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8518,	2,	3869},
+	{"cvmx_pcierc#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8520,	24,	3871},
+	{"cvmx_pcierc#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8522,	4,	3895},
+	{"cvmx_pcierc#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8524,	5,	3899},
+	{"cvmx_pcierc#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8526,	1,	3904},
+	{"cvmx_pcierc#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8528,	1,	3905},
+	{"cvmx_pcierc#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8530,	4,	3906},
+	{"cvmx_pcierc#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8532,	17,	3910},
+	{"cvmx_pcierc#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8534,	4,	3927},
+	{"cvmx_pcierc#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8536,	6,	3931},
+	{"cvmx_pcierc#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8538,	1,	3937},
+	{"cvmx_pcierc#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8540,	1,	3938},
+	{"cvmx_pcierc#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8542,	2,	3939},
+	{"cvmx_pcierc#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8544,	2,	3941},
+	{"cvmx_pcierc#_cfg014"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8546,	1,	3943},
+	{"cvmx_pcierc#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8548,	15,	3944},
+	{"cvmx_pcierc#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8550,	10,	3959},
+	{"cvmx_pcierc#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8552,	12,	3969},
+	{"cvmx_pcierc#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8554,	7,	3981},
+	{"cvmx_pcierc#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8556,	2,	3988},
+	{"cvmx_pcierc#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8558,	1,	3990},
+	{"cvmx_pcierc#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8560,	2,	3991},
+	{"cvmx_pcierc#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8562,	7,	3993},
+	{"cvmx_pcierc#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8564,	11,	4000},
+	{"cvmx_pcierc#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8566,	19,	4011},
+	{"cvmx_pcierc#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8568,	12,	4030},
+	{"cvmx_pcierc#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8570,	20,	4042},
+	{"cvmx_pcierc#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8572,	12,	4062},
+	{"cvmx_pcierc#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8574,	22,	4074},
+	{"cvmx_pcierc#_cfg035"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8576,	8,	4096},
+	{"cvmx_pcierc#_cfg036"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8578,	4,	4104},
+	{"cvmx_pcierc#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8580,	11,	4108},
+	{"cvmx_pcierc#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8582,	8,	4119},
+	{"cvmx_pcierc#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8584,	4,	4127},
+	{"cvmx_pcierc#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8586,	11,	4131},
+	{"cvmx_pcierc#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8588,	1,	4142},
+	{"cvmx_pcierc#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8590,	1,	4143},
+	{"cvmx_pcierc#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8592,	3,	4144},
+	{"cvmx_pcierc#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8594,	16,	4147},
+	{"cvmx_pcierc#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8596,	16,	4163},
+	{"cvmx_pcierc#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8598,	16,	4179},
+	{"cvmx_pcierc#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8600,	9,	4195},
+	{"cvmx_pcierc#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8602,	9,	4204},
+	{"cvmx_pcierc#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8604,	6,	4213},
+	{"cvmx_pcierc#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8606,	1,	4219},
+	{"cvmx_pcierc#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8608,	1,	4220},
+	{"cvmx_pcierc#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8610,	1,	4221},
+	{"cvmx_pcierc#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8612,	1,	4222},
+	{"cvmx_pcierc#_cfg075"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8614,	4,	4223},
+	{"cvmx_pcierc#_cfg076"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8616,	9,	4227},
+	{"cvmx_pcierc#_cfg077"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8618,	2,	4236},
+	{"cvmx_pcierc#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8620,	2,	4238},
+	{"cvmx_pcierc#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8622,	1,	4240},
+	{"cvmx_pcierc#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8624,	6,	4241},
+	{"cvmx_pcierc#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8626,	7,	4247},
+	{"cvmx_pcierc#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8628,	11,	4254},
+	{"cvmx_pcierc#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8630,	5,	4265},
+	{"cvmx_pcierc#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8632,	6,	4270},
+	{"cvmx_pcierc#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8634,	19,	4276},
+	{"cvmx_pcierc#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8636,	5,	4295},
+	{"cvmx_pcierc#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8638,	1,	4300},
+	{"cvmx_pcierc#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8640,	1,	4301},
+	{"cvmx_pcierc#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8642,	3,	4302},
+	{"cvmx_pcierc#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8644,	3,	4305},
+	{"cvmx_pcierc#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8646,	3,	4308},
+	{"cvmx_pcierc#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8648,	4,	4311},
+	{"cvmx_pcierc#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8650,	4,	4315},
+	{"cvmx_pcierc#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8652,	4,	4319},
+	{"cvmx_pcierc#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8654,	7,	4323},
+	{"cvmx_pcierc#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8656,	5,	4330},
+	{"cvmx_pcierc#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8658,	5,	4335},
+	{"cvmx_pcierc#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8660,	4,	4340},
+	{"cvmx_pcierc#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8662,	4,	4344},
+	{"cvmx_pcierc#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8664,	4,	4348},
+	{"cvmx_pcierc#_cfg515"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8666,	7,	4352},
+	{"cvmx_pcierc#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8668,	1,	4359},
+	{"cvmx_pcierc#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	8670,	1,	4360},
+	{"cvmx_pcs#_an#_adv_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	8672,	9,	4361},
+	{"cvmx_pcs#_an#_ext_st_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	8680,	6,	4370},
+	{"cvmx_pcs#_an#_lp_abil_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8688,	9,	4376},
+	{"cvmx_pcs#_an#_results_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8696,	6,	4385},
+	{"cvmx_pcs#_int#_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	8704,	14,	4391},
+	{"cvmx_pcs#_int#_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8712,	14,	4405},
+	{"cvmx_pcs#_link#_timer_count_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	8720,	2,	4419},
+	{"cvmx_pcs#_log_anl#_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	8728,	4,	4421},
+	{"cvmx_pcs#_misc#_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	8736,	8,	4425},
+	{"cvmx_pcs#_mr#_control_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8744,	13,	4433},
+	{"cvmx_pcs#_mr#_status_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	8752,	17,	4446},
+	{"cvmx_pcs#_rx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	8760,	7,	4463},
+	{"cvmx_pcs#_rx#_sync_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	8768,	3,	4470},
+	{"cvmx_pcs#_sgm#_an_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8776,	8,	4473},
+	{"cvmx_pcs#_sgm#_lp_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8784,	7,	4481},
+	{"cvmx_pcs#_tx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	8792,	4,	4488},
+	{"cvmx_pcs#_tx_rx#_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	8800,	5,	4492},
+	{"cvmx_pcsx#_10gbx_status_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	8808,	8,	4497},
+	{"cvmx_pcsx#_bist_status_reg"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	8810,	2,	4505},
+	{"cvmx_pcsx#_bit_lock_status_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	8812,	5,	4507},
+	{"cvmx_pcsx#_control1_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	8814,	10,	4512},
+	{"cvmx_pcsx#_control2_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	8816,	2,	4522},
+	{"cvmx_pcsx#_int_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	8818,	8,	4524},
+	{"cvmx_pcsx#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8820,	8,	4532},
+	{"cvmx_pcsx#_log_anl_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	8822,	6,	4540},
+	{"cvmx_pcsx#_misc_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	8824,	5,	4546},
+	{"cvmx_pcsx#_rx_sync_states_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	8826,	5,	4551},
+	{"cvmx_pcsx#_spd_abil_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	8828,	3,	4556},
+	{"cvmx_pcsx#_status1_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	8830,	6,	4559},
+	{"cvmx_pcsx#_status2_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	8832,	9,	4565},
+	{"cvmx_pcsx#_tx_rx_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	8834,	5,	4574},
+	{"cvmx_pcsx#_tx_rx_states_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	8836,	10,	4579},
+	{"cvmx_pem#_bar1_index#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	8838,	5,	4589},
+	{"cvmx_pem#_bar2_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	8870,	3,	4594},
+	{"cvmx_pem#_bar_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8872,	5,	4597},
+	{"cvmx_pem#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	8874,	9,	4602},
+	{"cvmx_pem#_bist_status2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	8876,	11,	4611},
+	{"cvmx_pem#_cfg_rd"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	8878,	2,	4622},
+	{"cvmx_pem#_cfg_wr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	8880,	2,	4624},
+	{"cvmx_pem#_cpl_lut_valid"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	8882,	2,	4626},
+	{"cvmx_pem#_ctl_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	8884,	18,	4628},
+	{"cvmx_pem#_dbg_info"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8886,	32,	4646},
+	{"cvmx_pem#_dbg_info_en"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	8888,	32,	4678},
+	{"cvmx_pem#_diag_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	8890,	5,	4710},
+	{"cvmx_pem#_inb_read_credits"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	8892,	2,	4715},
+	{"cvmx_pem#_int_enb"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8894,	15,	4717},
+	{"cvmx_pem#_int_enb_int"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	8896,	15,	4732},
+	{"cvmx_pem#_int_sum"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8898,	15,	4747},
+	{"cvmx_pem#_p2n_bar0_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	8900,	2,	4762},
+	{"cvmx_pem#_p2n_bar1_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	8902,	2,	4764},
+	{"cvmx_pem#_p2n_bar2_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	8904,	2,	4766},
+	{"cvmx_pem#_p2p_bar#_end"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	8906,	2,	4768},
+	{"cvmx_pem#_p2p_bar#_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	8914,	2,	4770},
+	{"cvmx_pem#_tlp_credits"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	8922,	8,	4772},
+	{"cvmx_pip_alt_skip_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	8924,	12,	4780},
+	{"cvmx_pip_bck_prs"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	8928,	5,	4792},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	8929,	2,	4797},
+	{"cvmx_pip_clken"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	8930,	2,	4799},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	8931,	4,	4801},
+	{"cvmx_pip_dsa_src_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	8935,	16,	4805},
+	{"cvmx_pip_dsa_vid_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	8936,	16,	4821},
+	{"cvmx_pip_frm_len_chk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	8937,	3,	4837},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	8938,	8,	4840},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	8939,	23,	4848},
+	{"cvmx_pip_hg_pri_qos"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	8940,	6,	4871},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	8941,	14,	4877},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	8942,	14,	4891},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8943,	2,	4905},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8944,	28,	4907},
+	{"cvmx_pip_prt_cfgb#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	8966,	4,	4935},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	8990,	25,	4939},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	9012,	2,	4964},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	9076,	4,	4966},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9084,	9,	4970},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	9092,	2,	4979},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	9093,	2,	4981},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9094,	2,	4983},
+	{"cvmx_pip_stat10_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9110,	2,	4985},
+	{"cvmx_pip_stat11_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9126,	2,	4987},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9142,	2,	4989},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9158,	2,	4991},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9174,	2,	4993},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9190,	2,	4995},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9206,	2,	4997},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9222,	2,	4999},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9238,	2,	5001},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9254,	2,	5003},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9270,	2,	5005},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	9286,	2,	5007},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	9287,	2,	5009},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	9309,	2,	5011},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	9331,	2,	5013},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	9353,	2,	5015},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	9417,	2,	5017},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9418,	3,	5019},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9419,	3,	5022},
+	{"cvmx_pip_vlan_etypes#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	9420,	4,	5025},
+	{"cvmx_pip_xstat0_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9422,	2,	5029},
+	{"cvmx_pip_xstat10_prt#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	9428,	2,	5031},
+	{"cvmx_pip_xstat11_prt#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	9434,	2,	5033},
+	{"cvmx_pip_xstat1_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9440,	2,	5035},
+	{"cvmx_pip_xstat2_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9446,	2,	5037},
+	{"cvmx_pip_xstat3_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9452,	2,	5039},
+	{"cvmx_pip_xstat4_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9458,	2,	5041},
+	{"cvmx_pip_xstat5_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9464,	2,	5043},
+	{"cvmx_pip_xstat6_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9470,	2,	5045},
+	{"cvmx_pip_xstat7_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9476,	2,	5047},
+	{"cvmx_pip_xstat8_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9482,	2,	5049},
+	{"cvmx_pip_xstat9_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9488,	2,	5051},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9494,	2,	5053},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9495,	2,	5055},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9496,	4,	5057},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9497,	5,	5061},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9498,	4,	5066},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9499,	8,	5070},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9500,	4,	5078},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9501,	5,	5082},
+	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9502,	1,	5087},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9503,	5,	5088},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9504,	1,	5093},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9505,	13,	5094},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9506,	6,	5107},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9507,	13,	5113},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9508,	6,	5126},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9509,	12,	5132},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9510,	4,	5144},
+	{"cvmx_pko_mem_port_ptrs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	9511,	7,	5148},
+	{"cvmx_pko_mem_port_qos"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	9512,	5,	5155},
+	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	9513,	5,	5160},
+	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	9514,	4,	5165},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	9515,	9,	5169},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	9516,	5,	5178},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	9517,	16,	5183},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9518,	4,	5199},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9519,	1,	5203},
+	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9520,	1,	5204},
+	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9521,	1,	5205},
+	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9522,	1,	5206},
+	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	9523,	15,	5207},
+	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	9524,	2,	5222},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	9525,	4,	5224},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	9526,	8,	5228},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	9527,	3,	5236},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	9528,	4,	5239},
+	{"cvmx_pko_reg_preempt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9529,	2,	5243},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	9530,	2,	5245},
+	{"cvmx_pko_reg_queue_preempt"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	9531,	3,	5247},
+	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	9532,	3,	5250},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	9533,	3,	5253},
+	{"cvmx_pko_reg_timestamp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	9534,	2,	5256},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	9535,	10,	5258},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	9536,	2,	5268},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	9537,	13,	5270},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	9538,	3,	5283},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	9539,	2,	5286},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	9547,	2,	5288},
+	{"cvmx_pow_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	9548,	2,	5290},
+	{"cvmx_pow_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	9549,	2,	5292},
+	{"cvmx_pow_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	9550,	2,	5294},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	9558,	2,	5296},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	9559,	2,	5298},
+	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	9560,	2,	5300},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	9561,	10,	5302},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	9571,	5,	5312},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	9579,	10,	5317},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	9587,	2,	5327},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	9588,	2,	5329},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	9589,	2,	5331},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	9597,	3,	5333},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	9598,	6,	5336},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	9614,	5,	5342},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	9615,	7,	5347},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	9631,	2,	5354},
+	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9647,	1,	5356},
+	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9648,	1,	5357},
+	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9649,	1,	5358},
+	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	9650,	5,	5359},
+	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9651,	5,	5364},
+	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	9652,	4,	5369},
+	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9653,	10,	5373},
+	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9654,	1,	5383},
+	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9655,	3,	5384},
+	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9656,	7,	5387},
+	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9657,	2,	5394},
+	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9658,	1,	5396},
+	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9659,	1,	5397},
+	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9660,	1,	5398},
+	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9661,	18,	5399},
+	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9662,	3,	5417},
+	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9663,	2,	5420},
+	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9664,	3,	5422},
+	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9665,	7,	5425},
+	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	9666,	2,	5432},
+	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	9667,	2,	5434},
+	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	9668,	2,	5436},
+	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	9669,	3,	5438},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	9670,	3,	5441},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9671,	10,	5444},
+	{"cvmx_rnm_eer_dbg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	9672,	1,	5454},
+	{"cvmx_rnm_eer_key"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	9673,	1,	5455},
+	{"cvmx_rnm_serial_num"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9674,	1,	5456},
+	{"cvmx_sli_bist_status"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9675,	24,	5457},
+	{"cvmx_sli_ctl_port#"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9676,	16,	5481},
+	{"cvmx_sli_ctl_status"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9680,	3,	5497},
+	{"cvmx_sli_data_out_cnt"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9681,	5,	5500},
+	{"cvmx_sli_dbg_data"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9682,	3,	5505},
+	{"cvmx_sli_dbg_select"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9683,	3,	5508},
+	{"cvmx_sli_dma#_cnt"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9684,	2,	5511},
+	{"cvmx_sli_dma#_int_level"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9686,	2,	5513},
+	{"cvmx_sli_dma#_tim"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9688,	2,	5515},
+	{"cvmx_sli_int_enb_ciu"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9690,	45,	5517},
+	{"cvmx_sli_int_enb_port#"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9691,	46,	5562},
+	{"cvmx_sli_int_sum"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9693,	46,	5608},
+	{"cvmx_sli_last_win_rdata0"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9694,	1,	5654},
+	{"cvmx_sli_last_win_rdata1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9695,	1,	5655},
+	{"cvmx_sli_last_win_rdata2"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9696,	1,	5656},
+	{"cvmx_sli_last_win_rdata3"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9697,	1,	5657},
+	{"cvmx_sli_mac_credit_cnt"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9698,	13,	5658},
+	{"cvmx_sli_mac_credit_cnt2"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9699,	13,	5671},
+	{"cvmx_sli_mac_number"         ,	CVMX_CSR_DB_TYPE_PEXP,	64,	9700,	3,	5684},
+	{"cvmx_sli_mem_access_ctl"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9701,	3,	5687},
+	{"cvmx_sli_mem_access_subid#"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9702,	9,	5690},
+	{"cvmx_sli_msi_enb0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9718,	1,	5699},
+	{"cvmx_sli_msi_enb1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9719,	1,	5700},
+	{"cvmx_sli_msi_enb2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9720,	1,	5701},
+	{"cvmx_sli_msi_enb3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9721,	1,	5702},
+	{"cvmx_sli_msi_rcv0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9722,	1,	5703},
+	{"cvmx_sli_msi_rcv1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9723,	1,	5704},
+	{"cvmx_sli_msi_rcv2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9724,	1,	5705},
+	{"cvmx_sli_msi_rcv3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9725,	1,	5706},
+	{"cvmx_sli_msi_rd_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9726,	3,	5707},
+	{"cvmx_sli_msi_w1c_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9727,	1,	5710},
+	{"cvmx_sli_msi_w1c_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9728,	1,	5711},
+	{"cvmx_sli_msi_w1c_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9729,	1,	5712},
+	{"cvmx_sli_msi_w1c_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9730,	1,	5713},
+	{"cvmx_sli_msi_w1s_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9731,	1,	5714},
+	{"cvmx_sli_msi_w1s_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9732,	1,	5715},
+	{"cvmx_sli_msi_w1s_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9733,	1,	5716},
+	{"cvmx_sli_msi_w1s_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9734,	1,	5717},
+	{"cvmx_sli_msi_wr_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9735,	3,	5718},
+	{"cvmx_sli_pcie_msi_rcv"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9736,	2,	5721},
+	{"cvmx_sli_pcie_msi_rcv_b1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9737,	3,	5723},
+	{"cvmx_sli_pcie_msi_rcv_b2"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9738,	3,	5726},
+	{"cvmx_sli_pcie_msi_rcv_b3"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9739,	3,	5729},
+	{"cvmx_sli_pkt#_cnts"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9740,	3,	5732},
+	{"cvmx_sli_pkt#_in_bp"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9772,	2,	5735},
+	{"cvmx_sli_pkt#_instr_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9804,	2,	5737},
+	{"cvmx_sli_pkt#_instr_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9836,	2,	5739},
+	{"cvmx_sli_pkt#_instr_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9868,	5,	5741},
+	{"cvmx_sli_pkt#_instr_header"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9900,	21,	5746},
+	{"cvmx_sli_pkt#_out_size"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9932,	3,	5767},
+	{"cvmx_sli_pkt#_slist_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9964,	2,	5770},
+	{"cvmx_sli_pkt#_slist_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	9996,	2,	5772},
+	{"cvmx_sli_pkt#_slist_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10028,	2,	5774},
+	{"cvmx_sli_pkt_cnt_int"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10060,	2,	5776},
+	{"cvmx_sli_pkt_cnt_int_enb"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10061,	2,	5778},
+	{"cvmx_sli_pkt_ctl"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10062,	3,	5780},
+	{"cvmx_sli_pkt_data_out_es"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10063,	1,	5783},
+	{"cvmx_sli_pkt_data_out_ns"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10064,	2,	5784},
+	{"cvmx_sli_pkt_data_out_ror"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10065,	2,	5786},
+	{"cvmx_sli_pkt_dpaddr"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10066,	2,	5788},
+	{"cvmx_sli_pkt_in_bp"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10067,	2,	5790},
+	{"cvmx_sli_pkt_in_done#_cnts"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10068,	2,	5792},
+	{"cvmx_sli_pkt_in_instr_counts",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10100,	2,	5794},
+	{"cvmx_sli_pkt_in_pcie_port"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10101,	1,	5796},
+	{"cvmx_sli_pkt_input_control"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10102,	17,	5797},
+	{"cvmx_sli_pkt_instr_enb"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10103,	2,	5814},
+	{"cvmx_sli_pkt_instr_rd_size"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10104,	1,	5816},
+	{"cvmx_sli_pkt_instr_size"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10105,	2,	5817},
+	{"cvmx_sli_pkt_int_levels"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10106,	3,	5819},
+	{"cvmx_sli_pkt_iptr"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10107,	2,	5822},
+	{"cvmx_sli_pkt_out_bmode"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10108,	2,	5824},
+	{"cvmx_sli_pkt_out_enb"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10109,	2,	5826},
+	{"cvmx_sli_pkt_output_wmark"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10110,	2,	5828},
+	{"cvmx_sli_pkt_pcie_port"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10111,	1,	5830},
+	{"cvmx_sli_pkt_port_in_rst"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10112,	2,	5831},
+	{"cvmx_sli_pkt_slist_es"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10113,	1,	5833},
+	{"cvmx_sli_pkt_slist_ns"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10114,	2,	5834},
+	{"cvmx_sli_pkt_slist_ror"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10115,	2,	5836},
+	{"cvmx_sli_pkt_time_int"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10116,	2,	5838},
+	{"cvmx_sli_pkt_time_int_enb"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10117,	2,	5840},
+	{"cvmx_sli_s2m_port#_ctl"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10118,	4,	5842},
+	{"cvmx_sli_scratch_1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10122,	1,	5846},
+	{"cvmx_sli_scratch_2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10123,	1,	5847},
+	{"cvmx_sli_state1"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10124,	4,	5848},
+	{"cvmx_sli_state2"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10125,	8,	5852},
+	{"cvmx_sli_state3"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10126,	5,	5860},
+	{"cvmx_sli_win_rd_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	10127,	4,	5865},
+	{"cvmx_sli_win_rd_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	10128,	1,	5869},
+	{"cvmx_sli_win_wr_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	10129,	4,	5870},
+	{"cvmx_sli_win_wr_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	10130,	1,	5874},
+	{"cvmx_sli_win_wr_mask"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	10131,	2,	5875},
+	{"cvmx_sli_window_ctl"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	10132,	2,	5877},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	10133,	10,	5879},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	10135,	6,	5889},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	10137,	2,	5895},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	10139,	4,	5897},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	10141,	4,	5901},
+	{"cvmx_smi_drv_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	10143,	4,	5905},
+	{"cvmx_srio#_acc_ctrl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	10144,	8,	5909},
+	{"cvmx_srio#_asmbly_id"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	10147,	3,	5917},
+	{"cvmx_srio#_asmbly_info"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	10150,	3,	5920},
+	{"cvmx_srio#_bell_resp_ctrl"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	10153,	5,	5923},
+	{"cvmx_srio#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	10156,	20,	5928},
+	{"cvmx_srio#_imsg_ctrl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	10159,	14,	5948},
+	{"cvmx_srio#_imsg_inst_hdr#"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	10162,	14,	5962},
+	{"cvmx_srio#_imsg_qos_grp#"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	10168,	24,	5976},
+	{"cvmx_srio#_imsg_status#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	10264,	24,	6000},
+	{"cvmx_srio#_imsg_vport_thr"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	10336,	13,	6024},
+	{"cvmx_srio#_imsg_vport_thr2"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	10339,	5,	6037},
+	{"cvmx_srio#_int2_enable"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	10342,	2,	6042},
+	{"cvmx_srio#_int2_reg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	10345,	4,	6044},
+	{"cvmx_srio#_int_enable"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	10348,	28,	6048},
+	{"cvmx_srio#_int_info0"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	10351,	9,	6076},
+	{"cvmx_srio#_int_info1"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	10354,	1,	6085},
+	{"cvmx_srio#_int_info2"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	10357,	11,	6086},
+	{"cvmx_srio#_int_info3"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	10360,	5,	6097},
+	{"cvmx_srio#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10363,	30,	6102},
+	{"cvmx_srio#_ip_feature"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	10366,	10,	6132},
+	{"cvmx_srio#_mac_buffers"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	10369,	10,	6142},
+	{"cvmx_srio#_maint_op"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	10372,	6,	6152},
+	{"cvmx_srio#_maint_rd_data"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	10375,	3,	6158},
+	{"cvmx_srio#_mce_tx_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	10378,	2,	6161},
+	{"cvmx_srio#_mem_op_ctrl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	10381,	8,	6163},
+	{"cvmx_srio#_omsg_ctrl#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	10384,	11,	6171},
+	{"cvmx_srio#_omsg_done_counts#",	CVMX_CSR_DB_TYPE_RSL,	64,	10390,	3,	6182},
+	{"cvmx_srio#_omsg_fmp_mr#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	10396,	16,	6185},
+	{"cvmx_srio#_omsg_nmp_mr#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	10402,	16,	6201},
+	{"cvmx_srio#_omsg_port#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	10408,	4,	6217},
+	{"cvmx_srio#_omsg_silo_thr"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	10414,	2,	6221},
+	{"cvmx_srio#_omsg_sp_mr#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	10417,	17,	6223},
+	{"cvmx_srio#_prio#_in_use"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	10423,	3,	6240},
+	{"cvmx_srio#_rx_bell"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10435,	9,	6243},
+	{"cvmx_srio#_rx_bell_seq"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	10438,	3,	6252},
+	{"cvmx_srio#_rx_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	10441,	9,	6255},
+	{"cvmx_srio#_s2m_type#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	10444,	11,	6264},
+	{"cvmx_srio#_seq"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	10492,	2,	6275},
+	{"cvmx_srio#_status_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	10495,	3,	6277},
+	{"cvmx_srio#_tag_ctrl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	10498,	6,	6280},
+	{"cvmx_srio#_tlp_credits"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	10501,	6,	6286},
+	{"cvmx_srio#_tx_bell"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10504,	10,	6292},
+	{"cvmx_srio#_tx_bell_info"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	10507,	11,	6302},
+	{"cvmx_srio#_tx_ctrl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10510,	12,	6313},
+	{"cvmx_srio#_tx_emphasis"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	10513,	2,	6325},
+	{"cvmx_srio#_tx_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	10516,	5,	6327},
+	{"cvmx_srio#_wr_done_counts"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	10519,	3,	6332},
+	{"cvmx_sriomaint#_asmbly_id"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10522,	2,	6335},
+	{"cvmx_sriomaint#_asmbly_info" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10525,	2,	6337},
+	{"cvmx_sriomaint#_bar1_idx#"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10528,	7,	6339},
+	{"cvmx_sriomaint#_bell_status" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10576,	2,	6346},
+	{"cvmx_sriomaint#_comp_tag"    ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10579,	1,	6348},
+	{"cvmx_sriomaint#_core_enables",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10582,	6,	6349},
+	{"cvmx_sriomaint#_dev_id"      ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10585,	2,	6355},
+	{"cvmx_sriomaint#_dev_rev"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10588,	2,	6357},
+	{"cvmx_sriomaint#_dst_ops"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10591,	26,	6359},
+	{"cvmx_sriomaint#_erb_attr_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10594,	5,	6385},
+	{"cvmx_sriomaint#_erb_err_det" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10597,	17,	6390},
+	{"cvmx_sriomaint#_erb_err_rate",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10600,	5,	6407},
+	{"cvmx_sriomaint#_erb_err_rate_en",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10603,	17,	6412},
+	{"cvmx_sriomaint#_erb_err_rate_thr",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10606,	3,	6429},
+	{"cvmx_sriomaint#_erb_hdr"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10609,	2,	6432},
+	{"cvmx_sriomaint#_erb_lt_addr_capt_h",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10612,	1,	6434},
+	{"cvmx_sriomaint#_erb_lt_addr_capt_l",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10615,	3,	6435},
+	{"cvmx_sriomaint#_erb_lt_ctrl_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10618,	9,	6438},
+	{"cvmx_sriomaint#_erb_lt_dev_id",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10621,	4,	6447},
+	{"cvmx_sriomaint#_erb_lt_dev_id_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10624,	4,	6451},
+	{"cvmx_sriomaint#_erb_lt_err_det",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10627,	12,	6455},
+	{"cvmx_sriomaint#_erb_lt_err_en",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10630,	12,	6467},
+	{"cvmx_sriomaint#_erb_pack_capt_1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10633,	1,	6479},
+	{"cvmx_sriomaint#_erb_pack_capt_2",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10636,	1,	6480},
+	{"cvmx_sriomaint#_erb_pack_capt_3",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10639,	1,	6481},
+	{"cvmx_sriomaint#_erb_pack_sym_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10642,	1,	6482},
+	{"cvmx_sriomaint#_hb_dev_id_lock",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10645,	2,	6483},
+	{"cvmx_sriomaint#_ir_buffer_config",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10648,	7,	6485},
+	{"cvmx_sriomaint#_ir_buffer_config2",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10651,	8,	6492},
+	{"cvmx_sriomaint#_ir_pd_phy_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10654,	1,	6500},
+	{"cvmx_sriomaint#_ir_pd_phy_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10657,	9,	6501},
+	{"cvmx_sriomaint#_ir_pi_phy_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10660,	5,	6510},
+	{"cvmx_sriomaint#_ir_pi_phy_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10663,	4,	6515},
+	{"cvmx_sriomaint#_ir_sp_rx_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10666,	2,	6519},
+	{"cvmx_sriomaint#_ir_sp_rx_data",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10669,	1,	6521},
+	{"cvmx_sriomaint#_ir_sp_rx_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10672,	5,	6522},
+	{"cvmx_sriomaint#_ir_sp_tx_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10675,	2,	6527},
+	{"cvmx_sriomaint#_ir_sp_tx_data",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10678,	1,	6529},
+	{"cvmx_sriomaint#_ir_sp_tx_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10681,	5,	6530},
+	{"cvmx_sriomaint#_lane_#_status_0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10684,	15,	6535},
+	{"cvmx_sriomaint#_lcs_ba0"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10696,	2,	6550},
+	{"cvmx_sriomaint#_lcs_ba1"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10699,	2,	6552},
+	{"cvmx_sriomaint#_m2s_bar0_start0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10702,	2,	6554},
+	{"cvmx_sriomaint#_m2s_bar0_start1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10705,	4,	6556},
+	{"cvmx_sriomaint#_m2s_bar1_start0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10708,	2,	6560},
+	{"cvmx_sriomaint#_m2s_bar1_start1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10711,	5,	6562},
+	{"cvmx_sriomaint#_m2s_bar2_start",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10714,	7,	6567},
+	{"cvmx_sriomaint#_mac_ctrl"    ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10717,	7,	6574},
+	{"cvmx_sriomaint#_pe_feat"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10720,	11,	6581},
+	{"cvmx_sriomaint#_pe_llc"      ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10723,	2,	6592},
+	{"cvmx_sriomaint#_port_0_ctl"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10726,	18,	6594},
+	{"cvmx_sriomaint#_port_0_ctl2" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10729,	16,	6612},
+	{"cvmx_sriomaint#_port_0_err_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10732,	20,	6628},
+	{"cvmx_sriomaint#_port_0_link_req",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10735,	2,	6648},
+	{"cvmx_sriomaint#_port_0_link_resp",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10738,	4,	6650},
+	{"cvmx_sriomaint#_port_0_local_ackid",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10741,	6,	6654},
+	{"cvmx_sriomaint#_port_gen_ctl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10744,	4,	6660},
+	{"cvmx_sriomaint#_port_lt_ctl" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10747,	2,	6664},
+	{"cvmx_sriomaint#_port_mbh0"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10750,	2,	6666},
+	{"cvmx_sriomaint#_port_rt_ctl" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10753,	2,	6668},
+	{"cvmx_sriomaint#_port_ttl_ctl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10756,	2,	6670},
+	{"cvmx_sriomaint#_pri_dev_id"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10759,	3,	6672},
+	{"cvmx_sriomaint#_sec_dev_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10762,	3,	6675},
+	{"cvmx_sriomaint#_sec_dev_id"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10765,	3,	6678},
+	{"cvmx_sriomaint#_serial_lane_hdr",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10768,	2,	6681},
+	{"cvmx_sriomaint#_src_ops"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10771,	26,	6683},
+	{"cvmx_sriomaint#_tx_drop"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	10774,	3,	6709},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	10777,	6,	6712},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	10778,	3,	6718},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	10779,	5,	6721},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10780,	4,	6726},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10781,	6,	6730},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	10782,	4,	6736},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10783,	2,	6740},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10784,	4,	6742},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	10785,	2,	6746},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	10786,	3,	6748},
+	{"cvmx_tra#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	10787,	2,	6751},
+	{"cvmx_tra#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	10788,	14,	6753},
+	{"cvmx_tra#_cycles_since"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	10789,	3,	6767},
+	{"cvmx_tra#_cycles_since1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	10790,	5,	6770},
+	{"cvmx_tra#_filt_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	10791,	2,	6775},
+	{"cvmx_tra#_filt_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	10792,	2,	6777},
+	{"cvmx_tra#_filt_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10793,	57,	6779},
+	{"cvmx_tra#_filt_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10794,	20,	6836},
+	{"cvmx_tra#_filt_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10795,	7,	6856},
+	{"cvmx_tra#_int_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	10796,	5,	6863},
+	{"cvmx_tra#_read_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10797,	1,	6868},
+	{"cvmx_tra#_read_dat_hi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	10798,	2,	6869},
+	{"cvmx_tra#_trig0_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	10799,	2,	6871},
+	{"cvmx_tra#_trig0_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	10800,	2,	6873},
+	{"cvmx_tra#_trig0_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	10801,	57,	6875},
+	{"cvmx_tra#_trig0_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	10802,	20,	6932},
+	{"cvmx_tra#_trig0_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	10803,	7,	6952},
+	{"cvmx_tra#_trig1_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	10804,	2,	6959},
+	{"cvmx_tra#_trig1_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	10805,	2,	6961},
+	{"cvmx_tra#_trig1_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	10806,	57,	6963},
+	{"cvmx_tra#_trig1_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	10807,	20,	7020},
+	{"cvmx_tra#_trig1_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	10808,	7,	7040},
+	{"cvmx_uahc#_ehci_asynclistaddr",	CVMX_CSR_DB_TYPE_NCB,	32,	10809,	2,	7047},
+	{"cvmx_uahc#_ehci_configflag"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	10810,	2,	7049},
+	{"cvmx_uahc#_ehci_ctrldssegment",	CVMX_CSR_DB_TYPE_NCB,	32,	10811,	1,	7051},
+	{"cvmx_uahc#_ehci_frindex"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	10812,	2,	7052},
+	{"cvmx_uahc#_ehci_hccapbase"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	10813,	3,	7054},
+	{"cvmx_uahc#_ehci_hccparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	10814,	7,	7057},
+	{"cvmx_uahc#_ehci_hcsparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	10815,	10,	7064},
+	{"cvmx_uahc#_ehci_insnreg00"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	10816,	3,	7074},
+	{"cvmx_uahc#_ehci_insnreg03"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	10817,	5,	7077},
+	{"cvmx_uahc#_ehci_insnreg04"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	10818,	7,	7082},
+	{"cvmx_uahc#_ehci_insnreg06"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	10819,	2,	7089},
+	{"cvmx_uahc#_ehci_insnreg07"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	10820,	1,	7091},
+	{"cvmx_uahc#_ehci_periodiclistbase",	CVMX_CSR_DB_TYPE_NCB,	32,	10821,	2,	7092},
+	{"cvmx_uahc#_ehci_portsc#"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	10822,	19,	7094},
+	{"cvmx_uahc#_ehci_usbcmd"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	10824,	13,	7113},
+	{"cvmx_uahc#_ehci_usbintr"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	10825,	7,	7126},
+	{"cvmx_uahc#_ehci_usbsts"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	10826,	12,	7133},
+	{"cvmx_uahc#_ohci0_hcbulkcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	10827,	2,	7145},
+	{"cvmx_uahc#_ohci0_hcbulkheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	10828,	2,	7147},
+	{"cvmx_uahc#_ohci0_hccommandstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	10829,	7,	7149},
+	{"cvmx_uahc#_ohci0_hccontrol"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	10830,	10,	7156},
+	{"cvmx_uahc#_ohci0_hccontrolcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	10831,	2,	7166},
+	{"cvmx_uahc#_ohci0_hccontrolheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	10832,	2,	7168},
+	{"cvmx_uahc#_ohci0_hcdonehead" ,	CVMX_CSR_DB_TYPE_NCB,	32,	10833,	2,	7170},
+	{"cvmx_uahc#_ohci0_hcfminterval",	CVMX_CSR_DB_TYPE_NCB,	32,	10834,	4,	7172},
+	{"cvmx_uahc#_ohci0_hcfmnumber" ,	CVMX_CSR_DB_TYPE_NCB,	32,	10835,	2,	7176},
+	{"cvmx_uahc#_ohci0_hcfmremaining",	CVMX_CSR_DB_TYPE_NCB,	32,	10836,	3,	7178},
+	{"cvmx_uahc#_ohci0_hchcca"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	10837,	2,	7181},
+	{"cvmx_uahc#_ohci0_hcinterruptdisable",	CVMX_CSR_DB_TYPE_NCB,	32,	10838,	10,	7183},
+	{"cvmx_uahc#_ohci0_hcinterruptenable",	CVMX_CSR_DB_TYPE_NCB,	32,	10839,	10,	7193},
+	{"cvmx_uahc#_ohci0_hcinterruptstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	10840,	10,	7203},
+	{"cvmx_uahc#_ohci0_hclsthreshold",	CVMX_CSR_DB_TYPE_NCB,	32,	10841,	2,	7213},
+	{"cvmx_uahc#_ohci0_hcperiodcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	10842,	2,	7215},
+	{"cvmx_uahc#_ohci0_hcperiodicstart",	CVMX_CSR_DB_TYPE_NCB,	32,	10843,	2,	7217},
+	{"cvmx_uahc#_ohci0_hcrevision" ,	CVMX_CSR_DB_TYPE_NCB,	32,	10844,	2,	7219},
+	{"cvmx_uahc#_ohci0_hcrhdescriptora",	CVMX_CSR_DB_TYPE_NCB,	32,	10845,	8,	7221},
+	{"cvmx_uahc#_ohci0_hcrhdescriptorb",	CVMX_CSR_DB_TYPE_NCB,	32,	10846,	2,	7229},
+	{"cvmx_uahc#_ohci0_hcrhportstatus#",	CVMX_CSR_DB_TYPE_NCB,	32,	10847,	15,	7231},
+	{"cvmx_uahc#_ohci0_hcrhstatus" ,	CVMX_CSR_DB_TYPE_NCB,	32,	10849,	8,	7246},
+	{"cvmx_uahc#_ohci0_insnreg06"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	10850,	2,	7254},
+	{"cvmx_uahc#_ohci0_insnreg07"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	10851,	1,	7256},
+	{"cvmx_uctl#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	10852,	7,	7257},
+	{"cvmx_uctl#_clk_rst_ctl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	10853,	21,	7264},
+	{"cvmx_uctl#_ehci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	10854,	12,	7285},
+	{"cvmx_uctl#_ehci_fla"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	10855,	2,	7297},
+	{"cvmx_uctl#_erto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	10856,	3,	7299},
+	{"cvmx_uctl#_if_ena"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	10857,	2,	7302},
+	{"cvmx_uctl#_int_ena"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10858,	9,	7304},
+	{"cvmx_uctl#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10859,	9,	7313},
+	{"cvmx_uctl#_ohci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	10860,	11,	7322},
+	{"cvmx_uctl#_orto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	10861,	3,	7333},
+	{"cvmx_uctl#_ppaf_wm"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10862,	2,	7336},
+	{"cvmx_uctl#_uphy_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	10863,	11,	7338},
+	{"cvmx_uctl#_uphy_port#_ctl_status",	CVMX_CSR_DB_TYPE_RSL,	64,	10864,	20,	7349},
+	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	10866,	3,	7369},
+	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	10867,	5,	7372},
+	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	10868,	3,	7377},
+	{"cvmx_zip_constants"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10869,	8,	7380},
+	{"cvmx_zip_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	10870,	2,	7388},
+	{"cvmx_zip_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	10871,	2,	7390},
+	{"cvmx_zip_int_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	10872,	2,	7392},
+	{"cvmx_zip_throttle"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	10873,	2,	7394},
+	{NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn66xx[] = {
+	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
+	{"AGL_GMX_BAD_REG"             ,	   0x11800e0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"AGL_GMX_BIST"                ,	   0x11800e0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"AGL_GMX_PRT0_CFG"            ,	   0x11800e0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"AGL_GMX_PRT1_CFG"            ,	   0x11800e0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"AGL_GMX_RX0_ADR_CAM0"        ,	   0x11800e0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"AGL_GMX_RX1_ADR_CAM0"        ,	   0x11800e0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"AGL_GMX_RX0_ADR_CAM1"        ,	   0x11800e0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_RX1_ADR_CAM1"        ,	   0x11800e0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_RX0_ADR_CAM2"        ,	   0x11800e0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX1_ADR_CAM2"        ,	   0x11800e0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX0_ADR_CAM3"        ,	   0x11800e0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX1_ADR_CAM3"        ,	   0x11800e0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX0_ADR_CAM4"        ,	   0x11800e00001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX1_ADR_CAM4"        ,	   0x11800e00009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX0_ADR_CAM5"        ,	   0x11800e00001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX1_ADR_CAM5"        ,	   0x11800e00009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX0_ADR_CAM_EN"      ,	   0x11800e0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX1_ADR_CAM_EN"      ,	   0x11800e0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX0_ADR_CTL"         ,	   0x11800e0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX1_ADR_CTL"         ,	   0x11800e0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX0_DECISION"        ,	   0x11800e0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX1_DECISION"        ,	   0x11800e0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX0_FRM_CHK"         ,	   0x11800e0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX1_FRM_CHK"         ,	   0x11800e0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX0_FRM_CTL"         ,	   0x11800e0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX1_FRM_CTL"         ,	   0x11800e0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX0_FRM_MAX"         ,	   0x11800e0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX1_FRM_MAX"         ,	   0x11800e0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX0_FRM_MIN"         ,	   0x11800e0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX1_FRM_MIN"         ,	   0x11800e0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX0_IFG"             ,	   0x11800e0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX1_IFG"             ,	   0x11800e0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX0_INT_EN"          ,	   0x11800e0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX1_INT_EN"          ,	   0x11800e0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX0_INT_REG"         ,	   0x11800e0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX1_INT_REG"         ,	   0x11800e0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX0_JABBER"          ,	   0x11800e0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX1_JABBER"          ,	   0x11800e0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX0_PAUSE_DROP_TIME" ,	   0x11800e0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX1_PAUSE_DROP_TIME" ,	   0x11800e0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX0_RX_INBND"        ,	   0x11800e0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX1_RX_INBND"        ,	   0x11800e0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX0_STATS_CTL"       ,	   0x11800e0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX1_STATS_CTL"       ,	   0x11800e0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX0_STATS_OCTS"      ,	   0x11800e0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX1_STATS_OCTS"      ,	   0x11800e0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX0_STATS_OCTS_CTL"  ,	   0x11800e0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX1_STATS_OCTS_CTL"  ,	   0x11800e0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX0_STATS_OCTS_DMAC" ,	   0x11800e00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX1_STATS_OCTS_DMAC" ,	   0x11800e00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX0_STATS_OCTS_DRP"  ,	   0x11800e00000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX1_STATS_OCTS_DRP"  ,	   0x11800e00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX0_STATS_PKTS"      ,	   0x11800e0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX1_STATS_PKTS"      ,	   0x11800e0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX0_STATS_PKTS_BAD"  ,	   0x11800e00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX1_STATS_PKTS_BAD"  ,	   0x11800e00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX0_STATS_PKTS_CTL"  ,	   0x11800e0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX1_STATS_PKTS_CTL"  ,	   0x11800e0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX0_STATS_PKTS_DMAC" ,	   0x11800e00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX1_STATS_PKTS_DMAC" ,	   0x11800e00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX0_STATS_PKTS_DRP"  ,	   0x11800e00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX1_STATS_PKTS_DRP"  ,	   0x11800e00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX0_UDD_SKP"         ,	   0x11800e0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX1_UDD_SKP"         ,	   0x11800e0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX_BP_DROP0"         ,	   0x11800e0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX_BP_DROP1"         ,	   0x11800e0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX_BP_OFF0"          ,	   0x11800e0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_OFF1"          ,	   0x11800e0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_ON0"           ,	   0x11800e0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_BP_ON1"           ,	   0x11800e0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_PRT_INFO"         ,	   0x11800e00004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"AGL_GMX_RX_TX_STATUS"        ,	   0x11800e00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"AGL_GMX_SMAC0"               ,	   0x11800e0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"AGL_GMX_SMAC1"               ,	   0x11800e0000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"AGL_GMX_STAT_BP"             ,	   0x11800e0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"AGL_GMX_TX0_APPEND"          ,	   0x11800e0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"AGL_GMX_TX1_APPEND"          ,	   0x11800e0000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"AGL_GMX_TX0_CLK"             ,	   0x11800e0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX1_CLK"             ,	   0x11800e0000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX0_CTL"             ,	   0x11800e0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX1_CTL"             ,	   0x11800e0000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX0_MIN_PKT"         ,	   0x11800e0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX1_MIN_PKT"         ,	   0x11800e0000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",	   0x11800e0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX1_PAUSE_PKT_INTERVAL",	   0x11800e0000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,	   0x11800e0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX1_PAUSE_PKT_TIME"  ,	   0x11800e0000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX0_PAUSE_TOGO"      ,	   0x11800e0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX1_PAUSE_TOGO"      ,	   0x11800e0000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX0_PAUSE_ZERO"      ,	   0x11800e0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX1_PAUSE_ZERO"      ,	   0x11800e0000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX0_SOFT_PAUSE"      ,	   0x11800e0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX1_SOFT_PAUSE"      ,	   0x11800e0000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX0_STAT0"           ,	   0x11800e0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX1_STAT0"           ,	   0x11800e0000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX0_STAT1"           ,	   0x11800e0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX1_STAT1"           ,	   0x11800e0000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX0_STAT2"           ,	   0x11800e0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX1_STAT2"           ,	   0x11800e0000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX0_STAT3"           ,	   0x11800e0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX1_STAT3"           ,	   0x11800e0000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX0_STAT4"           ,	   0x11800e00002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX1_STAT4"           ,	   0x11800e0000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX0_STAT5"           ,	   0x11800e00002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX1_STAT5"           ,	   0x11800e0000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX0_STAT6"           ,	   0x11800e00002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX1_STAT6"           ,	   0x11800e0000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX0_STAT7"           ,	   0x11800e00002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX1_STAT7"           ,	   0x11800e0000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX0_STAT8"           ,	   0x11800e00002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX1_STAT8"           ,	   0x11800e0000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX0_STAT9"           ,	   0x11800e00002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX1_STAT9"           ,	   0x11800e0000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX0_STATS_CTL"       ,	   0x11800e0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX1_STATS_CTL"       ,	   0x11800e0000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX0_THRESH"          ,	   0x11800e0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX1_THRESH"          ,	   0x11800e0000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX_BP"               ,	   0x11800e00004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"AGL_GMX_TX_COL_ATTEMPT"      ,	   0x11800e0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"AGL_GMX_TX_IFG"              ,	   0x11800e0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"AGL_GMX_TX_INT_EN"           ,	   0x11800e0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"AGL_GMX_TX_INT_REG"          ,	   0x11800e0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"AGL_GMX_TX_JAM"              ,	   0x11800e0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"AGL_GMX_TX_LFSR"             ,	   0x11800e00004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"AGL_GMX_TX_OVR_BP"           ,	   0x11800e00004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,	   0x11800e00004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,	   0x11800e00004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"AGL_PRT0_CTL"                ,	   0x11800e0002000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"AGL_PRT1_CTL"                ,	   0x11800e0002008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
+	{"CIU_BLOCK_INT"               ,	   0x10700000007c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU_EN2_IO0_INT"             ,	   0x107000000a600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_EN2_IO1_INT"             ,	   0x107000000a608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_EN2_IO0_INT_W1C"         ,	   0x107000000ce00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_EN2_IO1_INT_W1C"         ,	   0x107000000ce08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_EN2_IO0_INT_W1S"         ,	   0x107000000ae00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_EN2_IO1_INT_W1S"         ,	   0x107000000ae08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_EN2_PP0_IP2"             ,	   0x107000000a000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_EN2_PP1_IP2"             ,	   0x107000000a008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_EN2_PP2_IP2"             ,	   0x107000000a010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_EN2_PP3_IP2"             ,	   0x107000000a018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_EN2_PP4_IP2"             ,	   0x107000000a020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_EN2_PP5_IP2"             ,	   0x107000000a028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_EN2_PP6_IP2"             ,	   0x107000000a030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_EN2_PP7_IP2"             ,	   0x107000000a038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_EN2_PP8_IP2"             ,	   0x107000000a040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_EN2_PP9_IP2"             ,	   0x107000000a048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_EN2_PP0_IP2_W1C"         ,	   0x107000000c800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_EN2_PP1_IP2_W1C"         ,	   0x107000000c808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_EN2_PP2_IP2_W1C"         ,	   0x107000000c810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_EN2_PP3_IP2_W1C"         ,	   0x107000000c818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_EN2_PP4_IP2_W1C"         ,	   0x107000000c820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_EN2_PP5_IP2_W1C"         ,	   0x107000000c828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_EN2_PP6_IP2_W1C"         ,	   0x107000000c830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_EN2_PP7_IP2_W1C"         ,	   0x107000000c838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_EN2_PP8_IP2_W1C"         ,	   0x107000000c840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_EN2_PP9_IP2_W1C"         ,	   0x107000000c848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_EN2_PP0_IP2_W1S"         ,	   0x107000000a800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_EN2_PP1_IP2_W1S"         ,	   0x107000000a808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_EN2_PP2_IP2_W1S"         ,	   0x107000000a810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_EN2_PP3_IP2_W1S"         ,	   0x107000000a818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_EN2_PP4_IP2_W1S"         ,	   0x107000000a820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_EN2_PP5_IP2_W1S"         ,	   0x107000000a828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_EN2_PP6_IP2_W1S"         ,	   0x107000000a830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_EN2_PP7_IP2_W1S"         ,	   0x107000000a838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_EN2_PP8_IP2_W1S"         ,	   0x107000000a840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_EN2_PP9_IP2_W1S"         ,	   0x107000000a848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_EN2_PP0_IP3"             ,	   0x107000000a200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_EN2_PP1_IP3"             ,	   0x107000000a208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_EN2_PP2_IP3"             ,	   0x107000000a210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_EN2_PP3_IP3"             ,	   0x107000000a218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_EN2_PP4_IP3"             ,	   0x107000000a220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_EN2_PP5_IP3"             ,	   0x107000000a228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_EN2_PP6_IP3"             ,	   0x107000000a230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_EN2_PP7_IP3"             ,	   0x107000000a238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_EN2_PP8_IP3"             ,	   0x107000000a240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_EN2_PP9_IP3"             ,	   0x107000000a248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_EN2_PP0_IP3_W1C"         ,	   0x107000000ca00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_EN2_PP1_IP3_W1C"         ,	   0x107000000ca08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_EN2_PP2_IP3_W1C"         ,	   0x107000000ca10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_EN2_PP3_IP3_W1C"         ,	   0x107000000ca18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_EN2_PP4_IP3_W1C"         ,	   0x107000000ca20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_EN2_PP5_IP3_W1C"         ,	   0x107000000ca28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_EN2_PP6_IP3_W1C"         ,	   0x107000000ca30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_EN2_PP7_IP3_W1C"         ,	   0x107000000ca38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_EN2_PP8_IP3_W1C"         ,	   0x107000000ca40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_EN2_PP9_IP3_W1C"         ,	   0x107000000ca48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_EN2_PP0_IP3_W1S"         ,	   0x107000000aa00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_EN2_PP1_IP3_W1S"         ,	   0x107000000aa08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_EN2_PP2_IP3_W1S"         ,	   0x107000000aa10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_EN2_PP3_IP3_W1S"         ,	   0x107000000aa18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_EN2_PP4_IP3_W1S"         ,	   0x107000000aa20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_EN2_PP5_IP3_W1S"         ,	   0x107000000aa28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_EN2_PP6_IP3_W1S"         ,	   0x107000000aa30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_EN2_PP7_IP3_W1S"         ,	   0x107000000aa38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_EN2_PP8_IP3_W1S"         ,	   0x107000000aa40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_EN2_PP9_IP3_W1S"         ,	   0x107000000aa48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_EN2_PP0_IP4"             ,	   0x107000000a400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_EN2_PP1_IP4"             ,	   0x107000000a408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_EN2_PP2_IP4"             ,	   0x107000000a410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_EN2_PP3_IP4"             ,	   0x107000000a418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_EN2_PP4_IP4"             ,	   0x107000000a420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_EN2_PP5_IP4"             ,	   0x107000000a428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_EN2_PP6_IP4"             ,	   0x107000000a430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_EN2_PP7_IP4"             ,	   0x107000000a438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_EN2_PP8_IP4"             ,	   0x107000000a440ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_EN2_PP9_IP4"             ,	   0x107000000a448ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_EN2_PP0_IP4_W1C"         ,	   0x107000000cc00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_EN2_PP1_IP4_W1C"         ,	   0x107000000cc08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_EN2_PP2_IP4_W1C"         ,	   0x107000000cc10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_EN2_PP3_IP4_W1C"         ,	   0x107000000cc18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_EN2_PP4_IP4_W1C"         ,	   0x107000000cc20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_EN2_PP5_IP4_W1C"         ,	   0x107000000cc28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_EN2_PP6_IP4_W1C"         ,	   0x107000000cc30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_EN2_PP7_IP4_W1C"         ,	   0x107000000cc38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_EN2_PP8_IP4_W1C"         ,	   0x107000000cc40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_EN2_PP9_IP4_W1C"         ,	   0x107000000cc48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_EN2_PP0_IP4_W1S"         ,	   0x107000000ac00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_EN2_PP1_IP4_W1S"         ,	   0x107000000ac08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_EN2_PP2_IP4_W1S"         ,	   0x107000000ac10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_EN2_PP3_IP4_W1S"         ,	   0x107000000ac18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_EN2_PP4_IP4_W1S"         ,	   0x107000000ac20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_EN2_PP5_IP4_W1S"         ,	   0x107000000ac28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_EN2_PP6_IP4_W1S"         ,	   0x107000000ac30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_EN2_PP7_IP4_W1S"         ,	   0x107000000ac38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_EN2_PP8_IP4_W1S"         ,	   0x107000000ac40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_EN2_PP9_IP4_W1S"         ,	   0x107000000ac48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_GSTOP"                   ,	   0x1070000000710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT0_EN0"                ,	   0x1070000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT1_EN0"                ,	   0x1070000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT2_EN0"                ,	   0x1070000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT3_EN0"                ,	   0x1070000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT4_EN0"                ,	   0x1070000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT5_EN0"                ,	   0x1070000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT6_EN0"                ,	   0x1070000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT8_EN0"                ,	   0x1070000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT9_EN0"                ,	   0x1070000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT10_EN0"               ,	   0x10700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT11_EN0"               ,	   0x10700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT12_EN0"               ,	   0x10700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT13_EN0"               ,	   0x10700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT14_EN0"               ,	   0x10700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT15_EN0"               ,	   0x10700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT16_EN0"               ,	   0x1070000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT17_EN0"               ,	   0x1070000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT18_EN0"               ,	   0x1070000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT19_EN0"               ,	   0x1070000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT33_EN0"               ,	   0x1070000000410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT0_EN0_W1C"            ,	   0x1070000002200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT1_EN0_W1C"            ,	   0x1070000002210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT2_EN0_W1C"            ,	   0x1070000002220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT3_EN0_W1C"            ,	   0x1070000002230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT4_EN0_W1C"            ,	   0x1070000002240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT5_EN0_W1C"            ,	   0x1070000002250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT6_EN0_W1C"            ,	   0x1070000002260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT7_EN0_W1C"            ,	   0x1070000002270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT8_EN0_W1C"            ,	   0x1070000002280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT9_EN0_W1C"            ,	   0x1070000002290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT10_EN0_W1C"           ,	   0x10700000022a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT11_EN0_W1C"           ,	   0x10700000022b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT12_EN0_W1C"           ,	   0x10700000022c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT13_EN0_W1C"           ,	   0x10700000022d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT14_EN0_W1C"           ,	   0x10700000022e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT15_EN0_W1C"           ,	   0x10700000022f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT16_EN0_W1C"           ,	   0x1070000002300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT17_EN0_W1C"           ,	   0x1070000002310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT18_EN0_W1C"           ,	   0x1070000002320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT19_EN0_W1C"           ,	   0x1070000002330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT32_EN0_W1C"           ,	   0x1070000002400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT33_EN0_W1C"           ,	   0x1070000002410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT0_EN0_W1S"            ,	   0x1070000006200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT1_EN0_W1S"            ,	   0x1070000006210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT2_EN0_W1S"            ,	   0x1070000006220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT3_EN0_W1S"            ,	   0x1070000006230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT4_EN0_W1S"            ,	   0x1070000006240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT5_EN0_W1S"            ,	   0x1070000006250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT6_EN0_W1S"            ,	   0x1070000006260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT7_EN0_W1S"            ,	   0x1070000006270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT8_EN0_W1S"            ,	   0x1070000006280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT9_EN0_W1S"            ,	   0x1070000006290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT10_EN0_W1S"           ,	   0x10700000062a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT11_EN0_W1S"           ,	   0x10700000062b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT12_EN0_W1S"           ,	   0x10700000062c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT13_EN0_W1S"           ,	   0x10700000062d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT14_EN0_W1S"           ,	   0x10700000062e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT15_EN0_W1S"           ,	   0x10700000062f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT16_EN0_W1S"           ,	   0x1070000006300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT17_EN0_W1S"           ,	   0x1070000006310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT18_EN0_W1S"           ,	   0x1070000006320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT19_EN0_W1S"           ,	   0x1070000006330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT32_EN0_W1S"           ,	   0x1070000006400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT33_EN0_W1S"           ,	   0x1070000006410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT2_EN1"                ,	   0x1070000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT3_EN1"                ,	   0x1070000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT4_EN1"                ,	   0x1070000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT5_EN1"                ,	   0x1070000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT6_EN1"                ,	   0x1070000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT8_EN1"                ,	   0x1070000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT9_EN1"                ,	   0x1070000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT10_EN1"               ,	   0x10700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT11_EN1"               ,	   0x10700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT12_EN1"               ,	   0x10700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT13_EN1"               ,	   0x10700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT14_EN1"               ,	   0x10700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT15_EN1"               ,	   0x10700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT16_EN1"               ,	   0x1070000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT17_EN1"               ,	   0x1070000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT18_EN1"               ,	   0x1070000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT19_EN1"               ,	   0x1070000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT33_EN1"               ,	   0x1070000000418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT0_EN1_W1C"            ,	   0x1070000002208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT1_EN1_W1C"            ,	   0x1070000002218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT2_EN1_W1C"            ,	   0x1070000002228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT3_EN1_W1C"            ,	   0x1070000002238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT4_EN1_W1C"            ,	   0x1070000002248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT5_EN1_W1C"            ,	   0x1070000002258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT6_EN1_W1C"            ,	   0x1070000002268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT7_EN1_W1C"            ,	   0x1070000002278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT8_EN1_W1C"            ,	   0x1070000002288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT9_EN1_W1C"            ,	   0x1070000002298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT10_EN1_W1C"           ,	   0x10700000022a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT11_EN1_W1C"           ,	   0x10700000022b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT12_EN1_W1C"           ,	   0x10700000022c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT13_EN1_W1C"           ,	   0x10700000022d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT14_EN1_W1C"           ,	   0x10700000022e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT15_EN1_W1C"           ,	   0x10700000022f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT16_EN1_W1C"           ,	   0x1070000002308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT17_EN1_W1C"           ,	   0x1070000002318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT18_EN1_W1C"           ,	   0x1070000002328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT19_EN1_W1C"           ,	   0x1070000002338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT32_EN1_W1C"           ,	   0x1070000002408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT33_EN1_W1C"           ,	   0x1070000002418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_INT0_EN1_W1S"            ,	   0x1070000006208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT1_EN1_W1S"            ,	   0x1070000006218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT2_EN1_W1S"            ,	   0x1070000006228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT3_EN1_W1S"            ,	   0x1070000006238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT4_EN1_W1S"            ,	   0x1070000006248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT5_EN1_W1S"            ,	   0x1070000006258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT6_EN1_W1S"            ,	   0x1070000006268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT7_EN1_W1S"            ,	   0x1070000006278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT8_EN1_W1S"            ,	   0x1070000006288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT9_EN1_W1S"            ,	   0x1070000006298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT10_EN1_W1S"           ,	   0x10700000062a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT11_EN1_W1S"           ,	   0x10700000062b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT12_EN1_W1S"           ,	   0x10700000062c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT13_EN1_W1S"           ,	   0x10700000062d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT14_EN1_W1S"           ,	   0x10700000062e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT15_EN1_W1S"           ,	   0x10700000062f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT16_EN1_W1S"           ,	   0x1070000006308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT17_EN1_W1S"           ,	   0x1070000006318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT18_EN1_W1S"           ,	   0x1070000006328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT19_EN1_W1S"           ,	   0x1070000006338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT32_EN1_W1S"           ,	   0x1070000006408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT33_EN1_W1S"           ,	   0x1070000006418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_INT2_EN4_0"              ,	   0x1070000000ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_INT3_EN4_0"              ,	   0x1070000000cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_INT4_EN4_0"              ,	   0x1070000000cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_INT5_EN4_0"              ,	   0x1070000000cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_INT6_EN4_0"              ,	   0x1070000000ce0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_INT7_EN4_0"              ,	   0x1070000000cf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_INT8_EN4_0"              ,	   0x1070000000d00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_INT9_EN4_0"              ,	   0x1070000000d10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_INT0_EN4_0_W1C"          ,	   0x1070000002c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_INT1_EN4_0_W1C"          ,	   0x1070000002c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_INT2_EN4_0_W1C"          ,	   0x1070000002ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_INT3_EN4_0_W1C"          ,	   0x1070000002cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_INT4_EN4_0_W1C"          ,	   0x1070000002cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_INT5_EN4_0_W1C"          ,	   0x1070000002cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_INT6_EN4_0_W1C"          ,	   0x1070000002ce0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_INT7_EN4_0_W1C"          ,	   0x1070000002cf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_INT8_EN4_0_W1C"          ,	   0x1070000002d00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_INT9_EN4_0_W1C"          ,	   0x1070000002d10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_INT0_EN4_0_W1S"          ,	   0x1070000006c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_INT1_EN4_0_W1S"          ,	   0x1070000006c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_INT2_EN4_0_W1S"          ,	   0x1070000006ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_INT3_EN4_0_W1S"          ,	   0x1070000006cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_INT4_EN4_0_W1S"          ,	   0x1070000006cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_INT5_EN4_0_W1S"          ,	   0x1070000006cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_INT6_EN4_0_W1S"          ,	   0x1070000006ce0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_INT7_EN4_0_W1S"          ,	   0x1070000006cf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_INT8_EN4_0_W1S"          ,	   0x1070000006d00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_INT9_EN4_0_W1S"          ,	   0x1070000006d10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_INT2_EN4_1"              ,	   0x1070000000ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_INT3_EN4_1"              ,	   0x1070000000cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_INT4_EN4_1"              ,	   0x1070000000cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_INT5_EN4_1"              ,	   0x1070000000cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_INT6_EN4_1"              ,	   0x1070000000ce8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_INT7_EN4_1"              ,	   0x1070000000cf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_INT8_EN4_1"              ,	   0x1070000000d08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_INT9_EN4_1"              ,	   0x1070000000d18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_INT0_EN4_1_W1C"          ,	   0x1070000002c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_INT1_EN4_1_W1C"          ,	   0x1070000002c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_INT2_EN4_1_W1C"          ,	   0x1070000002ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_INT3_EN4_1_W1C"          ,	   0x1070000002cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_INT4_EN4_1_W1C"          ,	   0x1070000002cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_INT5_EN4_1_W1C"          ,	   0x1070000002cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_INT6_EN4_1_W1C"          ,	   0x1070000002ce8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_INT7_EN4_1_W1C"          ,	   0x1070000002cf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_INT8_EN4_1_W1C"          ,	   0x1070000002d08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_INT9_EN4_1_W1C"          ,	   0x1070000002d18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_INT0_EN4_1_W1S"          ,	   0x1070000006c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU_INT1_EN4_1_W1S"          ,	   0x1070000006c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU_INT2_EN4_1_W1S"          ,	   0x1070000006ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU_INT3_EN4_1_W1S"          ,	   0x1070000006cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU_INT4_EN4_1_W1S"          ,	   0x1070000006cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU_INT5_EN4_1_W1S"          ,	   0x1070000006cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU_INT6_EN4_1_W1S"          ,	   0x1070000006ce8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU_INT7_EN4_1_W1S"          ,	   0x1070000006cf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU_INT8_EN4_1_W1S"          ,	   0x1070000006d08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU_INT9_EN4_1_W1S"          ,	   0x1070000006d18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT3_SUM0"               ,	   0x1070000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT4_SUM0"               ,	   0x1070000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT5_SUM0"               ,	   0x1070000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT6_SUM0"               ,	   0x1070000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT7_SUM0"               ,	   0x1070000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT8_SUM0"               ,	   0x1070000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT9_SUM0"               ,	   0x1070000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT10_SUM0"              ,	   0x1070000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT11_SUM0"              ,	   0x1070000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT12_SUM0"              ,	   0x1070000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT13_SUM0"              ,	   0x1070000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT14_SUM0"              ,	   0x1070000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT15_SUM0"              ,	   0x1070000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT16_SUM0"              ,	   0x1070000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT17_SUM0"              ,	   0x1070000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT18_SUM0"              ,	   0x1070000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT19_SUM0"              ,	   0x1070000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000c00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000c08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU_INT2_SUM4"               ,	   0x1070000000c10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU_INT3_SUM4"               ,	   0x1070000000c18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU_INT4_SUM4"               ,	   0x1070000000c20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU_INT5_SUM4"               ,	   0x1070000000c28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU_INT6_SUM4"               ,	   0x1070000000c30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU_INT7_SUM4"               ,	   0x1070000000c38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU_INT8_SUM4"               ,	   0x1070000000c40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU_INT9_SUM4"               ,	   0x1070000000c48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU_INT33_SUM0"              ,	   0x1070000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU_INT_DBG_SEL"             ,	   0x10700000007d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU_MBOX_CLR4"               ,	   0x10700000006a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU_MBOX_CLR5"               ,	   0x10700000006a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU_MBOX_CLR6"               ,	   0x10700000006b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU_MBOX_CLR7"               ,	   0x10700000006b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU_MBOX_CLR8"               ,	   0x10700000006c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU_MBOX_CLR9"               ,	   0x10700000006c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU_MBOX_SET3"               ,	   0x1070000000618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU_MBOX_SET4"               ,	   0x1070000000620ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU_MBOX_SET5"               ,	   0x1070000000628ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU_MBOX_SET6"               ,	   0x1070000000630ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU_MBOX_SET7"               ,	   0x1070000000638ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU_MBOX_SET8"               ,	   0x1070000000640ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU_MBOX_SET9"               ,	   0x1070000000648ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU_NMI"                     ,	   0x1070000000718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU_PCI_INTA"                ,	   0x1070000000750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU_PP_DBG"                  ,	   0x1070000000708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU_PP_POKE0"                ,	   0x1070000000580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_PP_POKE4"                ,	   0x10700000005a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_PP_POKE5"                ,	   0x10700000005a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_PP_POKE6"                ,	   0x10700000005b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_PP_POKE7"                ,	   0x10700000005b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_PP_POKE8"                ,	   0x10700000005c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_PP_POKE9"                ,	   0x10700000005c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU_QLM0"                    ,	   0x1070000000780ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU_QLM1"                    ,	   0x1070000000788ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU_QLM2"                    ,	   0x1070000000790ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU_QLM_JTGC"                ,	   0x1070000000768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU_QLM_JTGD"                ,	   0x1070000000770ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU_SOFT_PRST1"              ,	   0x1070000000758ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU_SOFT_PRST2"              ,	   0x10700000007d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU_SOFT_PRST3"              ,	   0x10700000007e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU_SOFT_RST"                ,	   0x1070000000740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU_SUM1_IO0_INT"            ,	   0x1070000008600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU_SUM1_IO1_INT"            ,	   0x1070000008608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU_SUM1_PP0_IP2"            ,	   0x1070000008000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU_SUM1_PP1_IP2"            ,	   0x1070000008008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU_SUM1_PP2_IP2"            ,	   0x1070000008010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU_SUM1_PP3_IP2"            ,	   0x1070000008018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU_SUM1_PP4_IP2"            ,	   0x1070000008020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU_SUM1_PP5_IP2"            ,	   0x1070000008028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU_SUM1_PP6_IP2"            ,	   0x1070000008030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU_SUM1_PP7_IP2"            ,	   0x1070000008038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU_SUM1_PP8_IP2"            ,	   0x1070000008040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU_SUM1_PP9_IP2"            ,	   0x1070000008048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU_SUM1_PP0_IP3"            ,	   0x1070000008200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU_SUM1_PP1_IP3"            ,	   0x1070000008208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU_SUM1_PP2_IP3"            ,	   0x1070000008210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU_SUM1_PP3_IP3"            ,	   0x1070000008218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU_SUM1_PP4_IP3"            ,	   0x1070000008220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU_SUM1_PP5_IP3"            ,	   0x1070000008228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU_SUM1_PP6_IP3"            ,	   0x1070000008230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU_SUM1_PP7_IP3"            ,	   0x1070000008238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU_SUM1_PP8_IP3"            ,	   0x1070000008240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU_SUM1_PP9_IP3"            ,	   0x1070000008248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU_SUM1_PP0_IP4"            ,	   0x1070000008400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU_SUM1_PP1_IP4"            ,	   0x1070000008408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU_SUM1_PP2_IP4"            ,	   0x1070000008410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU_SUM1_PP3_IP4"            ,	   0x1070000008418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU_SUM1_PP4_IP4"            ,	   0x1070000008420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU_SUM1_PP5_IP4"            ,	   0x1070000008428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU_SUM1_PP6_IP4"            ,	   0x1070000008430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU_SUM1_PP7_IP4"            ,	   0x1070000008438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU_SUM1_PP8_IP4"            ,	   0x1070000008440ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU_SUM1_PP9_IP4"            ,	   0x1070000008448ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU_SUM2_IO0_INT"            ,	   0x1070000008e00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU_SUM2_IO1_INT"            ,	   0x1070000008e08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU_SUM2_PP0_IP2"            ,	   0x1070000008800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU_SUM2_PP1_IP2"            ,	   0x1070000008808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU_SUM2_PP2_IP2"            ,	   0x1070000008810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU_SUM2_PP3_IP2"            ,	   0x1070000008818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU_SUM2_PP4_IP2"            ,	   0x1070000008820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU_SUM2_PP5_IP2"            ,	   0x1070000008828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU_SUM2_PP6_IP2"            ,	   0x1070000008830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU_SUM2_PP7_IP2"            ,	   0x1070000008838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU_SUM2_PP8_IP2"            ,	   0x1070000008840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU_SUM2_PP9_IP2"            ,	   0x1070000008848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU_SUM2_PP0_IP3"            ,	   0x1070000008a00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_SUM2_PP1_IP3"            ,	   0x1070000008a08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_SUM2_PP2_IP3"            ,	   0x1070000008a10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_SUM2_PP3_IP3"            ,	   0x1070000008a18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_SUM2_PP4_IP3"            ,	   0x1070000008a20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_SUM2_PP5_IP3"            ,	   0x1070000008a28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_SUM2_PP6_IP3"            ,	   0x1070000008a30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_SUM2_PP7_IP3"            ,	   0x1070000008a38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_SUM2_PP8_IP3"            ,	   0x1070000008a40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_SUM2_PP9_IP3"            ,	   0x1070000008a48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU_SUM2_PP0_IP4"            ,	   0x1070000008c00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU_SUM2_PP1_IP4"            ,	   0x1070000008c08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU_SUM2_PP2_IP4"            ,	   0x1070000008c10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU_SUM2_PP3_IP4"            ,	   0x1070000008c18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU_SUM2_PP4_IP4"            ,	   0x1070000008c20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU_SUM2_PP5_IP4"            ,	   0x1070000008c28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU_SUM2_PP6_IP4"            ,	   0x1070000008c30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU_SUM2_PP7_IP4"            ,	   0x1070000008c38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU_SUM2_PP8_IP4"            ,	   0x1070000008c40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU_SUM2_PP9_IP4"            ,	   0x1070000008c48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU_TIM0"                    ,	   0x1070000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU_TIM1"                    ,	   0x1070000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU_TIM4"                    ,	   0x10700000004a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU_TIM5"                    ,	   0x10700000004a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU_TIM6"                    ,	   0x10700000004b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU_TIM7"                    ,	   0x10700000004b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU_TIM8"                    ,	   0x10700000004c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU_TIM9"                    ,	   0x10700000004c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU_TIM_MULTI_CAST"          ,	   0x107000000c200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU_WDOG2"                   ,	   0x1070000000510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU_WDOG3"                   ,	   0x1070000000518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU_WDOG4"                   ,	   0x1070000000520ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU_WDOG5"                   ,	   0x1070000000528ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU_WDOG6"                   ,	   0x1070000000530ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU_WDOG7"                   ,	   0x1070000000538ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU_WDOG8"                   ,	   0x1070000000540ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU_WDOG9"                   ,	   0x1070000000548ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"DFA_BIST0"                   ,	   0x11800370007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"DFA_BIST1"                   ,	   0x11800370007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"DFA_CONFIG"                  ,	   0x1180037000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"DFA_CONTROL"                 ,	   0x1180037000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"DFA_DBELL"                   ,	   0x1370000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"DFA_DEBUG0"                  ,	   0x1180037000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"DFA_DEBUG1"                  ,	   0x1180037000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"DFA_DEBUG2"                  ,	   0x1180037000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"DFA_DEBUG3"                  ,	   0x1180037000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"DFA_DIFCTL"                  ,	   0x1370600000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"DFA_DIFRDPTR"                ,	   0x1370200000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"DFA_DTCFADR"                 ,	   0x1180037000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"DFA_ERROR"                   ,	   0x1180037000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"DFA_INTMSK"                  ,	   0x1180037000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"DFA_MEMHIDAT"                ,	   0x1370700000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"DFA_PFC0_CNT"                ,	   0x1180037000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"DFA_PFC0_CTL"                ,	   0x1180037000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"DFA_PFC1_CNT"                ,	   0x11800370000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"DFA_PFC1_CTL"                ,	   0x1180037000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"DFA_PFC2_CNT"                ,	   0x11800370000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"DFA_PFC2_CTL"                ,	   0x11800370000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"DFA_PFC3_CNT"                ,	   0x11800370000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"DFA_PFC3_CTL"                ,	   0x11800370000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"DFA_PFC_GCTL"                ,	   0x1180037000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"DFM_CHAR_CTL"                ,	   0x11800d4000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"DFM_CHAR_MASK0"              ,	   0x11800d4000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"DFM_CHAR_MASK2"              ,	   0x11800d4000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"DFM_CHAR_MASK4"              ,	   0x11800d4000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"DFM_COMP_CTL2"               ,	   0x11800d40001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"DFM_CONFIG"                  ,	   0x11800d4000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"DFM_CONTROL"                 ,	   0x11800d4000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"DFM_DLL_CTL2"                ,	   0x11800d40001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"DFM_DLL_CTL3"                ,	   0x11800d4000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"DFM_FCLK_CNT"                ,	   0x11800d40001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"DFM_FNT_BIST"                ,	   0x11800d40007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"DFM_FNT_CTL"                 ,	   0x11800d4000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"DFM_FNT_IENA"                ,	   0x11800d4000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"DFM_FNT_SCLK"                ,	   0x11800d4000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"DFM_FNT_STAT"                ,	   0x11800d4000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"DFM_IFB_CNT"                 ,	   0x11800d40001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"DFM_MODEREG_PARAMS0"         ,	   0x11800d40001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"DFM_MODEREG_PARAMS1"         ,	   0x11800d4000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"DFM_OPS_CNT"                 ,	   0x11800d40001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"DFM_PHY_CTL"                 ,	   0x11800d4000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"DFM_RESET_CTL"               ,	   0x11800d4000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"DFM_RLEVEL_CTL"              ,	   0x11800d40002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"DFM_RLEVEL_DBG"              ,	   0x11800d40002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"DFM_RLEVEL_RANK0"            ,	   0x11800d4000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"DFM_RLEVEL_RANK1"            ,	   0x11800d4000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"DFM_RODT_MASK"               ,	   0x11800d4000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"DFM_SLOT_CTL0"               ,	   0x11800d40001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"DFM_SLOT_CTL1"               ,	   0x11800d4000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"DFM_TIMING_PARAMS0"          ,	   0x11800d4000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"DFM_TIMING_PARAMS1"          ,	   0x11800d40001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"DFM_WLEVEL_CTL"              ,	   0x11800d4000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"DFM_WLEVEL_DBG"              ,	   0x11800d4000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"DFM_WLEVEL_RANK0"            ,	   0x11800d40002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"DFM_WLEVEL_RANK1"            ,	   0x11800d40002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"DFM_WODT_MASK"               ,	   0x11800d40001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
+	{"DPI_BIST_STATUS"             ,	   0x1df0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"DPI_CTL"                     ,	   0x1df0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	193},
+	{"DPI_DMA0_COUNTS"             ,	   0x1df0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"DPI_DMA1_COUNTS"             ,	   0x1df0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"DPI_DMA2_COUNTS"             ,	   0x1df0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"DPI_DMA3_COUNTS"             ,	   0x1df0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"DPI_DMA4_COUNTS"             ,	   0x1df0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"DPI_DMA5_COUNTS"             ,	   0x1df0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"DPI_DMA6_COUNTS"             ,	   0x1df0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"DPI_DMA7_COUNTS"             ,	   0x1df0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"DPI_DMA0_DBELL"              ,	   0x1df0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"DPI_DMA1_DBELL"              ,	   0x1df0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"DPI_DMA2_DBELL"              ,	   0x1df0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"DPI_DMA3_DBELL"              ,	   0x1df0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"DPI_DMA4_DBELL"              ,	   0x1df0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"DPI_DMA5_DBELL"              ,	   0x1df0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"DPI_DMA6_DBELL"              ,	   0x1df0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"DPI_DMA7_DBELL"              ,	   0x1df0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"DPI_DMA0_ERR_RSP_STATUS"     ,	   0x1df0000000a80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"DPI_DMA1_ERR_RSP_STATUS"     ,	   0x1df0000000a88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"DPI_DMA2_ERR_RSP_STATUS"     ,	   0x1df0000000a90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"DPI_DMA3_ERR_RSP_STATUS"     ,	   0x1df0000000a98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"DPI_DMA4_ERR_RSP_STATUS"     ,	   0x1df0000000aa0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"DPI_DMA5_ERR_RSP_STATUS"     ,	   0x1df0000000aa8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"DPI_DMA6_ERR_RSP_STATUS"     ,	   0x1df0000000ab0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"DPI_DMA7_ERR_RSP_STATUS"     ,	   0x1df0000000ab8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"DPI_DMA0_IBUFF_SADDR"        ,	   0x1df0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"DPI_DMA1_IBUFF_SADDR"        ,	   0x1df0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"DPI_DMA2_IBUFF_SADDR"        ,	   0x1df0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"DPI_DMA3_IBUFF_SADDR"        ,	   0x1df0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"DPI_DMA4_IBUFF_SADDR"        ,	   0x1df00000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"DPI_DMA5_IBUFF_SADDR"        ,	   0x1df00000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"DPI_DMA6_IBUFF_SADDR"        ,	   0x1df00000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"DPI_DMA7_IBUFF_SADDR"        ,	   0x1df00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"DPI_DMA0_IFLIGHT"            ,	   0x1df0000000a00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"DPI_DMA1_IFLIGHT"            ,	   0x1df0000000a08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"DPI_DMA2_IFLIGHT"            ,	   0x1df0000000a10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"DPI_DMA3_IFLIGHT"            ,	   0x1df0000000a18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"DPI_DMA4_IFLIGHT"            ,	   0x1df0000000a20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"DPI_DMA5_IFLIGHT"            ,	   0x1df0000000a28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"DPI_DMA6_IFLIGHT"            ,	   0x1df0000000a30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"DPI_DMA7_IFLIGHT"            ,	   0x1df0000000a38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"DPI_DMA0_NADDR"              ,	   0x1df0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"DPI_DMA1_NADDR"              ,	   0x1df0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"DPI_DMA2_NADDR"              ,	   0x1df0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"DPI_DMA3_NADDR"              ,	   0x1df0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"DPI_DMA4_NADDR"              ,	   0x1df00000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"DPI_DMA5_NADDR"              ,	   0x1df00000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"DPI_DMA6_NADDR"              ,	   0x1df00000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"DPI_DMA7_NADDR"              ,	   0x1df00000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"DPI_DMA0_REQBNK0"            ,	   0x1df0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"DPI_DMA1_REQBNK0"            ,	   0x1df0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"DPI_DMA2_REQBNK0"            ,	   0x1df0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"DPI_DMA3_REQBNK0"            ,	   0x1df0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"DPI_DMA4_REQBNK0"            ,	   0x1df0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"DPI_DMA5_REQBNK0"            ,	   0x1df0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"DPI_DMA6_REQBNK0"            ,	   0x1df0000000430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"DPI_DMA7_REQBNK0"            ,	   0x1df0000000438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"DPI_DMA0_REQBNK1"            ,	   0x1df0000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"DPI_DMA1_REQBNK1"            ,	   0x1df0000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"DPI_DMA2_REQBNK1"            ,	   0x1df0000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"DPI_DMA3_REQBNK1"            ,	   0x1df0000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"DPI_DMA4_REQBNK1"            ,	   0x1df00000004a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"DPI_DMA5_REQBNK1"            ,	   0x1df00000004a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"DPI_DMA6_REQBNK1"            ,	   0x1df00000004b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"DPI_DMA7_REQBNK1"            ,	   0x1df00000004b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"DPI_DMA_CONTROL"             ,	   0x1df0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"DPI_DMA_ENG0_EN"             ,	   0x1df0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"DPI_DMA_ENG1_EN"             ,	   0x1df0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"DPI_DMA_ENG2_EN"             ,	   0x1df0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"DPI_DMA_ENG3_EN"             ,	   0x1df0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"DPI_DMA_ENG4_EN"             ,	   0x1df00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"DPI_DMA_ENG5_EN"             ,	   0x1df00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"DPI_ENG0_BUF"                ,	   0x1df0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"DPI_ENG1_BUF"                ,	   0x1df0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"DPI_ENG2_BUF"                ,	   0x1df0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"DPI_ENG3_BUF"                ,	   0x1df0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"DPI_ENG4_BUF"                ,	   0x1df00000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"DPI_ENG5_BUF"                ,	   0x1df00000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"DPI_INFO_REG"                ,	   0x1df0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"DPI_INT_EN"                  ,	   0x1df0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"DPI_INT_REG"                 ,	   0x1df0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"DPI_NCB0_CFG"                ,	   0x1df0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"DPI_PINT_INFO"               ,	   0x1df0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"DPI_PKT_ERR_RSP"             ,	   0x1df0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"DPI_REQ_ERR_RSP"             ,	   0x1df0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"DPI_REQ_ERR_RSP_EN"          ,	   0x1df0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"DPI_REQ_ERR_RST"             ,	   0x1df0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"DPI_REQ_ERR_RST_EN"          ,	   0x1df0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"DPI_REQ_ERR_SKIP_COMP"       ,	   0x1df0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"DPI_REQ_GBL_EN"              ,	   0x1df0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"DPI_SLI_PRT0_CFG"            ,	   0x1df0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"DPI_SLI_PRT1_CFG"            ,	   0x1df0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"DPI_SLI_PRT2_CFG"            ,	   0x1df0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"DPI_SLI_PRT3_CFG"            ,	   0x1df0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"DPI_SLI_PRT0_ERR"            ,	   0x1df0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"DPI_SLI_PRT1_ERR"            ,	   0x1df0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"DPI_SLI_PRT2_ERR"            ,	   0x1df0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"DPI_SLI_PRT3_ERR"            ,	   0x1df0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"DPI_SLI_PRT0_ERR_INFO"       ,	   0x1df0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"DPI_SLI_PRT1_ERR_INFO"       ,	   0x1df0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"DPI_SLI_PRT2_ERR_INFO"       ,	   0x1df0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"DPI_SLI_PRT3_ERR_INFO"       ,	   0x1df0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"FPA_ADDR_RANGE_ERROR"        ,	   0x1180028000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"FPA_FPF3_MARKS"              ,	   0x1180028000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"FPA_FPF4_MARKS"              ,	   0x1180028000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"FPA_FPF5_MARKS"              ,	   0x1180028000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"FPA_FPF6_MARKS"              ,	   0x1180028000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"FPA_FPF7_MARKS"              ,	   0x1180028000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"FPA_FPF1_SIZE"               ,	   0x1180028000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"FPA_FPF2_SIZE"               ,	   0x1180028000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"FPA_FPF3_SIZE"               ,	   0x1180028000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"FPA_FPF4_SIZE"               ,	   0x1180028000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"FPA_FPF5_SIZE"               ,	   0x1180028000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"FPA_FPF6_SIZE"               ,	   0x1180028000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"FPA_FPF7_SIZE"               ,	   0x1180028000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"FPA_FPF0_MARKS"              ,	   0x1180028000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"FPA_FPF0_SIZE"               ,	   0x1180028000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"FPA_PACKET_THRESHOLD"        ,	   0x1180028000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"FPA_POOL0_END_ADDR"          ,	   0x1180028000358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"FPA_POOL1_END_ADDR"          ,	   0x1180028000360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"FPA_POOL2_END_ADDR"          ,	   0x1180028000368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"FPA_POOL3_END_ADDR"          ,	   0x1180028000370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"FPA_POOL4_END_ADDR"          ,	   0x1180028000378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"FPA_POOL5_END_ADDR"          ,	   0x1180028000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"FPA_POOL6_END_ADDR"          ,	   0x1180028000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"FPA_POOL7_END_ADDR"          ,	   0x1180028000390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"FPA_POOL0_START_ADDR"        ,	   0x1180028000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"FPA_POOL1_START_ADDR"        ,	   0x1180028000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"FPA_POOL2_START_ADDR"        ,	   0x1180028000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"FPA_POOL3_START_ADDR"        ,	   0x1180028000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"FPA_POOL4_START_ADDR"        ,	   0x1180028000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"FPA_POOL5_START_ADDR"        ,	   0x1180028000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"FPA_POOL6_START_ADDR"        ,	   0x1180028000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"FPA_POOL7_START_ADDR"        ,	   0x1180028000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"FPA_POOL0_THRESHOLD"         ,	   0x1180028000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"FPA_POOL1_THRESHOLD"         ,	   0x1180028000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"FPA_POOL2_THRESHOLD"         ,	   0x1180028000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"FPA_POOL3_THRESHOLD"         ,	   0x1180028000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"FPA_POOL4_THRESHOLD"         ,	   0x1180028000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"FPA_POOL5_THRESHOLD"         ,	   0x1180028000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"FPA_POOL6_THRESHOLD"         ,	   0x1180028000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"FPA_POOL7_THRESHOLD"         ,	   0x1180028000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"FPA_QUE5_PAGE_INDEX"         ,	   0x1180028000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"FPA_QUE6_PAGE_INDEX"         ,	   0x1180028000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"FPA_WQE_THRESHOLD"           ,	   0x1180028000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"GMX1_BAD_REG"                ,	   0x1180010000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"GMX1_BIST"                   ,	   0x1180010000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"GMX0_CLK_EN"                 ,	   0x11800080007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"GMX1_CLK_EN"                 ,	   0x11800100007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"GMX0_HG2_CONTROL"            ,	   0x1180008000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"GMX1_HG2_CONTROL"            ,	   0x1180010000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"GMX0_INF_MODE"               ,	   0x11800080007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"GMX1_INF_MODE"               ,	   0x11800100007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"GMX1_NXA_ADR"                ,	   0x1180010000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"GMX0_PRT000_CBFC_CTL"        ,	   0x1180008000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"GMX1_PRT000_CBFC_CTL"        ,	   0x1180010000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"GMX0_PRT002_CFG"             ,	   0x1180008001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"GMX0_PRT003_CFG"             ,	   0x1180008001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"GMX1_PRT000_CFG"             ,	   0x1180010000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"GMX1_PRT001_CFG"             ,	   0x1180010000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"GMX1_PRT002_CFG"             ,	   0x1180010001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"GMX1_PRT003_CFG"             ,	   0x1180010001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"GMX0_RX000_ADR_CAM0"         ,	   0x1180008000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"GMX0_RX001_ADR_CAM0"         ,	   0x1180008000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"GMX0_RX002_ADR_CAM0"         ,	   0x1180008001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"GMX0_RX003_ADR_CAM0"         ,	   0x1180008001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"GMX1_RX000_ADR_CAM0"         ,	   0x1180010000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"GMX1_RX001_ADR_CAM0"         ,	   0x1180010000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"GMX1_RX002_ADR_CAM0"         ,	   0x1180010001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"GMX1_RX003_ADR_CAM0"         ,	   0x1180010001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"GMX0_RX000_ADR_CAM1"         ,	   0x1180008000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"GMX0_RX001_ADR_CAM1"         ,	   0x1180008000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"GMX0_RX002_ADR_CAM1"         ,	   0x1180008001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"GMX0_RX003_ADR_CAM1"         ,	   0x1180008001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"GMX1_RX000_ADR_CAM1"         ,	   0x1180010000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"GMX1_RX001_ADR_CAM1"         ,	   0x1180010000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"GMX1_RX002_ADR_CAM1"         ,	   0x1180010001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"GMX1_RX003_ADR_CAM1"         ,	   0x1180010001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"GMX0_RX000_ADR_CAM2"         ,	   0x1180008000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"GMX0_RX001_ADR_CAM2"         ,	   0x1180008000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"GMX0_RX002_ADR_CAM2"         ,	   0x1180008001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"GMX0_RX003_ADR_CAM2"         ,	   0x1180008001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"GMX1_RX000_ADR_CAM2"         ,	   0x1180010000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"GMX1_RX001_ADR_CAM2"         ,	   0x1180010000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"GMX1_RX002_ADR_CAM2"         ,	   0x1180010001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"GMX1_RX003_ADR_CAM2"         ,	   0x1180010001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"GMX0_RX003_ADR_CAM3"         ,	   0x1180008001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"GMX1_RX000_ADR_CAM3"         ,	   0x1180010000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"GMX1_RX001_ADR_CAM3"         ,	   0x1180010000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"GMX1_RX002_ADR_CAM3"         ,	   0x1180010001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"GMX1_RX003_ADR_CAM3"         ,	   0x1180010001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX0_RX000_ADR_CAM_ALL_EN"   ,	   0x1180008000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"GMX0_RX001_ADR_CAM_ALL_EN"   ,	   0x1180008000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"GMX0_RX002_ADR_CAM_ALL_EN"   ,	   0x1180008001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"GMX0_RX003_ADR_CAM_ALL_EN"   ,	   0x1180008001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"GMX1_RX000_ADR_CAM_ALL_EN"   ,	   0x1180010000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"GMX1_RX001_ADR_CAM_ALL_EN"   ,	   0x1180010000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"GMX1_RX002_ADR_CAM_ALL_EN"   ,	   0x1180010001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"GMX1_RX003_ADR_CAM_ALL_EN"   ,	   0x1180010001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"GMX0_RX003_ADR_CAM_EN"       ,	   0x1180008001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"GMX1_RX000_ADR_CAM_EN"       ,	   0x1180010000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"GMX1_RX001_ADR_CAM_EN"       ,	   0x1180010000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"GMX1_RX002_ADR_CAM_EN"       ,	   0x1180010001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"GMX1_RX003_ADR_CAM_EN"       ,	   0x1180010001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"GMX0_RX000_ADR_CTL"          ,	   0x1180008000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"GMX0_RX001_ADR_CTL"          ,	   0x1180008000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"GMX0_RX002_ADR_CTL"          ,	   0x1180008001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"GMX0_RX003_ADR_CTL"          ,	   0x1180008001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"GMX1_RX000_ADR_CTL"          ,	   0x1180010000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"GMX1_RX001_ADR_CTL"          ,	   0x1180010000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"GMX1_RX002_ADR_CTL"          ,	   0x1180010001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"GMX1_RX003_ADR_CTL"          ,	   0x1180010001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"GMX0_RX000_DECISION"         ,	   0x1180008000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX0_RX001_DECISION"         ,	   0x1180008000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX0_RX002_DECISION"         ,	   0x1180008001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX0_RX003_DECISION"         ,	   0x1180008001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX1_RX000_DECISION"         ,	   0x1180010000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX1_RX001_DECISION"         ,	   0x1180010000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX1_RX002_DECISION"         ,	   0x1180010001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX1_RX003_DECISION"         ,	   0x1180010001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX0_RX000_FRM_CHK"          ,	   0x1180008000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX0_RX001_FRM_CHK"          ,	   0x1180008000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX0_RX002_FRM_CHK"          ,	   0x1180008001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX0_RX003_FRM_CHK"          ,	   0x1180008001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX1_RX000_FRM_CHK"          ,	   0x1180010000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX1_RX001_FRM_CHK"          ,	   0x1180010000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX1_RX002_FRM_CHK"          ,	   0x1180010001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX1_RX003_FRM_CHK"          ,	   0x1180010001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX0_RX000_FRM_CTL"          ,	   0x1180008000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX0_RX001_FRM_CTL"          ,	   0x1180008000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX0_RX002_FRM_CTL"          ,	   0x1180008001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX0_RX003_FRM_CTL"          ,	   0x1180008001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX1_RX000_FRM_CTL"          ,	   0x1180010000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX1_RX001_FRM_CTL"          ,	   0x1180010000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX1_RX002_FRM_CTL"          ,	   0x1180010001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX1_RX003_FRM_CTL"          ,	   0x1180010001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX0_RX000_IFG"              ,	   0x1180008000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX0_RX001_IFG"              ,	   0x1180008000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX0_RX002_IFG"              ,	   0x1180008001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX0_RX003_IFG"              ,	   0x1180008001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX1_RX000_IFG"              ,	   0x1180010000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX1_RX001_IFG"              ,	   0x1180010000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX1_RX002_IFG"              ,	   0x1180010001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX1_RX003_IFG"              ,	   0x1180010001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX0_RX000_INT_EN"           ,	   0x1180008000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX0_RX001_INT_EN"           ,	   0x1180008000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX0_RX002_INT_EN"           ,	   0x1180008001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX0_RX003_INT_EN"           ,	   0x1180008001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX1_RX000_INT_EN"           ,	   0x1180010000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX1_RX001_INT_EN"           ,	   0x1180010000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX1_RX002_INT_EN"           ,	   0x1180010001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX1_RX003_INT_EN"           ,	   0x1180010001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX0_RX000_INT_REG"          ,	   0x1180008000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX0_RX001_INT_REG"          ,	   0x1180008000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX0_RX002_INT_REG"          ,	   0x1180008001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX0_RX003_INT_REG"          ,	   0x1180008001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX1_RX000_INT_REG"          ,	   0x1180010000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX1_RX001_INT_REG"          ,	   0x1180010000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX1_RX002_INT_REG"          ,	   0x1180010001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX1_RX003_INT_REG"          ,	   0x1180010001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX0_RX000_JABBER"           ,	   0x1180008000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX0_RX001_JABBER"           ,	   0x1180008000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX0_RX002_JABBER"           ,	   0x1180008001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX0_RX003_JABBER"           ,	   0x1180008001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX1_RX000_JABBER"           ,	   0x1180010000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX1_RX001_JABBER"           ,	   0x1180010000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX1_RX002_JABBER"           ,	   0x1180010001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX1_RX003_JABBER"           ,	   0x1180010001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX0_RX000_PAUSE_DROP_TIME"  ,	   0x1180008000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX0_RX001_PAUSE_DROP_TIME"  ,	   0x1180008000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX0_RX002_PAUSE_DROP_TIME"  ,	   0x1180008001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX0_RX003_PAUSE_DROP_TIME"  ,	   0x1180008001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX1_RX000_PAUSE_DROP_TIME"  ,	   0x1180010000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX1_RX001_PAUSE_DROP_TIME"  ,	   0x1180010000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX1_RX002_PAUSE_DROP_TIME"  ,	   0x1180010001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX1_RX003_PAUSE_DROP_TIME"  ,	   0x1180010001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX0_RX000_STATS_CTL"        ,	   0x1180008000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX0_RX001_STATS_CTL"        ,	   0x1180008000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX0_RX002_STATS_CTL"        ,	   0x1180008001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX0_RX003_STATS_CTL"        ,	   0x1180008001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX1_RX000_STATS_CTL"        ,	   0x1180010000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX1_RX001_STATS_CTL"        ,	   0x1180010000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX1_RX002_STATS_CTL"        ,	   0x1180010001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX1_RX003_STATS_CTL"        ,	   0x1180010001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX0_RX000_STATS_OCTS"       ,	   0x1180008000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX0_RX001_STATS_OCTS"       ,	   0x1180008000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX0_RX002_STATS_OCTS"       ,	   0x1180008001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX0_RX003_STATS_OCTS"       ,	   0x1180008001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX1_RX000_STATS_OCTS"       ,	   0x1180010000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX1_RX001_STATS_OCTS"       ,	   0x1180010000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX1_RX002_STATS_OCTS"       ,	   0x1180010001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX1_RX003_STATS_OCTS"       ,	   0x1180010001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX0_RX003_STATS_OCTS_CTL"   ,	   0x1180008001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX1_RX000_STATS_OCTS_CTL"   ,	   0x1180010000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX1_RX001_STATS_OCTS_CTL"   ,	   0x1180010000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX1_RX002_STATS_OCTS_CTL"   ,	   0x1180010001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX1_RX003_STATS_OCTS_CTL"   ,	   0x1180010001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX0_RX003_STATS_PKTS"       ,	   0x1180008001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX1_RX000_STATS_PKTS"       ,	   0x1180010000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX1_RX001_STATS_PKTS"       ,	   0x1180010000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX1_RX002_STATS_PKTS"       ,	   0x1180010001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX1_RX003_STATS_PKTS"       ,	   0x1180010001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX0_RX003_STATS_PKTS_CTL"   ,	   0x1180008001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX1_RX000_STATS_PKTS_CTL"   ,	   0x1180010000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX1_RX001_STATS_PKTS_CTL"   ,	   0x1180010000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX1_RX002_STATS_PKTS_CTL"   ,	   0x1180010001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX1_RX003_STATS_PKTS_CTL"   ,	   0x1180010001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX0_RX003_UDD_SKP"          ,	   0x1180008001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX1_RX000_UDD_SKP"          ,	   0x1180010000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX1_RX001_UDD_SKP"          ,	   0x1180010000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX1_RX002_UDD_SKP"          ,	   0x1180010001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX1_RX003_UDD_SKP"          ,	   0x1180010001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX0_RX_BP_DROP000"          ,	   0x1180008000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX0_RX_BP_DROP001"          ,	   0x1180008000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX0_RX_BP_DROP002"          ,	   0x1180008000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX0_RX_BP_DROP003"          ,	   0x1180008000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX1_RX_BP_DROP000"          ,	   0x1180010000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX1_RX_BP_DROP001"          ,	   0x1180010000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX1_RX_BP_DROP002"          ,	   0x1180010000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX1_RX_BP_DROP003"          ,	   0x1180010000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX0_RX_BP_OFF000"           ,	   0x1180008000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX0_RX_BP_OFF001"           ,	   0x1180008000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX0_RX_BP_OFF002"           ,	   0x1180008000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX0_RX_BP_OFF003"           ,	   0x1180008000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX1_RX_BP_OFF000"           ,	   0x1180010000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX1_RX_BP_OFF001"           ,	   0x1180010000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX1_RX_BP_OFF002"           ,	   0x1180010000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX1_RX_BP_OFF003"           ,	   0x1180010000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"GMX0_RX_BP_ON003"            ,	   0x1180008000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"GMX1_RX_BP_ON000"            ,	   0x1180010000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"GMX1_RX_BP_ON001"            ,	   0x1180010000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"GMX1_RX_BP_ON002"            ,	   0x1180010000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"GMX1_RX_BP_ON003"            ,	   0x1180010000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"GMX0_RX_HG2_STATUS"          ,	   0x1180008000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"GMX1_RX_HG2_STATUS"          ,	   0x1180010000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"GMX1_RX_PRT_INFO"            ,	   0x11800100004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"GMX1_RX_PRTS"                ,	   0x1180010000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"GMX0_RX_XAUI_BAD_COL"        ,	   0x1180008000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"GMX1_RX_XAUI_BAD_COL"        ,	   0x1180010000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"GMX0_RX_XAUI_CTL"            ,	   0x1180008000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"GMX1_RX_XAUI_CTL"            ,	   0x1180010000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"GMX0_SMAC001"                ,	   0x1180008000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"GMX0_SMAC003"                ,	   0x1180008001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"GMX1_SMAC000"                ,	   0x1180010000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"GMX1_SMAC001"                ,	   0x1180010000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"GMX1_SMAC002"                ,	   0x1180010001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"GMX1_SMAC003"                ,	   0x1180010001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"GMX0_SOFT_BIST"              ,	   0x11800080007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"GMX1_SOFT_BIST"              ,	   0x11800100007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"GMX1_STAT_BP"                ,	   0x1180010000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"GMX0_TB_REG"                 ,	   0x11800080007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"GMX1_TB_REG"                 ,	   0x11800100007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"GMX1_TX000_APPEND"           ,	   0x1180010000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"GMX1_TX001_APPEND"           ,	   0x1180010000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"GMX1_TX002_APPEND"           ,	   0x1180010001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"GMX1_TX003_APPEND"           ,	   0x1180010001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"GMX1_TX000_BURST"            ,	   0x1180010000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"GMX1_TX001_BURST"            ,	   0x1180010000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"GMX1_TX002_BURST"            ,	   0x1180010001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"GMX1_TX003_BURST"            ,	   0x1180010001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"GMX0_TX000_CBFC_XOFF"        ,	   0x11800080005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"GMX1_TX000_CBFC_XOFF"        ,	   0x11800100005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"GMX0_TX000_CBFC_XON"         ,	   0x11800080005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
+	{"GMX1_TX000_CBFC_XON"         ,	   0x11800100005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
+	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"GMX1_TX000_CTL"              ,	   0x1180010000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"GMX1_TX001_CTL"              ,	   0x1180010000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"GMX1_TX002_CTL"              ,	   0x1180010001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"GMX1_TX003_CTL"              ,	   0x1180010001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"GMX1_TX000_MIN_PKT"          ,	   0x1180010000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"GMX1_TX002_MIN_PKT"          ,	   0x1180010001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"GMX1_TX000_PAUSE_PKT_INTERVAL",	   0x1180010000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"GMX1_TX002_PAUSE_PKT_INTERVAL",	   0x1180010001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"GMX1_TX000_PAUSE_PKT_TIME"   ,	   0x1180010000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"GMX1_TX002_PAUSE_PKT_TIME"   ,	   0x1180010001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"GMX1_TX000_PAUSE_TOGO"       ,	   0x1180010000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"GMX1_TX002_PAUSE_TOGO"       ,	   0x1180010001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"GMX1_TX000_PAUSE_ZERO"       ,	   0x1180010000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"GMX1_TX002_PAUSE_ZERO"       ,	   0x1180010001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"GMX0_TX000_SGMII_CTL"        ,	   0x1180008000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"GMX0_TX002_SGMII_CTL"        ,	   0x1180008001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"GMX0_TX003_SGMII_CTL"        ,	   0x1180008001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"GMX1_TX000_SGMII_CTL"        ,	   0x1180010000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"GMX1_TX001_SGMII_CTL"        ,	   0x1180010000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"GMX1_TX002_SGMII_CTL"        ,	   0x1180010001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"GMX1_TX003_SGMII_CTL"        ,	   0x1180010001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"GMX1_TX000_SLOT"             ,	   0x1180010000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"GMX1_TX001_SLOT"             ,	   0x1180010000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"GMX1_TX002_SLOT"             ,	   0x1180010001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"GMX1_TX003_SLOT"             ,	   0x1180010001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"GMX1_TX000_SOFT_PAUSE"       ,	   0x1180010000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"GMX1_TX002_SOFT_PAUSE"       ,	   0x1180010001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"GMX1_TX000_STAT0"            ,	   0x1180010000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"GMX1_TX001_STAT0"            ,	   0x1180010000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"GMX1_TX002_STAT0"            ,	   0x1180010001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"GMX1_TX003_STAT0"            ,	   0x1180010001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"GMX1_TX000_STAT1"            ,	   0x1180010000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"GMX1_TX001_STAT1"            ,	   0x1180010000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"GMX1_TX002_STAT1"            ,	   0x1180010001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"GMX1_TX003_STAT1"            ,	   0x1180010001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"GMX1_TX000_STAT2"            ,	   0x1180010000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"GMX1_TX001_STAT2"            ,	   0x1180010000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"GMX1_TX002_STAT2"            ,	   0x1180010001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"GMX1_TX003_STAT2"            ,	   0x1180010001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"GMX1_TX000_STAT3"            ,	   0x1180010000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"GMX1_TX001_STAT3"            ,	   0x1180010000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"GMX1_TX002_STAT3"            ,	   0x1180010001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"GMX1_TX003_STAT3"            ,	   0x1180010001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"GMX1_TX000_STAT4"            ,	   0x11800100002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"GMX1_TX001_STAT4"            ,	   0x1180010000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"GMX1_TX002_STAT4"            ,	   0x11800100012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"GMX1_TX003_STAT4"            ,	   0x1180010001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"GMX1_TX000_STAT5"            ,	   0x11800100002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"GMX1_TX001_STAT5"            ,	   0x1180010000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"GMX1_TX002_STAT5"            ,	   0x11800100012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"GMX1_TX003_STAT5"            ,	   0x1180010001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"GMX1_TX000_STAT6"            ,	   0x11800100002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"GMX1_TX001_STAT6"            ,	   0x1180010000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"GMX1_TX002_STAT6"            ,	   0x11800100012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"GMX1_TX003_STAT6"            ,	   0x1180010001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"GMX1_TX000_STAT7"            ,	   0x11800100002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"GMX1_TX001_STAT7"            ,	   0x1180010000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"GMX1_TX002_STAT7"            ,	   0x11800100012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"GMX1_TX003_STAT7"            ,	   0x1180010001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"GMX1_TX000_STAT8"            ,	   0x11800100002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"GMX1_TX001_STAT8"            ,	   0x1180010000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"GMX1_TX002_STAT8"            ,	   0x11800100012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"GMX1_TX003_STAT8"            ,	   0x1180010001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"GMX1_TX000_STAT9"            ,	   0x11800100002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"GMX1_TX001_STAT9"            ,	   0x1180010000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"GMX1_TX002_STAT9"            ,	   0x11800100012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"GMX1_TX003_STAT9"            ,	   0x1180010001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"GMX1_TX000_STATS_CTL"        ,	   0x1180010000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"GMX1_TX002_STATS_CTL"        ,	   0x1180010001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"GMX1_TX000_THRESH"           ,	   0x1180010000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"GMX1_TX001_THRESH"           ,	   0x1180010000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"GMX1_TX002_THRESH"           ,	   0x1180010001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"GMX1_TX003_THRESH"           ,	   0x1180010001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"GMX0_TX_BP"                  ,	   0x11800080004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"GMX1_TX_BP"                  ,	   0x11800100004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"GMX1_TX_COL_ATTEMPT"         ,	   0x1180010000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"GMX1_TX_CORRUPT"             ,	   0x11800100004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"GMX0_TX_HG2_REG1"            ,	   0x1180008000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"GMX1_TX_HG2_REG1"            ,	   0x1180010000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"GMX0_TX_HG2_REG2"            ,	   0x1180008000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"GMX1_TX_HG2_REG2"            ,	   0x1180010000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"GMX1_TX_IFG"                 ,	   0x1180010000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"GMX1_TX_INT_EN"              ,	   0x1180010000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"GMX1_TX_INT_REG"             ,	   0x1180010000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"GMX1_TX_JAM"                 ,	   0x1180010000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"GMX1_TX_LFSR"                ,	   0x11800100004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"GMX1_TX_OVR_BP"              ,	   0x11800100004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"GMX1_TX_PRTS"                ,	   0x1180010000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"GMX0_TX_XAUI_CTL"            ,	   0x1180008000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"GMX1_TX_XAUI_CTL"            ,	   0x1180010000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"GMX0_XAUI_EXT_LOOPBACK"      ,	   0x1180008000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"GMX1_XAUI_EXT_LOOPBACK"      ,	   0x1180010000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"GPIO_BIT_CFG3"               ,	   0x1070000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"GPIO_BIT_CFG4"               ,	   0x1070000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"GPIO_BIT_CFG5"               ,	   0x1070000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"GPIO_BIT_CFG6"               ,	   0x1070000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"GPIO_BIT_CFG7"               ,	   0x1070000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"GPIO_BIT_CFG8"               ,	   0x1070000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"GPIO_BIT_CFG9"               ,	   0x1070000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"GPIO_BIT_CFG10"              ,	   0x1070000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"GPIO_BIT_CFG11"              ,	   0x1070000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"GPIO_BIT_CFG12"              ,	   0x1070000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"GPIO_CLK_GEN0"               ,	   0x10700000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
+	{"GPIO_CLK_GEN1"               ,	   0x10700000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
+	{"GPIO_CLK_GEN2"               ,	   0x10700000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
+	{"GPIO_CLK_GEN3"               ,	   0x10700000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
+	{"GPIO_CLK_QLM0"               ,	   0x10700000008e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
+	{"GPIO_CLK_QLM1"               ,	   0x10700000008e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
+	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	330},
+	{"GPIO_PIN_ENA"                ,	   0x10700000008b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	331},
+	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
+	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	333},
+	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"GPIO_XBIT_CFG16"             ,	   0x1070000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"GPIO_XBIT_CFG17"             ,	   0x1070000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"GPIO_XBIT_CFG18"             ,	   0x1070000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"GPIO_XBIT_CFG19"             ,	   0x1070000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"IOB_BIST_STATUS"             ,	   0x11800f00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
+	{"IOB_CTL_STATUS"              ,	   0x11800f0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800f0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800f0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800f0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800f0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800f0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800f0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800f0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"IOB_INT_ENB"                 ,	   0x11800f0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"IOB_INT_SUM"                 ,	   0x11800f0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800f0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800f0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800f0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800f0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800f00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800f0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800f00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	353},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800f0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800f0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800f0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"IOB_PKT_ERR"                 ,	   0x11800f0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"IOB_TO_CMB_CREDITS"          ,	   0x11800f00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"IPD_BIST_STATUS"             ,	   0x14f00000007f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14f0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	363},
+	{"IPD_CLK_COUNT"               ,	   0x14f0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
+	{"IPD_CTL_STATUS"              ,	   0x14f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	365},
+	{"IPD_INT_ENB"                 ,	   0x14f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
+	{"IPD_INT_SUM"                 ,	   0x14f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14f0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14f00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14f00000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14f00000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14f00000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14f0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14f0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"IPD_PORT36_BP_PAGE_CNT2"     ,	   0x14f0000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
+	{"IPD_PORT37_BP_PAGE_CNT2"     ,	   0x14f0000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
+	{"IPD_PORT38_BP_PAGE_CNT2"     ,	   0x14f0000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
+	{"IPD_PORT39_BP_PAGE_CNT2"     ,	   0x14f0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
+	{"IPD_PORT40_BP_PAGE_CNT3"     ,	   0x14f00000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
+	{"IPD_PORT41_BP_PAGE_CNT3"     ,	   0x14f00000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
+	{"IPD_PORT44_BP_PAGE_CNT3"     ,	   0x14f00000003f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
+	{"IPD_PORT45_BP_PAGE_CNT3"     ,	   0x14f00000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
+	{"IPD_PORT46_BP_PAGE_CNT3"     ,	   0x14f0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
+	{"IPD_PORT47_BP_PAGE_CNT3"     ,	   0x14f0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
+	{"IPD_PORT_BP_COUNTERS2_PAIR36",	   0x14f0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
+	{"IPD_PORT_BP_COUNTERS2_PAIR37",	   0x14f0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
+	{"IPD_PORT_BP_COUNTERS2_PAIR38",	   0x14f0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
+	{"IPD_PORT_BP_COUNTERS2_PAIR39",	   0x14f00000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
+	{"IPD_PORT_BP_COUNTERS3_PAIR40",	   0x14f00000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
+	{"IPD_PORT_BP_COUNTERS3_PAIR41",	   0x14f00000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
+	{"IPD_PORT_BP_COUNTERS3_PAIR42",	   0x14f00000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
+	{"IPD_PORT_BP_COUNTERS3_PAIR43",	   0x14f00000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
+	{"IPD_PORT_BP_COUNTERS4_PAIR44",	   0x14f0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
+	{"IPD_PORT_BP_COUNTERS4_PAIR45",	   0x14f0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
+	{"IPD_PORT_BP_COUNTERS4_PAIR46",	   0x14f0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
+	{"IPD_PORT_BP_COUNTERS4_PAIR47",	   0x14f0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14f00000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14f0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14f0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14f0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14f0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14f00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14f00000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14f00000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14f00000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"IPD_PORT_QOS_0_CNT"          ,	   0x14f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_1_CNT"          ,	   0x14f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_2_CNT"          ,	   0x14f0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_3_CNT"          ,	   0x14f00000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_4_CNT"          ,	   0x14f00000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_5_CNT"          ,	   0x14f00000008b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_6_CNT"          ,	   0x14f00000008b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_7_CNT"          ,	   0x14f00000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_8_CNT"          ,	   0x14f00000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_9_CNT"          ,	   0x14f00000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_10_CNT"         ,	   0x14f00000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_11_CNT"         ,	   0x14f00000008e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_12_CNT"         ,	   0x14f00000008e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_13_CNT"         ,	   0x14f00000008f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_14_CNT"         ,	   0x14f00000008f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_15_CNT"         ,	   0x14f0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_16_CNT"         ,	   0x14f0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_17_CNT"         ,	   0x14f0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_18_CNT"         ,	   0x14f0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_19_CNT"         ,	   0x14f0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_20_CNT"         ,	   0x14f0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_21_CNT"         ,	   0x14f0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_22_CNT"         ,	   0x14f0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_23_CNT"         ,	   0x14f0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_24_CNT"         ,	   0x14f0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_25_CNT"         ,	   0x14f0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_26_CNT"         ,	   0x14f0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_27_CNT"         ,	   0x14f0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_28_CNT"         ,	   0x14f0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_29_CNT"         ,	   0x14f0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_30_CNT"         ,	   0x14f0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_31_CNT"         ,	   0x14f0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_128_CNT"        ,	   0x14f0000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_129_CNT"        ,	   0x14f0000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_130_CNT"        ,	   0x14f0000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_131_CNT"        ,	   0x14f0000000ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_132_CNT"        ,	   0x14f0000000ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_133_CNT"        ,	   0x14f0000000cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_134_CNT"        ,	   0x14f0000000cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_135_CNT"        ,	   0x14f0000000cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_136_CNT"        ,	   0x14f0000000cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_137_CNT"        ,	   0x14f0000000cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_138_CNT"        ,	   0x14f0000000cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_139_CNT"        ,	   0x14f0000000ce0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_140_CNT"        ,	   0x14f0000000ce8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_141_CNT"        ,	   0x14f0000000cf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_142_CNT"        ,	   0x14f0000000cf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_143_CNT"        ,	   0x14f0000000d00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_144_CNT"        ,	   0x14f0000000d08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_145_CNT"        ,	   0x14f0000000d10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_146_CNT"        ,	   0x14f0000000d18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_147_CNT"        ,	   0x14f0000000d20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_148_CNT"        ,	   0x14f0000000d28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_149_CNT"        ,	   0x14f0000000d30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_150_CNT"        ,	   0x14f0000000d38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_151_CNT"        ,	   0x14f0000000d40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_152_CNT"        ,	   0x14f0000000d48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_153_CNT"        ,	   0x14f0000000d50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_154_CNT"        ,	   0x14f0000000d58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_155_CNT"        ,	   0x14f0000000d60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_156_CNT"        ,	   0x14f0000000d68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_157_CNT"        ,	   0x14f0000000d70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_158_CNT"        ,	   0x14f0000000d78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_159_CNT"        ,	   0x14f0000000d80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_256_CNT"        ,	   0x14f0000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_257_CNT"        ,	   0x14f0000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_258_CNT"        ,	   0x14f0000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_259_CNT"        ,	   0x14f00000010a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_260_CNT"        ,	   0x14f00000010a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_261_CNT"        ,	   0x14f00000010b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_262_CNT"        ,	   0x14f00000010b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_263_CNT"        ,	   0x14f00000010c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_264_CNT"        ,	   0x14f00000010c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_265_CNT"        ,	   0x14f00000010d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_266_CNT"        ,	   0x14f00000010d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_267_CNT"        ,	   0x14f00000010e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_268_CNT"        ,	   0x14f00000010e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_269_CNT"        ,	   0x14f00000010f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_270_CNT"        ,	   0x14f00000010f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_271_CNT"        ,	   0x14f0000001100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_272_CNT"        ,	   0x14f0000001108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_273_CNT"        ,	   0x14f0000001110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_274_CNT"        ,	   0x14f0000001118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_275_CNT"        ,	   0x14f0000001120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_276_CNT"        ,	   0x14f0000001128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_277_CNT"        ,	   0x14f0000001130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_278_CNT"        ,	   0x14f0000001138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_279_CNT"        ,	   0x14f0000001140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_280_CNT"        ,	   0x14f0000001148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_281_CNT"        ,	   0x14f0000001150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_282_CNT"        ,	   0x14f0000001158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_283_CNT"        ,	   0x14f0000001160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_284_CNT"        ,	   0x14f0000001168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_285_CNT"        ,	   0x14f0000001170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_286_CNT"        ,	   0x14f0000001178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_287_CNT"        ,	   0x14f0000001180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_288_CNT"        ,	   0x14f0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_289_CNT"        ,	   0x14f0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_290_CNT"        ,	   0x14f0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_291_CNT"        ,	   0x14f00000011a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_292_CNT"        ,	   0x14f00000011a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_293_CNT"        ,	   0x14f00000011b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_294_CNT"        ,	   0x14f00000011b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_295_CNT"        ,	   0x14f00000011c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_296_CNT"        ,	   0x14f00000011c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_297_CNT"        ,	   0x14f00000011d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_298_CNT"        ,	   0x14f00000011d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_299_CNT"        ,	   0x14f00000011e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_300_CNT"        ,	   0x14f00000011e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_301_CNT"        ,	   0x14f00000011f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_302_CNT"        ,	   0x14f00000011f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_303_CNT"        ,	   0x14f0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_304_CNT"        ,	   0x14f0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_305_CNT"        ,	   0x14f0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_306_CNT"        ,	   0x14f0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_307_CNT"        ,	   0x14f0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_308_CNT"        ,	   0x14f0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_309_CNT"        ,	   0x14f0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_310_CNT"        ,	   0x14f0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_311_CNT"        ,	   0x14f0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_312_CNT"        ,	   0x14f0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_313_CNT"        ,	   0x14f0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_314_CNT"        ,	   0x14f0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_315_CNT"        ,	   0x14f0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_316_CNT"        ,	   0x14f0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_317_CNT"        ,	   0x14f0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_318_CNT"        ,	   0x14f0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_319_CNT"        ,	   0x14f0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_320_CNT"        ,	   0x14f0000001288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_321_CNT"        ,	   0x14f0000001290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_322_CNT"        ,	   0x14f0000001298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_323_CNT"        ,	   0x14f00000012a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_324_CNT"        ,	   0x14f00000012a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_325_CNT"        ,	   0x14f00000012b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_326_CNT"        ,	   0x14f00000012b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_327_CNT"        ,	   0x14f00000012c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_328_CNT"        ,	   0x14f00000012c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_329_CNT"        ,	   0x14f00000012d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_330_CNT"        ,	   0x14f00000012d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_331_CNT"        ,	   0x14f00000012e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_332_CNT"        ,	   0x14f00000012e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_333_CNT"        ,	   0x14f00000012f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_334_CNT"        ,	   0x14f00000012f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_335_CNT"        ,	   0x14f0000001300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_352_CNT"        ,	   0x14f0000001388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_353_CNT"        ,	   0x14f0000001390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_354_CNT"        ,	   0x14f0000001398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_355_CNT"        ,	   0x14f00000013a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_356_CNT"        ,	   0x14f00000013a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_357_CNT"        ,	   0x14f00000013b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_358_CNT"        ,	   0x14f00000013b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_359_CNT"        ,	   0x14f00000013c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_360_CNT"        ,	   0x14f00000013c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_361_CNT"        ,	   0x14f00000013d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_362_CNT"        ,	   0x14f00000013d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_363_CNT"        ,	   0x14f00000013e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_364_CNT"        ,	   0x14f00000013e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_365_CNT"        ,	   0x14f00000013f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_366_CNT"        ,	   0x14f00000013f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_367_CNT"        ,	   0x14f0000001400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_368_CNT"        ,	   0x14f0000001408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_369_CNT"        ,	   0x14f0000001410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_370_CNT"        ,	   0x14f0000001418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_371_CNT"        ,	   0x14f0000001420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_372_CNT"        ,	   0x14f0000001428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_373_CNT"        ,	   0x14f0000001430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_374_CNT"        ,	   0x14f0000001438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_375_CNT"        ,	   0x14f0000001440ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_376_CNT"        ,	   0x14f0000001448ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_377_CNT"        ,	   0x14f0000001450ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_378_CNT"        ,	   0x14f0000001458ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_379_CNT"        ,	   0x14f0000001460ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_380_CNT"        ,	   0x14f0000001468ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_381_CNT"        ,	   0x14f0000001470ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_382_CNT"        ,	   0x14f0000001478ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_383_CNT"        ,	   0x14f0000001480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"IPD_PORT_QOS_INT0"           ,	   0x14f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
+	{"IPD_PORT_QOS_INT2"           ,	   0x14f0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
+	{"IPD_PORT_QOS_INT4"           ,	   0x14f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
+	{"IPD_PORT_QOS_INT5"           ,	   0x14f0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
+	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"IPD_PORT_QOS_INT_ENB2"       ,	   0x14f0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"IPD_PORT_QOS_INT_ENB5"       ,	   0x14f0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14f0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14f0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"IPD_PTR_COUNT"               ,	   0x14f0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14f0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14f0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14f00000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"IPD_RED_PORT_ENABLE2"        ,	   0x14f00000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14f00000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14f00000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14f00000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14f00000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14f0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14f0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14f0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14f0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
+	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14f0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
+	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"L2C_BIG_CTL"                 ,	   0x1180080800030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"L2C_BST"                     ,	   0x11800808007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"L2C_BST_MEM0"                ,	   0x1180080c007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"L2C_BST_TDT0"                ,	   0x1180080a007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_BST_TTG0"                ,	   0x1180080a007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"L2C_COP0_MAP0"               ,	   0x1180080940000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1"               ,	   0x1180080940008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2"               ,	   0x1180080940010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP3"               ,	   0x1180080940018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP4"               ,	   0x1180080940020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP5"               ,	   0x1180080940028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP6"               ,	   0x1180080940030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP7"               ,	   0x1180080940038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP8"               ,	   0x1180080940040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP9"               ,	   0x1180080940048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP10"              ,	   0x1180080940050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP11"              ,	   0x1180080940058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP12"              ,	   0x1180080940060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP13"              ,	   0x1180080940068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP14"              ,	   0x1180080940070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP15"              ,	   0x1180080940078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16"              ,	   0x1180080940080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP17"              ,	   0x1180080940088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP18"              ,	   0x1180080940090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP19"              ,	   0x1180080940098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP20"              ,	   0x11800809400a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP21"              ,	   0x11800809400a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP22"              ,	   0x11800809400b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP23"              ,	   0x11800809400b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP24"              ,	   0x11800809400c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP25"              ,	   0x11800809400c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP26"              ,	   0x11800809400d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP27"              ,	   0x11800809400d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP28"              ,	   0x11800809400e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP29"              ,	   0x11800809400e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP30"              ,	   0x11800809400f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP31"              ,	   0x11800809400f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP32"              ,	   0x1180080940100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP33"              ,	   0x1180080940108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP34"              ,	   0x1180080940110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP35"              ,	   0x1180080940118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP36"              ,	   0x1180080940120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP37"              ,	   0x1180080940128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP38"              ,	   0x1180080940130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP39"              ,	   0x1180080940138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP40"              ,	   0x1180080940140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP41"              ,	   0x1180080940148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP42"              ,	   0x1180080940150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP43"              ,	   0x1180080940158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP44"              ,	   0x1180080940160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP45"              ,	   0x1180080940168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP46"              ,	   0x1180080940170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP47"              ,	   0x1180080940178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP48"              ,	   0x1180080940180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP49"              ,	   0x1180080940188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP50"              ,	   0x1180080940190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP51"              ,	   0x1180080940198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP52"              ,	   0x11800809401a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP53"              ,	   0x11800809401a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP54"              ,	   0x11800809401b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP55"              ,	   0x11800809401b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP56"              ,	   0x11800809401c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP57"              ,	   0x11800809401c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP58"              ,	   0x11800809401d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP59"              ,	   0x11800809401d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP60"              ,	   0x11800809401e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP61"              ,	   0x11800809401e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP62"              ,	   0x11800809401f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP63"              ,	   0x11800809401f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP64"              ,	   0x1180080940200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP65"              ,	   0x1180080940208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP66"              ,	   0x1180080940210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP67"              ,	   0x1180080940218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP68"              ,	   0x1180080940220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP69"              ,	   0x1180080940228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP70"              ,	   0x1180080940230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP71"              ,	   0x1180080940238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP72"              ,	   0x1180080940240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP73"              ,	   0x1180080940248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP74"              ,	   0x1180080940250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP75"              ,	   0x1180080940258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP76"              ,	   0x1180080940260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP77"              ,	   0x1180080940268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP78"              ,	   0x1180080940270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP79"              ,	   0x1180080940278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP80"              ,	   0x1180080940280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP81"              ,	   0x1180080940288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP82"              ,	   0x1180080940290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP83"              ,	   0x1180080940298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP84"              ,	   0x11800809402a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP85"              ,	   0x11800809402a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP86"              ,	   0x11800809402b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP87"              ,	   0x11800809402b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP88"              ,	   0x11800809402c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP89"              ,	   0x11800809402c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP90"              ,	   0x11800809402d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP91"              ,	   0x11800809402d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP92"              ,	   0x11800809402e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP93"              ,	   0x11800809402e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP94"              ,	   0x11800809402f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP95"              ,	   0x11800809402f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP96"              ,	   0x1180080940300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP97"              ,	   0x1180080940308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP98"              ,	   0x1180080940310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP99"              ,	   0x1180080940318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP100"             ,	   0x1180080940320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP101"             ,	   0x1180080940328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP102"             ,	   0x1180080940330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP103"             ,	   0x1180080940338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP104"             ,	   0x1180080940340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP105"             ,	   0x1180080940348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP106"             ,	   0x1180080940350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP107"             ,	   0x1180080940358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP108"             ,	   0x1180080940360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP109"             ,	   0x1180080940368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP110"             ,	   0x1180080940370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP111"             ,	   0x1180080940378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP112"             ,	   0x1180080940380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP113"             ,	   0x1180080940388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP114"             ,	   0x1180080940390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP115"             ,	   0x1180080940398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP116"             ,	   0x11800809403a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP117"             ,	   0x11800809403a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP118"             ,	   0x11800809403b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP119"             ,	   0x11800809403b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP120"             ,	   0x11800809403c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP121"             ,	   0x11800809403c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP122"             ,	   0x11800809403d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP123"             ,	   0x11800809403d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP124"             ,	   0x11800809403e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP125"             ,	   0x11800809403e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP126"             ,	   0x11800809403f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP127"             ,	   0x11800809403f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP128"             ,	   0x1180080940400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP129"             ,	   0x1180080940408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP130"             ,	   0x1180080940410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP131"             ,	   0x1180080940418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP132"             ,	   0x1180080940420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP133"             ,	   0x1180080940428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP134"             ,	   0x1180080940430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP135"             ,	   0x1180080940438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP136"             ,	   0x1180080940440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP137"             ,	   0x1180080940448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP138"             ,	   0x1180080940450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP139"             ,	   0x1180080940458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP140"             ,	   0x1180080940460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP141"             ,	   0x1180080940468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP142"             ,	   0x1180080940470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP143"             ,	   0x1180080940478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP144"             ,	   0x1180080940480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP145"             ,	   0x1180080940488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP146"             ,	   0x1180080940490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP147"             ,	   0x1180080940498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP148"             ,	   0x11800809404a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP149"             ,	   0x11800809404a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP150"             ,	   0x11800809404b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP151"             ,	   0x11800809404b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP152"             ,	   0x11800809404c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP153"             ,	   0x11800809404c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP154"             ,	   0x11800809404d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP155"             ,	   0x11800809404d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP156"             ,	   0x11800809404e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP157"             ,	   0x11800809404e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP158"             ,	   0x11800809404f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP159"             ,	   0x11800809404f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP160"             ,	   0x1180080940500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP161"             ,	   0x1180080940508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP162"             ,	   0x1180080940510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP163"             ,	   0x1180080940518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP164"             ,	   0x1180080940520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP165"             ,	   0x1180080940528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP166"             ,	   0x1180080940530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP167"             ,	   0x1180080940538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP168"             ,	   0x1180080940540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP169"             ,	   0x1180080940548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP170"             ,	   0x1180080940550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP171"             ,	   0x1180080940558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP172"             ,	   0x1180080940560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP173"             ,	   0x1180080940568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP174"             ,	   0x1180080940570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP175"             ,	   0x1180080940578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP176"             ,	   0x1180080940580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP177"             ,	   0x1180080940588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP178"             ,	   0x1180080940590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP179"             ,	   0x1180080940598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP180"             ,	   0x11800809405a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP181"             ,	   0x11800809405a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP182"             ,	   0x11800809405b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP183"             ,	   0x11800809405b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP184"             ,	   0x11800809405c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP185"             ,	   0x11800809405c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP186"             ,	   0x11800809405d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP187"             ,	   0x11800809405d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP188"             ,	   0x11800809405e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP189"             ,	   0x11800809405e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP190"             ,	   0x11800809405f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP191"             ,	   0x11800809405f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP192"             ,	   0x1180080940600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP193"             ,	   0x1180080940608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP194"             ,	   0x1180080940610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP195"             ,	   0x1180080940618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP196"             ,	   0x1180080940620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP197"             ,	   0x1180080940628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP198"             ,	   0x1180080940630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP199"             ,	   0x1180080940638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP200"             ,	   0x1180080940640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP201"             ,	   0x1180080940648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP202"             ,	   0x1180080940650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP203"             ,	   0x1180080940658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP204"             ,	   0x1180080940660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP205"             ,	   0x1180080940668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP206"             ,	   0x1180080940670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP207"             ,	   0x1180080940678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP208"             ,	   0x1180080940680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP209"             ,	   0x1180080940688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP210"             ,	   0x1180080940690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP211"             ,	   0x1180080940698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP212"             ,	   0x11800809406a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP213"             ,	   0x11800809406a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP214"             ,	   0x11800809406b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP215"             ,	   0x11800809406b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP216"             ,	   0x11800809406c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP217"             ,	   0x11800809406c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP218"             ,	   0x11800809406d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP219"             ,	   0x11800809406d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP220"             ,	   0x11800809406e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP221"             ,	   0x11800809406e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP222"             ,	   0x11800809406f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP223"             ,	   0x11800809406f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP224"             ,	   0x1180080940700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP225"             ,	   0x1180080940708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP226"             ,	   0x1180080940710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP227"             ,	   0x1180080940718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP228"             ,	   0x1180080940720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP229"             ,	   0x1180080940728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP230"             ,	   0x1180080940730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP231"             ,	   0x1180080940738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP232"             ,	   0x1180080940740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP233"             ,	   0x1180080940748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP234"             ,	   0x1180080940750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP235"             ,	   0x1180080940758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP236"             ,	   0x1180080940760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP237"             ,	   0x1180080940768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP238"             ,	   0x1180080940770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP239"             ,	   0x1180080940778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP240"             ,	   0x1180080940780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP241"             ,	   0x1180080940788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP242"             ,	   0x1180080940790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP243"             ,	   0x1180080940798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP244"             ,	   0x11800809407a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP245"             ,	   0x11800809407a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP246"             ,	   0x11800809407b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP247"             ,	   0x11800809407b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP248"             ,	   0x11800809407c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP249"             ,	   0x11800809407c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP250"             ,	   0x11800809407d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP251"             ,	   0x11800809407d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP252"             ,	   0x11800809407e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP253"             ,	   0x11800809407e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP254"             ,	   0x11800809407f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP255"             ,	   0x11800809407f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP256"             ,	   0x1180080940800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP257"             ,	   0x1180080940808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP258"             ,	   0x1180080940810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP259"             ,	   0x1180080940818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP260"             ,	   0x1180080940820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP261"             ,	   0x1180080940828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP262"             ,	   0x1180080940830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP263"             ,	   0x1180080940838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP264"             ,	   0x1180080940840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP265"             ,	   0x1180080940848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP266"             ,	   0x1180080940850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP267"             ,	   0x1180080940858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP268"             ,	   0x1180080940860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP269"             ,	   0x1180080940868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP270"             ,	   0x1180080940870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP271"             ,	   0x1180080940878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP272"             ,	   0x1180080940880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP273"             ,	   0x1180080940888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP274"             ,	   0x1180080940890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP275"             ,	   0x1180080940898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP276"             ,	   0x11800809408a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP277"             ,	   0x11800809408a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP278"             ,	   0x11800809408b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP279"             ,	   0x11800809408b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP280"             ,	   0x11800809408c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP281"             ,	   0x11800809408c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP282"             ,	   0x11800809408d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP283"             ,	   0x11800809408d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP284"             ,	   0x11800809408e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP285"             ,	   0x11800809408e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP286"             ,	   0x11800809408f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP287"             ,	   0x11800809408f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP288"             ,	   0x1180080940900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP289"             ,	   0x1180080940908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP290"             ,	   0x1180080940910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP291"             ,	   0x1180080940918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP292"             ,	   0x1180080940920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP293"             ,	   0x1180080940928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP294"             ,	   0x1180080940930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP295"             ,	   0x1180080940938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP296"             ,	   0x1180080940940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP297"             ,	   0x1180080940948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP298"             ,	   0x1180080940950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP299"             ,	   0x1180080940958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP300"             ,	   0x1180080940960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP301"             ,	   0x1180080940968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP302"             ,	   0x1180080940970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP303"             ,	   0x1180080940978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP304"             ,	   0x1180080940980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP305"             ,	   0x1180080940988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP306"             ,	   0x1180080940990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP307"             ,	   0x1180080940998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP308"             ,	   0x11800809409a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP309"             ,	   0x11800809409a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP310"             ,	   0x11800809409b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP311"             ,	   0x11800809409b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP312"             ,	   0x11800809409c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP313"             ,	   0x11800809409c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP314"             ,	   0x11800809409d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP315"             ,	   0x11800809409d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP316"             ,	   0x11800809409e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP317"             ,	   0x11800809409e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP318"             ,	   0x11800809409f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP319"             ,	   0x11800809409f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP320"             ,	   0x1180080940a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP321"             ,	   0x1180080940a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP322"             ,	   0x1180080940a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP323"             ,	   0x1180080940a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP324"             ,	   0x1180080940a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP325"             ,	   0x1180080940a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP326"             ,	   0x1180080940a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP327"             ,	   0x1180080940a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP328"             ,	   0x1180080940a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP329"             ,	   0x1180080940a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP330"             ,	   0x1180080940a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP331"             ,	   0x1180080940a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP332"             ,	   0x1180080940a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP333"             ,	   0x1180080940a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP334"             ,	   0x1180080940a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP335"             ,	   0x1180080940a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP336"             ,	   0x1180080940a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP337"             ,	   0x1180080940a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP338"             ,	   0x1180080940a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP339"             ,	   0x1180080940a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP340"             ,	   0x1180080940aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP341"             ,	   0x1180080940aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP342"             ,	   0x1180080940ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP343"             ,	   0x1180080940ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP344"             ,	   0x1180080940ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP345"             ,	   0x1180080940ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP346"             ,	   0x1180080940ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP347"             ,	   0x1180080940ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP348"             ,	   0x1180080940ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP349"             ,	   0x1180080940ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP350"             ,	   0x1180080940af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP351"             ,	   0x1180080940af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP352"             ,	   0x1180080940b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP353"             ,	   0x1180080940b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP354"             ,	   0x1180080940b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP355"             ,	   0x1180080940b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP356"             ,	   0x1180080940b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP357"             ,	   0x1180080940b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP358"             ,	   0x1180080940b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP359"             ,	   0x1180080940b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP360"             ,	   0x1180080940b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP361"             ,	   0x1180080940b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP362"             ,	   0x1180080940b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP363"             ,	   0x1180080940b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP364"             ,	   0x1180080940b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP365"             ,	   0x1180080940b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP366"             ,	   0x1180080940b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP367"             ,	   0x1180080940b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP368"             ,	   0x1180080940b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP369"             ,	   0x1180080940b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP370"             ,	   0x1180080940b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP371"             ,	   0x1180080940b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP372"             ,	   0x1180080940ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP373"             ,	   0x1180080940ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP374"             ,	   0x1180080940bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP375"             ,	   0x1180080940bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP376"             ,	   0x1180080940bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP377"             ,	   0x1180080940bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP378"             ,	   0x1180080940bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP379"             ,	   0x1180080940bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP380"             ,	   0x1180080940be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP381"             ,	   0x1180080940be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP382"             ,	   0x1180080940bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP383"             ,	   0x1180080940bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP384"             ,	   0x1180080940c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP385"             ,	   0x1180080940c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP386"             ,	   0x1180080940c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP387"             ,	   0x1180080940c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP388"             ,	   0x1180080940c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP389"             ,	   0x1180080940c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP390"             ,	   0x1180080940c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP391"             ,	   0x1180080940c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP392"             ,	   0x1180080940c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP393"             ,	   0x1180080940c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP394"             ,	   0x1180080940c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP395"             ,	   0x1180080940c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP396"             ,	   0x1180080940c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP397"             ,	   0x1180080940c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP398"             ,	   0x1180080940c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP399"             ,	   0x1180080940c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP400"             ,	   0x1180080940c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP401"             ,	   0x1180080940c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP402"             ,	   0x1180080940c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP403"             ,	   0x1180080940c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP404"             ,	   0x1180080940ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP405"             ,	   0x1180080940ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP406"             ,	   0x1180080940cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP407"             ,	   0x1180080940cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP408"             ,	   0x1180080940cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP409"             ,	   0x1180080940cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP410"             ,	   0x1180080940cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP411"             ,	   0x1180080940cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP412"             ,	   0x1180080940ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP413"             ,	   0x1180080940ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP414"             ,	   0x1180080940cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP415"             ,	   0x1180080940cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP416"             ,	   0x1180080940d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP417"             ,	   0x1180080940d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP418"             ,	   0x1180080940d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP419"             ,	   0x1180080940d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP420"             ,	   0x1180080940d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP421"             ,	   0x1180080940d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP422"             ,	   0x1180080940d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP423"             ,	   0x1180080940d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP424"             ,	   0x1180080940d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP425"             ,	   0x1180080940d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP426"             ,	   0x1180080940d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP427"             ,	   0x1180080940d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP428"             ,	   0x1180080940d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP429"             ,	   0x1180080940d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP430"             ,	   0x1180080940d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP431"             ,	   0x1180080940d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP432"             ,	   0x1180080940d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP433"             ,	   0x1180080940d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP434"             ,	   0x1180080940d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP435"             ,	   0x1180080940d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP436"             ,	   0x1180080940da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP437"             ,	   0x1180080940da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP438"             ,	   0x1180080940db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP439"             ,	   0x1180080940db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP440"             ,	   0x1180080940dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP441"             ,	   0x1180080940dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP442"             ,	   0x1180080940dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP443"             ,	   0x1180080940dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP444"             ,	   0x1180080940de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP445"             ,	   0x1180080940de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP446"             ,	   0x1180080940df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP447"             ,	   0x1180080940df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP448"             ,	   0x1180080940e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP449"             ,	   0x1180080940e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP450"             ,	   0x1180080940e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP451"             ,	   0x1180080940e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP452"             ,	   0x1180080940e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP453"             ,	   0x1180080940e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP454"             ,	   0x1180080940e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP455"             ,	   0x1180080940e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP456"             ,	   0x1180080940e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP457"             ,	   0x1180080940e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP458"             ,	   0x1180080940e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP459"             ,	   0x1180080940e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP460"             ,	   0x1180080940e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP461"             ,	   0x1180080940e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP462"             ,	   0x1180080940e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP463"             ,	   0x1180080940e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP464"             ,	   0x1180080940e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP465"             ,	   0x1180080940e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP466"             ,	   0x1180080940e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP467"             ,	   0x1180080940e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP468"             ,	   0x1180080940ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP469"             ,	   0x1180080940ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP470"             ,	   0x1180080940eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP471"             ,	   0x1180080940eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP472"             ,	   0x1180080940ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP473"             ,	   0x1180080940ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP474"             ,	   0x1180080940ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP475"             ,	   0x1180080940ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP476"             ,	   0x1180080940ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP477"             ,	   0x1180080940ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP478"             ,	   0x1180080940ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP479"             ,	   0x1180080940ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP480"             ,	   0x1180080940f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP481"             ,	   0x1180080940f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP482"             ,	   0x1180080940f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP483"             ,	   0x1180080940f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP484"             ,	   0x1180080940f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP485"             ,	   0x1180080940f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP486"             ,	   0x1180080940f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP487"             ,	   0x1180080940f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP488"             ,	   0x1180080940f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP489"             ,	   0x1180080940f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP490"             ,	   0x1180080940f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP491"             ,	   0x1180080940f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP492"             ,	   0x1180080940f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP493"             ,	   0x1180080940f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP494"             ,	   0x1180080940f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP495"             ,	   0x1180080940f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP496"             ,	   0x1180080940f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP497"             ,	   0x1180080940f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP498"             ,	   0x1180080940f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP499"             ,	   0x1180080940f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP500"             ,	   0x1180080940fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP501"             ,	   0x1180080940fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP502"             ,	   0x1180080940fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP503"             ,	   0x1180080940fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP504"             ,	   0x1180080940fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP505"             ,	   0x1180080940fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP506"             ,	   0x1180080940fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP507"             ,	   0x1180080940fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP508"             ,	   0x1180080940fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP509"             ,	   0x1180080940fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP510"             ,	   0x1180080940ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP511"             ,	   0x1180080940ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP512"             ,	   0x1180080941000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP513"             ,	   0x1180080941008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP514"             ,	   0x1180080941010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP515"             ,	   0x1180080941018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP516"             ,	   0x1180080941020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP517"             ,	   0x1180080941028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP518"             ,	   0x1180080941030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP519"             ,	   0x1180080941038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP520"             ,	   0x1180080941040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP521"             ,	   0x1180080941048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP522"             ,	   0x1180080941050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP523"             ,	   0x1180080941058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP524"             ,	   0x1180080941060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP525"             ,	   0x1180080941068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP526"             ,	   0x1180080941070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP527"             ,	   0x1180080941078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP528"             ,	   0x1180080941080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP529"             ,	   0x1180080941088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP530"             ,	   0x1180080941090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP531"             ,	   0x1180080941098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP532"             ,	   0x11800809410a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP533"             ,	   0x11800809410a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP534"             ,	   0x11800809410b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP535"             ,	   0x11800809410b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP536"             ,	   0x11800809410c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP537"             ,	   0x11800809410c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP538"             ,	   0x11800809410d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP539"             ,	   0x11800809410d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP540"             ,	   0x11800809410e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP541"             ,	   0x11800809410e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP542"             ,	   0x11800809410f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP543"             ,	   0x11800809410f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP544"             ,	   0x1180080941100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP545"             ,	   0x1180080941108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP546"             ,	   0x1180080941110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP547"             ,	   0x1180080941118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP548"             ,	   0x1180080941120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP549"             ,	   0x1180080941128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP550"             ,	   0x1180080941130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP551"             ,	   0x1180080941138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP552"             ,	   0x1180080941140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP553"             ,	   0x1180080941148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP554"             ,	   0x1180080941150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP555"             ,	   0x1180080941158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP556"             ,	   0x1180080941160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP557"             ,	   0x1180080941168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP558"             ,	   0x1180080941170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP559"             ,	   0x1180080941178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP560"             ,	   0x1180080941180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP561"             ,	   0x1180080941188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP562"             ,	   0x1180080941190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP563"             ,	   0x1180080941198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP564"             ,	   0x11800809411a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP565"             ,	   0x11800809411a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP566"             ,	   0x11800809411b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP567"             ,	   0x11800809411b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP568"             ,	   0x11800809411c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP569"             ,	   0x11800809411c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP570"             ,	   0x11800809411d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP571"             ,	   0x11800809411d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP572"             ,	   0x11800809411e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP573"             ,	   0x11800809411e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP574"             ,	   0x11800809411f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP575"             ,	   0x11800809411f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP576"             ,	   0x1180080941200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP577"             ,	   0x1180080941208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP578"             ,	   0x1180080941210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP579"             ,	   0x1180080941218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP580"             ,	   0x1180080941220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP581"             ,	   0x1180080941228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP582"             ,	   0x1180080941230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP583"             ,	   0x1180080941238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP584"             ,	   0x1180080941240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP585"             ,	   0x1180080941248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP586"             ,	   0x1180080941250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP587"             ,	   0x1180080941258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP588"             ,	   0x1180080941260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP589"             ,	   0x1180080941268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP590"             ,	   0x1180080941270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP591"             ,	   0x1180080941278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP592"             ,	   0x1180080941280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP593"             ,	   0x1180080941288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP594"             ,	   0x1180080941290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP595"             ,	   0x1180080941298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP596"             ,	   0x11800809412a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP597"             ,	   0x11800809412a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP598"             ,	   0x11800809412b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP599"             ,	   0x11800809412b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP600"             ,	   0x11800809412c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP601"             ,	   0x11800809412c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP602"             ,	   0x11800809412d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP603"             ,	   0x11800809412d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP604"             ,	   0x11800809412e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP605"             ,	   0x11800809412e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP606"             ,	   0x11800809412f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP607"             ,	   0x11800809412f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP608"             ,	   0x1180080941300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP609"             ,	   0x1180080941308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP610"             ,	   0x1180080941310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP611"             ,	   0x1180080941318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP612"             ,	   0x1180080941320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP613"             ,	   0x1180080941328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP614"             ,	   0x1180080941330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP615"             ,	   0x1180080941338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP616"             ,	   0x1180080941340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP617"             ,	   0x1180080941348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP618"             ,	   0x1180080941350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP619"             ,	   0x1180080941358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP620"             ,	   0x1180080941360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP621"             ,	   0x1180080941368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP622"             ,	   0x1180080941370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP623"             ,	   0x1180080941378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP624"             ,	   0x1180080941380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP625"             ,	   0x1180080941388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP626"             ,	   0x1180080941390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP627"             ,	   0x1180080941398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP628"             ,	   0x11800809413a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP629"             ,	   0x11800809413a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP630"             ,	   0x11800809413b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP631"             ,	   0x11800809413b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP632"             ,	   0x11800809413c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP633"             ,	   0x11800809413c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP634"             ,	   0x11800809413d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP635"             ,	   0x11800809413d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP636"             ,	   0x11800809413e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP637"             ,	   0x11800809413e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP638"             ,	   0x11800809413f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP639"             ,	   0x11800809413f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP640"             ,	   0x1180080941400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP641"             ,	   0x1180080941408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP642"             ,	   0x1180080941410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP643"             ,	   0x1180080941418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP644"             ,	   0x1180080941420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP645"             ,	   0x1180080941428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP646"             ,	   0x1180080941430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP647"             ,	   0x1180080941438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP648"             ,	   0x1180080941440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP649"             ,	   0x1180080941448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP650"             ,	   0x1180080941450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP651"             ,	   0x1180080941458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP652"             ,	   0x1180080941460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP653"             ,	   0x1180080941468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP654"             ,	   0x1180080941470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP655"             ,	   0x1180080941478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP656"             ,	   0x1180080941480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP657"             ,	   0x1180080941488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP658"             ,	   0x1180080941490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP659"             ,	   0x1180080941498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP660"             ,	   0x11800809414a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP661"             ,	   0x11800809414a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP662"             ,	   0x11800809414b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP663"             ,	   0x11800809414b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP664"             ,	   0x11800809414c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP665"             ,	   0x11800809414c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP666"             ,	   0x11800809414d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP667"             ,	   0x11800809414d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP668"             ,	   0x11800809414e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP669"             ,	   0x11800809414e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP670"             ,	   0x11800809414f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP671"             ,	   0x11800809414f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP672"             ,	   0x1180080941500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP673"             ,	   0x1180080941508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP674"             ,	   0x1180080941510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP675"             ,	   0x1180080941518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP676"             ,	   0x1180080941520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP677"             ,	   0x1180080941528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP678"             ,	   0x1180080941530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP679"             ,	   0x1180080941538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP680"             ,	   0x1180080941540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP681"             ,	   0x1180080941548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP682"             ,	   0x1180080941550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP683"             ,	   0x1180080941558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP684"             ,	   0x1180080941560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP685"             ,	   0x1180080941568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP686"             ,	   0x1180080941570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP687"             ,	   0x1180080941578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP688"             ,	   0x1180080941580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP689"             ,	   0x1180080941588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP690"             ,	   0x1180080941590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP691"             ,	   0x1180080941598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP692"             ,	   0x11800809415a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP693"             ,	   0x11800809415a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP694"             ,	   0x11800809415b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP695"             ,	   0x11800809415b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP696"             ,	   0x11800809415c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP697"             ,	   0x11800809415c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP698"             ,	   0x11800809415d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP699"             ,	   0x11800809415d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP700"             ,	   0x11800809415e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP701"             ,	   0x11800809415e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP702"             ,	   0x11800809415f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP703"             ,	   0x11800809415f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP704"             ,	   0x1180080941600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP705"             ,	   0x1180080941608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP706"             ,	   0x1180080941610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP707"             ,	   0x1180080941618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP708"             ,	   0x1180080941620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP709"             ,	   0x1180080941628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP710"             ,	   0x1180080941630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP711"             ,	   0x1180080941638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP712"             ,	   0x1180080941640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP713"             ,	   0x1180080941648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP714"             ,	   0x1180080941650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP715"             ,	   0x1180080941658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP716"             ,	   0x1180080941660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP717"             ,	   0x1180080941668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP718"             ,	   0x1180080941670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP719"             ,	   0x1180080941678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP720"             ,	   0x1180080941680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP721"             ,	   0x1180080941688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP722"             ,	   0x1180080941690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP723"             ,	   0x1180080941698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP724"             ,	   0x11800809416a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP725"             ,	   0x11800809416a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP726"             ,	   0x11800809416b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP727"             ,	   0x11800809416b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP728"             ,	   0x11800809416c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP729"             ,	   0x11800809416c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP730"             ,	   0x11800809416d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP731"             ,	   0x11800809416d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP732"             ,	   0x11800809416e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP733"             ,	   0x11800809416e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP734"             ,	   0x11800809416f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP735"             ,	   0x11800809416f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP736"             ,	   0x1180080941700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP737"             ,	   0x1180080941708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP738"             ,	   0x1180080941710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP739"             ,	   0x1180080941718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP740"             ,	   0x1180080941720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP741"             ,	   0x1180080941728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP742"             ,	   0x1180080941730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP743"             ,	   0x1180080941738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP744"             ,	   0x1180080941740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP745"             ,	   0x1180080941748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP746"             ,	   0x1180080941750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP747"             ,	   0x1180080941758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP748"             ,	   0x1180080941760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP749"             ,	   0x1180080941768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP750"             ,	   0x1180080941770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP751"             ,	   0x1180080941778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP752"             ,	   0x1180080941780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP753"             ,	   0x1180080941788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP754"             ,	   0x1180080941790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP755"             ,	   0x1180080941798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP756"             ,	   0x11800809417a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP757"             ,	   0x11800809417a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP758"             ,	   0x11800809417b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP759"             ,	   0x11800809417b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP760"             ,	   0x11800809417c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP761"             ,	   0x11800809417c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP762"             ,	   0x11800809417d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP763"             ,	   0x11800809417d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP764"             ,	   0x11800809417e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP765"             ,	   0x11800809417e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP766"             ,	   0x11800809417f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP767"             ,	   0x11800809417f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP768"             ,	   0x1180080941800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP769"             ,	   0x1180080941808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP770"             ,	   0x1180080941810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP771"             ,	   0x1180080941818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP772"             ,	   0x1180080941820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP773"             ,	   0x1180080941828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP774"             ,	   0x1180080941830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP775"             ,	   0x1180080941838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP776"             ,	   0x1180080941840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP777"             ,	   0x1180080941848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP778"             ,	   0x1180080941850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP779"             ,	   0x1180080941858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP780"             ,	   0x1180080941860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP781"             ,	   0x1180080941868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP782"             ,	   0x1180080941870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP783"             ,	   0x1180080941878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP784"             ,	   0x1180080941880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP785"             ,	   0x1180080941888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP786"             ,	   0x1180080941890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP787"             ,	   0x1180080941898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP788"             ,	   0x11800809418a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP789"             ,	   0x11800809418a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP790"             ,	   0x11800809418b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP791"             ,	   0x11800809418b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP792"             ,	   0x11800809418c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP793"             ,	   0x11800809418c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP794"             ,	   0x11800809418d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP795"             ,	   0x11800809418d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP796"             ,	   0x11800809418e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP797"             ,	   0x11800809418e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP798"             ,	   0x11800809418f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP799"             ,	   0x11800809418f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP800"             ,	   0x1180080941900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP801"             ,	   0x1180080941908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP802"             ,	   0x1180080941910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP803"             ,	   0x1180080941918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP804"             ,	   0x1180080941920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP805"             ,	   0x1180080941928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP806"             ,	   0x1180080941930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP807"             ,	   0x1180080941938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP808"             ,	   0x1180080941940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP809"             ,	   0x1180080941948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP810"             ,	   0x1180080941950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP811"             ,	   0x1180080941958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP812"             ,	   0x1180080941960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP813"             ,	   0x1180080941968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP814"             ,	   0x1180080941970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP815"             ,	   0x1180080941978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP816"             ,	   0x1180080941980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP817"             ,	   0x1180080941988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP818"             ,	   0x1180080941990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP819"             ,	   0x1180080941998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP820"             ,	   0x11800809419a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP821"             ,	   0x11800809419a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP822"             ,	   0x11800809419b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP823"             ,	   0x11800809419b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP824"             ,	   0x11800809419c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP825"             ,	   0x11800809419c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP826"             ,	   0x11800809419d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP827"             ,	   0x11800809419d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP828"             ,	   0x11800809419e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP829"             ,	   0x11800809419e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP830"             ,	   0x11800809419f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP831"             ,	   0x11800809419f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP832"             ,	   0x1180080941a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP833"             ,	   0x1180080941a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP834"             ,	   0x1180080941a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP835"             ,	   0x1180080941a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP836"             ,	   0x1180080941a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP837"             ,	   0x1180080941a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP838"             ,	   0x1180080941a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP839"             ,	   0x1180080941a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP840"             ,	   0x1180080941a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP841"             ,	   0x1180080941a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP842"             ,	   0x1180080941a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP843"             ,	   0x1180080941a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP844"             ,	   0x1180080941a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP845"             ,	   0x1180080941a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP846"             ,	   0x1180080941a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP847"             ,	   0x1180080941a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP848"             ,	   0x1180080941a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP849"             ,	   0x1180080941a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP850"             ,	   0x1180080941a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP851"             ,	   0x1180080941a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP852"             ,	   0x1180080941aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP853"             ,	   0x1180080941aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP854"             ,	   0x1180080941ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP855"             ,	   0x1180080941ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP856"             ,	   0x1180080941ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP857"             ,	   0x1180080941ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP858"             ,	   0x1180080941ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP859"             ,	   0x1180080941ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP860"             ,	   0x1180080941ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP861"             ,	   0x1180080941ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP862"             ,	   0x1180080941af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP863"             ,	   0x1180080941af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP864"             ,	   0x1180080941b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP865"             ,	   0x1180080941b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP866"             ,	   0x1180080941b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP867"             ,	   0x1180080941b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP868"             ,	   0x1180080941b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP869"             ,	   0x1180080941b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP870"             ,	   0x1180080941b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP871"             ,	   0x1180080941b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP872"             ,	   0x1180080941b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP873"             ,	   0x1180080941b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP874"             ,	   0x1180080941b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP875"             ,	   0x1180080941b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP876"             ,	   0x1180080941b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP877"             ,	   0x1180080941b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP878"             ,	   0x1180080941b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP879"             ,	   0x1180080941b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP880"             ,	   0x1180080941b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP881"             ,	   0x1180080941b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP882"             ,	   0x1180080941b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP883"             ,	   0x1180080941b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP884"             ,	   0x1180080941ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP885"             ,	   0x1180080941ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP886"             ,	   0x1180080941bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP887"             ,	   0x1180080941bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP888"             ,	   0x1180080941bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP889"             ,	   0x1180080941bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP890"             ,	   0x1180080941bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP891"             ,	   0x1180080941bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP892"             ,	   0x1180080941be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP893"             ,	   0x1180080941be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP894"             ,	   0x1180080941bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP895"             ,	   0x1180080941bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP896"             ,	   0x1180080941c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP897"             ,	   0x1180080941c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP898"             ,	   0x1180080941c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP899"             ,	   0x1180080941c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP900"             ,	   0x1180080941c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP901"             ,	   0x1180080941c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP902"             ,	   0x1180080941c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP903"             ,	   0x1180080941c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP904"             ,	   0x1180080941c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP905"             ,	   0x1180080941c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP906"             ,	   0x1180080941c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP907"             ,	   0x1180080941c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP908"             ,	   0x1180080941c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP909"             ,	   0x1180080941c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP910"             ,	   0x1180080941c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP911"             ,	   0x1180080941c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP912"             ,	   0x1180080941c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP913"             ,	   0x1180080941c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP914"             ,	   0x1180080941c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP915"             ,	   0x1180080941c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP916"             ,	   0x1180080941ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP917"             ,	   0x1180080941ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP918"             ,	   0x1180080941cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP919"             ,	   0x1180080941cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP920"             ,	   0x1180080941cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP921"             ,	   0x1180080941cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP922"             ,	   0x1180080941cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP923"             ,	   0x1180080941cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP924"             ,	   0x1180080941ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP925"             ,	   0x1180080941ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP926"             ,	   0x1180080941cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP927"             ,	   0x1180080941cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP928"             ,	   0x1180080941d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP929"             ,	   0x1180080941d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP930"             ,	   0x1180080941d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP931"             ,	   0x1180080941d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP932"             ,	   0x1180080941d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP933"             ,	   0x1180080941d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP934"             ,	   0x1180080941d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP935"             ,	   0x1180080941d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP936"             ,	   0x1180080941d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP937"             ,	   0x1180080941d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP938"             ,	   0x1180080941d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP939"             ,	   0x1180080941d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP940"             ,	   0x1180080941d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP941"             ,	   0x1180080941d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP942"             ,	   0x1180080941d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP943"             ,	   0x1180080941d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP944"             ,	   0x1180080941d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP945"             ,	   0x1180080941d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP946"             ,	   0x1180080941d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP947"             ,	   0x1180080941d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP948"             ,	   0x1180080941da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP949"             ,	   0x1180080941da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP950"             ,	   0x1180080941db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP951"             ,	   0x1180080941db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP952"             ,	   0x1180080941dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP953"             ,	   0x1180080941dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP954"             ,	   0x1180080941dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP955"             ,	   0x1180080941dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP956"             ,	   0x1180080941de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP957"             ,	   0x1180080941de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP958"             ,	   0x1180080941df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP959"             ,	   0x1180080941df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP960"             ,	   0x1180080941e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP961"             ,	   0x1180080941e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP962"             ,	   0x1180080941e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP963"             ,	   0x1180080941e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP964"             ,	   0x1180080941e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP965"             ,	   0x1180080941e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP966"             ,	   0x1180080941e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP967"             ,	   0x1180080941e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP968"             ,	   0x1180080941e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP969"             ,	   0x1180080941e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP970"             ,	   0x1180080941e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP971"             ,	   0x1180080941e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP972"             ,	   0x1180080941e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP973"             ,	   0x1180080941e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP974"             ,	   0x1180080941e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP975"             ,	   0x1180080941e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP976"             ,	   0x1180080941e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP977"             ,	   0x1180080941e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP978"             ,	   0x1180080941e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP979"             ,	   0x1180080941e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP980"             ,	   0x1180080941ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP981"             ,	   0x1180080941ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP982"             ,	   0x1180080941eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP983"             ,	   0x1180080941eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP984"             ,	   0x1180080941ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP985"             ,	   0x1180080941ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP986"             ,	   0x1180080941ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP987"             ,	   0x1180080941ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP988"             ,	   0x1180080941ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP989"             ,	   0x1180080941ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP990"             ,	   0x1180080941ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP991"             ,	   0x1180080941ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP992"             ,	   0x1180080941f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP993"             ,	   0x1180080941f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP994"             ,	   0x1180080941f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP995"             ,	   0x1180080941f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP996"             ,	   0x1180080941f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP997"             ,	   0x1180080941f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP998"             ,	   0x1180080941f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP999"             ,	   0x1180080941f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1000"            ,	   0x1180080941f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1001"            ,	   0x1180080941f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1002"            ,	   0x1180080941f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1003"            ,	   0x1180080941f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1004"            ,	   0x1180080941f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1005"            ,	   0x1180080941f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1006"            ,	   0x1180080941f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1007"            ,	   0x1180080941f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1008"            ,	   0x1180080941f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1009"            ,	   0x1180080941f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1010"            ,	   0x1180080941f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1011"            ,	   0x1180080941f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1012"            ,	   0x1180080941fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1013"            ,	   0x1180080941fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1014"            ,	   0x1180080941fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1015"            ,	   0x1180080941fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1016"            ,	   0x1180080941fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1017"            ,	   0x1180080941fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1018"            ,	   0x1180080941fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1019"            ,	   0x1180080941fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1020"            ,	   0x1180080941fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1021"            ,	   0x1180080941fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1022"            ,	   0x1180080941ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1023"            ,	   0x1180080941ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1024"            ,	   0x1180080942000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1025"            ,	   0x1180080942008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1026"            ,	   0x1180080942010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1027"            ,	   0x1180080942018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1028"            ,	   0x1180080942020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1029"            ,	   0x1180080942028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1030"            ,	   0x1180080942030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1031"            ,	   0x1180080942038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1032"            ,	   0x1180080942040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1033"            ,	   0x1180080942048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1034"            ,	   0x1180080942050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1035"            ,	   0x1180080942058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1036"            ,	   0x1180080942060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1037"            ,	   0x1180080942068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1038"            ,	   0x1180080942070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1039"            ,	   0x1180080942078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1040"            ,	   0x1180080942080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1041"            ,	   0x1180080942088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1042"            ,	   0x1180080942090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1043"            ,	   0x1180080942098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1044"            ,	   0x11800809420a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1045"            ,	   0x11800809420a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1046"            ,	   0x11800809420b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1047"            ,	   0x11800809420b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1048"            ,	   0x11800809420c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1049"            ,	   0x11800809420c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1050"            ,	   0x11800809420d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1051"            ,	   0x11800809420d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1052"            ,	   0x11800809420e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1053"            ,	   0x11800809420e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1054"            ,	   0x11800809420f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1055"            ,	   0x11800809420f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1056"            ,	   0x1180080942100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1057"            ,	   0x1180080942108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1058"            ,	   0x1180080942110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1059"            ,	   0x1180080942118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1060"            ,	   0x1180080942120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1061"            ,	   0x1180080942128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1062"            ,	   0x1180080942130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1063"            ,	   0x1180080942138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1064"            ,	   0x1180080942140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1065"            ,	   0x1180080942148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1066"            ,	   0x1180080942150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1067"            ,	   0x1180080942158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1068"            ,	   0x1180080942160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1069"            ,	   0x1180080942168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1070"            ,	   0x1180080942170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1071"            ,	   0x1180080942178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1072"            ,	   0x1180080942180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1073"            ,	   0x1180080942188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1074"            ,	   0x1180080942190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1075"            ,	   0x1180080942198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1076"            ,	   0x11800809421a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1077"            ,	   0x11800809421a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1078"            ,	   0x11800809421b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1079"            ,	   0x11800809421b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1080"            ,	   0x11800809421c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1081"            ,	   0x11800809421c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1082"            ,	   0x11800809421d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1083"            ,	   0x11800809421d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1084"            ,	   0x11800809421e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1085"            ,	   0x11800809421e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1086"            ,	   0x11800809421f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1087"            ,	   0x11800809421f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1088"            ,	   0x1180080942200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1089"            ,	   0x1180080942208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1090"            ,	   0x1180080942210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1091"            ,	   0x1180080942218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1092"            ,	   0x1180080942220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1093"            ,	   0x1180080942228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1094"            ,	   0x1180080942230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1095"            ,	   0x1180080942238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1096"            ,	   0x1180080942240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1097"            ,	   0x1180080942248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1098"            ,	   0x1180080942250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1099"            ,	   0x1180080942258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1100"            ,	   0x1180080942260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1101"            ,	   0x1180080942268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1102"            ,	   0x1180080942270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1103"            ,	   0x1180080942278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1104"            ,	   0x1180080942280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1105"            ,	   0x1180080942288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1106"            ,	   0x1180080942290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1107"            ,	   0x1180080942298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1108"            ,	   0x11800809422a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1109"            ,	   0x11800809422a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1110"            ,	   0x11800809422b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1111"            ,	   0x11800809422b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1112"            ,	   0x11800809422c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1113"            ,	   0x11800809422c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1114"            ,	   0x11800809422d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1115"            ,	   0x11800809422d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1116"            ,	   0x11800809422e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1117"            ,	   0x11800809422e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1118"            ,	   0x11800809422f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1119"            ,	   0x11800809422f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1120"            ,	   0x1180080942300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1121"            ,	   0x1180080942308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1122"            ,	   0x1180080942310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1123"            ,	   0x1180080942318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1124"            ,	   0x1180080942320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1125"            ,	   0x1180080942328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1126"            ,	   0x1180080942330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1127"            ,	   0x1180080942338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1128"            ,	   0x1180080942340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1129"            ,	   0x1180080942348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1130"            ,	   0x1180080942350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1131"            ,	   0x1180080942358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1132"            ,	   0x1180080942360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1133"            ,	   0x1180080942368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1134"            ,	   0x1180080942370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1135"            ,	   0x1180080942378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1136"            ,	   0x1180080942380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1137"            ,	   0x1180080942388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1138"            ,	   0x1180080942390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1139"            ,	   0x1180080942398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1140"            ,	   0x11800809423a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1141"            ,	   0x11800809423a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1142"            ,	   0x11800809423b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1143"            ,	   0x11800809423b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1144"            ,	   0x11800809423c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1145"            ,	   0x11800809423c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1146"            ,	   0x11800809423d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1147"            ,	   0x11800809423d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1148"            ,	   0x11800809423e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1149"            ,	   0x11800809423e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1150"            ,	   0x11800809423f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1151"            ,	   0x11800809423f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1152"            ,	   0x1180080942400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1153"            ,	   0x1180080942408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1154"            ,	   0x1180080942410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1155"            ,	   0x1180080942418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1156"            ,	   0x1180080942420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1157"            ,	   0x1180080942428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1158"            ,	   0x1180080942430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1159"            ,	   0x1180080942438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1160"            ,	   0x1180080942440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1161"            ,	   0x1180080942448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1162"            ,	   0x1180080942450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1163"            ,	   0x1180080942458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1164"            ,	   0x1180080942460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1165"            ,	   0x1180080942468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1166"            ,	   0x1180080942470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1167"            ,	   0x1180080942478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1168"            ,	   0x1180080942480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1169"            ,	   0x1180080942488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1170"            ,	   0x1180080942490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1171"            ,	   0x1180080942498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1172"            ,	   0x11800809424a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1173"            ,	   0x11800809424a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1174"            ,	   0x11800809424b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1175"            ,	   0x11800809424b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1176"            ,	   0x11800809424c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1177"            ,	   0x11800809424c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1178"            ,	   0x11800809424d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1179"            ,	   0x11800809424d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1180"            ,	   0x11800809424e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1181"            ,	   0x11800809424e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1182"            ,	   0x11800809424f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1183"            ,	   0x11800809424f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1184"            ,	   0x1180080942500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1185"            ,	   0x1180080942508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1186"            ,	   0x1180080942510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1187"            ,	   0x1180080942518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1188"            ,	   0x1180080942520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1189"            ,	   0x1180080942528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1190"            ,	   0x1180080942530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1191"            ,	   0x1180080942538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1192"            ,	   0x1180080942540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1193"            ,	   0x1180080942548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1194"            ,	   0x1180080942550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1195"            ,	   0x1180080942558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1196"            ,	   0x1180080942560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1197"            ,	   0x1180080942568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1198"            ,	   0x1180080942570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1199"            ,	   0x1180080942578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1200"            ,	   0x1180080942580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1201"            ,	   0x1180080942588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1202"            ,	   0x1180080942590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1203"            ,	   0x1180080942598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1204"            ,	   0x11800809425a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1205"            ,	   0x11800809425a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1206"            ,	   0x11800809425b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1207"            ,	   0x11800809425b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1208"            ,	   0x11800809425c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1209"            ,	   0x11800809425c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1210"            ,	   0x11800809425d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1211"            ,	   0x11800809425d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1212"            ,	   0x11800809425e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1213"            ,	   0x11800809425e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1214"            ,	   0x11800809425f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1215"            ,	   0x11800809425f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1216"            ,	   0x1180080942600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1217"            ,	   0x1180080942608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1218"            ,	   0x1180080942610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1219"            ,	   0x1180080942618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1220"            ,	   0x1180080942620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1221"            ,	   0x1180080942628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1222"            ,	   0x1180080942630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1223"            ,	   0x1180080942638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1224"            ,	   0x1180080942640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1225"            ,	   0x1180080942648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1226"            ,	   0x1180080942650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1227"            ,	   0x1180080942658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1228"            ,	   0x1180080942660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1229"            ,	   0x1180080942668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1230"            ,	   0x1180080942670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1231"            ,	   0x1180080942678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1232"            ,	   0x1180080942680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1233"            ,	   0x1180080942688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1234"            ,	   0x1180080942690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1235"            ,	   0x1180080942698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1236"            ,	   0x11800809426a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1237"            ,	   0x11800809426a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1238"            ,	   0x11800809426b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1239"            ,	   0x11800809426b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1240"            ,	   0x11800809426c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1241"            ,	   0x11800809426c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1242"            ,	   0x11800809426d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1243"            ,	   0x11800809426d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1244"            ,	   0x11800809426e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1245"            ,	   0x11800809426e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1246"            ,	   0x11800809426f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1247"            ,	   0x11800809426f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1248"            ,	   0x1180080942700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1249"            ,	   0x1180080942708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1250"            ,	   0x1180080942710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1251"            ,	   0x1180080942718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1252"            ,	   0x1180080942720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1253"            ,	   0x1180080942728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1254"            ,	   0x1180080942730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1255"            ,	   0x1180080942738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1256"            ,	   0x1180080942740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1257"            ,	   0x1180080942748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1258"            ,	   0x1180080942750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1259"            ,	   0x1180080942758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1260"            ,	   0x1180080942760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1261"            ,	   0x1180080942768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1262"            ,	   0x1180080942770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1263"            ,	   0x1180080942778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1264"            ,	   0x1180080942780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1265"            ,	   0x1180080942788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1266"            ,	   0x1180080942790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1267"            ,	   0x1180080942798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1268"            ,	   0x11800809427a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1269"            ,	   0x11800809427a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1270"            ,	   0x11800809427b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1271"            ,	   0x11800809427b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1272"            ,	   0x11800809427c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1273"            ,	   0x11800809427c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1274"            ,	   0x11800809427d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1275"            ,	   0x11800809427d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1276"            ,	   0x11800809427e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1277"            ,	   0x11800809427e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1278"            ,	   0x11800809427f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1279"            ,	   0x11800809427f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1280"            ,	   0x1180080942800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1281"            ,	   0x1180080942808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1282"            ,	   0x1180080942810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1283"            ,	   0x1180080942818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1284"            ,	   0x1180080942820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1285"            ,	   0x1180080942828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1286"            ,	   0x1180080942830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1287"            ,	   0x1180080942838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1288"            ,	   0x1180080942840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1289"            ,	   0x1180080942848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1290"            ,	   0x1180080942850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1291"            ,	   0x1180080942858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1292"            ,	   0x1180080942860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1293"            ,	   0x1180080942868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1294"            ,	   0x1180080942870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1295"            ,	   0x1180080942878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1296"            ,	   0x1180080942880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1297"            ,	   0x1180080942888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1298"            ,	   0x1180080942890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1299"            ,	   0x1180080942898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1300"            ,	   0x11800809428a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1301"            ,	   0x11800809428a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1302"            ,	   0x11800809428b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1303"            ,	   0x11800809428b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1304"            ,	   0x11800809428c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1305"            ,	   0x11800809428c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1306"            ,	   0x11800809428d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1307"            ,	   0x11800809428d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1308"            ,	   0x11800809428e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1309"            ,	   0x11800809428e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1310"            ,	   0x11800809428f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1311"            ,	   0x11800809428f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1312"            ,	   0x1180080942900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1313"            ,	   0x1180080942908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1314"            ,	   0x1180080942910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1315"            ,	   0x1180080942918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1316"            ,	   0x1180080942920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1317"            ,	   0x1180080942928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1318"            ,	   0x1180080942930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1319"            ,	   0x1180080942938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1320"            ,	   0x1180080942940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1321"            ,	   0x1180080942948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1322"            ,	   0x1180080942950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1323"            ,	   0x1180080942958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1324"            ,	   0x1180080942960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1325"            ,	   0x1180080942968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1326"            ,	   0x1180080942970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1327"            ,	   0x1180080942978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1328"            ,	   0x1180080942980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1329"            ,	   0x1180080942988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1330"            ,	   0x1180080942990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1331"            ,	   0x1180080942998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1332"            ,	   0x11800809429a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1333"            ,	   0x11800809429a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1334"            ,	   0x11800809429b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1335"            ,	   0x11800809429b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1336"            ,	   0x11800809429c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1337"            ,	   0x11800809429c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1338"            ,	   0x11800809429d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1339"            ,	   0x11800809429d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1340"            ,	   0x11800809429e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1341"            ,	   0x11800809429e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1342"            ,	   0x11800809429f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1343"            ,	   0x11800809429f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1344"            ,	   0x1180080942a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1345"            ,	   0x1180080942a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1346"            ,	   0x1180080942a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1347"            ,	   0x1180080942a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1348"            ,	   0x1180080942a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1349"            ,	   0x1180080942a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1350"            ,	   0x1180080942a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1351"            ,	   0x1180080942a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1352"            ,	   0x1180080942a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1353"            ,	   0x1180080942a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1354"            ,	   0x1180080942a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1355"            ,	   0x1180080942a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1356"            ,	   0x1180080942a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1357"            ,	   0x1180080942a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1358"            ,	   0x1180080942a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1359"            ,	   0x1180080942a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1360"            ,	   0x1180080942a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1361"            ,	   0x1180080942a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1362"            ,	   0x1180080942a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1363"            ,	   0x1180080942a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1364"            ,	   0x1180080942aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1365"            ,	   0x1180080942aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1366"            ,	   0x1180080942ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1367"            ,	   0x1180080942ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1368"            ,	   0x1180080942ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1369"            ,	   0x1180080942ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1370"            ,	   0x1180080942ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1371"            ,	   0x1180080942ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1372"            ,	   0x1180080942ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1373"            ,	   0x1180080942ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1374"            ,	   0x1180080942af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1375"            ,	   0x1180080942af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1376"            ,	   0x1180080942b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1377"            ,	   0x1180080942b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1378"            ,	   0x1180080942b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1379"            ,	   0x1180080942b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1380"            ,	   0x1180080942b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1381"            ,	   0x1180080942b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1382"            ,	   0x1180080942b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1383"            ,	   0x1180080942b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1384"            ,	   0x1180080942b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1385"            ,	   0x1180080942b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1386"            ,	   0x1180080942b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1387"            ,	   0x1180080942b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1388"            ,	   0x1180080942b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1389"            ,	   0x1180080942b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1390"            ,	   0x1180080942b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1391"            ,	   0x1180080942b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1392"            ,	   0x1180080942b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1393"            ,	   0x1180080942b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1394"            ,	   0x1180080942b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1395"            ,	   0x1180080942b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1396"            ,	   0x1180080942ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1397"            ,	   0x1180080942ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1398"            ,	   0x1180080942bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1399"            ,	   0x1180080942bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1400"            ,	   0x1180080942bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1401"            ,	   0x1180080942bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1402"            ,	   0x1180080942bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1403"            ,	   0x1180080942bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1404"            ,	   0x1180080942be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1405"            ,	   0x1180080942be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1406"            ,	   0x1180080942bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1407"            ,	   0x1180080942bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1408"            ,	   0x1180080942c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1409"            ,	   0x1180080942c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1410"            ,	   0x1180080942c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1411"            ,	   0x1180080942c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1412"            ,	   0x1180080942c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1413"            ,	   0x1180080942c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1414"            ,	   0x1180080942c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1415"            ,	   0x1180080942c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1416"            ,	   0x1180080942c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1417"            ,	   0x1180080942c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1418"            ,	   0x1180080942c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1419"            ,	   0x1180080942c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1420"            ,	   0x1180080942c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1421"            ,	   0x1180080942c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1422"            ,	   0x1180080942c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1423"            ,	   0x1180080942c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1424"            ,	   0x1180080942c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1425"            ,	   0x1180080942c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1426"            ,	   0x1180080942c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1427"            ,	   0x1180080942c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1428"            ,	   0x1180080942ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1429"            ,	   0x1180080942ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1430"            ,	   0x1180080942cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1431"            ,	   0x1180080942cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1432"            ,	   0x1180080942cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1433"            ,	   0x1180080942cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1434"            ,	   0x1180080942cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1435"            ,	   0x1180080942cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1436"            ,	   0x1180080942ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1437"            ,	   0x1180080942ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1438"            ,	   0x1180080942cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1439"            ,	   0x1180080942cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1440"            ,	   0x1180080942d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1441"            ,	   0x1180080942d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1442"            ,	   0x1180080942d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1443"            ,	   0x1180080942d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1444"            ,	   0x1180080942d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1445"            ,	   0x1180080942d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1446"            ,	   0x1180080942d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1447"            ,	   0x1180080942d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1448"            ,	   0x1180080942d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1449"            ,	   0x1180080942d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1450"            ,	   0x1180080942d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1451"            ,	   0x1180080942d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1452"            ,	   0x1180080942d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1453"            ,	   0x1180080942d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1454"            ,	   0x1180080942d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1455"            ,	   0x1180080942d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1456"            ,	   0x1180080942d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1457"            ,	   0x1180080942d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1458"            ,	   0x1180080942d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1459"            ,	   0x1180080942d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1460"            ,	   0x1180080942da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1461"            ,	   0x1180080942da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1462"            ,	   0x1180080942db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1463"            ,	   0x1180080942db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1464"            ,	   0x1180080942dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1465"            ,	   0x1180080942dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1466"            ,	   0x1180080942dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1467"            ,	   0x1180080942dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1468"            ,	   0x1180080942de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1469"            ,	   0x1180080942de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1470"            ,	   0x1180080942df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1471"            ,	   0x1180080942df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1472"            ,	   0x1180080942e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1473"            ,	   0x1180080942e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1474"            ,	   0x1180080942e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1475"            ,	   0x1180080942e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1476"            ,	   0x1180080942e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1477"            ,	   0x1180080942e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1478"            ,	   0x1180080942e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1479"            ,	   0x1180080942e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1480"            ,	   0x1180080942e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1481"            ,	   0x1180080942e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1482"            ,	   0x1180080942e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1483"            ,	   0x1180080942e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1484"            ,	   0x1180080942e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1485"            ,	   0x1180080942e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1486"            ,	   0x1180080942e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1487"            ,	   0x1180080942e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1488"            ,	   0x1180080942e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1489"            ,	   0x1180080942e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1490"            ,	   0x1180080942e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1491"            ,	   0x1180080942e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1492"            ,	   0x1180080942ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1493"            ,	   0x1180080942ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1494"            ,	   0x1180080942eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1495"            ,	   0x1180080942eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1496"            ,	   0x1180080942ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1497"            ,	   0x1180080942ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1498"            ,	   0x1180080942ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1499"            ,	   0x1180080942ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1500"            ,	   0x1180080942ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1501"            ,	   0x1180080942ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1502"            ,	   0x1180080942ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1503"            ,	   0x1180080942ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1504"            ,	   0x1180080942f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1505"            ,	   0x1180080942f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1506"            ,	   0x1180080942f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1507"            ,	   0x1180080942f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1508"            ,	   0x1180080942f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1509"            ,	   0x1180080942f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1510"            ,	   0x1180080942f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1511"            ,	   0x1180080942f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1512"            ,	   0x1180080942f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1513"            ,	   0x1180080942f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1514"            ,	   0x1180080942f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1515"            ,	   0x1180080942f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1516"            ,	   0x1180080942f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1517"            ,	   0x1180080942f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1518"            ,	   0x1180080942f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1519"            ,	   0x1180080942f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1520"            ,	   0x1180080942f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1521"            ,	   0x1180080942f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1522"            ,	   0x1180080942f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1523"            ,	   0x1180080942f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1524"            ,	   0x1180080942fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1525"            ,	   0x1180080942fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1526"            ,	   0x1180080942fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1527"            ,	   0x1180080942fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1528"            ,	   0x1180080942fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1529"            ,	   0x1180080942fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1530"            ,	   0x1180080942fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1531"            ,	   0x1180080942fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1532"            ,	   0x1180080942fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1533"            ,	   0x1180080942fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1534"            ,	   0x1180080942ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1535"            ,	   0x1180080942ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1536"            ,	   0x1180080943000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1537"            ,	   0x1180080943008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1538"            ,	   0x1180080943010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1539"            ,	   0x1180080943018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1540"            ,	   0x1180080943020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1541"            ,	   0x1180080943028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1542"            ,	   0x1180080943030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1543"            ,	   0x1180080943038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1544"            ,	   0x1180080943040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1545"            ,	   0x1180080943048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1546"            ,	   0x1180080943050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1547"            ,	   0x1180080943058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1548"            ,	   0x1180080943060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1549"            ,	   0x1180080943068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1550"            ,	   0x1180080943070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1551"            ,	   0x1180080943078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1552"            ,	   0x1180080943080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1553"            ,	   0x1180080943088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1554"            ,	   0x1180080943090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1555"            ,	   0x1180080943098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1556"            ,	   0x11800809430a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1557"            ,	   0x11800809430a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1558"            ,	   0x11800809430b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1559"            ,	   0x11800809430b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1560"            ,	   0x11800809430c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1561"            ,	   0x11800809430c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1562"            ,	   0x11800809430d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1563"            ,	   0x11800809430d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1564"            ,	   0x11800809430e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1565"            ,	   0x11800809430e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1566"            ,	   0x11800809430f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1567"            ,	   0x11800809430f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1568"            ,	   0x1180080943100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1569"            ,	   0x1180080943108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1570"            ,	   0x1180080943110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1571"            ,	   0x1180080943118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1572"            ,	   0x1180080943120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1573"            ,	   0x1180080943128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1574"            ,	   0x1180080943130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1575"            ,	   0x1180080943138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1576"            ,	   0x1180080943140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1577"            ,	   0x1180080943148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1578"            ,	   0x1180080943150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1579"            ,	   0x1180080943158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1580"            ,	   0x1180080943160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1581"            ,	   0x1180080943168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1582"            ,	   0x1180080943170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1583"            ,	   0x1180080943178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1584"            ,	   0x1180080943180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1585"            ,	   0x1180080943188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1586"            ,	   0x1180080943190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1587"            ,	   0x1180080943198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1588"            ,	   0x11800809431a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1589"            ,	   0x11800809431a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1590"            ,	   0x11800809431b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1591"            ,	   0x11800809431b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1592"            ,	   0x11800809431c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1593"            ,	   0x11800809431c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1594"            ,	   0x11800809431d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1595"            ,	   0x11800809431d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1596"            ,	   0x11800809431e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1597"            ,	   0x11800809431e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1598"            ,	   0x11800809431f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1599"            ,	   0x11800809431f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1600"            ,	   0x1180080943200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1601"            ,	   0x1180080943208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1602"            ,	   0x1180080943210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1603"            ,	   0x1180080943218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1604"            ,	   0x1180080943220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1605"            ,	   0x1180080943228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1606"            ,	   0x1180080943230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1607"            ,	   0x1180080943238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1608"            ,	   0x1180080943240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1609"            ,	   0x1180080943248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1610"            ,	   0x1180080943250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1611"            ,	   0x1180080943258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1612"            ,	   0x1180080943260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1613"            ,	   0x1180080943268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1614"            ,	   0x1180080943270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1615"            ,	   0x1180080943278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1616"            ,	   0x1180080943280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1617"            ,	   0x1180080943288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1618"            ,	   0x1180080943290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1619"            ,	   0x1180080943298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1620"            ,	   0x11800809432a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1621"            ,	   0x11800809432a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1622"            ,	   0x11800809432b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1623"            ,	   0x11800809432b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1624"            ,	   0x11800809432c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1625"            ,	   0x11800809432c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1626"            ,	   0x11800809432d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1627"            ,	   0x11800809432d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1628"            ,	   0x11800809432e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1629"            ,	   0x11800809432e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1630"            ,	   0x11800809432f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1631"            ,	   0x11800809432f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1632"            ,	   0x1180080943300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1633"            ,	   0x1180080943308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1634"            ,	   0x1180080943310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1635"            ,	   0x1180080943318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1636"            ,	   0x1180080943320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1637"            ,	   0x1180080943328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1638"            ,	   0x1180080943330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1639"            ,	   0x1180080943338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1640"            ,	   0x1180080943340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1641"            ,	   0x1180080943348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1642"            ,	   0x1180080943350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1643"            ,	   0x1180080943358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1644"            ,	   0x1180080943360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1645"            ,	   0x1180080943368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1646"            ,	   0x1180080943370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1647"            ,	   0x1180080943378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1648"            ,	   0x1180080943380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1649"            ,	   0x1180080943388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1650"            ,	   0x1180080943390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1651"            ,	   0x1180080943398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1652"            ,	   0x11800809433a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1653"            ,	   0x11800809433a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1654"            ,	   0x11800809433b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1655"            ,	   0x11800809433b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1656"            ,	   0x11800809433c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1657"            ,	   0x11800809433c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1658"            ,	   0x11800809433d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1659"            ,	   0x11800809433d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1660"            ,	   0x11800809433e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1661"            ,	   0x11800809433e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1662"            ,	   0x11800809433f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1663"            ,	   0x11800809433f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1664"            ,	   0x1180080943400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1665"            ,	   0x1180080943408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1666"            ,	   0x1180080943410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1667"            ,	   0x1180080943418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1668"            ,	   0x1180080943420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1669"            ,	   0x1180080943428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1670"            ,	   0x1180080943430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1671"            ,	   0x1180080943438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1672"            ,	   0x1180080943440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1673"            ,	   0x1180080943448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1674"            ,	   0x1180080943450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1675"            ,	   0x1180080943458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1676"            ,	   0x1180080943460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1677"            ,	   0x1180080943468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1678"            ,	   0x1180080943470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1679"            ,	   0x1180080943478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1680"            ,	   0x1180080943480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1681"            ,	   0x1180080943488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1682"            ,	   0x1180080943490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1683"            ,	   0x1180080943498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1684"            ,	   0x11800809434a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1685"            ,	   0x11800809434a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1686"            ,	   0x11800809434b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1687"            ,	   0x11800809434b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1688"            ,	   0x11800809434c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1689"            ,	   0x11800809434c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1690"            ,	   0x11800809434d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1691"            ,	   0x11800809434d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1692"            ,	   0x11800809434e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1693"            ,	   0x11800809434e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1694"            ,	   0x11800809434f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1695"            ,	   0x11800809434f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1696"            ,	   0x1180080943500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1697"            ,	   0x1180080943508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1698"            ,	   0x1180080943510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1699"            ,	   0x1180080943518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1700"            ,	   0x1180080943520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1701"            ,	   0x1180080943528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1702"            ,	   0x1180080943530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1703"            ,	   0x1180080943538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1704"            ,	   0x1180080943540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1705"            ,	   0x1180080943548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1706"            ,	   0x1180080943550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1707"            ,	   0x1180080943558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1708"            ,	   0x1180080943560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1709"            ,	   0x1180080943568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1710"            ,	   0x1180080943570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1711"            ,	   0x1180080943578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1712"            ,	   0x1180080943580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1713"            ,	   0x1180080943588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1714"            ,	   0x1180080943590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1715"            ,	   0x1180080943598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1716"            ,	   0x11800809435a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1717"            ,	   0x11800809435a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1718"            ,	   0x11800809435b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1719"            ,	   0x11800809435b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1720"            ,	   0x11800809435c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1721"            ,	   0x11800809435c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1722"            ,	   0x11800809435d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1723"            ,	   0x11800809435d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1724"            ,	   0x11800809435e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1725"            ,	   0x11800809435e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1726"            ,	   0x11800809435f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1727"            ,	   0x11800809435f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1728"            ,	   0x1180080943600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1729"            ,	   0x1180080943608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1730"            ,	   0x1180080943610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1731"            ,	   0x1180080943618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1732"            ,	   0x1180080943620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1733"            ,	   0x1180080943628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1734"            ,	   0x1180080943630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1735"            ,	   0x1180080943638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1736"            ,	   0x1180080943640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1737"            ,	   0x1180080943648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1738"            ,	   0x1180080943650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1739"            ,	   0x1180080943658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1740"            ,	   0x1180080943660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1741"            ,	   0x1180080943668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1742"            ,	   0x1180080943670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1743"            ,	   0x1180080943678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1744"            ,	   0x1180080943680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1745"            ,	   0x1180080943688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1746"            ,	   0x1180080943690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1747"            ,	   0x1180080943698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1748"            ,	   0x11800809436a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1749"            ,	   0x11800809436a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1750"            ,	   0x11800809436b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1751"            ,	   0x11800809436b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1752"            ,	   0x11800809436c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1753"            ,	   0x11800809436c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1754"            ,	   0x11800809436d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1755"            ,	   0x11800809436d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1756"            ,	   0x11800809436e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1757"            ,	   0x11800809436e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1758"            ,	   0x11800809436f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1759"            ,	   0x11800809436f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1760"            ,	   0x1180080943700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1761"            ,	   0x1180080943708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1762"            ,	   0x1180080943710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1763"            ,	   0x1180080943718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1764"            ,	   0x1180080943720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1765"            ,	   0x1180080943728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1766"            ,	   0x1180080943730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1767"            ,	   0x1180080943738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1768"            ,	   0x1180080943740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1769"            ,	   0x1180080943748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1770"            ,	   0x1180080943750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1771"            ,	   0x1180080943758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1772"            ,	   0x1180080943760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1773"            ,	   0x1180080943768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1774"            ,	   0x1180080943770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1775"            ,	   0x1180080943778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1776"            ,	   0x1180080943780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1777"            ,	   0x1180080943788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1778"            ,	   0x1180080943790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1779"            ,	   0x1180080943798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1780"            ,	   0x11800809437a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1781"            ,	   0x11800809437a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1782"            ,	   0x11800809437b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1783"            ,	   0x11800809437b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1784"            ,	   0x11800809437c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1785"            ,	   0x11800809437c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1786"            ,	   0x11800809437d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1787"            ,	   0x11800809437d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1788"            ,	   0x11800809437e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1789"            ,	   0x11800809437e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1790"            ,	   0x11800809437f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1791"            ,	   0x11800809437f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1792"            ,	   0x1180080943800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1793"            ,	   0x1180080943808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1794"            ,	   0x1180080943810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1795"            ,	   0x1180080943818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1796"            ,	   0x1180080943820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1797"            ,	   0x1180080943828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1798"            ,	   0x1180080943830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1799"            ,	   0x1180080943838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1800"            ,	   0x1180080943840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1801"            ,	   0x1180080943848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1802"            ,	   0x1180080943850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1803"            ,	   0x1180080943858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1804"            ,	   0x1180080943860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1805"            ,	   0x1180080943868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1806"            ,	   0x1180080943870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1807"            ,	   0x1180080943878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1808"            ,	   0x1180080943880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1809"            ,	   0x1180080943888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1810"            ,	   0x1180080943890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1811"            ,	   0x1180080943898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1812"            ,	   0x11800809438a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1813"            ,	   0x11800809438a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1814"            ,	   0x11800809438b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1815"            ,	   0x11800809438b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1816"            ,	   0x11800809438c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1817"            ,	   0x11800809438c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1818"            ,	   0x11800809438d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1819"            ,	   0x11800809438d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1820"            ,	   0x11800809438e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1821"            ,	   0x11800809438e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1822"            ,	   0x11800809438f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1823"            ,	   0x11800809438f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1824"            ,	   0x1180080943900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1825"            ,	   0x1180080943908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1826"            ,	   0x1180080943910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1827"            ,	   0x1180080943918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1828"            ,	   0x1180080943920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1829"            ,	   0x1180080943928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1830"            ,	   0x1180080943930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1831"            ,	   0x1180080943938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1832"            ,	   0x1180080943940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1833"            ,	   0x1180080943948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1834"            ,	   0x1180080943950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1835"            ,	   0x1180080943958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1836"            ,	   0x1180080943960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1837"            ,	   0x1180080943968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1838"            ,	   0x1180080943970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1839"            ,	   0x1180080943978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1840"            ,	   0x1180080943980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1841"            ,	   0x1180080943988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1842"            ,	   0x1180080943990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1843"            ,	   0x1180080943998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1844"            ,	   0x11800809439a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1845"            ,	   0x11800809439a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1846"            ,	   0x11800809439b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1847"            ,	   0x11800809439b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1848"            ,	   0x11800809439c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1849"            ,	   0x11800809439c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1850"            ,	   0x11800809439d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1851"            ,	   0x11800809439d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1852"            ,	   0x11800809439e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1853"            ,	   0x11800809439e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1854"            ,	   0x11800809439f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1855"            ,	   0x11800809439f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1856"            ,	   0x1180080943a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1857"            ,	   0x1180080943a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1858"            ,	   0x1180080943a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1859"            ,	   0x1180080943a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1860"            ,	   0x1180080943a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1861"            ,	   0x1180080943a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1862"            ,	   0x1180080943a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1863"            ,	   0x1180080943a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1864"            ,	   0x1180080943a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1865"            ,	   0x1180080943a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1866"            ,	   0x1180080943a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1867"            ,	   0x1180080943a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1868"            ,	   0x1180080943a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1869"            ,	   0x1180080943a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1870"            ,	   0x1180080943a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1871"            ,	   0x1180080943a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1872"            ,	   0x1180080943a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1873"            ,	   0x1180080943a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1874"            ,	   0x1180080943a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1875"            ,	   0x1180080943a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1876"            ,	   0x1180080943aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1877"            ,	   0x1180080943aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1878"            ,	   0x1180080943ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1879"            ,	   0x1180080943ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1880"            ,	   0x1180080943ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1881"            ,	   0x1180080943ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1882"            ,	   0x1180080943ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1883"            ,	   0x1180080943ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1884"            ,	   0x1180080943ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1885"            ,	   0x1180080943ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1886"            ,	   0x1180080943af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1887"            ,	   0x1180080943af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1888"            ,	   0x1180080943b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1889"            ,	   0x1180080943b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1890"            ,	   0x1180080943b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1891"            ,	   0x1180080943b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1892"            ,	   0x1180080943b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1893"            ,	   0x1180080943b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1894"            ,	   0x1180080943b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1895"            ,	   0x1180080943b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1896"            ,	   0x1180080943b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1897"            ,	   0x1180080943b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1898"            ,	   0x1180080943b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1899"            ,	   0x1180080943b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1900"            ,	   0x1180080943b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1901"            ,	   0x1180080943b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1902"            ,	   0x1180080943b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1903"            ,	   0x1180080943b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1904"            ,	   0x1180080943b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1905"            ,	   0x1180080943b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1906"            ,	   0x1180080943b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1907"            ,	   0x1180080943b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1908"            ,	   0x1180080943ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1909"            ,	   0x1180080943ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1910"            ,	   0x1180080943bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1911"            ,	   0x1180080943bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1912"            ,	   0x1180080943bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1913"            ,	   0x1180080943bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1914"            ,	   0x1180080943bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1915"            ,	   0x1180080943bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1916"            ,	   0x1180080943be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1917"            ,	   0x1180080943be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1918"            ,	   0x1180080943bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1919"            ,	   0x1180080943bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1920"            ,	   0x1180080943c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1921"            ,	   0x1180080943c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1922"            ,	   0x1180080943c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1923"            ,	   0x1180080943c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1924"            ,	   0x1180080943c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1925"            ,	   0x1180080943c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1926"            ,	   0x1180080943c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1927"            ,	   0x1180080943c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1928"            ,	   0x1180080943c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1929"            ,	   0x1180080943c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1930"            ,	   0x1180080943c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1931"            ,	   0x1180080943c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1932"            ,	   0x1180080943c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1933"            ,	   0x1180080943c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1934"            ,	   0x1180080943c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1935"            ,	   0x1180080943c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1936"            ,	   0x1180080943c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1937"            ,	   0x1180080943c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1938"            ,	   0x1180080943c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1939"            ,	   0x1180080943c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1940"            ,	   0x1180080943ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1941"            ,	   0x1180080943ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1942"            ,	   0x1180080943cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1943"            ,	   0x1180080943cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1944"            ,	   0x1180080943cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1945"            ,	   0x1180080943cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1946"            ,	   0x1180080943cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1947"            ,	   0x1180080943cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1948"            ,	   0x1180080943ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1949"            ,	   0x1180080943ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1950"            ,	   0x1180080943cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1951"            ,	   0x1180080943cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1952"            ,	   0x1180080943d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1953"            ,	   0x1180080943d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1954"            ,	   0x1180080943d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1955"            ,	   0x1180080943d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1956"            ,	   0x1180080943d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1957"            ,	   0x1180080943d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1958"            ,	   0x1180080943d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1959"            ,	   0x1180080943d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1960"            ,	   0x1180080943d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1961"            ,	   0x1180080943d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1962"            ,	   0x1180080943d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1963"            ,	   0x1180080943d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1964"            ,	   0x1180080943d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1965"            ,	   0x1180080943d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1966"            ,	   0x1180080943d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1967"            ,	   0x1180080943d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1968"            ,	   0x1180080943d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1969"            ,	   0x1180080943d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1970"            ,	   0x1180080943d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1971"            ,	   0x1180080943d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1972"            ,	   0x1180080943da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1973"            ,	   0x1180080943da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1974"            ,	   0x1180080943db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1975"            ,	   0x1180080943db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1976"            ,	   0x1180080943dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1977"            ,	   0x1180080943dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1978"            ,	   0x1180080943dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1979"            ,	   0x1180080943dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1980"            ,	   0x1180080943de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1981"            ,	   0x1180080943de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1982"            ,	   0x1180080943df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1983"            ,	   0x1180080943df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1984"            ,	   0x1180080943e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1985"            ,	   0x1180080943e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1986"            ,	   0x1180080943e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1987"            ,	   0x1180080943e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1988"            ,	   0x1180080943e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1989"            ,	   0x1180080943e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1990"            ,	   0x1180080943e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1991"            ,	   0x1180080943e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1992"            ,	   0x1180080943e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1993"            ,	   0x1180080943e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1994"            ,	   0x1180080943e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1995"            ,	   0x1180080943e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1996"            ,	   0x1180080943e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1997"            ,	   0x1180080943e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1998"            ,	   0x1180080943e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP1999"            ,	   0x1180080943e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2000"            ,	   0x1180080943e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2001"            ,	   0x1180080943e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2002"            ,	   0x1180080943e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2003"            ,	   0x1180080943e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2004"            ,	   0x1180080943ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2005"            ,	   0x1180080943ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2006"            ,	   0x1180080943eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2007"            ,	   0x1180080943eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2008"            ,	   0x1180080943ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2009"            ,	   0x1180080943ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2010"            ,	   0x1180080943ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2011"            ,	   0x1180080943ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2012"            ,	   0x1180080943ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2013"            ,	   0x1180080943ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2014"            ,	   0x1180080943ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2015"            ,	   0x1180080943ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2016"            ,	   0x1180080943f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2017"            ,	   0x1180080943f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2018"            ,	   0x1180080943f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2019"            ,	   0x1180080943f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2020"            ,	   0x1180080943f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2021"            ,	   0x1180080943f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2022"            ,	   0x1180080943f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2023"            ,	   0x1180080943f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2024"            ,	   0x1180080943f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2025"            ,	   0x1180080943f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2026"            ,	   0x1180080943f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2027"            ,	   0x1180080943f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2028"            ,	   0x1180080943f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2029"            ,	   0x1180080943f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2030"            ,	   0x1180080943f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2031"            ,	   0x1180080943f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2032"            ,	   0x1180080943f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2033"            ,	   0x1180080943f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2034"            ,	   0x1180080943f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2035"            ,	   0x1180080943f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2036"            ,	   0x1180080943fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2037"            ,	   0x1180080943fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2038"            ,	   0x1180080943fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2039"            ,	   0x1180080943fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2040"            ,	   0x1180080943fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2041"            ,	   0x1180080943fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2042"            ,	   0x1180080943fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2043"            ,	   0x1180080943fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2044"            ,	   0x1180080943fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2045"            ,	   0x1180080943fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2046"            ,	   0x1180080943ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2047"            ,	   0x1180080943ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2048"            ,	   0x1180080944000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2049"            ,	   0x1180080944008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2050"            ,	   0x1180080944010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2051"            ,	   0x1180080944018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2052"            ,	   0x1180080944020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2053"            ,	   0x1180080944028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2054"            ,	   0x1180080944030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2055"            ,	   0x1180080944038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2056"            ,	   0x1180080944040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2057"            ,	   0x1180080944048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2058"            ,	   0x1180080944050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2059"            ,	   0x1180080944058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2060"            ,	   0x1180080944060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2061"            ,	   0x1180080944068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2062"            ,	   0x1180080944070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2063"            ,	   0x1180080944078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2064"            ,	   0x1180080944080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2065"            ,	   0x1180080944088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2066"            ,	   0x1180080944090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2067"            ,	   0x1180080944098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2068"            ,	   0x11800809440a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2069"            ,	   0x11800809440a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2070"            ,	   0x11800809440b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2071"            ,	   0x11800809440b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2072"            ,	   0x11800809440c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2073"            ,	   0x11800809440c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2074"            ,	   0x11800809440d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2075"            ,	   0x11800809440d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2076"            ,	   0x11800809440e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2077"            ,	   0x11800809440e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2078"            ,	   0x11800809440f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2079"            ,	   0x11800809440f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2080"            ,	   0x1180080944100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2081"            ,	   0x1180080944108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2082"            ,	   0x1180080944110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2083"            ,	   0x1180080944118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2084"            ,	   0x1180080944120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2085"            ,	   0x1180080944128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2086"            ,	   0x1180080944130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2087"            ,	   0x1180080944138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2088"            ,	   0x1180080944140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2089"            ,	   0x1180080944148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2090"            ,	   0x1180080944150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2091"            ,	   0x1180080944158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2092"            ,	   0x1180080944160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2093"            ,	   0x1180080944168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2094"            ,	   0x1180080944170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2095"            ,	   0x1180080944178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2096"            ,	   0x1180080944180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2097"            ,	   0x1180080944188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2098"            ,	   0x1180080944190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2099"            ,	   0x1180080944198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2100"            ,	   0x11800809441a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2101"            ,	   0x11800809441a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2102"            ,	   0x11800809441b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2103"            ,	   0x11800809441b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2104"            ,	   0x11800809441c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2105"            ,	   0x11800809441c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2106"            ,	   0x11800809441d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2107"            ,	   0x11800809441d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2108"            ,	   0x11800809441e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2109"            ,	   0x11800809441e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2110"            ,	   0x11800809441f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2111"            ,	   0x11800809441f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2112"            ,	   0x1180080944200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2113"            ,	   0x1180080944208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2114"            ,	   0x1180080944210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2115"            ,	   0x1180080944218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2116"            ,	   0x1180080944220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2117"            ,	   0x1180080944228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2118"            ,	   0x1180080944230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2119"            ,	   0x1180080944238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2120"            ,	   0x1180080944240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2121"            ,	   0x1180080944248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2122"            ,	   0x1180080944250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2123"            ,	   0x1180080944258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2124"            ,	   0x1180080944260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2125"            ,	   0x1180080944268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2126"            ,	   0x1180080944270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2127"            ,	   0x1180080944278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2128"            ,	   0x1180080944280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2129"            ,	   0x1180080944288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2130"            ,	   0x1180080944290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2131"            ,	   0x1180080944298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2132"            ,	   0x11800809442a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2133"            ,	   0x11800809442a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2134"            ,	   0x11800809442b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2135"            ,	   0x11800809442b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2136"            ,	   0x11800809442c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2137"            ,	   0x11800809442c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2138"            ,	   0x11800809442d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2139"            ,	   0x11800809442d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2140"            ,	   0x11800809442e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2141"            ,	   0x11800809442e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2142"            ,	   0x11800809442f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2143"            ,	   0x11800809442f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2144"            ,	   0x1180080944300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2145"            ,	   0x1180080944308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2146"            ,	   0x1180080944310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2147"            ,	   0x1180080944318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2148"            ,	   0x1180080944320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2149"            ,	   0x1180080944328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2150"            ,	   0x1180080944330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2151"            ,	   0x1180080944338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2152"            ,	   0x1180080944340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2153"            ,	   0x1180080944348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2154"            ,	   0x1180080944350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2155"            ,	   0x1180080944358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2156"            ,	   0x1180080944360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2157"            ,	   0x1180080944368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2158"            ,	   0x1180080944370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2159"            ,	   0x1180080944378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2160"            ,	   0x1180080944380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2161"            ,	   0x1180080944388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2162"            ,	   0x1180080944390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2163"            ,	   0x1180080944398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2164"            ,	   0x11800809443a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2165"            ,	   0x11800809443a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2166"            ,	   0x11800809443b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2167"            ,	   0x11800809443b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2168"            ,	   0x11800809443c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2169"            ,	   0x11800809443c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2170"            ,	   0x11800809443d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2171"            ,	   0x11800809443d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2172"            ,	   0x11800809443e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2173"            ,	   0x11800809443e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2174"            ,	   0x11800809443f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2175"            ,	   0x11800809443f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2176"            ,	   0x1180080944400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2177"            ,	   0x1180080944408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2178"            ,	   0x1180080944410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2179"            ,	   0x1180080944418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2180"            ,	   0x1180080944420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2181"            ,	   0x1180080944428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2182"            ,	   0x1180080944430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2183"            ,	   0x1180080944438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2184"            ,	   0x1180080944440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2185"            ,	   0x1180080944448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2186"            ,	   0x1180080944450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2187"            ,	   0x1180080944458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2188"            ,	   0x1180080944460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2189"            ,	   0x1180080944468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2190"            ,	   0x1180080944470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2191"            ,	   0x1180080944478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2192"            ,	   0x1180080944480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2193"            ,	   0x1180080944488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2194"            ,	   0x1180080944490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2195"            ,	   0x1180080944498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2196"            ,	   0x11800809444a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2197"            ,	   0x11800809444a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2198"            ,	   0x11800809444b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2199"            ,	   0x11800809444b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2200"            ,	   0x11800809444c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2201"            ,	   0x11800809444c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2202"            ,	   0x11800809444d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2203"            ,	   0x11800809444d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2204"            ,	   0x11800809444e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2205"            ,	   0x11800809444e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2206"            ,	   0x11800809444f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2207"            ,	   0x11800809444f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2208"            ,	   0x1180080944500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2209"            ,	   0x1180080944508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2210"            ,	   0x1180080944510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2211"            ,	   0x1180080944518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2212"            ,	   0x1180080944520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2213"            ,	   0x1180080944528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2214"            ,	   0x1180080944530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2215"            ,	   0x1180080944538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2216"            ,	   0x1180080944540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2217"            ,	   0x1180080944548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2218"            ,	   0x1180080944550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2219"            ,	   0x1180080944558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2220"            ,	   0x1180080944560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2221"            ,	   0x1180080944568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2222"            ,	   0x1180080944570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2223"            ,	   0x1180080944578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2224"            ,	   0x1180080944580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2225"            ,	   0x1180080944588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2226"            ,	   0x1180080944590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2227"            ,	   0x1180080944598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2228"            ,	   0x11800809445a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2229"            ,	   0x11800809445a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2230"            ,	   0x11800809445b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2231"            ,	   0x11800809445b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2232"            ,	   0x11800809445c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2233"            ,	   0x11800809445c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2234"            ,	   0x11800809445d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2235"            ,	   0x11800809445d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2236"            ,	   0x11800809445e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2237"            ,	   0x11800809445e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2238"            ,	   0x11800809445f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2239"            ,	   0x11800809445f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2240"            ,	   0x1180080944600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2241"            ,	   0x1180080944608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2242"            ,	   0x1180080944610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2243"            ,	   0x1180080944618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2244"            ,	   0x1180080944620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2245"            ,	   0x1180080944628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2246"            ,	   0x1180080944630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2247"            ,	   0x1180080944638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2248"            ,	   0x1180080944640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2249"            ,	   0x1180080944648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2250"            ,	   0x1180080944650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2251"            ,	   0x1180080944658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2252"            ,	   0x1180080944660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2253"            ,	   0x1180080944668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2254"            ,	   0x1180080944670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2255"            ,	   0x1180080944678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2256"            ,	   0x1180080944680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2257"            ,	   0x1180080944688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2258"            ,	   0x1180080944690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2259"            ,	   0x1180080944698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2260"            ,	   0x11800809446a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2261"            ,	   0x11800809446a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2262"            ,	   0x11800809446b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2263"            ,	   0x11800809446b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2264"            ,	   0x11800809446c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2265"            ,	   0x11800809446c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2266"            ,	   0x11800809446d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2267"            ,	   0x11800809446d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2268"            ,	   0x11800809446e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2269"            ,	   0x11800809446e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2270"            ,	   0x11800809446f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2271"            ,	   0x11800809446f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2272"            ,	   0x1180080944700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2273"            ,	   0x1180080944708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2274"            ,	   0x1180080944710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2275"            ,	   0x1180080944718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2276"            ,	   0x1180080944720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2277"            ,	   0x1180080944728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2278"            ,	   0x1180080944730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2279"            ,	   0x1180080944738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2280"            ,	   0x1180080944740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2281"            ,	   0x1180080944748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2282"            ,	   0x1180080944750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2283"            ,	   0x1180080944758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2284"            ,	   0x1180080944760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2285"            ,	   0x1180080944768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2286"            ,	   0x1180080944770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2287"            ,	   0x1180080944778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2288"            ,	   0x1180080944780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2289"            ,	   0x1180080944788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2290"            ,	   0x1180080944790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2291"            ,	   0x1180080944798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2292"            ,	   0x11800809447a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2293"            ,	   0x11800809447a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2294"            ,	   0x11800809447b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2295"            ,	   0x11800809447b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2296"            ,	   0x11800809447c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2297"            ,	   0x11800809447c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2298"            ,	   0x11800809447d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2299"            ,	   0x11800809447d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2300"            ,	   0x11800809447e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2301"            ,	   0x11800809447e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2302"            ,	   0x11800809447f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2303"            ,	   0x11800809447f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2304"            ,	   0x1180080944800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2305"            ,	   0x1180080944808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2306"            ,	   0x1180080944810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2307"            ,	   0x1180080944818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2308"            ,	   0x1180080944820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2309"            ,	   0x1180080944828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2310"            ,	   0x1180080944830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2311"            ,	   0x1180080944838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2312"            ,	   0x1180080944840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2313"            ,	   0x1180080944848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2314"            ,	   0x1180080944850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2315"            ,	   0x1180080944858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2316"            ,	   0x1180080944860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2317"            ,	   0x1180080944868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2318"            ,	   0x1180080944870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2319"            ,	   0x1180080944878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2320"            ,	   0x1180080944880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2321"            ,	   0x1180080944888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2322"            ,	   0x1180080944890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2323"            ,	   0x1180080944898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2324"            ,	   0x11800809448a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2325"            ,	   0x11800809448a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2326"            ,	   0x11800809448b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2327"            ,	   0x11800809448b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2328"            ,	   0x11800809448c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2329"            ,	   0x11800809448c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2330"            ,	   0x11800809448d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2331"            ,	   0x11800809448d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2332"            ,	   0x11800809448e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2333"            ,	   0x11800809448e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2334"            ,	   0x11800809448f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2335"            ,	   0x11800809448f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2336"            ,	   0x1180080944900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2337"            ,	   0x1180080944908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2338"            ,	   0x1180080944910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2339"            ,	   0x1180080944918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2340"            ,	   0x1180080944920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2341"            ,	   0x1180080944928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2342"            ,	   0x1180080944930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2343"            ,	   0x1180080944938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2344"            ,	   0x1180080944940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2345"            ,	   0x1180080944948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2346"            ,	   0x1180080944950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2347"            ,	   0x1180080944958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2348"            ,	   0x1180080944960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2349"            ,	   0x1180080944968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2350"            ,	   0x1180080944970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2351"            ,	   0x1180080944978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2352"            ,	   0x1180080944980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2353"            ,	   0x1180080944988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2354"            ,	   0x1180080944990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2355"            ,	   0x1180080944998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2356"            ,	   0x11800809449a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2357"            ,	   0x11800809449a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2358"            ,	   0x11800809449b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2359"            ,	   0x11800809449b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2360"            ,	   0x11800809449c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2361"            ,	   0x11800809449c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2362"            ,	   0x11800809449d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2363"            ,	   0x11800809449d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2364"            ,	   0x11800809449e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2365"            ,	   0x11800809449e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2366"            ,	   0x11800809449f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2367"            ,	   0x11800809449f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2368"            ,	   0x1180080944a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2369"            ,	   0x1180080944a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2370"            ,	   0x1180080944a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2371"            ,	   0x1180080944a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2372"            ,	   0x1180080944a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2373"            ,	   0x1180080944a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2374"            ,	   0x1180080944a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2375"            ,	   0x1180080944a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2376"            ,	   0x1180080944a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2377"            ,	   0x1180080944a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2378"            ,	   0x1180080944a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2379"            ,	   0x1180080944a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2380"            ,	   0x1180080944a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2381"            ,	   0x1180080944a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2382"            ,	   0x1180080944a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2383"            ,	   0x1180080944a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2384"            ,	   0x1180080944a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2385"            ,	   0x1180080944a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2386"            ,	   0x1180080944a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2387"            ,	   0x1180080944a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2388"            ,	   0x1180080944aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2389"            ,	   0x1180080944aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2390"            ,	   0x1180080944ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2391"            ,	   0x1180080944ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2392"            ,	   0x1180080944ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2393"            ,	   0x1180080944ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2394"            ,	   0x1180080944ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2395"            ,	   0x1180080944ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2396"            ,	   0x1180080944ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2397"            ,	   0x1180080944ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2398"            ,	   0x1180080944af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2399"            ,	   0x1180080944af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2400"            ,	   0x1180080944b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2401"            ,	   0x1180080944b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2402"            ,	   0x1180080944b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2403"            ,	   0x1180080944b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2404"            ,	   0x1180080944b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2405"            ,	   0x1180080944b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2406"            ,	   0x1180080944b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2407"            ,	   0x1180080944b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2408"            ,	   0x1180080944b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2409"            ,	   0x1180080944b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2410"            ,	   0x1180080944b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2411"            ,	   0x1180080944b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2412"            ,	   0x1180080944b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2413"            ,	   0x1180080944b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2414"            ,	   0x1180080944b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2415"            ,	   0x1180080944b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2416"            ,	   0x1180080944b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2417"            ,	   0x1180080944b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2418"            ,	   0x1180080944b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2419"            ,	   0x1180080944b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2420"            ,	   0x1180080944ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2421"            ,	   0x1180080944ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2422"            ,	   0x1180080944bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2423"            ,	   0x1180080944bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2424"            ,	   0x1180080944bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2425"            ,	   0x1180080944bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2426"            ,	   0x1180080944bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2427"            ,	   0x1180080944bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2428"            ,	   0x1180080944be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2429"            ,	   0x1180080944be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2430"            ,	   0x1180080944bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2431"            ,	   0x1180080944bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2432"            ,	   0x1180080944c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2433"            ,	   0x1180080944c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2434"            ,	   0x1180080944c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2435"            ,	   0x1180080944c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2436"            ,	   0x1180080944c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2437"            ,	   0x1180080944c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2438"            ,	   0x1180080944c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2439"            ,	   0x1180080944c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2440"            ,	   0x1180080944c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2441"            ,	   0x1180080944c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2442"            ,	   0x1180080944c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2443"            ,	   0x1180080944c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2444"            ,	   0x1180080944c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2445"            ,	   0x1180080944c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2446"            ,	   0x1180080944c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2447"            ,	   0x1180080944c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2448"            ,	   0x1180080944c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2449"            ,	   0x1180080944c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2450"            ,	   0x1180080944c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2451"            ,	   0x1180080944c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2452"            ,	   0x1180080944ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2453"            ,	   0x1180080944ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2454"            ,	   0x1180080944cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2455"            ,	   0x1180080944cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2456"            ,	   0x1180080944cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2457"            ,	   0x1180080944cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2458"            ,	   0x1180080944cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2459"            ,	   0x1180080944cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2460"            ,	   0x1180080944ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2461"            ,	   0x1180080944ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2462"            ,	   0x1180080944cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2463"            ,	   0x1180080944cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2464"            ,	   0x1180080944d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2465"            ,	   0x1180080944d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2466"            ,	   0x1180080944d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2467"            ,	   0x1180080944d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2468"            ,	   0x1180080944d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2469"            ,	   0x1180080944d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2470"            ,	   0x1180080944d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2471"            ,	   0x1180080944d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2472"            ,	   0x1180080944d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2473"            ,	   0x1180080944d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2474"            ,	   0x1180080944d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2475"            ,	   0x1180080944d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2476"            ,	   0x1180080944d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2477"            ,	   0x1180080944d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2478"            ,	   0x1180080944d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2479"            ,	   0x1180080944d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2480"            ,	   0x1180080944d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2481"            ,	   0x1180080944d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2482"            ,	   0x1180080944d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2483"            ,	   0x1180080944d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2484"            ,	   0x1180080944da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2485"            ,	   0x1180080944da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2486"            ,	   0x1180080944db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2487"            ,	   0x1180080944db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2488"            ,	   0x1180080944dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2489"            ,	   0x1180080944dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2490"            ,	   0x1180080944dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2491"            ,	   0x1180080944dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2492"            ,	   0x1180080944de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2493"            ,	   0x1180080944de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2494"            ,	   0x1180080944df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2495"            ,	   0x1180080944df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2496"            ,	   0x1180080944e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2497"            ,	   0x1180080944e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2498"            ,	   0x1180080944e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2499"            ,	   0x1180080944e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2500"            ,	   0x1180080944e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2501"            ,	   0x1180080944e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2502"            ,	   0x1180080944e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2503"            ,	   0x1180080944e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2504"            ,	   0x1180080944e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2505"            ,	   0x1180080944e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2506"            ,	   0x1180080944e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2507"            ,	   0x1180080944e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2508"            ,	   0x1180080944e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2509"            ,	   0x1180080944e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2510"            ,	   0x1180080944e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2511"            ,	   0x1180080944e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2512"            ,	   0x1180080944e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2513"            ,	   0x1180080944e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2514"            ,	   0x1180080944e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2515"            ,	   0x1180080944e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2516"            ,	   0x1180080944ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2517"            ,	   0x1180080944ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2518"            ,	   0x1180080944eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2519"            ,	   0x1180080944eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2520"            ,	   0x1180080944ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2521"            ,	   0x1180080944ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2522"            ,	   0x1180080944ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2523"            ,	   0x1180080944ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2524"            ,	   0x1180080944ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2525"            ,	   0x1180080944ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2526"            ,	   0x1180080944ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2527"            ,	   0x1180080944ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2528"            ,	   0x1180080944f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2529"            ,	   0x1180080944f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2530"            ,	   0x1180080944f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2531"            ,	   0x1180080944f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2532"            ,	   0x1180080944f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2533"            ,	   0x1180080944f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2534"            ,	   0x1180080944f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2535"            ,	   0x1180080944f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2536"            ,	   0x1180080944f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2537"            ,	   0x1180080944f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2538"            ,	   0x1180080944f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2539"            ,	   0x1180080944f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2540"            ,	   0x1180080944f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2541"            ,	   0x1180080944f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2542"            ,	   0x1180080944f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2543"            ,	   0x1180080944f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2544"            ,	   0x1180080944f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2545"            ,	   0x1180080944f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2546"            ,	   0x1180080944f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2547"            ,	   0x1180080944f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2548"            ,	   0x1180080944fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2549"            ,	   0x1180080944fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2550"            ,	   0x1180080944fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2551"            ,	   0x1180080944fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2552"            ,	   0x1180080944fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2553"            ,	   0x1180080944fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2554"            ,	   0x1180080944fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2555"            ,	   0x1180080944fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2556"            ,	   0x1180080944fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2557"            ,	   0x1180080944fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2558"            ,	   0x1180080944ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP2559"            ,	   0x1180080944ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16128"           ,	   0x118008095f800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16129"           ,	   0x118008095f808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16130"           ,	   0x118008095f810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16131"           ,	   0x118008095f818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16132"           ,	   0x118008095f820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16133"           ,	   0x118008095f828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16134"           ,	   0x118008095f830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16135"           ,	   0x118008095f838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16136"           ,	   0x118008095f840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16137"           ,	   0x118008095f848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16138"           ,	   0x118008095f850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16139"           ,	   0x118008095f858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16140"           ,	   0x118008095f860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16141"           ,	   0x118008095f868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16142"           ,	   0x118008095f870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16143"           ,	   0x118008095f878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16144"           ,	   0x118008095f880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16145"           ,	   0x118008095f888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16146"           ,	   0x118008095f890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16147"           ,	   0x118008095f898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16148"           ,	   0x118008095f8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16149"           ,	   0x118008095f8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16150"           ,	   0x118008095f8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16151"           ,	   0x118008095f8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16152"           ,	   0x118008095f8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16153"           ,	   0x118008095f8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16154"           ,	   0x118008095f8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16155"           ,	   0x118008095f8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16156"           ,	   0x118008095f8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16157"           ,	   0x118008095f8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16158"           ,	   0x118008095f8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16159"           ,	   0x118008095f8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16160"           ,	   0x118008095f900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16161"           ,	   0x118008095f908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16162"           ,	   0x118008095f910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16163"           ,	   0x118008095f918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16164"           ,	   0x118008095f920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16165"           ,	   0x118008095f928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16166"           ,	   0x118008095f930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16167"           ,	   0x118008095f938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16168"           ,	   0x118008095f940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16169"           ,	   0x118008095f948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16170"           ,	   0x118008095f950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16171"           ,	   0x118008095f958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16172"           ,	   0x118008095f960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16173"           ,	   0x118008095f968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16174"           ,	   0x118008095f970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16175"           ,	   0x118008095f978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16176"           ,	   0x118008095f980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16177"           ,	   0x118008095f988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16178"           ,	   0x118008095f990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16179"           ,	   0x118008095f998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16180"           ,	   0x118008095f9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16181"           ,	   0x118008095f9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16182"           ,	   0x118008095f9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16183"           ,	   0x118008095f9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16184"           ,	   0x118008095f9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16185"           ,	   0x118008095f9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16186"           ,	   0x118008095f9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16187"           ,	   0x118008095f9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16188"           ,	   0x118008095f9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16189"           ,	   0x118008095f9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16190"           ,	   0x118008095f9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16191"           ,	   0x118008095f9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16192"           ,	   0x118008095fa00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16193"           ,	   0x118008095fa08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16194"           ,	   0x118008095fa10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16195"           ,	   0x118008095fa18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16196"           ,	   0x118008095fa20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16197"           ,	   0x118008095fa28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16198"           ,	   0x118008095fa30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16199"           ,	   0x118008095fa38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16200"           ,	   0x118008095fa40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16201"           ,	   0x118008095fa48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16202"           ,	   0x118008095fa50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16203"           ,	   0x118008095fa58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16204"           ,	   0x118008095fa60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16205"           ,	   0x118008095fa68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16206"           ,	   0x118008095fa70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16207"           ,	   0x118008095fa78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16208"           ,	   0x118008095fa80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16209"           ,	   0x118008095fa88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16210"           ,	   0x118008095fa90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16211"           ,	   0x118008095fa98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16212"           ,	   0x118008095faa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16213"           ,	   0x118008095faa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16214"           ,	   0x118008095fab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16215"           ,	   0x118008095fab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16216"           ,	   0x118008095fac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16217"           ,	   0x118008095fac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16218"           ,	   0x118008095fad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16219"           ,	   0x118008095fad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16220"           ,	   0x118008095fae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16221"           ,	   0x118008095fae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16222"           ,	   0x118008095faf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16223"           ,	   0x118008095faf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16224"           ,	   0x118008095fb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16225"           ,	   0x118008095fb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16226"           ,	   0x118008095fb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16227"           ,	   0x118008095fb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16228"           ,	   0x118008095fb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16229"           ,	   0x118008095fb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16230"           ,	   0x118008095fb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16231"           ,	   0x118008095fb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16232"           ,	   0x118008095fb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16233"           ,	   0x118008095fb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16234"           ,	   0x118008095fb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16235"           ,	   0x118008095fb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16236"           ,	   0x118008095fb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16237"           ,	   0x118008095fb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16238"           ,	   0x118008095fb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16239"           ,	   0x118008095fb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16240"           ,	   0x118008095fb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16241"           ,	   0x118008095fb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16242"           ,	   0x118008095fb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16243"           ,	   0x118008095fb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16244"           ,	   0x118008095fba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16245"           ,	   0x118008095fba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16246"           ,	   0x118008095fbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16247"           ,	   0x118008095fbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16248"           ,	   0x118008095fbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16249"           ,	   0x118008095fbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16250"           ,	   0x118008095fbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16251"           ,	   0x118008095fbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16252"           ,	   0x118008095fbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16253"           ,	   0x118008095fbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16254"           ,	   0x118008095fbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16255"           ,	   0x118008095fbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16256"           ,	   0x118008095fc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16257"           ,	   0x118008095fc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16258"           ,	   0x118008095fc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16259"           ,	   0x118008095fc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16260"           ,	   0x118008095fc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16261"           ,	   0x118008095fc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16262"           ,	   0x118008095fc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16263"           ,	   0x118008095fc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16264"           ,	   0x118008095fc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16265"           ,	   0x118008095fc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16266"           ,	   0x118008095fc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16267"           ,	   0x118008095fc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16268"           ,	   0x118008095fc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16269"           ,	   0x118008095fc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16270"           ,	   0x118008095fc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16271"           ,	   0x118008095fc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16272"           ,	   0x118008095fc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16273"           ,	   0x118008095fc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16274"           ,	   0x118008095fc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16275"           ,	   0x118008095fc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16276"           ,	   0x118008095fca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16277"           ,	   0x118008095fca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16278"           ,	   0x118008095fcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16279"           ,	   0x118008095fcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16280"           ,	   0x118008095fcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16281"           ,	   0x118008095fcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16282"           ,	   0x118008095fcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16283"           ,	   0x118008095fcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16284"           ,	   0x118008095fce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16285"           ,	   0x118008095fce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16286"           ,	   0x118008095fcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16287"           ,	   0x118008095fcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16288"           ,	   0x118008095fd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16289"           ,	   0x118008095fd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16290"           ,	   0x118008095fd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16291"           ,	   0x118008095fd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16292"           ,	   0x118008095fd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16293"           ,	   0x118008095fd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16294"           ,	   0x118008095fd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16295"           ,	   0x118008095fd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16296"           ,	   0x118008095fd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16297"           ,	   0x118008095fd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16298"           ,	   0x118008095fd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16299"           ,	   0x118008095fd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16300"           ,	   0x118008095fd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16301"           ,	   0x118008095fd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16302"           ,	   0x118008095fd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16303"           ,	   0x118008095fd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16304"           ,	   0x118008095fd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16305"           ,	   0x118008095fd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16306"           ,	   0x118008095fd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16307"           ,	   0x118008095fd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16308"           ,	   0x118008095fda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16309"           ,	   0x118008095fda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16310"           ,	   0x118008095fdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16311"           ,	   0x118008095fdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16312"           ,	   0x118008095fdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16313"           ,	   0x118008095fdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16314"           ,	   0x118008095fdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16315"           ,	   0x118008095fdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16316"           ,	   0x118008095fde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16317"           ,	   0x118008095fde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16318"           ,	   0x118008095fdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16319"           ,	   0x118008095fdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16320"           ,	   0x118008095fe00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16321"           ,	   0x118008095fe08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16322"           ,	   0x118008095fe10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16323"           ,	   0x118008095fe18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16324"           ,	   0x118008095fe20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16325"           ,	   0x118008095fe28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16326"           ,	   0x118008095fe30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16327"           ,	   0x118008095fe38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16328"           ,	   0x118008095fe40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16329"           ,	   0x118008095fe48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16330"           ,	   0x118008095fe50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16331"           ,	   0x118008095fe58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16332"           ,	   0x118008095fe60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16333"           ,	   0x118008095fe68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16334"           ,	   0x118008095fe70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16335"           ,	   0x118008095fe78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16336"           ,	   0x118008095fe80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16337"           ,	   0x118008095fe88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16338"           ,	   0x118008095fe90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16339"           ,	   0x118008095fe98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16340"           ,	   0x118008095fea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16341"           ,	   0x118008095fea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16342"           ,	   0x118008095feb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16343"           ,	   0x118008095feb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16344"           ,	   0x118008095fec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16345"           ,	   0x118008095fec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16346"           ,	   0x118008095fed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16347"           ,	   0x118008095fed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16348"           ,	   0x118008095fee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16349"           ,	   0x118008095fee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16350"           ,	   0x118008095fef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16351"           ,	   0x118008095fef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16352"           ,	   0x118008095ff00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16353"           ,	   0x118008095ff08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16354"           ,	   0x118008095ff10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16355"           ,	   0x118008095ff18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16356"           ,	   0x118008095ff20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16357"           ,	   0x118008095ff28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16358"           ,	   0x118008095ff30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16359"           ,	   0x118008095ff38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16360"           ,	   0x118008095ff40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16361"           ,	   0x118008095ff48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16362"           ,	   0x118008095ff50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16363"           ,	   0x118008095ff58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16364"           ,	   0x118008095ff60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16365"           ,	   0x118008095ff68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16366"           ,	   0x118008095ff70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16367"           ,	   0x118008095ff78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16368"           ,	   0x118008095ff80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16369"           ,	   0x118008095ff88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16370"           ,	   0x118008095ff90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16371"           ,	   0x118008095ff98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16372"           ,	   0x118008095ffa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16373"           ,	   0x118008095ffa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16374"           ,	   0x118008095ffb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16375"           ,	   0x118008095ffb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16376"           ,	   0x118008095ffc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16377"           ,	   0x118008095ffc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16378"           ,	   0x118008095ffd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16379"           ,	   0x118008095ffd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16380"           ,	   0x118008095ffe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16381"           ,	   0x118008095ffe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16382"           ,	   0x118008095fff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_COP0_MAP16383"           ,	   0x118008095fff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_CTL"                     ,	   0x1180080800000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"L2C_DUT_MAP0"                ,	   0x1180080e00000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1"                ,	   0x1180080e00008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2"                ,	   0x1180080e00010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP3"                ,	   0x1180080e00018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP4"                ,	   0x1180080e00020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP5"                ,	   0x1180080e00028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP6"                ,	   0x1180080e00030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP7"                ,	   0x1180080e00038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP8"                ,	   0x1180080e00040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP9"                ,	   0x1180080e00048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP10"               ,	   0x1180080e00050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP11"               ,	   0x1180080e00058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP12"               ,	   0x1180080e00060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP13"               ,	   0x1180080e00068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP14"               ,	   0x1180080e00070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP15"               ,	   0x1180080e00078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP16"               ,	   0x1180080e00080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP17"               ,	   0x1180080e00088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP18"               ,	   0x1180080e00090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP19"               ,	   0x1180080e00098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP20"               ,	   0x1180080e000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP21"               ,	   0x1180080e000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP22"               ,	   0x1180080e000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP23"               ,	   0x1180080e000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP24"               ,	   0x1180080e000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP25"               ,	   0x1180080e000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP26"               ,	   0x1180080e000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP27"               ,	   0x1180080e000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP28"               ,	   0x1180080e000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP29"               ,	   0x1180080e000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP30"               ,	   0x1180080e000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP31"               ,	   0x1180080e000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP32"               ,	   0x1180080e00100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP33"               ,	   0x1180080e00108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP34"               ,	   0x1180080e00110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP35"               ,	   0x1180080e00118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP36"               ,	   0x1180080e00120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP37"               ,	   0x1180080e00128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP38"               ,	   0x1180080e00130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP39"               ,	   0x1180080e00138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP40"               ,	   0x1180080e00140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP41"               ,	   0x1180080e00148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP42"               ,	   0x1180080e00150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP43"               ,	   0x1180080e00158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP44"               ,	   0x1180080e00160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP45"               ,	   0x1180080e00168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP46"               ,	   0x1180080e00170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP47"               ,	   0x1180080e00178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP48"               ,	   0x1180080e00180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP49"               ,	   0x1180080e00188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP50"               ,	   0x1180080e00190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP51"               ,	   0x1180080e00198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP52"               ,	   0x1180080e001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP53"               ,	   0x1180080e001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP54"               ,	   0x1180080e001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP55"               ,	   0x1180080e001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP56"               ,	   0x1180080e001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP57"               ,	   0x1180080e001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP58"               ,	   0x1180080e001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP59"               ,	   0x1180080e001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP60"               ,	   0x1180080e001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP61"               ,	   0x1180080e001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP62"               ,	   0x1180080e001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP63"               ,	   0x1180080e001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP64"               ,	   0x1180080e00200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP65"               ,	   0x1180080e00208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP66"               ,	   0x1180080e00210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP67"               ,	   0x1180080e00218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP68"               ,	   0x1180080e00220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP69"               ,	   0x1180080e00228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP70"               ,	   0x1180080e00230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP71"               ,	   0x1180080e00238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP72"               ,	   0x1180080e00240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP73"               ,	   0x1180080e00248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP74"               ,	   0x1180080e00250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP75"               ,	   0x1180080e00258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP76"               ,	   0x1180080e00260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP77"               ,	   0x1180080e00268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP78"               ,	   0x1180080e00270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP79"               ,	   0x1180080e00278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP80"               ,	   0x1180080e00280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP81"               ,	   0x1180080e00288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP82"               ,	   0x1180080e00290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP83"               ,	   0x1180080e00298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP84"               ,	   0x1180080e002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP85"               ,	   0x1180080e002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP86"               ,	   0x1180080e002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP87"               ,	   0x1180080e002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP88"               ,	   0x1180080e002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP89"               ,	   0x1180080e002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP90"               ,	   0x1180080e002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP91"               ,	   0x1180080e002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP92"               ,	   0x1180080e002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP93"               ,	   0x1180080e002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP94"               ,	   0x1180080e002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP95"               ,	   0x1180080e002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP96"               ,	   0x1180080e00300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP97"               ,	   0x1180080e00308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP98"               ,	   0x1180080e00310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP99"               ,	   0x1180080e00318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP100"              ,	   0x1180080e00320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP101"              ,	   0x1180080e00328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP102"              ,	   0x1180080e00330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP103"              ,	   0x1180080e00338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP104"              ,	   0x1180080e00340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP105"              ,	   0x1180080e00348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP106"              ,	   0x1180080e00350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP107"              ,	   0x1180080e00358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP108"              ,	   0x1180080e00360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP109"              ,	   0x1180080e00368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP110"              ,	   0x1180080e00370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP111"              ,	   0x1180080e00378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP112"              ,	   0x1180080e00380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP113"              ,	   0x1180080e00388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP114"              ,	   0x1180080e00390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP115"              ,	   0x1180080e00398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP116"              ,	   0x1180080e003a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP117"              ,	   0x1180080e003a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP118"              ,	   0x1180080e003b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP119"              ,	   0x1180080e003b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP120"              ,	   0x1180080e003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP121"              ,	   0x1180080e003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP122"              ,	   0x1180080e003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP123"              ,	   0x1180080e003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP124"              ,	   0x1180080e003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP125"              ,	   0x1180080e003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP126"              ,	   0x1180080e003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP127"              ,	   0x1180080e003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP128"              ,	   0x1180080e00400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP129"              ,	   0x1180080e00408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP130"              ,	   0x1180080e00410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP131"              ,	   0x1180080e00418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP132"              ,	   0x1180080e00420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP133"              ,	   0x1180080e00428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP134"              ,	   0x1180080e00430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP135"              ,	   0x1180080e00438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP136"              ,	   0x1180080e00440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP137"              ,	   0x1180080e00448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP138"              ,	   0x1180080e00450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP139"              ,	   0x1180080e00458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP140"              ,	   0x1180080e00460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP141"              ,	   0x1180080e00468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP142"              ,	   0x1180080e00470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP143"              ,	   0x1180080e00478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP144"              ,	   0x1180080e00480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP145"              ,	   0x1180080e00488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP146"              ,	   0x1180080e00490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP147"              ,	   0x1180080e00498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP148"              ,	   0x1180080e004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP149"              ,	   0x1180080e004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP150"              ,	   0x1180080e004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP151"              ,	   0x1180080e004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP152"              ,	   0x1180080e004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP153"              ,	   0x1180080e004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP154"              ,	   0x1180080e004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP155"              ,	   0x1180080e004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP156"              ,	   0x1180080e004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP157"              ,	   0x1180080e004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP158"              ,	   0x1180080e004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP159"              ,	   0x1180080e004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP160"              ,	   0x1180080e00500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP161"              ,	   0x1180080e00508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP162"              ,	   0x1180080e00510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP163"              ,	   0x1180080e00518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP164"              ,	   0x1180080e00520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP165"              ,	   0x1180080e00528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP166"              ,	   0x1180080e00530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP167"              ,	   0x1180080e00538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP168"              ,	   0x1180080e00540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP169"              ,	   0x1180080e00548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP170"              ,	   0x1180080e00550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP171"              ,	   0x1180080e00558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP172"              ,	   0x1180080e00560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP173"              ,	   0x1180080e00568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP174"              ,	   0x1180080e00570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP175"              ,	   0x1180080e00578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP176"              ,	   0x1180080e00580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP177"              ,	   0x1180080e00588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP178"              ,	   0x1180080e00590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP179"              ,	   0x1180080e00598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP180"              ,	   0x1180080e005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP181"              ,	   0x1180080e005a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP182"              ,	   0x1180080e005b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP183"              ,	   0x1180080e005b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP184"              ,	   0x1180080e005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP185"              ,	   0x1180080e005c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP186"              ,	   0x1180080e005d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP187"              ,	   0x1180080e005d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP188"              ,	   0x1180080e005e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP189"              ,	   0x1180080e005e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP190"              ,	   0x1180080e005f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP191"              ,	   0x1180080e005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP192"              ,	   0x1180080e00600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP193"              ,	   0x1180080e00608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP194"              ,	   0x1180080e00610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP195"              ,	   0x1180080e00618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP196"              ,	   0x1180080e00620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP197"              ,	   0x1180080e00628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP198"              ,	   0x1180080e00630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP199"              ,	   0x1180080e00638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP200"              ,	   0x1180080e00640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP201"              ,	   0x1180080e00648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP202"              ,	   0x1180080e00650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP203"              ,	   0x1180080e00658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP204"              ,	   0x1180080e00660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP205"              ,	   0x1180080e00668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP206"              ,	   0x1180080e00670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP207"              ,	   0x1180080e00678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP208"              ,	   0x1180080e00680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP209"              ,	   0x1180080e00688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP210"              ,	   0x1180080e00690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP211"              ,	   0x1180080e00698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP212"              ,	   0x1180080e006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP213"              ,	   0x1180080e006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP214"              ,	   0x1180080e006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP215"              ,	   0x1180080e006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP216"              ,	   0x1180080e006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP217"              ,	   0x1180080e006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP218"              ,	   0x1180080e006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP219"              ,	   0x1180080e006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP220"              ,	   0x1180080e006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP221"              ,	   0x1180080e006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP222"              ,	   0x1180080e006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP223"              ,	   0x1180080e006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP224"              ,	   0x1180080e00700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP225"              ,	   0x1180080e00708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP226"              ,	   0x1180080e00710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP227"              ,	   0x1180080e00718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP228"              ,	   0x1180080e00720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP229"              ,	   0x1180080e00728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP230"              ,	   0x1180080e00730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP231"              ,	   0x1180080e00738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP232"              ,	   0x1180080e00740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP233"              ,	   0x1180080e00748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP234"              ,	   0x1180080e00750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP235"              ,	   0x1180080e00758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP236"              ,	   0x1180080e00760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP237"              ,	   0x1180080e00768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP238"              ,	   0x1180080e00770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP239"              ,	   0x1180080e00778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP240"              ,	   0x1180080e00780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP241"              ,	   0x1180080e00788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP242"              ,	   0x1180080e00790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP243"              ,	   0x1180080e00798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP244"              ,	   0x1180080e007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP245"              ,	   0x1180080e007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP246"              ,	   0x1180080e007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP247"              ,	   0x1180080e007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP248"              ,	   0x1180080e007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP249"              ,	   0x1180080e007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP250"              ,	   0x1180080e007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP251"              ,	   0x1180080e007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP252"              ,	   0x1180080e007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP253"              ,	   0x1180080e007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP254"              ,	   0x1180080e007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP255"              ,	   0x1180080e007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP256"              ,	   0x1180080e00800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP257"              ,	   0x1180080e00808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP258"              ,	   0x1180080e00810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP259"              ,	   0x1180080e00818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP260"              ,	   0x1180080e00820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP261"              ,	   0x1180080e00828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP262"              ,	   0x1180080e00830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP263"              ,	   0x1180080e00838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP264"              ,	   0x1180080e00840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP265"              ,	   0x1180080e00848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP266"              ,	   0x1180080e00850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP267"              ,	   0x1180080e00858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP268"              ,	   0x1180080e00860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP269"              ,	   0x1180080e00868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP270"              ,	   0x1180080e00870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP271"              ,	   0x1180080e00878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP272"              ,	   0x1180080e00880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP273"              ,	   0x1180080e00888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP274"              ,	   0x1180080e00890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP275"              ,	   0x1180080e00898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP276"              ,	   0x1180080e008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP277"              ,	   0x1180080e008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP278"              ,	   0x1180080e008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP279"              ,	   0x1180080e008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP280"              ,	   0x1180080e008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP281"              ,	   0x1180080e008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP282"              ,	   0x1180080e008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP283"              ,	   0x1180080e008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP284"              ,	   0x1180080e008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP285"              ,	   0x1180080e008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP286"              ,	   0x1180080e008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP287"              ,	   0x1180080e008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP288"              ,	   0x1180080e00900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP289"              ,	   0x1180080e00908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP290"              ,	   0x1180080e00910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP291"              ,	   0x1180080e00918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP292"              ,	   0x1180080e00920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP293"              ,	   0x1180080e00928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP294"              ,	   0x1180080e00930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP295"              ,	   0x1180080e00938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP296"              ,	   0x1180080e00940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP297"              ,	   0x1180080e00948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP298"              ,	   0x1180080e00950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP299"              ,	   0x1180080e00958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP300"              ,	   0x1180080e00960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP301"              ,	   0x1180080e00968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP302"              ,	   0x1180080e00970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP303"              ,	   0x1180080e00978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP304"              ,	   0x1180080e00980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP305"              ,	   0x1180080e00988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP306"              ,	   0x1180080e00990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP307"              ,	   0x1180080e00998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP308"              ,	   0x1180080e009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP309"              ,	   0x1180080e009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP310"              ,	   0x1180080e009b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP311"              ,	   0x1180080e009b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP312"              ,	   0x1180080e009c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP313"              ,	   0x1180080e009c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP314"              ,	   0x1180080e009d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP315"              ,	   0x1180080e009d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP316"              ,	   0x1180080e009e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP317"              ,	   0x1180080e009e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP318"              ,	   0x1180080e009f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP319"              ,	   0x1180080e009f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP320"              ,	   0x1180080e00a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP321"              ,	   0x1180080e00a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP322"              ,	   0x1180080e00a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP323"              ,	   0x1180080e00a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP324"              ,	   0x1180080e00a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP325"              ,	   0x1180080e00a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP326"              ,	   0x1180080e00a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP327"              ,	   0x1180080e00a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP328"              ,	   0x1180080e00a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP329"              ,	   0x1180080e00a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP330"              ,	   0x1180080e00a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP331"              ,	   0x1180080e00a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP332"              ,	   0x1180080e00a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP333"              ,	   0x1180080e00a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP334"              ,	   0x1180080e00a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP335"              ,	   0x1180080e00a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP336"              ,	   0x1180080e00a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP337"              ,	   0x1180080e00a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP338"              ,	   0x1180080e00a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP339"              ,	   0x1180080e00a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP340"              ,	   0x1180080e00aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP341"              ,	   0x1180080e00aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP342"              ,	   0x1180080e00ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP343"              ,	   0x1180080e00ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP344"              ,	   0x1180080e00ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP345"              ,	   0x1180080e00ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP346"              ,	   0x1180080e00ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP347"              ,	   0x1180080e00ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP348"              ,	   0x1180080e00ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP349"              ,	   0x1180080e00ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP350"              ,	   0x1180080e00af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP351"              ,	   0x1180080e00af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP352"              ,	   0x1180080e00b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP353"              ,	   0x1180080e00b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP354"              ,	   0x1180080e00b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP355"              ,	   0x1180080e00b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP356"              ,	   0x1180080e00b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP357"              ,	   0x1180080e00b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP358"              ,	   0x1180080e00b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP359"              ,	   0x1180080e00b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP360"              ,	   0x1180080e00b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP361"              ,	   0x1180080e00b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP362"              ,	   0x1180080e00b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP363"              ,	   0x1180080e00b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP364"              ,	   0x1180080e00b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP365"              ,	   0x1180080e00b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP366"              ,	   0x1180080e00b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP367"              ,	   0x1180080e00b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP368"              ,	   0x1180080e00b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP369"              ,	   0x1180080e00b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP370"              ,	   0x1180080e00b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP371"              ,	   0x1180080e00b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP372"              ,	   0x1180080e00ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP373"              ,	   0x1180080e00ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP374"              ,	   0x1180080e00bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP375"              ,	   0x1180080e00bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP376"              ,	   0x1180080e00bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP377"              ,	   0x1180080e00bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP378"              ,	   0x1180080e00bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP379"              ,	   0x1180080e00bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP380"              ,	   0x1180080e00be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP381"              ,	   0x1180080e00be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP382"              ,	   0x1180080e00bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP383"              ,	   0x1180080e00bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP384"              ,	   0x1180080e00c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP385"              ,	   0x1180080e00c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP386"              ,	   0x1180080e00c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP387"              ,	   0x1180080e00c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP388"              ,	   0x1180080e00c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP389"              ,	   0x1180080e00c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP390"              ,	   0x1180080e00c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP391"              ,	   0x1180080e00c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP392"              ,	   0x1180080e00c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP393"              ,	   0x1180080e00c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP394"              ,	   0x1180080e00c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP395"              ,	   0x1180080e00c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP396"              ,	   0x1180080e00c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP397"              ,	   0x1180080e00c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP398"              ,	   0x1180080e00c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP399"              ,	   0x1180080e00c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP400"              ,	   0x1180080e00c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP401"              ,	   0x1180080e00c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP402"              ,	   0x1180080e00c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP403"              ,	   0x1180080e00c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP404"              ,	   0x1180080e00ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP405"              ,	   0x1180080e00ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP406"              ,	   0x1180080e00cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP407"              ,	   0x1180080e00cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP408"              ,	   0x1180080e00cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP409"              ,	   0x1180080e00cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP410"              ,	   0x1180080e00cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP411"              ,	   0x1180080e00cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP412"              ,	   0x1180080e00ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP413"              ,	   0x1180080e00ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP414"              ,	   0x1180080e00cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP415"              ,	   0x1180080e00cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP416"              ,	   0x1180080e00d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP417"              ,	   0x1180080e00d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP418"              ,	   0x1180080e00d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP419"              ,	   0x1180080e00d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP420"              ,	   0x1180080e00d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP421"              ,	   0x1180080e00d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP422"              ,	   0x1180080e00d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP423"              ,	   0x1180080e00d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP424"              ,	   0x1180080e00d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP425"              ,	   0x1180080e00d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP426"              ,	   0x1180080e00d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP427"              ,	   0x1180080e00d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP428"              ,	   0x1180080e00d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP429"              ,	   0x1180080e00d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP430"              ,	   0x1180080e00d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP431"              ,	   0x1180080e00d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP432"              ,	   0x1180080e00d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP433"              ,	   0x1180080e00d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP434"              ,	   0x1180080e00d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP435"              ,	   0x1180080e00d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP436"              ,	   0x1180080e00da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP437"              ,	   0x1180080e00da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP438"              ,	   0x1180080e00db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP439"              ,	   0x1180080e00db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP440"              ,	   0x1180080e00dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP441"              ,	   0x1180080e00dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP442"              ,	   0x1180080e00dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP443"              ,	   0x1180080e00dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP444"              ,	   0x1180080e00de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP445"              ,	   0x1180080e00de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP446"              ,	   0x1180080e00df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP447"              ,	   0x1180080e00df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP448"              ,	   0x1180080e00e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP449"              ,	   0x1180080e00e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP450"              ,	   0x1180080e00e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP451"              ,	   0x1180080e00e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP452"              ,	   0x1180080e00e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP453"              ,	   0x1180080e00e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP454"              ,	   0x1180080e00e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP455"              ,	   0x1180080e00e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP456"              ,	   0x1180080e00e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP457"              ,	   0x1180080e00e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP458"              ,	   0x1180080e00e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP459"              ,	   0x1180080e00e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP460"              ,	   0x1180080e00e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP461"              ,	   0x1180080e00e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP462"              ,	   0x1180080e00e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP463"              ,	   0x1180080e00e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP464"              ,	   0x1180080e00e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP465"              ,	   0x1180080e00e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP466"              ,	   0x1180080e00e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP467"              ,	   0x1180080e00e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP468"              ,	   0x1180080e00ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP469"              ,	   0x1180080e00ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP470"              ,	   0x1180080e00eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP471"              ,	   0x1180080e00eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP472"              ,	   0x1180080e00ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP473"              ,	   0x1180080e00ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP474"              ,	   0x1180080e00ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP475"              ,	   0x1180080e00ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP476"              ,	   0x1180080e00ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP477"              ,	   0x1180080e00ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP478"              ,	   0x1180080e00ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP479"              ,	   0x1180080e00ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP480"              ,	   0x1180080e00f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP481"              ,	   0x1180080e00f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP482"              ,	   0x1180080e00f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP483"              ,	   0x1180080e00f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP484"              ,	   0x1180080e00f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP485"              ,	   0x1180080e00f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP486"              ,	   0x1180080e00f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP487"              ,	   0x1180080e00f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP488"              ,	   0x1180080e00f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP489"              ,	   0x1180080e00f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP490"              ,	   0x1180080e00f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP491"              ,	   0x1180080e00f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP492"              ,	   0x1180080e00f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP493"              ,	   0x1180080e00f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP494"              ,	   0x1180080e00f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP495"              ,	   0x1180080e00f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP496"              ,	   0x1180080e00f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP497"              ,	   0x1180080e00f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP498"              ,	   0x1180080e00f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP499"              ,	   0x1180080e00f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP500"              ,	   0x1180080e00fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP501"              ,	   0x1180080e00fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP502"              ,	   0x1180080e00fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP503"              ,	   0x1180080e00fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP504"              ,	   0x1180080e00fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP505"              ,	   0x1180080e00fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP506"              ,	   0x1180080e00fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP507"              ,	   0x1180080e00fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP508"              ,	   0x1180080e00fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP509"              ,	   0x1180080e00fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP510"              ,	   0x1180080e00ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP511"              ,	   0x1180080e00ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP512"              ,	   0x1180080e01000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP513"              ,	   0x1180080e01008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP514"              ,	   0x1180080e01010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP515"              ,	   0x1180080e01018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP516"              ,	   0x1180080e01020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP517"              ,	   0x1180080e01028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP518"              ,	   0x1180080e01030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP519"              ,	   0x1180080e01038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP520"              ,	   0x1180080e01040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP521"              ,	   0x1180080e01048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP522"              ,	   0x1180080e01050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP523"              ,	   0x1180080e01058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP524"              ,	   0x1180080e01060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP525"              ,	   0x1180080e01068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP526"              ,	   0x1180080e01070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP527"              ,	   0x1180080e01078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP528"              ,	   0x1180080e01080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP529"              ,	   0x1180080e01088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP530"              ,	   0x1180080e01090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP531"              ,	   0x1180080e01098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP532"              ,	   0x1180080e010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP533"              ,	   0x1180080e010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP534"              ,	   0x1180080e010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP535"              ,	   0x1180080e010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP536"              ,	   0x1180080e010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP537"              ,	   0x1180080e010c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP538"              ,	   0x1180080e010d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP539"              ,	   0x1180080e010d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP540"              ,	   0x1180080e010e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP541"              ,	   0x1180080e010e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP542"              ,	   0x1180080e010f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP543"              ,	   0x1180080e010f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP544"              ,	   0x1180080e01100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP545"              ,	   0x1180080e01108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP546"              ,	   0x1180080e01110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP547"              ,	   0x1180080e01118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP548"              ,	   0x1180080e01120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP549"              ,	   0x1180080e01128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP550"              ,	   0x1180080e01130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP551"              ,	   0x1180080e01138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP552"              ,	   0x1180080e01140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP553"              ,	   0x1180080e01148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP554"              ,	   0x1180080e01150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP555"              ,	   0x1180080e01158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP556"              ,	   0x1180080e01160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP557"              ,	   0x1180080e01168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP558"              ,	   0x1180080e01170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP559"              ,	   0x1180080e01178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP560"              ,	   0x1180080e01180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP561"              ,	   0x1180080e01188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP562"              ,	   0x1180080e01190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP563"              ,	   0x1180080e01198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP564"              ,	   0x1180080e011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP565"              ,	   0x1180080e011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP566"              ,	   0x1180080e011b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP567"              ,	   0x1180080e011b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP568"              ,	   0x1180080e011c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP569"              ,	   0x1180080e011c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP570"              ,	   0x1180080e011d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP571"              ,	   0x1180080e011d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP572"              ,	   0x1180080e011e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP573"              ,	   0x1180080e011e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP574"              ,	   0x1180080e011f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP575"              ,	   0x1180080e011f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP576"              ,	   0x1180080e01200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP577"              ,	   0x1180080e01208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP578"              ,	   0x1180080e01210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP579"              ,	   0x1180080e01218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP580"              ,	   0x1180080e01220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP581"              ,	   0x1180080e01228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP582"              ,	   0x1180080e01230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP583"              ,	   0x1180080e01238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP584"              ,	   0x1180080e01240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP585"              ,	   0x1180080e01248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP586"              ,	   0x1180080e01250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP587"              ,	   0x1180080e01258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP588"              ,	   0x1180080e01260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP589"              ,	   0x1180080e01268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP590"              ,	   0x1180080e01270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP591"              ,	   0x1180080e01278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP592"              ,	   0x1180080e01280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP593"              ,	   0x1180080e01288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP594"              ,	   0x1180080e01290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP595"              ,	   0x1180080e01298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP596"              ,	   0x1180080e012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP597"              ,	   0x1180080e012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP598"              ,	   0x1180080e012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP599"              ,	   0x1180080e012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP600"              ,	   0x1180080e012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP601"              ,	   0x1180080e012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP602"              ,	   0x1180080e012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP603"              ,	   0x1180080e012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP604"              ,	   0x1180080e012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP605"              ,	   0x1180080e012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP606"              ,	   0x1180080e012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP607"              ,	   0x1180080e012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP608"              ,	   0x1180080e01300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP609"              ,	   0x1180080e01308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP610"              ,	   0x1180080e01310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP611"              ,	   0x1180080e01318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP612"              ,	   0x1180080e01320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP613"              ,	   0x1180080e01328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP614"              ,	   0x1180080e01330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP615"              ,	   0x1180080e01338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP616"              ,	   0x1180080e01340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP617"              ,	   0x1180080e01348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP618"              ,	   0x1180080e01350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP619"              ,	   0x1180080e01358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP620"              ,	   0x1180080e01360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP621"              ,	   0x1180080e01368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP622"              ,	   0x1180080e01370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP623"              ,	   0x1180080e01378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP624"              ,	   0x1180080e01380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP625"              ,	   0x1180080e01388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP626"              ,	   0x1180080e01390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP627"              ,	   0x1180080e01398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP628"              ,	   0x1180080e013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP629"              ,	   0x1180080e013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP630"              ,	   0x1180080e013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP631"              ,	   0x1180080e013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP632"              ,	   0x1180080e013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP633"              ,	   0x1180080e013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP634"              ,	   0x1180080e013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP635"              ,	   0x1180080e013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP636"              ,	   0x1180080e013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP637"              ,	   0x1180080e013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP638"              ,	   0x1180080e013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP639"              ,	   0x1180080e013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP640"              ,	   0x1180080e01400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP641"              ,	   0x1180080e01408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP642"              ,	   0x1180080e01410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP643"              ,	   0x1180080e01418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP644"              ,	   0x1180080e01420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP645"              ,	   0x1180080e01428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP646"              ,	   0x1180080e01430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP647"              ,	   0x1180080e01438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP648"              ,	   0x1180080e01440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP649"              ,	   0x1180080e01448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP650"              ,	   0x1180080e01450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP651"              ,	   0x1180080e01458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP652"              ,	   0x1180080e01460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP653"              ,	   0x1180080e01468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP654"              ,	   0x1180080e01470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP655"              ,	   0x1180080e01478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP656"              ,	   0x1180080e01480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP657"              ,	   0x1180080e01488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP658"              ,	   0x1180080e01490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP659"              ,	   0x1180080e01498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP660"              ,	   0x1180080e014a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP661"              ,	   0x1180080e014a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP662"              ,	   0x1180080e014b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP663"              ,	   0x1180080e014b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP664"              ,	   0x1180080e014c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP665"              ,	   0x1180080e014c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP666"              ,	   0x1180080e014d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP667"              ,	   0x1180080e014d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP668"              ,	   0x1180080e014e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP669"              ,	   0x1180080e014e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP670"              ,	   0x1180080e014f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP671"              ,	   0x1180080e014f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP672"              ,	   0x1180080e01500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP673"              ,	   0x1180080e01508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP674"              ,	   0x1180080e01510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP675"              ,	   0x1180080e01518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP676"              ,	   0x1180080e01520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP677"              ,	   0x1180080e01528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP678"              ,	   0x1180080e01530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP679"              ,	   0x1180080e01538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP680"              ,	   0x1180080e01540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP681"              ,	   0x1180080e01548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP682"              ,	   0x1180080e01550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP683"              ,	   0x1180080e01558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP684"              ,	   0x1180080e01560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP685"              ,	   0x1180080e01568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP686"              ,	   0x1180080e01570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP687"              ,	   0x1180080e01578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP688"              ,	   0x1180080e01580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP689"              ,	   0x1180080e01588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP690"              ,	   0x1180080e01590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP691"              ,	   0x1180080e01598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP692"              ,	   0x1180080e015a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP693"              ,	   0x1180080e015a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP694"              ,	   0x1180080e015b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP695"              ,	   0x1180080e015b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP696"              ,	   0x1180080e015c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP697"              ,	   0x1180080e015c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP698"              ,	   0x1180080e015d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP699"              ,	   0x1180080e015d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP700"              ,	   0x1180080e015e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP701"              ,	   0x1180080e015e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP702"              ,	   0x1180080e015f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP703"              ,	   0x1180080e015f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP704"              ,	   0x1180080e01600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP705"              ,	   0x1180080e01608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP706"              ,	   0x1180080e01610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP707"              ,	   0x1180080e01618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP708"              ,	   0x1180080e01620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP709"              ,	   0x1180080e01628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP710"              ,	   0x1180080e01630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP711"              ,	   0x1180080e01638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP712"              ,	   0x1180080e01640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP713"              ,	   0x1180080e01648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP714"              ,	   0x1180080e01650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP715"              ,	   0x1180080e01658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP716"              ,	   0x1180080e01660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP717"              ,	   0x1180080e01668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP718"              ,	   0x1180080e01670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP719"              ,	   0x1180080e01678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP720"              ,	   0x1180080e01680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP721"              ,	   0x1180080e01688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP722"              ,	   0x1180080e01690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP723"              ,	   0x1180080e01698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP724"              ,	   0x1180080e016a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP725"              ,	   0x1180080e016a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP726"              ,	   0x1180080e016b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP727"              ,	   0x1180080e016b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP728"              ,	   0x1180080e016c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP729"              ,	   0x1180080e016c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP730"              ,	   0x1180080e016d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP731"              ,	   0x1180080e016d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP732"              ,	   0x1180080e016e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP733"              ,	   0x1180080e016e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP734"              ,	   0x1180080e016f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP735"              ,	   0x1180080e016f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP736"              ,	   0x1180080e01700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP737"              ,	   0x1180080e01708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP738"              ,	   0x1180080e01710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP739"              ,	   0x1180080e01718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP740"              ,	   0x1180080e01720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP741"              ,	   0x1180080e01728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP742"              ,	   0x1180080e01730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP743"              ,	   0x1180080e01738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP744"              ,	   0x1180080e01740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP745"              ,	   0x1180080e01748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP746"              ,	   0x1180080e01750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP747"              ,	   0x1180080e01758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP748"              ,	   0x1180080e01760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP749"              ,	   0x1180080e01768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP750"              ,	   0x1180080e01770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP751"              ,	   0x1180080e01778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP752"              ,	   0x1180080e01780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP753"              ,	   0x1180080e01788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP754"              ,	   0x1180080e01790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP755"              ,	   0x1180080e01798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP756"              ,	   0x1180080e017a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP757"              ,	   0x1180080e017a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP758"              ,	   0x1180080e017b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP759"              ,	   0x1180080e017b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP760"              ,	   0x1180080e017c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP761"              ,	   0x1180080e017c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP762"              ,	   0x1180080e017d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP763"              ,	   0x1180080e017d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP764"              ,	   0x1180080e017e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP765"              ,	   0x1180080e017e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP766"              ,	   0x1180080e017f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP767"              ,	   0x1180080e017f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP768"              ,	   0x1180080e01800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP769"              ,	   0x1180080e01808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP770"              ,	   0x1180080e01810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP771"              ,	   0x1180080e01818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP772"              ,	   0x1180080e01820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP773"              ,	   0x1180080e01828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP774"              ,	   0x1180080e01830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP775"              ,	   0x1180080e01838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP776"              ,	   0x1180080e01840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP777"              ,	   0x1180080e01848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP778"              ,	   0x1180080e01850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP779"              ,	   0x1180080e01858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP780"              ,	   0x1180080e01860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP781"              ,	   0x1180080e01868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP782"              ,	   0x1180080e01870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP783"              ,	   0x1180080e01878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP784"              ,	   0x1180080e01880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP785"              ,	   0x1180080e01888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP786"              ,	   0x1180080e01890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP787"              ,	   0x1180080e01898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP788"              ,	   0x1180080e018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP789"              ,	   0x1180080e018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP790"              ,	   0x1180080e018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP791"              ,	   0x1180080e018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP792"              ,	   0x1180080e018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP793"              ,	   0x1180080e018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP794"              ,	   0x1180080e018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP795"              ,	   0x1180080e018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP796"              ,	   0x1180080e018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP797"              ,	   0x1180080e018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP798"              ,	   0x1180080e018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP799"              ,	   0x1180080e018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP800"              ,	   0x1180080e01900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP801"              ,	   0x1180080e01908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP802"              ,	   0x1180080e01910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP803"              ,	   0x1180080e01918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP804"              ,	   0x1180080e01920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP805"              ,	   0x1180080e01928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP806"              ,	   0x1180080e01930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP807"              ,	   0x1180080e01938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP808"              ,	   0x1180080e01940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP809"              ,	   0x1180080e01948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP810"              ,	   0x1180080e01950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP811"              ,	   0x1180080e01958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP812"              ,	   0x1180080e01960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP813"              ,	   0x1180080e01968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP814"              ,	   0x1180080e01970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP815"              ,	   0x1180080e01978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP816"              ,	   0x1180080e01980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP817"              ,	   0x1180080e01988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP818"              ,	   0x1180080e01990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP819"              ,	   0x1180080e01998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP820"              ,	   0x1180080e019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP821"              ,	   0x1180080e019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP822"              ,	   0x1180080e019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP823"              ,	   0x1180080e019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP824"              ,	   0x1180080e019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP825"              ,	   0x1180080e019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP826"              ,	   0x1180080e019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP827"              ,	   0x1180080e019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP828"              ,	   0x1180080e019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP829"              ,	   0x1180080e019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP830"              ,	   0x1180080e019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP831"              ,	   0x1180080e019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP832"              ,	   0x1180080e01a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP833"              ,	   0x1180080e01a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP834"              ,	   0x1180080e01a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP835"              ,	   0x1180080e01a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP836"              ,	   0x1180080e01a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP837"              ,	   0x1180080e01a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP838"              ,	   0x1180080e01a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP839"              ,	   0x1180080e01a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP840"              ,	   0x1180080e01a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP841"              ,	   0x1180080e01a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP842"              ,	   0x1180080e01a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP843"              ,	   0x1180080e01a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP844"              ,	   0x1180080e01a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP845"              ,	   0x1180080e01a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP846"              ,	   0x1180080e01a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP847"              ,	   0x1180080e01a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP848"              ,	   0x1180080e01a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP849"              ,	   0x1180080e01a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP850"              ,	   0x1180080e01a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP851"              ,	   0x1180080e01a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP852"              ,	   0x1180080e01aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP853"              ,	   0x1180080e01aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP854"              ,	   0x1180080e01ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP855"              ,	   0x1180080e01ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP856"              ,	   0x1180080e01ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP857"              ,	   0x1180080e01ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP858"              ,	   0x1180080e01ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP859"              ,	   0x1180080e01ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP860"              ,	   0x1180080e01ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP861"              ,	   0x1180080e01ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP862"              ,	   0x1180080e01af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP863"              ,	   0x1180080e01af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP864"              ,	   0x1180080e01b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP865"              ,	   0x1180080e01b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP866"              ,	   0x1180080e01b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP867"              ,	   0x1180080e01b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP868"              ,	   0x1180080e01b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP869"              ,	   0x1180080e01b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP870"              ,	   0x1180080e01b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP871"              ,	   0x1180080e01b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP872"              ,	   0x1180080e01b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP873"              ,	   0x1180080e01b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP874"              ,	   0x1180080e01b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP875"              ,	   0x1180080e01b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP876"              ,	   0x1180080e01b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP877"              ,	   0x1180080e01b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP878"              ,	   0x1180080e01b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP879"              ,	   0x1180080e01b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP880"              ,	   0x1180080e01b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP881"              ,	   0x1180080e01b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP882"              ,	   0x1180080e01b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP883"              ,	   0x1180080e01b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP884"              ,	   0x1180080e01ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP885"              ,	   0x1180080e01ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP886"              ,	   0x1180080e01bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP887"              ,	   0x1180080e01bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP888"              ,	   0x1180080e01bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP889"              ,	   0x1180080e01bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP890"              ,	   0x1180080e01bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP891"              ,	   0x1180080e01bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP892"              ,	   0x1180080e01be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP893"              ,	   0x1180080e01be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP894"              ,	   0x1180080e01bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP895"              ,	   0x1180080e01bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP896"              ,	   0x1180080e01c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP897"              ,	   0x1180080e01c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP898"              ,	   0x1180080e01c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP899"              ,	   0x1180080e01c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP900"              ,	   0x1180080e01c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP901"              ,	   0x1180080e01c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP902"              ,	   0x1180080e01c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP903"              ,	   0x1180080e01c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP904"              ,	   0x1180080e01c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP905"              ,	   0x1180080e01c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP906"              ,	   0x1180080e01c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP907"              ,	   0x1180080e01c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP908"              ,	   0x1180080e01c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP909"              ,	   0x1180080e01c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP910"              ,	   0x1180080e01c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP911"              ,	   0x1180080e01c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP912"              ,	   0x1180080e01c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP913"              ,	   0x1180080e01c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP914"              ,	   0x1180080e01c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP915"              ,	   0x1180080e01c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP916"              ,	   0x1180080e01ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP917"              ,	   0x1180080e01ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP918"              ,	   0x1180080e01cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP919"              ,	   0x1180080e01cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP920"              ,	   0x1180080e01cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP921"              ,	   0x1180080e01cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP922"              ,	   0x1180080e01cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP923"              ,	   0x1180080e01cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP924"              ,	   0x1180080e01ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP925"              ,	   0x1180080e01ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP926"              ,	   0x1180080e01cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP927"              ,	   0x1180080e01cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP928"              ,	   0x1180080e01d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP929"              ,	   0x1180080e01d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP930"              ,	   0x1180080e01d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP931"              ,	   0x1180080e01d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP932"              ,	   0x1180080e01d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP933"              ,	   0x1180080e01d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP934"              ,	   0x1180080e01d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP935"              ,	   0x1180080e01d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP936"              ,	   0x1180080e01d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP937"              ,	   0x1180080e01d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP938"              ,	   0x1180080e01d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP939"              ,	   0x1180080e01d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP940"              ,	   0x1180080e01d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP941"              ,	   0x1180080e01d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP942"              ,	   0x1180080e01d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP943"              ,	   0x1180080e01d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP944"              ,	   0x1180080e01d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP945"              ,	   0x1180080e01d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP946"              ,	   0x1180080e01d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP947"              ,	   0x1180080e01d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP948"              ,	   0x1180080e01da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP949"              ,	   0x1180080e01da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP950"              ,	   0x1180080e01db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP951"              ,	   0x1180080e01db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP952"              ,	   0x1180080e01dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP953"              ,	   0x1180080e01dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP954"              ,	   0x1180080e01dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP955"              ,	   0x1180080e01dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP956"              ,	   0x1180080e01de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP957"              ,	   0x1180080e01de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP958"              ,	   0x1180080e01df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP959"              ,	   0x1180080e01df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP960"              ,	   0x1180080e01e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP961"              ,	   0x1180080e01e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP962"              ,	   0x1180080e01e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP963"              ,	   0x1180080e01e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP964"              ,	   0x1180080e01e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP965"              ,	   0x1180080e01e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP966"              ,	   0x1180080e01e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP967"              ,	   0x1180080e01e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP968"              ,	   0x1180080e01e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP969"              ,	   0x1180080e01e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP970"              ,	   0x1180080e01e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP971"              ,	   0x1180080e01e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP972"              ,	   0x1180080e01e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP973"              ,	   0x1180080e01e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP974"              ,	   0x1180080e01e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP975"              ,	   0x1180080e01e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP976"              ,	   0x1180080e01e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP977"              ,	   0x1180080e01e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP978"              ,	   0x1180080e01e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP979"              ,	   0x1180080e01e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP980"              ,	   0x1180080e01ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP981"              ,	   0x1180080e01ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP982"              ,	   0x1180080e01eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP983"              ,	   0x1180080e01eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP984"              ,	   0x1180080e01ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP985"              ,	   0x1180080e01ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP986"              ,	   0x1180080e01ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP987"              ,	   0x1180080e01ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP988"              ,	   0x1180080e01ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP989"              ,	   0x1180080e01ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP990"              ,	   0x1180080e01ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP991"              ,	   0x1180080e01ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP992"              ,	   0x1180080e01f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP993"              ,	   0x1180080e01f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP994"              ,	   0x1180080e01f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP995"              ,	   0x1180080e01f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP996"              ,	   0x1180080e01f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP997"              ,	   0x1180080e01f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP998"              ,	   0x1180080e01f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP999"              ,	   0x1180080e01f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1000"             ,	   0x1180080e01f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1001"             ,	   0x1180080e01f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1002"             ,	   0x1180080e01f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1003"             ,	   0x1180080e01f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1004"             ,	   0x1180080e01f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1005"             ,	   0x1180080e01f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1006"             ,	   0x1180080e01f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1007"             ,	   0x1180080e01f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1008"             ,	   0x1180080e01f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1009"             ,	   0x1180080e01f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1010"             ,	   0x1180080e01f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1011"             ,	   0x1180080e01f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1012"             ,	   0x1180080e01fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1013"             ,	   0x1180080e01fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1014"             ,	   0x1180080e01fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1015"             ,	   0x1180080e01fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1016"             ,	   0x1180080e01fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1017"             ,	   0x1180080e01fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1018"             ,	   0x1180080e01fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1019"             ,	   0x1180080e01fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1020"             ,	   0x1180080e01fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1021"             ,	   0x1180080e01fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1022"             ,	   0x1180080e01ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1023"             ,	   0x1180080e01ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1024"             ,	   0x1180080e02000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1025"             ,	   0x1180080e02008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1026"             ,	   0x1180080e02010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1027"             ,	   0x1180080e02018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1028"             ,	   0x1180080e02020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1029"             ,	   0x1180080e02028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1030"             ,	   0x1180080e02030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1031"             ,	   0x1180080e02038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1032"             ,	   0x1180080e02040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1033"             ,	   0x1180080e02048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1034"             ,	   0x1180080e02050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1035"             ,	   0x1180080e02058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1036"             ,	   0x1180080e02060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1037"             ,	   0x1180080e02068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1038"             ,	   0x1180080e02070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1039"             ,	   0x1180080e02078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1040"             ,	   0x1180080e02080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1041"             ,	   0x1180080e02088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1042"             ,	   0x1180080e02090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1043"             ,	   0x1180080e02098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1044"             ,	   0x1180080e020a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1045"             ,	   0x1180080e020a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1046"             ,	   0x1180080e020b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1047"             ,	   0x1180080e020b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1048"             ,	   0x1180080e020c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1049"             ,	   0x1180080e020c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1050"             ,	   0x1180080e020d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1051"             ,	   0x1180080e020d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1052"             ,	   0x1180080e020e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1053"             ,	   0x1180080e020e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1054"             ,	   0x1180080e020f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1055"             ,	   0x1180080e020f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1056"             ,	   0x1180080e02100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1057"             ,	   0x1180080e02108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1058"             ,	   0x1180080e02110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1059"             ,	   0x1180080e02118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1060"             ,	   0x1180080e02120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1061"             ,	   0x1180080e02128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1062"             ,	   0x1180080e02130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1063"             ,	   0x1180080e02138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1064"             ,	   0x1180080e02140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1065"             ,	   0x1180080e02148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1066"             ,	   0x1180080e02150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1067"             ,	   0x1180080e02158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1068"             ,	   0x1180080e02160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1069"             ,	   0x1180080e02168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1070"             ,	   0x1180080e02170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1071"             ,	   0x1180080e02178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1072"             ,	   0x1180080e02180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1073"             ,	   0x1180080e02188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1074"             ,	   0x1180080e02190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1075"             ,	   0x1180080e02198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1076"             ,	   0x1180080e021a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1077"             ,	   0x1180080e021a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1078"             ,	   0x1180080e021b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1079"             ,	   0x1180080e021b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1080"             ,	   0x1180080e021c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1081"             ,	   0x1180080e021c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1082"             ,	   0x1180080e021d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1083"             ,	   0x1180080e021d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1084"             ,	   0x1180080e021e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1085"             ,	   0x1180080e021e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1086"             ,	   0x1180080e021f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1087"             ,	   0x1180080e021f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1088"             ,	   0x1180080e02200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1089"             ,	   0x1180080e02208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1090"             ,	   0x1180080e02210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1091"             ,	   0x1180080e02218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1092"             ,	   0x1180080e02220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1093"             ,	   0x1180080e02228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1094"             ,	   0x1180080e02230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1095"             ,	   0x1180080e02238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1096"             ,	   0x1180080e02240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1097"             ,	   0x1180080e02248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1098"             ,	   0x1180080e02250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1099"             ,	   0x1180080e02258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1100"             ,	   0x1180080e02260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1101"             ,	   0x1180080e02268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1102"             ,	   0x1180080e02270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1103"             ,	   0x1180080e02278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1104"             ,	   0x1180080e02280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1105"             ,	   0x1180080e02288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1106"             ,	   0x1180080e02290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1107"             ,	   0x1180080e02298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1108"             ,	   0x1180080e022a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1109"             ,	   0x1180080e022a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1110"             ,	   0x1180080e022b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1111"             ,	   0x1180080e022b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1112"             ,	   0x1180080e022c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1113"             ,	   0x1180080e022c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1114"             ,	   0x1180080e022d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1115"             ,	   0x1180080e022d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1116"             ,	   0x1180080e022e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1117"             ,	   0x1180080e022e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1118"             ,	   0x1180080e022f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1119"             ,	   0x1180080e022f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1120"             ,	   0x1180080e02300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1121"             ,	   0x1180080e02308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1122"             ,	   0x1180080e02310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1123"             ,	   0x1180080e02318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1124"             ,	   0x1180080e02320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1125"             ,	   0x1180080e02328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1126"             ,	   0x1180080e02330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1127"             ,	   0x1180080e02338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1128"             ,	   0x1180080e02340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1129"             ,	   0x1180080e02348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1130"             ,	   0x1180080e02350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1131"             ,	   0x1180080e02358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1132"             ,	   0x1180080e02360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1133"             ,	   0x1180080e02368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1134"             ,	   0x1180080e02370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1135"             ,	   0x1180080e02378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1136"             ,	   0x1180080e02380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1137"             ,	   0x1180080e02388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1138"             ,	   0x1180080e02390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1139"             ,	   0x1180080e02398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1140"             ,	   0x1180080e023a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1141"             ,	   0x1180080e023a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1142"             ,	   0x1180080e023b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1143"             ,	   0x1180080e023b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1144"             ,	   0x1180080e023c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1145"             ,	   0x1180080e023c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1146"             ,	   0x1180080e023d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1147"             ,	   0x1180080e023d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1148"             ,	   0x1180080e023e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1149"             ,	   0x1180080e023e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1150"             ,	   0x1180080e023f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1151"             ,	   0x1180080e023f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1152"             ,	   0x1180080e02400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1153"             ,	   0x1180080e02408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1154"             ,	   0x1180080e02410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1155"             ,	   0x1180080e02418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1156"             ,	   0x1180080e02420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1157"             ,	   0x1180080e02428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1158"             ,	   0x1180080e02430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1159"             ,	   0x1180080e02438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1160"             ,	   0x1180080e02440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1161"             ,	   0x1180080e02448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1162"             ,	   0x1180080e02450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1163"             ,	   0x1180080e02458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1164"             ,	   0x1180080e02460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1165"             ,	   0x1180080e02468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1166"             ,	   0x1180080e02470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1167"             ,	   0x1180080e02478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1168"             ,	   0x1180080e02480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1169"             ,	   0x1180080e02488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1170"             ,	   0x1180080e02490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1171"             ,	   0x1180080e02498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1172"             ,	   0x1180080e024a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1173"             ,	   0x1180080e024a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1174"             ,	   0x1180080e024b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1175"             ,	   0x1180080e024b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1176"             ,	   0x1180080e024c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1177"             ,	   0x1180080e024c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1178"             ,	   0x1180080e024d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1179"             ,	   0x1180080e024d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1180"             ,	   0x1180080e024e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1181"             ,	   0x1180080e024e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1182"             ,	   0x1180080e024f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1183"             ,	   0x1180080e024f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1184"             ,	   0x1180080e02500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1185"             ,	   0x1180080e02508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1186"             ,	   0x1180080e02510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1187"             ,	   0x1180080e02518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1188"             ,	   0x1180080e02520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1189"             ,	   0x1180080e02528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1190"             ,	   0x1180080e02530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1191"             ,	   0x1180080e02538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1192"             ,	   0x1180080e02540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1193"             ,	   0x1180080e02548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1194"             ,	   0x1180080e02550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1195"             ,	   0x1180080e02558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1196"             ,	   0x1180080e02560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1197"             ,	   0x1180080e02568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1198"             ,	   0x1180080e02570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1199"             ,	   0x1180080e02578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1200"             ,	   0x1180080e02580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1201"             ,	   0x1180080e02588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1202"             ,	   0x1180080e02590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1203"             ,	   0x1180080e02598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1204"             ,	   0x1180080e025a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1205"             ,	   0x1180080e025a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1206"             ,	   0x1180080e025b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1207"             ,	   0x1180080e025b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1208"             ,	   0x1180080e025c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1209"             ,	   0x1180080e025c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1210"             ,	   0x1180080e025d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1211"             ,	   0x1180080e025d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1212"             ,	   0x1180080e025e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1213"             ,	   0x1180080e025e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1214"             ,	   0x1180080e025f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1215"             ,	   0x1180080e025f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1216"             ,	   0x1180080e02600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1217"             ,	   0x1180080e02608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1218"             ,	   0x1180080e02610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1219"             ,	   0x1180080e02618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1220"             ,	   0x1180080e02620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1221"             ,	   0x1180080e02628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1222"             ,	   0x1180080e02630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1223"             ,	   0x1180080e02638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1224"             ,	   0x1180080e02640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1225"             ,	   0x1180080e02648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1226"             ,	   0x1180080e02650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1227"             ,	   0x1180080e02658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1228"             ,	   0x1180080e02660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1229"             ,	   0x1180080e02668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1230"             ,	   0x1180080e02670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1231"             ,	   0x1180080e02678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1232"             ,	   0x1180080e02680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1233"             ,	   0x1180080e02688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1234"             ,	   0x1180080e02690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1235"             ,	   0x1180080e02698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1236"             ,	   0x1180080e026a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1237"             ,	   0x1180080e026a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1238"             ,	   0x1180080e026b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1239"             ,	   0x1180080e026b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1240"             ,	   0x1180080e026c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1241"             ,	   0x1180080e026c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1242"             ,	   0x1180080e026d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1243"             ,	   0x1180080e026d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1244"             ,	   0x1180080e026e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1245"             ,	   0x1180080e026e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1246"             ,	   0x1180080e026f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1247"             ,	   0x1180080e026f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1248"             ,	   0x1180080e02700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1249"             ,	   0x1180080e02708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1250"             ,	   0x1180080e02710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1251"             ,	   0x1180080e02718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1252"             ,	   0x1180080e02720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1253"             ,	   0x1180080e02728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1254"             ,	   0x1180080e02730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1255"             ,	   0x1180080e02738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1256"             ,	   0x1180080e02740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1257"             ,	   0x1180080e02748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1258"             ,	   0x1180080e02750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1259"             ,	   0x1180080e02758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1260"             ,	   0x1180080e02760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1261"             ,	   0x1180080e02768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1262"             ,	   0x1180080e02770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1263"             ,	   0x1180080e02778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1264"             ,	   0x1180080e02780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1265"             ,	   0x1180080e02788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1266"             ,	   0x1180080e02790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1267"             ,	   0x1180080e02798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1268"             ,	   0x1180080e027a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1269"             ,	   0x1180080e027a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1270"             ,	   0x1180080e027b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1271"             ,	   0x1180080e027b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1272"             ,	   0x1180080e027c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1273"             ,	   0x1180080e027c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1274"             ,	   0x1180080e027d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1275"             ,	   0x1180080e027d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1276"             ,	   0x1180080e027e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1277"             ,	   0x1180080e027e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1278"             ,	   0x1180080e027f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1279"             ,	   0x1180080e027f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1280"             ,	   0x1180080e02800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1281"             ,	   0x1180080e02808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1282"             ,	   0x1180080e02810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1283"             ,	   0x1180080e02818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1284"             ,	   0x1180080e02820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1285"             ,	   0x1180080e02828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1286"             ,	   0x1180080e02830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1287"             ,	   0x1180080e02838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1288"             ,	   0x1180080e02840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1289"             ,	   0x1180080e02848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1290"             ,	   0x1180080e02850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1291"             ,	   0x1180080e02858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1292"             ,	   0x1180080e02860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1293"             ,	   0x1180080e02868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1294"             ,	   0x1180080e02870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1295"             ,	   0x1180080e02878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1296"             ,	   0x1180080e02880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1297"             ,	   0x1180080e02888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1298"             ,	   0x1180080e02890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1299"             ,	   0x1180080e02898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1300"             ,	   0x1180080e028a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1301"             ,	   0x1180080e028a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1302"             ,	   0x1180080e028b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1303"             ,	   0x1180080e028b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1304"             ,	   0x1180080e028c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1305"             ,	   0x1180080e028c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1306"             ,	   0x1180080e028d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1307"             ,	   0x1180080e028d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1308"             ,	   0x1180080e028e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1309"             ,	   0x1180080e028e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1310"             ,	   0x1180080e028f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1311"             ,	   0x1180080e028f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1312"             ,	   0x1180080e02900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1313"             ,	   0x1180080e02908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1314"             ,	   0x1180080e02910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1315"             ,	   0x1180080e02918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1316"             ,	   0x1180080e02920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1317"             ,	   0x1180080e02928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1318"             ,	   0x1180080e02930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1319"             ,	   0x1180080e02938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1320"             ,	   0x1180080e02940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1321"             ,	   0x1180080e02948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1322"             ,	   0x1180080e02950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1323"             ,	   0x1180080e02958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1324"             ,	   0x1180080e02960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1325"             ,	   0x1180080e02968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1326"             ,	   0x1180080e02970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1327"             ,	   0x1180080e02978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1328"             ,	   0x1180080e02980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1329"             ,	   0x1180080e02988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1330"             ,	   0x1180080e02990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1331"             ,	   0x1180080e02998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1332"             ,	   0x1180080e029a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1333"             ,	   0x1180080e029a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1334"             ,	   0x1180080e029b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1335"             ,	   0x1180080e029b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1336"             ,	   0x1180080e029c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1337"             ,	   0x1180080e029c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1338"             ,	   0x1180080e029d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1339"             ,	   0x1180080e029d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1340"             ,	   0x1180080e029e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1341"             ,	   0x1180080e029e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1342"             ,	   0x1180080e029f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1343"             ,	   0x1180080e029f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1344"             ,	   0x1180080e02a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1345"             ,	   0x1180080e02a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1346"             ,	   0x1180080e02a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1347"             ,	   0x1180080e02a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1348"             ,	   0x1180080e02a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1349"             ,	   0x1180080e02a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1350"             ,	   0x1180080e02a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1351"             ,	   0x1180080e02a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1352"             ,	   0x1180080e02a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1353"             ,	   0x1180080e02a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1354"             ,	   0x1180080e02a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1355"             ,	   0x1180080e02a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1356"             ,	   0x1180080e02a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1357"             ,	   0x1180080e02a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1358"             ,	   0x1180080e02a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1359"             ,	   0x1180080e02a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1360"             ,	   0x1180080e02a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1361"             ,	   0x1180080e02a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1362"             ,	   0x1180080e02a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1363"             ,	   0x1180080e02a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1364"             ,	   0x1180080e02aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1365"             ,	   0x1180080e02aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1366"             ,	   0x1180080e02ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1367"             ,	   0x1180080e02ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1368"             ,	   0x1180080e02ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1369"             ,	   0x1180080e02ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1370"             ,	   0x1180080e02ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1371"             ,	   0x1180080e02ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1372"             ,	   0x1180080e02ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1373"             ,	   0x1180080e02ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1374"             ,	   0x1180080e02af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1375"             ,	   0x1180080e02af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1376"             ,	   0x1180080e02b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1377"             ,	   0x1180080e02b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1378"             ,	   0x1180080e02b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1379"             ,	   0x1180080e02b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1380"             ,	   0x1180080e02b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1381"             ,	   0x1180080e02b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1382"             ,	   0x1180080e02b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1383"             ,	   0x1180080e02b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1384"             ,	   0x1180080e02b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1385"             ,	   0x1180080e02b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1386"             ,	   0x1180080e02b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1387"             ,	   0x1180080e02b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1388"             ,	   0x1180080e02b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1389"             ,	   0x1180080e02b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1390"             ,	   0x1180080e02b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1391"             ,	   0x1180080e02b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1392"             ,	   0x1180080e02b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1393"             ,	   0x1180080e02b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1394"             ,	   0x1180080e02b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1395"             ,	   0x1180080e02b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1396"             ,	   0x1180080e02ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1397"             ,	   0x1180080e02ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1398"             ,	   0x1180080e02bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1399"             ,	   0x1180080e02bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1400"             ,	   0x1180080e02bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1401"             ,	   0x1180080e02bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1402"             ,	   0x1180080e02bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1403"             ,	   0x1180080e02bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1404"             ,	   0x1180080e02be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1405"             ,	   0x1180080e02be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1406"             ,	   0x1180080e02bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1407"             ,	   0x1180080e02bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1408"             ,	   0x1180080e02c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1409"             ,	   0x1180080e02c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1410"             ,	   0x1180080e02c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1411"             ,	   0x1180080e02c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1412"             ,	   0x1180080e02c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1413"             ,	   0x1180080e02c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1414"             ,	   0x1180080e02c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1415"             ,	   0x1180080e02c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1416"             ,	   0x1180080e02c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1417"             ,	   0x1180080e02c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1418"             ,	   0x1180080e02c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1419"             ,	   0x1180080e02c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1420"             ,	   0x1180080e02c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1421"             ,	   0x1180080e02c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1422"             ,	   0x1180080e02c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1423"             ,	   0x1180080e02c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1424"             ,	   0x1180080e02c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1425"             ,	   0x1180080e02c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1426"             ,	   0x1180080e02c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1427"             ,	   0x1180080e02c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1428"             ,	   0x1180080e02ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1429"             ,	   0x1180080e02ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1430"             ,	   0x1180080e02cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1431"             ,	   0x1180080e02cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1432"             ,	   0x1180080e02cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1433"             ,	   0x1180080e02cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1434"             ,	   0x1180080e02cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1435"             ,	   0x1180080e02cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1436"             ,	   0x1180080e02ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1437"             ,	   0x1180080e02ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1438"             ,	   0x1180080e02cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1439"             ,	   0x1180080e02cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1440"             ,	   0x1180080e02d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1441"             ,	   0x1180080e02d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1442"             ,	   0x1180080e02d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1443"             ,	   0x1180080e02d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1444"             ,	   0x1180080e02d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1445"             ,	   0x1180080e02d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1446"             ,	   0x1180080e02d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1447"             ,	   0x1180080e02d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1448"             ,	   0x1180080e02d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1449"             ,	   0x1180080e02d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1450"             ,	   0x1180080e02d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1451"             ,	   0x1180080e02d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1452"             ,	   0x1180080e02d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1453"             ,	   0x1180080e02d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1454"             ,	   0x1180080e02d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1455"             ,	   0x1180080e02d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1456"             ,	   0x1180080e02d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1457"             ,	   0x1180080e02d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1458"             ,	   0x1180080e02d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1459"             ,	   0x1180080e02d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1460"             ,	   0x1180080e02da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1461"             ,	   0x1180080e02da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1462"             ,	   0x1180080e02db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1463"             ,	   0x1180080e02db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1464"             ,	   0x1180080e02dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1465"             ,	   0x1180080e02dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1466"             ,	   0x1180080e02dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1467"             ,	   0x1180080e02dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1468"             ,	   0x1180080e02de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1469"             ,	   0x1180080e02de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1470"             ,	   0x1180080e02df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1471"             ,	   0x1180080e02df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1472"             ,	   0x1180080e02e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1473"             ,	   0x1180080e02e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1474"             ,	   0x1180080e02e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1475"             ,	   0x1180080e02e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1476"             ,	   0x1180080e02e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1477"             ,	   0x1180080e02e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1478"             ,	   0x1180080e02e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1479"             ,	   0x1180080e02e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1480"             ,	   0x1180080e02e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1481"             ,	   0x1180080e02e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1482"             ,	   0x1180080e02e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1483"             ,	   0x1180080e02e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1484"             ,	   0x1180080e02e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1485"             ,	   0x1180080e02e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1486"             ,	   0x1180080e02e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1487"             ,	   0x1180080e02e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1488"             ,	   0x1180080e02e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1489"             ,	   0x1180080e02e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1490"             ,	   0x1180080e02e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1491"             ,	   0x1180080e02e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1492"             ,	   0x1180080e02ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1493"             ,	   0x1180080e02ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1494"             ,	   0x1180080e02eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1495"             ,	   0x1180080e02eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1496"             ,	   0x1180080e02ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1497"             ,	   0x1180080e02ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1498"             ,	   0x1180080e02ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1499"             ,	   0x1180080e02ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1500"             ,	   0x1180080e02ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1501"             ,	   0x1180080e02ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1502"             ,	   0x1180080e02ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1503"             ,	   0x1180080e02ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1504"             ,	   0x1180080e02f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1505"             ,	   0x1180080e02f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1506"             ,	   0x1180080e02f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1507"             ,	   0x1180080e02f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1508"             ,	   0x1180080e02f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1509"             ,	   0x1180080e02f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1510"             ,	   0x1180080e02f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1511"             ,	   0x1180080e02f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1512"             ,	   0x1180080e02f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1513"             ,	   0x1180080e02f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1514"             ,	   0x1180080e02f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1515"             ,	   0x1180080e02f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1516"             ,	   0x1180080e02f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1517"             ,	   0x1180080e02f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1518"             ,	   0x1180080e02f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1519"             ,	   0x1180080e02f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1520"             ,	   0x1180080e02f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1521"             ,	   0x1180080e02f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1522"             ,	   0x1180080e02f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1523"             ,	   0x1180080e02f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1524"             ,	   0x1180080e02fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1525"             ,	   0x1180080e02fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1526"             ,	   0x1180080e02fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1527"             ,	   0x1180080e02fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1528"             ,	   0x1180080e02fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1529"             ,	   0x1180080e02fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1530"             ,	   0x1180080e02fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1531"             ,	   0x1180080e02fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1532"             ,	   0x1180080e02fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1533"             ,	   0x1180080e02fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1534"             ,	   0x1180080e02ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1535"             ,	   0x1180080e02ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1536"             ,	   0x1180080e03000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1537"             ,	   0x1180080e03008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1538"             ,	   0x1180080e03010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1539"             ,	   0x1180080e03018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1540"             ,	   0x1180080e03020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1541"             ,	   0x1180080e03028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1542"             ,	   0x1180080e03030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1543"             ,	   0x1180080e03038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1544"             ,	   0x1180080e03040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1545"             ,	   0x1180080e03048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1546"             ,	   0x1180080e03050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1547"             ,	   0x1180080e03058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1548"             ,	   0x1180080e03060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1549"             ,	   0x1180080e03068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1550"             ,	   0x1180080e03070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1551"             ,	   0x1180080e03078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1552"             ,	   0x1180080e03080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1553"             ,	   0x1180080e03088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1554"             ,	   0x1180080e03090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1555"             ,	   0x1180080e03098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1556"             ,	   0x1180080e030a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1557"             ,	   0x1180080e030a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1558"             ,	   0x1180080e030b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1559"             ,	   0x1180080e030b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1560"             ,	   0x1180080e030c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1561"             ,	   0x1180080e030c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1562"             ,	   0x1180080e030d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1563"             ,	   0x1180080e030d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1564"             ,	   0x1180080e030e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1565"             ,	   0x1180080e030e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1566"             ,	   0x1180080e030f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1567"             ,	   0x1180080e030f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1568"             ,	   0x1180080e03100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1569"             ,	   0x1180080e03108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1570"             ,	   0x1180080e03110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1571"             ,	   0x1180080e03118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1572"             ,	   0x1180080e03120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1573"             ,	   0x1180080e03128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1574"             ,	   0x1180080e03130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1575"             ,	   0x1180080e03138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1576"             ,	   0x1180080e03140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1577"             ,	   0x1180080e03148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1578"             ,	   0x1180080e03150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1579"             ,	   0x1180080e03158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1580"             ,	   0x1180080e03160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1581"             ,	   0x1180080e03168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1582"             ,	   0x1180080e03170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1583"             ,	   0x1180080e03178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1584"             ,	   0x1180080e03180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1585"             ,	   0x1180080e03188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1586"             ,	   0x1180080e03190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1587"             ,	   0x1180080e03198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1588"             ,	   0x1180080e031a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1589"             ,	   0x1180080e031a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1590"             ,	   0x1180080e031b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1591"             ,	   0x1180080e031b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1592"             ,	   0x1180080e031c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1593"             ,	   0x1180080e031c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1594"             ,	   0x1180080e031d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1595"             ,	   0x1180080e031d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1596"             ,	   0x1180080e031e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1597"             ,	   0x1180080e031e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1598"             ,	   0x1180080e031f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1599"             ,	   0x1180080e031f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1600"             ,	   0x1180080e03200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1601"             ,	   0x1180080e03208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1602"             ,	   0x1180080e03210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1603"             ,	   0x1180080e03218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1604"             ,	   0x1180080e03220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1605"             ,	   0x1180080e03228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1606"             ,	   0x1180080e03230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1607"             ,	   0x1180080e03238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1608"             ,	   0x1180080e03240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1609"             ,	   0x1180080e03248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1610"             ,	   0x1180080e03250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1611"             ,	   0x1180080e03258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1612"             ,	   0x1180080e03260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1613"             ,	   0x1180080e03268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1614"             ,	   0x1180080e03270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1615"             ,	   0x1180080e03278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1616"             ,	   0x1180080e03280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1617"             ,	   0x1180080e03288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1618"             ,	   0x1180080e03290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1619"             ,	   0x1180080e03298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1620"             ,	   0x1180080e032a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1621"             ,	   0x1180080e032a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1622"             ,	   0x1180080e032b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1623"             ,	   0x1180080e032b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1624"             ,	   0x1180080e032c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1625"             ,	   0x1180080e032c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1626"             ,	   0x1180080e032d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1627"             ,	   0x1180080e032d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1628"             ,	   0x1180080e032e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1629"             ,	   0x1180080e032e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1630"             ,	   0x1180080e032f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1631"             ,	   0x1180080e032f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1632"             ,	   0x1180080e03300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1633"             ,	   0x1180080e03308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1634"             ,	   0x1180080e03310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1635"             ,	   0x1180080e03318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1636"             ,	   0x1180080e03320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1637"             ,	   0x1180080e03328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1638"             ,	   0x1180080e03330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1639"             ,	   0x1180080e03338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1640"             ,	   0x1180080e03340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1641"             ,	   0x1180080e03348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1642"             ,	   0x1180080e03350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1643"             ,	   0x1180080e03358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1644"             ,	   0x1180080e03360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1645"             ,	   0x1180080e03368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1646"             ,	   0x1180080e03370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1647"             ,	   0x1180080e03378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1648"             ,	   0x1180080e03380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1649"             ,	   0x1180080e03388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1650"             ,	   0x1180080e03390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1651"             ,	   0x1180080e03398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1652"             ,	   0x1180080e033a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1653"             ,	   0x1180080e033a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1654"             ,	   0x1180080e033b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1655"             ,	   0x1180080e033b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1656"             ,	   0x1180080e033c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1657"             ,	   0x1180080e033c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1658"             ,	   0x1180080e033d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1659"             ,	   0x1180080e033d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1660"             ,	   0x1180080e033e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1661"             ,	   0x1180080e033e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1662"             ,	   0x1180080e033f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1663"             ,	   0x1180080e033f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1664"             ,	   0x1180080e03400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1665"             ,	   0x1180080e03408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1666"             ,	   0x1180080e03410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1667"             ,	   0x1180080e03418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1668"             ,	   0x1180080e03420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1669"             ,	   0x1180080e03428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1670"             ,	   0x1180080e03430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1671"             ,	   0x1180080e03438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1672"             ,	   0x1180080e03440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1673"             ,	   0x1180080e03448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1674"             ,	   0x1180080e03450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1675"             ,	   0x1180080e03458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1676"             ,	   0x1180080e03460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1677"             ,	   0x1180080e03468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1678"             ,	   0x1180080e03470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1679"             ,	   0x1180080e03478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1680"             ,	   0x1180080e03480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1681"             ,	   0x1180080e03488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1682"             ,	   0x1180080e03490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1683"             ,	   0x1180080e03498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1684"             ,	   0x1180080e034a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1685"             ,	   0x1180080e034a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1686"             ,	   0x1180080e034b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1687"             ,	   0x1180080e034b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1688"             ,	   0x1180080e034c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1689"             ,	   0x1180080e034c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1690"             ,	   0x1180080e034d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1691"             ,	   0x1180080e034d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1692"             ,	   0x1180080e034e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1693"             ,	   0x1180080e034e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1694"             ,	   0x1180080e034f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1695"             ,	   0x1180080e034f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1696"             ,	   0x1180080e03500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1697"             ,	   0x1180080e03508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1698"             ,	   0x1180080e03510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1699"             ,	   0x1180080e03518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1700"             ,	   0x1180080e03520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1701"             ,	   0x1180080e03528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1702"             ,	   0x1180080e03530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1703"             ,	   0x1180080e03538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1704"             ,	   0x1180080e03540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1705"             ,	   0x1180080e03548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1706"             ,	   0x1180080e03550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1707"             ,	   0x1180080e03558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1708"             ,	   0x1180080e03560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1709"             ,	   0x1180080e03568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1710"             ,	   0x1180080e03570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1711"             ,	   0x1180080e03578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1712"             ,	   0x1180080e03580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1713"             ,	   0x1180080e03588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1714"             ,	   0x1180080e03590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1715"             ,	   0x1180080e03598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1716"             ,	   0x1180080e035a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1717"             ,	   0x1180080e035a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1718"             ,	   0x1180080e035b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1719"             ,	   0x1180080e035b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1720"             ,	   0x1180080e035c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1721"             ,	   0x1180080e035c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1722"             ,	   0x1180080e035d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1723"             ,	   0x1180080e035d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1724"             ,	   0x1180080e035e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1725"             ,	   0x1180080e035e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1726"             ,	   0x1180080e035f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1727"             ,	   0x1180080e035f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1728"             ,	   0x1180080e03600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1729"             ,	   0x1180080e03608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1730"             ,	   0x1180080e03610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1731"             ,	   0x1180080e03618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1732"             ,	   0x1180080e03620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1733"             ,	   0x1180080e03628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1734"             ,	   0x1180080e03630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1735"             ,	   0x1180080e03638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1736"             ,	   0x1180080e03640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1737"             ,	   0x1180080e03648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1738"             ,	   0x1180080e03650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1739"             ,	   0x1180080e03658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1740"             ,	   0x1180080e03660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1741"             ,	   0x1180080e03668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1742"             ,	   0x1180080e03670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1743"             ,	   0x1180080e03678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1744"             ,	   0x1180080e03680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1745"             ,	   0x1180080e03688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1746"             ,	   0x1180080e03690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1747"             ,	   0x1180080e03698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1748"             ,	   0x1180080e036a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1749"             ,	   0x1180080e036a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1750"             ,	   0x1180080e036b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1751"             ,	   0x1180080e036b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1752"             ,	   0x1180080e036c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1753"             ,	   0x1180080e036c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1754"             ,	   0x1180080e036d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1755"             ,	   0x1180080e036d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1756"             ,	   0x1180080e036e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1757"             ,	   0x1180080e036e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1758"             ,	   0x1180080e036f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1759"             ,	   0x1180080e036f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1760"             ,	   0x1180080e03700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1761"             ,	   0x1180080e03708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1762"             ,	   0x1180080e03710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1763"             ,	   0x1180080e03718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1764"             ,	   0x1180080e03720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1765"             ,	   0x1180080e03728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1766"             ,	   0x1180080e03730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1767"             ,	   0x1180080e03738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1768"             ,	   0x1180080e03740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1769"             ,	   0x1180080e03748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1770"             ,	   0x1180080e03750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1771"             ,	   0x1180080e03758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1772"             ,	   0x1180080e03760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1773"             ,	   0x1180080e03768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1774"             ,	   0x1180080e03770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1775"             ,	   0x1180080e03778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1776"             ,	   0x1180080e03780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1777"             ,	   0x1180080e03788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1778"             ,	   0x1180080e03790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1779"             ,	   0x1180080e03798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1780"             ,	   0x1180080e037a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1781"             ,	   0x1180080e037a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1782"             ,	   0x1180080e037b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1783"             ,	   0x1180080e037b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1784"             ,	   0x1180080e037c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1785"             ,	   0x1180080e037c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1786"             ,	   0x1180080e037d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1787"             ,	   0x1180080e037d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1788"             ,	   0x1180080e037e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1789"             ,	   0x1180080e037e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1790"             ,	   0x1180080e037f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1791"             ,	   0x1180080e037f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1792"             ,	   0x1180080e03800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1793"             ,	   0x1180080e03808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1794"             ,	   0x1180080e03810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1795"             ,	   0x1180080e03818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1796"             ,	   0x1180080e03820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1797"             ,	   0x1180080e03828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1798"             ,	   0x1180080e03830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1799"             ,	   0x1180080e03838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1800"             ,	   0x1180080e03840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1801"             ,	   0x1180080e03848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1802"             ,	   0x1180080e03850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1803"             ,	   0x1180080e03858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1804"             ,	   0x1180080e03860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1805"             ,	   0x1180080e03868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1806"             ,	   0x1180080e03870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1807"             ,	   0x1180080e03878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1808"             ,	   0x1180080e03880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1809"             ,	   0x1180080e03888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1810"             ,	   0x1180080e03890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1811"             ,	   0x1180080e03898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1812"             ,	   0x1180080e038a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1813"             ,	   0x1180080e038a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1814"             ,	   0x1180080e038b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1815"             ,	   0x1180080e038b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1816"             ,	   0x1180080e038c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1817"             ,	   0x1180080e038c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1818"             ,	   0x1180080e038d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1819"             ,	   0x1180080e038d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1820"             ,	   0x1180080e038e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1821"             ,	   0x1180080e038e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1822"             ,	   0x1180080e038f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1823"             ,	   0x1180080e038f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1824"             ,	   0x1180080e03900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1825"             ,	   0x1180080e03908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1826"             ,	   0x1180080e03910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1827"             ,	   0x1180080e03918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1828"             ,	   0x1180080e03920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1829"             ,	   0x1180080e03928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1830"             ,	   0x1180080e03930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1831"             ,	   0x1180080e03938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1832"             ,	   0x1180080e03940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1833"             ,	   0x1180080e03948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1834"             ,	   0x1180080e03950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1835"             ,	   0x1180080e03958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1836"             ,	   0x1180080e03960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1837"             ,	   0x1180080e03968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1838"             ,	   0x1180080e03970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1839"             ,	   0x1180080e03978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1840"             ,	   0x1180080e03980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1841"             ,	   0x1180080e03988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1842"             ,	   0x1180080e03990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1843"             ,	   0x1180080e03998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1844"             ,	   0x1180080e039a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1845"             ,	   0x1180080e039a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1846"             ,	   0x1180080e039b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1847"             ,	   0x1180080e039b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1848"             ,	   0x1180080e039c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1849"             ,	   0x1180080e039c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1850"             ,	   0x1180080e039d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1851"             ,	   0x1180080e039d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1852"             ,	   0x1180080e039e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1853"             ,	   0x1180080e039e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1854"             ,	   0x1180080e039f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1855"             ,	   0x1180080e039f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1856"             ,	   0x1180080e03a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1857"             ,	   0x1180080e03a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1858"             ,	   0x1180080e03a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1859"             ,	   0x1180080e03a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1860"             ,	   0x1180080e03a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1861"             ,	   0x1180080e03a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1862"             ,	   0x1180080e03a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1863"             ,	   0x1180080e03a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1864"             ,	   0x1180080e03a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1865"             ,	   0x1180080e03a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1866"             ,	   0x1180080e03a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1867"             ,	   0x1180080e03a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1868"             ,	   0x1180080e03a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1869"             ,	   0x1180080e03a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1870"             ,	   0x1180080e03a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1871"             ,	   0x1180080e03a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1872"             ,	   0x1180080e03a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1873"             ,	   0x1180080e03a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1874"             ,	   0x1180080e03a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1875"             ,	   0x1180080e03a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1876"             ,	   0x1180080e03aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1877"             ,	   0x1180080e03aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1878"             ,	   0x1180080e03ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1879"             ,	   0x1180080e03ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1880"             ,	   0x1180080e03ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1881"             ,	   0x1180080e03ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1882"             ,	   0x1180080e03ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1883"             ,	   0x1180080e03ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1884"             ,	   0x1180080e03ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1885"             ,	   0x1180080e03ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1886"             ,	   0x1180080e03af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1887"             ,	   0x1180080e03af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1888"             ,	   0x1180080e03b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1889"             ,	   0x1180080e03b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1890"             ,	   0x1180080e03b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1891"             ,	   0x1180080e03b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1892"             ,	   0x1180080e03b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1893"             ,	   0x1180080e03b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1894"             ,	   0x1180080e03b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1895"             ,	   0x1180080e03b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1896"             ,	   0x1180080e03b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1897"             ,	   0x1180080e03b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1898"             ,	   0x1180080e03b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1899"             ,	   0x1180080e03b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1900"             ,	   0x1180080e03b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1901"             ,	   0x1180080e03b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1902"             ,	   0x1180080e03b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1903"             ,	   0x1180080e03b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1904"             ,	   0x1180080e03b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1905"             ,	   0x1180080e03b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1906"             ,	   0x1180080e03b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1907"             ,	   0x1180080e03b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1908"             ,	   0x1180080e03ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1909"             ,	   0x1180080e03ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1910"             ,	   0x1180080e03bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1911"             ,	   0x1180080e03bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1912"             ,	   0x1180080e03bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1913"             ,	   0x1180080e03bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1914"             ,	   0x1180080e03bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1915"             ,	   0x1180080e03bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1916"             ,	   0x1180080e03be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1917"             ,	   0x1180080e03be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1918"             ,	   0x1180080e03bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1919"             ,	   0x1180080e03bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1920"             ,	   0x1180080e03c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1921"             ,	   0x1180080e03c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1922"             ,	   0x1180080e03c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1923"             ,	   0x1180080e03c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1924"             ,	   0x1180080e03c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1925"             ,	   0x1180080e03c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1926"             ,	   0x1180080e03c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1927"             ,	   0x1180080e03c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1928"             ,	   0x1180080e03c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1929"             ,	   0x1180080e03c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1930"             ,	   0x1180080e03c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1931"             ,	   0x1180080e03c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1932"             ,	   0x1180080e03c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1933"             ,	   0x1180080e03c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1934"             ,	   0x1180080e03c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1935"             ,	   0x1180080e03c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1936"             ,	   0x1180080e03c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1937"             ,	   0x1180080e03c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1938"             ,	   0x1180080e03c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1939"             ,	   0x1180080e03c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1940"             ,	   0x1180080e03ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1941"             ,	   0x1180080e03ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1942"             ,	   0x1180080e03cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1943"             ,	   0x1180080e03cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1944"             ,	   0x1180080e03cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1945"             ,	   0x1180080e03cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1946"             ,	   0x1180080e03cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1947"             ,	   0x1180080e03cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1948"             ,	   0x1180080e03ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1949"             ,	   0x1180080e03ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1950"             ,	   0x1180080e03cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1951"             ,	   0x1180080e03cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1952"             ,	   0x1180080e03d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1953"             ,	   0x1180080e03d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1954"             ,	   0x1180080e03d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1955"             ,	   0x1180080e03d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1956"             ,	   0x1180080e03d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1957"             ,	   0x1180080e03d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1958"             ,	   0x1180080e03d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1959"             ,	   0x1180080e03d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1960"             ,	   0x1180080e03d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1961"             ,	   0x1180080e03d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1962"             ,	   0x1180080e03d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1963"             ,	   0x1180080e03d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1964"             ,	   0x1180080e03d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1965"             ,	   0x1180080e03d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1966"             ,	   0x1180080e03d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1967"             ,	   0x1180080e03d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1968"             ,	   0x1180080e03d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1969"             ,	   0x1180080e03d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1970"             ,	   0x1180080e03d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1971"             ,	   0x1180080e03d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1972"             ,	   0x1180080e03da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1973"             ,	   0x1180080e03da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1974"             ,	   0x1180080e03db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1975"             ,	   0x1180080e03db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1976"             ,	   0x1180080e03dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1977"             ,	   0x1180080e03dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1978"             ,	   0x1180080e03dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1979"             ,	   0x1180080e03dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1980"             ,	   0x1180080e03de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1981"             ,	   0x1180080e03de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1982"             ,	   0x1180080e03df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1983"             ,	   0x1180080e03df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1984"             ,	   0x1180080e03e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1985"             ,	   0x1180080e03e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1986"             ,	   0x1180080e03e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1987"             ,	   0x1180080e03e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1988"             ,	   0x1180080e03e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1989"             ,	   0x1180080e03e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1990"             ,	   0x1180080e03e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1991"             ,	   0x1180080e03e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1992"             ,	   0x1180080e03e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1993"             ,	   0x1180080e03e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1994"             ,	   0x1180080e03e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1995"             ,	   0x1180080e03e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1996"             ,	   0x1180080e03e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1997"             ,	   0x1180080e03e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1998"             ,	   0x1180080e03e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP1999"             ,	   0x1180080e03e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2000"             ,	   0x1180080e03e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2001"             ,	   0x1180080e03e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2002"             ,	   0x1180080e03e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2003"             ,	   0x1180080e03e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2004"             ,	   0x1180080e03ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2005"             ,	   0x1180080e03ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2006"             ,	   0x1180080e03eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2007"             ,	   0x1180080e03eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2008"             ,	   0x1180080e03ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2009"             ,	   0x1180080e03ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2010"             ,	   0x1180080e03ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2011"             ,	   0x1180080e03ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2012"             ,	   0x1180080e03ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2013"             ,	   0x1180080e03ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2014"             ,	   0x1180080e03ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2015"             ,	   0x1180080e03ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2016"             ,	   0x1180080e03f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2017"             ,	   0x1180080e03f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2018"             ,	   0x1180080e03f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2019"             ,	   0x1180080e03f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2020"             ,	   0x1180080e03f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2021"             ,	   0x1180080e03f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2022"             ,	   0x1180080e03f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2023"             ,	   0x1180080e03f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2024"             ,	   0x1180080e03f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2025"             ,	   0x1180080e03f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2026"             ,	   0x1180080e03f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2027"             ,	   0x1180080e03f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2028"             ,	   0x1180080e03f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2029"             ,	   0x1180080e03f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2030"             ,	   0x1180080e03f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2031"             ,	   0x1180080e03f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2032"             ,	   0x1180080e03f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2033"             ,	   0x1180080e03f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2034"             ,	   0x1180080e03f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2035"             ,	   0x1180080e03f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2036"             ,	   0x1180080e03fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2037"             ,	   0x1180080e03fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2038"             ,	   0x1180080e03fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2039"             ,	   0x1180080e03fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2040"             ,	   0x1180080e03fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2041"             ,	   0x1180080e03fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2042"             ,	   0x1180080e03fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2043"             ,	   0x1180080e03fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2044"             ,	   0x1180080e03fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2045"             ,	   0x1180080e03fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2046"             ,	   0x1180080e03ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2047"             ,	   0x1180080e03ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2048"             ,	   0x1180080e04000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2049"             ,	   0x1180080e04008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2050"             ,	   0x1180080e04010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2051"             ,	   0x1180080e04018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2052"             ,	   0x1180080e04020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2053"             ,	   0x1180080e04028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2054"             ,	   0x1180080e04030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2055"             ,	   0x1180080e04038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2056"             ,	   0x1180080e04040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2057"             ,	   0x1180080e04048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2058"             ,	   0x1180080e04050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2059"             ,	   0x1180080e04058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2060"             ,	   0x1180080e04060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2061"             ,	   0x1180080e04068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2062"             ,	   0x1180080e04070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2063"             ,	   0x1180080e04078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2064"             ,	   0x1180080e04080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2065"             ,	   0x1180080e04088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2066"             ,	   0x1180080e04090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2067"             ,	   0x1180080e04098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2068"             ,	   0x1180080e040a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2069"             ,	   0x1180080e040a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2070"             ,	   0x1180080e040b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2071"             ,	   0x1180080e040b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2072"             ,	   0x1180080e040c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2073"             ,	   0x1180080e040c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2074"             ,	   0x1180080e040d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2075"             ,	   0x1180080e040d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2076"             ,	   0x1180080e040e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2077"             ,	   0x1180080e040e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2078"             ,	   0x1180080e040f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2079"             ,	   0x1180080e040f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2080"             ,	   0x1180080e04100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2081"             ,	   0x1180080e04108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2082"             ,	   0x1180080e04110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2083"             ,	   0x1180080e04118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2084"             ,	   0x1180080e04120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2085"             ,	   0x1180080e04128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2086"             ,	   0x1180080e04130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2087"             ,	   0x1180080e04138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2088"             ,	   0x1180080e04140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2089"             ,	   0x1180080e04148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2090"             ,	   0x1180080e04150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2091"             ,	   0x1180080e04158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2092"             ,	   0x1180080e04160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2093"             ,	   0x1180080e04168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2094"             ,	   0x1180080e04170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2095"             ,	   0x1180080e04178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2096"             ,	   0x1180080e04180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2097"             ,	   0x1180080e04188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2098"             ,	   0x1180080e04190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2099"             ,	   0x1180080e04198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2100"             ,	   0x1180080e041a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2101"             ,	   0x1180080e041a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2102"             ,	   0x1180080e041b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2103"             ,	   0x1180080e041b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2104"             ,	   0x1180080e041c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2105"             ,	   0x1180080e041c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2106"             ,	   0x1180080e041d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2107"             ,	   0x1180080e041d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2108"             ,	   0x1180080e041e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2109"             ,	   0x1180080e041e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2110"             ,	   0x1180080e041f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2111"             ,	   0x1180080e041f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2112"             ,	   0x1180080e04200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2113"             ,	   0x1180080e04208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2114"             ,	   0x1180080e04210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2115"             ,	   0x1180080e04218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2116"             ,	   0x1180080e04220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2117"             ,	   0x1180080e04228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2118"             ,	   0x1180080e04230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2119"             ,	   0x1180080e04238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2120"             ,	   0x1180080e04240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2121"             ,	   0x1180080e04248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2122"             ,	   0x1180080e04250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2123"             ,	   0x1180080e04258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2124"             ,	   0x1180080e04260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2125"             ,	   0x1180080e04268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2126"             ,	   0x1180080e04270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2127"             ,	   0x1180080e04278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2128"             ,	   0x1180080e04280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2129"             ,	   0x1180080e04288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2130"             ,	   0x1180080e04290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2131"             ,	   0x1180080e04298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2132"             ,	   0x1180080e042a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2133"             ,	   0x1180080e042a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2134"             ,	   0x1180080e042b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2135"             ,	   0x1180080e042b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2136"             ,	   0x1180080e042c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2137"             ,	   0x1180080e042c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2138"             ,	   0x1180080e042d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2139"             ,	   0x1180080e042d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2140"             ,	   0x1180080e042e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2141"             ,	   0x1180080e042e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2142"             ,	   0x1180080e042f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2143"             ,	   0x1180080e042f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2144"             ,	   0x1180080e04300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2145"             ,	   0x1180080e04308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2146"             ,	   0x1180080e04310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2147"             ,	   0x1180080e04318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2148"             ,	   0x1180080e04320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2149"             ,	   0x1180080e04328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2150"             ,	   0x1180080e04330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2151"             ,	   0x1180080e04338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2152"             ,	   0x1180080e04340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2153"             ,	   0x1180080e04348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2154"             ,	   0x1180080e04350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2155"             ,	   0x1180080e04358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2156"             ,	   0x1180080e04360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2157"             ,	   0x1180080e04368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2158"             ,	   0x1180080e04370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2159"             ,	   0x1180080e04378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2160"             ,	   0x1180080e04380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2161"             ,	   0x1180080e04388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2162"             ,	   0x1180080e04390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2163"             ,	   0x1180080e04398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2164"             ,	   0x1180080e043a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2165"             ,	   0x1180080e043a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2166"             ,	   0x1180080e043b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2167"             ,	   0x1180080e043b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2168"             ,	   0x1180080e043c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2169"             ,	   0x1180080e043c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2170"             ,	   0x1180080e043d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2171"             ,	   0x1180080e043d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2172"             ,	   0x1180080e043e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2173"             ,	   0x1180080e043e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2174"             ,	   0x1180080e043f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2175"             ,	   0x1180080e043f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2176"             ,	   0x1180080e04400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2177"             ,	   0x1180080e04408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2178"             ,	   0x1180080e04410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2179"             ,	   0x1180080e04418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2180"             ,	   0x1180080e04420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2181"             ,	   0x1180080e04428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2182"             ,	   0x1180080e04430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2183"             ,	   0x1180080e04438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2184"             ,	   0x1180080e04440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2185"             ,	   0x1180080e04448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2186"             ,	   0x1180080e04450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2187"             ,	   0x1180080e04458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2188"             ,	   0x1180080e04460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2189"             ,	   0x1180080e04468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2190"             ,	   0x1180080e04470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2191"             ,	   0x1180080e04478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2192"             ,	   0x1180080e04480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2193"             ,	   0x1180080e04488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2194"             ,	   0x1180080e04490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2195"             ,	   0x1180080e04498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2196"             ,	   0x1180080e044a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2197"             ,	   0x1180080e044a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2198"             ,	   0x1180080e044b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2199"             ,	   0x1180080e044b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2200"             ,	   0x1180080e044c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2201"             ,	   0x1180080e044c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2202"             ,	   0x1180080e044d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2203"             ,	   0x1180080e044d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2204"             ,	   0x1180080e044e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2205"             ,	   0x1180080e044e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2206"             ,	   0x1180080e044f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2207"             ,	   0x1180080e044f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2208"             ,	   0x1180080e04500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2209"             ,	   0x1180080e04508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2210"             ,	   0x1180080e04510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2211"             ,	   0x1180080e04518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2212"             ,	   0x1180080e04520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2213"             ,	   0x1180080e04528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2214"             ,	   0x1180080e04530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2215"             ,	   0x1180080e04538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2216"             ,	   0x1180080e04540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2217"             ,	   0x1180080e04548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2218"             ,	   0x1180080e04550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2219"             ,	   0x1180080e04558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2220"             ,	   0x1180080e04560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2221"             ,	   0x1180080e04568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2222"             ,	   0x1180080e04570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2223"             ,	   0x1180080e04578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2224"             ,	   0x1180080e04580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2225"             ,	   0x1180080e04588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2226"             ,	   0x1180080e04590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2227"             ,	   0x1180080e04598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2228"             ,	   0x1180080e045a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2229"             ,	   0x1180080e045a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2230"             ,	   0x1180080e045b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2231"             ,	   0x1180080e045b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2232"             ,	   0x1180080e045c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2233"             ,	   0x1180080e045c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2234"             ,	   0x1180080e045d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2235"             ,	   0x1180080e045d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2236"             ,	   0x1180080e045e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2237"             ,	   0x1180080e045e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2238"             ,	   0x1180080e045f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2239"             ,	   0x1180080e045f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2240"             ,	   0x1180080e04600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2241"             ,	   0x1180080e04608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2242"             ,	   0x1180080e04610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2243"             ,	   0x1180080e04618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2244"             ,	   0x1180080e04620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2245"             ,	   0x1180080e04628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2246"             ,	   0x1180080e04630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2247"             ,	   0x1180080e04638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2248"             ,	   0x1180080e04640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2249"             ,	   0x1180080e04648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2250"             ,	   0x1180080e04650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2251"             ,	   0x1180080e04658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2252"             ,	   0x1180080e04660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2253"             ,	   0x1180080e04668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2254"             ,	   0x1180080e04670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2255"             ,	   0x1180080e04678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2256"             ,	   0x1180080e04680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2257"             ,	   0x1180080e04688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2258"             ,	   0x1180080e04690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2259"             ,	   0x1180080e04698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2260"             ,	   0x1180080e046a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2261"             ,	   0x1180080e046a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2262"             ,	   0x1180080e046b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2263"             ,	   0x1180080e046b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2264"             ,	   0x1180080e046c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2265"             ,	   0x1180080e046c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2266"             ,	   0x1180080e046d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2267"             ,	   0x1180080e046d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2268"             ,	   0x1180080e046e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2269"             ,	   0x1180080e046e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2270"             ,	   0x1180080e046f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2271"             ,	   0x1180080e046f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2272"             ,	   0x1180080e04700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2273"             ,	   0x1180080e04708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2274"             ,	   0x1180080e04710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2275"             ,	   0x1180080e04718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2276"             ,	   0x1180080e04720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2277"             ,	   0x1180080e04728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2278"             ,	   0x1180080e04730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2279"             ,	   0x1180080e04738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2280"             ,	   0x1180080e04740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2281"             ,	   0x1180080e04748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2282"             ,	   0x1180080e04750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2283"             ,	   0x1180080e04758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2284"             ,	   0x1180080e04760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2285"             ,	   0x1180080e04768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2286"             ,	   0x1180080e04770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2287"             ,	   0x1180080e04778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2288"             ,	   0x1180080e04780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2289"             ,	   0x1180080e04788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2290"             ,	   0x1180080e04790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2291"             ,	   0x1180080e04798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2292"             ,	   0x1180080e047a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2293"             ,	   0x1180080e047a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2294"             ,	   0x1180080e047b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2295"             ,	   0x1180080e047b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2296"             ,	   0x1180080e047c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2297"             ,	   0x1180080e047c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2298"             ,	   0x1180080e047d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2299"             ,	   0x1180080e047d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2300"             ,	   0x1180080e047e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2301"             ,	   0x1180080e047e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2302"             ,	   0x1180080e047f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2303"             ,	   0x1180080e047f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2304"             ,	   0x1180080e04800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2305"             ,	   0x1180080e04808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2306"             ,	   0x1180080e04810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2307"             ,	   0x1180080e04818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2308"             ,	   0x1180080e04820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2309"             ,	   0x1180080e04828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2310"             ,	   0x1180080e04830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2311"             ,	   0x1180080e04838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2312"             ,	   0x1180080e04840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2313"             ,	   0x1180080e04848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2314"             ,	   0x1180080e04850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2315"             ,	   0x1180080e04858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2316"             ,	   0x1180080e04860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2317"             ,	   0x1180080e04868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2318"             ,	   0x1180080e04870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2319"             ,	   0x1180080e04878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2320"             ,	   0x1180080e04880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2321"             ,	   0x1180080e04888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2322"             ,	   0x1180080e04890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2323"             ,	   0x1180080e04898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2324"             ,	   0x1180080e048a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2325"             ,	   0x1180080e048a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2326"             ,	   0x1180080e048b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2327"             ,	   0x1180080e048b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2328"             ,	   0x1180080e048c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2329"             ,	   0x1180080e048c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2330"             ,	   0x1180080e048d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2331"             ,	   0x1180080e048d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2332"             ,	   0x1180080e048e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2333"             ,	   0x1180080e048e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2334"             ,	   0x1180080e048f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2335"             ,	   0x1180080e048f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2336"             ,	   0x1180080e04900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2337"             ,	   0x1180080e04908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2338"             ,	   0x1180080e04910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2339"             ,	   0x1180080e04918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2340"             ,	   0x1180080e04920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2341"             ,	   0x1180080e04928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2342"             ,	   0x1180080e04930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2343"             ,	   0x1180080e04938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2344"             ,	   0x1180080e04940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2345"             ,	   0x1180080e04948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2346"             ,	   0x1180080e04950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2347"             ,	   0x1180080e04958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2348"             ,	   0x1180080e04960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2349"             ,	   0x1180080e04968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2350"             ,	   0x1180080e04970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2351"             ,	   0x1180080e04978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2352"             ,	   0x1180080e04980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2353"             ,	   0x1180080e04988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2354"             ,	   0x1180080e04990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2355"             ,	   0x1180080e04998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2356"             ,	   0x1180080e049a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2357"             ,	   0x1180080e049a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2358"             ,	   0x1180080e049b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2359"             ,	   0x1180080e049b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2360"             ,	   0x1180080e049c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2361"             ,	   0x1180080e049c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2362"             ,	   0x1180080e049d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2363"             ,	   0x1180080e049d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2364"             ,	   0x1180080e049e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2365"             ,	   0x1180080e049e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2366"             ,	   0x1180080e049f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2367"             ,	   0x1180080e049f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2368"             ,	   0x1180080e04a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2369"             ,	   0x1180080e04a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2370"             ,	   0x1180080e04a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2371"             ,	   0x1180080e04a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2372"             ,	   0x1180080e04a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2373"             ,	   0x1180080e04a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2374"             ,	   0x1180080e04a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2375"             ,	   0x1180080e04a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2376"             ,	   0x1180080e04a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2377"             ,	   0x1180080e04a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2378"             ,	   0x1180080e04a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2379"             ,	   0x1180080e04a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2380"             ,	   0x1180080e04a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2381"             ,	   0x1180080e04a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2382"             ,	   0x1180080e04a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2383"             ,	   0x1180080e04a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2384"             ,	   0x1180080e04a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2385"             ,	   0x1180080e04a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2386"             ,	   0x1180080e04a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2387"             ,	   0x1180080e04a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2388"             ,	   0x1180080e04aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2389"             ,	   0x1180080e04aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2390"             ,	   0x1180080e04ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2391"             ,	   0x1180080e04ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2392"             ,	   0x1180080e04ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2393"             ,	   0x1180080e04ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2394"             ,	   0x1180080e04ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2395"             ,	   0x1180080e04ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2396"             ,	   0x1180080e04ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2397"             ,	   0x1180080e04ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2398"             ,	   0x1180080e04af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2399"             ,	   0x1180080e04af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2400"             ,	   0x1180080e04b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2401"             ,	   0x1180080e04b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2402"             ,	   0x1180080e04b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2403"             ,	   0x1180080e04b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2404"             ,	   0x1180080e04b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2405"             ,	   0x1180080e04b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2406"             ,	   0x1180080e04b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2407"             ,	   0x1180080e04b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2408"             ,	   0x1180080e04b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2409"             ,	   0x1180080e04b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2410"             ,	   0x1180080e04b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2411"             ,	   0x1180080e04b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2412"             ,	   0x1180080e04b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2413"             ,	   0x1180080e04b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2414"             ,	   0x1180080e04b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2415"             ,	   0x1180080e04b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2416"             ,	   0x1180080e04b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2417"             ,	   0x1180080e04b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2418"             ,	   0x1180080e04b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2419"             ,	   0x1180080e04b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2420"             ,	   0x1180080e04ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2421"             ,	   0x1180080e04ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2422"             ,	   0x1180080e04bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2423"             ,	   0x1180080e04bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2424"             ,	   0x1180080e04bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2425"             ,	   0x1180080e04bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2426"             ,	   0x1180080e04bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2427"             ,	   0x1180080e04bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2428"             ,	   0x1180080e04be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2429"             ,	   0x1180080e04be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2430"             ,	   0x1180080e04bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2431"             ,	   0x1180080e04bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2432"             ,	   0x1180080e04c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2433"             ,	   0x1180080e04c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2434"             ,	   0x1180080e04c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2435"             ,	   0x1180080e04c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2436"             ,	   0x1180080e04c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2437"             ,	   0x1180080e04c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2438"             ,	   0x1180080e04c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2439"             ,	   0x1180080e04c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2440"             ,	   0x1180080e04c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2441"             ,	   0x1180080e04c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2442"             ,	   0x1180080e04c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2443"             ,	   0x1180080e04c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2444"             ,	   0x1180080e04c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2445"             ,	   0x1180080e04c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2446"             ,	   0x1180080e04c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2447"             ,	   0x1180080e04c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2448"             ,	   0x1180080e04c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2449"             ,	   0x1180080e04c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2450"             ,	   0x1180080e04c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2451"             ,	   0x1180080e04c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2452"             ,	   0x1180080e04ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2453"             ,	   0x1180080e04ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2454"             ,	   0x1180080e04cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2455"             ,	   0x1180080e04cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2456"             ,	   0x1180080e04cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2457"             ,	   0x1180080e04cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2458"             ,	   0x1180080e04cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2459"             ,	   0x1180080e04cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2460"             ,	   0x1180080e04ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2461"             ,	   0x1180080e04ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2462"             ,	   0x1180080e04cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2463"             ,	   0x1180080e04cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2464"             ,	   0x1180080e04d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2465"             ,	   0x1180080e04d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2466"             ,	   0x1180080e04d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2467"             ,	   0x1180080e04d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2468"             ,	   0x1180080e04d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2469"             ,	   0x1180080e04d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2470"             ,	   0x1180080e04d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2471"             ,	   0x1180080e04d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2472"             ,	   0x1180080e04d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2473"             ,	   0x1180080e04d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2474"             ,	   0x1180080e04d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2475"             ,	   0x1180080e04d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2476"             ,	   0x1180080e04d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2477"             ,	   0x1180080e04d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2478"             ,	   0x1180080e04d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2479"             ,	   0x1180080e04d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2480"             ,	   0x1180080e04d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2481"             ,	   0x1180080e04d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2482"             ,	   0x1180080e04d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2483"             ,	   0x1180080e04d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2484"             ,	   0x1180080e04da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2485"             ,	   0x1180080e04da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2486"             ,	   0x1180080e04db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2487"             ,	   0x1180080e04db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2488"             ,	   0x1180080e04dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2489"             ,	   0x1180080e04dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2490"             ,	   0x1180080e04dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2491"             ,	   0x1180080e04dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2492"             ,	   0x1180080e04de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2493"             ,	   0x1180080e04de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2494"             ,	   0x1180080e04df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2495"             ,	   0x1180080e04df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2496"             ,	   0x1180080e04e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2497"             ,	   0x1180080e04e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2498"             ,	   0x1180080e04e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2499"             ,	   0x1180080e04e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2500"             ,	   0x1180080e04e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2501"             ,	   0x1180080e04e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2502"             ,	   0x1180080e04e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2503"             ,	   0x1180080e04e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2504"             ,	   0x1180080e04e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2505"             ,	   0x1180080e04e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2506"             ,	   0x1180080e04e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2507"             ,	   0x1180080e04e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2508"             ,	   0x1180080e04e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2509"             ,	   0x1180080e04e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2510"             ,	   0x1180080e04e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2511"             ,	   0x1180080e04e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2512"             ,	   0x1180080e04e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2513"             ,	   0x1180080e04e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2514"             ,	   0x1180080e04e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2515"             ,	   0x1180080e04e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2516"             ,	   0x1180080e04ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2517"             ,	   0x1180080e04ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2518"             ,	   0x1180080e04eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2519"             ,	   0x1180080e04eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2520"             ,	   0x1180080e04ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2521"             ,	   0x1180080e04ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2522"             ,	   0x1180080e04ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2523"             ,	   0x1180080e04ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2524"             ,	   0x1180080e04ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2525"             ,	   0x1180080e04ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2526"             ,	   0x1180080e04ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2527"             ,	   0x1180080e04ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2528"             ,	   0x1180080e04f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2529"             ,	   0x1180080e04f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2530"             ,	   0x1180080e04f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2531"             ,	   0x1180080e04f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2532"             ,	   0x1180080e04f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2533"             ,	   0x1180080e04f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2534"             ,	   0x1180080e04f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2535"             ,	   0x1180080e04f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2536"             ,	   0x1180080e04f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2537"             ,	   0x1180080e04f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2538"             ,	   0x1180080e04f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2539"             ,	   0x1180080e04f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2540"             ,	   0x1180080e04f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2541"             ,	   0x1180080e04f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2542"             ,	   0x1180080e04f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2543"             ,	   0x1180080e04f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2544"             ,	   0x1180080e04f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2545"             ,	   0x1180080e04f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2546"             ,	   0x1180080e04f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2547"             ,	   0x1180080e04f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2548"             ,	   0x1180080e04fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2549"             ,	   0x1180080e04fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2550"             ,	   0x1180080e04fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2551"             ,	   0x1180080e04fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2552"             ,	   0x1180080e04fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2553"             ,	   0x1180080e04fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2554"             ,	   0x1180080e04fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2555"             ,	   0x1180080e04fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2556"             ,	   0x1180080e04fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2557"             ,	   0x1180080e04fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2558"             ,	   0x1180080e04ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_DUT_MAP2559"             ,	   0x1180080e04ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_ERR_TDT0"                ,	   0x1180080a007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"L2C_ERR_TTG0"                ,	   0x1180080a007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"L2C_ERR_VBF0"                ,	   0x1180080c007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"L2C_ERR_XMC"                 ,	   0x11800808007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"L2C_INT_ENA"                 ,	   0x1180080800020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"L2C_INT_REG"                 ,	   0x1180080800018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"L2C_IOC0_PFC"                ,	   0x1180080800420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"L2C_IOR0_PFC"                ,	   0x1180080800428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"L2C_QOS_IOB0"                ,	   0x1180080880200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"L2C_QOS_PP0"                 ,	   0x1180080880000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"L2C_QOS_PP1"                 ,	   0x1180080880008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"L2C_QOS_PP2"                 ,	   0x1180080880010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"L2C_QOS_PP3"                 ,	   0x1180080880018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"L2C_QOS_PP4"                 ,	   0x1180080880020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"L2C_QOS_PP5"                 ,	   0x1180080880028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"L2C_QOS_PP6"                 ,	   0x1180080880030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"L2C_QOS_PP7"                 ,	   0x1180080880038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"L2C_QOS_PP8"                 ,	   0x1180080880040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"L2C_QOS_PP9"                 ,	   0x1180080880048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"L2C_QOS_WGT"                 ,	   0x1180080800008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"L2C_RSC0_PFC"                ,	   0x1180080800410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"L2C_RSD0_PFC"                ,	   0x1180080800418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"L2C_TAD0_ECC0"               ,	   0x1180080a00018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"L2C_TAD0_ECC1"               ,	   0x1180080a00020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"L2C_TAD0_IEN"                ,	   0x1180080a00000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"L2C_TAD0_INT"                ,	   0x1180080a00028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"L2C_TAD0_PFC0"               ,	   0x1180080a00400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"L2C_TAD0_PFC1"               ,	   0x1180080a00408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"L2C_TAD0_PFC2"               ,	   0x1180080a00410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"L2C_TAD0_PFC3"               ,	   0x1180080a00418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"L2C_TAD0_PRF"                ,	   0x1180080a00008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"L2C_TAD0_TAG"                ,	   0x1180080a00010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"L2C_VER_ID"                  ,	   0x11800808007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"L2C_VER_IOB"                 ,	   0x11800808007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"L2C_VER_MSC"                 ,	   0x11800808007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"L2C_VER_PP"                  ,	   0x11800808007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"L2C_VIRTID_IOB0"             ,	   0x11800808c0200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"L2C_VIRTID_PP0"              ,	   0x11800808c0000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"L2C_VIRTID_PP1"              ,	   0x11800808c0008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"L2C_VIRTID_PP2"              ,	   0x11800808c0010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"L2C_VIRTID_PP3"              ,	   0x11800808c0018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"L2C_VIRTID_PP4"              ,	   0x11800808c0020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"L2C_VIRTID_PP5"              ,	   0x11800808c0028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"L2C_VIRTID_PP6"              ,	   0x11800808c0030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"L2C_VIRTID_PP7"              ,	   0x11800808c0038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"L2C_VIRTID_PP8"              ,	   0x11800808c0040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"L2C_VIRTID_PP9"              ,	   0x11800808c0048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"L2C_VRT_CTL"                 ,	   0x1180080800010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"L2C_VRT_MEM0"                ,	   0x1180080900000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1"                ,	   0x1180080900008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM2"                ,	   0x1180080900010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM3"                ,	   0x1180080900018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM4"                ,	   0x1180080900020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM5"                ,	   0x1180080900028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM6"                ,	   0x1180080900030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM7"                ,	   0x1180080900038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM8"                ,	   0x1180080900040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM9"                ,	   0x1180080900048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM10"               ,	   0x1180080900050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM11"               ,	   0x1180080900058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM12"               ,	   0x1180080900060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM13"               ,	   0x1180080900068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM14"               ,	   0x1180080900070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM15"               ,	   0x1180080900078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM16"               ,	   0x1180080900080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM17"               ,	   0x1180080900088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM18"               ,	   0x1180080900090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM19"               ,	   0x1180080900098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM20"               ,	   0x11800809000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM21"               ,	   0x11800809000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM22"               ,	   0x11800809000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM23"               ,	   0x11800809000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM24"               ,	   0x11800809000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM25"               ,	   0x11800809000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM26"               ,	   0x11800809000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM27"               ,	   0x11800809000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM28"               ,	   0x11800809000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM29"               ,	   0x11800809000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM30"               ,	   0x11800809000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM31"               ,	   0x11800809000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM32"               ,	   0x1180080900100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM33"               ,	   0x1180080900108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM34"               ,	   0x1180080900110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM35"               ,	   0x1180080900118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM36"               ,	   0x1180080900120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM37"               ,	   0x1180080900128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM38"               ,	   0x1180080900130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM39"               ,	   0x1180080900138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM40"               ,	   0x1180080900140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM41"               ,	   0x1180080900148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM42"               ,	   0x1180080900150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM43"               ,	   0x1180080900158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM44"               ,	   0x1180080900160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM45"               ,	   0x1180080900168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM46"               ,	   0x1180080900170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM47"               ,	   0x1180080900178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM48"               ,	   0x1180080900180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM49"               ,	   0x1180080900188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM50"               ,	   0x1180080900190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM51"               ,	   0x1180080900198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM52"               ,	   0x11800809001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM53"               ,	   0x11800809001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM54"               ,	   0x11800809001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM55"               ,	   0x11800809001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM56"               ,	   0x11800809001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM57"               ,	   0x11800809001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM58"               ,	   0x11800809001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM59"               ,	   0x11800809001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM60"               ,	   0x11800809001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM61"               ,	   0x11800809001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM62"               ,	   0x11800809001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM63"               ,	   0x11800809001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM64"               ,	   0x1180080900200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM65"               ,	   0x1180080900208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM66"               ,	   0x1180080900210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM67"               ,	   0x1180080900218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM68"               ,	   0x1180080900220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM69"               ,	   0x1180080900228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM70"               ,	   0x1180080900230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM71"               ,	   0x1180080900238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM72"               ,	   0x1180080900240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM73"               ,	   0x1180080900248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM74"               ,	   0x1180080900250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM75"               ,	   0x1180080900258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM76"               ,	   0x1180080900260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM77"               ,	   0x1180080900268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM78"               ,	   0x1180080900270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM79"               ,	   0x1180080900278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM80"               ,	   0x1180080900280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM81"               ,	   0x1180080900288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM82"               ,	   0x1180080900290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM83"               ,	   0x1180080900298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM84"               ,	   0x11800809002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM85"               ,	   0x11800809002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM86"               ,	   0x11800809002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM87"               ,	   0x11800809002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM88"               ,	   0x11800809002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM89"               ,	   0x11800809002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM90"               ,	   0x11800809002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM91"               ,	   0x11800809002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM92"               ,	   0x11800809002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM93"               ,	   0x11800809002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM94"               ,	   0x11800809002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM95"               ,	   0x11800809002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM96"               ,	   0x1180080900300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM97"               ,	   0x1180080900308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM98"               ,	   0x1180080900310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM99"               ,	   0x1180080900318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM100"              ,	   0x1180080900320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM101"              ,	   0x1180080900328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM102"              ,	   0x1180080900330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM103"              ,	   0x1180080900338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM104"              ,	   0x1180080900340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM105"              ,	   0x1180080900348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM106"              ,	   0x1180080900350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM107"              ,	   0x1180080900358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM108"              ,	   0x1180080900360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM109"              ,	   0x1180080900368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM110"              ,	   0x1180080900370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM111"              ,	   0x1180080900378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM112"              ,	   0x1180080900380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM113"              ,	   0x1180080900388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM114"              ,	   0x1180080900390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM115"              ,	   0x1180080900398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM116"              ,	   0x11800809003a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM117"              ,	   0x11800809003a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM118"              ,	   0x11800809003b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM119"              ,	   0x11800809003b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM120"              ,	   0x11800809003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM121"              ,	   0x11800809003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM122"              ,	   0x11800809003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM123"              ,	   0x11800809003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM124"              ,	   0x11800809003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM125"              ,	   0x11800809003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM126"              ,	   0x11800809003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM127"              ,	   0x11800809003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM128"              ,	   0x1180080900400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM129"              ,	   0x1180080900408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM130"              ,	   0x1180080900410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM131"              ,	   0x1180080900418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM132"              ,	   0x1180080900420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM133"              ,	   0x1180080900428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM134"              ,	   0x1180080900430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM135"              ,	   0x1180080900438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM136"              ,	   0x1180080900440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM137"              ,	   0x1180080900448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM138"              ,	   0x1180080900450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM139"              ,	   0x1180080900458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM140"              ,	   0x1180080900460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM141"              ,	   0x1180080900468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM142"              ,	   0x1180080900470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM143"              ,	   0x1180080900478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM144"              ,	   0x1180080900480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM145"              ,	   0x1180080900488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM146"              ,	   0x1180080900490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM147"              ,	   0x1180080900498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM148"              ,	   0x11800809004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM149"              ,	   0x11800809004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM150"              ,	   0x11800809004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM151"              ,	   0x11800809004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM152"              ,	   0x11800809004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM153"              ,	   0x11800809004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM154"              ,	   0x11800809004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM155"              ,	   0x11800809004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM156"              ,	   0x11800809004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM157"              ,	   0x11800809004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM158"              ,	   0x11800809004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM159"              ,	   0x11800809004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM160"              ,	   0x1180080900500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM161"              ,	   0x1180080900508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM162"              ,	   0x1180080900510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM163"              ,	   0x1180080900518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM164"              ,	   0x1180080900520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM165"              ,	   0x1180080900528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM166"              ,	   0x1180080900530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM167"              ,	   0x1180080900538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM168"              ,	   0x1180080900540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM169"              ,	   0x1180080900548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM170"              ,	   0x1180080900550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM171"              ,	   0x1180080900558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM172"              ,	   0x1180080900560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM173"              ,	   0x1180080900568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM174"              ,	   0x1180080900570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM175"              ,	   0x1180080900578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM176"              ,	   0x1180080900580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM177"              ,	   0x1180080900588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM178"              ,	   0x1180080900590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM179"              ,	   0x1180080900598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM180"              ,	   0x11800809005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM181"              ,	   0x11800809005a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM182"              ,	   0x11800809005b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM183"              ,	   0x11800809005b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM184"              ,	   0x11800809005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM185"              ,	   0x11800809005c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM186"              ,	   0x11800809005d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM187"              ,	   0x11800809005d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM188"              ,	   0x11800809005e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM189"              ,	   0x11800809005e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM190"              ,	   0x11800809005f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM191"              ,	   0x11800809005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM192"              ,	   0x1180080900600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM193"              ,	   0x1180080900608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM194"              ,	   0x1180080900610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM195"              ,	   0x1180080900618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM196"              ,	   0x1180080900620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM197"              ,	   0x1180080900628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM198"              ,	   0x1180080900630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM199"              ,	   0x1180080900638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM200"              ,	   0x1180080900640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM201"              ,	   0x1180080900648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM202"              ,	   0x1180080900650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM203"              ,	   0x1180080900658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM204"              ,	   0x1180080900660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM205"              ,	   0x1180080900668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM206"              ,	   0x1180080900670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM207"              ,	   0x1180080900678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM208"              ,	   0x1180080900680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM209"              ,	   0x1180080900688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM210"              ,	   0x1180080900690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM211"              ,	   0x1180080900698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM212"              ,	   0x11800809006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM213"              ,	   0x11800809006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM214"              ,	   0x11800809006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM215"              ,	   0x11800809006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM216"              ,	   0x11800809006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM217"              ,	   0x11800809006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM218"              ,	   0x11800809006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM219"              ,	   0x11800809006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM220"              ,	   0x11800809006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM221"              ,	   0x11800809006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM222"              ,	   0x11800809006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM223"              ,	   0x11800809006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM224"              ,	   0x1180080900700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM225"              ,	   0x1180080900708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM226"              ,	   0x1180080900710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM227"              ,	   0x1180080900718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM228"              ,	   0x1180080900720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM229"              ,	   0x1180080900728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM230"              ,	   0x1180080900730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM231"              ,	   0x1180080900738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM232"              ,	   0x1180080900740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM233"              ,	   0x1180080900748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM234"              ,	   0x1180080900750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM235"              ,	   0x1180080900758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM236"              ,	   0x1180080900760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM237"              ,	   0x1180080900768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM238"              ,	   0x1180080900770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM239"              ,	   0x1180080900778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM240"              ,	   0x1180080900780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM241"              ,	   0x1180080900788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM242"              ,	   0x1180080900790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM243"              ,	   0x1180080900798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM244"              ,	   0x11800809007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM245"              ,	   0x11800809007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM246"              ,	   0x11800809007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM247"              ,	   0x11800809007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM248"              ,	   0x11800809007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM249"              ,	   0x11800809007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM250"              ,	   0x11800809007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM251"              ,	   0x11800809007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM252"              ,	   0x11800809007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM253"              ,	   0x11800809007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM254"              ,	   0x11800809007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM255"              ,	   0x11800809007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM256"              ,	   0x1180080900800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM257"              ,	   0x1180080900808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM258"              ,	   0x1180080900810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM259"              ,	   0x1180080900818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM260"              ,	   0x1180080900820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM261"              ,	   0x1180080900828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM262"              ,	   0x1180080900830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM263"              ,	   0x1180080900838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM264"              ,	   0x1180080900840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM265"              ,	   0x1180080900848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM266"              ,	   0x1180080900850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM267"              ,	   0x1180080900858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM268"              ,	   0x1180080900860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM269"              ,	   0x1180080900868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM270"              ,	   0x1180080900870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM271"              ,	   0x1180080900878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM272"              ,	   0x1180080900880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM273"              ,	   0x1180080900888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM274"              ,	   0x1180080900890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM275"              ,	   0x1180080900898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM276"              ,	   0x11800809008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM277"              ,	   0x11800809008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM278"              ,	   0x11800809008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM279"              ,	   0x11800809008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM280"              ,	   0x11800809008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM281"              ,	   0x11800809008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM282"              ,	   0x11800809008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM283"              ,	   0x11800809008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM284"              ,	   0x11800809008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM285"              ,	   0x11800809008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM286"              ,	   0x11800809008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM287"              ,	   0x11800809008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM288"              ,	   0x1180080900900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM289"              ,	   0x1180080900908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM290"              ,	   0x1180080900910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM291"              ,	   0x1180080900918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM292"              ,	   0x1180080900920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM293"              ,	   0x1180080900928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM294"              ,	   0x1180080900930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM295"              ,	   0x1180080900938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM296"              ,	   0x1180080900940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM297"              ,	   0x1180080900948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM298"              ,	   0x1180080900950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM299"              ,	   0x1180080900958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM300"              ,	   0x1180080900960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM301"              ,	   0x1180080900968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM302"              ,	   0x1180080900970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM303"              ,	   0x1180080900978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM304"              ,	   0x1180080900980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM305"              ,	   0x1180080900988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM306"              ,	   0x1180080900990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM307"              ,	   0x1180080900998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM308"              ,	   0x11800809009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM309"              ,	   0x11800809009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM310"              ,	   0x11800809009b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM311"              ,	   0x11800809009b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM312"              ,	   0x11800809009c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM313"              ,	   0x11800809009c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM314"              ,	   0x11800809009d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM315"              ,	   0x11800809009d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM316"              ,	   0x11800809009e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM317"              ,	   0x11800809009e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM318"              ,	   0x11800809009f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM319"              ,	   0x11800809009f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM320"              ,	   0x1180080900a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM321"              ,	   0x1180080900a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM322"              ,	   0x1180080900a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM323"              ,	   0x1180080900a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM324"              ,	   0x1180080900a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM325"              ,	   0x1180080900a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM326"              ,	   0x1180080900a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM327"              ,	   0x1180080900a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM328"              ,	   0x1180080900a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM329"              ,	   0x1180080900a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM330"              ,	   0x1180080900a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM331"              ,	   0x1180080900a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM332"              ,	   0x1180080900a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM333"              ,	   0x1180080900a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM334"              ,	   0x1180080900a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM335"              ,	   0x1180080900a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM336"              ,	   0x1180080900a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM337"              ,	   0x1180080900a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM338"              ,	   0x1180080900a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM339"              ,	   0x1180080900a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM340"              ,	   0x1180080900aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM341"              ,	   0x1180080900aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM342"              ,	   0x1180080900ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM343"              ,	   0x1180080900ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM344"              ,	   0x1180080900ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM345"              ,	   0x1180080900ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM346"              ,	   0x1180080900ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM347"              ,	   0x1180080900ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM348"              ,	   0x1180080900ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM349"              ,	   0x1180080900ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM350"              ,	   0x1180080900af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM351"              ,	   0x1180080900af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM352"              ,	   0x1180080900b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM353"              ,	   0x1180080900b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM354"              ,	   0x1180080900b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM355"              ,	   0x1180080900b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM356"              ,	   0x1180080900b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM357"              ,	   0x1180080900b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM358"              ,	   0x1180080900b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM359"              ,	   0x1180080900b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM360"              ,	   0x1180080900b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM361"              ,	   0x1180080900b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM362"              ,	   0x1180080900b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM363"              ,	   0x1180080900b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM364"              ,	   0x1180080900b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM365"              ,	   0x1180080900b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM366"              ,	   0x1180080900b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM367"              ,	   0x1180080900b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM368"              ,	   0x1180080900b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM369"              ,	   0x1180080900b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM370"              ,	   0x1180080900b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM371"              ,	   0x1180080900b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM372"              ,	   0x1180080900ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM373"              ,	   0x1180080900ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM374"              ,	   0x1180080900bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM375"              ,	   0x1180080900bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM376"              ,	   0x1180080900bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM377"              ,	   0x1180080900bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM378"              ,	   0x1180080900bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM379"              ,	   0x1180080900bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM380"              ,	   0x1180080900be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM381"              ,	   0x1180080900be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM382"              ,	   0x1180080900bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM383"              ,	   0x1180080900bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM384"              ,	   0x1180080900c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM385"              ,	   0x1180080900c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM386"              ,	   0x1180080900c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM387"              ,	   0x1180080900c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM388"              ,	   0x1180080900c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM389"              ,	   0x1180080900c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM390"              ,	   0x1180080900c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM391"              ,	   0x1180080900c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM392"              ,	   0x1180080900c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM393"              ,	   0x1180080900c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM394"              ,	   0x1180080900c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM395"              ,	   0x1180080900c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM396"              ,	   0x1180080900c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM397"              ,	   0x1180080900c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM398"              ,	   0x1180080900c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM399"              ,	   0x1180080900c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM400"              ,	   0x1180080900c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM401"              ,	   0x1180080900c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM402"              ,	   0x1180080900c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM403"              ,	   0x1180080900c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM404"              ,	   0x1180080900ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM405"              ,	   0x1180080900ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM406"              ,	   0x1180080900cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM407"              ,	   0x1180080900cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM408"              ,	   0x1180080900cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM409"              ,	   0x1180080900cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM410"              ,	   0x1180080900cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM411"              ,	   0x1180080900cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM412"              ,	   0x1180080900ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM413"              ,	   0x1180080900ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM414"              ,	   0x1180080900cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM415"              ,	   0x1180080900cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM416"              ,	   0x1180080900d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM417"              ,	   0x1180080900d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM418"              ,	   0x1180080900d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM419"              ,	   0x1180080900d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM420"              ,	   0x1180080900d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM421"              ,	   0x1180080900d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM422"              ,	   0x1180080900d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM423"              ,	   0x1180080900d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM424"              ,	   0x1180080900d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM425"              ,	   0x1180080900d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM426"              ,	   0x1180080900d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM427"              ,	   0x1180080900d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM428"              ,	   0x1180080900d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM429"              ,	   0x1180080900d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM430"              ,	   0x1180080900d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM431"              ,	   0x1180080900d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM432"              ,	   0x1180080900d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM433"              ,	   0x1180080900d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM434"              ,	   0x1180080900d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM435"              ,	   0x1180080900d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM436"              ,	   0x1180080900da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM437"              ,	   0x1180080900da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM438"              ,	   0x1180080900db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM439"              ,	   0x1180080900db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM440"              ,	   0x1180080900dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM441"              ,	   0x1180080900dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM442"              ,	   0x1180080900dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM443"              ,	   0x1180080900dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM444"              ,	   0x1180080900de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM445"              ,	   0x1180080900de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM446"              ,	   0x1180080900df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM447"              ,	   0x1180080900df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM448"              ,	   0x1180080900e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM449"              ,	   0x1180080900e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM450"              ,	   0x1180080900e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM451"              ,	   0x1180080900e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM452"              ,	   0x1180080900e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM453"              ,	   0x1180080900e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM454"              ,	   0x1180080900e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM455"              ,	   0x1180080900e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM456"              ,	   0x1180080900e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM457"              ,	   0x1180080900e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM458"              ,	   0x1180080900e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM459"              ,	   0x1180080900e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM460"              ,	   0x1180080900e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM461"              ,	   0x1180080900e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM462"              ,	   0x1180080900e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM463"              ,	   0x1180080900e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM464"              ,	   0x1180080900e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM465"              ,	   0x1180080900e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM466"              ,	   0x1180080900e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM467"              ,	   0x1180080900e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM468"              ,	   0x1180080900ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM469"              ,	   0x1180080900ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM470"              ,	   0x1180080900eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM471"              ,	   0x1180080900eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM472"              ,	   0x1180080900ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM473"              ,	   0x1180080900ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM474"              ,	   0x1180080900ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM475"              ,	   0x1180080900ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM476"              ,	   0x1180080900ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM477"              ,	   0x1180080900ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM478"              ,	   0x1180080900ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM479"              ,	   0x1180080900ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM480"              ,	   0x1180080900f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM481"              ,	   0x1180080900f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM482"              ,	   0x1180080900f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM483"              ,	   0x1180080900f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM484"              ,	   0x1180080900f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM485"              ,	   0x1180080900f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM486"              ,	   0x1180080900f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM487"              ,	   0x1180080900f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM488"              ,	   0x1180080900f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM489"              ,	   0x1180080900f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM490"              ,	   0x1180080900f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM491"              ,	   0x1180080900f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM492"              ,	   0x1180080900f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM493"              ,	   0x1180080900f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM494"              ,	   0x1180080900f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM495"              ,	   0x1180080900f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM496"              ,	   0x1180080900f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM497"              ,	   0x1180080900f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM498"              ,	   0x1180080900f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM499"              ,	   0x1180080900f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM500"              ,	   0x1180080900fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM501"              ,	   0x1180080900fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM502"              ,	   0x1180080900fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM503"              ,	   0x1180080900fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM504"              ,	   0x1180080900fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM505"              ,	   0x1180080900fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM506"              ,	   0x1180080900fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM507"              ,	   0x1180080900fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM508"              ,	   0x1180080900fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM509"              ,	   0x1180080900fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM510"              ,	   0x1180080900ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM511"              ,	   0x1180080900ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM512"              ,	   0x1180080901000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM513"              ,	   0x1180080901008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM514"              ,	   0x1180080901010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM515"              ,	   0x1180080901018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM516"              ,	   0x1180080901020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM517"              ,	   0x1180080901028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM518"              ,	   0x1180080901030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM519"              ,	   0x1180080901038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM520"              ,	   0x1180080901040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM521"              ,	   0x1180080901048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM522"              ,	   0x1180080901050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM523"              ,	   0x1180080901058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM524"              ,	   0x1180080901060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM525"              ,	   0x1180080901068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM526"              ,	   0x1180080901070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM527"              ,	   0x1180080901078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM528"              ,	   0x1180080901080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM529"              ,	   0x1180080901088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM530"              ,	   0x1180080901090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM531"              ,	   0x1180080901098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM532"              ,	   0x11800809010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM533"              ,	   0x11800809010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM534"              ,	   0x11800809010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM535"              ,	   0x11800809010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM536"              ,	   0x11800809010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM537"              ,	   0x11800809010c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM538"              ,	   0x11800809010d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM539"              ,	   0x11800809010d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM540"              ,	   0x11800809010e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM541"              ,	   0x11800809010e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM542"              ,	   0x11800809010f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM543"              ,	   0x11800809010f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM544"              ,	   0x1180080901100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM545"              ,	   0x1180080901108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM546"              ,	   0x1180080901110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM547"              ,	   0x1180080901118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM548"              ,	   0x1180080901120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM549"              ,	   0x1180080901128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM550"              ,	   0x1180080901130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM551"              ,	   0x1180080901138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM552"              ,	   0x1180080901140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM553"              ,	   0x1180080901148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM554"              ,	   0x1180080901150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM555"              ,	   0x1180080901158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM556"              ,	   0x1180080901160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM557"              ,	   0x1180080901168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM558"              ,	   0x1180080901170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM559"              ,	   0x1180080901178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM560"              ,	   0x1180080901180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM561"              ,	   0x1180080901188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM562"              ,	   0x1180080901190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM563"              ,	   0x1180080901198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM564"              ,	   0x11800809011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM565"              ,	   0x11800809011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM566"              ,	   0x11800809011b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM567"              ,	   0x11800809011b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM568"              ,	   0x11800809011c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM569"              ,	   0x11800809011c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM570"              ,	   0x11800809011d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM571"              ,	   0x11800809011d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM572"              ,	   0x11800809011e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM573"              ,	   0x11800809011e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM574"              ,	   0x11800809011f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM575"              ,	   0x11800809011f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM576"              ,	   0x1180080901200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM577"              ,	   0x1180080901208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM578"              ,	   0x1180080901210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM579"              ,	   0x1180080901218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM580"              ,	   0x1180080901220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM581"              ,	   0x1180080901228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM582"              ,	   0x1180080901230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM583"              ,	   0x1180080901238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM584"              ,	   0x1180080901240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM585"              ,	   0x1180080901248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM586"              ,	   0x1180080901250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM587"              ,	   0x1180080901258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM588"              ,	   0x1180080901260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM589"              ,	   0x1180080901268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM590"              ,	   0x1180080901270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM591"              ,	   0x1180080901278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM592"              ,	   0x1180080901280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM593"              ,	   0x1180080901288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM594"              ,	   0x1180080901290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM595"              ,	   0x1180080901298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM596"              ,	   0x11800809012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM597"              ,	   0x11800809012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM598"              ,	   0x11800809012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM599"              ,	   0x11800809012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM600"              ,	   0x11800809012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM601"              ,	   0x11800809012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM602"              ,	   0x11800809012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM603"              ,	   0x11800809012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM604"              ,	   0x11800809012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM605"              ,	   0x11800809012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM606"              ,	   0x11800809012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM607"              ,	   0x11800809012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM608"              ,	   0x1180080901300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM609"              ,	   0x1180080901308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM610"              ,	   0x1180080901310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM611"              ,	   0x1180080901318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM612"              ,	   0x1180080901320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM613"              ,	   0x1180080901328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM614"              ,	   0x1180080901330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM615"              ,	   0x1180080901338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM616"              ,	   0x1180080901340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM617"              ,	   0x1180080901348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM618"              ,	   0x1180080901350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM619"              ,	   0x1180080901358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM620"              ,	   0x1180080901360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM621"              ,	   0x1180080901368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM622"              ,	   0x1180080901370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM623"              ,	   0x1180080901378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM624"              ,	   0x1180080901380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM625"              ,	   0x1180080901388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM626"              ,	   0x1180080901390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM627"              ,	   0x1180080901398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM628"              ,	   0x11800809013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM629"              ,	   0x11800809013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM630"              ,	   0x11800809013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM631"              ,	   0x11800809013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM632"              ,	   0x11800809013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM633"              ,	   0x11800809013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM634"              ,	   0x11800809013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM635"              ,	   0x11800809013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM636"              ,	   0x11800809013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM637"              ,	   0x11800809013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM638"              ,	   0x11800809013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM639"              ,	   0x11800809013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM640"              ,	   0x1180080901400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM641"              ,	   0x1180080901408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM642"              ,	   0x1180080901410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM643"              ,	   0x1180080901418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM644"              ,	   0x1180080901420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM645"              ,	   0x1180080901428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM646"              ,	   0x1180080901430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM647"              ,	   0x1180080901438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM648"              ,	   0x1180080901440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM649"              ,	   0x1180080901448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM650"              ,	   0x1180080901450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM651"              ,	   0x1180080901458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM652"              ,	   0x1180080901460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM653"              ,	   0x1180080901468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM654"              ,	   0x1180080901470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM655"              ,	   0x1180080901478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM656"              ,	   0x1180080901480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM657"              ,	   0x1180080901488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM658"              ,	   0x1180080901490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM659"              ,	   0x1180080901498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM660"              ,	   0x11800809014a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM661"              ,	   0x11800809014a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM662"              ,	   0x11800809014b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM663"              ,	   0x11800809014b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM664"              ,	   0x11800809014c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM665"              ,	   0x11800809014c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM666"              ,	   0x11800809014d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM667"              ,	   0x11800809014d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM668"              ,	   0x11800809014e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM669"              ,	   0x11800809014e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM670"              ,	   0x11800809014f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM671"              ,	   0x11800809014f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM672"              ,	   0x1180080901500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM673"              ,	   0x1180080901508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM674"              ,	   0x1180080901510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM675"              ,	   0x1180080901518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM676"              ,	   0x1180080901520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM677"              ,	   0x1180080901528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM678"              ,	   0x1180080901530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM679"              ,	   0x1180080901538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM680"              ,	   0x1180080901540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM681"              ,	   0x1180080901548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM682"              ,	   0x1180080901550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM683"              ,	   0x1180080901558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM684"              ,	   0x1180080901560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM685"              ,	   0x1180080901568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM686"              ,	   0x1180080901570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM687"              ,	   0x1180080901578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM688"              ,	   0x1180080901580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM689"              ,	   0x1180080901588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM690"              ,	   0x1180080901590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM691"              ,	   0x1180080901598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM692"              ,	   0x11800809015a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM693"              ,	   0x11800809015a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM694"              ,	   0x11800809015b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM695"              ,	   0x11800809015b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM696"              ,	   0x11800809015c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM697"              ,	   0x11800809015c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM698"              ,	   0x11800809015d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM699"              ,	   0x11800809015d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM700"              ,	   0x11800809015e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM701"              ,	   0x11800809015e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM702"              ,	   0x11800809015f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM703"              ,	   0x11800809015f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM704"              ,	   0x1180080901600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM705"              ,	   0x1180080901608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM706"              ,	   0x1180080901610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM707"              ,	   0x1180080901618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM708"              ,	   0x1180080901620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM709"              ,	   0x1180080901628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM710"              ,	   0x1180080901630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM711"              ,	   0x1180080901638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM712"              ,	   0x1180080901640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM713"              ,	   0x1180080901648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM714"              ,	   0x1180080901650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM715"              ,	   0x1180080901658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM716"              ,	   0x1180080901660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM717"              ,	   0x1180080901668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM718"              ,	   0x1180080901670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM719"              ,	   0x1180080901678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM720"              ,	   0x1180080901680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM721"              ,	   0x1180080901688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM722"              ,	   0x1180080901690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM723"              ,	   0x1180080901698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM724"              ,	   0x11800809016a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM725"              ,	   0x11800809016a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM726"              ,	   0x11800809016b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM727"              ,	   0x11800809016b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM728"              ,	   0x11800809016c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM729"              ,	   0x11800809016c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM730"              ,	   0x11800809016d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM731"              ,	   0x11800809016d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM732"              ,	   0x11800809016e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM733"              ,	   0x11800809016e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM734"              ,	   0x11800809016f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM735"              ,	   0x11800809016f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM736"              ,	   0x1180080901700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM737"              ,	   0x1180080901708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM738"              ,	   0x1180080901710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM739"              ,	   0x1180080901718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM740"              ,	   0x1180080901720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM741"              ,	   0x1180080901728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM742"              ,	   0x1180080901730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM743"              ,	   0x1180080901738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM744"              ,	   0x1180080901740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM745"              ,	   0x1180080901748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM746"              ,	   0x1180080901750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM747"              ,	   0x1180080901758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM748"              ,	   0x1180080901760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM749"              ,	   0x1180080901768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM750"              ,	   0x1180080901770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM751"              ,	   0x1180080901778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM752"              ,	   0x1180080901780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM753"              ,	   0x1180080901788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM754"              ,	   0x1180080901790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM755"              ,	   0x1180080901798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM756"              ,	   0x11800809017a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM757"              ,	   0x11800809017a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM758"              ,	   0x11800809017b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM759"              ,	   0x11800809017b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM760"              ,	   0x11800809017c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM761"              ,	   0x11800809017c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM762"              ,	   0x11800809017d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM763"              ,	   0x11800809017d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM764"              ,	   0x11800809017e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM765"              ,	   0x11800809017e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM766"              ,	   0x11800809017f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM767"              ,	   0x11800809017f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM768"              ,	   0x1180080901800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM769"              ,	   0x1180080901808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM770"              ,	   0x1180080901810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM771"              ,	   0x1180080901818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM772"              ,	   0x1180080901820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM773"              ,	   0x1180080901828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM774"              ,	   0x1180080901830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM775"              ,	   0x1180080901838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM776"              ,	   0x1180080901840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM777"              ,	   0x1180080901848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM778"              ,	   0x1180080901850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM779"              ,	   0x1180080901858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM780"              ,	   0x1180080901860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM781"              ,	   0x1180080901868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM782"              ,	   0x1180080901870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM783"              ,	   0x1180080901878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM784"              ,	   0x1180080901880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM785"              ,	   0x1180080901888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM786"              ,	   0x1180080901890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM787"              ,	   0x1180080901898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM788"              ,	   0x11800809018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM789"              ,	   0x11800809018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM790"              ,	   0x11800809018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM791"              ,	   0x11800809018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM792"              ,	   0x11800809018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM793"              ,	   0x11800809018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM794"              ,	   0x11800809018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM795"              ,	   0x11800809018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM796"              ,	   0x11800809018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM797"              ,	   0x11800809018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM798"              ,	   0x11800809018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM799"              ,	   0x11800809018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM800"              ,	   0x1180080901900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM801"              ,	   0x1180080901908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM802"              ,	   0x1180080901910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM803"              ,	   0x1180080901918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM804"              ,	   0x1180080901920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM805"              ,	   0x1180080901928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM806"              ,	   0x1180080901930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM807"              ,	   0x1180080901938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM808"              ,	   0x1180080901940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM809"              ,	   0x1180080901948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM810"              ,	   0x1180080901950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM811"              ,	   0x1180080901958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM812"              ,	   0x1180080901960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM813"              ,	   0x1180080901968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM814"              ,	   0x1180080901970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM815"              ,	   0x1180080901978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM816"              ,	   0x1180080901980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM817"              ,	   0x1180080901988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM818"              ,	   0x1180080901990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM819"              ,	   0x1180080901998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM820"              ,	   0x11800809019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM821"              ,	   0x11800809019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM822"              ,	   0x11800809019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM823"              ,	   0x11800809019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM824"              ,	   0x11800809019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM825"              ,	   0x11800809019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM826"              ,	   0x11800809019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM827"              ,	   0x11800809019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM828"              ,	   0x11800809019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM829"              ,	   0x11800809019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM830"              ,	   0x11800809019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM831"              ,	   0x11800809019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM832"              ,	   0x1180080901a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM833"              ,	   0x1180080901a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM834"              ,	   0x1180080901a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM835"              ,	   0x1180080901a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM836"              ,	   0x1180080901a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM837"              ,	   0x1180080901a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM838"              ,	   0x1180080901a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM839"              ,	   0x1180080901a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM840"              ,	   0x1180080901a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM841"              ,	   0x1180080901a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM842"              ,	   0x1180080901a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM843"              ,	   0x1180080901a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM844"              ,	   0x1180080901a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM845"              ,	   0x1180080901a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM846"              ,	   0x1180080901a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM847"              ,	   0x1180080901a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM848"              ,	   0x1180080901a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM849"              ,	   0x1180080901a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM850"              ,	   0x1180080901a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM851"              ,	   0x1180080901a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM852"              ,	   0x1180080901aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM853"              ,	   0x1180080901aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM854"              ,	   0x1180080901ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM855"              ,	   0x1180080901ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM856"              ,	   0x1180080901ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM857"              ,	   0x1180080901ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM858"              ,	   0x1180080901ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM859"              ,	   0x1180080901ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM860"              ,	   0x1180080901ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM861"              ,	   0x1180080901ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM862"              ,	   0x1180080901af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM863"              ,	   0x1180080901af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM864"              ,	   0x1180080901b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM865"              ,	   0x1180080901b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM866"              ,	   0x1180080901b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM867"              ,	   0x1180080901b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM868"              ,	   0x1180080901b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM869"              ,	   0x1180080901b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM870"              ,	   0x1180080901b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM871"              ,	   0x1180080901b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM872"              ,	   0x1180080901b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM873"              ,	   0x1180080901b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM874"              ,	   0x1180080901b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM875"              ,	   0x1180080901b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM876"              ,	   0x1180080901b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM877"              ,	   0x1180080901b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM878"              ,	   0x1180080901b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM879"              ,	   0x1180080901b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM880"              ,	   0x1180080901b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM881"              ,	   0x1180080901b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM882"              ,	   0x1180080901b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM883"              ,	   0x1180080901b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM884"              ,	   0x1180080901ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM885"              ,	   0x1180080901ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM886"              ,	   0x1180080901bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM887"              ,	   0x1180080901bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM888"              ,	   0x1180080901bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM889"              ,	   0x1180080901bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM890"              ,	   0x1180080901bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM891"              ,	   0x1180080901bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM892"              ,	   0x1180080901be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM893"              ,	   0x1180080901be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM894"              ,	   0x1180080901bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM895"              ,	   0x1180080901bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM896"              ,	   0x1180080901c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM897"              ,	   0x1180080901c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM898"              ,	   0x1180080901c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM899"              ,	   0x1180080901c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM900"              ,	   0x1180080901c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM901"              ,	   0x1180080901c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM902"              ,	   0x1180080901c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM903"              ,	   0x1180080901c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM904"              ,	   0x1180080901c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM905"              ,	   0x1180080901c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM906"              ,	   0x1180080901c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM907"              ,	   0x1180080901c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM908"              ,	   0x1180080901c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM909"              ,	   0x1180080901c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM910"              ,	   0x1180080901c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM911"              ,	   0x1180080901c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM912"              ,	   0x1180080901c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM913"              ,	   0x1180080901c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM914"              ,	   0x1180080901c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM915"              ,	   0x1180080901c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM916"              ,	   0x1180080901ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM917"              ,	   0x1180080901ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM918"              ,	   0x1180080901cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM919"              ,	   0x1180080901cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM920"              ,	   0x1180080901cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM921"              ,	   0x1180080901cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM922"              ,	   0x1180080901cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM923"              ,	   0x1180080901cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM924"              ,	   0x1180080901ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM925"              ,	   0x1180080901ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM926"              ,	   0x1180080901cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM927"              ,	   0x1180080901cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM928"              ,	   0x1180080901d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM929"              ,	   0x1180080901d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM930"              ,	   0x1180080901d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM931"              ,	   0x1180080901d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM932"              ,	   0x1180080901d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM933"              ,	   0x1180080901d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM934"              ,	   0x1180080901d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM935"              ,	   0x1180080901d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM936"              ,	   0x1180080901d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM937"              ,	   0x1180080901d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM938"              ,	   0x1180080901d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM939"              ,	   0x1180080901d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM940"              ,	   0x1180080901d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM941"              ,	   0x1180080901d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM942"              ,	   0x1180080901d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM943"              ,	   0x1180080901d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM944"              ,	   0x1180080901d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM945"              ,	   0x1180080901d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM946"              ,	   0x1180080901d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM947"              ,	   0x1180080901d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM948"              ,	   0x1180080901da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM949"              ,	   0x1180080901da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM950"              ,	   0x1180080901db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM951"              ,	   0x1180080901db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM952"              ,	   0x1180080901dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM953"              ,	   0x1180080901dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM954"              ,	   0x1180080901dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM955"              ,	   0x1180080901dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM956"              ,	   0x1180080901de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM957"              ,	   0x1180080901de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM958"              ,	   0x1180080901df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM959"              ,	   0x1180080901df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM960"              ,	   0x1180080901e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM961"              ,	   0x1180080901e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM962"              ,	   0x1180080901e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM963"              ,	   0x1180080901e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM964"              ,	   0x1180080901e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM965"              ,	   0x1180080901e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM966"              ,	   0x1180080901e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM967"              ,	   0x1180080901e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM968"              ,	   0x1180080901e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM969"              ,	   0x1180080901e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM970"              ,	   0x1180080901e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM971"              ,	   0x1180080901e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM972"              ,	   0x1180080901e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM973"              ,	   0x1180080901e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM974"              ,	   0x1180080901e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM975"              ,	   0x1180080901e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM976"              ,	   0x1180080901e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM977"              ,	   0x1180080901e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM978"              ,	   0x1180080901e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM979"              ,	   0x1180080901e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM980"              ,	   0x1180080901ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM981"              ,	   0x1180080901ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM982"              ,	   0x1180080901eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM983"              ,	   0x1180080901eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM984"              ,	   0x1180080901ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM985"              ,	   0x1180080901ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM986"              ,	   0x1180080901ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM987"              ,	   0x1180080901ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM988"              ,	   0x1180080901ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM989"              ,	   0x1180080901ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM990"              ,	   0x1180080901ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM991"              ,	   0x1180080901ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM992"              ,	   0x1180080901f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM993"              ,	   0x1180080901f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM994"              ,	   0x1180080901f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM995"              ,	   0x1180080901f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM996"              ,	   0x1180080901f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM997"              ,	   0x1180080901f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM998"              ,	   0x1180080901f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM999"              ,	   0x1180080901f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1000"             ,	   0x1180080901f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1001"             ,	   0x1180080901f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1002"             ,	   0x1180080901f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1003"             ,	   0x1180080901f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1004"             ,	   0x1180080901f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1005"             ,	   0x1180080901f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1006"             ,	   0x1180080901f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1007"             ,	   0x1180080901f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1008"             ,	   0x1180080901f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1009"             ,	   0x1180080901f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1010"             ,	   0x1180080901f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1011"             ,	   0x1180080901f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1012"             ,	   0x1180080901fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1013"             ,	   0x1180080901fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1014"             ,	   0x1180080901fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1015"             ,	   0x1180080901fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1016"             ,	   0x1180080901fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1017"             ,	   0x1180080901fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1018"             ,	   0x1180080901fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1019"             ,	   0x1180080901fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1020"             ,	   0x1180080901fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1021"             ,	   0x1180080901fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1022"             ,	   0x1180080901ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_VRT_MEM1023"             ,	   0x1180080901ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"L2C_WPAR_IOB0"               ,	   0x1180080840200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"L2C_WPAR_PP0"                ,	   0x1180080840000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"L2C_WPAR_PP1"                ,	   0x1180080840008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"L2C_WPAR_PP2"                ,	   0x1180080840010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"L2C_WPAR_PP3"                ,	   0x1180080840018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"L2C_WPAR_PP4"                ,	   0x1180080840020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"L2C_WPAR_PP5"                ,	   0x1180080840028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"L2C_WPAR_PP6"                ,	   0x1180080840030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"L2C_WPAR_PP7"                ,	   0x1180080840038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"L2C_WPAR_PP8"                ,	   0x1180080840040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"L2C_WPAR_PP9"                ,	   0x1180080840048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"L2C_XMC0_PFC"                ,	   0x1180080800400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"L2C_XMC_CMD"                 ,	   0x1180080800028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"L2C_XMD0_PFC"                ,	   0x1180080800408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"LMC0_CHAR_CTL"               ,	   0x1180088000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"LMC0_CHAR_MASK0"             ,	   0x1180088000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"LMC0_CHAR_MASK1"             ,	   0x1180088000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"LMC0_CHAR_MASK2"             ,	   0x1180088000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"LMC0_CHAR_MASK3"             ,	   0x1180088000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"LMC0_CHAR_MASK4"             ,	   0x1180088000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"LMC0_COMP_CTL2"              ,	   0x11800880001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"LMC0_CONFIG"                 ,	   0x1180088000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"LMC0_CONTROL"                ,	   0x1180088000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"LMC0_DCLK_CNT"               ,	   0x11800880001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"LMC0_DDR_PLL_CTL"            ,	   0x1180088000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"LMC0_DIMM000_PARAMS"         ,	   0x1180088000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"LMC0_DIMM001_PARAMS"         ,	   0x1180088000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"LMC0_DIMM_CTL"               ,	   0x1180088000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"LMC0_DLL_CTL2"               ,	   0x11800880001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"LMC0_DLL_CTL3"               ,	   0x1180088000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"LMC0_DUAL_MEMCFG"            ,	   0x1180088000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"LMC0_IFB_CNT"                ,	   0x11800880001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"LMC0_INT"                    ,	   0x11800880001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"LMC0_INT_EN"                 ,	   0x11800880001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"LMC0_MODEREG_PARAMS0"        ,	   0x11800880001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"LMC0_MODEREG_PARAMS1"        ,	   0x1180088000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"LMC0_NXM"                    ,	   0x11800880000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"LMC0_OPS_CNT"                ,	   0x11800880001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"LMC0_PHY_CTL"                ,	   0x1180088000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	468},
+	{"LMC0_RESET_CTL"              ,	   0x1180088000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"LMC0_RLEVEL_CTL"             ,	   0x11800880002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"LMC0_RLEVEL_DBG"             ,	   0x11800880002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"LMC0_RLEVEL_RANK000"         ,	   0x1180088000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"LMC0_RLEVEL_RANK001"         ,	   0x1180088000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"LMC0_RLEVEL_RANK002"         ,	   0x1180088000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"LMC0_RLEVEL_RANK003"         ,	   0x1180088000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"LMC0_RODT_MASK"              ,	   0x1180088000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	473},
+	{"LMC0_SCRAMBLE_CFG0"          ,	   0x1180088000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	474},
+	{"LMC0_SCRAMBLE_CFG1"          ,	   0x1180088000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	475},
+	{"LMC0_SCRAMBLED_FADR"         ,	   0x1180088000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	476},
+	{"LMC0_SLOT_CTL0"              ,	   0x11800880001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	477},
+	{"LMC0_SLOT_CTL1"              ,	   0x1180088000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	478},
+	{"LMC0_SLOT_CTL2"              ,	   0x1180088000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"LMC0_TIMING_PARAMS0"         ,	   0x1180088000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	480},
+	{"LMC0_TIMING_PARAMS1"         ,	   0x11800880001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"LMC0_TRO_CTL"                ,	   0x1180088000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	482},
+	{"LMC0_TRO_STAT"               ,	   0x1180088000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	483},
+	{"LMC0_WLEVEL_CTL"             ,	   0x1180088000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	484},
+	{"LMC0_WLEVEL_DBG"             ,	   0x1180088000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	485},
+	{"LMC0_WLEVEL_RANK000"         ,	   0x11800880002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	486},
+	{"LMC0_WLEVEL_RANK001"         ,	   0x11800880002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	486},
+	{"LMC0_WLEVEL_RANK002"         ,	   0x11800880002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	486},
+	{"LMC0_WLEVEL_RANK003"         ,	   0x11800880002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	486},
+	{"LMC0_WODT_MASK"              ,	   0x11800880001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	487},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	488},
+	{"MIO_BOOT_COMP"               ,	   0x11800000000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	489},
+	{"MIO_BOOT_DMA_CFG0"           ,	   0x1180000000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	490},
+	{"MIO_BOOT_DMA_CFG1"           ,	   0x1180000000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	490},
+	{"MIO_BOOT_DMA_INT0"           ,	   0x1180000000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
+	{"MIO_BOOT_DMA_INT1"           ,	   0x1180000000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
+	{"MIO_BOOT_DMA_INT_EN0"        ,	   0x1180000000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	492},
+	{"MIO_BOOT_DMA_INT_EN1"        ,	   0x1180000000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	492},
+	{"MIO_BOOT_DMA_TIM0"           ,	   0x1180000000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	493},
+	{"MIO_BOOT_DMA_TIM1"           ,	   0x1180000000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	493},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	494},
+	{"MIO_BOOT_INT"                ,	   0x11800000000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	495},
+	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"MIO_BOOT_PIN_DEFS"           ,	   0x11800000000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"MIO_BOOT_REG_CFG3"           ,	   0x1180000000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"MIO_BOOT_REG_CFG4"           ,	   0x1180000000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"MIO_BOOT_REG_CFG5"           ,	   0x1180000000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"MIO_BOOT_REG_CFG6"           ,	   0x1180000000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"MIO_BOOT_REG_CFG7"           ,	   0x1180000000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"MIO_BOOT_REG_TIM0"           ,	   0x1180000000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"MIO_BOOT_REG_TIM1"           ,	   0x1180000000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"MIO_BOOT_REG_TIM2"           ,	   0x1180000000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"MIO_BOOT_REG_TIM3"           ,	   0x1180000000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"MIO_BOOT_REG_TIM4"           ,	   0x1180000000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"MIO_BOOT_THR"                ,	   0x11800000000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"MIO_FUS_DAT3"                ,	   0x1180000001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"MIO_FUS_EMA"                 ,	   0x1180000001550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"MIO_FUS_PDF"                 ,	   0x1180000001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"MIO_FUS_PLL"                 ,	   0x1180000001580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"MIO_FUS_PROG"                ,	   0x1180000001510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"MIO_FUS_PROG_TIMES"          ,	   0x1180000001518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"MIO_FUS_RCMD"                ,	   0x1180000001500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"MIO_FUS_READ_TIMES"          ,	   0x1180000001570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"MIO_FUS_REPAIR_RES0"         ,	   0x1180000001558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
+	{"MIO_FUS_REPAIR_RES1"         ,	   0x1180000001560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	516},
+	{"MIO_FUS_REPAIR_RES2"         ,	   0x1180000001568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	517},
+	{"MIO_FUS_SPR_REPAIR_RES"      ,	   0x1180000001548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	518},
+	{"MIO_FUS_SPR_REPAIR_SUM"      ,	   0x1180000001540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
+	{"MIO_FUS_TGG"                 ,	   0x1180000001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
+	{"MIO_FUS_WADR"                ,	   0x1180000001508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"MIO_GPIO_COMP"               ,	   0x11800000000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
+	{"MIO_NDF_DMA_CFG"             ,	   0x1180000000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
+	{"MIO_NDF_DMA_INT"             ,	   0x1180000000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
+	{"MIO_NDF_DMA_INT_EN"          ,	   0x1180000000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
+	{"MIO_PTP_CKOUT_HI_INCR"       ,	   0x1070000000f40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"MIO_PTP_CKOUT_LO_INCR"       ,	   0x1070000000f48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	527},
+	{"MIO_PTP_CKOUT_THRESH_HI"     ,	   0x1070000000f38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"MIO_PTP_CKOUT_THRESH_LO"     ,	   0x1070000000f30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"MIO_PTP_CLOCK_CFG"           ,	   0x1070000000f00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	530},
+	{"MIO_PTP_CLOCK_COMP"          ,	   0x1070000000f18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	531},
+	{"MIO_PTP_CLOCK_HI"            ,	   0x1070000000f10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	532},
+	{"MIO_PTP_CLOCK_LO"            ,	   0x1070000000f08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	533},
+	{"MIO_PTP_EVT_CNT"             ,	   0x1070000000f28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	534},
+	{"MIO_PTP_PPS_HI_INCR"         ,	   0x1070000000f60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	535},
+	{"MIO_PTP_PPS_LO_INCR"         ,	   0x1070000000f68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	536},
+	{"MIO_PTP_PPS_THRESH_HI"       ,	   0x1070000000f58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	537},
+	{"MIO_PTP_PPS_THRESH_LO"       ,	   0x1070000000f50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	538},
+	{"MIO_PTP_TIMESTAMP"           ,	   0x1070000000f20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	539},
+	{"MIO_QLM0_CFG"                ,	   0x1180000001590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
+	{"MIO_QLM1_CFG"                ,	   0x1180000001598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
+	{"MIO_QLM2_CFG"                ,	   0x11800000015a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
+	{"MIO_RST_BOOT"                ,	   0x1180000001600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
+	{"MIO_RST_CFG"                 ,	   0x1180000001610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	542},
+	{"MIO_RST_CKILL"               ,	   0x1180000001638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	543},
+	{"MIO_RST_CNTL0"               ,	   0x1180000001648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	544},
+	{"MIO_RST_CNTL1"               ,	   0x1180000001650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	544},
+	{"MIO_RST_CNTL2"               ,	   0x1180000001658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	544},
+	{"MIO_RST_CNTL3"               ,	   0x1180000001660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	544},
+	{"MIO_RST_CTL0"                ,	   0x1180000001618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"MIO_RST_CTL1"                ,	   0x1180000001620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"MIO_RST_DELAY"               ,	   0x1180000001608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
+	{"MIO_RST_INT"                 ,	   0x1180000001628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
+	{"MIO_RST_INT_EN"              ,	   0x1180000001630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	548},
+	{"MIO_TWS0_INT"                ,	   0x1180000001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	549},
+	{"MIO_TWS1_INT"                ,	   0x1180000001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	549},
+	{"MIO_TWS0_SW_TWSI"            ,	   0x1180000001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	550},
+	{"MIO_TWS1_SW_TWSI"            ,	   0x1180000001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	550},
+	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	551},
+	{"MIO_TWS1_SW_TWSI_EXT"        ,	   0x1180000001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	551},
+	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	552},
+	{"MIO_TWS1_TWSI_SW"            ,	   0x1180000001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	552},
+	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
+	{"MIO_UART1_DLH"               ,	   0x1180000000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
+	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
+	{"MIO_UART1_DLL"               ,	   0x1180000000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
+	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"MIO_UART1_FAR"               ,	   0x1180000000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
+	{"MIO_UART1_FCR"               ,	   0x1180000000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
+	{"MIO_UART0_HTX"               ,	   0x1180000000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
+	{"MIO_UART1_HTX"               ,	   0x1180000000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
+	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"MIO_UART1_IER"               ,	   0x1180000000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
+	{"MIO_UART1_IIR"               ,	   0x1180000000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
+	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
+	{"MIO_UART1_LCR"               ,	   0x1180000000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
+	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
+	{"MIO_UART1_LSR"               ,	   0x1180000000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
+	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
+	{"MIO_UART1_MCR"               ,	   0x1180000000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
+	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
+	{"MIO_UART1_MSR"               ,	   0x1180000000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
+	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
+	{"MIO_UART1_RBR"               ,	   0x1180000000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
+	{"MIO_UART0_RFL"               ,	   0x1180000000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
+	{"MIO_UART1_RFL"               ,	   0x1180000000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
+	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
+	{"MIO_UART1_RFW"               ,	   0x1180000000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
+	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"MIO_UART1_SCR"               ,	   0x1180000000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"MIO_UART0_SFE"               ,	   0x1180000000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	569},
+	{"MIO_UART1_SFE"               ,	   0x1180000000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	569},
+	{"MIO_UART0_SRR"               ,	   0x1180000000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	570},
+	{"MIO_UART1_SRR"               ,	   0x1180000000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	570},
+	{"MIO_UART0_SRT"               ,	   0x1180000000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	571},
+	{"MIO_UART1_SRT"               ,	   0x1180000000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	571},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	572},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	572},
+	{"MIO_UART0_STT"               ,	   0x1180000000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	573},
+	{"MIO_UART1_STT"               ,	   0x1180000000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	573},
+	{"MIO_UART0_TFL"               ,	   0x1180000000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	574},
+	{"MIO_UART1_TFL"               ,	   0x1180000000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	574},
+	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
+	{"MIO_UART1_TFR"               ,	   0x1180000000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
+	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
+	{"MIO_UART1_THR"               ,	   0x1180000000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
+	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	577},
+	{"MIO_UART1_USR"               ,	   0x1180000000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	577},
+	{"MIX0_BIST"                   ,	   0x1070000100078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	578},
+	{"MIX1_BIST"                   ,	   0x1070000100878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	578},
+	{"MIX0_CTL"                    ,	   0x1070000100020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	579},
+	{"MIX1_CTL"                    ,	   0x1070000100820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	579},
+	{"MIX0_INTENA"                 ,	   0x1070000100050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	580},
+	{"MIX1_INTENA"                 ,	   0x1070000100850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	580},
+	{"MIX0_IRCNT"                  ,	   0x1070000100030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	581},
+	{"MIX1_IRCNT"                  ,	   0x1070000100830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	581},
+	{"MIX0_IRHWM"                  ,	   0x1070000100028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	582},
+	{"MIX1_IRHWM"                  ,	   0x1070000100828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	582},
+	{"MIX0_IRING1"                 ,	   0x1070000100010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"MIX1_IRING1"                 ,	   0x1070000100810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"MIX0_IRING2"                 ,	   0x1070000100018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	584},
+	{"MIX1_IRING2"                 ,	   0x1070000100818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	584},
+	{"MIX0_ISR"                    ,	   0x1070000100048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	585},
+	{"MIX1_ISR"                    ,	   0x1070000100848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	585},
+	{"MIX0_ORCNT"                  ,	   0x1070000100040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	586},
+	{"MIX1_ORCNT"                  ,	   0x1070000100840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	586},
+	{"MIX0_ORHWM"                  ,	   0x1070000100038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	587},
+	{"MIX1_ORHWM"                  ,	   0x1070000100838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	587},
+	{"MIX0_ORING1"                 ,	   0x1070000100000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"MIX1_ORING1"                 ,	   0x1070000100800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"MIX0_ORING2"                 ,	   0x1070000100008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	589},
+	{"MIX1_ORING2"                 ,	   0x1070000100808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	589},
+	{"MIX0_REMCNT"                 ,	   0x1070000100058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	590},
+	{"MIX1_REMCNT"                 ,	   0x1070000100858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	590},
+	{"MIX0_TSCTL"                  ,	   0x1070000100068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	591},
+	{"MIX1_TSCTL"                  ,	   0x1070000100868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	591},
+	{"MIX0_TSTAMP"                 ,	   0x1070000100060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	592},
+	{"MIX1_TSTAMP"                 ,	   0x1070000100860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	592},
+	{"MPI_CFG"                     ,	   0x1070000001000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	593},
+	{"MPI_DAT0"                    ,	   0x1070000001080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	594},
+	{"MPI_DAT1"                    ,	   0x1070000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	594},
+	{"MPI_DAT2"                    ,	   0x1070000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	594},
+	{"MPI_DAT3"                    ,	   0x1070000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	594},
+	{"MPI_DAT4"                    ,	   0x10700000010a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	594},
+	{"MPI_DAT5"                    ,	   0x10700000010a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	594},
+	{"MPI_DAT6"                    ,	   0x10700000010b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	594},
+	{"MPI_DAT7"                    ,	   0x10700000010b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	594},
+	{"MPI_DAT8"                    ,	   0x10700000010c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	594},
+	{"MPI_STS"                     ,	   0x1070000001008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	595},
+	{"MPI_TX"                      ,	   0x1070000001010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	596},
+	{"NDF_BT_PG_INFO"              ,	   0x1070001000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	597},
+	{"NDF_CMD"                     ,	   0x1070001000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	598},
+	{"NDF_DRBELL"                  ,	   0x1070001000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	599},
+	{"NDF_ECC_CNT"                 ,	   0x1070001000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	600},
+	{"NDF_INT"                     ,	   0x1070001000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	601},
+	{"NDF_INT_EN"                  ,	   0x1070001000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	602},
+	{"NDF_MISC"                    ,	   0x1070001000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	603},
+	{"NDF_ST_REG"                  ,	   0x1070001000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	604},
+	{"PCIEEP0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	605},
+	{"PCIEEP1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	605},
+	{"PCIEEP0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	606},
+	{"PCIEEP1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	606},
+	{"PCIEEP0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	607},
+	{"PCIEEP1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	607},
+	{"PCIEEP0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	608},
+	{"PCIEEP1_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	608},
+	{"PCIEEP0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	609},
+	{"PCIEEP1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	609},
+	{"PCIEEP0_CFG004_MASK"         ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	610},
+	{"PCIEEP1_CFG004_MASK"         ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	610},
+	{"PCIEEP0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	611},
+	{"PCIEEP1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	611},
+	{"PCIEEP0_CFG005_MASK"         ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	612},
+	{"PCIEEP1_CFG005_MASK"         ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	612},
+	{"PCIEEP0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	613},
+	{"PCIEEP1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	613},
+	{"PCIEEP0_CFG006_MASK"         ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	614},
+	{"PCIEEP1_CFG006_MASK"         ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	614},
+	{"PCIEEP0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	615},
+	{"PCIEEP1_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	615},
+	{"PCIEEP0_CFG007_MASK"         ,	        0x8000001cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	616},
+	{"PCIEEP1_CFG007_MASK"         ,	        0x8000001cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	616},
+	{"PCIEEP0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	617},
+	{"PCIEEP1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	617},
+	{"PCIEEP0_CFG008_MASK"         ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	618},
+	{"PCIEEP1_CFG008_MASK"         ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	618},
+	{"PCIEEP0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	619},
+	{"PCIEEP1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	619},
+	{"PCIEEP0_CFG009_MASK"         ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	620},
+	{"PCIEEP1_CFG009_MASK"         ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	620},
+	{"PCIEEP0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	621},
+	{"PCIEEP1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	621},
+	{"PCIEEP0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	622},
+	{"PCIEEP1_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	622},
+	{"PCIEEP0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	623},
+	{"PCIEEP1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	623},
+	{"PCIEEP0_CFG012_MASK"         ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	624},
+	{"PCIEEP1_CFG012_MASK"         ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	624},
+	{"PCIEEP0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	625},
+	{"PCIEEP1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	625},
+	{"PCIEEP0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	626},
+	{"PCIEEP1_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	626},
+	{"PCIEEP0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	627},
+	{"PCIEEP1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	627},
+	{"PCIEEP0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	628},
+	{"PCIEEP1_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	628},
+	{"PCIEEP0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	629},
+	{"PCIEEP1_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	629},
+	{"PCIEEP0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	630},
+	{"PCIEEP1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	630},
+	{"PCIEEP0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	631},
+	{"PCIEEP1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	631},
+	{"PCIEEP0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	632},
+	{"PCIEEP1_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	632},
+	{"PCIEEP0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	633},
+	{"PCIEEP1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	633},
+	{"PCIEEP0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	634},
+	{"PCIEEP1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	634},
+	{"PCIEEP0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	635},
+	{"PCIEEP1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	635},
+	{"PCIEEP0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	636},
+	{"PCIEEP1_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	636},
+	{"PCIEEP0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	637},
+	{"PCIEEP1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	637},
+	{"PCIEEP0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	638},
+	{"PCIEEP1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	638},
+	{"PCIEEP0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	639},
+	{"PCIEEP1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	639},
+	{"PCIEEP0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	640},
+	{"PCIEEP1_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	640},
+	{"PCIEEP0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	641},
+	{"PCIEEP1_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	641},
+	{"PCIEEP0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	642},
+	{"PCIEEP1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	642},
+	{"PCIEEP0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	643},
+	{"PCIEEP1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	643},
+	{"PCIEEP0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	644},
+	{"PCIEEP1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	644},
+	{"PCIEEP0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	645},
+	{"PCIEEP1_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	645},
+	{"PCIEEP0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	646},
+	{"PCIEEP1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	646},
+	{"PCIEEP0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	647},
+	{"PCIEEP1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	647},
+	{"PCIEEP0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	648},
+	{"PCIEEP1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	648},
+	{"PCIEEP0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	649},
+	{"PCIEEP1_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	649},
+	{"PCIEEP0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	650},
+	{"PCIEEP1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	650},
+	{"PCIEEP0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	651},
+	{"PCIEEP1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	651},
+	{"PCIEEP0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	652},
+	{"PCIEEP1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	652},
+	{"PCIEEP0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	653},
+	{"PCIEEP1_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	653},
+	{"PCIEEP0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	654},
+	{"PCIEEP1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	654},
+	{"PCIEEP0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	655},
+	{"PCIEEP1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	655},
+	{"PCIEEP0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	656},
+	{"PCIEEP1_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	656},
+	{"PCIEEP0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	657},
+	{"PCIEEP1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	657},
+	{"PCIEEP0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	658},
+	{"PCIEEP1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	658},
+	{"PCIEEP0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	659},
+	{"PCIEEP1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	659},
+	{"PCIEEP0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	660},
+	{"PCIEEP1_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	660},
+	{"PCIEEP0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	661},
+	{"PCIEEP1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	661},
+	{"PCIEEP0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	662},
+	{"PCIEEP1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	662},
+	{"PCIEEP0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	663},
+	{"PCIEEP1_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	663},
+	{"PCIEEP0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	664},
+	{"PCIEEP1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	664},
+	{"PCIEEP0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	665},
+	{"PCIEEP1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	665},
+	{"PCIEEP0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	666},
+	{"PCIEEP1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	666},
+	{"PCIEEP0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	667},
+	{"PCIEEP1_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	667},
+	{"PCIEEP0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	668},
+	{"PCIEEP1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	668},
+	{"PCIEEP0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	669},
+	{"PCIEEP1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	669},
+	{"PCIEEP0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	670},
+	{"PCIEEP1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	670},
+	{"PCIEEP0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	671},
+	{"PCIEEP1_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	671},
+	{"PCIEEP0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	672},
+	{"PCIEEP1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	672},
+	{"PCIEEP0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	673},
+	{"PCIEEP1_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	673},
+	{"PCIEEP0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	674},
+	{"PCIEEP1_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	674},
+	{"PCIEEP0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	675},
+	{"PCIEEP1_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	675},
+	{"PCIEEP0_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	676},
+	{"PCIEEP1_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	676},
+	{"PCIEEP0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	677},
+	{"PCIEEP1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	677},
+	{"PCIEEP0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	678},
+	{"PCIEEP1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	678},
+	{"PCIERC0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	679},
+	{"PCIERC1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	679},
+	{"PCIERC0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	680},
+	{"PCIERC1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	680},
+	{"PCIERC0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	681},
+	{"PCIERC1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	681},
+	{"PCIERC0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	682},
+	{"PCIERC1_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	682},
+	{"PCIERC0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	683},
+	{"PCIERC1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	683},
+	{"PCIERC0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	684},
+	{"PCIERC1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	684},
+	{"PCIERC0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	685},
+	{"PCIERC1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	685},
+	{"PCIERC0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	686},
+	{"PCIERC1_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	686},
+	{"PCIERC0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	687},
+	{"PCIERC1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	687},
+	{"PCIERC0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	688},
+	{"PCIERC1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	688},
+	{"PCIERC0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	689},
+	{"PCIERC1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	689},
+	{"PCIERC0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	690},
+	{"PCIERC1_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	690},
+	{"PCIERC0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	691},
+	{"PCIERC1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	691},
+	{"PCIERC0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	692},
+	{"PCIERC1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	692},
+	{"PCIERC0_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	693},
+	{"PCIERC1_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	693},
+	{"PCIERC0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	694},
+	{"PCIERC1_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	694},
+	{"PCIERC0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	695},
+	{"PCIERC1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	695},
+	{"PCIERC0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	696},
+	{"PCIERC1_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	696},
+	{"PCIERC0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	697},
+	{"PCIERC1_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	697},
+	{"PCIERC0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	698},
+	{"PCIERC1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	698},
+	{"PCIERC0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	699},
+	{"PCIERC1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	699},
+	{"PCIERC0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	700},
+	{"PCIERC1_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	700},
+	{"PCIERC0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	701},
+	{"PCIERC1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	701},
+	{"PCIERC0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	702},
+	{"PCIERC1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	702},
+	{"PCIERC0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	703},
+	{"PCIERC1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	703},
+	{"PCIERC0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	704},
+	{"PCIERC1_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	704},
+	{"PCIERC0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	705},
+	{"PCIERC1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	705},
+	{"PCIERC0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	706},
+	{"PCIERC1_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	706},
+	{"PCIERC0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	707},
+	{"PCIERC1_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	707},
+	{"PCIERC0_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	708},
+	{"PCIERC1_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	708},
+	{"PCIERC0_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	709},
+	{"PCIERC1_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	709},
+	{"PCIERC0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	710},
+	{"PCIERC1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	710},
+	{"PCIERC0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	711},
+	{"PCIERC1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	711},
+	{"PCIERC0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	712},
+	{"PCIERC1_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	712},
+	{"PCIERC0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	713},
+	{"PCIERC1_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	713},
+	{"PCIERC0_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	714},
+	{"PCIERC1_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	714},
+	{"PCIERC0_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	715},
+	{"PCIERC1_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	715},
+	{"PCIERC0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	716},
+	{"PCIERC1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	716},
+	{"PCIERC0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	717},
+	{"PCIERC1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	717},
+	{"PCIERC0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	718},
+	{"PCIERC1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	718},
+	{"PCIERC0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	719},
+	{"PCIERC1_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	719},
+	{"PCIERC0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	720},
+	{"PCIERC1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	720},
+	{"PCIERC0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	721},
+	{"PCIERC1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	721},
+	{"PCIERC0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	722},
+	{"PCIERC1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	722},
+	{"PCIERC0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	723},
+	{"PCIERC1_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	723},
+	{"PCIERC0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	724},
+	{"PCIERC1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	724},
+	{"PCIERC0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	725},
+	{"PCIERC1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	725},
+	{"PCIERC0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	726},
+	{"PCIERC1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	726},
+	{"PCIERC0_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	727},
+	{"PCIERC1_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	727},
+	{"PCIERC0_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	728},
+	{"PCIERC1_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	728},
+	{"PCIERC0_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	729},
+	{"PCIERC1_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	729},
+	{"PCIERC0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	730},
+	{"PCIERC1_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	730},
+	{"PCIERC0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	731},
+	{"PCIERC1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	731},
+	{"PCIERC0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	732},
+	{"PCIERC1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	732},
+	{"PCIERC0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	733},
+	{"PCIERC1_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	733},
+	{"PCIERC0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	734},
+	{"PCIERC1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	734},
+	{"PCIERC0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	735},
+	{"PCIERC1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	735},
+	{"PCIERC0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	736},
+	{"PCIERC1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	736},
+	{"PCIERC0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	737},
+	{"PCIERC1_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	737},
+	{"PCIERC0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	738},
+	{"PCIERC1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	738},
+	{"PCIERC0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	739},
+	{"PCIERC1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	739},
+	{"PCIERC0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	740},
+	{"PCIERC1_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	740},
+	{"PCIERC0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	741},
+	{"PCIERC1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	741},
+	{"PCIERC0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	742},
+	{"PCIERC1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	742},
+	{"PCIERC0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	743},
+	{"PCIERC1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	743},
+	{"PCIERC0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	744},
+	{"PCIERC1_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	744},
+	{"PCIERC0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	745},
+	{"PCIERC1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	745},
+	{"PCIERC0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	746},
+	{"PCIERC1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	746},
+	{"PCIERC0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	747},
+	{"PCIERC1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	747},
+	{"PCIERC0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	748},
+	{"PCIERC1_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	748},
+	{"PCIERC0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	749},
+	{"PCIERC1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	749},
+	{"PCIERC0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	750},
+	{"PCIERC1_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	750},
+	{"PCIERC0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	751},
+	{"PCIERC1_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	751},
+	{"PCIERC0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	752},
+	{"PCIERC1_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	752},
+	{"PCIERC0_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	753},
+	{"PCIERC1_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	753},
+	{"PCIERC0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	754},
+	{"PCIERC1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	754},
+	{"PCIERC0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	755},
+	{"PCIERC1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	755},
+	{"PCS0_AN000_ADV_REG"          ,	   0x11800b0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PCS0_AN001_ADV_REG"          ,	   0x11800b0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PCS0_AN002_ADV_REG"          ,	   0x11800b0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PCS0_AN003_ADV_REG"          ,	   0x11800b0001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PCS1_AN000_ADV_REG"          ,	   0x11800b8001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PCS1_AN001_ADV_REG"          ,	   0x11800b8001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PCS1_AN002_ADV_REG"          ,	   0x11800b8001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PCS1_AN003_ADV_REG"          ,	   0x11800b8001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800b0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800b0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PCS0_AN002_EXT_ST_REG"       ,	   0x11800b0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PCS0_AN003_EXT_ST_REG"       ,	   0x11800b0001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PCS1_AN000_EXT_ST_REG"       ,	   0x11800b8001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PCS1_AN001_EXT_ST_REG"       ,	   0x11800b8001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PCS1_AN002_EXT_ST_REG"       ,	   0x11800b8001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PCS1_AN003_EXT_ST_REG"       ,	   0x11800b8001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800b0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800b0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PCS0_AN002_LP_ABIL_REG"      ,	   0x11800b0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PCS0_AN003_LP_ABIL_REG"      ,	   0x11800b0001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PCS1_AN000_LP_ABIL_REG"      ,	   0x11800b8001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PCS1_AN001_LP_ABIL_REG"      ,	   0x11800b8001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PCS1_AN002_LP_ABIL_REG"      ,	   0x11800b8001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PCS1_AN003_LP_ABIL_REG"      ,	   0x11800b8001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800b0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800b0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PCS0_AN002_RESULTS_REG"      ,	   0x11800b0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PCS0_AN003_RESULTS_REG"      ,	   0x11800b0001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PCS1_AN000_RESULTS_REG"      ,	   0x11800b8001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PCS1_AN001_RESULTS_REG"      ,	   0x11800b8001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PCS1_AN002_RESULTS_REG"      ,	   0x11800b8001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PCS1_AN003_RESULTS_REG"      ,	   0x11800b8001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PCS0_INT000_EN_REG"          ,	   0x11800b0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PCS0_INT001_EN_REG"          ,	   0x11800b0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PCS0_INT002_EN_REG"          ,	   0x11800b0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PCS0_INT003_EN_REG"          ,	   0x11800b0001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PCS1_INT000_EN_REG"          ,	   0x11800b8001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PCS1_INT001_EN_REG"          ,	   0x11800b8001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PCS1_INT002_EN_REG"          ,	   0x11800b8001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PCS1_INT003_EN_REG"          ,	   0x11800b8001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PCS0_INT000_REG"             ,	   0x11800b0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PCS0_INT001_REG"             ,	   0x11800b0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PCS0_INT002_REG"             ,	   0x11800b0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PCS0_INT003_REG"             ,	   0x11800b0001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PCS1_INT000_REG"             ,	   0x11800b8001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PCS1_INT001_REG"             ,	   0x11800b8001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PCS1_INT002_REG"             ,	   0x11800b8001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PCS1_INT003_REG"             ,	   0x11800b8001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800b0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800b0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PCS0_LINK002_TIMER_COUNT_REG",	   0x11800b0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PCS0_LINK003_TIMER_COUNT_REG",	   0x11800b0001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PCS1_LINK000_TIMER_COUNT_REG",	   0x11800b8001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PCS1_LINK001_TIMER_COUNT_REG",	   0x11800b8001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PCS1_LINK002_TIMER_COUNT_REG",	   0x11800b8001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PCS1_LINK003_TIMER_COUNT_REG",	   0x11800b8001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PCS0_LOG_ANL000_REG"         ,	   0x11800b0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PCS0_LOG_ANL001_REG"         ,	   0x11800b0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PCS0_LOG_ANL002_REG"         ,	   0x11800b0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PCS0_LOG_ANL003_REG"         ,	   0x11800b0001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PCS1_LOG_ANL000_REG"         ,	   0x11800b8001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PCS1_LOG_ANL001_REG"         ,	   0x11800b8001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PCS1_LOG_ANL002_REG"         ,	   0x11800b8001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PCS1_LOG_ANL003_REG"         ,	   0x11800b8001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PCS0_MISC000_CTL_REG"        ,	   0x11800b0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PCS0_MISC001_CTL_REG"        ,	   0x11800b0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PCS0_MISC002_CTL_REG"        ,	   0x11800b0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PCS0_MISC003_CTL_REG"        ,	   0x11800b0001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PCS1_MISC000_CTL_REG"        ,	   0x11800b8001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PCS1_MISC001_CTL_REG"        ,	   0x11800b8001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PCS1_MISC002_CTL_REG"        ,	   0x11800b8001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PCS1_MISC003_CTL_REG"        ,	   0x11800b8001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800b0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800b0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PCS0_MR002_CONTROL_REG"      ,	   0x11800b0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PCS0_MR003_CONTROL_REG"      ,	   0x11800b0001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PCS1_MR000_CONTROL_REG"      ,	   0x11800b8001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PCS1_MR001_CONTROL_REG"      ,	   0x11800b8001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PCS1_MR002_CONTROL_REG"      ,	   0x11800b8001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PCS1_MR003_CONTROL_REG"      ,	   0x11800b8001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PCS0_MR000_STATUS_REG"       ,	   0x11800b0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PCS0_MR001_STATUS_REG"       ,	   0x11800b0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PCS0_MR002_STATUS_REG"       ,	   0x11800b0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PCS0_MR003_STATUS_REG"       ,	   0x11800b0001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PCS1_MR000_STATUS_REG"       ,	   0x11800b8001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PCS1_MR001_STATUS_REG"       ,	   0x11800b8001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PCS1_MR002_STATUS_REG"       ,	   0x11800b8001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PCS1_MR003_STATUS_REG"       ,	   0x11800b8001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PCS0_RX000_STATES_REG"       ,	   0x11800b0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PCS0_RX001_STATES_REG"       ,	   0x11800b0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PCS0_RX002_STATES_REG"       ,	   0x11800b0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PCS0_RX003_STATES_REG"       ,	   0x11800b0001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PCS1_RX000_STATES_REG"       ,	   0x11800b8001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PCS1_RX001_STATES_REG"       ,	   0x11800b8001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PCS1_RX002_STATES_REG"       ,	   0x11800b8001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PCS1_RX003_STATES_REG"       ,	   0x11800b8001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PCS0_RX000_SYNC_REG"         ,	   0x11800b0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PCS0_RX001_SYNC_REG"         ,	   0x11800b0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PCS0_RX002_SYNC_REG"         ,	   0x11800b0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PCS0_RX003_SYNC_REG"         ,	   0x11800b0001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PCS1_RX000_SYNC_REG"         ,	   0x11800b8001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PCS1_RX001_SYNC_REG"         ,	   0x11800b8001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PCS1_RX002_SYNC_REG"         ,	   0x11800b8001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PCS1_RX003_SYNC_REG"         ,	   0x11800b8001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800b0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800b0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PCS0_SGM002_AN_ADV_REG"      ,	   0x11800b0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PCS0_SGM003_AN_ADV_REG"      ,	   0x11800b0001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PCS1_SGM000_AN_ADV_REG"      ,	   0x11800b8001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PCS1_SGM001_AN_ADV_REG"      ,	   0x11800b8001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PCS1_SGM002_AN_ADV_REG"      ,	   0x11800b8001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PCS1_SGM003_AN_ADV_REG"      ,	   0x11800b8001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800b0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800b0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PCS0_SGM002_LP_ADV_REG"      ,	   0x11800b0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PCS0_SGM003_LP_ADV_REG"      ,	   0x11800b0001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PCS1_SGM000_LP_ADV_REG"      ,	   0x11800b8001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PCS1_SGM001_LP_ADV_REG"      ,	   0x11800b8001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PCS1_SGM002_LP_ADV_REG"      ,	   0x11800b8001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PCS1_SGM003_LP_ADV_REG"      ,	   0x11800b8001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PCS0_TX000_STATES_REG"       ,	   0x11800b0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PCS0_TX001_STATES_REG"       ,	   0x11800b0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PCS0_TX002_STATES_REG"       ,	   0x11800b0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PCS0_TX003_STATES_REG"       ,	   0x11800b0001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PCS1_TX000_STATES_REG"       ,	   0x11800b8001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PCS1_TX001_STATES_REG"       ,	   0x11800b8001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PCS1_TX002_STATES_REG"       ,	   0x11800b8001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PCS1_TX003_STATES_REG"       ,	   0x11800b8001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800b0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800b0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PCS0_TX_RX002_POLARITY_REG"  ,	   0x11800b0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PCS0_TX_RX003_POLARITY_REG"  ,	   0x11800b0001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PCS1_TX_RX000_POLARITY_REG"  ,	   0x11800b8001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PCS1_TX_RX001_POLARITY_REG"  ,	   0x11800b8001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PCS1_TX_RX002_POLARITY_REG"  ,	   0x11800b8001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PCS1_TX_RX003_POLARITY_REG"  ,	   0x11800b8001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PCSX0_10GBX_STATUS_REG"      ,	   0x11800b0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PCSX1_10GBX_STATUS_REG"      ,	   0x11800b8000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PCSX0_BIST_STATUS_REG"       ,	   0x11800b0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PCSX1_BIST_STATUS_REG"       ,	   0x11800b8000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PCSX0_BIT_LOCK_STATUS_REG"   ,	   0x11800b0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PCSX1_BIT_LOCK_STATUS_REG"   ,	   0x11800b8000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PCSX0_CONTROL1_REG"          ,	   0x11800b0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PCSX1_CONTROL1_REG"          ,	   0x11800b8000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PCSX0_CONTROL2_REG"          ,	   0x11800b0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PCSX1_CONTROL2_REG"          ,	   0x11800b8000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PCSX0_INT_EN_REG"            ,	   0x11800b0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PCSX1_INT_EN_REG"            ,	   0x11800b8000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PCSX0_INT_REG"               ,	   0x11800b0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PCSX1_INT_REG"               ,	   0x11800b8000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PCSX0_LOG_ANL_REG"           ,	   0x11800b0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PCSX1_LOG_ANL_REG"           ,	   0x11800b8000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PCSX0_MISC_CTL_REG"          ,	   0x11800b0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PCSX1_MISC_CTL_REG"          ,	   0x11800b8000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PCSX0_RX_SYNC_STATES_REG"    ,	   0x11800b0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PCSX1_RX_SYNC_STATES_REG"    ,	   0x11800b8000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PCSX0_SPD_ABIL_REG"          ,	   0x11800b0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PCSX1_SPD_ABIL_REG"          ,	   0x11800b8000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PCSX0_STATUS1_REG"           ,	   0x11800b0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PCSX1_STATUS1_REG"           ,	   0x11800b8000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PCSX0_STATUS2_REG"           ,	   0x11800b0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PCSX1_STATUS2_REG"           ,	   0x11800b8000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PCSX0_TX_RX_POLARITY_REG"    ,	   0x11800b0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PCSX1_TX_RX_POLARITY_REG"    ,	   0x11800b8000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PCSX0_TX_RX_STATES_REG"      ,	   0x11800b0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PCSX1_TX_RX_STATES_REG"      ,	   0x11800b8000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PEM0_BAR1_INDEX000"          ,	   0x11800c00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM0_BAR1_INDEX001"          ,	   0x11800c00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM0_BAR1_INDEX002"          ,	   0x11800c00000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM0_BAR1_INDEX003"          ,	   0x11800c00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM0_BAR1_INDEX004"          ,	   0x11800c00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM0_BAR1_INDEX005"          ,	   0x11800c00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM0_BAR1_INDEX006"          ,	   0x11800c00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM0_BAR1_INDEX007"          ,	   0x11800c00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM0_BAR1_INDEX008"          ,	   0x11800c00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM0_BAR1_INDEX009"          ,	   0x11800c00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM0_BAR1_INDEX010"          ,	   0x11800c00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM0_BAR1_INDEX011"          ,	   0x11800c0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM0_BAR1_INDEX012"          ,	   0x11800c0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM0_BAR1_INDEX013"          ,	   0x11800c0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM0_BAR1_INDEX014"          ,	   0x11800c0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM0_BAR1_INDEX015"          ,	   0x11800c0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM1_BAR1_INDEX000"          ,	   0x11800c10000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM1_BAR1_INDEX001"          ,	   0x11800c10000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM1_BAR1_INDEX002"          ,	   0x11800c10000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM1_BAR1_INDEX003"          ,	   0x11800c10000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM1_BAR1_INDEX004"          ,	   0x11800c10000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM1_BAR1_INDEX005"          ,	   0x11800c10000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM1_BAR1_INDEX006"          ,	   0x11800c10000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM1_BAR1_INDEX007"          ,	   0x11800c10000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM1_BAR1_INDEX008"          ,	   0x11800c10000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM1_BAR1_INDEX009"          ,	   0x11800c10000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM1_BAR1_INDEX010"          ,	   0x11800c10000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM1_BAR1_INDEX011"          ,	   0x11800c1000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM1_BAR1_INDEX012"          ,	   0x11800c1000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM1_BAR1_INDEX013"          ,	   0x11800c1000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM1_BAR1_INDEX014"          ,	   0x11800c1000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM1_BAR1_INDEX015"          ,	   0x11800c1000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PEM0_BAR2_MASK"              ,	   0x11800c0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PEM1_BAR2_MASK"              ,	   0x11800c1000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PEM0_BAR_CTL"                ,	   0x11800c0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PEM1_BAR_CTL"                ,	   0x11800c1000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PEM0_BIST_STATUS"            ,	   0x11800c0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM1_BIST_STATUS"            ,	   0x11800c1000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PEM0_BIST_STATUS2"           ,	   0x11800c0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PEM1_BIST_STATUS2"           ,	   0x11800c1000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PEM0_CFG_RD"                 ,	   0x11800c0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PEM1_CFG_RD"                 ,	   0x11800c1000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PEM0_CFG_WR"                 ,	   0x11800c0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PEM1_CFG_WR"                 ,	   0x11800c1000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PEM0_CPL_LUT_VALID"          ,	   0x11800c0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"PEM1_CPL_LUT_VALID"          ,	   0x11800c1000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"PEM0_CTL_STATUS"             ,	   0x11800c0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PEM1_CTL_STATUS"             ,	   0x11800c1000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PEM0_DBG_INFO"               ,	   0x11800c0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PEM1_DBG_INFO"               ,	   0x11800c1000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PEM0_DBG_INFO_EN"            ,	   0x11800c00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PEM1_DBG_INFO_EN"            ,	   0x11800c10000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PEM0_DIAG_STATUS"            ,	   0x11800c0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PEM1_DIAG_STATUS"            ,	   0x11800c1000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PEM0_INB_READ_CREDITS"       ,	   0x11800c0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PEM1_INB_READ_CREDITS"       ,	   0x11800c1000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PEM0_INT_ENB"                ,	   0x11800c0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"PEM1_INT_ENB"                ,	   0x11800c1000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"PEM0_INT_ENB_INT"            ,	   0x11800c0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"PEM1_INT_ENB_INT"            ,	   0x11800c1000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"PEM0_INT_SUM"                ,	   0x11800c0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"PEM1_INT_SUM"                ,	   0x11800c1000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"PEM0_P2N_BAR0_START"         ,	   0x11800c0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"PEM1_P2N_BAR0_START"         ,	   0x11800c1000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"PEM0_P2N_BAR1_START"         ,	   0x11800c0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"PEM1_P2N_BAR1_START"         ,	   0x11800c1000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"PEM0_P2N_BAR2_START"         ,	   0x11800c0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
+	{"PEM1_P2N_BAR2_START"         ,	   0x11800c1000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
+	{"PEM0_P2P_BAR000_END"         ,	   0x11800c0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"PEM0_P2P_BAR001_END"         ,	   0x11800c0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"PEM0_P2P_BAR002_END"         ,	   0x11800c0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"PEM0_P2P_BAR003_END"         ,	   0x11800c0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"PEM1_P2P_BAR000_END"         ,	   0x11800c1000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"PEM1_P2P_BAR001_END"         ,	   0x11800c1000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"PEM1_P2P_BAR002_END"         ,	   0x11800c1000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"PEM1_P2P_BAR003_END"         ,	   0x11800c1000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"PEM0_P2P_BAR000_START"       ,	   0x11800c0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"PEM0_P2P_BAR001_START"       ,	   0x11800c0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"PEM0_P2P_BAR002_START"       ,	   0x11800c0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"PEM0_P2P_BAR003_START"       ,	   0x11800c0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"PEM1_P2P_BAR000_START"       ,	   0x11800c1000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"PEM1_P2P_BAR001_START"       ,	   0x11800c1000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"PEM1_P2P_BAR002_START"       ,	   0x11800c1000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"PEM1_P2P_BAR003_START"       ,	   0x11800c1000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"PEM0_TLP_CREDITS"            ,	   0x11800c0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
+	{"PEM1_TLP_CREDITS"            ,	   0x11800c1000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
+	{"PIP_ALT_SKIP_CFG0"           ,	   0x11800a0002a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
+	{"PIP_ALT_SKIP_CFG1"           ,	   0x11800a0002a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
+	{"PIP_ALT_SKIP_CFG2"           ,	   0x11800a0002a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
+	{"PIP_ALT_SKIP_CFG3"           ,	   0x11800a0002a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
+	{"PIP_BCK_PRS"                 ,	   0x11800a0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
+	{"PIP_BIST_STATUS"             ,	   0x11800a0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
+	{"PIP_CLKEN"                   ,	   0x11800a0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800a0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800a0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800a0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800a0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"PIP_DSA_SRC_GRP"             ,	   0x11800a0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
+	{"PIP_DSA_VID_GRP"             ,	   0x11800a0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PIP_FRM_LEN_CHK0"            ,	   0x11800a0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	817},
+	{"PIP_GBL_CFG"                 ,	   0x11800a0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
+	{"PIP_GBL_CTL"                 ,	   0x11800a0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	819},
+	{"PIP_HG_PRI_QOS"              ,	   0x11800a00001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	820},
+	{"PIP_INT_EN"                  ,	   0x11800a0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	821},
+	{"PIP_INT_REG"                 ,	   0x11800a0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	822},
+	{"PIP_IP_OFFSET"               ,	   0x11800a0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	823},
+	{"PIP_PRT_CFG0"                ,	   0x11800a0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG1"                ,	   0x11800a0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG2"                ,	   0x11800a0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG3"                ,	   0x11800a0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG16"               ,	   0x11800a0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG17"               ,	   0x11800a0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG18"               ,	   0x11800a0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG19"               ,	   0x11800a0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG32"               ,	   0x11800a0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG33"               ,	   0x11800a0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG34"               ,	   0x11800a0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG35"               ,	   0x11800a0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG36"               ,	   0x11800a0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG37"               ,	   0x11800a0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG38"               ,	   0x11800a0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG39"               ,	   0x11800a0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG40"               ,	   0x11800a0000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG41"               ,	   0x11800a0000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG44"               ,	   0x11800a0000360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG45"               ,	   0x11800a0000368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG46"               ,	   0x11800a0000370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFG47"               ,	   0x11800a0000378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PIP_PRT_CFGB0"               ,	   0x11800a0008000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB1"               ,	   0x11800a0008008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB2"               ,	   0x11800a0008010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB3"               ,	   0x11800a0008018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB16"              ,	   0x11800a0008080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB17"              ,	   0x11800a0008088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB18"              ,	   0x11800a0008090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB19"              ,	   0x11800a0008098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB32"              ,	   0x11800a0008100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB33"              ,	   0x11800a0008108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB34"              ,	   0x11800a0008110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB35"              ,	   0x11800a0008118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB36"              ,	   0x11800a0008120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB37"              ,	   0x11800a0008128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB38"              ,	   0x11800a0008130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB39"              ,	   0x11800a0008138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB40"              ,	   0x11800a0008140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB41"              ,	   0x11800a0008148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB42"              ,	   0x11800a0008150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB43"              ,	   0x11800a0008158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB44"              ,	   0x11800a0008160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB45"              ,	   0x11800a0008168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB46"              ,	   0x11800a0008170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_CFGB47"              ,	   0x11800a0008178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PIP_PRT_TAG0"                ,	   0x11800a0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG1"                ,	   0x11800a0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG2"                ,	   0x11800a0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG3"                ,	   0x11800a0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG16"               ,	   0x11800a0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG17"               ,	   0x11800a0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG18"               ,	   0x11800a0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG19"               ,	   0x11800a0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG32"               ,	   0x11800a0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG33"               ,	   0x11800a0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG34"               ,	   0x11800a0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG35"               ,	   0x11800a0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG36"               ,	   0x11800a0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG37"               ,	   0x11800a0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG38"               ,	   0x11800a0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG39"               ,	   0x11800a0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG40"               ,	   0x11800a0000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG41"               ,	   0x11800a0000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG44"               ,	   0x11800a0000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG45"               ,	   0x11800a0000568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG46"               ,	   0x11800a0000570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_PRT_TAG47"               ,	   0x11800a0000578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PIP_QOS_DIFF0"               ,	   0x11800a0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF1"               ,	   0x11800a0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF2"               ,	   0x11800a0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF3"               ,	   0x11800a0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF4"               ,	   0x11800a0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF5"               ,	   0x11800a0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF6"               ,	   0x11800a0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF7"               ,	   0x11800a0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF8"               ,	   0x11800a0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF9"               ,	   0x11800a0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF10"              ,	   0x11800a0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF11"              ,	   0x11800a0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF12"              ,	   0x11800a0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF13"              ,	   0x11800a0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF14"              ,	   0x11800a0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF15"              ,	   0x11800a0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF16"              ,	   0x11800a0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF17"              ,	   0x11800a0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF18"              ,	   0x11800a0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF19"              ,	   0x11800a0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF20"              ,	   0x11800a00006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF21"              ,	   0x11800a00006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF22"              ,	   0x11800a00006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF23"              ,	   0x11800a00006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF24"              ,	   0x11800a00006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF25"              ,	   0x11800a00006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF26"              ,	   0x11800a00006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF27"              ,	   0x11800a00006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF28"              ,	   0x11800a00006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF29"              ,	   0x11800a00006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF30"              ,	   0x11800a00006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF31"              ,	   0x11800a00006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF32"              ,	   0x11800a0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF33"              ,	   0x11800a0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF34"              ,	   0x11800a0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF35"              ,	   0x11800a0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF36"              ,	   0x11800a0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF37"              ,	   0x11800a0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF38"              ,	   0x11800a0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF39"              ,	   0x11800a0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF40"              ,	   0x11800a0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF41"              ,	   0x11800a0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF42"              ,	   0x11800a0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF43"              ,	   0x11800a0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF44"              ,	   0x11800a0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF45"              ,	   0x11800a0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF46"              ,	   0x11800a0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF47"              ,	   0x11800a0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF48"              ,	   0x11800a0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF49"              ,	   0x11800a0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF50"              ,	   0x11800a0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF51"              ,	   0x11800a0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF52"              ,	   0x11800a00007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF53"              ,	   0x11800a00007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF54"              ,	   0x11800a00007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF55"              ,	   0x11800a00007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF56"              ,	   0x11800a00007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF57"              ,	   0x11800a00007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF58"              ,	   0x11800a00007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF59"              ,	   0x11800a00007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF60"              ,	   0x11800a00007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF61"              ,	   0x11800a00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF62"              ,	   0x11800a00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_DIFF63"              ,	   0x11800a00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PIP_QOS_VLAN0"               ,	   0x11800a00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_QOS_VLAN1"               ,	   0x11800a00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_QOS_VLAN2"               ,	   0x11800a00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_QOS_VLAN3"               ,	   0x11800a00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_QOS_VLAN4"               ,	   0x11800a00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_QOS_VLAN5"               ,	   0x11800a00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_QOS_VLAN6"               ,	   0x11800a00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_QOS_VLAN7"               ,	   0x11800a00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PIP_QOS_WATCH0"              ,	   0x11800a0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_QOS_WATCH1"              ,	   0x11800a0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_QOS_WATCH2"              ,	   0x11800a0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_QOS_WATCH3"              ,	   0x11800a0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_QOS_WATCH4"              ,	   0x11800a0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_QOS_WATCH5"              ,	   0x11800a0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_QOS_WATCH6"              ,	   0x11800a0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_QOS_WATCH7"              ,	   0x11800a0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PIP_RAW_WORD"                ,	   0x11800a00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PIP_SFT_RST"                 ,	   0x11800a0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PIP_STAT0_PRT0"              ,	   0x11800a0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_STAT0_PRT1"              ,	   0x11800a0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_STAT0_PRT2"              ,	   0x11800a00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_STAT0_PRT3"              ,	   0x11800a00008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_STAT0_PRT16"             ,	   0x11800a0000d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_STAT0_PRT17"             ,	   0x11800a0000d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_STAT0_PRT18"             ,	   0x11800a0000da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_STAT0_PRT19"             ,	   0x11800a0000df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_STAT0_PRT32"             ,	   0x11800a0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_STAT0_PRT33"             ,	   0x11800a0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_STAT0_PRT34"             ,	   0x11800a00012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_STAT0_PRT35"             ,	   0x11800a00012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_STAT0_PRT36"             ,	   0x11800a0001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_STAT0_PRT37"             ,	   0x11800a0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_STAT0_PRT38"             ,	   0x11800a00013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_STAT0_PRT39"             ,	   0x11800a0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PIP_STAT10_PRT0"             ,	   0x11800a0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_STAT10_PRT1"             ,	   0x11800a0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_STAT10_PRT2"             ,	   0x11800a00014a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_STAT10_PRT3"             ,	   0x11800a00014b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_STAT10_PRT16"            ,	   0x11800a0001580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_STAT10_PRT17"            ,	   0x11800a0001590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_STAT10_PRT18"            ,	   0x11800a00015a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_STAT10_PRT19"            ,	   0x11800a00015b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_STAT10_PRT32"            ,	   0x11800a0001680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_STAT10_PRT33"            ,	   0x11800a0001690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_STAT10_PRT34"            ,	   0x11800a00016a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_STAT10_PRT35"            ,	   0x11800a00016b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_STAT10_PRT36"            ,	   0x11800a00016c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_STAT10_PRT37"            ,	   0x11800a00016d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_STAT10_PRT38"            ,	   0x11800a00016e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_STAT10_PRT39"            ,	   0x11800a00016f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PIP_STAT11_PRT0"             ,	   0x11800a0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PIP_STAT11_PRT1"             ,	   0x11800a0001498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PIP_STAT11_PRT2"             ,	   0x11800a00014a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PIP_STAT11_PRT3"             ,	   0x11800a00014b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PIP_STAT11_PRT16"            ,	   0x11800a0001588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PIP_STAT11_PRT17"            ,	   0x11800a0001598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PIP_STAT11_PRT18"            ,	   0x11800a00015a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PIP_STAT11_PRT19"            ,	   0x11800a00015b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PIP_STAT11_PRT32"            ,	   0x11800a0001688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PIP_STAT11_PRT33"            ,	   0x11800a0001698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PIP_STAT11_PRT34"            ,	   0x11800a00016a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PIP_STAT11_PRT35"            ,	   0x11800a00016b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PIP_STAT11_PRT36"            ,	   0x11800a00016c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PIP_STAT11_PRT37"            ,	   0x11800a00016d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PIP_STAT11_PRT38"            ,	   0x11800a00016e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PIP_STAT11_PRT39"            ,	   0x11800a00016f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PIP_STAT1_PRT3"              ,	   0x11800a00008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PIP_STAT1_PRT16"             ,	   0x11800a0000d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PIP_STAT1_PRT17"             ,	   0x11800a0000d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PIP_STAT1_PRT18"             ,	   0x11800a0000da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PIP_STAT1_PRT19"             ,	   0x11800a0000df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PIP_STAT1_PRT32"             ,	   0x11800a0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PIP_STAT1_PRT33"             ,	   0x11800a0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PIP_STAT1_PRT34"             ,	   0x11800a00012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PIP_STAT1_PRT35"             ,	   0x11800a00012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PIP_STAT1_PRT36"             ,	   0x11800a0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PIP_STAT1_PRT37"             ,	   0x11800a0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PIP_STAT1_PRT38"             ,	   0x11800a00013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PIP_STAT1_PRT39"             ,	   0x11800a0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT2_PRT3"              ,	   0x11800a0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT2_PRT16"             ,	   0x11800a0000d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT2_PRT17"             ,	   0x11800a0000d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT2_PRT18"             ,	   0x11800a0000db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT2_PRT19"             ,	   0x11800a0000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT2_PRT32"             ,	   0x11800a0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT2_PRT33"             ,	   0x11800a0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT2_PRT34"             ,	   0x11800a00012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT2_PRT35"             ,	   0x11800a0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT2_PRT36"             ,	   0x11800a0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT2_PRT37"             ,	   0x11800a00013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT2_PRT38"             ,	   0x11800a00013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT2_PRT39"             ,	   0x11800a0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT3_PRT3"              ,	   0x11800a0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT3_PRT16"             ,	   0x11800a0000d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT3_PRT17"             ,	   0x11800a0000d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT3_PRT18"             ,	   0x11800a0000db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT3_PRT19"             ,	   0x11800a0000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT3_PRT32"             ,	   0x11800a0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT3_PRT33"             ,	   0x11800a0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT3_PRT34"             ,	   0x11800a00012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT3_PRT35"             ,	   0x11800a0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT3_PRT36"             ,	   0x11800a0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT3_PRT37"             ,	   0x11800a00013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT3_PRT38"             ,	   0x11800a00013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT3_PRT39"             ,	   0x11800a0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT4_PRT3"              ,	   0x11800a0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT4_PRT16"             ,	   0x11800a0000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT4_PRT17"             ,	   0x11800a0000d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT4_PRT18"             ,	   0x11800a0000dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT4_PRT19"             ,	   0x11800a0000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT4_PRT32"             ,	   0x11800a0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT4_PRT33"             ,	   0x11800a0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT4_PRT34"             ,	   0x11800a00012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT4_PRT35"             ,	   0x11800a0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT4_PRT36"             ,	   0x11800a0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT4_PRT37"             ,	   0x11800a00013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT4_PRT38"             ,	   0x11800a0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT4_PRT39"             ,	   0x11800a0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT5_PRT3"              ,	   0x11800a0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT5_PRT16"             ,	   0x11800a0000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT5_PRT17"             ,	   0x11800a0000d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT5_PRT18"             ,	   0x11800a0000dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT5_PRT19"             ,	   0x11800a0000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT5_PRT32"             ,	   0x11800a0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT5_PRT33"             ,	   0x11800a0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT5_PRT34"             ,	   0x11800a00012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT5_PRT35"             ,	   0x11800a0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT5_PRT36"             ,	   0x11800a0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT5_PRT37"             ,	   0x11800a00013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT5_PRT38"             ,	   0x11800a0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT5_PRT39"             ,	   0x11800a0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT6_PRT3"              ,	   0x11800a0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT6_PRT16"             ,	   0x11800a0000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT6_PRT17"             ,	   0x11800a0000d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT6_PRT18"             ,	   0x11800a0000dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT6_PRT19"             ,	   0x11800a0000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT6_PRT32"             ,	   0x11800a0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT6_PRT33"             ,	   0x11800a0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT6_PRT34"             ,	   0x11800a00012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT6_PRT35"             ,	   0x11800a0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT6_PRT36"             ,	   0x11800a0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT6_PRT37"             ,	   0x11800a00013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT6_PRT38"             ,	   0x11800a0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT6_PRT39"             ,	   0x11800a0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT7_PRT3"              ,	   0x11800a0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT7_PRT16"             ,	   0x11800a0000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT7_PRT17"             ,	   0x11800a0000d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT7_PRT18"             ,	   0x11800a0000dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT7_PRT19"             ,	   0x11800a0000e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT7_PRT32"             ,	   0x11800a0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT7_PRT33"             ,	   0x11800a0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT7_PRT34"             ,	   0x11800a00012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT7_PRT35"             ,	   0x11800a0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT7_PRT36"             ,	   0x11800a0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT7_PRT37"             ,	   0x11800a00013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT7_PRT38"             ,	   0x11800a0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT7_PRT39"             ,	   0x11800a0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT8_PRT3"              ,	   0x11800a0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT8_PRT16"             ,	   0x11800a0000d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT8_PRT17"             ,	   0x11800a0000d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT8_PRT18"             ,	   0x11800a0000de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT8_PRT19"             ,	   0x11800a0000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT8_PRT32"             ,	   0x11800a0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT8_PRT33"             ,	   0x11800a0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT8_PRT34"             ,	   0x11800a00012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT8_PRT35"             ,	   0x11800a0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT8_PRT36"             ,	   0x11800a0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT8_PRT37"             ,	   0x11800a00013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT8_PRT38"             ,	   0x11800a0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT8_PRT39"             ,	   0x11800a0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT9_PRT3"              ,	   0x11800a0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT9_PRT16"             ,	   0x11800a0000d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT9_PRT17"             ,	   0x11800a0000d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT9_PRT18"             ,	   0x11800a0000de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT9_PRT19"             ,	   0x11800a0000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT9_PRT32"             ,	   0x11800a0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT9_PRT33"             ,	   0x11800a0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT9_PRT34"             ,	   0x11800a00012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT9_PRT35"             ,	   0x11800a0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT9_PRT36"             ,	   0x11800a0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT9_PRT37"             ,	   0x11800a00013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT9_PRT38"             ,	   0x11800a0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT9_PRT39"             ,	   0x11800a0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800a0001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS16"         ,	   0x11800a0001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS17"         ,	   0x11800a0001c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS18"         ,	   0x11800a0001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS19"         ,	   0x11800a0001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800a0001e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800a0001e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800a0001e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800a0001e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS36"         ,	   0x11800a0001e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS37"         ,	   0x11800a0001eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS38"         ,	   0x11800a0001ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS39"         ,	   0x11800a0001ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS40"         ,	   0x11800a0001f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS41"         ,	   0x11800a0001f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS44"         ,	   0x11800a0001f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS45"         ,	   0x11800a0001fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS46"         ,	   0x11800a0001fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_ERRS47"         ,	   0x11800a0001ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800a0001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS16"         ,	   0x11800a0001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS17"         ,	   0x11800a0001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS18"         ,	   0x11800a0001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS19"         ,	   0x11800a0001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800a0001e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800a0001e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800a0001e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800a0001e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS36"         ,	   0x11800a0001e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS37"         ,	   0x11800a0001ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS38"         ,	   0x11800a0001ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS39"         ,	   0x11800a0001ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS40"         ,	   0x11800a0001f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS41"         ,	   0x11800a0001f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS44"         ,	   0x11800a0001f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS45"         ,	   0x11800a0001fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS46"         ,	   0x11800a0001fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_OCTS47"         ,	   0x11800a0001fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800a0001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS16"         ,	   0x11800a0001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS17"         ,	   0x11800a0001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS18"         ,	   0x11800a0001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS19"         ,	   0x11800a0001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800a0001e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800a0001e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800a0001e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800a0001e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS36"         ,	   0x11800a0001e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS37"         ,	   0x11800a0001ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS38"         ,	   0x11800a0001ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS39"         ,	   0x11800a0001ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS40"         ,	   0x11800a0001f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS41"         ,	   0x11800a0001f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS44"         ,	   0x11800a0001f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS45"         ,	   0x11800a0001fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS46"         ,	   0x11800a0001fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_STAT_INB_PKTS47"         ,	   0x11800a0001fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"PIP_VLAN_ETYPES0"            ,	   0x11800a00001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_VLAN_ETYPES1"            ,	   0x11800a00001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"PIP_XSTAT0_PRT40"            ,	   0x11800a0002000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	853},
+	{"PIP_XSTAT0_PRT41"            ,	   0x11800a0002050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	853},
+	{"PIP_XSTAT0_PRT44"            ,	   0x11800a0002140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	853},
+	{"PIP_XSTAT0_PRT45"            ,	   0x11800a0002190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	853},
+	{"PIP_XSTAT0_PRT46"            ,	   0x11800a00021e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	853},
+	{"PIP_XSTAT0_PRT47"            ,	   0x11800a0002230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	853},
+	{"PIP_XSTAT10_PRT40"           ,	   0x11800a0001700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	854},
+	{"PIP_XSTAT10_PRT41"           ,	   0x11800a0001710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	854},
+	{"PIP_XSTAT10_PRT44"           ,	   0x11800a0001740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	854},
+	{"PIP_XSTAT10_PRT45"           ,	   0x11800a0001750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	854},
+	{"PIP_XSTAT10_PRT46"           ,	   0x11800a0001760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	854},
+	{"PIP_XSTAT10_PRT47"           ,	   0x11800a0001770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	854},
+	{"PIP_XSTAT11_PRT40"           ,	   0x11800a0001708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	855},
+	{"PIP_XSTAT11_PRT41"           ,	   0x11800a0001718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	855},
+	{"PIP_XSTAT11_PRT44"           ,	   0x11800a0001748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	855},
+	{"PIP_XSTAT11_PRT45"           ,	   0x11800a0001758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	855},
+	{"PIP_XSTAT11_PRT46"           ,	   0x11800a0001768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	855},
+	{"PIP_XSTAT11_PRT47"           ,	   0x11800a0001778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	855},
+	{"PIP_XSTAT1_PRT40"            ,	   0x11800a0002008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	856},
+	{"PIP_XSTAT1_PRT41"            ,	   0x11800a0002058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	856},
+	{"PIP_XSTAT1_PRT44"            ,	   0x11800a0002148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	856},
+	{"PIP_XSTAT1_PRT45"            ,	   0x11800a0002198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	856},
+	{"PIP_XSTAT1_PRT46"            ,	   0x11800a00021e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	856},
+	{"PIP_XSTAT1_PRT47"            ,	   0x11800a0002238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	856},
+	{"PIP_XSTAT2_PRT40"            ,	   0x11800a0002010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	857},
+	{"PIP_XSTAT2_PRT41"            ,	   0x11800a0002060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	857},
+	{"PIP_XSTAT2_PRT44"            ,	   0x11800a0002150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	857},
+	{"PIP_XSTAT2_PRT45"            ,	   0x11800a00021a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	857},
+	{"PIP_XSTAT2_PRT46"            ,	   0x11800a00021f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	857},
+	{"PIP_XSTAT2_PRT47"            ,	   0x11800a0002240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	857},
+	{"PIP_XSTAT3_PRT40"            ,	   0x11800a0002018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	858},
+	{"PIP_XSTAT3_PRT41"            ,	   0x11800a0002068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	858},
+	{"PIP_XSTAT3_PRT44"            ,	   0x11800a0002158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	858},
+	{"PIP_XSTAT3_PRT45"            ,	   0x11800a00021a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	858},
+	{"PIP_XSTAT3_PRT46"            ,	   0x11800a00021f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	858},
+	{"PIP_XSTAT3_PRT47"            ,	   0x11800a0002248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	858},
+	{"PIP_XSTAT4_PRT40"            ,	   0x11800a0002020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	859},
+	{"PIP_XSTAT4_PRT41"            ,	   0x11800a0002070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	859},
+	{"PIP_XSTAT4_PRT44"            ,	   0x11800a0002160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	859},
+	{"PIP_XSTAT4_PRT45"            ,	   0x11800a00021b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	859},
+	{"PIP_XSTAT4_PRT46"            ,	   0x11800a0002200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	859},
+	{"PIP_XSTAT4_PRT47"            ,	   0x11800a0002250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	859},
+	{"PIP_XSTAT5_PRT40"            ,	   0x11800a0002028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	860},
+	{"PIP_XSTAT5_PRT41"            ,	   0x11800a0002078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	860},
+	{"PIP_XSTAT5_PRT44"            ,	   0x11800a0002168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	860},
+	{"PIP_XSTAT5_PRT45"            ,	   0x11800a00021b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	860},
+	{"PIP_XSTAT5_PRT46"            ,	   0x11800a0002208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	860},
+	{"PIP_XSTAT5_PRT47"            ,	   0x11800a0002258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	860},
+	{"PIP_XSTAT6_PRT40"            ,	   0x11800a0002030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	861},
+	{"PIP_XSTAT6_PRT41"            ,	   0x11800a0002080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	861},
+	{"PIP_XSTAT6_PRT44"            ,	   0x11800a0002170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	861},
+	{"PIP_XSTAT6_PRT45"            ,	   0x11800a00021c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	861},
+	{"PIP_XSTAT6_PRT46"            ,	   0x11800a0002210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	861},
+	{"PIP_XSTAT6_PRT47"            ,	   0x11800a0002260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	861},
+	{"PIP_XSTAT7_PRT40"            ,	   0x11800a0002038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	862},
+	{"PIP_XSTAT7_PRT41"            ,	   0x11800a0002088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	862},
+	{"PIP_XSTAT7_PRT44"            ,	   0x11800a0002178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	862},
+	{"PIP_XSTAT7_PRT45"            ,	   0x11800a00021c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	862},
+	{"PIP_XSTAT7_PRT46"            ,	   0x11800a0002218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	862},
+	{"PIP_XSTAT7_PRT47"            ,	   0x11800a0002268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	862},
+	{"PIP_XSTAT8_PRT40"            ,	   0x11800a0002040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	863},
+	{"PIP_XSTAT8_PRT41"            ,	   0x11800a0002090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	863},
+	{"PIP_XSTAT8_PRT44"            ,	   0x11800a0002180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	863},
+	{"PIP_XSTAT8_PRT45"            ,	   0x11800a00021d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	863},
+	{"PIP_XSTAT8_PRT46"            ,	   0x11800a0002220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	863},
+	{"PIP_XSTAT8_PRT47"            ,	   0x11800a0002270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	863},
+	{"PIP_XSTAT9_PRT40"            ,	   0x11800a0002048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	864},
+	{"PIP_XSTAT9_PRT41"            ,	   0x11800a0002098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	864},
+	{"PIP_XSTAT9_PRT44"            ,	   0x11800a0002188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	864},
+	{"PIP_XSTAT9_PRT45"            ,	   0x11800a00021d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	864},
+	{"PIP_XSTAT9_PRT46"            ,	   0x11800a0002228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	864},
+	{"PIP_XSTAT9_PRT47"            ,	   0x11800a0002278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	864},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	865},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	866},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	867},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	868},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	869},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	870},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	871},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PKO_MEM_DEBUG14"             ,	   0x1180050001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	873},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	874},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	875},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	876},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	877},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	878},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
+	{"PKO_MEM_PORT_PTRS"           ,	   0x1180050001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
+	{"PKO_MEM_PORT_QOS"            ,	   0x1180050001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
+	{"PKO_MEM_PORT_RATE0"          ,	   0x1180050001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
+	{"PKO_MEM_PORT_RATE1"          ,	   0x1180050001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
+	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	886},
+	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	887},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	888},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	889},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	890},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	891},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	892},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	893},
+	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	894},
+	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	895},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	896},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	898},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	899},
+	{"PKO_REG_PREEMPT"             ,	   0x1180050000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	900},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	901},
+	{"PKO_REG_QUEUE_PREEMPT"       ,	   0x1180050000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	902},
+	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	903},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	904},
+	{"PKO_REG_TIMESTAMP"           ,	   0x1180050000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	905},
+	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	906},
+	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	907},
+	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	908},
+	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	909},
+	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	910},
+	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	910},
+	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	910},
+	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	910},
+	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	910},
+	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	910},
+	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	910},
+	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	910},
+	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	911},
+	{"POW_IQ_INT"                  ,	   0x1670000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	912},
+	{"POW_IQ_INT_EN"               ,	   0x1670000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	913},
+	{"POW_IQ_THR0"                 ,	   0x16700000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	914},
+	{"POW_IQ_THR1"                 ,	   0x16700000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	914},
+	{"POW_IQ_THR2"                 ,	   0x16700000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	914},
+	{"POW_IQ_THR3"                 ,	   0x16700000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	914},
+	{"POW_IQ_THR4"                 ,	   0x16700000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	914},
+	{"POW_IQ_THR5"                 ,	   0x16700000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	914},
+	{"POW_IQ_THR6"                 ,	   0x16700000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	914},
+	{"POW_IQ_THR7"                 ,	   0x16700000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	914},
+	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	915},
+	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	916},
+	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	917},
+	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	918},
+	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	918},
+	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	918},
+	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	918},
+	{"POW_PP_GRP_MSK4"             ,	   0x1670000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	918},
+	{"POW_PP_GRP_MSK5"             ,	   0x1670000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	918},
+	{"POW_PP_GRP_MSK6"             ,	   0x1670000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	918},
+	{"POW_PP_GRP_MSK7"             ,	   0x1670000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	918},
+	{"POW_PP_GRP_MSK8"             ,	   0x1670000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	918},
+	{"POW_PP_GRP_MSK9"             ,	   0x1670000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	918},
+	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	919},
+	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	920},
+	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	921},
+	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	922},
+	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	923},
+	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	923},
+	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	923},
+	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	923},
+	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	923},
+	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	923},
+	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	923},
+	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	923},
+	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	924},
+	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	925},
+	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	925},
+	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	925},
+	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	925},
+	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	925},
+	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	925},
+	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	925},
+	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	925},
+	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	925},
+	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	925},
+	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	925},
+	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	925},
+	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	925},
+	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	925},
+	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	925},
+	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	925},
+	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	926},
+	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	927},
+	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	927},
+	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	927},
+	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	927},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	927},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	927},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	927},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	927},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	927},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	927},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	927},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	927},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	927},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	927},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	927},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	927},
+	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	928},
+	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	928},
+	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	928},
+	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	928},
+	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	928},
+	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	928},
+	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	928},
+	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	928},
+	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	928},
+	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	928},
+	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	928},
+	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	928},
+	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	928},
+	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	928},
+	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	928},
+	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	928},
+	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	929},
+	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	930},
+	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	931},
+	{"RAD_REG_BIST_RESULT"         ,	   0x1180070000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	932},
+	{"RAD_REG_CMD_BUF"             ,	   0x1180070000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"RAD_REG_CTL"                 ,	   0x1180070000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	934},
+	{"RAD_REG_DEBUG0"              ,	   0x1180070000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	935},
+	{"RAD_REG_DEBUG1"              ,	   0x1180070000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	936},
+	{"RAD_REG_DEBUG10"             ,	   0x1180070000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	937},
+	{"RAD_REG_DEBUG11"             ,	   0x1180070000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	938},
+	{"RAD_REG_DEBUG12"             ,	   0x1180070000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"RAD_REG_DEBUG2"              ,	   0x1180070000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"RAD_REG_DEBUG3"              ,	   0x1180070000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"RAD_REG_DEBUG4"              ,	   0x1180070000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"RAD_REG_DEBUG5"              ,	   0x1180070000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"RAD_REG_DEBUG6"              ,	   0x1180070000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"RAD_REG_DEBUG7"              ,	   0x1180070000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"RAD_REG_DEBUG8"              ,	   0x1180070000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"RAD_REG_DEBUG9"              ,	   0x1180070000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"RAD_REG_ERROR"               ,	   0x1180070000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"RAD_REG_INT_MASK"            ,	   0x1180070000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"RAD_REG_POLYNOMIAL"          ,	   0x1180070000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"RAD_REG_READ_IDX"            ,	   0x1180070000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"RNM_EER_DBG"                 ,	   0x1180040000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"RNM_EER_KEY"                 ,	   0x1180040000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"RNM_SERIAL_NUM"              ,	   0x1180040000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"SLI_BIST_STATUS"             ,	   0x11f0000010580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	957},
+	{"SLI_CTL_PORT0"               ,	   0x11f0000010050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	958},
+	{"SLI_CTL_PORT1"               ,	   0x11f0000010060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	958},
+	{"SLI_CTL_PORT2"               ,	   0x11f0000010070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	958},
+	{"SLI_CTL_PORT3"               ,	   0x11f0000010080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	958},
+	{"SLI_CTL_STATUS"              ,	   0x11f0000010570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	959},
+	{"SLI_DATA_OUT_CNT"            ,	   0x11f00000105f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_DBG_DATA"                ,	   0x11f0000010310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	961},
+	{"SLI_DBG_SELECT"              ,	   0x11f0000010300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	962},
+	{"SLI_DMA0_CNT"                ,	   0x11f0000010400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	963},
+	{"SLI_DMA1_CNT"                ,	   0x11f0000010410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	963},
+	{"SLI_DMA0_INT_LEVEL"          ,	   0x11f00000103e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	964},
+	{"SLI_DMA1_INT_LEVEL"          ,	   0x11f00000103f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	964},
+	{"SLI_DMA0_TIM"                ,	   0x11f0000010420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	965},
+	{"SLI_DMA1_TIM"                ,	   0x11f0000010430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	965},
+	{"SLI_INT_ENB_CIU"             ,	   0x11f0000013cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	966},
+	{"SLI_INT_ENB_PORT0"           ,	   0x11f0000010340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	967},
+	{"SLI_INT_ENB_PORT1"           ,	   0x11f0000010350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	967},
+	{"SLI_INT_SUM"                 ,	   0x11f0000010330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	968},
+	{"SLI_LAST_WIN_RDATA0"         ,	   0x11f0000010600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_LAST_WIN_RDATA1"         ,	   0x11f0000010610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	970},
+	{"SLI_LAST_WIN_RDATA2"         ,	   0x11f00000106c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	971},
+	{"SLI_LAST_WIN_RDATA3"         ,	   0x11f00000106d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	972},
+	{"SLI_MAC_CREDIT_CNT"          ,	   0x11f0000013d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	973},
+	{"SLI_MAC_CREDIT_CNT2"         ,	   0x11f0000013e10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	974},
+	{"SLI_MAC_NUMBER"              ,	            0x3e00ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	975},
+	{"SLI_MEM_ACCESS_CTL"          ,	   0x11f00000102f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	976},
+	{"SLI_MEM_ACCESS_SUBID12"      ,	   0x11f00000100e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_MEM_ACCESS_SUBID13"      ,	   0x11f00000100f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_MEM_ACCESS_SUBID14"      ,	   0x11f0000010100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_MEM_ACCESS_SUBID15"      ,	   0x11f0000010110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_MEM_ACCESS_SUBID16"      ,	   0x11f0000010120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_MEM_ACCESS_SUBID17"      ,	   0x11f0000010130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_MEM_ACCESS_SUBID18"      ,	   0x11f0000010140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_MEM_ACCESS_SUBID19"      ,	   0x11f0000010150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_MEM_ACCESS_SUBID20"      ,	   0x11f0000010160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_MEM_ACCESS_SUBID21"      ,	   0x11f0000010170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_MEM_ACCESS_SUBID22"      ,	   0x11f0000010180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_MEM_ACCESS_SUBID23"      ,	   0x11f0000010190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_MEM_ACCESS_SUBID24"      ,	   0x11f00000101a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_MEM_ACCESS_SUBID25"      ,	   0x11f00000101b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_MEM_ACCESS_SUBID26"      ,	   0x11f00000101c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_MEM_ACCESS_SUBID27"      ,	   0x11f00000101d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_MSI_ENB0"                ,	   0x11f0000013c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	978},
+	{"SLI_MSI_ENB1"                ,	   0x11f0000013c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	979},
+	{"SLI_MSI_ENB2"                ,	   0x11f0000013c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	980},
+	{"SLI_MSI_ENB3"                ,	   0x11f0000013c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	981},
+	{"SLI_MSI_RCV0"                ,	   0x11f0000013c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	982},
+	{"SLI_MSI_RCV1"                ,	   0x11f0000013c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	983},
+	{"SLI_MSI_RCV2"                ,	   0x11f0000013c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	984},
+	{"SLI_MSI_RCV3"                ,	   0x11f0000013c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	985},
+	{"SLI_MSI_RD_MAP"              ,	   0x11f0000013ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	986},
+	{"SLI_MSI_W1C_ENB0"            ,	   0x11f0000013cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	987},
+	{"SLI_MSI_W1C_ENB1"            ,	   0x11f0000013d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	988},
+	{"SLI_MSI_W1C_ENB2"            ,	   0x11f0000013d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	989},
+	{"SLI_MSI_W1C_ENB3"            ,	   0x11f0000013d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	990},
+	{"SLI_MSI_W1S_ENB0"            ,	   0x11f0000013d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	991},
+	{"SLI_MSI_W1S_ENB1"            ,	   0x11f0000013d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	992},
+	{"SLI_MSI_W1S_ENB2"            ,	   0x11f0000013d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	993},
+	{"SLI_MSI_W1S_ENB3"            ,	   0x11f0000013d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	994},
+	{"SLI_MSI_WR_MAP"              ,	   0x11f0000013c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	995},
+	{"SLI_PCIE_MSI_RCV"            ,	   0x11f0000013cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	996},
+	{"SLI_PCIE_MSI_RCV_B1"         ,	   0x11f0000010650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	997},
+	{"SLI_PCIE_MSI_RCV_B2"         ,	   0x11f0000010660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	998},
+	{"SLI_PCIE_MSI_RCV_B3"         ,	   0x11f0000010670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	999},
+	{"SLI_PKT0_CNTS"               ,	   0x11f0000012400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT1_CNTS"               ,	   0x11f0000012410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT2_CNTS"               ,	   0x11f0000012420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT3_CNTS"               ,	   0x11f0000012430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT4_CNTS"               ,	   0x11f0000012440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT5_CNTS"               ,	   0x11f0000012450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT6_CNTS"               ,	   0x11f0000012460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT7_CNTS"               ,	   0x11f0000012470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT8_CNTS"               ,	   0x11f0000012480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT9_CNTS"               ,	   0x11f0000012490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT10_CNTS"              ,	   0x11f00000124a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT11_CNTS"              ,	   0x11f00000124b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT12_CNTS"              ,	   0x11f00000124c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT13_CNTS"              ,	   0x11f00000124d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT14_CNTS"              ,	   0x11f00000124e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT15_CNTS"              ,	   0x11f00000124f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT16_CNTS"              ,	   0x11f0000012500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT17_CNTS"              ,	   0x11f0000012510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT18_CNTS"              ,	   0x11f0000012520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT19_CNTS"              ,	   0x11f0000012530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT20_CNTS"              ,	   0x11f0000012540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT21_CNTS"              ,	   0x11f0000012550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT22_CNTS"              ,	   0x11f0000012560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT23_CNTS"              ,	   0x11f0000012570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT24_CNTS"              ,	   0x11f0000012580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT25_CNTS"              ,	   0x11f0000012590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT26_CNTS"              ,	   0x11f00000125a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT27_CNTS"              ,	   0x11f00000125b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT28_CNTS"              ,	   0x11f00000125c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT29_CNTS"              ,	   0x11f00000125d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT30_CNTS"              ,	   0x11f00000125e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT31_CNTS"              ,	   0x11f00000125f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1000},
+	{"SLI_PKT0_IN_BP"              ,	   0x11f0000013800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT1_IN_BP"              ,	   0x11f0000013810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT2_IN_BP"              ,	   0x11f0000013820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT3_IN_BP"              ,	   0x11f0000013830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT4_IN_BP"              ,	   0x11f0000013840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT5_IN_BP"              ,	   0x11f0000013850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT6_IN_BP"              ,	   0x11f0000013860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT7_IN_BP"              ,	   0x11f0000013870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT8_IN_BP"              ,	   0x11f0000013880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT9_IN_BP"              ,	   0x11f0000013890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT10_IN_BP"             ,	   0x11f00000138a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT11_IN_BP"             ,	   0x11f00000138b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT12_IN_BP"             ,	   0x11f00000138c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT13_IN_BP"             ,	   0x11f00000138d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT14_IN_BP"             ,	   0x11f00000138e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT15_IN_BP"             ,	   0x11f00000138f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT16_IN_BP"             ,	   0x11f0000013900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT17_IN_BP"             ,	   0x11f0000013910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT18_IN_BP"             ,	   0x11f0000013920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT19_IN_BP"             ,	   0x11f0000013930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT20_IN_BP"             ,	   0x11f0000013940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT21_IN_BP"             ,	   0x11f0000013950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT22_IN_BP"             ,	   0x11f0000013960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT23_IN_BP"             ,	   0x11f0000013970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT24_IN_BP"             ,	   0x11f0000013980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT25_IN_BP"             ,	   0x11f0000013990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT26_IN_BP"             ,	   0x11f00000139a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT27_IN_BP"             ,	   0x11f00000139b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT28_IN_BP"             ,	   0x11f00000139c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT29_IN_BP"             ,	   0x11f00000139d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT30_IN_BP"             ,	   0x11f00000139e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT31_IN_BP"             ,	   0x11f00000139f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1001},
+	{"SLI_PKT0_INSTR_BADDR"        ,	   0x11f0000012800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT1_INSTR_BADDR"        ,	   0x11f0000012810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT2_INSTR_BADDR"        ,	   0x11f0000012820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT3_INSTR_BADDR"        ,	   0x11f0000012830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT4_INSTR_BADDR"        ,	   0x11f0000012840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT5_INSTR_BADDR"        ,	   0x11f0000012850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT6_INSTR_BADDR"        ,	   0x11f0000012860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT7_INSTR_BADDR"        ,	   0x11f0000012870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT8_INSTR_BADDR"        ,	   0x11f0000012880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT9_INSTR_BADDR"        ,	   0x11f0000012890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT10_INSTR_BADDR"       ,	   0x11f00000128a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT11_INSTR_BADDR"       ,	   0x11f00000128b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT12_INSTR_BADDR"       ,	   0x11f00000128c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT13_INSTR_BADDR"       ,	   0x11f00000128d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT14_INSTR_BADDR"       ,	   0x11f00000128e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT15_INSTR_BADDR"       ,	   0x11f00000128f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT16_INSTR_BADDR"       ,	   0x11f0000012900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT17_INSTR_BADDR"       ,	   0x11f0000012910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT18_INSTR_BADDR"       ,	   0x11f0000012920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT19_INSTR_BADDR"       ,	   0x11f0000012930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT20_INSTR_BADDR"       ,	   0x11f0000012940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT21_INSTR_BADDR"       ,	   0x11f0000012950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT22_INSTR_BADDR"       ,	   0x11f0000012960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT23_INSTR_BADDR"       ,	   0x11f0000012970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT24_INSTR_BADDR"       ,	   0x11f0000012980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT25_INSTR_BADDR"       ,	   0x11f0000012990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT26_INSTR_BADDR"       ,	   0x11f00000129a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT27_INSTR_BADDR"       ,	   0x11f00000129b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT28_INSTR_BADDR"       ,	   0x11f00000129c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT29_INSTR_BADDR"       ,	   0x11f00000129d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT30_INSTR_BADDR"       ,	   0x11f00000129e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT31_INSTR_BADDR"       ,	   0x11f00000129f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1002},
+	{"SLI_PKT0_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT1_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT2_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT3_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT4_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT5_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT6_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT7_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT8_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT9_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT10_INSTR_BAOFF_DBELL" ,	   0x11f0000012ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT11_INSTR_BAOFF_DBELL" ,	   0x11f0000012cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT12_INSTR_BAOFF_DBELL" ,	   0x11f0000012cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT13_INSTR_BAOFF_DBELL" ,	   0x11f0000012cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT14_INSTR_BAOFF_DBELL" ,	   0x11f0000012ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT15_INSTR_BAOFF_DBELL" ,	   0x11f0000012cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT16_INSTR_BAOFF_DBELL" ,	   0x11f0000012d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT17_INSTR_BAOFF_DBELL" ,	   0x11f0000012d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT18_INSTR_BAOFF_DBELL" ,	   0x11f0000012d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT19_INSTR_BAOFF_DBELL" ,	   0x11f0000012d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT20_INSTR_BAOFF_DBELL" ,	   0x11f0000012d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT21_INSTR_BAOFF_DBELL" ,	   0x11f0000012d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT22_INSTR_BAOFF_DBELL" ,	   0x11f0000012d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT23_INSTR_BAOFF_DBELL" ,	   0x11f0000012d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT24_INSTR_BAOFF_DBELL" ,	   0x11f0000012d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT25_INSTR_BAOFF_DBELL" ,	   0x11f0000012d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT26_INSTR_BAOFF_DBELL" ,	   0x11f0000012da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT27_INSTR_BAOFF_DBELL" ,	   0x11f0000012db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT28_INSTR_BAOFF_DBELL" ,	   0x11f0000012dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT29_INSTR_BAOFF_DBELL" ,	   0x11f0000012dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT30_INSTR_BAOFF_DBELL" ,	   0x11f0000012de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT31_INSTR_BAOFF_DBELL" ,	   0x11f0000012df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1003},
+	{"SLI_PKT0_INSTR_FIFO_RSIZE"   ,	   0x11f0000013000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT1_INSTR_FIFO_RSIZE"   ,	   0x11f0000013010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT2_INSTR_FIFO_RSIZE"   ,	   0x11f0000013020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT3_INSTR_FIFO_RSIZE"   ,	   0x11f0000013030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT4_INSTR_FIFO_RSIZE"   ,	   0x11f0000013040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT5_INSTR_FIFO_RSIZE"   ,	   0x11f0000013050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT6_INSTR_FIFO_RSIZE"   ,	   0x11f0000013060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT7_INSTR_FIFO_RSIZE"   ,	   0x11f0000013070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT8_INSTR_FIFO_RSIZE"   ,	   0x11f0000013080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT9_INSTR_FIFO_RSIZE"   ,	   0x11f0000013090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT10_INSTR_FIFO_RSIZE"  ,	   0x11f00000130a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT11_INSTR_FIFO_RSIZE"  ,	   0x11f00000130b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT12_INSTR_FIFO_RSIZE"  ,	   0x11f00000130c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT13_INSTR_FIFO_RSIZE"  ,	   0x11f00000130d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT14_INSTR_FIFO_RSIZE"  ,	   0x11f00000130e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT15_INSTR_FIFO_RSIZE"  ,	   0x11f00000130f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT16_INSTR_FIFO_RSIZE"  ,	   0x11f0000013100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT17_INSTR_FIFO_RSIZE"  ,	   0x11f0000013110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT18_INSTR_FIFO_RSIZE"  ,	   0x11f0000013120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT19_INSTR_FIFO_RSIZE"  ,	   0x11f0000013130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT20_INSTR_FIFO_RSIZE"  ,	   0x11f0000013140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT21_INSTR_FIFO_RSIZE"  ,	   0x11f0000013150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT22_INSTR_FIFO_RSIZE"  ,	   0x11f0000013160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT23_INSTR_FIFO_RSIZE"  ,	   0x11f0000013170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT24_INSTR_FIFO_RSIZE"  ,	   0x11f0000013180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT25_INSTR_FIFO_RSIZE"  ,	   0x11f0000013190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT26_INSTR_FIFO_RSIZE"  ,	   0x11f00000131a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT27_INSTR_FIFO_RSIZE"  ,	   0x11f00000131b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT28_INSTR_FIFO_RSIZE"  ,	   0x11f00000131c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT29_INSTR_FIFO_RSIZE"  ,	   0x11f00000131d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT30_INSTR_FIFO_RSIZE"  ,	   0x11f00000131e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT31_INSTR_FIFO_RSIZE"  ,	   0x11f00000131f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1004},
+	{"SLI_PKT0_INSTR_HEADER"       ,	   0x11f0000013400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT1_INSTR_HEADER"       ,	   0x11f0000013410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT2_INSTR_HEADER"       ,	   0x11f0000013420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT3_INSTR_HEADER"       ,	   0x11f0000013430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT4_INSTR_HEADER"       ,	   0x11f0000013440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT5_INSTR_HEADER"       ,	   0x11f0000013450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT6_INSTR_HEADER"       ,	   0x11f0000013460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT7_INSTR_HEADER"       ,	   0x11f0000013470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT8_INSTR_HEADER"       ,	   0x11f0000013480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT9_INSTR_HEADER"       ,	   0x11f0000013490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT10_INSTR_HEADER"      ,	   0x11f00000134a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT11_INSTR_HEADER"      ,	   0x11f00000134b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT12_INSTR_HEADER"      ,	   0x11f00000134c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT13_INSTR_HEADER"      ,	   0x11f00000134d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT14_INSTR_HEADER"      ,	   0x11f00000134e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT15_INSTR_HEADER"      ,	   0x11f00000134f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT16_INSTR_HEADER"      ,	   0x11f0000013500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT17_INSTR_HEADER"      ,	   0x11f0000013510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT18_INSTR_HEADER"      ,	   0x11f0000013520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT19_INSTR_HEADER"      ,	   0x11f0000013530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT20_INSTR_HEADER"      ,	   0x11f0000013540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT21_INSTR_HEADER"      ,	   0x11f0000013550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT22_INSTR_HEADER"      ,	   0x11f0000013560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT23_INSTR_HEADER"      ,	   0x11f0000013570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT24_INSTR_HEADER"      ,	   0x11f0000013580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT25_INSTR_HEADER"      ,	   0x11f0000013590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT26_INSTR_HEADER"      ,	   0x11f00000135a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT27_INSTR_HEADER"      ,	   0x11f00000135b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT28_INSTR_HEADER"      ,	   0x11f00000135c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT29_INSTR_HEADER"      ,	   0x11f00000135d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT30_INSTR_HEADER"      ,	   0x11f00000135e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT31_INSTR_HEADER"      ,	   0x11f00000135f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1005},
+	{"SLI_PKT0_OUT_SIZE"           ,	   0x11f0000010c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT1_OUT_SIZE"           ,	   0x11f0000010c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT2_OUT_SIZE"           ,	   0x11f0000010c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT3_OUT_SIZE"           ,	   0x11f0000010c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT4_OUT_SIZE"           ,	   0x11f0000010c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT5_OUT_SIZE"           ,	   0x11f0000010c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT6_OUT_SIZE"           ,	   0x11f0000010c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT7_OUT_SIZE"           ,	   0x11f0000010c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT8_OUT_SIZE"           ,	   0x11f0000010c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT9_OUT_SIZE"           ,	   0x11f0000010c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT10_OUT_SIZE"          ,	   0x11f0000010ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT11_OUT_SIZE"          ,	   0x11f0000010cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT12_OUT_SIZE"          ,	   0x11f0000010cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT13_OUT_SIZE"          ,	   0x11f0000010cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT14_OUT_SIZE"          ,	   0x11f0000010ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT15_OUT_SIZE"          ,	   0x11f0000010cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT16_OUT_SIZE"          ,	   0x11f0000010d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT17_OUT_SIZE"          ,	   0x11f0000010d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT18_OUT_SIZE"          ,	   0x11f0000010d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT19_OUT_SIZE"          ,	   0x11f0000010d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT20_OUT_SIZE"          ,	   0x11f0000010d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT21_OUT_SIZE"          ,	   0x11f0000010d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT22_OUT_SIZE"          ,	   0x11f0000010d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT23_OUT_SIZE"          ,	   0x11f0000010d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT24_OUT_SIZE"          ,	   0x11f0000010d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT25_OUT_SIZE"          ,	   0x11f0000010d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT26_OUT_SIZE"          ,	   0x11f0000010da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT27_OUT_SIZE"          ,	   0x11f0000010db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT28_OUT_SIZE"          ,	   0x11f0000010dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT29_OUT_SIZE"          ,	   0x11f0000010dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT30_OUT_SIZE"          ,	   0x11f0000010de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT31_OUT_SIZE"          ,	   0x11f0000010df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1006},
+	{"SLI_PKT0_SLIST_BADDR"        ,	   0x11f0000011400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT1_SLIST_BADDR"        ,	   0x11f0000011410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT2_SLIST_BADDR"        ,	   0x11f0000011420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT3_SLIST_BADDR"        ,	   0x11f0000011430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT4_SLIST_BADDR"        ,	   0x11f0000011440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT5_SLIST_BADDR"        ,	   0x11f0000011450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT6_SLIST_BADDR"        ,	   0x11f0000011460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT7_SLIST_BADDR"        ,	   0x11f0000011470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT8_SLIST_BADDR"        ,	   0x11f0000011480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT9_SLIST_BADDR"        ,	   0x11f0000011490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT10_SLIST_BADDR"       ,	   0x11f00000114a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT11_SLIST_BADDR"       ,	   0x11f00000114b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT12_SLIST_BADDR"       ,	   0x11f00000114c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT13_SLIST_BADDR"       ,	   0x11f00000114d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT14_SLIST_BADDR"       ,	   0x11f00000114e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT15_SLIST_BADDR"       ,	   0x11f00000114f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT16_SLIST_BADDR"       ,	   0x11f0000011500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT17_SLIST_BADDR"       ,	   0x11f0000011510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT18_SLIST_BADDR"       ,	   0x11f0000011520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT19_SLIST_BADDR"       ,	   0x11f0000011530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT20_SLIST_BADDR"       ,	   0x11f0000011540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT21_SLIST_BADDR"       ,	   0x11f0000011550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT22_SLIST_BADDR"       ,	   0x11f0000011560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT23_SLIST_BADDR"       ,	   0x11f0000011570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT24_SLIST_BADDR"       ,	   0x11f0000011580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT25_SLIST_BADDR"       ,	   0x11f0000011590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT26_SLIST_BADDR"       ,	   0x11f00000115a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT27_SLIST_BADDR"       ,	   0x11f00000115b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT28_SLIST_BADDR"       ,	   0x11f00000115c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT29_SLIST_BADDR"       ,	   0x11f00000115d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT30_SLIST_BADDR"       ,	   0x11f00000115e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT31_SLIST_BADDR"       ,	   0x11f00000115f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1007},
+	{"SLI_PKT0_SLIST_BAOFF_DBELL"  ,	   0x11f0000011800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT1_SLIST_BAOFF_DBELL"  ,	   0x11f0000011810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT2_SLIST_BAOFF_DBELL"  ,	   0x11f0000011820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT3_SLIST_BAOFF_DBELL"  ,	   0x11f0000011830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT4_SLIST_BAOFF_DBELL"  ,	   0x11f0000011840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT5_SLIST_BAOFF_DBELL"  ,	   0x11f0000011850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT6_SLIST_BAOFF_DBELL"  ,	   0x11f0000011860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT7_SLIST_BAOFF_DBELL"  ,	   0x11f0000011870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT8_SLIST_BAOFF_DBELL"  ,	   0x11f0000011880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT9_SLIST_BAOFF_DBELL"  ,	   0x11f0000011890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT10_SLIST_BAOFF_DBELL" ,	   0x11f00000118a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT11_SLIST_BAOFF_DBELL" ,	   0x11f00000118b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT12_SLIST_BAOFF_DBELL" ,	   0x11f00000118c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT13_SLIST_BAOFF_DBELL" ,	   0x11f00000118d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT14_SLIST_BAOFF_DBELL" ,	   0x11f00000118e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT15_SLIST_BAOFF_DBELL" ,	   0x11f00000118f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT16_SLIST_BAOFF_DBELL" ,	   0x11f0000011900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT17_SLIST_BAOFF_DBELL" ,	   0x11f0000011910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT18_SLIST_BAOFF_DBELL" ,	   0x11f0000011920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT19_SLIST_BAOFF_DBELL" ,	   0x11f0000011930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT20_SLIST_BAOFF_DBELL" ,	   0x11f0000011940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT21_SLIST_BAOFF_DBELL" ,	   0x11f0000011950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT22_SLIST_BAOFF_DBELL" ,	   0x11f0000011960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT23_SLIST_BAOFF_DBELL" ,	   0x11f0000011970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT24_SLIST_BAOFF_DBELL" ,	   0x11f0000011980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT25_SLIST_BAOFF_DBELL" ,	   0x11f0000011990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT26_SLIST_BAOFF_DBELL" ,	   0x11f00000119a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT27_SLIST_BAOFF_DBELL" ,	   0x11f00000119b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT28_SLIST_BAOFF_DBELL" ,	   0x11f00000119c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT29_SLIST_BAOFF_DBELL" ,	   0x11f00000119d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT30_SLIST_BAOFF_DBELL" ,	   0x11f00000119e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT31_SLIST_BAOFF_DBELL" ,	   0x11f00000119f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1008},
+	{"SLI_PKT0_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT1_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT2_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT3_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT4_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT5_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT6_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT7_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT8_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT9_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT10_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT11_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT12_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT13_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT14_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT15_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT16_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT17_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT18_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT19_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT20_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT21_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT22_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT23_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT24_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT25_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT26_SLIST_FIFO_RSIZE"  ,	   0x11f0000011da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT27_SLIST_FIFO_RSIZE"  ,	   0x11f0000011db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT28_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT29_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT30_SLIST_FIFO_RSIZE"  ,	   0x11f0000011de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT31_SLIST_FIFO_RSIZE"  ,	   0x11f0000011df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1009},
+	{"SLI_PKT_CNT_INT"             ,	   0x11f0000011130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1010},
+	{"SLI_PKT_CNT_INT_ENB"         ,	   0x11f0000011150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1011},
+	{"SLI_PKT_CTL"                 ,	   0x11f0000011220ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1012},
+	{"SLI_PKT_DATA_OUT_ES"         ,	   0x11f00000110b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1013},
+	{"SLI_PKT_DATA_OUT_NS"         ,	   0x11f00000110a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1014},
+	{"SLI_PKT_DATA_OUT_ROR"        ,	   0x11f0000011090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1015},
+	{"SLI_PKT_DPADDR"              ,	   0x11f0000011080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1016},
+	{"SLI_PKT_IN_BP"               ,	   0x11f0000011210ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1017},
+	{"SLI_PKT_IN_DONE0_CNTS"       ,	   0x11f0000012000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE1_CNTS"       ,	   0x11f0000012010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE2_CNTS"       ,	   0x11f0000012020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE3_CNTS"       ,	   0x11f0000012030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE4_CNTS"       ,	   0x11f0000012040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE5_CNTS"       ,	   0x11f0000012050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE6_CNTS"       ,	   0x11f0000012060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE7_CNTS"       ,	   0x11f0000012070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE8_CNTS"       ,	   0x11f0000012080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE9_CNTS"       ,	   0x11f0000012090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE10_CNTS"      ,	   0x11f00000120a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE11_CNTS"      ,	   0x11f00000120b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE12_CNTS"      ,	   0x11f00000120c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE13_CNTS"      ,	   0x11f00000120d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE14_CNTS"      ,	   0x11f00000120e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE15_CNTS"      ,	   0x11f00000120f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE16_CNTS"      ,	   0x11f0000012100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE17_CNTS"      ,	   0x11f0000012110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE18_CNTS"      ,	   0x11f0000012120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE19_CNTS"      ,	   0x11f0000012130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE20_CNTS"      ,	   0x11f0000012140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE21_CNTS"      ,	   0x11f0000012150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE22_CNTS"      ,	   0x11f0000012160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE23_CNTS"      ,	   0x11f0000012170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE24_CNTS"      ,	   0x11f0000012180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE25_CNTS"      ,	   0x11f0000012190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE26_CNTS"      ,	   0x11f00000121a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE27_CNTS"      ,	   0x11f00000121b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE28_CNTS"      ,	   0x11f00000121c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE29_CNTS"      ,	   0x11f00000121d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE30_CNTS"      ,	   0x11f00000121e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_DONE31_CNTS"      ,	   0x11f00000121f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018},
+	{"SLI_PKT_IN_INSTR_COUNTS"     ,	   0x11f0000011200ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1019},
+	{"SLI_PKT_IN_PCIE_PORT"        ,	   0x11f00000111b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1020},
+	{"SLI_PKT_INPUT_CONTROL"       ,	   0x11f0000011170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1021},
+	{"SLI_PKT_INSTR_ENB"           ,	   0x11f0000011000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1022},
+	{"SLI_PKT_INSTR_RD_SIZE"       ,	   0x11f00000111a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1023},
+	{"SLI_PKT_INSTR_SIZE"          ,	   0x11f0000011020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1024},
+	{"SLI_PKT_INT_LEVELS"          ,	   0x11f0000011120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1025},
+	{"SLI_PKT_IPTR"                ,	   0x11f0000011070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1026},
+	{"SLI_PKT_OUT_BMODE"           ,	   0x11f00000110d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1027},
+	{"SLI_PKT_OUT_ENB"             ,	   0x11f0000011010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1028},
+	{"SLI_PKT_OUTPUT_WMARK"        ,	   0x11f0000011180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1029},
+	{"SLI_PKT_PCIE_PORT"           ,	   0x11f00000110e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1030},
+	{"SLI_PKT_PORT_IN_RST"         ,	   0x11f00000111f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1031},
+	{"SLI_PKT_SLIST_ES"            ,	   0x11f0000011050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1032},
+	{"SLI_PKT_SLIST_NS"            ,	   0x11f0000011040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1033},
+	{"SLI_PKT_SLIST_ROR"           ,	   0x11f0000011030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1034},
+	{"SLI_PKT_TIME_INT"            ,	   0x11f0000011140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1035},
+	{"SLI_PKT_TIME_INT_ENB"        ,	   0x11f0000011160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1036},
+	{"SLI_S2M_PORT0_CTL"           ,	   0x11f0000013d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1037},
+	{"SLI_S2M_PORT1_CTL"           ,	   0x11f0000013d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1037},
+	{"SLI_S2M_PORT2_CTL"           ,	   0x11f0000013da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1037},
+	{"SLI_S2M_PORT3_CTL"           ,	   0x11f0000013db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1037},
+	{"SLI_SCRATCH_1"               ,	   0x11f00000103c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1038},
+	{"SLI_SCRATCH_2"               ,	   0x11f00000103d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1039},
+	{"SLI_STATE1"                  ,	   0x11f0000010620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1040},
+	{"SLI_STATE2"                  ,	   0x11f0000010630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1041},
+	{"SLI_STATE3"                  ,	   0x11f0000010640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1042},
+	{"SLI_WIN_RD_ADDR"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1043},
+	{"SLI_WIN_RD_DATA"             ,	              0x40ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1044},
+	{"SLI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1045},
+	{"SLI_WIN_WR_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1046},
+	{"SLI_WIN_WR_MASK"             ,	              0x30ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1047},
+	{"SLI_WINDOW_CTL"              ,	   0x11f00000102e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1048},
+	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1049},
+	{"SMI1_CLK"                    ,	   0x1180000001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1049},
+	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1050},
+	{"SMI1_CMD"                    ,	   0x1180000001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1050},
+	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1051},
+	{"SMI1_EN"                     ,	   0x1180000001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1051},
+	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1052},
+	{"SMI1_RD_DAT"                 ,	   0x1180000001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1052},
+	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1053},
+	{"SMI1_WR_DAT"                 ,	   0x1180000001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1053},
+	{"SMI_DRV_CTL"                 ,	   0x1180000001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1054},
+	{"SRIO0_ACC_CTRL"              ,	   0x11800c8000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1055},
+	{"SRIO2_ACC_CTRL"              ,	   0x11800ca000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1055},
+	{"SRIO3_ACC_CTRL"              ,	   0x11800cb000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1055},
+	{"SRIO0_ASMBLY_ID"             ,	   0x11800c8000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1056},
+	{"SRIO2_ASMBLY_ID"             ,	   0x11800ca000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1056},
+	{"SRIO3_ASMBLY_ID"             ,	   0x11800cb000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1056},
+	{"SRIO0_ASMBLY_INFO"           ,	   0x11800c8000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1057},
+	{"SRIO2_ASMBLY_INFO"           ,	   0x11800ca000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1057},
+	{"SRIO3_ASMBLY_INFO"           ,	   0x11800cb000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1057},
+	{"SRIO0_BELL_RESP_CTRL"        ,	   0x11800c8000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1058},
+	{"SRIO2_BELL_RESP_CTRL"        ,	   0x11800ca000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1058},
+	{"SRIO3_BELL_RESP_CTRL"        ,	   0x11800cb000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1058},
+	{"SRIO0_BIST_STATUS"           ,	   0x11800c8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1059},
+	{"SRIO2_BIST_STATUS"           ,	   0x11800ca000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1059},
+	{"SRIO3_BIST_STATUS"           ,	   0x11800cb000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1059},
+	{"SRIO0_IMSG_CTRL"             ,	   0x11800c8000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1060},
+	{"SRIO2_IMSG_CTRL"             ,	   0x11800ca000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1060},
+	{"SRIO3_IMSG_CTRL"             ,	   0x11800cb000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1060},
+	{"SRIO0_IMSG_INST_HDR000"      ,	   0x11800c8000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1061},
+	{"SRIO0_IMSG_INST_HDR001"      ,	   0x11800c8000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1061},
+	{"SRIO2_IMSG_INST_HDR000"      ,	   0x11800ca000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1061},
+	{"SRIO2_IMSG_INST_HDR001"      ,	   0x11800ca000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1061},
+	{"SRIO3_IMSG_INST_HDR000"      ,	   0x11800cb000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1061},
+	{"SRIO3_IMSG_INST_HDR001"      ,	   0x11800cb000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1061},
+	{"SRIO0_IMSG_QOS_GRP000"       ,	   0x11800c8000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP001"       ,	   0x11800c8000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP002"       ,	   0x11800c8000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP003"       ,	   0x11800c8000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP004"       ,	   0x11800c8000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP005"       ,	   0x11800c8000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP006"       ,	   0x11800c8000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP007"       ,	   0x11800c8000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP008"       ,	   0x11800c8000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP009"       ,	   0x11800c8000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP010"       ,	   0x11800c8000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP011"       ,	   0x11800c8000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP012"       ,	   0x11800c8000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP013"       ,	   0x11800c8000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP014"       ,	   0x11800c8000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP015"       ,	   0x11800c8000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP016"       ,	   0x11800c8000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP017"       ,	   0x11800c8000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP018"       ,	   0x11800c8000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP019"       ,	   0x11800c8000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP020"       ,	   0x11800c80006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP021"       ,	   0x11800c80006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP022"       ,	   0x11800c80006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP023"       ,	   0x11800c80006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP024"       ,	   0x11800c80006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP025"       ,	   0x11800c80006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP026"       ,	   0x11800c80006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP027"       ,	   0x11800c80006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP028"       ,	   0x11800c80006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP029"       ,	   0x11800c80006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP030"       ,	   0x11800c80006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_QOS_GRP031"       ,	   0x11800c80006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP000"       ,	   0x11800ca000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP001"       ,	   0x11800ca000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP002"       ,	   0x11800ca000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP003"       ,	   0x11800ca000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP004"       ,	   0x11800ca000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP005"       ,	   0x11800ca000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP006"       ,	   0x11800ca000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP007"       ,	   0x11800ca000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP008"       ,	   0x11800ca000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP009"       ,	   0x11800ca000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP010"       ,	   0x11800ca000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP011"       ,	   0x11800ca000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP012"       ,	   0x11800ca000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP013"       ,	   0x11800ca000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP014"       ,	   0x11800ca000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP015"       ,	   0x11800ca000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP016"       ,	   0x11800ca000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP017"       ,	   0x11800ca000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP018"       ,	   0x11800ca000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP019"       ,	   0x11800ca000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP020"       ,	   0x11800ca0006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP021"       ,	   0x11800ca0006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP022"       ,	   0x11800ca0006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP023"       ,	   0x11800ca0006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP024"       ,	   0x11800ca0006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP025"       ,	   0x11800ca0006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP026"       ,	   0x11800ca0006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP027"       ,	   0x11800ca0006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP028"       ,	   0x11800ca0006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP029"       ,	   0x11800ca0006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP030"       ,	   0x11800ca0006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO2_IMSG_QOS_GRP031"       ,	   0x11800ca0006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP000"       ,	   0x11800cb000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP001"       ,	   0x11800cb000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP002"       ,	   0x11800cb000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP003"       ,	   0x11800cb000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP004"       ,	   0x11800cb000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP005"       ,	   0x11800cb000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP006"       ,	   0x11800cb000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP007"       ,	   0x11800cb000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP008"       ,	   0x11800cb000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP009"       ,	   0x11800cb000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP010"       ,	   0x11800cb000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP011"       ,	   0x11800cb000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP012"       ,	   0x11800cb000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP013"       ,	   0x11800cb000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP014"       ,	   0x11800cb000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP015"       ,	   0x11800cb000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP016"       ,	   0x11800cb000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP017"       ,	   0x11800cb000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP018"       ,	   0x11800cb000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP019"       ,	   0x11800cb000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP020"       ,	   0x11800cb0006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP021"       ,	   0x11800cb0006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP022"       ,	   0x11800cb0006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP023"       ,	   0x11800cb0006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP024"       ,	   0x11800cb0006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP025"       ,	   0x11800cb0006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP026"       ,	   0x11800cb0006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP027"       ,	   0x11800cb0006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP028"       ,	   0x11800cb0006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP029"       ,	   0x11800cb0006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP030"       ,	   0x11800cb0006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO3_IMSG_QOS_GRP031"       ,	   0x11800cb0006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"SRIO0_IMSG_STATUS000"        ,	   0x11800c8000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS001"        ,	   0x11800c8000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS002"        ,	   0x11800c8000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS003"        ,	   0x11800c8000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS004"        ,	   0x11800c8000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS005"        ,	   0x11800c8000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS006"        ,	   0x11800c8000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS007"        ,	   0x11800c8000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS008"        ,	   0x11800c8000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS009"        ,	   0x11800c8000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS010"        ,	   0x11800c8000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS011"        ,	   0x11800c8000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS012"        ,	   0x11800c8000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS013"        ,	   0x11800c8000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS014"        ,	   0x11800c8000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS015"        ,	   0x11800c8000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS016"        ,	   0x11800c8000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS017"        ,	   0x11800c8000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS018"        ,	   0x11800c8000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS019"        ,	   0x11800c8000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS020"        ,	   0x11800c80007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS021"        ,	   0x11800c80007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS022"        ,	   0x11800c80007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_STATUS023"        ,	   0x11800c80007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS000"        ,	   0x11800ca000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS001"        ,	   0x11800ca000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS002"        ,	   0x11800ca000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS003"        ,	   0x11800ca000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS004"        ,	   0x11800ca000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS005"        ,	   0x11800ca000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS006"        ,	   0x11800ca000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS007"        ,	   0x11800ca000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS008"        ,	   0x11800ca000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS009"        ,	   0x11800ca000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS010"        ,	   0x11800ca000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS011"        ,	   0x11800ca000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS012"        ,	   0x11800ca000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS013"        ,	   0x11800ca000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS014"        ,	   0x11800ca000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS015"        ,	   0x11800ca000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS016"        ,	   0x11800ca000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS017"        ,	   0x11800ca000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS018"        ,	   0x11800ca000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS019"        ,	   0x11800ca000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS020"        ,	   0x11800ca0007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS021"        ,	   0x11800ca0007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS022"        ,	   0x11800ca0007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO2_IMSG_STATUS023"        ,	   0x11800ca0007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS000"        ,	   0x11800cb000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS001"        ,	   0x11800cb000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS002"        ,	   0x11800cb000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS003"        ,	   0x11800cb000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS004"        ,	   0x11800cb000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS005"        ,	   0x11800cb000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS006"        ,	   0x11800cb000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS007"        ,	   0x11800cb000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS008"        ,	   0x11800cb000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS009"        ,	   0x11800cb000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS010"        ,	   0x11800cb000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS011"        ,	   0x11800cb000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS012"        ,	   0x11800cb000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS013"        ,	   0x11800cb000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS014"        ,	   0x11800cb000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS015"        ,	   0x11800cb000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS016"        ,	   0x11800cb000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS017"        ,	   0x11800cb000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS018"        ,	   0x11800cb000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS019"        ,	   0x11800cb000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS020"        ,	   0x11800cb0007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS021"        ,	   0x11800cb0007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS022"        ,	   0x11800cb0007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO3_IMSG_STATUS023"        ,	   0x11800cb0007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"SRIO0_IMSG_VPORT_THR"        ,	   0x11800c8000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1064},
+	{"SRIO2_IMSG_VPORT_THR"        ,	   0x11800ca000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1064},
+	{"SRIO3_IMSG_VPORT_THR"        ,	   0x11800cb000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1064},
+	{"SRIO0_IMSG_VPORT_THR2"       ,	   0x11800c8000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1065},
+	{"SRIO2_IMSG_VPORT_THR2"       ,	   0x11800ca000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1065},
+	{"SRIO3_IMSG_VPORT_THR2"       ,	   0x11800cb000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1065},
+	{"SRIO0_INT2_ENABLE"           ,	   0x11800c80003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1066},
+	{"SRIO2_INT2_ENABLE"           ,	   0x11800ca0003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1066},
+	{"SRIO3_INT2_ENABLE"           ,	   0x11800cb0003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1066},
+	{"SRIO0_INT2_REG"              ,	   0x11800c80003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1067},
+	{"SRIO2_INT2_REG"              ,	   0x11800ca0003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1067},
+	{"SRIO3_INT2_REG"              ,	   0x11800cb0003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1067},
+	{"SRIO0_INT_ENABLE"            ,	   0x11800c8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1068},
+	{"SRIO2_INT_ENABLE"            ,	   0x11800ca000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1068},
+	{"SRIO3_INT_ENABLE"            ,	   0x11800cb000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1068},
+	{"SRIO0_INT_INFO0"             ,	   0x11800c8000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1069},
+	{"SRIO2_INT_INFO0"             ,	   0x11800ca000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1069},
+	{"SRIO3_INT_INFO0"             ,	   0x11800cb000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1069},
+	{"SRIO0_INT_INFO1"             ,	   0x11800c8000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1070},
+	{"SRIO2_INT_INFO1"             ,	   0x11800ca000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1070},
+	{"SRIO3_INT_INFO1"             ,	   0x11800cb000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1070},
+	{"SRIO0_INT_INFO2"             ,	   0x11800c8000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1071},
+	{"SRIO2_INT_INFO2"             ,	   0x11800ca000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1071},
+	{"SRIO3_INT_INFO2"             ,	   0x11800cb000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1071},
+	{"SRIO0_INT_INFO3"             ,	   0x11800c8000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1072},
+	{"SRIO2_INT_INFO3"             ,	   0x11800ca000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1072},
+	{"SRIO3_INT_INFO3"             ,	   0x11800cb000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1072},
+	{"SRIO0_INT_REG"               ,	   0x11800c8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1073},
+	{"SRIO2_INT_REG"               ,	   0x11800ca000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1073},
+	{"SRIO3_INT_REG"               ,	   0x11800cb000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1073},
+	{"SRIO0_IP_FEATURE"            ,	   0x11800c80003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1074},
+	{"SRIO2_IP_FEATURE"            ,	   0x11800ca0003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1074},
+	{"SRIO3_IP_FEATURE"            ,	   0x11800cb0003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1074},
+	{"SRIO0_MAC_BUFFERS"           ,	   0x11800c8000390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1075},
+	{"SRIO2_MAC_BUFFERS"           ,	   0x11800ca000390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1075},
+	{"SRIO3_MAC_BUFFERS"           ,	   0x11800cb000390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1075},
+	{"SRIO0_MAINT_OP"              ,	   0x11800c8000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1076},
+	{"SRIO2_MAINT_OP"              ,	   0x11800ca000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1076},
+	{"SRIO3_MAINT_OP"              ,	   0x11800cb000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1076},
+	{"SRIO0_MAINT_RD_DATA"         ,	   0x11800c8000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1077},
+	{"SRIO2_MAINT_RD_DATA"         ,	   0x11800ca000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1077},
+	{"SRIO3_MAINT_RD_DATA"         ,	   0x11800cb000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1077},
+	{"SRIO0_MCE_TX_CTL"            ,	   0x11800c8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1078},
+	{"SRIO2_MCE_TX_CTL"            ,	   0x11800ca000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1078},
+	{"SRIO3_MCE_TX_CTL"            ,	   0x11800cb000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1078},
+	{"SRIO0_MEM_OP_CTRL"           ,	   0x11800c8000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1079},
+	{"SRIO2_MEM_OP_CTRL"           ,	   0x11800ca000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1079},
+	{"SRIO3_MEM_OP_CTRL"           ,	   0x11800cb000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1079},
+	{"SRIO0_OMSG_CTRL000"          ,	   0x11800c8000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1080},
+	{"SRIO0_OMSG_CTRL001"          ,	   0x11800c80004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1080},
+	{"SRIO2_OMSG_CTRL000"          ,	   0x11800ca000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1080},
+	{"SRIO2_OMSG_CTRL001"          ,	   0x11800ca0004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1080},
+	{"SRIO3_OMSG_CTRL000"          ,	   0x11800cb000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1080},
+	{"SRIO3_OMSG_CTRL001"          ,	   0x11800cb0004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1080},
+	{"SRIO0_OMSG_DONE_COUNTS000"   ,	   0x11800c80004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1081},
+	{"SRIO0_OMSG_DONE_COUNTS001"   ,	   0x11800c80004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1081},
+	{"SRIO2_OMSG_DONE_COUNTS000"   ,	   0x11800ca0004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1081},
+	{"SRIO2_OMSG_DONE_COUNTS001"   ,	   0x11800ca0004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1081},
+	{"SRIO3_OMSG_DONE_COUNTS000"   ,	   0x11800cb0004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1081},
+	{"SRIO3_OMSG_DONE_COUNTS001"   ,	   0x11800cb0004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1081},
+	{"SRIO0_OMSG_FMP_MR000"        ,	   0x11800c8000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1082},
+	{"SRIO0_OMSG_FMP_MR001"        ,	   0x11800c80004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1082},
+	{"SRIO2_OMSG_FMP_MR000"        ,	   0x11800ca000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1082},
+	{"SRIO2_OMSG_FMP_MR001"        ,	   0x11800ca0004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1082},
+	{"SRIO3_OMSG_FMP_MR000"        ,	   0x11800cb000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1082},
+	{"SRIO3_OMSG_FMP_MR001"        ,	   0x11800cb0004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1082},
+	{"SRIO0_OMSG_NMP_MR000"        ,	   0x11800c80004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1083},
+	{"SRIO0_OMSG_NMP_MR001"        ,	   0x11800c80004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1083},
+	{"SRIO2_OMSG_NMP_MR000"        ,	   0x11800ca0004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1083},
+	{"SRIO2_OMSG_NMP_MR001"        ,	   0x11800ca0004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1083},
+	{"SRIO3_OMSG_NMP_MR000"        ,	   0x11800cb0004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1083},
+	{"SRIO3_OMSG_NMP_MR001"        ,	   0x11800cb0004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1083},
+	{"SRIO0_OMSG_PORT000"          ,	   0x11800c8000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1084},
+	{"SRIO0_OMSG_PORT001"          ,	   0x11800c80004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1084},
+	{"SRIO2_OMSG_PORT000"          ,	   0x11800ca000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1084},
+	{"SRIO2_OMSG_PORT001"          ,	   0x11800ca0004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1084},
+	{"SRIO3_OMSG_PORT000"          ,	   0x11800cb000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1084},
+	{"SRIO3_OMSG_PORT001"          ,	   0x11800cb0004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1084},
+	{"SRIO0_OMSG_SILO_THR"         ,	   0x11800c80004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1085},
+	{"SRIO2_OMSG_SILO_THR"         ,	   0x11800ca0004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1085},
+	{"SRIO3_OMSG_SILO_THR"         ,	   0x11800cb0004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1085},
+	{"SRIO0_OMSG_SP_MR000"         ,	   0x11800c8000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1086},
+	{"SRIO0_OMSG_SP_MR001"         ,	   0x11800c80004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1086},
+	{"SRIO2_OMSG_SP_MR000"         ,	   0x11800ca000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1086},
+	{"SRIO2_OMSG_SP_MR001"         ,	   0x11800ca0004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1086},
+	{"SRIO3_OMSG_SP_MR000"         ,	   0x11800cb000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1086},
+	{"SRIO3_OMSG_SP_MR001"         ,	   0x11800cb0004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1086},
+	{"SRIO0_PRIO000_IN_USE"        ,	   0x11800c80003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1087},
+	{"SRIO0_PRIO001_IN_USE"        ,	   0x11800c80003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1087},
+	{"SRIO0_PRIO002_IN_USE"        ,	   0x11800c80003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1087},
+	{"SRIO0_PRIO003_IN_USE"        ,	   0x11800c80003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1087},
+	{"SRIO2_PRIO000_IN_USE"        ,	   0x11800ca0003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1087},
+	{"SRIO2_PRIO001_IN_USE"        ,	   0x11800ca0003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1087},
+	{"SRIO2_PRIO002_IN_USE"        ,	   0x11800ca0003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1087},
+	{"SRIO2_PRIO003_IN_USE"        ,	   0x11800ca0003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1087},
+	{"SRIO3_PRIO000_IN_USE"        ,	   0x11800cb0003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1087},
+	{"SRIO3_PRIO001_IN_USE"        ,	   0x11800cb0003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1087},
+	{"SRIO3_PRIO002_IN_USE"        ,	   0x11800cb0003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1087},
+	{"SRIO3_PRIO003_IN_USE"        ,	   0x11800cb0003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1087},
+	{"SRIO0_RX_BELL"               ,	   0x11800c8000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1088},
+	{"SRIO2_RX_BELL"               ,	   0x11800ca000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1088},
+	{"SRIO3_RX_BELL"               ,	   0x11800cb000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1088},
+	{"SRIO0_RX_BELL_SEQ"           ,	   0x11800c8000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1089},
+	{"SRIO2_RX_BELL_SEQ"           ,	   0x11800ca000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1089},
+	{"SRIO3_RX_BELL_SEQ"           ,	   0x11800cb000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1089},
+	{"SRIO0_RX_STATUS"             ,	   0x11800c8000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1090},
+	{"SRIO2_RX_STATUS"             ,	   0x11800ca000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1090},
+	{"SRIO3_RX_STATUS"             ,	   0x11800cb000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1090},
+	{"SRIO0_S2M_TYPE000"           ,	   0x11800c8000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO0_S2M_TYPE001"           ,	   0x11800c8000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO0_S2M_TYPE002"           ,	   0x11800c8000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO0_S2M_TYPE003"           ,	   0x11800c8000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO0_S2M_TYPE004"           ,	   0x11800c80001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO0_S2M_TYPE005"           ,	   0x11800c80001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO0_S2M_TYPE006"           ,	   0x11800c80001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO0_S2M_TYPE007"           ,	   0x11800c80001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO0_S2M_TYPE008"           ,	   0x11800c80001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO0_S2M_TYPE009"           ,	   0x11800c80001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO0_S2M_TYPE010"           ,	   0x11800c80001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO0_S2M_TYPE011"           ,	   0x11800c80001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO0_S2M_TYPE012"           ,	   0x11800c80001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO0_S2M_TYPE013"           ,	   0x11800c80001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO0_S2M_TYPE014"           ,	   0x11800c80001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO0_S2M_TYPE015"           ,	   0x11800c80001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO2_S2M_TYPE000"           ,	   0x11800ca000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO2_S2M_TYPE001"           ,	   0x11800ca000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO2_S2M_TYPE002"           ,	   0x11800ca000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO2_S2M_TYPE003"           ,	   0x11800ca000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO2_S2M_TYPE004"           ,	   0x11800ca0001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO2_S2M_TYPE005"           ,	   0x11800ca0001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO2_S2M_TYPE006"           ,	   0x11800ca0001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO2_S2M_TYPE007"           ,	   0x11800ca0001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO2_S2M_TYPE008"           ,	   0x11800ca0001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO2_S2M_TYPE009"           ,	   0x11800ca0001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO2_S2M_TYPE010"           ,	   0x11800ca0001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO2_S2M_TYPE011"           ,	   0x11800ca0001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO2_S2M_TYPE012"           ,	   0x11800ca0001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO2_S2M_TYPE013"           ,	   0x11800ca0001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO2_S2M_TYPE014"           ,	   0x11800ca0001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO2_S2M_TYPE015"           ,	   0x11800ca0001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO3_S2M_TYPE000"           ,	   0x11800cb000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO3_S2M_TYPE001"           ,	   0x11800cb000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO3_S2M_TYPE002"           ,	   0x11800cb000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO3_S2M_TYPE003"           ,	   0x11800cb000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO3_S2M_TYPE004"           ,	   0x11800cb0001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO3_S2M_TYPE005"           ,	   0x11800cb0001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO3_S2M_TYPE006"           ,	   0x11800cb0001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO3_S2M_TYPE007"           ,	   0x11800cb0001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO3_S2M_TYPE008"           ,	   0x11800cb0001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO3_S2M_TYPE009"           ,	   0x11800cb0001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO3_S2M_TYPE010"           ,	   0x11800cb0001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO3_S2M_TYPE011"           ,	   0x11800cb0001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO3_S2M_TYPE012"           ,	   0x11800cb0001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO3_S2M_TYPE013"           ,	   0x11800cb0001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO3_S2M_TYPE014"           ,	   0x11800cb0001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO3_S2M_TYPE015"           ,	   0x11800cb0001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"SRIO0_SEQ"                   ,	   0x11800c8000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1092},
+	{"SRIO2_SEQ"                   ,	   0x11800ca000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1092},
+	{"SRIO3_SEQ"                   ,	   0x11800cb000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1092},
+	{"SRIO0_STATUS_REG"            ,	   0x11800c8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1093},
+	{"SRIO2_STATUS_REG"            ,	   0x11800ca000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1093},
+	{"SRIO3_STATUS_REG"            ,	   0x11800cb000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1093},
+	{"SRIO0_TAG_CTRL"              ,	   0x11800c8000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1094},
+	{"SRIO2_TAG_CTRL"              ,	   0x11800ca000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1094},
+	{"SRIO3_TAG_CTRL"              ,	   0x11800cb000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1094},
+	{"SRIO0_TLP_CREDITS"           ,	   0x11800c8000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1095},
+	{"SRIO2_TLP_CREDITS"           ,	   0x11800ca000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1095},
+	{"SRIO3_TLP_CREDITS"           ,	   0x11800cb000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1095},
+	{"SRIO0_TX_BELL"               ,	   0x11800c8000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1096},
+	{"SRIO2_TX_BELL"               ,	   0x11800ca000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1096},
+	{"SRIO3_TX_BELL"               ,	   0x11800cb000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1096},
+	{"SRIO0_TX_BELL_INFO"          ,	   0x11800c8000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1097},
+	{"SRIO2_TX_BELL_INFO"          ,	   0x11800ca000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1097},
+	{"SRIO3_TX_BELL_INFO"          ,	   0x11800cb000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1097},
+	{"SRIO0_TX_CTRL"               ,	   0x11800c8000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1098},
+	{"SRIO2_TX_CTRL"               ,	   0x11800ca000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1098},
+	{"SRIO3_TX_CTRL"               ,	   0x11800cb000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1098},
+	{"SRIO0_TX_EMPHASIS"           ,	   0x11800c80003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1099},
+	{"SRIO2_TX_EMPHASIS"           ,	   0x11800ca0003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1099},
+	{"SRIO3_TX_EMPHASIS"           ,	   0x11800cb0003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1099},
+	{"SRIO0_TX_STATUS"             ,	   0x11800c8000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1100},
+	{"SRIO2_TX_STATUS"             ,	   0x11800ca000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1100},
+	{"SRIO3_TX_STATUS"             ,	   0x11800cb000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1100},
+	{"SRIO0_WR_DONE_COUNTS"        ,	   0x11800c8000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1101},
+	{"SRIO2_WR_DONE_COUNTS"        ,	   0x11800ca000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1101},
+	{"SRIO3_WR_DONE_COUNTS"        ,	   0x11800cb000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1101},
+	{"SRIOMAINT0_ASMBLY_ID"        ,	               0x8ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1102},
+	{"SRIOMAINT2_ASMBLY_ID"        ,	               0x8ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1102},
+	{"SRIOMAINT3_ASMBLY_ID"        ,	               0x8ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1102},
+	{"SRIOMAINT0_ASMBLY_INFO"      ,	               0xcull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1103},
+	{"SRIOMAINT2_ASMBLY_INFO"      ,	               0xcull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1103},
+	{"SRIOMAINT3_ASMBLY_INFO"      ,	               0xcull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1103},
+	{"SRIOMAINT0_BAR1_IDX000"      ,	          0x200010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT0_BAR1_IDX001"      ,	          0x200014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT0_BAR1_IDX002"      ,	          0x200018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT0_BAR1_IDX003"      ,	          0x20001cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT0_BAR1_IDX004"      ,	          0x200020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT0_BAR1_IDX005"      ,	          0x200024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT0_BAR1_IDX006"      ,	          0x200028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT0_BAR1_IDX007"      ,	          0x20002cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT0_BAR1_IDX008"      ,	          0x200030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT0_BAR1_IDX009"      ,	          0x200034ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT0_BAR1_IDX010"      ,	          0x200038ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT0_BAR1_IDX011"      ,	          0x20003cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT0_BAR1_IDX012"      ,	          0x200040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT0_BAR1_IDX013"      ,	          0x200044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT0_BAR1_IDX014"      ,	          0x200048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT0_BAR1_IDX015"      ,	          0x20004cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT2_BAR1_IDX000"      ,	          0x200010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT2_BAR1_IDX001"      ,	          0x200014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT2_BAR1_IDX002"      ,	          0x200018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT2_BAR1_IDX003"      ,	          0x20001cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT2_BAR1_IDX004"      ,	          0x200020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT2_BAR1_IDX005"      ,	          0x200024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT2_BAR1_IDX006"      ,	          0x200028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT2_BAR1_IDX007"      ,	          0x20002cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT2_BAR1_IDX008"      ,	          0x200030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT2_BAR1_IDX009"      ,	          0x200034ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT2_BAR1_IDX010"      ,	          0x200038ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT2_BAR1_IDX011"      ,	          0x20003cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT2_BAR1_IDX012"      ,	          0x200040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT2_BAR1_IDX013"      ,	          0x200044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT2_BAR1_IDX014"      ,	          0x200048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT2_BAR1_IDX015"      ,	          0x20004cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT3_BAR1_IDX000"      ,	          0x200010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT3_BAR1_IDX001"      ,	          0x200014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT3_BAR1_IDX002"      ,	          0x200018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT3_BAR1_IDX003"      ,	          0x20001cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT3_BAR1_IDX004"      ,	          0x200020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT3_BAR1_IDX005"      ,	          0x200024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT3_BAR1_IDX006"      ,	          0x200028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT3_BAR1_IDX007"      ,	          0x20002cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT3_BAR1_IDX008"      ,	          0x200030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT3_BAR1_IDX009"      ,	          0x200034ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT3_BAR1_IDX010"      ,	          0x200038ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT3_BAR1_IDX011"      ,	          0x20003cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT3_BAR1_IDX012"      ,	          0x200040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT3_BAR1_IDX013"      ,	          0x200044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT3_BAR1_IDX014"      ,	          0x200048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT3_BAR1_IDX015"      ,	          0x20004cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1104},
+	{"SRIOMAINT0_BELL_STATUS"      ,	          0x200080ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1105},
+	{"SRIOMAINT2_BELL_STATUS"      ,	          0x200080ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1105},
+	{"SRIOMAINT3_BELL_STATUS"      ,	          0x200080ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1105},
+	{"SRIOMAINT0_COMP_TAG"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1106},
+	{"SRIOMAINT2_COMP_TAG"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1106},
+	{"SRIOMAINT3_COMP_TAG"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1106},
+	{"SRIOMAINT0_CORE_ENABLES"     ,	          0x200070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1107},
+	{"SRIOMAINT2_CORE_ENABLES"     ,	          0x200070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1107},
+	{"SRIOMAINT3_CORE_ENABLES"     ,	          0x200070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1107},
+	{"SRIOMAINT0_DEV_ID"           ,	               0x0ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1108},
+	{"SRIOMAINT2_DEV_ID"           ,	               0x0ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1108},
+	{"SRIOMAINT3_DEV_ID"           ,	               0x0ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1108},
+	{"SRIOMAINT0_DEV_REV"          ,	               0x4ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1109},
+	{"SRIOMAINT2_DEV_REV"          ,	               0x4ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1109},
+	{"SRIOMAINT3_DEV_REV"          ,	               0x4ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1109},
+	{"SRIOMAINT0_DST_OPS"          ,	              0x1cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1110},
+	{"SRIOMAINT2_DST_OPS"          ,	              0x1cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1110},
+	{"SRIOMAINT3_DST_OPS"          ,	              0x1cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1110},
+	{"SRIOMAINT0_ERB_ATTR_CAPT"    ,	            0x2048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1111},
+	{"SRIOMAINT2_ERB_ATTR_CAPT"    ,	            0x2048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1111},
+	{"SRIOMAINT3_ERB_ATTR_CAPT"    ,	            0x2048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1111},
+	{"SRIOMAINT0_ERB_ERR_DET"      ,	            0x2040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1112},
+	{"SRIOMAINT2_ERB_ERR_DET"      ,	            0x2040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1112},
+	{"SRIOMAINT3_ERB_ERR_DET"      ,	            0x2040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1112},
+	{"SRIOMAINT0_ERB_ERR_RATE"     ,	            0x2068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1113},
+	{"SRIOMAINT2_ERB_ERR_RATE"     ,	            0x2068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1113},
+	{"SRIOMAINT3_ERB_ERR_RATE"     ,	            0x2068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1113},
+	{"SRIOMAINT0_ERB_ERR_RATE_EN"  ,	            0x2044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1114},
+	{"SRIOMAINT2_ERB_ERR_RATE_EN"  ,	            0x2044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1114},
+	{"SRIOMAINT3_ERB_ERR_RATE_EN"  ,	            0x2044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1114},
+	{"SRIOMAINT0_ERB_ERR_RATE_THR" ,	            0x206cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1115},
+	{"SRIOMAINT2_ERB_ERR_RATE_THR" ,	            0x206cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1115},
+	{"SRIOMAINT3_ERB_ERR_RATE_THR" ,	            0x206cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1115},
+	{"SRIOMAINT0_ERB_HDR"          ,	            0x2000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1116},
+	{"SRIOMAINT2_ERB_HDR"          ,	            0x2000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1116},
+	{"SRIOMAINT3_ERB_HDR"          ,	            0x2000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1116},
+	{"SRIOMAINT0_ERB_LT_ADDR_CAPT_H",	            0x2010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1117},
+	{"SRIOMAINT2_ERB_LT_ADDR_CAPT_H",	            0x2010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1117},
+	{"SRIOMAINT3_ERB_LT_ADDR_CAPT_H",	            0x2010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1117},
+	{"SRIOMAINT0_ERB_LT_ADDR_CAPT_L",	            0x2014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1118},
+	{"SRIOMAINT2_ERB_LT_ADDR_CAPT_L",	            0x2014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1118},
+	{"SRIOMAINT3_ERB_LT_ADDR_CAPT_L",	            0x2014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1118},
+	{"SRIOMAINT0_ERB_LT_CTRL_CAPT" ,	            0x201cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1119},
+	{"SRIOMAINT2_ERB_LT_CTRL_CAPT" ,	            0x201cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1119},
+	{"SRIOMAINT3_ERB_LT_CTRL_CAPT" ,	            0x201cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1119},
+	{"SRIOMAINT0_ERB_LT_DEV_ID"    ,	            0x2028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1120},
+	{"SRIOMAINT2_ERB_LT_DEV_ID"    ,	            0x2028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1120},
+	{"SRIOMAINT3_ERB_LT_DEV_ID"    ,	            0x2028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1120},
+	{"SRIOMAINT0_ERB_LT_DEV_ID_CAPT",	            0x2018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1121},
+	{"SRIOMAINT2_ERB_LT_DEV_ID_CAPT",	            0x2018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1121},
+	{"SRIOMAINT3_ERB_LT_DEV_ID_CAPT",	            0x2018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1121},
+	{"SRIOMAINT0_ERB_LT_ERR_DET"   ,	            0x2008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1122},
+	{"SRIOMAINT2_ERB_LT_ERR_DET"   ,	            0x2008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1122},
+	{"SRIOMAINT3_ERB_LT_ERR_DET"   ,	            0x2008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1122},
+	{"SRIOMAINT0_ERB_LT_ERR_EN"    ,	            0x200cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1123},
+	{"SRIOMAINT2_ERB_LT_ERR_EN"    ,	            0x200cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1123},
+	{"SRIOMAINT3_ERB_LT_ERR_EN"    ,	            0x200cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1123},
+	{"SRIOMAINT0_ERB_PACK_CAPT_1"  ,	            0x2050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1124},
+	{"SRIOMAINT2_ERB_PACK_CAPT_1"  ,	            0x2050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1124},
+	{"SRIOMAINT3_ERB_PACK_CAPT_1"  ,	            0x2050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1124},
+	{"SRIOMAINT0_ERB_PACK_CAPT_2"  ,	            0x2054ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1125},
+	{"SRIOMAINT2_ERB_PACK_CAPT_2"  ,	            0x2054ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1125},
+	{"SRIOMAINT3_ERB_PACK_CAPT_2"  ,	            0x2054ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1125},
+	{"SRIOMAINT0_ERB_PACK_CAPT_3"  ,	            0x2058ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1126},
+	{"SRIOMAINT2_ERB_PACK_CAPT_3"  ,	            0x2058ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1126},
+	{"SRIOMAINT3_ERB_PACK_CAPT_3"  ,	            0x2058ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1126},
+	{"SRIOMAINT0_ERB_PACK_SYM_CAPT",	            0x204cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1127},
+	{"SRIOMAINT2_ERB_PACK_SYM_CAPT",	            0x204cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1127},
+	{"SRIOMAINT3_ERB_PACK_SYM_CAPT",	            0x204cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1127},
+	{"SRIOMAINT0_HB_DEV_ID_LOCK"   ,	              0x68ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1128},
+	{"SRIOMAINT2_HB_DEV_ID_LOCK"   ,	              0x68ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1128},
+	{"SRIOMAINT3_HB_DEV_ID_LOCK"   ,	              0x68ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1128},
+	{"SRIOMAINT0_IR_BUFFER_CONFIG" ,	          0x102000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1129},
+	{"SRIOMAINT2_IR_BUFFER_CONFIG" ,	          0x102000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1129},
+	{"SRIOMAINT3_IR_BUFFER_CONFIG" ,	          0x102000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1129},
+	{"SRIOMAINT0_IR_BUFFER_CONFIG2",	          0x102004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1130},
+	{"SRIOMAINT2_IR_BUFFER_CONFIG2",	          0x102004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1130},
+	{"SRIOMAINT3_IR_BUFFER_CONFIG2",	          0x102004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1130},
+	{"SRIOMAINT0_IR_PD_PHY_CTRL"   ,	          0x107028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1131},
+	{"SRIOMAINT2_IR_PD_PHY_CTRL"   ,	          0x107028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1131},
+	{"SRIOMAINT3_IR_PD_PHY_CTRL"   ,	          0x107028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1131},
+	{"SRIOMAINT0_IR_PD_PHY_STAT"   ,	          0x10702cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1132},
+	{"SRIOMAINT2_IR_PD_PHY_STAT"   ,	          0x10702cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1132},
+	{"SRIOMAINT3_IR_PD_PHY_STAT"   ,	          0x10702cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1132},
+	{"SRIOMAINT0_IR_PI_PHY_CTRL"   ,	          0x107020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1133},
+	{"SRIOMAINT2_IR_PI_PHY_CTRL"   ,	          0x107020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1133},
+	{"SRIOMAINT3_IR_PI_PHY_CTRL"   ,	          0x107020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1133},
+	{"SRIOMAINT0_IR_PI_PHY_STAT"   ,	          0x107024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1134},
+	{"SRIOMAINT2_IR_PI_PHY_STAT"   ,	          0x107024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1134},
+	{"SRIOMAINT3_IR_PI_PHY_STAT"   ,	          0x107024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1134},
+	{"SRIOMAINT0_IR_SP_RX_CTRL"    ,	          0x10700cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1135},
+	{"SRIOMAINT2_IR_SP_RX_CTRL"    ,	          0x10700cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1135},
+	{"SRIOMAINT3_IR_SP_RX_CTRL"    ,	          0x10700cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1135},
+	{"SRIOMAINT0_IR_SP_RX_DATA"    ,	          0x107014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1136},
+	{"SRIOMAINT2_IR_SP_RX_DATA"    ,	          0x107014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1136},
+	{"SRIOMAINT3_IR_SP_RX_DATA"    ,	          0x107014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1136},
+	{"SRIOMAINT0_IR_SP_RX_STAT"    ,	          0x107010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1137},
+	{"SRIOMAINT2_IR_SP_RX_STAT"    ,	          0x107010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1137},
+	{"SRIOMAINT3_IR_SP_RX_STAT"    ,	          0x107010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1137},
+	{"SRIOMAINT0_IR_SP_TX_CTRL"    ,	          0x107000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1138},
+	{"SRIOMAINT2_IR_SP_TX_CTRL"    ,	          0x107000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1138},
+	{"SRIOMAINT3_IR_SP_TX_CTRL"    ,	          0x107000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1138},
+	{"SRIOMAINT0_IR_SP_TX_DATA"    ,	          0x107008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1139},
+	{"SRIOMAINT2_IR_SP_TX_DATA"    ,	          0x107008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1139},
+	{"SRIOMAINT3_IR_SP_TX_DATA"    ,	          0x107008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1139},
+	{"SRIOMAINT0_IR_SP_TX_STAT"    ,	          0x107004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1140},
+	{"SRIOMAINT2_IR_SP_TX_STAT"    ,	          0x107004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1140},
+	{"SRIOMAINT3_IR_SP_TX_STAT"    ,	          0x107004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1140},
+	{"SRIOMAINT0_LANE_000_STATUS_0",	            0x1010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1141},
+	{"SRIOMAINT0_LANE_001_STATUS_0",	            0x1030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1141},
+	{"SRIOMAINT0_LANE_002_STATUS_0",	            0x1050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1141},
+	{"SRIOMAINT0_LANE_003_STATUS_0",	            0x1070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1141},
+	{"SRIOMAINT2_LANE_000_STATUS_0",	            0x1010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1141},
+	{"SRIOMAINT2_LANE_001_STATUS_0",	            0x1030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1141},
+	{"SRIOMAINT2_LANE_002_STATUS_0",	            0x1050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1141},
+	{"SRIOMAINT2_LANE_003_STATUS_0",	            0x1070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1141},
+	{"SRIOMAINT3_LANE_000_STATUS_0",	            0x1010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1141},
+	{"SRIOMAINT3_LANE_001_STATUS_0",	            0x1030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1141},
+	{"SRIOMAINT3_LANE_002_STATUS_0",	            0x1050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1141},
+	{"SRIOMAINT3_LANE_003_STATUS_0",	            0x1070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1141},
+	{"SRIOMAINT0_LCS_BA0"          ,	              0x58ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1142},
+	{"SRIOMAINT2_LCS_BA0"          ,	              0x58ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1142},
+	{"SRIOMAINT3_LCS_BA0"          ,	              0x58ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1142},
+	{"SRIOMAINT0_LCS_BA1"          ,	              0x5cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1143},
+	{"SRIOMAINT2_LCS_BA1"          ,	              0x5cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1143},
+	{"SRIOMAINT3_LCS_BA1"          ,	              0x5cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1143},
+	{"SRIOMAINT0_M2S_BAR0_START0"  ,	          0x200000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1144},
+	{"SRIOMAINT2_M2S_BAR0_START0"  ,	          0x200000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1144},
+	{"SRIOMAINT3_M2S_BAR0_START0"  ,	          0x200000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1144},
+	{"SRIOMAINT0_M2S_BAR0_START1"  ,	          0x200004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1145},
+	{"SRIOMAINT2_M2S_BAR0_START1"  ,	          0x200004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1145},
+	{"SRIOMAINT3_M2S_BAR0_START1"  ,	          0x200004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1145},
+	{"SRIOMAINT0_M2S_BAR1_START0"  ,	          0x200008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1146},
+	{"SRIOMAINT2_M2S_BAR1_START0"  ,	          0x200008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1146},
+	{"SRIOMAINT3_M2S_BAR1_START0"  ,	          0x200008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1146},
+	{"SRIOMAINT0_M2S_BAR1_START1"  ,	          0x20000cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1147},
+	{"SRIOMAINT2_M2S_BAR1_START1"  ,	          0x20000cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1147},
+	{"SRIOMAINT3_M2S_BAR1_START1"  ,	          0x20000cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1147},
+	{"SRIOMAINT0_M2S_BAR2_START"   ,	          0x200050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1148},
+	{"SRIOMAINT2_M2S_BAR2_START"   ,	          0x200050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1148},
+	{"SRIOMAINT3_M2S_BAR2_START"   ,	          0x200050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1148},
+	{"SRIOMAINT0_MAC_CTRL"         ,	          0x200068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1149},
+	{"SRIOMAINT2_MAC_CTRL"         ,	          0x200068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1149},
+	{"SRIOMAINT3_MAC_CTRL"         ,	          0x200068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1149},
+	{"SRIOMAINT0_PE_FEAT"          ,	              0x10ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1150},
+	{"SRIOMAINT2_PE_FEAT"          ,	              0x10ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1150},
+	{"SRIOMAINT3_PE_FEAT"          ,	              0x10ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1150},
+	{"SRIOMAINT0_PE_LLC"           ,	              0x4cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1151},
+	{"SRIOMAINT2_PE_LLC"           ,	              0x4cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1151},
+	{"SRIOMAINT3_PE_LLC"           ,	              0x4cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1151},
+	{"SRIOMAINT0_PORT_0_CTL"       ,	             0x15cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1152},
+	{"SRIOMAINT2_PORT_0_CTL"       ,	             0x15cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1152},
+	{"SRIOMAINT3_PORT_0_CTL"       ,	             0x15cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1152},
+	{"SRIOMAINT0_PORT_0_CTL2"      ,	             0x154ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1153},
+	{"SRIOMAINT2_PORT_0_CTL2"      ,	             0x154ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1153},
+	{"SRIOMAINT3_PORT_0_CTL2"      ,	             0x154ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1153},
+	{"SRIOMAINT0_PORT_0_ERR_STAT"  ,	             0x158ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1154},
+	{"SRIOMAINT2_PORT_0_ERR_STAT"  ,	             0x158ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1154},
+	{"SRIOMAINT3_PORT_0_ERR_STAT"  ,	             0x158ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1154},
+	{"SRIOMAINT0_PORT_0_LINK_REQ"  ,	             0x140ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1155},
+	{"SRIOMAINT2_PORT_0_LINK_REQ"  ,	             0x140ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1155},
+	{"SRIOMAINT3_PORT_0_LINK_REQ"  ,	             0x140ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1155},
+	{"SRIOMAINT0_PORT_0_LINK_RESP" ,	             0x144ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1156},
+	{"SRIOMAINT2_PORT_0_LINK_RESP" ,	             0x144ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1156},
+	{"SRIOMAINT3_PORT_0_LINK_RESP" ,	             0x144ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1156},
+	{"SRIOMAINT0_PORT_0_LOCAL_ACKID",	             0x148ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1157},
+	{"SRIOMAINT2_PORT_0_LOCAL_ACKID",	             0x148ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1157},
+	{"SRIOMAINT3_PORT_0_LOCAL_ACKID",	             0x148ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1157},
+	{"SRIOMAINT0_PORT_GEN_CTL"     ,	             0x13cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1158},
+	{"SRIOMAINT2_PORT_GEN_CTL"     ,	             0x13cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1158},
+	{"SRIOMAINT3_PORT_GEN_CTL"     ,	             0x13cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1158},
+	{"SRIOMAINT0_PORT_LT_CTL"      ,	             0x120ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1159},
+	{"SRIOMAINT2_PORT_LT_CTL"      ,	             0x120ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1159},
+	{"SRIOMAINT3_PORT_LT_CTL"      ,	             0x120ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1159},
+	{"SRIOMAINT0_PORT_MBH0"        ,	             0x100ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1160},
+	{"SRIOMAINT2_PORT_MBH0"        ,	             0x100ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1160},
+	{"SRIOMAINT3_PORT_MBH0"        ,	             0x100ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1160},
+	{"SRIOMAINT0_PORT_RT_CTL"      ,	             0x124ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1161},
+	{"SRIOMAINT2_PORT_RT_CTL"      ,	             0x124ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1161},
+	{"SRIOMAINT3_PORT_RT_CTL"      ,	             0x124ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1161},
+	{"SRIOMAINT0_PORT_TTL_CTL"     ,	             0x12cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1162},
+	{"SRIOMAINT2_PORT_TTL_CTL"     ,	             0x12cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1162},
+	{"SRIOMAINT3_PORT_TTL_CTL"     ,	             0x12cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1162},
+	{"SRIOMAINT0_PRI_DEV_ID"       ,	              0x60ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1163},
+	{"SRIOMAINT2_PRI_DEV_ID"       ,	              0x60ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1163},
+	{"SRIOMAINT3_PRI_DEV_ID"       ,	              0x60ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1163},
+	{"SRIOMAINT0_SEC_DEV_CTRL"     ,	          0x200064ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1164},
+	{"SRIOMAINT2_SEC_DEV_CTRL"     ,	          0x200064ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1164},
+	{"SRIOMAINT3_SEC_DEV_CTRL"     ,	          0x200064ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1164},
+	{"SRIOMAINT0_SEC_DEV_ID"       ,	          0x200060ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1165},
+	{"SRIOMAINT2_SEC_DEV_ID"       ,	          0x200060ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1165},
+	{"SRIOMAINT3_SEC_DEV_ID"       ,	          0x200060ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1165},
+	{"SRIOMAINT0_SERIAL_LANE_HDR"  ,	            0x1000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1166},
+	{"SRIOMAINT2_SERIAL_LANE_HDR"  ,	            0x1000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1166},
+	{"SRIOMAINT3_SERIAL_LANE_HDR"  ,	            0x1000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1166},
+	{"SRIOMAINT0_SRC_OPS"          ,	              0x18ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1167},
+	{"SRIOMAINT2_SRC_OPS"          ,	              0x18ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1167},
+	{"SRIOMAINT3_SRC_OPS"          ,	              0x18ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1167},
+	{"SRIOMAINT0_TX_DROP"          ,	          0x20006cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1168},
+	{"SRIOMAINT2_TX_DROP"          ,	          0x20006cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1168},
+	{"SRIOMAINT3_TX_DROP"          ,	          0x20006cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1168},
+	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1169},
+	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1170},
+	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1171},
+	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1172},
+	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1173},
+	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1174},
+	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1175},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1176},
+	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1177},
+	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1178},
+	{"TRA0_BIST_STATUS"            ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1179},
+	{"TRA0_CTL"                    ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1180},
+	{"TRA0_CYCLES_SINCE"           ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1181},
+	{"TRA0_CYCLES_SINCE1"          ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1182},
+	{"TRA0_FILT_ADR_ADR"           ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1183},
+	{"TRA0_FILT_ADR_MSK"           ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1184},
+	{"TRA0_FILT_CMD"               ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1185},
+	{"TRA0_FILT_DID"               ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1186},
+	{"TRA0_FILT_SID"               ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1187},
+	{"TRA0_INT_STATUS"             ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1188},
+	{"TRA0_READ_DAT"               ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1189},
+	{"TRA0_READ_DAT_HI"            ,	   0x11800a8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1190},
+	{"TRA0_TRIG0_ADR_ADR"          ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1191},
+	{"TRA0_TRIG0_ADR_MSK"          ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1192},
+	{"TRA0_TRIG0_CMD"              ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1193},
+	{"TRA0_TRIG0_DID"              ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1194},
+	{"TRA0_TRIG0_SID"              ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1195},
+	{"TRA0_TRIG1_ADR_ADR"          ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1196},
+	{"TRA0_TRIG1_ADR_MSK"          ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1197},
+	{"TRA0_TRIG1_CMD"              ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1198},
+	{"TRA0_TRIG1_DID"              ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1199},
+	{"TRA0_TRIG1_SID"              ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1200},
+	{"UAHC0_EHCI_ASYNCLISTADDR"    ,	   0x16f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1201},
+	{"UAHC0_EHCI_CONFIGFLAG"       ,	   0x16f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1202},
+	{"UAHC0_EHCI_CTRLDSSEGMENT"    ,	   0x16f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1203},
+	{"UAHC0_EHCI_FRINDEX"          ,	   0x16f000000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1204},
+	{"UAHC0_EHCI_HCCAPBASE"        ,	   0x16f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1205},
+	{"UAHC0_EHCI_HCCPARAMS"        ,	   0x16f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1206},
+	{"UAHC0_EHCI_HCSPARAMS"        ,	   0x16f0000000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1207},
+	{"UAHC0_EHCI_INSNREG00"        ,	   0x16f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1208},
+	{"UAHC0_EHCI_INSNREG03"        ,	   0x16f000000009cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1209},
+	{"UAHC0_EHCI_INSNREG04"        ,	   0x16f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1210},
+	{"UAHC0_EHCI_INSNREG06"        ,	   0x16f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1211},
+	{"UAHC0_EHCI_INSNREG07"        ,	   0x16f00000000ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	1212},
+	{"UAHC0_EHCI_PERIODICLISTBASE" ,	   0x16f0000000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1213},
+	{"UAHC0_EHCI_PORTSC001"        ,	   0x16f0000000054ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1214},
+	{"UAHC0_EHCI_PORTSC002"        ,	   0x16f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1214},
+	{"UAHC0_EHCI_USBCMD"           ,	   0x16f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1215},
+	{"UAHC0_EHCI_USBINTR"          ,	   0x16f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1216},
+	{"UAHC0_EHCI_USBSTS"           ,	   0x16f0000000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1217},
+	{"UAHC0_OHCI0_HCBULKCURRENTED" ,	   0x16f000000042cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1218},
+	{"UAHC0_OHCI0_HCBULKHEADED"    ,	   0x16f0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1219},
+	{"UAHC0_OHCI0_HCCOMMANDSTATUS" ,	   0x16f0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1220},
+	{"UAHC0_OHCI0_HCCONTROL"       ,	   0x16f0000000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1221},
+	{"UAHC0_OHCI0_HCCONTROLCURRENTED",	   0x16f0000000424ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1222},
+	{"UAHC0_OHCI0_HCCONTROLHEADED" ,	   0x16f0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1223},
+	{"UAHC0_OHCI0_HCDONEHEAD"      ,	   0x16f0000000430ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1224},
+	{"UAHC0_OHCI0_HCFMINTERVAL"    ,	   0x16f0000000434ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1225},
+	{"UAHC0_OHCI0_HCFMNUMBER"      ,	   0x16f000000043cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1226},
+	{"UAHC0_OHCI0_HCFMREMAINING"   ,	   0x16f0000000438ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1227},
+	{"UAHC0_OHCI0_HCHCCA"          ,	   0x16f0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1228},
+	{"UAHC0_OHCI0_HCINTERRUPTDISABLE",	   0x16f0000000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1229},
+	{"UAHC0_OHCI0_HCINTERRUPTENABLE",	   0x16f0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1230},
+	{"UAHC0_OHCI0_HCINTERRUPTSTATUS",	   0x16f000000040cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1231},
+	{"UAHC0_OHCI0_HCLSTHRESHOLD"   ,	   0x16f0000000444ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1232},
+	{"UAHC0_OHCI0_HCPERIODCURRENTED",	   0x16f000000041cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1233},
+	{"UAHC0_OHCI0_HCPERIODICSTART" ,	   0x16f0000000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1234},
+	{"UAHC0_OHCI0_HCREVISION"      ,	   0x16f0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1235},
+	{"UAHC0_OHCI0_HCRHDESCRIPTORA" ,	   0x16f0000000448ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1236},
+	{"UAHC0_OHCI0_HCRHDESCRIPTORB" ,	   0x16f000000044cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1237},
+	{"UAHC0_OHCI0_HCRHPORTSTATUS001",	   0x16f0000000454ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1238},
+	{"UAHC0_OHCI0_HCRHPORTSTATUS002",	   0x16f0000000458ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1238},
+	{"UAHC0_OHCI0_HCRHSTATUS"      ,	   0x16f0000000450ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1239},
+	{"UAHC0_OHCI0_INSNREG06"       ,	   0x16f0000000498ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1240},
+	{"UAHC0_OHCI0_INSNREG07"       ,	   0x16f000000049cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1241},
+	{"UCTL0_BIST_STATUS"           ,	   0x118006f0000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1242},
+	{"UCTL0_CLK_RST_CTL"           ,	   0x118006f000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1243},
+	{"UCTL0_EHCI_CTL"              ,	   0x118006f000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1244},
+	{"UCTL0_EHCI_FLA"              ,	   0x118006f0000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1245},
+	{"UCTL0_ERTO_CTL"              ,	   0x118006f000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1246},
+	{"UCTL0_IF_ENA"                ,	   0x118006f000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1247},
+	{"UCTL0_INT_ENA"               ,	   0x118006f000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1248},
+	{"UCTL0_INT_REG"               ,	   0x118006f000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1249},
+	{"UCTL0_OHCI_CTL"              ,	   0x118006f000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1250},
+	{"UCTL0_ORTO_CTL"              ,	   0x118006f000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1251},
+	{"UCTL0_PPAF_WM"               ,	   0x118006f000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1252},
+	{"UCTL0_UPHY_CTL_STATUS"       ,	   0x118006f000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1253},
+	{"UCTL0_UPHY_PORT000_CTL_STATUS",	   0x118006f000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1254},
+	{"UCTL0_UPHY_PORT001_CTL_STATUS",	   0x118006f000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1254},
+	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1255},
+	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1256},
+	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"ZIP_THROTTLE"                ,	   0x1180038000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1262},
+	{NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn66xx[] = {
+	/* name                        ,	bit,	width,	csr,	type,	rst un,	typ un,	reset,	typical */
+	{"RESERVED_0_1"                ,	0,	2,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OUT_OVR"                     ,	2,	2,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_21"               ,	4,	18,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LOSTSTAT"                    ,	22,	2,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_25"              ,	24,	2,	0,	"RAZ",	1,	1,	0,	0},
+	{"STATOVR"                     ,	26,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_31"              ,	27,	5,	0,	"RAZ",	1,	1,	0,	0},
+	{"OVRFLW"                      ,	32,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP"                       ,	33,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH"                       ,	34,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRFLW1"                     ,	35,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP1"                      ,	36,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH1"                      ,	37,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	0,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	25,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	2,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	2,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	2,	"R/W",	0,	1,	1ull,	0},
+	{"RX_EN"                       ,	4,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"TX_EN"                       ,	5,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"BURST"                       ,	6,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	2,	"RAZ",	1,	1,	0,	0},
+	{"SPEED_MSB"                   ,	8,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	2,	"RAZ",	1,	1,	0,	0},
+	{"RX_IDLE"                     ,	12,	1,	2,	"RO",	0,	1,	1ull,	0},
+	{"TX_IDLE"                     ,	13,	1,	2,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	2,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	3,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	4,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	5,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	6,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	7,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	8,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	9,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	9,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	10,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	10,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	10,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	10,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	11,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	11,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR"                      ,	2,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"JABBER"                      ,	3,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALNERR"                      ,	5,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR"                      ,	6,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"RCVERR"                      ,	7,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"NIBERR"                      ,	9,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	12,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	13,	"RO",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	7,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	8,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_ALIGN"                   ,	9,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"NULL_DIS"                    ,	10,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	13,	"RAZ",	1,	1,	0,	0},
+	{"PTP_MODE"                    ,	12,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	13,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	14,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_16_63"              ,	16,	48,	14,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	15,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_16_63"              ,	16,	48,	15,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	16,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	16,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	17,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	18,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	19,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	19,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	20,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	20,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	1,	21,	"RO",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	2,	21,	"RO",	0,	1,	0ull,	0},
+	{"DUPLEX"                      ,	3,	1,	21,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	21,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	22,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	22,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	23,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	23,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	24,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	24,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	25,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	25,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	26,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	26,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	27,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	27,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	28,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	28,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	29,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	29,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	30,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	30,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	31,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	31,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	32,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	32,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	32,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	32,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	33,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	33,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	34,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	34,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	35,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_9_63"               ,	9,	55,	35,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	2,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_15"               ,	2,	14,	36,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	2,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	36,	"RAZ",	1,	1,	0,	0},
+	{"RX"                          ,	0,	2,	37,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	37,	"RAZ",	1,	1,	0,	0},
+	{"TX"                          ,	4,	2,	37,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	37,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	38,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	38,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	39,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	39,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	40,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	6,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_63"               ,	6,	58,	41,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	42,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	43,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	43,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	44,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	44,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	45,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	45,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	46,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	46,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	47,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	47,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	48,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	48,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	51,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	51,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	52,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	52,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	59,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	6,	60,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	60,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	2,	61,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	61,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	62,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	62,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	63,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	63,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	63,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	64,	"RAZ",	1,	1,	0,	0},
+	{"UNDFLW"                      ,	2,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	64,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	8,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"XSDEF"                       ,	12,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"LATE_COL"                    ,	16,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"PTP_LOST"                    ,	20,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	64,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	65,	"RAZ",	1,	1,	0,	0},
+	{"UNDFLW"                      ,	2,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	65,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	8,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"XSDEF"                       ,	12,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"LATE_COL"                    ,	16,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"PTP_LOST"                    ,	20,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	65,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	66,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	66,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	67,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	67,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	68,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	4,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	68,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	8,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	68,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	69,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	69,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	70,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	70,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	1,	71,	"R/W",	0,	1,	1ull,	0},
+	{"CLKRST"                      ,	1,	1,	71,	"R/W",	0,	0,	1ull,	0ull},
+	{"ENABLE"                      ,	2,	1,	71,	"R/W",	0,	0,	1ull,	1ull},
+	{"COMP"                        ,	3,	1,	71,	"R/W",	0,	0,	0ull,	1ull},
+	{"DLLRST"                      ,	4,	1,	71,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	71,	"RAZ",	1,	1,	0,	0},
+	{"CLKTX_SET"                   ,	8,	5,	71,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_14"              ,	13,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CLKTX_BYP"                   ,	15,	1,	71,	"R/W",	0,	1,	1ull,	0},
+	{"CLKRX_SET"                   ,	16,	5,	71,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_22"              ,	21,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CLKRX_BYP"                   ,	23,	1,	71,	"R/W",	0,	1,	0ull,	0},
+	{"CLK_SET"                     ,	24,	5,	71,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_31"              ,	29,	3,	71,	"RAZ",	1,	1,	0,	0},
+	{"DRV_NCTL"                    ,	32,	6,	71,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_38_39"              ,	38,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"DRV_PCTL"                    ,	40,	6,	71,	"R/W",	0,	1,	19ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CMP_NCTL"                    ,	48,	6,	71,	"RO",	1,	1,	0,	0},
+	{"RESERVED_54_55"              ,	54,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CMP_PCTL"                    ,	56,	6,	71,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	71,	"RAZ",	1,	1,	0,	0},
+	{"DRV_BYP"                     ,	63,	1,	71,	"R/W",	0,	0,	1ull,	0ull},
+	{"BIST"                        ,	0,	6,	72,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	72,	"RAZ",	1,	1,	0,	0},
+	{"MIO"                         ,	0,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX0"                        ,	1,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX1"                        ,	2,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	3,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	4,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	5,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	6,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	7,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_8"                ,	8,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"IPD"                         ,	9,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	10,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	11,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	12,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	13,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	14,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	16,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	17,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	73,	"RAZ",	1,	1,	0,	0},
+	{"PIP"                         ,	20,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_21"              ,	21,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"ASXPCS0"                     ,	22,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"ASXPCS1"                     ,	23,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_24"              ,	24,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"PEM0"                        ,	25,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	26,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	28,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_29"              ,	29,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	30,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"SRIO0"                       ,	32,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	73,	"RAZ",	1,	1,	0,	0},
+	{"DFM"                         ,	40,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	41,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	42,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_59"              ,	43,	17,	73,	"RAZ",	1,	1,	0,	0},
+	{"SRIO2"                       ,	60,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"SRIO3"                       ,	61,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	73,	"RAZ",	1,	1,	0,	0},
+	{"DINT"                        ,	0,	10,	74,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	74,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	75,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	75,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	76,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	76,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	77,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	77,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	78,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	78,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	78,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	79,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	79,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	79,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	80,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	80,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	80,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	81,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	81,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	82,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	82,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	83,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	83,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	84,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	84,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	84,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	85,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	85,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	85,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	86,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	86,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	86,	"RAZ",	1,	1,	0,	0},
+	{"FUSE"                        ,	0,	10,	87,	"RO",	1,	1,	0,	0},
+	{"RESERVED_10_63"              ,	10,	54,	87,	"RAZ",	1,	1,	0,	0},
+	{"GSTOP"                       ,	0,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	88,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	89,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	89,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_57"              ,	57,	1,	89,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	89,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	90,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	90,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_57"              ,	57,	1,	90,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	91,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	91,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_57"              ,	57,	1,	91,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	10,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_17"              ,	10,	8,	92,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_45"              ,	38,	8,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFM"                         ,	56,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_59"              ,	57,	3,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRIO2"                       ,	60,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRIO3"                       ,	61,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	10,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_17"              ,	10,	8,	93,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_45"              ,	38,	8,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DFM"                         ,	56,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_59"              ,	57,	3,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SRIO2"                       ,	60,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SRIO3"                       ,	61,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	93,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	10,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_17"              ,	10,	8,	94,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_45"              ,	38,	8,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DFM"                         ,	56,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_59"              ,	57,	3,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SRIO2"                       ,	60,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SRIO3"                       ,	61,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	95,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	95,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_57"              ,	57,	1,	95,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	96,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	96,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_57"              ,	57,	1,	96,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	96,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	97,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	97,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_57"              ,	57,	1,	97,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	97,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	10,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_17"              ,	10,	8,	98,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_45"              ,	38,	8,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFM"                         ,	56,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_59"              ,	57,	3,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRIO2"                       ,	60,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRIO3"                       ,	61,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	10,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_17"              ,	10,	8,	99,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_45"              ,	38,	8,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DFM"                         ,	56,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_59"              ,	57,	3,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SRIO2"                       ,	60,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SRIO3"                       ,	61,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	99,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	99,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	10,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_17"              ,	10,	8,	100,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_45"              ,	38,	8,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DFM"                         ,	56,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_59"              ,	57,	3,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SRIO2"                       ,	60,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SRIO3"                       ,	61,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	100,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SUM2"                        ,	51,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_57"              ,	57,	1,	101,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	102,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	102,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SUM2"                        ,	51,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	102,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_57"              ,	57,	1,	102,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	102,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	103,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	103,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SUM2"                        ,	51,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	103,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_57"              ,	57,	1,	103,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	103,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	4,	104,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	104,	"RAZ",	1,	1,	0,	0},
+	{"IRQ"                         ,	8,	2,	104,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	104,	"RAZ",	1,	1,	0,	0},
+	{"SEL"                         ,	16,	3,	104,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_19_63"              ,	19,	45,	104,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	10,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_17"              ,	10,	8,	105,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_45"              ,	38,	8,	105,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	46,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	105,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	105,	"RAZ",	1,	1,	0,	0},
+	{"DFM"                         ,	56,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_59"              ,	57,	3,	105,	"RAZ",	1,	1,	0,	0},
+	{"SRIO2"                       ,	60,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"SRIO3"                       ,	61,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	105,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"BITS"                        ,	0,	32,	106,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	106,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	107,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	107,	"RAZ",	1,	1,	0,	0},
+	{"NMI"                         ,	0,	10,	108,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	108,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	2,	109,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	109,	"RAZ",	1,	1,	0,	0},
+	{"PPDBG"                       ,	0,	10,	110,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	110,	"RAZ",	1,	1,	0,	0},
+	{"POKE"                        ,	0,	64,	111,	"RAZ",	1,	1,	0,	0},
+	{"RST0"                        ,	0,	1,	112,	"R/W",	1,	1,	0,	0},
+	{"RST"                         ,	1,	9,	112,	"R/W",	0,	0,	511ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	112,	"RAZ",	1,	1,	0,	0},
+	{"LANE_EN"                     ,	0,	4,	113,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	113,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	113,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	113,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	113,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	113,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	113,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_39"              ,	32,	8,	113,	"RAZ",	1,	1,	0,	0},
+	{"G2MARGIN"                    ,	40,	5,	113,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	113,	"RAZ",	1,	1,	0,	0},
+	{"G2DEEMPH"                    ,	48,	5,	113,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_53_62"              ,	53,	10,	113,	"RAZ",	1,	1,	0,	0},
+	{"G2BYPASS"                    ,	63,	1,	113,	"R/W",	0,	1,	0ull,	0},
+	{"LANE_EN"                     ,	0,	4,	114,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	114,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	114,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	114,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	114,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	114,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	114,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_39"              ,	32,	8,	114,	"RAZ",	1,	1,	0,	0},
+	{"G2MARGIN"                    ,	40,	5,	114,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	114,	"RAZ",	1,	1,	0,	0},
+	{"G2DEEMPH"                    ,	48,	5,	114,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_53_62"              ,	53,	10,	114,	"RAZ",	1,	1,	0,	0},
+	{"G2BYPASS"                    ,	63,	1,	114,	"R/W",	0,	1,	0ull,	0},
+	{"LANE_EN"                     ,	0,	4,	115,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	115,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	115,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	115,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	115,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	115,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	115,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	115,	"RAZ",	1,	1,	0,	0},
+	{"BYPASS"                      ,	0,	3,	116,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	116,	"RAZ",	1,	1,	0,	0},
+	{"MUX_SEL"                     ,	4,	2,	116,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	116,	"RAZ",	1,	1,	0,	0},
+	{"CLK_DIV"                     ,	8,	3,	116,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	116,	"RAZ",	1,	1,	0,	0},
+	{"SHFT_REG"                    ,	0,	32,	117,	"R/W",	0,	1,	0ull,	0},
+	{"SHFT_CNT"                    ,	32,	5,	117,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_37_39"              ,	37,	3,	117,	"RAZ",	1,	1,	0,	0},
+	{"SELECT"                      ,	40,	3,	117,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_43_60"              ,	43,	18,	117,	"RAZ",	1,	1,	0,	0},
+	{"UPDATE"                      ,	61,	1,	117,	"R/W",	0,	1,	0ull,	0},
+	{"SHIFT"                       ,	62,	1,	117,	"R/W",	0,	1,	0ull,	0},
+	{"CAPTURE"                     ,	63,	1,	117,	"R/W",	0,	1,	0ull,	0},
+	{"SOFT_BIST"                   ,	0,	1,	118,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	118,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	119,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	119,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	120,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	120,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	121,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	121,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	122,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	122,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST"                    ,	0,	1,	123,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	123,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	10,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_17"              ,	10,	8,	124,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_45"              ,	38,	8,	124,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	46,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	124,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	124,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	124,	"RAZ",	1,	1,	0,	0},
+	{"DFM"                         ,	56,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_59"              ,	57,	3,	124,	"RAZ",	1,	1,	0,	0},
+	{"SRIO2"                       ,	60,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"SRIO3"                       ,	61,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	124,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	10,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_17"              ,	10,	8,	125,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_45"              ,	38,	8,	125,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	46,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	125,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	125,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	125,	"RAZ",	1,	1,	0,	0},
+	{"DFM"                         ,	56,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_59"              ,	57,	3,	125,	"RAZ",	1,	1,	0,	0},
+	{"SRIO2"                       ,	60,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"SRIO3"                       ,	61,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	125,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	10,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_17"              ,	10,	8,	126,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_45"              ,	38,	8,	126,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	46,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	126,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	126,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	126,	"RAZ",	1,	1,	0,	0},
+	{"DFM"                         ,	56,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_59"              ,	57,	3,	126,	"RAZ",	1,	1,	0,	0},
+	{"SRIO2"                       ,	60,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"SRIO3"                       ,	61,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	126,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	126,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	10,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_17"              ,	10,	8,	127,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX1"                        ,	37,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_45"              ,	38,	8,	127,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	46,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	127,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	127,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	127,	"RAZ",	1,	1,	0,	0},
+	{"DFM"                         ,	56,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_59"              ,	57,	3,	127,	"RAZ",	1,	1,	0,	0},
+	{"SRIO2"                       ,	60,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"SRIO3"                       ,	61,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	127,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	128,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	128,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	129,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	129,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	129,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	130,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	130,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	130,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	131,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	131,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	36,	132,	"R/W",	0,	0,	0ull,	0ull},
+	{"ONE_SHOT"                    ,	36,	1,	132,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	132,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	133,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	133,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	2,	2,	134,	"RO",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	4,	16,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	20,	24,	134,	"RO",	0,	0,	0ull,	0ull},
+	{"DSTOP"                       ,	44,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSTOPEN"                     ,	45,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	134,	"RAZ",	1,	1,	0,	0},
+	{"PDB"                         ,	0,	1,	135,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	135,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RDF"                         ,	4,	1,	135,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	135,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTX"                         ,	8,	2,	135,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	135,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STX"                         ,	16,	2,	135,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_23"              ,	18,	6,	135,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GFB"                         ,	24,	1,	135,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	135,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MWB"                         ,	28,	1,	135,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	135,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GFU"                         ,	0,	1,	136,	"RO",	0,	0,	0ull,	0ull},
+	{"GIB"                         ,	1,	1,	136,	"RO",	0,	0,	0ull,	0ull},
+	{"GIF"                         ,	2,	1,	136,	"RO",	0,	0,	0ull,	0ull},
+	{"NCD"                         ,	3,	1,	136,	"RO",	0,	0,	0ull,	0ull},
+	{"GUTP"                        ,	4,	1,	136,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	136,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GUTV"                        ,	8,	1,	136,	"RO",	0,	0,	0ull,	0ull},
+	{"CRQ"                         ,	9,	1,	136,	"RO",	0,	0,	0ull,	0ull},
+	{"RAM1"                        ,	10,	1,	136,	"RO",	0,	0,	0ull,	0ull},
+	{"RAM2"                        ,	11,	1,	136,	"RO",	0,	0,	0ull,	0ull},
+	{"RAM3"                        ,	12,	1,	136,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	136,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTECLKDIS"                   ,	0,	1,	137,	"R/W",	0,	0,	1ull,	0ull},
+	{"CLDTECRIP"                   ,	1,	3,	137,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLMSKCRIP"                   ,	4,	4,	137,	"R/W",	0,	0,	0ull,	0ull},
+	{"REPL_ENA"                    ,	8,	1,	137,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	137,	"RAZ",	1,	1,	0,	0},
+	{"IMODE"                       ,	0,	1,	138,	"R/W",	0,	0,	1ull,	1ull},
+	{"QMODE"                       ,	1,	1,	138,	"R/W",	0,	0,	1ull,	1ull},
+	{"PMODE"                       ,	2,	1,	138,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_4"                ,	3,	2,	138,	"RAZ",	1,	1,	0,	0},
+	{"SBDLCK"                      ,	5,	1,	138,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBDNUM"                      ,	6,	4,	138,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	138,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	20,	139,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	139,	"RAZ",	1,	1,	0,	0},
+	{"SBD0"                        ,	0,	64,	140,	"RO",	1,	1,	0,	0},
+	{"SBD1"                        ,	0,	64,	141,	"RO",	1,	1,	0,	0},
+	{"SBD2"                        ,	0,	64,	142,	"RO",	1,	1,	0,	0},
+	{"SBD3"                        ,	0,	64,	143,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	9,	144,	"R/W",	0,	1,	3ull,	0},
+	{"POOL"                        ,	9,	3,	144,	"R/W",	0,	1,	0ull,	0},
+	{"DWBCNT"                      ,	12,	8,	144,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	144,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	145,	"RAZ",	1,	1,	0,	0},
+	{"RDPTR"                       ,	5,	35,	145,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	145,	"RAZ",	1,	1,	0,	0},
+	{"RAM1FADR"                    ,	0,	14,	146,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	146,	"RAZ",	1,	1,	0,	0},
+	{"RAM2FADR"                    ,	16,	9,	146,	"RO",	1,	1,	0,	0},
+	{"RESERVED_25_31"              ,	25,	7,	146,	"RAZ",	1,	1,	0,	0},
+	{"RAM3FADR"                    ,	32,	12,	146,	"RO",	1,	1,	0,	0},
+	{"RESERVED_44_63"              ,	44,	20,	146,	"RAZ",	1,	1,	0,	0},
+	{"DBLOVF"                      ,	0,	1,	147,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC0PERR"                     ,	1,	3,	147,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	147,	"RAZ",	1,	1,	0,	0},
+	{"CNDRD"                       ,	16,	1,	147,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	147,	"RAZ",	1,	1,	0,	0},
+	{"DBLINA"                      ,	0,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC0PENA"                     ,	1,	3,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	148,	"RAZ",	1,	1,	0,	0},
+	{"HIDAT"                       ,	0,	64,	149,	"R/W",	1,	1,	0,	0},
+	{"PFCNT0"                      ,	0,	64,	150,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	151,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	151,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	151,	"RAZ",	1,	1,	0,	0},
+	{"PFCNT1"                      ,	0,	64,	152,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	153,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	153,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	153,	"RAZ",	1,	1,	0,	0},
+	{"PFCNT2"                      ,	0,	64,	154,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	155,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	155,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	155,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	155,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	155,	"RAZ",	1,	1,	0,	0},
+	{"PFCNT3"                      ,	0,	64,	156,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	157,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	157,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	157,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	157,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	157,	"RAZ",	1,	1,	0,	0},
+	{"CNT0ENA"                     ,	0,	1,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1ENA"                     ,	1,	1,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2ENA"                     ,	2,	1,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3ENA"                     ,	3,	1,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0WCLR"                    ,	4,	1,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1WCLR"                    ,	5,	1,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2WCLR"                    ,	6,	1,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3WCLR"                    ,	7,	1,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0RCLR"                    ,	8,	1,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1RCLR"                    ,	9,	1,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2RCLR"                    ,	10,	1,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3RCLR"                    ,	11,	1,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"SNODE"                       ,	12,	3,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENODE"                       ,	15,	3,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"EDNODE"                      ,	18,	2,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMODE"                       ,	20,	1,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGID"                        ,	21,	8,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	158,	"RAZ",	1,	1,	0,	0},
+	{"PRBS"                        ,	0,	32,	159,	"R/W",	1,	1,	0,	0},
+	{"PROG"                        ,	32,	8,	159,	"R/W",	1,	1,	0,	0},
+	{"SEL"                         ,	40,	1,	159,	"R/W",	1,	1,	0,	0},
+	{"EN"                          ,	41,	1,	159,	"R/W",	1,	1,	0,	0},
+	{"SKEW_ON"                     ,	42,	1,	159,	"R/W",	1,	1,	0,	0},
+	{"DR"                          ,	43,	1,	159,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_44_63"              ,	44,	20,	159,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	160,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	160,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	161,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	161,	"R/W",	1,	1,	0,	0},
+	{"CKE_MASK"                    ,	0,	2,	162,	"R/W",	1,	1,	0,	0},
+	{"CS0_N_MASK"                  ,	2,	2,	162,	"R/W",	1,	1,	0,	0},
+	{"CS1_N_MASK"                  ,	4,	2,	162,	"R/W",	1,	1,	0,	0},
+	{"ODT0_MASK"                   ,	6,	2,	162,	"R/W",	1,	1,	0,	0},
+	{"ODT1_MASK"                   ,	8,	2,	162,	"R/W",	1,	1,	0,	0},
+	{"RAS_N_MASK"                  ,	10,	1,	162,	"R/W",	1,	1,	0,	0},
+	{"CAS_N_MASK"                  ,	11,	1,	162,	"R/W",	1,	1,	0,	0},
+	{"WE_N_MASK"                   ,	12,	1,	162,	"R/W",	1,	1,	0,	0},
+	{"BA_MASK"                     ,	13,	3,	162,	"R/W",	1,	1,	0,	0},
+	{"A_MASK"                      ,	16,	16,	162,	"R/W",	1,	1,	0,	0},
+	{"RESET_N_MASK"                ,	32,	1,	162,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_33_63"              ,	33,	31,	162,	"R/W",	1,	1,	0,	0},
+	{"DQX_CTL"                     ,	0,	4,	163,	"R/W",	0,	1,	4ull,	0},
+	{"CK_CTL"                      ,	4,	4,	163,	"R/W",	0,	1,	4ull,	0},
+	{"CMD_CTL"                     ,	8,	4,	163,	"R/W",	0,	1,	4ull,	0},
+	{"RODT_CTL"                    ,	12,	4,	163,	"R/W",	0,	1,	0ull,	0},
+	{"NTUNE"                       ,	16,	4,	163,	"R/W",	0,	1,	0ull,	0},
+	{"PTUNE"                       ,	20,	4,	163,	"R/W",	0,	1,	0ull,	0},
+	{"BYP"                         ,	24,	1,	163,	"R/W",	0,	1,	0ull,	0},
+	{"M180"                        ,	25,	1,	163,	"R/W",	0,	1,	0ull,	0},
+	{"DDR__NTUNE"                  ,	26,	4,	163,	"RO",	1,	1,	0,	0},
+	{"DDR__PTUNE"                  ,	30,	4,	163,	"RO",	1,	1,	0,	0},
+	{"RESERVED_34_63"              ,	34,	30,	163,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	164,	"WR0",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	164,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROW_LSB"                     ,	2,	3,	164,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	164,	"R/W",	0,	1,	5ull,	0},
+	{"IDLEPOWER"                   ,	9,	3,	164,	"R/W",	0,	0,	0ull,	6ull},
+	{"FORCEWRITE"                  ,	12,	4,	164,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ADR"                     ,	16,	1,	164,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	164,	"R/W",	0,	1,	0ull,	0},
+	{"REF_ZQCS_INT"                ,	18,	19,	164,	"R/W",	1,	1,	0,	0},
+	{"SEQUENCE"                    ,	37,	3,	164,	"R/W",	0,	0,	0ull,	0ull},
+	{"EARLY_DQX"                   ,	40,	1,	164,	"R/W",	0,	0,	0ull,	0ull},
+	{"SREF_WITH_DLL"               ,	41,	1,	164,	"R/W",	0,	0,	0ull,	0ull},
+	{"RANK_ENA"                    ,	42,	1,	164,	"R/W",	0,	1,	0ull,	0},
+	{"RANKMASK"                    ,	43,	4,	164,	"R/W",	0,	1,	0ull,	0},
+	{"MIRRMASK"                    ,	47,	4,	164,	"R/W",	0,	1,	0ull,	0},
+	{"INIT_STATUS"                 ,	51,	4,	164,	"R/W1",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D0_R0"          ,	55,	1,	164,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D0_R1"          ,	56,	1,	164,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D1_R0"          ,	57,	1,	164,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D1_R1"          ,	58,	1,	164,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_59_63"              ,	59,	5,	164,	"RAZ",	1,	1,	0,	0},
+	{"RDIMM_ENA"                   ,	0,	1,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"BWCNT"                       ,	1,	1,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	2,	1,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"POCAS"                       ,	3,	1,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPRCH2"                      ,	4,	2,	165,	"R/W",	0,	0,	0ull,	1ull},
+	{"THROTTLE_RD"                 ,	6,	1,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"THROTTLE_WR"                 ,	7,	1,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_RD"                  ,	8,	1,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_WR"                  ,	9,	1,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"ELEV_PRIO_DIS"               ,	10,	1,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"NXM_WRITE_EN"                ,	11,	1,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	12,	4,	165,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	16,	1,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTO_FCLKDIS"                ,	17,	1,	165,	"R/W",	0,	0,	0ull,	1ull},
+	{"INT_ZQCS_DIS"                ,	18,	1,	165,	"R/W",	0,	0,	1ull,	0ull},
+	{"EXT_ZQCS_DIS"                ,	19,	1,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"BPRCH"                       ,	20,	2,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"WODT_BPRCH"                  ,	22,	1,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_BPRCH"                  ,	23,	1,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	165,	"RAZ",	1,	1,	0,	0},
+	{"BYP_SETTING"                 ,	0,	8,	166,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYP_SEL"                     ,	8,	4,	166,	"R/W",	0,	0,	0ull,	0ull},
+	{"QUAD_DLL_ENA"                ,	12,	1,	166,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	13,	1,	166,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLL_BRINGUP"                 ,	14,	1,	166,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	166,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	6,	167,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYTE_SEL"                    ,	6,	4,	167,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE_SEL"                    ,	10,	2,	167,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOAD_OFFSET"                 ,	12,	1,	167,	"WR0",	0,	0,	0ull,	0ull},
+	{"OFFSET_ENA"                  ,	13,	1,	167,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYTE_SEL"              ,	14,	4,	167,	"R/W",	0,	0,	1ull,	1ull},
+	{"DLL_MODE"                    ,	18,	1,	167,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINE_TUNE_MODE"              ,	19,	1,	167,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_SETTING"               ,	20,	8,	167,	"RO",	1,	1,	0,	0},
+	{"DLL_FAST"                    ,	28,	1,	167,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	167,	"RAZ",	1,	1,	0,	0},
+	{"FCLKCNT"                     ,	0,	64,	168,	"RO",	0,	1,	0ull,	0},
+	{"MWB"                         ,	0,	1,	169,	"RO",	0,	0,	0ull,	0ull},
+	{"RPB"                         ,	1,	1,	169,	"RO",	0,	0,	0ull,	0ull},
+	{"MFF"                         ,	2,	1,	169,	"RO",	0,	0,	0ull,	0ull},
+	{"MRQ"                         ,	3,	1,	169,	"RO",	0,	0,	0ull,	0ull},
+	{"CAB"                         ,	4,	1,	169,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	169,	"RAZ",	1,	1,	0,	0},
+	{"DFR_ENA"                     ,	0,	1,	170,	"R/W",	0,	0,	0ull,	1ull},
+	{"RECC_ENA"                    ,	1,	1,	170,	"R/W",	0,	0,	0ull,	1ull},
+	{"WECC_ENA"                    ,	2,	1,	170,	"R/W",	0,	0,	0ull,	1ull},
+	{"SBE_ENA"                     ,	3,	1,	170,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	170,	"RAZ",	1,	1,	0,	0},
+	{"SBE_INTENA"                  ,	0,	1,	171,	"R/W",	0,	0,	0ull,	1ull},
+	{"DBE_INTENA"                  ,	1,	1,	171,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	171,	"RAZ",	1,	1,	0,	0},
+	{"SCLKDIS"                     ,	0,	1,	172,	"R/W",	0,	0,	1ull,	0ull},
+	{"BIST_START"                  ,	1,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLEAR_BIST"                  ,	2,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	172,	"RAZ",	1,	1,	0,	0},
+	{"SBE_ERR"                     ,	0,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE_ERR"                     ,	1,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	173,	"RAZ",	1,	1,	0,	0},
+	{"FADR"                        ,	4,	28,	173,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN"                        ,	32,	10,	173,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	173,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT"                      ,	0,	64,	174,	"RO",	0,	1,	1ull,	0},
+	{"CWL"                         ,	0,	3,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPRLOC"                      ,	3,	2,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPR"                         ,	5,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL"                         ,	6,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"AL"                          ,	7,	2,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"WLEV"                        ,	9,	1,	175,	"RO",	0,	0,	0ull,	0ull},
+	{"TDQS"                        ,	10,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOFF"                        ,	11,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"BL"                          ,	12,	2,	175,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	14,	4,	175,	"R/W",	0,	0,	2ull,	2ull},
+	{"RBT"                         ,	18,	1,	175,	"RO",	0,	0,	1ull,	1ull},
+	{"TM"                          ,	19,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLR"                        ,	20,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRP"                         ,	21,	3,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPD"                         ,	24,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	175,	"RAZ",	1,	1,	0,	0},
+	{"PASR_00"                     ,	0,	3,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_00"                      ,	3,	1,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_00"                      ,	4,	1,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_00"                   ,	5,	2,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_00"                      ,	7,	2,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_00"                  ,	9,	3,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_01"                     ,	12,	3,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_01"                      ,	15,	1,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_01"                      ,	16,	1,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_01"                   ,	17,	2,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_01"                      ,	19,	2,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_01"                  ,	21,	3,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_10"                     ,	24,	3,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_10"                      ,	27,	1,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_10"                      ,	28,	1,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_10"                   ,	29,	2,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_10"                      ,	31,	2,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_10"                  ,	33,	3,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_11"                     ,	36,	3,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_11"                      ,	39,	1,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_11"                      ,	40,	1,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_11"                   ,	41,	2,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_11"                      ,	43,	2,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_11"                  ,	45,	3,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	176,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT"                      ,	0,	64,	177,	"RO",	0,	1,	1ull,	0},
+	{"TS_STAGGER"                  ,	0,	1,	178,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK_POS"                ,	1,	1,	178,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK"                    ,	2,	1,	178,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT0"                  ,	3,	4,	178,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE0"                    ,	7,	1,	178,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT1"                  ,	8,	4,	178,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE1"                    ,	12,	1,	178,	"R/W",	0,	1,	0ull,	0},
+	{"LV_MODE"                     ,	13,	1,	178,	"R/W",	0,	1,	0ull,	0},
+	{"RX_ALWAYS_ON"                ,	14,	1,	178,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	178,	"RAZ",	1,	1,	0,	0},
+	{"DDR3RST"                     ,	0,	1,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PWARM"                   ,	1,	1,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSOFT"                   ,	2,	1,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSV"                     ,	3,	1,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	179,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	180,	"R/W",	0,	1,	0ull,	0},
+	{"OFFSET"                      ,	4,	4,	180,	"R/W",	0,	0,	2ull,	2ull},
+	{"OFFSET_EN"                   ,	8,	1,	180,	"R/W",	0,	0,	1ull,	1ull},
+	{"OR_DIS"                      ,	9,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	10,	8,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_0"              ,	18,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_1"              ,	19,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_2"              ,	20,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_3"              ,	21,	1,	180,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	180,	"RAZ",	1,	1,	0,	0},
+	{"BITMASK"                     ,	0,	64,	181,	"RO",	0,	0,	0ull,	0ull},
+	{"BYTE0"                       ,	0,	6,	182,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	6,	6,	182,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_53"              ,	12,	42,	182,	"R/W",	1,	1,	0,	0},
+	{"STATUS"                      ,	54,	2,	182,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	182,	"RAZ",	1,	1,	0,	0},
+	{"RODT_D0_R0"                  ,	0,	8,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D0_R1"                  ,	8,	8,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D1_R0"                  ,	16,	8,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D1_R1"                  ,	24,	8,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D2_R0"                  ,	32,	8,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D2_R1"                  ,	40,	8,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R0"                  ,	48,	8,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R1"                  ,	56,	8,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"R2R_INIT"                    ,	0,	6,	184,	"R/W",	0,	1,	1ull,	0},
+	{"R2W_INIT"                    ,	6,	6,	184,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_INIT"                    ,	12,	6,	184,	"R/W",	0,	1,	9ull,	0},
+	{"W2W_INIT"                    ,	18,	6,	184,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	184,	"RAZ",	1,	1,	0,	0},
+	{"R2R_XRANK_INIT"              ,	0,	6,	185,	"R/W",	0,	1,	3ull,	0},
+	{"R2W_XRANK_INIT"              ,	6,	6,	185,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_XRANK_INIT"              ,	12,	6,	185,	"R/W",	0,	1,	4ull,	0},
+	{"W2W_XRANK_INIT"              ,	18,	6,	185,	"R/W",	0,	1,	5ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	185,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_9"                ,	0,	10,	186,	"RAZ",	1,	1,	0,	0},
+	{"TZQCS"                       ,	10,	4,	186,	"R/W",	0,	0,	4ull,	4ull},
+	{"TCKE"                        ,	14,	4,	186,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPR"                        ,	18,	4,	186,	"R/W",	0,	0,	5ull,	5ull},
+	{"TMRD"                        ,	22,	4,	186,	"R/W",	0,	0,	4ull,	4ull},
+	{"TMOD"                        ,	26,	4,	186,	"R/W",	0,	0,	12ull,	12ull},
+	{"TDLLK"                       ,	30,	4,	186,	"R/W",	0,	0,	2ull,	2ull},
+	{"TZQINIT"                     ,	34,	4,	186,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	38,	4,	186,	"R/W",	0,	0,	6ull,	6ull},
+	{"TCKSRE"                      ,	42,	4,	186,	"R/W",	0,	0,	5ull,	5ull},
+	{"TRP_EXT"                     ,	46,	1,	186,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	186,	"RAZ",	1,	1,	0,	0},
+	{"TMPRR"                       ,	0,	4,	187,	"R/W",	0,	0,	1ull,	1ull},
+	{"TRAS"                        ,	4,	5,	187,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	9,	4,	187,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	13,	4,	187,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRFC"                        ,	17,	5,	187,	"R/W",	0,	0,	6ull,	7ull},
+	{"TRRD"                        ,	22,	3,	187,	"R/W",	0,	0,	2ull,	2ull},
+	{"TXP"                         ,	25,	3,	187,	"R/W",	0,	0,	3ull,	3ull},
+	{"TWLMRD"                      ,	28,	4,	187,	"R/W",	0,	0,	10ull,	10ull},
+	{"TWLDQSEN"                    ,	32,	4,	187,	"R/W",	0,	0,	7ull,	7ull},
+	{"TFAW"                        ,	36,	5,	187,	"R/W",	0,	0,	0ull,	9ull},
+	{"TXPDLL"                      ,	41,	5,	187,	"R/W",	0,	0,	0ull,	10ull},
+	{"TRAS_EXT"                    ,	46,	1,	187,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	187,	"RAZ",	1,	1,	0,	0},
+	{"LANEMASK"                    ,	0,	9,	188,	"R/W",	0,	1,	0ull,	0},
+	{"SSET"                        ,	9,	1,	188,	"R/W",	0,	1,	0ull,	0},
+	{"OR_DIS"                      ,	10,	1,	188,	"R/W",	0,	1,	0ull,	0},
+	{"BITMASK"                     ,	11,	8,	188,	"R/W",	0,	1,	0ull,	0},
+	{"RTT_NOM"                     ,	19,	3,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	188,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	4,	8,	189,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	189,	"RAZ",	1,	1,	0,	0},
+	{"BYTE0"                       ,	0,	5,	190,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	5,	5,	190,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_44"              ,	10,	35,	190,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	45,	2,	190,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_47_63"              ,	47,	17,	190,	"RAZ",	1,	1,	0,	0},
+	{"WODT_D0_R0"                  ,	0,	8,	191,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D0_R1"                  ,	8,	8,	191,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D1_R0"                  ,	16,	8,	191,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D1_R1"                  ,	24,	8,	191,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D2_R0"                  ,	32,	8,	191,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D2_R1"                  ,	40,	8,	191,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D3_R0"                  ,	48,	8,	191,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D3_R1"                  ,	56,	8,	191,	"R/W",	0,	0,	255ull,	255ull},
+	{"BIST"                        ,	0,	47,	192,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	192,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	193,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLK"                         ,	1,	1,	193,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	193,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	194,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	195,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	195,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	6,	196,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	196,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_6"                ,	0,	7,	197,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	7,	29,	197,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	197,	"RAZ",	1,	1,	0,	0},
+	{"IDLE"                        ,	40,	1,	197,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_41_47"              ,	41,	7,	197,	"RAZ",	1,	1,	0,	0},
+	{"CSIZE"                       ,	48,	14,	197,	"R/W",	0,	1,	64ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	197,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	3,	198,	"R/W",	0,	0,	6ull,	6ull},
+	{"RESERVED_3_63"               ,	3,	61,	198,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	199,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	199,	"RAZ",	1,	1,	0,	0},
+	{"STATE"                       ,	0,	64,	200,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	0,	64,	201,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_13"               ,	0,	14,	202,	"RAZ",	1,	1,	0,	0},
+	{"O_MODE"                      ,	14,	1,	202,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ES"                        ,	15,	2,	202,	"R/W",	0,	1,	0ull,	0},
+	{"O_NS"                        ,	17,	1,	202,	"R/W",	0,	1,	0ull,	0},
+	{"O_RO"                        ,	18,	1,	202,	"R/W",	0,	1,	0ull,	0},
+	{"O_ADD1"                      ,	19,	1,	202,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA_QUE"                     ,	20,	3,	202,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_ICHK"                    ,	23,	9,	202,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_DENB"                    ,	32,	1,	202,	"R/W",	0,	0,	0ull,	1ull},
+	{"B0_LEND"                     ,	33,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_47"              ,	34,	14,	202,	"RAZ",	1,	1,	0,	0},
+	{"DMA_ENB"                     ,	48,	6,	202,	"R/W",	0,	0,	0ull,	63ull},
+	{"RESERVED_54_55"              ,	54,	2,	202,	"RAZ",	1,	1,	0,	0},
+	{"PKT_EN"                      ,	56,	1,	202,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_HP"                      ,	57,	1,	202,	"RO",	0,	0,	0ull,	0ull},
+	{"COMMIT_MODE"                 ,	58,	1,	202,	"R/W",	0,	0,	0ull,	1ull},
+	{"FFP_DIS"                     ,	59,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_EN1"                     ,	60,	1,	202,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_61_63"              ,	61,	3,	202,	"RAZ",	1,	1,	0,	0},
+	{"QEN"                         ,	0,	8,	203,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	203,	"RAZ",	1,	1,	0,	0},
+	{"BLKS"                        ,	0,	4,	204,	"R/W",	0,	1,	2ull,	0},
+	{"BASE"                        ,	4,	5,	204,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_31"               ,	9,	23,	204,	"RAZ",	1,	1,	0,	0},
+	{"COMPBLKS"                    ,	32,	5,	204,	"RO",	1,	1,	0,	0},
+	{"RESERVED_37_63"              ,	37,	27,	204,	"RAZ",	1,	1,	0,	0},
+	{"RSL"                         ,	0,	1,	205,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NCB"                         ,	1,	1,	205,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	205,	"RAZ",	1,	1,	0,	0},
+	{"FFP"                         ,	4,	4,	205,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	205,	"RAZ",	1,	1,	0,	0},
+	{"NDERR"                       ,	0,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFOVR"                       ,	1,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMADBO"                      ,	8,	8,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADADR"                  ,	16,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADLEN"                  ,	17,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_OVRFLW"                  ,	18,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_UNDFLW"                  ,	19,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_ANULL"                   ,	20,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_INULL"                   ,	21,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADFIL"                  ,	22,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	206,	"R/W",	1,	1,	0,	0},
+	{"SPRT0_RST"                   ,	24,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_RST"                   ,	25,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT2_RST"                   ,	26,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT3_RST"                   ,	27,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	206,	"RAZ",	1,	1,	0,	0},
+	{"NDERR"                       ,	0,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFOVR"                       ,	1,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	207,	"RAZ",	1,	1,	0,	0},
+	{"DMADBO"                      ,	8,	8,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADADR"                  ,	16,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADLEN"                  ,	17,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_OVRFLW"                  ,	18,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_UNDFLW"                  ,	19,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_ANULL"                   ,	20,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_INULL"                   ,	21,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADFIL"                  ,	22,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	207,	"RAZ",	1,	1,	0,	0},
+	{"SPRT0_RST"                   ,	24,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT1_RST"                   ,	25,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT2_RST"                   ,	26,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT3_RST"                   ,	27,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	207,	"RAZ",	1,	1,	0,	0},
+	{"MOLR"                        ,	0,	6,	208,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	208,	"RAZ",	1,	1,	0,	0},
+	{"SINFO"                       ,	0,	6,	209,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	209,	"RAZ",	1,	1,	0,	0},
+	{"IINFO"                       ,	8,	6,	209,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	209,	"RAZ",	1,	1,	0,	0},
+	{"PKTERR"                      ,	0,	1,	210,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	210,	"RAZ",	1,	1,	0,	0},
+	{"QERR"                        ,	0,	8,	211,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	211,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	212,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	212,	"RAZ",	1,	1,	0,	0},
+	{"QERR"                        ,	0,	8,	213,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	213,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	214,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	214,	"RAZ",	1,	1,	0,	0},
+	{"EN_RSP"                      ,	0,	8,	215,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	215,	"RAZ",	1,	1,	0,	0},
+	{"EN_RST"                      ,	16,	8,	215,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	215,	"RAZ",	1,	1,	0,	0},
+	{"QEN"                         ,	0,	8,	216,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	216,	"RAZ",	1,	1,	0,	0},
+	{"MRRS"                        ,	0,	2,	217,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	217,	"RAZ",	1,	1,	0,	0},
+	{"MRRS_LIM"                    ,	3,	1,	217,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPS"                         ,	4,	1,	217,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	217,	"RAZ",	1,	1,	0,	0},
+	{"MPS_LIM"                     ,	7,	1,	217,	"R/W",	0,	0,	0ull,	0ull},
+	{"MOLR"                        ,	8,	6,	217,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	217,	"RAZ",	1,	1,	0,	0},
+	{"RD_MODE"                     ,	16,	1,	217,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	217,	"RAZ",	1,	1,	0,	0},
+	{"QLM_CFG"                     ,	20,	4,	217,	"RO",	1,	1,	0,	0},
+	{"HALT"                        ,	24,	1,	217,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	217,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	218,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	61,	218,	"RO",	0,	1,	0ull,	0},
+	{"REQQ"                        ,	0,	3,	219,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	219,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	4,	1,	219,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	219,	"RAZ",	1,	1,	0,	0},
+	{"LOCK"                        ,	8,	1,	219,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	219,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	33,	220,	"RO",	0,	1,	0ull,	0},
+	{"POOL"                        ,	33,	5,	220,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	220,	"RAZ",	1,	1,	0,	0},
+	{"FDR"                         ,	0,	1,	221,	"RO",	0,	0,	0ull,	0ull},
+	{"FFR"                         ,	1,	1,	221,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF1"                        ,	2,	1,	221,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF0"                        ,	3,	1,	221,	"RO",	0,	0,	0ull,	0ull},
+	{"FRD"                         ,	4,	1,	221,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	221,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	14,	1,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_STT"                     ,	15,	1,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_LDT"                     ,	16,	1,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_OFF"                     ,	18,	1,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"RET_OFF"                     ,	19,	1,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE_EN"                     ,	20,	1,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	222,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	11,	223,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	11,	11,	223,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	223,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	11,	224,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	224,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	12,	225,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	12,	12,	225,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	225,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	12,	226,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	226,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL0TH"                     ,	28,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL1TH"                     ,	29,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL2TH"                     ,	30,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL3TH"                     ,	31,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL4TH"                     ,	32,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL5TH"                     ,	33,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL6TH"                     ,	34,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL7TH"                     ,	35,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE0"                       ,	36,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE1"                       ,	37,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE2"                       ,	38,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE3"                       ,	39,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE4"                       ,	40,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE5"                       ,	41,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE6"                       ,	42,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE7"                       ,	43,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"RES_44"                      ,	44,	5,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"PADDR_E"                     ,	49,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_63"              ,	50,	14,	227,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL0TH"                     ,	28,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL1TH"                     ,	29,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL2TH"                     ,	30,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL3TH"                     ,	31,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL4TH"                     ,	32,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL5TH"                     ,	33,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL6TH"                     ,	34,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL7TH"                     ,	35,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE0"                       ,	36,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE1"                       ,	37,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE2"                       ,	38,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE3"                       ,	39,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE4"                       ,	40,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE5"                       ,	41,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE6"                       ,	42,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE7"                       ,	43,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_48"              ,	44,	5,	228,	"RAZ",	1,	1,	0,	0},
+	{"PADDR_E"                     ,	49,	1,	228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_63"              ,	50,	14,	228,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	32,	229,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	229,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	33,	230,	"R/W",	0,	1,	8589934591ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	230,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	33,	231,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	231,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	29,	232,	"R/W",	0,	0,	536870911ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	232,	"RAZ",	1,	1,	0,	0},
+	{"QUE_SIZ"                     ,	0,	29,	233,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	233,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	234,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	234,	"RAZ",	1,	1,	0,	0},
+	{"ACT_INDX"                    ,	0,	26,	235,	"RO",	0,	1,	0ull,	0},
+	{"ACT_QUE"                     ,	26,	3,	235,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	235,	"RO",	0,	0,	0ull,	7ull},
+	{"EXP_INDX"                    ,	0,	26,	236,	"RO",	0,	1,	0ull,	0},
+	{"EXP_QUE"                     ,	26,	3,	236,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	236,	"RO",	0,	0,	0ull,	7ull},
+	{"THRESH"                      ,	0,	32,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	237,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	238,	"RAZ",	1,	1,	0,	0},
+	{"OUT_OVR"                     ,	2,	4,	238,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_21"               ,	6,	16,	238,	"RAZ",	1,	1,	0,	0},
+	{"LOSTSTAT"                    ,	22,	4,	238,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	238,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INB_NXA"                     ,	27,	4,	238,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	238,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	25,	239,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	239,	"RAZ",	1,	1,	0,	0},
+	{"CLK_EN"                      ,	0,	1,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	240,	"RAZ",	1,	1,	0,	0},
+	{"LOGL_EN"                     ,	0,	16,	241,	"R/W",	0,	1,	65535ull,	0},
+	{"PHYS_EN"                     ,	16,	1,	241,	"R/W",	0,	1,	1ull,	0},
+	{"HG2RX_EN"                    ,	17,	1,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2TX_EN"                    ,	18,	1,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	241,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	1,	242,	"RO",	0,	1,	0ull,	0},
+	{"EN"                          ,	1,	1,	242,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_3"                ,	2,	2,	242,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	4,	1,	242,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	242,	"RAZ",	1,	1,	0,	0},
+	{"SPEED"                       ,	8,	4,	242,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_15"              ,	12,	4,	242,	"RAZ",	1,	1,	0,	0},
+	{"RATE"                        ,	16,	4,	242,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_20_63"              ,	20,	44,	242,	"RAZ",	1,	1,	0,	0},
+	{"PRT"                         ,	0,	6,	243,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	243,	"RAZ",	1,	1,	0,	0},
+	{"RX_EN"                       ,	0,	1,	244,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_EN"                       ,	1,	1,	244,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRP_EN"                      ,	2,	1,	244,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCK_EN"                      ,	3,	1,	244,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	244,	"RAZ",	1,	1,	0,	0},
+	{"PHYS_BP"                     ,	16,	16,	244,	"R/W",	0,	1,	65535ull,	0},
+	{"LOGL_EN"                     ,	32,	16,	244,	"R/W",	0,	0,	255ull,	255ull},
+	{"PHYS_EN"                     ,	48,	16,	244,	"R/W",	0,	0,	255ull,	255ull},
+	{"EN"                          ,	0,	1,	245,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	245,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	245,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	245,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	245,	"RAZ",	1,	1,	0,	0},
+	{"SPEED_MSB"                   ,	8,	1,	245,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	245,	"RAZ",	1,	1,	0,	0},
+	{"RX_IDLE"                     ,	12,	1,	245,	"RO",	0,	1,	1ull,	0},
+	{"TX_IDLE"                     ,	13,	1,	245,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	245,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	246,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	247,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	248,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	249,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	250,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	251,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	32,	252,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	252,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	253,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	253,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	254,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	254,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	254,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	254,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	255,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	255,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	256,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	256,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_2"                ,	2,	1,	256,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	256,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	256,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_6"                ,	5,	2,	256,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	256,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	256,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	256,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	257,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	257,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	257,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	257,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	257,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	257,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	257,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_8"                ,	7,	2,	257,	"RAZ",	1,	1,	0,	0},
+	{"PRE_ALIGN"                   ,	9,	1,	257,	"R/W",	0,	0,	0ull,	0ull},
+	{"NULL_DIS"                    ,	10,	1,	257,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	257,	"RAZ",	1,	1,	0,	0},
+	{"PTP_MODE"                    ,	12,	1,	257,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	257,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	258,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	258,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	259,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	259,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	259,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	259,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	259,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	260,	"R/W1C",	0,	1,	0ull,	0},
+	{"CAREXT"                      ,	1,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	260,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	260,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	260,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	260,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	260,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	261,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	261,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	262,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	262,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	263,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	263,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	264,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	264,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	265,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	265,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	266,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	266,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	267,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	267,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	268,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	268,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	269,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	269,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	270,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	270,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	271,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	271,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	272,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	272,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	273,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	273,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	274,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	274,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	275,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	275,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	276,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_9_63"               ,	9,	55,	276,	"RAZ",	1,	1,	0,	0},
+	{"LGTIM2GO"                    ,	0,	16,	277,	"RO",	0,	1,	0ull,	0},
+	{"XOF"                         ,	16,	16,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"PHTIM2GO"                    ,	32,	16,	277,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	277,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	4,	278,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	278,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	4,	278,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	278,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	3,	279,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_3_63"               ,	3,	61,	279,	"RAZ",	1,	1,	0,	0},
+	{"LANE_RXD"                    ,	0,	32,	280,	"RO",	0,	1,	0ull,	0},
+	{"LANE_RXC"                    ,	32,	4,	280,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	3,	280,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	39,	1,	280,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	280,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	2,	281,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	281,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	282,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	282,	"RAZ",	1,	1,	0,	0},
+	{"CLEAR_BIST"                  ,	0,	1,	283,	"R/W",	0,	1,	0ull,	0},
+	{"START_BIST"                  ,	1,	1,	283,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	283,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	284,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	284,	"RAZ",	1,	1,	0,	0},
+	{"WR_MAGIC"                    ,	0,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	285,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	286,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	286,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	286,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	286,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	286,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	16,	287,	"R/W",	0,	0,	8192ull,	8192ull},
+	{"RESERVED_16_63"              ,	16,	48,	287,	"RAZ",	1,	1,	0,	0},
+	{"XOFF"                        ,	0,	16,	288,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	288,	"RAZ",	1,	1,	0,	0},
+	{"XON"                         ,	0,	16,	289,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	289,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	290,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	290,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	290,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	291,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	291,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	292,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	292,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	293,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	293,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	294,	"RO",	1,	1,	0,	0},
+	{"MSG_TIME"                    ,	16,	16,	294,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	294,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	295,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	295,	"RAZ",	1,	1,	0,	0},
+	{"ALIGN"                       ,	0,	1,	296,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	296,	"RAZ",	1,	1,	0,	0},
+	{"SLOT"                        ,	0,	10,	297,	"R/W",	0,	0,	512ull,	512ull},
+	{"RESERVED_10_63"              ,	10,	54,	297,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	298,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	298,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	299,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	299,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	300,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	300,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	301,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	301,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	302,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	302,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	303,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	303,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	304,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	304,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	305,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	305,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	306,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	306,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	307,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	307,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	308,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	308,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	309,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	9,	310,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_9_63"               ,	9,	55,	310,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	4,	311,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	311,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	312,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	312,	"RAZ",	1,	1,	0,	0},
+	{"CORRUPT"                     ,	0,	4,	313,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_4_63"               ,	4,	60,	313,	"RAZ",	1,	1,	0,	0},
+	{"TX_XOF"                      ,	0,	16,	314,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	314,	"RAZ",	1,	1,	0,	0},
+	{"TX_XON"                      ,	0,	16,	315,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	315,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	316,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	316,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	316,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	317,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	317,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTP_LOST"                    ,	20,	4,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"XCHANGE"                     ,	24,	1,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	317,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	318,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	318,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	318,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	318,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	318,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	318,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	318,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTP_LOST"                    ,	20,	4,	318,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XCHANGE"                     ,	24,	1,	318,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	318,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	319,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	319,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	320,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	320,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	4,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	4,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	4,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	321,	"RAZ",	1,	1,	0,	0},
+	{"TX_PRT_BP"                   ,	32,	16,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	321,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	322,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	322,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	323,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	323,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	5,	324,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	324,	"RAZ",	1,	1,	0,	0},
+	{"DIC_EN"                      ,	0,	1,	325,	"R/W",	0,	0,	0ull,	1ull},
+	{"UNI_EN"                      ,	1,	1,	325,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	325,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	4,	2,	325,	"R/W",	0,	0,	0ull,	0ull},
+	{"LS_BYP"                      ,	6,	1,	325,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	325,	"RAZ",	1,	1,	0,	0},
+	{"HG_EN"                       ,	8,	1,	325,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_PAUSE_HGI"                ,	9,	2,	325,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_11_63"              ,	11,	53,	325,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	4,	326,	"R/W",	0,	0,	6ull,	6ull},
+	{"EN"                          ,	4,	1,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	326,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_SEL"                     ,	12,	2,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_GEN"                     ,	14,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"SYNCE_SEL"                   ,	15,	2,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	327,	"RAZ",	1,	1,	0,	0},
+	{"N"                           ,	0,	32,	328,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	328,	"RAZ",	1,	1,	0,	0},
+	{"LANE_SEL"                    ,	0,	2,	329,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIV"                         ,	2,	1,	329,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	329,	"RAZ",	1,	1,	0,	0},
+	{"QLM_SEL"                     ,	8,	2,	329,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	329,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	330,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	330,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_17"               ,	0,	18,	331,	"RAZ",	1,	1,	0,	0},
+	{"ENA18"                       ,	18,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA19"                       ,	19,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	331,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	20,	332,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	332,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	20,	333,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	333,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	20,	334,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	334,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_SEL"                     ,	12,	2,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_GEN"                     ,	14,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"SYNCE_SEL"                   ,	15,	2,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	335,	"RAZ",	1,	1,	0,	0},
+	{"ICD"                         ,	0,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"IBD"                         ,	1,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP1"                       ,	2,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP0"                       ,	3,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN1"                       ,	4,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN0"                       ,	5,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ1"                       ,	6,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ0"                       ,	7,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRT"                       ,	8,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR1"                        ,	9,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR0"                        ,	10,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR1"                       ,	11,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR0"                       ,	12,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR0"                       ,	13,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR1"                       ,	14,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR1"                        ,	15,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR0"                        ,	16,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRCB"                      ,	17,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"IOCFIF"                      ,	18,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"RSDFIF"                      ,	19,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"IORFIF"                      ,	20,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"XMCFIF"                      ,	21,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"XMDFIF"                      ,	22,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	336,	"RAZ",	1,	1,	0,	0},
+	{"FAU_END"                     ,	0,	1,	337,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB_ENB"                     ,	1,	1,	337,	"R/W",	0,	0,	1ull,	1ull},
+	{"PKO_ENB"                     ,	2,	1,	337,	"R/W",	0,	0,	0ull,	0ull},
+	{"INB_MAT"                     ,	3,	1,	337,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTB_MAT"                    ,	4,	1,	337,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RR_MODE"                     ,	5,	1,	337,	"R/W",	0,	0,	0ull,	0ull},
+	{"XMC_PER"                     ,	6,	4,	337,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIF_DLY"                     ,	10,	1,	337,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	337,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	338,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	338,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	338,	"RAZ",	1,	1,	0,	0},
+	{"TOUT_VAL"                    ,	0,	12,	339,	"R/W",	0,	0,	4ull,	4ull},
+	{"TOUT_ENB"                    ,	12,	1,	339,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	339,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	340,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	340,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	340,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	341,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	341,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	341,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	341,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	341,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	342,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	342,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	342,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	342,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	342,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	343,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	344,	"R/W",	0,	1,	0ull,	0},
+	{"NP_SOP"                      ,	0,	1,	345,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	345,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	345,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	345,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	345,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	345,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	345,	"RAZ",	1,	1,	0,	0},
+	{"NP_SOP"                      ,	0,	1,	346,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	346,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	346,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	346,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	346,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	346,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	346,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	347,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	347,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	347,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	348,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	348,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	348,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	349,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	349,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	349,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	350,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	350,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	350,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	350,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	350,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	351,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	351,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	351,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	351,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	351,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	352,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	353,	"R/W",	0,	1,	0ull,	0},
+	{"CNT_VAL"                     ,	0,	15,	354,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	354,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	354,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	355,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	355,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	355,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	356,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	356,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	356,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	6,	357,	"RO",	0,	1,	0ull,	0},
+	{"VPORT"                       ,	6,	6,	357,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	357,	"RAZ",	1,	1,	0,	0},
+	{"NCB_WR"                      ,	0,	3,	358,	"R/W",	0,	1,	0ull,	0},
+	{"NCB_RD"                      ,	3,	3,	358,	"R/W",	0,	1,	0ull,	0},
+	{"PKO_RD"                      ,	6,	3,	358,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	358,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	359,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	359,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	360,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	360,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	361,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	361,	"RAZ",	1,	1,	0,	0},
+	{"PWP"                         ,	0,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_NEW"                     ,	1,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_OLD"                     ,	2,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"PRC_OFF"                     ,	3,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ0"                        ,	4,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ1"                        ,	5,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM_WORD"                    ,	6,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM0"                        ,	7,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM1"                        ,	8,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM2"                        ,	9,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM3"                        ,	10,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE0"                    ,	11,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE1"                    ,	12,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_POW"                     ,	13,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WP1"                     ,	14,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WQED"                    ,	15,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_NCMD"                    ,	16,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_MEM"                     ,	17,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	362,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	48,	363,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	363,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	64,	364,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_EN"                      ,	0,	1,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC_MODE"                    ,	1,	2,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBP_EN"                      ,	3,	1,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"WQE_LEND"                    ,	4,	1,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_LEND"                    ,	5,	1,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"NADDBUF"                     ,	6,	1,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDPKT"                      ,	7,	1,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	8,	1,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_M8"                      ,	9,	1,	365,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKT_OFF"                     ,	10,	1,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_FULL"                    ,	11,	1,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_NABUF"                    ,	12,	1,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_APKT"                     ,	13,	1,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"NO_WPTR"                     ,	14,	1,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKEN"                       ,	15,	1,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"RST_DONE"                    ,	16,	1,	365,	"RO",	0,	0,	1ull,	0ull},
+	{"USE_SOP"                     ,	17,	1,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	365,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	366,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	367,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	367,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	367,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	367,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	367,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	367,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	367,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	367,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	367,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	367,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	367,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	367,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	367,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	368,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	368,	"RAZ",	1,	1,	0,	0},
+	{"MB_SIZE"                     ,	0,	12,	369,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_12_63"              ,	12,	52,	369,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	370,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	370,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	371,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	371,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	371,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	372,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	372,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	372,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	373,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	373,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	373,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	374,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	374,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	375,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	375,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	376,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	376,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	377,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	377,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	378,	"RO",	0,	1,	0ull,	0},
+	{"WMARK"                       ,	32,	32,	378,	"R/W",	0,	1,	4294967295ull,	0},
+	{"INTR"                        ,	0,	64,	379,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	64,	380,	"R/W",	0,	0,	0ull,	1ull},
+	{"RADDR"                       ,	0,	3,	381,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	3,	1,	381,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	4,	29,	381,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	33,	3,	381,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	36,	3,	381,	"RO",	0,	0,	5ull,	5ull},
+	{"RESERVED_39_63"              ,	39,	25,	381,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	7,	382,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	7,	1,	382,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	8,	29,	382,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	37,	7,	382,	"RO",	0,	0,	64ull,	64ull},
+	{"RESERVED_44_63"              ,	44,	20,	382,	"RAZ",	1,	1,	0,	0},
+	{"WQE_PCNT"                    ,	0,	7,	383,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PCNT"                    ,	7,	7,	383,	"RO",	0,	0,	0ull,	0ull},
+	{"PFIF_CNT"                    ,	14,	3,	383,	"RO",	0,	0,	0ull,	0ull},
+	{"WQEV_CNT"                    ,	17,	1,	383,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTV_CNT"                    ,	18,	1,	383,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	383,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	8,	384,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	8,	1,	384,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	9,	29,	384,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	38,	8,	384,	"RO",	1,	1,	0,	0},
+	{"WRADDR"                      ,	46,	8,	384,	"RO",	1,	1,	0,	0},
+	{"MAX_CNTS"                    ,	54,	7,	384,	"RO",	0,	0,	64ull,	64ull},
+	{"RESERVED_61_63"              ,	61,	3,	384,	"RAZ",	1,	1,	0,	0},
+	{"PASS"                        ,	0,	32,	385,	"R/W",	0,	1,	0ull,	0},
+	{"DROP"                        ,	32,	32,	385,	"R/W",	0,	1,	0ull,	0},
+	{"Q0_PCNT"                     ,	0,	32,	386,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	386,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	387,	"R/W",	0,	0,	0ull,	0ull},
+	{"AVG_DLY"                     ,	36,	14,	387,	"R/W",	0,	1,	0ull,	0},
+	{"PRB_DLY"                     ,	50,	14,	387,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRT_ENB"                     ,	0,	12,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	388,	"RAZ",	1,	1,	0,	0},
+	{"PRB_CON"                     ,	0,	32,	389,	"R/W",	0,	1,	0ull,	0},
+	{"AVG_CON"                     ,	32,	8,	389,	"R/W",	0,	1,	0ull,	0},
+	{"NEW_CON"                     ,	40,	8,	389,	"R/W",	0,	1,	0ull,	0},
+	{"USE_PCNT"                    ,	48,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	389,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	25,	390,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	25,	6,	390,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	390,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT"                    ,	0,	32,	391,	"R/W",	0,	0,	4294967295ull,	4294967295ull},
+	{"RESERVED_32_35"              ,	32,	4,	391,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT2"                   ,	36,	4,	391,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_40_63"              ,	40,	24,	391,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	392,	"R/W",	1,	0,	0,	0ull},
+	{"PORT_QOS"                    ,	32,	9,	392,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_41_63"              ,	41,	23,	392,	"RAZ",	1,	1,	0,	0},
+	{"WQE_POOL"                    ,	0,	3,	393,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	393,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	394,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	394,	"RAZ",	1,	1,	0,	0},
+	{"MEM0"                        ,	0,	1,	395,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM1"                        ,	1,	1,	395,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	2,	1,	395,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	395,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	396,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	397,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	397,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	397,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	397,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	397,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	398,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	398,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	398,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	398,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	398,	"RAZ",	1,	1,	0,	0},
+	{"DISABLE"                     ,	0,	1,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	399,	"RAZ",	1,	1,	0,	0},
+	{"MAXDRAM"                     ,	4,	4,	399,	"R/W",	0,	0,	7ull,	7ull},
+	{"RESERVED_8_63"               ,	8,	56,	399,	"RAZ",	1,	1,	0,	0},
+	{"TDFFL"                       ,	0,	1,	400,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	400,	"RAZ",	1,	1,	0,	0},
+	{"VRTFL"                       ,	4,	1,	400,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	400,	"RAZ",	1,	1,	0,	0},
+	{"DUTRESFL"                    ,	8,	1,	400,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	400,	"RAZ",	1,	1,	0,	0},
+	{"IOCDATFL"                    ,	12,	1,	400,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	400,	"RAZ",	1,	1,	0,	0},
+	{"IOCCMDFL"                    ,	16,	1,	400,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	400,	"RAZ",	1,	1,	0,	0},
+	{"DUTFL"                       ,	32,	10,	400,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	400,	"RAZ",	1,	1,	0,	0},
+	{"VBFFL"                       ,	0,	4,	401,	"RO",	1,	0,	0,	0ull},
+	{"RDFFL"                       ,	4,	1,	401,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_5_61"               ,	5,	57,	401,	"RAZ",	1,	1,	0,	0},
+	{"CLEAR_BIST"                  ,	62,	1,	401,	"R/W",	0,	0,	0ull,	0ull},
+	{"START_BIST"                  ,	63,	1,	401,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFL"                       ,	0,	8,	402,	"RO",	1,	0,	0,	0ull},
+	{"FBFFL"                       ,	8,	8,	402,	"RO",	1,	0,	0,	0ull},
+	{"SBFFL"                       ,	16,	8,	402,	"RO",	1,	0,	0,	0ull},
+	{"FBFRSPFL"                    ,	24,	8,	402,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	402,	"RAZ",	1,	1,	0,	0},
+	{"TAGFL"                       ,	0,	16,	403,	"RO",	1,	0,	0,	0ull},
+	{"LRUFL"                       ,	16,	1,	403,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	403,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	404,	"R/W",	1,	1,	0,	0},
+	{"DISIDXALIAS"                 ,	0,	1,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISECC"                      ,	1,	1,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"VAB_THRESH"                  ,	2,	4,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"EF_CNT"                      ,	6,	7,	405,	"R/W",	0,	0,	0ull,	4ull},
+	{"EF_ENA"                      ,	13,	1,	405,	"R/W",	0,	0,	0ull,	1ull},
+	{"XMC_ARB_MODE"                ,	14,	1,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSP_ARB_MODE"                ,	15,	1,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXLFB"                      ,	16,	4,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXVAB"                      ,	20,	4,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISCCLK"                     ,	24,	1,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFDBE"                     ,	25,	1,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFSBE"                     ,	26,	1,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISSTGL2I"                   ,	27,	1,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDF_FAST"                    ,	28,	1,	405,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_29_63"              ,	29,	35,	405,	"RAZ",	1,	1,	0,	0},
+	{"VALID"                       ,	0,	1,	406,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_9"                ,	1,	9,	406,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	10,	28,	406,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	406,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	2,	407,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	407,	"RAZ",	1,	1,	0,	0},
+	{"WAYIDX"                      ,	4,	17,	407,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_21_49"              ,	21,	29,	407,	"RAZ",	1,	1,	0,	0},
+	{"SYN"                         ,	50,	10,	407,	"RO",	0,	0,	0ull,	0ull},
+	{"VSBE"                        ,	60,	1,	407,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VDBE"                        ,	61,	1,	407,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE"                         ,	62,	1,	407,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	63,	1,	407,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TYPE"                        ,	0,	2,	408,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_6"                ,	2,	5,	408,	"RAZ",	1,	1,	0,	0},
+	{"WAYIDX"                      ,	7,	14,	408,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_21_49"              ,	21,	29,	408,	"RAZ",	1,	1,	0,	0},
+	{"SYN"                         ,	50,	6,	408,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_60"              ,	56,	5,	408,	"RAZ",	1,	1,	0,	0},
+	{"NOWAY"                       ,	61,	1,	408,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE"                         ,	62,	1,	408,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	63,	1,	408,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TYPE"                        ,	0,	2,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_49"               ,	2,	48,	409,	"RAZ",	1,	1,	0,	0},
+	{"VSYN"                        ,	50,	10,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"VSBE"                        ,	60,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"VDBE"                        ,	61,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	409,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	38,	410,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_47"              ,	38,	10,	410,	"RAZ",	1,	1,	0,	0},
+	{"SID"                         ,	48,	5,	410,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_53_57"              ,	53,	5,	410,	"RAZ",	1,	1,	0,	0},
+	{"CMD"                         ,	58,	6,	410,	"RO",	0,	1,	0ull,	0},
+	{"HOLERD"                      ,	0,	1,	411,	"R/W",	0,	0,	0ull,	1ull},
+	{"HOLEWR"                      ,	1,	1,	411,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTWR"                       ,	2,	1,	411,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTIDRNG"                    ,	3,	1,	411,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTADRNG"                    ,	4,	1,	411,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTPE"                       ,	5,	1,	411,	"R/W",	0,	0,	0ull,	1ull},
+	{"BIGWR"                       ,	6,	1,	411,	"R/W",	0,	0,	0ull,	1ull},
+	{"BIGRD"                       ,	7,	1,	411,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_8_63"               ,	8,	56,	411,	"RAZ",	1,	1,	0,	0},
+	{"HOLERD"                      ,	0,	1,	412,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HOLEWR"                      ,	1,	1,	412,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTWR"                       ,	2,	1,	412,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTIDRNG"                    ,	3,	1,	412,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTADRNG"                    ,	4,	1,	412,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTPE"                       ,	5,	1,	412,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BIGWR"                       ,	6,	1,	412,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BIGRD"                       ,	7,	1,	412,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	412,	"RAZ",	1,	1,	0,	0},
+	{"TAD0"                        ,	16,	1,	412,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	412,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	413,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	414,	"R/W",	0,	1,	0ull,	0},
+	{"LVL"                         ,	0,	2,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	415,	"RAZ",	1,	1,	0,	0},
+	{"DWBLVL"                      ,	4,	2,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	415,	"RAZ",	1,	1,	0,	0},
+	{"LVL"                         ,	0,	2,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	416,	"RAZ",	1,	1,	0,	0},
+	{"WGT0"                        ,	0,	8,	417,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT1"                        ,	8,	8,	417,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT2"                        ,	16,	8,	417,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT3"                        ,	24,	8,	417,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_32_63"              ,	32,	32,	417,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	418,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	419,	"R/W",	0,	1,	0ull,	0},
+	{"OW0ECC"                      ,	0,	10,	420,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	420,	"RAZ",	1,	1,	0,	0},
+	{"OW1ECC"                      ,	16,	10,	420,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_31"              ,	26,	6,	420,	"RAZ",	1,	1,	0,	0},
+	{"OW2ECC"                      ,	32,	10,	420,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	420,	"RAZ",	1,	1,	0,	0},
+	{"OW3ECC"                      ,	48,	10,	420,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	420,	"RAZ",	1,	1,	0,	0},
+	{"OW4ECC"                      ,	0,	10,	421,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	421,	"RAZ",	1,	1,	0,	0},
+	{"OW5ECC"                      ,	16,	10,	421,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_31"              ,	26,	6,	421,	"RAZ",	1,	1,	0,	0},
+	{"OW6ECC"                      ,	32,	10,	421,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	421,	"RAZ",	1,	1,	0,	0},
+	{"OW7ECC"                      ,	48,	10,	421,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	421,	"RAZ",	1,	1,	0,	0},
+	{"L2DSBE"                      ,	0,	1,	422,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2DDBE"                      ,	1,	1,	422,	"R/W",	0,	0,	0ull,	1ull},
+	{"TAGSBE"                      ,	2,	1,	422,	"R/W",	0,	0,	0ull,	1ull},
+	{"TAGDBE"                      ,	3,	1,	422,	"R/W",	0,	0,	0ull,	1ull},
+	{"VBFSBE"                      ,	4,	1,	422,	"R/W",	0,	0,	0ull,	1ull},
+	{"VBFDBE"                      ,	5,	1,	422,	"R/W",	0,	0,	0ull,	1ull},
+	{"NOWAY"                       ,	6,	1,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDDISLMC"                    ,	7,	1,	422,	"R/W",	0,	0,	0ull,	1ull},
+	{"WRDISLMC"                    ,	8,	1,	422,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	422,	"RAZ",	1,	1,	0,	0},
+	{"L2DSBE"                      ,	0,	1,	423,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"L2DDBE"                      ,	1,	1,	423,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"TAGSBE"                      ,	2,	1,	423,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"TAGDBE"                      ,	3,	1,	423,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"VBFSBE"                      ,	4,	1,	423,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"VBFDBE"                      ,	5,	1,	423,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"NOWAY"                       ,	6,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDDISLMC"                    ,	7,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WRDISLMC"                    ,	8,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	423,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	424,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	425,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	426,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	427,	"R/W",	0,	1,	0ull,	0},
+	{"CNT0SEL"                     ,	0,	8,	428,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT1SEL"                     ,	8,	8,	428,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT2SEL"                     ,	16,	8,	428,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT3SEL"                     ,	24,	8,	428,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	428,	"RAZ",	1,	1,	0,	0},
+	{"LOCK"                        ,	0,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIRTY"                       ,	1,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"VALID"                       ,	2,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE"                         ,	3,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_16"               ,	4,	13,	429,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	17,	19,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_39"              ,	36,	4,	429,	"RAZ",	1,	1,	0,	0},
+	{"ECC"                         ,	40,	6,	429,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_46_63"              ,	46,	18,	429,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	430,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MASK"                        ,	0,	1,	431,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	431,	"RAZ",	1,	1,	0,	0},
+	{"DWB"                         ,	0,	1,	432,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	1,	1,	432,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	432,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	10,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	433,	"RAZ",	1,	1,	0,	0},
+	{"ID"                          ,	0,	6,	434,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	434,	"RAZ",	1,	1,	0,	0},
+	{"DWBID"                       ,	8,	6,	434,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	434,	"RAZ",	1,	1,	0,	0},
+	{"ID"                          ,	0,	6,	435,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	435,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	1,	436,	"R/W",	0,	0,	0ull,	1ull},
+	{"NUMID"                       ,	1,	3,	436,	"R/W",	0,	0,	5ull,	5ull},
+	{"MEMSZ"                       ,	4,	3,	436,	"R/W",	0,	0,	5ull,	5ull},
+	{"RESERVED_7_7"                ,	7,	1,	436,	"RAZ",	1,	1,	0,	0},
+	{"OOBERR"                      ,	8,	1,	436,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	436,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	32,	437,	"R/W",	0,	0,	0ull,	0ull},
+	{"PARITY"                      ,	32,	4,	437,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	437,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	438,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	439,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	439,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	440,	"R/W",	0,	1,	0ull,	0},
+	{"ADDR"                        ,	0,	38,	441,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_38_56"              ,	38,	19,	441,	"RAZ",	1,	1,	0,	0},
+	{"CMD"                         ,	57,	6,	441,	"R/W",	1,	1,	0,	0},
+	{"INUSE"                       ,	63,	1,	441,	"RO",	0,	0,	0ull,	0ull},
+	{"COUNT"                       ,	0,	64,	442,	"R/W",	0,	1,	0ull,	0},
+	{"PRBS"                        ,	0,	32,	443,	"R/W",	1,	1,	0,	0},
+	{"PROG"                        ,	32,	8,	443,	"R/W",	1,	1,	0,	0},
+	{"SEL"                         ,	40,	1,	443,	"R/W",	1,	1,	0,	0},
+	{"EN"                          ,	41,	1,	443,	"R/W",	1,	1,	0,	0},
+	{"SKEW_ON"                     ,	42,	1,	443,	"R/W",	1,	1,	0,	0},
+	{"DR"                          ,	43,	1,	443,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_44_63"              ,	44,	20,	443,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	444,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	8,	445,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	445,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	446,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	8,	447,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	447,	"R/W",	1,	1,	0,	0},
+	{"CKE_MASK"                    ,	0,	2,	448,	"R/W",	1,	1,	0,	0},
+	{"CS0_N_MASK"                  ,	2,	2,	448,	"R/W",	1,	1,	0,	0},
+	{"CS1_N_MASK"                  ,	4,	2,	448,	"R/W",	1,	1,	0,	0},
+	{"ODT0_MASK"                   ,	6,	2,	448,	"R/W",	1,	1,	0,	0},
+	{"ODT1_MASK"                   ,	8,	2,	448,	"R/W",	1,	1,	0,	0},
+	{"RAS_N_MASK"                  ,	10,	1,	448,	"R/W",	1,	1,	0,	0},
+	{"CAS_N_MASK"                  ,	11,	1,	448,	"R/W",	1,	1,	0,	0},
+	{"WE_N_MASK"                   ,	12,	1,	448,	"R/W",	1,	1,	0,	0},
+	{"BA_MASK"                     ,	13,	3,	448,	"R/W",	1,	1,	0,	0},
+	{"A_MASK"                      ,	16,	16,	448,	"R/W",	1,	1,	0,	0},
+	{"RESET_N_MASK"                ,	32,	1,	448,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_33_63"              ,	33,	31,	448,	"R/W",	1,	1,	0,	0},
+	{"DQX_CTL"                     ,	0,	4,	449,	"R/W",	0,	1,	4ull,	0},
+	{"CK_CTL"                      ,	4,	4,	449,	"R/W",	0,	1,	4ull,	0},
+	{"CMD_CTL"                     ,	8,	4,	449,	"R/W",	0,	1,	4ull,	0},
+	{"RODT_CTL"                    ,	12,	4,	449,	"R/W",	0,	1,	0ull,	0},
+	{"NTUNE"                       ,	16,	4,	449,	"R/W",	0,	1,	0ull,	0},
+	{"PTUNE"                       ,	20,	4,	449,	"R/W",	0,	1,	0ull,	0},
+	{"BYP"                         ,	24,	1,	449,	"R/W",	0,	1,	0ull,	0},
+	{"M180"                        ,	25,	1,	449,	"R/W",	0,	1,	0ull,	0},
+	{"DDR__NTUNE"                  ,	26,	4,	449,	"RO",	1,	1,	0,	0},
+	{"DDR__PTUNE"                  ,	30,	4,	449,	"RO",	1,	1,	0,	0},
+	{"RESERVED_34_63"              ,	34,	30,	449,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	450,	"WR0",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	450,	"R/W",	0,	0,	0ull,	1ull},
+	{"ROW_LSB"                     ,	2,	3,	450,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	450,	"R/W",	0,	1,	5ull,	0},
+	{"IDLEPOWER"                   ,	9,	3,	450,	"R/W",	0,	0,	0ull,	6ull},
+	{"FORCEWRITE"                  ,	12,	4,	450,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ADR"                     ,	16,	1,	450,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESET"                       ,	17,	1,	450,	"R/W",	0,	1,	0ull,	0},
+	{"REF_ZQCS_INT"                ,	18,	19,	450,	"R/W",	1,	1,	0,	0},
+	{"SEQUENCE"                    ,	37,	3,	450,	"R/W",	0,	0,	0ull,	0ull},
+	{"EARLY_DQX"                   ,	40,	1,	450,	"R/W",	0,	0,	0ull,	0ull},
+	{"SREF_WITH_DLL"               ,	41,	1,	450,	"R/W",	0,	0,	0ull,	0ull},
+	{"RANK_ENA"                    ,	42,	1,	450,	"R/W",	0,	1,	0ull,	0},
+	{"RANKMASK"                    ,	43,	4,	450,	"R/W",	0,	1,	0ull,	0},
+	{"MIRRMASK"                    ,	47,	4,	450,	"R/W",	0,	1,	0ull,	0},
+	{"INIT_STATUS"                 ,	51,	4,	450,	"R/W1",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D0_R0"          ,	55,	1,	450,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D0_R1"          ,	56,	1,	450,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D1_R0"          ,	57,	1,	450,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D1_R1"          ,	58,	1,	450,	"R/W",	0,	1,	0ull,	0},
+	{"SCRZ"                        ,	59,	1,	450,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	450,	"RAZ",	1,	1,	0,	0},
+	{"RDIMM_ENA"                   ,	0,	1,	451,	"R/W",	0,	1,	0ull,	0},
+	{"BWCNT"                       ,	1,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	2,	1,	451,	"R/W",	0,	0,	0ull,	1ull},
+	{"POCAS"                       ,	3,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPRCH2"                      ,	4,	2,	451,	"R/W",	0,	0,	0ull,	1ull},
+	{"THROTTLE_RD"                 ,	6,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"THROTTLE_WR"                 ,	7,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_RD"                  ,	8,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_WR"                  ,	9,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"ELEV_PRIO_DIS"               ,	10,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"NXM_WRITE_EN"                ,	11,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	12,	4,	451,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	16,	1,	451,	"R/W",	0,	0,	0ull,	1ull},
+	{"AUTO_DCLKDIS"                ,	17,	1,	451,	"R/W",	0,	0,	0ull,	1ull},
+	{"INT_ZQCS_DIS"                ,	18,	1,	451,	"R/W",	0,	0,	1ull,	0ull},
+	{"EXT_ZQCS_DIS"                ,	19,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"BPRCH"                       ,	20,	2,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"WODT_BPRCH"                  ,	22,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_BPRCH"                  ,	23,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_62"              ,	24,	39,	451,	"RAZ",	1,	1,	0,	0},
+	{"SCRAMBLE_ENA"                ,	63,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCLKCNT"                     ,	0,	64,	452,	"RO",	0,	1,	0ull,	0},
+	{"CLKF"                        ,	0,	7,	453,	"R/W",	0,	1,	48ull,	0},
+	{"RESET_N"                     ,	7,	1,	453,	"R/W",	0,	0,	0ull,	1ull},
+	{"CPB"                         ,	8,	3,	453,	"R/W",	0,	0,	0ull,	1ull},
+	{"CPS"                         ,	11,	3,	453,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIFFAMP"                     ,	14,	4,	453,	"R/W",	0,	0,	0ull,	1ull},
+	{"DDR_PS_EN"                   ,	18,	3,	453,	"R/W",	0,	1,	2ull,	0},
+	{"DDR_DIV_RESET"               ,	21,	1,	453,	"R/W",	0,	0,	1ull,	0ull},
+	{"DFM_PS_EN"                   ,	22,	3,	453,	"R/W",	0,	1,	2ull,	0},
+	{"DFM_DIV_RESET"               ,	25,	1,	453,	"R/W",	0,	0,	1ull,	0ull},
+	{"JTG_TEST_MODE"               ,	26,	1,	453,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	453,	"RAZ",	1,	1,	0,	0},
+	{"RC0"                         ,	0,	4,	454,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC1"                         ,	4,	4,	454,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC2"                         ,	8,	4,	454,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC3"                         ,	12,	4,	454,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC4"                         ,	16,	4,	454,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC5"                         ,	20,	4,	454,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC6"                         ,	24,	4,	454,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC7"                         ,	28,	4,	454,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC8"                         ,	32,	4,	454,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC9"                         ,	36,	4,	454,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC10"                        ,	40,	4,	454,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC11"                        ,	44,	4,	454,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC12"                        ,	48,	4,	454,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC13"                        ,	52,	4,	454,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC14"                        ,	56,	4,	454,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC15"                        ,	60,	4,	454,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIMM0_WMASK"                 ,	0,	16,	455,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"DIMM1_WMASK"                 ,	16,	16,	455,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"TCWS"                        ,	32,	13,	455,	"R/W",	0,	0,	1248ull,	1248ull},
+	{"PARITY"                      ,	45,	1,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	455,	"RAZ",	1,	1,	0,	0},
+	{"BYP_SETTING"                 ,	0,	8,	456,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYP_SEL"                     ,	8,	4,	456,	"R/W",	0,	0,	0ull,	0ull},
+	{"QUAD_DLL_ENA"                ,	12,	1,	456,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	13,	1,	456,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLL_BRINGUP"                 ,	14,	1,	456,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	456,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	6,	457,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYTE_SEL"                    ,	6,	4,	457,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE_SEL"                    ,	10,	2,	457,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOAD_OFFSET"                 ,	12,	1,	457,	"WR0",	0,	0,	0ull,	0ull},
+	{"OFFSET_ENA"                  ,	13,	1,	457,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYTE_SEL"              ,	14,	4,	457,	"R/W",	0,	0,	1ull,	1ull},
+	{"DLL_MODE"                    ,	18,	1,	457,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINE_TUNE_MODE"              ,	19,	1,	457,	"R/W",	0,	0,	0ull,	1ull},
+	{"DLL90_SETTING"               ,	20,	8,	457,	"RO",	1,	1,	0,	0},
+	{"DLL_FAST"                    ,	28,	1,	457,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	457,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	458,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	458,	"RAZ",	1,	1,	0,	0},
+	{"ROW_LSB"                     ,	16,	3,	458,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_19_63"              ,	19,	45,	458,	"RAZ",	1,	1,	0,	0},
+	{"MRDSYN0"                     ,	0,	8,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN1"                     ,	8,	8,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN2"                     ,	16,	8,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN3"                     ,	24,	8,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	459,	"RAZ",	1,	1,	0,	0},
+	{"FCOL"                        ,	0,	14,	460,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	14,	16,	460,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	30,	3,	460,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	33,	1,	460,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	34,	2,	460,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	460,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT"                      ,	0,	64,	461,	"RO",	0,	1,	1ull,	0},
+	{"NXM_WR_ERR"                  ,	0,	1,	462,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SEC_ERR"                     ,	1,	4,	462,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	5,	4,	462,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	462,	"RAZ",	1,	1,	0,	0},
+	{"INTR_NXM_WR_ENA"             ,	0,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_SEC_ENA"                ,	1,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_DED_ENA"                ,	2,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	463,	"RAZ",	1,	1,	0,	0},
+	{"CWL"                         ,	0,	3,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPRLOC"                      ,	3,	2,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPR"                         ,	5,	1,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL"                         ,	6,	1,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"AL"                          ,	7,	2,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"WLEV"                        ,	9,	1,	464,	"RO",	0,	0,	0ull,	0ull},
+	{"TDQS"                        ,	10,	1,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOFF"                        ,	11,	1,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"BL"                          ,	12,	2,	464,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	14,	4,	464,	"R/W",	0,	0,	2ull,	2ull},
+	{"RBT"                         ,	18,	1,	464,	"RO",	0,	0,	1ull,	1ull},
+	{"TM"                          ,	19,	1,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLR"                        ,	20,	1,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRP"                         ,	21,	3,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPD"                         ,	24,	1,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	464,	"RAZ",	1,	1,	0,	0},
+	{"PASR_00"                     ,	0,	3,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_00"                      ,	3,	1,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_00"                      ,	4,	1,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_00"                   ,	5,	2,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_00"                      ,	7,	2,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_00"                  ,	9,	3,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_01"                     ,	12,	3,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_01"                      ,	15,	1,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_01"                      ,	16,	1,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_01"                   ,	17,	2,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_01"                      ,	19,	2,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_01"                  ,	21,	3,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_10"                     ,	24,	3,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_10"                      ,	27,	1,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_10"                      ,	28,	1,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_10"                   ,	29,	2,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_10"                      ,	31,	2,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_10"                  ,	33,	3,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_11"                     ,	36,	3,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_11"                      ,	39,	1,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_11"                      ,	40,	1,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_11"                   ,	41,	2,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_11"                      ,	43,	2,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_11"                  ,	45,	3,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	465,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	466,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D0_R0"               ,	8,	4,	466,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D0_R1"               ,	12,	4,	466,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D1_R0"               ,	16,	4,	466,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D1_R1"               ,	20,	4,	466,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D2_R0"               ,	24,	4,	466,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D2_R1"               ,	28,	4,	466,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D3_R0"               ,	32,	4,	466,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D3_R1"               ,	36,	4,	466,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	466,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT"                      ,	0,	64,	467,	"RO",	0,	1,	1ull,	0},
+	{"TS_STAGGER"                  ,	0,	1,	468,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK_POS"                ,	1,	1,	468,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK"                    ,	2,	1,	468,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT0"                  ,	3,	4,	468,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE0"                    ,	7,	1,	468,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT1"                  ,	8,	4,	468,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE1"                    ,	12,	1,	468,	"R/W",	0,	1,	0ull,	0},
+	{"LV_MODE"                     ,	13,	1,	468,	"R/W",	0,	1,	0ull,	0},
+	{"RX_ALWAYS_ON"                ,	14,	1,	468,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	468,	"RAZ",	1,	1,	0,	0},
+	{"DDR3RST"                     ,	0,	1,	469,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PWARM"                   ,	1,	1,	469,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSOFT"                   ,	2,	1,	469,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSV"                     ,	3,	1,	469,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	469,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	470,	"R/W",	0,	1,	0ull,	0},
+	{"OFFSET"                      ,	4,	4,	470,	"R/W",	0,	0,	2ull,	2ull},
+	{"OFFSET_EN"                   ,	8,	1,	470,	"R/W",	0,	0,	1ull,	1ull},
+	{"OR_DIS"                      ,	9,	1,	470,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	10,	8,	470,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_0"              ,	18,	1,	470,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_1"              ,	19,	1,	470,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_2"              ,	20,	1,	470,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_3"              ,	21,	1,	470,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	470,	"RAZ",	1,	1,	0,	0},
+	{"BITMASK"                     ,	0,	64,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"BYTE0"                       ,	0,	6,	472,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	6,	6,	472,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE2"                       ,	12,	6,	472,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE3"                       ,	18,	6,	472,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE4"                       ,	24,	6,	472,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE5"                       ,	30,	6,	472,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE6"                       ,	36,	6,	472,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE7"                       ,	42,	6,	472,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE8"                       ,	48,	6,	472,	"R/W",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	54,	2,	472,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	472,	"RAZ",	1,	1,	0,	0},
+	{"RODT_D0_R0"                  ,	0,	8,	473,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D0_R1"                  ,	8,	8,	473,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D1_R0"                  ,	16,	8,	473,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D1_R1"                  ,	24,	8,	473,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D2_R0"                  ,	32,	8,	473,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D2_R1"                  ,	40,	8,	473,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R0"                  ,	48,	8,	473,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R1"                  ,	56,	8,	473,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	0,	64,	474,	"R/W",	0,	1,	0ull,	0},
+	{"KEY"                         ,	0,	64,	475,	"R/W",	0,	1,	0ull,	0},
+	{"FCOL"                        ,	0,	14,	476,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	14,	16,	476,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	30,	3,	476,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	33,	1,	476,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	34,	2,	476,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	476,	"RAZ",	1,	1,	0,	0},
+	{"R2R_INIT"                    ,	0,	6,	477,	"R/W",	0,	1,	1ull,	0},
+	{"R2W_INIT"                    ,	6,	6,	477,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_INIT"                    ,	12,	6,	477,	"R/W",	0,	1,	9ull,	0},
+	{"W2W_INIT"                    ,	18,	6,	477,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	477,	"RAZ",	1,	1,	0,	0},
+	{"R2R_XRANK_INIT"              ,	0,	6,	478,	"R/W",	0,	1,	3ull,	0},
+	{"R2W_XRANK_INIT"              ,	6,	6,	478,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_XRANK_INIT"              ,	12,	6,	478,	"R/W",	0,	1,	4ull,	0},
+	{"W2W_XRANK_INIT"              ,	18,	6,	478,	"R/W",	0,	1,	5ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	478,	"RAZ",	1,	1,	0,	0},
+	{"R2R_XDIMM_INIT"              ,	0,	6,	479,	"R/W",	0,	1,	4ull,	0},
+	{"R2W_XDIMM_INIT"              ,	6,	6,	479,	"R/W",	0,	1,	7ull,	0},
+	{"W2R_XDIMM_INIT"              ,	12,	6,	479,	"R/W",	0,	1,	4ull,	0},
+	{"W2W_XDIMM_INIT"              ,	18,	6,	479,	"R/W",	0,	1,	6ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	479,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_9"                ,	0,	10,	480,	"RAZ",	1,	1,	0,	0},
+	{"TZQCS"                       ,	10,	4,	480,	"R/W",	0,	0,	4ull,	4ull},
+	{"TCKE"                        ,	14,	4,	480,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPR"                        ,	18,	4,	480,	"R/W",	0,	0,	5ull,	5ull},
+	{"TMRD"                        ,	22,	4,	480,	"R/W",	0,	0,	4ull,	4ull},
+	{"TMOD"                        ,	26,	4,	480,	"R/W",	0,	0,	12ull,	12ull},
+	{"TDLLK"                       ,	30,	4,	480,	"R/W",	0,	0,	2ull,	2ull},
+	{"TZQINIT"                     ,	34,	4,	480,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	38,	4,	480,	"R/W",	0,	0,	6ull,	6ull},
+	{"TCKSRE"                      ,	42,	4,	480,	"R/W",	0,	0,	5ull,	5ull},
+	{"TRP_EXT"                     ,	46,	1,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	480,	"RAZ",	1,	1,	0,	0},
+	{"TMPRR"                       ,	0,	4,	481,	"R/W",	0,	0,	1ull,	1ull},
+	{"TRAS"                        ,	4,	5,	481,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	9,	4,	481,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	13,	4,	481,	"R/W",	0,	0,	2ull,	3ull},
+	{"TRFC"                        ,	17,	5,	481,	"R/W",	0,	0,	6ull,	7ull},
+	{"TRRD"                        ,	22,	3,	481,	"R/W",	0,	0,	2ull,	2ull},
+	{"TXP"                         ,	25,	3,	481,	"R/W",	0,	0,	3ull,	3ull},
+	{"TWLMRD"                      ,	28,	4,	481,	"R/W",	0,	0,	10ull,	10ull},
+	{"TWLDQSEN"                    ,	32,	4,	481,	"R/W",	0,	0,	7ull,	7ull},
+	{"TFAW"                        ,	36,	5,	481,	"R/W",	0,	0,	0ull,	9ull},
+	{"TXPDLL"                      ,	41,	5,	481,	"R/W",	0,	0,	0ull,	10ull},
+	{"TRAS_EXT"                    ,	46,	1,	481,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	481,	"RAZ",	1,	1,	0,	0},
+	{"TRESET"                      ,	0,	1,	482,	"R/W",	0,	1,	1ull,	0},
+	{"RCLK_CNT"                    ,	1,	32,	482,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	482,	"RAZ",	1,	1,	0,	0},
+	{"RING_CNT"                    ,	0,	32,	483,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	483,	"RAZ",	1,	1,	0,	0},
+	{"LANEMASK"                    ,	0,	9,	484,	"R/W",	0,	1,	0ull,	0},
+	{"SSET"                        ,	9,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"OR_DIS"                      ,	10,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"BITMASK"                     ,	11,	8,	484,	"R/W",	0,	1,	0ull,	0},
+	{"RTT_NOM"                     ,	19,	3,	484,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	484,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	485,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	4,	8,	485,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	485,	"RAZ",	1,	1,	0,	0},
+	{"BYTE0"                       ,	0,	5,	486,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	5,	5,	486,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE2"                       ,	10,	5,	486,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE3"                       ,	15,	5,	486,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE4"                       ,	20,	5,	486,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE5"                       ,	25,	5,	486,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE6"                       ,	30,	5,	486,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE7"                       ,	35,	5,	486,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE8"                       ,	40,	5,	486,	"R/W",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	45,	2,	486,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_47_63"              ,	47,	17,	486,	"RAZ",	1,	1,	0,	0},
+	{"WODT_D0_R0"                  ,	0,	8,	487,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D0_R1"                  ,	8,	8,	487,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D1_R0"                  ,	16,	8,	487,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D1_R1"                  ,	24,	8,	487,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D2_R0"                  ,	32,	8,	487,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D2_R1"                  ,	40,	8,	487,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D3_R0"                  ,	48,	8,	487,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D3_R1"                  ,	56,	8,	487,	"R/W",	0,	0,	255ull,	0ull},
+	{"STAT"                        ,	0,	10,	488,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	488,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	489,	"R/W",	1,	1,	0,	0},
+	{"PCTL"                        ,	6,	6,	489,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	489,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	490,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	490,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	490,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	490,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	490,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	490,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	490,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	490,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	490,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	490,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	491,	"R/W1C",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	491,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	491,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	492,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	492,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	492,	"RAZ",	1,	1,	0,	0},
+	{"DMARQ"                       ,	0,	6,	493,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_S"                     ,	6,	6,	493,	"R/W",	0,	1,	63ull,	0},
+	{"OE_A"                        ,	12,	6,	493,	"R/W",	0,	1,	63ull,	0},
+	{"OE_N"                        ,	18,	6,	493,	"R/W",	0,	1,	63ull,	0},
+	{"WE_A"                        ,	24,	6,	493,	"R/W",	0,	1,	63ull,	0},
+	{"WE_N"                        ,	30,	6,	493,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_H"                     ,	36,	6,	493,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	42,	6,	493,	"R/W",	0,	1,	63ull,	0},
+	{"RESERVED_48_54"              ,	48,	7,	493,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	55,	1,	493,	"R/W",	0,	1,	0ull,	0},
+	{"DDR"                         ,	56,	1,	493,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	57,	3,	493,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	60,	2,	493,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ_PI"                    ,	62,	1,	493,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK_PI"                    ,	63,	1,	493,	"R/W",	0,	1,	0ull,	0},
+	{"ADR_ERR"                     ,	0,	1,	494,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WAIT_ERR"                    ,	1,	1,	494,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	494,	"RAZ",	1,	1,	0,	0},
+	{"ADR_INT"                     ,	0,	1,	495,	"R/W",	0,	1,	0ull,	0},
+	{"WAIT_INT"                    ,	1,	1,	495,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	495,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	496,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	3,	5,	496,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	496,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	497,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	3,	25,	497,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_30"              ,	28,	3,	497,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	31,	1,	497,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	497,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	498,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	499,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	8,	1,	499,	"RO",	1,	1,	0,	0},
+	{"TERM"                        ,	9,	2,	499,	"RO",	1,	1,	0,	0},
+	{"DMACK_P0"                    ,	11,	1,	499,	"RO",	1,	1,	0,	0},
+	{"DMACK_P1"                    ,	12,	1,	499,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_13"              ,	13,	1,	499,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	14,	1,	499,	"RO",	1,	1,	0,	0},
+	{"ALE"                         ,	15,	1,	499,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	499,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	16,	500,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	16,	12,	500,	"R/W",	0,	1,	0ull,	0},
+	{"WIDTH"                       ,	28,	1,	500,	"R/W",	0,	1,	0ull,	0},
+	{"ALE"                         ,	29,	1,	500,	"R/W",	0,	1,	0ull,	0},
+	{"ORBIT"                       ,	30,	1,	500,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	31,	1,	500,	"R/W",	0,	1,	0ull,	0},
+	{"OE_EXT"                      ,	32,	2,	500,	"R/W",	0,	1,	0ull,	0},
+	{"WE_EXT"                      ,	34,	2,	500,	"R/W",	0,	1,	0ull,	0},
+	{"SAM"                         ,	36,	1,	500,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	37,	3,	500,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	40,	2,	500,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK"                       ,	42,	2,	500,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	500,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	6,	501,	"R/W",	0,	1,	63ull,	0},
+	{"CE"                          ,	6,	6,	501,	"R/W",	0,	1,	63ull,	0},
+	{"OE"                          ,	12,	6,	501,	"R/W",	0,	1,	63ull,	0},
+	{"WE"                          ,	18,	6,	501,	"R/W",	0,	1,	63ull,	0},
+	{"RD_HLD"                      ,	24,	6,	501,	"R/W",	0,	1,	63ull,	0},
+	{"WR_HLD"                      ,	30,	6,	501,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	36,	6,	501,	"R/W",	0,	1,	63ull,	0},
+	{"WAIT"                        ,	42,	6,	501,	"R/W",	0,	1,	63ull,	0},
+	{"PAGE"                        ,	48,	6,	501,	"R/W",	0,	1,	63ull,	0},
+	{"ALE"                         ,	54,	6,	501,	"R/W",	0,	1,	63ull,	0},
+	{"PAGES"                       ,	60,	2,	501,	"R/W",	0,	1,	0ull,	0},
+	{"WAITM"                       ,	62,	1,	501,	"R/W",	0,	1,	0ull,	0},
+	{"PAGEM"                       ,	63,	1,	501,	"R/W",	0,	1,	0ull,	0},
+	{"FIF_THR"                     ,	0,	6,	502,	"R/W",	0,	0,	25ull,	25ull},
+	{"RESERVED_6_7"                ,	6,	2,	502,	"RAZ",	1,	1,	0,	0},
+	{"FIF_CNT"                     ,	8,	6,	502,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	502,	"RAZ",	1,	1,	0,	0},
+	{"DMA_THR"                     ,	16,	6,	502,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_63"              ,	22,	42,	502,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	503,	"R/W",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	504,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	504,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	505,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	505,	"RAZ",	1,	1,	0,	0},
+	{"PP_DIS"                      ,	0,	10,	506,	"RO",	1,	1,	0,	0},
+	{"RESERVED_10_15"              ,	10,	6,	506,	"RO",	1,	1,	0,	0},
+	{"CHIP_ID"                     ,	16,	8,	506,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_25"              ,	24,	2,	506,	"RO",	1,	1,	0,	0},
+	{"NOCRYPTO"                    ,	26,	1,	506,	"RO",	1,	1,	0,	0},
+	{"NOMUL"                       ,	27,	1,	506,	"RO",	1,	1,	0,	0},
+	{"NODFA_CP2"                   ,	28,	1,	506,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_31"              ,	29,	3,	506,	"RO",	1,	1,	0,	0},
+	{"RAID_EN"                     ,	32,	1,	506,	"RO",	1,	1,	0,	0},
+	{"FUS318"                      ,	33,	1,	506,	"RO",	1,	1,	0,	0},
+	{"DORM_CRYPTO"                 ,	34,	1,	506,	"RO",	1,	1,	0,	0},
+	{"POWER_LIMIT"                 ,	35,	2,	506,	"RO",	1,	1,	0,	0},
+	{"ROM_INFO"                    ,	37,	10,	506,	"RO",	1,	1,	0,	0},
+	{"FUS118"                      ,	47,	1,	506,	"RO",	1,	1,	0,	0},
+	{"RESERVED_48_63"              ,	48,	16,	506,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	507,	"RAZ",	1,	1,	0,	0},
+	{"NODFA_DTE"                   ,	24,	1,	507,	"RO",	1,	1,	0,	0},
+	{"NOZIP"                       ,	25,	1,	507,	"RO",	1,	1,	0,	0},
+	{"EFUS_IGN"                    ,	26,	1,	507,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK"                    ,	27,	1,	507,	"RO",	1,	1,	0,	0},
+	{"BAR2_EN"                     ,	28,	1,	507,	"RO",	1,	1,	0,	0},
+	{"ZIP_INFO"                    ,	29,	2,	507,	"RO",	1,	1,	0,	0},
+	{"RESERVED_31_31"              ,	31,	1,	507,	"RAZ",	1,	1,	0,	0},
+	{"L2C_CRIP"                    ,	32,	3,	507,	"RO",	1,	1,	0,	0},
+	{"PLL_HALF_DIS"                ,	35,	1,	507,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK_MAN"                ,	36,	1,	507,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK_RSV"                ,	37,	1,	507,	"RO",	1,	1,	0,	0},
+	{"EMA"                         ,	38,	2,	507,	"RO",	1,	1,	0,	0},
+	{"RESERVED_40_40"              ,	40,	1,	507,	"RAZ",	1,	1,	0,	0},
+	{"DFA_INFO_CLM"                ,	41,	4,	507,	"RO",	1,	1,	0,	0},
+	{"DFA_INFO_DTE"                ,	45,	3,	507,	"RO",	1,	1,	0,	0},
+	{"PLL_CTL"                     ,	48,	10,	507,	"RO",	1,	1,	0,	0},
+	{"RESERVED_58_63"              ,	58,	6,	507,	"RAZ",	1,	1,	0,	0},
+	{"EMA"                         ,	0,	3,	508,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_3_3"                ,	3,	1,	508,	"RAZ",	1,	1,	0,	0},
+	{"EFF_EMA"                     ,	4,	3,	508,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_7_63"               ,	7,	57,	508,	"RAZ",	1,	1,	0,	0},
+	{"PDF"                         ,	0,	64,	509,	"RO",	1,	1,	0,	0},
+	{"FBSLIP"                      ,	0,	1,	510,	"RAZ",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	510,	"RAZ",	0,	1,	0ull,	0},
+	{"PNR_COUT_SEL"                ,	2,	2,	510,	"R/W",	0,	1,	0ull,	0},
+	{"PNR_COUT_RST"                ,	4,	1,	510,	"R/W",	0,	1,	0ull,	0},
+	{"C_COUT_SEL"                  ,	5,	2,	510,	"R/W",	0,	1,	0ull,	0},
+	{"C_COUT_RST"                  ,	7,	1,	510,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	510,	"RAZ",	1,	1,	0,	0},
+	{"PROG"                        ,	0,	1,	511,	"R/W",	1,	1,	0,	0},
+	{"SOFT"                        ,	1,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	511,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	6,	512,	"R/W",	0,	1,	1ull,	0},
+	{"SCLK_HI"                     ,	6,	15,	512,	"R/W",	0,	1,	5000ull,	0},
+	{"SCLK_LO"                     ,	21,	4,	512,	"R/W",	0,	1,	1ull,	0},
+	{"OUT"                         ,	25,	7,	512,	"R/W",	0,	1,	1ull,	0},
+	{"PROG_PIN"                    ,	32,	1,	512,	"RO",	0,	0,	0ull,	0ull},
+	{"FSRC_PIN"                    ,	33,	1,	512,	"RO",	0,	0,	0ull,	0ull},
+	{"VGATE_PIN"                   ,	34,	1,	512,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	512,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	8,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"EFUSE"                       ,	8,	1,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	513,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	12,	1,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	513,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	16,	8,	513,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_63"              ,	24,	40,	513,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	10,	514,	"R/W",	0,	1,	999ull,	0},
+	{"SDH"                         ,	10,	4,	514,	"R/W",	0,	1,	0ull,	0},
+	{"PRH"                         ,	14,	4,	514,	"R/W",	0,	1,	6ull,	0},
+	{"FSH"                         ,	18,	4,	514,	"R/W",	0,	1,	15ull,	0},
+	{"SCH"                         ,	22,	4,	514,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	514,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	18,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR1"                     ,	18,	18,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR2"                     ,	36,	18,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"TOO_MANY"                    ,	54,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	515,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR3"                     ,	0,	18,	516,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR4"                     ,	18,	18,	516,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR5"                     ,	36,	18,	516,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	516,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR6"                     ,	0,	18,	517,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	517,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	14,	518,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR1"                     ,	14,	14,	518,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR2"                     ,	28,	14,	518,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_42_63"              ,	42,	22,	518,	"RAZ",	1,	1,	0,	0},
+	{"TOO_MANY"                    ,	0,	1,	519,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	519,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	63,	520,	"RO",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	520,	"R/W",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	4,	521,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_4_63"               ,	4,	60,	521,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	522,	"R/W",	0,	1,	15ull,	0},
+	{"PCTL"                        ,	6,	6,	522,	"R/W",	0,	1,	19ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	522,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	523,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	523,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	523,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	523,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	523,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	523,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	523,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	523,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	523,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	523,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	524,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	524,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	525,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	525,	"RAZ",	1,	1,	0,	0},
+	{"FRNANOSEC"                   ,	0,	32,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	0,	64,	528,	"R/W",	0,	0,	18446744073709551615ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	529,	"R/W",	0,	0,	4294967295ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	529,	"RAZ",	1,	1,	0,	0},
+	{"PTP_EN"                      ,	0,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_CLK_EN"                  ,	1,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_CLK_IN"                  ,	2,	6,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_EN"                    ,	8,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_EDGE"                  ,	9,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_IN"                    ,	10,	6,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_EN"                    ,	16,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_EDGE"                  ,	17,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_IN"                    ,	18,	6,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT_EN"                    ,	24,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT_INV"                   ,	25,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT_OUT"                   ,	26,	4,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS_EN"                      ,	30,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS_INV"                     ,	31,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS_OUT"                     ,	32,	5,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT_OUT4"                  ,	37,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_CLK_EDGE"                ,	38,	2,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	530,	"RAZ",	1,	1,	0,	0},
+	{"FRNANOSEC"                   ,	0,	32,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	0,	64,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	533,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	533,	"RAZ",	1,	1,	0,	0},
+	{"CNTR"                        ,	0,	64,	534,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	0,	64,	537,	"R/W",	0,	0,	18446744073709551615ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	538,	"R/W",	0,	0,	4294967295ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	538,	"RAZ",	1,	1,	0,	0},
+	{"NANOSEC"                     ,	0,	64,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"QLM_CFG"                     ,	0,	4,	540,	"RO",	1,	1,	0,	0},
+	{"RESERVED_4_7"                ,	4,	4,	540,	"RAZ",	1,	1,	0,	0},
+	{"QLM_SPD"                     ,	8,	4,	540,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	540,	"RAZ",	1,	1,	0,	0},
+	{"RBOOT_PIN"                   ,	0,	1,	541,	"RO",	1,	1,	0,	0},
+	{"RBOOT"                       ,	1,	1,	541,	"R/W",	1,	1,	0,	0},
+	{"LBOOT"                       ,	2,	10,	541,	"R/W1C",	1,	1,	0,	0},
+	{"QLM0_SPD"                    ,	12,	4,	541,	"RO",	1,	1,	0,	0},
+	{"QLM1_SPD"                    ,	16,	4,	541,	"RO",	1,	1,	0,	0},
+	{"QLM2_SPD"                    ,	20,	4,	541,	"RO",	1,	1,	0,	0},
+	{"PNR_MUL"                     ,	24,	6,	541,	"RO",	1,	1,	0,	0},
+	{"C_MUL"                       ,	30,	6,	541,	"RO",	1,	1,	0,	0},
+	{"RESERVED_36_47"              ,	36,	12,	541,	"RAZ",	1,	1,	0,	0},
+	{"LBOOT_EXT"                   ,	48,	2,	541,	"R/W1C",	1,	1,	0,	0},
+	{"RESERVED_50_58"              ,	50,	9,	541,	"RAZ",	1,	1,	0,	0},
+	{"CKILL_PPDIS"                 ,	59,	1,	541,	"R/W",	0,	1,	1ull,	0},
+	{"ROMEN"                       ,	60,	1,	541,	"R/W",	1,	1,	0,	0},
+	{"EJTAGDIS"                    ,	61,	1,	541,	"R/W",	1,	1,	0,	0},
+	{"JTCSRDIS"                    ,	62,	1,	541,	"R/W",	1,	1,	0,	0},
+	{"CHIPKILL"                    ,	63,	1,	541,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SOFT_CLR_BIST"               ,	0,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"WARM_CLR_BIST"               ,	1,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNTL_CLR_BIST"               ,	2,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_5"                ,	3,	3,	542,	"RAZ",	1,	1,	0,	0},
+	{"BIST_DELAY"                  ,	6,	58,	542,	"RO",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	47,	543,	"R/W",	0,	1,	17179869183ull,	0},
+	{"RESERVED_47_63"              ,	47,	17,	543,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RST_VAL"                     ,	0,	1,	544,	"RO",	1,	1,	0,	0},
+	{"RST_CHIP"                    ,	1,	1,	544,	"R/W",	0,	1,	0ull,	0},
+	{"RST_RCV"                     ,	2,	1,	544,	"R/W",	1,	1,	0,	0},
+	{"RST_DRV"                     ,	3,	1,	544,	"R/W",	1,	1,	0,	0},
+	{"PRTMODE"                     ,	4,	2,	544,	"R/W",	1,	1,	0,	0},
+	{"HOST_MODE"                   ,	6,	1,	544,	"RO",	1,	1,	0,	0},
+	{"RST_LINK"                    ,	7,	1,	544,	"R/W",	1,	1,	0,	0},
+	{"RST_DONE"                    ,	8,	1,	544,	"RO",	1,	1,	0,	0},
+	{"PRST_LINK"                   ,	9,	1,	544,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	544,	"RAZ",	1,	1,	0,	0},
+	{"RST_VAL"                     ,	0,	1,	545,	"RO",	1,	1,	0,	0},
+	{"RST_CHIP"                    ,	1,	1,	545,	"R/W",	0,	1,	0ull,	0},
+	{"RST_RCV"                     ,	2,	1,	545,	"R/W",	1,	1,	0,	0},
+	{"RST_DRV"                     ,	3,	1,	545,	"R/W",	1,	1,	0,	0},
+	{"PRTMODE"                     ,	4,	2,	545,	"R/W",	1,	1,	0,	0},
+	{"HOST_MODE"                   ,	6,	1,	545,	"RO",	1,	1,	0,	0},
+	{"RST_LINK"                    ,	7,	1,	545,	"R/W",	1,	1,	0,	0},
+	{"RST_DONE"                    ,	8,	1,	545,	"RO",	1,	1,	0,	0},
+	{"PRST_LINK"                   ,	9,	1,	545,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	545,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST_DLY"                ,	0,	16,	546,	"R/W",	0,	1,	2047ull,	0},
+	{"WARM_RST_DLY"                ,	16,	16,	546,	"R/W",	0,	1,	2047ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	546,	"RAZ",	1,	1,	0,	0},
+	{"RST_LINK0"                   ,	0,	1,	547,	"R/W1C",	0,	1,	0ull,	0},
+	{"RST_LINK1"                   ,	1,	1,	547,	"R/W1C",	0,	1,	0ull,	0},
+	{"RST_LINK2"                   ,	2,	1,	547,	"R/W1C",	0,	1,	0ull,	0},
+	{"RST_LINK3"                   ,	3,	1,	547,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	547,	"RAZ",	1,	1,	0,	0},
+	{"PERST0"                      ,	8,	1,	547,	"R/W1C",	0,	1,	0ull,	0},
+	{"PERST1"                      ,	9,	1,	547,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	547,	"RAZ",	1,	1,	0,	0},
+	{"RST_LINK0"                   ,	0,	1,	548,	"R/W",	0,	1,	0ull,	0},
+	{"RST_LINK1"                   ,	1,	1,	548,	"R/W",	0,	1,	0ull,	0},
+	{"RST_LINK2"                   ,	2,	1,	548,	"R/W",	0,	1,	0ull,	0},
+	{"RST_LINK3"                   ,	3,	1,	548,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	548,	"RAZ",	1,	1,	0,	0},
+	{"PERST0"                      ,	8,	1,	548,	"R/W",	0,	1,	0ull,	0},
+	{"PERST1"                      ,	9,	1,	548,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	548,	"RAZ",	1,	1,	0,	0},
+	{"ST_INT"                      ,	0,	1,	549,	"R/W1C",	0,	1,	0ull,	0},
+	{"TS_INT"                      ,	1,	1,	549,	"R/W1C",	0,	1,	0ull,	0},
+	{"CORE_INT"                    ,	2,	1,	549,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	549,	"RAZ",	1,	1,	0,	0},
+	{"ST_EN"                       ,	4,	1,	549,	"R/W",	0,	1,	0ull,	0},
+	{"TS_EN"                       ,	5,	1,	549,	"R/W",	0,	1,	0ull,	0},
+	{"CORE_EN"                     ,	6,	1,	549,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	549,	"RAZ",	1,	1,	0,	0},
+	{"SDA_OVR"                     ,	8,	1,	549,	"R/W",	0,	1,	0ull,	0},
+	{"SCL_OVR"                     ,	9,	1,	549,	"R/W",	0,	1,	0ull,	0},
+	{"SDA"                         ,	10,	1,	549,	"RO",	1,	1,	0,	0},
+	{"SCL"                         ,	11,	1,	549,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	549,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	550,	"R/W",	0,	1,	0ull,	0},
+	{"EOP_IA"                      ,	32,	3,	550,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	35,	5,	550,	"R/W",	0,	1,	0ull,	0},
+	{"A"                           ,	40,	10,	550,	"R/W",	0,	1,	0ull,	0},
+	{"SCR"                         ,	50,	2,	550,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	52,	3,	550,	"R/W",	0,	1,	0ull,	0},
+	{"SOVR"                        ,	55,	1,	550,	"R/W",	0,	1,	0ull,	0},
+	{"R"                           ,	56,	1,	550,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	57,	4,	550,	"R/W",	0,	1,	0ull,	0},
+	{"EIA"                         ,	61,	1,	550,	"R/W",	0,	1,	0ull,	0},
+	{"SLONLY"                      ,	62,	1,	550,	"R/W",	0,	1,	0ull,	0},
+	{"V"                           ,	63,	1,	550,	"RC/W",	0,	1,	0ull,	0},
+	{"D"                           ,	0,	32,	551,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	32,	8,	551,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	551,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	552,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_32_61"              ,	32,	30,	552,	"RAZ",	1,	1,	0,	0},
+	{"V"                           ,	62,	2,	552,	"RC/W",	0,	1,	0ull,	0},
+	{"DLH"                         ,	0,	8,	553,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	553,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	554,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	554,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	555,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	555,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	556,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	556,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	556,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	556,	"RAZ",	1,	1,	0,	0},
+	{"TXTRIG"                      ,	4,	2,	556,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	556,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	556,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	557,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	557,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	558,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	558,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	558,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	558,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	558,	"RAZ",	1,	1,	0,	0},
+	{"PTIME"                       ,	7,	1,	558,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	558,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	559,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	559,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	559,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	559,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	560,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	560,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	560,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	560,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	560,	"RAZ",	1,	1,	0,	0},
+	{"BRK"                         ,	6,	1,	560,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	560,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	560,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	561,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	561,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	561,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	561,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	561,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	561,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	561,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	561,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	561,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	562,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	562,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	562,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	562,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	562,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	562,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	562,	"RAZ",	1,	1,	0,	0},
+	{"DCTS"                        ,	0,	1,	563,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	563,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	563,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	563,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	563,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	563,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	563,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	563,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	563,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	564,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	564,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	565,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	565,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	566,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	566,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	566,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	566,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	567,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	567,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	568,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	568,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	569,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	569,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	570,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	570,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	570,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	570,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	571,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	571,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	572,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	572,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	573,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	573,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	574,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	574,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	575,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	575,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	576,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	576,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	577,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	577,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	577,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	577,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	577,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	577,	"RAZ",	1,	1,	0,	0},
+	{"ORFDAT"                      ,	0,	1,	578,	"RO",	0,	0,	0ull,	0ull},
+	{"IRFDAT"                      ,	1,	1,	578,	"RO",	0,	0,	0ull,	0ull},
+	{"IPFDAT"                      ,	2,	1,	578,	"RO",	0,	0,	0ull,	0ull},
+	{"MRQDAT"                      ,	3,	1,	578,	"RO",	0,	0,	0ull,	0ull},
+	{"MRGDAT"                      ,	4,	1,	578,	"RO",	0,	0,	0ull,	0ull},
+	{"OPFDAT"                      ,	5,	1,	578,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	578,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MRQ_HWM"                     ,	0,	2,	579,	"R/W",	0,	0,	0ull,	1ull},
+	{"NBTARB"                      ,	2,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENDIAN"                     ,	3,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	4,	1,	579,	"R/W",	0,	0,	1ull,	0ull},
+	{"EN"                          ,	5,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"BUSY"                        ,	6,	1,	579,	"RO",	0,	0,	0ull,	0ull},
+	{"CRC_STRIP"                   ,	7,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"TS_THRESH"                   ,	8,	4,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	579,	"RAZ",	1,	1,	0,	0},
+	{"OVFENA"                      ,	0,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"IVFENA"                      ,	1,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTHENA"                      ,	2,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"ITHENA"                      ,	3,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_DRPENA"                 ,	4,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"IRUNENA"                     ,	5,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"ORUNENA"                     ,	6,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSENA"                       ,	7,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	580,	"RAZ",	1,	1,	0,	0},
+	{"IRCNT"                       ,	0,	20,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	581,	"RAZ",	1,	1,	0,	0},
+	{"IRHWM"                       ,	0,	20,	582,	"R/W",	0,	0,	0ull,	0ull},
+	{"IBPLWM"                      ,	20,	20,	582,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	582,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	583,	"RAZ",	1,	1,	0,	0},
+	{"IBASE"                       ,	3,	37,	583,	"R/W",	0,	1,	0ull,	0},
+	{"ISIZE"                       ,	40,	20,	583,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	583,	"RAZ",	1,	1,	0,	0},
+	{"IDBELL"                      ,	0,	20,	584,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	584,	"RAZ",	1,	1,	0,	0},
+	{"ITLPTR"                      ,	32,	20,	584,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	584,	"RAZ",	1,	1,	0,	0},
+	{"ODBLOVF"                     ,	0,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IDBLOVF"                     ,	1,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORTHRESH"                    ,	2,	1,	585,	"RO",	0,	0,	0ull,	0ull},
+	{"IRTHRESH"                    ,	3,	1,	585,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_DRP"                    ,	4,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IRUN"                        ,	5,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORUN"                        ,	6,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TS"                          ,	7,	1,	585,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	585,	"RAZ",	1,	1,	0,	0},
+	{"ORCNT"                       ,	0,	20,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	586,	"RAZ",	1,	1,	0,	0},
+	{"ORHWM"                       ,	0,	20,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	587,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	588,	"RAZ",	1,	1,	0,	0},
+	{"OBASE"                       ,	3,	37,	588,	"R/W",	0,	1,	0ull,	0},
+	{"OSIZE"                       ,	40,	20,	588,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	588,	"RAZ",	1,	1,	0,	0},
+	{"ODBELL"                      ,	0,	20,	589,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	589,	"RAZ",	1,	1,	0,	0},
+	{"OTLPTR"                      ,	32,	20,	589,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	589,	"RAZ",	1,	1,	0,	0},
+	{"OREMCNT"                     ,	0,	20,	590,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	590,	"RAZ",	1,	1,	0,	0},
+	{"IREMCNT"                     ,	32,	20,	590,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_52_63"              ,	52,	12,	590,	"RAZ",	1,	1,	0,	0},
+	{"TSCNT"                       ,	0,	5,	591,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	591,	"RAZ",	1,	1,	0,	0},
+	{"TSTOT"                       ,	8,	5,	591,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	591,	"RAZ",	1,	1,	0,	0},
+	{"TSAVL"                       ,	16,	5,	591,	"RO",	0,	0,	4ull,	4ull},
+	{"RESERVED_21_63"              ,	21,	43,	591,	"RAZ",	1,	1,	0,	0},
+	{"TSTAMP"                      ,	0,	64,	592,	"RO",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	593,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDLELO"                      ,	1,	1,	593,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_CONT"                    ,	2,	1,	593,	"R/W",	0,	0,	0ull,	0ull},
+	{"WIREOR"                      ,	3,	1,	593,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBFIRST"                    ,	4,	1,	593,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_ENA"                     ,	5,	1,	593,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	593,	"RAZ",	1,	1,	0,	0},
+	{"CSHI"                        ,	7,	1,	593,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDLECLKS"                    ,	8,	2,	593,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRITX"                       ,	10,	1,	593,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSLATE"                      ,	11,	1,	593,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_13"              ,	12,	2,	593,	"RAZ",	1,	1,	0,	0},
+	{"CSENA2"                      ,	14,	1,	593,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSENA3"                      ,	15,	1,	593,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKDIV"                      ,	16,	13,	593,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	593,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	8,	594,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	594,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	595,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	595,	"RAZ",	1,	1,	0,	0},
+	{"RXNUM"                       ,	8,	5,	595,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	595,	"RAZ",	1,	1,	0,	0},
+	{"TOTNUM"                      ,	0,	5,	596,	"WO",	1,	0,	0,	2ull},
+	{"RESERVED_5_7"                ,	5,	3,	596,	"RAZ",	1,	1,	0,	0},
+	{"TXNUM"                       ,	8,	5,	596,	"WO",	1,	0,	0,	1ull},
+	{"RESERVED_13_15"              ,	13,	3,	596,	"RAZ",	1,	1,	0,	0},
+	{"LEAVECS"                     ,	16,	1,	596,	"WO",	1,	0,	0,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	596,	"RAZ",	1,	1,	0,	0},
+	{"CSID"                        ,	20,	2,	596,	"WO",	1,	0,	0,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	596,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	3,	597,	"R/W",	0,	1,	0ull,	0},
+	{"ADR_CYC"                     ,	3,	4,	597,	"R/W",	0,	1,	8ull,	0},
+	{"T_MULT"                      ,	7,	4,	597,	"R/W",	0,	1,	9ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	597,	"RAZ",	1,	1,	0,	0},
+	{"NF_CMD"                      ,	0,	64,	598,	"R/W",	0,	1,	0ull,	0},
+	{"CNT"                         ,	0,	8,	599,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	599,	"RAZ",	1,	1,	0,	0},
+	{"ECC_ERR"                     ,	0,	8,	600,	"RO",	0,	1,	0ull,	0},
+	{"XOR_ECC"                     ,	8,	24,	600,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	600,	"RAZ",	1,	1,	0,	0},
+	{"EMPTY"                       ,	0,	1,	601,	"R/W1C",	0,	1,	0ull,	0},
+	{"FULL"                        ,	1,	1,	601,	"R/W1C",	0,	1,	0ull,	0},
+	{"WDOG"                        ,	2,	1,	601,	"R/W1C",	0,	1,	0ull,	0},
+	{"SM_BAD"                      ,	3,	1,	601,	"R/W1C",	0,	1,	0ull,	0},
+	{"ECC_1BIT"                    ,	4,	1,	601,	"R/W1C",	0,	1,	0ull,	0},
+	{"ECC_MULT"                    ,	5,	1,	601,	"R/W1C",	0,	1,	0ull,	0},
+	{"OVRF"                        ,	6,	1,	601,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	601,	"RAZ",	1,	1,	0,	0},
+	{"EMPTY"                       ,	0,	1,	602,	"R/W",	0,	1,	0ull,	0},
+	{"FULL"                        ,	1,	1,	602,	"R/W",	0,	1,	0ull,	0},
+	{"WDOG"                        ,	2,	1,	602,	"R/W",	0,	1,	0ull,	0},
+	{"SM_BAD"                      ,	3,	1,	602,	"R/W",	0,	1,	0ull,	0},
+	{"ECC_1BIT"                    ,	4,	1,	602,	"R/W",	0,	1,	0ull,	0},
+	{"ECC_MULT"                    ,	5,	1,	602,	"R/W",	0,	1,	0ull,	0},
+	{"OVRF"                        ,	6,	1,	602,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	602,	"RAZ",	1,	1,	0,	0},
+	{"RST_FF"                      ,	0,	1,	603,	"R/W",	0,	0,	0ull,	0ull},
+	{"EX_DIS"                      ,	1,	1,	603,	"R/W",	0,	0,	0ull,	0ull},
+	{"BT_DIS"                      ,	2,	1,	603,	"R/W",	0,	0,	0ull,	1ull},
+	{"BT_DMA"                      ,	3,	1,	603,	"R/W",	0,	1,	0ull,	0},
+	{"RD_CMD"                      ,	4,	1,	603,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD_VAL"                      ,	5,	1,	603,	"RO",	0,	1,	0ull,	0},
+	{"RD_DONE"                     ,	6,	1,	603,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FR_BYT"                      ,	7,	11,	603,	"RO",	0,	1,	0ull,	0},
+	{"WAIT_CNT"                    ,	18,	6,	603,	"R/W",	0,	1,	20ull,	0},
+	{"NBR_HWM"                     ,	24,	3,	603,	"R/W",	0,	0,	3ull,	3ull},
+	{"MB_DIS"                      ,	27,	1,	603,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	603,	"RAZ",	1,	1,	0,	0},
+	{"MAIN_SM"                     ,	0,	3,	604,	"RO",	0,	1,	0ull,	0},
+	{"MAIN_BAD"                    ,	3,	1,	604,	"RO",	0,	1,	0ull,	0},
+	{"RD_FF"                       ,	4,	2,	604,	"RO",	0,	1,	0ull,	0},
+	{"RD_FF_BAD"                   ,	6,	1,	604,	"RO",	0,	1,	0ull,	0},
+	{"BT_SM"                       ,	7,	4,	604,	"RO",	0,	1,	0ull,	0},
+	{"EXE_SM"                      ,	11,	4,	604,	"RO",	0,	1,	0ull,	0},
+	{"EXE_IDLE"                    ,	15,	1,	604,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	604,	"RAZ",	1,	1,	0,	0},
+	{"VENDID"                      ,	0,	16,	605,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	605,	"RO/WRSL",	0,	0,	146ull,	146ull},
+	{"ISAE"                        ,	0,	1,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	606,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	606,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	606,	"RAZ",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	606,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	606,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	606,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	606,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	606,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	606,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	607,	"RO/WRSL",	0,	0,	8ull,	8ull},
+	{"PI"                          ,	8,	8,	607,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	607,	"RO/WRSL",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	607,	"RO/WRSL",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	608,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	608,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	608,	"RO",	0,	0,	0ull,	0ull},
+	{"MFD"                         ,	23,	1,	608,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	608,	"RO",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	609,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	609,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	609,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_13"               ,	4,	10,	609,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	14,	18,	609,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	610,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	610,	"WORSL",	0,	0,	8191ull,	8191ull},
+	{"UBAB"                        ,	0,	32,	611,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	612,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	613,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	613,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	613,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_25"               ,	4,	22,	613,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	26,	6,	613,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	614,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	614,	"WORSL",	0,	0,	33554431ull,	33554431ull},
+	{"UBAB"                        ,	0,	32,	615,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	616,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	617,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	617,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	617,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_31"               ,	4,	28,	617,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	1,	618,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	618,	"WORSL",	0,	0,	2147483647ull,	2147483647ull},
+	{"RESERVED_0_8"                ,	0,	9,	619,	"RAZ",	1,	1,	0,	0},
+	{"UBAB"                        ,	9,	23,	619,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	620,	"WORSL",	0,	0,	511ull,	511ull},
+	{"CISP"                        ,	0,	32,	621,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SSVID"                       ,	0,	16,	622,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"SSID"                        ,	16,	16,	622,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"ER_EN"                       ,	0,	1,	623,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_15"               ,	1,	15,	623,	"RAZ",	1,	1,	0,	0},
+	{"ERADDR"                      ,	16,	16,	623,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	624,	"WORSL",	0,	0,	1ull,	1ull},
+	{"MASK"                        ,	1,	31,	624,	"WORSL",	0,	0,	32767ull,	32767ull},
+	{"CP"                          ,	0,	8,	625,	"RO/WRSL",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	625,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	626,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	626,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"MG"                          ,	16,	8,	626,	"RO",	0,	0,	0ull,	0ull},
+	{"ML"                          ,	24,	8,	626,	"RO",	0,	0,	0ull,	0ull},
+	{"PMCID"                       ,	0,	8,	627,	"RO",	0,	0,	1ull,	0ull},
+	{"NCP"                         ,	8,	8,	627,	"RO/WRSL",	0,	0,	80ull,	0ull},
+	{"PMSV"                        ,	16,	3,	627,	"RO/WRSL",	0,	0,	3ull,	0ull},
+	{"PME_CLOCK"                   ,	19,	1,	627,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	627,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	627,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	627,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	627,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	627,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	627,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	628,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	628,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	628,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	628,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	628,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	628,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	628,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	628,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	628,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	628,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	628,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	629,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	629,	"RO/WRSL",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	629,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	629,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	629,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	629,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"PVM"                         ,	24,	1,	629,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	629,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	630,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	632,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	633,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	633,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	633,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"SI"                          ,	24,	1,	633,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	633,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	633,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	634,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	634,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	634,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	634,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"EL1AL"                       ,	9,	3,	634,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"RESERVED_12_14"              ,	12,	3,	634,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	634,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	634,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	634,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	634,	"RO",	0,	0,	0ull,	0ull},
+	{"FLR"                         ,	28,	1,	634,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	634,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	635,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	635,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	635,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	635,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	635,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	635,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	635,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	635,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	635,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	635,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	635,	"R/W",	0,	0,	2ull,	2ull},
+	{"I_FLR"                       ,	15,	1,	635,	"RO",	0,	0,	0ull,	0ull},
+	{"CE_D"                        ,	16,	1,	635,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	635,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	635,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	635,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	635,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	635,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	635,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	636,	"RO/WRSL",	1,	1,	0,	0},
+	{"MLW"                         ,	4,	6,	636,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"ASLPMS"                      ,	10,	2,	636,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	636,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	636,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	636,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	636,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	636,	"RO",	0,	0,	0ull,	0ull},
+	{"LBNC"                        ,	21,	1,	636,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPM"                        ,	22,	1,	636,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_23_23"              ,	23,	1,	636,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	636,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	637,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	637,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	637,	"RO",	0,	0,	0ull,	0ull},
+	{"LD"                          ,	4,	1,	637,	"RO",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	637,	"RO",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	637,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	637,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	637,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	637,	"RO",	0,	0,	0ull,	0ull},
+	{"LBM_INT_ENB"                 ,	10,	1,	637,	"RO",	0,	0,	0ull,	0ull},
+	{"LAB_INT_ENB"                 ,	11,	1,	637,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	637,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	637,	"RO",	0,	0,	1ull,	1ull},
+	{"NLW"                         ,	20,	6,	637,	"RO",	0,	0,	0ull,	8ull},
+	{"RESERVED_26_26"              ,	26,	1,	637,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	637,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	637,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"DLLA"                        ,	29,	1,	637,	"RO",	0,	0,	0ull,	0ull},
+	{"LBM"                         ,	30,	1,	637,	"RO",	0,	0,	0ull,	0ull},
+	{"LAB"                         ,	31,	1,	637,	"RO",	0,	0,	0ull,	0ull},
+	{"CTRS"                        ,	0,	4,	638,	"RO",	0,	0,	15ull,	15ull},
+	{"CTDS"                        ,	4,	1,	638,	"RO",	0,	0,	1ull,	1ull},
+	{"ARI"                         ,	5,	1,	638,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OPS"                    ,	6,	1,	638,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM32S"                     ,	7,	1,	638,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM64S"                     ,	8,	1,	638,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM128S"                    ,	9,	1,	638,	"RO",	0,	0,	0ull,	0ull},
+	{"NOROPRPR"                    ,	10,	1,	638,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	638,	"RAZ",	1,	1,	0,	0},
+	{"TPH"                         ,	12,	2,	638,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	638,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	639,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	639,	"R/W",	0,	0,	0ull,	0ull},
+	{"ARI"                         ,	5,	1,	639,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP"                     ,	6,	1,	639,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP_EB"                  ,	7,	1,	639,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_RQ"                      ,	8,	1,	639,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_CP"                      ,	9,	1,	639,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_31"              ,	10,	22,	639,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	640,	"RAZ",	1,	1,	0,	0},
+	{"SLSV"                        ,	1,	7,	640,	"RO/WRSL",	1,	1,	0,	0},
+	{"CLS"                         ,	8,	1,	640,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	640,	"RAZ",	1,	1,	0,	0},
+	{"TLS"                         ,	0,	4,	641,	"R/W",	1,	0,	0,	2ull},
+	{"EC"                          ,	4,	1,	641,	"R/W",	0,	0,	0ull,	0ull},
+	{"HASD"                        ,	5,	1,	641,	"RO",	0,	0,	0ull,	0ull},
+	{"SDE"                         ,	6,	1,	641,	"RO",	0,	0,	0ull,	0ull},
+	{"TM"                          ,	7,	3,	641,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMC"                         ,	10,	1,	641,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSOS"                        ,	11,	1,	641,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDE"                         ,	12,	1,	641,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	641,	"RAZ",	1,	1,	0,	0},
+	{"CDL"                         ,	16,	1,	641,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	641,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	642,	"RO",	0,	0,	1ull,	1ull},
+	{"CV"                          ,	16,	4,	642,	"RO",	0,	0,	2ull,	2ull},
+	{"NCO"                         ,	20,	12,	642,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	643,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	643,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	643,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	643,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	643,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	643,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	643,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	643,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	643,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	643,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	643,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	643,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	643,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	643,	"RAZ",	1,	1,	0,	0},
+	{"UATOMBS"                     ,	24,	1,	643,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	643,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	644,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	644,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	644,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	644,	"RAZ",	1,	1,	0,	0},
+	{"UATOMBM"                     ,	24,	1,	644,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	644,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	645,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	645,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	645,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	645,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	645,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	645,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	645,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	645,	"RO",	0,	0,	2ull,	2ull},
+	{"UATOMBS"                     ,	24,	1,	645,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	645,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	646,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	646,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	646,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	647,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	647,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	647,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	647,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	648,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	648,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	648,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	648,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	648,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	648,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	650,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	651,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	652,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	653,	"R/W",	0,	1,	4143ull,	0},
+	{"RTL"                         ,	16,	16,	653,	"R/W",	0,	1,	12429ull,	0},
+	{"OMR"                         ,	0,	32,	654,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_14"               ,	8,	7,	655,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	655,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	655,	"R/W",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	656,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	656,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	656,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	656,	"R/W",	0,	0,	3ull,	3ull},
+	{"EASPML1"                     ,	30,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	656,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	657,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	657,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	657,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	657,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	657,	"R/W",	0,	0,	7ull,	7ull},
+	{"RESERVED_22_31"              ,	22,	10,	657,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	658,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"MFUNCN"                      ,	0,	8,	659,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_13"               ,	8,	6,	659,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	659,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	659,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	659,	"R/W",	0,	0,	0ull,	0ull},
+	{"CX_NFUNC"                    ,	29,	3,	659,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPIV"                       ,	0,	11,	660,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	660,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	660,	"R/W",	0,	0,	1ull,	1ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_DABORT_4UCPL"              ,	2,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_HANDLE_FLUSH"              ,	3,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_31"               ,	4,	28,	661,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	662,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	663,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	664,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	664,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	664,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	665,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	665,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	665,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	666,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	666,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	666,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	667,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	667,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	667,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	667,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	668,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	668,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	668,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	668,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	669,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	669,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	669,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	669,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	670,	"RO/WRSL",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	670,	"RO/WRSL",	0,	0,	96ull,	96ull},
+	{"RESERVED_20_20"              ,	20,	1,	670,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	670,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	670,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	670,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	670,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	671,	"RO/WRSL",	0,	0,	32ull,	32ull},
+	{"HEADER_CREDITS"              ,	12,	8,	671,	"RO/WRSL",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_20"              ,	20,	1,	671,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	671,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	671,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	672,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HEADER_CREDITS"              ,	12,	8,	672,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	672,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	672,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	672,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	673,	"RO/WRSL",	0,	0,	392ull,	392ull},
+	{"RESERVED_14_15"              ,	14,	2,	673,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	673,	"RO/WRSL",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	673,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	674,	"RO/WRSL",	0,	0,	136ull,	136ull},
+	{"RESERVED_14_15"              ,	14,	2,	674,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	674,	"RO/WRSL",	0,	0,	38ull,	38ull},
+	{"RESERVED_26_31"              ,	26,	6,	674,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	675,	"RO/WRSL",	0,	0,	392ull,	392ull},
+	{"RESERVED_14_15"              ,	14,	2,	675,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	675,	"RO/WRSL",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	675,	"RAZ",	1,	1,	0,	0},
+	{"N_FTS"                       ,	0,	8,	676,	"R/W",	0,	0,	128ull,	128ull},
+	{"LE"                          ,	8,	9,	676,	"R/W",	0,	0,	8ull,	8ull},
+	{"DSC"                         ,	17,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"CPYTS"                       ,	18,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTCRB"                       ,	19,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"S_D_E"                       ,	20,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	676,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	677,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	678,	"R/W",	0,	0,	0ull,	0ull},
+	{"VENDID"                      ,	0,	16,	679,	"R/W",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	679,	"R/W",	0,	0,	146ull,	146ull},
+	{"ISAE"                        ,	0,	1,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	680,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	680,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	680,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	680,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	680,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	680,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	680,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	680,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	680,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	680,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	680,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	680,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	681,	"R/W",	0,	0,	8ull,	8ull},
+	{"PI"                          ,	8,	8,	681,	"R/W",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	681,	"R/W",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	681,	"R/W",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	682,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	682,	"RO",	0,	0,	1ull,	1ull},
+	{"MFD"                         ,	23,	1,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	682,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_31"               ,	0,	32,	683,	"RO",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	684,	"RO",	1,	1,	0,	0},
+	{"PBNUM"                       ,	0,	8,	685,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBNUM"                       ,	8,	8,	685,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUBBNUM"                     ,	16,	8,	685,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLT"                         ,	24,	8,	685,	"RO",	0,	0,	0ull,	0ull},
+	{"IO32A"                       ,	0,	1,	686,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	686,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_BASE"                    ,	4,	4,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO32B"                       ,	8,	1,	686,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_11"               ,	9,	3,	686,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_LIMI"                    ,	12,	4,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_20"              ,	16,	5,	686,	"RAZ",	1,	1,	0,	0},
+	{"M66"                         ,	21,	1,	686,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	686,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	686,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	686,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	686,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	686,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	686,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	686,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	686,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	686,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	687,	"RO",	1,	1,	0,	0},
+	{"MB_ADDR"                     ,	4,	12,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_19"              ,	16,	4,	687,	"RO",	1,	1,	0,	0},
+	{"ML_ADDR"                     ,	20,	12,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64A"                      ,	0,	1,	688,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	688,	"RO",	1,	1,	0,	0},
+	{"LMEM_BASE"                   ,	4,	12,	688,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64B"                      ,	16,	1,	688,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_17_19"              ,	17,	3,	688,	"RO",	1,	1,	0,	0},
+	{"LMEM_LIMIT"                  ,	20,	12,	688,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_BASE"                   ,	0,	32,	689,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_LIMIT"                  ,	0,	32,	690,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_BASE"                    ,	0,	16,	691,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_LIMIT"                   ,	16,	16,	691,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP"                          ,	0,	8,	692,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	692,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	693,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	694,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	694,	"R/W",	0,	0,	1ull,	1ull},
+	{"PERE"                        ,	16,	1,	694,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	17,	1,	694,	"R/W",	0,	0,	0ull,	0ull},
+	{"ISAE"                        ,	18,	1,	694,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGAE"                        ,	19,	1,	694,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGA16D"                      ,	20,	1,	694,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAM"                         ,	21,	1,	694,	"RO",	0,	0,	0ull,	0ull},
+	{"SBRST"                       ,	22,	1,	694,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	23,	1,	694,	"RO",	0,	0,	0ull,	0ull},
+	{"PDT"                         ,	24,	1,	694,	"RO",	0,	0,	0ull,	0ull},
+	{"SDT"                         ,	25,	1,	694,	"RO",	0,	0,	0ull,	0ull},
+	{"DTS"                         ,	26,	1,	694,	"RO",	0,	0,	0ull,	0ull},
+	{"DTSEES"                      ,	27,	1,	694,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	694,	"RO",	1,	1,	0,	0},
+	{"PMCID"                       ,	0,	8,	695,	"RO",	0,	0,	1ull,	1ull},
+	{"NCP"                         ,	8,	8,	695,	"R/W",	0,	0,	80ull,	80ull},
+	{"PMSV"                        ,	16,	3,	695,	"R/W",	0,	0,	3ull,	3ull},
+	{"PME_CLOCK"                   ,	19,	1,	695,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	695,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	695,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	695,	"R/W",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	695,	"R/W",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	695,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	695,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	696,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	696,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	696,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	696,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	696,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	696,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	696,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	696,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	696,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	696,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	696,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	696,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	697,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	697,	"R/W",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	697,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	697,	"R/W",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	697,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	697,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	697,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	698,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	698,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	699,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	700,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	700,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	701,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	701,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	701,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	701,	"RO",	0,	0,	4ull,	4ull},
+	{"SI"                          ,	24,	1,	701,	"R/W",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	701,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	701,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	702,	"R/W",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	702,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	702,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	702,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL1AL"                       ,	9,	3,	702,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_14"              ,	12,	3,	702,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	702,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	702,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	702,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	702,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	702,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	703,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	703,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	703,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_15_15"              ,	15,	1,	703,	"RAZ",	1,	1,	0,	0},
+	{"CE_D"                        ,	16,	1,	703,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	703,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	703,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	703,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	703,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	703,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	703,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	704,	"R/W",	1,	1,	0,	0},
+	{"MLW"                         ,	4,	6,	704,	"R/W",	0,	0,	4ull,	4ull},
+	{"ASLPMS"                      ,	10,	2,	704,	"R/W",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	704,	"R/W",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	704,	"R/W",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	704,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	704,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	704,	"RO",	0,	0,	1ull,	1ull},
+	{"LBNC"                        ,	21,	1,	704,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"ASPM"                        ,	22,	1,	704,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_23_23"              ,	23,	1,	704,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	704,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	705,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	705,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	705,	"R/W",	0,	0,	1ull,	1ull},
+	{"LD"                          ,	4,	1,	705,	"R/W",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	705,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	705,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	705,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	705,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	705,	"R/W",	0,	0,	0ull,	0ull},
+	{"LBM_INT_ENB"                 ,	10,	1,	705,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAB_INT_ENB"                 ,	11,	1,	705,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	705,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	705,	"RO",	1,	1,	0,	0},
+	{"NLW"                         ,	20,	6,	705,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_26"              ,	26,	1,	705,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	705,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	705,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLLA"                        ,	29,	1,	705,	"RO",	0,	0,	0ull,	1ull},
+	{"LBM"                         ,	30,	1,	705,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LAB"                         ,	31,	1,	705,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ABP"                         ,	0,	1,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCP"                         ,	1,	1,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLSP"                       ,	2,	1,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIP"                         ,	3,	1,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	4,	1,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_S"                        ,	5,	1,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_C"                        ,	6,	1,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LV"                       ,	7,	8,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LS"                       ,	15,	2,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIP"                        ,	17,	1,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"NCCS"                        ,	18,	1,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS_NUM"                      ,	19,	13,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABP_EN"                      ,	0,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	1,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLS_EN"                     ,	2,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"PD_EN"                       ,	3,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCINT_EN"                    ,	4,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"HPINT_EN"                    ,	5,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIC"                         ,	6,	2,	707,	"R/W",	0,	0,	3ull,	3ull},
+	{"PIC"                         ,	8,	2,	707,	"R/W",	0,	0,	3ull,	3ull},
+	{"PCC"                         ,	10,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIC"                        ,	11,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLS_EN"                     ,	12,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	707,	"RAZ",	1,	1,	0,	0},
+	{"ABP_D"                       ,	16,	1,	707,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PF_D"                        ,	17,	1,	707,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLS_C"                      ,	18,	1,	707,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PD_C"                        ,	19,	1,	707,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CCINT_D"                     ,	20,	1,	707,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLSS"                       ,	21,	1,	707,	"RO",	0,	0,	0ull,	0ull},
+	{"PDS"                         ,	22,	1,	707,	"RO",	0,	0,	1ull,	1ull},
+	{"EMIS"                        ,	23,	1,	707,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLS_C"                      ,	24,	1,	707,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	707,	"RAZ",	1,	1,	0,	0},
+	{"SECEE"                       ,	0,	1,	708,	"R/W",	0,	0,	0ull,	0ull},
+	{"SENFEE"                      ,	1,	1,	708,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEFEE"                       ,	2,	1,	708,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMEIE"                       ,	3,	1,	708,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRSSVE"                      ,	4,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_15"               ,	5,	11,	708,	"RAZ",	1,	1,	0,	0},
+	{"CRSSV"                       ,	16,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	708,	"RAZ",	1,	1,	0,	0},
+	{"PME_RID"                     ,	0,	16,	709,	"RO",	0,	0,	0ull,	0ull},
+	{"PME_STAT"                    ,	16,	1,	709,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PME_PEND"                    ,	17,	1,	709,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	709,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTRS"                        ,	0,	4,	710,	"RO",	0,	0,	15ull,	15ull},
+	{"CTDS"                        ,	4,	1,	710,	"RO",	0,	0,	1ull,	1ull},
+	{"ARI"                         ,	5,	1,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OPS"                    ,	6,	1,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM32S"                     ,	7,	1,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM64S"                     ,	8,	1,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM128S"                    ,	9,	1,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"NOROPRPR"                    ,	10,	1,	710,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_11_11"              ,	11,	1,	710,	"RAZ",	1,	1,	0,	0},
+	{"TPH"                         ,	12,	2,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	710,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	711,	"R/W",	0,	0,	0ull,	0ull},
+	{"ARI"                         ,	5,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP"                     ,	6,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP_EB"                  ,	7,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_RQ"                      ,	8,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_CP"                      ,	9,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_31"              ,	10,	22,	711,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	712,	"RAZ",	1,	1,	0,	0},
+	{"SLSV"                        ,	1,	7,	712,	"RO/WRSL",	1,	1,	0,	0},
+	{"CLS"                         ,	8,	1,	712,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	712,	"RAZ",	1,	1,	0,	0},
+	{"TLS"                         ,	0,	4,	713,	"R/W",	1,	1,	0,	0},
+	{"EC"                          ,	4,	1,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"HASD"                        ,	5,	1,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDE"                         ,	6,	1,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"TM"                          ,	7,	3,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMC"                         ,	10,	1,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSOS"                        ,	11,	1,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDE"                         ,	12,	1,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	713,	"RAZ",	1,	1,	0,	0},
+	{"CDL"                         ,	16,	1,	713,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	713,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	714,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	715,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	716,	"RO",	0,	0,	1ull,	1ull},
+	{"CV"                          ,	16,	4,	716,	"RO",	0,	0,	2ull,	2ull},
+	{"NCO"                         ,	20,	12,	716,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	717,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	717,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	717,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	717,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	717,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	717,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	717,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	717,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	717,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	717,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	717,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	717,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	717,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	717,	"RAZ",	1,	1,	0,	0},
+	{"UATOMBS"                     ,	24,	1,	717,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	717,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	718,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	718,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	718,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	718,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	718,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	718,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	718,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	718,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	718,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	718,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	718,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	718,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	718,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	718,	"RAZ",	1,	1,	0,	0},
+	{"UATOMBM"                     ,	24,	1,	718,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	718,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	719,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	719,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	719,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	719,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	719,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	719,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	719,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	719,	"RO",	0,	0,	2ull,	2ull},
+	{"UATOMBS"                     ,	24,	1,	719,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	719,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	720,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	720,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	720,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	720,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	720,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	720,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	720,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	720,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	720,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	721,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	721,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	721,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	721,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	721,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	721,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	721,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	721,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	721,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	722,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	722,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	722,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	722,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	722,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	722,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	723,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	724,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	725,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	726,	"RO",	0,	0,	0ull,	0ull},
+	{"CERE"                        ,	0,	1,	727,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFERE"                       ,	1,	1,	727,	"R/W",	0,	0,	0ull,	0ull},
+	{"FERE"                        ,	2,	1,	727,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	727,	"RAZ",	1,	1,	0,	0},
+	{"ECR"                         ,	0,	1,	728,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_ECR"                   ,	1,	1,	728,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EFNFR"                       ,	2,	1,	728,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_EFNFR"                 ,	3,	1,	728,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FUF"                         ,	4,	1,	728,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFEMR"                       ,	5,	1,	728,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEMR"                        ,	6,	1,	728,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_26"               ,	7,	20,	728,	"RAZ",	1,	1,	0,	0},
+	{"AEIMN"                       ,	27,	5,	728,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECSI"                        ,	0,	16,	729,	"RO",	0,	0,	0ull,	0ull},
+	{"EFNFSI"                      ,	16,	16,	729,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	730,	"R/W",	0,	1,	4143ull,	0},
+	{"RTL"                         ,	16,	16,	730,	"R/W",	0,	1,	12429ull,	0},
+	{"OMR"                         ,	0,	32,	731,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	732,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_8_14"               ,	8,	7,	732,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	732,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	732,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	732,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	732,	"RO",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	733,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	733,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	733,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	733,	"R/W",	0,	0,	3ull,	3ull},
+	{"EASPML1"                     ,	30,	1,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	733,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	734,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	734,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	734,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	734,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	734,	"R/W",	0,	0,	15ull,	7ull},
+	{"RESERVED_22_31"              ,	22,	10,	734,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	735,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	735,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	735,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	735,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	735,	"R/W",	0,	0,	0ull,	0ull},
+	{"MFUNCN"                      ,	0,	8,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_13"               ,	8,	6,	736,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	736,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"CX_NFUNC"                    ,	29,	3,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPIV"                       ,	0,	11,	737,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	737,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	737,	"R/W",	0,	0,	1ull,	1ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	738,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	738,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_DABORT_4UCPL"              ,	2,	1,	738,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_HANDLE_FLUSH"              ,	3,	1,	738,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_31"               ,	4,	28,	738,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	739,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	740,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	741,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	741,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	741,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	742,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	742,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	742,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	743,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	743,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	743,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	744,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	744,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	744,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	744,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	745,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	745,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	745,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	745,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	746,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	746,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	746,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	746,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	747,	"R/W",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	747,	"R/W",	0,	0,	96ull,	96ull},
+	{"RESERVED_20_20"              ,	20,	1,	747,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	747,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	747,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	747,	"R/W",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	748,	"R/W",	0,	0,	32ull,	32ull},
+	{"HEADER_CREDITS"              ,	12,	8,	748,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_20"              ,	20,	1,	748,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	748,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	748,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	749,	"R/W",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	749,	"R/W",	0,	0,	96ull,	96ull},
+	{"RESERVED_20_20"              ,	20,	1,	749,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	749,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	749,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	750,	"R/W",	0,	0,	392ull,	392ull},
+	{"RESERVED_14_15"              ,	14,	2,	750,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	750,	"R/W",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	750,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	751,	"R/W",	0,	0,	136ull,	136ull},
+	{"RESERVED_14_15"              ,	14,	2,	751,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	751,	"R/W",	0,	0,	38ull,	38ull},
+	{"RESERVED_26_31"              ,	26,	6,	751,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	752,	"R/W",	0,	0,	392ull,	392ull},
+	{"RESERVED_14_15"              ,	14,	2,	752,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	752,	"R/W",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	752,	"RAZ",	1,	1,	0,	0},
+	{"N_FTS"                       ,	0,	8,	753,	"R/W",	0,	0,	128ull,	128ull},
+	{"LE"                          ,	8,	9,	753,	"R/W",	0,	0,	8ull,	8ull},
+	{"DSC"                         ,	17,	1,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"CPYTS"                       ,	18,	1,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTCRB"                       ,	19,	1,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"S_D_E"                       ,	20,	1,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	753,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	754,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	756,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	756,	"R/W",	0,	0,	1ull,	1ull},
+	{"HFD"                         ,	6,	1,	756,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAUSE"                       ,	7,	2,	756,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	756,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	756,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	756,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NP"                          ,	15,	1,	756,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	756,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_11"               ,	0,	12,	757,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_THD"                    ,	12,	1,	757,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_TFD"                    ,	13,	1,	757,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_XHD"                    ,	14,	1,	757,	"RO",	0,	0,	1ull,	1ull},
+	{"THOU_XFD"                    ,	15,	1,	757,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	757,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	758,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	758,	"RO",	0,	0,	0ull,	0ull},
+	{"HFD"                         ,	6,	1,	758,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	7,	2,	758,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	758,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	758,	"RO",	0,	0,	0ull,	0ull},
+	{"ACK"                         ,	14,	1,	758,	"RO",	0,	1,	0ull,	0},
+	{"NP"                          ,	15,	1,	758,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	758,	"RAZ",	1,	1,	0,	0},
+	{"LINK_OK"                     ,	0,	1,	759,	"RO",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	1,	1,	759,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	2,	1,	759,	"RO",	0,	0,	0ull,	1ull},
+	{"SPD"                         ,	3,	2,	759,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	5,	2,	759,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	759,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD_EN"                   ,	0,	1,	760,	"R/W",	0,	0,	0ull,	1ull},
+	{"XMIT_EN"                     ,	1,	1,	760,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_ERR_EN"                   ,	2,	1,	760,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFU_EN"                   ,	3,	1,	760,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFO_EN"                   ,	4,	1,	760,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXBAD_EN"                    ,	5,	1,	760,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXERR_EN"                    ,	6,	1,	760,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	7,	1,	760,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXLOCK_EN"                   ,	8,	1,	760,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_BAD_EN"                   ,	9,	1,	760,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNC_BAD_EN"                 ,	10,	1,	760,	"R/W",	0,	0,	0ull,	1ull},
+	{"DUP"                         ,	11,	1,	760,	"R/W",	0,	0,	0ull,	1ull},
+	{"DBG_SYNC_EN"                 ,	12,	1,	760,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	760,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD"                      ,	0,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	1,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_ERR"                      ,	2,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFU"                      ,	3,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFO"                      ,	4,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXBAD"                       ,	5,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXERR"                       ,	6,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	7,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXLOCK"                      ,	8,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	9,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	10,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	11,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBG_SYNC"                    ,	12,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	761,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	16,	762,	"R/W",	0,	1,	1094ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	762,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	763,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	763,	"RAZ",	1,	1,	0,	0},
+	{"SAMP_PT"                     ,	0,	7,	764,	"R/W",	0,	1,	1ull,	0},
+	{"AN_OVRD"                     ,	7,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE"                        ,	8,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAC_PHY"                     ,	9,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK2"                    ,	10,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMXENO"                      ,	11,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"SGMII"                       ,	12,	1,	764,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	764,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	765,	"RAZ",	1,	1,	0,	0},
+	{"UNI"                         ,	5,	1,	765,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDMSB"                      ,	6,	1,	765,	"R/W",	0,	0,	1ull,	1ull},
+	{"COLTST"                      ,	7,	1,	765,	"R/W",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	8,	1,	765,	"R/W",	0,	0,	1ull,	1ull},
+	{"RST_AN"                      ,	9,	1,	765,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	765,	"RAZ",	1,	1,	0,	0},
+	{"PWR_DN"                      ,	11,	1,	765,	"R/W",	0,	0,	1ull,	0ull},
+	{"AN_EN"                       ,	12,	1,	765,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDLSB"                      ,	13,	1,	765,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK1"                    ,	14,	1,	765,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	765,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	765,	"RAZ",	1,	1,	0,	0},
+	{"EXTND"                       ,	0,	1,	766,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	766,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LNK_ST"                      ,	2,	1,	766,	"RO",	0,	0,	0ull,	1ull},
+	{"AN_ABIL"                     ,	3,	1,	766,	"RO",	0,	0,	1ull,	1ull},
+	{"RM_FLT"                      ,	4,	1,	766,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	5,	1,	766,	"RO",	0,	0,	0ull,	0ull},
+	{"PRB_SUP"                     ,	6,	1,	766,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_7"                ,	7,	1,	766,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EXT_ST"                      ,	8,	1,	766,	"RO",	0,	0,	1ull,	1ull},
+	{"HUN_T2HD"                    ,	9,	1,	766,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T2FD"                    ,	10,	1,	766,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_HD"                      ,	11,	1,	766,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_FD"                      ,	12,	1,	766,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XHD"                     ,	13,	1,	766,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XFD"                     ,	14,	1,	766,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T4"                      ,	15,	1,	766,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	766,	"RAZ",	1,	1,	0,	0},
+	{"AN_ST"                       ,	0,	4,	767,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	4,	1,	767,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	5,	4,	767,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	9,	1,	767,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_ST"                       ,	10,	5,	767,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_BAD"                      ,	15,	1,	767,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	767,	"RAZ",	1,	1,	0,	0},
+	{"BIT_LOCK"                    ,	0,	1,	768,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	1,	1,	768,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	768,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	769,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	769,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	769,	"R/W",	0,	0,	2ull,	2ull},
+	{"DUP"                         ,	12,	1,	769,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_13"              ,	13,	1,	769,	"RAZ",	0,	1,	0ull,	0},
+	{"ACK"                         ,	14,	1,	769,	"RO",	0,	0,	0ull,	0ull},
+	{"LINK"                        ,	15,	1,	769,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	769,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	770,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	770,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	770,	"RO",	0,	0,	0ull,	2ull},
+	{"DUP"                         ,	12,	1,	770,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_14"              ,	13,	2,	770,	"RAZ",	0,	1,	0ull,	0},
+	{"LINK"                        ,	15,	1,	770,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	770,	"RAZ",	1,	1,	0,	0},
+	{"ORD_ST"                      ,	0,	4,	771,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_BAD"                      ,	4,	1,	771,	"RO",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	5,	2,	771,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	771,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTORXPL"                    ,	2,	1,	772,	"RO",	0,	0,	0ull,	0ull},
+	{"RXOVRD"                      ,	3,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	772,	"RAZ",	1,	1,	0,	0},
+	{"L0SYNC"                      ,	0,	1,	773,	"RO",	0,	0,	0ull,	1ull},
+	{"L1SYNC"                      ,	1,	1,	773,	"RO",	0,	0,	0ull,	1ull},
+	{"L2SYNC"                      ,	2,	1,	773,	"RO",	0,	0,	0ull,	1ull},
+	{"L3SYNC"                      ,	3,	1,	773,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_10"               ,	4,	7,	773,	"RAZ",	1,	1,	0,	0},
+	{"PATTST"                      ,	11,	1,	773,	"RO",	0,	0,	0ull,	0ull},
+	{"ALIGND"                      ,	12,	1,	773,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_63"              ,	13,	51,	773,	"RAZ",	1,	1,	0,	0},
+	{"BIST_STATUS"                 ,	0,	1,	774,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	774,	"RAZ",	1,	1,	0,	0},
+	{"BITLCK0"                     ,	0,	1,	775,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK1"                     ,	1,	1,	775,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK2"                     ,	2,	1,	775,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK3"                     ,	3,	1,	775,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	775,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	776,	"RAZ",	1,	1,	0,	0},
+	{"SPD"                         ,	2,	4,	776,	"RO",	0,	0,	0ull,	0ull},
+	{"SPDSEL0"                     ,	6,	1,	776,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_10"               ,	7,	4,	776,	"RAZ",	1,	1,	0,	0},
+	{"LO_PWR"                      ,	11,	1,	776,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_12_12"              ,	12,	1,	776,	"RAZ",	1,	1,	0,	0},
+	{"SPDSEL1"                     ,	13,	1,	776,	"RO",	0,	0,	1ull,	1ull},
+	{"LOOPBCK1"                    ,	14,	1,	776,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	776,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	776,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	2,	777,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	777,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT_EN"                    ,	0,	1,	778,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	1,	1,	778,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXSYNBAD_EN"                 ,	2,	1,	778,	"R/W",	0,	0,	0ull,	1ull},
+	{"BITLCKLS_EN"                 ,	3,	1,	778,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNLOS_EN"                   ,	4,	1,	778,	"R/W",	0,	0,	0ull,	1ull},
+	{"ALGNLOS_EN"                  ,	5,	1,	778,	"R/W",	0,	0,	0ull,	1ull},
+	{"DBG_SYNC_EN"                 ,	6,	1,	778,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	778,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT"                       ,	0,	1,	779,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	1,	1,	779,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXSYNBAD"                    ,	2,	1,	779,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BITLCKLS"                    ,	3,	1,	779,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNLOS"                      ,	4,	1,	779,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALGNLOS"                     ,	5,	1,	779,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBG_SYNC"                    ,	6,	1,	779,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	779,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	780,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	780,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	780,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DROP_LN"                     ,	4,	2,	780,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENC_MODE"                    ,	6,	1,	780,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	780,	"RAZ",	1,	1,	0,	0},
+	{"GMXENO"                      ,	0,	1,	781,	"R/W",	0,	0,	0ull,	0ull},
+	{"XAUI"                        ,	1,	1,	781,	"RO",	1,	1,	0,	0},
+	{"RX_SWAP"                     ,	2,	1,	781,	"R/W",	0,	1,	0ull,	0},
+	{"TX_SWAP"                     ,	3,	1,	781,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	781,	"RAZ",	1,	1,	0,	0},
+	{"SYNC0ST"                     ,	0,	4,	782,	"RO",	0,	1,	0ull,	0},
+	{"SYNC1ST"                     ,	4,	4,	782,	"RO",	0,	1,	0ull,	0},
+	{"SYNC2ST"                     ,	8,	4,	782,	"RO",	0,	1,	0ull,	0},
+	{"SYNC3ST"                     ,	12,	4,	782,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	782,	"RAZ",	1,	1,	0,	0},
+	{"TENGB"                       ,	0,	1,	783,	"RO",	0,	0,	1ull,	1ull},
+	{"TENPASST"                    ,	1,	1,	783,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	783,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	784,	"RAZ",	1,	1,	0,	0},
+	{"LPABLE"                      ,	1,	1,	784,	"RO",	0,	0,	1ull,	1ull},
+	{"RCV_LNK"                     ,	2,	1,	784,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_6"                ,	3,	4,	784,	"RAZ",	1,	1,	0,	0},
+	{"FLT"                         ,	7,	1,	784,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	784,	"RAZ",	1,	1,	0,	0},
+	{"TENGB_R"                     ,	0,	1,	785,	"RO",	0,	0,	0ull,	0ull},
+	{"TENGB_X"                     ,	1,	1,	785,	"RO",	0,	0,	1ull,	1ull},
+	{"TENGB_W"                     ,	2,	1,	785,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_9"                ,	3,	7,	785,	"RAZ",	1,	1,	0,	0},
+	{"RCVFLT"                      ,	10,	1,	785,	"RC",	0,	0,	0ull,	0ull},
+	{"XMTFLT"                      ,	11,	1,	785,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_13"              ,	12,	2,	785,	"RAZ",	1,	1,	0,	0},
+	{"DEV"                         ,	14,	2,	785,	"RO",	0,	0,	2ull,	2ull},
+	{"RESERVED_16_63"              ,	16,	48,	785,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	786,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	786,	"R/W",	0,	0,	0ull,	0ull},
+	{"XOR_TXPLRT"                  ,	2,	4,	786,	"R/W",	0,	0,	0ull,	0ull},
+	{"XOR_RXPLRT"                  ,	6,	4,	786,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	786,	"RAZ",	1,	1,	0,	0},
+	{"TX_ST"                       ,	0,	3,	787,	"RO",	0,	1,	0ull,	0},
+	{"RX_ST"                       ,	3,	2,	787,	"RO",	0,	1,	0ull,	0},
+	{"ALGN_ST"                     ,	5,	3,	787,	"RO",	0,	1,	0ull,	0},
+	{"RXBAD"                       ,	8,	1,	787,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN0BAD"                     ,	9,	1,	787,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN1BAD"                     ,	10,	1,	787,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN2BAD"                     ,	11,	1,	787,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN3BAD"                     ,	12,	1,	787,	"RO",	0,	0,	0ull,	0ull},
+	{"TERM_ERR"                    ,	13,	1,	787,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	787,	"RAZ",	1,	1,	0,	0},
+	{"ADDR_V"                      ,	0,	1,	788,	"R/W",	0,	1,	0ull,	0},
+	{"END_SWP"                     ,	1,	2,	788,	"R/W",	0,	1,	0ull,	0},
+	{"CA"                          ,	3,	1,	788,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR_IDX"                    ,	4,	16,	788,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	788,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	789,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	3,	35,	789,	"R/W",	0,	0,	34359738367ull,	34359738367ull},
+	{"RESERVED_38_63"              ,	38,	26,	789,	"RAZ",	1,	1,	0,	0},
+	{"BAR2_CAX"                    ,	0,	1,	790,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	1,	2,	790,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	3,	1,	790,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR1_SIZ"                    ,	4,	3,	790,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_63"               ,	7,	57,	790,	"RAZ",	1,	1,	0,	0},
+	{"SOT"                         ,	0,	1,	791,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR0"                      ,	1,	1,	791,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR1"                      ,	2,	1,	791,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA3"                     ,	3,	1,	791,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA2"                     ,	4,	1,	791,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA1"                     ,	5,	1,	791,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA0"                     ,	6,	1,	791,	"RO",	0,	0,	0ull,	0ull},
+	{"RETRY"                       ,	7,	1,	791,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	791,	"RAZ",	1,	1,	0,	0},
+	{"PPF"                         ,	0,	1,	792,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TC0"                     ,	1,	1,	792,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TCF1"                    ,	2,	1,	792,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TNF"                     ,	3,	1,	792,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF0"                    ,	4,	1,	792,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF1"                    ,	5,	1,	792,	"RO",	0,	0,	0ull,	0ull},
+	{"PEAI_P2E"                    ,	6,	1,	792,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_P"                       ,	7,	1,	792,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_N"                       ,	8,	1,	792,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_CPL"                     ,	9,	1,	792,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	792,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	32,	793,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	793,	"R/W",	0,	1,	0ull,	0},
+	{"ADDR"                        ,	0,	32,	794,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	794,	"R/W",	0,	1,	0ull,	0},
+	{"TAG"                         ,	0,	32,	795,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	795,	"RAZ",	1,	1,	0,	0},
+	{"INV_LCRC"                    ,	0,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_ECRC"                    ,	1,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAST_LM"                     ,	2,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_CTLP"                     ,	3,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_ENB"                     ,	4,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLY_ONE"                     ,	5,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"NF_ECRC"                     ,	6,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_8"                ,	7,	2,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"OB_P_CMD"                    ,	9,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XPME"                     ,	10,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XTOFF"                    ,	11,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	796,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CFG_RTRY"                    ,	16,	16,	796,	"R/W",	0,	0,	0ull,	32ull},
+	{"RESERVED_32_33"              ,	32,	2,	796,	"RAZ",	1,	1,	0,	0},
+	{"PBUS"                        ,	34,	8,	796,	"RO",	1,	1,	0,	0},
+	{"DNUM"                        ,	42,	5,	796,	"RO",	1,	1,	0,	0},
+	{"AUTO_SD"                     ,	47,	1,	796,	"RO",	1,	1,	0,	0},
+	{"RESERVED_48_63"              ,	48,	16,	796,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	797,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	798,	"RAZ",	1,	1,	0,	0},
+	{"AUX_EN"                      ,	0,	1,	799,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_EN"                       ,	1,	1,	799,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_STAT"                     ,	2,	1,	799,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_DST"                      ,	3,	1,	799,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	799,	"RO",	1,	1,	0,	0},
+	{"NUM"                         ,	0,	6,	800,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	800,	"RAZ",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	801,	"R/W",	0,	0,	0ull,	1ull},
+	{"SE"                          ,	1,	1,	801,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEI"                        ,	2,	1,	801,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEM"                        ,	3,	1,	801,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B1"                       ,	4,	1,	801,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B2"                       ,	5,	1,	801,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_BX"                       ,	6,	1,	801,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B1"                       ,	7,	1,	801,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B2"                       ,	8,	1,	801,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_BX"                       ,	9,	1,	801,	"R/W",	0,	0,	0ull,	1ull},
+	{"EXC"                         ,	10,	1,	801,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDLK"                        ,	11,	1,	801,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_ER"                      ,	12,	1,	801,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_DR"                      ,	13,	1,	801,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_14_63"              ,	14,	50,	801,	"RAZ",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	802,	"R/W",	0,	0,	0ull,	1ull},
+	{"SE"                          ,	1,	1,	802,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEI"                        ,	2,	1,	802,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEM"                        ,	3,	1,	802,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B1"                       ,	4,	1,	802,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B2"                       ,	5,	1,	802,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_BX"                       ,	6,	1,	802,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B1"                       ,	7,	1,	802,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B2"                       ,	8,	1,	802,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_BX"                       ,	9,	1,	802,	"R/W",	0,	0,	0ull,	1ull},
+	{"EXC"                         ,	10,	1,	802,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDLK"                        ,	11,	1,	802,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_ER"                      ,	12,	1,	802,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_DR"                      ,	13,	1,	802,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_14_63"              ,	14,	50,	802,	"RAZ",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	803,	"RO",	0,	0,	0ull,	0ull},
+	{"SE"                          ,	1,	1,	803,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PMEI"                        ,	2,	1,	803,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEM"                        ,	3,	1,	803,	"RO",	0,	0,	0ull,	0ull},
+	{"UP_B1"                       ,	4,	1,	803,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UP_B2"                       ,	5,	1,	803,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UP_BX"                       ,	6,	1,	803,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_B1"                       ,	7,	1,	803,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_B2"                       ,	8,	1,	803,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_BX"                       ,	9,	1,	803,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EXC"                         ,	10,	1,	803,	"RO",	0,	0,	0ull,	0ull},
+	{"RDLK"                        ,	11,	1,	803,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS_ER"                      ,	12,	1,	803,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS_DR"                      ,	13,	1,	803,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	803,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_13"               ,	0,	14,	804,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	14,	50,	804,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_25"               ,	0,	26,	805,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	26,	38,	805,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_40"               ,	0,	41,	806,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	41,	23,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_11"               ,	0,	12,	807,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	12,	52,	807,	"R/W",	0,	1,	4503599627370495ull,	0},
+	{"RESERVED_0_11"               ,	0,	12,	808,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	12,	52,	808,	"R/W",	0,	1,	4503599627370495ull,	0},
+	{"SLI_P"                       ,	0,	8,	809,	"R/W",	0,	0,	128ull,	128ull},
+	{"SLI_NP"                      ,	8,	8,	809,	"R/W",	0,	0,	16ull,	16ull},
+	{"SLI_CPL"                     ,	16,	8,	809,	"R/W",	0,	0,	128ull,	128ull},
+	{"PEM_P"                       ,	24,	8,	809,	"R/W",	0,	0,	128ull,	128ull},
+	{"PEM_NP"                      ,	32,	8,	809,	"R/W",	0,	0,	16ull,	16ull},
+	{"PEM_CPL"                     ,	40,	8,	809,	"R/W",	0,	0,	128ull,	128ull},
+	{"PEAI_PPF"                    ,	48,	8,	809,	"R/W",	0,	0,	128ull,	128ull},
+	{"RESERVED_56_63"              ,	56,	8,	809,	"RAZ",	1,	1,	0,	0},
+	{"SKIP1"                       ,	0,	7,	810,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	810,	"RAZ",	1,	1,	0,	0},
+	{"SKIP2"                       ,	8,	7,	810,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	810,	"RAZ",	1,	1,	0,	0},
+	{"SKIP3"                       ,	16,	7,	810,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_31"              ,	23,	9,	810,	"RAZ",	1,	1,	0,	0},
+	{"BIT0"                        ,	32,	6,	810,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_39"              ,	38,	2,	810,	"RAZ",	1,	1,	0,	0},
+	{"BIT1"                        ,	40,	6,	810,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_46_55"              ,	46,	10,	810,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	56,	1,	810,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_57_63"              ,	57,	7,	810,	"RAZ",	1,	1,	0,	0},
+	{"LOWATER"                     ,	0,	5,	811,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_5_7"                ,	5,	3,	811,	"RAZ",	0,	1,	0ull,	0},
+	{"HIWATER"                     ,	8,	5,	811,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_13_62"              ,	13,	50,	811,	"RAZ",	0,	1,	0ull,	0},
+	{"BCKPRS"                      ,	63,	1,	811,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	20,	812,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	812,	"RAZ",	1,	1,	0,	0},
+	{"CLKEN"                       ,	0,	1,	813,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	813,	"RAZ",	0,	1,	0ull,	0},
+	{"DPRT"                        ,	0,	16,	814,	"R/W",	0,	0,	0ull,	0ull},
+	{"UDP"                         ,	16,	1,	814,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP"                         ,	17,	1,	814,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	814,	"RAZ",	1,	1,	0,	0},
+	{"MAP0"                        ,	0,	4,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP0"                        ,	0,	4,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINLEN"                      ,	0,	16,	817,	"R/W",	0,	0,	64ull,	64ull},
+	{"MAXLEN"                      ,	16,	16,	817,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_32_63"              ,	32,	32,	817,	"RAZ",	1,	1,	0,	0},
+	{"NIP_SHF"                     ,	0,	3,	818,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	818,	"RAZ",	1,	1,	0,	0},
+	{"RAW_SHF"                     ,	8,	3,	818,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	818,	"RAZ",	1,	1,	0,	0},
+	{"MAX_L2"                      ,	16,	1,	818,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_UDP"                     ,	17,	1,	818,	"R/W",	0,	0,	1ull,	1ull},
+	{"TAG_SYN"                     ,	18,	1,	818,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	818,	"RAZ",	1,	1,	0,	0},
+	{"IP_CHK"                      ,	0,	1,	819,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_MAL"                      ,	1,	1,	819,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_HOP"                      ,	2,	1,	819,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP4_OPTS"                    ,	3,	1,	819,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP6_EEXT"                    ,	4,	2,	819,	"R/W",	0,	0,	1ull,	3ull},
+	{"RESERVED_6_7"                ,	6,	2,	819,	"RAZ",	1,	1,	0,	0},
+	{"L4_MAL"                      ,	8,	1,	819,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_PRT"                      ,	9,	1,	819,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_CHK"                      ,	10,	1,	819,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_LEN"                      ,	11,	1,	819,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCP_FLAG"                    ,	12,	1,	819,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2_MAL"                      ,	13,	1,	819,	"R/W",	0,	0,	1ull,	1ull},
+	{"VS_QOS"                      ,	14,	1,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"VS_WQE"                      ,	15,	1,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNRS"                       ,	16,	1,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	819,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RING_EN"                     ,	20,	1,	819,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_21_23"              ,	21,	3,	819,	"RAZ",	1,	1,	0,	0},
+	{"DSA_GRP_SID"                 ,	24,	1,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_SCMD"                ,	25,	1,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_TVID"                ,	26,	1,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"IHMSK_DIS"                   ,	27,	1,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	819,	"RAZ",	1,	1,	0,	0},
+	{"PRI"                         ,	0,	6,	820,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	820,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	8,	3,	820,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	820,	"RAZ",	1,	1,	0,	0},
+	{"UP_QOS"                      ,	12,	1,	820,	"RAZ",	0,	1,	0ull,	0},
+	{"RESERVED_13_63"              ,	13,	51,	820,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	821,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	821,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	821,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	821,	"R/W",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	821,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	821,	"R/W",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	821,	"R/W",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	821,	"R/W",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	821,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	821,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	821,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	821,	"R/W",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	821,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	821,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	822,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	822,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	822,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	822,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	822,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	822,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	822,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	822,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	822,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	822,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	822,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	822,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	822,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	822,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	3,	823,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	823,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	824,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	2,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_EN"                      ,	10,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"HIGIG_EN"                    ,	11,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRC_EN"                      ,	12,	1,	824,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	824,	"RAZ",	1,	1,	0,	0},
+	{"QOS_VLAN"                    ,	16,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_DIFF"                    ,	17,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VOD"                     ,	18,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VSEL"                    ,	19,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_WAT"                     ,	20,	4,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS"                         ,	24,	3,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_QOS"                      ,	27,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT"                     ,	28,	4,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"INST_HDR"                    ,	32,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"DYN_RS"                      ,	33,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_INC"                     ,	34,	2,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWDRP"                      ,	36,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	824,	"RAZ",	1,	1,	0,	0},
+	{"QOS_WAT_47"                  ,	40,	4,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT_47"                  ,	44,	4,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR_EN"                   ,	48,	1,	824,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR_EN"                   ,	49,	1,	824,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR_EN"                   ,	50,	1,	824,	"R/W",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	51,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	52,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_63"              ,	53,	11,	824,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_35"               ,	0,	36,	825,	"RAZ",	1,	1,	0,	0},
+	{"ALT_SKP_EN"                  ,	36,	1,	825,	"R/W",	0,	1,	0ull,	0},
+	{"ALT_SKP_SEL"                 ,	37,	2,	825,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_39_63"              ,	39,	25,	825,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	0,	4,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"NON_TAG_TYPE"                ,	4,	2,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_TAG_TYPE"                ,	6,	2,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_TAG_TYPE"                ,	8,	2,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP4_TAG_TYPE"               ,	10,	2,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP6_TAG_TYPE"               ,	12,	2,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SRC_FLAG"                ,	14,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SRC_FLAG"                ,	15,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DST_FLAG"                ,	16,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DST_FLAG"                ,	17,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_PCTL_FLAG"               ,	18,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_NXTH_FLAG"               ,	19,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SPRT_FLAG"               ,	20,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SPRT_FLAG"               ,	21,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DPRT_FLAG"               ,	22,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DPRT_FLAG"               ,	23,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_PRT_FLAG"                ,	24,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VLAN"                    ,	25,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VS"                      ,	26,	2,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_MODE"                    ,	28,	2,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG_MSKIP"                ,	30,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG"                      ,	31,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGMASK"                  ,	32,	4,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGBASE"                  ,	36,	4,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	826,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	827,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	828,	"RAZ",	1,	1,	0,	0},
+	{"QOS1"                        ,	4,	3,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	828,	"RAZ",	1,	1,	0,	0},
+	{"MATCH_VALUE"                 ,	0,	16,	829,	"R/W",	0,	0,	0ull,	0ull},
+	{"MATCH_TYPE"                  ,	16,	3,	829,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	829,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	20,	3,	829,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	829,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	24,	4,	829,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	829,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	32,	16,	829,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	829,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	0,	56,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	830,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	0,	1,	831,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	831,	"RAZ",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	832,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	832,	"R/W",	0,	1,	0ull,	0},
+	{"MCAST"                       ,	0,	32,	833,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	833,	"R/W",	0,	1,	0ull,	0},
+	{"MCAST"                       ,	0,	32,	834,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	834,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	835,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	835,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	836,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	836,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	837,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	837,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	838,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	838,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	839,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	839,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	840,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	840,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	841,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	841,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	842,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	842,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	843,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	843,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	844,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	844,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	845,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	845,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	846,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	846,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	847,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	847,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	848,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	848,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	849,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	849,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	850,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	850,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	850,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	851,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	851,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	851,	"RO",	1,	1,	0,	0},
+	{"TYPE0"                       ,	0,	16,	852,	"R/W",	0,	0,	33024ull,	33024ull},
+	{"TYPE1"                       ,	16,	16,	852,	"R/W",	0,	0,	33024ull,	33024ull},
+	{"TYPE2"                       ,	32,	16,	852,	"R/W",	0,	0,	33024ull,	33024ull},
+	{"TYPE3"                       ,	48,	16,	852,	"R/W",	0,	0,	33024ull,	33024ull},
+	{"DRP_OCTS"                    ,	0,	32,	853,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	853,	"R/W",	0,	1,	0ull,	0},
+	{"MCAST"                       ,	0,	32,	854,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	854,	"R/W",	0,	1,	0ull,	0},
+	{"MCAST"                       ,	0,	32,	855,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	855,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	856,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	856,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	857,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	857,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	858,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	858,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	859,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	859,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	860,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	860,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	861,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	861,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	862,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	862,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	863,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	863,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	864,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	864,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	32,	865,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	865,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	866,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	866,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	867,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	867,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	867,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	867,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	868,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	868,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	868,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	868,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	868,	"RO",	1,	0,	0,	0ull},
+	{"PTRS2"                       ,	0,	17,	869,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	869,	"RAZ",	1,	1,	0,	0},
+	{"PTRS1"                       ,	32,	17,	869,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	869,	"RAZ",	1,	1,	0,	0},
+	{"MOD"                         ,	0,	3,	870,	"RO",	1,	0,	0,	0ull},
+	{"CNT"                         ,	3,	13,	870,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	16,	1,	870,	"RO",	1,	0,	0,	0ull},
+	{"LEN"                         ,	17,	1,	870,	"RO",	1,	0,	0,	0ull},
+	{"SOP"                         ,	18,	1,	870,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	19,	3,	870,	"RO",	1,	0,	0,	0ull},
+	{"MAJ"                         ,	22,	1,	870,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	870,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	871,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	871,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	871,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	871,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	872,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	872,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	872,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	872,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	872,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	873,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	874,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	874,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	874,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	874,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	874,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	875,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	3,	876,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	3,	2,	876,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	5,	1,	876,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	6,	1,	876,	"RO",	1,	0,	0,	0ull},
+	{"CHK_ONCE"                    ,	7,	1,	876,	"RO",	1,	0,	0,	0ull},
+	{"INIT_DWRITE"                 ,	8,	1,	876,	"RO",	1,	0,	0,	0ull},
+	{"DREAD_SOP"                   ,	9,	1,	876,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	10,	2,	876,	"RO",	1,	0,	0,	0ull},
+	{"CMND_OFF"                    ,	12,	6,	876,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	18,	16,	876,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	34,	6,	876,	"RO",	1,	0,	0,	0ull},
+	{"CURR_OFF"                    ,	40,	16,	876,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	56,	8,	876,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	0,	8,	877,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	8,	40,	877,	"RO",	1,	0,	0,	0ull},
+	{"NXT_INFLT"                   ,	48,	6,	877,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR_3"                     ,	54,	1,	877,	"RO",	1,	0,	0,	0ull},
+	{"PTP"                         ,	55,	1,	877,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	877,	"RAZ",	1,	1,	0,	0},
+	{"QID_BASE"                    ,	0,	8,	878,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	8,	4,	878,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFMAX"                  ,	12,	4,	878,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	16,	5,	878,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	21,	3,	878,	"RO",	1,	0,	0,	0ull},
+	{"STATC"                       ,	24,	1,	878,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	25,	1,	878,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTED"                   ,	26,	1,	878,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	27,	1,	878,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	878,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFTHS"                  ,	29,	4,	878,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFRES"                  ,	33,	4,	878,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	878,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	6,	879,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	6,	6,	879,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	12,	33,	879,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	45,	13,	879,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	58,	1,	879,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	59,	5,	879,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	3,	880,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	3,	1,	880,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	4,	1,	880,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	5,	1,	880,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	6,	1,	880,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	880,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	8,	20,	880,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	880,	"RO",	1,	0,	0,	0ull},
+	{"QID_IDX"                     ,	29,	4,	880,	"RO",	1,	1,	0,	0},
+	{"RESERVED_33_33"              ,	33,	1,	880,	"RAZ",	1,	1,	0,	0},
+	{"QID_QQOS"                    ,	34,	8,	880,	"RO",	1,	1,	0,	0},
+	{"RESERVED_42_63"              ,	42,	22,	880,	"RAZ",	1,	1,	0,	0},
+	{"PTRS3"                       ,	0,	17,	881,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	881,	"RAZ",	1,	1,	0,	0},
+	{"PTRS0"                       ,	32,	17,	881,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	881,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	882,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	882,	"R/W",	1,	0,	0,	0ull},
+	{"BP_PORT"                     ,	10,	6,	882,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_52"              ,	16,	37,	882,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	882,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	61,	1,	882,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	882,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	883,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	883,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_10_52"              ,	10,	43,	883,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	883,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	883,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	884,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	884,	"RAZ",	1,	1,	0,	0},
+	{"RATE_PKT"                    ,	8,	24,	884,	"R/W",	1,	0,	0,	0ull},
+	{"RATE_WORD"                   ,	32,	19,	884,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	884,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	885,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	885,	"RAZ",	1,	1,	0,	0},
+	{"RATE_LIM"                    ,	8,	24,	885,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	885,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE"                       ,	0,	7,	886,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	7,	6,	886,	"WR0",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	13,	3,	886,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	16,	1,	886,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	17,	36,	886,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	886,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	886,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	886,	"R/W",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	886,	"R/W",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	7,	887,	"R/W",	1,	0,	0,	0ull},
+	{"PID"                         ,	7,	6,	887,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	887,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	887,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	887,	"RAZ",	1,	1,	0,	0},
+	{"DAT_PTR"                     ,	0,	4,	888,	"RO",	1,	0,	0,	0ull},
+	{"DAT_DAT"                     ,	4,	2,	888,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CTL"                     ,	6,	2,	888,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QSB"                     ,	8,	3,	888,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QCB"                     ,	11,	2,	888,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	13,	2,	888,	"RO",	1,	0,	0,	0ull},
+	{"PRT_PSB"                     ,	15,	8,	888,	"RO",	1,	0,	0,	0ull},
+	{"PRT_NXT"                     ,	23,	1,	888,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CHK"                     ,	24,	3,	888,	"RO",	1,	0,	0,	0ull},
+	{"OUT_WIF"                     ,	27,	1,	888,	"RO",	1,	0,	0,	0ull},
+	{"OUT_STA"                     ,	28,	1,	888,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CTL"                     ,	29,	3,	888,	"RO",	1,	0,	0,	0ull},
+	{"OUT_DAT"                     ,	32,	1,	888,	"RO",	1,	0,	0,	0ull},
+	{"IOB"                         ,	33,	1,	888,	"RO",	1,	0,	0,	0ull},
+	{"CSR"                         ,	34,	1,	888,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	888,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	13,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	889,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	64,	890,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	891,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	892,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"ENGINE0"                     ,	0,	4,	894,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE1"                     ,	4,	4,	894,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE2"                     ,	8,	4,	894,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE3"                     ,	12,	4,	894,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE4"                     ,	16,	4,	894,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE5"                     ,	20,	4,	894,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE6"                     ,	24,	4,	894,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE7"                     ,	28,	4,	894,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE8"                     ,	32,	4,	894,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE9"                     ,	36,	4,	894,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE10"                    ,	40,	4,	894,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE11"                    ,	44,	4,	894,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE12"                    ,	48,	4,	894,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE13"                    ,	52,	4,	894,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_56_63"              ,	56,	8,	894,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	14,	895,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	895,	"RAZ",	1,	1,	0,	0},
+	{"PARITY"                      ,	0,	1,	896,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	896,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	896,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	896,	"RAZ",	1,	1,	0,	0},
+	{"ENA_PKO"                     ,	0,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	897,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_6"                ,	4,	3,	897,	"RAZ",	1,	1,	0,	0},
+	{"DIS_PERF2"                   ,	7,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIS_PERF3"                   ,	8,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	897,	"RAZ",	1,	1,	0,	0},
+	{"MODE0"                       ,	0,	3,	898,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE1"                       ,	3,	3,	898,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	898,	"RAZ",	1,	1,	0,	0},
+	{"PARITY"                      ,	0,	1,	899,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	899,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	899,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	899,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	16,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	900,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	901,	"RAZ",	1,	1,	0,	0},
+	{"PREEMPTER"                   ,	0,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"PREEMPTEE"                   ,	1,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	902,	"RAZ",	1,	1,	0,	0},
+	{"QID7"                        ,	0,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDX3"                        ,	1,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	903,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	904,	"RAZ",	1,	1,	0,	0},
+	{"WQE_WORD"                    ,	0,	4,	905,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_4_63"               ,	4,	60,	905,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	1,	906,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND"                        ,	1,	1,	906,	"RO",	0,	0,	0ull,	0ull},
+	{"FIDX"                        ,	2,	1,	906,	"RO",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	3,	1,	906,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT"                         ,	4,	4,	906,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR"                         ,	8,	3,	906,	"RO",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	11,	1,	906,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	906,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	16,	10,	906,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_63"              ,	26,	38,	906,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	32,	907,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	907,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	908,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	908,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE_IE"                      ,	2,	1,	908,	"R/W",	0,	1,	0ull,	0},
+	{"DBE_IE"                      ,	3,	1,	908,	"R/W",	0,	1,	0ull,	0},
+	{"SYN"                         ,	4,	5,	908,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_11"               ,	9,	3,	908,	"RAZ",	1,	1,	0,	0},
+	{"RPE"                         ,	12,	1,	908,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE_IE"                      ,	13,	1,	908,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	908,	"RAZ",	1,	1,	0,	0},
+	{"IOP"                         ,	16,	13,	908,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	908,	"RAZ",	1,	1,	0,	0},
+	{"IOP_IE"                      ,	32,	13,	908,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_63"              ,	45,	19,	908,	"RAZ",	1,	1,	0,	0},
+	{"NBR_THR"                     ,	0,	5,	909,	"R/W",	0,	0,	2ull,	2ull},
+	{"PFR_DIS"                     ,	5,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	909,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	910,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	910,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	911,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	911,	"RAZ",	1,	1,	0,	0},
+	{"IQ_INT"                      ,	0,	8,	912,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	912,	"RAZ",	1,	1,	0,	0},
+	{"INT_EN"                      ,	0,	8,	913,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	913,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	32,	914,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	914,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	11,	915,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	915,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	916,	"R/W",	0,	0,	0ull,	1023ull},
+	{"RESERVED_10_63"              ,	10,	54,	916,	"RAZ",	1,	1,	0,	0},
+	{"RST_MSK"                     ,	0,	8,	917,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	917,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	16,	918,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"QOS0_PRI"                    ,	16,	4,	918,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1_PRI"                    ,	20,	4,	918,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2_PRI"                    ,	24,	4,	918,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3_PRI"                    ,	28,	4,	918,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4_PRI"                    ,	32,	4,	918,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5_PRI"                    ,	36,	4,	918,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6_PRI"                    ,	40,	4,	918,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7_PRI"                    ,	44,	4,	918,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	918,	"RAZ",	1,	1,	0,	0},
+	{"RND"                         ,	0,	8,	919,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P1"                      ,	8,	8,	919,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P2"                      ,	16,	8,	919,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P3"                      ,	24,	8,	919,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	919,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	10,	920,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_11"              ,	10,	2,	920,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	12,	10,	920,	"R/W",	0,	1,	1023ull,	0},
+	{"RESERVED_22_23"              ,	22,	2,	920,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	24,	11,	920,	"RO",	0,	1,	1003ull,	0},
+	{"RESERVED_35_35"              ,	35,	1,	920,	"RAZ",	1,	1,	0,	0},
+	{"BUF_CNT"                     ,	36,	11,	920,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	920,	"RAZ",	1,	1,	0,	0},
+	{"DES_CNT"                     ,	48,	11,	920,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_59_63"              ,	59,	5,	920,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	32,	921,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	921,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	922,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	922,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	923,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	923,	"RAZ",	1,	1,	0,	0},
+	{"WQ_INT"                      ,	0,	16,	924,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_DIS"                      ,	16,	16,	924,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	924,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	11,	925,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	925,	"RAZ",	1,	1,	0,	0},
+	{"DS_CNT"                      ,	12,	11,	925,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	925,	"RAZ",	1,	1,	0,	0},
+	{"TC_CNT"                      ,	24,	4,	925,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	925,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	926,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	926,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	926,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	926,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	926,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	10,	927,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_11"              ,	10,	2,	927,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	12,	10,	927,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_23"              ,	22,	2,	927,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	24,	4,	927,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	28,	1,	927,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	927,	"RAZ",	1,	1,	0,	0},
+	{"WS_PC"                       ,	0,	32,	928,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	928,	"RAZ",	1,	1,	0,	0},
+	{"IWORD"                       ,	0,	64,	929,	"RO",	1,	1,	0,	0},
+	{"P_DAT"                       ,	0,	64,	930,	"RO",	1,	1,	0,	0},
+	{"Q_DAT"                       ,	0,	64,	931,	"RO",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	2,	932,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	2,	2,	932,	"RO",	1,	0,	0,	0ull},
+	{"NCB_OUB"                     ,	4,	1,	932,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	5,	1,	932,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	932,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	933,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	33,	13,	933,	"R/W",	0,	1,	0ull,	0},
+	{"POOL"                        ,	46,	3,	933,	"R/W",	0,	1,	0ull,	0},
+	{"DWB"                         ,	49,	9,	933,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	933,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	934,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STORE_LE"                    ,	1,	1,	934,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_READ"                    ,	2,	4,	934,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_6_63"               ,	6,	58,	934,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	0,	5,	935,	"RO",	1,	1,	0,	0},
+	{"COMMIT"                      ,	5,	1,	935,	"RO",	1,	1,	0,	0},
+	{"OWORDPV"                     ,	6,	1,	935,	"RO",	1,	1,	0,	0},
+	{"OWORDQV"                     ,	7,	1,	935,	"RO",	1,	1,	0,	0},
+	{"IWIDX"                       ,	8,	6,	935,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	935,	"RO",	1,	1,	0,	0},
+	{"IRIDX"                       ,	16,	6,	935,	"RO",	1,	1,	0,	0},
+	{"RESERVED_22_31"              ,	22,	10,	935,	"RO",	1,	1,	0,	0},
+	{"LOOP"                        ,	32,	25,	935,	"RO",	1,	1,	0,	0},
+	{"RESERVED_57_63"              ,	57,	7,	935,	"RO",	1,	1,	0,	0},
+	{"CWORD"                       ,	0,	64,	936,	"RO",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	937,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	937,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	937,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	938,	"RO",	1,	1,	0,	0},
+	{"SOD"                         ,	8,	1,	938,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	9,	1,	938,	"RO",	1,	1,	0,	0},
+	{"WC"                          ,	10,	1,	938,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	11,	1,	938,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	12,	1,	938,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	938,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	15,	939,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	939,	"RAZ",	1,	1,	0,	0},
+	{"OWORDP"                      ,	0,	64,	940,	"RO",	1,	1,	0,	0},
+	{"OWORDQ"                      ,	0,	64,	941,	"RO",	1,	1,	0,	0},
+	{"RWORD"                       ,	0,	64,	942,	"RO",	1,	1,	0,	0},
+	{"N0CREDS"                     ,	0,	4,	943,	"RO",	0,	0,	8ull,	0ull},
+	{"N1CREDS"                     ,	4,	4,	943,	"RO",	0,	0,	8ull,	0ull},
+	{"POWCREDS"                    ,	8,	2,	943,	"RO",	0,	0,	2ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	943,	"RAZ",	1,	1,	0,	0},
+	{"FPACREDS"                    ,	12,	2,	943,	"RO",	0,	0,	1ull,	0ull},
+	{"WCCREDS"                     ,	14,	2,	943,	"RO",	0,	0,	0ull,	0ull},
+	{"NIWIDX0"                     ,	16,	4,	943,	"RO",	1,	1,	0,	0},
+	{"NIRIDX0"                     ,	20,	4,	943,	"RO",	1,	1,	0,	0},
+	{"NIWIDX1"                     ,	24,	4,	943,	"RO",	1,	1,	0,	0},
+	{"NIRIDX1"                     ,	28,	4,	943,	"RO",	1,	1,	0,	0},
+	{"NIRVAL6"                     ,	32,	5,	943,	"RO",	1,	1,	0,	0},
+	{"NIRARB6"                     ,	37,	1,	943,	"RO",	1,	1,	0,	0},
+	{"NIRQUE6"                     ,	38,	2,	943,	"RO",	1,	1,	0,	0},
+	{"NIROPC6"                     ,	40,	3,	943,	"RO",	1,	1,	0,	0},
+	{"NIRVAL7"                     ,	43,	5,	943,	"RO",	1,	1,	0,	0},
+	{"NIRQUE7"                     ,	48,	2,	943,	"RO",	1,	1,	0,	0},
+	{"NIROPC7"                     ,	50,	3,	943,	"RO",	1,	1,	0,	0},
+	{"RESERVED_53_63"              ,	53,	11,	943,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	944,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	944,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	56,	8,	944,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	15,	945,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	945,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	946,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	946,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	946,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	947,	"RO",	1,	1,	0,	0},
+	{"MUL"                         ,	8,	8,	947,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	16,	1,	947,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	17,	1,	947,	"RO",	1,	1,	0,	0},
+	{"INI"                         ,	18,	1,	947,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	19,	1,	947,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_63"              ,	20,	44,	947,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	948,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	948,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	949,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	949,	"RAZ",	1,	1,	0,	0},
+	{"COEFFS"                      ,	0,	8,	950,	"R/W",	0,	0,	29ull,	29ull},
+	{"RESERVED_8_63"               ,	8,	56,	950,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	0,	16,	951,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	16,	16,	951,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	951,	"RAZ",	1,	1,	0,	0},
+	{"MEM"                         ,	0,	1,	952,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	952,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	952,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	953,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	953,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	953,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	953,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXP_ENT"                     ,	4,	1,	953,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENT_SEL"                     ,	5,	4,	953,	"R/W",	0,	0,	0ull,	0ull},
+	{"EER_VAL"                     ,	9,	1,	953,	"RO",	0,	0,	0ull,	0ull},
+	{"EER_LCK"                     ,	10,	1,	953,	"RO",	0,	0,	0ull,	0ull},
+	{"DIS_MAK"                     ,	11,	1,	953,	"R/W1",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	953,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	954,	"RO",	1,	1,	0,	0},
+	{"KEY"                         ,	0,	64,	955,	"WO",	0,	0,	0ull,	0ull},
+	{"DAT"                         ,	0,	64,	956,	"RO",	1,	1,	0,	0},
+	{"NCB_CMD"                     ,	0,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"MSI"                         ,	1,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI0_0"                      ,	2,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI0_1"                      ,	3,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI1_0"                      ,	4,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI1_1"                      ,	5,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_8"                ,	6,	3,	957,	"RAZ",	1,	1,	0,	0},
+	{"P2N1_P1"                     ,	9,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_P0"                     ,	10,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_N"                      ,	11,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C1"                     ,	12,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C0"                     ,	13,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P1"                     ,	14,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P0"                     ,	15,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_N"                      ,	16,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C1"                     ,	17,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C0"                     ,	18,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_24"              ,	19,	6,	957,	"RAZ",	1,	1,	0,	0},
+	{"CPL_P1"                      ,	25,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"CPL_P0"                      ,	26,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_28"              ,	27,	2,	957,	"RAZ",	1,	1,	0,	0},
+	{"N2P0_O"                      ,	29,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_C"                      ,	30,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	957,	"RAZ",	1,	1,	0,	0},
+	{"WAIT_COM"                    ,	0,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_4"                ,	1,	4,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTLP_RO"                     ,	5,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTLP_RO"                     ,	7,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTA_MAP"                    ,	8,	2,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTB_MAP"                    ,	10,	2,	958,	"R/W",	0,	0,	1ull,	1ull},
+	{"INTC_MAP"                    ,	12,	2,	958,	"R/W",	0,	0,	2ull,	2ull},
+	{"INTD_MAP"                    ,	14,	2,	958,	"R/W",	0,	0,	3ull,	3ull},
+	{"WAITL_COM"                   ,	16,	1,	958,	"R/W",	0,	1,	0ull,	0},
+	{"DIS_PORT"                    ,	17,	1,	958,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTA"                        ,	18,	1,	958,	"RO",	0,	0,	1ull,	1ull},
+	{"INTB"                        ,	19,	1,	958,	"RO",	0,	0,	1ull,	1ull},
+	{"INTC"                        ,	20,	1,	958,	"RO",	0,	0,	1ull,	1ull},
+	{"INTD"                        ,	21,	1,	958,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	958,	"RAZ",	1,	1,	0,	0},
+	{"CHIP_REV"                    ,	0,	8,	959,	"RO",	1,	1,	0,	0},
+	{"P0_NTAGS"                    ,	8,	6,	959,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_14_63"              ,	14,	50,	959,	"R/W",	0,	0,	32ull,	32ull},
+	{"P0_FCNT"                     ,	0,	6,	960,	"RO",	0,	1,	0ull,	0},
+	{"P0_UCNT"                     ,	6,	16,	960,	"RO",	0,	1,	0ull,	0},
+	{"P1_FCNT"                     ,	22,	6,	960,	"RAZ",	0,	1,	0ull,	0},
+	{"P1_UCNT"                     ,	28,	16,	960,	"RAZ",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	960,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	961,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	961,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	961,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	32,	962,	"R/W",	0,	1,	0ull,	0},
+	{"ADBG_SEL"                    ,	32,	1,	962,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	962,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	963,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	963,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	964,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	32,	964,	"R/W",	0,	1,	0ull,	0},
+	{"TIM"                         ,	0,	32,	965,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	965,	"RAZ",	1,	1,	0,	0},
+	{"RML_TO"                      ,	0,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	4,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	5,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UP_WI"                    ,	9,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_B0"                    ,	10,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_WI"                    ,	11,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_B0"                    ,	12,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_WI"                    ,	13,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_B0"                    ,	14,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_WI"                    ,	15,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT0"                    ,	16,	1,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO_INT1"                    ,	17,	1,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"M2_UP_B0"                    ,	20,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"M2_UP_WI"                    ,	21,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"M2_UN_B0"                    ,	22,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"M2_UN_WI"                    ,	23,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"M3_UP_B0"                    ,	24,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"M3_UP_WI"                    ,	25,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"M3_UN_B0"                    ,	26,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"M3_UN_WI"                    ,	27,	1,	966,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_28_31"              ,	28,	4,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAFI"                       ,	32,	2,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	48,	1,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT2_ERR"                   ,	58,	1,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT3_ERR"                   ,	59,	1,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	966,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML_TO"                      ,	0,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	4,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	5,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UP_WI"                    ,	9,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_B0"                    ,	10,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_WI"                    ,	11,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_B0"                    ,	12,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_WI"                    ,	13,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_B0"                    ,	14,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_WI"                    ,	15,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT0"                    ,	16,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT1"                    ,	17,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC0_INT"                    ,	18,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC1_INT"                    ,	19,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"M2_UP_B0"                    ,	20,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"M2_UP_WI"                    ,	21,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"M2_UN_B0"                    ,	22,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"M2_UN_WI"                    ,	23,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"M3_UP_B0"                    ,	24,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"M3_UP_WI"                    ,	25,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"M3_UN_B0"                    ,	26,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"M3_UN_WI"                    ,	27,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_28_31"              ,	28,	4,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAFI"                       ,	32,	2,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	48,	1,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT2_ERR"                   ,	58,	1,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT3_ERR"                   ,	59,	1,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML_TO"                      ,	0,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAR0_TO"                     ,	2,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB2BIG"                     ,	3,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT"                        ,	4,	1,	968,	"RO",	0,	0,	0ull,	0ull},
+	{"PTIME"                       ,	5,	1,	968,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UP_WI"                    ,	9,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UN_B0"                    ,	10,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UN_WI"                    ,	11,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UP_B0"                    ,	12,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UP_WI"                    ,	13,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UN_B0"                    ,	14,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UN_WI"                    ,	15,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO_INT0"                    ,	16,	1,	968,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO_INT1"                    ,	17,	1,	968,	"RO",	0,	0,	0ull,	0ull},
+	{"MAC0_INT"                    ,	18,	1,	968,	"RO",	0,	0,	0ull,	0ull},
+	{"MAC1_INT"                    ,	19,	1,	968,	"RO",	0,	0,	0ull,	0ull},
+	{"M2_UP_B0"                    ,	20,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M2_UP_WI"                    ,	21,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M2_UN_B0"                    ,	22,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M2_UN_WI"                    ,	23,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M3_UP_B0"                    ,	24,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M3_UP_WI"                    ,	25,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M3_UN_B0"                    ,	26,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M3_UN_WI"                    ,	27,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	968,	"RAZ",	1,	1,	0,	0},
+	{"DMAFI"                       ,	32,	2,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	968,	"RO",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	968,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	968,	"RAZ",	1,	1,	0,	0},
+	{"PIDBOF"                      ,	48,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT2_ERR"                   ,	58,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT3_ERR"                   ,	59,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	968,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	968,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	969,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	970,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	971,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	972,	"RO",	0,	1,	0ull,	0},
+	{"P0_PCNT"                     ,	0,	8,	973,	"R/W",	0,	0,	128ull,	128ull},
+	{"P0_NCNT"                     ,	8,	8,	973,	"R/W",	0,	0,	16ull,	16ull},
+	{"P0_CCNT"                     ,	16,	8,	973,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_PCNT"                     ,	24,	8,	973,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_NCNT"                     ,	32,	8,	973,	"R/W",	0,	0,	16ull,	16ull},
+	{"P1_CCNT"                     ,	40,	8,	973,	"R/W",	0,	0,	128ull,	128ull},
+	{"P0_P_D"                      ,	48,	1,	973,	"R/W",	0,	0,	1ull,	1ull},
+	{"P0_N_D"                      ,	49,	1,	973,	"R/W",	0,	0,	1ull,	1ull},
+	{"P0_C_D"                      ,	50,	1,	973,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_P_D"                      ,	51,	1,	973,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_N_D"                      ,	52,	1,	973,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_C_D"                      ,	53,	1,	973,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_54_63"              ,	54,	10,	973,	"RAZ",	1,	1,	0,	0},
+	{"P2_PCNT"                     ,	0,	8,	974,	"R/W",	0,	0,	128ull,	128ull},
+	{"P2_NCNT"                     ,	8,	8,	974,	"R/W",	0,	0,	16ull,	16ull},
+	{"P2_CCNT"                     ,	16,	8,	974,	"R/W",	0,	0,	128ull,	128ull},
+	{"P3_PCNT"                     ,	24,	8,	974,	"R/W",	0,	0,	128ull,	128ull},
+	{"P3_NCNT"                     ,	32,	8,	974,	"R/W",	0,	0,	16ull,	16ull},
+	{"P3_CCNT"                     ,	40,	8,	974,	"R/W",	0,	0,	128ull,	128ull},
+	{"P2_P_D"                      ,	48,	1,	974,	"R/W",	0,	0,	1ull,	1ull},
+	{"P2_N_D"                      ,	49,	1,	974,	"R/W",	0,	0,	1ull,	1ull},
+	{"P2_C_D"                      ,	50,	1,	974,	"R/W",	0,	0,	1ull,	1ull},
+	{"P3_P_D"                      ,	51,	1,	974,	"R/W",	0,	0,	1ull,	1ull},
+	{"P3_N_D"                      ,	52,	1,	974,	"R/W",	0,	0,	1ull,	1ull},
+	{"P3_C_D"                      ,	53,	1,	974,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_54_63"              ,	54,	10,	974,	"RAZ",	1,	1,	0,	0},
+	{"NUM"                         ,	0,	8,	975,	"RO",	1,	1,	0,	0},
+	{"A_MODE"                      ,	8,	1,	975,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_63"               ,	9,	55,	975,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	10,	976,	"R/W",	0,	0,	0ull,	50ull},
+	{"MAX_WORD"                    ,	10,	4,	976,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	976,	"RAZ",	1,	1,	0,	0},
+	{"BA"                          ,	0,	30,	977,	"R/W",	0,	1,	0ull,	0},
+	{"RTYPE"                       ,	30,	2,	977,	"R/W",	0,	1,	0ull,	0},
+	{"WTYPE"                       ,	32,	2,	977,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	34,	2,	977,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	36,	2,	977,	"R/W",	0,	1,	0ull,	0},
+	{"NMERGE"                      ,	38,	1,	977,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORT"                        ,	39,	3,	977,	"R/W",	0,	1,	0ull,	0},
+	{"ZERO"                        ,	42,	1,	977,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	977,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	64,	978,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	979,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	980,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	981,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"INTR"                        ,	0,	64,	982,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	983,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	984,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	985,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	986,	"R/W",	0,	1,	0ull,	0},
+	{"RD_INT"                      ,	8,	8,	986,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	986,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	64,	987,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	988,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	989,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	990,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	991,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	992,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	993,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	994,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	995,	"R/W",	0,	1,	0ull,	0},
+	{"CIU_INT"                     ,	8,	8,	995,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	995,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	8,	996,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	996,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	997,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	8,	8,	997,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	997,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	998,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	16,	8,	998,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	998,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	999,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	24,	8,	999,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	999,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1000,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	32,	22,	1000,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	1000,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"WMARK"                       ,	32,	32,	1001,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	1002,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	61,	1002,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	1003,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	1003,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"FCNT"                        ,	32,	5,	1004,	"RO",	0,	1,	0ull,	0},
+	{"WRP"                         ,	37,	9,	1004,	"RO",	0,	1,	0ull,	0},
+	{"RRP"                         ,	46,	9,	1004,	"RO",	0,	1,	0ull,	0},
+	{"MAX"                         ,	55,	9,	1004,	"RO",	0,	1,	16ull,	0},
+	{"NTAG"                        ,	0,	1,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"NTT"                         ,	1,	1,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"NGRP"                        ,	2,	1,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"NQOS"                        ,	3,	1,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_13"              ,	13,	1,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_20"              ,	16,	5,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"RNTAG"                       ,	22,	1,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"RNTT"                        ,	23,	1,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"RNGRP"                       ,	24,	1,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"RNQOS"                       ,	25,	1,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_27"              ,	26,	2,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_35_35"              ,	35,	1,	1005,	"RAZ",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_42"              ,	38,	5,	1005,	"RAZ",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	1005,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	16,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"ISIZE"                       ,	16,	7,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	1006,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1007,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	4,	60,	1007,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	1008,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	1008,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	1009,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1009,	"RO",	0,	1,	0ull,	0},
+	{"PORT"                        ,	0,	32,	1010,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1010,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	1011,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1011,	"RAZ",	1,	1,	0,	0},
+	{"PKT_BP"                      ,	0,	4,	1012,	"R/W",	0,	0,	15ull,	15ull},
+	{"RING_EN"                     ,	4,	1,	1012,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	1012,	"RAZ",	1,	1,	0,	0},
+	{"ES"                          ,	0,	64,	1013,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	1014,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1014,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	1015,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1015,	"RAZ",	1,	1,	0,	0},
+	{"DPTR"                        ,	0,	32,	1016,	"R/W",	0,	0,	0ull,	4294967295ull},
+	{"RESERVED_32_63"              ,	32,	32,	1016,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	32,	1017,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1017,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1018,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1018,	"RO",	0,	1,	0ull,	0},
+	{"RD_CNT"                      ,	0,	32,	1019,	"RO",	0,	1,	0ull,	0},
+	{"WR_CNT"                      ,	32,	32,	1019,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	0,	64,	1020,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	0,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	1,	2,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	3,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"USE_CSR"                     ,	4,	1,	1021,	"R/W",	0,	0,	0ull,	1ull},
+	{"D_ROR"                       ,	5,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"D_ESR"                       ,	6,	2,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"D_NSR"                       ,	8,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"PBP_DHI"                     ,	9,	13,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_RR"                      ,	22,	1,	1021,	"R/W",	0,	0,	0ull,	1ull},
+	{"PIN_RST"                     ,	23,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_39"              ,	24,	16,	1021,	"RAZ",	1,	1,	0,	0},
+	{"PRC_IDLE"                    ,	40,	1,	1021,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_41_47"              ,	41,	7,	1021,	"RAZ",	1,	1,	0,	0},
+	{"GII_RDS"                     ,	48,	7,	1021,	"RO",	0,	1,	0ull,	0},
+	{"GII_ERST"                    ,	55,	1,	1021,	"RO",	0,	1,	0ull,	0},
+	{"PRD_RDS"                     ,	56,	7,	1021,	"RO",	0,	1,	0ull,	0},
+	{"PRD_ERST"                    ,	63,	1,	1021,	"RO",	0,	1,	0ull,	0},
+	{"ENB"                         ,	0,	32,	1022,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1022,	"RAZ",	1,	1,	0,	0},
+	{"RDSIZE"                      ,	0,	64,	1023,	"R/W",	0,	1,	0ull,	0},
+	{"IS_64B"                      ,	0,	32,	1024,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1024,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1025,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	22,	1025,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_54_63"              ,	54,	10,	1025,	"RAZ",	1,	1,	0,	0},
+	{"IPTR"                        ,	0,	32,	1026,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1026,	"RAZ",	1,	1,	0,	0},
+	{"BMODE"                       ,	0,	32,	1027,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1027,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	32,	1028,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1028,	"RAZ",	1,	1,	0,	0},
+	{"WMARK"                       ,	0,	32,	1029,	"R/W",	0,	0,	0ull,	14ull},
+	{"RESERVED_32_63"              ,	32,	32,	1029,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	0,	64,	1030,	"R/W",	0,	1,	0ull,	0},
+	{"OUT_RST"                     ,	0,	32,	1031,	"RO",	0,	1,	0ull,	0},
+	{"IN_RST"                      ,	32,	32,	1031,	"RO",	0,	1,	0ull,	0},
+	{"ES"                          ,	0,	64,	1032,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	1033,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1033,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	1034,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1034,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	1035,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1035,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	1036,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1036,	"RAZ",	1,	1,	0,	0},
+	{"MRRS"                        ,	0,	3,	1037,	"R/W",	0,	0,	2ull,	2ull},
+	{"BAR0_D"                      ,	3,	1,	1037,	"R/W",	1,	1,	0,	0},
+	{"WIND_D"                      ,	4,	1,	1037,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_5_63"               ,	5,	59,	1037,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	1038,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	1039,	"R/W",	0,	1,	0ull,	0},
+	{"CSR"                         ,	0,	39,	1040,	"RO",	0,	1,	1ull,	0},
+	{"ARB"                         ,	39,	1,	1040,	"RO",	0,	1,	0ull,	0},
+	{"CPL0"                        ,	40,	12,	1040,	"RO",	0,	1,	1ull,	0},
+	{"CPL1"                        ,	52,	12,	1040,	"RO",	0,	1,	1ull,	0},
+	{"NND"                         ,	0,	8,	1041,	"RO",	0,	1,	1ull,	0},
+	{"NNP0"                        ,	8,	8,	1041,	"RO",	0,	1,	1ull,	0},
+	{"CSM0"                        ,	16,	15,	1041,	"RO",	0,	1,	1ull,	0},
+	{"CSM1"                        ,	31,	15,	1041,	"RO",	0,	1,	1ull,	0},
+	{"RAC"                         ,	46,	1,	1041,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	1041,	"RAZ",	1,	1,	0,	0},
+	{"NNP1"                        ,	48,	8,	1041,	"RAZ",	0,	1,	0ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	1041,	"RAZ",	1,	1,	0,	0},
+	{"NSM0"                        ,	0,	13,	1042,	"RO",	0,	1,	1ull,	0},
+	{"NSM1"                        ,	13,	13,	1042,	"RO",	0,	1,	1ull,	0},
+	{"PSM0"                        ,	26,	15,	1042,	"RO",	0,	1,	1ull,	0},
+	{"PSM1"                        ,	41,	15,	1042,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	1042,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	0,	48,	1043,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	1043,	"R/W",	0,	0,	0ull,	0ull},
+	{"LD_CMD"                      ,	49,	2,	1043,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_51_63"              ,	51,	13,	1043,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	1044,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	1045,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	3,	45,	1045,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	1045,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	1045,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	1046,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	1047,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1047,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	1048,	"R/W",	0,	0,	0ull,	2097152ull},
+	{"RESERVED_32_63"              ,	32,	32,	1048,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	1049,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	1049,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	1049,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	1049,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	1049,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	24,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1049,	"RAZ",	1,	1,	0,	0},
+	{"REG_ADR"                     ,	0,	5,	1050,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1050,	"RAZ",	1,	1,	0,	0},
+	{"PHY_ADR"                     ,	8,	5,	1050,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	1050,	"RAZ",	1,	1,	0,	0},
+	{"PHY_OP"                      ,	16,	2,	1050,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	1050,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	1051,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	1051,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	1052,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	1052,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	1052,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	1052,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	1053,	"R/W",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	1053,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	1053,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	1053,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	1054,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_6_7"                ,	6,	2,	1054,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	8,	6,	1054,	"R/W",	0,	0,	19ull,	19ull},
+	{"RESERVED_14_63"              ,	14,	50,	1054,	"RAZ",	1,	1,	0,	0},
+	{"DENY_BAR0"                   ,	0,	1,	1055,	"R/W",	1,	1,	0,	0},
+	{"DENY_BAR1"                   ,	1,	1,	1055,	"R/W",	1,	1,	0,	0},
+	{"DENY_BAR2"                   ,	2,	1,	1055,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_3_3"                ,	3,	1,	1055,	"RAZ",	1,	1,	0,	0},
+	{"DENY_ADR0"                   ,	4,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"DENY_ADR1"                   ,	5,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"DENY_ADR2"                   ,	6,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	1055,	"RAZ",	1,	1,	0,	0},
+	{"ASSY_VEN"                    ,	0,	16,	1056,	"R/W",	0,	0,	140ull,	0ull},
+	{"ASSY_ID"                     ,	16,	16,	1056,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1056,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	1057,	"RAZ",	1,	1,	0,	0},
+	{"ASSY_REV"                    ,	16,	16,	1057,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1057,	"RAZ",	1,	1,	0,	0},
+	{"RP0_PID"                     ,	0,	2,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_PID"                     ,	2,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP0_SID"                     ,	3,	2,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_SID"                     ,	5,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1058,	"RAZ",	1,	1,	0,	0},
+	{"OMSG"                        ,	0,	7,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"IMSG"                        ,	7,	5,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"RXBUF"                       ,	12,	2,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"TXBUF"                       ,	14,	2,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"OSPF"                        ,	16,	1,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"ISPF"                        ,	17,	1,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"OARB"                        ,	18,	2,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"RXBUF2"                      ,	20,	2,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"OARB2"                       ,	22,	2,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"OPTRS"                       ,	24,	4,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"OBULK"                       ,	28,	4,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"RTN"                         ,	32,	2,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"OFREE"                       ,	34,	1,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"ITAG"                        ,	35,	1,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"OTAG"                        ,	36,	2,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"BELL"                        ,	38,	2,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"CRAM"                        ,	40,	2,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"MRAM"                        ,	42,	2,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"LRAM"                        ,	44,	1,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_63"              ,	45,	19,	1059,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	1060,	"R/W",	0,	1,	0ull,	0},
+	{"PRIO"                        ,	4,	4,	1060,	"R/W",	0,	1,	0ull,	0},
+	{"LTTR"                        ,	8,	4,	1060,	"R/W",	0,	1,	0ull,	0},
+	{"PRT_SEL"                     ,	12,	3,	1060,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	1060,	"RAZ",	1,	1,	0,	0},
+	{"RP0_PID"                     ,	16,	2,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_PID"                     ,	18,	1,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP0_SID"                     ,	19,	2,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_SID"                     ,	21,	1,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1060,	"RAZ",	1,	1,	0,	0},
+	{"RSP_THR"                     ,	24,	6,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	1060,	"RAZ",	1,	1,	0,	0},
+	{"TO_MODE"                     ,	31,	1,	1060,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1060,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	0,	32,	1061,	"R/W",	0,	1,	0ull,	0},
+	{"TT"                          ,	32,	2,	1061,	"R/W",	0,	1,	0ull,	0},
+	{"RS"                          ,	34,	1,	1061,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_35_41"              ,	35,	7,	1061,	"RAZ",	1,	1,	0,	0},
+	{"NTAG"                        ,	42,	1,	1061,	"R/W",	0,	1,	0ull,	0},
+	{"NTT"                         ,	43,	1,	1061,	"R/W",	0,	1,	0ull,	0},
+	{"NGRP"                        ,	44,	1,	1061,	"R/W",	0,	1,	0ull,	0},
+	{"NQOS"                        ,	45,	1,	1061,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	1061,	"RAZ",	1,	1,	0,	0},
+	{"SL"                          ,	48,	7,	1061,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_55_55"              ,	55,	1,	1061,	"RAZ",	1,	1,	0,	0},
+	{"PM"                          ,	56,	2,	1061,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_58_62"              ,	58,	5,	1061,	"RAZ",	1,	1,	0,	0},
+	{"R"                           ,	63,	1,	1061,	"R/W",	0,	1,	0ull,	0},
+	{"GRP0"                        ,	0,	4,	1062,	"R/W",	0,	1,	0ull,	0},
+	{"QOS0"                        ,	4,	3,	1062,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	1062,	"RAZ",	1,	1,	0,	0},
+	{"GRP1"                        ,	8,	4,	1062,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1"                        ,	12,	3,	1062,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	1062,	"RAZ",	1,	1,	0,	0},
+	{"GRP2"                        ,	16,	4,	1062,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2"                        ,	20,	3,	1062,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	1062,	"RAZ",	1,	1,	0,	0},
+	{"GRP3"                        ,	24,	4,	1062,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3"                        ,	28,	3,	1062,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_31_31"              ,	31,	1,	1062,	"RAZ",	1,	1,	0,	0},
+	{"GRP4"                        ,	32,	4,	1062,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4"                        ,	36,	3,	1062,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_39_39"              ,	39,	1,	1062,	"RAZ",	1,	1,	0,	0},
+	{"GRP5"                        ,	40,	4,	1062,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5"                        ,	44,	3,	1062,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	1062,	"RAZ",	1,	1,	0,	0},
+	{"GRP6"                        ,	48,	4,	1062,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6"                        ,	52,	3,	1062,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_55_55"              ,	55,	1,	1062,	"RAZ",	1,	1,	0,	0},
+	{"GRP7"                        ,	56,	4,	1062,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7"                        ,	60,	3,	1062,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_63_63"              ,	63,	1,	1062,	"RAZ",	1,	1,	0,	0},
+	{"SID0"                        ,	0,	16,	1063,	"RO",	0,	1,	0ull,	0},
+	{"LTTR0"                       ,	16,	2,	1063,	"RO",	0,	1,	0ull,	0},
+	{"MBOX0"                       ,	18,	2,	1063,	"RO",	0,	1,	0ull,	0},
+	{"SEG0"                        ,	20,	4,	1063,	"RO",	0,	1,	0ull,	0},
+	{"DIS0"                        ,	24,	1,	1063,	"RO",	0,	1,	0ull,	0},
+	{"TT0"                         ,	25,	1,	1063,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_26"              ,	26,	1,	1063,	"RAZ",	1,	1,	0,	0},
+	{"PRT0"                        ,	27,	1,	1063,	"RO",	0,	1,	0ull,	0},
+	{"TOC0"                        ,	28,	1,	1063,	"RO",	0,	1,	0ull,	0},
+	{"TOE0"                        ,	29,	1,	1063,	"RO",	0,	1,	0ull,	0},
+	{"ERR0"                        ,	30,	1,	1063,	"RO",	0,	1,	0ull,	0},
+	{"VAL0"                        ,	31,	1,	1063,	"RO",	0,	1,	0ull,	0},
+	{"SID1"                        ,	32,	16,	1063,	"RO",	0,	1,	0ull,	0},
+	{"LTTR1"                       ,	48,	2,	1063,	"RO",	0,	1,	0ull,	0},
+	{"MBOX1"                       ,	50,	2,	1063,	"RO",	0,	1,	0ull,	0},
+	{"SEG1"                        ,	52,	4,	1063,	"RO",	0,	1,	0ull,	0},
+	{"DIS1"                        ,	56,	1,	1063,	"RO",	0,	1,	0ull,	0},
+	{"TT1"                         ,	57,	1,	1063,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_58"              ,	58,	1,	1063,	"RAZ",	1,	1,	0,	0},
+	{"PRT1"                        ,	59,	1,	1063,	"RO",	0,	1,	0ull,	0},
+	{"TOC1"                        ,	60,	1,	1063,	"RO",	0,	1,	0ull,	0},
+	{"TOE1"                        ,	61,	1,	1063,	"RO",	0,	1,	0ull,	0},
+	{"ERR1"                        ,	62,	1,	1063,	"RO",	0,	1,	0ull,	0},
+	{"VAL1"                        ,	63,	1,	1063,	"RO",	0,	1,	0ull,	0},
+	{"MAX_P0"                      ,	0,	6,	1064,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	1064,	"RAZ",	1,	1,	0,	0},
+	{"MAX_P1"                      ,	8,	6,	1064,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	1064,	"RAZ",	1,	1,	0,	0},
+	{"BUF_THR"                     ,	16,	4,	1064,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_30"              ,	20,	11,	1064,	"RAZ",	1,	1,	0,	0},
+	{"SP_VPORT"                    ,	31,	1,	1064,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAX_S0"                      ,	32,	6,	1064,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_38_39"              ,	38,	2,	1064,	"RAZ",	1,	1,	0,	0},
+	{"MAX_S1"                      ,	40,	6,	1064,	"R/W",	0,	0,	48ull,	48ull},
+	{"RESERVED_46_47"              ,	46,	2,	1064,	"RAZ",	1,	1,	0,	0},
+	{"MAX_TOT"                     ,	48,	6,	1064,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_54_63"              ,	54,	10,	1064,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	1065,	"RAZ",	1,	1,	0,	0},
+	{"MAX_S2"                      ,	32,	6,	1065,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_38_39"              ,	38,	2,	1065,	"RAZ",	1,	1,	0,	0},
+	{"MAX_S3"                      ,	40,	6,	1065,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_46_63"              ,	46,	18,	1065,	"RAZ",	1,	1,	0,	0},
+	{"PKO_RST"                     ,	0,	1,	1066,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	1066,	"RAZ",	1,	1,	0,	0},
+	{"PKO_RST"                     ,	0,	1,	1067,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_30"               ,	1,	30,	1067,	"RAZ",	1,	1,	0,	0},
+	{"INT_SUM"                     ,	31,	1,	1067,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1067,	"RAZ",	1,	1,	0,	0},
+	{"TXBELL"                      ,	0,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"BELL_ERR"                    ,	1,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBELL"                      ,	2,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAINT_OP"                    ,	3,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR_ERR"                     ,	4,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"DENY_WR"                     ,	5,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"SLI_ERR"                     ,	6,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"WR_DONE"                     ,	7,	1,	1068,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCE_TX"                      ,	8,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"MCE_RX"                      ,	9,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"SOFT_TX"                     ,	10,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"SOFT_RX"                     ,	11,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"LOG_ERB"                     ,	12,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"PHY_ERB"                     ,	13,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"LINK_DWN"                    ,	14,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"LINK_UP"                     ,	15,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"OMSG0"                       ,	16,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"OMSG1"                       ,	17,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"OMSG_ERR"                    ,	18,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO_ERR"                     ,	19,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"RTRY_ERR"                    ,	20,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"F_ERROR"                     ,	21,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC_BUF"                     ,	22,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"DEGRADE"                     ,	23,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAIL"                        ,	24,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"TTL_TOUT"                    ,	25,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZERO_PKT"                    ,	26,	1,	1068,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_63"              ,	27,	37,	1068,	"RAZ",	1,	1,	0,	0},
+	{"BE1"                         ,	0,	8,	1069,	"RO",	0,	1,	0ull,	0},
+	{"BE0"                         ,	8,	8,	1069,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_28"              ,	16,	13,	1069,	"RO",	1,	1,	0,	0},
+	{"STATUS"                      ,	29,	3,	1069,	"RO",	0,	1,	0ull,	0},
+	{"LENGTH"                      ,	32,	10,	1069,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	1069,	"RO",	1,	1,	0,	0},
+	{"TAG"                         ,	48,	8,	1069,	"RO",	0,	1,	0ull,	0},
+	{"TYPE"                        ,	56,	4,	1069,	"RO",	0,	1,	0ull,	0},
+	{"CMD"                         ,	60,	4,	1069,	"RO",	0,	1,	0ull,	0},
+	{"INFO1"                       ,	0,	64,	1070,	"RO",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	1,	1071,	"RO",	0,	1,	0ull,	0},
+	{"LNS"                         ,	1,	1,	1071,	"RO",	0,	1,	0ull,	0},
+	{"RSRVD"                       ,	2,	30,	1071,	"RO",	0,	1,	0ull,	0},
+	{"LETTER"                      ,	32,	2,	1071,	"RO",	0,	1,	0ull,	0},
+	{"MBOX"                        ,	34,	2,	1071,	"RO",	0,	1,	0ull,	0},
+	{"XMBOX"                       ,	36,	4,	1071,	"RO",	0,	1,	0ull,	0},
+	{"DID"                         ,	40,	16,	1071,	"RO",	0,	1,	0ull,	0},
+	{"SSIZE"                       ,	56,	4,	1071,	"RO",	0,	1,	0ull,	0},
+	{"SIS"                         ,	60,	1,	1071,	"RO",	0,	1,	0ull,	0},
+	{"TT"                          ,	61,	1,	1071,	"RO",	0,	1,	0ull,	0},
+	{"PRIO"                        ,	62,	2,	1071,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1072,	"RAZ",	1,	1,	0,	0},
+	{"OTHER"                       ,	8,	48,	1072,	"RO",	0,	1,	0ull,	0},
+	{"TYPE"                        ,	56,	4,	1072,	"RO",	0,	1,	0ull,	0},
+	{"TT"                          ,	60,	2,	1072,	"RO",	0,	1,	0ull,	0},
+	{"PRIO"                        ,	62,	2,	1072,	"RO",	0,	1,	0ull,	0},
+	{"TXBELL"                      ,	0,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BELL_ERR"                    ,	1,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBELL"                      ,	2,	1,	1073,	"RO",	0,	0,	0ull,	0ull},
+	{"MAINT_OP"                    ,	3,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAR_ERR"                     ,	4,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DENY_WR"                     ,	5,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SLI_ERR"                     ,	6,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WR_DONE"                     ,	7,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCE_TX"                      ,	8,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCE_RX"                      ,	9,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SOFT_TX"                     ,	10,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SOFT_RX"                     ,	11,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LOG_ERB"                     ,	12,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_ERB"                     ,	13,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LINK_DWN"                    ,	14,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LINK_UP"                     ,	15,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OMSG0"                       ,	16,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OMSG1"                       ,	17,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OMSG_ERR"                    ,	18,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO_ERR"                     ,	19,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTRY_ERR"                    ,	20,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"F_ERROR"                     ,	21,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAC_BUF"                     ,	22,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEGRAD"                      ,	23,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FAIL"                        ,	24,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TTL_TOUT"                    ,	25,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ZERO_PKT"                    ,	26,	1,	1073,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_30"              ,	27,	4,	1073,	"RAZ",	1,	1,	0,	0},
+	{"INT2_SUM"                    ,	31,	1,	1073,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1073,	"RAZ",	1,	1,	0,	0},
+	{"RX_POL"                      ,	0,	4,	1074,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_POL"                      ,	4,	4,	1074,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_WIDTH"                    ,	8,	2,	1074,	"R/W",	0,	0,	3ull,	3ull},
+	{"TX_FLOW"                     ,	10,	1,	1074,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_11_11"              ,	11,	1,	1074,	"RAZ",	1,	1,	0,	0},
+	{"A50"                         ,	12,	1,	1074,	"R/W",	0,	0,	1ull,	1ull},
+	{"A66"                         ,	13,	1,	1074,	"R/W",	0,	0,	1ull,	1ull},
+	{"NO_VMIN"                     ,	14,	1,	1074,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_31"              ,	15,	17,	1074,	"RAZ",	1,	1,	0,	0},
+	{"OPS"                         ,	32,	32,	1074,	"R/W",	0,	0,	64756ull,	64756ull},
+	{"RX_STAT"                     ,	0,	8,	1075,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_INUSE"                    ,	8,	4,	1075,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_15"              ,	12,	4,	1075,	"RAZ",	1,	1,	0,	0},
+	{"RX_ENB"                      ,	16,	8,	1075,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_24_31"              ,	24,	8,	1075,	"RAZ",	1,	1,	0,	0},
+	{"TX_STAT"                     ,	32,	8,	1075,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_INUSE"                    ,	40,	4,	1075,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_44_47"              ,	44,	4,	1075,	"RAZ",	1,	1,	0,	0},
+	{"TX_ENB"                      ,	48,	8,	1075,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_56_63"              ,	56,	8,	1075,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	24,	1076,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	24,	1,	1076,	"R/W",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	25,	1,	1076,	"RO",	0,	1,	0ull,	0},
+	{"FAIL"                        ,	26,	1,	1076,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_27_31"              ,	27,	5,	1076,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	32,	32,	1076,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DATA"                     ,	0,	32,	1077,	"RO",	0,	1,	0ull,	0},
+	{"VALID"                       ,	32,	1,	1077,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	1077,	"RAZ",	1,	1,	0,	0},
+	{"MCE"                         ,	0,	1,	1078,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1078,	"RAZ",	1,	1,	0,	0},
+	{"RP0_PID"                     ,	0,	2,	1079,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_PID"                     ,	2,	1,	1079,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP0_SID"                     ,	3,	2,	1079,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_SID"                     ,	5,	1,	1079,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	1079,	"RAZ",	1,	1,	0,	0},
+	{"W_RO"                        ,	8,	1,	1079,	"R/W",	0,	0,	0ull,	0ull},
+	{"RR_RO"                       ,	9,	1,	1079,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1079,	"RAZ",	1,	1,	0,	0},
+	{"LTTR_MP"                     ,	0,	4,	1080,	"R/W",	0,	1,	15ull,	0},
+	{"LTTR_SP"                     ,	4,	4,	1080,	"R/W",	0,	1,	15ull,	0},
+	{"IDM_DID"                     ,	8,	1,	1080,	"R/W",	0,	1,	1ull,	0},
+	{"IDM_SIS"                     ,	9,	1,	1080,	"R/W",	0,	1,	1ull,	0},
+	{"IDM_TT"                      ,	10,	1,	1080,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_11_14"              ,	11,	4,	1080,	"RAZ",	1,	1,	0,	0},
+	{"RTRY_EN"                     ,	15,	1,	1080,	"R/W",	0,	1,	0ull,	0},
+	{"RTRY_THR"                    ,	16,	16,	1080,	"R/W",	0,	1,	0ull,	0},
+	{"SILO_MAX"                    ,	32,	5,	1080,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_37_62"              ,	37,	26,	1080,	"RAZ",	1,	1,	0,	0},
+	{"TESTMODE"                    ,	63,	1,	1080,	"R/W",	0,	0,	0ull,	0ull},
+	{"GOOD"                        ,	0,	16,	1081,	"R/W",	0,	1,	0ull,	0},
+	{"BAD"                         ,	16,	16,	1081,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1081,	"RAZ",	1,	1,	0,	0},
+	{"ALL_PSD"                     ,	0,	1,	1082,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_NMP"                     ,	1,	1,	1082,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_FMP"                     ,	2,	1,	1082,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_SP"                      ,	3,	1,	1082,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_PSD"                    ,	4,	1,	1082,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_NMP"                    ,	5,	1,	1082,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_FMP"                    ,	6,	1,	1082,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_SP"                     ,	7,	1,	1082,	"R/W",	0,	1,	0ull,	0},
+	{"ID_PSD"                      ,	8,	1,	1082,	"R/W",	0,	1,	0ull,	0},
+	{"ID_NMP"                      ,	9,	1,	1082,	"R/W",	0,	1,	0ull,	0},
+	{"ID_FMP"                      ,	10,	1,	1082,	"R/W",	0,	1,	0ull,	0},
+	{"ID_SP"                       ,	11,	1,	1082,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_NMP"                    ,	12,	1,	1082,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_FMP"                    ,	13,	1,	1082,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_SP"                     ,	14,	1,	1082,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	1082,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	1083,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALL_NMP"                     ,	1,	1,	1083,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_FMP"                     ,	2,	1,	1083,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_SP"                      ,	3,	1,	1083,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_4"                ,	4,	1,	1083,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX_NMP"                    ,	5,	1,	1083,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_FMP"                    ,	6,	1,	1083,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_SP"                     ,	7,	1,	1083,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_8"                ,	8,	1,	1083,	"R/W",	0,	0,	0ull,	0ull},
+	{"ID_NMP"                      ,	9,	1,	1083,	"R/W",	0,	1,	0ull,	0},
+	{"ID_FMP"                      ,	10,	1,	1083,	"R/W",	0,	1,	0ull,	0},
+	{"ID_SP"                       ,	11,	1,	1083,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_NMP"                    ,	12,	1,	1083,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_FMP"                    ,	13,	1,	1083,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_SP"                     ,	14,	1,	1083,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	1083,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	3,	1084,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_30"               ,	3,	28,	1084,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	31,	1,	1084,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1084,	"RAZ",	1,	1,	0,	0},
+	{"TOT_SILO"                    ,	0,	5,	1085,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	1085,	"RAZ",	1,	1,	0,	0},
+	{"ALL_PSD"                     ,	0,	1,	1086,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_NMP"                     ,	1,	1,	1086,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_FMP"                     ,	2,	1,	1086,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_SP"                      ,	3,	1,	1086,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_PSD"                    ,	4,	1,	1086,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_NMP"                    ,	5,	1,	1086,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_FMP"                    ,	6,	1,	1086,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_SP"                     ,	7,	1,	1086,	"R/W",	0,	1,	0ull,	0},
+	{"ID_PSD"                      ,	8,	1,	1086,	"R/W",	0,	1,	0ull,	0},
+	{"ID_NMP"                      ,	9,	1,	1086,	"R/W",	0,	1,	0ull,	0},
+	{"ID_FMP"                      ,	10,	1,	1086,	"R/W",	0,	1,	0ull,	0},
+	{"ID_SP"                       ,	11,	1,	1086,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_NMP"                    ,	12,	1,	1086,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_FMP"                    ,	13,	1,	1086,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_SP"                     ,	14,	1,	1086,	"R/W",	0,	1,	0ull,	0},
+	{"XMBOX_SP"                    ,	15,	1,	1086,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	1086,	"RAZ",	1,	1,	0,	0},
+	{"START_CNT"                   ,	0,	16,	1087,	"RO",	0,	1,	0ull,	0},
+	{"END_CNT"                     ,	16,	16,	1087,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1087,	"RAZ",	1,	1,	0,	0},
+	{"PRIORITY"                    ,	0,	2,	1088,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1088,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	3,	1,	1088,	"RO",	0,	0,	0ull,	0ull},
+	{"DEST_ID"                     ,	4,	1,	1088,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	1088,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	8,	8,	1088,	"RO",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	16,	16,	1088,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	32,	16,	1088,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1088,	"RAZ",	1,	1,	0,	0},
+	{"SEQ"                         ,	0,	32,	1089,	"RO",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	32,	8,	1089,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	1089,	"RAZ",	1,	1,	0,	0},
+	{"POST"                        ,	0,	8,	1090,	"RO",	0,	1,	128ull,	0},
+	{"N_POST"                      ,	8,	5,	1090,	"RO",	0,	1,	16ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	1090,	"RAZ",	1,	1,	0,	0},
+	{"COMP"                        ,	16,	8,	1090,	"RO",	0,	1,	128ull,	0},
+	{"MBOX"                        ,	24,	4,	1090,	"RO",	0,	1,	8ull,	0},
+	{"RESERVED_28_39"              ,	28,	12,	1090,	"RAZ",	1,	1,	0,	0},
+	{"RTN_PR1"                     ,	40,	8,	1090,	"RO",	0,	1,	0ull,	0},
+	{"RTN_PR2"                     ,	48,	8,	1090,	"RO",	0,	1,	0ull,	0},
+	{"RTN_PR3"                     ,	56,	8,	1090,	"RO",	0,	1,	0ull,	0},
+	{"IAOW_SEL"                    ,	0,	2,	1091,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	1091,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	4,	1,	1091,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	5,	1,	1091,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	1091,	"RAZ",	1,	1,	0,	0},
+	{"RD_PRIOR"                    ,	8,	2,	1091,	"R/W",	0,	0,	1ull,	1ull},
+	{"WR_PRIOR"                    ,	10,	2,	1091,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD_OP"                       ,	12,	3,	1091,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	1091,	"RAZ",	1,	1,	0,	0},
+	{"WR_OP"                       ,	16,	3,	1091,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	1091,	"RAZ",	1,	1,	0,	0},
+	{"SEQ"                         ,	0,	32,	1092,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1092,	"RAZ",	1,	1,	0,	0},
+	{"SRIO"                        ,	0,	1,	1093,	"RO",	1,	1,	0,	0},
+	{"ACCESS"                      ,	1,	1,	1093,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	1093,	"RAZ",	1,	1,	0,	0},
+	{"ITAG"                        ,	0,	5,	1094,	"RO",	0,	1,	16ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1094,	"RAZ",	1,	1,	0,	0},
+	{"OTAG"                        ,	8,	5,	1094,	"RO",	0,	1,	16ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	1094,	"RAZ",	1,	1,	0,	0},
+	{"O_CLR"                       ,	16,	1,	1094,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	1094,	"RAZ",	1,	1,	0,	0},
+	{"POST"                        ,	0,	8,	1095,	"R/W",	1,	1,	0,	0},
+	{"N_POST"                      ,	8,	5,	1095,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_13_15"              ,	13,	3,	1095,	"RAZ",	1,	1,	0,	0},
+	{"COMP"                        ,	16,	8,	1095,	"R/W",	1,	1,	0,	0},
+	{"MBOX"                        ,	24,	4,	1095,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_28_63"              ,	28,	36,	1095,	"RAZ",	1,	1,	0,	0},
+	{"PRIORITY"                    ,	0,	2,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1096,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	3,	1,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	4,	1,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	1096,	"RAZ",	1,	1,	0,	0},
+	{"PENDING"                     ,	8,	1,	1096,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_15"               ,	9,	7,	1096,	"RAZ",	1,	1,	0,	0},
+	{"DEST_ID"                     ,	16,	16,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	32,	16,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1096,	"RAZ",	1,	1,	0,	0},
+	{"PRIORITY"                    ,	0,	2,	1097,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1097,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	3,	1,	1097,	"RO",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	4,	1,	1097,	"RO",	0,	0,	0ull,	0ull},
+	{"RETRY"                       ,	5,	1,	1097,	"RO",	0,	0,	0ull,	0ull},
+	{"ERROR"                       ,	6,	1,	1097,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMEOUT"                     ,	7,	1,	1097,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1097,	"RAZ",	1,	1,	0,	0},
+	{"DEST_ID"                     ,	16,	16,	1097,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	32,	16,	1097,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1097,	"RAZ",	1,	1,	0,	0},
+	{"TX_TH0"                      ,	0,	4,	1098,	"R/W",	0,	0,	6ull,	3ull},
+	{"RESERVED_4_7"                ,	4,	4,	1098,	"RAZ",	1,	1,	0,	0},
+	{"TX_TH1"                      ,	8,	4,	1098,	"R/W",	0,	0,	4ull,	2ull},
+	{"RESERVED_12_15"              ,	12,	4,	1098,	"RAZ",	1,	1,	0,	0},
+	{"TX_TH2"                      ,	16,	4,	1098,	"R/W",	0,	0,	2ull,	1ull},
+	{"RESERVED_20_31"              ,	20,	12,	1098,	"RAZ",	1,	1,	0,	0},
+	{"TAG_TH0"                     ,	32,	5,	1098,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_37_39"              ,	37,	3,	1098,	"RAZ",	1,	1,	0,	0},
+	{"TAG_TH1"                     ,	40,	5,	1098,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_45_47"              ,	45,	3,	1098,	"RAZ",	1,	1,	0,	0},
+	{"TAG_TH2"                     ,	48,	5,	1098,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_53_63"              ,	53,	11,	1098,	"RAZ",	1,	1,	0,	0},
+	{"EMPH"                        ,	0,	4,	1099,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1099,	"RAZ",	1,	1,	0,	0},
+	{"S2M_PR0"                     ,	0,	8,	1100,	"RO",	0,	1,	0ull,	0},
+	{"S2M_PR1"                     ,	8,	8,	1100,	"RO",	0,	1,	0ull,	0},
+	{"S2M_PR2"                     ,	16,	8,	1100,	"RO",	0,	1,	0ull,	0},
+	{"S2M_PR3"                     ,	24,	8,	1100,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1100,	"RAZ",	1,	1,	0,	0},
+	{"GOOD"                        ,	0,	16,	1101,	"R/W",	0,	1,	0ull,	0},
+	{"BAD"                         ,	16,	16,	1101,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1101,	"RAZ",	1,	1,	0,	0},
+	{"ASSY_VEN"                    ,	0,	16,	1102,	"RO",	0,	0,	140ull,	0ull},
+	{"ASSY_ID"                     ,	16,	16,	1102,	"RO",	0,	0,	0ull,	0ull},
+	{"EXT_FPTR"                    ,	0,	16,	1103,	"RO",	0,	0,	256ull,	256ull},
+	{"ASSY_REV"                    ,	16,	16,	1103,	"RO",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1104,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_2"                ,	1,	2,	1104,	"RAZ",	1,	1,	0,	0},
+	{"NCA"                         ,	3,	1,	1104,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	4,	2,	1104,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	1104,	"RAZ",	1,	1,	0,	0},
+	{"LA"                          ,	8,	22,	1104,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_30_31"              ,	30,	2,	1104,	"RAZ",	1,	1,	0,	0},
+	{"FULL"                        ,	0,	1,	1105,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	1105,	"RAZ",	1,	1,	0,	0},
+	{"COMP_TAG"                    ,	0,	32,	1106,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEMORY"                      ,	0,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"DOORBELL"                    ,	1,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"IMSG0"                       ,	2,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"IMSG1"                       ,	3,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"HALT"                        ,	4,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	1107,	"RAZ",	1,	1,	0,	0},
+	{"VENDOR"                      ,	0,	16,	1108,	"RO",	0,	0,	140ull,	140ull},
+	{"DEVICE"                      ,	16,	16,	1108,	"RO",	0,	1,	146ull,	0},
+	{"REVISION"                    ,	0,	8,	1109,	"RO",	1,	1,	0,	0},
+	{"RESERVED_8_31"               ,	8,	24,	1109,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	1110,	"RAZ",	1,	1,	0,	0},
+	{"PORT_WR"                     ,	2,	1,	1110,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SWP"                    ,	3,	1,	1110,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_CLR"                    ,	4,	1,	1110,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SET"                    ,	5,	1,	1110,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_DEC"                    ,	6,	1,	1110,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_INC"                    ,	7,	1,	1110,	"RO",	0,	0,	1ull,	1ull},
+	{"TESTSWAP"                    ,	8,	1,	1110,	"RO",	0,	0,	0ull,	0ull},
+	{"COMPSWAP"                    ,	9,	1,	1110,	"RO",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	10,	1,	1110,	"RO",	0,	0,	1ull,	1ull},
+	{"MSG"                         ,	11,	1,	1110,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE_R"                     ,	12,	1,	1110,	"RO",	0,	0,	1ull,	1ull},
+	{"SWRITE"                      ,	13,	1,	1110,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE"                       ,	14,	1,	1110,	"RO",	0,	0,	1ull,	1ull},
+	{"READ"                        ,	15,	1,	1110,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_21"              ,	16,	6,	1110,	"RAZ",	1,	1,	0,	0},
+	{"TLB_INVS"                    ,	22,	1,	1110,	"RO",	0,	0,	0ull,	0ull},
+	{"TLB_INV"                     ,	23,	1,	1110,	"RO",	0,	0,	0ull,	0ull},
+	{"I_INVALD"                    ,	24,	1,	1110,	"RO",	0,	0,	0ull,	0ull},
+	{"IO_READ"                     ,	25,	1,	1110,	"RO",	0,	0,	0ull,	0ull},
+	{"D_FLUSH"                     ,	26,	1,	1110,	"RO",	0,	0,	0ull,	0ull},
+	{"CASTOUT"                     ,	27,	1,	1110,	"RO",	0,	0,	0ull,	0ull},
+	{"D_INVALD"                    ,	28,	1,	1110,	"RO",	0,	0,	0ull,	0ull},
+	{"RD_OWN"                      ,	29,	1,	1110,	"RO",	0,	0,	0ull,	0ull},
+	{"I_READ"                      ,	30,	1,	1110,	"RO",	0,	0,	0ull,	0ull},
+	{"GSM_READ"                    ,	31,	1,	1110,	"RO",	0,	0,	0ull,	0ull},
+	{"VALID"                       ,	0,	1,	1111,	"R/W0C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	1111,	"RAZ",	1,	1,	0,	0},
+	{"ERR_INFO"                    ,	4,	20,	1111,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_TYPE"                    ,	24,	5,	1111,	"R/W",	0,	0,	0ull,	0ull},
+	{"INF_TYPE"                    ,	29,	3,	1111,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_TOUT"                    ,	0,	1,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ACK"                     ,	1,	1,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEL_ERR"                     ,	2,	1,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"F_TOGGLE"                    ,	3,	1,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"PROTERR"                     ,	4,	1,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_ACK"                     ,	5,	1,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_14"               ,	6,	9,	1112,	"RAZ",	1,	1,	0,	0},
+	{"INV_DATA"                    ,	15,	1,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_CHAR"                    ,	16,	1,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	17,	1,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_CRC"                     ,	18,	1,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUT_ACK"                     ,	19,	1,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"NACK"                        ,	20,	1,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ID"                      ,	21,	1,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTL_CRC"                     ,	22,	1,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_30"              ,	23,	8,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"IMP_ERR"                     ,	31,	1,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RATE_CNT"                    ,	0,	8,	1113,	"R/W",	0,	1,	0ull,	0},
+	{"PK_RATE"                     ,	8,	8,	1113,	"R/W",	0,	1,	0ull,	0},
+	{"RATE_LIM"                    ,	16,	2,	1113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_23"              ,	18,	6,	1113,	"RAZ",	1,	1,	0,	0},
+	{"ERR_BIAS"                    ,	24,	8,	1113,	"R/W",	0,	0,	128ull,	128ull},
+	{"LNK_TOUT"                    ,	0,	1,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ACK"                     ,	1,	1,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEL_ERR"                     ,	2,	1,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"F_TOGGLE"                    ,	3,	1,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"PROTERR"                     ,	4,	1,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_ACK"                     ,	5,	1,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_14"               ,	6,	9,	1114,	"RAZ",	1,	1,	0,	0},
+	{"INV_DATA"                    ,	15,	1,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_CHAR"                    ,	16,	1,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	17,	1,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_CRC"                     ,	18,	1,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUT_ACK"                     ,	19,	1,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"NACK"                        ,	20,	1,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ID"                      ,	21,	1,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTL_CRC"                     ,	22,	1,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_30"              ,	23,	8,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"IMP_ERR"                     ,	31,	1,	1114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_15"               ,	0,	16,	1115,	"RAZ",	1,	1,	0,	0},
+	{"DGRAD_TH"                    ,	16,	8,	1115,	"R/W",	0,	0,	255ull,	128ull},
+	{"FAIL_TH"                     ,	24,	8,	1115,	"R/W",	0,	0,	255ull,	255ull},
+	{"EF_ID"                       ,	0,	16,	1116,	"RO",	0,	0,	7ull,	7ull},
+	{"EF_PTR"                      ,	16,	16,	1116,	"RO",	0,	0,	0ull,	0ull},
+	{"ADDR"                        ,	0,	32,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"XADDR"                       ,	0,	2,	1118,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1118,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	29,	1118,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPT_IDX"                    ,	0,	5,	1119,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_5"                ,	5,	1,	1119,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDPTR"                       ,	6,	1,	1119,	"R/W",	0,	0,	0ull,	0ull},
+	{"TT"                          ,	7,	1,	1119,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	8,	4,	1119,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATUS"                      ,	12,	4,	1119,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXTRA"                       ,	16,	8,	1119,	"R/W",	0,	0,	0ull,	0ull},
+	{"TTYPE"                       ,	24,	4,	1119,	"R/W",	0,	0,	0ull,	0ull},
+	{"FTYPE"                       ,	28,	4,	1119,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_14"               ,	0,	15,	1120,	"RAZ",	1,	1,	0,	0},
+	{"TT"                          ,	15,	1,	1120,	"R/W",	0,	0,	0ull,	0ull},
+	{"ID8"                         ,	16,	8,	1120,	"R/W",	0,	0,	0ull,	0ull},
+	{"ID16"                        ,	24,	8,	1120,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID8"                     ,	0,	8,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID16"                    ,	8,	8,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST_ID8"                     ,	16,	8,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST_ID16"                    ,	24,	8,	1121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESP_SZ"                     ,	0,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_21"               ,	1,	21,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_TRAN"                    ,	22,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_RESP"                    ,	23,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_TOUT"                    ,	24,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_TOUT"                    ,	25,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TGT"                     ,	26,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TRAN"                    ,	27,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_FMT"                     ,	28,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSM_ERR"                     ,	29,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_ERR"                     ,	30,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO_ERR"                      ,	31,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESP_SZ"                     ,	0,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_21"               ,	1,	21,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_TRAN"                    ,	22,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_RESP"                    ,	23,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_TOUT"                    ,	24,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_TOUT"                    ,	25,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TGT"                     ,	26,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TRAN"                    ,	27,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_FMT"                     ,	28,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSM_ERR"                     ,	29,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_ERR"                     ,	30,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO_ERR"                      ,	31,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1125,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1126,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1127,	"R/W",	0,	0,	0ull,	0ull},
+	{"HOSTID"                      ,	0,	16,	1128,	"R/W",	0,	0,	65535ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1128,	"RAZ",	1,	1,	0,	0},
+	{"RX_SYNC"                     ,	0,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_SYNC"                     ,	1,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_FLOW"                     ,	2,	1,	1129,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_19"               ,	3,	17,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_WM2"                      ,	20,	4,	1129,	"R/W",	0,	1,	2ull,	0},
+	{"TX_WM1"                      ,	24,	4,	1129,	"R/W",	0,	1,	3ull,	0},
+	{"TX_WM0"                      ,	28,	4,	1129,	"R/W",	0,	1,	4ull,	0},
+	{"RX_WM0"                      ,	0,	4,	1130,	"R/W",	0,	0,	4ull,	4ull},
+	{"RX_WM1"                      ,	4,	4,	1130,	"R/W",	0,	0,	3ull,	3ull},
+	{"RX_WM2"                      ,	8,	4,	1130,	"R/W",	0,	0,	2ull,	2ull},
+	{"RX_WM3"                      ,	12,	4,	1130,	"R/W",	0,	0,	1ull,	1ull},
+	{"TX_WM0"                      ,	16,	4,	1130,	"R/W",	0,	0,	4ull,	4ull},
+	{"TX_WM1"                      ,	20,	4,	1130,	"R/W",	0,	0,	3ull,	3ull},
+	{"TX_WM2"                      ,	24,	4,	1130,	"R/W",	0,	0,	2ull,	2ull},
+	{"TX_WM3"                      ,	28,	4,	1130,	"R/W",	0,	0,	1ull,	1ull},
+	{"PD_CTRL"                     ,	0,	32,	1131,	"R/W",	0,	0,	0ull,	0ull},
+	{"LN0_DIS"                     ,	0,	1,	1132,	"RO",	0,	0,	0ull,	0ull},
+	{"LN0_RX"                      ,	1,	3,	1132,	"RO",	0,	0,	0ull,	0ull},
+	{"LN1_DIS"                     ,	4,	1,	1132,	"RO",	0,	0,	0ull,	0ull},
+	{"LN1_RX"                      ,	5,	3,	1132,	"RO",	0,	0,	0ull,	0ull},
+	{"LN2_DIS"                     ,	8,	1,	1132,	"RO",	0,	0,	0ull,	0ull},
+	{"LN2_RX"                      ,	9,	3,	1132,	"RO",	0,	0,	0ull,	0ull},
+	{"LN3_DIS"                     ,	12,	1,	1132,	"RO",	0,	0,	0ull,	0ull},
+	{"LN3_RX"                      ,	13,	3,	1132,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1132,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_26"               ,	0,	27,	1133,	"RAZ",	1,	1,	0,	0},
+	{"LOOPBACK"                    ,	27,	2,	1133,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_29"              ,	29,	1,	1133,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_RESET"                    ,	30,	1,	1133,	"R/W",	0,	0,	1ull,	1ull},
+	{"TX_RESET"                    ,	31,	1,	1133,	"R/W",	0,	0,	1ull,	1ull},
+	{"INIT_SM"                     ,	0,	10,	1134,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_RDY"                      ,	10,	1,	1134,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_RDY"                      ,	11,	1,	1134,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	1134,	"RAZ",	1,	1,	0,	0},
+	{"OVERWRT"                     ,	0,	1,	1135,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	1135,	"RAZ",	1,	1,	0,	0},
+	{"PKT_DATA"                    ,	0,	32,	1136,	"RO",	0,	0,	0ull,	0ull},
+	{"FIFO_ST"                     ,	0,	4,	1137,	"RO",	0,	0,	0ull,	0ull},
+	{"FULL"                        ,	4,	1,	1137,	"RO",	0,	0,	0ull,	0ull},
+	{"DROP_CNT"                    ,	5,	7,	1137,	"RO",	0,	1,	0ull,	0},
+	{"BUFFERS"                     ,	12,	4,	1137,	"RO",	0,	0,	0ull,	0ull},
+	{"OCTETS"                      ,	16,	16,	1137,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_15"               ,	0,	16,	1138,	"RAZ",	1,	1,	0,	0},
+	{"OCTETS"                      ,	16,	16,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_DATA"                    ,	0,	32,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIFO_ST"                     ,	0,	4,	1140,	"RO",	0,	0,	0ull,	0ull},
+	{"FULL"                        ,	4,	1,	1140,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_11"               ,	5,	7,	1140,	"RAZ",	1,	1,	0,	0},
+	{"BUFFERS"                     ,	12,	4,	1140,	"RO",	0,	0,	0ull,	0ull},
+	{"OCTETS"                      ,	16,	16,	1140,	"RO",	0,	0,	0ull,	0ull},
+	{"STATUSN"                     ,	0,	3,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"STATUS1"                     ,	3,	1,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_5"                ,	4,	2,	1141,	"RAZ",	1,	1,	0,	0},
+	{"XTRAIN"                      ,	6,	1,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"XSYNC"                       ,	7,	1,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"DEC_ERR"                     ,	8,	4,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_TRAIN"                    ,	12,	1,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_SYNC"                     ,	13,	1,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_ADAPT"                    ,	14,	1,	1141,	"RO",	0,	0,	1ull,	1ull},
+	{"RX_INV"                      ,	15,	1,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_TYPE"                     ,	16,	2,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_MODE"                     ,	18,	1,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_TYPE"                     ,	19,	1,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"LANE"                        ,	20,	4,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"PORT"                        ,	24,	8,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"LCSBA"                       ,	0,	31,	1142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1142,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_20"               ,	0,	21,	1143,	"R/W",	0,	0,	0ull,	0ull},
+	{"LCSBA"                       ,	21,	11,	1143,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR48"                      ,	0,	16,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR64"                      ,	16,	16,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR66"                      ,	1,	2,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_13"               ,	3,	11,	1145,	"RAZ",	1,	1,	0,	0},
+	{"ADDR32"                      ,	14,	18,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR48"                      ,	0,	16,	1146,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR64"                      ,	16,	16,	1146,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1147,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR66"                      ,	1,	2,	1147,	"R/W",	0,	0,	0ull,	0ull},
+	{"BARSIZE"                     ,	3,	4,	1147,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_19"               ,	7,	13,	1147,	"RAZ",	1,	1,	0,	0},
+	{"ADDR32"                      ,	20,	12,	1147,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1148,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR66"                      ,	1,	2,	1148,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAX"                         ,	3,	1,	1148,	"R/W",	0,	0,	0ull,	0ull},
+	{"ESX"                         ,	4,	2,	1148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_8"                ,	6,	3,	1148,	"RAZ",	1,	1,	0,	0},
+	{"ADDR48"                      ,	9,	7,	1148,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR64"                      ,	16,	16,	1148,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_RTRY"                    ,	0,	16,	1149,	"R/W",	0,	1,	0ull,	0},
+	{"TYPE_MRG"                    ,	16,	1,	1149,	"R/W",	0,	0,	1ull,	1ull},
+	{"EOP_MRG"                     ,	17,	1,	1149,	"R/W",	0,	0,	1ull,	1ull},
+	{"RX_SPF"                      ,	18,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_ZERO"                    ,	19,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEC_SPF"                     ,	20,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	1149,	"RAZ",	1,	1,	0,	0},
+	{"EX_ADDR"                     ,	0,	3,	1150,	"RO",	0,	0,	7ull,	7ull},
+	{"EX_FEAT"                     ,	3,	1,	1150,	"RO",	0,	0,	1ull,	1ull},
+	{"LG_TRAN"                     ,	4,	1,	1150,	"RO",	0,	0,	1ull,	1ull},
+	{"CRF"                         ,	5,	1,	1150,	"RO",	0,	0,	0ull,	0ull},
+	{"SUPPRESS"                    ,	6,	1,	1150,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_26"               ,	7,	20,	1150,	"RAZ",	1,	1,	0,	0},
+	{"MULT_PRT"                    ,	27,	1,	1150,	"RO",	0,	0,	0ull,	0ull},
+	{"SWITCHF"                     ,	28,	1,	1150,	"RO",	0,	0,	0ull,	0ull},
+	{"PROC"                        ,	29,	1,	1150,	"RO",	0,	0,	1ull,	1ull},
+	{"MEMORY"                      ,	30,	1,	1150,	"RO",	0,	0,	1ull,	1ull},
+	{"BRIDGE"                      ,	31,	1,	1150,	"RO",	0,	0,	0ull,	0ull},
+	{"EX_ADDR"                     ,	0,	3,	1151,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_31"               ,	3,	29,	1151,	"RAZ",	1,	1,	0,	0},
+	{"PT_TYPE"                     ,	0,	1,	1152,	"RO",	0,	0,	1ull,	1ull},
+	{"PRT_LOCK"                    ,	1,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"DROP_PKT"                    ,	2,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"STP_PORT"                    ,	3,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUPPRESS"                    ,	4,	8,	1152,	"RO",	0,	0,	0ull,	0ull},
+	{"EX_STAT"                     ,	12,	2,	1152,	"RO",	0,	0,	0ull,	0ull},
+	{"EX_WIDTH"                    ,	14,	2,	1152,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	1152,	"RAZ",	1,	1,	0,	0},
+	{"ENUMB"                       ,	17,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_18"              ,	18,	1,	1152,	"RAZ",	1,	1,	0,	0},
+	{"MCAST"                       ,	19,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIS_ERR"                     ,	20,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"I_ENABLE"                    ,	21,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ENABLE"                    ,	22,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"DISABLE"                     ,	23,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"OV_WIDTH"                    ,	24,	3,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"IT_WIDTH"                    ,	27,	3,	1152,	"RO",	0,	1,	0ull,	0},
+	{"PT_WIDTH"                    ,	30,	2,	1152,	"RO",	0,	0,	3ull,	3ull},
+	{"EMPH_EN"                     ,	0,	1,	1153,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_EMPH"                     ,	1,	1,	1153,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_15"               ,	2,	14,	1153,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB_625G"                    ,	16,	1,	1153,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUP_625G"                    ,	17,	1,	1153,	"RO",	0,	0,	0ull,	0ull},
+	{"ENB_500G"                    ,	18,	1,	1153,	"R/W",	1,	1,	0,	0},
+	{"SUB_500G"                    ,	19,	1,	1153,	"RO",	1,	1,	0,	0},
+	{"ENB_312G"                    ,	20,	1,	1153,	"R/W",	1,	1,	0,	0},
+	{"SUP_312G"                    ,	21,	1,	1153,	"RO",	1,	1,	0,	0},
+	{"ENB_250G"                    ,	22,	1,	1153,	"R/W",	1,	1,	0,	0},
+	{"SUP_250G"                    ,	23,	1,	1153,	"RO",	1,	1,	0,	0},
+	{"ENB_125G"                    ,	24,	1,	1153,	"R/W",	1,	1,	0,	0},
+	{"SUP_125G"                    ,	25,	1,	1153,	"RO",	1,	1,	0,	0},
+	{"BAUD_ENB"                    ,	26,	1,	1153,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAUD_SUP"                    ,	27,	1,	1153,	"RO",	0,	0,	0ull,	0ull},
+	{"SEL_BAUD"                    ,	28,	4,	1153,	"RO",	0,	1,	0ull,	0},
+	{"PT_UINIT"                    ,	0,	1,	1154,	"RO",	0,	0,	1ull,	0ull},
+	{"PT_OK"                       ,	1,	1,	1154,	"RO",	0,	0,	0ull,	1ull},
+	{"PT_ERROR"                    ,	2,	1,	1154,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1154,	"RAZ",	1,	1,	0,	0},
+	{"PT_WRITE"                    ,	4,	1,	1154,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	1154,	"RAZ",	1,	1,	0,	0},
+	{"I_SM_ERR"                    ,	8,	1,	1154,	"RO",	0,	0,	0ull,	0ull},
+	{"I_ERROR"                     ,	9,	1,	1154,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I_SM_RET"                    ,	10,	1,	1154,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	1154,	"RAZ",	1,	1,	0,	0},
+	{"O_SM_ERR"                    ,	16,	1,	1154,	"RO",	0,	0,	0ull,	0ull},
+	{"O_ERROR"                     ,	17,	1,	1154,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"O_SM_RET"                    ,	18,	1,	1154,	"RO",	0,	0,	0ull,	0ull},
+	{"O_RTRIED"                    ,	19,	1,	1154,	"RO",	0,	0,	0ull,	0ull},
+	{"O_RETRY"                     ,	20,	1,	1154,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	1154,	"RAZ",	1,	1,	0,	0},
+	{"O_DGRAD"                     ,	24,	1,	1154,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"O_FAIL"                      ,	25,	1,	1154,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKT_DROP"                    ,	26,	1,	1154,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_31"              ,	27,	5,	1154,	"RAZ",	1,	1,	0,	0},
+	{"CMD"                         ,	0,	3,	1155,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_31"               ,	3,	29,	1155,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	5,	1156,	"RO",	0,	1,	0ull,	0},
+	{"ACKID"                       ,	5,	6,	1156,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_11_30"              ,	11,	20,	1156,	"RAZ",	1,	1,	0,	0},
+	{"VALID"                       ,	31,	1,	1156,	"RO",	0,	1,	0ull,	0},
+	{"O_ACKID"                     ,	0,	6,	1157,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	1157,	"RAZ",	1,	1,	0,	0},
+	{"E_ACKID"                     ,	8,	6,	1157,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_23"              ,	14,	10,	1157,	"RAZ",	1,	1,	0,	0},
+	{"I_ACKID"                     ,	24,	6,	1157,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_30_31"              ,	30,	2,	1157,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_28"               ,	0,	29,	1158,	"RAZ",	1,	1,	0,	0},
+	{"DISCOVER"                    ,	29,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"MENABLE"                     ,	30,	1,	1158,	"R/W",	1,	0,	0,	1ull},
+	{"HOST"                        ,	31,	1,	1158,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1159,	"RAZ",	1,	1,	0,	0},
+	{"TIMEOUT"                     ,	8,	24,	1159,	"R/W",	0,	0,	16777215ull,	0ull},
+	{"EF_ID"                       ,	0,	16,	1160,	"RO",	0,	0,	1ull,	0ull},
+	{"EF_PTR"                      ,	16,	16,	1160,	"RO",	0,	0,	4096ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	1161,	"RAZ",	1,	1,	0,	0},
+	{"TIMEOUT"                     ,	8,	24,	1161,	"R/W",	0,	0,	16777215ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	1162,	"RAZ",	1,	1,	0,	0},
+	{"TIMEOUT"                     ,	8,	24,	1162,	"R/W",	0,	1,	0ull,	0},
+	{"ID16"                        ,	0,	16,	1163,	"R/W",	0,	0,	65535ull,	0ull},
+	{"ID8"                         ,	16,	8,	1163,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1163,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE16"                    ,	0,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE8"                     ,	1,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	1164,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	0,	16,	1165,	"R/W",	0,	0,	65535ull,	0ull},
+	{"ID8"                         ,	16,	8,	1165,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1165,	"RAZ",	1,	1,	0,	0},
+	{"EF_ID"                       ,	0,	16,	1166,	"RO",	0,	0,	13ull,	13ull},
+	{"EF_PTR"                      ,	16,	16,	1166,	"RO",	0,	0,	8192ull,	0ull},
+	{"RESERVED_0_1"                ,	0,	2,	1167,	"RAZ",	1,	1,	0,	0},
+	{"PORT_WR"                     ,	2,	1,	1167,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SWP"                    ,	3,	1,	1167,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_CLR"                    ,	4,	1,	1167,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SET"                    ,	5,	1,	1167,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_DEC"                    ,	6,	1,	1167,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_INC"                    ,	7,	1,	1167,	"RO",	0,	0,	1ull,	1ull},
+	{"TESTSWAP"                    ,	8,	1,	1167,	"RO",	0,	0,	0ull,	0ull},
+	{"COMPSWAP"                    ,	9,	1,	1167,	"RO",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	10,	1,	1167,	"RO",	0,	0,	1ull,	1ull},
+	{"MSG"                         ,	11,	1,	1167,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE_R"                     ,	12,	1,	1167,	"RO",	0,	0,	1ull,	1ull},
+	{"SWRITE"                      ,	13,	1,	1167,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE"                       ,	14,	1,	1167,	"RO",	0,	0,	1ull,	1ull},
+	{"READ"                        ,	15,	1,	1167,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_21"              ,	16,	6,	1167,	"RAZ",	1,	1,	0,	0},
+	{"TLB_INVS"                    ,	22,	1,	1167,	"RO",	0,	0,	0ull,	0ull},
+	{"TLB_INV"                     ,	23,	1,	1167,	"RO",	0,	0,	0ull,	0ull},
+	{"I_INVALD"                    ,	24,	1,	1167,	"RO",	0,	0,	0ull,	0ull},
+	{"IO_READ"                     ,	25,	1,	1167,	"RO",	0,	0,	0ull,	0ull},
+	{"D_FLUSH"                     ,	26,	1,	1167,	"RO",	0,	0,	0ull,	0ull},
+	{"CASTOUT"                     ,	27,	1,	1167,	"RO",	0,	0,	0ull,	0ull},
+	{"D_INVALD"                    ,	28,	1,	1167,	"RO",	0,	0,	0ull,	0ull},
+	{"RD_OWN"                      ,	29,	1,	1167,	"RO",	0,	0,	0ull,	0ull},
+	{"I_READ"                      ,	30,	1,	1167,	"RO",	0,	0,	0ull,	0ull},
+	{"GSM_READ"                    ,	31,	1,	1167,	"RO",	0,	0,	0ull,	0ull},
+	{"DROP_CNT"                    ,	0,	16,	1168,	"RO",	0,	1,	0ull,	0},
+	{"DROP"                        ,	16,	1,	1168,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	1168,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	22,	1169,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1169,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	24,	22,	1169,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	1169,	"RAZ",	1,	1,	0,	0},
+	{"ENA"                         ,	47,	1,	1169,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1169,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	20,	1170,	"RO",	1,	0,	0,	0ull},
+	{"BASE"                        ,	20,	31,	1170,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	51,	13,	1170,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	0,	7,	1171,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	1171,	"RO",	1,	0,	0,	0ull},
+	{"CSIZE"                       ,	8,	13,	1171,	"RO",	1,	0,	0,	0ull},
+	{"CPOOL"                       ,	21,	3,	1171,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	1171,	"RAZ",	1,	1,	0,	0},
+	{"RING"                        ,	0,	4,	1172,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_BUCKETS"                 ,	4,	20,	1172,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIRST_BUCKET"                ,	24,	31,	1172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	1172,	"RAZ",	1,	1,	0,	0},
+	{"RING"                        ,	0,	4,	1173,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	4,	22,	1173,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORDS_PER_CHUNK"             ,	26,	13,	1173,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	39,	3,	1173,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	42,	1,	1173,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	1173,	"RAZ",	1,	1,	0,	0},
+	{"CTL"                         ,	0,	1,	1174,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	1,	1,	1174,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	2,	2,	1174,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1174,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	1175,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1175,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE_TIMERS"               ,	0,	1,	1176,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	1176,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	2,	1,	1176,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	1176,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	1177,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1177,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	1178,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	1178,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1178,	"RAZ",	1,	1,	0,	0},
+	{"TDF"                         ,	0,	1,	1179,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1179,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRAP"                        ,	1,	1,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRIG_CTL"                    ,	2,	2,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIME_GRN"                    ,	4,	3,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"FULL_THR"                    ,	7,	2,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	9,	1,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	10,	1,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	11,	1,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	12,	1,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_ENA"                    ,	13,	1,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNORE_O"                    ,	14,	1,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKALWAYS"                   ,	15,	1,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDAT_MD"                     ,	16,	1,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	1180,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	8,	1181,	"RO",	0,	0,	0ull,	0ull},
+	{"RPTR"                        ,	8,	8,	1181,	"RO",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	16,	48,	1181,	"RO",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	10,	1182,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	1182,	"RAZ",	1,	1,	0,	0},
+	{"RPTR"                        ,	12,	10,	1182,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1182,	"RAZ",	1,	1,	0,	0},
+	{"CYCLES"                      ,	24,	40,	1182,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1183,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1183,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1184,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1184,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1185,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1185,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1185,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1185,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1185,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1185,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1186,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1186,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1186,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1186,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1186,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1186,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1186,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1186,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1186,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1186,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1186,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1186,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1186,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1186,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1186,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1186,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1186,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1186,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1186,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1186,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	10,	1187,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	1187,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1187,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1187,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1187,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1187,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1187,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	0,	1,	1188,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	1,	1,	1188,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	2,	1,	1188,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	3,	1,	1188,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1188,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	1189,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	5,	1190,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	1190,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1191,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1191,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1192,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1192,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1193,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1193,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1193,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1193,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1193,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1193,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1194,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1194,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1194,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1194,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1194,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1194,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1194,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1194,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1194,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1194,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1194,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1194,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1194,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1194,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1194,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1194,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1194,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1194,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1194,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1194,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	10,	1195,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	1195,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1195,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1195,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1195,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1195,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1195,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1196,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1196,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1197,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1197,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1198,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1198,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1198,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1198,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1198,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1198,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1199,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1199,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1199,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1199,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1199,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1199,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1199,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1199,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1199,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1199,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1199,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1199,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1199,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1199,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1199,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1199,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1199,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1199,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1199,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1199,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	10,	1200,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	1200,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1200,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1200,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1200,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1200,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1200,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	1201,	"R/W",	0,	1,	0ull,	0},
+	{"LPL"                         ,	5,	27,	1201,	"R/W",	0,	1,	0ull,	0},
+	{"CF"                          ,	0,	1,	1202,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_31"               ,	1,	31,	1202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTRLDSSEG"                   ,	0,	32,	1203,	"R/W",	0,	1,	0ull,	0},
+	{"FI"                          ,	0,	14,	1204,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_31"              ,	14,	18,	1204,	"RO",	0,	0,	0ull,	0ull},
+	{"CAPLENGTH"                   ,	0,	8,	1205,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_8_15"               ,	8,	8,	1205,	"RO",	0,	0,	0ull,	0ull},
+	{"HCIVERSION"                  ,	16,	16,	1205,	"RO",	0,	0,	256ull,	256ull},
+	{"AC64"                        ,	0,	1,	1206,	"RO",	0,	0,	1ull,	1ull},
+	{"PFLF"                        ,	1,	1,	1206,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPC"                        ,	2,	1,	1206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1206,	"RO",	0,	0,	0ull,	0ull},
+	{"IST"                         ,	4,	4,	1206,	"RO",	0,	0,	2ull,	2ull},
+	{"EECP"                        ,	8,	8,	1206,	"RO",	0,	0,	160ull,	160ull},
+	{"RESERVED_16_31"              ,	16,	16,	1206,	"RO",	0,	0,	0ull,	0ull},
+	{"N_PORTS"                     ,	0,	4,	1207,	"RO",	0,	0,	2ull,	2ull},
+	{"PPC"                         ,	4,	1,	1207,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	1207,	"RO",	0,	0,	0ull,	0ull},
+	{"PRR"                         ,	7,	1,	1207,	"RO",	0,	0,	0ull,	0ull},
+	{"N_PCC"                       ,	8,	4,	1207,	"RO",	0,	0,	2ull,	2ull},
+	{"N_CC"                        ,	12,	4,	1207,	"RO",	0,	0,	1ull,	1ull},
+	{"P_INDICATOR"                 ,	16,	1,	1207,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	1207,	"RO",	0,	0,	0ull,	0ull},
+	{"DPN"                         ,	20,	4,	1207,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1207,	"RO",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	0,	1,	1208,	"R/W",	0,	0,	0ull,	0ull},
+	{"MFMC"                        ,	1,	13,	1208,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	1208,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_0"                ,	0,	1,	1209,	"R/W",	0,	0,	0ull,	0ull},
+	{"TA_OFF"                      ,	1,	8,	1209,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	1209,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXTX_TADAO"                  ,	10,	3,	1209,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	1209,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCP_RW"                      ,	0,	1,	1210,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCP_FW"                      ,	1,	1,	1210,	"R/W",	0,	0,	0ull,	0ull},
+	{"PESD"                        ,	2,	1,	1210,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1210,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NAKRF_DIS"                   ,	4,	1,	1210,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTO_DIS"                    ,	5,	1,	1210,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	1210,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_30"               ,	0,	31,	1211,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	31,	1,	1211,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_ADDR"                    ,	0,	32,	1212,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_11"               ,	0,	12,	1213,	"R/W",	0,	1,	0ull,	0},
+	{"BADDR"                       ,	12,	20,	1213,	"R/W",	0,	1,	0ull,	0},
+	{"CCS"                         ,	0,	1,	1214,	"RO",	0,	0,	0ull,	0ull},
+	{"CSC"                         ,	1,	1,	1214,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PED"                         ,	2,	1,	1214,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEDC"                        ,	3,	1,	1214,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OCA"                         ,	4,	1,	1214,	"RO",	0,	0,	0ull,	0ull},
+	{"OCC"                         ,	5,	1,	1214,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPR"                         ,	6,	1,	1214,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPD"                         ,	7,	1,	1214,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRST"                        ,	8,	1,	1214,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	1214,	"RO",	0,	0,	0ull,	0ull},
+	{"LSTS"                        ,	10,	2,	1214,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	12,	1,	1214,	"RO",	0,	0,	1ull,	1ull},
+	{"PO"                          ,	13,	1,	1214,	"R/W",	0,	0,	1ull,	0ull},
+	{"PIC"                         ,	14,	2,	1214,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTC"                         ,	16,	4,	1214,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKCNNT_E"                    ,	20,	1,	1214,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKDSCNNT_E"                  ,	21,	1,	1214,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKOC_E"                      ,	22,	1,	1214,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	1214,	"RO",	0,	0,	0ull,	0ull},
+	{"RS"                          ,	0,	1,	1215,	"R/W",	0,	0,	0ull,	1ull},
+	{"HCRESET"                     ,	1,	1,	1215,	"R/W",	0,	0,	0ull,	0ull},
+	{"FLS"                         ,	2,	2,	1215,	"RO",	0,	0,	0ull,	0ull},
+	{"PS_EN"                       ,	4,	1,	1215,	"R/W",	0,	0,	0ull,	0ull},
+	{"AS_EN"                       ,	5,	1,	1215,	"R/W",	0,	0,	0ull,	0ull},
+	{"IAA_DB"                      ,	6,	1,	1215,	"R/W",	0,	0,	0ull,	0ull},
+	{"LHCR"                        ,	7,	1,	1215,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASPMC"                       ,	8,	2,	1215,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	1215,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPM_EN"                     ,	11,	1,	1215,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	1215,	"RO",	0,	0,	0ull,	0ull},
+	{"ITC"                         ,	16,	8,	1215,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_24_31"              ,	24,	8,	1215,	"RO",	0,	0,	0ull,	0ull},
+	{"USBINT_EN"                   ,	0,	1,	1216,	"R/W",	0,	1,	0ull,	0},
+	{"USBERRINT_EN"                ,	1,	1,	1216,	"R/W",	0,	1,	0ull,	0},
+	{"PCI_EN"                      ,	2,	1,	1216,	"R/W",	0,	1,	0ull,	0},
+	{"FLRO_EN"                     ,	3,	1,	1216,	"R/W",	0,	1,	0ull,	0},
+	{"HSERR_EN"                    ,	4,	1,	1216,	"R/W",	0,	1,	0ull,	0},
+	{"IOAA_EN"                     ,	5,	1,	1216,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_31"               ,	6,	26,	1216,	"RO",	0,	0,	0ull,	0ull},
+	{"USBINT"                      ,	0,	1,	1217,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBERRINT"                   ,	1,	1,	1217,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCD"                         ,	2,	1,	1217,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FLRO"                        ,	3,	1,	1217,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HSYSERR"                     ,	4,	1,	1217,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOAA"                        ,	5,	1,	1217,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	1217,	"RO",	0,	0,	0ull,	0ull},
+	{"HCHTD"                       ,	12,	1,	1217,	"RO",	0,	0,	1ull,	0ull},
+	{"RECLM"                       ,	13,	1,	1217,	"RO",	0,	0,	0ull,	0ull},
+	{"PSS"                         ,	14,	1,	1217,	"RO",	0,	0,	0ull,	0ull},
+	{"ASS"                         ,	15,	1,	1217,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1217,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1218,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCED"                        ,	4,	28,	1218,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1219,	"R/W",	0,	0,	0ull,	0ull},
+	{"BHED"                        ,	4,	28,	1219,	"R/W",	0,	1,	0ull,	0},
+	{"HCR"                         ,	0,	1,	1220,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLF"                         ,	1,	1,	1220,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLF"                         ,	2,	1,	1220,	"R/W",	0,	0,	0ull,	0ull},
+	{"OCR"                         ,	3,	1,	1220,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	1220,	"RO",	0,	0,	0ull,	0ull},
+	{"SOC"                         ,	16,	2,	1220,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	1220,	"RO",	0,	0,	0ull,	0ull},
+	{"CBSR"                        ,	0,	2,	1221,	"R/W",	0,	1,	0ull,	0},
+	{"PLE"                         ,	2,	1,	1221,	"R/W",	0,	0,	0ull,	0ull},
+	{"IE"                          ,	3,	1,	1221,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLE"                         ,	4,	1,	1221,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLE"                         ,	5,	1,	1221,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCFS"                        ,	6,	2,	1221,	"R/W",	0,	0,	0ull,	0ull},
+	{"IR"                          ,	8,	1,	1221,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWC"                         ,	9,	1,	1221,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWE"                         ,	10,	1,	1221,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	1221,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1222,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCED"                        ,	4,	28,	1222,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1223,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHED"                        ,	4,	28,	1223,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1224,	"RO",	0,	0,	0ull,	0ull},
+	{"DH"                          ,	4,	28,	1224,	"RO",	0,	1,	0ull,	0},
+	{"FI"                          ,	0,	14,	1225,	"R/W",	0,	1,	11999ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	1225,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSMPS"                       ,	16,	15,	1225,	"R/W",	0,	1,	0ull,	0},
+	{"FIT"                         ,	31,	1,	1225,	"R/W",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	0,	16,	1226,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	1226,	"RO",	0,	0,	0ull,	0ull},
+	{"FR"                          ,	0,	14,	1227,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_30"              ,	14,	17,	1227,	"RO",	0,	0,	0ull,	0ull},
+	{"FRT"                         ,	31,	1,	1227,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	1228,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCCA"                        ,	8,	24,	1228,	"R/W",	0,	1,	0ull,	0},
+	{"SO"                          ,	0,	1,	1229,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1229,	"R/W",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1229,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1229,	"R/W",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1229,	"R/W",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1229,	"R/W",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1229,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1229,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1229,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIE"                         ,	31,	1,	1229,	"R/W",	0,	0,	0ull,	0ull},
+	{"SO"                          ,	0,	1,	1230,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1230,	"R/W",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1230,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1230,	"R/W",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1230,	"R/W",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1230,	"R/W",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1230,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1230,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1230,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIE"                         ,	31,	1,	1230,	"R/W",	0,	0,	0ull,	0ull},
+	{"SO"                          ,	0,	1,	1231,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1231,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1231,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1231,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1231,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1231,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1231,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1231,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1231,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1231,	"RO",	0,	0,	0ull,	0ull},
+	{"LST"                         ,	0,	12,	1232,	"R/W",	0,	1,	1576ull,	0},
+	{"RESERVED_12_31"              ,	12,	20,	1232,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1233,	"RO",	0,	0,	0ull,	0ull},
+	{"PCED"                        ,	4,	28,	1233,	"RO",	0,	1,	0ull,	0},
+	{"PS"                          ,	0,	14,	1234,	"R/W",	0,	0,	0ull,	15975ull},
+	{"RESERVED_14_31"              ,	14,	18,	1234,	"R/W",	0,	0,	0ull,	0ull},
+	{"REV"                         ,	0,	8,	1235,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_8_31"               ,	8,	24,	1235,	"RO",	0,	0,	0ull,	0ull},
+	{"NDP"                         ,	0,	8,	1236,	"RO",	0,	0,	2ull,	2ull},
+	{"NPS"                         ,	8,	1,	1236,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSM"                         ,	9,	1,	1236,	"R/W",	0,	0,	1ull,	1ull},
+	{"DT"                          ,	10,	1,	1236,	"RO",	0,	0,	0ull,	0ull},
+	{"OCPM"                        ,	11,	1,	1236,	"R/W",	1,	1,	0,	0},
+	{"NOCP"                        ,	12,	1,	1236,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_23"              ,	13,	11,	1236,	"RO",	0,	0,	0ull,	0ull},
+	{"POTPGT"                      ,	24,	8,	1236,	"R/W",	0,	0,	1ull,	1ull},
+	{"DR"                          ,	0,	16,	1237,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPCM"                        ,	16,	16,	1237,	"R/W",	0,	1,	0ull,	0},
+	{"CCS"                         ,	0,	1,	1238,	"R/W",	0,	1,	0ull,	0},
+	{"PES"                         ,	1,	1,	1238,	"R/W",	0,	1,	0ull,	0},
+	{"PSS"                         ,	2,	1,	1238,	"R/W",	0,	1,	0ull,	0},
+	{"POCI"                        ,	3,	1,	1238,	"R/W",	0,	1,	0ull,	0},
+	{"PRS"                         ,	4,	1,	1238,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1238,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS"                         ,	8,	1,	1238,	"R/W",	0,	1,	0ull,	0},
+	{"LSDA"                        ,	9,	1,	1238,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_10_15"              ,	10,	6,	1238,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSC"                         ,	16,	1,	1238,	"R/W",	0,	1,	0ull,	0},
+	{"PESC"                        ,	17,	1,	1238,	"R/W",	0,	1,	0ull,	0},
+	{"PSSC"                        ,	18,	1,	1238,	"R/W",	0,	1,	0ull,	0},
+	{"OCIC"                        ,	19,	1,	1238,	"R/W",	0,	1,	0ull,	0},
+	{"PRSC"                        ,	20,	1,	1238,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_31"              ,	21,	11,	1238,	"R/W",	0,	0,	0ull,	0ull},
+	{"LPS"                         ,	0,	1,	1239,	"R/W",	0,	0,	0ull,	0ull},
+	{"OCI"                         ,	1,	1,	1239,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_14"               ,	2,	13,	1239,	"RO",	0,	0,	0ull,	0ull},
+	{"DRWE"                        ,	15,	1,	1239,	"R/W",	0,	1,	0ull,	0},
+	{"LPSC"                        ,	16,	1,	1239,	"R/W",	0,	1,	0ull,	0},
+	{"CCIC"                        ,	17,	1,	1239,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_18_30"              ,	18,	13,	1239,	"RO",	0,	0,	0ull,	0ull},
+	{"CRWE"                        ,	31,	1,	1239,	"WO",	1,	1,	0,	0},
+	{"RESERVED_0_30"               ,	0,	31,	1240,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	31,	1,	1240,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_ADDR"                    ,	0,	32,	1241,	"RO",	0,	0,	0ull,	0ull},
+	{"PPAF_BIS"                    ,	0,	1,	1242,	"RO",	0,	0,	0ull,	0ull},
+	{"WRBM_BIS"                    ,	1,	1,	1242,	"RO",	0,	0,	0ull,	0ull},
+	{"ORBM_BIS"                    ,	2,	1,	1242,	"RO",	0,	0,	0ull,	0ull},
+	{"ERBM_BIS"                    ,	3,	1,	1242,	"RO",	0,	0,	0ull,	0ull},
+	{"DESC_BIS"                    ,	4,	1,	1242,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_BIS"                    ,	5,	1,	1242,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1242,	"RO",	1,	1,	0,	0},
+	{"HRST"                        ,	0,	1,	1243,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_PRST"                      ,	1,	1,	1243,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_POR"                       ,	2,	1,	1243,	"R/W",	0,	0,	1ull,	0ull},
+	{"P_COM_ON"                    ,	3,	1,	1243,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	1243,	"R/W",	0,	1,	0ull,	0},
+	{"P_REFCLK_DIV"                ,	5,	2,	1243,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_REFCLK_SEL"                ,	7,	2,	1243,	"R/W",	0,	0,	0ull,	0ull},
+	{"H_DIV"                       ,	9,	4,	1243,	"R/W",	0,	0,	6ull,	6ull},
+	{"O_CLKDIV_EN"                 ,	13,	1,	1243,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_EN"                 ,	14,	1,	1243,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_RST"                ,	15,	1,	1243,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_BYP"                ,	16,	1,	1243,	"R/W",	0,	0,	0ull,	0ull},
+	{"O_CLKDIV_RST"                ,	17,	1,	1243,	"R/W",	0,	0,	0ull,	1ull},
+	{"APP_START_CLK"               ,	18,	1,	1243,	"R/W",	0,	0,	0ull,	0ull},
+	{"OHCI_SUSP_LGCY"              ,	19,	1,	1243,	"R/W",	0,	0,	1ull,	1ull},
+	{"OHCI_SM"                     ,	20,	1,	1243,	"R/W",	0,	0,	0ull,	0ull},
+	{"OHCI_CLKCKTRST"              ,	21,	1,	1243,	"R/W",	0,	0,	1ull,	1ull},
+	{"EHCI_SM"                     ,	22,	1,	1243,	"R/W",	0,	0,	0ull,	0ull},
+	{"START_BIST"                  ,	23,	1,	1243,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLEAR_BIST"                  ,	24,	1,	1243,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1243,	"RAZ",	1,	1,	0,	0},
+	{"L2C_ADDR_MSB"                ,	0,	8,	1244,	"R/W",	0,	1,	0ull,	0},
+	{"EHCI_64B_ADDR_EN"            ,	8,	1,	1244,	"R/W",	0,	0,	1ull,	1ull},
+	{"INV_REG_A2"                  ,	9,	1,	1244,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DESC_EMOD"               ,	10,	2,	1244,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BUFF_EMOD"               ,	12,	2,	1244,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2C_STT"                     ,	14,	1,	1244,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_0PAG"                    ,	15,	1,	1244,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BC"                      ,	16,	1,	1244,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DC"                      ,	17,	1,	1244,	"R/W",	0,	0,	1ull,	1ull},
+	{"REG_NB"                      ,	18,	1,	1244,	"R/W",	0,	0,	0ull,	0ull},
+	{"DESC_RBM"                    ,	19,	1,	1244,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1244,	"RAZ",	1,	1,	0,	0},
+	{"FLA"                         ,	0,	6,	1245,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	1245,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	1246,	"RAZ",	1,	1,	0,	0},
+	{"TO_VAL"                      ,	5,	27,	1246,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1246,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	1247,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	1247,	"RAZ",	1,	1,	0,	0},
+	{"PP_PSH_F"                    ,	0,	1,	1248,	"R/W",	0,	0,	0ull,	0ull},
+	{"ER_PSH_F"                    ,	1,	1,	1248,	"R/W",	0,	0,	0ull,	0ull},
+	{"OR_PSH_F"                    ,	2,	1,	1248,	"R/W",	0,	0,	0ull,	0ull},
+	{"CF_PSH_F"                    ,	3,	1,	1248,	"R/W",	0,	0,	0ull,	0ull},
+	{"WB_PSH_F"                    ,	4,	1,	1248,	"R/W",	0,	0,	0ull,	0ull},
+	{"WB_POP_E"                    ,	5,	1,	1248,	"R/W",	0,	0,	0ull,	0ull},
+	{"OC_OVF_E"                    ,	6,	1,	1248,	"R/W",	0,	0,	0ull,	0ull},
+	{"EC_OVF_E"                    ,	7,	1,	1248,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1248,	"RAZ",	1,	1,	0,	0},
+	{"PP_PSH_F"                    ,	0,	1,	1249,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ER_PSH_F"                    ,	1,	1,	1249,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OR_PSH_F"                    ,	2,	1,	1249,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CF_PSH_F"                    ,	3,	1,	1249,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WB_PSH_F"                    ,	4,	1,	1249,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WB_POP_E"                    ,	5,	1,	1249,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OC_OVF_E"                    ,	6,	1,	1249,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EC_OVF_E"                    ,	7,	1,	1249,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1249,	"RAZ",	1,	1,	0,	0},
+	{"L2C_ADDR_MSB"                ,	0,	8,	1250,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_8"                ,	8,	1,	1250,	"RAZ",	1,	1,	0,	0},
+	{"INV_REG_A2"                  ,	9,	1,	1250,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DESC_EMOD"               ,	10,	2,	1250,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BUFF_EMOD"               ,	12,	2,	1250,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2C_STT"                     ,	14,	1,	1250,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_0PAG"                    ,	15,	1,	1250,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BC"                      ,	16,	1,	1250,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DC"                      ,	17,	1,	1250,	"R/W",	0,	0,	1ull,	1ull},
+	{"REG_NB"                      ,	18,	1,	1250,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	1250,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1251,	"RAZ",	1,	1,	0,	0},
+	{"TO_VAL"                      ,	8,	24,	1251,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1251,	"RAZ",	1,	1,	0,	0},
+	{"WM"                          ,	0,	5,	1252,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_5_63"               ,	5,	59,	1252,	"RAZ",	1,	1,	0,	0},
+	{"ATE_RESET"                   ,	0,	1,	1253,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_EN"                     ,	1,	1,	1253,	"R/W",	0,	0,	0ull,	0ull},
+	{"UPHY_BIST"                   ,	2,	1,	1253,	"R/W",	0,	0,	0ull,	0ull},
+	{"VTEST_EN"                    ,	3,	1,	1253,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIDDQ"                       ,	4,	1,	1253,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBIST"                      ,	5,	1,	1253,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSBIST"                      ,	6,	1,	1253,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSBIST"                      ,	7,	1,	1253,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_ERR"                    ,	8,	1,	1253,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST_DONE"                   ,	9,	1,	1253,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1253,	"RAZ",	1,	1,	0,	0},
+	{"TDATA_IN"                    ,	0,	8,	1254,	"R/W",	0,	0,	0ull,	0ull},
+	{"TADDR_IN"                    ,	8,	4,	1254,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_SEL"                   ,	12,	1,	1254,	"R/W",	0,	0,	1ull,	0ull},
+	{"TCLK"                        ,	13,	1,	1254,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOP_EN"                     ,	14,	1,	1254,	"R/W",	0,	0,	0ull,	0ull},
+	{"COMPDISTUNE"                 ,	15,	3,	1254,	"R/W",	0,	0,	4ull,	4ull},
+	{"SQRXTUNE"                    ,	18,	3,	1254,	"R/W",	0,	0,	4ull,	4ull},
+	{"TXFSLSTUNE"                  ,	21,	4,	1254,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPREEMPHASISTUNE"           ,	25,	1,	1254,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXRISETUNE"                  ,	26,	1,	1254,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXVREFTUNE"                  ,	27,	4,	1254,	"R/W",	0,	0,	5ull,	15ull},
+	{"TXHSVXTUNE"                  ,	31,	2,	1254,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORTRESET"                   ,	33,	1,	1254,	"R/W",	0,	0,	0ull,	0ull},
+	{"VBUSVLDEXT"                  ,	34,	1,	1254,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPPULLDOWN"                  ,	35,	1,	1254,	"R/W",	0,	0,	1ull,	1ull},
+	{"DMPULLDOWN"                  ,	36,	1,	1254,	"R/W",	0,	0,	1ull,	1ull},
+	{"TXBISTSTUFFEN"               ,	37,	1,	1254,	"R/W",	0,	0,	1ull,	1ull},
+	{"TXBISTSTUFFENH"              ,	38,	1,	1254,	"R/W",	0,	0,	1ull,	1ull},
+	{"TDATA_OUT"                   ,	39,	4,	1254,	"RO",	1,	1,	0,	0},
+	{"RESERVED_43_63"              ,	43,	21,	1254,	"RAZ",	1,	1,	0,	0},
+	{"ZIP_CTL"                     ,	0,	4,	1255,	"RO",	1,	0,	0,	0ull},
+	{"ZIP_CORE"                    ,	4,	53,	1255,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_57_63"              ,	57,	7,	1255,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	1256,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	33,	13,	1256,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	46,	3,	1256,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	49,	9,	1256,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	1256,	"RAZ",	1,	1,	0,	0},
+	{"RESET"                       ,	0,	1,	1257,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FORCECLK"                    ,	1,	1,	1257,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1257,	"RAZ",	1,	1,	0,	0},
+	{"DISABLED"                    ,	0,	1,	1258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	1258,	"RAZ",	1,	1,	0,	0},
+	{"CTXSIZE"                     ,	8,	12,	1258,	"RO",	0,	0,	1536ull,	1536ull},
+	{"ONFSIZE"                     ,	20,	12,	1258,	"RO",	0,	0,	512ull,	512ull},
+	{"DEPTH"                       ,	32,	16,	1258,	"RO",	0,	0,	31744ull,	31744ull},
+	{"SYNCFLUSH_CAPABLE"           ,	48,	1,	1258,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_49_55"              ,	49,	7,	1258,	"RAZ",	1,	1,	0,	0},
+	{"NEXEC"                       ,	56,	8,	1258,	"RO",	0,	0,	1ull,	1ull},
+	{"ASSERTS"                     ,	0,	17,	1259,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	1259,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1260,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1260,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1261,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1261,	"RAZ",	1,	1,	0,	0},
+	{"MAX_INFL"                    ,	0,	4,	1262,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	1262,	"RAZ",	1,	1,	0,	0},
+	{NULL,0,0,0,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn68xxp1[] = {
+	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
+	{"cvmx_agl_gmx_bad_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	0,	14,	0},
+	{"cvmx_agl_gmx_bist"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1,	2,	14},
+	{"cvmx_agl_gmx_prt#_cfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2,	13,	16},
+	{"cvmx_agl_gmx_rx#_adr_cam0"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	3,	1,	29},
+	{"cvmx_agl_gmx_rx#_adr_cam1"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	4,	1,	30},
+	{"cvmx_agl_gmx_rx#_adr_cam2"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5,	1,	31},
+	{"cvmx_agl_gmx_rx#_adr_cam3"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	6,	1,	32},
+	{"cvmx_agl_gmx_rx#_adr_cam4"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7,	1,	33},
+	{"cvmx_agl_gmx_rx#_adr_cam5"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8,	1,	34},
+	{"cvmx_agl_gmx_rx#_adr_cam_en" ,	CVMX_CSR_DB_TYPE_RSL,	64,	9,	2,	35},
+	{"cvmx_agl_gmx_rx#_adr_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	10,	4,	37},
+	{"cvmx_agl_gmx_rx#_decision"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	11,	2,	41},
+	{"cvmx_agl_gmx_rx#_frm_chk"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	12,	11,	43},
+	{"cvmx_agl_gmx_rx#_frm_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	13,	14,	54},
+	{"cvmx_agl_gmx_rx#_frm_max"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	14,	2,	68},
+	{"cvmx_agl_gmx_rx#_frm_min"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	15,	2,	70},
+	{"cvmx_agl_gmx_rx#_ifg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	16,	2,	72},
+	{"cvmx_agl_gmx_rx#_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	17,	21,	74},
+	{"cvmx_agl_gmx_rx#_int_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	18,	21,	95},
+	{"cvmx_agl_gmx_rx#_jabber"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	19,	2,	116},
+	{"cvmx_agl_gmx_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	20,	2,	118},
+	{"cvmx_agl_gmx_rx#_rx_inbnd"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	21,	4,	120},
+	{"cvmx_agl_gmx_rx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	22,	2,	124},
+	{"cvmx_agl_gmx_rx#_stats_octs" ,	CVMX_CSR_DB_TYPE_RSL,	64,	23,	2,	126},
+	{"cvmx_agl_gmx_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	24,	2,	128},
+	{"cvmx_agl_gmx_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	25,	2,	130},
+	{"cvmx_agl_gmx_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	26,	2,	132},
+	{"cvmx_agl_gmx_rx#_stats_pkts" ,	CVMX_CSR_DB_TYPE_RSL,	64,	27,	2,	134},
+	{"cvmx_agl_gmx_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	28,	2,	136},
+	{"cvmx_agl_gmx_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	29,	2,	138},
+	{"cvmx_agl_gmx_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	30,	2,	140},
+	{"cvmx_agl_gmx_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	31,	2,	142},
+	{"cvmx_agl_gmx_rx#_udd_skp"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	32,	4,	144},
+	{"cvmx_agl_gmx_rx_bp_drop#"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	33,	2,	148},
+	{"cvmx_agl_gmx_rx_bp_off#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	34,	2,	150},
+	{"cvmx_agl_gmx_rx_bp_on#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	35,	2,	152},
+	{"cvmx_agl_gmx_rx_prt_info"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	36,	4,	154},
+	{"cvmx_agl_gmx_rx_tx_status"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	37,	4,	158},
+	{"cvmx_agl_gmx_smac#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	38,	2,	162},
+	{"cvmx_agl_gmx_stat_bp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	39,	3,	164},
+	{"cvmx_agl_gmx_tx#_append"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	40,	5,	167},
+	{"cvmx_agl_gmx_tx#_clk"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	41,	2,	172},
+	{"cvmx_agl_gmx_tx#_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	42,	3,	174},
+	{"cvmx_agl_gmx_tx#_min_pkt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	43,	2,	177},
+	{"cvmx_agl_gmx_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	44,	2,	179},
+	{"cvmx_agl_gmx_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	45,	2,	181},
+	{"cvmx_agl_gmx_tx#_pause_togo" ,	CVMX_CSR_DB_TYPE_RSL,	64,	46,	2,	183},
+	{"cvmx_agl_gmx_tx#_pause_zero" ,	CVMX_CSR_DB_TYPE_RSL,	64,	47,	2,	185},
+	{"cvmx_agl_gmx_tx#_soft_pause" ,	CVMX_CSR_DB_TYPE_RSL,	64,	48,	2,	187},
+	{"cvmx_agl_gmx_tx#_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	49,	2,	189},
+	{"cvmx_agl_gmx_tx#_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	50,	2,	191},
+	{"cvmx_agl_gmx_tx#_stat2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	51,	2,	193},
+	{"cvmx_agl_gmx_tx#_stat3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	52,	2,	195},
+	{"cvmx_agl_gmx_tx#_stat4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	53,	2,	197},
+	{"cvmx_agl_gmx_tx#_stat5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	54,	2,	199},
+	{"cvmx_agl_gmx_tx#_stat6"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	55,	2,	201},
+	{"cvmx_agl_gmx_tx#_stat7"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	56,	2,	203},
+	{"cvmx_agl_gmx_tx#_stat8"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	57,	2,	205},
+	{"cvmx_agl_gmx_tx#_stat9"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	58,	2,	207},
+	{"cvmx_agl_gmx_tx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	59,	2,	209},
+	{"cvmx_agl_gmx_tx#_thresh"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	60,	2,	211},
+	{"cvmx_agl_gmx_tx_bp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	61,	2,	213},
+	{"cvmx_agl_gmx_tx_col_attempt" ,	CVMX_CSR_DB_TYPE_RSL,	64,	62,	2,	215},
+	{"cvmx_agl_gmx_tx_ifg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	63,	3,	217},
+	{"cvmx_agl_gmx_tx_int_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	64,	12,	220},
+	{"cvmx_agl_gmx_tx_int_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	65,	12,	232},
+	{"cvmx_agl_gmx_tx_jam"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	66,	2,	244},
+	{"cvmx_agl_gmx_tx_lfsr"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	67,	2,	246},
+	{"cvmx_agl_gmx_tx_ovr_bp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	68,	6,	248},
+	{"cvmx_agl_gmx_tx_pause_pkt_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	69,	2,	254},
+	{"cvmx_agl_gmx_tx_pause_pkt_type",	CVMX_CSR_DB_TYPE_RSL,	64,	70,	2,	256},
+	{"cvmx_agl_prt#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	71,	23,	258},
+	{"cvmx_ciu2_ack_io#_int"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	72,	2,	281},
+	{"cvmx_ciu2_ack_pp#_ip2"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	74,	2,	283},
+	{"cvmx_ciu2_ack_pp#_ip3"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	106,	2,	285},
+	{"cvmx_ciu2_ack_pp#_ip4"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	138,	2,	287},
+	{"cvmx_ciu2_en_io#_int_gpio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	170,	2,	289},
+	{"cvmx_ciu2_en_io#_int_gpio_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	172,	2,	291},
+	{"cvmx_ciu2_en_io#_int_gpio_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	174,	2,	293},
+	{"cvmx_ciu2_en_io#_int_io"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	176,	9,	295},
+	{"cvmx_ciu2_en_io#_int_io_w1c" ,	CVMX_CSR_DB_TYPE_NCB,	64,	178,	9,	304},
+	{"cvmx_ciu2_en_io#_int_io_w1s" ,	CVMX_CSR_DB_TYPE_NCB,	64,	180,	9,	313},
+	{"cvmx_ciu2_en_io#_int_mbox"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	182,	2,	322},
+	{"cvmx_ciu2_en_io#_int_mbox_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	184,	2,	324},
+	{"cvmx_ciu2_en_io#_int_mbox_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	186,	2,	326},
+	{"cvmx_ciu2_en_io#_int_mem"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	188,	2,	328},
+	{"cvmx_ciu2_en_io#_int_mem_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	190,	2,	330},
+	{"cvmx_ciu2_en_io#_int_mem_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	192,	2,	332},
+	{"cvmx_ciu2_en_io#_int_mio"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	194,	21,	334},
+	{"cvmx_ciu2_en_io#_int_mio_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	196,	21,	355},
+	{"cvmx_ciu2_en_io#_int_mio_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	198,	21,	376},
+	{"cvmx_ciu2_en_io#_int_pkt"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	200,	10,	397},
+	{"cvmx_ciu2_en_io#_int_pkt_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	202,	10,	407},
+	{"cvmx_ciu2_en_io#_int_pkt_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	204,	10,	417},
+	{"cvmx_ciu2_en_io#_int_rml"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	206,	24,	427},
+	{"cvmx_ciu2_en_io#_int_rml_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	208,	24,	451},
+	{"cvmx_ciu2_en_io#_int_rml_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	210,	24,	475},
+	{"cvmx_ciu2_en_io#_int_wdog"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	212,	2,	499},
+	{"cvmx_ciu2_en_io#_int_wdog_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	214,	2,	501},
+	{"cvmx_ciu2_en_io#_int_wdog_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	216,	2,	503},
+	{"cvmx_ciu2_en_io#_int_wrkq"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	218,	1,	505},
+	{"cvmx_ciu2_en_io#_int_wrkq_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	220,	1,	506},
+	{"cvmx_ciu2_en_io#_int_wrkq_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	222,	1,	507},
+	{"cvmx_ciu2_en_pp#_ip2_gpio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	224,	2,	508},
+	{"cvmx_ciu2_en_pp#_ip2_gpio_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	256,	2,	510},
+	{"cvmx_ciu2_en_pp#_ip2_gpio_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	288,	2,	512},
+	{"cvmx_ciu2_en_pp#_ip2_io"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	320,	9,	514},
+	{"cvmx_ciu2_en_pp#_ip2_io_w1c" ,	CVMX_CSR_DB_TYPE_NCB,	64,	352,	9,	523},
+	{"cvmx_ciu2_en_pp#_ip2_io_w1s" ,	CVMX_CSR_DB_TYPE_NCB,	64,	384,	9,	532},
+	{"cvmx_ciu2_en_pp#_ip2_mbox"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	416,	2,	541},
+	{"cvmx_ciu2_en_pp#_ip2_mbox_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	448,	2,	543},
+	{"cvmx_ciu2_en_pp#_ip2_mbox_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	480,	2,	545},
+	{"cvmx_ciu2_en_pp#_ip2_mem"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	512,	2,	547},
+	{"cvmx_ciu2_en_pp#_ip2_mem_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	544,	2,	549},
+	{"cvmx_ciu2_en_pp#_ip2_mem_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	576,	2,	551},
+	{"cvmx_ciu2_en_pp#_ip2_mio"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	608,	21,	553},
+	{"cvmx_ciu2_en_pp#_ip2_mio_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	640,	21,	574},
+	{"cvmx_ciu2_en_pp#_ip2_mio_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	672,	21,	595},
+	{"cvmx_ciu2_en_pp#_ip2_pkt"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	704,	10,	616},
+	{"cvmx_ciu2_en_pp#_ip2_pkt_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	736,	10,	626},
+	{"cvmx_ciu2_en_pp#_ip2_pkt_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	768,	10,	636},
+	{"cvmx_ciu2_en_pp#_ip2_rml"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	800,	24,	646},
+	{"cvmx_ciu2_en_pp#_ip2_rml_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	832,	24,	670},
+	{"cvmx_ciu2_en_pp#_ip2_rml_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	864,	24,	694},
+	{"cvmx_ciu2_en_pp#_ip2_wdog"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	896,	2,	718},
+	{"cvmx_ciu2_en_pp#_ip2_wdog_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	928,	2,	720},
+	{"cvmx_ciu2_en_pp#_ip2_wdog_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	960,	2,	722},
+	{"cvmx_ciu2_en_pp#_ip2_wrkq"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	992,	1,	724},
+	{"cvmx_ciu2_en_pp#_ip2_wrkq_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1024,	1,	725},
+	{"cvmx_ciu2_en_pp#_ip2_wrkq_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	1056,	1,	726},
+	{"cvmx_ciu2_en_pp#_ip3_gpio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1088,	2,	727},
+	{"cvmx_ciu2_en_pp#_ip3_gpio_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1120,	2,	729},
+	{"cvmx_ciu2_en_pp#_ip3_gpio_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	1152,	2,	731},
+	{"cvmx_ciu2_en_pp#_ip3_io"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1184,	9,	733},
+	{"cvmx_ciu2_en_pp#_ip3_io_w1c" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1216,	9,	742},
+	{"cvmx_ciu2_en_pp#_ip3_io_w1s" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1248,	9,	751},
+	{"cvmx_ciu2_en_pp#_ip3_mbox"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1280,	2,	760},
+	{"cvmx_ciu2_en_pp#_ip3_mbox_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1312,	2,	762},
+	{"cvmx_ciu2_en_pp#_ip3_mbox_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	1344,	2,	764},
+	{"cvmx_ciu2_en_pp#_ip3_mem"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1376,	2,	766},
+	{"cvmx_ciu2_en_pp#_ip3_mem_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1408,	2,	768},
+	{"cvmx_ciu2_en_pp#_ip3_mem_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	1440,	2,	770},
+	{"cvmx_ciu2_en_pp#_ip3_mio"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1472,	21,	772},
+	{"cvmx_ciu2_en_pp#_ip3_mio_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1504,	21,	793},
+	{"cvmx_ciu2_en_pp#_ip3_mio_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	1536,	21,	814},
+	{"cvmx_ciu2_en_pp#_ip3_pkt"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1568,	10,	835},
+	{"cvmx_ciu2_en_pp#_ip3_pkt_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1600,	10,	845},
+	{"cvmx_ciu2_en_pp#_ip3_pkt_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	1632,	10,	855},
+	{"cvmx_ciu2_en_pp#_ip3_rml"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1664,	24,	865},
+	{"cvmx_ciu2_en_pp#_ip3_rml_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1696,	24,	889},
+	{"cvmx_ciu2_en_pp#_ip3_rml_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	1728,	24,	913},
+	{"cvmx_ciu2_en_pp#_ip3_wdog"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1760,	2,	937},
+	{"cvmx_ciu2_en_pp#_ip3_wdog_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1792,	2,	939},
+	{"cvmx_ciu2_en_pp#_ip3_wdog_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	1824,	2,	941},
+	{"cvmx_ciu2_en_pp#_ip3_wrkq"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1856,	1,	943},
+	{"cvmx_ciu2_en_pp#_ip3_wrkq_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1888,	1,	944},
+	{"cvmx_ciu2_en_pp#_ip3_wrkq_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	1920,	1,	945},
+	{"cvmx_ciu2_en_pp#_ip4_gpio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1952,	2,	946},
+	{"cvmx_ciu2_en_pp#_ip4_gpio_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1984,	2,	948},
+	{"cvmx_ciu2_en_pp#_ip4_gpio_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	2016,	2,	950},
+	{"cvmx_ciu2_en_pp#_ip4_io"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	2048,	9,	952},
+	{"cvmx_ciu2_en_pp#_ip4_io_w1c" ,	CVMX_CSR_DB_TYPE_NCB,	64,	2080,	9,	961},
+	{"cvmx_ciu2_en_pp#_ip4_io_w1s" ,	CVMX_CSR_DB_TYPE_NCB,	64,	2112,	9,	970},
+	{"cvmx_ciu2_en_pp#_ip4_mbox"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2144,	2,	979},
+	{"cvmx_ciu2_en_pp#_ip4_mbox_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	2176,	2,	981},
+	{"cvmx_ciu2_en_pp#_ip4_mbox_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	2208,	2,	983},
+	{"cvmx_ciu2_en_pp#_ip4_mem"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2240,	2,	985},
+	{"cvmx_ciu2_en_pp#_ip4_mem_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	2272,	2,	987},
+	{"cvmx_ciu2_en_pp#_ip4_mem_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	2304,	2,	989},
+	{"cvmx_ciu2_en_pp#_ip4_mio"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2336,	21,	991},
+	{"cvmx_ciu2_en_pp#_ip4_mio_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	2368,	21,	1012},
+	{"cvmx_ciu2_en_pp#_ip4_mio_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	2400,	21,	1033},
+	{"cvmx_ciu2_en_pp#_ip4_pkt"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2432,	10,	1054},
+	{"cvmx_ciu2_en_pp#_ip4_pkt_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	2464,	10,	1064},
+	{"cvmx_ciu2_en_pp#_ip4_pkt_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	2496,	10,	1074},
+	{"cvmx_ciu2_en_pp#_ip4_rml"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2528,	24,	1084},
+	{"cvmx_ciu2_en_pp#_ip4_rml_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	2560,	24,	1108},
+	{"cvmx_ciu2_en_pp#_ip4_rml_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	2592,	24,	1132},
+	{"cvmx_ciu2_en_pp#_ip4_wdog"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2624,	2,	1156},
+	{"cvmx_ciu2_en_pp#_ip4_wdog_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	2656,	2,	1158},
+	{"cvmx_ciu2_en_pp#_ip4_wdog_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	2688,	2,	1160},
+	{"cvmx_ciu2_en_pp#_ip4_wrkq"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2720,	1,	1162},
+	{"cvmx_ciu2_en_pp#_ip4_wrkq_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	2752,	1,	1163},
+	{"cvmx_ciu2_en_pp#_ip4_wrkq_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	2784,	1,	1164},
+	{"cvmx_ciu2_intr_ciu_ready"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2816,	2,	1165},
+	{"cvmx_ciu2_intr_ram_ecc_ctl"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	2817,	3,	1167},
+	{"cvmx_ciu2_intr_ram_ecc_st"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2818,	7,	1170},
+	{"cvmx_ciu2_intr_slowdown"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	2819,	2,	1177},
+	{"cvmx_ciu2_msi_rcv#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2820,	2,	1179},
+	{"cvmx_ciu2_msi_sel#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	3076,	6,	1181},
+	{"cvmx_ciu2_msired_pp#_ip2"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3332,	6,	1187},
+	{"cvmx_ciu2_msired_pp#_ip3"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3364,	6,	1193},
+	{"cvmx_ciu2_msired_pp#_ip4"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3396,	6,	1199},
+	{"cvmx_ciu2_raw_io#_int_gpio"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3428,	2,	1205},
+	{"cvmx_ciu2_raw_io#_int_io"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3430,	9,	1207},
+	{"cvmx_ciu2_raw_io#_int_mem"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3432,	2,	1216},
+	{"cvmx_ciu2_raw_io#_int_mio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3434,	21,	1218},
+	{"cvmx_ciu2_raw_io#_int_pkt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3436,	10,	1239},
+	{"cvmx_ciu2_raw_io#_int_rml"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3438,	24,	1249},
+	{"cvmx_ciu2_raw_io#_int_wdog"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3440,	2,	1273},
+	{"cvmx_ciu2_raw_io#_int_wrkq"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3442,	1,	1275},
+	{"cvmx_ciu2_raw_pp#_ip2_gpio"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3444,	2,	1276},
+	{"cvmx_ciu2_raw_pp#_ip2_io"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3476,	9,	1278},
+	{"cvmx_ciu2_raw_pp#_ip2_mem"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3508,	2,	1287},
+	{"cvmx_ciu2_raw_pp#_ip2_mio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3540,	21,	1289},
+	{"cvmx_ciu2_raw_pp#_ip2_pkt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3572,	10,	1310},
+	{"cvmx_ciu2_raw_pp#_ip2_rml"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3604,	24,	1320},
+	{"cvmx_ciu2_raw_pp#_ip2_wdog"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3636,	2,	1344},
+	{"cvmx_ciu2_raw_pp#_ip2_wrkq"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3668,	1,	1346},
+	{"cvmx_ciu2_raw_pp#_ip3_gpio"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3700,	2,	1347},
+	{"cvmx_ciu2_raw_pp#_ip3_io"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3732,	9,	1349},
+	{"cvmx_ciu2_raw_pp#_ip3_mem"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3764,	2,	1358},
+	{"cvmx_ciu2_raw_pp#_ip3_mio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3796,	21,	1360},
+	{"cvmx_ciu2_raw_pp#_ip3_pkt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3828,	10,	1381},
+	{"cvmx_ciu2_raw_pp#_ip3_rml"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3860,	24,	1391},
+	{"cvmx_ciu2_raw_pp#_ip3_wdog"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3892,	2,	1415},
+	{"cvmx_ciu2_raw_pp#_ip3_wrkq"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3924,	1,	1417},
+	{"cvmx_ciu2_raw_pp#_ip4_gpio"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3956,	2,	1418},
+	{"cvmx_ciu2_raw_pp#_ip4_io"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3988,	9,	1420},
+	{"cvmx_ciu2_raw_pp#_ip4_mem"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4020,	2,	1429},
+	{"cvmx_ciu2_raw_pp#_ip4_mio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4052,	21,	1431},
+	{"cvmx_ciu2_raw_pp#_ip4_pkt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4084,	10,	1452},
+	{"cvmx_ciu2_raw_pp#_ip4_rml"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4116,	24,	1462},
+	{"cvmx_ciu2_raw_pp#_ip4_wdog"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4148,	2,	1486},
+	{"cvmx_ciu2_raw_pp#_ip4_wrkq"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4180,	1,	1488},
+	{"cvmx_ciu2_src_io#_int_gpio"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4212,	2,	1489},
+	{"cvmx_ciu2_src_io#_int_io"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	4214,	9,	1491},
+	{"cvmx_ciu2_src_io#_int_mbox"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4216,	2,	1500},
+	{"cvmx_ciu2_src_io#_int_mem"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4218,	2,	1502},
+	{"cvmx_ciu2_src_io#_int_mio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4220,	21,	1504},
+	{"cvmx_ciu2_src_io#_int_pkt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4222,	10,	1525},
+	{"cvmx_ciu2_src_io#_int_rml"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4224,	24,	1535},
+	{"cvmx_ciu2_src_io#_int_wdog"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4226,	2,	1559},
+	{"cvmx_ciu2_src_io#_int_wrkq"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4228,	1,	1561},
+	{"cvmx_ciu2_src_pp#_ip2_gpio"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4230,	2,	1562},
+	{"cvmx_ciu2_src_pp#_ip2_io"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	4262,	9,	1564},
+	{"cvmx_ciu2_src_pp#_ip2_mbox"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4294,	2,	1573},
+	{"cvmx_ciu2_src_pp#_ip2_mem"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4326,	2,	1575},
+	{"cvmx_ciu2_src_pp#_ip2_mio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4358,	21,	1577},
+	{"cvmx_ciu2_src_pp#_ip2_pkt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4390,	10,	1598},
+	{"cvmx_ciu2_src_pp#_ip2_rml"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4422,	24,	1608},
+	{"cvmx_ciu2_src_pp#_ip2_wdog"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4454,	2,	1632},
+	{"cvmx_ciu2_src_pp#_ip2_wrkq"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4486,	1,	1634},
+	{"cvmx_ciu2_src_pp#_ip3_gpio"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4518,	2,	1635},
+	{"cvmx_ciu2_src_pp#_ip3_io"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	4550,	9,	1637},
+	{"cvmx_ciu2_src_pp#_ip3_mbox"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4582,	2,	1646},
+	{"cvmx_ciu2_src_pp#_ip3_mem"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4614,	2,	1648},
+	{"cvmx_ciu2_src_pp#_ip3_mio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4646,	21,	1650},
+	{"cvmx_ciu2_src_pp#_ip3_pkt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4678,	10,	1671},
+	{"cvmx_ciu2_src_pp#_ip3_rml"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4710,	24,	1681},
+	{"cvmx_ciu2_src_pp#_ip3_wdog"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4742,	2,	1705},
+	{"cvmx_ciu2_src_pp#_ip3_wrkq"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4774,	1,	1707},
+	{"cvmx_ciu2_src_pp#_ip4_gpio"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4806,	2,	1708},
+	{"cvmx_ciu2_src_pp#_ip4_io"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	4838,	9,	1710},
+	{"cvmx_ciu2_src_pp#_ip4_mbox"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4870,	2,	1719},
+	{"cvmx_ciu2_src_pp#_ip4_mem"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4902,	2,	1721},
+	{"cvmx_ciu2_src_pp#_ip4_mio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4934,	21,	1723},
+	{"cvmx_ciu2_src_pp#_ip4_pkt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4966,	10,	1744},
+	{"cvmx_ciu2_src_pp#_ip4_rml"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4998,	24,	1754},
+	{"cvmx_ciu2_src_pp#_ip4_wdog"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	5030,	2,	1778},
+	{"cvmx_ciu2_src_pp#_ip4_wrkq"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	5062,	1,	1780},
+	{"cvmx_ciu2_sum_io#_int"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5094,	10,	1781},
+	{"cvmx_ciu2_sum_pp#_ip2"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5096,	10,	1791},
+	{"cvmx_ciu2_sum_pp#_ip3"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5128,	10,	1801},
+	{"cvmx_ciu2_sum_pp#_ip4"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5160,	10,	1811},
+	{"cvmx_ciu_bist"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5192,	2,	1821},
+	{"cvmx_ciu_dint"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5193,	2,	1823},
+	{"cvmx_ciu_fuse"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5194,	2,	1825},
+	{"cvmx_ciu_gstop"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	5195,	2,	1827},
+	{"cvmx_ciu_int_dbg_sel"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5196,	6,	1829},
+	{"cvmx_ciu_mbox_clr#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	5197,	2,	1835},
+	{"cvmx_ciu_mbox_set#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	5229,	2,	1837},
+	{"cvmx_ciu_nmi"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	5261,	2,	1839},
+	{"cvmx_ciu_pci_inta"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5262,	2,	1841},
+	{"cvmx_ciu_pp_bist_stat"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5263,	2,	1843},
+	{"cvmx_ciu_pp_dbg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5264,	2,	1845},
+	{"cvmx_ciu_pp_poke#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5265,	1,	1847},
+	{"cvmx_ciu_pp_rst"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5297,	3,	1848},
+	{"cvmx_ciu_qlm0"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5298,	8,	1851},
+	{"cvmx_ciu_qlm1"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5299,	13,	1859},
+	{"cvmx_ciu_qlm2"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5300,	13,	1872},
+	{"cvmx_ciu_qlm3"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5301,	13,	1885},
+	{"cvmx_ciu_qlm4"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5302,	13,	1898},
+	{"cvmx_ciu_qlm_jtgc"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5303,	7,	1911},
+	{"cvmx_ciu_qlm_jtgd"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5304,	8,	1918},
+	{"cvmx_ciu_soft_bist"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	5305,	2,	1926},
+	{"cvmx_ciu_soft_prst"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	5306,	2,	1928},
+	{"cvmx_ciu_soft_prst1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	5307,	2,	1930},
+	{"cvmx_ciu_soft_rst"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5308,	2,	1932},
+	{"cvmx_ciu_tim#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5309,	3,	1934},
+	{"cvmx_ciu_wdog#"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	5313,	7,	1937},
+	{"cvmx_dfa_bist0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	5345,	16,	1944},
+	{"cvmx_dfa_bist1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	5346,	20,	1960},
+	{"cvmx_dfa_config"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	5347,	7,	1980},
+	{"cvmx_dfa_control"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5348,	7,	1987},
+	{"cvmx_dfa_dbell"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	5349,	2,	1994},
+	{"cvmx_dfa_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	5350,	1,	1996},
+	{"cvmx_dfa_debug1"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	5351,	1,	1997},
+	{"cvmx_dfa_debug2"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	5352,	1,	1998},
+	{"cvmx_dfa_debug3"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	5353,	1,	1999},
+	{"cvmx_dfa_difctl"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5354,	5,	2000},
+	{"cvmx_dfa_difrdptr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5355,	3,	2005},
+	{"cvmx_dfa_dtcfadr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5356,	6,	2008},
+	{"cvmx_dfa_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	5357,	12,	2014},
+	{"cvmx_dfa_intmsk"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	5358,	11,	2026},
+	{"cvmx_dfa_memhidat"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5359,	1,	2037},
+	{"cvmx_dfa_pfc0_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5360,	1,	2038},
+	{"cvmx_dfa_pfc0_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5361,	5,	2039},
+	{"cvmx_dfa_pfc1_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5362,	1,	2044},
+	{"cvmx_dfa_pfc1_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5363,	5,	2045},
+	{"cvmx_dfa_pfc2_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5364,	1,	2050},
+	{"cvmx_dfa_pfc2_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5365,	5,	2051},
+	{"cvmx_dfa_pfc3_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5366,	1,	2056},
+	{"cvmx_dfa_pfc3_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5367,	5,	2057},
+	{"cvmx_dfa_pfc_gctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5368,	18,	2062},
+	{"cvmx_dpi_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5369,	2,	2080},
+	{"cvmx_dpi_ctl"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	5370,	3,	2082},
+	{"cvmx_dpi_dma#_counts"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5371,	3,	2085},
+	{"cvmx_dpi_dma#_dbell"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	5379,	2,	2088},
+	{"cvmx_dpi_dma#_err_rsp_status",	CVMX_CSR_DB_TYPE_NCB,	64,	5387,	2,	2090},
+	{"cvmx_dpi_dma#_ibuff_saddr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	5395,	6,	2092},
+	{"cvmx_dpi_dma#_iflight"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5403,	2,	2098},
+	{"cvmx_dpi_dma#_naddr"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	5411,	2,	2100},
+	{"cvmx_dpi_dma#_reqbnk0"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5419,	1,	2102},
+	{"cvmx_dpi_dma#_reqbnk1"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5427,	1,	2103},
+	{"cvmx_dpi_dma_control"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5435,	19,	2104},
+	{"cvmx_dpi_dma_eng#_en"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5436,	2,	2123},
+	{"cvmx_dpi_eng#_buf"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5442,	5,	2125},
+	{"cvmx_dpi_info_reg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5448,	5,	2130},
+	{"cvmx_dpi_int_en"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5449,	15,	2135},
+	{"cvmx_dpi_int_reg"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5450,	15,	2150},
+	{"cvmx_dpi_pint_info"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	5451,	4,	2165},
+	{"cvmx_dpi_pkt_err_rsp"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5452,	2,	2169},
+	{"cvmx_dpi_req_err_rsp"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5453,	2,	2171},
+	{"cvmx_dpi_req_err_rsp_en"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	5454,	2,	2173},
+	{"cvmx_dpi_req_err_rst"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5455,	2,	2175},
+	{"cvmx_dpi_req_err_rst_en"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	5456,	2,	2177},
+	{"cvmx_dpi_req_err_skip_comp"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	5457,	4,	2179},
+	{"cvmx_dpi_req_gbl_en"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	5458,	2,	2183},
+	{"cvmx_dpi_sli_prt#_cfg"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5459,	14,	2185},
+	{"cvmx_dpi_sli_prt#_err"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5461,	2,	2199},
+	{"cvmx_dpi_sli_prt#_err_info"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	5463,	6,	2201},
+	{"cvmx_fpa_addr_range_error"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5465,	3,	2207},
+	{"cvmx_fpa_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5466,	6,	2210},
+	{"cvmx_fpa_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5467,	10,	2216},
+	{"cvmx_fpa_fpf#_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5468,	3,	2226},
+	{"cvmx_fpa_fpf#_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5475,	2,	2229},
+	{"cvmx_fpa_fpf0_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5482,	3,	2231},
+	{"cvmx_fpa_fpf0_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5483,	2,	2234},
+	{"cvmx_fpa_fpf8_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5484,	3,	2236},
+	{"cvmx_fpa_fpf8_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5485,	2,	2239},
+	{"cvmx_fpa_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5486,	51,	2241},
+	{"cvmx_fpa_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5487,	51,	2292},
+	{"cvmx_fpa_packet_threshold"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5488,	2,	2343},
+	{"cvmx_fpa_pool#_end_addr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5489,	2,	2345},
+	{"cvmx_fpa_pool#_start_addr"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5498,	2,	2347},
+	{"cvmx_fpa_pool#_threshold"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5507,	2,	2349},
+	{"cvmx_fpa_que#_available"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5516,	2,	2351},
+	{"cvmx_fpa_que#_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5525,	2,	2353},
+	{"cvmx_fpa_que8_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5533,	2,	2355},
+	{"cvmx_fpa_que_act"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5534,	3,	2357},
+	{"cvmx_fpa_que_exp"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5535,	3,	2360},
+	{"cvmx_fpa_wqe_threshold"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5536,	2,	2363},
+	{"cvmx_gmx#_bad_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5537,	7,	2365},
+	{"cvmx_gmx#_bist"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	5542,	2,	2372},
+	{"cvmx_gmx#_bpid_map#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5547,	6,	2374},
+	{"cvmx_gmx#_bpid_msk"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5627,	4,	2380},
+	{"cvmx_gmx#_clk_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5632,	2,	2384},
+	{"cvmx_gmx#_ebp_dis"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5637,	2,	2386},
+	{"cvmx_gmx#_ebp_msk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5642,	2,	2388},
+	{"cvmx_gmx#_hg2_control"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5647,	5,	2390},
+	{"cvmx_gmx#_inf_mode"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5652,	7,	2395},
+	{"cvmx_gmx#_nxa_adr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5657,	4,	2402},
+	{"cvmx_gmx#_pipe_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5662,	6,	2406},
+	{"cvmx_gmx#_prt#_cbfc_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5667,	8,	2412},
+	{"cvmx_gmx#_prt#_cfg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5672,	12,	2420},
+	{"cvmx_gmx#_rx#_adr_cam0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5692,	1,	2432},
+	{"cvmx_gmx#_rx#_adr_cam1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5712,	1,	2433},
+	{"cvmx_gmx#_rx#_adr_cam2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5732,	1,	2434},
+	{"cvmx_gmx#_rx#_adr_cam3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5752,	1,	2435},
+	{"cvmx_gmx#_rx#_adr_cam4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5772,	1,	2436},
+	{"cvmx_gmx#_rx#_adr_cam5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5792,	1,	2437},
+	{"cvmx_gmx#_rx#_adr_cam_en"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5812,	2,	2438},
+	{"cvmx_gmx#_rx#_adr_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5832,	4,	2440},
+	{"cvmx_gmx#_rx#_decision"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5852,	2,	2444},
+	{"cvmx_gmx#_rx#_frm_chk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5872,	9,	2446},
+	{"cvmx_gmx#_rx#_frm_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5892,	13,	2455},
+	{"cvmx_gmx#_rx#_ifg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5912,	2,	2468},
+	{"cvmx_gmx#_rx#_int_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5932,	27,	2470},
+	{"cvmx_gmx#_rx#_int_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5952,	27,	2497},
+	{"cvmx_gmx#_rx#_jabber"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5972,	2,	2524},
+	{"cvmx_gmx#_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	5992,	2,	2526},
+	{"cvmx_gmx#_rx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6012,	2,	2528},
+	{"cvmx_gmx#_rx#_stats_octs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6032,	2,	2530},
+	{"cvmx_gmx#_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	6052,	2,	2532},
+	{"cvmx_gmx#_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	6072,	2,	2534},
+	{"cvmx_gmx#_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	6092,	2,	2536},
+	{"cvmx_gmx#_rx#_stats_pkts"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6112,	2,	2538},
+	{"cvmx_gmx#_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	6132,	2,	2540},
+	{"cvmx_gmx#_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	6152,	2,	2542},
+	{"cvmx_gmx#_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	6172,	2,	2544},
+	{"cvmx_gmx#_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	6192,	2,	2546},
+	{"cvmx_gmx#_rx#_udd_skp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6212,	4,	2548},
+	{"cvmx_gmx#_rx_bp_drop#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6232,	2,	2552},
+	{"cvmx_gmx#_rx_bp_off#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6252,	2,	2554},
+	{"cvmx_gmx#_rx_bp_on#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6272,	2,	2556},
+	{"cvmx_gmx#_rx_hg2_status"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6292,	4,	2558},
+	{"cvmx_gmx#_rx_prt_info"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6297,	4,	2562},
+	{"cvmx_gmx#_rx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6302,	2,	2566},
+	{"cvmx_gmx#_rx_xaui_bad_col"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	6307,	5,	2568},
+	{"cvmx_gmx#_rx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6312,	2,	2573},
+	{"cvmx_gmx#_rxaui_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6317,	2,	2575},
+	{"cvmx_gmx#_smac#"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	6322,	2,	2577},
+	{"cvmx_gmx#_soft_bist"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6342,	3,	2579},
+	{"cvmx_gmx#_stat_bp"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6347,	3,	2582},
+	{"cvmx_gmx#_tx#_append"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6352,	5,	2585},
+	{"cvmx_gmx#_tx#_burst"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6372,	2,	2590},
+	{"cvmx_gmx#_tx#_cbfc_xoff"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6392,	2,	2592},
+	{"cvmx_gmx#_tx#_cbfc_xon"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6397,	2,	2594},
+	{"cvmx_gmx#_tx#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6402,	3,	2596},
+	{"cvmx_gmx#_tx#_min_pkt"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6422,	2,	2599},
+	{"cvmx_gmx#_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	6442,	2,	2601},
+	{"cvmx_gmx#_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	6462,	2,	2603},
+	{"cvmx_gmx#_tx#_pause_togo"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6482,	3,	2605},
+	{"cvmx_gmx#_tx#_pause_zero"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6502,	2,	2608},
+	{"cvmx_gmx#_tx#_pipe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6522,	6,	2610},
+	{"cvmx_gmx#_tx#_sgmii_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6542,	2,	2616},
+	{"cvmx_gmx#_tx#_slot"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6562,	2,	2618},
+	{"cvmx_gmx#_tx#_soft_pause"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6582,	2,	2620},
+	{"cvmx_gmx#_tx#_stat0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6602,	2,	2622},
+	{"cvmx_gmx#_tx#_stat1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6622,	2,	2624},
+	{"cvmx_gmx#_tx#_stat2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6642,	2,	2626},
+	{"cvmx_gmx#_tx#_stat3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6662,	2,	2628},
+	{"cvmx_gmx#_tx#_stat4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6682,	2,	2630},
+	{"cvmx_gmx#_tx#_stat5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6702,	2,	2632},
+	{"cvmx_gmx#_tx#_stat6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6722,	2,	2634},
+	{"cvmx_gmx#_tx#_stat7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6742,	2,	2636},
+	{"cvmx_gmx#_tx#_stat8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6762,	2,	2638},
+	{"cvmx_gmx#_tx#_stat9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6782,	2,	2640},
+	{"cvmx_gmx#_tx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6802,	2,	2642},
+	{"cvmx_gmx#_tx#_thresh"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6822,	2,	2644},
+	{"cvmx_gmx#_tx_bp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	6842,	2,	2646},
+	{"cvmx_gmx#_tx_col_attempt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6847,	2,	2648},
+	{"cvmx_gmx#_tx_corrupt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6852,	2,	2650},
+	{"cvmx_gmx#_tx_hg2_reg1"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6857,	2,	2652},
+	{"cvmx_gmx#_tx_hg2_reg2"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6862,	2,	2654},
+	{"cvmx_gmx#_tx_ifg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6867,	3,	2656},
+	{"cvmx_gmx#_tx_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6872,	10,	2659},
+	{"cvmx_gmx#_tx_int_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6877,	10,	2669},
+	{"cvmx_gmx#_tx_jam"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6882,	2,	2679},
+	{"cvmx_gmx#_tx_lfsr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6887,	2,	2681},
+	{"cvmx_gmx#_tx_ovr_bp"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6892,	6,	2683},
+	{"cvmx_gmx#_tx_pause_pkt_dmac" ,	CVMX_CSR_DB_TYPE_RSL,	64,	6897,	2,	2689},
+	{"cvmx_gmx#_tx_pause_pkt_type" ,	CVMX_CSR_DB_TYPE_RSL,	64,	6902,	2,	2691},
+	{"cvmx_gmx#_tx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6907,	2,	2693},
+	{"cvmx_gmx#_tx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6912,	9,	2695},
+	{"cvmx_gmx#_xaui_ext_loopback" ,	CVMX_CSR_DB_TYPE_RSL,	64,	6917,	3,	2704},
+	{"cvmx_gpio_bit_cfg#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6922,	10,	2707},
+	{"cvmx_gpio_clk_gen#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6938,	2,	2717},
+	{"cvmx_gpio_clk_qlm#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6942,	5,	2719},
+	{"cvmx_gpio_int_clr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	6944,	2,	2724},
+	{"cvmx_gpio_rx_dat"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6945,	2,	2726},
+	{"cvmx_gpio_tim_ctl"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	6946,	2,	2728},
+	{"cvmx_gpio_tx_clr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6947,	2,	2730},
+	{"cvmx_gpio_tx_set"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6948,	2,	2732},
+	{"cvmx_ilk_bist_sum"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6949,	42,	2734},
+	{"cvmx_ilk_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6950,	3,	2776},
+	{"cvmx_ilk_gbl_int"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6951,	6,	2779},
+	{"cvmx_ilk_gbl_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6952,	6,	2785},
+	{"cvmx_ilk_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6953,	14,	2791},
+	{"cvmx_ilk_lne_dbg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6954,	11,	2805},
+	{"cvmx_ilk_lne_sts_msg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6955,	8,	2816},
+	{"cvmx_ilk_rx#_cfg0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6956,	16,	2824},
+	{"cvmx_ilk_rx#_cfg1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6958,	14,	2840},
+	{"cvmx_ilk_rx#_flow_ctl0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6960,	1,	2854},
+	{"cvmx_ilk_rx#_flow_ctl1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6962,	1,	2855},
+	{"cvmx_ilk_rx#_idx_cal"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6964,	4,	2856},
+	{"cvmx_ilk_rx#_idx_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6966,	6,	2860},
+	{"cvmx_ilk_rx#_idx_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6968,	6,	2866},
+	{"cvmx_ilk_rx#_int"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6970,	9,	2872},
+	{"cvmx_ilk_rx#_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6972,	9,	2881},
+	{"cvmx_ilk_rx#_jabber"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6974,	2,	2890},
+	{"cvmx_ilk_rx#_mem_cal0"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6976,	9,	2892},
+	{"cvmx_ilk_rx#_mem_cal1"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6978,	9,	2901},
+	{"cvmx_ilk_rx#_mem_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6980,	2,	2910},
+	{"cvmx_ilk_rx#_mem_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6982,	2,	2912},
+	{"cvmx_ilk_rx#_stat0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6984,	2,	2914},
+	{"cvmx_ilk_rx#_stat1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6986,	2,	2916},
+	{"cvmx_ilk_rx#_stat2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6988,	4,	2918},
+	{"cvmx_ilk_rx#_stat3"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6990,	2,	2922},
+	{"cvmx_ilk_rx#_stat4"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6992,	2,	2924},
+	{"cvmx_ilk_rx#_stat5"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6994,	2,	2926},
+	{"cvmx_ilk_rx#_stat6"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6996,	2,	2928},
+	{"cvmx_ilk_rx#_stat7"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6998,	2,	2930},
+	{"cvmx_ilk_rx#_stat8"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7000,	3,	2932},
+	{"cvmx_ilk_rx#_stat9"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7002,	1,	2935},
+	{"cvmx_ilk_rx_lne#_cfg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7004,	6,	2936},
+	{"cvmx_ilk_rx_lne#_int"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7012,	10,	2942},
+	{"cvmx_ilk_rx_lne#_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7020,	10,	2952},
+	{"cvmx_ilk_rx_lne#_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7028,	2,	2962},
+	{"cvmx_ilk_rx_lne#_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7036,	2,	2964},
+	{"cvmx_ilk_rx_lne#_stat2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7044,	4,	2966},
+	{"cvmx_ilk_rx_lne#_stat3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7052,	2,	2970},
+	{"cvmx_ilk_rx_lne#_stat4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7060,	4,	2972},
+	{"cvmx_ilk_rx_lne#_stat5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7068,	2,	2976},
+	{"cvmx_ilk_rx_lne#_stat6"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7076,	2,	2978},
+	{"cvmx_ilk_rx_lne#_stat7"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7084,	2,	2980},
+	{"cvmx_ilk_rx_lne#_stat8"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7092,	2,	2982},
+	{"cvmx_ilk_rx_lne#_stat9"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7100,	4,	2984},
+	{"cvmx_ilk_rxf_idx_pmap"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7108,	4,	2988},
+	{"cvmx_ilk_rxf_mem_pmap"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7109,	2,	2992},
+	{"cvmx_ilk_ser_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7110,	12,	2994},
+	{"cvmx_ilk_tx#_cfg0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7111,	17,	3006},
+	{"cvmx_ilk_tx#_cfg1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7113,	15,	3023},
+	{"cvmx_ilk_tx#_dbg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7115,	4,	3038},
+	{"cvmx_ilk_tx#_flow_ctl0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7117,	1,	3042},
+	{"cvmx_ilk_tx#_flow_ctl1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7119,	1,	3043},
+	{"cvmx_ilk_tx#_idx_cal"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7121,	4,	3044},
+	{"cvmx_ilk_tx#_idx_pmap"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7123,	4,	3048},
+	{"cvmx_ilk_tx#_idx_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7125,	6,	3052},
+	{"cvmx_ilk_tx#_idx_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7127,	6,	3058},
+	{"cvmx_ilk_tx#_int"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7129,	5,	3064},
+	{"cvmx_ilk_tx#_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7131,	5,	3069},
+	{"cvmx_ilk_tx#_mem_cal0"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7133,	13,	3074},
+	{"cvmx_ilk_tx#_mem_cal1"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7135,	13,	3087},
+	{"cvmx_ilk_tx#_mem_pmap"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7137,	2,	3100},
+	{"cvmx_ilk_tx#_mem_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7139,	2,	3102},
+	{"cvmx_ilk_tx#_mem_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7141,	2,	3104},
+	{"cvmx_ilk_tx#_pipe"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7143,	4,	3106},
+	{"cvmx_ilk_tx#_rmatch"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7145,	5,	3110},
+	{"cvmx_iob1_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7147,	9,	3115},
+	{"cvmx_iob1_ctl_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7148,	4,	3124},
+	{"cvmx_iob1_to_cmb_credits"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7149,	4,	3128},
+	{"cvmx_iob_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7150,	19,	3132},
+	{"cvmx_iob_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7151,	9,	3151},
+	{"cvmx_iob_fau_timeout"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7152,	3,	3160},
+	{"cvmx_iob_inb_control_match"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	7153,	5,	3163},
+	{"cvmx_iob_inb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	7154,	5,	3168},
+	{"cvmx_iob_inb_data_match"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7155,	1,	3173},
+	{"cvmx_iob_inb_data_match_enb" ,	CVMX_CSR_DB_TYPE_RSL,	64,	7156,	1,	3174},
+	{"cvmx_iob_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7157,	1,	3175},
+	{"cvmx_iob_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7158,	1,	3176},
+	{"cvmx_iob_outb_com_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7159,	3,	3177},
+	{"cvmx_iob_outb_control_match" ,	CVMX_CSR_DB_TYPE_RSL,	64,	7160,	5,	3180},
+	{"cvmx_iob_outb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	7161,	5,	3185},
+	{"cvmx_iob_outb_data_match"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7162,	1,	3190},
+	{"cvmx_iob_outb_data_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	7163,	1,	3191},
+	{"cvmx_iob_outb_fpa_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7164,	3,	3192},
+	{"cvmx_iob_outb_req_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7165,	3,	3195},
+	{"cvmx_iob_to_cmb_credits"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7166,	4,	3198},
+	{"cvmx_iob_to_ncb_did_00_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7167,	2,	3202},
+	{"cvmx_iob_to_ncb_did_111_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7168,	2,	3204},
+	{"cvmx_iob_to_ncb_did_223_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7169,	2,	3206},
+	{"cvmx_iob_to_ncb_did_24_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7170,	2,	3208},
+	{"cvmx_iob_to_ncb_did_32_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7171,	2,	3210},
+	{"cvmx_iob_to_ncb_did_40_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7172,	2,	3212},
+	{"cvmx_iob_to_ncb_did_55_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7173,	2,	3214},
+	{"cvmx_iob_to_ncb_did_64_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7174,	2,	3216},
+	{"cvmx_iob_to_ncb_did_79_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7175,	2,	3218},
+	{"cvmx_iob_to_ncb_did_96_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7176,	2,	3220},
+	{"cvmx_iob_to_ncb_did_98_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7177,	2,	3222},
+	{"cvmx_ipd_1st_mbuff_skip"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	7178,	2,	3224},
+	{"cvmx_ipd_1st_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	7179,	2,	3226},
+	{"cvmx_ipd_2nd_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	7180,	2,	3228},
+	{"cvmx_ipd_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	7181,	24,	3230},
+	{"cvmx_ipd_bpid#_mbuf_th"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	7182,	3,	3254},
+	{"cvmx_ipd_bpid_bp_counter#"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	7246,	2,	3257},
+	{"cvmx_ipd_clk_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	7310,	1,	3259},
+	{"cvmx_ipd_credits"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	7311,	3,	3260},
+	{"cvmx_ipd_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	7312,	18,	3263},
+	{"cvmx_ipd_ecc_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	7313,	5,	3281},
+	{"cvmx_ipd_free_ptr_fifo_ctl"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	7314,	6,	3286},
+	{"cvmx_ipd_free_ptr_value"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	7315,	2,	3292},
+	{"cvmx_ipd_hold_ptr_fifo_ctl"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	7316,	6,	3294},
+	{"cvmx_ipd_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	7317,	24,	3300},
+	{"cvmx_ipd_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	7318,	24,	3324},
+	{"cvmx_ipd_next_pkt_ptr"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	7319,	2,	3348},
+	{"cvmx_ipd_next_wqe_ptr"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	7320,	2,	3350},
+	{"cvmx_ipd_not_1st_mbuff_skip" ,	CVMX_CSR_DB_TYPE_NCB,	64,	7321,	2,	3352},
+	{"cvmx_ipd_on_bp_drop_pkt#"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	7322,	1,	3354},
+	{"cvmx_ipd_packet_mbuff_size"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	7323,	2,	3355},
+	{"cvmx_ipd_pkt_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	7324,	2,	3357},
+	{"cvmx_ipd_port_ptr_fifo_ctl"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	7325,	5,	3359},
+	{"cvmx_ipd_port_qos_#_cnt"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	7326,	2,	3364},
+	{"cvmx_ipd_port_qos_int#"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	7838,	1,	3366},
+	{"cvmx_ipd_port_qos_int_enb#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	7846,	1,	3367},
+	{"cvmx_ipd_port_sop#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	7854,	1,	3368},
+	{"cvmx_ipd_ptr_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	7855,	6,	3369},
+	{"cvmx_ipd_qos#_red_marks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	7856,	2,	3375},
+	{"cvmx_ipd_que0_free_page_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	64,	7864,	2,	3377},
+	{"cvmx_ipd_red_bpid_enable#"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	7865,	1,	3379},
+	{"cvmx_ipd_red_delay"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	7866,	3,	3380},
+	{"cvmx_ipd_red_que#_param"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	7867,	5,	3383},
+	{"cvmx_ipd_sub_port_bp_page_cnt",	CVMX_CSR_DB_TYPE_NCB,	64,	7875,	3,	3388},
+	{"cvmx_ipd_sub_port_qos_cnt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	7876,	3,	3391},
+	{"cvmx_ipd_wqe_fpa_queue"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	7877,	2,	3394},
+	{"cvmx_key_bist_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7878,	4,	3396},
+	{"cvmx_key_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7879,	3,	3400},
+	{"cvmx_key_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7880,	5,	3403},
+	{"cvmx_key_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7881,	5,	3408},
+	{"cvmx_l2c_big_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7882,	4,	3413},
+	{"cvmx_l2c_bst"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	7883,	9,	3417},
+	{"cvmx_l2c_bst_mem#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7884,	5,	3426},
+	{"cvmx_l2c_bst_tdt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7888,	5,	3431},
+	{"cvmx_l2c_bst_ttg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7892,	3,	3436},
+	{"cvmx_l2c_cop0_map#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7896,	1,	3439},
+	{"cvmx_l2c_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	16344,	14,	3440},
+	{"cvmx_l2c_dut_map#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	16345,	4,	3454},
+	{"cvmx_l2c_err_tdt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24537,	9,	3458},
+	{"cvmx_l2c_err_ttg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24541,	9,	3467},
+	{"cvmx_l2c_err_vbf#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24545,	6,	3476},
+	{"cvmx_l2c_err_xmc"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	24549,	5,	3482},
+	{"cvmx_l2c_int_ena"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	24550,	9,	3487},
+	{"cvmx_l2c_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	24551,	14,	3496},
+	{"cvmx_l2c_ioc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24552,	1,	3510},
+	{"cvmx_l2c_ior#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24553,	1,	3511},
+	{"cvmx_l2c_qos_iob#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24554,	4,	3512},
+	{"cvmx_l2c_qos_pp#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	24556,	2,	3516},
+	{"cvmx_l2c_qos_wgt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	24588,	8,	3518},
+	{"cvmx_l2c_rsc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24589,	1,	3526},
+	{"cvmx_l2c_rsd#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24593,	1,	3527},
+	{"cvmx_l2c_tad#_ecc0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	24597,	8,	3528},
+	{"cvmx_l2c_tad#_ecc1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	24601,	8,	3536},
+	{"cvmx_l2c_tad#_ien"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24605,	10,	3544},
+	{"cvmx_l2c_tad#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24609,	10,	3554},
+	{"cvmx_l2c_tad#_pfc0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	24613,	1,	3564},
+	{"cvmx_l2c_tad#_pfc1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	24617,	1,	3565},
+	{"cvmx_l2c_tad#_pfc2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	24621,	1,	3566},
+	{"cvmx_l2c_tad#_pfc3"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	24625,	1,	3567},
+	{"cvmx_l2c_tad#_prf"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24629,	5,	3568},
+	{"cvmx_l2c_tad#_tag"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24633,	9,	3573},
+	{"cvmx_l2c_ver_id"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	24637,	1,	3582},
+	{"cvmx_l2c_ver_iob"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	24638,	2,	3583},
+	{"cvmx_l2c_ver_msc"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	24639,	3,	3585},
+	{"cvmx_l2c_ver_pp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	24640,	2,	3588},
+	{"cvmx_l2c_virtid_iob#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	24641,	4,	3590},
+	{"cvmx_l2c_virtid_pp#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	24643,	2,	3594},
+	{"cvmx_l2c_vrt_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	24675,	6,	3596},
+	{"cvmx_l2c_vrt_mem#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24676,	3,	3602},
+	{"cvmx_l2c_wpar_iob#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	25700,	2,	3605},
+	{"cvmx_l2c_wpar_pp#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25702,	2,	3607},
+	{"cvmx_l2c_xmc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25734,	1,	3609},
+	{"cvmx_l2c_xmc_cmd"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	25738,	4,	3610},
+	{"cvmx_l2c_xmd#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25739,	1,	3614},
+	{"cvmx_lmc#_char_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	25743,	5,	3615},
+	{"cvmx_lmc#_char_mask0"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25747,	1,	3620},
+	{"cvmx_lmc#_char_mask1"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25751,	2,	3621},
+	{"cvmx_lmc#_char_mask2"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25755,	1,	3623},
+	{"cvmx_lmc#_char_mask3"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25759,	2,	3624},
+	{"cvmx_lmc#_char_mask4"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25763,	12,	3626},
+	{"cvmx_lmc#_comp_ctl2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	25767,	11,	3638},
+	{"cvmx_lmc#_config"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	25771,	21,	3649},
+	{"cvmx_lmc#_control"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25775,	26,	3670},
+	{"cvmx_lmc#_dclk_cnt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	25779,	1,	3696},
+	{"cvmx_lmc#_ddr_pll_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	25783,	11,	3697},
+	{"cvmx_lmc#_dimm#_params"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	25787,	16,	3708},
+	{"cvmx_lmc#_dimm_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	25795,	5,	3724},
+	{"cvmx_lmc#_dll_ctl2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	25799,	7,	3729},
+	{"cvmx_lmc#_dll_ctl3"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	25803,	16,	3736},
+	{"cvmx_lmc#_dual_memcfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	25807,	4,	3752},
+	{"cvmx_lmc#_ecc_synd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	25811,	5,	3756},
+	{"cvmx_lmc#_fadr"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	25815,	6,	3761},
+	{"cvmx_lmc#_ifb_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25819,	1,	3767},
+	{"cvmx_lmc#_int"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	25823,	4,	3768},
+	{"cvmx_lmc#_int_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	25827,	4,	3772},
+	{"cvmx_lmc#_modereg_params0"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	25831,	16,	3776},
+	{"cvmx_lmc#_modereg_params1"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	25835,	25,	3792},
+	{"cvmx_lmc#_nxm"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	25839,	10,	3817},
+	{"cvmx_lmc#_ops_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25843,	1,	3827},
+	{"cvmx_lmc#_phy_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25847,	10,	3828},
+	{"cvmx_lmc#_reset_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	25851,	5,	3838},
+	{"cvmx_lmc#_rlevel_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25855,	10,	3843},
+	{"cvmx_lmc#_rlevel_dbg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25859,	1,	3853},
+	{"cvmx_lmc#_rlevel_rank#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	25863,	11,	3854},
+	{"cvmx_lmc#_rodt_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	25879,	8,	3865},
+	{"cvmx_lmc#_slot_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	25883,	5,	3873},
+	{"cvmx_lmc#_slot_ctl1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	25887,	5,	3878},
+	{"cvmx_lmc#_slot_ctl2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	25891,	5,	3883},
+	{"cvmx_lmc#_timing_params0"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	25895,	12,	3888},
+	{"cvmx_lmc#_timing_params1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	25899,	13,	3900},
+	{"cvmx_lmc#_tro_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25903,	3,	3913},
+	{"cvmx_lmc#_tro_stat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	25907,	2,	3916},
+	{"cvmx_lmc#_wlevel_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25911,	6,	3918},
+	{"cvmx_lmc#_wlevel_dbg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25915,	3,	3924},
+	{"cvmx_lmc#_wlevel_rank#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	25919,	11,	3927},
+	{"cvmx_lmc#_wodt_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	25935,	8,	3938},
+	{"cvmx_mio_boot_bist_stat"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	25939,	2,	3946},
+	{"cvmx_mio_boot_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	25940,	3,	3948},
+	{"cvmx_mio_boot_dma_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	25941,	10,	3951},
+	{"cvmx_mio_boot_dma_int#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	25943,	3,	3961},
+	{"cvmx_mio_boot_dma_int_en#"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	25945,	3,	3964},
+	{"cvmx_mio_boot_dma_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	25947,	15,	3967},
+	{"cvmx_mio_boot_err"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25949,	3,	3982},
+	{"cvmx_mio_boot_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25950,	3,	3985},
+	{"cvmx_mio_boot_loc_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	25951,	3,	3988},
+	{"cvmx_mio_boot_loc_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	25952,	5,	3991},
+	{"cvmx_mio_boot_loc_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	25954,	1,	3996},
+	{"cvmx_mio_boot_pin_defs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	25955,	9,	3997},
+	{"cvmx_mio_boot_reg_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	25956,	13,	4006},
+	{"cvmx_mio_boot_reg_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	25964,	13,	4019},
+	{"cvmx_mio_boot_thr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25972,	6,	4032},
+	{"cvmx_mio_fus_bnk_dat#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	25973,	1,	4038},
+	{"cvmx_mio_fus_dat0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25975,	2,	4039},
+	{"cvmx_mio_fus_dat1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25976,	2,	4041},
+	{"cvmx_mio_fus_dat2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25977,	12,	4043},
+	{"cvmx_mio_fus_dat3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25978,	18,	4055},
+	{"cvmx_mio_fus_ema"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	25979,	4,	4073},
+	{"cvmx_mio_fus_pdf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	25980,	1,	4077},
+	{"cvmx_mio_fus_pll"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	25981,	10,	4078},
+	{"cvmx_mio_fus_prog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25982,	3,	4088},
+	{"cvmx_mio_fus_prog_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	25983,	8,	4091},
+	{"cvmx_mio_fus_rcmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25984,	7,	4099},
+	{"cvmx_mio_fus_read_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	25985,	6,	4106},
+	{"cvmx_mio_fus_repair_res0"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	25986,	5,	4112},
+	{"cvmx_mio_fus_repair_res1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	25987,	4,	4117},
+	{"cvmx_mio_fus_repair_res2"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	25988,	2,	4121},
+	{"cvmx_mio_fus_spr_repair_res" ,	CVMX_CSR_DB_TYPE_RSL,	64,	25989,	4,	4123},
+	{"cvmx_mio_fus_spr_repair_sum" ,	CVMX_CSR_DB_TYPE_RSL,	64,	25990,	2,	4127},
+	{"cvmx_mio_fus_wadr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25991,	2,	4129},
+	{"cvmx_mio_gpio_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	25992,	3,	4131},
+	{"cvmx_mio_ndf_dma_cfg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25993,	10,	4134},
+	{"cvmx_mio_ndf_dma_int"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25994,	2,	4144},
+	{"cvmx_mio_ndf_dma_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	25995,	2,	4146},
+	{"cvmx_mio_ptp_clock_cfg"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	25996,	10,	4148},
+	{"cvmx_mio_ptp_clock_comp"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	25997,	2,	4158},
+	{"cvmx_mio_ptp_clock_hi"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	25998,	1,	4160},
+	{"cvmx_mio_ptp_clock_lo"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	25999,	2,	4161},
+	{"cvmx_mio_ptp_evt_cnt"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	26000,	1,	4163},
+	{"cvmx_mio_ptp_timestamp"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	26001,	1,	4164},
+	{"cvmx_mio_qlm#_cfg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26002,	4,	4165},
+	{"cvmx_mio_rst_boot"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26007,	11,	4169},
+	{"cvmx_mio_rst_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	26008,	5,	4180},
+	{"cvmx_mio_rst_ctl#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26009,	10,	4185},
+	{"cvmx_mio_rst_delay"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26011,	3,	4195},
+	{"cvmx_mio_rst_int"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	26012,	6,	4198},
+	{"cvmx_mio_rst_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	26013,	6,	4204},
+	{"cvmx_mio_tws#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26014,	13,	4210},
+	{"cvmx_mio_tws#_sw_twsi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26016,	12,	4223},
+	{"cvmx_mio_tws#_sw_twsi_ext"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	26018,	3,	4235},
+	{"cvmx_mio_tws#_twsi_sw"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26020,	3,	4238},
+	{"cvmx_mio_uart#_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26022,	2,	4241},
+	{"cvmx_mio_uart#_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26024,	2,	4243},
+	{"cvmx_mio_uart#_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26026,	2,	4245},
+	{"cvmx_mio_uart#_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26028,	7,	4247},
+	{"cvmx_mio_uart#_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26030,	2,	4254},
+	{"cvmx_mio_uart#_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26032,	7,	4256},
+	{"cvmx_mio_uart#_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26034,	4,	4263},
+	{"cvmx_mio_uart#_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26036,	8,	4267},
+	{"cvmx_mio_uart#_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26038,	9,	4275},
+	{"cvmx_mio_uart#_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26040,	7,	4284},
+	{"cvmx_mio_uart#_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26042,	9,	4291},
+	{"cvmx_mio_uart#_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26044,	2,	4300},
+	{"cvmx_mio_uart#_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26046,	2,	4302},
+	{"cvmx_mio_uart#_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26048,	4,	4304},
+	{"cvmx_mio_uart#_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	26050,	2,	4308},
+	{"cvmx_mio_uart#_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26052,	2,	4310},
+	{"cvmx_mio_uart#_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26054,	2,	4312},
+	{"cvmx_mio_uart#_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26056,	4,	4314},
+	{"cvmx_mio_uart#_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26058,	2,	4318},
+	{"cvmx_mio_uart#_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	26060,	2,	4320},
+	{"cvmx_mio_uart#_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26062,	2,	4322},
+	{"cvmx_mio_uart#_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26064,	2,	4324},
+	{"cvmx_mio_uart#_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26066,	2,	4326},
+	{"cvmx_mio_uart#_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26068,	2,	4328},
+	{"cvmx_mio_uart#_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26070,	6,	4330},
+	{"cvmx_mix#_bist"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	26072,	7,	4336},
+	{"cvmx_mix#_ctl"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	26073,	9,	4343},
+	{"cvmx_mix#_intena"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	26074,	9,	4352},
+	{"cvmx_mix#_ircnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	26075,	2,	4361},
+	{"cvmx_mix#_irhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	26076,	3,	4363},
+	{"cvmx_mix#_iring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	26077,	4,	4366},
+	{"cvmx_mix#_iring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	26078,	4,	4370},
+	{"cvmx_mix#_isr"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	26079,	9,	4374},
+	{"cvmx_mix#_orcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	26080,	2,	4383},
+	{"cvmx_mix#_orhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	26081,	2,	4385},
+	{"cvmx_mix#_oring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	26082,	4,	4387},
+	{"cvmx_mix#_oring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	26083,	4,	4391},
+	{"cvmx_mix#_remcnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	26084,	4,	4395},
+	{"cvmx_mix#_tsctl"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	26085,	6,	4399},
+	{"cvmx_mix#_tstamp"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	26086,	1,	4405},
+	{"cvmx_ndf_bt_pg_info"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	26087,	4,	4406},
+	{"cvmx_ndf_cmd"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	26088,	1,	4410},
+	{"cvmx_ndf_drbell"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	26089,	2,	4411},
+	{"cvmx_ndf_ecc_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	26090,	3,	4413},
+	{"cvmx_ndf_int"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	26091,	8,	4416},
+	{"cvmx_ndf_int_en"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	26092,	8,	4424},
+	{"cvmx_ndf_misc"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	26093,	12,	4432},
+	{"cvmx_ndf_st_reg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	26094,	8,	4444},
+	{"cvmx_pcieep#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26095,	2,	4452},
+	{"cvmx_pcieep#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26097,	24,	4454},
+	{"cvmx_pcieep#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26099,	4,	4478},
+	{"cvmx_pcieep#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26101,	5,	4482},
+	{"cvmx_pcieep#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26103,	5,	4487},
+	{"cvmx_pcieep#_cfg004_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26105,	2,	4492},
+	{"cvmx_pcieep#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26107,	1,	4494},
+	{"cvmx_pcieep#_cfg005_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26109,	1,	4495},
+	{"cvmx_pcieep#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26111,	5,	4496},
+	{"cvmx_pcieep#_cfg006_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26113,	2,	4501},
+	{"cvmx_pcieep#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26115,	1,	4503},
+	{"cvmx_pcieep#_cfg007_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26117,	1,	4504},
+	{"cvmx_pcieep#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26119,	4,	4505},
+	{"cvmx_pcieep#_cfg008_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26121,	2,	4509},
+	{"cvmx_pcieep#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26123,	2,	4511},
+	{"cvmx_pcieep#_cfg009_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26125,	1,	4513},
+	{"cvmx_pcieep#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26127,	1,	4514},
+	{"cvmx_pcieep#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26129,	2,	4515},
+	{"cvmx_pcieep#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26131,	3,	4517},
+	{"cvmx_pcieep#_cfg012_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26133,	2,	4520},
+	{"cvmx_pcieep#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26135,	2,	4522},
+	{"cvmx_pcieep#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26137,	4,	4524},
+	{"cvmx_pcieep#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26139,	10,	4528},
+	{"cvmx_pcieep#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26141,	12,	4538},
+	{"cvmx_pcieep#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26143,	8,	4550},
+	{"cvmx_pcieep#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26145,	2,	4558},
+	{"cvmx_pcieep#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26147,	1,	4560},
+	{"cvmx_pcieep#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26149,	2,	4561},
+	{"cvmx_pcieep#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26151,	7,	4563},
+	{"cvmx_pcieep#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26153,	12,	4570},
+	{"cvmx_pcieep#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26155,	19,	4582},
+	{"cvmx_pcieep#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26157,	11,	4601},
+	{"cvmx_pcieep#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26159,	19,	4612},
+	{"cvmx_pcieep#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26161,	11,	4631},
+	{"cvmx_pcieep#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26163,	8,	4642},
+	{"cvmx_pcieep#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26165,	4,	4650},
+	{"cvmx_pcieep#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26167,	11,	4654},
+	{"cvmx_pcieep#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26169,	3,	4665},
+	{"cvmx_pcieep#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26171,	14,	4668},
+	{"cvmx_pcieep#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26173,	14,	4682},
+	{"cvmx_pcieep#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26175,	14,	4696},
+	{"cvmx_pcieep#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26177,	9,	4710},
+	{"cvmx_pcieep#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26179,	9,	4719},
+	{"cvmx_pcieep#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26181,	6,	4728},
+	{"cvmx_pcieep#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26183,	1,	4734},
+	{"cvmx_pcieep#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26185,	1,	4735},
+	{"cvmx_pcieep#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26187,	1,	4736},
+	{"cvmx_pcieep#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26189,	1,	4737},
+	{"cvmx_pcieep#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26191,	2,	4738},
+	{"cvmx_pcieep#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26193,	1,	4740},
+	{"cvmx_pcieep#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26195,	6,	4741},
+	{"cvmx_pcieep#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26197,	7,	4747},
+	{"cvmx_pcieep#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26199,	11,	4754},
+	{"cvmx_pcieep#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26201,	5,	4765},
+	{"cvmx_pcieep#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26203,	8,	4770},
+	{"cvmx_pcieep#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26205,	19,	4778},
+	{"cvmx_pcieep#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26207,	3,	4797},
+	{"cvmx_pcieep#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26209,	1,	4800},
+	{"cvmx_pcieep#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26211,	1,	4801},
+	{"cvmx_pcieep#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26213,	3,	4802},
+	{"cvmx_pcieep#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26215,	3,	4805},
+	{"cvmx_pcieep#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26217,	3,	4808},
+	{"cvmx_pcieep#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26219,	4,	4811},
+	{"cvmx_pcieep#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26221,	4,	4815},
+	{"cvmx_pcieep#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26223,	4,	4819},
+	{"cvmx_pcieep#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26225,	7,	4823},
+	{"cvmx_pcieep#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26227,	5,	4830},
+	{"cvmx_pcieep#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26229,	5,	4835},
+	{"cvmx_pcieep#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26231,	4,	4840},
+	{"cvmx_pcieep#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26233,	4,	4844},
+	{"cvmx_pcieep#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26235,	4,	4848},
+	{"cvmx_pcieep#_cfg515"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26237,	7,	4852},
+	{"cvmx_pcieep#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26239,	1,	4859},
+	{"cvmx_pcieep#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26241,	1,	4860},
+	{"cvmx_pcierc#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26243,	2,	4861},
+	{"cvmx_pcierc#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26245,	24,	4863},
+	{"cvmx_pcierc#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26247,	4,	4887},
+	{"cvmx_pcierc#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26249,	5,	4891},
+	{"cvmx_pcierc#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26251,	1,	4896},
+	{"cvmx_pcierc#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26253,	1,	4897},
+	{"cvmx_pcierc#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26255,	4,	4898},
+	{"cvmx_pcierc#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26257,	17,	4902},
+	{"cvmx_pcierc#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26259,	4,	4919},
+	{"cvmx_pcierc#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26261,	6,	4923},
+	{"cvmx_pcierc#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26263,	1,	4929},
+	{"cvmx_pcierc#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26265,	1,	4930},
+	{"cvmx_pcierc#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26267,	2,	4931},
+	{"cvmx_pcierc#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26269,	2,	4933},
+	{"cvmx_pcierc#_cfg014"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26271,	1,	4935},
+	{"cvmx_pcierc#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26273,	15,	4936},
+	{"cvmx_pcierc#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26275,	10,	4951},
+	{"cvmx_pcierc#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26277,	12,	4961},
+	{"cvmx_pcierc#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26279,	7,	4973},
+	{"cvmx_pcierc#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26281,	2,	4980},
+	{"cvmx_pcierc#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26283,	1,	4982},
+	{"cvmx_pcierc#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26285,	2,	4983},
+	{"cvmx_pcierc#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26287,	7,	4985},
+	{"cvmx_pcierc#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26289,	11,	4992},
+	{"cvmx_pcierc#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26291,	19,	5003},
+	{"cvmx_pcierc#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26293,	11,	5022},
+	{"cvmx_pcierc#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26295,	20,	5033},
+	{"cvmx_pcierc#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26297,	12,	5053},
+	{"cvmx_pcierc#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26299,	22,	5065},
+	{"cvmx_pcierc#_cfg035"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26301,	8,	5087},
+	{"cvmx_pcierc#_cfg036"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26303,	4,	5095},
+	{"cvmx_pcierc#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26305,	11,	5099},
+	{"cvmx_pcierc#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26307,	8,	5110},
+	{"cvmx_pcierc#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26309,	4,	5118},
+	{"cvmx_pcierc#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26311,	11,	5122},
+	{"cvmx_pcierc#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26313,	1,	5133},
+	{"cvmx_pcierc#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26315,	1,	5134},
+	{"cvmx_pcierc#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26317,	3,	5135},
+	{"cvmx_pcierc#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26319,	14,	5138},
+	{"cvmx_pcierc#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26321,	14,	5152},
+	{"cvmx_pcierc#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26323,	14,	5166},
+	{"cvmx_pcierc#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26325,	9,	5180},
+	{"cvmx_pcierc#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26327,	9,	5189},
+	{"cvmx_pcierc#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26329,	6,	5198},
+	{"cvmx_pcierc#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26331,	1,	5204},
+	{"cvmx_pcierc#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26333,	1,	5205},
+	{"cvmx_pcierc#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26335,	1,	5206},
+	{"cvmx_pcierc#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26337,	1,	5207},
+	{"cvmx_pcierc#_cfg075"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26339,	4,	5208},
+	{"cvmx_pcierc#_cfg076"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26341,	9,	5212},
+	{"cvmx_pcierc#_cfg077"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26343,	2,	5221},
+	{"cvmx_pcierc#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26345,	2,	5223},
+	{"cvmx_pcierc#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26347,	1,	5225},
+	{"cvmx_pcierc#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26349,	6,	5226},
+	{"cvmx_pcierc#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26351,	7,	5232},
+	{"cvmx_pcierc#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26353,	11,	5239},
+	{"cvmx_pcierc#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26355,	5,	5250},
+	{"cvmx_pcierc#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26357,	8,	5255},
+	{"cvmx_pcierc#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26359,	19,	5263},
+	{"cvmx_pcierc#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26361,	3,	5282},
+	{"cvmx_pcierc#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26363,	1,	5285},
+	{"cvmx_pcierc#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26365,	1,	5286},
+	{"cvmx_pcierc#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26367,	3,	5287},
+	{"cvmx_pcierc#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26369,	3,	5290},
+	{"cvmx_pcierc#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26371,	3,	5293},
+	{"cvmx_pcierc#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26373,	4,	5296},
+	{"cvmx_pcierc#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26375,	4,	5300},
+	{"cvmx_pcierc#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26377,	4,	5304},
+	{"cvmx_pcierc#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26379,	7,	5308},
+	{"cvmx_pcierc#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26381,	5,	5315},
+	{"cvmx_pcierc#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26383,	5,	5320},
+	{"cvmx_pcierc#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26385,	4,	5325},
+	{"cvmx_pcierc#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26387,	4,	5329},
+	{"cvmx_pcierc#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26389,	4,	5333},
+	{"cvmx_pcierc#_cfg515"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26391,	7,	5337},
+	{"cvmx_pcierc#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26393,	1,	5344},
+	{"cvmx_pcierc#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26395,	1,	5345},
+	{"cvmx_pcs#_an#_adv_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26397,	9,	5346},
+	{"cvmx_pcs#_an#_ext_st_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26417,	6,	5355},
+	{"cvmx_pcs#_an#_lp_abil_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	26437,	9,	5361},
+	{"cvmx_pcs#_an#_results_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	26457,	6,	5370},
+	{"cvmx_pcs#_int#_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26477,	14,	5376},
+	{"cvmx_pcs#_int#_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26497,	14,	5390},
+	{"cvmx_pcs#_link#_timer_count_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	26517,	2,	5404},
+	{"cvmx_pcs#_log_anl#_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26537,	4,	5406},
+	{"cvmx_pcs#_misc#_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	26557,	8,	5410},
+	{"cvmx_pcs#_mr#_control_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	26577,	13,	5418},
+	{"cvmx_pcs#_mr#_status_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26597,	17,	5431},
+	{"cvmx_pcs#_rx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26617,	7,	5448},
+	{"cvmx_pcs#_rx#_sync_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26637,	3,	5455},
+	{"cvmx_pcs#_sgm#_an_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	26657,	8,	5458},
+	{"cvmx_pcs#_sgm#_lp_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	26677,	7,	5466},
+	{"cvmx_pcs#_tx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26697,	4,	5473},
+	{"cvmx_pcs#_tx_rx#_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	26717,	5,	5477},
+	{"cvmx_pcsx#_10gbx_status_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	26737,	8,	5482},
+	{"cvmx_pcsx#_bist_status_reg"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	26742,	2,	5490},
+	{"cvmx_pcsx#_bit_lock_status_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	26747,	5,	5492},
+	{"cvmx_pcsx#_control1_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	26752,	10,	5497},
+	{"cvmx_pcsx#_control2_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	26757,	2,	5507},
+	{"cvmx_pcsx#_int_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26762,	8,	5509},
+	{"cvmx_pcsx#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26767,	8,	5517},
+	{"cvmx_pcsx#_log_anl_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26772,	6,	5525},
+	{"cvmx_pcsx#_misc_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	26777,	5,	5531},
+	{"cvmx_pcsx#_rx_sync_states_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	26782,	5,	5536},
+	{"cvmx_pcsx#_spd_abil_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	26787,	3,	5541},
+	{"cvmx_pcsx#_status1_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26792,	6,	5544},
+	{"cvmx_pcsx#_status2_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26797,	9,	5550},
+	{"cvmx_pcsx#_tx_rx_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	26802,	5,	5559},
+	{"cvmx_pcsx#_tx_rx_states_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	26807,	10,	5564},
+	{"cvmx_pem#_bar1_index#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26812,	5,	5574},
+	{"cvmx_pem#_bar2_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	26844,	3,	5579},
+	{"cvmx_pem#_bar_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26846,	5,	5582},
+	{"cvmx_pem#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26848,	9,	5587},
+	{"cvmx_pem#_bist_status2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26850,	11,	5596},
+	{"cvmx_pem#_cfg_rd"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	26852,	2,	5607},
+	{"cvmx_pem#_cfg_wr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	26854,	2,	5609},
+	{"cvmx_pem#_cpl_lut_valid"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	26856,	2,	5611},
+	{"cvmx_pem#_ctl_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	26858,	18,	5613},
+	{"cvmx_pem#_dbg_info"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26860,	32,	5631},
+	{"cvmx_pem#_dbg_info_en"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26862,	32,	5663},
+	{"cvmx_pem#_diag_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26864,	5,	5695},
+	{"cvmx_pem#_int_enb"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26866,	15,	5700},
+	{"cvmx_pem#_int_enb_int"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26868,	15,	5715},
+	{"cvmx_pem#_int_sum"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26870,	15,	5730},
+	{"cvmx_pem#_p2n_bar0_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26872,	2,	5745},
+	{"cvmx_pem#_p2n_bar1_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26874,	2,	5747},
+	{"cvmx_pem#_p2n_bar2_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26876,	2,	5749},
+	{"cvmx_pem#_p2p_bar#_end"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26878,	2,	5751},
+	{"cvmx_pem#_p2p_bar#_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26886,	2,	5753},
+	{"cvmx_pem#_tlp_credits"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26894,	8,	5755},
+	{"cvmx_pip_bck_prs"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	26896,	5,	5763},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	26897,	2,	5768},
+	{"cvmx_pip_clken"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	26898,	2,	5770},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	26899,	4,	5772},
+	{"cvmx_pip_dsa_src_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	26903,	16,	5776},
+	{"cvmx_pip_dsa_vid_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	26904,	16,	5792},
+	{"cvmx_pip_frm_len_chk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26905,	3,	5808},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	26907,	8,	5811},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	26908,	21,	5819},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	26909,	14,	5840},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	26910,	14,	5854},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26911,	2,	5868},
+	{"cvmx_pip_pri_tbl#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26912,	15,	5870},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	27168,	30,	5885},
+	{"cvmx_pip_prt_cfgb#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	27232,	4,	5915},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	27296,	33,	5919},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	27360,	9,	5952},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	27368,	2,	5961},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	27369,	2,	5963},
+	{"cvmx_pip_stat0_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	27370,	2,	5965},
+	{"cvmx_pip_stat10_#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	27434,	2,	5967},
+	{"cvmx_pip_stat11_#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	27498,	2,	5969},
+	{"cvmx_pip_stat1_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	27562,	2,	5971},
+	{"cvmx_pip_stat2_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	27626,	2,	5973},
+	{"cvmx_pip_stat3_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	27690,	2,	5975},
+	{"cvmx_pip_stat4_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	27754,	2,	5977},
+	{"cvmx_pip_stat5_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	27818,	2,	5979},
+	{"cvmx_pip_stat6_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	27882,	2,	5981},
+	{"cvmx_pip_stat7_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	27946,	2,	5983},
+	{"cvmx_pip_stat8_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	28010,	2,	5985},
+	{"cvmx_pip_stat9_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	28074,	2,	5987},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	28138,	4,	5989},
+	{"cvmx_pip_stat_inb_errs_pknd#",	CVMX_CSR_DB_TYPE_RSL,	64,	28139,	2,	5993},
+	{"cvmx_pip_stat_inb_octs_pknd#",	CVMX_CSR_DB_TYPE_RSL,	64,	28203,	2,	5995},
+	{"cvmx_pip_stat_inb_pkts_pknd#",	CVMX_CSR_DB_TYPE_RSL,	64,	28267,	2,	5997},
+	{"cvmx_pip_sub_pkind_fcs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	28331,	1,	5999},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	28332,	2,	6000},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	28396,	2,	6002},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28397,	3,	6004},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28398,	3,	6007},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28399,	2,	6010},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28400,	2,	6012},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28401,	4,	6014},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28402,	5,	6018},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	28403,	4,	6023},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	28404,	8,	6027},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	28405,	1,	6035},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	28406,	1,	6036},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28407,	5,	6037},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28408,	1,	6042},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28409,	13,	6043},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28410,	7,	6056},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28411,	13,	6063},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28412,	6,	6076},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28413,	9,	6082},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28414,	4,	6091},
+	{"cvmx_pko_mem_iport_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	28415,	13,	6095},
+	{"cvmx_pko_mem_iport_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	28416,	6,	6108},
+	{"cvmx_pko_mem_iqueue_ptrs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	28417,	10,	6114},
+	{"cvmx_pko_mem_iqueue_qos"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	28418,	5,	6124},
+	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	28419,	5,	6129},
+	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	28420,	4,	6134},
+	{"cvmx_pko_mem_throttle_int"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	28421,	6,	6138},
+	{"cvmx_pko_mem_throttle_pipe"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	28422,	6,	6144},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	28423,	19,	6150},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	28424,	4,	6169},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28425,	1,	6173},
+	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28426,	1,	6174},
+	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28427,	1,	6175},
+	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28428,	1,	6176},
+	{"cvmx_pko_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28429,	1,	6177},
+	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	28430,	16,	6178},
+	{"cvmx_pko_reg_engine_inflight1",	CVMX_CSR_DB_TYPE_RSL,	64,	28431,	5,	6194},
+	{"cvmx_pko_reg_engine_storage#",	CVMX_CSR_DB_TYPE_RSL,	64,	28432,	16,	6199},
+	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	28434,	2,	6215},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	28435,	5,	6217},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	28436,	8,	6222},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	28437,	5,	6230},
+	{"cvmx_pko_reg_loopback_bpid"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	28438,	17,	6235},
+	{"cvmx_pko_reg_loopback_pkind" ,	CVMX_CSR_DB_TYPE_RSL,	64,	28439,	17,	6252},
+	{"cvmx_pko_reg_min_pkt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	28440,	8,	6269},
+	{"cvmx_pko_reg_preempt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	28441,	2,	6277},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	28442,	2,	6279},
+	{"cvmx_pko_reg_queue_preempt"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	28443,	3,	6281},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	28444,	3,	6284},
+	{"cvmx_pko_reg_throttle"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	28445,	2,	6287},
+	{"cvmx_pko_reg_timestamp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	28446,	2,	6289},
+	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28447,	1,	6291},
+	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28448,	1,	6292},
+	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28449,	1,	6293},
+	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	28450,	5,	6294},
+	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	28451,	5,	6299},
+	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	28452,	4,	6304},
+	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28453,	10,	6308},
+	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28454,	1,	6318},
+	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	28455,	3,	6319},
+	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	28456,	7,	6322},
+	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	28457,	2,	6329},
+	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28458,	1,	6331},
+	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28459,	1,	6332},
+	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28460,	1,	6333},
+	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28461,	18,	6334},
+	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28462,	3,	6352},
+	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28463,	2,	6355},
+	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28464,	3,	6357},
+	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28465,	7,	6360},
+	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	28466,	2,	6367},
+	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	28467,	2,	6369},
+	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	28468,	2,	6371},
+	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	28469,	3,	6373},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	28470,	3,	6376},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28471,	9,	6379},
+	{"cvmx_rnm_eer_dbg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	28472,	1,	6388},
+	{"cvmx_rnm_eer_key"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	28473,	1,	6389},
+	{"cvmx_rnm_serial_num"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28474,	1,	6390},
+	{"cvmx_sli_bist_status"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28475,	26,	6391},
+	{"cvmx_sli_ctl_port#"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28476,	16,	6417},
+	{"cvmx_sli_ctl_status"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28478,	4,	6433},
+	{"cvmx_sli_data_out_cnt"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28479,	5,	6437},
+	{"cvmx_sli_dbg_data"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28480,	3,	6442},
+	{"cvmx_sli_dbg_select"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28481,	3,	6445},
+	{"cvmx_sli_dma#_cnt"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28482,	2,	6448},
+	{"cvmx_sli_dma#_int_level"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28484,	2,	6450},
+	{"cvmx_sli_dma#_tim"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28486,	2,	6452},
+	{"cvmx_sli_int_enb_ciu"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28488,	36,	6454},
+	{"cvmx_sli_int_enb_port#"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28489,	38,	6490},
+	{"cvmx_sli_int_sum"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28491,	38,	6528},
+	{"cvmx_sli_last_win_rdata0"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28492,	1,	6566},
+	{"cvmx_sli_last_win_rdata1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28493,	1,	6567},
+	{"cvmx_sli_mac_credit_cnt"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28494,	13,	6568},
+	{"cvmx_sli_mac_number"         ,	CVMX_CSR_DB_TYPE_PEXP,	64,	28495,	2,	6581},
+	{"cvmx_sli_mem_access_ctl"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28496,	3,	6583},
+	{"cvmx_sli_mem_access_subid#"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28497,	10,	6586},
+	{"cvmx_sli_msi_enb0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28513,	1,	6596},
+	{"cvmx_sli_msi_enb1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28514,	1,	6597},
+	{"cvmx_sli_msi_enb2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28515,	1,	6598},
+	{"cvmx_sli_msi_enb3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28516,	1,	6599},
+	{"cvmx_sli_msi_rcv0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28517,	1,	6600},
+	{"cvmx_sli_msi_rcv1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28518,	1,	6601},
+	{"cvmx_sli_msi_rcv2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28519,	1,	6602},
+	{"cvmx_sli_msi_rcv3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28520,	1,	6603},
+	{"cvmx_sli_msi_rd_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28521,	3,	6604},
+	{"cvmx_sli_msi_w1c_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28522,	1,	6607},
+	{"cvmx_sli_msi_w1c_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28523,	1,	6608},
+	{"cvmx_sli_msi_w1c_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28524,	1,	6609},
+	{"cvmx_sli_msi_w1c_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28525,	1,	6610},
+	{"cvmx_sli_msi_w1s_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28526,	1,	6611},
+	{"cvmx_sli_msi_w1s_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28527,	1,	6612},
+	{"cvmx_sli_msi_w1s_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28528,	1,	6613},
+	{"cvmx_sli_msi_w1s_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28529,	1,	6614},
+	{"cvmx_sli_msi_wr_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28530,	3,	6615},
+	{"cvmx_sli_pcie_msi_rcv"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28531,	2,	6618},
+	{"cvmx_sli_pcie_msi_rcv_b1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28532,	3,	6620},
+	{"cvmx_sli_pcie_msi_rcv_b2"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28533,	3,	6623},
+	{"cvmx_sli_pcie_msi_rcv_b3"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28534,	3,	6626},
+	{"cvmx_sli_pkt#_cnts"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28535,	3,	6629},
+	{"cvmx_sli_pkt#_instr_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28567,	2,	6632},
+	{"cvmx_sli_pkt#_instr_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28599,	2,	6634},
+	{"cvmx_sli_pkt#_instr_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28631,	5,	6636},
+	{"cvmx_sli_pkt#_instr_header"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28663,	21,	6641},
+	{"cvmx_sli_pkt#_out_size"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28695,	3,	6662},
+	{"cvmx_sli_pkt#_slist_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28727,	2,	6665},
+	{"cvmx_sli_pkt#_slist_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28759,	2,	6667},
+	{"cvmx_sli_pkt#_slist_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28791,	2,	6669},
+	{"cvmx_sli_pkt_cnt_int"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28823,	2,	6671},
+	{"cvmx_sli_pkt_cnt_int_enb"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28824,	2,	6673},
+	{"cvmx_sli_pkt_ctl"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28825,	3,	6675},
+	{"cvmx_sli_pkt_data_out_es"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28826,	1,	6678},
+	{"cvmx_sli_pkt_data_out_ns"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28827,	2,	6679},
+	{"cvmx_sli_pkt_data_out_ror"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28828,	2,	6681},
+	{"cvmx_sli_pkt_dpaddr"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28829,	2,	6683},
+	{"cvmx_sli_pkt_in_done#_cnts"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28830,	2,	6685},
+	{"cvmx_sli_pkt_in_instr_counts",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28862,	2,	6687},
+	{"cvmx_sli_pkt_in_pcie_port"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28863,	1,	6689},
+	{"cvmx_sli_pkt_input_control"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28864,	17,	6690},
+	{"cvmx_sli_pkt_instr_enb"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28865,	2,	6707},
+	{"cvmx_sli_pkt_instr_rd_size"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28866,	1,	6709},
+	{"cvmx_sli_pkt_instr_size"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28867,	2,	6710},
+	{"cvmx_sli_pkt_int_levels"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28868,	3,	6712},
+	{"cvmx_sli_pkt_iptr"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28869,	2,	6715},
+	{"cvmx_sli_pkt_out_bmode"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28870,	2,	6717},
+	{"cvmx_sli_pkt_out_bp_en"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28871,	2,	6719},
+	{"cvmx_sli_pkt_out_enb"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28872,	2,	6721},
+	{"cvmx_sli_pkt_output_wmark"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28873,	2,	6723},
+	{"cvmx_sli_pkt_pcie_port"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28874,	1,	6725},
+	{"cvmx_sli_pkt_port_in_rst"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28875,	2,	6726},
+	{"cvmx_sli_pkt_slist_es"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28876,	1,	6728},
+	{"cvmx_sli_pkt_slist_ns"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28877,	2,	6729},
+	{"cvmx_sli_pkt_slist_ror"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28878,	2,	6731},
+	{"cvmx_sli_pkt_time_int"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28879,	2,	6733},
+	{"cvmx_sli_pkt_time_int_enb"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28880,	2,	6735},
+	{"cvmx_sli_port#_pkind"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28881,	4,	6737},
+	{"cvmx_sli_s2m_port#_ctl"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28913,	4,	6741},
+	{"cvmx_sli_scratch_1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28915,	1,	6745},
+	{"cvmx_sli_scratch_2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28916,	1,	6746},
+	{"cvmx_sli_state1"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28917,	4,	6747},
+	{"cvmx_sli_state2"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28918,	8,	6751},
+	{"cvmx_sli_state3"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28919,	5,	6759},
+	{"cvmx_sli_tx_pipe"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28920,	4,	6764},
+	{"cvmx_sli_win_rd_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	28921,	4,	6768},
+	{"cvmx_sli_win_rd_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	28922,	1,	6772},
+	{"cvmx_sli_win_wr_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	28923,	4,	6773},
+	{"cvmx_sli_win_wr_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	28924,	1,	6777},
+	{"cvmx_sli_win_wr_mask"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	28925,	2,	6778},
+	{"cvmx_sli_window_ctl"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	28926,	2,	6780},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	28927,	10,	6782},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	28931,	6,	6792},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	28935,	2,	6798},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	28939,	4,	6800},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	28943,	4,	6804},
+	{"cvmx_smi_drv_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	28947,	4,	6808},
+	{"cvmx_sso_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	28948,	19,	6812},
+	{"cvmx_sso_cfg"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	28949,	9,	6831},
+	{"cvmx_sso_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	28950,	1,	6840},
+	{"cvmx_sso_err"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	28951,	19,	6841},
+	{"cvmx_sso_err_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	28952,	19,	6860},
+	{"cvmx_sso_fidx_ecc_ctl"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	28953,	3,	6879},
+	{"cvmx_sso_fidx_ecc_st"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	28954,	5,	6882},
+	{"cvmx_sso_fpage_cnt"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	28955,	2,	6887},
+	{"cvmx_sso_gwe_cfg"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	28956,	5,	6889},
+	{"cvmx_sso_idx_ecc_ctl"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	28957,	3,	6894},
+	{"cvmx_sso_idx_ecc_st"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	28958,	5,	6897},
+	{"cvmx_sso_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	28959,	2,	6902},
+	{"cvmx_sso_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	28967,	2,	6904},
+	{"cvmx_sso_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	28968,	2,	6906},
+	{"cvmx_sso_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	28969,	2,	6908},
+	{"cvmx_sso_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	28970,	2,	6910},
+	{"cvmx_sso_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	28978,	2,	6912},
+	{"cvmx_sso_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	28979,	2,	6914},
+	{"cvmx_sso_oth_ecc_ctl"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	28980,	5,	6916},
+	{"cvmx_sso_oth_ecc_st"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	28981,	9,	6921},
+	{"cvmx_sso_pnd_ecc_ctl"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	28982,	5,	6930},
+	{"cvmx_sso_pnd_ecc_st"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	28983,	9,	6935},
+	{"cvmx_sso_pp#_grp_msk"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	28984,	1,	6944},
+	{"cvmx_sso_pp#_qos_pri"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	29016,	16,	6945},
+	{"cvmx_sso_pp_strict"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	29048,	2,	6961},
+	{"cvmx_sso_qos#_rnd"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	29049,	2,	6963},
+	{"cvmx_sso_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	29057,	6,	6965},
+	{"cvmx_sso_qos_we"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	29065,	4,	6971},
+	{"cvmx_sso_rwq_head_ptr#"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	29066,	4,	6975},
+	{"cvmx_sso_rwq_pop_fptr"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	29074,	4,	6979},
+	{"cvmx_sso_rwq_psh_fptr"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	29075,	4,	6983},
+	{"cvmx_sso_rwq_tail_ptr#"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	29076,	4,	6987},
+	{"cvmx_sso_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	29084,	1,	6991},
+	{"cvmx_sso_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	29085,	1,	6992},
+	{"cvmx_sso_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	29086,	1,	6993},
+	{"cvmx_sso_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	29094,	1,	6994},
+	{"cvmx_sso_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	29095,	6,	6995},
+	{"cvmx_sso_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	29159,	5,	7001},
+	{"cvmx_sso_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	29160,	7,	7006},
+	{"cvmx_sso_wq_iq_dis"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	29224,	1,	7013},
+	{"cvmx_sso_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	29225,	1,	7014},
+	{"cvmx_tim_bist_result"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	29289,	4,	7015},
+	{"cvmx_tim_dbg2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	29290,	11,	7019},
+	{"cvmx_tim_dbg3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	29291,	1,	7030},
+	{"cvmx_tim_ecc_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29292,	3,	7031},
+	{"cvmx_tim_fr_rn_tt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	29293,	2,	7034},
+	{"cvmx_tim_int0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	29294,	1,	7036},
+	{"cvmx_tim_int0_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29295,	1,	7037},
+	{"cvmx_tim_int0_event"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29296,	2,	7038},
+	{"cvmx_tim_int_eccerr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29297,	3,	7040},
+	{"cvmx_tim_int_eccerr_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	29298,	3,	7043},
+	{"cvmx_tim_int_eccerr_event0"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	29299,	3,	7046},
+	{"cvmx_tim_int_eccerr_event1"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	29300,	3,	7049},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	29301,	7,	7052},
+	{"cvmx_tim_ring#_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29302,	5,	7059},
+	{"cvmx_tim_ring#_ctl1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29366,	4,	7064},
+	{"cvmx_tim_ring#_ctl2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29430,	4,	7068},
+	{"cvmx_tim_ring#_dbg0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29494,	3,	7072},
+	{"cvmx_tim_ring#_dbg1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29558,	2,	7075},
+	{"cvmx_tra#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	29622,	2,	7077},
+	{"cvmx_tra#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	29626,	14,	7079},
+	{"cvmx_tra#_cycles_since"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	29630,	3,	7093},
+	{"cvmx_tra#_cycles_since1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	29634,	5,	7096},
+	{"cvmx_tra#_filt_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	29638,	2,	7101},
+	{"cvmx_tra#_filt_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	29642,	2,	7103},
+	{"cvmx_tra#_filt_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	29646,	57,	7105},
+	{"cvmx_tra#_filt_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	29650,	20,	7162},
+	{"cvmx_tra#_filt_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	29654,	7,	7182},
+	{"cvmx_tra#_int_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	29658,	5,	7189},
+	{"cvmx_tra#_read_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	29662,	1,	7194},
+	{"cvmx_tra#_read_dat_hi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	29666,	2,	7195},
+	{"cvmx_tra#_trig0_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	29670,	2,	7197},
+	{"cvmx_tra#_trig0_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	29674,	2,	7199},
+	{"cvmx_tra#_trig0_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29678,	57,	7201},
+	{"cvmx_tra#_trig0_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29682,	20,	7258},
+	{"cvmx_tra#_trig0_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29686,	7,	7278},
+	{"cvmx_tra#_trig1_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	29690,	2,	7285},
+	{"cvmx_tra#_trig1_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	29694,	2,	7287},
+	{"cvmx_tra#_trig1_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29698,	57,	7289},
+	{"cvmx_tra#_trig1_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29702,	20,	7346},
+	{"cvmx_tra#_trig1_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29706,	7,	7366},
+	{"cvmx_uahc#_ehci_asynclistaddr",	CVMX_CSR_DB_TYPE_NCB,	32,	29710,	2,	7373},
+	{"cvmx_uahc#_ehci_configflag"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	29711,	2,	7375},
+	{"cvmx_uahc#_ehci_ctrldssegment",	CVMX_CSR_DB_TYPE_NCB,	32,	29712,	1,	7377},
+	{"cvmx_uahc#_ehci_frindex"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	29713,	2,	7378},
+	{"cvmx_uahc#_ehci_hccapbase"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	29714,	3,	7380},
+	{"cvmx_uahc#_ehci_hccparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	29715,	7,	7383},
+	{"cvmx_uahc#_ehci_hcsparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	29716,	10,	7390},
+	{"cvmx_uahc#_ehci_insnreg00"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	29717,	3,	7400},
+	{"cvmx_uahc#_ehci_insnreg03"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	29718,	5,	7403},
+	{"cvmx_uahc#_ehci_insnreg04"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	29719,	7,	7408},
+	{"cvmx_uahc#_ehci_insnreg06"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	29720,	2,	7415},
+	{"cvmx_uahc#_ehci_insnreg07"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	29721,	1,	7417},
+	{"cvmx_uahc#_ehci_periodiclistbase",	CVMX_CSR_DB_TYPE_NCB,	32,	29722,	2,	7418},
+	{"cvmx_uahc#_ehci_portsc#"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	29723,	19,	7420},
+	{"cvmx_uahc#_ehci_usbcmd"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	29725,	13,	7439},
+	{"cvmx_uahc#_ehci_usbintr"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	29726,	7,	7452},
+	{"cvmx_uahc#_ehci_usbsts"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	29727,	12,	7459},
+	{"cvmx_uahc#_ohci0_hcbulkcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	29728,	2,	7471},
+	{"cvmx_uahc#_ohci0_hcbulkheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	29729,	2,	7473},
+	{"cvmx_uahc#_ohci0_hccommandstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	29730,	7,	7475},
+	{"cvmx_uahc#_ohci0_hccontrol"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	29731,	10,	7482},
+	{"cvmx_uahc#_ohci0_hccontrolcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	29732,	2,	7492},
+	{"cvmx_uahc#_ohci0_hccontrolheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	29733,	2,	7494},
+	{"cvmx_uahc#_ohci0_hcdonehead" ,	CVMX_CSR_DB_TYPE_NCB,	32,	29734,	2,	7496},
+	{"cvmx_uahc#_ohci0_hcfminterval",	CVMX_CSR_DB_TYPE_NCB,	32,	29735,	4,	7498},
+	{"cvmx_uahc#_ohci0_hcfmnumber" ,	CVMX_CSR_DB_TYPE_NCB,	32,	29736,	2,	7502},
+	{"cvmx_uahc#_ohci0_hcfmremaining",	CVMX_CSR_DB_TYPE_NCB,	32,	29737,	3,	7504},
+	{"cvmx_uahc#_ohci0_hchcca"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	29738,	2,	7507},
+	{"cvmx_uahc#_ohci0_hcinterruptdisable",	CVMX_CSR_DB_TYPE_NCB,	32,	29739,	10,	7509},
+	{"cvmx_uahc#_ohci0_hcinterruptenable",	CVMX_CSR_DB_TYPE_NCB,	32,	29740,	10,	7519},
+	{"cvmx_uahc#_ohci0_hcinterruptstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	29741,	10,	7529},
+	{"cvmx_uahc#_ohci0_hclsthreshold",	CVMX_CSR_DB_TYPE_NCB,	32,	29742,	2,	7539},
+	{"cvmx_uahc#_ohci0_hcperiodcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	29743,	2,	7541},
+	{"cvmx_uahc#_ohci0_hcperiodicstart",	CVMX_CSR_DB_TYPE_NCB,	32,	29744,	2,	7543},
+	{"cvmx_uahc#_ohci0_hcrevision" ,	CVMX_CSR_DB_TYPE_NCB,	32,	29745,	2,	7545},
+	{"cvmx_uahc#_ohci0_hcrhdescriptora",	CVMX_CSR_DB_TYPE_NCB,	32,	29746,	8,	7547},
+	{"cvmx_uahc#_ohci0_hcrhdescriptorb",	CVMX_CSR_DB_TYPE_NCB,	32,	29747,	2,	7555},
+	{"cvmx_uahc#_ohci0_hcrhportstatus#",	CVMX_CSR_DB_TYPE_NCB,	32,	29748,	15,	7557},
+	{"cvmx_uahc#_ohci0_hcrhstatus" ,	CVMX_CSR_DB_TYPE_NCB,	32,	29750,	8,	7572},
+	{"cvmx_uahc#_ohci0_insnreg06"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	29751,	2,	7580},
+	{"cvmx_uahc#_ohci0_insnreg07"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	29752,	1,	7582},
+	{"cvmx_uctl#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	29753,	7,	7583},
+	{"cvmx_uctl#_clk_rst_ctl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	29754,	21,	7590},
+	{"cvmx_uctl#_ehci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29755,	12,	7611},
+	{"cvmx_uctl#_ehci_fla"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29756,	2,	7623},
+	{"cvmx_uctl#_erto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29757,	3,	7625},
+	{"cvmx_uctl#_if_ena"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	29758,	2,	7628},
+	{"cvmx_uctl#_int_ena"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	29759,	9,	7630},
+	{"cvmx_uctl#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	29760,	9,	7639},
+	{"cvmx_uctl#_ohci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29761,	11,	7648},
+	{"cvmx_uctl#_orto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29762,	3,	7659},
+	{"cvmx_uctl#_uphy_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	29763,	11,	7662},
+	{"cvmx_uctl#_uphy_port#_ctl_status",	CVMX_CSR_DB_TYPE_RSL,	64,	29764,	20,	7673},
+	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	29766,	3,	7693},
+	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29767,	5,	7696},
+	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29768,	3,	7701},
+	{"cvmx_zip_constants"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	29769,	6,	7704},
+	{"cvmx_zip_core#_bist_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	29770,	2,	7710},
+	{"cvmx_zip_ctl_bist_status"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	29772,	2,	7712},
+	{"cvmx_zip_ctl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29773,	15,	7714},
+	{"cvmx_zip_dbg_core#_inst"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	29774,	4,	7729},
+	{"cvmx_zip_dbg_core#_sta"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	29776,	4,	7733},
+	{"cvmx_zip_dbg_que#_sta"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	29778,	4,	7737},
+	{"cvmx_zip_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	29780,	2,	7741},
+	{"cvmx_zip_ecc_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29781,	4,	7743},
+	{"cvmx_zip_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	29782,	2,	7747},
+	{"cvmx_zip_int_ena"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29783,	7,	7749},
+	{"cvmx_zip_int_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	29784,	2,	7756},
+	{"cvmx_zip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29785,	7,	7758},
+	{"cvmx_zip_que#_buf"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	29786,	5,	7765},
+	{"cvmx_zip_que#_ecc_err_sta"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	29788,	3,	7770},
+	{"cvmx_zip_que#_map"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	29790,	2,	7773},
+	{"cvmx_zip_que_ena"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29792,	2,	7775},
+	{"cvmx_zip_que_pri"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29793,	2,	7777},
+	{"cvmx_zip_throttle"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	29794,	2,	7779},
+	{NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn68xxp1[] = {
+	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
+	{"AGL_GMX_BAD_REG"             ,	   0x11800e0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"AGL_GMX_BIST"                ,	   0x11800e0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"AGL_GMX_PRT0_CFG"            ,	   0x11800e0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"AGL_GMX_RX0_ADR_CAM0"        ,	   0x11800e0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"AGL_GMX_RX0_ADR_CAM1"        ,	   0x11800e0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_RX0_ADR_CAM2"        ,	   0x11800e0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX0_ADR_CAM3"        ,	   0x11800e0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX0_ADR_CAM4"        ,	   0x11800e00001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX0_ADR_CAM5"        ,	   0x11800e00001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX0_ADR_CAM_EN"      ,	   0x11800e0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX0_ADR_CTL"         ,	   0x11800e0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX0_DECISION"        ,	   0x11800e0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX0_FRM_CHK"         ,	   0x11800e0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX0_FRM_CTL"         ,	   0x11800e0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX0_FRM_MAX"         ,	   0x11800e0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX0_FRM_MIN"         ,	   0x11800e0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX0_IFG"             ,	   0x11800e0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX0_INT_EN"          ,	   0x11800e0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX0_INT_REG"         ,	   0x11800e0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX0_JABBER"          ,	   0x11800e0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX0_PAUSE_DROP_TIME" ,	   0x11800e0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX0_RX_INBND"        ,	   0x11800e0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX0_STATS_CTL"       ,	   0x11800e0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX0_STATS_OCTS"      ,	   0x11800e0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX0_STATS_OCTS_CTL"  ,	   0x11800e0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX0_STATS_OCTS_DMAC" ,	   0x11800e00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX0_STATS_OCTS_DRP"  ,	   0x11800e00000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX0_STATS_PKTS"      ,	   0x11800e0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX0_STATS_PKTS_BAD"  ,	   0x11800e00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX0_STATS_PKTS_CTL"  ,	   0x11800e0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX0_STATS_PKTS_DMAC" ,	   0x11800e00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX0_STATS_PKTS_DRP"  ,	   0x11800e00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX0_UDD_SKP"         ,	   0x11800e0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX_BP_DROP0"         ,	   0x11800e0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX_BP_OFF0"          ,	   0x11800e0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_ON0"           ,	   0x11800e0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_PRT_INFO"         ,	   0x11800e00004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"AGL_GMX_RX_TX_STATUS"        ,	   0x11800e00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"AGL_GMX_SMAC0"               ,	   0x11800e0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"AGL_GMX_STAT_BP"             ,	   0x11800e0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"AGL_GMX_TX0_APPEND"          ,	   0x11800e0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"AGL_GMX_TX0_CLK"             ,	   0x11800e0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX0_CTL"             ,	   0x11800e0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX0_MIN_PKT"         ,	   0x11800e0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",	   0x11800e0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,	   0x11800e0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX0_PAUSE_TOGO"      ,	   0x11800e0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX0_PAUSE_ZERO"      ,	   0x11800e0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX0_SOFT_PAUSE"      ,	   0x11800e0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX0_STAT0"           ,	   0x11800e0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX0_STAT1"           ,	   0x11800e0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX0_STAT2"           ,	   0x11800e0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX0_STAT3"           ,	   0x11800e0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX0_STAT4"           ,	   0x11800e00002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX0_STAT5"           ,	   0x11800e00002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX0_STAT6"           ,	   0x11800e00002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX0_STAT7"           ,	   0x11800e00002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX0_STAT8"           ,	   0x11800e00002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX0_STAT9"           ,	   0x11800e00002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX0_STATS_CTL"       ,	   0x11800e0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX0_THRESH"          ,	   0x11800e0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX_BP"               ,	   0x11800e00004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"AGL_GMX_TX_COL_ATTEMPT"      ,	   0x11800e0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"AGL_GMX_TX_IFG"              ,	   0x11800e0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"AGL_GMX_TX_INT_EN"           ,	   0x11800e0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"AGL_GMX_TX_INT_REG"          ,	   0x11800e0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"AGL_GMX_TX_JAM"              ,	   0x11800e0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"AGL_GMX_TX_LFSR"             ,	   0x11800e00004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"AGL_GMX_TX_OVR_BP"           ,	   0x11800e00004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,	   0x11800e00004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,	   0x11800e00004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"AGL_PRT0_CTL"                ,	   0x11800e0002000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"CIU2_ACK_IO0_INT"            ,	   0x10701080c0800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
+	{"CIU2_ACK_IO1_INT"            ,	   0x10701082c0800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
+	{"CIU2_ACK_PP0_IP2"            ,	   0x10701000c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP1_IP2"            ,	   0x10701002c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP2_IP2"            ,	   0x10701004c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP3_IP2"            ,	   0x10701006c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP4_IP2"            ,	   0x10701008c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP5_IP2"            ,	   0x1070100ac0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP6_IP2"            ,	   0x1070100cc0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP7_IP2"            ,	   0x1070100ec0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP8_IP2"            ,	   0x10701010c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP9_IP2"            ,	   0x10701012c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP10_IP2"           ,	   0x10701014c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP11_IP2"           ,	   0x10701016c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP12_IP2"           ,	   0x10701018c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP13_IP2"           ,	   0x1070101ac0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP14_IP2"           ,	   0x1070101cc0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP15_IP2"           ,	   0x1070101ec0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP16_IP2"           ,	   0x10701020c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP17_IP2"           ,	   0x10701022c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP18_IP2"           ,	   0x10701024c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP19_IP2"           ,	   0x10701026c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP20_IP2"           ,	   0x10701028c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP21_IP2"           ,	   0x1070102ac0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP22_IP2"           ,	   0x1070102cc0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP23_IP2"           ,	   0x1070102ec0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP24_IP2"           ,	   0x10701030c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP25_IP2"           ,	   0x10701032c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP26_IP2"           ,	   0x10701034c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP27_IP2"           ,	   0x10701036c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP28_IP2"           ,	   0x10701038c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP29_IP2"           ,	   0x1070103ac0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP30_IP2"           ,	   0x1070103cc0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP31_IP2"           ,	   0x1070103ec0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP0_IP3"            ,	   0x10701000c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP1_IP3"            ,	   0x10701002c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP2_IP3"            ,	   0x10701004c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP3_IP3"            ,	   0x10701006c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP4_IP3"            ,	   0x10701008c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP5_IP3"            ,	   0x1070100ac0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP6_IP3"            ,	   0x1070100cc0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP7_IP3"            ,	   0x1070100ec0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP8_IP3"            ,	   0x10701010c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP9_IP3"            ,	   0x10701012c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP10_IP3"           ,	   0x10701014c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP11_IP3"           ,	   0x10701016c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP12_IP3"           ,	   0x10701018c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP13_IP3"           ,	   0x1070101ac0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP14_IP3"           ,	   0x1070101cc0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP15_IP3"           ,	   0x1070101ec0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP16_IP3"           ,	   0x10701020c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP17_IP3"           ,	   0x10701022c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP18_IP3"           ,	   0x10701024c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP19_IP3"           ,	   0x10701026c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP20_IP3"           ,	   0x10701028c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP21_IP3"           ,	   0x1070102ac0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP22_IP3"           ,	   0x1070102cc0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP23_IP3"           ,	   0x1070102ec0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP24_IP3"           ,	   0x10701030c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP25_IP3"           ,	   0x10701032c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP26_IP3"           ,	   0x10701034c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP27_IP3"           ,	   0x10701036c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP28_IP3"           ,	   0x10701038c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP29_IP3"           ,	   0x1070103ac0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP30_IP3"           ,	   0x1070103cc0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP31_IP3"           ,	   0x1070103ec0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP0_IP4"            ,	   0x10701000c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP1_IP4"            ,	   0x10701002c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP2_IP4"            ,	   0x10701004c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP3_IP4"            ,	   0x10701006c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP4_IP4"            ,	   0x10701008c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP5_IP4"            ,	   0x1070100ac0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP6_IP4"            ,	   0x1070100cc0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP7_IP4"            ,	   0x1070100ec0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP8_IP4"            ,	   0x10701010c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP9_IP4"            ,	   0x10701012c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP10_IP4"           ,	   0x10701014c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP11_IP4"           ,	   0x10701016c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP12_IP4"           ,	   0x10701018c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP13_IP4"           ,	   0x1070101ac0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP14_IP4"           ,	   0x1070101cc0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP15_IP4"           ,	   0x1070101ec0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP16_IP4"           ,	   0x10701020c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP17_IP4"           ,	   0x10701022c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP18_IP4"           ,	   0x10701024c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP19_IP4"           ,	   0x10701026c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP20_IP4"           ,	   0x10701028c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP21_IP4"           ,	   0x1070102ac0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP22_IP4"           ,	   0x1070102cc0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP23_IP4"           ,	   0x1070102ec0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP24_IP4"           ,	   0x10701030c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP25_IP4"           ,	   0x10701032c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP26_IP4"           ,	   0x10701034c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP27_IP4"           ,	   0x10701036c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP28_IP4"           ,	   0x10701038c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP29_IP4"           ,	   0x1070103ac0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP30_IP4"           ,	   0x1070103cc0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP31_IP4"           ,	   0x1070103ec0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_EN_IO0_INT_GPIO"        ,	   0x1070108097800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU2_EN_IO1_INT_GPIO"        ,	   0x1070108297800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU2_EN_IO0_INT_GPIO_W1C"    ,	   0x10701080b7800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU2_EN_IO1_INT_GPIO_W1C"    ,	   0x10701082b7800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU2_EN_IO0_INT_GPIO_W1S"    ,	   0x10701080a7800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU2_EN_IO1_INT_GPIO_W1S"    ,	   0x10701082a7800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU2_EN_IO0_INT_IO"          ,	   0x1070108094800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU2_EN_IO1_INT_IO"          ,	   0x1070108294800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU2_EN_IO0_INT_IO_W1C"      ,	   0x10701080b4800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU2_EN_IO1_INT_IO_W1C"      ,	   0x10701082b4800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU2_EN_IO0_INT_IO_W1S"      ,	   0x10701080a4800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU2_EN_IO1_INT_IO_W1S"      ,	   0x10701082a4800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU2_EN_IO0_INT_MBOX"        ,	   0x1070108098800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU2_EN_IO1_INT_MBOX"        ,	   0x1070108298800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU2_EN_IO0_INT_MBOX_W1C"    ,	   0x10701080b8800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU2_EN_IO1_INT_MBOX_W1C"    ,	   0x10701082b8800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU2_EN_IO0_INT_MBOX_W1S"    ,	   0x10701080a8800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU2_EN_IO1_INT_MBOX_W1S"    ,	   0x10701082a8800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU2_EN_IO0_INT_MEM"         ,	   0x1070108095800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU2_EN_IO1_INT_MEM"         ,	   0x1070108295800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU2_EN_IO0_INT_MEM_W1C"     ,	   0x10701080b5800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU2_EN_IO1_INT_MEM_W1C"     ,	   0x10701082b5800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU2_EN_IO0_INT_MEM_W1S"     ,	   0x10701080a5800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU2_EN_IO1_INT_MEM_W1S"     ,	   0x10701082a5800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU2_EN_IO0_INT_MIO"         ,	   0x1070108093800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU2_EN_IO1_INT_MIO"         ,	   0x1070108293800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU2_EN_IO0_INT_MIO_W1C"     ,	   0x10701080b3800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU2_EN_IO1_INT_MIO_W1C"     ,	   0x10701082b3800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU2_EN_IO0_INT_MIO_W1S"     ,	   0x10701080a3800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU2_EN_IO1_INT_MIO_W1S"     ,	   0x10701082a3800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU2_EN_IO0_INT_PKT"         ,	   0x1070108096800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU2_EN_IO1_INT_PKT"         ,	   0x1070108296800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU2_EN_IO0_INT_PKT_W1C"     ,	   0x10701080b6800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU2_EN_IO1_INT_PKT_W1C"     ,	   0x10701082b6800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU2_EN_IO0_INT_PKT_W1S"     ,	   0x10701080a6800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU2_EN_IO1_INT_PKT_W1S"     ,	   0x10701082a6800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU2_EN_IO0_INT_RML"         ,	   0x1070108092800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU2_EN_IO1_INT_RML"         ,	   0x1070108292800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU2_EN_IO0_INT_RML_W1C"     ,	   0x10701080b2800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU2_EN_IO1_INT_RML_W1C"     ,	   0x10701082b2800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU2_EN_IO0_INT_RML_W1S"     ,	   0x10701080a2800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU2_EN_IO1_INT_RML_W1S"     ,	   0x10701082a2800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU2_EN_IO0_INT_WDOG"        ,	   0x1070108091800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU2_EN_IO1_INT_WDOG"        ,	   0x1070108291800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU2_EN_IO0_INT_WDOG_W1C"    ,	   0x10701080b1800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU2_EN_IO1_INT_WDOG_W1C"    ,	   0x10701082b1800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU2_EN_IO0_INT_WDOG_W1S"    ,	   0x10701080a1800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU2_EN_IO1_INT_WDOG_W1S"    ,	   0x10701082a1800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU2_EN_IO0_INT_WRKQ"        ,	   0x1070108090800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU2_EN_IO1_INT_WRKQ"        ,	   0x1070108290800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU2_EN_IO0_INT_WRKQ_W1C"    ,	   0x10701080b0800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU2_EN_IO1_INT_WRKQ_W1C"    ,	   0x10701082b0800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU2_EN_IO0_INT_WRKQ_W1S"    ,	   0x10701080a0800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU2_EN_IO1_INT_WRKQ_W1S"    ,	   0x10701082a0800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU2_EN_PP0_IP2_GPIO"        ,	   0x1070100097000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP1_IP2_GPIO"        ,	   0x1070100297000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP2_IP2_GPIO"        ,	   0x1070100497000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP3_IP2_GPIO"        ,	   0x1070100697000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP4_IP2_GPIO"        ,	   0x1070100897000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP5_IP2_GPIO"        ,	   0x1070100a97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP6_IP2_GPIO"        ,	   0x1070100c97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP7_IP2_GPIO"        ,	   0x1070100e97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP8_IP2_GPIO"        ,	   0x1070101097000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP9_IP2_GPIO"        ,	   0x1070101297000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP10_IP2_GPIO"       ,	   0x1070101497000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP11_IP2_GPIO"       ,	   0x1070101697000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP12_IP2_GPIO"       ,	   0x1070101897000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP13_IP2_GPIO"       ,	   0x1070101a97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP14_IP2_GPIO"       ,	   0x1070101c97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP15_IP2_GPIO"       ,	   0x1070101e97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP16_IP2_GPIO"       ,	   0x1070102097000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP17_IP2_GPIO"       ,	   0x1070102297000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP18_IP2_GPIO"       ,	   0x1070102497000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP19_IP2_GPIO"       ,	   0x1070102697000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP20_IP2_GPIO"       ,	   0x1070102897000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP21_IP2_GPIO"       ,	   0x1070102a97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP22_IP2_GPIO"       ,	   0x1070102c97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP23_IP2_GPIO"       ,	   0x1070102e97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP24_IP2_GPIO"       ,	   0x1070103097000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP25_IP2_GPIO"       ,	   0x1070103297000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP26_IP2_GPIO"       ,	   0x1070103497000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP27_IP2_GPIO"       ,	   0x1070103697000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP28_IP2_GPIO"       ,	   0x1070103897000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP29_IP2_GPIO"       ,	   0x1070103a97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP30_IP2_GPIO"       ,	   0x1070103c97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP31_IP2_GPIO"       ,	   0x1070103e97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP0_IP2_GPIO_W1C"    ,	   0x10701000b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP1_IP2_GPIO_W1C"    ,	   0x10701002b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP2_IP2_GPIO_W1C"    ,	   0x10701004b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP3_IP2_GPIO_W1C"    ,	   0x10701006b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP4_IP2_GPIO_W1C"    ,	   0x10701008b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP5_IP2_GPIO_W1C"    ,	   0x1070100ab7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP6_IP2_GPIO_W1C"    ,	   0x1070100cb7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP7_IP2_GPIO_W1C"    ,	   0x1070100eb7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP8_IP2_GPIO_W1C"    ,	   0x10701010b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP9_IP2_GPIO_W1C"    ,	   0x10701012b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP10_IP2_GPIO_W1C"   ,	   0x10701014b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP11_IP2_GPIO_W1C"   ,	   0x10701016b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP12_IP2_GPIO_W1C"   ,	   0x10701018b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP13_IP2_GPIO_W1C"   ,	   0x1070101ab7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP14_IP2_GPIO_W1C"   ,	   0x1070101cb7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP15_IP2_GPIO_W1C"   ,	   0x1070101eb7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP16_IP2_GPIO_W1C"   ,	   0x10701020b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP17_IP2_GPIO_W1C"   ,	   0x10701022b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP18_IP2_GPIO_W1C"   ,	   0x10701024b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP19_IP2_GPIO_W1C"   ,	   0x10701026b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP20_IP2_GPIO_W1C"   ,	   0x10701028b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP21_IP2_GPIO_W1C"   ,	   0x1070102ab7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP22_IP2_GPIO_W1C"   ,	   0x1070102cb7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP23_IP2_GPIO_W1C"   ,	   0x1070102eb7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP24_IP2_GPIO_W1C"   ,	   0x10701030b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP25_IP2_GPIO_W1C"   ,	   0x10701032b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP26_IP2_GPIO_W1C"   ,	   0x10701034b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP27_IP2_GPIO_W1C"   ,	   0x10701036b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP28_IP2_GPIO_W1C"   ,	   0x10701038b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP29_IP2_GPIO_W1C"   ,	   0x1070103ab7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP30_IP2_GPIO_W1C"   ,	   0x1070103cb7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP31_IP2_GPIO_W1C"   ,	   0x1070103eb7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP0_IP2_GPIO_W1S"    ,	   0x10701000a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP1_IP2_GPIO_W1S"    ,	   0x10701002a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP2_IP2_GPIO_W1S"    ,	   0x10701004a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP3_IP2_GPIO_W1S"    ,	   0x10701006a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP4_IP2_GPIO_W1S"    ,	   0x10701008a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP5_IP2_GPIO_W1S"    ,	   0x1070100aa7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP6_IP2_GPIO_W1S"    ,	   0x1070100ca7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP7_IP2_GPIO_W1S"    ,	   0x1070100ea7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP8_IP2_GPIO_W1S"    ,	   0x10701010a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP9_IP2_GPIO_W1S"    ,	   0x10701012a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP10_IP2_GPIO_W1S"   ,	   0x10701014a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP11_IP2_GPIO_W1S"   ,	   0x10701016a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP12_IP2_GPIO_W1S"   ,	   0x10701018a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP13_IP2_GPIO_W1S"   ,	   0x1070101aa7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP14_IP2_GPIO_W1S"   ,	   0x1070101ca7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP15_IP2_GPIO_W1S"   ,	   0x1070101ea7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP16_IP2_GPIO_W1S"   ,	   0x10701020a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP17_IP2_GPIO_W1S"   ,	   0x10701022a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP18_IP2_GPIO_W1S"   ,	   0x10701024a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP19_IP2_GPIO_W1S"   ,	   0x10701026a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP20_IP2_GPIO_W1S"   ,	   0x10701028a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP21_IP2_GPIO_W1S"   ,	   0x1070102aa7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP22_IP2_GPIO_W1S"   ,	   0x1070102ca7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP23_IP2_GPIO_W1S"   ,	   0x1070102ea7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP24_IP2_GPIO_W1S"   ,	   0x10701030a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP25_IP2_GPIO_W1S"   ,	   0x10701032a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP26_IP2_GPIO_W1S"   ,	   0x10701034a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP27_IP2_GPIO_W1S"   ,	   0x10701036a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP28_IP2_GPIO_W1S"   ,	   0x10701038a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP29_IP2_GPIO_W1S"   ,	   0x1070103aa7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP30_IP2_GPIO_W1S"   ,	   0x1070103ca7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP31_IP2_GPIO_W1S"   ,	   0x1070103ea7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP0_IP2_IO"          ,	   0x1070100094000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP1_IP2_IO"          ,	   0x1070100294000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP2_IP2_IO"          ,	   0x1070100494000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP3_IP2_IO"          ,	   0x1070100694000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP4_IP2_IO"          ,	   0x1070100894000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP5_IP2_IO"          ,	   0x1070100a94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP6_IP2_IO"          ,	   0x1070100c94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP7_IP2_IO"          ,	   0x1070100e94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP8_IP2_IO"          ,	   0x1070101094000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP9_IP2_IO"          ,	   0x1070101294000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP10_IP2_IO"         ,	   0x1070101494000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP11_IP2_IO"         ,	   0x1070101694000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP12_IP2_IO"         ,	   0x1070101894000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP13_IP2_IO"         ,	   0x1070101a94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP14_IP2_IO"         ,	   0x1070101c94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP15_IP2_IO"         ,	   0x1070101e94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP16_IP2_IO"         ,	   0x1070102094000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP17_IP2_IO"         ,	   0x1070102294000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP18_IP2_IO"         ,	   0x1070102494000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP19_IP2_IO"         ,	   0x1070102694000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP20_IP2_IO"         ,	   0x1070102894000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP21_IP2_IO"         ,	   0x1070102a94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP22_IP2_IO"         ,	   0x1070102c94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP23_IP2_IO"         ,	   0x1070102e94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP24_IP2_IO"         ,	   0x1070103094000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP25_IP2_IO"         ,	   0x1070103294000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP26_IP2_IO"         ,	   0x1070103494000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP27_IP2_IO"         ,	   0x1070103694000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP28_IP2_IO"         ,	   0x1070103894000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP29_IP2_IO"         ,	   0x1070103a94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP30_IP2_IO"         ,	   0x1070103c94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP31_IP2_IO"         ,	   0x1070103e94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP0_IP2_IO_W1C"      ,	   0x10701000b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP1_IP2_IO_W1C"      ,	   0x10701002b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP2_IP2_IO_W1C"      ,	   0x10701004b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP3_IP2_IO_W1C"      ,	   0x10701006b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP4_IP2_IO_W1C"      ,	   0x10701008b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP5_IP2_IO_W1C"      ,	   0x1070100ab4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP6_IP2_IO_W1C"      ,	   0x1070100cb4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP7_IP2_IO_W1C"      ,	   0x1070100eb4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP8_IP2_IO_W1C"      ,	   0x10701010b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP9_IP2_IO_W1C"      ,	   0x10701012b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP10_IP2_IO_W1C"     ,	   0x10701014b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP11_IP2_IO_W1C"     ,	   0x10701016b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP12_IP2_IO_W1C"     ,	   0x10701018b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP13_IP2_IO_W1C"     ,	   0x1070101ab4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP14_IP2_IO_W1C"     ,	   0x1070101cb4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP15_IP2_IO_W1C"     ,	   0x1070101eb4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP16_IP2_IO_W1C"     ,	   0x10701020b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP17_IP2_IO_W1C"     ,	   0x10701022b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP18_IP2_IO_W1C"     ,	   0x10701024b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP19_IP2_IO_W1C"     ,	   0x10701026b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP20_IP2_IO_W1C"     ,	   0x10701028b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP21_IP2_IO_W1C"     ,	   0x1070102ab4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP22_IP2_IO_W1C"     ,	   0x1070102cb4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP23_IP2_IO_W1C"     ,	   0x1070102eb4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP24_IP2_IO_W1C"     ,	   0x10701030b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP25_IP2_IO_W1C"     ,	   0x10701032b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP26_IP2_IO_W1C"     ,	   0x10701034b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP27_IP2_IO_W1C"     ,	   0x10701036b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP28_IP2_IO_W1C"     ,	   0x10701038b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP29_IP2_IO_W1C"     ,	   0x1070103ab4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP30_IP2_IO_W1C"     ,	   0x1070103cb4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP31_IP2_IO_W1C"     ,	   0x1070103eb4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP0_IP2_IO_W1S"      ,	   0x10701000a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP1_IP2_IO_W1S"      ,	   0x10701002a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP2_IP2_IO_W1S"      ,	   0x10701004a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP3_IP2_IO_W1S"      ,	   0x10701006a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP4_IP2_IO_W1S"      ,	   0x10701008a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP5_IP2_IO_W1S"      ,	   0x1070100aa4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP6_IP2_IO_W1S"      ,	   0x1070100ca4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP7_IP2_IO_W1S"      ,	   0x1070100ea4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP8_IP2_IO_W1S"      ,	   0x10701010a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP9_IP2_IO_W1S"      ,	   0x10701012a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP10_IP2_IO_W1S"     ,	   0x10701014a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP11_IP2_IO_W1S"     ,	   0x10701016a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP12_IP2_IO_W1S"     ,	   0x10701018a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP13_IP2_IO_W1S"     ,	   0x1070101aa4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP14_IP2_IO_W1S"     ,	   0x1070101ca4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP15_IP2_IO_W1S"     ,	   0x1070101ea4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP16_IP2_IO_W1S"     ,	   0x10701020a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP17_IP2_IO_W1S"     ,	   0x10701022a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP18_IP2_IO_W1S"     ,	   0x10701024a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP19_IP2_IO_W1S"     ,	   0x10701026a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP20_IP2_IO_W1S"     ,	   0x10701028a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP21_IP2_IO_W1S"     ,	   0x1070102aa4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP22_IP2_IO_W1S"     ,	   0x1070102ca4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP23_IP2_IO_W1S"     ,	   0x1070102ea4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP24_IP2_IO_W1S"     ,	   0x10701030a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP25_IP2_IO_W1S"     ,	   0x10701032a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP26_IP2_IO_W1S"     ,	   0x10701034a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP27_IP2_IO_W1S"     ,	   0x10701036a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP28_IP2_IO_W1S"     ,	   0x10701038a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP29_IP2_IO_W1S"     ,	   0x1070103aa4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP30_IP2_IO_W1S"     ,	   0x1070103ca4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP31_IP2_IO_W1S"     ,	   0x1070103ea4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP0_IP2_MBOX"        ,	   0x1070100098000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP1_IP2_MBOX"        ,	   0x1070100298000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP2_IP2_MBOX"        ,	   0x1070100498000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP3_IP2_MBOX"        ,	   0x1070100698000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP4_IP2_MBOX"        ,	   0x1070100898000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP5_IP2_MBOX"        ,	   0x1070100a98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP6_IP2_MBOX"        ,	   0x1070100c98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP7_IP2_MBOX"        ,	   0x1070100e98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP8_IP2_MBOX"        ,	   0x1070101098000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP9_IP2_MBOX"        ,	   0x1070101298000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP10_IP2_MBOX"       ,	   0x1070101498000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP11_IP2_MBOX"       ,	   0x1070101698000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP12_IP2_MBOX"       ,	   0x1070101898000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP13_IP2_MBOX"       ,	   0x1070101a98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP14_IP2_MBOX"       ,	   0x1070101c98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP15_IP2_MBOX"       ,	   0x1070101e98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP16_IP2_MBOX"       ,	   0x1070102098000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP17_IP2_MBOX"       ,	   0x1070102298000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP18_IP2_MBOX"       ,	   0x1070102498000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP19_IP2_MBOX"       ,	   0x1070102698000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP20_IP2_MBOX"       ,	   0x1070102898000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP21_IP2_MBOX"       ,	   0x1070102a98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP22_IP2_MBOX"       ,	   0x1070102c98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP23_IP2_MBOX"       ,	   0x1070102e98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP24_IP2_MBOX"       ,	   0x1070103098000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP25_IP2_MBOX"       ,	   0x1070103298000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP26_IP2_MBOX"       ,	   0x1070103498000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP27_IP2_MBOX"       ,	   0x1070103698000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP28_IP2_MBOX"       ,	   0x1070103898000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP29_IP2_MBOX"       ,	   0x1070103a98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP30_IP2_MBOX"       ,	   0x1070103c98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP31_IP2_MBOX"       ,	   0x1070103e98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP0_IP2_MBOX_W1C"    ,	   0x10701000b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP1_IP2_MBOX_W1C"    ,	   0x10701002b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP2_IP2_MBOX_W1C"    ,	   0x10701004b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP3_IP2_MBOX_W1C"    ,	   0x10701006b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP4_IP2_MBOX_W1C"    ,	   0x10701008b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP5_IP2_MBOX_W1C"    ,	   0x1070100ab8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP6_IP2_MBOX_W1C"    ,	   0x1070100cb8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP7_IP2_MBOX_W1C"    ,	   0x1070100eb8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP8_IP2_MBOX_W1C"    ,	   0x10701010b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP9_IP2_MBOX_W1C"    ,	   0x10701012b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP10_IP2_MBOX_W1C"   ,	   0x10701014b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP11_IP2_MBOX_W1C"   ,	   0x10701016b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP12_IP2_MBOX_W1C"   ,	   0x10701018b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP13_IP2_MBOX_W1C"   ,	   0x1070101ab8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP14_IP2_MBOX_W1C"   ,	   0x1070101cb8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP15_IP2_MBOX_W1C"   ,	   0x1070101eb8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP16_IP2_MBOX_W1C"   ,	   0x10701020b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP17_IP2_MBOX_W1C"   ,	   0x10701022b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP18_IP2_MBOX_W1C"   ,	   0x10701024b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP19_IP2_MBOX_W1C"   ,	   0x10701026b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP20_IP2_MBOX_W1C"   ,	   0x10701028b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP21_IP2_MBOX_W1C"   ,	   0x1070102ab8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP22_IP2_MBOX_W1C"   ,	   0x1070102cb8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP23_IP2_MBOX_W1C"   ,	   0x1070102eb8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP24_IP2_MBOX_W1C"   ,	   0x10701030b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP25_IP2_MBOX_W1C"   ,	   0x10701032b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP26_IP2_MBOX_W1C"   ,	   0x10701034b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP27_IP2_MBOX_W1C"   ,	   0x10701036b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP28_IP2_MBOX_W1C"   ,	   0x10701038b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP29_IP2_MBOX_W1C"   ,	   0x1070103ab8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP30_IP2_MBOX_W1C"   ,	   0x1070103cb8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP31_IP2_MBOX_W1C"   ,	   0x1070103eb8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP0_IP2_MBOX_W1S"    ,	   0x10701000a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP1_IP2_MBOX_W1S"    ,	   0x10701002a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP2_IP2_MBOX_W1S"    ,	   0x10701004a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP3_IP2_MBOX_W1S"    ,	   0x10701006a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP4_IP2_MBOX_W1S"    ,	   0x10701008a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP5_IP2_MBOX_W1S"    ,	   0x1070100aa8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP6_IP2_MBOX_W1S"    ,	   0x1070100ca8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP7_IP2_MBOX_W1S"    ,	   0x1070100ea8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP8_IP2_MBOX_W1S"    ,	   0x10701010a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP9_IP2_MBOX_W1S"    ,	   0x10701012a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP10_IP2_MBOX_W1S"   ,	   0x10701014a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP11_IP2_MBOX_W1S"   ,	   0x10701016a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP12_IP2_MBOX_W1S"   ,	   0x10701018a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP13_IP2_MBOX_W1S"   ,	   0x1070101aa8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP14_IP2_MBOX_W1S"   ,	   0x1070101ca8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP15_IP2_MBOX_W1S"   ,	   0x1070101ea8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP16_IP2_MBOX_W1S"   ,	   0x10701020a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP17_IP2_MBOX_W1S"   ,	   0x10701022a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP18_IP2_MBOX_W1S"   ,	   0x10701024a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP19_IP2_MBOX_W1S"   ,	   0x10701026a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP20_IP2_MBOX_W1S"   ,	   0x10701028a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP21_IP2_MBOX_W1S"   ,	   0x1070102aa8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP22_IP2_MBOX_W1S"   ,	   0x1070102ca8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP23_IP2_MBOX_W1S"   ,	   0x1070102ea8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP24_IP2_MBOX_W1S"   ,	   0x10701030a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP25_IP2_MBOX_W1S"   ,	   0x10701032a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP26_IP2_MBOX_W1S"   ,	   0x10701034a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP27_IP2_MBOX_W1S"   ,	   0x10701036a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP28_IP2_MBOX_W1S"   ,	   0x10701038a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP29_IP2_MBOX_W1S"   ,	   0x1070103aa8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP30_IP2_MBOX_W1S"   ,	   0x1070103ca8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP31_IP2_MBOX_W1S"   ,	   0x1070103ea8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP0_IP2_MEM"         ,	   0x1070100095000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP1_IP2_MEM"         ,	   0x1070100295000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP2_IP2_MEM"         ,	   0x1070100495000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP3_IP2_MEM"         ,	   0x1070100695000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP4_IP2_MEM"         ,	   0x1070100895000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP5_IP2_MEM"         ,	   0x1070100a95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP6_IP2_MEM"         ,	   0x1070100c95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP7_IP2_MEM"         ,	   0x1070100e95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP8_IP2_MEM"         ,	   0x1070101095000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP9_IP2_MEM"         ,	   0x1070101295000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP10_IP2_MEM"        ,	   0x1070101495000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP11_IP2_MEM"        ,	   0x1070101695000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP12_IP2_MEM"        ,	   0x1070101895000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP13_IP2_MEM"        ,	   0x1070101a95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP14_IP2_MEM"        ,	   0x1070101c95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP15_IP2_MEM"        ,	   0x1070101e95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP16_IP2_MEM"        ,	   0x1070102095000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP17_IP2_MEM"        ,	   0x1070102295000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP18_IP2_MEM"        ,	   0x1070102495000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP19_IP2_MEM"        ,	   0x1070102695000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP20_IP2_MEM"        ,	   0x1070102895000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP21_IP2_MEM"        ,	   0x1070102a95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP22_IP2_MEM"        ,	   0x1070102c95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP23_IP2_MEM"        ,	   0x1070102e95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP24_IP2_MEM"        ,	   0x1070103095000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP25_IP2_MEM"        ,	   0x1070103295000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP26_IP2_MEM"        ,	   0x1070103495000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP27_IP2_MEM"        ,	   0x1070103695000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP28_IP2_MEM"        ,	   0x1070103895000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP29_IP2_MEM"        ,	   0x1070103a95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP30_IP2_MEM"        ,	   0x1070103c95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP31_IP2_MEM"        ,	   0x1070103e95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP0_IP2_MEM_W1C"     ,	   0x10701000b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP1_IP2_MEM_W1C"     ,	   0x10701002b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP2_IP2_MEM_W1C"     ,	   0x10701004b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP3_IP2_MEM_W1C"     ,	   0x10701006b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP4_IP2_MEM_W1C"     ,	   0x10701008b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP5_IP2_MEM_W1C"     ,	   0x1070100ab5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP6_IP2_MEM_W1C"     ,	   0x1070100cb5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP7_IP2_MEM_W1C"     ,	   0x1070100eb5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP8_IP2_MEM_W1C"     ,	   0x10701010b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP9_IP2_MEM_W1C"     ,	   0x10701012b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP10_IP2_MEM_W1C"    ,	   0x10701014b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP11_IP2_MEM_W1C"    ,	   0x10701016b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP12_IP2_MEM_W1C"    ,	   0x10701018b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP13_IP2_MEM_W1C"    ,	   0x1070101ab5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP14_IP2_MEM_W1C"    ,	   0x1070101cb5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP15_IP2_MEM_W1C"    ,	   0x1070101eb5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP16_IP2_MEM_W1C"    ,	   0x10701020b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP17_IP2_MEM_W1C"    ,	   0x10701022b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP18_IP2_MEM_W1C"    ,	   0x10701024b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP19_IP2_MEM_W1C"    ,	   0x10701026b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP20_IP2_MEM_W1C"    ,	   0x10701028b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP21_IP2_MEM_W1C"    ,	   0x1070102ab5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP22_IP2_MEM_W1C"    ,	   0x1070102cb5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP23_IP2_MEM_W1C"    ,	   0x1070102eb5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP24_IP2_MEM_W1C"    ,	   0x10701030b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP25_IP2_MEM_W1C"    ,	   0x10701032b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP26_IP2_MEM_W1C"    ,	   0x10701034b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP27_IP2_MEM_W1C"    ,	   0x10701036b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP28_IP2_MEM_W1C"    ,	   0x10701038b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP29_IP2_MEM_W1C"    ,	   0x1070103ab5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP30_IP2_MEM_W1C"    ,	   0x1070103cb5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP31_IP2_MEM_W1C"    ,	   0x1070103eb5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP0_IP2_MEM_W1S"     ,	   0x10701000a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP1_IP2_MEM_W1S"     ,	   0x10701002a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP2_IP2_MEM_W1S"     ,	   0x10701004a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP3_IP2_MEM_W1S"     ,	   0x10701006a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP4_IP2_MEM_W1S"     ,	   0x10701008a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP5_IP2_MEM_W1S"     ,	   0x1070100aa5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP6_IP2_MEM_W1S"     ,	   0x1070100ca5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP7_IP2_MEM_W1S"     ,	   0x1070100ea5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP8_IP2_MEM_W1S"     ,	   0x10701010a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP9_IP2_MEM_W1S"     ,	   0x10701012a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP10_IP2_MEM_W1S"    ,	   0x10701014a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP11_IP2_MEM_W1S"    ,	   0x10701016a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP12_IP2_MEM_W1S"    ,	   0x10701018a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP13_IP2_MEM_W1S"    ,	   0x1070101aa5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP14_IP2_MEM_W1S"    ,	   0x1070101ca5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP15_IP2_MEM_W1S"    ,	   0x1070101ea5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP16_IP2_MEM_W1S"    ,	   0x10701020a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP17_IP2_MEM_W1S"    ,	   0x10701022a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP18_IP2_MEM_W1S"    ,	   0x10701024a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP19_IP2_MEM_W1S"    ,	   0x10701026a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP20_IP2_MEM_W1S"    ,	   0x10701028a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP21_IP2_MEM_W1S"    ,	   0x1070102aa5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP22_IP2_MEM_W1S"    ,	   0x1070102ca5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP23_IP2_MEM_W1S"    ,	   0x1070102ea5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP24_IP2_MEM_W1S"    ,	   0x10701030a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP25_IP2_MEM_W1S"    ,	   0x10701032a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP26_IP2_MEM_W1S"    ,	   0x10701034a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP27_IP2_MEM_W1S"    ,	   0x10701036a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP28_IP2_MEM_W1S"    ,	   0x10701038a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP29_IP2_MEM_W1S"    ,	   0x1070103aa5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP30_IP2_MEM_W1S"    ,	   0x1070103ca5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP31_IP2_MEM_W1S"    ,	   0x1070103ea5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP0_IP2_MIO"         ,	   0x1070100093000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP1_IP2_MIO"         ,	   0x1070100293000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP2_IP2_MIO"         ,	   0x1070100493000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP3_IP2_MIO"         ,	   0x1070100693000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP4_IP2_MIO"         ,	   0x1070100893000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP5_IP2_MIO"         ,	   0x1070100a93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP6_IP2_MIO"         ,	   0x1070100c93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP7_IP2_MIO"         ,	   0x1070100e93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP8_IP2_MIO"         ,	   0x1070101093000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP9_IP2_MIO"         ,	   0x1070101293000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP10_IP2_MIO"        ,	   0x1070101493000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP11_IP2_MIO"        ,	   0x1070101693000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP12_IP2_MIO"        ,	   0x1070101893000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP13_IP2_MIO"        ,	   0x1070101a93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP14_IP2_MIO"        ,	   0x1070101c93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP15_IP2_MIO"        ,	   0x1070101e93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP16_IP2_MIO"        ,	   0x1070102093000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP17_IP2_MIO"        ,	   0x1070102293000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP18_IP2_MIO"        ,	   0x1070102493000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP19_IP2_MIO"        ,	   0x1070102693000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP20_IP2_MIO"        ,	   0x1070102893000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP21_IP2_MIO"        ,	   0x1070102a93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP22_IP2_MIO"        ,	   0x1070102c93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP23_IP2_MIO"        ,	   0x1070102e93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP24_IP2_MIO"        ,	   0x1070103093000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP25_IP2_MIO"        ,	   0x1070103293000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP26_IP2_MIO"        ,	   0x1070103493000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP27_IP2_MIO"        ,	   0x1070103693000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP28_IP2_MIO"        ,	   0x1070103893000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP29_IP2_MIO"        ,	   0x1070103a93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP30_IP2_MIO"        ,	   0x1070103c93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP31_IP2_MIO"        ,	   0x1070103e93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP0_IP2_MIO_W1C"     ,	   0x10701000b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP1_IP2_MIO_W1C"     ,	   0x10701002b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP2_IP2_MIO_W1C"     ,	   0x10701004b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP3_IP2_MIO_W1C"     ,	   0x10701006b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP4_IP2_MIO_W1C"     ,	   0x10701008b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP5_IP2_MIO_W1C"     ,	   0x1070100ab3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP6_IP2_MIO_W1C"     ,	   0x1070100cb3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP7_IP2_MIO_W1C"     ,	   0x1070100eb3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP8_IP2_MIO_W1C"     ,	   0x10701010b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP9_IP2_MIO_W1C"     ,	   0x10701012b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP10_IP2_MIO_W1C"    ,	   0x10701014b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP11_IP2_MIO_W1C"    ,	   0x10701016b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP12_IP2_MIO_W1C"    ,	   0x10701018b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP13_IP2_MIO_W1C"    ,	   0x1070101ab3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP14_IP2_MIO_W1C"    ,	   0x1070101cb3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP15_IP2_MIO_W1C"    ,	   0x1070101eb3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP16_IP2_MIO_W1C"    ,	   0x10701020b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP17_IP2_MIO_W1C"    ,	   0x10701022b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP18_IP2_MIO_W1C"    ,	   0x10701024b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP19_IP2_MIO_W1C"    ,	   0x10701026b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP20_IP2_MIO_W1C"    ,	   0x10701028b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP21_IP2_MIO_W1C"    ,	   0x1070102ab3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP22_IP2_MIO_W1C"    ,	   0x1070102cb3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP23_IP2_MIO_W1C"    ,	   0x1070102eb3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP24_IP2_MIO_W1C"    ,	   0x10701030b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP25_IP2_MIO_W1C"    ,	   0x10701032b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP26_IP2_MIO_W1C"    ,	   0x10701034b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP27_IP2_MIO_W1C"    ,	   0x10701036b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP28_IP2_MIO_W1C"    ,	   0x10701038b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP29_IP2_MIO_W1C"    ,	   0x1070103ab3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP30_IP2_MIO_W1C"    ,	   0x1070103cb3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP31_IP2_MIO_W1C"    ,	   0x1070103eb3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP0_IP2_MIO_W1S"     ,	   0x10701000a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP1_IP2_MIO_W1S"     ,	   0x10701002a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP2_IP2_MIO_W1S"     ,	   0x10701004a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP3_IP2_MIO_W1S"     ,	   0x10701006a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP4_IP2_MIO_W1S"     ,	   0x10701008a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP5_IP2_MIO_W1S"     ,	   0x1070100aa3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP6_IP2_MIO_W1S"     ,	   0x1070100ca3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP7_IP2_MIO_W1S"     ,	   0x1070100ea3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP8_IP2_MIO_W1S"     ,	   0x10701010a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP9_IP2_MIO_W1S"     ,	   0x10701012a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP10_IP2_MIO_W1S"    ,	   0x10701014a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP11_IP2_MIO_W1S"    ,	   0x10701016a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP12_IP2_MIO_W1S"    ,	   0x10701018a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP13_IP2_MIO_W1S"    ,	   0x1070101aa3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP14_IP2_MIO_W1S"    ,	   0x1070101ca3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP15_IP2_MIO_W1S"    ,	   0x1070101ea3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP16_IP2_MIO_W1S"    ,	   0x10701020a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP17_IP2_MIO_W1S"    ,	   0x10701022a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP18_IP2_MIO_W1S"    ,	   0x10701024a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP19_IP2_MIO_W1S"    ,	   0x10701026a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP20_IP2_MIO_W1S"    ,	   0x10701028a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP21_IP2_MIO_W1S"    ,	   0x1070102aa3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP22_IP2_MIO_W1S"    ,	   0x1070102ca3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP23_IP2_MIO_W1S"    ,	   0x1070102ea3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP24_IP2_MIO_W1S"    ,	   0x10701030a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP25_IP2_MIO_W1S"    ,	   0x10701032a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP26_IP2_MIO_W1S"    ,	   0x10701034a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP27_IP2_MIO_W1S"    ,	   0x10701036a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP28_IP2_MIO_W1S"    ,	   0x10701038a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP29_IP2_MIO_W1S"    ,	   0x1070103aa3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP30_IP2_MIO_W1S"    ,	   0x1070103ca3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP31_IP2_MIO_W1S"    ,	   0x1070103ea3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP0_IP2_PKT"         ,	   0x1070100096000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP1_IP2_PKT"         ,	   0x1070100296000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP2_IP2_PKT"         ,	   0x1070100496000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP3_IP2_PKT"         ,	   0x1070100696000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP4_IP2_PKT"         ,	   0x1070100896000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP5_IP2_PKT"         ,	   0x1070100a96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP6_IP2_PKT"         ,	   0x1070100c96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP7_IP2_PKT"         ,	   0x1070100e96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP8_IP2_PKT"         ,	   0x1070101096000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP9_IP2_PKT"         ,	   0x1070101296000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP10_IP2_PKT"        ,	   0x1070101496000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP11_IP2_PKT"        ,	   0x1070101696000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP12_IP2_PKT"        ,	   0x1070101896000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP13_IP2_PKT"        ,	   0x1070101a96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP14_IP2_PKT"        ,	   0x1070101c96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP15_IP2_PKT"        ,	   0x1070101e96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP16_IP2_PKT"        ,	   0x1070102096000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP17_IP2_PKT"        ,	   0x1070102296000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP18_IP2_PKT"        ,	   0x1070102496000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP19_IP2_PKT"        ,	   0x1070102696000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP20_IP2_PKT"        ,	   0x1070102896000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP21_IP2_PKT"        ,	   0x1070102a96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP22_IP2_PKT"        ,	   0x1070102c96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP23_IP2_PKT"        ,	   0x1070102e96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP24_IP2_PKT"        ,	   0x1070103096000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP25_IP2_PKT"        ,	   0x1070103296000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP26_IP2_PKT"        ,	   0x1070103496000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP27_IP2_PKT"        ,	   0x1070103696000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP28_IP2_PKT"        ,	   0x1070103896000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP29_IP2_PKT"        ,	   0x1070103a96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP30_IP2_PKT"        ,	   0x1070103c96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP31_IP2_PKT"        ,	   0x1070103e96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP0_IP2_PKT_W1C"     ,	   0x10701000b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP1_IP2_PKT_W1C"     ,	   0x10701002b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP2_IP2_PKT_W1C"     ,	   0x10701004b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP3_IP2_PKT_W1C"     ,	   0x10701006b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP4_IP2_PKT_W1C"     ,	   0x10701008b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP5_IP2_PKT_W1C"     ,	   0x1070100ab6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP6_IP2_PKT_W1C"     ,	   0x1070100cb6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP7_IP2_PKT_W1C"     ,	   0x1070100eb6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP8_IP2_PKT_W1C"     ,	   0x10701010b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP9_IP2_PKT_W1C"     ,	   0x10701012b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP10_IP2_PKT_W1C"    ,	   0x10701014b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP11_IP2_PKT_W1C"    ,	   0x10701016b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP12_IP2_PKT_W1C"    ,	   0x10701018b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP13_IP2_PKT_W1C"    ,	   0x1070101ab6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP14_IP2_PKT_W1C"    ,	   0x1070101cb6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP15_IP2_PKT_W1C"    ,	   0x1070101eb6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP16_IP2_PKT_W1C"    ,	   0x10701020b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP17_IP2_PKT_W1C"    ,	   0x10701022b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP18_IP2_PKT_W1C"    ,	   0x10701024b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP19_IP2_PKT_W1C"    ,	   0x10701026b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP20_IP2_PKT_W1C"    ,	   0x10701028b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP21_IP2_PKT_W1C"    ,	   0x1070102ab6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP22_IP2_PKT_W1C"    ,	   0x1070102cb6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP23_IP2_PKT_W1C"    ,	   0x1070102eb6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP24_IP2_PKT_W1C"    ,	   0x10701030b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP25_IP2_PKT_W1C"    ,	   0x10701032b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP26_IP2_PKT_W1C"    ,	   0x10701034b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP27_IP2_PKT_W1C"    ,	   0x10701036b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP28_IP2_PKT_W1C"    ,	   0x10701038b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP29_IP2_PKT_W1C"    ,	   0x1070103ab6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP30_IP2_PKT_W1C"    ,	   0x1070103cb6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP31_IP2_PKT_W1C"    ,	   0x1070103eb6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP0_IP2_PKT_W1S"     ,	   0x10701000a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP1_IP2_PKT_W1S"     ,	   0x10701002a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP2_IP2_PKT_W1S"     ,	   0x10701004a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP3_IP2_PKT_W1S"     ,	   0x10701006a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP4_IP2_PKT_W1S"     ,	   0x10701008a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP5_IP2_PKT_W1S"     ,	   0x1070100aa6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP6_IP2_PKT_W1S"     ,	   0x1070100ca6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP7_IP2_PKT_W1S"     ,	   0x1070100ea6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP8_IP2_PKT_W1S"     ,	   0x10701010a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP9_IP2_PKT_W1S"     ,	   0x10701012a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP10_IP2_PKT_W1S"    ,	   0x10701014a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP11_IP2_PKT_W1S"    ,	   0x10701016a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP12_IP2_PKT_W1S"    ,	   0x10701018a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP13_IP2_PKT_W1S"    ,	   0x1070101aa6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP14_IP2_PKT_W1S"    ,	   0x1070101ca6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP15_IP2_PKT_W1S"    ,	   0x1070101ea6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP16_IP2_PKT_W1S"    ,	   0x10701020a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP17_IP2_PKT_W1S"    ,	   0x10701022a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP18_IP2_PKT_W1S"    ,	   0x10701024a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP19_IP2_PKT_W1S"    ,	   0x10701026a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP20_IP2_PKT_W1S"    ,	   0x10701028a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP21_IP2_PKT_W1S"    ,	   0x1070102aa6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP22_IP2_PKT_W1S"    ,	   0x1070102ca6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP23_IP2_PKT_W1S"    ,	   0x1070102ea6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP24_IP2_PKT_W1S"    ,	   0x10701030a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP25_IP2_PKT_W1S"    ,	   0x10701032a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP26_IP2_PKT_W1S"    ,	   0x10701034a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP27_IP2_PKT_W1S"    ,	   0x10701036a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP28_IP2_PKT_W1S"    ,	   0x10701038a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP29_IP2_PKT_W1S"    ,	   0x1070103aa6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP30_IP2_PKT_W1S"    ,	   0x1070103ca6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP31_IP2_PKT_W1S"    ,	   0x1070103ea6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP0_IP2_RML"         ,	   0x1070100092000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP1_IP2_RML"         ,	   0x1070100292000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP2_IP2_RML"         ,	   0x1070100492000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP3_IP2_RML"         ,	   0x1070100692000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP4_IP2_RML"         ,	   0x1070100892000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP5_IP2_RML"         ,	   0x1070100a92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP6_IP2_RML"         ,	   0x1070100c92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP7_IP2_RML"         ,	   0x1070100e92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP8_IP2_RML"         ,	   0x1070101092000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP9_IP2_RML"         ,	   0x1070101292000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP10_IP2_RML"        ,	   0x1070101492000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP11_IP2_RML"        ,	   0x1070101692000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP12_IP2_RML"        ,	   0x1070101892000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP13_IP2_RML"        ,	   0x1070101a92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP14_IP2_RML"        ,	   0x1070101c92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP15_IP2_RML"        ,	   0x1070101e92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP16_IP2_RML"        ,	   0x1070102092000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP17_IP2_RML"        ,	   0x1070102292000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP18_IP2_RML"        ,	   0x1070102492000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP19_IP2_RML"        ,	   0x1070102692000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP20_IP2_RML"        ,	   0x1070102892000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP21_IP2_RML"        ,	   0x1070102a92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP22_IP2_RML"        ,	   0x1070102c92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP23_IP2_RML"        ,	   0x1070102e92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP24_IP2_RML"        ,	   0x1070103092000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP25_IP2_RML"        ,	   0x1070103292000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP26_IP2_RML"        ,	   0x1070103492000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP27_IP2_RML"        ,	   0x1070103692000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP28_IP2_RML"        ,	   0x1070103892000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP29_IP2_RML"        ,	   0x1070103a92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP30_IP2_RML"        ,	   0x1070103c92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP31_IP2_RML"        ,	   0x1070103e92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP0_IP2_RML_W1C"     ,	   0x10701000b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP1_IP2_RML_W1C"     ,	   0x10701002b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP2_IP2_RML_W1C"     ,	   0x10701004b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP3_IP2_RML_W1C"     ,	   0x10701006b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP4_IP2_RML_W1C"     ,	   0x10701008b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP5_IP2_RML_W1C"     ,	   0x1070100ab2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP6_IP2_RML_W1C"     ,	   0x1070100cb2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP7_IP2_RML_W1C"     ,	   0x1070100eb2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP8_IP2_RML_W1C"     ,	   0x10701010b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP9_IP2_RML_W1C"     ,	   0x10701012b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP10_IP2_RML_W1C"    ,	   0x10701014b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP11_IP2_RML_W1C"    ,	   0x10701016b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP12_IP2_RML_W1C"    ,	   0x10701018b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP13_IP2_RML_W1C"    ,	   0x1070101ab2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP14_IP2_RML_W1C"    ,	   0x1070101cb2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP15_IP2_RML_W1C"    ,	   0x1070101eb2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP16_IP2_RML_W1C"    ,	   0x10701020b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP17_IP2_RML_W1C"    ,	   0x10701022b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP18_IP2_RML_W1C"    ,	   0x10701024b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP19_IP2_RML_W1C"    ,	   0x10701026b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP20_IP2_RML_W1C"    ,	   0x10701028b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP21_IP2_RML_W1C"    ,	   0x1070102ab2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP22_IP2_RML_W1C"    ,	   0x1070102cb2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP23_IP2_RML_W1C"    ,	   0x1070102eb2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP24_IP2_RML_W1C"    ,	   0x10701030b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP25_IP2_RML_W1C"    ,	   0x10701032b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP26_IP2_RML_W1C"    ,	   0x10701034b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP27_IP2_RML_W1C"    ,	   0x10701036b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP28_IP2_RML_W1C"    ,	   0x10701038b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP29_IP2_RML_W1C"    ,	   0x1070103ab2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP30_IP2_RML_W1C"    ,	   0x1070103cb2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP31_IP2_RML_W1C"    ,	   0x1070103eb2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP0_IP2_RML_W1S"     ,	   0x10701000a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP1_IP2_RML_W1S"     ,	   0x10701002a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP2_IP2_RML_W1S"     ,	   0x10701004a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP3_IP2_RML_W1S"     ,	   0x10701006a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP4_IP2_RML_W1S"     ,	   0x10701008a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP5_IP2_RML_W1S"     ,	   0x1070100aa2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP6_IP2_RML_W1S"     ,	   0x1070100ca2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP7_IP2_RML_W1S"     ,	   0x1070100ea2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP8_IP2_RML_W1S"     ,	   0x10701010a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP9_IP2_RML_W1S"     ,	   0x10701012a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP10_IP2_RML_W1S"    ,	   0x10701014a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP11_IP2_RML_W1S"    ,	   0x10701016a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP12_IP2_RML_W1S"    ,	   0x10701018a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP13_IP2_RML_W1S"    ,	   0x1070101aa2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP14_IP2_RML_W1S"    ,	   0x1070101ca2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP15_IP2_RML_W1S"    ,	   0x1070101ea2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP16_IP2_RML_W1S"    ,	   0x10701020a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP17_IP2_RML_W1S"    ,	   0x10701022a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP18_IP2_RML_W1S"    ,	   0x10701024a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP19_IP2_RML_W1S"    ,	   0x10701026a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP20_IP2_RML_W1S"    ,	   0x10701028a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP21_IP2_RML_W1S"    ,	   0x1070102aa2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP22_IP2_RML_W1S"    ,	   0x1070102ca2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP23_IP2_RML_W1S"    ,	   0x1070102ea2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP24_IP2_RML_W1S"    ,	   0x10701030a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP25_IP2_RML_W1S"    ,	   0x10701032a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP26_IP2_RML_W1S"    ,	   0x10701034a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP27_IP2_RML_W1S"    ,	   0x10701036a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP28_IP2_RML_W1S"    ,	   0x10701038a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP29_IP2_RML_W1S"    ,	   0x1070103aa2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP30_IP2_RML_W1S"    ,	   0x1070103ca2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP31_IP2_RML_W1S"    ,	   0x1070103ea2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP0_IP2_WDOG"        ,	   0x1070100091000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP1_IP2_WDOG"        ,	   0x1070100291000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP2_IP2_WDOG"        ,	   0x1070100491000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP3_IP2_WDOG"        ,	   0x1070100691000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP4_IP2_WDOG"        ,	   0x1070100891000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP5_IP2_WDOG"        ,	   0x1070100a91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP6_IP2_WDOG"        ,	   0x1070100c91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP7_IP2_WDOG"        ,	   0x1070100e91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP8_IP2_WDOG"        ,	   0x1070101091000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP9_IP2_WDOG"        ,	   0x1070101291000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP10_IP2_WDOG"       ,	   0x1070101491000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP11_IP2_WDOG"       ,	   0x1070101691000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP12_IP2_WDOG"       ,	   0x1070101891000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP13_IP2_WDOG"       ,	   0x1070101a91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP14_IP2_WDOG"       ,	   0x1070101c91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP15_IP2_WDOG"       ,	   0x1070101e91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP16_IP2_WDOG"       ,	   0x1070102091000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP17_IP2_WDOG"       ,	   0x1070102291000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP18_IP2_WDOG"       ,	   0x1070102491000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP19_IP2_WDOG"       ,	   0x1070102691000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP20_IP2_WDOG"       ,	   0x1070102891000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP21_IP2_WDOG"       ,	   0x1070102a91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP22_IP2_WDOG"       ,	   0x1070102c91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP23_IP2_WDOG"       ,	   0x1070102e91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP24_IP2_WDOG"       ,	   0x1070103091000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP25_IP2_WDOG"       ,	   0x1070103291000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP26_IP2_WDOG"       ,	   0x1070103491000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP27_IP2_WDOG"       ,	   0x1070103691000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP28_IP2_WDOG"       ,	   0x1070103891000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP29_IP2_WDOG"       ,	   0x1070103a91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP30_IP2_WDOG"       ,	   0x1070103c91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP31_IP2_WDOG"       ,	   0x1070103e91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP0_IP2_WDOG_W1C"    ,	   0x10701000b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP1_IP2_WDOG_W1C"    ,	   0x10701002b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP2_IP2_WDOG_W1C"    ,	   0x10701004b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP3_IP2_WDOG_W1C"    ,	   0x10701006b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP4_IP2_WDOG_W1C"    ,	   0x10701008b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP5_IP2_WDOG_W1C"    ,	   0x1070100ab1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP6_IP2_WDOG_W1C"    ,	   0x1070100cb1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP7_IP2_WDOG_W1C"    ,	   0x1070100eb1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP8_IP2_WDOG_W1C"    ,	   0x10701010b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP9_IP2_WDOG_W1C"    ,	   0x10701012b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP10_IP2_WDOG_W1C"   ,	   0x10701014b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP11_IP2_WDOG_W1C"   ,	   0x10701016b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP12_IP2_WDOG_W1C"   ,	   0x10701018b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP13_IP2_WDOG_W1C"   ,	   0x1070101ab1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP14_IP2_WDOG_W1C"   ,	   0x1070101cb1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP15_IP2_WDOG_W1C"   ,	   0x1070101eb1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP16_IP2_WDOG_W1C"   ,	   0x10701020b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP17_IP2_WDOG_W1C"   ,	   0x10701022b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP18_IP2_WDOG_W1C"   ,	   0x10701024b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP19_IP2_WDOG_W1C"   ,	   0x10701026b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP20_IP2_WDOG_W1C"   ,	   0x10701028b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP21_IP2_WDOG_W1C"   ,	   0x1070102ab1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP22_IP2_WDOG_W1C"   ,	   0x1070102cb1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP23_IP2_WDOG_W1C"   ,	   0x1070102eb1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP24_IP2_WDOG_W1C"   ,	   0x10701030b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP25_IP2_WDOG_W1C"   ,	   0x10701032b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP26_IP2_WDOG_W1C"   ,	   0x10701034b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP27_IP2_WDOG_W1C"   ,	   0x10701036b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP28_IP2_WDOG_W1C"   ,	   0x10701038b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP29_IP2_WDOG_W1C"   ,	   0x1070103ab1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP30_IP2_WDOG_W1C"   ,	   0x1070103cb1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP31_IP2_WDOG_W1C"   ,	   0x1070103eb1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP0_IP2_WDOG_W1S"    ,	   0x10701000a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP1_IP2_WDOG_W1S"    ,	   0x10701002a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP2_IP2_WDOG_W1S"    ,	   0x10701004a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP3_IP2_WDOG_W1S"    ,	   0x10701006a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP4_IP2_WDOG_W1S"    ,	   0x10701008a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP5_IP2_WDOG_W1S"    ,	   0x1070100aa1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP6_IP2_WDOG_W1S"    ,	   0x1070100ca1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP7_IP2_WDOG_W1S"    ,	   0x1070100ea1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP8_IP2_WDOG_W1S"    ,	   0x10701010a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP9_IP2_WDOG_W1S"    ,	   0x10701012a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP10_IP2_WDOG_W1S"   ,	   0x10701014a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP11_IP2_WDOG_W1S"   ,	   0x10701016a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP12_IP2_WDOG_W1S"   ,	   0x10701018a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP13_IP2_WDOG_W1S"   ,	   0x1070101aa1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP14_IP2_WDOG_W1S"   ,	   0x1070101ca1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP15_IP2_WDOG_W1S"   ,	   0x1070101ea1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP16_IP2_WDOG_W1S"   ,	   0x10701020a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP17_IP2_WDOG_W1S"   ,	   0x10701022a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP18_IP2_WDOG_W1S"   ,	   0x10701024a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP19_IP2_WDOG_W1S"   ,	   0x10701026a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP20_IP2_WDOG_W1S"   ,	   0x10701028a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP21_IP2_WDOG_W1S"   ,	   0x1070102aa1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP22_IP2_WDOG_W1S"   ,	   0x1070102ca1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP23_IP2_WDOG_W1S"   ,	   0x1070102ea1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP24_IP2_WDOG_W1S"   ,	   0x10701030a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP25_IP2_WDOG_W1S"   ,	   0x10701032a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP26_IP2_WDOG_W1S"   ,	   0x10701034a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP27_IP2_WDOG_W1S"   ,	   0x10701036a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP28_IP2_WDOG_W1S"   ,	   0x10701038a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP29_IP2_WDOG_W1S"   ,	   0x1070103aa1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP30_IP2_WDOG_W1S"   ,	   0x1070103ca1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP31_IP2_WDOG_W1S"   ,	   0x1070103ea1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP0_IP2_WRKQ"        ,	   0x1070100090000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP1_IP2_WRKQ"        ,	   0x1070100290000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP2_IP2_WRKQ"        ,	   0x1070100490000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP3_IP2_WRKQ"        ,	   0x1070100690000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP4_IP2_WRKQ"        ,	   0x1070100890000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP5_IP2_WRKQ"        ,	   0x1070100a90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP6_IP2_WRKQ"        ,	   0x1070100c90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP7_IP2_WRKQ"        ,	   0x1070100e90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP8_IP2_WRKQ"        ,	   0x1070101090000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP9_IP2_WRKQ"        ,	   0x1070101290000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP10_IP2_WRKQ"       ,	   0x1070101490000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP11_IP2_WRKQ"       ,	   0x1070101690000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP12_IP2_WRKQ"       ,	   0x1070101890000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP13_IP2_WRKQ"       ,	   0x1070101a90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP14_IP2_WRKQ"       ,	   0x1070101c90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP15_IP2_WRKQ"       ,	   0x1070101e90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP16_IP2_WRKQ"       ,	   0x1070102090000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP17_IP2_WRKQ"       ,	   0x1070102290000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP18_IP2_WRKQ"       ,	   0x1070102490000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP19_IP2_WRKQ"       ,	   0x1070102690000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP20_IP2_WRKQ"       ,	   0x1070102890000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP21_IP2_WRKQ"       ,	   0x1070102a90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP22_IP2_WRKQ"       ,	   0x1070102c90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP23_IP2_WRKQ"       ,	   0x1070102e90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP24_IP2_WRKQ"       ,	   0x1070103090000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP25_IP2_WRKQ"       ,	   0x1070103290000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP26_IP2_WRKQ"       ,	   0x1070103490000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP27_IP2_WRKQ"       ,	   0x1070103690000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP28_IP2_WRKQ"       ,	   0x1070103890000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP29_IP2_WRKQ"       ,	   0x1070103a90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP30_IP2_WRKQ"       ,	   0x1070103c90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP31_IP2_WRKQ"       ,	   0x1070103e90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP0_IP2_WRKQ_W1C"    ,	   0x10701000b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP1_IP2_WRKQ_W1C"    ,	   0x10701002b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP2_IP2_WRKQ_W1C"    ,	   0x10701004b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP3_IP2_WRKQ_W1C"    ,	   0x10701006b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP4_IP2_WRKQ_W1C"    ,	   0x10701008b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP5_IP2_WRKQ_W1C"    ,	   0x1070100ab0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP6_IP2_WRKQ_W1C"    ,	   0x1070100cb0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP7_IP2_WRKQ_W1C"    ,	   0x1070100eb0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP8_IP2_WRKQ_W1C"    ,	   0x10701010b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP9_IP2_WRKQ_W1C"    ,	   0x10701012b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP10_IP2_WRKQ_W1C"   ,	   0x10701014b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP11_IP2_WRKQ_W1C"   ,	   0x10701016b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP12_IP2_WRKQ_W1C"   ,	   0x10701018b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP13_IP2_WRKQ_W1C"   ,	   0x1070101ab0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP14_IP2_WRKQ_W1C"   ,	   0x1070101cb0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP15_IP2_WRKQ_W1C"   ,	   0x1070101eb0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP16_IP2_WRKQ_W1C"   ,	   0x10701020b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP17_IP2_WRKQ_W1C"   ,	   0x10701022b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP18_IP2_WRKQ_W1C"   ,	   0x10701024b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP19_IP2_WRKQ_W1C"   ,	   0x10701026b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP20_IP2_WRKQ_W1C"   ,	   0x10701028b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP21_IP2_WRKQ_W1C"   ,	   0x1070102ab0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP22_IP2_WRKQ_W1C"   ,	   0x1070102cb0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP23_IP2_WRKQ_W1C"   ,	   0x1070102eb0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP24_IP2_WRKQ_W1C"   ,	   0x10701030b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP25_IP2_WRKQ_W1C"   ,	   0x10701032b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP26_IP2_WRKQ_W1C"   ,	   0x10701034b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP27_IP2_WRKQ_W1C"   ,	   0x10701036b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP28_IP2_WRKQ_W1C"   ,	   0x10701038b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP29_IP2_WRKQ_W1C"   ,	   0x1070103ab0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP30_IP2_WRKQ_W1C"   ,	   0x1070103cb0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP31_IP2_WRKQ_W1C"   ,	   0x1070103eb0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP0_IP2_WRKQ_W1S"    ,	   0x10701000a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP1_IP2_WRKQ_W1S"    ,	   0x10701002a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP2_IP2_WRKQ_W1S"    ,	   0x10701004a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP3_IP2_WRKQ_W1S"    ,	   0x10701006a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP4_IP2_WRKQ_W1S"    ,	   0x10701008a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP5_IP2_WRKQ_W1S"    ,	   0x1070100aa0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP6_IP2_WRKQ_W1S"    ,	   0x1070100ca0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP7_IP2_WRKQ_W1S"    ,	   0x1070100ea0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP8_IP2_WRKQ_W1S"    ,	   0x10701010a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP9_IP2_WRKQ_W1S"    ,	   0x10701012a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP10_IP2_WRKQ_W1S"   ,	   0x10701014a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP11_IP2_WRKQ_W1S"   ,	   0x10701016a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP12_IP2_WRKQ_W1S"   ,	   0x10701018a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP13_IP2_WRKQ_W1S"   ,	   0x1070101aa0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP14_IP2_WRKQ_W1S"   ,	   0x1070101ca0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP15_IP2_WRKQ_W1S"   ,	   0x1070101ea0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP16_IP2_WRKQ_W1S"   ,	   0x10701020a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP17_IP2_WRKQ_W1S"   ,	   0x10701022a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP18_IP2_WRKQ_W1S"   ,	   0x10701024a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP19_IP2_WRKQ_W1S"   ,	   0x10701026a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP20_IP2_WRKQ_W1S"   ,	   0x10701028a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP21_IP2_WRKQ_W1S"   ,	   0x1070102aa0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP22_IP2_WRKQ_W1S"   ,	   0x1070102ca0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP23_IP2_WRKQ_W1S"   ,	   0x1070102ea0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP24_IP2_WRKQ_W1S"   ,	   0x10701030a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP25_IP2_WRKQ_W1S"   ,	   0x10701032a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP26_IP2_WRKQ_W1S"   ,	   0x10701034a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP27_IP2_WRKQ_W1S"   ,	   0x10701036a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP28_IP2_WRKQ_W1S"   ,	   0x10701038a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP29_IP2_WRKQ_W1S"   ,	   0x1070103aa0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP30_IP2_WRKQ_W1S"   ,	   0x1070103ca0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP31_IP2_WRKQ_W1S"   ,	   0x1070103ea0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP0_IP3_GPIO"        ,	   0x1070100097200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP1_IP3_GPIO"        ,	   0x1070100297200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP2_IP3_GPIO"        ,	   0x1070100497200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP3_IP3_GPIO"        ,	   0x1070100697200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP4_IP3_GPIO"        ,	   0x1070100897200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP5_IP3_GPIO"        ,	   0x1070100a97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP6_IP3_GPIO"        ,	   0x1070100c97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP7_IP3_GPIO"        ,	   0x1070100e97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP8_IP3_GPIO"        ,	   0x1070101097200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP9_IP3_GPIO"        ,	   0x1070101297200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP10_IP3_GPIO"       ,	   0x1070101497200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP11_IP3_GPIO"       ,	   0x1070101697200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP12_IP3_GPIO"       ,	   0x1070101897200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP13_IP3_GPIO"       ,	   0x1070101a97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP14_IP3_GPIO"       ,	   0x1070101c97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP15_IP3_GPIO"       ,	   0x1070101e97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP16_IP3_GPIO"       ,	   0x1070102097200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP17_IP3_GPIO"       ,	   0x1070102297200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP18_IP3_GPIO"       ,	   0x1070102497200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP19_IP3_GPIO"       ,	   0x1070102697200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP20_IP3_GPIO"       ,	   0x1070102897200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP21_IP3_GPIO"       ,	   0x1070102a97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP22_IP3_GPIO"       ,	   0x1070102c97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP23_IP3_GPIO"       ,	   0x1070102e97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP24_IP3_GPIO"       ,	   0x1070103097200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP25_IP3_GPIO"       ,	   0x1070103297200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP26_IP3_GPIO"       ,	   0x1070103497200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP27_IP3_GPIO"       ,	   0x1070103697200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP28_IP3_GPIO"       ,	   0x1070103897200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP29_IP3_GPIO"       ,	   0x1070103a97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP30_IP3_GPIO"       ,	   0x1070103c97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP31_IP3_GPIO"       ,	   0x1070103e97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP0_IP3_GPIO_W1C"    ,	   0x10701000b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP1_IP3_GPIO_W1C"    ,	   0x10701002b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP2_IP3_GPIO_W1C"    ,	   0x10701004b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP3_IP3_GPIO_W1C"    ,	   0x10701006b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP4_IP3_GPIO_W1C"    ,	   0x10701008b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP5_IP3_GPIO_W1C"    ,	   0x1070100ab7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP6_IP3_GPIO_W1C"    ,	   0x1070100cb7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP7_IP3_GPIO_W1C"    ,	   0x1070100eb7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP8_IP3_GPIO_W1C"    ,	   0x10701010b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP9_IP3_GPIO_W1C"    ,	   0x10701012b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP10_IP3_GPIO_W1C"   ,	   0x10701014b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP11_IP3_GPIO_W1C"   ,	   0x10701016b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP12_IP3_GPIO_W1C"   ,	   0x10701018b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP13_IP3_GPIO_W1C"   ,	   0x1070101ab7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP14_IP3_GPIO_W1C"   ,	   0x1070101cb7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP15_IP3_GPIO_W1C"   ,	   0x1070101eb7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP16_IP3_GPIO_W1C"   ,	   0x10701020b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP17_IP3_GPIO_W1C"   ,	   0x10701022b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP18_IP3_GPIO_W1C"   ,	   0x10701024b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP19_IP3_GPIO_W1C"   ,	   0x10701026b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP20_IP3_GPIO_W1C"   ,	   0x10701028b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP21_IP3_GPIO_W1C"   ,	   0x1070102ab7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP22_IP3_GPIO_W1C"   ,	   0x1070102cb7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP23_IP3_GPIO_W1C"   ,	   0x1070102eb7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP24_IP3_GPIO_W1C"   ,	   0x10701030b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP25_IP3_GPIO_W1C"   ,	   0x10701032b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP26_IP3_GPIO_W1C"   ,	   0x10701034b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP27_IP3_GPIO_W1C"   ,	   0x10701036b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP28_IP3_GPIO_W1C"   ,	   0x10701038b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP29_IP3_GPIO_W1C"   ,	   0x1070103ab7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP30_IP3_GPIO_W1C"   ,	   0x1070103cb7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP31_IP3_GPIO_W1C"   ,	   0x1070103eb7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP0_IP3_GPIO_W1S"    ,	   0x10701000a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP1_IP3_GPIO_W1S"    ,	   0x10701002a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP2_IP3_GPIO_W1S"    ,	   0x10701004a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP3_IP3_GPIO_W1S"    ,	   0x10701006a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP4_IP3_GPIO_W1S"    ,	   0x10701008a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP5_IP3_GPIO_W1S"    ,	   0x1070100aa7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP6_IP3_GPIO_W1S"    ,	   0x1070100ca7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP7_IP3_GPIO_W1S"    ,	   0x1070100ea7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP8_IP3_GPIO_W1S"    ,	   0x10701010a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP9_IP3_GPIO_W1S"    ,	   0x10701012a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP10_IP3_GPIO_W1S"   ,	   0x10701014a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP11_IP3_GPIO_W1S"   ,	   0x10701016a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP12_IP3_GPIO_W1S"   ,	   0x10701018a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP13_IP3_GPIO_W1S"   ,	   0x1070101aa7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP14_IP3_GPIO_W1S"   ,	   0x1070101ca7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP15_IP3_GPIO_W1S"   ,	   0x1070101ea7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP16_IP3_GPIO_W1S"   ,	   0x10701020a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP17_IP3_GPIO_W1S"   ,	   0x10701022a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP18_IP3_GPIO_W1S"   ,	   0x10701024a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP19_IP3_GPIO_W1S"   ,	   0x10701026a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP20_IP3_GPIO_W1S"   ,	   0x10701028a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP21_IP3_GPIO_W1S"   ,	   0x1070102aa7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP22_IP3_GPIO_W1S"   ,	   0x1070102ca7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP23_IP3_GPIO_W1S"   ,	   0x1070102ea7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP24_IP3_GPIO_W1S"   ,	   0x10701030a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP25_IP3_GPIO_W1S"   ,	   0x10701032a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP26_IP3_GPIO_W1S"   ,	   0x10701034a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP27_IP3_GPIO_W1S"   ,	   0x10701036a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP28_IP3_GPIO_W1S"   ,	   0x10701038a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP29_IP3_GPIO_W1S"   ,	   0x1070103aa7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP30_IP3_GPIO_W1S"   ,	   0x1070103ca7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP31_IP3_GPIO_W1S"   ,	   0x1070103ea7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP0_IP3_IO"          ,	   0x1070100094200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP1_IP3_IO"          ,	   0x1070100294200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP2_IP3_IO"          ,	   0x1070100494200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP3_IP3_IO"          ,	   0x1070100694200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP4_IP3_IO"          ,	   0x1070100894200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP5_IP3_IO"          ,	   0x1070100a94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP6_IP3_IO"          ,	   0x1070100c94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP7_IP3_IO"          ,	   0x1070100e94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP8_IP3_IO"          ,	   0x1070101094200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP9_IP3_IO"          ,	   0x1070101294200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP10_IP3_IO"         ,	   0x1070101494200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP11_IP3_IO"         ,	   0x1070101694200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP12_IP3_IO"         ,	   0x1070101894200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP13_IP3_IO"         ,	   0x1070101a94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP14_IP3_IO"         ,	   0x1070101c94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP15_IP3_IO"         ,	   0x1070101e94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP16_IP3_IO"         ,	   0x1070102094200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP17_IP3_IO"         ,	   0x1070102294200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP18_IP3_IO"         ,	   0x1070102494200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP19_IP3_IO"         ,	   0x1070102694200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP20_IP3_IO"         ,	   0x1070102894200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP21_IP3_IO"         ,	   0x1070102a94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP22_IP3_IO"         ,	   0x1070102c94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP23_IP3_IO"         ,	   0x1070102e94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP24_IP3_IO"         ,	   0x1070103094200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP25_IP3_IO"         ,	   0x1070103294200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP26_IP3_IO"         ,	   0x1070103494200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP27_IP3_IO"         ,	   0x1070103694200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP28_IP3_IO"         ,	   0x1070103894200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP29_IP3_IO"         ,	   0x1070103a94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP30_IP3_IO"         ,	   0x1070103c94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP31_IP3_IO"         ,	   0x1070103e94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP0_IP3_IO_W1C"      ,	   0x10701000b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP1_IP3_IO_W1C"      ,	   0x10701002b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP2_IP3_IO_W1C"      ,	   0x10701004b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP3_IP3_IO_W1C"      ,	   0x10701006b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP4_IP3_IO_W1C"      ,	   0x10701008b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP5_IP3_IO_W1C"      ,	   0x1070100ab4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP6_IP3_IO_W1C"      ,	   0x1070100cb4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP7_IP3_IO_W1C"      ,	   0x1070100eb4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP8_IP3_IO_W1C"      ,	   0x10701010b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP9_IP3_IO_W1C"      ,	   0x10701012b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP10_IP3_IO_W1C"     ,	   0x10701014b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP11_IP3_IO_W1C"     ,	   0x10701016b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP12_IP3_IO_W1C"     ,	   0x10701018b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP13_IP3_IO_W1C"     ,	   0x1070101ab4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP14_IP3_IO_W1C"     ,	   0x1070101cb4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP15_IP3_IO_W1C"     ,	   0x1070101eb4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP16_IP3_IO_W1C"     ,	   0x10701020b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP17_IP3_IO_W1C"     ,	   0x10701022b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP18_IP3_IO_W1C"     ,	   0x10701024b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP19_IP3_IO_W1C"     ,	   0x10701026b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP20_IP3_IO_W1C"     ,	   0x10701028b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP21_IP3_IO_W1C"     ,	   0x1070102ab4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP22_IP3_IO_W1C"     ,	   0x1070102cb4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP23_IP3_IO_W1C"     ,	   0x1070102eb4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP24_IP3_IO_W1C"     ,	   0x10701030b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP25_IP3_IO_W1C"     ,	   0x10701032b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP26_IP3_IO_W1C"     ,	   0x10701034b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP27_IP3_IO_W1C"     ,	   0x10701036b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP28_IP3_IO_W1C"     ,	   0x10701038b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP29_IP3_IO_W1C"     ,	   0x1070103ab4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP30_IP3_IO_W1C"     ,	   0x1070103cb4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP31_IP3_IO_W1C"     ,	   0x1070103eb4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP0_IP3_IO_W1S"      ,	   0x10701000a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP1_IP3_IO_W1S"      ,	   0x10701002a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP2_IP3_IO_W1S"      ,	   0x10701004a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP3_IP3_IO_W1S"      ,	   0x10701006a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP4_IP3_IO_W1S"      ,	   0x10701008a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP5_IP3_IO_W1S"      ,	   0x1070100aa4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP6_IP3_IO_W1S"      ,	   0x1070100ca4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP7_IP3_IO_W1S"      ,	   0x1070100ea4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP8_IP3_IO_W1S"      ,	   0x10701010a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP9_IP3_IO_W1S"      ,	   0x10701012a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP10_IP3_IO_W1S"     ,	   0x10701014a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP11_IP3_IO_W1S"     ,	   0x10701016a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP12_IP3_IO_W1S"     ,	   0x10701018a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP13_IP3_IO_W1S"     ,	   0x1070101aa4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP14_IP3_IO_W1S"     ,	   0x1070101ca4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP15_IP3_IO_W1S"     ,	   0x1070101ea4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP16_IP3_IO_W1S"     ,	   0x10701020a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP17_IP3_IO_W1S"     ,	   0x10701022a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP18_IP3_IO_W1S"     ,	   0x10701024a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP19_IP3_IO_W1S"     ,	   0x10701026a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP20_IP3_IO_W1S"     ,	   0x10701028a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP21_IP3_IO_W1S"     ,	   0x1070102aa4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP22_IP3_IO_W1S"     ,	   0x1070102ca4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP23_IP3_IO_W1S"     ,	   0x1070102ea4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP24_IP3_IO_W1S"     ,	   0x10701030a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP25_IP3_IO_W1S"     ,	   0x10701032a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP26_IP3_IO_W1S"     ,	   0x10701034a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP27_IP3_IO_W1S"     ,	   0x10701036a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP28_IP3_IO_W1S"     ,	   0x10701038a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP29_IP3_IO_W1S"     ,	   0x1070103aa4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP30_IP3_IO_W1S"     ,	   0x1070103ca4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP31_IP3_IO_W1S"     ,	   0x1070103ea4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP0_IP3_MBOX"        ,	   0x1070100098200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP1_IP3_MBOX"        ,	   0x1070100298200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP2_IP3_MBOX"        ,	   0x1070100498200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP3_IP3_MBOX"        ,	   0x1070100698200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP4_IP3_MBOX"        ,	   0x1070100898200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP5_IP3_MBOX"        ,	   0x1070100a98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP6_IP3_MBOX"        ,	   0x1070100c98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP7_IP3_MBOX"        ,	   0x1070100e98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP8_IP3_MBOX"        ,	   0x1070101098200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP9_IP3_MBOX"        ,	   0x1070101298200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP10_IP3_MBOX"       ,	   0x1070101498200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP11_IP3_MBOX"       ,	   0x1070101698200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP12_IP3_MBOX"       ,	   0x1070101898200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP13_IP3_MBOX"       ,	   0x1070101a98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP14_IP3_MBOX"       ,	   0x1070101c98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP15_IP3_MBOX"       ,	   0x1070101e98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP16_IP3_MBOX"       ,	   0x1070102098200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP17_IP3_MBOX"       ,	   0x1070102298200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP18_IP3_MBOX"       ,	   0x1070102498200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP19_IP3_MBOX"       ,	   0x1070102698200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP20_IP3_MBOX"       ,	   0x1070102898200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP21_IP3_MBOX"       ,	   0x1070102a98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP22_IP3_MBOX"       ,	   0x1070102c98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP23_IP3_MBOX"       ,	   0x1070102e98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP24_IP3_MBOX"       ,	   0x1070103098200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP25_IP3_MBOX"       ,	   0x1070103298200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP26_IP3_MBOX"       ,	   0x1070103498200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP27_IP3_MBOX"       ,	   0x1070103698200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP28_IP3_MBOX"       ,	   0x1070103898200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP29_IP3_MBOX"       ,	   0x1070103a98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP30_IP3_MBOX"       ,	   0x1070103c98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP31_IP3_MBOX"       ,	   0x1070103e98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP0_IP3_MBOX_W1C"    ,	   0x10701000b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP1_IP3_MBOX_W1C"    ,	   0x10701002b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP2_IP3_MBOX_W1C"    ,	   0x10701004b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP3_IP3_MBOX_W1C"    ,	   0x10701006b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP4_IP3_MBOX_W1C"    ,	   0x10701008b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP5_IP3_MBOX_W1C"    ,	   0x1070100ab8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP6_IP3_MBOX_W1C"    ,	   0x1070100cb8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP7_IP3_MBOX_W1C"    ,	   0x1070100eb8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP8_IP3_MBOX_W1C"    ,	   0x10701010b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP9_IP3_MBOX_W1C"    ,	   0x10701012b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP10_IP3_MBOX_W1C"   ,	   0x10701014b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP11_IP3_MBOX_W1C"   ,	   0x10701016b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP12_IP3_MBOX_W1C"   ,	   0x10701018b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP13_IP3_MBOX_W1C"   ,	   0x1070101ab8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP14_IP3_MBOX_W1C"   ,	   0x1070101cb8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP15_IP3_MBOX_W1C"   ,	   0x1070101eb8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP16_IP3_MBOX_W1C"   ,	   0x10701020b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP17_IP3_MBOX_W1C"   ,	   0x10701022b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP18_IP3_MBOX_W1C"   ,	   0x10701024b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP19_IP3_MBOX_W1C"   ,	   0x10701026b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP20_IP3_MBOX_W1C"   ,	   0x10701028b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP21_IP3_MBOX_W1C"   ,	   0x1070102ab8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP22_IP3_MBOX_W1C"   ,	   0x1070102cb8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP23_IP3_MBOX_W1C"   ,	   0x1070102eb8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP24_IP3_MBOX_W1C"   ,	   0x10701030b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP25_IP3_MBOX_W1C"   ,	   0x10701032b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP26_IP3_MBOX_W1C"   ,	   0x10701034b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP27_IP3_MBOX_W1C"   ,	   0x10701036b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP28_IP3_MBOX_W1C"   ,	   0x10701038b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP29_IP3_MBOX_W1C"   ,	   0x1070103ab8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP30_IP3_MBOX_W1C"   ,	   0x1070103cb8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP31_IP3_MBOX_W1C"   ,	   0x1070103eb8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP0_IP3_MBOX_W1S"    ,	   0x10701000a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP1_IP3_MBOX_W1S"    ,	   0x10701002a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP2_IP3_MBOX_W1S"    ,	   0x10701004a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP3_IP3_MBOX_W1S"    ,	   0x10701006a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP4_IP3_MBOX_W1S"    ,	   0x10701008a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP5_IP3_MBOX_W1S"    ,	   0x1070100aa8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP6_IP3_MBOX_W1S"    ,	   0x1070100ca8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP7_IP3_MBOX_W1S"    ,	   0x1070100ea8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP8_IP3_MBOX_W1S"    ,	   0x10701010a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP9_IP3_MBOX_W1S"    ,	   0x10701012a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP10_IP3_MBOX_W1S"   ,	   0x10701014a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP11_IP3_MBOX_W1S"   ,	   0x10701016a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP12_IP3_MBOX_W1S"   ,	   0x10701018a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP13_IP3_MBOX_W1S"   ,	   0x1070101aa8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP14_IP3_MBOX_W1S"   ,	   0x1070101ca8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP15_IP3_MBOX_W1S"   ,	   0x1070101ea8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP16_IP3_MBOX_W1S"   ,	   0x10701020a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP17_IP3_MBOX_W1S"   ,	   0x10701022a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP18_IP3_MBOX_W1S"   ,	   0x10701024a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP19_IP3_MBOX_W1S"   ,	   0x10701026a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP20_IP3_MBOX_W1S"   ,	   0x10701028a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP21_IP3_MBOX_W1S"   ,	   0x1070102aa8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP22_IP3_MBOX_W1S"   ,	   0x1070102ca8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP23_IP3_MBOX_W1S"   ,	   0x1070102ea8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP24_IP3_MBOX_W1S"   ,	   0x10701030a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP25_IP3_MBOX_W1S"   ,	   0x10701032a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP26_IP3_MBOX_W1S"   ,	   0x10701034a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP27_IP3_MBOX_W1S"   ,	   0x10701036a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP28_IP3_MBOX_W1S"   ,	   0x10701038a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP29_IP3_MBOX_W1S"   ,	   0x1070103aa8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP30_IP3_MBOX_W1S"   ,	   0x1070103ca8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP31_IP3_MBOX_W1S"   ,	   0x1070103ea8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP0_IP3_MEM"         ,	   0x1070100095200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP1_IP3_MEM"         ,	   0x1070100295200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP2_IP3_MEM"         ,	   0x1070100495200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP3_IP3_MEM"         ,	   0x1070100695200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP4_IP3_MEM"         ,	   0x1070100895200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP5_IP3_MEM"         ,	   0x1070100a95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP6_IP3_MEM"         ,	   0x1070100c95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP7_IP3_MEM"         ,	   0x1070100e95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP8_IP3_MEM"         ,	   0x1070101095200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP9_IP3_MEM"         ,	   0x1070101295200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP10_IP3_MEM"        ,	   0x1070101495200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP11_IP3_MEM"        ,	   0x1070101695200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP12_IP3_MEM"        ,	   0x1070101895200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP13_IP3_MEM"        ,	   0x1070101a95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP14_IP3_MEM"        ,	   0x1070101c95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP15_IP3_MEM"        ,	   0x1070101e95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP16_IP3_MEM"        ,	   0x1070102095200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP17_IP3_MEM"        ,	   0x1070102295200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP18_IP3_MEM"        ,	   0x1070102495200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP19_IP3_MEM"        ,	   0x1070102695200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP20_IP3_MEM"        ,	   0x1070102895200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP21_IP3_MEM"        ,	   0x1070102a95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP22_IP3_MEM"        ,	   0x1070102c95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP23_IP3_MEM"        ,	   0x1070102e95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP24_IP3_MEM"        ,	   0x1070103095200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP25_IP3_MEM"        ,	   0x1070103295200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP26_IP3_MEM"        ,	   0x1070103495200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP27_IP3_MEM"        ,	   0x1070103695200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP28_IP3_MEM"        ,	   0x1070103895200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP29_IP3_MEM"        ,	   0x1070103a95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP30_IP3_MEM"        ,	   0x1070103c95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP31_IP3_MEM"        ,	   0x1070103e95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP0_IP3_MEM_W1C"     ,	   0x10701000b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP1_IP3_MEM_W1C"     ,	   0x10701002b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP2_IP3_MEM_W1C"     ,	   0x10701004b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP3_IP3_MEM_W1C"     ,	   0x10701006b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP4_IP3_MEM_W1C"     ,	   0x10701008b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP5_IP3_MEM_W1C"     ,	   0x1070100ab5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP6_IP3_MEM_W1C"     ,	   0x1070100cb5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP7_IP3_MEM_W1C"     ,	   0x1070100eb5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP8_IP3_MEM_W1C"     ,	   0x10701010b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP9_IP3_MEM_W1C"     ,	   0x10701012b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP10_IP3_MEM_W1C"    ,	   0x10701014b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP11_IP3_MEM_W1C"    ,	   0x10701016b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP12_IP3_MEM_W1C"    ,	   0x10701018b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP13_IP3_MEM_W1C"    ,	   0x1070101ab5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP14_IP3_MEM_W1C"    ,	   0x1070101cb5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP15_IP3_MEM_W1C"    ,	   0x1070101eb5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP16_IP3_MEM_W1C"    ,	   0x10701020b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP17_IP3_MEM_W1C"    ,	   0x10701022b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP18_IP3_MEM_W1C"    ,	   0x10701024b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP19_IP3_MEM_W1C"    ,	   0x10701026b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP20_IP3_MEM_W1C"    ,	   0x10701028b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP21_IP3_MEM_W1C"    ,	   0x1070102ab5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP22_IP3_MEM_W1C"    ,	   0x1070102cb5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP23_IP3_MEM_W1C"    ,	   0x1070102eb5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP24_IP3_MEM_W1C"    ,	   0x10701030b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP25_IP3_MEM_W1C"    ,	   0x10701032b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP26_IP3_MEM_W1C"    ,	   0x10701034b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP27_IP3_MEM_W1C"    ,	   0x10701036b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP28_IP3_MEM_W1C"    ,	   0x10701038b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP29_IP3_MEM_W1C"    ,	   0x1070103ab5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP30_IP3_MEM_W1C"    ,	   0x1070103cb5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP31_IP3_MEM_W1C"    ,	   0x1070103eb5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP0_IP3_MEM_W1S"     ,	   0x10701000a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP1_IP3_MEM_W1S"     ,	   0x10701002a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP2_IP3_MEM_W1S"     ,	   0x10701004a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP3_IP3_MEM_W1S"     ,	   0x10701006a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP4_IP3_MEM_W1S"     ,	   0x10701008a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP5_IP3_MEM_W1S"     ,	   0x1070100aa5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP6_IP3_MEM_W1S"     ,	   0x1070100ca5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP7_IP3_MEM_W1S"     ,	   0x1070100ea5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP8_IP3_MEM_W1S"     ,	   0x10701010a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP9_IP3_MEM_W1S"     ,	   0x10701012a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP10_IP3_MEM_W1S"    ,	   0x10701014a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP11_IP3_MEM_W1S"    ,	   0x10701016a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP12_IP3_MEM_W1S"    ,	   0x10701018a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP13_IP3_MEM_W1S"    ,	   0x1070101aa5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP14_IP3_MEM_W1S"    ,	   0x1070101ca5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP15_IP3_MEM_W1S"    ,	   0x1070101ea5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP16_IP3_MEM_W1S"    ,	   0x10701020a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP17_IP3_MEM_W1S"    ,	   0x10701022a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP18_IP3_MEM_W1S"    ,	   0x10701024a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP19_IP3_MEM_W1S"    ,	   0x10701026a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP20_IP3_MEM_W1S"    ,	   0x10701028a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP21_IP3_MEM_W1S"    ,	   0x1070102aa5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP22_IP3_MEM_W1S"    ,	   0x1070102ca5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP23_IP3_MEM_W1S"    ,	   0x1070102ea5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP24_IP3_MEM_W1S"    ,	   0x10701030a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP25_IP3_MEM_W1S"    ,	   0x10701032a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP26_IP3_MEM_W1S"    ,	   0x10701034a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP27_IP3_MEM_W1S"    ,	   0x10701036a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP28_IP3_MEM_W1S"    ,	   0x10701038a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP29_IP3_MEM_W1S"    ,	   0x1070103aa5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP30_IP3_MEM_W1S"    ,	   0x1070103ca5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP31_IP3_MEM_W1S"    ,	   0x1070103ea5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP0_IP3_MIO"         ,	   0x1070100093200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP1_IP3_MIO"         ,	   0x1070100293200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP2_IP3_MIO"         ,	   0x1070100493200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP3_IP3_MIO"         ,	   0x1070100693200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP4_IP3_MIO"         ,	   0x1070100893200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP5_IP3_MIO"         ,	   0x1070100a93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP6_IP3_MIO"         ,	   0x1070100c93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP7_IP3_MIO"         ,	   0x1070100e93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP8_IP3_MIO"         ,	   0x1070101093200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP9_IP3_MIO"         ,	   0x1070101293200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP10_IP3_MIO"        ,	   0x1070101493200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP11_IP3_MIO"        ,	   0x1070101693200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP12_IP3_MIO"        ,	   0x1070101893200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP13_IP3_MIO"        ,	   0x1070101a93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP14_IP3_MIO"        ,	   0x1070101c93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP15_IP3_MIO"        ,	   0x1070101e93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP16_IP3_MIO"        ,	   0x1070102093200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP17_IP3_MIO"        ,	   0x1070102293200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP18_IP3_MIO"        ,	   0x1070102493200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP19_IP3_MIO"        ,	   0x1070102693200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP20_IP3_MIO"        ,	   0x1070102893200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP21_IP3_MIO"        ,	   0x1070102a93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP22_IP3_MIO"        ,	   0x1070102c93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP23_IP3_MIO"        ,	   0x1070102e93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP24_IP3_MIO"        ,	   0x1070103093200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP25_IP3_MIO"        ,	   0x1070103293200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP26_IP3_MIO"        ,	   0x1070103493200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP27_IP3_MIO"        ,	   0x1070103693200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP28_IP3_MIO"        ,	   0x1070103893200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP29_IP3_MIO"        ,	   0x1070103a93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP30_IP3_MIO"        ,	   0x1070103c93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP31_IP3_MIO"        ,	   0x1070103e93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP0_IP3_MIO_W1C"     ,	   0x10701000b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP1_IP3_MIO_W1C"     ,	   0x10701002b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP2_IP3_MIO_W1C"     ,	   0x10701004b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP3_IP3_MIO_W1C"     ,	   0x10701006b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP4_IP3_MIO_W1C"     ,	   0x10701008b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP5_IP3_MIO_W1C"     ,	   0x1070100ab3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP6_IP3_MIO_W1C"     ,	   0x1070100cb3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP7_IP3_MIO_W1C"     ,	   0x1070100eb3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP8_IP3_MIO_W1C"     ,	   0x10701010b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP9_IP3_MIO_W1C"     ,	   0x10701012b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP10_IP3_MIO_W1C"    ,	   0x10701014b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP11_IP3_MIO_W1C"    ,	   0x10701016b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP12_IP3_MIO_W1C"    ,	   0x10701018b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP13_IP3_MIO_W1C"    ,	   0x1070101ab3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP14_IP3_MIO_W1C"    ,	   0x1070101cb3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP15_IP3_MIO_W1C"    ,	   0x1070101eb3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP16_IP3_MIO_W1C"    ,	   0x10701020b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP17_IP3_MIO_W1C"    ,	   0x10701022b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP18_IP3_MIO_W1C"    ,	   0x10701024b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP19_IP3_MIO_W1C"    ,	   0x10701026b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP20_IP3_MIO_W1C"    ,	   0x10701028b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP21_IP3_MIO_W1C"    ,	   0x1070102ab3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP22_IP3_MIO_W1C"    ,	   0x1070102cb3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP23_IP3_MIO_W1C"    ,	   0x1070102eb3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP24_IP3_MIO_W1C"    ,	   0x10701030b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP25_IP3_MIO_W1C"    ,	   0x10701032b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP26_IP3_MIO_W1C"    ,	   0x10701034b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP27_IP3_MIO_W1C"    ,	   0x10701036b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP28_IP3_MIO_W1C"    ,	   0x10701038b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP29_IP3_MIO_W1C"    ,	   0x1070103ab3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP30_IP3_MIO_W1C"    ,	   0x1070103cb3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP31_IP3_MIO_W1C"    ,	   0x1070103eb3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP0_IP3_MIO_W1S"     ,	   0x10701000a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP1_IP3_MIO_W1S"     ,	   0x10701002a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP2_IP3_MIO_W1S"     ,	   0x10701004a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP3_IP3_MIO_W1S"     ,	   0x10701006a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP4_IP3_MIO_W1S"     ,	   0x10701008a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP5_IP3_MIO_W1S"     ,	   0x1070100aa3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP6_IP3_MIO_W1S"     ,	   0x1070100ca3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP7_IP3_MIO_W1S"     ,	   0x1070100ea3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP8_IP3_MIO_W1S"     ,	   0x10701010a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP9_IP3_MIO_W1S"     ,	   0x10701012a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP10_IP3_MIO_W1S"    ,	   0x10701014a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP11_IP3_MIO_W1S"    ,	   0x10701016a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP12_IP3_MIO_W1S"    ,	   0x10701018a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP13_IP3_MIO_W1S"    ,	   0x1070101aa3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP14_IP3_MIO_W1S"    ,	   0x1070101ca3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP15_IP3_MIO_W1S"    ,	   0x1070101ea3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP16_IP3_MIO_W1S"    ,	   0x10701020a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP17_IP3_MIO_W1S"    ,	   0x10701022a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP18_IP3_MIO_W1S"    ,	   0x10701024a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP19_IP3_MIO_W1S"    ,	   0x10701026a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP20_IP3_MIO_W1S"    ,	   0x10701028a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP21_IP3_MIO_W1S"    ,	   0x1070102aa3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP22_IP3_MIO_W1S"    ,	   0x1070102ca3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP23_IP3_MIO_W1S"    ,	   0x1070102ea3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP24_IP3_MIO_W1S"    ,	   0x10701030a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP25_IP3_MIO_W1S"    ,	   0x10701032a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP26_IP3_MIO_W1S"    ,	   0x10701034a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP27_IP3_MIO_W1S"    ,	   0x10701036a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP28_IP3_MIO_W1S"    ,	   0x10701038a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP29_IP3_MIO_W1S"    ,	   0x1070103aa3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP30_IP3_MIO_W1S"    ,	   0x1070103ca3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP31_IP3_MIO_W1S"    ,	   0x1070103ea3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP0_IP3_PKT"         ,	   0x1070100096200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP1_IP3_PKT"         ,	   0x1070100296200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP2_IP3_PKT"         ,	   0x1070100496200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP3_IP3_PKT"         ,	   0x1070100696200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP4_IP3_PKT"         ,	   0x1070100896200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP5_IP3_PKT"         ,	   0x1070100a96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP6_IP3_PKT"         ,	   0x1070100c96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP7_IP3_PKT"         ,	   0x1070100e96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP8_IP3_PKT"         ,	   0x1070101096200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP9_IP3_PKT"         ,	   0x1070101296200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP10_IP3_PKT"        ,	   0x1070101496200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP11_IP3_PKT"        ,	   0x1070101696200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP12_IP3_PKT"        ,	   0x1070101896200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP13_IP3_PKT"        ,	   0x1070101a96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP14_IP3_PKT"        ,	   0x1070101c96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP15_IP3_PKT"        ,	   0x1070101e96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP16_IP3_PKT"        ,	   0x1070102096200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP17_IP3_PKT"        ,	   0x1070102296200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP18_IP3_PKT"        ,	   0x1070102496200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP19_IP3_PKT"        ,	   0x1070102696200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP20_IP3_PKT"        ,	   0x1070102896200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP21_IP3_PKT"        ,	   0x1070102a96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP22_IP3_PKT"        ,	   0x1070102c96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP23_IP3_PKT"        ,	   0x1070102e96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP24_IP3_PKT"        ,	   0x1070103096200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP25_IP3_PKT"        ,	   0x1070103296200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP26_IP3_PKT"        ,	   0x1070103496200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP27_IP3_PKT"        ,	   0x1070103696200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP28_IP3_PKT"        ,	   0x1070103896200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP29_IP3_PKT"        ,	   0x1070103a96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP30_IP3_PKT"        ,	   0x1070103c96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP31_IP3_PKT"        ,	   0x1070103e96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP0_IP3_PKT_W1C"     ,	   0x10701000b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP1_IP3_PKT_W1C"     ,	   0x10701002b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP2_IP3_PKT_W1C"     ,	   0x10701004b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP3_IP3_PKT_W1C"     ,	   0x10701006b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP4_IP3_PKT_W1C"     ,	   0x10701008b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP5_IP3_PKT_W1C"     ,	   0x1070100ab6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP6_IP3_PKT_W1C"     ,	   0x1070100cb6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP7_IP3_PKT_W1C"     ,	   0x1070100eb6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP8_IP3_PKT_W1C"     ,	   0x10701010b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP9_IP3_PKT_W1C"     ,	   0x10701012b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP10_IP3_PKT_W1C"    ,	   0x10701014b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP11_IP3_PKT_W1C"    ,	   0x10701016b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP12_IP3_PKT_W1C"    ,	   0x10701018b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP13_IP3_PKT_W1C"    ,	   0x1070101ab6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP14_IP3_PKT_W1C"    ,	   0x1070101cb6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP15_IP3_PKT_W1C"    ,	   0x1070101eb6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP16_IP3_PKT_W1C"    ,	   0x10701020b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP17_IP3_PKT_W1C"    ,	   0x10701022b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP18_IP3_PKT_W1C"    ,	   0x10701024b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP19_IP3_PKT_W1C"    ,	   0x10701026b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP20_IP3_PKT_W1C"    ,	   0x10701028b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP21_IP3_PKT_W1C"    ,	   0x1070102ab6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP22_IP3_PKT_W1C"    ,	   0x1070102cb6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP23_IP3_PKT_W1C"    ,	   0x1070102eb6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP24_IP3_PKT_W1C"    ,	   0x10701030b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP25_IP3_PKT_W1C"    ,	   0x10701032b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP26_IP3_PKT_W1C"    ,	   0x10701034b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP27_IP3_PKT_W1C"    ,	   0x10701036b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP28_IP3_PKT_W1C"    ,	   0x10701038b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP29_IP3_PKT_W1C"    ,	   0x1070103ab6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP30_IP3_PKT_W1C"    ,	   0x1070103cb6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP31_IP3_PKT_W1C"    ,	   0x1070103eb6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP0_IP3_PKT_W1S"     ,	   0x10701000a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP1_IP3_PKT_W1S"     ,	   0x10701002a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP2_IP3_PKT_W1S"     ,	   0x10701004a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP3_IP3_PKT_W1S"     ,	   0x10701006a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP4_IP3_PKT_W1S"     ,	   0x10701008a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP5_IP3_PKT_W1S"     ,	   0x1070100aa6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP6_IP3_PKT_W1S"     ,	   0x1070100ca6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP7_IP3_PKT_W1S"     ,	   0x1070100ea6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP8_IP3_PKT_W1S"     ,	   0x10701010a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP9_IP3_PKT_W1S"     ,	   0x10701012a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP10_IP3_PKT_W1S"    ,	   0x10701014a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP11_IP3_PKT_W1S"    ,	   0x10701016a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP12_IP3_PKT_W1S"    ,	   0x10701018a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP13_IP3_PKT_W1S"    ,	   0x1070101aa6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP14_IP3_PKT_W1S"    ,	   0x1070101ca6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP15_IP3_PKT_W1S"    ,	   0x1070101ea6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP16_IP3_PKT_W1S"    ,	   0x10701020a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP17_IP3_PKT_W1S"    ,	   0x10701022a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP18_IP3_PKT_W1S"    ,	   0x10701024a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP19_IP3_PKT_W1S"    ,	   0x10701026a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP20_IP3_PKT_W1S"    ,	   0x10701028a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP21_IP3_PKT_W1S"    ,	   0x1070102aa6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP22_IP3_PKT_W1S"    ,	   0x1070102ca6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP23_IP3_PKT_W1S"    ,	   0x1070102ea6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP24_IP3_PKT_W1S"    ,	   0x10701030a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP25_IP3_PKT_W1S"    ,	   0x10701032a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP26_IP3_PKT_W1S"    ,	   0x10701034a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP27_IP3_PKT_W1S"    ,	   0x10701036a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP28_IP3_PKT_W1S"    ,	   0x10701038a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP29_IP3_PKT_W1S"    ,	   0x1070103aa6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP30_IP3_PKT_W1S"    ,	   0x1070103ca6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP31_IP3_PKT_W1S"    ,	   0x1070103ea6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP0_IP3_RML"         ,	   0x1070100092200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP1_IP3_RML"         ,	   0x1070100292200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP2_IP3_RML"         ,	   0x1070100492200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP3_IP3_RML"         ,	   0x1070100692200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP4_IP3_RML"         ,	   0x1070100892200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP5_IP3_RML"         ,	   0x1070100a92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP6_IP3_RML"         ,	   0x1070100c92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP7_IP3_RML"         ,	   0x1070100e92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP8_IP3_RML"         ,	   0x1070101092200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP9_IP3_RML"         ,	   0x1070101292200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP10_IP3_RML"        ,	   0x1070101492200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP11_IP3_RML"        ,	   0x1070101692200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP12_IP3_RML"        ,	   0x1070101892200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP13_IP3_RML"        ,	   0x1070101a92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP14_IP3_RML"        ,	   0x1070101c92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP15_IP3_RML"        ,	   0x1070101e92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP16_IP3_RML"        ,	   0x1070102092200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP17_IP3_RML"        ,	   0x1070102292200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP18_IP3_RML"        ,	   0x1070102492200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP19_IP3_RML"        ,	   0x1070102692200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP20_IP3_RML"        ,	   0x1070102892200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP21_IP3_RML"        ,	   0x1070102a92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP22_IP3_RML"        ,	   0x1070102c92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP23_IP3_RML"        ,	   0x1070102e92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP24_IP3_RML"        ,	   0x1070103092200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP25_IP3_RML"        ,	   0x1070103292200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP26_IP3_RML"        ,	   0x1070103492200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP27_IP3_RML"        ,	   0x1070103692200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP28_IP3_RML"        ,	   0x1070103892200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP29_IP3_RML"        ,	   0x1070103a92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP30_IP3_RML"        ,	   0x1070103c92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP31_IP3_RML"        ,	   0x1070103e92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP0_IP3_RML_W1C"     ,	   0x10701000b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP1_IP3_RML_W1C"     ,	   0x10701002b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP2_IP3_RML_W1C"     ,	   0x10701004b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP3_IP3_RML_W1C"     ,	   0x10701006b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP4_IP3_RML_W1C"     ,	   0x10701008b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP5_IP3_RML_W1C"     ,	   0x1070100ab2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP6_IP3_RML_W1C"     ,	   0x1070100cb2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP7_IP3_RML_W1C"     ,	   0x1070100eb2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP8_IP3_RML_W1C"     ,	   0x10701010b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP9_IP3_RML_W1C"     ,	   0x10701012b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP10_IP3_RML_W1C"    ,	   0x10701014b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP11_IP3_RML_W1C"    ,	   0x10701016b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP12_IP3_RML_W1C"    ,	   0x10701018b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP13_IP3_RML_W1C"    ,	   0x1070101ab2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP14_IP3_RML_W1C"    ,	   0x1070101cb2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP15_IP3_RML_W1C"    ,	   0x1070101eb2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP16_IP3_RML_W1C"    ,	   0x10701020b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP17_IP3_RML_W1C"    ,	   0x10701022b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP18_IP3_RML_W1C"    ,	   0x10701024b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP19_IP3_RML_W1C"    ,	   0x10701026b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP20_IP3_RML_W1C"    ,	   0x10701028b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP21_IP3_RML_W1C"    ,	   0x1070102ab2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP22_IP3_RML_W1C"    ,	   0x1070102cb2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP23_IP3_RML_W1C"    ,	   0x1070102eb2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP24_IP3_RML_W1C"    ,	   0x10701030b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP25_IP3_RML_W1C"    ,	   0x10701032b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP26_IP3_RML_W1C"    ,	   0x10701034b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP27_IP3_RML_W1C"    ,	   0x10701036b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP28_IP3_RML_W1C"    ,	   0x10701038b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP29_IP3_RML_W1C"    ,	   0x1070103ab2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP30_IP3_RML_W1C"    ,	   0x1070103cb2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP31_IP3_RML_W1C"    ,	   0x1070103eb2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP0_IP3_RML_W1S"     ,	   0x10701000a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP1_IP3_RML_W1S"     ,	   0x10701002a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP2_IP3_RML_W1S"     ,	   0x10701004a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP3_IP3_RML_W1S"     ,	   0x10701006a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP4_IP3_RML_W1S"     ,	   0x10701008a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP5_IP3_RML_W1S"     ,	   0x1070100aa2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP6_IP3_RML_W1S"     ,	   0x1070100ca2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP7_IP3_RML_W1S"     ,	   0x1070100ea2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP8_IP3_RML_W1S"     ,	   0x10701010a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP9_IP3_RML_W1S"     ,	   0x10701012a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP10_IP3_RML_W1S"    ,	   0x10701014a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP11_IP3_RML_W1S"    ,	   0x10701016a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP12_IP3_RML_W1S"    ,	   0x10701018a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP13_IP3_RML_W1S"    ,	   0x1070101aa2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP14_IP3_RML_W1S"    ,	   0x1070101ca2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP15_IP3_RML_W1S"    ,	   0x1070101ea2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP16_IP3_RML_W1S"    ,	   0x10701020a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP17_IP3_RML_W1S"    ,	   0x10701022a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP18_IP3_RML_W1S"    ,	   0x10701024a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP19_IP3_RML_W1S"    ,	   0x10701026a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP20_IP3_RML_W1S"    ,	   0x10701028a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP21_IP3_RML_W1S"    ,	   0x1070102aa2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP22_IP3_RML_W1S"    ,	   0x1070102ca2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP23_IP3_RML_W1S"    ,	   0x1070102ea2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP24_IP3_RML_W1S"    ,	   0x10701030a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP25_IP3_RML_W1S"    ,	   0x10701032a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP26_IP3_RML_W1S"    ,	   0x10701034a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP27_IP3_RML_W1S"    ,	   0x10701036a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP28_IP3_RML_W1S"    ,	   0x10701038a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP29_IP3_RML_W1S"    ,	   0x1070103aa2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP30_IP3_RML_W1S"    ,	   0x1070103ca2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP31_IP3_RML_W1S"    ,	   0x1070103ea2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP0_IP3_WDOG"        ,	   0x1070100091200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP1_IP3_WDOG"        ,	   0x1070100291200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP2_IP3_WDOG"        ,	   0x1070100491200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP3_IP3_WDOG"        ,	   0x1070100691200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP4_IP3_WDOG"        ,	   0x1070100891200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP5_IP3_WDOG"        ,	   0x1070100a91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP6_IP3_WDOG"        ,	   0x1070100c91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP7_IP3_WDOG"        ,	   0x1070100e91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP8_IP3_WDOG"        ,	   0x1070101091200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP9_IP3_WDOG"        ,	   0x1070101291200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP10_IP3_WDOG"       ,	   0x1070101491200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP11_IP3_WDOG"       ,	   0x1070101691200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP12_IP3_WDOG"       ,	   0x1070101891200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP13_IP3_WDOG"       ,	   0x1070101a91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP14_IP3_WDOG"       ,	   0x1070101c91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP15_IP3_WDOG"       ,	   0x1070101e91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP16_IP3_WDOG"       ,	   0x1070102091200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP17_IP3_WDOG"       ,	   0x1070102291200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP18_IP3_WDOG"       ,	   0x1070102491200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP19_IP3_WDOG"       ,	   0x1070102691200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP20_IP3_WDOG"       ,	   0x1070102891200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP21_IP3_WDOG"       ,	   0x1070102a91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP22_IP3_WDOG"       ,	   0x1070102c91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP23_IP3_WDOG"       ,	   0x1070102e91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP24_IP3_WDOG"       ,	   0x1070103091200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP25_IP3_WDOG"       ,	   0x1070103291200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP26_IP3_WDOG"       ,	   0x1070103491200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP27_IP3_WDOG"       ,	   0x1070103691200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP28_IP3_WDOG"       ,	   0x1070103891200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP29_IP3_WDOG"       ,	   0x1070103a91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP30_IP3_WDOG"       ,	   0x1070103c91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP31_IP3_WDOG"       ,	   0x1070103e91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP0_IP3_WDOG_W1C"    ,	   0x10701000b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP1_IP3_WDOG_W1C"    ,	   0x10701002b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP2_IP3_WDOG_W1C"    ,	   0x10701004b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP3_IP3_WDOG_W1C"    ,	   0x10701006b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP4_IP3_WDOG_W1C"    ,	   0x10701008b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP5_IP3_WDOG_W1C"    ,	   0x1070100ab1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP6_IP3_WDOG_W1C"    ,	   0x1070100cb1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP7_IP3_WDOG_W1C"    ,	   0x1070100eb1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP8_IP3_WDOG_W1C"    ,	   0x10701010b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP9_IP3_WDOG_W1C"    ,	   0x10701012b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP10_IP3_WDOG_W1C"   ,	   0x10701014b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP11_IP3_WDOG_W1C"   ,	   0x10701016b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP12_IP3_WDOG_W1C"   ,	   0x10701018b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP13_IP3_WDOG_W1C"   ,	   0x1070101ab1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP14_IP3_WDOG_W1C"   ,	   0x1070101cb1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP15_IP3_WDOG_W1C"   ,	   0x1070101eb1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP16_IP3_WDOG_W1C"   ,	   0x10701020b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP17_IP3_WDOG_W1C"   ,	   0x10701022b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP18_IP3_WDOG_W1C"   ,	   0x10701024b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP19_IP3_WDOG_W1C"   ,	   0x10701026b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP20_IP3_WDOG_W1C"   ,	   0x10701028b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP21_IP3_WDOG_W1C"   ,	   0x1070102ab1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP22_IP3_WDOG_W1C"   ,	   0x1070102cb1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP23_IP3_WDOG_W1C"   ,	   0x1070102eb1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP24_IP3_WDOG_W1C"   ,	   0x10701030b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP25_IP3_WDOG_W1C"   ,	   0x10701032b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP26_IP3_WDOG_W1C"   ,	   0x10701034b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP27_IP3_WDOG_W1C"   ,	   0x10701036b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP28_IP3_WDOG_W1C"   ,	   0x10701038b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP29_IP3_WDOG_W1C"   ,	   0x1070103ab1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP30_IP3_WDOG_W1C"   ,	   0x1070103cb1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP31_IP3_WDOG_W1C"   ,	   0x1070103eb1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP0_IP3_WDOG_W1S"    ,	   0x10701000a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP1_IP3_WDOG_W1S"    ,	   0x10701002a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP2_IP3_WDOG_W1S"    ,	   0x10701004a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP3_IP3_WDOG_W1S"    ,	   0x10701006a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP4_IP3_WDOG_W1S"    ,	   0x10701008a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP5_IP3_WDOG_W1S"    ,	   0x1070100aa1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP6_IP3_WDOG_W1S"    ,	   0x1070100ca1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP7_IP3_WDOG_W1S"    ,	   0x1070100ea1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP8_IP3_WDOG_W1S"    ,	   0x10701010a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP9_IP3_WDOG_W1S"    ,	   0x10701012a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP10_IP3_WDOG_W1S"   ,	   0x10701014a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP11_IP3_WDOG_W1S"   ,	   0x10701016a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP12_IP3_WDOG_W1S"   ,	   0x10701018a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP13_IP3_WDOG_W1S"   ,	   0x1070101aa1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP14_IP3_WDOG_W1S"   ,	   0x1070101ca1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP15_IP3_WDOG_W1S"   ,	   0x1070101ea1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP16_IP3_WDOG_W1S"   ,	   0x10701020a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP17_IP3_WDOG_W1S"   ,	   0x10701022a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP18_IP3_WDOG_W1S"   ,	   0x10701024a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP19_IP3_WDOG_W1S"   ,	   0x10701026a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP20_IP3_WDOG_W1S"   ,	   0x10701028a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP21_IP3_WDOG_W1S"   ,	   0x1070102aa1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP22_IP3_WDOG_W1S"   ,	   0x1070102ca1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP23_IP3_WDOG_W1S"   ,	   0x1070102ea1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP24_IP3_WDOG_W1S"   ,	   0x10701030a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP25_IP3_WDOG_W1S"   ,	   0x10701032a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP26_IP3_WDOG_W1S"   ,	   0x10701034a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP27_IP3_WDOG_W1S"   ,	   0x10701036a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP28_IP3_WDOG_W1S"   ,	   0x10701038a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP29_IP3_WDOG_W1S"   ,	   0x1070103aa1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP30_IP3_WDOG_W1S"   ,	   0x1070103ca1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP31_IP3_WDOG_W1S"   ,	   0x1070103ea1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP0_IP3_WRKQ"        ,	   0x1070100090200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP1_IP3_WRKQ"        ,	   0x1070100290200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP2_IP3_WRKQ"        ,	   0x1070100490200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP3_IP3_WRKQ"        ,	   0x1070100690200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP4_IP3_WRKQ"        ,	   0x1070100890200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP5_IP3_WRKQ"        ,	   0x1070100a90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP6_IP3_WRKQ"        ,	   0x1070100c90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP7_IP3_WRKQ"        ,	   0x1070100e90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP8_IP3_WRKQ"        ,	   0x1070101090200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP9_IP3_WRKQ"        ,	   0x1070101290200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP10_IP3_WRKQ"       ,	   0x1070101490200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP11_IP3_WRKQ"       ,	   0x1070101690200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP12_IP3_WRKQ"       ,	   0x1070101890200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP13_IP3_WRKQ"       ,	   0x1070101a90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP14_IP3_WRKQ"       ,	   0x1070101c90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP15_IP3_WRKQ"       ,	   0x1070101e90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP16_IP3_WRKQ"       ,	   0x1070102090200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP17_IP3_WRKQ"       ,	   0x1070102290200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP18_IP3_WRKQ"       ,	   0x1070102490200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP19_IP3_WRKQ"       ,	   0x1070102690200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP20_IP3_WRKQ"       ,	   0x1070102890200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP21_IP3_WRKQ"       ,	   0x1070102a90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP22_IP3_WRKQ"       ,	   0x1070102c90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP23_IP3_WRKQ"       ,	   0x1070102e90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP24_IP3_WRKQ"       ,	   0x1070103090200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP25_IP3_WRKQ"       ,	   0x1070103290200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP26_IP3_WRKQ"       ,	   0x1070103490200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP27_IP3_WRKQ"       ,	   0x1070103690200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP28_IP3_WRKQ"       ,	   0x1070103890200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP29_IP3_WRKQ"       ,	   0x1070103a90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP30_IP3_WRKQ"       ,	   0x1070103c90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP31_IP3_WRKQ"       ,	   0x1070103e90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP0_IP3_WRKQ_W1C"    ,	   0x10701000b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP1_IP3_WRKQ_W1C"    ,	   0x10701002b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP2_IP3_WRKQ_W1C"    ,	   0x10701004b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP3_IP3_WRKQ_W1C"    ,	   0x10701006b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP4_IP3_WRKQ_W1C"    ,	   0x10701008b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP5_IP3_WRKQ_W1C"    ,	   0x1070100ab0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP6_IP3_WRKQ_W1C"    ,	   0x1070100cb0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP7_IP3_WRKQ_W1C"    ,	   0x1070100eb0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP8_IP3_WRKQ_W1C"    ,	   0x10701010b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP9_IP3_WRKQ_W1C"    ,	   0x10701012b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP10_IP3_WRKQ_W1C"   ,	   0x10701014b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP11_IP3_WRKQ_W1C"   ,	   0x10701016b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP12_IP3_WRKQ_W1C"   ,	   0x10701018b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP13_IP3_WRKQ_W1C"   ,	   0x1070101ab0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP14_IP3_WRKQ_W1C"   ,	   0x1070101cb0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP15_IP3_WRKQ_W1C"   ,	   0x1070101eb0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP16_IP3_WRKQ_W1C"   ,	   0x10701020b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP17_IP3_WRKQ_W1C"   ,	   0x10701022b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP18_IP3_WRKQ_W1C"   ,	   0x10701024b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP19_IP3_WRKQ_W1C"   ,	   0x10701026b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP20_IP3_WRKQ_W1C"   ,	   0x10701028b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP21_IP3_WRKQ_W1C"   ,	   0x1070102ab0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP22_IP3_WRKQ_W1C"   ,	   0x1070102cb0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP23_IP3_WRKQ_W1C"   ,	   0x1070102eb0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP24_IP3_WRKQ_W1C"   ,	   0x10701030b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP25_IP3_WRKQ_W1C"   ,	   0x10701032b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP26_IP3_WRKQ_W1C"   ,	   0x10701034b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP27_IP3_WRKQ_W1C"   ,	   0x10701036b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP28_IP3_WRKQ_W1C"   ,	   0x10701038b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP29_IP3_WRKQ_W1C"   ,	   0x1070103ab0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP30_IP3_WRKQ_W1C"   ,	   0x1070103cb0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP31_IP3_WRKQ_W1C"   ,	   0x1070103eb0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP0_IP3_WRKQ_W1S"    ,	   0x10701000a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP1_IP3_WRKQ_W1S"    ,	   0x10701002a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP2_IP3_WRKQ_W1S"    ,	   0x10701004a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP3_IP3_WRKQ_W1S"    ,	   0x10701006a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP4_IP3_WRKQ_W1S"    ,	   0x10701008a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP5_IP3_WRKQ_W1S"    ,	   0x1070100aa0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP6_IP3_WRKQ_W1S"    ,	   0x1070100ca0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP7_IP3_WRKQ_W1S"    ,	   0x1070100ea0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP8_IP3_WRKQ_W1S"    ,	   0x10701010a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP9_IP3_WRKQ_W1S"    ,	   0x10701012a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP10_IP3_WRKQ_W1S"   ,	   0x10701014a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP11_IP3_WRKQ_W1S"   ,	   0x10701016a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP12_IP3_WRKQ_W1S"   ,	   0x10701018a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP13_IP3_WRKQ_W1S"   ,	   0x1070101aa0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP14_IP3_WRKQ_W1S"   ,	   0x1070101ca0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP15_IP3_WRKQ_W1S"   ,	   0x1070101ea0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP16_IP3_WRKQ_W1S"   ,	   0x10701020a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP17_IP3_WRKQ_W1S"   ,	   0x10701022a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP18_IP3_WRKQ_W1S"   ,	   0x10701024a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP19_IP3_WRKQ_W1S"   ,	   0x10701026a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP20_IP3_WRKQ_W1S"   ,	   0x10701028a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP21_IP3_WRKQ_W1S"   ,	   0x1070102aa0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP22_IP3_WRKQ_W1S"   ,	   0x1070102ca0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP23_IP3_WRKQ_W1S"   ,	   0x1070102ea0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP24_IP3_WRKQ_W1S"   ,	   0x10701030a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP25_IP3_WRKQ_W1S"   ,	   0x10701032a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP26_IP3_WRKQ_W1S"   ,	   0x10701034a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP27_IP3_WRKQ_W1S"   ,	   0x10701036a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP28_IP3_WRKQ_W1S"   ,	   0x10701038a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP29_IP3_WRKQ_W1S"   ,	   0x1070103aa0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP30_IP3_WRKQ_W1S"   ,	   0x1070103ca0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP31_IP3_WRKQ_W1S"   ,	   0x1070103ea0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP0_IP4_GPIO"        ,	   0x1070100097400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP1_IP4_GPIO"        ,	   0x1070100297400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP2_IP4_GPIO"        ,	   0x1070100497400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP3_IP4_GPIO"        ,	   0x1070100697400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP4_IP4_GPIO"        ,	   0x1070100897400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP5_IP4_GPIO"        ,	   0x1070100a97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP6_IP4_GPIO"        ,	   0x1070100c97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP7_IP4_GPIO"        ,	   0x1070100e97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP8_IP4_GPIO"        ,	   0x1070101097400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP9_IP4_GPIO"        ,	   0x1070101297400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP10_IP4_GPIO"       ,	   0x1070101497400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP11_IP4_GPIO"       ,	   0x1070101697400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP12_IP4_GPIO"       ,	   0x1070101897400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP13_IP4_GPIO"       ,	   0x1070101a97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP14_IP4_GPIO"       ,	   0x1070101c97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP15_IP4_GPIO"       ,	   0x1070101e97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP16_IP4_GPIO"       ,	   0x1070102097400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP17_IP4_GPIO"       ,	   0x1070102297400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP18_IP4_GPIO"       ,	   0x1070102497400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP19_IP4_GPIO"       ,	   0x1070102697400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP20_IP4_GPIO"       ,	   0x1070102897400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP21_IP4_GPIO"       ,	   0x1070102a97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP22_IP4_GPIO"       ,	   0x1070102c97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP23_IP4_GPIO"       ,	   0x1070102e97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP24_IP4_GPIO"       ,	   0x1070103097400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP25_IP4_GPIO"       ,	   0x1070103297400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP26_IP4_GPIO"       ,	   0x1070103497400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP27_IP4_GPIO"       ,	   0x1070103697400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP28_IP4_GPIO"       ,	   0x1070103897400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP29_IP4_GPIO"       ,	   0x1070103a97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP30_IP4_GPIO"       ,	   0x1070103c97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP31_IP4_GPIO"       ,	   0x1070103e97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP0_IP4_GPIO_W1C"    ,	   0x10701000b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP1_IP4_GPIO_W1C"    ,	   0x10701002b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP2_IP4_GPIO_W1C"    ,	   0x10701004b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP3_IP4_GPIO_W1C"    ,	   0x10701006b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP4_IP4_GPIO_W1C"    ,	   0x10701008b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP5_IP4_GPIO_W1C"    ,	   0x1070100ab7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP6_IP4_GPIO_W1C"    ,	   0x1070100cb7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP7_IP4_GPIO_W1C"    ,	   0x1070100eb7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP8_IP4_GPIO_W1C"    ,	   0x10701010b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP9_IP4_GPIO_W1C"    ,	   0x10701012b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP10_IP4_GPIO_W1C"   ,	   0x10701014b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP11_IP4_GPIO_W1C"   ,	   0x10701016b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP12_IP4_GPIO_W1C"   ,	   0x10701018b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP13_IP4_GPIO_W1C"   ,	   0x1070101ab7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP14_IP4_GPIO_W1C"   ,	   0x1070101cb7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP15_IP4_GPIO_W1C"   ,	   0x1070101eb7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP16_IP4_GPIO_W1C"   ,	   0x10701020b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP17_IP4_GPIO_W1C"   ,	   0x10701022b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP18_IP4_GPIO_W1C"   ,	   0x10701024b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP19_IP4_GPIO_W1C"   ,	   0x10701026b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP20_IP4_GPIO_W1C"   ,	   0x10701028b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP21_IP4_GPIO_W1C"   ,	   0x1070102ab7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP22_IP4_GPIO_W1C"   ,	   0x1070102cb7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP23_IP4_GPIO_W1C"   ,	   0x1070102eb7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP24_IP4_GPIO_W1C"   ,	   0x10701030b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP25_IP4_GPIO_W1C"   ,	   0x10701032b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP26_IP4_GPIO_W1C"   ,	   0x10701034b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP27_IP4_GPIO_W1C"   ,	   0x10701036b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP28_IP4_GPIO_W1C"   ,	   0x10701038b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP29_IP4_GPIO_W1C"   ,	   0x1070103ab7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP30_IP4_GPIO_W1C"   ,	   0x1070103cb7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP31_IP4_GPIO_W1C"   ,	   0x1070103eb7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP0_IP4_GPIO_W1S"    ,	   0x10701000a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP1_IP4_GPIO_W1S"    ,	   0x10701002a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP2_IP4_GPIO_W1S"    ,	   0x10701004a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP3_IP4_GPIO_W1S"    ,	   0x10701006a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP4_IP4_GPIO_W1S"    ,	   0x10701008a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP5_IP4_GPIO_W1S"    ,	   0x1070100aa7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP6_IP4_GPIO_W1S"    ,	   0x1070100ca7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP7_IP4_GPIO_W1S"    ,	   0x1070100ea7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP8_IP4_GPIO_W1S"    ,	   0x10701010a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP9_IP4_GPIO_W1S"    ,	   0x10701012a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP10_IP4_GPIO_W1S"   ,	   0x10701014a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP11_IP4_GPIO_W1S"   ,	   0x10701016a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP12_IP4_GPIO_W1S"   ,	   0x10701018a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP13_IP4_GPIO_W1S"   ,	   0x1070101aa7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP14_IP4_GPIO_W1S"   ,	   0x1070101ca7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP15_IP4_GPIO_W1S"   ,	   0x1070101ea7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP16_IP4_GPIO_W1S"   ,	   0x10701020a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP17_IP4_GPIO_W1S"   ,	   0x10701022a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP18_IP4_GPIO_W1S"   ,	   0x10701024a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP19_IP4_GPIO_W1S"   ,	   0x10701026a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP20_IP4_GPIO_W1S"   ,	   0x10701028a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP21_IP4_GPIO_W1S"   ,	   0x1070102aa7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP22_IP4_GPIO_W1S"   ,	   0x1070102ca7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP23_IP4_GPIO_W1S"   ,	   0x1070102ea7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP24_IP4_GPIO_W1S"   ,	   0x10701030a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP25_IP4_GPIO_W1S"   ,	   0x10701032a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP26_IP4_GPIO_W1S"   ,	   0x10701034a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP27_IP4_GPIO_W1S"   ,	   0x10701036a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP28_IP4_GPIO_W1S"   ,	   0x10701038a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP29_IP4_GPIO_W1S"   ,	   0x1070103aa7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP30_IP4_GPIO_W1S"   ,	   0x1070103ca7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP31_IP4_GPIO_W1S"   ,	   0x1070103ea7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP0_IP4_IO"          ,	   0x1070100094400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP1_IP4_IO"          ,	   0x1070100294400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP2_IP4_IO"          ,	   0x1070100494400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP3_IP4_IO"          ,	   0x1070100694400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP4_IP4_IO"          ,	   0x1070100894400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP5_IP4_IO"          ,	   0x1070100a94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP6_IP4_IO"          ,	   0x1070100c94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP7_IP4_IO"          ,	   0x1070100e94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP8_IP4_IO"          ,	   0x1070101094400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP9_IP4_IO"          ,	   0x1070101294400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP10_IP4_IO"         ,	   0x1070101494400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP11_IP4_IO"         ,	   0x1070101694400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP12_IP4_IO"         ,	   0x1070101894400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP13_IP4_IO"         ,	   0x1070101a94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP14_IP4_IO"         ,	   0x1070101c94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP15_IP4_IO"         ,	   0x1070101e94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP16_IP4_IO"         ,	   0x1070102094400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP17_IP4_IO"         ,	   0x1070102294400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP18_IP4_IO"         ,	   0x1070102494400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP19_IP4_IO"         ,	   0x1070102694400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP20_IP4_IO"         ,	   0x1070102894400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP21_IP4_IO"         ,	   0x1070102a94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP22_IP4_IO"         ,	   0x1070102c94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP23_IP4_IO"         ,	   0x1070102e94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP24_IP4_IO"         ,	   0x1070103094400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP25_IP4_IO"         ,	   0x1070103294400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP26_IP4_IO"         ,	   0x1070103494400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP27_IP4_IO"         ,	   0x1070103694400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP28_IP4_IO"         ,	   0x1070103894400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP29_IP4_IO"         ,	   0x1070103a94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP30_IP4_IO"         ,	   0x1070103c94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP31_IP4_IO"         ,	   0x1070103e94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP0_IP4_IO_W1C"      ,	   0x10701000b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP1_IP4_IO_W1C"      ,	   0x10701002b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP2_IP4_IO_W1C"      ,	   0x10701004b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP3_IP4_IO_W1C"      ,	   0x10701006b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP4_IP4_IO_W1C"      ,	   0x10701008b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP5_IP4_IO_W1C"      ,	   0x1070100ab4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP6_IP4_IO_W1C"      ,	   0x1070100cb4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP7_IP4_IO_W1C"      ,	   0x1070100eb4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP8_IP4_IO_W1C"      ,	   0x10701010b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP9_IP4_IO_W1C"      ,	   0x10701012b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP10_IP4_IO_W1C"     ,	   0x10701014b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP11_IP4_IO_W1C"     ,	   0x10701016b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP12_IP4_IO_W1C"     ,	   0x10701018b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP13_IP4_IO_W1C"     ,	   0x1070101ab4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP14_IP4_IO_W1C"     ,	   0x1070101cb4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP15_IP4_IO_W1C"     ,	   0x1070101eb4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP16_IP4_IO_W1C"     ,	   0x10701020b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP17_IP4_IO_W1C"     ,	   0x10701022b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP18_IP4_IO_W1C"     ,	   0x10701024b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP19_IP4_IO_W1C"     ,	   0x10701026b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP20_IP4_IO_W1C"     ,	   0x10701028b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP21_IP4_IO_W1C"     ,	   0x1070102ab4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP22_IP4_IO_W1C"     ,	   0x1070102cb4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP23_IP4_IO_W1C"     ,	   0x1070102eb4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP24_IP4_IO_W1C"     ,	   0x10701030b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP25_IP4_IO_W1C"     ,	   0x10701032b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP26_IP4_IO_W1C"     ,	   0x10701034b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP27_IP4_IO_W1C"     ,	   0x10701036b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP28_IP4_IO_W1C"     ,	   0x10701038b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP29_IP4_IO_W1C"     ,	   0x1070103ab4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP30_IP4_IO_W1C"     ,	   0x1070103cb4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP31_IP4_IO_W1C"     ,	   0x1070103eb4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP0_IP4_IO_W1S"      ,	   0x10701000a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP1_IP4_IO_W1S"      ,	   0x10701002a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP2_IP4_IO_W1S"      ,	   0x10701004a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP3_IP4_IO_W1S"      ,	   0x10701006a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP4_IP4_IO_W1S"      ,	   0x10701008a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP5_IP4_IO_W1S"      ,	   0x1070100aa4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP6_IP4_IO_W1S"      ,	   0x1070100ca4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP7_IP4_IO_W1S"      ,	   0x1070100ea4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP8_IP4_IO_W1S"      ,	   0x10701010a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP9_IP4_IO_W1S"      ,	   0x10701012a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP10_IP4_IO_W1S"     ,	   0x10701014a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP11_IP4_IO_W1S"     ,	   0x10701016a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP12_IP4_IO_W1S"     ,	   0x10701018a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP13_IP4_IO_W1S"     ,	   0x1070101aa4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP14_IP4_IO_W1S"     ,	   0x1070101ca4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP15_IP4_IO_W1S"     ,	   0x1070101ea4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP16_IP4_IO_W1S"     ,	   0x10701020a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP17_IP4_IO_W1S"     ,	   0x10701022a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP18_IP4_IO_W1S"     ,	   0x10701024a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP19_IP4_IO_W1S"     ,	   0x10701026a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP20_IP4_IO_W1S"     ,	   0x10701028a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP21_IP4_IO_W1S"     ,	   0x1070102aa4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP22_IP4_IO_W1S"     ,	   0x1070102ca4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP23_IP4_IO_W1S"     ,	   0x1070102ea4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP24_IP4_IO_W1S"     ,	   0x10701030a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP25_IP4_IO_W1S"     ,	   0x10701032a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP26_IP4_IO_W1S"     ,	   0x10701034a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP27_IP4_IO_W1S"     ,	   0x10701036a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP28_IP4_IO_W1S"     ,	   0x10701038a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP29_IP4_IO_W1S"     ,	   0x1070103aa4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP30_IP4_IO_W1S"     ,	   0x1070103ca4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP31_IP4_IO_W1S"     ,	   0x1070103ea4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP0_IP4_MBOX"        ,	   0x1070100098400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP1_IP4_MBOX"        ,	   0x1070100298400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP2_IP4_MBOX"        ,	   0x1070100498400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP3_IP4_MBOX"        ,	   0x1070100698400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP4_IP4_MBOX"        ,	   0x1070100898400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP5_IP4_MBOX"        ,	   0x1070100a98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP6_IP4_MBOX"        ,	   0x1070100c98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP7_IP4_MBOX"        ,	   0x1070100e98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP8_IP4_MBOX"        ,	   0x1070101098400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP9_IP4_MBOX"        ,	   0x1070101298400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP10_IP4_MBOX"       ,	   0x1070101498400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP11_IP4_MBOX"       ,	   0x1070101698400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP12_IP4_MBOX"       ,	   0x1070101898400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP13_IP4_MBOX"       ,	   0x1070101a98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP14_IP4_MBOX"       ,	   0x1070101c98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP15_IP4_MBOX"       ,	   0x1070101e98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP16_IP4_MBOX"       ,	   0x1070102098400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP17_IP4_MBOX"       ,	   0x1070102298400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP18_IP4_MBOX"       ,	   0x1070102498400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP19_IP4_MBOX"       ,	   0x1070102698400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP20_IP4_MBOX"       ,	   0x1070102898400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP21_IP4_MBOX"       ,	   0x1070102a98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP22_IP4_MBOX"       ,	   0x1070102c98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP23_IP4_MBOX"       ,	   0x1070102e98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP24_IP4_MBOX"       ,	   0x1070103098400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP25_IP4_MBOX"       ,	   0x1070103298400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP26_IP4_MBOX"       ,	   0x1070103498400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP27_IP4_MBOX"       ,	   0x1070103698400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP28_IP4_MBOX"       ,	   0x1070103898400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP29_IP4_MBOX"       ,	   0x1070103a98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP30_IP4_MBOX"       ,	   0x1070103c98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP31_IP4_MBOX"       ,	   0x1070103e98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP0_IP4_MBOX_W1C"    ,	   0x10701000b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP1_IP4_MBOX_W1C"    ,	   0x10701002b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP2_IP4_MBOX_W1C"    ,	   0x10701004b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP3_IP4_MBOX_W1C"    ,	   0x10701006b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP4_IP4_MBOX_W1C"    ,	   0x10701008b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP5_IP4_MBOX_W1C"    ,	   0x1070100ab8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP6_IP4_MBOX_W1C"    ,	   0x1070100cb8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP7_IP4_MBOX_W1C"    ,	   0x1070100eb8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP8_IP4_MBOX_W1C"    ,	   0x10701010b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP9_IP4_MBOX_W1C"    ,	   0x10701012b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP10_IP4_MBOX_W1C"   ,	   0x10701014b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP11_IP4_MBOX_W1C"   ,	   0x10701016b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP12_IP4_MBOX_W1C"   ,	   0x10701018b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP13_IP4_MBOX_W1C"   ,	   0x1070101ab8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP14_IP4_MBOX_W1C"   ,	   0x1070101cb8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP15_IP4_MBOX_W1C"   ,	   0x1070101eb8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP16_IP4_MBOX_W1C"   ,	   0x10701020b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP17_IP4_MBOX_W1C"   ,	   0x10701022b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP18_IP4_MBOX_W1C"   ,	   0x10701024b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP19_IP4_MBOX_W1C"   ,	   0x10701026b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP20_IP4_MBOX_W1C"   ,	   0x10701028b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP21_IP4_MBOX_W1C"   ,	   0x1070102ab8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP22_IP4_MBOX_W1C"   ,	   0x1070102cb8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP23_IP4_MBOX_W1C"   ,	   0x1070102eb8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP24_IP4_MBOX_W1C"   ,	   0x10701030b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP25_IP4_MBOX_W1C"   ,	   0x10701032b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP26_IP4_MBOX_W1C"   ,	   0x10701034b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP27_IP4_MBOX_W1C"   ,	   0x10701036b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP28_IP4_MBOX_W1C"   ,	   0x10701038b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP29_IP4_MBOX_W1C"   ,	   0x1070103ab8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP30_IP4_MBOX_W1C"   ,	   0x1070103cb8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP31_IP4_MBOX_W1C"   ,	   0x1070103eb8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP0_IP4_MBOX_W1S"    ,	   0x10701000a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP1_IP4_MBOX_W1S"    ,	   0x10701002a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP2_IP4_MBOX_W1S"    ,	   0x10701004a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP3_IP4_MBOX_W1S"    ,	   0x10701006a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP4_IP4_MBOX_W1S"    ,	   0x10701008a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP5_IP4_MBOX_W1S"    ,	   0x1070100aa8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP6_IP4_MBOX_W1S"    ,	   0x1070100ca8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP7_IP4_MBOX_W1S"    ,	   0x1070100ea8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP8_IP4_MBOX_W1S"    ,	   0x10701010a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP9_IP4_MBOX_W1S"    ,	   0x10701012a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP10_IP4_MBOX_W1S"   ,	   0x10701014a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP11_IP4_MBOX_W1S"   ,	   0x10701016a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP12_IP4_MBOX_W1S"   ,	   0x10701018a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP13_IP4_MBOX_W1S"   ,	   0x1070101aa8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP14_IP4_MBOX_W1S"   ,	   0x1070101ca8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP15_IP4_MBOX_W1S"   ,	   0x1070101ea8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP16_IP4_MBOX_W1S"   ,	   0x10701020a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP17_IP4_MBOX_W1S"   ,	   0x10701022a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP18_IP4_MBOX_W1S"   ,	   0x10701024a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP19_IP4_MBOX_W1S"   ,	   0x10701026a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP20_IP4_MBOX_W1S"   ,	   0x10701028a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP21_IP4_MBOX_W1S"   ,	   0x1070102aa8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP22_IP4_MBOX_W1S"   ,	   0x1070102ca8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP23_IP4_MBOX_W1S"   ,	   0x1070102ea8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP24_IP4_MBOX_W1S"   ,	   0x10701030a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP25_IP4_MBOX_W1S"   ,	   0x10701032a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP26_IP4_MBOX_W1S"   ,	   0x10701034a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP27_IP4_MBOX_W1S"   ,	   0x10701036a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP28_IP4_MBOX_W1S"   ,	   0x10701038a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP29_IP4_MBOX_W1S"   ,	   0x1070103aa8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP30_IP4_MBOX_W1S"   ,	   0x1070103ca8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP31_IP4_MBOX_W1S"   ,	   0x1070103ea8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP0_IP4_MEM"         ,	   0x1070100095400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP1_IP4_MEM"         ,	   0x1070100295400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP2_IP4_MEM"         ,	   0x1070100495400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP3_IP4_MEM"         ,	   0x1070100695400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP4_IP4_MEM"         ,	   0x1070100895400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP5_IP4_MEM"         ,	   0x1070100a95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP6_IP4_MEM"         ,	   0x1070100c95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP7_IP4_MEM"         ,	   0x1070100e95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP8_IP4_MEM"         ,	   0x1070101095400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP9_IP4_MEM"         ,	   0x1070101295400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP10_IP4_MEM"        ,	   0x1070101495400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP11_IP4_MEM"        ,	   0x1070101695400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP12_IP4_MEM"        ,	   0x1070101895400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP13_IP4_MEM"        ,	   0x1070101a95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP14_IP4_MEM"        ,	   0x1070101c95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP15_IP4_MEM"        ,	   0x1070101e95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP16_IP4_MEM"        ,	   0x1070102095400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP17_IP4_MEM"        ,	   0x1070102295400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP18_IP4_MEM"        ,	   0x1070102495400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP19_IP4_MEM"        ,	   0x1070102695400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP20_IP4_MEM"        ,	   0x1070102895400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP21_IP4_MEM"        ,	   0x1070102a95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP22_IP4_MEM"        ,	   0x1070102c95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP23_IP4_MEM"        ,	   0x1070102e95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP24_IP4_MEM"        ,	   0x1070103095400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP25_IP4_MEM"        ,	   0x1070103295400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP26_IP4_MEM"        ,	   0x1070103495400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP27_IP4_MEM"        ,	   0x1070103695400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP28_IP4_MEM"        ,	   0x1070103895400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP29_IP4_MEM"        ,	   0x1070103a95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP30_IP4_MEM"        ,	   0x1070103c95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP31_IP4_MEM"        ,	   0x1070103e95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP0_IP4_MEM_W1C"     ,	   0x10701000b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP1_IP4_MEM_W1C"     ,	   0x10701002b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP2_IP4_MEM_W1C"     ,	   0x10701004b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP3_IP4_MEM_W1C"     ,	   0x10701006b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP4_IP4_MEM_W1C"     ,	   0x10701008b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP5_IP4_MEM_W1C"     ,	   0x1070100ab5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP6_IP4_MEM_W1C"     ,	   0x1070100cb5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP7_IP4_MEM_W1C"     ,	   0x1070100eb5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP8_IP4_MEM_W1C"     ,	   0x10701010b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP9_IP4_MEM_W1C"     ,	   0x10701012b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP10_IP4_MEM_W1C"    ,	   0x10701014b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP11_IP4_MEM_W1C"    ,	   0x10701016b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP12_IP4_MEM_W1C"    ,	   0x10701018b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP13_IP4_MEM_W1C"    ,	   0x1070101ab5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP14_IP4_MEM_W1C"    ,	   0x1070101cb5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP15_IP4_MEM_W1C"    ,	   0x1070101eb5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP16_IP4_MEM_W1C"    ,	   0x10701020b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP17_IP4_MEM_W1C"    ,	   0x10701022b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP18_IP4_MEM_W1C"    ,	   0x10701024b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP19_IP4_MEM_W1C"    ,	   0x10701026b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP20_IP4_MEM_W1C"    ,	   0x10701028b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP21_IP4_MEM_W1C"    ,	   0x1070102ab5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP22_IP4_MEM_W1C"    ,	   0x1070102cb5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP23_IP4_MEM_W1C"    ,	   0x1070102eb5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP24_IP4_MEM_W1C"    ,	   0x10701030b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP25_IP4_MEM_W1C"    ,	   0x10701032b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP26_IP4_MEM_W1C"    ,	   0x10701034b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP27_IP4_MEM_W1C"    ,	   0x10701036b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP28_IP4_MEM_W1C"    ,	   0x10701038b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP29_IP4_MEM_W1C"    ,	   0x1070103ab5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP30_IP4_MEM_W1C"    ,	   0x1070103cb5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP31_IP4_MEM_W1C"    ,	   0x1070103eb5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP0_IP4_MEM_W1S"     ,	   0x10701000a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP1_IP4_MEM_W1S"     ,	   0x10701002a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP2_IP4_MEM_W1S"     ,	   0x10701004a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP3_IP4_MEM_W1S"     ,	   0x10701006a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP4_IP4_MEM_W1S"     ,	   0x10701008a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP5_IP4_MEM_W1S"     ,	   0x1070100aa5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP6_IP4_MEM_W1S"     ,	   0x1070100ca5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP7_IP4_MEM_W1S"     ,	   0x1070100ea5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP8_IP4_MEM_W1S"     ,	   0x10701010a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP9_IP4_MEM_W1S"     ,	   0x10701012a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP10_IP4_MEM_W1S"    ,	   0x10701014a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP11_IP4_MEM_W1S"    ,	   0x10701016a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP12_IP4_MEM_W1S"    ,	   0x10701018a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP13_IP4_MEM_W1S"    ,	   0x1070101aa5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP14_IP4_MEM_W1S"    ,	   0x1070101ca5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP15_IP4_MEM_W1S"    ,	   0x1070101ea5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP16_IP4_MEM_W1S"    ,	   0x10701020a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP17_IP4_MEM_W1S"    ,	   0x10701022a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP18_IP4_MEM_W1S"    ,	   0x10701024a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP19_IP4_MEM_W1S"    ,	   0x10701026a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP20_IP4_MEM_W1S"    ,	   0x10701028a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP21_IP4_MEM_W1S"    ,	   0x1070102aa5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP22_IP4_MEM_W1S"    ,	   0x1070102ca5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP23_IP4_MEM_W1S"    ,	   0x1070102ea5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP24_IP4_MEM_W1S"    ,	   0x10701030a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP25_IP4_MEM_W1S"    ,	   0x10701032a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP26_IP4_MEM_W1S"    ,	   0x10701034a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP27_IP4_MEM_W1S"    ,	   0x10701036a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP28_IP4_MEM_W1S"    ,	   0x10701038a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP29_IP4_MEM_W1S"    ,	   0x1070103aa5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP30_IP4_MEM_W1S"    ,	   0x1070103ca5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP31_IP4_MEM_W1S"    ,	   0x1070103ea5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP0_IP4_MIO"         ,	   0x1070100093400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP1_IP4_MIO"         ,	   0x1070100293400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP2_IP4_MIO"         ,	   0x1070100493400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP3_IP4_MIO"         ,	   0x1070100693400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP4_IP4_MIO"         ,	   0x1070100893400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP5_IP4_MIO"         ,	   0x1070100a93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP6_IP4_MIO"         ,	   0x1070100c93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP7_IP4_MIO"         ,	   0x1070100e93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP8_IP4_MIO"         ,	   0x1070101093400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP9_IP4_MIO"         ,	   0x1070101293400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP10_IP4_MIO"        ,	   0x1070101493400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP11_IP4_MIO"        ,	   0x1070101693400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP12_IP4_MIO"        ,	   0x1070101893400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP13_IP4_MIO"        ,	   0x1070101a93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP14_IP4_MIO"        ,	   0x1070101c93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP15_IP4_MIO"        ,	   0x1070101e93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP16_IP4_MIO"        ,	   0x1070102093400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP17_IP4_MIO"        ,	   0x1070102293400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP18_IP4_MIO"        ,	   0x1070102493400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP19_IP4_MIO"        ,	   0x1070102693400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP20_IP4_MIO"        ,	   0x1070102893400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP21_IP4_MIO"        ,	   0x1070102a93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP22_IP4_MIO"        ,	   0x1070102c93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP23_IP4_MIO"        ,	   0x1070102e93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP24_IP4_MIO"        ,	   0x1070103093400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP25_IP4_MIO"        ,	   0x1070103293400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP26_IP4_MIO"        ,	   0x1070103493400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP27_IP4_MIO"        ,	   0x1070103693400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP28_IP4_MIO"        ,	   0x1070103893400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP29_IP4_MIO"        ,	   0x1070103a93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP30_IP4_MIO"        ,	   0x1070103c93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP31_IP4_MIO"        ,	   0x1070103e93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP0_IP4_MIO_W1C"     ,	   0x10701000b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP1_IP4_MIO_W1C"     ,	   0x10701002b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP2_IP4_MIO_W1C"     ,	   0x10701004b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP3_IP4_MIO_W1C"     ,	   0x10701006b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP4_IP4_MIO_W1C"     ,	   0x10701008b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP5_IP4_MIO_W1C"     ,	   0x1070100ab3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP6_IP4_MIO_W1C"     ,	   0x1070100cb3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP7_IP4_MIO_W1C"     ,	   0x1070100eb3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP8_IP4_MIO_W1C"     ,	   0x10701010b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP9_IP4_MIO_W1C"     ,	   0x10701012b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP10_IP4_MIO_W1C"    ,	   0x10701014b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP11_IP4_MIO_W1C"    ,	   0x10701016b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP12_IP4_MIO_W1C"    ,	   0x10701018b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP13_IP4_MIO_W1C"    ,	   0x1070101ab3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP14_IP4_MIO_W1C"    ,	   0x1070101cb3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP15_IP4_MIO_W1C"    ,	   0x1070101eb3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP16_IP4_MIO_W1C"    ,	   0x10701020b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP17_IP4_MIO_W1C"    ,	   0x10701022b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP18_IP4_MIO_W1C"    ,	   0x10701024b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP19_IP4_MIO_W1C"    ,	   0x10701026b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP20_IP4_MIO_W1C"    ,	   0x10701028b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP21_IP4_MIO_W1C"    ,	   0x1070102ab3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP22_IP4_MIO_W1C"    ,	   0x1070102cb3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP23_IP4_MIO_W1C"    ,	   0x1070102eb3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP24_IP4_MIO_W1C"    ,	   0x10701030b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP25_IP4_MIO_W1C"    ,	   0x10701032b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP26_IP4_MIO_W1C"    ,	   0x10701034b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP27_IP4_MIO_W1C"    ,	   0x10701036b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP28_IP4_MIO_W1C"    ,	   0x10701038b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP29_IP4_MIO_W1C"    ,	   0x1070103ab3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP30_IP4_MIO_W1C"    ,	   0x1070103cb3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP31_IP4_MIO_W1C"    ,	   0x1070103eb3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP0_IP4_MIO_W1S"     ,	   0x10701000a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP1_IP4_MIO_W1S"     ,	   0x10701002a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP2_IP4_MIO_W1S"     ,	   0x10701004a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP3_IP4_MIO_W1S"     ,	   0x10701006a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP4_IP4_MIO_W1S"     ,	   0x10701008a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP5_IP4_MIO_W1S"     ,	   0x1070100aa3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP6_IP4_MIO_W1S"     ,	   0x1070100ca3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP7_IP4_MIO_W1S"     ,	   0x1070100ea3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP8_IP4_MIO_W1S"     ,	   0x10701010a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP9_IP4_MIO_W1S"     ,	   0x10701012a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP10_IP4_MIO_W1S"    ,	   0x10701014a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP11_IP4_MIO_W1S"    ,	   0x10701016a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP12_IP4_MIO_W1S"    ,	   0x10701018a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP13_IP4_MIO_W1S"    ,	   0x1070101aa3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP14_IP4_MIO_W1S"    ,	   0x1070101ca3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP15_IP4_MIO_W1S"    ,	   0x1070101ea3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP16_IP4_MIO_W1S"    ,	   0x10701020a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP17_IP4_MIO_W1S"    ,	   0x10701022a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP18_IP4_MIO_W1S"    ,	   0x10701024a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP19_IP4_MIO_W1S"    ,	   0x10701026a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP20_IP4_MIO_W1S"    ,	   0x10701028a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP21_IP4_MIO_W1S"    ,	   0x1070102aa3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP22_IP4_MIO_W1S"    ,	   0x1070102ca3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP23_IP4_MIO_W1S"    ,	   0x1070102ea3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP24_IP4_MIO_W1S"    ,	   0x10701030a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP25_IP4_MIO_W1S"    ,	   0x10701032a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP26_IP4_MIO_W1S"    ,	   0x10701034a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP27_IP4_MIO_W1S"    ,	   0x10701036a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP28_IP4_MIO_W1S"    ,	   0x10701038a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP29_IP4_MIO_W1S"    ,	   0x1070103aa3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP30_IP4_MIO_W1S"    ,	   0x1070103ca3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP31_IP4_MIO_W1S"    ,	   0x1070103ea3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP0_IP4_PKT"         ,	   0x1070100096400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP1_IP4_PKT"         ,	   0x1070100296400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP2_IP4_PKT"         ,	   0x1070100496400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP3_IP4_PKT"         ,	   0x1070100696400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP4_IP4_PKT"         ,	   0x1070100896400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP5_IP4_PKT"         ,	   0x1070100a96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP6_IP4_PKT"         ,	   0x1070100c96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP7_IP4_PKT"         ,	   0x1070100e96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP8_IP4_PKT"         ,	   0x1070101096400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP9_IP4_PKT"         ,	   0x1070101296400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP10_IP4_PKT"        ,	   0x1070101496400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP11_IP4_PKT"        ,	   0x1070101696400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP12_IP4_PKT"        ,	   0x1070101896400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP13_IP4_PKT"        ,	   0x1070101a96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP14_IP4_PKT"        ,	   0x1070101c96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP15_IP4_PKT"        ,	   0x1070101e96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP16_IP4_PKT"        ,	   0x1070102096400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP17_IP4_PKT"        ,	   0x1070102296400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP18_IP4_PKT"        ,	   0x1070102496400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP19_IP4_PKT"        ,	   0x1070102696400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP20_IP4_PKT"        ,	   0x1070102896400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP21_IP4_PKT"        ,	   0x1070102a96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP22_IP4_PKT"        ,	   0x1070102c96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP23_IP4_PKT"        ,	   0x1070102e96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP24_IP4_PKT"        ,	   0x1070103096400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP25_IP4_PKT"        ,	   0x1070103296400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP26_IP4_PKT"        ,	   0x1070103496400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP27_IP4_PKT"        ,	   0x1070103696400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP28_IP4_PKT"        ,	   0x1070103896400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP29_IP4_PKT"        ,	   0x1070103a96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP30_IP4_PKT"        ,	   0x1070103c96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP31_IP4_PKT"        ,	   0x1070103e96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP0_IP4_PKT_W1C"     ,	   0x10701000b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP1_IP4_PKT_W1C"     ,	   0x10701002b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP2_IP4_PKT_W1C"     ,	   0x10701004b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP3_IP4_PKT_W1C"     ,	   0x10701006b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP4_IP4_PKT_W1C"     ,	   0x10701008b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP5_IP4_PKT_W1C"     ,	   0x1070100ab6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP6_IP4_PKT_W1C"     ,	   0x1070100cb6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP7_IP4_PKT_W1C"     ,	   0x1070100eb6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP8_IP4_PKT_W1C"     ,	   0x10701010b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP9_IP4_PKT_W1C"     ,	   0x10701012b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP10_IP4_PKT_W1C"    ,	   0x10701014b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP11_IP4_PKT_W1C"    ,	   0x10701016b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP12_IP4_PKT_W1C"    ,	   0x10701018b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP13_IP4_PKT_W1C"    ,	   0x1070101ab6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP14_IP4_PKT_W1C"    ,	   0x1070101cb6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP15_IP4_PKT_W1C"    ,	   0x1070101eb6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP16_IP4_PKT_W1C"    ,	   0x10701020b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP17_IP4_PKT_W1C"    ,	   0x10701022b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP18_IP4_PKT_W1C"    ,	   0x10701024b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP19_IP4_PKT_W1C"    ,	   0x10701026b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP20_IP4_PKT_W1C"    ,	   0x10701028b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP21_IP4_PKT_W1C"    ,	   0x1070102ab6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP22_IP4_PKT_W1C"    ,	   0x1070102cb6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP23_IP4_PKT_W1C"    ,	   0x1070102eb6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP24_IP4_PKT_W1C"    ,	   0x10701030b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP25_IP4_PKT_W1C"    ,	   0x10701032b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP26_IP4_PKT_W1C"    ,	   0x10701034b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP27_IP4_PKT_W1C"    ,	   0x10701036b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP28_IP4_PKT_W1C"    ,	   0x10701038b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP29_IP4_PKT_W1C"    ,	   0x1070103ab6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP30_IP4_PKT_W1C"    ,	   0x1070103cb6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP31_IP4_PKT_W1C"    ,	   0x1070103eb6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP0_IP4_PKT_W1S"     ,	   0x10701000a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP1_IP4_PKT_W1S"     ,	   0x10701002a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP2_IP4_PKT_W1S"     ,	   0x10701004a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP3_IP4_PKT_W1S"     ,	   0x10701006a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP4_IP4_PKT_W1S"     ,	   0x10701008a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP5_IP4_PKT_W1S"     ,	   0x1070100aa6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP6_IP4_PKT_W1S"     ,	   0x1070100ca6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP7_IP4_PKT_W1S"     ,	   0x1070100ea6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP8_IP4_PKT_W1S"     ,	   0x10701010a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP9_IP4_PKT_W1S"     ,	   0x10701012a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP10_IP4_PKT_W1S"    ,	   0x10701014a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP11_IP4_PKT_W1S"    ,	   0x10701016a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP12_IP4_PKT_W1S"    ,	   0x10701018a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP13_IP4_PKT_W1S"    ,	   0x1070101aa6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP14_IP4_PKT_W1S"    ,	   0x1070101ca6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP15_IP4_PKT_W1S"    ,	   0x1070101ea6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP16_IP4_PKT_W1S"    ,	   0x10701020a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP17_IP4_PKT_W1S"    ,	   0x10701022a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP18_IP4_PKT_W1S"    ,	   0x10701024a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP19_IP4_PKT_W1S"    ,	   0x10701026a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP20_IP4_PKT_W1S"    ,	   0x10701028a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP21_IP4_PKT_W1S"    ,	   0x1070102aa6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP22_IP4_PKT_W1S"    ,	   0x1070102ca6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP23_IP4_PKT_W1S"    ,	   0x1070102ea6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP24_IP4_PKT_W1S"    ,	   0x10701030a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP25_IP4_PKT_W1S"    ,	   0x10701032a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP26_IP4_PKT_W1S"    ,	   0x10701034a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP27_IP4_PKT_W1S"    ,	   0x10701036a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP28_IP4_PKT_W1S"    ,	   0x10701038a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP29_IP4_PKT_W1S"    ,	   0x1070103aa6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP30_IP4_PKT_W1S"    ,	   0x1070103ca6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP31_IP4_PKT_W1S"    ,	   0x1070103ea6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP0_IP4_RML"         ,	   0x1070100092400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP1_IP4_RML"         ,	   0x1070100292400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP2_IP4_RML"         ,	   0x1070100492400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP3_IP4_RML"         ,	   0x1070100692400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP4_IP4_RML"         ,	   0x1070100892400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP5_IP4_RML"         ,	   0x1070100a92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP6_IP4_RML"         ,	   0x1070100c92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP7_IP4_RML"         ,	   0x1070100e92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP8_IP4_RML"         ,	   0x1070101092400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP9_IP4_RML"         ,	   0x1070101292400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP10_IP4_RML"        ,	   0x1070101492400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP11_IP4_RML"        ,	   0x1070101692400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP12_IP4_RML"        ,	   0x1070101892400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP13_IP4_RML"        ,	   0x1070101a92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP14_IP4_RML"        ,	   0x1070101c92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP15_IP4_RML"        ,	   0x1070101e92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP16_IP4_RML"        ,	   0x1070102092400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP17_IP4_RML"        ,	   0x1070102292400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP18_IP4_RML"        ,	   0x1070102492400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP19_IP4_RML"        ,	   0x1070102692400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP20_IP4_RML"        ,	   0x1070102892400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP21_IP4_RML"        ,	   0x1070102a92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP22_IP4_RML"        ,	   0x1070102c92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP23_IP4_RML"        ,	   0x1070102e92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP24_IP4_RML"        ,	   0x1070103092400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP25_IP4_RML"        ,	   0x1070103292400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP26_IP4_RML"        ,	   0x1070103492400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP27_IP4_RML"        ,	   0x1070103692400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP28_IP4_RML"        ,	   0x1070103892400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP29_IP4_RML"        ,	   0x1070103a92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP30_IP4_RML"        ,	   0x1070103c92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP31_IP4_RML"        ,	   0x1070103e92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP0_IP4_RML_W1C"     ,	   0x10701000b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP1_IP4_RML_W1C"     ,	   0x10701002b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP2_IP4_RML_W1C"     ,	   0x10701004b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP3_IP4_RML_W1C"     ,	   0x10701006b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP4_IP4_RML_W1C"     ,	   0x10701008b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP5_IP4_RML_W1C"     ,	   0x1070100ab2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP6_IP4_RML_W1C"     ,	   0x1070100cb2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP7_IP4_RML_W1C"     ,	   0x1070100eb2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP8_IP4_RML_W1C"     ,	   0x10701010b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP9_IP4_RML_W1C"     ,	   0x10701012b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP10_IP4_RML_W1C"    ,	   0x10701014b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP11_IP4_RML_W1C"    ,	   0x10701016b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP12_IP4_RML_W1C"    ,	   0x10701018b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP13_IP4_RML_W1C"    ,	   0x1070101ab2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP14_IP4_RML_W1C"    ,	   0x1070101cb2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP15_IP4_RML_W1C"    ,	   0x1070101eb2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP16_IP4_RML_W1C"    ,	   0x10701020b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP17_IP4_RML_W1C"    ,	   0x10701022b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP18_IP4_RML_W1C"    ,	   0x10701024b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP19_IP4_RML_W1C"    ,	   0x10701026b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP20_IP4_RML_W1C"    ,	   0x10701028b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP21_IP4_RML_W1C"    ,	   0x1070102ab2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP22_IP4_RML_W1C"    ,	   0x1070102cb2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP23_IP4_RML_W1C"    ,	   0x1070102eb2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP24_IP4_RML_W1C"    ,	   0x10701030b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP25_IP4_RML_W1C"    ,	   0x10701032b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP26_IP4_RML_W1C"    ,	   0x10701034b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP27_IP4_RML_W1C"    ,	   0x10701036b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP28_IP4_RML_W1C"    ,	   0x10701038b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP29_IP4_RML_W1C"    ,	   0x1070103ab2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP30_IP4_RML_W1C"    ,	   0x1070103cb2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP31_IP4_RML_W1C"    ,	   0x1070103eb2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP0_IP4_RML_W1S"     ,	   0x10701000a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP1_IP4_RML_W1S"     ,	   0x10701002a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP2_IP4_RML_W1S"     ,	   0x10701004a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP3_IP4_RML_W1S"     ,	   0x10701006a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP4_IP4_RML_W1S"     ,	   0x10701008a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP5_IP4_RML_W1S"     ,	   0x1070100aa2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP6_IP4_RML_W1S"     ,	   0x1070100ca2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP7_IP4_RML_W1S"     ,	   0x1070100ea2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP8_IP4_RML_W1S"     ,	   0x10701010a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP9_IP4_RML_W1S"     ,	   0x10701012a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP10_IP4_RML_W1S"    ,	   0x10701014a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP11_IP4_RML_W1S"    ,	   0x10701016a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP12_IP4_RML_W1S"    ,	   0x10701018a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP13_IP4_RML_W1S"    ,	   0x1070101aa2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP14_IP4_RML_W1S"    ,	   0x1070101ca2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP15_IP4_RML_W1S"    ,	   0x1070101ea2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP16_IP4_RML_W1S"    ,	   0x10701020a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP17_IP4_RML_W1S"    ,	   0x10701022a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP18_IP4_RML_W1S"    ,	   0x10701024a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP19_IP4_RML_W1S"    ,	   0x10701026a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP20_IP4_RML_W1S"    ,	   0x10701028a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP21_IP4_RML_W1S"    ,	   0x1070102aa2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP22_IP4_RML_W1S"    ,	   0x1070102ca2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP23_IP4_RML_W1S"    ,	   0x1070102ea2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP24_IP4_RML_W1S"    ,	   0x10701030a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP25_IP4_RML_W1S"    ,	   0x10701032a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP26_IP4_RML_W1S"    ,	   0x10701034a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP27_IP4_RML_W1S"    ,	   0x10701036a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP28_IP4_RML_W1S"    ,	   0x10701038a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP29_IP4_RML_W1S"    ,	   0x1070103aa2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP30_IP4_RML_W1S"    ,	   0x1070103ca2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP31_IP4_RML_W1S"    ,	   0x1070103ea2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP0_IP4_WDOG"        ,	   0x1070100091400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP1_IP4_WDOG"        ,	   0x1070100291400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP2_IP4_WDOG"        ,	   0x1070100491400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP3_IP4_WDOG"        ,	   0x1070100691400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP4_IP4_WDOG"        ,	   0x1070100891400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP5_IP4_WDOG"        ,	   0x1070100a91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP6_IP4_WDOG"        ,	   0x1070100c91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP7_IP4_WDOG"        ,	   0x1070100e91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP8_IP4_WDOG"        ,	   0x1070101091400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP9_IP4_WDOG"        ,	   0x1070101291400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP10_IP4_WDOG"       ,	   0x1070101491400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP11_IP4_WDOG"       ,	   0x1070101691400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP12_IP4_WDOG"       ,	   0x1070101891400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP13_IP4_WDOG"       ,	   0x1070101a91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP14_IP4_WDOG"       ,	   0x1070101c91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP15_IP4_WDOG"       ,	   0x1070101e91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP16_IP4_WDOG"       ,	   0x1070102091400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP17_IP4_WDOG"       ,	   0x1070102291400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP18_IP4_WDOG"       ,	   0x1070102491400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP19_IP4_WDOG"       ,	   0x1070102691400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP20_IP4_WDOG"       ,	   0x1070102891400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP21_IP4_WDOG"       ,	   0x1070102a91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP22_IP4_WDOG"       ,	   0x1070102c91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP23_IP4_WDOG"       ,	   0x1070102e91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP24_IP4_WDOG"       ,	   0x1070103091400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP25_IP4_WDOG"       ,	   0x1070103291400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP26_IP4_WDOG"       ,	   0x1070103491400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP27_IP4_WDOG"       ,	   0x1070103691400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP28_IP4_WDOG"       ,	   0x1070103891400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP29_IP4_WDOG"       ,	   0x1070103a91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP30_IP4_WDOG"       ,	   0x1070103c91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP31_IP4_WDOG"       ,	   0x1070103e91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP0_IP4_WDOG_W1C"    ,	   0x10701000b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP1_IP4_WDOG_W1C"    ,	   0x10701002b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP2_IP4_WDOG_W1C"    ,	   0x10701004b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP3_IP4_WDOG_W1C"    ,	   0x10701006b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP4_IP4_WDOG_W1C"    ,	   0x10701008b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP5_IP4_WDOG_W1C"    ,	   0x1070100ab1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP6_IP4_WDOG_W1C"    ,	   0x1070100cb1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP7_IP4_WDOG_W1C"    ,	   0x1070100eb1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP8_IP4_WDOG_W1C"    ,	   0x10701010b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP9_IP4_WDOG_W1C"    ,	   0x10701012b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP10_IP4_WDOG_W1C"   ,	   0x10701014b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP11_IP4_WDOG_W1C"   ,	   0x10701016b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP12_IP4_WDOG_W1C"   ,	   0x10701018b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP13_IP4_WDOG_W1C"   ,	   0x1070101ab1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP14_IP4_WDOG_W1C"   ,	   0x1070101cb1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP15_IP4_WDOG_W1C"   ,	   0x1070101eb1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP16_IP4_WDOG_W1C"   ,	   0x10701020b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP17_IP4_WDOG_W1C"   ,	   0x10701022b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP18_IP4_WDOG_W1C"   ,	   0x10701024b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP19_IP4_WDOG_W1C"   ,	   0x10701026b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP20_IP4_WDOG_W1C"   ,	   0x10701028b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP21_IP4_WDOG_W1C"   ,	   0x1070102ab1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP22_IP4_WDOG_W1C"   ,	   0x1070102cb1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP23_IP4_WDOG_W1C"   ,	   0x1070102eb1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP24_IP4_WDOG_W1C"   ,	   0x10701030b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP25_IP4_WDOG_W1C"   ,	   0x10701032b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP26_IP4_WDOG_W1C"   ,	   0x10701034b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP27_IP4_WDOG_W1C"   ,	   0x10701036b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP28_IP4_WDOG_W1C"   ,	   0x10701038b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP29_IP4_WDOG_W1C"   ,	   0x1070103ab1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP30_IP4_WDOG_W1C"   ,	   0x1070103cb1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP31_IP4_WDOG_W1C"   ,	   0x1070103eb1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP0_IP4_WDOG_W1S"    ,	   0x10701000a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP1_IP4_WDOG_W1S"    ,	   0x10701002a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP2_IP4_WDOG_W1S"    ,	   0x10701004a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP3_IP4_WDOG_W1S"    ,	   0x10701006a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP4_IP4_WDOG_W1S"    ,	   0x10701008a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP5_IP4_WDOG_W1S"    ,	   0x1070100aa1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP6_IP4_WDOG_W1S"    ,	   0x1070100ca1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP7_IP4_WDOG_W1S"    ,	   0x1070100ea1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP8_IP4_WDOG_W1S"    ,	   0x10701010a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP9_IP4_WDOG_W1S"    ,	   0x10701012a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP10_IP4_WDOG_W1S"   ,	   0x10701014a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP11_IP4_WDOG_W1S"   ,	   0x10701016a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP12_IP4_WDOG_W1S"   ,	   0x10701018a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP13_IP4_WDOG_W1S"   ,	   0x1070101aa1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP14_IP4_WDOG_W1S"   ,	   0x1070101ca1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP15_IP4_WDOG_W1S"   ,	   0x1070101ea1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP16_IP4_WDOG_W1S"   ,	   0x10701020a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP17_IP4_WDOG_W1S"   ,	   0x10701022a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP18_IP4_WDOG_W1S"   ,	   0x10701024a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP19_IP4_WDOG_W1S"   ,	   0x10701026a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP20_IP4_WDOG_W1S"   ,	   0x10701028a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP21_IP4_WDOG_W1S"   ,	   0x1070102aa1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP22_IP4_WDOG_W1S"   ,	   0x1070102ca1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP23_IP4_WDOG_W1S"   ,	   0x1070102ea1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP24_IP4_WDOG_W1S"   ,	   0x10701030a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP25_IP4_WDOG_W1S"   ,	   0x10701032a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP26_IP4_WDOG_W1S"   ,	   0x10701034a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP27_IP4_WDOG_W1S"   ,	   0x10701036a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP28_IP4_WDOG_W1S"   ,	   0x10701038a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP29_IP4_WDOG_W1S"   ,	   0x1070103aa1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP30_IP4_WDOG_W1S"   ,	   0x1070103ca1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP31_IP4_WDOG_W1S"   ,	   0x1070103ea1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP0_IP4_WRKQ"        ,	   0x1070100090400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP1_IP4_WRKQ"        ,	   0x1070100290400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP2_IP4_WRKQ"        ,	   0x1070100490400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP3_IP4_WRKQ"        ,	   0x1070100690400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP4_IP4_WRKQ"        ,	   0x1070100890400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP5_IP4_WRKQ"        ,	   0x1070100a90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP6_IP4_WRKQ"        ,	   0x1070100c90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP7_IP4_WRKQ"        ,	   0x1070100e90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP8_IP4_WRKQ"        ,	   0x1070101090400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP9_IP4_WRKQ"        ,	   0x1070101290400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP10_IP4_WRKQ"       ,	   0x1070101490400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP11_IP4_WRKQ"       ,	   0x1070101690400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP12_IP4_WRKQ"       ,	   0x1070101890400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP13_IP4_WRKQ"       ,	   0x1070101a90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP14_IP4_WRKQ"       ,	   0x1070101c90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP15_IP4_WRKQ"       ,	   0x1070101e90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP16_IP4_WRKQ"       ,	   0x1070102090400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP17_IP4_WRKQ"       ,	   0x1070102290400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP18_IP4_WRKQ"       ,	   0x1070102490400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP19_IP4_WRKQ"       ,	   0x1070102690400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP20_IP4_WRKQ"       ,	   0x1070102890400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP21_IP4_WRKQ"       ,	   0x1070102a90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP22_IP4_WRKQ"       ,	   0x1070102c90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP23_IP4_WRKQ"       ,	   0x1070102e90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP24_IP4_WRKQ"       ,	   0x1070103090400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP25_IP4_WRKQ"       ,	   0x1070103290400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP26_IP4_WRKQ"       ,	   0x1070103490400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP27_IP4_WRKQ"       ,	   0x1070103690400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP28_IP4_WRKQ"       ,	   0x1070103890400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP29_IP4_WRKQ"       ,	   0x1070103a90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP30_IP4_WRKQ"       ,	   0x1070103c90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP31_IP4_WRKQ"       ,	   0x1070103e90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP0_IP4_WRKQ_W1C"    ,	   0x10701000b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP1_IP4_WRKQ_W1C"    ,	   0x10701002b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP2_IP4_WRKQ_W1C"    ,	   0x10701004b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP3_IP4_WRKQ_W1C"    ,	   0x10701006b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP4_IP4_WRKQ_W1C"    ,	   0x10701008b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP5_IP4_WRKQ_W1C"    ,	   0x1070100ab0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP6_IP4_WRKQ_W1C"    ,	   0x1070100cb0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP7_IP4_WRKQ_W1C"    ,	   0x1070100eb0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP8_IP4_WRKQ_W1C"    ,	   0x10701010b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP9_IP4_WRKQ_W1C"    ,	   0x10701012b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP10_IP4_WRKQ_W1C"   ,	   0x10701014b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP11_IP4_WRKQ_W1C"   ,	   0x10701016b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP12_IP4_WRKQ_W1C"   ,	   0x10701018b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP13_IP4_WRKQ_W1C"   ,	   0x1070101ab0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP14_IP4_WRKQ_W1C"   ,	   0x1070101cb0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP15_IP4_WRKQ_W1C"   ,	   0x1070101eb0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP16_IP4_WRKQ_W1C"   ,	   0x10701020b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP17_IP4_WRKQ_W1C"   ,	   0x10701022b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP18_IP4_WRKQ_W1C"   ,	   0x10701024b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP19_IP4_WRKQ_W1C"   ,	   0x10701026b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP20_IP4_WRKQ_W1C"   ,	   0x10701028b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP21_IP4_WRKQ_W1C"   ,	   0x1070102ab0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP22_IP4_WRKQ_W1C"   ,	   0x1070102cb0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP23_IP4_WRKQ_W1C"   ,	   0x1070102eb0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP24_IP4_WRKQ_W1C"   ,	   0x10701030b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP25_IP4_WRKQ_W1C"   ,	   0x10701032b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP26_IP4_WRKQ_W1C"   ,	   0x10701034b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP27_IP4_WRKQ_W1C"   ,	   0x10701036b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP28_IP4_WRKQ_W1C"   ,	   0x10701038b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP29_IP4_WRKQ_W1C"   ,	   0x1070103ab0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP30_IP4_WRKQ_W1C"   ,	   0x1070103cb0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP31_IP4_WRKQ_W1C"   ,	   0x1070103eb0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP0_IP4_WRKQ_W1S"    ,	   0x10701000a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP1_IP4_WRKQ_W1S"    ,	   0x10701002a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP2_IP4_WRKQ_W1S"    ,	   0x10701004a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP3_IP4_WRKQ_W1S"    ,	   0x10701006a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP4_IP4_WRKQ_W1S"    ,	   0x10701008a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP5_IP4_WRKQ_W1S"    ,	   0x1070100aa0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP6_IP4_WRKQ_W1S"    ,	   0x1070100ca0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP7_IP4_WRKQ_W1S"    ,	   0x1070100ea0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP8_IP4_WRKQ_W1S"    ,	   0x10701010a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP9_IP4_WRKQ_W1S"    ,	   0x10701012a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP10_IP4_WRKQ_W1S"   ,	   0x10701014a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP11_IP4_WRKQ_W1S"   ,	   0x10701016a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP12_IP4_WRKQ_W1S"   ,	   0x10701018a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP13_IP4_WRKQ_W1S"   ,	   0x1070101aa0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP14_IP4_WRKQ_W1S"   ,	   0x1070101ca0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP15_IP4_WRKQ_W1S"   ,	   0x1070101ea0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP16_IP4_WRKQ_W1S"   ,	   0x10701020a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP17_IP4_WRKQ_W1S"   ,	   0x10701022a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP18_IP4_WRKQ_W1S"   ,	   0x10701024a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP19_IP4_WRKQ_W1S"   ,	   0x10701026a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP20_IP4_WRKQ_W1S"   ,	   0x10701028a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP21_IP4_WRKQ_W1S"   ,	   0x1070102aa0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP22_IP4_WRKQ_W1S"   ,	   0x1070102ca0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP23_IP4_WRKQ_W1S"   ,	   0x1070102ea0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP24_IP4_WRKQ_W1S"   ,	   0x10701030a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP25_IP4_WRKQ_W1S"   ,	   0x10701032a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP26_IP4_WRKQ_W1S"   ,	   0x10701034a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP27_IP4_WRKQ_W1S"   ,	   0x10701036a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP28_IP4_WRKQ_W1S"   ,	   0x10701038a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP29_IP4_WRKQ_W1S"   ,	   0x1070103aa0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP30_IP4_WRKQ_W1S"   ,	   0x1070103ca0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP31_IP4_WRKQ_W1S"   ,	   0x1070103ea0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_INTR_CIU_READY"         ,	   0x1070100102008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"CIU2_INTR_RAM_ECC_CTL"       ,	   0x1070100102010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	185},
+	{"CIU2_INTR_RAM_ECC_ST"        ,	   0x1070100102018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	186},
+	{"CIU2_INTR_SLOWDOWN"          ,	   0x1070100102000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	187},
+	{"CIU2_MSI_RCV0"               ,	   0x10701000c2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV1"               ,	   0x10701000c2008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV2"               ,	   0x10701000c2010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV3"               ,	   0x10701000c2018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV4"               ,	   0x10701000c2020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV5"               ,	   0x10701000c2028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV6"               ,	   0x10701000c2030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV7"               ,	   0x10701000c2038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV8"               ,	   0x10701000c2040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV9"               ,	   0x10701000c2048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV10"              ,	   0x10701000c2050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV11"              ,	   0x10701000c2058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV12"              ,	   0x10701000c2060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV13"              ,	   0x10701000c2068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV14"              ,	   0x10701000c2070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV15"              ,	   0x10701000c2078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV16"              ,	   0x10701000c2080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV17"              ,	   0x10701000c2088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV18"              ,	   0x10701000c2090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV19"              ,	   0x10701000c2098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV20"              ,	   0x10701000c20a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV21"              ,	   0x10701000c20a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV22"              ,	   0x10701000c20b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV23"              ,	   0x10701000c20b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV24"              ,	   0x10701000c20c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV25"              ,	   0x10701000c20c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV26"              ,	   0x10701000c20d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV27"              ,	   0x10701000c20d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV28"              ,	   0x10701000c20e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV29"              ,	   0x10701000c20e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV30"              ,	   0x10701000c20f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV31"              ,	   0x10701000c20f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV32"              ,	   0x10701000c2100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV33"              ,	   0x10701000c2108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV34"              ,	   0x10701000c2110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV35"              ,	   0x10701000c2118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV36"              ,	   0x10701000c2120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV37"              ,	   0x10701000c2128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV38"              ,	   0x10701000c2130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV39"              ,	   0x10701000c2138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV40"              ,	   0x10701000c2140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV41"              ,	   0x10701000c2148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV42"              ,	   0x10701000c2150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV43"              ,	   0x10701000c2158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV44"              ,	   0x10701000c2160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV45"              ,	   0x10701000c2168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV46"              ,	   0x10701000c2170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV47"              ,	   0x10701000c2178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV48"              ,	   0x10701000c2180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV49"              ,	   0x10701000c2188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV50"              ,	   0x10701000c2190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV51"              ,	   0x10701000c2198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV52"              ,	   0x10701000c21a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV53"              ,	   0x10701000c21a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV54"              ,	   0x10701000c21b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV55"              ,	   0x10701000c21b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV56"              ,	   0x10701000c21c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV57"              ,	   0x10701000c21c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV58"              ,	   0x10701000c21d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV59"              ,	   0x10701000c21d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV60"              ,	   0x10701000c21e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV61"              ,	   0x10701000c21e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV62"              ,	   0x10701000c21f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV63"              ,	   0x10701000c21f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV64"              ,	   0x10701000c2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV65"              ,	   0x10701000c2208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV66"              ,	   0x10701000c2210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV67"              ,	   0x10701000c2218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV68"              ,	   0x10701000c2220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV69"              ,	   0x10701000c2228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV70"              ,	   0x10701000c2230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV71"              ,	   0x10701000c2238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV72"              ,	   0x10701000c2240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV73"              ,	   0x10701000c2248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV74"              ,	   0x10701000c2250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV75"              ,	   0x10701000c2258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV76"              ,	   0x10701000c2260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV77"              ,	   0x10701000c2268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV78"              ,	   0x10701000c2270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV79"              ,	   0x10701000c2278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV80"              ,	   0x10701000c2280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV81"              ,	   0x10701000c2288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV82"              ,	   0x10701000c2290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV83"              ,	   0x10701000c2298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV84"              ,	   0x10701000c22a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV85"              ,	   0x10701000c22a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV86"              ,	   0x10701000c22b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV87"              ,	   0x10701000c22b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV88"              ,	   0x10701000c22c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV89"              ,	   0x10701000c22c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV90"              ,	   0x10701000c22d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV91"              ,	   0x10701000c22d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV92"              ,	   0x10701000c22e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV93"              ,	   0x10701000c22e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV94"              ,	   0x10701000c22f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV95"              ,	   0x10701000c22f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV96"              ,	   0x10701000c2300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV97"              ,	   0x10701000c2308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV98"              ,	   0x10701000c2310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV99"              ,	   0x10701000c2318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV100"             ,	   0x10701000c2320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV101"             ,	   0x10701000c2328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV102"             ,	   0x10701000c2330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV103"             ,	   0x10701000c2338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV104"             ,	   0x10701000c2340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV105"             ,	   0x10701000c2348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV106"             ,	   0x10701000c2350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV107"             ,	   0x10701000c2358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV108"             ,	   0x10701000c2360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV109"             ,	   0x10701000c2368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV110"             ,	   0x10701000c2370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV111"             ,	   0x10701000c2378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV112"             ,	   0x10701000c2380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV113"             ,	   0x10701000c2388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV114"             ,	   0x10701000c2390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV115"             ,	   0x10701000c2398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV116"             ,	   0x10701000c23a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV117"             ,	   0x10701000c23a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV118"             ,	   0x10701000c23b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV119"             ,	   0x10701000c23b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV120"             ,	   0x10701000c23c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV121"             ,	   0x10701000c23c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV122"             ,	   0x10701000c23d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV123"             ,	   0x10701000c23d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV124"             ,	   0x10701000c23e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV125"             ,	   0x10701000c23e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV126"             ,	   0x10701000c23f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV127"             ,	   0x10701000c23f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV128"             ,	   0x10701000c2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV129"             ,	   0x10701000c2408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV130"             ,	   0x10701000c2410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV131"             ,	   0x10701000c2418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV132"             ,	   0x10701000c2420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV133"             ,	   0x10701000c2428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV134"             ,	   0x10701000c2430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV135"             ,	   0x10701000c2438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV136"             ,	   0x10701000c2440ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV137"             ,	   0x10701000c2448ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV138"             ,	   0x10701000c2450ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV139"             ,	   0x10701000c2458ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV140"             ,	   0x10701000c2460ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV141"             ,	   0x10701000c2468ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV142"             ,	   0x10701000c2470ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV143"             ,	   0x10701000c2478ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV144"             ,	   0x10701000c2480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV145"             ,	   0x10701000c2488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV146"             ,	   0x10701000c2490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV147"             ,	   0x10701000c2498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV148"             ,	   0x10701000c24a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV149"             ,	   0x10701000c24a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV150"             ,	   0x10701000c24b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV151"             ,	   0x10701000c24b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV152"             ,	   0x10701000c24c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV153"             ,	   0x10701000c24c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV154"             ,	   0x10701000c24d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV155"             ,	   0x10701000c24d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV156"             ,	   0x10701000c24e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV157"             ,	   0x10701000c24e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV158"             ,	   0x10701000c24f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV159"             ,	   0x10701000c24f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV160"             ,	   0x10701000c2500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV161"             ,	   0x10701000c2508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV162"             ,	   0x10701000c2510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV163"             ,	   0x10701000c2518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV164"             ,	   0x10701000c2520ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV165"             ,	   0x10701000c2528ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV166"             ,	   0x10701000c2530ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV167"             ,	   0x10701000c2538ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV168"             ,	   0x10701000c2540ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV169"             ,	   0x10701000c2548ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV170"             ,	   0x10701000c2550ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV171"             ,	   0x10701000c2558ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV172"             ,	   0x10701000c2560ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV173"             ,	   0x10701000c2568ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV174"             ,	   0x10701000c2570ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV175"             ,	   0x10701000c2578ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV176"             ,	   0x10701000c2580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV177"             ,	   0x10701000c2588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV178"             ,	   0x10701000c2590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV179"             ,	   0x10701000c2598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV180"             ,	   0x10701000c25a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV181"             ,	   0x10701000c25a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV182"             ,	   0x10701000c25b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV183"             ,	   0x10701000c25b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV184"             ,	   0x10701000c25c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV185"             ,	   0x10701000c25c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV186"             ,	   0x10701000c25d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV187"             ,	   0x10701000c25d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV188"             ,	   0x10701000c25e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV189"             ,	   0x10701000c25e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV190"             ,	   0x10701000c25f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV191"             ,	   0x10701000c25f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV192"             ,	   0x10701000c2600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV193"             ,	   0x10701000c2608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV194"             ,	   0x10701000c2610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV195"             ,	   0x10701000c2618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV196"             ,	   0x10701000c2620ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV197"             ,	   0x10701000c2628ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV198"             ,	   0x10701000c2630ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV199"             ,	   0x10701000c2638ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV200"             ,	   0x10701000c2640ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV201"             ,	   0x10701000c2648ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV202"             ,	   0x10701000c2650ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV203"             ,	   0x10701000c2658ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV204"             ,	   0x10701000c2660ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV205"             ,	   0x10701000c2668ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV206"             ,	   0x10701000c2670ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV207"             ,	   0x10701000c2678ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV208"             ,	   0x10701000c2680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV209"             ,	   0x10701000c2688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV210"             ,	   0x10701000c2690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV211"             ,	   0x10701000c2698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV212"             ,	   0x10701000c26a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV213"             ,	   0x10701000c26a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV214"             ,	   0x10701000c26b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV215"             ,	   0x10701000c26b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV216"             ,	   0x10701000c26c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV217"             ,	   0x10701000c26c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV218"             ,	   0x10701000c26d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV219"             ,	   0x10701000c26d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV220"             ,	   0x10701000c26e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV221"             ,	   0x10701000c26e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV222"             ,	   0x10701000c26f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV223"             ,	   0x10701000c26f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV224"             ,	   0x10701000c2700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV225"             ,	   0x10701000c2708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV226"             ,	   0x10701000c2710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV227"             ,	   0x10701000c2718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV228"             ,	   0x10701000c2720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV229"             ,	   0x10701000c2728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV230"             ,	   0x10701000c2730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV231"             ,	   0x10701000c2738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV232"             ,	   0x10701000c2740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV233"             ,	   0x10701000c2748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV234"             ,	   0x10701000c2750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV235"             ,	   0x10701000c2758ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV236"             ,	   0x10701000c2760ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV237"             ,	   0x10701000c2768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV238"             ,	   0x10701000c2770ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV239"             ,	   0x10701000c2778ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV240"             ,	   0x10701000c2780ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV241"             ,	   0x10701000c2788ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV242"             ,	   0x10701000c2790ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV243"             ,	   0x10701000c2798ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV244"             ,	   0x10701000c27a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV245"             ,	   0x10701000c27a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV246"             ,	   0x10701000c27b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV247"             ,	   0x10701000c27b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV248"             ,	   0x10701000c27c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV249"             ,	   0x10701000c27c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV250"             ,	   0x10701000c27d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV251"             ,	   0x10701000c27d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV252"             ,	   0x10701000c27e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV253"             ,	   0x10701000c27e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV254"             ,	   0x10701000c27f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV255"             ,	   0x10701000c27f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_SEL0"               ,	   0x10701000c3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL1"               ,	   0x10701000c3008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL2"               ,	   0x10701000c3010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL3"               ,	   0x10701000c3018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL4"               ,	   0x10701000c3020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL5"               ,	   0x10701000c3028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL6"               ,	   0x10701000c3030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL7"               ,	   0x10701000c3038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL8"               ,	   0x10701000c3040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL9"               ,	   0x10701000c3048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL10"              ,	   0x10701000c3050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL11"              ,	   0x10701000c3058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL12"              ,	   0x10701000c3060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL13"              ,	   0x10701000c3068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL14"              ,	   0x10701000c3070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL15"              ,	   0x10701000c3078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL16"              ,	   0x10701000c3080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL17"              ,	   0x10701000c3088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL18"              ,	   0x10701000c3090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL19"              ,	   0x10701000c3098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL20"              ,	   0x10701000c30a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL21"              ,	   0x10701000c30a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL22"              ,	   0x10701000c30b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL23"              ,	   0x10701000c30b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL24"              ,	   0x10701000c30c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL25"              ,	   0x10701000c30c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL26"              ,	   0x10701000c30d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL27"              ,	   0x10701000c30d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL28"              ,	   0x10701000c30e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL29"              ,	   0x10701000c30e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL30"              ,	   0x10701000c30f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL31"              ,	   0x10701000c30f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL32"              ,	   0x10701000c3100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL33"              ,	   0x10701000c3108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL34"              ,	   0x10701000c3110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL35"              ,	   0x10701000c3118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL36"              ,	   0x10701000c3120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL37"              ,	   0x10701000c3128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL38"              ,	   0x10701000c3130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL39"              ,	   0x10701000c3138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL40"              ,	   0x10701000c3140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL41"              ,	   0x10701000c3148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL42"              ,	   0x10701000c3150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL43"              ,	   0x10701000c3158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL44"              ,	   0x10701000c3160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL45"              ,	   0x10701000c3168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL46"              ,	   0x10701000c3170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL47"              ,	   0x10701000c3178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL48"              ,	   0x10701000c3180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL49"              ,	   0x10701000c3188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL50"              ,	   0x10701000c3190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL51"              ,	   0x10701000c3198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL52"              ,	   0x10701000c31a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL53"              ,	   0x10701000c31a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL54"              ,	   0x10701000c31b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL55"              ,	   0x10701000c31b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL56"              ,	   0x10701000c31c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL57"              ,	   0x10701000c31c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL58"              ,	   0x10701000c31d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL59"              ,	   0x10701000c31d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL60"              ,	   0x10701000c31e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL61"              ,	   0x10701000c31e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL62"              ,	   0x10701000c31f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL63"              ,	   0x10701000c31f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL64"              ,	   0x10701000c3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL65"              ,	   0x10701000c3208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL66"              ,	   0x10701000c3210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL67"              ,	   0x10701000c3218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL68"              ,	   0x10701000c3220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL69"              ,	   0x10701000c3228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL70"              ,	   0x10701000c3230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL71"              ,	   0x10701000c3238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL72"              ,	   0x10701000c3240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL73"              ,	   0x10701000c3248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL74"              ,	   0x10701000c3250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL75"              ,	   0x10701000c3258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL76"              ,	   0x10701000c3260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL77"              ,	   0x10701000c3268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL78"              ,	   0x10701000c3270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL79"              ,	   0x10701000c3278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL80"              ,	   0x10701000c3280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL81"              ,	   0x10701000c3288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL82"              ,	   0x10701000c3290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL83"              ,	   0x10701000c3298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL84"              ,	   0x10701000c32a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL85"              ,	   0x10701000c32a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL86"              ,	   0x10701000c32b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL87"              ,	   0x10701000c32b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL88"              ,	   0x10701000c32c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL89"              ,	   0x10701000c32c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL90"              ,	   0x10701000c32d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL91"              ,	   0x10701000c32d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL92"              ,	   0x10701000c32e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL93"              ,	   0x10701000c32e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL94"              ,	   0x10701000c32f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL95"              ,	   0x10701000c32f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL96"              ,	   0x10701000c3300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL97"              ,	   0x10701000c3308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL98"              ,	   0x10701000c3310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL99"              ,	   0x10701000c3318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL100"             ,	   0x10701000c3320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL101"             ,	   0x10701000c3328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL102"             ,	   0x10701000c3330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL103"             ,	   0x10701000c3338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL104"             ,	   0x10701000c3340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL105"             ,	   0x10701000c3348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL106"             ,	   0x10701000c3350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL107"             ,	   0x10701000c3358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL108"             ,	   0x10701000c3360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL109"             ,	   0x10701000c3368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL110"             ,	   0x10701000c3370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL111"             ,	   0x10701000c3378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL112"             ,	   0x10701000c3380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL113"             ,	   0x10701000c3388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL114"             ,	   0x10701000c3390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL115"             ,	   0x10701000c3398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL116"             ,	   0x10701000c33a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL117"             ,	   0x10701000c33a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL118"             ,	   0x10701000c33b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL119"             ,	   0x10701000c33b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL120"             ,	   0x10701000c33c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL121"             ,	   0x10701000c33c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL122"             ,	   0x10701000c33d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL123"             ,	   0x10701000c33d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL124"             ,	   0x10701000c33e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL125"             ,	   0x10701000c33e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL126"             ,	   0x10701000c33f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL127"             ,	   0x10701000c33f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL128"             ,	   0x10701000c3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL129"             ,	   0x10701000c3408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL130"             ,	   0x10701000c3410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL131"             ,	   0x10701000c3418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL132"             ,	   0x10701000c3420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL133"             ,	   0x10701000c3428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL134"             ,	   0x10701000c3430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL135"             ,	   0x10701000c3438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL136"             ,	   0x10701000c3440ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL137"             ,	   0x10701000c3448ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL138"             ,	   0x10701000c3450ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL139"             ,	   0x10701000c3458ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL140"             ,	   0x10701000c3460ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL141"             ,	   0x10701000c3468ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL142"             ,	   0x10701000c3470ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL143"             ,	   0x10701000c3478ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL144"             ,	   0x10701000c3480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL145"             ,	   0x10701000c3488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL146"             ,	   0x10701000c3490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL147"             ,	   0x10701000c3498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL148"             ,	   0x10701000c34a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL149"             ,	   0x10701000c34a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL150"             ,	   0x10701000c34b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL151"             ,	   0x10701000c34b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL152"             ,	   0x10701000c34c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL153"             ,	   0x10701000c34c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL154"             ,	   0x10701000c34d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL155"             ,	   0x10701000c34d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL156"             ,	   0x10701000c34e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL157"             ,	   0x10701000c34e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL158"             ,	   0x10701000c34f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL159"             ,	   0x10701000c34f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL160"             ,	   0x10701000c3500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL161"             ,	   0x10701000c3508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL162"             ,	   0x10701000c3510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL163"             ,	   0x10701000c3518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL164"             ,	   0x10701000c3520ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL165"             ,	   0x10701000c3528ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL166"             ,	   0x10701000c3530ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL167"             ,	   0x10701000c3538ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL168"             ,	   0x10701000c3540ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL169"             ,	   0x10701000c3548ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL170"             ,	   0x10701000c3550ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL171"             ,	   0x10701000c3558ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL172"             ,	   0x10701000c3560ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL173"             ,	   0x10701000c3568ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL174"             ,	   0x10701000c3570ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL175"             ,	   0x10701000c3578ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL176"             ,	   0x10701000c3580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL177"             ,	   0x10701000c3588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL178"             ,	   0x10701000c3590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL179"             ,	   0x10701000c3598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL180"             ,	   0x10701000c35a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL181"             ,	   0x10701000c35a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL182"             ,	   0x10701000c35b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL183"             ,	   0x10701000c35b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL184"             ,	   0x10701000c35c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL185"             ,	   0x10701000c35c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL186"             ,	   0x10701000c35d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL187"             ,	   0x10701000c35d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL188"             ,	   0x10701000c35e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL189"             ,	   0x10701000c35e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL190"             ,	   0x10701000c35f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL191"             ,	   0x10701000c35f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL192"             ,	   0x10701000c3600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL193"             ,	   0x10701000c3608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL194"             ,	   0x10701000c3610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL195"             ,	   0x10701000c3618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL196"             ,	   0x10701000c3620ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL197"             ,	   0x10701000c3628ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL198"             ,	   0x10701000c3630ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL199"             ,	   0x10701000c3638ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL200"             ,	   0x10701000c3640ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL201"             ,	   0x10701000c3648ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL202"             ,	   0x10701000c3650ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL203"             ,	   0x10701000c3658ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL204"             ,	   0x10701000c3660ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL205"             ,	   0x10701000c3668ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL206"             ,	   0x10701000c3670ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL207"             ,	   0x10701000c3678ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL208"             ,	   0x10701000c3680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL209"             ,	   0x10701000c3688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL210"             ,	   0x10701000c3690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL211"             ,	   0x10701000c3698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL212"             ,	   0x10701000c36a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL213"             ,	   0x10701000c36a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL214"             ,	   0x10701000c36b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL215"             ,	   0x10701000c36b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL216"             ,	   0x10701000c36c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL217"             ,	   0x10701000c36c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL218"             ,	   0x10701000c36d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL219"             ,	   0x10701000c36d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL220"             ,	   0x10701000c36e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL221"             ,	   0x10701000c36e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL222"             ,	   0x10701000c36f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL223"             ,	   0x10701000c36f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL224"             ,	   0x10701000c3700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL225"             ,	   0x10701000c3708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL226"             ,	   0x10701000c3710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL227"             ,	   0x10701000c3718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL228"             ,	   0x10701000c3720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL229"             ,	   0x10701000c3728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL230"             ,	   0x10701000c3730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL231"             ,	   0x10701000c3738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL232"             ,	   0x10701000c3740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL233"             ,	   0x10701000c3748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL234"             ,	   0x10701000c3750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL235"             ,	   0x10701000c3758ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL236"             ,	   0x10701000c3760ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL237"             ,	   0x10701000c3768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL238"             ,	   0x10701000c3770ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL239"             ,	   0x10701000c3778ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL240"             ,	   0x10701000c3780ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL241"             ,	   0x10701000c3788ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL242"             ,	   0x10701000c3790ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL243"             ,	   0x10701000c3798ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL244"             ,	   0x10701000c37a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL245"             ,	   0x10701000c37a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL246"             ,	   0x10701000c37b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL247"             ,	   0x10701000c37b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL248"             ,	   0x10701000c37c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL249"             ,	   0x10701000c37c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL250"             ,	   0x10701000c37d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL251"             ,	   0x10701000c37d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL252"             ,	   0x10701000c37e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL253"             ,	   0x10701000c37e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL254"             ,	   0x10701000c37f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL255"             ,	   0x10701000c37f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSIRED_PP0_IP2"         ,	   0x10701000c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP1_IP2"         ,	   0x10701002c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP2_IP2"         ,	   0x10701004c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP3_IP2"         ,	   0x10701006c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP4_IP2"         ,	   0x10701008c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP5_IP2"         ,	   0x1070100ac1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP6_IP2"         ,	   0x1070100cc1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP7_IP2"         ,	   0x1070100ec1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP8_IP2"         ,	   0x10701010c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP9_IP2"         ,	   0x10701012c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP10_IP2"        ,	   0x10701014c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP11_IP2"        ,	   0x10701016c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP12_IP2"        ,	   0x10701018c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP13_IP2"        ,	   0x1070101ac1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP14_IP2"        ,	   0x1070101cc1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP15_IP2"        ,	   0x1070101ec1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP16_IP2"        ,	   0x10701020c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP17_IP2"        ,	   0x10701022c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP18_IP2"        ,	   0x10701024c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP19_IP2"        ,	   0x10701026c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP20_IP2"        ,	   0x10701028c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP21_IP2"        ,	   0x1070102ac1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP22_IP2"        ,	   0x1070102cc1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP23_IP2"        ,	   0x1070102ec1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP24_IP2"        ,	   0x10701030c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP25_IP2"        ,	   0x10701032c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP26_IP2"        ,	   0x10701034c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP27_IP2"        ,	   0x10701036c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP28_IP2"        ,	   0x10701038c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP29_IP2"        ,	   0x1070103ac1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP30_IP2"        ,	   0x1070103cc1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP31_IP2"        ,	   0x1070103ec1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP0_IP3"         ,	   0x10701000c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP1_IP3"         ,	   0x10701002c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP2_IP3"         ,	   0x10701004c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP3_IP3"         ,	   0x10701006c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP4_IP3"         ,	   0x10701008c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP5_IP3"         ,	   0x1070100ac1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP6_IP3"         ,	   0x1070100cc1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP7_IP3"         ,	   0x1070100ec1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP8_IP3"         ,	   0x10701010c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP9_IP3"         ,	   0x10701012c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP10_IP3"        ,	   0x10701014c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP11_IP3"        ,	   0x10701016c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP12_IP3"        ,	   0x10701018c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP13_IP3"        ,	   0x1070101ac1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP14_IP3"        ,	   0x1070101cc1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP15_IP3"        ,	   0x1070101ec1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP16_IP3"        ,	   0x10701020c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP17_IP3"        ,	   0x10701022c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP18_IP3"        ,	   0x10701024c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP19_IP3"        ,	   0x10701026c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP20_IP3"        ,	   0x10701028c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP21_IP3"        ,	   0x1070102ac1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP22_IP3"        ,	   0x1070102cc1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP23_IP3"        ,	   0x1070102ec1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP24_IP3"        ,	   0x10701030c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP25_IP3"        ,	   0x10701032c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP26_IP3"        ,	   0x10701034c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP27_IP3"        ,	   0x10701036c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP28_IP3"        ,	   0x10701038c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP29_IP3"        ,	   0x1070103ac1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP30_IP3"        ,	   0x1070103cc1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP31_IP3"        ,	   0x1070103ec1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP0_IP4"         ,	   0x10701000c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP1_IP4"         ,	   0x10701002c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP2_IP4"         ,	   0x10701004c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP3_IP4"         ,	   0x10701006c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP4_IP4"         ,	   0x10701008c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP5_IP4"         ,	   0x1070100ac1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP6_IP4"         ,	   0x1070100cc1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP7_IP4"         ,	   0x1070100ec1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP8_IP4"         ,	   0x10701010c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP9_IP4"         ,	   0x10701012c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP10_IP4"        ,	   0x10701014c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP11_IP4"        ,	   0x10701016c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP12_IP4"        ,	   0x10701018c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP13_IP4"        ,	   0x1070101ac1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP14_IP4"        ,	   0x1070101cc1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP15_IP4"        ,	   0x1070101ec1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP16_IP4"        ,	   0x10701020c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP17_IP4"        ,	   0x10701022c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP18_IP4"        ,	   0x10701024c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP19_IP4"        ,	   0x10701026c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP20_IP4"        ,	   0x10701028c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP21_IP4"        ,	   0x1070102ac1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP22_IP4"        ,	   0x1070102cc1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP23_IP4"        ,	   0x1070102ec1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP24_IP4"        ,	   0x10701030c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP25_IP4"        ,	   0x10701032c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP26_IP4"        ,	   0x10701034c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP27_IP4"        ,	   0x10701036c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP28_IP4"        ,	   0x10701038c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP29_IP4"        ,	   0x1070103ac1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP30_IP4"        ,	   0x1070103cc1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP31_IP4"        ,	   0x1070103ec1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_RAW_IO0_INT_GPIO"       ,	   0x1070108047800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	193},
+	{"CIU2_RAW_IO1_INT_GPIO"       ,	   0x1070108247800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	193},
+	{"CIU2_RAW_IO0_INT_IO"         ,	   0x1070108044800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"CIU2_RAW_IO1_INT_IO"         ,	   0x1070108244800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"CIU2_RAW_IO0_INT_MEM"        ,	   0x1070108045800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"CIU2_RAW_IO1_INT_MEM"        ,	   0x1070108245800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"CIU2_RAW_IO0_INT_MIO"        ,	   0x1070108043800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"CIU2_RAW_IO1_INT_MIO"        ,	   0x1070108243800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"CIU2_RAW_IO0_INT_PKT"        ,	   0x1070108046800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"CIU2_RAW_IO1_INT_PKT"        ,	   0x1070108246800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"CIU2_RAW_IO0_INT_RML"        ,	   0x1070108042800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"CIU2_RAW_IO1_INT_RML"        ,	   0x1070108242800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"CIU2_RAW_IO0_INT_WDOG"       ,	   0x1070108041800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"CIU2_RAW_IO1_INT_WDOG"       ,	   0x1070108241800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"CIU2_RAW_IO0_INT_WRKQ"       ,	   0x1070108040800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"CIU2_RAW_IO1_INT_WRKQ"       ,	   0x1070108240800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"CIU2_RAW_PP0_IP2_GPIO"       ,	   0x1070100047000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP1_IP2_GPIO"       ,	   0x1070100247000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP2_IP2_GPIO"       ,	   0x1070100447000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP3_IP2_GPIO"       ,	   0x1070100647000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP4_IP2_GPIO"       ,	   0x1070100847000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP5_IP2_GPIO"       ,	   0x1070100a47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP6_IP2_GPIO"       ,	   0x1070100c47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP7_IP2_GPIO"       ,	   0x1070100e47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP8_IP2_GPIO"       ,	   0x1070101047000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP9_IP2_GPIO"       ,	   0x1070101247000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP10_IP2_GPIO"      ,	   0x1070101447000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP11_IP2_GPIO"      ,	   0x1070101647000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP12_IP2_GPIO"      ,	   0x1070101847000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP13_IP2_GPIO"      ,	   0x1070101a47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP14_IP2_GPIO"      ,	   0x1070101c47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP15_IP2_GPIO"      ,	   0x1070101e47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP16_IP2_GPIO"      ,	   0x1070102047000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP17_IP2_GPIO"      ,	   0x1070102247000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP18_IP2_GPIO"      ,	   0x1070102447000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP19_IP2_GPIO"      ,	   0x1070102647000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP20_IP2_GPIO"      ,	   0x1070102847000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP21_IP2_GPIO"      ,	   0x1070102a47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP22_IP2_GPIO"      ,	   0x1070102c47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP23_IP2_GPIO"      ,	   0x1070102e47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP24_IP2_GPIO"      ,	   0x1070103047000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP25_IP2_GPIO"      ,	   0x1070103247000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP26_IP2_GPIO"      ,	   0x1070103447000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP27_IP2_GPIO"      ,	   0x1070103647000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP28_IP2_GPIO"      ,	   0x1070103847000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP29_IP2_GPIO"      ,	   0x1070103a47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP30_IP2_GPIO"      ,	   0x1070103c47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP31_IP2_GPIO"      ,	   0x1070103e47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP0_IP2_IO"         ,	   0x1070100044000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP1_IP2_IO"         ,	   0x1070100244000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP2_IP2_IO"         ,	   0x1070100444000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP3_IP2_IO"         ,	   0x1070100644000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP4_IP2_IO"         ,	   0x1070100844000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP5_IP2_IO"         ,	   0x1070100a44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP6_IP2_IO"         ,	   0x1070100c44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP7_IP2_IO"         ,	   0x1070100e44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP8_IP2_IO"         ,	   0x1070101044000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP9_IP2_IO"         ,	   0x1070101244000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP10_IP2_IO"        ,	   0x1070101444000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP11_IP2_IO"        ,	   0x1070101644000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP12_IP2_IO"        ,	   0x1070101844000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP13_IP2_IO"        ,	   0x1070101a44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP14_IP2_IO"        ,	   0x1070101c44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP15_IP2_IO"        ,	   0x1070101e44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP16_IP2_IO"        ,	   0x1070102044000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP17_IP2_IO"        ,	   0x1070102244000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP18_IP2_IO"        ,	   0x1070102444000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP19_IP2_IO"        ,	   0x1070102644000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP20_IP2_IO"        ,	   0x1070102844000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP21_IP2_IO"        ,	   0x1070102a44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP22_IP2_IO"        ,	   0x1070102c44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP23_IP2_IO"        ,	   0x1070102e44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP24_IP2_IO"        ,	   0x1070103044000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP25_IP2_IO"        ,	   0x1070103244000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP26_IP2_IO"        ,	   0x1070103444000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP27_IP2_IO"        ,	   0x1070103644000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP28_IP2_IO"        ,	   0x1070103844000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP29_IP2_IO"        ,	   0x1070103a44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP30_IP2_IO"        ,	   0x1070103c44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP31_IP2_IO"        ,	   0x1070103e44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP0_IP2_MEM"        ,	   0x1070100045000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP1_IP2_MEM"        ,	   0x1070100245000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP2_IP2_MEM"        ,	   0x1070100445000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP3_IP2_MEM"        ,	   0x1070100645000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP4_IP2_MEM"        ,	   0x1070100845000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP5_IP2_MEM"        ,	   0x1070100a45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP6_IP2_MEM"        ,	   0x1070100c45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP7_IP2_MEM"        ,	   0x1070100e45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP8_IP2_MEM"        ,	   0x1070101045000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP9_IP2_MEM"        ,	   0x1070101245000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP10_IP2_MEM"       ,	   0x1070101445000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP11_IP2_MEM"       ,	   0x1070101645000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP12_IP2_MEM"       ,	   0x1070101845000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP13_IP2_MEM"       ,	   0x1070101a45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP14_IP2_MEM"       ,	   0x1070101c45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP15_IP2_MEM"       ,	   0x1070101e45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP16_IP2_MEM"       ,	   0x1070102045000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP17_IP2_MEM"       ,	   0x1070102245000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP18_IP2_MEM"       ,	   0x1070102445000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP19_IP2_MEM"       ,	   0x1070102645000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP20_IP2_MEM"       ,	   0x1070102845000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP21_IP2_MEM"       ,	   0x1070102a45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP22_IP2_MEM"       ,	   0x1070102c45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP23_IP2_MEM"       ,	   0x1070102e45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP24_IP2_MEM"       ,	   0x1070103045000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP25_IP2_MEM"       ,	   0x1070103245000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP26_IP2_MEM"       ,	   0x1070103445000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP27_IP2_MEM"       ,	   0x1070103645000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP28_IP2_MEM"       ,	   0x1070103845000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP29_IP2_MEM"       ,	   0x1070103a45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP30_IP2_MEM"       ,	   0x1070103c45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP31_IP2_MEM"       ,	   0x1070103e45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP0_IP2_MIO"        ,	   0x1070100043000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP1_IP2_MIO"        ,	   0x1070100243000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP2_IP2_MIO"        ,	   0x1070100443000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP3_IP2_MIO"        ,	   0x1070100643000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP4_IP2_MIO"        ,	   0x1070100843000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP5_IP2_MIO"        ,	   0x1070100a43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP6_IP2_MIO"        ,	   0x1070100c43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP7_IP2_MIO"        ,	   0x1070100e43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP8_IP2_MIO"        ,	   0x1070101043000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP9_IP2_MIO"        ,	   0x1070101243000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP10_IP2_MIO"       ,	   0x1070101443000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP11_IP2_MIO"       ,	   0x1070101643000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP12_IP2_MIO"       ,	   0x1070101843000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP13_IP2_MIO"       ,	   0x1070101a43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP14_IP2_MIO"       ,	   0x1070101c43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP15_IP2_MIO"       ,	   0x1070101e43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP16_IP2_MIO"       ,	   0x1070102043000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP17_IP2_MIO"       ,	   0x1070102243000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP18_IP2_MIO"       ,	   0x1070102443000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP19_IP2_MIO"       ,	   0x1070102643000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP20_IP2_MIO"       ,	   0x1070102843000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP21_IP2_MIO"       ,	   0x1070102a43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP22_IP2_MIO"       ,	   0x1070102c43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP23_IP2_MIO"       ,	   0x1070102e43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP24_IP2_MIO"       ,	   0x1070103043000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP25_IP2_MIO"       ,	   0x1070103243000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP26_IP2_MIO"       ,	   0x1070103443000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP27_IP2_MIO"       ,	   0x1070103643000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP28_IP2_MIO"       ,	   0x1070103843000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP29_IP2_MIO"       ,	   0x1070103a43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP30_IP2_MIO"       ,	   0x1070103c43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP31_IP2_MIO"       ,	   0x1070103e43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP0_IP2_PKT"        ,	   0x1070100046000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP1_IP2_PKT"        ,	   0x1070100246000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP2_IP2_PKT"        ,	   0x1070100446000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP3_IP2_PKT"        ,	   0x1070100646000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP4_IP2_PKT"        ,	   0x1070100846000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP5_IP2_PKT"        ,	   0x1070100a46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP6_IP2_PKT"        ,	   0x1070100c46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP7_IP2_PKT"        ,	   0x1070100e46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP8_IP2_PKT"        ,	   0x1070101046000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP9_IP2_PKT"        ,	   0x1070101246000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP10_IP2_PKT"       ,	   0x1070101446000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP11_IP2_PKT"       ,	   0x1070101646000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP12_IP2_PKT"       ,	   0x1070101846000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP13_IP2_PKT"       ,	   0x1070101a46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP14_IP2_PKT"       ,	   0x1070101c46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP15_IP2_PKT"       ,	   0x1070101e46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP16_IP2_PKT"       ,	   0x1070102046000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP17_IP2_PKT"       ,	   0x1070102246000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP18_IP2_PKT"       ,	   0x1070102446000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP19_IP2_PKT"       ,	   0x1070102646000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP20_IP2_PKT"       ,	   0x1070102846000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP21_IP2_PKT"       ,	   0x1070102a46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP22_IP2_PKT"       ,	   0x1070102c46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP23_IP2_PKT"       ,	   0x1070102e46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP24_IP2_PKT"       ,	   0x1070103046000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP25_IP2_PKT"       ,	   0x1070103246000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP26_IP2_PKT"       ,	   0x1070103446000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP27_IP2_PKT"       ,	   0x1070103646000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP28_IP2_PKT"       ,	   0x1070103846000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP29_IP2_PKT"       ,	   0x1070103a46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP30_IP2_PKT"       ,	   0x1070103c46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP31_IP2_PKT"       ,	   0x1070103e46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP0_IP2_RML"        ,	   0x1070100042000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP1_IP2_RML"        ,	   0x1070100242000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP2_IP2_RML"        ,	   0x1070100442000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP3_IP2_RML"        ,	   0x1070100642000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP4_IP2_RML"        ,	   0x1070100842000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP5_IP2_RML"        ,	   0x1070100a42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP6_IP2_RML"        ,	   0x1070100c42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP7_IP2_RML"        ,	   0x1070100e42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP8_IP2_RML"        ,	   0x1070101042000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP9_IP2_RML"        ,	   0x1070101242000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP10_IP2_RML"       ,	   0x1070101442000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP11_IP2_RML"       ,	   0x1070101642000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP12_IP2_RML"       ,	   0x1070101842000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP13_IP2_RML"       ,	   0x1070101a42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP14_IP2_RML"       ,	   0x1070101c42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP15_IP2_RML"       ,	   0x1070101e42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP16_IP2_RML"       ,	   0x1070102042000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP17_IP2_RML"       ,	   0x1070102242000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP18_IP2_RML"       ,	   0x1070102442000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP19_IP2_RML"       ,	   0x1070102642000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP20_IP2_RML"       ,	   0x1070102842000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP21_IP2_RML"       ,	   0x1070102a42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP22_IP2_RML"       ,	   0x1070102c42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP23_IP2_RML"       ,	   0x1070102e42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP24_IP2_RML"       ,	   0x1070103042000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP25_IP2_RML"       ,	   0x1070103242000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP26_IP2_RML"       ,	   0x1070103442000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP27_IP2_RML"       ,	   0x1070103642000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP28_IP2_RML"       ,	   0x1070103842000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP29_IP2_RML"       ,	   0x1070103a42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP30_IP2_RML"       ,	   0x1070103c42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP31_IP2_RML"       ,	   0x1070103e42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP0_IP2_WDOG"       ,	   0x1070100041000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP1_IP2_WDOG"       ,	   0x1070100241000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP2_IP2_WDOG"       ,	   0x1070100441000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP3_IP2_WDOG"       ,	   0x1070100641000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP4_IP2_WDOG"       ,	   0x1070100841000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP5_IP2_WDOG"       ,	   0x1070100a41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP6_IP2_WDOG"       ,	   0x1070100c41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP7_IP2_WDOG"       ,	   0x1070100e41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP8_IP2_WDOG"       ,	   0x1070101041000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP9_IP2_WDOG"       ,	   0x1070101241000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP10_IP2_WDOG"      ,	   0x1070101441000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP11_IP2_WDOG"      ,	   0x1070101641000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP12_IP2_WDOG"      ,	   0x1070101841000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP13_IP2_WDOG"      ,	   0x1070101a41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP14_IP2_WDOG"      ,	   0x1070101c41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP15_IP2_WDOG"      ,	   0x1070101e41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP16_IP2_WDOG"      ,	   0x1070102041000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP17_IP2_WDOG"      ,	   0x1070102241000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP18_IP2_WDOG"      ,	   0x1070102441000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP19_IP2_WDOG"      ,	   0x1070102641000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP20_IP2_WDOG"      ,	   0x1070102841000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP21_IP2_WDOG"      ,	   0x1070102a41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP22_IP2_WDOG"      ,	   0x1070102c41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP23_IP2_WDOG"      ,	   0x1070102e41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP24_IP2_WDOG"      ,	   0x1070103041000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP25_IP2_WDOG"      ,	   0x1070103241000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP26_IP2_WDOG"      ,	   0x1070103441000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP27_IP2_WDOG"      ,	   0x1070103641000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP28_IP2_WDOG"      ,	   0x1070103841000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP29_IP2_WDOG"      ,	   0x1070103a41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP30_IP2_WDOG"      ,	   0x1070103c41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP31_IP2_WDOG"      ,	   0x1070103e41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP0_IP2_WRKQ"       ,	   0x1070100040000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP1_IP2_WRKQ"       ,	   0x1070100240000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP2_IP2_WRKQ"       ,	   0x1070100440000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP3_IP2_WRKQ"       ,	   0x1070100640000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP4_IP2_WRKQ"       ,	   0x1070100840000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP5_IP2_WRKQ"       ,	   0x1070100a40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP6_IP2_WRKQ"       ,	   0x1070100c40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP7_IP2_WRKQ"       ,	   0x1070100e40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP8_IP2_WRKQ"       ,	   0x1070101040000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP9_IP2_WRKQ"       ,	   0x1070101240000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP10_IP2_WRKQ"      ,	   0x1070101440000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP11_IP2_WRKQ"      ,	   0x1070101640000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP12_IP2_WRKQ"      ,	   0x1070101840000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP13_IP2_WRKQ"      ,	   0x1070101a40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP14_IP2_WRKQ"      ,	   0x1070101c40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP15_IP2_WRKQ"      ,	   0x1070101e40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP16_IP2_WRKQ"      ,	   0x1070102040000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP17_IP2_WRKQ"      ,	   0x1070102240000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP18_IP2_WRKQ"      ,	   0x1070102440000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP19_IP2_WRKQ"      ,	   0x1070102640000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP20_IP2_WRKQ"      ,	   0x1070102840000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP21_IP2_WRKQ"      ,	   0x1070102a40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP22_IP2_WRKQ"      ,	   0x1070102c40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP23_IP2_WRKQ"      ,	   0x1070102e40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP24_IP2_WRKQ"      ,	   0x1070103040000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP25_IP2_WRKQ"      ,	   0x1070103240000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP26_IP2_WRKQ"      ,	   0x1070103440000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP27_IP2_WRKQ"      ,	   0x1070103640000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP28_IP2_WRKQ"      ,	   0x1070103840000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP29_IP2_WRKQ"      ,	   0x1070103a40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP30_IP2_WRKQ"      ,	   0x1070103c40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP31_IP2_WRKQ"      ,	   0x1070103e40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP0_IP3_GPIO"       ,	   0x1070100047200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP1_IP3_GPIO"       ,	   0x1070100247200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP2_IP3_GPIO"       ,	   0x1070100447200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP3_IP3_GPIO"       ,	   0x1070100647200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP4_IP3_GPIO"       ,	   0x1070100847200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP5_IP3_GPIO"       ,	   0x1070100a47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP6_IP3_GPIO"       ,	   0x1070100c47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP7_IP3_GPIO"       ,	   0x1070100e47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP8_IP3_GPIO"       ,	   0x1070101047200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP9_IP3_GPIO"       ,	   0x1070101247200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP10_IP3_GPIO"      ,	   0x1070101447200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP11_IP3_GPIO"      ,	   0x1070101647200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP12_IP3_GPIO"      ,	   0x1070101847200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP13_IP3_GPIO"      ,	   0x1070101a47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP14_IP3_GPIO"      ,	   0x1070101c47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP15_IP3_GPIO"      ,	   0x1070101e47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP16_IP3_GPIO"      ,	   0x1070102047200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP17_IP3_GPIO"      ,	   0x1070102247200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP18_IP3_GPIO"      ,	   0x1070102447200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP19_IP3_GPIO"      ,	   0x1070102647200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP20_IP3_GPIO"      ,	   0x1070102847200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP21_IP3_GPIO"      ,	   0x1070102a47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP22_IP3_GPIO"      ,	   0x1070102c47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP23_IP3_GPIO"      ,	   0x1070102e47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP24_IP3_GPIO"      ,	   0x1070103047200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP25_IP3_GPIO"      ,	   0x1070103247200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP26_IP3_GPIO"      ,	   0x1070103447200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP27_IP3_GPIO"      ,	   0x1070103647200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP28_IP3_GPIO"      ,	   0x1070103847200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP29_IP3_GPIO"      ,	   0x1070103a47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP30_IP3_GPIO"      ,	   0x1070103c47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP31_IP3_GPIO"      ,	   0x1070103e47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP0_IP3_IO"         ,	   0x1070100044200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP1_IP3_IO"         ,	   0x1070100244200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP2_IP3_IO"         ,	   0x1070100444200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP3_IP3_IO"         ,	   0x1070100644200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP4_IP3_IO"         ,	   0x1070100844200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP5_IP3_IO"         ,	   0x1070100a44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP6_IP3_IO"         ,	   0x1070100c44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP7_IP3_IO"         ,	   0x1070100e44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP8_IP3_IO"         ,	   0x1070101044200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP9_IP3_IO"         ,	   0x1070101244200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP10_IP3_IO"        ,	   0x1070101444200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP11_IP3_IO"        ,	   0x1070101644200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP12_IP3_IO"        ,	   0x1070101844200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP13_IP3_IO"        ,	   0x1070101a44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP14_IP3_IO"        ,	   0x1070101c44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP15_IP3_IO"        ,	   0x1070101e44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP16_IP3_IO"        ,	   0x1070102044200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP17_IP3_IO"        ,	   0x1070102244200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP18_IP3_IO"        ,	   0x1070102444200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP19_IP3_IO"        ,	   0x1070102644200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP20_IP3_IO"        ,	   0x1070102844200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP21_IP3_IO"        ,	   0x1070102a44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP22_IP3_IO"        ,	   0x1070102c44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP23_IP3_IO"        ,	   0x1070102e44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP24_IP3_IO"        ,	   0x1070103044200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP25_IP3_IO"        ,	   0x1070103244200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP26_IP3_IO"        ,	   0x1070103444200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP27_IP3_IO"        ,	   0x1070103644200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP28_IP3_IO"        ,	   0x1070103844200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP29_IP3_IO"        ,	   0x1070103a44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP30_IP3_IO"        ,	   0x1070103c44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP31_IP3_IO"        ,	   0x1070103e44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP0_IP3_MEM"        ,	   0x1070100045200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP1_IP3_MEM"        ,	   0x1070100245200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP2_IP3_MEM"        ,	   0x1070100445200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP3_IP3_MEM"        ,	   0x1070100645200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP4_IP3_MEM"        ,	   0x1070100845200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP5_IP3_MEM"        ,	   0x1070100a45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP6_IP3_MEM"        ,	   0x1070100c45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP7_IP3_MEM"        ,	   0x1070100e45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP8_IP3_MEM"        ,	   0x1070101045200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP9_IP3_MEM"        ,	   0x1070101245200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP10_IP3_MEM"       ,	   0x1070101445200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP11_IP3_MEM"       ,	   0x1070101645200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP12_IP3_MEM"       ,	   0x1070101845200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP13_IP3_MEM"       ,	   0x1070101a45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP14_IP3_MEM"       ,	   0x1070101c45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP15_IP3_MEM"       ,	   0x1070101e45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP16_IP3_MEM"       ,	   0x1070102045200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP17_IP3_MEM"       ,	   0x1070102245200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP18_IP3_MEM"       ,	   0x1070102445200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP19_IP3_MEM"       ,	   0x1070102645200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP20_IP3_MEM"       ,	   0x1070102845200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP21_IP3_MEM"       ,	   0x1070102a45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP22_IP3_MEM"       ,	   0x1070102c45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP23_IP3_MEM"       ,	   0x1070102e45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP24_IP3_MEM"       ,	   0x1070103045200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP25_IP3_MEM"       ,	   0x1070103245200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP26_IP3_MEM"       ,	   0x1070103445200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP27_IP3_MEM"       ,	   0x1070103645200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP28_IP3_MEM"       ,	   0x1070103845200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP29_IP3_MEM"       ,	   0x1070103a45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP30_IP3_MEM"       ,	   0x1070103c45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP31_IP3_MEM"       ,	   0x1070103e45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP0_IP3_MIO"        ,	   0x1070100043200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP1_IP3_MIO"        ,	   0x1070100243200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP2_IP3_MIO"        ,	   0x1070100443200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP3_IP3_MIO"        ,	   0x1070100643200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP4_IP3_MIO"        ,	   0x1070100843200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP5_IP3_MIO"        ,	   0x1070100a43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP6_IP3_MIO"        ,	   0x1070100c43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP7_IP3_MIO"        ,	   0x1070100e43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP8_IP3_MIO"        ,	   0x1070101043200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP9_IP3_MIO"        ,	   0x1070101243200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP10_IP3_MIO"       ,	   0x1070101443200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP11_IP3_MIO"       ,	   0x1070101643200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP12_IP3_MIO"       ,	   0x1070101843200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP13_IP3_MIO"       ,	   0x1070101a43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP14_IP3_MIO"       ,	   0x1070101c43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP15_IP3_MIO"       ,	   0x1070101e43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP16_IP3_MIO"       ,	   0x1070102043200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP17_IP3_MIO"       ,	   0x1070102243200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP18_IP3_MIO"       ,	   0x1070102443200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP19_IP3_MIO"       ,	   0x1070102643200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP20_IP3_MIO"       ,	   0x1070102843200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP21_IP3_MIO"       ,	   0x1070102a43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP22_IP3_MIO"       ,	   0x1070102c43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP23_IP3_MIO"       ,	   0x1070102e43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP24_IP3_MIO"       ,	   0x1070103043200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP25_IP3_MIO"       ,	   0x1070103243200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP26_IP3_MIO"       ,	   0x1070103443200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP27_IP3_MIO"       ,	   0x1070103643200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP28_IP3_MIO"       ,	   0x1070103843200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP29_IP3_MIO"       ,	   0x1070103a43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP30_IP3_MIO"       ,	   0x1070103c43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP31_IP3_MIO"       ,	   0x1070103e43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP0_IP3_PKT"        ,	   0x1070100046200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP1_IP3_PKT"        ,	   0x1070100246200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP2_IP3_PKT"        ,	   0x1070100446200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP3_IP3_PKT"        ,	   0x1070100646200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP4_IP3_PKT"        ,	   0x1070100846200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP5_IP3_PKT"        ,	   0x1070100a46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP6_IP3_PKT"        ,	   0x1070100c46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP7_IP3_PKT"        ,	   0x1070100e46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP8_IP3_PKT"        ,	   0x1070101046200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP9_IP3_PKT"        ,	   0x1070101246200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP10_IP3_PKT"       ,	   0x1070101446200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP11_IP3_PKT"       ,	   0x1070101646200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP12_IP3_PKT"       ,	   0x1070101846200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP13_IP3_PKT"       ,	   0x1070101a46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP14_IP3_PKT"       ,	   0x1070101c46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP15_IP3_PKT"       ,	   0x1070101e46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP16_IP3_PKT"       ,	   0x1070102046200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP17_IP3_PKT"       ,	   0x1070102246200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP18_IP3_PKT"       ,	   0x1070102446200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP19_IP3_PKT"       ,	   0x1070102646200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP20_IP3_PKT"       ,	   0x1070102846200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP21_IP3_PKT"       ,	   0x1070102a46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP22_IP3_PKT"       ,	   0x1070102c46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP23_IP3_PKT"       ,	   0x1070102e46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP24_IP3_PKT"       ,	   0x1070103046200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP25_IP3_PKT"       ,	   0x1070103246200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP26_IP3_PKT"       ,	   0x1070103446200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP27_IP3_PKT"       ,	   0x1070103646200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP28_IP3_PKT"       ,	   0x1070103846200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP29_IP3_PKT"       ,	   0x1070103a46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP30_IP3_PKT"       ,	   0x1070103c46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP31_IP3_PKT"       ,	   0x1070103e46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP0_IP3_RML"        ,	   0x1070100042200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP1_IP3_RML"        ,	   0x1070100242200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP2_IP3_RML"        ,	   0x1070100442200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP3_IP3_RML"        ,	   0x1070100642200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP4_IP3_RML"        ,	   0x1070100842200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP5_IP3_RML"        ,	   0x1070100a42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP6_IP3_RML"        ,	   0x1070100c42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP7_IP3_RML"        ,	   0x1070100e42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP8_IP3_RML"        ,	   0x1070101042200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP9_IP3_RML"        ,	   0x1070101242200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP10_IP3_RML"       ,	   0x1070101442200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP11_IP3_RML"       ,	   0x1070101642200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP12_IP3_RML"       ,	   0x1070101842200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP13_IP3_RML"       ,	   0x1070101a42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP14_IP3_RML"       ,	   0x1070101c42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP15_IP3_RML"       ,	   0x1070101e42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP16_IP3_RML"       ,	   0x1070102042200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP17_IP3_RML"       ,	   0x1070102242200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP18_IP3_RML"       ,	   0x1070102442200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP19_IP3_RML"       ,	   0x1070102642200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP20_IP3_RML"       ,	   0x1070102842200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP21_IP3_RML"       ,	   0x1070102a42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP22_IP3_RML"       ,	   0x1070102c42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP23_IP3_RML"       ,	   0x1070102e42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP24_IP3_RML"       ,	   0x1070103042200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP25_IP3_RML"       ,	   0x1070103242200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP26_IP3_RML"       ,	   0x1070103442200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP27_IP3_RML"       ,	   0x1070103642200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP28_IP3_RML"       ,	   0x1070103842200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP29_IP3_RML"       ,	   0x1070103a42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP30_IP3_RML"       ,	   0x1070103c42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP31_IP3_RML"       ,	   0x1070103e42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP0_IP3_WDOG"       ,	   0x1070100041200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP1_IP3_WDOG"       ,	   0x1070100241200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP2_IP3_WDOG"       ,	   0x1070100441200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP3_IP3_WDOG"       ,	   0x1070100641200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP4_IP3_WDOG"       ,	   0x1070100841200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP5_IP3_WDOG"       ,	   0x1070100a41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP6_IP3_WDOG"       ,	   0x1070100c41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP7_IP3_WDOG"       ,	   0x1070100e41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP8_IP3_WDOG"       ,	   0x1070101041200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP9_IP3_WDOG"       ,	   0x1070101241200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP10_IP3_WDOG"      ,	   0x1070101441200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP11_IP3_WDOG"      ,	   0x1070101641200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP12_IP3_WDOG"      ,	   0x1070101841200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP13_IP3_WDOG"      ,	   0x1070101a41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP14_IP3_WDOG"      ,	   0x1070101c41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP15_IP3_WDOG"      ,	   0x1070101e41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP16_IP3_WDOG"      ,	   0x1070102041200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP17_IP3_WDOG"      ,	   0x1070102241200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP18_IP3_WDOG"      ,	   0x1070102441200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP19_IP3_WDOG"      ,	   0x1070102641200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP20_IP3_WDOG"      ,	   0x1070102841200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP21_IP3_WDOG"      ,	   0x1070102a41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP22_IP3_WDOG"      ,	   0x1070102c41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP23_IP3_WDOG"      ,	   0x1070102e41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP24_IP3_WDOG"      ,	   0x1070103041200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP25_IP3_WDOG"      ,	   0x1070103241200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP26_IP3_WDOG"      ,	   0x1070103441200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP27_IP3_WDOG"      ,	   0x1070103641200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP28_IP3_WDOG"      ,	   0x1070103841200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP29_IP3_WDOG"      ,	   0x1070103a41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP30_IP3_WDOG"      ,	   0x1070103c41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP31_IP3_WDOG"      ,	   0x1070103e41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP0_IP3_WRKQ"       ,	   0x1070100040200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP1_IP3_WRKQ"       ,	   0x1070100240200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP2_IP3_WRKQ"       ,	   0x1070100440200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP3_IP3_WRKQ"       ,	   0x1070100640200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP4_IP3_WRKQ"       ,	   0x1070100840200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP5_IP3_WRKQ"       ,	   0x1070100a40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP6_IP3_WRKQ"       ,	   0x1070100c40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP7_IP3_WRKQ"       ,	   0x1070100e40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP8_IP3_WRKQ"       ,	   0x1070101040200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP9_IP3_WRKQ"       ,	   0x1070101240200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP10_IP3_WRKQ"      ,	   0x1070101440200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP11_IP3_WRKQ"      ,	   0x1070101640200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP12_IP3_WRKQ"      ,	   0x1070101840200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP13_IP3_WRKQ"      ,	   0x1070101a40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP14_IP3_WRKQ"      ,	   0x1070101c40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP15_IP3_WRKQ"      ,	   0x1070101e40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP16_IP3_WRKQ"      ,	   0x1070102040200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP17_IP3_WRKQ"      ,	   0x1070102240200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP18_IP3_WRKQ"      ,	   0x1070102440200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP19_IP3_WRKQ"      ,	   0x1070102640200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP20_IP3_WRKQ"      ,	   0x1070102840200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP21_IP3_WRKQ"      ,	   0x1070102a40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP22_IP3_WRKQ"      ,	   0x1070102c40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP23_IP3_WRKQ"      ,	   0x1070102e40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP24_IP3_WRKQ"      ,	   0x1070103040200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP25_IP3_WRKQ"      ,	   0x1070103240200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP26_IP3_WRKQ"      ,	   0x1070103440200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP27_IP3_WRKQ"      ,	   0x1070103640200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP28_IP3_WRKQ"      ,	   0x1070103840200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP29_IP3_WRKQ"      ,	   0x1070103a40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP30_IP3_WRKQ"      ,	   0x1070103c40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP31_IP3_WRKQ"      ,	   0x1070103e40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP0_IP4_GPIO"       ,	   0x1070100047400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP1_IP4_GPIO"       ,	   0x1070100247400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP2_IP4_GPIO"       ,	   0x1070100447400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP3_IP4_GPIO"       ,	   0x1070100647400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP4_IP4_GPIO"       ,	   0x1070100847400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP5_IP4_GPIO"       ,	   0x1070100a47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP6_IP4_GPIO"       ,	   0x1070100c47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP7_IP4_GPIO"       ,	   0x1070100e47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP8_IP4_GPIO"       ,	   0x1070101047400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP9_IP4_GPIO"       ,	   0x1070101247400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP10_IP4_GPIO"      ,	   0x1070101447400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP11_IP4_GPIO"      ,	   0x1070101647400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP12_IP4_GPIO"      ,	   0x1070101847400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP13_IP4_GPIO"      ,	   0x1070101a47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP14_IP4_GPIO"      ,	   0x1070101c47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP15_IP4_GPIO"      ,	   0x1070101e47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP16_IP4_GPIO"      ,	   0x1070102047400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP17_IP4_GPIO"      ,	   0x1070102247400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP18_IP4_GPIO"      ,	   0x1070102447400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP19_IP4_GPIO"      ,	   0x1070102647400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP20_IP4_GPIO"      ,	   0x1070102847400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP21_IP4_GPIO"      ,	   0x1070102a47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP22_IP4_GPIO"      ,	   0x1070102c47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP23_IP4_GPIO"      ,	   0x1070102e47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP24_IP4_GPIO"      ,	   0x1070103047400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP25_IP4_GPIO"      ,	   0x1070103247400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP26_IP4_GPIO"      ,	   0x1070103447400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP27_IP4_GPIO"      ,	   0x1070103647400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP28_IP4_GPIO"      ,	   0x1070103847400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP29_IP4_GPIO"      ,	   0x1070103a47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP30_IP4_GPIO"      ,	   0x1070103c47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP31_IP4_GPIO"      ,	   0x1070103e47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP0_IP4_IO"         ,	   0x1070100044400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP1_IP4_IO"         ,	   0x1070100244400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP2_IP4_IO"         ,	   0x1070100444400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP3_IP4_IO"         ,	   0x1070100644400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP4_IP4_IO"         ,	   0x1070100844400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP5_IP4_IO"         ,	   0x1070100a44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP6_IP4_IO"         ,	   0x1070100c44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP7_IP4_IO"         ,	   0x1070100e44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP8_IP4_IO"         ,	   0x1070101044400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP9_IP4_IO"         ,	   0x1070101244400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP10_IP4_IO"        ,	   0x1070101444400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP11_IP4_IO"        ,	   0x1070101644400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP12_IP4_IO"        ,	   0x1070101844400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP13_IP4_IO"        ,	   0x1070101a44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP14_IP4_IO"        ,	   0x1070101c44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP15_IP4_IO"        ,	   0x1070101e44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP16_IP4_IO"        ,	   0x1070102044400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP17_IP4_IO"        ,	   0x1070102244400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP18_IP4_IO"        ,	   0x1070102444400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP19_IP4_IO"        ,	   0x1070102644400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP20_IP4_IO"        ,	   0x1070102844400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP21_IP4_IO"        ,	   0x1070102a44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP22_IP4_IO"        ,	   0x1070102c44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP23_IP4_IO"        ,	   0x1070102e44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP24_IP4_IO"        ,	   0x1070103044400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP25_IP4_IO"        ,	   0x1070103244400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP26_IP4_IO"        ,	   0x1070103444400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP27_IP4_IO"        ,	   0x1070103644400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP28_IP4_IO"        ,	   0x1070103844400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP29_IP4_IO"        ,	   0x1070103a44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP30_IP4_IO"        ,	   0x1070103c44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP31_IP4_IO"        ,	   0x1070103e44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP0_IP4_MEM"        ,	   0x1070100045400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP1_IP4_MEM"        ,	   0x1070100245400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP2_IP4_MEM"        ,	   0x1070100445400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP3_IP4_MEM"        ,	   0x1070100645400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP4_IP4_MEM"        ,	   0x1070100845400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP5_IP4_MEM"        ,	   0x1070100a45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP6_IP4_MEM"        ,	   0x1070100c45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP7_IP4_MEM"        ,	   0x1070100e45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP8_IP4_MEM"        ,	   0x1070101045400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP9_IP4_MEM"        ,	   0x1070101245400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP10_IP4_MEM"       ,	   0x1070101445400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP11_IP4_MEM"       ,	   0x1070101645400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP12_IP4_MEM"       ,	   0x1070101845400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP13_IP4_MEM"       ,	   0x1070101a45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP14_IP4_MEM"       ,	   0x1070101c45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP15_IP4_MEM"       ,	   0x1070101e45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP16_IP4_MEM"       ,	   0x1070102045400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP17_IP4_MEM"       ,	   0x1070102245400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP18_IP4_MEM"       ,	   0x1070102445400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP19_IP4_MEM"       ,	   0x1070102645400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP20_IP4_MEM"       ,	   0x1070102845400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP21_IP4_MEM"       ,	   0x1070102a45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP22_IP4_MEM"       ,	   0x1070102c45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP23_IP4_MEM"       ,	   0x1070102e45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP24_IP4_MEM"       ,	   0x1070103045400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP25_IP4_MEM"       ,	   0x1070103245400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP26_IP4_MEM"       ,	   0x1070103445400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP27_IP4_MEM"       ,	   0x1070103645400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP28_IP4_MEM"       ,	   0x1070103845400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP29_IP4_MEM"       ,	   0x1070103a45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP30_IP4_MEM"       ,	   0x1070103c45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP31_IP4_MEM"       ,	   0x1070103e45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP0_IP4_MIO"        ,	   0x1070100043400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP1_IP4_MIO"        ,	   0x1070100243400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP2_IP4_MIO"        ,	   0x1070100443400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP3_IP4_MIO"        ,	   0x1070100643400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP4_IP4_MIO"        ,	   0x1070100843400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP5_IP4_MIO"        ,	   0x1070100a43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP6_IP4_MIO"        ,	   0x1070100c43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP7_IP4_MIO"        ,	   0x1070100e43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP8_IP4_MIO"        ,	   0x1070101043400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP9_IP4_MIO"        ,	   0x1070101243400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP10_IP4_MIO"       ,	   0x1070101443400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP11_IP4_MIO"       ,	   0x1070101643400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP12_IP4_MIO"       ,	   0x1070101843400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP13_IP4_MIO"       ,	   0x1070101a43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP14_IP4_MIO"       ,	   0x1070101c43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP15_IP4_MIO"       ,	   0x1070101e43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP16_IP4_MIO"       ,	   0x1070102043400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP17_IP4_MIO"       ,	   0x1070102243400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP18_IP4_MIO"       ,	   0x1070102443400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP19_IP4_MIO"       ,	   0x1070102643400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP20_IP4_MIO"       ,	   0x1070102843400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP21_IP4_MIO"       ,	   0x1070102a43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP22_IP4_MIO"       ,	   0x1070102c43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP23_IP4_MIO"       ,	   0x1070102e43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP24_IP4_MIO"       ,	   0x1070103043400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP25_IP4_MIO"       ,	   0x1070103243400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP26_IP4_MIO"       ,	   0x1070103443400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP27_IP4_MIO"       ,	   0x1070103643400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP28_IP4_MIO"       ,	   0x1070103843400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP29_IP4_MIO"       ,	   0x1070103a43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP30_IP4_MIO"       ,	   0x1070103c43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP31_IP4_MIO"       ,	   0x1070103e43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP0_IP4_PKT"        ,	   0x1070100046400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP1_IP4_PKT"        ,	   0x1070100246400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP2_IP4_PKT"        ,	   0x1070100446400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP3_IP4_PKT"        ,	   0x1070100646400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP4_IP4_PKT"        ,	   0x1070100846400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP5_IP4_PKT"        ,	   0x1070100a46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP6_IP4_PKT"        ,	   0x1070100c46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP7_IP4_PKT"        ,	   0x1070100e46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP8_IP4_PKT"        ,	   0x1070101046400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP9_IP4_PKT"        ,	   0x1070101246400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP10_IP4_PKT"       ,	   0x1070101446400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP11_IP4_PKT"       ,	   0x1070101646400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP12_IP4_PKT"       ,	   0x1070101846400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP13_IP4_PKT"       ,	   0x1070101a46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP14_IP4_PKT"       ,	   0x1070101c46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP15_IP4_PKT"       ,	   0x1070101e46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP16_IP4_PKT"       ,	   0x1070102046400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP17_IP4_PKT"       ,	   0x1070102246400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP18_IP4_PKT"       ,	   0x1070102446400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP19_IP4_PKT"       ,	   0x1070102646400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP20_IP4_PKT"       ,	   0x1070102846400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP21_IP4_PKT"       ,	   0x1070102a46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP22_IP4_PKT"       ,	   0x1070102c46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP23_IP4_PKT"       ,	   0x1070102e46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP24_IP4_PKT"       ,	   0x1070103046400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP25_IP4_PKT"       ,	   0x1070103246400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP26_IP4_PKT"       ,	   0x1070103446400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP27_IP4_PKT"       ,	   0x1070103646400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP28_IP4_PKT"       ,	   0x1070103846400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP29_IP4_PKT"       ,	   0x1070103a46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP30_IP4_PKT"       ,	   0x1070103c46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP31_IP4_PKT"       ,	   0x1070103e46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP0_IP4_RML"        ,	   0x1070100042400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP1_IP4_RML"        ,	   0x1070100242400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP2_IP4_RML"        ,	   0x1070100442400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP3_IP4_RML"        ,	   0x1070100642400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP4_IP4_RML"        ,	   0x1070100842400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP5_IP4_RML"        ,	   0x1070100a42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP6_IP4_RML"        ,	   0x1070100c42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP7_IP4_RML"        ,	   0x1070100e42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP8_IP4_RML"        ,	   0x1070101042400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP9_IP4_RML"        ,	   0x1070101242400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP10_IP4_RML"       ,	   0x1070101442400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP11_IP4_RML"       ,	   0x1070101642400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP12_IP4_RML"       ,	   0x1070101842400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP13_IP4_RML"       ,	   0x1070101a42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP14_IP4_RML"       ,	   0x1070101c42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP15_IP4_RML"       ,	   0x1070101e42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP16_IP4_RML"       ,	   0x1070102042400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP17_IP4_RML"       ,	   0x1070102242400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP18_IP4_RML"       ,	   0x1070102442400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP19_IP4_RML"       ,	   0x1070102642400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP20_IP4_RML"       ,	   0x1070102842400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP21_IP4_RML"       ,	   0x1070102a42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP22_IP4_RML"       ,	   0x1070102c42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP23_IP4_RML"       ,	   0x1070102e42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP24_IP4_RML"       ,	   0x1070103042400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP25_IP4_RML"       ,	   0x1070103242400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP26_IP4_RML"       ,	   0x1070103442400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP27_IP4_RML"       ,	   0x1070103642400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP28_IP4_RML"       ,	   0x1070103842400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP29_IP4_RML"       ,	   0x1070103a42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP30_IP4_RML"       ,	   0x1070103c42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP31_IP4_RML"       ,	   0x1070103e42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP0_IP4_WDOG"       ,	   0x1070100041400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP1_IP4_WDOG"       ,	   0x1070100241400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP2_IP4_WDOG"       ,	   0x1070100441400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP3_IP4_WDOG"       ,	   0x1070100641400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP4_IP4_WDOG"       ,	   0x1070100841400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP5_IP4_WDOG"       ,	   0x1070100a41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP6_IP4_WDOG"       ,	   0x1070100c41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP7_IP4_WDOG"       ,	   0x1070100e41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP8_IP4_WDOG"       ,	   0x1070101041400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP9_IP4_WDOG"       ,	   0x1070101241400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP10_IP4_WDOG"      ,	   0x1070101441400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP11_IP4_WDOG"      ,	   0x1070101641400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP12_IP4_WDOG"      ,	   0x1070101841400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP13_IP4_WDOG"      ,	   0x1070101a41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP14_IP4_WDOG"      ,	   0x1070101c41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP15_IP4_WDOG"      ,	   0x1070101e41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP16_IP4_WDOG"      ,	   0x1070102041400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP17_IP4_WDOG"      ,	   0x1070102241400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP18_IP4_WDOG"      ,	   0x1070102441400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP19_IP4_WDOG"      ,	   0x1070102641400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP20_IP4_WDOG"      ,	   0x1070102841400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP21_IP4_WDOG"      ,	   0x1070102a41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP22_IP4_WDOG"      ,	   0x1070102c41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP23_IP4_WDOG"      ,	   0x1070102e41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP24_IP4_WDOG"      ,	   0x1070103041400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP25_IP4_WDOG"      ,	   0x1070103241400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP26_IP4_WDOG"      ,	   0x1070103441400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP27_IP4_WDOG"      ,	   0x1070103641400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP28_IP4_WDOG"      ,	   0x1070103841400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP29_IP4_WDOG"      ,	   0x1070103a41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP30_IP4_WDOG"      ,	   0x1070103c41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP31_IP4_WDOG"      ,	   0x1070103e41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP0_IP4_WRKQ"       ,	   0x1070100040400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP1_IP4_WRKQ"       ,	   0x1070100240400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP2_IP4_WRKQ"       ,	   0x1070100440400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP3_IP4_WRKQ"       ,	   0x1070100640400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP4_IP4_WRKQ"       ,	   0x1070100840400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP5_IP4_WRKQ"       ,	   0x1070100a40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP6_IP4_WRKQ"       ,	   0x1070100c40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP7_IP4_WRKQ"       ,	   0x1070100e40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP8_IP4_WRKQ"       ,	   0x1070101040400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP9_IP4_WRKQ"       ,	   0x1070101240400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP10_IP4_WRKQ"      ,	   0x1070101440400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP11_IP4_WRKQ"      ,	   0x1070101640400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP12_IP4_WRKQ"      ,	   0x1070101840400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP13_IP4_WRKQ"      ,	   0x1070101a40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP14_IP4_WRKQ"      ,	   0x1070101c40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP15_IP4_WRKQ"      ,	   0x1070101e40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP16_IP4_WRKQ"      ,	   0x1070102040400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP17_IP4_WRKQ"      ,	   0x1070102240400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP18_IP4_WRKQ"      ,	   0x1070102440400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP19_IP4_WRKQ"      ,	   0x1070102640400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP20_IP4_WRKQ"      ,	   0x1070102840400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP21_IP4_WRKQ"      ,	   0x1070102a40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP22_IP4_WRKQ"      ,	   0x1070102c40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP23_IP4_WRKQ"      ,	   0x1070102e40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP24_IP4_WRKQ"      ,	   0x1070103040400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP25_IP4_WRKQ"      ,	   0x1070103240400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP26_IP4_WRKQ"      ,	   0x1070103440400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP27_IP4_WRKQ"      ,	   0x1070103640400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP28_IP4_WRKQ"      ,	   0x1070103840400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP29_IP4_WRKQ"      ,	   0x1070103a40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP30_IP4_WRKQ"      ,	   0x1070103c40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP31_IP4_WRKQ"      ,	   0x1070103e40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_SRC_IO0_INT_GPIO"       ,	   0x1070108087800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	225},
+	{"CIU2_SRC_IO1_INT_GPIO"       ,	   0x1070108287800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	225},
+	{"CIU2_SRC_IO0_INT_IO"         ,	   0x1070108084800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	226},
+	{"CIU2_SRC_IO1_INT_IO"         ,	   0x1070108284800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	226},
+	{"CIU2_SRC_IO0_INT_MBOX"       ,	   0x1070108088800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	227},
+	{"CIU2_SRC_IO1_INT_MBOX"       ,	   0x1070108288800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	227},
+	{"CIU2_SRC_IO0_INT_MEM"        ,	   0x1070108085800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	228},
+	{"CIU2_SRC_IO1_INT_MEM"        ,	   0x1070108285800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	228},
+	{"CIU2_SRC_IO0_INT_MIO"        ,	   0x1070108083800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	229},
+	{"CIU2_SRC_IO1_INT_MIO"        ,	   0x1070108283800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	229},
+	{"CIU2_SRC_IO0_INT_PKT"        ,	   0x1070108086800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	230},
+	{"CIU2_SRC_IO1_INT_PKT"        ,	   0x1070108286800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	230},
+	{"CIU2_SRC_IO0_INT_RML"        ,	   0x1070108082800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"CIU2_SRC_IO1_INT_RML"        ,	   0x1070108282800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"CIU2_SRC_IO0_INT_WDOG"       ,	   0x1070108081800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"CIU2_SRC_IO1_INT_WDOG"       ,	   0x1070108281800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"CIU2_SRC_IO0_INT_WRKQ"       ,	   0x1070108080800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"CIU2_SRC_IO1_INT_WRKQ"       ,	   0x1070108280800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"CIU2_SRC_PP0_IP2_GPIO"       ,	   0x1070100087000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP1_IP2_GPIO"       ,	   0x1070100287000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP2_IP2_GPIO"       ,	   0x1070100487000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP3_IP2_GPIO"       ,	   0x1070100687000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP4_IP2_GPIO"       ,	   0x1070100887000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP5_IP2_GPIO"       ,	   0x1070100a87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP6_IP2_GPIO"       ,	   0x1070100c87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP7_IP2_GPIO"       ,	   0x1070100e87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP8_IP2_GPIO"       ,	   0x1070101087000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP9_IP2_GPIO"       ,	   0x1070101287000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP10_IP2_GPIO"      ,	   0x1070101487000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP11_IP2_GPIO"      ,	   0x1070101687000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP12_IP2_GPIO"      ,	   0x1070101887000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP13_IP2_GPIO"      ,	   0x1070101a87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP14_IP2_GPIO"      ,	   0x1070101c87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP15_IP2_GPIO"      ,	   0x1070101e87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP16_IP2_GPIO"      ,	   0x1070102087000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP17_IP2_GPIO"      ,	   0x1070102287000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP18_IP2_GPIO"      ,	   0x1070102487000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP19_IP2_GPIO"      ,	   0x1070102687000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP20_IP2_GPIO"      ,	   0x1070102887000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP21_IP2_GPIO"      ,	   0x1070102a87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP22_IP2_GPIO"      ,	   0x1070102c87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP23_IP2_GPIO"      ,	   0x1070102e87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP24_IP2_GPIO"      ,	   0x1070103087000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP25_IP2_GPIO"      ,	   0x1070103287000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP26_IP2_GPIO"      ,	   0x1070103487000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP27_IP2_GPIO"      ,	   0x1070103687000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP28_IP2_GPIO"      ,	   0x1070103887000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP29_IP2_GPIO"      ,	   0x1070103a87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP30_IP2_GPIO"      ,	   0x1070103c87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP31_IP2_GPIO"      ,	   0x1070103e87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP0_IP2_IO"         ,	   0x1070100084000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP1_IP2_IO"         ,	   0x1070100284000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP2_IP2_IO"         ,	   0x1070100484000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP3_IP2_IO"         ,	   0x1070100684000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP4_IP2_IO"         ,	   0x1070100884000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP5_IP2_IO"         ,	   0x1070100a84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP6_IP2_IO"         ,	   0x1070100c84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP7_IP2_IO"         ,	   0x1070100e84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP8_IP2_IO"         ,	   0x1070101084000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP9_IP2_IO"         ,	   0x1070101284000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP10_IP2_IO"        ,	   0x1070101484000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP11_IP2_IO"        ,	   0x1070101684000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP12_IP2_IO"        ,	   0x1070101884000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP13_IP2_IO"        ,	   0x1070101a84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP14_IP2_IO"        ,	   0x1070101c84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP15_IP2_IO"        ,	   0x1070101e84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP16_IP2_IO"        ,	   0x1070102084000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP17_IP2_IO"        ,	   0x1070102284000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP18_IP2_IO"        ,	   0x1070102484000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP19_IP2_IO"        ,	   0x1070102684000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP20_IP2_IO"        ,	   0x1070102884000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP21_IP2_IO"        ,	   0x1070102a84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP22_IP2_IO"        ,	   0x1070102c84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP23_IP2_IO"        ,	   0x1070102e84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP24_IP2_IO"        ,	   0x1070103084000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP25_IP2_IO"        ,	   0x1070103284000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP26_IP2_IO"        ,	   0x1070103484000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP27_IP2_IO"        ,	   0x1070103684000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP28_IP2_IO"        ,	   0x1070103884000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP29_IP2_IO"        ,	   0x1070103a84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP30_IP2_IO"        ,	   0x1070103c84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP31_IP2_IO"        ,	   0x1070103e84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP0_IP2_MBOX"       ,	   0x1070100088000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP1_IP2_MBOX"       ,	   0x1070100288000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP2_IP2_MBOX"       ,	   0x1070100488000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP3_IP2_MBOX"       ,	   0x1070100688000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP4_IP2_MBOX"       ,	   0x1070100888000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP5_IP2_MBOX"       ,	   0x1070100a88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP6_IP2_MBOX"       ,	   0x1070100c88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP7_IP2_MBOX"       ,	   0x1070100e88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP8_IP2_MBOX"       ,	   0x1070101088000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP9_IP2_MBOX"       ,	   0x1070101288000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP10_IP2_MBOX"      ,	   0x1070101488000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP11_IP2_MBOX"      ,	   0x1070101688000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP12_IP2_MBOX"      ,	   0x1070101888000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP13_IP2_MBOX"      ,	   0x1070101a88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP14_IP2_MBOX"      ,	   0x1070101c88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP15_IP2_MBOX"      ,	   0x1070101e88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP16_IP2_MBOX"      ,	   0x1070102088000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP17_IP2_MBOX"      ,	   0x1070102288000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP18_IP2_MBOX"      ,	   0x1070102488000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP19_IP2_MBOX"      ,	   0x1070102688000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP20_IP2_MBOX"      ,	   0x1070102888000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP21_IP2_MBOX"      ,	   0x1070102a88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP22_IP2_MBOX"      ,	   0x1070102c88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP23_IP2_MBOX"      ,	   0x1070102e88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP24_IP2_MBOX"      ,	   0x1070103088000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP25_IP2_MBOX"      ,	   0x1070103288000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP26_IP2_MBOX"      ,	   0x1070103488000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP27_IP2_MBOX"      ,	   0x1070103688000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP28_IP2_MBOX"      ,	   0x1070103888000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP29_IP2_MBOX"      ,	   0x1070103a88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP30_IP2_MBOX"      ,	   0x1070103c88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP31_IP2_MBOX"      ,	   0x1070103e88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP0_IP2_MEM"        ,	   0x1070100085000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP1_IP2_MEM"        ,	   0x1070100285000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP2_IP2_MEM"        ,	   0x1070100485000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP3_IP2_MEM"        ,	   0x1070100685000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP4_IP2_MEM"        ,	   0x1070100885000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP5_IP2_MEM"        ,	   0x1070100a85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP6_IP2_MEM"        ,	   0x1070100c85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP7_IP2_MEM"        ,	   0x1070100e85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP8_IP2_MEM"        ,	   0x1070101085000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP9_IP2_MEM"        ,	   0x1070101285000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP10_IP2_MEM"       ,	   0x1070101485000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP11_IP2_MEM"       ,	   0x1070101685000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP12_IP2_MEM"       ,	   0x1070101885000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP13_IP2_MEM"       ,	   0x1070101a85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP14_IP2_MEM"       ,	   0x1070101c85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP15_IP2_MEM"       ,	   0x1070101e85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP16_IP2_MEM"       ,	   0x1070102085000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP17_IP2_MEM"       ,	   0x1070102285000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP18_IP2_MEM"       ,	   0x1070102485000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP19_IP2_MEM"       ,	   0x1070102685000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP20_IP2_MEM"       ,	   0x1070102885000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP21_IP2_MEM"       ,	   0x1070102a85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP22_IP2_MEM"       ,	   0x1070102c85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP23_IP2_MEM"       ,	   0x1070102e85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP24_IP2_MEM"       ,	   0x1070103085000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP25_IP2_MEM"       ,	   0x1070103285000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP26_IP2_MEM"       ,	   0x1070103485000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP27_IP2_MEM"       ,	   0x1070103685000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP28_IP2_MEM"       ,	   0x1070103885000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP29_IP2_MEM"       ,	   0x1070103a85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP30_IP2_MEM"       ,	   0x1070103c85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP31_IP2_MEM"       ,	   0x1070103e85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP0_IP2_MIO"        ,	   0x1070100083000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP1_IP2_MIO"        ,	   0x1070100283000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP2_IP2_MIO"        ,	   0x1070100483000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP3_IP2_MIO"        ,	   0x1070100683000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP4_IP2_MIO"        ,	   0x1070100883000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP5_IP2_MIO"        ,	   0x1070100a83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP6_IP2_MIO"        ,	   0x1070100c83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP7_IP2_MIO"        ,	   0x1070100e83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP8_IP2_MIO"        ,	   0x1070101083000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP9_IP2_MIO"        ,	   0x1070101283000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP10_IP2_MIO"       ,	   0x1070101483000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP11_IP2_MIO"       ,	   0x1070101683000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP12_IP2_MIO"       ,	   0x1070101883000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP13_IP2_MIO"       ,	   0x1070101a83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP14_IP2_MIO"       ,	   0x1070101c83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP15_IP2_MIO"       ,	   0x1070101e83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP16_IP2_MIO"       ,	   0x1070102083000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP17_IP2_MIO"       ,	   0x1070102283000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP18_IP2_MIO"       ,	   0x1070102483000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP19_IP2_MIO"       ,	   0x1070102683000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP20_IP2_MIO"       ,	   0x1070102883000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP21_IP2_MIO"       ,	   0x1070102a83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP22_IP2_MIO"       ,	   0x1070102c83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP23_IP2_MIO"       ,	   0x1070102e83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP24_IP2_MIO"       ,	   0x1070103083000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP25_IP2_MIO"       ,	   0x1070103283000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP26_IP2_MIO"       ,	   0x1070103483000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP27_IP2_MIO"       ,	   0x1070103683000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP28_IP2_MIO"       ,	   0x1070103883000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP29_IP2_MIO"       ,	   0x1070103a83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP30_IP2_MIO"       ,	   0x1070103c83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP31_IP2_MIO"       ,	   0x1070103e83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP0_IP2_PKT"        ,	   0x1070100086000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP1_IP2_PKT"        ,	   0x1070100286000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP2_IP2_PKT"        ,	   0x1070100486000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP3_IP2_PKT"        ,	   0x1070100686000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP4_IP2_PKT"        ,	   0x1070100886000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP5_IP2_PKT"        ,	   0x1070100a86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP6_IP2_PKT"        ,	   0x1070100c86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP7_IP2_PKT"        ,	   0x1070100e86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP8_IP2_PKT"        ,	   0x1070101086000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP9_IP2_PKT"        ,	   0x1070101286000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP10_IP2_PKT"       ,	   0x1070101486000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP11_IP2_PKT"       ,	   0x1070101686000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP12_IP2_PKT"       ,	   0x1070101886000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP13_IP2_PKT"       ,	   0x1070101a86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP14_IP2_PKT"       ,	   0x1070101c86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP15_IP2_PKT"       ,	   0x1070101e86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP16_IP2_PKT"       ,	   0x1070102086000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP17_IP2_PKT"       ,	   0x1070102286000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP18_IP2_PKT"       ,	   0x1070102486000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP19_IP2_PKT"       ,	   0x1070102686000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP20_IP2_PKT"       ,	   0x1070102886000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP21_IP2_PKT"       ,	   0x1070102a86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP22_IP2_PKT"       ,	   0x1070102c86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP23_IP2_PKT"       ,	   0x1070102e86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP24_IP2_PKT"       ,	   0x1070103086000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP25_IP2_PKT"       ,	   0x1070103286000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP26_IP2_PKT"       ,	   0x1070103486000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP27_IP2_PKT"       ,	   0x1070103686000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP28_IP2_PKT"       ,	   0x1070103886000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP29_IP2_PKT"       ,	   0x1070103a86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP30_IP2_PKT"       ,	   0x1070103c86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP31_IP2_PKT"       ,	   0x1070103e86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP0_IP2_RML"        ,	   0x1070100082000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP1_IP2_RML"        ,	   0x1070100282000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP2_IP2_RML"        ,	   0x1070100482000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP3_IP2_RML"        ,	   0x1070100682000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP4_IP2_RML"        ,	   0x1070100882000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP5_IP2_RML"        ,	   0x1070100a82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP6_IP2_RML"        ,	   0x1070100c82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP7_IP2_RML"        ,	   0x1070100e82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP8_IP2_RML"        ,	   0x1070101082000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP9_IP2_RML"        ,	   0x1070101282000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP10_IP2_RML"       ,	   0x1070101482000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP11_IP2_RML"       ,	   0x1070101682000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP12_IP2_RML"       ,	   0x1070101882000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP13_IP2_RML"       ,	   0x1070101a82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP14_IP2_RML"       ,	   0x1070101c82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP15_IP2_RML"       ,	   0x1070101e82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP16_IP2_RML"       ,	   0x1070102082000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP17_IP2_RML"       ,	   0x1070102282000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP18_IP2_RML"       ,	   0x1070102482000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP19_IP2_RML"       ,	   0x1070102682000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP20_IP2_RML"       ,	   0x1070102882000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP21_IP2_RML"       ,	   0x1070102a82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP22_IP2_RML"       ,	   0x1070102c82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP23_IP2_RML"       ,	   0x1070102e82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP24_IP2_RML"       ,	   0x1070103082000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP25_IP2_RML"       ,	   0x1070103282000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP26_IP2_RML"       ,	   0x1070103482000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP27_IP2_RML"       ,	   0x1070103682000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP28_IP2_RML"       ,	   0x1070103882000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP29_IP2_RML"       ,	   0x1070103a82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP30_IP2_RML"       ,	   0x1070103c82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP31_IP2_RML"       ,	   0x1070103e82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP0_IP2_WDOG"       ,	   0x1070100081000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP1_IP2_WDOG"       ,	   0x1070100281000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP2_IP2_WDOG"       ,	   0x1070100481000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP3_IP2_WDOG"       ,	   0x1070100681000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP4_IP2_WDOG"       ,	   0x1070100881000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP5_IP2_WDOG"       ,	   0x1070100a81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP6_IP2_WDOG"       ,	   0x1070100c81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP7_IP2_WDOG"       ,	   0x1070100e81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP8_IP2_WDOG"       ,	   0x1070101081000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP9_IP2_WDOG"       ,	   0x1070101281000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP10_IP2_WDOG"      ,	   0x1070101481000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP11_IP2_WDOG"      ,	   0x1070101681000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP12_IP2_WDOG"      ,	   0x1070101881000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP13_IP2_WDOG"      ,	   0x1070101a81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP14_IP2_WDOG"      ,	   0x1070101c81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP15_IP2_WDOG"      ,	   0x1070101e81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP16_IP2_WDOG"      ,	   0x1070102081000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP17_IP2_WDOG"      ,	   0x1070102281000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP18_IP2_WDOG"      ,	   0x1070102481000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP19_IP2_WDOG"      ,	   0x1070102681000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP20_IP2_WDOG"      ,	   0x1070102881000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP21_IP2_WDOG"      ,	   0x1070102a81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP22_IP2_WDOG"      ,	   0x1070102c81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP23_IP2_WDOG"      ,	   0x1070102e81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP24_IP2_WDOG"      ,	   0x1070103081000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP25_IP2_WDOG"      ,	   0x1070103281000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP26_IP2_WDOG"      ,	   0x1070103481000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP27_IP2_WDOG"      ,	   0x1070103681000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP28_IP2_WDOG"      ,	   0x1070103881000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP29_IP2_WDOG"      ,	   0x1070103a81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP30_IP2_WDOG"      ,	   0x1070103c81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP31_IP2_WDOG"      ,	   0x1070103e81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP0_IP2_WRKQ"       ,	   0x1070100080000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP1_IP2_WRKQ"       ,	   0x1070100280000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP2_IP2_WRKQ"       ,	   0x1070100480000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP3_IP2_WRKQ"       ,	   0x1070100680000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP4_IP2_WRKQ"       ,	   0x1070100880000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP5_IP2_WRKQ"       ,	   0x1070100a80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP6_IP2_WRKQ"       ,	   0x1070100c80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP7_IP2_WRKQ"       ,	   0x1070100e80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP8_IP2_WRKQ"       ,	   0x1070101080000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP9_IP2_WRKQ"       ,	   0x1070101280000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP10_IP2_WRKQ"      ,	   0x1070101480000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP11_IP2_WRKQ"      ,	   0x1070101680000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP12_IP2_WRKQ"      ,	   0x1070101880000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP13_IP2_WRKQ"      ,	   0x1070101a80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP14_IP2_WRKQ"      ,	   0x1070101c80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP15_IP2_WRKQ"      ,	   0x1070101e80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP16_IP2_WRKQ"      ,	   0x1070102080000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP17_IP2_WRKQ"      ,	   0x1070102280000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP18_IP2_WRKQ"      ,	   0x1070102480000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP19_IP2_WRKQ"      ,	   0x1070102680000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP20_IP2_WRKQ"      ,	   0x1070102880000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP21_IP2_WRKQ"      ,	   0x1070102a80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP22_IP2_WRKQ"      ,	   0x1070102c80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP23_IP2_WRKQ"      ,	   0x1070102e80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP24_IP2_WRKQ"      ,	   0x1070103080000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP25_IP2_WRKQ"      ,	   0x1070103280000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP26_IP2_WRKQ"      ,	   0x1070103480000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP27_IP2_WRKQ"      ,	   0x1070103680000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP28_IP2_WRKQ"      ,	   0x1070103880000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP29_IP2_WRKQ"      ,	   0x1070103a80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP30_IP2_WRKQ"      ,	   0x1070103c80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP31_IP2_WRKQ"      ,	   0x1070103e80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP0_IP3_GPIO"       ,	   0x1070100087200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP1_IP3_GPIO"       ,	   0x1070100287200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP2_IP3_GPIO"       ,	   0x1070100487200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP3_IP3_GPIO"       ,	   0x1070100687200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP4_IP3_GPIO"       ,	   0x1070100887200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP5_IP3_GPIO"       ,	   0x1070100a87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP6_IP3_GPIO"       ,	   0x1070100c87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP7_IP3_GPIO"       ,	   0x1070100e87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP8_IP3_GPIO"       ,	   0x1070101087200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP9_IP3_GPIO"       ,	   0x1070101287200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP10_IP3_GPIO"      ,	   0x1070101487200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP11_IP3_GPIO"      ,	   0x1070101687200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP12_IP3_GPIO"      ,	   0x1070101887200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP13_IP3_GPIO"      ,	   0x1070101a87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP14_IP3_GPIO"      ,	   0x1070101c87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP15_IP3_GPIO"      ,	   0x1070101e87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP16_IP3_GPIO"      ,	   0x1070102087200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP17_IP3_GPIO"      ,	   0x1070102287200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP18_IP3_GPIO"      ,	   0x1070102487200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP19_IP3_GPIO"      ,	   0x1070102687200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP20_IP3_GPIO"      ,	   0x1070102887200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP21_IP3_GPIO"      ,	   0x1070102a87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP22_IP3_GPIO"      ,	   0x1070102c87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP23_IP3_GPIO"      ,	   0x1070102e87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP24_IP3_GPIO"      ,	   0x1070103087200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP25_IP3_GPIO"      ,	   0x1070103287200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP26_IP3_GPIO"      ,	   0x1070103487200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP27_IP3_GPIO"      ,	   0x1070103687200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP28_IP3_GPIO"      ,	   0x1070103887200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP29_IP3_GPIO"      ,	   0x1070103a87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP30_IP3_GPIO"      ,	   0x1070103c87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP31_IP3_GPIO"      ,	   0x1070103e87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP0_IP3_IO"         ,	   0x1070100084200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP1_IP3_IO"         ,	   0x1070100284200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP2_IP3_IO"         ,	   0x1070100484200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP3_IP3_IO"         ,	   0x1070100684200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP4_IP3_IO"         ,	   0x1070100884200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP5_IP3_IO"         ,	   0x1070100a84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP6_IP3_IO"         ,	   0x1070100c84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP7_IP3_IO"         ,	   0x1070100e84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP8_IP3_IO"         ,	   0x1070101084200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP9_IP3_IO"         ,	   0x1070101284200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP10_IP3_IO"        ,	   0x1070101484200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP11_IP3_IO"        ,	   0x1070101684200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP12_IP3_IO"        ,	   0x1070101884200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP13_IP3_IO"        ,	   0x1070101a84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP14_IP3_IO"        ,	   0x1070101c84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP15_IP3_IO"        ,	   0x1070101e84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP16_IP3_IO"        ,	   0x1070102084200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP17_IP3_IO"        ,	   0x1070102284200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP18_IP3_IO"        ,	   0x1070102484200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP19_IP3_IO"        ,	   0x1070102684200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP20_IP3_IO"        ,	   0x1070102884200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP21_IP3_IO"        ,	   0x1070102a84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP22_IP3_IO"        ,	   0x1070102c84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP23_IP3_IO"        ,	   0x1070102e84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP24_IP3_IO"        ,	   0x1070103084200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP25_IP3_IO"        ,	   0x1070103284200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP26_IP3_IO"        ,	   0x1070103484200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP27_IP3_IO"        ,	   0x1070103684200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP28_IP3_IO"        ,	   0x1070103884200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP29_IP3_IO"        ,	   0x1070103a84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP30_IP3_IO"        ,	   0x1070103c84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP31_IP3_IO"        ,	   0x1070103e84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP0_IP3_MBOX"       ,	   0x1070100088200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP1_IP3_MBOX"       ,	   0x1070100288200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP2_IP3_MBOX"       ,	   0x1070100488200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP3_IP3_MBOX"       ,	   0x1070100688200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP4_IP3_MBOX"       ,	   0x1070100888200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP5_IP3_MBOX"       ,	   0x1070100a88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP6_IP3_MBOX"       ,	   0x1070100c88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP7_IP3_MBOX"       ,	   0x1070100e88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP8_IP3_MBOX"       ,	   0x1070101088200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP9_IP3_MBOX"       ,	   0x1070101288200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP10_IP3_MBOX"      ,	   0x1070101488200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP11_IP3_MBOX"      ,	   0x1070101688200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP12_IP3_MBOX"      ,	   0x1070101888200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP13_IP3_MBOX"      ,	   0x1070101a88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP14_IP3_MBOX"      ,	   0x1070101c88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP15_IP3_MBOX"      ,	   0x1070101e88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP16_IP3_MBOX"      ,	   0x1070102088200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP17_IP3_MBOX"      ,	   0x1070102288200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP18_IP3_MBOX"      ,	   0x1070102488200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP19_IP3_MBOX"      ,	   0x1070102688200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP20_IP3_MBOX"      ,	   0x1070102888200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP21_IP3_MBOX"      ,	   0x1070102a88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP22_IP3_MBOX"      ,	   0x1070102c88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP23_IP3_MBOX"      ,	   0x1070102e88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP24_IP3_MBOX"      ,	   0x1070103088200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP25_IP3_MBOX"      ,	   0x1070103288200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP26_IP3_MBOX"      ,	   0x1070103488200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP27_IP3_MBOX"      ,	   0x1070103688200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP28_IP3_MBOX"      ,	   0x1070103888200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP29_IP3_MBOX"      ,	   0x1070103a88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP30_IP3_MBOX"      ,	   0x1070103c88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP31_IP3_MBOX"      ,	   0x1070103e88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP0_IP3_MEM"        ,	   0x1070100085200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP1_IP3_MEM"        ,	   0x1070100285200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP2_IP3_MEM"        ,	   0x1070100485200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP3_IP3_MEM"        ,	   0x1070100685200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP4_IP3_MEM"        ,	   0x1070100885200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP5_IP3_MEM"        ,	   0x1070100a85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP6_IP3_MEM"        ,	   0x1070100c85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP7_IP3_MEM"        ,	   0x1070100e85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP8_IP3_MEM"        ,	   0x1070101085200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP9_IP3_MEM"        ,	   0x1070101285200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP10_IP3_MEM"       ,	   0x1070101485200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP11_IP3_MEM"       ,	   0x1070101685200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP12_IP3_MEM"       ,	   0x1070101885200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP13_IP3_MEM"       ,	   0x1070101a85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP14_IP3_MEM"       ,	   0x1070101c85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP15_IP3_MEM"       ,	   0x1070101e85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP16_IP3_MEM"       ,	   0x1070102085200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP17_IP3_MEM"       ,	   0x1070102285200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP18_IP3_MEM"       ,	   0x1070102485200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP19_IP3_MEM"       ,	   0x1070102685200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP20_IP3_MEM"       ,	   0x1070102885200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP21_IP3_MEM"       ,	   0x1070102a85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP22_IP3_MEM"       ,	   0x1070102c85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP23_IP3_MEM"       ,	   0x1070102e85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP24_IP3_MEM"       ,	   0x1070103085200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP25_IP3_MEM"       ,	   0x1070103285200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP26_IP3_MEM"       ,	   0x1070103485200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP27_IP3_MEM"       ,	   0x1070103685200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP28_IP3_MEM"       ,	   0x1070103885200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP29_IP3_MEM"       ,	   0x1070103a85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP30_IP3_MEM"       ,	   0x1070103c85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP31_IP3_MEM"       ,	   0x1070103e85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP0_IP3_MIO"        ,	   0x1070100083200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP1_IP3_MIO"        ,	   0x1070100283200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP2_IP3_MIO"        ,	   0x1070100483200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP3_IP3_MIO"        ,	   0x1070100683200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP4_IP3_MIO"        ,	   0x1070100883200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP5_IP3_MIO"        ,	   0x1070100a83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP6_IP3_MIO"        ,	   0x1070100c83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP7_IP3_MIO"        ,	   0x1070100e83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP8_IP3_MIO"        ,	   0x1070101083200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP9_IP3_MIO"        ,	   0x1070101283200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP10_IP3_MIO"       ,	   0x1070101483200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP11_IP3_MIO"       ,	   0x1070101683200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP12_IP3_MIO"       ,	   0x1070101883200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP13_IP3_MIO"       ,	   0x1070101a83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP14_IP3_MIO"       ,	   0x1070101c83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP15_IP3_MIO"       ,	   0x1070101e83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP16_IP3_MIO"       ,	   0x1070102083200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP17_IP3_MIO"       ,	   0x1070102283200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP18_IP3_MIO"       ,	   0x1070102483200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP19_IP3_MIO"       ,	   0x1070102683200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP20_IP3_MIO"       ,	   0x1070102883200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP21_IP3_MIO"       ,	   0x1070102a83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP22_IP3_MIO"       ,	   0x1070102c83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP23_IP3_MIO"       ,	   0x1070102e83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP24_IP3_MIO"       ,	   0x1070103083200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP25_IP3_MIO"       ,	   0x1070103283200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP26_IP3_MIO"       ,	   0x1070103483200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP27_IP3_MIO"       ,	   0x1070103683200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP28_IP3_MIO"       ,	   0x1070103883200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP29_IP3_MIO"       ,	   0x1070103a83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP30_IP3_MIO"       ,	   0x1070103c83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP31_IP3_MIO"       ,	   0x1070103e83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP0_IP3_PKT"        ,	   0x1070100086200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP1_IP3_PKT"        ,	   0x1070100286200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP2_IP3_PKT"        ,	   0x1070100486200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP3_IP3_PKT"        ,	   0x1070100686200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP4_IP3_PKT"        ,	   0x1070100886200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP5_IP3_PKT"        ,	   0x1070100a86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP6_IP3_PKT"        ,	   0x1070100c86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP7_IP3_PKT"        ,	   0x1070100e86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP8_IP3_PKT"        ,	   0x1070101086200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP9_IP3_PKT"        ,	   0x1070101286200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP10_IP3_PKT"       ,	   0x1070101486200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP11_IP3_PKT"       ,	   0x1070101686200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP12_IP3_PKT"       ,	   0x1070101886200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP13_IP3_PKT"       ,	   0x1070101a86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP14_IP3_PKT"       ,	   0x1070101c86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP15_IP3_PKT"       ,	   0x1070101e86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP16_IP3_PKT"       ,	   0x1070102086200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP17_IP3_PKT"       ,	   0x1070102286200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP18_IP3_PKT"       ,	   0x1070102486200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP19_IP3_PKT"       ,	   0x1070102686200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP20_IP3_PKT"       ,	   0x1070102886200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP21_IP3_PKT"       ,	   0x1070102a86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP22_IP3_PKT"       ,	   0x1070102c86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP23_IP3_PKT"       ,	   0x1070102e86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP24_IP3_PKT"       ,	   0x1070103086200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP25_IP3_PKT"       ,	   0x1070103286200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP26_IP3_PKT"       ,	   0x1070103486200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP27_IP3_PKT"       ,	   0x1070103686200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP28_IP3_PKT"       ,	   0x1070103886200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP29_IP3_PKT"       ,	   0x1070103a86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP30_IP3_PKT"       ,	   0x1070103c86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP31_IP3_PKT"       ,	   0x1070103e86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP0_IP3_RML"        ,	   0x1070100082200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP1_IP3_RML"        ,	   0x1070100282200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP2_IP3_RML"        ,	   0x1070100482200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP3_IP3_RML"        ,	   0x1070100682200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP4_IP3_RML"        ,	   0x1070100882200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP5_IP3_RML"        ,	   0x1070100a82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP6_IP3_RML"        ,	   0x1070100c82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP7_IP3_RML"        ,	   0x1070100e82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP8_IP3_RML"        ,	   0x1070101082200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP9_IP3_RML"        ,	   0x1070101282200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP10_IP3_RML"       ,	   0x1070101482200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP11_IP3_RML"       ,	   0x1070101682200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP12_IP3_RML"       ,	   0x1070101882200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP13_IP3_RML"       ,	   0x1070101a82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP14_IP3_RML"       ,	   0x1070101c82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP15_IP3_RML"       ,	   0x1070101e82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP16_IP3_RML"       ,	   0x1070102082200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP17_IP3_RML"       ,	   0x1070102282200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP18_IP3_RML"       ,	   0x1070102482200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP19_IP3_RML"       ,	   0x1070102682200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP20_IP3_RML"       ,	   0x1070102882200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP21_IP3_RML"       ,	   0x1070102a82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP22_IP3_RML"       ,	   0x1070102c82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP23_IP3_RML"       ,	   0x1070102e82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP24_IP3_RML"       ,	   0x1070103082200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP25_IP3_RML"       ,	   0x1070103282200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP26_IP3_RML"       ,	   0x1070103482200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP27_IP3_RML"       ,	   0x1070103682200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP28_IP3_RML"       ,	   0x1070103882200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP29_IP3_RML"       ,	   0x1070103a82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP30_IP3_RML"       ,	   0x1070103c82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP31_IP3_RML"       ,	   0x1070103e82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP0_IP3_WDOG"       ,	   0x1070100081200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP1_IP3_WDOG"       ,	   0x1070100281200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP2_IP3_WDOG"       ,	   0x1070100481200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP3_IP3_WDOG"       ,	   0x1070100681200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP4_IP3_WDOG"       ,	   0x1070100881200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP5_IP3_WDOG"       ,	   0x1070100a81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP6_IP3_WDOG"       ,	   0x1070100c81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP7_IP3_WDOG"       ,	   0x1070100e81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP8_IP3_WDOG"       ,	   0x1070101081200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP9_IP3_WDOG"       ,	   0x1070101281200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP10_IP3_WDOG"      ,	   0x1070101481200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP11_IP3_WDOG"      ,	   0x1070101681200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP12_IP3_WDOG"      ,	   0x1070101881200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP13_IP3_WDOG"      ,	   0x1070101a81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP14_IP3_WDOG"      ,	   0x1070101c81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP15_IP3_WDOG"      ,	   0x1070101e81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP16_IP3_WDOG"      ,	   0x1070102081200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP17_IP3_WDOG"      ,	   0x1070102281200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP18_IP3_WDOG"      ,	   0x1070102481200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP19_IP3_WDOG"      ,	   0x1070102681200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP20_IP3_WDOG"      ,	   0x1070102881200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP21_IP3_WDOG"      ,	   0x1070102a81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP22_IP3_WDOG"      ,	   0x1070102c81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP23_IP3_WDOG"      ,	   0x1070102e81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP24_IP3_WDOG"      ,	   0x1070103081200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP25_IP3_WDOG"      ,	   0x1070103281200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP26_IP3_WDOG"      ,	   0x1070103481200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP27_IP3_WDOG"      ,	   0x1070103681200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP28_IP3_WDOG"      ,	   0x1070103881200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP29_IP3_WDOG"      ,	   0x1070103a81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP30_IP3_WDOG"      ,	   0x1070103c81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP31_IP3_WDOG"      ,	   0x1070103e81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP0_IP3_WRKQ"       ,	   0x1070100080200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP1_IP3_WRKQ"       ,	   0x1070100280200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP2_IP3_WRKQ"       ,	   0x1070100480200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP3_IP3_WRKQ"       ,	   0x1070100680200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP4_IP3_WRKQ"       ,	   0x1070100880200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP5_IP3_WRKQ"       ,	   0x1070100a80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP6_IP3_WRKQ"       ,	   0x1070100c80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP7_IP3_WRKQ"       ,	   0x1070100e80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP8_IP3_WRKQ"       ,	   0x1070101080200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP9_IP3_WRKQ"       ,	   0x1070101280200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP10_IP3_WRKQ"      ,	   0x1070101480200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP11_IP3_WRKQ"      ,	   0x1070101680200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP12_IP3_WRKQ"      ,	   0x1070101880200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP13_IP3_WRKQ"      ,	   0x1070101a80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP14_IP3_WRKQ"      ,	   0x1070101c80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP15_IP3_WRKQ"      ,	   0x1070101e80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP16_IP3_WRKQ"      ,	   0x1070102080200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP17_IP3_WRKQ"      ,	   0x1070102280200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP18_IP3_WRKQ"      ,	   0x1070102480200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP19_IP3_WRKQ"      ,	   0x1070102680200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP20_IP3_WRKQ"      ,	   0x1070102880200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP21_IP3_WRKQ"      ,	   0x1070102a80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP22_IP3_WRKQ"      ,	   0x1070102c80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP23_IP3_WRKQ"      ,	   0x1070102e80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP24_IP3_WRKQ"      ,	   0x1070103080200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP25_IP3_WRKQ"      ,	   0x1070103280200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP26_IP3_WRKQ"      ,	   0x1070103480200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP27_IP3_WRKQ"      ,	   0x1070103680200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP28_IP3_WRKQ"      ,	   0x1070103880200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP29_IP3_WRKQ"      ,	   0x1070103a80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP30_IP3_WRKQ"      ,	   0x1070103c80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP31_IP3_WRKQ"      ,	   0x1070103e80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP0_IP4_GPIO"       ,	   0x1070100087400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP1_IP4_GPIO"       ,	   0x1070100287400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP2_IP4_GPIO"       ,	   0x1070100487400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP3_IP4_GPIO"       ,	   0x1070100687400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP4_IP4_GPIO"       ,	   0x1070100887400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP5_IP4_GPIO"       ,	   0x1070100a87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP6_IP4_GPIO"       ,	   0x1070100c87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP7_IP4_GPIO"       ,	   0x1070100e87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP8_IP4_GPIO"       ,	   0x1070101087400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP9_IP4_GPIO"       ,	   0x1070101287400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP10_IP4_GPIO"      ,	   0x1070101487400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP11_IP4_GPIO"      ,	   0x1070101687400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP12_IP4_GPIO"      ,	   0x1070101887400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP13_IP4_GPIO"      ,	   0x1070101a87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP14_IP4_GPIO"      ,	   0x1070101c87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP15_IP4_GPIO"      ,	   0x1070101e87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP16_IP4_GPIO"      ,	   0x1070102087400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP17_IP4_GPIO"      ,	   0x1070102287400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP18_IP4_GPIO"      ,	   0x1070102487400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP19_IP4_GPIO"      ,	   0x1070102687400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP20_IP4_GPIO"      ,	   0x1070102887400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP21_IP4_GPIO"      ,	   0x1070102a87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP22_IP4_GPIO"      ,	   0x1070102c87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP23_IP4_GPIO"      ,	   0x1070102e87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP24_IP4_GPIO"      ,	   0x1070103087400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP25_IP4_GPIO"      ,	   0x1070103287400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP26_IP4_GPIO"      ,	   0x1070103487400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP27_IP4_GPIO"      ,	   0x1070103687400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP28_IP4_GPIO"      ,	   0x1070103887400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP29_IP4_GPIO"      ,	   0x1070103a87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP30_IP4_GPIO"      ,	   0x1070103c87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP31_IP4_GPIO"      ,	   0x1070103e87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP0_IP4_IO"         ,	   0x1070100084400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP1_IP4_IO"         ,	   0x1070100284400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP2_IP4_IO"         ,	   0x1070100484400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP3_IP4_IO"         ,	   0x1070100684400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP4_IP4_IO"         ,	   0x1070100884400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP5_IP4_IO"         ,	   0x1070100a84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP6_IP4_IO"         ,	   0x1070100c84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP7_IP4_IO"         ,	   0x1070100e84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP8_IP4_IO"         ,	   0x1070101084400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP9_IP4_IO"         ,	   0x1070101284400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP10_IP4_IO"        ,	   0x1070101484400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP11_IP4_IO"        ,	   0x1070101684400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP12_IP4_IO"        ,	   0x1070101884400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP13_IP4_IO"        ,	   0x1070101a84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP14_IP4_IO"        ,	   0x1070101c84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP15_IP4_IO"        ,	   0x1070101e84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP16_IP4_IO"        ,	   0x1070102084400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP17_IP4_IO"        ,	   0x1070102284400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP18_IP4_IO"        ,	   0x1070102484400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP19_IP4_IO"        ,	   0x1070102684400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP20_IP4_IO"        ,	   0x1070102884400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP21_IP4_IO"        ,	   0x1070102a84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP22_IP4_IO"        ,	   0x1070102c84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP23_IP4_IO"        ,	   0x1070102e84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP24_IP4_IO"        ,	   0x1070103084400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP25_IP4_IO"        ,	   0x1070103284400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP26_IP4_IO"        ,	   0x1070103484400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP27_IP4_IO"        ,	   0x1070103684400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP28_IP4_IO"        ,	   0x1070103884400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP29_IP4_IO"        ,	   0x1070103a84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP30_IP4_IO"        ,	   0x1070103c84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP31_IP4_IO"        ,	   0x1070103e84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP0_IP4_MBOX"       ,	   0x1070100088400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP1_IP4_MBOX"       ,	   0x1070100288400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP2_IP4_MBOX"       ,	   0x1070100488400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP3_IP4_MBOX"       ,	   0x1070100688400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP4_IP4_MBOX"       ,	   0x1070100888400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP5_IP4_MBOX"       ,	   0x1070100a88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP6_IP4_MBOX"       ,	   0x1070100c88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP7_IP4_MBOX"       ,	   0x1070100e88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP8_IP4_MBOX"       ,	   0x1070101088400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP9_IP4_MBOX"       ,	   0x1070101288400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP10_IP4_MBOX"      ,	   0x1070101488400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP11_IP4_MBOX"      ,	   0x1070101688400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP12_IP4_MBOX"      ,	   0x1070101888400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP13_IP4_MBOX"      ,	   0x1070101a88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP14_IP4_MBOX"      ,	   0x1070101c88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP15_IP4_MBOX"      ,	   0x1070101e88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP16_IP4_MBOX"      ,	   0x1070102088400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP17_IP4_MBOX"      ,	   0x1070102288400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP18_IP4_MBOX"      ,	   0x1070102488400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP19_IP4_MBOX"      ,	   0x1070102688400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP20_IP4_MBOX"      ,	   0x1070102888400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP21_IP4_MBOX"      ,	   0x1070102a88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP22_IP4_MBOX"      ,	   0x1070102c88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP23_IP4_MBOX"      ,	   0x1070102e88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP24_IP4_MBOX"      ,	   0x1070103088400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP25_IP4_MBOX"      ,	   0x1070103288400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP26_IP4_MBOX"      ,	   0x1070103488400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP27_IP4_MBOX"      ,	   0x1070103688400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP28_IP4_MBOX"      ,	   0x1070103888400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP29_IP4_MBOX"      ,	   0x1070103a88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP30_IP4_MBOX"      ,	   0x1070103c88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP31_IP4_MBOX"      ,	   0x1070103e88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP0_IP4_MEM"        ,	   0x1070100085400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP1_IP4_MEM"        ,	   0x1070100285400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP2_IP4_MEM"        ,	   0x1070100485400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP3_IP4_MEM"        ,	   0x1070100685400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP4_IP4_MEM"        ,	   0x1070100885400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP5_IP4_MEM"        ,	   0x1070100a85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP6_IP4_MEM"        ,	   0x1070100c85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP7_IP4_MEM"        ,	   0x1070100e85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP8_IP4_MEM"        ,	   0x1070101085400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP9_IP4_MEM"        ,	   0x1070101285400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP10_IP4_MEM"       ,	   0x1070101485400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP11_IP4_MEM"       ,	   0x1070101685400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP12_IP4_MEM"       ,	   0x1070101885400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP13_IP4_MEM"       ,	   0x1070101a85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP14_IP4_MEM"       ,	   0x1070101c85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP15_IP4_MEM"       ,	   0x1070101e85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP16_IP4_MEM"       ,	   0x1070102085400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP17_IP4_MEM"       ,	   0x1070102285400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP18_IP4_MEM"       ,	   0x1070102485400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP19_IP4_MEM"       ,	   0x1070102685400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP20_IP4_MEM"       ,	   0x1070102885400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP21_IP4_MEM"       ,	   0x1070102a85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP22_IP4_MEM"       ,	   0x1070102c85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP23_IP4_MEM"       ,	   0x1070102e85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP24_IP4_MEM"       ,	   0x1070103085400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP25_IP4_MEM"       ,	   0x1070103285400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP26_IP4_MEM"       ,	   0x1070103485400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP27_IP4_MEM"       ,	   0x1070103685400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP28_IP4_MEM"       ,	   0x1070103885400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP29_IP4_MEM"       ,	   0x1070103a85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP30_IP4_MEM"       ,	   0x1070103c85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP31_IP4_MEM"       ,	   0x1070103e85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP0_IP4_MIO"        ,	   0x1070100083400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP1_IP4_MIO"        ,	   0x1070100283400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP2_IP4_MIO"        ,	   0x1070100483400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP3_IP4_MIO"        ,	   0x1070100683400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP4_IP4_MIO"        ,	   0x1070100883400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP5_IP4_MIO"        ,	   0x1070100a83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP6_IP4_MIO"        ,	   0x1070100c83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP7_IP4_MIO"        ,	   0x1070100e83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP8_IP4_MIO"        ,	   0x1070101083400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP9_IP4_MIO"        ,	   0x1070101283400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP10_IP4_MIO"       ,	   0x1070101483400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP11_IP4_MIO"       ,	   0x1070101683400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP12_IP4_MIO"       ,	   0x1070101883400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP13_IP4_MIO"       ,	   0x1070101a83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP14_IP4_MIO"       ,	   0x1070101c83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP15_IP4_MIO"       ,	   0x1070101e83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP16_IP4_MIO"       ,	   0x1070102083400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP17_IP4_MIO"       ,	   0x1070102283400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP18_IP4_MIO"       ,	   0x1070102483400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP19_IP4_MIO"       ,	   0x1070102683400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP20_IP4_MIO"       ,	   0x1070102883400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP21_IP4_MIO"       ,	   0x1070102a83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP22_IP4_MIO"       ,	   0x1070102c83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP23_IP4_MIO"       ,	   0x1070102e83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP24_IP4_MIO"       ,	   0x1070103083400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP25_IP4_MIO"       ,	   0x1070103283400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP26_IP4_MIO"       ,	   0x1070103483400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP27_IP4_MIO"       ,	   0x1070103683400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP28_IP4_MIO"       ,	   0x1070103883400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP29_IP4_MIO"       ,	   0x1070103a83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP30_IP4_MIO"       ,	   0x1070103c83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP31_IP4_MIO"       ,	   0x1070103e83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP0_IP4_PKT"        ,	   0x1070100086400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP1_IP4_PKT"        ,	   0x1070100286400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP2_IP4_PKT"        ,	   0x1070100486400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP3_IP4_PKT"        ,	   0x1070100686400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP4_IP4_PKT"        ,	   0x1070100886400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP5_IP4_PKT"        ,	   0x1070100a86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP6_IP4_PKT"        ,	   0x1070100c86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP7_IP4_PKT"        ,	   0x1070100e86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP8_IP4_PKT"        ,	   0x1070101086400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP9_IP4_PKT"        ,	   0x1070101286400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP10_IP4_PKT"       ,	   0x1070101486400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP11_IP4_PKT"       ,	   0x1070101686400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP12_IP4_PKT"       ,	   0x1070101886400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP13_IP4_PKT"       ,	   0x1070101a86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP14_IP4_PKT"       ,	   0x1070101c86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP15_IP4_PKT"       ,	   0x1070101e86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP16_IP4_PKT"       ,	   0x1070102086400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP17_IP4_PKT"       ,	   0x1070102286400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP18_IP4_PKT"       ,	   0x1070102486400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP19_IP4_PKT"       ,	   0x1070102686400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP20_IP4_PKT"       ,	   0x1070102886400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP21_IP4_PKT"       ,	   0x1070102a86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP22_IP4_PKT"       ,	   0x1070102c86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP23_IP4_PKT"       ,	   0x1070102e86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP24_IP4_PKT"       ,	   0x1070103086400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP25_IP4_PKT"       ,	   0x1070103286400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP26_IP4_PKT"       ,	   0x1070103486400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP27_IP4_PKT"       ,	   0x1070103686400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP28_IP4_PKT"       ,	   0x1070103886400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP29_IP4_PKT"       ,	   0x1070103a86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP30_IP4_PKT"       ,	   0x1070103c86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP31_IP4_PKT"       ,	   0x1070103e86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP0_IP4_RML"        ,	   0x1070100082400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP1_IP4_RML"        ,	   0x1070100282400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP2_IP4_RML"        ,	   0x1070100482400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP3_IP4_RML"        ,	   0x1070100682400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP4_IP4_RML"        ,	   0x1070100882400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP5_IP4_RML"        ,	   0x1070100a82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP6_IP4_RML"        ,	   0x1070100c82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP7_IP4_RML"        ,	   0x1070100e82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP8_IP4_RML"        ,	   0x1070101082400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP9_IP4_RML"        ,	   0x1070101282400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP10_IP4_RML"       ,	   0x1070101482400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP11_IP4_RML"       ,	   0x1070101682400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP12_IP4_RML"       ,	   0x1070101882400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP13_IP4_RML"       ,	   0x1070101a82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP14_IP4_RML"       ,	   0x1070101c82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP15_IP4_RML"       ,	   0x1070101e82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP16_IP4_RML"       ,	   0x1070102082400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP17_IP4_RML"       ,	   0x1070102282400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP18_IP4_RML"       ,	   0x1070102482400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP19_IP4_RML"       ,	   0x1070102682400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP20_IP4_RML"       ,	   0x1070102882400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP21_IP4_RML"       ,	   0x1070102a82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP22_IP4_RML"       ,	   0x1070102c82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP23_IP4_RML"       ,	   0x1070102e82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP24_IP4_RML"       ,	   0x1070103082400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP25_IP4_RML"       ,	   0x1070103282400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP26_IP4_RML"       ,	   0x1070103482400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP27_IP4_RML"       ,	   0x1070103682400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP28_IP4_RML"       ,	   0x1070103882400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP29_IP4_RML"       ,	   0x1070103a82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP30_IP4_RML"       ,	   0x1070103c82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP31_IP4_RML"       ,	   0x1070103e82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP0_IP4_WDOG"       ,	   0x1070100081400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP1_IP4_WDOG"       ,	   0x1070100281400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP2_IP4_WDOG"       ,	   0x1070100481400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP3_IP4_WDOG"       ,	   0x1070100681400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP4_IP4_WDOG"       ,	   0x1070100881400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP5_IP4_WDOG"       ,	   0x1070100a81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP6_IP4_WDOG"       ,	   0x1070100c81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP7_IP4_WDOG"       ,	   0x1070100e81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP8_IP4_WDOG"       ,	   0x1070101081400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP9_IP4_WDOG"       ,	   0x1070101281400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP10_IP4_WDOG"      ,	   0x1070101481400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP11_IP4_WDOG"      ,	   0x1070101681400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP12_IP4_WDOG"      ,	   0x1070101881400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP13_IP4_WDOG"      ,	   0x1070101a81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP14_IP4_WDOG"      ,	   0x1070101c81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP15_IP4_WDOG"      ,	   0x1070101e81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP16_IP4_WDOG"      ,	   0x1070102081400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP17_IP4_WDOG"      ,	   0x1070102281400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP18_IP4_WDOG"      ,	   0x1070102481400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP19_IP4_WDOG"      ,	   0x1070102681400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP20_IP4_WDOG"      ,	   0x1070102881400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP21_IP4_WDOG"      ,	   0x1070102a81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP22_IP4_WDOG"      ,	   0x1070102c81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP23_IP4_WDOG"      ,	   0x1070102e81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP24_IP4_WDOG"      ,	   0x1070103081400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP25_IP4_WDOG"      ,	   0x1070103281400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP26_IP4_WDOG"      ,	   0x1070103481400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP27_IP4_WDOG"      ,	   0x1070103681400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP28_IP4_WDOG"      ,	   0x1070103881400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP29_IP4_WDOG"      ,	   0x1070103a81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP30_IP4_WDOG"      ,	   0x1070103c81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP31_IP4_WDOG"      ,	   0x1070103e81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP0_IP4_WRKQ"       ,	   0x1070100080400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP1_IP4_WRKQ"       ,	   0x1070100280400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP2_IP4_WRKQ"       ,	   0x1070100480400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP3_IP4_WRKQ"       ,	   0x1070100680400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP4_IP4_WRKQ"       ,	   0x1070100880400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP5_IP4_WRKQ"       ,	   0x1070100a80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP6_IP4_WRKQ"       ,	   0x1070100c80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP7_IP4_WRKQ"       ,	   0x1070100e80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP8_IP4_WRKQ"       ,	   0x1070101080400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP9_IP4_WRKQ"       ,	   0x1070101280400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP10_IP4_WRKQ"      ,	   0x1070101480400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP11_IP4_WRKQ"      ,	   0x1070101680400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP12_IP4_WRKQ"      ,	   0x1070101880400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP13_IP4_WRKQ"      ,	   0x1070101a80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP14_IP4_WRKQ"      ,	   0x1070101c80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP15_IP4_WRKQ"      ,	   0x1070101e80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP16_IP4_WRKQ"      ,	   0x1070102080400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP17_IP4_WRKQ"      ,	   0x1070102280400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP18_IP4_WRKQ"      ,	   0x1070102480400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP19_IP4_WRKQ"      ,	   0x1070102680400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP20_IP4_WRKQ"      ,	   0x1070102880400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP21_IP4_WRKQ"      ,	   0x1070102a80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP22_IP4_WRKQ"      ,	   0x1070102c80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP23_IP4_WRKQ"      ,	   0x1070102e80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP24_IP4_WRKQ"      ,	   0x1070103080400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP25_IP4_WRKQ"      ,	   0x1070103280400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP26_IP4_WRKQ"      ,	   0x1070103480400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP27_IP4_WRKQ"      ,	   0x1070103680400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP28_IP4_WRKQ"      ,	   0x1070103880400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP29_IP4_WRKQ"      ,	   0x1070103a80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP30_IP4_WRKQ"      ,	   0x1070103c80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP31_IP4_WRKQ"      ,	   0x1070103e80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SUM_IO0_INT"            ,	   0x1070100000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"CIU2_SUM_IO1_INT"            ,	   0x1070100000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"CIU2_SUM_PP0_IP2"            ,	   0x1070100000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP1_IP2"            ,	   0x1070100000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP2_IP2"            ,	   0x1070100000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP3_IP2"            ,	   0x1070100000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP4_IP2"            ,	   0x1070100000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP5_IP2"            ,	   0x1070100000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP6_IP2"            ,	   0x1070100000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP7_IP2"            ,	   0x1070100000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP8_IP2"            ,	   0x1070100000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP9_IP2"            ,	   0x1070100000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP10_IP2"           ,	   0x1070100000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP11_IP2"           ,	   0x1070100000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP12_IP2"           ,	   0x1070100000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP13_IP2"           ,	   0x1070100000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP14_IP2"           ,	   0x1070100000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP15_IP2"           ,	   0x1070100000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP16_IP2"           ,	   0x1070100000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP17_IP2"           ,	   0x1070100000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP18_IP2"           ,	   0x1070100000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP19_IP2"           ,	   0x1070100000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP20_IP2"           ,	   0x10701000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP21_IP2"           ,	   0x10701000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP22_IP2"           ,	   0x10701000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP23_IP2"           ,	   0x10701000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP24_IP2"           ,	   0x10701000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP25_IP2"           ,	   0x10701000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP26_IP2"           ,	   0x10701000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP27_IP2"           ,	   0x10701000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP28_IP2"           ,	   0x10701000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP29_IP2"           ,	   0x10701000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP30_IP2"           ,	   0x10701000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP31_IP2"           ,	   0x10701000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP0_IP3"            ,	   0x1070100000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP1_IP3"            ,	   0x1070100000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP2_IP3"            ,	   0x1070100000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP3_IP3"            ,	   0x1070100000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP4_IP3"            ,	   0x1070100000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP5_IP3"            ,	   0x1070100000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP6_IP3"            ,	   0x1070100000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP7_IP3"            ,	   0x1070100000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP8_IP3"            ,	   0x1070100000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP9_IP3"            ,	   0x1070100000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP10_IP3"           ,	   0x1070100000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP11_IP3"           ,	   0x1070100000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP12_IP3"           ,	   0x1070100000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP13_IP3"           ,	   0x1070100000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP14_IP3"           ,	   0x1070100000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP15_IP3"           ,	   0x1070100000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP16_IP3"           ,	   0x1070100000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP17_IP3"           ,	   0x1070100000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP18_IP3"           ,	   0x1070100000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP19_IP3"           ,	   0x1070100000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP20_IP3"           ,	   0x10701000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP21_IP3"           ,	   0x10701000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP22_IP3"           ,	   0x10701000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP23_IP3"           ,	   0x10701000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP24_IP3"           ,	   0x10701000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP25_IP3"           ,	   0x10701000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP26_IP3"           ,	   0x10701000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP27_IP3"           ,	   0x10701000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP28_IP3"           ,	   0x10701000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP29_IP3"           ,	   0x10701000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP30_IP3"           ,	   0x10701000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP31_IP3"           ,	   0x10701000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP0_IP4"            ,	   0x1070100000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP1_IP4"            ,	   0x1070100000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP2_IP4"            ,	   0x1070100000410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP3_IP4"            ,	   0x1070100000418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP4_IP4"            ,	   0x1070100000420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP5_IP4"            ,	   0x1070100000428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP6_IP4"            ,	   0x1070100000430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP7_IP4"            ,	   0x1070100000438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP8_IP4"            ,	   0x1070100000440ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP9_IP4"            ,	   0x1070100000448ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP10_IP4"           ,	   0x1070100000450ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP11_IP4"           ,	   0x1070100000458ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP12_IP4"           ,	   0x1070100000460ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP13_IP4"           ,	   0x1070100000468ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP14_IP4"           ,	   0x1070100000470ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP15_IP4"           ,	   0x1070100000478ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP16_IP4"           ,	   0x1070100000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP17_IP4"           ,	   0x1070100000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP18_IP4"           ,	   0x1070100000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP19_IP4"           ,	   0x1070100000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP20_IP4"           ,	   0x10701000004a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP21_IP4"           ,	   0x10701000004a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP22_IP4"           ,	   0x10701000004b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP23_IP4"           ,	   0x10701000004b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP24_IP4"           ,	   0x10701000004c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP25_IP4"           ,	   0x10701000004c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP26_IP4"           ,	   0x10701000004d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP27_IP4"           ,	   0x10701000004d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP28_IP4"           ,	   0x10701000004e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP29_IP4"           ,	   0x10701000004e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP30_IP4"           ,	   0x10701000004f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP31_IP4"           ,	   0x10701000004f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	265},
+	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	266},
+	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	267},
+	{"CIU_GSTOP"                   ,	   0x1070000000710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
+	{"CIU_INT_DBG_SEL"             ,	   0x10700000007d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	269},
+	{"CIU_MBOX_CLR0"               ,	   0x1070100100600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR1"               ,	   0x1070100100608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR2"               ,	   0x1070100100610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR3"               ,	   0x1070100100618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR4"               ,	   0x1070100100620ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR5"               ,	   0x1070100100628ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR6"               ,	   0x1070100100630ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR7"               ,	   0x1070100100638ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR8"               ,	   0x1070100100640ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR9"               ,	   0x1070100100648ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR10"              ,	   0x1070100100650ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR11"              ,	   0x1070100100658ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR12"              ,	   0x1070100100660ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR13"              ,	   0x1070100100668ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR14"              ,	   0x1070100100670ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR15"              ,	   0x1070100100678ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR16"              ,	   0x1070100100680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR17"              ,	   0x1070100100688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR18"              ,	   0x1070100100690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR19"              ,	   0x1070100100698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR20"              ,	   0x10701001006a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR21"              ,	   0x10701001006a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR22"              ,	   0x10701001006b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR23"              ,	   0x10701001006b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR24"              ,	   0x10701001006c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR25"              ,	   0x10701001006c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR26"              ,	   0x10701001006d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR27"              ,	   0x10701001006d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR28"              ,	   0x10701001006e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR29"              ,	   0x10701001006e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR30"              ,	   0x10701001006f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR31"              ,	   0x10701001006f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_SET0"               ,	   0x1070100100400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET1"               ,	   0x1070100100408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET2"               ,	   0x1070100100410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET3"               ,	   0x1070100100418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET4"               ,	   0x1070100100420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET5"               ,	   0x1070100100428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET6"               ,	   0x1070100100430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET7"               ,	   0x1070100100438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET8"               ,	   0x1070100100440ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET9"               ,	   0x1070100100448ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET10"              ,	   0x1070100100450ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET11"              ,	   0x1070100100458ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET12"              ,	   0x1070100100460ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET13"              ,	   0x1070100100468ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET14"              ,	   0x1070100100470ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET15"              ,	   0x1070100100478ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET16"              ,	   0x1070100100480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET17"              ,	   0x1070100100488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET18"              ,	   0x1070100100490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET19"              ,	   0x1070100100498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET20"              ,	   0x10701001004a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET21"              ,	   0x10701001004a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET22"              ,	   0x10701001004b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET23"              ,	   0x10701001004b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET24"              ,	   0x10701001004c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET25"              ,	   0x10701001004c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET26"              ,	   0x10701001004d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET27"              ,	   0x10701001004d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET28"              ,	   0x10701001004e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET29"              ,	   0x10701001004e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET30"              ,	   0x10701001004f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET31"              ,	   0x10701001004f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_NMI"                     ,	   0x1070000000718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	272},
+	{"CIU_PCI_INTA"                ,	   0x1070000000750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	273},
+	{"CIU_PP_BIST_STAT"            ,	   0x10700000007e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	274},
+	{"CIU_PP_DBG"                  ,	   0x1070000000708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	275},
+	{"CIU_PP_POKE0"                ,	   0x1070100100200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE1"                ,	   0x1070100100208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE2"                ,	   0x1070100100210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE3"                ,	   0x1070100100218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE4"                ,	   0x1070100100220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE5"                ,	   0x1070100100228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE6"                ,	   0x1070100100230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE7"                ,	   0x1070100100238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE8"                ,	   0x1070100100240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE9"                ,	   0x1070100100248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE10"               ,	   0x1070100100250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE11"               ,	   0x1070100100258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE12"               ,	   0x1070100100260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE13"               ,	   0x1070100100268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE14"               ,	   0x1070100100270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE15"               ,	   0x1070100100278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE16"               ,	   0x1070100100280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE17"               ,	   0x1070100100288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE18"               ,	   0x1070100100290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE19"               ,	   0x1070100100298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE20"               ,	   0x10701001002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE21"               ,	   0x10701001002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE22"               ,	   0x10701001002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE23"               ,	   0x10701001002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE24"               ,	   0x10701001002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE25"               ,	   0x10701001002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE26"               ,	   0x10701001002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE27"               ,	   0x10701001002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE28"               ,	   0x10701001002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE29"               ,	   0x10701001002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE30"               ,	   0x10701001002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE31"               ,	   0x10701001002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
+	{"CIU_QLM0"                    ,	   0x1070000000780ull,	CVMX_CSR_DB_TYPE_NCB,	64,	278},
+	{"CIU_QLM1"                    ,	   0x1070000000788ull,	CVMX_CSR_DB_TYPE_NCB,	64,	279},
+	{"CIU_QLM2"                    ,	   0x1070000000790ull,	CVMX_CSR_DB_TYPE_NCB,	64,	280},
+	{"CIU_QLM3"                    ,	   0x1070000000798ull,	CVMX_CSR_DB_TYPE_NCB,	64,	281},
+	{"CIU_QLM4"                    ,	   0x10700000007a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	282},
+	{"CIU_QLM_JTGC"                ,	   0x1070000000768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	283},
+	{"CIU_QLM_JTGD"                ,	   0x1070000000770ull,	CVMX_CSR_DB_TYPE_NCB,	64,	284},
+	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	285},
+	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"CIU_SOFT_PRST1"              ,	   0x1070000000758ull,	CVMX_CSR_DB_TYPE_NCB,	64,	287},
+	{"CIU_SOFT_RST"                ,	   0x1070000000740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	288},
+	{"CIU_TIM0"                    ,	   0x1070000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"CIU_TIM1"                    ,	   0x1070000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"CIU_WDOG0"                   ,	   0x1070100100000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG1"                   ,	   0x1070100100008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG2"                   ,	   0x1070100100010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG3"                   ,	   0x1070100100018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG4"                   ,	   0x1070100100020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG5"                   ,	   0x1070100100028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG6"                   ,	   0x1070100100030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG7"                   ,	   0x1070100100038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG8"                   ,	   0x1070100100040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG9"                   ,	   0x1070100100048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG10"                  ,	   0x1070100100050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG11"                  ,	   0x1070100100058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG12"                  ,	   0x1070100100060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG13"                  ,	   0x1070100100068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG14"                  ,	   0x1070100100070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG15"                  ,	   0x1070100100078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG16"                  ,	   0x1070100100080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG17"                  ,	   0x1070100100088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG18"                  ,	   0x1070100100090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG19"                  ,	   0x1070100100098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG20"                  ,	   0x10701001000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG21"                  ,	   0x10701001000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG22"                  ,	   0x10701001000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG23"                  ,	   0x10701001000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG24"                  ,	   0x10701001000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG25"                  ,	   0x10701001000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG26"                  ,	   0x10701001000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG27"                  ,	   0x10701001000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG28"                  ,	   0x10701001000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG29"                  ,	   0x10701001000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG30"                  ,	   0x10701001000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG31"                  ,	   0x10701001000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"DFA_BIST0"                   ,	   0x11800370007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"DFA_BIST1"                   ,	   0x11800370007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"DFA_CONFIG"                  ,	   0x1180037000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"DFA_CONTROL"                 ,	   0x1180037000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"DFA_DBELL"                   ,	   0x1370000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"DFA_DEBUG0"                  ,	   0x1180037000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"DFA_DEBUG1"                  ,	   0x1180037000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"DFA_DEBUG2"                  ,	   0x1180037000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"DFA_DEBUG3"                  ,	   0x1180037000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"DFA_DIFCTL"                  ,	   0x1370600000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	300},
+	{"DFA_DIFRDPTR"                ,	   0x1370200000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	301},
+	{"DFA_DTCFADR"                 ,	   0x1180037000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"DFA_ERROR"                   ,	   0x1180037000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"DFA_INTMSK"                  ,	   0x1180037000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"DFA_MEMHIDAT"                ,	   0x1370700000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	305},
+	{"DFA_PFC0_CNT"                ,	   0x1180037000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"DFA_PFC0_CTL"                ,	   0x1180037000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"DFA_PFC1_CNT"                ,	   0x11800370000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"DFA_PFC1_CTL"                ,	   0x1180037000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"DFA_PFC2_CNT"                ,	   0x11800370000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"DFA_PFC2_CTL"                ,	   0x11800370000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"DFA_PFC3_CNT"                ,	   0x11800370000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"DFA_PFC3_CTL"                ,	   0x11800370000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"DFA_PFC_GCTL"                ,	   0x1180037000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"DPI_BIST_STATUS"             ,	   0x1df0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	315},
+	{"DPI_CTL"                     ,	   0x1df0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	316},
+	{"DPI_DMA0_COUNTS"             ,	   0x1df0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"DPI_DMA1_COUNTS"             ,	   0x1df0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"DPI_DMA2_COUNTS"             ,	   0x1df0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"DPI_DMA3_COUNTS"             ,	   0x1df0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"DPI_DMA4_COUNTS"             ,	   0x1df0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"DPI_DMA5_COUNTS"             ,	   0x1df0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"DPI_DMA6_COUNTS"             ,	   0x1df0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"DPI_DMA7_COUNTS"             ,	   0x1df0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"DPI_DMA0_DBELL"              ,	   0x1df0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"DPI_DMA1_DBELL"              ,	   0x1df0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"DPI_DMA2_DBELL"              ,	   0x1df0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"DPI_DMA3_DBELL"              ,	   0x1df0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"DPI_DMA4_DBELL"              ,	   0x1df0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"DPI_DMA5_DBELL"              ,	   0x1df0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"DPI_DMA6_DBELL"              ,	   0x1df0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"DPI_DMA7_DBELL"              ,	   0x1df0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"DPI_DMA0_ERR_RSP_STATUS"     ,	   0x1df0000000a80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"DPI_DMA1_ERR_RSP_STATUS"     ,	   0x1df0000000a88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"DPI_DMA2_ERR_RSP_STATUS"     ,	   0x1df0000000a90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"DPI_DMA3_ERR_RSP_STATUS"     ,	   0x1df0000000a98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"DPI_DMA4_ERR_RSP_STATUS"     ,	   0x1df0000000aa0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"DPI_DMA5_ERR_RSP_STATUS"     ,	   0x1df0000000aa8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"DPI_DMA6_ERR_RSP_STATUS"     ,	   0x1df0000000ab0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"DPI_DMA7_ERR_RSP_STATUS"     ,	   0x1df0000000ab8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"DPI_DMA0_IBUFF_SADDR"        ,	   0x1df0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"DPI_DMA1_IBUFF_SADDR"        ,	   0x1df0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"DPI_DMA2_IBUFF_SADDR"        ,	   0x1df0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"DPI_DMA3_IBUFF_SADDR"        ,	   0x1df0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"DPI_DMA4_IBUFF_SADDR"        ,	   0x1df00000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"DPI_DMA5_IBUFF_SADDR"        ,	   0x1df00000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"DPI_DMA6_IBUFF_SADDR"        ,	   0x1df00000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"DPI_DMA7_IBUFF_SADDR"        ,	   0x1df00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"DPI_DMA0_IFLIGHT"            ,	   0x1df0000000a00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"DPI_DMA1_IFLIGHT"            ,	   0x1df0000000a08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"DPI_DMA2_IFLIGHT"            ,	   0x1df0000000a10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"DPI_DMA3_IFLIGHT"            ,	   0x1df0000000a18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"DPI_DMA4_IFLIGHT"            ,	   0x1df0000000a20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"DPI_DMA5_IFLIGHT"            ,	   0x1df0000000a28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"DPI_DMA6_IFLIGHT"            ,	   0x1df0000000a30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"DPI_DMA7_IFLIGHT"            ,	   0x1df0000000a38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"DPI_DMA0_NADDR"              ,	   0x1df0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"DPI_DMA1_NADDR"              ,	   0x1df0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"DPI_DMA2_NADDR"              ,	   0x1df0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"DPI_DMA3_NADDR"              ,	   0x1df0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"DPI_DMA4_NADDR"              ,	   0x1df00000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"DPI_DMA5_NADDR"              ,	   0x1df00000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"DPI_DMA6_NADDR"              ,	   0x1df00000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"DPI_DMA7_NADDR"              ,	   0x1df00000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"DPI_DMA0_REQBNK0"            ,	   0x1df0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"DPI_DMA1_REQBNK0"            ,	   0x1df0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"DPI_DMA2_REQBNK0"            ,	   0x1df0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"DPI_DMA3_REQBNK0"            ,	   0x1df0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"DPI_DMA4_REQBNK0"            ,	   0x1df0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"DPI_DMA5_REQBNK0"            ,	   0x1df0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"DPI_DMA6_REQBNK0"            ,	   0x1df0000000430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"DPI_DMA7_REQBNK0"            ,	   0x1df0000000438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"DPI_DMA0_REQBNK1"            ,	   0x1df0000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"DPI_DMA1_REQBNK1"            ,	   0x1df0000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"DPI_DMA2_REQBNK1"            ,	   0x1df0000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"DPI_DMA3_REQBNK1"            ,	   0x1df0000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"DPI_DMA4_REQBNK1"            ,	   0x1df00000004a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"DPI_DMA5_REQBNK1"            ,	   0x1df00000004a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"DPI_DMA6_REQBNK1"            ,	   0x1df00000004b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"DPI_DMA7_REQBNK1"            ,	   0x1df00000004b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"DPI_DMA_CONTROL"             ,	   0x1df0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	325},
+	{"DPI_DMA_ENG0_EN"             ,	   0x1df0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"DPI_DMA_ENG1_EN"             ,	   0x1df0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"DPI_DMA_ENG2_EN"             ,	   0x1df0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"DPI_DMA_ENG3_EN"             ,	   0x1df0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"DPI_DMA_ENG4_EN"             ,	   0x1df00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"DPI_DMA_ENG5_EN"             ,	   0x1df00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"DPI_ENG0_BUF"                ,	   0x1df0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_ENG1_BUF"                ,	   0x1df0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_ENG2_BUF"                ,	   0x1df0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_ENG3_BUF"                ,	   0x1df0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_ENG4_BUF"                ,	   0x1df00000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_ENG5_BUF"                ,	   0x1df00000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_INFO_REG"                ,	   0x1df0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
+	{"DPI_INT_EN"                  ,	   0x1df0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
+	{"DPI_INT_REG"                 ,	   0x1df0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	330},
+	{"DPI_PINT_INFO"               ,	   0x1df0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	331},
+	{"DPI_PKT_ERR_RSP"             ,	   0x1df0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
+	{"DPI_REQ_ERR_RSP"             ,	   0x1df0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	333},
+	{"DPI_REQ_ERR_RSP_EN"          ,	   0x1df0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"DPI_REQ_ERR_RST"             ,	   0x1df0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"DPI_REQ_ERR_RST_EN"          ,	   0x1df0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"DPI_REQ_ERR_SKIP_COMP"       ,	   0x1df0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"DPI_REQ_GBL_EN"              ,	   0x1df0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"DPI_SLI_PRT0_CFG"            ,	   0x1df0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"DPI_SLI_PRT1_CFG"            ,	   0x1df0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"DPI_SLI_PRT0_ERR"            ,	   0x1df0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"DPI_SLI_PRT1_ERR"            ,	   0x1df0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"DPI_SLI_PRT0_ERR_INFO"       ,	   0x1df0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"DPI_SLI_PRT1_ERR_INFO"       ,	   0x1df0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"FPA_ADDR_RANGE_ERROR"        ,	   0x1180028000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"FPA_FPF3_MARKS"              ,	   0x1180028000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"FPA_FPF4_MARKS"              ,	   0x1180028000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"FPA_FPF5_MARKS"              ,	   0x1180028000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"FPA_FPF6_MARKS"              ,	   0x1180028000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"FPA_FPF7_MARKS"              ,	   0x1180028000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"FPA_FPF1_SIZE"               ,	   0x1180028000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"FPA_FPF2_SIZE"               ,	   0x1180028000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"FPA_FPF3_SIZE"               ,	   0x1180028000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"FPA_FPF4_SIZE"               ,	   0x1180028000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"FPA_FPF5_SIZE"               ,	   0x1180028000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"FPA_FPF6_SIZE"               ,	   0x1180028000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"FPA_FPF7_SIZE"               ,	   0x1180028000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"FPA_FPF0_MARKS"              ,	   0x1180028000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"FPA_FPF0_SIZE"               ,	   0x1180028000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
+	{"FPA_FPF8_MARKS"              ,	   0x1180028000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"FPA_FPF8_SIZE"               ,	   0x1180028000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
+	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
+	{"FPA_PACKET_THRESHOLD"        ,	   0x1180028000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	353},
+	{"FPA_POOL0_END_ADDR"          ,	   0x1180028000358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"FPA_POOL1_END_ADDR"          ,	   0x1180028000360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"FPA_POOL2_END_ADDR"          ,	   0x1180028000368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"FPA_POOL3_END_ADDR"          ,	   0x1180028000370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"FPA_POOL4_END_ADDR"          ,	   0x1180028000378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"FPA_POOL5_END_ADDR"          ,	   0x1180028000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"FPA_POOL6_END_ADDR"          ,	   0x1180028000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"FPA_POOL7_END_ADDR"          ,	   0x1180028000390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"FPA_POOL8_END_ADDR"          ,	   0x1180028000398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"FPA_POOL0_START_ADDR"        ,	   0x1180028000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"FPA_POOL1_START_ADDR"        ,	   0x1180028000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"FPA_POOL2_START_ADDR"        ,	   0x1180028000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"FPA_POOL3_START_ADDR"        ,	   0x1180028000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"FPA_POOL4_START_ADDR"        ,	   0x1180028000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"FPA_POOL5_START_ADDR"        ,	   0x1180028000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"FPA_POOL6_START_ADDR"        ,	   0x1180028000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"FPA_POOL7_START_ADDR"        ,	   0x1180028000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"FPA_POOL8_START_ADDR"        ,	   0x1180028000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"FPA_POOL0_THRESHOLD"         ,	   0x1180028000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"FPA_POOL1_THRESHOLD"         ,	   0x1180028000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"FPA_POOL2_THRESHOLD"         ,	   0x1180028000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"FPA_POOL3_THRESHOLD"         ,	   0x1180028000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"FPA_POOL4_THRESHOLD"         ,	   0x1180028000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"FPA_POOL5_THRESHOLD"         ,	   0x1180028000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"FPA_POOL6_THRESHOLD"         ,	   0x1180028000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"FPA_POOL7_THRESHOLD"         ,	   0x1180028000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"FPA_POOL8_THRESHOLD"         ,	   0x1180028000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"FPA_QUE8_AVAILABLE"          ,	   0x11800280000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"FPA_QUE5_PAGE_INDEX"         ,	   0x1180028000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"FPA_QUE6_PAGE_INDEX"         ,	   0x1180028000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"FPA_QUE8_PAGE_INDEX"         ,	   0x1180028000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	361},
+	{"FPA_WQE_THRESHOLD"           ,	   0x1180028000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	362},
+	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"GMX1_BAD_REG"                ,	   0x1180009000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"GMX2_BAD_REG"                ,	   0x118000a000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"GMX3_BAD_REG"                ,	   0x118000b000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"GMX4_BAD_REG"                ,	   0x118000c000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
+	{"GMX1_BIST"                   ,	   0x1180009000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
+	{"GMX2_BIST"                   ,	   0x118000a000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
+	{"GMX3_BIST"                   ,	   0x118000b000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
+	{"GMX4_BIST"                   ,	   0x118000c000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
+	{"GMX0_BPID_MAP000"            ,	   0x1180008000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_BPID_MAP001"            ,	   0x1180008000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_BPID_MAP002"            ,	   0x1180008000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_BPID_MAP003"            ,	   0x1180008000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_BPID_MAP004"            ,	   0x11800080006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_BPID_MAP005"            ,	   0x11800080006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_BPID_MAP006"            ,	   0x11800080006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_BPID_MAP007"            ,	   0x11800080006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_BPID_MAP008"            ,	   0x11800080006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_BPID_MAP009"            ,	   0x11800080006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_BPID_MAP010"            ,	   0x11800080006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_BPID_MAP011"            ,	   0x11800080006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_BPID_MAP012"            ,	   0x11800080006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_BPID_MAP013"            ,	   0x11800080006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_BPID_MAP014"            ,	   0x11800080006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_BPID_MAP015"            ,	   0x11800080006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX1_BPID_MAP000"            ,	   0x1180009000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX1_BPID_MAP001"            ,	   0x1180009000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX1_BPID_MAP002"            ,	   0x1180009000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX1_BPID_MAP003"            ,	   0x1180009000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX1_BPID_MAP004"            ,	   0x11800090006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX1_BPID_MAP005"            ,	   0x11800090006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX1_BPID_MAP006"            ,	   0x11800090006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX1_BPID_MAP007"            ,	   0x11800090006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX1_BPID_MAP008"            ,	   0x11800090006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX1_BPID_MAP009"            ,	   0x11800090006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX1_BPID_MAP010"            ,	   0x11800090006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX1_BPID_MAP011"            ,	   0x11800090006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX1_BPID_MAP012"            ,	   0x11800090006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX1_BPID_MAP013"            ,	   0x11800090006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX1_BPID_MAP014"            ,	   0x11800090006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX1_BPID_MAP015"            ,	   0x11800090006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX2_BPID_MAP000"            ,	   0x118000a000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX2_BPID_MAP001"            ,	   0x118000a000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX2_BPID_MAP002"            ,	   0x118000a000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX2_BPID_MAP003"            ,	   0x118000a000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX2_BPID_MAP004"            ,	   0x118000a0006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX2_BPID_MAP005"            ,	   0x118000a0006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX2_BPID_MAP006"            ,	   0x118000a0006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX2_BPID_MAP007"            ,	   0x118000a0006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX2_BPID_MAP008"            ,	   0x118000a0006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX2_BPID_MAP009"            ,	   0x118000a0006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX2_BPID_MAP010"            ,	   0x118000a0006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX2_BPID_MAP011"            ,	   0x118000a0006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX2_BPID_MAP012"            ,	   0x118000a0006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX2_BPID_MAP013"            ,	   0x118000a0006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX2_BPID_MAP014"            ,	   0x118000a0006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX2_BPID_MAP015"            ,	   0x118000a0006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX3_BPID_MAP000"            ,	   0x118000b000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX3_BPID_MAP001"            ,	   0x118000b000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX3_BPID_MAP002"            ,	   0x118000b000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX3_BPID_MAP003"            ,	   0x118000b000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX3_BPID_MAP004"            ,	   0x118000b0006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX3_BPID_MAP005"            ,	   0x118000b0006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX3_BPID_MAP006"            ,	   0x118000b0006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX3_BPID_MAP007"            ,	   0x118000b0006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX3_BPID_MAP008"            ,	   0x118000b0006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX3_BPID_MAP009"            ,	   0x118000b0006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX3_BPID_MAP010"            ,	   0x118000b0006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX3_BPID_MAP011"            ,	   0x118000b0006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX3_BPID_MAP012"            ,	   0x118000b0006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX3_BPID_MAP013"            ,	   0x118000b0006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX3_BPID_MAP014"            ,	   0x118000b0006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX3_BPID_MAP015"            ,	   0x118000b0006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX4_BPID_MAP000"            ,	   0x118000c000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX4_BPID_MAP001"            ,	   0x118000c000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX4_BPID_MAP002"            ,	   0x118000c000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX4_BPID_MAP003"            ,	   0x118000c000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX4_BPID_MAP004"            ,	   0x118000c0006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX4_BPID_MAP005"            ,	   0x118000c0006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX4_BPID_MAP006"            ,	   0x118000c0006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX4_BPID_MAP007"            ,	   0x118000c0006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX4_BPID_MAP008"            ,	   0x118000c0006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX4_BPID_MAP009"            ,	   0x118000c0006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX4_BPID_MAP010"            ,	   0x118000c0006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX4_BPID_MAP011"            ,	   0x118000c0006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX4_BPID_MAP012"            ,	   0x118000c0006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX4_BPID_MAP013"            ,	   0x118000c0006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX4_BPID_MAP014"            ,	   0x118000c0006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX4_BPID_MAP015"            ,	   0x118000c0006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_BPID_MSK"               ,	   0x1180008000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"GMX1_BPID_MSK"               ,	   0x1180009000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"GMX2_BPID_MSK"               ,	   0x118000a000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"GMX3_BPID_MSK"               ,	   0x118000b000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"GMX4_BPID_MSK"               ,	   0x118000c000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"GMX0_CLK_EN"                 ,	   0x11800080007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX1_CLK_EN"                 ,	   0x11800090007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX2_CLK_EN"                 ,	   0x118000a0007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX3_CLK_EN"                 ,	   0x118000b0007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX4_CLK_EN"                 ,	   0x118000c0007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_EBP_DIS"                ,	   0x1180008000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"GMX1_EBP_DIS"                ,	   0x1180009000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"GMX2_EBP_DIS"                ,	   0x118000a000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"GMX3_EBP_DIS"                ,	   0x118000b000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"GMX4_EBP_DIS"                ,	   0x118000c000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"GMX0_EBP_MSK"                ,	   0x1180008000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"GMX1_EBP_MSK"                ,	   0x1180009000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"GMX2_EBP_MSK"                ,	   0x118000a000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"GMX3_EBP_MSK"                ,	   0x118000b000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"GMX4_EBP_MSK"                ,	   0x118000c000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"GMX0_HG2_CONTROL"            ,	   0x1180008000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"GMX1_HG2_CONTROL"            ,	   0x1180009000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"GMX2_HG2_CONTROL"            ,	   0x118000a000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"GMX3_HG2_CONTROL"            ,	   0x118000b000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"GMX4_HG2_CONTROL"            ,	   0x118000c000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"GMX0_INF_MODE"               ,	   0x11800080007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"GMX1_INF_MODE"               ,	   0x11800090007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"GMX2_INF_MODE"               ,	   0x118000a0007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"GMX3_INF_MODE"               ,	   0x118000b0007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"GMX4_INF_MODE"               ,	   0x118000c0007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"GMX1_NXA_ADR"                ,	   0x1180009000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"GMX2_NXA_ADR"                ,	   0x118000a000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"GMX3_NXA_ADR"                ,	   0x118000b000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"GMX4_NXA_ADR"                ,	   0x118000c000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"GMX0_PIPE_STATUS"            ,	   0x1180008000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"GMX1_PIPE_STATUS"            ,	   0x1180009000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"GMX2_PIPE_STATUS"            ,	   0x118000a000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"GMX3_PIPE_STATUS"            ,	   0x118000b000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"GMX4_PIPE_STATUS"            ,	   0x118000c000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"GMX0_PRT000_CBFC_CTL"        ,	   0x1180008000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"GMX1_PRT000_CBFC_CTL"        ,	   0x1180009000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"GMX2_PRT000_CBFC_CTL"        ,	   0x118000a000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"GMX3_PRT000_CBFC_CTL"        ,	   0x118000b000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"GMX4_PRT000_CBFC_CTL"        ,	   0x118000c000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX0_PRT002_CFG"             ,	   0x1180008001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX0_PRT003_CFG"             ,	   0x1180008001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX1_PRT000_CFG"             ,	   0x1180009000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX1_PRT001_CFG"             ,	   0x1180009000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX1_PRT002_CFG"             ,	   0x1180009001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX1_PRT003_CFG"             ,	   0x1180009001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX2_PRT000_CFG"             ,	   0x118000a000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX2_PRT001_CFG"             ,	   0x118000a000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX2_PRT002_CFG"             ,	   0x118000a001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX2_PRT003_CFG"             ,	   0x118000a001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX3_PRT000_CFG"             ,	   0x118000b000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX3_PRT001_CFG"             ,	   0x118000b000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX3_PRT002_CFG"             ,	   0x118000b001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX3_PRT003_CFG"             ,	   0x118000b001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX4_PRT000_CFG"             ,	   0x118000c000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX4_PRT001_CFG"             ,	   0x118000c000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX4_PRT002_CFG"             ,	   0x118000c001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX4_PRT003_CFG"             ,	   0x118000c001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX0_RX000_ADR_CAM0"         ,	   0x1180008000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX0_RX001_ADR_CAM0"         ,	   0x1180008000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX0_RX002_ADR_CAM0"         ,	   0x1180008001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX0_RX003_ADR_CAM0"         ,	   0x1180008001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX1_RX000_ADR_CAM0"         ,	   0x1180009000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX1_RX001_ADR_CAM0"         ,	   0x1180009000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX1_RX002_ADR_CAM0"         ,	   0x1180009001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX1_RX003_ADR_CAM0"         ,	   0x1180009001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX2_RX000_ADR_CAM0"         ,	   0x118000a000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX2_RX001_ADR_CAM0"         ,	   0x118000a000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX2_RX002_ADR_CAM0"         ,	   0x118000a001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX2_RX003_ADR_CAM0"         ,	   0x118000a001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX3_RX000_ADR_CAM0"         ,	   0x118000b000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX3_RX001_ADR_CAM0"         ,	   0x118000b000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX3_RX002_ADR_CAM0"         ,	   0x118000b001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX3_RX003_ADR_CAM0"         ,	   0x118000b001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX4_RX000_ADR_CAM0"         ,	   0x118000c000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX4_RX001_ADR_CAM0"         ,	   0x118000c000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX4_RX002_ADR_CAM0"         ,	   0x118000c001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX4_RX003_ADR_CAM0"         ,	   0x118000c001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX0_RX000_ADR_CAM1"         ,	   0x1180008000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX0_RX001_ADR_CAM1"         ,	   0x1180008000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX0_RX002_ADR_CAM1"         ,	   0x1180008001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX0_RX003_ADR_CAM1"         ,	   0x1180008001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX1_RX000_ADR_CAM1"         ,	   0x1180009000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX1_RX001_ADR_CAM1"         ,	   0x1180009000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX1_RX002_ADR_CAM1"         ,	   0x1180009001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX1_RX003_ADR_CAM1"         ,	   0x1180009001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX2_RX000_ADR_CAM1"         ,	   0x118000a000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX2_RX001_ADR_CAM1"         ,	   0x118000a000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX2_RX002_ADR_CAM1"         ,	   0x118000a001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX2_RX003_ADR_CAM1"         ,	   0x118000a001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX3_RX000_ADR_CAM1"         ,	   0x118000b000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX3_RX001_ADR_CAM1"         ,	   0x118000b000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX3_RX002_ADR_CAM1"         ,	   0x118000b001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX3_RX003_ADR_CAM1"         ,	   0x118000b001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX4_RX000_ADR_CAM1"         ,	   0x118000c000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX4_RX001_ADR_CAM1"         ,	   0x118000c000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX4_RX002_ADR_CAM1"         ,	   0x118000c001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX4_RX003_ADR_CAM1"         ,	   0x118000c001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX0_RX000_ADR_CAM2"         ,	   0x1180008000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX0_RX001_ADR_CAM2"         ,	   0x1180008000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX0_RX002_ADR_CAM2"         ,	   0x1180008001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX0_RX003_ADR_CAM2"         ,	   0x1180008001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX1_RX000_ADR_CAM2"         ,	   0x1180009000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX1_RX001_ADR_CAM2"         ,	   0x1180009000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX1_RX002_ADR_CAM2"         ,	   0x1180009001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX1_RX003_ADR_CAM2"         ,	   0x1180009001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX2_RX000_ADR_CAM2"         ,	   0x118000a000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX2_RX001_ADR_CAM2"         ,	   0x118000a000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX2_RX002_ADR_CAM2"         ,	   0x118000a001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX2_RX003_ADR_CAM2"         ,	   0x118000a001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX3_RX000_ADR_CAM2"         ,	   0x118000b000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX3_RX001_ADR_CAM2"         ,	   0x118000b000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX3_RX002_ADR_CAM2"         ,	   0x118000b001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX3_RX003_ADR_CAM2"         ,	   0x118000b001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX4_RX000_ADR_CAM2"         ,	   0x118000c000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX4_RX001_ADR_CAM2"         ,	   0x118000c000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX4_RX002_ADR_CAM2"         ,	   0x118000c001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX4_RX003_ADR_CAM2"         ,	   0x118000c001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX0_RX003_ADR_CAM3"         ,	   0x1180008001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX1_RX000_ADR_CAM3"         ,	   0x1180009000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX1_RX001_ADR_CAM3"         ,	   0x1180009000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX1_RX002_ADR_CAM3"         ,	   0x1180009001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX1_RX003_ADR_CAM3"         ,	   0x1180009001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX2_RX000_ADR_CAM3"         ,	   0x118000a000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX2_RX001_ADR_CAM3"         ,	   0x118000a000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX2_RX002_ADR_CAM3"         ,	   0x118000a001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX2_RX003_ADR_CAM3"         ,	   0x118000a001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX3_RX000_ADR_CAM3"         ,	   0x118000b000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX3_RX001_ADR_CAM3"         ,	   0x118000b000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX3_RX002_ADR_CAM3"         ,	   0x118000b001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX3_RX003_ADR_CAM3"         ,	   0x118000b001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX4_RX000_ADR_CAM3"         ,	   0x118000c000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX4_RX001_ADR_CAM3"         ,	   0x118000c000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX4_RX002_ADR_CAM3"         ,	   0x118000c001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX4_RX003_ADR_CAM3"         ,	   0x118000c001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800090001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800090009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800090011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800090019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX2_RX000_ADR_CAM4"         ,	   0x118000a0001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX2_RX001_ADR_CAM4"         ,	   0x118000a0009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX2_RX002_ADR_CAM4"         ,	   0x118000a0011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX2_RX003_ADR_CAM4"         ,	   0x118000a0019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX3_RX000_ADR_CAM4"         ,	   0x118000b0001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX3_RX001_ADR_CAM4"         ,	   0x118000b0009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX3_RX002_ADR_CAM4"         ,	   0x118000b0011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX3_RX003_ADR_CAM4"         ,	   0x118000b0019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX4_RX000_ADR_CAM4"         ,	   0x118000c0001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX4_RX001_ADR_CAM4"         ,	   0x118000c0009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX4_RX002_ADR_CAM4"         ,	   0x118000c0011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX4_RX003_ADR_CAM4"         ,	   0x118000c0019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800090001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800090009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800090011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800090019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX2_RX000_ADR_CAM5"         ,	   0x118000a0001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX2_RX001_ADR_CAM5"         ,	   0x118000a0009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX2_RX002_ADR_CAM5"         ,	   0x118000a0011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX2_RX003_ADR_CAM5"         ,	   0x118000a0019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX3_RX000_ADR_CAM5"         ,	   0x118000b0001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX3_RX001_ADR_CAM5"         ,	   0x118000b0009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX3_RX002_ADR_CAM5"         ,	   0x118000b0011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX3_RX003_ADR_CAM5"         ,	   0x118000b0019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX4_RX000_ADR_CAM5"         ,	   0x118000c0001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX4_RX001_ADR_CAM5"         ,	   0x118000c0009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX4_RX002_ADR_CAM5"         ,	   0x118000c0011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX4_RX003_ADR_CAM5"         ,	   0x118000c0019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX0_RX003_ADR_CAM_EN"       ,	   0x1180008001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX1_RX000_ADR_CAM_EN"       ,	   0x1180009000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX1_RX001_ADR_CAM_EN"       ,	   0x1180009000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX1_RX002_ADR_CAM_EN"       ,	   0x1180009001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX1_RX003_ADR_CAM_EN"       ,	   0x1180009001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX2_RX000_ADR_CAM_EN"       ,	   0x118000a000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX2_RX001_ADR_CAM_EN"       ,	   0x118000a000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX2_RX002_ADR_CAM_EN"       ,	   0x118000a001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX2_RX003_ADR_CAM_EN"       ,	   0x118000a001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX3_RX000_ADR_CAM_EN"       ,	   0x118000b000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX3_RX001_ADR_CAM_EN"       ,	   0x118000b000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX3_RX002_ADR_CAM_EN"       ,	   0x118000b001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX3_RX003_ADR_CAM_EN"       ,	   0x118000b001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX4_RX000_ADR_CAM_EN"       ,	   0x118000c000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX4_RX001_ADR_CAM_EN"       ,	   0x118000c000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX4_RX002_ADR_CAM_EN"       ,	   0x118000c001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX4_RX003_ADR_CAM_EN"       ,	   0x118000c001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX0_RX000_ADR_CTL"          ,	   0x1180008000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX0_RX001_ADR_CTL"          ,	   0x1180008000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX0_RX002_ADR_CTL"          ,	   0x1180008001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX0_RX003_ADR_CTL"          ,	   0x1180008001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX1_RX000_ADR_CTL"          ,	   0x1180009000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX1_RX001_ADR_CTL"          ,	   0x1180009000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX1_RX002_ADR_CTL"          ,	   0x1180009001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX1_RX003_ADR_CTL"          ,	   0x1180009001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX2_RX000_ADR_CTL"          ,	   0x118000a000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX2_RX001_ADR_CTL"          ,	   0x118000a000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX2_RX002_ADR_CTL"          ,	   0x118000a001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX2_RX003_ADR_CTL"          ,	   0x118000a001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX3_RX000_ADR_CTL"          ,	   0x118000b000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX3_RX001_ADR_CTL"          ,	   0x118000b000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX3_RX002_ADR_CTL"          ,	   0x118000b001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX3_RX003_ADR_CTL"          ,	   0x118000b001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX4_RX000_ADR_CTL"          ,	   0x118000c000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX4_RX001_ADR_CTL"          ,	   0x118000c000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX4_RX002_ADR_CTL"          ,	   0x118000c001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX4_RX003_ADR_CTL"          ,	   0x118000c001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX0_RX000_DECISION"         ,	   0x1180008000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX0_RX001_DECISION"         ,	   0x1180008000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX0_RX002_DECISION"         ,	   0x1180008001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX0_RX003_DECISION"         ,	   0x1180008001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX1_RX000_DECISION"         ,	   0x1180009000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX1_RX001_DECISION"         ,	   0x1180009000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX1_RX002_DECISION"         ,	   0x1180009001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX1_RX003_DECISION"         ,	   0x1180009001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX2_RX000_DECISION"         ,	   0x118000a000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX2_RX001_DECISION"         ,	   0x118000a000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX2_RX002_DECISION"         ,	   0x118000a001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX2_RX003_DECISION"         ,	   0x118000a001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX3_RX000_DECISION"         ,	   0x118000b000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX3_RX001_DECISION"         ,	   0x118000b000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX3_RX002_DECISION"         ,	   0x118000b001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX3_RX003_DECISION"         ,	   0x118000b001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX4_RX000_DECISION"         ,	   0x118000c000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX4_RX001_DECISION"         ,	   0x118000c000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX4_RX002_DECISION"         ,	   0x118000c001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX4_RX003_DECISION"         ,	   0x118000c001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX0_RX000_FRM_CHK"          ,	   0x1180008000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX0_RX001_FRM_CHK"          ,	   0x1180008000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX0_RX002_FRM_CHK"          ,	   0x1180008001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX0_RX003_FRM_CHK"          ,	   0x1180008001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX1_RX000_FRM_CHK"          ,	   0x1180009000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX1_RX001_FRM_CHK"          ,	   0x1180009000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX1_RX002_FRM_CHK"          ,	   0x1180009001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX1_RX003_FRM_CHK"          ,	   0x1180009001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX2_RX000_FRM_CHK"          ,	   0x118000a000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX2_RX001_FRM_CHK"          ,	   0x118000a000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX2_RX002_FRM_CHK"          ,	   0x118000a001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX2_RX003_FRM_CHK"          ,	   0x118000a001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX3_RX000_FRM_CHK"          ,	   0x118000b000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX3_RX001_FRM_CHK"          ,	   0x118000b000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX3_RX002_FRM_CHK"          ,	   0x118000b001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX3_RX003_FRM_CHK"          ,	   0x118000b001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX4_RX000_FRM_CHK"          ,	   0x118000c000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX4_RX001_FRM_CHK"          ,	   0x118000c000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX4_RX002_FRM_CHK"          ,	   0x118000c001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX4_RX003_FRM_CHK"          ,	   0x118000c001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX0_RX000_FRM_CTL"          ,	   0x1180008000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX0_RX001_FRM_CTL"          ,	   0x1180008000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX0_RX002_FRM_CTL"          ,	   0x1180008001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX0_RX003_FRM_CTL"          ,	   0x1180008001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX1_RX000_FRM_CTL"          ,	   0x1180009000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX1_RX001_FRM_CTL"          ,	   0x1180009000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX1_RX002_FRM_CTL"          ,	   0x1180009001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX1_RX003_FRM_CTL"          ,	   0x1180009001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX2_RX000_FRM_CTL"          ,	   0x118000a000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX2_RX001_FRM_CTL"          ,	   0x118000a000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX2_RX002_FRM_CTL"          ,	   0x118000a001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX2_RX003_FRM_CTL"          ,	   0x118000a001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX3_RX000_FRM_CTL"          ,	   0x118000b000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX3_RX001_FRM_CTL"          ,	   0x118000b000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX3_RX002_FRM_CTL"          ,	   0x118000b001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX3_RX003_FRM_CTL"          ,	   0x118000b001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX4_RX000_FRM_CTL"          ,	   0x118000c000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX4_RX001_FRM_CTL"          ,	   0x118000c000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX4_RX002_FRM_CTL"          ,	   0x118000c001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX4_RX003_FRM_CTL"          ,	   0x118000c001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX0_RX000_IFG"              ,	   0x1180008000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX0_RX001_IFG"              ,	   0x1180008000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX0_RX002_IFG"              ,	   0x1180008001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX0_RX003_IFG"              ,	   0x1180008001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX1_RX000_IFG"              ,	   0x1180009000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX1_RX001_IFG"              ,	   0x1180009000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX1_RX002_IFG"              ,	   0x1180009001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX1_RX003_IFG"              ,	   0x1180009001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX2_RX000_IFG"              ,	   0x118000a000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX2_RX001_IFG"              ,	   0x118000a000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX2_RX002_IFG"              ,	   0x118000a001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX2_RX003_IFG"              ,	   0x118000a001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX3_RX000_IFG"              ,	   0x118000b000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX3_RX001_IFG"              ,	   0x118000b000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX3_RX002_IFG"              ,	   0x118000b001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX3_RX003_IFG"              ,	   0x118000b001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX4_RX000_IFG"              ,	   0x118000c000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX4_RX001_IFG"              ,	   0x118000c000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX4_RX002_IFG"              ,	   0x118000c001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX4_RX003_IFG"              ,	   0x118000c001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX0_RX000_INT_EN"           ,	   0x1180008000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX0_RX001_INT_EN"           ,	   0x1180008000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX0_RX002_INT_EN"           ,	   0x1180008001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX0_RX003_INT_EN"           ,	   0x1180008001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX1_RX000_INT_EN"           ,	   0x1180009000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX1_RX001_INT_EN"           ,	   0x1180009000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX1_RX002_INT_EN"           ,	   0x1180009001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX1_RX003_INT_EN"           ,	   0x1180009001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX2_RX000_INT_EN"           ,	   0x118000a000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX2_RX001_INT_EN"           ,	   0x118000a000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX2_RX002_INT_EN"           ,	   0x118000a001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX2_RX003_INT_EN"           ,	   0x118000a001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX3_RX000_INT_EN"           ,	   0x118000b000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX3_RX001_INT_EN"           ,	   0x118000b000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX3_RX002_INT_EN"           ,	   0x118000b001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX3_RX003_INT_EN"           ,	   0x118000b001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX4_RX000_INT_EN"           ,	   0x118000c000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX4_RX001_INT_EN"           ,	   0x118000c000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX4_RX002_INT_EN"           ,	   0x118000c001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX4_RX003_INT_EN"           ,	   0x118000c001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX0_RX000_INT_REG"          ,	   0x1180008000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX0_RX001_INT_REG"          ,	   0x1180008000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX0_RX002_INT_REG"          ,	   0x1180008001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX0_RX003_INT_REG"          ,	   0x1180008001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX1_RX000_INT_REG"          ,	   0x1180009000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX1_RX001_INT_REG"          ,	   0x1180009000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX1_RX002_INT_REG"          ,	   0x1180009001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX1_RX003_INT_REG"          ,	   0x1180009001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX2_RX000_INT_REG"          ,	   0x118000a000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX2_RX001_INT_REG"          ,	   0x118000a000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX2_RX002_INT_REG"          ,	   0x118000a001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX2_RX003_INT_REG"          ,	   0x118000a001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX3_RX000_INT_REG"          ,	   0x118000b000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX3_RX001_INT_REG"          ,	   0x118000b000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX3_RX002_INT_REG"          ,	   0x118000b001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX3_RX003_INT_REG"          ,	   0x118000b001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX4_RX000_INT_REG"          ,	   0x118000c000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX4_RX001_INT_REG"          ,	   0x118000c000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX4_RX002_INT_REG"          ,	   0x118000c001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX4_RX003_INT_REG"          ,	   0x118000c001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX0_RX000_JABBER"           ,	   0x1180008000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX0_RX001_JABBER"           ,	   0x1180008000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX0_RX002_JABBER"           ,	   0x1180008001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX0_RX003_JABBER"           ,	   0x1180008001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX1_RX000_JABBER"           ,	   0x1180009000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX1_RX001_JABBER"           ,	   0x1180009000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX1_RX002_JABBER"           ,	   0x1180009001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX1_RX003_JABBER"           ,	   0x1180009001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX2_RX000_JABBER"           ,	   0x118000a000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX2_RX001_JABBER"           ,	   0x118000a000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX2_RX002_JABBER"           ,	   0x118000a001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX2_RX003_JABBER"           ,	   0x118000a001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX3_RX000_JABBER"           ,	   0x118000b000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX3_RX001_JABBER"           ,	   0x118000b000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX3_RX002_JABBER"           ,	   0x118000b001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX3_RX003_JABBER"           ,	   0x118000b001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX4_RX000_JABBER"           ,	   0x118000c000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX4_RX001_JABBER"           ,	   0x118000c000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX4_RX002_JABBER"           ,	   0x118000c001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX4_RX003_JABBER"           ,	   0x118000c001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX0_RX000_PAUSE_DROP_TIME"  ,	   0x1180008000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX0_RX001_PAUSE_DROP_TIME"  ,	   0x1180008000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX0_RX002_PAUSE_DROP_TIME"  ,	   0x1180008001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX0_RX003_PAUSE_DROP_TIME"  ,	   0x1180008001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX1_RX000_PAUSE_DROP_TIME"  ,	   0x1180009000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX1_RX001_PAUSE_DROP_TIME"  ,	   0x1180009000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX1_RX002_PAUSE_DROP_TIME"  ,	   0x1180009001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX1_RX003_PAUSE_DROP_TIME"  ,	   0x1180009001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX2_RX000_PAUSE_DROP_TIME"  ,	   0x118000a000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX2_RX001_PAUSE_DROP_TIME"  ,	   0x118000a000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX2_RX002_PAUSE_DROP_TIME"  ,	   0x118000a001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX2_RX003_PAUSE_DROP_TIME"  ,	   0x118000a001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX3_RX000_PAUSE_DROP_TIME"  ,	   0x118000b000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX3_RX001_PAUSE_DROP_TIME"  ,	   0x118000b000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX3_RX002_PAUSE_DROP_TIME"  ,	   0x118000b001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX3_RX003_PAUSE_DROP_TIME"  ,	   0x118000b001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX4_RX000_PAUSE_DROP_TIME"  ,	   0x118000c000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX4_RX001_PAUSE_DROP_TIME"  ,	   0x118000c000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX4_RX002_PAUSE_DROP_TIME"  ,	   0x118000c001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX4_RX003_PAUSE_DROP_TIME"  ,	   0x118000c001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX0_RX000_STATS_CTL"        ,	   0x1180008000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX0_RX001_STATS_CTL"        ,	   0x1180008000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX0_RX002_STATS_CTL"        ,	   0x1180008001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX0_RX003_STATS_CTL"        ,	   0x1180008001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX1_RX000_STATS_CTL"        ,	   0x1180009000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX1_RX001_STATS_CTL"        ,	   0x1180009000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX1_RX002_STATS_CTL"        ,	   0x1180009001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX1_RX003_STATS_CTL"        ,	   0x1180009001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX2_RX000_STATS_CTL"        ,	   0x118000a000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX2_RX001_STATS_CTL"        ,	   0x118000a000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX2_RX002_STATS_CTL"        ,	   0x118000a001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX2_RX003_STATS_CTL"        ,	   0x118000a001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX3_RX000_STATS_CTL"        ,	   0x118000b000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX3_RX001_STATS_CTL"        ,	   0x118000b000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX3_RX002_STATS_CTL"        ,	   0x118000b001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX3_RX003_STATS_CTL"        ,	   0x118000b001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX4_RX000_STATS_CTL"        ,	   0x118000c000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX4_RX001_STATS_CTL"        ,	   0x118000c000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX4_RX002_STATS_CTL"        ,	   0x118000c001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX4_RX003_STATS_CTL"        ,	   0x118000c001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX0_RX000_STATS_OCTS"       ,	   0x1180008000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX0_RX001_STATS_OCTS"       ,	   0x1180008000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX0_RX002_STATS_OCTS"       ,	   0x1180008001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX0_RX003_STATS_OCTS"       ,	   0x1180008001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX1_RX000_STATS_OCTS"       ,	   0x1180009000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX1_RX001_STATS_OCTS"       ,	   0x1180009000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX1_RX002_STATS_OCTS"       ,	   0x1180009001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX1_RX003_STATS_OCTS"       ,	   0x1180009001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX2_RX000_STATS_OCTS"       ,	   0x118000a000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX2_RX001_STATS_OCTS"       ,	   0x118000a000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX2_RX002_STATS_OCTS"       ,	   0x118000a001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX2_RX003_STATS_OCTS"       ,	   0x118000a001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX3_RX000_STATS_OCTS"       ,	   0x118000b000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX3_RX001_STATS_OCTS"       ,	   0x118000b000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX3_RX002_STATS_OCTS"       ,	   0x118000b001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX3_RX003_STATS_OCTS"       ,	   0x118000b001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX4_RX000_STATS_OCTS"       ,	   0x118000c000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX4_RX001_STATS_OCTS"       ,	   0x118000c000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX4_RX002_STATS_OCTS"       ,	   0x118000c001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX4_RX003_STATS_OCTS"       ,	   0x118000c001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX0_RX003_STATS_OCTS_CTL"   ,	   0x1180008001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX1_RX000_STATS_OCTS_CTL"   ,	   0x1180009000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX1_RX001_STATS_OCTS_CTL"   ,	   0x1180009000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX1_RX002_STATS_OCTS_CTL"   ,	   0x1180009001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX1_RX003_STATS_OCTS_CTL"   ,	   0x1180009001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX2_RX000_STATS_OCTS_CTL"   ,	   0x118000a000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX2_RX001_STATS_OCTS_CTL"   ,	   0x118000a000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX2_RX002_STATS_OCTS_CTL"   ,	   0x118000a001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX2_RX003_STATS_OCTS_CTL"   ,	   0x118000a001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX3_RX000_STATS_OCTS_CTL"   ,	   0x118000b000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX3_RX001_STATS_OCTS_CTL"   ,	   0x118000b000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX3_RX002_STATS_OCTS_CTL"   ,	   0x118000b001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX3_RX003_STATS_OCTS_CTL"   ,	   0x118000b001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX4_RX000_STATS_OCTS_CTL"   ,	   0x118000c000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX4_RX001_STATS_OCTS_CTL"   ,	   0x118000c000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX4_RX002_STATS_OCTS_CTL"   ,	   0x118000c001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX4_RX003_STATS_OCTS_CTL"   ,	   0x118000c001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800090000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800090008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800090010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800090018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX2_RX000_STATS_OCTS_DMAC"  ,	   0x118000a0000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX2_RX001_STATS_OCTS_DMAC"  ,	   0x118000a0008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX2_RX002_STATS_OCTS_DMAC"  ,	   0x118000a0010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX2_RX003_STATS_OCTS_DMAC"  ,	   0x118000a0018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX3_RX000_STATS_OCTS_DMAC"  ,	   0x118000b0000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX3_RX001_STATS_OCTS_DMAC"  ,	   0x118000b0008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX3_RX002_STATS_OCTS_DMAC"  ,	   0x118000b0010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX3_RX003_STATS_OCTS_DMAC"  ,	   0x118000b0018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX4_RX000_STATS_OCTS_DMAC"  ,	   0x118000c0000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX4_RX001_STATS_OCTS_DMAC"  ,	   0x118000c0008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX4_RX002_STATS_OCTS_DMAC"  ,	   0x118000c0010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX4_RX003_STATS_OCTS_DMAC"  ,	   0x118000c0018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800090000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800090008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800090010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800090018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX2_RX000_STATS_OCTS_DRP"   ,	   0x118000a0000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX2_RX001_STATS_OCTS_DRP"   ,	   0x118000a0008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX2_RX002_STATS_OCTS_DRP"   ,	   0x118000a0010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX2_RX003_STATS_OCTS_DRP"   ,	   0x118000a0018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX3_RX000_STATS_OCTS_DRP"   ,	   0x118000b0000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX3_RX001_STATS_OCTS_DRP"   ,	   0x118000b0008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX3_RX002_STATS_OCTS_DRP"   ,	   0x118000b0010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX3_RX003_STATS_OCTS_DRP"   ,	   0x118000b0018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX4_RX000_STATS_OCTS_DRP"   ,	   0x118000c0000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX4_RX001_STATS_OCTS_DRP"   ,	   0x118000c0008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX4_RX002_STATS_OCTS_DRP"   ,	   0x118000c0010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX4_RX003_STATS_OCTS_DRP"   ,	   0x118000c0018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX0_RX003_STATS_PKTS"       ,	   0x1180008001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX1_RX000_STATS_PKTS"       ,	   0x1180009000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX1_RX001_STATS_PKTS"       ,	   0x1180009000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX1_RX002_STATS_PKTS"       ,	   0x1180009001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX1_RX003_STATS_PKTS"       ,	   0x1180009001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX2_RX000_STATS_PKTS"       ,	   0x118000a000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX2_RX001_STATS_PKTS"       ,	   0x118000a000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX2_RX002_STATS_PKTS"       ,	   0x118000a001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX2_RX003_STATS_PKTS"       ,	   0x118000a001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX3_RX000_STATS_PKTS"       ,	   0x118000b000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX3_RX001_STATS_PKTS"       ,	   0x118000b000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX3_RX002_STATS_PKTS"       ,	   0x118000b001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX3_RX003_STATS_PKTS"       ,	   0x118000b001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX4_RX000_STATS_PKTS"       ,	   0x118000c000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX4_RX001_STATS_PKTS"       ,	   0x118000c000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX4_RX002_STATS_PKTS"       ,	   0x118000c001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX4_RX003_STATS_PKTS"       ,	   0x118000c001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800090000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800090008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800090010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800090018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX2_RX000_STATS_PKTS_BAD"   ,	   0x118000a0000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX2_RX001_STATS_PKTS_BAD"   ,	   0x118000a0008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX2_RX002_STATS_PKTS_BAD"   ,	   0x118000a0010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX2_RX003_STATS_PKTS_BAD"   ,	   0x118000a0018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX3_RX000_STATS_PKTS_BAD"   ,	   0x118000b0000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX3_RX001_STATS_PKTS_BAD"   ,	   0x118000b0008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX3_RX002_STATS_PKTS_BAD"   ,	   0x118000b0010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX3_RX003_STATS_PKTS_BAD"   ,	   0x118000b0018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX4_RX000_STATS_PKTS_BAD"   ,	   0x118000c0000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX4_RX001_STATS_PKTS_BAD"   ,	   0x118000c0008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX4_RX002_STATS_PKTS_BAD"   ,	   0x118000c0010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX4_RX003_STATS_PKTS_BAD"   ,	   0x118000c0018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX0_RX003_STATS_PKTS_CTL"   ,	   0x1180008001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX1_RX000_STATS_PKTS_CTL"   ,	   0x1180009000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX1_RX001_STATS_PKTS_CTL"   ,	   0x1180009000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX1_RX002_STATS_PKTS_CTL"   ,	   0x1180009001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX1_RX003_STATS_PKTS_CTL"   ,	   0x1180009001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX2_RX000_STATS_PKTS_CTL"   ,	   0x118000a000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX2_RX001_STATS_PKTS_CTL"   ,	   0x118000a000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX2_RX002_STATS_PKTS_CTL"   ,	   0x118000a001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX2_RX003_STATS_PKTS_CTL"   ,	   0x118000a001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX3_RX000_STATS_PKTS_CTL"   ,	   0x118000b000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX3_RX001_STATS_PKTS_CTL"   ,	   0x118000b000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX3_RX002_STATS_PKTS_CTL"   ,	   0x118000b001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX3_RX003_STATS_PKTS_CTL"   ,	   0x118000b001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX4_RX000_STATS_PKTS_CTL"   ,	   0x118000c000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX4_RX001_STATS_PKTS_CTL"   ,	   0x118000c000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX4_RX002_STATS_PKTS_CTL"   ,	   0x118000c001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX4_RX003_STATS_PKTS_CTL"   ,	   0x118000c001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800090000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800090008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800090010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800090018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX2_RX000_STATS_PKTS_DMAC"  ,	   0x118000a0000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX2_RX001_STATS_PKTS_DMAC"  ,	   0x118000a0008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX2_RX002_STATS_PKTS_DMAC"  ,	   0x118000a0010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX2_RX003_STATS_PKTS_DMAC"  ,	   0x118000a0018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX3_RX000_STATS_PKTS_DMAC"  ,	   0x118000b0000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX3_RX001_STATS_PKTS_DMAC"  ,	   0x118000b0008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX3_RX002_STATS_PKTS_DMAC"  ,	   0x118000b0010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX3_RX003_STATS_PKTS_DMAC"  ,	   0x118000b0018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX4_RX000_STATS_PKTS_DMAC"  ,	   0x118000c0000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX4_RX001_STATS_PKTS_DMAC"  ,	   0x118000c0008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX4_RX002_STATS_PKTS_DMAC"  ,	   0x118000c0010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX4_RX003_STATS_PKTS_DMAC"  ,	   0x118000c0018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800090000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800090008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800090010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800090018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX2_RX000_STATS_PKTS_DRP"   ,	   0x118000a0000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX2_RX001_STATS_PKTS_DRP"   ,	   0x118000a0008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX2_RX002_STATS_PKTS_DRP"   ,	   0x118000a0010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX2_RX003_STATS_PKTS_DRP"   ,	   0x118000a0018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX3_RX000_STATS_PKTS_DRP"   ,	   0x118000b0000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX3_RX001_STATS_PKTS_DRP"   ,	   0x118000b0008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX3_RX002_STATS_PKTS_DRP"   ,	   0x118000b0010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX3_RX003_STATS_PKTS_DRP"   ,	   0x118000b0018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX4_RX000_STATS_PKTS_DRP"   ,	   0x118000c0000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX4_RX001_STATS_PKTS_DRP"   ,	   0x118000c0008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX4_RX002_STATS_PKTS_DRP"   ,	   0x118000c0010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX4_RX003_STATS_PKTS_DRP"   ,	   0x118000c0018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX0_RX003_UDD_SKP"          ,	   0x1180008001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX1_RX000_UDD_SKP"          ,	   0x1180009000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX1_RX001_UDD_SKP"          ,	   0x1180009000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX1_RX002_UDD_SKP"          ,	   0x1180009001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX1_RX003_UDD_SKP"          ,	   0x1180009001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX2_RX000_UDD_SKP"          ,	   0x118000a000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX2_RX001_UDD_SKP"          ,	   0x118000a000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX2_RX002_UDD_SKP"          ,	   0x118000a001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX2_RX003_UDD_SKP"          ,	   0x118000a001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX3_RX000_UDD_SKP"          ,	   0x118000b000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX3_RX001_UDD_SKP"          ,	   0x118000b000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX3_RX002_UDD_SKP"          ,	   0x118000b001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX3_RX003_UDD_SKP"          ,	   0x118000b001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX4_RX000_UDD_SKP"          ,	   0x118000c000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX4_RX001_UDD_SKP"          ,	   0x118000c000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX4_RX002_UDD_SKP"          ,	   0x118000c001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX4_RX003_UDD_SKP"          ,	   0x118000c001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX0_RX_BP_DROP000"          ,	   0x1180008000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX0_RX_BP_DROP001"          ,	   0x1180008000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX0_RX_BP_DROP002"          ,	   0x1180008000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX0_RX_BP_DROP003"          ,	   0x1180008000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX1_RX_BP_DROP000"          ,	   0x1180009000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX1_RX_BP_DROP001"          ,	   0x1180009000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX1_RX_BP_DROP002"          ,	   0x1180009000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX1_RX_BP_DROP003"          ,	   0x1180009000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX2_RX_BP_DROP000"          ,	   0x118000a000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX2_RX_BP_DROP001"          ,	   0x118000a000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX2_RX_BP_DROP002"          ,	   0x118000a000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX2_RX_BP_DROP003"          ,	   0x118000a000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX3_RX_BP_DROP000"          ,	   0x118000b000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX3_RX_BP_DROP001"          ,	   0x118000b000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX3_RX_BP_DROP002"          ,	   0x118000b000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX3_RX_BP_DROP003"          ,	   0x118000b000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX4_RX_BP_DROP000"          ,	   0x118000c000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX4_RX_BP_DROP001"          ,	   0x118000c000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX4_RX_BP_DROP002"          ,	   0x118000c000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX4_RX_BP_DROP003"          ,	   0x118000c000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX0_RX_BP_OFF000"           ,	   0x1180008000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX0_RX_BP_OFF001"           ,	   0x1180008000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX0_RX_BP_OFF002"           ,	   0x1180008000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX0_RX_BP_OFF003"           ,	   0x1180008000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX1_RX_BP_OFF000"           ,	   0x1180009000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX1_RX_BP_OFF001"           ,	   0x1180009000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX1_RX_BP_OFF002"           ,	   0x1180009000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX1_RX_BP_OFF003"           ,	   0x1180009000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX2_RX_BP_OFF000"           ,	   0x118000a000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX2_RX_BP_OFF001"           ,	   0x118000a000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX2_RX_BP_OFF002"           ,	   0x118000a000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX2_RX_BP_OFF003"           ,	   0x118000a000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX3_RX_BP_OFF000"           ,	   0x118000b000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX3_RX_BP_OFF001"           ,	   0x118000b000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX3_RX_BP_OFF002"           ,	   0x118000b000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX3_RX_BP_OFF003"           ,	   0x118000b000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX4_RX_BP_OFF000"           ,	   0x118000c000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX4_RX_BP_OFF001"           ,	   0x118000c000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX4_RX_BP_OFF002"           ,	   0x118000c000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX4_RX_BP_OFF003"           ,	   0x118000c000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX0_RX_BP_ON003"            ,	   0x1180008000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX1_RX_BP_ON000"            ,	   0x1180009000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX1_RX_BP_ON001"            ,	   0x1180009000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX1_RX_BP_ON002"            ,	   0x1180009000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX1_RX_BP_ON003"            ,	   0x1180009000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX2_RX_BP_ON000"            ,	   0x118000a000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX2_RX_BP_ON001"            ,	   0x118000a000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX2_RX_BP_ON002"            ,	   0x118000a000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX2_RX_BP_ON003"            ,	   0x118000a000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX3_RX_BP_ON000"            ,	   0x118000b000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX3_RX_BP_ON001"            ,	   0x118000b000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX3_RX_BP_ON002"            ,	   0x118000b000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX3_RX_BP_ON003"            ,	   0x118000b000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX4_RX_BP_ON000"            ,	   0x118000c000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX4_RX_BP_ON001"            ,	   0x118000c000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX4_RX_BP_ON002"            ,	   0x118000c000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX4_RX_BP_ON003"            ,	   0x118000c000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX0_RX_HG2_STATUS"          ,	   0x1180008000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX1_RX_HG2_STATUS"          ,	   0x1180009000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX2_RX_HG2_STATUS"          ,	   0x118000a000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX3_RX_HG2_STATUS"          ,	   0x118000b000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX4_RX_HG2_STATUS"          ,	   0x118000c000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX1_RX_PRT_INFO"            ,	   0x11800090004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX2_RX_PRT_INFO"            ,	   0x118000a0004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX3_RX_PRT_INFO"            ,	   0x118000b0004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX4_RX_PRT_INFO"            ,	   0x118000c0004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX1_RX_PRTS"                ,	   0x1180009000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX2_RX_PRTS"                ,	   0x118000a000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX3_RX_PRTS"                ,	   0x118000b000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX4_RX_PRTS"                ,	   0x118000c000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX0_RX_XAUI_BAD_COL"        ,	   0x1180008000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"GMX1_RX_XAUI_BAD_COL"        ,	   0x1180009000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"GMX2_RX_XAUI_BAD_COL"        ,	   0x118000a000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"GMX3_RX_XAUI_BAD_COL"        ,	   0x118000b000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"GMX4_RX_XAUI_BAD_COL"        ,	   0x118000c000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"GMX0_RX_XAUI_CTL"            ,	   0x1180008000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"GMX1_RX_XAUI_CTL"            ,	   0x1180009000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"GMX2_RX_XAUI_CTL"            ,	   0x118000a000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"GMX3_RX_XAUI_CTL"            ,	   0x118000b000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"GMX4_RX_XAUI_CTL"            ,	   0x118000c000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"GMX0_RXAUI_CTL"              ,	   0x1180008000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"GMX1_RXAUI_CTL"              ,	   0x1180009000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"GMX2_RXAUI_CTL"              ,	   0x118000a000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"GMX3_RXAUI_CTL"              ,	   0x118000b000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"GMX4_RXAUI_CTL"              ,	   0x118000c000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX0_SMAC001"                ,	   0x1180008000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX0_SMAC003"                ,	   0x1180008001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX1_SMAC000"                ,	   0x1180009000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX1_SMAC001"                ,	   0x1180009000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX1_SMAC002"                ,	   0x1180009001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX1_SMAC003"                ,	   0x1180009001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX2_SMAC000"                ,	   0x118000a000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX2_SMAC001"                ,	   0x118000a000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX2_SMAC002"                ,	   0x118000a001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX2_SMAC003"                ,	   0x118000a001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX3_SMAC000"                ,	   0x118000b000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX3_SMAC001"                ,	   0x118000b000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX3_SMAC002"                ,	   0x118000b001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX3_SMAC003"                ,	   0x118000b001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX4_SMAC000"                ,	   0x118000c000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX4_SMAC001"                ,	   0x118000c000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX4_SMAC002"                ,	   0x118000c001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX4_SMAC003"                ,	   0x118000c001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX0_SOFT_BIST"              ,	   0x11800080007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"GMX1_SOFT_BIST"              ,	   0x11800090007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"GMX2_SOFT_BIST"              ,	   0x118000a0007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"GMX3_SOFT_BIST"              ,	   0x118000b0007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"GMX4_SOFT_BIST"              ,	   0x118000c0007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"GMX1_STAT_BP"                ,	   0x1180009000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"GMX2_STAT_BP"                ,	   0x118000a000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"GMX3_STAT_BP"                ,	   0x118000b000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"GMX4_STAT_BP"                ,	   0x118000c000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX1_TX000_APPEND"           ,	   0x1180009000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX1_TX001_APPEND"           ,	   0x1180009000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX1_TX002_APPEND"           ,	   0x1180009001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX1_TX003_APPEND"           ,	   0x1180009001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX2_TX000_APPEND"           ,	   0x118000a000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX2_TX001_APPEND"           ,	   0x118000a000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX2_TX002_APPEND"           ,	   0x118000a001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX2_TX003_APPEND"           ,	   0x118000a001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX3_TX000_APPEND"           ,	   0x118000b000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX3_TX001_APPEND"           ,	   0x118000b000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX3_TX002_APPEND"           ,	   0x118000b001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX3_TX003_APPEND"           ,	   0x118000b001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX4_TX000_APPEND"           ,	   0x118000c000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX4_TX001_APPEND"           ,	   0x118000c000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX4_TX002_APPEND"           ,	   0x118000c001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX4_TX003_APPEND"           ,	   0x118000c001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX1_TX000_BURST"            ,	   0x1180009000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX1_TX001_BURST"            ,	   0x1180009000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX1_TX002_BURST"            ,	   0x1180009001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX1_TX003_BURST"            ,	   0x1180009001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX2_TX000_BURST"            ,	   0x118000a000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX2_TX001_BURST"            ,	   0x118000a000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX2_TX002_BURST"            ,	   0x118000a001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX2_TX003_BURST"            ,	   0x118000a001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX3_TX000_BURST"            ,	   0x118000b000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX3_TX001_BURST"            ,	   0x118000b000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX3_TX002_BURST"            ,	   0x118000b001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX3_TX003_BURST"            ,	   0x118000b001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX4_TX000_BURST"            ,	   0x118000c000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX4_TX001_BURST"            ,	   0x118000c000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX4_TX002_BURST"            ,	   0x118000c001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX4_TX003_BURST"            ,	   0x118000c001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX0_TX000_CBFC_XOFF"        ,	   0x11800080005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"GMX1_TX000_CBFC_XOFF"        ,	   0x11800090005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"GMX2_TX000_CBFC_XOFF"        ,	   0x118000a0005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"GMX3_TX000_CBFC_XOFF"        ,	   0x118000b0005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"GMX4_TX000_CBFC_XOFF"        ,	   0x118000c0005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"GMX0_TX000_CBFC_XON"         ,	   0x11800080005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"GMX1_TX000_CBFC_XON"         ,	   0x11800090005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"GMX2_TX000_CBFC_XON"         ,	   0x118000a0005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"GMX3_TX000_CBFC_XON"         ,	   0x118000b0005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"GMX4_TX000_CBFC_XON"         ,	   0x118000c0005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX1_TX000_CTL"              ,	   0x1180009000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX1_TX001_CTL"              ,	   0x1180009000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX1_TX002_CTL"              ,	   0x1180009001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX1_TX003_CTL"              ,	   0x1180009001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX2_TX000_CTL"              ,	   0x118000a000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX2_TX001_CTL"              ,	   0x118000a000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX2_TX002_CTL"              ,	   0x118000a001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX2_TX003_CTL"              ,	   0x118000a001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX3_TX000_CTL"              ,	   0x118000b000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX3_TX001_CTL"              ,	   0x118000b000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX3_TX002_CTL"              ,	   0x118000b001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX3_TX003_CTL"              ,	   0x118000b001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX4_TX000_CTL"              ,	   0x118000c000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX4_TX001_CTL"              ,	   0x118000c000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX4_TX002_CTL"              ,	   0x118000c001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX4_TX003_CTL"              ,	   0x118000c001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX1_TX000_MIN_PKT"          ,	   0x1180009000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX1_TX001_MIN_PKT"          ,	   0x1180009000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX1_TX002_MIN_PKT"          ,	   0x1180009001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX1_TX003_MIN_PKT"          ,	   0x1180009001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX2_TX000_MIN_PKT"          ,	   0x118000a000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX2_TX001_MIN_PKT"          ,	   0x118000a000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX2_TX002_MIN_PKT"          ,	   0x118000a001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX2_TX003_MIN_PKT"          ,	   0x118000a001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX3_TX000_MIN_PKT"          ,	   0x118000b000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX3_TX001_MIN_PKT"          ,	   0x118000b000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX3_TX002_MIN_PKT"          ,	   0x118000b001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX3_TX003_MIN_PKT"          ,	   0x118000b001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX4_TX000_MIN_PKT"          ,	   0x118000c000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX4_TX001_MIN_PKT"          ,	   0x118000c000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX4_TX002_MIN_PKT"          ,	   0x118000c001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX4_TX003_MIN_PKT"          ,	   0x118000c001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX1_TX000_PAUSE_PKT_INTERVAL",	   0x1180009000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180009000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX1_TX002_PAUSE_PKT_INTERVAL",	   0x1180009001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180009001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX2_TX000_PAUSE_PKT_INTERVAL",	   0x118000a000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX2_TX001_PAUSE_PKT_INTERVAL",	   0x118000a000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX2_TX002_PAUSE_PKT_INTERVAL",	   0x118000a001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX2_TX003_PAUSE_PKT_INTERVAL",	   0x118000a001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX3_TX000_PAUSE_PKT_INTERVAL",	   0x118000b000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX3_TX001_PAUSE_PKT_INTERVAL",	   0x118000b000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX3_TX002_PAUSE_PKT_INTERVAL",	   0x118000b001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX3_TX003_PAUSE_PKT_INTERVAL",	   0x118000b001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX4_TX000_PAUSE_PKT_INTERVAL",	   0x118000c000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX4_TX001_PAUSE_PKT_INTERVAL",	   0x118000c000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX4_TX002_PAUSE_PKT_INTERVAL",	   0x118000c001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX4_TX003_PAUSE_PKT_INTERVAL",	   0x118000c001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX1_TX000_PAUSE_PKT_TIME"   ,	   0x1180009000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180009000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX1_TX002_PAUSE_PKT_TIME"   ,	   0x1180009001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180009001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX2_TX000_PAUSE_PKT_TIME"   ,	   0x118000a000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX2_TX001_PAUSE_PKT_TIME"   ,	   0x118000a000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX2_TX002_PAUSE_PKT_TIME"   ,	   0x118000a001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX2_TX003_PAUSE_PKT_TIME"   ,	   0x118000a001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX3_TX000_PAUSE_PKT_TIME"   ,	   0x118000b000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX3_TX001_PAUSE_PKT_TIME"   ,	   0x118000b000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX3_TX002_PAUSE_PKT_TIME"   ,	   0x118000b001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX3_TX003_PAUSE_PKT_TIME"   ,	   0x118000b001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX4_TX000_PAUSE_PKT_TIME"   ,	   0x118000c000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX4_TX001_PAUSE_PKT_TIME"   ,	   0x118000c000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX4_TX002_PAUSE_PKT_TIME"   ,	   0x118000c001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX4_TX003_PAUSE_PKT_TIME"   ,	   0x118000c001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX1_TX000_PAUSE_TOGO"       ,	   0x1180009000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180009000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX1_TX002_PAUSE_TOGO"       ,	   0x1180009001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180009001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX2_TX000_PAUSE_TOGO"       ,	   0x118000a000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX2_TX001_PAUSE_TOGO"       ,	   0x118000a000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX2_TX002_PAUSE_TOGO"       ,	   0x118000a001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX2_TX003_PAUSE_TOGO"       ,	   0x118000a001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX3_TX000_PAUSE_TOGO"       ,	   0x118000b000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX3_TX001_PAUSE_TOGO"       ,	   0x118000b000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX3_TX002_PAUSE_TOGO"       ,	   0x118000b001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX3_TX003_PAUSE_TOGO"       ,	   0x118000b001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX4_TX000_PAUSE_TOGO"       ,	   0x118000c000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX4_TX001_PAUSE_TOGO"       ,	   0x118000c000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX4_TX002_PAUSE_TOGO"       ,	   0x118000c001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX4_TX003_PAUSE_TOGO"       ,	   0x118000c001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX1_TX000_PAUSE_ZERO"       ,	   0x1180009000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180009000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX1_TX002_PAUSE_ZERO"       ,	   0x1180009001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180009001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX2_TX000_PAUSE_ZERO"       ,	   0x118000a000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX2_TX001_PAUSE_ZERO"       ,	   0x118000a000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX2_TX002_PAUSE_ZERO"       ,	   0x118000a001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX2_TX003_PAUSE_ZERO"       ,	   0x118000a001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX3_TX000_PAUSE_ZERO"       ,	   0x118000b000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX3_TX001_PAUSE_ZERO"       ,	   0x118000b000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX3_TX002_PAUSE_ZERO"       ,	   0x118000b001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX3_TX003_PAUSE_ZERO"       ,	   0x118000b001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX4_TX000_PAUSE_ZERO"       ,	   0x118000c000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX4_TX001_PAUSE_ZERO"       ,	   0x118000c000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX4_TX002_PAUSE_ZERO"       ,	   0x118000c001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX4_TX003_PAUSE_ZERO"       ,	   0x118000c001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX0_TX000_PIPE"             ,	   0x1180008000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX0_TX001_PIPE"             ,	   0x1180008000b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX0_TX002_PIPE"             ,	   0x1180008001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX0_TX003_PIPE"             ,	   0x1180008001b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX1_TX000_PIPE"             ,	   0x1180009000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX1_TX001_PIPE"             ,	   0x1180009000b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX1_TX002_PIPE"             ,	   0x1180009001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX1_TX003_PIPE"             ,	   0x1180009001b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX2_TX000_PIPE"             ,	   0x118000a000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX2_TX001_PIPE"             ,	   0x118000a000b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX2_TX002_PIPE"             ,	   0x118000a001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX2_TX003_PIPE"             ,	   0x118000a001b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX3_TX000_PIPE"             ,	   0x118000b000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX3_TX001_PIPE"             ,	   0x118000b000b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX3_TX002_PIPE"             ,	   0x118000b001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX3_TX003_PIPE"             ,	   0x118000b001b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX4_TX000_PIPE"             ,	   0x118000c000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX4_TX001_PIPE"             ,	   0x118000c000b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX4_TX002_PIPE"             ,	   0x118000c001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX4_TX003_PIPE"             ,	   0x118000c001b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX0_TX000_SGMII_CTL"        ,	   0x1180008000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX0_TX002_SGMII_CTL"        ,	   0x1180008001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX0_TX003_SGMII_CTL"        ,	   0x1180008001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX1_TX000_SGMII_CTL"        ,	   0x1180009000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX1_TX001_SGMII_CTL"        ,	   0x1180009000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX1_TX002_SGMII_CTL"        ,	   0x1180009001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX1_TX003_SGMII_CTL"        ,	   0x1180009001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX2_TX000_SGMII_CTL"        ,	   0x118000a000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX2_TX001_SGMII_CTL"        ,	   0x118000a000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX2_TX002_SGMII_CTL"        ,	   0x118000a001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX2_TX003_SGMII_CTL"        ,	   0x118000a001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX3_TX000_SGMII_CTL"        ,	   0x118000b000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX3_TX001_SGMII_CTL"        ,	   0x118000b000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX3_TX002_SGMII_CTL"        ,	   0x118000b001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX3_TX003_SGMII_CTL"        ,	   0x118000b001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX4_TX000_SGMII_CTL"        ,	   0x118000c000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX4_TX001_SGMII_CTL"        ,	   0x118000c000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX4_TX002_SGMII_CTL"        ,	   0x118000c001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX4_TX003_SGMII_CTL"        ,	   0x118000c001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX1_TX000_SLOT"             ,	   0x1180009000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX1_TX001_SLOT"             ,	   0x1180009000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX1_TX002_SLOT"             ,	   0x1180009001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX1_TX003_SLOT"             ,	   0x1180009001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX2_TX000_SLOT"             ,	   0x118000a000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX2_TX001_SLOT"             ,	   0x118000a000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX2_TX002_SLOT"             ,	   0x118000a001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX2_TX003_SLOT"             ,	   0x118000a001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX3_TX000_SLOT"             ,	   0x118000b000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX3_TX001_SLOT"             ,	   0x118000b000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX3_TX002_SLOT"             ,	   0x118000b001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX3_TX003_SLOT"             ,	   0x118000b001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX4_TX000_SLOT"             ,	   0x118000c000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX4_TX001_SLOT"             ,	   0x118000c000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX4_TX002_SLOT"             ,	   0x118000c001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX4_TX003_SLOT"             ,	   0x118000c001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX1_TX000_SOFT_PAUSE"       ,	   0x1180009000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180009000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX1_TX002_SOFT_PAUSE"       ,	   0x1180009001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180009001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX2_TX000_SOFT_PAUSE"       ,	   0x118000a000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX2_TX001_SOFT_PAUSE"       ,	   0x118000a000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX2_TX002_SOFT_PAUSE"       ,	   0x118000a001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX2_TX003_SOFT_PAUSE"       ,	   0x118000a001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX3_TX000_SOFT_PAUSE"       ,	   0x118000b000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX3_TX001_SOFT_PAUSE"       ,	   0x118000b000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX3_TX002_SOFT_PAUSE"       ,	   0x118000b001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX3_TX003_SOFT_PAUSE"       ,	   0x118000b001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX4_TX000_SOFT_PAUSE"       ,	   0x118000c000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX4_TX001_SOFT_PAUSE"       ,	   0x118000c000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX4_TX002_SOFT_PAUSE"       ,	   0x118000c001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX4_TX003_SOFT_PAUSE"       ,	   0x118000c001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX1_TX000_STAT0"            ,	   0x1180009000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX1_TX001_STAT0"            ,	   0x1180009000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX1_TX002_STAT0"            ,	   0x1180009001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX1_TX003_STAT0"            ,	   0x1180009001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX2_TX000_STAT0"            ,	   0x118000a000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX2_TX001_STAT0"            ,	   0x118000a000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX2_TX002_STAT0"            ,	   0x118000a001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX2_TX003_STAT0"            ,	   0x118000a001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX3_TX000_STAT0"            ,	   0x118000b000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX3_TX001_STAT0"            ,	   0x118000b000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX3_TX002_STAT0"            ,	   0x118000b001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX3_TX003_STAT0"            ,	   0x118000b001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX4_TX000_STAT0"            ,	   0x118000c000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX4_TX001_STAT0"            ,	   0x118000c000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX4_TX002_STAT0"            ,	   0x118000c001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX4_TX003_STAT0"            ,	   0x118000c001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX1_TX000_STAT1"            ,	   0x1180009000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX1_TX001_STAT1"            ,	   0x1180009000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX1_TX002_STAT1"            ,	   0x1180009001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX1_TX003_STAT1"            ,	   0x1180009001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX2_TX000_STAT1"            ,	   0x118000a000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX2_TX001_STAT1"            ,	   0x118000a000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX2_TX002_STAT1"            ,	   0x118000a001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX2_TX003_STAT1"            ,	   0x118000a001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX3_TX000_STAT1"            ,	   0x118000b000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX3_TX001_STAT1"            ,	   0x118000b000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX3_TX002_STAT1"            ,	   0x118000b001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX3_TX003_STAT1"            ,	   0x118000b001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX4_TX000_STAT1"            ,	   0x118000c000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX4_TX001_STAT1"            ,	   0x118000c000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX4_TX002_STAT1"            ,	   0x118000c001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX4_TX003_STAT1"            ,	   0x118000c001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX1_TX000_STAT2"            ,	   0x1180009000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX1_TX001_STAT2"            ,	   0x1180009000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX1_TX002_STAT2"            ,	   0x1180009001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX1_TX003_STAT2"            ,	   0x1180009001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX2_TX000_STAT2"            ,	   0x118000a000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX2_TX001_STAT2"            ,	   0x118000a000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX2_TX002_STAT2"            ,	   0x118000a001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX2_TX003_STAT2"            ,	   0x118000a001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX3_TX000_STAT2"            ,	   0x118000b000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX3_TX001_STAT2"            ,	   0x118000b000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX3_TX002_STAT2"            ,	   0x118000b001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX3_TX003_STAT2"            ,	   0x118000b001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX4_TX000_STAT2"            ,	   0x118000c000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX4_TX001_STAT2"            ,	   0x118000c000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX4_TX002_STAT2"            ,	   0x118000c001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX4_TX003_STAT2"            ,	   0x118000c001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX1_TX000_STAT3"            ,	   0x1180009000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX1_TX001_STAT3"            ,	   0x1180009000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX1_TX002_STAT3"            ,	   0x1180009001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX1_TX003_STAT3"            ,	   0x1180009001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX2_TX000_STAT3"            ,	   0x118000a000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX2_TX001_STAT3"            ,	   0x118000a000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX2_TX002_STAT3"            ,	   0x118000a001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX2_TX003_STAT3"            ,	   0x118000a001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX3_TX000_STAT3"            ,	   0x118000b000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX3_TX001_STAT3"            ,	   0x118000b000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX3_TX002_STAT3"            ,	   0x118000b001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX3_TX003_STAT3"            ,	   0x118000b001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX4_TX000_STAT3"            ,	   0x118000c000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX4_TX001_STAT3"            ,	   0x118000c000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX4_TX002_STAT3"            ,	   0x118000c001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX4_TX003_STAT3"            ,	   0x118000c001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX1_TX000_STAT4"            ,	   0x11800090002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX1_TX001_STAT4"            ,	   0x1180009000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX1_TX002_STAT4"            ,	   0x11800090012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX1_TX003_STAT4"            ,	   0x1180009001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX2_TX000_STAT4"            ,	   0x118000a0002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX2_TX001_STAT4"            ,	   0x118000a000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX2_TX002_STAT4"            ,	   0x118000a0012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX2_TX003_STAT4"            ,	   0x118000a001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX3_TX000_STAT4"            ,	   0x118000b0002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX3_TX001_STAT4"            ,	   0x118000b000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX3_TX002_STAT4"            ,	   0x118000b0012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX3_TX003_STAT4"            ,	   0x118000b001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX4_TX000_STAT4"            ,	   0x118000c0002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX4_TX001_STAT4"            ,	   0x118000c000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX4_TX002_STAT4"            ,	   0x118000c0012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX4_TX003_STAT4"            ,	   0x118000c001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX1_TX000_STAT5"            ,	   0x11800090002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX1_TX001_STAT5"            ,	   0x1180009000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX1_TX002_STAT5"            ,	   0x11800090012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX1_TX003_STAT5"            ,	   0x1180009001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX2_TX000_STAT5"            ,	   0x118000a0002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX2_TX001_STAT5"            ,	   0x118000a000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX2_TX002_STAT5"            ,	   0x118000a0012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX2_TX003_STAT5"            ,	   0x118000a001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX3_TX000_STAT5"            ,	   0x118000b0002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX3_TX001_STAT5"            ,	   0x118000b000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX3_TX002_STAT5"            ,	   0x118000b0012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX3_TX003_STAT5"            ,	   0x118000b001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX4_TX000_STAT5"            ,	   0x118000c0002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX4_TX001_STAT5"            ,	   0x118000c000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX4_TX002_STAT5"            ,	   0x118000c0012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX4_TX003_STAT5"            ,	   0x118000c001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX1_TX000_STAT6"            ,	   0x11800090002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX1_TX001_STAT6"            ,	   0x1180009000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX1_TX002_STAT6"            ,	   0x11800090012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX1_TX003_STAT6"            ,	   0x1180009001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX2_TX000_STAT6"            ,	   0x118000a0002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX2_TX001_STAT6"            ,	   0x118000a000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX2_TX002_STAT6"            ,	   0x118000a0012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX2_TX003_STAT6"            ,	   0x118000a001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX3_TX000_STAT6"            ,	   0x118000b0002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX3_TX001_STAT6"            ,	   0x118000b000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX3_TX002_STAT6"            ,	   0x118000b0012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX3_TX003_STAT6"            ,	   0x118000b001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX4_TX000_STAT6"            ,	   0x118000c0002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX4_TX001_STAT6"            ,	   0x118000c000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX4_TX002_STAT6"            ,	   0x118000c0012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX4_TX003_STAT6"            ,	   0x118000c001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX1_TX000_STAT7"            ,	   0x11800090002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX1_TX001_STAT7"            ,	   0x1180009000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX1_TX002_STAT7"            ,	   0x11800090012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX1_TX003_STAT7"            ,	   0x1180009001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX2_TX000_STAT7"            ,	   0x118000a0002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX2_TX001_STAT7"            ,	   0x118000a000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX2_TX002_STAT7"            ,	   0x118000a0012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX2_TX003_STAT7"            ,	   0x118000a001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX3_TX000_STAT7"            ,	   0x118000b0002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX3_TX001_STAT7"            ,	   0x118000b000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX3_TX002_STAT7"            ,	   0x118000b0012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX3_TX003_STAT7"            ,	   0x118000b001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX4_TX000_STAT7"            ,	   0x118000c0002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX4_TX001_STAT7"            ,	   0x118000c000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX4_TX002_STAT7"            ,	   0x118000c0012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX4_TX003_STAT7"            ,	   0x118000c001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX1_TX000_STAT8"            ,	   0x11800090002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX1_TX001_STAT8"            ,	   0x1180009000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX1_TX002_STAT8"            ,	   0x11800090012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX1_TX003_STAT8"            ,	   0x1180009001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX2_TX000_STAT8"            ,	   0x118000a0002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX2_TX001_STAT8"            ,	   0x118000a000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX2_TX002_STAT8"            ,	   0x118000a0012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX2_TX003_STAT8"            ,	   0x118000a001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX3_TX000_STAT8"            ,	   0x118000b0002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX3_TX001_STAT8"            ,	   0x118000b000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX3_TX002_STAT8"            ,	   0x118000b0012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX3_TX003_STAT8"            ,	   0x118000b001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX4_TX000_STAT8"            ,	   0x118000c0002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX4_TX001_STAT8"            ,	   0x118000c000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX4_TX002_STAT8"            ,	   0x118000c0012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX4_TX003_STAT8"            ,	   0x118000c001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX1_TX000_STAT9"            ,	   0x11800090002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX1_TX001_STAT9"            ,	   0x1180009000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX1_TX002_STAT9"            ,	   0x11800090012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX1_TX003_STAT9"            ,	   0x1180009001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX2_TX000_STAT9"            ,	   0x118000a0002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX2_TX001_STAT9"            ,	   0x118000a000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX2_TX002_STAT9"            ,	   0x118000a0012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX2_TX003_STAT9"            ,	   0x118000a001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX3_TX000_STAT9"            ,	   0x118000b0002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX3_TX001_STAT9"            ,	   0x118000b000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX3_TX002_STAT9"            ,	   0x118000b0012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX3_TX003_STAT9"            ,	   0x118000b001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX4_TX000_STAT9"            ,	   0x118000c0002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX4_TX001_STAT9"            ,	   0x118000c000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX4_TX002_STAT9"            ,	   0x118000c0012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX4_TX003_STAT9"            ,	   0x118000c001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX1_TX000_STATS_CTL"        ,	   0x1180009000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX1_TX001_STATS_CTL"        ,	   0x1180009000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX1_TX002_STATS_CTL"        ,	   0x1180009001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX1_TX003_STATS_CTL"        ,	   0x1180009001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX2_TX000_STATS_CTL"        ,	   0x118000a000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX2_TX001_STATS_CTL"        ,	   0x118000a000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX2_TX002_STATS_CTL"        ,	   0x118000a001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX2_TX003_STATS_CTL"        ,	   0x118000a001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX3_TX000_STATS_CTL"        ,	   0x118000b000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX3_TX001_STATS_CTL"        ,	   0x118000b000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX3_TX002_STATS_CTL"        ,	   0x118000b001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX3_TX003_STATS_CTL"        ,	   0x118000b001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX4_TX000_STATS_CTL"        ,	   0x118000c000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX4_TX001_STATS_CTL"        ,	   0x118000c000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX4_TX002_STATS_CTL"        ,	   0x118000c001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX4_TX003_STATS_CTL"        ,	   0x118000c001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX1_TX000_THRESH"           ,	   0x1180009000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX1_TX001_THRESH"           ,	   0x1180009000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX1_TX002_THRESH"           ,	   0x1180009001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX1_TX003_THRESH"           ,	   0x1180009001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX2_TX000_THRESH"           ,	   0x118000a000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX2_TX001_THRESH"           ,	   0x118000a000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX2_TX002_THRESH"           ,	   0x118000a001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX2_TX003_THRESH"           ,	   0x118000a001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX3_TX000_THRESH"           ,	   0x118000b000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX3_TX001_THRESH"           ,	   0x118000b000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX3_TX002_THRESH"           ,	   0x118000b001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX3_TX003_THRESH"           ,	   0x118000b001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX4_TX000_THRESH"           ,	   0x118000c000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX4_TX001_THRESH"           ,	   0x118000c000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX4_TX002_THRESH"           ,	   0x118000c001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX4_TX003_THRESH"           ,	   0x118000c001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX0_TX_BP"                  ,	   0x11800080004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX1_TX_BP"                  ,	   0x11800090004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX2_TX_BP"                  ,	   0x118000a0004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX3_TX_BP"                  ,	   0x118000b0004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX4_TX_BP"                  ,	   0x118000c0004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX1_TX_COL_ATTEMPT"         ,	   0x1180009000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX2_TX_COL_ATTEMPT"         ,	   0x118000a000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX3_TX_COL_ATTEMPT"         ,	   0x118000b000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX4_TX_COL_ATTEMPT"         ,	   0x118000c000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX1_TX_CORRUPT"             ,	   0x11800090004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX2_TX_CORRUPT"             ,	   0x118000a0004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX3_TX_CORRUPT"             ,	   0x118000b0004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX4_TX_CORRUPT"             ,	   0x118000c0004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX0_TX_HG2_REG1"            ,	   0x1180008000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX1_TX_HG2_REG1"            ,	   0x1180009000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX2_TX_HG2_REG1"            ,	   0x118000a000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX3_TX_HG2_REG1"            ,	   0x118000b000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX4_TX_HG2_REG1"            ,	   0x118000c000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX0_TX_HG2_REG2"            ,	   0x1180008000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"GMX1_TX_HG2_REG2"            ,	   0x1180009000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"GMX2_TX_HG2_REG2"            ,	   0x118000a000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"GMX3_TX_HG2_REG2"            ,	   0x118000b000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"GMX4_TX_HG2_REG2"            ,	   0x118000c000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"GMX1_TX_IFG"                 ,	   0x1180009000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"GMX2_TX_IFG"                 ,	   0x118000a000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"GMX3_TX_IFG"                 ,	   0x118000b000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"GMX4_TX_IFG"                 ,	   0x118000c000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"GMX1_TX_INT_EN"              ,	   0x1180009000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"GMX2_TX_INT_EN"              ,	   0x118000a000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"GMX3_TX_INT_EN"              ,	   0x118000b000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"GMX4_TX_INT_EN"              ,	   0x118000c000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"GMX1_TX_INT_REG"             ,	   0x1180009000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"GMX2_TX_INT_REG"             ,	   0x118000a000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"GMX3_TX_INT_REG"             ,	   0x118000b000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"GMX4_TX_INT_REG"             ,	   0x118000c000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"GMX1_TX_JAM"                 ,	   0x1180009000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"GMX2_TX_JAM"                 ,	   0x118000a000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"GMX3_TX_JAM"                 ,	   0x118000b000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"GMX4_TX_JAM"                 ,	   0x118000c000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"GMX1_TX_LFSR"                ,	   0x11800090004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"GMX2_TX_LFSR"                ,	   0x118000a0004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"GMX3_TX_LFSR"                ,	   0x118000b0004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"GMX4_TX_LFSR"                ,	   0x118000c0004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"GMX1_TX_OVR_BP"              ,	   0x11800090004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"GMX2_TX_OVR_BP"              ,	   0x118000a0004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"GMX3_TX_OVR_BP"              ,	   0x118000b0004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"GMX4_TX_OVR_BP"              ,	   0x118000c0004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800090004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"GMX2_TX_PAUSE_PKT_DMAC"      ,	   0x118000a0004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"GMX3_TX_PAUSE_PKT_DMAC"      ,	   0x118000b0004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"GMX4_TX_PAUSE_PKT_DMAC"      ,	   0x118000c0004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800090004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"GMX2_TX_PAUSE_PKT_TYPE"      ,	   0x118000a0004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"GMX3_TX_PAUSE_PKT_TYPE"      ,	   0x118000b0004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"GMX4_TX_PAUSE_PKT_TYPE"      ,	   0x118000c0004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"GMX1_TX_PRTS"                ,	   0x1180009000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"GMX2_TX_PRTS"                ,	   0x118000a000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"GMX3_TX_PRTS"                ,	   0x118000b000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"GMX4_TX_PRTS"                ,	   0x118000c000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"GMX0_TX_XAUI_CTL"            ,	   0x1180008000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"GMX1_TX_XAUI_CTL"            ,	   0x1180009000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"GMX2_TX_XAUI_CTL"            ,	   0x118000a000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"GMX3_TX_XAUI_CTL"            ,	   0x118000b000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"GMX4_TX_XAUI_CTL"            ,	   0x118000c000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"GMX0_XAUI_EXT_LOOPBACK"      ,	   0x1180008000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"GMX1_XAUI_EXT_LOOPBACK"      ,	   0x1180009000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"GMX2_XAUI_EXT_LOOPBACK"      ,	   0x118000a000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"GMX3_XAUI_EXT_LOOPBACK"      ,	   0x118000b000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"GMX4_XAUI_EXT_LOOPBACK"      ,	   0x118000c000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	457},
+	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	457},
+	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	457},
+	{"GPIO_BIT_CFG3"               ,	   0x1070000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	457},
+	{"GPIO_BIT_CFG4"               ,	   0x1070000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	457},
+	{"GPIO_BIT_CFG5"               ,	   0x1070000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	457},
+	{"GPIO_BIT_CFG6"               ,	   0x1070000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	457},
+	{"GPIO_BIT_CFG7"               ,	   0x1070000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	457},
+	{"GPIO_BIT_CFG8"               ,	   0x1070000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	457},
+	{"GPIO_BIT_CFG9"               ,	   0x1070000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	457},
+	{"GPIO_BIT_CFG10"              ,	   0x1070000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	457},
+	{"GPIO_BIT_CFG11"              ,	   0x1070000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	457},
+	{"GPIO_BIT_CFG12"              ,	   0x1070000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	457},
+	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	457},
+	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	457},
+	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	457},
+	{"GPIO_CLK_GEN0"               ,	   0x10700000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	458},
+	{"GPIO_CLK_GEN1"               ,	   0x10700000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	458},
+	{"GPIO_CLK_GEN2"               ,	   0x10700000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	458},
+	{"GPIO_CLK_GEN3"               ,	   0x10700000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	458},
+	{"GPIO_CLK_QLM0"               ,	   0x10700000008e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	459},
+	{"GPIO_CLK_QLM1"               ,	   0x10700000008e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	459},
+	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	460},
+	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"GPIO_TIM_CTL"                ,	   0x10700000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
+	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	463},
+	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	464},
+	{"ILK_BIST_SUM"                ,	   0x1180014000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"ILK_GBL_CFG"                 ,	   0x1180014000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"ILK_GBL_INT"                 ,	   0x1180014000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"ILK_GBL_INT_EN"              ,	   0x1180014000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	468},
+	{"ILK_INT_SUM"                 ,	   0x1180014000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"ILK_LNE_DBG"                 ,	   0x1180014030008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"ILK_LNE_STS_MSG"             ,	   0x1180014030000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"ILK_RX0_CFG0"                ,	   0x1180014020000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"ILK_RX1_CFG0"                ,	   0x1180014024000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"ILK_RX0_CFG1"                ,	   0x1180014020008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	473},
+	{"ILK_RX1_CFG1"                ,	   0x1180014024008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	473},
+	{"ILK_RX0_FLOW_CTL0"           ,	   0x1180014020090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	474},
+	{"ILK_RX1_FLOW_CTL0"           ,	   0x1180014024090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	474},
+	{"ILK_RX0_FLOW_CTL1"           ,	   0x1180014020098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	475},
+	{"ILK_RX1_FLOW_CTL1"           ,	   0x1180014024098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	475},
+	{"ILK_RX0_IDX_CAL"             ,	   0x11800140200a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	476},
+	{"ILK_RX1_IDX_CAL"             ,	   0x11800140240a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	476},
+	{"ILK_RX0_IDX_STAT0"           ,	   0x1180014020070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	477},
+	{"ILK_RX1_IDX_STAT0"           ,	   0x1180014024070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	477},
+	{"ILK_RX0_IDX_STAT1"           ,	   0x1180014020078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	478},
+	{"ILK_RX1_IDX_STAT1"           ,	   0x1180014024078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	478},
+	{"ILK_RX0_INT"                 ,	   0x1180014020010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"ILK_RX1_INT"                 ,	   0x1180014024010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"ILK_RX0_INT_EN"              ,	   0x1180014020018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	480},
+	{"ILK_RX1_INT_EN"              ,	   0x1180014024018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	480},
+	{"ILK_RX0_JABBER"              ,	   0x11800140200b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"ILK_RX1_JABBER"              ,	   0x11800140240b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"ILK_RX0_MEM_CAL0"            ,	   0x11800140200a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	482},
+	{"ILK_RX1_MEM_CAL0"            ,	   0x11800140240a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	482},
+	{"ILK_RX0_MEM_CAL1"            ,	   0x11800140200b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	483},
+	{"ILK_RX1_MEM_CAL1"            ,	   0x11800140240b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	483},
+	{"ILK_RX0_MEM_STAT0"           ,	   0x1180014020080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	484},
+	{"ILK_RX1_MEM_STAT0"           ,	   0x1180014024080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	484},
+	{"ILK_RX0_MEM_STAT1"           ,	   0x1180014020088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	485},
+	{"ILK_RX1_MEM_STAT1"           ,	   0x1180014024088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	485},
+	{"ILK_RX0_STAT0"               ,	   0x1180014020020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	486},
+	{"ILK_RX1_STAT0"               ,	   0x1180014024020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	486},
+	{"ILK_RX0_STAT1"               ,	   0x1180014020028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	487},
+	{"ILK_RX1_STAT1"               ,	   0x1180014024028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	487},
+	{"ILK_RX0_STAT2"               ,	   0x1180014020030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	488},
+	{"ILK_RX1_STAT2"               ,	   0x1180014024030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	488},
+	{"ILK_RX0_STAT3"               ,	   0x1180014020038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	489},
+	{"ILK_RX1_STAT3"               ,	   0x1180014024038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	489},
+	{"ILK_RX0_STAT4"               ,	   0x1180014020040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	490},
+	{"ILK_RX1_STAT4"               ,	   0x1180014024040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	490},
+	{"ILK_RX0_STAT5"               ,	   0x1180014020048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
+	{"ILK_RX1_STAT5"               ,	   0x1180014024048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
+	{"ILK_RX0_STAT6"               ,	   0x1180014020050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	492},
+	{"ILK_RX1_STAT6"               ,	   0x1180014024050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	492},
+	{"ILK_RX0_STAT7"               ,	   0x1180014020058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	493},
+	{"ILK_RX1_STAT7"               ,	   0x1180014024058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	493},
+	{"ILK_RX0_STAT8"               ,	   0x1180014020060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	494},
+	{"ILK_RX1_STAT8"               ,	   0x1180014024060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	494},
+	{"ILK_RX0_STAT9"               ,	   0x1180014020068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	495},
+	{"ILK_RX1_STAT9"               ,	   0x1180014024068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	495},
+	{"ILK_RX_LNE0_CFG"             ,	   0x1180014038000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"ILK_RX_LNE1_CFG"             ,	   0x1180014038400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"ILK_RX_LNE2_CFG"             ,	   0x1180014038800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"ILK_RX_LNE3_CFG"             ,	   0x1180014038c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"ILK_RX_LNE4_CFG"             ,	   0x1180014039000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"ILK_RX_LNE5_CFG"             ,	   0x1180014039400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"ILK_RX_LNE6_CFG"             ,	   0x1180014039800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"ILK_RX_LNE7_CFG"             ,	   0x1180014039c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"ILK_RX_LNE0_INT"             ,	   0x1180014038008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"ILK_RX_LNE1_INT"             ,	   0x1180014038408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"ILK_RX_LNE2_INT"             ,	   0x1180014038808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"ILK_RX_LNE3_INT"             ,	   0x1180014038c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"ILK_RX_LNE4_INT"             ,	   0x1180014039008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"ILK_RX_LNE5_INT"             ,	   0x1180014039408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"ILK_RX_LNE6_INT"             ,	   0x1180014039808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"ILK_RX_LNE7_INT"             ,	   0x1180014039c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"ILK_RX_LNE0_INT_EN"          ,	   0x1180014038010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"ILK_RX_LNE1_INT_EN"          ,	   0x1180014038410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"ILK_RX_LNE2_INT_EN"          ,	   0x1180014038810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"ILK_RX_LNE3_INT_EN"          ,	   0x1180014038c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"ILK_RX_LNE4_INT_EN"          ,	   0x1180014039010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"ILK_RX_LNE5_INT_EN"          ,	   0x1180014039410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"ILK_RX_LNE6_INT_EN"          ,	   0x1180014039810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"ILK_RX_LNE7_INT_EN"          ,	   0x1180014039c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"ILK_RX_LNE0_STAT0"           ,	   0x1180014038018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"ILK_RX_LNE1_STAT0"           ,	   0x1180014038418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"ILK_RX_LNE2_STAT0"           ,	   0x1180014038818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"ILK_RX_LNE3_STAT0"           ,	   0x1180014038c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"ILK_RX_LNE4_STAT0"           ,	   0x1180014039018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"ILK_RX_LNE5_STAT0"           ,	   0x1180014039418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"ILK_RX_LNE6_STAT0"           ,	   0x1180014039818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"ILK_RX_LNE7_STAT0"           ,	   0x1180014039c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"ILK_RX_LNE0_STAT1"           ,	   0x1180014038020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"ILK_RX_LNE1_STAT1"           ,	   0x1180014038420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"ILK_RX_LNE2_STAT1"           ,	   0x1180014038820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"ILK_RX_LNE3_STAT1"           ,	   0x1180014038c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"ILK_RX_LNE4_STAT1"           ,	   0x1180014039020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"ILK_RX_LNE5_STAT1"           ,	   0x1180014039420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"ILK_RX_LNE6_STAT1"           ,	   0x1180014039820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"ILK_RX_LNE7_STAT1"           ,	   0x1180014039c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"ILK_RX_LNE0_STAT2"           ,	   0x1180014038028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"ILK_RX_LNE1_STAT2"           ,	   0x1180014038428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"ILK_RX_LNE2_STAT2"           ,	   0x1180014038828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"ILK_RX_LNE3_STAT2"           ,	   0x1180014038c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"ILK_RX_LNE4_STAT2"           ,	   0x1180014039028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"ILK_RX_LNE5_STAT2"           ,	   0x1180014039428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"ILK_RX_LNE6_STAT2"           ,	   0x1180014039828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"ILK_RX_LNE7_STAT2"           ,	   0x1180014039c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"ILK_RX_LNE0_STAT3"           ,	   0x1180014038030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"ILK_RX_LNE1_STAT3"           ,	   0x1180014038430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"ILK_RX_LNE2_STAT3"           ,	   0x1180014038830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"ILK_RX_LNE3_STAT3"           ,	   0x1180014038c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"ILK_RX_LNE4_STAT3"           ,	   0x1180014039030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"ILK_RX_LNE5_STAT3"           ,	   0x1180014039430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"ILK_RX_LNE6_STAT3"           ,	   0x1180014039830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"ILK_RX_LNE7_STAT3"           ,	   0x1180014039c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"ILK_RX_LNE0_STAT4"           ,	   0x1180014038038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"ILK_RX_LNE1_STAT4"           ,	   0x1180014038438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"ILK_RX_LNE2_STAT4"           ,	   0x1180014038838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"ILK_RX_LNE3_STAT4"           ,	   0x1180014038c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"ILK_RX_LNE4_STAT4"           ,	   0x1180014039038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"ILK_RX_LNE5_STAT4"           ,	   0x1180014039438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"ILK_RX_LNE6_STAT4"           ,	   0x1180014039838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"ILK_RX_LNE7_STAT4"           ,	   0x1180014039c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"ILK_RX_LNE0_STAT5"           ,	   0x1180014038040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"ILK_RX_LNE1_STAT5"           ,	   0x1180014038440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"ILK_RX_LNE2_STAT5"           ,	   0x1180014038840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"ILK_RX_LNE3_STAT5"           ,	   0x1180014038c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"ILK_RX_LNE4_STAT5"           ,	   0x1180014039040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"ILK_RX_LNE5_STAT5"           ,	   0x1180014039440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"ILK_RX_LNE6_STAT5"           ,	   0x1180014039840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"ILK_RX_LNE7_STAT5"           ,	   0x1180014039c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"ILK_RX_LNE0_STAT6"           ,	   0x1180014038048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"ILK_RX_LNE1_STAT6"           ,	   0x1180014038448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"ILK_RX_LNE2_STAT6"           ,	   0x1180014038848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"ILK_RX_LNE3_STAT6"           ,	   0x1180014038c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"ILK_RX_LNE4_STAT6"           ,	   0x1180014039048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"ILK_RX_LNE5_STAT6"           ,	   0x1180014039448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"ILK_RX_LNE6_STAT6"           ,	   0x1180014039848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"ILK_RX_LNE7_STAT6"           ,	   0x1180014039c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"ILK_RX_LNE0_STAT7"           ,	   0x1180014038050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"ILK_RX_LNE1_STAT7"           ,	   0x1180014038450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"ILK_RX_LNE2_STAT7"           ,	   0x1180014038850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"ILK_RX_LNE3_STAT7"           ,	   0x1180014038c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"ILK_RX_LNE4_STAT7"           ,	   0x1180014039050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"ILK_RX_LNE5_STAT7"           ,	   0x1180014039450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"ILK_RX_LNE6_STAT7"           ,	   0x1180014039850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"ILK_RX_LNE7_STAT7"           ,	   0x1180014039c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"ILK_RX_LNE0_STAT8"           ,	   0x1180014038058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"ILK_RX_LNE1_STAT8"           ,	   0x1180014038458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"ILK_RX_LNE2_STAT8"           ,	   0x1180014038858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"ILK_RX_LNE3_STAT8"           ,	   0x1180014038c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"ILK_RX_LNE4_STAT8"           ,	   0x1180014039058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"ILK_RX_LNE5_STAT8"           ,	   0x1180014039458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"ILK_RX_LNE6_STAT8"           ,	   0x1180014039858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"ILK_RX_LNE7_STAT8"           ,	   0x1180014039c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"ILK_RX_LNE0_STAT9"           ,	   0x1180014038060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"ILK_RX_LNE1_STAT9"           ,	   0x1180014038460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"ILK_RX_LNE2_STAT9"           ,	   0x1180014038860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"ILK_RX_LNE3_STAT9"           ,	   0x1180014038c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"ILK_RX_LNE4_STAT9"           ,	   0x1180014039060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"ILK_RX_LNE5_STAT9"           ,	   0x1180014039460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"ILK_RX_LNE6_STAT9"           ,	   0x1180014039860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"ILK_RX_LNE7_STAT9"           ,	   0x1180014039c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"ILK_RXF_IDX_PMAP"            ,	   0x1180014000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"ILK_RXF_MEM_PMAP"            ,	   0x1180014000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"ILK_SER_CFG"                 ,	   0x1180014000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"ILK_TX0_CFG0"                ,	   0x1180014010000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"ILK_TX1_CFG0"                ,	   0x1180014014000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"ILK_TX0_CFG1"                ,	   0x1180014010008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"ILK_TX1_CFG1"                ,	   0x1180014014008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"ILK_TX0_DBG"                 ,	   0x1180014010070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"ILK_TX1_DBG"                 ,	   0x1180014014070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"ILK_TX0_FLOW_CTL0"           ,	   0x1180014010048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
+	{"ILK_TX1_FLOW_CTL0"           ,	   0x1180014014048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
+	{"ILK_TX0_FLOW_CTL1"           ,	   0x1180014010050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	516},
+	{"ILK_TX1_FLOW_CTL1"           ,	   0x1180014014050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	516},
+	{"ILK_TX0_IDX_CAL"             ,	   0x1180014010058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	517},
+	{"ILK_TX1_IDX_CAL"             ,	   0x1180014014058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	517},
+	{"ILK_TX0_IDX_PMAP"            ,	   0x1180014010010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	518},
+	{"ILK_TX1_IDX_PMAP"            ,	   0x1180014014010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	518},
+	{"ILK_TX0_IDX_STAT0"           ,	   0x1180014010020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
+	{"ILK_TX1_IDX_STAT0"           ,	   0x1180014014020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
+	{"ILK_TX0_IDX_STAT1"           ,	   0x1180014010028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
+	{"ILK_TX1_IDX_STAT1"           ,	   0x1180014014028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
+	{"ILK_TX0_INT"                 ,	   0x1180014010078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"ILK_TX1_INT"                 ,	   0x1180014014078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"ILK_TX0_INT_EN"              ,	   0x1180014010080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
+	{"ILK_TX1_INT_EN"              ,	   0x1180014014080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
+	{"ILK_TX0_MEM_CAL0"            ,	   0x1180014010060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
+	{"ILK_TX1_MEM_CAL0"            ,	   0x1180014014060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
+	{"ILK_TX0_MEM_CAL1"            ,	   0x1180014010068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
+	{"ILK_TX1_MEM_CAL1"            ,	   0x1180014014068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
+	{"ILK_TX0_MEM_PMAP"            ,	   0x1180014010018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
+	{"ILK_TX1_MEM_PMAP"            ,	   0x1180014014018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
+	{"ILK_TX0_MEM_STAT0"           ,	   0x1180014010030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
+	{"ILK_TX1_MEM_STAT0"           ,	   0x1180014014030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
+	{"ILK_TX0_MEM_STAT1"           ,	   0x1180014010038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	527},
+	{"ILK_TX1_MEM_STAT1"           ,	   0x1180014014038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	527},
+	{"ILK_TX0_PIPE"                ,	   0x1180014010088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
+	{"ILK_TX1_PIPE"                ,	   0x1180014014088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
+	{"ILK_TX0_RMATCH"              ,	   0x1180014010040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	529},
+	{"ILK_TX1_RMATCH"              ,	   0x1180014014040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	529},
+	{"IOB1_BIST_STATUS"            ,	   0x11800f00107f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
+	{"IOB1_CTL_STATUS"             ,	   0x11800f0010050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	531},
+	{"IOB1_TO_CMB_CREDITS"         ,	   0x11800f00100b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"IOB_BIST_STATUS"             ,	   0x11800f00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	533},
+	{"IOB_CTL_STATUS"              ,	   0x11800f0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	534},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800f0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	535},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800f0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	536},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800f0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	537},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800f0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	538},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800f0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	539},
+	{"IOB_INT_ENB"                 ,	   0x11800f0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
+	{"IOB_INT_SUM"                 ,	   0x11800f0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800f0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	542},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800f0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	543},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800f00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	544},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800f0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800f00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800f0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800f0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	548},
+	{"IOB_TO_CMB_CREDITS"          ,	   0x11800f00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	549},
+	{"IOB_TO_NCB_DID_00_CREDITS"   ,	   0x11800f0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	550},
+	{"IOB_TO_NCB_DID_111_CREDITS"  ,	   0x11800f0000b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	551},
+	{"IOB_TO_NCB_DID_223_CREDITS"  ,	   0x11800f0000ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	552},
+	{"IOB_TO_NCB_DID_24_CREDITS"   ,	   0x11800f00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
+	{"IOB_TO_NCB_DID_32_CREDITS"   ,	   0x11800f0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
+	{"IOB_TO_NCB_DID_40_CREDITS"   ,	   0x11800f0000940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"IOB_TO_NCB_DID_55_CREDITS"   ,	   0x11800f00009b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
+	{"IOB_TO_NCB_DID_64_CREDITS"   ,	   0x11800f0000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
+	{"IOB_TO_NCB_DID_79_CREDITS"   ,	   0x11800f0000a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"IOB_TO_NCB_DID_96_CREDITS"   ,	   0x11800f0000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
+	{"IOB_TO_NCB_DID_98_CREDITS"   ,	   0x11800f0000b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	561},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	562},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	563},
+	{"IPD_BIST_STATUS"             ,	   0x14f00000007f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	564},
+	{"IPD_BPID0_MBUF_TH"           ,	   0x14f0000002000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID1_MBUF_TH"           ,	   0x14f0000002008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID2_MBUF_TH"           ,	   0x14f0000002010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID3_MBUF_TH"           ,	   0x14f0000002018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID4_MBUF_TH"           ,	   0x14f0000002020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID5_MBUF_TH"           ,	   0x14f0000002028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID6_MBUF_TH"           ,	   0x14f0000002030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID7_MBUF_TH"           ,	   0x14f0000002038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID8_MBUF_TH"           ,	   0x14f0000002040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID9_MBUF_TH"           ,	   0x14f0000002048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID10_MBUF_TH"          ,	   0x14f0000002050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID11_MBUF_TH"          ,	   0x14f0000002058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID12_MBUF_TH"          ,	   0x14f0000002060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID13_MBUF_TH"          ,	   0x14f0000002068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID14_MBUF_TH"          ,	   0x14f0000002070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID15_MBUF_TH"          ,	   0x14f0000002078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID16_MBUF_TH"          ,	   0x14f0000002080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID17_MBUF_TH"          ,	   0x14f0000002088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID18_MBUF_TH"          ,	   0x14f0000002090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID19_MBUF_TH"          ,	   0x14f0000002098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID20_MBUF_TH"          ,	   0x14f00000020a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID21_MBUF_TH"          ,	   0x14f00000020a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID22_MBUF_TH"          ,	   0x14f00000020b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID23_MBUF_TH"          ,	   0x14f00000020b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID24_MBUF_TH"          ,	   0x14f00000020c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID25_MBUF_TH"          ,	   0x14f00000020c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID26_MBUF_TH"          ,	   0x14f00000020d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID27_MBUF_TH"          ,	   0x14f00000020d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID28_MBUF_TH"          ,	   0x14f00000020e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID29_MBUF_TH"          ,	   0x14f00000020e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID30_MBUF_TH"          ,	   0x14f00000020f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID31_MBUF_TH"          ,	   0x14f00000020f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID32_MBUF_TH"          ,	   0x14f0000002100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID33_MBUF_TH"          ,	   0x14f0000002108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID34_MBUF_TH"          ,	   0x14f0000002110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID35_MBUF_TH"          ,	   0x14f0000002118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID36_MBUF_TH"          ,	   0x14f0000002120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID37_MBUF_TH"          ,	   0x14f0000002128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID38_MBUF_TH"          ,	   0x14f0000002130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID39_MBUF_TH"          ,	   0x14f0000002138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID40_MBUF_TH"          ,	   0x14f0000002140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID41_MBUF_TH"          ,	   0x14f0000002148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID42_MBUF_TH"          ,	   0x14f0000002150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID43_MBUF_TH"          ,	   0x14f0000002158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID44_MBUF_TH"          ,	   0x14f0000002160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID45_MBUF_TH"          ,	   0x14f0000002168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID46_MBUF_TH"          ,	   0x14f0000002170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID47_MBUF_TH"          ,	   0x14f0000002178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID48_MBUF_TH"          ,	   0x14f0000002180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID49_MBUF_TH"          ,	   0x14f0000002188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID50_MBUF_TH"          ,	   0x14f0000002190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID51_MBUF_TH"          ,	   0x14f0000002198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID52_MBUF_TH"          ,	   0x14f00000021a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID53_MBUF_TH"          ,	   0x14f00000021a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID54_MBUF_TH"          ,	   0x14f00000021b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID55_MBUF_TH"          ,	   0x14f00000021b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID56_MBUF_TH"          ,	   0x14f00000021c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID57_MBUF_TH"          ,	   0x14f00000021c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID58_MBUF_TH"          ,	   0x14f00000021d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID59_MBUF_TH"          ,	   0x14f00000021d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID60_MBUF_TH"          ,	   0x14f00000021e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID61_MBUF_TH"          ,	   0x14f00000021e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID62_MBUF_TH"          ,	   0x14f00000021f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID63_MBUF_TH"          ,	   0x14f00000021f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"IPD_BPID_BP_COUNTER0"        ,	   0x14f0000003000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER1"        ,	   0x14f0000003008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER2"        ,	   0x14f0000003010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER3"        ,	   0x14f0000003018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER4"        ,	   0x14f0000003020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER5"        ,	   0x14f0000003028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER6"        ,	   0x14f0000003030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER7"        ,	   0x14f0000003038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER8"        ,	   0x14f0000003040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER9"        ,	   0x14f0000003048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER10"       ,	   0x14f0000003050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER11"       ,	   0x14f0000003058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER12"       ,	   0x14f0000003060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER13"       ,	   0x14f0000003068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER14"       ,	   0x14f0000003070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER15"       ,	   0x14f0000003078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER16"       ,	   0x14f0000003080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER17"       ,	   0x14f0000003088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER18"       ,	   0x14f0000003090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER19"       ,	   0x14f0000003098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER20"       ,	   0x14f00000030a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER21"       ,	   0x14f00000030a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER22"       ,	   0x14f00000030b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER23"       ,	   0x14f00000030b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER24"       ,	   0x14f00000030c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER25"       ,	   0x14f00000030c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER26"       ,	   0x14f00000030d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER27"       ,	   0x14f00000030d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER28"       ,	   0x14f00000030e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER29"       ,	   0x14f00000030e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER30"       ,	   0x14f00000030f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER31"       ,	   0x14f00000030f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER32"       ,	   0x14f0000003100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER33"       ,	   0x14f0000003108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER34"       ,	   0x14f0000003110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER35"       ,	   0x14f0000003118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER36"       ,	   0x14f0000003120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER37"       ,	   0x14f0000003128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER38"       ,	   0x14f0000003130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER39"       ,	   0x14f0000003138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER40"       ,	   0x14f0000003140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER41"       ,	   0x14f0000003148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER42"       ,	   0x14f0000003150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER43"       ,	   0x14f0000003158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER44"       ,	   0x14f0000003160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER45"       ,	   0x14f0000003168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER46"       ,	   0x14f0000003170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER47"       ,	   0x14f0000003178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER48"       ,	   0x14f0000003180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER49"       ,	   0x14f0000003188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER50"       ,	   0x14f0000003190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER51"       ,	   0x14f0000003198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER52"       ,	   0x14f00000031a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER53"       ,	   0x14f00000031a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER54"       ,	   0x14f00000031b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER55"       ,	   0x14f00000031b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER56"       ,	   0x14f00000031c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER57"       ,	   0x14f00000031c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER58"       ,	   0x14f00000031d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER59"       ,	   0x14f00000031d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER60"       ,	   0x14f00000031e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER61"       ,	   0x14f00000031e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER62"       ,	   0x14f00000031f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_BPID_BP_COUNTER63"       ,	   0x14f00000031f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_CLK_COUNT"               ,	   0x14f0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	567},
+	{"IPD_CREDITS"                 ,	   0x14f0000004410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	568},
+	{"IPD_CTL_STATUS"              ,	   0x14f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	569},
+	{"IPD_ECC_CTL"                 ,	   0x14f0000004408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_FREE_PTR_FIFO_CTL"       ,	   0x14f0000000780ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_FREE_PTR_VALUE"          ,	   0x14f0000000788ull,	CVMX_CSR_DB_TYPE_NCB,	64,	572},
+	{"IPD_HOLD_PTR_FIFO_CTL"       ,	   0x14f0000000790ull,	CVMX_CSR_DB_TYPE_NCB,	64,	573},
+	{"IPD_INT_ENB"                 ,	   0x14f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	574},
+	{"IPD_INT_SUM"                 ,	   0x14f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	575},
+	{"IPD_NEXT_PKT_PTR"            ,	   0x14f00000007a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	576},
+	{"IPD_NEXT_WQE_PTR"            ,	   0x14f00000007a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	577},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	578},
+	{"IPD_ON_BP_DROP_PKT0"         ,	   0x14f0000004100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	579},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	580},
+	{"IPD_PKT_ERR"                 ,	   0x14f00000003f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	581},
+	{"IPD_PORT_PTR_FIFO_CTL"       ,	   0x14f0000000798ull,	CVMX_CSR_DB_TYPE_NCB,	64,	582},
+	{"IPD_PORT_QOS_0_CNT"          ,	   0x14f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_1_CNT"          ,	   0x14f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_2_CNT"          ,	   0x14f0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_3_CNT"          ,	   0x14f00000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_4_CNT"          ,	   0x14f00000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_5_CNT"          ,	   0x14f00000008b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_6_CNT"          ,	   0x14f00000008b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_7_CNT"          ,	   0x14f00000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_8_CNT"          ,	   0x14f00000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_9_CNT"          ,	   0x14f00000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_10_CNT"         ,	   0x14f00000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_11_CNT"         ,	   0x14f00000008e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_12_CNT"         ,	   0x14f00000008e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_13_CNT"         ,	   0x14f00000008f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_14_CNT"         ,	   0x14f00000008f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_15_CNT"         ,	   0x14f0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_16_CNT"         ,	   0x14f0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_17_CNT"         ,	   0x14f0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_18_CNT"         ,	   0x14f0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_19_CNT"         ,	   0x14f0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_20_CNT"         ,	   0x14f0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_21_CNT"         ,	   0x14f0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_22_CNT"         ,	   0x14f0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_23_CNT"         ,	   0x14f0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_24_CNT"         ,	   0x14f0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_25_CNT"         ,	   0x14f0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_26_CNT"         ,	   0x14f0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_27_CNT"         ,	   0x14f0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_28_CNT"         ,	   0x14f0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_29_CNT"         ,	   0x14f0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_30_CNT"         ,	   0x14f0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_31_CNT"         ,	   0x14f0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_32_CNT"         ,	   0x14f0000000988ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_33_CNT"         ,	   0x14f0000000990ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_34_CNT"         ,	   0x14f0000000998ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_35_CNT"         ,	   0x14f00000009a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_36_CNT"         ,	   0x14f00000009a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_37_CNT"         ,	   0x14f00000009b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_38_CNT"         ,	   0x14f00000009b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_39_CNT"         ,	   0x14f00000009c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_40_CNT"         ,	   0x14f00000009c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_41_CNT"         ,	   0x14f00000009d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_42_CNT"         ,	   0x14f00000009d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_43_CNT"         ,	   0x14f00000009e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_44_CNT"         ,	   0x14f00000009e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_45_CNT"         ,	   0x14f00000009f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_46_CNT"         ,	   0x14f00000009f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_47_CNT"         ,	   0x14f0000000a00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_48_CNT"         ,	   0x14f0000000a08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_49_CNT"         ,	   0x14f0000000a10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_50_CNT"         ,	   0x14f0000000a18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_51_CNT"         ,	   0x14f0000000a20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_52_CNT"         ,	   0x14f0000000a28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_53_CNT"         ,	   0x14f0000000a30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_54_CNT"         ,	   0x14f0000000a38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_55_CNT"         ,	   0x14f0000000a40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_56_CNT"         ,	   0x14f0000000a48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_57_CNT"         ,	   0x14f0000000a50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_58_CNT"         ,	   0x14f0000000a58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_59_CNT"         ,	   0x14f0000000a60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_60_CNT"         ,	   0x14f0000000a68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_61_CNT"         ,	   0x14f0000000a70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_62_CNT"         ,	   0x14f0000000a78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_63_CNT"         ,	   0x14f0000000a80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_64_CNT"         ,	   0x14f0000000a88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_65_CNT"         ,	   0x14f0000000a90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_66_CNT"         ,	   0x14f0000000a98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_67_CNT"         ,	   0x14f0000000aa0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_68_CNT"         ,	   0x14f0000000aa8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_69_CNT"         ,	   0x14f0000000ab0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_70_CNT"         ,	   0x14f0000000ab8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_71_CNT"         ,	   0x14f0000000ac0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_72_CNT"         ,	   0x14f0000000ac8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_73_CNT"         ,	   0x14f0000000ad0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_74_CNT"         ,	   0x14f0000000ad8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_75_CNT"         ,	   0x14f0000000ae0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_76_CNT"         ,	   0x14f0000000ae8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_77_CNT"         ,	   0x14f0000000af0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_78_CNT"         ,	   0x14f0000000af8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_79_CNT"         ,	   0x14f0000000b00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_80_CNT"         ,	   0x14f0000000b08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_81_CNT"         ,	   0x14f0000000b10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_82_CNT"         ,	   0x14f0000000b18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_83_CNT"         ,	   0x14f0000000b20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_84_CNT"         ,	   0x14f0000000b28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_85_CNT"         ,	   0x14f0000000b30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_86_CNT"         ,	   0x14f0000000b38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_87_CNT"         ,	   0x14f0000000b40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_88_CNT"         ,	   0x14f0000000b48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_89_CNT"         ,	   0x14f0000000b50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_90_CNT"         ,	   0x14f0000000b58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_91_CNT"         ,	   0x14f0000000b60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_92_CNT"         ,	   0x14f0000000b68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_93_CNT"         ,	   0x14f0000000b70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_94_CNT"         ,	   0x14f0000000b78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_95_CNT"         ,	   0x14f0000000b80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_96_CNT"         ,	   0x14f0000000b88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_97_CNT"         ,	   0x14f0000000b90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_98_CNT"         ,	   0x14f0000000b98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_99_CNT"         ,	   0x14f0000000ba0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_100_CNT"        ,	   0x14f0000000ba8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_101_CNT"        ,	   0x14f0000000bb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_102_CNT"        ,	   0x14f0000000bb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_103_CNT"        ,	   0x14f0000000bc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_104_CNT"        ,	   0x14f0000000bc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_105_CNT"        ,	   0x14f0000000bd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_106_CNT"        ,	   0x14f0000000bd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_107_CNT"        ,	   0x14f0000000be0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_108_CNT"        ,	   0x14f0000000be8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_109_CNT"        ,	   0x14f0000000bf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_110_CNT"        ,	   0x14f0000000bf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_111_CNT"        ,	   0x14f0000000c00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_112_CNT"        ,	   0x14f0000000c08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_113_CNT"        ,	   0x14f0000000c10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_114_CNT"        ,	   0x14f0000000c18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_115_CNT"        ,	   0x14f0000000c20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_116_CNT"        ,	   0x14f0000000c28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_117_CNT"        ,	   0x14f0000000c30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_118_CNT"        ,	   0x14f0000000c38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_119_CNT"        ,	   0x14f0000000c40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_120_CNT"        ,	   0x14f0000000c48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_121_CNT"        ,	   0x14f0000000c50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_122_CNT"        ,	   0x14f0000000c58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_123_CNT"        ,	   0x14f0000000c60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_124_CNT"        ,	   0x14f0000000c68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_125_CNT"        ,	   0x14f0000000c70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_126_CNT"        ,	   0x14f0000000c78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_127_CNT"        ,	   0x14f0000000c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_128_CNT"        ,	   0x14f0000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_129_CNT"        ,	   0x14f0000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_130_CNT"        ,	   0x14f0000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_131_CNT"        ,	   0x14f0000000ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_132_CNT"        ,	   0x14f0000000ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_133_CNT"        ,	   0x14f0000000cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_134_CNT"        ,	   0x14f0000000cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_135_CNT"        ,	   0x14f0000000cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_136_CNT"        ,	   0x14f0000000cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_137_CNT"        ,	   0x14f0000000cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_138_CNT"        ,	   0x14f0000000cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_139_CNT"        ,	   0x14f0000000ce0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_140_CNT"        ,	   0x14f0000000ce8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_141_CNT"        ,	   0x14f0000000cf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_142_CNT"        ,	   0x14f0000000cf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_143_CNT"        ,	   0x14f0000000d00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_144_CNT"        ,	   0x14f0000000d08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_145_CNT"        ,	   0x14f0000000d10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_146_CNT"        ,	   0x14f0000000d18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_147_CNT"        ,	   0x14f0000000d20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_148_CNT"        ,	   0x14f0000000d28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_149_CNT"        ,	   0x14f0000000d30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_150_CNT"        ,	   0x14f0000000d38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_151_CNT"        ,	   0x14f0000000d40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_152_CNT"        ,	   0x14f0000000d48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_153_CNT"        ,	   0x14f0000000d50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_154_CNT"        ,	   0x14f0000000d58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_155_CNT"        ,	   0x14f0000000d60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_156_CNT"        ,	   0x14f0000000d68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_157_CNT"        ,	   0x14f0000000d70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_158_CNT"        ,	   0x14f0000000d78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_159_CNT"        ,	   0x14f0000000d80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_160_CNT"        ,	   0x14f0000000d88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_161_CNT"        ,	   0x14f0000000d90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_162_CNT"        ,	   0x14f0000000d98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_163_CNT"        ,	   0x14f0000000da0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_164_CNT"        ,	   0x14f0000000da8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_165_CNT"        ,	   0x14f0000000db0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_166_CNT"        ,	   0x14f0000000db8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_167_CNT"        ,	   0x14f0000000dc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_168_CNT"        ,	   0x14f0000000dc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_169_CNT"        ,	   0x14f0000000dd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_170_CNT"        ,	   0x14f0000000dd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_171_CNT"        ,	   0x14f0000000de0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_172_CNT"        ,	   0x14f0000000de8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_173_CNT"        ,	   0x14f0000000df0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_174_CNT"        ,	   0x14f0000000df8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_175_CNT"        ,	   0x14f0000000e00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_176_CNT"        ,	   0x14f0000000e08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_177_CNT"        ,	   0x14f0000000e10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_178_CNT"        ,	   0x14f0000000e18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_179_CNT"        ,	   0x14f0000000e20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_180_CNT"        ,	   0x14f0000000e28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_181_CNT"        ,	   0x14f0000000e30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_182_CNT"        ,	   0x14f0000000e38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_183_CNT"        ,	   0x14f0000000e40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_184_CNT"        ,	   0x14f0000000e48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_185_CNT"        ,	   0x14f0000000e50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_186_CNT"        ,	   0x14f0000000e58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_187_CNT"        ,	   0x14f0000000e60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_188_CNT"        ,	   0x14f0000000e68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_189_CNT"        ,	   0x14f0000000e70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_190_CNT"        ,	   0x14f0000000e78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_191_CNT"        ,	   0x14f0000000e80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_192_CNT"        ,	   0x14f0000000e88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_193_CNT"        ,	   0x14f0000000e90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_194_CNT"        ,	   0x14f0000000e98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_195_CNT"        ,	   0x14f0000000ea0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_196_CNT"        ,	   0x14f0000000ea8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_197_CNT"        ,	   0x14f0000000eb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_198_CNT"        ,	   0x14f0000000eb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_199_CNT"        ,	   0x14f0000000ec0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_200_CNT"        ,	   0x14f0000000ec8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_201_CNT"        ,	   0x14f0000000ed0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_202_CNT"        ,	   0x14f0000000ed8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_203_CNT"        ,	   0x14f0000000ee0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_204_CNT"        ,	   0x14f0000000ee8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_205_CNT"        ,	   0x14f0000000ef0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_206_CNT"        ,	   0x14f0000000ef8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_207_CNT"        ,	   0x14f0000000f00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_208_CNT"        ,	   0x14f0000000f08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_209_CNT"        ,	   0x14f0000000f10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_210_CNT"        ,	   0x14f0000000f18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_211_CNT"        ,	   0x14f0000000f20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_212_CNT"        ,	   0x14f0000000f28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_213_CNT"        ,	   0x14f0000000f30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_214_CNT"        ,	   0x14f0000000f38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_215_CNT"        ,	   0x14f0000000f40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_216_CNT"        ,	   0x14f0000000f48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_217_CNT"        ,	   0x14f0000000f50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_218_CNT"        ,	   0x14f0000000f58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_219_CNT"        ,	   0x14f0000000f60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_220_CNT"        ,	   0x14f0000000f68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_221_CNT"        ,	   0x14f0000000f70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_222_CNT"        ,	   0x14f0000000f78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_223_CNT"        ,	   0x14f0000000f80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_224_CNT"        ,	   0x14f0000000f88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_225_CNT"        ,	   0x14f0000000f90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_226_CNT"        ,	   0x14f0000000f98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_227_CNT"        ,	   0x14f0000000fa0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_228_CNT"        ,	   0x14f0000000fa8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_229_CNT"        ,	   0x14f0000000fb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_230_CNT"        ,	   0x14f0000000fb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_231_CNT"        ,	   0x14f0000000fc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_232_CNT"        ,	   0x14f0000000fc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_233_CNT"        ,	   0x14f0000000fd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_234_CNT"        ,	   0x14f0000000fd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_235_CNT"        ,	   0x14f0000000fe0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_236_CNT"        ,	   0x14f0000000fe8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_237_CNT"        ,	   0x14f0000000ff0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_238_CNT"        ,	   0x14f0000000ff8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_239_CNT"        ,	   0x14f0000001000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_240_CNT"        ,	   0x14f0000001008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_241_CNT"        ,	   0x14f0000001010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_242_CNT"        ,	   0x14f0000001018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_243_CNT"        ,	   0x14f0000001020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_244_CNT"        ,	   0x14f0000001028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_245_CNT"        ,	   0x14f0000001030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_246_CNT"        ,	   0x14f0000001038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_247_CNT"        ,	   0x14f0000001040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_248_CNT"        ,	   0x14f0000001048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_249_CNT"        ,	   0x14f0000001050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_250_CNT"        ,	   0x14f0000001058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_251_CNT"        ,	   0x14f0000001060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_252_CNT"        ,	   0x14f0000001068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_253_CNT"        ,	   0x14f0000001070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_254_CNT"        ,	   0x14f0000001078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_255_CNT"        ,	   0x14f0000001080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_256_CNT"        ,	   0x14f0000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_257_CNT"        ,	   0x14f0000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_258_CNT"        ,	   0x14f0000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_259_CNT"        ,	   0x14f00000010a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_260_CNT"        ,	   0x14f00000010a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_261_CNT"        ,	   0x14f00000010b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_262_CNT"        ,	   0x14f00000010b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_263_CNT"        ,	   0x14f00000010c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_264_CNT"        ,	   0x14f00000010c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_265_CNT"        ,	   0x14f00000010d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_266_CNT"        ,	   0x14f00000010d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_267_CNT"        ,	   0x14f00000010e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_268_CNT"        ,	   0x14f00000010e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_269_CNT"        ,	   0x14f00000010f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_270_CNT"        ,	   0x14f00000010f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_271_CNT"        ,	   0x14f0000001100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_272_CNT"        ,	   0x14f0000001108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_273_CNT"        ,	   0x14f0000001110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_274_CNT"        ,	   0x14f0000001118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_275_CNT"        ,	   0x14f0000001120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_276_CNT"        ,	   0x14f0000001128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_277_CNT"        ,	   0x14f0000001130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_278_CNT"        ,	   0x14f0000001138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_279_CNT"        ,	   0x14f0000001140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_280_CNT"        ,	   0x14f0000001148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_281_CNT"        ,	   0x14f0000001150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_282_CNT"        ,	   0x14f0000001158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_283_CNT"        ,	   0x14f0000001160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_284_CNT"        ,	   0x14f0000001168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_285_CNT"        ,	   0x14f0000001170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_286_CNT"        ,	   0x14f0000001178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_287_CNT"        ,	   0x14f0000001180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_288_CNT"        ,	   0x14f0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_289_CNT"        ,	   0x14f0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_290_CNT"        ,	   0x14f0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_291_CNT"        ,	   0x14f00000011a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_292_CNT"        ,	   0x14f00000011a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_293_CNT"        ,	   0x14f00000011b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_294_CNT"        ,	   0x14f00000011b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_295_CNT"        ,	   0x14f00000011c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_296_CNT"        ,	   0x14f00000011c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_297_CNT"        ,	   0x14f00000011d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_298_CNT"        ,	   0x14f00000011d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_299_CNT"        ,	   0x14f00000011e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_300_CNT"        ,	   0x14f00000011e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_301_CNT"        ,	   0x14f00000011f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_302_CNT"        ,	   0x14f00000011f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_303_CNT"        ,	   0x14f0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_304_CNT"        ,	   0x14f0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_305_CNT"        ,	   0x14f0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_306_CNT"        ,	   0x14f0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_307_CNT"        ,	   0x14f0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_308_CNT"        ,	   0x14f0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_309_CNT"        ,	   0x14f0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_310_CNT"        ,	   0x14f0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_311_CNT"        ,	   0x14f0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_312_CNT"        ,	   0x14f0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_313_CNT"        ,	   0x14f0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_314_CNT"        ,	   0x14f0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_315_CNT"        ,	   0x14f0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_316_CNT"        ,	   0x14f0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_317_CNT"        ,	   0x14f0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_318_CNT"        ,	   0x14f0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_319_CNT"        ,	   0x14f0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_320_CNT"        ,	   0x14f0000001288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_321_CNT"        ,	   0x14f0000001290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_322_CNT"        ,	   0x14f0000001298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_323_CNT"        ,	   0x14f00000012a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_324_CNT"        ,	   0x14f00000012a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_325_CNT"        ,	   0x14f00000012b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_326_CNT"        ,	   0x14f00000012b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_327_CNT"        ,	   0x14f00000012c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_328_CNT"        ,	   0x14f00000012c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_329_CNT"        ,	   0x14f00000012d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_330_CNT"        ,	   0x14f00000012d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_331_CNT"        ,	   0x14f00000012e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_332_CNT"        ,	   0x14f00000012e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_333_CNT"        ,	   0x14f00000012f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_334_CNT"        ,	   0x14f00000012f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_335_CNT"        ,	   0x14f0000001300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_336_CNT"        ,	   0x14f0000001308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_337_CNT"        ,	   0x14f0000001310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_338_CNT"        ,	   0x14f0000001318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_339_CNT"        ,	   0x14f0000001320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_340_CNT"        ,	   0x14f0000001328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_341_CNT"        ,	   0x14f0000001330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_342_CNT"        ,	   0x14f0000001338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_343_CNT"        ,	   0x14f0000001340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_344_CNT"        ,	   0x14f0000001348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_345_CNT"        ,	   0x14f0000001350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_346_CNT"        ,	   0x14f0000001358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_347_CNT"        ,	   0x14f0000001360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_348_CNT"        ,	   0x14f0000001368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_349_CNT"        ,	   0x14f0000001370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_350_CNT"        ,	   0x14f0000001378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_351_CNT"        ,	   0x14f0000001380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_352_CNT"        ,	   0x14f0000001388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_353_CNT"        ,	   0x14f0000001390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_354_CNT"        ,	   0x14f0000001398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_355_CNT"        ,	   0x14f00000013a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_356_CNT"        ,	   0x14f00000013a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_357_CNT"        ,	   0x14f00000013b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_358_CNT"        ,	   0x14f00000013b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_359_CNT"        ,	   0x14f00000013c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_360_CNT"        ,	   0x14f00000013c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_361_CNT"        ,	   0x14f00000013d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_362_CNT"        ,	   0x14f00000013d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_363_CNT"        ,	   0x14f00000013e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_364_CNT"        ,	   0x14f00000013e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_365_CNT"        ,	   0x14f00000013f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_366_CNT"        ,	   0x14f00000013f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_367_CNT"        ,	   0x14f0000001400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_368_CNT"        ,	   0x14f0000001408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_369_CNT"        ,	   0x14f0000001410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_370_CNT"        ,	   0x14f0000001418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_371_CNT"        ,	   0x14f0000001420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_372_CNT"        ,	   0x14f0000001428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_373_CNT"        ,	   0x14f0000001430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_374_CNT"        ,	   0x14f0000001438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_375_CNT"        ,	   0x14f0000001440ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_376_CNT"        ,	   0x14f0000001448ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_377_CNT"        ,	   0x14f0000001450ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_378_CNT"        ,	   0x14f0000001458ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_379_CNT"        ,	   0x14f0000001460ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_380_CNT"        ,	   0x14f0000001468ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_381_CNT"        ,	   0x14f0000001470ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_382_CNT"        ,	   0x14f0000001478ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_383_CNT"        ,	   0x14f0000001480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_384_CNT"        ,	   0x14f0000001488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_385_CNT"        ,	   0x14f0000001490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_386_CNT"        ,	   0x14f0000001498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_387_CNT"        ,	   0x14f00000014a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_388_CNT"        ,	   0x14f00000014a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_389_CNT"        ,	   0x14f00000014b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_390_CNT"        ,	   0x14f00000014b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_391_CNT"        ,	   0x14f00000014c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_392_CNT"        ,	   0x14f00000014c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_393_CNT"        ,	   0x14f00000014d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_394_CNT"        ,	   0x14f00000014d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_395_CNT"        ,	   0x14f00000014e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_396_CNT"        ,	   0x14f00000014e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_397_CNT"        ,	   0x14f00000014f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_398_CNT"        ,	   0x14f00000014f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_399_CNT"        ,	   0x14f0000001500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_400_CNT"        ,	   0x14f0000001508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_401_CNT"        ,	   0x14f0000001510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_402_CNT"        ,	   0x14f0000001518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_403_CNT"        ,	   0x14f0000001520ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_404_CNT"        ,	   0x14f0000001528ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_405_CNT"        ,	   0x14f0000001530ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_406_CNT"        ,	   0x14f0000001538ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_407_CNT"        ,	   0x14f0000001540ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_408_CNT"        ,	   0x14f0000001548ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_409_CNT"        ,	   0x14f0000001550ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_410_CNT"        ,	   0x14f0000001558ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_411_CNT"        ,	   0x14f0000001560ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_412_CNT"        ,	   0x14f0000001568ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_413_CNT"        ,	   0x14f0000001570ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_414_CNT"        ,	   0x14f0000001578ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_415_CNT"        ,	   0x14f0000001580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_416_CNT"        ,	   0x14f0000001588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_417_CNT"        ,	   0x14f0000001590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_418_CNT"        ,	   0x14f0000001598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_419_CNT"        ,	   0x14f00000015a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_420_CNT"        ,	   0x14f00000015a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_421_CNT"        ,	   0x14f00000015b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_422_CNT"        ,	   0x14f00000015b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_423_CNT"        ,	   0x14f00000015c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_424_CNT"        ,	   0x14f00000015c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_425_CNT"        ,	   0x14f00000015d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_426_CNT"        ,	   0x14f00000015d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_427_CNT"        ,	   0x14f00000015e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_428_CNT"        ,	   0x14f00000015e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_429_CNT"        ,	   0x14f00000015f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_430_CNT"        ,	   0x14f00000015f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_431_CNT"        ,	   0x14f0000001600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_432_CNT"        ,	   0x14f0000001608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_433_CNT"        ,	   0x14f0000001610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_434_CNT"        ,	   0x14f0000001618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_435_CNT"        ,	   0x14f0000001620ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_436_CNT"        ,	   0x14f0000001628ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_437_CNT"        ,	   0x14f0000001630ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_438_CNT"        ,	   0x14f0000001638ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_439_CNT"        ,	   0x14f0000001640ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_440_CNT"        ,	   0x14f0000001648ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_441_CNT"        ,	   0x14f0000001650ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_442_CNT"        ,	   0x14f0000001658ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_443_CNT"        ,	   0x14f0000001660ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_444_CNT"        ,	   0x14f0000001668ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_445_CNT"        ,	   0x14f0000001670ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_446_CNT"        ,	   0x14f0000001678ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_447_CNT"        ,	   0x14f0000001680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_448_CNT"        ,	   0x14f0000001688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_449_CNT"        ,	   0x14f0000001690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_450_CNT"        ,	   0x14f0000001698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_451_CNT"        ,	   0x14f00000016a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_452_CNT"        ,	   0x14f00000016a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_453_CNT"        ,	   0x14f00000016b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_454_CNT"        ,	   0x14f00000016b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_455_CNT"        ,	   0x14f00000016c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_456_CNT"        ,	   0x14f00000016c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_457_CNT"        ,	   0x14f00000016d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_458_CNT"        ,	   0x14f00000016d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_459_CNT"        ,	   0x14f00000016e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_460_CNT"        ,	   0x14f00000016e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_461_CNT"        ,	   0x14f00000016f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_462_CNT"        ,	   0x14f00000016f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_463_CNT"        ,	   0x14f0000001700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_464_CNT"        ,	   0x14f0000001708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_465_CNT"        ,	   0x14f0000001710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_466_CNT"        ,	   0x14f0000001718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_467_CNT"        ,	   0x14f0000001720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_468_CNT"        ,	   0x14f0000001728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_469_CNT"        ,	   0x14f0000001730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_470_CNT"        ,	   0x14f0000001738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_471_CNT"        ,	   0x14f0000001740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_472_CNT"        ,	   0x14f0000001748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_473_CNT"        ,	   0x14f0000001750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_474_CNT"        ,	   0x14f0000001758ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_475_CNT"        ,	   0x14f0000001760ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_476_CNT"        ,	   0x14f0000001768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_477_CNT"        ,	   0x14f0000001770ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_478_CNT"        ,	   0x14f0000001778ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_479_CNT"        ,	   0x14f0000001780ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_480_CNT"        ,	   0x14f0000001788ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_481_CNT"        ,	   0x14f0000001790ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_482_CNT"        ,	   0x14f0000001798ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_483_CNT"        ,	   0x14f00000017a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_484_CNT"        ,	   0x14f00000017a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_485_CNT"        ,	   0x14f00000017b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_486_CNT"        ,	   0x14f00000017b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_487_CNT"        ,	   0x14f00000017c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_488_CNT"        ,	   0x14f00000017c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_489_CNT"        ,	   0x14f00000017d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_490_CNT"        ,	   0x14f00000017d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_491_CNT"        ,	   0x14f00000017e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_492_CNT"        ,	   0x14f00000017e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_493_CNT"        ,	   0x14f00000017f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_494_CNT"        ,	   0x14f00000017f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_495_CNT"        ,	   0x14f0000001800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_496_CNT"        ,	   0x14f0000001808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_497_CNT"        ,	   0x14f0000001810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_498_CNT"        ,	   0x14f0000001818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_499_CNT"        ,	   0x14f0000001820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_500_CNT"        ,	   0x14f0000001828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_501_CNT"        ,	   0x14f0000001830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_502_CNT"        ,	   0x14f0000001838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_503_CNT"        ,	   0x14f0000001840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_504_CNT"        ,	   0x14f0000001848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_505_CNT"        ,	   0x14f0000001850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_506_CNT"        ,	   0x14f0000001858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_507_CNT"        ,	   0x14f0000001860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_508_CNT"        ,	   0x14f0000001868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_509_CNT"        ,	   0x14f0000001870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_510_CNT"        ,	   0x14f0000001878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_511_CNT"        ,	   0x14f0000001880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_PORT_QOS_INT0"           ,	   0x14f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	584},
+	{"IPD_PORT_QOS_INT1"           ,	   0x14f0000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	584},
+	{"IPD_PORT_QOS_INT2"           ,	   0x14f0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	584},
+	{"IPD_PORT_QOS_INT3"           ,	   0x14f0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	584},
+	{"IPD_PORT_QOS_INT4"           ,	   0x14f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	584},
+	{"IPD_PORT_QOS_INT5"           ,	   0x14f0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	584},
+	{"IPD_PORT_QOS_INT6"           ,	   0x14f0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	584},
+	{"IPD_PORT_QOS_INT7"           ,	   0x14f0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	584},
+	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	585},
+	{"IPD_PORT_QOS_INT_ENB1"       ,	   0x14f0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	585},
+	{"IPD_PORT_QOS_INT_ENB2"       ,	   0x14f0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	585},
+	{"IPD_PORT_QOS_INT_ENB3"       ,	   0x14f0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	585},
+	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	585},
+	{"IPD_PORT_QOS_INT_ENB5"       ,	   0x14f0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	585},
+	{"IPD_PORT_QOS_INT_ENB6"       ,	   0x14f0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	585},
+	{"IPD_PORT_QOS_INT_ENB7"       ,	   0x14f0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	585},
+	{"IPD_PORT_SOP0"               ,	   0x14f0000004400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	586},
+	{"IPD_PTR_COUNT"               ,	   0x14f0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	587},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14f0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	589},
+	{"IPD_RED_BPID_ENABLE0"        ,	   0x14f0000004200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	590},
+	{"IPD_RED_DELAY"               ,	   0x14f0000004300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	591},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14f00000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	592},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14f00000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	592},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14f00000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	592},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14f00000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	592},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14f0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	592},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14f0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	592},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14f0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	592},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14f0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	592},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	593},
+	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	594},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	595},
+	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	596},
+	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	597},
+	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	598},
+	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	599},
+	{"L2C_BIG_CTL"                 ,	   0x1180080800030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	600},
+	{"L2C_BST"                     ,	   0x11800808007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	601},
+	{"L2C_BST_MEM0"                ,	   0x1180080c007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	602},
+	{"L2C_BST_MEM1"                ,	   0x1180080c407f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	602},
+	{"L2C_BST_MEM2"                ,	   0x1180080c807f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	602},
+	{"L2C_BST_MEM3"                ,	   0x1180080cc07f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	602},
+	{"L2C_BST_TDT0"                ,	   0x1180080a007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	603},
+	{"L2C_BST_TDT1"                ,	   0x1180080a407f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	603},
+	{"L2C_BST_TDT2"                ,	   0x1180080a807f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	603},
+	{"L2C_BST_TDT3"                ,	   0x1180080ac07f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	603},
+	{"L2C_BST_TTG0"                ,	   0x1180080a007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	604},
+	{"L2C_BST_TTG1"                ,	   0x1180080a407f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	604},
+	{"L2C_BST_TTG2"                ,	   0x1180080a807f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	604},
+	{"L2C_BST_TTG3"                ,	   0x1180080ac07f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	604},
+	{"L2C_COP0_MAP0"               ,	   0x1180080940000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1"               ,	   0x1180080940008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2"               ,	   0x1180080940010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3"               ,	   0x1180080940018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4"               ,	   0x1180080940020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5"               ,	   0x1180080940028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6"               ,	   0x1180080940030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7"               ,	   0x1180080940038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8"               ,	   0x1180080940040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP9"               ,	   0x1180080940048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP10"              ,	   0x1180080940050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP11"              ,	   0x1180080940058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP12"              ,	   0x1180080940060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP13"              ,	   0x1180080940068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP14"              ,	   0x1180080940070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP15"              ,	   0x1180080940078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16"              ,	   0x1180080940080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP17"              ,	   0x1180080940088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP18"              ,	   0x1180080940090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP19"              ,	   0x1180080940098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP20"              ,	   0x11800809400a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP21"              ,	   0x11800809400a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP22"              ,	   0x11800809400b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP23"              ,	   0x11800809400b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP24"              ,	   0x11800809400c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP25"              ,	   0x11800809400c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP26"              ,	   0x11800809400d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP27"              ,	   0x11800809400d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP28"              ,	   0x11800809400e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP29"              ,	   0x11800809400e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP30"              ,	   0x11800809400f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP31"              ,	   0x11800809400f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP32"              ,	   0x1180080940100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP33"              ,	   0x1180080940108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP34"              ,	   0x1180080940110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP35"              ,	   0x1180080940118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP36"              ,	   0x1180080940120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP37"              ,	   0x1180080940128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP38"              ,	   0x1180080940130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP39"              ,	   0x1180080940138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP40"              ,	   0x1180080940140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP41"              ,	   0x1180080940148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP42"              ,	   0x1180080940150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP43"              ,	   0x1180080940158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP44"              ,	   0x1180080940160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP45"              ,	   0x1180080940168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP46"              ,	   0x1180080940170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP47"              ,	   0x1180080940178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP48"              ,	   0x1180080940180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP49"              ,	   0x1180080940188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP50"              ,	   0x1180080940190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP51"              ,	   0x1180080940198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP52"              ,	   0x11800809401a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP53"              ,	   0x11800809401a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP54"              ,	   0x11800809401b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP55"              ,	   0x11800809401b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP56"              ,	   0x11800809401c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP57"              ,	   0x11800809401c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP58"              ,	   0x11800809401d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP59"              ,	   0x11800809401d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP60"              ,	   0x11800809401e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP61"              ,	   0x11800809401e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP62"              ,	   0x11800809401f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP63"              ,	   0x11800809401f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP64"              ,	   0x1180080940200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP65"              ,	   0x1180080940208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP66"              ,	   0x1180080940210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP67"              ,	   0x1180080940218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP68"              ,	   0x1180080940220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP69"              ,	   0x1180080940228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP70"              ,	   0x1180080940230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP71"              ,	   0x1180080940238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP72"              ,	   0x1180080940240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP73"              ,	   0x1180080940248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP74"              ,	   0x1180080940250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP75"              ,	   0x1180080940258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP76"              ,	   0x1180080940260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP77"              ,	   0x1180080940268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP78"              ,	   0x1180080940270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP79"              ,	   0x1180080940278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP80"              ,	   0x1180080940280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP81"              ,	   0x1180080940288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP82"              ,	   0x1180080940290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP83"              ,	   0x1180080940298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP84"              ,	   0x11800809402a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP85"              ,	   0x11800809402a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP86"              ,	   0x11800809402b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP87"              ,	   0x11800809402b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP88"              ,	   0x11800809402c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP89"              ,	   0x11800809402c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP90"              ,	   0x11800809402d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP91"              ,	   0x11800809402d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP92"              ,	   0x11800809402e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP93"              ,	   0x11800809402e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP94"              ,	   0x11800809402f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP95"              ,	   0x11800809402f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP96"              ,	   0x1180080940300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP97"              ,	   0x1180080940308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP98"              ,	   0x1180080940310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP99"              ,	   0x1180080940318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP100"             ,	   0x1180080940320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP101"             ,	   0x1180080940328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP102"             ,	   0x1180080940330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP103"             ,	   0x1180080940338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP104"             ,	   0x1180080940340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP105"             ,	   0x1180080940348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP106"             ,	   0x1180080940350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP107"             ,	   0x1180080940358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP108"             ,	   0x1180080940360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP109"             ,	   0x1180080940368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP110"             ,	   0x1180080940370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP111"             ,	   0x1180080940378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP112"             ,	   0x1180080940380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP113"             ,	   0x1180080940388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP114"             ,	   0x1180080940390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP115"             ,	   0x1180080940398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP116"             ,	   0x11800809403a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP117"             ,	   0x11800809403a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP118"             ,	   0x11800809403b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP119"             ,	   0x11800809403b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP120"             ,	   0x11800809403c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP121"             ,	   0x11800809403c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP122"             ,	   0x11800809403d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP123"             ,	   0x11800809403d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP124"             ,	   0x11800809403e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP125"             ,	   0x11800809403e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP126"             ,	   0x11800809403f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP127"             ,	   0x11800809403f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP128"             ,	   0x1180080940400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP129"             ,	   0x1180080940408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP130"             ,	   0x1180080940410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP131"             ,	   0x1180080940418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP132"             ,	   0x1180080940420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP133"             ,	   0x1180080940428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP134"             ,	   0x1180080940430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP135"             ,	   0x1180080940438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP136"             ,	   0x1180080940440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP137"             ,	   0x1180080940448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP138"             ,	   0x1180080940450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP139"             ,	   0x1180080940458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP140"             ,	   0x1180080940460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP141"             ,	   0x1180080940468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP142"             ,	   0x1180080940470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP143"             ,	   0x1180080940478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP144"             ,	   0x1180080940480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP145"             ,	   0x1180080940488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP146"             ,	   0x1180080940490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP147"             ,	   0x1180080940498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP148"             ,	   0x11800809404a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP149"             ,	   0x11800809404a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP150"             ,	   0x11800809404b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP151"             ,	   0x11800809404b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP152"             ,	   0x11800809404c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP153"             ,	   0x11800809404c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP154"             ,	   0x11800809404d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP155"             ,	   0x11800809404d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP156"             ,	   0x11800809404e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP157"             ,	   0x11800809404e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP158"             ,	   0x11800809404f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP159"             ,	   0x11800809404f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP160"             ,	   0x1180080940500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP161"             ,	   0x1180080940508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP162"             ,	   0x1180080940510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP163"             ,	   0x1180080940518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP164"             ,	   0x1180080940520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP165"             ,	   0x1180080940528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP166"             ,	   0x1180080940530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP167"             ,	   0x1180080940538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP168"             ,	   0x1180080940540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP169"             ,	   0x1180080940548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP170"             ,	   0x1180080940550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP171"             ,	   0x1180080940558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP172"             ,	   0x1180080940560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP173"             ,	   0x1180080940568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP174"             ,	   0x1180080940570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP175"             ,	   0x1180080940578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP176"             ,	   0x1180080940580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP177"             ,	   0x1180080940588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP178"             ,	   0x1180080940590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP179"             ,	   0x1180080940598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP180"             ,	   0x11800809405a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP181"             ,	   0x11800809405a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP182"             ,	   0x11800809405b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP183"             ,	   0x11800809405b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP184"             ,	   0x11800809405c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP185"             ,	   0x11800809405c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP186"             ,	   0x11800809405d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP187"             ,	   0x11800809405d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP188"             ,	   0x11800809405e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP189"             ,	   0x11800809405e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP190"             ,	   0x11800809405f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP191"             ,	   0x11800809405f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP192"             ,	   0x1180080940600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP193"             ,	   0x1180080940608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP194"             ,	   0x1180080940610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP195"             ,	   0x1180080940618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP196"             ,	   0x1180080940620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP197"             ,	   0x1180080940628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP198"             ,	   0x1180080940630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP199"             ,	   0x1180080940638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP200"             ,	   0x1180080940640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP201"             ,	   0x1180080940648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP202"             ,	   0x1180080940650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP203"             ,	   0x1180080940658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP204"             ,	   0x1180080940660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP205"             ,	   0x1180080940668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP206"             ,	   0x1180080940670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP207"             ,	   0x1180080940678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP208"             ,	   0x1180080940680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP209"             ,	   0x1180080940688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP210"             ,	   0x1180080940690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP211"             ,	   0x1180080940698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP212"             ,	   0x11800809406a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP213"             ,	   0x11800809406a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP214"             ,	   0x11800809406b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP215"             ,	   0x11800809406b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP216"             ,	   0x11800809406c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP217"             ,	   0x11800809406c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP218"             ,	   0x11800809406d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP219"             ,	   0x11800809406d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP220"             ,	   0x11800809406e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP221"             ,	   0x11800809406e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP222"             ,	   0x11800809406f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP223"             ,	   0x11800809406f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP224"             ,	   0x1180080940700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP225"             ,	   0x1180080940708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP226"             ,	   0x1180080940710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP227"             ,	   0x1180080940718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP228"             ,	   0x1180080940720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP229"             ,	   0x1180080940728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP230"             ,	   0x1180080940730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP231"             ,	   0x1180080940738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP232"             ,	   0x1180080940740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP233"             ,	   0x1180080940748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP234"             ,	   0x1180080940750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP235"             ,	   0x1180080940758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP236"             ,	   0x1180080940760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP237"             ,	   0x1180080940768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP238"             ,	   0x1180080940770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP239"             ,	   0x1180080940778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP240"             ,	   0x1180080940780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP241"             ,	   0x1180080940788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP242"             ,	   0x1180080940790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP243"             ,	   0x1180080940798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP244"             ,	   0x11800809407a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP245"             ,	   0x11800809407a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP246"             ,	   0x11800809407b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP247"             ,	   0x11800809407b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP248"             ,	   0x11800809407c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP249"             ,	   0x11800809407c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP250"             ,	   0x11800809407d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP251"             ,	   0x11800809407d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP252"             ,	   0x11800809407e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP253"             ,	   0x11800809407e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP254"             ,	   0x11800809407f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP255"             ,	   0x11800809407f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP256"             ,	   0x1180080940800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP257"             ,	   0x1180080940808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP258"             ,	   0x1180080940810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP259"             ,	   0x1180080940818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP260"             ,	   0x1180080940820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP261"             ,	   0x1180080940828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP262"             ,	   0x1180080940830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP263"             ,	   0x1180080940838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP264"             ,	   0x1180080940840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP265"             ,	   0x1180080940848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP266"             ,	   0x1180080940850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP267"             ,	   0x1180080940858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP268"             ,	   0x1180080940860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP269"             ,	   0x1180080940868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP270"             ,	   0x1180080940870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP271"             ,	   0x1180080940878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP272"             ,	   0x1180080940880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP273"             ,	   0x1180080940888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP274"             ,	   0x1180080940890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP275"             ,	   0x1180080940898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP276"             ,	   0x11800809408a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP277"             ,	   0x11800809408a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP278"             ,	   0x11800809408b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP279"             ,	   0x11800809408b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP280"             ,	   0x11800809408c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP281"             ,	   0x11800809408c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP282"             ,	   0x11800809408d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP283"             ,	   0x11800809408d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP284"             ,	   0x11800809408e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP285"             ,	   0x11800809408e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP286"             ,	   0x11800809408f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP287"             ,	   0x11800809408f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP288"             ,	   0x1180080940900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP289"             ,	   0x1180080940908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP290"             ,	   0x1180080940910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP291"             ,	   0x1180080940918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP292"             ,	   0x1180080940920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP293"             ,	   0x1180080940928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP294"             ,	   0x1180080940930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP295"             ,	   0x1180080940938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP296"             ,	   0x1180080940940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP297"             ,	   0x1180080940948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP298"             ,	   0x1180080940950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP299"             ,	   0x1180080940958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP300"             ,	   0x1180080940960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP301"             ,	   0x1180080940968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP302"             ,	   0x1180080940970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP303"             ,	   0x1180080940978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP304"             ,	   0x1180080940980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP305"             ,	   0x1180080940988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP306"             ,	   0x1180080940990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP307"             ,	   0x1180080940998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP308"             ,	   0x11800809409a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP309"             ,	   0x11800809409a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP310"             ,	   0x11800809409b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP311"             ,	   0x11800809409b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP312"             ,	   0x11800809409c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP313"             ,	   0x11800809409c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP314"             ,	   0x11800809409d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP315"             ,	   0x11800809409d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP316"             ,	   0x11800809409e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP317"             ,	   0x11800809409e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP318"             ,	   0x11800809409f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP319"             ,	   0x11800809409f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP320"             ,	   0x1180080940a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP321"             ,	   0x1180080940a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP322"             ,	   0x1180080940a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP323"             ,	   0x1180080940a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP324"             ,	   0x1180080940a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP325"             ,	   0x1180080940a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP326"             ,	   0x1180080940a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP327"             ,	   0x1180080940a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP328"             ,	   0x1180080940a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP329"             ,	   0x1180080940a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP330"             ,	   0x1180080940a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP331"             ,	   0x1180080940a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP332"             ,	   0x1180080940a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP333"             ,	   0x1180080940a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP334"             ,	   0x1180080940a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP335"             ,	   0x1180080940a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP336"             ,	   0x1180080940a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP337"             ,	   0x1180080940a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP338"             ,	   0x1180080940a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP339"             ,	   0x1180080940a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP340"             ,	   0x1180080940aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP341"             ,	   0x1180080940aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP342"             ,	   0x1180080940ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP343"             ,	   0x1180080940ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP344"             ,	   0x1180080940ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP345"             ,	   0x1180080940ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP346"             ,	   0x1180080940ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP347"             ,	   0x1180080940ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP348"             ,	   0x1180080940ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP349"             ,	   0x1180080940ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP350"             ,	   0x1180080940af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP351"             ,	   0x1180080940af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP352"             ,	   0x1180080940b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP353"             ,	   0x1180080940b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP354"             ,	   0x1180080940b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP355"             ,	   0x1180080940b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP356"             ,	   0x1180080940b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP357"             ,	   0x1180080940b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP358"             ,	   0x1180080940b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP359"             ,	   0x1180080940b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP360"             ,	   0x1180080940b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP361"             ,	   0x1180080940b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP362"             ,	   0x1180080940b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP363"             ,	   0x1180080940b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP364"             ,	   0x1180080940b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP365"             ,	   0x1180080940b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP366"             ,	   0x1180080940b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP367"             ,	   0x1180080940b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP368"             ,	   0x1180080940b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP369"             ,	   0x1180080940b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP370"             ,	   0x1180080940b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP371"             ,	   0x1180080940b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP372"             ,	   0x1180080940ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP373"             ,	   0x1180080940ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP374"             ,	   0x1180080940bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP375"             ,	   0x1180080940bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP376"             ,	   0x1180080940bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP377"             ,	   0x1180080940bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP378"             ,	   0x1180080940bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP379"             ,	   0x1180080940bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP380"             ,	   0x1180080940be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP381"             ,	   0x1180080940be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP382"             ,	   0x1180080940bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP383"             ,	   0x1180080940bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP384"             ,	   0x1180080940c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP385"             ,	   0x1180080940c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP386"             ,	   0x1180080940c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP387"             ,	   0x1180080940c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP388"             ,	   0x1180080940c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP389"             ,	   0x1180080940c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP390"             ,	   0x1180080940c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP391"             ,	   0x1180080940c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP392"             ,	   0x1180080940c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP393"             ,	   0x1180080940c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP394"             ,	   0x1180080940c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP395"             ,	   0x1180080940c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP396"             ,	   0x1180080940c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP397"             ,	   0x1180080940c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP398"             ,	   0x1180080940c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP399"             ,	   0x1180080940c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP400"             ,	   0x1180080940c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP401"             ,	   0x1180080940c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP402"             ,	   0x1180080940c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP403"             ,	   0x1180080940c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP404"             ,	   0x1180080940ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP405"             ,	   0x1180080940ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP406"             ,	   0x1180080940cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP407"             ,	   0x1180080940cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP408"             ,	   0x1180080940cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP409"             ,	   0x1180080940cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP410"             ,	   0x1180080940cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP411"             ,	   0x1180080940cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP412"             ,	   0x1180080940ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP413"             ,	   0x1180080940ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP414"             ,	   0x1180080940cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP415"             ,	   0x1180080940cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP416"             ,	   0x1180080940d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP417"             ,	   0x1180080940d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP418"             ,	   0x1180080940d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP419"             ,	   0x1180080940d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP420"             ,	   0x1180080940d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP421"             ,	   0x1180080940d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP422"             ,	   0x1180080940d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP423"             ,	   0x1180080940d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP424"             ,	   0x1180080940d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP425"             ,	   0x1180080940d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP426"             ,	   0x1180080940d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP427"             ,	   0x1180080940d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP428"             ,	   0x1180080940d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP429"             ,	   0x1180080940d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP430"             ,	   0x1180080940d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP431"             ,	   0x1180080940d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP432"             ,	   0x1180080940d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP433"             ,	   0x1180080940d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP434"             ,	   0x1180080940d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP435"             ,	   0x1180080940d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP436"             ,	   0x1180080940da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP437"             ,	   0x1180080940da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP438"             ,	   0x1180080940db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP439"             ,	   0x1180080940db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP440"             ,	   0x1180080940dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP441"             ,	   0x1180080940dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP442"             ,	   0x1180080940dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP443"             ,	   0x1180080940dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP444"             ,	   0x1180080940de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP445"             ,	   0x1180080940de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP446"             ,	   0x1180080940df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP447"             ,	   0x1180080940df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP448"             ,	   0x1180080940e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP449"             ,	   0x1180080940e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP450"             ,	   0x1180080940e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP451"             ,	   0x1180080940e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP452"             ,	   0x1180080940e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP453"             ,	   0x1180080940e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP454"             ,	   0x1180080940e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP455"             ,	   0x1180080940e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP456"             ,	   0x1180080940e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP457"             ,	   0x1180080940e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP458"             ,	   0x1180080940e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP459"             ,	   0x1180080940e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP460"             ,	   0x1180080940e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP461"             ,	   0x1180080940e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP462"             ,	   0x1180080940e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP463"             ,	   0x1180080940e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP464"             ,	   0x1180080940e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP465"             ,	   0x1180080940e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP466"             ,	   0x1180080940e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP467"             ,	   0x1180080940e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP468"             ,	   0x1180080940ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP469"             ,	   0x1180080940ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP470"             ,	   0x1180080940eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP471"             ,	   0x1180080940eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP472"             ,	   0x1180080940ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP473"             ,	   0x1180080940ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP474"             ,	   0x1180080940ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP475"             ,	   0x1180080940ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP476"             ,	   0x1180080940ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP477"             ,	   0x1180080940ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP478"             ,	   0x1180080940ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP479"             ,	   0x1180080940ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP480"             ,	   0x1180080940f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP481"             ,	   0x1180080940f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP482"             ,	   0x1180080940f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP483"             ,	   0x1180080940f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP484"             ,	   0x1180080940f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP485"             ,	   0x1180080940f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP486"             ,	   0x1180080940f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP487"             ,	   0x1180080940f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP488"             ,	   0x1180080940f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP489"             ,	   0x1180080940f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP490"             ,	   0x1180080940f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP491"             ,	   0x1180080940f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP492"             ,	   0x1180080940f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP493"             ,	   0x1180080940f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP494"             ,	   0x1180080940f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP495"             ,	   0x1180080940f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP496"             ,	   0x1180080940f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP497"             ,	   0x1180080940f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP498"             ,	   0x1180080940f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP499"             ,	   0x1180080940f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP500"             ,	   0x1180080940fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP501"             ,	   0x1180080940fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP502"             ,	   0x1180080940fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP503"             ,	   0x1180080940fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP504"             ,	   0x1180080940fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP505"             ,	   0x1180080940fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP506"             ,	   0x1180080940fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP507"             ,	   0x1180080940fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP508"             ,	   0x1180080940fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP509"             ,	   0x1180080940fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP510"             ,	   0x1180080940ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP511"             ,	   0x1180080940ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP512"             ,	   0x1180080941000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP513"             ,	   0x1180080941008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP514"             ,	   0x1180080941010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP515"             ,	   0x1180080941018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP516"             ,	   0x1180080941020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP517"             ,	   0x1180080941028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP518"             ,	   0x1180080941030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP519"             ,	   0x1180080941038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP520"             ,	   0x1180080941040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP521"             ,	   0x1180080941048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP522"             ,	   0x1180080941050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP523"             ,	   0x1180080941058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP524"             ,	   0x1180080941060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP525"             ,	   0x1180080941068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP526"             ,	   0x1180080941070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP527"             ,	   0x1180080941078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP528"             ,	   0x1180080941080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP529"             ,	   0x1180080941088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP530"             ,	   0x1180080941090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP531"             ,	   0x1180080941098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP532"             ,	   0x11800809410a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP533"             ,	   0x11800809410a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP534"             ,	   0x11800809410b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP535"             ,	   0x11800809410b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP536"             ,	   0x11800809410c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP537"             ,	   0x11800809410c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP538"             ,	   0x11800809410d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP539"             ,	   0x11800809410d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP540"             ,	   0x11800809410e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP541"             ,	   0x11800809410e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP542"             ,	   0x11800809410f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP543"             ,	   0x11800809410f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP544"             ,	   0x1180080941100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP545"             ,	   0x1180080941108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP546"             ,	   0x1180080941110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP547"             ,	   0x1180080941118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP548"             ,	   0x1180080941120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP549"             ,	   0x1180080941128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP550"             ,	   0x1180080941130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP551"             ,	   0x1180080941138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP552"             ,	   0x1180080941140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP553"             ,	   0x1180080941148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP554"             ,	   0x1180080941150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP555"             ,	   0x1180080941158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP556"             ,	   0x1180080941160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP557"             ,	   0x1180080941168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP558"             ,	   0x1180080941170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP559"             ,	   0x1180080941178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP560"             ,	   0x1180080941180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP561"             ,	   0x1180080941188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP562"             ,	   0x1180080941190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP563"             ,	   0x1180080941198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP564"             ,	   0x11800809411a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP565"             ,	   0x11800809411a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP566"             ,	   0x11800809411b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP567"             ,	   0x11800809411b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP568"             ,	   0x11800809411c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP569"             ,	   0x11800809411c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP570"             ,	   0x11800809411d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP571"             ,	   0x11800809411d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP572"             ,	   0x11800809411e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP573"             ,	   0x11800809411e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP574"             ,	   0x11800809411f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP575"             ,	   0x11800809411f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP576"             ,	   0x1180080941200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP577"             ,	   0x1180080941208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP578"             ,	   0x1180080941210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP579"             ,	   0x1180080941218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP580"             ,	   0x1180080941220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP581"             ,	   0x1180080941228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP582"             ,	   0x1180080941230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP583"             ,	   0x1180080941238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP584"             ,	   0x1180080941240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP585"             ,	   0x1180080941248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP586"             ,	   0x1180080941250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP587"             ,	   0x1180080941258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP588"             ,	   0x1180080941260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP589"             ,	   0x1180080941268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP590"             ,	   0x1180080941270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP591"             ,	   0x1180080941278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP592"             ,	   0x1180080941280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP593"             ,	   0x1180080941288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP594"             ,	   0x1180080941290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP595"             ,	   0x1180080941298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP596"             ,	   0x11800809412a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP597"             ,	   0x11800809412a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP598"             ,	   0x11800809412b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP599"             ,	   0x11800809412b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP600"             ,	   0x11800809412c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP601"             ,	   0x11800809412c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP602"             ,	   0x11800809412d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP603"             ,	   0x11800809412d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP604"             ,	   0x11800809412e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP605"             ,	   0x11800809412e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP606"             ,	   0x11800809412f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP607"             ,	   0x11800809412f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP608"             ,	   0x1180080941300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP609"             ,	   0x1180080941308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP610"             ,	   0x1180080941310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP611"             ,	   0x1180080941318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP612"             ,	   0x1180080941320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP613"             ,	   0x1180080941328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP614"             ,	   0x1180080941330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP615"             ,	   0x1180080941338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP616"             ,	   0x1180080941340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP617"             ,	   0x1180080941348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP618"             ,	   0x1180080941350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP619"             ,	   0x1180080941358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP620"             ,	   0x1180080941360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP621"             ,	   0x1180080941368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP622"             ,	   0x1180080941370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP623"             ,	   0x1180080941378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP624"             ,	   0x1180080941380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP625"             ,	   0x1180080941388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP626"             ,	   0x1180080941390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP627"             ,	   0x1180080941398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP628"             ,	   0x11800809413a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP629"             ,	   0x11800809413a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP630"             ,	   0x11800809413b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP631"             ,	   0x11800809413b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP632"             ,	   0x11800809413c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP633"             ,	   0x11800809413c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP634"             ,	   0x11800809413d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP635"             ,	   0x11800809413d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP636"             ,	   0x11800809413e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP637"             ,	   0x11800809413e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP638"             ,	   0x11800809413f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP639"             ,	   0x11800809413f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP640"             ,	   0x1180080941400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP641"             ,	   0x1180080941408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP642"             ,	   0x1180080941410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP643"             ,	   0x1180080941418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP644"             ,	   0x1180080941420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP645"             ,	   0x1180080941428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP646"             ,	   0x1180080941430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP647"             ,	   0x1180080941438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP648"             ,	   0x1180080941440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP649"             ,	   0x1180080941448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP650"             ,	   0x1180080941450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP651"             ,	   0x1180080941458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP652"             ,	   0x1180080941460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP653"             ,	   0x1180080941468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP654"             ,	   0x1180080941470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP655"             ,	   0x1180080941478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP656"             ,	   0x1180080941480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP657"             ,	   0x1180080941488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP658"             ,	   0x1180080941490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP659"             ,	   0x1180080941498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP660"             ,	   0x11800809414a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP661"             ,	   0x11800809414a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP662"             ,	   0x11800809414b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP663"             ,	   0x11800809414b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP664"             ,	   0x11800809414c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP665"             ,	   0x11800809414c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP666"             ,	   0x11800809414d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP667"             ,	   0x11800809414d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP668"             ,	   0x11800809414e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP669"             ,	   0x11800809414e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP670"             ,	   0x11800809414f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP671"             ,	   0x11800809414f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP672"             ,	   0x1180080941500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP673"             ,	   0x1180080941508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP674"             ,	   0x1180080941510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP675"             ,	   0x1180080941518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP676"             ,	   0x1180080941520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP677"             ,	   0x1180080941528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP678"             ,	   0x1180080941530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP679"             ,	   0x1180080941538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP680"             ,	   0x1180080941540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP681"             ,	   0x1180080941548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP682"             ,	   0x1180080941550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP683"             ,	   0x1180080941558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP684"             ,	   0x1180080941560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP685"             ,	   0x1180080941568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP686"             ,	   0x1180080941570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP687"             ,	   0x1180080941578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP688"             ,	   0x1180080941580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP689"             ,	   0x1180080941588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP690"             ,	   0x1180080941590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP691"             ,	   0x1180080941598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP692"             ,	   0x11800809415a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP693"             ,	   0x11800809415a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP694"             ,	   0x11800809415b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP695"             ,	   0x11800809415b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP696"             ,	   0x11800809415c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP697"             ,	   0x11800809415c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP698"             ,	   0x11800809415d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP699"             ,	   0x11800809415d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP700"             ,	   0x11800809415e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP701"             ,	   0x11800809415e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP702"             ,	   0x11800809415f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP703"             ,	   0x11800809415f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP704"             ,	   0x1180080941600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP705"             ,	   0x1180080941608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP706"             ,	   0x1180080941610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP707"             ,	   0x1180080941618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP708"             ,	   0x1180080941620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP709"             ,	   0x1180080941628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP710"             ,	   0x1180080941630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP711"             ,	   0x1180080941638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP712"             ,	   0x1180080941640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP713"             ,	   0x1180080941648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP714"             ,	   0x1180080941650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP715"             ,	   0x1180080941658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP716"             ,	   0x1180080941660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP717"             ,	   0x1180080941668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP718"             ,	   0x1180080941670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP719"             ,	   0x1180080941678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP720"             ,	   0x1180080941680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP721"             ,	   0x1180080941688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP722"             ,	   0x1180080941690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP723"             ,	   0x1180080941698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP724"             ,	   0x11800809416a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP725"             ,	   0x11800809416a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP726"             ,	   0x11800809416b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP727"             ,	   0x11800809416b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP728"             ,	   0x11800809416c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP729"             ,	   0x11800809416c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP730"             ,	   0x11800809416d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP731"             ,	   0x11800809416d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP732"             ,	   0x11800809416e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP733"             ,	   0x11800809416e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP734"             ,	   0x11800809416f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP735"             ,	   0x11800809416f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP736"             ,	   0x1180080941700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP737"             ,	   0x1180080941708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP738"             ,	   0x1180080941710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP739"             ,	   0x1180080941718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP740"             ,	   0x1180080941720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP741"             ,	   0x1180080941728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP742"             ,	   0x1180080941730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP743"             ,	   0x1180080941738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP744"             ,	   0x1180080941740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP745"             ,	   0x1180080941748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP746"             ,	   0x1180080941750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP747"             ,	   0x1180080941758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP748"             ,	   0x1180080941760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP749"             ,	   0x1180080941768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP750"             ,	   0x1180080941770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP751"             ,	   0x1180080941778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP752"             ,	   0x1180080941780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP753"             ,	   0x1180080941788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP754"             ,	   0x1180080941790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP755"             ,	   0x1180080941798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP756"             ,	   0x11800809417a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP757"             ,	   0x11800809417a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP758"             ,	   0x11800809417b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP759"             ,	   0x11800809417b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP760"             ,	   0x11800809417c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP761"             ,	   0x11800809417c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP762"             ,	   0x11800809417d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP763"             ,	   0x11800809417d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP764"             ,	   0x11800809417e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP765"             ,	   0x11800809417e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP766"             ,	   0x11800809417f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP767"             ,	   0x11800809417f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP768"             ,	   0x1180080941800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP769"             ,	   0x1180080941808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP770"             ,	   0x1180080941810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP771"             ,	   0x1180080941818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP772"             ,	   0x1180080941820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP773"             ,	   0x1180080941828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP774"             ,	   0x1180080941830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP775"             ,	   0x1180080941838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP776"             ,	   0x1180080941840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP777"             ,	   0x1180080941848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP778"             ,	   0x1180080941850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP779"             ,	   0x1180080941858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP780"             ,	   0x1180080941860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP781"             ,	   0x1180080941868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP782"             ,	   0x1180080941870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP783"             ,	   0x1180080941878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP784"             ,	   0x1180080941880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP785"             ,	   0x1180080941888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP786"             ,	   0x1180080941890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP787"             ,	   0x1180080941898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP788"             ,	   0x11800809418a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP789"             ,	   0x11800809418a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP790"             ,	   0x11800809418b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP791"             ,	   0x11800809418b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP792"             ,	   0x11800809418c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP793"             ,	   0x11800809418c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP794"             ,	   0x11800809418d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP795"             ,	   0x11800809418d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP796"             ,	   0x11800809418e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP797"             ,	   0x11800809418e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP798"             ,	   0x11800809418f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP799"             ,	   0x11800809418f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP800"             ,	   0x1180080941900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP801"             ,	   0x1180080941908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP802"             ,	   0x1180080941910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP803"             ,	   0x1180080941918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP804"             ,	   0x1180080941920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP805"             ,	   0x1180080941928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP806"             ,	   0x1180080941930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP807"             ,	   0x1180080941938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP808"             ,	   0x1180080941940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP809"             ,	   0x1180080941948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP810"             ,	   0x1180080941950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP811"             ,	   0x1180080941958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP812"             ,	   0x1180080941960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP813"             ,	   0x1180080941968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP814"             ,	   0x1180080941970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP815"             ,	   0x1180080941978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP816"             ,	   0x1180080941980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP817"             ,	   0x1180080941988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP818"             ,	   0x1180080941990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP819"             ,	   0x1180080941998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP820"             ,	   0x11800809419a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP821"             ,	   0x11800809419a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP822"             ,	   0x11800809419b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP823"             ,	   0x11800809419b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP824"             ,	   0x11800809419c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP825"             ,	   0x11800809419c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP826"             ,	   0x11800809419d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP827"             ,	   0x11800809419d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP828"             ,	   0x11800809419e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP829"             ,	   0x11800809419e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP830"             ,	   0x11800809419f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP831"             ,	   0x11800809419f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP832"             ,	   0x1180080941a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP833"             ,	   0x1180080941a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP834"             ,	   0x1180080941a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP835"             ,	   0x1180080941a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP836"             ,	   0x1180080941a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP837"             ,	   0x1180080941a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP838"             ,	   0x1180080941a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP839"             ,	   0x1180080941a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP840"             ,	   0x1180080941a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP841"             ,	   0x1180080941a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP842"             ,	   0x1180080941a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP843"             ,	   0x1180080941a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP844"             ,	   0x1180080941a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP845"             ,	   0x1180080941a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP846"             ,	   0x1180080941a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP847"             ,	   0x1180080941a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP848"             ,	   0x1180080941a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP849"             ,	   0x1180080941a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP850"             ,	   0x1180080941a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP851"             ,	   0x1180080941a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP852"             ,	   0x1180080941aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP853"             ,	   0x1180080941aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP854"             ,	   0x1180080941ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP855"             ,	   0x1180080941ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP856"             ,	   0x1180080941ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP857"             ,	   0x1180080941ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP858"             ,	   0x1180080941ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP859"             ,	   0x1180080941ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP860"             ,	   0x1180080941ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP861"             ,	   0x1180080941ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP862"             ,	   0x1180080941af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP863"             ,	   0x1180080941af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP864"             ,	   0x1180080941b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP865"             ,	   0x1180080941b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP866"             ,	   0x1180080941b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP867"             ,	   0x1180080941b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP868"             ,	   0x1180080941b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP869"             ,	   0x1180080941b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP870"             ,	   0x1180080941b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP871"             ,	   0x1180080941b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP872"             ,	   0x1180080941b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP873"             ,	   0x1180080941b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP874"             ,	   0x1180080941b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP875"             ,	   0x1180080941b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP876"             ,	   0x1180080941b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP877"             ,	   0x1180080941b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP878"             ,	   0x1180080941b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP879"             ,	   0x1180080941b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP880"             ,	   0x1180080941b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP881"             ,	   0x1180080941b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP882"             ,	   0x1180080941b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP883"             ,	   0x1180080941b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP884"             ,	   0x1180080941ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP885"             ,	   0x1180080941ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP886"             ,	   0x1180080941bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP887"             ,	   0x1180080941bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP888"             ,	   0x1180080941bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP889"             ,	   0x1180080941bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP890"             ,	   0x1180080941bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP891"             ,	   0x1180080941bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP892"             ,	   0x1180080941be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP893"             ,	   0x1180080941be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP894"             ,	   0x1180080941bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP895"             ,	   0x1180080941bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP896"             ,	   0x1180080941c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP897"             ,	   0x1180080941c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP898"             ,	   0x1180080941c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP899"             ,	   0x1180080941c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP900"             ,	   0x1180080941c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP901"             ,	   0x1180080941c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP902"             ,	   0x1180080941c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP903"             ,	   0x1180080941c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP904"             ,	   0x1180080941c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP905"             ,	   0x1180080941c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP906"             ,	   0x1180080941c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP907"             ,	   0x1180080941c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP908"             ,	   0x1180080941c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP909"             ,	   0x1180080941c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP910"             ,	   0x1180080941c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP911"             ,	   0x1180080941c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP912"             ,	   0x1180080941c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP913"             ,	   0x1180080941c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP914"             ,	   0x1180080941c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP915"             ,	   0x1180080941c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP916"             ,	   0x1180080941ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP917"             ,	   0x1180080941ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP918"             ,	   0x1180080941cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP919"             ,	   0x1180080941cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP920"             ,	   0x1180080941cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP921"             ,	   0x1180080941cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP922"             ,	   0x1180080941cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP923"             ,	   0x1180080941cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP924"             ,	   0x1180080941ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP925"             ,	   0x1180080941ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP926"             ,	   0x1180080941cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP927"             ,	   0x1180080941cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP928"             ,	   0x1180080941d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP929"             ,	   0x1180080941d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP930"             ,	   0x1180080941d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP931"             ,	   0x1180080941d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP932"             ,	   0x1180080941d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP933"             ,	   0x1180080941d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP934"             ,	   0x1180080941d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP935"             ,	   0x1180080941d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP936"             ,	   0x1180080941d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP937"             ,	   0x1180080941d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP938"             ,	   0x1180080941d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP939"             ,	   0x1180080941d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP940"             ,	   0x1180080941d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP941"             ,	   0x1180080941d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP942"             ,	   0x1180080941d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP943"             ,	   0x1180080941d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP944"             ,	   0x1180080941d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP945"             ,	   0x1180080941d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP946"             ,	   0x1180080941d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP947"             ,	   0x1180080941d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP948"             ,	   0x1180080941da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP949"             ,	   0x1180080941da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP950"             ,	   0x1180080941db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP951"             ,	   0x1180080941db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP952"             ,	   0x1180080941dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP953"             ,	   0x1180080941dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP954"             ,	   0x1180080941dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP955"             ,	   0x1180080941dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP956"             ,	   0x1180080941de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP957"             ,	   0x1180080941de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP958"             ,	   0x1180080941df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP959"             ,	   0x1180080941df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP960"             ,	   0x1180080941e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP961"             ,	   0x1180080941e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP962"             ,	   0x1180080941e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP963"             ,	   0x1180080941e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP964"             ,	   0x1180080941e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP965"             ,	   0x1180080941e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP966"             ,	   0x1180080941e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP967"             ,	   0x1180080941e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP968"             ,	   0x1180080941e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP969"             ,	   0x1180080941e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP970"             ,	   0x1180080941e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP971"             ,	   0x1180080941e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP972"             ,	   0x1180080941e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP973"             ,	   0x1180080941e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP974"             ,	   0x1180080941e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP975"             ,	   0x1180080941e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP976"             ,	   0x1180080941e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP977"             ,	   0x1180080941e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP978"             ,	   0x1180080941e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP979"             ,	   0x1180080941e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP980"             ,	   0x1180080941ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP981"             ,	   0x1180080941ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP982"             ,	   0x1180080941eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP983"             ,	   0x1180080941eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP984"             ,	   0x1180080941ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP985"             ,	   0x1180080941ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP986"             ,	   0x1180080941ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP987"             ,	   0x1180080941ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP988"             ,	   0x1180080941ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP989"             ,	   0x1180080941ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP990"             ,	   0x1180080941ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP991"             ,	   0x1180080941ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP992"             ,	   0x1180080941f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP993"             ,	   0x1180080941f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP994"             ,	   0x1180080941f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP995"             ,	   0x1180080941f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP996"             ,	   0x1180080941f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP997"             ,	   0x1180080941f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP998"             ,	   0x1180080941f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP999"             ,	   0x1180080941f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1000"            ,	   0x1180080941f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1001"            ,	   0x1180080941f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1002"            ,	   0x1180080941f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1003"            ,	   0x1180080941f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1004"            ,	   0x1180080941f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1005"            ,	   0x1180080941f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1006"            ,	   0x1180080941f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1007"            ,	   0x1180080941f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1008"            ,	   0x1180080941f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1009"            ,	   0x1180080941f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1010"            ,	   0x1180080941f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1011"            ,	   0x1180080941f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1012"            ,	   0x1180080941fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1013"            ,	   0x1180080941fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1014"            ,	   0x1180080941fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1015"            ,	   0x1180080941fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1016"            ,	   0x1180080941fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1017"            ,	   0x1180080941fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1018"            ,	   0x1180080941fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1019"            ,	   0x1180080941fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1020"            ,	   0x1180080941fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1021"            ,	   0x1180080941fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1022"            ,	   0x1180080941ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1023"            ,	   0x1180080941ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1024"            ,	   0x1180080942000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1025"            ,	   0x1180080942008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1026"            ,	   0x1180080942010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1027"            ,	   0x1180080942018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1028"            ,	   0x1180080942020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1029"            ,	   0x1180080942028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1030"            ,	   0x1180080942030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1031"            ,	   0x1180080942038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1032"            ,	   0x1180080942040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1033"            ,	   0x1180080942048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1034"            ,	   0x1180080942050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1035"            ,	   0x1180080942058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1036"            ,	   0x1180080942060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1037"            ,	   0x1180080942068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1038"            ,	   0x1180080942070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1039"            ,	   0x1180080942078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1040"            ,	   0x1180080942080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1041"            ,	   0x1180080942088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1042"            ,	   0x1180080942090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1043"            ,	   0x1180080942098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1044"            ,	   0x11800809420a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1045"            ,	   0x11800809420a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1046"            ,	   0x11800809420b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1047"            ,	   0x11800809420b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1048"            ,	   0x11800809420c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1049"            ,	   0x11800809420c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1050"            ,	   0x11800809420d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1051"            ,	   0x11800809420d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1052"            ,	   0x11800809420e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1053"            ,	   0x11800809420e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1054"            ,	   0x11800809420f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1055"            ,	   0x11800809420f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1056"            ,	   0x1180080942100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1057"            ,	   0x1180080942108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1058"            ,	   0x1180080942110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1059"            ,	   0x1180080942118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1060"            ,	   0x1180080942120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1061"            ,	   0x1180080942128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1062"            ,	   0x1180080942130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1063"            ,	   0x1180080942138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1064"            ,	   0x1180080942140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1065"            ,	   0x1180080942148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1066"            ,	   0x1180080942150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1067"            ,	   0x1180080942158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1068"            ,	   0x1180080942160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1069"            ,	   0x1180080942168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1070"            ,	   0x1180080942170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1071"            ,	   0x1180080942178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1072"            ,	   0x1180080942180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1073"            ,	   0x1180080942188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1074"            ,	   0x1180080942190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1075"            ,	   0x1180080942198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1076"            ,	   0x11800809421a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1077"            ,	   0x11800809421a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1078"            ,	   0x11800809421b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1079"            ,	   0x11800809421b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1080"            ,	   0x11800809421c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1081"            ,	   0x11800809421c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1082"            ,	   0x11800809421d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1083"            ,	   0x11800809421d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1084"            ,	   0x11800809421e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1085"            ,	   0x11800809421e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1086"            ,	   0x11800809421f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1087"            ,	   0x11800809421f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1088"            ,	   0x1180080942200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1089"            ,	   0x1180080942208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1090"            ,	   0x1180080942210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1091"            ,	   0x1180080942218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1092"            ,	   0x1180080942220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1093"            ,	   0x1180080942228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1094"            ,	   0x1180080942230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1095"            ,	   0x1180080942238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1096"            ,	   0x1180080942240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1097"            ,	   0x1180080942248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1098"            ,	   0x1180080942250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1099"            ,	   0x1180080942258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1100"            ,	   0x1180080942260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1101"            ,	   0x1180080942268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1102"            ,	   0x1180080942270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1103"            ,	   0x1180080942278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1104"            ,	   0x1180080942280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1105"            ,	   0x1180080942288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1106"            ,	   0x1180080942290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1107"            ,	   0x1180080942298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1108"            ,	   0x11800809422a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1109"            ,	   0x11800809422a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1110"            ,	   0x11800809422b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1111"            ,	   0x11800809422b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1112"            ,	   0x11800809422c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1113"            ,	   0x11800809422c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1114"            ,	   0x11800809422d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1115"            ,	   0x11800809422d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1116"            ,	   0x11800809422e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1117"            ,	   0x11800809422e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1118"            ,	   0x11800809422f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1119"            ,	   0x11800809422f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1120"            ,	   0x1180080942300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1121"            ,	   0x1180080942308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1122"            ,	   0x1180080942310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1123"            ,	   0x1180080942318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1124"            ,	   0x1180080942320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1125"            ,	   0x1180080942328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1126"            ,	   0x1180080942330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1127"            ,	   0x1180080942338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1128"            ,	   0x1180080942340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1129"            ,	   0x1180080942348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1130"            ,	   0x1180080942350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1131"            ,	   0x1180080942358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1132"            ,	   0x1180080942360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1133"            ,	   0x1180080942368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1134"            ,	   0x1180080942370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1135"            ,	   0x1180080942378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1136"            ,	   0x1180080942380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1137"            ,	   0x1180080942388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1138"            ,	   0x1180080942390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1139"            ,	   0x1180080942398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1140"            ,	   0x11800809423a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1141"            ,	   0x11800809423a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1142"            ,	   0x11800809423b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1143"            ,	   0x11800809423b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1144"            ,	   0x11800809423c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1145"            ,	   0x11800809423c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1146"            ,	   0x11800809423d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1147"            ,	   0x11800809423d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1148"            ,	   0x11800809423e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1149"            ,	   0x11800809423e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1150"            ,	   0x11800809423f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1151"            ,	   0x11800809423f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1152"            ,	   0x1180080942400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1153"            ,	   0x1180080942408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1154"            ,	   0x1180080942410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1155"            ,	   0x1180080942418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1156"            ,	   0x1180080942420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1157"            ,	   0x1180080942428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1158"            ,	   0x1180080942430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1159"            ,	   0x1180080942438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1160"            ,	   0x1180080942440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1161"            ,	   0x1180080942448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1162"            ,	   0x1180080942450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1163"            ,	   0x1180080942458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1164"            ,	   0x1180080942460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1165"            ,	   0x1180080942468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1166"            ,	   0x1180080942470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1167"            ,	   0x1180080942478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1168"            ,	   0x1180080942480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1169"            ,	   0x1180080942488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1170"            ,	   0x1180080942490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1171"            ,	   0x1180080942498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1172"            ,	   0x11800809424a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1173"            ,	   0x11800809424a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1174"            ,	   0x11800809424b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1175"            ,	   0x11800809424b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1176"            ,	   0x11800809424c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1177"            ,	   0x11800809424c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1178"            ,	   0x11800809424d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1179"            ,	   0x11800809424d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1180"            ,	   0x11800809424e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1181"            ,	   0x11800809424e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1182"            ,	   0x11800809424f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1183"            ,	   0x11800809424f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1184"            ,	   0x1180080942500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1185"            ,	   0x1180080942508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1186"            ,	   0x1180080942510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1187"            ,	   0x1180080942518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1188"            ,	   0x1180080942520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1189"            ,	   0x1180080942528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1190"            ,	   0x1180080942530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1191"            ,	   0x1180080942538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1192"            ,	   0x1180080942540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1193"            ,	   0x1180080942548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1194"            ,	   0x1180080942550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1195"            ,	   0x1180080942558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1196"            ,	   0x1180080942560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1197"            ,	   0x1180080942568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1198"            ,	   0x1180080942570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1199"            ,	   0x1180080942578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1200"            ,	   0x1180080942580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1201"            ,	   0x1180080942588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1202"            ,	   0x1180080942590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1203"            ,	   0x1180080942598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1204"            ,	   0x11800809425a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1205"            ,	   0x11800809425a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1206"            ,	   0x11800809425b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1207"            ,	   0x11800809425b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1208"            ,	   0x11800809425c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1209"            ,	   0x11800809425c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1210"            ,	   0x11800809425d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1211"            ,	   0x11800809425d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1212"            ,	   0x11800809425e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1213"            ,	   0x11800809425e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1214"            ,	   0x11800809425f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1215"            ,	   0x11800809425f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1216"            ,	   0x1180080942600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1217"            ,	   0x1180080942608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1218"            ,	   0x1180080942610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1219"            ,	   0x1180080942618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1220"            ,	   0x1180080942620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1221"            ,	   0x1180080942628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1222"            ,	   0x1180080942630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1223"            ,	   0x1180080942638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1224"            ,	   0x1180080942640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1225"            ,	   0x1180080942648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1226"            ,	   0x1180080942650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1227"            ,	   0x1180080942658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1228"            ,	   0x1180080942660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1229"            ,	   0x1180080942668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1230"            ,	   0x1180080942670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1231"            ,	   0x1180080942678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1232"            ,	   0x1180080942680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1233"            ,	   0x1180080942688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1234"            ,	   0x1180080942690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1235"            ,	   0x1180080942698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1236"            ,	   0x11800809426a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1237"            ,	   0x11800809426a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1238"            ,	   0x11800809426b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1239"            ,	   0x11800809426b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1240"            ,	   0x11800809426c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1241"            ,	   0x11800809426c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1242"            ,	   0x11800809426d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1243"            ,	   0x11800809426d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1244"            ,	   0x11800809426e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1245"            ,	   0x11800809426e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1246"            ,	   0x11800809426f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1247"            ,	   0x11800809426f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1248"            ,	   0x1180080942700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1249"            ,	   0x1180080942708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1250"            ,	   0x1180080942710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1251"            ,	   0x1180080942718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1252"            ,	   0x1180080942720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1253"            ,	   0x1180080942728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1254"            ,	   0x1180080942730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1255"            ,	   0x1180080942738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1256"            ,	   0x1180080942740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1257"            ,	   0x1180080942748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1258"            ,	   0x1180080942750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1259"            ,	   0x1180080942758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1260"            ,	   0x1180080942760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1261"            ,	   0x1180080942768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1262"            ,	   0x1180080942770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1263"            ,	   0x1180080942778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1264"            ,	   0x1180080942780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1265"            ,	   0x1180080942788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1266"            ,	   0x1180080942790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1267"            ,	   0x1180080942798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1268"            ,	   0x11800809427a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1269"            ,	   0x11800809427a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1270"            ,	   0x11800809427b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1271"            ,	   0x11800809427b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1272"            ,	   0x11800809427c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1273"            ,	   0x11800809427c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1274"            ,	   0x11800809427d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1275"            ,	   0x11800809427d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1276"            ,	   0x11800809427e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1277"            ,	   0x11800809427e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1278"            ,	   0x11800809427f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1279"            ,	   0x11800809427f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1280"            ,	   0x1180080942800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1281"            ,	   0x1180080942808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1282"            ,	   0x1180080942810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1283"            ,	   0x1180080942818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1284"            ,	   0x1180080942820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1285"            ,	   0x1180080942828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1286"            ,	   0x1180080942830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1287"            ,	   0x1180080942838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1288"            ,	   0x1180080942840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1289"            ,	   0x1180080942848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1290"            ,	   0x1180080942850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1291"            ,	   0x1180080942858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1292"            ,	   0x1180080942860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1293"            ,	   0x1180080942868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1294"            ,	   0x1180080942870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1295"            ,	   0x1180080942878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1296"            ,	   0x1180080942880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1297"            ,	   0x1180080942888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1298"            ,	   0x1180080942890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1299"            ,	   0x1180080942898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1300"            ,	   0x11800809428a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1301"            ,	   0x11800809428a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1302"            ,	   0x11800809428b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1303"            ,	   0x11800809428b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1304"            ,	   0x11800809428c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1305"            ,	   0x11800809428c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1306"            ,	   0x11800809428d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1307"            ,	   0x11800809428d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1308"            ,	   0x11800809428e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1309"            ,	   0x11800809428e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1310"            ,	   0x11800809428f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1311"            ,	   0x11800809428f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1312"            ,	   0x1180080942900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1313"            ,	   0x1180080942908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1314"            ,	   0x1180080942910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1315"            ,	   0x1180080942918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1316"            ,	   0x1180080942920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1317"            ,	   0x1180080942928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1318"            ,	   0x1180080942930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1319"            ,	   0x1180080942938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1320"            ,	   0x1180080942940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1321"            ,	   0x1180080942948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1322"            ,	   0x1180080942950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1323"            ,	   0x1180080942958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1324"            ,	   0x1180080942960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1325"            ,	   0x1180080942968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1326"            ,	   0x1180080942970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1327"            ,	   0x1180080942978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1328"            ,	   0x1180080942980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1329"            ,	   0x1180080942988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1330"            ,	   0x1180080942990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1331"            ,	   0x1180080942998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1332"            ,	   0x11800809429a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1333"            ,	   0x11800809429a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1334"            ,	   0x11800809429b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1335"            ,	   0x11800809429b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1336"            ,	   0x11800809429c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1337"            ,	   0x11800809429c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1338"            ,	   0x11800809429d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1339"            ,	   0x11800809429d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1340"            ,	   0x11800809429e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1341"            ,	   0x11800809429e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1342"            ,	   0x11800809429f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1343"            ,	   0x11800809429f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1344"            ,	   0x1180080942a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1345"            ,	   0x1180080942a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1346"            ,	   0x1180080942a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1347"            ,	   0x1180080942a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1348"            ,	   0x1180080942a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1349"            ,	   0x1180080942a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1350"            ,	   0x1180080942a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1351"            ,	   0x1180080942a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1352"            ,	   0x1180080942a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1353"            ,	   0x1180080942a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1354"            ,	   0x1180080942a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1355"            ,	   0x1180080942a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1356"            ,	   0x1180080942a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1357"            ,	   0x1180080942a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1358"            ,	   0x1180080942a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1359"            ,	   0x1180080942a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1360"            ,	   0x1180080942a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1361"            ,	   0x1180080942a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1362"            ,	   0x1180080942a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1363"            ,	   0x1180080942a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1364"            ,	   0x1180080942aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1365"            ,	   0x1180080942aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1366"            ,	   0x1180080942ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1367"            ,	   0x1180080942ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1368"            ,	   0x1180080942ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1369"            ,	   0x1180080942ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1370"            ,	   0x1180080942ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1371"            ,	   0x1180080942ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1372"            ,	   0x1180080942ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1373"            ,	   0x1180080942ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1374"            ,	   0x1180080942af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1375"            ,	   0x1180080942af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1376"            ,	   0x1180080942b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1377"            ,	   0x1180080942b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1378"            ,	   0x1180080942b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1379"            ,	   0x1180080942b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1380"            ,	   0x1180080942b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1381"            ,	   0x1180080942b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1382"            ,	   0x1180080942b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1383"            ,	   0x1180080942b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1384"            ,	   0x1180080942b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1385"            ,	   0x1180080942b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1386"            ,	   0x1180080942b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1387"            ,	   0x1180080942b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1388"            ,	   0x1180080942b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1389"            ,	   0x1180080942b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1390"            ,	   0x1180080942b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1391"            ,	   0x1180080942b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1392"            ,	   0x1180080942b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1393"            ,	   0x1180080942b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1394"            ,	   0x1180080942b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1395"            ,	   0x1180080942b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1396"            ,	   0x1180080942ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1397"            ,	   0x1180080942ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1398"            ,	   0x1180080942bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1399"            ,	   0x1180080942bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1400"            ,	   0x1180080942bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1401"            ,	   0x1180080942bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1402"            ,	   0x1180080942bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1403"            ,	   0x1180080942bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1404"            ,	   0x1180080942be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1405"            ,	   0x1180080942be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1406"            ,	   0x1180080942bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1407"            ,	   0x1180080942bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1408"            ,	   0x1180080942c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1409"            ,	   0x1180080942c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1410"            ,	   0x1180080942c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1411"            ,	   0x1180080942c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1412"            ,	   0x1180080942c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1413"            ,	   0x1180080942c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1414"            ,	   0x1180080942c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1415"            ,	   0x1180080942c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1416"            ,	   0x1180080942c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1417"            ,	   0x1180080942c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1418"            ,	   0x1180080942c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1419"            ,	   0x1180080942c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1420"            ,	   0x1180080942c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1421"            ,	   0x1180080942c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1422"            ,	   0x1180080942c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1423"            ,	   0x1180080942c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1424"            ,	   0x1180080942c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1425"            ,	   0x1180080942c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1426"            ,	   0x1180080942c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1427"            ,	   0x1180080942c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1428"            ,	   0x1180080942ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1429"            ,	   0x1180080942ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1430"            ,	   0x1180080942cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1431"            ,	   0x1180080942cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1432"            ,	   0x1180080942cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1433"            ,	   0x1180080942cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1434"            ,	   0x1180080942cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1435"            ,	   0x1180080942cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1436"            ,	   0x1180080942ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1437"            ,	   0x1180080942ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1438"            ,	   0x1180080942cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1439"            ,	   0x1180080942cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1440"            ,	   0x1180080942d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1441"            ,	   0x1180080942d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1442"            ,	   0x1180080942d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1443"            ,	   0x1180080942d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1444"            ,	   0x1180080942d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1445"            ,	   0x1180080942d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1446"            ,	   0x1180080942d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1447"            ,	   0x1180080942d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1448"            ,	   0x1180080942d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1449"            ,	   0x1180080942d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1450"            ,	   0x1180080942d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1451"            ,	   0x1180080942d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1452"            ,	   0x1180080942d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1453"            ,	   0x1180080942d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1454"            ,	   0x1180080942d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1455"            ,	   0x1180080942d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1456"            ,	   0x1180080942d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1457"            ,	   0x1180080942d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1458"            ,	   0x1180080942d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1459"            ,	   0x1180080942d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1460"            ,	   0x1180080942da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1461"            ,	   0x1180080942da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1462"            ,	   0x1180080942db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1463"            ,	   0x1180080942db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1464"            ,	   0x1180080942dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1465"            ,	   0x1180080942dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1466"            ,	   0x1180080942dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1467"            ,	   0x1180080942dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1468"            ,	   0x1180080942de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1469"            ,	   0x1180080942de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1470"            ,	   0x1180080942df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1471"            ,	   0x1180080942df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1472"            ,	   0x1180080942e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1473"            ,	   0x1180080942e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1474"            ,	   0x1180080942e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1475"            ,	   0x1180080942e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1476"            ,	   0x1180080942e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1477"            ,	   0x1180080942e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1478"            ,	   0x1180080942e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1479"            ,	   0x1180080942e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1480"            ,	   0x1180080942e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1481"            ,	   0x1180080942e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1482"            ,	   0x1180080942e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1483"            ,	   0x1180080942e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1484"            ,	   0x1180080942e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1485"            ,	   0x1180080942e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1486"            ,	   0x1180080942e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1487"            ,	   0x1180080942e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1488"            ,	   0x1180080942e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1489"            ,	   0x1180080942e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1490"            ,	   0x1180080942e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1491"            ,	   0x1180080942e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1492"            ,	   0x1180080942ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1493"            ,	   0x1180080942ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1494"            ,	   0x1180080942eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1495"            ,	   0x1180080942eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1496"            ,	   0x1180080942ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1497"            ,	   0x1180080942ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1498"            ,	   0x1180080942ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1499"            ,	   0x1180080942ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1500"            ,	   0x1180080942ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1501"            ,	   0x1180080942ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1502"            ,	   0x1180080942ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1503"            ,	   0x1180080942ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1504"            ,	   0x1180080942f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1505"            ,	   0x1180080942f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1506"            ,	   0x1180080942f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1507"            ,	   0x1180080942f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1508"            ,	   0x1180080942f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1509"            ,	   0x1180080942f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1510"            ,	   0x1180080942f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1511"            ,	   0x1180080942f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1512"            ,	   0x1180080942f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1513"            ,	   0x1180080942f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1514"            ,	   0x1180080942f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1515"            ,	   0x1180080942f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1516"            ,	   0x1180080942f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1517"            ,	   0x1180080942f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1518"            ,	   0x1180080942f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1519"            ,	   0x1180080942f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1520"            ,	   0x1180080942f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1521"            ,	   0x1180080942f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1522"            ,	   0x1180080942f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1523"            ,	   0x1180080942f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1524"            ,	   0x1180080942fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1525"            ,	   0x1180080942fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1526"            ,	   0x1180080942fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1527"            ,	   0x1180080942fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1528"            ,	   0x1180080942fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1529"            ,	   0x1180080942fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1530"            ,	   0x1180080942fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1531"            ,	   0x1180080942fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1532"            ,	   0x1180080942fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1533"            ,	   0x1180080942fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1534"            ,	   0x1180080942ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1535"            ,	   0x1180080942ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1536"            ,	   0x1180080943000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1537"            ,	   0x1180080943008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1538"            ,	   0x1180080943010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1539"            ,	   0x1180080943018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1540"            ,	   0x1180080943020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1541"            ,	   0x1180080943028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1542"            ,	   0x1180080943030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1543"            ,	   0x1180080943038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1544"            ,	   0x1180080943040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1545"            ,	   0x1180080943048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1546"            ,	   0x1180080943050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1547"            ,	   0x1180080943058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1548"            ,	   0x1180080943060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1549"            ,	   0x1180080943068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1550"            ,	   0x1180080943070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1551"            ,	   0x1180080943078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1552"            ,	   0x1180080943080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1553"            ,	   0x1180080943088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1554"            ,	   0x1180080943090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1555"            ,	   0x1180080943098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1556"            ,	   0x11800809430a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1557"            ,	   0x11800809430a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1558"            ,	   0x11800809430b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1559"            ,	   0x11800809430b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1560"            ,	   0x11800809430c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1561"            ,	   0x11800809430c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1562"            ,	   0x11800809430d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1563"            ,	   0x11800809430d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1564"            ,	   0x11800809430e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1565"            ,	   0x11800809430e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1566"            ,	   0x11800809430f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1567"            ,	   0x11800809430f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1568"            ,	   0x1180080943100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1569"            ,	   0x1180080943108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1570"            ,	   0x1180080943110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1571"            ,	   0x1180080943118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1572"            ,	   0x1180080943120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1573"            ,	   0x1180080943128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1574"            ,	   0x1180080943130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1575"            ,	   0x1180080943138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1576"            ,	   0x1180080943140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1577"            ,	   0x1180080943148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1578"            ,	   0x1180080943150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1579"            ,	   0x1180080943158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1580"            ,	   0x1180080943160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1581"            ,	   0x1180080943168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1582"            ,	   0x1180080943170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1583"            ,	   0x1180080943178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1584"            ,	   0x1180080943180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1585"            ,	   0x1180080943188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1586"            ,	   0x1180080943190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1587"            ,	   0x1180080943198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1588"            ,	   0x11800809431a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1589"            ,	   0x11800809431a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1590"            ,	   0x11800809431b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1591"            ,	   0x11800809431b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1592"            ,	   0x11800809431c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1593"            ,	   0x11800809431c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1594"            ,	   0x11800809431d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1595"            ,	   0x11800809431d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1596"            ,	   0x11800809431e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1597"            ,	   0x11800809431e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1598"            ,	   0x11800809431f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1599"            ,	   0x11800809431f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1600"            ,	   0x1180080943200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1601"            ,	   0x1180080943208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1602"            ,	   0x1180080943210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1603"            ,	   0x1180080943218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1604"            ,	   0x1180080943220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1605"            ,	   0x1180080943228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1606"            ,	   0x1180080943230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1607"            ,	   0x1180080943238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1608"            ,	   0x1180080943240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1609"            ,	   0x1180080943248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1610"            ,	   0x1180080943250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1611"            ,	   0x1180080943258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1612"            ,	   0x1180080943260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1613"            ,	   0x1180080943268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1614"            ,	   0x1180080943270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1615"            ,	   0x1180080943278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1616"            ,	   0x1180080943280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1617"            ,	   0x1180080943288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1618"            ,	   0x1180080943290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1619"            ,	   0x1180080943298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1620"            ,	   0x11800809432a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1621"            ,	   0x11800809432a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1622"            ,	   0x11800809432b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1623"            ,	   0x11800809432b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1624"            ,	   0x11800809432c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1625"            ,	   0x11800809432c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1626"            ,	   0x11800809432d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1627"            ,	   0x11800809432d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1628"            ,	   0x11800809432e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1629"            ,	   0x11800809432e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1630"            ,	   0x11800809432f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1631"            ,	   0x11800809432f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1632"            ,	   0x1180080943300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1633"            ,	   0x1180080943308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1634"            ,	   0x1180080943310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1635"            ,	   0x1180080943318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1636"            ,	   0x1180080943320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1637"            ,	   0x1180080943328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1638"            ,	   0x1180080943330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1639"            ,	   0x1180080943338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1640"            ,	   0x1180080943340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1641"            ,	   0x1180080943348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1642"            ,	   0x1180080943350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1643"            ,	   0x1180080943358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1644"            ,	   0x1180080943360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1645"            ,	   0x1180080943368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1646"            ,	   0x1180080943370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1647"            ,	   0x1180080943378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1648"            ,	   0x1180080943380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1649"            ,	   0x1180080943388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1650"            ,	   0x1180080943390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1651"            ,	   0x1180080943398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1652"            ,	   0x11800809433a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1653"            ,	   0x11800809433a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1654"            ,	   0x11800809433b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1655"            ,	   0x11800809433b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1656"            ,	   0x11800809433c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1657"            ,	   0x11800809433c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1658"            ,	   0x11800809433d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1659"            ,	   0x11800809433d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1660"            ,	   0x11800809433e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1661"            ,	   0x11800809433e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1662"            ,	   0x11800809433f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1663"            ,	   0x11800809433f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1664"            ,	   0x1180080943400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1665"            ,	   0x1180080943408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1666"            ,	   0x1180080943410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1667"            ,	   0x1180080943418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1668"            ,	   0x1180080943420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1669"            ,	   0x1180080943428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1670"            ,	   0x1180080943430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1671"            ,	   0x1180080943438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1672"            ,	   0x1180080943440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1673"            ,	   0x1180080943448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1674"            ,	   0x1180080943450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1675"            ,	   0x1180080943458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1676"            ,	   0x1180080943460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1677"            ,	   0x1180080943468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1678"            ,	   0x1180080943470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1679"            ,	   0x1180080943478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1680"            ,	   0x1180080943480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1681"            ,	   0x1180080943488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1682"            ,	   0x1180080943490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1683"            ,	   0x1180080943498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1684"            ,	   0x11800809434a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1685"            ,	   0x11800809434a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1686"            ,	   0x11800809434b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1687"            ,	   0x11800809434b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1688"            ,	   0x11800809434c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1689"            ,	   0x11800809434c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1690"            ,	   0x11800809434d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1691"            ,	   0x11800809434d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1692"            ,	   0x11800809434e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1693"            ,	   0x11800809434e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1694"            ,	   0x11800809434f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1695"            ,	   0x11800809434f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1696"            ,	   0x1180080943500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1697"            ,	   0x1180080943508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1698"            ,	   0x1180080943510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1699"            ,	   0x1180080943518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1700"            ,	   0x1180080943520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1701"            ,	   0x1180080943528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1702"            ,	   0x1180080943530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1703"            ,	   0x1180080943538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1704"            ,	   0x1180080943540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1705"            ,	   0x1180080943548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1706"            ,	   0x1180080943550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1707"            ,	   0x1180080943558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1708"            ,	   0x1180080943560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1709"            ,	   0x1180080943568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1710"            ,	   0x1180080943570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1711"            ,	   0x1180080943578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1712"            ,	   0x1180080943580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1713"            ,	   0x1180080943588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1714"            ,	   0x1180080943590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1715"            ,	   0x1180080943598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1716"            ,	   0x11800809435a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1717"            ,	   0x11800809435a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1718"            ,	   0x11800809435b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1719"            ,	   0x11800809435b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1720"            ,	   0x11800809435c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1721"            ,	   0x11800809435c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1722"            ,	   0x11800809435d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1723"            ,	   0x11800809435d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1724"            ,	   0x11800809435e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1725"            ,	   0x11800809435e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1726"            ,	   0x11800809435f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1727"            ,	   0x11800809435f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1728"            ,	   0x1180080943600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1729"            ,	   0x1180080943608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1730"            ,	   0x1180080943610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1731"            ,	   0x1180080943618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1732"            ,	   0x1180080943620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1733"            ,	   0x1180080943628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1734"            ,	   0x1180080943630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1735"            ,	   0x1180080943638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1736"            ,	   0x1180080943640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1737"            ,	   0x1180080943648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1738"            ,	   0x1180080943650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1739"            ,	   0x1180080943658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1740"            ,	   0x1180080943660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1741"            ,	   0x1180080943668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1742"            ,	   0x1180080943670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1743"            ,	   0x1180080943678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1744"            ,	   0x1180080943680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1745"            ,	   0x1180080943688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1746"            ,	   0x1180080943690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1747"            ,	   0x1180080943698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1748"            ,	   0x11800809436a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1749"            ,	   0x11800809436a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1750"            ,	   0x11800809436b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1751"            ,	   0x11800809436b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1752"            ,	   0x11800809436c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1753"            ,	   0x11800809436c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1754"            ,	   0x11800809436d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1755"            ,	   0x11800809436d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1756"            ,	   0x11800809436e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1757"            ,	   0x11800809436e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1758"            ,	   0x11800809436f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1759"            ,	   0x11800809436f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1760"            ,	   0x1180080943700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1761"            ,	   0x1180080943708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1762"            ,	   0x1180080943710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1763"            ,	   0x1180080943718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1764"            ,	   0x1180080943720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1765"            ,	   0x1180080943728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1766"            ,	   0x1180080943730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1767"            ,	   0x1180080943738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1768"            ,	   0x1180080943740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1769"            ,	   0x1180080943748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1770"            ,	   0x1180080943750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1771"            ,	   0x1180080943758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1772"            ,	   0x1180080943760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1773"            ,	   0x1180080943768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1774"            ,	   0x1180080943770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1775"            ,	   0x1180080943778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1776"            ,	   0x1180080943780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1777"            ,	   0x1180080943788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1778"            ,	   0x1180080943790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1779"            ,	   0x1180080943798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1780"            ,	   0x11800809437a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1781"            ,	   0x11800809437a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1782"            ,	   0x11800809437b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1783"            ,	   0x11800809437b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1784"            ,	   0x11800809437c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1785"            ,	   0x11800809437c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1786"            ,	   0x11800809437d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1787"            ,	   0x11800809437d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1788"            ,	   0x11800809437e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1789"            ,	   0x11800809437e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1790"            ,	   0x11800809437f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1791"            ,	   0x11800809437f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1792"            ,	   0x1180080943800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1793"            ,	   0x1180080943808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1794"            ,	   0x1180080943810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1795"            ,	   0x1180080943818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1796"            ,	   0x1180080943820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1797"            ,	   0x1180080943828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1798"            ,	   0x1180080943830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1799"            ,	   0x1180080943838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1800"            ,	   0x1180080943840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1801"            ,	   0x1180080943848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1802"            ,	   0x1180080943850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1803"            ,	   0x1180080943858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1804"            ,	   0x1180080943860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1805"            ,	   0x1180080943868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1806"            ,	   0x1180080943870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1807"            ,	   0x1180080943878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1808"            ,	   0x1180080943880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1809"            ,	   0x1180080943888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1810"            ,	   0x1180080943890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1811"            ,	   0x1180080943898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1812"            ,	   0x11800809438a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1813"            ,	   0x11800809438a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1814"            ,	   0x11800809438b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1815"            ,	   0x11800809438b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1816"            ,	   0x11800809438c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1817"            ,	   0x11800809438c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1818"            ,	   0x11800809438d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1819"            ,	   0x11800809438d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1820"            ,	   0x11800809438e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1821"            ,	   0x11800809438e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1822"            ,	   0x11800809438f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1823"            ,	   0x11800809438f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1824"            ,	   0x1180080943900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1825"            ,	   0x1180080943908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1826"            ,	   0x1180080943910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1827"            ,	   0x1180080943918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1828"            ,	   0x1180080943920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1829"            ,	   0x1180080943928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1830"            ,	   0x1180080943930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1831"            ,	   0x1180080943938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1832"            ,	   0x1180080943940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1833"            ,	   0x1180080943948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1834"            ,	   0x1180080943950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1835"            ,	   0x1180080943958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1836"            ,	   0x1180080943960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1837"            ,	   0x1180080943968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1838"            ,	   0x1180080943970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1839"            ,	   0x1180080943978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1840"            ,	   0x1180080943980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1841"            ,	   0x1180080943988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1842"            ,	   0x1180080943990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1843"            ,	   0x1180080943998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1844"            ,	   0x11800809439a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1845"            ,	   0x11800809439a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1846"            ,	   0x11800809439b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1847"            ,	   0x11800809439b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1848"            ,	   0x11800809439c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1849"            ,	   0x11800809439c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1850"            ,	   0x11800809439d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1851"            ,	   0x11800809439d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1852"            ,	   0x11800809439e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1853"            ,	   0x11800809439e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1854"            ,	   0x11800809439f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1855"            ,	   0x11800809439f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1856"            ,	   0x1180080943a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1857"            ,	   0x1180080943a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1858"            ,	   0x1180080943a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1859"            ,	   0x1180080943a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1860"            ,	   0x1180080943a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1861"            ,	   0x1180080943a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1862"            ,	   0x1180080943a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1863"            ,	   0x1180080943a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1864"            ,	   0x1180080943a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1865"            ,	   0x1180080943a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1866"            ,	   0x1180080943a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1867"            ,	   0x1180080943a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1868"            ,	   0x1180080943a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1869"            ,	   0x1180080943a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1870"            ,	   0x1180080943a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1871"            ,	   0x1180080943a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1872"            ,	   0x1180080943a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1873"            ,	   0x1180080943a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1874"            ,	   0x1180080943a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1875"            ,	   0x1180080943a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1876"            ,	   0x1180080943aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1877"            ,	   0x1180080943aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1878"            ,	   0x1180080943ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1879"            ,	   0x1180080943ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1880"            ,	   0x1180080943ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1881"            ,	   0x1180080943ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1882"            ,	   0x1180080943ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1883"            ,	   0x1180080943ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1884"            ,	   0x1180080943ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1885"            ,	   0x1180080943ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1886"            ,	   0x1180080943af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1887"            ,	   0x1180080943af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1888"            ,	   0x1180080943b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1889"            ,	   0x1180080943b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1890"            ,	   0x1180080943b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1891"            ,	   0x1180080943b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1892"            ,	   0x1180080943b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1893"            ,	   0x1180080943b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1894"            ,	   0x1180080943b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1895"            ,	   0x1180080943b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1896"            ,	   0x1180080943b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1897"            ,	   0x1180080943b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1898"            ,	   0x1180080943b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1899"            ,	   0x1180080943b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1900"            ,	   0x1180080943b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1901"            ,	   0x1180080943b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1902"            ,	   0x1180080943b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1903"            ,	   0x1180080943b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1904"            ,	   0x1180080943b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1905"            ,	   0x1180080943b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1906"            ,	   0x1180080943b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1907"            ,	   0x1180080943b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1908"            ,	   0x1180080943ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1909"            ,	   0x1180080943ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1910"            ,	   0x1180080943bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1911"            ,	   0x1180080943bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1912"            ,	   0x1180080943bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1913"            ,	   0x1180080943bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1914"            ,	   0x1180080943bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1915"            ,	   0x1180080943bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1916"            ,	   0x1180080943be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1917"            ,	   0x1180080943be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1918"            ,	   0x1180080943bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1919"            ,	   0x1180080943bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1920"            ,	   0x1180080943c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1921"            ,	   0x1180080943c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1922"            ,	   0x1180080943c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1923"            ,	   0x1180080943c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1924"            ,	   0x1180080943c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1925"            ,	   0x1180080943c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1926"            ,	   0x1180080943c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1927"            ,	   0x1180080943c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1928"            ,	   0x1180080943c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1929"            ,	   0x1180080943c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1930"            ,	   0x1180080943c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1931"            ,	   0x1180080943c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1932"            ,	   0x1180080943c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1933"            ,	   0x1180080943c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1934"            ,	   0x1180080943c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1935"            ,	   0x1180080943c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1936"            ,	   0x1180080943c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1937"            ,	   0x1180080943c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1938"            ,	   0x1180080943c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1939"            ,	   0x1180080943c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1940"            ,	   0x1180080943ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1941"            ,	   0x1180080943ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1942"            ,	   0x1180080943cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1943"            ,	   0x1180080943cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1944"            ,	   0x1180080943cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1945"            ,	   0x1180080943cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1946"            ,	   0x1180080943cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1947"            ,	   0x1180080943cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1948"            ,	   0x1180080943ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1949"            ,	   0x1180080943ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1950"            ,	   0x1180080943cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1951"            ,	   0x1180080943cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1952"            ,	   0x1180080943d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1953"            ,	   0x1180080943d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1954"            ,	   0x1180080943d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1955"            ,	   0x1180080943d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1956"            ,	   0x1180080943d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1957"            ,	   0x1180080943d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1958"            ,	   0x1180080943d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1959"            ,	   0x1180080943d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1960"            ,	   0x1180080943d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1961"            ,	   0x1180080943d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1962"            ,	   0x1180080943d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1963"            ,	   0x1180080943d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1964"            ,	   0x1180080943d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1965"            ,	   0x1180080943d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1966"            ,	   0x1180080943d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1967"            ,	   0x1180080943d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1968"            ,	   0x1180080943d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1969"            ,	   0x1180080943d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1970"            ,	   0x1180080943d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1971"            ,	   0x1180080943d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1972"            ,	   0x1180080943da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1973"            ,	   0x1180080943da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1974"            ,	   0x1180080943db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1975"            ,	   0x1180080943db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1976"            ,	   0x1180080943dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1977"            ,	   0x1180080943dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1978"            ,	   0x1180080943dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1979"            ,	   0x1180080943dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1980"            ,	   0x1180080943de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1981"            ,	   0x1180080943de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1982"            ,	   0x1180080943df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1983"            ,	   0x1180080943df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1984"            ,	   0x1180080943e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1985"            ,	   0x1180080943e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1986"            ,	   0x1180080943e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1987"            ,	   0x1180080943e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1988"            ,	   0x1180080943e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1989"            ,	   0x1180080943e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1990"            ,	   0x1180080943e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1991"            ,	   0x1180080943e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1992"            ,	   0x1180080943e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1993"            ,	   0x1180080943e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1994"            ,	   0x1180080943e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1995"            ,	   0x1180080943e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1996"            ,	   0x1180080943e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1997"            ,	   0x1180080943e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1998"            ,	   0x1180080943e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP1999"            ,	   0x1180080943e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2000"            ,	   0x1180080943e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2001"            ,	   0x1180080943e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2002"            ,	   0x1180080943e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2003"            ,	   0x1180080943e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2004"            ,	   0x1180080943ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2005"            ,	   0x1180080943ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2006"            ,	   0x1180080943eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2007"            ,	   0x1180080943eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2008"            ,	   0x1180080943ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2009"            ,	   0x1180080943ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2010"            ,	   0x1180080943ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2011"            ,	   0x1180080943ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2012"            ,	   0x1180080943ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2013"            ,	   0x1180080943ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2014"            ,	   0x1180080943ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2015"            ,	   0x1180080943ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2016"            ,	   0x1180080943f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2017"            ,	   0x1180080943f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2018"            ,	   0x1180080943f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2019"            ,	   0x1180080943f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2020"            ,	   0x1180080943f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2021"            ,	   0x1180080943f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2022"            ,	   0x1180080943f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2023"            ,	   0x1180080943f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2024"            ,	   0x1180080943f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2025"            ,	   0x1180080943f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2026"            ,	   0x1180080943f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2027"            ,	   0x1180080943f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2028"            ,	   0x1180080943f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2029"            ,	   0x1180080943f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2030"            ,	   0x1180080943f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2031"            ,	   0x1180080943f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2032"            ,	   0x1180080943f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2033"            ,	   0x1180080943f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2034"            ,	   0x1180080943f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2035"            ,	   0x1180080943f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2036"            ,	   0x1180080943fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2037"            ,	   0x1180080943fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2038"            ,	   0x1180080943fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2039"            ,	   0x1180080943fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2040"            ,	   0x1180080943fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2041"            ,	   0x1180080943fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2042"            ,	   0x1180080943fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2043"            ,	   0x1180080943fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2044"            ,	   0x1180080943fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2045"            ,	   0x1180080943fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2046"            ,	   0x1180080943ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2047"            ,	   0x1180080943ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2048"            ,	   0x1180080944000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2049"            ,	   0x1180080944008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2050"            ,	   0x1180080944010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2051"            ,	   0x1180080944018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2052"            ,	   0x1180080944020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2053"            ,	   0x1180080944028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2054"            ,	   0x1180080944030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2055"            ,	   0x1180080944038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2056"            ,	   0x1180080944040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2057"            ,	   0x1180080944048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2058"            ,	   0x1180080944050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2059"            ,	   0x1180080944058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2060"            ,	   0x1180080944060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2061"            ,	   0x1180080944068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2062"            ,	   0x1180080944070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2063"            ,	   0x1180080944078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2064"            ,	   0x1180080944080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2065"            ,	   0x1180080944088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2066"            ,	   0x1180080944090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2067"            ,	   0x1180080944098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2068"            ,	   0x11800809440a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2069"            ,	   0x11800809440a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2070"            ,	   0x11800809440b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2071"            ,	   0x11800809440b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2072"            ,	   0x11800809440c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2073"            ,	   0x11800809440c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2074"            ,	   0x11800809440d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2075"            ,	   0x11800809440d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2076"            ,	   0x11800809440e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2077"            ,	   0x11800809440e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2078"            ,	   0x11800809440f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2079"            ,	   0x11800809440f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2080"            ,	   0x1180080944100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2081"            ,	   0x1180080944108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2082"            ,	   0x1180080944110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2083"            ,	   0x1180080944118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2084"            ,	   0x1180080944120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2085"            ,	   0x1180080944128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2086"            ,	   0x1180080944130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2087"            ,	   0x1180080944138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2088"            ,	   0x1180080944140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2089"            ,	   0x1180080944148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2090"            ,	   0x1180080944150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2091"            ,	   0x1180080944158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2092"            ,	   0x1180080944160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2093"            ,	   0x1180080944168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2094"            ,	   0x1180080944170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2095"            ,	   0x1180080944178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2096"            ,	   0x1180080944180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2097"            ,	   0x1180080944188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2098"            ,	   0x1180080944190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2099"            ,	   0x1180080944198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2100"            ,	   0x11800809441a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2101"            ,	   0x11800809441a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2102"            ,	   0x11800809441b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2103"            ,	   0x11800809441b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2104"            ,	   0x11800809441c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2105"            ,	   0x11800809441c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2106"            ,	   0x11800809441d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2107"            ,	   0x11800809441d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2108"            ,	   0x11800809441e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2109"            ,	   0x11800809441e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2110"            ,	   0x11800809441f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2111"            ,	   0x11800809441f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2112"            ,	   0x1180080944200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2113"            ,	   0x1180080944208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2114"            ,	   0x1180080944210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2115"            ,	   0x1180080944218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2116"            ,	   0x1180080944220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2117"            ,	   0x1180080944228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2118"            ,	   0x1180080944230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2119"            ,	   0x1180080944238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2120"            ,	   0x1180080944240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2121"            ,	   0x1180080944248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2122"            ,	   0x1180080944250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2123"            ,	   0x1180080944258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2124"            ,	   0x1180080944260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2125"            ,	   0x1180080944268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2126"            ,	   0x1180080944270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2127"            ,	   0x1180080944278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2128"            ,	   0x1180080944280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2129"            ,	   0x1180080944288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2130"            ,	   0x1180080944290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2131"            ,	   0x1180080944298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2132"            ,	   0x11800809442a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2133"            ,	   0x11800809442a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2134"            ,	   0x11800809442b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2135"            ,	   0x11800809442b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2136"            ,	   0x11800809442c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2137"            ,	   0x11800809442c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2138"            ,	   0x11800809442d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2139"            ,	   0x11800809442d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2140"            ,	   0x11800809442e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2141"            ,	   0x11800809442e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2142"            ,	   0x11800809442f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2143"            ,	   0x11800809442f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2144"            ,	   0x1180080944300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2145"            ,	   0x1180080944308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2146"            ,	   0x1180080944310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2147"            ,	   0x1180080944318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2148"            ,	   0x1180080944320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2149"            ,	   0x1180080944328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2150"            ,	   0x1180080944330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2151"            ,	   0x1180080944338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2152"            ,	   0x1180080944340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2153"            ,	   0x1180080944348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2154"            ,	   0x1180080944350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2155"            ,	   0x1180080944358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2156"            ,	   0x1180080944360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2157"            ,	   0x1180080944368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2158"            ,	   0x1180080944370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2159"            ,	   0x1180080944378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2160"            ,	   0x1180080944380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2161"            ,	   0x1180080944388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2162"            ,	   0x1180080944390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2163"            ,	   0x1180080944398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2164"            ,	   0x11800809443a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2165"            ,	   0x11800809443a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2166"            ,	   0x11800809443b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2167"            ,	   0x11800809443b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2168"            ,	   0x11800809443c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2169"            ,	   0x11800809443c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2170"            ,	   0x11800809443d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2171"            ,	   0x11800809443d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2172"            ,	   0x11800809443e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2173"            ,	   0x11800809443e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2174"            ,	   0x11800809443f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2175"            ,	   0x11800809443f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2176"            ,	   0x1180080944400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2177"            ,	   0x1180080944408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2178"            ,	   0x1180080944410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2179"            ,	   0x1180080944418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2180"            ,	   0x1180080944420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2181"            ,	   0x1180080944428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2182"            ,	   0x1180080944430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2183"            ,	   0x1180080944438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2184"            ,	   0x1180080944440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2185"            ,	   0x1180080944448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2186"            ,	   0x1180080944450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2187"            ,	   0x1180080944458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2188"            ,	   0x1180080944460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2189"            ,	   0x1180080944468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2190"            ,	   0x1180080944470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2191"            ,	   0x1180080944478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2192"            ,	   0x1180080944480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2193"            ,	   0x1180080944488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2194"            ,	   0x1180080944490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2195"            ,	   0x1180080944498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2196"            ,	   0x11800809444a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2197"            ,	   0x11800809444a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2198"            ,	   0x11800809444b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2199"            ,	   0x11800809444b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2200"            ,	   0x11800809444c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2201"            ,	   0x11800809444c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2202"            ,	   0x11800809444d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2203"            ,	   0x11800809444d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2204"            ,	   0x11800809444e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2205"            ,	   0x11800809444e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2206"            ,	   0x11800809444f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2207"            ,	   0x11800809444f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2208"            ,	   0x1180080944500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2209"            ,	   0x1180080944508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2210"            ,	   0x1180080944510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2211"            ,	   0x1180080944518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2212"            ,	   0x1180080944520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2213"            ,	   0x1180080944528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2214"            ,	   0x1180080944530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2215"            ,	   0x1180080944538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2216"            ,	   0x1180080944540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2217"            ,	   0x1180080944548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2218"            ,	   0x1180080944550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2219"            ,	   0x1180080944558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2220"            ,	   0x1180080944560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2221"            ,	   0x1180080944568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2222"            ,	   0x1180080944570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2223"            ,	   0x1180080944578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2224"            ,	   0x1180080944580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2225"            ,	   0x1180080944588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2226"            ,	   0x1180080944590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2227"            ,	   0x1180080944598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2228"            ,	   0x11800809445a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2229"            ,	   0x11800809445a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2230"            ,	   0x11800809445b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2231"            ,	   0x11800809445b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2232"            ,	   0x11800809445c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2233"            ,	   0x11800809445c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2234"            ,	   0x11800809445d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2235"            ,	   0x11800809445d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2236"            ,	   0x11800809445e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2237"            ,	   0x11800809445e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2238"            ,	   0x11800809445f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2239"            ,	   0x11800809445f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2240"            ,	   0x1180080944600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2241"            ,	   0x1180080944608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2242"            ,	   0x1180080944610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2243"            ,	   0x1180080944618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2244"            ,	   0x1180080944620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2245"            ,	   0x1180080944628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2246"            ,	   0x1180080944630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2247"            ,	   0x1180080944638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2248"            ,	   0x1180080944640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2249"            ,	   0x1180080944648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2250"            ,	   0x1180080944650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2251"            ,	   0x1180080944658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2252"            ,	   0x1180080944660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2253"            ,	   0x1180080944668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2254"            ,	   0x1180080944670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2255"            ,	   0x1180080944678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2256"            ,	   0x1180080944680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2257"            ,	   0x1180080944688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2258"            ,	   0x1180080944690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2259"            ,	   0x1180080944698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2260"            ,	   0x11800809446a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2261"            ,	   0x11800809446a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2262"            ,	   0x11800809446b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2263"            ,	   0x11800809446b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2264"            ,	   0x11800809446c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2265"            ,	   0x11800809446c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2266"            ,	   0x11800809446d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2267"            ,	   0x11800809446d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2268"            ,	   0x11800809446e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2269"            ,	   0x11800809446e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2270"            ,	   0x11800809446f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2271"            ,	   0x11800809446f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2272"            ,	   0x1180080944700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2273"            ,	   0x1180080944708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2274"            ,	   0x1180080944710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2275"            ,	   0x1180080944718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2276"            ,	   0x1180080944720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2277"            ,	   0x1180080944728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2278"            ,	   0x1180080944730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2279"            ,	   0x1180080944738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2280"            ,	   0x1180080944740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2281"            ,	   0x1180080944748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2282"            ,	   0x1180080944750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2283"            ,	   0x1180080944758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2284"            ,	   0x1180080944760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2285"            ,	   0x1180080944768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2286"            ,	   0x1180080944770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2287"            ,	   0x1180080944778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2288"            ,	   0x1180080944780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2289"            ,	   0x1180080944788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2290"            ,	   0x1180080944790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2291"            ,	   0x1180080944798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2292"            ,	   0x11800809447a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2293"            ,	   0x11800809447a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2294"            ,	   0x11800809447b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2295"            ,	   0x11800809447b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2296"            ,	   0x11800809447c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2297"            ,	   0x11800809447c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2298"            ,	   0x11800809447d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2299"            ,	   0x11800809447d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2300"            ,	   0x11800809447e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2301"            ,	   0x11800809447e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2302"            ,	   0x11800809447f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2303"            ,	   0x11800809447f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2304"            ,	   0x1180080944800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2305"            ,	   0x1180080944808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2306"            ,	   0x1180080944810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2307"            ,	   0x1180080944818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2308"            ,	   0x1180080944820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2309"            ,	   0x1180080944828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2310"            ,	   0x1180080944830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2311"            ,	   0x1180080944838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2312"            ,	   0x1180080944840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2313"            ,	   0x1180080944848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2314"            ,	   0x1180080944850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2315"            ,	   0x1180080944858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2316"            ,	   0x1180080944860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2317"            ,	   0x1180080944868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2318"            ,	   0x1180080944870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2319"            ,	   0x1180080944878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2320"            ,	   0x1180080944880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2321"            ,	   0x1180080944888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2322"            ,	   0x1180080944890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2323"            ,	   0x1180080944898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2324"            ,	   0x11800809448a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2325"            ,	   0x11800809448a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2326"            ,	   0x11800809448b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2327"            ,	   0x11800809448b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2328"            ,	   0x11800809448c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2329"            ,	   0x11800809448c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2330"            ,	   0x11800809448d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2331"            ,	   0x11800809448d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2332"            ,	   0x11800809448e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2333"            ,	   0x11800809448e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2334"            ,	   0x11800809448f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2335"            ,	   0x11800809448f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2336"            ,	   0x1180080944900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2337"            ,	   0x1180080944908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2338"            ,	   0x1180080944910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2339"            ,	   0x1180080944918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2340"            ,	   0x1180080944920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2341"            ,	   0x1180080944928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2342"            ,	   0x1180080944930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2343"            ,	   0x1180080944938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2344"            ,	   0x1180080944940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2345"            ,	   0x1180080944948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2346"            ,	   0x1180080944950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2347"            ,	   0x1180080944958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2348"            ,	   0x1180080944960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2349"            ,	   0x1180080944968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2350"            ,	   0x1180080944970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2351"            ,	   0x1180080944978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2352"            ,	   0x1180080944980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2353"            ,	   0x1180080944988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2354"            ,	   0x1180080944990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2355"            ,	   0x1180080944998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2356"            ,	   0x11800809449a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2357"            ,	   0x11800809449a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2358"            ,	   0x11800809449b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2359"            ,	   0x11800809449b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2360"            ,	   0x11800809449c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2361"            ,	   0x11800809449c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2362"            ,	   0x11800809449d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2363"            ,	   0x11800809449d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2364"            ,	   0x11800809449e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2365"            ,	   0x11800809449e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2366"            ,	   0x11800809449f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2367"            ,	   0x11800809449f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2368"            ,	   0x1180080944a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2369"            ,	   0x1180080944a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2370"            ,	   0x1180080944a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2371"            ,	   0x1180080944a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2372"            ,	   0x1180080944a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2373"            ,	   0x1180080944a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2374"            ,	   0x1180080944a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2375"            ,	   0x1180080944a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2376"            ,	   0x1180080944a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2377"            ,	   0x1180080944a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2378"            ,	   0x1180080944a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2379"            ,	   0x1180080944a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2380"            ,	   0x1180080944a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2381"            ,	   0x1180080944a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2382"            ,	   0x1180080944a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2383"            ,	   0x1180080944a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2384"            ,	   0x1180080944a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2385"            ,	   0x1180080944a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2386"            ,	   0x1180080944a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2387"            ,	   0x1180080944a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2388"            ,	   0x1180080944aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2389"            ,	   0x1180080944aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2390"            ,	   0x1180080944ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2391"            ,	   0x1180080944ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2392"            ,	   0x1180080944ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2393"            ,	   0x1180080944ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2394"            ,	   0x1180080944ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2395"            ,	   0x1180080944ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2396"            ,	   0x1180080944ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2397"            ,	   0x1180080944ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2398"            ,	   0x1180080944af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2399"            ,	   0x1180080944af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2400"            ,	   0x1180080944b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2401"            ,	   0x1180080944b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2402"            ,	   0x1180080944b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2403"            ,	   0x1180080944b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2404"            ,	   0x1180080944b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2405"            ,	   0x1180080944b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2406"            ,	   0x1180080944b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2407"            ,	   0x1180080944b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2408"            ,	   0x1180080944b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2409"            ,	   0x1180080944b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2410"            ,	   0x1180080944b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2411"            ,	   0x1180080944b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2412"            ,	   0x1180080944b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2413"            ,	   0x1180080944b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2414"            ,	   0x1180080944b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2415"            ,	   0x1180080944b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2416"            ,	   0x1180080944b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2417"            ,	   0x1180080944b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2418"            ,	   0x1180080944b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2419"            ,	   0x1180080944b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2420"            ,	   0x1180080944ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2421"            ,	   0x1180080944ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2422"            ,	   0x1180080944bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2423"            ,	   0x1180080944bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2424"            ,	   0x1180080944bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2425"            ,	   0x1180080944bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2426"            ,	   0x1180080944bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2427"            ,	   0x1180080944bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2428"            ,	   0x1180080944be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2429"            ,	   0x1180080944be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2430"            ,	   0x1180080944bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2431"            ,	   0x1180080944bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2432"            ,	   0x1180080944c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2433"            ,	   0x1180080944c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2434"            ,	   0x1180080944c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2435"            ,	   0x1180080944c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2436"            ,	   0x1180080944c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2437"            ,	   0x1180080944c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2438"            ,	   0x1180080944c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2439"            ,	   0x1180080944c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2440"            ,	   0x1180080944c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2441"            ,	   0x1180080944c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2442"            ,	   0x1180080944c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2443"            ,	   0x1180080944c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2444"            ,	   0x1180080944c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2445"            ,	   0x1180080944c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2446"            ,	   0x1180080944c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2447"            ,	   0x1180080944c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2448"            ,	   0x1180080944c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2449"            ,	   0x1180080944c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2450"            ,	   0x1180080944c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2451"            ,	   0x1180080944c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2452"            ,	   0x1180080944ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2453"            ,	   0x1180080944ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2454"            ,	   0x1180080944cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2455"            ,	   0x1180080944cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2456"            ,	   0x1180080944cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2457"            ,	   0x1180080944cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2458"            ,	   0x1180080944cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2459"            ,	   0x1180080944cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2460"            ,	   0x1180080944ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2461"            ,	   0x1180080944ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2462"            ,	   0x1180080944cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2463"            ,	   0x1180080944cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2464"            ,	   0x1180080944d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2465"            ,	   0x1180080944d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2466"            ,	   0x1180080944d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2467"            ,	   0x1180080944d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2468"            ,	   0x1180080944d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2469"            ,	   0x1180080944d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2470"            ,	   0x1180080944d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2471"            ,	   0x1180080944d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2472"            ,	   0x1180080944d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2473"            ,	   0x1180080944d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2474"            ,	   0x1180080944d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2475"            ,	   0x1180080944d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2476"            ,	   0x1180080944d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2477"            ,	   0x1180080944d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2478"            ,	   0x1180080944d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2479"            ,	   0x1180080944d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2480"            ,	   0x1180080944d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2481"            ,	   0x1180080944d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2482"            ,	   0x1180080944d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2483"            ,	   0x1180080944d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2484"            ,	   0x1180080944da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2485"            ,	   0x1180080944da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2486"            ,	   0x1180080944db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2487"            ,	   0x1180080944db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2488"            ,	   0x1180080944dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2489"            ,	   0x1180080944dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2490"            ,	   0x1180080944dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2491"            ,	   0x1180080944dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2492"            ,	   0x1180080944de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2493"            ,	   0x1180080944de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2494"            ,	   0x1180080944df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2495"            ,	   0x1180080944df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2496"            ,	   0x1180080944e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2497"            ,	   0x1180080944e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2498"            ,	   0x1180080944e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2499"            ,	   0x1180080944e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2500"            ,	   0x1180080944e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2501"            ,	   0x1180080944e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2502"            ,	   0x1180080944e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2503"            ,	   0x1180080944e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2504"            ,	   0x1180080944e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2505"            ,	   0x1180080944e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2506"            ,	   0x1180080944e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2507"            ,	   0x1180080944e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2508"            ,	   0x1180080944e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2509"            ,	   0x1180080944e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2510"            ,	   0x1180080944e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2511"            ,	   0x1180080944e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2512"            ,	   0x1180080944e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2513"            ,	   0x1180080944e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2514"            ,	   0x1180080944e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2515"            ,	   0x1180080944e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2516"            ,	   0x1180080944ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2517"            ,	   0x1180080944ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2518"            ,	   0x1180080944eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2519"            ,	   0x1180080944eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2520"            ,	   0x1180080944ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2521"            ,	   0x1180080944ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2522"            ,	   0x1180080944ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2523"            ,	   0x1180080944ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2524"            ,	   0x1180080944ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2525"            ,	   0x1180080944ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2526"            ,	   0x1180080944ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2527"            ,	   0x1180080944ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2528"            ,	   0x1180080944f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2529"            ,	   0x1180080944f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2530"            ,	   0x1180080944f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2531"            ,	   0x1180080944f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2532"            ,	   0x1180080944f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2533"            ,	   0x1180080944f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2534"            ,	   0x1180080944f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2535"            ,	   0x1180080944f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2536"            ,	   0x1180080944f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2537"            ,	   0x1180080944f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2538"            ,	   0x1180080944f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2539"            ,	   0x1180080944f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2540"            ,	   0x1180080944f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2541"            ,	   0x1180080944f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2542"            ,	   0x1180080944f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2543"            ,	   0x1180080944f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2544"            ,	   0x1180080944f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2545"            ,	   0x1180080944f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2546"            ,	   0x1180080944f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2547"            ,	   0x1180080944f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2548"            ,	   0x1180080944fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2549"            ,	   0x1180080944fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2550"            ,	   0x1180080944fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2551"            ,	   0x1180080944fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2552"            ,	   0x1180080944fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2553"            ,	   0x1180080944fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2554"            ,	   0x1180080944fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2555"            ,	   0x1180080944fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2556"            ,	   0x1180080944fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2557"            ,	   0x1180080944fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2558"            ,	   0x1180080944ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2559"            ,	   0x1180080944ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2560"            ,	   0x1180080945000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2561"            ,	   0x1180080945008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2562"            ,	   0x1180080945010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2563"            ,	   0x1180080945018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2564"            ,	   0x1180080945020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2565"            ,	   0x1180080945028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2566"            ,	   0x1180080945030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2567"            ,	   0x1180080945038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2568"            ,	   0x1180080945040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2569"            ,	   0x1180080945048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2570"            ,	   0x1180080945050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2571"            ,	   0x1180080945058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2572"            ,	   0x1180080945060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2573"            ,	   0x1180080945068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2574"            ,	   0x1180080945070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2575"            ,	   0x1180080945078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2576"            ,	   0x1180080945080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2577"            ,	   0x1180080945088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2578"            ,	   0x1180080945090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2579"            ,	   0x1180080945098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2580"            ,	   0x11800809450a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2581"            ,	   0x11800809450a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2582"            ,	   0x11800809450b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2583"            ,	   0x11800809450b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2584"            ,	   0x11800809450c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2585"            ,	   0x11800809450c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2586"            ,	   0x11800809450d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2587"            ,	   0x11800809450d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2588"            ,	   0x11800809450e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2589"            ,	   0x11800809450e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2590"            ,	   0x11800809450f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2591"            ,	   0x11800809450f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2592"            ,	   0x1180080945100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2593"            ,	   0x1180080945108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2594"            ,	   0x1180080945110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2595"            ,	   0x1180080945118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2596"            ,	   0x1180080945120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2597"            ,	   0x1180080945128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2598"            ,	   0x1180080945130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2599"            ,	   0x1180080945138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2600"            ,	   0x1180080945140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2601"            ,	   0x1180080945148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2602"            ,	   0x1180080945150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2603"            ,	   0x1180080945158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2604"            ,	   0x1180080945160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2605"            ,	   0x1180080945168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2606"            ,	   0x1180080945170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2607"            ,	   0x1180080945178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2608"            ,	   0x1180080945180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2609"            ,	   0x1180080945188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2610"            ,	   0x1180080945190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2611"            ,	   0x1180080945198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2612"            ,	   0x11800809451a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2613"            ,	   0x11800809451a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2614"            ,	   0x11800809451b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2615"            ,	   0x11800809451b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2616"            ,	   0x11800809451c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2617"            ,	   0x11800809451c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2618"            ,	   0x11800809451d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2619"            ,	   0x11800809451d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2620"            ,	   0x11800809451e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2621"            ,	   0x11800809451e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2622"            ,	   0x11800809451f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2623"            ,	   0x11800809451f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2624"            ,	   0x1180080945200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2625"            ,	   0x1180080945208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2626"            ,	   0x1180080945210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2627"            ,	   0x1180080945218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2628"            ,	   0x1180080945220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2629"            ,	   0x1180080945228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2630"            ,	   0x1180080945230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2631"            ,	   0x1180080945238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2632"            ,	   0x1180080945240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2633"            ,	   0x1180080945248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2634"            ,	   0x1180080945250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2635"            ,	   0x1180080945258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2636"            ,	   0x1180080945260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2637"            ,	   0x1180080945268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2638"            ,	   0x1180080945270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2639"            ,	   0x1180080945278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2640"            ,	   0x1180080945280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2641"            ,	   0x1180080945288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2642"            ,	   0x1180080945290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2643"            ,	   0x1180080945298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2644"            ,	   0x11800809452a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2645"            ,	   0x11800809452a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2646"            ,	   0x11800809452b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2647"            ,	   0x11800809452b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2648"            ,	   0x11800809452c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2649"            ,	   0x11800809452c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2650"            ,	   0x11800809452d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2651"            ,	   0x11800809452d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2652"            ,	   0x11800809452e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2653"            ,	   0x11800809452e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2654"            ,	   0x11800809452f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2655"            ,	   0x11800809452f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2656"            ,	   0x1180080945300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2657"            ,	   0x1180080945308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2658"            ,	   0x1180080945310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2659"            ,	   0x1180080945318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2660"            ,	   0x1180080945320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2661"            ,	   0x1180080945328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2662"            ,	   0x1180080945330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2663"            ,	   0x1180080945338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2664"            ,	   0x1180080945340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2665"            ,	   0x1180080945348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2666"            ,	   0x1180080945350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2667"            ,	   0x1180080945358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2668"            ,	   0x1180080945360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2669"            ,	   0x1180080945368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2670"            ,	   0x1180080945370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2671"            ,	   0x1180080945378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2672"            ,	   0x1180080945380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2673"            ,	   0x1180080945388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2674"            ,	   0x1180080945390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2675"            ,	   0x1180080945398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2676"            ,	   0x11800809453a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2677"            ,	   0x11800809453a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2678"            ,	   0x11800809453b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2679"            ,	   0x11800809453b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2680"            ,	   0x11800809453c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2681"            ,	   0x11800809453c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2682"            ,	   0x11800809453d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2683"            ,	   0x11800809453d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2684"            ,	   0x11800809453e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2685"            ,	   0x11800809453e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2686"            ,	   0x11800809453f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2687"            ,	   0x11800809453f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2688"            ,	   0x1180080945400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2689"            ,	   0x1180080945408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2690"            ,	   0x1180080945410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2691"            ,	   0x1180080945418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2692"            ,	   0x1180080945420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2693"            ,	   0x1180080945428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2694"            ,	   0x1180080945430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2695"            ,	   0x1180080945438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2696"            ,	   0x1180080945440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2697"            ,	   0x1180080945448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2698"            ,	   0x1180080945450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2699"            ,	   0x1180080945458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2700"            ,	   0x1180080945460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2701"            ,	   0x1180080945468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2702"            ,	   0x1180080945470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2703"            ,	   0x1180080945478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2704"            ,	   0x1180080945480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2705"            ,	   0x1180080945488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2706"            ,	   0x1180080945490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2707"            ,	   0x1180080945498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2708"            ,	   0x11800809454a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2709"            ,	   0x11800809454a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2710"            ,	   0x11800809454b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2711"            ,	   0x11800809454b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2712"            ,	   0x11800809454c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2713"            ,	   0x11800809454c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2714"            ,	   0x11800809454d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2715"            ,	   0x11800809454d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2716"            ,	   0x11800809454e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2717"            ,	   0x11800809454e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2718"            ,	   0x11800809454f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2719"            ,	   0x11800809454f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2720"            ,	   0x1180080945500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2721"            ,	   0x1180080945508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2722"            ,	   0x1180080945510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2723"            ,	   0x1180080945518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2724"            ,	   0x1180080945520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2725"            ,	   0x1180080945528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2726"            ,	   0x1180080945530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2727"            ,	   0x1180080945538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2728"            ,	   0x1180080945540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2729"            ,	   0x1180080945548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2730"            ,	   0x1180080945550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2731"            ,	   0x1180080945558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2732"            ,	   0x1180080945560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2733"            ,	   0x1180080945568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2734"            ,	   0x1180080945570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2735"            ,	   0x1180080945578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2736"            ,	   0x1180080945580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2737"            ,	   0x1180080945588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2738"            ,	   0x1180080945590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2739"            ,	   0x1180080945598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2740"            ,	   0x11800809455a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2741"            ,	   0x11800809455a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2742"            ,	   0x11800809455b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2743"            ,	   0x11800809455b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2744"            ,	   0x11800809455c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2745"            ,	   0x11800809455c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2746"            ,	   0x11800809455d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2747"            ,	   0x11800809455d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2748"            ,	   0x11800809455e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2749"            ,	   0x11800809455e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2750"            ,	   0x11800809455f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2751"            ,	   0x11800809455f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2752"            ,	   0x1180080945600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2753"            ,	   0x1180080945608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2754"            ,	   0x1180080945610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2755"            ,	   0x1180080945618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2756"            ,	   0x1180080945620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2757"            ,	   0x1180080945628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2758"            ,	   0x1180080945630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2759"            ,	   0x1180080945638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2760"            ,	   0x1180080945640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2761"            ,	   0x1180080945648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2762"            ,	   0x1180080945650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2763"            ,	   0x1180080945658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2764"            ,	   0x1180080945660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2765"            ,	   0x1180080945668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2766"            ,	   0x1180080945670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2767"            ,	   0x1180080945678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2768"            ,	   0x1180080945680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2769"            ,	   0x1180080945688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2770"            ,	   0x1180080945690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2771"            ,	   0x1180080945698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2772"            ,	   0x11800809456a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2773"            ,	   0x11800809456a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2774"            ,	   0x11800809456b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2775"            ,	   0x11800809456b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2776"            ,	   0x11800809456c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2777"            ,	   0x11800809456c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2778"            ,	   0x11800809456d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2779"            ,	   0x11800809456d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2780"            ,	   0x11800809456e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2781"            ,	   0x11800809456e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2782"            ,	   0x11800809456f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2783"            ,	   0x11800809456f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2784"            ,	   0x1180080945700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2785"            ,	   0x1180080945708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2786"            ,	   0x1180080945710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2787"            ,	   0x1180080945718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2788"            ,	   0x1180080945720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2789"            ,	   0x1180080945728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2790"            ,	   0x1180080945730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2791"            ,	   0x1180080945738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2792"            ,	   0x1180080945740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2793"            ,	   0x1180080945748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2794"            ,	   0x1180080945750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2795"            ,	   0x1180080945758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2796"            ,	   0x1180080945760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2797"            ,	   0x1180080945768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2798"            ,	   0x1180080945770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2799"            ,	   0x1180080945778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2800"            ,	   0x1180080945780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2801"            ,	   0x1180080945788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2802"            ,	   0x1180080945790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2803"            ,	   0x1180080945798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2804"            ,	   0x11800809457a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2805"            ,	   0x11800809457a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2806"            ,	   0x11800809457b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2807"            ,	   0x11800809457b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2808"            ,	   0x11800809457c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2809"            ,	   0x11800809457c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2810"            ,	   0x11800809457d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2811"            ,	   0x11800809457d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2812"            ,	   0x11800809457e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2813"            ,	   0x11800809457e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2814"            ,	   0x11800809457f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2815"            ,	   0x11800809457f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2816"            ,	   0x1180080945800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2817"            ,	   0x1180080945808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2818"            ,	   0x1180080945810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2819"            ,	   0x1180080945818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2820"            ,	   0x1180080945820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2821"            ,	   0x1180080945828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2822"            ,	   0x1180080945830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2823"            ,	   0x1180080945838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2824"            ,	   0x1180080945840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2825"            ,	   0x1180080945848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2826"            ,	   0x1180080945850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2827"            ,	   0x1180080945858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2828"            ,	   0x1180080945860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2829"            ,	   0x1180080945868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2830"            ,	   0x1180080945870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2831"            ,	   0x1180080945878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2832"            ,	   0x1180080945880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2833"            ,	   0x1180080945888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2834"            ,	   0x1180080945890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2835"            ,	   0x1180080945898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2836"            ,	   0x11800809458a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2837"            ,	   0x11800809458a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2838"            ,	   0x11800809458b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2839"            ,	   0x11800809458b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2840"            ,	   0x11800809458c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2841"            ,	   0x11800809458c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2842"            ,	   0x11800809458d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2843"            ,	   0x11800809458d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2844"            ,	   0x11800809458e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2845"            ,	   0x11800809458e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2846"            ,	   0x11800809458f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2847"            ,	   0x11800809458f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2848"            ,	   0x1180080945900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2849"            ,	   0x1180080945908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2850"            ,	   0x1180080945910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2851"            ,	   0x1180080945918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2852"            ,	   0x1180080945920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2853"            ,	   0x1180080945928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2854"            ,	   0x1180080945930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2855"            ,	   0x1180080945938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2856"            ,	   0x1180080945940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2857"            ,	   0x1180080945948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2858"            ,	   0x1180080945950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2859"            ,	   0x1180080945958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2860"            ,	   0x1180080945960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2861"            ,	   0x1180080945968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2862"            ,	   0x1180080945970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2863"            ,	   0x1180080945978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2864"            ,	   0x1180080945980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2865"            ,	   0x1180080945988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2866"            ,	   0x1180080945990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2867"            ,	   0x1180080945998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2868"            ,	   0x11800809459a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2869"            ,	   0x11800809459a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2870"            ,	   0x11800809459b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2871"            ,	   0x11800809459b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2872"            ,	   0x11800809459c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2873"            ,	   0x11800809459c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2874"            ,	   0x11800809459d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2875"            ,	   0x11800809459d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2876"            ,	   0x11800809459e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2877"            ,	   0x11800809459e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2878"            ,	   0x11800809459f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2879"            ,	   0x11800809459f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2880"            ,	   0x1180080945a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2881"            ,	   0x1180080945a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2882"            ,	   0x1180080945a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2883"            ,	   0x1180080945a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2884"            ,	   0x1180080945a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2885"            ,	   0x1180080945a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2886"            ,	   0x1180080945a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2887"            ,	   0x1180080945a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2888"            ,	   0x1180080945a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2889"            ,	   0x1180080945a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2890"            ,	   0x1180080945a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2891"            ,	   0x1180080945a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2892"            ,	   0x1180080945a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2893"            ,	   0x1180080945a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2894"            ,	   0x1180080945a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2895"            ,	   0x1180080945a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2896"            ,	   0x1180080945a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2897"            ,	   0x1180080945a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2898"            ,	   0x1180080945a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2899"            ,	   0x1180080945a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2900"            ,	   0x1180080945aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2901"            ,	   0x1180080945aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2902"            ,	   0x1180080945ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2903"            ,	   0x1180080945ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2904"            ,	   0x1180080945ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2905"            ,	   0x1180080945ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2906"            ,	   0x1180080945ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2907"            ,	   0x1180080945ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2908"            ,	   0x1180080945ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2909"            ,	   0x1180080945ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2910"            ,	   0x1180080945af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2911"            ,	   0x1180080945af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2912"            ,	   0x1180080945b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2913"            ,	   0x1180080945b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2914"            ,	   0x1180080945b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2915"            ,	   0x1180080945b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2916"            ,	   0x1180080945b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2917"            ,	   0x1180080945b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2918"            ,	   0x1180080945b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2919"            ,	   0x1180080945b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2920"            ,	   0x1180080945b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2921"            ,	   0x1180080945b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2922"            ,	   0x1180080945b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2923"            ,	   0x1180080945b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2924"            ,	   0x1180080945b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2925"            ,	   0x1180080945b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2926"            ,	   0x1180080945b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2927"            ,	   0x1180080945b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2928"            ,	   0x1180080945b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2929"            ,	   0x1180080945b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2930"            ,	   0x1180080945b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2931"            ,	   0x1180080945b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2932"            ,	   0x1180080945ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2933"            ,	   0x1180080945ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2934"            ,	   0x1180080945bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2935"            ,	   0x1180080945bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2936"            ,	   0x1180080945bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2937"            ,	   0x1180080945bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2938"            ,	   0x1180080945bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2939"            ,	   0x1180080945bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2940"            ,	   0x1180080945be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2941"            ,	   0x1180080945be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2942"            ,	   0x1180080945bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2943"            ,	   0x1180080945bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2944"            ,	   0x1180080945c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2945"            ,	   0x1180080945c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2946"            ,	   0x1180080945c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2947"            ,	   0x1180080945c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2948"            ,	   0x1180080945c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2949"            ,	   0x1180080945c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2950"            ,	   0x1180080945c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2951"            ,	   0x1180080945c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2952"            ,	   0x1180080945c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2953"            ,	   0x1180080945c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2954"            ,	   0x1180080945c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2955"            ,	   0x1180080945c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2956"            ,	   0x1180080945c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2957"            ,	   0x1180080945c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2958"            ,	   0x1180080945c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2959"            ,	   0x1180080945c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2960"            ,	   0x1180080945c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2961"            ,	   0x1180080945c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2962"            ,	   0x1180080945c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2963"            ,	   0x1180080945c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2964"            ,	   0x1180080945ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2965"            ,	   0x1180080945ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2966"            ,	   0x1180080945cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2967"            ,	   0x1180080945cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2968"            ,	   0x1180080945cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2969"            ,	   0x1180080945cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2970"            ,	   0x1180080945cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2971"            ,	   0x1180080945cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2972"            ,	   0x1180080945ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2973"            ,	   0x1180080945ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2974"            ,	   0x1180080945cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2975"            ,	   0x1180080945cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2976"            ,	   0x1180080945d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2977"            ,	   0x1180080945d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2978"            ,	   0x1180080945d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2979"            ,	   0x1180080945d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2980"            ,	   0x1180080945d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2981"            ,	   0x1180080945d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2982"            ,	   0x1180080945d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2983"            ,	   0x1180080945d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2984"            ,	   0x1180080945d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2985"            ,	   0x1180080945d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2986"            ,	   0x1180080945d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2987"            ,	   0x1180080945d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2988"            ,	   0x1180080945d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2989"            ,	   0x1180080945d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2990"            ,	   0x1180080945d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2991"            ,	   0x1180080945d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2992"            ,	   0x1180080945d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2993"            ,	   0x1180080945d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2994"            ,	   0x1180080945d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2995"            ,	   0x1180080945d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2996"            ,	   0x1180080945da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2997"            ,	   0x1180080945da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2998"            ,	   0x1180080945db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP2999"            ,	   0x1180080945db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3000"            ,	   0x1180080945dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3001"            ,	   0x1180080945dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3002"            ,	   0x1180080945dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3003"            ,	   0x1180080945dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3004"            ,	   0x1180080945de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3005"            ,	   0x1180080945de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3006"            ,	   0x1180080945df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3007"            ,	   0x1180080945df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3008"            ,	   0x1180080945e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3009"            ,	   0x1180080945e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3010"            ,	   0x1180080945e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3011"            ,	   0x1180080945e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3012"            ,	   0x1180080945e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3013"            ,	   0x1180080945e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3014"            ,	   0x1180080945e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3015"            ,	   0x1180080945e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3016"            ,	   0x1180080945e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3017"            ,	   0x1180080945e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3018"            ,	   0x1180080945e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3019"            ,	   0x1180080945e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3020"            ,	   0x1180080945e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3021"            ,	   0x1180080945e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3022"            ,	   0x1180080945e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3023"            ,	   0x1180080945e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3024"            ,	   0x1180080945e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3025"            ,	   0x1180080945e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3026"            ,	   0x1180080945e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3027"            ,	   0x1180080945e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3028"            ,	   0x1180080945ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3029"            ,	   0x1180080945ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3030"            ,	   0x1180080945eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3031"            ,	   0x1180080945eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3032"            ,	   0x1180080945ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3033"            ,	   0x1180080945ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3034"            ,	   0x1180080945ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3035"            ,	   0x1180080945ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3036"            ,	   0x1180080945ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3037"            ,	   0x1180080945ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3038"            ,	   0x1180080945ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3039"            ,	   0x1180080945ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3040"            ,	   0x1180080945f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3041"            ,	   0x1180080945f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3042"            ,	   0x1180080945f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3043"            ,	   0x1180080945f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3044"            ,	   0x1180080945f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3045"            ,	   0x1180080945f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3046"            ,	   0x1180080945f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3047"            ,	   0x1180080945f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3048"            ,	   0x1180080945f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3049"            ,	   0x1180080945f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3050"            ,	   0x1180080945f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3051"            ,	   0x1180080945f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3052"            ,	   0x1180080945f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3053"            ,	   0x1180080945f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3054"            ,	   0x1180080945f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3055"            ,	   0x1180080945f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3056"            ,	   0x1180080945f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3057"            ,	   0x1180080945f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3058"            ,	   0x1180080945f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3059"            ,	   0x1180080945f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3060"            ,	   0x1180080945fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3061"            ,	   0x1180080945fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3062"            ,	   0x1180080945fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3063"            ,	   0x1180080945fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3064"            ,	   0x1180080945fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3065"            ,	   0x1180080945fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3066"            ,	   0x1180080945fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3067"            ,	   0x1180080945fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3068"            ,	   0x1180080945fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3069"            ,	   0x1180080945fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3070"            ,	   0x1180080945ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3071"            ,	   0x1180080945ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3072"            ,	   0x1180080946000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3073"            ,	   0x1180080946008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3074"            ,	   0x1180080946010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3075"            ,	   0x1180080946018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3076"            ,	   0x1180080946020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3077"            ,	   0x1180080946028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3078"            ,	   0x1180080946030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3079"            ,	   0x1180080946038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3080"            ,	   0x1180080946040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3081"            ,	   0x1180080946048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3082"            ,	   0x1180080946050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3083"            ,	   0x1180080946058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3084"            ,	   0x1180080946060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3085"            ,	   0x1180080946068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3086"            ,	   0x1180080946070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3087"            ,	   0x1180080946078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3088"            ,	   0x1180080946080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3089"            ,	   0x1180080946088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3090"            ,	   0x1180080946090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3091"            ,	   0x1180080946098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3092"            ,	   0x11800809460a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3093"            ,	   0x11800809460a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3094"            ,	   0x11800809460b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3095"            ,	   0x11800809460b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3096"            ,	   0x11800809460c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3097"            ,	   0x11800809460c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3098"            ,	   0x11800809460d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3099"            ,	   0x11800809460d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3100"            ,	   0x11800809460e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3101"            ,	   0x11800809460e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3102"            ,	   0x11800809460f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3103"            ,	   0x11800809460f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3104"            ,	   0x1180080946100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3105"            ,	   0x1180080946108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3106"            ,	   0x1180080946110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3107"            ,	   0x1180080946118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3108"            ,	   0x1180080946120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3109"            ,	   0x1180080946128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3110"            ,	   0x1180080946130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3111"            ,	   0x1180080946138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3112"            ,	   0x1180080946140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3113"            ,	   0x1180080946148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3114"            ,	   0x1180080946150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3115"            ,	   0x1180080946158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3116"            ,	   0x1180080946160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3117"            ,	   0x1180080946168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3118"            ,	   0x1180080946170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3119"            ,	   0x1180080946178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3120"            ,	   0x1180080946180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3121"            ,	   0x1180080946188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3122"            ,	   0x1180080946190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3123"            ,	   0x1180080946198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3124"            ,	   0x11800809461a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3125"            ,	   0x11800809461a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3126"            ,	   0x11800809461b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3127"            ,	   0x11800809461b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3128"            ,	   0x11800809461c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3129"            ,	   0x11800809461c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3130"            ,	   0x11800809461d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3131"            ,	   0x11800809461d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3132"            ,	   0x11800809461e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3133"            ,	   0x11800809461e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3134"            ,	   0x11800809461f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3135"            ,	   0x11800809461f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3136"            ,	   0x1180080946200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3137"            ,	   0x1180080946208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3138"            ,	   0x1180080946210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3139"            ,	   0x1180080946218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3140"            ,	   0x1180080946220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3141"            ,	   0x1180080946228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3142"            ,	   0x1180080946230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3143"            ,	   0x1180080946238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3144"            ,	   0x1180080946240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3145"            ,	   0x1180080946248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3146"            ,	   0x1180080946250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3147"            ,	   0x1180080946258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3148"            ,	   0x1180080946260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3149"            ,	   0x1180080946268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3150"            ,	   0x1180080946270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3151"            ,	   0x1180080946278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3152"            ,	   0x1180080946280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3153"            ,	   0x1180080946288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3154"            ,	   0x1180080946290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3155"            ,	   0x1180080946298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3156"            ,	   0x11800809462a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3157"            ,	   0x11800809462a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3158"            ,	   0x11800809462b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3159"            ,	   0x11800809462b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3160"            ,	   0x11800809462c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3161"            ,	   0x11800809462c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3162"            ,	   0x11800809462d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3163"            ,	   0x11800809462d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3164"            ,	   0x11800809462e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3165"            ,	   0x11800809462e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3166"            ,	   0x11800809462f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3167"            ,	   0x11800809462f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3168"            ,	   0x1180080946300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3169"            ,	   0x1180080946308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3170"            ,	   0x1180080946310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3171"            ,	   0x1180080946318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3172"            ,	   0x1180080946320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3173"            ,	   0x1180080946328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3174"            ,	   0x1180080946330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3175"            ,	   0x1180080946338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3176"            ,	   0x1180080946340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3177"            ,	   0x1180080946348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3178"            ,	   0x1180080946350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3179"            ,	   0x1180080946358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3180"            ,	   0x1180080946360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3181"            ,	   0x1180080946368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3182"            ,	   0x1180080946370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3183"            ,	   0x1180080946378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3184"            ,	   0x1180080946380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3185"            ,	   0x1180080946388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3186"            ,	   0x1180080946390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3187"            ,	   0x1180080946398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3188"            ,	   0x11800809463a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3189"            ,	   0x11800809463a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3190"            ,	   0x11800809463b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3191"            ,	   0x11800809463b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3192"            ,	   0x11800809463c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3193"            ,	   0x11800809463c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3194"            ,	   0x11800809463d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3195"            ,	   0x11800809463d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3196"            ,	   0x11800809463e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3197"            ,	   0x11800809463e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3198"            ,	   0x11800809463f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3199"            ,	   0x11800809463f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3200"            ,	   0x1180080946400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3201"            ,	   0x1180080946408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3202"            ,	   0x1180080946410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3203"            ,	   0x1180080946418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3204"            ,	   0x1180080946420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3205"            ,	   0x1180080946428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3206"            ,	   0x1180080946430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3207"            ,	   0x1180080946438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3208"            ,	   0x1180080946440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3209"            ,	   0x1180080946448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3210"            ,	   0x1180080946450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3211"            ,	   0x1180080946458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3212"            ,	   0x1180080946460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3213"            ,	   0x1180080946468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3214"            ,	   0x1180080946470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3215"            ,	   0x1180080946478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3216"            ,	   0x1180080946480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3217"            ,	   0x1180080946488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3218"            ,	   0x1180080946490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3219"            ,	   0x1180080946498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3220"            ,	   0x11800809464a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3221"            ,	   0x11800809464a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3222"            ,	   0x11800809464b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3223"            ,	   0x11800809464b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3224"            ,	   0x11800809464c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3225"            ,	   0x11800809464c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3226"            ,	   0x11800809464d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3227"            ,	   0x11800809464d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3228"            ,	   0x11800809464e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3229"            ,	   0x11800809464e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3230"            ,	   0x11800809464f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3231"            ,	   0x11800809464f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3232"            ,	   0x1180080946500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3233"            ,	   0x1180080946508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3234"            ,	   0x1180080946510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3235"            ,	   0x1180080946518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3236"            ,	   0x1180080946520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3237"            ,	   0x1180080946528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3238"            ,	   0x1180080946530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3239"            ,	   0x1180080946538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3240"            ,	   0x1180080946540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3241"            ,	   0x1180080946548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3242"            ,	   0x1180080946550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3243"            ,	   0x1180080946558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3244"            ,	   0x1180080946560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3245"            ,	   0x1180080946568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3246"            ,	   0x1180080946570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3247"            ,	   0x1180080946578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3248"            ,	   0x1180080946580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3249"            ,	   0x1180080946588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3250"            ,	   0x1180080946590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3251"            ,	   0x1180080946598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3252"            ,	   0x11800809465a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3253"            ,	   0x11800809465a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3254"            ,	   0x11800809465b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3255"            ,	   0x11800809465b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3256"            ,	   0x11800809465c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3257"            ,	   0x11800809465c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3258"            ,	   0x11800809465d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3259"            ,	   0x11800809465d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3260"            ,	   0x11800809465e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3261"            ,	   0x11800809465e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3262"            ,	   0x11800809465f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3263"            ,	   0x11800809465f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3264"            ,	   0x1180080946600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3265"            ,	   0x1180080946608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3266"            ,	   0x1180080946610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3267"            ,	   0x1180080946618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3268"            ,	   0x1180080946620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3269"            ,	   0x1180080946628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3270"            ,	   0x1180080946630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3271"            ,	   0x1180080946638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3272"            ,	   0x1180080946640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3273"            ,	   0x1180080946648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3274"            ,	   0x1180080946650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3275"            ,	   0x1180080946658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3276"            ,	   0x1180080946660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3277"            ,	   0x1180080946668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3278"            ,	   0x1180080946670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3279"            ,	   0x1180080946678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3280"            ,	   0x1180080946680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3281"            ,	   0x1180080946688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3282"            ,	   0x1180080946690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3283"            ,	   0x1180080946698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3284"            ,	   0x11800809466a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3285"            ,	   0x11800809466a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3286"            ,	   0x11800809466b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3287"            ,	   0x11800809466b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3288"            ,	   0x11800809466c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3289"            ,	   0x11800809466c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3290"            ,	   0x11800809466d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3291"            ,	   0x11800809466d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3292"            ,	   0x11800809466e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3293"            ,	   0x11800809466e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3294"            ,	   0x11800809466f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3295"            ,	   0x11800809466f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3296"            ,	   0x1180080946700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3297"            ,	   0x1180080946708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3298"            ,	   0x1180080946710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3299"            ,	   0x1180080946718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3300"            ,	   0x1180080946720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3301"            ,	   0x1180080946728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3302"            ,	   0x1180080946730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3303"            ,	   0x1180080946738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3304"            ,	   0x1180080946740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3305"            ,	   0x1180080946748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3306"            ,	   0x1180080946750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3307"            ,	   0x1180080946758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3308"            ,	   0x1180080946760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3309"            ,	   0x1180080946768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3310"            ,	   0x1180080946770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3311"            ,	   0x1180080946778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3312"            ,	   0x1180080946780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3313"            ,	   0x1180080946788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3314"            ,	   0x1180080946790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3315"            ,	   0x1180080946798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3316"            ,	   0x11800809467a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3317"            ,	   0x11800809467a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3318"            ,	   0x11800809467b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3319"            ,	   0x11800809467b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3320"            ,	   0x11800809467c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3321"            ,	   0x11800809467c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3322"            ,	   0x11800809467d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3323"            ,	   0x11800809467d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3324"            ,	   0x11800809467e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3325"            ,	   0x11800809467e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3326"            ,	   0x11800809467f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3327"            ,	   0x11800809467f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3328"            ,	   0x1180080946800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3329"            ,	   0x1180080946808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3330"            ,	   0x1180080946810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3331"            ,	   0x1180080946818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3332"            ,	   0x1180080946820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3333"            ,	   0x1180080946828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3334"            ,	   0x1180080946830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3335"            ,	   0x1180080946838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3336"            ,	   0x1180080946840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3337"            ,	   0x1180080946848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3338"            ,	   0x1180080946850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3339"            ,	   0x1180080946858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3340"            ,	   0x1180080946860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3341"            ,	   0x1180080946868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3342"            ,	   0x1180080946870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3343"            ,	   0x1180080946878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3344"            ,	   0x1180080946880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3345"            ,	   0x1180080946888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3346"            ,	   0x1180080946890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3347"            ,	   0x1180080946898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3348"            ,	   0x11800809468a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3349"            ,	   0x11800809468a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3350"            ,	   0x11800809468b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3351"            ,	   0x11800809468b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3352"            ,	   0x11800809468c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3353"            ,	   0x11800809468c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3354"            ,	   0x11800809468d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3355"            ,	   0x11800809468d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3356"            ,	   0x11800809468e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3357"            ,	   0x11800809468e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3358"            ,	   0x11800809468f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3359"            ,	   0x11800809468f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3360"            ,	   0x1180080946900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3361"            ,	   0x1180080946908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3362"            ,	   0x1180080946910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3363"            ,	   0x1180080946918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3364"            ,	   0x1180080946920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3365"            ,	   0x1180080946928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3366"            ,	   0x1180080946930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3367"            ,	   0x1180080946938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3368"            ,	   0x1180080946940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3369"            ,	   0x1180080946948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3370"            ,	   0x1180080946950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3371"            ,	   0x1180080946958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3372"            ,	   0x1180080946960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3373"            ,	   0x1180080946968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3374"            ,	   0x1180080946970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3375"            ,	   0x1180080946978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3376"            ,	   0x1180080946980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3377"            ,	   0x1180080946988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3378"            ,	   0x1180080946990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3379"            ,	   0x1180080946998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3380"            ,	   0x11800809469a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3381"            ,	   0x11800809469a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3382"            ,	   0x11800809469b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3383"            ,	   0x11800809469b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3384"            ,	   0x11800809469c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3385"            ,	   0x11800809469c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3386"            ,	   0x11800809469d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3387"            ,	   0x11800809469d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3388"            ,	   0x11800809469e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3389"            ,	   0x11800809469e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3390"            ,	   0x11800809469f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3391"            ,	   0x11800809469f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3392"            ,	   0x1180080946a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3393"            ,	   0x1180080946a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3394"            ,	   0x1180080946a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3395"            ,	   0x1180080946a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3396"            ,	   0x1180080946a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3397"            ,	   0x1180080946a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3398"            ,	   0x1180080946a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3399"            ,	   0x1180080946a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3400"            ,	   0x1180080946a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3401"            ,	   0x1180080946a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3402"            ,	   0x1180080946a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3403"            ,	   0x1180080946a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3404"            ,	   0x1180080946a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3405"            ,	   0x1180080946a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3406"            ,	   0x1180080946a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3407"            ,	   0x1180080946a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3408"            ,	   0x1180080946a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3409"            ,	   0x1180080946a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3410"            ,	   0x1180080946a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3411"            ,	   0x1180080946a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3412"            ,	   0x1180080946aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3413"            ,	   0x1180080946aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3414"            ,	   0x1180080946ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3415"            ,	   0x1180080946ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3416"            ,	   0x1180080946ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3417"            ,	   0x1180080946ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3418"            ,	   0x1180080946ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3419"            ,	   0x1180080946ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3420"            ,	   0x1180080946ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3421"            ,	   0x1180080946ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3422"            ,	   0x1180080946af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3423"            ,	   0x1180080946af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3424"            ,	   0x1180080946b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3425"            ,	   0x1180080946b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3426"            ,	   0x1180080946b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3427"            ,	   0x1180080946b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3428"            ,	   0x1180080946b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3429"            ,	   0x1180080946b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3430"            ,	   0x1180080946b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3431"            ,	   0x1180080946b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3432"            ,	   0x1180080946b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3433"            ,	   0x1180080946b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3434"            ,	   0x1180080946b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3435"            ,	   0x1180080946b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3436"            ,	   0x1180080946b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3437"            ,	   0x1180080946b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3438"            ,	   0x1180080946b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3439"            ,	   0x1180080946b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3440"            ,	   0x1180080946b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3441"            ,	   0x1180080946b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3442"            ,	   0x1180080946b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3443"            ,	   0x1180080946b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3444"            ,	   0x1180080946ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3445"            ,	   0x1180080946ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3446"            ,	   0x1180080946bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3447"            ,	   0x1180080946bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3448"            ,	   0x1180080946bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3449"            ,	   0x1180080946bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3450"            ,	   0x1180080946bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3451"            ,	   0x1180080946bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3452"            ,	   0x1180080946be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3453"            ,	   0x1180080946be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3454"            ,	   0x1180080946bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3455"            ,	   0x1180080946bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3456"            ,	   0x1180080946c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3457"            ,	   0x1180080946c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3458"            ,	   0x1180080946c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3459"            ,	   0x1180080946c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3460"            ,	   0x1180080946c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3461"            ,	   0x1180080946c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3462"            ,	   0x1180080946c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3463"            ,	   0x1180080946c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3464"            ,	   0x1180080946c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3465"            ,	   0x1180080946c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3466"            ,	   0x1180080946c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3467"            ,	   0x1180080946c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3468"            ,	   0x1180080946c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3469"            ,	   0x1180080946c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3470"            ,	   0x1180080946c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3471"            ,	   0x1180080946c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3472"            ,	   0x1180080946c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3473"            ,	   0x1180080946c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3474"            ,	   0x1180080946c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3475"            ,	   0x1180080946c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3476"            ,	   0x1180080946ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3477"            ,	   0x1180080946ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3478"            ,	   0x1180080946cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3479"            ,	   0x1180080946cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3480"            ,	   0x1180080946cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3481"            ,	   0x1180080946cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3482"            ,	   0x1180080946cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3483"            ,	   0x1180080946cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3484"            ,	   0x1180080946ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3485"            ,	   0x1180080946ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3486"            ,	   0x1180080946cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3487"            ,	   0x1180080946cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3488"            ,	   0x1180080946d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3489"            ,	   0x1180080946d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3490"            ,	   0x1180080946d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3491"            ,	   0x1180080946d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3492"            ,	   0x1180080946d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3493"            ,	   0x1180080946d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3494"            ,	   0x1180080946d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3495"            ,	   0x1180080946d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3496"            ,	   0x1180080946d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3497"            ,	   0x1180080946d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3498"            ,	   0x1180080946d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3499"            ,	   0x1180080946d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3500"            ,	   0x1180080946d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3501"            ,	   0x1180080946d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3502"            ,	   0x1180080946d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3503"            ,	   0x1180080946d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3504"            ,	   0x1180080946d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3505"            ,	   0x1180080946d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3506"            ,	   0x1180080946d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3507"            ,	   0x1180080946d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3508"            ,	   0x1180080946da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3509"            ,	   0x1180080946da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3510"            ,	   0x1180080946db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3511"            ,	   0x1180080946db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3512"            ,	   0x1180080946dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3513"            ,	   0x1180080946dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3514"            ,	   0x1180080946dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3515"            ,	   0x1180080946dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3516"            ,	   0x1180080946de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3517"            ,	   0x1180080946de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3518"            ,	   0x1180080946df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3519"            ,	   0x1180080946df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3520"            ,	   0x1180080946e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3521"            ,	   0x1180080946e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3522"            ,	   0x1180080946e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3523"            ,	   0x1180080946e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3524"            ,	   0x1180080946e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3525"            ,	   0x1180080946e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3526"            ,	   0x1180080946e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3527"            ,	   0x1180080946e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3528"            ,	   0x1180080946e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3529"            ,	   0x1180080946e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3530"            ,	   0x1180080946e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3531"            ,	   0x1180080946e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3532"            ,	   0x1180080946e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3533"            ,	   0x1180080946e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3534"            ,	   0x1180080946e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3535"            ,	   0x1180080946e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3536"            ,	   0x1180080946e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3537"            ,	   0x1180080946e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3538"            ,	   0x1180080946e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3539"            ,	   0x1180080946e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3540"            ,	   0x1180080946ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3541"            ,	   0x1180080946ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3542"            ,	   0x1180080946eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3543"            ,	   0x1180080946eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3544"            ,	   0x1180080946ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3545"            ,	   0x1180080946ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3546"            ,	   0x1180080946ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3547"            ,	   0x1180080946ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3548"            ,	   0x1180080946ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3549"            ,	   0x1180080946ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3550"            ,	   0x1180080946ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3551"            ,	   0x1180080946ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3552"            ,	   0x1180080946f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3553"            ,	   0x1180080946f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3554"            ,	   0x1180080946f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3555"            ,	   0x1180080946f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3556"            ,	   0x1180080946f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3557"            ,	   0x1180080946f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3558"            ,	   0x1180080946f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3559"            ,	   0x1180080946f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3560"            ,	   0x1180080946f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3561"            ,	   0x1180080946f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3562"            ,	   0x1180080946f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3563"            ,	   0x1180080946f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3564"            ,	   0x1180080946f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3565"            ,	   0x1180080946f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3566"            ,	   0x1180080946f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3567"            ,	   0x1180080946f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3568"            ,	   0x1180080946f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3569"            ,	   0x1180080946f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3570"            ,	   0x1180080946f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3571"            ,	   0x1180080946f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3572"            ,	   0x1180080946fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3573"            ,	   0x1180080946fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3574"            ,	   0x1180080946fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3575"            ,	   0x1180080946fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3576"            ,	   0x1180080946fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3577"            ,	   0x1180080946fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3578"            ,	   0x1180080946fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3579"            ,	   0x1180080946fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3580"            ,	   0x1180080946fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3581"            ,	   0x1180080946fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3582"            ,	   0x1180080946ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3583"            ,	   0x1180080946ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3584"            ,	   0x1180080947000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3585"            ,	   0x1180080947008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3586"            ,	   0x1180080947010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3587"            ,	   0x1180080947018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3588"            ,	   0x1180080947020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3589"            ,	   0x1180080947028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3590"            ,	   0x1180080947030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3591"            ,	   0x1180080947038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3592"            ,	   0x1180080947040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3593"            ,	   0x1180080947048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3594"            ,	   0x1180080947050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3595"            ,	   0x1180080947058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3596"            ,	   0x1180080947060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3597"            ,	   0x1180080947068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3598"            ,	   0x1180080947070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3599"            ,	   0x1180080947078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3600"            ,	   0x1180080947080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3601"            ,	   0x1180080947088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3602"            ,	   0x1180080947090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3603"            ,	   0x1180080947098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3604"            ,	   0x11800809470a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3605"            ,	   0x11800809470a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3606"            ,	   0x11800809470b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3607"            ,	   0x11800809470b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3608"            ,	   0x11800809470c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3609"            ,	   0x11800809470c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3610"            ,	   0x11800809470d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3611"            ,	   0x11800809470d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3612"            ,	   0x11800809470e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3613"            ,	   0x11800809470e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3614"            ,	   0x11800809470f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3615"            ,	   0x11800809470f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3616"            ,	   0x1180080947100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3617"            ,	   0x1180080947108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3618"            ,	   0x1180080947110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3619"            ,	   0x1180080947118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3620"            ,	   0x1180080947120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3621"            ,	   0x1180080947128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3622"            ,	   0x1180080947130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3623"            ,	   0x1180080947138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3624"            ,	   0x1180080947140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3625"            ,	   0x1180080947148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3626"            ,	   0x1180080947150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3627"            ,	   0x1180080947158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3628"            ,	   0x1180080947160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3629"            ,	   0x1180080947168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3630"            ,	   0x1180080947170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3631"            ,	   0x1180080947178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3632"            ,	   0x1180080947180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3633"            ,	   0x1180080947188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3634"            ,	   0x1180080947190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3635"            ,	   0x1180080947198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3636"            ,	   0x11800809471a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3637"            ,	   0x11800809471a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3638"            ,	   0x11800809471b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3639"            ,	   0x11800809471b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3640"            ,	   0x11800809471c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3641"            ,	   0x11800809471c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3642"            ,	   0x11800809471d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3643"            ,	   0x11800809471d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3644"            ,	   0x11800809471e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3645"            ,	   0x11800809471e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3646"            ,	   0x11800809471f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3647"            ,	   0x11800809471f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3648"            ,	   0x1180080947200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3649"            ,	   0x1180080947208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3650"            ,	   0x1180080947210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3651"            ,	   0x1180080947218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3652"            ,	   0x1180080947220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3653"            ,	   0x1180080947228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3654"            ,	   0x1180080947230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3655"            ,	   0x1180080947238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3656"            ,	   0x1180080947240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3657"            ,	   0x1180080947248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3658"            ,	   0x1180080947250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3659"            ,	   0x1180080947258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3660"            ,	   0x1180080947260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3661"            ,	   0x1180080947268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3662"            ,	   0x1180080947270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3663"            ,	   0x1180080947278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3664"            ,	   0x1180080947280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3665"            ,	   0x1180080947288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3666"            ,	   0x1180080947290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3667"            ,	   0x1180080947298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3668"            ,	   0x11800809472a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3669"            ,	   0x11800809472a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3670"            ,	   0x11800809472b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3671"            ,	   0x11800809472b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3672"            ,	   0x11800809472c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3673"            ,	   0x11800809472c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3674"            ,	   0x11800809472d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3675"            ,	   0x11800809472d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3676"            ,	   0x11800809472e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3677"            ,	   0x11800809472e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3678"            ,	   0x11800809472f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3679"            ,	   0x11800809472f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3680"            ,	   0x1180080947300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3681"            ,	   0x1180080947308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3682"            ,	   0x1180080947310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3683"            ,	   0x1180080947318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3684"            ,	   0x1180080947320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3685"            ,	   0x1180080947328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3686"            ,	   0x1180080947330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3687"            ,	   0x1180080947338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3688"            ,	   0x1180080947340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3689"            ,	   0x1180080947348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3690"            ,	   0x1180080947350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3691"            ,	   0x1180080947358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3692"            ,	   0x1180080947360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3693"            ,	   0x1180080947368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3694"            ,	   0x1180080947370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3695"            ,	   0x1180080947378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3696"            ,	   0x1180080947380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3697"            ,	   0x1180080947388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3698"            ,	   0x1180080947390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3699"            ,	   0x1180080947398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3700"            ,	   0x11800809473a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3701"            ,	   0x11800809473a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3702"            ,	   0x11800809473b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3703"            ,	   0x11800809473b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3704"            ,	   0x11800809473c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3705"            ,	   0x11800809473c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3706"            ,	   0x11800809473d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3707"            ,	   0x11800809473d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3708"            ,	   0x11800809473e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3709"            ,	   0x11800809473e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3710"            ,	   0x11800809473f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3711"            ,	   0x11800809473f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3712"            ,	   0x1180080947400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3713"            ,	   0x1180080947408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3714"            ,	   0x1180080947410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3715"            ,	   0x1180080947418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3716"            ,	   0x1180080947420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3717"            ,	   0x1180080947428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3718"            ,	   0x1180080947430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3719"            ,	   0x1180080947438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3720"            ,	   0x1180080947440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3721"            ,	   0x1180080947448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3722"            ,	   0x1180080947450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3723"            ,	   0x1180080947458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3724"            ,	   0x1180080947460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3725"            ,	   0x1180080947468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3726"            ,	   0x1180080947470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3727"            ,	   0x1180080947478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3728"            ,	   0x1180080947480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3729"            ,	   0x1180080947488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3730"            ,	   0x1180080947490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3731"            ,	   0x1180080947498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3732"            ,	   0x11800809474a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3733"            ,	   0x11800809474a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3734"            ,	   0x11800809474b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3735"            ,	   0x11800809474b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3736"            ,	   0x11800809474c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3737"            ,	   0x11800809474c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3738"            ,	   0x11800809474d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3739"            ,	   0x11800809474d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3740"            ,	   0x11800809474e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3741"            ,	   0x11800809474e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3742"            ,	   0x11800809474f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3743"            ,	   0x11800809474f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3744"            ,	   0x1180080947500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3745"            ,	   0x1180080947508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3746"            ,	   0x1180080947510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3747"            ,	   0x1180080947518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3748"            ,	   0x1180080947520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3749"            ,	   0x1180080947528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3750"            ,	   0x1180080947530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3751"            ,	   0x1180080947538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3752"            ,	   0x1180080947540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3753"            ,	   0x1180080947548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3754"            ,	   0x1180080947550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3755"            ,	   0x1180080947558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3756"            ,	   0x1180080947560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3757"            ,	   0x1180080947568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3758"            ,	   0x1180080947570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3759"            ,	   0x1180080947578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3760"            ,	   0x1180080947580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3761"            ,	   0x1180080947588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3762"            ,	   0x1180080947590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3763"            ,	   0x1180080947598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3764"            ,	   0x11800809475a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3765"            ,	   0x11800809475a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3766"            ,	   0x11800809475b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3767"            ,	   0x11800809475b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3768"            ,	   0x11800809475c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3769"            ,	   0x11800809475c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3770"            ,	   0x11800809475d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3771"            ,	   0x11800809475d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3772"            ,	   0x11800809475e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3773"            ,	   0x11800809475e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3774"            ,	   0x11800809475f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3775"            ,	   0x11800809475f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3776"            ,	   0x1180080947600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3777"            ,	   0x1180080947608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3778"            ,	   0x1180080947610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3779"            ,	   0x1180080947618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3780"            ,	   0x1180080947620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3781"            ,	   0x1180080947628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3782"            ,	   0x1180080947630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3783"            ,	   0x1180080947638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3784"            ,	   0x1180080947640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3785"            ,	   0x1180080947648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3786"            ,	   0x1180080947650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3787"            ,	   0x1180080947658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3788"            ,	   0x1180080947660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3789"            ,	   0x1180080947668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3790"            ,	   0x1180080947670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3791"            ,	   0x1180080947678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3792"            ,	   0x1180080947680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3793"            ,	   0x1180080947688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3794"            ,	   0x1180080947690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3795"            ,	   0x1180080947698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3796"            ,	   0x11800809476a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3797"            ,	   0x11800809476a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3798"            ,	   0x11800809476b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3799"            ,	   0x11800809476b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3800"            ,	   0x11800809476c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3801"            ,	   0x11800809476c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3802"            ,	   0x11800809476d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3803"            ,	   0x11800809476d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3804"            ,	   0x11800809476e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3805"            ,	   0x11800809476e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3806"            ,	   0x11800809476f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3807"            ,	   0x11800809476f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3808"            ,	   0x1180080947700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3809"            ,	   0x1180080947708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3810"            ,	   0x1180080947710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3811"            ,	   0x1180080947718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3812"            ,	   0x1180080947720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3813"            ,	   0x1180080947728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3814"            ,	   0x1180080947730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3815"            ,	   0x1180080947738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3816"            ,	   0x1180080947740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3817"            ,	   0x1180080947748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3818"            ,	   0x1180080947750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3819"            ,	   0x1180080947758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3820"            ,	   0x1180080947760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3821"            ,	   0x1180080947768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3822"            ,	   0x1180080947770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3823"            ,	   0x1180080947778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3824"            ,	   0x1180080947780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3825"            ,	   0x1180080947788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3826"            ,	   0x1180080947790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3827"            ,	   0x1180080947798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3828"            ,	   0x11800809477a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3829"            ,	   0x11800809477a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3830"            ,	   0x11800809477b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3831"            ,	   0x11800809477b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3832"            ,	   0x11800809477c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3833"            ,	   0x11800809477c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3834"            ,	   0x11800809477d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3835"            ,	   0x11800809477d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3836"            ,	   0x11800809477e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3837"            ,	   0x11800809477e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3838"            ,	   0x11800809477f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3839"            ,	   0x11800809477f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3840"            ,	   0x1180080947800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3841"            ,	   0x1180080947808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3842"            ,	   0x1180080947810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3843"            ,	   0x1180080947818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3844"            ,	   0x1180080947820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3845"            ,	   0x1180080947828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3846"            ,	   0x1180080947830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3847"            ,	   0x1180080947838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3848"            ,	   0x1180080947840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3849"            ,	   0x1180080947848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3850"            ,	   0x1180080947850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3851"            ,	   0x1180080947858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3852"            ,	   0x1180080947860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3853"            ,	   0x1180080947868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3854"            ,	   0x1180080947870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3855"            ,	   0x1180080947878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3856"            ,	   0x1180080947880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3857"            ,	   0x1180080947888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3858"            ,	   0x1180080947890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3859"            ,	   0x1180080947898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3860"            ,	   0x11800809478a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3861"            ,	   0x11800809478a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3862"            ,	   0x11800809478b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3863"            ,	   0x11800809478b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3864"            ,	   0x11800809478c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3865"            ,	   0x11800809478c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3866"            ,	   0x11800809478d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3867"            ,	   0x11800809478d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3868"            ,	   0x11800809478e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3869"            ,	   0x11800809478e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3870"            ,	   0x11800809478f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3871"            ,	   0x11800809478f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3872"            ,	   0x1180080947900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3873"            ,	   0x1180080947908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3874"            ,	   0x1180080947910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3875"            ,	   0x1180080947918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3876"            ,	   0x1180080947920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3877"            ,	   0x1180080947928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3878"            ,	   0x1180080947930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3879"            ,	   0x1180080947938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3880"            ,	   0x1180080947940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3881"            ,	   0x1180080947948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3882"            ,	   0x1180080947950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3883"            ,	   0x1180080947958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3884"            ,	   0x1180080947960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3885"            ,	   0x1180080947968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3886"            ,	   0x1180080947970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3887"            ,	   0x1180080947978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3888"            ,	   0x1180080947980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3889"            ,	   0x1180080947988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3890"            ,	   0x1180080947990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3891"            ,	   0x1180080947998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3892"            ,	   0x11800809479a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3893"            ,	   0x11800809479a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3894"            ,	   0x11800809479b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3895"            ,	   0x11800809479b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3896"            ,	   0x11800809479c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3897"            ,	   0x11800809479c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3898"            ,	   0x11800809479d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3899"            ,	   0x11800809479d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3900"            ,	   0x11800809479e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3901"            ,	   0x11800809479e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3902"            ,	   0x11800809479f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3903"            ,	   0x11800809479f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3904"            ,	   0x1180080947a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3905"            ,	   0x1180080947a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3906"            ,	   0x1180080947a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3907"            ,	   0x1180080947a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3908"            ,	   0x1180080947a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3909"            ,	   0x1180080947a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3910"            ,	   0x1180080947a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3911"            ,	   0x1180080947a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3912"            ,	   0x1180080947a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3913"            ,	   0x1180080947a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3914"            ,	   0x1180080947a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3915"            ,	   0x1180080947a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3916"            ,	   0x1180080947a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3917"            ,	   0x1180080947a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3918"            ,	   0x1180080947a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3919"            ,	   0x1180080947a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3920"            ,	   0x1180080947a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3921"            ,	   0x1180080947a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3922"            ,	   0x1180080947a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3923"            ,	   0x1180080947a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3924"            ,	   0x1180080947aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3925"            ,	   0x1180080947aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3926"            ,	   0x1180080947ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3927"            ,	   0x1180080947ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3928"            ,	   0x1180080947ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3929"            ,	   0x1180080947ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3930"            ,	   0x1180080947ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3931"            ,	   0x1180080947ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3932"            ,	   0x1180080947ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3933"            ,	   0x1180080947ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3934"            ,	   0x1180080947af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3935"            ,	   0x1180080947af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3936"            ,	   0x1180080947b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3937"            ,	   0x1180080947b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3938"            ,	   0x1180080947b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3939"            ,	   0x1180080947b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3940"            ,	   0x1180080947b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3941"            ,	   0x1180080947b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3942"            ,	   0x1180080947b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3943"            ,	   0x1180080947b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3944"            ,	   0x1180080947b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3945"            ,	   0x1180080947b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3946"            ,	   0x1180080947b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3947"            ,	   0x1180080947b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3948"            ,	   0x1180080947b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3949"            ,	   0x1180080947b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3950"            ,	   0x1180080947b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3951"            ,	   0x1180080947b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3952"            ,	   0x1180080947b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3953"            ,	   0x1180080947b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3954"            ,	   0x1180080947b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3955"            ,	   0x1180080947b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3956"            ,	   0x1180080947ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3957"            ,	   0x1180080947ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3958"            ,	   0x1180080947bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3959"            ,	   0x1180080947bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3960"            ,	   0x1180080947bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3961"            ,	   0x1180080947bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3962"            ,	   0x1180080947bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3963"            ,	   0x1180080947bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3964"            ,	   0x1180080947be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3965"            ,	   0x1180080947be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3966"            ,	   0x1180080947bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3967"            ,	   0x1180080947bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3968"            ,	   0x1180080947c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3969"            ,	   0x1180080947c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3970"            ,	   0x1180080947c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3971"            ,	   0x1180080947c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3972"            ,	   0x1180080947c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3973"            ,	   0x1180080947c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3974"            ,	   0x1180080947c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3975"            ,	   0x1180080947c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3976"            ,	   0x1180080947c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3977"            ,	   0x1180080947c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3978"            ,	   0x1180080947c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3979"            ,	   0x1180080947c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3980"            ,	   0x1180080947c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3981"            ,	   0x1180080947c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3982"            ,	   0x1180080947c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3983"            ,	   0x1180080947c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3984"            ,	   0x1180080947c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3985"            ,	   0x1180080947c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3986"            ,	   0x1180080947c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3987"            ,	   0x1180080947c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3988"            ,	   0x1180080947ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3989"            ,	   0x1180080947ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3990"            ,	   0x1180080947cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3991"            ,	   0x1180080947cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3992"            ,	   0x1180080947cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3993"            ,	   0x1180080947cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3994"            ,	   0x1180080947cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3995"            ,	   0x1180080947cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3996"            ,	   0x1180080947ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3997"            ,	   0x1180080947ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3998"            ,	   0x1180080947cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP3999"            ,	   0x1180080947cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4000"            ,	   0x1180080947d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4001"            ,	   0x1180080947d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4002"            ,	   0x1180080947d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4003"            ,	   0x1180080947d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4004"            ,	   0x1180080947d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4005"            ,	   0x1180080947d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4006"            ,	   0x1180080947d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4007"            ,	   0x1180080947d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4008"            ,	   0x1180080947d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4009"            ,	   0x1180080947d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4010"            ,	   0x1180080947d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4011"            ,	   0x1180080947d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4012"            ,	   0x1180080947d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4013"            ,	   0x1180080947d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4014"            ,	   0x1180080947d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4015"            ,	   0x1180080947d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4016"            ,	   0x1180080947d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4017"            ,	   0x1180080947d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4018"            ,	   0x1180080947d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4019"            ,	   0x1180080947d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4020"            ,	   0x1180080947da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4021"            ,	   0x1180080947da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4022"            ,	   0x1180080947db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4023"            ,	   0x1180080947db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4024"            ,	   0x1180080947dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4025"            ,	   0x1180080947dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4026"            ,	   0x1180080947dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4027"            ,	   0x1180080947dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4028"            ,	   0x1180080947de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4029"            ,	   0x1180080947de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4030"            ,	   0x1180080947df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4031"            ,	   0x1180080947df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4032"            ,	   0x1180080947e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4033"            ,	   0x1180080947e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4034"            ,	   0x1180080947e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4035"            ,	   0x1180080947e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4036"            ,	   0x1180080947e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4037"            ,	   0x1180080947e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4038"            ,	   0x1180080947e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4039"            ,	   0x1180080947e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4040"            ,	   0x1180080947e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4041"            ,	   0x1180080947e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4042"            ,	   0x1180080947e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4043"            ,	   0x1180080947e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4044"            ,	   0x1180080947e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4045"            ,	   0x1180080947e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4046"            ,	   0x1180080947e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4047"            ,	   0x1180080947e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4048"            ,	   0x1180080947e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4049"            ,	   0x1180080947e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4050"            ,	   0x1180080947e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4051"            ,	   0x1180080947e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4052"            ,	   0x1180080947ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4053"            ,	   0x1180080947ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4054"            ,	   0x1180080947eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4055"            ,	   0x1180080947eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4056"            ,	   0x1180080947ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4057"            ,	   0x1180080947ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4058"            ,	   0x1180080947ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4059"            ,	   0x1180080947ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4060"            ,	   0x1180080947ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4061"            ,	   0x1180080947ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4062"            ,	   0x1180080947ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4063"            ,	   0x1180080947ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4064"            ,	   0x1180080947f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4065"            ,	   0x1180080947f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4066"            ,	   0x1180080947f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4067"            ,	   0x1180080947f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4068"            ,	   0x1180080947f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4069"            ,	   0x1180080947f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4070"            ,	   0x1180080947f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4071"            ,	   0x1180080947f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4072"            ,	   0x1180080947f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4073"            ,	   0x1180080947f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4074"            ,	   0x1180080947f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4075"            ,	   0x1180080947f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4076"            ,	   0x1180080947f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4077"            ,	   0x1180080947f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4078"            ,	   0x1180080947f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4079"            ,	   0x1180080947f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4080"            ,	   0x1180080947f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4081"            ,	   0x1180080947f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4082"            ,	   0x1180080947f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4083"            ,	   0x1180080947f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4084"            ,	   0x1180080947fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4085"            ,	   0x1180080947fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4086"            ,	   0x1180080947fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4087"            ,	   0x1180080947fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4088"            ,	   0x1180080947fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4089"            ,	   0x1180080947fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4090"            ,	   0x1180080947fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4091"            ,	   0x1180080947fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4092"            ,	   0x1180080947fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4093"            ,	   0x1180080947fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4094"            ,	   0x1180080947ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4095"            ,	   0x1180080947ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4096"            ,	   0x1180080948000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4097"            ,	   0x1180080948008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4098"            ,	   0x1180080948010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4099"            ,	   0x1180080948018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4100"            ,	   0x1180080948020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4101"            ,	   0x1180080948028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4102"            ,	   0x1180080948030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4103"            ,	   0x1180080948038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4104"            ,	   0x1180080948040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4105"            ,	   0x1180080948048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4106"            ,	   0x1180080948050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4107"            ,	   0x1180080948058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4108"            ,	   0x1180080948060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4109"            ,	   0x1180080948068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4110"            ,	   0x1180080948070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4111"            ,	   0x1180080948078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4112"            ,	   0x1180080948080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4113"            ,	   0x1180080948088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4114"            ,	   0x1180080948090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4115"            ,	   0x1180080948098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4116"            ,	   0x11800809480a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4117"            ,	   0x11800809480a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4118"            ,	   0x11800809480b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4119"            ,	   0x11800809480b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4120"            ,	   0x11800809480c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4121"            ,	   0x11800809480c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4122"            ,	   0x11800809480d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4123"            ,	   0x11800809480d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4124"            ,	   0x11800809480e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4125"            ,	   0x11800809480e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4126"            ,	   0x11800809480f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4127"            ,	   0x11800809480f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4128"            ,	   0x1180080948100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4129"            ,	   0x1180080948108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4130"            ,	   0x1180080948110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4131"            ,	   0x1180080948118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4132"            ,	   0x1180080948120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4133"            ,	   0x1180080948128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4134"            ,	   0x1180080948130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4135"            ,	   0x1180080948138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4136"            ,	   0x1180080948140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4137"            ,	   0x1180080948148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4138"            ,	   0x1180080948150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4139"            ,	   0x1180080948158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4140"            ,	   0x1180080948160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4141"            ,	   0x1180080948168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4142"            ,	   0x1180080948170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4143"            ,	   0x1180080948178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4144"            ,	   0x1180080948180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4145"            ,	   0x1180080948188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4146"            ,	   0x1180080948190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4147"            ,	   0x1180080948198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4148"            ,	   0x11800809481a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4149"            ,	   0x11800809481a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4150"            ,	   0x11800809481b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4151"            ,	   0x11800809481b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4152"            ,	   0x11800809481c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4153"            ,	   0x11800809481c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4154"            ,	   0x11800809481d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4155"            ,	   0x11800809481d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4156"            ,	   0x11800809481e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4157"            ,	   0x11800809481e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4158"            ,	   0x11800809481f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4159"            ,	   0x11800809481f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4160"            ,	   0x1180080948200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4161"            ,	   0x1180080948208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4162"            ,	   0x1180080948210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4163"            ,	   0x1180080948218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4164"            ,	   0x1180080948220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4165"            ,	   0x1180080948228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4166"            ,	   0x1180080948230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4167"            ,	   0x1180080948238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4168"            ,	   0x1180080948240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4169"            ,	   0x1180080948248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4170"            ,	   0x1180080948250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4171"            ,	   0x1180080948258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4172"            ,	   0x1180080948260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4173"            ,	   0x1180080948268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4174"            ,	   0x1180080948270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4175"            ,	   0x1180080948278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4176"            ,	   0x1180080948280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4177"            ,	   0x1180080948288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4178"            ,	   0x1180080948290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4179"            ,	   0x1180080948298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4180"            ,	   0x11800809482a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4181"            ,	   0x11800809482a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4182"            ,	   0x11800809482b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4183"            ,	   0x11800809482b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4184"            ,	   0x11800809482c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4185"            ,	   0x11800809482c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4186"            ,	   0x11800809482d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4187"            ,	   0x11800809482d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4188"            ,	   0x11800809482e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4189"            ,	   0x11800809482e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4190"            ,	   0x11800809482f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4191"            ,	   0x11800809482f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4192"            ,	   0x1180080948300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4193"            ,	   0x1180080948308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4194"            ,	   0x1180080948310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4195"            ,	   0x1180080948318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4196"            ,	   0x1180080948320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4197"            ,	   0x1180080948328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4198"            ,	   0x1180080948330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4199"            ,	   0x1180080948338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4200"            ,	   0x1180080948340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4201"            ,	   0x1180080948348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4202"            ,	   0x1180080948350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4203"            ,	   0x1180080948358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4204"            ,	   0x1180080948360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4205"            ,	   0x1180080948368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4206"            ,	   0x1180080948370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4207"            ,	   0x1180080948378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4208"            ,	   0x1180080948380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4209"            ,	   0x1180080948388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4210"            ,	   0x1180080948390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4211"            ,	   0x1180080948398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4212"            ,	   0x11800809483a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4213"            ,	   0x11800809483a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4214"            ,	   0x11800809483b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4215"            ,	   0x11800809483b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4216"            ,	   0x11800809483c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4217"            ,	   0x11800809483c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4218"            ,	   0x11800809483d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4219"            ,	   0x11800809483d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4220"            ,	   0x11800809483e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4221"            ,	   0x11800809483e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4222"            ,	   0x11800809483f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4223"            ,	   0x11800809483f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4224"            ,	   0x1180080948400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4225"            ,	   0x1180080948408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4226"            ,	   0x1180080948410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4227"            ,	   0x1180080948418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4228"            ,	   0x1180080948420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4229"            ,	   0x1180080948428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4230"            ,	   0x1180080948430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4231"            ,	   0x1180080948438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4232"            ,	   0x1180080948440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4233"            ,	   0x1180080948448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4234"            ,	   0x1180080948450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4235"            ,	   0x1180080948458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4236"            ,	   0x1180080948460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4237"            ,	   0x1180080948468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4238"            ,	   0x1180080948470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4239"            ,	   0x1180080948478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4240"            ,	   0x1180080948480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4241"            ,	   0x1180080948488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4242"            ,	   0x1180080948490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4243"            ,	   0x1180080948498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4244"            ,	   0x11800809484a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4245"            ,	   0x11800809484a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4246"            ,	   0x11800809484b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4247"            ,	   0x11800809484b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4248"            ,	   0x11800809484c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4249"            ,	   0x11800809484c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4250"            ,	   0x11800809484d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4251"            ,	   0x11800809484d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4252"            ,	   0x11800809484e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4253"            ,	   0x11800809484e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4254"            ,	   0x11800809484f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4255"            ,	   0x11800809484f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4256"            ,	   0x1180080948500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4257"            ,	   0x1180080948508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4258"            ,	   0x1180080948510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4259"            ,	   0x1180080948518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4260"            ,	   0x1180080948520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4261"            ,	   0x1180080948528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4262"            ,	   0x1180080948530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4263"            ,	   0x1180080948538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4264"            ,	   0x1180080948540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4265"            ,	   0x1180080948548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4266"            ,	   0x1180080948550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4267"            ,	   0x1180080948558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4268"            ,	   0x1180080948560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4269"            ,	   0x1180080948568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4270"            ,	   0x1180080948570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4271"            ,	   0x1180080948578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4272"            ,	   0x1180080948580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4273"            ,	   0x1180080948588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4274"            ,	   0x1180080948590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4275"            ,	   0x1180080948598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4276"            ,	   0x11800809485a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4277"            ,	   0x11800809485a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4278"            ,	   0x11800809485b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4279"            ,	   0x11800809485b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4280"            ,	   0x11800809485c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4281"            ,	   0x11800809485c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4282"            ,	   0x11800809485d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4283"            ,	   0x11800809485d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4284"            ,	   0x11800809485e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4285"            ,	   0x11800809485e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4286"            ,	   0x11800809485f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4287"            ,	   0x11800809485f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4288"            ,	   0x1180080948600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4289"            ,	   0x1180080948608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4290"            ,	   0x1180080948610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4291"            ,	   0x1180080948618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4292"            ,	   0x1180080948620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4293"            ,	   0x1180080948628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4294"            ,	   0x1180080948630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4295"            ,	   0x1180080948638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4296"            ,	   0x1180080948640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4297"            ,	   0x1180080948648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4298"            ,	   0x1180080948650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4299"            ,	   0x1180080948658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4300"            ,	   0x1180080948660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4301"            ,	   0x1180080948668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4302"            ,	   0x1180080948670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4303"            ,	   0x1180080948678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4304"            ,	   0x1180080948680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4305"            ,	   0x1180080948688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4306"            ,	   0x1180080948690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4307"            ,	   0x1180080948698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4308"            ,	   0x11800809486a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4309"            ,	   0x11800809486a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4310"            ,	   0x11800809486b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4311"            ,	   0x11800809486b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4312"            ,	   0x11800809486c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4313"            ,	   0x11800809486c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4314"            ,	   0x11800809486d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4315"            ,	   0x11800809486d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4316"            ,	   0x11800809486e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4317"            ,	   0x11800809486e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4318"            ,	   0x11800809486f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4319"            ,	   0x11800809486f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4320"            ,	   0x1180080948700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4321"            ,	   0x1180080948708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4322"            ,	   0x1180080948710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4323"            ,	   0x1180080948718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4324"            ,	   0x1180080948720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4325"            ,	   0x1180080948728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4326"            ,	   0x1180080948730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4327"            ,	   0x1180080948738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4328"            ,	   0x1180080948740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4329"            ,	   0x1180080948748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4330"            ,	   0x1180080948750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4331"            ,	   0x1180080948758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4332"            ,	   0x1180080948760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4333"            ,	   0x1180080948768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4334"            ,	   0x1180080948770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4335"            ,	   0x1180080948778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4336"            ,	   0x1180080948780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4337"            ,	   0x1180080948788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4338"            ,	   0x1180080948790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4339"            ,	   0x1180080948798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4340"            ,	   0x11800809487a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4341"            ,	   0x11800809487a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4342"            ,	   0x11800809487b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4343"            ,	   0x11800809487b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4344"            ,	   0x11800809487c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4345"            ,	   0x11800809487c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4346"            ,	   0x11800809487d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4347"            ,	   0x11800809487d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4348"            ,	   0x11800809487e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4349"            ,	   0x11800809487e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4350"            ,	   0x11800809487f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4351"            ,	   0x11800809487f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4352"            ,	   0x1180080948800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4353"            ,	   0x1180080948808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4354"            ,	   0x1180080948810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4355"            ,	   0x1180080948818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4356"            ,	   0x1180080948820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4357"            ,	   0x1180080948828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4358"            ,	   0x1180080948830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4359"            ,	   0x1180080948838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4360"            ,	   0x1180080948840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4361"            ,	   0x1180080948848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4362"            ,	   0x1180080948850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4363"            ,	   0x1180080948858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4364"            ,	   0x1180080948860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4365"            ,	   0x1180080948868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4366"            ,	   0x1180080948870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4367"            ,	   0x1180080948878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4368"            ,	   0x1180080948880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4369"            ,	   0x1180080948888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4370"            ,	   0x1180080948890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4371"            ,	   0x1180080948898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4372"            ,	   0x11800809488a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4373"            ,	   0x11800809488a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4374"            ,	   0x11800809488b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4375"            ,	   0x11800809488b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4376"            ,	   0x11800809488c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4377"            ,	   0x11800809488c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4378"            ,	   0x11800809488d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4379"            ,	   0x11800809488d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4380"            ,	   0x11800809488e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4381"            ,	   0x11800809488e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4382"            ,	   0x11800809488f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4383"            ,	   0x11800809488f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4384"            ,	   0x1180080948900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4385"            ,	   0x1180080948908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4386"            ,	   0x1180080948910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4387"            ,	   0x1180080948918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4388"            ,	   0x1180080948920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4389"            ,	   0x1180080948928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4390"            ,	   0x1180080948930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4391"            ,	   0x1180080948938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4392"            ,	   0x1180080948940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4393"            ,	   0x1180080948948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4394"            ,	   0x1180080948950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4395"            ,	   0x1180080948958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4396"            ,	   0x1180080948960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4397"            ,	   0x1180080948968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4398"            ,	   0x1180080948970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4399"            ,	   0x1180080948978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4400"            ,	   0x1180080948980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4401"            ,	   0x1180080948988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4402"            ,	   0x1180080948990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4403"            ,	   0x1180080948998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4404"            ,	   0x11800809489a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4405"            ,	   0x11800809489a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4406"            ,	   0x11800809489b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4407"            ,	   0x11800809489b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4408"            ,	   0x11800809489c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4409"            ,	   0x11800809489c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4410"            ,	   0x11800809489d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4411"            ,	   0x11800809489d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4412"            ,	   0x11800809489e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4413"            ,	   0x11800809489e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4414"            ,	   0x11800809489f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4415"            ,	   0x11800809489f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4416"            ,	   0x1180080948a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4417"            ,	   0x1180080948a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4418"            ,	   0x1180080948a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4419"            ,	   0x1180080948a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4420"            ,	   0x1180080948a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4421"            ,	   0x1180080948a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4422"            ,	   0x1180080948a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4423"            ,	   0x1180080948a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4424"            ,	   0x1180080948a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4425"            ,	   0x1180080948a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4426"            ,	   0x1180080948a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4427"            ,	   0x1180080948a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4428"            ,	   0x1180080948a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4429"            ,	   0x1180080948a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4430"            ,	   0x1180080948a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4431"            ,	   0x1180080948a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4432"            ,	   0x1180080948a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4433"            ,	   0x1180080948a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4434"            ,	   0x1180080948a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4435"            ,	   0x1180080948a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4436"            ,	   0x1180080948aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4437"            ,	   0x1180080948aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4438"            ,	   0x1180080948ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4439"            ,	   0x1180080948ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4440"            ,	   0x1180080948ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4441"            ,	   0x1180080948ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4442"            ,	   0x1180080948ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4443"            ,	   0x1180080948ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4444"            ,	   0x1180080948ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4445"            ,	   0x1180080948ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4446"            ,	   0x1180080948af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4447"            ,	   0x1180080948af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4448"            ,	   0x1180080948b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4449"            ,	   0x1180080948b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4450"            ,	   0x1180080948b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4451"            ,	   0x1180080948b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4452"            ,	   0x1180080948b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4453"            ,	   0x1180080948b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4454"            ,	   0x1180080948b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4455"            ,	   0x1180080948b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4456"            ,	   0x1180080948b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4457"            ,	   0x1180080948b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4458"            ,	   0x1180080948b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4459"            ,	   0x1180080948b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4460"            ,	   0x1180080948b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4461"            ,	   0x1180080948b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4462"            ,	   0x1180080948b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4463"            ,	   0x1180080948b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4464"            ,	   0x1180080948b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4465"            ,	   0x1180080948b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4466"            ,	   0x1180080948b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4467"            ,	   0x1180080948b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4468"            ,	   0x1180080948ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4469"            ,	   0x1180080948ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4470"            ,	   0x1180080948bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4471"            ,	   0x1180080948bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4472"            ,	   0x1180080948bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4473"            ,	   0x1180080948bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4474"            ,	   0x1180080948bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4475"            ,	   0x1180080948bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4476"            ,	   0x1180080948be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4477"            ,	   0x1180080948be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4478"            ,	   0x1180080948bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4479"            ,	   0x1180080948bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4480"            ,	   0x1180080948c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4481"            ,	   0x1180080948c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4482"            ,	   0x1180080948c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4483"            ,	   0x1180080948c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4484"            ,	   0x1180080948c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4485"            ,	   0x1180080948c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4486"            ,	   0x1180080948c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4487"            ,	   0x1180080948c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4488"            ,	   0x1180080948c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4489"            ,	   0x1180080948c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4490"            ,	   0x1180080948c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4491"            ,	   0x1180080948c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4492"            ,	   0x1180080948c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4493"            ,	   0x1180080948c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4494"            ,	   0x1180080948c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4495"            ,	   0x1180080948c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4496"            ,	   0x1180080948c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4497"            ,	   0x1180080948c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4498"            ,	   0x1180080948c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4499"            ,	   0x1180080948c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4500"            ,	   0x1180080948ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4501"            ,	   0x1180080948ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4502"            ,	   0x1180080948cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4503"            ,	   0x1180080948cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4504"            ,	   0x1180080948cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4505"            ,	   0x1180080948cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4506"            ,	   0x1180080948cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4507"            ,	   0x1180080948cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4508"            ,	   0x1180080948ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4509"            ,	   0x1180080948ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4510"            ,	   0x1180080948cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4511"            ,	   0x1180080948cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4512"            ,	   0x1180080948d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4513"            ,	   0x1180080948d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4514"            ,	   0x1180080948d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4515"            ,	   0x1180080948d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4516"            ,	   0x1180080948d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4517"            ,	   0x1180080948d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4518"            ,	   0x1180080948d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4519"            ,	   0x1180080948d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4520"            ,	   0x1180080948d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4521"            ,	   0x1180080948d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4522"            ,	   0x1180080948d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4523"            ,	   0x1180080948d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4524"            ,	   0x1180080948d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4525"            ,	   0x1180080948d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4526"            ,	   0x1180080948d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4527"            ,	   0x1180080948d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4528"            ,	   0x1180080948d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4529"            ,	   0x1180080948d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4530"            ,	   0x1180080948d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4531"            ,	   0x1180080948d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4532"            ,	   0x1180080948da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4533"            ,	   0x1180080948da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4534"            ,	   0x1180080948db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4535"            ,	   0x1180080948db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4536"            ,	   0x1180080948dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4537"            ,	   0x1180080948dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4538"            ,	   0x1180080948dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4539"            ,	   0x1180080948dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4540"            ,	   0x1180080948de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4541"            ,	   0x1180080948de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4542"            ,	   0x1180080948df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4543"            ,	   0x1180080948df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4544"            ,	   0x1180080948e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4545"            ,	   0x1180080948e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4546"            ,	   0x1180080948e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4547"            ,	   0x1180080948e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4548"            ,	   0x1180080948e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4549"            ,	   0x1180080948e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4550"            ,	   0x1180080948e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4551"            ,	   0x1180080948e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4552"            ,	   0x1180080948e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4553"            ,	   0x1180080948e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4554"            ,	   0x1180080948e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4555"            ,	   0x1180080948e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4556"            ,	   0x1180080948e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4557"            ,	   0x1180080948e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4558"            ,	   0x1180080948e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4559"            ,	   0x1180080948e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4560"            ,	   0x1180080948e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4561"            ,	   0x1180080948e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4562"            ,	   0x1180080948e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4563"            ,	   0x1180080948e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4564"            ,	   0x1180080948ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4565"            ,	   0x1180080948ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4566"            ,	   0x1180080948eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4567"            ,	   0x1180080948eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4568"            ,	   0x1180080948ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4569"            ,	   0x1180080948ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4570"            ,	   0x1180080948ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4571"            ,	   0x1180080948ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4572"            ,	   0x1180080948ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4573"            ,	   0x1180080948ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4574"            ,	   0x1180080948ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4575"            ,	   0x1180080948ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4576"            ,	   0x1180080948f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4577"            ,	   0x1180080948f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4578"            ,	   0x1180080948f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4579"            ,	   0x1180080948f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4580"            ,	   0x1180080948f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4581"            ,	   0x1180080948f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4582"            ,	   0x1180080948f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4583"            ,	   0x1180080948f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4584"            ,	   0x1180080948f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4585"            ,	   0x1180080948f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4586"            ,	   0x1180080948f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4587"            ,	   0x1180080948f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4588"            ,	   0x1180080948f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4589"            ,	   0x1180080948f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4590"            ,	   0x1180080948f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4591"            ,	   0x1180080948f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4592"            ,	   0x1180080948f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4593"            ,	   0x1180080948f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4594"            ,	   0x1180080948f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4595"            ,	   0x1180080948f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4596"            ,	   0x1180080948fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4597"            ,	   0x1180080948fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4598"            ,	   0x1180080948fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4599"            ,	   0x1180080948fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4600"            ,	   0x1180080948fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4601"            ,	   0x1180080948fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4602"            ,	   0x1180080948fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4603"            ,	   0x1180080948fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4604"            ,	   0x1180080948fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4605"            ,	   0x1180080948fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4606"            ,	   0x1180080948ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4607"            ,	   0x1180080948ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4608"            ,	   0x1180080949000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4609"            ,	   0x1180080949008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4610"            ,	   0x1180080949010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4611"            ,	   0x1180080949018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4612"            ,	   0x1180080949020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4613"            ,	   0x1180080949028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4614"            ,	   0x1180080949030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4615"            ,	   0x1180080949038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4616"            ,	   0x1180080949040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4617"            ,	   0x1180080949048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4618"            ,	   0x1180080949050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4619"            ,	   0x1180080949058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4620"            ,	   0x1180080949060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4621"            ,	   0x1180080949068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4622"            ,	   0x1180080949070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4623"            ,	   0x1180080949078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4624"            ,	   0x1180080949080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4625"            ,	   0x1180080949088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4626"            ,	   0x1180080949090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4627"            ,	   0x1180080949098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4628"            ,	   0x11800809490a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4629"            ,	   0x11800809490a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4630"            ,	   0x11800809490b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4631"            ,	   0x11800809490b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4632"            ,	   0x11800809490c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4633"            ,	   0x11800809490c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4634"            ,	   0x11800809490d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4635"            ,	   0x11800809490d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4636"            ,	   0x11800809490e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4637"            ,	   0x11800809490e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4638"            ,	   0x11800809490f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4639"            ,	   0x11800809490f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4640"            ,	   0x1180080949100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4641"            ,	   0x1180080949108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4642"            ,	   0x1180080949110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4643"            ,	   0x1180080949118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4644"            ,	   0x1180080949120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4645"            ,	   0x1180080949128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4646"            ,	   0x1180080949130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4647"            ,	   0x1180080949138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4648"            ,	   0x1180080949140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4649"            ,	   0x1180080949148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4650"            ,	   0x1180080949150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4651"            ,	   0x1180080949158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4652"            ,	   0x1180080949160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4653"            ,	   0x1180080949168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4654"            ,	   0x1180080949170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4655"            ,	   0x1180080949178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4656"            ,	   0x1180080949180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4657"            ,	   0x1180080949188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4658"            ,	   0x1180080949190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4659"            ,	   0x1180080949198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4660"            ,	   0x11800809491a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4661"            ,	   0x11800809491a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4662"            ,	   0x11800809491b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4663"            ,	   0x11800809491b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4664"            ,	   0x11800809491c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4665"            ,	   0x11800809491c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4666"            ,	   0x11800809491d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4667"            ,	   0x11800809491d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4668"            ,	   0x11800809491e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4669"            ,	   0x11800809491e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4670"            ,	   0x11800809491f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4671"            ,	   0x11800809491f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4672"            ,	   0x1180080949200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4673"            ,	   0x1180080949208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4674"            ,	   0x1180080949210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4675"            ,	   0x1180080949218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4676"            ,	   0x1180080949220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4677"            ,	   0x1180080949228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4678"            ,	   0x1180080949230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4679"            ,	   0x1180080949238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4680"            ,	   0x1180080949240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4681"            ,	   0x1180080949248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4682"            ,	   0x1180080949250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4683"            ,	   0x1180080949258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4684"            ,	   0x1180080949260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4685"            ,	   0x1180080949268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4686"            ,	   0x1180080949270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4687"            ,	   0x1180080949278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4688"            ,	   0x1180080949280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4689"            ,	   0x1180080949288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4690"            ,	   0x1180080949290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4691"            ,	   0x1180080949298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4692"            ,	   0x11800809492a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4693"            ,	   0x11800809492a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4694"            ,	   0x11800809492b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4695"            ,	   0x11800809492b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4696"            ,	   0x11800809492c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4697"            ,	   0x11800809492c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4698"            ,	   0x11800809492d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4699"            ,	   0x11800809492d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4700"            ,	   0x11800809492e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4701"            ,	   0x11800809492e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4702"            ,	   0x11800809492f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4703"            ,	   0x11800809492f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4704"            ,	   0x1180080949300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4705"            ,	   0x1180080949308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4706"            ,	   0x1180080949310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4707"            ,	   0x1180080949318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4708"            ,	   0x1180080949320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4709"            ,	   0x1180080949328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4710"            ,	   0x1180080949330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4711"            ,	   0x1180080949338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4712"            ,	   0x1180080949340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4713"            ,	   0x1180080949348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4714"            ,	   0x1180080949350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4715"            ,	   0x1180080949358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4716"            ,	   0x1180080949360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4717"            ,	   0x1180080949368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4718"            ,	   0x1180080949370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4719"            ,	   0x1180080949378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4720"            ,	   0x1180080949380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4721"            ,	   0x1180080949388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4722"            ,	   0x1180080949390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4723"            ,	   0x1180080949398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4724"            ,	   0x11800809493a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4725"            ,	   0x11800809493a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4726"            ,	   0x11800809493b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4727"            ,	   0x11800809493b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4728"            ,	   0x11800809493c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4729"            ,	   0x11800809493c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4730"            ,	   0x11800809493d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4731"            ,	   0x11800809493d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4732"            ,	   0x11800809493e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4733"            ,	   0x11800809493e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4734"            ,	   0x11800809493f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4735"            ,	   0x11800809493f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4736"            ,	   0x1180080949400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4737"            ,	   0x1180080949408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4738"            ,	   0x1180080949410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4739"            ,	   0x1180080949418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4740"            ,	   0x1180080949420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4741"            ,	   0x1180080949428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4742"            ,	   0x1180080949430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4743"            ,	   0x1180080949438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4744"            ,	   0x1180080949440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4745"            ,	   0x1180080949448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4746"            ,	   0x1180080949450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4747"            ,	   0x1180080949458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4748"            ,	   0x1180080949460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4749"            ,	   0x1180080949468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4750"            ,	   0x1180080949470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4751"            ,	   0x1180080949478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4752"            ,	   0x1180080949480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4753"            ,	   0x1180080949488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4754"            ,	   0x1180080949490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4755"            ,	   0x1180080949498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4756"            ,	   0x11800809494a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4757"            ,	   0x11800809494a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4758"            ,	   0x11800809494b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4759"            ,	   0x11800809494b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4760"            ,	   0x11800809494c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4761"            ,	   0x11800809494c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4762"            ,	   0x11800809494d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4763"            ,	   0x11800809494d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4764"            ,	   0x11800809494e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4765"            ,	   0x11800809494e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4766"            ,	   0x11800809494f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4767"            ,	   0x11800809494f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4768"            ,	   0x1180080949500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4769"            ,	   0x1180080949508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4770"            ,	   0x1180080949510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4771"            ,	   0x1180080949518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4772"            ,	   0x1180080949520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4773"            ,	   0x1180080949528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4774"            ,	   0x1180080949530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4775"            ,	   0x1180080949538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4776"            ,	   0x1180080949540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4777"            ,	   0x1180080949548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4778"            ,	   0x1180080949550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4779"            ,	   0x1180080949558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4780"            ,	   0x1180080949560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4781"            ,	   0x1180080949568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4782"            ,	   0x1180080949570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4783"            ,	   0x1180080949578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4784"            ,	   0x1180080949580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4785"            ,	   0x1180080949588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4786"            ,	   0x1180080949590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4787"            ,	   0x1180080949598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4788"            ,	   0x11800809495a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4789"            ,	   0x11800809495a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4790"            ,	   0x11800809495b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4791"            ,	   0x11800809495b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4792"            ,	   0x11800809495c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4793"            ,	   0x11800809495c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4794"            ,	   0x11800809495d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4795"            ,	   0x11800809495d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4796"            ,	   0x11800809495e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4797"            ,	   0x11800809495e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4798"            ,	   0x11800809495f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4799"            ,	   0x11800809495f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4800"            ,	   0x1180080949600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4801"            ,	   0x1180080949608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4802"            ,	   0x1180080949610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4803"            ,	   0x1180080949618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4804"            ,	   0x1180080949620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4805"            ,	   0x1180080949628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4806"            ,	   0x1180080949630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4807"            ,	   0x1180080949638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4808"            ,	   0x1180080949640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4809"            ,	   0x1180080949648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4810"            ,	   0x1180080949650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4811"            ,	   0x1180080949658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4812"            ,	   0x1180080949660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4813"            ,	   0x1180080949668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4814"            ,	   0x1180080949670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4815"            ,	   0x1180080949678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4816"            ,	   0x1180080949680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4817"            ,	   0x1180080949688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4818"            ,	   0x1180080949690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4819"            ,	   0x1180080949698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4820"            ,	   0x11800809496a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4821"            ,	   0x11800809496a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4822"            ,	   0x11800809496b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4823"            ,	   0x11800809496b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4824"            ,	   0x11800809496c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4825"            ,	   0x11800809496c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4826"            ,	   0x11800809496d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4827"            ,	   0x11800809496d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4828"            ,	   0x11800809496e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4829"            ,	   0x11800809496e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4830"            ,	   0x11800809496f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4831"            ,	   0x11800809496f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4832"            ,	   0x1180080949700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4833"            ,	   0x1180080949708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4834"            ,	   0x1180080949710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4835"            ,	   0x1180080949718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4836"            ,	   0x1180080949720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4837"            ,	   0x1180080949728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4838"            ,	   0x1180080949730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4839"            ,	   0x1180080949738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4840"            ,	   0x1180080949740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4841"            ,	   0x1180080949748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4842"            ,	   0x1180080949750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4843"            ,	   0x1180080949758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4844"            ,	   0x1180080949760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4845"            ,	   0x1180080949768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4846"            ,	   0x1180080949770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4847"            ,	   0x1180080949778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4848"            ,	   0x1180080949780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4849"            ,	   0x1180080949788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4850"            ,	   0x1180080949790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4851"            ,	   0x1180080949798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4852"            ,	   0x11800809497a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4853"            ,	   0x11800809497a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4854"            ,	   0x11800809497b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4855"            ,	   0x11800809497b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4856"            ,	   0x11800809497c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4857"            ,	   0x11800809497c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4858"            ,	   0x11800809497d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4859"            ,	   0x11800809497d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4860"            ,	   0x11800809497e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4861"            ,	   0x11800809497e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4862"            ,	   0x11800809497f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4863"            ,	   0x11800809497f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4864"            ,	   0x1180080949800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4865"            ,	   0x1180080949808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4866"            ,	   0x1180080949810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4867"            ,	   0x1180080949818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4868"            ,	   0x1180080949820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4869"            ,	   0x1180080949828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4870"            ,	   0x1180080949830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4871"            ,	   0x1180080949838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4872"            ,	   0x1180080949840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4873"            ,	   0x1180080949848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4874"            ,	   0x1180080949850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4875"            ,	   0x1180080949858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4876"            ,	   0x1180080949860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4877"            ,	   0x1180080949868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4878"            ,	   0x1180080949870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4879"            ,	   0x1180080949878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4880"            ,	   0x1180080949880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4881"            ,	   0x1180080949888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4882"            ,	   0x1180080949890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4883"            ,	   0x1180080949898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4884"            ,	   0x11800809498a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4885"            ,	   0x11800809498a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4886"            ,	   0x11800809498b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4887"            ,	   0x11800809498b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4888"            ,	   0x11800809498c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4889"            ,	   0x11800809498c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4890"            ,	   0x11800809498d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4891"            ,	   0x11800809498d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4892"            ,	   0x11800809498e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4893"            ,	   0x11800809498e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4894"            ,	   0x11800809498f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4895"            ,	   0x11800809498f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4896"            ,	   0x1180080949900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4897"            ,	   0x1180080949908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4898"            ,	   0x1180080949910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4899"            ,	   0x1180080949918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4900"            ,	   0x1180080949920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4901"            ,	   0x1180080949928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4902"            ,	   0x1180080949930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4903"            ,	   0x1180080949938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4904"            ,	   0x1180080949940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4905"            ,	   0x1180080949948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4906"            ,	   0x1180080949950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4907"            ,	   0x1180080949958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4908"            ,	   0x1180080949960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4909"            ,	   0x1180080949968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4910"            ,	   0x1180080949970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4911"            ,	   0x1180080949978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4912"            ,	   0x1180080949980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4913"            ,	   0x1180080949988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4914"            ,	   0x1180080949990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4915"            ,	   0x1180080949998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4916"            ,	   0x11800809499a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4917"            ,	   0x11800809499a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4918"            ,	   0x11800809499b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4919"            ,	   0x11800809499b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4920"            ,	   0x11800809499c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4921"            ,	   0x11800809499c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4922"            ,	   0x11800809499d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4923"            ,	   0x11800809499d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4924"            ,	   0x11800809499e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4925"            ,	   0x11800809499e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4926"            ,	   0x11800809499f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4927"            ,	   0x11800809499f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4928"            ,	   0x1180080949a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4929"            ,	   0x1180080949a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4930"            ,	   0x1180080949a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4931"            ,	   0x1180080949a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4932"            ,	   0x1180080949a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4933"            ,	   0x1180080949a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4934"            ,	   0x1180080949a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4935"            ,	   0x1180080949a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4936"            ,	   0x1180080949a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4937"            ,	   0x1180080949a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4938"            ,	   0x1180080949a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4939"            ,	   0x1180080949a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4940"            ,	   0x1180080949a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4941"            ,	   0x1180080949a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4942"            ,	   0x1180080949a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4943"            ,	   0x1180080949a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4944"            ,	   0x1180080949a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4945"            ,	   0x1180080949a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4946"            ,	   0x1180080949a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4947"            ,	   0x1180080949a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4948"            ,	   0x1180080949aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4949"            ,	   0x1180080949aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4950"            ,	   0x1180080949ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4951"            ,	   0x1180080949ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4952"            ,	   0x1180080949ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4953"            ,	   0x1180080949ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4954"            ,	   0x1180080949ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4955"            ,	   0x1180080949ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4956"            ,	   0x1180080949ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4957"            ,	   0x1180080949ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4958"            ,	   0x1180080949af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4959"            ,	   0x1180080949af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4960"            ,	   0x1180080949b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4961"            ,	   0x1180080949b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4962"            ,	   0x1180080949b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4963"            ,	   0x1180080949b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4964"            ,	   0x1180080949b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4965"            ,	   0x1180080949b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4966"            ,	   0x1180080949b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4967"            ,	   0x1180080949b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4968"            ,	   0x1180080949b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4969"            ,	   0x1180080949b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4970"            ,	   0x1180080949b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4971"            ,	   0x1180080949b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4972"            ,	   0x1180080949b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4973"            ,	   0x1180080949b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4974"            ,	   0x1180080949b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4975"            ,	   0x1180080949b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4976"            ,	   0x1180080949b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4977"            ,	   0x1180080949b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4978"            ,	   0x1180080949b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4979"            ,	   0x1180080949b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4980"            ,	   0x1180080949ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4981"            ,	   0x1180080949ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4982"            ,	   0x1180080949bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4983"            ,	   0x1180080949bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4984"            ,	   0x1180080949bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4985"            ,	   0x1180080949bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4986"            ,	   0x1180080949bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4987"            ,	   0x1180080949bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4988"            ,	   0x1180080949be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4989"            ,	   0x1180080949be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4990"            ,	   0x1180080949bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4991"            ,	   0x1180080949bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4992"            ,	   0x1180080949c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4993"            ,	   0x1180080949c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4994"            ,	   0x1180080949c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4995"            ,	   0x1180080949c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4996"            ,	   0x1180080949c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4997"            ,	   0x1180080949c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4998"            ,	   0x1180080949c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP4999"            ,	   0x1180080949c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5000"            ,	   0x1180080949c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5001"            ,	   0x1180080949c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5002"            ,	   0x1180080949c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5003"            ,	   0x1180080949c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5004"            ,	   0x1180080949c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5005"            ,	   0x1180080949c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5006"            ,	   0x1180080949c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5007"            ,	   0x1180080949c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5008"            ,	   0x1180080949c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5009"            ,	   0x1180080949c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5010"            ,	   0x1180080949c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5011"            ,	   0x1180080949c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5012"            ,	   0x1180080949ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5013"            ,	   0x1180080949ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5014"            ,	   0x1180080949cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5015"            ,	   0x1180080949cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5016"            ,	   0x1180080949cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5017"            ,	   0x1180080949cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5018"            ,	   0x1180080949cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5019"            ,	   0x1180080949cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5020"            ,	   0x1180080949ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5021"            ,	   0x1180080949ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5022"            ,	   0x1180080949cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5023"            ,	   0x1180080949cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5024"            ,	   0x1180080949d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5025"            ,	   0x1180080949d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5026"            ,	   0x1180080949d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5027"            ,	   0x1180080949d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5028"            ,	   0x1180080949d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5029"            ,	   0x1180080949d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5030"            ,	   0x1180080949d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5031"            ,	   0x1180080949d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5032"            ,	   0x1180080949d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5033"            ,	   0x1180080949d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5034"            ,	   0x1180080949d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5035"            ,	   0x1180080949d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5036"            ,	   0x1180080949d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5037"            ,	   0x1180080949d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5038"            ,	   0x1180080949d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5039"            ,	   0x1180080949d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5040"            ,	   0x1180080949d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5041"            ,	   0x1180080949d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5042"            ,	   0x1180080949d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5043"            ,	   0x1180080949d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5044"            ,	   0x1180080949da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5045"            ,	   0x1180080949da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5046"            ,	   0x1180080949db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5047"            ,	   0x1180080949db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5048"            ,	   0x1180080949dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5049"            ,	   0x1180080949dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5050"            ,	   0x1180080949dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5051"            ,	   0x1180080949dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5052"            ,	   0x1180080949de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5053"            ,	   0x1180080949de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5054"            ,	   0x1180080949df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5055"            ,	   0x1180080949df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5056"            ,	   0x1180080949e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5057"            ,	   0x1180080949e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5058"            ,	   0x1180080949e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5059"            ,	   0x1180080949e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5060"            ,	   0x1180080949e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5061"            ,	   0x1180080949e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5062"            ,	   0x1180080949e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5063"            ,	   0x1180080949e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5064"            ,	   0x1180080949e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5065"            ,	   0x1180080949e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5066"            ,	   0x1180080949e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5067"            ,	   0x1180080949e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5068"            ,	   0x1180080949e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5069"            ,	   0x1180080949e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5070"            ,	   0x1180080949e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5071"            ,	   0x1180080949e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5072"            ,	   0x1180080949e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5073"            ,	   0x1180080949e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5074"            ,	   0x1180080949e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5075"            ,	   0x1180080949e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5076"            ,	   0x1180080949ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5077"            ,	   0x1180080949ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5078"            ,	   0x1180080949eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5079"            ,	   0x1180080949eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5080"            ,	   0x1180080949ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5081"            ,	   0x1180080949ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5082"            ,	   0x1180080949ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5083"            ,	   0x1180080949ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5084"            ,	   0x1180080949ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5085"            ,	   0x1180080949ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5086"            ,	   0x1180080949ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5087"            ,	   0x1180080949ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5088"            ,	   0x1180080949f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5089"            ,	   0x1180080949f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5090"            ,	   0x1180080949f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5091"            ,	   0x1180080949f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5092"            ,	   0x1180080949f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5093"            ,	   0x1180080949f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5094"            ,	   0x1180080949f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5095"            ,	   0x1180080949f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5096"            ,	   0x1180080949f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5097"            ,	   0x1180080949f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5098"            ,	   0x1180080949f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5099"            ,	   0x1180080949f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5100"            ,	   0x1180080949f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5101"            ,	   0x1180080949f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5102"            ,	   0x1180080949f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5103"            ,	   0x1180080949f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5104"            ,	   0x1180080949f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5105"            ,	   0x1180080949f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5106"            ,	   0x1180080949f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5107"            ,	   0x1180080949f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5108"            ,	   0x1180080949fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5109"            ,	   0x1180080949fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5110"            ,	   0x1180080949fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5111"            ,	   0x1180080949fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5112"            ,	   0x1180080949fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5113"            ,	   0x1180080949fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5114"            ,	   0x1180080949fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5115"            ,	   0x1180080949fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5116"            ,	   0x1180080949fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5117"            ,	   0x1180080949fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5118"            ,	   0x1180080949ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5119"            ,	   0x1180080949ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5120"            ,	   0x118008094a000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5121"            ,	   0x118008094a008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5122"            ,	   0x118008094a010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5123"            ,	   0x118008094a018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5124"            ,	   0x118008094a020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5125"            ,	   0x118008094a028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5126"            ,	   0x118008094a030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5127"            ,	   0x118008094a038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5128"            ,	   0x118008094a040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5129"            ,	   0x118008094a048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5130"            ,	   0x118008094a050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5131"            ,	   0x118008094a058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5132"            ,	   0x118008094a060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5133"            ,	   0x118008094a068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5134"            ,	   0x118008094a070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5135"            ,	   0x118008094a078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5136"            ,	   0x118008094a080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5137"            ,	   0x118008094a088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5138"            ,	   0x118008094a090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5139"            ,	   0x118008094a098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5140"            ,	   0x118008094a0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5141"            ,	   0x118008094a0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5142"            ,	   0x118008094a0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5143"            ,	   0x118008094a0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5144"            ,	   0x118008094a0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5145"            ,	   0x118008094a0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5146"            ,	   0x118008094a0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5147"            ,	   0x118008094a0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5148"            ,	   0x118008094a0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5149"            ,	   0x118008094a0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5150"            ,	   0x118008094a0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5151"            ,	   0x118008094a0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5152"            ,	   0x118008094a100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5153"            ,	   0x118008094a108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5154"            ,	   0x118008094a110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5155"            ,	   0x118008094a118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5156"            ,	   0x118008094a120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5157"            ,	   0x118008094a128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5158"            ,	   0x118008094a130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5159"            ,	   0x118008094a138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5160"            ,	   0x118008094a140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5161"            ,	   0x118008094a148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5162"            ,	   0x118008094a150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5163"            ,	   0x118008094a158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5164"            ,	   0x118008094a160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5165"            ,	   0x118008094a168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5166"            ,	   0x118008094a170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5167"            ,	   0x118008094a178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5168"            ,	   0x118008094a180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5169"            ,	   0x118008094a188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5170"            ,	   0x118008094a190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5171"            ,	   0x118008094a198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5172"            ,	   0x118008094a1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5173"            ,	   0x118008094a1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5174"            ,	   0x118008094a1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5175"            ,	   0x118008094a1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5176"            ,	   0x118008094a1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5177"            ,	   0x118008094a1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5178"            ,	   0x118008094a1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5179"            ,	   0x118008094a1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5180"            ,	   0x118008094a1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5181"            ,	   0x118008094a1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5182"            ,	   0x118008094a1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5183"            ,	   0x118008094a1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5184"            ,	   0x118008094a200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5185"            ,	   0x118008094a208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5186"            ,	   0x118008094a210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5187"            ,	   0x118008094a218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5188"            ,	   0x118008094a220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5189"            ,	   0x118008094a228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5190"            ,	   0x118008094a230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5191"            ,	   0x118008094a238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5192"            ,	   0x118008094a240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5193"            ,	   0x118008094a248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5194"            ,	   0x118008094a250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5195"            ,	   0x118008094a258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5196"            ,	   0x118008094a260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5197"            ,	   0x118008094a268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5198"            ,	   0x118008094a270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5199"            ,	   0x118008094a278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5200"            ,	   0x118008094a280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5201"            ,	   0x118008094a288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5202"            ,	   0x118008094a290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5203"            ,	   0x118008094a298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5204"            ,	   0x118008094a2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5205"            ,	   0x118008094a2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5206"            ,	   0x118008094a2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5207"            ,	   0x118008094a2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5208"            ,	   0x118008094a2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5209"            ,	   0x118008094a2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5210"            ,	   0x118008094a2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5211"            ,	   0x118008094a2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5212"            ,	   0x118008094a2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5213"            ,	   0x118008094a2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5214"            ,	   0x118008094a2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5215"            ,	   0x118008094a2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5216"            ,	   0x118008094a300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5217"            ,	   0x118008094a308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5218"            ,	   0x118008094a310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5219"            ,	   0x118008094a318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5220"            ,	   0x118008094a320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5221"            ,	   0x118008094a328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5222"            ,	   0x118008094a330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5223"            ,	   0x118008094a338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5224"            ,	   0x118008094a340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5225"            ,	   0x118008094a348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5226"            ,	   0x118008094a350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5227"            ,	   0x118008094a358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5228"            ,	   0x118008094a360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5229"            ,	   0x118008094a368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5230"            ,	   0x118008094a370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5231"            ,	   0x118008094a378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5232"            ,	   0x118008094a380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5233"            ,	   0x118008094a388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5234"            ,	   0x118008094a390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5235"            ,	   0x118008094a398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5236"            ,	   0x118008094a3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5237"            ,	   0x118008094a3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5238"            ,	   0x118008094a3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5239"            ,	   0x118008094a3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5240"            ,	   0x118008094a3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5241"            ,	   0x118008094a3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5242"            ,	   0x118008094a3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5243"            ,	   0x118008094a3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5244"            ,	   0x118008094a3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5245"            ,	   0x118008094a3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5246"            ,	   0x118008094a3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5247"            ,	   0x118008094a3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5248"            ,	   0x118008094a400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5249"            ,	   0x118008094a408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5250"            ,	   0x118008094a410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5251"            ,	   0x118008094a418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5252"            ,	   0x118008094a420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5253"            ,	   0x118008094a428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5254"            ,	   0x118008094a430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5255"            ,	   0x118008094a438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5256"            ,	   0x118008094a440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5257"            ,	   0x118008094a448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5258"            ,	   0x118008094a450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5259"            ,	   0x118008094a458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5260"            ,	   0x118008094a460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5261"            ,	   0x118008094a468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5262"            ,	   0x118008094a470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5263"            ,	   0x118008094a478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5264"            ,	   0x118008094a480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5265"            ,	   0x118008094a488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5266"            ,	   0x118008094a490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5267"            ,	   0x118008094a498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5268"            ,	   0x118008094a4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5269"            ,	   0x118008094a4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5270"            ,	   0x118008094a4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5271"            ,	   0x118008094a4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5272"            ,	   0x118008094a4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5273"            ,	   0x118008094a4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5274"            ,	   0x118008094a4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5275"            ,	   0x118008094a4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5276"            ,	   0x118008094a4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5277"            ,	   0x118008094a4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5278"            ,	   0x118008094a4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5279"            ,	   0x118008094a4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5280"            ,	   0x118008094a500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5281"            ,	   0x118008094a508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5282"            ,	   0x118008094a510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5283"            ,	   0x118008094a518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5284"            ,	   0x118008094a520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5285"            ,	   0x118008094a528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5286"            ,	   0x118008094a530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5287"            ,	   0x118008094a538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5288"            ,	   0x118008094a540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5289"            ,	   0x118008094a548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5290"            ,	   0x118008094a550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5291"            ,	   0x118008094a558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5292"            ,	   0x118008094a560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5293"            ,	   0x118008094a568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5294"            ,	   0x118008094a570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5295"            ,	   0x118008094a578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5296"            ,	   0x118008094a580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5297"            ,	   0x118008094a588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5298"            ,	   0x118008094a590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5299"            ,	   0x118008094a598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5300"            ,	   0x118008094a5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5301"            ,	   0x118008094a5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5302"            ,	   0x118008094a5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5303"            ,	   0x118008094a5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5304"            ,	   0x118008094a5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5305"            ,	   0x118008094a5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5306"            ,	   0x118008094a5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5307"            ,	   0x118008094a5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5308"            ,	   0x118008094a5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5309"            ,	   0x118008094a5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5310"            ,	   0x118008094a5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5311"            ,	   0x118008094a5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5312"            ,	   0x118008094a600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5313"            ,	   0x118008094a608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5314"            ,	   0x118008094a610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5315"            ,	   0x118008094a618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5316"            ,	   0x118008094a620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5317"            ,	   0x118008094a628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5318"            ,	   0x118008094a630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5319"            ,	   0x118008094a638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5320"            ,	   0x118008094a640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5321"            ,	   0x118008094a648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5322"            ,	   0x118008094a650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5323"            ,	   0x118008094a658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5324"            ,	   0x118008094a660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5325"            ,	   0x118008094a668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5326"            ,	   0x118008094a670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5327"            ,	   0x118008094a678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5328"            ,	   0x118008094a680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5329"            ,	   0x118008094a688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5330"            ,	   0x118008094a690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5331"            ,	   0x118008094a698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5332"            ,	   0x118008094a6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5333"            ,	   0x118008094a6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5334"            ,	   0x118008094a6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5335"            ,	   0x118008094a6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5336"            ,	   0x118008094a6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5337"            ,	   0x118008094a6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5338"            ,	   0x118008094a6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5339"            ,	   0x118008094a6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5340"            ,	   0x118008094a6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5341"            ,	   0x118008094a6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5342"            ,	   0x118008094a6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5343"            ,	   0x118008094a6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5344"            ,	   0x118008094a700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5345"            ,	   0x118008094a708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5346"            ,	   0x118008094a710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5347"            ,	   0x118008094a718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5348"            ,	   0x118008094a720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5349"            ,	   0x118008094a728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5350"            ,	   0x118008094a730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5351"            ,	   0x118008094a738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5352"            ,	   0x118008094a740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5353"            ,	   0x118008094a748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5354"            ,	   0x118008094a750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5355"            ,	   0x118008094a758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5356"            ,	   0x118008094a760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5357"            ,	   0x118008094a768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5358"            ,	   0x118008094a770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5359"            ,	   0x118008094a778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5360"            ,	   0x118008094a780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5361"            ,	   0x118008094a788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5362"            ,	   0x118008094a790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5363"            ,	   0x118008094a798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5364"            ,	   0x118008094a7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5365"            ,	   0x118008094a7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5366"            ,	   0x118008094a7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5367"            ,	   0x118008094a7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5368"            ,	   0x118008094a7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5369"            ,	   0x118008094a7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5370"            ,	   0x118008094a7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5371"            ,	   0x118008094a7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5372"            ,	   0x118008094a7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5373"            ,	   0x118008094a7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5374"            ,	   0x118008094a7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5375"            ,	   0x118008094a7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5376"            ,	   0x118008094a800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5377"            ,	   0x118008094a808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5378"            ,	   0x118008094a810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5379"            ,	   0x118008094a818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5380"            ,	   0x118008094a820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5381"            ,	   0x118008094a828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5382"            ,	   0x118008094a830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5383"            ,	   0x118008094a838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5384"            ,	   0x118008094a840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5385"            ,	   0x118008094a848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5386"            ,	   0x118008094a850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5387"            ,	   0x118008094a858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5388"            ,	   0x118008094a860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5389"            ,	   0x118008094a868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5390"            ,	   0x118008094a870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5391"            ,	   0x118008094a878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5392"            ,	   0x118008094a880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5393"            ,	   0x118008094a888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5394"            ,	   0x118008094a890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5395"            ,	   0x118008094a898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5396"            ,	   0x118008094a8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5397"            ,	   0x118008094a8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5398"            ,	   0x118008094a8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5399"            ,	   0x118008094a8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5400"            ,	   0x118008094a8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5401"            ,	   0x118008094a8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5402"            ,	   0x118008094a8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5403"            ,	   0x118008094a8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5404"            ,	   0x118008094a8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5405"            ,	   0x118008094a8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5406"            ,	   0x118008094a8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5407"            ,	   0x118008094a8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5408"            ,	   0x118008094a900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5409"            ,	   0x118008094a908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5410"            ,	   0x118008094a910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5411"            ,	   0x118008094a918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5412"            ,	   0x118008094a920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5413"            ,	   0x118008094a928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5414"            ,	   0x118008094a930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5415"            ,	   0x118008094a938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5416"            ,	   0x118008094a940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5417"            ,	   0x118008094a948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5418"            ,	   0x118008094a950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5419"            ,	   0x118008094a958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5420"            ,	   0x118008094a960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5421"            ,	   0x118008094a968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5422"            ,	   0x118008094a970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5423"            ,	   0x118008094a978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5424"            ,	   0x118008094a980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5425"            ,	   0x118008094a988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5426"            ,	   0x118008094a990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5427"            ,	   0x118008094a998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5428"            ,	   0x118008094a9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5429"            ,	   0x118008094a9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5430"            ,	   0x118008094a9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5431"            ,	   0x118008094a9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5432"            ,	   0x118008094a9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5433"            ,	   0x118008094a9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5434"            ,	   0x118008094a9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5435"            ,	   0x118008094a9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5436"            ,	   0x118008094a9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5437"            ,	   0x118008094a9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5438"            ,	   0x118008094a9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5439"            ,	   0x118008094a9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5440"            ,	   0x118008094aa00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5441"            ,	   0x118008094aa08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5442"            ,	   0x118008094aa10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5443"            ,	   0x118008094aa18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5444"            ,	   0x118008094aa20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5445"            ,	   0x118008094aa28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5446"            ,	   0x118008094aa30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5447"            ,	   0x118008094aa38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5448"            ,	   0x118008094aa40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5449"            ,	   0x118008094aa48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5450"            ,	   0x118008094aa50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5451"            ,	   0x118008094aa58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5452"            ,	   0x118008094aa60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5453"            ,	   0x118008094aa68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5454"            ,	   0x118008094aa70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5455"            ,	   0x118008094aa78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5456"            ,	   0x118008094aa80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5457"            ,	   0x118008094aa88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5458"            ,	   0x118008094aa90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5459"            ,	   0x118008094aa98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5460"            ,	   0x118008094aaa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5461"            ,	   0x118008094aaa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5462"            ,	   0x118008094aab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5463"            ,	   0x118008094aab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5464"            ,	   0x118008094aac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5465"            ,	   0x118008094aac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5466"            ,	   0x118008094aad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5467"            ,	   0x118008094aad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5468"            ,	   0x118008094aae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5469"            ,	   0x118008094aae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5470"            ,	   0x118008094aaf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5471"            ,	   0x118008094aaf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5472"            ,	   0x118008094ab00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5473"            ,	   0x118008094ab08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5474"            ,	   0x118008094ab10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5475"            ,	   0x118008094ab18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5476"            ,	   0x118008094ab20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5477"            ,	   0x118008094ab28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5478"            ,	   0x118008094ab30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5479"            ,	   0x118008094ab38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5480"            ,	   0x118008094ab40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5481"            ,	   0x118008094ab48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5482"            ,	   0x118008094ab50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5483"            ,	   0x118008094ab58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5484"            ,	   0x118008094ab60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5485"            ,	   0x118008094ab68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5486"            ,	   0x118008094ab70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5487"            ,	   0x118008094ab78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5488"            ,	   0x118008094ab80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5489"            ,	   0x118008094ab88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5490"            ,	   0x118008094ab90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5491"            ,	   0x118008094ab98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5492"            ,	   0x118008094aba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5493"            ,	   0x118008094aba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5494"            ,	   0x118008094abb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5495"            ,	   0x118008094abb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5496"            ,	   0x118008094abc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5497"            ,	   0x118008094abc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5498"            ,	   0x118008094abd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5499"            ,	   0x118008094abd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5500"            ,	   0x118008094abe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5501"            ,	   0x118008094abe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5502"            ,	   0x118008094abf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5503"            ,	   0x118008094abf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5504"            ,	   0x118008094ac00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5505"            ,	   0x118008094ac08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5506"            ,	   0x118008094ac10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5507"            ,	   0x118008094ac18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5508"            ,	   0x118008094ac20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5509"            ,	   0x118008094ac28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5510"            ,	   0x118008094ac30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5511"            ,	   0x118008094ac38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5512"            ,	   0x118008094ac40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5513"            ,	   0x118008094ac48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5514"            ,	   0x118008094ac50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5515"            ,	   0x118008094ac58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5516"            ,	   0x118008094ac60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5517"            ,	   0x118008094ac68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5518"            ,	   0x118008094ac70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5519"            ,	   0x118008094ac78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5520"            ,	   0x118008094ac80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5521"            ,	   0x118008094ac88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5522"            ,	   0x118008094ac90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5523"            ,	   0x118008094ac98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5524"            ,	   0x118008094aca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5525"            ,	   0x118008094aca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5526"            ,	   0x118008094acb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5527"            ,	   0x118008094acb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5528"            ,	   0x118008094acc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5529"            ,	   0x118008094acc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5530"            ,	   0x118008094acd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5531"            ,	   0x118008094acd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5532"            ,	   0x118008094ace0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5533"            ,	   0x118008094ace8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5534"            ,	   0x118008094acf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5535"            ,	   0x118008094acf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5536"            ,	   0x118008094ad00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5537"            ,	   0x118008094ad08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5538"            ,	   0x118008094ad10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5539"            ,	   0x118008094ad18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5540"            ,	   0x118008094ad20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5541"            ,	   0x118008094ad28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5542"            ,	   0x118008094ad30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5543"            ,	   0x118008094ad38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5544"            ,	   0x118008094ad40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5545"            ,	   0x118008094ad48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5546"            ,	   0x118008094ad50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5547"            ,	   0x118008094ad58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5548"            ,	   0x118008094ad60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5549"            ,	   0x118008094ad68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5550"            ,	   0x118008094ad70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5551"            ,	   0x118008094ad78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5552"            ,	   0x118008094ad80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5553"            ,	   0x118008094ad88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5554"            ,	   0x118008094ad90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5555"            ,	   0x118008094ad98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5556"            ,	   0x118008094ada0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5557"            ,	   0x118008094ada8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5558"            ,	   0x118008094adb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5559"            ,	   0x118008094adb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5560"            ,	   0x118008094adc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5561"            ,	   0x118008094adc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5562"            ,	   0x118008094add0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5563"            ,	   0x118008094add8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5564"            ,	   0x118008094ade0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5565"            ,	   0x118008094ade8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5566"            ,	   0x118008094adf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5567"            ,	   0x118008094adf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5568"            ,	   0x118008094ae00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5569"            ,	   0x118008094ae08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5570"            ,	   0x118008094ae10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5571"            ,	   0x118008094ae18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5572"            ,	   0x118008094ae20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5573"            ,	   0x118008094ae28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5574"            ,	   0x118008094ae30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5575"            ,	   0x118008094ae38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5576"            ,	   0x118008094ae40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5577"            ,	   0x118008094ae48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5578"            ,	   0x118008094ae50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5579"            ,	   0x118008094ae58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5580"            ,	   0x118008094ae60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5581"            ,	   0x118008094ae68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5582"            ,	   0x118008094ae70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5583"            ,	   0x118008094ae78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5584"            ,	   0x118008094ae80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5585"            ,	   0x118008094ae88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5586"            ,	   0x118008094ae90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5587"            ,	   0x118008094ae98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5588"            ,	   0x118008094aea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5589"            ,	   0x118008094aea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5590"            ,	   0x118008094aeb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5591"            ,	   0x118008094aeb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5592"            ,	   0x118008094aec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5593"            ,	   0x118008094aec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5594"            ,	   0x118008094aed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5595"            ,	   0x118008094aed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5596"            ,	   0x118008094aee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5597"            ,	   0x118008094aee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5598"            ,	   0x118008094aef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5599"            ,	   0x118008094aef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5600"            ,	   0x118008094af00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5601"            ,	   0x118008094af08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5602"            ,	   0x118008094af10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5603"            ,	   0x118008094af18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5604"            ,	   0x118008094af20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5605"            ,	   0x118008094af28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5606"            ,	   0x118008094af30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5607"            ,	   0x118008094af38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5608"            ,	   0x118008094af40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5609"            ,	   0x118008094af48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5610"            ,	   0x118008094af50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5611"            ,	   0x118008094af58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5612"            ,	   0x118008094af60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5613"            ,	   0x118008094af68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5614"            ,	   0x118008094af70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5615"            ,	   0x118008094af78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5616"            ,	   0x118008094af80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5617"            ,	   0x118008094af88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5618"            ,	   0x118008094af90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5619"            ,	   0x118008094af98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5620"            ,	   0x118008094afa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5621"            ,	   0x118008094afa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5622"            ,	   0x118008094afb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5623"            ,	   0x118008094afb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5624"            ,	   0x118008094afc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5625"            ,	   0x118008094afc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5626"            ,	   0x118008094afd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5627"            ,	   0x118008094afd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5628"            ,	   0x118008094afe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5629"            ,	   0x118008094afe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5630"            ,	   0x118008094aff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5631"            ,	   0x118008094aff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5632"            ,	   0x118008094b000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5633"            ,	   0x118008094b008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5634"            ,	   0x118008094b010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5635"            ,	   0x118008094b018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5636"            ,	   0x118008094b020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5637"            ,	   0x118008094b028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5638"            ,	   0x118008094b030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5639"            ,	   0x118008094b038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5640"            ,	   0x118008094b040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5641"            ,	   0x118008094b048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5642"            ,	   0x118008094b050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5643"            ,	   0x118008094b058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5644"            ,	   0x118008094b060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5645"            ,	   0x118008094b068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5646"            ,	   0x118008094b070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5647"            ,	   0x118008094b078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5648"            ,	   0x118008094b080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5649"            ,	   0x118008094b088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5650"            ,	   0x118008094b090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5651"            ,	   0x118008094b098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5652"            ,	   0x118008094b0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5653"            ,	   0x118008094b0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5654"            ,	   0x118008094b0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5655"            ,	   0x118008094b0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5656"            ,	   0x118008094b0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5657"            ,	   0x118008094b0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5658"            ,	   0x118008094b0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5659"            ,	   0x118008094b0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5660"            ,	   0x118008094b0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5661"            ,	   0x118008094b0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5662"            ,	   0x118008094b0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5663"            ,	   0x118008094b0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5664"            ,	   0x118008094b100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5665"            ,	   0x118008094b108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5666"            ,	   0x118008094b110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5667"            ,	   0x118008094b118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5668"            ,	   0x118008094b120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5669"            ,	   0x118008094b128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5670"            ,	   0x118008094b130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5671"            ,	   0x118008094b138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5672"            ,	   0x118008094b140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5673"            ,	   0x118008094b148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5674"            ,	   0x118008094b150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5675"            ,	   0x118008094b158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5676"            ,	   0x118008094b160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5677"            ,	   0x118008094b168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5678"            ,	   0x118008094b170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5679"            ,	   0x118008094b178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5680"            ,	   0x118008094b180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5681"            ,	   0x118008094b188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5682"            ,	   0x118008094b190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5683"            ,	   0x118008094b198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5684"            ,	   0x118008094b1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5685"            ,	   0x118008094b1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5686"            ,	   0x118008094b1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5687"            ,	   0x118008094b1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5688"            ,	   0x118008094b1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5689"            ,	   0x118008094b1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5690"            ,	   0x118008094b1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5691"            ,	   0x118008094b1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5692"            ,	   0x118008094b1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5693"            ,	   0x118008094b1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5694"            ,	   0x118008094b1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5695"            ,	   0x118008094b1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5696"            ,	   0x118008094b200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5697"            ,	   0x118008094b208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5698"            ,	   0x118008094b210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5699"            ,	   0x118008094b218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5700"            ,	   0x118008094b220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5701"            ,	   0x118008094b228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5702"            ,	   0x118008094b230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5703"            ,	   0x118008094b238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5704"            ,	   0x118008094b240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5705"            ,	   0x118008094b248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5706"            ,	   0x118008094b250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5707"            ,	   0x118008094b258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5708"            ,	   0x118008094b260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5709"            ,	   0x118008094b268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5710"            ,	   0x118008094b270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5711"            ,	   0x118008094b278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5712"            ,	   0x118008094b280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5713"            ,	   0x118008094b288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5714"            ,	   0x118008094b290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5715"            ,	   0x118008094b298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5716"            ,	   0x118008094b2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5717"            ,	   0x118008094b2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5718"            ,	   0x118008094b2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5719"            ,	   0x118008094b2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5720"            ,	   0x118008094b2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5721"            ,	   0x118008094b2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5722"            ,	   0x118008094b2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5723"            ,	   0x118008094b2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5724"            ,	   0x118008094b2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5725"            ,	   0x118008094b2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5726"            ,	   0x118008094b2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5727"            ,	   0x118008094b2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5728"            ,	   0x118008094b300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5729"            ,	   0x118008094b308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5730"            ,	   0x118008094b310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5731"            ,	   0x118008094b318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5732"            ,	   0x118008094b320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5733"            ,	   0x118008094b328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5734"            ,	   0x118008094b330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5735"            ,	   0x118008094b338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5736"            ,	   0x118008094b340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5737"            ,	   0x118008094b348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5738"            ,	   0x118008094b350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5739"            ,	   0x118008094b358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5740"            ,	   0x118008094b360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5741"            ,	   0x118008094b368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5742"            ,	   0x118008094b370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5743"            ,	   0x118008094b378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5744"            ,	   0x118008094b380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5745"            ,	   0x118008094b388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5746"            ,	   0x118008094b390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5747"            ,	   0x118008094b398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5748"            ,	   0x118008094b3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5749"            ,	   0x118008094b3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5750"            ,	   0x118008094b3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5751"            ,	   0x118008094b3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5752"            ,	   0x118008094b3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5753"            ,	   0x118008094b3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5754"            ,	   0x118008094b3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5755"            ,	   0x118008094b3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5756"            ,	   0x118008094b3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5757"            ,	   0x118008094b3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5758"            ,	   0x118008094b3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5759"            ,	   0x118008094b3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5760"            ,	   0x118008094b400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5761"            ,	   0x118008094b408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5762"            ,	   0x118008094b410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5763"            ,	   0x118008094b418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5764"            ,	   0x118008094b420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5765"            ,	   0x118008094b428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5766"            ,	   0x118008094b430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5767"            ,	   0x118008094b438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5768"            ,	   0x118008094b440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5769"            ,	   0x118008094b448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5770"            ,	   0x118008094b450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5771"            ,	   0x118008094b458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5772"            ,	   0x118008094b460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5773"            ,	   0x118008094b468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5774"            ,	   0x118008094b470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5775"            ,	   0x118008094b478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5776"            ,	   0x118008094b480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5777"            ,	   0x118008094b488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5778"            ,	   0x118008094b490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5779"            ,	   0x118008094b498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5780"            ,	   0x118008094b4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5781"            ,	   0x118008094b4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5782"            ,	   0x118008094b4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5783"            ,	   0x118008094b4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5784"            ,	   0x118008094b4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5785"            ,	   0x118008094b4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5786"            ,	   0x118008094b4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5787"            ,	   0x118008094b4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5788"            ,	   0x118008094b4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5789"            ,	   0x118008094b4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5790"            ,	   0x118008094b4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5791"            ,	   0x118008094b4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5792"            ,	   0x118008094b500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5793"            ,	   0x118008094b508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5794"            ,	   0x118008094b510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5795"            ,	   0x118008094b518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5796"            ,	   0x118008094b520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5797"            ,	   0x118008094b528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5798"            ,	   0x118008094b530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5799"            ,	   0x118008094b538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5800"            ,	   0x118008094b540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5801"            ,	   0x118008094b548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5802"            ,	   0x118008094b550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5803"            ,	   0x118008094b558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5804"            ,	   0x118008094b560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5805"            ,	   0x118008094b568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5806"            ,	   0x118008094b570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5807"            ,	   0x118008094b578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5808"            ,	   0x118008094b580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5809"            ,	   0x118008094b588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5810"            ,	   0x118008094b590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5811"            ,	   0x118008094b598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5812"            ,	   0x118008094b5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5813"            ,	   0x118008094b5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5814"            ,	   0x118008094b5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5815"            ,	   0x118008094b5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5816"            ,	   0x118008094b5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5817"            ,	   0x118008094b5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5818"            ,	   0x118008094b5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5819"            ,	   0x118008094b5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5820"            ,	   0x118008094b5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5821"            ,	   0x118008094b5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5822"            ,	   0x118008094b5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5823"            ,	   0x118008094b5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5824"            ,	   0x118008094b600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5825"            ,	   0x118008094b608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5826"            ,	   0x118008094b610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5827"            ,	   0x118008094b618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5828"            ,	   0x118008094b620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5829"            ,	   0x118008094b628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5830"            ,	   0x118008094b630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5831"            ,	   0x118008094b638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5832"            ,	   0x118008094b640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5833"            ,	   0x118008094b648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5834"            ,	   0x118008094b650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5835"            ,	   0x118008094b658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5836"            ,	   0x118008094b660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5837"            ,	   0x118008094b668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5838"            ,	   0x118008094b670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5839"            ,	   0x118008094b678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5840"            ,	   0x118008094b680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5841"            ,	   0x118008094b688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5842"            ,	   0x118008094b690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5843"            ,	   0x118008094b698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5844"            ,	   0x118008094b6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5845"            ,	   0x118008094b6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5846"            ,	   0x118008094b6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5847"            ,	   0x118008094b6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5848"            ,	   0x118008094b6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5849"            ,	   0x118008094b6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5850"            ,	   0x118008094b6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5851"            ,	   0x118008094b6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5852"            ,	   0x118008094b6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5853"            ,	   0x118008094b6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5854"            ,	   0x118008094b6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5855"            ,	   0x118008094b6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5856"            ,	   0x118008094b700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5857"            ,	   0x118008094b708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5858"            ,	   0x118008094b710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5859"            ,	   0x118008094b718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5860"            ,	   0x118008094b720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5861"            ,	   0x118008094b728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5862"            ,	   0x118008094b730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5863"            ,	   0x118008094b738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5864"            ,	   0x118008094b740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5865"            ,	   0x118008094b748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5866"            ,	   0x118008094b750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5867"            ,	   0x118008094b758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5868"            ,	   0x118008094b760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5869"            ,	   0x118008094b768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5870"            ,	   0x118008094b770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5871"            ,	   0x118008094b778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5872"            ,	   0x118008094b780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5873"            ,	   0x118008094b788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5874"            ,	   0x118008094b790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5875"            ,	   0x118008094b798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5876"            ,	   0x118008094b7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5877"            ,	   0x118008094b7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5878"            ,	   0x118008094b7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5879"            ,	   0x118008094b7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5880"            ,	   0x118008094b7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5881"            ,	   0x118008094b7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5882"            ,	   0x118008094b7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5883"            ,	   0x118008094b7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5884"            ,	   0x118008094b7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5885"            ,	   0x118008094b7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5886"            ,	   0x118008094b7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5887"            ,	   0x118008094b7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5888"            ,	   0x118008094b800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5889"            ,	   0x118008094b808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5890"            ,	   0x118008094b810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5891"            ,	   0x118008094b818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5892"            ,	   0x118008094b820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5893"            ,	   0x118008094b828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5894"            ,	   0x118008094b830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5895"            ,	   0x118008094b838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5896"            ,	   0x118008094b840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5897"            ,	   0x118008094b848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5898"            ,	   0x118008094b850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5899"            ,	   0x118008094b858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5900"            ,	   0x118008094b860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5901"            ,	   0x118008094b868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5902"            ,	   0x118008094b870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5903"            ,	   0x118008094b878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5904"            ,	   0x118008094b880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5905"            ,	   0x118008094b888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5906"            ,	   0x118008094b890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5907"            ,	   0x118008094b898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5908"            ,	   0x118008094b8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5909"            ,	   0x118008094b8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5910"            ,	   0x118008094b8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5911"            ,	   0x118008094b8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5912"            ,	   0x118008094b8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5913"            ,	   0x118008094b8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5914"            ,	   0x118008094b8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5915"            ,	   0x118008094b8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5916"            ,	   0x118008094b8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5917"            ,	   0x118008094b8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5918"            ,	   0x118008094b8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5919"            ,	   0x118008094b8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5920"            ,	   0x118008094b900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5921"            ,	   0x118008094b908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5922"            ,	   0x118008094b910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5923"            ,	   0x118008094b918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5924"            ,	   0x118008094b920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5925"            ,	   0x118008094b928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5926"            ,	   0x118008094b930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5927"            ,	   0x118008094b938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5928"            ,	   0x118008094b940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5929"            ,	   0x118008094b948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5930"            ,	   0x118008094b950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5931"            ,	   0x118008094b958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5932"            ,	   0x118008094b960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5933"            ,	   0x118008094b968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5934"            ,	   0x118008094b970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5935"            ,	   0x118008094b978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5936"            ,	   0x118008094b980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5937"            ,	   0x118008094b988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5938"            ,	   0x118008094b990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5939"            ,	   0x118008094b998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5940"            ,	   0x118008094b9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5941"            ,	   0x118008094b9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5942"            ,	   0x118008094b9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5943"            ,	   0x118008094b9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5944"            ,	   0x118008094b9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5945"            ,	   0x118008094b9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5946"            ,	   0x118008094b9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5947"            ,	   0x118008094b9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5948"            ,	   0x118008094b9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5949"            ,	   0x118008094b9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5950"            ,	   0x118008094b9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5951"            ,	   0x118008094b9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5952"            ,	   0x118008094ba00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5953"            ,	   0x118008094ba08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5954"            ,	   0x118008094ba10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5955"            ,	   0x118008094ba18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5956"            ,	   0x118008094ba20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5957"            ,	   0x118008094ba28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5958"            ,	   0x118008094ba30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5959"            ,	   0x118008094ba38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5960"            ,	   0x118008094ba40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5961"            ,	   0x118008094ba48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5962"            ,	   0x118008094ba50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5963"            ,	   0x118008094ba58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5964"            ,	   0x118008094ba60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5965"            ,	   0x118008094ba68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5966"            ,	   0x118008094ba70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5967"            ,	   0x118008094ba78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5968"            ,	   0x118008094ba80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5969"            ,	   0x118008094ba88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5970"            ,	   0x118008094ba90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5971"            ,	   0x118008094ba98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5972"            ,	   0x118008094baa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5973"            ,	   0x118008094baa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5974"            ,	   0x118008094bab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5975"            ,	   0x118008094bab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5976"            ,	   0x118008094bac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5977"            ,	   0x118008094bac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5978"            ,	   0x118008094bad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5979"            ,	   0x118008094bad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5980"            ,	   0x118008094bae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5981"            ,	   0x118008094bae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5982"            ,	   0x118008094baf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5983"            ,	   0x118008094baf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5984"            ,	   0x118008094bb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5985"            ,	   0x118008094bb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5986"            ,	   0x118008094bb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5987"            ,	   0x118008094bb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5988"            ,	   0x118008094bb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5989"            ,	   0x118008094bb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5990"            ,	   0x118008094bb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5991"            ,	   0x118008094bb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5992"            ,	   0x118008094bb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5993"            ,	   0x118008094bb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5994"            ,	   0x118008094bb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5995"            ,	   0x118008094bb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5996"            ,	   0x118008094bb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5997"            ,	   0x118008094bb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5998"            ,	   0x118008094bb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP5999"            ,	   0x118008094bb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6000"            ,	   0x118008094bb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6001"            ,	   0x118008094bb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6002"            ,	   0x118008094bb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6003"            ,	   0x118008094bb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6004"            ,	   0x118008094bba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6005"            ,	   0x118008094bba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6006"            ,	   0x118008094bbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6007"            ,	   0x118008094bbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6008"            ,	   0x118008094bbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6009"            ,	   0x118008094bbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6010"            ,	   0x118008094bbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6011"            ,	   0x118008094bbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6012"            ,	   0x118008094bbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6013"            ,	   0x118008094bbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6014"            ,	   0x118008094bbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6015"            ,	   0x118008094bbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6016"            ,	   0x118008094bc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6017"            ,	   0x118008094bc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6018"            ,	   0x118008094bc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6019"            ,	   0x118008094bc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6020"            ,	   0x118008094bc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6021"            ,	   0x118008094bc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6022"            ,	   0x118008094bc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6023"            ,	   0x118008094bc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6024"            ,	   0x118008094bc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6025"            ,	   0x118008094bc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6026"            ,	   0x118008094bc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6027"            ,	   0x118008094bc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6028"            ,	   0x118008094bc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6029"            ,	   0x118008094bc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6030"            ,	   0x118008094bc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6031"            ,	   0x118008094bc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6032"            ,	   0x118008094bc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6033"            ,	   0x118008094bc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6034"            ,	   0x118008094bc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6035"            ,	   0x118008094bc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6036"            ,	   0x118008094bca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6037"            ,	   0x118008094bca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6038"            ,	   0x118008094bcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6039"            ,	   0x118008094bcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6040"            ,	   0x118008094bcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6041"            ,	   0x118008094bcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6042"            ,	   0x118008094bcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6043"            ,	   0x118008094bcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6044"            ,	   0x118008094bce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6045"            ,	   0x118008094bce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6046"            ,	   0x118008094bcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6047"            ,	   0x118008094bcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6048"            ,	   0x118008094bd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6049"            ,	   0x118008094bd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6050"            ,	   0x118008094bd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6051"            ,	   0x118008094bd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6052"            ,	   0x118008094bd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6053"            ,	   0x118008094bd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6054"            ,	   0x118008094bd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6055"            ,	   0x118008094bd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6056"            ,	   0x118008094bd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6057"            ,	   0x118008094bd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6058"            ,	   0x118008094bd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6059"            ,	   0x118008094bd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6060"            ,	   0x118008094bd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6061"            ,	   0x118008094bd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6062"            ,	   0x118008094bd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6063"            ,	   0x118008094bd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6064"            ,	   0x118008094bd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6065"            ,	   0x118008094bd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6066"            ,	   0x118008094bd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6067"            ,	   0x118008094bd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6068"            ,	   0x118008094bda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6069"            ,	   0x118008094bda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6070"            ,	   0x118008094bdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6071"            ,	   0x118008094bdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6072"            ,	   0x118008094bdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6073"            ,	   0x118008094bdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6074"            ,	   0x118008094bdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6075"            ,	   0x118008094bdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6076"            ,	   0x118008094bde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6077"            ,	   0x118008094bde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6078"            ,	   0x118008094bdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6079"            ,	   0x118008094bdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6080"            ,	   0x118008094be00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6081"            ,	   0x118008094be08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6082"            ,	   0x118008094be10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6083"            ,	   0x118008094be18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6084"            ,	   0x118008094be20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6085"            ,	   0x118008094be28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6086"            ,	   0x118008094be30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6087"            ,	   0x118008094be38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6088"            ,	   0x118008094be40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6089"            ,	   0x118008094be48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6090"            ,	   0x118008094be50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6091"            ,	   0x118008094be58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6092"            ,	   0x118008094be60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6093"            ,	   0x118008094be68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6094"            ,	   0x118008094be70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6095"            ,	   0x118008094be78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6096"            ,	   0x118008094be80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6097"            ,	   0x118008094be88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6098"            ,	   0x118008094be90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6099"            ,	   0x118008094be98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6100"            ,	   0x118008094bea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6101"            ,	   0x118008094bea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6102"            ,	   0x118008094beb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6103"            ,	   0x118008094beb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6104"            ,	   0x118008094bec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6105"            ,	   0x118008094bec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6106"            ,	   0x118008094bed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6107"            ,	   0x118008094bed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6108"            ,	   0x118008094bee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6109"            ,	   0x118008094bee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6110"            ,	   0x118008094bef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6111"            ,	   0x118008094bef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6112"            ,	   0x118008094bf00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6113"            ,	   0x118008094bf08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6114"            ,	   0x118008094bf10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6115"            ,	   0x118008094bf18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6116"            ,	   0x118008094bf20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6117"            ,	   0x118008094bf28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6118"            ,	   0x118008094bf30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6119"            ,	   0x118008094bf38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6120"            ,	   0x118008094bf40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6121"            ,	   0x118008094bf48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6122"            ,	   0x118008094bf50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6123"            ,	   0x118008094bf58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6124"            ,	   0x118008094bf60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6125"            ,	   0x118008094bf68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6126"            ,	   0x118008094bf70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6127"            ,	   0x118008094bf78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6128"            ,	   0x118008094bf80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6129"            ,	   0x118008094bf88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6130"            ,	   0x118008094bf90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6131"            ,	   0x118008094bf98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6132"            ,	   0x118008094bfa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6133"            ,	   0x118008094bfa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6134"            ,	   0x118008094bfb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6135"            ,	   0x118008094bfb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6136"            ,	   0x118008094bfc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6137"            ,	   0x118008094bfc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6138"            ,	   0x118008094bfd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6139"            ,	   0x118008094bfd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6140"            ,	   0x118008094bfe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6141"            ,	   0x118008094bfe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6142"            ,	   0x118008094bff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6143"            ,	   0x118008094bff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6144"            ,	   0x118008094c000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6145"            ,	   0x118008094c008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6146"            ,	   0x118008094c010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6147"            ,	   0x118008094c018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6148"            ,	   0x118008094c020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6149"            ,	   0x118008094c028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6150"            ,	   0x118008094c030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6151"            ,	   0x118008094c038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6152"            ,	   0x118008094c040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6153"            ,	   0x118008094c048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6154"            ,	   0x118008094c050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6155"            ,	   0x118008094c058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6156"            ,	   0x118008094c060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6157"            ,	   0x118008094c068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6158"            ,	   0x118008094c070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6159"            ,	   0x118008094c078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6160"            ,	   0x118008094c080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6161"            ,	   0x118008094c088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6162"            ,	   0x118008094c090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6163"            ,	   0x118008094c098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6164"            ,	   0x118008094c0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6165"            ,	   0x118008094c0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6166"            ,	   0x118008094c0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6167"            ,	   0x118008094c0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6168"            ,	   0x118008094c0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6169"            ,	   0x118008094c0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6170"            ,	   0x118008094c0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6171"            ,	   0x118008094c0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6172"            ,	   0x118008094c0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6173"            ,	   0x118008094c0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6174"            ,	   0x118008094c0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6175"            ,	   0x118008094c0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6176"            ,	   0x118008094c100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6177"            ,	   0x118008094c108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6178"            ,	   0x118008094c110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6179"            ,	   0x118008094c118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6180"            ,	   0x118008094c120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6181"            ,	   0x118008094c128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6182"            ,	   0x118008094c130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6183"            ,	   0x118008094c138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6184"            ,	   0x118008094c140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6185"            ,	   0x118008094c148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6186"            ,	   0x118008094c150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6187"            ,	   0x118008094c158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6188"            ,	   0x118008094c160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6189"            ,	   0x118008094c168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6190"            ,	   0x118008094c170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6191"            ,	   0x118008094c178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6192"            ,	   0x118008094c180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6193"            ,	   0x118008094c188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6194"            ,	   0x118008094c190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6195"            ,	   0x118008094c198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6196"            ,	   0x118008094c1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6197"            ,	   0x118008094c1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6198"            ,	   0x118008094c1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6199"            ,	   0x118008094c1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6200"            ,	   0x118008094c1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6201"            ,	   0x118008094c1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6202"            ,	   0x118008094c1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6203"            ,	   0x118008094c1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6204"            ,	   0x118008094c1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6205"            ,	   0x118008094c1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6206"            ,	   0x118008094c1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6207"            ,	   0x118008094c1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6208"            ,	   0x118008094c200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6209"            ,	   0x118008094c208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6210"            ,	   0x118008094c210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6211"            ,	   0x118008094c218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6212"            ,	   0x118008094c220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6213"            ,	   0x118008094c228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6214"            ,	   0x118008094c230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6215"            ,	   0x118008094c238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6216"            ,	   0x118008094c240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6217"            ,	   0x118008094c248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6218"            ,	   0x118008094c250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6219"            ,	   0x118008094c258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6220"            ,	   0x118008094c260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6221"            ,	   0x118008094c268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6222"            ,	   0x118008094c270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6223"            ,	   0x118008094c278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6224"            ,	   0x118008094c280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6225"            ,	   0x118008094c288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6226"            ,	   0x118008094c290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6227"            ,	   0x118008094c298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6228"            ,	   0x118008094c2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6229"            ,	   0x118008094c2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6230"            ,	   0x118008094c2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6231"            ,	   0x118008094c2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6232"            ,	   0x118008094c2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6233"            ,	   0x118008094c2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6234"            ,	   0x118008094c2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6235"            ,	   0x118008094c2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6236"            ,	   0x118008094c2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6237"            ,	   0x118008094c2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6238"            ,	   0x118008094c2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6239"            ,	   0x118008094c2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6240"            ,	   0x118008094c300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6241"            ,	   0x118008094c308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6242"            ,	   0x118008094c310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6243"            ,	   0x118008094c318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6244"            ,	   0x118008094c320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6245"            ,	   0x118008094c328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6246"            ,	   0x118008094c330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6247"            ,	   0x118008094c338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6248"            ,	   0x118008094c340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6249"            ,	   0x118008094c348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6250"            ,	   0x118008094c350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6251"            ,	   0x118008094c358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6252"            ,	   0x118008094c360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6253"            ,	   0x118008094c368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6254"            ,	   0x118008094c370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6255"            ,	   0x118008094c378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6256"            ,	   0x118008094c380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6257"            ,	   0x118008094c388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6258"            ,	   0x118008094c390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6259"            ,	   0x118008094c398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6260"            ,	   0x118008094c3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6261"            ,	   0x118008094c3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6262"            ,	   0x118008094c3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6263"            ,	   0x118008094c3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6264"            ,	   0x118008094c3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6265"            ,	   0x118008094c3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6266"            ,	   0x118008094c3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6267"            ,	   0x118008094c3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6268"            ,	   0x118008094c3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6269"            ,	   0x118008094c3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6270"            ,	   0x118008094c3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6271"            ,	   0x118008094c3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6272"            ,	   0x118008094c400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6273"            ,	   0x118008094c408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6274"            ,	   0x118008094c410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6275"            ,	   0x118008094c418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6276"            ,	   0x118008094c420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6277"            ,	   0x118008094c428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6278"            ,	   0x118008094c430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6279"            ,	   0x118008094c438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6280"            ,	   0x118008094c440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6281"            ,	   0x118008094c448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6282"            ,	   0x118008094c450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6283"            ,	   0x118008094c458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6284"            ,	   0x118008094c460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6285"            ,	   0x118008094c468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6286"            ,	   0x118008094c470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6287"            ,	   0x118008094c478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6288"            ,	   0x118008094c480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6289"            ,	   0x118008094c488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6290"            ,	   0x118008094c490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6291"            ,	   0x118008094c498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6292"            ,	   0x118008094c4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6293"            ,	   0x118008094c4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6294"            ,	   0x118008094c4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6295"            ,	   0x118008094c4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6296"            ,	   0x118008094c4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6297"            ,	   0x118008094c4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6298"            ,	   0x118008094c4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6299"            ,	   0x118008094c4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6300"            ,	   0x118008094c4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6301"            ,	   0x118008094c4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6302"            ,	   0x118008094c4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6303"            ,	   0x118008094c4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6304"            ,	   0x118008094c500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6305"            ,	   0x118008094c508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6306"            ,	   0x118008094c510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6307"            ,	   0x118008094c518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6308"            ,	   0x118008094c520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6309"            ,	   0x118008094c528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6310"            ,	   0x118008094c530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6311"            ,	   0x118008094c538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6312"            ,	   0x118008094c540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6313"            ,	   0x118008094c548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6314"            ,	   0x118008094c550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6315"            ,	   0x118008094c558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6316"            ,	   0x118008094c560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6317"            ,	   0x118008094c568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6318"            ,	   0x118008094c570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6319"            ,	   0x118008094c578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6320"            ,	   0x118008094c580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6321"            ,	   0x118008094c588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6322"            ,	   0x118008094c590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6323"            ,	   0x118008094c598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6324"            ,	   0x118008094c5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6325"            ,	   0x118008094c5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6326"            ,	   0x118008094c5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6327"            ,	   0x118008094c5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6328"            ,	   0x118008094c5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6329"            ,	   0x118008094c5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6330"            ,	   0x118008094c5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6331"            ,	   0x118008094c5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6332"            ,	   0x118008094c5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6333"            ,	   0x118008094c5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6334"            ,	   0x118008094c5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6335"            ,	   0x118008094c5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6336"            ,	   0x118008094c600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6337"            ,	   0x118008094c608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6338"            ,	   0x118008094c610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6339"            ,	   0x118008094c618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6340"            ,	   0x118008094c620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6341"            ,	   0x118008094c628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6342"            ,	   0x118008094c630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6343"            ,	   0x118008094c638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6344"            ,	   0x118008094c640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6345"            ,	   0x118008094c648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6346"            ,	   0x118008094c650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6347"            ,	   0x118008094c658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6348"            ,	   0x118008094c660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6349"            ,	   0x118008094c668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6350"            ,	   0x118008094c670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6351"            ,	   0x118008094c678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6352"            ,	   0x118008094c680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6353"            ,	   0x118008094c688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6354"            ,	   0x118008094c690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6355"            ,	   0x118008094c698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6356"            ,	   0x118008094c6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6357"            ,	   0x118008094c6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6358"            ,	   0x118008094c6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6359"            ,	   0x118008094c6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6360"            ,	   0x118008094c6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6361"            ,	   0x118008094c6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6362"            ,	   0x118008094c6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6363"            ,	   0x118008094c6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6364"            ,	   0x118008094c6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6365"            ,	   0x118008094c6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6366"            ,	   0x118008094c6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6367"            ,	   0x118008094c6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6368"            ,	   0x118008094c700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6369"            ,	   0x118008094c708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6370"            ,	   0x118008094c710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6371"            ,	   0x118008094c718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6372"            ,	   0x118008094c720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6373"            ,	   0x118008094c728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6374"            ,	   0x118008094c730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6375"            ,	   0x118008094c738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6376"            ,	   0x118008094c740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6377"            ,	   0x118008094c748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6378"            ,	   0x118008094c750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6379"            ,	   0x118008094c758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6380"            ,	   0x118008094c760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6381"            ,	   0x118008094c768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6382"            ,	   0x118008094c770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6383"            ,	   0x118008094c778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6384"            ,	   0x118008094c780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6385"            ,	   0x118008094c788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6386"            ,	   0x118008094c790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6387"            ,	   0x118008094c798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6388"            ,	   0x118008094c7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6389"            ,	   0x118008094c7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6390"            ,	   0x118008094c7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6391"            ,	   0x118008094c7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6392"            ,	   0x118008094c7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6393"            ,	   0x118008094c7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6394"            ,	   0x118008094c7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6395"            ,	   0x118008094c7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6396"            ,	   0x118008094c7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6397"            ,	   0x118008094c7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6398"            ,	   0x118008094c7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6399"            ,	   0x118008094c7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6400"            ,	   0x118008094c800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6401"            ,	   0x118008094c808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6402"            ,	   0x118008094c810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6403"            ,	   0x118008094c818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6404"            ,	   0x118008094c820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6405"            ,	   0x118008094c828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6406"            ,	   0x118008094c830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6407"            ,	   0x118008094c838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6408"            ,	   0x118008094c840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6409"            ,	   0x118008094c848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6410"            ,	   0x118008094c850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6411"            ,	   0x118008094c858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6412"            ,	   0x118008094c860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6413"            ,	   0x118008094c868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6414"            ,	   0x118008094c870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6415"            ,	   0x118008094c878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6416"            ,	   0x118008094c880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6417"            ,	   0x118008094c888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6418"            ,	   0x118008094c890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6419"            ,	   0x118008094c898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6420"            ,	   0x118008094c8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6421"            ,	   0x118008094c8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6422"            ,	   0x118008094c8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6423"            ,	   0x118008094c8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6424"            ,	   0x118008094c8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6425"            ,	   0x118008094c8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6426"            ,	   0x118008094c8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6427"            ,	   0x118008094c8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6428"            ,	   0x118008094c8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6429"            ,	   0x118008094c8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6430"            ,	   0x118008094c8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6431"            ,	   0x118008094c8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6432"            ,	   0x118008094c900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6433"            ,	   0x118008094c908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6434"            ,	   0x118008094c910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6435"            ,	   0x118008094c918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6436"            ,	   0x118008094c920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6437"            ,	   0x118008094c928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6438"            ,	   0x118008094c930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6439"            ,	   0x118008094c938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6440"            ,	   0x118008094c940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6441"            ,	   0x118008094c948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6442"            ,	   0x118008094c950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6443"            ,	   0x118008094c958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6444"            ,	   0x118008094c960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6445"            ,	   0x118008094c968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6446"            ,	   0x118008094c970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6447"            ,	   0x118008094c978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6448"            ,	   0x118008094c980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6449"            ,	   0x118008094c988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6450"            ,	   0x118008094c990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6451"            ,	   0x118008094c998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6452"            ,	   0x118008094c9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6453"            ,	   0x118008094c9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6454"            ,	   0x118008094c9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6455"            ,	   0x118008094c9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6456"            ,	   0x118008094c9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6457"            ,	   0x118008094c9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6458"            ,	   0x118008094c9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6459"            ,	   0x118008094c9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6460"            ,	   0x118008094c9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6461"            ,	   0x118008094c9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6462"            ,	   0x118008094c9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6463"            ,	   0x118008094c9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6464"            ,	   0x118008094ca00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6465"            ,	   0x118008094ca08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6466"            ,	   0x118008094ca10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6467"            ,	   0x118008094ca18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6468"            ,	   0x118008094ca20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6469"            ,	   0x118008094ca28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6470"            ,	   0x118008094ca30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6471"            ,	   0x118008094ca38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6472"            ,	   0x118008094ca40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6473"            ,	   0x118008094ca48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6474"            ,	   0x118008094ca50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6475"            ,	   0x118008094ca58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6476"            ,	   0x118008094ca60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6477"            ,	   0x118008094ca68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6478"            ,	   0x118008094ca70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6479"            ,	   0x118008094ca78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6480"            ,	   0x118008094ca80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6481"            ,	   0x118008094ca88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6482"            ,	   0x118008094ca90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6483"            ,	   0x118008094ca98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6484"            ,	   0x118008094caa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6485"            ,	   0x118008094caa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6486"            ,	   0x118008094cab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6487"            ,	   0x118008094cab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6488"            ,	   0x118008094cac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6489"            ,	   0x118008094cac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6490"            ,	   0x118008094cad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6491"            ,	   0x118008094cad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6492"            ,	   0x118008094cae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6493"            ,	   0x118008094cae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6494"            ,	   0x118008094caf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6495"            ,	   0x118008094caf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6496"            ,	   0x118008094cb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6497"            ,	   0x118008094cb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6498"            ,	   0x118008094cb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6499"            ,	   0x118008094cb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6500"            ,	   0x118008094cb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6501"            ,	   0x118008094cb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6502"            ,	   0x118008094cb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6503"            ,	   0x118008094cb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6504"            ,	   0x118008094cb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6505"            ,	   0x118008094cb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6506"            ,	   0x118008094cb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6507"            ,	   0x118008094cb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6508"            ,	   0x118008094cb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6509"            ,	   0x118008094cb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6510"            ,	   0x118008094cb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6511"            ,	   0x118008094cb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6512"            ,	   0x118008094cb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6513"            ,	   0x118008094cb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6514"            ,	   0x118008094cb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6515"            ,	   0x118008094cb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6516"            ,	   0x118008094cba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6517"            ,	   0x118008094cba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6518"            ,	   0x118008094cbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6519"            ,	   0x118008094cbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6520"            ,	   0x118008094cbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6521"            ,	   0x118008094cbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6522"            ,	   0x118008094cbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6523"            ,	   0x118008094cbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6524"            ,	   0x118008094cbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6525"            ,	   0x118008094cbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6526"            ,	   0x118008094cbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6527"            ,	   0x118008094cbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6528"            ,	   0x118008094cc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6529"            ,	   0x118008094cc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6530"            ,	   0x118008094cc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6531"            ,	   0x118008094cc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6532"            ,	   0x118008094cc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6533"            ,	   0x118008094cc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6534"            ,	   0x118008094cc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6535"            ,	   0x118008094cc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6536"            ,	   0x118008094cc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6537"            ,	   0x118008094cc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6538"            ,	   0x118008094cc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6539"            ,	   0x118008094cc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6540"            ,	   0x118008094cc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6541"            ,	   0x118008094cc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6542"            ,	   0x118008094cc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6543"            ,	   0x118008094cc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6544"            ,	   0x118008094cc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6545"            ,	   0x118008094cc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6546"            ,	   0x118008094cc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6547"            ,	   0x118008094cc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6548"            ,	   0x118008094cca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6549"            ,	   0x118008094cca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6550"            ,	   0x118008094ccb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6551"            ,	   0x118008094ccb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6552"            ,	   0x118008094ccc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6553"            ,	   0x118008094ccc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6554"            ,	   0x118008094ccd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6555"            ,	   0x118008094ccd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6556"            ,	   0x118008094cce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6557"            ,	   0x118008094cce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6558"            ,	   0x118008094ccf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6559"            ,	   0x118008094ccf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6560"            ,	   0x118008094cd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6561"            ,	   0x118008094cd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6562"            ,	   0x118008094cd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6563"            ,	   0x118008094cd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6564"            ,	   0x118008094cd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6565"            ,	   0x118008094cd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6566"            ,	   0x118008094cd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6567"            ,	   0x118008094cd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6568"            ,	   0x118008094cd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6569"            ,	   0x118008094cd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6570"            ,	   0x118008094cd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6571"            ,	   0x118008094cd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6572"            ,	   0x118008094cd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6573"            ,	   0x118008094cd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6574"            ,	   0x118008094cd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6575"            ,	   0x118008094cd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6576"            ,	   0x118008094cd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6577"            ,	   0x118008094cd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6578"            ,	   0x118008094cd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6579"            ,	   0x118008094cd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6580"            ,	   0x118008094cda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6581"            ,	   0x118008094cda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6582"            ,	   0x118008094cdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6583"            ,	   0x118008094cdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6584"            ,	   0x118008094cdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6585"            ,	   0x118008094cdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6586"            ,	   0x118008094cdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6587"            ,	   0x118008094cdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6588"            ,	   0x118008094cde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6589"            ,	   0x118008094cde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6590"            ,	   0x118008094cdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6591"            ,	   0x118008094cdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6592"            ,	   0x118008094ce00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6593"            ,	   0x118008094ce08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6594"            ,	   0x118008094ce10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6595"            ,	   0x118008094ce18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6596"            ,	   0x118008094ce20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6597"            ,	   0x118008094ce28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6598"            ,	   0x118008094ce30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6599"            ,	   0x118008094ce38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6600"            ,	   0x118008094ce40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6601"            ,	   0x118008094ce48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6602"            ,	   0x118008094ce50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6603"            ,	   0x118008094ce58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6604"            ,	   0x118008094ce60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6605"            ,	   0x118008094ce68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6606"            ,	   0x118008094ce70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6607"            ,	   0x118008094ce78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6608"            ,	   0x118008094ce80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6609"            ,	   0x118008094ce88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6610"            ,	   0x118008094ce90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6611"            ,	   0x118008094ce98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6612"            ,	   0x118008094cea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6613"            ,	   0x118008094cea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6614"            ,	   0x118008094ceb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6615"            ,	   0x118008094ceb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6616"            ,	   0x118008094cec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6617"            ,	   0x118008094cec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6618"            ,	   0x118008094ced0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6619"            ,	   0x118008094ced8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6620"            ,	   0x118008094cee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6621"            ,	   0x118008094cee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6622"            ,	   0x118008094cef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6623"            ,	   0x118008094cef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6624"            ,	   0x118008094cf00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6625"            ,	   0x118008094cf08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6626"            ,	   0x118008094cf10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6627"            ,	   0x118008094cf18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6628"            ,	   0x118008094cf20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6629"            ,	   0x118008094cf28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6630"            ,	   0x118008094cf30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6631"            ,	   0x118008094cf38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6632"            ,	   0x118008094cf40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6633"            ,	   0x118008094cf48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6634"            ,	   0x118008094cf50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6635"            ,	   0x118008094cf58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6636"            ,	   0x118008094cf60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6637"            ,	   0x118008094cf68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6638"            ,	   0x118008094cf70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6639"            ,	   0x118008094cf78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6640"            ,	   0x118008094cf80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6641"            ,	   0x118008094cf88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6642"            ,	   0x118008094cf90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6643"            ,	   0x118008094cf98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6644"            ,	   0x118008094cfa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6645"            ,	   0x118008094cfa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6646"            ,	   0x118008094cfb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6647"            ,	   0x118008094cfb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6648"            ,	   0x118008094cfc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6649"            ,	   0x118008094cfc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6650"            ,	   0x118008094cfd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6651"            ,	   0x118008094cfd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6652"            ,	   0x118008094cfe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6653"            ,	   0x118008094cfe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6654"            ,	   0x118008094cff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6655"            ,	   0x118008094cff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6656"            ,	   0x118008094d000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6657"            ,	   0x118008094d008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6658"            ,	   0x118008094d010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6659"            ,	   0x118008094d018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6660"            ,	   0x118008094d020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6661"            ,	   0x118008094d028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6662"            ,	   0x118008094d030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6663"            ,	   0x118008094d038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6664"            ,	   0x118008094d040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6665"            ,	   0x118008094d048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6666"            ,	   0x118008094d050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6667"            ,	   0x118008094d058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6668"            ,	   0x118008094d060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6669"            ,	   0x118008094d068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6670"            ,	   0x118008094d070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6671"            ,	   0x118008094d078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6672"            ,	   0x118008094d080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6673"            ,	   0x118008094d088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6674"            ,	   0x118008094d090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6675"            ,	   0x118008094d098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6676"            ,	   0x118008094d0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6677"            ,	   0x118008094d0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6678"            ,	   0x118008094d0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6679"            ,	   0x118008094d0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6680"            ,	   0x118008094d0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6681"            ,	   0x118008094d0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6682"            ,	   0x118008094d0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6683"            ,	   0x118008094d0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6684"            ,	   0x118008094d0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6685"            ,	   0x118008094d0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6686"            ,	   0x118008094d0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6687"            ,	   0x118008094d0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6688"            ,	   0x118008094d100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6689"            ,	   0x118008094d108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6690"            ,	   0x118008094d110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6691"            ,	   0x118008094d118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6692"            ,	   0x118008094d120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6693"            ,	   0x118008094d128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6694"            ,	   0x118008094d130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6695"            ,	   0x118008094d138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6696"            ,	   0x118008094d140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6697"            ,	   0x118008094d148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6698"            ,	   0x118008094d150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6699"            ,	   0x118008094d158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6700"            ,	   0x118008094d160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6701"            ,	   0x118008094d168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6702"            ,	   0x118008094d170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6703"            ,	   0x118008094d178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6704"            ,	   0x118008094d180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6705"            ,	   0x118008094d188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6706"            ,	   0x118008094d190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6707"            ,	   0x118008094d198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6708"            ,	   0x118008094d1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6709"            ,	   0x118008094d1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6710"            ,	   0x118008094d1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6711"            ,	   0x118008094d1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6712"            ,	   0x118008094d1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6713"            ,	   0x118008094d1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6714"            ,	   0x118008094d1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6715"            ,	   0x118008094d1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6716"            ,	   0x118008094d1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6717"            ,	   0x118008094d1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6718"            ,	   0x118008094d1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6719"            ,	   0x118008094d1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6720"            ,	   0x118008094d200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6721"            ,	   0x118008094d208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6722"            ,	   0x118008094d210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6723"            ,	   0x118008094d218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6724"            ,	   0x118008094d220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6725"            ,	   0x118008094d228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6726"            ,	   0x118008094d230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6727"            ,	   0x118008094d238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6728"            ,	   0x118008094d240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6729"            ,	   0x118008094d248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6730"            ,	   0x118008094d250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6731"            ,	   0x118008094d258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6732"            ,	   0x118008094d260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6733"            ,	   0x118008094d268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6734"            ,	   0x118008094d270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6735"            ,	   0x118008094d278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6736"            ,	   0x118008094d280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6737"            ,	   0x118008094d288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6738"            ,	   0x118008094d290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6739"            ,	   0x118008094d298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6740"            ,	   0x118008094d2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6741"            ,	   0x118008094d2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6742"            ,	   0x118008094d2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6743"            ,	   0x118008094d2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6744"            ,	   0x118008094d2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6745"            ,	   0x118008094d2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6746"            ,	   0x118008094d2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6747"            ,	   0x118008094d2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6748"            ,	   0x118008094d2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6749"            ,	   0x118008094d2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6750"            ,	   0x118008094d2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6751"            ,	   0x118008094d2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6752"            ,	   0x118008094d300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6753"            ,	   0x118008094d308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6754"            ,	   0x118008094d310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6755"            ,	   0x118008094d318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6756"            ,	   0x118008094d320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6757"            ,	   0x118008094d328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6758"            ,	   0x118008094d330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6759"            ,	   0x118008094d338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6760"            ,	   0x118008094d340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6761"            ,	   0x118008094d348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6762"            ,	   0x118008094d350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6763"            ,	   0x118008094d358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6764"            ,	   0x118008094d360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6765"            ,	   0x118008094d368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6766"            ,	   0x118008094d370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6767"            ,	   0x118008094d378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6768"            ,	   0x118008094d380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6769"            ,	   0x118008094d388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6770"            ,	   0x118008094d390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6771"            ,	   0x118008094d398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6772"            ,	   0x118008094d3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6773"            ,	   0x118008094d3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6774"            ,	   0x118008094d3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6775"            ,	   0x118008094d3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6776"            ,	   0x118008094d3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6777"            ,	   0x118008094d3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6778"            ,	   0x118008094d3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6779"            ,	   0x118008094d3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6780"            ,	   0x118008094d3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6781"            ,	   0x118008094d3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6782"            ,	   0x118008094d3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6783"            ,	   0x118008094d3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6784"            ,	   0x118008094d400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6785"            ,	   0x118008094d408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6786"            ,	   0x118008094d410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6787"            ,	   0x118008094d418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6788"            ,	   0x118008094d420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6789"            ,	   0x118008094d428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6790"            ,	   0x118008094d430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6791"            ,	   0x118008094d438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6792"            ,	   0x118008094d440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6793"            ,	   0x118008094d448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6794"            ,	   0x118008094d450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6795"            ,	   0x118008094d458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6796"            ,	   0x118008094d460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6797"            ,	   0x118008094d468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6798"            ,	   0x118008094d470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6799"            ,	   0x118008094d478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6800"            ,	   0x118008094d480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6801"            ,	   0x118008094d488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6802"            ,	   0x118008094d490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6803"            ,	   0x118008094d498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6804"            ,	   0x118008094d4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6805"            ,	   0x118008094d4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6806"            ,	   0x118008094d4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6807"            ,	   0x118008094d4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6808"            ,	   0x118008094d4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6809"            ,	   0x118008094d4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6810"            ,	   0x118008094d4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6811"            ,	   0x118008094d4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6812"            ,	   0x118008094d4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6813"            ,	   0x118008094d4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6814"            ,	   0x118008094d4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6815"            ,	   0x118008094d4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6816"            ,	   0x118008094d500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6817"            ,	   0x118008094d508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6818"            ,	   0x118008094d510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6819"            ,	   0x118008094d518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6820"            ,	   0x118008094d520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6821"            ,	   0x118008094d528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6822"            ,	   0x118008094d530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6823"            ,	   0x118008094d538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6824"            ,	   0x118008094d540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6825"            ,	   0x118008094d548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6826"            ,	   0x118008094d550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6827"            ,	   0x118008094d558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6828"            ,	   0x118008094d560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6829"            ,	   0x118008094d568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6830"            ,	   0x118008094d570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6831"            ,	   0x118008094d578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6832"            ,	   0x118008094d580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6833"            ,	   0x118008094d588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6834"            ,	   0x118008094d590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6835"            ,	   0x118008094d598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6836"            ,	   0x118008094d5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6837"            ,	   0x118008094d5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6838"            ,	   0x118008094d5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6839"            ,	   0x118008094d5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6840"            ,	   0x118008094d5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6841"            ,	   0x118008094d5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6842"            ,	   0x118008094d5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6843"            ,	   0x118008094d5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6844"            ,	   0x118008094d5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6845"            ,	   0x118008094d5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6846"            ,	   0x118008094d5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6847"            ,	   0x118008094d5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6848"            ,	   0x118008094d600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6849"            ,	   0x118008094d608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6850"            ,	   0x118008094d610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6851"            ,	   0x118008094d618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6852"            ,	   0x118008094d620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6853"            ,	   0x118008094d628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6854"            ,	   0x118008094d630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6855"            ,	   0x118008094d638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6856"            ,	   0x118008094d640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6857"            ,	   0x118008094d648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6858"            ,	   0x118008094d650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6859"            ,	   0x118008094d658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6860"            ,	   0x118008094d660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6861"            ,	   0x118008094d668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6862"            ,	   0x118008094d670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6863"            ,	   0x118008094d678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6864"            ,	   0x118008094d680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6865"            ,	   0x118008094d688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6866"            ,	   0x118008094d690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6867"            ,	   0x118008094d698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6868"            ,	   0x118008094d6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6869"            ,	   0x118008094d6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6870"            ,	   0x118008094d6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6871"            ,	   0x118008094d6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6872"            ,	   0x118008094d6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6873"            ,	   0x118008094d6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6874"            ,	   0x118008094d6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6875"            ,	   0x118008094d6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6876"            ,	   0x118008094d6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6877"            ,	   0x118008094d6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6878"            ,	   0x118008094d6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6879"            ,	   0x118008094d6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6880"            ,	   0x118008094d700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6881"            ,	   0x118008094d708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6882"            ,	   0x118008094d710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6883"            ,	   0x118008094d718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6884"            ,	   0x118008094d720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6885"            ,	   0x118008094d728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6886"            ,	   0x118008094d730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6887"            ,	   0x118008094d738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6888"            ,	   0x118008094d740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6889"            ,	   0x118008094d748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6890"            ,	   0x118008094d750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6891"            ,	   0x118008094d758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6892"            ,	   0x118008094d760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6893"            ,	   0x118008094d768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6894"            ,	   0x118008094d770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6895"            ,	   0x118008094d778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6896"            ,	   0x118008094d780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6897"            ,	   0x118008094d788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6898"            ,	   0x118008094d790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6899"            ,	   0x118008094d798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6900"            ,	   0x118008094d7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6901"            ,	   0x118008094d7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6902"            ,	   0x118008094d7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6903"            ,	   0x118008094d7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6904"            ,	   0x118008094d7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6905"            ,	   0x118008094d7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6906"            ,	   0x118008094d7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6907"            ,	   0x118008094d7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6908"            ,	   0x118008094d7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6909"            ,	   0x118008094d7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6910"            ,	   0x118008094d7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6911"            ,	   0x118008094d7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6912"            ,	   0x118008094d800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6913"            ,	   0x118008094d808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6914"            ,	   0x118008094d810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6915"            ,	   0x118008094d818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6916"            ,	   0x118008094d820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6917"            ,	   0x118008094d828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6918"            ,	   0x118008094d830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6919"            ,	   0x118008094d838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6920"            ,	   0x118008094d840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6921"            ,	   0x118008094d848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6922"            ,	   0x118008094d850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6923"            ,	   0x118008094d858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6924"            ,	   0x118008094d860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6925"            ,	   0x118008094d868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6926"            ,	   0x118008094d870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6927"            ,	   0x118008094d878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6928"            ,	   0x118008094d880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6929"            ,	   0x118008094d888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6930"            ,	   0x118008094d890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6931"            ,	   0x118008094d898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6932"            ,	   0x118008094d8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6933"            ,	   0x118008094d8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6934"            ,	   0x118008094d8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6935"            ,	   0x118008094d8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6936"            ,	   0x118008094d8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6937"            ,	   0x118008094d8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6938"            ,	   0x118008094d8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6939"            ,	   0x118008094d8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6940"            ,	   0x118008094d8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6941"            ,	   0x118008094d8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6942"            ,	   0x118008094d8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6943"            ,	   0x118008094d8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6944"            ,	   0x118008094d900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6945"            ,	   0x118008094d908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6946"            ,	   0x118008094d910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6947"            ,	   0x118008094d918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6948"            ,	   0x118008094d920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6949"            ,	   0x118008094d928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6950"            ,	   0x118008094d930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6951"            ,	   0x118008094d938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6952"            ,	   0x118008094d940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6953"            ,	   0x118008094d948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6954"            ,	   0x118008094d950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6955"            ,	   0x118008094d958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6956"            ,	   0x118008094d960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6957"            ,	   0x118008094d968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6958"            ,	   0x118008094d970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6959"            ,	   0x118008094d978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6960"            ,	   0x118008094d980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6961"            ,	   0x118008094d988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6962"            ,	   0x118008094d990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6963"            ,	   0x118008094d998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6964"            ,	   0x118008094d9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6965"            ,	   0x118008094d9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6966"            ,	   0x118008094d9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6967"            ,	   0x118008094d9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6968"            ,	   0x118008094d9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6969"            ,	   0x118008094d9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6970"            ,	   0x118008094d9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6971"            ,	   0x118008094d9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6972"            ,	   0x118008094d9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6973"            ,	   0x118008094d9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6974"            ,	   0x118008094d9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6975"            ,	   0x118008094d9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6976"            ,	   0x118008094da00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6977"            ,	   0x118008094da08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6978"            ,	   0x118008094da10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6979"            ,	   0x118008094da18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6980"            ,	   0x118008094da20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6981"            ,	   0x118008094da28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6982"            ,	   0x118008094da30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6983"            ,	   0x118008094da38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6984"            ,	   0x118008094da40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6985"            ,	   0x118008094da48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6986"            ,	   0x118008094da50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6987"            ,	   0x118008094da58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6988"            ,	   0x118008094da60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6989"            ,	   0x118008094da68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6990"            ,	   0x118008094da70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6991"            ,	   0x118008094da78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6992"            ,	   0x118008094da80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6993"            ,	   0x118008094da88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6994"            ,	   0x118008094da90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6995"            ,	   0x118008094da98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6996"            ,	   0x118008094daa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6997"            ,	   0x118008094daa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6998"            ,	   0x118008094dab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP6999"            ,	   0x118008094dab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7000"            ,	   0x118008094dac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7001"            ,	   0x118008094dac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7002"            ,	   0x118008094dad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7003"            ,	   0x118008094dad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7004"            ,	   0x118008094dae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7005"            ,	   0x118008094dae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7006"            ,	   0x118008094daf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7007"            ,	   0x118008094daf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7008"            ,	   0x118008094db00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7009"            ,	   0x118008094db08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7010"            ,	   0x118008094db10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7011"            ,	   0x118008094db18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7012"            ,	   0x118008094db20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7013"            ,	   0x118008094db28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7014"            ,	   0x118008094db30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7015"            ,	   0x118008094db38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7016"            ,	   0x118008094db40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7017"            ,	   0x118008094db48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7018"            ,	   0x118008094db50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7019"            ,	   0x118008094db58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7020"            ,	   0x118008094db60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7021"            ,	   0x118008094db68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7022"            ,	   0x118008094db70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7023"            ,	   0x118008094db78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7024"            ,	   0x118008094db80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7025"            ,	   0x118008094db88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7026"            ,	   0x118008094db90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7027"            ,	   0x118008094db98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7028"            ,	   0x118008094dba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7029"            ,	   0x118008094dba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7030"            ,	   0x118008094dbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7031"            ,	   0x118008094dbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7032"            ,	   0x118008094dbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7033"            ,	   0x118008094dbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7034"            ,	   0x118008094dbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7035"            ,	   0x118008094dbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7036"            ,	   0x118008094dbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7037"            ,	   0x118008094dbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7038"            ,	   0x118008094dbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7039"            ,	   0x118008094dbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7040"            ,	   0x118008094dc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7041"            ,	   0x118008094dc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7042"            ,	   0x118008094dc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7043"            ,	   0x118008094dc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7044"            ,	   0x118008094dc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7045"            ,	   0x118008094dc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7046"            ,	   0x118008094dc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7047"            ,	   0x118008094dc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7048"            ,	   0x118008094dc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7049"            ,	   0x118008094dc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7050"            ,	   0x118008094dc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7051"            ,	   0x118008094dc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7052"            ,	   0x118008094dc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7053"            ,	   0x118008094dc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7054"            ,	   0x118008094dc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7055"            ,	   0x118008094dc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7056"            ,	   0x118008094dc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7057"            ,	   0x118008094dc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7058"            ,	   0x118008094dc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7059"            ,	   0x118008094dc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7060"            ,	   0x118008094dca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7061"            ,	   0x118008094dca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7062"            ,	   0x118008094dcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7063"            ,	   0x118008094dcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7064"            ,	   0x118008094dcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7065"            ,	   0x118008094dcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7066"            ,	   0x118008094dcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7067"            ,	   0x118008094dcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7068"            ,	   0x118008094dce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7069"            ,	   0x118008094dce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7070"            ,	   0x118008094dcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7071"            ,	   0x118008094dcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7072"            ,	   0x118008094dd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7073"            ,	   0x118008094dd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7074"            ,	   0x118008094dd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7075"            ,	   0x118008094dd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7076"            ,	   0x118008094dd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7077"            ,	   0x118008094dd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7078"            ,	   0x118008094dd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7079"            ,	   0x118008094dd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7080"            ,	   0x118008094dd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7081"            ,	   0x118008094dd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7082"            ,	   0x118008094dd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7083"            ,	   0x118008094dd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7084"            ,	   0x118008094dd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7085"            ,	   0x118008094dd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7086"            ,	   0x118008094dd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7087"            ,	   0x118008094dd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7088"            ,	   0x118008094dd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7089"            ,	   0x118008094dd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7090"            ,	   0x118008094dd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7091"            ,	   0x118008094dd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7092"            ,	   0x118008094dda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7093"            ,	   0x118008094dda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7094"            ,	   0x118008094ddb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7095"            ,	   0x118008094ddb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7096"            ,	   0x118008094ddc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7097"            ,	   0x118008094ddc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7098"            ,	   0x118008094ddd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7099"            ,	   0x118008094ddd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7100"            ,	   0x118008094dde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7101"            ,	   0x118008094dde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7102"            ,	   0x118008094ddf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7103"            ,	   0x118008094ddf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7104"            ,	   0x118008094de00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7105"            ,	   0x118008094de08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7106"            ,	   0x118008094de10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7107"            ,	   0x118008094de18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7108"            ,	   0x118008094de20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7109"            ,	   0x118008094de28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7110"            ,	   0x118008094de30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7111"            ,	   0x118008094de38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7112"            ,	   0x118008094de40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7113"            ,	   0x118008094de48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7114"            ,	   0x118008094de50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7115"            ,	   0x118008094de58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7116"            ,	   0x118008094de60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7117"            ,	   0x118008094de68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7118"            ,	   0x118008094de70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7119"            ,	   0x118008094de78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7120"            ,	   0x118008094de80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7121"            ,	   0x118008094de88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7122"            ,	   0x118008094de90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7123"            ,	   0x118008094de98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7124"            ,	   0x118008094dea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7125"            ,	   0x118008094dea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7126"            ,	   0x118008094deb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7127"            ,	   0x118008094deb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7128"            ,	   0x118008094dec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7129"            ,	   0x118008094dec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7130"            ,	   0x118008094ded0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7131"            ,	   0x118008094ded8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7132"            ,	   0x118008094dee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7133"            ,	   0x118008094dee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7134"            ,	   0x118008094def0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7135"            ,	   0x118008094def8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7136"            ,	   0x118008094df00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7137"            ,	   0x118008094df08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7138"            ,	   0x118008094df10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7139"            ,	   0x118008094df18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7140"            ,	   0x118008094df20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7141"            ,	   0x118008094df28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7142"            ,	   0x118008094df30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7143"            ,	   0x118008094df38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7144"            ,	   0x118008094df40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7145"            ,	   0x118008094df48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7146"            ,	   0x118008094df50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7147"            ,	   0x118008094df58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7148"            ,	   0x118008094df60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7149"            ,	   0x118008094df68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7150"            ,	   0x118008094df70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7151"            ,	   0x118008094df78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7152"            ,	   0x118008094df80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7153"            ,	   0x118008094df88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7154"            ,	   0x118008094df90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7155"            ,	   0x118008094df98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7156"            ,	   0x118008094dfa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7157"            ,	   0x118008094dfa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7158"            ,	   0x118008094dfb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7159"            ,	   0x118008094dfb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7160"            ,	   0x118008094dfc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7161"            ,	   0x118008094dfc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7162"            ,	   0x118008094dfd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7163"            ,	   0x118008094dfd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7164"            ,	   0x118008094dfe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7165"            ,	   0x118008094dfe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7166"            ,	   0x118008094dff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7167"            ,	   0x118008094dff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7168"            ,	   0x118008094e000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7169"            ,	   0x118008094e008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7170"            ,	   0x118008094e010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7171"            ,	   0x118008094e018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7172"            ,	   0x118008094e020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7173"            ,	   0x118008094e028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7174"            ,	   0x118008094e030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7175"            ,	   0x118008094e038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7176"            ,	   0x118008094e040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7177"            ,	   0x118008094e048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7178"            ,	   0x118008094e050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7179"            ,	   0x118008094e058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7180"            ,	   0x118008094e060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7181"            ,	   0x118008094e068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7182"            ,	   0x118008094e070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7183"            ,	   0x118008094e078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7184"            ,	   0x118008094e080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7185"            ,	   0x118008094e088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7186"            ,	   0x118008094e090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7187"            ,	   0x118008094e098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7188"            ,	   0x118008094e0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7189"            ,	   0x118008094e0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7190"            ,	   0x118008094e0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7191"            ,	   0x118008094e0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7192"            ,	   0x118008094e0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7193"            ,	   0x118008094e0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7194"            ,	   0x118008094e0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7195"            ,	   0x118008094e0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7196"            ,	   0x118008094e0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7197"            ,	   0x118008094e0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7198"            ,	   0x118008094e0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7199"            ,	   0x118008094e0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7200"            ,	   0x118008094e100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7201"            ,	   0x118008094e108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7202"            ,	   0x118008094e110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7203"            ,	   0x118008094e118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7204"            ,	   0x118008094e120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7205"            ,	   0x118008094e128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7206"            ,	   0x118008094e130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7207"            ,	   0x118008094e138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7208"            ,	   0x118008094e140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7209"            ,	   0x118008094e148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7210"            ,	   0x118008094e150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7211"            ,	   0x118008094e158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7212"            ,	   0x118008094e160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7213"            ,	   0x118008094e168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7214"            ,	   0x118008094e170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7215"            ,	   0x118008094e178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7216"            ,	   0x118008094e180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7217"            ,	   0x118008094e188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7218"            ,	   0x118008094e190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7219"            ,	   0x118008094e198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7220"            ,	   0x118008094e1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7221"            ,	   0x118008094e1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7222"            ,	   0x118008094e1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7223"            ,	   0x118008094e1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7224"            ,	   0x118008094e1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7225"            ,	   0x118008094e1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7226"            ,	   0x118008094e1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7227"            ,	   0x118008094e1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7228"            ,	   0x118008094e1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7229"            ,	   0x118008094e1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7230"            ,	   0x118008094e1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7231"            ,	   0x118008094e1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7232"            ,	   0x118008094e200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7233"            ,	   0x118008094e208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7234"            ,	   0x118008094e210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7235"            ,	   0x118008094e218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7236"            ,	   0x118008094e220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7237"            ,	   0x118008094e228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7238"            ,	   0x118008094e230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7239"            ,	   0x118008094e238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7240"            ,	   0x118008094e240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7241"            ,	   0x118008094e248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7242"            ,	   0x118008094e250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7243"            ,	   0x118008094e258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7244"            ,	   0x118008094e260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7245"            ,	   0x118008094e268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7246"            ,	   0x118008094e270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7247"            ,	   0x118008094e278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7248"            ,	   0x118008094e280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7249"            ,	   0x118008094e288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7250"            ,	   0x118008094e290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7251"            ,	   0x118008094e298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7252"            ,	   0x118008094e2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7253"            ,	   0x118008094e2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7254"            ,	   0x118008094e2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7255"            ,	   0x118008094e2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7256"            ,	   0x118008094e2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7257"            ,	   0x118008094e2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7258"            ,	   0x118008094e2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7259"            ,	   0x118008094e2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7260"            ,	   0x118008094e2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7261"            ,	   0x118008094e2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7262"            ,	   0x118008094e2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7263"            ,	   0x118008094e2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7264"            ,	   0x118008094e300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7265"            ,	   0x118008094e308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7266"            ,	   0x118008094e310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7267"            ,	   0x118008094e318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7268"            ,	   0x118008094e320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7269"            ,	   0x118008094e328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7270"            ,	   0x118008094e330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7271"            ,	   0x118008094e338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7272"            ,	   0x118008094e340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7273"            ,	   0x118008094e348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7274"            ,	   0x118008094e350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7275"            ,	   0x118008094e358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7276"            ,	   0x118008094e360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7277"            ,	   0x118008094e368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7278"            ,	   0x118008094e370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7279"            ,	   0x118008094e378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7280"            ,	   0x118008094e380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7281"            ,	   0x118008094e388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7282"            ,	   0x118008094e390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7283"            ,	   0x118008094e398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7284"            ,	   0x118008094e3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7285"            ,	   0x118008094e3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7286"            ,	   0x118008094e3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7287"            ,	   0x118008094e3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7288"            ,	   0x118008094e3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7289"            ,	   0x118008094e3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7290"            ,	   0x118008094e3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7291"            ,	   0x118008094e3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7292"            ,	   0x118008094e3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7293"            ,	   0x118008094e3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7294"            ,	   0x118008094e3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7295"            ,	   0x118008094e3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7296"            ,	   0x118008094e400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7297"            ,	   0x118008094e408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7298"            ,	   0x118008094e410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7299"            ,	   0x118008094e418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7300"            ,	   0x118008094e420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7301"            ,	   0x118008094e428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7302"            ,	   0x118008094e430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7303"            ,	   0x118008094e438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7304"            ,	   0x118008094e440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7305"            ,	   0x118008094e448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7306"            ,	   0x118008094e450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7307"            ,	   0x118008094e458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7308"            ,	   0x118008094e460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7309"            ,	   0x118008094e468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7310"            ,	   0x118008094e470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7311"            ,	   0x118008094e478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7312"            ,	   0x118008094e480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7313"            ,	   0x118008094e488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7314"            ,	   0x118008094e490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7315"            ,	   0x118008094e498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7316"            ,	   0x118008094e4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7317"            ,	   0x118008094e4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7318"            ,	   0x118008094e4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7319"            ,	   0x118008094e4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7320"            ,	   0x118008094e4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7321"            ,	   0x118008094e4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7322"            ,	   0x118008094e4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7323"            ,	   0x118008094e4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7324"            ,	   0x118008094e4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7325"            ,	   0x118008094e4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7326"            ,	   0x118008094e4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7327"            ,	   0x118008094e4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7328"            ,	   0x118008094e500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7329"            ,	   0x118008094e508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7330"            ,	   0x118008094e510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7331"            ,	   0x118008094e518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7332"            ,	   0x118008094e520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7333"            ,	   0x118008094e528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7334"            ,	   0x118008094e530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7335"            ,	   0x118008094e538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7336"            ,	   0x118008094e540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7337"            ,	   0x118008094e548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7338"            ,	   0x118008094e550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7339"            ,	   0x118008094e558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7340"            ,	   0x118008094e560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7341"            ,	   0x118008094e568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7342"            ,	   0x118008094e570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7343"            ,	   0x118008094e578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7344"            ,	   0x118008094e580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7345"            ,	   0x118008094e588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7346"            ,	   0x118008094e590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7347"            ,	   0x118008094e598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7348"            ,	   0x118008094e5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7349"            ,	   0x118008094e5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7350"            ,	   0x118008094e5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7351"            ,	   0x118008094e5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7352"            ,	   0x118008094e5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7353"            ,	   0x118008094e5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7354"            ,	   0x118008094e5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7355"            ,	   0x118008094e5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7356"            ,	   0x118008094e5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7357"            ,	   0x118008094e5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7358"            ,	   0x118008094e5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7359"            ,	   0x118008094e5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7360"            ,	   0x118008094e600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7361"            ,	   0x118008094e608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7362"            ,	   0x118008094e610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7363"            ,	   0x118008094e618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7364"            ,	   0x118008094e620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7365"            ,	   0x118008094e628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7366"            ,	   0x118008094e630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7367"            ,	   0x118008094e638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7368"            ,	   0x118008094e640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7369"            ,	   0x118008094e648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7370"            ,	   0x118008094e650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7371"            ,	   0x118008094e658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7372"            ,	   0x118008094e660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7373"            ,	   0x118008094e668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7374"            ,	   0x118008094e670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7375"            ,	   0x118008094e678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7376"            ,	   0x118008094e680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7377"            ,	   0x118008094e688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7378"            ,	   0x118008094e690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7379"            ,	   0x118008094e698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7380"            ,	   0x118008094e6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7381"            ,	   0x118008094e6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7382"            ,	   0x118008094e6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7383"            ,	   0x118008094e6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7384"            ,	   0x118008094e6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7385"            ,	   0x118008094e6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7386"            ,	   0x118008094e6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7387"            ,	   0x118008094e6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7388"            ,	   0x118008094e6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7389"            ,	   0x118008094e6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7390"            ,	   0x118008094e6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7391"            ,	   0x118008094e6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7392"            ,	   0x118008094e700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7393"            ,	   0x118008094e708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7394"            ,	   0x118008094e710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7395"            ,	   0x118008094e718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7396"            ,	   0x118008094e720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7397"            ,	   0x118008094e728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7398"            ,	   0x118008094e730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7399"            ,	   0x118008094e738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7400"            ,	   0x118008094e740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7401"            ,	   0x118008094e748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7402"            ,	   0x118008094e750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7403"            ,	   0x118008094e758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7404"            ,	   0x118008094e760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7405"            ,	   0x118008094e768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7406"            ,	   0x118008094e770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7407"            ,	   0x118008094e778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7408"            ,	   0x118008094e780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7409"            ,	   0x118008094e788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7410"            ,	   0x118008094e790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7411"            ,	   0x118008094e798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7412"            ,	   0x118008094e7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7413"            ,	   0x118008094e7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7414"            ,	   0x118008094e7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7415"            ,	   0x118008094e7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7416"            ,	   0x118008094e7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7417"            ,	   0x118008094e7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7418"            ,	   0x118008094e7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7419"            ,	   0x118008094e7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7420"            ,	   0x118008094e7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7421"            ,	   0x118008094e7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7422"            ,	   0x118008094e7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7423"            ,	   0x118008094e7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7424"            ,	   0x118008094e800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7425"            ,	   0x118008094e808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7426"            ,	   0x118008094e810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7427"            ,	   0x118008094e818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7428"            ,	   0x118008094e820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7429"            ,	   0x118008094e828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7430"            ,	   0x118008094e830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7431"            ,	   0x118008094e838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7432"            ,	   0x118008094e840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7433"            ,	   0x118008094e848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7434"            ,	   0x118008094e850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7435"            ,	   0x118008094e858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7436"            ,	   0x118008094e860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7437"            ,	   0x118008094e868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7438"            ,	   0x118008094e870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7439"            ,	   0x118008094e878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7440"            ,	   0x118008094e880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7441"            ,	   0x118008094e888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7442"            ,	   0x118008094e890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7443"            ,	   0x118008094e898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7444"            ,	   0x118008094e8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7445"            ,	   0x118008094e8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7446"            ,	   0x118008094e8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7447"            ,	   0x118008094e8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7448"            ,	   0x118008094e8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7449"            ,	   0x118008094e8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7450"            ,	   0x118008094e8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7451"            ,	   0x118008094e8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7452"            ,	   0x118008094e8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7453"            ,	   0x118008094e8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7454"            ,	   0x118008094e8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7455"            ,	   0x118008094e8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7456"            ,	   0x118008094e900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7457"            ,	   0x118008094e908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7458"            ,	   0x118008094e910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7459"            ,	   0x118008094e918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7460"            ,	   0x118008094e920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7461"            ,	   0x118008094e928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7462"            ,	   0x118008094e930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7463"            ,	   0x118008094e938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7464"            ,	   0x118008094e940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7465"            ,	   0x118008094e948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7466"            ,	   0x118008094e950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7467"            ,	   0x118008094e958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7468"            ,	   0x118008094e960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7469"            ,	   0x118008094e968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7470"            ,	   0x118008094e970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7471"            ,	   0x118008094e978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7472"            ,	   0x118008094e980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7473"            ,	   0x118008094e988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7474"            ,	   0x118008094e990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7475"            ,	   0x118008094e998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7476"            ,	   0x118008094e9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7477"            ,	   0x118008094e9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7478"            ,	   0x118008094e9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7479"            ,	   0x118008094e9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7480"            ,	   0x118008094e9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7481"            ,	   0x118008094e9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7482"            ,	   0x118008094e9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7483"            ,	   0x118008094e9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7484"            ,	   0x118008094e9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7485"            ,	   0x118008094e9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7486"            ,	   0x118008094e9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7487"            ,	   0x118008094e9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7488"            ,	   0x118008094ea00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7489"            ,	   0x118008094ea08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7490"            ,	   0x118008094ea10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7491"            ,	   0x118008094ea18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7492"            ,	   0x118008094ea20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7493"            ,	   0x118008094ea28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7494"            ,	   0x118008094ea30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7495"            ,	   0x118008094ea38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7496"            ,	   0x118008094ea40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7497"            ,	   0x118008094ea48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7498"            ,	   0x118008094ea50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7499"            ,	   0x118008094ea58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7500"            ,	   0x118008094ea60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7501"            ,	   0x118008094ea68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7502"            ,	   0x118008094ea70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7503"            ,	   0x118008094ea78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7504"            ,	   0x118008094ea80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7505"            ,	   0x118008094ea88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7506"            ,	   0x118008094ea90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7507"            ,	   0x118008094ea98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7508"            ,	   0x118008094eaa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7509"            ,	   0x118008094eaa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7510"            ,	   0x118008094eab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7511"            ,	   0x118008094eab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7512"            ,	   0x118008094eac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7513"            ,	   0x118008094eac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7514"            ,	   0x118008094ead0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7515"            ,	   0x118008094ead8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7516"            ,	   0x118008094eae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7517"            ,	   0x118008094eae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7518"            ,	   0x118008094eaf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7519"            ,	   0x118008094eaf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7520"            ,	   0x118008094eb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7521"            ,	   0x118008094eb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7522"            ,	   0x118008094eb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7523"            ,	   0x118008094eb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7524"            ,	   0x118008094eb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7525"            ,	   0x118008094eb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7526"            ,	   0x118008094eb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7527"            ,	   0x118008094eb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7528"            ,	   0x118008094eb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7529"            ,	   0x118008094eb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7530"            ,	   0x118008094eb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7531"            ,	   0x118008094eb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7532"            ,	   0x118008094eb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7533"            ,	   0x118008094eb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7534"            ,	   0x118008094eb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7535"            ,	   0x118008094eb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7536"            ,	   0x118008094eb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7537"            ,	   0x118008094eb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7538"            ,	   0x118008094eb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7539"            ,	   0x118008094eb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7540"            ,	   0x118008094eba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7541"            ,	   0x118008094eba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7542"            ,	   0x118008094ebb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7543"            ,	   0x118008094ebb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7544"            ,	   0x118008094ebc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7545"            ,	   0x118008094ebc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7546"            ,	   0x118008094ebd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7547"            ,	   0x118008094ebd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7548"            ,	   0x118008094ebe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7549"            ,	   0x118008094ebe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7550"            ,	   0x118008094ebf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7551"            ,	   0x118008094ebf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7552"            ,	   0x118008094ec00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7553"            ,	   0x118008094ec08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7554"            ,	   0x118008094ec10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7555"            ,	   0x118008094ec18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7556"            ,	   0x118008094ec20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7557"            ,	   0x118008094ec28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7558"            ,	   0x118008094ec30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7559"            ,	   0x118008094ec38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7560"            ,	   0x118008094ec40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7561"            ,	   0x118008094ec48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7562"            ,	   0x118008094ec50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7563"            ,	   0x118008094ec58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7564"            ,	   0x118008094ec60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7565"            ,	   0x118008094ec68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7566"            ,	   0x118008094ec70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7567"            ,	   0x118008094ec78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7568"            ,	   0x118008094ec80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7569"            ,	   0x118008094ec88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7570"            ,	   0x118008094ec90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7571"            ,	   0x118008094ec98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7572"            ,	   0x118008094eca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7573"            ,	   0x118008094eca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7574"            ,	   0x118008094ecb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7575"            ,	   0x118008094ecb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7576"            ,	   0x118008094ecc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7577"            ,	   0x118008094ecc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7578"            ,	   0x118008094ecd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7579"            ,	   0x118008094ecd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7580"            ,	   0x118008094ece0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7581"            ,	   0x118008094ece8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7582"            ,	   0x118008094ecf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7583"            ,	   0x118008094ecf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7584"            ,	   0x118008094ed00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7585"            ,	   0x118008094ed08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7586"            ,	   0x118008094ed10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7587"            ,	   0x118008094ed18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7588"            ,	   0x118008094ed20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7589"            ,	   0x118008094ed28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7590"            ,	   0x118008094ed30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7591"            ,	   0x118008094ed38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7592"            ,	   0x118008094ed40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7593"            ,	   0x118008094ed48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7594"            ,	   0x118008094ed50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7595"            ,	   0x118008094ed58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7596"            ,	   0x118008094ed60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7597"            ,	   0x118008094ed68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7598"            ,	   0x118008094ed70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7599"            ,	   0x118008094ed78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7600"            ,	   0x118008094ed80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7601"            ,	   0x118008094ed88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7602"            ,	   0x118008094ed90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7603"            ,	   0x118008094ed98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7604"            ,	   0x118008094eda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7605"            ,	   0x118008094eda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7606"            ,	   0x118008094edb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7607"            ,	   0x118008094edb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7608"            ,	   0x118008094edc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7609"            ,	   0x118008094edc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7610"            ,	   0x118008094edd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7611"            ,	   0x118008094edd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7612"            ,	   0x118008094ede0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7613"            ,	   0x118008094ede8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7614"            ,	   0x118008094edf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7615"            ,	   0x118008094edf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7616"            ,	   0x118008094ee00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7617"            ,	   0x118008094ee08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7618"            ,	   0x118008094ee10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7619"            ,	   0x118008094ee18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7620"            ,	   0x118008094ee20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7621"            ,	   0x118008094ee28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7622"            ,	   0x118008094ee30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7623"            ,	   0x118008094ee38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7624"            ,	   0x118008094ee40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7625"            ,	   0x118008094ee48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7626"            ,	   0x118008094ee50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7627"            ,	   0x118008094ee58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7628"            ,	   0x118008094ee60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7629"            ,	   0x118008094ee68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7630"            ,	   0x118008094ee70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7631"            ,	   0x118008094ee78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7632"            ,	   0x118008094ee80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7633"            ,	   0x118008094ee88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7634"            ,	   0x118008094ee90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7635"            ,	   0x118008094ee98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7636"            ,	   0x118008094eea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7637"            ,	   0x118008094eea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7638"            ,	   0x118008094eeb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7639"            ,	   0x118008094eeb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7640"            ,	   0x118008094eec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7641"            ,	   0x118008094eec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7642"            ,	   0x118008094eed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7643"            ,	   0x118008094eed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7644"            ,	   0x118008094eee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7645"            ,	   0x118008094eee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7646"            ,	   0x118008094eef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7647"            ,	   0x118008094eef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7648"            ,	   0x118008094ef00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7649"            ,	   0x118008094ef08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7650"            ,	   0x118008094ef10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7651"            ,	   0x118008094ef18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7652"            ,	   0x118008094ef20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7653"            ,	   0x118008094ef28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7654"            ,	   0x118008094ef30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7655"            ,	   0x118008094ef38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7656"            ,	   0x118008094ef40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7657"            ,	   0x118008094ef48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7658"            ,	   0x118008094ef50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7659"            ,	   0x118008094ef58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7660"            ,	   0x118008094ef60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7661"            ,	   0x118008094ef68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7662"            ,	   0x118008094ef70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7663"            ,	   0x118008094ef78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7664"            ,	   0x118008094ef80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7665"            ,	   0x118008094ef88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7666"            ,	   0x118008094ef90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7667"            ,	   0x118008094ef98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7668"            ,	   0x118008094efa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7669"            ,	   0x118008094efa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7670"            ,	   0x118008094efb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7671"            ,	   0x118008094efb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7672"            ,	   0x118008094efc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7673"            ,	   0x118008094efc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7674"            ,	   0x118008094efd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7675"            ,	   0x118008094efd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7676"            ,	   0x118008094efe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7677"            ,	   0x118008094efe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7678"            ,	   0x118008094eff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7679"            ,	   0x118008094eff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7680"            ,	   0x118008094f000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7681"            ,	   0x118008094f008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7682"            ,	   0x118008094f010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7683"            ,	   0x118008094f018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7684"            ,	   0x118008094f020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7685"            ,	   0x118008094f028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7686"            ,	   0x118008094f030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7687"            ,	   0x118008094f038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7688"            ,	   0x118008094f040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7689"            ,	   0x118008094f048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7690"            ,	   0x118008094f050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7691"            ,	   0x118008094f058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7692"            ,	   0x118008094f060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7693"            ,	   0x118008094f068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7694"            ,	   0x118008094f070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7695"            ,	   0x118008094f078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7696"            ,	   0x118008094f080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7697"            ,	   0x118008094f088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7698"            ,	   0x118008094f090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7699"            ,	   0x118008094f098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7700"            ,	   0x118008094f0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7701"            ,	   0x118008094f0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7702"            ,	   0x118008094f0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7703"            ,	   0x118008094f0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7704"            ,	   0x118008094f0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7705"            ,	   0x118008094f0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7706"            ,	   0x118008094f0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7707"            ,	   0x118008094f0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7708"            ,	   0x118008094f0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7709"            ,	   0x118008094f0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7710"            ,	   0x118008094f0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7711"            ,	   0x118008094f0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7712"            ,	   0x118008094f100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7713"            ,	   0x118008094f108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7714"            ,	   0x118008094f110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7715"            ,	   0x118008094f118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7716"            ,	   0x118008094f120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7717"            ,	   0x118008094f128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7718"            ,	   0x118008094f130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7719"            ,	   0x118008094f138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7720"            ,	   0x118008094f140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7721"            ,	   0x118008094f148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7722"            ,	   0x118008094f150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7723"            ,	   0x118008094f158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7724"            ,	   0x118008094f160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7725"            ,	   0x118008094f168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7726"            ,	   0x118008094f170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7727"            ,	   0x118008094f178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7728"            ,	   0x118008094f180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7729"            ,	   0x118008094f188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7730"            ,	   0x118008094f190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7731"            ,	   0x118008094f198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7732"            ,	   0x118008094f1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7733"            ,	   0x118008094f1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7734"            ,	   0x118008094f1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7735"            ,	   0x118008094f1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7736"            ,	   0x118008094f1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7737"            ,	   0x118008094f1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7738"            ,	   0x118008094f1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7739"            ,	   0x118008094f1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7740"            ,	   0x118008094f1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7741"            ,	   0x118008094f1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7742"            ,	   0x118008094f1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7743"            ,	   0x118008094f1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7744"            ,	   0x118008094f200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7745"            ,	   0x118008094f208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7746"            ,	   0x118008094f210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7747"            ,	   0x118008094f218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7748"            ,	   0x118008094f220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7749"            ,	   0x118008094f228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7750"            ,	   0x118008094f230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7751"            ,	   0x118008094f238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7752"            ,	   0x118008094f240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7753"            ,	   0x118008094f248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7754"            ,	   0x118008094f250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7755"            ,	   0x118008094f258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7756"            ,	   0x118008094f260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7757"            ,	   0x118008094f268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7758"            ,	   0x118008094f270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7759"            ,	   0x118008094f278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7760"            ,	   0x118008094f280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7761"            ,	   0x118008094f288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7762"            ,	   0x118008094f290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7763"            ,	   0x118008094f298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7764"            ,	   0x118008094f2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7765"            ,	   0x118008094f2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7766"            ,	   0x118008094f2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7767"            ,	   0x118008094f2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7768"            ,	   0x118008094f2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7769"            ,	   0x118008094f2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7770"            ,	   0x118008094f2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7771"            ,	   0x118008094f2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7772"            ,	   0x118008094f2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7773"            ,	   0x118008094f2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7774"            ,	   0x118008094f2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7775"            ,	   0x118008094f2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7776"            ,	   0x118008094f300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7777"            ,	   0x118008094f308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7778"            ,	   0x118008094f310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7779"            ,	   0x118008094f318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7780"            ,	   0x118008094f320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7781"            ,	   0x118008094f328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7782"            ,	   0x118008094f330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7783"            ,	   0x118008094f338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7784"            ,	   0x118008094f340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7785"            ,	   0x118008094f348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7786"            ,	   0x118008094f350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7787"            ,	   0x118008094f358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7788"            ,	   0x118008094f360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7789"            ,	   0x118008094f368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7790"            ,	   0x118008094f370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7791"            ,	   0x118008094f378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7792"            ,	   0x118008094f380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7793"            ,	   0x118008094f388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7794"            ,	   0x118008094f390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7795"            ,	   0x118008094f398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7796"            ,	   0x118008094f3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7797"            ,	   0x118008094f3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7798"            ,	   0x118008094f3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7799"            ,	   0x118008094f3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7800"            ,	   0x118008094f3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7801"            ,	   0x118008094f3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7802"            ,	   0x118008094f3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7803"            ,	   0x118008094f3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7804"            ,	   0x118008094f3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7805"            ,	   0x118008094f3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7806"            ,	   0x118008094f3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7807"            ,	   0x118008094f3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7808"            ,	   0x118008094f400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7809"            ,	   0x118008094f408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7810"            ,	   0x118008094f410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7811"            ,	   0x118008094f418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7812"            ,	   0x118008094f420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7813"            ,	   0x118008094f428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7814"            ,	   0x118008094f430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7815"            ,	   0x118008094f438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7816"            ,	   0x118008094f440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7817"            ,	   0x118008094f448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7818"            ,	   0x118008094f450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7819"            ,	   0x118008094f458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7820"            ,	   0x118008094f460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7821"            ,	   0x118008094f468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7822"            ,	   0x118008094f470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7823"            ,	   0x118008094f478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7824"            ,	   0x118008094f480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7825"            ,	   0x118008094f488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7826"            ,	   0x118008094f490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7827"            ,	   0x118008094f498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7828"            ,	   0x118008094f4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7829"            ,	   0x118008094f4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7830"            ,	   0x118008094f4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7831"            ,	   0x118008094f4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7832"            ,	   0x118008094f4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7833"            ,	   0x118008094f4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7834"            ,	   0x118008094f4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7835"            ,	   0x118008094f4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7836"            ,	   0x118008094f4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7837"            ,	   0x118008094f4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7838"            ,	   0x118008094f4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7839"            ,	   0x118008094f4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7840"            ,	   0x118008094f500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7841"            ,	   0x118008094f508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7842"            ,	   0x118008094f510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7843"            ,	   0x118008094f518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7844"            ,	   0x118008094f520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7845"            ,	   0x118008094f528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7846"            ,	   0x118008094f530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7847"            ,	   0x118008094f538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7848"            ,	   0x118008094f540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7849"            ,	   0x118008094f548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7850"            ,	   0x118008094f550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7851"            ,	   0x118008094f558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7852"            ,	   0x118008094f560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7853"            ,	   0x118008094f568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7854"            ,	   0x118008094f570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7855"            ,	   0x118008094f578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7856"            ,	   0x118008094f580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7857"            ,	   0x118008094f588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7858"            ,	   0x118008094f590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7859"            ,	   0x118008094f598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7860"            ,	   0x118008094f5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7861"            ,	   0x118008094f5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7862"            ,	   0x118008094f5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7863"            ,	   0x118008094f5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7864"            ,	   0x118008094f5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7865"            ,	   0x118008094f5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7866"            ,	   0x118008094f5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7867"            ,	   0x118008094f5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7868"            ,	   0x118008094f5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7869"            ,	   0x118008094f5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7870"            ,	   0x118008094f5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7871"            ,	   0x118008094f5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7872"            ,	   0x118008094f600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7873"            ,	   0x118008094f608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7874"            ,	   0x118008094f610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7875"            ,	   0x118008094f618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7876"            ,	   0x118008094f620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7877"            ,	   0x118008094f628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7878"            ,	   0x118008094f630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7879"            ,	   0x118008094f638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7880"            ,	   0x118008094f640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7881"            ,	   0x118008094f648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7882"            ,	   0x118008094f650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7883"            ,	   0x118008094f658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7884"            ,	   0x118008094f660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7885"            ,	   0x118008094f668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7886"            ,	   0x118008094f670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7887"            ,	   0x118008094f678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7888"            ,	   0x118008094f680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7889"            ,	   0x118008094f688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7890"            ,	   0x118008094f690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7891"            ,	   0x118008094f698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7892"            ,	   0x118008094f6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7893"            ,	   0x118008094f6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7894"            ,	   0x118008094f6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7895"            ,	   0x118008094f6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7896"            ,	   0x118008094f6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7897"            ,	   0x118008094f6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7898"            ,	   0x118008094f6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7899"            ,	   0x118008094f6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7900"            ,	   0x118008094f6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7901"            ,	   0x118008094f6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7902"            ,	   0x118008094f6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7903"            ,	   0x118008094f6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7904"            ,	   0x118008094f700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7905"            ,	   0x118008094f708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7906"            ,	   0x118008094f710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7907"            ,	   0x118008094f718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7908"            ,	   0x118008094f720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7909"            ,	   0x118008094f728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7910"            ,	   0x118008094f730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7911"            ,	   0x118008094f738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7912"            ,	   0x118008094f740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7913"            ,	   0x118008094f748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7914"            ,	   0x118008094f750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7915"            ,	   0x118008094f758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7916"            ,	   0x118008094f760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7917"            ,	   0x118008094f768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7918"            ,	   0x118008094f770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7919"            ,	   0x118008094f778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7920"            ,	   0x118008094f780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7921"            ,	   0x118008094f788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7922"            ,	   0x118008094f790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7923"            ,	   0x118008094f798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7924"            ,	   0x118008094f7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7925"            ,	   0x118008094f7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7926"            ,	   0x118008094f7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7927"            ,	   0x118008094f7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7928"            ,	   0x118008094f7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7929"            ,	   0x118008094f7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7930"            ,	   0x118008094f7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7931"            ,	   0x118008094f7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7932"            ,	   0x118008094f7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7933"            ,	   0x118008094f7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7934"            ,	   0x118008094f7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7935"            ,	   0x118008094f7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7936"            ,	   0x118008094f800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7937"            ,	   0x118008094f808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7938"            ,	   0x118008094f810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7939"            ,	   0x118008094f818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7940"            ,	   0x118008094f820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7941"            ,	   0x118008094f828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7942"            ,	   0x118008094f830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7943"            ,	   0x118008094f838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7944"            ,	   0x118008094f840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7945"            ,	   0x118008094f848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7946"            ,	   0x118008094f850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7947"            ,	   0x118008094f858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7948"            ,	   0x118008094f860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7949"            ,	   0x118008094f868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7950"            ,	   0x118008094f870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7951"            ,	   0x118008094f878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7952"            ,	   0x118008094f880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7953"            ,	   0x118008094f888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7954"            ,	   0x118008094f890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7955"            ,	   0x118008094f898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7956"            ,	   0x118008094f8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7957"            ,	   0x118008094f8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7958"            ,	   0x118008094f8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7959"            ,	   0x118008094f8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7960"            ,	   0x118008094f8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7961"            ,	   0x118008094f8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7962"            ,	   0x118008094f8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7963"            ,	   0x118008094f8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7964"            ,	   0x118008094f8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7965"            ,	   0x118008094f8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7966"            ,	   0x118008094f8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7967"            ,	   0x118008094f8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7968"            ,	   0x118008094f900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7969"            ,	   0x118008094f908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7970"            ,	   0x118008094f910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7971"            ,	   0x118008094f918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7972"            ,	   0x118008094f920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7973"            ,	   0x118008094f928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7974"            ,	   0x118008094f930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7975"            ,	   0x118008094f938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7976"            ,	   0x118008094f940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7977"            ,	   0x118008094f948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7978"            ,	   0x118008094f950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7979"            ,	   0x118008094f958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7980"            ,	   0x118008094f960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7981"            ,	   0x118008094f968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7982"            ,	   0x118008094f970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7983"            ,	   0x118008094f978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7984"            ,	   0x118008094f980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7985"            ,	   0x118008094f988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7986"            ,	   0x118008094f990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7987"            ,	   0x118008094f998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7988"            ,	   0x118008094f9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7989"            ,	   0x118008094f9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7990"            ,	   0x118008094f9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7991"            ,	   0x118008094f9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7992"            ,	   0x118008094f9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7993"            ,	   0x118008094f9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7994"            ,	   0x118008094f9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7995"            ,	   0x118008094f9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7996"            ,	   0x118008094f9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7997"            ,	   0x118008094f9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7998"            ,	   0x118008094f9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP7999"            ,	   0x118008094f9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8000"            ,	   0x118008094fa00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8001"            ,	   0x118008094fa08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8002"            ,	   0x118008094fa10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8003"            ,	   0x118008094fa18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8004"            ,	   0x118008094fa20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8005"            ,	   0x118008094fa28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8006"            ,	   0x118008094fa30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8007"            ,	   0x118008094fa38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8008"            ,	   0x118008094fa40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8009"            ,	   0x118008094fa48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8010"            ,	   0x118008094fa50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8011"            ,	   0x118008094fa58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8012"            ,	   0x118008094fa60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8013"            ,	   0x118008094fa68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8014"            ,	   0x118008094fa70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8015"            ,	   0x118008094fa78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8016"            ,	   0x118008094fa80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8017"            ,	   0x118008094fa88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8018"            ,	   0x118008094fa90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8019"            ,	   0x118008094fa98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8020"            ,	   0x118008094faa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8021"            ,	   0x118008094faa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8022"            ,	   0x118008094fab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8023"            ,	   0x118008094fab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8024"            ,	   0x118008094fac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8025"            ,	   0x118008094fac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8026"            ,	   0x118008094fad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8027"            ,	   0x118008094fad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8028"            ,	   0x118008094fae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8029"            ,	   0x118008094fae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8030"            ,	   0x118008094faf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8031"            ,	   0x118008094faf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8032"            ,	   0x118008094fb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8033"            ,	   0x118008094fb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8034"            ,	   0x118008094fb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8035"            ,	   0x118008094fb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8036"            ,	   0x118008094fb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8037"            ,	   0x118008094fb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8038"            ,	   0x118008094fb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8039"            ,	   0x118008094fb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8040"            ,	   0x118008094fb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8041"            ,	   0x118008094fb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8042"            ,	   0x118008094fb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8043"            ,	   0x118008094fb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8044"            ,	   0x118008094fb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8045"            ,	   0x118008094fb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8046"            ,	   0x118008094fb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8047"            ,	   0x118008094fb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8048"            ,	   0x118008094fb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8049"            ,	   0x118008094fb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8050"            ,	   0x118008094fb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8051"            ,	   0x118008094fb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8052"            ,	   0x118008094fba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8053"            ,	   0x118008094fba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8054"            ,	   0x118008094fbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8055"            ,	   0x118008094fbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8056"            ,	   0x118008094fbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8057"            ,	   0x118008094fbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8058"            ,	   0x118008094fbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8059"            ,	   0x118008094fbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8060"            ,	   0x118008094fbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8061"            ,	   0x118008094fbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8062"            ,	   0x118008094fbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8063"            ,	   0x118008094fbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8064"            ,	   0x118008094fc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8065"            ,	   0x118008094fc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8066"            ,	   0x118008094fc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8067"            ,	   0x118008094fc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8068"            ,	   0x118008094fc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8069"            ,	   0x118008094fc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8070"            ,	   0x118008094fc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8071"            ,	   0x118008094fc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8072"            ,	   0x118008094fc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8073"            ,	   0x118008094fc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8074"            ,	   0x118008094fc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8075"            ,	   0x118008094fc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8076"            ,	   0x118008094fc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8077"            ,	   0x118008094fc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8078"            ,	   0x118008094fc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8079"            ,	   0x118008094fc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8080"            ,	   0x118008094fc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8081"            ,	   0x118008094fc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8082"            ,	   0x118008094fc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8083"            ,	   0x118008094fc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8084"            ,	   0x118008094fca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8085"            ,	   0x118008094fca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8086"            ,	   0x118008094fcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8087"            ,	   0x118008094fcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8088"            ,	   0x118008094fcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8089"            ,	   0x118008094fcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8090"            ,	   0x118008094fcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8091"            ,	   0x118008094fcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8092"            ,	   0x118008094fce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8093"            ,	   0x118008094fce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8094"            ,	   0x118008094fcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8095"            ,	   0x118008094fcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8096"            ,	   0x118008094fd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8097"            ,	   0x118008094fd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8098"            ,	   0x118008094fd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8099"            ,	   0x118008094fd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8100"            ,	   0x118008094fd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8101"            ,	   0x118008094fd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8102"            ,	   0x118008094fd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8103"            ,	   0x118008094fd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8104"            ,	   0x118008094fd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8105"            ,	   0x118008094fd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8106"            ,	   0x118008094fd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8107"            ,	   0x118008094fd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8108"            ,	   0x118008094fd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8109"            ,	   0x118008094fd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8110"            ,	   0x118008094fd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8111"            ,	   0x118008094fd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8112"            ,	   0x118008094fd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8113"            ,	   0x118008094fd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8114"            ,	   0x118008094fd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8115"            ,	   0x118008094fd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8116"            ,	   0x118008094fda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8117"            ,	   0x118008094fda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8118"            ,	   0x118008094fdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8119"            ,	   0x118008094fdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8120"            ,	   0x118008094fdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8121"            ,	   0x118008094fdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8122"            ,	   0x118008094fdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8123"            ,	   0x118008094fdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8124"            ,	   0x118008094fde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8125"            ,	   0x118008094fde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8126"            ,	   0x118008094fdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8127"            ,	   0x118008094fdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8128"            ,	   0x118008094fe00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8129"            ,	   0x118008094fe08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8130"            ,	   0x118008094fe10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8131"            ,	   0x118008094fe18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8132"            ,	   0x118008094fe20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8133"            ,	   0x118008094fe28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8134"            ,	   0x118008094fe30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8135"            ,	   0x118008094fe38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8136"            ,	   0x118008094fe40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8137"            ,	   0x118008094fe48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8138"            ,	   0x118008094fe50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8139"            ,	   0x118008094fe58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8140"            ,	   0x118008094fe60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8141"            ,	   0x118008094fe68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8142"            ,	   0x118008094fe70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8143"            ,	   0x118008094fe78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8144"            ,	   0x118008094fe80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8145"            ,	   0x118008094fe88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8146"            ,	   0x118008094fe90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8147"            ,	   0x118008094fe98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8148"            ,	   0x118008094fea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8149"            ,	   0x118008094fea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8150"            ,	   0x118008094feb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8151"            ,	   0x118008094feb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8152"            ,	   0x118008094fec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8153"            ,	   0x118008094fec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8154"            ,	   0x118008094fed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8155"            ,	   0x118008094fed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8156"            ,	   0x118008094fee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8157"            ,	   0x118008094fee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8158"            ,	   0x118008094fef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8159"            ,	   0x118008094fef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8160"            ,	   0x118008094ff00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8161"            ,	   0x118008094ff08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8162"            ,	   0x118008094ff10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8163"            ,	   0x118008094ff18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8164"            ,	   0x118008094ff20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8165"            ,	   0x118008094ff28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8166"            ,	   0x118008094ff30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8167"            ,	   0x118008094ff38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8168"            ,	   0x118008094ff40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8169"            ,	   0x118008094ff48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8170"            ,	   0x118008094ff50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8171"            ,	   0x118008094ff58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8172"            ,	   0x118008094ff60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8173"            ,	   0x118008094ff68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8174"            ,	   0x118008094ff70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8175"            ,	   0x118008094ff78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8176"            ,	   0x118008094ff80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8177"            ,	   0x118008094ff88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8178"            ,	   0x118008094ff90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8179"            ,	   0x118008094ff98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8180"            ,	   0x118008094ffa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8181"            ,	   0x118008094ffa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8182"            ,	   0x118008094ffb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8183"            ,	   0x118008094ffb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8184"            ,	   0x118008094ffc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8185"            ,	   0x118008094ffc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8186"            ,	   0x118008094ffd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8187"            ,	   0x118008094ffd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8188"            ,	   0x118008094ffe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8189"            ,	   0x118008094ffe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8190"            ,	   0x118008094fff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP8191"            ,	   0x118008094fff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16128"           ,	   0x118008095f800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16129"           ,	   0x118008095f808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16130"           ,	   0x118008095f810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16131"           ,	   0x118008095f818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16132"           ,	   0x118008095f820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16133"           ,	   0x118008095f828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16134"           ,	   0x118008095f830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16135"           ,	   0x118008095f838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16136"           ,	   0x118008095f840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16137"           ,	   0x118008095f848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16138"           ,	   0x118008095f850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16139"           ,	   0x118008095f858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16140"           ,	   0x118008095f860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16141"           ,	   0x118008095f868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16142"           ,	   0x118008095f870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16143"           ,	   0x118008095f878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16144"           ,	   0x118008095f880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16145"           ,	   0x118008095f888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16146"           ,	   0x118008095f890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16147"           ,	   0x118008095f898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16148"           ,	   0x118008095f8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16149"           ,	   0x118008095f8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16150"           ,	   0x118008095f8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16151"           ,	   0x118008095f8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16152"           ,	   0x118008095f8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16153"           ,	   0x118008095f8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16154"           ,	   0x118008095f8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16155"           ,	   0x118008095f8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16156"           ,	   0x118008095f8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16157"           ,	   0x118008095f8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16158"           ,	   0x118008095f8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16159"           ,	   0x118008095f8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16160"           ,	   0x118008095f900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16161"           ,	   0x118008095f908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16162"           ,	   0x118008095f910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16163"           ,	   0x118008095f918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16164"           ,	   0x118008095f920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16165"           ,	   0x118008095f928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16166"           ,	   0x118008095f930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16167"           ,	   0x118008095f938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16168"           ,	   0x118008095f940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16169"           ,	   0x118008095f948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16170"           ,	   0x118008095f950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16171"           ,	   0x118008095f958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16172"           ,	   0x118008095f960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16173"           ,	   0x118008095f968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16174"           ,	   0x118008095f970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16175"           ,	   0x118008095f978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16176"           ,	   0x118008095f980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16177"           ,	   0x118008095f988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16178"           ,	   0x118008095f990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16179"           ,	   0x118008095f998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16180"           ,	   0x118008095f9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16181"           ,	   0x118008095f9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16182"           ,	   0x118008095f9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16183"           ,	   0x118008095f9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16184"           ,	   0x118008095f9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16185"           ,	   0x118008095f9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16186"           ,	   0x118008095f9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16187"           ,	   0x118008095f9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16188"           ,	   0x118008095f9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16189"           ,	   0x118008095f9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16190"           ,	   0x118008095f9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16191"           ,	   0x118008095f9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16192"           ,	   0x118008095fa00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16193"           ,	   0x118008095fa08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16194"           ,	   0x118008095fa10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16195"           ,	   0x118008095fa18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16196"           ,	   0x118008095fa20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16197"           ,	   0x118008095fa28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16198"           ,	   0x118008095fa30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16199"           ,	   0x118008095fa38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16200"           ,	   0x118008095fa40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16201"           ,	   0x118008095fa48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16202"           ,	   0x118008095fa50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16203"           ,	   0x118008095fa58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16204"           ,	   0x118008095fa60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16205"           ,	   0x118008095fa68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16206"           ,	   0x118008095fa70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16207"           ,	   0x118008095fa78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16208"           ,	   0x118008095fa80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16209"           ,	   0x118008095fa88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16210"           ,	   0x118008095fa90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16211"           ,	   0x118008095fa98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16212"           ,	   0x118008095faa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16213"           ,	   0x118008095faa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16214"           ,	   0x118008095fab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16215"           ,	   0x118008095fab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16216"           ,	   0x118008095fac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16217"           ,	   0x118008095fac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16218"           ,	   0x118008095fad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16219"           ,	   0x118008095fad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16220"           ,	   0x118008095fae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16221"           ,	   0x118008095fae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16222"           ,	   0x118008095faf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16223"           ,	   0x118008095faf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16224"           ,	   0x118008095fb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16225"           ,	   0x118008095fb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16226"           ,	   0x118008095fb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16227"           ,	   0x118008095fb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16228"           ,	   0x118008095fb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16229"           ,	   0x118008095fb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16230"           ,	   0x118008095fb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16231"           ,	   0x118008095fb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16232"           ,	   0x118008095fb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16233"           ,	   0x118008095fb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16234"           ,	   0x118008095fb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16235"           ,	   0x118008095fb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16236"           ,	   0x118008095fb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16237"           ,	   0x118008095fb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16238"           ,	   0x118008095fb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16239"           ,	   0x118008095fb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16240"           ,	   0x118008095fb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16241"           ,	   0x118008095fb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16242"           ,	   0x118008095fb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16243"           ,	   0x118008095fb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16244"           ,	   0x118008095fba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16245"           ,	   0x118008095fba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16246"           ,	   0x118008095fbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16247"           ,	   0x118008095fbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16248"           ,	   0x118008095fbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16249"           ,	   0x118008095fbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16250"           ,	   0x118008095fbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16251"           ,	   0x118008095fbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16252"           ,	   0x118008095fbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16253"           ,	   0x118008095fbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16254"           ,	   0x118008095fbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16255"           ,	   0x118008095fbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16256"           ,	   0x118008095fc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16257"           ,	   0x118008095fc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16258"           ,	   0x118008095fc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16259"           ,	   0x118008095fc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16260"           ,	   0x118008095fc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16261"           ,	   0x118008095fc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16262"           ,	   0x118008095fc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16263"           ,	   0x118008095fc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16264"           ,	   0x118008095fc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16265"           ,	   0x118008095fc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16266"           ,	   0x118008095fc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16267"           ,	   0x118008095fc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16268"           ,	   0x118008095fc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16269"           ,	   0x118008095fc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16270"           ,	   0x118008095fc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16271"           ,	   0x118008095fc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16272"           ,	   0x118008095fc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16273"           ,	   0x118008095fc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16274"           ,	   0x118008095fc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16275"           ,	   0x118008095fc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16276"           ,	   0x118008095fca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16277"           ,	   0x118008095fca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16278"           ,	   0x118008095fcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16279"           ,	   0x118008095fcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16280"           ,	   0x118008095fcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16281"           ,	   0x118008095fcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16282"           ,	   0x118008095fcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16283"           ,	   0x118008095fcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16284"           ,	   0x118008095fce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16285"           ,	   0x118008095fce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16286"           ,	   0x118008095fcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16287"           ,	   0x118008095fcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16288"           ,	   0x118008095fd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16289"           ,	   0x118008095fd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16290"           ,	   0x118008095fd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16291"           ,	   0x118008095fd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16292"           ,	   0x118008095fd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16293"           ,	   0x118008095fd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16294"           ,	   0x118008095fd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16295"           ,	   0x118008095fd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16296"           ,	   0x118008095fd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16297"           ,	   0x118008095fd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16298"           ,	   0x118008095fd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16299"           ,	   0x118008095fd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16300"           ,	   0x118008095fd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16301"           ,	   0x118008095fd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16302"           ,	   0x118008095fd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16303"           ,	   0x118008095fd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16304"           ,	   0x118008095fd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16305"           ,	   0x118008095fd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16306"           ,	   0x118008095fd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16307"           ,	   0x118008095fd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16308"           ,	   0x118008095fda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16309"           ,	   0x118008095fda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16310"           ,	   0x118008095fdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16311"           ,	   0x118008095fdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16312"           ,	   0x118008095fdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16313"           ,	   0x118008095fdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16314"           ,	   0x118008095fdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16315"           ,	   0x118008095fdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16316"           ,	   0x118008095fde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16317"           ,	   0x118008095fde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16318"           ,	   0x118008095fdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16319"           ,	   0x118008095fdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16320"           ,	   0x118008095fe00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16321"           ,	   0x118008095fe08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16322"           ,	   0x118008095fe10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16323"           ,	   0x118008095fe18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16324"           ,	   0x118008095fe20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16325"           ,	   0x118008095fe28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16326"           ,	   0x118008095fe30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16327"           ,	   0x118008095fe38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16328"           ,	   0x118008095fe40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16329"           ,	   0x118008095fe48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16330"           ,	   0x118008095fe50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16331"           ,	   0x118008095fe58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16332"           ,	   0x118008095fe60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16333"           ,	   0x118008095fe68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16334"           ,	   0x118008095fe70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16335"           ,	   0x118008095fe78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16336"           ,	   0x118008095fe80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16337"           ,	   0x118008095fe88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16338"           ,	   0x118008095fe90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16339"           ,	   0x118008095fe98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16340"           ,	   0x118008095fea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16341"           ,	   0x118008095fea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16342"           ,	   0x118008095feb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16343"           ,	   0x118008095feb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16344"           ,	   0x118008095fec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16345"           ,	   0x118008095fec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16346"           ,	   0x118008095fed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16347"           ,	   0x118008095fed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16348"           ,	   0x118008095fee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16349"           ,	   0x118008095fee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16350"           ,	   0x118008095fef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16351"           ,	   0x118008095fef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16352"           ,	   0x118008095ff00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16353"           ,	   0x118008095ff08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16354"           ,	   0x118008095ff10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16355"           ,	   0x118008095ff18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16356"           ,	   0x118008095ff20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16357"           ,	   0x118008095ff28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16358"           ,	   0x118008095ff30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16359"           ,	   0x118008095ff38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16360"           ,	   0x118008095ff40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16361"           ,	   0x118008095ff48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16362"           ,	   0x118008095ff50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16363"           ,	   0x118008095ff58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16364"           ,	   0x118008095ff60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16365"           ,	   0x118008095ff68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16366"           ,	   0x118008095ff70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16367"           ,	   0x118008095ff78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16368"           ,	   0x118008095ff80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16369"           ,	   0x118008095ff88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16370"           ,	   0x118008095ff90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16371"           ,	   0x118008095ff98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16372"           ,	   0x118008095ffa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16373"           ,	   0x118008095ffa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16374"           ,	   0x118008095ffb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16375"           ,	   0x118008095ffb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16376"           ,	   0x118008095ffc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16377"           ,	   0x118008095ffc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16378"           ,	   0x118008095ffd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16379"           ,	   0x118008095ffd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16380"           ,	   0x118008095ffe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16381"           ,	   0x118008095ffe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16382"           ,	   0x118008095fff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_COP0_MAP16383"           ,	   0x118008095fff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_CTL"                     ,	   0x1180080800000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	606},
+	{"L2C_DUT_MAP0"                ,	   0x1180080e00000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1"                ,	   0x1180080e00008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2"                ,	   0x1180080e00010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3"                ,	   0x1180080e00018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4"                ,	   0x1180080e00020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5"                ,	   0x1180080e00028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6"                ,	   0x1180080e00030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7"                ,	   0x1180080e00038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8"                ,	   0x1180080e00040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP9"                ,	   0x1180080e00048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP10"               ,	   0x1180080e00050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP11"               ,	   0x1180080e00058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP12"               ,	   0x1180080e00060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP13"               ,	   0x1180080e00068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP14"               ,	   0x1180080e00070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP15"               ,	   0x1180080e00078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP16"               ,	   0x1180080e00080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP17"               ,	   0x1180080e00088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP18"               ,	   0x1180080e00090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP19"               ,	   0x1180080e00098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP20"               ,	   0x1180080e000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP21"               ,	   0x1180080e000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP22"               ,	   0x1180080e000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP23"               ,	   0x1180080e000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP24"               ,	   0x1180080e000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP25"               ,	   0x1180080e000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP26"               ,	   0x1180080e000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP27"               ,	   0x1180080e000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP28"               ,	   0x1180080e000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP29"               ,	   0x1180080e000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP30"               ,	   0x1180080e000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP31"               ,	   0x1180080e000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP32"               ,	   0x1180080e00100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP33"               ,	   0x1180080e00108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP34"               ,	   0x1180080e00110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP35"               ,	   0x1180080e00118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP36"               ,	   0x1180080e00120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP37"               ,	   0x1180080e00128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP38"               ,	   0x1180080e00130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP39"               ,	   0x1180080e00138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP40"               ,	   0x1180080e00140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP41"               ,	   0x1180080e00148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP42"               ,	   0x1180080e00150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP43"               ,	   0x1180080e00158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP44"               ,	   0x1180080e00160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP45"               ,	   0x1180080e00168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP46"               ,	   0x1180080e00170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP47"               ,	   0x1180080e00178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP48"               ,	   0x1180080e00180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP49"               ,	   0x1180080e00188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP50"               ,	   0x1180080e00190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP51"               ,	   0x1180080e00198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP52"               ,	   0x1180080e001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP53"               ,	   0x1180080e001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP54"               ,	   0x1180080e001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP55"               ,	   0x1180080e001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP56"               ,	   0x1180080e001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP57"               ,	   0x1180080e001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP58"               ,	   0x1180080e001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP59"               ,	   0x1180080e001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP60"               ,	   0x1180080e001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP61"               ,	   0x1180080e001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP62"               ,	   0x1180080e001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP63"               ,	   0x1180080e001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP64"               ,	   0x1180080e00200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP65"               ,	   0x1180080e00208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP66"               ,	   0x1180080e00210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP67"               ,	   0x1180080e00218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP68"               ,	   0x1180080e00220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP69"               ,	   0x1180080e00228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP70"               ,	   0x1180080e00230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP71"               ,	   0x1180080e00238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP72"               ,	   0x1180080e00240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP73"               ,	   0x1180080e00248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP74"               ,	   0x1180080e00250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP75"               ,	   0x1180080e00258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP76"               ,	   0x1180080e00260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP77"               ,	   0x1180080e00268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP78"               ,	   0x1180080e00270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP79"               ,	   0x1180080e00278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP80"               ,	   0x1180080e00280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP81"               ,	   0x1180080e00288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP82"               ,	   0x1180080e00290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP83"               ,	   0x1180080e00298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP84"               ,	   0x1180080e002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP85"               ,	   0x1180080e002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP86"               ,	   0x1180080e002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP87"               ,	   0x1180080e002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP88"               ,	   0x1180080e002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP89"               ,	   0x1180080e002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP90"               ,	   0x1180080e002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP91"               ,	   0x1180080e002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP92"               ,	   0x1180080e002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP93"               ,	   0x1180080e002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP94"               ,	   0x1180080e002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP95"               ,	   0x1180080e002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP96"               ,	   0x1180080e00300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP97"               ,	   0x1180080e00308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP98"               ,	   0x1180080e00310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP99"               ,	   0x1180080e00318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP100"              ,	   0x1180080e00320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP101"              ,	   0x1180080e00328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP102"              ,	   0x1180080e00330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP103"              ,	   0x1180080e00338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP104"              ,	   0x1180080e00340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP105"              ,	   0x1180080e00348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP106"              ,	   0x1180080e00350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP107"              ,	   0x1180080e00358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP108"              ,	   0x1180080e00360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP109"              ,	   0x1180080e00368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP110"              ,	   0x1180080e00370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP111"              ,	   0x1180080e00378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP112"              ,	   0x1180080e00380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP113"              ,	   0x1180080e00388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP114"              ,	   0x1180080e00390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP115"              ,	   0x1180080e00398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP116"              ,	   0x1180080e003a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP117"              ,	   0x1180080e003a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP118"              ,	   0x1180080e003b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP119"              ,	   0x1180080e003b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP120"              ,	   0x1180080e003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP121"              ,	   0x1180080e003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP122"              ,	   0x1180080e003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP123"              ,	   0x1180080e003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP124"              ,	   0x1180080e003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP125"              ,	   0x1180080e003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP126"              ,	   0x1180080e003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP127"              ,	   0x1180080e003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP128"              ,	   0x1180080e00400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP129"              ,	   0x1180080e00408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP130"              ,	   0x1180080e00410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP131"              ,	   0x1180080e00418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP132"              ,	   0x1180080e00420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP133"              ,	   0x1180080e00428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP134"              ,	   0x1180080e00430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP135"              ,	   0x1180080e00438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP136"              ,	   0x1180080e00440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP137"              ,	   0x1180080e00448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP138"              ,	   0x1180080e00450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP139"              ,	   0x1180080e00458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP140"              ,	   0x1180080e00460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP141"              ,	   0x1180080e00468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP142"              ,	   0x1180080e00470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP143"              ,	   0x1180080e00478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP144"              ,	   0x1180080e00480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP145"              ,	   0x1180080e00488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP146"              ,	   0x1180080e00490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP147"              ,	   0x1180080e00498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP148"              ,	   0x1180080e004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP149"              ,	   0x1180080e004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP150"              ,	   0x1180080e004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP151"              ,	   0x1180080e004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP152"              ,	   0x1180080e004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP153"              ,	   0x1180080e004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP154"              ,	   0x1180080e004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP155"              ,	   0x1180080e004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP156"              ,	   0x1180080e004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP157"              ,	   0x1180080e004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP158"              ,	   0x1180080e004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP159"              ,	   0x1180080e004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP160"              ,	   0x1180080e00500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP161"              ,	   0x1180080e00508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP162"              ,	   0x1180080e00510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP163"              ,	   0x1180080e00518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP164"              ,	   0x1180080e00520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP165"              ,	   0x1180080e00528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP166"              ,	   0x1180080e00530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP167"              ,	   0x1180080e00538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP168"              ,	   0x1180080e00540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP169"              ,	   0x1180080e00548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP170"              ,	   0x1180080e00550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP171"              ,	   0x1180080e00558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP172"              ,	   0x1180080e00560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP173"              ,	   0x1180080e00568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP174"              ,	   0x1180080e00570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP175"              ,	   0x1180080e00578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP176"              ,	   0x1180080e00580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP177"              ,	   0x1180080e00588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP178"              ,	   0x1180080e00590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP179"              ,	   0x1180080e00598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP180"              ,	   0x1180080e005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP181"              ,	   0x1180080e005a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP182"              ,	   0x1180080e005b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP183"              ,	   0x1180080e005b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP184"              ,	   0x1180080e005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP185"              ,	   0x1180080e005c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP186"              ,	   0x1180080e005d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP187"              ,	   0x1180080e005d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP188"              ,	   0x1180080e005e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP189"              ,	   0x1180080e005e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP190"              ,	   0x1180080e005f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP191"              ,	   0x1180080e005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP192"              ,	   0x1180080e00600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP193"              ,	   0x1180080e00608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP194"              ,	   0x1180080e00610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP195"              ,	   0x1180080e00618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP196"              ,	   0x1180080e00620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP197"              ,	   0x1180080e00628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP198"              ,	   0x1180080e00630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP199"              ,	   0x1180080e00638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP200"              ,	   0x1180080e00640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP201"              ,	   0x1180080e00648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP202"              ,	   0x1180080e00650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP203"              ,	   0x1180080e00658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP204"              ,	   0x1180080e00660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP205"              ,	   0x1180080e00668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP206"              ,	   0x1180080e00670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP207"              ,	   0x1180080e00678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP208"              ,	   0x1180080e00680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP209"              ,	   0x1180080e00688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP210"              ,	   0x1180080e00690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP211"              ,	   0x1180080e00698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP212"              ,	   0x1180080e006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP213"              ,	   0x1180080e006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP214"              ,	   0x1180080e006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP215"              ,	   0x1180080e006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP216"              ,	   0x1180080e006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP217"              ,	   0x1180080e006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP218"              ,	   0x1180080e006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP219"              ,	   0x1180080e006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP220"              ,	   0x1180080e006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP221"              ,	   0x1180080e006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP222"              ,	   0x1180080e006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP223"              ,	   0x1180080e006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP224"              ,	   0x1180080e00700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP225"              ,	   0x1180080e00708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP226"              ,	   0x1180080e00710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP227"              ,	   0x1180080e00718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP228"              ,	   0x1180080e00720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP229"              ,	   0x1180080e00728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP230"              ,	   0x1180080e00730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP231"              ,	   0x1180080e00738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP232"              ,	   0x1180080e00740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP233"              ,	   0x1180080e00748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP234"              ,	   0x1180080e00750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP235"              ,	   0x1180080e00758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP236"              ,	   0x1180080e00760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP237"              ,	   0x1180080e00768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP238"              ,	   0x1180080e00770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP239"              ,	   0x1180080e00778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP240"              ,	   0x1180080e00780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP241"              ,	   0x1180080e00788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP242"              ,	   0x1180080e00790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP243"              ,	   0x1180080e00798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP244"              ,	   0x1180080e007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP245"              ,	   0x1180080e007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP246"              ,	   0x1180080e007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP247"              ,	   0x1180080e007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP248"              ,	   0x1180080e007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP249"              ,	   0x1180080e007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP250"              ,	   0x1180080e007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP251"              ,	   0x1180080e007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP252"              ,	   0x1180080e007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP253"              ,	   0x1180080e007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP254"              ,	   0x1180080e007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP255"              ,	   0x1180080e007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP256"              ,	   0x1180080e00800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP257"              ,	   0x1180080e00808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP258"              ,	   0x1180080e00810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP259"              ,	   0x1180080e00818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP260"              ,	   0x1180080e00820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP261"              ,	   0x1180080e00828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP262"              ,	   0x1180080e00830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP263"              ,	   0x1180080e00838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP264"              ,	   0x1180080e00840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP265"              ,	   0x1180080e00848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP266"              ,	   0x1180080e00850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP267"              ,	   0x1180080e00858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP268"              ,	   0x1180080e00860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP269"              ,	   0x1180080e00868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP270"              ,	   0x1180080e00870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP271"              ,	   0x1180080e00878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP272"              ,	   0x1180080e00880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP273"              ,	   0x1180080e00888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP274"              ,	   0x1180080e00890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP275"              ,	   0x1180080e00898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP276"              ,	   0x1180080e008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP277"              ,	   0x1180080e008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP278"              ,	   0x1180080e008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP279"              ,	   0x1180080e008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP280"              ,	   0x1180080e008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP281"              ,	   0x1180080e008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP282"              ,	   0x1180080e008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP283"              ,	   0x1180080e008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP284"              ,	   0x1180080e008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP285"              ,	   0x1180080e008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP286"              ,	   0x1180080e008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP287"              ,	   0x1180080e008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP288"              ,	   0x1180080e00900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP289"              ,	   0x1180080e00908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP290"              ,	   0x1180080e00910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP291"              ,	   0x1180080e00918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP292"              ,	   0x1180080e00920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP293"              ,	   0x1180080e00928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP294"              ,	   0x1180080e00930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP295"              ,	   0x1180080e00938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP296"              ,	   0x1180080e00940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP297"              ,	   0x1180080e00948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP298"              ,	   0x1180080e00950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP299"              ,	   0x1180080e00958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP300"              ,	   0x1180080e00960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP301"              ,	   0x1180080e00968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP302"              ,	   0x1180080e00970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP303"              ,	   0x1180080e00978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP304"              ,	   0x1180080e00980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP305"              ,	   0x1180080e00988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP306"              ,	   0x1180080e00990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP307"              ,	   0x1180080e00998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP308"              ,	   0x1180080e009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP309"              ,	   0x1180080e009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP310"              ,	   0x1180080e009b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP311"              ,	   0x1180080e009b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP312"              ,	   0x1180080e009c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP313"              ,	   0x1180080e009c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP314"              ,	   0x1180080e009d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP315"              ,	   0x1180080e009d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP316"              ,	   0x1180080e009e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP317"              ,	   0x1180080e009e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP318"              ,	   0x1180080e009f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP319"              ,	   0x1180080e009f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP320"              ,	   0x1180080e00a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP321"              ,	   0x1180080e00a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP322"              ,	   0x1180080e00a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP323"              ,	   0x1180080e00a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP324"              ,	   0x1180080e00a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP325"              ,	   0x1180080e00a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP326"              ,	   0x1180080e00a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP327"              ,	   0x1180080e00a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP328"              ,	   0x1180080e00a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP329"              ,	   0x1180080e00a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP330"              ,	   0x1180080e00a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP331"              ,	   0x1180080e00a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP332"              ,	   0x1180080e00a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP333"              ,	   0x1180080e00a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP334"              ,	   0x1180080e00a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP335"              ,	   0x1180080e00a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP336"              ,	   0x1180080e00a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP337"              ,	   0x1180080e00a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP338"              ,	   0x1180080e00a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP339"              ,	   0x1180080e00a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP340"              ,	   0x1180080e00aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP341"              ,	   0x1180080e00aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP342"              ,	   0x1180080e00ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP343"              ,	   0x1180080e00ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP344"              ,	   0x1180080e00ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP345"              ,	   0x1180080e00ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP346"              ,	   0x1180080e00ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP347"              ,	   0x1180080e00ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP348"              ,	   0x1180080e00ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP349"              ,	   0x1180080e00ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP350"              ,	   0x1180080e00af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP351"              ,	   0x1180080e00af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP352"              ,	   0x1180080e00b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP353"              ,	   0x1180080e00b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP354"              ,	   0x1180080e00b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP355"              ,	   0x1180080e00b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP356"              ,	   0x1180080e00b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP357"              ,	   0x1180080e00b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP358"              ,	   0x1180080e00b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP359"              ,	   0x1180080e00b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP360"              ,	   0x1180080e00b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP361"              ,	   0x1180080e00b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP362"              ,	   0x1180080e00b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP363"              ,	   0x1180080e00b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP364"              ,	   0x1180080e00b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP365"              ,	   0x1180080e00b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP366"              ,	   0x1180080e00b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP367"              ,	   0x1180080e00b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP368"              ,	   0x1180080e00b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP369"              ,	   0x1180080e00b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP370"              ,	   0x1180080e00b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP371"              ,	   0x1180080e00b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP372"              ,	   0x1180080e00ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP373"              ,	   0x1180080e00ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP374"              ,	   0x1180080e00bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP375"              ,	   0x1180080e00bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP376"              ,	   0x1180080e00bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP377"              ,	   0x1180080e00bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP378"              ,	   0x1180080e00bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP379"              ,	   0x1180080e00bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP380"              ,	   0x1180080e00be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP381"              ,	   0x1180080e00be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP382"              ,	   0x1180080e00bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP383"              ,	   0x1180080e00bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP384"              ,	   0x1180080e00c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP385"              ,	   0x1180080e00c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP386"              ,	   0x1180080e00c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP387"              ,	   0x1180080e00c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP388"              ,	   0x1180080e00c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP389"              ,	   0x1180080e00c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP390"              ,	   0x1180080e00c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP391"              ,	   0x1180080e00c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP392"              ,	   0x1180080e00c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP393"              ,	   0x1180080e00c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP394"              ,	   0x1180080e00c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP395"              ,	   0x1180080e00c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP396"              ,	   0x1180080e00c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP397"              ,	   0x1180080e00c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP398"              ,	   0x1180080e00c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP399"              ,	   0x1180080e00c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP400"              ,	   0x1180080e00c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP401"              ,	   0x1180080e00c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP402"              ,	   0x1180080e00c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP403"              ,	   0x1180080e00c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP404"              ,	   0x1180080e00ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP405"              ,	   0x1180080e00ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP406"              ,	   0x1180080e00cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP407"              ,	   0x1180080e00cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP408"              ,	   0x1180080e00cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP409"              ,	   0x1180080e00cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP410"              ,	   0x1180080e00cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP411"              ,	   0x1180080e00cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP412"              ,	   0x1180080e00ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP413"              ,	   0x1180080e00ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP414"              ,	   0x1180080e00cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP415"              ,	   0x1180080e00cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP416"              ,	   0x1180080e00d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP417"              ,	   0x1180080e00d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP418"              ,	   0x1180080e00d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP419"              ,	   0x1180080e00d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP420"              ,	   0x1180080e00d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP421"              ,	   0x1180080e00d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP422"              ,	   0x1180080e00d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP423"              ,	   0x1180080e00d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP424"              ,	   0x1180080e00d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP425"              ,	   0x1180080e00d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP426"              ,	   0x1180080e00d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP427"              ,	   0x1180080e00d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP428"              ,	   0x1180080e00d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP429"              ,	   0x1180080e00d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP430"              ,	   0x1180080e00d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP431"              ,	   0x1180080e00d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP432"              ,	   0x1180080e00d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP433"              ,	   0x1180080e00d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP434"              ,	   0x1180080e00d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP435"              ,	   0x1180080e00d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP436"              ,	   0x1180080e00da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP437"              ,	   0x1180080e00da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP438"              ,	   0x1180080e00db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP439"              ,	   0x1180080e00db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP440"              ,	   0x1180080e00dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP441"              ,	   0x1180080e00dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP442"              ,	   0x1180080e00dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP443"              ,	   0x1180080e00dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP444"              ,	   0x1180080e00de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP445"              ,	   0x1180080e00de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP446"              ,	   0x1180080e00df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP447"              ,	   0x1180080e00df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP448"              ,	   0x1180080e00e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP449"              ,	   0x1180080e00e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP450"              ,	   0x1180080e00e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP451"              ,	   0x1180080e00e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP452"              ,	   0x1180080e00e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP453"              ,	   0x1180080e00e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP454"              ,	   0x1180080e00e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP455"              ,	   0x1180080e00e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP456"              ,	   0x1180080e00e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP457"              ,	   0x1180080e00e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP458"              ,	   0x1180080e00e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP459"              ,	   0x1180080e00e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP460"              ,	   0x1180080e00e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP461"              ,	   0x1180080e00e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP462"              ,	   0x1180080e00e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP463"              ,	   0x1180080e00e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP464"              ,	   0x1180080e00e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP465"              ,	   0x1180080e00e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP466"              ,	   0x1180080e00e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP467"              ,	   0x1180080e00e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP468"              ,	   0x1180080e00ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP469"              ,	   0x1180080e00ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP470"              ,	   0x1180080e00eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP471"              ,	   0x1180080e00eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP472"              ,	   0x1180080e00ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP473"              ,	   0x1180080e00ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP474"              ,	   0x1180080e00ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP475"              ,	   0x1180080e00ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP476"              ,	   0x1180080e00ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP477"              ,	   0x1180080e00ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP478"              ,	   0x1180080e00ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP479"              ,	   0x1180080e00ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP480"              ,	   0x1180080e00f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP481"              ,	   0x1180080e00f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP482"              ,	   0x1180080e00f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP483"              ,	   0x1180080e00f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP484"              ,	   0x1180080e00f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP485"              ,	   0x1180080e00f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP486"              ,	   0x1180080e00f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP487"              ,	   0x1180080e00f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP488"              ,	   0x1180080e00f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP489"              ,	   0x1180080e00f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP490"              ,	   0x1180080e00f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP491"              ,	   0x1180080e00f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP492"              ,	   0x1180080e00f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP493"              ,	   0x1180080e00f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP494"              ,	   0x1180080e00f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP495"              ,	   0x1180080e00f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP496"              ,	   0x1180080e00f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP497"              ,	   0x1180080e00f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP498"              ,	   0x1180080e00f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP499"              ,	   0x1180080e00f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP500"              ,	   0x1180080e00fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP501"              ,	   0x1180080e00fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP502"              ,	   0x1180080e00fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP503"              ,	   0x1180080e00fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP504"              ,	   0x1180080e00fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP505"              ,	   0x1180080e00fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP506"              ,	   0x1180080e00fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP507"              ,	   0x1180080e00fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP508"              ,	   0x1180080e00fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP509"              ,	   0x1180080e00fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP510"              ,	   0x1180080e00ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP511"              ,	   0x1180080e00ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP512"              ,	   0x1180080e01000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP513"              ,	   0x1180080e01008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP514"              ,	   0x1180080e01010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP515"              ,	   0x1180080e01018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP516"              ,	   0x1180080e01020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP517"              ,	   0x1180080e01028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP518"              ,	   0x1180080e01030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP519"              ,	   0x1180080e01038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP520"              ,	   0x1180080e01040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP521"              ,	   0x1180080e01048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP522"              ,	   0x1180080e01050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP523"              ,	   0x1180080e01058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP524"              ,	   0x1180080e01060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP525"              ,	   0x1180080e01068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP526"              ,	   0x1180080e01070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP527"              ,	   0x1180080e01078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP528"              ,	   0x1180080e01080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP529"              ,	   0x1180080e01088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP530"              ,	   0x1180080e01090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP531"              ,	   0x1180080e01098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP532"              ,	   0x1180080e010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP533"              ,	   0x1180080e010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP534"              ,	   0x1180080e010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP535"              ,	   0x1180080e010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP536"              ,	   0x1180080e010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP537"              ,	   0x1180080e010c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP538"              ,	   0x1180080e010d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP539"              ,	   0x1180080e010d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP540"              ,	   0x1180080e010e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP541"              ,	   0x1180080e010e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP542"              ,	   0x1180080e010f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP543"              ,	   0x1180080e010f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP544"              ,	   0x1180080e01100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP545"              ,	   0x1180080e01108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP546"              ,	   0x1180080e01110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP547"              ,	   0x1180080e01118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP548"              ,	   0x1180080e01120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP549"              ,	   0x1180080e01128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP550"              ,	   0x1180080e01130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP551"              ,	   0x1180080e01138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP552"              ,	   0x1180080e01140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP553"              ,	   0x1180080e01148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP554"              ,	   0x1180080e01150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP555"              ,	   0x1180080e01158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP556"              ,	   0x1180080e01160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP557"              ,	   0x1180080e01168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP558"              ,	   0x1180080e01170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP559"              ,	   0x1180080e01178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP560"              ,	   0x1180080e01180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP561"              ,	   0x1180080e01188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP562"              ,	   0x1180080e01190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP563"              ,	   0x1180080e01198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP564"              ,	   0x1180080e011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP565"              ,	   0x1180080e011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP566"              ,	   0x1180080e011b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP567"              ,	   0x1180080e011b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP568"              ,	   0x1180080e011c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP569"              ,	   0x1180080e011c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP570"              ,	   0x1180080e011d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP571"              ,	   0x1180080e011d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP572"              ,	   0x1180080e011e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP573"              ,	   0x1180080e011e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP574"              ,	   0x1180080e011f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP575"              ,	   0x1180080e011f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP576"              ,	   0x1180080e01200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP577"              ,	   0x1180080e01208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP578"              ,	   0x1180080e01210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP579"              ,	   0x1180080e01218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP580"              ,	   0x1180080e01220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP581"              ,	   0x1180080e01228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP582"              ,	   0x1180080e01230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP583"              ,	   0x1180080e01238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP584"              ,	   0x1180080e01240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP585"              ,	   0x1180080e01248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP586"              ,	   0x1180080e01250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP587"              ,	   0x1180080e01258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP588"              ,	   0x1180080e01260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP589"              ,	   0x1180080e01268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP590"              ,	   0x1180080e01270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP591"              ,	   0x1180080e01278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP592"              ,	   0x1180080e01280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP593"              ,	   0x1180080e01288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP594"              ,	   0x1180080e01290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP595"              ,	   0x1180080e01298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP596"              ,	   0x1180080e012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP597"              ,	   0x1180080e012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP598"              ,	   0x1180080e012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP599"              ,	   0x1180080e012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP600"              ,	   0x1180080e012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP601"              ,	   0x1180080e012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP602"              ,	   0x1180080e012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP603"              ,	   0x1180080e012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP604"              ,	   0x1180080e012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP605"              ,	   0x1180080e012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP606"              ,	   0x1180080e012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP607"              ,	   0x1180080e012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP608"              ,	   0x1180080e01300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP609"              ,	   0x1180080e01308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP610"              ,	   0x1180080e01310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP611"              ,	   0x1180080e01318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP612"              ,	   0x1180080e01320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP613"              ,	   0x1180080e01328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP614"              ,	   0x1180080e01330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP615"              ,	   0x1180080e01338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP616"              ,	   0x1180080e01340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP617"              ,	   0x1180080e01348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP618"              ,	   0x1180080e01350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP619"              ,	   0x1180080e01358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP620"              ,	   0x1180080e01360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP621"              ,	   0x1180080e01368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP622"              ,	   0x1180080e01370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP623"              ,	   0x1180080e01378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP624"              ,	   0x1180080e01380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP625"              ,	   0x1180080e01388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP626"              ,	   0x1180080e01390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP627"              ,	   0x1180080e01398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP628"              ,	   0x1180080e013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP629"              ,	   0x1180080e013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP630"              ,	   0x1180080e013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP631"              ,	   0x1180080e013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP632"              ,	   0x1180080e013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP633"              ,	   0x1180080e013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP634"              ,	   0x1180080e013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP635"              ,	   0x1180080e013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP636"              ,	   0x1180080e013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP637"              ,	   0x1180080e013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP638"              ,	   0x1180080e013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP639"              ,	   0x1180080e013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP640"              ,	   0x1180080e01400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP641"              ,	   0x1180080e01408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP642"              ,	   0x1180080e01410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP643"              ,	   0x1180080e01418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP644"              ,	   0x1180080e01420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP645"              ,	   0x1180080e01428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP646"              ,	   0x1180080e01430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP647"              ,	   0x1180080e01438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP648"              ,	   0x1180080e01440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP649"              ,	   0x1180080e01448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP650"              ,	   0x1180080e01450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP651"              ,	   0x1180080e01458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP652"              ,	   0x1180080e01460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP653"              ,	   0x1180080e01468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP654"              ,	   0x1180080e01470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP655"              ,	   0x1180080e01478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP656"              ,	   0x1180080e01480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP657"              ,	   0x1180080e01488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP658"              ,	   0x1180080e01490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP659"              ,	   0x1180080e01498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP660"              ,	   0x1180080e014a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP661"              ,	   0x1180080e014a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP662"              ,	   0x1180080e014b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP663"              ,	   0x1180080e014b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP664"              ,	   0x1180080e014c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP665"              ,	   0x1180080e014c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP666"              ,	   0x1180080e014d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP667"              ,	   0x1180080e014d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP668"              ,	   0x1180080e014e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP669"              ,	   0x1180080e014e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP670"              ,	   0x1180080e014f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP671"              ,	   0x1180080e014f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP672"              ,	   0x1180080e01500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP673"              ,	   0x1180080e01508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP674"              ,	   0x1180080e01510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP675"              ,	   0x1180080e01518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP676"              ,	   0x1180080e01520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP677"              ,	   0x1180080e01528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP678"              ,	   0x1180080e01530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP679"              ,	   0x1180080e01538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP680"              ,	   0x1180080e01540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP681"              ,	   0x1180080e01548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP682"              ,	   0x1180080e01550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP683"              ,	   0x1180080e01558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP684"              ,	   0x1180080e01560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP685"              ,	   0x1180080e01568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP686"              ,	   0x1180080e01570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP687"              ,	   0x1180080e01578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP688"              ,	   0x1180080e01580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP689"              ,	   0x1180080e01588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP690"              ,	   0x1180080e01590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP691"              ,	   0x1180080e01598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP692"              ,	   0x1180080e015a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP693"              ,	   0x1180080e015a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP694"              ,	   0x1180080e015b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP695"              ,	   0x1180080e015b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP696"              ,	   0x1180080e015c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP697"              ,	   0x1180080e015c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP698"              ,	   0x1180080e015d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP699"              ,	   0x1180080e015d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP700"              ,	   0x1180080e015e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP701"              ,	   0x1180080e015e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP702"              ,	   0x1180080e015f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP703"              ,	   0x1180080e015f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP704"              ,	   0x1180080e01600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP705"              ,	   0x1180080e01608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP706"              ,	   0x1180080e01610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP707"              ,	   0x1180080e01618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP708"              ,	   0x1180080e01620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP709"              ,	   0x1180080e01628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP710"              ,	   0x1180080e01630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP711"              ,	   0x1180080e01638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP712"              ,	   0x1180080e01640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP713"              ,	   0x1180080e01648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP714"              ,	   0x1180080e01650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP715"              ,	   0x1180080e01658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP716"              ,	   0x1180080e01660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP717"              ,	   0x1180080e01668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP718"              ,	   0x1180080e01670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP719"              ,	   0x1180080e01678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP720"              ,	   0x1180080e01680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP721"              ,	   0x1180080e01688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP722"              ,	   0x1180080e01690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP723"              ,	   0x1180080e01698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP724"              ,	   0x1180080e016a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP725"              ,	   0x1180080e016a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP726"              ,	   0x1180080e016b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP727"              ,	   0x1180080e016b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP728"              ,	   0x1180080e016c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP729"              ,	   0x1180080e016c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP730"              ,	   0x1180080e016d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP731"              ,	   0x1180080e016d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP732"              ,	   0x1180080e016e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP733"              ,	   0x1180080e016e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP734"              ,	   0x1180080e016f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP735"              ,	   0x1180080e016f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP736"              ,	   0x1180080e01700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP737"              ,	   0x1180080e01708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP738"              ,	   0x1180080e01710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP739"              ,	   0x1180080e01718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP740"              ,	   0x1180080e01720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP741"              ,	   0x1180080e01728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP742"              ,	   0x1180080e01730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP743"              ,	   0x1180080e01738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP744"              ,	   0x1180080e01740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP745"              ,	   0x1180080e01748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP746"              ,	   0x1180080e01750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP747"              ,	   0x1180080e01758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP748"              ,	   0x1180080e01760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP749"              ,	   0x1180080e01768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP750"              ,	   0x1180080e01770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP751"              ,	   0x1180080e01778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP752"              ,	   0x1180080e01780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP753"              ,	   0x1180080e01788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP754"              ,	   0x1180080e01790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP755"              ,	   0x1180080e01798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP756"              ,	   0x1180080e017a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP757"              ,	   0x1180080e017a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP758"              ,	   0x1180080e017b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP759"              ,	   0x1180080e017b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP760"              ,	   0x1180080e017c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP761"              ,	   0x1180080e017c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP762"              ,	   0x1180080e017d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP763"              ,	   0x1180080e017d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP764"              ,	   0x1180080e017e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP765"              ,	   0x1180080e017e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP766"              ,	   0x1180080e017f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP767"              ,	   0x1180080e017f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP768"              ,	   0x1180080e01800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP769"              ,	   0x1180080e01808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP770"              ,	   0x1180080e01810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP771"              ,	   0x1180080e01818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP772"              ,	   0x1180080e01820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP773"              ,	   0x1180080e01828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP774"              ,	   0x1180080e01830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP775"              ,	   0x1180080e01838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP776"              ,	   0x1180080e01840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP777"              ,	   0x1180080e01848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP778"              ,	   0x1180080e01850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP779"              ,	   0x1180080e01858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP780"              ,	   0x1180080e01860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP781"              ,	   0x1180080e01868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP782"              ,	   0x1180080e01870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP783"              ,	   0x1180080e01878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP784"              ,	   0x1180080e01880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP785"              ,	   0x1180080e01888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP786"              ,	   0x1180080e01890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP787"              ,	   0x1180080e01898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP788"              ,	   0x1180080e018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP789"              ,	   0x1180080e018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP790"              ,	   0x1180080e018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP791"              ,	   0x1180080e018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP792"              ,	   0x1180080e018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP793"              ,	   0x1180080e018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP794"              ,	   0x1180080e018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP795"              ,	   0x1180080e018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP796"              ,	   0x1180080e018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP797"              ,	   0x1180080e018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP798"              ,	   0x1180080e018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP799"              ,	   0x1180080e018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP800"              ,	   0x1180080e01900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP801"              ,	   0x1180080e01908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP802"              ,	   0x1180080e01910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP803"              ,	   0x1180080e01918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP804"              ,	   0x1180080e01920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP805"              ,	   0x1180080e01928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP806"              ,	   0x1180080e01930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP807"              ,	   0x1180080e01938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP808"              ,	   0x1180080e01940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP809"              ,	   0x1180080e01948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP810"              ,	   0x1180080e01950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP811"              ,	   0x1180080e01958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP812"              ,	   0x1180080e01960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP813"              ,	   0x1180080e01968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP814"              ,	   0x1180080e01970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP815"              ,	   0x1180080e01978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP816"              ,	   0x1180080e01980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP817"              ,	   0x1180080e01988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP818"              ,	   0x1180080e01990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP819"              ,	   0x1180080e01998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP820"              ,	   0x1180080e019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP821"              ,	   0x1180080e019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP822"              ,	   0x1180080e019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP823"              ,	   0x1180080e019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP824"              ,	   0x1180080e019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP825"              ,	   0x1180080e019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP826"              ,	   0x1180080e019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP827"              ,	   0x1180080e019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP828"              ,	   0x1180080e019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP829"              ,	   0x1180080e019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP830"              ,	   0x1180080e019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP831"              ,	   0x1180080e019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP832"              ,	   0x1180080e01a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP833"              ,	   0x1180080e01a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP834"              ,	   0x1180080e01a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP835"              ,	   0x1180080e01a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP836"              ,	   0x1180080e01a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP837"              ,	   0x1180080e01a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP838"              ,	   0x1180080e01a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP839"              ,	   0x1180080e01a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP840"              ,	   0x1180080e01a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP841"              ,	   0x1180080e01a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP842"              ,	   0x1180080e01a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP843"              ,	   0x1180080e01a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP844"              ,	   0x1180080e01a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP845"              ,	   0x1180080e01a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP846"              ,	   0x1180080e01a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP847"              ,	   0x1180080e01a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP848"              ,	   0x1180080e01a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP849"              ,	   0x1180080e01a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP850"              ,	   0x1180080e01a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP851"              ,	   0x1180080e01a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP852"              ,	   0x1180080e01aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP853"              ,	   0x1180080e01aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP854"              ,	   0x1180080e01ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP855"              ,	   0x1180080e01ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP856"              ,	   0x1180080e01ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP857"              ,	   0x1180080e01ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP858"              ,	   0x1180080e01ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP859"              ,	   0x1180080e01ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP860"              ,	   0x1180080e01ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP861"              ,	   0x1180080e01ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP862"              ,	   0x1180080e01af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP863"              ,	   0x1180080e01af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP864"              ,	   0x1180080e01b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP865"              ,	   0x1180080e01b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP866"              ,	   0x1180080e01b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP867"              ,	   0x1180080e01b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP868"              ,	   0x1180080e01b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP869"              ,	   0x1180080e01b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP870"              ,	   0x1180080e01b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP871"              ,	   0x1180080e01b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP872"              ,	   0x1180080e01b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP873"              ,	   0x1180080e01b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP874"              ,	   0x1180080e01b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP875"              ,	   0x1180080e01b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP876"              ,	   0x1180080e01b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP877"              ,	   0x1180080e01b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP878"              ,	   0x1180080e01b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP879"              ,	   0x1180080e01b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP880"              ,	   0x1180080e01b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP881"              ,	   0x1180080e01b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP882"              ,	   0x1180080e01b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP883"              ,	   0x1180080e01b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP884"              ,	   0x1180080e01ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP885"              ,	   0x1180080e01ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP886"              ,	   0x1180080e01bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP887"              ,	   0x1180080e01bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP888"              ,	   0x1180080e01bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP889"              ,	   0x1180080e01bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP890"              ,	   0x1180080e01bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP891"              ,	   0x1180080e01bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP892"              ,	   0x1180080e01be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP893"              ,	   0x1180080e01be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP894"              ,	   0x1180080e01bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP895"              ,	   0x1180080e01bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP896"              ,	   0x1180080e01c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP897"              ,	   0x1180080e01c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP898"              ,	   0x1180080e01c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP899"              ,	   0x1180080e01c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP900"              ,	   0x1180080e01c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP901"              ,	   0x1180080e01c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP902"              ,	   0x1180080e01c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP903"              ,	   0x1180080e01c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP904"              ,	   0x1180080e01c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP905"              ,	   0x1180080e01c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP906"              ,	   0x1180080e01c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP907"              ,	   0x1180080e01c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP908"              ,	   0x1180080e01c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP909"              ,	   0x1180080e01c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP910"              ,	   0x1180080e01c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP911"              ,	   0x1180080e01c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP912"              ,	   0x1180080e01c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP913"              ,	   0x1180080e01c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP914"              ,	   0x1180080e01c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP915"              ,	   0x1180080e01c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP916"              ,	   0x1180080e01ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP917"              ,	   0x1180080e01ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP918"              ,	   0x1180080e01cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP919"              ,	   0x1180080e01cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP920"              ,	   0x1180080e01cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP921"              ,	   0x1180080e01cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP922"              ,	   0x1180080e01cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP923"              ,	   0x1180080e01cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP924"              ,	   0x1180080e01ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP925"              ,	   0x1180080e01ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP926"              ,	   0x1180080e01cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP927"              ,	   0x1180080e01cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP928"              ,	   0x1180080e01d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP929"              ,	   0x1180080e01d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP930"              ,	   0x1180080e01d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP931"              ,	   0x1180080e01d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP932"              ,	   0x1180080e01d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP933"              ,	   0x1180080e01d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP934"              ,	   0x1180080e01d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP935"              ,	   0x1180080e01d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP936"              ,	   0x1180080e01d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP937"              ,	   0x1180080e01d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP938"              ,	   0x1180080e01d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP939"              ,	   0x1180080e01d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP940"              ,	   0x1180080e01d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP941"              ,	   0x1180080e01d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP942"              ,	   0x1180080e01d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP943"              ,	   0x1180080e01d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP944"              ,	   0x1180080e01d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP945"              ,	   0x1180080e01d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP946"              ,	   0x1180080e01d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP947"              ,	   0x1180080e01d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP948"              ,	   0x1180080e01da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP949"              ,	   0x1180080e01da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP950"              ,	   0x1180080e01db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP951"              ,	   0x1180080e01db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP952"              ,	   0x1180080e01dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP953"              ,	   0x1180080e01dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP954"              ,	   0x1180080e01dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP955"              ,	   0x1180080e01dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP956"              ,	   0x1180080e01de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP957"              ,	   0x1180080e01de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP958"              ,	   0x1180080e01df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP959"              ,	   0x1180080e01df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP960"              ,	   0x1180080e01e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP961"              ,	   0x1180080e01e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP962"              ,	   0x1180080e01e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP963"              ,	   0x1180080e01e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP964"              ,	   0x1180080e01e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP965"              ,	   0x1180080e01e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP966"              ,	   0x1180080e01e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP967"              ,	   0x1180080e01e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP968"              ,	   0x1180080e01e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP969"              ,	   0x1180080e01e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP970"              ,	   0x1180080e01e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP971"              ,	   0x1180080e01e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP972"              ,	   0x1180080e01e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP973"              ,	   0x1180080e01e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP974"              ,	   0x1180080e01e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP975"              ,	   0x1180080e01e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP976"              ,	   0x1180080e01e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP977"              ,	   0x1180080e01e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP978"              ,	   0x1180080e01e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP979"              ,	   0x1180080e01e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP980"              ,	   0x1180080e01ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP981"              ,	   0x1180080e01ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP982"              ,	   0x1180080e01eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP983"              ,	   0x1180080e01eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP984"              ,	   0x1180080e01ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP985"              ,	   0x1180080e01ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP986"              ,	   0x1180080e01ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP987"              ,	   0x1180080e01ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP988"              ,	   0x1180080e01ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP989"              ,	   0x1180080e01ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP990"              ,	   0x1180080e01ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP991"              ,	   0x1180080e01ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP992"              ,	   0x1180080e01f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP993"              ,	   0x1180080e01f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP994"              ,	   0x1180080e01f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP995"              ,	   0x1180080e01f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP996"              ,	   0x1180080e01f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP997"              ,	   0x1180080e01f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP998"              ,	   0x1180080e01f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP999"              ,	   0x1180080e01f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1000"             ,	   0x1180080e01f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1001"             ,	   0x1180080e01f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1002"             ,	   0x1180080e01f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1003"             ,	   0x1180080e01f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1004"             ,	   0x1180080e01f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1005"             ,	   0x1180080e01f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1006"             ,	   0x1180080e01f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1007"             ,	   0x1180080e01f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1008"             ,	   0x1180080e01f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1009"             ,	   0x1180080e01f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1010"             ,	   0x1180080e01f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1011"             ,	   0x1180080e01f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1012"             ,	   0x1180080e01fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1013"             ,	   0x1180080e01fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1014"             ,	   0x1180080e01fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1015"             ,	   0x1180080e01fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1016"             ,	   0x1180080e01fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1017"             ,	   0x1180080e01fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1018"             ,	   0x1180080e01fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1019"             ,	   0x1180080e01fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1020"             ,	   0x1180080e01fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1021"             ,	   0x1180080e01fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1022"             ,	   0x1180080e01ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1023"             ,	   0x1180080e01ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1024"             ,	   0x1180080e02000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1025"             ,	   0x1180080e02008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1026"             ,	   0x1180080e02010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1027"             ,	   0x1180080e02018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1028"             ,	   0x1180080e02020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1029"             ,	   0x1180080e02028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1030"             ,	   0x1180080e02030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1031"             ,	   0x1180080e02038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1032"             ,	   0x1180080e02040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1033"             ,	   0x1180080e02048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1034"             ,	   0x1180080e02050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1035"             ,	   0x1180080e02058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1036"             ,	   0x1180080e02060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1037"             ,	   0x1180080e02068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1038"             ,	   0x1180080e02070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1039"             ,	   0x1180080e02078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1040"             ,	   0x1180080e02080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1041"             ,	   0x1180080e02088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1042"             ,	   0x1180080e02090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1043"             ,	   0x1180080e02098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1044"             ,	   0x1180080e020a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1045"             ,	   0x1180080e020a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1046"             ,	   0x1180080e020b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1047"             ,	   0x1180080e020b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1048"             ,	   0x1180080e020c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1049"             ,	   0x1180080e020c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1050"             ,	   0x1180080e020d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1051"             ,	   0x1180080e020d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1052"             ,	   0x1180080e020e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1053"             ,	   0x1180080e020e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1054"             ,	   0x1180080e020f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1055"             ,	   0x1180080e020f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1056"             ,	   0x1180080e02100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1057"             ,	   0x1180080e02108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1058"             ,	   0x1180080e02110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1059"             ,	   0x1180080e02118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1060"             ,	   0x1180080e02120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1061"             ,	   0x1180080e02128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1062"             ,	   0x1180080e02130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1063"             ,	   0x1180080e02138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1064"             ,	   0x1180080e02140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1065"             ,	   0x1180080e02148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1066"             ,	   0x1180080e02150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1067"             ,	   0x1180080e02158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1068"             ,	   0x1180080e02160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1069"             ,	   0x1180080e02168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1070"             ,	   0x1180080e02170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1071"             ,	   0x1180080e02178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1072"             ,	   0x1180080e02180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1073"             ,	   0x1180080e02188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1074"             ,	   0x1180080e02190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1075"             ,	   0x1180080e02198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1076"             ,	   0x1180080e021a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1077"             ,	   0x1180080e021a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1078"             ,	   0x1180080e021b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1079"             ,	   0x1180080e021b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1080"             ,	   0x1180080e021c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1081"             ,	   0x1180080e021c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1082"             ,	   0x1180080e021d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1083"             ,	   0x1180080e021d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1084"             ,	   0x1180080e021e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1085"             ,	   0x1180080e021e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1086"             ,	   0x1180080e021f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1087"             ,	   0x1180080e021f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1088"             ,	   0x1180080e02200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1089"             ,	   0x1180080e02208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1090"             ,	   0x1180080e02210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1091"             ,	   0x1180080e02218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1092"             ,	   0x1180080e02220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1093"             ,	   0x1180080e02228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1094"             ,	   0x1180080e02230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1095"             ,	   0x1180080e02238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1096"             ,	   0x1180080e02240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1097"             ,	   0x1180080e02248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1098"             ,	   0x1180080e02250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1099"             ,	   0x1180080e02258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1100"             ,	   0x1180080e02260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1101"             ,	   0x1180080e02268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1102"             ,	   0x1180080e02270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1103"             ,	   0x1180080e02278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1104"             ,	   0x1180080e02280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1105"             ,	   0x1180080e02288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1106"             ,	   0x1180080e02290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1107"             ,	   0x1180080e02298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1108"             ,	   0x1180080e022a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1109"             ,	   0x1180080e022a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1110"             ,	   0x1180080e022b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1111"             ,	   0x1180080e022b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1112"             ,	   0x1180080e022c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1113"             ,	   0x1180080e022c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1114"             ,	   0x1180080e022d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1115"             ,	   0x1180080e022d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1116"             ,	   0x1180080e022e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1117"             ,	   0x1180080e022e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1118"             ,	   0x1180080e022f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1119"             ,	   0x1180080e022f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1120"             ,	   0x1180080e02300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1121"             ,	   0x1180080e02308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1122"             ,	   0x1180080e02310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1123"             ,	   0x1180080e02318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1124"             ,	   0x1180080e02320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1125"             ,	   0x1180080e02328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1126"             ,	   0x1180080e02330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1127"             ,	   0x1180080e02338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1128"             ,	   0x1180080e02340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1129"             ,	   0x1180080e02348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1130"             ,	   0x1180080e02350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1131"             ,	   0x1180080e02358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1132"             ,	   0x1180080e02360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1133"             ,	   0x1180080e02368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1134"             ,	   0x1180080e02370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1135"             ,	   0x1180080e02378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1136"             ,	   0x1180080e02380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1137"             ,	   0x1180080e02388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1138"             ,	   0x1180080e02390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1139"             ,	   0x1180080e02398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1140"             ,	   0x1180080e023a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1141"             ,	   0x1180080e023a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1142"             ,	   0x1180080e023b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1143"             ,	   0x1180080e023b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1144"             ,	   0x1180080e023c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1145"             ,	   0x1180080e023c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1146"             ,	   0x1180080e023d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1147"             ,	   0x1180080e023d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1148"             ,	   0x1180080e023e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1149"             ,	   0x1180080e023e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1150"             ,	   0x1180080e023f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1151"             ,	   0x1180080e023f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1152"             ,	   0x1180080e02400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1153"             ,	   0x1180080e02408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1154"             ,	   0x1180080e02410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1155"             ,	   0x1180080e02418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1156"             ,	   0x1180080e02420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1157"             ,	   0x1180080e02428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1158"             ,	   0x1180080e02430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1159"             ,	   0x1180080e02438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1160"             ,	   0x1180080e02440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1161"             ,	   0x1180080e02448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1162"             ,	   0x1180080e02450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1163"             ,	   0x1180080e02458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1164"             ,	   0x1180080e02460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1165"             ,	   0x1180080e02468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1166"             ,	   0x1180080e02470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1167"             ,	   0x1180080e02478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1168"             ,	   0x1180080e02480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1169"             ,	   0x1180080e02488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1170"             ,	   0x1180080e02490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1171"             ,	   0x1180080e02498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1172"             ,	   0x1180080e024a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1173"             ,	   0x1180080e024a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1174"             ,	   0x1180080e024b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1175"             ,	   0x1180080e024b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1176"             ,	   0x1180080e024c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1177"             ,	   0x1180080e024c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1178"             ,	   0x1180080e024d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1179"             ,	   0x1180080e024d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1180"             ,	   0x1180080e024e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1181"             ,	   0x1180080e024e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1182"             ,	   0x1180080e024f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1183"             ,	   0x1180080e024f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1184"             ,	   0x1180080e02500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1185"             ,	   0x1180080e02508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1186"             ,	   0x1180080e02510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1187"             ,	   0x1180080e02518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1188"             ,	   0x1180080e02520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1189"             ,	   0x1180080e02528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1190"             ,	   0x1180080e02530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1191"             ,	   0x1180080e02538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1192"             ,	   0x1180080e02540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1193"             ,	   0x1180080e02548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1194"             ,	   0x1180080e02550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1195"             ,	   0x1180080e02558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1196"             ,	   0x1180080e02560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1197"             ,	   0x1180080e02568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1198"             ,	   0x1180080e02570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1199"             ,	   0x1180080e02578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1200"             ,	   0x1180080e02580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1201"             ,	   0x1180080e02588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1202"             ,	   0x1180080e02590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1203"             ,	   0x1180080e02598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1204"             ,	   0x1180080e025a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1205"             ,	   0x1180080e025a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1206"             ,	   0x1180080e025b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1207"             ,	   0x1180080e025b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1208"             ,	   0x1180080e025c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1209"             ,	   0x1180080e025c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1210"             ,	   0x1180080e025d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1211"             ,	   0x1180080e025d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1212"             ,	   0x1180080e025e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1213"             ,	   0x1180080e025e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1214"             ,	   0x1180080e025f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1215"             ,	   0x1180080e025f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1216"             ,	   0x1180080e02600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1217"             ,	   0x1180080e02608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1218"             ,	   0x1180080e02610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1219"             ,	   0x1180080e02618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1220"             ,	   0x1180080e02620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1221"             ,	   0x1180080e02628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1222"             ,	   0x1180080e02630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1223"             ,	   0x1180080e02638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1224"             ,	   0x1180080e02640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1225"             ,	   0x1180080e02648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1226"             ,	   0x1180080e02650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1227"             ,	   0x1180080e02658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1228"             ,	   0x1180080e02660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1229"             ,	   0x1180080e02668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1230"             ,	   0x1180080e02670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1231"             ,	   0x1180080e02678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1232"             ,	   0x1180080e02680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1233"             ,	   0x1180080e02688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1234"             ,	   0x1180080e02690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1235"             ,	   0x1180080e02698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1236"             ,	   0x1180080e026a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1237"             ,	   0x1180080e026a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1238"             ,	   0x1180080e026b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1239"             ,	   0x1180080e026b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1240"             ,	   0x1180080e026c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1241"             ,	   0x1180080e026c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1242"             ,	   0x1180080e026d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1243"             ,	   0x1180080e026d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1244"             ,	   0x1180080e026e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1245"             ,	   0x1180080e026e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1246"             ,	   0x1180080e026f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1247"             ,	   0x1180080e026f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1248"             ,	   0x1180080e02700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1249"             ,	   0x1180080e02708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1250"             ,	   0x1180080e02710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1251"             ,	   0x1180080e02718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1252"             ,	   0x1180080e02720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1253"             ,	   0x1180080e02728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1254"             ,	   0x1180080e02730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1255"             ,	   0x1180080e02738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1256"             ,	   0x1180080e02740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1257"             ,	   0x1180080e02748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1258"             ,	   0x1180080e02750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1259"             ,	   0x1180080e02758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1260"             ,	   0x1180080e02760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1261"             ,	   0x1180080e02768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1262"             ,	   0x1180080e02770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1263"             ,	   0x1180080e02778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1264"             ,	   0x1180080e02780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1265"             ,	   0x1180080e02788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1266"             ,	   0x1180080e02790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1267"             ,	   0x1180080e02798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1268"             ,	   0x1180080e027a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1269"             ,	   0x1180080e027a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1270"             ,	   0x1180080e027b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1271"             ,	   0x1180080e027b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1272"             ,	   0x1180080e027c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1273"             ,	   0x1180080e027c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1274"             ,	   0x1180080e027d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1275"             ,	   0x1180080e027d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1276"             ,	   0x1180080e027e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1277"             ,	   0x1180080e027e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1278"             ,	   0x1180080e027f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1279"             ,	   0x1180080e027f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1280"             ,	   0x1180080e02800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1281"             ,	   0x1180080e02808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1282"             ,	   0x1180080e02810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1283"             ,	   0x1180080e02818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1284"             ,	   0x1180080e02820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1285"             ,	   0x1180080e02828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1286"             ,	   0x1180080e02830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1287"             ,	   0x1180080e02838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1288"             ,	   0x1180080e02840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1289"             ,	   0x1180080e02848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1290"             ,	   0x1180080e02850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1291"             ,	   0x1180080e02858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1292"             ,	   0x1180080e02860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1293"             ,	   0x1180080e02868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1294"             ,	   0x1180080e02870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1295"             ,	   0x1180080e02878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1296"             ,	   0x1180080e02880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1297"             ,	   0x1180080e02888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1298"             ,	   0x1180080e02890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1299"             ,	   0x1180080e02898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1300"             ,	   0x1180080e028a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1301"             ,	   0x1180080e028a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1302"             ,	   0x1180080e028b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1303"             ,	   0x1180080e028b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1304"             ,	   0x1180080e028c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1305"             ,	   0x1180080e028c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1306"             ,	   0x1180080e028d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1307"             ,	   0x1180080e028d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1308"             ,	   0x1180080e028e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1309"             ,	   0x1180080e028e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1310"             ,	   0x1180080e028f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1311"             ,	   0x1180080e028f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1312"             ,	   0x1180080e02900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1313"             ,	   0x1180080e02908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1314"             ,	   0x1180080e02910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1315"             ,	   0x1180080e02918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1316"             ,	   0x1180080e02920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1317"             ,	   0x1180080e02928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1318"             ,	   0x1180080e02930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1319"             ,	   0x1180080e02938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1320"             ,	   0x1180080e02940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1321"             ,	   0x1180080e02948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1322"             ,	   0x1180080e02950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1323"             ,	   0x1180080e02958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1324"             ,	   0x1180080e02960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1325"             ,	   0x1180080e02968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1326"             ,	   0x1180080e02970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1327"             ,	   0x1180080e02978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1328"             ,	   0x1180080e02980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1329"             ,	   0x1180080e02988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1330"             ,	   0x1180080e02990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1331"             ,	   0x1180080e02998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1332"             ,	   0x1180080e029a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1333"             ,	   0x1180080e029a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1334"             ,	   0x1180080e029b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1335"             ,	   0x1180080e029b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1336"             ,	   0x1180080e029c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1337"             ,	   0x1180080e029c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1338"             ,	   0x1180080e029d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1339"             ,	   0x1180080e029d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1340"             ,	   0x1180080e029e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1341"             ,	   0x1180080e029e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1342"             ,	   0x1180080e029f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1343"             ,	   0x1180080e029f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1344"             ,	   0x1180080e02a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1345"             ,	   0x1180080e02a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1346"             ,	   0x1180080e02a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1347"             ,	   0x1180080e02a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1348"             ,	   0x1180080e02a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1349"             ,	   0x1180080e02a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1350"             ,	   0x1180080e02a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1351"             ,	   0x1180080e02a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1352"             ,	   0x1180080e02a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1353"             ,	   0x1180080e02a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1354"             ,	   0x1180080e02a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1355"             ,	   0x1180080e02a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1356"             ,	   0x1180080e02a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1357"             ,	   0x1180080e02a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1358"             ,	   0x1180080e02a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1359"             ,	   0x1180080e02a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1360"             ,	   0x1180080e02a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1361"             ,	   0x1180080e02a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1362"             ,	   0x1180080e02a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1363"             ,	   0x1180080e02a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1364"             ,	   0x1180080e02aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1365"             ,	   0x1180080e02aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1366"             ,	   0x1180080e02ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1367"             ,	   0x1180080e02ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1368"             ,	   0x1180080e02ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1369"             ,	   0x1180080e02ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1370"             ,	   0x1180080e02ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1371"             ,	   0x1180080e02ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1372"             ,	   0x1180080e02ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1373"             ,	   0x1180080e02ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1374"             ,	   0x1180080e02af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1375"             ,	   0x1180080e02af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1376"             ,	   0x1180080e02b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1377"             ,	   0x1180080e02b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1378"             ,	   0x1180080e02b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1379"             ,	   0x1180080e02b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1380"             ,	   0x1180080e02b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1381"             ,	   0x1180080e02b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1382"             ,	   0x1180080e02b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1383"             ,	   0x1180080e02b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1384"             ,	   0x1180080e02b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1385"             ,	   0x1180080e02b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1386"             ,	   0x1180080e02b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1387"             ,	   0x1180080e02b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1388"             ,	   0x1180080e02b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1389"             ,	   0x1180080e02b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1390"             ,	   0x1180080e02b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1391"             ,	   0x1180080e02b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1392"             ,	   0x1180080e02b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1393"             ,	   0x1180080e02b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1394"             ,	   0x1180080e02b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1395"             ,	   0x1180080e02b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1396"             ,	   0x1180080e02ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1397"             ,	   0x1180080e02ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1398"             ,	   0x1180080e02bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1399"             ,	   0x1180080e02bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1400"             ,	   0x1180080e02bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1401"             ,	   0x1180080e02bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1402"             ,	   0x1180080e02bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1403"             ,	   0x1180080e02bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1404"             ,	   0x1180080e02be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1405"             ,	   0x1180080e02be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1406"             ,	   0x1180080e02bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1407"             ,	   0x1180080e02bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1408"             ,	   0x1180080e02c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1409"             ,	   0x1180080e02c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1410"             ,	   0x1180080e02c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1411"             ,	   0x1180080e02c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1412"             ,	   0x1180080e02c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1413"             ,	   0x1180080e02c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1414"             ,	   0x1180080e02c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1415"             ,	   0x1180080e02c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1416"             ,	   0x1180080e02c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1417"             ,	   0x1180080e02c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1418"             ,	   0x1180080e02c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1419"             ,	   0x1180080e02c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1420"             ,	   0x1180080e02c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1421"             ,	   0x1180080e02c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1422"             ,	   0x1180080e02c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1423"             ,	   0x1180080e02c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1424"             ,	   0x1180080e02c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1425"             ,	   0x1180080e02c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1426"             ,	   0x1180080e02c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1427"             ,	   0x1180080e02c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1428"             ,	   0x1180080e02ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1429"             ,	   0x1180080e02ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1430"             ,	   0x1180080e02cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1431"             ,	   0x1180080e02cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1432"             ,	   0x1180080e02cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1433"             ,	   0x1180080e02cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1434"             ,	   0x1180080e02cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1435"             ,	   0x1180080e02cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1436"             ,	   0x1180080e02ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1437"             ,	   0x1180080e02ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1438"             ,	   0x1180080e02cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1439"             ,	   0x1180080e02cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1440"             ,	   0x1180080e02d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1441"             ,	   0x1180080e02d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1442"             ,	   0x1180080e02d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1443"             ,	   0x1180080e02d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1444"             ,	   0x1180080e02d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1445"             ,	   0x1180080e02d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1446"             ,	   0x1180080e02d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1447"             ,	   0x1180080e02d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1448"             ,	   0x1180080e02d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1449"             ,	   0x1180080e02d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1450"             ,	   0x1180080e02d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1451"             ,	   0x1180080e02d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1452"             ,	   0x1180080e02d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1453"             ,	   0x1180080e02d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1454"             ,	   0x1180080e02d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1455"             ,	   0x1180080e02d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1456"             ,	   0x1180080e02d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1457"             ,	   0x1180080e02d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1458"             ,	   0x1180080e02d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1459"             ,	   0x1180080e02d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1460"             ,	   0x1180080e02da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1461"             ,	   0x1180080e02da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1462"             ,	   0x1180080e02db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1463"             ,	   0x1180080e02db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1464"             ,	   0x1180080e02dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1465"             ,	   0x1180080e02dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1466"             ,	   0x1180080e02dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1467"             ,	   0x1180080e02dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1468"             ,	   0x1180080e02de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1469"             ,	   0x1180080e02de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1470"             ,	   0x1180080e02df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1471"             ,	   0x1180080e02df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1472"             ,	   0x1180080e02e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1473"             ,	   0x1180080e02e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1474"             ,	   0x1180080e02e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1475"             ,	   0x1180080e02e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1476"             ,	   0x1180080e02e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1477"             ,	   0x1180080e02e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1478"             ,	   0x1180080e02e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1479"             ,	   0x1180080e02e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1480"             ,	   0x1180080e02e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1481"             ,	   0x1180080e02e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1482"             ,	   0x1180080e02e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1483"             ,	   0x1180080e02e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1484"             ,	   0x1180080e02e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1485"             ,	   0x1180080e02e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1486"             ,	   0x1180080e02e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1487"             ,	   0x1180080e02e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1488"             ,	   0x1180080e02e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1489"             ,	   0x1180080e02e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1490"             ,	   0x1180080e02e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1491"             ,	   0x1180080e02e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1492"             ,	   0x1180080e02ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1493"             ,	   0x1180080e02ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1494"             ,	   0x1180080e02eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1495"             ,	   0x1180080e02eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1496"             ,	   0x1180080e02ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1497"             ,	   0x1180080e02ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1498"             ,	   0x1180080e02ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1499"             ,	   0x1180080e02ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1500"             ,	   0x1180080e02ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1501"             ,	   0x1180080e02ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1502"             ,	   0x1180080e02ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1503"             ,	   0x1180080e02ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1504"             ,	   0x1180080e02f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1505"             ,	   0x1180080e02f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1506"             ,	   0x1180080e02f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1507"             ,	   0x1180080e02f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1508"             ,	   0x1180080e02f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1509"             ,	   0x1180080e02f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1510"             ,	   0x1180080e02f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1511"             ,	   0x1180080e02f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1512"             ,	   0x1180080e02f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1513"             ,	   0x1180080e02f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1514"             ,	   0x1180080e02f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1515"             ,	   0x1180080e02f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1516"             ,	   0x1180080e02f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1517"             ,	   0x1180080e02f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1518"             ,	   0x1180080e02f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1519"             ,	   0x1180080e02f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1520"             ,	   0x1180080e02f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1521"             ,	   0x1180080e02f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1522"             ,	   0x1180080e02f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1523"             ,	   0x1180080e02f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1524"             ,	   0x1180080e02fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1525"             ,	   0x1180080e02fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1526"             ,	   0x1180080e02fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1527"             ,	   0x1180080e02fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1528"             ,	   0x1180080e02fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1529"             ,	   0x1180080e02fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1530"             ,	   0x1180080e02fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1531"             ,	   0x1180080e02fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1532"             ,	   0x1180080e02fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1533"             ,	   0x1180080e02fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1534"             ,	   0x1180080e02ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1535"             ,	   0x1180080e02ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1536"             ,	   0x1180080e03000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1537"             ,	   0x1180080e03008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1538"             ,	   0x1180080e03010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1539"             ,	   0x1180080e03018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1540"             ,	   0x1180080e03020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1541"             ,	   0x1180080e03028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1542"             ,	   0x1180080e03030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1543"             ,	   0x1180080e03038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1544"             ,	   0x1180080e03040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1545"             ,	   0x1180080e03048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1546"             ,	   0x1180080e03050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1547"             ,	   0x1180080e03058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1548"             ,	   0x1180080e03060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1549"             ,	   0x1180080e03068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1550"             ,	   0x1180080e03070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1551"             ,	   0x1180080e03078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1552"             ,	   0x1180080e03080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1553"             ,	   0x1180080e03088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1554"             ,	   0x1180080e03090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1555"             ,	   0x1180080e03098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1556"             ,	   0x1180080e030a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1557"             ,	   0x1180080e030a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1558"             ,	   0x1180080e030b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1559"             ,	   0x1180080e030b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1560"             ,	   0x1180080e030c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1561"             ,	   0x1180080e030c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1562"             ,	   0x1180080e030d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1563"             ,	   0x1180080e030d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1564"             ,	   0x1180080e030e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1565"             ,	   0x1180080e030e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1566"             ,	   0x1180080e030f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1567"             ,	   0x1180080e030f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1568"             ,	   0x1180080e03100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1569"             ,	   0x1180080e03108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1570"             ,	   0x1180080e03110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1571"             ,	   0x1180080e03118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1572"             ,	   0x1180080e03120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1573"             ,	   0x1180080e03128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1574"             ,	   0x1180080e03130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1575"             ,	   0x1180080e03138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1576"             ,	   0x1180080e03140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1577"             ,	   0x1180080e03148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1578"             ,	   0x1180080e03150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1579"             ,	   0x1180080e03158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1580"             ,	   0x1180080e03160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1581"             ,	   0x1180080e03168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1582"             ,	   0x1180080e03170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1583"             ,	   0x1180080e03178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1584"             ,	   0x1180080e03180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1585"             ,	   0x1180080e03188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1586"             ,	   0x1180080e03190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1587"             ,	   0x1180080e03198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1588"             ,	   0x1180080e031a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1589"             ,	   0x1180080e031a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1590"             ,	   0x1180080e031b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1591"             ,	   0x1180080e031b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1592"             ,	   0x1180080e031c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1593"             ,	   0x1180080e031c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1594"             ,	   0x1180080e031d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1595"             ,	   0x1180080e031d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1596"             ,	   0x1180080e031e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1597"             ,	   0x1180080e031e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1598"             ,	   0x1180080e031f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1599"             ,	   0x1180080e031f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1600"             ,	   0x1180080e03200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1601"             ,	   0x1180080e03208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1602"             ,	   0x1180080e03210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1603"             ,	   0x1180080e03218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1604"             ,	   0x1180080e03220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1605"             ,	   0x1180080e03228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1606"             ,	   0x1180080e03230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1607"             ,	   0x1180080e03238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1608"             ,	   0x1180080e03240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1609"             ,	   0x1180080e03248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1610"             ,	   0x1180080e03250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1611"             ,	   0x1180080e03258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1612"             ,	   0x1180080e03260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1613"             ,	   0x1180080e03268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1614"             ,	   0x1180080e03270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1615"             ,	   0x1180080e03278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1616"             ,	   0x1180080e03280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1617"             ,	   0x1180080e03288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1618"             ,	   0x1180080e03290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1619"             ,	   0x1180080e03298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1620"             ,	   0x1180080e032a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1621"             ,	   0x1180080e032a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1622"             ,	   0x1180080e032b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1623"             ,	   0x1180080e032b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1624"             ,	   0x1180080e032c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1625"             ,	   0x1180080e032c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1626"             ,	   0x1180080e032d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1627"             ,	   0x1180080e032d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1628"             ,	   0x1180080e032e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1629"             ,	   0x1180080e032e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1630"             ,	   0x1180080e032f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1631"             ,	   0x1180080e032f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1632"             ,	   0x1180080e03300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1633"             ,	   0x1180080e03308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1634"             ,	   0x1180080e03310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1635"             ,	   0x1180080e03318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1636"             ,	   0x1180080e03320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1637"             ,	   0x1180080e03328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1638"             ,	   0x1180080e03330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1639"             ,	   0x1180080e03338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1640"             ,	   0x1180080e03340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1641"             ,	   0x1180080e03348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1642"             ,	   0x1180080e03350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1643"             ,	   0x1180080e03358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1644"             ,	   0x1180080e03360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1645"             ,	   0x1180080e03368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1646"             ,	   0x1180080e03370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1647"             ,	   0x1180080e03378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1648"             ,	   0x1180080e03380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1649"             ,	   0x1180080e03388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1650"             ,	   0x1180080e03390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1651"             ,	   0x1180080e03398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1652"             ,	   0x1180080e033a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1653"             ,	   0x1180080e033a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1654"             ,	   0x1180080e033b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1655"             ,	   0x1180080e033b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1656"             ,	   0x1180080e033c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1657"             ,	   0x1180080e033c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1658"             ,	   0x1180080e033d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1659"             ,	   0x1180080e033d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1660"             ,	   0x1180080e033e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1661"             ,	   0x1180080e033e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1662"             ,	   0x1180080e033f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1663"             ,	   0x1180080e033f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1664"             ,	   0x1180080e03400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1665"             ,	   0x1180080e03408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1666"             ,	   0x1180080e03410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1667"             ,	   0x1180080e03418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1668"             ,	   0x1180080e03420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1669"             ,	   0x1180080e03428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1670"             ,	   0x1180080e03430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1671"             ,	   0x1180080e03438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1672"             ,	   0x1180080e03440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1673"             ,	   0x1180080e03448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1674"             ,	   0x1180080e03450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1675"             ,	   0x1180080e03458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1676"             ,	   0x1180080e03460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1677"             ,	   0x1180080e03468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1678"             ,	   0x1180080e03470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1679"             ,	   0x1180080e03478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1680"             ,	   0x1180080e03480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1681"             ,	   0x1180080e03488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1682"             ,	   0x1180080e03490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1683"             ,	   0x1180080e03498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1684"             ,	   0x1180080e034a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1685"             ,	   0x1180080e034a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1686"             ,	   0x1180080e034b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1687"             ,	   0x1180080e034b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1688"             ,	   0x1180080e034c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1689"             ,	   0x1180080e034c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1690"             ,	   0x1180080e034d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1691"             ,	   0x1180080e034d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1692"             ,	   0x1180080e034e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1693"             ,	   0x1180080e034e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1694"             ,	   0x1180080e034f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1695"             ,	   0x1180080e034f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1696"             ,	   0x1180080e03500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1697"             ,	   0x1180080e03508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1698"             ,	   0x1180080e03510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1699"             ,	   0x1180080e03518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1700"             ,	   0x1180080e03520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1701"             ,	   0x1180080e03528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1702"             ,	   0x1180080e03530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1703"             ,	   0x1180080e03538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1704"             ,	   0x1180080e03540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1705"             ,	   0x1180080e03548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1706"             ,	   0x1180080e03550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1707"             ,	   0x1180080e03558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1708"             ,	   0x1180080e03560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1709"             ,	   0x1180080e03568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1710"             ,	   0x1180080e03570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1711"             ,	   0x1180080e03578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1712"             ,	   0x1180080e03580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1713"             ,	   0x1180080e03588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1714"             ,	   0x1180080e03590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1715"             ,	   0x1180080e03598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1716"             ,	   0x1180080e035a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1717"             ,	   0x1180080e035a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1718"             ,	   0x1180080e035b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1719"             ,	   0x1180080e035b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1720"             ,	   0x1180080e035c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1721"             ,	   0x1180080e035c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1722"             ,	   0x1180080e035d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1723"             ,	   0x1180080e035d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1724"             ,	   0x1180080e035e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1725"             ,	   0x1180080e035e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1726"             ,	   0x1180080e035f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1727"             ,	   0x1180080e035f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1728"             ,	   0x1180080e03600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1729"             ,	   0x1180080e03608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1730"             ,	   0x1180080e03610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1731"             ,	   0x1180080e03618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1732"             ,	   0x1180080e03620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1733"             ,	   0x1180080e03628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1734"             ,	   0x1180080e03630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1735"             ,	   0x1180080e03638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1736"             ,	   0x1180080e03640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1737"             ,	   0x1180080e03648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1738"             ,	   0x1180080e03650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1739"             ,	   0x1180080e03658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1740"             ,	   0x1180080e03660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1741"             ,	   0x1180080e03668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1742"             ,	   0x1180080e03670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1743"             ,	   0x1180080e03678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1744"             ,	   0x1180080e03680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1745"             ,	   0x1180080e03688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1746"             ,	   0x1180080e03690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1747"             ,	   0x1180080e03698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1748"             ,	   0x1180080e036a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1749"             ,	   0x1180080e036a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1750"             ,	   0x1180080e036b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1751"             ,	   0x1180080e036b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1752"             ,	   0x1180080e036c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1753"             ,	   0x1180080e036c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1754"             ,	   0x1180080e036d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1755"             ,	   0x1180080e036d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1756"             ,	   0x1180080e036e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1757"             ,	   0x1180080e036e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1758"             ,	   0x1180080e036f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1759"             ,	   0x1180080e036f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1760"             ,	   0x1180080e03700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1761"             ,	   0x1180080e03708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1762"             ,	   0x1180080e03710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1763"             ,	   0x1180080e03718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1764"             ,	   0x1180080e03720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1765"             ,	   0x1180080e03728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1766"             ,	   0x1180080e03730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1767"             ,	   0x1180080e03738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1768"             ,	   0x1180080e03740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1769"             ,	   0x1180080e03748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1770"             ,	   0x1180080e03750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1771"             ,	   0x1180080e03758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1772"             ,	   0x1180080e03760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1773"             ,	   0x1180080e03768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1774"             ,	   0x1180080e03770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1775"             ,	   0x1180080e03778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1776"             ,	   0x1180080e03780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1777"             ,	   0x1180080e03788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1778"             ,	   0x1180080e03790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1779"             ,	   0x1180080e03798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1780"             ,	   0x1180080e037a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1781"             ,	   0x1180080e037a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1782"             ,	   0x1180080e037b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1783"             ,	   0x1180080e037b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1784"             ,	   0x1180080e037c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1785"             ,	   0x1180080e037c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1786"             ,	   0x1180080e037d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1787"             ,	   0x1180080e037d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1788"             ,	   0x1180080e037e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1789"             ,	   0x1180080e037e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1790"             ,	   0x1180080e037f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1791"             ,	   0x1180080e037f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1792"             ,	   0x1180080e03800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1793"             ,	   0x1180080e03808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1794"             ,	   0x1180080e03810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1795"             ,	   0x1180080e03818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1796"             ,	   0x1180080e03820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1797"             ,	   0x1180080e03828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1798"             ,	   0x1180080e03830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1799"             ,	   0x1180080e03838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1800"             ,	   0x1180080e03840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1801"             ,	   0x1180080e03848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1802"             ,	   0x1180080e03850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1803"             ,	   0x1180080e03858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1804"             ,	   0x1180080e03860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1805"             ,	   0x1180080e03868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1806"             ,	   0x1180080e03870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1807"             ,	   0x1180080e03878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1808"             ,	   0x1180080e03880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1809"             ,	   0x1180080e03888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1810"             ,	   0x1180080e03890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1811"             ,	   0x1180080e03898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1812"             ,	   0x1180080e038a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1813"             ,	   0x1180080e038a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1814"             ,	   0x1180080e038b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1815"             ,	   0x1180080e038b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1816"             ,	   0x1180080e038c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1817"             ,	   0x1180080e038c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1818"             ,	   0x1180080e038d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1819"             ,	   0x1180080e038d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1820"             ,	   0x1180080e038e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1821"             ,	   0x1180080e038e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1822"             ,	   0x1180080e038f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1823"             ,	   0x1180080e038f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1824"             ,	   0x1180080e03900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1825"             ,	   0x1180080e03908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1826"             ,	   0x1180080e03910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1827"             ,	   0x1180080e03918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1828"             ,	   0x1180080e03920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1829"             ,	   0x1180080e03928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1830"             ,	   0x1180080e03930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1831"             ,	   0x1180080e03938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1832"             ,	   0x1180080e03940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1833"             ,	   0x1180080e03948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1834"             ,	   0x1180080e03950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1835"             ,	   0x1180080e03958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1836"             ,	   0x1180080e03960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1837"             ,	   0x1180080e03968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1838"             ,	   0x1180080e03970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1839"             ,	   0x1180080e03978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1840"             ,	   0x1180080e03980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1841"             ,	   0x1180080e03988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1842"             ,	   0x1180080e03990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1843"             ,	   0x1180080e03998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1844"             ,	   0x1180080e039a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1845"             ,	   0x1180080e039a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1846"             ,	   0x1180080e039b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1847"             ,	   0x1180080e039b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1848"             ,	   0x1180080e039c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1849"             ,	   0x1180080e039c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1850"             ,	   0x1180080e039d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1851"             ,	   0x1180080e039d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1852"             ,	   0x1180080e039e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1853"             ,	   0x1180080e039e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1854"             ,	   0x1180080e039f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1855"             ,	   0x1180080e039f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1856"             ,	   0x1180080e03a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1857"             ,	   0x1180080e03a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1858"             ,	   0x1180080e03a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1859"             ,	   0x1180080e03a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1860"             ,	   0x1180080e03a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1861"             ,	   0x1180080e03a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1862"             ,	   0x1180080e03a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1863"             ,	   0x1180080e03a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1864"             ,	   0x1180080e03a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1865"             ,	   0x1180080e03a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1866"             ,	   0x1180080e03a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1867"             ,	   0x1180080e03a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1868"             ,	   0x1180080e03a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1869"             ,	   0x1180080e03a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1870"             ,	   0x1180080e03a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1871"             ,	   0x1180080e03a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1872"             ,	   0x1180080e03a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1873"             ,	   0x1180080e03a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1874"             ,	   0x1180080e03a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1875"             ,	   0x1180080e03a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1876"             ,	   0x1180080e03aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1877"             ,	   0x1180080e03aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1878"             ,	   0x1180080e03ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1879"             ,	   0x1180080e03ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1880"             ,	   0x1180080e03ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1881"             ,	   0x1180080e03ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1882"             ,	   0x1180080e03ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1883"             ,	   0x1180080e03ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1884"             ,	   0x1180080e03ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1885"             ,	   0x1180080e03ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1886"             ,	   0x1180080e03af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1887"             ,	   0x1180080e03af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1888"             ,	   0x1180080e03b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1889"             ,	   0x1180080e03b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1890"             ,	   0x1180080e03b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1891"             ,	   0x1180080e03b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1892"             ,	   0x1180080e03b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1893"             ,	   0x1180080e03b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1894"             ,	   0x1180080e03b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1895"             ,	   0x1180080e03b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1896"             ,	   0x1180080e03b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1897"             ,	   0x1180080e03b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1898"             ,	   0x1180080e03b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1899"             ,	   0x1180080e03b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1900"             ,	   0x1180080e03b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1901"             ,	   0x1180080e03b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1902"             ,	   0x1180080e03b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1903"             ,	   0x1180080e03b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1904"             ,	   0x1180080e03b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1905"             ,	   0x1180080e03b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1906"             ,	   0x1180080e03b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1907"             ,	   0x1180080e03b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1908"             ,	   0x1180080e03ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1909"             ,	   0x1180080e03ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1910"             ,	   0x1180080e03bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1911"             ,	   0x1180080e03bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1912"             ,	   0x1180080e03bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1913"             ,	   0x1180080e03bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1914"             ,	   0x1180080e03bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1915"             ,	   0x1180080e03bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1916"             ,	   0x1180080e03be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1917"             ,	   0x1180080e03be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1918"             ,	   0x1180080e03bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1919"             ,	   0x1180080e03bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1920"             ,	   0x1180080e03c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1921"             ,	   0x1180080e03c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1922"             ,	   0x1180080e03c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1923"             ,	   0x1180080e03c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1924"             ,	   0x1180080e03c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1925"             ,	   0x1180080e03c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1926"             ,	   0x1180080e03c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1927"             ,	   0x1180080e03c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1928"             ,	   0x1180080e03c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1929"             ,	   0x1180080e03c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1930"             ,	   0x1180080e03c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1931"             ,	   0x1180080e03c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1932"             ,	   0x1180080e03c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1933"             ,	   0x1180080e03c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1934"             ,	   0x1180080e03c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1935"             ,	   0x1180080e03c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1936"             ,	   0x1180080e03c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1937"             ,	   0x1180080e03c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1938"             ,	   0x1180080e03c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1939"             ,	   0x1180080e03c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1940"             ,	   0x1180080e03ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1941"             ,	   0x1180080e03ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1942"             ,	   0x1180080e03cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1943"             ,	   0x1180080e03cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1944"             ,	   0x1180080e03cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1945"             ,	   0x1180080e03cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1946"             ,	   0x1180080e03cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1947"             ,	   0x1180080e03cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1948"             ,	   0x1180080e03ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1949"             ,	   0x1180080e03ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1950"             ,	   0x1180080e03cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1951"             ,	   0x1180080e03cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1952"             ,	   0x1180080e03d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1953"             ,	   0x1180080e03d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1954"             ,	   0x1180080e03d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1955"             ,	   0x1180080e03d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1956"             ,	   0x1180080e03d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1957"             ,	   0x1180080e03d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1958"             ,	   0x1180080e03d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1959"             ,	   0x1180080e03d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1960"             ,	   0x1180080e03d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1961"             ,	   0x1180080e03d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1962"             ,	   0x1180080e03d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1963"             ,	   0x1180080e03d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1964"             ,	   0x1180080e03d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1965"             ,	   0x1180080e03d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1966"             ,	   0x1180080e03d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1967"             ,	   0x1180080e03d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1968"             ,	   0x1180080e03d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1969"             ,	   0x1180080e03d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1970"             ,	   0x1180080e03d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1971"             ,	   0x1180080e03d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1972"             ,	   0x1180080e03da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1973"             ,	   0x1180080e03da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1974"             ,	   0x1180080e03db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1975"             ,	   0x1180080e03db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1976"             ,	   0x1180080e03dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1977"             ,	   0x1180080e03dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1978"             ,	   0x1180080e03dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1979"             ,	   0x1180080e03dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1980"             ,	   0x1180080e03de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1981"             ,	   0x1180080e03de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1982"             ,	   0x1180080e03df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1983"             ,	   0x1180080e03df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1984"             ,	   0x1180080e03e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1985"             ,	   0x1180080e03e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1986"             ,	   0x1180080e03e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1987"             ,	   0x1180080e03e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1988"             ,	   0x1180080e03e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1989"             ,	   0x1180080e03e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1990"             ,	   0x1180080e03e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1991"             ,	   0x1180080e03e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1992"             ,	   0x1180080e03e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1993"             ,	   0x1180080e03e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1994"             ,	   0x1180080e03e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1995"             ,	   0x1180080e03e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1996"             ,	   0x1180080e03e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1997"             ,	   0x1180080e03e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1998"             ,	   0x1180080e03e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP1999"             ,	   0x1180080e03e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2000"             ,	   0x1180080e03e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2001"             ,	   0x1180080e03e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2002"             ,	   0x1180080e03e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2003"             ,	   0x1180080e03e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2004"             ,	   0x1180080e03ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2005"             ,	   0x1180080e03ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2006"             ,	   0x1180080e03eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2007"             ,	   0x1180080e03eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2008"             ,	   0x1180080e03ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2009"             ,	   0x1180080e03ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2010"             ,	   0x1180080e03ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2011"             ,	   0x1180080e03ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2012"             ,	   0x1180080e03ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2013"             ,	   0x1180080e03ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2014"             ,	   0x1180080e03ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2015"             ,	   0x1180080e03ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2016"             ,	   0x1180080e03f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2017"             ,	   0x1180080e03f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2018"             ,	   0x1180080e03f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2019"             ,	   0x1180080e03f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2020"             ,	   0x1180080e03f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2021"             ,	   0x1180080e03f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2022"             ,	   0x1180080e03f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2023"             ,	   0x1180080e03f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2024"             ,	   0x1180080e03f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2025"             ,	   0x1180080e03f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2026"             ,	   0x1180080e03f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2027"             ,	   0x1180080e03f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2028"             ,	   0x1180080e03f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2029"             ,	   0x1180080e03f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2030"             ,	   0x1180080e03f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2031"             ,	   0x1180080e03f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2032"             ,	   0x1180080e03f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2033"             ,	   0x1180080e03f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2034"             ,	   0x1180080e03f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2035"             ,	   0x1180080e03f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2036"             ,	   0x1180080e03fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2037"             ,	   0x1180080e03fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2038"             ,	   0x1180080e03fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2039"             ,	   0x1180080e03fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2040"             ,	   0x1180080e03fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2041"             ,	   0x1180080e03fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2042"             ,	   0x1180080e03fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2043"             ,	   0x1180080e03fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2044"             ,	   0x1180080e03fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2045"             ,	   0x1180080e03fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2046"             ,	   0x1180080e03ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2047"             ,	   0x1180080e03ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2048"             ,	   0x1180080e04000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2049"             ,	   0x1180080e04008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2050"             ,	   0x1180080e04010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2051"             ,	   0x1180080e04018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2052"             ,	   0x1180080e04020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2053"             ,	   0x1180080e04028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2054"             ,	   0x1180080e04030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2055"             ,	   0x1180080e04038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2056"             ,	   0x1180080e04040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2057"             ,	   0x1180080e04048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2058"             ,	   0x1180080e04050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2059"             ,	   0x1180080e04058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2060"             ,	   0x1180080e04060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2061"             ,	   0x1180080e04068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2062"             ,	   0x1180080e04070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2063"             ,	   0x1180080e04078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2064"             ,	   0x1180080e04080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2065"             ,	   0x1180080e04088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2066"             ,	   0x1180080e04090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2067"             ,	   0x1180080e04098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2068"             ,	   0x1180080e040a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2069"             ,	   0x1180080e040a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2070"             ,	   0x1180080e040b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2071"             ,	   0x1180080e040b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2072"             ,	   0x1180080e040c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2073"             ,	   0x1180080e040c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2074"             ,	   0x1180080e040d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2075"             ,	   0x1180080e040d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2076"             ,	   0x1180080e040e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2077"             ,	   0x1180080e040e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2078"             ,	   0x1180080e040f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2079"             ,	   0x1180080e040f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2080"             ,	   0x1180080e04100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2081"             ,	   0x1180080e04108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2082"             ,	   0x1180080e04110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2083"             ,	   0x1180080e04118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2084"             ,	   0x1180080e04120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2085"             ,	   0x1180080e04128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2086"             ,	   0x1180080e04130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2087"             ,	   0x1180080e04138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2088"             ,	   0x1180080e04140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2089"             ,	   0x1180080e04148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2090"             ,	   0x1180080e04150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2091"             ,	   0x1180080e04158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2092"             ,	   0x1180080e04160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2093"             ,	   0x1180080e04168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2094"             ,	   0x1180080e04170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2095"             ,	   0x1180080e04178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2096"             ,	   0x1180080e04180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2097"             ,	   0x1180080e04188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2098"             ,	   0x1180080e04190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2099"             ,	   0x1180080e04198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2100"             ,	   0x1180080e041a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2101"             ,	   0x1180080e041a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2102"             ,	   0x1180080e041b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2103"             ,	   0x1180080e041b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2104"             ,	   0x1180080e041c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2105"             ,	   0x1180080e041c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2106"             ,	   0x1180080e041d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2107"             ,	   0x1180080e041d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2108"             ,	   0x1180080e041e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2109"             ,	   0x1180080e041e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2110"             ,	   0x1180080e041f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2111"             ,	   0x1180080e041f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2112"             ,	   0x1180080e04200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2113"             ,	   0x1180080e04208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2114"             ,	   0x1180080e04210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2115"             ,	   0x1180080e04218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2116"             ,	   0x1180080e04220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2117"             ,	   0x1180080e04228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2118"             ,	   0x1180080e04230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2119"             ,	   0x1180080e04238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2120"             ,	   0x1180080e04240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2121"             ,	   0x1180080e04248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2122"             ,	   0x1180080e04250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2123"             ,	   0x1180080e04258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2124"             ,	   0x1180080e04260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2125"             ,	   0x1180080e04268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2126"             ,	   0x1180080e04270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2127"             ,	   0x1180080e04278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2128"             ,	   0x1180080e04280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2129"             ,	   0x1180080e04288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2130"             ,	   0x1180080e04290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2131"             ,	   0x1180080e04298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2132"             ,	   0x1180080e042a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2133"             ,	   0x1180080e042a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2134"             ,	   0x1180080e042b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2135"             ,	   0x1180080e042b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2136"             ,	   0x1180080e042c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2137"             ,	   0x1180080e042c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2138"             ,	   0x1180080e042d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2139"             ,	   0x1180080e042d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2140"             ,	   0x1180080e042e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2141"             ,	   0x1180080e042e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2142"             ,	   0x1180080e042f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2143"             ,	   0x1180080e042f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2144"             ,	   0x1180080e04300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2145"             ,	   0x1180080e04308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2146"             ,	   0x1180080e04310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2147"             ,	   0x1180080e04318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2148"             ,	   0x1180080e04320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2149"             ,	   0x1180080e04328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2150"             ,	   0x1180080e04330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2151"             ,	   0x1180080e04338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2152"             ,	   0x1180080e04340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2153"             ,	   0x1180080e04348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2154"             ,	   0x1180080e04350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2155"             ,	   0x1180080e04358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2156"             ,	   0x1180080e04360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2157"             ,	   0x1180080e04368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2158"             ,	   0x1180080e04370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2159"             ,	   0x1180080e04378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2160"             ,	   0x1180080e04380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2161"             ,	   0x1180080e04388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2162"             ,	   0x1180080e04390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2163"             ,	   0x1180080e04398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2164"             ,	   0x1180080e043a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2165"             ,	   0x1180080e043a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2166"             ,	   0x1180080e043b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2167"             ,	   0x1180080e043b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2168"             ,	   0x1180080e043c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2169"             ,	   0x1180080e043c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2170"             ,	   0x1180080e043d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2171"             ,	   0x1180080e043d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2172"             ,	   0x1180080e043e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2173"             ,	   0x1180080e043e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2174"             ,	   0x1180080e043f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2175"             ,	   0x1180080e043f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2176"             ,	   0x1180080e04400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2177"             ,	   0x1180080e04408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2178"             ,	   0x1180080e04410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2179"             ,	   0x1180080e04418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2180"             ,	   0x1180080e04420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2181"             ,	   0x1180080e04428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2182"             ,	   0x1180080e04430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2183"             ,	   0x1180080e04438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2184"             ,	   0x1180080e04440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2185"             ,	   0x1180080e04448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2186"             ,	   0x1180080e04450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2187"             ,	   0x1180080e04458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2188"             ,	   0x1180080e04460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2189"             ,	   0x1180080e04468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2190"             ,	   0x1180080e04470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2191"             ,	   0x1180080e04478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2192"             ,	   0x1180080e04480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2193"             ,	   0x1180080e04488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2194"             ,	   0x1180080e04490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2195"             ,	   0x1180080e04498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2196"             ,	   0x1180080e044a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2197"             ,	   0x1180080e044a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2198"             ,	   0x1180080e044b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2199"             ,	   0x1180080e044b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2200"             ,	   0x1180080e044c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2201"             ,	   0x1180080e044c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2202"             ,	   0x1180080e044d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2203"             ,	   0x1180080e044d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2204"             ,	   0x1180080e044e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2205"             ,	   0x1180080e044e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2206"             ,	   0x1180080e044f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2207"             ,	   0x1180080e044f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2208"             ,	   0x1180080e04500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2209"             ,	   0x1180080e04508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2210"             ,	   0x1180080e04510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2211"             ,	   0x1180080e04518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2212"             ,	   0x1180080e04520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2213"             ,	   0x1180080e04528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2214"             ,	   0x1180080e04530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2215"             ,	   0x1180080e04538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2216"             ,	   0x1180080e04540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2217"             ,	   0x1180080e04548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2218"             ,	   0x1180080e04550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2219"             ,	   0x1180080e04558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2220"             ,	   0x1180080e04560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2221"             ,	   0x1180080e04568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2222"             ,	   0x1180080e04570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2223"             ,	   0x1180080e04578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2224"             ,	   0x1180080e04580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2225"             ,	   0x1180080e04588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2226"             ,	   0x1180080e04590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2227"             ,	   0x1180080e04598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2228"             ,	   0x1180080e045a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2229"             ,	   0x1180080e045a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2230"             ,	   0x1180080e045b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2231"             ,	   0x1180080e045b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2232"             ,	   0x1180080e045c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2233"             ,	   0x1180080e045c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2234"             ,	   0x1180080e045d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2235"             ,	   0x1180080e045d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2236"             ,	   0x1180080e045e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2237"             ,	   0x1180080e045e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2238"             ,	   0x1180080e045f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2239"             ,	   0x1180080e045f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2240"             ,	   0x1180080e04600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2241"             ,	   0x1180080e04608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2242"             ,	   0x1180080e04610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2243"             ,	   0x1180080e04618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2244"             ,	   0x1180080e04620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2245"             ,	   0x1180080e04628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2246"             ,	   0x1180080e04630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2247"             ,	   0x1180080e04638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2248"             ,	   0x1180080e04640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2249"             ,	   0x1180080e04648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2250"             ,	   0x1180080e04650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2251"             ,	   0x1180080e04658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2252"             ,	   0x1180080e04660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2253"             ,	   0x1180080e04668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2254"             ,	   0x1180080e04670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2255"             ,	   0x1180080e04678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2256"             ,	   0x1180080e04680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2257"             ,	   0x1180080e04688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2258"             ,	   0x1180080e04690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2259"             ,	   0x1180080e04698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2260"             ,	   0x1180080e046a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2261"             ,	   0x1180080e046a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2262"             ,	   0x1180080e046b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2263"             ,	   0x1180080e046b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2264"             ,	   0x1180080e046c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2265"             ,	   0x1180080e046c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2266"             ,	   0x1180080e046d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2267"             ,	   0x1180080e046d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2268"             ,	   0x1180080e046e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2269"             ,	   0x1180080e046e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2270"             ,	   0x1180080e046f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2271"             ,	   0x1180080e046f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2272"             ,	   0x1180080e04700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2273"             ,	   0x1180080e04708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2274"             ,	   0x1180080e04710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2275"             ,	   0x1180080e04718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2276"             ,	   0x1180080e04720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2277"             ,	   0x1180080e04728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2278"             ,	   0x1180080e04730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2279"             ,	   0x1180080e04738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2280"             ,	   0x1180080e04740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2281"             ,	   0x1180080e04748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2282"             ,	   0x1180080e04750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2283"             ,	   0x1180080e04758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2284"             ,	   0x1180080e04760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2285"             ,	   0x1180080e04768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2286"             ,	   0x1180080e04770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2287"             ,	   0x1180080e04778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2288"             ,	   0x1180080e04780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2289"             ,	   0x1180080e04788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2290"             ,	   0x1180080e04790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2291"             ,	   0x1180080e04798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2292"             ,	   0x1180080e047a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2293"             ,	   0x1180080e047a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2294"             ,	   0x1180080e047b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2295"             ,	   0x1180080e047b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2296"             ,	   0x1180080e047c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2297"             ,	   0x1180080e047c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2298"             ,	   0x1180080e047d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2299"             ,	   0x1180080e047d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2300"             ,	   0x1180080e047e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2301"             ,	   0x1180080e047e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2302"             ,	   0x1180080e047f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2303"             ,	   0x1180080e047f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2304"             ,	   0x1180080e04800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2305"             ,	   0x1180080e04808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2306"             ,	   0x1180080e04810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2307"             ,	   0x1180080e04818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2308"             ,	   0x1180080e04820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2309"             ,	   0x1180080e04828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2310"             ,	   0x1180080e04830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2311"             ,	   0x1180080e04838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2312"             ,	   0x1180080e04840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2313"             ,	   0x1180080e04848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2314"             ,	   0x1180080e04850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2315"             ,	   0x1180080e04858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2316"             ,	   0x1180080e04860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2317"             ,	   0x1180080e04868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2318"             ,	   0x1180080e04870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2319"             ,	   0x1180080e04878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2320"             ,	   0x1180080e04880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2321"             ,	   0x1180080e04888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2322"             ,	   0x1180080e04890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2323"             ,	   0x1180080e04898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2324"             ,	   0x1180080e048a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2325"             ,	   0x1180080e048a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2326"             ,	   0x1180080e048b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2327"             ,	   0x1180080e048b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2328"             ,	   0x1180080e048c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2329"             ,	   0x1180080e048c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2330"             ,	   0x1180080e048d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2331"             ,	   0x1180080e048d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2332"             ,	   0x1180080e048e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2333"             ,	   0x1180080e048e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2334"             ,	   0x1180080e048f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2335"             ,	   0x1180080e048f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2336"             ,	   0x1180080e04900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2337"             ,	   0x1180080e04908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2338"             ,	   0x1180080e04910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2339"             ,	   0x1180080e04918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2340"             ,	   0x1180080e04920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2341"             ,	   0x1180080e04928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2342"             ,	   0x1180080e04930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2343"             ,	   0x1180080e04938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2344"             ,	   0x1180080e04940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2345"             ,	   0x1180080e04948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2346"             ,	   0x1180080e04950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2347"             ,	   0x1180080e04958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2348"             ,	   0x1180080e04960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2349"             ,	   0x1180080e04968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2350"             ,	   0x1180080e04970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2351"             ,	   0x1180080e04978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2352"             ,	   0x1180080e04980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2353"             ,	   0x1180080e04988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2354"             ,	   0x1180080e04990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2355"             ,	   0x1180080e04998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2356"             ,	   0x1180080e049a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2357"             ,	   0x1180080e049a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2358"             ,	   0x1180080e049b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2359"             ,	   0x1180080e049b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2360"             ,	   0x1180080e049c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2361"             ,	   0x1180080e049c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2362"             ,	   0x1180080e049d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2363"             ,	   0x1180080e049d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2364"             ,	   0x1180080e049e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2365"             ,	   0x1180080e049e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2366"             ,	   0x1180080e049f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2367"             ,	   0x1180080e049f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2368"             ,	   0x1180080e04a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2369"             ,	   0x1180080e04a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2370"             ,	   0x1180080e04a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2371"             ,	   0x1180080e04a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2372"             ,	   0x1180080e04a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2373"             ,	   0x1180080e04a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2374"             ,	   0x1180080e04a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2375"             ,	   0x1180080e04a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2376"             ,	   0x1180080e04a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2377"             ,	   0x1180080e04a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2378"             ,	   0x1180080e04a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2379"             ,	   0x1180080e04a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2380"             ,	   0x1180080e04a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2381"             ,	   0x1180080e04a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2382"             ,	   0x1180080e04a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2383"             ,	   0x1180080e04a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2384"             ,	   0x1180080e04a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2385"             ,	   0x1180080e04a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2386"             ,	   0x1180080e04a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2387"             ,	   0x1180080e04a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2388"             ,	   0x1180080e04aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2389"             ,	   0x1180080e04aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2390"             ,	   0x1180080e04ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2391"             ,	   0x1180080e04ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2392"             ,	   0x1180080e04ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2393"             ,	   0x1180080e04ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2394"             ,	   0x1180080e04ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2395"             ,	   0x1180080e04ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2396"             ,	   0x1180080e04ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2397"             ,	   0x1180080e04ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2398"             ,	   0x1180080e04af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2399"             ,	   0x1180080e04af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2400"             ,	   0x1180080e04b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2401"             ,	   0x1180080e04b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2402"             ,	   0x1180080e04b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2403"             ,	   0x1180080e04b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2404"             ,	   0x1180080e04b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2405"             ,	   0x1180080e04b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2406"             ,	   0x1180080e04b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2407"             ,	   0x1180080e04b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2408"             ,	   0x1180080e04b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2409"             ,	   0x1180080e04b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2410"             ,	   0x1180080e04b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2411"             ,	   0x1180080e04b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2412"             ,	   0x1180080e04b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2413"             ,	   0x1180080e04b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2414"             ,	   0x1180080e04b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2415"             ,	   0x1180080e04b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2416"             ,	   0x1180080e04b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2417"             ,	   0x1180080e04b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2418"             ,	   0x1180080e04b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2419"             ,	   0x1180080e04b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2420"             ,	   0x1180080e04ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2421"             ,	   0x1180080e04ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2422"             ,	   0x1180080e04bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2423"             ,	   0x1180080e04bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2424"             ,	   0x1180080e04bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2425"             ,	   0x1180080e04bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2426"             ,	   0x1180080e04bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2427"             ,	   0x1180080e04bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2428"             ,	   0x1180080e04be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2429"             ,	   0x1180080e04be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2430"             ,	   0x1180080e04bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2431"             ,	   0x1180080e04bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2432"             ,	   0x1180080e04c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2433"             ,	   0x1180080e04c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2434"             ,	   0x1180080e04c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2435"             ,	   0x1180080e04c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2436"             ,	   0x1180080e04c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2437"             ,	   0x1180080e04c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2438"             ,	   0x1180080e04c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2439"             ,	   0x1180080e04c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2440"             ,	   0x1180080e04c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2441"             ,	   0x1180080e04c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2442"             ,	   0x1180080e04c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2443"             ,	   0x1180080e04c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2444"             ,	   0x1180080e04c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2445"             ,	   0x1180080e04c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2446"             ,	   0x1180080e04c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2447"             ,	   0x1180080e04c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2448"             ,	   0x1180080e04c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2449"             ,	   0x1180080e04c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2450"             ,	   0x1180080e04c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2451"             ,	   0x1180080e04c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2452"             ,	   0x1180080e04ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2453"             ,	   0x1180080e04ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2454"             ,	   0x1180080e04cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2455"             ,	   0x1180080e04cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2456"             ,	   0x1180080e04cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2457"             ,	   0x1180080e04cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2458"             ,	   0x1180080e04cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2459"             ,	   0x1180080e04cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2460"             ,	   0x1180080e04ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2461"             ,	   0x1180080e04ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2462"             ,	   0x1180080e04cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2463"             ,	   0x1180080e04cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2464"             ,	   0x1180080e04d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2465"             ,	   0x1180080e04d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2466"             ,	   0x1180080e04d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2467"             ,	   0x1180080e04d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2468"             ,	   0x1180080e04d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2469"             ,	   0x1180080e04d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2470"             ,	   0x1180080e04d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2471"             ,	   0x1180080e04d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2472"             ,	   0x1180080e04d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2473"             ,	   0x1180080e04d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2474"             ,	   0x1180080e04d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2475"             ,	   0x1180080e04d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2476"             ,	   0x1180080e04d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2477"             ,	   0x1180080e04d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2478"             ,	   0x1180080e04d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2479"             ,	   0x1180080e04d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2480"             ,	   0x1180080e04d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2481"             ,	   0x1180080e04d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2482"             ,	   0x1180080e04d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2483"             ,	   0x1180080e04d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2484"             ,	   0x1180080e04da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2485"             ,	   0x1180080e04da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2486"             ,	   0x1180080e04db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2487"             ,	   0x1180080e04db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2488"             ,	   0x1180080e04dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2489"             ,	   0x1180080e04dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2490"             ,	   0x1180080e04dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2491"             ,	   0x1180080e04dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2492"             ,	   0x1180080e04de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2493"             ,	   0x1180080e04de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2494"             ,	   0x1180080e04df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2495"             ,	   0x1180080e04df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2496"             ,	   0x1180080e04e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2497"             ,	   0x1180080e04e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2498"             ,	   0x1180080e04e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2499"             ,	   0x1180080e04e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2500"             ,	   0x1180080e04e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2501"             ,	   0x1180080e04e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2502"             ,	   0x1180080e04e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2503"             ,	   0x1180080e04e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2504"             ,	   0x1180080e04e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2505"             ,	   0x1180080e04e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2506"             ,	   0x1180080e04e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2507"             ,	   0x1180080e04e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2508"             ,	   0x1180080e04e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2509"             ,	   0x1180080e04e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2510"             ,	   0x1180080e04e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2511"             ,	   0x1180080e04e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2512"             ,	   0x1180080e04e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2513"             ,	   0x1180080e04e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2514"             ,	   0x1180080e04e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2515"             ,	   0x1180080e04e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2516"             ,	   0x1180080e04ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2517"             ,	   0x1180080e04ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2518"             ,	   0x1180080e04eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2519"             ,	   0x1180080e04eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2520"             ,	   0x1180080e04ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2521"             ,	   0x1180080e04ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2522"             ,	   0x1180080e04ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2523"             ,	   0x1180080e04ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2524"             ,	   0x1180080e04ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2525"             ,	   0x1180080e04ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2526"             ,	   0x1180080e04ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2527"             ,	   0x1180080e04ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2528"             ,	   0x1180080e04f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2529"             ,	   0x1180080e04f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2530"             ,	   0x1180080e04f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2531"             ,	   0x1180080e04f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2532"             ,	   0x1180080e04f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2533"             ,	   0x1180080e04f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2534"             ,	   0x1180080e04f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2535"             ,	   0x1180080e04f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2536"             ,	   0x1180080e04f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2537"             ,	   0x1180080e04f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2538"             ,	   0x1180080e04f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2539"             ,	   0x1180080e04f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2540"             ,	   0x1180080e04f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2541"             ,	   0x1180080e04f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2542"             ,	   0x1180080e04f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2543"             ,	   0x1180080e04f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2544"             ,	   0x1180080e04f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2545"             ,	   0x1180080e04f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2546"             ,	   0x1180080e04f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2547"             ,	   0x1180080e04f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2548"             ,	   0x1180080e04fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2549"             ,	   0x1180080e04fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2550"             ,	   0x1180080e04fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2551"             ,	   0x1180080e04fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2552"             ,	   0x1180080e04fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2553"             ,	   0x1180080e04fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2554"             ,	   0x1180080e04fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2555"             ,	   0x1180080e04fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2556"             ,	   0x1180080e04fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2557"             ,	   0x1180080e04fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2558"             ,	   0x1180080e04ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2559"             ,	   0x1180080e04ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2560"             ,	   0x1180080e05000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2561"             ,	   0x1180080e05008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2562"             ,	   0x1180080e05010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2563"             ,	   0x1180080e05018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2564"             ,	   0x1180080e05020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2565"             ,	   0x1180080e05028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2566"             ,	   0x1180080e05030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2567"             ,	   0x1180080e05038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2568"             ,	   0x1180080e05040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2569"             ,	   0x1180080e05048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2570"             ,	   0x1180080e05050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2571"             ,	   0x1180080e05058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2572"             ,	   0x1180080e05060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2573"             ,	   0x1180080e05068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2574"             ,	   0x1180080e05070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2575"             ,	   0x1180080e05078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2576"             ,	   0x1180080e05080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2577"             ,	   0x1180080e05088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2578"             ,	   0x1180080e05090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2579"             ,	   0x1180080e05098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2580"             ,	   0x1180080e050a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2581"             ,	   0x1180080e050a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2582"             ,	   0x1180080e050b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2583"             ,	   0x1180080e050b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2584"             ,	   0x1180080e050c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2585"             ,	   0x1180080e050c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2586"             ,	   0x1180080e050d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2587"             ,	   0x1180080e050d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2588"             ,	   0x1180080e050e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2589"             ,	   0x1180080e050e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2590"             ,	   0x1180080e050f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2591"             ,	   0x1180080e050f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2592"             ,	   0x1180080e05100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2593"             ,	   0x1180080e05108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2594"             ,	   0x1180080e05110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2595"             ,	   0x1180080e05118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2596"             ,	   0x1180080e05120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2597"             ,	   0x1180080e05128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2598"             ,	   0x1180080e05130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2599"             ,	   0x1180080e05138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2600"             ,	   0x1180080e05140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2601"             ,	   0x1180080e05148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2602"             ,	   0x1180080e05150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2603"             ,	   0x1180080e05158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2604"             ,	   0x1180080e05160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2605"             ,	   0x1180080e05168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2606"             ,	   0x1180080e05170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2607"             ,	   0x1180080e05178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2608"             ,	   0x1180080e05180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2609"             ,	   0x1180080e05188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2610"             ,	   0x1180080e05190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2611"             ,	   0x1180080e05198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2612"             ,	   0x1180080e051a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2613"             ,	   0x1180080e051a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2614"             ,	   0x1180080e051b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2615"             ,	   0x1180080e051b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2616"             ,	   0x1180080e051c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2617"             ,	   0x1180080e051c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2618"             ,	   0x1180080e051d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2619"             ,	   0x1180080e051d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2620"             ,	   0x1180080e051e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2621"             ,	   0x1180080e051e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2622"             ,	   0x1180080e051f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2623"             ,	   0x1180080e051f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2624"             ,	   0x1180080e05200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2625"             ,	   0x1180080e05208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2626"             ,	   0x1180080e05210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2627"             ,	   0x1180080e05218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2628"             ,	   0x1180080e05220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2629"             ,	   0x1180080e05228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2630"             ,	   0x1180080e05230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2631"             ,	   0x1180080e05238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2632"             ,	   0x1180080e05240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2633"             ,	   0x1180080e05248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2634"             ,	   0x1180080e05250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2635"             ,	   0x1180080e05258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2636"             ,	   0x1180080e05260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2637"             ,	   0x1180080e05268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2638"             ,	   0x1180080e05270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2639"             ,	   0x1180080e05278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2640"             ,	   0x1180080e05280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2641"             ,	   0x1180080e05288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2642"             ,	   0x1180080e05290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2643"             ,	   0x1180080e05298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2644"             ,	   0x1180080e052a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2645"             ,	   0x1180080e052a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2646"             ,	   0x1180080e052b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2647"             ,	   0x1180080e052b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2648"             ,	   0x1180080e052c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2649"             ,	   0x1180080e052c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2650"             ,	   0x1180080e052d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2651"             ,	   0x1180080e052d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2652"             ,	   0x1180080e052e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2653"             ,	   0x1180080e052e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2654"             ,	   0x1180080e052f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2655"             ,	   0x1180080e052f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2656"             ,	   0x1180080e05300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2657"             ,	   0x1180080e05308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2658"             ,	   0x1180080e05310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2659"             ,	   0x1180080e05318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2660"             ,	   0x1180080e05320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2661"             ,	   0x1180080e05328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2662"             ,	   0x1180080e05330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2663"             ,	   0x1180080e05338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2664"             ,	   0x1180080e05340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2665"             ,	   0x1180080e05348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2666"             ,	   0x1180080e05350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2667"             ,	   0x1180080e05358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2668"             ,	   0x1180080e05360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2669"             ,	   0x1180080e05368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2670"             ,	   0x1180080e05370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2671"             ,	   0x1180080e05378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2672"             ,	   0x1180080e05380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2673"             ,	   0x1180080e05388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2674"             ,	   0x1180080e05390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2675"             ,	   0x1180080e05398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2676"             ,	   0x1180080e053a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2677"             ,	   0x1180080e053a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2678"             ,	   0x1180080e053b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2679"             ,	   0x1180080e053b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2680"             ,	   0x1180080e053c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2681"             ,	   0x1180080e053c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2682"             ,	   0x1180080e053d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2683"             ,	   0x1180080e053d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2684"             ,	   0x1180080e053e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2685"             ,	   0x1180080e053e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2686"             ,	   0x1180080e053f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2687"             ,	   0x1180080e053f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2688"             ,	   0x1180080e05400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2689"             ,	   0x1180080e05408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2690"             ,	   0x1180080e05410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2691"             ,	   0x1180080e05418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2692"             ,	   0x1180080e05420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2693"             ,	   0x1180080e05428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2694"             ,	   0x1180080e05430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2695"             ,	   0x1180080e05438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2696"             ,	   0x1180080e05440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2697"             ,	   0x1180080e05448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2698"             ,	   0x1180080e05450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2699"             ,	   0x1180080e05458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2700"             ,	   0x1180080e05460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2701"             ,	   0x1180080e05468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2702"             ,	   0x1180080e05470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2703"             ,	   0x1180080e05478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2704"             ,	   0x1180080e05480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2705"             ,	   0x1180080e05488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2706"             ,	   0x1180080e05490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2707"             ,	   0x1180080e05498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2708"             ,	   0x1180080e054a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2709"             ,	   0x1180080e054a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2710"             ,	   0x1180080e054b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2711"             ,	   0x1180080e054b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2712"             ,	   0x1180080e054c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2713"             ,	   0x1180080e054c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2714"             ,	   0x1180080e054d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2715"             ,	   0x1180080e054d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2716"             ,	   0x1180080e054e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2717"             ,	   0x1180080e054e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2718"             ,	   0x1180080e054f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2719"             ,	   0x1180080e054f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2720"             ,	   0x1180080e05500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2721"             ,	   0x1180080e05508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2722"             ,	   0x1180080e05510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2723"             ,	   0x1180080e05518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2724"             ,	   0x1180080e05520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2725"             ,	   0x1180080e05528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2726"             ,	   0x1180080e05530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2727"             ,	   0x1180080e05538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2728"             ,	   0x1180080e05540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2729"             ,	   0x1180080e05548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2730"             ,	   0x1180080e05550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2731"             ,	   0x1180080e05558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2732"             ,	   0x1180080e05560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2733"             ,	   0x1180080e05568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2734"             ,	   0x1180080e05570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2735"             ,	   0x1180080e05578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2736"             ,	   0x1180080e05580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2737"             ,	   0x1180080e05588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2738"             ,	   0x1180080e05590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2739"             ,	   0x1180080e05598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2740"             ,	   0x1180080e055a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2741"             ,	   0x1180080e055a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2742"             ,	   0x1180080e055b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2743"             ,	   0x1180080e055b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2744"             ,	   0x1180080e055c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2745"             ,	   0x1180080e055c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2746"             ,	   0x1180080e055d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2747"             ,	   0x1180080e055d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2748"             ,	   0x1180080e055e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2749"             ,	   0x1180080e055e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2750"             ,	   0x1180080e055f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2751"             ,	   0x1180080e055f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2752"             ,	   0x1180080e05600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2753"             ,	   0x1180080e05608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2754"             ,	   0x1180080e05610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2755"             ,	   0x1180080e05618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2756"             ,	   0x1180080e05620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2757"             ,	   0x1180080e05628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2758"             ,	   0x1180080e05630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2759"             ,	   0x1180080e05638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2760"             ,	   0x1180080e05640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2761"             ,	   0x1180080e05648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2762"             ,	   0x1180080e05650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2763"             ,	   0x1180080e05658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2764"             ,	   0x1180080e05660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2765"             ,	   0x1180080e05668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2766"             ,	   0x1180080e05670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2767"             ,	   0x1180080e05678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2768"             ,	   0x1180080e05680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2769"             ,	   0x1180080e05688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2770"             ,	   0x1180080e05690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2771"             ,	   0x1180080e05698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2772"             ,	   0x1180080e056a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2773"             ,	   0x1180080e056a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2774"             ,	   0x1180080e056b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2775"             ,	   0x1180080e056b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2776"             ,	   0x1180080e056c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2777"             ,	   0x1180080e056c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2778"             ,	   0x1180080e056d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2779"             ,	   0x1180080e056d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2780"             ,	   0x1180080e056e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2781"             ,	   0x1180080e056e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2782"             ,	   0x1180080e056f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2783"             ,	   0x1180080e056f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2784"             ,	   0x1180080e05700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2785"             ,	   0x1180080e05708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2786"             ,	   0x1180080e05710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2787"             ,	   0x1180080e05718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2788"             ,	   0x1180080e05720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2789"             ,	   0x1180080e05728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2790"             ,	   0x1180080e05730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2791"             ,	   0x1180080e05738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2792"             ,	   0x1180080e05740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2793"             ,	   0x1180080e05748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2794"             ,	   0x1180080e05750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2795"             ,	   0x1180080e05758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2796"             ,	   0x1180080e05760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2797"             ,	   0x1180080e05768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2798"             ,	   0x1180080e05770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2799"             ,	   0x1180080e05778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2800"             ,	   0x1180080e05780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2801"             ,	   0x1180080e05788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2802"             ,	   0x1180080e05790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2803"             ,	   0x1180080e05798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2804"             ,	   0x1180080e057a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2805"             ,	   0x1180080e057a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2806"             ,	   0x1180080e057b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2807"             ,	   0x1180080e057b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2808"             ,	   0x1180080e057c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2809"             ,	   0x1180080e057c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2810"             ,	   0x1180080e057d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2811"             ,	   0x1180080e057d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2812"             ,	   0x1180080e057e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2813"             ,	   0x1180080e057e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2814"             ,	   0x1180080e057f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2815"             ,	   0x1180080e057f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2816"             ,	   0x1180080e05800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2817"             ,	   0x1180080e05808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2818"             ,	   0x1180080e05810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2819"             ,	   0x1180080e05818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2820"             ,	   0x1180080e05820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2821"             ,	   0x1180080e05828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2822"             ,	   0x1180080e05830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2823"             ,	   0x1180080e05838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2824"             ,	   0x1180080e05840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2825"             ,	   0x1180080e05848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2826"             ,	   0x1180080e05850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2827"             ,	   0x1180080e05858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2828"             ,	   0x1180080e05860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2829"             ,	   0x1180080e05868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2830"             ,	   0x1180080e05870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2831"             ,	   0x1180080e05878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2832"             ,	   0x1180080e05880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2833"             ,	   0x1180080e05888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2834"             ,	   0x1180080e05890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2835"             ,	   0x1180080e05898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2836"             ,	   0x1180080e058a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2837"             ,	   0x1180080e058a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2838"             ,	   0x1180080e058b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2839"             ,	   0x1180080e058b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2840"             ,	   0x1180080e058c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2841"             ,	   0x1180080e058c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2842"             ,	   0x1180080e058d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2843"             ,	   0x1180080e058d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2844"             ,	   0x1180080e058e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2845"             ,	   0x1180080e058e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2846"             ,	   0x1180080e058f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2847"             ,	   0x1180080e058f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2848"             ,	   0x1180080e05900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2849"             ,	   0x1180080e05908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2850"             ,	   0x1180080e05910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2851"             ,	   0x1180080e05918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2852"             ,	   0x1180080e05920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2853"             ,	   0x1180080e05928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2854"             ,	   0x1180080e05930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2855"             ,	   0x1180080e05938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2856"             ,	   0x1180080e05940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2857"             ,	   0x1180080e05948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2858"             ,	   0x1180080e05950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2859"             ,	   0x1180080e05958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2860"             ,	   0x1180080e05960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2861"             ,	   0x1180080e05968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2862"             ,	   0x1180080e05970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2863"             ,	   0x1180080e05978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2864"             ,	   0x1180080e05980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2865"             ,	   0x1180080e05988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2866"             ,	   0x1180080e05990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2867"             ,	   0x1180080e05998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2868"             ,	   0x1180080e059a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2869"             ,	   0x1180080e059a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2870"             ,	   0x1180080e059b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2871"             ,	   0x1180080e059b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2872"             ,	   0x1180080e059c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2873"             ,	   0x1180080e059c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2874"             ,	   0x1180080e059d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2875"             ,	   0x1180080e059d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2876"             ,	   0x1180080e059e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2877"             ,	   0x1180080e059e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2878"             ,	   0x1180080e059f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2879"             ,	   0x1180080e059f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2880"             ,	   0x1180080e05a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2881"             ,	   0x1180080e05a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2882"             ,	   0x1180080e05a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2883"             ,	   0x1180080e05a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2884"             ,	   0x1180080e05a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2885"             ,	   0x1180080e05a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2886"             ,	   0x1180080e05a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2887"             ,	   0x1180080e05a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2888"             ,	   0x1180080e05a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2889"             ,	   0x1180080e05a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2890"             ,	   0x1180080e05a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2891"             ,	   0x1180080e05a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2892"             ,	   0x1180080e05a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2893"             ,	   0x1180080e05a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2894"             ,	   0x1180080e05a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2895"             ,	   0x1180080e05a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2896"             ,	   0x1180080e05a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2897"             ,	   0x1180080e05a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2898"             ,	   0x1180080e05a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2899"             ,	   0x1180080e05a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2900"             ,	   0x1180080e05aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2901"             ,	   0x1180080e05aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2902"             ,	   0x1180080e05ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2903"             ,	   0x1180080e05ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2904"             ,	   0x1180080e05ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2905"             ,	   0x1180080e05ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2906"             ,	   0x1180080e05ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2907"             ,	   0x1180080e05ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2908"             ,	   0x1180080e05ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2909"             ,	   0x1180080e05ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2910"             ,	   0x1180080e05af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2911"             ,	   0x1180080e05af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2912"             ,	   0x1180080e05b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2913"             ,	   0x1180080e05b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2914"             ,	   0x1180080e05b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2915"             ,	   0x1180080e05b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2916"             ,	   0x1180080e05b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2917"             ,	   0x1180080e05b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2918"             ,	   0x1180080e05b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2919"             ,	   0x1180080e05b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2920"             ,	   0x1180080e05b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2921"             ,	   0x1180080e05b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2922"             ,	   0x1180080e05b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2923"             ,	   0x1180080e05b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2924"             ,	   0x1180080e05b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2925"             ,	   0x1180080e05b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2926"             ,	   0x1180080e05b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2927"             ,	   0x1180080e05b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2928"             ,	   0x1180080e05b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2929"             ,	   0x1180080e05b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2930"             ,	   0x1180080e05b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2931"             ,	   0x1180080e05b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2932"             ,	   0x1180080e05ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2933"             ,	   0x1180080e05ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2934"             ,	   0x1180080e05bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2935"             ,	   0x1180080e05bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2936"             ,	   0x1180080e05bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2937"             ,	   0x1180080e05bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2938"             ,	   0x1180080e05bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2939"             ,	   0x1180080e05bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2940"             ,	   0x1180080e05be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2941"             ,	   0x1180080e05be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2942"             ,	   0x1180080e05bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2943"             ,	   0x1180080e05bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2944"             ,	   0x1180080e05c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2945"             ,	   0x1180080e05c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2946"             ,	   0x1180080e05c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2947"             ,	   0x1180080e05c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2948"             ,	   0x1180080e05c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2949"             ,	   0x1180080e05c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2950"             ,	   0x1180080e05c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2951"             ,	   0x1180080e05c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2952"             ,	   0x1180080e05c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2953"             ,	   0x1180080e05c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2954"             ,	   0x1180080e05c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2955"             ,	   0x1180080e05c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2956"             ,	   0x1180080e05c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2957"             ,	   0x1180080e05c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2958"             ,	   0x1180080e05c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2959"             ,	   0x1180080e05c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2960"             ,	   0x1180080e05c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2961"             ,	   0x1180080e05c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2962"             ,	   0x1180080e05c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2963"             ,	   0x1180080e05c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2964"             ,	   0x1180080e05ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2965"             ,	   0x1180080e05ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2966"             ,	   0x1180080e05cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2967"             ,	   0x1180080e05cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2968"             ,	   0x1180080e05cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2969"             ,	   0x1180080e05cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2970"             ,	   0x1180080e05cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2971"             ,	   0x1180080e05cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2972"             ,	   0x1180080e05ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2973"             ,	   0x1180080e05ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2974"             ,	   0x1180080e05cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2975"             ,	   0x1180080e05cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2976"             ,	   0x1180080e05d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2977"             ,	   0x1180080e05d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2978"             ,	   0x1180080e05d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2979"             ,	   0x1180080e05d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2980"             ,	   0x1180080e05d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2981"             ,	   0x1180080e05d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2982"             ,	   0x1180080e05d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2983"             ,	   0x1180080e05d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2984"             ,	   0x1180080e05d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2985"             ,	   0x1180080e05d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2986"             ,	   0x1180080e05d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2987"             ,	   0x1180080e05d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2988"             ,	   0x1180080e05d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2989"             ,	   0x1180080e05d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2990"             ,	   0x1180080e05d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2991"             ,	   0x1180080e05d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2992"             ,	   0x1180080e05d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2993"             ,	   0x1180080e05d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2994"             ,	   0x1180080e05d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2995"             ,	   0x1180080e05d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2996"             ,	   0x1180080e05da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2997"             ,	   0x1180080e05da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2998"             ,	   0x1180080e05db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP2999"             ,	   0x1180080e05db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3000"             ,	   0x1180080e05dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3001"             ,	   0x1180080e05dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3002"             ,	   0x1180080e05dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3003"             ,	   0x1180080e05dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3004"             ,	   0x1180080e05de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3005"             ,	   0x1180080e05de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3006"             ,	   0x1180080e05df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3007"             ,	   0x1180080e05df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3008"             ,	   0x1180080e05e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3009"             ,	   0x1180080e05e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3010"             ,	   0x1180080e05e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3011"             ,	   0x1180080e05e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3012"             ,	   0x1180080e05e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3013"             ,	   0x1180080e05e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3014"             ,	   0x1180080e05e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3015"             ,	   0x1180080e05e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3016"             ,	   0x1180080e05e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3017"             ,	   0x1180080e05e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3018"             ,	   0x1180080e05e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3019"             ,	   0x1180080e05e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3020"             ,	   0x1180080e05e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3021"             ,	   0x1180080e05e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3022"             ,	   0x1180080e05e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3023"             ,	   0x1180080e05e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3024"             ,	   0x1180080e05e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3025"             ,	   0x1180080e05e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3026"             ,	   0x1180080e05e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3027"             ,	   0x1180080e05e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3028"             ,	   0x1180080e05ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3029"             ,	   0x1180080e05ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3030"             ,	   0x1180080e05eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3031"             ,	   0x1180080e05eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3032"             ,	   0x1180080e05ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3033"             ,	   0x1180080e05ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3034"             ,	   0x1180080e05ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3035"             ,	   0x1180080e05ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3036"             ,	   0x1180080e05ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3037"             ,	   0x1180080e05ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3038"             ,	   0x1180080e05ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3039"             ,	   0x1180080e05ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3040"             ,	   0x1180080e05f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3041"             ,	   0x1180080e05f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3042"             ,	   0x1180080e05f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3043"             ,	   0x1180080e05f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3044"             ,	   0x1180080e05f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3045"             ,	   0x1180080e05f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3046"             ,	   0x1180080e05f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3047"             ,	   0x1180080e05f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3048"             ,	   0x1180080e05f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3049"             ,	   0x1180080e05f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3050"             ,	   0x1180080e05f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3051"             ,	   0x1180080e05f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3052"             ,	   0x1180080e05f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3053"             ,	   0x1180080e05f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3054"             ,	   0x1180080e05f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3055"             ,	   0x1180080e05f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3056"             ,	   0x1180080e05f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3057"             ,	   0x1180080e05f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3058"             ,	   0x1180080e05f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3059"             ,	   0x1180080e05f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3060"             ,	   0x1180080e05fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3061"             ,	   0x1180080e05fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3062"             ,	   0x1180080e05fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3063"             ,	   0x1180080e05fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3064"             ,	   0x1180080e05fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3065"             ,	   0x1180080e05fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3066"             ,	   0x1180080e05fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3067"             ,	   0x1180080e05fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3068"             ,	   0x1180080e05fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3069"             ,	   0x1180080e05fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3070"             ,	   0x1180080e05ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3071"             ,	   0x1180080e05ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3072"             ,	   0x1180080e06000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3073"             ,	   0x1180080e06008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3074"             ,	   0x1180080e06010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3075"             ,	   0x1180080e06018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3076"             ,	   0x1180080e06020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3077"             ,	   0x1180080e06028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3078"             ,	   0x1180080e06030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3079"             ,	   0x1180080e06038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3080"             ,	   0x1180080e06040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3081"             ,	   0x1180080e06048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3082"             ,	   0x1180080e06050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3083"             ,	   0x1180080e06058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3084"             ,	   0x1180080e06060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3085"             ,	   0x1180080e06068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3086"             ,	   0x1180080e06070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3087"             ,	   0x1180080e06078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3088"             ,	   0x1180080e06080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3089"             ,	   0x1180080e06088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3090"             ,	   0x1180080e06090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3091"             ,	   0x1180080e06098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3092"             ,	   0x1180080e060a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3093"             ,	   0x1180080e060a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3094"             ,	   0x1180080e060b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3095"             ,	   0x1180080e060b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3096"             ,	   0x1180080e060c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3097"             ,	   0x1180080e060c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3098"             ,	   0x1180080e060d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3099"             ,	   0x1180080e060d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3100"             ,	   0x1180080e060e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3101"             ,	   0x1180080e060e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3102"             ,	   0x1180080e060f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3103"             ,	   0x1180080e060f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3104"             ,	   0x1180080e06100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3105"             ,	   0x1180080e06108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3106"             ,	   0x1180080e06110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3107"             ,	   0x1180080e06118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3108"             ,	   0x1180080e06120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3109"             ,	   0x1180080e06128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3110"             ,	   0x1180080e06130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3111"             ,	   0x1180080e06138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3112"             ,	   0x1180080e06140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3113"             ,	   0x1180080e06148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3114"             ,	   0x1180080e06150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3115"             ,	   0x1180080e06158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3116"             ,	   0x1180080e06160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3117"             ,	   0x1180080e06168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3118"             ,	   0x1180080e06170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3119"             ,	   0x1180080e06178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3120"             ,	   0x1180080e06180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3121"             ,	   0x1180080e06188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3122"             ,	   0x1180080e06190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3123"             ,	   0x1180080e06198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3124"             ,	   0x1180080e061a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3125"             ,	   0x1180080e061a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3126"             ,	   0x1180080e061b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3127"             ,	   0x1180080e061b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3128"             ,	   0x1180080e061c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3129"             ,	   0x1180080e061c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3130"             ,	   0x1180080e061d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3131"             ,	   0x1180080e061d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3132"             ,	   0x1180080e061e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3133"             ,	   0x1180080e061e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3134"             ,	   0x1180080e061f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3135"             ,	   0x1180080e061f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3136"             ,	   0x1180080e06200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3137"             ,	   0x1180080e06208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3138"             ,	   0x1180080e06210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3139"             ,	   0x1180080e06218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3140"             ,	   0x1180080e06220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3141"             ,	   0x1180080e06228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3142"             ,	   0x1180080e06230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3143"             ,	   0x1180080e06238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3144"             ,	   0x1180080e06240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3145"             ,	   0x1180080e06248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3146"             ,	   0x1180080e06250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3147"             ,	   0x1180080e06258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3148"             ,	   0x1180080e06260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3149"             ,	   0x1180080e06268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3150"             ,	   0x1180080e06270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3151"             ,	   0x1180080e06278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3152"             ,	   0x1180080e06280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3153"             ,	   0x1180080e06288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3154"             ,	   0x1180080e06290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3155"             ,	   0x1180080e06298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3156"             ,	   0x1180080e062a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3157"             ,	   0x1180080e062a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3158"             ,	   0x1180080e062b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3159"             ,	   0x1180080e062b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3160"             ,	   0x1180080e062c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3161"             ,	   0x1180080e062c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3162"             ,	   0x1180080e062d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3163"             ,	   0x1180080e062d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3164"             ,	   0x1180080e062e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3165"             ,	   0x1180080e062e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3166"             ,	   0x1180080e062f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3167"             ,	   0x1180080e062f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3168"             ,	   0x1180080e06300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3169"             ,	   0x1180080e06308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3170"             ,	   0x1180080e06310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3171"             ,	   0x1180080e06318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3172"             ,	   0x1180080e06320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3173"             ,	   0x1180080e06328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3174"             ,	   0x1180080e06330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3175"             ,	   0x1180080e06338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3176"             ,	   0x1180080e06340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3177"             ,	   0x1180080e06348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3178"             ,	   0x1180080e06350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3179"             ,	   0x1180080e06358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3180"             ,	   0x1180080e06360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3181"             ,	   0x1180080e06368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3182"             ,	   0x1180080e06370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3183"             ,	   0x1180080e06378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3184"             ,	   0x1180080e06380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3185"             ,	   0x1180080e06388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3186"             ,	   0x1180080e06390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3187"             ,	   0x1180080e06398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3188"             ,	   0x1180080e063a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3189"             ,	   0x1180080e063a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3190"             ,	   0x1180080e063b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3191"             ,	   0x1180080e063b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3192"             ,	   0x1180080e063c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3193"             ,	   0x1180080e063c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3194"             ,	   0x1180080e063d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3195"             ,	   0x1180080e063d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3196"             ,	   0x1180080e063e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3197"             ,	   0x1180080e063e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3198"             ,	   0x1180080e063f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3199"             ,	   0x1180080e063f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3200"             ,	   0x1180080e06400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3201"             ,	   0x1180080e06408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3202"             ,	   0x1180080e06410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3203"             ,	   0x1180080e06418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3204"             ,	   0x1180080e06420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3205"             ,	   0x1180080e06428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3206"             ,	   0x1180080e06430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3207"             ,	   0x1180080e06438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3208"             ,	   0x1180080e06440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3209"             ,	   0x1180080e06448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3210"             ,	   0x1180080e06450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3211"             ,	   0x1180080e06458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3212"             ,	   0x1180080e06460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3213"             ,	   0x1180080e06468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3214"             ,	   0x1180080e06470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3215"             ,	   0x1180080e06478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3216"             ,	   0x1180080e06480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3217"             ,	   0x1180080e06488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3218"             ,	   0x1180080e06490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3219"             ,	   0x1180080e06498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3220"             ,	   0x1180080e064a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3221"             ,	   0x1180080e064a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3222"             ,	   0x1180080e064b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3223"             ,	   0x1180080e064b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3224"             ,	   0x1180080e064c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3225"             ,	   0x1180080e064c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3226"             ,	   0x1180080e064d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3227"             ,	   0x1180080e064d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3228"             ,	   0x1180080e064e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3229"             ,	   0x1180080e064e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3230"             ,	   0x1180080e064f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3231"             ,	   0x1180080e064f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3232"             ,	   0x1180080e06500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3233"             ,	   0x1180080e06508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3234"             ,	   0x1180080e06510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3235"             ,	   0x1180080e06518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3236"             ,	   0x1180080e06520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3237"             ,	   0x1180080e06528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3238"             ,	   0x1180080e06530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3239"             ,	   0x1180080e06538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3240"             ,	   0x1180080e06540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3241"             ,	   0x1180080e06548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3242"             ,	   0x1180080e06550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3243"             ,	   0x1180080e06558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3244"             ,	   0x1180080e06560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3245"             ,	   0x1180080e06568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3246"             ,	   0x1180080e06570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3247"             ,	   0x1180080e06578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3248"             ,	   0x1180080e06580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3249"             ,	   0x1180080e06588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3250"             ,	   0x1180080e06590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3251"             ,	   0x1180080e06598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3252"             ,	   0x1180080e065a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3253"             ,	   0x1180080e065a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3254"             ,	   0x1180080e065b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3255"             ,	   0x1180080e065b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3256"             ,	   0x1180080e065c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3257"             ,	   0x1180080e065c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3258"             ,	   0x1180080e065d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3259"             ,	   0x1180080e065d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3260"             ,	   0x1180080e065e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3261"             ,	   0x1180080e065e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3262"             ,	   0x1180080e065f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3263"             ,	   0x1180080e065f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3264"             ,	   0x1180080e06600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3265"             ,	   0x1180080e06608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3266"             ,	   0x1180080e06610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3267"             ,	   0x1180080e06618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3268"             ,	   0x1180080e06620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3269"             ,	   0x1180080e06628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3270"             ,	   0x1180080e06630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3271"             ,	   0x1180080e06638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3272"             ,	   0x1180080e06640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3273"             ,	   0x1180080e06648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3274"             ,	   0x1180080e06650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3275"             ,	   0x1180080e06658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3276"             ,	   0x1180080e06660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3277"             ,	   0x1180080e06668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3278"             ,	   0x1180080e06670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3279"             ,	   0x1180080e06678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3280"             ,	   0x1180080e06680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3281"             ,	   0x1180080e06688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3282"             ,	   0x1180080e06690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3283"             ,	   0x1180080e06698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3284"             ,	   0x1180080e066a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3285"             ,	   0x1180080e066a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3286"             ,	   0x1180080e066b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3287"             ,	   0x1180080e066b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3288"             ,	   0x1180080e066c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3289"             ,	   0x1180080e066c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3290"             ,	   0x1180080e066d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3291"             ,	   0x1180080e066d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3292"             ,	   0x1180080e066e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3293"             ,	   0x1180080e066e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3294"             ,	   0x1180080e066f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3295"             ,	   0x1180080e066f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3296"             ,	   0x1180080e06700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3297"             ,	   0x1180080e06708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3298"             ,	   0x1180080e06710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3299"             ,	   0x1180080e06718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3300"             ,	   0x1180080e06720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3301"             ,	   0x1180080e06728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3302"             ,	   0x1180080e06730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3303"             ,	   0x1180080e06738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3304"             ,	   0x1180080e06740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3305"             ,	   0x1180080e06748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3306"             ,	   0x1180080e06750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3307"             ,	   0x1180080e06758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3308"             ,	   0x1180080e06760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3309"             ,	   0x1180080e06768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3310"             ,	   0x1180080e06770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3311"             ,	   0x1180080e06778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3312"             ,	   0x1180080e06780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3313"             ,	   0x1180080e06788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3314"             ,	   0x1180080e06790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3315"             ,	   0x1180080e06798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3316"             ,	   0x1180080e067a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3317"             ,	   0x1180080e067a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3318"             ,	   0x1180080e067b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3319"             ,	   0x1180080e067b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3320"             ,	   0x1180080e067c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3321"             ,	   0x1180080e067c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3322"             ,	   0x1180080e067d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3323"             ,	   0x1180080e067d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3324"             ,	   0x1180080e067e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3325"             ,	   0x1180080e067e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3326"             ,	   0x1180080e067f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3327"             ,	   0x1180080e067f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3328"             ,	   0x1180080e06800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3329"             ,	   0x1180080e06808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3330"             ,	   0x1180080e06810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3331"             ,	   0x1180080e06818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3332"             ,	   0x1180080e06820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3333"             ,	   0x1180080e06828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3334"             ,	   0x1180080e06830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3335"             ,	   0x1180080e06838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3336"             ,	   0x1180080e06840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3337"             ,	   0x1180080e06848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3338"             ,	   0x1180080e06850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3339"             ,	   0x1180080e06858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3340"             ,	   0x1180080e06860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3341"             ,	   0x1180080e06868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3342"             ,	   0x1180080e06870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3343"             ,	   0x1180080e06878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3344"             ,	   0x1180080e06880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3345"             ,	   0x1180080e06888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3346"             ,	   0x1180080e06890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3347"             ,	   0x1180080e06898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3348"             ,	   0x1180080e068a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3349"             ,	   0x1180080e068a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3350"             ,	   0x1180080e068b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3351"             ,	   0x1180080e068b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3352"             ,	   0x1180080e068c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3353"             ,	   0x1180080e068c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3354"             ,	   0x1180080e068d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3355"             ,	   0x1180080e068d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3356"             ,	   0x1180080e068e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3357"             ,	   0x1180080e068e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3358"             ,	   0x1180080e068f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3359"             ,	   0x1180080e068f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3360"             ,	   0x1180080e06900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3361"             ,	   0x1180080e06908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3362"             ,	   0x1180080e06910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3363"             ,	   0x1180080e06918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3364"             ,	   0x1180080e06920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3365"             ,	   0x1180080e06928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3366"             ,	   0x1180080e06930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3367"             ,	   0x1180080e06938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3368"             ,	   0x1180080e06940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3369"             ,	   0x1180080e06948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3370"             ,	   0x1180080e06950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3371"             ,	   0x1180080e06958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3372"             ,	   0x1180080e06960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3373"             ,	   0x1180080e06968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3374"             ,	   0x1180080e06970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3375"             ,	   0x1180080e06978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3376"             ,	   0x1180080e06980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3377"             ,	   0x1180080e06988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3378"             ,	   0x1180080e06990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3379"             ,	   0x1180080e06998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3380"             ,	   0x1180080e069a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3381"             ,	   0x1180080e069a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3382"             ,	   0x1180080e069b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3383"             ,	   0x1180080e069b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3384"             ,	   0x1180080e069c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3385"             ,	   0x1180080e069c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3386"             ,	   0x1180080e069d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3387"             ,	   0x1180080e069d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3388"             ,	   0x1180080e069e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3389"             ,	   0x1180080e069e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3390"             ,	   0x1180080e069f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3391"             ,	   0x1180080e069f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3392"             ,	   0x1180080e06a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3393"             ,	   0x1180080e06a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3394"             ,	   0x1180080e06a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3395"             ,	   0x1180080e06a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3396"             ,	   0x1180080e06a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3397"             ,	   0x1180080e06a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3398"             ,	   0x1180080e06a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3399"             ,	   0x1180080e06a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3400"             ,	   0x1180080e06a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3401"             ,	   0x1180080e06a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3402"             ,	   0x1180080e06a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3403"             ,	   0x1180080e06a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3404"             ,	   0x1180080e06a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3405"             ,	   0x1180080e06a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3406"             ,	   0x1180080e06a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3407"             ,	   0x1180080e06a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3408"             ,	   0x1180080e06a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3409"             ,	   0x1180080e06a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3410"             ,	   0x1180080e06a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3411"             ,	   0x1180080e06a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3412"             ,	   0x1180080e06aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3413"             ,	   0x1180080e06aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3414"             ,	   0x1180080e06ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3415"             ,	   0x1180080e06ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3416"             ,	   0x1180080e06ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3417"             ,	   0x1180080e06ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3418"             ,	   0x1180080e06ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3419"             ,	   0x1180080e06ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3420"             ,	   0x1180080e06ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3421"             ,	   0x1180080e06ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3422"             ,	   0x1180080e06af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3423"             ,	   0x1180080e06af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3424"             ,	   0x1180080e06b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3425"             ,	   0x1180080e06b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3426"             ,	   0x1180080e06b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3427"             ,	   0x1180080e06b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3428"             ,	   0x1180080e06b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3429"             ,	   0x1180080e06b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3430"             ,	   0x1180080e06b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3431"             ,	   0x1180080e06b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3432"             ,	   0x1180080e06b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3433"             ,	   0x1180080e06b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3434"             ,	   0x1180080e06b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3435"             ,	   0x1180080e06b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3436"             ,	   0x1180080e06b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3437"             ,	   0x1180080e06b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3438"             ,	   0x1180080e06b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3439"             ,	   0x1180080e06b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3440"             ,	   0x1180080e06b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3441"             ,	   0x1180080e06b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3442"             ,	   0x1180080e06b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3443"             ,	   0x1180080e06b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3444"             ,	   0x1180080e06ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3445"             ,	   0x1180080e06ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3446"             ,	   0x1180080e06bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3447"             ,	   0x1180080e06bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3448"             ,	   0x1180080e06bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3449"             ,	   0x1180080e06bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3450"             ,	   0x1180080e06bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3451"             ,	   0x1180080e06bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3452"             ,	   0x1180080e06be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3453"             ,	   0x1180080e06be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3454"             ,	   0x1180080e06bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3455"             ,	   0x1180080e06bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3456"             ,	   0x1180080e06c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3457"             ,	   0x1180080e06c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3458"             ,	   0x1180080e06c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3459"             ,	   0x1180080e06c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3460"             ,	   0x1180080e06c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3461"             ,	   0x1180080e06c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3462"             ,	   0x1180080e06c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3463"             ,	   0x1180080e06c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3464"             ,	   0x1180080e06c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3465"             ,	   0x1180080e06c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3466"             ,	   0x1180080e06c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3467"             ,	   0x1180080e06c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3468"             ,	   0x1180080e06c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3469"             ,	   0x1180080e06c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3470"             ,	   0x1180080e06c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3471"             ,	   0x1180080e06c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3472"             ,	   0x1180080e06c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3473"             ,	   0x1180080e06c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3474"             ,	   0x1180080e06c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3475"             ,	   0x1180080e06c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3476"             ,	   0x1180080e06ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3477"             ,	   0x1180080e06ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3478"             ,	   0x1180080e06cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3479"             ,	   0x1180080e06cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3480"             ,	   0x1180080e06cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3481"             ,	   0x1180080e06cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3482"             ,	   0x1180080e06cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3483"             ,	   0x1180080e06cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3484"             ,	   0x1180080e06ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3485"             ,	   0x1180080e06ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3486"             ,	   0x1180080e06cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3487"             ,	   0x1180080e06cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3488"             ,	   0x1180080e06d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3489"             ,	   0x1180080e06d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3490"             ,	   0x1180080e06d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3491"             ,	   0x1180080e06d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3492"             ,	   0x1180080e06d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3493"             ,	   0x1180080e06d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3494"             ,	   0x1180080e06d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3495"             ,	   0x1180080e06d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3496"             ,	   0x1180080e06d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3497"             ,	   0x1180080e06d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3498"             ,	   0x1180080e06d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3499"             ,	   0x1180080e06d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3500"             ,	   0x1180080e06d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3501"             ,	   0x1180080e06d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3502"             ,	   0x1180080e06d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3503"             ,	   0x1180080e06d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3504"             ,	   0x1180080e06d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3505"             ,	   0x1180080e06d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3506"             ,	   0x1180080e06d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3507"             ,	   0x1180080e06d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3508"             ,	   0x1180080e06da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3509"             ,	   0x1180080e06da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3510"             ,	   0x1180080e06db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3511"             ,	   0x1180080e06db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3512"             ,	   0x1180080e06dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3513"             ,	   0x1180080e06dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3514"             ,	   0x1180080e06dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3515"             ,	   0x1180080e06dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3516"             ,	   0x1180080e06de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3517"             ,	   0x1180080e06de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3518"             ,	   0x1180080e06df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3519"             ,	   0x1180080e06df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3520"             ,	   0x1180080e06e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3521"             ,	   0x1180080e06e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3522"             ,	   0x1180080e06e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3523"             ,	   0x1180080e06e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3524"             ,	   0x1180080e06e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3525"             ,	   0x1180080e06e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3526"             ,	   0x1180080e06e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3527"             ,	   0x1180080e06e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3528"             ,	   0x1180080e06e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3529"             ,	   0x1180080e06e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3530"             ,	   0x1180080e06e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3531"             ,	   0x1180080e06e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3532"             ,	   0x1180080e06e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3533"             ,	   0x1180080e06e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3534"             ,	   0x1180080e06e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3535"             ,	   0x1180080e06e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3536"             ,	   0x1180080e06e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3537"             ,	   0x1180080e06e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3538"             ,	   0x1180080e06e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3539"             ,	   0x1180080e06e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3540"             ,	   0x1180080e06ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3541"             ,	   0x1180080e06ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3542"             ,	   0x1180080e06eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3543"             ,	   0x1180080e06eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3544"             ,	   0x1180080e06ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3545"             ,	   0x1180080e06ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3546"             ,	   0x1180080e06ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3547"             ,	   0x1180080e06ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3548"             ,	   0x1180080e06ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3549"             ,	   0x1180080e06ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3550"             ,	   0x1180080e06ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3551"             ,	   0x1180080e06ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3552"             ,	   0x1180080e06f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3553"             ,	   0x1180080e06f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3554"             ,	   0x1180080e06f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3555"             ,	   0x1180080e06f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3556"             ,	   0x1180080e06f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3557"             ,	   0x1180080e06f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3558"             ,	   0x1180080e06f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3559"             ,	   0x1180080e06f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3560"             ,	   0x1180080e06f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3561"             ,	   0x1180080e06f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3562"             ,	   0x1180080e06f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3563"             ,	   0x1180080e06f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3564"             ,	   0x1180080e06f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3565"             ,	   0x1180080e06f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3566"             ,	   0x1180080e06f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3567"             ,	   0x1180080e06f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3568"             ,	   0x1180080e06f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3569"             ,	   0x1180080e06f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3570"             ,	   0x1180080e06f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3571"             ,	   0x1180080e06f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3572"             ,	   0x1180080e06fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3573"             ,	   0x1180080e06fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3574"             ,	   0x1180080e06fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3575"             ,	   0x1180080e06fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3576"             ,	   0x1180080e06fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3577"             ,	   0x1180080e06fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3578"             ,	   0x1180080e06fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3579"             ,	   0x1180080e06fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3580"             ,	   0x1180080e06fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3581"             ,	   0x1180080e06fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3582"             ,	   0x1180080e06ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3583"             ,	   0x1180080e06ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3584"             ,	   0x1180080e07000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3585"             ,	   0x1180080e07008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3586"             ,	   0x1180080e07010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3587"             ,	   0x1180080e07018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3588"             ,	   0x1180080e07020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3589"             ,	   0x1180080e07028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3590"             ,	   0x1180080e07030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3591"             ,	   0x1180080e07038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3592"             ,	   0x1180080e07040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3593"             ,	   0x1180080e07048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3594"             ,	   0x1180080e07050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3595"             ,	   0x1180080e07058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3596"             ,	   0x1180080e07060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3597"             ,	   0x1180080e07068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3598"             ,	   0x1180080e07070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3599"             ,	   0x1180080e07078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3600"             ,	   0x1180080e07080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3601"             ,	   0x1180080e07088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3602"             ,	   0x1180080e07090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3603"             ,	   0x1180080e07098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3604"             ,	   0x1180080e070a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3605"             ,	   0x1180080e070a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3606"             ,	   0x1180080e070b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3607"             ,	   0x1180080e070b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3608"             ,	   0x1180080e070c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3609"             ,	   0x1180080e070c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3610"             ,	   0x1180080e070d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3611"             ,	   0x1180080e070d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3612"             ,	   0x1180080e070e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3613"             ,	   0x1180080e070e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3614"             ,	   0x1180080e070f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3615"             ,	   0x1180080e070f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3616"             ,	   0x1180080e07100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3617"             ,	   0x1180080e07108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3618"             ,	   0x1180080e07110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3619"             ,	   0x1180080e07118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3620"             ,	   0x1180080e07120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3621"             ,	   0x1180080e07128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3622"             ,	   0x1180080e07130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3623"             ,	   0x1180080e07138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3624"             ,	   0x1180080e07140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3625"             ,	   0x1180080e07148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3626"             ,	   0x1180080e07150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3627"             ,	   0x1180080e07158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3628"             ,	   0x1180080e07160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3629"             ,	   0x1180080e07168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3630"             ,	   0x1180080e07170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3631"             ,	   0x1180080e07178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3632"             ,	   0x1180080e07180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3633"             ,	   0x1180080e07188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3634"             ,	   0x1180080e07190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3635"             ,	   0x1180080e07198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3636"             ,	   0x1180080e071a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3637"             ,	   0x1180080e071a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3638"             ,	   0x1180080e071b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3639"             ,	   0x1180080e071b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3640"             ,	   0x1180080e071c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3641"             ,	   0x1180080e071c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3642"             ,	   0x1180080e071d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3643"             ,	   0x1180080e071d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3644"             ,	   0x1180080e071e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3645"             ,	   0x1180080e071e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3646"             ,	   0x1180080e071f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3647"             ,	   0x1180080e071f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3648"             ,	   0x1180080e07200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3649"             ,	   0x1180080e07208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3650"             ,	   0x1180080e07210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3651"             ,	   0x1180080e07218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3652"             ,	   0x1180080e07220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3653"             ,	   0x1180080e07228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3654"             ,	   0x1180080e07230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3655"             ,	   0x1180080e07238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3656"             ,	   0x1180080e07240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3657"             ,	   0x1180080e07248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3658"             ,	   0x1180080e07250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3659"             ,	   0x1180080e07258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3660"             ,	   0x1180080e07260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3661"             ,	   0x1180080e07268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3662"             ,	   0x1180080e07270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3663"             ,	   0x1180080e07278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3664"             ,	   0x1180080e07280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3665"             ,	   0x1180080e07288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3666"             ,	   0x1180080e07290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3667"             ,	   0x1180080e07298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3668"             ,	   0x1180080e072a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3669"             ,	   0x1180080e072a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3670"             ,	   0x1180080e072b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3671"             ,	   0x1180080e072b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3672"             ,	   0x1180080e072c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3673"             ,	   0x1180080e072c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3674"             ,	   0x1180080e072d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3675"             ,	   0x1180080e072d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3676"             ,	   0x1180080e072e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3677"             ,	   0x1180080e072e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3678"             ,	   0x1180080e072f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3679"             ,	   0x1180080e072f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3680"             ,	   0x1180080e07300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3681"             ,	   0x1180080e07308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3682"             ,	   0x1180080e07310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3683"             ,	   0x1180080e07318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3684"             ,	   0x1180080e07320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3685"             ,	   0x1180080e07328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3686"             ,	   0x1180080e07330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3687"             ,	   0x1180080e07338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3688"             ,	   0x1180080e07340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3689"             ,	   0x1180080e07348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3690"             ,	   0x1180080e07350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3691"             ,	   0x1180080e07358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3692"             ,	   0x1180080e07360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3693"             ,	   0x1180080e07368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3694"             ,	   0x1180080e07370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3695"             ,	   0x1180080e07378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3696"             ,	   0x1180080e07380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3697"             ,	   0x1180080e07388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3698"             ,	   0x1180080e07390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3699"             ,	   0x1180080e07398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3700"             ,	   0x1180080e073a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3701"             ,	   0x1180080e073a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3702"             ,	   0x1180080e073b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3703"             ,	   0x1180080e073b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3704"             ,	   0x1180080e073c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3705"             ,	   0x1180080e073c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3706"             ,	   0x1180080e073d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3707"             ,	   0x1180080e073d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3708"             ,	   0x1180080e073e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3709"             ,	   0x1180080e073e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3710"             ,	   0x1180080e073f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3711"             ,	   0x1180080e073f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3712"             ,	   0x1180080e07400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3713"             ,	   0x1180080e07408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3714"             ,	   0x1180080e07410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3715"             ,	   0x1180080e07418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3716"             ,	   0x1180080e07420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3717"             ,	   0x1180080e07428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3718"             ,	   0x1180080e07430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3719"             ,	   0x1180080e07438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3720"             ,	   0x1180080e07440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3721"             ,	   0x1180080e07448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3722"             ,	   0x1180080e07450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3723"             ,	   0x1180080e07458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3724"             ,	   0x1180080e07460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3725"             ,	   0x1180080e07468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3726"             ,	   0x1180080e07470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3727"             ,	   0x1180080e07478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3728"             ,	   0x1180080e07480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3729"             ,	   0x1180080e07488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3730"             ,	   0x1180080e07490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3731"             ,	   0x1180080e07498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3732"             ,	   0x1180080e074a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3733"             ,	   0x1180080e074a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3734"             ,	   0x1180080e074b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3735"             ,	   0x1180080e074b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3736"             ,	   0x1180080e074c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3737"             ,	   0x1180080e074c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3738"             ,	   0x1180080e074d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3739"             ,	   0x1180080e074d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3740"             ,	   0x1180080e074e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3741"             ,	   0x1180080e074e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3742"             ,	   0x1180080e074f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3743"             ,	   0x1180080e074f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3744"             ,	   0x1180080e07500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3745"             ,	   0x1180080e07508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3746"             ,	   0x1180080e07510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3747"             ,	   0x1180080e07518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3748"             ,	   0x1180080e07520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3749"             ,	   0x1180080e07528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3750"             ,	   0x1180080e07530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3751"             ,	   0x1180080e07538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3752"             ,	   0x1180080e07540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3753"             ,	   0x1180080e07548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3754"             ,	   0x1180080e07550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3755"             ,	   0x1180080e07558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3756"             ,	   0x1180080e07560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3757"             ,	   0x1180080e07568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3758"             ,	   0x1180080e07570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3759"             ,	   0x1180080e07578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3760"             ,	   0x1180080e07580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3761"             ,	   0x1180080e07588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3762"             ,	   0x1180080e07590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3763"             ,	   0x1180080e07598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3764"             ,	   0x1180080e075a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3765"             ,	   0x1180080e075a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3766"             ,	   0x1180080e075b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3767"             ,	   0x1180080e075b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3768"             ,	   0x1180080e075c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3769"             ,	   0x1180080e075c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3770"             ,	   0x1180080e075d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3771"             ,	   0x1180080e075d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3772"             ,	   0x1180080e075e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3773"             ,	   0x1180080e075e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3774"             ,	   0x1180080e075f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3775"             ,	   0x1180080e075f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3776"             ,	   0x1180080e07600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3777"             ,	   0x1180080e07608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3778"             ,	   0x1180080e07610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3779"             ,	   0x1180080e07618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3780"             ,	   0x1180080e07620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3781"             ,	   0x1180080e07628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3782"             ,	   0x1180080e07630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3783"             ,	   0x1180080e07638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3784"             ,	   0x1180080e07640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3785"             ,	   0x1180080e07648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3786"             ,	   0x1180080e07650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3787"             ,	   0x1180080e07658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3788"             ,	   0x1180080e07660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3789"             ,	   0x1180080e07668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3790"             ,	   0x1180080e07670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3791"             ,	   0x1180080e07678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3792"             ,	   0x1180080e07680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3793"             ,	   0x1180080e07688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3794"             ,	   0x1180080e07690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3795"             ,	   0x1180080e07698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3796"             ,	   0x1180080e076a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3797"             ,	   0x1180080e076a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3798"             ,	   0x1180080e076b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3799"             ,	   0x1180080e076b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3800"             ,	   0x1180080e076c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3801"             ,	   0x1180080e076c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3802"             ,	   0x1180080e076d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3803"             ,	   0x1180080e076d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3804"             ,	   0x1180080e076e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3805"             ,	   0x1180080e076e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3806"             ,	   0x1180080e076f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3807"             ,	   0x1180080e076f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3808"             ,	   0x1180080e07700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3809"             ,	   0x1180080e07708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3810"             ,	   0x1180080e07710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3811"             ,	   0x1180080e07718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3812"             ,	   0x1180080e07720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3813"             ,	   0x1180080e07728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3814"             ,	   0x1180080e07730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3815"             ,	   0x1180080e07738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3816"             ,	   0x1180080e07740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3817"             ,	   0x1180080e07748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3818"             ,	   0x1180080e07750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3819"             ,	   0x1180080e07758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3820"             ,	   0x1180080e07760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3821"             ,	   0x1180080e07768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3822"             ,	   0x1180080e07770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3823"             ,	   0x1180080e07778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3824"             ,	   0x1180080e07780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3825"             ,	   0x1180080e07788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3826"             ,	   0x1180080e07790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3827"             ,	   0x1180080e07798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3828"             ,	   0x1180080e077a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3829"             ,	   0x1180080e077a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3830"             ,	   0x1180080e077b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3831"             ,	   0x1180080e077b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3832"             ,	   0x1180080e077c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3833"             ,	   0x1180080e077c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3834"             ,	   0x1180080e077d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3835"             ,	   0x1180080e077d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3836"             ,	   0x1180080e077e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3837"             ,	   0x1180080e077e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3838"             ,	   0x1180080e077f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3839"             ,	   0x1180080e077f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3840"             ,	   0x1180080e07800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3841"             ,	   0x1180080e07808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3842"             ,	   0x1180080e07810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3843"             ,	   0x1180080e07818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3844"             ,	   0x1180080e07820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3845"             ,	   0x1180080e07828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3846"             ,	   0x1180080e07830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3847"             ,	   0x1180080e07838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3848"             ,	   0x1180080e07840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3849"             ,	   0x1180080e07848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3850"             ,	   0x1180080e07850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3851"             ,	   0x1180080e07858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3852"             ,	   0x1180080e07860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3853"             ,	   0x1180080e07868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3854"             ,	   0x1180080e07870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3855"             ,	   0x1180080e07878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3856"             ,	   0x1180080e07880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3857"             ,	   0x1180080e07888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3858"             ,	   0x1180080e07890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3859"             ,	   0x1180080e07898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3860"             ,	   0x1180080e078a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3861"             ,	   0x1180080e078a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3862"             ,	   0x1180080e078b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3863"             ,	   0x1180080e078b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3864"             ,	   0x1180080e078c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3865"             ,	   0x1180080e078c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3866"             ,	   0x1180080e078d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3867"             ,	   0x1180080e078d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3868"             ,	   0x1180080e078e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3869"             ,	   0x1180080e078e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3870"             ,	   0x1180080e078f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3871"             ,	   0x1180080e078f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3872"             ,	   0x1180080e07900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3873"             ,	   0x1180080e07908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3874"             ,	   0x1180080e07910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3875"             ,	   0x1180080e07918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3876"             ,	   0x1180080e07920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3877"             ,	   0x1180080e07928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3878"             ,	   0x1180080e07930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3879"             ,	   0x1180080e07938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3880"             ,	   0x1180080e07940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3881"             ,	   0x1180080e07948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3882"             ,	   0x1180080e07950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3883"             ,	   0x1180080e07958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3884"             ,	   0x1180080e07960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3885"             ,	   0x1180080e07968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3886"             ,	   0x1180080e07970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3887"             ,	   0x1180080e07978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3888"             ,	   0x1180080e07980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3889"             ,	   0x1180080e07988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3890"             ,	   0x1180080e07990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3891"             ,	   0x1180080e07998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3892"             ,	   0x1180080e079a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3893"             ,	   0x1180080e079a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3894"             ,	   0x1180080e079b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3895"             ,	   0x1180080e079b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3896"             ,	   0x1180080e079c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3897"             ,	   0x1180080e079c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3898"             ,	   0x1180080e079d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3899"             ,	   0x1180080e079d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3900"             ,	   0x1180080e079e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3901"             ,	   0x1180080e079e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3902"             ,	   0x1180080e079f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3903"             ,	   0x1180080e079f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3904"             ,	   0x1180080e07a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3905"             ,	   0x1180080e07a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3906"             ,	   0x1180080e07a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3907"             ,	   0x1180080e07a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3908"             ,	   0x1180080e07a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3909"             ,	   0x1180080e07a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3910"             ,	   0x1180080e07a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3911"             ,	   0x1180080e07a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3912"             ,	   0x1180080e07a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3913"             ,	   0x1180080e07a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3914"             ,	   0x1180080e07a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3915"             ,	   0x1180080e07a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3916"             ,	   0x1180080e07a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3917"             ,	   0x1180080e07a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3918"             ,	   0x1180080e07a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3919"             ,	   0x1180080e07a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3920"             ,	   0x1180080e07a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3921"             ,	   0x1180080e07a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3922"             ,	   0x1180080e07a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3923"             ,	   0x1180080e07a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3924"             ,	   0x1180080e07aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3925"             ,	   0x1180080e07aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3926"             ,	   0x1180080e07ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3927"             ,	   0x1180080e07ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3928"             ,	   0x1180080e07ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3929"             ,	   0x1180080e07ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3930"             ,	   0x1180080e07ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3931"             ,	   0x1180080e07ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3932"             ,	   0x1180080e07ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3933"             ,	   0x1180080e07ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3934"             ,	   0x1180080e07af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3935"             ,	   0x1180080e07af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3936"             ,	   0x1180080e07b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3937"             ,	   0x1180080e07b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3938"             ,	   0x1180080e07b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3939"             ,	   0x1180080e07b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3940"             ,	   0x1180080e07b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3941"             ,	   0x1180080e07b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3942"             ,	   0x1180080e07b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3943"             ,	   0x1180080e07b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3944"             ,	   0x1180080e07b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3945"             ,	   0x1180080e07b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3946"             ,	   0x1180080e07b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3947"             ,	   0x1180080e07b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3948"             ,	   0x1180080e07b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3949"             ,	   0x1180080e07b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3950"             ,	   0x1180080e07b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3951"             ,	   0x1180080e07b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3952"             ,	   0x1180080e07b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3953"             ,	   0x1180080e07b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3954"             ,	   0x1180080e07b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3955"             ,	   0x1180080e07b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3956"             ,	   0x1180080e07ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3957"             ,	   0x1180080e07ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3958"             ,	   0x1180080e07bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3959"             ,	   0x1180080e07bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3960"             ,	   0x1180080e07bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3961"             ,	   0x1180080e07bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3962"             ,	   0x1180080e07bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3963"             ,	   0x1180080e07bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3964"             ,	   0x1180080e07be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3965"             ,	   0x1180080e07be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3966"             ,	   0x1180080e07bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3967"             ,	   0x1180080e07bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3968"             ,	   0x1180080e07c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3969"             ,	   0x1180080e07c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3970"             ,	   0x1180080e07c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3971"             ,	   0x1180080e07c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3972"             ,	   0x1180080e07c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3973"             ,	   0x1180080e07c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3974"             ,	   0x1180080e07c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3975"             ,	   0x1180080e07c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3976"             ,	   0x1180080e07c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3977"             ,	   0x1180080e07c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3978"             ,	   0x1180080e07c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3979"             ,	   0x1180080e07c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3980"             ,	   0x1180080e07c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3981"             ,	   0x1180080e07c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3982"             ,	   0x1180080e07c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3983"             ,	   0x1180080e07c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3984"             ,	   0x1180080e07c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3985"             ,	   0x1180080e07c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3986"             ,	   0x1180080e07c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3987"             ,	   0x1180080e07c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3988"             ,	   0x1180080e07ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3989"             ,	   0x1180080e07ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3990"             ,	   0x1180080e07cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3991"             ,	   0x1180080e07cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3992"             ,	   0x1180080e07cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3993"             ,	   0x1180080e07cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3994"             ,	   0x1180080e07cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3995"             ,	   0x1180080e07cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3996"             ,	   0x1180080e07ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3997"             ,	   0x1180080e07ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3998"             ,	   0x1180080e07cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP3999"             ,	   0x1180080e07cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4000"             ,	   0x1180080e07d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4001"             ,	   0x1180080e07d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4002"             ,	   0x1180080e07d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4003"             ,	   0x1180080e07d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4004"             ,	   0x1180080e07d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4005"             ,	   0x1180080e07d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4006"             ,	   0x1180080e07d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4007"             ,	   0x1180080e07d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4008"             ,	   0x1180080e07d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4009"             ,	   0x1180080e07d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4010"             ,	   0x1180080e07d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4011"             ,	   0x1180080e07d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4012"             ,	   0x1180080e07d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4013"             ,	   0x1180080e07d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4014"             ,	   0x1180080e07d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4015"             ,	   0x1180080e07d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4016"             ,	   0x1180080e07d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4017"             ,	   0x1180080e07d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4018"             ,	   0x1180080e07d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4019"             ,	   0x1180080e07d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4020"             ,	   0x1180080e07da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4021"             ,	   0x1180080e07da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4022"             ,	   0x1180080e07db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4023"             ,	   0x1180080e07db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4024"             ,	   0x1180080e07dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4025"             ,	   0x1180080e07dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4026"             ,	   0x1180080e07dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4027"             ,	   0x1180080e07dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4028"             ,	   0x1180080e07de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4029"             ,	   0x1180080e07de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4030"             ,	   0x1180080e07df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4031"             ,	   0x1180080e07df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4032"             ,	   0x1180080e07e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4033"             ,	   0x1180080e07e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4034"             ,	   0x1180080e07e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4035"             ,	   0x1180080e07e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4036"             ,	   0x1180080e07e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4037"             ,	   0x1180080e07e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4038"             ,	   0x1180080e07e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4039"             ,	   0x1180080e07e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4040"             ,	   0x1180080e07e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4041"             ,	   0x1180080e07e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4042"             ,	   0x1180080e07e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4043"             ,	   0x1180080e07e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4044"             ,	   0x1180080e07e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4045"             ,	   0x1180080e07e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4046"             ,	   0x1180080e07e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4047"             ,	   0x1180080e07e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4048"             ,	   0x1180080e07e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4049"             ,	   0x1180080e07e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4050"             ,	   0x1180080e07e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4051"             ,	   0x1180080e07e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4052"             ,	   0x1180080e07ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4053"             ,	   0x1180080e07ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4054"             ,	   0x1180080e07eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4055"             ,	   0x1180080e07eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4056"             ,	   0x1180080e07ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4057"             ,	   0x1180080e07ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4058"             ,	   0x1180080e07ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4059"             ,	   0x1180080e07ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4060"             ,	   0x1180080e07ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4061"             ,	   0x1180080e07ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4062"             ,	   0x1180080e07ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4063"             ,	   0x1180080e07ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4064"             ,	   0x1180080e07f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4065"             ,	   0x1180080e07f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4066"             ,	   0x1180080e07f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4067"             ,	   0x1180080e07f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4068"             ,	   0x1180080e07f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4069"             ,	   0x1180080e07f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4070"             ,	   0x1180080e07f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4071"             ,	   0x1180080e07f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4072"             ,	   0x1180080e07f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4073"             ,	   0x1180080e07f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4074"             ,	   0x1180080e07f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4075"             ,	   0x1180080e07f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4076"             ,	   0x1180080e07f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4077"             ,	   0x1180080e07f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4078"             ,	   0x1180080e07f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4079"             ,	   0x1180080e07f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4080"             ,	   0x1180080e07f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4081"             ,	   0x1180080e07f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4082"             ,	   0x1180080e07f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4083"             ,	   0x1180080e07f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4084"             ,	   0x1180080e07fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4085"             ,	   0x1180080e07fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4086"             ,	   0x1180080e07fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4087"             ,	   0x1180080e07fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4088"             ,	   0x1180080e07fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4089"             ,	   0x1180080e07fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4090"             ,	   0x1180080e07fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4091"             ,	   0x1180080e07fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4092"             ,	   0x1180080e07fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4093"             ,	   0x1180080e07fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4094"             ,	   0x1180080e07ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4095"             ,	   0x1180080e07ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4096"             ,	   0x1180080e08000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4097"             ,	   0x1180080e08008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4098"             ,	   0x1180080e08010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4099"             ,	   0x1180080e08018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4100"             ,	   0x1180080e08020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4101"             ,	   0x1180080e08028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4102"             ,	   0x1180080e08030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4103"             ,	   0x1180080e08038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4104"             ,	   0x1180080e08040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4105"             ,	   0x1180080e08048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4106"             ,	   0x1180080e08050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4107"             ,	   0x1180080e08058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4108"             ,	   0x1180080e08060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4109"             ,	   0x1180080e08068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4110"             ,	   0x1180080e08070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4111"             ,	   0x1180080e08078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4112"             ,	   0x1180080e08080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4113"             ,	   0x1180080e08088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4114"             ,	   0x1180080e08090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4115"             ,	   0x1180080e08098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4116"             ,	   0x1180080e080a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4117"             ,	   0x1180080e080a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4118"             ,	   0x1180080e080b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4119"             ,	   0x1180080e080b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4120"             ,	   0x1180080e080c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4121"             ,	   0x1180080e080c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4122"             ,	   0x1180080e080d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4123"             ,	   0x1180080e080d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4124"             ,	   0x1180080e080e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4125"             ,	   0x1180080e080e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4126"             ,	   0x1180080e080f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4127"             ,	   0x1180080e080f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4128"             ,	   0x1180080e08100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4129"             ,	   0x1180080e08108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4130"             ,	   0x1180080e08110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4131"             ,	   0x1180080e08118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4132"             ,	   0x1180080e08120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4133"             ,	   0x1180080e08128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4134"             ,	   0x1180080e08130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4135"             ,	   0x1180080e08138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4136"             ,	   0x1180080e08140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4137"             ,	   0x1180080e08148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4138"             ,	   0x1180080e08150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4139"             ,	   0x1180080e08158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4140"             ,	   0x1180080e08160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4141"             ,	   0x1180080e08168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4142"             ,	   0x1180080e08170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4143"             ,	   0x1180080e08178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4144"             ,	   0x1180080e08180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4145"             ,	   0x1180080e08188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4146"             ,	   0x1180080e08190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4147"             ,	   0x1180080e08198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4148"             ,	   0x1180080e081a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4149"             ,	   0x1180080e081a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4150"             ,	   0x1180080e081b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4151"             ,	   0x1180080e081b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4152"             ,	   0x1180080e081c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4153"             ,	   0x1180080e081c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4154"             ,	   0x1180080e081d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4155"             ,	   0x1180080e081d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4156"             ,	   0x1180080e081e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4157"             ,	   0x1180080e081e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4158"             ,	   0x1180080e081f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4159"             ,	   0x1180080e081f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4160"             ,	   0x1180080e08200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4161"             ,	   0x1180080e08208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4162"             ,	   0x1180080e08210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4163"             ,	   0x1180080e08218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4164"             ,	   0x1180080e08220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4165"             ,	   0x1180080e08228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4166"             ,	   0x1180080e08230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4167"             ,	   0x1180080e08238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4168"             ,	   0x1180080e08240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4169"             ,	   0x1180080e08248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4170"             ,	   0x1180080e08250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4171"             ,	   0x1180080e08258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4172"             ,	   0x1180080e08260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4173"             ,	   0x1180080e08268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4174"             ,	   0x1180080e08270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4175"             ,	   0x1180080e08278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4176"             ,	   0x1180080e08280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4177"             ,	   0x1180080e08288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4178"             ,	   0x1180080e08290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4179"             ,	   0x1180080e08298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4180"             ,	   0x1180080e082a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4181"             ,	   0x1180080e082a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4182"             ,	   0x1180080e082b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4183"             ,	   0x1180080e082b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4184"             ,	   0x1180080e082c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4185"             ,	   0x1180080e082c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4186"             ,	   0x1180080e082d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4187"             ,	   0x1180080e082d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4188"             ,	   0x1180080e082e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4189"             ,	   0x1180080e082e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4190"             ,	   0x1180080e082f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4191"             ,	   0x1180080e082f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4192"             ,	   0x1180080e08300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4193"             ,	   0x1180080e08308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4194"             ,	   0x1180080e08310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4195"             ,	   0x1180080e08318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4196"             ,	   0x1180080e08320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4197"             ,	   0x1180080e08328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4198"             ,	   0x1180080e08330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4199"             ,	   0x1180080e08338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4200"             ,	   0x1180080e08340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4201"             ,	   0x1180080e08348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4202"             ,	   0x1180080e08350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4203"             ,	   0x1180080e08358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4204"             ,	   0x1180080e08360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4205"             ,	   0x1180080e08368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4206"             ,	   0x1180080e08370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4207"             ,	   0x1180080e08378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4208"             ,	   0x1180080e08380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4209"             ,	   0x1180080e08388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4210"             ,	   0x1180080e08390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4211"             ,	   0x1180080e08398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4212"             ,	   0x1180080e083a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4213"             ,	   0x1180080e083a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4214"             ,	   0x1180080e083b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4215"             ,	   0x1180080e083b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4216"             ,	   0x1180080e083c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4217"             ,	   0x1180080e083c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4218"             ,	   0x1180080e083d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4219"             ,	   0x1180080e083d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4220"             ,	   0x1180080e083e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4221"             ,	   0x1180080e083e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4222"             ,	   0x1180080e083f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4223"             ,	   0x1180080e083f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4224"             ,	   0x1180080e08400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4225"             ,	   0x1180080e08408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4226"             ,	   0x1180080e08410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4227"             ,	   0x1180080e08418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4228"             ,	   0x1180080e08420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4229"             ,	   0x1180080e08428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4230"             ,	   0x1180080e08430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4231"             ,	   0x1180080e08438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4232"             ,	   0x1180080e08440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4233"             ,	   0x1180080e08448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4234"             ,	   0x1180080e08450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4235"             ,	   0x1180080e08458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4236"             ,	   0x1180080e08460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4237"             ,	   0x1180080e08468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4238"             ,	   0x1180080e08470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4239"             ,	   0x1180080e08478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4240"             ,	   0x1180080e08480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4241"             ,	   0x1180080e08488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4242"             ,	   0x1180080e08490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4243"             ,	   0x1180080e08498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4244"             ,	   0x1180080e084a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4245"             ,	   0x1180080e084a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4246"             ,	   0x1180080e084b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4247"             ,	   0x1180080e084b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4248"             ,	   0x1180080e084c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4249"             ,	   0x1180080e084c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4250"             ,	   0x1180080e084d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4251"             ,	   0x1180080e084d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4252"             ,	   0x1180080e084e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4253"             ,	   0x1180080e084e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4254"             ,	   0x1180080e084f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4255"             ,	   0x1180080e084f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4256"             ,	   0x1180080e08500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4257"             ,	   0x1180080e08508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4258"             ,	   0x1180080e08510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4259"             ,	   0x1180080e08518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4260"             ,	   0x1180080e08520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4261"             ,	   0x1180080e08528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4262"             ,	   0x1180080e08530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4263"             ,	   0x1180080e08538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4264"             ,	   0x1180080e08540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4265"             ,	   0x1180080e08548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4266"             ,	   0x1180080e08550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4267"             ,	   0x1180080e08558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4268"             ,	   0x1180080e08560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4269"             ,	   0x1180080e08568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4270"             ,	   0x1180080e08570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4271"             ,	   0x1180080e08578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4272"             ,	   0x1180080e08580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4273"             ,	   0x1180080e08588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4274"             ,	   0x1180080e08590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4275"             ,	   0x1180080e08598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4276"             ,	   0x1180080e085a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4277"             ,	   0x1180080e085a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4278"             ,	   0x1180080e085b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4279"             ,	   0x1180080e085b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4280"             ,	   0x1180080e085c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4281"             ,	   0x1180080e085c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4282"             ,	   0x1180080e085d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4283"             ,	   0x1180080e085d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4284"             ,	   0x1180080e085e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4285"             ,	   0x1180080e085e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4286"             ,	   0x1180080e085f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4287"             ,	   0x1180080e085f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4288"             ,	   0x1180080e08600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4289"             ,	   0x1180080e08608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4290"             ,	   0x1180080e08610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4291"             ,	   0x1180080e08618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4292"             ,	   0x1180080e08620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4293"             ,	   0x1180080e08628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4294"             ,	   0x1180080e08630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4295"             ,	   0x1180080e08638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4296"             ,	   0x1180080e08640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4297"             ,	   0x1180080e08648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4298"             ,	   0x1180080e08650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4299"             ,	   0x1180080e08658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4300"             ,	   0x1180080e08660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4301"             ,	   0x1180080e08668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4302"             ,	   0x1180080e08670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4303"             ,	   0x1180080e08678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4304"             ,	   0x1180080e08680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4305"             ,	   0x1180080e08688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4306"             ,	   0x1180080e08690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4307"             ,	   0x1180080e08698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4308"             ,	   0x1180080e086a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4309"             ,	   0x1180080e086a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4310"             ,	   0x1180080e086b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4311"             ,	   0x1180080e086b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4312"             ,	   0x1180080e086c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4313"             ,	   0x1180080e086c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4314"             ,	   0x1180080e086d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4315"             ,	   0x1180080e086d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4316"             ,	   0x1180080e086e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4317"             ,	   0x1180080e086e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4318"             ,	   0x1180080e086f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4319"             ,	   0x1180080e086f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4320"             ,	   0x1180080e08700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4321"             ,	   0x1180080e08708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4322"             ,	   0x1180080e08710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4323"             ,	   0x1180080e08718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4324"             ,	   0x1180080e08720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4325"             ,	   0x1180080e08728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4326"             ,	   0x1180080e08730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4327"             ,	   0x1180080e08738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4328"             ,	   0x1180080e08740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4329"             ,	   0x1180080e08748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4330"             ,	   0x1180080e08750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4331"             ,	   0x1180080e08758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4332"             ,	   0x1180080e08760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4333"             ,	   0x1180080e08768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4334"             ,	   0x1180080e08770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4335"             ,	   0x1180080e08778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4336"             ,	   0x1180080e08780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4337"             ,	   0x1180080e08788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4338"             ,	   0x1180080e08790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4339"             ,	   0x1180080e08798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4340"             ,	   0x1180080e087a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4341"             ,	   0x1180080e087a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4342"             ,	   0x1180080e087b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4343"             ,	   0x1180080e087b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4344"             ,	   0x1180080e087c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4345"             ,	   0x1180080e087c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4346"             ,	   0x1180080e087d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4347"             ,	   0x1180080e087d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4348"             ,	   0x1180080e087e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4349"             ,	   0x1180080e087e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4350"             ,	   0x1180080e087f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4351"             ,	   0x1180080e087f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4352"             ,	   0x1180080e08800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4353"             ,	   0x1180080e08808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4354"             ,	   0x1180080e08810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4355"             ,	   0x1180080e08818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4356"             ,	   0x1180080e08820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4357"             ,	   0x1180080e08828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4358"             ,	   0x1180080e08830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4359"             ,	   0x1180080e08838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4360"             ,	   0x1180080e08840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4361"             ,	   0x1180080e08848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4362"             ,	   0x1180080e08850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4363"             ,	   0x1180080e08858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4364"             ,	   0x1180080e08860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4365"             ,	   0x1180080e08868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4366"             ,	   0x1180080e08870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4367"             ,	   0x1180080e08878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4368"             ,	   0x1180080e08880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4369"             ,	   0x1180080e08888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4370"             ,	   0x1180080e08890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4371"             ,	   0x1180080e08898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4372"             ,	   0x1180080e088a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4373"             ,	   0x1180080e088a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4374"             ,	   0x1180080e088b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4375"             ,	   0x1180080e088b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4376"             ,	   0x1180080e088c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4377"             ,	   0x1180080e088c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4378"             ,	   0x1180080e088d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4379"             ,	   0x1180080e088d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4380"             ,	   0x1180080e088e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4381"             ,	   0x1180080e088e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4382"             ,	   0x1180080e088f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4383"             ,	   0x1180080e088f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4384"             ,	   0x1180080e08900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4385"             ,	   0x1180080e08908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4386"             ,	   0x1180080e08910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4387"             ,	   0x1180080e08918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4388"             ,	   0x1180080e08920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4389"             ,	   0x1180080e08928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4390"             ,	   0x1180080e08930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4391"             ,	   0x1180080e08938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4392"             ,	   0x1180080e08940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4393"             ,	   0x1180080e08948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4394"             ,	   0x1180080e08950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4395"             ,	   0x1180080e08958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4396"             ,	   0x1180080e08960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4397"             ,	   0x1180080e08968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4398"             ,	   0x1180080e08970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4399"             ,	   0x1180080e08978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4400"             ,	   0x1180080e08980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4401"             ,	   0x1180080e08988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4402"             ,	   0x1180080e08990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4403"             ,	   0x1180080e08998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4404"             ,	   0x1180080e089a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4405"             ,	   0x1180080e089a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4406"             ,	   0x1180080e089b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4407"             ,	   0x1180080e089b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4408"             ,	   0x1180080e089c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4409"             ,	   0x1180080e089c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4410"             ,	   0x1180080e089d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4411"             ,	   0x1180080e089d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4412"             ,	   0x1180080e089e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4413"             ,	   0x1180080e089e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4414"             ,	   0x1180080e089f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4415"             ,	   0x1180080e089f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4416"             ,	   0x1180080e08a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4417"             ,	   0x1180080e08a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4418"             ,	   0x1180080e08a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4419"             ,	   0x1180080e08a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4420"             ,	   0x1180080e08a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4421"             ,	   0x1180080e08a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4422"             ,	   0x1180080e08a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4423"             ,	   0x1180080e08a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4424"             ,	   0x1180080e08a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4425"             ,	   0x1180080e08a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4426"             ,	   0x1180080e08a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4427"             ,	   0x1180080e08a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4428"             ,	   0x1180080e08a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4429"             ,	   0x1180080e08a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4430"             ,	   0x1180080e08a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4431"             ,	   0x1180080e08a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4432"             ,	   0x1180080e08a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4433"             ,	   0x1180080e08a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4434"             ,	   0x1180080e08a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4435"             ,	   0x1180080e08a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4436"             ,	   0x1180080e08aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4437"             ,	   0x1180080e08aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4438"             ,	   0x1180080e08ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4439"             ,	   0x1180080e08ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4440"             ,	   0x1180080e08ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4441"             ,	   0x1180080e08ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4442"             ,	   0x1180080e08ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4443"             ,	   0x1180080e08ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4444"             ,	   0x1180080e08ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4445"             ,	   0x1180080e08ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4446"             ,	   0x1180080e08af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4447"             ,	   0x1180080e08af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4448"             ,	   0x1180080e08b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4449"             ,	   0x1180080e08b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4450"             ,	   0x1180080e08b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4451"             ,	   0x1180080e08b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4452"             ,	   0x1180080e08b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4453"             ,	   0x1180080e08b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4454"             ,	   0x1180080e08b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4455"             ,	   0x1180080e08b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4456"             ,	   0x1180080e08b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4457"             ,	   0x1180080e08b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4458"             ,	   0x1180080e08b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4459"             ,	   0x1180080e08b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4460"             ,	   0x1180080e08b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4461"             ,	   0x1180080e08b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4462"             ,	   0x1180080e08b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4463"             ,	   0x1180080e08b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4464"             ,	   0x1180080e08b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4465"             ,	   0x1180080e08b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4466"             ,	   0x1180080e08b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4467"             ,	   0x1180080e08b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4468"             ,	   0x1180080e08ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4469"             ,	   0x1180080e08ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4470"             ,	   0x1180080e08bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4471"             ,	   0x1180080e08bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4472"             ,	   0x1180080e08bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4473"             ,	   0x1180080e08bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4474"             ,	   0x1180080e08bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4475"             ,	   0x1180080e08bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4476"             ,	   0x1180080e08be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4477"             ,	   0x1180080e08be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4478"             ,	   0x1180080e08bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4479"             ,	   0x1180080e08bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4480"             ,	   0x1180080e08c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4481"             ,	   0x1180080e08c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4482"             ,	   0x1180080e08c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4483"             ,	   0x1180080e08c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4484"             ,	   0x1180080e08c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4485"             ,	   0x1180080e08c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4486"             ,	   0x1180080e08c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4487"             ,	   0x1180080e08c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4488"             ,	   0x1180080e08c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4489"             ,	   0x1180080e08c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4490"             ,	   0x1180080e08c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4491"             ,	   0x1180080e08c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4492"             ,	   0x1180080e08c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4493"             ,	   0x1180080e08c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4494"             ,	   0x1180080e08c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4495"             ,	   0x1180080e08c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4496"             ,	   0x1180080e08c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4497"             ,	   0x1180080e08c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4498"             ,	   0x1180080e08c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4499"             ,	   0x1180080e08c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4500"             ,	   0x1180080e08ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4501"             ,	   0x1180080e08ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4502"             ,	   0x1180080e08cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4503"             ,	   0x1180080e08cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4504"             ,	   0x1180080e08cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4505"             ,	   0x1180080e08cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4506"             ,	   0x1180080e08cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4507"             ,	   0x1180080e08cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4508"             ,	   0x1180080e08ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4509"             ,	   0x1180080e08ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4510"             ,	   0x1180080e08cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4511"             ,	   0x1180080e08cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4512"             ,	   0x1180080e08d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4513"             ,	   0x1180080e08d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4514"             ,	   0x1180080e08d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4515"             ,	   0x1180080e08d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4516"             ,	   0x1180080e08d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4517"             ,	   0x1180080e08d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4518"             ,	   0x1180080e08d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4519"             ,	   0x1180080e08d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4520"             ,	   0x1180080e08d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4521"             ,	   0x1180080e08d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4522"             ,	   0x1180080e08d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4523"             ,	   0x1180080e08d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4524"             ,	   0x1180080e08d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4525"             ,	   0x1180080e08d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4526"             ,	   0x1180080e08d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4527"             ,	   0x1180080e08d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4528"             ,	   0x1180080e08d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4529"             ,	   0x1180080e08d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4530"             ,	   0x1180080e08d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4531"             ,	   0x1180080e08d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4532"             ,	   0x1180080e08da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4533"             ,	   0x1180080e08da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4534"             ,	   0x1180080e08db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4535"             ,	   0x1180080e08db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4536"             ,	   0x1180080e08dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4537"             ,	   0x1180080e08dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4538"             ,	   0x1180080e08dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4539"             ,	   0x1180080e08dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4540"             ,	   0x1180080e08de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4541"             ,	   0x1180080e08de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4542"             ,	   0x1180080e08df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4543"             ,	   0x1180080e08df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4544"             ,	   0x1180080e08e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4545"             ,	   0x1180080e08e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4546"             ,	   0x1180080e08e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4547"             ,	   0x1180080e08e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4548"             ,	   0x1180080e08e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4549"             ,	   0x1180080e08e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4550"             ,	   0x1180080e08e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4551"             ,	   0x1180080e08e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4552"             ,	   0x1180080e08e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4553"             ,	   0x1180080e08e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4554"             ,	   0x1180080e08e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4555"             ,	   0x1180080e08e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4556"             ,	   0x1180080e08e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4557"             ,	   0x1180080e08e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4558"             ,	   0x1180080e08e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4559"             ,	   0x1180080e08e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4560"             ,	   0x1180080e08e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4561"             ,	   0x1180080e08e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4562"             ,	   0x1180080e08e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4563"             ,	   0x1180080e08e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4564"             ,	   0x1180080e08ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4565"             ,	   0x1180080e08ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4566"             ,	   0x1180080e08eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4567"             ,	   0x1180080e08eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4568"             ,	   0x1180080e08ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4569"             ,	   0x1180080e08ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4570"             ,	   0x1180080e08ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4571"             ,	   0x1180080e08ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4572"             ,	   0x1180080e08ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4573"             ,	   0x1180080e08ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4574"             ,	   0x1180080e08ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4575"             ,	   0x1180080e08ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4576"             ,	   0x1180080e08f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4577"             ,	   0x1180080e08f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4578"             ,	   0x1180080e08f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4579"             ,	   0x1180080e08f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4580"             ,	   0x1180080e08f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4581"             ,	   0x1180080e08f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4582"             ,	   0x1180080e08f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4583"             ,	   0x1180080e08f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4584"             ,	   0x1180080e08f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4585"             ,	   0x1180080e08f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4586"             ,	   0x1180080e08f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4587"             ,	   0x1180080e08f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4588"             ,	   0x1180080e08f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4589"             ,	   0x1180080e08f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4590"             ,	   0x1180080e08f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4591"             ,	   0x1180080e08f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4592"             ,	   0x1180080e08f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4593"             ,	   0x1180080e08f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4594"             ,	   0x1180080e08f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4595"             ,	   0x1180080e08f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4596"             ,	   0x1180080e08fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4597"             ,	   0x1180080e08fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4598"             ,	   0x1180080e08fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4599"             ,	   0x1180080e08fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4600"             ,	   0x1180080e08fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4601"             ,	   0x1180080e08fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4602"             ,	   0x1180080e08fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4603"             ,	   0x1180080e08fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4604"             ,	   0x1180080e08fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4605"             ,	   0x1180080e08fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4606"             ,	   0x1180080e08ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4607"             ,	   0x1180080e08ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4608"             ,	   0x1180080e09000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4609"             ,	   0x1180080e09008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4610"             ,	   0x1180080e09010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4611"             ,	   0x1180080e09018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4612"             ,	   0x1180080e09020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4613"             ,	   0x1180080e09028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4614"             ,	   0x1180080e09030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4615"             ,	   0x1180080e09038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4616"             ,	   0x1180080e09040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4617"             ,	   0x1180080e09048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4618"             ,	   0x1180080e09050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4619"             ,	   0x1180080e09058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4620"             ,	   0x1180080e09060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4621"             ,	   0x1180080e09068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4622"             ,	   0x1180080e09070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4623"             ,	   0x1180080e09078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4624"             ,	   0x1180080e09080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4625"             ,	   0x1180080e09088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4626"             ,	   0x1180080e09090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4627"             ,	   0x1180080e09098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4628"             ,	   0x1180080e090a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4629"             ,	   0x1180080e090a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4630"             ,	   0x1180080e090b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4631"             ,	   0x1180080e090b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4632"             ,	   0x1180080e090c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4633"             ,	   0x1180080e090c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4634"             ,	   0x1180080e090d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4635"             ,	   0x1180080e090d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4636"             ,	   0x1180080e090e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4637"             ,	   0x1180080e090e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4638"             ,	   0x1180080e090f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4639"             ,	   0x1180080e090f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4640"             ,	   0x1180080e09100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4641"             ,	   0x1180080e09108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4642"             ,	   0x1180080e09110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4643"             ,	   0x1180080e09118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4644"             ,	   0x1180080e09120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4645"             ,	   0x1180080e09128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4646"             ,	   0x1180080e09130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4647"             ,	   0x1180080e09138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4648"             ,	   0x1180080e09140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4649"             ,	   0x1180080e09148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4650"             ,	   0x1180080e09150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4651"             ,	   0x1180080e09158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4652"             ,	   0x1180080e09160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4653"             ,	   0x1180080e09168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4654"             ,	   0x1180080e09170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4655"             ,	   0x1180080e09178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4656"             ,	   0x1180080e09180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4657"             ,	   0x1180080e09188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4658"             ,	   0x1180080e09190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4659"             ,	   0x1180080e09198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4660"             ,	   0x1180080e091a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4661"             ,	   0x1180080e091a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4662"             ,	   0x1180080e091b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4663"             ,	   0x1180080e091b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4664"             ,	   0x1180080e091c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4665"             ,	   0x1180080e091c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4666"             ,	   0x1180080e091d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4667"             ,	   0x1180080e091d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4668"             ,	   0x1180080e091e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4669"             ,	   0x1180080e091e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4670"             ,	   0x1180080e091f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4671"             ,	   0x1180080e091f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4672"             ,	   0x1180080e09200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4673"             ,	   0x1180080e09208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4674"             ,	   0x1180080e09210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4675"             ,	   0x1180080e09218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4676"             ,	   0x1180080e09220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4677"             ,	   0x1180080e09228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4678"             ,	   0x1180080e09230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4679"             ,	   0x1180080e09238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4680"             ,	   0x1180080e09240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4681"             ,	   0x1180080e09248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4682"             ,	   0x1180080e09250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4683"             ,	   0x1180080e09258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4684"             ,	   0x1180080e09260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4685"             ,	   0x1180080e09268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4686"             ,	   0x1180080e09270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4687"             ,	   0x1180080e09278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4688"             ,	   0x1180080e09280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4689"             ,	   0x1180080e09288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4690"             ,	   0x1180080e09290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4691"             ,	   0x1180080e09298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4692"             ,	   0x1180080e092a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4693"             ,	   0x1180080e092a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4694"             ,	   0x1180080e092b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4695"             ,	   0x1180080e092b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4696"             ,	   0x1180080e092c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4697"             ,	   0x1180080e092c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4698"             ,	   0x1180080e092d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4699"             ,	   0x1180080e092d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4700"             ,	   0x1180080e092e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4701"             ,	   0x1180080e092e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4702"             ,	   0x1180080e092f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4703"             ,	   0x1180080e092f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4704"             ,	   0x1180080e09300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4705"             ,	   0x1180080e09308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4706"             ,	   0x1180080e09310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4707"             ,	   0x1180080e09318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4708"             ,	   0x1180080e09320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4709"             ,	   0x1180080e09328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4710"             ,	   0x1180080e09330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4711"             ,	   0x1180080e09338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4712"             ,	   0x1180080e09340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4713"             ,	   0x1180080e09348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4714"             ,	   0x1180080e09350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4715"             ,	   0x1180080e09358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4716"             ,	   0x1180080e09360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4717"             ,	   0x1180080e09368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4718"             ,	   0x1180080e09370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4719"             ,	   0x1180080e09378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4720"             ,	   0x1180080e09380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4721"             ,	   0x1180080e09388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4722"             ,	   0x1180080e09390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4723"             ,	   0x1180080e09398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4724"             ,	   0x1180080e093a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4725"             ,	   0x1180080e093a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4726"             ,	   0x1180080e093b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4727"             ,	   0x1180080e093b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4728"             ,	   0x1180080e093c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4729"             ,	   0x1180080e093c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4730"             ,	   0x1180080e093d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4731"             ,	   0x1180080e093d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4732"             ,	   0x1180080e093e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4733"             ,	   0x1180080e093e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4734"             ,	   0x1180080e093f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4735"             ,	   0x1180080e093f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4736"             ,	   0x1180080e09400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4737"             ,	   0x1180080e09408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4738"             ,	   0x1180080e09410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4739"             ,	   0x1180080e09418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4740"             ,	   0x1180080e09420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4741"             ,	   0x1180080e09428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4742"             ,	   0x1180080e09430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4743"             ,	   0x1180080e09438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4744"             ,	   0x1180080e09440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4745"             ,	   0x1180080e09448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4746"             ,	   0x1180080e09450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4747"             ,	   0x1180080e09458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4748"             ,	   0x1180080e09460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4749"             ,	   0x1180080e09468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4750"             ,	   0x1180080e09470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4751"             ,	   0x1180080e09478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4752"             ,	   0x1180080e09480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4753"             ,	   0x1180080e09488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4754"             ,	   0x1180080e09490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4755"             ,	   0x1180080e09498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4756"             ,	   0x1180080e094a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4757"             ,	   0x1180080e094a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4758"             ,	   0x1180080e094b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4759"             ,	   0x1180080e094b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4760"             ,	   0x1180080e094c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4761"             ,	   0x1180080e094c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4762"             ,	   0x1180080e094d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4763"             ,	   0x1180080e094d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4764"             ,	   0x1180080e094e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4765"             ,	   0x1180080e094e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4766"             ,	   0x1180080e094f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4767"             ,	   0x1180080e094f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4768"             ,	   0x1180080e09500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4769"             ,	   0x1180080e09508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4770"             ,	   0x1180080e09510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4771"             ,	   0x1180080e09518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4772"             ,	   0x1180080e09520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4773"             ,	   0x1180080e09528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4774"             ,	   0x1180080e09530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4775"             ,	   0x1180080e09538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4776"             ,	   0x1180080e09540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4777"             ,	   0x1180080e09548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4778"             ,	   0x1180080e09550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4779"             ,	   0x1180080e09558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4780"             ,	   0x1180080e09560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4781"             ,	   0x1180080e09568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4782"             ,	   0x1180080e09570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4783"             ,	   0x1180080e09578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4784"             ,	   0x1180080e09580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4785"             ,	   0x1180080e09588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4786"             ,	   0x1180080e09590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4787"             ,	   0x1180080e09598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4788"             ,	   0x1180080e095a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4789"             ,	   0x1180080e095a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4790"             ,	   0x1180080e095b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4791"             ,	   0x1180080e095b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4792"             ,	   0x1180080e095c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4793"             ,	   0x1180080e095c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4794"             ,	   0x1180080e095d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4795"             ,	   0x1180080e095d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4796"             ,	   0x1180080e095e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4797"             ,	   0x1180080e095e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4798"             ,	   0x1180080e095f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4799"             ,	   0x1180080e095f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4800"             ,	   0x1180080e09600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4801"             ,	   0x1180080e09608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4802"             ,	   0x1180080e09610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4803"             ,	   0x1180080e09618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4804"             ,	   0x1180080e09620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4805"             ,	   0x1180080e09628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4806"             ,	   0x1180080e09630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4807"             ,	   0x1180080e09638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4808"             ,	   0x1180080e09640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4809"             ,	   0x1180080e09648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4810"             ,	   0x1180080e09650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4811"             ,	   0x1180080e09658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4812"             ,	   0x1180080e09660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4813"             ,	   0x1180080e09668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4814"             ,	   0x1180080e09670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4815"             ,	   0x1180080e09678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4816"             ,	   0x1180080e09680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4817"             ,	   0x1180080e09688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4818"             ,	   0x1180080e09690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4819"             ,	   0x1180080e09698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4820"             ,	   0x1180080e096a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4821"             ,	   0x1180080e096a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4822"             ,	   0x1180080e096b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4823"             ,	   0x1180080e096b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4824"             ,	   0x1180080e096c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4825"             ,	   0x1180080e096c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4826"             ,	   0x1180080e096d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4827"             ,	   0x1180080e096d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4828"             ,	   0x1180080e096e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4829"             ,	   0x1180080e096e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4830"             ,	   0x1180080e096f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4831"             ,	   0x1180080e096f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4832"             ,	   0x1180080e09700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4833"             ,	   0x1180080e09708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4834"             ,	   0x1180080e09710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4835"             ,	   0x1180080e09718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4836"             ,	   0x1180080e09720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4837"             ,	   0x1180080e09728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4838"             ,	   0x1180080e09730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4839"             ,	   0x1180080e09738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4840"             ,	   0x1180080e09740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4841"             ,	   0x1180080e09748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4842"             ,	   0x1180080e09750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4843"             ,	   0x1180080e09758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4844"             ,	   0x1180080e09760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4845"             ,	   0x1180080e09768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4846"             ,	   0x1180080e09770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4847"             ,	   0x1180080e09778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4848"             ,	   0x1180080e09780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4849"             ,	   0x1180080e09788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4850"             ,	   0x1180080e09790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4851"             ,	   0x1180080e09798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4852"             ,	   0x1180080e097a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4853"             ,	   0x1180080e097a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4854"             ,	   0x1180080e097b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4855"             ,	   0x1180080e097b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4856"             ,	   0x1180080e097c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4857"             ,	   0x1180080e097c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4858"             ,	   0x1180080e097d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4859"             ,	   0x1180080e097d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4860"             ,	   0x1180080e097e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4861"             ,	   0x1180080e097e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4862"             ,	   0x1180080e097f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4863"             ,	   0x1180080e097f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4864"             ,	   0x1180080e09800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4865"             ,	   0x1180080e09808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4866"             ,	   0x1180080e09810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4867"             ,	   0x1180080e09818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4868"             ,	   0x1180080e09820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4869"             ,	   0x1180080e09828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4870"             ,	   0x1180080e09830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4871"             ,	   0x1180080e09838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4872"             ,	   0x1180080e09840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4873"             ,	   0x1180080e09848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4874"             ,	   0x1180080e09850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4875"             ,	   0x1180080e09858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4876"             ,	   0x1180080e09860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4877"             ,	   0x1180080e09868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4878"             ,	   0x1180080e09870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4879"             ,	   0x1180080e09878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4880"             ,	   0x1180080e09880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4881"             ,	   0x1180080e09888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4882"             ,	   0x1180080e09890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4883"             ,	   0x1180080e09898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4884"             ,	   0x1180080e098a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4885"             ,	   0x1180080e098a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4886"             ,	   0x1180080e098b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4887"             ,	   0x1180080e098b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4888"             ,	   0x1180080e098c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4889"             ,	   0x1180080e098c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4890"             ,	   0x1180080e098d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4891"             ,	   0x1180080e098d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4892"             ,	   0x1180080e098e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4893"             ,	   0x1180080e098e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4894"             ,	   0x1180080e098f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4895"             ,	   0x1180080e098f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4896"             ,	   0x1180080e09900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4897"             ,	   0x1180080e09908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4898"             ,	   0x1180080e09910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4899"             ,	   0x1180080e09918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4900"             ,	   0x1180080e09920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4901"             ,	   0x1180080e09928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4902"             ,	   0x1180080e09930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4903"             ,	   0x1180080e09938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4904"             ,	   0x1180080e09940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4905"             ,	   0x1180080e09948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4906"             ,	   0x1180080e09950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4907"             ,	   0x1180080e09958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4908"             ,	   0x1180080e09960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4909"             ,	   0x1180080e09968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4910"             ,	   0x1180080e09970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4911"             ,	   0x1180080e09978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4912"             ,	   0x1180080e09980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4913"             ,	   0x1180080e09988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4914"             ,	   0x1180080e09990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4915"             ,	   0x1180080e09998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4916"             ,	   0x1180080e099a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4917"             ,	   0x1180080e099a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4918"             ,	   0x1180080e099b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4919"             ,	   0x1180080e099b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4920"             ,	   0x1180080e099c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4921"             ,	   0x1180080e099c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4922"             ,	   0x1180080e099d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4923"             ,	   0x1180080e099d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4924"             ,	   0x1180080e099e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4925"             ,	   0x1180080e099e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4926"             ,	   0x1180080e099f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4927"             ,	   0x1180080e099f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4928"             ,	   0x1180080e09a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4929"             ,	   0x1180080e09a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4930"             ,	   0x1180080e09a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4931"             ,	   0x1180080e09a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4932"             ,	   0x1180080e09a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4933"             ,	   0x1180080e09a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4934"             ,	   0x1180080e09a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4935"             ,	   0x1180080e09a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4936"             ,	   0x1180080e09a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4937"             ,	   0x1180080e09a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4938"             ,	   0x1180080e09a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4939"             ,	   0x1180080e09a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4940"             ,	   0x1180080e09a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4941"             ,	   0x1180080e09a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4942"             ,	   0x1180080e09a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4943"             ,	   0x1180080e09a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4944"             ,	   0x1180080e09a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4945"             ,	   0x1180080e09a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4946"             ,	   0x1180080e09a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4947"             ,	   0x1180080e09a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4948"             ,	   0x1180080e09aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4949"             ,	   0x1180080e09aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4950"             ,	   0x1180080e09ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4951"             ,	   0x1180080e09ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4952"             ,	   0x1180080e09ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4953"             ,	   0x1180080e09ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4954"             ,	   0x1180080e09ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4955"             ,	   0x1180080e09ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4956"             ,	   0x1180080e09ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4957"             ,	   0x1180080e09ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4958"             ,	   0x1180080e09af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4959"             ,	   0x1180080e09af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4960"             ,	   0x1180080e09b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4961"             ,	   0x1180080e09b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4962"             ,	   0x1180080e09b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4963"             ,	   0x1180080e09b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4964"             ,	   0x1180080e09b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4965"             ,	   0x1180080e09b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4966"             ,	   0x1180080e09b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4967"             ,	   0x1180080e09b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4968"             ,	   0x1180080e09b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4969"             ,	   0x1180080e09b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4970"             ,	   0x1180080e09b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4971"             ,	   0x1180080e09b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4972"             ,	   0x1180080e09b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4973"             ,	   0x1180080e09b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4974"             ,	   0x1180080e09b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4975"             ,	   0x1180080e09b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4976"             ,	   0x1180080e09b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4977"             ,	   0x1180080e09b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4978"             ,	   0x1180080e09b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4979"             ,	   0x1180080e09b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4980"             ,	   0x1180080e09ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4981"             ,	   0x1180080e09ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4982"             ,	   0x1180080e09bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4983"             ,	   0x1180080e09bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4984"             ,	   0x1180080e09bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4985"             ,	   0x1180080e09bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4986"             ,	   0x1180080e09bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4987"             ,	   0x1180080e09bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4988"             ,	   0x1180080e09be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4989"             ,	   0x1180080e09be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4990"             ,	   0x1180080e09bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4991"             ,	   0x1180080e09bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4992"             ,	   0x1180080e09c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4993"             ,	   0x1180080e09c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4994"             ,	   0x1180080e09c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4995"             ,	   0x1180080e09c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4996"             ,	   0x1180080e09c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4997"             ,	   0x1180080e09c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4998"             ,	   0x1180080e09c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP4999"             ,	   0x1180080e09c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5000"             ,	   0x1180080e09c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5001"             ,	   0x1180080e09c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5002"             ,	   0x1180080e09c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5003"             ,	   0x1180080e09c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5004"             ,	   0x1180080e09c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5005"             ,	   0x1180080e09c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5006"             ,	   0x1180080e09c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5007"             ,	   0x1180080e09c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5008"             ,	   0x1180080e09c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5009"             ,	   0x1180080e09c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5010"             ,	   0x1180080e09c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5011"             ,	   0x1180080e09c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5012"             ,	   0x1180080e09ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5013"             ,	   0x1180080e09ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5014"             ,	   0x1180080e09cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5015"             ,	   0x1180080e09cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5016"             ,	   0x1180080e09cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5017"             ,	   0x1180080e09cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5018"             ,	   0x1180080e09cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5019"             ,	   0x1180080e09cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5020"             ,	   0x1180080e09ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5021"             ,	   0x1180080e09ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5022"             ,	   0x1180080e09cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5023"             ,	   0x1180080e09cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5024"             ,	   0x1180080e09d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5025"             ,	   0x1180080e09d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5026"             ,	   0x1180080e09d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5027"             ,	   0x1180080e09d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5028"             ,	   0x1180080e09d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5029"             ,	   0x1180080e09d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5030"             ,	   0x1180080e09d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5031"             ,	   0x1180080e09d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5032"             ,	   0x1180080e09d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5033"             ,	   0x1180080e09d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5034"             ,	   0x1180080e09d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5035"             ,	   0x1180080e09d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5036"             ,	   0x1180080e09d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5037"             ,	   0x1180080e09d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5038"             ,	   0x1180080e09d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5039"             ,	   0x1180080e09d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5040"             ,	   0x1180080e09d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5041"             ,	   0x1180080e09d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5042"             ,	   0x1180080e09d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5043"             ,	   0x1180080e09d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5044"             ,	   0x1180080e09da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5045"             ,	   0x1180080e09da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5046"             ,	   0x1180080e09db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5047"             ,	   0x1180080e09db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5048"             ,	   0x1180080e09dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5049"             ,	   0x1180080e09dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5050"             ,	   0x1180080e09dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5051"             ,	   0x1180080e09dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5052"             ,	   0x1180080e09de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5053"             ,	   0x1180080e09de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5054"             ,	   0x1180080e09df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5055"             ,	   0x1180080e09df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5056"             ,	   0x1180080e09e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5057"             ,	   0x1180080e09e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5058"             ,	   0x1180080e09e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5059"             ,	   0x1180080e09e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5060"             ,	   0x1180080e09e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5061"             ,	   0x1180080e09e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5062"             ,	   0x1180080e09e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5063"             ,	   0x1180080e09e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5064"             ,	   0x1180080e09e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5065"             ,	   0x1180080e09e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5066"             ,	   0x1180080e09e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5067"             ,	   0x1180080e09e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5068"             ,	   0x1180080e09e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5069"             ,	   0x1180080e09e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5070"             ,	   0x1180080e09e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5071"             ,	   0x1180080e09e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5072"             ,	   0x1180080e09e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5073"             ,	   0x1180080e09e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5074"             ,	   0x1180080e09e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5075"             ,	   0x1180080e09e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5076"             ,	   0x1180080e09ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5077"             ,	   0x1180080e09ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5078"             ,	   0x1180080e09eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5079"             ,	   0x1180080e09eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5080"             ,	   0x1180080e09ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5081"             ,	   0x1180080e09ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5082"             ,	   0x1180080e09ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5083"             ,	   0x1180080e09ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5084"             ,	   0x1180080e09ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5085"             ,	   0x1180080e09ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5086"             ,	   0x1180080e09ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5087"             ,	   0x1180080e09ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5088"             ,	   0x1180080e09f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5089"             ,	   0x1180080e09f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5090"             ,	   0x1180080e09f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5091"             ,	   0x1180080e09f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5092"             ,	   0x1180080e09f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5093"             ,	   0x1180080e09f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5094"             ,	   0x1180080e09f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5095"             ,	   0x1180080e09f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5096"             ,	   0x1180080e09f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5097"             ,	   0x1180080e09f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5098"             ,	   0x1180080e09f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5099"             ,	   0x1180080e09f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5100"             ,	   0x1180080e09f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5101"             ,	   0x1180080e09f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5102"             ,	   0x1180080e09f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5103"             ,	   0x1180080e09f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5104"             ,	   0x1180080e09f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5105"             ,	   0x1180080e09f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5106"             ,	   0x1180080e09f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5107"             ,	   0x1180080e09f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5108"             ,	   0x1180080e09fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5109"             ,	   0x1180080e09fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5110"             ,	   0x1180080e09fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5111"             ,	   0x1180080e09fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5112"             ,	   0x1180080e09fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5113"             ,	   0x1180080e09fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5114"             ,	   0x1180080e09fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5115"             ,	   0x1180080e09fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5116"             ,	   0x1180080e09fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5117"             ,	   0x1180080e09fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5118"             ,	   0x1180080e09ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5119"             ,	   0x1180080e09ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5120"             ,	   0x1180080e0a000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5121"             ,	   0x1180080e0a008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5122"             ,	   0x1180080e0a010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5123"             ,	   0x1180080e0a018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5124"             ,	   0x1180080e0a020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5125"             ,	   0x1180080e0a028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5126"             ,	   0x1180080e0a030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5127"             ,	   0x1180080e0a038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5128"             ,	   0x1180080e0a040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5129"             ,	   0x1180080e0a048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5130"             ,	   0x1180080e0a050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5131"             ,	   0x1180080e0a058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5132"             ,	   0x1180080e0a060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5133"             ,	   0x1180080e0a068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5134"             ,	   0x1180080e0a070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5135"             ,	   0x1180080e0a078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5136"             ,	   0x1180080e0a080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5137"             ,	   0x1180080e0a088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5138"             ,	   0x1180080e0a090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5139"             ,	   0x1180080e0a098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5140"             ,	   0x1180080e0a0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5141"             ,	   0x1180080e0a0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5142"             ,	   0x1180080e0a0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5143"             ,	   0x1180080e0a0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5144"             ,	   0x1180080e0a0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5145"             ,	   0x1180080e0a0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5146"             ,	   0x1180080e0a0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5147"             ,	   0x1180080e0a0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5148"             ,	   0x1180080e0a0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5149"             ,	   0x1180080e0a0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5150"             ,	   0x1180080e0a0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5151"             ,	   0x1180080e0a0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5152"             ,	   0x1180080e0a100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5153"             ,	   0x1180080e0a108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5154"             ,	   0x1180080e0a110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5155"             ,	   0x1180080e0a118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5156"             ,	   0x1180080e0a120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5157"             ,	   0x1180080e0a128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5158"             ,	   0x1180080e0a130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5159"             ,	   0x1180080e0a138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5160"             ,	   0x1180080e0a140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5161"             ,	   0x1180080e0a148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5162"             ,	   0x1180080e0a150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5163"             ,	   0x1180080e0a158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5164"             ,	   0x1180080e0a160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5165"             ,	   0x1180080e0a168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5166"             ,	   0x1180080e0a170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5167"             ,	   0x1180080e0a178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5168"             ,	   0x1180080e0a180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5169"             ,	   0x1180080e0a188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5170"             ,	   0x1180080e0a190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5171"             ,	   0x1180080e0a198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5172"             ,	   0x1180080e0a1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5173"             ,	   0x1180080e0a1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5174"             ,	   0x1180080e0a1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5175"             ,	   0x1180080e0a1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5176"             ,	   0x1180080e0a1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5177"             ,	   0x1180080e0a1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5178"             ,	   0x1180080e0a1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5179"             ,	   0x1180080e0a1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5180"             ,	   0x1180080e0a1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5181"             ,	   0x1180080e0a1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5182"             ,	   0x1180080e0a1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5183"             ,	   0x1180080e0a1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5184"             ,	   0x1180080e0a200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5185"             ,	   0x1180080e0a208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5186"             ,	   0x1180080e0a210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5187"             ,	   0x1180080e0a218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5188"             ,	   0x1180080e0a220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5189"             ,	   0x1180080e0a228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5190"             ,	   0x1180080e0a230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5191"             ,	   0x1180080e0a238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5192"             ,	   0x1180080e0a240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5193"             ,	   0x1180080e0a248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5194"             ,	   0x1180080e0a250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5195"             ,	   0x1180080e0a258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5196"             ,	   0x1180080e0a260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5197"             ,	   0x1180080e0a268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5198"             ,	   0x1180080e0a270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5199"             ,	   0x1180080e0a278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5200"             ,	   0x1180080e0a280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5201"             ,	   0x1180080e0a288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5202"             ,	   0x1180080e0a290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5203"             ,	   0x1180080e0a298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5204"             ,	   0x1180080e0a2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5205"             ,	   0x1180080e0a2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5206"             ,	   0x1180080e0a2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5207"             ,	   0x1180080e0a2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5208"             ,	   0x1180080e0a2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5209"             ,	   0x1180080e0a2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5210"             ,	   0x1180080e0a2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5211"             ,	   0x1180080e0a2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5212"             ,	   0x1180080e0a2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5213"             ,	   0x1180080e0a2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5214"             ,	   0x1180080e0a2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5215"             ,	   0x1180080e0a2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5216"             ,	   0x1180080e0a300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5217"             ,	   0x1180080e0a308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5218"             ,	   0x1180080e0a310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5219"             ,	   0x1180080e0a318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5220"             ,	   0x1180080e0a320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5221"             ,	   0x1180080e0a328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5222"             ,	   0x1180080e0a330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5223"             ,	   0x1180080e0a338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5224"             ,	   0x1180080e0a340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5225"             ,	   0x1180080e0a348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5226"             ,	   0x1180080e0a350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5227"             ,	   0x1180080e0a358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5228"             ,	   0x1180080e0a360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5229"             ,	   0x1180080e0a368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5230"             ,	   0x1180080e0a370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5231"             ,	   0x1180080e0a378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5232"             ,	   0x1180080e0a380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5233"             ,	   0x1180080e0a388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5234"             ,	   0x1180080e0a390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5235"             ,	   0x1180080e0a398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5236"             ,	   0x1180080e0a3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5237"             ,	   0x1180080e0a3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5238"             ,	   0x1180080e0a3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5239"             ,	   0x1180080e0a3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5240"             ,	   0x1180080e0a3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5241"             ,	   0x1180080e0a3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5242"             ,	   0x1180080e0a3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5243"             ,	   0x1180080e0a3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5244"             ,	   0x1180080e0a3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5245"             ,	   0x1180080e0a3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5246"             ,	   0x1180080e0a3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5247"             ,	   0x1180080e0a3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5248"             ,	   0x1180080e0a400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5249"             ,	   0x1180080e0a408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5250"             ,	   0x1180080e0a410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5251"             ,	   0x1180080e0a418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5252"             ,	   0x1180080e0a420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5253"             ,	   0x1180080e0a428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5254"             ,	   0x1180080e0a430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5255"             ,	   0x1180080e0a438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5256"             ,	   0x1180080e0a440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5257"             ,	   0x1180080e0a448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5258"             ,	   0x1180080e0a450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5259"             ,	   0x1180080e0a458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5260"             ,	   0x1180080e0a460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5261"             ,	   0x1180080e0a468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5262"             ,	   0x1180080e0a470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5263"             ,	   0x1180080e0a478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5264"             ,	   0x1180080e0a480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5265"             ,	   0x1180080e0a488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5266"             ,	   0x1180080e0a490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5267"             ,	   0x1180080e0a498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5268"             ,	   0x1180080e0a4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5269"             ,	   0x1180080e0a4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5270"             ,	   0x1180080e0a4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5271"             ,	   0x1180080e0a4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5272"             ,	   0x1180080e0a4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5273"             ,	   0x1180080e0a4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5274"             ,	   0x1180080e0a4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5275"             ,	   0x1180080e0a4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5276"             ,	   0x1180080e0a4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5277"             ,	   0x1180080e0a4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5278"             ,	   0x1180080e0a4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5279"             ,	   0x1180080e0a4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5280"             ,	   0x1180080e0a500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5281"             ,	   0x1180080e0a508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5282"             ,	   0x1180080e0a510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5283"             ,	   0x1180080e0a518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5284"             ,	   0x1180080e0a520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5285"             ,	   0x1180080e0a528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5286"             ,	   0x1180080e0a530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5287"             ,	   0x1180080e0a538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5288"             ,	   0x1180080e0a540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5289"             ,	   0x1180080e0a548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5290"             ,	   0x1180080e0a550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5291"             ,	   0x1180080e0a558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5292"             ,	   0x1180080e0a560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5293"             ,	   0x1180080e0a568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5294"             ,	   0x1180080e0a570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5295"             ,	   0x1180080e0a578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5296"             ,	   0x1180080e0a580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5297"             ,	   0x1180080e0a588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5298"             ,	   0x1180080e0a590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5299"             ,	   0x1180080e0a598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5300"             ,	   0x1180080e0a5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5301"             ,	   0x1180080e0a5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5302"             ,	   0x1180080e0a5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5303"             ,	   0x1180080e0a5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5304"             ,	   0x1180080e0a5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5305"             ,	   0x1180080e0a5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5306"             ,	   0x1180080e0a5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5307"             ,	   0x1180080e0a5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5308"             ,	   0x1180080e0a5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5309"             ,	   0x1180080e0a5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5310"             ,	   0x1180080e0a5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5311"             ,	   0x1180080e0a5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5312"             ,	   0x1180080e0a600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5313"             ,	   0x1180080e0a608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5314"             ,	   0x1180080e0a610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5315"             ,	   0x1180080e0a618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5316"             ,	   0x1180080e0a620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5317"             ,	   0x1180080e0a628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5318"             ,	   0x1180080e0a630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5319"             ,	   0x1180080e0a638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5320"             ,	   0x1180080e0a640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5321"             ,	   0x1180080e0a648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5322"             ,	   0x1180080e0a650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5323"             ,	   0x1180080e0a658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5324"             ,	   0x1180080e0a660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5325"             ,	   0x1180080e0a668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5326"             ,	   0x1180080e0a670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5327"             ,	   0x1180080e0a678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5328"             ,	   0x1180080e0a680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5329"             ,	   0x1180080e0a688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5330"             ,	   0x1180080e0a690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5331"             ,	   0x1180080e0a698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5332"             ,	   0x1180080e0a6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5333"             ,	   0x1180080e0a6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5334"             ,	   0x1180080e0a6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5335"             ,	   0x1180080e0a6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5336"             ,	   0x1180080e0a6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5337"             ,	   0x1180080e0a6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5338"             ,	   0x1180080e0a6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5339"             ,	   0x1180080e0a6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5340"             ,	   0x1180080e0a6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5341"             ,	   0x1180080e0a6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5342"             ,	   0x1180080e0a6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5343"             ,	   0x1180080e0a6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5344"             ,	   0x1180080e0a700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5345"             ,	   0x1180080e0a708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5346"             ,	   0x1180080e0a710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5347"             ,	   0x1180080e0a718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5348"             ,	   0x1180080e0a720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5349"             ,	   0x1180080e0a728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5350"             ,	   0x1180080e0a730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5351"             ,	   0x1180080e0a738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5352"             ,	   0x1180080e0a740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5353"             ,	   0x1180080e0a748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5354"             ,	   0x1180080e0a750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5355"             ,	   0x1180080e0a758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5356"             ,	   0x1180080e0a760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5357"             ,	   0x1180080e0a768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5358"             ,	   0x1180080e0a770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5359"             ,	   0x1180080e0a778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5360"             ,	   0x1180080e0a780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5361"             ,	   0x1180080e0a788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5362"             ,	   0x1180080e0a790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5363"             ,	   0x1180080e0a798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5364"             ,	   0x1180080e0a7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5365"             ,	   0x1180080e0a7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5366"             ,	   0x1180080e0a7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5367"             ,	   0x1180080e0a7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5368"             ,	   0x1180080e0a7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5369"             ,	   0x1180080e0a7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5370"             ,	   0x1180080e0a7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5371"             ,	   0x1180080e0a7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5372"             ,	   0x1180080e0a7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5373"             ,	   0x1180080e0a7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5374"             ,	   0x1180080e0a7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5375"             ,	   0x1180080e0a7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5376"             ,	   0x1180080e0a800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5377"             ,	   0x1180080e0a808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5378"             ,	   0x1180080e0a810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5379"             ,	   0x1180080e0a818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5380"             ,	   0x1180080e0a820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5381"             ,	   0x1180080e0a828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5382"             ,	   0x1180080e0a830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5383"             ,	   0x1180080e0a838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5384"             ,	   0x1180080e0a840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5385"             ,	   0x1180080e0a848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5386"             ,	   0x1180080e0a850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5387"             ,	   0x1180080e0a858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5388"             ,	   0x1180080e0a860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5389"             ,	   0x1180080e0a868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5390"             ,	   0x1180080e0a870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5391"             ,	   0x1180080e0a878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5392"             ,	   0x1180080e0a880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5393"             ,	   0x1180080e0a888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5394"             ,	   0x1180080e0a890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5395"             ,	   0x1180080e0a898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5396"             ,	   0x1180080e0a8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5397"             ,	   0x1180080e0a8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5398"             ,	   0x1180080e0a8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5399"             ,	   0x1180080e0a8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5400"             ,	   0x1180080e0a8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5401"             ,	   0x1180080e0a8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5402"             ,	   0x1180080e0a8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5403"             ,	   0x1180080e0a8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5404"             ,	   0x1180080e0a8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5405"             ,	   0x1180080e0a8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5406"             ,	   0x1180080e0a8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5407"             ,	   0x1180080e0a8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5408"             ,	   0x1180080e0a900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5409"             ,	   0x1180080e0a908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5410"             ,	   0x1180080e0a910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5411"             ,	   0x1180080e0a918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5412"             ,	   0x1180080e0a920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5413"             ,	   0x1180080e0a928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5414"             ,	   0x1180080e0a930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5415"             ,	   0x1180080e0a938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5416"             ,	   0x1180080e0a940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5417"             ,	   0x1180080e0a948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5418"             ,	   0x1180080e0a950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5419"             ,	   0x1180080e0a958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5420"             ,	   0x1180080e0a960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5421"             ,	   0x1180080e0a968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5422"             ,	   0x1180080e0a970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5423"             ,	   0x1180080e0a978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5424"             ,	   0x1180080e0a980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5425"             ,	   0x1180080e0a988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5426"             ,	   0x1180080e0a990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5427"             ,	   0x1180080e0a998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5428"             ,	   0x1180080e0a9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5429"             ,	   0x1180080e0a9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5430"             ,	   0x1180080e0a9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5431"             ,	   0x1180080e0a9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5432"             ,	   0x1180080e0a9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5433"             ,	   0x1180080e0a9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5434"             ,	   0x1180080e0a9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5435"             ,	   0x1180080e0a9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5436"             ,	   0x1180080e0a9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5437"             ,	   0x1180080e0a9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5438"             ,	   0x1180080e0a9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5439"             ,	   0x1180080e0a9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5440"             ,	   0x1180080e0aa00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5441"             ,	   0x1180080e0aa08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5442"             ,	   0x1180080e0aa10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5443"             ,	   0x1180080e0aa18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5444"             ,	   0x1180080e0aa20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5445"             ,	   0x1180080e0aa28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5446"             ,	   0x1180080e0aa30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5447"             ,	   0x1180080e0aa38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5448"             ,	   0x1180080e0aa40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5449"             ,	   0x1180080e0aa48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5450"             ,	   0x1180080e0aa50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5451"             ,	   0x1180080e0aa58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5452"             ,	   0x1180080e0aa60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5453"             ,	   0x1180080e0aa68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5454"             ,	   0x1180080e0aa70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5455"             ,	   0x1180080e0aa78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5456"             ,	   0x1180080e0aa80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5457"             ,	   0x1180080e0aa88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5458"             ,	   0x1180080e0aa90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5459"             ,	   0x1180080e0aa98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5460"             ,	   0x1180080e0aaa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5461"             ,	   0x1180080e0aaa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5462"             ,	   0x1180080e0aab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5463"             ,	   0x1180080e0aab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5464"             ,	   0x1180080e0aac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5465"             ,	   0x1180080e0aac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5466"             ,	   0x1180080e0aad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5467"             ,	   0x1180080e0aad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5468"             ,	   0x1180080e0aae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5469"             ,	   0x1180080e0aae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5470"             ,	   0x1180080e0aaf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5471"             ,	   0x1180080e0aaf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5472"             ,	   0x1180080e0ab00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5473"             ,	   0x1180080e0ab08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5474"             ,	   0x1180080e0ab10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5475"             ,	   0x1180080e0ab18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5476"             ,	   0x1180080e0ab20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5477"             ,	   0x1180080e0ab28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5478"             ,	   0x1180080e0ab30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5479"             ,	   0x1180080e0ab38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5480"             ,	   0x1180080e0ab40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5481"             ,	   0x1180080e0ab48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5482"             ,	   0x1180080e0ab50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5483"             ,	   0x1180080e0ab58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5484"             ,	   0x1180080e0ab60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5485"             ,	   0x1180080e0ab68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5486"             ,	   0x1180080e0ab70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5487"             ,	   0x1180080e0ab78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5488"             ,	   0x1180080e0ab80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5489"             ,	   0x1180080e0ab88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5490"             ,	   0x1180080e0ab90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5491"             ,	   0x1180080e0ab98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5492"             ,	   0x1180080e0aba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5493"             ,	   0x1180080e0aba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5494"             ,	   0x1180080e0abb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5495"             ,	   0x1180080e0abb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5496"             ,	   0x1180080e0abc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5497"             ,	   0x1180080e0abc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5498"             ,	   0x1180080e0abd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5499"             ,	   0x1180080e0abd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5500"             ,	   0x1180080e0abe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5501"             ,	   0x1180080e0abe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5502"             ,	   0x1180080e0abf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5503"             ,	   0x1180080e0abf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5504"             ,	   0x1180080e0ac00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5505"             ,	   0x1180080e0ac08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5506"             ,	   0x1180080e0ac10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5507"             ,	   0x1180080e0ac18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5508"             ,	   0x1180080e0ac20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5509"             ,	   0x1180080e0ac28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5510"             ,	   0x1180080e0ac30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5511"             ,	   0x1180080e0ac38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5512"             ,	   0x1180080e0ac40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5513"             ,	   0x1180080e0ac48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5514"             ,	   0x1180080e0ac50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5515"             ,	   0x1180080e0ac58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5516"             ,	   0x1180080e0ac60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5517"             ,	   0x1180080e0ac68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5518"             ,	   0x1180080e0ac70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5519"             ,	   0x1180080e0ac78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5520"             ,	   0x1180080e0ac80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5521"             ,	   0x1180080e0ac88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5522"             ,	   0x1180080e0ac90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5523"             ,	   0x1180080e0ac98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5524"             ,	   0x1180080e0aca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5525"             ,	   0x1180080e0aca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5526"             ,	   0x1180080e0acb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5527"             ,	   0x1180080e0acb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5528"             ,	   0x1180080e0acc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5529"             ,	   0x1180080e0acc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5530"             ,	   0x1180080e0acd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5531"             ,	   0x1180080e0acd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5532"             ,	   0x1180080e0ace0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5533"             ,	   0x1180080e0ace8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5534"             ,	   0x1180080e0acf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5535"             ,	   0x1180080e0acf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5536"             ,	   0x1180080e0ad00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5537"             ,	   0x1180080e0ad08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5538"             ,	   0x1180080e0ad10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5539"             ,	   0x1180080e0ad18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5540"             ,	   0x1180080e0ad20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5541"             ,	   0x1180080e0ad28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5542"             ,	   0x1180080e0ad30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5543"             ,	   0x1180080e0ad38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5544"             ,	   0x1180080e0ad40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5545"             ,	   0x1180080e0ad48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5546"             ,	   0x1180080e0ad50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5547"             ,	   0x1180080e0ad58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5548"             ,	   0x1180080e0ad60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5549"             ,	   0x1180080e0ad68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5550"             ,	   0x1180080e0ad70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5551"             ,	   0x1180080e0ad78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5552"             ,	   0x1180080e0ad80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5553"             ,	   0x1180080e0ad88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5554"             ,	   0x1180080e0ad90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5555"             ,	   0x1180080e0ad98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5556"             ,	   0x1180080e0ada0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5557"             ,	   0x1180080e0ada8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5558"             ,	   0x1180080e0adb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5559"             ,	   0x1180080e0adb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5560"             ,	   0x1180080e0adc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5561"             ,	   0x1180080e0adc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5562"             ,	   0x1180080e0add0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5563"             ,	   0x1180080e0add8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5564"             ,	   0x1180080e0ade0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5565"             ,	   0x1180080e0ade8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5566"             ,	   0x1180080e0adf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5567"             ,	   0x1180080e0adf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5568"             ,	   0x1180080e0ae00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5569"             ,	   0x1180080e0ae08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5570"             ,	   0x1180080e0ae10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5571"             ,	   0x1180080e0ae18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5572"             ,	   0x1180080e0ae20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5573"             ,	   0x1180080e0ae28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5574"             ,	   0x1180080e0ae30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5575"             ,	   0x1180080e0ae38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5576"             ,	   0x1180080e0ae40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5577"             ,	   0x1180080e0ae48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5578"             ,	   0x1180080e0ae50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5579"             ,	   0x1180080e0ae58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5580"             ,	   0x1180080e0ae60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5581"             ,	   0x1180080e0ae68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5582"             ,	   0x1180080e0ae70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5583"             ,	   0x1180080e0ae78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5584"             ,	   0x1180080e0ae80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5585"             ,	   0x1180080e0ae88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5586"             ,	   0x1180080e0ae90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5587"             ,	   0x1180080e0ae98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5588"             ,	   0x1180080e0aea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5589"             ,	   0x1180080e0aea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5590"             ,	   0x1180080e0aeb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5591"             ,	   0x1180080e0aeb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5592"             ,	   0x1180080e0aec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5593"             ,	   0x1180080e0aec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5594"             ,	   0x1180080e0aed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5595"             ,	   0x1180080e0aed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5596"             ,	   0x1180080e0aee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5597"             ,	   0x1180080e0aee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5598"             ,	   0x1180080e0aef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5599"             ,	   0x1180080e0aef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5600"             ,	   0x1180080e0af00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5601"             ,	   0x1180080e0af08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5602"             ,	   0x1180080e0af10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5603"             ,	   0x1180080e0af18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5604"             ,	   0x1180080e0af20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5605"             ,	   0x1180080e0af28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5606"             ,	   0x1180080e0af30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5607"             ,	   0x1180080e0af38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5608"             ,	   0x1180080e0af40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5609"             ,	   0x1180080e0af48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5610"             ,	   0x1180080e0af50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5611"             ,	   0x1180080e0af58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5612"             ,	   0x1180080e0af60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5613"             ,	   0x1180080e0af68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5614"             ,	   0x1180080e0af70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5615"             ,	   0x1180080e0af78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5616"             ,	   0x1180080e0af80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5617"             ,	   0x1180080e0af88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5618"             ,	   0x1180080e0af90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5619"             ,	   0x1180080e0af98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5620"             ,	   0x1180080e0afa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5621"             ,	   0x1180080e0afa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5622"             ,	   0x1180080e0afb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5623"             ,	   0x1180080e0afb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5624"             ,	   0x1180080e0afc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5625"             ,	   0x1180080e0afc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5626"             ,	   0x1180080e0afd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5627"             ,	   0x1180080e0afd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5628"             ,	   0x1180080e0afe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5629"             ,	   0x1180080e0afe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5630"             ,	   0x1180080e0aff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5631"             ,	   0x1180080e0aff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5632"             ,	   0x1180080e0b000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5633"             ,	   0x1180080e0b008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5634"             ,	   0x1180080e0b010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5635"             ,	   0x1180080e0b018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5636"             ,	   0x1180080e0b020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5637"             ,	   0x1180080e0b028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5638"             ,	   0x1180080e0b030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5639"             ,	   0x1180080e0b038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5640"             ,	   0x1180080e0b040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5641"             ,	   0x1180080e0b048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5642"             ,	   0x1180080e0b050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5643"             ,	   0x1180080e0b058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5644"             ,	   0x1180080e0b060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5645"             ,	   0x1180080e0b068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5646"             ,	   0x1180080e0b070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5647"             ,	   0x1180080e0b078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5648"             ,	   0x1180080e0b080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5649"             ,	   0x1180080e0b088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5650"             ,	   0x1180080e0b090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5651"             ,	   0x1180080e0b098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5652"             ,	   0x1180080e0b0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5653"             ,	   0x1180080e0b0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5654"             ,	   0x1180080e0b0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5655"             ,	   0x1180080e0b0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5656"             ,	   0x1180080e0b0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5657"             ,	   0x1180080e0b0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5658"             ,	   0x1180080e0b0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5659"             ,	   0x1180080e0b0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5660"             ,	   0x1180080e0b0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5661"             ,	   0x1180080e0b0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5662"             ,	   0x1180080e0b0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5663"             ,	   0x1180080e0b0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5664"             ,	   0x1180080e0b100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5665"             ,	   0x1180080e0b108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5666"             ,	   0x1180080e0b110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5667"             ,	   0x1180080e0b118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5668"             ,	   0x1180080e0b120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5669"             ,	   0x1180080e0b128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5670"             ,	   0x1180080e0b130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5671"             ,	   0x1180080e0b138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5672"             ,	   0x1180080e0b140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5673"             ,	   0x1180080e0b148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5674"             ,	   0x1180080e0b150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5675"             ,	   0x1180080e0b158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5676"             ,	   0x1180080e0b160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5677"             ,	   0x1180080e0b168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5678"             ,	   0x1180080e0b170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5679"             ,	   0x1180080e0b178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5680"             ,	   0x1180080e0b180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5681"             ,	   0x1180080e0b188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5682"             ,	   0x1180080e0b190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5683"             ,	   0x1180080e0b198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5684"             ,	   0x1180080e0b1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5685"             ,	   0x1180080e0b1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5686"             ,	   0x1180080e0b1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5687"             ,	   0x1180080e0b1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5688"             ,	   0x1180080e0b1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5689"             ,	   0x1180080e0b1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5690"             ,	   0x1180080e0b1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5691"             ,	   0x1180080e0b1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5692"             ,	   0x1180080e0b1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5693"             ,	   0x1180080e0b1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5694"             ,	   0x1180080e0b1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5695"             ,	   0x1180080e0b1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5696"             ,	   0x1180080e0b200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5697"             ,	   0x1180080e0b208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5698"             ,	   0x1180080e0b210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5699"             ,	   0x1180080e0b218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5700"             ,	   0x1180080e0b220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5701"             ,	   0x1180080e0b228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5702"             ,	   0x1180080e0b230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5703"             ,	   0x1180080e0b238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5704"             ,	   0x1180080e0b240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5705"             ,	   0x1180080e0b248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5706"             ,	   0x1180080e0b250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5707"             ,	   0x1180080e0b258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5708"             ,	   0x1180080e0b260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5709"             ,	   0x1180080e0b268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5710"             ,	   0x1180080e0b270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5711"             ,	   0x1180080e0b278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5712"             ,	   0x1180080e0b280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5713"             ,	   0x1180080e0b288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5714"             ,	   0x1180080e0b290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5715"             ,	   0x1180080e0b298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5716"             ,	   0x1180080e0b2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5717"             ,	   0x1180080e0b2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5718"             ,	   0x1180080e0b2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5719"             ,	   0x1180080e0b2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5720"             ,	   0x1180080e0b2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5721"             ,	   0x1180080e0b2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5722"             ,	   0x1180080e0b2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5723"             ,	   0x1180080e0b2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5724"             ,	   0x1180080e0b2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5725"             ,	   0x1180080e0b2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5726"             ,	   0x1180080e0b2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5727"             ,	   0x1180080e0b2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5728"             ,	   0x1180080e0b300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5729"             ,	   0x1180080e0b308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5730"             ,	   0x1180080e0b310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5731"             ,	   0x1180080e0b318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5732"             ,	   0x1180080e0b320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5733"             ,	   0x1180080e0b328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5734"             ,	   0x1180080e0b330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5735"             ,	   0x1180080e0b338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5736"             ,	   0x1180080e0b340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5737"             ,	   0x1180080e0b348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5738"             ,	   0x1180080e0b350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5739"             ,	   0x1180080e0b358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5740"             ,	   0x1180080e0b360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5741"             ,	   0x1180080e0b368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5742"             ,	   0x1180080e0b370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5743"             ,	   0x1180080e0b378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5744"             ,	   0x1180080e0b380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5745"             ,	   0x1180080e0b388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5746"             ,	   0x1180080e0b390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5747"             ,	   0x1180080e0b398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5748"             ,	   0x1180080e0b3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5749"             ,	   0x1180080e0b3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5750"             ,	   0x1180080e0b3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5751"             ,	   0x1180080e0b3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5752"             ,	   0x1180080e0b3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5753"             ,	   0x1180080e0b3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5754"             ,	   0x1180080e0b3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5755"             ,	   0x1180080e0b3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5756"             ,	   0x1180080e0b3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5757"             ,	   0x1180080e0b3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5758"             ,	   0x1180080e0b3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5759"             ,	   0x1180080e0b3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5760"             ,	   0x1180080e0b400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5761"             ,	   0x1180080e0b408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5762"             ,	   0x1180080e0b410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5763"             ,	   0x1180080e0b418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5764"             ,	   0x1180080e0b420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5765"             ,	   0x1180080e0b428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5766"             ,	   0x1180080e0b430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5767"             ,	   0x1180080e0b438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5768"             ,	   0x1180080e0b440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5769"             ,	   0x1180080e0b448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5770"             ,	   0x1180080e0b450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5771"             ,	   0x1180080e0b458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5772"             ,	   0x1180080e0b460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5773"             ,	   0x1180080e0b468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5774"             ,	   0x1180080e0b470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5775"             ,	   0x1180080e0b478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5776"             ,	   0x1180080e0b480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5777"             ,	   0x1180080e0b488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5778"             ,	   0x1180080e0b490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5779"             ,	   0x1180080e0b498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5780"             ,	   0x1180080e0b4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5781"             ,	   0x1180080e0b4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5782"             ,	   0x1180080e0b4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5783"             ,	   0x1180080e0b4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5784"             ,	   0x1180080e0b4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5785"             ,	   0x1180080e0b4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5786"             ,	   0x1180080e0b4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5787"             ,	   0x1180080e0b4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5788"             ,	   0x1180080e0b4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5789"             ,	   0x1180080e0b4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5790"             ,	   0x1180080e0b4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5791"             ,	   0x1180080e0b4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5792"             ,	   0x1180080e0b500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5793"             ,	   0x1180080e0b508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5794"             ,	   0x1180080e0b510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5795"             ,	   0x1180080e0b518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5796"             ,	   0x1180080e0b520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5797"             ,	   0x1180080e0b528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5798"             ,	   0x1180080e0b530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5799"             ,	   0x1180080e0b538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5800"             ,	   0x1180080e0b540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5801"             ,	   0x1180080e0b548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5802"             ,	   0x1180080e0b550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5803"             ,	   0x1180080e0b558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5804"             ,	   0x1180080e0b560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5805"             ,	   0x1180080e0b568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5806"             ,	   0x1180080e0b570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5807"             ,	   0x1180080e0b578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5808"             ,	   0x1180080e0b580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5809"             ,	   0x1180080e0b588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5810"             ,	   0x1180080e0b590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5811"             ,	   0x1180080e0b598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5812"             ,	   0x1180080e0b5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5813"             ,	   0x1180080e0b5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5814"             ,	   0x1180080e0b5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5815"             ,	   0x1180080e0b5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5816"             ,	   0x1180080e0b5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5817"             ,	   0x1180080e0b5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5818"             ,	   0x1180080e0b5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5819"             ,	   0x1180080e0b5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5820"             ,	   0x1180080e0b5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5821"             ,	   0x1180080e0b5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5822"             ,	   0x1180080e0b5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5823"             ,	   0x1180080e0b5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5824"             ,	   0x1180080e0b600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5825"             ,	   0x1180080e0b608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5826"             ,	   0x1180080e0b610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5827"             ,	   0x1180080e0b618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5828"             ,	   0x1180080e0b620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5829"             ,	   0x1180080e0b628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5830"             ,	   0x1180080e0b630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5831"             ,	   0x1180080e0b638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5832"             ,	   0x1180080e0b640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5833"             ,	   0x1180080e0b648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5834"             ,	   0x1180080e0b650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5835"             ,	   0x1180080e0b658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5836"             ,	   0x1180080e0b660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5837"             ,	   0x1180080e0b668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5838"             ,	   0x1180080e0b670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5839"             ,	   0x1180080e0b678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5840"             ,	   0x1180080e0b680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5841"             ,	   0x1180080e0b688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5842"             ,	   0x1180080e0b690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5843"             ,	   0x1180080e0b698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5844"             ,	   0x1180080e0b6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5845"             ,	   0x1180080e0b6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5846"             ,	   0x1180080e0b6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5847"             ,	   0x1180080e0b6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5848"             ,	   0x1180080e0b6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5849"             ,	   0x1180080e0b6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5850"             ,	   0x1180080e0b6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5851"             ,	   0x1180080e0b6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5852"             ,	   0x1180080e0b6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5853"             ,	   0x1180080e0b6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5854"             ,	   0x1180080e0b6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5855"             ,	   0x1180080e0b6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5856"             ,	   0x1180080e0b700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5857"             ,	   0x1180080e0b708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5858"             ,	   0x1180080e0b710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5859"             ,	   0x1180080e0b718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5860"             ,	   0x1180080e0b720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5861"             ,	   0x1180080e0b728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5862"             ,	   0x1180080e0b730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5863"             ,	   0x1180080e0b738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5864"             ,	   0x1180080e0b740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5865"             ,	   0x1180080e0b748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5866"             ,	   0x1180080e0b750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5867"             ,	   0x1180080e0b758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5868"             ,	   0x1180080e0b760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5869"             ,	   0x1180080e0b768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5870"             ,	   0x1180080e0b770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5871"             ,	   0x1180080e0b778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5872"             ,	   0x1180080e0b780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5873"             ,	   0x1180080e0b788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5874"             ,	   0x1180080e0b790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5875"             ,	   0x1180080e0b798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5876"             ,	   0x1180080e0b7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5877"             ,	   0x1180080e0b7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5878"             ,	   0x1180080e0b7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5879"             ,	   0x1180080e0b7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5880"             ,	   0x1180080e0b7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5881"             ,	   0x1180080e0b7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5882"             ,	   0x1180080e0b7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5883"             ,	   0x1180080e0b7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5884"             ,	   0x1180080e0b7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5885"             ,	   0x1180080e0b7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5886"             ,	   0x1180080e0b7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5887"             ,	   0x1180080e0b7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5888"             ,	   0x1180080e0b800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5889"             ,	   0x1180080e0b808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5890"             ,	   0x1180080e0b810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5891"             ,	   0x1180080e0b818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5892"             ,	   0x1180080e0b820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5893"             ,	   0x1180080e0b828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5894"             ,	   0x1180080e0b830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5895"             ,	   0x1180080e0b838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5896"             ,	   0x1180080e0b840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5897"             ,	   0x1180080e0b848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5898"             ,	   0x1180080e0b850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5899"             ,	   0x1180080e0b858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5900"             ,	   0x1180080e0b860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5901"             ,	   0x1180080e0b868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5902"             ,	   0x1180080e0b870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5903"             ,	   0x1180080e0b878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5904"             ,	   0x1180080e0b880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5905"             ,	   0x1180080e0b888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5906"             ,	   0x1180080e0b890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5907"             ,	   0x1180080e0b898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5908"             ,	   0x1180080e0b8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5909"             ,	   0x1180080e0b8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5910"             ,	   0x1180080e0b8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5911"             ,	   0x1180080e0b8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5912"             ,	   0x1180080e0b8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5913"             ,	   0x1180080e0b8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5914"             ,	   0x1180080e0b8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5915"             ,	   0x1180080e0b8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5916"             ,	   0x1180080e0b8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5917"             ,	   0x1180080e0b8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5918"             ,	   0x1180080e0b8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5919"             ,	   0x1180080e0b8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5920"             ,	   0x1180080e0b900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5921"             ,	   0x1180080e0b908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5922"             ,	   0x1180080e0b910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5923"             ,	   0x1180080e0b918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5924"             ,	   0x1180080e0b920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5925"             ,	   0x1180080e0b928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5926"             ,	   0x1180080e0b930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5927"             ,	   0x1180080e0b938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5928"             ,	   0x1180080e0b940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5929"             ,	   0x1180080e0b948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5930"             ,	   0x1180080e0b950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5931"             ,	   0x1180080e0b958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5932"             ,	   0x1180080e0b960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5933"             ,	   0x1180080e0b968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5934"             ,	   0x1180080e0b970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5935"             ,	   0x1180080e0b978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5936"             ,	   0x1180080e0b980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5937"             ,	   0x1180080e0b988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5938"             ,	   0x1180080e0b990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5939"             ,	   0x1180080e0b998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5940"             ,	   0x1180080e0b9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5941"             ,	   0x1180080e0b9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5942"             ,	   0x1180080e0b9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5943"             ,	   0x1180080e0b9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5944"             ,	   0x1180080e0b9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5945"             ,	   0x1180080e0b9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5946"             ,	   0x1180080e0b9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5947"             ,	   0x1180080e0b9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5948"             ,	   0x1180080e0b9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5949"             ,	   0x1180080e0b9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5950"             ,	   0x1180080e0b9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5951"             ,	   0x1180080e0b9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5952"             ,	   0x1180080e0ba00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5953"             ,	   0x1180080e0ba08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5954"             ,	   0x1180080e0ba10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5955"             ,	   0x1180080e0ba18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5956"             ,	   0x1180080e0ba20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5957"             ,	   0x1180080e0ba28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5958"             ,	   0x1180080e0ba30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5959"             ,	   0x1180080e0ba38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5960"             ,	   0x1180080e0ba40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5961"             ,	   0x1180080e0ba48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5962"             ,	   0x1180080e0ba50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5963"             ,	   0x1180080e0ba58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5964"             ,	   0x1180080e0ba60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5965"             ,	   0x1180080e0ba68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5966"             ,	   0x1180080e0ba70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5967"             ,	   0x1180080e0ba78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5968"             ,	   0x1180080e0ba80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5969"             ,	   0x1180080e0ba88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5970"             ,	   0x1180080e0ba90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5971"             ,	   0x1180080e0ba98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5972"             ,	   0x1180080e0baa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5973"             ,	   0x1180080e0baa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5974"             ,	   0x1180080e0bab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5975"             ,	   0x1180080e0bab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5976"             ,	   0x1180080e0bac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5977"             ,	   0x1180080e0bac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5978"             ,	   0x1180080e0bad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5979"             ,	   0x1180080e0bad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5980"             ,	   0x1180080e0bae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5981"             ,	   0x1180080e0bae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5982"             ,	   0x1180080e0baf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5983"             ,	   0x1180080e0baf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5984"             ,	   0x1180080e0bb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5985"             ,	   0x1180080e0bb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5986"             ,	   0x1180080e0bb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5987"             ,	   0x1180080e0bb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5988"             ,	   0x1180080e0bb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5989"             ,	   0x1180080e0bb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5990"             ,	   0x1180080e0bb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5991"             ,	   0x1180080e0bb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5992"             ,	   0x1180080e0bb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5993"             ,	   0x1180080e0bb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5994"             ,	   0x1180080e0bb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5995"             ,	   0x1180080e0bb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5996"             ,	   0x1180080e0bb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5997"             ,	   0x1180080e0bb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5998"             ,	   0x1180080e0bb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP5999"             ,	   0x1180080e0bb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6000"             ,	   0x1180080e0bb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6001"             ,	   0x1180080e0bb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6002"             ,	   0x1180080e0bb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6003"             ,	   0x1180080e0bb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6004"             ,	   0x1180080e0bba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6005"             ,	   0x1180080e0bba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6006"             ,	   0x1180080e0bbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6007"             ,	   0x1180080e0bbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6008"             ,	   0x1180080e0bbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6009"             ,	   0x1180080e0bbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6010"             ,	   0x1180080e0bbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6011"             ,	   0x1180080e0bbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6012"             ,	   0x1180080e0bbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6013"             ,	   0x1180080e0bbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6014"             ,	   0x1180080e0bbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6015"             ,	   0x1180080e0bbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6016"             ,	   0x1180080e0bc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6017"             ,	   0x1180080e0bc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6018"             ,	   0x1180080e0bc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6019"             ,	   0x1180080e0bc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6020"             ,	   0x1180080e0bc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6021"             ,	   0x1180080e0bc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6022"             ,	   0x1180080e0bc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6023"             ,	   0x1180080e0bc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6024"             ,	   0x1180080e0bc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6025"             ,	   0x1180080e0bc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6026"             ,	   0x1180080e0bc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6027"             ,	   0x1180080e0bc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6028"             ,	   0x1180080e0bc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6029"             ,	   0x1180080e0bc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6030"             ,	   0x1180080e0bc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6031"             ,	   0x1180080e0bc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6032"             ,	   0x1180080e0bc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6033"             ,	   0x1180080e0bc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6034"             ,	   0x1180080e0bc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6035"             ,	   0x1180080e0bc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6036"             ,	   0x1180080e0bca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6037"             ,	   0x1180080e0bca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6038"             ,	   0x1180080e0bcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6039"             ,	   0x1180080e0bcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6040"             ,	   0x1180080e0bcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6041"             ,	   0x1180080e0bcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6042"             ,	   0x1180080e0bcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6043"             ,	   0x1180080e0bcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6044"             ,	   0x1180080e0bce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6045"             ,	   0x1180080e0bce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6046"             ,	   0x1180080e0bcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6047"             ,	   0x1180080e0bcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6048"             ,	   0x1180080e0bd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6049"             ,	   0x1180080e0bd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6050"             ,	   0x1180080e0bd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6051"             ,	   0x1180080e0bd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6052"             ,	   0x1180080e0bd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6053"             ,	   0x1180080e0bd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6054"             ,	   0x1180080e0bd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6055"             ,	   0x1180080e0bd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6056"             ,	   0x1180080e0bd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6057"             ,	   0x1180080e0bd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6058"             ,	   0x1180080e0bd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6059"             ,	   0x1180080e0bd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6060"             ,	   0x1180080e0bd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6061"             ,	   0x1180080e0bd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6062"             ,	   0x1180080e0bd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6063"             ,	   0x1180080e0bd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6064"             ,	   0x1180080e0bd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6065"             ,	   0x1180080e0bd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6066"             ,	   0x1180080e0bd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6067"             ,	   0x1180080e0bd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6068"             ,	   0x1180080e0bda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6069"             ,	   0x1180080e0bda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6070"             ,	   0x1180080e0bdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6071"             ,	   0x1180080e0bdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6072"             ,	   0x1180080e0bdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6073"             ,	   0x1180080e0bdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6074"             ,	   0x1180080e0bdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6075"             ,	   0x1180080e0bdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6076"             ,	   0x1180080e0bde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6077"             ,	   0x1180080e0bde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6078"             ,	   0x1180080e0bdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6079"             ,	   0x1180080e0bdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6080"             ,	   0x1180080e0be00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6081"             ,	   0x1180080e0be08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6082"             ,	   0x1180080e0be10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6083"             ,	   0x1180080e0be18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6084"             ,	   0x1180080e0be20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6085"             ,	   0x1180080e0be28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6086"             ,	   0x1180080e0be30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6087"             ,	   0x1180080e0be38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6088"             ,	   0x1180080e0be40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6089"             ,	   0x1180080e0be48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6090"             ,	   0x1180080e0be50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6091"             ,	   0x1180080e0be58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6092"             ,	   0x1180080e0be60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6093"             ,	   0x1180080e0be68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6094"             ,	   0x1180080e0be70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6095"             ,	   0x1180080e0be78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6096"             ,	   0x1180080e0be80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6097"             ,	   0x1180080e0be88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6098"             ,	   0x1180080e0be90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6099"             ,	   0x1180080e0be98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6100"             ,	   0x1180080e0bea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6101"             ,	   0x1180080e0bea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6102"             ,	   0x1180080e0beb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6103"             ,	   0x1180080e0beb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6104"             ,	   0x1180080e0bec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6105"             ,	   0x1180080e0bec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6106"             ,	   0x1180080e0bed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6107"             ,	   0x1180080e0bed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6108"             ,	   0x1180080e0bee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6109"             ,	   0x1180080e0bee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6110"             ,	   0x1180080e0bef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6111"             ,	   0x1180080e0bef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6112"             ,	   0x1180080e0bf00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6113"             ,	   0x1180080e0bf08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6114"             ,	   0x1180080e0bf10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6115"             ,	   0x1180080e0bf18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6116"             ,	   0x1180080e0bf20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6117"             ,	   0x1180080e0bf28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6118"             ,	   0x1180080e0bf30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6119"             ,	   0x1180080e0bf38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6120"             ,	   0x1180080e0bf40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6121"             ,	   0x1180080e0bf48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6122"             ,	   0x1180080e0bf50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6123"             ,	   0x1180080e0bf58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6124"             ,	   0x1180080e0bf60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6125"             ,	   0x1180080e0bf68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6126"             ,	   0x1180080e0bf70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6127"             ,	   0x1180080e0bf78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6128"             ,	   0x1180080e0bf80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6129"             ,	   0x1180080e0bf88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6130"             ,	   0x1180080e0bf90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6131"             ,	   0x1180080e0bf98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6132"             ,	   0x1180080e0bfa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6133"             ,	   0x1180080e0bfa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6134"             ,	   0x1180080e0bfb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6135"             ,	   0x1180080e0bfb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6136"             ,	   0x1180080e0bfc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6137"             ,	   0x1180080e0bfc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6138"             ,	   0x1180080e0bfd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6139"             ,	   0x1180080e0bfd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6140"             ,	   0x1180080e0bfe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6141"             ,	   0x1180080e0bfe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6142"             ,	   0x1180080e0bff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6143"             ,	   0x1180080e0bff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6144"             ,	   0x1180080e0c000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6145"             ,	   0x1180080e0c008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6146"             ,	   0x1180080e0c010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6147"             ,	   0x1180080e0c018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6148"             ,	   0x1180080e0c020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6149"             ,	   0x1180080e0c028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6150"             ,	   0x1180080e0c030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6151"             ,	   0x1180080e0c038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6152"             ,	   0x1180080e0c040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6153"             ,	   0x1180080e0c048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6154"             ,	   0x1180080e0c050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6155"             ,	   0x1180080e0c058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6156"             ,	   0x1180080e0c060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6157"             ,	   0x1180080e0c068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6158"             ,	   0x1180080e0c070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6159"             ,	   0x1180080e0c078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6160"             ,	   0x1180080e0c080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6161"             ,	   0x1180080e0c088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6162"             ,	   0x1180080e0c090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6163"             ,	   0x1180080e0c098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6164"             ,	   0x1180080e0c0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6165"             ,	   0x1180080e0c0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6166"             ,	   0x1180080e0c0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6167"             ,	   0x1180080e0c0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6168"             ,	   0x1180080e0c0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6169"             ,	   0x1180080e0c0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6170"             ,	   0x1180080e0c0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6171"             ,	   0x1180080e0c0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6172"             ,	   0x1180080e0c0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6173"             ,	   0x1180080e0c0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6174"             ,	   0x1180080e0c0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6175"             ,	   0x1180080e0c0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6176"             ,	   0x1180080e0c100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6177"             ,	   0x1180080e0c108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6178"             ,	   0x1180080e0c110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6179"             ,	   0x1180080e0c118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6180"             ,	   0x1180080e0c120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6181"             ,	   0x1180080e0c128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6182"             ,	   0x1180080e0c130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6183"             ,	   0x1180080e0c138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6184"             ,	   0x1180080e0c140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6185"             ,	   0x1180080e0c148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6186"             ,	   0x1180080e0c150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6187"             ,	   0x1180080e0c158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6188"             ,	   0x1180080e0c160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6189"             ,	   0x1180080e0c168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6190"             ,	   0x1180080e0c170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6191"             ,	   0x1180080e0c178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6192"             ,	   0x1180080e0c180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6193"             ,	   0x1180080e0c188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6194"             ,	   0x1180080e0c190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6195"             ,	   0x1180080e0c198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6196"             ,	   0x1180080e0c1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6197"             ,	   0x1180080e0c1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6198"             ,	   0x1180080e0c1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6199"             ,	   0x1180080e0c1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6200"             ,	   0x1180080e0c1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6201"             ,	   0x1180080e0c1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6202"             ,	   0x1180080e0c1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6203"             ,	   0x1180080e0c1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6204"             ,	   0x1180080e0c1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6205"             ,	   0x1180080e0c1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6206"             ,	   0x1180080e0c1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6207"             ,	   0x1180080e0c1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6208"             ,	   0x1180080e0c200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6209"             ,	   0x1180080e0c208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6210"             ,	   0x1180080e0c210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6211"             ,	   0x1180080e0c218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6212"             ,	   0x1180080e0c220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6213"             ,	   0x1180080e0c228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6214"             ,	   0x1180080e0c230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6215"             ,	   0x1180080e0c238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6216"             ,	   0x1180080e0c240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6217"             ,	   0x1180080e0c248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6218"             ,	   0x1180080e0c250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6219"             ,	   0x1180080e0c258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6220"             ,	   0x1180080e0c260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6221"             ,	   0x1180080e0c268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6222"             ,	   0x1180080e0c270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6223"             ,	   0x1180080e0c278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6224"             ,	   0x1180080e0c280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6225"             ,	   0x1180080e0c288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6226"             ,	   0x1180080e0c290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6227"             ,	   0x1180080e0c298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6228"             ,	   0x1180080e0c2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6229"             ,	   0x1180080e0c2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6230"             ,	   0x1180080e0c2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6231"             ,	   0x1180080e0c2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6232"             ,	   0x1180080e0c2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6233"             ,	   0x1180080e0c2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6234"             ,	   0x1180080e0c2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6235"             ,	   0x1180080e0c2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6236"             ,	   0x1180080e0c2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6237"             ,	   0x1180080e0c2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6238"             ,	   0x1180080e0c2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6239"             ,	   0x1180080e0c2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6240"             ,	   0x1180080e0c300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6241"             ,	   0x1180080e0c308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6242"             ,	   0x1180080e0c310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6243"             ,	   0x1180080e0c318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6244"             ,	   0x1180080e0c320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6245"             ,	   0x1180080e0c328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6246"             ,	   0x1180080e0c330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6247"             ,	   0x1180080e0c338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6248"             ,	   0x1180080e0c340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6249"             ,	   0x1180080e0c348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6250"             ,	   0x1180080e0c350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6251"             ,	   0x1180080e0c358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6252"             ,	   0x1180080e0c360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6253"             ,	   0x1180080e0c368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6254"             ,	   0x1180080e0c370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6255"             ,	   0x1180080e0c378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6256"             ,	   0x1180080e0c380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6257"             ,	   0x1180080e0c388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6258"             ,	   0x1180080e0c390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6259"             ,	   0x1180080e0c398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6260"             ,	   0x1180080e0c3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6261"             ,	   0x1180080e0c3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6262"             ,	   0x1180080e0c3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6263"             ,	   0x1180080e0c3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6264"             ,	   0x1180080e0c3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6265"             ,	   0x1180080e0c3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6266"             ,	   0x1180080e0c3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6267"             ,	   0x1180080e0c3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6268"             ,	   0x1180080e0c3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6269"             ,	   0x1180080e0c3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6270"             ,	   0x1180080e0c3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6271"             ,	   0x1180080e0c3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6272"             ,	   0x1180080e0c400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6273"             ,	   0x1180080e0c408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6274"             ,	   0x1180080e0c410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6275"             ,	   0x1180080e0c418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6276"             ,	   0x1180080e0c420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6277"             ,	   0x1180080e0c428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6278"             ,	   0x1180080e0c430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6279"             ,	   0x1180080e0c438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6280"             ,	   0x1180080e0c440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6281"             ,	   0x1180080e0c448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6282"             ,	   0x1180080e0c450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6283"             ,	   0x1180080e0c458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6284"             ,	   0x1180080e0c460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6285"             ,	   0x1180080e0c468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6286"             ,	   0x1180080e0c470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6287"             ,	   0x1180080e0c478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6288"             ,	   0x1180080e0c480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6289"             ,	   0x1180080e0c488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6290"             ,	   0x1180080e0c490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6291"             ,	   0x1180080e0c498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6292"             ,	   0x1180080e0c4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6293"             ,	   0x1180080e0c4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6294"             ,	   0x1180080e0c4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6295"             ,	   0x1180080e0c4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6296"             ,	   0x1180080e0c4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6297"             ,	   0x1180080e0c4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6298"             ,	   0x1180080e0c4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6299"             ,	   0x1180080e0c4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6300"             ,	   0x1180080e0c4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6301"             ,	   0x1180080e0c4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6302"             ,	   0x1180080e0c4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6303"             ,	   0x1180080e0c4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6304"             ,	   0x1180080e0c500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6305"             ,	   0x1180080e0c508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6306"             ,	   0x1180080e0c510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6307"             ,	   0x1180080e0c518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6308"             ,	   0x1180080e0c520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6309"             ,	   0x1180080e0c528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6310"             ,	   0x1180080e0c530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6311"             ,	   0x1180080e0c538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6312"             ,	   0x1180080e0c540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6313"             ,	   0x1180080e0c548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6314"             ,	   0x1180080e0c550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6315"             ,	   0x1180080e0c558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6316"             ,	   0x1180080e0c560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6317"             ,	   0x1180080e0c568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6318"             ,	   0x1180080e0c570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6319"             ,	   0x1180080e0c578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6320"             ,	   0x1180080e0c580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6321"             ,	   0x1180080e0c588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6322"             ,	   0x1180080e0c590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6323"             ,	   0x1180080e0c598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6324"             ,	   0x1180080e0c5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6325"             ,	   0x1180080e0c5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6326"             ,	   0x1180080e0c5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6327"             ,	   0x1180080e0c5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6328"             ,	   0x1180080e0c5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6329"             ,	   0x1180080e0c5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6330"             ,	   0x1180080e0c5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6331"             ,	   0x1180080e0c5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6332"             ,	   0x1180080e0c5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6333"             ,	   0x1180080e0c5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6334"             ,	   0x1180080e0c5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6335"             ,	   0x1180080e0c5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6336"             ,	   0x1180080e0c600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6337"             ,	   0x1180080e0c608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6338"             ,	   0x1180080e0c610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6339"             ,	   0x1180080e0c618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6340"             ,	   0x1180080e0c620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6341"             ,	   0x1180080e0c628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6342"             ,	   0x1180080e0c630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6343"             ,	   0x1180080e0c638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6344"             ,	   0x1180080e0c640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6345"             ,	   0x1180080e0c648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6346"             ,	   0x1180080e0c650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6347"             ,	   0x1180080e0c658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6348"             ,	   0x1180080e0c660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6349"             ,	   0x1180080e0c668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6350"             ,	   0x1180080e0c670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6351"             ,	   0x1180080e0c678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6352"             ,	   0x1180080e0c680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6353"             ,	   0x1180080e0c688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6354"             ,	   0x1180080e0c690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6355"             ,	   0x1180080e0c698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6356"             ,	   0x1180080e0c6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6357"             ,	   0x1180080e0c6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6358"             ,	   0x1180080e0c6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6359"             ,	   0x1180080e0c6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6360"             ,	   0x1180080e0c6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6361"             ,	   0x1180080e0c6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6362"             ,	   0x1180080e0c6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6363"             ,	   0x1180080e0c6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6364"             ,	   0x1180080e0c6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6365"             ,	   0x1180080e0c6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6366"             ,	   0x1180080e0c6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6367"             ,	   0x1180080e0c6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6368"             ,	   0x1180080e0c700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6369"             ,	   0x1180080e0c708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6370"             ,	   0x1180080e0c710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6371"             ,	   0x1180080e0c718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6372"             ,	   0x1180080e0c720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6373"             ,	   0x1180080e0c728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6374"             ,	   0x1180080e0c730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6375"             ,	   0x1180080e0c738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6376"             ,	   0x1180080e0c740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6377"             ,	   0x1180080e0c748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6378"             ,	   0x1180080e0c750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6379"             ,	   0x1180080e0c758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6380"             ,	   0x1180080e0c760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6381"             ,	   0x1180080e0c768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6382"             ,	   0x1180080e0c770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6383"             ,	   0x1180080e0c778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6384"             ,	   0x1180080e0c780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6385"             ,	   0x1180080e0c788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6386"             ,	   0x1180080e0c790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6387"             ,	   0x1180080e0c798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6388"             ,	   0x1180080e0c7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6389"             ,	   0x1180080e0c7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6390"             ,	   0x1180080e0c7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6391"             ,	   0x1180080e0c7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6392"             ,	   0x1180080e0c7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6393"             ,	   0x1180080e0c7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6394"             ,	   0x1180080e0c7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6395"             ,	   0x1180080e0c7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6396"             ,	   0x1180080e0c7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6397"             ,	   0x1180080e0c7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6398"             ,	   0x1180080e0c7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6399"             ,	   0x1180080e0c7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6400"             ,	   0x1180080e0c800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6401"             ,	   0x1180080e0c808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6402"             ,	   0x1180080e0c810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6403"             ,	   0x1180080e0c818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6404"             ,	   0x1180080e0c820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6405"             ,	   0x1180080e0c828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6406"             ,	   0x1180080e0c830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6407"             ,	   0x1180080e0c838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6408"             ,	   0x1180080e0c840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6409"             ,	   0x1180080e0c848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6410"             ,	   0x1180080e0c850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6411"             ,	   0x1180080e0c858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6412"             ,	   0x1180080e0c860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6413"             ,	   0x1180080e0c868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6414"             ,	   0x1180080e0c870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6415"             ,	   0x1180080e0c878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6416"             ,	   0x1180080e0c880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6417"             ,	   0x1180080e0c888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6418"             ,	   0x1180080e0c890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6419"             ,	   0x1180080e0c898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6420"             ,	   0x1180080e0c8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6421"             ,	   0x1180080e0c8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6422"             ,	   0x1180080e0c8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6423"             ,	   0x1180080e0c8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6424"             ,	   0x1180080e0c8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6425"             ,	   0x1180080e0c8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6426"             ,	   0x1180080e0c8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6427"             ,	   0x1180080e0c8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6428"             ,	   0x1180080e0c8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6429"             ,	   0x1180080e0c8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6430"             ,	   0x1180080e0c8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6431"             ,	   0x1180080e0c8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6432"             ,	   0x1180080e0c900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6433"             ,	   0x1180080e0c908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6434"             ,	   0x1180080e0c910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6435"             ,	   0x1180080e0c918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6436"             ,	   0x1180080e0c920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6437"             ,	   0x1180080e0c928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6438"             ,	   0x1180080e0c930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6439"             ,	   0x1180080e0c938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6440"             ,	   0x1180080e0c940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6441"             ,	   0x1180080e0c948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6442"             ,	   0x1180080e0c950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6443"             ,	   0x1180080e0c958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6444"             ,	   0x1180080e0c960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6445"             ,	   0x1180080e0c968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6446"             ,	   0x1180080e0c970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6447"             ,	   0x1180080e0c978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6448"             ,	   0x1180080e0c980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6449"             ,	   0x1180080e0c988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6450"             ,	   0x1180080e0c990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6451"             ,	   0x1180080e0c998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6452"             ,	   0x1180080e0c9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6453"             ,	   0x1180080e0c9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6454"             ,	   0x1180080e0c9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6455"             ,	   0x1180080e0c9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6456"             ,	   0x1180080e0c9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6457"             ,	   0x1180080e0c9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6458"             ,	   0x1180080e0c9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6459"             ,	   0x1180080e0c9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6460"             ,	   0x1180080e0c9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6461"             ,	   0x1180080e0c9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6462"             ,	   0x1180080e0c9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6463"             ,	   0x1180080e0c9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6464"             ,	   0x1180080e0ca00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6465"             ,	   0x1180080e0ca08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6466"             ,	   0x1180080e0ca10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6467"             ,	   0x1180080e0ca18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6468"             ,	   0x1180080e0ca20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6469"             ,	   0x1180080e0ca28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6470"             ,	   0x1180080e0ca30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6471"             ,	   0x1180080e0ca38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6472"             ,	   0x1180080e0ca40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6473"             ,	   0x1180080e0ca48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6474"             ,	   0x1180080e0ca50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6475"             ,	   0x1180080e0ca58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6476"             ,	   0x1180080e0ca60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6477"             ,	   0x1180080e0ca68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6478"             ,	   0x1180080e0ca70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6479"             ,	   0x1180080e0ca78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6480"             ,	   0x1180080e0ca80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6481"             ,	   0x1180080e0ca88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6482"             ,	   0x1180080e0ca90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6483"             ,	   0x1180080e0ca98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6484"             ,	   0x1180080e0caa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6485"             ,	   0x1180080e0caa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6486"             ,	   0x1180080e0cab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6487"             ,	   0x1180080e0cab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6488"             ,	   0x1180080e0cac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6489"             ,	   0x1180080e0cac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6490"             ,	   0x1180080e0cad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6491"             ,	   0x1180080e0cad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6492"             ,	   0x1180080e0cae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6493"             ,	   0x1180080e0cae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6494"             ,	   0x1180080e0caf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6495"             ,	   0x1180080e0caf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6496"             ,	   0x1180080e0cb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6497"             ,	   0x1180080e0cb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6498"             ,	   0x1180080e0cb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6499"             ,	   0x1180080e0cb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6500"             ,	   0x1180080e0cb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6501"             ,	   0x1180080e0cb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6502"             ,	   0x1180080e0cb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6503"             ,	   0x1180080e0cb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6504"             ,	   0x1180080e0cb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6505"             ,	   0x1180080e0cb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6506"             ,	   0x1180080e0cb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6507"             ,	   0x1180080e0cb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6508"             ,	   0x1180080e0cb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6509"             ,	   0x1180080e0cb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6510"             ,	   0x1180080e0cb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6511"             ,	   0x1180080e0cb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6512"             ,	   0x1180080e0cb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6513"             ,	   0x1180080e0cb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6514"             ,	   0x1180080e0cb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6515"             ,	   0x1180080e0cb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6516"             ,	   0x1180080e0cba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6517"             ,	   0x1180080e0cba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6518"             ,	   0x1180080e0cbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6519"             ,	   0x1180080e0cbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6520"             ,	   0x1180080e0cbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6521"             ,	   0x1180080e0cbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6522"             ,	   0x1180080e0cbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6523"             ,	   0x1180080e0cbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6524"             ,	   0x1180080e0cbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6525"             ,	   0x1180080e0cbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6526"             ,	   0x1180080e0cbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6527"             ,	   0x1180080e0cbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6528"             ,	   0x1180080e0cc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6529"             ,	   0x1180080e0cc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6530"             ,	   0x1180080e0cc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6531"             ,	   0x1180080e0cc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6532"             ,	   0x1180080e0cc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6533"             ,	   0x1180080e0cc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6534"             ,	   0x1180080e0cc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6535"             ,	   0x1180080e0cc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6536"             ,	   0x1180080e0cc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6537"             ,	   0x1180080e0cc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6538"             ,	   0x1180080e0cc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6539"             ,	   0x1180080e0cc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6540"             ,	   0x1180080e0cc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6541"             ,	   0x1180080e0cc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6542"             ,	   0x1180080e0cc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6543"             ,	   0x1180080e0cc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6544"             ,	   0x1180080e0cc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6545"             ,	   0x1180080e0cc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6546"             ,	   0x1180080e0cc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6547"             ,	   0x1180080e0cc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6548"             ,	   0x1180080e0cca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6549"             ,	   0x1180080e0cca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6550"             ,	   0x1180080e0ccb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6551"             ,	   0x1180080e0ccb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6552"             ,	   0x1180080e0ccc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6553"             ,	   0x1180080e0ccc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6554"             ,	   0x1180080e0ccd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6555"             ,	   0x1180080e0ccd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6556"             ,	   0x1180080e0cce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6557"             ,	   0x1180080e0cce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6558"             ,	   0x1180080e0ccf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6559"             ,	   0x1180080e0ccf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6560"             ,	   0x1180080e0cd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6561"             ,	   0x1180080e0cd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6562"             ,	   0x1180080e0cd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6563"             ,	   0x1180080e0cd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6564"             ,	   0x1180080e0cd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6565"             ,	   0x1180080e0cd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6566"             ,	   0x1180080e0cd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6567"             ,	   0x1180080e0cd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6568"             ,	   0x1180080e0cd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6569"             ,	   0x1180080e0cd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6570"             ,	   0x1180080e0cd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6571"             ,	   0x1180080e0cd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6572"             ,	   0x1180080e0cd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6573"             ,	   0x1180080e0cd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6574"             ,	   0x1180080e0cd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6575"             ,	   0x1180080e0cd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6576"             ,	   0x1180080e0cd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6577"             ,	   0x1180080e0cd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6578"             ,	   0x1180080e0cd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6579"             ,	   0x1180080e0cd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6580"             ,	   0x1180080e0cda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6581"             ,	   0x1180080e0cda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6582"             ,	   0x1180080e0cdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6583"             ,	   0x1180080e0cdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6584"             ,	   0x1180080e0cdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6585"             ,	   0x1180080e0cdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6586"             ,	   0x1180080e0cdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6587"             ,	   0x1180080e0cdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6588"             ,	   0x1180080e0cde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6589"             ,	   0x1180080e0cde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6590"             ,	   0x1180080e0cdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6591"             ,	   0x1180080e0cdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6592"             ,	   0x1180080e0ce00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6593"             ,	   0x1180080e0ce08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6594"             ,	   0x1180080e0ce10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6595"             ,	   0x1180080e0ce18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6596"             ,	   0x1180080e0ce20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6597"             ,	   0x1180080e0ce28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6598"             ,	   0x1180080e0ce30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6599"             ,	   0x1180080e0ce38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6600"             ,	   0x1180080e0ce40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6601"             ,	   0x1180080e0ce48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6602"             ,	   0x1180080e0ce50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6603"             ,	   0x1180080e0ce58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6604"             ,	   0x1180080e0ce60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6605"             ,	   0x1180080e0ce68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6606"             ,	   0x1180080e0ce70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6607"             ,	   0x1180080e0ce78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6608"             ,	   0x1180080e0ce80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6609"             ,	   0x1180080e0ce88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6610"             ,	   0x1180080e0ce90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6611"             ,	   0x1180080e0ce98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6612"             ,	   0x1180080e0cea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6613"             ,	   0x1180080e0cea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6614"             ,	   0x1180080e0ceb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6615"             ,	   0x1180080e0ceb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6616"             ,	   0x1180080e0cec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6617"             ,	   0x1180080e0cec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6618"             ,	   0x1180080e0ced0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6619"             ,	   0x1180080e0ced8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6620"             ,	   0x1180080e0cee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6621"             ,	   0x1180080e0cee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6622"             ,	   0x1180080e0cef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6623"             ,	   0x1180080e0cef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6624"             ,	   0x1180080e0cf00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6625"             ,	   0x1180080e0cf08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6626"             ,	   0x1180080e0cf10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6627"             ,	   0x1180080e0cf18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6628"             ,	   0x1180080e0cf20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6629"             ,	   0x1180080e0cf28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6630"             ,	   0x1180080e0cf30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6631"             ,	   0x1180080e0cf38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6632"             ,	   0x1180080e0cf40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6633"             ,	   0x1180080e0cf48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6634"             ,	   0x1180080e0cf50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6635"             ,	   0x1180080e0cf58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6636"             ,	   0x1180080e0cf60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6637"             ,	   0x1180080e0cf68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6638"             ,	   0x1180080e0cf70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6639"             ,	   0x1180080e0cf78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6640"             ,	   0x1180080e0cf80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6641"             ,	   0x1180080e0cf88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6642"             ,	   0x1180080e0cf90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6643"             ,	   0x1180080e0cf98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6644"             ,	   0x1180080e0cfa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6645"             ,	   0x1180080e0cfa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6646"             ,	   0x1180080e0cfb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6647"             ,	   0x1180080e0cfb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6648"             ,	   0x1180080e0cfc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6649"             ,	   0x1180080e0cfc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6650"             ,	   0x1180080e0cfd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6651"             ,	   0x1180080e0cfd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6652"             ,	   0x1180080e0cfe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6653"             ,	   0x1180080e0cfe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6654"             ,	   0x1180080e0cff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6655"             ,	   0x1180080e0cff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6656"             ,	   0x1180080e0d000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6657"             ,	   0x1180080e0d008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6658"             ,	   0x1180080e0d010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6659"             ,	   0x1180080e0d018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6660"             ,	   0x1180080e0d020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6661"             ,	   0x1180080e0d028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6662"             ,	   0x1180080e0d030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6663"             ,	   0x1180080e0d038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6664"             ,	   0x1180080e0d040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6665"             ,	   0x1180080e0d048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6666"             ,	   0x1180080e0d050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6667"             ,	   0x1180080e0d058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6668"             ,	   0x1180080e0d060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6669"             ,	   0x1180080e0d068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6670"             ,	   0x1180080e0d070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6671"             ,	   0x1180080e0d078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6672"             ,	   0x1180080e0d080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6673"             ,	   0x1180080e0d088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6674"             ,	   0x1180080e0d090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6675"             ,	   0x1180080e0d098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6676"             ,	   0x1180080e0d0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6677"             ,	   0x1180080e0d0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6678"             ,	   0x1180080e0d0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6679"             ,	   0x1180080e0d0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6680"             ,	   0x1180080e0d0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6681"             ,	   0x1180080e0d0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6682"             ,	   0x1180080e0d0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6683"             ,	   0x1180080e0d0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6684"             ,	   0x1180080e0d0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6685"             ,	   0x1180080e0d0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6686"             ,	   0x1180080e0d0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6687"             ,	   0x1180080e0d0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6688"             ,	   0x1180080e0d100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6689"             ,	   0x1180080e0d108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6690"             ,	   0x1180080e0d110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6691"             ,	   0x1180080e0d118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6692"             ,	   0x1180080e0d120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6693"             ,	   0x1180080e0d128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6694"             ,	   0x1180080e0d130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6695"             ,	   0x1180080e0d138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6696"             ,	   0x1180080e0d140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6697"             ,	   0x1180080e0d148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6698"             ,	   0x1180080e0d150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6699"             ,	   0x1180080e0d158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6700"             ,	   0x1180080e0d160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6701"             ,	   0x1180080e0d168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6702"             ,	   0x1180080e0d170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6703"             ,	   0x1180080e0d178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6704"             ,	   0x1180080e0d180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6705"             ,	   0x1180080e0d188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6706"             ,	   0x1180080e0d190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6707"             ,	   0x1180080e0d198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6708"             ,	   0x1180080e0d1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6709"             ,	   0x1180080e0d1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6710"             ,	   0x1180080e0d1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6711"             ,	   0x1180080e0d1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6712"             ,	   0x1180080e0d1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6713"             ,	   0x1180080e0d1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6714"             ,	   0x1180080e0d1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6715"             ,	   0x1180080e0d1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6716"             ,	   0x1180080e0d1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6717"             ,	   0x1180080e0d1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6718"             ,	   0x1180080e0d1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6719"             ,	   0x1180080e0d1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6720"             ,	   0x1180080e0d200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6721"             ,	   0x1180080e0d208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6722"             ,	   0x1180080e0d210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6723"             ,	   0x1180080e0d218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6724"             ,	   0x1180080e0d220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6725"             ,	   0x1180080e0d228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6726"             ,	   0x1180080e0d230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6727"             ,	   0x1180080e0d238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6728"             ,	   0x1180080e0d240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6729"             ,	   0x1180080e0d248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6730"             ,	   0x1180080e0d250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6731"             ,	   0x1180080e0d258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6732"             ,	   0x1180080e0d260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6733"             ,	   0x1180080e0d268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6734"             ,	   0x1180080e0d270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6735"             ,	   0x1180080e0d278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6736"             ,	   0x1180080e0d280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6737"             ,	   0x1180080e0d288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6738"             ,	   0x1180080e0d290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6739"             ,	   0x1180080e0d298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6740"             ,	   0x1180080e0d2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6741"             ,	   0x1180080e0d2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6742"             ,	   0x1180080e0d2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6743"             ,	   0x1180080e0d2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6744"             ,	   0x1180080e0d2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6745"             ,	   0x1180080e0d2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6746"             ,	   0x1180080e0d2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6747"             ,	   0x1180080e0d2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6748"             ,	   0x1180080e0d2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6749"             ,	   0x1180080e0d2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6750"             ,	   0x1180080e0d2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6751"             ,	   0x1180080e0d2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6752"             ,	   0x1180080e0d300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6753"             ,	   0x1180080e0d308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6754"             ,	   0x1180080e0d310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6755"             ,	   0x1180080e0d318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6756"             ,	   0x1180080e0d320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6757"             ,	   0x1180080e0d328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6758"             ,	   0x1180080e0d330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6759"             ,	   0x1180080e0d338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6760"             ,	   0x1180080e0d340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6761"             ,	   0x1180080e0d348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6762"             ,	   0x1180080e0d350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6763"             ,	   0x1180080e0d358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6764"             ,	   0x1180080e0d360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6765"             ,	   0x1180080e0d368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6766"             ,	   0x1180080e0d370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6767"             ,	   0x1180080e0d378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6768"             ,	   0x1180080e0d380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6769"             ,	   0x1180080e0d388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6770"             ,	   0x1180080e0d390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6771"             ,	   0x1180080e0d398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6772"             ,	   0x1180080e0d3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6773"             ,	   0x1180080e0d3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6774"             ,	   0x1180080e0d3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6775"             ,	   0x1180080e0d3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6776"             ,	   0x1180080e0d3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6777"             ,	   0x1180080e0d3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6778"             ,	   0x1180080e0d3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6779"             ,	   0x1180080e0d3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6780"             ,	   0x1180080e0d3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6781"             ,	   0x1180080e0d3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6782"             ,	   0x1180080e0d3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6783"             ,	   0x1180080e0d3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6784"             ,	   0x1180080e0d400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6785"             ,	   0x1180080e0d408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6786"             ,	   0x1180080e0d410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6787"             ,	   0x1180080e0d418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6788"             ,	   0x1180080e0d420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6789"             ,	   0x1180080e0d428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6790"             ,	   0x1180080e0d430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6791"             ,	   0x1180080e0d438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6792"             ,	   0x1180080e0d440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6793"             ,	   0x1180080e0d448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6794"             ,	   0x1180080e0d450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6795"             ,	   0x1180080e0d458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6796"             ,	   0x1180080e0d460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6797"             ,	   0x1180080e0d468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6798"             ,	   0x1180080e0d470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6799"             ,	   0x1180080e0d478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6800"             ,	   0x1180080e0d480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6801"             ,	   0x1180080e0d488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6802"             ,	   0x1180080e0d490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6803"             ,	   0x1180080e0d498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6804"             ,	   0x1180080e0d4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6805"             ,	   0x1180080e0d4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6806"             ,	   0x1180080e0d4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6807"             ,	   0x1180080e0d4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6808"             ,	   0x1180080e0d4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6809"             ,	   0x1180080e0d4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6810"             ,	   0x1180080e0d4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6811"             ,	   0x1180080e0d4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6812"             ,	   0x1180080e0d4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6813"             ,	   0x1180080e0d4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6814"             ,	   0x1180080e0d4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6815"             ,	   0x1180080e0d4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6816"             ,	   0x1180080e0d500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6817"             ,	   0x1180080e0d508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6818"             ,	   0x1180080e0d510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6819"             ,	   0x1180080e0d518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6820"             ,	   0x1180080e0d520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6821"             ,	   0x1180080e0d528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6822"             ,	   0x1180080e0d530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6823"             ,	   0x1180080e0d538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6824"             ,	   0x1180080e0d540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6825"             ,	   0x1180080e0d548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6826"             ,	   0x1180080e0d550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6827"             ,	   0x1180080e0d558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6828"             ,	   0x1180080e0d560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6829"             ,	   0x1180080e0d568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6830"             ,	   0x1180080e0d570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6831"             ,	   0x1180080e0d578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6832"             ,	   0x1180080e0d580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6833"             ,	   0x1180080e0d588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6834"             ,	   0x1180080e0d590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6835"             ,	   0x1180080e0d598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6836"             ,	   0x1180080e0d5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6837"             ,	   0x1180080e0d5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6838"             ,	   0x1180080e0d5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6839"             ,	   0x1180080e0d5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6840"             ,	   0x1180080e0d5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6841"             ,	   0x1180080e0d5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6842"             ,	   0x1180080e0d5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6843"             ,	   0x1180080e0d5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6844"             ,	   0x1180080e0d5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6845"             ,	   0x1180080e0d5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6846"             ,	   0x1180080e0d5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6847"             ,	   0x1180080e0d5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6848"             ,	   0x1180080e0d600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6849"             ,	   0x1180080e0d608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6850"             ,	   0x1180080e0d610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6851"             ,	   0x1180080e0d618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6852"             ,	   0x1180080e0d620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6853"             ,	   0x1180080e0d628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6854"             ,	   0x1180080e0d630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6855"             ,	   0x1180080e0d638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6856"             ,	   0x1180080e0d640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6857"             ,	   0x1180080e0d648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6858"             ,	   0x1180080e0d650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6859"             ,	   0x1180080e0d658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6860"             ,	   0x1180080e0d660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6861"             ,	   0x1180080e0d668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6862"             ,	   0x1180080e0d670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6863"             ,	   0x1180080e0d678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6864"             ,	   0x1180080e0d680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6865"             ,	   0x1180080e0d688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6866"             ,	   0x1180080e0d690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6867"             ,	   0x1180080e0d698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6868"             ,	   0x1180080e0d6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6869"             ,	   0x1180080e0d6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6870"             ,	   0x1180080e0d6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6871"             ,	   0x1180080e0d6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6872"             ,	   0x1180080e0d6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6873"             ,	   0x1180080e0d6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6874"             ,	   0x1180080e0d6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6875"             ,	   0x1180080e0d6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6876"             ,	   0x1180080e0d6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6877"             ,	   0x1180080e0d6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6878"             ,	   0x1180080e0d6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6879"             ,	   0x1180080e0d6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6880"             ,	   0x1180080e0d700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6881"             ,	   0x1180080e0d708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6882"             ,	   0x1180080e0d710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6883"             ,	   0x1180080e0d718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6884"             ,	   0x1180080e0d720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6885"             ,	   0x1180080e0d728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6886"             ,	   0x1180080e0d730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6887"             ,	   0x1180080e0d738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6888"             ,	   0x1180080e0d740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6889"             ,	   0x1180080e0d748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6890"             ,	   0x1180080e0d750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6891"             ,	   0x1180080e0d758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6892"             ,	   0x1180080e0d760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6893"             ,	   0x1180080e0d768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6894"             ,	   0x1180080e0d770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6895"             ,	   0x1180080e0d778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6896"             ,	   0x1180080e0d780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6897"             ,	   0x1180080e0d788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6898"             ,	   0x1180080e0d790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6899"             ,	   0x1180080e0d798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6900"             ,	   0x1180080e0d7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6901"             ,	   0x1180080e0d7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6902"             ,	   0x1180080e0d7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6903"             ,	   0x1180080e0d7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6904"             ,	   0x1180080e0d7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6905"             ,	   0x1180080e0d7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6906"             ,	   0x1180080e0d7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6907"             ,	   0x1180080e0d7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6908"             ,	   0x1180080e0d7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6909"             ,	   0x1180080e0d7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6910"             ,	   0x1180080e0d7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6911"             ,	   0x1180080e0d7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6912"             ,	   0x1180080e0d800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6913"             ,	   0x1180080e0d808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6914"             ,	   0x1180080e0d810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6915"             ,	   0x1180080e0d818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6916"             ,	   0x1180080e0d820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6917"             ,	   0x1180080e0d828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6918"             ,	   0x1180080e0d830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6919"             ,	   0x1180080e0d838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6920"             ,	   0x1180080e0d840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6921"             ,	   0x1180080e0d848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6922"             ,	   0x1180080e0d850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6923"             ,	   0x1180080e0d858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6924"             ,	   0x1180080e0d860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6925"             ,	   0x1180080e0d868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6926"             ,	   0x1180080e0d870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6927"             ,	   0x1180080e0d878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6928"             ,	   0x1180080e0d880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6929"             ,	   0x1180080e0d888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6930"             ,	   0x1180080e0d890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6931"             ,	   0x1180080e0d898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6932"             ,	   0x1180080e0d8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6933"             ,	   0x1180080e0d8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6934"             ,	   0x1180080e0d8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6935"             ,	   0x1180080e0d8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6936"             ,	   0x1180080e0d8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6937"             ,	   0x1180080e0d8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6938"             ,	   0x1180080e0d8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6939"             ,	   0x1180080e0d8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6940"             ,	   0x1180080e0d8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6941"             ,	   0x1180080e0d8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6942"             ,	   0x1180080e0d8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6943"             ,	   0x1180080e0d8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6944"             ,	   0x1180080e0d900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6945"             ,	   0x1180080e0d908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6946"             ,	   0x1180080e0d910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6947"             ,	   0x1180080e0d918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6948"             ,	   0x1180080e0d920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6949"             ,	   0x1180080e0d928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6950"             ,	   0x1180080e0d930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6951"             ,	   0x1180080e0d938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6952"             ,	   0x1180080e0d940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6953"             ,	   0x1180080e0d948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6954"             ,	   0x1180080e0d950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6955"             ,	   0x1180080e0d958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6956"             ,	   0x1180080e0d960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6957"             ,	   0x1180080e0d968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6958"             ,	   0x1180080e0d970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6959"             ,	   0x1180080e0d978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6960"             ,	   0x1180080e0d980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6961"             ,	   0x1180080e0d988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6962"             ,	   0x1180080e0d990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6963"             ,	   0x1180080e0d998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6964"             ,	   0x1180080e0d9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6965"             ,	   0x1180080e0d9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6966"             ,	   0x1180080e0d9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6967"             ,	   0x1180080e0d9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6968"             ,	   0x1180080e0d9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6969"             ,	   0x1180080e0d9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6970"             ,	   0x1180080e0d9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6971"             ,	   0x1180080e0d9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6972"             ,	   0x1180080e0d9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6973"             ,	   0x1180080e0d9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6974"             ,	   0x1180080e0d9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6975"             ,	   0x1180080e0d9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6976"             ,	   0x1180080e0da00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6977"             ,	   0x1180080e0da08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6978"             ,	   0x1180080e0da10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6979"             ,	   0x1180080e0da18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6980"             ,	   0x1180080e0da20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6981"             ,	   0x1180080e0da28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6982"             ,	   0x1180080e0da30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6983"             ,	   0x1180080e0da38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6984"             ,	   0x1180080e0da40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6985"             ,	   0x1180080e0da48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6986"             ,	   0x1180080e0da50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6987"             ,	   0x1180080e0da58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6988"             ,	   0x1180080e0da60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6989"             ,	   0x1180080e0da68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6990"             ,	   0x1180080e0da70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6991"             ,	   0x1180080e0da78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6992"             ,	   0x1180080e0da80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6993"             ,	   0x1180080e0da88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6994"             ,	   0x1180080e0da90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6995"             ,	   0x1180080e0da98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6996"             ,	   0x1180080e0daa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6997"             ,	   0x1180080e0daa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6998"             ,	   0x1180080e0dab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP6999"             ,	   0x1180080e0dab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7000"             ,	   0x1180080e0dac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7001"             ,	   0x1180080e0dac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7002"             ,	   0x1180080e0dad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7003"             ,	   0x1180080e0dad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7004"             ,	   0x1180080e0dae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7005"             ,	   0x1180080e0dae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7006"             ,	   0x1180080e0daf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7007"             ,	   0x1180080e0daf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7008"             ,	   0x1180080e0db00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7009"             ,	   0x1180080e0db08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7010"             ,	   0x1180080e0db10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7011"             ,	   0x1180080e0db18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7012"             ,	   0x1180080e0db20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7013"             ,	   0x1180080e0db28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7014"             ,	   0x1180080e0db30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7015"             ,	   0x1180080e0db38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7016"             ,	   0x1180080e0db40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7017"             ,	   0x1180080e0db48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7018"             ,	   0x1180080e0db50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7019"             ,	   0x1180080e0db58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7020"             ,	   0x1180080e0db60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7021"             ,	   0x1180080e0db68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7022"             ,	   0x1180080e0db70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7023"             ,	   0x1180080e0db78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7024"             ,	   0x1180080e0db80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7025"             ,	   0x1180080e0db88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7026"             ,	   0x1180080e0db90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7027"             ,	   0x1180080e0db98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7028"             ,	   0x1180080e0dba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7029"             ,	   0x1180080e0dba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7030"             ,	   0x1180080e0dbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7031"             ,	   0x1180080e0dbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7032"             ,	   0x1180080e0dbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7033"             ,	   0x1180080e0dbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7034"             ,	   0x1180080e0dbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7035"             ,	   0x1180080e0dbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7036"             ,	   0x1180080e0dbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7037"             ,	   0x1180080e0dbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7038"             ,	   0x1180080e0dbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7039"             ,	   0x1180080e0dbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7040"             ,	   0x1180080e0dc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7041"             ,	   0x1180080e0dc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7042"             ,	   0x1180080e0dc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7043"             ,	   0x1180080e0dc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7044"             ,	   0x1180080e0dc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7045"             ,	   0x1180080e0dc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7046"             ,	   0x1180080e0dc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7047"             ,	   0x1180080e0dc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7048"             ,	   0x1180080e0dc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7049"             ,	   0x1180080e0dc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7050"             ,	   0x1180080e0dc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7051"             ,	   0x1180080e0dc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7052"             ,	   0x1180080e0dc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7053"             ,	   0x1180080e0dc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7054"             ,	   0x1180080e0dc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7055"             ,	   0x1180080e0dc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7056"             ,	   0x1180080e0dc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7057"             ,	   0x1180080e0dc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7058"             ,	   0x1180080e0dc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7059"             ,	   0x1180080e0dc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7060"             ,	   0x1180080e0dca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7061"             ,	   0x1180080e0dca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7062"             ,	   0x1180080e0dcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7063"             ,	   0x1180080e0dcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7064"             ,	   0x1180080e0dcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7065"             ,	   0x1180080e0dcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7066"             ,	   0x1180080e0dcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7067"             ,	   0x1180080e0dcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7068"             ,	   0x1180080e0dce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7069"             ,	   0x1180080e0dce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7070"             ,	   0x1180080e0dcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7071"             ,	   0x1180080e0dcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7072"             ,	   0x1180080e0dd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7073"             ,	   0x1180080e0dd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7074"             ,	   0x1180080e0dd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7075"             ,	   0x1180080e0dd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7076"             ,	   0x1180080e0dd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7077"             ,	   0x1180080e0dd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7078"             ,	   0x1180080e0dd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7079"             ,	   0x1180080e0dd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7080"             ,	   0x1180080e0dd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7081"             ,	   0x1180080e0dd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7082"             ,	   0x1180080e0dd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7083"             ,	   0x1180080e0dd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7084"             ,	   0x1180080e0dd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7085"             ,	   0x1180080e0dd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7086"             ,	   0x1180080e0dd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7087"             ,	   0x1180080e0dd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7088"             ,	   0x1180080e0dd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7089"             ,	   0x1180080e0dd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7090"             ,	   0x1180080e0dd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7091"             ,	   0x1180080e0dd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7092"             ,	   0x1180080e0dda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7093"             ,	   0x1180080e0dda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7094"             ,	   0x1180080e0ddb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7095"             ,	   0x1180080e0ddb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7096"             ,	   0x1180080e0ddc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7097"             ,	   0x1180080e0ddc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7098"             ,	   0x1180080e0ddd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7099"             ,	   0x1180080e0ddd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7100"             ,	   0x1180080e0dde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7101"             ,	   0x1180080e0dde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7102"             ,	   0x1180080e0ddf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7103"             ,	   0x1180080e0ddf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7104"             ,	   0x1180080e0de00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7105"             ,	   0x1180080e0de08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7106"             ,	   0x1180080e0de10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7107"             ,	   0x1180080e0de18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7108"             ,	   0x1180080e0de20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7109"             ,	   0x1180080e0de28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7110"             ,	   0x1180080e0de30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7111"             ,	   0x1180080e0de38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7112"             ,	   0x1180080e0de40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7113"             ,	   0x1180080e0de48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7114"             ,	   0x1180080e0de50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7115"             ,	   0x1180080e0de58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7116"             ,	   0x1180080e0de60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7117"             ,	   0x1180080e0de68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7118"             ,	   0x1180080e0de70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7119"             ,	   0x1180080e0de78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7120"             ,	   0x1180080e0de80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7121"             ,	   0x1180080e0de88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7122"             ,	   0x1180080e0de90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7123"             ,	   0x1180080e0de98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7124"             ,	   0x1180080e0dea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7125"             ,	   0x1180080e0dea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7126"             ,	   0x1180080e0deb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7127"             ,	   0x1180080e0deb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7128"             ,	   0x1180080e0dec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7129"             ,	   0x1180080e0dec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7130"             ,	   0x1180080e0ded0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7131"             ,	   0x1180080e0ded8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7132"             ,	   0x1180080e0dee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7133"             ,	   0x1180080e0dee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7134"             ,	   0x1180080e0def0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7135"             ,	   0x1180080e0def8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7136"             ,	   0x1180080e0df00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7137"             ,	   0x1180080e0df08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7138"             ,	   0x1180080e0df10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7139"             ,	   0x1180080e0df18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7140"             ,	   0x1180080e0df20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7141"             ,	   0x1180080e0df28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7142"             ,	   0x1180080e0df30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7143"             ,	   0x1180080e0df38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7144"             ,	   0x1180080e0df40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7145"             ,	   0x1180080e0df48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7146"             ,	   0x1180080e0df50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7147"             ,	   0x1180080e0df58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7148"             ,	   0x1180080e0df60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7149"             ,	   0x1180080e0df68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7150"             ,	   0x1180080e0df70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7151"             ,	   0x1180080e0df78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7152"             ,	   0x1180080e0df80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7153"             ,	   0x1180080e0df88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7154"             ,	   0x1180080e0df90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7155"             ,	   0x1180080e0df98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7156"             ,	   0x1180080e0dfa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7157"             ,	   0x1180080e0dfa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7158"             ,	   0x1180080e0dfb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7159"             ,	   0x1180080e0dfb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7160"             ,	   0x1180080e0dfc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7161"             ,	   0x1180080e0dfc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7162"             ,	   0x1180080e0dfd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7163"             ,	   0x1180080e0dfd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7164"             ,	   0x1180080e0dfe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7165"             ,	   0x1180080e0dfe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7166"             ,	   0x1180080e0dff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7167"             ,	   0x1180080e0dff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7168"             ,	   0x1180080e0e000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7169"             ,	   0x1180080e0e008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7170"             ,	   0x1180080e0e010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7171"             ,	   0x1180080e0e018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7172"             ,	   0x1180080e0e020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7173"             ,	   0x1180080e0e028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7174"             ,	   0x1180080e0e030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7175"             ,	   0x1180080e0e038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7176"             ,	   0x1180080e0e040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7177"             ,	   0x1180080e0e048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7178"             ,	   0x1180080e0e050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7179"             ,	   0x1180080e0e058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7180"             ,	   0x1180080e0e060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7181"             ,	   0x1180080e0e068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7182"             ,	   0x1180080e0e070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7183"             ,	   0x1180080e0e078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7184"             ,	   0x1180080e0e080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7185"             ,	   0x1180080e0e088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7186"             ,	   0x1180080e0e090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7187"             ,	   0x1180080e0e098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7188"             ,	   0x1180080e0e0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7189"             ,	   0x1180080e0e0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7190"             ,	   0x1180080e0e0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7191"             ,	   0x1180080e0e0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7192"             ,	   0x1180080e0e0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7193"             ,	   0x1180080e0e0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7194"             ,	   0x1180080e0e0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7195"             ,	   0x1180080e0e0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7196"             ,	   0x1180080e0e0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7197"             ,	   0x1180080e0e0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7198"             ,	   0x1180080e0e0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7199"             ,	   0x1180080e0e0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7200"             ,	   0x1180080e0e100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7201"             ,	   0x1180080e0e108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7202"             ,	   0x1180080e0e110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7203"             ,	   0x1180080e0e118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7204"             ,	   0x1180080e0e120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7205"             ,	   0x1180080e0e128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7206"             ,	   0x1180080e0e130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7207"             ,	   0x1180080e0e138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7208"             ,	   0x1180080e0e140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7209"             ,	   0x1180080e0e148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7210"             ,	   0x1180080e0e150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7211"             ,	   0x1180080e0e158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7212"             ,	   0x1180080e0e160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7213"             ,	   0x1180080e0e168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7214"             ,	   0x1180080e0e170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7215"             ,	   0x1180080e0e178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7216"             ,	   0x1180080e0e180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7217"             ,	   0x1180080e0e188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7218"             ,	   0x1180080e0e190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7219"             ,	   0x1180080e0e198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7220"             ,	   0x1180080e0e1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7221"             ,	   0x1180080e0e1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7222"             ,	   0x1180080e0e1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7223"             ,	   0x1180080e0e1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7224"             ,	   0x1180080e0e1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7225"             ,	   0x1180080e0e1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7226"             ,	   0x1180080e0e1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7227"             ,	   0x1180080e0e1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7228"             ,	   0x1180080e0e1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7229"             ,	   0x1180080e0e1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7230"             ,	   0x1180080e0e1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7231"             ,	   0x1180080e0e1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7232"             ,	   0x1180080e0e200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7233"             ,	   0x1180080e0e208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7234"             ,	   0x1180080e0e210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7235"             ,	   0x1180080e0e218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7236"             ,	   0x1180080e0e220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7237"             ,	   0x1180080e0e228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7238"             ,	   0x1180080e0e230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7239"             ,	   0x1180080e0e238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7240"             ,	   0x1180080e0e240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7241"             ,	   0x1180080e0e248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7242"             ,	   0x1180080e0e250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7243"             ,	   0x1180080e0e258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7244"             ,	   0x1180080e0e260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7245"             ,	   0x1180080e0e268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7246"             ,	   0x1180080e0e270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7247"             ,	   0x1180080e0e278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7248"             ,	   0x1180080e0e280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7249"             ,	   0x1180080e0e288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7250"             ,	   0x1180080e0e290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7251"             ,	   0x1180080e0e298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7252"             ,	   0x1180080e0e2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7253"             ,	   0x1180080e0e2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7254"             ,	   0x1180080e0e2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7255"             ,	   0x1180080e0e2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7256"             ,	   0x1180080e0e2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7257"             ,	   0x1180080e0e2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7258"             ,	   0x1180080e0e2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7259"             ,	   0x1180080e0e2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7260"             ,	   0x1180080e0e2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7261"             ,	   0x1180080e0e2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7262"             ,	   0x1180080e0e2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7263"             ,	   0x1180080e0e2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7264"             ,	   0x1180080e0e300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7265"             ,	   0x1180080e0e308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7266"             ,	   0x1180080e0e310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7267"             ,	   0x1180080e0e318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7268"             ,	   0x1180080e0e320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7269"             ,	   0x1180080e0e328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7270"             ,	   0x1180080e0e330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7271"             ,	   0x1180080e0e338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7272"             ,	   0x1180080e0e340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7273"             ,	   0x1180080e0e348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7274"             ,	   0x1180080e0e350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7275"             ,	   0x1180080e0e358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7276"             ,	   0x1180080e0e360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7277"             ,	   0x1180080e0e368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7278"             ,	   0x1180080e0e370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7279"             ,	   0x1180080e0e378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7280"             ,	   0x1180080e0e380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7281"             ,	   0x1180080e0e388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7282"             ,	   0x1180080e0e390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7283"             ,	   0x1180080e0e398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7284"             ,	   0x1180080e0e3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7285"             ,	   0x1180080e0e3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7286"             ,	   0x1180080e0e3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7287"             ,	   0x1180080e0e3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7288"             ,	   0x1180080e0e3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7289"             ,	   0x1180080e0e3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7290"             ,	   0x1180080e0e3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7291"             ,	   0x1180080e0e3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7292"             ,	   0x1180080e0e3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7293"             ,	   0x1180080e0e3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7294"             ,	   0x1180080e0e3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7295"             ,	   0x1180080e0e3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7296"             ,	   0x1180080e0e400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7297"             ,	   0x1180080e0e408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7298"             ,	   0x1180080e0e410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7299"             ,	   0x1180080e0e418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7300"             ,	   0x1180080e0e420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7301"             ,	   0x1180080e0e428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7302"             ,	   0x1180080e0e430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7303"             ,	   0x1180080e0e438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7304"             ,	   0x1180080e0e440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7305"             ,	   0x1180080e0e448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7306"             ,	   0x1180080e0e450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7307"             ,	   0x1180080e0e458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7308"             ,	   0x1180080e0e460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7309"             ,	   0x1180080e0e468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7310"             ,	   0x1180080e0e470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7311"             ,	   0x1180080e0e478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7312"             ,	   0x1180080e0e480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7313"             ,	   0x1180080e0e488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7314"             ,	   0x1180080e0e490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7315"             ,	   0x1180080e0e498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7316"             ,	   0x1180080e0e4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7317"             ,	   0x1180080e0e4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7318"             ,	   0x1180080e0e4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7319"             ,	   0x1180080e0e4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7320"             ,	   0x1180080e0e4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7321"             ,	   0x1180080e0e4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7322"             ,	   0x1180080e0e4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7323"             ,	   0x1180080e0e4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7324"             ,	   0x1180080e0e4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7325"             ,	   0x1180080e0e4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7326"             ,	   0x1180080e0e4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7327"             ,	   0x1180080e0e4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7328"             ,	   0x1180080e0e500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7329"             ,	   0x1180080e0e508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7330"             ,	   0x1180080e0e510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7331"             ,	   0x1180080e0e518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7332"             ,	   0x1180080e0e520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7333"             ,	   0x1180080e0e528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7334"             ,	   0x1180080e0e530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7335"             ,	   0x1180080e0e538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7336"             ,	   0x1180080e0e540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7337"             ,	   0x1180080e0e548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7338"             ,	   0x1180080e0e550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7339"             ,	   0x1180080e0e558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7340"             ,	   0x1180080e0e560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7341"             ,	   0x1180080e0e568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7342"             ,	   0x1180080e0e570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7343"             ,	   0x1180080e0e578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7344"             ,	   0x1180080e0e580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7345"             ,	   0x1180080e0e588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7346"             ,	   0x1180080e0e590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7347"             ,	   0x1180080e0e598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7348"             ,	   0x1180080e0e5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7349"             ,	   0x1180080e0e5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7350"             ,	   0x1180080e0e5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7351"             ,	   0x1180080e0e5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7352"             ,	   0x1180080e0e5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7353"             ,	   0x1180080e0e5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7354"             ,	   0x1180080e0e5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7355"             ,	   0x1180080e0e5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7356"             ,	   0x1180080e0e5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7357"             ,	   0x1180080e0e5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7358"             ,	   0x1180080e0e5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7359"             ,	   0x1180080e0e5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7360"             ,	   0x1180080e0e600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7361"             ,	   0x1180080e0e608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7362"             ,	   0x1180080e0e610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7363"             ,	   0x1180080e0e618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7364"             ,	   0x1180080e0e620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7365"             ,	   0x1180080e0e628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7366"             ,	   0x1180080e0e630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7367"             ,	   0x1180080e0e638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7368"             ,	   0x1180080e0e640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7369"             ,	   0x1180080e0e648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7370"             ,	   0x1180080e0e650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7371"             ,	   0x1180080e0e658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7372"             ,	   0x1180080e0e660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7373"             ,	   0x1180080e0e668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7374"             ,	   0x1180080e0e670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7375"             ,	   0x1180080e0e678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7376"             ,	   0x1180080e0e680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7377"             ,	   0x1180080e0e688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7378"             ,	   0x1180080e0e690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7379"             ,	   0x1180080e0e698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7380"             ,	   0x1180080e0e6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7381"             ,	   0x1180080e0e6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7382"             ,	   0x1180080e0e6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7383"             ,	   0x1180080e0e6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7384"             ,	   0x1180080e0e6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7385"             ,	   0x1180080e0e6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7386"             ,	   0x1180080e0e6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7387"             ,	   0x1180080e0e6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7388"             ,	   0x1180080e0e6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7389"             ,	   0x1180080e0e6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7390"             ,	   0x1180080e0e6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7391"             ,	   0x1180080e0e6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7392"             ,	   0x1180080e0e700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7393"             ,	   0x1180080e0e708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7394"             ,	   0x1180080e0e710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7395"             ,	   0x1180080e0e718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7396"             ,	   0x1180080e0e720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7397"             ,	   0x1180080e0e728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7398"             ,	   0x1180080e0e730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7399"             ,	   0x1180080e0e738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7400"             ,	   0x1180080e0e740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7401"             ,	   0x1180080e0e748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7402"             ,	   0x1180080e0e750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7403"             ,	   0x1180080e0e758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7404"             ,	   0x1180080e0e760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7405"             ,	   0x1180080e0e768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7406"             ,	   0x1180080e0e770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7407"             ,	   0x1180080e0e778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7408"             ,	   0x1180080e0e780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7409"             ,	   0x1180080e0e788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7410"             ,	   0x1180080e0e790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7411"             ,	   0x1180080e0e798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7412"             ,	   0x1180080e0e7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7413"             ,	   0x1180080e0e7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7414"             ,	   0x1180080e0e7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7415"             ,	   0x1180080e0e7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7416"             ,	   0x1180080e0e7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7417"             ,	   0x1180080e0e7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7418"             ,	   0x1180080e0e7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7419"             ,	   0x1180080e0e7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7420"             ,	   0x1180080e0e7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7421"             ,	   0x1180080e0e7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7422"             ,	   0x1180080e0e7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7423"             ,	   0x1180080e0e7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7424"             ,	   0x1180080e0e800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7425"             ,	   0x1180080e0e808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7426"             ,	   0x1180080e0e810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7427"             ,	   0x1180080e0e818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7428"             ,	   0x1180080e0e820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7429"             ,	   0x1180080e0e828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7430"             ,	   0x1180080e0e830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7431"             ,	   0x1180080e0e838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7432"             ,	   0x1180080e0e840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7433"             ,	   0x1180080e0e848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7434"             ,	   0x1180080e0e850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7435"             ,	   0x1180080e0e858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7436"             ,	   0x1180080e0e860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7437"             ,	   0x1180080e0e868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7438"             ,	   0x1180080e0e870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7439"             ,	   0x1180080e0e878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7440"             ,	   0x1180080e0e880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7441"             ,	   0x1180080e0e888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7442"             ,	   0x1180080e0e890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7443"             ,	   0x1180080e0e898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7444"             ,	   0x1180080e0e8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7445"             ,	   0x1180080e0e8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7446"             ,	   0x1180080e0e8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7447"             ,	   0x1180080e0e8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7448"             ,	   0x1180080e0e8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7449"             ,	   0x1180080e0e8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7450"             ,	   0x1180080e0e8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7451"             ,	   0x1180080e0e8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7452"             ,	   0x1180080e0e8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7453"             ,	   0x1180080e0e8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7454"             ,	   0x1180080e0e8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7455"             ,	   0x1180080e0e8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7456"             ,	   0x1180080e0e900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7457"             ,	   0x1180080e0e908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7458"             ,	   0x1180080e0e910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7459"             ,	   0x1180080e0e918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7460"             ,	   0x1180080e0e920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7461"             ,	   0x1180080e0e928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7462"             ,	   0x1180080e0e930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7463"             ,	   0x1180080e0e938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7464"             ,	   0x1180080e0e940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7465"             ,	   0x1180080e0e948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7466"             ,	   0x1180080e0e950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7467"             ,	   0x1180080e0e958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7468"             ,	   0x1180080e0e960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7469"             ,	   0x1180080e0e968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7470"             ,	   0x1180080e0e970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7471"             ,	   0x1180080e0e978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7472"             ,	   0x1180080e0e980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7473"             ,	   0x1180080e0e988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7474"             ,	   0x1180080e0e990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7475"             ,	   0x1180080e0e998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7476"             ,	   0x1180080e0e9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7477"             ,	   0x1180080e0e9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7478"             ,	   0x1180080e0e9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7479"             ,	   0x1180080e0e9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7480"             ,	   0x1180080e0e9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7481"             ,	   0x1180080e0e9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7482"             ,	   0x1180080e0e9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7483"             ,	   0x1180080e0e9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7484"             ,	   0x1180080e0e9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7485"             ,	   0x1180080e0e9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7486"             ,	   0x1180080e0e9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7487"             ,	   0x1180080e0e9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7488"             ,	   0x1180080e0ea00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7489"             ,	   0x1180080e0ea08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7490"             ,	   0x1180080e0ea10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7491"             ,	   0x1180080e0ea18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7492"             ,	   0x1180080e0ea20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7493"             ,	   0x1180080e0ea28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7494"             ,	   0x1180080e0ea30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7495"             ,	   0x1180080e0ea38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7496"             ,	   0x1180080e0ea40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7497"             ,	   0x1180080e0ea48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7498"             ,	   0x1180080e0ea50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7499"             ,	   0x1180080e0ea58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7500"             ,	   0x1180080e0ea60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7501"             ,	   0x1180080e0ea68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7502"             ,	   0x1180080e0ea70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7503"             ,	   0x1180080e0ea78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7504"             ,	   0x1180080e0ea80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7505"             ,	   0x1180080e0ea88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7506"             ,	   0x1180080e0ea90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7507"             ,	   0x1180080e0ea98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7508"             ,	   0x1180080e0eaa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7509"             ,	   0x1180080e0eaa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7510"             ,	   0x1180080e0eab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7511"             ,	   0x1180080e0eab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7512"             ,	   0x1180080e0eac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7513"             ,	   0x1180080e0eac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7514"             ,	   0x1180080e0ead0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7515"             ,	   0x1180080e0ead8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7516"             ,	   0x1180080e0eae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7517"             ,	   0x1180080e0eae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7518"             ,	   0x1180080e0eaf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7519"             ,	   0x1180080e0eaf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7520"             ,	   0x1180080e0eb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7521"             ,	   0x1180080e0eb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7522"             ,	   0x1180080e0eb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7523"             ,	   0x1180080e0eb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7524"             ,	   0x1180080e0eb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7525"             ,	   0x1180080e0eb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7526"             ,	   0x1180080e0eb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7527"             ,	   0x1180080e0eb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7528"             ,	   0x1180080e0eb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7529"             ,	   0x1180080e0eb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7530"             ,	   0x1180080e0eb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7531"             ,	   0x1180080e0eb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7532"             ,	   0x1180080e0eb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7533"             ,	   0x1180080e0eb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7534"             ,	   0x1180080e0eb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7535"             ,	   0x1180080e0eb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7536"             ,	   0x1180080e0eb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7537"             ,	   0x1180080e0eb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7538"             ,	   0x1180080e0eb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7539"             ,	   0x1180080e0eb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7540"             ,	   0x1180080e0eba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7541"             ,	   0x1180080e0eba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7542"             ,	   0x1180080e0ebb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7543"             ,	   0x1180080e0ebb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7544"             ,	   0x1180080e0ebc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7545"             ,	   0x1180080e0ebc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7546"             ,	   0x1180080e0ebd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7547"             ,	   0x1180080e0ebd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7548"             ,	   0x1180080e0ebe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7549"             ,	   0x1180080e0ebe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7550"             ,	   0x1180080e0ebf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7551"             ,	   0x1180080e0ebf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7552"             ,	   0x1180080e0ec00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7553"             ,	   0x1180080e0ec08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7554"             ,	   0x1180080e0ec10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7555"             ,	   0x1180080e0ec18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7556"             ,	   0x1180080e0ec20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7557"             ,	   0x1180080e0ec28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7558"             ,	   0x1180080e0ec30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7559"             ,	   0x1180080e0ec38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7560"             ,	   0x1180080e0ec40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7561"             ,	   0x1180080e0ec48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7562"             ,	   0x1180080e0ec50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7563"             ,	   0x1180080e0ec58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7564"             ,	   0x1180080e0ec60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7565"             ,	   0x1180080e0ec68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7566"             ,	   0x1180080e0ec70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7567"             ,	   0x1180080e0ec78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7568"             ,	   0x1180080e0ec80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7569"             ,	   0x1180080e0ec88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7570"             ,	   0x1180080e0ec90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7571"             ,	   0x1180080e0ec98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7572"             ,	   0x1180080e0eca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7573"             ,	   0x1180080e0eca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7574"             ,	   0x1180080e0ecb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7575"             ,	   0x1180080e0ecb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7576"             ,	   0x1180080e0ecc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7577"             ,	   0x1180080e0ecc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7578"             ,	   0x1180080e0ecd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7579"             ,	   0x1180080e0ecd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7580"             ,	   0x1180080e0ece0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7581"             ,	   0x1180080e0ece8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7582"             ,	   0x1180080e0ecf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7583"             ,	   0x1180080e0ecf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7584"             ,	   0x1180080e0ed00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7585"             ,	   0x1180080e0ed08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7586"             ,	   0x1180080e0ed10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7587"             ,	   0x1180080e0ed18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7588"             ,	   0x1180080e0ed20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7589"             ,	   0x1180080e0ed28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7590"             ,	   0x1180080e0ed30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7591"             ,	   0x1180080e0ed38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7592"             ,	   0x1180080e0ed40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7593"             ,	   0x1180080e0ed48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7594"             ,	   0x1180080e0ed50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7595"             ,	   0x1180080e0ed58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7596"             ,	   0x1180080e0ed60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7597"             ,	   0x1180080e0ed68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7598"             ,	   0x1180080e0ed70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7599"             ,	   0x1180080e0ed78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7600"             ,	   0x1180080e0ed80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7601"             ,	   0x1180080e0ed88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7602"             ,	   0x1180080e0ed90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7603"             ,	   0x1180080e0ed98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7604"             ,	   0x1180080e0eda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7605"             ,	   0x1180080e0eda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7606"             ,	   0x1180080e0edb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7607"             ,	   0x1180080e0edb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7608"             ,	   0x1180080e0edc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7609"             ,	   0x1180080e0edc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7610"             ,	   0x1180080e0edd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7611"             ,	   0x1180080e0edd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7612"             ,	   0x1180080e0ede0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7613"             ,	   0x1180080e0ede8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7614"             ,	   0x1180080e0edf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7615"             ,	   0x1180080e0edf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7616"             ,	   0x1180080e0ee00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7617"             ,	   0x1180080e0ee08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7618"             ,	   0x1180080e0ee10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7619"             ,	   0x1180080e0ee18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7620"             ,	   0x1180080e0ee20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7621"             ,	   0x1180080e0ee28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7622"             ,	   0x1180080e0ee30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7623"             ,	   0x1180080e0ee38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7624"             ,	   0x1180080e0ee40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7625"             ,	   0x1180080e0ee48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7626"             ,	   0x1180080e0ee50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7627"             ,	   0x1180080e0ee58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7628"             ,	   0x1180080e0ee60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7629"             ,	   0x1180080e0ee68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7630"             ,	   0x1180080e0ee70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7631"             ,	   0x1180080e0ee78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7632"             ,	   0x1180080e0ee80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7633"             ,	   0x1180080e0ee88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7634"             ,	   0x1180080e0ee90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7635"             ,	   0x1180080e0ee98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7636"             ,	   0x1180080e0eea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7637"             ,	   0x1180080e0eea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7638"             ,	   0x1180080e0eeb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7639"             ,	   0x1180080e0eeb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7640"             ,	   0x1180080e0eec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7641"             ,	   0x1180080e0eec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7642"             ,	   0x1180080e0eed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7643"             ,	   0x1180080e0eed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7644"             ,	   0x1180080e0eee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7645"             ,	   0x1180080e0eee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7646"             ,	   0x1180080e0eef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7647"             ,	   0x1180080e0eef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7648"             ,	   0x1180080e0ef00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7649"             ,	   0x1180080e0ef08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7650"             ,	   0x1180080e0ef10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7651"             ,	   0x1180080e0ef18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7652"             ,	   0x1180080e0ef20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7653"             ,	   0x1180080e0ef28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7654"             ,	   0x1180080e0ef30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7655"             ,	   0x1180080e0ef38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7656"             ,	   0x1180080e0ef40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7657"             ,	   0x1180080e0ef48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7658"             ,	   0x1180080e0ef50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7659"             ,	   0x1180080e0ef58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7660"             ,	   0x1180080e0ef60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7661"             ,	   0x1180080e0ef68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7662"             ,	   0x1180080e0ef70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7663"             ,	   0x1180080e0ef78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7664"             ,	   0x1180080e0ef80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7665"             ,	   0x1180080e0ef88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7666"             ,	   0x1180080e0ef90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7667"             ,	   0x1180080e0ef98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7668"             ,	   0x1180080e0efa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7669"             ,	   0x1180080e0efa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7670"             ,	   0x1180080e0efb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7671"             ,	   0x1180080e0efb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7672"             ,	   0x1180080e0efc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7673"             ,	   0x1180080e0efc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7674"             ,	   0x1180080e0efd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7675"             ,	   0x1180080e0efd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7676"             ,	   0x1180080e0efe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7677"             ,	   0x1180080e0efe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7678"             ,	   0x1180080e0eff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7679"             ,	   0x1180080e0eff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7680"             ,	   0x1180080e0f000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7681"             ,	   0x1180080e0f008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7682"             ,	   0x1180080e0f010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7683"             ,	   0x1180080e0f018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7684"             ,	   0x1180080e0f020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7685"             ,	   0x1180080e0f028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7686"             ,	   0x1180080e0f030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7687"             ,	   0x1180080e0f038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7688"             ,	   0x1180080e0f040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7689"             ,	   0x1180080e0f048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7690"             ,	   0x1180080e0f050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7691"             ,	   0x1180080e0f058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7692"             ,	   0x1180080e0f060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7693"             ,	   0x1180080e0f068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7694"             ,	   0x1180080e0f070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7695"             ,	   0x1180080e0f078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7696"             ,	   0x1180080e0f080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7697"             ,	   0x1180080e0f088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7698"             ,	   0x1180080e0f090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7699"             ,	   0x1180080e0f098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7700"             ,	   0x1180080e0f0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7701"             ,	   0x1180080e0f0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7702"             ,	   0x1180080e0f0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7703"             ,	   0x1180080e0f0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7704"             ,	   0x1180080e0f0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7705"             ,	   0x1180080e0f0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7706"             ,	   0x1180080e0f0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7707"             ,	   0x1180080e0f0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7708"             ,	   0x1180080e0f0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7709"             ,	   0x1180080e0f0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7710"             ,	   0x1180080e0f0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7711"             ,	   0x1180080e0f0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7712"             ,	   0x1180080e0f100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7713"             ,	   0x1180080e0f108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7714"             ,	   0x1180080e0f110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7715"             ,	   0x1180080e0f118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7716"             ,	   0x1180080e0f120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7717"             ,	   0x1180080e0f128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7718"             ,	   0x1180080e0f130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7719"             ,	   0x1180080e0f138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7720"             ,	   0x1180080e0f140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7721"             ,	   0x1180080e0f148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7722"             ,	   0x1180080e0f150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7723"             ,	   0x1180080e0f158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7724"             ,	   0x1180080e0f160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7725"             ,	   0x1180080e0f168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7726"             ,	   0x1180080e0f170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7727"             ,	   0x1180080e0f178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7728"             ,	   0x1180080e0f180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7729"             ,	   0x1180080e0f188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7730"             ,	   0x1180080e0f190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7731"             ,	   0x1180080e0f198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7732"             ,	   0x1180080e0f1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7733"             ,	   0x1180080e0f1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7734"             ,	   0x1180080e0f1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7735"             ,	   0x1180080e0f1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7736"             ,	   0x1180080e0f1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7737"             ,	   0x1180080e0f1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7738"             ,	   0x1180080e0f1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7739"             ,	   0x1180080e0f1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7740"             ,	   0x1180080e0f1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7741"             ,	   0x1180080e0f1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7742"             ,	   0x1180080e0f1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7743"             ,	   0x1180080e0f1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7744"             ,	   0x1180080e0f200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7745"             ,	   0x1180080e0f208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7746"             ,	   0x1180080e0f210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7747"             ,	   0x1180080e0f218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7748"             ,	   0x1180080e0f220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7749"             ,	   0x1180080e0f228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7750"             ,	   0x1180080e0f230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7751"             ,	   0x1180080e0f238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7752"             ,	   0x1180080e0f240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7753"             ,	   0x1180080e0f248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7754"             ,	   0x1180080e0f250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7755"             ,	   0x1180080e0f258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7756"             ,	   0x1180080e0f260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7757"             ,	   0x1180080e0f268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7758"             ,	   0x1180080e0f270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7759"             ,	   0x1180080e0f278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7760"             ,	   0x1180080e0f280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7761"             ,	   0x1180080e0f288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7762"             ,	   0x1180080e0f290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7763"             ,	   0x1180080e0f298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7764"             ,	   0x1180080e0f2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7765"             ,	   0x1180080e0f2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7766"             ,	   0x1180080e0f2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7767"             ,	   0x1180080e0f2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7768"             ,	   0x1180080e0f2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7769"             ,	   0x1180080e0f2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7770"             ,	   0x1180080e0f2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7771"             ,	   0x1180080e0f2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7772"             ,	   0x1180080e0f2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7773"             ,	   0x1180080e0f2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7774"             ,	   0x1180080e0f2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7775"             ,	   0x1180080e0f2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7776"             ,	   0x1180080e0f300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7777"             ,	   0x1180080e0f308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7778"             ,	   0x1180080e0f310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7779"             ,	   0x1180080e0f318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7780"             ,	   0x1180080e0f320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7781"             ,	   0x1180080e0f328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7782"             ,	   0x1180080e0f330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7783"             ,	   0x1180080e0f338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7784"             ,	   0x1180080e0f340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7785"             ,	   0x1180080e0f348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7786"             ,	   0x1180080e0f350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7787"             ,	   0x1180080e0f358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7788"             ,	   0x1180080e0f360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7789"             ,	   0x1180080e0f368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7790"             ,	   0x1180080e0f370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7791"             ,	   0x1180080e0f378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7792"             ,	   0x1180080e0f380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7793"             ,	   0x1180080e0f388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7794"             ,	   0x1180080e0f390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7795"             ,	   0x1180080e0f398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7796"             ,	   0x1180080e0f3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7797"             ,	   0x1180080e0f3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7798"             ,	   0x1180080e0f3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7799"             ,	   0x1180080e0f3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7800"             ,	   0x1180080e0f3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7801"             ,	   0x1180080e0f3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7802"             ,	   0x1180080e0f3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7803"             ,	   0x1180080e0f3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7804"             ,	   0x1180080e0f3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7805"             ,	   0x1180080e0f3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7806"             ,	   0x1180080e0f3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7807"             ,	   0x1180080e0f3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7808"             ,	   0x1180080e0f400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7809"             ,	   0x1180080e0f408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7810"             ,	   0x1180080e0f410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7811"             ,	   0x1180080e0f418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7812"             ,	   0x1180080e0f420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7813"             ,	   0x1180080e0f428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7814"             ,	   0x1180080e0f430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7815"             ,	   0x1180080e0f438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7816"             ,	   0x1180080e0f440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7817"             ,	   0x1180080e0f448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7818"             ,	   0x1180080e0f450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7819"             ,	   0x1180080e0f458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7820"             ,	   0x1180080e0f460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7821"             ,	   0x1180080e0f468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7822"             ,	   0x1180080e0f470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7823"             ,	   0x1180080e0f478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7824"             ,	   0x1180080e0f480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7825"             ,	   0x1180080e0f488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7826"             ,	   0x1180080e0f490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7827"             ,	   0x1180080e0f498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7828"             ,	   0x1180080e0f4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7829"             ,	   0x1180080e0f4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7830"             ,	   0x1180080e0f4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7831"             ,	   0x1180080e0f4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7832"             ,	   0x1180080e0f4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7833"             ,	   0x1180080e0f4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7834"             ,	   0x1180080e0f4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7835"             ,	   0x1180080e0f4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7836"             ,	   0x1180080e0f4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7837"             ,	   0x1180080e0f4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7838"             ,	   0x1180080e0f4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7839"             ,	   0x1180080e0f4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7840"             ,	   0x1180080e0f500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7841"             ,	   0x1180080e0f508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7842"             ,	   0x1180080e0f510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7843"             ,	   0x1180080e0f518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7844"             ,	   0x1180080e0f520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7845"             ,	   0x1180080e0f528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7846"             ,	   0x1180080e0f530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7847"             ,	   0x1180080e0f538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7848"             ,	   0x1180080e0f540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7849"             ,	   0x1180080e0f548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7850"             ,	   0x1180080e0f550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7851"             ,	   0x1180080e0f558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7852"             ,	   0x1180080e0f560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7853"             ,	   0x1180080e0f568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7854"             ,	   0x1180080e0f570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7855"             ,	   0x1180080e0f578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7856"             ,	   0x1180080e0f580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7857"             ,	   0x1180080e0f588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7858"             ,	   0x1180080e0f590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7859"             ,	   0x1180080e0f598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7860"             ,	   0x1180080e0f5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7861"             ,	   0x1180080e0f5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7862"             ,	   0x1180080e0f5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7863"             ,	   0x1180080e0f5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7864"             ,	   0x1180080e0f5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7865"             ,	   0x1180080e0f5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7866"             ,	   0x1180080e0f5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7867"             ,	   0x1180080e0f5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7868"             ,	   0x1180080e0f5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7869"             ,	   0x1180080e0f5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7870"             ,	   0x1180080e0f5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7871"             ,	   0x1180080e0f5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7872"             ,	   0x1180080e0f600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7873"             ,	   0x1180080e0f608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7874"             ,	   0x1180080e0f610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7875"             ,	   0x1180080e0f618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7876"             ,	   0x1180080e0f620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7877"             ,	   0x1180080e0f628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7878"             ,	   0x1180080e0f630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7879"             ,	   0x1180080e0f638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7880"             ,	   0x1180080e0f640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7881"             ,	   0x1180080e0f648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7882"             ,	   0x1180080e0f650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7883"             ,	   0x1180080e0f658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7884"             ,	   0x1180080e0f660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7885"             ,	   0x1180080e0f668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7886"             ,	   0x1180080e0f670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7887"             ,	   0x1180080e0f678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7888"             ,	   0x1180080e0f680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7889"             ,	   0x1180080e0f688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7890"             ,	   0x1180080e0f690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7891"             ,	   0x1180080e0f698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7892"             ,	   0x1180080e0f6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7893"             ,	   0x1180080e0f6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7894"             ,	   0x1180080e0f6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7895"             ,	   0x1180080e0f6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7896"             ,	   0x1180080e0f6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7897"             ,	   0x1180080e0f6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7898"             ,	   0x1180080e0f6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7899"             ,	   0x1180080e0f6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7900"             ,	   0x1180080e0f6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7901"             ,	   0x1180080e0f6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7902"             ,	   0x1180080e0f6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7903"             ,	   0x1180080e0f6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7904"             ,	   0x1180080e0f700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7905"             ,	   0x1180080e0f708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7906"             ,	   0x1180080e0f710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7907"             ,	   0x1180080e0f718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7908"             ,	   0x1180080e0f720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7909"             ,	   0x1180080e0f728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7910"             ,	   0x1180080e0f730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7911"             ,	   0x1180080e0f738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7912"             ,	   0x1180080e0f740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7913"             ,	   0x1180080e0f748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7914"             ,	   0x1180080e0f750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7915"             ,	   0x1180080e0f758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7916"             ,	   0x1180080e0f760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7917"             ,	   0x1180080e0f768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7918"             ,	   0x1180080e0f770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7919"             ,	   0x1180080e0f778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7920"             ,	   0x1180080e0f780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7921"             ,	   0x1180080e0f788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7922"             ,	   0x1180080e0f790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7923"             ,	   0x1180080e0f798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7924"             ,	   0x1180080e0f7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7925"             ,	   0x1180080e0f7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7926"             ,	   0x1180080e0f7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7927"             ,	   0x1180080e0f7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7928"             ,	   0x1180080e0f7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7929"             ,	   0x1180080e0f7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7930"             ,	   0x1180080e0f7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7931"             ,	   0x1180080e0f7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7932"             ,	   0x1180080e0f7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7933"             ,	   0x1180080e0f7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7934"             ,	   0x1180080e0f7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7935"             ,	   0x1180080e0f7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7936"             ,	   0x1180080e0f800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7937"             ,	   0x1180080e0f808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7938"             ,	   0x1180080e0f810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7939"             ,	   0x1180080e0f818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7940"             ,	   0x1180080e0f820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7941"             ,	   0x1180080e0f828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7942"             ,	   0x1180080e0f830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7943"             ,	   0x1180080e0f838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7944"             ,	   0x1180080e0f840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7945"             ,	   0x1180080e0f848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7946"             ,	   0x1180080e0f850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7947"             ,	   0x1180080e0f858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7948"             ,	   0x1180080e0f860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7949"             ,	   0x1180080e0f868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7950"             ,	   0x1180080e0f870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7951"             ,	   0x1180080e0f878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7952"             ,	   0x1180080e0f880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7953"             ,	   0x1180080e0f888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7954"             ,	   0x1180080e0f890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7955"             ,	   0x1180080e0f898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7956"             ,	   0x1180080e0f8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7957"             ,	   0x1180080e0f8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7958"             ,	   0x1180080e0f8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7959"             ,	   0x1180080e0f8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7960"             ,	   0x1180080e0f8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7961"             ,	   0x1180080e0f8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7962"             ,	   0x1180080e0f8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7963"             ,	   0x1180080e0f8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7964"             ,	   0x1180080e0f8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7965"             ,	   0x1180080e0f8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7966"             ,	   0x1180080e0f8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7967"             ,	   0x1180080e0f8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7968"             ,	   0x1180080e0f900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7969"             ,	   0x1180080e0f908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7970"             ,	   0x1180080e0f910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7971"             ,	   0x1180080e0f918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7972"             ,	   0x1180080e0f920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7973"             ,	   0x1180080e0f928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7974"             ,	   0x1180080e0f930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7975"             ,	   0x1180080e0f938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7976"             ,	   0x1180080e0f940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7977"             ,	   0x1180080e0f948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7978"             ,	   0x1180080e0f950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7979"             ,	   0x1180080e0f958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7980"             ,	   0x1180080e0f960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7981"             ,	   0x1180080e0f968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7982"             ,	   0x1180080e0f970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7983"             ,	   0x1180080e0f978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7984"             ,	   0x1180080e0f980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7985"             ,	   0x1180080e0f988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7986"             ,	   0x1180080e0f990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7987"             ,	   0x1180080e0f998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7988"             ,	   0x1180080e0f9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7989"             ,	   0x1180080e0f9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7990"             ,	   0x1180080e0f9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7991"             ,	   0x1180080e0f9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7992"             ,	   0x1180080e0f9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7993"             ,	   0x1180080e0f9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7994"             ,	   0x1180080e0f9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7995"             ,	   0x1180080e0f9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7996"             ,	   0x1180080e0f9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7997"             ,	   0x1180080e0f9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7998"             ,	   0x1180080e0f9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP7999"             ,	   0x1180080e0f9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8000"             ,	   0x1180080e0fa00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8001"             ,	   0x1180080e0fa08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8002"             ,	   0x1180080e0fa10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8003"             ,	   0x1180080e0fa18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8004"             ,	   0x1180080e0fa20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8005"             ,	   0x1180080e0fa28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8006"             ,	   0x1180080e0fa30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8007"             ,	   0x1180080e0fa38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8008"             ,	   0x1180080e0fa40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8009"             ,	   0x1180080e0fa48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8010"             ,	   0x1180080e0fa50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8011"             ,	   0x1180080e0fa58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8012"             ,	   0x1180080e0fa60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8013"             ,	   0x1180080e0fa68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8014"             ,	   0x1180080e0fa70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8015"             ,	   0x1180080e0fa78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8016"             ,	   0x1180080e0fa80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8017"             ,	   0x1180080e0fa88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8018"             ,	   0x1180080e0fa90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8019"             ,	   0x1180080e0fa98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8020"             ,	   0x1180080e0faa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8021"             ,	   0x1180080e0faa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8022"             ,	   0x1180080e0fab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8023"             ,	   0x1180080e0fab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8024"             ,	   0x1180080e0fac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8025"             ,	   0x1180080e0fac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8026"             ,	   0x1180080e0fad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8027"             ,	   0x1180080e0fad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8028"             ,	   0x1180080e0fae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8029"             ,	   0x1180080e0fae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8030"             ,	   0x1180080e0faf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8031"             ,	   0x1180080e0faf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8032"             ,	   0x1180080e0fb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8033"             ,	   0x1180080e0fb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8034"             ,	   0x1180080e0fb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8035"             ,	   0x1180080e0fb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8036"             ,	   0x1180080e0fb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8037"             ,	   0x1180080e0fb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8038"             ,	   0x1180080e0fb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8039"             ,	   0x1180080e0fb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8040"             ,	   0x1180080e0fb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8041"             ,	   0x1180080e0fb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8042"             ,	   0x1180080e0fb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8043"             ,	   0x1180080e0fb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8044"             ,	   0x1180080e0fb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8045"             ,	   0x1180080e0fb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8046"             ,	   0x1180080e0fb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8047"             ,	   0x1180080e0fb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8048"             ,	   0x1180080e0fb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8049"             ,	   0x1180080e0fb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8050"             ,	   0x1180080e0fb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8051"             ,	   0x1180080e0fb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8052"             ,	   0x1180080e0fba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8053"             ,	   0x1180080e0fba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8054"             ,	   0x1180080e0fbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8055"             ,	   0x1180080e0fbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8056"             ,	   0x1180080e0fbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8057"             ,	   0x1180080e0fbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8058"             ,	   0x1180080e0fbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8059"             ,	   0x1180080e0fbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8060"             ,	   0x1180080e0fbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8061"             ,	   0x1180080e0fbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8062"             ,	   0x1180080e0fbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8063"             ,	   0x1180080e0fbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8064"             ,	   0x1180080e0fc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8065"             ,	   0x1180080e0fc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8066"             ,	   0x1180080e0fc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8067"             ,	   0x1180080e0fc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8068"             ,	   0x1180080e0fc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8069"             ,	   0x1180080e0fc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8070"             ,	   0x1180080e0fc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8071"             ,	   0x1180080e0fc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8072"             ,	   0x1180080e0fc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8073"             ,	   0x1180080e0fc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8074"             ,	   0x1180080e0fc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8075"             ,	   0x1180080e0fc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8076"             ,	   0x1180080e0fc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8077"             ,	   0x1180080e0fc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8078"             ,	   0x1180080e0fc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8079"             ,	   0x1180080e0fc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8080"             ,	   0x1180080e0fc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8081"             ,	   0x1180080e0fc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8082"             ,	   0x1180080e0fc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8083"             ,	   0x1180080e0fc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8084"             ,	   0x1180080e0fca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8085"             ,	   0x1180080e0fca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8086"             ,	   0x1180080e0fcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8087"             ,	   0x1180080e0fcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8088"             ,	   0x1180080e0fcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8089"             ,	   0x1180080e0fcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8090"             ,	   0x1180080e0fcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8091"             ,	   0x1180080e0fcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8092"             ,	   0x1180080e0fce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8093"             ,	   0x1180080e0fce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8094"             ,	   0x1180080e0fcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8095"             ,	   0x1180080e0fcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8096"             ,	   0x1180080e0fd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8097"             ,	   0x1180080e0fd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8098"             ,	   0x1180080e0fd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8099"             ,	   0x1180080e0fd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8100"             ,	   0x1180080e0fd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8101"             ,	   0x1180080e0fd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8102"             ,	   0x1180080e0fd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8103"             ,	   0x1180080e0fd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8104"             ,	   0x1180080e0fd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8105"             ,	   0x1180080e0fd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8106"             ,	   0x1180080e0fd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8107"             ,	   0x1180080e0fd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8108"             ,	   0x1180080e0fd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8109"             ,	   0x1180080e0fd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8110"             ,	   0x1180080e0fd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8111"             ,	   0x1180080e0fd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8112"             ,	   0x1180080e0fd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8113"             ,	   0x1180080e0fd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8114"             ,	   0x1180080e0fd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8115"             ,	   0x1180080e0fd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8116"             ,	   0x1180080e0fda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8117"             ,	   0x1180080e0fda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8118"             ,	   0x1180080e0fdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8119"             ,	   0x1180080e0fdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8120"             ,	   0x1180080e0fdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8121"             ,	   0x1180080e0fdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8122"             ,	   0x1180080e0fdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8123"             ,	   0x1180080e0fdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8124"             ,	   0x1180080e0fde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8125"             ,	   0x1180080e0fde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8126"             ,	   0x1180080e0fdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8127"             ,	   0x1180080e0fdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8128"             ,	   0x1180080e0fe00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8129"             ,	   0x1180080e0fe08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8130"             ,	   0x1180080e0fe10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8131"             ,	   0x1180080e0fe18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8132"             ,	   0x1180080e0fe20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8133"             ,	   0x1180080e0fe28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8134"             ,	   0x1180080e0fe30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8135"             ,	   0x1180080e0fe38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8136"             ,	   0x1180080e0fe40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8137"             ,	   0x1180080e0fe48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8138"             ,	   0x1180080e0fe50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8139"             ,	   0x1180080e0fe58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8140"             ,	   0x1180080e0fe60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8141"             ,	   0x1180080e0fe68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8142"             ,	   0x1180080e0fe70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8143"             ,	   0x1180080e0fe78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8144"             ,	   0x1180080e0fe80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8145"             ,	   0x1180080e0fe88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8146"             ,	   0x1180080e0fe90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8147"             ,	   0x1180080e0fe98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8148"             ,	   0x1180080e0fea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8149"             ,	   0x1180080e0fea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8150"             ,	   0x1180080e0feb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8151"             ,	   0x1180080e0feb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8152"             ,	   0x1180080e0fec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8153"             ,	   0x1180080e0fec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8154"             ,	   0x1180080e0fed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8155"             ,	   0x1180080e0fed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8156"             ,	   0x1180080e0fee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8157"             ,	   0x1180080e0fee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8158"             ,	   0x1180080e0fef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8159"             ,	   0x1180080e0fef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8160"             ,	   0x1180080e0ff00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8161"             ,	   0x1180080e0ff08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8162"             ,	   0x1180080e0ff10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8163"             ,	   0x1180080e0ff18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8164"             ,	   0x1180080e0ff20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8165"             ,	   0x1180080e0ff28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8166"             ,	   0x1180080e0ff30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8167"             ,	   0x1180080e0ff38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8168"             ,	   0x1180080e0ff40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8169"             ,	   0x1180080e0ff48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8170"             ,	   0x1180080e0ff50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8171"             ,	   0x1180080e0ff58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8172"             ,	   0x1180080e0ff60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8173"             ,	   0x1180080e0ff68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8174"             ,	   0x1180080e0ff70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8175"             ,	   0x1180080e0ff78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8176"             ,	   0x1180080e0ff80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8177"             ,	   0x1180080e0ff88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8178"             ,	   0x1180080e0ff90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8179"             ,	   0x1180080e0ff98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8180"             ,	   0x1180080e0ffa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8181"             ,	   0x1180080e0ffa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8182"             ,	   0x1180080e0ffb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8183"             ,	   0x1180080e0ffb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8184"             ,	   0x1180080e0ffc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8185"             ,	   0x1180080e0ffc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8186"             ,	   0x1180080e0ffd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8187"             ,	   0x1180080e0ffd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8188"             ,	   0x1180080e0ffe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8189"             ,	   0x1180080e0ffe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8190"             ,	   0x1180080e0fff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_DUT_MAP8191"             ,	   0x1180080e0fff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_ERR_TDT0"                ,	   0x1180080a007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	608},
+	{"L2C_ERR_TDT1"                ,	   0x1180080a407e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	608},
+	{"L2C_ERR_TDT2"                ,	   0x1180080a807e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	608},
+	{"L2C_ERR_TDT3"                ,	   0x1180080ac07e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	608},
+	{"L2C_ERR_TTG0"                ,	   0x1180080a007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	609},
+	{"L2C_ERR_TTG1"                ,	   0x1180080a407e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	609},
+	{"L2C_ERR_TTG2"                ,	   0x1180080a807e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	609},
+	{"L2C_ERR_TTG3"                ,	   0x1180080ac07e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	609},
+	{"L2C_ERR_VBF0"                ,	   0x1180080c007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	610},
+	{"L2C_ERR_VBF1"                ,	   0x1180080c407f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	610},
+	{"L2C_ERR_VBF2"                ,	   0x1180080c807f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	610},
+	{"L2C_ERR_VBF3"                ,	   0x1180080cc07f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	610},
+	{"L2C_ERR_XMC"                 ,	   0x11800808007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_INT_ENA"                 ,	   0x1180080800020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	612},
+	{"L2C_INT_REG"                 ,	   0x1180080800018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_IOC0_PFC"                ,	   0x1180080800420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	614},
+	{"L2C_IOR0_PFC"                ,	   0x1180080800428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	615},
+	{"L2C_QOS_IOB0"                ,	   0x1180080880200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"L2C_QOS_IOB1"                ,	   0x1180080880208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"L2C_QOS_PP0"                 ,	   0x1180080880000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP1"                 ,	   0x1180080880008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP2"                 ,	   0x1180080880010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP3"                 ,	   0x1180080880018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP4"                 ,	   0x1180080880020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP5"                 ,	   0x1180080880028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP6"                 ,	   0x1180080880030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP7"                 ,	   0x1180080880038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP8"                 ,	   0x1180080880040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP9"                 ,	   0x1180080880048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP10"                ,	   0x1180080880050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP11"                ,	   0x1180080880058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP12"                ,	   0x1180080880060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP13"                ,	   0x1180080880068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP14"                ,	   0x1180080880070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP15"                ,	   0x1180080880078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP16"                ,	   0x1180080880080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP17"                ,	   0x1180080880088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP18"                ,	   0x1180080880090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP19"                ,	   0x1180080880098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP20"                ,	   0x11800808800a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP21"                ,	   0x11800808800a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP22"                ,	   0x11800808800b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP23"                ,	   0x11800808800b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP24"                ,	   0x11800808800c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP25"                ,	   0x11800808800c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP26"                ,	   0x11800808800d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP27"                ,	   0x11800808800d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP28"                ,	   0x11800808800e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP29"                ,	   0x11800808800e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP30"                ,	   0x11800808800f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_PP31"                ,	   0x11800808800f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_QOS_WGT"                 ,	   0x1180080800008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
+	{"L2C_RSC0_PFC"                ,	   0x1180080800410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"L2C_RSC1_PFC"                ,	   0x1180080800450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"L2C_RSC2_PFC"                ,	   0x1180080800490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"L2C_RSC3_PFC"                ,	   0x11800808004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"L2C_RSD0_PFC"                ,	   0x1180080800418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"L2C_RSD1_PFC"                ,	   0x1180080800458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"L2C_RSD2_PFC"                ,	   0x1180080800498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"L2C_RSD3_PFC"                ,	   0x11800808004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"L2C_TAD0_ECC0"               ,	   0x1180080a00018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"L2C_TAD1_ECC0"               ,	   0x1180080a40018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"L2C_TAD2_ECC0"               ,	   0x1180080a80018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"L2C_TAD3_ECC0"               ,	   0x1180080ac0018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"L2C_TAD0_ECC1"               ,	   0x1180080a00020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"L2C_TAD1_ECC1"               ,	   0x1180080a40020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"L2C_TAD2_ECC1"               ,	   0x1180080a80020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"L2C_TAD3_ECC1"               ,	   0x1180080ac0020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"L2C_TAD0_IEN"                ,	   0x1180080a00000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_TAD1_IEN"                ,	   0x1180080a40000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_TAD2_IEN"                ,	   0x1180080a80000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_TAD3_IEN"                ,	   0x1180080ac0000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_TAD0_INT"                ,	   0x1180080a00028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"L2C_TAD1_INT"                ,	   0x1180080a40028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"L2C_TAD2_INT"                ,	   0x1180080a80028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"L2C_TAD3_INT"                ,	   0x1180080ac0028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"L2C_TAD0_PFC0"               ,	   0x1180080a00400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"L2C_TAD1_PFC0"               ,	   0x1180080a40400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"L2C_TAD2_PFC0"               ,	   0x1180080a80400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"L2C_TAD3_PFC0"               ,	   0x1180080ac0400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"L2C_TAD0_PFC1"               ,	   0x1180080a00408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"L2C_TAD1_PFC1"               ,	   0x1180080a40408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"L2C_TAD2_PFC1"               ,	   0x1180080a80408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"L2C_TAD3_PFC1"               ,	   0x1180080ac0408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"L2C_TAD0_PFC2"               ,	   0x1180080a00410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"L2C_TAD1_PFC2"               ,	   0x1180080a40410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"L2C_TAD2_PFC2"               ,	   0x1180080a80410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"L2C_TAD3_PFC2"               ,	   0x1180080ac0410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"L2C_TAD0_PFC3"               ,	   0x1180080a00418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"L2C_TAD1_PFC3"               ,	   0x1180080a40418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"L2C_TAD2_PFC3"               ,	   0x1180080a80418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"L2C_TAD3_PFC3"               ,	   0x1180080ac0418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"L2C_TAD0_PRF"                ,	   0x1180080a00008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"L2C_TAD1_PRF"                ,	   0x1180080a40008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"L2C_TAD2_PRF"                ,	   0x1180080a80008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"L2C_TAD3_PRF"                ,	   0x1180080ac0008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"L2C_TAD0_TAG"                ,	   0x1180080a00010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"L2C_TAD1_TAG"                ,	   0x1180080a40010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"L2C_TAD2_TAG"                ,	   0x1180080a80010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"L2C_TAD3_TAG"                ,	   0x1180080ac0010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"L2C_VER_ID"                  ,	   0x11800808007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"L2C_VER_IOB"                 ,	   0x11800808007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"L2C_VER_MSC"                 ,	   0x11800808007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
+	{"L2C_VER_PP"                  ,	   0x11800808007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
+	{"L2C_VIRTID_IOB0"             ,	   0x11800808c0200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"L2C_VIRTID_IOB1"             ,	   0x11800808c0208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"L2C_VIRTID_PP0"              ,	   0x11800808c0000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP1"              ,	   0x11800808c0008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP2"              ,	   0x11800808c0010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP3"              ,	   0x11800808c0018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP4"              ,	   0x11800808c0020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP5"              ,	   0x11800808c0028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP6"              ,	   0x11800808c0030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP7"              ,	   0x11800808c0038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP8"              ,	   0x11800808c0040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP9"              ,	   0x11800808c0048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP10"             ,	   0x11800808c0050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP11"             ,	   0x11800808c0058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP12"             ,	   0x11800808c0060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP13"             ,	   0x11800808c0068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP14"             ,	   0x11800808c0070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP15"             ,	   0x11800808c0078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP16"             ,	   0x11800808c0080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP17"             ,	   0x11800808c0088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP18"             ,	   0x11800808c0090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP19"             ,	   0x11800808c0098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP20"             ,	   0x11800808c00a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP21"             ,	   0x11800808c00a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP22"             ,	   0x11800808c00b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP23"             ,	   0x11800808c00b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP24"             ,	   0x11800808c00c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP25"             ,	   0x11800808c00c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP26"             ,	   0x11800808c00d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP27"             ,	   0x11800808c00d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP28"             ,	   0x11800808c00e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP29"             ,	   0x11800808c00e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP30"             ,	   0x11800808c00f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VIRTID_PP31"             ,	   0x11800808c00f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VRT_CTL"                 ,	   0x1180080800010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
+	{"L2C_VRT_MEM0"                ,	   0x1180080900000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1"                ,	   0x1180080900008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM2"                ,	   0x1180080900010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM3"                ,	   0x1180080900018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM4"                ,	   0x1180080900020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM5"                ,	   0x1180080900028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM6"                ,	   0x1180080900030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM7"                ,	   0x1180080900038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM8"                ,	   0x1180080900040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM9"                ,	   0x1180080900048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM10"               ,	   0x1180080900050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM11"               ,	   0x1180080900058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM12"               ,	   0x1180080900060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM13"               ,	   0x1180080900068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM14"               ,	   0x1180080900070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM15"               ,	   0x1180080900078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM16"               ,	   0x1180080900080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM17"               ,	   0x1180080900088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM18"               ,	   0x1180080900090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM19"               ,	   0x1180080900098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM20"               ,	   0x11800809000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM21"               ,	   0x11800809000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM22"               ,	   0x11800809000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM23"               ,	   0x11800809000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM24"               ,	   0x11800809000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM25"               ,	   0x11800809000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM26"               ,	   0x11800809000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM27"               ,	   0x11800809000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM28"               ,	   0x11800809000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM29"               ,	   0x11800809000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM30"               ,	   0x11800809000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM31"               ,	   0x11800809000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM32"               ,	   0x1180080900100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM33"               ,	   0x1180080900108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM34"               ,	   0x1180080900110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM35"               ,	   0x1180080900118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM36"               ,	   0x1180080900120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM37"               ,	   0x1180080900128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM38"               ,	   0x1180080900130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM39"               ,	   0x1180080900138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM40"               ,	   0x1180080900140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM41"               ,	   0x1180080900148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM42"               ,	   0x1180080900150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM43"               ,	   0x1180080900158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM44"               ,	   0x1180080900160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM45"               ,	   0x1180080900168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM46"               ,	   0x1180080900170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM47"               ,	   0x1180080900178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM48"               ,	   0x1180080900180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM49"               ,	   0x1180080900188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM50"               ,	   0x1180080900190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM51"               ,	   0x1180080900198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM52"               ,	   0x11800809001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM53"               ,	   0x11800809001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM54"               ,	   0x11800809001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM55"               ,	   0x11800809001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM56"               ,	   0x11800809001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM57"               ,	   0x11800809001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM58"               ,	   0x11800809001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM59"               ,	   0x11800809001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM60"               ,	   0x11800809001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM61"               ,	   0x11800809001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM62"               ,	   0x11800809001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM63"               ,	   0x11800809001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM64"               ,	   0x1180080900200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM65"               ,	   0x1180080900208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM66"               ,	   0x1180080900210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM67"               ,	   0x1180080900218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM68"               ,	   0x1180080900220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM69"               ,	   0x1180080900228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM70"               ,	   0x1180080900230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM71"               ,	   0x1180080900238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM72"               ,	   0x1180080900240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM73"               ,	   0x1180080900248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM74"               ,	   0x1180080900250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM75"               ,	   0x1180080900258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM76"               ,	   0x1180080900260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM77"               ,	   0x1180080900268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM78"               ,	   0x1180080900270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM79"               ,	   0x1180080900278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM80"               ,	   0x1180080900280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM81"               ,	   0x1180080900288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM82"               ,	   0x1180080900290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM83"               ,	   0x1180080900298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM84"               ,	   0x11800809002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM85"               ,	   0x11800809002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM86"               ,	   0x11800809002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM87"               ,	   0x11800809002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM88"               ,	   0x11800809002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM89"               ,	   0x11800809002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM90"               ,	   0x11800809002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM91"               ,	   0x11800809002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM92"               ,	   0x11800809002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM93"               ,	   0x11800809002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM94"               ,	   0x11800809002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM95"               ,	   0x11800809002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM96"               ,	   0x1180080900300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM97"               ,	   0x1180080900308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM98"               ,	   0x1180080900310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM99"               ,	   0x1180080900318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM100"              ,	   0x1180080900320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM101"              ,	   0x1180080900328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM102"              ,	   0x1180080900330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM103"              ,	   0x1180080900338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM104"              ,	   0x1180080900340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM105"              ,	   0x1180080900348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM106"              ,	   0x1180080900350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM107"              ,	   0x1180080900358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM108"              ,	   0x1180080900360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM109"              ,	   0x1180080900368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM110"              ,	   0x1180080900370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM111"              ,	   0x1180080900378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM112"              ,	   0x1180080900380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM113"              ,	   0x1180080900388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM114"              ,	   0x1180080900390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM115"              ,	   0x1180080900398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM116"              ,	   0x11800809003a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM117"              ,	   0x11800809003a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM118"              ,	   0x11800809003b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM119"              ,	   0x11800809003b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM120"              ,	   0x11800809003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM121"              ,	   0x11800809003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM122"              ,	   0x11800809003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM123"              ,	   0x11800809003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM124"              ,	   0x11800809003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM125"              ,	   0x11800809003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM126"              ,	   0x11800809003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM127"              ,	   0x11800809003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM128"              ,	   0x1180080900400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM129"              ,	   0x1180080900408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM130"              ,	   0x1180080900410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM131"              ,	   0x1180080900418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM132"              ,	   0x1180080900420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM133"              ,	   0x1180080900428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM134"              ,	   0x1180080900430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM135"              ,	   0x1180080900438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM136"              ,	   0x1180080900440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM137"              ,	   0x1180080900448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM138"              ,	   0x1180080900450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM139"              ,	   0x1180080900458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM140"              ,	   0x1180080900460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM141"              ,	   0x1180080900468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM142"              ,	   0x1180080900470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM143"              ,	   0x1180080900478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM144"              ,	   0x1180080900480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM145"              ,	   0x1180080900488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM146"              ,	   0x1180080900490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM147"              ,	   0x1180080900498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM148"              ,	   0x11800809004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM149"              ,	   0x11800809004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM150"              ,	   0x11800809004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM151"              ,	   0x11800809004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM152"              ,	   0x11800809004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM153"              ,	   0x11800809004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM154"              ,	   0x11800809004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM155"              ,	   0x11800809004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM156"              ,	   0x11800809004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM157"              ,	   0x11800809004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM158"              ,	   0x11800809004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM159"              ,	   0x11800809004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM160"              ,	   0x1180080900500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM161"              ,	   0x1180080900508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM162"              ,	   0x1180080900510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM163"              ,	   0x1180080900518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM164"              ,	   0x1180080900520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM165"              ,	   0x1180080900528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM166"              ,	   0x1180080900530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM167"              ,	   0x1180080900538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM168"              ,	   0x1180080900540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM169"              ,	   0x1180080900548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM170"              ,	   0x1180080900550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM171"              ,	   0x1180080900558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM172"              ,	   0x1180080900560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM173"              ,	   0x1180080900568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM174"              ,	   0x1180080900570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM175"              ,	   0x1180080900578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM176"              ,	   0x1180080900580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM177"              ,	   0x1180080900588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM178"              ,	   0x1180080900590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM179"              ,	   0x1180080900598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM180"              ,	   0x11800809005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM181"              ,	   0x11800809005a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM182"              ,	   0x11800809005b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM183"              ,	   0x11800809005b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM184"              ,	   0x11800809005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM185"              ,	   0x11800809005c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM186"              ,	   0x11800809005d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM187"              ,	   0x11800809005d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM188"              ,	   0x11800809005e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM189"              ,	   0x11800809005e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM190"              ,	   0x11800809005f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM191"              ,	   0x11800809005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM192"              ,	   0x1180080900600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM193"              ,	   0x1180080900608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM194"              ,	   0x1180080900610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM195"              ,	   0x1180080900618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM196"              ,	   0x1180080900620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM197"              ,	   0x1180080900628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM198"              ,	   0x1180080900630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM199"              ,	   0x1180080900638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM200"              ,	   0x1180080900640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM201"              ,	   0x1180080900648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM202"              ,	   0x1180080900650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM203"              ,	   0x1180080900658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM204"              ,	   0x1180080900660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM205"              ,	   0x1180080900668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM206"              ,	   0x1180080900670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM207"              ,	   0x1180080900678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM208"              ,	   0x1180080900680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM209"              ,	   0x1180080900688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM210"              ,	   0x1180080900690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM211"              ,	   0x1180080900698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM212"              ,	   0x11800809006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM213"              ,	   0x11800809006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM214"              ,	   0x11800809006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM215"              ,	   0x11800809006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM216"              ,	   0x11800809006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM217"              ,	   0x11800809006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM218"              ,	   0x11800809006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM219"              ,	   0x11800809006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM220"              ,	   0x11800809006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM221"              ,	   0x11800809006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM222"              ,	   0x11800809006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM223"              ,	   0x11800809006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM224"              ,	   0x1180080900700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM225"              ,	   0x1180080900708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM226"              ,	   0x1180080900710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM227"              ,	   0x1180080900718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM228"              ,	   0x1180080900720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM229"              ,	   0x1180080900728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM230"              ,	   0x1180080900730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM231"              ,	   0x1180080900738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM232"              ,	   0x1180080900740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM233"              ,	   0x1180080900748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM234"              ,	   0x1180080900750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM235"              ,	   0x1180080900758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM236"              ,	   0x1180080900760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM237"              ,	   0x1180080900768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM238"              ,	   0x1180080900770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM239"              ,	   0x1180080900778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM240"              ,	   0x1180080900780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM241"              ,	   0x1180080900788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM242"              ,	   0x1180080900790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM243"              ,	   0x1180080900798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM244"              ,	   0x11800809007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM245"              ,	   0x11800809007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM246"              ,	   0x11800809007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM247"              ,	   0x11800809007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM248"              ,	   0x11800809007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM249"              ,	   0x11800809007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM250"              ,	   0x11800809007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM251"              ,	   0x11800809007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM252"              ,	   0x11800809007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM253"              ,	   0x11800809007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM254"              ,	   0x11800809007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM255"              ,	   0x11800809007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM256"              ,	   0x1180080900800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM257"              ,	   0x1180080900808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM258"              ,	   0x1180080900810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM259"              ,	   0x1180080900818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM260"              ,	   0x1180080900820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM261"              ,	   0x1180080900828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM262"              ,	   0x1180080900830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM263"              ,	   0x1180080900838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM264"              ,	   0x1180080900840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM265"              ,	   0x1180080900848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM266"              ,	   0x1180080900850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM267"              ,	   0x1180080900858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM268"              ,	   0x1180080900860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM269"              ,	   0x1180080900868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM270"              ,	   0x1180080900870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM271"              ,	   0x1180080900878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM272"              ,	   0x1180080900880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM273"              ,	   0x1180080900888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM274"              ,	   0x1180080900890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM275"              ,	   0x1180080900898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM276"              ,	   0x11800809008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM277"              ,	   0x11800809008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM278"              ,	   0x11800809008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM279"              ,	   0x11800809008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM280"              ,	   0x11800809008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM281"              ,	   0x11800809008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM282"              ,	   0x11800809008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM283"              ,	   0x11800809008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM284"              ,	   0x11800809008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM285"              ,	   0x11800809008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM286"              ,	   0x11800809008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM287"              ,	   0x11800809008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM288"              ,	   0x1180080900900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM289"              ,	   0x1180080900908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM290"              ,	   0x1180080900910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM291"              ,	   0x1180080900918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM292"              ,	   0x1180080900920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM293"              ,	   0x1180080900928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM294"              ,	   0x1180080900930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM295"              ,	   0x1180080900938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM296"              ,	   0x1180080900940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM297"              ,	   0x1180080900948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM298"              ,	   0x1180080900950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM299"              ,	   0x1180080900958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM300"              ,	   0x1180080900960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM301"              ,	   0x1180080900968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM302"              ,	   0x1180080900970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM303"              ,	   0x1180080900978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM304"              ,	   0x1180080900980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM305"              ,	   0x1180080900988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM306"              ,	   0x1180080900990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM307"              ,	   0x1180080900998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM308"              ,	   0x11800809009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM309"              ,	   0x11800809009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM310"              ,	   0x11800809009b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM311"              ,	   0x11800809009b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM312"              ,	   0x11800809009c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM313"              ,	   0x11800809009c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM314"              ,	   0x11800809009d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM315"              ,	   0x11800809009d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM316"              ,	   0x11800809009e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM317"              ,	   0x11800809009e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM318"              ,	   0x11800809009f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM319"              ,	   0x11800809009f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM320"              ,	   0x1180080900a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM321"              ,	   0x1180080900a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM322"              ,	   0x1180080900a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM323"              ,	   0x1180080900a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM324"              ,	   0x1180080900a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM325"              ,	   0x1180080900a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM326"              ,	   0x1180080900a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM327"              ,	   0x1180080900a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM328"              ,	   0x1180080900a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM329"              ,	   0x1180080900a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM330"              ,	   0x1180080900a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM331"              ,	   0x1180080900a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM332"              ,	   0x1180080900a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM333"              ,	   0x1180080900a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM334"              ,	   0x1180080900a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM335"              ,	   0x1180080900a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM336"              ,	   0x1180080900a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM337"              ,	   0x1180080900a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM338"              ,	   0x1180080900a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM339"              ,	   0x1180080900a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM340"              ,	   0x1180080900aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM341"              ,	   0x1180080900aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM342"              ,	   0x1180080900ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM343"              ,	   0x1180080900ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM344"              ,	   0x1180080900ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM345"              ,	   0x1180080900ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM346"              ,	   0x1180080900ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM347"              ,	   0x1180080900ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM348"              ,	   0x1180080900ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM349"              ,	   0x1180080900ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM350"              ,	   0x1180080900af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM351"              ,	   0x1180080900af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM352"              ,	   0x1180080900b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM353"              ,	   0x1180080900b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM354"              ,	   0x1180080900b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM355"              ,	   0x1180080900b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM356"              ,	   0x1180080900b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM357"              ,	   0x1180080900b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM358"              ,	   0x1180080900b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM359"              ,	   0x1180080900b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM360"              ,	   0x1180080900b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM361"              ,	   0x1180080900b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM362"              ,	   0x1180080900b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM363"              ,	   0x1180080900b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM364"              ,	   0x1180080900b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM365"              ,	   0x1180080900b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM366"              ,	   0x1180080900b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM367"              ,	   0x1180080900b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM368"              ,	   0x1180080900b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM369"              ,	   0x1180080900b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM370"              ,	   0x1180080900b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM371"              ,	   0x1180080900b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM372"              ,	   0x1180080900ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM373"              ,	   0x1180080900ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM374"              ,	   0x1180080900bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM375"              ,	   0x1180080900bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM376"              ,	   0x1180080900bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM377"              ,	   0x1180080900bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM378"              ,	   0x1180080900bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM379"              ,	   0x1180080900bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM380"              ,	   0x1180080900be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM381"              ,	   0x1180080900be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM382"              ,	   0x1180080900bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM383"              ,	   0x1180080900bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM384"              ,	   0x1180080900c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM385"              ,	   0x1180080900c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM386"              ,	   0x1180080900c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM387"              ,	   0x1180080900c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM388"              ,	   0x1180080900c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM389"              ,	   0x1180080900c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM390"              ,	   0x1180080900c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM391"              ,	   0x1180080900c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM392"              ,	   0x1180080900c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM393"              ,	   0x1180080900c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM394"              ,	   0x1180080900c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM395"              ,	   0x1180080900c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM396"              ,	   0x1180080900c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM397"              ,	   0x1180080900c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM398"              ,	   0x1180080900c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM399"              ,	   0x1180080900c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM400"              ,	   0x1180080900c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM401"              ,	   0x1180080900c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM402"              ,	   0x1180080900c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM403"              ,	   0x1180080900c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM404"              ,	   0x1180080900ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM405"              ,	   0x1180080900ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM406"              ,	   0x1180080900cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM407"              ,	   0x1180080900cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM408"              ,	   0x1180080900cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM409"              ,	   0x1180080900cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM410"              ,	   0x1180080900cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM411"              ,	   0x1180080900cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM412"              ,	   0x1180080900ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM413"              ,	   0x1180080900ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM414"              ,	   0x1180080900cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM415"              ,	   0x1180080900cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM416"              ,	   0x1180080900d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM417"              ,	   0x1180080900d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM418"              ,	   0x1180080900d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM419"              ,	   0x1180080900d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM420"              ,	   0x1180080900d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM421"              ,	   0x1180080900d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM422"              ,	   0x1180080900d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM423"              ,	   0x1180080900d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM424"              ,	   0x1180080900d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM425"              ,	   0x1180080900d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM426"              ,	   0x1180080900d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM427"              ,	   0x1180080900d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM428"              ,	   0x1180080900d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM429"              ,	   0x1180080900d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM430"              ,	   0x1180080900d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM431"              ,	   0x1180080900d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM432"              ,	   0x1180080900d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM433"              ,	   0x1180080900d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM434"              ,	   0x1180080900d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM435"              ,	   0x1180080900d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM436"              ,	   0x1180080900da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM437"              ,	   0x1180080900da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM438"              ,	   0x1180080900db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM439"              ,	   0x1180080900db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM440"              ,	   0x1180080900dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM441"              ,	   0x1180080900dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM442"              ,	   0x1180080900dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM443"              ,	   0x1180080900dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM444"              ,	   0x1180080900de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM445"              ,	   0x1180080900de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM446"              ,	   0x1180080900df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM447"              ,	   0x1180080900df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM448"              ,	   0x1180080900e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM449"              ,	   0x1180080900e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM450"              ,	   0x1180080900e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM451"              ,	   0x1180080900e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM452"              ,	   0x1180080900e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM453"              ,	   0x1180080900e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM454"              ,	   0x1180080900e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM455"              ,	   0x1180080900e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM456"              ,	   0x1180080900e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM457"              ,	   0x1180080900e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM458"              ,	   0x1180080900e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM459"              ,	   0x1180080900e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM460"              ,	   0x1180080900e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM461"              ,	   0x1180080900e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM462"              ,	   0x1180080900e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM463"              ,	   0x1180080900e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM464"              ,	   0x1180080900e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM465"              ,	   0x1180080900e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM466"              ,	   0x1180080900e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM467"              ,	   0x1180080900e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM468"              ,	   0x1180080900ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM469"              ,	   0x1180080900ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM470"              ,	   0x1180080900eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM471"              ,	   0x1180080900eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM472"              ,	   0x1180080900ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM473"              ,	   0x1180080900ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM474"              ,	   0x1180080900ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM475"              ,	   0x1180080900ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM476"              ,	   0x1180080900ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM477"              ,	   0x1180080900ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM478"              ,	   0x1180080900ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM479"              ,	   0x1180080900ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM480"              ,	   0x1180080900f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM481"              ,	   0x1180080900f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM482"              ,	   0x1180080900f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM483"              ,	   0x1180080900f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM484"              ,	   0x1180080900f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM485"              ,	   0x1180080900f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM486"              ,	   0x1180080900f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM487"              ,	   0x1180080900f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM488"              ,	   0x1180080900f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM489"              ,	   0x1180080900f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM490"              ,	   0x1180080900f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM491"              ,	   0x1180080900f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM492"              ,	   0x1180080900f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM493"              ,	   0x1180080900f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM494"              ,	   0x1180080900f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM495"              ,	   0x1180080900f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM496"              ,	   0x1180080900f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM497"              ,	   0x1180080900f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM498"              ,	   0x1180080900f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM499"              ,	   0x1180080900f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM500"              ,	   0x1180080900fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM501"              ,	   0x1180080900fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM502"              ,	   0x1180080900fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM503"              ,	   0x1180080900fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM504"              ,	   0x1180080900fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM505"              ,	   0x1180080900fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM506"              ,	   0x1180080900fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM507"              ,	   0x1180080900fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM508"              ,	   0x1180080900fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM509"              ,	   0x1180080900fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM510"              ,	   0x1180080900ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM511"              ,	   0x1180080900ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM512"              ,	   0x1180080901000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM513"              ,	   0x1180080901008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM514"              ,	   0x1180080901010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM515"              ,	   0x1180080901018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM516"              ,	   0x1180080901020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM517"              ,	   0x1180080901028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM518"              ,	   0x1180080901030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM519"              ,	   0x1180080901038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM520"              ,	   0x1180080901040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM521"              ,	   0x1180080901048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM522"              ,	   0x1180080901050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM523"              ,	   0x1180080901058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM524"              ,	   0x1180080901060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM525"              ,	   0x1180080901068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM526"              ,	   0x1180080901070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM527"              ,	   0x1180080901078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM528"              ,	   0x1180080901080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM529"              ,	   0x1180080901088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM530"              ,	   0x1180080901090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM531"              ,	   0x1180080901098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM532"              ,	   0x11800809010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM533"              ,	   0x11800809010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM534"              ,	   0x11800809010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM535"              ,	   0x11800809010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM536"              ,	   0x11800809010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM537"              ,	   0x11800809010c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM538"              ,	   0x11800809010d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM539"              ,	   0x11800809010d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM540"              ,	   0x11800809010e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM541"              ,	   0x11800809010e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM542"              ,	   0x11800809010f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM543"              ,	   0x11800809010f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM544"              ,	   0x1180080901100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM545"              ,	   0x1180080901108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM546"              ,	   0x1180080901110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM547"              ,	   0x1180080901118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM548"              ,	   0x1180080901120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM549"              ,	   0x1180080901128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM550"              ,	   0x1180080901130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM551"              ,	   0x1180080901138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM552"              ,	   0x1180080901140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM553"              ,	   0x1180080901148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM554"              ,	   0x1180080901150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM555"              ,	   0x1180080901158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM556"              ,	   0x1180080901160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM557"              ,	   0x1180080901168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM558"              ,	   0x1180080901170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM559"              ,	   0x1180080901178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM560"              ,	   0x1180080901180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM561"              ,	   0x1180080901188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM562"              ,	   0x1180080901190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM563"              ,	   0x1180080901198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM564"              ,	   0x11800809011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM565"              ,	   0x11800809011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM566"              ,	   0x11800809011b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM567"              ,	   0x11800809011b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM568"              ,	   0x11800809011c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM569"              ,	   0x11800809011c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM570"              ,	   0x11800809011d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM571"              ,	   0x11800809011d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM572"              ,	   0x11800809011e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM573"              ,	   0x11800809011e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM574"              ,	   0x11800809011f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM575"              ,	   0x11800809011f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM576"              ,	   0x1180080901200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM577"              ,	   0x1180080901208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM578"              ,	   0x1180080901210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM579"              ,	   0x1180080901218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM580"              ,	   0x1180080901220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM581"              ,	   0x1180080901228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM582"              ,	   0x1180080901230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM583"              ,	   0x1180080901238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM584"              ,	   0x1180080901240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM585"              ,	   0x1180080901248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM586"              ,	   0x1180080901250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM587"              ,	   0x1180080901258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM588"              ,	   0x1180080901260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM589"              ,	   0x1180080901268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM590"              ,	   0x1180080901270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM591"              ,	   0x1180080901278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM592"              ,	   0x1180080901280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM593"              ,	   0x1180080901288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM594"              ,	   0x1180080901290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM595"              ,	   0x1180080901298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM596"              ,	   0x11800809012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM597"              ,	   0x11800809012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM598"              ,	   0x11800809012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM599"              ,	   0x11800809012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM600"              ,	   0x11800809012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM601"              ,	   0x11800809012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM602"              ,	   0x11800809012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM603"              ,	   0x11800809012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM604"              ,	   0x11800809012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM605"              ,	   0x11800809012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM606"              ,	   0x11800809012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM607"              ,	   0x11800809012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM608"              ,	   0x1180080901300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM609"              ,	   0x1180080901308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM610"              ,	   0x1180080901310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM611"              ,	   0x1180080901318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM612"              ,	   0x1180080901320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM613"              ,	   0x1180080901328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM614"              ,	   0x1180080901330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM615"              ,	   0x1180080901338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM616"              ,	   0x1180080901340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM617"              ,	   0x1180080901348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM618"              ,	   0x1180080901350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM619"              ,	   0x1180080901358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM620"              ,	   0x1180080901360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM621"              ,	   0x1180080901368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM622"              ,	   0x1180080901370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM623"              ,	   0x1180080901378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM624"              ,	   0x1180080901380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM625"              ,	   0x1180080901388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM626"              ,	   0x1180080901390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM627"              ,	   0x1180080901398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM628"              ,	   0x11800809013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM629"              ,	   0x11800809013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM630"              ,	   0x11800809013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM631"              ,	   0x11800809013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM632"              ,	   0x11800809013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM633"              ,	   0x11800809013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM634"              ,	   0x11800809013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM635"              ,	   0x11800809013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM636"              ,	   0x11800809013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM637"              ,	   0x11800809013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM638"              ,	   0x11800809013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM639"              ,	   0x11800809013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM640"              ,	   0x1180080901400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM641"              ,	   0x1180080901408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM642"              ,	   0x1180080901410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM643"              ,	   0x1180080901418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM644"              ,	   0x1180080901420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM645"              ,	   0x1180080901428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM646"              ,	   0x1180080901430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM647"              ,	   0x1180080901438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM648"              ,	   0x1180080901440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM649"              ,	   0x1180080901448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM650"              ,	   0x1180080901450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM651"              ,	   0x1180080901458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM652"              ,	   0x1180080901460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM653"              ,	   0x1180080901468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM654"              ,	   0x1180080901470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM655"              ,	   0x1180080901478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM656"              ,	   0x1180080901480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM657"              ,	   0x1180080901488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM658"              ,	   0x1180080901490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM659"              ,	   0x1180080901498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM660"              ,	   0x11800809014a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM661"              ,	   0x11800809014a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM662"              ,	   0x11800809014b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM663"              ,	   0x11800809014b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM664"              ,	   0x11800809014c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM665"              ,	   0x11800809014c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM666"              ,	   0x11800809014d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM667"              ,	   0x11800809014d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM668"              ,	   0x11800809014e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM669"              ,	   0x11800809014e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM670"              ,	   0x11800809014f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM671"              ,	   0x11800809014f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM672"              ,	   0x1180080901500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM673"              ,	   0x1180080901508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM674"              ,	   0x1180080901510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM675"              ,	   0x1180080901518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM676"              ,	   0x1180080901520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM677"              ,	   0x1180080901528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM678"              ,	   0x1180080901530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM679"              ,	   0x1180080901538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM680"              ,	   0x1180080901540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM681"              ,	   0x1180080901548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM682"              ,	   0x1180080901550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM683"              ,	   0x1180080901558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM684"              ,	   0x1180080901560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM685"              ,	   0x1180080901568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM686"              ,	   0x1180080901570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM687"              ,	   0x1180080901578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM688"              ,	   0x1180080901580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM689"              ,	   0x1180080901588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM690"              ,	   0x1180080901590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM691"              ,	   0x1180080901598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM692"              ,	   0x11800809015a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM693"              ,	   0x11800809015a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM694"              ,	   0x11800809015b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM695"              ,	   0x11800809015b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM696"              ,	   0x11800809015c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM697"              ,	   0x11800809015c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM698"              ,	   0x11800809015d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM699"              ,	   0x11800809015d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM700"              ,	   0x11800809015e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM701"              ,	   0x11800809015e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM702"              ,	   0x11800809015f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM703"              ,	   0x11800809015f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM704"              ,	   0x1180080901600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM705"              ,	   0x1180080901608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM706"              ,	   0x1180080901610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM707"              ,	   0x1180080901618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM708"              ,	   0x1180080901620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM709"              ,	   0x1180080901628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM710"              ,	   0x1180080901630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM711"              ,	   0x1180080901638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM712"              ,	   0x1180080901640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM713"              ,	   0x1180080901648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM714"              ,	   0x1180080901650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM715"              ,	   0x1180080901658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM716"              ,	   0x1180080901660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM717"              ,	   0x1180080901668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM718"              ,	   0x1180080901670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM719"              ,	   0x1180080901678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM720"              ,	   0x1180080901680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM721"              ,	   0x1180080901688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM722"              ,	   0x1180080901690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM723"              ,	   0x1180080901698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM724"              ,	   0x11800809016a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM725"              ,	   0x11800809016a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM726"              ,	   0x11800809016b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM727"              ,	   0x11800809016b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM728"              ,	   0x11800809016c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM729"              ,	   0x11800809016c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM730"              ,	   0x11800809016d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM731"              ,	   0x11800809016d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM732"              ,	   0x11800809016e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM733"              ,	   0x11800809016e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM734"              ,	   0x11800809016f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM735"              ,	   0x11800809016f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM736"              ,	   0x1180080901700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM737"              ,	   0x1180080901708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM738"              ,	   0x1180080901710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM739"              ,	   0x1180080901718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM740"              ,	   0x1180080901720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM741"              ,	   0x1180080901728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM742"              ,	   0x1180080901730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM743"              ,	   0x1180080901738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM744"              ,	   0x1180080901740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM745"              ,	   0x1180080901748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM746"              ,	   0x1180080901750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM747"              ,	   0x1180080901758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM748"              ,	   0x1180080901760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM749"              ,	   0x1180080901768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM750"              ,	   0x1180080901770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM751"              ,	   0x1180080901778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM752"              ,	   0x1180080901780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM753"              ,	   0x1180080901788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM754"              ,	   0x1180080901790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM755"              ,	   0x1180080901798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM756"              ,	   0x11800809017a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM757"              ,	   0x11800809017a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM758"              ,	   0x11800809017b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM759"              ,	   0x11800809017b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM760"              ,	   0x11800809017c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM761"              ,	   0x11800809017c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM762"              ,	   0x11800809017d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM763"              ,	   0x11800809017d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM764"              ,	   0x11800809017e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM765"              ,	   0x11800809017e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM766"              ,	   0x11800809017f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM767"              ,	   0x11800809017f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM768"              ,	   0x1180080901800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM769"              ,	   0x1180080901808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM770"              ,	   0x1180080901810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM771"              ,	   0x1180080901818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM772"              ,	   0x1180080901820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM773"              ,	   0x1180080901828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM774"              ,	   0x1180080901830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM775"              ,	   0x1180080901838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM776"              ,	   0x1180080901840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM777"              ,	   0x1180080901848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM778"              ,	   0x1180080901850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM779"              ,	   0x1180080901858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM780"              ,	   0x1180080901860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM781"              ,	   0x1180080901868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM782"              ,	   0x1180080901870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM783"              ,	   0x1180080901878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM784"              ,	   0x1180080901880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM785"              ,	   0x1180080901888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM786"              ,	   0x1180080901890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM787"              ,	   0x1180080901898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM788"              ,	   0x11800809018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM789"              ,	   0x11800809018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM790"              ,	   0x11800809018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM791"              ,	   0x11800809018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM792"              ,	   0x11800809018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM793"              ,	   0x11800809018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM794"              ,	   0x11800809018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM795"              ,	   0x11800809018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM796"              ,	   0x11800809018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM797"              ,	   0x11800809018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM798"              ,	   0x11800809018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM799"              ,	   0x11800809018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM800"              ,	   0x1180080901900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM801"              ,	   0x1180080901908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM802"              ,	   0x1180080901910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM803"              ,	   0x1180080901918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM804"              ,	   0x1180080901920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM805"              ,	   0x1180080901928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM806"              ,	   0x1180080901930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM807"              ,	   0x1180080901938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM808"              ,	   0x1180080901940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM809"              ,	   0x1180080901948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM810"              ,	   0x1180080901950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM811"              ,	   0x1180080901958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM812"              ,	   0x1180080901960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM813"              ,	   0x1180080901968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM814"              ,	   0x1180080901970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM815"              ,	   0x1180080901978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM816"              ,	   0x1180080901980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM817"              ,	   0x1180080901988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM818"              ,	   0x1180080901990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM819"              ,	   0x1180080901998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM820"              ,	   0x11800809019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM821"              ,	   0x11800809019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM822"              ,	   0x11800809019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM823"              ,	   0x11800809019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM824"              ,	   0x11800809019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM825"              ,	   0x11800809019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM826"              ,	   0x11800809019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM827"              ,	   0x11800809019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM828"              ,	   0x11800809019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM829"              ,	   0x11800809019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM830"              ,	   0x11800809019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM831"              ,	   0x11800809019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM832"              ,	   0x1180080901a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM833"              ,	   0x1180080901a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM834"              ,	   0x1180080901a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM835"              ,	   0x1180080901a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM836"              ,	   0x1180080901a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM837"              ,	   0x1180080901a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM838"              ,	   0x1180080901a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM839"              ,	   0x1180080901a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM840"              ,	   0x1180080901a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM841"              ,	   0x1180080901a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM842"              ,	   0x1180080901a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM843"              ,	   0x1180080901a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM844"              ,	   0x1180080901a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM845"              ,	   0x1180080901a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM846"              ,	   0x1180080901a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM847"              ,	   0x1180080901a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM848"              ,	   0x1180080901a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM849"              ,	   0x1180080901a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM850"              ,	   0x1180080901a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM851"              ,	   0x1180080901a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM852"              ,	   0x1180080901aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM853"              ,	   0x1180080901aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM854"              ,	   0x1180080901ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM855"              ,	   0x1180080901ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM856"              ,	   0x1180080901ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM857"              ,	   0x1180080901ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM858"              ,	   0x1180080901ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM859"              ,	   0x1180080901ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM860"              ,	   0x1180080901ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM861"              ,	   0x1180080901ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM862"              ,	   0x1180080901af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM863"              ,	   0x1180080901af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM864"              ,	   0x1180080901b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM865"              ,	   0x1180080901b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM866"              ,	   0x1180080901b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM867"              ,	   0x1180080901b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM868"              ,	   0x1180080901b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM869"              ,	   0x1180080901b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM870"              ,	   0x1180080901b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM871"              ,	   0x1180080901b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM872"              ,	   0x1180080901b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM873"              ,	   0x1180080901b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM874"              ,	   0x1180080901b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM875"              ,	   0x1180080901b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM876"              ,	   0x1180080901b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM877"              ,	   0x1180080901b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM878"              ,	   0x1180080901b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM879"              ,	   0x1180080901b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM880"              ,	   0x1180080901b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM881"              ,	   0x1180080901b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM882"              ,	   0x1180080901b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM883"              ,	   0x1180080901b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM884"              ,	   0x1180080901ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM885"              ,	   0x1180080901ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM886"              ,	   0x1180080901bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM887"              ,	   0x1180080901bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM888"              ,	   0x1180080901bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM889"              ,	   0x1180080901bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM890"              ,	   0x1180080901bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM891"              ,	   0x1180080901bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM892"              ,	   0x1180080901be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM893"              ,	   0x1180080901be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM894"              ,	   0x1180080901bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM895"              ,	   0x1180080901bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM896"              ,	   0x1180080901c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM897"              ,	   0x1180080901c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM898"              ,	   0x1180080901c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM899"              ,	   0x1180080901c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM900"              ,	   0x1180080901c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM901"              ,	   0x1180080901c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM902"              ,	   0x1180080901c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM903"              ,	   0x1180080901c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM904"              ,	   0x1180080901c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM905"              ,	   0x1180080901c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM906"              ,	   0x1180080901c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM907"              ,	   0x1180080901c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM908"              ,	   0x1180080901c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM909"              ,	   0x1180080901c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM910"              ,	   0x1180080901c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM911"              ,	   0x1180080901c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM912"              ,	   0x1180080901c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM913"              ,	   0x1180080901c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM914"              ,	   0x1180080901c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM915"              ,	   0x1180080901c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM916"              ,	   0x1180080901ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM917"              ,	   0x1180080901ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM918"              ,	   0x1180080901cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM919"              ,	   0x1180080901cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM920"              ,	   0x1180080901cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM921"              ,	   0x1180080901cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM922"              ,	   0x1180080901cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM923"              ,	   0x1180080901cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM924"              ,	   0x1180080901ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM925"              ,	   0x1180080901ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM926"              ,	   0x1180080901cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM927"              ,	   0x1180080901cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM928"              ,	   0x1180080901d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM929"              ,	   0x1180080901d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM930"              ,	   0x1180080901d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM931"              ,	   0x1180080901d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM932"              ,	   0x1180080901d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM933"              ,	   0x1180080901d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM934"              ,	   0x1180080901d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM935"              ,	   0x1180080901d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM936"              ,	   0x1180080901d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM937"              ,	   0x1180080901d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM938"              ,	   0x1180080901d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM939"              ,	   0x1180080901d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM940"              ,	   0x1180080901d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM941"              ,	   0x1180080901d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM942"              ,	   0x1180080901d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM943"              ,	   0x1180080901d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM944"              ,	   0x1180080901d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM945"              ,	   0x1180080901d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM946"              ,	   0x1180080901d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM947"              ,	   0x1180080901d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM948"              ,	   0x1180080901da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM949"              ,	   0x1180080901da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM950"              ,	   0x1180080901db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM951"              ,	   0x1180080901db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM952"              ,	   0x1180080901dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM953"              ,	   0x1180080901dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM954"              ,	   0x1180080901dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM955"              ,	   0x1180080901dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM956"              ,	   0x1180080901de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM957"              ,	   0x1180080901de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM958"              ,	   0x1180080901df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM959"              ,	   0x1180080901df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM960"              ,	   0x1180080901e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM961"              ,	   0x1180080901e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM962"              ,	   0x1180080901e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM963"              ,	   0x1180080901e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM964"              ,	   0x1180080901e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM965"              ,	   0x1180080901e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM966"              ,	   0x1180080901e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM967"              ,	   0x1180080901e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM968"              ,	   0x1180080901e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM969"              ,	   0x1180080901e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM970"              ,	   0x1180080901e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM971"              ,	   0x1180080901e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM972"              ,	   0x1180080901e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM973"              ,	   0x1180080901e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM974"              ,	   0x1180080901e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM975"              ,	   0x1180080901e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM976"              ,	   0x1180080901e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM977"              ,	   0x1180080901e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM978"              ,	   0x1180080901e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM979"              ,	   0x1180080901e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM980"              ,	   0x1180080901ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM981"              ,	   0x1180080901ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM982"              ,	   0x1180080901eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM983"              ,	   0x1180080901eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM984"              ,	   0x1180080901ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM985"              ,	   0x1180080901ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM986"              ,	   0x1180080901ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM987"              ,	   0x1180080901ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM988"              ,	   0x1180080901ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM989"              ,	   0x1180080901ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM990"              ,	   0x1180080901ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM991"              ,	   0x1180080901ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM992"              ,	   0x1180080901f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM993"              ,	   0x1180080901f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM994"              ,	   0x1180080901f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM995"              ,	   0x1180080901f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM996"              ,	   0x1180080901f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM997"              ,	   0x1180080901f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM998"              ,	   0x1180080901f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM999"              ,	   0x1180080901f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1000"             ,	   0x1180080901f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1001"             ,	   0x1180080901f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1002"             ,	   0x1180080901f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1003"             ,	   0x1180080901f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1004"             ,	   0x1180080901f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1005"             ,	   0x1180080901f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1006"             ,	   0x1180080901f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1007"             ,	   0x1180080901f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1008"             ,	   0x1180080901f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1009"             ,	   0x1180080901f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1010"             ,	   0x1180080901f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1011"             ,	   0x1180080901f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1012"             ,	   0x1180080901fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1013"             ,	   0x1180080901fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1014"             ,	   0x1180080901fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1015"             ,	   0x1180080901fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1016"             ,	   0x1180080901fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1017"             ,	   0x1180080901fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1018"             ,	   0x1180080901fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1019"             ,	   0x1180080901fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1020"             ,	   0x1180080901fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1021"             ,	   0x1180080901fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1022"             ,	   0x1180080901ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VRT_MEM1023"             ,	   0x1180080901ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_WPAR_IOB0"               ,	   0x1180080840200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
+	{"L2C_WPAR_IOB1"               ,	   0x1180080840208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
+	{"L2C_WPAR_PP0"                ,	   0x1180080840000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP1"                ,	   0x1180080840008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP2"                ,	   0x1180080840010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP3"                ,	   0x1180080840018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP4"                ,	   0x1180080840020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP5"                ,	   0x1180080840028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP6"                ,	   0x1180080840030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP7"                ,	   0x1180080840038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP8"                ,	   0x1180080840040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP9"                ,	   0x1180080840048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP10"               ,	   0x1180080840050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP11"               ,	   0x1180080840058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP12"               ,	   0x1180080840060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP13"               ,	   0x1180080840068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP14"               ,	   0x1180080840070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP15"               ,	   0x1180080840078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP16"               ,	   0x1180080840080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP17"               ,	   0x1180080840088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP18"               ,	   0x1180080840090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP19"               ,	   0x1180080840098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP20"               ,	   0x11800808400a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP21"               ,	   0x11800808400a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP22"               ,	   0x11800808400b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP23"               ,	   0x11800808400b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP24"               ,	   0x11800808400c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP25"               ,	   0x11800808400c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP26"               ,	   0x11800808400d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP27"               ,	   0x11800808400d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP28"               ,	   0x11800808400e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP29"               ,	   0x11800808400e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP30"               ,	   0x11800808400f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_WPAR_PP31"               ,	   0x11800808400f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_XMC0_PFC"                ,	   0x1180080800400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
+	{"L2C_XMC1_PFC"                ,	   0x1180080800440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
+	{"L2C_XMC2_PFC"                ,	   0x1180080800480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
+	{"L2C_XMC3_PFC"                ,	   0x11800808004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
+	{"L2C_XMC_CMD"                 ,	   0x1180080800028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_XMD0_PFC"                ,	   0x1180080800408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	643},
+	{"L2C_XMD1_PFC"                ,	   0x1180080800448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	643},
+	{"L2C_XMD2_PFC"                ,	   0x1180080800488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	643},
+	{"L2C_XMD3_PFC"                ,	   0x11800808004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	643},
+	{"LMC0_CHAR_CTL"               ,	   0x1180088000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"LMC1_CHAR_CTL"               ,	   0x1180089000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"LMC2_CHAR_CTL"               ,	   0x118008a000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"LMC3_CHAR_CTL"               ,	   0x118008b000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"LMC0_CHAR_MASK0"             ,	   0x1180088000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
+	{"LMC1_CHAR_MASK0"             ,	   0x1180089000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
+	{"LMC2_CHAR_MASK0"             ,	   0x118008a000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
+	{"LMC3_CHAR_MASK0"             ,	   0x118008b000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
+	{"LMC0_CHAR_MASK1"             ,	   0x1180088000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"LMC1_CHAR_MASK1"             ,	   0x1180089000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"LMC2_CHAR_MASK1"             ,	   0x118008a000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"LMC3_CHAR_MASK1"             ,	   0x118008b000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"LMC0_CHAR_MASK2"             ,	   0x1180088000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
+	{"LMC1_CHAR_MASK2"             ,	   0x1180089000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
+	{"LMC2_CHAR_MASK2"             ,	   0x118008a000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
+	{"LMC3_CHAR_MASK2"             ,	   0x118008b000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
+	{"LMC0_CHAR_MASK3"             ,	   0x1180088000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	648},
+	{"LMC1_CHAR_MASK3"             ,	   0x1180089000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	648},
+	{"LMC2_CHAR_MASK3"             ,	   0x118008a000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	648},
+	{"LMC3_CHAR_MASK3"             ,	   0x118008b000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	648},
+	{"LMC0_CHAR_MASK4"             ,	   0x1180088000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
+	{"LMC1_CHAR_MASK4"             ,	   0x1180089000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
+	{"LMC2_CHAR_MASK4"             ,	   0x118008a000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
+	{"LMC3_CHAR_MASK4"             ,	   0x118008b000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
+	{"LMC0_COMP_CTL2"              ,	   0x11800880001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
+	{"LMC1_COMP_CTL2"              ,	   0x11800890001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
+	{"LMC2_COMP_CTL2"              ,	   0x118008a0001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
+	{"LMC3_COMP_CTL2"              ,	   0x118008b0001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
+	{"LMC0_CONFIG"                 ,	   0x1180088000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
+	{"LMC1_CONFIG"                 ,	   0x1180089000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
+	{"LMC2_CONFIG"                 ,	   0x118008a000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
+	{"LMC3_CONFIG"                 ,	   0x118008b000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
+	{"LMC0_CONTROL"                ,	   0x1180088000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
+	{"LMC1_CONTROL"                ,	   0x1180089000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
+	{"LMC2_CONTROL"                ,	   0x118008a000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
+	{"LMC3_CONTROL"                ,	   0x118008b000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
+	{"LMC0_DCLK_CNT"               ,	   0x11800880001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
+	{"LMC1_DCLK_CNT"               ,	   0x11800890001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
+	{"LMC2_DCLK_CNT"               ,	   0x118008a0001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
+	{"LMC3_DCLK_CNT"               ,	   0x118008b0001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
+	{"LMC0_DDR_PLL_CTL"            ,	   0x1180088000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
+	{"LMC1_DDR_PLL_CTL"            ,	   0x1180089000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
+	{"LMC2_DDR_PLL_CTL"            ,	   0x118008a000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
+	{"LMC3_DDR_PLL_CTL"            ,	   0x118008b000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
+	{"LMC0_DIMM000_PARAMS"         ,	   0x1180088000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"LMC0_DIMM001_PARAMS"         ,	   0x1180088000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"LMC1_DIMM000_PARAMS"         ,	   0x1180089000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"LMC1_DIMM001_PARAMS"         ,	   0x1180089000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"LMC2_DIMM000_PARAMS"         ,	   0x118008a000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"LMC2_DIMM001_PARAMS"         ,	   0x118008a000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"LMC3_DIMM000_PARAMS"         ,	   0x118008b000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"LMC3_DIMM001_PARAMS"         ,	   0x118008b000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"LMC0_DIMM_CTL"               ,	   0x1180088000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
+	{"LMC1_DIMM_CTL"               ,	   0x1180089000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
+	{"LMC2_DIMM_CTL"               ,	   0x118008a000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
+	{"LMC3_DIMM_CTL"               ,	   0x118008b000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
+	{"LMC0_DLL_CTL2"               ,	   0x11800880001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
+	{"LMC1_DLL_CTL2"               ,	   0x11800890001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
+	{"LMC2_DLL_CTL2"               ,	   0x118008a0001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
+	{"LMC3_DLL_CTL2"               ,	   0x118008b0001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
+	{"LMC0_DLL_CTL3"               ,	   0x1180088000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
+	{"LMC1_DLL_CTL3"               ,	   0x1180089000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
+	{"LMC2_DLL_CTL3"               ,	   0x118008a000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
+	{"LMC3_DLL_CTL3"               ,	   0x118008b000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
+	{"LMC0_DUAL_MEMCFG"            ,	   0x1180088000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
+	{"LMC1_DUAL_MEMCFG"            ,	   0x1180089000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
+	{"LMC2_DUAL_MEMCFG"            ,	   0x118008a000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
+	{"LMC3_DUAL_MEMCFG"            ,	   0x118008b000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
+	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
+	{"LMC1_ECC_SYND"               ,	   0x1180089000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
+	{"LMC2_ECC_SYND"               ,	   0x118008a000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
+	{"LMC3_ECC_SYND"               ,	   0x118008b000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
+	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"LMC1_FADR"                   ,	   0x1180089000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"LMC2_FADR"                   ,	   0x118008a000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"LMC3_FADR"                   ,	   0x118008b000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"LMC0_IFB_CNT"                ,	   0x11800880001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"LMC1_IFB_CNT"                ,	   0x11800890001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"LMC2_IFB_CNT"                ,	   0x118008a0001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"LMC3_IFB_CNT"                ,	   0x118008b0001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"LMC0_INT"                    ,	   0x11800880001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
+	{"LMC1_INT"                    ,	   0x11800890001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
+	{"LMC2_INT"                    ,	   0x118008a0001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
+	{"LMC3_INT"                    ,	   0x118008b0001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
+	{"LMC0_INT_EN"                 ,	   0x11800880001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
+	{"LMC1_INT_EN"                 ,	   0x11800890001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
+	{"LMC2_INT_EN"                 ,	   0x118008a0001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
+	{"LMC3_INT_EN"                 ,	   0x118008b0001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
+	{"LMC0_MODEREG_PARAMS0"        ,	   0x11800880001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
+	{"LMC1_MODEREG_PARAMS0"        ,	   0x11800890001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
+	{"LMC2_MODEREG_PARAMS0"        ,	   0x118008a0001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
+	{"LMC3_MODEREG_PARAMS0"        ,	   0x118008b0001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
+	{"LMC0_MODEREG_PARAMS1"        ,	   0x1180088000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"LMC1_MODEREG_PARAMS1"        ,	   0x1180089000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"LMC2_MODEREG_PARAMS1"        ,	   0x118008a000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"LMC3_MODEREG_PARAMS1"        ,	   0x118008b000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"LMC0_NXM"                    ,	   0x11800880000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
+	{"LMC1_NXM"                    ,	   0x11800890000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
+	{"LMC2_NXM"                    ,	   0x118008a0000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
+	{"LMC3_NXM"                    ,	   0x118008b0000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
+	{"LMC0_OPS_CNT"                ,	   0x11800880001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"LMC1_OPS_CNT"                ,	   0x11800890001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"LMC2_OPS_CNT"                ,	   0x118008a0001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"LMC3_OPS_CNT"                ,	   0x118008b0001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"LMC0_PHY_CTL"                ,	   0x1180088000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"LMC1_PHY_CTL"                ,	   0x1180089000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"LMC2_PHY_CTL"                ,	   0x118008a000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"LMC3_PHY_CTL"                ,	   0x118008b000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"LMC0_RESET_CTL"              ,	   0x1180088000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	670},
+	{"LMC1_RESET_CTL"              ,	   0x1180089000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	670},
+	{"LMC2_RESET_CTL"              ,	   0x118008a000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	670},
+	{"LMC3_RESET_CTL"              ,	   0x118008b000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	670},
+	{"LMC0_RLEVEL_CTL"             ,	   0x11800880002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	671},
+	{"LMC1_RLEVEL_CTL"             ,	   0x11800890002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	671},
+	{"LMC2_RLEVEL_CTL"             ,	   0x118008a0002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	671},
+	{"LMC3_RLEVEL_CTL"             ,	   0x118008b0002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	671},
+	{"LMC0_RLEVEL_DBG"             ,	   0x11800880002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
+	{"LMC1_RLEVEL_DBG"             ,	   0x11800890002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
+	{"LMC2_RLEVEL_DBG"             ,	   0x118008a0002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
+	{"LMC3_RLEVEL_DBG"             ,	   0x118008b0002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
+	{"LMC0_RLEVEL_RANK000"         ,	   0x1180088000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC0_RLEVEL_RANK001"         ,	   0x1180088000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC0_RLEVEL_RANK002"         ,	   0x1180088000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC0_RLEVEL_RANK003"         ,	   0x1180088000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC1_RLEVEL_RANK000"         ,	   0x1180089000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC1_RLEVEL_RANK001"         ,	   0x1180089000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC1_RLEVEL_RANK002"         ,	   0x1180089000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC1_RLEVEL_RANK003"         ,	   0x1180089000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC2_RLEVEL_RANK000"         ,	   0x118008a000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC2_RLEVEL_RANK001"         ,	   0x118008a000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC2_RLEVEL_RANK002"         ,	   0x118008a000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC2_RLEVEL_RANK003"         ,	   0x118008a000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC3_RLEVEL_RANK000"         ,	   0x118008b000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC3_RLEVEL_RANK001"         ,	   0x118008b000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC3_RLEVEL_RANK002"         ,	   0x118008b000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC3_RLEVEL_RANK003"         ,	   0x118008b000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC0_RODT_MASK"              ,	   0x1180088000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"LMC1_RODT_MASK"              ,	   0x1180089000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"LMC2_RODT_MASK"              ,	   0x118008a000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"LMC3_RODT_MASK"              ,	   0x118008b000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"LMC0_SLOT_CTL0"              ,	   0x11800880001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"LMC1_SLOT_CTL0"              ,	   0x11800890001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"LMC2_SLOT_CTL0"              ,	   0x118008a0001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"LMC3_SLOT_CTL0"              ,	   0x118008b0001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"LMC0_SLOT_CTL1"              ,	   0x1180088000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"LMC1_SLOT_CTL1"              ,	   0x1180089000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"LMC2_SLOT_CTL1"              ,	   0x118008a000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"LMC3_SLOT_CTL1"              ,	   0x118008b000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"LMC0_SLOT_CTL2"              ,	   0x1180088000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"LMC1_SLOT_CTL2"              ,	   0x1180089000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"LMC2_SLOT_CTL2"              ,	   0x118008a000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"LMC3_SLOT_CTL2"              ,	   0x118008b000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"LMC0_TIMING_PARAMS0"         ,	   0x1180088000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	678},
+	{"LMC1_TIMING_PARAMS0"         ,	   0x1180089000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	678},
+	{"LMC2_TIMING_PARAMS0"         ,	   0x118008a000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	678},
+	{"LMC3_TIMING_PARAMS0"         ,	   0x118008b000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	678},
+	{"LMC0_TIMING_PARAMS1"         ,	   0x11800880001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC1_TIMING_PARAMS1"         ,	   0x11800890001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC2_TIMING_PARAMS1"         ,	   0x118008a0001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC3_TIMING_PARAMS1"         ,	   0x118008b0001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC0_TRO_CTL"                ,	   0x1180088000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"LMC1_TRO_CTL"                ,	   0x1180089000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"LMC2_TRO_CTL"                ,	   0x118008a000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"LMC3_TRO_CTL"                ,	   0x118008b000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"LMC0_TRO_STAT"               ,	   0x1180088000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"LMC1_TRO_STAT"               ,	   0x1180089000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"LMC2_TRO_STAT"               ,	   0x118008a000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"LMC3_TRO_STAT"               ,	   0x118008b000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"LMC0_WLEVEL_CTL"             ,	   0x1180088000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"LMC1_WLEVEL_CTL"             ,	   0x1180089000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"LMC2_WLEVEL_CTL"             ,	   0x118008a000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"LMC3_WLEVEL_CTL"             ,	   0x118008b000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"LMC0_WLEVEL_DBG"             ,	   0x1180088000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"LMC1_WLEVEL_DBG"             ,	   0x1180089000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"LMC2_WLEVEL_DBG"             ,	   0x118008a000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"LMC3_WLEVEL_DBG"             ,	   0x118008b000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"LMC0_WLEVEL_RANK000"         ,	   0x11800880002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC0_WLEVEL_RANK001"         ,	   0x11800880002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC0_WLEVEL_RANK002"         ,	   0x11800880002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC0_WLEVEL_RANK003"         ,	   0x11800880002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC1_WLEVEL_RANK000"         ,	   0x11800890002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC1_WLEVEL_RANK001"         ,	   0x11800890002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC1_WLEVEL_RANK002"         ,	   0x11800890002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC1_WLEVEL_RANK003"         ,	   0x11800890002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC2_WLEVEL_RANK000"         ,	   0x118008a0002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC2_WLEVEL_RANK001"         ,	   0x118008a0002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC2_WLEVEL_RANK002"         ,	   0x118008a0002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC2_WLEVEL_RANK003"         ,	   0x118008a0002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC3_WLEVEL_RANK000"         ,	   0x118008b0002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC3_WLEVEL_RANK001"         ,	   0x118008b0002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC3_WLEVEL_RANK002"         ,	   0x118008b0002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC3_WLEVEL_RANK003"         ,	   0x118008b0002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC0_WODT_MASK"              ,	   0x11800880001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"LMC1_WODT_MASK"              ,	   0x11800890001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"LMC2_WODT_MASK"              ,	   0x118008a0001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"LMC3_WODT_MASK"              ,	   0x118008b0001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"MIO_BOOT_COMP"               ,	   0x11800000000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"MIO_BOOT_DMA_CFG0"           ,	   0x1180000000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"MIO_BOOT_DMA_CFG1"           ,	   0x1180000000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"MIO_BOOT_DMA_INT0"           ,	   0x1180000000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"MIO_BOOT_DMA_INT1"           ,	   0x1180000000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"MIO_BOOT_DMA_INT_EN0"        ,	   0x1180000000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"MIO_BOOT_DMA_INT_EN1"        ,	   0x1180000000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"MIO_BOOT_DMA_TIM0"           ,	   0x1180000000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"MIO_BOOT_DMA_TIM1"           ,	   0x1180000000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"MIO_BOOT_INT"                ,	   0x11800000000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"MIO_BOOT_PIN_DEFS"           ,	   0x11800000000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"MIO_BOOT_REG_CFG3"           ,	   0x1180000000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"MIO_BOOT_REG_CFG4"           ,	   0x1180000000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"MIO_BOOT_REG_CFG5"           ,	   0x1180000000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"MIO_BOOT_REG_CFG6"           ,	   0x1180000000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"MIO_BOOT_REG_CFG7"           ,	   0x1180000000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"MIO_BOOT_REG_TIM0"           ,	   0x1180000000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"MIO_BOOT_REG_TIM1"           ,	   0x1180000000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"MIO_BOOT_REG_TIM2"           ,	   0x1180000000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"MIO_BOOT_REG_TIM3"           ,	   0x1180000000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"MIO_BOOT_REG_TIM4"           ,	   0x1180000000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"MIO_BOOT_THR"                ,	   0x11800000000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"MIO_FUS_DAT3"                ,	   0x1180000001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"MIO_FUS_EMA"                 ,	   0x1180000001550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"MIO_FUS_PDF"                 ,	   0x1180000001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"MIO_FUS_PLL"                 ,	   0x1180000001580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"MIO_FUS_PROG"                ,	   0x1180000001510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"MIO_FUS_PROG_TIMES"          ,	   0x1180000001518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"MIO_FUS_RCMD"                ,	   0x1180000001500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"MIO_FUS_READ_TIMES"          ,	   0x1180000001570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"MIO_FUS_REPAIR_RES0"         ,	   0x1180000001558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"MIO_FUS_REPAIR_RES1"         ,	   0x1180000001560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"MIO_FUS_REPAIR_RES2"         ,	   0x1180000001568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
+	{"MIO_FUS_SPR_REPAIR_RES"      ,	   0x1180000001548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
+	{"MIO_FUS_SPR_REPAIR_SUM"      ,	   0x1180000001540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
+	{"MIO_FUS_WADR"                ,	   0x1180000001508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
+	{"MIO_GPIO_COMP"               ,	   0x11800000000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
+	{"MIO_NDF_DMA_CFG"             ,	   0x1180000000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
+	{"MIO_NDF_DMA_INT"             ,	   0x1180000000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
+	{"MIO_NDF_DMA_INT_EN"          ,	   0x1180000000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
+	{"MIO_PTP_CLOCK_CFG"           ,	   0x1070000000f00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	723},
+	{"MIO_PTP_CLOCK_COMP"          ,	   0x1070000000f18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	724},
+	{"MIO_PTP_CLOCK_HI"            ,	   0x1070000000f10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	725},
+	{"MIO_PTP_CLOCK_LO"            ,	   0x1070000000f08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	726},
+	{"MIO_PTP_EVT_CNT"             ,	   0x1070000000f28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	727},
+	{"MIO_PTP_TIMESTAMP"           ,	   0x1070000000f20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	728},
+	{"MIO_QLM0_CFG"                ,	   0x1180000001590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"MIO_QLM1_CFG"                ,	   0x1180000001598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"MIO_QLM2_CFG"                ,	   0x11800000015a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"MIO_QLM3_CFG"                ,	   0x11800000015a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"MIO_QLM4_CFG"                ,	   0x11800000015b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"MIO_RST_BOOT"                ,	   0x1180000001600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"MIO_RST_CFG"                 ,	   0x1180000001610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	731},
+	{"MIO_RST_CTL0"                ,	   0x1180000001618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
+	{"MIO_RST_CTL1"                ,	   0x1180000001620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
+	{"MIO_RST_DELAY"               ,	   0x1180000001608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	733},
+	{"MIO_RST_INT"                 ,	   0x1180000001628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	734},
+	{"MIO_RST_INT_EN"              ,	   0x1180000001630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	735},
+	{"MIO_TWS0_INT"                ,	   0x1180000001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	736},
+	{"MIO_TWS1_INT"                ,	   0x1180000001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	736},
+	{"MIO_TWS0_SW_TWSI"            ,	   0x1180000001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	737},
+	{"MIO_TWS1_SW_TWSI"            ,	   0x1180000001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	737},
+	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"MIO_TWS1_SW_TWSI_EXT"        ,	   0x1180000001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"MIO_TWS1_TWSI_SW"            ,	   0x1180000001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"MIO_UART1_DLH"               ,	   0x1180000000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"MIO_UART1_DLL"               ,	   0x1180000000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"MIO_UART1_FAR"               ,	   0x1180000000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"MIO_UART1_FCR"               ,	   0x1180000000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"MIO_UART0_HTX"               ,	   0x1180000000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	744},
+	{"MIO_UART1_HTX"               ,	   0x1180000000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	744},
+	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	745},
+	{"MIO_UART1_IER"               ,	   0x1180000000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	745},
+	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"MIO_UART1_IIR"               ,	   0x1180000000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"MIO_UART1_LCR"               ,	   0x1180000000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"MIO_UART1_LSR"               ,	   0x1180000000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"MIO_UART1_MCR"               ,	   0x1180000000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"MIO_UART1_MSR"               ,	   0x1180000000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"MIO_UART1_RBR"               ,	   0x1180000000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"MIO_UART0_RFL"               ,	   0x1180000000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"MIO_UART1_RFL"               ,	   0x1180000000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"MIO_UART1_RFW"               ,	   0x1180000000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"MIO_UART1_SCR"               ,	   0x1180000000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"MIO_UART0_SFE"               ,	   0x1180000000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"MIO_UART1_SFE"               ,	   0x1180000000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"MIO_UART0_SRR"               ,	   0x1180000000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"MIO_UART1_SRR"               ,	   0x1180000000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"MIO_UART0_SRT"               ,	   0x1180000000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"MIO_UART1_SRT"               ,	   0x1180000000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"MIO_UART0_STT"               ,	   0x1180000000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"MIO_UART1_STT"               ,	   0x1180000000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"MIO_UART0_TFL"               ,	   0x1180000000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"MIO_UART1_TFL"               ,	   0x1180000000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"MIO_UART1_TFR"               ,	   0x1180000000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"MIO_UART1_THR"               ,	   0x1180000000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"MIO_UART1_USR"               ,	   0x1180000000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"MIX0_BIST"                   ,	   0x1070000100078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	765},
+	{"MIX0_CTL"                    ,	   0x1070000100020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"MIX0_INTENA"                 ,	   0x1070000100050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"MIX0_IRCNT"                  ,	   0x1070000100030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	768},
+	{"MIX0_IRHWM"                  ,	   0x1070000100028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	769},
+	{"MIX0_IRING1"                 ,	   0x1070000100010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	770},
+	{"MIX0_IRING2"                 ,	   0x1070000100018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	771},
+	{"MIX0_ISR"                    ,	   0x1070000100048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	772},
+	{"MIX0_ORCNT"                  ,	   0x1070000100040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	773},
+	{"MIX0_ORHWM"                  ,	   0x1070000100038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	774},
+	{"MIX0_ORING1"                 ,	   0x1070000100000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	775},
+	{"MIX0_ORING2"                 ,	   0x1070000100008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	776},
+	{"MIX0_REMCNT"                 ,	   0x1070000100058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	777},
+	{"MIX0_TSCTL"                  ,	   0x1070000100068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	778},
+	{"MIX0_TSTAMP"                 ,	   0x1070000100060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	779},
+	{"NDF_BT_PG_INFO"              ,	   0x1070001000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	780},
+	{"NDF_CMD"                     ,	   0x1070001000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	781},
+	{"NDF_DRBELL"                  ,	   0x1070001000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	782},
+	{"NDF_ECC_CNT"                 ,	   0x1070001000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	783},
+	{"NDF_INT"                     ,	   0x1070001000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	784},
+	{"NDF_INT_EN"                  ,	   0x1070001000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	785},
+	{"NDF_MISC"                    ,	   0x1070001000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	786},
+	{"NDF_ST_REG"                  ,	   0x1070001000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	787},
+	{"PCIEEP0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	788},
+	{"PCIEEP1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	788},
+	{"PCIEEP0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	789},
+	{"PCIEEP1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	789},
+	{"PCIEEP0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	790},
+	{"PCIEEP1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	790},
+	{"PCIEEP0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	791},
+	{"PCIEEP1_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	791},
+	{"PCIEEP0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	792},
+	{"PCIEEP1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	792},
+	{"PCIEEP0_CFG004_MASK"         ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	793},
+	{"PCIEEP1_CFG004_MASK"         ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	793},
+	{"PCIEEP0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	794},
+	{"PCIEEP1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	794},
+	{"PCIEEP0_CFG005_MASK"         ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	795},
+	{"PCIEEP1_CFG005_MASK"         ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	795},
+	{"PCIEEP0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	796},
+	{"PCIEEP1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	796},
+	{"PCIEEP0_CFG006_MASK"         ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	797},
+	{"PCIEEP1_CFG006_MASK"         ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	797},
+	{"PCIEEP0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	798},
+	{"PCIEEP1_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	798},
+	{"PCIEEP0_CFG007_MASK"         ,	        0x8000001cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	799},
+	{"PCIEEP1_CFG007_MASK"         ,	        0x8000001cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	799},
+	{"PCIEEP0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	800},
+	{"PCIEEP1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	800},
+	{"PCIEEP0_CFG008_MASK"         ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	801},
+	{"PCIEEP1_CFG008_MASK"         ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	801},
+	{"PCIEEP0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	802},
+	{"PCIEEP1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	802},
+	{"PCIEEP0_CFG009_MASK"         ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	803},
+	{"PCIEEP1_CFG009_MASK"         ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	803},
+	{"PCIEEP0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	804},
+	{"PCIEEP1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	804},
+	{"PCIEEP0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	805},
+	{"PCIEEP1_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	805},
+	{"PCIEEP0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	806},
+	{"PCIEEP1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	806},
+	{"PCIEEP0_CFG012_MASK"         ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	807},
+	{"PCIEEP1_CFG012_MASK"         ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	807},
+	{"PCIEEP0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	808},
+	{"PCIEEP1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	808},
+	{"PCIEEP0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	809},
+	{"PCIEEP1_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	809},
+	{"PCIEEP0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	810},
+	{"PCIEEP1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	810},
+	{"PCIEEP0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	811},
+	{"PCIEEP1_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	811},
+	{"PCIEEP0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	812},
+	{"PCIEEP1_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	812},
+	{"PCIEEP0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	813},
+	{"PCIEEP1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	813},
+	{"PCIEEP0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	814},
+	{"PCIEEP1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	814},
+	{"PCIEEP0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	815},
+	{"PCIEEP1_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	815},
+	{"PCIEEP0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	816},
+	{"PCIEEP1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	816},
+	{"PCIEEP0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	817},
+	{"PCIEEP1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	817},
+	{"PCIEEP0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	818},
+	{"PCIEEP1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	818},
+	{"PCIEEP0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	819},
+	{"PCIEEP1_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	819},
+	{"PCIEEP0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	820},
+	{"PCIEEP1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	820},
+	{"PCIEEP0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	821},
+	{"PCIEEP1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	821},
+	{"PCIEEP0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	822},
+	{"PCIEEP1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	822},
+	{"PCIEEP0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	823},
+	{"PCIEEP1_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	823},
+	{"PCIEEP0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	824},
+	{"PCIEEP1_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	824},
+	{"PCIEEP0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	825},
+	{"PCIEEP1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	825},
+	{"PCIEEP0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	826},
+	{"PCIEEP1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	826},
+	{"PCIEEP0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	827},
+	{"PCIEEP1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	827},
+	{"PCIEEP0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	828},
+	{"PCIEEP1_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	828},
+	{"PCIEEP0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	829},
+	{"PCIEEP1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	829},
+	{"PCIEEP0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	830},
+	{"PCIEEP1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	830},
+	{"PCIEEP0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	831},
+	{"PCIEEP1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	831},
+	{"PCIEEP0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	832},
+	{"PCIEEP1_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	832},
+	{"PCIEEP0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	833},
+	{"PCIEEP1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	833},
+	{"PCIEEP0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	834},
+	{"PCIEEP1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	834},
+	{"PCIEEP0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	835},
+	{"PCIEEP1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	835},
+	{"PCIEEP0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	836},
+	{"PCIEEP1_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	836},
+	{"PCIEEP0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	837},
+	{"PCIEEP1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	837},
+	{"PCIEEP0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	838},
+	{"PCIEEP1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	838},
+	{"PCIEEP0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	839},
+	{"PCIEEP1_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	839},
+	{"PCIEEP0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	840},
+	{"PCIEEP1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	840},
+	{"PCIEEP0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	841},
+	{"PCIEEP1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	841},
+	{"PCIEEP0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	842},
+	{"PCIEEP1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	842},
+	{"PCIEEP0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	843},
+	{"PCIEEP1_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	843},
+	{"PCIEEP0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	844},
+	{"PCIEEP1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	844},
+	{"PCIEEP0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	845},
+	{"PCIEEP1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	845},
+	{"PCIEEP0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	846},
+	{"PCIEEP1_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	846},
+	{"PCIEEP0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	847},
+	{"PCIEEP1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	847},
+	{"PCIEEP0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	848},
+	{"PCIEEP1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	848},
+	{"PCIEEP0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	849},
+	{"PCIEEP1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	849},
+	{"PCIEEP0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	850},
+	{"PCIEEP1_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	850},
+	{"PCIEEP0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	851},
+	{"PCIEEP1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	851},
+	{"PCIEEP0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	852},
+	{"PCIEEP1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	852},
+	{"PCIEEP0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	853},
+	{"PCIEEP1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	853},
+	{"PCIEEP0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	854},
+	{"PCIEEP1_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	854},
+	{"PCIEEP0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	855},
+	{"PCIEEP1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	855},
+	{"PCIEEP0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	856},
+	{"PCIEEP1_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	856},
+	{"PCIEEP0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	857},
+	{"PCIEEP1_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	857},
+	{"PCIEEP0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	858},
+	{"PCIEEP1_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	858},
+	{"PCIEEP0_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	859},
+	{"PCIEEP1_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	859},
+	{"PCIEEP0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	860},
+	{"PCIEEP1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	860},
+	{"PCIEEP0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	861},
+	{"PCIEEP1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	861},
+	{"PCIERC0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	862},
+	{"PCIERC1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	862},
+	{"PCIERC0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	863},
+	{"PCIERC1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	863},
+	{"PCIERC0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	864},
+	{"PCIERC1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	864},
+	{"PCIERC0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	865},
+	{"PCIERC1_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	865},
+	{"PCIERC0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	866},
+	{"PCIERC1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	866},
+	{"PCIERC0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	867},
+	{"PCIERC1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	867},
+	{"PCIERC0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	868},
+	{"PCIERC1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	868},
+	{"PCIERC0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	869},
+	{"PCIERC1_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	869},
+	{"PCIERC0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	870},
+	{"PCIERC1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	870},
+	{"PCIERC0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	871},
+	{"PCIERC1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	871},
+	{"PCIERC0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	872},
+	{"PCIERC1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	872},
+	{"PCIERC0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	873},
+	{"PCIERC1_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	873},
+	{"PCIERC0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	874},
+	{"PCIERC1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	874},
+	{"PCIERC0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	875},
+	{"PCIERC1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	875},
+	{"PCIERC0_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	876},
+	{"PCIERC1_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	876},
+	{"PCIERC0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	877},
+	{"PCIERC1_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	877},
+	{"PCIERC0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	878},
+	{"PCIERC1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	878},
+	{"PCIERC0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	879},
+	{"PCIERC1_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	879},
+	{"PCIERC0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	880},
+	{"PCIERC1_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	880},
+	{"PCIERC0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	881},
+	{"PCIERC1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	881},
+	{"PCIERC0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	882},
+	{"PCIERC1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	882},
+	{"PCIERC0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	883},
+	{"PCIERC1_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	883},
+	{"PCIERC0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	884},
+	{"PCIERC1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	884},
+	{"PCIERC0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	885},
+	{"PCIERC1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	885},
+	{"PCIERC0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	886},
+	{"PCIERC1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	886},
+	{"PCIERC0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	887},
+	{"PCIERC1_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	887},
+	{"PCIERC0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	888},
+	{"PCIERC1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	888},
+	{"PCIERC0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	889},
+	{"PCIERC1_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	889},
+	{"PCIERC0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	890},
+	{"PCIERC1_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	890},
+	{"PCIERC0_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	891},
+	{"PCIERC1_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	891},
+	{"PCIERC0_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	892},
+	{"PCIERC1_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	892},
+	{"PCIERC0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	893},
+	{"PCIERC1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	893},
+	{"PCIERC0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	894},
+	{"PCIERC1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	894},
+	{"PCIERC0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	895},
+	{"PCIERC1_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	895},
+	{"PCIERC0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	896},
+	{"PCIERC1_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	896},
+	{"PCIERC0_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	897},
+	{"PCIERC1_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	897},
+	{"PCIERC0_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	898},
+	{"PCIERC1_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	898},
+	{"PCIERC0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	899},
+	{"PCIERC1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	899},
+	{"PCIERC0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	900},
+	{"PCIERC1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	900},
+	{"PCIERC0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	901},
+	{"PCIERC1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	901},
+	{"PCIERC0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	902},
+	{"PCIERC1_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	902},
+	{"PCIERC0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	903},
+	{"PCIERC1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	903},
+	{"PCIERC0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	904},
+	{"PCIERC1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	904},
+	{"PCIERC0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	905},
+	{"PCIERC1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	905},
+	{"PCIERC0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	906},
+	{"PCIERC1_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	906},
+	{"PCIERC0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	907},
+	{"PCIERC1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	907},
+	{"PCIERC0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	908},
+	{"PCIERC1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	908},
+	{"PCIERC0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	909},
+	{"PCIERC1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	909},
+	{"PCIERC0_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	910},
+	{"PCIERC1_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	910},
+	{"PCIERC0_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	911},
+	{"PCIERC1_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	911},
+	{"PCIERC0_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	912},
+	{"PCIERC1_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	912},
+	{"PCIERC0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	913},
+	{"PCIERC1_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	913},
+	{"PCIERC0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	914},
+	{"PCIERC1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	914},
+	{"PCIERC0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	915},
+	{"PCIERC1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	915},
+	{"PCIERC0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	916},
+	{"PCIERC1_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	916},
+	{"PCIERC0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	917},
+	{"PCIERC1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	917},
+	{"PCIERC0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	918},
+	{"PCIERC1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	918},
+	{"PCIERC0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	919},
+	{"PCIERC1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	919},
+	{"PCIERC0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	920},
+	{"PCIERC1_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	920},
+	{"PCIERC0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	921},
+	{"PCIERC1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	921},
+	{"PCIERC0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	922},
+	{"PCIERC1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	922},
+	{"PCIERC0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	923},
+	{"PCIERC1_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	923},
+	{"PCIERC0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	924},
+	{"PCIERC1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	924},
+	{"PCIERC0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	925},
+	{"PCIERC1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	925},
+	{"PCIERC0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	926},
+	{"PCIERC1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	926},
+	{"PCIERC0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	927},
+	{"PCIERC1_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	927},
+	{"PCIERC0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	928},
+	{"PCIERC1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	928},
+	{"PCIERC0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	929},
+	{"PCIERC1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	929},
+	{"PCIERC0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	930},
+	{"PCIERC1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	930},
+	{"PCIERC0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	931},
+	{"PCIERC1_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	931},
+	{"PCIERC0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	932},
+	{"PCIERC1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	932},
+	{"PCIERC0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	933},
+	{"PCIERC1_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	933},
+	{"PCIERC0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	934},
+	{"PCIERC1_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	934},
+	{"PCIERC0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	935},
+	{"PCIERC1_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	935},
+	{"PCIERC0_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	936},
+	{"PCIERC1_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	936},
+	{"PCIERC0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	937},
+	{"PCIERC1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	937},
+	{"PCIERC0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	938},
+	{"PCIERC1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	938},
+	{"PCS0_AN000_ADV_REG"          ,	   0x11800b0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS0_AN001_ADV_REG"          ,	   0x11800b0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS0_AN002_ADV_REG"          ,	   0x11800b0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS0_AN003_ADV_REG"          ,	   0x11800b0001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS1_AN000_ADV_REG"          ,	   0x11800b1001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS1_AN001_ADV_REG"          ,	   0x11800b1001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS1_AN002_ADV_REG"          ,	   0x11800b1001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS1_AN003_ADV_REG"          ,	   0x11800b1001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS2_AN000_ADV_REG"          ,	   0x11800b2001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS2_AN001_ADV_REG"          ,	   0x11800b2001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS2_AN002_ADV_REG"          ,	   0x11800b2001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS2_AN003_ADV_REG"          ,	   0x11800b2001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS3_AN000_ADV_REG"          ,	   0x11800b3001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS3_AN001_ADV_REG"          ,	   0x11800b3001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS3_AN002_ADV_REG"          ,	   0x11800b3001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS3_AN003_ADV_REG"          ,	   0x11800b3001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS4_AN000_ADV_REG"          ,	   0x11800b4001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS4_AN001_ADV_REG"          ,	   0x11800b4001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS4_AN002_ADV_REG"          ,	   0x11800b4001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS4_AN003_ADV_REG"          ,	   0x11800b4001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800b0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800b0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS0_AN002_EXT_ST_REG"       ,	   0x11800b0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS0_AN003_EXT_ST_REG"       ,	   0x11800b0001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS1_AN000_EXT_ST_REG"       ,	   0x11800b1001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS1_AN001_EXT_ST_REG"       ,	   0x11800b1001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS1_AN002_EXT_ST_REG"       ,	   0x11800b1001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS1_AN003_EXT_ST_REG"       ,	   0x11800b1001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS2_AN000_EXT_ST_REG"       ,	   0x11800b2001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS2_AN001_EXT_ST_REG"       ,	   0x11800b2001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS2_AN002_EXT_ST_REG"       ,	   0x11800b2001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS2_AN003_EXT_ST_REG"       ,	   0x11800b2001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS3_AN000_EXT_ST_REG"       ,	   0x11800b3001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS3_AN001_EXT_ST_REG"       ,	   0x11800b3001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS3_AN002_EXT_ST_REG"       ,	   0x11800b3001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS3_AN003_EXT_ST_REG"       ,	   0x11800b3001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS4_AN000_EXT_ST_REG"       ,	   0x11800b4001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS4_AN001_EXT_ST_REG"       ,	   0x11800b4001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS4_AN002_EXT_ST_REG"       ,	   0x11800b4001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS4_AN003_EXT_ST_REG"       ,	   0x11800b4001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800b0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800b0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS0_AN002_LP_ABIL_REG"      ,	   0x11800b0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS0_AN003_LP_ABIL_REG"      ,	   0x11800b0001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS1_AN000_LP_ABIL_REG"      ,	   0x11800b1001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS1_AN001_LP_ABIL_REG"      ,	   0x11800b1001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS1_AN002_LP_ABIL_REG"      ,	   0x11800b1001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS1_AN003_LP_ABIL_REG"      ,	   0x11800b1001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS2_AN000_LP_ABIL_REG"      ,	   0x11800b2001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS2_AN001_LP_ABIL_REG"      ,	   0x11800b2001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS2_AN002_LP_ABIL_REG"      ,	   0x11800b2001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS2_AN003_LP_ABIL_REG"      ,	   0x11800b2001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS3_AN000_LP_ABIL_REG"      ,	   0x11800b3001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS3_AN001_LP_ABIL_REG"      ,	   0x11800b3001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS3_AN002_LP_ABIL_REG"      ,	   0x11800b3001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS3_AN003_LP_ABIL_REG"      ,	   0x11800b3001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS4_AN000_LP_ABIL_REG"      ,	   0x11800b4001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS4_AN001_LP_ABIL_REG"      ,	   0x11800b4001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS4_AN002_LP_ABIL_REG"      ,	   0x11800b4001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS4_AN003_LP_ABIL_REG"      ,	   0x11800b4001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800b0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800b0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS0_AN002_RESULTS_REG"      ,	   0x11800b0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS0_AN003_RESULTS_REG"      ,	   0x11800b0001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS1_AN000_RESULTS_REG"      ,	   0x11800b1001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS1_AN001_RESULTS_REG"      ,	   0x11800b1001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS1_AN002_RESULTS_REG"      ,	   0x11800b1001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS1_AN003_RESULTS_REG"      ,	   0x11800b1001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS2_AN000_RESULTS_REG"      ,	   0x11800b2001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS2_AN001_RESULTS_REG"      ,	   0x11800b2001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS2_AN002_RESULTS_REG"      ,	   0x11800b2001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS2_AN003_RESULTS_REG"      ,	   0x11800b2001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS3_AN000_RESULTS_REG"      ,	   0x11800b3001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS3_AN001_RESULTS_REG"      ,	   0x11800b3001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS3_AN002_RESULTS_REG"      ,	   0x11800b3001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS3_AN003_RESULTS_REG"      ,	   0x11800b3001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS4_AN000_RESULTS_REG"      ,	   0x11800b4001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS4_AN001_RESULTS_REG"      ,	   0x11800b4001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS4_AN002_RESULTS_REG"      ,	   0x11800b4001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS4_AN003_RESULTS_REG"      ,	   0x11800b4001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PCS0_INT000_EN_REG"          ,	   0x11800b0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS0_INT001_EN_REG"          ,	   0x11800b0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS0_INT002_EN_REG"          ,	   0x11800b0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS0_INT003_EN_REG"          ,	   0x11800b0001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS1_INT000_EN_REG"          ,	   0x11800b1001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS1_INT001_EN_REG"          ,	   0x11800b1001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS1_INT002_EN_REG"          ,	   0x11800b1001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS1_INT003_EN_REG"          ,	   0x11800b1001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS2_INT000_EN_REG"          ,	   0x11800b2001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS2_INT001_EN_REG"          ,	   0x11800b2001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS2_INT002_EN_REG"          ,	   0x11800b2001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS2_INT003_EN_REG"          ,	   0x11800b2001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS3_INT000_EN_REG"          ,	   0x11800b3001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS3_INT001_EN_REG"          ,	   0x11800b3001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS3_INT002_EN_REG"          ,	   0x11800b3001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS3_INT003_EN_REG"          ,	   0x11800b3001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS4_INT000_EN_REG"          ,	   0x11800b4001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS4_INT001_EN_REG"          ,	   0x11800b4001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS4_INT002_EN_REG"          ,	   0x11800b4001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS4_INT003_EN_REG"          ,	   0x11800b4001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PCS0_INT000_REG"             ,	   0x11800b0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS0_INT001_REG"             ,	   0x11800b0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS0_INT002_REG"             ,	   0x11800b0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS0_INT003_REG"             ,	   0x11800b0001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS1_INT000_REG"             ,	   0x11800b1001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS1_INT001_REG"             ,	   0x11800b1001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS1_INT002_REG"             ,	   0x11800b1001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS1_INT003_REG"             ,	   0x11800b1001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS2_INT000_REG"             ,	   0x11800b2001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS2_INT001_REG"             ,	   0x11800b2001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS2_INT002_REG"             ,	   0x11800b2001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS2_INT003_REG"             ,	   0x11800b2001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS3_INT000_REG"             ,	   0x11800b3001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS3_INT001_REG"             ,	   0x11800b3001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS3_INT002_REG"             ,	   0x11800b3001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS3_INT003_REG"             ,	   0x11800b3001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS4_INT000_REG"             ,	   0x11800b4001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS4_INT001_REG"             ,	   0x11800b4001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS4_INT002_REG"             ,	   0x11800b4001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS4_INT003_REG"             ,	   0x11800b4001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800b0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800b0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS0_LINK002_TIMER_COUNT_REG",	   0x11800b0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS0_LINK003_TIMER_COUNT_REG",	   0x11800b0001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS1_LINK000_TIMER_COUNT_REG",	   0x11800b1001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS1_LINK001_TIMER_COUNT_REG",	   0x11800b1001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS1_LINK002_TIMER_COUNT_REG",	   0x11800b1001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS1_LINK003_TIMER_COUNT_REG",	   0x11800b1001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS2_LINK000_TIMER_COUNT_REG",	   0x11800b2001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS2_LINK001_TIMER_COUNT_REG",	   0x11800b2001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS2_LINK002_TIMER_COUNT_REG",	   0x11800b2001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS2_LINK003_TIMER_COUNT_REG",	   0x11800b2001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS3_LINK000_TIMER_COUNT_REG",	   0x11800b3001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS3_LINK001_TIMER_COUNT_REG",	   0x11800b3001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS3_LINK002_TIMER_COUNT_REG",	   0x11800b3001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS3_LINK003_TIMER_COUNT_REG",	   0x11800b3001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS4_LINK000_TIMER_COUNT_REG",	   0x11800b4001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS4_LINK001_TIMER_COUNT_REG",	   0x11800b4001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS4_LINK002_TIMER_COUNT_REG",	   0x11800b4001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS4_LINK003_TIMER_COUNT_REG",	   0x11800b4001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PCS0_LOG_ANL000_REG"         ,	   0x11800b0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS0_LOG_ANL001_REG"         ,	   0x11800b0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS0_LOG_ANL002_REG"         ,	   0x11800b0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS0_LOG_ANL003_REG"         ,	   0x11800b0001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS1_LOG_ANL000_REG"         ,	   0x11800b1001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS1_LOG_ANL001_REG"         ,	   0x11800b1001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS1_LOG_ANL002_REG"         ,	   0x11800b1001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS1_LOG_ANL003_REG"         ,	   0x11800b1001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS2_LOG_ANL000_REG"         ,	   0x11800b2001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS2_LOG_ANL001_REG"         ,	   0x11800b2001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS2_LOG_ANL002_REG"         ,	   0x11800b2001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS2_LOG_ANL003_REG"         ,	   0x11800b2001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS3_LOG_ANL000_REG"         ,	   0x11800b3001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS3_LOG_ANL001_REG"         ,	   0x11800b3001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS3_LOG_ANL002_REG"         ,	   0x11800b3001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS3_LOG_ANL003_REG"         ,	   0x11800b3001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS4_LOG_ANL000_REG"         ,	   0x11800b4001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS4_LOG_ANL001_REG"         ,	   0x11800b4001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS4_LOG_ANL002_REG"         ,	   0x11800b4001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS4_LOG_ANL003_REG"         ,	   0x11800b4001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PCS0_MISC000_CTL_REG"        ,	   0x11800b0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS0_MISC001_CTL_REG"        ,	   0x11800b0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS0_MISC002_CTL_REG"        ,	   0x11800b0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS0_MISC003_CTL_REG"        ,	   0x11800b0001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS1_MISC000_CTL_REG"        ,	   0x11800b1001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS1_MISC001_CTL_REG"        ,	   0x11800b1001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS1_MISC002_CTL_REG"        ,	   0x11800b1001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS1_MISC003_CTL_REG"        ,	   0x11800b1001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS2_MISC000_CTL_REG"        ,	   0x11800b2001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS2_MISC001_CTL_REG"        ,	   0x11800b2001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS2_MISC002_CTL_REG"        ,	   0x11800b2001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS2_MISC003_CTL_REG"        ,	   0x11800b2001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS3_MISC000_CTL_REG"        ,	   0x11800b3001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS3_MISC001_CTL_REG"        ,	   0x11800b3001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS3_MISC002_CTL_REG"        ,	   0x11800b3001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS3_MISC003_CTL_REG"        ,	   0x11800b3001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS4_MISC000_CTL_REG"        ,	   0x11800b4001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS4_MISC001_CTL_REG"        ,	   0x11800b4001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS4_MISC002_CTL_REG"        ,	   0x11800b4001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS4_MISC003_CTL_REG"        ,	   0x11800b4001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800b0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800b0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS0_MR002_CONTROL_REG"      ,	   0x11800b0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS0_MR003_CONTROL_REG"      ,	   0x11800b0001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS1_MR000_CONTROL_REG"      ,	   0x11800b1001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS1_MR001_CONTROL_REG"      ,	   0x11800b1001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS1_MR002_CONTROL_REG"      ,	   0x11800b1001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS1_MR003_CONTROL_REG"      ,	   0x11800b1001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS2_MR000_CONTROL_REG"      ,	   0x11800b2001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS2_MR001_CONTROL_REG"      ,	   0x11800b2001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS2_MR002_CONTROL_REG"      ,	   0x11800b2001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS2_MR003_CONTROL_REG"      ,	   0x11800b2001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS3_MR000_CONTROL_REG"      ,	   0x11800b3001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS3_MR001_CONTROL_REG"      ,	   0x11800b3001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS3_MR002_CONTROL_REG"      ,	   0x11800b3001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS3_MR003_CONTROL_REG"      ,	   0x11800b3001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS4_MR000_CONTROL_REG"      ,	   0x11800b4001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS4_MR001_CONTROL_REG"      ,	   0x11800b4001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS4_MR002_CONTROL_REG"      ,	   0x11800b4001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS4_MR003_CONTROL_REG"      ,	   0x11800b4001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PCS0_MR000_STATUS_REG"       ,	   0x11800b0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS0_MR001_STATUS_REG"       ,	   0x11800b0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS0_MR002_STATUS_REG"       ,	   0x11800b0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS0_MR003_STATUS_REG"       ,	   0x11800b0001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS1_MR000_STATUS_REG"       ,	   0x11800b1001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS1_MR001_STATUS_REG"       ,	   0x11800b1001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS1_MR002_STATUS_REG"       ,	   0x11800b1001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS1_MR003_STATUS_REG"       ,	   0x11800b1001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS2_MR000_STATUS_REG"       ,	   0x11800b2001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS2_MR001_STATUS_REG"       ,	   0x11800b2001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS2_MR002_STATUS_REG"       ,	   0x11800b2001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS2_MR003_STATUS_REG"       ,	   0x11800b2001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS3_MR000_STATUS_REG"       ,	   0x11800b3001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS3_MR001_STATUS_REG"       ,	   0x11800b3001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS3_MR002_STATUS_REG"       ,	   0x11800b3001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS3_MR003_STATUS_REG"       ,	   0x11800b3001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS4_MR000_STATUS_REG"       ,	   0x11800b4001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS4_MR001_STATUS_REG"       ,	   0x11800b4001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS4_MR002_STATUS_REG"       ,	   0x11800b4001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS4_MR003_STATUS_REG"       ,	   0x11800b4001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PCS0_RX000_STATES_REG"       ,	   0x11800b0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS0_RX001_STATES_REG"       ,	   0x11800b0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS0_RX002_STATES_REG"       ,	   0x11800b0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS0_RX003_STATES_REG"       ,	   0x11800b0001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS1_RX000_STATES_REG"       ,	   0x11800b1001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS1_RX001_STATES_REG"       ,	   0x11800b1001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS1_RX002_STATES_REG"       ,	   0x11800b1001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS1_RX003_STATES_REG"       ,	   0x11800b1001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS2_RX000_STATES_REG"       ,	   0x11800b2001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS2_RX001_STATES_REG"       ,	   0x11800b2001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS2_RX002_STATES_REG"       ,	   0x11800b2001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS2_RX003_STATES_REG"       ,	   0x11800b2001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS3_RX000_STATES_REG"       ,	   0x11800b3001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS3_RX001_STATES_REG"       ,	   0x11800b3001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS3_RX002_STATES_REG"       ,	   0x11800b3001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS3_RX003_STATES_REG"       ,	   0x11800b3001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS4_RX000_STATES_REG"       ,	   0x11800b4001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS4_RX001_STATES_REG"       ,	   0x11800b4001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS4_RX002_STATES_REG"       ,	   0x11800b4001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS4_RX003_STATES_REG"       ,	   0x11800b4001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PCS0_RX000_SYNC_REG"         ,	   0x11800b0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS0_RX001_SYNC_REG"         ,	   0x11800b0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS0_RX002_SYNC_REG"         ,	   0x11800b0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS0_RX003_SYNC_REG"         ,	   0x11800b0001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS1_RX000_SYNC_REG"         ,	   0x11800b1001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS1_RX001_SYNC_REG"         ,	   0x11800b1001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS1_RX002_SYNC_REG"         ,	   0x11800b1001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS1_RX003_SYNC_REG"         ,	   0x11800b1001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS2_RX000_SYNC_REG"         ,	   0x11800b2001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS2_RX001_SYNC_REG"         ,	   0x11800b2001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS2_RX002_SYNC_REG"         ,	   0x11800b2001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS2_RX003_SYNC_REG"         ,	   0x11800b2001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS3_RX000_SYNC_REG"         ,	   0x11800b3001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS3_RX001_SYNC_REG"         ,	   0x11800b3001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS3_RX002_SYNC_REG"         ,	   0x11800b3001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS3_RX003_SYNC_REG"         ,	   0x11800b3001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS4_RX000_SYNC_REG"         ,	   0x11800b4001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS4_RX001_SYNC_REG"         ,	   0x11800b4001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS4_RX002_SYNC_REG"         ,	   0x11800b4001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS4_RX003_SYNC_REG"         ,	   0x11800b4001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800b0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800b0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS0_SGM002_AN_ADV_REG"      ,	   0x11800b0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS0_SGM003_AN_ADV_REG"      ,	   0x11800b0001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS1_SGM000_AN_ADV_REG"      ,	   0x11800b1001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS1_SGM001_AN_ADV_REG"      ,	   0x11800b1001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS1_SGM002_AN_ADV_REG"      ,	   0x11800b1001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS1_SGM003_AN_ADV_REG"      ,	   0x11800b1001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS2_SGM000_AN_ADV_REG"      ,	   0x11800b2001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS2_SGM001_AN_ADV_REG"      ,	   0x11800b2001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS2_SGM002_AN_ADV_REG"      ,	   0x11800b2001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS2_SGM003_AN_ADV_REG"      ,	   0x11800b2001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS3_SGM000_AN_ADV_REG"      ,	   0x11800b3001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS3_SGM001_AN_ADV_REG"      ,	   0x11800b3001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS3_SGM002_AN_ADV_REG"      ,	   0x11800b3001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS3_SGM003_AN_ADV_REG"      ,	   0x11800b3001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS4_SGM000_AN_ADV_REG"      ,	   0x11800b4001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS4_SGM001_AN_ADV_REG"      ,	   0x11800b4001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS4_SGM002_AN_ADV_REG"      ,	   0x11800b4001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS4_SGM003_AN_ADV_REG"      ,	   0x11800b4001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800b0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800b0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS0_SGM002_LP_ADV_REG"      ,	   0x11800b0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS0_SGM003_LP_ADV_REG"      ,	   0x11800b0001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS1_SGM000_LP_ADV_REG"      ,	   0x11800b1001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS1_SGM001_LP_ADV_REG"      ,	   0x11800b1001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS1_SGM002_LP_ADV_REG"      ,	   0x11800b1001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS1_SGM003_LP_ADV_REG"      ,	   0x11800b1001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS2_SGM000_LP_ADV_REG"      ,	   0x11800b2001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS2_SGM001_LP_ADV_REG"      ,	   0x11800b2001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS2_SGM002_LP_ADV_REG"      ,	   0x11800b2001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS2_SGM003_LP_ADV_REG"      ,	   0x11800b2001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS3_SGM000_LP_ADV_REG"      ,	   0x11800b3001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS3_SGM001_LP_ADV_REG"      ,	   0x11800b3001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS3_SGM002_LP_ADV_REG"      ,	   0x11800b3001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS3_SGM003_LP_ADV_REG"      ,	   0x11800b3001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS4_SGM000_LP_ADV_REG"      ,	   0x11800b4001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS4_SGM001_LP_ADV_REG"      ,	   0x11800b4001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS4_SGM002_LP_ADV_REG"      ,	   0x11800b4001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS4_SGM003_LP_ADV_REG"      ,	   0x11800b4001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PCS0_TX000_STATES_REG"       ,	   0x11800b0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS0_TX001_STATES_REG"       ,	   0x11800b0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS0_TX002_STATES_REG"       ,	   0x11800b0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS0_TX003_STATES_REG"       ,	   0x11800b0001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS1_TX000_STATES_REG"       ,	   0x11800b1001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS1_TX001_STATES_REG"       ,	   0x11800b1001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS1_TX002_STATES_REG"       ,	   0x11800b1001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS1_TX003_STATES_REG"       ,	   0x11800b1001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS2_TX000_STATES_REG"       ,	   0x11800b2001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS2_TX001_STATES_REG"       ,	   0x11800b2001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS2_TX002_STATES_REG"       ,	   0x11800b2001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS2_TX003_STATES_REG"       ,	   0x11800b2001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS3_TX000_STATES_REG"       ,	   0x11800b3001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS3_TX001_STATES_REG"       ,	   0x11800b3001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS3_TX002_STATES_REG"       ,	   0x11800b3001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS3_TX003_STATES_REG"       ,	   0x11800b3001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS4_TX000_STATES_REG"       ,	   0x11800b4001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS4_TX001_STATES_REG"       ,	   0x11800b4001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS4_TX002_STATES_REG"       ,	   0x11800b4001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS4_TX003_STATES_REG"       ,	   0x11800b4001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800b0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800b0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS0_TX_RX002_POLARITY_REG"  ,	   0x11800b0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS0_TX_RX003_POLARITY_REG"  ,	   0x11800b0001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS1_TX_RX000_POLARITY_REG"  ,	   0x11800b1001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS1_TX_RX001_POLARITY_REG"  ,	   0x11800b1001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS1_TX_RX002_POLARITY_REG"  ,	   0x11800b1001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS1_TX_RX003_POLARITY_REG"  ,	   0x11800b1001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS2_TX_RX000_POLARITY_REG"  ,	   0x11800b2001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS2_TX_RX001_POLARITY_REG"  ,	   0x11800b2001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS2_TX_RX002_POLARITY_REG"  ,	   0x11800b2001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS2_TX_RX003_POLARITY_REG"  ,	   0x11800b2001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS3_TX_RX000_POLARITY_REG"  ,	   0x11800b3001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS3_TX_RX001_POLARITY_REG"  ,	   0x11800b3001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS3_TX_RX002_POLARITY_REG"  ,	   0x11800b3001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS3_TX_RX003_POLARITY_REG"  ,	   0x11800b3001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS4_TX_RX000_POLARITY_REG"  ,	   0x11800b4001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS4_TX_RX001_POLARITY_REG"  ,	   0x11800b4001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS4_TX_RX002_POLARITY_REG"  ,	   0x11800b4001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS4_TX_RX003_POLARITY_REG"  ,	   0x11800b4001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCSX0_10GBX_STATUS_REG"      ,	   0x11800b0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCSX1_10GBX_STATUS_REG"      ,	   0x11800b1000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCSX2_10GBX_STATUS_REG"      ,	   0x11800b2000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCSX3_10GBX_STATUS_REG"      ,	   0x11800b3000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCSX4_10GBX_STATUS_REG"      ,	   0x11800b4000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCSX0_BIST_STATUS_REG"       ,	   0x11800b0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCSX1_BIST_STATUS_REG"       ,	   0x11800b1000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCSX2_BIST_STATUS_REG"       ,	   0x11800b2000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCSX3_BIST_STATUS_REG"       ,	   0x11800b3000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCSX4_BIST_STATUS_REG"       ,	   0x11800b4000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCSX0_BIT_LOCK_STATUS_REG"   ,	   0x11800b0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCSX1_BIT_LOCK_STATUS_REG"   ,	   0x11800b1000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCSX2_BIT_LOCK_STATUS_REG"   ,	   0x11800b2000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCSX3_BIT_LOCK_STATUS_REG"   ,	   0x11800b3000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCSX4_BIT_LOCK_STATUS_REG"   ,	   0x11800b4000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCSX0_CONTROL1_REG"          ,	   0x11800b0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCSX1_CONTROL1_REG"          ,	   0x11800b1000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCSX2_CONTROL1_REG"          ,	   0x11800b2000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCSX3_CONTROL1_REG"          ,	   0x11800b3000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCSX4_CONTROL1_REG"          ,	   0x11800b4000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCSX0_CONTROL2_REG"          ,	   0x11800b0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCSX1_CONTROL2_REG"          ,	   0x11800b1000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCSX2_CONTROL2_REG"          ,	   0x11800b2000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCSX3_CONTROL2_REG"          ,	   0x11800b3000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCSX4_CONTROL2_REG"          ,	   0x11800b4000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCSX0_INT_EN_REG"            ,	   0x11800b0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCSX1_INT_EN_REG"            ,	   0x11800b1000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCSX2_INT_EN_REG"            ,	   0x11800b2000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCSX3_INT_EN_REG"            ,	   0x11800b3000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCSX4_INT_EN_REG"            ,	   0x11800b4000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCSX0_INT_REG"               ,	   0x11800b0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCSX1_INT_REG"               ,	   0x11800b1000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCSX2_INT_REG"               ,	   0x11800b2000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCSX3_INT_REG"               ,	   0x11800b3000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCSX4_INT_REG"               ,	   0x11800b4000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCSX0_LOG_ANL_REG"           ,	   0x11800b0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCSX1_LOG_ANL_REG"           ,	   0x11800b1000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCSX2_LOG_ANL_REG"           ,	   0x11800b2000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCSX3_LOG_ANL_REG"           ,	   0x11800b3000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCSX4_LOG_ANL_REG"           ,	   0x11800b4000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCSX0_MISC_CTL_REG"          ,	   0x11800b0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCSX1_MISC_CTL_REG"          ,	   0x11800b1000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCSX2_MISC_CTL_REG"          ,	   0x11800b2000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCSX3_MISC_CTL_REG"          ,	   0x11800b3000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCSX4_MISC_CTL_REG"          ,	   0x11800b4000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCSX0_RX_SYNC_STATES_REG"    ,	   0x11800b0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCSX1_RX_SYNC_STATES_REG"    ,	   0x11800b1000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCSX2_RX_SYNC_STATES_REG"    ,	   0x11800b2000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCSX3_RX_SYNC_STATES_REG"    ,	   0x11800b3000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCSX4_RX_SYNC_STATES_REG"    ,	   0x11800b4000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCSX0_SPD_ABIL_REG"          ,	   0x11800b0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCSX1_SPD_ABIL_REG"          ,	   0x11800b1000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCSX2_SPD_ABIL_REG"          ,	   0x11800b2000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCSX3_SPD_ABIL_REG"          ,	   0x11800b3000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCSX4_SPD_ABIL_REG"          ,	   0x11800b4000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCSX0_STATUS1_REG"           ,	   0x11800b0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCSX1_STATUS1_REG"           ,	   0x11800b1000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCSX2_STATUS1_REG"           ,	   0x11800b2000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCSX3_STATUS1_REG"           ,	   0x11800b3000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCSX4_STATUS1_REG"           ,	   0x11800b4000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCSX0_STATUS2_REG"           ,	   0x11800b0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCSX1_STATUS2_REG"           ,	   0x11800b1000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCSX2_STATUS2_REG"           ,	   0x11800b2000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCSX3_STATUS2_REG"           ,	   0x11800b3000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCSX4_STATUS2_REG"           ,	   0x11800b4000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCSX0_TX_RX_POLARITY_REG"    ,	   0x11800b0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCSX1_TX_RX_POLARITY_REG"    ,	   0x11800b1000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCSX2_TX_RX_POLARITY_REG"    ,	   0x11800b2000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCSX3_TX_RX_POLARITY_REG"    ,	   0x11800b3000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCSX4_TX_RX_POLARITY_REG"    ,	   0x11800b4000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCSX0_TX_RX_STATES_REG"      ,	   0x11800b0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCSX1_TX_RX_STATES_REG"      ,	   0x11800b1000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCSX2_TX_RX_STATES_REG"      ,	   0x11800b2000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCSX3_TX_RX_STATES_REG"      ,	   0x11800b3000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCSX4_TX_RX_STATES_REG"      ,	   0x11800b4000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PEM0_BAR1_INDEX000"          ,	   0x11800c00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM0_BAR1_INDEX001"          ,	   0x11800c00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM0_BAR1_INDEX002"          ,	   0x11800c00000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM0_BAR1_INDEX003"          ,	   0x11800c00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM0_BAR1_INDEX004"          ,	   0x11800c00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM0_BAR1_INDEX005"          ,	   0x11800c00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM0_BAR1_INDEX006"          ,	   0x11800c00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM0_BAR1_INDEX007"          ,	   0x11800c00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM0_BAR1_INDEX008"          ,	   0x11800c00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM0_BAR1_INDEX009"          ,	   0x11800c00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM0_BAR1_INDEX010"          ,	   0x11800c00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM0_BAR1_INDEX011"          ,	   0x11800c0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM0_BAR1_INDEX012"          ,	   0x11800c0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM0_BAR1_INDEX013"          ,	   0x11800c0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM0_BAR1_INDEX014"          ,	   0x11800c0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM0_BAR1_INDEX015"          ,	   0x11800c0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM1_BAR1_INDEX000"          ,	   0x11800c10000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM1_BAR1_INDEX001"          ,	   0x11800c10000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM1_BAR1_INDEX002"          ,	   0x11800c10000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM1_BAR1_INDEX003"          ,	   0x11800c10000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM1_BAR1_INDEX004"          ,	   0x11800c10000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM1_BAR1_INDEX005"          ,	   0x11800c10000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM1_BAR1_INDEX006"          ,	   0x11800c10000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM1_BAR1_INDEX007"          ,	   0x11800c10000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM1_BAR1_INDEX008"          ,	   0x11800c10000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM1_BAR1_INDEX009"          ,	   0x11800c10000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM1_BAR1_INDEX010"          ,	   0x11800c10000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM1_BAR1_INDEX011"          ,	   0x11800c1000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM1_BAR1_INDEX012"          ,	   0x11800c1000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM1_BAR1_INDEX013"          ,	   0x11800c1000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM1_BAR1_INDEX014"          ,	   0x11800c1000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM1_BAR1_INDEX015"          ,	   0x11800c1000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PEM0_BAR2_MASK"              ,	   0x11800c0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	972},
+	{"PEM1_BAR2_MASK"              ,	   0x11800c1000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	972},
+	{"PEM0_BAR_CTL"                ,	   0x11800c0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	973},
+	{"PEM1_BAR_CTL"                ,	   0x11800c1000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	973},
+	{"PEM0_BIST_STATUS"            ,	   0x11800c0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	974},
+	{"PEM1_BIST_STATUS"            ,	   0x11800c1000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	974},
+	{"PEM0_BIST_STATUS2"           ,	   0x11800c0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	975},
+	{"PEM1_BIST_STATUS2"           ,	   0x11800c1000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	975},
+	{"PEM0_CFG_RD"                 ,	   0x11800c0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	976},
+	{"PEM1_CFG_RD"                 ,	   0x11800c1000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	976},
+	{"PEM0_CFG_WR"                 ,	   0x11800c0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	977},
+	{"PEM1_CFG_WR"                 ,	   0x11800c1000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	977},
+	{"PEM0_CPL_LUT_VALID"          ,	   0x11800c0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	978},
+	{"PEM1_CPL_LUT_VALID"          ,	   0x11800c1000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	978},
+	{"PEM0_CTL_STATUS"             ,	   0x11800c0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	979},
+	{"PEM1_CTL_STATUS"             ,	   0x11800c1000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	979},
+	{"PEM0_DBG_INFO"               ,	   0x11800c0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	980},
+	{"PEM1_DBG_INFO"               ,	   0x11800c1000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	980},
+	{"PEM0_DBG_INFO_EN"            ,	   0x11800c00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	981},
+	{"PEM1_DBG_INFO_EN"            ,	   0x11800c10000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	981},
+	{"PEM0_DIAG_STATUS"            ,	   0x11800c0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	982},
+	{"PEM1_DIAG_STATUS"            ,	   0x11800c1000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	982},
+	{"PEM0_INT_ENB"                ,	   0x11800c0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	983},
+	{"PEM1_INT_ENB"                ,	   0x11800c1000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	983},
+	{"PEM0_INT_ENB_INT"            ,	   0x11800c0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	984},
+	{"PEM1_INT_ENB_INT"            ,	   0x11800c1000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	984},
+	{"PEM0_INT_SUM"                ,	   0x11800c0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	985},
+	{"PEM1_INT_SUM"                ,	   0x11800c1000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	985},
+	{"PEM0_P2N_BAR0_START"         ,	   0x11800c0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM1_P2N_BAR0_START"         ,	   0x11800c1000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM0_P2N_BAR1_START"         ,	   0x11800c0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	987},
+	{"PEM1_P2N_BAR1_START"         ,	   0x11800c1000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	987},
+	{"PEM0_P2N_BAR2_START"         ,	   0x11800c0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"PEM1_P2N_BAR2_START"         ,	   0x11800c1000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"PEM0_P2P_BAR000_END"         ,	   0x11800c0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"PEM0_P2P_BAR001_END"         ,	   0x11800c0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"PEM0_P2P_BAR002_END"         ,	   0x11800c0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"PEM0_P2P_BAR003_END"         ,	   0x11800c0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"PEM1_P2P_BAR000_END"         ,	   0x11800c1000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"PEM1_P2P_BAR001_END"         ,	   0x11800c1000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"PEM1_P2P_BAR002_END"         ,	   0x11800c1000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"PEM1_P2P_BAR003_END"         ,	   0x11800c1000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"PEM0_P2P_BAR000_START"       ,	   0x11800c0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	990},
+	{"PEM0_P2P_BAR001_START"       ,	   0x11800c0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	990},
+	{"PEM0_P2P_BAR002_START"       ,	   0x11800c0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	990},
+	{"PEM0_P2P_BAR003_START"       ,	   0x11800c0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	990},
+	{"PEM1_P2P_BAR000_START"       ,	   0x11800c1000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	990},
+	{"PEM1_P2P_BAR001_START"       ,	   0x11800c1000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	990},
+	{"PEM1_P2P_BAR002_START"       ,	   0x11800c1000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	990},
+	{"PEM1_P2P_BAR003_START"       ,	   0x11800c1000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	990},
+	{"PEM0_TLP_CREDITS"            ,	   0x11800c0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	991},
+	{"PEM1_TLP_CREDITS"            ,	   0x11800c1000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	991},
+	{"PIP_BCK_PRS"                 ,	   0x11800a0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	992},
+	{"PIP_BIST_STATUS"             ,	   0x11800a0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	993},
+	{"PIP_CLKEN"                   ,	   0x11800a0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800a0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800a0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800a0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800a0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"PIP_DSA_SRC_GRP"             ,	   0x11800a0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	996},
+	{"PIP_DSA_VID_GRP"             ,	   0x11800a0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
+	{"PIP_FRM_LEN_CHK0"            ,	   0x11800a0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"PIP_FRM_LEN_CHK1"            ,	   0x11800a0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"PIP_GBL_CFG"                 ,	   0x11800a0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"PIP_GBL_CTL"                 ,	   0x11800a0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1000},
+	{"PIP_INT_EN"                  ,	   0x11800a0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1001},
+	{"PIP_INT_REG"                 ,	   0x11800a0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
+	{"PIP_IP_OFFSET"               ,	   0x11800a0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
+	{"PIP_PRI_TBL0"                ,	   0x11800a0004000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL1"                ,	   0x11800a0004008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL2"                ,	   0x11800a0004010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL3"                ,	   0x11800a0004018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL4"                ,	   0x11800a0004020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL5"                ,	   0x11800a0004028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL6"                ,	   0x11800a0004030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL7"                ,	   0x11800a0004038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL8"                ,	   0x11800a0004040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL9"                ,	   0x11800a0004048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL10"               ,	   0x11800a0004050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL11"               ,	   0x11800a0004058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL12"               ,	   0x11800a0004060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL13"               ,	   0x11800a0004068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL14"               ,	   0x11800a0004070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL15"               ,	   0x11800a0004078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL16"               ,	   0x11800a0004080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL17"               ,	   0x11800a0004088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL18"               ,	   0x11800a0004090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL19"               ,	   0x11800a0004098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL20"               ,	   0x11800a00040a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL21"               ,	   0x11800a00040a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL22"               ,	   0x11800a00040b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL23"               ,	   0x11800a00040b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL24"               ,	   0x11800a00040c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL25"               ,	   0x11800a00040c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL26"               ,	   0x11800a00040d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL27"               ,	   0x11800a00040d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL28"               ,	   0x11800a00040e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL29"               ,	   0x11800a00040e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL30"               ,	   0x11800a00040f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL31"               ,	   0x11800a00040f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL32"               ,	   0x11800a0004100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL33"               ,	   0x11800a0004108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL34"               ,	   0x11800a0004110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL35"               ,	   0x11800a0004118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL36"               ,	   0x11800a0004120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL37"               ,	   0x11800a0004128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL38"               ,	   0x11800a0004130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL39"               ,	   0x11800a0004138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL40"               ,	   0x11800a0004140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL41"               ,	   0x11800a0004148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL42"               ,	   0x11800a0004150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL43"               ,	   0x11800a0004158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL44"               ,	   0x11800a0004160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL45"               ,	   0x11800a0004168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL46"               ,	   0x11800a0004170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL47"               ,	   0x11800a0004178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL48"               ,	   0x11800a0004180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL49"               ,	   0x11800a0004188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL50"               ,	   0x11800a0004190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL51"               ,	   0x11800a0004198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL52"               ,	   0x11800a00041a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL53"               ,	   0x11800a00041a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL54"               ,	   0x11800a00041b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL55"               ,	   0x11800a00041b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL56"               ,	   0x11800a00041c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL57"               ,	   0x11800a00041c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL58"               ,	   0x11800a00041d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL59"               ,	   0x11800a00041d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL60"               ,	   0x11800a00041e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL61"               ,	   0x11800a00041e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL62"               ,	   0x11800a00041f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL63"               ,	   0x11800a00041f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL64"               ,	   0x11800a0004200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL65"               ,	   0x11800a0004208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL66"               ,	   0x11800a0004210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL67"               ,	   0x11800a0004218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL68"               ,	   0x11800a0004220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL69"               ,	   0x11800a0004228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL70"               ,	   0x11800a0004230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL71"               ,	   0x11800a0004238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL72"               ,	   0x11800a0004240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL73"               ,	   0x11800a0004248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL74"               ,	   0x11800a0004250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL75"               ,	   0x11800a0004258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL76"               ,	   0x11800a0004260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL77"               ,	   0x11800a0004268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL78"               ,	   0x11800a0004270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL79"               ,	   0x11800a0004278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL80"               ,	   0x11800a0004280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL81"               ,	   0x11800a0004288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL82"               ,	   0x11800a0004290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL83"               ,	   0x11800a0004298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL84"               ,	   0x11800a00042a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL85"               ,	   0x11800a00042a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL86"               ,	   0x11800a00042b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL87"               ,	   0x11800a00042b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL88"               ,	   0x11800a00042c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL89"               ,	   0x11800a00042c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL90"               ,	   0x11800a00042d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL91"               ,	   0x11800a00042d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL92"               ,	   0x11800a00042e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL93"               ,	   0x11800a00042e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL94"               ,	   0x11800a00042f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL95"               ,	   0x11800a00042f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL96"               ,	   0x11800a0004300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL97"               ,	   0x11800a0004308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL98"               ,	   0x11800a0004310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL99"               ,	   0x11800a0004318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL100"              ,	   0x11800a0004320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL101"              ,	   0x11800a0004328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL102"              ,	   0x11800a0004330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL103"              ,	   0x11800a0004338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL104"              ,	   0x11800a0004340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL105"              ,	   0x11800a0004348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL106"              ,	   0x11800a0004350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL107"              ,	   0x11800a0004358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL108"              ,	   0x11800a0004360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL109"              ,	   0x11800a0004368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL110"              ,	   0x11800a0004370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL111"              ,	   0x11800a0004378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL112"              ,	   0x11800a0004380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL113"              ,	   0x11800a0004388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL114"              ,	   0x11800a0004390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL115"              ,	   0x11800a0004398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL116"              ,	   0x11800a00043a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL117"              ,	   0x11800a00043a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL118"              ,	   0x11800a00043b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL119"              ,	   0x11800a00043b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL120"              ,	   0x11800a00043c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL121"              ,	   0x11800a00043c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL122"              ,	   0x11800a00043d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL123"              ,	   0x11800a00043d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL124"              ,	   0x11800a00043e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL125"              ,	   0x11800a00043e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL126"              ,	   0x11800a00043f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL127"              ,	   0x11800a00043f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL128"              ,	   0x11800a0004400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL129"              ,	   0x11800a0004408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL130"              ,	   0x11800a0004410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL131"              ,	   0x11800a0004418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL132"              ,	   0x11800a0004420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL133"              ,	   0x11800a0004428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL134"              ,	   0x11800a0004430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL135"              ,	   0x11800a0004438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL136"              ,	   0x11800a0004440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL137"              ,	   0x11800a0004448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL138"              ,	   0x11800a0004450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL139"              ,	   0x11800a0004458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL140"              ,	   0x11800a0004460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL141"              ,	   0x11800a0004468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL142"              ,	   0x11800a0004470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL143"              ,	   0x11800a0004478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL144"              ,	   0x11800a0004480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL145"              ,	   0x11800a0004488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL146"              ,	   0x11800a0004490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL147"              ,	   0x11800a0004498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL148"              ,	   0x11800a00044a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL149"              ,	   0x11800a00044a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL150"              ,	   0x11800a00044b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL151"              ,	   0x11800a00044b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL152"              ,	   0x11800a00044c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL153"              ,	   0x11800a00044c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL154"              ,	   0x11800a00044d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL155"              ,	   0x11800a00044d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL156"              ,	   0x11800a00044e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL157"              ,	   0x11800a00044e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL158"              ,	   0x11800a00044f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL159"              ,	   0x11800a00044f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL160"              ,	   0x11800a0004500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL161"              ,	   0x11800a0004508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL162"              ,	   0x11800a0004510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL163"              ,	   0x11800a0004518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL164"              ,	   0x11800a0004520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL165"              ,	   0x11800a0004528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL166"              ,	   0x11800a0004530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL167"              ,	   0x11800a0004538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL168"              ,	   0x11800a0004540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL169"              ,	   0x11800a0004548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL170"              ,	   0x11800a0004550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL171"              ,	   0x11800a0004558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL172"              ,	   0x11800a0004560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL173"              ,	   0x11800a0004568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL174"              ,	   0x11800a0004570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL175"              ,	   0x11800a0004578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL176"              ,	   0x11800a0004580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL177"              ,	   0x11800a0004588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL178"              ,	   0x11800a0004590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL179"              ,	   0x11800a0004598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL180"              ,	   0x11800a00045a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL181"              ,	   0x11800a00045a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL182"              ,	   0x11800a00045b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL183"              ,	   0x11800a00045b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL184"              ,	   0x11800a00045c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL185"              ,	   0x11800a00045c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL186"              ,	   0x11800a00045d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL187"              ,	   0x11800a00045d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL188"              ,	   0x11800a00045e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL189"              ,	   0x11800a00045e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL190"              ,	   0x11800a00045f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL191"              ,	   0x11800a00045f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL192"              ,	   0x11800a0004600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL193"              ,	   0x11800a0004608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL194"              ,	   0x11800a0004610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL195"              ,	   0x11800a0004618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL196"              ,	   0x11800a0004620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL197"              ,	   0x11800a0004628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL198"              ,	   0x11800a0004630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL199"              ,	   0x11800a0004638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL200"              ,	   0x11800a0004640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL201"              ,	   0x11800a0004648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL202"              ,	   0x11800a0004650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL203"              ,	   0x11800a0004658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL204"              ,	   0x11800a0004660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL205"              ,	   0x11800a0004668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL206"              ,	   0x11800a0004670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL207"              ,	   0x11800a0004678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL208"              ,	   0x11800a0004680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL209"              ,	   0x11800a0004688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL210"              ,	   0x11800a0004690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL211"              ,	   0x11800a0004698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL212"              ,	   0x11800a00046a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL213"              ,	   0x11800a00046a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL214"              ,	   0x11800a00046b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL215"              ,	   0x11800a00046b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL216"              ,	   0x11800a00046c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL217"              ,	   0x11800a00046c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL218"              ,	   0x11800a00046d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL219"              ,	   0x11800a00046d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL220"              ,	   0x11800a00046e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL221"              ,	   0x11800a00046e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL222"              ,	   0x11800a00046f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL223"              ,	   0x11800a00046f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL224"              ,	   0x11800a0004700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL225"              ,	   0x11800a0004708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL226"              ,	   0x11800a0004710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL227"              ,	   0x11800a0004718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL228"              ,	   0x11800a0004720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL229"              ,	   0x11800a0004728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL230"              ,	   0x11800a0004730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL231"              ,	   0x11800a0004738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL232"              ,	   0x11800a0004740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL233"              ,	   0x11800a0004748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL234"              ,	   0x11800a0004750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL235"              ,	   0x11800a0004758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL236"              ,	   0x11800a0004760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL237"              ,	   0x11800a0004768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL238"              ,	   0x11800a0004770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL239"              ,	   0x11800a0004778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL240"              ,	   0x11800a0004780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL241"              ,	   0x11800a0004788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL242"              ,	   0x11800a0004790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL243"              ,	   0x11800a0004798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL244"              ,	   0x11800a00047a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL245"              ,	   0x11800a00047a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL246"              ,	   0x11800a00047b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL247"              ,	   0x11800a00047b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL248"              ,	   0x11800a00047c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL249"              ,	   0x11800a00047c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL250"              ,	   0x11800a00047d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL251"              ,	   0x11800a00047d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL252"              ,	   0x11800a00047e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL253"              ,	   0x11800a00047e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL254"              ,	   0x11800a00047f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRI_TBL255"              ,	   0x11800a00047f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PIP_PRT_CFG0"                ,	   0x11800a0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG1"                ,	   0x11800a0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG2"                ,	   0x11800a0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG3"                ,	   0x11800a0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG4"                ,	   0x11800a0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG5"                ,	   0x11800a0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG6"                ,	   0x11800a0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG7"                ,	   0x11800a0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG8"                ,	   0x11800a0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG9"                ,	   0x11800a0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG10"               ,	   0x11800a0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG11"               ,	   0x11800a0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG12"               ,	   0x11800a0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG13"               ,	   0x11800a0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG14"               ,	   0x11800a0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG15"               ,	   0x11800a0000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG16"               ,	   0x11800a0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG17"               ,	   0x11800a0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG18"               ,	   0x11800a0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG19"               ,	   0x11800a0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG20"               ,	   0x11800a00002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG21"               ,	   0x11800a00002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG22"               ,	   0x11800a00002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG23"               ,	   0x11800a00002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG24"               ,	   0x11800a00002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG25"               ,	   0x11800a00002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG26"               ,	   0x11800a00002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG27"               ,	   0x11800a00002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG28"               ,	   0x11800a00002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG29"               ,	   0x11800a00002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG30"               ,	   0x11800a00002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG31"               ,	   0x11800a00002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG32"               ,	   0x11800a0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG33"               ,	   0x11800a0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG34"               ,	   0x11800a0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG35"               ,	   0x11800a0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG36"               ,	   0x11800a0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG37"               ,	   0x11800a0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG38"               ,	   0x11800a0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG39"               ,	   0x11800a0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG40"               ,	   0x11800a0000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG41"               ,	   0x11800a0000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG42"               ,	   0x11800a0000350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG43"               ,	   0x11800a0000358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG44"               ,	   0x11800a0000360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG45"               ,	   0x11800a0000368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG46"               ,	   0x11800a0000370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG47"               ,	   0x11800a0000378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG48"               ,	   0x11800a0000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG49"               ,	   0x11800a0000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG50"               ,	   0x11800a0000390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG51"               ,	   0x11800a0000398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG52"               ,	   0x11800a00003a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG53"               ,	   0x11800a00003a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG54"               ,	   0x11800a00003b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG55"               ,	   0x11800a00003b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG56"               ,	   0x11800a00003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG57"               ,	   0x11800a00003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG58"               ,	   0x11800a00003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG59"               ,	   0x11800a00003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG60"               ,	   0x11800a00003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG61"               ,	   0x11800a00003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG62"               ,	   0x11800a00003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFG63"               ,	   0x11800a00003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PIP_PRT_CFGB0"               ,	   0x11800a0008000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB1"               ,	   0x11800a0008008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB2"               ,	   0x11800a0008010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB3"               ,	   0x11800a0008018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB4"               ,	   0x11800a0008020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB5"               ,	   0x11800a0008028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB6"               ,	   0x11800a0008030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB7"               ,	   0x11800a0008038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB8"               ,	   0x11800a0008040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB9"               ,	   0x11800a0008048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB10"              ,	   0x11800a0008050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB11"              ,	   0x11800a0008058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB12"              ,	   0x11800a0008060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB13"              ,	   0x11800a0008068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB14"              ,	   0x11800a0008070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB15"              ,	   0x11800a0008078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB16"              ,	   0x11800a0008080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB17"              ,	   0x11800a0008088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB18"              ,	   0x11800a0008090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB19"              ,	   0x11800a0008098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB20"              ,	   0x11800a00080a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB21"              ,	   0x11800a00080a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB22"              ,	   0x11800a00080b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB23"              ,	   0x11800a00080b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB24"              ,	   0x11800a00080c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB25"              ,	   0x11800a00080c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB26"              ,	   0x11800a00080d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB27"              ,	   0x11800a00080d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB28"              ,	   0x11800a00080e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB29"              ,	   0x11800a00080e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB30"              ,	   0x11800a00080f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB31"              ,	   0x11800a00080f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB32"              ,	   0x11800a0008100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB33"              ,	   0x11800a0008108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB34"              ,	   0x11800a0008110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB35"              ,	   0x11800a0008118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB36"              ,	   0x11800a0008120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB37"              ,	   0x11800a0008128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB38"              ,	   0x11800a0008130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB39"              ,	   0x11800a0008138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB40"              ,	   0x11800a0008140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB41"              ,	   0x11800a0008148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB42"              ,	   0x11800a0008150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB43"              ,	   0x11800a0008158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB44"              ,	   0x11800a0008160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB45"              ,	   0x11800a0008168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB46"              ,	   0x11800a0008170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB47"              ,	   0x11800a0008178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB48"              ,	   0x11800a0008180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB49"              ,	   0x11800a0008188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB50"              ,	   0x11800a0008190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB51"              ,	   0x11800a0008198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB52"              ,	   0x11800a00081a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB53"              ,	   0x11800a00081a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB54"              ,	   0x11800a00081b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB55"              ,	   0x11800a00081b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB56"              ,	   0x11800a00081c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB57"              ,	   0x11800a00081c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB58"              ,	   0x11800a00081d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB59"              ,	   0x11800a00081d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB60"              ,	   0x11800a00081e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB61"              ,	   0x11800a00081e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB62"              ,	   0x11800a00081f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_CFGB63"              ,	   0x11800a00081f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PIP_PRT_TAG0"                ,	   0x11800a0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG1"                ,	   0x11800a0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG2"                ,	   0x11800a0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG3"                ,	   0x11800a0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG4"                ,	   0x11800a0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG5"                ,	   0x11800a0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG6"                ,	   0x11800a0000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG7"                ,	   0x11800a0000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG8"                ,	   0x11800a0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG9"                ,	   0x11800a0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG10"               ,	   0x11800a0000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG11"               ,	   0x11800a0000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG12"               ,	   0x11800a0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG13"               ,	   0x11800a0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG14"               ,	   0x11800a0000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG15"               ,	   0x11800a0000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG16"               ,	   0x11800a0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG17"               ,	   0x11800a0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG18"               ,	   0x11800a0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG19"               ,	   0x11800a0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG20"               ,	   0x11800a00004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG21"               ,	   0x11800a00004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG22"               ,	   0x11800a00004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG23"               ,	   0x11800a00004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG24"               ,	   0x11800a00004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG25"               ,	   0x11800a00004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG26"               ,	   0x11800a00004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG27"               ,	   0x11800a00004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG28"               ,	   0x11800a00004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG29"               ,	   0x11800a00004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG30"               ,	   0x11800a00004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG31"               ,	   0x11800a00004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG32"               ,	   0x11800a0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG33"               ,	   0x11800a0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG34"               ,	   0x11800a0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG35"               ,	   0x11800a0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG36"               ,	   0x11800a0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG37"               ,	   0x11800a0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG38"               ,	   0x11800a0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG39"               ,	   0x11800a0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG40"               ,	   0x11800a0000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG41"               ,	   0x11800a0000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG42"               ,	   0x11800a0000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG43"               ,	   0x11800a0000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG44"               ,	   0x11800a0000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG45"               ,	   0x11800a0000568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG46"               ,	   0x11800a0000570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG47"               ,	   0x11800a0000578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG48"               ,	   0x11800a0000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG49"               ,	   0x11800a0000588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG50"               ,	   0x11800a0000590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG51"               ,	   0x11800a0000598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG52"               ,	   0x11800a00005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG53"               ,	   0x11800a00005a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG54"               ,	   0x11800a00005b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG55"               ,	   0x11800a00005b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG56"               ,	   0x11800a00005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG57"               ,	   0x11800a00005c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG58"               ,	   0x11800a00005d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG59"               ,	   0x11800a00005d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG60"               ,	   0x11800a00005e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG61"               ,	   0x11800a00005e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG62"               ,	   0x11800a00005f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_PRT_TAG63"               ,	   0x11800a00005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_QOS_WATCH0"              ,	   0x11800a0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"PIP_QOS_WATCH1"              ,	   0x11800a0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"PIP_QOS_WATCH2"              ,	   0x11800a0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"PIP_QOS_WATCH3"              ,	   0x11800a0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"PIP_QOS_WATCH4"              ,	   0x11800a0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"PIP_QOS_WATCH5"              ,	   0x11800a0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"PIP_QOS_WATCH6"              ,	   0x11800a0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"PIP_QOS_WATCH7"              ,	   0x11800a0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"PIP_RAW_WORD"                ,	   0x11800a00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1009},
+	{"PIP_SFT_RST"                 ,	   0x11800a0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"PIP_STAT0_0"                 ,	   0x11800a0040000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_1"                 ,	   0x11800a0040080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_2"                 ,	   0x11800a0040100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_3"                 ,	   0x11800a0040180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_4"                 ,	   0x11800a0040200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_5"                 ,	   0x11800a0040280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_6"                 ,	   0x11800a0040300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_7"                 ,	   0x11800a0040380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_8"                 ,	   0x11800a0040400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_9"                 ,	   0x11800a0040480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_10"                ,	   0x11800a0040500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_11"                ,	   0x11800a0040580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_12"                ,	   0x11800a0040600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_13"                ,	   0x11800a0040680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_14"                ,	   0x11800a0040700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_15"                ,	   0x11800a0040780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_16"                ,	   0x11800a0040800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_17"                ,	   0x11800a0040880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_18"                ,	   0x11800a0040900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_19"                ,	   0x11800a0040980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_20"                ,	   0x11800a0040a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_21"                ,	   0x11800a0040a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_22"                ,	   0x11800a0040b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_23"                ,	   0x11800a0040b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_24"                ,	   0x11800a0040c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_25"                ,	   0x11800a0040c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_26"                ,	   0x11800a0040d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_27"                ,	   0x11800a0040d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_28"                ,	   0x11800a0040e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_29"                ,	   0x11800a0040e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_30"                ,	   0x11800a0040f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_31"                ,	   0x11800a0040f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_32"                ,	   0x11800a0041000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_33"                ,	   0x11800a0041080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_34"                ,	   0x11800a0041100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_35"                ,	   0x11800a0041180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_36"                ,	   0x11800a0041200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_37"                ,	   0x11800a0041280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_38"                ,	   0x11800a0041300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_39"                ,	   0x11800a0041380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_40"                ,	   0x11800a0041400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_41"                ,	   0x11800a0041480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_42"                ,	   0x11800a0041500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_43"                ,	   0x11800a0041580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_44"                ,	   0x11800a0041600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_45"                ,	   0x11800a0041680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_46"                ,	   0x11800a0041700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_47"                ,	   0x11800a0041780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_48"                ,	   0x11800a0041800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_49"                ,	   0x11800a0041880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_50"                ,	   0x11800a0041900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_51"                ,	   0x11800a0041980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_52"                ,	   0x11800a0041a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_53"                ,	   0x11800a0041a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_54"                ,	   0x11800a0041b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_55"                ,	   0x11800a0041b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_56"                ,	   0x11800a0041c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_57"                ,	   0x11800a0041c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_58"                ,	   0x11800a0041d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_59"                ,	   0x11800a0041d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_60"                ,	   0x11800a0041e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_61"                ,	   0x11800a0041e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_62"                ,	   0x11800a0041f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT0_63"                ,	   0x11800a0041f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_STAT10_0"                ,	   0x11800a0040050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_1"                ,	   0x11800a00400d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_2"                ,	   0x11800a0040150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_3"                ,	   0x11800a00401d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_4"                ,	   0x11800a0040250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_5"                ,	   0x11800a00402d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_6"                ,	   0x11800a0040350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_7"                ,	   0x11800a00403d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_8"                ,	   0x11800a0040450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_9"                ,	   0x11800a00404d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_10"               ,	   0x11800a0040550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_11"               ,	   0x11800a00405d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_12"               ,	   0x11800a0040650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_13"               ,	   0x11800a00406d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_14"               ,	   0x11800a0040750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_15"               ,	   0x11800a00407d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_16"               ,	   0x11800a0040850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_17"               ,	   0x11800a00408d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_18"               ,	   0x11800a0040950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_19"               ,	   0x11800a00409d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_20"               ,	   0x11800a0040a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_21"               ,	   0x11800a0040ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_22"               ,	   0x11800a0040b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_23"               ,	   0x11800a0040bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_24"               ,	   0x11800a0040c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_25"               ,	   0x11800a0040cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_26"               ,	   0x11800a0040d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_27"               ,	   0x11800a0040dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_28"               ,	   0x11800a0040e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_29"               ,	   0x11800a0040ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_30"               ,	   0x11800a0040f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_31"               ,	   0x11800a0040fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_32"               ,	   0x11800a0041050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_33"               ,	   0x11800a00410d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_34"               ,	   0x11800a0041150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_35"               ,	   0x11800a00411d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_36"               ,	   0x11800a0041250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_37"               ,	   0x11800a00412d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_38"               ,	   0x11800a0041350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_39"               ,	   0x11800a00413d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_40"               ,	   0x11800a0041450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_41"               ,	   0x11800a00414d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_42"               ,	   0x11800a0041550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_43"               ,	   0x11800a00415d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_44"               ,	   0x11800a0041650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_45"               ,	   0x11800a00416d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_46"               ,	   0x11800a0041750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_47"               ,	   0x11800a00417d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_48"               ,	   0x11800a0041850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_49"               ,	   0x11800a00418d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_50"               ,	   0x11800a0041950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_51"               ,	   0x11800a00419d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_52"               ,	   0x11800a0041a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_53"               ,	   0x11800a0041ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_54"               ,	   0x11800a0041b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_55"               ,	   0x11800a0041bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_56"               ,	   0x11800a0041c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_57"               ,	   0x11800a0041cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_58"               ,	   0x11800a0041d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_59"               ,	   0x11800a0041dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_60"               ,	   0x11800a0041e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_61"               ,	   0x11800a0041ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_62"               ,	   0x11800a0041f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT10_63"               ,	   0x11800a0041fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_STAT11_0"                ,	   0x11800a0040058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_1"                ,	   0x11800a00400d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_2"                ,	   0x11800a0040158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_3"                ,	   0x11800a00401d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_4"                ,	   0x11800a0040258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_5"                ,	   0x11800a00402d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_6"                ,	   0x11800a0040358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_7"                ,	   0x11800a00403d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_8"                ,	   0x11800a0040458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_9"                ,	   0x11800a00404d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_10"               ,	   0x11800a0040558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_11"               ,	   0x11800a00405d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_12"               ,	   0x11800a0040658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_13"               ,	   0x11800a00406d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_14"               ,	   0x11800a0040758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_15"               ,	   0x11800a00407d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_16"               ,	   0x11800a0040858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_17"               ,	   0x11800a00408d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_18"               ,	   0x11800a0040958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_19"               ,	   0x11800a00409d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_20"               ,	   0x11800a0040a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_21"               ,	   0x11800a0040ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_22"               ,	   0x11800a0040b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_23"               ,	   0x11800a0040bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_24"               ,	   0x11800a0040c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_25"               ,	   0x11800a0040cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_26"               ,	   0x11800a0040d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_27"               ,	   0x11800a0040dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_28"               ,	   0x11800a0040e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_29"               ,	   0x11800a0040ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_30"               ,	   0x11800a0040f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_31"               ,	   0x11800a0040fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_32"               ,	   0x11800a0041058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_33"               ,	   0x11800a00410d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_34"               ,	   0x11800a0041158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_35"               ,	   0x11800a00411d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_36"               ,	   0x11800a0041258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_37"               ,	   0x11800a00412d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_38"               ,	   0x11800a0041358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_39"               ,	   0x11800a00413d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_40"               ,	   0x11800a0041458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_41"               ,	   0x11800a00414d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_42"               ,	   0x11800a0041558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_43"               ,	   0x11800a00415d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_44"               ,	   0x11800a0041658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_45"               ,	   0x11800a00416d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_46"               ,	   0x11800a0041758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_47"               ,	   0x11800a00417d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_48"               ,	   0x11800a0041858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_49"               ,	   0x11800a00418d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_50"               ,	   0x11800a0041958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_51"               ,	   0x11800a00419d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_52"               ,	   0x11800a0041a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_53"               ,	   0x11800a0041ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_54"               ,	   0x11800a0041b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_55"               ,	   0x11800a0041bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_56"               ,	   0x11800a0041c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_57"               ,	   0x11800a0041cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_58"               ,	   0x11800a0041d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_59"               ,	   0x11800a0041dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_60"               ,	   0x11800a0041e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_61"               ,	   0x11800a0041ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_62"               ,	   0x11800a0041f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT11_63"               ,	   0x11800a0041fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_STAT1_0"                 ,	   0x11800a0040008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_1"                 ,	   0x11800a0040088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_2"                 ,	   0x11800a0040108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_3"                 ,	   0x11800a0040188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_4"                 ,	   0x11800a0040208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_5"                 ,	   0x11800a0040288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_6"                 ,	   0x11800a0040308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_7"                 ,	   0x11800a0040388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_8"                 ,	   0x11800a0040408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_9"                 ,	   0x11800a0040488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_10"                ,	   0x11800a0040508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_11"                ,	   0x11800a0040588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_12"                ,	   0x11800a0040608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_13"                ,	   0x11800a0040688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_14"                ,	   0x11800a0040708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_15"                ,	   0x11800a0040788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_16"                ,	   0x11800a0040808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_17"                ,	   0x11800a0040888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_18"                ,	   0x11800a0040908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_19"                ,	   0x11800a0040988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_20"                ,	   0x11800a0040a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_21"                ,	   0x11800a0040a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_22"                ,	   0x11800a0040b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_23"                ,	   0x11800a0040b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_24"                ,	   0x11800a0040c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_25"                ,	   0x11800a0040c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_26"                ,	   0x11800a0040d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_27"                ,	   0x11800a0040d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_28"                ,	   0x11800a0040e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_29"                ,	   0x11800a0040e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_30"                ,	   0x11800a0040f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_31"                ,	   0x11800a0040f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_32"                ,	   0x11800a0041008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_33"                ,	   0x11800a0041088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_34"                ,	   0x11800a0041108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_35"                ,	   0x11800a0041188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_36"                ,	   0x11800a0041208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_37"                ,	   0x11800a0041288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_38"                ,	   0x11800a0041308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_39"                ,	   0x11800a0041388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_40"                ,	   0x11800a0041408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_41"                ,	   0x11800a0041488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_42"                ,	   0x11800a0041508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_43"                ,	   0x11800a0041588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_44"                ,	   0x11800a0041608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_45"                ,	   0x11800a0041688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_46"                ,	   0x11800a0041708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_47"                ,	   0x11800a0041788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_48"                ,	   0x11800a0041808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_49"                ,	   0x11800a0041888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_50"                ,	   0x11800a0041908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_51"                ,	   0x11800a0041988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_52"                ,	   0x11800a0041a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_53"                ,	   0x11800a0041a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_54"                ,	   0x11800a0041b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_55"                ,	   0x11800a0041b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_56"                ,	   0x11800a0041c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_57"                ,	   0x11800a0041c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_58"                ,	   0x11800a0041d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_59"                ,	   0x11800a0041d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_60"                ,	   0x11800a0041e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_61"                ,	   0x11800a0041e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_62"                ,	   0x11800a0041f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT1_63"                ,	   0x11800a0041f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_STAT2_0"                 ,	   0x11800a0040010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_1"                 ,	   0x11800a0040090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_2"                 ,	   0x11800a0040110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_3"                 ,	   0x11800a0040190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_4"                 ,	   0x11800a0040210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_5"                 ,	   0x11800a0040290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_6"                 ,	   0x11800a0040310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_7"                 ,	   0x11800a0040390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_8"                 ,	   0x11800a0040410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_9"                 ,	   0x11800a0040490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_10"                ,	   0x11800a0040510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_11"                ,	   0x11800a0040590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_12"                ,	   0x11800a0040610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_13"                ,	   0x11800a0040690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_14"                ,	   0x11800a0040710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_15"                ,	   0x11800a0040790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_16"                ,	   0x11800a0040810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_17"                ,	   0x11800a0040890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_18"                ,	   0x11800a0040910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_19"                ,	   0x11800a0040990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_20"                ,	   0x11800a0040a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_21"                ,	   0x11800a0040a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_22"                ,	   0x11800a0040b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_23"                ,	   0x11800a0040b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_24"                ,	   0x11800a0040c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_25"                ,	   0x11800a0040c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_26"                ,	   0x11800a0040d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_27"                ,	   0x11800a0040d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_28"                ,	   0x11800a0040e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_29"                ,	   0x11800a0040e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_30"                ,	   0x11800a0040f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_31"                ,	   0x11800a0040f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_32"                ,	   0x11800a0041010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_33"                ,	   0x11800a0041090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_34"                ,	   0x11800a0041110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_35"                ,	   0x11800a0041190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_36"                ,	   0x11800a0041210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_37"                ,	   0x11800a0041290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_38"                ,	   0x11800a0041310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_39"                ,	   0x11800a0041390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_40"                ,	   0x11800a0041410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_41"                ,	   0x11800a0041490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_42"                ,	   0x11800a0041510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_43"                ,	   0x11800a0041590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_44"                ,	   0x11800a0041610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_45"                ,	   0x11800a0041690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_46"                ,	   0x11800a0041710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_47"                ,	   0x11800a0041790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_48"                ,	   0x11800a0041810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_49"                ,	   0x11800a0041890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_50"                ,	   0x11800a0041910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_51"                ,	   0x11800a0041990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_52"                ,	   0x11800a0041a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_53"                ,	   0x11800a0041a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_54"                ,	   0x11800a0041b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_55"                ,	   0x11800a0041b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_56"                ,	   0x11800a0041c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_57"                ,	   0x11800a0041c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_58"                ,	   0x11800a0041d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_59"                ,	   0x11800a0041d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_60"                ,	   0x11800a0041e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_61"                ,	   0x11800a0041e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_62"                ,	   0x11800a0041f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT2_63"                ,	   0x11800a0041f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_STAT3_0"                 ,	   0x11800a0040018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_1"                 ,	   0x11800a0040098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_2"                 ,	   0x11800a0040118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_3"                 ,	   0x11800a0040198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_4"                 ,	   0x11800a0040218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_5"                 ,	   0x11800a0040298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_6"                 ,	   0x11800a0040318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_7"                 ,	   0x11800a0040398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_8"                 ,	   0x11800a0040418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_9"                 ,	   0x11800a0040498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_10"                ,	   0x11800a0040518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_11"                ,	   0x11800a0040598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_12"                ,	   0x11800a0040618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_13"                ,	   0x11800a0040698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_14"                ,	   0x11800a0040718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_15"                ,	   0x11800a0040798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_16"                ,	   0x11800a0040818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_17"                ,	   0x11800a0040898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_18"                ,	   0x11800a0040918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_19"                ,	   0x11800a0040998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_20"                ,	   0x11800a0040a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_21"                ,	   0x11800a0040a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_22"                ,	   0x11800a0040b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_23"                ,	   0x11800a0040b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_24"                ,	   0x11800a0040c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_25"                ,	   0x11800a0040c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_26"                ,	   0x11800a0040d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_27"                ,	   0x11800a0040d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_28"                ,	   0x11800a0040e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_29"                ,	   0x11800a0040e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_30"                ,	   0x11800a0040f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_31"                ,	   0x11800a0040f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_32"                ,	   0x11800a0041018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_33"                ,	   0x11800a0041098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_34"                ,	   0x11800a0041118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_35"                ,	   0x11800a0041198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_36"                ,	   0x11800a0041218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_37"                ,	   0x11800a0041298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_38"                ,	   0x11800a0041318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_39"                ,	   0x11800a0041398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_40"                ,	   0x11800a0041418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_41"                ,	   0x11800a0041498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_42"                ,	   0x11800a0041518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_43"                ,	   0x11800a0041598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_44"                ,	   0x11800a0041618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_45"                ,	   0x11800a0041698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_46"                ,	   0x11800a0041718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_47"                ,	   0x11800a0041798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_48"                ,	   0x11800a0041818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_49"                ,	   0x11800a0041898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_50"                ,	   0x11800a0041918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_51"                ,	   0x11800a0041998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_52"                ,	   0x11800a0041a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_53"                ,	   0x11800a0041a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_54"                ,	   0x11800a0041b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_55"                ,	   0x11800a0041b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_56"                ,	   0x11800a0041c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_57"                ,	   0x11800a0041c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_58"                ,	   0x11800a0041d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_59"                ,	   0x11800a0041d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_60"                ,	   0x11800a0041e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_61"                ,	   0x11800a0041e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_62"                ,	   0x11800a0041f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT3_63"                ,	   0x11800a0041f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_STAT4_0"                 ,	   0x11800a0040020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_1"                 ,	   0x11800a00400a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_2"                 ,	   0x11800a0040120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_3"                 ,	   0x11800a00401a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_4"                 ,	   0x11800a0040220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_5"                 ,	   0x11800a00402a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_6"                 ,	   0x11800a0040320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_7"                 ,	   0x11800a00403a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_8"                 ,	   0x11800a0040420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_9"                 ,	   0x11800a00404a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_10"                ,	   0x11800a0040520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_11"                ,	   0x11800a00405a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_12"                ,	   0x11800a0040620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_13"                ,	   0x11800a00406a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_14"                ,	   0x11800a0040720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_15"                ,	   0x11800a00407a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_16"                ,	   0x11800a0040820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_17"                ,	   0x11800a00408a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_18"                ,	   0x11800a0040920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_19"                ,	   0x11800a00409a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_20"                ,	   0x11800a0040a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_21"                ,	   0x11800a0040aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_22"                ,	   0x11800a0040b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_23"                ,	   0x11800a0040ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_24"                ,	   0x11800a0040c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_25"                ,	   0x11800a0040ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_26"                ,	   0x11800a0040d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_27"                ,	   0x11800a0040da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_28"                ,	   0x11800a0040e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_29"                ,	   0x11800a0040ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_30"                ,	   0x11800a0040f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_31"                ,	   0x11800a0040fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_32"                ,	   0x11800a0041020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_33"                ,	   0x11800a00410a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_34"                ,	   0x11800a0041120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_35"                ,	   0x11800a00411a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_36"                ,	   0x11800a0041220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_37"                ,	   0x11800a00412a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_38"                ,	   0x11800a0041320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_39"                ,	   0x11800a00413a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_40"                ,	   0x11800a0041420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_41"                ,	   0x11800a00414a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_42"                ,	   0x11800a0041520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_43"                ,	   0x11800a00415a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_44"                ,	   0x11800a0041620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_45"                ,	   0x11800a00416a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_46"                ,	   0x11800a0041720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_47"                ,	   0x11800a00417a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_48"                ,	   0x11800a0041820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_49"                ,	   0x11800a00418a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_50"                ,	   0x11800a0041920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_51"                ,	   0x11800a00419a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_52"                ,	   0x11800a0041a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_53"                ,	   0x11800a0041aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_54"                ,	   0x11800a0041b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_55"                ,	   0x11800a0041ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_56"                ,	   0x11800a0041c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_57"                ,	   0x11800a0041ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_58"                ,	   0x11800a0041d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_59"                ,	   0x11800a0041da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_60"                ,	   0x11800a0041e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_61"                ,	   0x11800a0041ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_62"                ,	   0x11800a0041f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT4_63"                ,	   0x11800a0041fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_STAT5_0"                 ,	   0x11800a0040028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_1"                 ,	   0x11800a00400a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_2"                 ,	   0x11800a0040128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_3"                 ,	   0x11800a00401a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_4"                 ,	   0x11800a0040228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_5"                 ,	   0x11800a00402a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_6"                 ,	   0x11800a0040328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_7"                 ,	   0x11800a00403a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_8"                 ,	   0x11800a0040428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_9"                 ,	   0x11800a00404a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_10"                ,	   0x11800a0040528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_11"                ,	   0x11800a00405a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_12"                ,	   0x11800a0040628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_13"                ,	   0x11800a00406a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_14"                ,	   0x11800a0040728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_15"                ,	   0x11800a00407a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_16"                ,	   0x11800a0040828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_17"                ,	   0x11800a00408a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_18"                ,	   0x11800a0040928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_19"                ,	   0x11800a00409a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_20"                ,	   0x11800a0040a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_21"                ,	   0x11800a0040aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_22"                ,	   0x11800a0040b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_23"                ,	   0x11800a0040ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_24"                ,	   0x11800a0040c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_25"                ,	   0x11800a0040ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_26"                ,	   0x11800a0040d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_27"                ,	   0x11800a0040da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_28"                ,	   0x11800a0040e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_29"                ,	   0x11800a0040ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_30"                ,	   0x11800a0040f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_31"                ,	   0x11800a0040fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_32"                ,	   0x11800a0041028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_33"                ,	   0x11800a00410a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_34"                ,	   0x11800a0041128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_35"                ,	   0x11800a00411a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_36"                ,	   0x11800a0041228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_37"                ,	   0x11800a00412a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_38"                ,	   0x11800a0041328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_39"                ,	   0x11800a00413a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_40"                ,	   0x11800a0041428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_41"                ,	   0x11800a00414a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_42"                ,	   0x11800a0041528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_43"                ,	   0x11800a00415a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_44"                ,	   0x11800a0041628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_45"                ,	   0x11800a00416a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_46"                ,	   0x11800a0041728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_47"                ,	   0x11800a00417a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_48"                ,	   0x11800a0041828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_49"                ,	   0x11800a00418a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_50"                ,	   0x11800a0041928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_51"                ,	   0x11800a00419a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_52"                ,	   0x11800a0041a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_53"                ,	   0x11800a0041aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_54"                ,	   0x11800a0041b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_55"                ,	   0x11800a0041ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_56"                ,	   0x11800a0041c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_57"                ,	   0x11800a0041ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_58"                ,	   0x11800a0041d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_59"                ,	   0x11800a0041da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_60"                ,	   0x11800a0041e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_61"                ,	   0x11800a0041ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_62"                ,	   0x11800a0041f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT5_63"                ,	   0x11800a0041fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_STAT6_0"                 ,	   0x11800a0040030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_1"                 ,	   0x11800a00400b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_2"                 ,	   0x11800a0040130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_3"                 ,	   0x11800a00401b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_4"                 ,	   0x11800a0040230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_5"                 ,	   0x11800a00402b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_6"                 ,	   0x11800a0040330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_7"                 ,	   0x11800a00403b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_8"                 ,	   0x11800a0040430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_9"                 ,	   0x11800a00404b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_10"                ,	   0x11800a0040530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_11"                ,	   0x11800a00405b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_12"                ,	   0x11800a0040630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_13"                ,	   0x11800a00406b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_14"                ,	   0x11800a0040730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_15"                ,	   0x11800a00407b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_16"                ,	   0x11800a0040830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_17"                ,	   0x11800a00408b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_18"                ,	   0x11800a0040930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_19"                ,	   0x11800a00409b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_20"                ,	   0x11800a0040a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_21"                ,	   0x11800a0040ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_22"                ,	   0x11800a0040b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_23"                ,	   0x11800a0040bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_24"                ,	   0x11800a0040c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_25"                ,	   0x11800a0040cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_26"                ,	   0x11800a0040d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_27"                ,	   0x11800a0040db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_28"                ,	   0x11800a0040e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_29"                ,	   0x11800a0040eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_30"                ,	   0x11800a0040f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_31"                ,	   0x11800a0040fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_32"                ,	   0x11800a0041030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_33"                ,	   0x11800a00410b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_34"                ,	   0x11800a0041130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_35"                ,	   0x11800a00411b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_36"                ,	   0x11800a0041230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_37"                ,	   0x11800a00412b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_38"                ,	   0x11800a0041330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_39"                ,	   0x11800a00413b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_40"                ,	   0x11800a0041430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_41"                ,	   0x11800a00414b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_42"                ,	   0x11800a0041530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_43"                ,	   0x11800a00415b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_44"                ,	   0x11800a0041630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_45"                ,	   0x11800a00416b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_46"                ,	   0x11800a0041730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_47"                ,	   0x11800a00417b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_48"                ,	   0x11800a0041830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_49"                ,	   0x11800a00418b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_50"                ,	   0x11800a0041930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_51"                ,	   0x11800a00419b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_52"                ,	   0x11800a0041a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_53"                ,	   0x11800a0041ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_54"                ,	   0x11800a0041b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_55"                ,	   0x11800a0041bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_56"                ,	   0x11800a0041c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_57"                ,	   0x11800a0041cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_58"                ,	   0x11800a0041d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_59"                ,	   0x11800a0041db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_60"                ,	   0x11800a0041e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_61"                ,	   0x11800a0041eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_62"                ,	   0x11800a0041f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT6_63"                ,	   0x11800a0041fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_STAT7_0"                 ,	   0x11800a0040038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_1"                 ,	   0x11800a00400b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_2"                 ,	   0x11800a0040138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_3"                 ,	   0x11800a00401b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_4"                 ,	   0x11800a0040238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_5"                 ,	   0x11800a00402b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_6"                 ,	   0x11800a0040338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_7"                 ,	   0x11800a00403b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_8"                 ,	   0x11800a0040438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_9"                 ,	   0x11800a00404b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_10"                ,	   0x11800a0040538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_11"                ,	   0x11800a00405b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_12"                ,	   0x11800a0040638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_13"                ,	   0x11800a00406b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_14"                ,	   0x11800a0040738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_15"                ,	   0x11800a00407b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_16"                ,	   0x11800a0040838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_17"                ,	   0x11800a00408b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_18"                ,	   0x11800a0040938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_19"                ,	   0x11800a00409b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_20"                ,	   0x11800a0040a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_21"                ,	   0x11800a0040ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_22"                ,	   0x11800a0040b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_23"                ,	   0x11800a0040bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_24"                ,	   0x11800a0040c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_25"                ,	   0x11800a0040cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_26"                ,	   0x11800a0040d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_27"                ,	   0x11800a0040db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_28"                ,	   0x11800a0040e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_29"                ,	   0x11800a0040eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_30"                ,	   0x11800a0040f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_31"                ,	   0x11800a0040fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_32"                ,	   0x11800a0041038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_33"                ,	   0x11800a00410b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_34"                ,	   0x11800a0041138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_35"                ,	   0x11800a00411b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_36"                ,	   0x11800a0041238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_37"                ,	   0x11800a00412b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_38"                ,	   0x11800a0041338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_39"                ,	   0x11800a00413b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_40"                ,	   0x11800a0041438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_41"                ,	   0x11800a00414b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_42"                ,	   0x11800a0041538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_43"                ,	   0x11800a00415b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_44"                ,	   0x11800a0041638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_45"                ,	   0x11800a00416b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_46"                ,	   0x11800a0041738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_47"                ,	   0x11800a00417b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_48"                ,	   0x11800a0041838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_49"                ,	   0x11800a00418b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_50"                ,	   0x11800a0041938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_51"                ,	   0x11800a00419b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_52"                ,	   0x11800a0041a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_53"                ,	   0x11800a0041ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_54"                ,	   0x11800a0041b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_55"                ,	   0x11800a0041bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_56"                ,	   0x11800a0041c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_57"                ,	   0x11800a0041cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_58"                ,	   0x11800a0041d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_59"                ,	   0x11800a0041db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_60"                ,	   0x11800a0041e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_61"                ,	   0x11800a0041eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_62"                ,	   0x11800a0041f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT7_63"                ,	   0x11800a0041fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_STAT8_0"                 ,	   0x11800a0040040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_1"                 ,	   0x11800a00400c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_2"                 ,	   0x11800a0040140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_3"                 ,	   0x11800a00401c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_4"                 ,	   0x11800a0040240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_5"                 ,	   0x11800a00402c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_6"                 ,	   0x11800a0040340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_7"                 ,	   0x11800a00403c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_8"                 ,	   0x11800a0040440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_9"                 ,	   0x11800a00404c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_10"                ,	   0x11800a0040540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_11"                ,	   0x11800a00405c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_12"                ,	   0x11800a0040640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_13"                ,	   0x11800a00406c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_14"                ,	   0x11800a0040740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_15"                ,	   0x11800a00407c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_16"                ,	   0x11800a0040840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_17"                ,	   0x11800a00408c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_18"                ,	   0x11800a0040940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_19"                ,	   0x11800a00409c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_20"                ,	   0x11800a0040a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_21"                ,	   0x11800a0040ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_22"                ,	   0x11800a0040b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_23"                ,	   0x11800a0040bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_24"                ,	   0x11800a0040c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_25"                ,	   0x11800a0040cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_26"                ,	   0x11800a0040d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_27"                ,	   0x11800a0040dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_28"                ,	   0x11800a0040e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_29"                ,	   0x11800a0040ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_30"                ,	   0x11800a0040f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_31"                ,	   0x11800a0040fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_32"                ,	   0x11800a0041040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_33"                ,	   0x11800a00410c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_34"                ,	   0x11800a0041140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_35"                ,	   0x11800a00411c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_36"                ,	   0x11800a0041240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_37"                ,	   0x11800a00412c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_38"                ,	   0x11800a0041340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_39"                ,	   0x11800a00413c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_40"                ,	   0x11800a0041440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_41"                ,	   0x11800a00414c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_42"                ,	   0x11800a0041540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_43"                ,	   0x11800a00415c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_44"                ,	   0x11800a0041640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_45"                ,	   0x11800a00416c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_46"                ,	   0x11800a0041740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_47"                ,	   0x11800a00417c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_48"                ,	   0x11800a0041840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_49"                ,	   0x11800a00418c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_50"                ,	   0x11800a0041940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_51"                ,	   0x11800a00419c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_52"                ,	   0x11800a0041a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_53"                ,	   0x11800a0041ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_54"                ,	   0x11800a0041b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_55"                ,	   0x11800a0041bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_56"                ,	   0x11800a0041c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_57"                ,	   0x11800a0041cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_58"                ,	   0x11800a0041d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_59"                ,	   0x11800a0041dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_60"                ,	   0x11800a0041e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_61"                ,	   0x11800a0041ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_62"                ,	   0x11800a0041f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT8_63"                ,	   0x11800a0041fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_STAT9_0"                 ,	   0x11800a0040048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_1"                 ,	   0x11800a00400c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_2"                 ,	   0x11800a0040148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_3"                 ,	   0x11800a00401c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_4"                 ,	   0x11800a0040248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_5"                 ,	   0x11800a00402c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_6"                 ,	   0x11800a0040348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_7"                 ,	   0x11800a00403c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_8"                 ,	   0x11800a0040448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_9"                 ,	   0x11800a00404c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_10"                ,	   0x11800a0040548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_11"                ,	   0x11800a00405c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_12"                ,	   0x11800a0040648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_13"                ,	   0x11800a00406c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_14"                ,	   0x11800a0040748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_15"                ,	   0x11800a00407c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_16"                ,	   0x11800a0040848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_17"                ,	   0x11800a00408c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_18"                ,	   0x11800a0040948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_19"                ,	   0x11800a00409c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_20"                ,	   0x11800a0040a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_21"                ,	   0x11800a0040ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_22"                ,	   0x11800a0040b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_23"                ,	   0x11800a0040bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_24"                ,	   0x11800a0040c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_25"                ,	   0x11800a0040cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_26"                ,	   0x11800a0040d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_27"                ,	   0x11800a0040dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_28"                ,	   0x11800a0040e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_29"                ,	   0x11800a0040ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_30"                ,	   0x11800a0040f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_31"                ,	   0x11800a0040fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_32"                ,	   0x11800a0041048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_33"                ,	   0x11800a00410c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_34"                ,	   0x11800a0041148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_35"                ,	   0x11800a00411c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_36"                ,	   0x11800a0041248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_37"                ,	   0x11800a00412c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_38"                ,	   0x11800a0041348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_39"                ,	   0x11800a00413c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_40"                ,	   0x11800a0041448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_41"                ,	   0x11800a00414c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_42"                ,	   0x11800a0041548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_43"                ,	   0x11800a00415c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_44"                ,	   0x11800a0041648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_45"                ,	   0x11800a00416c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_46"                ,	   0x11800a0041748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_47"                ,	   0x11800a00417c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_48"                ,	   0x11800a0041848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_49"                ,	   0x11800a00418c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_50"                ,	   0x11800a0041948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_51"                ,	   0x11800a00419c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_52"                ,	   0x11800a0041a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_53"                ,	   0x11800a0041ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_54"                ,	   0x11800a0041b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_55"                ,	   0x11800a0041bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_56"                ,	   0x11800a0041c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_57"                ,	   0x11800a0041cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_58"                ,	   0x11800a0041d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_59"                ,	   0x11800a0041dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_60"                ,	   0x11800a0041e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_61"                ,	   0x11800a0041ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_62"                ,	   0x11800a0041f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT9_63"                ,	   0x11800a0041fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1023},
+	{"PIP_STAT_INB_ERRS_PKND0"     ,	   0x11800a0020010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND1"     ,	   0x11800a0020030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND2"     ,	   0x11800a0020050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND3"     ,	   0x11800a0020070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND4"     ,	   0x11800a0020090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND5"     ,	   0x11800a00200b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND6"     ,	   0x11800a00200d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND7"     ,	   0x11800a00200f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND8"     ,	   0x11800a0020110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND9"     ,	   0x11800a0020130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND10"    ,	   0x11800a0020150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND11"    ,	   0x11800a0020170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND12"    ,	   0x11800a0020190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND13"    ,	   0x11800a00201b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND14"    ,	   0x11800a00201d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND15"    ,	   0x11800a00201f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND16"    ,	   0x11800a0020210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND17"    ,	   0x11800a0020230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND18"    ,	   0x11800a0020250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND19"    ,	   0x11800a0020270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND20"    ,	   0x11800a0020290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND21"    ,	   0x11800a00202b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND22"    ,	   0x11800a00202d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND23"    ,	   0x11800a00202f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND24"    ,	   0x11800a0020310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND25"    ,	   0x11800a0020330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND26"    ,	   0x11800a0020350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND27"    ,	   0x11800a0020370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND28"    ,	   0x11800a0020390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND29"    ,	   0x11800a00203b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND30"    ,	   0x11800a00203d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND31"    ,	   0x11800a00203f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND32"    ,	   0x11800a0020410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND33"    ,	   0x11800a0020430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND34"    ,	   0x11800a0020450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND35"    ,	   0x11800a0020470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND36"    ,	   0x11800a0020490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND37"    ,	   0x11800a00204b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND38"    ,	   0x11800a00204d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND39"    ,	   0x11800a00204f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND40"    ,	   0x11800a0020510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND41"    ,	   0x11800a0020530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND42"    ,	   0x11800a0020550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND43"    ,	   0x11800a0020570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND44"    ,	   0x11800a0020590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND45"    ,	   0x11800a00205b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND46"    ,	   0x11800a00205d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND47"    ,	   0x11800a00205f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND48"    ,	   0x11800a0020610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND49"    ,	   0x11800a0020630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND50"    ,	   0x11800a0020650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND51"    ,	   0x11800a0020670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND52"    ,	   0x11800a0020690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND53"    ,	   0x11800a00206b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND54"    ,	   0x11800a00206d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND55"    ,	   0x11800a00206f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND56"    ,	   0x11800a0020710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND57"    ,	   0x11800a0020730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND58"    ,	   0x11800a0020750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND59"    ,	   0x11800a0020770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND60"    ,	   0x11800a0020790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND61"    ,	   0x11800a00207b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND62"    ,	   0x11800a00207d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_ERRS_PKND63"    ,	   0x11800a00207f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_STAT_INB_OCTS_PKND0"     ,	   0x11800a0020008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND1"     ,	   0x11800a0020028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND2"     ,	   0x11800a0020048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND3"     ,	   0x11800a0020068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND4"     ,	   0x11800a0020088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND5"     ,	   0x11800a00200a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND6"     ,	   0x11800a00200c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND7"     ,	   0x11800a00200e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND8"     ,	   0x11800a0020108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND9"     ,	   0x11800a0020128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND10"    ,	   0x11800a0020148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND11"    ,	   0x11800a0020168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND12"    ,	   0x11800a0020188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND13"    ,	   0x11800a00201a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND14"    ,	   0x11800a00201c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND15"    ,	   0x11800a00201e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND16"    ,	   0x11800a0020208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND17"    ,	   0x11800a0020228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND18"    ,	   0x11800a0020248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND19"    ,	   0x11800a0020268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND20"    ,	   0x11800a0020288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND21"    ,	   0x11800a00202a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND22"    ,	   0x11800a00202c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND23"    ,	   0x11800a00202e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND24"    ,	   0x11800a0020308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND25"    ,	   0x11800a0020328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND26"    ,	   0x11800a0020348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND27"    ,	   0x11800a0020368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND28"    ,	   0x11800a0020388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND29"    ,	   0x11800a00203a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND30"    ,	   0x11800a00203c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND31"    ,	   0x11800a00203e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND32"    ,	   0x11800a0020408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND33"    ,	   0x11800a0020428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND34"    ,	   0x11800a0020448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND35"    ,	   0x11800a0020468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND36"    ,	   0x11800a0020488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND37"    ,	   0x11800a00204a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND38"    ,	   0x11800a00204c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND39"    ,	   0x11800a00204e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND40"    ,	   0x11800a0020508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND41"    ,	   0x11800a0020528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND42"    ,	   0x11800a0020548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND43"    ,	   0x11800a0020568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND44"    ,	   0x11800a0020588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND45"    ,	   0x11800a00205a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND46"    ,	   0x11800a00205c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND47"    ,	   0x11800a00205e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND48"    ,	   0x11800a0020608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND49"    ,	   0x11800a0020628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND50"    ,	   0x11800a0020648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND51"    ,	   0x11800a0020668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND52"    ,	   0x11800a0020688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND53"    ,	   0x11800a00206a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND54"    ,	   0x11800a00206c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND55"    ,	   0x11800a00206e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND56"    ,	   0x11800a0020708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND57"    ,	   0x11800a0020728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND58"    ,	   0x11800a0020748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND59"    ,	   0x11800a0020768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND60"    ,	   0x11800a0020788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND61"    ,	   0x11800a00207a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND62"    ,	   0x11800a00207c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_OCTS_PKND63"    ,	   0x11800a00207e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_STAT_INB_PKTS_PKND0"     ,	   0x11800a0020000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND1"     ,	   0x11800a0020020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND2"     ,	   0x11800a0020040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND3"     ,	   0x11800a0020060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND4"     ,	   0x11800a0020080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND5"     ,	   0x11800a00200a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND6"     ,	   0x11800a00200c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND7"     ,	   0x11800a00200e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND8"     ,	   0x11800a0020100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND9"     ,	   0x11800a0020120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND10"    ,	   0x11800a0020140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND11"    ,	   0x11800a0020160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND12"    ,	   0x11800a0020180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND13"    ,	   0x11800a00201a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND14"    ,	   0x11800a00201c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND15"    ,	   0x11800a00201e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND16"    ,	   0x11800a0020200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND17"    ,	   0x11800a0020220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND18"    ,	   0x11800a0020240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND19"    ,	   0x11800a0020260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND20"    ,	   0x11800a0020280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND21"    ,	   0x11800a00202a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND22"    ,	   0x11800a00202c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND23"    ,	   0x11800a00202e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND24"    ,	   0x11800a0020300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND25"    ,	   0x11800a0020320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND26"    ,	   0x11800a0020340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND27"    ,	   0x11800a0020360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND28"    ,	   0x11800a0020380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND29"    ,	   0x11800a00203a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND30"    ,	   0x11800a00203c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND31"    ,	   0x11800a00203e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND32"    ,	   0x11800a0020400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND33"    ,	   0x11800a0020420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND34"    ,	   0x11800a0020440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND35"    ,	   0x11800a0020460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND36"    ,	   0x11800a0020480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND37"    ,	   0x11800a00204a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND38"    ,	   0x11800a00204c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND39"    ,	   0x11800a00204e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND40"    ,	   0x11800a0020500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND41"    ,	   0x11800a0020520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND42"    ,	   0x11800a0020540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND43"    ,	   0x11800a0020560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND44"    ,	   0x11800a0020580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND45"    ,	   0x11800a00205a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND46"    ,	   0x11800a00205c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND47"    ,	   0x11800a00205e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND48"    ,	   0x11800a0020600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND49"    ,	   0x11800a0020620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND50"    ,	   0x11800a0020640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND51"    ,	   0x11800a0020660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND52"    ,	   0x11800a0020680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND53"    ,	   0x11800a00206a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND54"    ,	   0x11800a00206c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND55"    ,	   0x11800a00206e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND56"    ,	   0x11800a0020700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND57"    ,	   0x11800a0020720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND58"    ,	   0x11800a0020740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND59"    ,	   0x11800a0020760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND60"    ,	   0x11800a0020780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND61"    ,	   0x11800a00207a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND62"    ,	   0x11800a00207c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_STAT_INB_PKTS_PKND63"    ,	   0x11800a00207e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_SUB_PKIND_FCS0"          ,	   0x11800a0080000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1029},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1030},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1043},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1047},
+	{"PKO_MEM_IPORT_PTRS"          ,	   0x1180050001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PKO_MEM_IPORT_QOS"           ,	   0x1180050001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1049},
+	{"PKO_MEM_IQUEUE_PTRS"         ,	   0x1180050001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1050},
+	{"PKO_MEM_IQUEUE_QOS"          ,	   0x1180050001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1051},
+	{"PKO_MEM_PORT_RATE0"          ,	   0x1180050001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1052},
+	{"PKO_MEM_PORT_RATE1"          ,	   0x1180050001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1053},
+	{"PKO_MEM_THROTTLE_INT"        ,	   0x1180050001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1054},
+	{"PKO_MEM_THROTTLE_PIPE"       ,	   0x1180050001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1055},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1056},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1057},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1058},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1059},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1060},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1061},
+	{"PKO_REG_DEBUG4"              ,	   0x11800500000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"PKO_REG_ENGINE_INFLIGHT1"    ,	   0x1180050000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1064},
+	{"PKO_REG_ENGINE_STORAGE0"     ,	   0x1180050000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1065},
+	{"PKO_REG_ENGINE_STORAGE1"     ,	   0x1180050000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1065},
+	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1066},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1067},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1068},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1069},
+	{"PKO_REG_LOOPBACK_BPID"       ,	   0x1180050000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1070},
+	{"PKO_REG_LOOPBACK_PKIND"      ,	   0x1180050000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1071},
+	{"PKO_REG_MIN_PKT"             ,	   0x1180050000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1072},
+	{"PKO_REG_PREEMPT"             ,	   0x1180050000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1073},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1074},
+	{"PKO_REG_QUEUE_PREEMPT"       ,	   0x1180050000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1075},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1076},
+	{"PKO_REG_THROTTLE"            ,	   0x1180050000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1077},
+	{"PKO_REG_TIMESTAMP"           ,	   0x1180050000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1078},
+	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1079},
+	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1080},
+	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1081},
+	{"RAD_REG_BIST_RESULT"         ,	   0x1180070000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1082},
+	{"RAD_REG_CMD_BUF"             ,	   0x1180070000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1083},
+	{"RAD_REG_CTL"                 ,	   0x1180070000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1084},
+	{"RAD_REG_DEBUG0"              ,	   0x1180070000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1085},
+	{"RAD_REG_DEBUG1"              ,	   0x1180070000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1086},
+	{"RAD_REG_DEBUG10"             ,	   0x1180070000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1087},
+	{"RAD_REG_DEBUG11"             ,	   0x1180070000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1088},
+	{"RAD_REG_DEBUG12"             ,	   0x1180070000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1089},
+	{"RAD_REG_DEBUG2"              ,	   0x1180070000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1090},
+	{"RAD_REG_DEBUG3"              ,	   0x1180070000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"RAD_REG_DEBUG4"              ,	   0x1180070000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1092},
+	{"RAD_REG_DEBUG5"              ,	   0x1180070000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1093},
+	{"RAD_REG_DEBUG6"              ,	   0x1180070000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1094},
+	{"RAD_REG_DEBUG7"              ,	   0x1180070000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1095},
+	{"RAD_REG_DEBUG8"              ,	   0x1180070000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1096},
+	{"RAD_REG_DEBUG9"              ,	   0x1180070000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1097},
+	{"RAD_REG_ERROR"               ,	   0x1180070000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1098},
+	{"RAD_REG_INT_MASK"            ,	   0x1180070000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1099},
+	{"RAD_REG_POLYNOMIAL"          ,	   0x1180070000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1100},
+	{"RAD_REG_READ_IDX"            ,	   0x1180070000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1101},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1102},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1103},
+	{"RNM_EER_DBG"                 ,	   0x1180040000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1104},
+	{"RNM_EER_KEY"                 ,	   0x1180040000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1105},
+	{"RNM_SERIAL_NUM"              ,	   0x1180040000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1106},
+	{"SLI_BIST_STATUS"             ,	   0x11f0000010580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1107},
+	{"SLI_CTL_PORT0"               ,	   0x11f0000010050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1108},
+	{"SLI_CTL_PORT1"               ,	   0x11f0000010060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1108},
+	{"SLI_CTL_STATUS"              ,	   0x11f0000010570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1109},
+	{"SLI_DATA_OUT_CNT"            ,	   0x11f00000105f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1110},
+	{"SLI_DBG_DATA"                ,	   0x11f0000010310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1111},
+	{"SLI_DBG_SELECT"              ,	   0x11f0000010300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1112},
+	{"SLI_DMA0_CNT"                ,	   0x11f0000010400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1113},
+	{"SLI_DMA1_CNT"                ,	   0x11f0000010410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1113},
+	{"SLI_DMA0_INT_LEVEL"          ,	   0x11f00000103e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1114},
+	{"SLI_DMA1_INT_LEVEL"          ,	   0x11f00000103f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1114},
+	{"SLI_DMA0_TIM"                ,	   0x11f0000010420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1115},
+	{"SLI_DMA1_TIM"                ,	   0x11f0000010430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1115},
+	{"SLI_INT_ENB_CIU"             ,	   0x11f0000013cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1116},
+	{"SLI_INT_ENB_PORT0"           ,	   0x11f0000010340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1117},
+	{"SLI_INT_ENB_PORT1"           ,	   0x11f0000010350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1117},
+	{"SLI_INT_SUM"                 ,	   0x11f0000010330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1118},
+	{"SLI_LAST_WIN_RDATA0"         ,	   0x11f0000010600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1119},
+	{"SLI_LAST_WIN_RDATA1"         ,	   0x11f0000010610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1120},
+	{"SLI_MAC_CREDIT_CNT"          ,	   0x11f0000013d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1121},
+	{"SLI_MAC_NUMBER"              ,	            0x3e00ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1122},
+	{"SLI_MEM_ACCESS_CTL"          ,	   0x11f00000102f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1123},
+	{"SLI_MEM_ACCESS_SUBID12"      ,	   0x11f00000100e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1124},
+	{"SLI_MEM_ACCESS_SUBID13"      ,	   0x11f00000100f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1124},
+	{"SLI_MEM_ACCESS_SUBID14"      ,	   0x11f0000010100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1124},
+	{"SLI_MEM_ACCESS_SUBID15"      ,	   0x11f0000010110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1124},
+	{"SLI_MEM_ACCESS_SUBID16"      ,	   0x11f0000010120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1124},
+	{"SLI_MEM_ACCESS_SUBID17"      ,	   0x11f0000010130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1124},
+	{"SLI_MEM_ACCESS_SUBID18"      ,	   0x11f0000010140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1124},
+	{"SLI_MEM_ACCESS_SUBID19"      ,	   0x11f0000010150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1124},
+	{"SLI_MEM_ACCESS_SUBID20"      ,	   0x11f0000010160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1124},
+	{"SLI_MEM_ACCESS_SUBID21"      ,	   0x11f0000010170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1124},
+	{"SLI_MEM_ACCESS_SUBID22"      ,	   0x11f0000010180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1124},
+	{"SLI_MEM_ACCESS_SUBID23"      ,	   0x11f0000010190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1124},
+	{"SLI_MEM_ACCESS_SUBID24"      ,	   0x11f00000101a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1124},
+	{"SLI_MEM_ACCESS_SUBID25"      ,	   0x11f00000101b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1124},
+	{"SLI_MEM_ACCESS_SUBID26"      ,	   0x11f00000101c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1124},
+	{"SLI_MEM_ACCESS_SUBID27"      ,	   0x11f00000101d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1124},
+	{"SLI_MSI_ENB0"                ,	   0x11f0000013c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1125},
+	{"SLI_MSI_ENB1"                ,	   0x11f0000013c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1126},
+	{"SLI_MSI_ENB2"                ,	   0x11f0000013c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1127},
+	{"SLI_MSI_ENB3"                ,	   0x11f0000013c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1128},
+	{"SLI_MSI_RCV0"                ,	   0x11f0000013c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1129},
+	{"SLI_MSI_RCV1"                ,	   0x11f0000013c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1130},
+	{"SLI_MSI_RCV2"                ,	   0x11f0000013c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1131},
+	{"SLI_MSI_RCV3"                ,	   0x11f0000013c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1132},
+	{"SLI_MSI_RD_MAP"              ,	   0x11f0000013ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1133},
+	{"SLI_MSI_W1C_ENB0"            ,	   0x11f0000013cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1134},
+	{"SLI_MSI_W1C_ENB1"            ,	   0x11f0000013d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1135},
+	{"SLI_MSI_W1C_ENB2"            ,	   0x11f0000013d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1136},
+	{"SLI_MSI_W1C_ENB3"            ,	   0x11f0000013d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1137},
+	{"SLI_MSI_W1S_ENB0"            ,	   0x11f0000013d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1138},
+	{"SLI_MSI_W1S_ENB1"            ,	   0x11f0000013d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1139},
+	{"SLI_MSI_W1S_ENB2"            ,	   0x11f0000013d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1140},
+	{"SLI_MSI_W1S_ENB3"            ,	   0x11f0000013d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1141},
+	{"SLI_MSI_WR_MAP"              ,	   0x11f0000013c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1142},
+	{"SLI_PCIE_MSI_RCV"            ,	   0x11f0000013cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1143},
+	{"SLI_PCIE_MSI_RCV_B1"         ,	   0x11f0000010650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1144},
+	{"SLI_PCIE_MSI_RCV_B2"         ,	   0x11f0000010660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1145},
+	{"SLI_PCIE_MSI_RCV_B3"         ,	   0x11f0000010670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1146},
+	{"SLI_PKT0_CNTS"               ,	   0x11f0000012400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT1_CNTS"               ,	   0x11f0000012410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT2_CNTS"               ,	   0x11f0000012420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT3_CNTS"               ,	   0x11f0000012430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT4_CNTS"               ,	   0x11f0000012440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT5_CNTS"               ,	   0x11f0000012450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT6_CNTS"               ,	   0x11f0000012460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT7_CNTS"               ,	   0x11f0000012470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT8_CNTS"               ,	   0x11f0000012480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT9_CNTS"               ,	   0x11f0000012490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT10_CNTS"              ,	   0x11f00000124a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT11_CNTS"              ,	   0x11f00000124b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT12_CNTS"              ,	   0x11f00000124c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT13_CNTS"              ,	   0x11f00000124d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT14_CNTS"              ,	   0x11f00000124e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT15_CNTS"              ,	   0x11f00000124f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT16_CNTS"              ,	   0x11f0000012500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT17_CNTS"              ,	   0x11f0000012510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT18_CNTS"              ,	   0x11f0000012520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT19_CNTS"              ,	   0x11f0000012530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT20_CNTS"              ,	   0x11f0000012540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT21_CNTS"              ,	   0x11f0000012550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT22_CNTS"              ,	   0x11f0000012560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT23_CNTS"              ,	   0x11f0000012570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT24_CNTS"              ,	   0x11f0000012580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT25_CNTS"              ,	   0x11f0000012590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT26_CNTS"              ,	   0x11f00000125a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT27_CNTS"              ,	   0x11f00000125b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT28_CNTS"              ,	   0x11f00000125c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT29_CNTS"              ,	   0x11f00000125d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT30_CNTS"              ,	   0x11f00000125e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT31_CNTS"              ,	   0x11f00000125f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_PKT0_INSTR_BADDR"        ,	   0x11f0000012800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT1_INSTR_BADDR"        ,	   0x11f0000012810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT2_INSTR_BADDR"        ,	   0x11f0000012820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT3_INSTR_BADDR"        ,	   0x11f0000012830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT4_INSTR_BADDR"        ,	   0x11f0000012840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT5_INSTR_BADDR"        ,	   0x11f0000012850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT6_INSTR_BADDR"        ,	   0x11f0000012860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT7_INSTR_BADDR"        ,	   0x11f0000012870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT8_INSTR_BADDR"        ,	   0x11f0000012880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT9_INSTR_BADDR"        ,	   0x11f0000012890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT10_INSTR_BADDR"       ,	   0x11f00000128a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT11_INSTR_BADDR"       ,	   0x11f00000128b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT12_INSTR_BADDR"       ,	   0x11f00000128c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT13_INSTR_BADDR"       ,	   0x11f00000128d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT14_INSTR_BADDR"       ,	   0x11f00000128e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT15_INSTR_BADDR"       ,	   0x11f00000128f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT16_INSTR_BADDR"       ,	   0x11f0000012900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT17_INSTR_BADDR"       ,	   0x11f0000012910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT18_INSTR_BADDR"       ,	   0x11f0000012920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT19_INSTR_BADDR"       ,	   0x11f0000012930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT20_INSTR_BADDR"       ,	   0x11f0000012940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT21_INSTR_BADDR"       ,	   0x11f0000012950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT22_INSTR_BADDR"       ,	   0x11f0000012960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT23_INSTR_BADDR"       ,	   0x11f0000012970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT24_INSTR_BADDR"       ,	   0x11f0000012980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT25_INSTR_BADDR"       ,	   0x11f0000012990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT26_INSTR_BADDR"       ,	   0x11f00000129a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT27_INSTR_BADDR"       ,	   0x11f00000129b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT28_INSTR_BADDR"       ,	   0x11f00000129c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT29_INSTR_BADDR"       ,	   0x11f00000129d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT30_INSTR_BADDR"       ,	   0x11f00000129e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT31_INSTR_BADDR"       ,	   0x11f00000129f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_PKT0_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT1_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT2_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT3_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT4_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT5_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT6_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT7_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT8_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT9_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT10_INSTR_BAOFF_DBELL" ,	   0x11f0000012ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT11_INSTR_BAOFF_DBELL" ,	   0x11f0000012cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT12_INSTR_BAOFF_DBELL" ,	   0x11f0000012cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT13_INSTR_BAOFF_DBELL" ,	   0x11f0000012cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT14_INSTR_BAOFF_DBELL" ,	   0x11f0000012ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT15_INSTR_BAOFF_DBELL" ,	   0x11f0000012cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT16_INSTR_BAOFF_DBELL" ,	   0x11f0000012d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT17_INSTR_BAOFF_DBELL" ,	   0x11f0000012d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT18_INSTR_BAOFF_DBELL" ,	   0x11f0000012d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT19_INSTR_BAOFF_DBELL" ,	   0x11f0000012d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT20_INSTR_BAOFF_DBELL" ,	   0x11f0000012d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT21_INSTR_BAOFF_DBELL" ,	   0x11f0000012d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT22_INSTR_BAOFF_DBELL" ,	   0x11f0000012d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT23_INSTR_BAOFF_DBELL" ,	   0x11f0000012d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT24_INSTR_BAOFF_DBELL" ,	   0x11f0000012d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT25_INSTR_BAOFF_DBELL" ,	   0x11f0000012d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT26_INSTR_BAOFF_DBELL" ,	   0x11f0000012da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT27_INSTR_BAOFF_DBELL" ,	   0x11f0000012db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT28_INSTR_BAOFF_DBELL" ,	   0x11f0000012dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT29_INSTR_BAOFF_DBELL" ,	   0x11f0000012dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT30_INSTR_BAOFF_DBELL" ,	   0x11f0000012de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT31_INSTR_BAOFF_DBELL" ,	   0x11f0000012df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_PKT0_INSTR_FIFO_RSIZE"   ,	   0x11f0000013000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT1_INSTR_FIFO_RSIZE"   ,	   0x11f0000013010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT2_INSTR_FIFO_RSIZE"   ,	   0x11f0000013020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT3_INSTR_FIFO_RSIZE"   ,	   0x11f0000013030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT4_INSTR_FIFO_RSIZE"   ,	   0x11f0000013040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT5_INSTR_FIFO_RSIZE"   ,	   0x11f0000013050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT6_INSTR_FIFO_RSIZE"   ,	   0x11f0000013060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT7_INSTR_FIFO_RSIZE"   ,	   0x11f0000013070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT8_INSTR_FIFO_RSIZE"   ,	   0x11f0000013080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT9_INSTR_FIFO_RSIZE"   ,	   0x11f0000013090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT10_INSTR_FIFO_RSIZE"  ,	   0x11f00000130a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT11_INSTR_FIFO_RSIZE"  ,	   0x11f00000130b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT12_INSTR_FIFO_RSIZE"  ,	   0x11f00000130c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT13_INSTR_FIFO_RSIZE"  ,	   0x11f00000130d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT14_INSTR_FIFO_RSIZE"  ,	   0x11f00000130e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT15_INSTR_FIFO_RSIZE"  ,	   0x11f00000130f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT16_INSTR_FIFO_RSIZE"  ,	   0x11f0000013100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT17_INSTR_FIFO_RSIZE"  ,	   0x11f0000013110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT18_INSTR_FIFO_RSIZE"  ,	   0x11f0000013120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT19_INSTR_FIFO_RSIZE"  ,	   0x11f0000013130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT20_INSTR_FIFO_RSIZE"  ,	   0x11f0000013140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT21_INSTR_FIFO_RSIZE"  ,	   0x11f0000013150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT22_INSTR_FIFO_RSIZE"  ,	   0x11f0000013160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT23_INSTR_FIFO_RSIZE"  ,	   0x11f0000013170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT24_INSTR_FIFO_RSIZE"  ,	   0x11f0000013180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT25_INSTR_FIFO_RSIZE"  ,	   0x11f0000013190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT26_INSTR_FIFO_RSIZE"  ,	   0x11f00000131a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT27_INSTR_FIFO_RSIZE"  ,	   0x11f00000131b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT28_INSTR_FIFO_RSIZE"  ,	   0x11f00000131c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT29_INSTR_FIFO_RSIZE"  ,	   0x11f00000131d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT30_INSTR_FIFO_RSIZE"  ,	   0x11f00000131e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT31_INSTR_FIFO_RSIZE"  ,	   0x11f00000131f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_PKT0_INSTR_HEADER"       ,	   0x11f0000013400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT1_INSTR_HEADER"       ,	   0x11f0000013410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT2_INSTR_HEADER"       ,	   0x11f0000013420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT3_INSTR_HEADER"       ,	   0x11f0000013430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT4_INSTR_HEADER"       ,	   0x11f0000013440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT5_INSTR_HEADER"       ,	   0x11f0000013450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT6_INSTR_HEADER"       ,	   0x11f0000013460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT7_INSTR_HEADER"       ,	   0x11f0000013470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT8_INSTR_HEADER"       ,	   0x11f0000013480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT9_INSTR_HEADER"       ,	   0x11f0000013490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT10_INSTR_HEADER"      ,	   0x11f00000134a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT11_INSTR_HEADER"      ,	   0x11f00000134b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT12_INSTR_HEADER"      ,	   0x11f00000134c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT13_INSTR_HEADER"      ,	   0x11f00000134d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT14_INSTR_HEADER"      ,	   0x11f00000134e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT15_INSTR_HEADER"      ,	   0x11f00000134f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT16_INSTR_HEADER"      ,	   0x11f0000013500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT17_INSTR_HEADER"      ,	   0x11f0000013510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT18_INSTR_HEADER"      ,	   0x11f0000013520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT19_INSTR_HEADER"      ,	   0x11f0000013530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT20_INSTR_HEADER"      ,	   0x11f0000013540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT21_INSTR_HEADER"      ,	   0x11f0000013550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT22_INSTR_HEADER"      ,	   0x11f0000013560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT23_INSTR_HEADER"      ,	   0x11f0000013570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT24_INSTR_HEADER"      ,	   0x11f0000013580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT25_INSTR_HEADER"      ,	   0x11f0000013590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT26_INSTR_HEADER"      ,	   0x11f00000135a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT27_INSTR_HEADER"      ,	   0x11f00000135b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT28_INSTR_HEADER"      ,	   0x11f00000135c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT29_INSTR_HEADER"      ,	   0x11f00000135d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT30_INSTR_HEADER"      ,	   0x11f00000135e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT31_INSTR_HEADER"      ,	   0x11f00000135f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_PKT0_OUT_SIZE"           ,	   0x11f0000010c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT1_OUT_SIZE"           ,	   0x11f0000010c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT2_OUT_SIZE"           ,	   0x11f0000010c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT3_OUT_SIZE"           ,	   0x11f0000010c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT4_OUT_SIZE"           ,	   0x11f0000010c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT5_OUT_SIZE"           ,	   0x11f0000010c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT6_OUT_SIZE"           ,	   0x11f0000010c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT7_OUT_SIZE"           ,	   0x11f0000010c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT8_OUT_SIZE"           ,	   0x11f0000010c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT9_OUT_SIZE"           ,	   0x11f0000010c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT10_OUT_SIZE"          ,	   0x11f0000010ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT11_OUT_SIZE"          ,	   0x11f0000010cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT12_OUT_SIZE"          ,	   0x11f0000010cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT13_OUT_SIZE"          ,	   0x11f0000010cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT14_OUT_SIZE"          ,	   0x11f0000010ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT15_OUT_SIZE"          ,	   0x11f0000010cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT16_OUT_SIZE"          ,	   0x11f0000010d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT17_OUT_SIZE"          ,	   0x11f0000010d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT18_OUT_SIZE"          ,	   0x11f0000010d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT19_OUT_SIZE"          ,	   0x11f0000010d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT20_OUT_SIZE"          ,	   0x11f0000010d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT21_OUT_SIZE"          ,	   0x11f0000010d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT22_OUT_SIZE"          ,	   0x11f0000010d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT23_OUT_SIZE"          ,	   0x11f0000010d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT24_OUT_SIZE"          ,	   0x11f0000010d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT25_OUT_SIZE"          ,	   0x11f0000010d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT26_OUT_SIZE"          ,	   0x11f0000010da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT27_OUT_SIZE"          ,	   0x11f0000010db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT28_OUT_SIZE"          ,	   0x11f0000010dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT29_OUT_SIZE"          ,	   0x11f0000010dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT30_OUT_SIZE"          ,	   0x11f0000010de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT31_OUT_SIZE"          ,	   0x11f0000010df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_PKT0_SLIST_BADDR"        ,	   0x11f0000011400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT1_SLIST_BADDR"        ,	   0x11f0000011410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT2_SLIST_BADDR"        ,	   0x11f0000011420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT3_SLIST_BADDR"        ,	   0x11f0000011430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT4_SLIST_BADDR"        ,	   0x11f0000011440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT5_SLIST_BADDR"        ,	   0x11f0000011450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT6_SLIST_BADDR"        ,	   0x11f0000011460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT7_SLIST_BADDR"        ,	   0x11f0000011470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT8_SLIST_BADDR"        ,	   0x11f0000011480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT9_SLIST_BADDR"        ,	   0x11f0000011490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT10_SLIST_BADDR"       ,	   0x11f00000114a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT11_SLIST_BADDR"       ,	   0x11f00000114b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT12_SLIST_BADDR"       ,	   0x11f00000114c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT13_SLIST_BADDR"       ,	   0x11f00000114d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT14_SLIST_BADDR"       ,	   0x11f00000114e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT15_SLIST_BADDR"       ,	   0x11f00000114f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT16_SLIST_BADDR"       ,	   0x11f0000011500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT17_SLIST_BADDR"       ,	   0x11f0000011510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT18_SLIST_BADDR"       ,	   0x11f0000011520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT19_SLIST_BADDR"       ,	   0x11f0000011530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT20_SLIST_BADDR"       ,	   0x11f0000011540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT21_SLIST_BADDR"       ,	   0x11f0000011550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT22_SLIST_BADDR"       ,	   0x11f0000011560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT23_SLIST_BADDR"       ,	   0x11f0000011570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT24_SLIST_BADDR"       ,	   0x11f0000011580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT25_SLIST_BADDR"       ,	   0x11f0000011590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT26_SLIST_BADDR"       ,	   0x11f00000115a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT27_SLIST_BADDR"       ,	   0x11f00000115b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT28_SLIST_BADDR"       ,	   0x11f00000115c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT29_SLIST_BADDR"       ,	   0x11f00000115d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT30_SLIST_BADDR"       ,	   0x11f00000115e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT31_SLIST_BADDR"       ,	   0x11f00000115f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_PKT0_SLIST_BAOFF_DBELL"  ,	   0x11f0000011800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT1_SLIST_BAOFF_DBELL"  ,	   0x11f0000011810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT2_SLIST_BAOFF_DBELL"  ,	   0x11f0000011820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT3_SLIST_BAOFF_DBELL"  ,	   0x11f0000011830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT4_SLIST_BAOFF_DBELL"  ,	   0x11f0000011840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT5_SLIST_BAOFF_DBELL"  ,	   0x11f0000011850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT6_SLIST_BAOFF_DBELL"  ,	   0x11f0000011860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT7_SLIST_BAOFF_DBELL"  ,	   0x11f0000011870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT8_SLIST_BAOFF_DBELL"  ,	   0x11f0000011880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT9_SLIST_BAOFF_DBELL"  ,	   0x11f0000011890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT10_SLIST_BAOFF_DBELL" ,	   0x11f00000118a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT11_SLIST_BAOFF_DBELL" ,	   0x11f00000118b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT12_SLIST_BAOFF_DBELL" ,	   0x11f00000118c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT13_SLIST_BAOFF_DBELL" ,	   0x11f00000118d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT14_SLIST_BAOFF_DBELL" ,	   0x11f00000118e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT15_SLIST_BAOFF_DBELL" ,	   0x11f00000118f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT16_SLIST_BAOFF_DBELL" ,	   0x11f0000011900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT17_SLIST_BAOFF_DBELL" ,	   0x11f0000011910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT18_SLIST_BAOFF_DBELL" ,	   0x11f0000011920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT19_SLIST_BAOFF_DBELL" ,	   0x11f0000011930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT20_SLIST_BAOFF_DBELL" ,	   0x11f0000011940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT21_SLIST_BAOFF_DBELL" ,	   0x11f0000011950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT22_SLIST_BAOFF_DBELL" ,	   0x11f0000011960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT23_SLIST_BAOFF_DBELL" ,	   0x11f0000011970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT24_SLIST_BAOFF_DBELL" ,	   0x11f0000011980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT25_SLIST_BAOFF_DBELL" ,	   0x11f0000011990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT26_SLIST_BAOFF_DBELL" ,	   0x11f00000119a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT27_SLIST_BAOFF_DBELL" ,	   0x11f00000119b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT28_SLIST_BAOFF_DBELL" ,	   0x11f00000119c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT29_SLIST_BAOFF_DBELL" ,	   0x11f00000119d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT30_SLIST_BAOFF_DBELL" ,	   0x11f00000119e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT31_SLIST_BAOFF_DBELL" ,	   0x11f00000119f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_PKT0_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT1_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT2_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT3_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT4_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT5_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT6_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT7_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT8_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT9_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT10_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT11_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT12_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT13_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT14_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT15_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT16_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT17_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT18_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT19_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT20_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT21_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT22_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT23_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT24_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT25_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT26_SLIST_FIFO_RSIZE"  ,	   0x11f0000011da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT27_SLIST_FIFO_RSIZE"  ,	   0x11f0000011db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT28_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT29_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT30_SLIST_FIFO_RSIZE"  ,	   0x11f0000011de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT31_SLIST_FIFO_RSIZE"  ,	   0x11f0000011df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_PKT_CNT_INT"             ,	   0x11f0000011130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1156},
+	{"SLI_PKT_CNT_INT_ENB"         ,	   0x11f0000011150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1157},
+	{"SLI_PKT_CTL"                 ,	   0x11f0000011220ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1158},
+	{"SLI_PKT_DATA_OUT_ES"         ,	   0x11f00000110b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1159},
+	{"SLI_PKT_DATA_OUT_NS"         ,	   0x11f00000110a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1160},
+	{"SLI_PKT_DATA_OUT_ROR"        ,	   0x11f0000011090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1161},
+	{"SLI_PKT_DPADDR"              ,	   0x11f0000011080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1162},
+	{"SLI_PKT_IN_DONE0_CNTS"       ,	   0x11f0000012000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE1_CNTS"       ,	   0x11f0000012010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE2_CNTS"       ,	   0x11f0000012020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE3_CNTS"       ,	   0x11f0000012030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE4_CNTS"       ,	   0x11f0000012040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE5_CNTS"       ,	   0x11f0000012050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE6_CNTS"       ,	   0x11f0000012060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE7_CNTS"       ,	   0x11f0000012070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE8_CNTS"       ,	   0x11f0000012080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE9_CNTS"       ,	   0x11f0000012090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE10_CNTS"      ,	   0x11f00000120a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE11_CNTS"      ,	   0x11f00000120b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE12_CNTS"      ,	   0x11f00000120c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE13_CNTS"      ,	   0x11f00000120d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE14_CNTS"      ,	   0x11f00000120e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE15_CNTS"      ,	   0x11f00000120f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE16_CNTS"      ,	   0x11f0000012100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE17_CNTS"      ,	   0x11f0000012110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE18_CNTS"      ,	   0x11f0000012120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE19_CNTS"      ,	   0x11f0000012130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE20_CNTS"      ,	   0x11f0000012140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE21_CNTS"      ,	   0x11f0000012150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE22_CNTS"      ,	   0x11f0000012160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE23_CNTS"      ,	   0x11f0000012170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE24_CNTS"      ,	   0x11f0000012180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE25_CNTS"      ,	   0x11f0000012190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE26_CNTS"      ,	   0x11f00000121a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE27_CNTS"      ,	   0x11f00000121b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE28_CNTS"      ,	   0x11f00000121c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE29_CNTS"      ,	   0x11f00000121d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE30_CNTS"      ,	   0x11f00000121e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_DONE31_CNTS"      ,	   0x11f00000121f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PKT_IN_INSTR_COUNTS"     ,	   0x11f0000011200ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1164},
+	{"SLI_PKT_IN_PCIE_PORT"        ,	   0x11f00000111b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1165},
+	{"SLI_PKT_INPUT_CONTROL"       ,	   0x11f0000011170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1166},
+	{"SLI_PKT_INSTR_ENB"           ,	   0x11f0000011000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1167},
+	{"SLI_PKT_INSTR_RD_SIZE"       ,	   0x11f00000111a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT_INSTR_SIZE"          ,	   0x11f0000011020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT_INT_LEVELS"          ,	   0x11f0000011120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT_IPTR"                ,	   0x11f0000011070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT_OUT_BMODE"           ,	   0x11f00000110d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT_OUT_BP_EN"           ,	   0x11f0000011240ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT_OUT_ENB"             ,	   0x11f0000011010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT_OUTPUT_WMARK"        ,	   0x11f0000011180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT_PCIE_PORT"           ,	   0x11f00000110e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT_PORT_IN_RST"         ,	   0x11f00000111f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1177},
+	{"SLI_PKT_SLIST_ES"            ,	   0x11f0000011050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1178},
+	{"SLI_PKT_SLIST_NS"            ,	   0x11f0000011040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1179},
+	{"SLI_PKT_SLIST_ROR"           ,	   0x11f0000011030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1180},
+	{"SLI_PKT_TIME_INT"            ,	   0x11f0000011140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1181},
+	{"SLI_PKT_TIME_INT_ENB"        ,	   0x11f0000011160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1182},
+	{"SLI_PORT0_PKIND"             ,	   0x11f0000010800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT1_PKIND"             ,	   0x11f0000010810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT2_PKIND"             ,	   0x11f0000010820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT3_PKIND"             ,	   0x11f0000010830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT4_PKIND"             ,	   0x11f0000010840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT5_PKIND"             ,	   0x11f0000010850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT6_PKIND"             ,	   0x11f0000010860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT7_PKIND"             ,	   0x11f0000010870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT8_PKIND"             ,	   0x11f0000010880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT9_PKIND"             ,	   0x11f0000010890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT10_PKIND"            ,	   0x11f00000108a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT11_PKIND"            ,	   0x11f00000108b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT12_PKIND"            ,	   0x11f00000108c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT13_PKIND"            ,	   0x11f00000108d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT14_PKIND"            ,	   0x11f00000108e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT15_PKIND"            ,	   0x11f00000108f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT16_PKIND"            ,	   0x11f0000010900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT17_PKIND"            ,	   0x11f0000010910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT18_PKIND"            ,	   0x11f0000010920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT19_PKIND"            ,	   0x11f0000010930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT20_PKIND"            ,	   0x11f0000010940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT21_PKIND"            ,	   0x11f0000010950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT22_PKIND"            ,	   0x11f0000010960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT23_PKIND"            ,	   0x11f0000010970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT24_PKIND"            ,	   0x11f0000010980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT25_PKIND"            ,	   0x11f0000010990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT26_PKIND"            ,	   0x11f00000109a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT27_PKIND"            ,	   0x11f00000109b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT28_PKIND"            ,	   0x11f00000109c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT29_PKIND"            ,	   0x11f00000109d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT30_PKIND"            ,	   0x11f00000109e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PORT31_PKIND"            ,	   0x11f00000109f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_S2M_PORT0_CTL"           ,	   0x11f0000013d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_S2M_PORT1_CTL"           ,	   0x11f0000013d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_SCRATCH_1"               ,	   0x11f00000103c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1185},
+	{"SLI_SCRATCH_2"               ,	   0x11f00000103d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1186},
+	{"SLI_STATE1"                  ,	   0x11f0000010620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1187},
+	{"SLI_STATE2"                  ,	   0x11f0000010630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1188},
+	{"SLI_STATE3"                  ,	   0x11f0000010640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1189},
+	{"SLI_TX_PIPE"                 ,	   0x11f0000011230ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1190},
+	{"SLI_WIN_RD_ADDR"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1191},
+	{"SLI_WIN_RD_DATA"             ,	              0x40ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1192},
+	{"SLI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1193},
+	{"SLI_WIN_WR_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1194},
+	{"SLI_WIN_WR_MASK"             ,	              0x30ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1195},
+	{"SLI_WINDOW_CTL"              ,	   0x11f00000102e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1196},
+	{"SMI0_CLK"                    ,	   0x1180000003818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1197},
+	{"SMI1_CLK"                    ,	   0x1180000003898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1197},
+	{"SMI2_CLK"                    ,	   0x1180000003918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1197},
+	{"SMI3_CLK"                    ,	   0x1180000003998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1197},
+	{"SMI0_CMD"                    ,	   0x1180000003800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1198},
+	{"SMI1_CMD"                    ,	   0x1180000003880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1198},
+	{"SMI2_CMD"                    ,	   0x1180000003900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1198},
+	{"SMI3_CMD"                    ,	   0x1180000003980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1198},
+	{"SMI0_EN"                     ,	   0x1180000003820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1199},
+	{"SMI1_EN"                     ,	   0x11800000038a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1199},
+	{"SMI2_EN"                     ,	   0x1180000003920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1199},
+	{"SMI3_EN"                     ,	   0x11800000039a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1199},
+	{"SMI0_RD_DAT"                 ,	   0x1180000003810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1200},
+	{"SMI1_RD_DAT"                 ,	   0x1180000003890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1200},
+	{"SMI2_RD_DAT"                 ,	   0x1180000003910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1200},
+	{"SMI3_RD_DAT"                 ,	   0x1180000003990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1200},
+	{"SMI0_WR_DAT"                 ,	   0x1180000003808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1201},
+	{"SMI1_WR_DAT"                 ,	   0x1180000003888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1201},
+	{"SMI2_WR_DAT"                 ,	   0x1180000003908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1201},
+	{"SMI3_WR_DAT"                 ,	   0x1180000003988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1201},
+	{"SMI_DRV_CTL"                 ,	   0x1180000001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1202},
+	{"SSO_BIST_STAT"               ,	   0x1670000001078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1203},
+	{"SSO_CFG"                     ,	   0x1670000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1204},
+	{"SSO_DS_PC"                   ,	   0x1670000001070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1205},
+	{"SSO_ERR"                     ,	   0x1670000001038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1206},
+	{"SSO_ERR_ENB"                 ,	   0x1670000001030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1207},
+	{"SSO_FIDX_ECC_CTL"            ,	   0x16700000010d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1208},
+	{"SSO_FIDX_ECC_ST"             ,	   0x16700000010d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1209},
+	{"SSO_FPAGE_CNT"               ,	   0x1670000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1210},
+	{"SSO_GWE_CFG"                 ,	   0x1670000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1211},
+	{"SSO_IDX_ECC_CTL"             ,	   0x16700000010c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1212},
+	{"SSO_IDX_ECC_ST"              ,	   0x16700000010c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1213},
+	{"SSO_IQ_CNT0"                 ,	   0x1670000009000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1214},
+	{"SSO_IQ_CNT1"                 ,	   0x1670000009008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1214},
+	{"SSO_IQ_CNT2"                 ,	   0x1670000009010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1214},
+	{"SSO_IQ_CNT3"                 ,	   0x1670000009018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1214},
+	{"SSO_IQ_CNT4"                 ,	   0x1670000009020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1214},
+	{"SSO_IQ_CNT5"                 ,	   0x1670000009028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1214},
+	{"SSO_IQ_CNT6"                 ,	   0x1670000009030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1214},
+	{"SSO_IQ_CNT7"                 ,	   0x1670000009038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1214},
+	{"SSO_IQ_COM_CNT"              ,	   0x1670000001058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1215},
+	{"SSO_IQ_INT"                  ,	   0x1670000001048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1216},
+	{"SSO_IQ_INT_EN"               ,	   0x1670000001050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1217},
+	{"SSO_IQ_THR0"                 ,	   0x167000000a000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1218},
+	{"SSO_IQ_THR1"                 ,	   0x167000000a008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1218},
+	{"SSO_IQ_THR2"                 ,	   0x167000000a010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1218},
+	{"SSO_IQ_THR3"                 ,	   0x167000000a018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1218},
+	{"SSO_IQ_THR4"                 ,	   0x167000000a020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1218},
+	{"SSO_IQ_THR5"                 ,	   0x167000000a028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1218},
+	{"SSO_IQ_THR6"                 ,	   0x167000000a030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1218},
+	{"SSO_IQ_THR7"                 ,	   0x167000000a038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1218},
+	{"SSO_NOS_CNT"                 ,	   0x1670000001040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1219},
+	{"SSO_NW_TIM"                  ,	   0x1670000001028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1220},
+	{"SSO_OTH_ECC_CTL"             ,	   0x16700000010b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1221},
+	{"SSO_OTH_ECC_ST"              ,	   0x16700000010b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1222},
+	{"SSO_PND_ECC_CTL"             ,	   0x16700000010a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1223},
+	{"SSO_PND_ECC_ST"              ,	   0x16700000010a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1224},
+	{"SSO_PP0_GRP_MSK"             ,	   0x1670000006000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP1_GRP_MSK"             ,	   0x1670000006008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP2_GRP_MSK"             ,	   0x1670000006010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP3_GRP_MSK"             ,	   0x1670000006018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP4_GRP_MSK"             ,	   0x1670000006020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP5_GRP_MSK"             ,	   0x1670000006028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP6_GRP_MSK"             ,	   0x1670000006030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP7_GRP_MSK"             ,	   0x1670000006038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP8_GRP_MSK"             ,	   0x1670000006040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP9_GRP_MSK"             ,	   0x1670000006048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP10_GRP_MSK"            ,	   0x1670000006050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP11_GRP_MSK"            ,	   0x1670000006058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP12_GRP_MSK"            ,	   0x1670000006060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP13_GRP_MSK"            ,	   0x1670000006068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP14_GRP_MSK"            ,	   0x1670000006070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP15_GRP_MSK"            ,	   0x1670000006078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP16_GRP_MSK"            ,	   0x1670000006080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP17_GRP_MSK"            ,	   0x1670000006088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP18_GRP_MSK"            ,	   0x1670000006090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP19_GRP_MSK"            ,	   0x1670000006098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP20_GRP_MSK"            ,	   0x16700000060a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP21_GRP_MSK"            ,	   0x16700000060a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP22_GRP_MSK"            ,	   0x16700000060b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP23_GRP_MSK"            ,	   0x16700000060b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP24_GRP_MSK"            ,	   0x16700000060c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP25_GRP_MSK"            ,	   0x16700000060c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP26_GRP_MSK"            ,	   0x16700000060d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP27_GRP_MSK"            ,	   0x16700000060d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP28_GRP_MSK"            ,	   0x16700000060e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP29_GRP_MSK"            ,	   0x16700000060e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP30_GRP_MSK"            ,	   0x16700000060f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP31_GRP_MSK"            ,	   0x16700000060f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_PP0_QOS_PRI"             ,	   0x1670000003000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP1_QOS_PRI"             ,	   0x1670000003008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP2_QOS_PRI"             ,	   0x1670000003010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP3_QOS_PRI"             ,	   0x1670000003018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP4_QOS_PRI"             ,	   0x1670000003020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP5_QOS_PRI"             ,	   0x1670000003028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP6_QOS_PRI"             ,	   0x1670000003030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP7_QOS_PRI"             ,	   0x1670000003038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP8_QOS_PRI"             ,	   0x1670000003040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP9_QOS_PRI"             ,	   0x1670000003048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP10_QOS_PRI"            ,	   0x1670000003050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP11_QOS_PRI"            ,	   0x1670000003058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP12_QOS_PRI"            ,	   0x1670000003060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP13_QOS_PRI"            ,	   0x1670000003068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP14_QOS_PRI"            ,	   0x1670000003070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP15_QOS_PRI"            ,	   0x1670000003078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP16_QOS_PRI"            ,	   0x1670000003080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP17_QOS_PRI"            ,	   0x1670000003088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP18_QOS_PRI"            ,	   0x1670000003090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP19_QOS_PRI"            ,	   0x1670000003098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP20_QOS_PRI"            ,	   0x16700000030a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP21_QOS_PRI"            ,	   0x16700000030a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP22_QOS_PRI"            ,	   0x16700000030b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP23_QOS_PRI"            ,	   0x16700000030b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP24_QOS_PRI"            ,	   0x16700000030c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP25_QOS_PRI"            ,	   0x16700000030c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP26_QOS_PRI"            ,	   0x16700000030d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP27_QOS_PRI"            ,	   0x16700000030d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP28_QOS_PRI"            ,	   0x16700000030e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP29_QOS_PRI"            ,	   0x16700000030e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP30_QOS_PRI"            ,	   0x16700000030f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP31_QOS_PRI"            ,	   0x16700000030f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_PP_STRICT"               ,	   0x16700000010e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1227},
+	{"SSO_QOS0_RND"                ,	   0x1670000002000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1228},
+	{"SSO_QOS1_RND"                ,	   0x1670000002008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1228},
+	{"SSO_QOS2_RND"                ,	   0x1670000002010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1228},
+	{"SSO_QOS3_RND"                ,	   0x1670000002018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1228},
+	{"SSO_QOS4_RND"                ,	   0x1670000002020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1228},
+	{"SSO_QOS5_RND"                ,	   0x1670000002028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1228},
+	{"SSO_QOS6_RND"                ,	   0x1670000002030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1228},
+	{"SSO_QOS7_RND"                ,	   0x1670000002038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1228},
+	{"SSO_QOS_THR0"                ,	   0x167000000b000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1229},
+	{"SSO_QOS_THR1"                ,	   0x167000000b008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1229},
+	{"SSO_QOS_THR2"                ,	   0x167000000b010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1229},
+	{"SSO_QOS_THR3"                ,	   0x167000000b018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1229},
+	{"SSO_QOS_THR4"                ,	   0x167000000b020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1229},
+	{"SSO_QOS_THR5"                ,	   0x167000000b028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1229},
+	{"SSO_QOS_THR6"                ,	   0x167000000b030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1229},
+	{"SSO_QOS_THR7"                ,	   0x167000000b038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1229},
+	{"SSO_QOS_WE"                  ,	   0x1670000001080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1230},
+	{"SSO_RWQ_HEAD_PTR0"           ,	   0x167000000c000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1231},
+	{"SSO_RWQ_HEAD_PTR1"           ,	   0x167000000c008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1231},
+	{"SSO_RWQ_HEAD_PTR2"           ,	   0x167000000c010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1231},
+	{"SSO_RWQ_HEAD_PTR3"           ,	   0x167000000c018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1231},
+	{"SSO_RWQ_HEAD_PTR4"           ,	   0x167000000c020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1231},
+	{"SSO_RWQ_HEAD_PTR5"           ,	   0x167000000c028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1231},
+	{"SSO_RWQ_HEAD_PTR6"           ,	   0x167000000c030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1231},
+	{"SSO_RWQ_HEAD_PTR7"           ,	   0x167000000c038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1231},
+	{"SSO_RWQ_POP_FPTR"            ,	   0x167000000c408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1232},
+	{"SSO_RWQ_PSH_FPTR"            ,	   0x167000000c400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1233},
+	{"SSO_RWQ_TAIL_PTR0"           ,	   0x167000000c200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1234},
+	{"SSO_RWQ_TAIL_PTR1"           ,	   0x167000000c208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1234},
+	{"SSO_RWQ_TAIL_PTR2"           ,	   0x167000000c210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1234},
+	{"SSO_RWQ_TAIL_PTR3"           ,	   0x167000000c218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1234},
+	{"SSO_RWQ_TAIL_PTR4"           ,	   0x167000000c220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1234},
+	{"SSO_RWQ_TAIL_PTR5"           ,	   0x167000000c228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1234},
+	{"SSO_RWQ_TAIL_PTR6"           ,	   0x167000000c230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1234},
+	{"SSO_RWQ_TAIL_PTR7"           ,	   0x167000000c238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1234},
+	{"SSO_TS_PC"                   ,	   0x1670000001068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1235},
+	{"SSO_WA_COM_PC"               ,	   0x1670000001060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1236},
+	{"SSO_WA_PC0"                  ,	   0x1670000005000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1237},
+	{"SSO_WA_PC1"                  ,	   0x1670000005008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1237},
+	{"SSO_WA_PC2"                  ,	   0x1670000005010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1237},
+	{"SSO_WA_PC3"                  ,	   0x1670000005018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1237},
+	{"SSO_WA_PC4"                  ,	   0x1670000005020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1237},
+	{"SSO_WA_PC5"                  ,	   0x1670000005028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1237},
+	{"SSO_WA_PC6"                  ,	   0x1670000005030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1237},
+	{"SSO_WA_PC7"                  ,	   0x1670000005038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1237},
+	{"SSO_WQ_INT"                  ,	   0x1670000001000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1238},
+	{"SSO_WQ_INT_CNT0"             ,	   0x1670000008000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT1"             ,	   0x1670000008008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT2"             ,	   0x1670000008010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT3"             ,	   0x1670000008018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT4"             ,	   0x1670000008020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT5"             ,	   0x1670000008028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT6"             ,	   0x1670000008030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT7"             ,	   0x1670000008038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT8"             ,	   0x1670000008040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT9"             ,	   0x1670000008048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT10"            ,	   0x1670000008050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT11"            ,	   0x1670000008058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT12"            ,	   0x1670000008060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT13"            ,	   0x1670000008068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT14"            ,	   0x1670000008070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT15"            ,	   0x1670000008078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT16"            ,	   0x1670000008080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT17"            ,	   0x1670000008088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT18"            ,	   0x1670000008090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT19"            ,	   0x1670000008098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT20"            ,	   0x16700000080a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT21"            ,	   0x16700000080a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT22"            ,	   0x16700000080b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT23"            ,	   0x16700000080b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT24"            ,	   0x16700000080c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT25"            ,	   0x16700000080c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT26"            ,	   0x16700000080d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT27"            ,	   0x16700000080d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT28"            ,	   0x16700000080e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT29"            ,	   0x16700000080e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT30"            ,	   0x16700000080f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT31"            ,	   0x16700000080f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT32"            ,	   0x1670000008100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT33"            ,	   0x1670000008108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT34"            ,	   0x1670000008110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT35"            ,	   0x1670000008118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT36"            ,	   0x1670000008120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT37"            ,	   0x1670000008128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT38"            ,	   0x1670000008130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT39"            ,	   0x1670000008138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT40"            ,	   0x1670000008140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT41"            ,	   0x1670000008148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT42"            ,	   0x1670000008150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT43"            ,	   0x1670000008158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT44"            ,	   0x1670000008160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT45"            ,	   0x1670000008168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT46"            ,	   0x1670000008170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT47"            ,	   0x1670000008178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT48"            ,	   0x1670000008180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT49"            ,	   0x1670000008188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT50"            ,	   0x1670000008190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT51"            ,	   0x1670000008198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT52"            ,	   0x16700000081a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT53"            ,	   0x16700000081a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT54"            ,	   0x16700000081b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT55"            ,	   0x16700000081b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT56"            ,	   0x16700000081c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT57"            ,	   0x16700000081c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT58"            ,	   0x16700000081d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT59"            ,	   0x16700000081d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT60"            ,	   0x16700000081e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT61"            ,	   0x16700000081e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT62"            ,	   0x16700000081f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_CNT63"            ,	   0x16700000081f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_WQ_INT_PC"               ,	   0x1670000001020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1240},
+	{"SSO_WQ_INT_THR0"             ,	   0x1670000007000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR1"             ,	   0x1670000007008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR2"             ,	   0x1670000007010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR3"             ,	   0x1670000007018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR4"             ,	   0x1670000007020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR5"             ,	   0x1670000007028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR6"             ,	   0x1670000007030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR7"             ,	   0x1670000007038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR8"             ,	   0x1670000007040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR9"             ,	   0x1670000007048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR10"            ,	   0x1670000007050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR11"            ,	   0x1670000007058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR12"            ,	   0x1670000007060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR13"            ,	   0x1670000007068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR14"            ,	   0x1670000007070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR15"            ,	   0x1670000007078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR16"            ,	   0x1670000007080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR17"            ,	   0x1670000007088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR18"            ,	   0x1670000007090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR19"            ,	   0x1670000007098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR20"            ,	   0x16700000070a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR21"            ,	   0x16700000070a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR22"            ,	   0x16700000070b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR23"            ,	   0x16700000070b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR24"            ,	   0x16700000070c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR25"            ,	   0x16700000070c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR26"            ,	   0x16700000070d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR27"            ,	   0x16700000070d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR28"            ,	   0x16700000070e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR29"            ,	   0x16700000070e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR30"            ,	   0x16700000070f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR31"            ,	   0x16700000070f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR32"            ,	   0x1670000007100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR33"            ,	   0x1670000007108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR34"            ,	   0x1670000007110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR35"            ,	   0x1670000007118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR36"            ,	   0x1670000007120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR37"            ,	   0x1670000007128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR38"            ,	   0x1670000007130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR39"            ,	   0x1670000007138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR40"            ,	   0x1670000007140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR41"            ,	   0x1670000007148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR42"            ,	   0x1670000007150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR43"            ,	   0x1670000007158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR44"            ,	   0x1670000007160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR45"            ,	   0x1670000007168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR46"            ,	   0x1670000007170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR47"            ,	   0x1670000007178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR48"            ,	   0x1670000007180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR49"            ,	   0x1670000007188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR50"            ,	   0x1670000007190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR51"            ,	   0x1670000007198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR52"            ,	   0x16700000071a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR53"            ,	   0x16700000071a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR54"            ,	   0x16700000071b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR55"            ,	   0x16700000071b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR56"            ,	   0x16700000071c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR57"            ,	   0x16700000071c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR58"            ,	   0x16700000071d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR59"            ,	   0x16700000071d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR60"            ,	   0x16700000071e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR61"            ,	   0x16700000071e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR62"            ,	   0x16700000071f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_INT_THR63"            ,	   0x16700000071f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_WQ_IQ_DIS"               ,	   0x1670000001010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1242},
+	{"SSO_WS_PC0"                  ,	   0x1670000004000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC1"                  ,	   0x1670000004008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC2"                  ,	   0x1670000004010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC3"                  ,	   0x1670000004018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC4"                  ,	   0x1670000004020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC5"                  ,	   0x1670000004028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC6"                  ,	   0x1670000004030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC7"                  ,	   0x1670000004038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC8"                  ,	   0x1670000004040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC9"                  ,	   0x1670000004048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC10"                 ,	   0x1670000004050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC11"                 ,	   0x1670000004058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC12"                 ,	   0x1670000004060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC13"                 ,	   0x1670000004068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC14"                 ,	   0x1670000004070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC15"                 ,	   0x1670000004078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC16"                 ,	   0x1670000004080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC17"                 ,	   0x1670000004088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC18"                 ,	   0x1670000004090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC19"                 ,	   0x1670000004098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC20"                 ,	   0x16700000040a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC21"                 ,	   0x16700000040a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC22"                 ,	   0x16700000040b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC23"                 ,	   0x16700000040b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC24"                 ,	   0x16700000040c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC25"                 ,	   0x16700000040c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC26"                 ,	   0x16700000040d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC27"                 ,	   0x16700000040d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC28"                 ,	   0x16700000040e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC29"                 ,	   0x16700000040e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC30"                 ,	   0x16700000040f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC31"                 ,	   0x16700000040f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC32"                 ,	   0x1670000004100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC33"                 ,	   0x1670000004108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC34"                 ,	   0x1670000004110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC35"                 ,	   0x1670000004118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC36"                 ,	   0x1670000004120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC37"                 ,	   0x1670000004128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC38"                 ,	   0x1670000004130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC39"                 ,	   0x1670000004138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC40"                 ,	   0x1670000004140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC41"                 ,	   0x1670000004148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC42"                 ,	   0x1670000004150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC43"                 ,	   0x1670000004158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC44"                 ,	   0x1670000004160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC45"                 ,	   0x1670000004168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC46"                 ,	   0x1670000004170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC47"                 ,	   0x1670000004178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC48"                 ,	   0x1670000004180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC49"                 ,	   0x1670000004188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC50"                 ,	   0x1670000004190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC51"                 ,	   0x1670000004198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC52"                 ,	   0x16700000041a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC53"                 ,	   0x16700000041a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC54"                 ,	   0x16700000041b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC55"                 ,	   0x16700000041b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC56"                 ,	   0x16700000041c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC57"                 ,	   0x16700000041c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC58"                 ,	   0x16700000041d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC59"                 ,	   0x16700000041d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC60"                 ,	   0x16700000041e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC61"                 ,	   0x16700000041e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC62"                 ,	   0x16700000041f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_WS_PC63"                 ,	   0x16700000041f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"TIM_BIST_RESULT"             ,	   0x1180058000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1244},
+	{"TIM_DBG2"                    ,	   0x11800580000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1245},
+	{"TIM_DBG3"                    ,	   0x11800580000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1246},
+	{"TIM_ECC_CFG"                 ,	   0x1180058000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1247},
+	{"TIM_FR_RN_TT"                ,	   0x1180058000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1248},
+	{"TIM_INT0"                    ,	   0x1180058000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1249},
+	{"TIM_INT0_EN"                 ,	   0x1180058000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1250},
+	{"TIM_INT0_EVENT"              ,	   0x1180058000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1251},
+	{"TIM_INT_ECCERR"              ,	   0x1180058000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1252},
+	{"TIM_INT_ECCERR_EN"           ,	   0x1180058000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1253},
+	{"TIM_INT_ECCERR_EVENT0"       ,	   0x1180058000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1254},
+	{"TIM_INT_ECCERR_EVENT1"       ,	   0x1180058000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1255},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1256},
+	{"TIM_RING0_CTL0"              ,	   0x1180058002000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING1_CTL0"              ,	   0x1180058002008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING2_CTL0"              ,	   0x1180058002010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING3_CTL0"              ,	   0x1180058002018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING4_CTL0"              ,	   0x1180058002020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING5_CTL0"              ,	   0x1180058002028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING6_CTL0"              ,	   0x1180058002030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING7_CTL0"              ,	   0x1180058002038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING8_CTL0"              ,	   0x1180058002040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING9_CTL0"              ,	   0x1180058002048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING10_CTL0"             ,	   0x1180058002050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING11_CTL0"             ,	   0x1180058002058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING12_CTL0"             ,	   0x1180058002060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING13_CTL0"             ,	   0x1180058002068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING14_CTL0"             ,	   0x1180058002070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING15_CTL0"             ,	   0x1180058002078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING16_CTL0"             ,	   0x1180058002080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING17_CTL0"             ,	   0x1180058002088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING18_CTL0"             ,	   0x1180058002090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING19_CTL0"             ,	   0x1180058002098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING20_CTL0"             ,	   0x11800580020a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING21_CTL0"             ,	   0x11800580020a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING22_CTL0"             ,	   0x11800580020b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING23_CTL0"             ,	   0x11800580020b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING24_CTL0"             ,	   0x11800580020c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING25_CTL0"             ,	   0x11800580020c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING26_CTL0"             ,	   0x11800580020d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING27_CTL0"             ,	   0x11800580020d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING28_CTL0"             ,	   0x11800580020e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING29_CTL0"             ,	   0x11800580020e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING30_CTL0"             ,	   0x11800580020f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING31_CTL0"             ,	   0x11800580020f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING32_CTL0"             ,	   0x1180058002100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING33_CTL0"             ,	   0x1180058002108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING34_CTL0"             ,	   0x1180058002110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING35_CTL0"             ,	   0x1180058002118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING36_CTL0"             ,	   0x1180058002120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING37_CTL0"             ,	   0x1180058002128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING38_CTL0"             ,	   0x1180058002130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING39_CTL0"             ,	   0x1180058002138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING40_CTL0"             ,	   0x1180058002140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING41_CTL0"             ,	   0x1180058002148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING42_CTL0"             ,	   0x1180058002150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING43_CTL0"             ,	   0x1180058002158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING44_CTL0"             ,	   0x1180058002160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING45_CTL0"             ,	   0x1180058002168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING46_CTL0"             ,	   0x1180058002170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING47_CTL0"             ,	   0x1180058002178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING48_CTL0"             ,	   0x1180058002180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING49_CTL0"             ,	   0x1180058002188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING50_CTL0"             ,	   0x1180058002190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING51_CTL0"             ,	   0x1180058002198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING52_CTL0"             ,	   0x11800580021a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING53_CTL0"             ,	   0x11800580021a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING54_CTL0"             ,	   0x11800580021b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING55_CTL0"             ,	   0x11800580021b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING56_CTL0"             ,	   0x11800580021c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING57_CTL0"             ,	   0x11800580021c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING58_CTL0"             ,	   0x11800580021d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING59_CTL0"             ,	   0x11800580021d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING60_CTL0"             ,	   0x11800580021e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING61_CTL0"             ,	   0x11800580021e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING62_CTL0"             ,	   0x11800580021f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING63_CTL0"             ,	   0x11800580021f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1257},
+	{"TIM_RING0_CTL1"              ,	   0x1180058002400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING1_CTL1"              ,	   0x1180058002408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING2_CTL1"              ,	   0x1180058002410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING3_CTL1"              ,	   0x1180058002418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING4_CTL1"              ,	   0x1180058002420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING5_CTL1"              ,	   0x1180058002428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING6_CTL1"              ,	   0x1180058002430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING7_CTL1"              ,	   0x1180058002438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING8_CTL1"              ,	   0x1180058002440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING9_CTL1"              ,	   0x1180058002448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING10_CTL1"             ,	   0x1180058002450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING11_CTL1"             ,	   0x1180058002458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING12_CTL1"             ,	   0x1180058002460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING13_CTL1"             ,	   0x1180058002468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING14_CTL1"             ,	   0x1180058002470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING15_CTL1"             ,	   0x1180058002478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING16_CTL1"             ,	   0x1180058002480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING17_CTL1"             ,	   0x1180058002488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING18_CTL1"             ,	   0x1180058002490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING19_CTL1"             ,	   0x1180058002498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING20_CTL1"             ,	   0x11800580024a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING21_CTL1"             ,	   0x11800580024a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING22_CTL1"             ,	   0x11800580024b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING23_CTL1"             ,	   0x11800580024b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING24_CTL1"             ,	   0x11800580024c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING25_CTL1"             ,	   0x11800580024c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING26_CTL1"             ,	   0x11800580024d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING27_CTL1"             ,	   0x11800580024d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING28_CTL1"             ,	   0x11800580024e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING29_CTL1"             ,	   0x11800580024e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING30_CTL1"             ,	   0x11800580024f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING31_CTL1"             ,	   0x11800580024f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING32_CTL1"             ,	   0x1180058002500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING33_CTL1"             ,	   0x1180058002508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING34_CTL1"             ,	   0x1180058002510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING35_CTL1"             ,	   0x1180058002518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING36_CTL1"             ,	   0x1180058002520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING37_CTL1"             ,	   0x1180058002528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING38_CTL1"             ,	   0x1180058002530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING39_CTL1"             ,	   0x1180058002538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING40_CTL1"             ,	   0x1180058002540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING41_CTL1"             ,	   0x1180058002548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING42_CTL1"             ,	   0x1180058002550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING43_CTL1"             ,	   0x1180058002558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING44_CTL1"             ,	   0x1180058002560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING45_CTL1"             ,	   0x1180058002568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING46_CTL1"             ,	   0x1180058002570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING47_CTL1"             ,	   0x1180058002578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING48_CTL1"             ,	   0x1180058002580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING49_CTL1"             ,	   0x1180058002588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING50_CTL1"             ,	   0x1180058002590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING51_CTL1"             ,	   0x1180058002598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING52_CTL1"             ,	   0x11800580025a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING53_CTL1"             ,	   0x11800580025a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING54_CTL1"             ,	   0x11800580025b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING55_CTL1"             ,	   0x11800580025b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING56_CTL1"             ,	   0x11800580025c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING57_CTL1"             ,	   0x11800580025c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING58_CTL1"             ,	   0x11800580025d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING59_CTL1"             ,	   0x11800580025d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING60_CTL1"             ,	   0x11800580025e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING61_CTL1"             ,	   0x11800580025e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING62_CTL1"             ,	   0x11800580025f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING63_CTL1"             ,	   0x11800580025f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1258},
+	{"TIM_RING0_CTL2"              ,	   0x1180058002800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING1_CTL2"              ,	   0x1180058002808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING2_CTL2"              ,	   0x1180058002810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING3_CTL2"              ,	   0x1180058002818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING4_CTL2"              ,	   0x1180058002820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING5_CTL2"              ,	   0x1180058002828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING6_CTL2"              ,	   0x1180058002830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING7_CTL2"              ,	   0x1180058002838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING8_CTL2"              ,	   0x1180058002840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING9_CTL2"              ,	   0x1180058002848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING10_CTL2"             ,	   0x1180058002850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING11_CTL2"             ,	   0x1180058002858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING12_CTL2"             ,	   0x1180058002860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING13_CTL2"             ,	   0x1180058002868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING14_CTL2"             ,	   0x1180058002870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING15_CTL2"             ,	   0x1180058002878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING16_CTL2"             ,	   0x1180058002880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING17_CTL2"             ,	   0x1180058002888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING18_CTL2"             ,	   0x1180058002890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING19_CTL2"             ,	   0x1180058002898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING20_CTL2"             ,	   0x11800580028a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING21_CTL2"             ,	   0x11800580028a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING22_CTL2"             ,	   0x11800580028b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING23_CTL2"             ,	   0x11800580028b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING24_CTL2"             ,	   0x11800580028c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING25_CTL2"             ,	   0x11800580028c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING26_CTL2"             ,	   0x11800580028d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING27_CTL2"             ,	   0x11800580028d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING28_CTL2"             ,	   0x11800580028e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING29_CTL2"             ,	   0x11800580028e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING30_CTL2"             ,	   0x11800580028f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING31_CTL2"             ,	   0x11800580028f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING32_CTL2"             ,	   0x1180058002900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING33_CTL2"             ,	   0x1180058002908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING34_CTL2"             ,	   0x1180058002910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING35_CTL2"             ,	   0x1180058002918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING36_CTL2"             ,	   0x1180058002920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING37_CTL2"             ,	   0x1180058002928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING38_CTL2"             ,	   0x1180058002930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING39_CTL2"             ,	   0x1180058002938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING40_CTL2"             ,	   0x1180058002940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING41_CTL2"             ,	   0x1180058002948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING42_CTL2"             ,	   0x1180058002950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING43_CTL2"             ,	   0x1180058002958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING44_CTL2"             ,	   0x1180058002960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING45_CTL2"             ,	   0x1180058002968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING46_CTL2"             ,	   0x1180058002970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING47_CTL2"             ,	   0x1180058002978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING48_CTL2"             ,	   0x1180058002980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING49_CTL2"             ,	   0x1180058002988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING50_CTL2"             ,	   0x1180058002990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING51_CTL2"             ,	   0x1180058002998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING52_CTL2"             ,	   0x11800580029a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING53_CTL2"             ,	   0x11800580029a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING54_CTL2"             ,	   0x11800580029b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING55_CTL2"             ,	   0x11800580029b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING56_CTL2"             ,	   0x11800580029c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING57_CTL2"             ,	   0x11800580029c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING58_CTL2"             ,	   0x11800580029d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING59_CTL2"             ,	   0x11800580029d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING60_CTL2"             ,	   0x11800580029e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING61_CTL2"             ,	   0x11800580029e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING62_CTL2"             ,	   0x11800580029f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING63_CTL2"             ,	   0x11800580029f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1259},
+	{"TIM_RING0_DBG0"              ,	   0x1180058003000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING1_DBG0"              ,	   0x1180058003008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING2_DBG0"              ,	   0x1180058003010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING3_DBG0"              ,	   0x1180058003018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING4_DBG0"              ,	   0x1180058003020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING5_DBG0"              ,	   0x1180058003028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING6_DBG0"              ,	   0x1180058003030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING7_DBG0"              ,	   0x1180058003038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING8_DBG0"              ,	   0x1180058003040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING9_DBG0"              ,	   0x1180058003048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING10_DBG0"             ,	   0x1180058003050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING11_DBG0"             ,	   0x1180058003058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING12_DBG0"             ,	   0x1180058003060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING13_DBG0"             ,	   0x1180058003068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING14_DBG0"             ,	   0x1180058003070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING15_DBG0"             ,	   0x1180058003078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING16_DBG0"             ,	   0x1180058003080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING17_DBG0"             ,	   0x1180058003088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING18_DBG0"             ,	   0x1180058003090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING19_DBG0"             ,	   0x1180058003098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING20_DBG0"             ,	   0x11800580030a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING21_DBG0"             ,	   0x11800580030a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING22_DBG0"             ,	   0x11800580030b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING23_DBG0"             ,	   0x11800580030b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING24_DBG0"             ,	   0x11800580030c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING25_DBG0"             ,	   0x11800580030c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING26_DBG0"             ,	   0x11800580030d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING27_DBG0"             ,	   0x11800580030d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING28_DBG0"             ,	   0x11800580030e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING29_DBG0"             ,	   0x11800580030e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING30_DBG0"             ,	   0x11800580030f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING31_DBG0"             ,	   0x11800580030f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING32_DBG0"             ,	   0x1180058003100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING33_DBG0"             ,	   0x1180058003108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING34_DBG0"             ,	   0x1180058003110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING35_DBG0"             ,	   0x1180058003118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING36_DBG0"             ,	   0x1180058003120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING37_DBG0"             ,	   0x1180058003128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING38_DBG0"             ,	   0x1180058003130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING39_DBG0"             ,	   0x1180058003138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING40_DBG0"             ,	   0x1180058003140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING41_DBG0"             ,	   0x1180058003148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING42_DBG0"             ,	   0x1180058003150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING43_DBG0"             ,	   0x1180058003158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING44_DBG0"             ,	   0x1180058003160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING45_DBG0"             ,	   0x1180058003168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING46_DBG0"             ,	   0x1180058003170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING47_DBG0"             ,	   0x1180058003178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING48_DBG0"             ,	   0x1180058003180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING49_DBG0"             ,	   0x1180058003188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING50_DBG0"             ,	   0x1180058003190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING51_DBG0"             ,	   0x1180058003198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING52_DBG0"             ,	   0x11800580031a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING53_DBG0"             ,	   0x11800580031a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING54_DBG0"             ,	   0x11800580031b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING55_DBG0"             ,	   0x11800580031b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING56_DBG0"             ,	   0x11800580031c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING57_DBG0"             ,	   0x11800580031c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING58_DBG0"             ,	   0x11800580031d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING59_DBG0"             ,	   0x11800580031d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING60_DBG0"             ,	   0x11800580031e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING61_DBG0"             ,	   0x11800580031e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING62_DBG0"             ,	   0x11800580031f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING63_DBG0"             ,	   0x11800580031f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1260},
+	{"TIM_RING0_DBG1"              ,	   0x1180058001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING1_DBG1"              ,	   0x1180058001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING2_DBG1"              ,	   0x1180058001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING3_DBG1"              ,	   0x1180058001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING4_DBG1"              ,	   0x1180058001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING5_DBG1"              ,	   0x1180058001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING6_DBG1"              ,	   0x1180058001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING7_DBG1"              ,	   0x1180058001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING8_DBG1"              ,	   0x1180058001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING9_DBG1"              ,	   0x1180058001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING10_DBG1"             ,	   0x1180058001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING11_DBG1"             ,	   0x1180058001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING12_DBG1"             ,	   0x1180058001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING13_DBG1"             ,	   0x1180058001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING14_DBG1"             ,	   0x1180058001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING15_DBG1"             ,	   0x1180058001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING16_DBG1"             ,	   0x1180058001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING17_DBG1"             ,	   0x1180058001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING18_DBG1"             ,	   0x1180058001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING19_DBG1"             ,	   0x1180058001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING20_DBG1"             ,	   0x11800580012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING21_DBG1"             ,	   0x11800580012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING22_DBG1"             ,	   0x11800580012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING23_DBG1"             ,	   0x11800580012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING24_DBG1"             ,	   0x11800580012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING25_DBG1"             ,	   0x11800580012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING26_DBG1"             ,	   0x11800580012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING27_DBG1"             ,	   0x11800580012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING28_DBG1"             ,	   0x11800580012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING29_DBG1"             ,	   0x11800580012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING30_DBG1"             ,	   0x11800580012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING31_DBG1"             ,	   0x11800580012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING32_DBG1"             ,	   0x1180058001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING33_DBG1"             ,	   0x1180058001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING34_DBG1"             ,	   0x1180058001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING35_DBG1"             ,	   0x1180058001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING36_DBG1"             ,	   0x1180058001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING37_DBG1"             ,	   0x1180058001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING38_DBG1"             ,	   0x1180058001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING39_DBG1"             ,	   0x1180058001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING40_DBG1"             ,	   0x1180058001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING41_DBG1"             ,	   0x1180058001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING42_DBG1"             ,	   0x1180058001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING43_DBG1"             ,	   0x1180058001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING44_DBG1"             ,	   0x1180058001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING45_DBG1"             ,	   0x1180058001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING46_DBG1"             ,	   0x1180058001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING47_DBG1"             ,	   0x1180058001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING48_DBG1"             ,	   0x1180058001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING49_DBG1"             ,	   0x1180058001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING50_DBG1"             ,	   0x1180058001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING51_DBG1"             ,	   0x1180058001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING52_DBG1"             ,	   0x11800580013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING53_DBG1"             ,	   0x11800580013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING54_DBG1"             ,	   0x11800580013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING55_DBG1"             ,	   0x11800580013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING56_DBG1"             ,	   0x11800580013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING57_DBG1"             ,	   0x11800580013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING58_DBG1"             ,	   0x11800580013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING59_DBG1"             ,	   0x11800580013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING60_DBG1"             ,	   0x11800580013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING61_DBG1"             ,	   0x11800580013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING62_DBG1"             ,	   0x11800580013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TIM_RING63_DBG1"             ,	   0x11800580013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1261},
+	{"TRA0_BIST_STATUS"            ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1262},
+	{"TRA1_BIST_STATUS"            ,	   0x11800a8100010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1262},
+	{"TRA2_BIST_STATUS"            ,	   0x11800a8200010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1262},
+	{"TRA3_BIST_STATUS"            ,	   0x11800a8300010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1262},
+	{"TRA0_CTL"                    ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1263},
+	{"TRA1_CTL"                    ,	   0x11800a8100000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1263},
+	{"TRA2_CTL"                    ,	   0x11800a8200000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1263},
+	{"TRA3_CTL"                    ,	   0x11800a8300000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1263},
+	{"TRA0_CYCLES_SINCE"           ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1264},
+	{"TRA1_CYCLES_SINCE"           ,	   0x11800a8100018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1264},
+	{"TRA2_CYCLES_SINCE"           ,	   0x11800a8200018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1264},
+	{"TRA3_CYCLES_SINCE"           ,	   0x11800a8300018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1264},
+	{"TRA0_CYCLES_SINCE1"          ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1265},
+	{"TRA1_CYCLES_SINCE1"          ,	   0x11800a8100028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1265},
+	{"TRA2_CYCLES_SINCE1"          ,	   0x11800a8200028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1265},
+	{"TRA3_CYCLES_SINCE1"          ,	   0x11800a8300028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1265},
+	{"TRA0_FILT_ADR_ADR"           ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1266},
+	{"TRA1_FILT_ADR_ADR"           ,	   0x11800a8100058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1266},
+	{"TRA2_FILT_ADR_ADR"           ,	   0x11800a8200058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1266},
+	{"TRA3_FILT_ADR_ADR"           ,	   0x11800a8300058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1266},
+	{"TRA0_FILT_ADR_MSK"           ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1267},
+	{"TRA1_FILT_ADR_MSK"           ,	   0x11800a8100060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1267},
+	{"TRA2_FILT_ADR_MSK"           ,	   0x11800a8200060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1267},
+	{"TRA3_FILT_ADR_MSK"           ,	   0x11800a8300060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1267},
+	{"TRA0_FILT_CMD"               ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1268},
+	{"TRA1_FILT_CMD"               ,	   0x11800a8100040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1268},
+	{"TRA2_FILT_CMD"               ,	   0x11800a8200040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1268},
+	{"TRA3_FILT_CMD"               ,	   0x11800a8300040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1268},
+	{"TRA0_FILT_DID"               ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1269},
+	{"TRA1_FILT_DID"               ,	   0x11800a8100050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1269},
+	{"TRA2_FILT_DID"               ,	   0x11800a8200050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1269},
+	{"TRA3_FILT_DID"               ,	   0x11800a8300050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1269},
+	{"TRA0_FILT_SID"               ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1270},
+	{"TRA1_FILT_SID"               ,	   0x11800a8100048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1270},
+	{"TRA2_FILT_SID"               ,	   0x11800a8200048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1270},
+	{"TRA3_FILT_SID"               ,	   0x11800a8300048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1270},
+	{"TRA0_INT_STATUS"             ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1271},
+	{"TRA1_INT_STATUS"             ,	   0x11800a8100008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1271},
+	{"TRA2_INT_STATUS"             ,	   0x11800a8200008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1271},
+	{"TRA3_INT_STATUS"             ,	   0x11800a8300008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1271},
+	{"TRA0_READ_DAT"               ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1272},
+	{"TRA1_READ_DAT"               ,	   0x11800a8100020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1272},
+	{"TRA2_READ_DAT"               ,	   0x11800a8200020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1272},
+	{"TRA3_READ_DAT"               ,	   0x11800a8300020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1272},
+	{"TRA0_READ_DAT_HI"            ,	   0x11800a8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1273},
+	{"TRA1_READ_DAT_HI"            ,	   0x11800a8100030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1273},
+	{"TRA2_READ_DAT_HI"            ,	   0x11800a8200030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1273},
+	{"TRA3_READ_DAT_HI"            ,	   0x11800a8300030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1273},
+	{"TRA0_TRIG0_ADR_ADR"          ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1274},
+	{"TRA1_TRIG0_ADR_ADR"          ,	   0x11800a8100098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1274},
+	{"TRA2_TRIG0_ADR_ADR"          ,	   0x11800a8200098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1274},
+	{"TRA3_TRIG0_ADR_ADR"          ,	   0x11800a8300098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1274},
+	{"TRA0_TRIG0_ADR_MSK"          ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1275},
+	{"TRA1_TRIG0_ADR_MSK"          ,	   0x11800a81000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1275},
+	{"TRA2_TRIG0_ADR_MSK"          ,	   0x11800a82000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1275},
+	{"TRA3_TRIG0_ADR_MSK"          ,	   0x11800a83000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1275},
+	{"TRA0_TRIG0_CMD"              ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1276},
+	{"TRA1_TRIG0_CMD"              ,	   0x11800a8100080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1276},
+	{"TRA2_TRIG0_CMD"              ,	   0x11800a8200080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1276},
+	{"TRA3_TRIG0_CMD"              ,	   0x11800a8300080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1276},
+	{"TRA0_TRIG0_DID"              ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1277},
+	{"TRA1_TRIG0_DID"              ,	   0x11800a8100090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1277},
+	{"TRA2_TRIG0_DID"              ,	   0x11800a8200090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1277},
+	{"TRA3_TRIG0_DID"              ,	   0x11800a8300090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1277},
+	{"TRA0_TRIG0_SID"              ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1278},
+	{"TRA1_TRIG0_SID"              ,	   0x11800a8100088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1278},
+	{"TRA2_TRIG0_SID"              ,	   0x11800a8200088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1278},
+	{"TRA3_TRIG0_SID"              ,	   0x11800a8300088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1278},
+	{"TRA0_TRIG1_ADR_ADR"          ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1279},
+	{"TRA1_TRIG1_ADR_ADR"          ,	   0x11800a81000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1279},
+	{"TRA2_TRIG1_ADR_ADR"          ,	   0x11800a82000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1279},
+	{"TRA3_TRIG1_ADR_ADR"          ,	   0x11800a83000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1279},
+	{"TRA0_TRIG1_ADR_MSK"          ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1280},
+	{"TRA1_TRIG1_ADR_MSK"          ,	   0x11800a81000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1280},
+	{"TRA2_TRIG1_ADR_MSK"          ,	   0x11800a82000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1280},
+	{"TRA3_TRIG1_ADR_MSK"          ,	   0x11800a83000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1280},
+	{"TRA0_TRIG1_CMD"              ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TRA1_TRIG1_CMD"              ,	   0x11800a81000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TRA2_TRIG1_CMD"              ,	   0x11800a82000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TRA3_TRIG1_CMD"              ,	   0x11800a83000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TRA0_TRIG1_DID"              ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TRA1_TRIG1_DID"              ,	   0x11800a81000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TRA2_TRIG1_DID"              ,	   0x11800a82000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TRA3_TRIG1_DID"              ,	   0x11800a83000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TRA0_TRIG1_SID"              ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TRA1_TRIG1_SID"              ,	   0x11800a81000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TRA2_TRIG1_SID"              ,	   0x11800a82000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TRA3_TRIG1_SID"              ,	   0x11800a83000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"UAHC0_EHCI_ASYNCLISTADDR"    ,	   0x16f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1284},
+	{"UAHC0_EHCI_CONFIGFLAG"       ,	   0x16f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1285},
+	{"UAHC0_EHCI_CTRLDSSEGMENT"    ,	   0x16f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1286},
+	{"UAHC0_EHCI_FRINDEX"          ,	   0x16f000000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1287},
+	{"UAHC0_EHCI_HCCAPBASE"        ,	   0x16f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1288},
+	{"UAHC0_EHCI_HCCPARAMS"        ,	   0x16f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1289},
+	{"UAHC0_EHCI_HCSPARAMS"        ,	   0x16f0000000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1290},
+	{"UAHC0_EHCI_INSNREG00"        ,	   0x16f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1291},
+	{"UAHC0_EHCI_INSNREG03"        ,	   0x16f000000009cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1292},
+	{"UAHC0_EHCI_INSNREG04"        ,	   0x16f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1293},
+	{"UAHC0_EHCI_INSNREG06"        ,	   0x16f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1294},
+	{"UAHC0_EHCI_INSNREG07"        ,	   0x16f00000000ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	1295},
+	{"UAHC0_EHCI_PERIODICLISTBASE" ,	   0x16f0000000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1296},
+	{"UAHC0_EHCI_PORTSC001"        ,	   0x16f0000000054ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1297},
+	{"UAHC0_EHCI_PORTSC002"        ,	   0x16f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1297},
+	{"UAHC0_EHCI_USBCMD"           ,	   0x16f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1298},
+	{"UAHC0_EHCI_USBINTR"          ,	   0x16f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1299},
+	{"UAHC0_EHCI_USBSTS"           ,	   0x16f0000000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1300},
+	{"UAHC0_OHCI0_HCBULKCURRENTED" ,	   0x16f000000042cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1301},
+	{"UAHC0_OHCI0_HCBULKHEADED"    ,	   0x16f0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1302},
+	{"UAHC0_OHCI0_HCCOMMANDSTATUS" ,	   0x16f0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1303},
+	{"UAHC0_OHCI0_HCCONTROL"       ,	   0x16f0000000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1304},
+	{"UAHC0_OHCI0_HCCONTROLCURRENTED",	   0x16f0000000424ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1305},
+	{"UAHC0_OHCI0_HCCONTROLHEADED" ,	   0x16f0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1306},
+	{"UAHC0_OHCI0_HCDONEHEAD"      ,	   0x16f0000000430ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1307},
+	{"UAHC0_OHCI0_HCFMINTERVAL"    ,	   0x16f0000000434ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1308},
+	{"UAHC0_OHCI0_HCFMNUMBER"      ,	   0x16f000000043cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1309},
+	{"UAHC0_OHCI0_HCFMREMAINING"   ,	   0x16f0000000438ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1310},
+	{"UAHC0_OHCI0_HCHCCA"          ,	   0x16f0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1311},
+	{"UAHC0_OHCI0_HCINTERRUPTDISABLE",	   0x16f0000000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1312},
+	{"UAHC0_OHCI0_HCINTERRUPTENABLE",	   0x16f0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1313},
+	{"UAHC0_OHCI0_HCINTERRUPTSTATUS",	   0x16f000000040cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1314},
+	{"UAHC0_OHCI0_HCLSTHRESHOLD"   ,	   0x16f0000000444ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1315},
+	{"UAHC0_OHCI0_HCPERIODCURRENTED",	   0x16f000000041cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1316},
+	{"UAHC0_OHCI0_HCPERIODICSTART" ,	   0x16f0000000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1317},
+	{"UAHC0_OHCI0_HCREVISION"      ,	   0x16f0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1318},
+	{"UAHC0_OHCI0_HCRHDESCRIPTORA" ,	   0x16f0000000448ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1319},
+	{"UAHC0_OHCI0_HCRHDESCRIPTORB" ,	   0x16f000000044cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1320},
+	{"UAHC0_OHCI0_HCRHPORTSTATUS001",	   0x16f0000000454ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1321},
+	{"UAHC0_OHCI0_HCRHPORTSTATUS002",	   0x16f0000000458ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1321},
+	{"UAHC0_OHCI0_HCRHSTATUS"      ,	   0x16f0000000450ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1322},
+	{"UAHC0_OHCI0_INSNREG06"       ,	   0x16f0000000498ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1323},
+	{"UAHC0_OHCI0_INSNREG07"       ,	   0x16f000000049cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1324},
+	{"UCTL0_BIST_STATUS"           ,	   0x118006f0000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1325},
+	{"UCTL0_CLK_RST_CTL"           ,	   0x118006f000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1326},
+	{"UCTL0_EHCI_CTL"              ,	   0x118006f000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1327},
+	{"UCTL0_EHCI_FLA"              ,	   0x118006f0000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1328},
+	{"UCTL0_ERTO_CTL"              ,	   0x118006f000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1329},
+	{"UCTL0_IF_ENA"                ,	   0x118006f000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1330},
+	{"UCTL0_INT_ENA"               ,	   0x118006f000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1331},
+	{"UCTL0_INT_REG"               ,	   0x118006f000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1332},
+	{"UCTL0_OHCI_CTL"              ,	   0x118006f000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1333},
+	{"UCTL0_ORTO_CTL"              ,	   0x118006f000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1334},
+	{"UCTL0_UPHY_CTL_STATUS"       ,	   0x118006f000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1335},
+	{"UCTL0_UPHY_PORT000_CTL_STATUS",	   0x118006f000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1336},
+	{"UCTL0_UPHY_PORT001_CTL_STATUS",	   0x118006f000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1336},
+	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1337},
+	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1338},
+	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1339},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1340},
+	{"ZIP_CORE0_BIST_STATUS"       ,	   0x1180038000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1341},
+	{"ZIP_CORE1_BIST_STATUS"       ,	   0x1180038000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1341},
+	{"ZIP_CTL_BIST_STATUS"         ,	   0x1180038000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1342},
+	{"ZIP_CTL_CFG"                 ,	   0x1180038000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1343},
+	{"ZIP_DBG_CORE0_INST"          ,	   0x1180038000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1344},
+	{"ZIP_DBG_CORE1_INST"          ,	   0x1180038000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1344},
+	{"ZIP_DBG_CORE0_STA"           ,	   0x1180038000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1345},
+	{"ZIP_DBG_CORE1_STA"           ,	   0x1180038000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1345},
+	{"ZIP_DBG_QUE0_STA"            ,	   0x1180038000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1346},
+	{"ZIP_DBG_QUE1_STA"            ,	   0x1180038000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1346},
+	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1347},
+	{"ZIP_ECC_CTL"                 ,	   0x1180038000568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1348},
+	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1349},
+	{"ZIP_INT_ENA"                 ,	   0x1180038000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1350},
+	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1351},
+	{"ZIP_INT_REG"                 ,	   0x1180038000570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1352},
+	{"ZIP_QUE0_BUF"                ,	   0x1180038000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1353},
+	{"ZIP_QUE1_BUF"                ,	   0x1180038000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1353},
+	{"ZIP_QUE0_ECC_ERR_STA"        ,	   0x1180038000590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1354},
+	{"ZIP_QUE1_ECC_ERR_STA"        ,	   0x1180038000598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1354},
+	{"ZIP_QUE0_MAP"                ,	   0x1180038000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1355},
+	{"ZIP_QUE1_MAP"                ,	   0x1180038000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1355},
+	{"ZIP_QUE_ENA"                 ,	   0x1180038000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1356},
+	{"ZIP_QUE_PRI"                 ,	   0x1180038000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1357},
+	{"ZIP_THROTTLE"                ,	   0x1180038000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1358},
+	{NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn68xxp1[] = {
+	/* name                        ,	bit,	width,	csr,	type,	rst un,	typ un,	reset,	typical */
+	{"RESERVED_0_1"                ,	0,	2,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OUT_OVR"                     ,	2,	2,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_21"               ,	4,	18,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LOSTSTAT"                    ,	22,	2,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_25"              ,	24,	2,	0,	"RAZ",	1,	1,	0,	0},
+	{"STATOVR"                     ,	26,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_31"              ,	27,	5,	0,	"RAZ",	1,	1,	0,	0},
+	{"OVRFLW"                      ,	32,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP"                       ,	33,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH"                       ,	34,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRFLW1"                     ,	35,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP1"                      ,	36,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH1"                      ,	37,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	0,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	25,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	2,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	2,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	2,	"R/W",	0,	1,	1ull,	0},
+	{"RX_EN"                       ,	4,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"TX_EN"                       ,	5,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"BURST"                       ,	6,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	2,	"RAZ",	1,	1,	0,	0},
+	{"SPEED_MSB"                   ,	8,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	2,	"RAZ",	1,	1,	0,	0},
+	{"RX_IDLE"                     ,	12,	1,	2,	"RO",	0,	1,	1ull,	0},
+	{"TX_IDLE"                     ,	13,	1,	2,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	2,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	3,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	4,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	5,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	6,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	7,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	8,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	9,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	9,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	10,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	10,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	10,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	10,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	11,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	11,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR"                      ,	2,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"JABBER"                      ,	3,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALNERR"                      ,	5,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR"                      ,	6,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"RCVERR"                      ,	7,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"NIBERR"                      ,	9,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	12,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	13,	"RO",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	7,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	8,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_ALIGN"                   ,	9,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"NULL_DIS"                    ,	10,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	13,	"RAZ",	1,	1,	0,	0},
+	{"PTP_MODE"                    ,	12,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	13,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	14,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_16_63"              ,	16,	48,	14,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	15,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_16_63"              ,	16,	48,	15,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	16,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	16,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	17,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	18,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	19,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	19,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	20,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	20,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	1,	21,	"RO",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	2,	21,	"RO",	0,	1,	0ull,	0},
+	{"DUPLEX"                      ,	3,	1,	21,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	21,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	22,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	22,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	23,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	23,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	24,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	24,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	25,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	25,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	26,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	26,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	27,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	27,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	28,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	28,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	29,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	29,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	30,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	30,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	31,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	31,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	32,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	32,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	32,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	32,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	33,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	33,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	34,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	34,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	35,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_9_63"               ,	9,	55,	35,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	2,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_15"               ,	2,	14,	36,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	2,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	36,	"RAZ",	1,	1,	0,	0},
+	{"RX"                          ,	0,	2,	37,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	37,	"RAZ",	1,	1,	0,	0},
+	{"TX"                          ,	4,	2,	37,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	37,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	38,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	38,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	39,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	39,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	40,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	6,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_63"               ,	6,	58,	41,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	42,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	43,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	43,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	44,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	44,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	45,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	45,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	46,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	46,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	47,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	47,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	48,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	48,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	51,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	51,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	52,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	52,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	59,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	6,	60,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	60,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	2,	61,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	61,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	62,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	62,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	63,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	63,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	63,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	64,	"RAZ",	1,	1,	0,	0},
+	{"UNDFLW"                      ,	2,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	64,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	8,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"XSDEF"                       ,	12,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"LATE_COL"                    ,	16,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"PTP_LOST"                    ,	20,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	64,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	65,	"RAZ",	1,	1,	0,	0},
+	{"UNDFLW"                      ,	2,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	65,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	8,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"XSDEF"                       ,	12,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"LATE_COL"                    ,	16,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"PTP_LOST"                    ,	20,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	65,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	66,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	66,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	67,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	67,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	68,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	4,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	68,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	8,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	68,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	69,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	69,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	70,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	70,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	1,	71,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKRST"                      ,	1,	1,	71,	"R/W",	0,	0,	1ull,	0ull},
+	{"ENABLE"                      ,	2,	1,	71,	"R/W",	0,	0,	1ull,	1ull},
+	{"COMP"                        ,	3,	1,	71,	"R/W",	0,	0,	0ull,	1ull},
+	{"DLLRST"                      ,	4,	1,	71,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	71,	"RAZ",	1,	1,	0,	0},
+	{"CLKTX_SET"                   ,	8,	5,	71,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_14"              ,	13,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CLKTX_BYP"                   ,	15,	1,	71,	"R/W",	0,	1,	1ull,	0},
+	{"CLKRX_SET"                   ,	16,	5,	71,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_22"              ,	21,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CLKRX_BYP"                   ,	23,	1,	71,	"R/W",	0,	1,	0ull,	0},
+	{"CLK_SET"                     ,	24,	5,	71,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_31"              ,	29,	3,	71,	"RAZ",	1,	1,	0,	0},
+	{"DRV_NCTL"                    ,	32,	6,	71,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_38_39"              ,	38,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"DRV_PCTL"                    ,	40,	6,	71,	"R/W",	0,	1,	19ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CMP_NCTL"                    ,	48,	6,	71,	"RO",	1,	1,	0,	0},
+	{"RESERVED_54_55"              ,	54,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CMP_PCTL"                    ,	56,	6,	71,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	71,	"RAZ",	1,	1,	0,	0},
+	{"DRV_BYP"                     ,	63,	1,	71,	"R/W",	0,	0,	1ull,	0ull},
+	{"ACK"                         ,	0,	1,	72,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	72,	"RAZ",	1,	1,	0,	0},
+	{"ACK"                         ,	0,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	73,	"RAZ",	1,	1,	0,	0},
+	{"ACK"                         ,	0,	1,	74,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	74,	"RAZ",	1,	1,	0,	0},
+	{"ACK"                         ,	0,	1,	75,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	75,	"RAZ",	1,	1,	0,	0},
+	{"GPIO"                        ,	0,	16,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	76,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	77,	"RAZ",	1,	0,	0,	0ull},
+	{"GPIO"                        ,	0,	16,	78,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	78,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	79,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	79,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	79,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	79,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	79,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	79,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	79,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	79,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	79,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTR"                    ,	0,	4,	80,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	80,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	80,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	80,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	80,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	80,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	80,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	80,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	80,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTR"                    ,	0,	4,	81,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	81,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	81,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	81,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	81,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	81,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	81,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	81,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	81,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	82,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	82,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	0,	4,	83,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	83,	"RAZ",	1,	0,	0,	0ull},
+	{"MBOX"                        ,	0,	4,	84,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	84,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	0,	4,	85,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	85,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	86,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	86,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	87,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	87,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	88,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	88,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	88,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	88,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	88,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	88,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	88,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	88,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	0,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	89,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	89,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	89,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	89,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	89,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	89,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	89,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	89,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	0,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	90,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	90,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	90,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	90,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	90,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	90,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	90,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	90,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	91,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	91,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	91,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	91,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	91,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	91,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	91,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	91,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	91,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	91,	"RAZ",	1,	1,	0,	0},
+	{"AGX"                         ,	0,	5,	92,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	92,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	92,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	92,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	92,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	92,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	92,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	92,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	92,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	92,	"RAZ",	1,	1,	0,	0},
+	{"AGX"                         ,	0,	5,	93,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	93,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	93,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	93,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	93,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	93,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	93,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	93,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	93,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	93,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	94,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	94,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	94,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	94,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	94,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	94,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	94,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	94,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	94,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	95,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	95,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	95,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	95,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	95,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	95,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	95,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	95,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	95,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	96,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	96,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	96,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	96,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	96,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	96,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	96,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	96,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	96,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	97,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	32,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	98,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	32,	99,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	99,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	102,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	103,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	103,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	104,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	104,	"RAZ",	1,	0,	0,	0ull},
+	{"GPIO"                        ,	0,	16,	105,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	105,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	106,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	106,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	106,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	106,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	106,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	106,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	106,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	106,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	106,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTR"                    ,	0,	4,	107,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	107,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	107,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	107,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	107,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	107,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	107,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	107,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	107,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTR"                    ,	0,	4,	108,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	108,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	108,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	108,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	108,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	108,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	108,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	108,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	108,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	109,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	109,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	0,	4,	110,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	110,	"RAZ",	1,	0,	0,	0ull},
+	{"MBOX"                        ,	0,	4,	111,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	111,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	0,	4,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	112,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	113,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	114,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	114,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	115,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	115,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	115,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	115,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	115,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	115,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	115,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	115,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	0,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	116,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	116,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	116,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	116,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	116,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	116,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	116,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	116,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	0,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	117,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	117,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	117,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	117,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	117,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	117,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	117,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	117,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	118,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	118,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	118,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	118,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	118,	"RAZ",	1,	1,	0,	0},
+	{"AGX"                         ,	0,	5,	119,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	119,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	119,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	119,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	119,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	119,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	119,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	119,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	119,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	119,	"RAZ",	1,	1,	0,	0},
+	{"AGX"                         ,	0,	5,	120,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	120,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	120,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	120,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	120,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	120,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	120,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	120,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	120,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	120,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	121,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	121,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	121,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	121,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	121,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	121,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	121,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	121,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	121,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	122,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	122,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	122,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	122,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	122,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	122,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	122,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	122,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	122,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	123,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	123,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	123,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	123,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	123,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	123,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	123,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	123,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	123,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	124,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	32,	125,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	125,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	32,	126,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	126,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	129,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	130,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	131,	"RAZ",	1,	0,	0,	0ull},
+	{"GPIO"                        ,	0,	16,	132,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	132,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	133,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	133,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	133,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	133,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	133,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	133,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	133,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	133,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	133,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTR"                    ,	0,	4,	134,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	134,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	134,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	134,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	134,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	134,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	134,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	134,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	134,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTR"                    ,	0,	4,	135,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	135,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	135,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	135,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	135,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	135,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	135,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	135,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	135,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	136,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	0,	4,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	137,	"RAZ",	1,	0,	0,	0ull},
+	{"MBOX"                        ,	0,	4,	138,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	138,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	0,	4,	139,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	139,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	140,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	140,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	141,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	141,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	142,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	142,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	142,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	142,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	142,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	142,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	142,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	142,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	0,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	143,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	143,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	143,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	143,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	143,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	143,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	143,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	143,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	0,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	144,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	144,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	144,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	144,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	144,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	144,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	144,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	144,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	145,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	145,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	145,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	145,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	145,	"RAZ",	1,	1,	0,	0},
+	{"AGX"                         ,	0,	5,	146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	146,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	146,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	146,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	146,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	146,	"RAZ",	1,	1,	0,	0},
+	{"AGX"                         ,	0,	5,	147,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	147,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	147,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	147,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	147,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	147,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	147,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	147,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	147,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	147,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	148,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	148,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	148,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	148,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	148,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	148,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	148,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	148,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	148,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	149,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	149,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	149,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	149,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	149,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	149,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	149,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	149,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	149,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	150,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	150,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	150,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	150,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	150,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	150,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	150,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	150,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	150,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	151,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	32,	152,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	152,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	32,	153,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	153,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	154,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	155,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	156,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	157,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	157,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	158,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	158,	"RAZ",	1,	0,	0,	0ull},
+	{"GPIO"                        ,	0,	16,	159,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	159,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	160,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	160,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	160,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	160,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTR"                    ,	0,	4,	161,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	161,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	161,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	161,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	161,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	161,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	161,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	161,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	161,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTR"                    ,	0,	4,	162,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	162,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	162,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	162,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	162,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	162,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	162,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	162,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	162,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	163,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	163,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	0,	4,	164,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	164,	"RAZ",	1,	0,	0,	0ull},
+	{"MBOX"                        ,	0,	4,	165,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	165,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	0,	4,	166,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	166,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	167,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	167,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	168,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	168,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	169,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	169,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	169,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	169,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	169,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	169,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	169,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	169,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	0,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	170,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	170,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	170,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	170,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	170,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	170,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	170,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	170,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	0,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	171,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	171,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	171,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	171,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	171,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	171,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	171,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	171,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	172,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	172,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	172,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	172,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	172,	"RAZ",	1,	1,	0,	0},
+	{"AGX"                         ,	0,	5,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	173,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	173,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	173,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	173,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	173,	"RAZ",	1,	1,	0,	0},
+	{"AGX"                         ,	0,	5,	174,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	174,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	174,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	174,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	174,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	174,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	174,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	174,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	174,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	174,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	175,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	175,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	175,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	175,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	175,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	175,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	175,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	175,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	175,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	176,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	176,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	176,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	176,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	176,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	176,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	176,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	176,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	176,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	177,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	177,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	177,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	177,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	177,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	177,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	177,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	177,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	177,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	178,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	178,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	32,	179,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	179,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	32,	180,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	180,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	183,	"R/W1",	0,	0,	0ull,	0ull},
+	{"READY"                       ,	0,	1,	184,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	184,	"RAZ",	1,	1,	0,	0},
+	{"ECC_ENA"                     ,	0,	1,	185,	"R/W",	0,	0,	1ull,	1ull},
+	{"FLIP_SYND"                   ,	1,	2,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	185,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	186,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	186,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	186,	"RAZ",	1,	1,	0,	0},
+	{"SYNDROM"                     ,	4,	9,	186,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	186,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	16,	7,	186,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	186,	"RAZ",	1,	1,	0,	0},
+	{"CTL"                         ,	0,	3,	187,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	187,	"RAZ",	1,	1,	0,	0},
+	{"MSI_RCV"                     ,	0,	1,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	188,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	189,	"RAZ",	1,	1,	0,	0},
+	{"IP_NUM"                      ,	4,	2,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	189,	"RAZ",	1,	1,	0,	0},
+	{"PP_NUM"                      ,	8,	5,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	189,	"RAZ",	1,	1,	0,	0},
+	{"MSI_NUM"                     ,	0,	8,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	190,	"RAZ",	1,	1,	0,	0},
+	{"NEWINT"                      ,	16,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	190,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	20,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	190,	"RAZ",	1,	1,	0,	0},
+	{"MSI_NUM"                     ,	0,	8,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	191,	"RAZ",	1,	1,	0,	0},
+	{"NEWINT"                      ,	16,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	191,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	20,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	191,	"RAZ",	1,	1,	0,	0},
+	{"MSI_NUM"                     ,	0,	8,	192,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	192,	"RAZ",	1,	1,	0,	0},
+	{"NEWINT"                      ,	16,	1,	192,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	192,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	20,	1,	192,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	192,	"RAZ",	1,	1,	0,	0},
+	{"GPIO"                        ,	0,	16,	193,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	193,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	194,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	194,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	194,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	194,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	195,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	195,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	196,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	196,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	196,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	196,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	196,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	196,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	196,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	196,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	196,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	196,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	196,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	197,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	197,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	197,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	197,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	197,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	197,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	198,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	198,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	198,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	198,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	198,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	198,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	198,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	198,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	198,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	199,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	200,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	201,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	201,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	202,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	202,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	202,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	202,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	202,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	202,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	202,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	202,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	202,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	203,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	203,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	204,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	204,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	204,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	204,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	204,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	204,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	204,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	204,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	205,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	205,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	205,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	205,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	205,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	205,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	206,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	206,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	206,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	206,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	206,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	206,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	206,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	206,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	206,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	207,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	207,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	209,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	209,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	210,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	210,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	210,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	210,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	211,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	211,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	212,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	212,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	212,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	212,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	212,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	212,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	212,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	212,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	212,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	212,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	212,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	213,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	213,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	213,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	213,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	213,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	213,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	213,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	213,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	213,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	213,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	214,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	214,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	214,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	214,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	214,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	214,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	214,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	214,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	214,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	215,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	215,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	216,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	217,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	217,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	218,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	218,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	218,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	218,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	219,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	220,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	220,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	220,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	220,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	220,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	220,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	220,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	220,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	220,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	220,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	220,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	221,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	221,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	221,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	221,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	221,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	221,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	221,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	221,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	221,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	221,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	222,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	222,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	222,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	222,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	222,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	222,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	222,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	222,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	222,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	223,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	223,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	224,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	225,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	225,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	226,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	226,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	226,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	226,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	227,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	0,	4,	228,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	228,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	229,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	229,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	229,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	229,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	229,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	229,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	229,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	229,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	230,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	230,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	230,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	230,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	230,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	230,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	230,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	230,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	230,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	230,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	231,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	231,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	231,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	231,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	231,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	231,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	231,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	231,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	231,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	232,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	232,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	233,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	234,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	235,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	235,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	235,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	235,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	236,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	0,	4,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	237,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	238,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	238,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	238,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	238,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	238,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	238,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	238,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	238,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	239,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	239,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	239,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	239,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	239,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	239,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	239,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	239,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	239,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	239,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	240,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	240,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	240,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	240,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	240,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	240,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	240,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	240,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	240,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	241,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	242,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	243,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	243,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	244,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	244,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	244,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	244,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	245,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	245,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	0,	4,	246,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	246,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	247,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	247,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	247,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	247,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	247,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	247,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	247,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	247,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	248,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	248,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	248,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	248,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	248,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	249,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	249,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	249,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	249,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	249,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	249,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	249,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	249,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	249,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	250,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	250,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	251,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	252,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	253,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	253,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	253,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	253,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	254,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	254,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	0,	4,	255,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	255,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	256,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	256,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	256,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	256,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	256,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	256,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	256,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	256,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	257,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	257,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	257,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	257,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	257,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	258,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	258,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	258,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	258,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	258,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	258,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	258,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	258,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	258,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	259,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	259,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	260,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	1,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	1,	1,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	2,	1,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	3,	1,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"IO"                          ,	4,	1,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM"                         ,	5,	1,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT"                         ,	6,	1,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	7,	1,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_59"               ,	8,	52,	261,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	60,	4,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	1,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	1,	1,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	2,	1,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	3,	1,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"IO"                          ,	4,	1,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM"                         ,	5,	1,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT"                         ,	6,	1,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	7,	1,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_59"               ,	8,	52,	262,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	60,	4,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	1,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	1,	1,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	2,	1,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	3,	1,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"IO"                          ,	4,	1,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM"                         ,	5,	1,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT"                         ,	6,	1,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	7,	1,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_59"               ,	8,	52,	263,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	60,	4,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	1,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	2,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	3,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"IO"                          ,	4,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM"                         ,	5,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT"                         ,	6,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	7,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_59"               ,	8,	52,	264,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	60,	4,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	7,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	265,	"RAZ",	1,	1,	0,	0},
+	{"DINT"                        ,	0,	32,	266,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	266,	"RAZ",	1,	1,	0,	0},
+	{"FUSE"                        ,	0,	32,	267,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	267,	"RAZ",	1,	1,	0,	0},
+	{"GSTOP"                       ,	0,	1,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	268,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	0,	5,	269,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	269,	"RAZ",	1,	1,	0,	0},
+	{"IRQ"                         ,	8,	2,	269,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	269,	"RAZ",	1,	1,	0,	0},
+	{"SEL"                         ,	16,	3,	269,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_19_63"              ,	19,	45,	269,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	270,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	270,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	271,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	271,	"RAZ",	1,	1,	0,	0},
+	{"NMI"                         ,	0,	32,	272,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	272,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	2,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	273,	"RAZ",	1,	1,	0,	0},
+	{"PP_BIST"                     ,	0,	32,	274,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	274,	"RAZ",	1,	1,	0,	0},
+	{"PPDBG"                       ,	0,	32,	275,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	275,	"RAZ",	1,	1,	0,	0},
+	{"POKE"                        ,	0,	64,	276,	"R/W",	1,	1,	0,	0},
+	{"RST0"                        ,	0,	1,	277,	"R/W",	1,	1,	0,	0},
+	{"RST"                         ,	1,	31,	277,	"R/W",	0,	0,	2147483647ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	277,	"RAZ",	1,	1,	0,	0},
+	{"LANE_EN"                     ,	0,	4,	278,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	278,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	278,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	278,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	278,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	278,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	278,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	278,	"RAZ",	1,	1,	0,	0},
+	{"LANE_EN"                     ,	0,	4,	279,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	279,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	279,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	279,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	279,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	279,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	279,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_39"              ,	32,	8,	279,	"RAZ",	1,	1,	0,	0},
+	{"G2MARGIN"                    ,	40,	5,	279,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	279,	"RAZ",	1,	1,	0,	0},
+	{"G2DEEMPH"                    ,	48,	5,	279,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_53_62"              ,	53,	10,	279,	"RAZ",	1,	1,	0,	0},
+	{"G2BYPASS"                    ,	63,	1,	279,	"R/W",	0,	1,	0ull,	0},
+	{"LANE_EN"                     ,	0,	4,	280,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	280,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	280,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	280,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	280,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	280,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	280,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_39"              ,	32,	8,	280,	"RAZ",	1,	1,	0,	0},
+	{"G2MARGIN"                    ,	40,	5,	280,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	280,	"RAZ",	1,	1,	0,	0},
+	{"G2DEEMPH"                    ,	48,	5,	280,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_53_62"              ,	53,	10,	280,	"RAZ",	1,	1,	0,	0},
+	{"G2BYPASS"                    ,	63,	1,	280,	"R/W",	0,	1,	0ull,	0},
+	{"LANE_EN"                     ,	0,	4,	281,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	281,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	281,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	281,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	281,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	281,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	281,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_39"              ,	32,	8,	281,	"RAZ",	1,	1,	0,	0},
+	{"G2MARGIN"                    ,	40,	5,	281,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	281,	"RAZ",	1,	1,	0,	0},
+	{"G2DEEMPH"                    ,	48,	5,	281,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_53_62"              ,	53,	10,	281,	"RAZ",	1,	1,	0,	0},
+	{"G2BYPASS"                    ,	63,	1,	281,	"R/W",	0,	1,	0ull,	0},
+	{"LANE_EN"                     ,	0,	4,	282,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	282,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	282,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	282,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	282,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	282,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	282,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_39"              ,	32,	8,	282,	"RAZ",	1,	1,	0,	0},
+	{"G2MARGIN"                    ,	40,	5,	282,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	282,	"RAZ",	1,	1,	0,	0},
+	{"G2DEEMPH"                    ,	48,	5,	282,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_53_62"              ,	53,	10,	282,	"RAZ",	1,	1,	0,	0},
+	{"G2BYPASS"                    ,	63,	1,	282,	"R/W",	0,	1,	0ull,	0},
+	{"BYPASS"                      ,	0,	4,	283,	"R/W",	0,	1,	0ull,	0},
+	{"MUX_SEL"                     ,	4,	3,	283,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	283,	"RAZ",	1,	1,	0,	0},
+	{"CLK_DIV"                     ,	8,	3,	283,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_15"              ,	11,	5,	283,	"RAZ",	1,	1,	0,	0},
+	{"BYPASS_EXT"                  ,	16,	1,	283,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	283,	"RAZ",	1,	1,	0,	0},
+	{"SHFT_REG"                    ,	0,	32,	284,	"R/W",	0,	1,	0ull,	0},
+	{"SHFT_CNT"                    ,	32,	5,	284,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_37_39"              ,	37,	3,	284,	"RAZ",	1,	1,	0,	0},
+	{"SELECT"                      ,	40,	5,	284,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_60"              ,	45,	16,	284,	"RAZ",	1,	1,	0,	0},
+	{"UPDATE"                      ,	61,	1,	284,	"R/W",	0,	1,	0ull,	0},
+	{"SHIFT"                       ,	62,	1,	284,	"R/W",	0,	1,	0ull,	0},
+	{"CAPTURE"                     ,	63,	1,	284,	"R/W",	0,	1,	0ull,	0},
+	{"SOFT_BIST"                   ,	0,	1,	285,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	285,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	286,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	286,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	287,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	287,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST"                    ,	0,	1,	288,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	288,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	36,	289,	"R/W",	0,	0,	0ull,	0ull},
+	{"ONE_SHOT"                    ,	36,	1,	289,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	289,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	2,	2,	290,	"RO",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	4,	16,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	20,	24,	290,	"RO",	0,	0,	0ull,	0ull},
+	{"DSTOP"                       ,	44,	1,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSTOPEN"                     ,	45,	1,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	290,	"RAZ",	1,	1,	0,	0},
+	{"PDB"                         ,	0,	3,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	291,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RDF"                         ,	4,	3,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	291,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTX"                         ,	8,	2,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"DTX1"                        ,	10,	2,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"DTX2"                        ,	12,	2,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	291,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STX"                         ,	16,	2,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"STX1"                        ,	18,	2,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"STX2"                        ,	20,	2,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	291,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GFB"                         ,	24,	3,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	291,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MRP"                         ,	28,	2,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_63"              ,	30,	34,	291,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GFU"                         ,	0,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"GIB"                         ,	1,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"GIF"                         ,	2,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"NCD"                         ,	3,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"GUTP"                        ,	4,	3,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	292,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GUTV"                        ,	8,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"CRQ"                         ,	9,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"RAM1"                        ,	10,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"RAM2"                        ,	11,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"RAM3"                        ,	12,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"DC1RAM1"                     ,	13,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"DC1RAM2"                     ,	14,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"DC1RAM3"                     ,	15,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"DC2RAM1"                     ,	16,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"DC2RAM2"                     ,	17,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"DC2RAM3"                     ,	18,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"DLC0RAM"                     ,	19,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"DLC1RAM"                     ,	20,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	292,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTECLKDIS"                   ,	0,	1,	293,	"R/W",	0,	0,	1ull,	0ull},
+	{"CLDTECRIP"                   ,	1,	3,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLMSKCRIP"                   ,	4,	4,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"REPL_ENA"                    ,	8,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLCSTART_BIST"               ,	9,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLCCLEAR_BIST"               ,	10,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	293,	"RAZ",	1,	1,	0,	0},
+	{"IMODE"                       ,	0,	1,	294,	"R/W",	0,	0,	1ull,	1ull},
+	{"QMODE"                       ,	1,	1,	294,	"R/W",	0,	0,	1ull,	1ull},
+	{"PMODE"                       ,	2,	1,	294,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_4"                ,	3,	2,	294,	"RAZ",	1,	1,	0,	0},
+	{"SBDLCK"                      ,	5,	1,	294,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBDNUM"                      ,	6,	6,	294,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	294,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	20,	295,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	295,	"RAZ",	1,	1,	0,	0},
+	{"SBD0"                        ,	0,	64,	296,	"RO",	1,	1,	0,	0},
+	{"SBD1"                        ,	0,	64,	297,	"RO",	1,	1,	0,	0},
+	{"SBD2"                        ,	0,	64,	298,	"RO",	1,	1,	0,	0},
+	{"SBD3"                        ,	0,	64,	299,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	9,	300,	"R/W",	0,	1,	3ull,	0},
+	{"POOL"                        ,	9,	3,	300,	"R/W",	0,	1,	0ull,	0},
+	{"DWBCNT"                      ,	12,	8,	300,	"R/W",	0,	1,	1ull,	0},
+	{"MSEGBASE"                    ,	20,	6,	300,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	300,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	301,	"RAZ",	1,	1,	0,	0},
+	{"RDPTR"                       ,	5,	35,	301,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	301,	"RAZ",	1,	1,	0,	0},
+	{"RAM1FADR"                    ,	0,	14,	302,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	302,	"RAZ",	1,	1,	0,	0},
+	{"RAM2FADR"                    ,	16,	9,	302,	"RO",	1,	1,	0,	0},
+	{"RESERVED_25_31"              ,	25,	7,	302,	"RAZ",	1,	1,	0,	0},
+	{"RAM3FADR"                    ,	32,	12,	302,	"RO",	1,	1,	0,	0},
+	{"RESERVED_44_63"              ,	44,	20,	302,	"RAZ",	1,	1,	0,	0},
+	{"DBLOVF"                      ,	0,	1,	303,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC0PERR"                     ,	1,	3,	303,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC1PERR"                     ,	4,	3,	303,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC2PERR"                     ,	7,	3,	303,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_12"              ,	10,	3,	303,	"RAZ",	1,	1,	0,	0},
+	{"DLC0_OVFERR"                 ,	13,	1,	303,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DLC1_OVFERR"                 ,	14,	1,	303,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	303,	"RAZ",	1,	1,	0,	0},
+	{"CNDRD"                       ,	16,	1,	303,	"RO",	0,	0,	0ull,	0ull},
+	{"DFANXM"                      ,	17,	1,	303,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REPLERR"                     ,	18,	1,	303,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	303,	"RAZ",	1,	1,	0,	0},
+	{"DBLINA"                      ,	0,	1,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC0PENA"                     ,	1,	3,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC1PENA"                     ,	4,	3,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC2PENA"                     ,	7,	3,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_12"              ,	10,	3,	304,	"RAZ",	1,	1,	0,	0},
+	{"DLC0_OVFENA"                 ,	13,	1,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLC1_OVFENA"                 ,	14,	1,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_16"              ,	15,	2,	304,	"RAZ",	1,	1,	0,	0},
+	{"DFANXMENA"                   ,	17,	1,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"REPLERRENA"                  ,	18,	1,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	304,	"RAZ",	1,	1,	0,	0},
+	{"HIDAT"                       ,	0,	64,	305,	"R/W",	1,	1,	0,	0},
+	{"PFCNT0"                      ,	0,	64,	306,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	307,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	307,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	307,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	307,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	307,	"RAZ",	1,	1,	0,	0},
+	{"PFCNT1"                      ,	0,	64,	308,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	309,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	309,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	309,	"RAZ",	1,	1,	0,	0},
+	{"PFCNT2"                      ,	0,	64,	310,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	311,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	311,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	311,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	311,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	311,	"RAZ",	1,	1,	0,	0},
+	{"PFCNT3"                      ,	0,	64,	312,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	313,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	313,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	313,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	313,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	313,	"RAZ",	1,	1,	0,	0},
+	{"CNT0ENA"                     ,	0,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1ENA"                     ,	1,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2ENA"                     ,	2,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3ENA"                     ,	3,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0WCLR"                    ,	4,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1WCLR"                    ,	5,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2WCLR"                    ,	6,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3WCLR"                    ,	7,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0RCLR"                    ,	8,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1RCLR"                    ,	9,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2RCLR"                    ,	10,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3RCLR"                    ,	11,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"SNODE"                       ,	12,	3,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENODE"                       ,	15,	3,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"EDNODE"                      ,	18,	2,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMODE"                       ,	20,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGID"                        ,	21,	8,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	314,	"RAZ",	1,	1,	0,	0},
+	{"BIST"                        ,	0,	45,	315,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_63"              ,	45,	19,	315,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	316,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLK"                         ,	1,	1,	316,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	316,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	317,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	317,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	317,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	318,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	318,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	6,	319,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	319,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_6"                ,	0,	7,	320,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	7,	33,	320,	"R/W",	0,	1,	0ull,	0},
+	{"IDLE"                        ,	40,	1,	320,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_41_47"              ,	41,	7,	320,	"RAZ",	1,	1,	0,	0},
+	{"CSIZE"                       ,	48,	14,	320,	"R/W",	0,	1,	64ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	320,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	3,	321,	"R/W",	0,	0,	6ull,	6ull},
+	{"RESERVED_3_63"               ,	3,	61,	321,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	40,	322,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	322,	"RAZ",	1,	1,	0,	0},
+	{"STATE"                       ,	0,	64,	323,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	0,	64,	324,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_13"               ,	0,	14,	325,	"RAZ",	1,	1,	0,	0},
+	{"O_MODE"                      ,	14,	1,	325,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ES"                        ,	15,	2,	325,	"R/W",	0,	1,	0ull,	0},
+	{"O_NS"                        ,	17,	1,	325,	"R/W",	0,	1,	0ull,	0},
+	{"O_RO"                        ,	18,	1,	325,	"R/W",	0,	1,	0ull,	0},
+	{"O_ADD1"                      ,	19,	1,	325,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA_QUE"                     ,	20,	3,	325,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_ICHK"                    ,	23,	9,	325,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_DENB"                    ,	32,	1,	325,	"R/W",	0,	0,	0ull,	1ull},
+	{"B0_LEND"                     ,	33,	1,	325,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_47"              ,	34,	14,	325,	"RAZ",	1,	1,	0,	0},
+	{"DMA_ENB"                     ,	48,	6,	325,	"R/W",	0,	0,	0ull,	63ull},
+	{"RESERVED_54_55"              ,	54,	2,	325,	"RAZ",	1,	1,	0,	0},
+	{"PKT_EN"                      ,	56,	1,	325,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_HP"                      ,	57,	1,	325,	"RO",	0,	0,	0ull,	0ull},
+	{"COMMIT_MODE"                 ,	58,	1,	325,	"R/W",	0,	0,	0ull,	1ull},
+	{"FFP_DIS"                     ,	59,	1,	325,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_EN1"                     ,	60,	1,	325,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_61_63"              ,	61,	3,	325,	"RAZ",	1,	1,	0,	0},
+	{"QEN"                         ,	0,	8,	326,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	326,	"RAZ",	1,	1,	0,	0},
+	{"BLKS"                        ,	0,	4,	327,	"R/W",	0,	1,	2ull,	0},
+	{"BASE"                        ,	4,	5,	327,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_31"               ,	9,	23,	327,	"RAZ",	1,	1,	0,	0},
+	{"COMPBLKS"                    ,	32,	5,	327,	"RO",	1,	1,	0,	0},
+	{"RESERVED_37_63"              ,	37,	27,	327,	"RAZ",	1,	1,	0,	0},
+	{"RSL"                         ,	0,	1,	328,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NCB"                         ,	1,	1,	328,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	328,	"RAZ",	1,	1,	0,	0},
+	{"FFP"                         ,	4,	4,	328,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	328,	"RAZ",	1,	1,	0,	0},
+	{"NDERR"                       ,	0,	1,	329,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFOVR"                       ,	1,	1,	329,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	329,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMADBO"                      ,	8,	8,	329,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADADR"                  ,	16,	1,	329,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADLEN"                  ,	17,	1,	329,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_OVRFLW"                  ,	18,	1,	329,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_UNDFLW"                  ,	19,	1,	329,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_ANULL"                   ,	20,	1,	329,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_INULL"                   ,	21,	1,	329,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADFIL"                  ,	22,	1,	329,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	329,	"R/W",	1,	1,	0,	0},
+	{"SPRT0_RST"                   ,	24,	1,	329,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_RST"                   ,	25,	1,	329,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_63"              ,	26,	38,	329,	"R/W",	1,	1,	0,	0},
+	{"NDERR"                       ,	0,	1,	330,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFOVR"                       ,	1,	1,	330,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	330,	"RAZ",	1,	1,	0,	0},
+	{"DMADBO"                      ,	8,	8,	330,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADADR"                  ,	16,	1,	330,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADLEN"                  ,	17,	1,	330,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_OVRFLW"                  ,	18,	1,	330,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_UNDFLW"                  ,	19,	1,	330,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_ANULL"                   ,	20,	1,	330,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_INULL"                   ,	21,	1,	330,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADFIL"                  ,	22,	1,	330,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	330,	"RAZ",	1,	1,	0,	0},
+	{"SPRT0_RST"                   ,	24,	1,	330,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT1_RST"                   ,	25,	1,	330,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_63"              ,	26,	38,	330,	"RAZ",	1,	1,	0,	0},
+	{"SINFO"                       ,	0,	6,	331,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	331,	"RAZ",	1,	1,	0,	0},
+	{"IINFO"                       ,	8,	6,	331,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	331,	"RAZ",	1,	1,	0,	0},
+	{"PKTERR"                      ,	0,	1,	332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	332,	"RAZ",	1,	1,	0,	0},
+	{"QERR"                        ,	0,	8,	333,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	333,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	334,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	334,	"RAZ",	1,	1,	0,	0},
+	{"QERR"                        ,	0,	8,	335,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	335,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	336,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	336,	"RAZ",	1,	1,	0,	0},
+	{"EN_RSP"                      ,	0,	8,	337,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	337,	"RAZ",	1,	1,	0,	0},
+	{"EN_RST"                      ,	16,	8,	337,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	337,	"RAZ",	1,	1,	0,	0},
+	{"QEN"                         ,	0,	8,	338,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	338,	"RAZ",	1,	1,	0,	0},
+	{"MRRS"                        ,	0,	2,	339,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	339,	"RAZ",	1,	1,	0,	0},
+	{"MRRS_LIM"                    ,	3,	1,	339,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPS"                         ,	4,	1,	339,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	339,	"RAZ",	1,	1,	0,	0},
+	{"MPS_LIM"                     ,	7,	1,	339,	"R/W",	0,	0,	0ull,	0ull},
+	{"MOLR"                        ,	8,	6,	339,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_14_15"              ,	14,	2,	339,	"RAZ",	1,	1,	0,	0},
+	{"RD_MODE"                     ,	16,	1,	339,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	339,	"RAZ",	1,	1,	0,	0},
+	{"QLM_CFG"                     ,	20,	1,	339,	"RO",	1,	1,	0,	0},
+	{"RESERVED_21_23"              ,	21,	3,	339,	"RAZ",	1,	1,	0,	0},
+	{"HALT"                        ,	24,	1,	339,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	339,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	340,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	61,	340,	"RO",	0,	1,	0ull,	0},
+	{"REQQ"                        ,	0,	3,	341,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	341,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	4,	1,	341,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	341,	"RAZ",	1,	1,	0,	0},
+	{"LOCK"                        ,	8,	1,	341,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	341,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	33,	342,	"RO",	0,	1,	0ull,	0},
+	{"POOL"                        ,	33,	5,	342,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	342,	"RAZ",	1,	1,	0,	0},
+	{"FDR"                         ,	0,	1,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"FFR"                         ,	1,	1,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF1"                        ,	2,	1,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF0"                        ,	3,	1,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"FRD"                         ,	4,	1,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	343,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	344,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	344,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	14,	1,	344,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_STT"                     ,	15,	1,	344,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_LDT"                     ,	16,	1,	344,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	344,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_OFF"                     ,	18,	1,	344,	"R/W",	0,	0,	0ull,	0ull},
+	{"RET_OFF"                     ,	19,	1,	344,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE_EN"                     ,	20,	1,	344,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	344,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	11,	345,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	11,	11,	345,	"R/W",	0,	0,	164ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	345,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	11,	346,	"R/W",	0,	0,	224ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	346,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	12,	347,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	12,	12,	347,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	347,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	12,	348,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	348,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	11,	349,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	11,	11,	349,	"R/W",	0,	0,	164ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	349,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	12,	350,	"R/W",	0,	0,	224ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	350,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL0TH"                     ,	28,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL1TH"                     ,	29,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL2TH"                     ,	30,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL3TH"                     ,	31,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL4TH"                     ,	32,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL5TH"                     ,	33,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL6TH"                     ,	34,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL7TH"                     ,	35,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE0"                       ,	36,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE1"                       ,	37,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE2"                       ,	38,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE3"                       ,	39,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE4"                       ,	40,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE5"                       ,	41,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE6"                       ,	42,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE7"                       ,	43,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE8"                       ,	44,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q8_UND"                      ,	45,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q8_COFF"                     ,	46,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q8_PERR"                     ,	47,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL8TH"                     ,	48,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"PADDR_E"                     ,	49,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_63"              ,	50,	14,	351,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL0TH"                     ,	28,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL1TH"                     ,	29,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL2TH"                     ,	30,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL3TH"                     ,	31,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL4TH"                     ,	32,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL5TH"                     ,	33,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL6TH"                     ,	34,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL7TH"                     ,	35,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE0"                       ,	36,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE1"                       ,	37,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE2"                       ,	38,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE3"                       ,	39,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE4"                       ,	40,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE5"                       ,	41,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE6"                       ,	42,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE7"                       ,	43,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE8"                       ,	44,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q8_UND"                      ,	45,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q8_COFF"                     ,	46,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q8_PERR"                     ,	47,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL8TH"                     ,	48,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PADDR_E"                     ,	49,	1,	352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_63"              ,	50,	14,	352,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	32,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	353,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	33,	354,	"R/W",	0,	1,	8589934591ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	354,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	33,	355,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	355,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	32,	356,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	356,	"RAZ",	1,	1,	0,	0},
+	{"QUE_SIZ"                     ,	0,	32,	357,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	357,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	358,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	358,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	359,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	359,	"RAZ",	1,	1,	0,	0},
+	{"ACT_INDX"                    ,	0,	26,	360,	"RO",	0,	1,	0ull,	0},
+	{"ACT_QUE"                     ,	26,	3,	360,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	360,	"RO",	0,	0,	0ull,	7ull},
+	{"EXP_INDX"                    ,	0,	26,	361,	"RO",	0,	1,	0ull,	0},
+	{"EXP_QUE"                     ,	26,	3,	361,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	361,	"RO",	0,	0,	0ull,	7ull},
+	{"THRESH"                      ,	0,	32,	362,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	362,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	363,	"RAZ",	1,	1,	0,	0},
+	{"OUT_OVR"                     ,	2,	4,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_21"               ,	6,	16,	363,	"RAZ",	1,	1,	0,	0},
+	{"LOSTSTAT"                    ,	22,	4,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INB_NXA"                     ,	27,	4,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	363,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	25,	364,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	364,	"RAZ",	1,	1,	0,	0},
+	{"BPID"                        ,	0,	6,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	365,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	8,	1,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_15"               ,	9,	7,	365,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	16,	1,	365,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	365,	"RAZ",	1,	1,	0,	0},
+	{"MSK_AND"                     ,	0,	16,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	366,	"RAZ",	1,	1,	0,	0},
+	{"MSK_OR"                      ,	32,	16,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	366,	"RAZ",	1,	1,	0,	0},
+	{"CLK_EN"                      ,	0,	1,	367,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	367,	"RAZ",	1,	1,	0,	0},
+	{"DIS"                         ,	0,	16,	368,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	368,	"RAZ",	1,	1,	0,	0},
+	{"MSK"                         ,	0,	16,	369,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	369,	"RAZ",	1,	1,	0,	0},
+	{"LOGL_EN"                     ,	0,	16,	370,	"R/W",	0,	1,	65535ull,	0},
+	{"PHYS_EN"                     ,	16,	1,	370,	"R/W",	0,	1,	1ull,	0},
+	{"HG2RX_EN"                    ,	17,	1,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2TX_EN"                    ,	18,	1,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	370,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	1,	371,	"RO",	0,	1,	0ull,	0},
+	{"EN"                          ,	1,	1,	371,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_3"                ,	2,	2,	371,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	4,	3,	371,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	371,	"RAZ",	1,	1,	0,	0},
+	{"SPEED"                       ,	8,	4,	371,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	371,	"RAZ",	1,	1,	0,	0},
+	{"PRT"                         ,	0,	6,	372,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_15"               ,	6,	10,	372,	"RAZ",	1,	1,	0,	0},
+	{"PIPE"                        ,	16,	7,	372,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	372,	"RAZ",	1,	1,	0,	0},
+	{"STOP"                        ,	0,	4,	373,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	373,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	8,	4,	373,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	373,	"RAZ",	1,	1,	0,	0},
+	{"OVR"                         ,	16,	4,	373,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	373,	"RAZ",	1,	1,	0,	0},
+	{"RX_EN"                       ,	0,	1,	374,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_EN"                       ,	1,	1,	374,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRP_EN"                      ,	2,	1,	374,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCK_EN"                      ,	3,	1,	374,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	374,	"RAZ",	1,	1,	0,	0},
+	{"PHYS_BP"                     ,	16,	16,	374,	"R/W",	0,	1,	65535ull,	0},
+	{"LOGL_EN"                     ,	32,	16,	374,	"R/W",	0,	0,	255ull,	255ull},
+	{"PHYS_EN"                     ,	48,	16,	374,	"R/W",	0,	0,	255ull,	255ull},
+	{"EN"                          ,	0,	1,	375,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	375,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	375,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	375,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	375,	"RAZ",	1,	1,	0,	0},
+	{"SPEED_MSB"                   ,	8,	1,	375,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	375,	"RAZ",	1,	1,	0,	0},
+	{"RX_IDLE"                     ,	12,	1,	375,	"RO",	0,	1,	1ull,	0},
+	{"TX_IDLE"                     ,	13,	1,	375,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	375,	"RAZ",	1,	1,	0,	0},
+	{"PKND"                        ,	16,	6,	375,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_63"              ,	22,	42,	375,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	376,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	377,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	378,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	379,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	380,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	381,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	382,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	382,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	383,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	383,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	383,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	383,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	384,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	384,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	385,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	385,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_2"                ,	2,	1,	385,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	385,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	385,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_6"                ,	5,	2,	385,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	385,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	385,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	385,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	386,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	386,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	386,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	386,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	386,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	386,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	386,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_8"                ,	7,	2,	386,	"RAZ",	1,	1,	0,	0},
+	{"PRE_ALIGN"                   ,	9,	1,	386,	"R/W",	0,	0,	0ull,	0ull},
+	{"NULL_DIS"                    ,	10,	1,	386,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	386,	"RAZ",	1,	1,	0,	0},
+	{"PTP_MODE"                    ,	12,	1,	386,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	386,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	387,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	387,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	388,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	388,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	388,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	388,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	388,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	388,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	389,	"R/W1C",	0,	1,	0ull,	0},
+	{"CAREXT"                      ,	1,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	389,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	389,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	389,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	389,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	389,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	390,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	390,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	391,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	391,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	392,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	392,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	393,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	393,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	394,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	394,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	395,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	395,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	396,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	396,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	397,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	397,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	398,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	398,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	399,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	399,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	400,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	400,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	401,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	401,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	402,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	402,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	403,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	403,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	404,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	404,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	11,	405,	"R/W",	0,	0,	128ull,	128ull},
+	{"RESERVED_11_63"              ,	11,	53,	405,	"RAZ",	1,	1,	0,	0},
+	{"LGTIM2GO"                    ,	0,	16,	406,	"RO",	0,	1,	0ull,	0},
+	{"XOF"                         ,	16,	16,	406,	"RO",	0,	0,	0ull,	0ull},
+	{"PHTIM2GO"                    ,	32,	16,	406,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	406,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	4,	407,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	407,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	4,	407,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	407,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	3,	408,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_3_63"               ,	3,	61,	408,	"RAZ",	1,	1,	0,	0},
+	{"LANE_RXD"                    ,	0,	32,	409,	"RO",	0,	1,	0ull,	0},
+	{"LANE_RXC"                    ,	32,	4,	409,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	3,	409,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	39,	1,	409,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	409,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	2,	410,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	410,	"RAZ",	1,	1,	0,	0},
+	{"DISPARITY"                   ,	0,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	411,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	412,	"RAZ",	1,	1,	0,	0},
+	{"CLEAR_BIST"                  ,	0,	1,	413,	"R/W",	0,	1,	0ull,	0},
+	{"START_BIST"                  ,	1,	1,	413,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	413,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	414,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	415,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	415,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	415,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	415,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	415,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	16,	416,	"R/W",	0,	0,	8192ull,	8192ull},
+	{"RESERVED_16_63"              ,	16,	48,	416,	"RAZ",	1,	1,	0,	0},
+	{"XOFF"                        ,	0,	16,	417,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	417,	"RAZ",	1,	1,	0,	0},
+	{"XON"                         ,	0,	16,	418,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	418,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	419,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	419,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	419,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	420,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	420,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	421,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	421,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	422,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	422,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	423,	"RO",	1,	1,	0,	0},
+	{"MSG_TIME"                    ,	16,	16,	423,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	423,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	424,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	424,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	7,	425,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_15"               ,	7,	9,	425,	"RAZ",	1,	1,	0,	0},
+	{"NUMP"                        ,	16,	5,	425,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_31"              ,	21,	11,	425,	"RAZ",	1,	1,	0,	0},
+	{"IGN_BP"                      ,	32,	1,	425,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	425,	"RAZ",	1,	1,	0,	0},
+	{"ALIGN"                       ,	0,	1,	426,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	426,	"RAZ",	1,	1,	0,	0},
+	{"SLOT"                        ,	0,	10,	427,	"R/W",	0,	0,	512ull,	512ull},
+	{"RESERVED_10_63"              ,	10,	54,	427,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	428,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	428,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	429,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	429,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	430,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	430,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	431,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	431,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	432,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	432,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	433,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	433,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	434,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	434,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	435,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	435,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	436,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	436,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	437,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	437,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	438,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	438,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	439,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	439,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	10,	440,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_10_63"              ,	10,	54,	440,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	4,	441,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	441,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	442,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	442,	"RAZ",	1,	1,	0,	0},
+	{"CORRUPT"                     ,	0,	4,	443,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_4_63"               ,	4,	60,	443,	"RAZ",	1,	1,	0,	0},
+	{"TX_XOF"                      ,	0,	16,	444,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	444,	"RAZ",	1,	1,	0,	0},
+	{"TX_XON"                      ,	0,	16,	445,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	445,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	446,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	446,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	446,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	447,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO_NXP"                     ,	1,	1,	447,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	447,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	447,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	447,	"R/W",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	447,	"R/W",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	447,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTP_LOST"                    ,	20,	4,	447,	"R/W",	0,	0,	0ull,	0ull},
+	{"XCHANGE"                     ,	24,	1,	447,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	447,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	448,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO_NXP"                     ,	1,	1,	448,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	448,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	448,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	448,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	448,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	448,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTP_LOST"                    ,	20,	4,	448,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XCHANGE"                     ,	24,	1,	448,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	448,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	449,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	449,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	450,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	450,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	4,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	4,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	4,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	451,	"RAZ",	1,	1,	0,	0},
+	{"TX_PRT_BP"                   ,	32,	16,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	451,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	452,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	452,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	453,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	453,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	5,	454,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	454,	"RAZ",	1,	1,	0,	0},
+	{"DIC_EN"                      ,	0,	1,	455,	"R/W",	0,	0,	0ull,	1ull},
+	{"UNI_EN"                      ,	1,	1,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	455,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	4,	2,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"LS_BYP"                      ,	6,	1,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	455,	"RAZ",	1,	1,	0,	0},
+	{"HG_EN"                       ,	8,	1,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_PAUSE_HGI"                ,	9,	2,	455,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_11_63"              ,	11,	53,	455,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	4,	456,	"R/W",	0,	0,	6ull,	6ull},
+	{"EN"                          ,	4,	1,	456,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	456,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	457,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	457,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	457,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	457,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	457,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	457,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_SEL"                     ,	12,	2,	457,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_GEN"                     ,	14,	1,	457,	"R/W",	0,	0,	0ull,	0ull},
+	{"SYNCE_SEL"                   ,	15,	2,	457,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	457,	"RAZ",	1,	1,	0,	0},
+	{"N"                           ,	0,	32,	458,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	458,	"RAZ",	1,	1,	0,	0},
+	{"LANE_SEL"                    ,	0,	2,	459,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIV"                         ,	2,	1,	459,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	459,	"RAZ",	1,	1,	0,	0},
+	{"QLM_SEL"                     ,	8,	3,	459,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	459,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	460,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	460,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	461,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	461,	"RAZ",	1,	1,	0,	0},
+	{"SEL"                         ,	0,	4,	462,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	462,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	16,	463,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	463,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	16,	464,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	464,	"RAZ",	1,	1,	0,	0},
+	{"TLK0_TXF0"                   ,	0,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"TLK0_TXF1"                   ,	1,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"TLK0_TXF2"                   ,	2,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"TLK0_STAT"                   ,	3,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"TLK0_FWC"                    ,	4,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	465,	"RAZ",	0,	1,	0ull,	0},
+	{"TLK1_TXF0"                   ,	6,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"TLK1_TXF1"                   ,	7,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"TLK1_TXF2"                   ,	8,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"TLK1_STAT"                   ,	9,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"TLK1_FWC"                    ,	10,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	465,	"RAZ",	0,	1,	0ull,	0},
+	{"RLK0_STAT"                   ,	12,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RLK0_FWC"                    ,	13,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	465,	"RAZ",	0,	1,	0ull,	0},
+	{"RLK1_STAT"                   ,	16,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RLK1_FWC"                    ,	17,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_19"              ,	18,	2,	465,	"RAZ",	0,	1,	0ull,	0},
+	{"RLE0_DSK0"                   ,	20,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RLE0_DSK1"                   ,	21,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RLE1_DSK0"                   ,	22,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RLE1_DSK1"                   ,	23,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RLE2_DSK0"                   ,	24,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RLE2_DSK1"                   ,	25,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RLE3_DSK0"                   ,	26,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RLE3_DSK1"                   ,	27,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RLE4_DSK0"                   ,	28,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RLE4_DSK1"                   ,	29,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RLE5_DSK0"                   ,	30,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RLE5_DSK1"                   ,	31,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RLE6_DSK0"                   ,	32,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RLE6_DSK1"                   ,	33,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RLE7_DSK0"                   ,	34,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RLE7_DSK1"                   ,	35,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_51"              ,	36,	16,	465,	"RAZ",	0,	1,	0ull,	0},
+	{"RXF_MEM0"                    ,	52,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RXF_MEM1"                    ,	53,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RXF_MEM2"                    ,	54,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RXF_PMAP"                    ,	55,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RXF_X2P0"                    ,	56,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RXF_X2P1"                    ,	57,	1,	465,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	465,	"RAZ",	0,	1,	0ull,	0},
+	{"RXF_XLINK"                   ,	0,	1,	466,	"R/W",	0,	1,	0ull,	0},
+	{"CCLK_DIS"                    ,	1,	1,	466,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	466,	"RAZ",	0,	1,	0ull,	0},
+	{"RXF_LNK0_PERR"               ,	0,	1,	467,	"R/W1C",	0,	1,	0ull,	0},
+	{"RXF_LNK1_PERR"               ,	1,	1,	467,	"R/W1C",	0,	1,	0ull,	0},
+	{"RXF_CTL_PERR"                ,	2,	1,	467,	"R/W1C",	0,	1,	0ull,	0},
+	{"RXF_POP_EMPTY"               ,	3,	1,	467,	"R/W1C",	0,	1,	0ull,	0},
+	{"RXF_PUSH_FULL"               ,	4,	1,	467,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	467,	"RAZ",	0,	1,	0ull,	0},
+	{"RXF_LNK0_PERR"               ,	0,	1,	468,	"R/W",	0,	1,	0ull,	0},
+	{"RXF_LNK1_PERR"               ,	1,	1,	468,	"R/W",	0,	1,	0ull,	0},
+	{"RXF_CTL_PERR"                ,	2,	1,	468,	"R/W",	0,	1,	0ull,	0},
+	{"RXF_POP_EMPTY"               ,	3,	1,	468,	"R/W",	0,	1,	0ull,	0},
+	{"RXF_PUSH_FULL"               ,	4,	1,	468,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	468,	"RAZ",	0,	1,	0ull,	0},
+	{"GBL_INT"                     ,	0,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"TLK0_INT"                    ,	1,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"TLK1_INT"                    ,	2,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLK0_INT"                    ,	3,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLK1_INT"                    ,	4,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE0_INT"                    ,	5,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE1_INT"                    ,	6,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE2_INT"                    ,	7,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE3_INT"                    ,	8,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE4_INT"                    ,	9,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE5_INT"                    ,	10,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE6_INT"                    ,	11,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE7_INT"                    ,	12,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_13_63"              ,	13,	51,	469,	"RAZ",	0,	1,	0ull,	0},
+	{"TX_DIS_SCRAM"                ,	0,	8,	470,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	470,	"RAZ",	0,	1,	0ull,	0},
+	{"TX_DIS_DISPR"                ,	16,	8,	470,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_31"              ,	24,	8,	470,	"RAZ",	0,	1,	0ull,	0},
+	{"TX_BAD_LANE_SEL"             ,	32,	8,	470,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_47"              ,	40,	8,	470,	"RAZ",	0,	1,	0ull,	0},
+	{"TX_BAD_SCRAM_CNT"            ,	48,	3,	470,	"R/W",	0,	1,	0ull,	0},
+	{"TX_BAD_SYNC_CNT"             ,	51,	3,	470,	"R/W",	0,	1,	0ull,	0},
+	{"TX_BAD_6467_CNT"             ,	54,	5,	470,	"R/W",	0,	1,	0ull,	0},
+	{"TX_BAD_CRC32"                ,	59,	1,	470,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	470,	"RAZ",	0,	1,	0ull,	0},
+	{"TX_LNE_STAT"                 ,	0,	8,	471,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	471,	"RAZ",	0,	1,	0ull,	0},
+	{"TX_LNK_STAT"                 ,	16,	8,	471,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_24_31"              ,	24,	8,	471,	"RAZ",	0,	1,	0ull,	0},
+	{"RX_LNE_STAT"                 ,	32,	8,	471,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_40_47"              ,	40,	8,	471,	"RAZ",	0,	1,	0ull,	0},
+	{"RX_LNK_STAT"                 ,	48,	8,	471,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	471,	"RAZ",	0,	1,	0ull,	0},
+	{"LANE_ENA"                    ,	0,	8,	472,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	472,	"RAZ",	0,	1,	0ull,	0},
+	{"CAL_DEPTH"                   ,	16,	9,	472,	"R/W",	0,	1,	144ull,	0},
+	{"RESERVED_25_25"              ,	25,	1,	472,	"RAZ",	0,	1,	0ull,	0},
+	{"BRST_MAX"                    ,	26,	5,	472,	"R/W",	0,	1,	4ull,	0},
+	{"LANE_REV"                    ,	31,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"BRST_SHRT"                   ,	32,	7,	472,	"R/W",	0,	1,	4ull,	0},
+	{"MFRM_LEN"                    ,	39,	13,	472,	"R/W",	0,	1,	1024ull,	0},
+	{"CAL_ENA"                     ,	52,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"MLTUSE_FC_ENA"               ,	53,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"LNK_STATS_ENA"               ,	54,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"LNK_STATS_RDCLR"             ,	55,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"PTRN_MODE"                   ,	56,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_57_61"              ,	57,	5,	472,	"RAZ",	0,	1,	0ull,	0},
+	{"EXT_LPBK"                    ,	62,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"EXT_LPBK_FC"                 ,	63,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"RX_BDRY_LOCK_ENA"            ,	0,	8,	473,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	473,	"RAZ",	0,	1,	0ull,	0},
+	{"RX_ALIGN_ENA"                ,	16,	1,	473,	"R/W",	0,	1,	0ull,	0},
+	{"RX_LINK_FC"                  ,	17,	1,	473,	"RO",	0,	1,	0ull,	0},
+	{"TX_LINK_FC"                  ,	18,	1,	473,	"RO",	0,	1,	0ull,	0},
+	{"LA_MODE"                     ,	19,	1,	473,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_ENA"                     ,	20,	1,	473,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_FLUSH"                   ,	21,	1,	473,	"WR0",	0,	1,	0ull,	0},
+	{"RX_FIFO_MAX"                 ,	22,	12,	473,	"R/W",	0,	1,	1024ull,	0},
+	{"RESERVED_34_35"              ,	34,	2,	473,	"RAZ",	0,	1,	0ull,	0},
+	{"RX_FIFO_HWM"                 ,	36,	12,	473,	"R/W",	0,	1,	512ull,	0},
+	{"RESERVED_48_49"              ,	48,	2,	473,	"RAZ",	0,	1,	0ull,	0},
+	{"RX_FIFO_CNT"                 ,	50,	12,	473,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	473,	"RAZ",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	0,	64,	474,	"RO",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	0,	64,	475,	"RO",	0,	1,	0ull,	0},
+	{"INDEX"                       ,	0,	6,	476,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	476,	"RAZ",	0,	1,	0ull,	0},
+	{"INC"                         ,	8,	6,	476,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	476,	"RAZ",	0,	1,	0ull,	0},
+	{"INDEX"                       ,	0,	8,	477,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	477,	"RAZ",	0,	1,	0ull,	0},
+	{"INC"                         ,	16,	8,	477,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_30"              ,	24,	7,	477,	"RAZ",	0,	1,	0ull,	0},
+	{"CLR"                         ,	31,	1,	477,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	477,	"RAZ",	0,	1,	0ull,	0},
+	{"INDEX"                       ,	0,	8,	478,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	478,	"RAZ",	0,	1,	0ull,	0},
+	{"INC"                         ,	16,	8,	478,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_30"              ,	24,	7,	478,	"RAZ",	0,	1,	0ull,	0},
+	{"CLR"                         ,	31,	1,	478,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	478,	"RAZ",	0,	1,	0ull,	0},
+	{"LANE_ALIGN_FAIL"             ,	0,	1,	479,	"R/W1C",	0,	1,	0ull,	0},
+	{"CRC24_ERR"                   ,	1,	1,	479,	"R/W1C",	0,	1,	0ull,	0},
+	{"WORD_SYNC_DONE"              ,	2,	1,	479,	"R/W1C",	0,	1,	0ull,	0},
+	{"LANE_ALIGN_DONE"             ,	3,	1,	479,	"R/W1C",	0,	1,	0ull,	0},
+	{"STAT_CNT_OVFL"               ,	4,	1,	479,	"R/W1C",	0,	1,	0ull,	0},
+	{"LANE_BAD_WORD"               ,	5,	1,	479,	"R/W1C",	0,	1,	0ull,	0},
+	{"PKT_DROP_RXF"                ,	6,	1,	479,	"R/W1C",	0,	1,	0ull,	0},
+	{"PKT_DROP_RID"                ,	7,	1,	479,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	479,	"RAZ",	0,	1,	0ull,	0},
+	{"LANE_ALIGN_FAIL"             ,	0,	1,	480,	"R/W",	0,	1,	0ull,	0},
+	{"CRC24_ERR"                   ,	1,	1,	480,	"R/W",	0,	1,	0ull,	0},
+	{"WORD_SYNC_DONE"              ,	2,	1,	480,	"R/W",	0,	1,	0ull,	0},
+	{"LANE_ALIGN_DONE"             ,	3,	1,	480,	"R/W",	0,	1,	0ull,	0},
+	{"STAT_CNT_OVFL"               ,	4,	1,	480,	"R/W",	0,	1,	0ull,	0},
+	{"LANE_BAD_WORD"               ,	5,	1,	480,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_DROP_RXF"                ,	6,	1,	480,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_DROP_RID"                ,	7,	1,	480,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	480,	"RAZ",	0,	1,	0ull,	0},
+	{"CNT"                         ,	0,	16,	481,	"R/W",	0,	1,	10240ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	481,	"RAZ",	0,	1,	0ull,	0},
+	{"PORT_PIPE0"                  ,	0,	7,	482,	"R/W",	0,	1,	0ull,	0},
+	{"ENTRY_CTL0"                  ,	7,	2,	482,	"R/W",	0,	1,	0ull,	0},
+	{"PORT_PIPE1"                  ,	9,	7,	482,	"R/W",	0,	1,	0ull,	0},
+	{"ENTRY_CTL1"                  ,	16,	2,	482,	"R/W",	0,	1,	0ull,	0},
+	{"PORT_PIPE2"                  ,	18,	7,	482,	"R/W",	0,	1,	0ull,	0},
+	{"ENTRY_CTL2"                  ,	25,	2,	482,	"R/W",	0,	1,	0ull,	0},
+	{"PORT_PIPE3"                  ,	27,	7,	482,	"R/W",	0,	1,	0ull,	0},
+	{"ENTRY_CTL3"                  ,	34,	2,	482,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	482,	"RAZ",	0,	1,	0ull,	0},
+	{"PORT_PIPE4"                  ,	0,	7,	483,	"R/W",	0,	1,	0ull,	0},
+	{"ENTRY_CTL4"                  ,	7,	2,	483,	"R/W",	0,	1,	0ull,	0},
+	{"PORT_PIPE5"                  ,	9,	7,	483,	"R/W",	0,	1,	0ull,	0},
+	{"ENTRY_CTL5"                  ,	16,	2,	483,	"R/W",	0,	1,	0ull,	0},
+	{"PORT_PIPE6"                  ,	18,	7,	483,	"R/W",	0,	1,	0ull,	0},
+	{"ENTRY_CTL6"                  ,	25,	2,	483,	"R/W",	0,	1,	0ull,	0},
+	{"PORT_PIPE7"                  ,	27,	7,	483,	"R/W",	0,	1,	0ull,	0},
+	{"ENTRY_CTL7"                  ,	34,	2,	483,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	483,	"RAZ",	0,	1,	0ull,	0},
+	{"RX_PKT"                      ,	0,	28,	484,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	484,	"RAZ",	0,	1,	0ull,	0},
+	{"RX_BYTES"                    ,	0,	36,	485,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	485,	"RAZ",	0,	1,	0ull,	0},
+	{"CRC24_MATCH_CNT"             ,	0,	27,	486,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_27_63"              ,	27,	37,	486,	"RAZ",	0,	1,	0ull,	0},
+	{"CRC24_ERR_CNT"               ,	0,	18,	487,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	487,	"RAZ",	0,	1,	0ull,	0},
+	{"BRST_CNT"                    ,	0,	16,	488,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	488,	"RAZ",	0,	1,	0ull,	0},
+	{"BRST_NOT_FULL_CNT"           ,	32,	16,	488,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	488,	"RAZ",	0,	1,	0ull,	0},
+	{"BRST_MAX_ERR_CNT"            ,	0,	16,	489,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	489,	"RAZ",	0,	1,	0ull,	0},
+	{"BRST_SHRT_ERR_CNT"           ,	0,	16,	490,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	490,	"RAZ",	0,	1,	0ull,	0},
+	{"ALIGN_CNT"                   ,	0,	16,	491,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	491,	"RAZ",	0,	1,	0ull,	0},
+	{"ALIGN_ERR_CNT"               ,	0,	16,	492,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	492,	"RAZ",	0,	1,	0ull,	0},
+	{"BAD_64B67B_CNT"              ,	0,	16,	493,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	493,	"RAZ",	0,	1,	0ull,	0},
+	{"PKT_DROP_RXF_CNT"            ,	0,	16,	494,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_DROP_RID_CNT"            ,	16,	16,	494,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	494,	"RAZ",	0,	1,	0ull,	0},
+	{"RESERVED_0_63"               ,	0,	64,	495,	"RAZ",	0,	1,	0ull,	0},
+	{"STAT_ENA"                    ,	0,	1,	496,	"R/W",	0,	1,	0ull,	0},
+	{"STAT_RDCLR"                  ,	1,	1,	496,	"R/W",	0,	1,	0ull,	0},
+	{"RX_DIS_SCRAM"                ,	2,	1,	496,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_DIS_UKWN"                 ,	3,	1,	496,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_BDRY_SYNC"                ,	4,	1,	496,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	496,	"RAZ",	0,	1,	0ull,	0},
+	{"SERDES_LOCK_LOSS"            ,	0,	1,	497,	"R/W1C",	0,	1,	0ull,	0},
+	{"BDRY_SYNC_LOSS"              ,	1,	1,	497,	"R/W1C",	0,	1,	0ull,	0},
+	{"CRC32_ERR"                   ,	2,	1,	497,	"R/W1C",	0,	1,	0ull,	0},
+	{"UKWN_CNTL_WORD"              ,	3,	1,	497,	"R/W1C",	0,	1,	0ull,	0},
+	{"SCRM_SYNC_LOSS"              ,	4,	1,	497,	"R/W1C",	0,	1,	0ull,	0},
+	{"DSKEW_FIFO_OVFL"             ,	5,	1,	497,	"R/W1C",	0,	1,	0ull,	0},
+	{"STAT_MSG"                    ,	6,	1,	497,	"R/W1C",	0,	1,	0ull,	0},
+	{"STAT_CNT_OVFL"               ,	7,	1,	497,	"R/W1C",	0,	1,	0ull,	0},
+	{"BAD_64B67B"                  ,	8,	1,	497,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	497,	"RAZ",	0,	1,	0ull,	0},
+	{"SERDES_LOCK_LOSS"            ,	0,	1,	498,	"R/W",	0,	1,	0ull,	0},
+	{"BDRY_SYNC_LOSS"              ,	1,	1,	498,	"R/W",	0,	1,	0ull,	0},
+	{"CRC32_ERR"                   ,	2,	1,	498,	"R/W",	0,	1,	0ull,	0},
+	{"UKWN_CNTL_WORD"              ,	3,	1,	498,	"R/W",	0,	1,	0ull,	0},
+	{"SCRM_SYNC_LOSS"              ,	4,	1,	498,	"R/W",	0,	1,	0ull,	0},
+	{"DSKEW_FIFO_OVFL"             ,	5,	1,	498,	"R/W",	0,	1,	0ull,	0},
+	{"STAT_MSG"                    ,	6,	1,	498,	"R/W",	0,	1,	0ull,	0},
+	{"STAT_CNT_OVFL"               ,	7,	1,	498,	"R/W",	0,	1,	0ull,	0},
+	{"BAD_64B67B"                  ,	8,	1,	498,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	498,	"RAZ",	0,	1,	0ull,	0},
+	{"SER_LOCK_LOSS_CNT"           ,	0,	18,	499,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	499,	"RAZ",	0,	1,	0ull,	0},
+	{"BDRY_SYNC_LOSS_CNT"          ,	0,	18,	500,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	500,	"RAZ",	0,	1,	0ull,	0},
+	{"SYNCW_BAD_CNT"               ,	0,	18,	501,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_31"              ,	18,	14,	501,	"RAZ",	0,	1,	0ull,	0},
+	{"SYNCW_GOOD_CNT"              ,	32,	18,	501,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_50_63"              ,	50,	14,	501,	"RAZ",	0,	1,	0ull,	0},
+	{"BAD_64B67B_CNT"              ,	0,	18,	502,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	502,	"RAZ",	0,	1,	0ull,	0},
+	{"DATA_WORD_CNT"               ,	0,	27,	503,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_27_31"              ,	27,	5,	503,	"RAZ",	0,	1,	0ull,	0},
+	{"CNTL_WORD_CNT"               ,	32,	27,	503,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_59_63"              ,	59,	5,	503,	"RAZ",	0,	1,	0ull,	0},
+	{"UNKWN_WORD_CNT"              ,	0,	18,	504,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	504,	"RAZ",	0,	1,	0ull,	0},
+	{"SCRM_SYNC_LOSS_CNT"          ,	0,	18,	505,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	505,	"RAZ",	0,	1,	0ull,	0},
+	{"SCRM_MATCH_CNT"              ,	0,	18,	506,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	506,	"RAZ",	0,	1,	0ull,	0},
+	{"SKIPW_GOOD_CNT"              ,	0,	18,	507,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	507,	"RAZ",	0,	1,	0ull,	0},
+	{"CRC32_MATCH_CNT"             ,	0,	27,	508,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_27_31"              ,	27,	5,	508,	"RAZ",	0,	1,	0ull,	0},
+	{"CRC32_ERR_CNT"               ,	32,	18,	508,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_50_63"              ,	50,	14,	508,	"RAZ",	0,	1,	0ull,	0},
+	{"INDEX"                       ,	0,	9,	509,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_15"               ,	9,	7,	509,	"RAZ",	0,	1,	0ull,	0},
+	{"INC"                         ,	16,	9,	509,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	509,	"RAZ",	0,	1,	0ull,	0},
+	{"PORT_KIND"                   ,	0,	6,	510,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	510,	"RAZ",	0,	1,	0ull,	0},
+	{"SER_HAUL"                    ,	0,	2,	511,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_3"                ,	2,	2,	511,	"RAZ",	0,	1,	0ull,	0},
+	{"SER_PWRUP"                   ,	4,	2,	511,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	511,	"RAZ",	0,	1,	0ull,	0},
+	{"SER_RESET_N"                 ,	8,	8,	511,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_23"              ,	16,	8,	511,	"RAZ",	0,	1,	0ull,	0},
+	{"SER_TXPOL"                   ,	24,	8,	511,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_39"              ,	32,	8,	511,	"RAZ",	0,	1,	0ull,	0},
+	{"SER_RXPOL"                   ,	40,	8,	511,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_55"              ,	48,	8,	511,	"RAZ",	0,	1,	0ull,	0},
+	{"SER_RXPOL_AUTO"              ,	56,	1,	511,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_57_63"              ,	57,	7,	511,	"RAZ",	0,	1,	0ull,	0},
+	{"LANE_ENA"                    ,	0,	8,	512,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	512,	"RAZ",	0,	1,	0ull,	0},
+	{"CAL_DEPTH"                   ,	16,	9,	512,	"R/W",	0,	1,	72ull,	0},
+	{"RESERVED_25_25"              ,	25,	1,	512,	"RAZ",	0,	1,	0ull,	0},
+	{"BRST_MAX"                    ,	26,	5,	512,	"R/W",	0,	1,	4ull,	0},
+	{"LANE_REV"                    ,	31,	1,	512,	"R/W",	0,	1,	0ull,	0},
+	{"BRST_SHRT"                   ,	32,	7,	512,	"R/W",	0,	1,	4ull,	0},
+	{"MFRM_LEN"                    ,	39,	13,	512,	"R/W",	0,	1,	1024ull,	0},
+	{"CAL_ENA"                     ,	52,	1,	512,	"R/W",	0,	1,	0ull,	0},
+	{"MLTUSE_FC_ENA"               ,	53,	1,	512,	"R/W",	0,	1,	0ull,	0},
+	{"LNK_STATS_ENA"               ,	54,	1,	512,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_55_55"              ,	55,	1,	512,	"RAZ",	0,	1,	0ull,	0},
+	{"PTRN_MODE"                   ,	56,	1,	512,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_57_60"              ,	57,	4,	512,	"RAZ",	0,	1,	0ull,	0},
+	{"INT_LPBK"                    ,	61,	1,	512,	"R/W",	0,	1,	0ull,	0},
+	{"EXT_LPBK"                    ,	62,	1,	512,	"R/W",	0,	1,	0ull,	0},
+	{"EXT_LPBK_FC"                 ,	63,	1,	512,	"R/W",	0,	1,	0ull,	0},
+	{"TX_MLTUSE"                   ,	0,	8,	513,	"R/W",	0,	1,	0ull,	0},
+	{"RMATCH"                      ,	8,	1,	513,	"R/W",	0,	1,	0ull,	0},
+	{"RX_LINK_FC_IGN"              ,	9,	1,	513,	"R/W",	0,	1,	0ull,	0},
+	{"RX_LINK_FC_PKT"              ,	10,	1,	513,	"R/W",	0,	1,	0ull,	0},
+	{"TX_LINK_FC_JAM"              ,	11,	1,	513,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_16"              ,	12,	5,	513,	"RAZ",	0,	1,	0ull,	0},
+	{"RX_LINK_FC"                  ,	17,	1,	513,	"RO",	0,	1,	0ull,	0},
+	{"TX_LINK_FC"                  ,	18,	1,	513,	"RO",	0,	1,	0ull,	0},
+	{"LA_MODE"                     ,	19,	1,	513,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_ENA"                     ,	20,	1,	513,	"R/W",	0,	1,	1ull,	0},
+	{"PKT_FLUSH"                   ,	21,	1,	513,	"R/W",	0,	1,	0ull,	0},
+	{"SKIP_CNT"                    ,	22,	4,	513,	"R/W",	0,	1,	1ull,	0},
+	{"PTP_DELAY"                   ,	26,	5,	513,	"R/W",	0,	1,	26ull,	0},
+	{"PIPE_CRD_DIS"                ,	31,	1,	513,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	513,	"RAZ",	0,	1,	0ull,	0},
+	{"TX_BAD_CTLW1"                ,	0,	1,	514,	"R/W",	0,	1,	0ull,	0},
+	{"TX_BAD_CTLW2"                ,	1,	1,	514,	"R/W",	0,	1,	0ull,	0},
+	{"TX_BAD_CRC24"                ,	2,	1,	514,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	514,	"RAZ",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	0,	64,	515,	"RO",	0,	1,	18446744073709551615ull,	0},
+	{"RESERVED_0_63"               ,	0,	64,	516,	"RAZ",	0,	1,	0ull,	0},
+	{"INDEX"                       ,	0,	6,	517,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	517,	"RAZ",	0,	1,	0ull,	0},
+	{"INC"                         ,	8,	6,	517,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	517,	"RAZ",	0,	1,	0ull,	0},
+	{"INDEX"                       ,	0,	7,	518,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_15"               ,	7,	9,	518,	"RAZ",	0,	1,	0ull,	0},
+	{"INC"                         ,	16,	7,	518,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	518,	"RAZ",	0,	1,	0ull,	0},
+	{"INDEX"                       ,	0,	8,	519,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	519,	"RAZ",	0,	1,	0ull,	0},
+	{"INC"                         ,	16,	8,	519,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_30"              ,	24,	7,	519,	"RAZ",	0,	1,	0ull,	0},
+	{"CLR"                         ,	31,	1,	519,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	519,	"RAZ",	0,	1,	0ull,	0},
+	{"INDEX"                       ,	0,	8,	520,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	520,	"RAZ",	0,	1,	0ull,	0},
+	{"INC"                         ,	16,	8,	520,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_30"              ,	24,	7,	520,	"RAZ",	0,	1,	0ull,	0},
+	{"CLR"                         ,	31,	1,	520,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	520,	"RAZ",	0,	1,	0ull,	0},
+	{"TXF_ERR"                     ,	0,	1,	521,	"R/W1C",	0,	1,	0ull,	0},
+	{"BAD_SEQ"                     ,	1,	1,	521,	"R/W1C",	0,	1,	0ull,	0},
+	{"BAD_PIPE"                    ,	2,	1,	521,	"R/W1C",	0,	1,	0ull,	0},
+	{"STAT_CNT_OVFL"               ,	3,	1,	521,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	521,	"RAZ",	0,	1,	0ull,	0},
+	{"TXF_ERR"                     ,	0,	1,	522,	"R/W",	0,	1,	0ull,	0},
+	{"BAD_SEQ"                     ,	1,	1,	522,	"R/W",	0,	1,	0ull,	0},
+	{"BAD_PIPE"                    ,	2,	1,	522,	"R/W",	0,	1,	0ull,	0},
+	{"STAT_CNT_OVFL"               ,	3,	1,	522,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	522,	"RAZ",	0,	1,	0ull,	0},
+	{"BPID0"                       ,	0,	6,	523,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_6"                ,	6,	1,	523,	"RAZ",	0,	1,	0ull,	0},
+	{"ENTRY_CTL0"                  ,	7,	2,	523,	"R/W",	0,	1,	0ull,	0},
+	{"BPID1"                       ,	9,	6,	523,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	523,	"RAZ",	0,	1,	0ull,	0},
+	{"ENTRY_CTL1"                  ,	16,	2,	523,	"R/W",	0,	1,	0ull,	0},
+	{"BPID2"                       ,	18,	6,	523,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_24"              ,	24,	1,	523,	"RAZ",	0,	1,	0ull,	0},
+	{"ENTRY_CTL2"                  ,	25,	2,	523,	"R/W",	0,	1,	0ull,	0},
+	{"BPID3"                       ,	27,	6,	523,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_33"              ,	33,	1,	523,	"RAZ",	0,	1,	0ull,	0},
+	{"ENTRY_CTL3"                  ,	34,	2,	523,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	523,	"RAZ",	0,	1,	0ull,	0},
+	{"BPID4"                       ,	0,	6,	524,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_6"                ,	6,	1,	524,	"RAZ",	0,	1,	0ull,	0},
+	{"ENTRY_CTL4"                  ,	7,	2,	524,	"R/W",	0,	1,	0ull,	0},
+	{"BPID5"                       ,	9,	6,	524,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	524,	"RAZ",	0,	1,	0ull,	0},
+	{"ENTRY_CTL5"                  ,	16,	2,	524,	"R/W",	0,	1,	0ull,	0},
+	{"BPID6"                       ,	18,	6,	524,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_24"              ,	24,	1,	524,	"RAZ",	0,	1,	0ull,	0},
+	{"ENTRY_CTL6"                  ,	25,	2,	524,	"R/W",	0,	1,	0ull,	0},
+	{"BPID7"                       ,	27,	6,	524,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_33"              ,	33,	1,	524,	"RAZ",	0,	1,	0ull,	0},
+	{"ENTRY_CTL7"                  ,	34,	2,	524,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	524,	"RAZ",	0,	1,	0ull,	0},
+	{"CHANNEL"                     ,	0,	8,	525,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	525,	"RAZ",	0,	1,	0ull,	0},
+	{"TX_PKT"                      ,	0,	28,	526,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	526,	"RAZ",	0,	1,	0ull,	0},
+	{"TX_BYTES"                    ,	0,	36,	527,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	527,	"RAZ",	0,	1,	0ull,	0},
+	{"BASE"                        ,	0,	7,	528,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_15"               ,	7,	9,	528,	"RAZ",	0,	1,	0ull,	0},
+	{"NUMP"                        ,	16,	8,	528,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	528,	"RAZ",	0,	1,	0ull,	0},
+	{"RATE_LIMIT"                  ,	0,	16,	529,	"R/W",	0,	1,	1024ull,	0},
+	{"TIME_LIMIT"                  ,	16,	16,	529,	"R/W",	0,	1,	256ull,	0},
+	{"BRST_LIMIT"                  ,	32,	16,	529,	"R/W",	0,	1,	1024ull,	0},
+	{"GRNLRTY"                     ,	48,	2,	529,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_50_63"              ,	50,	14,	529,	"RAZ",	0,	1,	0ull,	0},
+	{"ICRP1"                       ,	0,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP0"                       ,	1,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	530,	"RAZ",	1,	1,	0,	0},
+	{"IOCFIF"                      ,	4,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"RSDFIF"                      ,	5,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"IORFIF"                      ,	6,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"XMCFIF"                      ,	7,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"XMDFIF"                      ,	8,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	530,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_5"                ,	0,	6,	531,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XMC_PER"                     ,	6,	4,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIF_DLY"                     ,	10,	1,	531,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	531,	"RAZ",	1,	1,	0,	0},
+	{"NCB_WR"                      ,	0,	3,	532,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_5"                ,	3,	3,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO_RD"                      ,	6,	4,	532,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	532,	"RAZ",	1,	1,	0,	0},
+	{"ICD"                         ,	0,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"IBD"                         ,	1,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN1"                       ,	2,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN0"                       ,	3,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ1"                       ,	4,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ0"                       ,	5,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRT"                       ,	6,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR1"                        ,	7,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR0"                        ,	8,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR0"                       ,	9,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR1"                        ,	10,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR0"                        ,	11,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRCB"                      ,	12,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"IOCFIF"                      ,	13,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"RSDFIF"                      ,	14,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"IORFIF"                      ,	15,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"XMCFIF"                      ,	16,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"XMDFIF"                      ,	17,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	533,	"RAZ",	1,	1,	0,	0},
+	{"FAU_END"                     ,	0,	1,	534,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB_ENB"                     ,	1,	1,	534,	"R/W",	0,	0,	1ull,	1ull},
+	{"PKO_ENB"                     ,	2,	1,	534,	"R/W",	0,	0,	0ull,	0ull},
+	{"INB_MAT"                     ,	3,	1,	534,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTB_MAT"                    ,	4,	1,	534,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVR5"                       ,	5,	1,	534,	"R/W",	0,	0,	0ull,	0ull},
+	{"XMC_PER"                     ,	6,	4,	534,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIF_DLY"                     ,	10,	1,	534,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	534,	"RAZ",	1,	1,	0,	0},
+	{"TOUT_VAL"                    ,	0,	12,	535,	"R/W",	0,	0,	4ull,	4ull},
+	{"TOUT_ENB"                    ,	12,	1,	535,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	535,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	536,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	536,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	536,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	536,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	536,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	537,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	537,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	537,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	537,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	537,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	538,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	539,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_63"               ,	0,	64,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_63"               ,	0,	64,	541,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	542,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	543,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	543,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	543,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	543,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	543,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	544,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	544,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	544,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	544,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	544,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	545,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	546,	"R/W",	0,	1,	0ull,	0},
+	{"CNT_VAL"                     ,	0,	15,	547,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	547,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	547,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	548,	"RAZ",	1,	1,	0,	0},
+	{"NCB_WR"                      ,	0,	3,	549,	"R/W",	0,	1,	0ull,	0},
+	{"NCB_RD"                      ,	3,	3,	549,	"R/W",	0,	1,	0ull,	0},
+	{"DWB"                         ,	6,	3,	549,	"R/W",	0,	1,	2ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	549,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	550,	"R/W",	0,	1,	14ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	550,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	551,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	551,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	552,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	552,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	553,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	553,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	554,	"R/W",	0,	1,	12ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	554,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	555,	"R/W",	0,	1,	40ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	555,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	556,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	556,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	557,	"R/W",	0,	1,	8ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	557,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	558,	"R/W",	0,	1,	8ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	558,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	559,	"R/W",	0,	1,	24ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	559,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	560,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	560,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	561,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	561,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	562,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	563,	"RAZ",	1,	1,	0,	0},
+	{"PWP"                         ,	0,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_NEW"                     ,	1,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_OLD"                     ,	2,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PRC_OFF"                     ,	3,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ0"                        ,	4,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ1"                        ,	5,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM_WORD"                    ,	6,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM0"                        ,	7,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM1"                        ,	8,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM2"                        ,	9,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM3"                        ,	10,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE0"                    ,	11,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE1"                    ,	12,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_POW"                     ,	13,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WP1"                     ,	14,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WQED"                    ,	15,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_NCMD"                    ,	16,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_MEM"                     ,	17,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM4"                        ,	18,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"IIO0"                        ,	19,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"IIO1"                        ,	20,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"IIWO0"                       ,	21,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"IIWO1"                       ,	22,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	564,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	565,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	565,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	565,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	566,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	566,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	64,	567,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB_WR"                      ,	0,	8,	568,	"R/W",	0,	0,	8ull,	8ull},
+	{"IOB_WRC"                     ,	8,	8,	568,	"RO",	0,	1,	8ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	568,	"RAZ",	1,	1,	0,	0},
+	{"IPD_EN"                      ,	0,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC_MODE"                    ,	1,	2,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBP_EN"                      ,	3,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"WQE_LEND"                    ,	4,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_LEND"                    ,	5,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"NADDBUF"                     ,	6,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDPKT"                      ,	7,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	8,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_M8"                      ,	9,	1,	569,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKT_OFF"                     ,	10,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_FULL"                    ,	11,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_NABUF"                    ,	12,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_APKT"                     ,	13,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"NO_WPTR"                     ,	14,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKEN"                       ,	15,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"RST_DONE"                    ,	16,	1,	569,	"RO",	0,	0,	1ull,	0ull},
+	{"USE_SOP"                     ,	17,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	569,	"RAZ",	1,	1,	0,	0},
+	{"PM0_SYN"                     ,	0,	2,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM1_SYN"                     ,	2,	2,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM2_SYN"                     ,	4,	2,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM3_SYN"                     ,	6,	2,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	570,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	8,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	8,	1,	571,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRADDR"                      ,	9,	8,	571,	"RO",	1,	1,	0,	0},
+	{"WRADDR"                      ,	17,	8,	571,	"RO",	1,	1,	0,	0},
+	{"MAX_CNTS"                    ,	25,	7,	571,	"RO",	0,	0,	64ull,	64ull},
+	{"RESERVED_32_63"              ,	32,	32,	571,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	572,	"RO",	1,	1,	0,	0},
+	{"RESERVED_33_63"              ,	33,	31,	572,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	3,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	3,	1,	573,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRADDR"                      ,	4,	3,	573,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	7,	3,	573,	"RO",	0,	0,	5ull,	5ull},
+	{"PTR"                         ,	10,	33,	573,	"RO",	1,	1,	0,	0},
+	{"RESERVED_43_63"              ,	43,	21,	573,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"SOP"                         ,	12,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"EOP"                         ,	13,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"DAT"                         ,	14,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PW0_SBE"                     ,	15,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PW0_DBE"                     ,	16,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PW1_SBE"                     ,	17,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PW1_DBE"                     ,	18,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PW2_SBE"                     ,	19,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PW2_DBE"                     ,	20,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PW3_SBE"                     ,	21,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PW3_DBE"                     ,	22,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	574,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SOP"                         ,	12,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EOP"                         ,	13,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DAT"                         ,	14,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PW0_SBE"                     ,	15,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PW0_DBE"                     ,	16,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PW1_SBE"                     ,	17,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PW1_DBE"                     ,	18,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PW2_SBE"                     ,	19,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PW2_DBE"                     ,	20,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PW3_SBE"                     ,	21,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PW3_DBE"                     ,	22,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	575,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	576,	"RO",	1,	1,	0,	0},
+	{"RESERVED_33_63"              ,	33,	31,	576,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	577,	"RO",	1,	1,	0,	0},
+	{"RESERVED_33_63"              ,	33,	31,	577,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	578,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	64,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"MB_SIZE"                     ,	0,	12,	580,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_12_63"              ,	12,	52,	580,	"RAZ",	1,	1,	0,	0},
+	{"REASM"                       ,	0,	6,	581,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	581,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	7,	582,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	7,	1,	582,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAX_PKT"                     ,	8,	7,	582,	"RO",	0,	0,	64ull,	64ull},
+	{"PTR"                         ,	15,	33,	582,	"RO",	1,	1,	0,	0},
+	{"RESERVED_48_63"              ,	48,	16,	582,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	583,	"RO",	0,	1,	0ull,	0},
+	{"WMARK"                       ,	32,	32,	583,	"R/W",	0,	1,	4294967295ull,	0},
+	{"INTR"                        ,	0,	64,	584,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	64,	585,	"R/W",	0,	0,	0ull,	1ull},
+	{"SOP"                         ,	0,	64,	586,	"RO",	0,	1,	0ull,	0},
+	{"WQE_PCNT"                    ,	0,	7,	587,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PCNT"                    ,	7,	7,	587,	"RO",	0,	0,	0ull,	0ull},
+	{"PFIF_CNT"                    ,	14,	3,	587,	"RO",	0,	0,	0ull,	0ull},
+	{"WQEV_CNT"                    ,	17,	1,	587,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTV_CNT"                    ,	18,	1,	587,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	587,	"RAZ",	1,	1,	0,	0},
+	{"PASS"                        ,	0,	32,	588,	"R/W",	0,	1,	0ull,	0},
+	{"DROP"                        ,	32,	32,	588,	"R/W",	0,	1,	0ull,	0},
+	{"Q0_PCNT"                     ,	0,	32,	589,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	589,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	64,	590,	"R/W",	0,	0,	0ull,	0ull},
+	{"AVG_DLY"                     ,	0,	14,	591,	"R/W",	0,	1,	0ull,	0},
+	{"PRB_DLY"                     ,	14,	14,	591,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	591,	"RAZ",	1,	1,	0,	0},
+	{"PRB_CON"                     ,	0,	32,	592,	"R/W",	0,	1,	0ull,	0},
+	{"AVG_CON"                     ,	32,	8,	592,	"R/W",	0,	1,	0ull,	0},
+	{"NEW_CON"                     ,	40,	8,	592,	"R/W",	0,	1,	0ull,	0},
+	{"USE_PCNT"                    ,	48,	1,	592,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	592,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	25,	593,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	25,	6,	593,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	593,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	594,	"R/W",	1,	0,	0,	0ull},
+	{"PORT_QOS"                    ,	32,	9,	594,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_41_63"              ,	41,	23,	594,	"RAZ",	1,	1,	0,	0},
+	{"WQE_POOL"                    ,	0,	3,	595,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	595,	"RAZ",	1,	1,	0,	0},
+	{"MEM0"                        ,	0,	1,	596,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM1"                        ,	1,	1,	596,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	2,	1,	596,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	596,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	597,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	598,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	599,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	599,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	599,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	599,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	599,	"RAZ",	1,	1,	0,	0},
+	{"DISABLE"                     ,	0,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	600,	"RAZ",	1,	1,	0,	0},
+	{"MAXDRAM"                     ,	4,	4,	600,	"R/W",	0,	0,	9ull,	9ull},
+	{"RESERVED_8_63"               ,	8,	56,	600,	"RAZ",	1,	1,	0,	0},
+	{"TDFFL"                       ,	0,	4,	601,	"RO",	1,	0,	0,	0ull},
+	{"VRTFL"                       ,	4,	4,	601,	"RO",	1,	0,	0,	0ull},
+	{"DUTRESFL"                    ,	8,	4,	601,	"RO",	1,	0,	0,	0ull},
+	{"IOCDATFL"                    ,	12,	4,	601,	"RO",	1,	0,	0,	0ull},
+	{"IOCCMDFL"                    ,	16,	4,	601,	"RO",	1,	0,	0,	0ull},
+	{"TDPFL"                       ,	20,	4,	601,	"RO",	1,	0,	0,	0ull},
+	{"XBFFL"                       ,	24,	4,	601,	"RO",	1,	0,	0,	0ull},
+	{"RBFFL"                       ,	28,	4,	601,	"RO",	1,	0,	0,	0ull},
+	{"DUTFL"                       ,	32,	32,	601,	"RO",	1,	0,	0,	0ull},
+	{"VBFFL"                       ,	0,	4,	602,	"RO",	1,	0,	0,	0ull},
+	{"RDFFL"                       ,	4,	1,	602,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_5_61"               ,	5,	57,	602,	"RAZ",	1,	1,	0,	0},
+	{"CLEAR_BIST"                  ,	62,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"START_BIST"                  ,	63,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFL"                       ,	0,	8,	603,	"RO",	1,	0,	0,	0ull},
+	{"FBFFL"                       ,	8,	8,	603,	"RO",	1,	0,	0,	0ull},
+	{"SBFFL"                       ,	16,	8,	603,	"RO",	1,	0,	0,	0ull},
+	{"FBFRSPFL"                    ,	24,	8,	603,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	603,	"RAZ",	1,	1,	0,	0},
+	{"TAGFL"                       ,	0,	16,	604,	"RO",	1,	0,	0,	0ull},
+	{"LRUFL"                       ,	16,	1,	604,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	604,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	605,	"R/W",	1,	1,	0,	0},
+	{"DISIDXALIAS"                 ,	0,	1,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISECC"                      ,	1,	1,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"VAB_THRESH"                  ,	2,	4,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"EF_CNT"                      ,	6,	7,	606,	"R/W",	0,	0,	0ull,	4ull},
+	{"EF_ENA"                      ,	13,	1,	606,	"R/W",	0,	0,	0ull,	1ull},
+	{"XMC_ARB_MODE"                ,	14,	1,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSP_ARB_MODE"                ,	15,	1,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXLFB"                      ,	16,	4,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXVAB"                      ,	20,	4,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISCCLK"                     ,	24,	1,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFDBE"                     ,	25,	1,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFSBE"                     ,	26,	1,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISSTGL2I"                   ,	27,	1,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	606,	"RAZ",	1,	1,	0,	0},
+	{"VALID"                       ,	0,	1,	607,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_9"                ,	1,	9,	607,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	10,	28,	607,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	607,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	2,	608,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	608,	"RAZ",	1,	1,	0,	0},
+	{"WAYIDX"                      ,	4,	18,	608,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_22_49"              ,	22,	28,	608,	"RAZ",	1,	1,	0,	0},
+	{"SYN"                         ,	50,	10,	608,	"RO",	0,	0,	0ull,	0ull},
+	{"VSBE"                        ,	60,	1,	608,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VDBE"                        ,	61,	1,	608,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE"                         ,	62,	1,	608,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	63,	1,	608,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TYPE"                        ,	0,	2,	609,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_6"                ,	2,	5,	609,	"RAZ",	1,	1,	0,	0},
+	{"WAYIDX"                      ,	7,	15,	609,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_22_49"              ,	22,	28,	609,	"RAZ",	1,	1,	0,	0},
+	{"SYN"                         ,	50,	6,	609,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_60"              ,	56,	5,	609,	"RAZ",	1,	1,	0,	0},
+	{"NOWAY"                       ,	61,	1,	609,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE"                         ,	62,	1,	609,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	63,	1,	609,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TYPE"                        ,	0,	2,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_49"               ,	2,	48,	610,	"RAZ",	1,	1,	0,	0},
+	{"VSYN"                        ,	50,	10,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"VSBE"                        ,	60,	1,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"VDBE"                        ,	61,	1,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	610,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	38,	611,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_47"              ,	38,	10,	611,	"RAZ",	1,	1,	0,	0},
+	{"SID"                         ,	48,	6,	611,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_54_57"              ,	54,	4,	611,	"RAZ",	1,	1,	0,	0},
+	{"CMD"                         ,	58,	6,	611,	"RO",	0,	1,	0ull,	0},
+	{"HOLERD"                      ,	0,	1,	612,	"R/W",	0,	0,	0ull,	1ull},
+	{"HOLEWR"                      ,	1,	1,	612,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTWR"                       ,	2,	1,	612,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTIDRNG"                    ,	3,	1,	612,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTADRNG"                    ,	4,	1,	612,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTPE"                       ,	5,	1,	612,	"R/W",	0,	0,	0ull,	1ull},
+	{"BIGWR"                       ,	6,	1,	612,	"R/W",	0,	0,	0ull,	1ull},
+	{"BIGRD"                       ,	7,	1,	612,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_8_63"               ,	8,	56,	612,	"RAZ",	1,	1,	0,	0},
+	{"HOLERD"                      ,	0,	1,	613,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HOLEWR"                      ,	1,	1,	613,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTWR"                       ,	2,	1,	613,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTIDRNG"                    ,	3,	1,	613,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTADRNG"                    ,	4,	1,	613,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTPE"                       ,	5,	1,	613,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BIGWR"                       ,	6,	1,	613,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BIGRD"                       ,	7,	1,	613,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	613,	"RAZ",	1,	1,	0,	0},
+	{"TAD0"                        ,	16,	1,	613,	"RO",	0,	0,	0ull,	0ull},
+	{"TAD1"                        ,	17,	1,	613,	"RO",	0,	0,	0ull,	0ull},
+	{"TAD2"                        ,	18,	1,	613,	"RO",	0,	0,	0ull,	0ull},
+	{"TAD3"                        ,	19,	1,	613,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	613,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	614,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	615,	"R/W",	0,	1,	0ull,	0},
+	{"LVL"                         ,	0,	3,	616,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	616,	"RAZ",	1,	1,	0,	0},
+	{"DWBLVL"                      ,	4,	3,	616,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	616,	"RAZ",	1,	1,	0,	0},
+	{"LVL"                         ,	0,	3,	617,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	617,	"RAZ",	1,	1,	0,	0},
+	{"WGT0"                        ,	0,	8,	618,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT1"                        ,	8,	8,	618,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT2"                        ,	16,	8,	618,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT3"                        ,	24,	8,	618,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT4"                        ,	32,	8,	618,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT5"                        ,	40,	8,	618,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT6"                        ,	48,	8,	618,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT7"                        ,	56,	8,	618,	"R/W",	0,	0,	255ull,	255ull},
+	{"COUNT"                       ,	0,	64,	619,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	620,	"R/W",	0,	1,	0ull,	0},
+	{"OW0ECC"                      ,	0,	10,	621,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	621,	"RAZ",	1,	1,	0,	0},
+	{"OW1ECC"                      ,	16,	10,	621,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_31"              ,	26,	6,	621,	"RAZ",	1,	1,	0,	0},
+	{"OW2ECC"                      ,	32,	10,	621,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	621,	"RAZ",	1,	1,	0,	0},
+	{"OW3ECC"                      ,	48,	10,	621,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	621,	"RAZ",	1,	1,	0,	0},
+	{"OW4ECC"                      ,	0,	10,	622,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	622,	"RAZ",	1,	1,	0,	0},
+	{"OW5ECC"                      ,	16,	10,	622,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_31"              ,	26,	6,	622,	"RAZ",	1,	1,	0,	0},
+	{"OW6ECC"                      ,	32,	10,	622,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	622,	"RAZ",	1,	1,	0,	0},
+	{"OW7ECC"                      ,	48,	10,	622,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	622,	"RAZ",	1,	1,	0,	0},
+	{"L2DSBE"                      ,	0,	1,	623,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2DDBE"                      ,	1,	1,	623,	"R/W",	0,	0,	0ull,	1ull},
+	{"TAGSBE"                      ,	2,	1,	623,	"R/W",	0,	0,	0ull,	1ull},
+	{"TAGDBE"                      ,	3,	1,	623,	"R/W",	0,	0,	0ull,	1ull},
+	{"VBFSBE"                      ,	4,	1,	623,	"R/W",	0,	0,	0ull,	1ull},
+	{"VBFDBE"                      ,	5,	1,	623,	"R/W",	0,	0,	0ull,	1ull},
+	{"NOWAY"                       ,	6,	1,	623,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDDISLMC"                    ,	7,	1,	623,	"R/W",	0,	0,	0ull,	1ull},
+	{"WRDISLMC"                    ,	8,	1,	623,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	623,	"RAZ",	1,	1,	0,	0},
+	{"L2DSBE"                      ,	0,	1,	624,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"L2DDBE"                      ,	1,	1,	624,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"TAGSBE"                      ,	2,	1,	624,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"TAGDBE"                      ,	3,	1,	624,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"VBFSBE"                      ,	4,	1,	624,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"VBFDBE"                      ,	5,	1,	624,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"NOWAY"                       ,	6,	1,	624,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDDISLMC"                    ,	7,	1,	624,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WRDISLMC"                    ,	8,	1,	624,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	624,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	625,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	626,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	627,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	628,	"R/W",	0,	1,	0ull,	0},
+	{"CNT0SEL"                     ,	0,	8,	629,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT1SEL"                     ,	8,	8,	629,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT2SEL"                     ,	16,	8,	629,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT3SEL"                     ,	24,	8,	629,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	629,	"RAZ",	1,	1,	0,	0},
+	{"LOCK"                        ,	0,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIRTY"                       ,	1,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"VALID"                       ,	2,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE"                         ,	3,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_16"               ,	4,	13,	630,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	17,	19,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_39"              ,	36,	4,	630,	"RAZ",	1,	1,	0,	0},
+	{"ECC"                         ,	40,	6,	630,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_46_63"              ,	46,	18,	630,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	631,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MASK"                        ,	0,	2,	632,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	632,	"RAZ",	1,	1,	0,	0},
+	{"DWB"                         ,	0,	1,	633,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	1,	1,	633,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	633,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	32,	634,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	634,	"RAZ",	1,	1,	0,	0},
+	{"ID"                          ,	0,	6,	635,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	635,	"RAZ",	1,	1,	0,	0},
+	{"DWBID"                       ,	8,	6,	635,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	635,	"RAZ",	1,	1,	0,	0},
+	{"ID"                          ,	0,	6,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	636,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	1,	637,	"R/W",	0,	0,	0ull,	1ull},
+	{"NUMID"                       ,	1,	3,	637,	"R/W",	0,	0,	5ull,	5ull},
+	{"MEMSZ"                       ,	4,	3,	637,	"R/W",	0,	0,	5ull,	5ull},
+	{"RESERVED_7_7"                ,	7,	1,	637,	"RAZ",	1,	1,	0,	0},
+	{"OOBERR"                      ,	8,	1,	637,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	637,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	32,	638,	"R/W",	0,	0,	0ull,	0ull},
+	{"PARITY"                      ,	32,	4,	638,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	638,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	639,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	639,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	640,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	640,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	641,	"R/W",	0,	1,	0ull,	0},
+	{"ADDR"                        ,	0,	38,	642,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_38_56"              ,	38,	19,	642,	"RAZ",	1,	1,	0,	0},
+	{"CMD"                         ,	57,	6,	642,	"R/W",	1,	1,	0,	0},
+	{"INUSE"                       ,	63,	1,	642,	"RO",	0,	0,	0ull,	0ull},
+	{"COUNT"                       ,	0,	64,	643,	"R/W",	0,	1,	0ull,	0},
+	{"PRBS"                        ,	0,	32,	644,	"R/W",	1,	1,	0,	0},
+	{"PROG"                        ,	32,	8,	644,	"R/W",	1,	1,	0,	0},
+	{"SEL"                         ,	40,	1,	644,	"R/W",	1,	1,	0,	0},
+	{"EN"                          ,	41,	1,	644,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_42_63"              ,	42,	22,	644,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	645,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	8,	646,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	646,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	647,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	8,	648,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	648,	"R/W",	1,	1,	0,	0},
+	{"CKE_MASK"                    ,	0,	2,	649,	"R/W",	1,	1,	0,	0},
+	{"CS0_N_MASK"                  ,	2,	2,	649,	"R/W",	1,	1,	0,	0},
+	{"CS1_N_MASK"                  ,	4,	2,	649,	"R/W",	1,	1,	0,	0},
+	{"ODT0_MASK"                   ,	6,	2,	649,	"R/W",	1,	1,	0,	0},
+	{"ODT1_MASK"                   ,	8,	2,	649,	"R/W",	1,	1,	0,	0},
+	{"RAS_N_MASK"                  ,	10,	1,	649,	"R/W",	1,	1,	0,	0},
+	{"CAS_N_MASK"                  ,	11,	1,	649,	"R/W",	1,	1,	0,	0},
+	{"WE_N_MASK"                   ,	12,	1,	649,	"R/W",	1,	1,	0,	0},
+	{"BA_MASK"                     ,	13,	3,	649,	"R/W",	1,	1,	0,	0},
+	{"A_MASK"                      ,	16,	16,	649,	"R/W",	1,	1,	0,	0},
+	{"RESET_N_MASK"                ,	32,	1,	649,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_33_63"              ,	33,	31,	649,	"R/W",	1,	1,	0,	0},
+	{"DQX_CTL"                     ,	0,	4,	650,	"R/W",	0,	1,	4ull,	0},
+	{"CK_CTL"                      ,	4,	4,	650,	"R/W",	0,	1,	4ull,	0},
+	{"CMD_CTL"                     ,	8,	4,	650,	"R/W",	0,	1,	4ull,	0},
+	{"RODT_CTL"                    ,	12,	4,	650,	"R/W",	0,	1,	0ull,	0},
+	{"NTUNE"                       ,	16,	4,	650,	"R/W",	0,	1,	0ull,	0},
+	{"PTUNE"                       ,	20,	4,	650,	"R/W",	0,	1,	0ull,	0},
+	{"BYP"                         ,	24,	1,	650,	"R/W",	0,	1,	0ull,	0},
+	{"M180"                        ,	25,	1,	650,	"R/W",	0,	1,	0ull,	0},
+	{"DDR__NTUNE"                  ,	26,	4,	650,	"RO",	1,	1,	0,	0},
+	{"DDR__PTUNE"                  ,	30,	4,	650,	"RO",	1,	1,	0,	0},
+	{"RESERVED_34_63"              ,	34,	30,	650,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	651,	"WR0",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	651,	"R/W",	0,	0,	0ull,	1ull},
+	{"ROW_LSB"                     ,	2,	3,	651,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	651,	"R/W",	0,	1,	5ull,	0},
+	{"IDLEPOWER"                   ,	9,	3,	651,	"R/W",	0,	0,	0ull,	6ull},
+	{"FORCEWRITE"                  ,	12,	4,	651,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ADR"                     ,	16,	1,	651,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESET"                       ,	17,	1,	651,	"R/W",	0,	1,	0ull,	0},
+	{"REF_ZQCS_INT"                ,	18,	19,	651,	"R/W",	1,	1,	0,	0},
+	{"SEQUENCE"                    ,	37,	3,	651,	"R/W",	0,	0,	0ull,	0ull},
+	{"EARLY_DQX"                   ,	40,	1,	651,	"R/W",	0,	0,	0ull,	0ull},
+	{"SREF_WITH_DLL"               ,	41,	1,	651,	"R/W",	0,	0,	0ull,	0ull},
+	{"RANK_ENA"                    ,	42,	1,	651,	"R/W",	0,	1,	0ull,	0},
+	{"RANKMASK"                    ,	43,	4,	651,	"R/W",	0,	1,	0ull,	0},
+	{"MIRRMASK"                    ,	47,	4,	651,	"R/W",	0,	1,	0ull,	0},
+	{"INIT_STATUS"                 ,	51,	4,	651,	"R/W1",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D0_R0"          ,	55,	1,	651,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D0_R1"          ,	56,	1,	651,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D1_R0"          ,	57,	1,	651,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D1_R1"          ,	58,	1,	651,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_59_63"              ,	59,	5,	651,	"RAZ",	1,	1,	0,	0},
+	{"RDIMM_ENA"                   ,	0,	1,	652,	"R/W",	0,	1,	0ull,	0},
+	{"BWCNT"                       ,	1,	1,	652,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	2,	1,	652,	"R/W",	0,	0,	0ull,	1ull},
+	{"POCAS"                       ,	3,	1,	652,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPRCH2"                      ,	4,	2,	652,	"R/W",	0,	0,	0ull,	1ull},
+	{"THROTTLE_RD"                 ,	6,	1,	652,	"R/W",	0,	0,	0ull,	0ull},
+	{"THROTTLE_WR"                 ,	7,	1,	652,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_RD"                  ,	8,	1,	652,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_WR"                  ,	9,	1,	652,	"R/W",	0,	0,	0ull,	0ull},
+	{"ELEV_PRIO_DIS"               ,	10,	1,	652,	"R/W",	0,	0,	0ull,	0ull},
+	{"NXM_WRITE_EN"                ,	11,	1,	652,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	12,	4,	652,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	16,	1,	652,	"R/W",	0,	0,	0ull,	1ull},
+	{"AUTO_DCLKDIS"                ,	17,	1,	652,	"R/W",	0,	0,	0ull,	1ull},
+	{"INT_ZQCS_DIS"                ,	18,	1,	652,	"R/W",	0,	0,	1ull,	0ull},
+	{"EXT_ZQCS_DIS"                ,	19,	1,	652,	"R/W",	0,	0,	0ull,	0ull},
+	{"BPRCH"                       ,	20,	2,	652,	"R/W",	0,	0,	0ull,	0ull},
+	{"WODT_BPRCH"                  ,	22,	1,	652,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_BPRCH"                  ,	23,	1,	652,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRM_MAX"                     ,	24,	5,	652,	"R/W",	0,	0,	31ull,	31ull},
+	{"CRM_THR"                     ,	29,	5,	652,	"R/W",	0,	0,	0ull,	8ull},
+	{"CRM_CNT"                     ,	34,	5,	652,	"RO",	0,	0,	0ull,	0ull},
+	{"THRMAX"                      ,	39,	4,	652,	"R/W",	0,	0,	15ull,	2ull},
+	{"PERSUB"                      ,	43,	8,	652,	"R/W",	0,	0,	0ull,	0ull},
+	{"THRCNT"                      ,	51,	12,	652,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_63_63"              ,	63,	1,	652,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT"                     ,	0,	64,	653,	"RO",	0,	1,	0ull,	0},
+	{"CLKF"                        ,	0,	7,	654,	"R/W",	0,	1,	48ull,	0},
+	{"RESET_N"                     ,	7,	1,	654,	"R/W",	0,	0,	0ull,	1ull},
+	{"CPB"                         ,	8,	3,	654,	"R/W",	0,	0,	0ull,	1ull},
+	{"CPS"                         ,	11,	3,	654,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIFFAMP"                     ,	14,	4,	654,	"R/W",	0,	0,	0ull,	1ull},
+	{"DDR_PS_EN"                   ,	18,	3,	654,	"R/W",	0,	1,	2ull,	0},
+	{"DDR_DIV_RESET"               ,	21,	1,	654,	"R/W",	0,	0,	1ull,	0ull},
+	{"DFM_PS_EN"                   ,	22,	3,	654,	"R/W",	0,	1,	2ull,	0},
+	{"DFM_DIV_RESET"               ,	25,	1,	654,	"R/W",	0,	0,	1ull,	0ull},
+	{"JTG_TEST_MODE"               ,	26,	1,	654,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	654,	"RAZ",	1,	1,	0,	0},
+	{"RC0"                         ,	0,	4,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC1"                         ,	4,	4,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC2"                         ,	8,	4,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC3"                         ,	12,	4,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC4"                         ,	16,	4,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC5"                         ,	20,	4,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC6"                         ,	24,	4,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC7"                         ,	28,	4,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC8"                         ,	32,	4,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC9"                         ,	36,	4,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC10"                        ,	40,	4,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC11"                        ,	44,	4,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC12"                        ,	48,	4,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC13"                        ,	52,	4,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC14"                        ,	56,	4,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC15"                        ,	60,	4,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIMM0_WMASK"                 ,	0,	16,	656,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"DIMM1_WMASK"                 ,	16,	16,	656,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"TCWS"                        ,	32,	13,	656,	"R/W",	0,	0,	1248ull,	1248ull},
+	{"PARITY"                      ,	45,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	656,	"RAZ",	1,	1,	0,	0},
+	{"BYP_SETTING"                 ,	0,	8,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYP_SEL"                     ,	8,	4,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"QUAD_DLL_ENA"                ,	12,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	13,	1,	657,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLL_BRINGUP"                 ,	14,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTF_EN"                     ,	15,	1,	657,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	657,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	6,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYTE_SEL"                    ,	6,	4,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE_SEL"                    ,	10,	2,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOAD_OFFSET"                 ,	12,	1,	658,	"WR0",	0,	0,	0ull,	0ull},
+	{"OFFSET_ENA"                  ,	13,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYTE_SEL"              ,	14,	4,	658,	"R/W",	0,	0,	1ull,	1ull},
+	{"DLL_MODE"                    ,	18,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINE_TUNE_MODE"              ,	19,	1,	658,	"R/W",	0,	0,	0ull,	1ull},
+	{"DLL90_SETTING"               ,	20,	8,	658,	"RO",	1,	1,	0,	0},
+	{"DLL_FAST"                    ,	28,	1,	658,	"RO",	1,	1,	0,	0},
+	{"DCLK90_BYP_SETTING"          ,	29,	8,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCLK90_BYP_SEL"              ,	37,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCLK90_RECAL_DIS"            ,	38,	1,	658,	"R/W",	0,	0,	0ull,	1ull},
+	{"DDR_90_DLY_BYP"              ,	39,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCLK90_FWD"                  ,	40,	1,	658,	"WR0",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_63"              ,	41,	23,	658,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	659,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	659,	"RAZ",	1,	1,	0,	0},
+	{"ROW_LSB"                     ,	16,	3,	659,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_19_63"              ,	19,	45,	659,	"RAZ",	1,	1,	0,	0},
+	{"MRDSYN0"                     ,	0,	8,	660,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN1"                     ,	8,	8,	660,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN2"                     ,	16,	8,	660,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN3"                     ,	24,	8,	660,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	660,	"RAZ",	1,	1,	0,	0},
+	{"FCOL"                        ,	0,	14,	661,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	14,	16,	661,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	30,	3,	661,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	33,	1,	661,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	34,	2,	661,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	661,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT"                      ,	0,	64,	662,	"RO",	0,	1,	1ull,	0},
+	{"NXM_WR_ERR"                  ,	0,	1,	663,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SEC_ERR"                     ,	1,	4,	663,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	5,	4,	663,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	663,	"RAZ",	1,	1,	0,	0},
+	{"INTR_NXM_WR_ENA"             ,	0,	1,	664,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_SEC_ENA"                ,	1,	1,	664,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_DED_ENA"                ,	2,	1,	664,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	664,	"RAZ",	1,	1,	0,	0},
+	{"CWL"                         ,	0,	3,	665,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPRLOC"                      ,	3,	2,	665,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPR"                         ,	5,	1,	665,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL"                         ,	6,	1,	665,	"R/W",	0,	0,	0ull,	0ull},
+	{"AL"                          ,	7,	2,	665,	"R/W",	0,	0,	0ull,	0ull},
+	{"WLEV"                        ,	9,	1,	665,	"RO",	0,	0,	0ull,	0ull},
+	{"TDQS"                        ,	10,	1,	665,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOFF"                        ,	11,	1,	665,	"R/W",	0,	0,	0ull,	0ull},
+	{"BL"                          ,	12,	2,	665,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	14,	4,	665,	"R/W",	0,	0,	2ull,	2ull},
+	{"RBT"                         ,	18,	1,	665,	"RO",	0,	0,	1ull,	1ull},
+	{"TM"                          ,	19,	1,	665,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLR"                        ,	20,	1,	665,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRP"                         ,	21,	3,	665,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPD"                         ,	24,	1,	665,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	665,	"RAZ",	1,	1,	0,	0},
+	{"PASR_00"                     ,	0,	3,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_00"                      ,	3,	1,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_00"                      ,	4,	1,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_00"                   ,	5,	2,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_00"                      ,	7,	2,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_00"                  ,	9,	3,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_01"                     ,	12,	3,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_01"                      ,	15,	1,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_01"                      ,	16,	1,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_01"                   ,	17,	2,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_01"                      ,	19,	2,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_01"                  ,	21,	3,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_10"                     ,	24,	3,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_10"                      ,	27,	1,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_10"                      ,	28,	1,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_10"                   ,	29,	2,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_10"                      ,	31,	2,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_10"                  ,	33,	3,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_11"                     ,	36,	3,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_11"                      ,	39,	1,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_11"                      ,	40,	1,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_11"                   ,	41,	2,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_11"                      ,	43,	2,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_11"                  ,	45,	3,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	666,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	667,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D0_R0"               ,	8,	4,	667,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D0_R1"               ,	12,	4,	667,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D1_R0"               ,	16,	4,	667,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D1_R1"               ,	20,	4,	667,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D2_R0"               ,	24,	4,	667,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D2_R1"               ,	28,	4,	667,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D3_R0"               ,	32,	4,	667,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D3_R1"               ,	36,	4,	667,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	667,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT"                      ,	0,	64,	668,	"RO",	0,	1,	1ull,	0},
+	{"TS_STAGGER"                  ,	0,	1,	669,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK_POS"                ,	1,	1,	669,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK"                    ,	2,	1,	669,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT0"                  ,	3,	4,	669,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE0"                    ,	7,	1,	669,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT1"                  ,	8,	4,	669,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE1"                    ,	12,	1,	669,	"R/W",	0,	1,	0ull,	0},
+	{"LV_MODE"                     ,	13,	1,	669,	"R/W",	0,	1,	0ull,	0},
+	{"RX_ALWAYS_ON"                ,	14,	1,	669,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	669,	"RAZ",	1,	1,	0,	0},
+	{"DDR3RST"                     ,	0,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PWARM"                   ,	1,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSOFT"                   ,	2,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSV"                     ,	3,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	670,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	671,	"R/W",	0,	1,	0ull,	0},
+	{"OFFSET"                      ,	4,	4,	671,	"R/W",	0,	0,	2ull,	2ull},
+	{"OFFSET_EN"                   ,	8,	1,	671,	"R/W",	0,	0,	1ull,	1ull},
+	{"OR_DIS"                      ,	9,	1,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	10,	8,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_0"              ,	18,	1,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_1"              ,	19,	1,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_2"              ,	20,	1,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_3"              ,	21,	1,	671,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	671,	"RAZ",	1,	1,	0,	0},
+	{"BITMASK"                     ,	0,	64,	672,	"RO",	0,	0,	0ull,	0ull},
+	{"BYTE0"                       ,	0,	6,	673,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	6,	6,	673,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE2"                       ,	12,	6,	673,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE3"                       ,	18,	6,	673,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE4"                       ,	24,	6,	673,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE5"                       ,	30,	6,	673,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE6"                       ,	36,	6,	673,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE7"                       ,	42,	6,	673,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE8"                       ,	48,	6,	673,	"R/W",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	54,	2,	673,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	673,	"RAZ",	1,	1,	0,	0},
+	{"RODT_D0_R0"                  ,	0,	8,	674,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D0_R1"                  ,	8,	8,	674,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D1_R0"                  ,	16,	8,	674,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D1_R1"                  ,	24,	8,	674,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D2_R0"                  ,	32,	8,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D2_R1"                  ,	40,	8,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R0"                  ,	48,	8,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R1"                  ,	56,	8,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"R2R_INIT"                    ,	0,	6,	675,	"R/W",	0,	1,	1ull,	0},
+	{"R2W_INIT"                    ,	6,	6,	675,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_INIT"                    ,	12,	6,	675,	"R/W",	0,	1,	9ull,	0},
+	{"W2W_INIT"                    ,	18,	6,	675,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	675,	"RAZ",	1,	1,	0,	0},
+	{"R2R_XRANK_INIT"              ,	0,	6,	676,	"R/W",	0,	1,	3ull,	0},
+	{"R2W_XRANK_INIT"              ,	6,	6,	676,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_XRANK_INIT"              ,	12,	6,	676,	"R/W",	0,	1,	4ull,	0},
+	{"W2W_XRANK_INIT"              ,	18,	6,	676,	"R/W",	0,	1,	5ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	676,	"RAZ",	1,	1,	0,	0},
+	{"R2R_XDIMM_INIT"              ,	0,	6,	677,	"R/W",	0,	1,	4ull,	0},
+	{"R2W_XDIMM_INIT"              ,	6,	6,	677,	"R/W",	0,	1,	7ull,	0},
+	{"W2R_XDIMM_INIT"              ,	12,	6,	677,	"R/W",	0,	1,	4ull,	0},
+	{"W2W_XDIMM_INIT"              ,	18,	6,	677,	"R/W",	0,	1,	6ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	677,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_9"                ,	0,	10,	678,	"RAZ",	1,	1,	0,	0},
+	{"TZQCS"                       ,	10,	4,	678,	"R/W",	0,	0,	4ull,	4ull},
+	{"TCKE"                        ,	14,	4,	678,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPR"                        ,	18,	4,	678,	"R/W",	0,	0,	5ull,	5ull},
+	{"TMRD"                        ,	22,	4,	678,	"R/W",	0,	0,	4ull,	4ull},
+	{"TMOD"                        ,	26,	4,	678,	"R/W",	0,	0,	12ull,	12ull},
+	{"TDLLK"                       ,	30,	4,	678,	"R/W",	0,	0,	2ull,	2ull},
+	{"TZQINIT"                     ,	34,	4,	678,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	38,	4,	678,	"R/W",	0,	0,	6ull,	6ull},
+	{"TCKSRE"                      ,	42,	4,	678,	"R/W",	0,	0,	5ull,	5ull},
+	{"TRP_EXT"                     ,	46,	1,	678,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	678,	"RAZ",	1,	1,	0,	0},
+	{"TMPRR"                       ,	0,	4,	679,	"R/W",	0,	0,	1ull,	1ull},
+	{"TRAS"                        ,	4,	5,	679,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	9,	4,	679,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	13,	4,	679,	"R/W",	0,	0,	2ull,	3ull},
+	{"TRFC"                        ,	17,	5,	679,	"R/W",	0,	0,	6ull,	7ull},
+	{"TRRD"                        ,	22,	3,	679,	"R/W",	0,	0,	2ull,	2ull},
+	{"TXP"                         ,	25,	3,	679,	"R/W",	0,	0,	3ull,	3ull},
+	{"TWLMRD"                      ,	28,	4,	679,	"R/W",	0,	0,	10ull,	10ull},
+	{"TWLDQSEN"                    ,	32,	4,	679,	"R/W",	0,	0,	7ull,	7ull},
+	{"TFAW"                        ,	36,	5,	679,	"R/W",	0,	0,	0ull,	9ull},
+	{"TXPDLL"                      ,	41,	5,	679,	"R/W",	0,	0,	0ull,	10ull},
+	{"TRAS_EXT"                    ,	46,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	679,	"RAZ",	1,	1,	0,	0},
+	{"TRESET"                      ,	0,	1,	680,	"R/W",	0,	1,	1ull,	0},
+	{"RCLK_CNT"                    ,	1,	32,	680,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	680,	"RAZ",	1,	1,	0,	0},
+	{"RING_CNT"                    ,	0,	32,	681,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	681,	"RAZ",	1,	1,	0,	0},
+	{"LANEMASK"                    ,	0,	9,	682,	"R/W",	0,	1,	0ull,	0},
+	{"SSET"                        ,	9,	1,	682,	"R/W",	0,	1,	0ull,	0},
+	{"OR_DIS"                      ,	10,	1,	682,	"R/W",	0,	1,	0ull,	0},
+	{"BITMASK"                     ,	11,	8,	682,	"R/W",	0,	1,	0ull,	0},
+	{"RTT_NOM"                     ,	19,	3,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	682,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	4,	8,	683,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	683,	"RAZ",	1,	1,	0,	0},
+	{"BYTE0"                       ,	0,	5,	684,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	5,	5,	684,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE2"                       ,	10,	5,	684,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE3"                       ,	15,	5,	684,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE4"                       ,	20,	5,	684,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE5"                       ,	25,	5,	684,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE6"                       ,	30,	5,	684,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE7"                       ,	35,	5,	684,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE8"                       ,	40,	5,	684,	"R/W",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	45,	2,	684,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_47_63"              ,	47,	17,	684,	"RAZ",	1,	1,	0,	0},
+	{"WODT_D0_R0"                  ,	0,	8,	685,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D0_R1"                  ,	8,	8,	685,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D1_R0"                  ,	16,	8,	685,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D1_R1"                  ,	24,	8,	685,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D2_R0"                  ,	32,	8,	685,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D2_R1"                  ,	40,	8,	685,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D3_R0"                  ,	48,	8,	685,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D3_R1"                  ,	56,	8,	685,	"R/W",	0,	0,	255ull,	0ull},
+	{"STAT"                        ,	0,	10,	686,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	686,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	687,	"R/W",	1,	1,	0,	0},
+	{"PCTL"                        ,	6,	6,	687,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	687,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	688,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	688,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	688,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	688,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	688,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	688,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	688,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	688,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	688,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	688,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	689,	"R/W1C",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	689,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	689,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	690,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	690,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	690,	"RAZ",	1,	1,	0,	0},
+	{"DMARQ"                       ,	0,	6,	691,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_S"                     ,	6,	6,	691,	"R/W",	0,	1,	63ull,	0},
+	{"OE_A"                        ,	12,	6,	691,	"R/W",	0,	1,	63ull,	0},
+	{"OE_N"                        ,	18,	6,	691,	"R/W",	0,	1,	63ull,	0},
+	{"WE_A"                        ,	24,	6,	691,	"R/W",	0,	1,	63ull,	0},
+	{"WE_N"                        ,	30,	6,	691,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_H"                     ,	36,	6,	691,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	42,	6,	691,	"R/W",	0,	1,	63ull,	0},
+	{"RESERVED_48_54"              ,	48,	7,	691,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	55,	1,	691,	"R/W",	0,	1,	0ull,	0},
+	{"DDR"                         ,	56,	1,	691,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	57,	3,	691,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	60,	2,	691,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ_PI"                    ,	62,	1,	691,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK_PI"                    ,	63,	1,	691,	"R/W",	0,	1,	0ull,	0},
+	{"ADR_ERR"                     ,	0,	1,	692,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WAIT_ERR"                    ,	1,	1,	692,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	692,	"RAZ",	1,	1,	0,	0},
+	{"ADR_INT"                     ,	0,	1,	693,	"R/W",	0,	1,	0ull,	0},
+	{"WAIT_INT"                    ,	1,	1,	693,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	693,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	694,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	3,	5,	694,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	694,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	695,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	3,	25,	695,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_30"              ,	28,	3,	695,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	31,	1,	695,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	695,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	696,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	697,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	8,	1,	697,	"RO",	1,	1,	0,	0},
+	{"TERM"                        ,	9,	2,	697,	"RO",	1,	1,	0,	0},
+	{"DMACK_P0"                    ,	11,	1,	697,	"RO",	1,	1,	0,	0},
+	{"DMACK_P1"                    ,	12,	1,	697,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_13"              ,	13,	1,	697,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	14,	1,	697,	"RO",	1,	1,	0,	0},
+	{"ALE"                         ,	15,	1,	697,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	697,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	16,	698,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	16,	12,	698,	"R/W",	0,	1,	0ull,	0},
+	{"WIDTH"                       ,	28,	1,	698,	"R/W",	0,	1,	0ull,	0},
+	{"ALE"                         ,	29,	1,	698,	"R/W",	0,	1,	0ull,	0},
+	{"ORBIT"                       ,	30,	1,	698,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	31,	1,	698,	"R/W",	0,	1,	0ull,	0},
+	{"OE_EXT"                      ,	32,	2,	698,	"R/W",	0,	1,	0ull,	0},
+	{"WE_EXT"                      ,	34,	2,	698,	"R/W",	0,	1,	0ull,	0},
+	{"SAM"                         ,	36,	1,	698,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	37,	3,	698,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	40,	2,	698,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK"                       ,	42,	2,	698,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	698,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	6,	699,	"R/W",	0,	1,	63ull,	0},
+	{"CE"                          ,	6,	6,	699,	"R/W",	0,	1,	63ull,	0},
+	{"OE"                          ,	12,	6,	699,	"R/W",	0,	1,	63ull,	0},
+	{"WE"                          ,	18,	6,	699,	"R/W",	0,	1,	63ull,	0},
+	{"RD_HLD"                      ,	24,	6,	699,	"R/W",	0,	1,	63ull,	0},
+	{"WR_HLD"                      ,	30,	6,	699,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	36,	6,	699,	"R/W",	0,	1,	63ull,	0},
+	{"WAIT"                        ,	42,	6,	699,	"R/W",	0,	1,	63ull,	0},
+	{"PAGE"                        ,	48,	6,	699,	"R/W",	0,	1,	63ull,	0},
+	{"ALE"                         ,	54,	6,	699,	"R/W",	0,	1,	63ull,	0},
+	{"PAGES"                       ,	60,	2,	699,	"R/W",	0,	1,	0ull,	0},
+	{"WAITM"                       ,	62,	1,	699,	"R/W",	0,	1,	0ull,	0},
+	{"PAGEM"                       ,	63,	1,	699,	"R/W",	0,	1,	0ull,	0},
+	{"FIF_THR"                     ,	0,	6,	700,	"R/W",	0,	0,	25ull,	25ull},
+	{"RESERVED_6_7"                ,	6,	2,	700,	"RAZ",	1,	1,	0,	0},
+	{"FIF_CNT"                     ,	8,	6,	700,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	700,	"RAZ",	1,	1,	0,	0},
+	{"DMA_THR"                     ,	16,	6,	700,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_63"              ,	22,	42,	700,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	701,	"R/W",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	702,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	702,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	703,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	703,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	704,	"RO",	1,	1,	0,	0},
+	{"CHIP_ID"                     ,	16,	8,	704,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_25"              ,	24,	2,	704,	"RO",	1,	1,	0,	0},
+	{"NOCRYPTO"                    ,	26,	1,	704,	"RO",	1,	1,	0,	0},
+	{"NOMUL"                       ,	27,	1,	704,	"RO",	1,	1,	0,	0},
+	{"NODFA_CP2"                   ,	28,	1,	704,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_31"              ,	29,	3,	704,	"RO",	1,	1,	0,	0},
+	{"RAID_EN"                     ,	32,	1,	704,	"RO",	1,	1,	0,	0},
+	{"FUS318"                      ,	33,	1,	704,	"RO",	1,	1,	0,	0},
+	{"DORM_CRYPTO"                 ,	34,	1,	704,	"RO",	1,	1,	0,	0},
+	{"POWER_LIMIT"                 ,	35,	2,	704,	"RO",	1,	1,	0,	0},
+	{"RESERVED_37_63"              ,	37,	27,	704,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	705,	"RAZ",	1,	1,	0,	0},
+	{"NODFA_DTE"                   ,	24,	1,	705,	"RO",	1,	1,	0,	0},
+	{"NOZIP"                       ,	25,	1,	705,	"RO",	1,	1,	0,	0},
+	{"EFUS_IGN"                    ,	26,	1,	705,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK"                    ,	27,	1,	705,	"RO",	1,	1,	0,	0},
+	{"BAR2_EN"                     ,	28,	1,	705,	"RO",	1,	1,	0,	0},
+	{"ZIP_INFO"                    ,	29,	2,	705,	"RO",	1,	1,	0,	0},
+	{"RESERVED_31_31"              ,	31,	1,	705,	"RAZ",	1,	1,	0,	0},
+	{"L2C_CRIP"                    ,	32,	3,	705,	"RO",	1,	1,	0,	0},
+	{"PLL_HALF_DIS"                ,	35,	1,	705,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK_MAN"                ,	36,	1,	705,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK_RSV"                ,	37,	1,	705,	"RO",	1,	1,	0,	0},
+	{"EMA"                         ,	38,	2,	705,	"RO",	1,	1,	0,	0},
+	{"RESERVED_40_40"              ,	40,	1,	705,	"RAZ",	1,	1,	0,	0},
+	{"DFA_INFO_CLM"                ,	41,	4,	705,	"RO",	1,	1,	0,	0},
+	{"DFA_INFO_DTE"                ,	45,	3,	705,	"RO",	1,	1,	0,	0},
+	{"PLL_CTL"                     ,	48,	10,	705,	"RO",	1,	1,	0,	0},
+	{"RESERVED_58_63"              ,	58,	6,	705,	"RAZ",	1,	1,	0,	0},
+	{"EMA"                         ,	0,	3,	706,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_3_3"                ,	3,	1,	706,	"RAZ",	1,	1,	0,	0},
+	{"EFF_EMA"                     ,	4,	3,	706,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_7_63"               ,	7,	57,	706,	"RAZ",	1,	1,	0,	0},
+	{"PDF"                         ,	0,	64,	707,	"RO",	1,	1,	0,	0},
+	{"FBSLIP"                      ,	0,	1,	708,	"RAZ",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	708,	"RAZ",	0,	1,	0ull,	0},
+	{"PNR_COUT_SEL"                ,	2,	2,	708,	"R/W",	0,	1,	0ull,	0},
+	{"PNR_COUT_RST"                ,	4,	1,	708,	"R/W",	0,	1,	0ull,	0},
+	{"C_COUT_SEL"                  ,	5,	2,	708,	"R/W",	0,	1,	0ull,	0},
+	{"C_COUT_RST"                  ,	7,	1,	708,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_31"               ,	8,	24,	708,	"RAZ",	1,	1,	0,	0},
+	{"RCLK_ALIGN_L"                ,	32,	8,	708,	"RO",	1,	1,	0,	0},
+	{"RCLK_ALIGN_R"                ,	40,	8,	708,	"RO",	1,	1,	0,	0},
+	{"RESERVED_48_63"              ,	48,	16,	708,	"RO",	1,	1,	0,	0},
+	{"PROG"                        ,	0,	1,	709,	"R/W",	1,	1,	0,	0},
+	{"SOFT"                        ,	1,	1,	709,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	709,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	6,	710,	"R/W",	0,	1,	1ull,	0},
+	{"SCLK_HI"                     ,	6,	15,	710,	"R/W",	0,	1,	5000ull,	0},
+	{"SCLK_LO"                     ,	21,	4,	710,	"R/W",	0,	1,	1ull,	0},
+	{"OUT"                         ,	25,	7,	710,	"R/W",	0,	1,	1ull,	0},
+	{"PROG_PIN"                    ,	32,	1,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"FSRC_PIN"                    ,	33,	1,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"VGATE_PIN"                   ,	34,	1,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	710,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	8,	711,	"R/W",	0,	0,	0ull,	0ull},
+	{"EFUSE"                       ,	8,	1,	711,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	711,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	12,	1,	711,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	711,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	16,	8,	711,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_63"              ,	24,	40,	711,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	10,	712,	"R/W",	0,	1,	999ull,	0},
+	{"SDH"                         ,	10,	4,	712,	"R/W",	0,	1,	0ull,	0},
+	{"PRH"                         ,	14,	4,	712,	"R/W",	0,	1,	6ull,	0},
+	{"FSH"                         ,	18,	4,	712,	"R/W",	0,	1,	15ull,	0},
+	{"SCH"                         ,	22,	4,	712,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	712,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	18,	713,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR1"                     ,	18,	18,	713,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR2"                     ,	36,	18,	713,	"RO",	0,	0,	0ull,	0ull},
+	{"TOO_MANY"                    ,	54,	1,	713,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	713,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR3"                     ,	0,	18,	714,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR4"                     ,	18,	18,	714,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR5"                     ,	36,	18,	714,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	714,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR6"                     ,	0,	18,	715,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	715,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	14,	716,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR1"                     ,	14,	14,	716,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR2"                     ,	28,	14,	716,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_42_63"              ,	42,	22,	716,	"RAZ",	1,	1,	0,	0},
+	{"TOO_MANY"                    ,	0,	1,	717,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	717,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	4,	718,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_4_63"               ,	4,	60,	718,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	719,	"R/W",	0,	1,	15ull,	0},
+	{"PCTL"                        ,	6,	6,	719,	"R/W",	0,	1,	19ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	719,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	720,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	720,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	720,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	720,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	720,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	720,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	720,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	720,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	720,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	720,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	721,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	721,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	722,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	722,	"RAZ",	1,	1,	0,	0},
+	{"PTP_EN"                      ,	0,	1,	723,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_CLK_EN"                  ,	1,	1,	723,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_CLK_IN"                  ,	2,	6,	723,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_EN"                    ,	8,	1,	723,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_EDGE"                  ,	9,	1,	723,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_IN"                    ,	10,	6,	723,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_EN"                    ,	16,	1,	723,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_EDGE"                  ,	17,	1,	723,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_IN"                    ,	18,	6,	723,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	723,	"RAZ",	1,	1,	0,	0},
+	{"FRNANOSEC"                   ,	0,	32,	724,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	724,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	0,	64,	725,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	726,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	726,	"RAZ",	1,	1,	0,	0},
+	{"CNTR"                        ,	0,	64,	727,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	0,	64,	728,	"R/W",	0,	0,	0ull,	0ull},
+	{"QLM_CFG"                     ,	0,	3,	729,	"RO",	1,	1,	0,	0},
+	{"RESERVED_3_7"                ,	3,	5,	729,	"RAZ",	1,	1,	0,	0},
+	{"QLM_SPD"                     ,	8,	4,	729,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	729,	"RAZ",	1,	1,	0,	0},
+	{"RBOOT_PIN"                   ,	0,	1,	730,	"RO",	1,	1,	0,	0},
+	{"RBOOT"                       ,	1,	1,	730,	"R/W",	1,	1,	0,	0},
+	{"LBOOT"                       ,	2,	10,	730,	"R/W1C",	1,	1,	0,	0},
+	{"QLM0_SPD"                    ,	12,	4,	730,	"RO",	1,	1,	0,	0},
+	{"QLM1_SPD"                    ,	16,	4,	730,	"RO",	1,	1,	0,	0},
+	{"QLM2_SPD"                    ,	20,	4,	730,	"RO",	1,	1,	0,	0},
+	{"PNR_MUL"                     ,	24,	6,	730,	"RO",	1,	1,	0,	0},
+	{"C_MUL"                       ,	30,	6,	730,	"RO",	1,	1,	0,	0},
+	{"QLM3_SPD"                    ,	36,	4,	730,	"RO",	1,	1,	0,	0},
+	{"QLM4_SPD"                    ,	40,	4,	730,	"RO",	1,	1,	0,	0},
+	{"RESERVED_44_63"              ,	44,	20,	730,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_CLR_BIST"               ,	0,	1,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"WARM_CLR_BIST"               ,	1,	1,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNTL_CLR_BIST"               ,	2,	1,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	731,	"RAZ",	1,	1,	0,	0},
+	{"BIST_DELAY"                  ,	8,	56,	731,	"RO",	1,	1,	0,	0},
+	{"RST_VAL"                     ,	0,	1,	732,	"RO",	1,	1,	0,	0},
+	{"RST_CHIP"                    ,	1,	1,	732,	"R/W",	0,	1,	0ull,	0},
+	{"RST_RCV"                     ,	2,	1,	732,	"R/W",	1,	1,	0,	0},
+	{"RST_DRV"                     ,	3,	1,	732,	"R/W",	1,	1,	0,	0},
+	{"PRTMODE"                     ,	4,	2,	732,	"R/W",	1,	1,	0,	0},
+	{"HOST_MODE"                   ,	6,	1,	732,	"RO",	1,	1,	0,	0},
+	{"RST_LINK"                    ,	7,	1,	732,	"R/W",	1,	1,	0,	0},
+	{"RST_DONE"                    ,	8,	1,	732,	"RO",	1,	1,	0,	0},
+	{"PRST_LINK"                   ,	9,	1,	732,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	732,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST_DLY"                ,	0,	16,	733,	"R/W",	0,	1,	2047ull,	0},
+	{"WARM_RST_DLY"                ,	16,	16,	733,	"R/W",	0,	1,	2047ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	733,	"RAZ",	1,	1,	0,	0},
+	{"RST_LINK0"                   ,	0,	1,	734,	"R/W1C",	0,	1,	0ull,	0},
+	{"RST_LINK1"                   ,	1,	1,	734,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_7"                ,	2,	6,	734,	"RAZ",	1,	1,	0,	0},
+	{"PERST0"                      ,	8,	1,	734,	"R/W1C",	0,	1,	0ull,	0},
+	{"PERST1"                      ,	9,	1,	734,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	734,	"RAZ",	1,	1,	0,	0},
+	{"RST_LINK0"                   ,	0,	1,	735,	"R/W",	0,	1,	0ull,	0},
+	{"RST_LINK1"                   ,	1,	1,	735,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_7"                ,	2,	6,	735,	"RAZ",	1,	1,	0,	0},
+	{"PERST0"                      ,	8,	1,	735,	"R/W",	0,	1,	0ull,	0},
+	{"PERST1"                      ,	9,	1,	735,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	735,	"RAZ",	1,	1,	0,	0},
+	{"ST_INT"                      ,	0,	1,	736,	"R/W1C",	0,	1,	0ull,	0},
+	{"TS_INT"                      ,	1,	1,	736,	"R/W1C",	0,	1,	0ull,	0},
+	{"CORE_INT"                    ,	2,	1,	736,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	736,	"RAZ",	1,	1,	0,	0},
+	{"ST_EN"                       ,	4,	1,	736,	"R/W",	0,	1,	0ull,	0},
+	{"TS_EN"                       ,	5,	1,	736,	"R/W",	0,	1,	0ull,	0},
+	{"CORE_EN"                     ,	6,	1,	736,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	736,	"RAZ",	1,	1,	0,	0},
+	{"SDA_OVR"                     ,	8,	1,	736,	"R/W",	0,	1,	0ull,	0},
+	{"SCL_OVR"                     ,	9,	1,	736,	"R/W",	0,	1,	0ull,	0},
+	{"SDA"                         ,	10,	1,	736,	"RO",	1,	1,	0,	0},
+	{"SCL"                         ,	11,	1,	736,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	736,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	737,	"R/W",	0,	1,	0ull,	0},
+	{"EOP_IA"                      ,	32,	3,	737,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	35,	5,	737,	"R/W",	0,	1,	0ull,	0},
+	{"A"                           ,	40,	10,	737,	"R/W",	0,	1,	0ull,	0},
+	{"SCR"                         ,	50,	2,	737,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	52,	3,	737,	"R/W",	0,	1,	0ull,	0},
+	{"SOVR"                        ,	55,	1,	737,	"R/W",	0,	1,	0ull,	0},
+	{"R"                           ,	56,	1,	737,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	57,	4,	737,	"R/W",	0,	1,	0ull,	0},
+	{"EIA"                         ,	61,	1,	737,	"R/W",	0,	1,	0ull,	0},
+	{"SLONLY"                      ,	62,	1,	737,	"R/W",	0,	1,	0ull,	0},
+	{"V"                           ,	63,	1,	737,	"RC/W",	0,	1,	0ull,	0},
+	{"D"                           ,	0,	32,	738,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	32,	8,	738,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	738,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	739,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_32_61"              ,	32,	30,	739,	"RAZ",	1,	1,	0,	0},
+	{"V"                           ,	62,	2,	739,	"RC/W",	0,	1,	0ull,	0},
+	{"DLH"                         ,	0,	8,	740,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	740,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	741,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	741,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	742,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	742,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	743,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	743,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	743,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	743,	"RAZ",	1,	1,	0,	0},
+	{"TXTRIG"                      ,	4,	2,	743,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	743,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	743,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	744,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	744,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	745,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	745,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	745,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	745,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	745,	"RAZ",	1,	1,	0,	0},
+	{"PTIME"                       ,	7,	1,	745,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	745,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	746,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	746,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	746,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	746,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	747,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	747,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	747,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	747,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	747,	"RAZ",	1,	1,	0,	0},
+	{"BRK"                         ,	6,	1,	747,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	747,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	747,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	748,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	748,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	748,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	748,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	748,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	748,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	748,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	748,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	748,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	749,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	749,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	749,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	749,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	749,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	749,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	749,	"RAZ",	1,	1,	0,	0},
+	{"DCTS"                        ,	0,	1,	750,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	750,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	750,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	750,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	750,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	750,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	750,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	750,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	750,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	751,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	751,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	752,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	752,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	753,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	753,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	753,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	753,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	754,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	754,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	755,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	755,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	756,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	756,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	757,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	757,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	757,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	757,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	758,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	758,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	759,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	759,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	760,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	760,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	761,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	761,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	762,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	762,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	763,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	763,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	764,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	764,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	764,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	764,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	764,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	764,	"RAZ",	1,	1,	0,	0},
+	{"ORFDAT"                      ,	0,	1,	765,	"RO",	0,	0,	0ull,	0ull},
+	{"IRFDAT"                      ,	1,	1,	765,	"RO",	0,	0,	0ull,	0ull},
+	{"IPFDAT"                      ,	2,	1,	765,	"RO",	0,	0,	0ull,	0ull},
+	{"MRQDAT"                      ,	3,	1,	765,	"RO",	0,	0,	0ull,	0ull},
+	{"MRGDAT"                      ,	4,	1,	765,	"RO",	0,	0,	0ull,	0ull},
+	{"OPFDAT"                      ,	5,	1,	765,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	765,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MRQ_HWM"                     ,	0,	2,	766,	"R/W",	0,	0,	0ull,	1ull},
+	{"NBTARB"                      ,	2,	1,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENDIAN"                     ,	3,	1,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	4,	1,	766,	"R/W",	0,	0,	1ull,	0ull},
+	{"EN"                          ,	5,	1,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"BUSY"                        ,	6,	1,	766,	"RO",	0,	0,	0ull,	0ull},
+	{"CRC_STRIP"                   ,	7,	1,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"TS_THRESH"                   ,	8,	4,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	766,	"RAZ",	1,	1,	0,	0},
+	{"OVFENA"                      ,	0,	1,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"IVFENA"                      ,	1,	1,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTHENA"                      ,	2,	1,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"ITHENA"                      ,	3,	1,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_DRPENA"                 ,	4,	1,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"IRUNENA"                     ,	5,	1,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"ORUNENA"                     ,	6,	1,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSENA"                       ,	7,	1,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	767,	"RAZ",	1,	1,	0,	0},
+	{"IRCNT"                       ,	0,	20,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	768,	"RAZ",	1,	1,	0,	0},
+	{"IRHWM"                       ,	0,	20,	769,	"R/W",	0,	0,	0ull,	0ull},
+	{"IBPLWM"                      ,	20,	20,	769,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	769,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	770,	"RAZ",	1,	1,	0,	0},
+	{"IBASE"                       ,	3,	37,	770,	"R/W",	0,	1,	0ull,	0},
+	{"ISIZE"                       ,	40,	20,	770,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	770,	"RAZ",	1,	1,	0,	0},
+	{"IDBELL"                      ,	0,	20,	771,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	771,	"RAZ",	1,	1,	0,	0},
+	{"ITLPTR"                      ,	32,	20,	771,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	771,	"RAZ",	1,	1,	0,	0},
+	{"ODBLOVF"                     ,	0,	1,	772,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IDBLOVF"                     ,	1,	1,	772,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORTHRESH"                    ,	2,	1,	772,	"RO",	0,	0,	0ull,	0ull},
+	{"IRTHRESH"                    ,	3,	1,	772,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_DRP"                    ,	4,	1,	772,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IRUN"                        ,	5,	1,	772,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORUN"                        ,	6,	1,	772,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TS"                          ,	7,	1,	772,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	772,	"RAZ",	1,	1,	0,	0},
+	{"ORCNT"                       ,	0,	20,	773,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	773,	"RAZ",	1,	1,	0,	0},
+	{"ORHWM"                       ,	0,	20,	774,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	774,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	775,	"RAZ",	1,	1,	0,	0},
+	{"OBASE"                       ,	3,	37,	775,	"R/W",	0,	1,	0ull,	0},
+	{"OSIZE"                       ,	40,	20,	775,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	775,	"RAZ",	1,	1,	0,	0},
+	{"ODBELL"                      ,	0,	20,	776,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	776,	"RAZ",	1,	1,	0,	0},
+	{"OTLPTR"                      ,	32,	20,	776,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	776,	"RAZ",	1,	1,	0,	0},
+	{"OREMCNT"                     ,	0,	20,	777,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	777,	"RAZ",	1,	1,	0,	0},
+	{"IREMCNT"                     ,	32,	20,	777,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_52_63"              ,	52,	12,	777,	"RAZ",	1,	1,	0,	0},
+	{"TSCNT"                       ,	0,	5,	778,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	778,	"RAZ",	1,	1,	0,	0},
+	{"TSTOT"                       ,	8,	5,	778,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	778,	"RAZ",	1,	1,	0,	0},
+	{"TSAVL"                       ,	16,	5,	778,	"RO",	0,	0,	4ull,	4ull},
+	{"RESERVED_21_63"              ,	21,	43,	778,	"RAZ",	1,	1,	0,	0},
+	{"TSTAMP"                      ,	0,	64,	779,	"RO",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	3,	780,	"R/W",	0,	1,	0ull,	0},
+	{"ADR_CYC"                     ,	3,	4,	780,	"R/W",	0,	1,	8ull,	0},
+	{"T_MULT"                      ,	7,	4,	780,	"R/W",	0,	1,	9ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	780,	"RAZ",	1,	1,	0,	0},
+	{"NF_CMD"                      ,	0,	64,	781,	"R/W",	0,	1,	0ull,	0},
+	{"CNT"                         ,	0,	8,	782,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	782,	"RAZ",	1,	1,	0,	0},
+	{"ECC_ERR"                     ,	0,	8,	783,	"RO",	0,	1,	0ull,	0},
+	{"XOR_ECC"                     ,	8,	24,	783,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	783,	"RAZ",	1,	1,	0,	0},
+	{"EMPTY"                       ,	0,	1,	784,	"R/W1C",	0,	1,	0ull,	0},
+	{"FULL"                        ,	1,	1,	784,	"R/W1C",	0,	1,	0ull,	0},
+	{"WDOG"                        ,	2,	1,	784,	"R/W1C",	0,	1,	0ull,	0},
+	{"SM_BAD"                      ,	3,	1,	784,	"R/W1C",	0,	1,	0ull,	0},
+	{"ECC_1BIT"                    ,	4,	1,	784,	"R/W1C",	0,	1,	0ull,	0},
+	{"ECC_MULT"                    ,	5,	1,	784,	"R/W1C",	0,	1,	0ull,	0},
+	{"OVRF"                        ,	6,	1,	784,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	784,	"RAZ",	1,	1,	0,	0},
+	{"EMPTY"                       ,	0,	1,	785,	"R/W",	0,	1,	0ull,	0},
+	{"FULL"                        ,	1,	1,	785,	"R/W",	0,	1,	0ull,	0},
+	{"WDOG"                        ,	2,	1,	785,	"R/W",	0,	1,	0ull,	0},
+	{"SM_BAD"                      ,	3,	1,	785,	"R/W",	0,	1,	0ull,	0},
+	{"ECC_1BIT"                    ,	4,	1,	785,	"R/W",	0,	1,	0ull,	0},
+	{"ECC_MULT"                    ,	5,	1,	785,	"R/W",	0,	1,	0ull,	0},
+	{"OVRF"                        ,	6,	1,	785,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	785,	"RAZ",	1,	1,	0,	0},
+	{"RST_FF"                      ,	0,	1,	786,	"R/W",	0,	0,	0ull,	0ull},
+	{"EX_DIS"                      ,	1,	1,	786,	"R/W",	0,	0,	0ull,	0ull},
+	{"BT_DIS"                      ,	2,	1,	786,	"R/W",	0,	0,	0ull,	1ull},
+	{"BT_DMA"                      ,	3,	1,	786,	"R/W",	0,	1,	0ull,	0},
+	{"RD_CMD"                      ,	4,	1,	786,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD_VAL"                      ,	5,	1,	786,	"RO",	0,	1,	0ull,	0},
+	{"RD_DONE"                     ,	6,	1,	786,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FR_BYT"                      ,	7,	11,	786,	"RO",	0,	1,	0ull,	0},
+	{"WAIT_CNT"                    ,	18,	6,	786,	"R/W",	0,	1,	20ull,	0},
+	{"NBR_HWM"                     ,	24,	3,	786,	"R/W",	0,	0,	3ull,	3ull},
+	{"MB_DIS"                      ,	27,	1,	786,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	786,	"RAZ",	1,	1,	0,	0},
+	{"MAIN_SM"                     ,	0,	3,	787,	"RO",	0,	1,	0ull,	0},
+	{"MAIN_BAD"                    ,	3,	1,	787,	"RO",	0,	1,	0ull,	0},
+	{"RD_FF"                       ,	4,	2,	787,	"RO",	0,	1,	0ull,	0},
+	{"RD_FF_BAD"                   ,	6,	1,	787,	"RO",	0,	1,	0ull,	0},
+	{"BT_SM"                       ,	7,	4,	787,	"RO",	0,	1,	0ull,	0},
+	{"EXE_SM"                      ,	11,	4,	787,	"RO",	0,	1,	0ull,	0},
+	{"EXE_IDLE"                    ,	15,	1,	787,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	787,	"RAZ",	1,	1,	0,	0},
+	{"VENDID"                      ,	0,	16,	788,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	788,	"RO/WRSL",	0,	0,	145ull,	145ull},
+	{"ISAE"                        ,	0,	1,	789,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	789,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	789,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	789,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	789,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	789,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	789,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	789,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	789,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	789,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	789,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	789,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	789,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	789,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	789,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	789,	"RAZ",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	789,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	789,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	789,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	789,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	789,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	789,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	789,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	789,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	790,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PI"                          ,	8,	8,	790,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	790,	"RO/WRSL",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	790,	"RO/WRSL",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	791,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	791,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	791,	"RO",	0,	0,	0ull,	0ull},
+	{"MFD"                         ,	23,	1,	791,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	791,	"RO",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	792,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	792,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	792,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_13"               ,	4,	10,	792,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	14,	18,	792,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	793,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	793,	"WORSL",	0,	0,	8191ull,	8191ull},
+	{"UBAB"                        ,	0,	32,	794,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	795,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	796,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	796,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	796,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_25"               ,	4,	22,	796,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	26,	6,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	797,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	797,	"WORSL",	0,	0,	33554431ull,	33554431ull},
+	{"UBAB"                        ,	0,	32,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	799,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	800,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	800,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	800,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_31"               ,	4,	28,	800,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	1,	801,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	801,	"WORSL",	0,	0,	2147483647ull,	2147483647ull},
+	{"RESERVED_0_8"                ,	0,	9,	802,	"RAZ",	1,	1,	0,	0},
+	{"UBAB"                        ,	9,	23,	802,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	803,	"WORSL",	0,	0,	511ull,	511ull},
+	{"CISP"                        ,	0,	32,	804,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SSVID"                       ,	0,	16,	805,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"SSID"                        ,	16,	16,	805,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"ER_EN"                       ,	0,	1,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_15"               ,	1,	15,	806,	"RAZ",	1,	1,	0,	0},
+	{"ERADDR"                      ,	16,	16,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	807,	"WORSL",	0,	0,	1ull,	1ull},
+	{"MASK"                        ,	1,	31,	807,	"WORSL",	0,	0,	32767ull,	32767ull},
+	{"CP"                          ,	0,	8,	808,	"RO/WRSL",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	808,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	809,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	809,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"MG"                          ,	16,	8,	809,	"RO",	0,	0,	0ull,	0ull},
+	{"ML"                          ,	24,	8,	809,	"RO",	0,	0,	0ull,	0ull},
+	{"PMCID"                       ,	0,	8,	810,	"RO",	0,	0,	1ull,	0ull},
+	{"NCP"                         ,	8,	8,	810,	"RO/WRSL",	0,	0,	80ull,	0ull},
+	{"PMSV"                        ,	16,	3,	810,	"RO/WRSL",	0,	0,	3ull,	0ull},
+	{"PME_CLOCK"                   ,	19,	1,	810,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	810,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	810,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	810,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	810,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	810,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	810,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	811,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	811,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	811,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	811,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	811,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	811,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	811,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	811,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	811,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	811,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	811,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	811,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	812,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	812,	"RO/WRSL",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	812,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	812,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	812,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	812,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"PVM"                         ,	24,	1,	812,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	812,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	813,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	813,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	814,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	815,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	816,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	816,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	816,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	816,	"RO",	0,	0,	0ull,	0ull},
+	{"SI"                          ,	24,	1,	816,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	816,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	816,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	817,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	817,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	817,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	817,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"EL1AL"                       ,	9,	3,	817,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"RESERVED_12_14"              ,	12,	3,	817,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	817,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	817,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	817,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	817,	"RO",	0,	0,	0ull,	0ull},
+	{"FLR"                         ,	28,	1,	817,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	817,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	818,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	818,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	818,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	818,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	818,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	818,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	818,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	818,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	818,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	818,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	818,	"R/W",	0,	0,	2ull,	2ull},
+	{"I_FLR"                       ,	15,	1,	818,	"RO",	0,	0,	0ull,	0ull},
+	{"CE_D"                        ,	16,	1,	818,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	818,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	818,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	818,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	818,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	818,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	818,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	819,	"RO/WRSL",	1,	1,	0,	0},
+	{"MLW"                         ,	4,	6,	819,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"ASLPMS"                      ,	10,	2,	819,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	819,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	819,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	819,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	819,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	819,	"RO",	0,	0,	0ull,	0ull},
+	{"LBNC"                        ,	21,	1,	819,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	819,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	819,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	820,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	820,	"RO",	0,	0,	0ull,	0ull},
+	{"LD"                          ,	4,	1,	820,	"RO",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	820,	"RO",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"LBM_INT_ENB"                 ,	10,	1,	820,	"RO",	0,	0,	0ull,	0ull},
+	{"LAB_INT_ENB"                 ,	11,	1,	820,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	820,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	820,	"RO",	0,	0,	1ull,	1ull},
+	{"NLW"                         ,	20,	6,	820,	"RO",	0,	0,	0ull,	8ull},
+	{"RESERVED_26_26"              ,	26,	1,	820,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	820,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	820,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"DLLA"                        ,	29,	1,	820,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	820,	"RAZ",	1,	1,	0,	0},
+	{"CTRS"                        ,	0,	4,	821,	"RO",	0,	0,	0ull,	0ull},
+	{"CTDS"                        ,	4,	1,	821,	"RO",	0,	0,	1ull,	1ull},
+	{"ARI"                         ,	5,	1,	821,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OPS"                    ,	6,	1,	821,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM32S"                     ,	7,	1,	821,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM64S"                     ,	8,	1,	821,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM128S"                    ,	9,	1,	821,	"RO",	0,	0,	0ull,	0ull},
+	{"NOROPRPR"                    ,	10,	1,	821,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	821,	"RAZ",	1,	1,	0,	0},
+	{"TPH"                         ,	12,	2,	821,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	821,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	822,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	822,	"R/W",	0,	0,	0ull,	0ull},
+	{"ARI"                         ,	5,	1,	822,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP"                     ,	6,	1,	822,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP_EB"                  ,	7,	1,	822,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_RQ"                      ,	8,	1,	822,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_CP"                      ,	9,	1,	822,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_31"              ,	10,	22,	822,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	823,	"RAZ",	1,	1,	0,	0},
+	{"SLSV"                        ,	1,	7,	823,	"RO/WRSL",	1,	1,	0,	0},
+	{"CLS"                         ,	8,	1,	823,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	823,	"RAZ",	1,	1,	0,	0},
+	{"TLS"                         ,	0,	4,	824,	"R/W",	1,	0,	0,	2ull},
+	{"EC"                          ,	4,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"HASD"                        ,	5,	1,	824,	"RO",	0,	0,	0ull,	0ull},
+	{"SDE"                         ,	6,	1,	824,	"RO",	0,	0,	0ull,	0ull},
+	{"TM"                          ,	7,	3,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMC"                         ,	10,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSOS"                        ,	11,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDE"                         ,	12,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	824,	"RAZ",	1,	1,	0,	0},
+	{"CDL"                         ,	16,	1,	824,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	824,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	825,	"RO",	0,	0,	1ull,	1ull},
+	{"CV"                          ,	16,	4,	825,	"RO",	0,	0,	2ull,	2ull},
+	{"NCO"                         ,	20,	12,	825,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	826,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	826,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	826,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	826,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	827,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	827,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	827,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	827,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	828,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	828,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	828,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	828,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	828,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	828,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	828,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	828,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	829,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	829,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	829,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	829,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	829,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	829,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	829,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	829,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	829,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	830,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	830,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	830,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	830,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	831,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	831,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	831,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	831,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	831,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	831,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	832,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	833,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	834,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	835,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	836,	"R/W",	0,	1,	4143ull,	0},
+	{"RTL"                         ,	16,	16,	836,	"R/W",	0,	1,	12429ull,	0},
+	{"OMR"                         ,	0,	32,	837,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	838,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_14"               ,	8,	7,	838,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	838,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	838,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	838,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	838,	"R/W",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	839,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	839,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	839,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	839,	"R/W",	0,	0,	3ull,	3ull},
+	{"EASPML1"                     ,	30,	1,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	839,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	840,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	840,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	840,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	840,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	840,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	840,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	840,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	840,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	840,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	840,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_22_31"              ,	22,	10,	840,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	841,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	841,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	841,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	841,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	841,	"R/W",	0,	0,	0ull,	0ull},
+	{"NTSS"                        ,	0,	4,	842,	"R/W",	0,	0,	10ull,	10ull},
+	{"RESERVED_4_7"                ,	4,	4,	842,	"RO",	1,	1,	0,	0},
+	{"NSKPS"                       ,	8,	3,	842,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_11_13"              ,	11,	3,	842,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	842,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	842,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	842,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	842,	"RO",	1,	1,	0,	0},
+	{"SKPIV"                       ,	0,	11,	843,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	843,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	843,	"R/W",	0,	0,	1ull,	1ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	844,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	844,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	844,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	845,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	846,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	847,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	847,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	847,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	848,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	848,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	848,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	849,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	849,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	849,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	850,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	850,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	850,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	850,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	851,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	852,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	852,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	852,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	852,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	853,	"RO/WRSL",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	853,	"RO/WRSL",	0,	0,	96ull,	96ull},
+	{"RESERVED_20_20"              ,	20,	1,	853,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	853,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	853,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	853,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	853,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	854,	"RO/WRSL",	0,	0,	32ull,	32ull},
+	{"HEADER_CREDITS"              ,	12,	8,	854,	"RO/WRSL",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_20"              ,	20,	1,	854,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	854,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	854,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	855,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HEADER_CREDITS"              ,	12,	8,	855,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	855,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	855,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	855,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	856,	"RO/WRSL",	0,	0,	392ull,	392ull},
+	{"RESERVED_14_15"              ,	14,	2,	856,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	856,	"RO/WRSL",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	856,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	857,	"RO/WRSL",	0,	0,	136ull,	136ull},
+	{"RESERVED_14_15"              ,	14,	2,	857,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	857,	"RO/WRSL",	0,	0,	38ull,	38ull},
+	{"RESERVED_26_31"              ,	26,	6,	857,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	858,	"RO/WRSL",	0,	0,	679ull,	679ull},
+	{"RESERVED_14_15"              ,	14,	2,	858,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	858,	"RO/WRSL",	0,	0,	133ull,	133ull},
+	{"RESERVED_26_31"              ,	26,	6,	858,	"RAZ",	1,	1,	0,	0},
+	{"N_FTS"                       ,	0,	8,	859,	"R/W",	0,	0,	128ull,	128ull},
+	{"LE"                          ,	8,	9,	859,	"R/W",	0,	0,	8ull,	8ull},
+	{"DSC"                         ,	17,	1,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"CPYTS"                       ,	18,	1,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTCRB"                       ,	19,	1,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"S_D_E"                       ,	20,	1,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	859,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	860,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	861,	"R/W",	0,	0,	0ull,	0ull},
+	{"VENDID"                      ,	0,	16,	862,	"R/W",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	862,	"R/W",	0,	0,	145ull,	145ull},
+	{"ISAE"                        ,	0,	1,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	863,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	863,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	863,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	863,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	863,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	863,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	863,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	863,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	863,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	863,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	863,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	863,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	863,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	863,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	863,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	863,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	863,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	863,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	864,	"R/W",	0,	0,	0ull,	0ull},
+	{"PI"                          ,	8,	8,	864,	"R/W",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	864,	"R/W",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	864,	"R/W",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	865,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	865,	"RO",	0,	0,	1ull,	1ull},
+	{"MFD"                         ,	23,	1,	865,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_31"               ,	0,	32,	866,	"RO",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	867,	"RO",	1,	1,	0,	0},
+	{"PBNUM"                       ,	0,	8,	868,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBNUM"                       ,	8,	8,	868,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUBBNUM"                     ,	16,	8,	868,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLT"                         ,	24,	8,	868,	"RO",	0,	0,	0ull,	0ull},
+	{"IO32A"                       ,	0,	1,	869,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	869,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_BASE"                    ,	4,	4,	869,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO32B"                       ,	8,	1,	869,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_11"               ,	9,	3,	869,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_LIMI"                    ,	12,	4,	869,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_20"              ,	16,	5,	869,	"RAZ",	1,	1,	0,	0},
+	{"M66"                         ,	21,	1,	869,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	869,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	869,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	869,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	869,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	869,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	869,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	869,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	869,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	869,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	870,	"RO",	1,	1,	0,	0},
+	{"MB_ADDR"                     ,	4,	12,	870,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_19"              ,	16,	4,	870,	"RO",	1,	1,	0,	0},
+	{"ML_ADDR"                     ,	20,	12,	870,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64A"                      ,	0,	1,	871,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	871,	"RO",	1,	1,	0,	0},
+	{"LMEM_BASE"                   ,	4,	12,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64B"                      ,	16,	1,	871,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_17_19"              ,	17,	3,	871,	"RO",	1,	1,	0,	0},
+	{"LMEM_LIMIT"                  ,	20,	12,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_BASE"                   ,	0,	32,	872,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_LIMIT"                  ,	0,	32,	873,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_BASE"                    ,	0,	16,	874,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_LIMIT"                   ,	16,	16,	874,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP"                          ,	0,	8,	875,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	875,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	876,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	877,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	877,	"R/W",	0,	0,	1ull,	1ull},
+	{"PERE"                        ,	16,	1,	877,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	17,	1,	877,	"R/W",	0,	0,	0ull,	0ull},
+	{"ISAE"                        ,	18,	1,	877,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGAE"                        ,	19,	1,	877,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGA16D"                      ,	20,	1,	877,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAM"                         ,	21,	1,	877,	"RO",	0,	0,	0ull,	0ull},
+	{"SBRST"                       ,	22,	1,	877,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	23,	1,	877,	"RO",	0,	0,	0ull,	0ull},
+	{"PDT"                         ,	24,	1,	877,	"RO",	0,	0,	0ull,	0ull},
+	{"SDT"                         ,	25,	1,	877,	"RO",	0,	0,	0ull,	0ull},
+	{"DTS"                         ,	26,	1,	877,	"RO",	0,	0,	0ull,	0ull},
+	{"DTSEES"                      ,	27,	1,	877,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	877,	"RO",	1,	1,	0,	0},
+	{"PMCID"                       ,	0,	8,	878,	"RO",	0,	0,	1ull,	1ull},
+	{"NCP"                         ,	8,	8,	878,	"R/W",	0,	0,	80ull,	80ull},
+	{"PMSV"                        ,	16,	3,	878,	"R/W",	0,	0,	3ull,	3ull},
+	{"PME_CLOCK"                   ,	19,	1,	878,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	878,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	878,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	878,	"R/W",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	878,	"R/W",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	878,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	878,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	879,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	879,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	879,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	879,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	879,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	879,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	879,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	879,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	879,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	879,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	879,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	879,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	880,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	880,	"R/W",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	880,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	880,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	881,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	881,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	883,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	883,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	884,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	884,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	884,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	884,	"RO",	0,	0,	4ull,	4ull},
+	{"SI"                          ,	24,	1,	884,	"R/W",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	884,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	884,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	885,	"R/W",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	885,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	885,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	885,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL1AL"                       ,	9,	3,	885,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_14"              ,	12,	3,	885,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	885,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	885,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	885,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	885,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	885,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	886,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	886,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	886,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	886,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	886,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	886,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	886,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	886,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	886,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	886,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	886,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_15_15"              ,	15,	1,	886,	"RAZ",	1,	1,	0,	0},
+	{"CE_D"                        ,	16,	1,	886,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	886,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	886,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	886,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	886,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	886,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	886,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	887,	"R/W",	1,	1,	0,	0},
+	{"MLW"                         ,	4,	6,	887,	"R/W",	0,	0,	8ull,	8ull},
+	{"ASLPMS"                      ,	10,	2,	887,	"R/W",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	887,	"R/W",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	887,	"R/W",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	887,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	887,	"RO",	0,	0,	1ull,	1ull},
+	{"LBNC"                        ,	21,	1,	887,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_23"              ,	22,	2,	887,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	887,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	888,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	888,	"R/W",	0,	0,	1ull,	1ull},
+	{"LD"                          ,	4,	1,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"LBM_INT_ENB"                 ,	10,	1,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAB_INT_ENB"                 ,	11,	1,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	888,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	888,	"RO",	1,	1,	0,	0},
+	{"NLW"                         ,	20,	6,	888,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_26"              ,	26,	1,	888,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	888,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	888,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLLA"                        ,	29,	1,	888,	"RO",	0,	0,	0ull,	1ull},
+	{"LBM"                         ,	30,	1,	888,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LAB"                         ,	31,	1,	888,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ABP"                         ,	0,	1,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCP"                         ,	1,	1,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLSP"                       ,	2,	1,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIP"                         ,	3,	1,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	4,	1,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_S"                        ,	5,	1,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_C"                        ,	6,	1,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LV"                       ,	7,	8,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LS"                       ,	15,	2,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIP"                        ,	17,	1,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"NCCS"                        ,	18,	1,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS_NUM"                      ,	19,	13,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABP_EN"                      ,	0,	1,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	1,	1,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLS_EN"                     ,	2,	1,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"PD_EN"                       ,	3,	1,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCINT_EN"                    ,	4,	1,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"HPINT_EN"                    ,	5,	1,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIC"                         ,	6,	2,	890,	"R/W",	0,	0,	3ull,	3ull},
+	{"PIC"                         ,	8,	2,	890,	"R/W",	0,	0,	3ull,	3ull},
+	{"PCC"                         ,	10,	1,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIC"                        ,	11,	1,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLS_EN"                     ,	12,	1,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	890,	"RAZ",	1,	1,	0,	0},
+	{"ABP_D"                       ,	16,	1,	890,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PF_D"                        ,	17,	1,	890,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLS_C"                      ,	18,	1,	890,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PD_C"                        ,	19,	1,	890,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CCINT_D"                     ,	20,	1,	890,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLSS"                       ,	21,	1,	890,	"RO",	0,	0,	0ull,	0ull},
+	{"PDS"                         ,	22,	1,	890,	"RO",	0,	0,	1ull,	1ull},
+	{"EMIS"                        ,	23,	1,	890,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLS_C"                      ,	24,	1,	890,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	890,	"RAZ",	1,	1,	0,	0},
+	{"SECEE"                       ,	0,	1,	891,	"R/W",	0,	0,	0ull,	0ull},
+	{"SENFEE"                      ,	1,	1,	891,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEFEE"                       ,	2,	1,	891,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMEIE"                       ,	3,	1,	891,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRSSVE"                      ,	4,	1,	891,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_15"               ,	5,	11,	891,	"RAZ",	1,	1,	0,	0},
+	{"CRSSV"                       ,	16,	1,	891,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	891,	"RAZ",	1,	1,	0,	0},
+	{"PME_RID"                     ,	0,	16,	892,	"RO",	0,	0,	0ull,	0ull},
+	{"PME_STAT"                    ,	16,	1,	892,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PME_PEND"                    ,	17,	1,	892,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	892,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTRS"                        ,	0,	4,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"CTDS"                        ,	4,	1,	893,	"RO",	0,	0,	1ull,	1ull},
+	{"ARI"                         ,	5,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OPS"                    ,	6,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM32S"                     ,	7,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM64S"                     ,	8,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM128S"                    ,	9,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"NOROPRPR"                    ,	10,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	893,	"RAZ",	1,	1,	0,	0},
+	{"TPH"                         ,	12,	2,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	893,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	894,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"ARI"                         ,	5,	1,	894,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP"                     ,	6,	1,	894,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP_EB"                  ,	7,	1,	894,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_RQ"                      ,	8,	1,	894,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_CP"                      ,	9,	1,	894,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_31"              ,	10,	22,	894,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	895,	"RAZ",	1,	1,	0,	0},
+	{"SLSV"                        ,	1,	7,	895,	"RO/WRSL",	1,	1,	0,	0},
+	{"CLS"                         ,	8,	1,	895,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	895,	"RAZ",	1,	1,	0,	0},
+	{"TLS"                         ,	0,	4,	896,	"R/W",	1,	1,	0,	0},
+	{"EC"                          ,	4,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"HASD"                        ,	5,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDE"                         ,	6,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"TM"                          ,	7,	3,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMC"                         ,	10,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSOS"                        ,	11,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDE"                         ,	12,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	896,	"RAZ",	1,	1,	0,	0},
+	{"CDL"                         ,	16,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	896,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	897,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	898,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	899,	"RO",	0,	0,	1ull,	1ull},
+	{"CV"                          ,	16,	4,	899,	"RO",	0,	0,	2ull,	2ull},
+	{"NCO"                         ,	20,	12,	899,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	900,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	900,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	900,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	900,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	900,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	900,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	900,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	900,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	900,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	900,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	900,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	900,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	900,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	900,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	901,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	901,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	901,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	901,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	902,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	902,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	902,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	902,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	902,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	902,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	902,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	902,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	903,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	903,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	903,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	903,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	903,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	903,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	903,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	903,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	903,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	904,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	904,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	904,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	904,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	905,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	905,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	905,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	905,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	906,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	907,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	908,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	909,	"RO",	0,	0,	0ull,	0ull},
+	{"CERE"                        ,	0,	1,	910,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFERE"                       ,	1,	1,	910,	"R/W",	0,	0,	0ull,	0ull},
+	{"FERE"                        ,	2,	1,	910,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	910,	"RAZ",	1,	1,	0,	0},
+	{"ECR"                         ,	0,	1,	911,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_ECR"                   ,	1,	1,	911,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EFNFR"                       ,	2,	1,	911,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_EFNFR"                 ,	3,	1,	911,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FUF"                         ,	4,	1,	911,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFEMR"                       ,	5,	1,	911,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEMR"                        ,	6,	1,	911,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_26"               ,	7,	20,	911,	"RAZ",	1,	1,	0,	0},
+	{"AEIMN"                       ,	27,	5,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECSI"                        ,	0,	16,	912,	"RO",	0,	0,	0ull,	0ull},
+	{"EFNFSI"                      ,	16,	16,	912,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	913,	"R/W",	0,	1,	4143ull,	0},
+	{"RTL"                         ,	16,	16,	913,	"R/W",	0,	1,	12429ull,	0},
+	{"OMR"                         ,	0,	32,	914,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	915,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_8_14"               ,	8,	7,	915,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	915,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	915,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	915,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	915,	"RO",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	916,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	916,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	916,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	916,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	916,	"R/W",	0,	0,	3ull,	3ull},
+	{"EASPML1"                     ,	30,	1,	916,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	916,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	917,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	917,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	917,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	917,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	917,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	917,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	917,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	917,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	917,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	917,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_22_31"              ,	22,	10,	917,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	918,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	918,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	918,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	918,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	918,	"R/W",	0,	0,	0ull,	0ull},
+	{"NTSS"                        ,	0,	4,	919,	"R/W",	0,	0,	10ull,	10ull},
+	{"RESERVED_4_7"                ,	4,	4,	919,	"RO",	1,	1,	0,	0},
+	{"NSKPS"                       ,	8,	3,	919,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_11_13"              ,	11,	3,	919,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	919,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	919,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	919,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	919,	"RO",	1,	1,	0,	0},
+	{"SKPIV"                       ,	0,	11,	920,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	920,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	920,	"R/W",	0,	0,	1ull,	1ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	921,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	921,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	921,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	922,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	923,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	924,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	924,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	924,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	925,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	925,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	925,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	926,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	926,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	926,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	927,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	927,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	927,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	927,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	928,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	928,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	928,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	928,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	929,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	929,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	929,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	929,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	930,	"R/W",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	930,	"R/W",	0,	0,	96ull,	96ull},
+	{"RESERVED_20_20"              ,	20,	1,	930,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	930,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	930,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	930,	"R/W",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	930,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	931,	"R/W",	0,	0,	32ull,	32ull},
+	{"HEADER_CREDITS"              ,	12,	8,	931,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_20"              ,	20,	1,	931,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	931,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	931,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	932,	"R/W",	0,	0,	256ull,	256ull},
+	{"HEADER_CREDITS"              ,	12,	8,	932,	"R/W",	0,	0,	127ull,	127ull},
+	{"RESERVED_20_20"              ,	20,	1,	932,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	932,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	932,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	933,	"R/W",	0,	0,	392ull,	392ull},
+	{"RESERVED_14_15"              ,	14,	2,	933,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	933,	"R/W",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	933,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	934,	"R/W",	0,	0,	136ull,	136ull},
+	{"RESERVED_14_15"              ,	14,	2,	934,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	934,	"R/W",	0,	0,	38ull,	38ull},
+	{"RESERVED_26_31"              ,	26,	6,	934,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	935,	"R/W",	0,	0,	679ull,	679ull},
+	{"RESERVED_14_15"              ,	14,	2,	935,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	935,	"R/W",	0,	0,	133ull,	133ull},
+	{"RESERVED_26_31"              ,	26,	6,	935,	"RAZ",	1,	1,	0,	0},
+	{"N_FTS"                       ,	0,	8,	936,	"R/W",	0,	0,	128ull,	128ull},
+	{"LE"                          ,	8,	9,	936,	"R/W",	0,	0,	8ull,	8ull},
+	{"DSC"                         ,	17,	1,	936,	"R/W",	0,	0,	0ull,	0ull},
+	{"CPYTS"                       ,	18,	1,	936,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTCRB"                       ,	19,	1,	936,	"R/W",	0,	0,	0ull,	0ull},
+	{"S_D_E"                       ,	20,	1,	936,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	936,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	937,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	938,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	939,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	939,	"R/W",	0,	0,	1ull,	1ull},
+	{"HFD"                         ,	6,	1,	939,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAUSE"                       ,	7,	2,	939,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	939,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	939,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	939,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NP"                          ,	15,	1,	939,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	939,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_11"               ,	0,	12,	940,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_THD"                    ,	12,	1,	940,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_TFD"                    ,	13,	1,	940,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_XHD"                    ,	14,	1,	940,	"RO",	0,	0,	1ull,	1ull},
+	{"THOU_XFD"                    ,	15,	1,	940,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	940,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	941,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	941,	"RO",	0,	0,	0ull,	0ull},
+	{"HFD"                         ,	6,	1,	941,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	7,	2,	941,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	941,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	941,	"RO",	0,	0,	0ull,	0ull},
+	{"ACK"                         ,	14,	1,	941,	"RO",	0,	1,	0ull,	0},
+	{"NP"                          ,	15,	1,	941,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	941,	"RAZ",	1,	1,	0,	0},
+	{"LINK_OK"                     ,	0,	1,	942,	"RO",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	1,	1,	942,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	2,	1,	942,	"RO",	0,	0,	0ull,	1ull},
+	{"SPD"                         ,	3,	2,	942,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	5,	2,	942,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	942,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD_EN"                   ,	0,	1,	943,	"R/W",	0,	0,	0ull,	1ull},
+	{"XMIT_EN"                     ,	1,	1,	943,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_ERR_EN"                   ,	2,	1,	943,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFU_EN"                   ,	3,	1,	943,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFO_EN"                   ,	4,	1,	943,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXBAD_EN"                    ,	5,	1,	943,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXERR_EN"                    ,	6,	1,	943,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	7,	1,	943,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXLOCK_EN"                   ,	8,	1,	943,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_BAD_EN"                   ,	9,	1,	943,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNC_BAD_EN"                 ,	10,	1,	943,	"R/W",	0,	0,	0ull,	1ull},
+	{"DUP"                         ,	11,	1,	943,	"R/W",	0,	0,	0ull,	1ull},
+	{"DBG_SYNC_EN"                 ,	12,	1,	943,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	943,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD"                      ,	0,	1,	944,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	1,	1,	944,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_ERR"                      ,	2,	1,	944,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFU"                      ,	3,	1,	944,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFO"                      ,	4,	1,	944,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXBAD"                       ,	5,	1,	944,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXERR"                       ,	6,	1,	944,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	7,	1,	944,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXLOCK"                      ,	8,	1,	944,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	9,	1,	944,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	10,	1,	944,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	11,	1,	944,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBG_SYNC"                    ,	12,	1,	944,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	944,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	16,	945,	"R/W",	0,	1,	1094ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	945,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	946,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	946,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	946,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	946,	"RAZ",	1,	1,	0,	0},
+	{"SAMP_PT"                     ,	0,	7,	947,	"R/W",	0,	1,	1ull,	0},
+	{"AN_OVRD"                     ,	7,	1,	947,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE"                        ,	8,	1,	947,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAC_PHY"                     ,	9,	1,	947,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK2"                    ,	10,	1,	947,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMXENO"                      ,	11,	1,	947,	"R/W",	0,	0,	0ull,	0ull},
+	{"SGMII"                       ,	12,	1,	947,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	947,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	948,	"RAZ",	1,	1,	0,	0},
+	{"UNI"                         ,	5,	1,	948,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDMSB"                      ,	6,	1,	948,	"R/W",	0,	0,	1ull,	1ull},
+	{"COLTST"                      ,	7,	1,	948,	"R/W",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	8,	1,	948,	"R/W",	0,	0,	1ull,	1ull},
+	{"RST_AN"                      ,	9,	1,	948,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	948,	"RAZ",	1,	1,	0,	0},
+	{"PWR_DN"                      ,	11,	1,	948,	"R/W",	0,	0,	1ull,	0ull},
+	{"AN_EN"                       ,	12,	1,	948,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDLSB"                      ,	13,	1,	948,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK1"                    ,	14,	1,	948,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	948,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	948,	"RAZ",	1,	1,	0,	0},
+	{"EXTND"                       ,	0,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	949,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LNK_ST"                      ,	2,	1,	949,	"RO",	0,	0,	0ull,	1ull},
+	{"AN_ABIL"                     ,	3,	1,	949,	"RO",	0,	0,	1ull,	1ull},
+	{"RM_FLT"                      ,	4,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	5,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"PRB_SUP"                     ,	6,	1,	949,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_7"                ,	7,	1,	949,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EXT_ST"                      ,	8,	1,	949,	"RO",	0,	0,	1ull,	1ull},
+	{"HUN_T2HD"                    ,	9,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T2FD"                    ,	10,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_HD"                      ,	11,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_FD"                      ,	12,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XHD"                     ,	13,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XFD"                     ,	14,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T4"                      ,	15,	1,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	949,	"RAZ",	1,	1,	0,	0},
+	{"AN_ST"                       ,	0,	4,	950,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	4,	1,	950,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	5,	4,	950,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	9,	1,	950,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_ST"                       ,	10,	5,	950,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_BAD"                      ,	15,	1,	950,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	950,	"RAZ",	1,	1,	0,	0},
+	{"BIT_LOCK"                    ,	0,	1,	951,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	1,	1,	951,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	951,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	952,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	952,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	952,	"R/W",	0,	0,	2ull,	2ull},
+	{"DUP"                         ,	12,	1,	952,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_13"              ,	13,	1,	952,	"RAZ",	0,	1,	0ull,	0},
+	{"ACK"                         ,	14,	1,	952,	"RO",	0,	0,	0ull,	0ull},
+	{"LINK"                        ,	15,	1,	952,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	952,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	953,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	953,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	953,	"RO",	0,	0,	0ull,	2ull},
+	{"DUP"                         ,	12,	1,	953,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_14"              ,	13,	2,	953,	"RAZ",	0,	1,	0ull,	0},
+	{"LINK"                        ,	15,	1,	953,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	953,	"RAZ",	1,	1,	0,	0},
+	{"ORD_ST"                      ,	0,	4,	954,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_BAD"                      ,	4,	1,	954,	"RO",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	5,	2,	954,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	954,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	955,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	955,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTORXPL"                    ,	2,	1,	955,	"RO",	0,	0,	0ull,	0ull},
+	{"RXOVRD"                      ,	3,	1,	955,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	955,	"RAZ",	1,	1,	0,	0},
+	{"L0SYNC"                      ,	0,	1,	956,	"RO",	0,	0,	0ull,	1ull},
+	{"L1SYNC"                      ,	1,	1,	956,	"RO",	0,	0,	0ull,	1ull},
+	{"L2SYNC"                      ,	2,	1,	956,	"RO",	0,	0,	0ull,	1ull},
+	{"L3SYNC"                      ,	3,	1,	956,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_10"               ,	4,	7,	956,	"RAZ",	1,	1,	0,	0},
+	{"PATTST"                      ,	11,	1,	956,	"RO",	0,	0,	0ull,	0ull},
+	{"ALIGND"                      ,	12,	1,	956,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_63"              ,	13,	51,	956,	"RAZ",	1,	1,	0,	0},
+	{"BIST_STATUS"                 ,	0,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	957,	"RAZ",	1,	1,	0,	0},
+	{"BITLCK0"                     ,	0,	1,	958,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK1"                     ,	1,	1,	958,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK2"                     ,	2,	1,	958,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK3"                     ,	3,	1,	958,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	958,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	959,	"RAZ",	1,	1,	0,	0},
+	{"SPD"                         ,	2,	4,	959,	"RO",	0,	0,	0ull,	0ull},
+	{"SPDSEL0"                     ,	6,	1,	959,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_10"               ,	7,	4,	959,	"RAZ",	1,	1,	0,	0},
+	{"LO_PWR"                      ,	11,	1,	959,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_12_12"              ,	12,	1,	959,	"RAZ",	1,	1,	0,	0},
+	{"SPDSEL1"                     ,	13,	1,	959,	"RO",	0,	0,	1ull,	1ull},
+	{"LOOPBCK1"                    ,	14,	1,	959,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	959,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	959,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	2,	960,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	960,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT_EN"                    ,	0,	1,	961,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	1,	1,	961,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXSYNBAD_EN"                 ,	2,	1,	961,	"R/W",	0,	0,	0ull,	1ull},
+	{"BITLCKLS_EN"                 ,	3,	1,	961,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNLOS_EN"                   ,	4,	1,	961,	"R/W",	0,	0,	0ull,	1ull},
+	{"ALGNLOS_EN"                  ,	5,	1,	961,	"R/W",	0,	0,	0ull,	1ull},
+	{"DBG_SYNC_EN"                 ,	6,	1,	961,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	961,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT"                       ,	0,	1,	962,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	1,	1,	962,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXSYNBAD"                    ,	2,	1,	962,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BITLCKLS"                    ,	3,	1,	962,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNLOS"                      ,	4,	1,	962,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALGNLOS"                     ,	5,	1,	962,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBG_SYNC"                    ,	6,	1,	962,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	962,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	963,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	963,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	963,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DROP_LN"                     ,	4,	2,	963,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENC_MODE"                    ,	6,	1,	963,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	963,	"RAZ",	1,	1,	0,	0},
+	{"GMXENO"                      ,	0,	1,	964,	"R/W",	0,	0,	0ull,	0ull},
+	{"XAUI"                        ,	1,	1,	964,	"RO",	1,	1,	0,	0},
+	{"RX_SWAP"                     ,	2,	1,	964,	"R/W",	0,	1,	0ull,	0},
+	{"TX_SWAP"                     ,	3,	1,	964,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	964,	"RAZ",	1,	1,	0,	0},
+	{"SYNC0ST"                     ,	0,	4,	965,	"RO",	0,	1,	0ull,	0},
+	{"SYNC1ST"                     ,	4,	4,	965,	"RO",	0,	1,	0ull,	0},
+	{"SYNC2ST"                     ,	8,	4,	965,	"RO",	0,	1,	0ull,	0},
+	{"SYNC3ST"                     ,	12,	4,	965,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	965,	"RAZ",	1,	1,	0,	0},
+	{"TENGB"                       ,	0,	1,	966,	"RO",	0,	0,	1ull,	1ull},
+	{"TENPASST"                    ,	1,	1,	966,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	966,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	967,	"RAZ",	1,	1,	0,	0},
+	{"LPABLE"                      ,	1,	1,	967,	"RO",	0,	0,	1ull,	1ull},
+	{"RCV_LNK"                     ,	2,	1,	967,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_6"                ,	3,	4,	967,	"RAZ",	1,	1,	0,	0},
+	{"FLT"                         ,	7,	1,	967,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	967,	"RAZ",	1,	1,	0,	0},
+	{"TENGB_R"                     ,	0,	1,	968,	"RO",	0,	0,	0ull,	0ull},
+	{"TENGB_X"                     ,	1,	1,	968,	"RO",	0,	0,	1ull,	1ull},
+	{"TENGB_W"                     ,	2,	1,	968,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_9"                ,	3,	7,	968,	"RAZ",	1,	1,	0,	0},
+	{"RCVFLT"                      ,	10,	1,	968,	"RC",	0,	0,	0ull,	0ull},
+	{"XMTFLT"                      ,	11,	1,	968,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_13"              ,	12,	2,	968,	"RAZ",	1,	1,	0,	0},
+	{"DEV"                         ,	14,	2,	968,	"RO",	0,	0,	2ull,	2ull},
+	{"RESERVED_16_63"              ,	16,	48,	968,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	969,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	969,	"R/W",	0,	0,	0ull,	0ull},
+	{"XOR_TXPLRT"                  ,	2,	4,	969,	"R/W",	0,	0,	0ull,	0ull},
+	{"XOR_RXPLRT"                  ,	6,	4,	969,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	969,	"RAZ",	1,	1,	0,	0},
+	{"TX_ST"                       ,	0,	3,	970,	"RO",	0,	1,	0ull,	0},
+	{"RX_ST"                       ,	3,	2,	970,	"RO",	0,	1,	0ull,	0},
+	{"ALGN_ST"                     ,	5,	3,	970,	"RO",	0,	1,	0ull,	0},
+	{"RXBAD"                       ,	8,	1,	970,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN0BAD"                     ,	9,	1,	970,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN1BAD"                     ,	10,	1,	970,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN2BAD"                     ,	11,	1,	970,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN3BAD"                     ,	12,	1,	970,	"RO",	0,	0,	0ull,	0ull},
+	{"TERM_ERR"                    ,	13,	1,	970,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	970,	"RAZ",	1,	1,	0,	0},
+	{"ADDR_V"                      ,	0,	1,	971,	"R/W",	0,	1,	0ull,	0},
+	{"END_SWP"                     ,	1,	2,	971,	"R/W",	0,	1,	0ull,	0},
+	{"CA"                          ,	3,	1,	971,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR_IDX"                    ,	4,	16,	971,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	971,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	972,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	3,	35,	972,	"R/W",	0,	0,	34359738367ull,	34359738367ull},
+	{"RESERVED_38_63"              ,	38,	26,	972,	"RAZ",	1,	1,	0,	0},
+	{"BAR2_CAX"                    ,	0,	1,	973,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	1,	2,	973,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	3,	1,	973,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR1_SIZ"                    ,	4,	3,	973,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_63"               ,	7,	57,	973,	"RAZ",	1,	1,	0,	0},
+	{"SOT"                         ,	0,	1,	974,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR0"                      ,	1,	1,	974,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR1"                      ,	2,	1,	974,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA3"                     ,	3,	1,	974,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA2"                     ,	4,	1,	974,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA1"                     ,	5,	1,	974,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA0"                     ,	6,	1,	974,	"RO",	0,	0,	0ull,	0ull},
+	{"RETRY"                       ,	7,	1,	974,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	974,	"RAZ",	1,	1,	0,	0},
+	{"PPF"                         ,	0,	1,	975,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TC0"                     ,	1,	1,	975,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TCF1"                    ,	2,	1,	975,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TNF"                     ,	3,	1,	975,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF0"                    ,	4,	1,	975,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF1"                    ,	5,	1,	975,	"RO",	0,	0,	0ull,	0ull},
+	{"PEAI_P2E"                    ,	6,	1,	975,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_P"                       ,	7,	1,	975,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_N"                       ,	8,	1,	975,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_CPL"                     ,	9,	1,	975,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	975,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	32,	976,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	976,	"R/W",	0,	1,	0ull,	0},
+	{"ADDR"                        ,	0,	32,	977,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	977,	"R/W",	0,	1,	0ull,	0},
+	{"TAG"                         ,	0,	32,	978,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	978,	"RAZ",	1,	1,	0,	0},
+	{"INV_LCRC"                    ,	0,	1,	979,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_ECRC"                    ,	1,	1,	979,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAST_LM"                     ,	2,	1,	979,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_CTLP"                     ,	3,	1,	979,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_ENB"                     ,	4,	1,	979,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLY_ONE"                     ,	5,	1,	979,	"R/W",	0,	0,	0ull,	0ull},
+	{"NF_ECRC"                     ,	6,	1,	979,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_8"                ,	7,	2,	979,	"R/W",	0,	0,	0ull,	0ull},
+	{"OB_P_CMD"                    ,	9,	1,	979,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XPME"                     ,	10,	1,	979,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XTOFF"                    ,	11,	1,	979,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	979,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CFG_RTRY"                    ,	16,	16,	979,	"R/W",	0,	0,	0ull,	32ull},
+	{"RESERVED_32_33"              ,	32,	2,	979,	"RAZ",	1,	1,	0,	0},
+	{"PBUS"                        ,	34,	8,	979,	"RO",	1,	1,	0,	0},
+	{"DNUM"                        ,	42,	5,	979,	"RO",	1,	1,	0,	0},
+	{"AUTO_SD"                     ,	47,	1,	979,	"RO",	1,	1,	0,	0},
+	{"RESERVED_48_63"              ,	48,	16,	979,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	980,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	980,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	981,	"RAZ",	1,	1,	0,	0},
+	{"AUX_EN"                      ,	0,	1,	982,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_EN"                       ,	1,	1,	982,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_STAT"                     ,	2,	1,	982,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_DST"                      ,	3,	1,	982,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	982,	"RO",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	983,	"R/W",	0,	0,	0ull,	1ull},
+	{"SE"                          ,	1,	1,	983,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEI"                        ,	2,	1,	983,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEM"                        ,	3,	1,	983,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B1"                       ,	4,	1,	983,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B2"                       ,	5,	1,	983,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_BX"                       ,	6,	1,	983,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B1"                       ,	7,	1,	983,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B2"                       ,	8,	1,	983,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_BX"                       ,	9,	1,	983,	"R/W",	0,	0,	0ull,	1ull},
+	{"EXC"                         ,	10,	1,	983,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDLK"                        ,	11,	1,	983,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_ER"                      ,	12,	1,	983,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_DR"                      ,	13,	1,	983,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_14_63"              ,	14,	50,	983,	"RAZ",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	984,	"R/W",	0,	0,	0ull,	1ull},
+	{"SE"                          ,	1,	1,	984,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEI"                        ,	2,	1,	984,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEM"                        ,	3,	1,	984,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B1"                       ,	4,	1,	984,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B2"                       ,	5,	1,	984,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_BX"                       ,	6,	1,	984,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B1"                       ,	7,	1,	984,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B2"                       ,	8,	1,	984,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_BX"                       ,	9,	1,	984,	"R/W",	0,	0,	0ull,	1ull},
+	{"EXC"                         ,	10,	1,	984,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDLK"                        ,	11,	1,	984,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_ER"                      ,	12,	1,	984,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_DR"                      ,	13,	1,	984,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_14_63"              ,	14,	50,	984,	"RAZ",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"SE"                          ,	1,	1,	985,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PMEI"                        ,	2,	1,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEM"                        ,	3,	1,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"UP_B1"                       ,	4,	1,	985,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UP_B2"                       ,	5,	1,	985,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UP_BX"                       ,	6,	1,	985,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_B1"                       ,	7,	1,	985,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_B2"                       ,	8,	1,	985,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_BX"                       ,	9,	1,	985,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EXC"                         ,	10,	1,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"RDLK"                        ,	11,	1,	985,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS_ER"                      ,	12,	1,	985,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS_DR"                      ,	13,	1,	985,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	985,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_13"               ,	0,	14,	986,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	14,	50,	986,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_25"               ,	0,	26,	987,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	26,	38,	987,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_40"               ,	0,	41,	988,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	41,	23,	988,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_11"               ,	0,	12,	989,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	12,	52,	989,	"R/W",	0,	1,	4503599627370495ull,	0},
+	{"RESERVED_0_11"               ,	0,	12,	990,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	12,	52,	990,	"R/W",	0,	1,	4503599627370495ull,	0},
+	{"SLI_P"                       ,	0,	8,	991,	"R/W",	0,	0,	128ull,	128ull},
+	{"SLI_NP"                      ,	8,	8,	991,	"R/W",	0,	0,	16ull,	16ull},
+	{"SLI_CPL"                     ,	16,	8,	991,	"R/W",	0,	0,	128ull,	128ull},
+	{"PEM_P"                       ,	24,	8,	991,	"R/W",	0,	0,	128ull,	128ull},
+	{"PEM_NP"                      ,	32,	8,	991,	"R/W",	0,	0,	16ull,	16ull},
+	{"PEM_CPL"                     ,	40,	8,	991,	"R/W",	0,	0,	128ull,	128ull},
+	{"PEAI_PPF"                    ,	48,	8,	991,	"R/W",	0,	0,	128ull,	128ull},
+	{"RESERVED_56_63"              ,	56,	8,	991,	"RAZ",	1,	1,	0,	0},
+	{"LOWATER"                     ,	0,	5,	992,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_5_7"                ,	5,	3,	992,	"RAZ",	0,	1,	0ull,	0},
+	{"HIWATER"                     ,	8,	5,	992,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_13_62"              ,	13,	50,	992,	"RAZ",	0,	1,	0ull,	0},
+	{"BCKPRS"                      ,	63,	1,	992,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	20,	993,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	993,	"RAZ",	1,	1,	0,	0},
+	{"CLKEN"                       ,	0,	1,	994,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	994,	"RAZ",	0,	1,	0ull,	0},
+	{"DPRT"                        ,	0,	16,	995,	"R/W",	0,	0,	0ull,	0ull},
+	{"UDP"                         ,	16,	1,	995,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP"                         ,	17,	1,	995,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	995,	"RAZ",	1,	1,	0,	0},
+	{"MAP0"                        ,	0,	4,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP0"                        ,	0,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINLEN"                      ,	0,	16,	998,	"R/W",	0,	0,	64ull,	64ull},
+	{"MAXLEN"                      ,	16,	16,	998,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_32_63"              ,	32,	32,	998,	"RAZ",	1,	1,	0,	0},
+	{"NIP_SHF"                     ,	0,	3,	999,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	999,	"RAZ",	1,	1,	0,	0},
+	{"RAW_SHF"                     ,	8,	3,	999,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	999,	"RAZ",	1,	1,	0,	0},
+	{"MAX_L2"                      ,	16,	1,	999,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_UDP"                     ,	17,	1,	999,	"R/W",	0,	0,	1ull,	1ull},
+	{"TAG_SYN"                     ,	18,	1,	999,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	999,	"RAZ",	1,	1,	0,	0},
+	{"IP_CHK"                      ,	0,	1,	1000,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_MAL"                      ,	1,	1,	1000,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_HOP"                      ,	2,	1,	1000,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP4_OPTS"                    ,	3,	1,	1000,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP6_EEXT"                    ,	4,	2,	1000,	"R/W",	0,	0,	1ull,	3ull},
+	{"RESERVED_6_7"                ,	6,	2,	1000,	"RAZ",	1,	1,	0,	0},
+	{"L4_MAL"                      ,	8,	1,	1000,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_PRT"                      ,	9,	1,	1000,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_CHK"                      ,	10,	1,	1000,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_LEN"                      ,	11,	1,	1000,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCP_FLAG"                    ,	12,	1,	1000,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2_MAL"                      ,	13,	1,	1000,	"R/W",	0,	0,	1ull,	1ull},
+	{"VS_QOS"                      ,	14,	1,	1000,	"R/W",	0,	0,	0ull,	0ull},
+	{"VS_WQE"                      ,	15,	1,	1000,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNRS"                       ,	16,	1,	1000,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	1000,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_SID"                 ,	24,	1,	1000,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_SCMD"                ,	25,	1,	1000,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_TVID"                ,	26,	1,	1000,	"R/W",	0,	0,	0ull,	0ull},
+	{"IHMSK_DIS"                   ,	27,	1,	1000,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	1000,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	1001,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	1002,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	3,	1003,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	1003,	"RAZ",	1,	1,	0,	0},
+	{"VLAN2_QOS"                   ,	0,	3,	1004,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1004,	"RAZ",	1,	1,	0,	0},
+	{"HG2_QOS"                     ,	4,	3,	1004,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	1004,	"RAZ",	1,	1,	0,	0},
+	{"DIFF2_QOS"                   ,	8,	3,	1004,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	1004,	"RAZ",	1,	1,	0,	0},
+	{"VLAN2_BPID"                  ,	16,	6,	1004,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1004,	"RAZ",	1,	1,	0,	0},
+	{"HG2_BPID"                    ,	24,	6,	1004,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	1004,	"RAZ",	1,	1,	0,	0},
+	{"DIFF2_BPID"                  ,	32,	6,	1004,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	1004,	"RAZ",	1,	1,	0,	0},
+	{"VLAN2_PADD"                  ,	40,	8,	1004,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2_PADD"                    ,	48,	8,	1004,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIFF2_PADD"                  ,	56,	8,	1004,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKIP"                        ,	0,	7,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	1005,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	2,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_EN"                      ,	10,	1,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"HIGIG_EN"                    ,	11,	1,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRC_EN"                      ,	12,	1,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	1005,	"RAZ",	1,	1,	0,	0},
+	{"QOS_VLAN"                    ,	16,	1,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_DIFF"                    ,	17,	1,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VOD"                     ,	18,	1,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	1005,	"RAZ",	0,	0,	0ull,	0ull},
+	{"QOS_WAT"                     ,	20,	4,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS"                         ,	24,	3,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_QOS"                      ,	27,	1,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT"                     ,	28,	4,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"INST_HDR"                    ,	32,	1,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"DYN_RS"                      ,	33,	1,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_INC"                     ,	34,	2,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWDRP"                      ,	36,	1,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	1005,	"RAZ",	1,	1,	0,	0},
+	{"QOS_WAT_47"                  ,	40,	4,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT_47"                  ,	44,	4,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR_EN"                   ,	48,	1,	1005,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR_EN"                   ,	49,	1,	1005,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR_EN"                   ,	50,	1,	1005,	"R/W",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	51,	1,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	52,	1,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_CHK_SEL"                 ,	53,	1,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"IH_PRI"                      ,	54,	1,	1005,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	1005,	"RAZ",	1,	1,	0,	0},
+	{"BPID"                        ,	0,	6,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_15"               ,	6,	10,	1006,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	16,	8,	1006,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	1006,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	0,	4,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"NON_TAG_TYPE"                ,	4,	2,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_TAG_TYPE"                ,	6,	2,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_TAG_TYPE"                ,	8,	2,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP4_TAG_TYPE"               ,	10,	2,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP6_TAG_TYPE"               ,	12,	2,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SRC_FLAG"                ,	14,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SRC_FLAG"                ,	15,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DST_FLAG"                ,	16,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DST_FLAG"                ,	17,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_PCTL_FLAG"               ,	18,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_NXTH_FLAG"               ,	19,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SPRT_FLAG"               ,	20,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SPRT_FLAG"               ,	21,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DPRT_FLAG"               ,	22,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DPRT_FLAG"               ,	23,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_PRT_FLAG"                ,	24,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VLAN"                    ,	25,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VS"                      ,	26,	2,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_MODE"                    ,	28,	2,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG_MSKIP"                ,	30,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG"                      ,	31,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGMASK"                  ,	32,	4,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGBASE"                  ,	36,	4,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_MSB"                     ,	40,	2,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_43"              ,	42,	2,	1007,	"RAZ",	1,	1,	0,	0},
+	{"GRPTAGMASK_MSB"              ,	44,	2,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_47"              ,	46,	2,	1007,	"RAZ",	1,	1,	0,	0},
+	{"GRPTAGBASE_MSB"              ,	48,	2,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	1007,	"RAZ",	1,	1,	0,	0},
+	{"INC_HWCHK"                   ,	52,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORTADD_EN"                  ,	53,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	1007,	"RAZ",	1,	1,	0,	0},
+	{"MATCH_VALUE"                 ,	0,	16,	1008,	"R/W",	0,	0,	0ull,	0ull},
+	{"MATCH_TYPE"                  ,	16,	3,	1008,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	1008,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	20,	3,	1008,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	1008,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	24,	6,	1008,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	1008,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	32,	16,	1008,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1008,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	0,	56,	1009,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	1009,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	0,	1,	1010,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1010,	"RAZ",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	1011,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	1011,	"R/W",	0,	1,	0ull,	0},
+	{"MCAST"                       ,	0,	32,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"MCAST"                       ,	0,	32,	1013,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	1013,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	1014,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	1014,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	1015,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	1015,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	1016,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	1016,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	1018,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	1018,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	1019,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	1019,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	1020,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	1020,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	1022,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	1022,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	1023,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_7"                ,	1,	7,	1023,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	1,	1023,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	1023,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	1024,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	1024,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	1025,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	1025,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	1026,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1026,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT"                    ,	0,	64,	1027,	"R/W",	0,	0,	18446744073709551615ull,	18446744073709551615ull},
+	{"EN"                          ,	0,	8,	1028,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1028,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	1029,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1029,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	1030,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	1030,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1030,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	1031,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	1031,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	1031,	"RO",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	32,	1032,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1032,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	1033,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1033,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	1034,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	1034,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	1034,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	1034,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	1035,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	1035,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	1035,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	1035,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	1035,	"RO",	1,	0,	0,	0ull},
+	{"PTRS2"                       ,	0,	17,	1036,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	1036,	"RO",	1,	1,	0,	0},
+	{"PTRS1"                       ,	32,	17,	1036,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	1036,	"RO",	1,	1,	0,	0},
+	{"MOD"                         ,	0,	3,	1037,	"RO",	1,	0,	0,	0ull},
+	{"CNT"                         ,	3,	13,	1037,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	16,	1,	1037,	"RO",	1,	0,	0,	0ull},
+	{"LEN"                         ,	17,	1,	1037,	"RO",	1,	0,	0,	0ull},
+	{"SOP"                         ,	18,	1,	1037,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	19,	3,	1037,	"RO",	1,	0,	0,	0ull},
+	{"MAJ"                         ,	22,	1,	1037,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	1037,	"RO",	1,	1,	0,	0},
+	{"STATE"                       ,	0,	64,	1038,	"RO",	1,	1,	0,	0},
+	{"STATE"                       ,	0,	64,	1039,	"RO",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	1040,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	1040,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	1040,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	1040,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	1040,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	1041,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	3,	1042,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	3,	2,	1042,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	5,	1,	1042,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	6,	1,	1042,	"RO",	1,	0,	0,	0ull},
+	{"CHK_ONCE"                    ,	7,	1,	1042,	"RO",	1,	0,	0,	0ull},
+	{"INIT_DWRITE"                 ,	8,	1,	1042,	"RO",	1,	0,	0,	0ull},
+	{"DREAD_SOP"                   ,	9,	1,	1042,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	10,	2,	1042,	"RO",	1,	0,	0,	0ull},
+	{"CMND_OFF"                    ,	12,	6,	1042,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	18,	16,	1042,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	34,	6,	1042,	"RO",	1,	0,	0,	0ull},
+	{"CURR_OFF"                    ,	40,	16,	1042,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	56,	8,	1042,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	0,	8,	1043,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	8,	40,	1043,	"RO",	1,	0,	0,	0ull},
+	{"NXT_INFLT"                   ,	48,	6,	1043,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR_3"                     ,	54,	1,	1043,	"RO",	1,	0,	0,	0ull},
+	{"PTP"                         ,	55,	1,	1043,	"RO",	1,	0,	0,	0ull},
+	{"UID_2"                       ,	56,	1,	1043,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_57_63"              ,	57,	7,	1043,	"RO",	1,	1,	0,	0},
+	{"QID_BASE"                    ,	0,	8,	1044,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	8,	4,	1044,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFMAX"                  ,	12,	4,	1044,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	16,	5,	1044,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	21,	3,	1044,	"RO",	1,	0,	0,	0ull},
+	{"STATC"                       ,	24,	1,	1044,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	25,	1,	1044,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTED"                   ,	26,	1,	1044,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	27,	1,	1044,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	1044,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFTHS"                  ,	29,	4,	1044,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFRES"                  ,	33,	4,	1044,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	1044,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	7,	1045,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	7,	7,	1045,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	14,	33,	1045,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	47,	13,	1045,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	60,	1,	1045,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	61,	3,	1045,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	5,	1046,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	5,	1,	1046,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	6,	1,	1046,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	7,	1,	1046,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	8,	1,	1046,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_9_15"               ,	9,	7,	1046,	"RO",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	16,	20,	1046,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	36,	1,	1046,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	1046,	"RO",	1,	1,	0,	0},
+	{"PTRS3"                       ,	0,	17,	1047,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	1047,	"RO",	1,	1,	0,	0},
+	{"PTRS0"                       ,	32,	17,	1047,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	1047,	"RO",	1,	1,	0,	0},
+	{"IPID"                        ,	0,	7,	1048,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_7_7"                ,	7,	1,	1048,	"RAZ",	1,	1,	0,	0},
+	{"EID"                         ,	8,	5,	1048,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_13_15"              ,	13,	3,	1048,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	16,	5,	1048,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_21_23"              ,	21,	3,	1048,	"RAZ",	1,	1,	0,	0},
+	{"PIPE"                        ,	24,	7,	1048,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_31_49"              ,	31,	19,	1048,	"RAZ",	1,	1,	0,	0},
+	{"MIN_PKT"                     ,	50,	3,	1048,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	1048,	"R/W",	1,	1,	0,	0},
+	{"STATIC_P"                    ,	61,	1,	1048,	"R/W",	1,	0,	0,	0ull},
+	{"CRC"                         ,	62,	1,	1048,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_63_63"              ,	63,	1,	1048,	"R/W",	1,	0,	0,	0ull},
+	{"IPID"                        ,	0,	7,	1049,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_7_7"                ,	7,	1,	1049,	"RAZ",	1,	1,	0,	0},
+	{"EID"                         ,	8,	5,	1049,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_13_52"              ,	13,	40,	1049,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	1049,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_61_63"              ,	61,	3,	1049,	"RAZ",	1,	1,	0,	0},
+	{"QID"                         ,	0,	8,	1050,	"R/W",	1,	0,	0,	0ull},
+	{"IPID"                        ,	8,	7,	1050,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	1050,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	16,	5,	1050,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	21,	1,	1050,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	22,	31,	1050,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	1050,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	1050,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	1050,	"R/W",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	1050,	"R/W",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	8,	1051,	"R/W",	1,	0,	0,	0ull},
+	{"IPID"                        ,	8,	7,	1051,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_15_52"              ,	15,	38,	1051,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	1051,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	1051,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	7,	1052,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	1052,	"RAZ",	1,	1,	0,	0},
+	{"RATE_PKT"                    ,	8,	24,	1052,	"R/W",	1,	0,	0,	0ull},
+	{"RATE_WORD"                   ,	32,	19,	1052,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	1052,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	7,	1053,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	1053,	"RAZ",	1,	1,	0,	0},
+	{"RATE_LIM"                    ,	8,	24,	1053,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1053,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	5,	1054,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	1054,	"RAZ",	1,	1,	0,	0},
+	{"PACKET"                      ,	8,	6,	1054,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	1054,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	32,	15,	1054,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	1054,	"RAZ",	1,	1,	0,	0},
+	{"PIPE"                        ,	0,	7,	1055,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	1055,	"RAZ",	1,	1,	0,	0},
+	{"PACKET"                      ,	8,	6,	1055,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	1055,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	32,	15,	1055,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	1055,	"RAZ",	1,	1,	0,	0},
+	{"DAT_PTR"                     ,	0,	4,	1056,	"RO",	1,	0,	0,	0ull},
+	{"DAT_DAT"                     ,	4,	2,	1056,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CTL"                     ,	6,	2,	1056,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QSB"                     ,	8,	3,	1056,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QCB"                     ,	11,	2,	1056,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	13,	2,	1056,	"RO",	1,	0,	0,	0ull},
+	{"PRT_PSB"                     ,	15,	6,	1056,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_21_21"              ,	21,	1,	1056,	"RAZ",	1,	1,	0,	0},
+	{"PRT_PSB7"                    ,	22,	1,	1056,	"RO",	1,	0,	0,	0ull},
+	{"PRT_NXT"                     ,	23,	1,	1056,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CHK"                     ,	24,	3,	1056,	"RO",	1,	0,	0,	0ull},
+	{"OUT_WIF"                     ,	27,	1,	1056,	"RO",	1,	0,	0,	0ull},
+	{"OUT_STA"                     ,	28,	1,	1056,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CTL"                     ,	29,	2,	1056,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1056,	"RAZ",	1,	1,	0,	0},
+	{"OUT_DAT"                     ,	32,	1,	1056,	"RO",	1,	0,	0,	0ull},
+	{"IOB"                         ,	33,	1,	1056,	"RO",	1,	0,	0,	0ull},
+	{"CSR"                         ,	34,	1,	1056,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	1056,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	13,	1057,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	1057,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	1057,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	1057,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	64,	1058,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	1059,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	1060,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	1061,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	1062,	"RO",	0,	0,	0ull,	0ull},
+	{"ENGINE0"                     ,	0,	4,	1063,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE1"                     ,	4,	4,	1063,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE2"                     ,	8,	4,	1063,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE3"                     ,	12,	4,	1063,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE4"                     ,	16,	4,	1063,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE5"                     ,	20,	4,	1063,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE6"                     ,	24,	4,	1063,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE7"                     ,	28,	4,	1063,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE8"                     ,	32,	4,	1063,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE9"                     ,	36,	4,	1063,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE10"                    ,	40,	4,	1063,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE11"                    ,	44,	4,	1063,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE12"                    ,	48,	4,	1063,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE13"                    ,	52,	4,	1063,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE14"                    ,	56,	4,	1063,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE15"                    ,	60,	4,	1063,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE16"                    ,	0,	4,	1064,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE17"                    ,	4,	4,	1064,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE18"                    ,	8,	4,	1064,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE19"                    ,	12,	4,	1064,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_16_63"              ,	16,	48,	1064,	"RAZ",	1,	1,	0,	0},
+	{"ENGINE0"                     ,	0,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE1"                     ,	4,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE2"                     ,	8,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE3"                     ,	12,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE4"                     ,	16,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE5"                     ,	20,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE6"                     ,	24,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE7"                     ,	28,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE8"                     ,	32,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE9"                     ,	36,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE10"                    ,	40,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE11"                    ,	44,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE12"                    ,	48,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE13"                    ,	52,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE14"                    ,	56,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE15"                    ,	60,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
+	{"MASK"                        ,	0,	20,	1066,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1066,	"RAZ",	1,	1,	0,	0},
+	{"PARITY"                      ,	0,	1,	1067,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	1067,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	1067,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LOOPBACK"                    ,	3,	1,	1067,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1067,	"RAZ",	1,	1,	0,	0},
+	{"ENA_PKO"                     ,	0,	1,	1068,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	1068,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	1068,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	1068,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA_THROTTLE"                ,	4,	1,	1068,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIS_PERF0"                   ,	5,	1,	1068,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIS_PERF1"                   ,	6,	1,	1068,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	1068,	"RAZ",	1,	1,	0,	0},
+	{"PARITY"                      ,	0,	1,	1069,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	1069,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	1069,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBACK"                    ,	3,	1,	1069,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1069,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1070,	"RAZ",	1,	1,	0,	0},
+	{"BPID0"                       ,	4,	6,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	1070,	"RAZ",	1,	1,	0,	0},
+	{"BPID1"                       ,	11,	6,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_17"              ,	17,	1,	1070,	"RAZ",	1,	1,	0,	0},
+	{"BPID2"                       ,	18,	6,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_24"              ,	24,	1,	1070,	"RAZ",	1,	1,	0,	0},
+	{"BPID3"                       ,	25,	6,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1070,	"RAZ",	1,	1,	0,	0},
+	{"BPID4"                       ,	32,	6,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_38"              ,	38,	1,	1070,	"RAZ",	1,	1,	0,	0},
+	{"BPID5"                       ,	39,	6,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_45"              ,	45,	1,	1070,	"RAZ",	1,	1,	0,	0},
+	{"BPID6"                       ,	46,	6,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_52_52"              ,	52,	1,	1070,	"RAZ",	1,	1,	0,	0},
+	{"BPID7"                       ,	53,	6,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_59_63"              ,	59,	5,	1070,	"RAZ",	1,	1,	0,	0},
+	{"NUM_PORTS"                   ,	0,	4,	1071,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKIND0"                      ,	4,	6,	1071,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	1071,	"RAZ",	1,	1,	0,	0},
+	{"PKIND1"                      ,	11,	6,	1071,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_17"              ,	17,	1,	1071,	"RAZ",	1,	1,	0,	0},
+	{"PKIND2"                      ,	18,	6,	1071,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_24"              ,	24,	1,	1071,	"RAZ",	1,	1,	0,	0},
+	{"PKIND3"                      ,	25,	6,	1071,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1071,	"RAZ",	1,	1,	0,	0},
+	{"PKIND4"                      ,	32,	6,	1071,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_38"              ,	38,	1,	1071,	"RAZ",	1,	1,	0,	0},
+	{"PKIND5"                      ,	39,	6,	1071,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_45"              ,	45,	1,	1071,	"RAZ",	1,	1,	0,	0},
+	{"PKIND6"                      ,	46,	6,	1071,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_52_52"              ,	52,	1,	1071,	"RAZ",	1,	1,	0,	0},
+	{"PKIND7"                      ,	53,	6,	1071,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_59_63"              ,	59,	5,	1071,	"RAZ",	1,	1,	0,	0},
+	{"SIZE0"                       ,	0,	8,	1072,	"RO",	0,	0,	0ull,	0ull},
+	{"SIZE1"                       ,	8,	8,	1072,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE2"                       ,	16,	8,	1072,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE3"                       ,	24,	8,	1072,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE4"                       ,	32,	8,	1072,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE5"                       ,	40,	8,	1072,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE6"                       ,	48,	8,	1072,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE7"                       ,	56,	8,	1072,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIN_SIZE"                    ,	0,	16,	1073,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1073,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	1074,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1074,	"RAZ",	1,	1,	0,	0},
+	{"PREEMPTER"                   ,	0,	1,	1075,	"R/W",	0,	0,	0ull,	0ull},
+	{"PREEMPTEE"                   ,	1,	1,	1075,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1075,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	1076,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	1076,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1076,	"RAZ",	1,	1,	0,	0},
+	{"INT_MASK"                    ,	0,	32,	1077,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1077,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WQE_WORD"                    ,	0,	4,	1078,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_4_63"               ,	4,	60,	1078,	"RAZ",	1,	1,	0,	0},
+	{"IWORD"                       ,	0,	64,	1079,	"RO",	1,	1,	0,	0},
+	{"P_DAT"                       ,	0,	64,	1080,	"RO",	1,	1,	0,	0},
+	{"Q_DAT"                       ,	0,	64,	1081,	"RO",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	2,	1082,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	2,	2,	1082,	"RO",	1,	0,	0,	0ull},
+	{"NCB_OUB"                     ,	4,	1,	1082,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	5,	1,	1082,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1082,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	1083,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	33,	13,	1083,	"R/W",	0,	1,	0ull,	0},
+	{"POOL"                        ,	46,	3,	1083,	"R/W",	0,	1,	0ull,	0},
+	{"DWB"                         ,	49,	9,	1083,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	1083,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	1084,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STORE_LE"                    ,	1,	1,	1084,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_READ"                    ,	2,	4,	1084,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_6_63"               ,	6,	58,	1084,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	0,	5,	1085,	"RO",	1,	1,	0,	0},
+	{"COMMIT"                      ,	5,	1,	1085,	"RO",	1,	1,	0,	0},
+	{"OWORDPV"                     ,	6,	1,	1085,	"RO",	1,	1,	0,	0},
+	{"OWORDQV"                     ,	7,	1,	1085,	"RO",	1,	1,	0,	0},
+	{"IWIDX"                       ,	8,	6,	1085,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	1085,	"RO",	1,	1,	0,	0},
+	{"IRIDX"                       ,	16,	6,	1085,	"RO",	1,	1,	0,	0},
+	{"RESERVED_22_31"              ,	22,	10,	1085,	"RO",	1,	1,	0,	0},
+	{"LOOP"                        ,	32,	25,	1085,	"RO",	1,	1,	0,	0},
+	{"RESERVED_57_63"              ,	57,	7,	1085,	"RO",	1,	1,	0,	0},
+	{"CWORD"                       ,	0,	64,	1086,	"RO",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	1087,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	1087,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	1087,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	1088,	"RO",	1,	1,	0,	0},
+	{"SOD"                         ,	8,	1,	1088,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	9,	1,	1088,	"RO",	1,	1,	0,	0},
+	{"WC"                          ,	10,	1,	1088,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	11,	1,	1088,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	12,	1,	1088,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	1088,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	15,	1089,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	1089,	"RAZ",	1,	1,	0,	0},
+	{"OWORDP"                      ,	0,	64,	1090,	"RO",	1,	1,	0,	0},
+	{"OWORDQ"                      ,	0,	64,	1091,	"RO",	1,	1,	0,	0},
+	{"RWORD"                       ,	0,	64,	1092,	"RO",	1,	1,	0,	0},
+	{"N0CREDS"                     ,	0,	4,	1093,	"RO",	0,	0,	8ull,	0ull},
+	{"N1CREDS"                     ,	4,	4,	1093,	"RO",	0,	0,	8ull,	0ull},
+	{"POWCREDS"                    ,	8,	2,	1093,	"RO",	0,	0,	2ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	1093,	"RAZ",	1,	1,	0,	0},
+	{"FPACREDS"                    ,	12,	2,	1093,	"RO",	0,	0,	1ull,	0ull},
+	{"WCCREDS"                     ,	14,	2,	1093,	"RO",	0,	0,	0ull,	0ull},
+	{"NIWIDX0"                     ,	16,	4,	1093,	"RO",	1,	1,	0,	0},
+	{"NIRIDX0"                     ,	20,	4,	1093,	"RO",	1,	1,	0,	0},
+	{"NIWIDX1"                     ,	24,	4,	1093,	"RO",	1,	1,	0,	0},
+	{"NIRIDX1"                     ,	28,	4,	1093,	"RO",	1,	1,	0,	0},
+	{"NIRVAL6"                     ,	32,	5,	1093,	"RO",	1,	1,	0,	0},
+	{"NIRARB6"                     ,	37,	1,	1093,	"RO",	1,	1,	0,	0},
+	{"NIRQUE6"                     ,	38,	2,	1093,	"RO",	1,	1,	0,	0},
+	{"NIROPC6"                     ,	40,	3,	1093,	"RO",	1,	1,	0,	0},
+	{"NIRVAL7"                     ,	43,	5,	1093,	"RO",	1,	1,	0,	0},
+	{"NIRQUE7"                     ,	48,	2,	1093,	"RO",	1,	1,	0,	0},
+	{"NIROPC7"                     ,	50,	3,	1093,	"RO",	1,	1,	0,	0},
+	{"RESERVED_53_63"              ,	53,	11,	1093,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	1094,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	1094,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	56,	8,	1094,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	15,	1095,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	1095,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	1096,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	1096,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	1096,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	1097,	"RO",	1,	1,	0,	0},
+	{"MUL"                         ,	8,	8,	1097,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	16,	1,	1097,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	17,	1,	1097,	"RO",	1,	1,	0,	0},
+	{"INI"                         ,	18,	1,	1097,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	19,	1,	1097,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_63"              ,	20,	44,	1097,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1098,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1098,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1099,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1099,	"RAZ",	1,	1,	0,	0},
+	{"COEFFS"                      ,	0,	8,	1100,	"R/W",	0,	0,	29ull,	29ull},
+	{"RESERVED_8_63"               ,	8,	56,	1100,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	0,	16,	1101,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	16,	16,	1101,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1101,	"RAZ",	1,	1,	0,	0},
+	{"MEM"                         ,	0,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1102,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	1103,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	1103,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	1103,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	1103,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXP_ENT"                     ,	4,	1,	1103,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENT_SEL"                     ,	5,	4,	1103,	"R/W",	0,	0,	0ull,	0ull},
+	{"EER_VAL"                     ,	9,	1,	1103,	"RO",	0,	0,	0ull,	0ull},
+	{"EER_LCK"                     ,	10,	1,	1103,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	1103,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	1104,	"RO",	1,	1,	0,	0},
+	{"KEY"                         ,	0,	64,	1105,	"WO",	0,	0,	0ull,	0ull},
+	{"DAT"                         ,	0,	64,	1106,	"RO",	1,	1,	0,	0},
+	{"NCB_CMD"                     ,	0,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"MSI"                         ,	1,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI0_0"                      ,	2,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI0_1"                      ,	3,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI1_0"                      ,	4,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI1_1"                      ,	5,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_8"                ,	6,	3,	1107,	"RAZ",	1,	1,	0,	0},
+	{"P2N1_P1"                     ,	9,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_P0"                     ,	10,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_N"                      ,	11,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C1"                     ,	12,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C0"                     ,	13,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P1"                     ,	14,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P0"                     ,	15,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_N"                      ,	16,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C1"                     ,	17,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C0"                     ,	18,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_24"              ,	19,	6,	1107,	"RAZ",	1,	1,	0,	0},
+	{"CPL_P1"                      ,	25,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"CPL_P0"                      ,	26,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_O"                      ,	27,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_C"                      ,	28,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_O"                      ,	29,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_C"                      ,	30,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"NCB_REQ"                     ,	31,	1,	1107,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1107,	"RAZ",	1,	1,	0,	0},
+	{"WAIT_COM"                    ,	0,	1,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_4"                ,	1,	4,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTLP_RO"                     ,	5,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTLP_RO"                     ,	7,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTA_MAP"                    ,	8,	2,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTB_MAP"                    ,	10,	2,	1108,	"R/W",	0,	0,	1ull,	1ull},
+	{"INTC_MAP"                    ,	12,	2,	1108,	"R/W",	0,	0,	2ull,	2ull},
+	{"INTD_MAP"                    ,	14,	2,	1108,	"R/W",	0,	0,	3ull,	3ull},
+	{"WAITL_COM"                   ,	16,	1,	1108,	"R/W",	0,	1,	0ull,	0},
+	{"DIS_PORT"                    ,	17,	1,	1108,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTA"                        ,	18,	1,	1108,	"RO",	0,	0,	1ull,	1ull},
+	{"INTB"                        ,	19,	1,	1108,	"RO",	0,	0,	1ull,	1ull},
+	{"INTC"                        ,	20,	1,	1108,	"RO",	0,	0,	1ull,	1ull},
+	{"INTD"                        ,	21,	1,	1108,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	1108,	"RAZ",	1,	1,	0,	0},
+	{"CHIP_REV"                    ,	0,	8,	1109,	"RO",	1,	1,	0,	0},
+	{"P0_NTAGS"                    ,	8,	6,	1109,	"R/W",	0,	0,	32ull,	32ull},
+	{"P1_NTAGS"                    ,	14,	6,	1109,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_63"              ,	20,	44,	1109,	"RAZ",	1,	1,	0,	0},
+	{"P0_FCNT"                     ,	0,	6,	1110,	"RO",	0,	1,	0ull,	0},
+	{"P0_UCNT"                     ,	6,	16,	1110,	"RO",	0,	1,	0ull,	0},
+	{"P1_FCNT"                     ,	22,	6,	1110,	"RO",	0,	1,	0ull,	0},
+	{"P1_UCNT"                     ,	28,	16,	1110,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	1110,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	1111,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	1111,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	1111,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	32,	1112,	"R/W",	0,	1,	0ull,	0},
+	{"ADBG_SEL"                    ,	32,	1,	1112,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	1112,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1113,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1113,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1114,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	32,	1114,	"R/W",	0,	1,	0ull,	0},
+	{"TIM"                         ,	0,	32,	1115,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1115,	"RAZ",	1,	1,	0,	0},
+	{"RML_TO"                      ,	0,	1,	1116,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	1116,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	1116,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	1116,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	4,	1,	1116,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	5,	1,	1116,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	1116,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UP_WI"                    ,	9,	1,	1116,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_B0"                    ,	10,	1,	1116,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_WI"                    ,	11,	1,	1116,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_B0"                    ,	12,	1,	1116,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_WI"                    ,	13,	1,	1116,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_B0"                    ,	14,	1,	1116,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_WI"                    ,	15,	1,	1116,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT0"                    ,	16,	1,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO_INT1"                    ,	17,	1,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAFI"                       ,	32,	2,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	48,	1,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_59"              ,	58,	2,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIPE_ERR"                    ,	61,	1,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML_TO"                      ,	0,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	4,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	5,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UP_WI"                    ,	9,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_B0"                    ,	10,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_WI"                    ,	11,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_B0"                    ,	12,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_WI"                    ,	13,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_B0"                    ,	14,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_WI"                    ,	15,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT0"                    ,	16,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT1"                    ,	17,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC0_INT"                    ,	18,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC1_INT"                    ,	19,	1,	1117,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_31"              ,	20,	12,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAFI"                       ,	32,	2,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	48,	1,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_59"              ,	58,	2,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIPE_ERR"                    ,	61,	1,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML_TO"                      ,	0,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAR0_TO"                     ,	2,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB2BIG"                     ,	3,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT"                        ,	4,	1,	1118,	"RO",	0,	0,	0ull,	0ull},
+	{"PTIME"                       ,	5,	1,	1118,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UP_WI"                    ,	9,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UN_B0"                    ,	10,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UN_WI"                    ,	11,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UP_B0"                    ,	12,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UP_WI"                    ,	13,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UN_B0"                    ,	14,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UN_WI"                    ,	15,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO_INT0"                    ,	16,	1,	1118,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO_INT1"                    ,	17,	1,	1118,	"RO",	0,	0,	0ull,	0ull},
+	{"MAC0_INT"                    ,	18,	1,	1118,	"RO",	0,	0,	0ull,	0ull},
+	{"MAC1_INT"                    ,	19,	1,	1118,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	1118,	"RAZ",	1,	1,	0,	0},
+	{"DMAFI"                       ,	32,	2,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	1118,	"RO",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	1118,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	1118,	"RAZ",	1,	1,	0,	0},
+	{"PIDBOF"                      ,	48,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	1118,	"RAZ",	1,	1,	0,	0},
+	{"PGL_ERR"                     ,	52,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_59"              ,	58,	2,	1118,	"RAZ",	1,	1,	0,	0},
+	{"ILL_PAD"                     ,	60,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIPE_ERR"                    ,	61,	1,	1118,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	1118,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	1119,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	1120,	"RO",	0,	1,	0ull,	0},
+	{"P0_PCNT"                     ,	0,	8,	1121,	"R/W",	0,	0,	128ull,	128ull},
+	{"P0_NCNT"                     ,	8,	8,	1121,	"R/W",	0,	0,	16ull,	16ull},
+	{"P0_CCNT"                     ,	16,	8,	1121,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_PCNT"                     ,	24,	8,	1121,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_NCNT"                     ,	32,	8,	1121,	"R/W",	0,	0,	16ull,	16ull},
+	{"P1_CCNT"                     ,	40,	8,	1121,	"R/W",	0,	0,	128ull,	128ull},
+	{"P0_P_D"                      ,	48,	1,	1121,	"R/W",	0,	0,	1ull,	1ull},
+	{"P0_N_D"                      ,	49,	1,	1121,	"R/W",	0,	0,	1ull,	1ull},
+	{"P0_C_D"                      ,	50,	1,	1121,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_P_D"                      ,	51,	1,	1121,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_N_D"                      ,	52,	1,	1121,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_C_D"                      ,	53,	1,	1121,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_54_63"              ,	54,	10,	1121,	"RAZ",	1,	1,	0,	0},
+	{"NUM"                         ,	0,	8,	1122,	"RO",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	1122,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	10,	1123,	"R/W",	0,	0,	0ull,	50ull},
+	{"MAX_WORD"                    ,	10,	4,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	1123,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"BA"                          ,	2,	28,	1124,	"R/W",	0,	1,	0ull,	0},
+	{"RTYPE"                       ,	30,	2,	1124,	"R/W",	0,	1,	0ull,	0},
+	{"WTYPE"                       ,	32,	2,	1124,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	34,	2,	1124,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	36,	2,	1124,	"R/W",	0,	1,	0ull,	0},
+	{"NMERGE"                      ,	38,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORT"                        ,	39,	3,	1124,	"R/W",	0,	1,	0ull,	0},
+	{"ZERO"                        ,	42,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	1124,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	64,	1125,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	1126,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	1127,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	1128,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"INTR"                        ,	0,	64,	1129,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	1130,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	1131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	1132,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	1133,	"R/W",	0,	1,	0ull,	0},
+	{"RD_INT"                      ,	8,	8,	1133,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	1133,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	64,	1134,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	1135,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	1136,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	1140,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	1141,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	1142,	"R/W",	0,	1,	0ull,	0},
+	{"CIU_INT"                     ,	8,	8,	1142,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	1142,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	8,	1143,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	1143,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1144,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	8,	8,	1144,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	1144,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	1145,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	16,	8,	1145,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	1145,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	1146,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	24,	8,	1146,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1146,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1147,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	32,	22,	1147,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	1147,	"RO",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	1148,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	61,	1148,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	1149,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	1150,	"R/W",	0,	1,	0ull,	0},
+	{"FCNT"                        ,	32,	5,	1150,	"RO",	0,	1,	0ull,	0},
+	{"WRP"                         ,	37,	9,	1150,	"RO",	0,	1,	0ull,	0},
+	{"RRP"                         ,	46,	9,	1150,	"RO",	0,	1,	0ull,	0},
+	{"MAX"                         ,	55,	9,	1150,	"RO",	0,	1,	16ull,	0},
+	{"NTAG"                        ,	0,	1,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"NTT"                         ,	1,	1,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"NGRP"                        ,	2,	1,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"NQOS"                        ,	3,	1,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_13"              ,	13,	1,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_20"              ,	16,	5,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"RNTAG"                       ,	22,	1,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"RNTT"                        ,	23,	1,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"RNGRP"                       ,	24,	1,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"RNQOS"                       ,	25,	1,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_27"              ,	26,	2,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_35_35"              ,	35,	1,	1151,	"RAZ",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_42"              ,	38,	5,	1151,	"RAZ",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	1151,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	16,	1152,	"R/W",	0,	1,	0ull,	0},
+	{"ISIZE"                       ,	16,	7,	1152,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	1152,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1153,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	4,	60,	1153,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	1154,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	1154,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	1155,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1155,	"RO",	0,	1,	0ull,	0},
+	{"PORT"                        ,	0,	32,	1156,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1156,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	1157,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1157,	"RAZ",	1,	1,	0,	0},
+	{"PKT_BP"                      ,	0,	4,	1158,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RING_EN"                     ,	4,	1,	1158,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	1158,	"RAZ",	1,	1,	0,	0},
+	{"ES"                          ,	0,	64,	1159,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	1160,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1160,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	1161,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1161,	"RAZ",	1,	1,	0,	0},
+	{"DPTR"                        ,	0,	32,	1162,	"R/W",	0,	0,	0ull,	4294967295ull},
+	{"RESERVED_32_63"              ,	32,	32,	1162,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1163,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1163,	"RO",	0,	1,	0ull,	0},
+	{"RD_CNT"                      ,	0,	32,	1164,	"RO",	0,	1,	0ull,	0},
+	{"WR_CNT"                      ,	32,	32,	1164,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	0,	64,	1165,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	0,	1,	1166,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	1,	2,	1166,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	3,	1,	1166,	"R/W",	0,	1,	0ull,	0},
+	{"USE_CSR"                     ,	4,	1,	1166,	"R/W",	0,	0,	0ull,	1ull},
+	{"D_ROR"                       ,	5,	1,	1166,	"R/W",	0,	1,	0ull,	0},
+	{"D_ESR"                       ,	6,	2,	1166,	"R/W",	0,	1,	0ull,	0},
+	{"D_NSR"                       ,	8,	1,	1166,	"R/W",	0,	1,	0ull,	0},
+	{"PBP_DHI"                     ,	9,	13,	1166,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_RR"                      ,	22,	1,	1166,	"R/W",	0,	0,	0ull,	1ull},
+	{"PIN_RST"                     ,	23,	1,	1166,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_39"              ,	24,	16,	1166,	"RAZ",	1,	1,	0,	0},
+	{"PRC_IDLE"                    ,	40,	1,	1166,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_41_47"              ,	41,	7,	1166,	"RAZ",	1,	1,	0,	0},
+	{"GII_RDS"                     ,	48,	7,	1166,	"RO",	0,	1,	0ull,	0},
+	{"GII_ERST"                    ,	55,	1,	1166,	"RO",	0,	1,	0ull,	0},
+	{"PRD_RDS"                     ,	56,	7,	1166,	"RO",	0,	1,	0ull,	0},
+	{"PRD_ERST"                    ,	63,	1,	1166,	"RO",	0,	1,	0ull,	0},
+	{"ENB"                         ,	0,	32,	1167,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1167,	"RAZ",	1,	1,	0,	0},
+	{"RDSIZE"                      ,	0,	64,	1168,	"R/W",	0,	1,	0ull,	0},
+	{"IS_64B"                      ,	0,	32,	1169,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1169,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1170,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	22,	1170,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_54_63"              ,	54,	10,	1170,	"RAZ",	1,	1,	0,	0},
+	{"IPTR"                        ,	0,	32,	1171,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1171,	"RAZ",	1,	1,	0,	0},
+	{"BMODE"                       ,	0,	32,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1172,	"RAZ",	1,	1,	0,	0},
+	{"BP_EN"                       ,	0,	32,	1173,	"R/W",	0,	0,	4294967295ull,	4294967295ull},
+	{"RESERVED_32_63"              ,	32,	32,	1173,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	32,	1174,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1174,	"RAZ",	1,	1,	0,	0},
+	{"WMARK"                       ,	0,	32,	1175,	"R/W",	0,	0,	0ull,	14ull},
+	{"RESERVED_32_63"              ,	32,	32,	1175,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	0,	64,	1176,	"R/W",	0,	1,	0ull,	0},
+	{"OUT_RST"                     ,	0,	32,	1177,	"RO",	0,	1,	0ull,	0},
+	{"IN_RST"                      ,	32,	32,	1177,	"RO",	0,	1,	0ull,	0},
+	{"ES"                          ,	0,	64,	1178,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	1179,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1179,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	1180,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1180,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	1181,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1181,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	1182,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1182,	"RAZ",	1,	1,	0,	0},
+	{"PKIND"                       ,	0,	6,	1183,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	1183,	"RAZ",	1,	1,	0,	0},
+	{"BPKIND"                      ,	8,	6,	1183,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	1183,	"RAZ",	1,	1,	0,	0},
+	{"MRRS"                        ,	0,	3,	1184,	"R/W",	0,	0,	2ull,	2ull},
+	{"BAR0_D"                      ,	3,	1,	1184,	"R/W",	0,	0,	0ull,	0ull},
+	{"WIND_D"                      ,	4,	1,	1184,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	1184,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	1185,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	1186,	"R/W",	0,	1,	0ull,	0},
+	{"CSR"                         ,	0,	39,	1187,	"RO",	0,	1,	1ull,	0},
+	{"ARB"                         ,	39,	1,	1187,	"RO",	0,	1,	0ull,	0},
+	{"CPL0"                        ,	40,	12,	1187,	"RO",	0,	1,	1ull,	0},
+	{"CPL1"                        ,	52,	12,	1187,	"RO",	0,	1,	1ull,	0},
+	{"NND"                         ,	0,	8,	1188,	"RO",	0,	1,	1ull,	0},
+	{"NNP0"                        ,	8,	8,	1188,	"RO",	0,	1,	1ull,	0},
+	{"CSM0"                        ,	16,	15,	1188,	"RO",	0,	1,	1ull,	0},
+	{"CSM1"                        ,	31,	15,	1188,	"RO",	0,	1,	1ull,	0},
+	{"RAC"                         ,	46,	1,	1188,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	1188,	"RAZ",	1,	1,	0,	0},
+	{"NNP1"                        ,	48,	8,	1188,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	1188,	"RAZ",	1,	1,	0,	0},
+	{"NSM0"                        ,	0,	13,	1189,	"RO",	0,	1,	1ull,	0},
+	{"NSM1"                        ,	13,	13,	1189,	"RO",	0,	1,	1ull,	0},
+	{"PSM0"                        ,	26,	15,	1189,	"RO",	0,	1,	1ull,	0},
+	{"PSM1"                        ,	41,	15,	1189,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	1189,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	7,	1190,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_15"               ,	7,	9,	1190,	"RAZ",	1,	1,	0,	0},
+	{"NUMP"                        ,	16,	8,	1190,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	1190,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	0,	48,	1191,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	1191,	"R/W",	0,	0,	0ull,	0ull},
+	{"LD_CMD"                      ,	49,	2,	1191,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_51_63"              ,	51,	13,	1191,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	1192,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	1193,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	3,	45,	1193,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	1193,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	1193,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	1194,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	1195,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1195,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	1196,	"R/W",	0,	0,	0ull,	2097152ull},
+	{"RESERVED_32_63"              ,	32,	32,	1196,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	1197,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	1197,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	1197,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	1197,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	1197,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	1197,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	1197,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	1197,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	24,	1,	1197,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1197,	"RAZ",	1,	1,	0,	0},
+	{"REG_ADR"                     ,	0,	5,	1198,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1198,	"RAZ",	1,	1,	0,	0},
+	{"PHY_ADR"                     ,	8,	5,	1198,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	1198,	"RAZ",	1,	1,	0,	0},
+	{"PHY_OP"                      ,	16,	2,	1198,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	1198,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	1199,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	1199,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	1200,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	1200,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	1200,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	1200,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	1201,	"R/W",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	1201,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	1201,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	1201,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	1202,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_6_7"                ,	6,	2,	1202,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	8,	6,	1202,	"R/W",	0,	0,	19ull,	19ull},
+	{"RESERVED_14_63"              ,	14,	50,	1202,	"RAZ",	1,	1,	0,	0},
+	{"OTH"                         ,	0,	2,	1203,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	1203,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	8,	2,	1203,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	1203,	"RAZ",	1,	1,	0,	0},
+	{"FIDX"                        ,	16,	1,	1203,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	1203,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	20,	1,	1203,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	1203,	"RAZ",	1,	1,	0,	0},
+	{"NCBO"                        ,	24,	4,	1203,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_30"              ,	28,	3,	1203,	"RAZ",	1,	1,	0,	0},
+	{"SOC"                         ,	31,	1,	1203,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_33"              ,	32,	2,	1203,	"RAZ",	1,	1,	0,	0},
+	{"RWI_DAT"                     ,	34,	1,	1203,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_41"              ,	35,	7,	1203,	"RAZ",	1,	1,	0,	0},
+	{"RWO"                         ,	42,	2,	1203,	"RO",	0,	0,	0ull,	0ull},
+	{"RWO_DAT"                     ,	44,	1,	1203,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_51"              ,	45,	7,	1203,	"RAZ",	1,	1,	0,	0},
+	{"FPTR"                        ,	52,	2,	1203,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	1203,	"RAZ",	1,	1,	0,	0},
+	{"RWEN"                        ,	0,	1,	1204,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	1,	1,	1204,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDT"                         ,	2,	1,	1204,	"R/W",	0,	0,	1ull,	1ull},
+	{"STT"                         ,	3,	1,	1204,	"R/W",	0,	0,	1ull,	1ull},
+	{"RWQ_BYP_DIS"                 ,	4,	1,	1204,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWIO_BYP_DIS"                ,	5,	1,	1204,	"R/W",	0,	0,	0ull,	0ull},
+	{"WFE_THR"                     ,	6,	1,	1204,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWO_FLUSH"                   ,	7,	1,	1204,	"WR0",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1204,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	64,	1205,	"R/W",	0,	1,	0ull,	0},
+	{"FIDX_SBE"                    ,	0,	1,	1206,	"R/W1C",	0,	1,	0ull,	0},
+	{"FIDX_DBE"                    ,	1,	1,	1206,	"R/W1C",	0,	1,	0ull,	0},
+	{"IDX_SBE"                     ,	2,	1,	1206,	"R/W1C",	0,	1,	0ull,	0},
+	{"IDX_DBE"                     ,	3,	1,	1206,	"R/W1C",	0,	1,	0ull,	0},
+	{"OTH_SBE1"                    ,	4,	1,	1206,	"R/W1C",	0,	1,	0ull,	0},
+	{"OTH_DBE1"                    ,	5,	1,	1206,	"R/W1C",	0,	1,	0ull,	0},
+	{"OTH_SBE0"                    ,	6,	1,	1206,	"R/W1C",	0,	1,	0ull,	0},
+	{"OTH_DBE0"                    ,	7,	1,	1206,	"R/W1C",	0,	1,	0ull,	0},
+	{"PND_SBE1"                    ,	8,	1,	1206,	"R/W1C",	0,	1,	0ull,	0},
+	{"PND_DBE1"                    ,	9,	1,	1206,	"R/W1C",	0,	1,	0ull,	0},
+	{"PND_SBE0"                    ,	10,	1,	1206,	"R/W1C",	0,	1,	0ull,	0},
+	{"PND_DBE0"                    ,	11,	1,	1206,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_12_31"              ,	12,	20,	1206,	"RAZ",	1,	1,	0,	0},
+	{"IOP"                         ,	32,	11,	1206,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_44"              ,	43,	2,	1206,	"RAZ",	1,	1,	0,	0},
+	{"FPE"                         ,	45,	1,	1206,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AWE"                         ,	46,	1,	1206,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BFP"                         ,	47,	1,	1206,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1206,	"RAZ",	1,	1,	0,	0},
+	{"FIDX_SBE_IE"                 ,	0,	1,	1207,	"R/W",	0,	1,	0ull,	0},
+	{"FIDX_DBE_IE"                 ,	1,	1,	1207,	"R/W",	0,	1,	0ull,	0},
+	{"IDX_SBE_IE"                  ,	2,	1,	1207,	"R/W",	0,	1,	0ull,	0},
+	{"IDX_DBE_IE"                  ,	3,	1,	1207,	"R/W",	0,	1,	0ull,	0},
+	{"OTH_SBE1_IE"                 ,	4,	1,	1207,	"R/W",	0,	1,	0ull,	0},
+	{"OTH_DBE1_IE"                 ,	5,	1,	1207,	"R/W",	0,	1,	0ull,	0},
+	{"OTH_SBE0_IE"                 ,	6,	1,	1207,	"R/W",	0,	1,	0ull,	0},
+	{"OTH_DBE0_IE"                 ,	7,	1,	1207,	"R/W",	0,	1,	0ull,	0},
+	{"PND_SBE1_IE"                 ,	8,	1,	1207,	"R/W",	0,	1,	0ull,	0},
+	{"PND_DBE1_IE"                 ,	9,	1,	1207,	"R/W",	0,	1,	0ull,	0},
+	{"PND_SBE0_IE"                 ,	10,	1,	1207,	"R/W",	0,	1,	0ull,	0},
+	{"PND_DBE0_IE"                 ,	11,	1,	1207,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_31"              ,	12,	20,	1207,	"RAZ",	1,	1,	0,	0},
+	{"IOP_IE"                      ,	32,	11,	1207,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_43_44"              ,	43,	2,	1207,	"RAZ",	1,	1,	0,	0},
+	{"FPE_IE"                      ,	45,	1,	1207,	"R/W",	0,	1,	0ull,	0},
+	{"AWE_IE"                      ,	46,	1,	1207,	"R/W",	0,	1,	0ull,	0},
+	{"BFP_IE"                      ,	47,	1,	1207,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	1207,	"RAZ",	1,	1,	0,	0},
+	{"ECC_ENA"                     ,	0,	1,	1208,	"R/W",	0,	0,	1ull,	1ull},
+	{"FLIP_SYND"                   ,	1,	2,	1208,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	1208,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1209,	"RAZ",	1,	1,	0,	0},
+	{"SYNDROM"                     ,	4,	5,	1209,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_15"               ,	9,	7,	1209,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	16,	11,	1209,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	1209,	"RAZ",	1,	1,	0,	0},
+	{"FPAGE_CNT"                   ,	0,	32,	1210,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1210,	"RAZ",	1,	1,	0,	0},
+	{"GWE_DIS"                     ,	0,	1,	1211,	"R/W",	0,	0,	0ull,	0ull},
+	{"GWE_RAH"                     ,	1,	1,	1211,	"R/W",	0,	0,	0ull,	0ull},
+	{"GWE_FPOR"                    ,	2,	1,	1211,	"R/W",	0,	0,	0ull,	0ull},
+	{"GWE_POE"                     ,	3,	1,	1211,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1211,	"RAZ",	1,	1,	0,	0},
+	{"ECC_ENA"                     ,	0,	1,	1212,	"R/W",	0,	0,	1ull,	1ull},
+	{"FLIP_SYND"                   ,	1,	2,	1212,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	1212,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1213,	"RAZ",	1,	1,	0,	0},
+	{"SYNDROM"                     ,	4,	5,	1213,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_15"               ,	9,	7,	1213,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	16,	11,	1213,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	1213,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	1214,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1214,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	1215,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1215,	"RAZ",	1,	1,	0,	0},
+	{"IQ_INT"                      ,	0,	8,	1216,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	1216,	"RAZ",	1,	1,	0,	0},
+	{"INT_EN"                      ,	0,	8,	1217,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	1217,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	32,	1218,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1218,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	12,	1219,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	1219,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	1220,	"R/W",	0,	0,	0ull,	1023ull},
+	{"RESERVED_10_63"              ,	10,	54,	1220,	"RAZ",	1,	1,	0,	0},
+	{"ECC_ENA0"                    ,	0,	1,	1221,	"R/W",	0,	0,	1ull,	1ull},
+	{"FLIP_SYND0"                  ,	1,	2,	1221,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ENA1"                    ,	3,	1,	1221,	"R/W",	0,	0,	1ull,	1ull},
+	{"FLIP_SYND1"                  ,	4,	2,	1221,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1221,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1222,	"RAZ",	1,	1,	0,	0},
+	{"SYNDROM0"                    ,	4,	7,	1222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	1222,	"RAZ",	1,	1,	0,	0},
+	{"ADDR0"                       ,	16,	11,	1222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_35"              ,	27,	9,	1222,	"RAZ",	1,	1,	0,	0},
+	{"SYNDROM1"                    ,	36,	7,	1222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_47"              ,	43,	5,	1222,	"RAZ",	1,	1,	0,	0},
+	{"ADDR1"                       ,	48,	11,	1222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_59_63"              ,	59,	5,	1222,	"RAZ",	1,	1,	0,	0},
+	{"ECC_ENA0"                    ,	0,	1,	1223,	"R/W",	0,	0,	1ull,	1ull},
+	{"FLIP_SYND0"                  ,	1,	2,	1223,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ENA1"                    ,	3,	1,	1223,	"R/W",	0,	0,	1ull,	1ull},
+	{"FLIP_SYND1"                  ,	4,	2,	1223,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1223,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1224,	"RAZ",	1,	1,	0,	0},
+	{"SYNDROM0"                    ,	4,	7,	1224,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	1224,	"RAZ",	1,	1,	0,	0},
+	{"ADDR0"                       ,	16,	11,	1224,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_35"              ,	27,	9,	1224,	"RAZ",	1,	1,	0,	0},
+	{"SYNDROM1"                    ,	36,	7,	1224,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_47"              ,	43,	5,	1224,	"RAZ",	1,	1,	0,	0},
+	{"ADDR1"                       ,	48,	11,	1224,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_59_63"              ,	59,	5,	1224,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	64,	1225,	"R/W",	0,	0,	18446744073709551615ull,	18446744073709551615ull},
+	{"QOS0_PRI"                    ,	0,	4,	1226,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	1226,	"RAZ",	1,	1,	0,	0},
+	{"QOS1_PRI"                    ,	8,	4,	1226,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_15"              ,	12,	4,	1226,	"RAZ",	1,	1,	0,	0},
+	{"QOS2_PRI"                    ,	16,	4,	1226,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_23"              ,	20,	4,	1226,	"RAZ",	1,	1,	0,	0},
+	{"QOS3_PRI"                    ,	24,	4,	1226,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	1226,	"RAZ",	1,	1,	0,	0},
+	{"QOS4_PRI"                    ,	32,	4,	1226,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	1226,	"RAZ",	1,	1,	0,	0},
+	{"QOS5_PRI"                    ,	40,	4,	1226,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_47"              ,	44,	4,	1226,	"RAZ",	1,	1,	0,	0},
+	{"QOS6_PRI"                    ,	48,	4,	1226,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_52_55"              ,	52,	4,	1226,	"RAZ",	1,	1,	0,	0},
+	{"QOS7_PRI"                    ,	56,	4,	1226,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	1226,	"RAZ",	1,	1,	0,	0},
+	{"PP_STRICT"                   ,	0,	32,	1227,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1227,	"RAZ",	1,	1,	0,	0},
+	{"RNDS_QOS"                    ,	0,	8,	1228,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	1228,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	12,	1229,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_13"              ,	12,	2,	1229,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	14,	12,	1229,	"R/W",	0,	1,	241ull,	0},
+	{"RESERVED_26_27"              ,	26,	2,	1229,	"RAZ",	1,	1,	0,	0},
+	{"BUF_CNT"                     ,	28,	12,	1229,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	1229,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	0,	12,	1230,	"RO",	0,	1,	2000ull,	0},
+	{"RESERVED_12_13"              ,	12,	2,	1230,	"RAZ",	1,	1,	0,	0},
+	{"DES_CNT"                     ,	14,	12,	1230,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	1230,	"RAZ",	1,	1,	0,	0},
+	{"RCTR"                        ,	0,	5,	1231,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_6"                ,	5,	2,	1231,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	7,	31,	1231,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1231,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_6"                ,	0,	7,	1232,	"RAZ",	1,	1,	0,	0},
+	{"FPTR"                        ,	7,	31,	1232,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_62"              ,	38,	25,	1232,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	1232,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_6"                ,	0,	7,	1233,	"RAZ",	1,	1,	0,	0},
+	{"FPTR"                        ,	7,	31,	1233,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_38_62"              ,	38,	25,	1233,	"RAZ",	1,	1,	0,	0},
+	{"FULL"                        ,	63,	1,	1233,	"RO",	0,	1,	0ull,	0},
+	{"RCTR"                        ,	0,	5,	1234,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_6"                ,	5,	2,	1234,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	7,	31,	1234,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1234,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	64,	1235,	"R/W",	0,	1,	0ull,	0},
+	{"WA_PC"                       ,	0,	64,	1236,	"R/W",	0,	1,	0ull,	0},
+	{"WA_PC"                       ,	0,	64,	1237,	"R/W",	0,	1,	0ull,	0},
+	{"WQ_INT"                      ,	0,	64,	1238,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_CNT"                      ,	0,	12,	1239,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_13"              ,	12,	2,	1239,	"RAZ",	1,	1,	0,	0},
+	{"DS_CNT"                      ,	14,	12,	1239,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_27"              ,	26,	2,	1239,	"RAZ",	1,	1,	0,	0},
+	{"TC_CNT"                      ,	28,	4,	1239,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1239,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1240,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	1240,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	1240,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	1240,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	1240,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	12,	1241,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_13"              ,	12,	2,	1241,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	14,	12,	1241,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_27"              ,	26,	2,	1241,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	28,	4,	1241,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	32,	1,	1241,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	1241,	"RAZ",	1,	1,	0,	0},
+	{"IQ_DIS"                      ,	0,	64,	1242,	"R/W1",	0,	1,	0ull,	0},
+	{"WS_PC"                       ,	0,	64,	1243,	"R/W",	0,	1,	0ull,	0},
+	{"RDS_MEM"                     ,	0,	1,	1244,	"RO",	1,	0,	0,	0ull},
+	{"LSLR_FIFO"                   ,	1,	1,	1244,	"RO",	1,	0,	0,	0ull},
+	{"WQE_FIFO"                    ,	2,	1,	1244,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	1244,	"RAZ",	1,	1,	0,	0},
+	{"FSM0_STATE"                  ,	0,	4,	1245,	"RO",	0,	0,	0ull,	0ull},
+	{"FSM1_STATE"                  ,	4,	4,	1245,	"RO",	0,	0,	0ull,	0ull},
+	{"FSM2_STATE"                  ,	8,	4,	1245,	"RO",	0,	0,	0ull,	0ull},
+	{"FSM3_STATE"                  ,	12,	4,	1245,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1245,	"RAZ",	1,	1,	0,	0},
+	{"WQE_FIFO_LEVEL"              ,	32,	8,	1245,	"RO",	0,	0,	0ull,	0ull},
+	{"RWF_FIFO_LEVEL"              ,	40,	5,	1245,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	1245,	"RAZ",	1,	1,	0,	0},
+	{"GNT_FIFO_LEVEL"              ,	48,	3,	1245,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_55"              ,	51,	5,	1245,	"RAZ",	1,	1,	0,	0},
+	{"MEM_ALLOC_REG"               ,	56,	8,	1245,	"RO",	0,	0,	0ull,	0ull},
+	{"RINGS_PENDING_VEC"           ,	0,	64,	1246,	"RO",	0,	0,	0ull,	0ull},
+	{"ECC_EN"                      ,	0,	1,	1247,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECC_FLP_SYN"                 ,	1,	2,	1247,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	1247,	"RAZ",	1,	1,	0,	0},
+	{"FR_RN_TT"                    ,	0,	22,	1248,	"R/W",	0,	0,	1024ull,	1024ull},
+	{"RESERVED_22_63"              ,	22,	42,	1248,	"RAZ",	1,	1,	0,	0},
+	{"INT0"                        ,	0,	64,	1249,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INT0_EN"                     ,	0,	64,	1250,	"R/W",	0,	0,	0ull,	0ull},
+	{"RING_ID"                     ,	0,	6,	1251,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1251,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	1252,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	1252,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1252,	"RAZ",	1,	1,	0,	0},
+	{"SBE_EN"                      ,	0,	1,	1253,	"R/W",	0,	0,	0ull,	0ull},
+	{"DBE_EN"                      ,	1,	1,	1253,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1253,	"RAZ",	1,	1,	0,	0},
+	{"ADD"                         ,	0,	8,	1254,	"RO",	0,	0,	0ull,	0ull},
+	{"SYND"                        ,	8,	7,	1254,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	1254,	"RAZ",	1,	1,	0,	0},
+	{"ORG_RDS_DAT"                 ,	0,	48,	1255,	"RO",	0,	0,	0ull,	0ull},
+	{"ORG_ECC"                     ,	48,	7,	1255,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	1255,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE_TIMERS"               ,	0,	1,	1256,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	1256,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	2,	1,	1256,	"WO",	0,	0,	0ull,	0ull},
+	{"ENA_DFB"                     ,	3,	1,	1256,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_GPIO"                    ,	4,	1,	1256,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO_EDGE"                   ,	5,	2,	1256,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	1256,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	22,	1257,	"R/W",	1,	0,	0,	0ull},
+	{"TIMERCOUNT"                  ,	22,	22,	1257,	"R/W",	1,	0,	0,	0ull},
+	{"INTC"                        ,	44,	2,	1257,	"R/W",	1,	0,	0,	0ull},
+	{"ENA"                         ,	46,	1,	1257,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	1257,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	20,	1258,	"R/W",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	20,	20,	1258,	"R/W",	1,	0,	0,	0ull},
+	{"CPOOL"                       ,	40,	3,	1258,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	1258,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	31,	1259,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_33"              ,	31,	3,	1259,	"RAZ",	1,	1,	0,	0},
+	{"CSIZE"                       ,	34,	13,	1259,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	1259,	"RAZ",	1,	1,	0,	0},
+	{"CUR_BUCKET"                  ,	0,	20,	1260,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMERCOUNT"                  ,	20,	22,	1260,	"RO",	0,	0,	4096ull,	0ull},
+	{"FR_RN_HT"                    ,	42,	22,	1260,	"RO",	0,	0,	0ull,	0ull},
+	{"RING_ESR"                    ,	0,	2,	1261,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1261,	"RAZ",	1,	1,	0,	0},
+	{"TDF"                         ,	0,	1,	1262,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1262,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	1263,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRAP"                        ,	1,	1,	1263,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRIG_CTL"                    ,	2,	2,	1263,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIME_GRN"                    ,	4,	3,	1263,	"R/W",	0,	0,	0ull,	0ull},
+	{"FULL_THR"                    ,	7,	2,	1263,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	9,	1,	1263,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	10,	1,	1263,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	11,	1,	1263,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	12,	1,	1263,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_ENA"                    ,	13,	1,	1263,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNORE_O"                    ,	14,	1,	1263,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKALWAYS"                   ,	15,	1,	1263,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDAT_MD"                     ,	16,	1,	1263,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	1263,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	8,	1264,	"RO",	0,	0,	0ull,	0ull},
+	{"RPTR"                        ,	8,	8,	1264,	"RO",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	16,	48,	1264,	"RO",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	10,	1265,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	1265,	"RAZ",	1,	1,	0,	0},
+	{"RPTR"                        ,	12,	10,	1265,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1265,	"RAZ",	1,	1,	0,	0},
+	{"CYCLES"                      ,	24,	40,	1265,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1266,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1266,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1267,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1267,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1268,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1268,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1268,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1268,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1268,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1268,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1269,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1269,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1269,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1269,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1269,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1269,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1269,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1269,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1269,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1269,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1269,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1269,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1269,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1269,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1269,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1269,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1269,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1269,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1269,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1269,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	8,	1270,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1270,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1270,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1270,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1270,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1270,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1270,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	0,	1,	1271,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	1,	1,	1271,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	2,	1,	1271,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	3,	1,	1271,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1271,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	1272,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	5,	1273,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	1273,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1274,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1274,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1275,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1275,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1276,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1276,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1276,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1276,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1276,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1276,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1277,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1277,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1277,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1277,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1277,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1277,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1277,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1277,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1277,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1277,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1277,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1277,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1277,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1277,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1277,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1277,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1277,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1277,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1277,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1277,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	8,	1278,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1278,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1278,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1278,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1278,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1278,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1278,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1279,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1279,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1280,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1280,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1281,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1281,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1281,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1281,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1281,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1281,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1282,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1282,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1282,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1282,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1282,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1282,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1282,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1282,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1282,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1282,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1282,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1282,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1282,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1282,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1282,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1282,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1282,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1282,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1282,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1282,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	8,	1283,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1283,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1283,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1283,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1283,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1283,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1283,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	1284,	"R/W",	0,	1,	0ull,	0},
+	{"LPL"                         ,	5,	27,	1284,	"R/W",	0,	1,	0ull,	0},
+	{"CF"                          ,	0,	1,	1285,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_31"               ,	1,	31,	1285,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTRLDSSEG"                   ,	0,	32,	1286,	"R/W",	0,	1,	0ull,	0},
+	{"FI"                          ,	0,	14,	1287,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_31"              ,	14,	18,	1287,	"RO",	0,	0,	0ull,	0ull},
+	{"CAPLENGTH"                   ,	0,	8,	1288,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_8_15"               ,	8,	8,	1288,	"RO",	0,	0,	0ull,	0ull},
+	{"HCIVERSION"                  ,	16,	16,	1288,	"RO",	0,	0,	256ull,	256ull},
+	{"AC64"                        ,	0,	1,	1289,	"RO",	0,	0,	1ull,	1ull},
+	{"PFLF"                        ,	1,	1,	1289,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPC"                        ,	2,	1,	1289,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1289,	"RO",	0,	0,	0ull,	0ull},
+	{"IST"                         ,	4,	4,	1289,	"RO",	0,	0,	2ull,	2ull},
+	{"EECP"                        ,	8,	8,	1289,	"RO",	0,	0,	160ull,	160ull},
+	{"RESERVED_16_31"              ,	16,	16,	1289,	"RO",	0,	0,	0ull,	0ull},
+	{"N_PORTS"                     ,	0,	4,	1290,	"RO",	0,	0,	2ull,	2ull},
+	{"PPC"                         ,	4,	1,	1290,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	1290,	"RO",	0,	0,	0ull,	0ull},
+	{"PRR"                         ,	7,	1,	1290,	"RO",	0,	0,	0ull,	0ull},
+	{"N_PCC"                       ,	8,	4,	1290,	"RO",	0,	0,	2ull,	2ull},
+	{"N_CC"                        ,	12,	4,	1290,	"RO",	0,	0,	1ull,	1ull},
+	{"P_INDICATOR"                 ,	16,	1,	1290,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	1290,	"RO",	0,	0,	0ull,	0ull},
+	{"DPN"                         ,	20,	4,	1290,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1290,	"RO",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	0,	1,	1291,	"R/W",	0,	0,	0ull,	0ull},
+	{"MFMC"                        ,	1,	13,	1291,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	1291,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_0"                ,	0,	1,	1292,	"R/W",	0,	0,	0ull,	0ull},
+	{"TA_OFF"                      ,	1,	8,	1292,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	1292,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXTX_TADAO"                  ,	10,	3,	1292,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	1292,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCP_RW"                      ,	0,	1,	1293,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCP_FW"                      ,	1,	1,	1293,	"R/W",	0,	0,	0ull,	0ull},
+	{"PESD"                        ,	2,	1,	1293,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1293,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NAKRF_DIS"                   ,	4,	1,	1293,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTO_DIS"                    ,	5,	1,	1293,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	1293,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_30"               ,	0,	31,	1294,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	31,	1,	1294,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_ADDR"                    ,	0,	32,	1295,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_11"               ,	0,	12,	1296,	"R/W",	0,	1,	0ull,	0},
+	{"BADDR"                       ,	12,	20,	1296,	"R/W",	0,	1,	0ull,	0},
+	{"CCS"                         ,	0,	1,	1297,	"RO",	0,	0,	0ull,	0ull},
+	{"CSC"                         ,	1,	1,	1297,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PED"                         ,	2,	1,	1297,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEDC"                        ,	3,	1,	1297,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OCA"                         ,	4,	1,	1297,	"RO",	0,	0,	0ull,	0ull},
+	{"OCC"                         ,	5,	1,	1297,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPR"                         ,	6,	1,	1297,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPD"                         ,	7,	1,	1297,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRST"                        ,	8,	1,	1297,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	1297,	"RO",	0,	0,	0ull,	0ull},
+	{"LSTS"                        ,	10,	2,	1297,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	12,	1,	1297,	"RO",	0,	0,	1ull,	1ull},
+	{"PO"                          ,	13,	1,	1297,	"R/W",	0,	0,	1ull,	0ull},
+	{"PIC"                         ,	14,	2,	1297,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTC"                         ,	16,	4,	1297,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKCNNT_E"                    ,	20,	1,	1297,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKDSCNNT_E"                  ,	21,	1,	1297,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKOC_E"                      ,	22,	1,	1297,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	1297,	"RO",	0,	0,	0ull,	0ull},
+	{"RS"                          ,	0,	1,	1298,	"R/W",	0,	0,	0ull,	1ull},
+	{"HCRESET"                     ,	1,	1,	1298,	"R/W",	0,	0,	0ull,	0ull},
+	{"FLS"                         ,	2,	2,	1298,	"RO",	0,	0,	0ull,	0ull},
+	{"PS_EN"                       ,	4,	1,	1298,	"R/W",	0,	0,	0ull,	0ull},
+	{"AS_EN"                       ,	5,	1,	1298,	"R/W",	0,	0,	0ull,	0ull},
+	{"IAA_DB"                      ,	6,	1,	1298,	"R/W",	0,	0,	0ull,	0ull},
+	{"LHCR"                        ,	7,	1,	1298,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASPMC"                       ,	8,	2,	1298,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	1298,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPM_EN"                     ,	11,	1,	1298,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	1298,	"RO",	0,	0,	0ull,	0ull},
+	{"ITC"                         ,	16,	8,	1298,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_24_31"              ,	24,	8,	1298,	"RO",	0,	0,	0ull,	0ull},
+	{"USBINT_EN"                   ,	0,	1,	1299,	"R/W",	0,	1,	0ull,	0},
+	{"USBERRINT_EN"                ,	1,	1,	1299,	"R/W",	0,	1,	0ull,	0},
+	{"PCI_EN"                      ,	2,	1,	1299,	"R/W",	0,	1,	0ull,	0},
+	{"FLRO_EN"                     ,	3,	1,	1299,	"R/W",	0,	1,	0ull,	0},
+	{"HSERR_EN"                    ,	4,	1,	1299,	"R/W",	0,	1,	0ull,	0},
+	{"IOAA_EN"                     ,	5,	1,	1299,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_31"               ,	6,	26,	1299,	"RO",	0,	0,	0ull,	0ull},
+	{"USBINT"                      ,	0,	1,	1300,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBERRINT"                   ,	1,	1,	1300,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCD"                         ,	2,	1,	1300,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FLRO"                        ,	3,	1,	1300,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HSYSERR"                     ,	4,	1,	1300,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOAA"                        ,	5,	1,	1300,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	1300,	"RO",	0,	0,	0ull,	0ull},
+	{"HCHTD"                       ,	12,	1,	1300,	"RO",	0,	0,	1ull,	0ull},
+	{"RECLM"                       ,	13,	1,	1300,	"RO",	0,	0,	0ull,	0ull},
+	{"PSS"                         ,	14,	1,	1300,	"RO",	0,	0,	0ull,	0ull},
+	{"ASS"                         ,	15,	1,	1300,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1300,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1301,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCED"                        ,	4,	28,	1301,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1302,	"R/W",	0,	0,	0ull,	0ull},
+	{"BHED"                        ,	4,	28,	1302,	"R/W",	0,	1,	0ull,	0},
+	{"HCR"                         ,	0,	1,	1303,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLF"                         ,	1,	1,	1303,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLF"                         ,	2,	1,	1303,	"R/W",	0,	0,	0ull,	0ull},
+	{"OCR"                         ,	3,	1,	1303,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	1303,	"RO",	0,	0,	0ull,	0ull},
+	{"SOC"                         ,	16,	2,	1303,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	1303,	"RO",	0,	0,	0ull,	0ull},
+	{"CBSR"                        ,	0,	2,	1304,	"R/W",	0,	1,	0ull,	0},
+	{"PLE"                         ,	2,	1,	1304,	"R/W",	0,	0,	0ull,	0ull},
+	{"IE"                          ,	3,	1,	1304,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLE"                         ,	4,	1,	1304,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLE"                         ,	5,	1,	1304,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCFS"                        ,	6,	2,	1304,	"R/W",	0,	0,	0ull,	0ull},
+	{"IR"                          ,	8,	1,	1304,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWC"                         ,	9,	1,	1304,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWE"                         ,	10,	1,	1304,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	1304,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1305,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCED"                        ,	4,	28,	1305,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1306,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHED"                        ,	4,	28,	1306,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1307,	"RO",	0,	0,	0ull,	0ull},
+	{"DH"                          ,	4,	28,	1307,	"RO",	0,	1,	0ull,	0},
+	{"FI"                          ,	0,	14,	1308,	"R/W",	0,	1,	11999ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	1308,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSMPS"                       ,	16,	15,	1308,	"R/W",	0,	1,	0ull,	0},
+	{"FIT"                         ,	31,	1,	1308,	"R/W",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	0,	16,	1309,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	1309,	"RO",	0,	0,	0ull,	0ull},
+	{"FR"                          ,	0,	14,	1310,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_30"              ,	14,	17,	1310,	"RO",	0,	0,	0ull,	0ull},
+	{"FRT"                         ,	31,	1,	1310,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	1311,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCCA"                        ,	8,	24,	1311,	"R/W",	0,	1,	0ull,	0},
+	{"SO"                          ,	0,	1,	1312,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1312,	"R/W",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1312,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1312,	"R/W",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1312,	"R/W",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1312,	"R/W",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1312,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1312,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1312,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIE"                         ,	31,	1,	1312,	"R/W",	0,	0,	0ull,	0ull},
+	{"SO"                          ,	0,	1,	1313,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1313,	"R/W",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1313,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1313,	"R/W",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1313,	"R/W",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1313,	"R/W",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1313,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1313,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1313,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIE"                         ,	31,	1,	1313,	"R/W",	0,	0,	0ull,	0ull},
+	{"SO"                          ,	0,	1,	1314,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1314,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1314,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1314,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1314,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1314,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1314,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1314,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1314,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1314,	"RO",	0,	0,	0ull,	0ull},
+	{"LST"                         ,	0,	12,	1315,	"R/W",	0,	1,	1576ull,	0},
+	{"RESERVED_12_31"              ,	12,	20,	1315,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1316,	"RO",	0,	0,	0ull,	0ull},
+	{"PCED"                        ,	4,	28,	1316,	"RO",	0,	1,	0ull,	0},
+	{"PS"                          ,	0,	14,	1317,	"R/W",	0,	0,	0ull,	15975ull},
+	{"RESERVED_14_31"              ,	14,	18,	1317,	"R/W",	0,	0,	0ull,	0ull},
+	{"REV"                         ,	0,	8,	1318,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_8_31"               ,	8,	24,	1318,	"RO",	0,	0,	0ull,	0ull},
+	{"NDP"                         ,	0,	8,	1319,	"RO",	0,	0,	2ull,	2ull},
+	{"NPS"                         ,	8,	1,	1319,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSM"                         ,	9,	1,	1319,	"R/W",	0,	0,	1ull,	1ull},
+	{"DT"                          ,	10,	1,	1319,	"RO",	0,	0,	0ull,	0ull},
+	{"OCPM"                        ,	11,	1,	1319,	"R/W",	1,	1,	0,	0},
+	{"NOCP"                        ,	12,	1,	1319,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_23"              ,	13,	11,	1319,	"RO",	0,	0,	0ull,	0ull},
+	{"POTPGT"                      ,	24,	8,	1319,	"R/W",	0,	0,	1ull,	1ull},
+	{"DR"                          ,	0,	16,	1320,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPCM"                        ,	16,	16,	1320,	"R/W",	0,	1,	0ull,	0},
+	{"CCS"                         ,	0,	1,	1321,	"R/W",	0,	1,	0ull,	0},
+	{"PES"                         ,	1,	1,	1321,	"R/W",	0,	1,	0ull,	0},
+	{"PSS"                         ,	2,	1,	1321,	"R/W",	0,	1,	0ull,	0},
+	{"POCI"                        ,	3,	1,	1321,	"R/W",	0,	1,	0ull,	0},
+	{"PRS"                         ,	4,	1,	1321,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1321,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS"                         ,	8,	1,	1321,	"R/W",	0,	1,	0ull,	0},
+	{"LSDA"                        ,	9,	1,	1321,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_10_15"              ,	10,	6,	1321,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSC"                         ,	16,	1,	1321,	"R/W",	0,	1,	0ull,	0},
+	{"PESC"                        ,	17,	1,	1321,	"R/W",	0,	1,	0ull,	0},
+	{"PSSC"                        ,	18,	1,	1321,	"R/W",	0,	1,	0ull,	0},
+	{"OCIC"                        ,	19,	1,	1321,	"R/W",	0,	1,	0ull,	0},
+	{"PRSC"                        ,	20,	1,	1321,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_31"              ,	21,	11,	1321,	"R/W",	0,	0,	0ull,	0ull},
+	{"LPS"                         ,	0,	1,	1322,	"R/W",	0,	0,	0ull,	0ull},
+	{"OCI"                         ,	1,	1,	1322,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_14"               ,	2,	13,	1322,	"RO",	0,	0,	0ull,	0ull},
+	{"DRWE"                        ,	15,	1,	1322,	"R/W",	0,	1,	0ull,	0},
+	{"LPSC"                        ,	16,	1,	1322,	"R/W",	0,	1,	0ull,	0},
+	{"CCIC"                        ,	17,	1,	1322,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_18_30"              ,	18,	13,	1322,	"RO",	0,	0,	0ull,	0ull},
+	{"CRWE"                        ,	31,	1,	1322,	"WO",	1,	1,	0,	0},
+	{"RESERVED_0_30"               ,	0,	31,	1323,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	31,	1,	1323,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_ADDR"                    ,	0,	32,	1324,	"RO",	0,	0,	0ull,	0ull},
+	{"PPAF_BIS"                    ,	0,	1,	1325,	"RO",	0,	0,	0ull,	0ull},
+	{"WRBM_BIS"                    ,	1,	1,	1325,	"RO",	0,	0,	0ull,	0ull},
+	{"ORBM_BIS"                    ,	2,	1,	1325,	"RO",	0,	0,	0ull,	0ull},
+	{"ERBM_BIS"                    ,	3,	1,	1325,	"RO",	0,	0,	0ull,	0ull},
+	{"DESC_BIS"                    ,	4,	1,	1325,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_BIS"                    ,	5,	1,	1325,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1325,	"RO",	1,	1,	0,	0},
+	{"HRST"                        ,	0,	1,	1326,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_PRST"                      ,	1,	1,	1326,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_POR"                       ,	2,	1,	1326,	"R/W",	0,	0,	1ull,	0ull},
+	{"P_COM_ON"                    ,	3,	1,	1326,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	1326,	"R/W",	0,	1,	0ull,	0},
+	{"P_REFCLK_DIV"                ,	5,	2,	1326,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_REFCLK_SEL"                ,	7,	2,	1326,	"R/W",	0,	0,	0ull,	0ull},
+	{"H_DIV"                       ,	9,	4,	1326,	"R/W",	0,	0,	6ull,	6ull},
+	{"O_CLKDIV_EN"                 ,	13,	1,	1326,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_EN"                 ,	14,	1,	1326,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_RST"                ,	15,	1,	1326,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_BYP"                ,	16,	1,	1326,	"R/W",	0,	0,	0ull,	0ull},
+	{"O_CLKDIV_RST"                ,	17,	1,	1326,	"R/W",	0,	0,	0ull,	1ull},
+	{"APP_START_CLK"               ,	18,	1,	1326,	"R/W",	0,	0,	0ull,	0ull},
+	{"OHCI_SUSP_LGCY"              ,	19,	1,	1326,	"R/W",	0,	0,	1ull,	1ull},
+	{"OHCI_SM"                     ,	20,	1,	1326,	"R/W",	0,	0,	0ull,	0ull},
+	{"OHCI_CLKCKTRST"              ,	21,	1,	1326,	"R/W",	0,	0,	1ull,	1ull},
+	{"EHCI_SM"                     ,	22,	1,	1326,	"R/W",	0,	0,	0ull,	0ull},
+	{"START_BIST"                  ,	23,	1,	1326,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLEAR_BIST"                  ,	24,	1,	1326,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1326,	"RAZ",	1,	1,	0,	0},
+	{"L2C_ADDR_MSB"                ,	0,	8,	1327,	"R/W",	0,	1,	0ull,	0},
+	{"EHCI_64B_ADDR_EN"            ,	8,	1,	1327,	"R/W",	0,	0,	1ull,	1ull},
+	{"INV_REG_A2"                  ,	9,	1,	1327,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DESC_EMOD"               ,	10,	2,	1327,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BUFF_EMOD"               ,	12,	2,	1327,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2C_STT"                     ,	14,	1,	1327,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_0PAG"                    ,	15,	1,	1327,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BC"                      ,	16,	1,	1327,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DC"                      ,	17,	1,	1327,	"R/W",	0,	0,	1ull,	1ull},
+	{"REG_NB"                      ,	18,	1,	1327,	"R/W",	0,	0,	0ull,	0ull},
+	{"DESC_RBM"                    ,	19,	1,	1327,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1327,	"RAZ",	1,	1,	0,	0},
+	{"FLA"                         ,	0,	6,	1328,	"R/W",	0,	0,	0ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	1328,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	1329,	"RAZ",	1,	1,	0,	0},
+	{"TO_VAL"                      ,	5,	27,	1329,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1329,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	1330,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	1330,	"RAZ",	1,	1,	0,	0},
+	{"PP_PSH_F"                    ,	0,	1,	1331,	"R/W",	0,	0,	0ull,	0ull},
+	{"ER_PSH_F"                    ,	1,	1,	1331,	"R/W",	0,	0,	0ull,	0ull},
+	{"OR_PSH_F"                    ,	2,	1,	1331,	"R/W",	0,	0,	0ull,	0ull},
+	{"CF_PSH_F"                    ,	3,	1,	1331,	"R/W",	0,	0,	0ull,	0ull},
+	{"WB_PSH_F"                    ,	4,	1,	1331,	"R/W",	0,	0,	0ull,	0ull},
+	{"WB_POP_E"                    ,	5,	1,	1331,	"R/W",	0,	0,	0ull,	0ull},
+	{"OC_OVF_E"                    ,	6,	1,	1331,	"R/W",	0,	0,	0ull,	0ull},
+	{"EC_OVF_E"                    ,	7,	1,	1331,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1331,	"RAZ",	1,	1,	0,	0},
+	{"PP_PSH_F"                    ,	0,	1,	1332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ER_PSH_F"                    ,	1,	1,	1332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OR_PSH_F"                    ,	2,	1,	1332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CF_PSH_F"                    ,	3,	1,	1332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WB_PSH_F"                    ,	4,	1,	1332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WB_POP_E"                    ,	5,	1,	1332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OC_OVF_E"                    ,	6,	1,	1332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EC_OVF_E"                    ,	7,	1,	1332,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1332,	"RAZ",	1,	1,	0,	0},
+	{"L2C_ADDR_MSB"                ,	0,	8,	1333,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_8"                ,	8,	1,	1333,	"RAZ",	1,	1,	0,	0},
+	{"INV_REG_A2"                  ,	9,	1,	1333,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DESC_EMOD"               ,	10,	2,	1333,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BUFF_EMOD"               ,	12,	2,	1333,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2C_STT"                     ,	14,	1,	1333,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_0PAG"                    ,	15,	1,	1333,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BC"                      ,	16,	1,	1333,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DC"                      ,	17,	1,	1333,	"R/W",	0,	0,	1ull,	1ull},
+	{"REG_NB"                      ,	18,	1,	1333,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	1333,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1334,	"RAZ",	1,	1,	0,	0},
+	{"TO_VAL"                      ,	8,	24,	1334,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1334,	"RAZ",	1,	1,	0,	0},
+	{"ATE_RESET"                   ,	0,	1,	1335,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_EN"                     ,	1,	1,	1335,	"R/W",	0,	0,	0ull,	0ull},
+	{"UPHY_BIST"                   ,	2,	1,	1335,	"R/W",	0,	0,	0ull,	0ull},
+	{"VTEST_EN"                    ,	3,	1,	1335,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIDDQ"                       ,	4,	1,	1335,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBIST"                      ,	5,	1,	1335,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSBIST"                      ,	6,	1,	1335,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSBIST"                      ,	7,	1,	1335,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_ERR"                    ,	8,	1,	1335,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST_DONE"                   ,	9,	1,	1335,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1335,	"RAZ",	1,	1,	0,	0},
+	{"TDATA_IN"                    ,	0,	8,	1336,	"R/W",	0,	0,	0ull,	0ull},
+	{"TADDR_IN"                    ,	8,	4,	1336,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_SEL"                   ,	12,	1,	1336,	"R/W",	0,	0,	1ull,	0ull},
+	{"TCLK"                        ,	13,	1,	1336,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOP_EN"                     ,	14,	1,	1336,	"R/W",	0,	0,	0ull,	0ull},
+	{"COMPDISTUNE"                 ,	15,	3,	1336,	"R/W",	0,	0,	4ull,	4ull},
+	{"SQRXTUNE"                    ,	18,	3,	1336,	"R/W",	0,	0,	4ull,	4ull},
+	{"TXFSLSTUNE"                  ,	21,	4,	1336,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPREEMPHASISTUNE"           ,	25,	1,	1336,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXRISETUNE"                  ,	26,	1,	1336,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXVREFTUNE"                  ,	27,	4,	1336,	"R/W",	0,	0,	5ull,	15ull},
+	{"TXHSVXTUNE"                  ,	31,	2,	1336,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORTRESET"                   ,	33,	1,	1336,	"R/W",	0,	0,	0ull,	0ull},
+	{"VBUSVLDEXT"                  ,	34,	1,	1336,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPPULLDOWN"                  ,	35,	1,	1336,	"R/W",	0,	0,	1ull,	1ull},
+	{"DMPULLDOWN"                  ,	36,	1,	1336,	"R/W",	0,	0,	1ull,	1ull},
+	{"TXBISTSTUFFEN"               ,	37,	1,	1336,	"R/W",	0,	0,	1ull,	1ull},
+	{"TXBISTSTUFFENH"              ,	38,	1,	1336,	"R/W",	0,	0,	1ull,	1ull},
+	{"TDATA_OUT"                   ,	39,	4,	1336,	"RO",	1,	1,	0,	0},
+	{"RESERVED_43_63"              ,	43,	21,	1336,	"RAZ",	1,	1,	0,	0},
+	{"ZIP_CTL"                     ,	0,	4,	1337,	"RO",	1,	0,	0,	0ull},
+	{"ZIP_CORE"                    ,	4,	53,	1337,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_57_63"              ,	57,	7,	1337,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	1338,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	33,	13,	1338,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	46,	3,	1338,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	49,	9,	1338,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	1338,	"RAZ",	1,	1,	0,	0},
+	{"RESET"                       ,	0,	1,	1339,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FORCECLK"                    ,	1,	1,	1339,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1339,	"RAZ",	1,	1,	0,	0},
+	{"DISABLED"                    ,	0,	1,	1340,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	1340,	"RAZ",	1,	1,	0,	0},
+	{"CTXSIZE"                     ,	8,	12,	1340,	"RO",	0,	0,	1536ull,	1536ull},
+	{"ONFSIZE"                     ,	20,	12,	1340,	"RO",	0,	0,	512ull,	512ull},
+	{"DEPTH"                       ,	32,	16,	1340,	"RO",	0,	0,	31744ull,	31744ull},
+	{"RESERVED_48_63"              ,	48,	16,	1340,	"RAZ",	1,	1,	0,	0},
+	{"BSTATUS"                     ,	0,	53,	1341,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_53_63"              ,	53,	11,	1341,	"RAZ",	1,	1,	0,	0},
+	{"BSTATUS"                     ,	0,	7,	1342,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	1342,	"RAZ",	1,	1,	0,	0},
+	{"LMOD"                        ,	0,	1,	1343,	"R/W",	0,	0,	0ull,	0ull},
+	{"BUSY"                        ,	1,	1,	1343,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_2_3"                ,	2,	2,	1343,	"RAZ",	1,	0,	0,	0ull},
+	{"WKQF"                        ,	4,	2,	1343,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_7"                ,	6,	2,	1343,	"RAZ",	1,	0,	0,	0ull},
+	{"LDF"                         ,	8,	3,	1343,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_11_11"              ,	11,	1,	1343,	"RAZ",	1,	0,	0,	0ull},
+	{"STCF"                        ,	12,	3,	1343,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_15_15"              ,	15,	1,	1343,	"RAZ",	1,	0,	0,	0ull},
+	{"GSTF"                        ,	16,	3,	1343,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_19_19"              ,	19,	1,	1343,	"RAZ",	1,	0,	0,	0ull},
+	{"IPRF"                        ,	20,	2,	1343,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_22_23"              ,	22,	2,	1343,	"RAZ",	1,	0,	0,	0ull},
+	{"ILDF"                        ,	24,	3,	1343,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_27_63"              ,	27,	37,	1343,	"RAZ",	1,	0,	0,	0ull},
+	{"IID"                         ,	0,	32,	1344,	"RO",	0,	1,	0ull,	0},
+	{"QID"                         ,	32,	1,	1344,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_33_62"              ,	33,	30,	1344,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	63,	1,	1344,	"RO",	0,	1,	0ull,	0},
+	{"NIE"                         ,	0,	32,	1345,	"RO",	0,	1,	0ull,	0},
+	{"IST"                         ,	32,	5,	1345,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_37_62"              ,	37,	26,	1345,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	63,	1,	1345,	"RO",	0,	1,	0ull,	0},
+	{"NII"                         ,	0,	32,	1346,	"RO",	0,	1,	0ull,	0},
+	{"CDBC"                        ,	32,	20,	1346,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_62"              ,	52,	11,	1346,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	63,	1,	1346,	"RO",	0,	1,	0ull,	0},
+	{"ASSERTS"                     ,	0,	30,	1347,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_63"              ,	30,	34,	1347,	"RAZ",	1,	1,	0,	0},
+	{"IBEN"                        ,	0,	1,	1348,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_31"               ,	1,	31,	1348,	"RAZ",	1,	1,	0,	0},
+	{"IBGE"                        ,	32,	2,	1348,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	1348,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1349,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1349,	"RAZ",	1,	1,	0,	0},
+	{"FIFE"                        ,	0,	1,	1350,	"R/W",	0,	0,	0ull,	0ull},
+	{"IBSBE"                       ,	1,	1,	1350,	"R/W",	0,	0,	0ull,	0ull},
+	{"IBDBE"                       ,	2,	1,	1350,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	1350,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL0"                   ,	8,	1,	1350,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL1"                   ,	9,	1,	1350,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1350,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1351,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1351,	"RAZ",	1,	1,	0,	0},
+	{"FIFE"                        ,	0,	1,	1352,	"RO",	0,	0,	0ull,	0ull},
+	{"IBSBE"                       ,	1,	1,	1352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IBDBE"                       ,	2,	1,	1352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	1352,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL0"                   ,	8,	1,	1352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL1"                   ,	9,	1,	1352,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1352,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	1353,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	33,	13,	1353,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	46,	3,	1353,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	49,	9,	1353,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	1353,	"RAZ",	1,	1,	0,	0},
+	{"INUM"                        ,	0,	32,	1354,	"RO",	0,	0,	0ull,	0ull},
+	{"WNUM"                        ,	32,	3,	1354,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	1354,	"RAZ",	1,	1,	0,	0},
+	{"ZCE"                         ,	0,	2,	1355,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_2_63"               ,	2,	62,	1355,	"RAZ",	1,	1,	0,	0},
+	{"ENA"                         ,	0,	2,	1356,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_2_63"               ,	2,	62,	1356,	"RAZ",	1,	1,	0,	0},
+	{"PRI"                         ,	0,	2,	1357,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1357,	"RAZ",	1,	1,	0,	0},
+	{"MAX_INFL"                    ,	0,	5,	1358,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	1358,	"RAZ",	1,	1,	0,	0},
+	{NULL,0,0,0,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn68xx[] = {
+	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
+	{"cvmx_agl_gmx_bad_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	0,	14,	0},
+	{"cvmx_agl_gmx_bist"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1,	2,	14},
+	{"cvmx_agl_gmx_prt#_cfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2,	13,	16},
+	{"cvmx_agl_gmx_rx#_adr_cam0"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	3,	1,	29},
+	{"cvmx_agl_gmx_rx#_adr_cam1"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	4,	1,	30},
+	{"cvmx_agl_gmx_rx#_adr_cam2"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5,	1,	31},
+	{"cvmx_agl_gmx_rx#_adr_cam3"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	6,	1,	32},
+	{"cvmx_agl_gmx_rx#_adr_cam4"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7,	1,	33},
+	{"cvmx_agl_gmx_rx#_adr_cam5"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8,	1,	34},
+	{"cvmx_agl_gmx_rx#_adr_cam_en" ,	CVMX_CSR_DB_TYPE_RSL,	64,	9,	2,	35},
+	{"cvmx_agl_gmx_rx#_adr_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	10,	4,	37},
+	{"cvmx_agl_gmx_rx#_decision"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	11,	2,	41},
+	{"cvmx_agl_gmx_rx#_frm_chk"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	12,	11,	43},
+	{"cvmx_agl_gmx_rx#_frm_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	13,	14,	54},
+	{"cvmx_agl_gmx_rx#_frm_max"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	14,	2,	68},
+	{"cvmx_agl_gmx_rx#_frm_min"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	15,	2,	70},
+	{"cvmx_agl_gmx_rx#_ifg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	16,	2,	72},
+	{"cvmx_agl_gmx_rx#_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	17,	21,	74},
+	{"cvmx_agl_gmx_rx#_int_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	18,	21,	95},
+	{"cvmx_agl_gmx_rx#_jabber"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	19,	2,	116},
+	{"cvmx_agl_gmx_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	20,	2,	118},
+	{"cvmx_agl_gmx_rx#_rx_inbnd"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	21,	4,	120},
+	{"cvmx_agl_gmx_rx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	22,	2,	124},
+	{"cvmx_agl_gmx_rx#_stats_octs" ,	CVMX_CSR_DB_TYPE_RSL,	64,	23,	2,	126},
+	{"cvmx_agl_gmx_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	24,	2,	128},
+	{"cvmx_agl_gmx_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	25,	2,	130},
+	{"cvmx_agl_gmx_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	26,	2,	132},
+	{"cvmx_agl_gmx_rx#_stats_pkts" ,	CVMX_CSR_DB_TYPE_RSL,	64,	27,	2,	134},
+	{"cvmx_agl_gmx_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	28,	2,	136},
+	{"cvmx_agl_gmx_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	29,	2,	138},
+	{"cvmx_agl_gmx_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	30,	2,	140},
+	{"cvmx_agl_gmx_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	31,	2,	142},
+	{"cvmx_agl_gmx_rx#_udd_skp"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	32,	4,	144},
+	{"cvmx_agl_gmx_rx_bp_drop#"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	33,	2,	148},
+	{"cvmx_agl_gmx_rx_bp_off#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	34,	2,	150},
+	{"cvmx_agl_gmx_rx_bp_on#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	35,	2,	152},
+	{"cvmx_agl_gmx_rx_prt_info"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	36,	4,	154},
+	{"cvmx_agl_gmx_rx_tx_status"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	37,	4,	158},
+	{"cvmx_agl_gmx_smac#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	38,	2,	162},
+	{"cvmx_agl_gmx_stat_bp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	39,	3,	164},
+	{"cvmx_agl_gmx_tx#_append"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	40,	5,	167},
+	{"cvmx_agl_gmx_tx#_clk"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	41,	2,	172},
+	{"cvmx_agl_gmx_tx#_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	42,	3,	174},
+	{"cvmx_agl_gmx_tx#_min_pkt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	43,	2,	177},
+	{"cvmx_agl_gmx_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	44,	2,	179},
+	{"cvmx_agl_gmx_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	45,	2,	181},
+	{"cvmx_agl_gmx_tx#_pause_togo" ,	CVMX_CSR_DB_TYPE_RSL,	64,	46,	2,	183},
+	{"cvmx_agl_gmx_tx#_pause_zero" ,	CVMX_CSR_DB_TYPE_RSL,	64,	47,	2,	185},
+	{"cvmx_agl_gmx_tx#_soft_pause" ,	CVMX_CSR_DB_TYPE_RSL,	64,	48,	2,	187},
+	{"cvmx_agl_gmx_tx#_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	49,	2,	189},
+	{"cvmx_agl_gmx_tx#_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	50,	2,	191},
+	{"cvmx_agl_gmx_tx#_stat2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	51,	2,	193},
+	{"cvmx_agl_gmx_tx#_stat3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	52,	2,	195},
+	{"cvmx_agl_gmx_tx#_stat4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	53,	2,	197},
+	{"cvmx_agl_gmx_tx#_stat5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	54,	2,	199},
+	{"cvmx_agl_gmx_tx#_stat6"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	55,	2,	201},
+	{"cvmx_agl_gmx_tx#_stat7"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	56,	2,	203},
+	{"cvmx_agl_gmx_tx#_stat8"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	57,	2,	205},
+	{"cvmx_agl_gmx_tx#_stat9"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	58,	2,	207},
+	{"cvmx_agl_gmx_tx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	59,	2,	209},
+	{"cvmx_agl_gmx_tx#_thresh"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	60,	2,	211},
+	{"cvmx_agl_gmx_tx_bp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	61,	2,	213},
+	{"cvmx_agl_gmx_tx_col_attempt" ,	CVMX_CSR_DB_TYPE_RSL,	64,	62,	2,	215},
+	{"cvmx_agl_gmx_tx_ifg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	63,	3,	217},
+	{"cvmx_agl_gmx_tx_int_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	64,	12,	220},
+	{"cvmx_agl_gmx_tx_int_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	65,	12,	232},
+	{"cvmx_agl_gmx_tx_jam"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	66,	2,	244},
+	{"cvmx_agl_gmx_tx_lfsr"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	67,	2,	246},
+	{"cvmx_agl_gmx_tx_ovr_bp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	68,	6,	248},
+	{"cvmx_agl_gmx_tx_pause_pkt_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	69,	2,	254},
+	{"cvmx_agl_gmx_tx_pause_pkt_type",	CVMX_CSR_DB_TYPE_RSL,	64,	70,	2,	256},
+	{"cvmx_agl_prt#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	71,	23,	258},
+	{"cvmx_ciu2_ack_io#_int"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	72,	2,	281},
+	{"cvmx_ciu2_ack_pp#_ip2"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	74,	2,	283},
+	{"cvmx_ciu2_ack_pp#_ip3"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	106,	2,	285},
+	{"cvmx_ciu2_ack_pp#_ip4"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	138,	2,	287},
+	{"cvmx_ciu2_en_io#_int_gpio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	170,	2,	289},
+	{"cvmx_ciu2_en_io#_int_gpio_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	172,	2,	291},
+	{"cvmx_ciu2_en_io#_int_gpio_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	174,	2,	293},
+	{"cvmx_ciu2_en_io#_int_io"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	176,	9,	295},
+	{"cvmx_ciu2_en_io#_int_io_w1c" ,	CVMX_CSR_DB_TYPE_NCB,	64,	178,	9,	304},
+	{"cvmx_ciu2_en_io#_int_io_w1s" ,	CVMX_CSR_DB_TYPE_NCB,	64,	180,	9,	313},
+	{"cvmx_ciu2_en_io#_int_mbox"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	182,	2,	322},
+	{"cvmx_ciu2_en_io#_int_mbox_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	184,	2,	324},
+	{"cvmx_ciu2_en_io#_int_mbox_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	186,	2,	326},
+	{"cvmx_ciu2_en_io#_int_mem"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	188,	2,	328},
+	{"cvmx_ciu2_en_io#_int_mem_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	190,	2,	330},
+	{"cvmx_ciu2_en_io#_int_mem_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	192,	2,	332},
+	{"cvmx_ciu2_en_io#_int_mio"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	194,	21,	334},
+	{"cvmx_ciu2_en_io#_int_mio_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	196,	21,	355},
+	{"cvmx_ciu2_en_io#_int_mio_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	198,	21,	376},
+	{"cvmx_ciu2_en_io#_int_pkt"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	200,	12,	397},
+	{"cvmx_ciu2_en_io#_int_pkt_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	202,	12,	409},
+	{"cvmx_ciu2_en_io#_int_pkt_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	204,	12,	421},
+	{"cvmx_ciu2_en_io#_int_rml"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	206,	26,	433},
+	{"cvmx_ciu2_en_io#_int_rml_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	208,	26,	459},
+	{"cvmx_ciu2_en_io#_int_rml_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	210,	26,	485},
+	{"cvmx_ciu2_en_io#_int_wdog"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	212,	2,	511},
+	{"cvmx_ciu2_en_io#_int_wdog_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	214,	2,	513},
+	{"cvmx_ciu2_en_io#_int_wdog_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	216,	2,	515},
+	{"cvmx_ciu2_en_io#_int_wrkq"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	218,	1,	517},
+	{"cvmx_ciu2_en_io#_int_wrkq_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	220,	1,	518},
+	{"cvmx_ciu2_en_io#_int_wrkq_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	222,	1,	519},
+	{"cvmx_ciu2_en_pp#_ip2_gpio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	224,	2,	520},
+	{"cvmx_ciu2_en_pp#_ip2_gpio_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	256,	2,	522},
+	{"cvmx_ciu2_en_pp#_ip2_gpio_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	288,	2,	524},
+	{"cvmx_ciu2_en_pp#_ip2_io"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	320,	9,	526},
+	{"cvmx_ciu2_en_pp#_ip2_io_w1c" ,	CVMX_CSR_DB_TYPE_NCB,	64,	352,	9,	535},
+	{"cvmx_ciu2_en_pp#_ip2_io_w1s" ,	CVMX_CSR_DB_TYPE_NCB,	64,	384,	9,	544},
+	{"cvmx_ciu2_en_pp#_ip2_mbox"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	416,	2,	553},
+	{"cvmx_ciu2_en_pp#_ip2_mbox_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	448,	2,	555},
+	{"cvmx_ciu2_en_pp#_ip2_mbox_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	480,	2,	557},
+	{"cvmx_ciu2_en_pp#_ip2_mem"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	512,	2,	559},
+	{"cvmx_ciu2_en_pp#_ip2_mem_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	544,	2,	561},
+	{"cvmx_ciu2_en_pp#_ip2_mem_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	576,	2,	563},
+	{"cvmx_ciu2_en_pp#_ip2_mio"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	608,	21,	565},
+	{"cvmx_ciu2_en_pp#_ip2_mio_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	640,	21,	586},
+	{"cvmx_ciu2_en_pp#_ip2_mio_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	672,	21,	607},
+	{"cvmx_ciu2_en_pp#_ip2_pkt"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	704,	12,	628},
+	{"cvmx_ciu2_en_pp#_ip2_pkt_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	736,	12,	640},
+	{"cvmx_ciu2_en_pp#_ip2_pkt_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	768,	12,	652},
+	{"cvmx_ciu2_en_pp#_ip2_rml"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	800,	26,	664},
+	{"cvmx_ciu2_en_pp#_ip2_rml_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	832,	26,	690},
+	{"cvmx_ciu2_en_pp#_ip2_rml_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	864,	26,	716},
+	{"cvmx_ciu2_en_pp#_ip2_wdog"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	896,	2,	742},
+	{"cvmx_ciu2_en_pp#_ip2_wdog_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	928,	2,	744},
+	{"cvmx_ciu2_en_pp#_ip2_wdog_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	960,	2,	746},
+	{"cvmx_ciu2_en_pp#_ip2_wrkq"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	992,	1,	748},
+	{"cvmx_ciu2_en_pp#_ip2_wrkq_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1024,	1,	749},
+	{"cvmx_ciu2_en_pp#_ip2_wrkq_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	1056,	1,	750},
+	{"cvmx_ciu2_en_pp#_ip3_gpio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1088,	2,	751},
+	{"cvmx_ciu2_en_pp#_ip3_gpio_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1120,	2,	753},
+	{"cvmx_ciu2_en_pp#_ip3_gpio_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	1152,	2,	755},
+	{"cvmx_ciu2_en_pp#_ip3_io"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1184,	9,	757},
+	{"cvmx_ciu2_en_pp#_ip3_io_w1c" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1216,	9,	766},
+	{"cvmx_ciu2_en_pp#_ip3_io_w1s" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1248,	9,	775},
+	{"cvmx_ciu2_en_pp#_ip3_mbox"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1280,	2,	784},
+	{"cvmx_ciu2_en_pp#_ip3_mbox_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1312,	2,	786},
+	{"cvmx_ciu2_en_pp#_ip3_mbox_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	1344,	2,	788},
+	{"cvmx_ciu2_en_pp#_ip3_mem"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1376,	2,	790},
+	{"cvmx_ciu2_en_pp#_ip3_mem_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1408,	2,	792},
+	{"cvmx_ciu2_en_pp#_ip3_mem_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	1440,	2,	794},
+	{"cvmx_ciu2_en_pp#_ip3_mio"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1472,	21,	796},
+	{"cvmx_ciu2_en_pp#_ip3_mio_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1504,	21,	817},
+	{"cvmx_ciu2_en_pp#_ip3_mio_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	1536,	21,	838},
+	{"cvmx_ciu2_en_pp#_ip3_pkt"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1568,	12,	859},
+	{"cvmx_ciu2_en_pp#_ip3_pkt_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1600,	12,	871},
+	{"cvmx_ciu2_en_pp#_ip3_pkt_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	1632,	12,	883},
+	{"cvmx_ciu2_en_pp#_ip3_rml"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1664,	26,	895},
+	{"cvmx_ciu2_en_pp#_ip3_rml_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1696,	26,	921},
+	{"cvmx_ciu2_en_pp#_ip3_rml_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	1728,	26,	947},
+	{"cvmx_ciu2_en_pp#_ip3_wdog"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1760,	2,	973},
+	{"cvmx_ciu2_en_pp#_ip3_wdog_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1792,	2,	975},
+	{"cvmx_ciu2_en_pp#_ip3_wdog_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	1824,	2,	977},
+	{"cvmx_ciu2_en_pp#_ip3_wrkq"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1856,	1,	979},
+	{"cvmx_ciu2_en_pp#_ip3_wrkq_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1888,	1,	980},
+	{"cvmx_ciu2_en_pp#_ip3_wrkq_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	1920,	1,	981},
+	{"cvmx_ciu2_en_pp#_ip4_gpio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1952,	2,	982},
+	{"cvmx_ciu2_en_pp#_ip4_gpio_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	1984,	2,	984},
+	{"cvmx_ciu2_en_pp#_ip4_gpio_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	2016,	2,	986},
+	{"cvmx_ciu2_en_pp#_ip4_io"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	2048,	9,	988},
+	{"cvmx_ciu2_en_pp#_ip4_io_w1c" ,	CVMX_CSR_DB_TYPE_NCB,	64,	2080,	9,	997},
+	{"cvmx_ciu2_en_pp#_ip4_io_w1s" ,	CVMX_CSR_DB_TYPE_NCB,	64,	2112,	9,	1006},
+	{"cvmx_ciu2_en_pp#_ip4_mbox"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2144,	2,	1015},
+	{"cvmx_ciu2_en_pp#_ip4_mbox_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	2176,	2,	1017},
+	{"cvmx_ciu2_en_pp#_ip4_mbox_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	2208,	2,	1019},
+	{"cvmx_ciu2_en_pp#_ip4_mem"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2240,	2,	1021},
+	{"cvmx_ciu2_en_pp#_ip4_mem_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	2272,	2,	1023},
+	{"cvmx_ciu2_en_pp#_ip4_mem_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	2304,	2,	1025},
+	{"cvmx_ciu2_en_pp#_ip4_mio"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2336,	21,	1027},
+	{"cvmx_ciu2_en_pp#_ip4_mio_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	2368,	21,	1048},
+	{"cvmx_ciu2_en_pp#_ip4_mio_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	2400,	21,	1069},
+	{"cvmx_ciu2_en_pp#_ip4_pkt"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2432,	12,	1090},
+	{"cvmx_ciu2_en_pp#_ip4_pkt_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	2464,	12,	1102},
+	{"cvmx_ciu2_en_pp#_ip4_pkt_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	2496,	12,	1114},
+	{"cvmx_ciu2_en_pp#_ip4_rml"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2528,	26,	1126},
+	{"cvmx_ciu2_en_pp#_ip4_rml_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	2560,	26,	1152},
+	{"cvmx_ciu2_en_pp#_ip4_rml_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	2592,	26,	1178},
+	{"cvmx_ciu2_en_pp#_ip4_wdog"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2624,	2,	1204},
+	{"cvmx_ciu2_en_pp#_ip4_wdog_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	2656,	2,	1206},
+	{"cvmx_ciu2_en_pp#_ip4_wdog_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	2688,	2,	1208},
+	{"cvmx_ciu2_en_pp#_ip4_wrkq"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2720,	1,	1210},
+	{"cvmx_ciu2_en_pp#_ip4_wrkq_w1c",	CVMX_CSR_DB_TYPE_NCB,	64,	2752,	1,	1211},
+	{"cvmx_ciu2_en_pp#_ip4_wrkq_w1s",	CVMX_CSR_DB_TYPE_NCB,	64,	2784,	1,	1212},
+	{"cvmx_ciu2_intr_ciu_ready"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2816,	2,	1213},
+	{"cvmx_ciu2_intr_ram_ecc_ctl"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	2817,	3,	1215},
+	{"cvmx_ciu2_intr_ram_ecc_st"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2818,	7,	1218},
+	{"cvmx_ciu2_intr_slowdown"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	2819,	2,	1225},
+	{"cvmx_ciu2_msi_rcv#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2820,	2,	1227},
+	{"cvmx_ciu2_msi_sel#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	3076,	6,	1229},
+	{"cvmx_ciu2_msired_pp#_ip2"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3332,	6,	1235},
+	{"cvmx_ciu2_msired_pp#_ip3"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3364,	6,	1241},
+	{"cvmx_ciu2_msired_pp#_ip4"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3396,	6,	1247},
+	{"cvmx_ciu2_raw_io#_int_gpio"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3428,	2,	1253},
+	{"cvmx_ciu2_raw_io#_int_io"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3430,	9,	1255},
+	{"cvmx_ciu2_raw_io#_int_mem"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3432,	2,	1264},
+	{"cvmx_ciu2_raw_io#_int_mio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3434,	21,	1266},
+	{"cvmx_ciu2_raw_io#_int_pkt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3436,	12,	1287},
+	{"cvmx_ciu2_raw_io#_int_rml"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3438,	26,	1299},
+	{"cvmx_ciu2_raw_io#_int_wdog"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3440,	2,	1325},
+	{"cvmx_ciu2_raw_io#_int_wrkq"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3442,	1,	1327},
+	{"cvmx_ciu2_raw_pp#_ip2_gpio"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3444,	2,	1328},
+	{"cvmx_ciu2_raw_pp#_ip2_io"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3476,	9,	1330},
+	{"cvmx_ciu2_raw_pp#_ip2_mem"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3508,	2,	1339},
+	{"cvmx_ciu2_raw_pp#_ip2_mio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3540,	21,	1341},
+	{"cvmx_ciu2_raw_pp#_ip2_pkt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3572,	12,	1362},
+	{"cvmx_ciu2_raw_pp#_ip2_rml"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3604,	26,	1374},
+	{"cvmx_ciu2_raw_pp#_ip2_wdog"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3636,	2,	1400},
+	{"cvmx_ciu2_raw_pp#_ip2_wrkq"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3668,	1,	1402},
+	{"cvmx_ciu2_raw_pp#_ip3_gpio"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3700,	2,	1403},
+	{"cvmx_ciu2_raw_pp#_ip3_io"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3732,	9,	1405},
+	{"cvmx_ciu2_raw_pp#_ip3_mem"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3764,	2,	1414},
+	{"cvmx_ciu2_raw_pp#_ip3_mio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3796,	21,	1416},
+	{"cvmx_ciu2_raw_pp#_ip3_pkt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3828,	12,	1437},
+	{"cvmx_ciu2_raw_pp#_ip3_rml"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3860,	26,	1449},
+	{"cvmx_ciu2_raw_pp#_ip3_wdog"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3892,	2,	1475},
+	{"cvmx_ciu2_raw_pp#_ip3_wrkq"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3924,	1,	1477},
+	{"cvmx_ciu2_raw_pp#_ip4_gpio"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	3956,	2,	1478},
+	{"cvmx_ciu2_raw_pp#_ip4_io"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3988,	9,	1480},
+	{"cvmx_ciu2_raw_pp#_ip4_mem"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4020,	2,	1489},
+	{"cvmx_ciu2_raw_pp#_ip4_mio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4052,	21,	1491},
+	{"cvmx_ciu2_raw_pp#_ip4_pkt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4084,	12,	1512},
+	{"cvmx_ciu2_raw_pp#_ip4_rml"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4116,	26,	1524},
+	{"cvmx_ciu2_raw_pp#_ip4_wdog"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4148,	2,	1550},
+	{"cvmx_ciu2_raw_pp#_ip4_wrkq"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4180,	1,	1552},
+	{"cvmx_ciu2_src_io#_int_gpio"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4212,	2,	1553},
+	{"cvmx_ciu2_src_io#_int_io"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	4214,	9,	1555},
+	{"cvmx_ciu2_src_io#_int_mbox"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4216,	2,	1564},
+	{"cvmx_ciu2_src_io#_int_mem"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4218,	2,	1566},
+	{"cvmx_ciu2_src_io#_int_mio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4220,	21,	1568},
+	{"cvmx_ciu2_src_io#_int_pkt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4222,	12,	1589},
+	{"cvmx_ciu2_src_io#_int_rml"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4224,	26,	1601},
+	{"cvmx_ciu2_src_io#_int_wdog"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4226,	2,	1627},
+	{"cvmx_ciu2_src_io#_int_wrkq"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4228,	1,	1629},
+	{"cvmx_ciu2_src_pp#_ip2_gpio"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4230,	2,	1630},
+	{"cvmx_ciu2_src_pp#_ip2_io"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	4262,	9,	1632},
+	{"cvmx_ciu2_src_pp#_ip2_mbox"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4294,	2,	1641},
+	{"cvmx_ciu2_src_pp#_ip2_mem"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4326,	2,	1643},
+	{"cvmx_ciu2_src_pp#_ip2_mio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4358,	21,	1645},
+	{"cvmx_ciu2_src_pp#_ip2_pkt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4390,	12,	1666},
+	{"cvmx_ciu2_src_pp#_ip2_rml"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4422,	26,	1678},
+	{"cvmx_ciu2_src_pp#_ip2_wdog"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4454,	2,	1704},
+	{"cvmx_ciu2_src_pp#_ip2_wrkq"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4486,	1,	1706},
+	{"cvmx_ciu2_src_pp#_ip3_gpio"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4518,	2,	1707},
+	{"cvmx_ciu2_src_pp#_ip3_io"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	4550,	9,	1709},
+	{"cvmx_ciu2_src_pp#_ip3_mbox"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4582,	2,	1718},
+	{"cvmx_ciu2_src_pp#_ip3_mem"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4614,	2,	1720},
+	{"cvmx_ciu2_src_pp#_ip3_mio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4646,	21,	1722},
+	{"cvmx_ciu2_src_pp#_ip3_pkt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4678,	12,	1743},
+	{"cvmx_ciu2_src_pp#_ip3_rml"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4710,	26,	1755},
+	{"cvmx_ciu2_src_pp#_ip3_wdog"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4742,	2,	1781},
+	{"cvmx_ciu2_src_pp#_ip3_wrkq"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4774,	1,	1783},
+	{"cvmx_ciu2_src_pp#_ip4_gpio"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4806,	2,	1784},
+	{"cvmx_ciu2_src_pp#_ip4_io"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	4838,	9,	1786},
+	{"cvmx_ciu2_src_pp#_ip4_mbox"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4870,	2,	1795},
+	{"cvmx_ciu2_src_pp#_ip4_mem"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4902,	2,	1797},
+	{"cvmx_ciu2_src_pp#_ip4_mio"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4934,	21,	1799},
+	{"cvmx_ciu2_src_pp#_ip4_pkt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4966,	12,	1820},
+	{"cvmx_ciu2_src_pp#_ip4_rml"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	4998,	26,	1832},
+	{"cvmx_ciu2_src_pp#_ip4_wdog"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	5030,	2,	1858},
+	{"cvmx_ciu2_src_pp#_ip4_wrkq"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	5062,	1,	1860},
+	{"cvmx_ciu2_sum_io#_int"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5094,	10,	1861},
+	{"cvmx_ciu2_sum_pp#_ip2"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5096,	10,	1871},
+	{"cvmx_ciu2_sum_pp#_ip3"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5128,	10,	1881},
+	{"cvmx_ciu2_sum_pp#_ip4"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5160,	10,	1891},
+	{"cvmx_ciu_bist"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5192,	2,	1901},
+	{"cvmx_ciu_dint"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5193,	2,	1903},
+	{"cvmx_ciu_fuse"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5194,	2,	1905},
+	{"cvmx_ciu_gstop"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	5195,	2,	1907},
+	{"cvmx_ciu_int_dbg_sel"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5196,	6,	1909},
+	{"cvmx_ciu_mbox_clr#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	5197,	2,	1915},
+	{"cvmx_ciu_mbox_set#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	5229,	2,	1917},
+	{"cvmx_ciu_nmi"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	5261,	2,	1919},
+	{"cvmx_ciu_pci_inta"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5262,	2,	1921},
+	{"cvmx_ciu_pp_bist_stat"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5263,	2,	1923},
+	{"cvmx_ciu_pp_dbg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5264,	2,	1925},
+	{"cvmx_ciu_pp_poke#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5265,	1,	1927},
+	{"cvmx_ciu_pp_rst"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5297,	3,	1928},
+	{"cvmx_ciu_qlm0"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5298,	8,	1931},
+	{"cvmx_ciu_qlm1"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5299,	13,	1939},
+	{"cvmx_ciu_qlm2"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5300,	13,	1952},
+	{"cvmx_ciu_qlm3"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5301,	13,	1965},
+	{"cvmx_ciu_qlm4"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5302,	13,	1978},
+	{"cvmx_ciu_qlm_jtgc"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5303,	7,	1991},
+	{"cvmx_ciu_qlm_jtgd"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5304,	8,	1998},
+	{"cvmx_ciu_soft_bist"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	5305,	2,	2006},
+	{"cvmx_ciu_soft_prst"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	5306,	2,	2008},
+	{"cvmx_ciu_soft_prst1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	5307,	2,	2010},
+	{"cvmx_ciu_soft_rst"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5308,	2,	2012},
+	{"cvmx_ciu_tim#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5309,	3,	2014},
+	{"cvmx_ciu_wdog#"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	5313,	7,	2017},
+	{"cvmx_dfa_bist0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	5345,	16,	2024},
+	{"cvmx_dfa_bist1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	5346,	20,	2040},
+	{"cvmx_dfa_config"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	5347,	7,	2060},
+	{"cvmx_dfa_control"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5348,	7,	2067},
+	{"cvmx_dfa_dbell"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	5349,	2,	2074},
+	{"cvmx_dfa_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	5350,	1,	2076},
+	{"cvmx_dfa_debug1"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	5351,	1,	2077},
+	{"cvmx_dfa_debug2"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	5352,	1,	2078},
+	{"cvmx_dfa_debug3"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	5353,	1,	2079},
+	{"cvmx_dfa_difctl"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5354,	5,	2080},
+	{"cvmx_dfa_difrdptr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5355,	3,	2085},
+	{"cvmx_dfa_dtcfadr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5356,	6,	2088},
+	{"cvmx_dfa_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	5357,	12,	2094},
+	{"cvmx_dfa_intmsk"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	5358,	11,	2106},
+	{"cvmx_dfa_memhidat"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5359,	1,	2117},
+	{"cvmx_dfa_pfc0_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5360,	1,	2118},
+	{"cvmx_dfa_pfc0_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5361,	5,	2119},
+	{"cvmx_dfa_pfc1_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5362,	1,	2124},
+	{"cvmx_dfa_pfc1_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5363,	5,	2125},
+	{"cvmx_dfa_pfc2_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5364,	1,	2130},
+	{"cvmx_dfa_pfc2_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5365,	5,	2131},
+	{"cvmx_dfa_pfc3_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5366,	1,	2136},
+	{"cvmx_dfa_pfc3_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5367,	5,	2137},
+	{"cvmx_dfa_pfc_gctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5368,	18,	2142},
+	{"cvmx_dpi_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5369,	2,	2160},
+	{"cvmx_dpi_ctl"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	5370,	3,	2162},
+	{"cvmx_dpi_dma#_counts"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5371,	3,	2165},
+	{"cvmx_dpi_dma#_dbell"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	5379,	2,	2168},
+	{"cvmx_dpi_dma#_err_rsp_status",	CVMX_CSR_DB_TYPE_NCB,	64,	5387,	2,	2170},
+	{"cvmx_dpi_dma#_ibuff_saddr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	5395,	6,	2172},
+	{"cvmx_dpi_dma#_iflight"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5403,	2,	2178},
+	{"cvmx_dpi_dma#_naddr"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	5411,	2,	2180},
+	{"cvmx_dpi_dma#_reqbnk0"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5419,	1,	2182},
+	{"cvmx_dpi_dma#_reqbnk1"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5427,	1,	2183},
+	{"cvmx_dpi_dma_control"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5435,	20,	2184},
+	{"cvmx_dpi_dma_eng#_en"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5436,	2,	2204},
+	{"cvmx_dpi_dma_pp#_cnt"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5442,	2,	2206},
+	{"cvmx_dpi_eng#_buf"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5474,	5,	2208},
+	{"cvmx_dpi_info_reg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5480,	5,	2213},
+	{"cvmx_dpi_int_en"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5481,	15,	2218},
+	{"cvmx_dpi_int_reg"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5482,	15,	2233},
+	{"cvmx_dpi_ncb#_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5483,	2,	2248},
+	{"cvmx_dpi_pint_info"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	5484,	4,	2250},
+	{"cvmx_dpi_pkt_err_rsp"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5485,	2,	2254},
+	{"cvmx_dpi_req_err_rsp"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5486,	2,	2256},
+	{"cvmx_dpi_req_err_rsp_en"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	5487,	2,	2258},
+	{"cvmx_dpi_req_err_rst"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5488,	2,	2260},
+	{"cvmx_dpi_req_err_rst_en"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	5489,	2,	2262},
+	{"cvmx_dpi_req_err_skip_comp"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	5490,	4,	2264},
+	{"cvmx_dpi_req_gbl_en"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	5491,	2,	2268},
+	{"cvmx_dpi_sli_prt#_cfg"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5492,	14,	2270},
+	{"cvmx_dpi_sli_prt#_err"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5494,	2,	2284},
+	{"cvmx_dpi_sli_prt#_err_info"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	5496,	6,	2286},
+	{"cvmx_fpa_addr_range_error"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5498,	3,	2292},
+	{"cvmx_fpa_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5499,	6,	2295},
+	{"cvmx_fpa_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5500,	10,	2301},
+	{"cvmx_fpa_fpf#_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5501,	3,	2311},
+	{"cvmx_fpa_fpf#_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5508,	2,	2314},
+	{"cvmx_fpa_fpf0_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5515,	3,	2316},
+	{"cvmx_fpa_fpf0_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5516,	2,	2319},
+	{"cvmx_fpa_fpf8_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5517,	3,	2321},
+	{"cvmx_fpa_fpf8_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5518,	2,	2324},
+	{"cvmx_fpa_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5519,	51,	2326},
+	{"cvmx_fpa_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5520,	51,	2377},
+	{"cvmx_fpa_packet_threshold"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5521,	2,	2428},
+	{"cvmx_fpa_pool#_end_addr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5522,	2,	2430},
+	{"cvmx_fpa_pool#_start_addr"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5531,	2,	2432},
+	{"cvmx_fpa_pool#_threshold"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5540,	2,	2434},
+	{"cvmx_fpa_que#_available"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5549,	2,	2436},
+	{"cvmx_fpa_que#_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5558,	2,	2438},
+	{"cvmx_fpa_que8_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5566,	2,	2440},
+	{"cvmx_fpa_que_act"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5567,	3,	2442},
+	{"cvmx_fpa_que_exp"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5568,	3,	2445},
+	{"cvmx_fpa_wqe_threshold"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5569,	2,	2448},
+	{"cvmx_gmx#_bad_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5570,	7,	2450},
+	{"cvmx_gmx#_bist"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	5575,	2,	2457},
+	{"cvmx_gmx#_bpid_map#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5580,	6,	2459},
+	{"cvmx_gmx#_bpid_msk"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5660,	4,	2465},
+	{"cvmx_gmx#_clk_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5665,	2,	2469},
+	{"cvmx_gmx#_ebp_dis"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5670,	2,	2471},
+	{"cvmx_gmx#_ebp_msk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5675,	2,	2473},
+	{"cvmx_gmx#_hg2_control"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5680,	5,	2475},
+	{"cvmx_gmx#_inf_mode"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5685,	7,	2480},
+	{"cvmx_gmx#_nxa_adr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5690,	4,	2487},
+	{"cvmx_gmx#_pipe_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5695,	6,	2491},
+	{"cvmx_gmx#_prt#_cbfc_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5700,	8,	2497},
+	{"cvmx_gmx#_prt#_cfg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5705,	12,	2505},
+	{"cvmx_gmx#_rx#_adr_cam0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5725,	1,	2517},
+	{"cvmx_gmx#_rx#_adr_cam1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5745,	1,	2518},
+	{"cvmx_gmx#_rx#_adr_cam2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5765,	1,	2519},
+	{"cvmx_gmx#_rx#_adr_cam3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5785,	1,	2520},
+	{"cvmx_gmx#_rx#_adr_cam4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5805,	1,	2521},
+	{"cvmx_gmx#_rx#_adr_cam5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5825,	1,	2522},
+	{"cvmx_gmx#_rx#_adr_cam_all_en",	CVMX_CSR_DB_TYPE_RSL,	64,	5845,	2,	2523},
+	{"cvmx_gmx#_rx#_adr_cam_en"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5865,	2,	2525},
+	{"cvmx_gmx#_rx#_adr_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5885,	4,	2527},
+	{"cvmx_gmx#_rx#_decision"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5905,	2,	2531},
+	{"cvmx_gmx#_rx#_frm_chk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5925,	9,	2533},
+	{"cvmx_gmx#_rx#_frm_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5945,	13,	2542},
+	{"cvmx_gmx#_rx#_ifg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5965,	2,	2555},
+	{"cvmx_gmx#_rx#_int_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5985,	27,	2557},
+	{"cvmx_gmx#_rx#_int_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6005,	27,	2584},
+	{"cvmx_gmx#_rx#_jabber"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6025,	2,	2611},
+	{"cvmx_gmx#_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	6045,	2,	2613},
+	{"cvmx_gmx#_rx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6065,	2,	2615},
+	{"cvmx_gmx#_rx#_stats_octs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6085,	2,	2617},
+	{"cvmx_gmx#_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	6105,	2,	2619},
+	{"cvmx_gmx#_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	6125,	2,	2621},
+	{"cvmx_gmx#_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	6145,	2,	2623},
+	{"cvmx_gmx#_rx#_stats_pkts"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6165,	2,	2625},
+	{"cvmx_gmx#_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	6185,	2,	2627},
+	{"cvmx_gmx#_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	6205,	2,	2629},
+	{"cvmx_gmx#_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	6225,	2,	2631},
+	{"cvmx_gmx#_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	6245,	2,	2633},
+	{"cvmx_gmx#_rx#_udd_skp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6265,	4,	2635},
+	{"cvmx_gmx#_rx_bp_drop#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6285,	2,	2639},
+	{"cvmx_gmx#_rx_bp_off#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6305,	2,	2641},
+	{"cvmx_gmx#_rx_bp_on#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6325,	2,	2643},
+	{"cvmx_gmx#_rx_hg2_status"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6345,	4,	2645},
+	{"cvmx_gmx#_rx_prt_info"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6350,	4,	2649},
+	{"cvmx_gmx#_rx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6355,	2,	2653},
+	{"cvmx_gmx#_rx_xaui_bad_col"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	6360,	5,	2655},
+	{"cvmx_gmx#_rx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6365,	2,	2660},
+	{"cvmx_gmx#_rxaui_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6370,	2,	2662},
+	{"cvmx_gmx#_smac#"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	6375,	2,	2664},
+	{"cvmx_gmx#_soft_bist"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6395,	3,	2666},
+	{"cvmx_gmx#_stat_bp"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6400,	3,	2669},
+	{"cvmx_gmx#_tb_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6405,	2,	2672},
+	{"cvmx_gmx#_tx#_append"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6410,	5,	2674},
+	{"cvmx_gmx#_tx#_burst"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6430,	2,	2679},
+	{"cvmx_gmx#_tx#_cbfc_xoff"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6450,	2,	2681},
+	{"cvmx_gmx#_tx#_cbfc_xon"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6455,	2,	2683},
+	{"cvmx_gmx#_tx#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6460,	3,	2685},
+	{"cvmx_gmx#_tx#_min_pkt"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6480,	2,	2688},
+	{"cvmx_gmx#_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	6500,	2,	2690},
+	{"cvmx_gmx#_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	6520,	2,	2692},
+	{"cvmx_gmx#_tx#_pause_togo"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6540,	3,	2694},
+	{"cvmx_gmx#_tx#_pause_zero"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6560,	2,	2697},
+	{"cvmx_gmx#_tx#_pipe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6580,	6,	2699},
+	{"cvmx_gmx#_tx#_sgmii_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6600,	2,	2705},
+	{"cvmx_gmx#_tx#_slot"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6620,	2,	2707},
+	{"cvmx_gmx#_tx#_soft_pause"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6640,	2,	2709},
+	{"cvmx_gmx#_tx#_stat0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6660,	2,	2711},
+	{"cvmx_gmx#_tx#_stat1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6680,	2,	2713},
+	{"cvmx_gmx#_tx#_stat2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6700,	2,	2715},
+	{"cvmx_gmx#_tx#_stat3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6720,	2,	2717},
+	{"cvmx_gmx#_tx#_stat4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6740,	2,	2719},
+	{"cvmx_gmx#_tx#_stat5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6760,	2,	2721},
+	{"cvmx_gmx#_tx#_stat6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6780,	2,	2723},
+	{"cvmx_gmx#_tx#_stat7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6800,	2,	2725},
+	{"cvmx_gmx#_tx#_stat8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6820,	2,	2727},
+	{"cvmx_gmx#_tx#_stat9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6840,	2,	2729},
+	{"cvmx_gmx#_tx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6860,	2,	2731},
+	{"cvmx_gmx#_tx#_thresh"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6880,	2,	2733},
+	{"cvmx_gmx#_tx_bp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	6900,	2,	2735},
+	{"cvmx_gmx#_tx_col_attempt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6905,	2,	2737},
+	{"cvmx_gmx#_tx_corrupt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6910,	2,	2739},
+	{"cvmx_gmx#_tx_hg2_reg1"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6915,	2,	2741},
+	{"cvmx_gmx#_tx_hg2_reg2"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6920,	2,	2743},
+	{"cvmx_gmx#_tx_ifg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6925,	3,	2745},
+	{"cvmx_gmx#_tx_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6930,	10,	2748},
+	{"cvmx_gmx#_tx_int_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6935,	10,	2758},
+	{"cvmx_gmx#_tx_jam"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6940,	2,	2768},
+	{"cvmx_gmx#_tx_lfsr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6945,	2,	2770},
+	{"cvmx_gmx#_tx_ovr_bp"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6950,	6,	2772},
+	{"cvmx_gmx#_tx_pause_pkt_dmac" ,	CVMX_CSR_DB_TYPE_RSL,	64,	6955,	2,	2778},
+	{"cvmx_gmx#_tx_pause_pkt_type" ,	CVMX_CSR_DB_TYPE_RSL,	64,	6960,	2,	2780},
+	{"cvmx_gmx#_tx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6965,	2,	2782},
+	{"cvmx_gmx#_tx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6970,	9,	2784},
+	{"cvmx_gmx#_xaui_ext_loopback" ,	CVMX_CSR_DB_TYPE_RSL,	64,	6975,	3,	2793},
+	{"cvmx_gpio_bit_cfg#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6980,	10,	2796},
+	{"cvmx_gpio_clk_gen#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6996,	2,	2806},
+	{"cvmx_gpio_clk_qlm#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	7000,	5,	2808},
+	{"cvmx_gpio_int_clr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	7002,	2,	2813},
+	{"cvmx_gpio_rx_dat"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	7003,	2,	2815},
+	{"cvmx_gpio_tim_ctl"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	7004,	2,	2817},
+	{"cvmx_gpio_tx_clr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	7005,	2,	2819},
+	{"cvmx_gpio_tx_set"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	7006,	2,	2821},
+	{"cvmx_ilk_bist_sum"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7007,	44,	2823},
+	{"cvmx_ilk_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7008,	5,	2867},
+	{"cvmx_ilk_gbl_int"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7009,	6,	2872},
+	{"cvmx_ilk_gbl_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7010,	6,	2878},
+	{"cvmx_ilk_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7011,	14,	2884},
+	{"cvmx_ilk_lne_dbg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7012,	11,	2898},
+	{"cvmx_ilk_lne_sts_msg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7013,	8,	2909},
+	{"cvmx_ilk_rx#_cfg0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7014,	19,	2917},
+	{"cvmx_ilk_rx#_cfg1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7016,	14,	2936},
+	{"cvmx_ilk_rx#_flow_ctl0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7018,	1,	2950},
+	{"cvmx_ilk_rx#_flow_ctl1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7020,	1,	2951},
+	{"cvmx_ilk_rx#_idx_cal"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7022,	4,	2952},
+	{"cvmx_ilk_rx#_idx_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7024,	6,	2956},
+	{"cvmx_ilk_rx#_idx_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7026,	6,	2962},
+	{"cvmx_ilk_rx#_int"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7028,	10,	2968},
+	{"cvmx_ilk_rx#_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7030,	10,	2978},
+	{"cvmx_ilk_rx#_jabber"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7032,	2,	2988},
+	{"cvmx_ilk_rx#_mem_cal0"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7034,	9,	2990},
+	{"cvmx_ilk_rx#_mem_cal1"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7036,	9,	2999},
+	{"cvmx_ilk_rx#_mem_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7038,	2,	3008},
+	{"cvmx_ilk_rx#_mem_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7040,	2,	3010},
+	{"cvmx_ilk_rx#_rid"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7042,	2,	3012},
+	{"cvmx_ilk_rx#_stat0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7044,	2,	3014},
+	{"cvmx_ilk_rx#_stat1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7046,	2,	3016},
+	{"cvmx_ilk_rx#_stat2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7048,	4,	3018},
+	{"cvmx_ilk_rx#_stat3"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7050,	2,	3022},
+	{"cvmx_ilk_rx#_stat4"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7052,	2,	3024},
+	{"cvmx_ilk_rx#_stat5"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7054,	2,	3026},
+	{"cvmx_ilk_rx#_stat6"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7056,	2,	3028},
+	{"cvmx_ilk_rx#_stat7"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7058,	2,	3030},
+	{"cvmx_ilk_rx#_stat8"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7060,	3,	3032},
+	{"cvmx_ilk_rx#_stat9"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7062,	1,	3035},
+	{"cvmx_ilk_rx_lne#_cfg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7064,	9,	3036},
+	{"cvmx_ilk_rx_lne#_int"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7072,	10,	3045},
+	{"cvmx_ilk_rx_lne#_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7080,	10,	3055},
+	{"cvmx_ilk_rx_lne#_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7088,	2,	3065},
+	{"cvmx_ilk_rx_lne#_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7096,	2,	3067},
+	{"cvmx_ilk_rx_lne#_stat2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7104,	4,	3069},
+	{"cvmx_ilk_rx_lne#_stat3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7112,	2,	3073},
+	{"cvmx_ilk_rx_lne#_stat4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7120,	4,	3075},
+	{"cvmx_ilk_rx_lne#_stat5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7128,	2,	3079},
+	{"cvmx_ilk_rx_lne#_stat6"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7136,	2,	3081},
+	{"cvmx_ilk_rx_lne#_stat7"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7144,	2,	3083},
+	{"cvmx_ilk_rx_lne#_stat8"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7152,	2,	3085},
+	{"cvmx_ilk_rx_lne#_stat9"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7160,	4,	3087},
+	{"cvmx_ilk_rxf_idx_pmap"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7168,	4,	3091},
+	{"cvmx_ilk_rxf_mem_pmap"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7169,	2,	3095},
+	{"cvmx_ilk_ser_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7170,	12,	3097},
+	{"cvmx_ilk_tx#_cfg0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7171,	17,	3109},
+	{"cvmx_ilk_tx#_cfg1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7173,	16,	3126},
+	{"cvmx_ilk_tx#_dbg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7175,	4,	3142},
+	{"cvmx_ilk_tx#_flow_ctl0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7177,	1,	3146},
+	{"cvmx_ilk_tx#_flow_ctl1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7179,	1,	3147},
+	{"cvmx_ilk_tx#_idx_cal"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7181,	4,	3148},
+	{"cvmx_ilk_tx#_idx_pmap"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7183,	4,	3152},
+	{"cvmx_ilk_tx#_idx_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7185,	6,	3156},
+	{"cvmx_ilk_tx#_idx_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7187,	6,	3162},
+	{"cvmx_ilk_tx#_int"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7189,	5,	3168},
+	{"cvmx_ilk_tx#_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7191,	5,	3173},
+	{"cvmx_ilk_tx#_mem_cal0"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7193,	13,	3178},
+	{"cvmx_ilk_tx#_mem_cal1"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7195,	13,	3191},
+	{"cvmx_ilk_tx#_mem_pmap"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7197,	4,	3204},
+	{"cvmx_ilk_tx#_mem_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7199,	2,	3208},
+	{"cvmx_ilk_tx#_mem_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7201,	2,	3210},
+	{"cvmx_ilk_tx#_pipe"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7203,	4,	3212},
+	{"cvmx_ilk_tx#_rmatch"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7205,	5,	3216},
+	{"cvmx_iob1_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7207,	9,	3221},
+	{"cvmx_iob1_ctl_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7208,	4,	3230},
+	{"cvmx_iob1_to_cmb_credits"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7209,	4,	3234},
+	{"cvmx_iob_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7210,	19,	3238},
+	{"cvmx_iob_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7211,	9,	3257},
+	{"cvmx_iob_fau_timeout"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7212,	3,	3266},
+	{"cvmx_iob_inb_control_match"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	7213,	5,	3269},
+	{"cvmx_iob_inb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	7214,	5,	3274},
+	{"cvmx_iob_inb_data_match"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7215,	1,	3279},
+	{"cvmx_iob_inb_data_match_enb" ,	CVMX_CSR_DB_TYPE_RSL,	64,	7216,	1,	3280},
+	{"cvmx_iob_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7217,	1,	3281},
+	{"cvmx_iob_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7218,	1,	3282},
+	{"cvmx_iob_outb_com_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7219,	3,	3283},
+	{"cvmx_iob_outb_control_match" ,	CVMX_CSR_DB_TYPE_RSL,	64,	7220,	5,	3286},
+	{"cvmx_iob_outb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	7221,	5,	3291},
+	{"cvmx_iob_outb_data_match"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7222,	1,	3296},
+	{"cvmx_iob_outb_data_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	7223,	1,	3297},
+	{"cvmx_iob_outb_fpa_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7224,	3,	3298},
+	{"cvmx_iob_outb_req_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7225,	3,	3301},
+	{"cvmx_iob_to_cmb_credits"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7226,	4,	3304},
+	{"cvmx_iob_to_ncb_did_00_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7227,	2,	3308},
+	{"cvmx_iob_to_ncb_did_111_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7228,	2,	3310},
+	{"cvmx_iob_to_ncb_did_223_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7229,	2,	3312},
+	{"cvmx_iob_to_ncb_did_24_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7230,	2,	3314},
+	{"cvmx_iob_to_ncb_did_32_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7231,	2,	3316},
+	{"cvmx_iob_to_ncb_did_40_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7232,	2,	3318},
+	{"cvmx_iob_to_ncb_did_55_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7233,	2,	3320},
+	{"cvmx_iob_to_ncb_did_64_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7234,	2,	3322},
+	{"cvmx_iob_to_ncb_did_79_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7235,	2,	3324},
+	{"cvmx_iob_to_ncb_did_96_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7236,	2,	3326},
+	{"cvmx_iob_to_ncb_did_98_credits",	CVMX_CSR_DB_TYPE_RSL,	64,	7237,	2,	3328},
+	{"cvmx_ipd_1st_mbuff_skip"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	7238,	2,	3330},
+	{"cvmx_ipd_1st_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	7239,	2,	3332},
+	{"cvmx_ipd_2nd_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	7240,	2,	3334},
+	{"cvmx_ipd_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	7241,	24,	3336},
+	{"cvmx_ipd_bpid#_mbuf_th"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	7242,	3,	3360},
+	{"cvmx_ipd_bpid_bp_counter#"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	7306,	2,	3363},
+	{"cvmx_ipd_clk_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	7370,	1,	3365},
+	{"cvmx_ipd_credits"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	7371,	3,	3366},
+	{"cvmx_ipd_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	7372,	18,	3369},
+	{"cvmx_ipd_ecc_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	7373,	5,	3387},
+	{"cvmx_ipd_free_ptr_fifo_ctl"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	7374,	6,	3392},
+	{"cvmx_ipd_free_ptr_value"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	7375,	2,	3398},
+	{"cvmx_ipd_hold_ptr_fifo_ctl"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	7376,	6,	3400},
+	{"cvmx_ipd_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	7377,	24,	3406},
+	{"cvmx_ipd_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	7378,	24,	3430},
+	{"cvmx_ipd_next_pkt_ptr"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	7379,	2,	3454},
+	{"cvmx_ipd_next_wqe_ptr"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	7380,	2,	3456},
+	{"cvmx_ipd_not_1st_mbuff_skip" ,	CVMX_CSR_DB_TYPE_NCB,	64,	7381,	2,	3458},
+	{"cvmx_ipd_on_bp_drop_pkt#"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	7382,	1,	3460},
+	{"cvmx_ipd_packet_mbuff_size"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	7383,	2,	3461},
+	{"cvmx_ipd_pkt_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	7384,	2,	3463},
+	{"cvmx_ipd_port_ptr_fifo_ctl"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	7385,	5,	3465},
+	{"cvmx_ipd_port_qos_#_cnt"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	7386,	2,	3470},
+	{"cvmx_ipd_port_qos_int#"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	7898,	1,	3472},
+	{"cvmx_ipd_port_qos_int_enb#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	7906,	1,	3473},
+	{"cvmx_ipd_port_sop#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	7914,	1,	3474},
+	{"cvmx_ipd_ptr_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	7915,	6,	3475},
+	{"cvmx_ipd_qos#_red_marks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	7916,	2,	3481},
+	{"cvmx_ipd_que0_free_page_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	64,	7924,	2,	3483},
+	{"cvmx_ipd_red_bpid_enable#"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	7925,	1,	3485},
+	{"cvmx_ipd_red_delay"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	7926,	3,	3486},
+	{"cvmx_ipd_red_que#_param"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	7927,	5,	3489},
+	{"cvmx_ipd_req_wgt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	7935,	8,	3494},
+	{"cvmx_ipd_sub_port_bp_page_cnt",	CVMX_CSR_DB_TYPE_NCB,	64,	7936,	3,	3502},
+	{"cvmx_ipd_sub_port_qos_cnt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	7937,	3,	3505},
+	{"cvmx_ipd_wqe_fpa_queue"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	7938,	2,	3508},
+	{"cvmx_key_bist_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7939,	4,	3510},
+	{"cvmx_key_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7940,	3,	3514},
+	{"cvmx_key_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7941,	5,	3517},
+	{"cvmx_key_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7942,	5,	3522},
+	{"cvmx_l2c_big_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7943,	4,	3527},
+	{"cvmx_l2c_bst"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	7944,	9,	3531},
+	{"cvmx_l2c_bst_mem#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7945,	5,	3540},
+	{"cvmx_l2c_bst_tdt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7949,	5,	3545},
+	{"cvmx_l2c_bst_ttg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7953,	3,	3550},
+	{"cvmx_l2c_cop0_map#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7957,	1,	3553},
+	{"cvmx_l2c_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	16405,	16,	3554},
+	{"cvmx_l2c_dut_map#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	16406,	4,	3570},
+	{"cvmx_l2c_err_tdt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24598,	9,	3574},
+	{"cvmx_l2c_err_ttg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24602,	9,	3583},
+	{"cvmx_l2c_err_vbf#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24606,	6,	3592},
+	{"cvmx_l2c_err_xmc"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	24610,	5,	3598},
+	{"cvmx_l2c_int_ena"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	24611,	9,	3603},
+	{"cvmx_l2c_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	24612,	14,	3612},
+	{"cvmx_l2c_ioc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24613,	1,	3626},
+	{"cvmx_l2c_ior#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24614,	1,	3627},
+	{"cvmx_l2c_qos_iob#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24615,	4,	3628},
+	{"cvmx_l2c_qos_pp#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	24617,	2,	3632},
+	{"cvmx_l2c_qos_wgt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	24649,	8,	3634},
+	{"cvmx_l2c_rsc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24650,	1,	3642},
+	{"cvmx_l2c_rsd#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24654,	1,	3643},
+	{"cvmx_l2c_tad#_ecc0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	24658,	8,	3644},
+	{"cvmx_l2c_tad#_ecc1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	24662,	8,	3652},
+	{"cvmx_l2c_tad#_ien"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24666,	10,	3660},
+	{"cvmx_l2c_tad#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24670,	10,	3670},
+	{"cvmx_l2c_tad#_pfc0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	24674,	1,	3680},
+	{"cvmx_l2c_tad#_pfc1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	24678,	1,	3681},
+	{"cvmx_l2c_tad#_pfc2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	24682,	1,	3682},
+	{"cvmx_l2c_tad#_pfc3"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	24686,	1,	3683},
+	{"cvmx_l2c_tad#_prf"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24690,	5,	3684},
+	{"cvmx_l2c_tad#_tag"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24694,	9,	3689},
+	{"cvmx_l2c_ver_id"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	24698,	1,	3698},
+	{"cvmx_l2c_ver_iob"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	24699,	2,	3699},
+	{"cvmx_l2c_ver_msc"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	24700,	3,	3701},
+	{"cvmx_l2c_ver_pp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	24701,	2,	3704},
+	{"cvmx_l2c_virtid_iob#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	24702,	4,	3706},
+	{"cvmx_l2c_virtid_pp#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	24704,	2,	3710},
+	{"cvmx_l2c_vrt_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	24736,	6,	3712},
+	{"cvmx_l2c_vrt_mem#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	24737,	3,	3718},
+	{"cvmx_l2c_wpar_iob#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	25761,	2,	3721},
+	{"cvmx_l2c_wpar_pp#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25763,	2,	3723},
+	{"cvmx_l2c_xmc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25795,	1,	3725},
+	{"cvmx_l2c_xmc_cmd"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	25799,	4,	3726},
+	{"cvmx_l2c_xmd#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25800,	1,	3730},
+	{"cvmx_lmc#_char_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	25804,	7,	3731},
+	{"cvmx_lmc#_char_mask0"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25808,	1,	3738},
+	{"cvmx_lmc#_char_mask1"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25812,	2,	3739},
+	{"cvmx_lmc#_char_mask2"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25816,	1,	3741},
+	{"cvmx_lmc#_char_mask3"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25820,	2,	3742},
+	{"cvmx_lmc#_char_mask4"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25824,	12,	3744},
+	{"cvmx_lmc#_comp_ctl2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	25828,	11,	3756},
+	{"cvmx_lmc#_config"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	25832,	21,	3767},
+	{"cvmx_lmc#_control"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25836,	26,	3788},
+	{"cvmx_lmc#_dclk_cnt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	25840,	1,	3814},
+	{"cvmx_lmc#_ddr_pll_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	25844,	11,	3815},
+	{"cvmx_lmc#_dimm#_params"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	25848,	16,	3826},
+	{"cvmx_lmc#_dimm_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	25856,	5,	3842},
+	{"cvmx_lmc#_dll_ctl2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	25860,	7,	3847},
+	{"cvmx_lmc#_dll_ctl3"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	25864,	16,	3854},
+	{"cvmx_lmc#_dual_memcfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	25868,	4,	3870},
+	{"cvmx_lmc#_ecc_synd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	25872,	5,	3874},
+	{"cvmx_lmc#_fadr"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	25876,	6,	3879},
+	{"cvmx_lmc#_ifb_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25880,	1,	3885},
+	{"cvmx_lmc#_int"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	25884,	4,	3886},
+	{"cvmx_lmc#_int_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	25888,	4,	3890},
+	{"cvmx_lmc#_modereg_params0"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	25892,	16,	3894},
+	{"cvmx_lmc#_modereg_params1"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	25896,	25,	3910},
+	{"cvmx_lmc#_nxm"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	25900,	10,	3935},
+	{"cvmx_lmc#_ops_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25904,	1,	3945},
+	{"cvmx_lmc#_phy_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25908,	10,	3946},
+	{"cvmx_lmc#_reset_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	25912,	5,	3956},
+	{"cvmx_lmc#_rlevel_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25916,	10,	3961},
+	{"cvmx_lmc#_rlevel_dbg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25920,	1,	3971},
+	{"cvmx_lmc#_rlevel_rank#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	25924,	11,	3972},
+	{"cvmx_lmc#_rodt_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	25940,	8,	3983},
+	{"cvmx_lmc#_slot_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	25944,	5,	3991},
+	{"cvmx_lmc#_slot_ctl1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	25948,	5,	3996},
+	{"cvmx_lmc#_slot_ctl2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	25952,	5,	4001},
+	{"cvmx_lmc#_timing_params0"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	25956,	12,	4006},
+	{"cvmx_lmc#_timing_params1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	25960,	13,	4018},
+	{"cvmx_lmc#_tro_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	25964,	3,	4031},
+	{"cvmx_lmc#_tro_stat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	25968,	2,	4034},
+	{"cvmx_lmc#_wlevel_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25972,	6,	4036},
+	{"cvmx_lmc#_wlevel_dbg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	25976,	3,	4042},
+	{"cvmx_lmc#_wlevel_rank#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	25980,	11,	4045},
+	{"cvmx_lmc#_wodt_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	25996,	8,	4056},
+	{"cvmx_mio_boot_bist_stat"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	26000,	2,	4064},
+	{"cvmx_mio_boot_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26001,	3,	4066},
+	{"cvmx_mio_boot_dma_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26002,	10,	4069},
+	{"cvmx_mio_boot_dma_int#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26004,	3,	4079},
+	{"cvmx_mio_boot_dma_int_en#"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	26006,	3,	4082},
+	{"cvmx_mio_boot_dma_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26008,	15,	4085},
+	{"cvmx_mio_boot_err"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26010,	3,	4100},
+	{"cvmx_mio_boot_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26011,	3,	4103},
+	{"cvmx_mio_boot_loc_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26012,	3,	4106},
+	{"cvmx_mio_boot_loc_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26013,	5,	4109},
+	{"cvmx_mio_boot_loc_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26015,	1,	4114},
+	{"cvmx_mio_boot_pin_defs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26016,	9,	4115},
+	{"cvmx_mio_boot_reg_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26017,	13,	4124},
+	{"cvmx_mio_boot_reg_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26025,	13,	4137},
+	{"cvmx_mio_boot_thr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26033,	6,	4150},
+	{"cvmx_mio_fus_bnk_dat#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26034,	1,	4156},
+	{"cvmx_mio_fus_dat0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26036,	2,	4157},
+	{"cvmx_mio_fus_dat1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26037,	2,	4159},
+	{"cvmx_mio_fus_dat2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26038,	12,	4161},
+	{"cvmx_mio_fus_dat3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26039,	18,	4173},
+	{"cvmx_mio_fus_ema"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	26040,	4,	4191},
+	{"cvmx_mio_fus_pdf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	26041,	1,	4195},
+	{"cvmx_mio_fus_pll"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	26042,	10,	4196},
+	{"cvmx_mio_fus_prog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26043,	3,	4206},
+	{"cvmx_mio_fus_prog_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	26044,	8,	4209},
+	{"cvmx_mio_fus_rcmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26045,	7,	4217},
+	{"cvmx_mio_fus_read_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	26046,	6,	4224},
+	{"cvmx_mio_fus_repair_res0"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26047,	5,	4230},
+	{"cvmx_mio_fus_repair_res1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26048,	4,	4235},
+	{"cvmx_mio_fus_repair_res2"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26049,	2,	4239},
+	{"cvmx_mio_fus_spr_repair_res" ,	CVMX_CSR_DB_TYPE_RSL,	64,	26050,	4,	4241},
+	{"cvmx_mio_fus_spr_repair_sum" ,	CVMX_CSR_DB_TYPE_RSL,	64,	26051,	2,	4245},
+	{"cvmx_mio_fus_wadr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26052,	2,	4247},
+	{"cvmx_mio_gpio_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26053,	3,	4249},
+	{"cvmx_mio_ndf_dma_cfg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	26054,	10,	4252},
+	{"cvmx_mio_ndf_dma_int"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	26055,	2,	4262},
+	{"cvmx_mio_ndf_dma_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	26056,	2,	4264},
+	{"cvmx_mio_ptp_ckout_hi_incr"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	26057,	2,	4266},
+	{"cvmx_mio_ptp_ckout_lo_incr"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	26058,	2,	4268},
+	{"cvmx_mio_ptp_ckout_thresh_hi",	CVMX_CSR_DB_TYPE_NCB,	64,	26059,	1,	4270},
+	{"cvmx_mio_ptp_ckout_thresh_lo",	CVMX_CSR_DB_TYPE_NCB,	64,	26060,	2,	4271},
+	{"cvmx_mio_ptp_clock_cfg"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	26061,	20,	4273},
+	{"cvmx_mio_ptp_clock_comp"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	26062,	2,	4293},
+	{"cvmx_mio_ptp_clock_hi"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	26063,	1,	4295},
+	{"cvmx_mio_ptp_clock_lo"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	26064,	2,	4296},
+	{"cvmx_mio_ptp_evt_cnt"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	26065,	1,	4298},
+	{"cvmx_mio_ptp_pps_hi_incr"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	26066,	2,	4299},
+	{"cvmx_mio_ptp_pps_lo_incr"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	26067,	2,	4301},
+	{"cvmx_mio_ptp_pps_thresh_hi"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	26068,	1,	4303},
+	{"cvmx_mio_ptp_pps_thresh_lo"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	26069,	2,	4304},
+	{"cvmx_mio_ptp_timestamp"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	26070,	1,	4306},
+	{"cvmx_mio_qlm#_cfg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26071,	4,	4307},
+	{"cvmx_mio_rst_boot"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26076,	13,	4311},
+	{"cvmx_mio_rst_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	26077,	5,	4324},
+	{"cvmx_mio_rst_cntl#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26078,	10,	4329},
+	{"cvmx_mio_rst_ctl#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26080,	10,	4339},
+	{"cvmx_mio_rst_delay"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26082,	3,	4349},
+	{"cvmx_mio_rst_int"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	26083,	6,	4352},
+	{"cvmx_mio_rst_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	26084,	6,	4358},
+	{"cvmx_mio_tws#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26085,	13,	4364},
+	{"cvmx_mio_tws#_sw_twsi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26087,	12,	4377},
+	{"cvmx_mio_tws#_sw_twsi_ext"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	26089,	3,	4389},
+	{"cvmx_mio_tws#_twsi_sw"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26091,	3,	4392},
+	{"cvmx_mio_uart#_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26093,	2,	4395},
+	{"cvmx_mio_uart#_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26095,	2,	4397},
+	{"cvmx_mio_uart#_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26097,	2,	4399},
+	{"cvmx_mio_uart#_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26099,	7,	4401},
+	{"cvmx_mio_uart#_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26101,	2,	4408},
+	{"cvmx_mio_uart#_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26103,	7,	4410},
+	{"cvmx_mio_uart#_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26105,	4,	4417},
+	{"cvmx_mio_uart#_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26107,	8,	4421},
+	{"cvmx_mio_uart#_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26109,	9,	4429},
+	{"cvmx_mio_uart#_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26111,	7,	4438},
+	{"cvmx_mio_uart#_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26113,	9,	4445},
+	{"cvmx_mio_uart#_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26115,	2,	4454},
+	{"cvmx_mio_uart#_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26117,	2,	4456},
+	{"cvmx_mio_uart#_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26119,	4,	4458},
+	{"cvmx_mio_uart#_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	26121,	2,	4462},
+	{"cvmx_mio_uart#_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26123,	2,	4464},
+	{"cvmx_mio_uart#_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26125,	2,	4466},
+	{"cvmx_mio_uart#_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26127,	4,	4468},
+	{"cvmx_mio_uart#_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26129,	2,	4472},
+	{"cvmx_mio_uart#_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	26131,	2,	4474},
+	{"cvmx_mio_uart#_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26133,	2,	4476},
+	{"cvmx_mio_uart#_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26135,	2,	4478},
+	{"cvmx_mio_uart#_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26137,	2,	4480},
+	{"cvmx_mio_uart#_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26139,	2,	4482},
+	{"cvmx_mio_uart#_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26141,	6,	4484},
+	{"cvmx_mix#_bist"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	26143,	7,	4490},
+	{"cvmx_mix#_ctl"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	26144,	9,	4497},
+	{"cvmx_mix#_intena"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	26145,	9,	4506},
+	{"cvmx_mix#_ircnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	26146,	2,	4515},
+	{"cvmx_mix#_irhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	26147,	3,	4517},
+	{"cvmx_mix#_iring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	26148,	4,	4520},
+	{"cvmx_mix#_iring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	26149,	4,	4524},
+	{"cvmx_mix#_isr"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	26150,	9,	4528},
+	{"cvmx_mix#_orcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	26151,	2,	4537},
+	{"cvmx_mix#_orhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	26152,	2,	4539},
+	{"cvmx_mix#_oring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	26153,	4,	4541},
+	{"cvmx_mix#_oring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	26154,	4,	4545},
+	{"cvmx_mix#_remcnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	26155,	4,	4549},
+	{"cvmx_mix#_tsctl"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	26156,	6,	4553},
+	{"cvmx_mix#_tstamp"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	26157,	1,	4559},
+	{"cvmx_ndf_bt_pg_info"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	26158,	4,	4560},
+	{"cvmx_ndf_cmd"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	26159,	1,	4564},
+	{"cvmx_ndf_drbell"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	26160,	2,	4565},
+	{"cvmx_ndf_ecc_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	26161,	3,	4567},
+	{"cvmx_ndf_int"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	26162,	8,	4570},
+	{"cvmx_ndf_int_en"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	26163,	8,	4578},
+	{"cvmx_ndf_misc"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	26164,	12,	4586},
+	{"cvmx_ndf_st_reg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	26165,	8,	4598},
+	{"cvmx_pcieep#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26166,	2,	4606},
+	{"cvmx_pcieep#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26168,	24,	4608},
+	{"cvmx_pcieep#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26170,	4,	4632},
+	{"cvmx_pcieep#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26172,	5,	4636},
+	{"cvmx_pcieep#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26174,	5,	4641},
+	{"cvmx_pcieep#_cfg004_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26176,	2,	4646},
+	{"cvmx_pcieep#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26178,	1,	4648},
+	{"cvmx_pcieep#_cfg005_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26180,	1,	4649},
+	{"cvmx_pcieep#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26182,	5,	4650},
+	{"cvmx_pcieep#_cfg006_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26184,	2,	4655},
+	{"cvmx_pcieep#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26186,	1,	4657},
+	{"cvmx_pcieep#_cfg007_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26188,	1,	4658},
+	{"cvmx_pcieep#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26190,	4,	4659},
+	{"cvmx_pcieep#_cfg008_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26192,	2,	4663},
+	{"cvmx_pcieep#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26194,	2,	4665},
+	{"cvmx_pcieep#_cfg009_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26196,	1,	4667},
+	{"cvmx_pcieep#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26198,	1,	4668},
+	{"cvmx_pcieep#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26200,	2,	4669},
+	{"cvmx_pcieep#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26202,	3,	4671},
+	{"cvmx_pcieep#_cfg012_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26204,	2,	4674},
+	{"cvmx_pcieep#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26206,	2,	4676},
+	{"cvmx_pcieep#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26208,	4,	4678},
+	{"cvmx_pcieep#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26210,	10,	4682},
+	{"cvmx_pcieep#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26212,	12,	4692},
+	{"cvmx_pcieep#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26214,	8,	4704},
+	{"cvmx_pcieep#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26216,	2,	4712},
+	{"cvmx_pcieep#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26218,	1,	4714},
+	{"cvmx_pcieep#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26220,	2,	4715},
+	{"cvmx_pcieep#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26222,	7,	4717},
+	{"cvmx_pcieep#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26224,	12,	4724},
+	{"cvmx_pcieep#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26226,	19,	4736},
+	{"cvmx_pcieep#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26228,	12,	4755},
+	{"cvmx_pcieep#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26230,	20,	4767},
+	{"cvmx_pcieep#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26232,	11,	4787},
+	{"cvmx_pcieep#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26234,	8,	4798},
+	{"cvmx_pcieep#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26236,	4,	4806},
+	{"cvmx_pcieep#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26238,	11,	4810},
+	{"cvmx_pcieep#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26240,	3,	4821},
+	{"cvmx_pcieep#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26242,	16,	4824},
+	{"cvmx_pcieep#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26244,	16,	4840},
+	{"cvmx_pcieep#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26246,	16,	4856},
+	{"cvmx_pcieep#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26248,	9,	4872},
+	{"cvmx_pcieep#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26250,	9,	4881},
+	{"cvmx_pcieep#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26252,	6,	4890},
+	{"cvmx_pcieep#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26254,	1,	4896},
+	{"cvmx_pcieep#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26256,	1,	4897},
+	{"cvmx_pcieep#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26258,	1,	4898},
+	{"cvmx_pcieep#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26260,	1,	4899},
+	{"cvmx_pcieep#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26262,	2,	4900},
+	{"cvmx_pcieep#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26264,	1,	4902},
+	{"cvmx_pcieep#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26266,	6,	4903},
+	{"cvmx_pcieep#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26268,	7,	4909},
+	{"cvmx_pcieep#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26270,	11,	4916},
+	{"cvmx_pcieep#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26272,	5,	4927},
+	{"cvmx_pcieep#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26274,	6,	4932},
+	{"cvmx_pcieep#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26276,	19,	4938},
+	{"cvmx_pcieep#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26278,	5,	4957},
+	{"cvmx_pcieep#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26280,	1,	4962},
+	{"cvmx_pcieep#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26282,	1,	4963},
+	{"cvmx_pcieep#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26284,	3,	4964},
+	{"cvmx_pcieep#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26286,	3,	4967},
+	{"cvmx_pcieep#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26288,	3,	4970},
+	{"cvmx_pcieep#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26290,	4,	4973},
+	{"cvmx_pcieep#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26292,	4,	4977},
+	{"cvmx_pcieep#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26294,	4,	4981},
+	{"cvmx_pcieep#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26296,	7,	4985},
+	{"cvmx_pcieep#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26298,	5,	4992},
+	{"cvmx_pcieep#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26300,	5,	4997},
+	{"cvmx_pcieep#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26302,	4,	5002},
+	{"cvmx_pcieep#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26304,	4,	5006},
+	{"cvmx_pcieep#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26306,	4,	5010},
+	{"cvmx_pcieep#_cfg515"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26308,	7,	5014},
+	{"cvmx_pcieep#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26310,	1,	5021},
+	{"cvmx_pcieep#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	26312,	1,	5022},
+	{"cvmx_pcierc#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26314,	2,	5023},
+	{"cvmx_pcierc#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26316,	24,	5025},
+	{"cvmx_pcierc#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26318,	4,	5049},
+	{"cvmx_pcierc#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26320,	5,	5053},
+	{"cvmx_pcierc#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26322,	1,	5058},
+	{"cvmx_pcierc#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26324,	1,	5059},
+	{"cvmx_pcierc#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26326,	4,	5060},
+	{"cvmx_pcierc#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26328,	17,	5064},
+	{"cvmx_pcierc#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26330,	4,	5081},
+	{"cvmx_pcierc#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26332,	6,	5085},
+	{"cvmx_pcierc#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26334,	1,	5091},
+	{"cvmx_pcierc#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26336,	1,	5092},
+	{"cvmx_pcierc#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26338,	2,	5093},
+	{"cvmx_pcierc#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26340,	2,	5095},
+	{"cvmx_pcierc#_cfg014"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26342,	1,	5097},
+	{"cvmx_pcierc#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26344,	15,	5098},
+	{"cvmx_pcierc#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26346,	10,	5113},
+	{"cvmx_pcierc#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26348,	12,	5123},
+	{"cvmx_pcierc#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26350,	7,	5135},
+	{"cvmx_pcierc#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26352,	2,	5142},
+	{"cvmx_pcierc#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26354,	1,	5144},
+	{"cvmx_pcierc#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26356,	2,	5145},
+	{"cvmx_pcierc#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26358,	7,	5147},
+	{"cvmx_pcierc#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26360,	11,	5154},
+	{"cvmx_pcierc#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26362,	19,	5165},
+	{"cvmx_pcierc#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26364,	12,	5184},
+	{"cvmx_pcierc#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26366,	20,	5196},
+	{"cvmx_pcierc#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26368,	12,	5216},
+	{"cvmx_pcierc#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26370,	22,	5228},
+	{"cvmx_pcierc#_cfg035"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26372,	8,	5250},
+	{"cvmx_pcierc#_cfg036"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26374,	4,	5258},
+	{"cvmx_pcierc#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26376,	11,	5262},
+	{"cvmx_pcierc#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26378,	8,	5273},
+	{"cvmx_pcierc#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26380,	4,	5281},
+	{"cvmx_pcierc#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26382,	11,	5285},
+	{"cvmx_pcierc#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26384,	1,	5296},
+	{"cvmx_pcierc#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26386,	1,	5297},
+	{"cvmx_pcierc#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26388,	3,	5298},
+	{"cvmx_pcierc#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26390,	16,	5301},
+	{"cvmx_pcierc#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26392,	16,	5317},
+	{"cvmx_pcierc#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26394,	16,	5333},
+	{"cvmx_pcierc#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26396,	9,	5349},
+	{"cvmx_pcierc#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26398,	9,	5358},
+	{"cvmx_pcierc#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26400,	6,	5367},
+	{"cvmx_pcierc#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26402,	1,	5373},
+	{"cvmx_pcierc#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26404,	1,	5374},
+	{"cvmx_pcierc#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26406,	1,	5375},
+	{"cvmx_pcierc#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26408,	1,	5376},
+	{"cvmx_pcierc#_cfg075"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26410,	4,	5377},
+	{"cvmx_pcierc#_cfg076"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26412,	9,	5381},
+	{"cvmx_pcierc#_cfg077"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26414,	2,	5390},
+	{"cvmx_pcierc#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26416,	2,	5392},
+	{"cvmx_pcierc#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26418,	1,	5394},
+	{"cvmx_pcierc#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26420,	6,	5395},
+	{"cvmx_pcierc#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26422,	7,	5401},
+	{"cvmx_pcierc#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26424,	11,	5408},
+	{"cvmx_pcierc#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26426,	5,	5419},
+	{"cvmx_pcierc#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26428,	6,	5424},
+	{"cvmx_pcierc#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26430,	19,	5430},
+	{"cvmx_pcierc#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26432,	5,	5449},
+	{"cvmx_pcierc#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26434,	1,	5454},
+	{"cvmx_pcierc#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26436,	1,	5455},
+	{"cvmx_pcierc#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26438,	3,	5456},
+	{"cvmx_pcierc#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26440,	3,	5459},
+	{"cvmx_pcierc#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26442,	3,	5462},
+	{"cvmx_pcierc#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26444,	4,	5465},
+	{"cvmx_pcierc#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26446,	4,	5469},
+	{"cvmx_pcierc#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26448,	4,	5473},
+	{"cvmx_pcierc#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26450,	7,	5477},
+	{"cvmx_pcierc#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26452,	5,	5484},
+	{"cvmx_pcierc#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26454,	5,	5489},
+	{"cvmx_pcierc#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26456,	4,	5494},
+	{"cvmx_pcierc#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26458,	4,	5498},
+	{"cvmx_pcierc#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26460,	4,	5502},
+	{"cvmx_pcierc#_cfg515"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26462,	7,	5506},
+	{"cvmx_pcierc#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26464,	1,	5513},
+	{"cvmx_pcierc#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	26466,	1,	5514},
+	{"cvmx_pcs#_an#_adv_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26468,	9,	5515},
+	{"cvmx_pcs#_an#_ext_st_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26488,	6,	5524},
+	{"cvmx_pcs#_an#_lp_abil_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	26508,	9,	5530},
+	{"cvmx_pcs#_an#_results_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	26528,	6,	5539},
+	{"cvmx_pcs#_int#_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26548,	14,	5545},
+	{"cvmx_pcs#_int#_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26568,	14,	5559},
+	{"cvmx_pcs#_link#_timer_count_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	26588,	2,	5573},
+	{"cvmx_pcs#_log_anl#_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26608,	4,	5575},
+	{"cvmx_pcs#_misc#_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	26628,	8,	5579},
+	{"cvmx_pcs#_mr#_control_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	26648,	13,	5587},
+	{"cvmx_pcs#_mr#_status_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26668,	17,	5600},
+	{"cvmx_pcs#_rx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26688,	7,	5617},
+	{"cvmx_pcs#_rx#_sync_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26708,	3,	5624},
+	{"cvmx_pcs#_sgm#_an_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	26728,	8,	5627},
+	{"cvmx_pcs#_sgm#_lp_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	26748,	7,	5635},
+	{"cvmx_pcs#_tx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26768,	4,	5642},
+	{"cvmx_pcs#_tx_rx#_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	26788,	5,	5646},
+	{"cvmx_pcsx#_10gbx_status_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	26808,	8,	5651},
+	{"cvmx_pcsx#_bist_status_reg"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	26813,	2,	5659},
+	{"cvmx_pcsx#_bit_lock_status_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	26818,	5,	5661},
+	{"cvmx_pcsx#_control1_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	26823,	10,	5666},
+	{"cvmx_pcsx#_control2_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	26828,	2,	5676},
+	{"cvmx_pcsx#_int_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26833,	8,	5678},
+	{"cvmx_pcsx#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26838,	8,	5686},
+	{"cvmx_pcsx#_log_anl_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26843,	6,	5694},
+	{"cvmx_pcsx#_misc_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	26848,	5,	5700},
+	{"cvmx_pcsx#_rx_sync_states_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	26853,	5,	5705},
+	{"cvmx_pcsx#_spd_abil_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	26858,	3,	5710},
+	{"cvmx_pcsx#_status1_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26863,	6,	5713},
+	{"cvmx_pcsx#_status2_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26868,	9,	5719},
+	{"cvmx_pcsx#_tx_rx_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	26873,	5,	5728},
+	{"cvmx_pcsx#_tx_rx_states_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	26878,	10,	5733},
+	{"cvmx_pem#_bar1_index#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26883,	5,	5743},
+	{"cvmx_pem#_bar2_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	26915,	3,	5748},
+	{"cvmx_pem#_bar_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26917,	5,	5751},
+	{"cvmx_pem#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26919,	9,	5756},
+	{"cvmx_pem#_bist_status2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26921,	11,	5765},
+	{"cvmx_pem#_cfg_rd"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	26923,	2,	5776},
+	{"cvmx_pem#_cfg_wr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	26925,	2,	5778},
+	{"cvmx_pem#_cpl_lut_valid"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	26927,	2,	5780},
+	{"cvmx_pem#_ctl_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	26929,	18,	5782},
+	{"cvmx_pem#_dbg_info"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	26931,	32,	5800},
+	{"cvmx_pem#_dbg_info_en"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26933,	32,	5832},
+	{"cvmx_pem#_diag_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26935,	5,	5864},
+	{"cvmx_pem#_inb_read_credits"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	26937,	2,	5869},
+	{"cvmx_pem#_int_enb"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26939,	15,	5871},
+	{"cvmx_pem#_int_enb_int"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26941,	15,	5886},
+	{"cvmx_pem#_int_sum"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	26943,	15,	5901},
+	{"cvmx_pem#_p2n_bar0_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26945,	2,	5916},
+	{"cvmx_pem#_p2n_bar1_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26947,	2,	5918},
+	{"cvmx_pem#_p2n_bar2_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26949,	2,	5920},
+	{"cvmx_pem#_p2p_bar#_end"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26951,	2,	5922},
+	{"cvmx_pem#_p2p_bar#_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26959,	2,	5924},
+	{"cvmx_pem#_tlp_credits"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26967,	8,	5926},
+	{"cvmx_pip_alt_skip_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26969,	12,	5934},
+	{"cvmx_pip_bck_prs"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	26973,	5,	5946},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	26974,	2,	5951},
+	{"cvmx_pip_bsel_ext_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26975,	7,	5953},
+	{"cvmx_pip_bsel_ext_pos#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26979,	16,	5960},
+	{"cvmx_pip_bsel_tbl_ent#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	26983,	12,	5976},
+	{"cvmx_pip_clken"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	27495,	2,	5988},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	27496,	4,	5990},
+	{"cvmx_pip_dsa_src_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	27500,	16,	5994},
+	{"cvmx_pip_dsa_vid_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	27501,	16,	6010},
+	{"cvmx_pip_frm_len_chk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	27502,	3,	6026},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	27504,	8,	6029},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	27505,	22,	6037},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	27506,	14,	6059},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	27507,	14,	6073},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	27508,	2,	6087},
+	{"cvmx_pip_pri_tbl#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	27509,	15,	6089},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	27765,	30,	6104},
+	{"cvmx_pip_prt_cfgb#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	27829,	10,	6134},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	27893,	33,	6144},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	27957,	9,	6177},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	27965,	2,	6186},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	27966,	2,	6188},
+	{"cvmx_pip_stat0_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	27967,	2,	6190},
+	{"cvmx_pip_stat10_#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	28031,	2,	6192},
+	{"cvmx_pip_stat11_#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	28095,	2,	6194},
+	{"cvmx_pip_stat1_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	28159,	2,	6196},
+	{"cvmx_pip_stat2_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	28223,	2,	6198},
+	{"cvmx_pip_stat3_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	28287,	2,	6200},
+	{"cvmx_pip_stat4_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	28351,	2,	6202},
+	{"cvmx_pip_stat5_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	28415,	2,	6204},
+	{"cvmx_pip_stat6_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	28479,	2,	6206},
+	{"cvmx_pip_stat7_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	28543,	2,	6208},
+	{"cvmx_pip_stat8_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	28607,	2,	6210},
+	{"cvmx_pip_stat9_#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	28671,	2,	6212},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	28735,	4,	6214},
+	{"cvmx_pip_stat_inb_errs_pknd#",	CVMX_CSR_DB_TYPE_RSL,	64,	28736,	2,	6218},
+	{"cvmx_pip_stat_inb_octs_pknd#",	CVMX_CSR_DB_TYPE_RSL,	64,	28800,	2,	6220},
+	{"cvmx_pip_stat_inb_pkts_pknd#",	CVMX_CSR_DB_TYPE_RSL,	64,	28864,	2,	6222},
+	{"cvmx_pip_sub_pkind_fcs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	28928,	1,	6224},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	28929,	2,	6225},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	28993,	2,	6227},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28994,	3,	6229},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28995,	3,	6232},
+	{"cvmx_pip_vlan_etypes#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	28996,	4,	6235},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28998,	2,	6239},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	28999,	2,	6241},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29000,	4,	6243},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29001,	5,	6247},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	29002,	4,	6252},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	29003,	8,	6256},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	29004,	1,	6264},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	29005,	1,	6265},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29006,	5,	6266},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29007,	1,	6271},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29008,	13,	6272},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29009,	7,	6285},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29010,	13,	6292},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29011,	6,	6305},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29012,	9,	6311},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29013,	4,	6320},
+	{"cvmx_pko_mem_iport_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	29014,	13,	6324},
+	{"cvmx_pko_mem_iport_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	29015,	6,	6337},
+	{"cvmx_pko_mem_iqueue_ptrs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	29016,	10,	6343},
+	{"cvmx_pko_mem_iqueue_qos"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	29017,	5,	6353},
+	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	29018,	5,	6358},
+	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	29019,	4,	6363},
+	{"cvmx_pko_mem_throttle_int"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	29020,	6,	6367},
+	{"cvmx_pko_mem_throttle_pipe"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	29021,	6,	6373},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	29022,	20,	6379},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	29023,	4,	6399},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29024,	1,	6403},
+	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29025,	1,	6404},
+	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29026,	1,	6405},
+	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29027,	1,	6406},
+	{"cvmx_pko_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29028,	1,	6407},
+	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	29029,	16,	6408},
+	{"cvmx_pko_reg_engine_inflight1",	CVMX_CSR_DB_TYPE_RSL,	64,	29030,	5,	6424},
+	{"cvmx_pko_reg_engine_storage#",	CVMX_CSR_DB_TYPE_RSL,	64,	29031,	16,	6429},
+	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	29033,	2,	6445},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	29034,	5,	6447},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	29035,	10,	6452},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	29036,	5,	6462},
+	{"cvmx_pko_reg_loopback_bpid"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	29037,	17,	6467},
+	{"cvmx_pko_reg_loopback_pkind" ,	CVMX_CSR_DB_TYPE_RSL,	64,	29038,	17,	6484},
+	{"cvmx_pko_reg_min_pkt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	29039,	8,	6501},
+	{"cvmx_pko_reg_preempt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	29040,	2,	6509},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	29041,	2,	6511},
+	{"cvmx_pko_reg_queue_preempt"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	29042,	3,	6513},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	29043,	3,	6516},
+	{"cvmx_pko_reg_throttle"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	29044,	2,	6519},
+	{"cvmx_pko_reg_timestamp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	29045,	2,	6521},
+	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29046,	1,	6523},
+	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29047,	1,	6524},
+	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29048,	1,	6525},
+	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	29049,	5,	6526},
+	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	29050,	5,	6531},
+	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29051,	4,	6536},
+	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29052,	10,	6540},
+	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29053,	1,	6550},
+	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	29054,	3,	6551},
+	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	29055,	7,	6554},
+	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	29056,	2,	6561},
+	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29057,	1,	6563},
+	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29058,	1,	6564},
+	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29059,	1,	6565},
+	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29060,	18,	6566},
+	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29061,	3,	6584},
+	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29062,	2,	6587},
+	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29063,	3,	6589},
+	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29064,	7,	6592},
+	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	29065,	2,	6599},
+	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	29066,	2,	6601},
+	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	29067,	2,	6603},
+	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	29068,	3,	6605},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	29069,	3,	6608},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29070,	9,	6611},
+	{"cvmx_rnm_eer_dbg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29071,	1,	6620},
+	{"cvmx_rnm_eer_key"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29072,	1,	6621},
+	{"cvmx_rnm_serial_num"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29073,	1,	6622},
+	{"cvmx_sli_bist_status"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29074,	26,	6623},
+	{"cvmx_sli_ctl_port#"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29075,	16,	6649},
+	{"cvmx_sli_ctl_status"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29077,	4,	6665},
+	{"cvmx_sli_data_out_cnt"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29078,	5,	6669},
+	{"cvmx_sli_dbg_data"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29079,	3,	6674},
+	{"cvmx_sli_dbg_select"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29080,	3,	6677},
+	{"cvmx_sli_dma#_cnt"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29081,	2,	6680},
+	{"cvmx_sli_dma#_int_level"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29083,	2,	6682},
+	{"cvmx_sli_dma#_tim"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29085,	2,	6684},
+	{"cvmx_sli_int_enb_ciu"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29087,	36,	6686},
+	{"cvmx_sli_int_enb_port#"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29088,	38,	6722},
+	{"cvmx_sli_int_sum"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29090,	38,	6760},
+	{"cvmx_sli_last_win_rdata0"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29091,	1,	6798},
+	{"cvmx_sli_last_win_rdata1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29092,	1,	6799},
+	{"cvmx_sli_mac_credit_cnt"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29093,	13,	6800},
+	{"cvmx_sli_mac_number"         ,	CVMX_CSR_DB_TYPE_PEXP,	64,	29094,	2,	6813},
+	{"cvmx_sli_mem_access_ctl"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29095,	3,	6815},
+	{"cvmx_sli_mem_access_subid#"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29096,	10,	6818},
+	{"cvmx_sli_msi_enb0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29112,	1,	6828},
+	{"cvmx_sli_msi_enb1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29113,	1,	6829},
+	{"cvmx_sli_msi_enb2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29114,	1,	6830},
+	{"cvmx_sli_msi_enb3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29115,	1,	6831},
+	{"cvmx_sli_msi_rcv0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29116,	1,	6832},
+	{"cvmx_sli_msi_rcv1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29117,	1,	6833},
+	{"cvmx_sli_msi_rcv2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29118,	1,	6834},
+	{"cvmx_sli_msi_rcv3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29119,	1,	6835},
+	{"cvmx_sli_msi_rd_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29120,	3,	6836},
+	{"cvmx_sli_msi_w1c_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29121,	1,	6839},
+	{"cvmx_sli_msi_w1c_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29122,	1,	6840},
+	{"cvmx_sli_msi_w1c_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29123,	1,	6841},
+	{"cvmx_sli_msi_w1c_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29124,	1,	6842},
+	{"cvmx_sli_msi_w1s_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29125,	1,	6843},
+	{"cvmx_sli_msi_w1s_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29126,	1,	6844},
+	{"cvmx_sli_msi_w1s_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29127,	1,	6845},
+	{"cvmx_sli_msi_w1s_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29128,	1,	6846},
+	{"cvmx_sli_msi_wr_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29129,	3,	6847},
+	{"cvmx_sli_pcie_msi_rcv"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29130,	2,	6850},
+	{"cvmx_sli_pcie_msi_rcv_b1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29131,	3,	6852},
+	{"cvmx_sli_pcie_msi_rcv_b2"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29132,	3,	6855},
+	{"cvmx_sli_pcie_msi_rcv_b3"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29133,	3,	6858},
+	{"cvmx_sli_pkt#_cnts"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29134,	3,	6861},
+	{"cvmx_sli_pkt#_instr_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29166,	2,	6864},
+	{"cvmx_sli_pkt#_instr_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29198,	2,	6866},
+	{"cvmx_sli_pkt#_instr_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29230,	5,	6868},
+	{"cvmx_sli_pkt#_instr_header"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29262,	21,	6873},
+	{"cvmx_sli_pkt#_out_size"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29294,	3,	6894},
+	{"cvmx_sli_pkt#_slist_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29326,	2,	6897},
+	{"cvmx_sli_pkt#_slist_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29358,	2,	6899},
+	{"cvmx_sli_pkt#_slist_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29390,	2,	6901},
+	{"cvmx_sli_pkt_cnt_int"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29422,	2,	6903},
+	{"cvmx_sli_pkt_cnt_int_enb"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29423,	2,	6905},
+	{"cvmx_sli_pkt_ctl"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29424,	3,	6907},
+	{"cvmx_sli_pkt_data_out_es"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29425,	1,	6910},
+	{"cvmx_sli_pkt_data_out_ns"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29426,	2,	6911},
+	{"cvmx_sli_pkt_data_out_ror"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29427,	2,	6913},
+	{"cvmx_sli_pkt_dpaddr"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29428,	2,	6915},
+	{"cvmx_sli_pkt_in_done#_cnts"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29429,	2,	6917},
+	{"cvmx_sli_pkt_in_instr_counts",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29461,	2,	6919},
+	{"cvmx_sli_pkt_in_pcie_port"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29462,	1,	6921},
+	{"cvmx_sli_pkt_input_control"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29463,	17,	6922},
+	{"cvmx_sli_pkt_instr_enb"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29464,	2,	6939},
+	{"cvmx_sli_pkt_instr_rd_size"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29465,	1,	6941},
+	{"cvmx_sli_pkt_instr_size"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29466,	2,	6942},
+	{"cvmx_sli_pkt_int_levels"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29467,	3,	6944},
+	{"cvmx_sli_pkt_iptr"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29468,	2,	6947},
+	{"cvmx_sli_pkt_out_bmode"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29469,	2,	6949},
+	{"cvmx_sli_pkt_out_bp_en"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29470,	2,	6951},
+	{"cvmx_sli_pkt_out_enb"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29471,	2,	6953},
+	{"cvmx_sli_pkt_output_wmark"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29472,	2,	6955},
+	{"cvmx_sli_pkt_pcie_port"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29473,	1,	6957},
+	{"cvmx_sli_pkt_port_in_rst"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29474,	2,	6958},
+	{"cvmx_sli_pkt_slist_es"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29475,	1,	6960},
+	{"cvmx_sli_pkt_slist_ns"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29476,	2,	6961},
+	{"cvmx_sli_pkt_slist_ror"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29477,	2,	6963},
+	{"cvmx_sli_pkt_time_int"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29478,	2,	6965},
+	{"cvmx_sli_pkt_time_int_enb"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29479,	2,	6967},
+	{"cvmx_sli_port#_pkind"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29480,	8,	6969},
+	{"cvmx_sli_s2m_port#_ctl"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29512,	4,	6977},
+	{"cvmx_sli_scratch_1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29514,	1,	6981},
+	{"cvmx_sli_scratch_2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29515,	1,	6982},
+	{"cvmx_sli_state1"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29516,	4,	6983},
+	{"cvmx_sli_state2"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29517,	8,	6987},
+	{"cvmx_sli_state3"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29518,	5,	6995},
+	{"cvmx_sli_tx_pipe"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29519,	4,	7000},
+	{"cvmx_sli_win_rd_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	29520,	4,	7004},
+	{"cvmx_sli_win_rd_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	29521,	1,	7008},
+	{"cvmx_sli_win_wr_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	29522,	4,	7009},
+	{"cvmx_sli_win_wr_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	29523,	1,	7013},
+	{"cvmx_sli_win_wr_mask"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	29524,	2,	7014},
+	{"cvmx_sli_window_ctl"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	29525,	2,	7016},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	29526,	10,	7018},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	29530,	6,	7028},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	29534,	2,	7034},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29538,	4,	7036},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29542,	4,	7040},
+	{"cvmx_smi_drv_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29546,	4,	7044},
+	{"cvmx_sso_active_cycles"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	29547,	1,	7048},
+	{"cvmx_sso_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	29548,	21,	7049},
+	{"cvmx_sso_cfg"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	29549,	15,	7070},
+	{"cvmx_sso_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	29550,	1,	7085},
+	{"cvmx_sso_err"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	29551,	19,	7086},
+	{"cvmx_sso_err_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	29552,	19,	7105},
+	{"cvmx_sso_fidx_ecc_ctl"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	29553,	3,	7124},
+	{"cvmx_sso_fidx_ecc_st"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	29554,	5,	7127},
+	{"cvmx_sso_fpage_cnt"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	29555,	2,	7132},
+	{"cvmx_sso_gwe_cfg"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	29556,	11,	7134},
+	{"cvmx_sso_idx_ecc_ctl"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	29557,	3,	7145},
+	{"cvmx_sso_idx_ecc_st"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	29558,	5,	7148},
+	{"cvmx_sso_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	29559,	2,	7153},
+	{"cvmx_sso_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	29567,	2,	7155},
+	{"cvmx_sso_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	29568,	2,	7157},
+	{"cvmx_sso_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	29569,	2,	7159},
+	{"cvmx_sso_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	29570,	2,	7161},
+	{"cvmx_sso_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	29578,	2,	7163},
+	{"cvmx_sso_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	29579,	2,	7165},
+	{"cvmx_sso_oth_ecc_ctl"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	29580,	5,	7167},
+	{"cvmx_sso_oth_ecc_st"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	29581,	9,	7172},
+	{"cvmx_sso_pnd_ecc_ctl"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	29582,	5,	7181},
+	{"cvmx_sso_pnd_ecc_st"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	29583,	9,	7186},
+	{"cvmx_sso_pp#_grp_msk"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	29584,	1,	7195},
+	{"cvmx_sso_pp#_qos_pri"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	29616,	16,	7196},
+	{"cvmx_sso_pp_strict"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	29648,	2,	7212},
+	{"cvmx_sso_qos#_rnd"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	29649,	2,	7214},
+	{"cvmx_sso_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	29657,	6,	7216},
+	{"cvmx_sso_qos_we"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	29665,	4,	7222},
+	{"cvmx_sso_reset"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	29666,	2,	7226},
+	{"cvmx_sso_rwq_head_ptr#"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	29667,	4,	7228},
+	{"cvmx_sso_rwq_pop_fptr"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	29675,	5,	7232},
+	{"cvmx_sso_rwq_psh_fptr"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	29676,	5,	7237},
+	{"cvmx_sso_rwq_tail_ptr#"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	29677,	4,	7242},
+	{"cvmx_sso_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	29685,	1,	7246},
+	{"cvmx_sso_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	29686,	1,	7247},
+	{"cvmx_sso_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	29687,	1,	7248},
+	{"cvmx_sso_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	29695,	1,	7249},
+	{"cvmx_sso_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	29696,	6,	7250},
+	{"cvmx_sso_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	29760,	5,	7256},
+	{"cvmx_sso_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	29761,	7,	7261},
+	{"cvmx_sso_wq_iq_dis"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	29825,	1,	7268},
+	{"cvmx_sso_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	29826,	1,	7269},
+	{"cvmx_tim_bist_result"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	29890,	4,	7270},
+	{"cvmx_tim_dbg2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	29891,	11,	7274},
+	{"cvmx_tim_dbg3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	29892,	1,	7285},
+	{"cvmx_tim_ecc_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29893,	3,	7286},
+	{"cvmx_tim_fr_rn_tt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	29894,	4,	7289},
+	{"cvmx_tim_gpio_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29895,	1,	7293},
+	{"cvmx_tim_int0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	29896,	1,	7294},
+	{"cvmx_tim_int0_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	29897,	1,	7295},
+	{"cvmx_tim_int0_event"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29898,	2,	7296},
+	{"cvmx_tim_int_eccerr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29899,	3,	7298},
+	{"cvmx_tim_int_eccerr_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	29900,	3,	7301},
+	{"cvmx_tim_int_eccerr_event0"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	29901,	3,	7304},
+	{"cvmx_tim_int_eccerr_event1"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	29902,	3,	7307},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	29903,	7,	7310},
+	{"cvmx_tim_ring#_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29904,	5,	7317},
+	{"cvmx_tim_ring#_ctl1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	29968,	8,	7322},
+	{"cvmx_tim_ring#_ctl2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	30032,	4,	7330},
+	{"cvmx_tim_ring#_dbg0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	30096,	3,	7334},
+	{"cvmx_tim_ring#_dbg1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	30160,	2,	7337},
+	{"cvmx_tra#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	30224,	2,	7339},
+	{"cvmx_tra#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	30228,	14,	7341},
+	{"cvmx_tra#_cycles_since"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	30232,	3,	7355},
+	{"cvmx_tra#_cycles_since1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	30236,	5,	7358},
+	{"cvmx_tra#_filt_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	30240,	2,	7363},
+	{"cvmx_tra#_filt_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	30244,	2,	7365},
+	{"cvmx_tra#_filt_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	30248,	57,	7367},
+	{"cvmx_tra#_filt_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	30252,	20,	7424},
+	{"cvmx_tra#_filt_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	30256,	7,	7444},
+	{"cvmx_tra#_int_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	30260,	5,	7451},
+	{"cvmx_tra#_read_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	30264,	1,	7456},
+	{"cvmx_tra#_read_dat_hi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	30268,	2,	7457},
+	{"cvmx_tra#_trig0_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	30272,	2,	7459},
+	{"cvmx_tra#_trig0_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	30276,	2,	7461},
+	{"cvmx_tra#_trig0_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	30280,	57,	7463},
+	{"cvmx_tra#_trig0_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	30284,	20,	7520},
+	{"cvmx_tra#_trig0_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	30288,	7,	7540},
+	{"cvmx_tra#_trig1_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	30292,	2,	7547},
+	{"cvmx_tra#_trig1_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	30296,	2,	7549},
+	{"cvmx_tra#_trig1_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	30300,	57,	7551},
+	{"cvmx_tra#_trig1_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	30304,	20,	7608},
+	{"cvmx_tra#_trig1_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	30308,	7,	7628},
+	{"cvmx_uahc#_ehci_asynclistaddr",	CVMX_CSR_DB_TYPE_NCB,	32,	30312,	2,	7635},
+	{"cvmx_uahc#_ehci_configflag"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	30313,	2,	7637},
+	{"cvmx_uahc#_ehci_ctrldssegment",	CVMX_CSR_DB_TYPE_NCB,	32,	30314,	1,	7639},
+	{"cvmx_uahc#_ehci_frindex"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	30315,	2,	7640},
+	{"cvmx_uahc#_ehci_hccapbase"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	30316,	3,	7642},
+	{"cvmx_uahc#_ehci_hccparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	30317,	7,	7645},
+	{"cvmx_uahc#_ehci_hcsparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	30318,	10,	7652},
+	{"cvmx_uahc#_ehci_insnreg00"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	30319,	3,	7662},
+	{"cvmx_uahc#_ehci_insnreg03"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	30320,	5,	7665},
+	{"cvmx_uahc#_ehci_insnreg04"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	30321,	7,	7670},
+	{"cvmx_uahc#_ehci_insnreg06"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	30322,	2,	7677},
+	{"cvmx_uahc#_ehci_insnreg07"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	30323,	1,	7679},
+	{"cvmx_uahc#_ehci_periodiclistbase",	CVMX_CSR_DB_TYPE_NCB,	32,	30324,	2,	7680},
+	{"cvmx_uahc#_ehci_portsc#"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	30325,	19,	7682},
+	{"cvmx_uahc#_ehci_usbcmd"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	30327,	13,	7701},
+	{"cvmx_uahc#_ehci_usbintr"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	30328,	7,	7714},
+	{"cvmx_uahc#_ehci_usbsts"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	30329,	12,	7721},
+	{"cvmx_uahc#_ohci0_hcbulkcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	30330,	2,	7733},
+	{"cvmx_uahc#_ohci0_hcbulkheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	30331,	2,	7735},
+	{"cvmx_uahc#_ohci0_hccommandstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	30332,	7,	7737},
+	{"cvmx_uahc#_ohci0_hccontrol"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	30333,	10,	7744},
+	{"cvmx_uahc#_ohci0_hccontrolcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	30334,	2,	7754},
+	{"cvmx_uahc#_ohci0_hccontrolheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	30335,	2,	7756},
+	{"cvmx_uahc#_ohci0_hcdonehead" ,	CVMX_CSR_DB_TYPE_NCB,	32,	30336,	2,	7758},
+	{"cvmx_uahc#_ohci0_hcfminterval",	CVMX_CSR_DB_TYPE_NCB,	32,	30337,	4,	7760},
+	{"cvmx_uahc#_ohci0_hcfmnumber" ,	CVMX_CSR_DB_TYPE_NCB,	32,	30338,	2,	7764},
+	{"cvmx_uahc#_ohci0_hcfmremaining",	CVMX_CSR_DB_TYPE_NCB,	32,	30339,	3,	7766},
+	{"cvmx_uahc#_ohci0_hchcca"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	30340,	2,	7769},
+	{"cvmx_uahc#_ohci0_hcinterruptdisable",	CVMX_CSR_DB_TYPE_NCB,	32,	30341,	10,	7771},
+	{"cvmx_uahc#_ohci0_hcinterruptenable",	CVMX_CSR_DB_TYPE_NCB,	32,	30342,	10,	7781},
+	{"cvmx_uahc#_ohci0_hcinterruptstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	30343,	10,	7791},
+	{"cvmx_uahc#_ohci0_hclsthreshold",	CVMX_CSR_DB_TYPE_NCB,	32,	30344,	2,	7801},
+	{"cvmx_uahc#_ohci0_hcperiodcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	30345,	2,	7803},
+	{"cvmx_uahc#_ohci0_hcperiodicstart",	CVMX_CSR_DB_TYPE_NCB,	32,	30346,	2,	7805},
+	{"cvmx_uahc#_ohci0_hcrevision" ,	CVMX_CSR_DB_TYPE_NCB,	32,	30347,	2,	7807},
+	{"cvmx_uahc#_ohci0_hcrhdescriptora",	CVMX_CSR_DB_TYPE_NCB,	32,	30348,	8,	7809},
+	{"cvmx_uahc#_ohci0_hcrhdescriptorb",	CVMX_CSR_DB_TYPE_NCB,	32,	30349,	2,	7817},
+	{"cvmx_uahc#_ohci0_hcrhportstatus#",	CVMX_CSR_DB_TYPE_NCB,	32,	30350,	15,	7819},
+	{"cvmx_uahc#_ohci0_hcrhstatus" ,	CVMX_CSR_DB_TYPE_NCB,	32,	30352,	8,	7834},
+	{"cvmx_uahc#_ohci0_insnreg06"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	30353,	2,	7842},
+	{"cvmx_uahc#_ohci0_insnreg07"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	30354,	1,	7844},
+	{"cvmx_uctl#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	30355,	7,	7845},
+	{"cvmx_uctl#_clk_rst_ctl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	30356,	21,	7852},
+	{"cvmx_uctl#_ehci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	30357,	12,	7873},
+	{"cvmx_uctl#_ehci_fla"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	30358,	2,	7885},
+	{"cvmx_uctl#_erto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	30359,	3,	7887},
+	{"cvmx_uctl#_if_ena"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	30360,	2,	7890},
+	{"cvmx_uctl#_int_ena"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	30361,	9,	7892},
+	{"cvmx_uctl#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	30362,	9,	7901},
+	{"cvmx_uctl#_ohci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	30363,	11,	7910},
+	{"cvmx_uctl#_orto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	30364,	3,	7921},
+	{"cvmx_uctl#_uphy_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	30365,	11,	7924},
+	{"cvmx_uctl#_uphy_port#_ctl_status",	CVMX_CSR_DB_TYPE_RSL,	64,	30366,	20,	7935},
+	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	30368,	3,	7955},
+	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	30369,	5,	7958},
+	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	30370,	3,	7963},
+	{"cvmx_zip_constants"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	30371,	8,	7966},
+	{"cvmx_zip_core#_bist_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	30372,	2,	7974},
+	{"cvmx_zip_ctl_bist_status"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	30374,	2,	7976},
+	{"cvmx_zip_ctl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	30375,	15,	7978},
+	{"cvmx_zip_dbg_core#_inst"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	30376,	4,	7993},
+	{"cvmx_zip_dbg_core#_sta"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	30378,	4,	7997},
+	{"cvmx_zip_dbg_que#_sta"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	30380,	4,	8001},
+	{"cvmx_zip_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	30382,	2,	8005},
+	{"cvmx_zip_ecc_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	30383,	4,	8007},
+	{"cvmx_zip_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	30384,	2,	8011},
+	{"cvmx_zip_int_ena"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	30385,	7,	8013},
+	{"cvmx_zip_int_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	30386,	2,	8020},
+	{"cvmx_zip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	30387,	7,	8022},
+	{"cvmx_zip_que#_buf"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	30388,	5,	8029},
+	{"cvmx_zip_que#_ecc_err_sta"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	30390,	3,	8034},
+	{"cvmx_zip_que#_map"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	30392,	2,	8037},
+	{"cvmx_zip_que_ena"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	30394,	2,	8039},
+	{"cvmx_zip_que_pri"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	30395,	2,	8041},
+	{"cvmx_zip_throttle"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	30396,	2,	8043},
+	{NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn68xx[] = {
+	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
+	{"AGL_GMX_BAD_REG"             ,	   0x11800e0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"AGL_GMX_BIST"                ,	   0x11800e0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"AGL_GMX_PRT0_CFG"            ,	   0x11800e0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"AGL_GMX_RX0_ADR_CAM0"        ,	   0x11800e0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"AGL_GMX_RX0_ADR_CAM1"        ,	   0x11800e0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_RX0_ADR_CAM2"        ,	   0x11800e0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX0_ADR_CAM3"        ,	   0x11800e0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX0_ADR_CAM4"        ,	   0x11800e00001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX0_ADR_CAM5"        ,	   0x11800e00001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX0_ADR_CAM_EN"      ,	   0x11800e0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX0_ADR_CTL"         ,	   0x11800e0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX0_DECISION"        ,	   0x11800e0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX0_FRM_CHK"         ,	   0x11800e0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX0_FRM_CTL"         ,	   0x11800e0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX0_FRM_MAX"         ,	   0x11800e0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX0_FRM_MIN"         ,	   0x11800e0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX0_IFG"             ,	   0x11800e0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX0_INT_EN"          ,	   0x11800e0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX0_INT_REG"         ,	   0x11800e0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX0_JABBER"          ,	   0x11800e0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX0_PAUSE_DROP_TIME" ,	   0x11800e0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX0_RX_INBND"        ,	   0x11800e0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX0_STATS_CTL"       ,	   0x11800e0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX0_STATS_OCTS"      ,	   0x11800e0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX0_STATS_OCTS_CTL"  ,	   0x11800e0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX0_STATS_OCTS_DMAC" ,	   0x11800e00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX0_STATS_OCTS_DRP"  ,	   0x11800e00000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX0_STATS_PKTS"      ,	   0x11800e0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX0_STATS_PKTS_BAD"  ,	   0x11800e00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX0_STATS_PKTS_CTL"  ,	   0x11800e0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX0_STATS_PKTS_DMAC" ,	   0x11800e00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX0_STATS_PKTS_DRP"  ,	   0x11800e00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX0_UDD_SKP"         ,	   0x11800e0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX_BP_DROP0"         ,	   0x11800e0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX_BP_OFF0"          ,	   0x11800e0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_ON0"           ,	   0x11800e0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_PRT_INFO"         ,	   0x11800e00004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"AGL_GMX_RX_TX_STATUS"        ,	   0x11800e00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"AGL_GMX_SMAC0"               ,	   0x11800e0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"AGL_GMX_STAT_BP"             ,	   0x11800e0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"AGL_GMX_TX0_APPEND"          ,	   0x11800e0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"AGL_GMX_TX0_CLK"             ,	   0x11800e0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX0_CTL"             ,	   0x11800e0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX0_MIN_PKT"         ,	   0x11800e0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",	   0x11800e0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,	   0x11800e0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX0_PAUSE_TOGO"      ,	   0x11800e0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX0_PAUSE_ZERO"      ,	   0x11800e0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX0_SOFT_PAUSE"      ,	   0x11800e0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX0_STAT0"           ,	   0x11800e0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX0_STAT1"           ,	   0x11800e0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX0_STAT2"           ,	   0x11800e0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX0_STAT3"           ,	   0x11800e0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX0_STAT4"           ,	   0x11800e00002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX0_STAT5"           ,	   0x11800e00002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX0_STAT6"           ,	   0x11800e00002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX0_STAT7"           ,	   0x11800e00002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX0_STAT8"           ,	   0x11800e00002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX0_STAT9"           ,	   0x11800e00002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX0_STATS_CTL"       ,	   0x11800e0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX0_THRESH"          ,	   0x11800e0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX_BP"               ,	   0x11800e00004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"AGL_GMX_TX_COL_ATTEMPT"      ,	   0x11800e0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"AGL_GMX_TX_IFG"              ,	   0x11800e0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"AGL_GMX_TX_INT_EN"           ,	   0x11800e0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"AGL_GMX_TX_INT_REG"          ,	   0x11800e0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"AGL_GMX_TX_JAM"              ,	   0x11800e0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"AGL_GMX_TX_LFSR"             ,	   0x11800e00004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"AGL_GMX_TX_OVR_BP"           ,	   0x11800e00004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,	   0x11800e00004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,	   0x11800e00004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"AGL_PRT0_CTL"                ,	   0x11800e0002000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"CIU2_ACK_IO0_INT"            ,	   0x10701080c0800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
+	{"CIU2_ACK_IO1_INT"            ,	   0x10701082c0800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
+	{"CIU2_ACK_PP0_IP2"            ,	   0x10701000c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP1_IP2"            ,	   0x10701002c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP2_IP2"            ,	   0x10701004c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP3_IP2"            ,	   0x10701006c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP4_IP2"            ,	   0x10701008c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP5_IP2"            ,	   0x1070100ac0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP6_IP2"            ,	   0x1070100cc0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP7_IP2"            ,	   0x1070100ec0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP8_IP2"            ,	   0x10701010c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP9_IP2"            ,	   0x10701012c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP10_IP2"           ,	   0x10701014c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP11_IP2"           ,	   0x10701016c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP12_IP2"           ,	   0x10701018c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP13_IP2"           ,	   0x1070101ac0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP14_IP2"           ,	   0x1070101cc0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP15_IP2"           ,	   0x1070101ec0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP16_IP2"           ,	   0x10701020c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP17_IP2"           ,	   0x10701022c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP18_IP2"           ,	   0x10701024c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP19_IP2"           ,	   0x10701026c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP20_IP2"           ,	   0x10701028c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP21_IP2"           ,	   0x1070102ac0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP22_IP2"           ,	   0x1070102cc0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP23_IP2"           ,	   0x1070102ec0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP24_IP2"           ,	   0x10701030c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP25_IP2"           ,	   0x10701032c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP26_IP2"           ,	   0x10701034c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP27_IP2"           ,	   0x10701036c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP28_IP2"           ,	   0x10701038c0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP29_IP2"           ,	   0x1070103ac0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP30_IP2"           ,	   0x1070103cc0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP31_IP2"           ,	   0x1070103ec0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU2_ACK_PP0_IP3"            ,	   0x10701000c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP1_IP3"            ,	   0x10701002c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP2_IP3"            ,	   0x10701004c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP3_IP3"            ,	   0x10701006c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP4_IP3"            ,	   0x10701008c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP5_IP3"            ,	   0x1070100ac0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP6_IP3"            ,	   0x1070100cc0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP7_IP3"            ,	   0x1070100ec0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP8_IP3"            ,	   0x10701010c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP9_IP3"            ,	   0x10701012c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP10_IP3"           ,	   0x10701014c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP11_IP3"           ,	   0x10701016c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP12_IP3"           ,	   0x10701018c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP13_IP3"           ,	   0x1070101ac0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP14_IP3"           ,	   0x1070101cc0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP15_IP3"           ,	   0x1070101ec0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP16_IP3"           ,	   0x10701020c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP17_IP3"           ,	   0x10701022c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP18_IP3"           ,	   0x10701024c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP19_IP3"           ,	   0x10701026c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP20_IP3"           ,	   0x10701028c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP21_IP3"           ,	   0x1070102ac0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP22_IP3"           ,	   0x1070102cc0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP23_IP3"           ,	   0x1070102ec0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP24_IP3"           ,	   0x10701030c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP25_IP3"           ,	   0x10701032c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP26_IP3"           ,	   0x10701034c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP27_IP3"           ,	   0x10701036c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP28_IP3"           ,	   0x10701038c0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP29_IP3"           ,	   0x1070103ac0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP30_IP3"           ,	   0x1070103cc0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP31_IP3"           ,	   0x1070103ec0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU2_ACK_PP0_IP4"            ,	   0x10701000c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP1_IP4"            ,	   0x10701002c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP2_IP4"            ,	   0x10701004c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP3_IP4"            ,	   0x10701006c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP4_IP4"            ,	   0x10701008c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP5_IP4"            ,	   0x1070100ac0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP6_IP4"            ,	   0x1070100cc0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP7_IP4"            ,	   0x1070100ec0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP8_IP4"            ,	   0x10701010c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP9_IP4"            ,	   0x10701012c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP10_IP4"           ,	   0x10701014c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP11_IP4"           ,	   0x10701016c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP12_IP4"           ,	   0x10701018c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP13_IP4"           ,	   0x1070101ac0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP14_IP4"           ,	   0x1070101cc0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP15_IP4"           ,	   0x1070101ec0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP16_IP4"           ,	   0x10701020c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP17_IP4"           ,	   0x10701022c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP18_IP4"           ,	   0x10701024c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP19_IP4"           ,	   0x10701026c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP20_IP4"           ,	   0x10701028c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP21_IP4"           ,	   0x1070102ac0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP22_IP4"           ,	   0x1070102cc0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP23_IP4"           ,	   0x1070102ec0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP24_IP4"           ,	   0x10701030c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP25_IP4"           ,	   0x10701032c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP26_IP4"           ,	   0x10701034c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP27_IP4"           ,	   0x10701036c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP28_IP4"           ,	   0x10701038c0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP29_IP4"           ,	   0x1070103ac0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP30_IP4"           ,	   0x1070103cc0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_ACK_PP31_IP4"           ,	   0x1070103ec0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU2_EN_IO0_INT_GPIO"        ,	   0x1070108097800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU2_EN_IO1_INT_GPIO"        ,	   0x1070108297800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU2_EN_IO0_INT_GPIO_W1C"    ,	   0x10701080b7800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU2_EN_IO1_INT_GPIO_W1C"    ,	   0x10701082b7800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU2_EN_IO0_INT_GPIO_W1S"    ,	   0x10701080a7800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU2_EN_IO1_INT_GPIO_W1S"    ,	   0x10701082a7800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU2_EN_IO0_INT_IO"          ,	   0x1070108094800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU2_EN_IO1_INT_IO"          ,	   0x1070108294800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU2_EN_IO0_INT_IO_W1C"      ,	   0x10701080b4800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU2_EN_IO1_INT_IO_W1C"      ,	   0x10701082b4800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU2_EN_IO0_INT_IO_W1S"      ,	   0x10701080a4800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU2_EN_IO1_INT_IO_W1S"      ,	   0x10701082a4800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU2_EN_IO0_INT_MBOX"        ,	   0x1070108098800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU2_EN_IO1_INT_MBOX"        ,	   0x1070108298800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU2_EN_IO0_INT_MBOX_W1C"    ,	   0x10701080b8800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU2_EN_IO1_INT_MBOX_W1C"    ,	   0x10701082b8800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU2_EN_IO0_INT_MBOX_W1S"    ,	   0x10701080a8800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU2_EN_IO1_INT_MBOX_W1S"    ,	   0x10701082a8800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU2_EN_IO0_INT_MEM"         ,	   0x1070108095800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU2_EN_IO1_INT_MEM"         ,	   0x1070108295800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU2_EN_IO0_INT_MEM_W1C"     ,	   0x10701080b5800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU2_EN_IO1_INT_MEM_W1C"     ,	   0x10701082b5800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU2_EN_IO0_INT_MEM_W1S"     ,	   0x10701080a5800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU2_EN_IO1_INT_MEM_W1S"     ,	   0x10701082a5800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU2_EN_IO0_INT_MIO"         ,	   0x1070108093800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU2_EN_IO1_INT_MIO"         ,	   0x1070108293800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU2_EN_IO0_INT_MIO_W1C"     ,	   0x10701080b3800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU2_EN_IO1_INT_MIO_W1C"     ,	   0x10701082b3800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU2_EN_IO0_INT_MIO_W1S"     ,	   0x10701080a3800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU2_EN_IO1_INT_MIO_W1S"     ,	   0x10701082a3800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU2_EN_IO0_INT_PKT"         ,	   0x1070108096800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU2_EN_IO1_INT_PKT"         ,	   0x1070108296800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU2_EN_IO0_INT_PKT_W1C"     ,	   0x10701080b6800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU2_EN_IO1_INT_PKT_W1C"     ,	   0x10701082b6800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU2_EN_IO0_INT_PKT_W1S"     ,	   0x10701080a6800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU2_EN_IO1_INT_PKT_W1S"     ,	   0x10701082a6800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU2_EN_IO0_INT_RML"         ,	   0x1070108092800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU2_EN_IO1_INT_RML"         ,	   0x1070108292800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU2_EN_IO0_INT_RML_W1C"     ,	   0x10701080b2800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU2_EN_IO1_INT_RML_W1C"     ,	   0x10701082b2800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU2_EN_IO0_INT_RML_W1S"     ,	   0x10701080a2800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU2_EN_IO1_INT_RML_W1S"     ,	   0x10701082a2800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU2_EN_IO0_INT_WDOG"        ,	   0x1070108091800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU2_EN_IO1_INT_WDOG"        ,	   0x1070108291800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU2_EN_IO0_INT_WDOG_W1C"    ,	   0x10701080b1800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU2_EN_IO1_INT_WDOG_W1C"    ,	   0x10701082b1800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU2_EN_IO0_INT_WDOG_W1S"    ,	   0x10701080a1800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU2_EN_IO1_INT_WDOG_W1S"    ,	   0x10701082a1800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU2_EN_IO0_INT_WRKQ"        ,	   0x1070108090800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU2_EN_IO1_INT_WRKQ"        ,	   0x1070108290800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU2_EN_IO0_INT_WRKQ_W1C"    ,	   0x10701080b0800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU2_EN_IO1_INT_WRKQ_W1C"    ,	   0x10701082b0800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU2_EN_IO0_INT_WRKQ_W1S"    ,	   0x10701080a0800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU2_EN_IO1_INT_WRKQ_W1S"    ,	   0x10701082a0800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU2_EN_PP0_IP2_GPIO"        ,	   0x1070100097000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP1_IP2_GPIO"        ,	   0x1070100297000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP2_IP2_GPIO"        ,	   0x1070100497000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP3_IP2_GPIO"        ,	   0x1070100697000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP4_IP2_GPIO"        ,	   0x1070100897000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP5_IP2_GPIO"        ,	   0x1070100a97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP6_IP2_GPIO"        ,	   0x1070100c97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP7_IP2_GPIO"        ,	   0x1070100e97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP8_IP2_GPIO"        ,	   0x1070101097000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP9_IP2_GPIO"        ,	   0x1070101297000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP10_IP2_GPIO"       ,	   0x1070101497000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP11_IP2_GPIO"       ,	   0x1070101697000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP12_IP2_GPIO"       ,	   0x1070101897000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP13_IP2_GPIO"       ,	   0x1070101a97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP14_IP2_GPIO"       ,	   0x1070101c97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP15_IP2_GPIO"       ,	   0x1070101e97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP16_IP2_GPIO"       ,	   0x1070102097000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP17_IP2_GPIO"       ,	   0x1070102297000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP18_IP2_GPIO"       ,	   0x1070102497000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP19_IP2_GPIO"       ,	   0x1070102697000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP20_IP2_GPIO"       ,	   0x1070102897000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP21_IP2_GPIO"       ,	   0x1070102a97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP22_IP2_GPIO"       ,	   0x1070102c97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP23_IP2_GPIO"       ,	   0x1070102e97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP24_IP2_GPIO"       ,	   0x1070103097000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP25_IP2_GPIO"       ,	   0x1070103297000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP26_IP2_GPIO"       ,	   0x1070103497000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP27_IP2_GPIO"       ,	   0x1070103697000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP28_IP2_GPIO"       ,	   0x1070103897000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP29_IP2_GPIO"       ,	   0x1070103a97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP30_IP2_GPIO"       ,	   0x1070103c97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP31_IP2_GPIO"       ,	   0x1070103e97000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU2_EN_PP0_IP2_GPIO_W1C"    ,	   0x10701000b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP1_IP2_GPIO_W1C"    ,	   0x10701002b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP2_IP2_GPIO_W1C"    ,	   0x10701004b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP3_IP2_GPIO_W1C"    ,	   0x10701006b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP4_IP2_GPIO_W1C"    ,	   0x10701008b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP5_IP2_GPIO_W1C"    ,	   0x1070100ab7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP6_IP2_GPIO_W1C"    ,	   0x1070100cb7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP7_IP2_GPIO_W1C"    ,	   0x1070100eb7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP8_IP2_GPIO_W1C"    ,	   0x10701010b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP9_IP2_GPIO_W1C"    ,	   0x10701012b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP10_IP2_GPIO_W1C"   ,	   0x10701014b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP11_IP2_GPIO_W1C"   ,	   0x10701016b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP12_IP2_GPIO_W1C"   ,	   0x10701018b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP13_IP2_GPIO_W1C"   ,	   0x1070101ab7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP14_IP2_GPIO_W1C"   ,	   0x1070101cb7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP15_IP2_GPIO_W1C"   ,	   0x1070101eb7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP16_IP2_GPIO_W1C"   ,	   0x10701020b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP17_IP2_GPIO_W1C"   ,	   0x10701022b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP18_IP2_GPIO_W1C"   ,	   0x10701024b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP19_IP2_GPIO_W1C"   ,	   0x10701026b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP20_IP2_GPIO_W1C"   ,	   0x10701028b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP21_IP2_GPIO_W1C"   ,	   0x1070102ab7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP22_IP2_GPIO_W1C"   ,	   0x1070102cb7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP23_IP2_GPIO_W1C"   ,	   0x1070102eb7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP24_IP2_GPIO_W1C"   ,	   0x10701030b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP25_IP2_GPIO_W1C"   ,	   0x10701032b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP26_IP2_GPIO_W1C"   ,	   0x10701034b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP27_IP2_GPIO_W1C"   ,	   0x10701036b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP28_IP2_GPIO_W1C"   ,	   0x10701038b7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP29_IP2_GPIO_W1C"   ,	   0x1070103ab7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP30_IP2_GPIO_W1C"   ,	   0x1070103cb7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP31_IP2_GPIO_W1C"   ,	   0x1070103eb7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU2_EN_PP0_IP2_GPIO_W1S"    ,	   0x10701000a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP1_IP2_GPIO_W1S"    ,	   0x10701002a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP2_IP2_GPIO_W1S"    ,	   0x10701004a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP3_IP2_GPIO_W1S"    ,	   0x10701006a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP4_IP2_GPIO_W1S"    ,	   0x10701008a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP5_IP2_GPIO_W1S"    ,	   0x1070100aa7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP6_IP2_GPIO_W1S"    ,	   0x1070100ca7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP7_IP2_GPIO_W1S"    ,	   0x1070100ea7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP8_IP2_GPIO_W1S"    ,	   0x10701010a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP9_IP2_GPIO_W1S"    ,	   0x10701012a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP10_IP2_GPIO_W1S"   ,	   0x10701014a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP11_IP2_GPIO_W1S"   ,	   0x10701016a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP12_IP2_GPIO_W1S"   ,	   0x10701018a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP13_IP2_GPIO_W1S"   ,	   0x1070101aa7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP14_IP2_GPIO_W1S"   ,	   0x1070101ca7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP15_IP2_GPIO_W1S"   ,	   0x1070101ea7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP16_IP2_GPIO_W1S"   ,	   0x10701020a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP17_IP2_GPIO_W1S"   ,	   0x10701022a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP18_IP2_GPIO_W1S"   ,	   0x10701024a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP19_IP2_GPIO_W1S"   ,	   0x10701026a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP20_IP2_GPIO_W1S"   ,	   0x10701028a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP21_IP2_GPIO_W1S"   ,	   0x1070102aa7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP22_IP2_GPIO_W1S"   ,	   0x1070102ca7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP23_IP2_GPIO_W1S"   ,	   0x1070102ea7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP24_IP2_GPIO_W1S"   ,	   0x10701030a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP25_IP2_GPIO_W1S"   ,	   0x10701032a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP26_IP2_GPIO_W1S"   ,	   0x10701034a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP27_IP2_GPIO_W1S"   ,	   0x10701036a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP28_IP2_GPIO_W1S"   ,	   0x10701038a7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP29_IP2_GPIO_W1S"   ,	   0x1070103aa7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP30_IP2_GPIO_W1S"   ,	   0x1070103ca7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP31_IP2_GPIO_W1S"   ,	   0x1070103ea7000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU2_EN_PP0_IP2_IO"          ,	   0x1070100094000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP1_IP2_IO"          ,	   0x1070100294000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP2_IP2_IO"          ,	   0x1070100494000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP3_IP2_IO"          ,	   0x1070100694000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP4_IP2_IO"          ,	   0x1070100894000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP5_IP2_IO"          ,	   0x1070100a94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP6_IP2_IO"          ,	   0x1070100c94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP7_IP2_IO"          ,	   0x1070100e94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP8_IP2_IO"          ,	   0x1070101094000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP9_IP2_IO"          ,	   0x1070101294000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP10_IP2_IO"         ,	   0x1070101494000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP11_IP2_IO"         ,	   0x1070101694000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP12_IP2_IO"         ,	   0x1070101894000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP13_IP2_IO"         ,	   0x1070101a94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP14_IP2_IO"         ,	   0x1070101c94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP15_IP2_IO"         ,	   0x1070101e94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP16_IP2_IO"         ,	   0x1070102094000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP17_IP2_IO"         ,	   0x1070102294000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP18_IP2_IO"         ,	   0x1070102494000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP19_IP2_IO"         ,	   0x1070102694000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP20_IP2_IO"         ,	   0x1070102894000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP21_IP2_IO"         ,	   0x1070102a94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP22_IP2_IO"         ,	   0x1070102c94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP23_IP2_IO"         ,	   0x1070102e94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP24_IP2_IO"         ,	   0x1070103094000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP25_IP2_IO"         ,	   0x1070103294000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP26_IP2_IO"         ,	   0x1070103494000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP27_IP2_IO"         ,	   0x1070103694000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP28_IP2_IO"         ,	   0x1070103894000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP29_IP2_IO"         ,	   0x1070103a94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP30_IP2_IO"         ,	   0x1070103c94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP31_IP2_IO"         ,	   0x1070103e94000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU2_EN_PP0_IP2_IO_W1C"      ,	   0x10701000b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP1_IP2_IO_W1C"      ,	   0x10701002b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP2_IP2_IO_W1C"      ,	   0x10701004b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP3_IP2_IO_W1C"      ,	   0x10701006b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP4_IP2_IO_W1C"      ,	   0x10701008b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP5_IP2_IO_W1C"      ,	   0x1070100ab4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP6_IP2_IO_W1C"      ,	   0x1070100cb4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP7_IP2_IO_W1C"      ,	   0x1070100eb4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP8_IP2_IO_W1C"      ,	   0x10701010b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP9_IP2_IO_W1C"      ,	   0x10701012b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP10_IP2_IO_W1C"     ,	   0x10701014b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP11_IP2_IO_W1C"     ,	   0x10701016b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP12_IP2_IO_W1C"     ,	   0x10701018b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP13_IP2_IO_W1C"     ,	   0x1070101ab4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP14_IP2_IO_W1C"     ,	   0x1070101cb4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP15_IP2_IO_W1C"     ,	   0x1070101eb4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP16_IP2_IO_W1C"     ,	   0x10701020b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP17_IP2_IO_W1C"     ,	   0x10701022b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP18_IP2_IO_W1C"     ,	   0x10701024b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP19_IP2_IO_W1C"     ,	   0x10701026b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP20_IP2_IO_W1C"     ,	   0x10701028b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP21_IP2_IO_W1C"     ,	   0x1070102ab4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP22_IP2_IO_W1C"     ,	   0x1070102cb4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP23_IP2_IO_W1C"     ,	   0x1070102eb4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP24_IP2_IO_W1C"     ,	   0x10701030b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP25_IP2_IO_W1C"     ,	   0x10701032b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP26_IP2_IO_W1C"     ,	   0x10701034b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP27_IP2_IO_W1C"     ,	   0x10701036b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP28_IP2_IO_W1C"     ,	   0x10701038b4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP29_IP2_IO_W1C"     ,	   0x1070103ab4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP30_IP2_IO_W1C"     ,	   0x1070103cb4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP31_IP2_IO_W1C"     ,	   0x1070103eb4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU2_EN_PP0_IP2_IO_W1S"      ,	   0x10701000a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP1_IP2_IO_W1S"      ,	   0x10701002a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP2_IP2_IO_W1S"      ,	   0x10701004a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP3_IP2_IO_W1S"      ,	   0x10701006a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP4_IP2_IO_W1S"      ,	   0x10701008a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP5_IP2_IO_W1S"      ,	   0x1070100aa4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP6_IP2_IO_W1S"      ,	   0x1070100ca4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP7_IP2_IO_W1S"      ,	   0x1070100ea4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP8_IP2_IO_W1S"      ,	   0x10701010a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP9_IP2_IO_W1S"      ,	   0x10701012a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP10_IP2_IO_W1S"     ,	   0x10701014a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP11_IP2_IO_W1S"     ,	   0x10701016a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP12_IP2_IO_W1S"     ,	   0x10701018a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP13_IP2_IO_W1S"     ,	   0x1070101aa4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP14_IP2_IO_W1S"     ,	   0x1070101ca4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP15_IP2_IO_W1S"     ,	   0x1070101ea4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP16_IP2_IO_W1S"     ,	   0x10701020a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP17_IP2_IO_W1S"     ,	   0x10701022a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP18_IP2_IO_W1S"     ,	   0x10701024a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP19_IP2_IO_W1S"     ,	   0x10701026a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP20_IP2_IO_W1S"     ,	   0x10701028a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP21_IP2_IO_W1S"     ,	   0x1070102aa4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP22_IP2_IO_W1S"     ,	   0x1070102ca4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP23_IP2_IO_W1S"     ,	   0x1070102ea4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP24_IP2_IO_W1S"     ,	   0x10701030a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP25_IP2_IO_W1S"     ,	   0x10701032a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP26_IP2_IO_W1S"     ,	   0x10701034a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP27_IP2_IO_W1S"     ,	   0x10701036a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP28_IP2_IO_W1S"     ,	   0x10701038a4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP29_IP2_IO_W1S"     ,	   0x1070103aa4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP30_IP2_IO_W1S"     ,	   0x1070103ca4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP31_IP2_IO_W1S"     ,	   0x1070103ea4000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU2_EN_PP0_IP2_MBOX"        ,	   0x1070100098000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP1_IP2_MBOX"        ,	   0x1070100298000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP2_IP2_MBOX"        ,	   0x1070100498000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP3_IP2_MBOX"        ,	   0x1070100698000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP4_IP2_MBOX"        ,	   0x1070100898000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP5_IP2_MBOX"        ,	   0x1070100a98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP6_IP2_MBOX"        ,	   0x1070100c98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP7_IP2_MBOX"        ,	   0x1070100e98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP8_IP2_MBOX"        ,	   0x1070101098000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP9_IP2_MBOX"        ,	   0x1070101298000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP10_IP2_MBOX"       ,	   0x1070101498000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP11_IP2_MBOX"       ,	   0x1070101698000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP12_IP2_MBOX"       ,	   0x1070101898000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP13_IP2_MBOX"       ,	   0x1070101a98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP14_IP2_MBOX"       ,	   0x1070101c98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP15_IP2_MBOX"       ,	   0x1070101e98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP16_IP2_MBOX"       ,	   0x1070102098000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP17_IP2_MBOX"       ,	   0x1070102298000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP18_IP2_MBOX"       ,	   0x1070102498000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP19_IP2_MBOX"       ,	   0x1070102698000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP20_IP2_MBOX"       ,	   0x1070102898000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP21_IP2_MBOX"       ,	   0x1070102a98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP22_IP2_MBOX"       ,	   0x1070102c98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP23_IP2_MBOX"       ,	   0x1070102e98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP24_IP2_MBOX"       ,	   0x1070103098000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP25_IP2_MBOX"       ,	   0x1070103298000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP26_IP2_MBOX"       ,	   0x1070103498000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP27_IP2_MBOX"       ,	   0x1070103698000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP28_IP2_MBOX"       ,	   0x1070103898000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP29_IP2_MBOX"       ,	   0x1070103a98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP30_IP2_MBOX"       ,	   0x1070103c98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP31_IP2_MBOX"       ,	   0x1070103e98000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU2_EN_PP0_IP2_MBOX_W1C"    ,	   0x10701000b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP1_IP2_MBOX_W1C"    ,	   0x10701002b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP2_IP2_MBOX_W1C"    ,	   0x10701004b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP3_IP2_MBOX_W1C"    ,	   0x10701006b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP4_IP2_MBOX_W1C"    ,	   0x10701008b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP5_IP2_MBOX_W1C"    ,	   0x1070100ab8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP6_IP2_MBOX_W1C"    ,	   0x1070100cb8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP7_IP2_MBOX_W1C"    ,	   0x1070100eb8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP8_IP2_MBOX_W1C"    ,	   0x10701010b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP9_IP2_MBOX_W1C"    ,	   0x10701012b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP10_IP2_MBOX_W1C"   ,	   0x10701014b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP11_IP2_MBOX_W1C"   ,	   0x10701016b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP12_IP2_MBOX_W1C"   ,	   0x10701018b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP13_IP2_MBOX_W1C"   ,	   0x1070101ab8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP14_IP2_MBOX_W1C"   ,	   0x1070101cb8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP15_IP2_MBOX_W1C"   ,	   0x1070101eb8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP16_IP2_MBOX_W1C"   ,	   0x10701020b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP17_IP2_MBOX_W1C"   ,	   0x10701022b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP18_IP2_MBOX_W1C"   ,	   0x10701024b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP19_IP2_MBOX_W1C"   ,	   0x10701026b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP20_IP2_MBOX_W1C"   ,	   0x10701028b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP21_IP2_MBOX_W1C"   ,	   0x1070102ab8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP22_IP2_MBOX_W1C"   ,	   0x1070102cb8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP23_IP2_MBOX_W1C"   ,	   0x1070102eb8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP24_IP2_MBOX_W1C"   ,	   0x10701030b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP25_IP2_MBOX_W1C"   ,	   0x10701032b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP26_IP2_MBOX_W1C"   ,	   0x10701034b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP27_IP2_MBOX_W1C"   ,	   0x10701036b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP28_IP2_MBOX_W1C"   ,	   0x10701038b8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP29_IP2_MBOX_W1C"   ,	   0x1070103ab8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP30_IP2_MBOX_W1C"   ,	   0x1070103cb8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP31_IP2_MBOX_W1C"   ,	   0x1070103eb8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU2_EN_PP0_IP2_MBOX_W1S"    ,	   0x10701000a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP1_IP2_MBOX_W1S"    ,	   0x10701002a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP2_IP2_MBOX_W1S"    ,	   0x10701004a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP3_IP2_MBOX_W1S"    ,	   0x10701006a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP4_IP2_MBOX_W1S"    ,	   0x10701008a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP5_IP2_MBOX_W1S"    ,	   0x1070100aa8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP6_IP2_MBOX_W1S"    ,	   0x1070100ca8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP7_IP2_MBOX_W1S"    ,	   0x1070100ea8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP8_IP2_MBOX_W1S"    ,	   0x10701010a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP9_IP2_MBOX_W1S"    ,	   0x10701012a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP10_IP2_MBOX_W1S"   ,	   0x10701014a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP11_IP2_MBOX_W1S"   ,	   0x10701016a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP12_IP2_MBOX_W1S"   ,	   0x10701018a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP13_IP2_MBOX_W1S"   ,	   0x1070101aa8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP14_IP2_MBOX_W1S"   ,	   0x1070101ca8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP15_IP2_MBOX_W1S"   ,	   0x1070101ea8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP16_IP2_MBOX_W1S"   ,	   0x10701020a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP17_IP2_MBOX_W1S"   ,	   0x10701022a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP18_IP2_MBOX_W1S"   ,	   0x10701024a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP19_IP2_MBOX_W1S"   ,	   0x10701026a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP20_IP2_MBOX_W1S"   ,	   0x10701028a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP21_IP2_MBOX_W1S"   ,	   0x1070102aa8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP22_IP2_MBOX_W1S"   ,	   0x1070102ca8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP23_IP2_MBOX_W1S"   ,	   0x1070102ea8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP24_IP2_MBOX_W1S"   ,	   0x10701030a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP25_IP2_MBOX_W1S"   ,	   0x10701032a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP26_IP2_MBOX_W1S"   ,	   0x10701034a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP27_IP2_MBOX_W1S"   ,	   0x10701036a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP28_IP2_MBOX_W1S"   ,	   0x10701038a8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP29_IP2_MBOX_W1S"   ,	   0x1070103aa8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP30_IP2_MBOX_W1S"   ,	   0x1070103ca8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP31_IP2_MBOX_W1S"   ,	   0x1070103ea8000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU2_EN_PP0_IP2_MEM"         ,	   0x1070100095000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP1_IP2_MEM"         ,	   0x1070100295000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP2_IP2_MEM"         ,	   0x1070100495000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP3_IP2_MEM"         ,	   0x1070100695000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP4_IP2_MEM"         ,	   0x1070100895000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP5_IP2_MEM"         ,	   0x1070100a95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP6_IP2_MEM"         ,	   0x1070100c95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP7_IP2_MEM"         ,	   0x1070100e95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP8_IP2_MEM"         ,	   0x1070101095000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP9_IP2_MEM"         ,	   0x1070101295000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP10_IP2_MEM"        ,	   0x1070101495000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP11_IP2_MEM"        ,	   0x1070101695000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP12_IP2_MEM"        ,	   0x1070101895000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP13_IP2_MEM"        ,	   0x1070101a95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP14_IP2_MEM"        ,	   0x1070101c95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP15_IP2_MEM"        ,	   0x1070101e95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP16_IP2_MEM"        ,	   0x1070102095000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP17_IP2_MEM"        ,	   0x1070102295000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP18_IP2_MEM"        ,	   0x1070102495000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP19_IP2_MEM"        ,	   0x1070102695000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP20_IP2_MEM"        ,	   0x1070102895000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP21_IP2_MEM"        ,	   0x1070102a95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP22_IP2_MEM"        ,	   0x1070102c95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP23_IP2_MEM"        ,	   0x1070102e95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP24_IP2_MEM"        ,	   0x1070103095000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP25_IP2_MEM"        ,	   0x1070103295000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP26_IP2_MEM"        ,	   0x1070103495000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP27_IP2_MEM"        ,	   0x1070103695000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP28_IP2_MEM"        ,	   0x1070103895000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP29_IP2_MEM"        ,	   0x1070103a95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP30_IP2_MEM"        ,	   0x1070103c95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP31_IP2_MEM"        ,	   0x1070103e95000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	112},
+	{"CIU2_EN_PP0_IP2_MEM_W1C"     ,	   0x10701000b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP1_IP2_MEM_W1C"     ,	   0x10701002b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP2_IP2_MEM_W1C"     ,	   0x10701004b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP3_IP2_MEM_W1C"     ,	   0x10701006b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP4_IP2_MEM_W1C"     ,	   0x10701008b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP5_IP2_MEM_W1C"     ,	   0x1070100ab5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP6_IP2_MEM_W1C"     ,	   0x1070100cb5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP7_IP2_MEM_W1C"     ,	   0x1070100eb5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP8_IP2_MEM_W1C"     ,	   0x10701010b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP9_IP2_MEM_W1C"     ,	   0x10701012b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP10_IP2_MEM_W1C"    ,	   0x10701014b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP11_IP2_MEM_W1C"    ,	   0x10701016b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP12_IP2_MEM_W1C"    ,	   0x10701018b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP13_IP2_MEM_W1C"    ,	   0x1070101ab5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP14_IP2_MEM_W1C"    ,	   0x1070101cb5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP15_IP2_MEM_W1C"    ,	   0x1070101eb5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP16_IP2_MEM_W1C"    ,	   0x10701020b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP17_IP2_MEM_W1C"    ,	   0x10701022b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP18_IP2_MEM_W1C"    ,	   0x10701024b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP19_IP2_MEM_W1C"    ,	   0x10701026b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP20_IP2_MEM_W1C"    ,	   0x10701028b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP21_IP2_MEM_W1C"    ,	   0x1070102ab5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP22_IP2_MEM_W1C"    ,	   0x1070102cb5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP23_IP2_MEM_W1C"    ,	   0x1070102eb5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP24_IP2_MEM_W1C"    ,	   0x10701030b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP25_IP2_MEM_W1C"    ,	   0x10701032b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP26_IP2_MEM_W1C"    ,	   0x10701034b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP27_IP2_MEM_W1C"    ,	   0x10701036b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP28_IP2_MEM_W1C"    ,	   0x10701038b5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP29_IP2_MEM_W1C"    ,	   0x1070103ab5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP30_IP2_MEM_W1C"    ,	   0x1070103cb5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP31_IP2_MEM_W1C"    ,	   0x1070103eb5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	113},
+	{"CIU2_EN_PP0_IP2_MEM_W1S"     ,	   0x10701000a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP1_IP2_MEM_W1S"     ,	   0x10701002a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP2_IP2_MEM_W1S"     ,	   0x10701004a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP3_IP2_MEM_W1S"     ,	   0x10701006a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP4_IP2_MEM_W1S"     ,	   0x10701008a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP5_IP2_MEM_W1S"     ,	   0x1070100aa5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP6_IP2_MEM_W1S"     ,	   0x1070100ca5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP7_IP2_MEM_W1S"     ,	   0x1070100ea5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP8_IP2_MEM_W1S"     ,	   0x10701010a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP9_IP2_MEM_W1S"     ,	   0x10701012a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP10_IP2_MEM_W1S"    ,	   0x10701014a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP11_IP2_MEM_W1S"    ,	   0x10701016a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP12_IP2_MEM_W1S"    ,	   0x10701018a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP13_IP2_MEM_W1S"    ,	   0x1070101aa5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP14_IP2_MEM_W1S"    ,	   0x1070101ca5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP15_IP2_MEM_W1S"    ,	   0x1070101ea5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP16_IP2_MEM_W1S"    ,	   0x10701020a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP17_IP2_MEM_W1S"    ,	   0x10701022a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP18_IP2_MEM_W1S"    ,	   0x10701024a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP19_IP2_MEM_W1S"    ,	   0x10701026a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP20_IP2_MEM_W1S"    ,	   0x10701028a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP21_IP2_MEM_W1S"    ,	   0x1070102aa5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP22_IP2_MEM_W1S"    ,	   0x1070102ca5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP23_IP2_MEM_W1S"    ,	   0x1070102ea5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP24_IP2_MEM_W1S"    ,	   0x10701030a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP25_IP2_MEM_W1S"    ,	   0x10701032a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP26_IP2_MEM_W1S"    ,	   0x10701034a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP27_IP2_MEM_W1S"    ,	   0x10701036a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP28_IP2_MEM_W1S"    ,	   0x10701038a5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP29_IP2_MEM_W1S"    ,	   0x1070103aa5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP30_IP2_MEM_W1S"    ,	   0x1070103ca5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP31_IP2_MEM_W1S"    ,	   0x1070103ea5000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	114},
+	{"CIU2_EN_PP0_IP2_MIO"         ,	   0x1070100093000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP1_IP2_MIO"         ,	   0x1070100293000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP2_IP2_MIO"         ,	   0x1070100493000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP3_IP2_MIO"         ,	   0x1070100693000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP4_IP2_MIO"         ,	   0x1070100893000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP5_IP2_MIO"         ,	   0x1070100a93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP6_IP2_MIO"         ,	   0x1070100c93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP7_IP2_MIO"         ,	   0x1070100e93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP8_IP2_MIO"         ,	   0x1070101093000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP9_IP2_MIO"         ,	   0x1070101293000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP10_IP2_MIO"        ,	   0x1070101493000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP11_IP2_MIO"        ,	   0x1070101693000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP12_IP2_MIO"        ,	   0x1070101893000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP13_IP2_MIO"        ,	   0x1070101a93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP14_IP2_MIO"        ,	   0x1070101c93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP15_IP2_MIO"        ,	   0x1070101e93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP16_IP2_MIO"        ,	   0x1070102093000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP17_IP2_MIO"        ,	   0x1070102293000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP18_IP2_MIO"        ,	   0x1070102493000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP19_IP2_MIO"        ,	   0x1070102693000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP20_IP2_MIO"        ,	   0x1070102893000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP21_IP2_MIO"        ,	   0x1070102a93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP22_IP2_MIO"        ,	   0x1070102c93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP23_IP2_MIO"        ,	   0x1070102e93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP24_IP2_MIO"        ,	   0x1070103093000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP25_IP2_MIO"        ,	   0x1070103293000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP26_IP2_MIO"        ,	   0x1070103493000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP27_IP2_MIO"        ,	   0x1070103693000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP28_IP2_MIO"        ,	   0x1070103893000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP29_IP2_MIO"        ,	   0x1070103a93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP30_IP2_MIO"        ,	   0x1070103c93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP31_IP2_MIO"        ,	   0x1070103e93000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"CIU2_EN_PP0_IP2_MIO_W1C"     ,	   0x10701000b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP1_IP2_MIO_W1C"     ,	   0x10701002b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP2_IP2_MIO_W1C"     ,	   0x10701004b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP3_IP2_MIO_W1C"     ,	   0x10701006b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP4_IP2_MIO_W1C"     ,	   0x10701008b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP5_IP2_MIO_W1C"     ,	   0x1070100ab3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP6_IP2_MIO_W1C"     ,	   0x1070100cb3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP7_IP2_MIO_W1C"     ,	   0x1070100eb3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP8_IP2_MIO_W1C"     ,	   0x10701010b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP9_IP2_MIO_W1C"     ,	   0x10701012b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP10_IP2_MIO_W1C"    ,	   0x10701014b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP11_IP2_MIO_W1C"    ,	   0x10701016b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP12_IP2_MIO_W1C"    ,	   0x10701018b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP13_IP2_MIO_W1C"    ,	   0x1070101ab3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP14_IP2_MIO_W1C"    ,	   0x1070101cb3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP15_IP2_MIO_W1C"    ,	   0x1070101eb3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP16_IP2_MIO_W1C"    ,	   0x10701020b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP17_IP2_MIO_W1C"    ,	   0x10701022b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP18_IP2_MIO_W1C"    ,	   0x10701024b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP19_IP2_MIO_W1C"    ,	   0x10701026b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP20_IP2_MIO_W1C"    ,	   0x10701028b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP21_IP2_MIO_W1C"    ,	   0x1070102ab3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP22_IP2_MIO_W1C"    ,	   0x1070102cb3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP23_IP2_MIO_W1C"    ,	   0x1070102eb3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP24_IP2_MIO_W1C"    ,	   0x10701030b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP25_IP2_MIO_W1C"    ,	   0x10701032b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP26_IP2_MIO_W1C"    ,	   0x10701034b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP27_IP2_MIO_W1C"    ,	   0x10701036b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP28_IP2_MIO_W1C"    ,	   0x10701038b3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP29_IP2_MIO_W1C"    ,	   0x1070103ab3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP30_IP2_MIO_W1C"    ,	   0x1070103cb3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP31_IP2_MIO_W1C"    ,	   0x1070103eb3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"CIU2_EN_PP0_IP2_MIO_W1S"     ,	   0x10701000a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP1_IP2_MIO_W1S"     ,	   0x10701002a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP2_IP2_MIO_W1S"     ,	   0x10701004a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP3_IP2_MIO_W1S"     ,	   0x10701006a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP4_IP2_MIO_W1S"     ,	   0x10701008a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP5_IP2_MIO_W1S"     ,	   0x1070100aa3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP6_IP2_MIO_W1S"     ,	   0x1070100ca3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP7_IP2_MIO_W1S"     ,	   0x1070100ea3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP8_IP2_MIO_W1S"     ,	   0x10701010a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP9_IP2_MIO_W1S"     ,	   0x10701012a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP10_IP2_MIO_W1S"    ,	   0x10701014a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP11_IP2_MIO_W1S"    ,	   0x10701016a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP12_IP2_MIO_W1S"    ,	   0x10701018a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP13_IP2_MIO_W1S"    ,	   0x1070101aa3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP14_IP2_MIO_W1S"    ,	   0x1070101ca3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP15_IP2_MIO_W1S"    ,	   0x1070101ea3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP16_IP2_MIO_W1S"    ,	   0x10701020a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP17_IP2_MIO_W1S"    ,	   0x10701022a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP18_IP2_MIO_W1S"    ,	   0x10701024a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP19_IP2_MIO_W1S"    ,	   0x10701026a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP20_IP2_MIO_W1S"    ,	   0x10701028a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP21_IP2_MIO_W1S"    ,	   0x1070102aa3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP22_IP2_MIO_W1S"    ,	   0x1070102ca3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP23_IP2_MIO_W1S"    ,	   0x1070102ea3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP24_IP2_MIO_W1S"    ,	   0x10701030a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP25_IP2_MIO_W1S"    ,	   0x10701032a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP26_IP2_MIO_W1S"    ,	   0x10701034a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP27_IP2_MIO_W1S"    ,	   0x10701036a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP28_IP2_MIO_W1S"    ,	   0x10701038a3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP29_IP2_MIO_W1S"    ,	   0x1070103aa3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP30_IP2_MIO_W1S"    ,	   0x1070103ca3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP31_IP2_MIO_W1S"    ,	   0x1070103ea3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	117},
+	{"CIU2_EN_PP0_IP2_PKT"         ,	   0x1070100096000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP1_IP2_PKT"         ,	   0x1070100296000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP2_IP2_PKT"         ,	   0x1070100496000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP3_IP2_PKT"         ,	   0x1070100696000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP4_IP2_PKT"         ,	   0x1070100896000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP5_IP2_PKT"         ,	   0x1070100a96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP6_IP2_PKT"         ,	   0x1070100c96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP7_IP2_PKT"         ,	   0x1070100e96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP8_IP2_PKT"         ,	   0x1070101096000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP9_IP2_PKT"         ,	   0x1070101296000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP10_IP2_PKT"        ,	   0x1070101496000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP11_IP2_PKT"        ,	   0x1070101696000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP12_IP2_PKT"        ,	   0x1070101896000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP13_IP2_PKT"        ,	   0x1070101a96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP14_IP2_PKT"        ,	   0x1070101c96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP15_IP2_PKT"        ,	   0x1070101e96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP16_IP2_PKT"        ,	   0x1070102096000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP17_IP2_PKT"        ,	   0x1070102296000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP18_IP2_PKT"        ,	   0x1070102496000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP19_IP2_PKT"        ,	   0x1070102696000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP20_IP2_PKT"        ,	   0x1070102896000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP21_IP2_PKT"        ,	   0x1070102a96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP22_IP2_PKT"        ,	   0x1070102c96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP23_IP2_PKT"        ,	   0x1070102e96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP24_IP2_PKT"        ,	   0x1070103096000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP25_IP2_PKT"        ,	   0x1070103296000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP26_IP2_PKT"        ,	   0x1070103496000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP27_IP2_PKT"        ,	   0x1070103696000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP28_IP2_PKT"        ,	   0x1070103896000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP29_IP2_PKT"        ,	   0x1070103a96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP30_IP2_PKT"        ,	   0x1070103c96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP31_IP2_PKT"        ,	   0x1070103e96000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	118},
+	{"CIU2_EN_PP0_IP2_PKT_W1C"     ,	   0x10701000b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP1_IP2_PKT_W1C"     ,	   0x10701002b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP2_IP2_PKT_W1C"     ,	   0x10701004b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP3_IP2_PKT_W1C"     ,	   0x10701006b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP4_IP2_PKT_W1C"     ,	   0x10701008b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP5_IP2_PKT_W1C"     ,	   0x1070100ab6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP6_IP2_PKT_W1C"     ,	   0x1070100cb6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP7_IP2_PKT_W1C"     ,	   0x1070100eb6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP8_IP2_PKT_W1C"     ,	   0x10701010b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP9_IP2_PKT_W1C"     ,	   0x10701012b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP10_IP2_PKT_W1C"    ,	   0x10701014b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP11_IP2_PKT_W1C"    ,	   0x10701016b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP12_IP2_PKT_W1C"    ,	   0x10701018b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP13_IP2_PKT_W1C"    ,	   0x1070101ab6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP14_IP2_PKT_W1C"    ,	   0x1070101cb6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP15_IP2_PKT_W1C"    ,	   0x1070101eb6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP16_IP2_PKT_W1C"    ,	   0x10701020b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP17_IP2_PKT_W1C"    ,	   0x10701022b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP18_IP2_PKT_W1C"    ,	   0x10701024b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP19_IP2_PKT_W1C"    ,	   0x10701026b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP20_IP2_PKT_W1C"    ,	   0x10701028b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP21_IP2_PKT_W1C"    ,	   0x1070102ab6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP22_IP2_PKT_W1C"    ,	   0x1070102cb6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP23_IP2_PKT_W1C"    ,	   0x1070102eb6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP24_IP2_PKT_W1C"    ,	   0x10701030b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP25_IP2_PKT_W1C"    ,	   0x10701032b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP26_IP2_PKT_W1C"    ,	   0x10701034b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP27_IP2_PKT_W1C"    ,	   0x10701036b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP28_IP2_PKT_W1C"    ,	   0x10701038b6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP29_IP2_PKT_W1C"    ,	   0x1070103ab6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP30_IP2_PKT_W1C"    ,	   0x1070103cb6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP31_IP2_PKT_W1C"    ,	   0x1070103eb6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	119},
+	{"CIU2_EN_PP0_IP2_PKT_W1S"     ,	   0x10701000a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP1_IP2_PKT_W1S"     ,	   0x10701002a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP2_IP2_PKT_W1S"     ,	   0x10701004a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP3_IP2_PKT_W1S"     ,	   0x10701006a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP4_IP2_PKT_W1S"     ,	   0x10701008a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP5_IP2_PKT_W1S"     ,	   0x1070100aa6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP6_IP2_PKT_W1S"     ,	   0x1070100ca6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP7_IP2_PKT_W1S"     ,	   0x1070100ea6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP8_IP2_PKT_W1S"     ,	   0x10701010a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP9_IP2_PKT_W1S"     ,	   0x10701012a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP10_IP2_PKT_W1S"    ,	   0x10701014a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP11_IP2_PKT_W1S"    ,	   0x10701016a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP12_IP2_PKT_W1S"    ,	   0x10701018a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP13_IP2_PKT_W1S"    ,	   0x1070101aa6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP14_IP2_PKT_W1S"    ,	   0x1070101ca6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP15_IP2_PKT_W1S"    ,	   0x1070101ea6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP16_IP2_PKT_W1S"    ,	   0x10701020a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP17_IP2_PKT_W1S"    ,	   0x10701022a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP18_IP2_PKT_W1S"    ,	   0x10701024a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP19_IP2_PKT_W1S"    ,	   0x10701026a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP20_IP2_PKT_W1S"    ,	   0x10701028a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP21_IP2_PKT_W1S"    ,	   0x1070102aa6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP22_IP2_PKT_W1S"    ,	   0x1070102ca6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP23_IP2_PKT_W1S"    ,	   0x1070102ea6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP24_IP2_PKT_W1S"    ,	   0x10701030a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP25_IP2_PKT_W1S"    ,	   0x10701032a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP26_IP2_PKT_W1S"    ,	   0x10701034a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP27_IP2_PKT_W1S"    ,	   0x10701036a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP28_IP2_PKT_W1S"    ,	   0x10701038a6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP29_IP2_PKT_W1S"    ,	   0x1070103aa6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP30_IP2_PKT_W1S"    ,	   0x1070103ca6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP31_IP2_PKT_W1S"    ,	   0x1070103ea6000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"CIU2_EN_PP0_IP2_RML"         ,	   0x1070100092000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP1_IP2_RML"         ,	   0x1070100292000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP2_IP2_RML"         ,	   0x1070100492000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP3_IP2_RML"         ,	   0x1070100692000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP4_IP2_RML"         ,	   0x1070100892000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP5_IP2_RML"         ,	   0x1070100a92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP6_IP2_RML"         ,	   0x1070100c92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP7_IP2_RML"         ,	   0x1070100e92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP8_IP2_RML"         ,	   0x1070101092000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP9_IP2_RML"         ,	   0x1070101292000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP10_IP2_RML"        ,	   0x1070101492000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP11_IP2_RML"        ,	   0x1070101692000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP12_IP2_RML"        ,	   0x1070101892000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP13_IP2_RML"        ,	   0x1070101a92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP14_IP2_RML"        ,	   0x1070101c92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP15_IP2_RML"        ,	   0x1070101e92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP16_IP2_RML"        ,	   0x1070102092000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP17_IP2_RML"        ,	   0x1070102292000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP18_IP2_RML"        ,	   0x1070102492000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP19_IP2_RML"        ,	   0x1070102692000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP20_IP2_RML"        ,	   0x1070102892000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP21_IP2_RML"        ,	   0x1070102a92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP22_IP2_RML"        ,	   0x1070102c92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP23_IP2_RML"        ,	   0x1070102e92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP24_IP2_RML"        ,	   0x1070103092000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP25_IP2_RML"        ,	   0x1070103292000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP26_IP2_RML"        ,	   0x1070103492000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP27_IP2_RML"        ,	   0x1070103692000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP28_IP2_RML"        ,	   0x1070103892000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP29_IP2_RML"        ,	   0x1070103a92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP30_IP2_RML"        ,	   0x1070103c92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP31_IP2_RML"        ,	   0x1070103e92000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"CIU2_EN_PP0_IP2_RML_W1C"     ,	   0x10701000b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP1_IP2_RML_W1C"     ,	   0x10701002b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP2_IP2_RML_W1C"     ,	   0x10701004b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP3_IP2_RML_W1C"     ,	   0x10701006b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP4_IP2_RML_W1C"     ,	   0x10701008b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP5_IP2_RML_W1C"     ,	   0x1070100ab2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP6_IP2_RML_W1C"     ,	   0x1070100cb2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP7_IP2_RML_W1C"     ,	   0x1070100eb2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP8_IP2_RML_W1C"     ,	   0x10701010b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP9_IP2_RML_W1C"     ,	   0x10701012b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP10_IP2_RML_W1C"    ,	   0x10701014b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP11_IP2_RML_W1C"    ,	   0x10701016b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP12_IP2_RML_W1C"    ,	   0x10701018b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP13_IP2_RML_W1C"    ,	   0x1070101ab2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP14_IP2_RML_W1C"    ,	   0x1070101cb2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP15_IP2_RML_W1C"    ,	   0x1070101eb2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP16_IP2_RML_W1C"    ,	   0x10701020b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP17_IP2_RML_W1C"    ,	   0x10701022b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP18_IP2_RML_W1C"    ,	   0x10701024b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP19_IP2_RML_W1C"    ,	   0x10701026b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP20_IP2_RML_W1C"    ,	   0x10701028b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP21_IP2_RML_W1C"    ,	   0x1070102ab2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP22_IP2_RML_W1C"    ,	   0x1070102cb2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP23_IP2_RML_W1C"    ,	   0x1070102eb2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP24_IP2_RML_W1C"    ,	   0x10701030b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP25_IP2_RML_W1C"    ,	   0x10701032b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP26_IP2_RML_W1C"    ,	   0x10701034b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP27_IP2_RML_W1C"    ,	   0x10701036b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP28_IP2_RML_W1C"    ,	   0x10701038b2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP29_IP2_RML_W1C"    ,	   0x1070103ab2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP30_IP2_RML_W1C"    ,	   0x1070103cb2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP31_IP2_RML_W1C"    ,	   0x1070103eb2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"CIU2_EN_PP0_IP2_RML_W1S"     ,	   0x10701000a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP1_IP2_RML_W1S"     ,	   0x10701002a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP2_IP2_RML_W1S"     ,	   0x10701004a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP3_IP2_RML_W1S"     ,	   0x10701006a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP4_IP2_RML_W1S"     ,	   0x10701008a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP5_IP2_RML_W1S"     ,	   0x1070100aa2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP6_IP2_RML_W1S"     ,	   0x1070100ca2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP7_IP2_RML_W1S"     ,	   0x1070100ea2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP8_IP2_RML_W1S"     ,	   0x10701010a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP9_IP2_RML_W1S"     ,	   0x10701012a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP10_IP2_RML_W1S"    ,	   0x10701014a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP11_IP2_RML_W1S"    ,	   0x10701016a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP12_IP2_RML_W1S"    ,	   0x10701018a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP13_IP2_RML_W1S"    ,	   0x1070101aa2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP14_IP2_RML_W1S"    ,	   0x1070101ca2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP15_IP2_RML_W1S"    ,	   0x1070101ea2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP16_IP2_RML_W1S"    ,	   0x10701020a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP17_IP2_RML_W1S"    ,	   0x10701022a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP18_IP2_RML_W1S"    ,	   0x10701024a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP19_IP2_RML_W1S"    ,	   0x10701026a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP20_IP2_RML_W1S"    ,	   0x10701028a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP21_IP2_RML_W1S"    ,	   0x1070102aa2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP22_IP2_RML_W1S"    ,	   0x1070102ca2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP23_IP2_RML_W1S"    ,	   0x1070102ea2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP24_IP2_RML_W1S"    ,	   0x10701030a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP25_IP2_RML_W1S"    ,	   0x10701032a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP26_IP2_RML_W1S"    ,	   0x10701034a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP27_IP2_RML_W1S"    ,	   0x10701036a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP28_IP2_RML_W1S"    ,	   0x10701038a2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP29_IP2_RML_W1S"    ,	   0x1070103aa2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP30_IP2_RML_W1S"    ,	   0x1070103ca2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP31_IP2_RML_W1S"    ,	   0x1070103ea2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"CIU2_EN_PP0_IP2_WDOG"        ,	   0x1070100091000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP1_IP2_WDOG"        ,	   0x1070100291000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP2_IP2_WDOG"        ,	   0x1070100491000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP3_IP2_WDOG"        ,	   0x1070100691000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP4_IP2_WDOG"        ,	   0x1070100891000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP5_IP2_WDOG"        ,	   0x1070100a91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP6_IP2_WDOG"        ,	   0x1070100c91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP7_IP2_WDOG"        ,	   0x1070100e91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP8_IP2_WDOG"        ,	   0x1070101091000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP9_IP2_WDOG"        ,	   0x1070101291000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP10_IP2_WDOG"       ,	   0x1070101491000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP11_IP2_WDOG"       ,	   0x1070101691000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP12_IP2_WDOG"       ,	   0x1070101891000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP13_IP2_WDOG"       ,	   0x1070101a91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP14_IP2_WDOG"       ,	   0x1070101c91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP15_IP2_WDOG"       ,	   0x1070101e91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP16_IP2_WDOG"       ,	   0x1070102091000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP17_IP2_WDOG"       ,	   0x1070102291000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP18_IP2_WDOG"       ,	   0x1070102491000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP19_IP2_WDOG"       ,	   0x1070102691000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP20_IP2_WDOG"       ,	   0x1070102891000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP21_IP2_WDOG"       ,	   0x1070102a91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP22_IP2_WDOG"       ,	   0x1070102c91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP23_IP2_WDOG"       ,	   0x1070102e91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP24_IP2_WDOG"       ,	   0x1070103091000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP25_IP2_WDOG"       ,	   0x1070103291000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP26_IP2_WDOG"       ,	   0x1070103491000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP27_IP2_WDOG"       ,	   0x1070103691000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP28_IP2_WDOG"       ,	   0x1070103891000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP29_IP2_WDOG"       ,	   0x1070103a91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP30_IP2_WDOG"       ,	   0x1070103c91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP31_IP2_WDOG"       ,	   0x1070103e91000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"CIU2_EN_PP0_IP2_WDOG_W1C"    ,	   0x10701000b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP1_IP2_WDOG_W1C"    ,	   0x10701002b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP2_IP2_WDOG_W1C"    ,	   0x10701004b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP3_IP2_WDOG_W1C"    ,	   0x10701006b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP4_IP2_WDOG_W1C"    ,	   0x10701008b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP5_IP2_WDOG_W1C"    ,	   0x1070100ab1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP6_IP2_WDOG_W1C"    ,	   0x1070100cb1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP7_IP2_WDOG_W1C"    ,	   0x1070100eb1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP8_IP2_WDOG_W1C"    ,	   0x10701010b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP9_IP2_WDOG_W1C"    ,	   0x10701012b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP10_IP2_WDOG_W1C"   ,	   0x10701014b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP11_IP2_WDOG_W1C"   ,	   0x10701016b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP12_IP2_WDOG_W1C"   ,	   0x10701018b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP13_IP2_WDOG_W1C"   ,	   0x1070101ab1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP14_IP2_WDOG_W1C"   ,	   0x1070101cb1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP15_IP2_WDOG_W1C"   ,	   0x1070101eb1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP16_IP2_WDOG_W1C"   ,	   0x10701020b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP17_IP2_WDOG_W1C"   ,	   0x10701022b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP18_IP2_WDOG_W1C"   ,	   0x10701024b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP19_IP2_WDOG_W1C"   ,	   0x10701026b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP20_IP2_WDOG_W1C"   ,	   0x10701028b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP21_IP2_WDOG_W1C"   ,	   0x1070102ab1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP22_IP2_WDOG_W1C"   ,	   0x1070102cb1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP23_IP2_WDOG_W1C"   ,	   0x1070102eb1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP24_IP2_WDOG_W1C"   ,	   0x10701030b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP25_IP2_WDOG_W1C"   ,	   0x10701032b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP26_IP2_WDOG_W1C"   ,	   0x10701034b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP27_IP2_WDOG_W1C"   ,	   0x10701036b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP28_IP2_WDOG_W1C"   ,	   0x10701038b1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP29_IP2_WDOG_W1C"   ,	   0x1070103ab1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP30_IP2_WDOG_W1C"   ,	   0x1070103cb1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP31_IP2_WDOG_W1C"   ,	   0x1070103eb1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"CIU2_EN_PP0_IP2_WDOG_W1S"    ,	   0x10701000a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP1_IP2_WDOG_W1S"    ,	   0x10701002a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP2_IP2_WDOG_W1S"    ,	   0x10701004a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP3_IP2_WDOG_W1S"    ,	   0x10701006a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP4_IP2_WDOG_W1S"    ,	   0x10701008a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP5_IP2_WDOG_W1S"    ,	   0x1070100aa1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP6_IP2_WDOG_W1S"    ,	   0x1070100ca1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP7_IP2_WDOG_W1S"    ,	   0x1070100ea1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP8_IP2_WDOG_W1S"    ,	   0x10701010a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP9_IP2_WDOG_W1S"    ,	   0x10701012a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP10_IP2_WDOG_W1S"   ,	   0x10701014a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP11_IP2_WDOG_W1S"   ,	   0x10701016a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP12_IP2_WDOG_W1S"   ,	   0x10701018a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP13_IP2_WDOG_W1S"   ,	   0x1070101aa1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP14_IP2_WDOG_W1S"   ,	   0x1070101ca1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP15_IP2_WDOG_W1S"   ,	   0x1070101ea1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP16_IP2_WDOG_W1S"   ,	   0x10701020a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP17_IP2_WDOG_W1S"   ,	   0x10701022a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP18_IP2_WDOG_W1S"   ,	   0x10701024a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP19_IP2_WDOG_W1S"   ,	   0x10701026a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP20_IP2_WDOG_W1S"   ,	   0x10701028a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP21_IP2_WDOG_W1S"   ,	   0x1070102aa1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP22_IP2_WDOG_W1S"   ,	   0x1070102ca1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP23_IP2_WDOG_W1S"   ,	   0x1070102ea1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP24_IP2_WDOG_W1S"   ,	   0x10701030a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP25_IP2_WDOG_W1S"   ,	   0x10701032a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP26_IP2_WDOG_W1S"   ,	   0x10701034a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP27_IP2_WDOG_W1S"   ,	   0x10701036a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP28_IP2_WDOG_W1S"   ,	   0x10701038a1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP29_IP2_WDOG_W1S"   ,	   0x1070103aa1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP30_IP2_WDOG_W1S"   ,	   0x1070103ca1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP31_IP2_WDOG_W1S"   ,	   0x1070103ea1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"CIU2_EN_PP0_IP2_WRKQ"        ,	   0x1070100090000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP1_IP2_WRKQ"        ,	   0x1070100290000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP2_IP2_WRKQ"        ,	   0x1070100490000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP3_IP2_WRKQ"        ,	   0x1070100690000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP4_IP2_WRKQ"        ,	   0x1070100890000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP5_IP2_WRKQ"        ,	   0x1070100a90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP6_IP2_WRKQ"        ,	   0x1070100c90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP7_IP2_WRKQ"        ,	   0x1070100e90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP8_IP2_WRKQ"        ,	   0x1070101090000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP9_IP2_WRKQ"        ,	   0x1070101290000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP10_IP2_WRKQ"       ,	   0x1070101490000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP11_IP2_WRKQ"       ,	   0x1070101690000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP12_IP2_WRKQ"       ,	   0x1070101890000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP13_IP2_WRKQ"       ,	   0x1070101a90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP14_IP2_WRKQ"       ,	   0x1070101c90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP15_IP2_WRKQ"       ,	   0x1070101e90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP16_IP2_WRKQ"       ,	   0x1070102090000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP17_IP2_WRKQ"       ,	   0x1070102290000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP18_IP2_WRKQ"       ,	   0x1070102490000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP19_IP2_WRKQ"       ,	   0x1070102690000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP20_IP2_WRKQ"       ,	   0x1070102890000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP21_IP2_WRKQ"       ,	   0x1070102a90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP22_IP2_WRKQ"       ,	   0x1070102c90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP23_IP2_WRKQ"       ,	   0x1070102e90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP24_IP2_WRKQ"       ,	   0x1070103090000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP25_IP2_WRKQ"       ,	   0x1070103290000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP26_IP2_WRKQ"       ,	   0x1070103490000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP27_IP2_WRKQ"       ,	   0x1070103690000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP28_IP2_WRKQ"       ,	   0x1070103890000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP29_IP2_WRKQ"       ,	   0x1070103a90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP30_IP2_WRKQ"       ,	   0x1070103c90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP31_IP2_WRKQ"       ,	   0x1070103e90000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"CIU2_EN_PP0_IP2_WRKQ_W1C"    ,	   0x10701000b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP1_IP2_WRKQ_W1C"    ,	   0x10701002b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP2_IP2_WRKQ_W1C"    ,	   0x10701004b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP3_IP2_WRKQ_W1C"    ,	   0x10701006b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP4_IP2_WRKQ_W1C"    ,	   0x10701008b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP5_IP2_WRKQ_W1C"    ,	   0x1070100ab0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP6_IP2_WRKQ_W1C"    ,	   0x1070100cb0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP7_IP2_WRKQ_W1C"    ,	   0x1070100eb0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP8_IP2_WRKQ_W1C"    ,	   0x10701010b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP9_IP2_WRKQ_W1C"    ,	   0x10701012b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP10_IP2_WRKQ_W1C"   ,	   0x10701014b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP11_IP2_WRKQ_W1C"   ,	   0x10701016b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP12_IP2_WRKQ_W1C"   ,	   0x10701018b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP13_IP2_WRKQ_W1C"   ,	   0x1070101ab0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP14_IP2_WRKQ_W1C"   ,	   0x1070101cb0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP15_IP2_WRKQ_W1C"   ,	   0x1070101eb0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP16_IP2_WRKQ_W1C"   ,	   0x10701020b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP17_IP2_WRKQ_W1C"   ,	   0x10701022b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP18_IP2_WRKQ_W1C"   ,	   0x10701024b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP19_IP2_WRKQ_W1C"   ,	   0x10701026b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP20_IP2_WRKQ_W1C"   ,	   0x10701028b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP21_IP2_WRKQ_W1C"   ,	   0x1070102ab0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP22_IP2_WRKQ_W1C"   ,	   0x1070102cb0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP23_IP2_WRKQ_W1C"   ,	   0x1070102eb0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP24_IP2_WRKQ_W1C"   ,	   0x10701030b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP25_IP2_WRKQ_W1C"   ,	   0x10701032b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP26_IP2_WRKQ_W1C"   ,	   0x10701034b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP27_IP2_WRKQ_W1C"   ,	   0x10701036b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP28_IP2_WRKQ_W1C"   ,	   0x10701038b0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP29_IP2_WRKQ_W1C"   ,	   0x1070103ab0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP30_IP2_WRKQ_W1C"   ,	   0x1070103cb0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP31_IP2_WRKQ_W1C"   ,	   0x1070103eb0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"CIU2_EN_PP0_IP2_WRKQ_W1S"    ,	   0x10701000a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP1_IP2_WRKQ_W1S"    ,	   0x10701002a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP2_IP2_WRKQ_W1S"    ,	   0x10701004a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP3_IP2_WRKQ_W1S"    ,	   0x10701006a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP4_IP2_WRKQ_W1S"    ,	   0x10701008a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP5_IP2_WRKQ_W1S"    ,	   0x1070100aa0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP6_IP2_WRKQ_W1S"    ,	   0x1070100ca0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP7_IP2_WRKQ_W1S"    ,	   0x1070100ea0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP8_IP2_WRKQ_W1S"    ,	   0x10701010a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP9_IP2_WRKQ_W1S"    ,	   0x10701012a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP10_IP2_WRKQ_W1S"   ,	   0x10701014a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP11_IP2_WRKQ_W1S"   ,	   0x10701016a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP12_IP2_WRKQ_W1S"   ,	   0x10701018a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP13_IP2_WRKQ_W1S"   ,	   0x1070101aa0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP14_IP2_WRKQ_W1S"   ,	   0x1070101ca0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP15_IP2_WRKQ_W1S"   ,	   0x1070101ea0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP16_IP2_WRKQ_W1S"   ,	   0x10701020a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP17_IP2_WRKQ_W1S"   ,	   0x10701022a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP18_IP2_WRKQ_W1S"   ,	   0x10701024a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP19_IP2_WRKQ_W1S"   ,	   0x10701026a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP20_IP2_WRKQ_W1S"   ,	   0x10701028a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP21_IP2_WRKQ_W1S"   ,	   0x1070102aa0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP22_IP2_WRKQ_W1S"   ,	   0x1070102ca0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP23_IP2_WRKQ_W1S"   ,	   0x1070102ea0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP24_IP2_WRKQ_W1S"   ,	   0x10701030a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP25_IP2_WRKQ_W1S"   ,	   0x10701032a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP26_IP2_WRKQ_W1S"   ,	   0x10701034a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP27_IP2_WRKQ_W1S"   ,	   0x10701036a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP28_IP2_WRKQ_W1S"   ,	   0x10701038a0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP29_IP2_WRKQ_W1S"   ,	   0x1070103aa0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP30_IP2_WRKQ_W1S"   ,	   0x1070103ca0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP31_IP2_WRKQ_W1S"   ,	   0x1070103ea0000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"CIU2_EN_PP0_IP3_GPIO"        ,	   0x1070100097200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP1_IP3_GPIO"        ,	   0x1070100297200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP2_IP3_GPIO"        ,	   0x1070100497200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP3_IP3_GPIO"        ,	   0x1070100697200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP4_IP3_GPIO"        ,	   0x1070100897200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP5_IP3_GPIO"        ,	   0x1070100a97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP6_IP3_GPIO"        ,	   0x1070100c97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP7_IP3_GPIO"        ,	   0x1070100e97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP8_IP3_GPIO"        ,	   0x1070101097200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP9_IP3_GPIO"        ,	   0x1070101297200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP10_IP3_GPIO"       ,	   0x1070101497200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP11_IP3_GPIO"       ,	   0x1070101697200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP12_IP3_GPIO"       ,	   0x1070101897200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP13_IP3_GPIO"       ,	   0x1070101a97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP14_IP3_GPIO"       ,	   0x1070101c97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP15_IP3_GPIO"       ,	   0x1070101e97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP16_IP3_GPIO"       ,	   0x1070102097200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP17_IP3_GPIO"       ,	   0x1070102297200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP18_IP3_GPIO"       ,	   0x1070102497200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP19_IP3_GPIO"       ,	   0x1070102697200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP20_IP3_GPIO"       ,	   0x1070102897200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP21_IP3_GPIO"       ,	   0x1070102a97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP22_IP3_GPIO"       ,	   0x1070102c97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP23_IP3_GPIO"       ,	   0x1070102e97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP24_IP3_GPIO"       ,	   0x1070103097200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP25_IP3_GPIO"       ,	   0x1070103297200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP26_IP3_GPIO"       ,	   0x1070103497200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP27_IP3_GPIO"       ,	   0x1070103697200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP28_IP3_GPIO"       ,	   0x1070103897200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP29_IP3_GPIO"       ,	   0x1070103a97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP30_IP3_GPIO"       ,	   0x1070103c97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP31_IP3_GPIO"       ,	   0x1070103e97200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"CIU2_EN_PP0_IP3_GPIO_W1C"    ,	   0x10701000b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP1_IP3_GPIO_W1C"    ,	   0x10701002b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP2_IP3_GPIO_W1C"    ,	   0x10701004b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP3_IP3_GPIO_W1C"    ,	   0x10701006b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP4_IP3_GPIO_W1C"    ,	   0x10701008b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP5_IP3_GPIO_W1C"    ,	   0x1070100ab7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP6_IP3_GPIO_W1C"    ,	   0x1070100cb7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP7_IP3_GPIO_W1C"    ,	   0x1070100eb7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP8_IP3_GPIO_W1C"    ,	   0x10701010b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP9_IP3_GPIO_W1C"    ,	   0x10701012b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP10_IP3_GPIO_W1C"   ,	   0x10701014b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP11_IP3_GPIO_W1C"   ,	   0x10701016b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP12_IP3_GPIO_W1C"   ,	   0x10701018b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP13_IP3_GPIO_W1C"   ,	   0x1070101ab7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP14_IP3_GPIO_W1C"   ,	   0x1070101cb7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP15_IP3_GPIO_W1C"   ,	   0x1070101eb7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP16_IP3_GPIO_W1C"   ,	   0x10701020b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP17_IP3_GPIO_W1C"   ,	   0x10701022b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP18_IP3_GPIO_W1C"   ,	   0x10701024b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP19_IP3_GPIO_W1C"   ,	   0x10701026b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP20_IP3_GPIO_W1C"   ,	   0x10701028b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP21_IP3_GPIO_W1C"   ,	   0x1070102ab7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP22_IP3_GPIO_W1C"   ,	   0x1070102cb7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP23_IP3_GPIO_W1C"   ,	   0x1070102eb7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP24_IP3_GPIO_W1C"   ,	   0x10701030b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP25_IP3_GPIO_W1C"   ,	   0x10701032b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP26_IP3_GPIO_W1C"   ,	   0x10701034b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP27_IP3_GPIO_W1C"   ,	   0x10701036b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP28_IP3_GPIO_W1C"   ,	   0x10701038b7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP29_IP3_GPIO_W1C"   ,	   0x1070103ab7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP30_IP3_GPIO_W1C"   ,	   0x1070103cb7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP31_IP3_GPIO_W1C"   ,	   0x1070103eb7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	131},
+	{"CIU2_EN_PP0_IP3_GPIO_W1S"    ,	   0x10701000a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP1_IP3_GPIO_W1S"    ,	   0x10701002a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP2_IP3_GPIO_W1S"    ,	   0x10701004a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP3_IP3_GPIO_W1S"    ,	   0x10701006a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP4_IP3_GPIO_W1S"    ,	   0x10701008a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP5_IP3_GPIO_W1S"    ,	   0x1070100aa7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP6_IP3_GPIO_W1S"    ,	   0x1070100ca7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP7_IP3_GPIO_W1S"    ,	   0x1070100ea7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP8_IP3_GPIO_W1S"    ,	   0x10701010a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP9_IP3_GPIO_W1S"    ,	   0x10701012a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP10_IP3_GPIO_W1S"   ,	   0x10701014a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP11_IP3_GPIO_W1S"   ,	   0x10701016a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP12_IP3_GPIO_W1S"   ,	   0x10701018a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP13_IP3_GPIO_W1S"   ,	   0x1070101aa7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP14_IP3_GPIO_W1S"   ,	   0x1070101ca7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP15_IP3_GPIO_W1S"   ,	   0x1070101ea7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP16_IP3_GPIO_W1S"   ,	   0x10701020a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP17_IP3_GPIO_W1S"   ,	   0x10701022a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP18_IP3_GPIO_W1S"   ,	   0x10701024a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP19_IP3_GPIO_W1S"   ,	   0x10701026a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP20_IP3_GPIO_W1S"   ,	   0x10701028a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP21_IP3_GPIO_W1S"   ,	   0x1070102aa7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP22_IP3_GPIO_W1S"   ,	   0x1070102ca7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP23_IP3_GPIO_W1S"   ,	   0x1070102ea7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP24_IP3_GPIO_W1S"   ,	   0x10701030a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP25_IP3_GPIO_W1S"   ,	   0x10701032a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP26_IP3_GPIO_W1S"   ,	   0x10701034a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP27_IP3_GPIO_W1S"   ,	   0x10701036a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP28_IP3_GPIO_W1S"   ,	   0x10701038a7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP29_IP3_GPIO_W1S"   ,	   0x1070103aa7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP30_IP3_GPIO_W1S"   ,	   0x1070103ca7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP31_IP3_GPIO_W1S"   ,	   0x1070103ea7200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	132},
+	{"CIU2_EN_PP0_IP3_IO"          ,	   0x1070100094200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP1_IP3_IO"          ,	   0x1070100294200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP2_IP3_IO"          ,	   0x1070100494200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP3_IP3_IO"          ,	   0x1070100694200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP4_IP3_IO"          ,	   0x1070100894200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP5_IP3_IO"          ,	   0x1070100a94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP6_IP3_IO"          ,	   0x1070100c94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP7_IP3_IO"          ,	   0x1070100e94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP8_IP3_IO"          ,	   0x1070101094200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP9_IP3_IO"          ,	   0x1070101294200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP10_IP3_IO"         ,	   0x1070101494200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP11_IP3_IO"         ,	   0x1070101694200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP12_IP3_IO"         ,	   0x1070101894200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP13_IP3_IO"         ,	   0x1070101a94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP14_IP3_IO"         ,	   0x1070101c94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP15_IP3_IO"         ,	   0x1070101e94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP16_IP3_IO"         ,	   0x1070102094200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP17_IP3_IO"         ,	   0x1070102294200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP18_IP3_IO"         ,	   0x1070102494200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP19_IP3_IO"         ,	   0x1070102694200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP20_IP3_IO"         ,	   0x1070102894200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP21_IP3_IO"         ,	   0x1070102a94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP22_IP3_IO"         ,	   0x1070102c94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP23_IP3_IO"         ,	   0x1070102e94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP24_IP3_IO"         ,	   0x1070103094200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP25_IP3_IO"         ,	   0x1070103294200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP26_IP3_IO"         ,	   0x1070103494200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP27_IP3_IO"         ,	   0x1070103694200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP28_IP3_IO"         ,	   0x1070103894200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP29_IP3_IO"         ,	   0x1070103a94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP30_IP3_IO"         ,	   0x1070103c94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP31_IP3_IO"         ,	   0x1070103e94200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	133},
+	{"CIU2_EN_PP0_IP3_IO_W1C"      ,	   0x10701000b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP1_IP3_IO_W1C"      ,	   0x10701002b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP2_IP3_IO_W1C"      ,	   0x10701004b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP3_IP3_IO_W1C"      ,	   0x10701006b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP4_IP3_IO_W1C"      ,	   0x10701008b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP5_IP3_IO_W1C"      ,	   0x1070100ab4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP6_IP3_IO_W1C"      ,	   0x1070100cb4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP7_IP3_IO_W1C"      ,	   0x1070100eb4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP8_IP3_IO_W1C"      ,	   0x10701010b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP9_IP3_IO_W1C"      ,	   0x10701012b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP10_IP3_IO_W1C"     ,	   0x10701014b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP11_IP3_IO_W1C"     ,	   0x10701016b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP12_IP3_IO_W1C"     ,	   0x10701018b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP13_IP3_IO_W1C"     ,	   0x1070101ab4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP14_IP3_IO_W1C"     ,	   0x1070101cb4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP15_IP3_IO_W1C"     ,	   0x1070101eb4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP16_IP3_IO_W1C"     ,	   0x10701020b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP17_IP3_IO_W1C"     ,	   0x10701022b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP18_IP3_IO_W1C"     ,	   0x10701024b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP19_IP3_IO_W1C"     ,	   0x10701026b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP20_IP3_IO_W1C"     ,	   0x10701028b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP21_IP3_IO_W1C"     ,	   0x1070102ab4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP22_IP3_IO_W1C"     ,	   0x1070102cb4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP23_IP3_IO_W1C"     ,	   0x1070102eb4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP24_IP3_IO_W1C"     ,	   0x10701030b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP25_IP3_IO_W1C"     ,	   0x10701032b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP26_IP3_IO_W1C"     ,	   0x10701034b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP27_IP3_IO_W1C"     ,	   0x10701036b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP28_IP3_IO_W1C"     ,	   0x10701038b4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP29_IP3_IO_W1C"     ,	   0x1070103ab4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP30_IP3_IO_W1C"     ,	   0x1070103cb4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP31_IP3_IO_W1C"     ,	   0x1070103eb4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	134},
+	{"CIU2_EN_PP0_IP3_IO_W1S"      ,	   0x10701000a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP1_IP3_IO_W1S"      ,	   0x10701002a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP2_IP3_IO_W1S"      ,	   0x10701004a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP3_IP3_IO_W1S"      ,	   0x10701006a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP4_IP3_IO_W1S"      ,	   0x10701008a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP5_IP3_IO_W1S"      ,	   0x1070100aa4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP6_IP3_IO_W1S"      ,	   0x1070100ca4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP7_IP3_IO_W1S"      ,	   0x1070100ea4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP8_IP3_IO_W1S"      ,	   0x10701010a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP9_IP3_IO_W1S"      ,	   0x10701012a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP10_IP3_IO_W1S"     ,	   0x10701014a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP11_IP3_IO_W1S"     ,	   0x10701016a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP12_IP3_IO_W1S"     ,	   0x10701018a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP13_IP3_IO_W1S"     ,	   0x1070101aa4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP14_IP3_IO_W1S"     ,	   0x1070101ca4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP15_IP3_IO_W1S"     ,	   0x1070101ea4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP16_IP3_IO_W1S"     ,	   0x10701020a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP17_IP3_IO_W1S"     ,	   0x10701022a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP18_IP3_IO_W1S"     ,	   0x10701024a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP19_IP3_IO_W1S"     ,	   0x10701026a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP20_IP3_IO_W1S"     ,	   0x10701028a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP21_IP3_IO_W1S"     ,	   0x1070102aa4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP22_IP3_IO_W1S"     ,	   0x1070102ca4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP23_IP3_IO_W1S"     ,	   0x1070102ea4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP24_IP3_IO_W1S"     ,	   0x10701030a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP25_IP3_IO_W1S"     ,	   0x10701032a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP26_IP3_IO_W1S"     ,	   0x10701034a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP27_IP3_IO_W1S"     ,	   0x10701036a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP28_IP3_IO_W1S"     ,	   0x10701038a4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP29_IP3_IO_W1S"     ,	   0x1070103aa4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP30_IP3_IO_W1S"     ,	   0x1070103ca4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP31_IP3_IO_W1S"     ,	   0x1070103ea4200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	135},
+	{"CIU2_EN_PP0_IP3_MBOX"        ,	   0x1070100098200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP1_IP3_MBOX"        ,	   0x1070100298200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP2_IP3_MBOX"        ,	   0x1070100498200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP3_IP3_MBOX"        ,	   0x1070100698200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP4_IP3_MBOX"        ,	   0x1070100898200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP5_IP3_MBOX"        ,	   0x1070100a98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP6_IP3_MBOX"        ,	   0x1070100c98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP7_IP3_MBOX"        ,	   0x1070100e98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP8_IP3_MBOX"        ,	   0x1070101098200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP9_IP3_MBOX"        ,	   0x1070101298200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP10_IP3_MBOX"       ,	   0x1070101498200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP11_IP3_MBOX"       ,	   0x1070101698200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP12_IP3_MBOX"       ,	   0x1070101898200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP13_IP3_MBOX"       ,	   0x1070101a98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP14_IP3_MBOX"       ,	   0x1070101c98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP15_IP3_MBOX"       ,	   0x1070101e98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP16_IP3_MBOX"       ,	   0x1070102098200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP17_IP3_MBOX"       ,	   0x1070102298200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP18_IP3_MBOX"       ,	   0x1070102498200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP19_IP3_MBOX"       ,	   0x1070102698200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP20_IP3_MBOX"       ,	   0x1070102898200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP21_IP3_MBOX"       ,	   0x1070102a98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP22_IP3_MBOX"       ,	   0x1070102c98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP23_IP3_MBOX"       ,	   0x1070102e98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP24_IP3_MBOX"       ,	   0x1070103098200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP25_IP3_MBOX"       ,	   0x1070103298200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP26_IP3_MBOX"       ,	   0x1070103498200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP27_IP3_MBOX"       ,	   0x1070103698200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP28_IP3_MBOX"       ,	   0x1070103898200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP29_IP3_MBOX"       ,	   0x1070103a98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP30_IP3_MBOX"       ,	   0x1070103c98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP31_IP3_MBOX"       ,	   0x1070103e98200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	136},
+	{"CIU2_EN_PP0_IP3_MBOX_W1C"    ,	   0x10701000b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP1_IP3_MBOX_W1C"    ,	   0x10701002b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP2_IP3_MBOX_W1C"    ,	   0x10701004b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP3_IP3_MBOX_W1C"    ,	   0x10701006b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP4_IP3_MBOX_W1C"    ,	   0x10701008b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP5_IP3_MBOX_W1C"    ,	   0x1070100ab8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP6_IP3_MBOX_W1C"    ,	   0x1070100cb8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP7_IP3_MBOX_W1C"    ,	   0x1070100eb8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP8_IP3_MBOX_W1C"    ,	   0x10701010b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP9_IP3_MBOX_W1C"    ,	   0x10701012b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP10_IP3_MBOX_W1C"   ,	   0x10701014b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP11_IP3_MBOX_W1C"   ,	   0x10701016b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP12_IP3_MBOX_W1C"   ,	   0x10701018b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP13_IP3_MBOX_W1C"   ,	   0x1070101ab8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP14_IP3_MBOX_W1C"   ,	   0x1070101cb8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP15_IP3_MBOX_W1C"   ,	   0x1070101eb8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP16_IP3_MBOX_W1C"   ,	   0x10701020b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP17_IP3_MBOX_W1C"   ,	   0x10701022b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP18_IP3_MBOX_W1C"   ,	   0x10701024b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP19_IP3_MBOX_W1C"   ,	   0x10701026b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP20_IP3_MBOX_W1C"   ,	   0x10701028b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP21_IP3_MBOX_W1C"   ,	   0x1070102ab8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP22_IP3_MBOX_W1C"   ,	   0x1070102cb8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP23_IP3_MBOX_W1C"   ,	   0x1070102eb8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP24_IP3_MBOX_W1C"   ,	   0x10701030b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP25_IP3_MBOX_W1C"   ,	   0x10701032b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP26_IP3_MBOX_W1C"   ,	   0x10701034b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP27_IP3_MBOX_W1C"   ,	   0x10701036b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP28_IP3_MBOX_W1C"   ,	   0x10701038b8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP29_IP3_MBOX_W1C"   ,	   0x1070103ab8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP30_IP3_MBOX_W1C"   ,	   0x1070103cb8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP31_IP3_MBOX_W1C"   ,	   0x1070103eb8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	137},
+	{"CIU2_EN_PP0_IP3_MBOX_W1S"    ,	   0x10701000a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP1_IP3_MBOX_W1S"    ,	   0x10701002a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP2_IP3_MBOX_W1S"    ,	   0x10701004a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP3_IP3_MBOX_W1S"    ,	   0x10701006a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP4_IP3_MBOX_W1S"    ,	   0x10701008a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP5_IP3_MBOX_W1S"    ,	   0x1070100aa8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP6_IP3_MBOX_W1S"    ,	   0x1070100ca8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP7_IP3_MBOX_W1S"    ,	   0x1070100ea8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP8_IP3_MBOX_W1S"    ,	   0x10701010a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP9_IP3_MBOX_W1S"    ,	   0x10701012a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP10_IP3_MBOX_W1S"   ,	   0x10701014a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP11_IP3_MBOX_W1S"   ,	   0x10701016a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP12_IP3_MBOX_W1S"   ,	   0x10701018a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP13_IP3_MBOX_W1S"   ,	   0x1070101aa8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP14_IP3_MBOX_W1S"   ,	   0x1070101ca8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP15_IP3_MBOX_W1S"   ,	   0x1070101ea8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP16_IP3_MBOX_W1S"   ,	   0x10701020a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP17_IP3_MBOX_W1S"   ,	   0x10701022a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP18_IP3_MBOX_W1S"   ,	   0x10701024a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP19_IP3_MBOX_W1S"   ,	   0x10701026a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP20_IP3_MBOX_W1S"   ,	   0x10701028a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP21_IP3_MBOX_W1S"   ,	   0x1070102aa8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP22_IP3_MBOX_W1S"   ,	   0x1070102ca8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP23_IP3_MBOX_W1S"   ,	   0x1070102ea8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP24_IP3_MBOX_W1S"   ,	   0x10701030a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP25_IP3_MBOX_W1S"   ,	   0x10701032a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP26_IP3_MBOX_W1S"   ,	   0x10701034a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP27_IP3_MBOX_W1S"   ,	   0x10701036a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP28_IP3_MBOX_W1S"   ,	   0x10701038a8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP29_IP3_MBOX_W1S"   ,	   0x1070103aa8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP30_IP3_MBOX_W1S"   ,	   0x1070103ca8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP31_IP3_MBOX_W1S"   ,	   0x1070103ea8200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	138},
+	{"CIU2_EN_PP0_IP3_MEM"         ,	   0x1070100095200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP1_IP3_MEM"         ,	   0x1070100295200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP2_IP3_MEM"         ,	   0x1070100495200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP3_IP3_MEM"         ,	   0x1070100695200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP4_IP3_MEM"         ,	   0x1070100895200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP5_IP3_MEM"         ,	   0x1070100a95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP6_IP3_MEM"         ,	   0x1070100c95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP7_IP3_MEM"         ,	   0x1070100e95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP8_IP3_MEM"         ,	   0x1070101095200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP9_IP3_MEM"         ,	   0x1070101295200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP10_IP3_MEM"        ,	   0x1070101495200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP11_IP3_MEM"        ,	   0x1070101695200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP12_IP3_MEM"        ,	   0x1070101895200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP13_IP3_MEM"        ,	   0x1070101a95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP14_IP3_MEM"        ,	   0x1070101c95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP15_IP3_MEM"        ,	   0x1070101e95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP16_IP3_MEM"        ,	   0x1070102095200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP17_IP3_MEM"        ,	   0x1070102295200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP18_IP3_MEM"        ,	   0x1070102495200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP19_IP3_MEM"        ,	   0x1070102695200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP20_IP3_MEM"        ,	   0x1070102895200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP21_IP3_MEM"        ,	   0x1070102a95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP22_IP3_MEM"        ,	   0x1070102c95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP23_IP3_MEM"        ,	   0x1070102e95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP24_IP3_MEM"        ,	   0x1070103095200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP25_IP3_MEM"        ,	   0x1070103295200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP26_IP3_MEM"        ,	   0x1070103495200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP27_IP3_MEM"        ,	   0x1070103695200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP28_IP3_MEM"        ,	   0x1070103895200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP29_IP3_MEM"        ,	   0x1070103a95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP30_IP3_MEM"        ,	   0x1070103c95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP31_IP3_MEM"        ,	   0x1070103e95200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	139},
+	{"CIU2_EN_PP0_IP3_MEM_W1C"     ,	   0x10701000b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP1_IP3_MEM_W1C"     ,	   0x10701002b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP2_IP3_MEM_W1C"     ,	   0x10701004b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP3_IP3_MEM_W1C"     ,	   0x10701006b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP4_IP3_MEM_W1C"     ,	   0x10701008b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP5_IP3_MEM_W1C"     ,	   0x1070100ab5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP6_IP3_MEM_W1C"     ,	   0x1070100cb5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP7_IP3_MEM_W1C"     ,	   0x1070100eb5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP8_IP3_MEM_W1C"     ,	   0x10701010b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP9_IP3_MEM_W1C"     ,	   0x10701012b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP10_IP3_MEM_W1C"    ,	   0x10701014b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP11_IP3_MEM_W1C"    ,	   0x10701016b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP12_IP3_MEM_W1C"    ,	   0x10701018b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP13_IP3_MEM_W1C"    ,	   0x1070101ab5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP14_IP3_MEM_W1C"    ,	   0x1070101cb5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP15_IP3_MEM_W1C"    ,	   0x1070101eb5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP16_IP3_MEM_W1C"    ,	   0x10701020b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP17_IP3_MEM_W1C"    ,	   0x10701022b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP18_IP3_MEM_W1C"    ,	   0x10701024b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP19_IP3_MEM_W1C"    ,	   0x10701026b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP20_IP3_MEM_W1C"    ,	   0x10701028b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP21_IP3_MEM_W1C"    ,	   0x1070102ab5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP22_IP3_MEM_W1C"    ,	   0x1070102cb5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP23_IP3_MEM_W1C"    ,	   0x1070102eb5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP24_IP3_MEM_W1C"    ,	   0x10701030b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP25_IP3_MEM_W1C"    ,	   0x10701032b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP26_IP3_MEM_W1C"    ,	   0x10701034b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP27_IP3_MEM_W1C"    ,	   0x10701036b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP28_IP3_MEM_W1C"    ,	   0x10701038b5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP29_IP3_MEM_W1C"    ,	   0x1070103ab5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP30_IP3_MEM_W1C"    ,	   0x1070103cb5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP31_IP3_MEM_W1C"    ,	   0x1070103eb5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	140},
+	{"CIU2_EN_PP0_IP3_MEM_W1S"     ,	   0x10701000a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP1_IP3_MEM_W1S"     ,	   0x10701002a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP2_IP3_MEM_W1S"     ,	   0x10701004a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP3_IP3_MEM_W1S"     ,	   0x10701006a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP4_IP3_MEM_W1S"     ,	   0x10701008a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP5_IP3_MEM_W1S"     ,	   0x1070100aa5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP6_IP3_MEM_W1S"     ,	   0x1070100ca5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP7_IP3_MEM_W1S"     ,	   0x1070100ea5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP8_IP3_MEM_W1S"     ,	   0x10701010a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP9_IP3_MEM_W1S"     ,	   0x10701012a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP10_IP3_MEM_W1S"    ,	   0x10701014a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP11_IP3_MEM_W1S"    ,	   0x10701016a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP12_IP3_MEM_W1S"    ,	   0x10701018a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP13_IP3_MEM_W1S"    ,	   0x1070101aa5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP14_IP3_MEM_W1S"    ,	   0x1070101ca5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP15_IP3_MEM_W1S"    ,	   0x1070101ea5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP16_IP3_MEM_W1S"    ,	   0x10701020a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP17_IP3_MEM_W1S"    ,	   0x10701022a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP18_IP3_MEM_W1S"    ,	   0x10701024a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP19_IP3_MEM_W1S"    ,	   0x10701026a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP20_IP3_MEM_W1S"    ,	   0x10701028a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP21_IP3_MEM_W1S"    ,	   0x1070102aa5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP22_IP3_MEM_W1S"    ,	   0x1070102ca5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP23_IP3_MEM_W1S"    ,	   0x1070102ea5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP24_IP3_MEM_W1S"    ,	   0x10701030a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP25_IP3_MEM_W1S"    ,	   0x10701032a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP26_IP3_MEM_W1S"    ,	   0x10701034a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP27_IP3_MEM_W1S"    ,	   0x10701036a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP28_IP3_MEM_W1S"    ,	   0x10701038a5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP29_IP3_MEM_W1S"    ,	   0x1070103aa5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP30_IP3_MEM_W1S"    ,	   0x1070103ca5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP31_IP3_MEM_W1S"    ,	   0x1070103ea5200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"CIU2_EN_PP0_IP3_MIO"         ,	   0x1070100093200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP1_IP3_MIO"         ,	   0x1070100293200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP2_IP3_MIO"         ,	   0x1070100493200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP3_IP3_MIO"         ,	   0x1070100693200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP4_IP3_MIO"         ,	   0x1070100893200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP5_IP3_MIO"         ,	   0x1070100a93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP6_IP3_MIO"         ,	   0x1070100c93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP7_IP3_MIO"         ,	   0x1070100e93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP8_IP3_MIO"         ,	   0x1070101093200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP9_IP3_MIO"         ,	   0x1070101293200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP10_IP3_MIO"        ,	   0x1070101493200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP11_IP3_MIO"        ,	   0x1070101693200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP12_IP3_MIO"        ,	   0x1070101893200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP13_IP3_MIO"        ,	   0x1070101a93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP14_IP3_MIO"        ,	   0x1070101c93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP15_IP3_MIO"        ,	   0x1070101e93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP16_IP3_MIO"        ,	   0x1070102093200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP17_IP3_MIO"        ,	   0x1070102293200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP18_IP3_MIO"        ,	   0x1070102493200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP19_IP3_MIO"        ,	   0x1070102693200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP20_IP3_MIO"        ,	   0x1070102893200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP21_IP3_MIO"        ,	   0x1070102a93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP22_IP3_MIO"        ,	   0x1070102c93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP23_IP3_MIO"        ,	   0x1070102e93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP24_IP3_MIO"        ,	   0x1070103093200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP25_IP3_MIO"        ,	   0x1070103293200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP26_IP3_MIO"        ,	   0x1070103493200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP27_IP3_MIO"        ,	   0x1070103693200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP28_IP3_MIO"        ,	   0x1070103893200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP29_IP3_MIO"        ,	   0x1070103a93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP30_IP3_MIO"        ,	   0x1070103c93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP31_IP3_MIO"        ,	   0x1070103e93200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"CIU2_EN_PP0_IP3_MIO_W1C"     ,	   0x10701000b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP1_IP3_MIO_W1C"     ,	   0x10701002b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP2_IP3_MIO_W1C"     ,	   0x10701004b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP3_IP3_MIO_W1C"     ,	   0x10701006b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP4_IP3_MIO_W1C"     ,	   0x10701008b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP5_IP3_MIO_W1C"     ,	   0x1070100ab3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP6_IP3_MIO_W1C"     ,	   0x1070100cb3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP7_IP3_MIO_W1C"     ,	   0x1070100eb3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP8_IP3_MIO_W1C"     ,	   0x10701010b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP9_IP3_MIO_W1C"     ,	   0x10701012b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP10_IP3_MIO_W1C"    ,	   0x10701014b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP11_IP3_MIO_W1C"    ,	   0x10701016b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP12_IP3_MIO_W1C"    ,	   0x10701018b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP13_IP3_MIO_W1C"    ,	   0x1070101ab3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP14_IP3_MIO_W1C"    ,	   0x1070101cb3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP15_IP3_MIO_W1C"    ,	   0x1070101eb3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP16_IP3_MIO_W1C"    ,	   0x10701020b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP17_IP3_MIO_W1C"    ,	   0x10701022b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP18_IP3_MIO_W1C"    ,	   0x10701024b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP19_IP3_MIO_W1C"    ,	   0x10701026b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP20_IP3_MIO_W1C"    ,	   0x10701028b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP21_IP3_MIO_W1C"    ,	   0x1070102ab3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP22_IP3_MIO_W1C"    ,	   0x1070102cb3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP23_IP3_MIO_W1C"    ,	   0x1070102eb3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP24_IP3_MIO_W1C"    ,	   0x10701030b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP25_IP3_MIO_W1C"    ,	   0x10701032b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP26_IP3_MIO_W1C"    ,	   0x10701034b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP27_IP3_MIO_W1C"    ,	   0x10701036b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP28_IP3_MIO_W1C"    ,	   0x10701038b3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP29_IP3_MIO_W1C"    ,	   0x1070103ab3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP30_IP3_MIO_W1C"    ,	   0x1070103cb3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP31_IP3_MIO_W1C"    ,	   0x1070103eb3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"CIU2_EN_PP0_IP3_MIO_W1S"     ,	   0x10701000a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP1_IP3_MIO_W1S"     ,	   0x10701002a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP2_IP3_MIO_W1S"     ,	   0x10701004a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP3_IP3_MIO_W1S"     ,	   0x10701006a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP4_IP3_MIO_W1S"     ,	   0x10701008a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP5_IP3_MIO_W1S"     ,	   0x1070100aa3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP6_IP3_MIO_W1S"     ,	   0x1070100ca3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP7_IP3_MIO_W1S"     ,	   0x1070100ea3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP8_IP3_MIO_W1S"     ,	   0x10701010a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP9_IP3_MIO_W1S"     ,	   0x10701012a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP10_IP3_MIO_W1S"    ,	   0x10701014a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP11_IP3_MIO_W1S"    ,	   0x10701016a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP12_IP3_MIO_W1S"    ,	   0x10701018a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP13_IP3_MIO_W1S"    ,	   0x1070101aa3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP14_IP3_MIO_W1S"    ,	   0x1070101ca3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP15_IP3_MIO_W1S"    ,	   0x1070101ea3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP16_IP3_MIO_W1S"    ,	   0x10701020a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP17_IP3_MIO_W1S"    ,	   0x10701022a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP18_IP3_MIO_W1S"    ,	   0x10701024a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP19_IP3_MIO_W1S"    ,	   0x10701026a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP20_IP3_MIO_W1S"    ,	   0x10701028a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP21_IP3_MIO_W1S"    ,	   0x1070102aa3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP22_IP3_MIO_W1S"    ,	   0x1070102ca3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP23_IP3_MIO_W1S"    ,	   0x1070102ea3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP24_IP3_MIO_W1S"    ,	   0x10701030a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP25_IP3_MIO_W1S"    ,	   0x10701032a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP26_IP3_MIO_W1S"    ,	   0x10701034a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP27_IP3_MIO_W1S"    ,	   0x10701036a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP28_IP3_MIO_W1S"    ,	   0x10701038a3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP29_IP3_MIO_W1S"    ,	   0x1070103aa3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP30_IP3_MIO_W1S"    ,	   0x1070103ca3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP31_IP3_MIO_W1S"    ,	   0x1070103ea3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"CIU2_EN_PP0_IP3_PKT"         ,	   0x1070100096200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP1_IP3_PKT"         ,	   0x1070100296200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP2_IP3_PKT"         ,	   0x1070100496200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP3_IP3_PKT"         ,	   0x1070100696200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP4_IP3_PKT"         ,	   0x1070100896200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP5_IP3_PKT"         ,	   0x1070100a96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP6_IP3_PKT"         ,	   0x1070100c96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP7_IP3_PKT"         ,	   0x1070100e96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP8_IP3_PKT"         ,	   0x1070101096200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP9_IP3_PKT"         ,	   0x1070101296200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP10_IP3_PKT"        ,	   0x1070101496200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP11_IP3_PKT"        ,	   0x1070101696200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP12_IP3_PKT"        ,	   0x1070101896200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP13_IP3_PKT"        ,	   0x1070101a96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP14_IP3_PKT"        ,	   0x1070101c96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP15_IP3_PKT"        ,	   0x1070101e96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP16_IP3_PKT"        ,	   0x1070102096200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP17_IP3_PKT"        ,	   0x1070102296200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP18_IP3_PKT"        ,	   0x1070102496200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP19_IP3_PKT"        ,	   0x1070102696200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP20_IP3_PKT"        ,	   0x1070102896200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP21_IP3_PKT"        ,	   0x1070102a96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP22_IP3_PKT"        ,	   0x1070102c96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP23_IP3_PKT"        ,	   0x1070102e96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP24_IP3_PKT"        ,	   0x1070103096200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP25_IP3_PKT"        ,	   0x1070103296200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP26_IP3_PKT"        ,	   0x1070103496200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP27_IP3_PKT"        ,	   0x1070103696200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP28_IP3_PKT"        ,	   0x1070103896200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP29_IP3_PKT"        ,	   0x1070103a96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP30_IP3_PKT"        ,	   0x1070103c96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP31_IP3_PKT"        ,	   0x1070103e96200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"CIU2_EN_PP0_IP3_PKT_W1C"     ,	   0x10701000b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP1_IP3_PKT_W1C"     ,	   0x10701002b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP2_IP3_PKT_W1C"     ,	   0x10701004b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP3_IP3_PKT_W1C"     ,	   0x10701006b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP4_IP3_PKT_W1C"     ,	   0x10701008b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP5_IP3_PKT_W1C"     ,	   0x1070100ab6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP6_IP3_PKT_W1C"     ,	   0x1070100cb6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP7_IP3_PKT_W1C"     ,	   0x1070100eb6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP8_IP3_PKT_W1C"     ,	   0x10701010b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP9_IP3_PKT_W1C"     ,	   0x10701012b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP10_IP3_PKT_W1C"    ,	   0x10701014b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP11_IP3_PKT_W1C"    ,	   0x10701016b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP12_IP3_PKT_W1C"    ,	   0x10701018b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP13_IP3_PKT_W1C"    ,	   0x1070101ab6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP14_IP3_PKT_W1C"    ,	   0x1070101cb6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP15_IP3_PKT_W1C"    ,	   0x1070101eb6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP16_IP3_PKT_W1C"    ,	   0x10701020b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP17_IP3_PKT_W1C"    ,	   0x10701022b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP18_IP3_PKT_W1C"    ,	   0x10701024b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP19_IP3_PKT_W1C"    ,	   0x10701026b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP20_IP3_PKT_W1C"    ,	   0x10701028b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP21_IP3_PKT_W1C"    ,	   0x1070102ab6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP22_IP3_PKT_W1C"    ,	   0x1070102cb6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP23_IP3_PKT_W1C"    ,	   0x1070102eb6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP24_IP3_PKT_W1C"    ,	   0x10701030b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP25_IP3_PKT_W1C"    ,	   0x10701032b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP26_IP3_PKT_W1C"    ,	   0x10701034b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP27_IP3_PKT_W1C"    ,	   0x10701036b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP28_IP3_PKT_W1C"    ,	   0x10701038b6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP29_IP3_PKT_W1C"    ,	   0x1070103ab6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP30_IP3_PKT_W1C"    ,	   0x1070103cb6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP31_IP3_PKT_W1C"    ,	   0x1070103eb6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"CIU2_EN_PP0_IP3_PKT_W1S"     ,	   0x10701000a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP1_IP3_PKT_W1S"     ,	   0x10701002a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP2_IP3_PKT_W1S"     ,	   0x10701004a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP3_IP3_PKT_W1S"     ,	   0x10701006a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP4_IP3_PKT_W1S"     ,	   0x10701008a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP5_IP3_PKT_W1S"     ,	   0x1070100aa6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP6_IP3_PKT_W1S"     ,	   0x1070100ca6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP7_IP3_PKT_W1S"     ,	   0x1070100ea6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP8_IP3_PKT_W1S"     ,	   0x10701010a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP9_IP3_PKT_W1S"     ,	   0x10701012a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP10_IP3_PKT_W1S"    ,	   0x10701014a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP11_IP3_PKT_W1S"    ,	   0x10701016a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP12_IP3_PKT_W1S"    ,	   0x10701018a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP13_IP3_PKT_W1S"    ,	   0x1070101aa6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP14_IP3_PKT_W1S"    ,	   0x1070101ca6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP15_IP3_PKT_W1S"    ,	   0x1070101ea6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP16_IP3_PKT_W1S"    ,	   0x10701020a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP17_IP3_PKT_W1S"    ,	   0x10701022a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP18_IP3_PKT_W1S"    ,	   0x10701024a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP19_IP3_PKT_W1S"    ,	   0x10701026a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP20_IP3_PKT_W1S"    ,	   0x10701028a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP21_IP3_PKT_W1S"    ,	   0x1070102aa6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP22_IP3_PKT_W1S"    ,	   0x1070102ca6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP23_IP3_PKT_W1S"    ,	   0x1070102ea6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP24_IP3_PKT_W1S"    ,	   0x10701030a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP25_IP3_PKT_W1S"    ,	   0x10701032a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP26_IP3_PKT_W1S"    ,	   0x10701034a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP27_IP3_PKT_W1S"    ,	   0x10701036a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP28_IP3_PKT_W1S"    ,	   0x10701038a6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP29_IP3_PKT_W1S"    ,	   0x1070103aa6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP30_IP3_PKT_W1S"    ,	   0x1070103ca6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP31_IP3_PKT_W1S"    ,	   0x1070103ea6200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"CIU2_EN_PP0_IP3_RML"         ,	   0x1070100092200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP1_IP3_RML"         ,	   0x1070100292200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP2_IP3_RML"         ,	   0x1070100492200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP3_IP3_RML"         ,	   0x1070100692200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP4_IP3_RML"         ,	   0x1070100892200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP5_IP3_RML"         ,	   0x1070100a92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP6_IP3_RML"         ,	   0x1070100c92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP7_IP3_RML"         ,	   0x1070100e92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP8_IP3_RML"         ,	   0x1070101092200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP9_IP3_RML"         ,	   0x1070101292200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP10_IP3_RML"        ,	   0x1070101492200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP11_IP3_RML"        ,	   0x1070101692200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP12_IP3_RML"        ,	   0x1070101892200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP13_IP3_RML"        ,	   0x1070101a92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP14_IP3_RML"        ,	   0x1070101c92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP15_IP3_RML"        ,	   0x1070101e92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP16_IP3_RML"        ,	   0x1070102092200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP17_IP3_RML"        ,	   0x1070102292200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP18_IP3_RML"        ,	   0x1070102492200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP19_IP3_RML"        ,	   0x1070102692200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP20_IP3_RML"        ,	   0x1070102892200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP21_IP3_RML"        ,	   0x1070102a92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP22_IP3_RML"        ,	   0x1070102c92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP23_IP3_RML"        ,	   0x1070102e92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP24_IP3_RML"        ,	   0x1070103092200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP25_IP3_RML"        ,	   0x1070103292200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP26_IP3_RML"        ,	   0x1070103492200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP27_IP3_RML"        ,	   0x1070103692200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP28_IP3_RML"        ,	   0x1070103892200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP29_IP3_RML"        ,	   0x1070103a92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP30_IP3_RML"        ,	   0x1070103c92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP31_IP3_RML"        ,	   0x1070103e92200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"CIU2_EN_PP0_IP3_RML_W1C"     ,	   0x10701000b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP1_IP3_RML_W1C"     ,	   0x10701002b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP2_IP3_RML_W1C"     ,	   0x10701004b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP3_IP3_RML_W1C"     ,	   0x10701006b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP4_IP3_RML_W1C"     ,	   0x10701008b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP5_IP3_RML_W1C"     ,	   0x1070100ab2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP6_IP3_RML_W1C"     ,	   0x1070100cb2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP7_IP3_RML_W1C"     ,	   0x1070100eb2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP8_IP3_RML_W1C"     ,	   0x10701010b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP9_IP3_RML_W1C"     ,	   0x10701012b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP10_IP3_RML_W1C"    ,	   0x10701014b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP11_IP3_RML_W1C"    ,	   0x10701016b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP12_IP3_RML_W1C"    ,	   0x10701018b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP13_IP3_RML_W1C"    ,	   0x1070101ab2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP14_IP3_RML_W1C"    ,	   0x1070101cb2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP15_IP3_RML_W1C"    ,	   0x1070101eb2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP16_IP3_RML_W1C"    ,	   0x10701020b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP17_IP3_RML_W1C"    ,	   0x10701022b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP18_IP3_RML_W1C"    ,	   0x10701024b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP19_IP3_RML_W1C"    ,	   0x10701026b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP20_IP3_RML_W1C"    ,	   0x10701028b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP21_IP3_RML_W1C"    ,	   0x1070102ab2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP22_IP3_RML_W1C"    ,	   0x1070102cb2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP23_IP3_RML_W1C"    ,	   0x1070102eb2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP24_IP3_RML_W1C"    ,	   0x10701030b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP25_IP3_RML_W1C"    ,	   0x10701032b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP26_IP3_RML_W1C"    ,	   0x10701034b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP27_IP3_RML_W1C"    ,	   0x10701036b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP28_IP3_RML_W1C"    ,	   0x10701038b2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP29_IP3_RML_W1C"    ,	   0x1070103ab2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP30_IP3_RML_W1C"    ,	   0x1070103cb2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP31_IP3_RML_W1C"    ,	   0x1070103eb2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"CIU2_EN_PP0_IP3_RML_W1S"     ,	   0x10701000a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP1_IP3_RML_W1S"     ,	   0x10701002a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP2_IP3_RML_W1S"     ,	   0x10701004a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP3_IP3_RML_W1S"     ,	   0x10701006a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP4_IP3_RML_W1S"     ,	   0x10701008a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP5_IP3_RML_W1S"     ,	   0x1070100aa2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP6_IP3_RML_W1S"     ,	   0x1070100ca2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP7_IP3_RML_W1S"     ,	   0x1070100ea2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP8_IP3_RML_W1S"     ,	   0x10701010a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP9_IP3_RML_W1S"     ,	   0x10701012a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP10_IP3_RML_W1S"    ,	   0x10701014a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP11_IP3_RML_W1S"    ,	   0x10701016a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP12_IP3_RML_W1S"    ,	   0x10701018a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP13_IP3_RML_W1S"    ,	   0x1070101aa2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP14_IP3_RML_W1S"    ,	   0x1070101ca2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP15_IP3_RML_W1S"    ,	   0x1070101ea2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP16_IP3_RML_W1S"    ,	   0x10701020a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP17_IP3_RML_W1S"    ,	   0x10701022a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP18_IP3_RML_W1S"    ,	   0x10701024a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP19_IP3_RML_W1S"    ,	   0x10701026a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP20_IP3_RML_W1S"    ,	   0x10701028a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP21_IP3_RML_W1S"    ,	   0x1070102aa2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP22_IP3_RML_W1S"    ,	   0x1070102ca2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP23_IP3_RML_W1S"    ,	   0x1070102ea2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP24_IP3_RML_W1S"    ,	   0x10701030a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP25_IP3_RML_W1S"    ,	   0x10701032a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP26_IP3_RML_W1S"    ,	   0x10701034a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP27_IP3_RML_W1S"    ,	   0x10701036a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP28_IP3_RML_W1S"    ,	   0x10701038a2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP29_IP3_RML_W1S"    ,	   0x1070103aa2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP30_IP3_RML_W1S"    ,	   0x1070103ca2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP31_IP3_RML_W1S"    ,	   0x1070103ea2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"CIU2_EN_PP0_IP3_WDOG"        ,	   0x1070100091200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP1_IP3_WDOG"        ,	   0x1070100291200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP2_IP3_WDOG"        ,	   0x1070100491200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP3_IP3_WDOG"        ,	   0x1070100691200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP4_IP3_WDOG"        ,	   0x1070100891200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP5_IP3_WDOG"        ,	   0x1070100a91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP6_IP3_WDOG"        ,	   0x1070100c91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP7_IP3_WDOG"        ,	   0x1070100e91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP8_IP3_WDOG"        ,	   0x1070101091200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP9_IP3_WDOG"        ,	   0x1070101291200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP10_IP3_WDOG"       ,	   0x1070101491200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP11_IP3_WDOG"       ,	   0x1070101691200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP12_IP3_WDOG"       ,	   0x1070101891200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP13_IP3_WDOG"       ,	   0x1070101a91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP14_IP3_WDOG"       ,	   0x1070101c91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP15_IP3_WDOG"       ,	   0x1070101e91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP16_IP3_WDOG"       ,	   0x1070102091200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP17_IP3_WDOG"       ,	   0x1070102291200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP18_IP3_WDOG"       ,	   0x1070102491200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP19_IP3_WDOG"       ,	   0x1070102691200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP20_IP3_WDOG"       ,	   0x1070102891200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP21_IP3_WDOG"       ,	   0x1070102a91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP22_IP3_WDOG"       ,	   0x1070102c91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP23_IP3_WDOG"       ,	   0x1070102e91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP24_IP3_WDOG"       ,	   0x1070103091200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP25_IP3_WDOG"       ,	   0x1070103291200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP26_IP3_WDOG"       ,	   0x1070103491200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP27_IP3_WDOG"       ,	   0x1070103691200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP28_IP3_WDOG"       ,	   0x1070103891200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP29_IP3_WDOG"       ,	   0x1070103a91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP30_IP3_WDOG"       ,	   0x1070103c91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP31_IP3_WDOG"       ,	   0x1070103e91200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"CIU2_EN_PP0_IP3_WDOG_W1C"    ,	   0x10701000b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP1_IP3_WDOG_W1C"    ,	   0x10701002b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP2_IP3_WDOG_W1C"    ,	   0x10701004b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP3_IP3_WDOG_W1C"    ,	   0x10701006b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP4_IP3_WDOG_W1C"    ,	   0x10701008b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP5_IP3_WDOG_W1C"    ,	   0x1070100ab1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP6_IP3_WDOG_W1C"    ,	   0x1070100cb1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP7_IP3_WDOG_W1C"    ,	   0x1070100eb1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP8_IP3_WDOG_W1C"    ,	   0x10701010b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP9_IP3_WDOG_W1C"    ,	   0x10701012b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP10_IP3_WDOG_W1C"   ,	   0x10701014b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP11_IP3_WDOG_W1C"   ,	   0x10701016b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP12_IP3_WDOG_W1C"   ,	   0x10701018b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP13_IP3_WDOG_W1C"   ,	   0x1070101ab1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP14_IP3_WDOG_W1C"   ,	   0x1070101cb1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP15_IP3_WDOG_W1C"   ,	   0x1070101eb1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP16_IP3_WDOG_W1C"   ,	   0x10701020b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP17_IP3_WDOG_W1C"   ,	   0x10701022b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP18_IP3_WDOG_W1C"   ,	   0x10701024b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP19_IP3_WDOG_W1C"   ,	   0x10701026b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP20_IP3_WDOG_W1C"   ,	   0x10701028b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP21_IP3_WDOG_W1C"   ,	   0x1070102ab1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP22_IP3_WDOG_W1C"   ,	   0x1070102cb1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP23_IP3_WDOG_W1C"   ,	   0x1070102eb1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP24_IP3_WDOG_W1C"   ,	   0x10701030b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP25_IP3_WDOG_W1C"   ,	   0x10701032b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP26_IP3_WDOG_W1C"   ,	   0x10701034b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP27_IP3_WDOG_W1C"   ,	   0x10701036b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP28_IP3_WDOG_W1C"   ,	   0x10701038b1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP29_IP3_WDOG_W1C"   ,	   0x1070103ab1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP30_IP3_WDOG_W1C"   ,	   0x1070103cb1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP31_IP3_WDOG_W1C"   ,	   0x1070103eb1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"CIU2_EN_PP0_IP3_WDOG_W1S"    ,	   0x10701000a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP1_IP3_WDOG_W1S"    ,	   0x10701002a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP2_IP3_WDOG_W1S"    ,	   0x10701004a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP3_IP3_WDOG_W1S"    ,	   0x10701006a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP4_IP3_WDOG_W1S"    ,	   0x10701008a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP5_IP3_WDOG_W1S"    ,	   0x1070100aa1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP6_IP3_WDOG_W1S"    ,	   0x1070100ca1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP7_IP3_WDOG_W1S"    ,	   0x1070100ea1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP8_IP3_WDOG_W1S"    ,	   0x10701010a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP9_IP3_WDOG_W1S"    ,	   0x10701012a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP10_IP3_WDOG_W1S"   ,	   0x10701014a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP11_IP3_WDOG_W1S"   ,	   0x10701016a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP12_IP3_WDOG_W1S"   ,	   0x10701018a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP13_IP3_WDOG_W1S"   ,	   0x1070101aa1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP14_IP3_WDOG_W1S"   ,	   0x1070101ca1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP15_IP3_WDOG_W1S"   ,	   0x1070101ea1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP16_IP3_WDOG_W1S"   ,	   0x10701020a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP17_IP3_WDOG_W1S"   ,	   0x10701022a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP18_IP3_WDOG_W1S"   ,	   0x10701024a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP19_IP3_WDOG_W1S"   ,	   0x10701026a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP20_IP3_WDOG_W1S"   ,	   0x10701028a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP21_IP3_WDOG_W1S"   ,	   0x1070102aa1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP22_IP3_WDOG_W1S"   ,	   0x1070102ca1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP23_IP3_WDOG_W1S"   ,	   0x1070102ea1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP24_IP3_WDOG_W1S"   ,	   0x10701030a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP25_IP3_WDOG_W1S"   ,	   0x10701032a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP26_IP3_WDOG_W1S"   ,	   0x10701034a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP27_IP3_WDOG_W1S"   ,	   0x10701036a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP28_IP3_WDOG_W1S"   ,	   0x10701038a1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP29_IP3_WDOG_W1S"   ,	   0x1070103aa1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP30_IP3_WDOG_W1S"   ,	   0x1070103ca1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP31_IP3_WDOG_W1S"   ,	   0x1070103ea1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"CIU2_EN_PP0_IP3_WRKQ"        ,	   0x1070100090200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP1_IP3_WRKQ"        ,	   0x1070100290200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP2_IP3_WRKQ"        ,	   0x1070100490200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP3_IP3_WRKQ"        ,	   0x1070100690200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP4_IP3_WRKQ"        ,	   0x1070100890200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP5_IP3_WRKQ"        ,	   0x1070100a90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP6_IP3_WRKQ"        ,	   0x1070100c90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP7_IP3_WRKQ"        ,	   0x1070100e90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP8_IP3_WRKQ"        ,	   0x1070101090200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP9_IP3_WRKQ"        ,	   0x1070101290200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP10_IP3_WRKQ"       ,	   0x1070101490200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP11_IP3_WRKQ"       ,	   0x1070101690200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP12_IP3_WRKQ"       ,	   0x1070101890200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP13_IP3_WRKQ"       ,	   0x1070101a90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP14_IP3_WRKQ"       ,	   0x1070101c90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP15_IP3_WRKQ"       ,	   0x1070101e90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP16_IP3_WRKQ"       ,	   0x1070102090200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP17_IP3_WRKQ"       ,	   0x1070102290200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP18_IP3_WRKQ"       ,	   0x1070102490200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP19_IP3_WRKQ"       ,	   0x1070102690200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP20_IP3_WRKQ"       ,	   0x1070102890200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP21_IP3_WRKQ"       ,	   0x1070102a90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP22_IP3_WRKQ"       ,	   0x1070102c90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP23_IP3_WRKQ"       ,	   0x1070102e90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP24_IP3_WRKQ"       ,	   0x1070103090200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP25_IP3_WRKQ"       ,	   0x1070103290200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP26_IP3_WRKQ"       ,	   0x1070103490200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP27_IP3_WRKQ"       ,	   0x1070103690200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP28_IP3_WRKQ"       ,	   0x1070103890200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP29_IP3_WRKQ"       ,	   0x1070103a90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP30_IP3_WRKQ"       ,	   0x1070103c90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP31_IP3_WRKQ"       ,	   0x1070103e90200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"CIU2_EN_PP0_IP3_WRKQ_W1C"    ,	   0x10701000b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP1_IP3_WRKQ_W1C"    ,	   0x10701002b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP2_IP3_WRKQ_W1C"    ,	   0x10701004b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP3_IP3_WRKQ_W1C"    ,	   0x10701006b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP4_IP3_WRKQ_W1C"    ,	   0x10701008b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP5_IP3_WRKQ_W1C"    ,	   0x1070100ab0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP6_IP3_WRKQ_W1C"    ,	   0x1070100cb0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP7_IP3_WRKQ_W1C"    ,	   0x1070100eb0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP8_IP3_WRKQ_W1C"    ,	   0x10701010b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP9_IP3_WRKQ_W1C"    ,	   0x10701012b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP10_IP3_WRKQ_W1C"   ,	   0x10701014b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP11_IP3_WRKQ_W1C"   ,	   0x10701016b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP12_IP3_WRKQ_W1C"   ,	   0x10701018b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP13_IP3_WRKQ_W1C"   ,	   0x1070101ab0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP14_IP3_WRKQ_W1C"   ,	   0x1070101cb0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP15_IP3_WRKQ_W1C"   ,	   0x1070101eb0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP16_IP3_WRKQ_W1C"   ,	   0x10701020b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP17_IP3_WRKQ_W1C"   ,	   0x10701022b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP18_IP3_WRKQ_W1C"   ,	   0x10701024b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP19_IP3_WRKQ_W1C"   ,	   0x10701026b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP20_IP3_WRKQ_W1C"   ,	   0x10701028b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP21_IP3_WRKQ_W1C"   ,	   0x1070102ab0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP22_IP3_WRKQ_W1C"   ,	   0x1070102cb0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP23_IP3_WRKQ_W1C"   ,	   0x1070102eb0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP24_IP3_WRKQ_W1C"   ,	   0x10701030b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP25_IP3_WRKQ_W1C"   ,	   0x10701032b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP26_IP3_WRKQ_W1C"   ,	   0x10701034b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP27_IP3_WRKQ_W1C"   ,	   0x10701036b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP28_IP3_WRKQ_W1C"   ,	   0x10701038b0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP29_IP3_WRKQ_W1C"   ,	   0x1070103ab0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP30_IP3_WRKQ_W1C"   ,	   0x1070103cb0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP31_IP3_WRKQ_W1C"   ,	   0x1070103eb0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"CIU2_EN_PP0_IP3_WRKQ_W1S"    ,	   0x10701000a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP1_IP3_WRKQ_W1S"    ,	   0x10701002a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP2_IP3_WRKQ_W1S"    ,	   0x10701004a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP3_IP3_WRKQ_W1S"    ,	   0x10701006a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP4_IP3_WRKQ_W1S"    ,	   0x10701008a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP5_IP3_WRKQ_W1S"    ,	   0x1070100aa0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP6_IP3_WRKQ_W1S"    ,	   0x1070100ca0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP7_IP3_WRKQ_W1S"    ,	   0x1070100ea0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP8_IP3_WRKQ_W1S"    ,	   0x10701010a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP9_IP3_WRKQ_W1S"    ,	   0x10701012a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP10_IP3_WRKQ_W1S"   ,	   0x10701014a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP11_IP3_WRKQ_W1S"   ,	   0x10701016a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP12_IP3_WRKQ_W1S"   ,	   0x10701018a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP13_IP3_WRKQ_W1S"   ,	   0x1070101aa0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP14_IP3_WRKQ_W1S"   ,	   0x1070101ca0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP15_IP3_WRKQ_W1S"   ,	   0x1070101ea0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP16_IP3_WRKQ_W1S"   ,	   0x10701020a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP17_IP3_WRKQ_W1S"   ,	   0x10701022a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP18_IP3_WRKQ_W1S"   ,	   0x10701024a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP19_IP3_WRKQ_W1S"   ,	   0x10701026a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP20_IP3_WRKQ_W1S"   ,	   0x10701028a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP21_IP3_WRKQ_W1S"   ,	   0x1070102aa0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP22_IP3_WRKQ_W1S"   ,	   0x1070102ca0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP23_IP3_WRKQ_W1S"   ,	   0x1070102ea0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP24_IP3_WRKQ_W1S"   ,	   0x10701030a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP25_IP3_WRKQ_W1S"   ,	   0x10701032a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP26_IP3_WRKQ_W1S"   ,	   0x10701034a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP27_IP3_WRKQ_W1S"   ,	   0x10701036a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP28_IP3_WRKQ_W1S"   ,	   0x10701038a0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP29_IP3_WRKQ_W1S"   ,	   0x1070103aa0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP30_IP3_WRKQ_W1S"   ,	   0x1070103ca0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP31_IP3_WRKQ_W1S"   ,	   0x1070103ea0200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"CIU2_EN_PP0_IP4_GPIO"        ,	   0x1070100097400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP1_IP4_GPIO"        ,	   0x1070100297400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP2_IP4_GPIO"        ,	   0x1070100497400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP3_IP4_GPIO"        ,	   0x1070100697400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP4_IP4_GPIO"        ,	   0x1070100897400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP5_IP4_GPIO"        ,	   0x1070100a97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP6_IP4_GPIO"        ,	   0x1070100c97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP7_IP4_GPIO"        ,	   0x1070100e97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP8_IP4_GPIO"        ,	   0x1070101097400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP9_IP4_GPIO"        ,	   0x1070101297400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP10_IP4_GPIO"       ,	   0x1070101497400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP11_IP4_GPIO"       ,	   0x1070101697400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP12_IP4_GPIO"       ,	   0x1070101897400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP13_IP4_GPIO"       ,	   0x1070101a97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP14_IP4_GPIO"       ,	   0x1070101c97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP15_IP4_GPIO"       ,	   0x1070101e97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP16_IP4_GPIO"       ,	   0x1070102097400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP17_IP4_GPIO"       ,	   0x1070102297400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP18_IP4_GPIO"       ,	   0x1070102497400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP19_IP4_GPIO"       ,	   0x1070102697400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP20_IP4_GPIO"       ,	   0x1070102897400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP21_IP4_GPIO"       ,	   0x1070102a97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP22_IP4_GPIO"       ,	   0x1070102c97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP23_IP4_GPIO"       ,	   0x1070102e97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP24_IP4_GPIO"       ,	   0x1070103097400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP25_IP4_GPIO"       ,	   0x1070103297400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP26_IP4_GPIO"       ,	   0x1070103497400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP27_IP4_GPIO"       ,	   0x1070103697400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP28_IP4_GPIO"       ,	   0x1070103897400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP29_IP4_GPIO"       ,	   0x1070103a97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP30_IP4_GPIO"       ,	   0x1070103c97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP31_IP4_GPIO"       ,	   0x1070103e97400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"CIU2_EN_PP0_IP4_GPIO_W1C"    ,	   0x10701000b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP1_IP4_GPIO_W1C"    ,	   0x10701002b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP2_IP4_GPIO_W1C"    ,	   0x10701004b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP3_IP4_GPIO_W1C"    ,	   0x10701006b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP4_IP4_GPIO_W1C"    ,	   0x10701008b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP5_IP4_GPIO_W1C"    ,	   0x1070100ab7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP6_IP4_GPIO_W1C"    ,	   0x1070100cb7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP7_IP4_GPIO_W1C"    ,	   0x1070100eb7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP8_IP4_GPIO_W1C"    ,	   0x10701010b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP9_IP4_GPIO_W1C"    ,	   0x10701012b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP10_IP4_GPIO_W1C"   ,	   0x10701014b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP11_IP4_GPIO_W1C"   ,	   0x10701016b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP12_IP4_GPIO_W1C"   ,	   0x10701018b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP13_IP4_GPIO_W1C"   ,	   0x1070101ab7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP14_IP4_GPIO_W1C"   ,	   0x1070101cb7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP15_IP4_GPIO_W1C"   ,	   0x1070101eb7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP16_IP4_GPIO_W1C"   ,	   0x10701020b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP17_IP4_GPIO_W1C"   ,	   0x10701022b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP18_IP4_GPIO_W1C"   ,	   0x10701024b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP19_IP4_GPIO_W1C"   ,	   0x10701026b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP20_IP4_GPIO_W1C"   ,	   0x10701028b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP21_IP4_GPIO_W1C"   ,	   0x1070102ab7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP22_IP4_GPIO_W1C"   ,	   0x1070102cb7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP23_IP4_GPIO_W1C"   ,	   0x1070102eb7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP24_IP4_GPIO_W1C"   ,	   0x10701030b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP25_IP4_GPIO_W1C"   ,	   0x10701032b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP26_IP4_GPIO_W1C"   ,	   0x10701034b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP27_IP4_GPIO_W1C"   ,	   0x10701036b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP28_IP4_GPIO_W1C"   ,	   0x10701038b7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP29_IP4_GPIO_W1C"   ,	   0x1070103ab7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP30_IP4_GPIO_W1C"   ,	   0x1070103cb7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP31_IP4_GPIO_W1C"   ,	   0x1070103eb7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"CIU2_EN_PP0_IP4_GPIO_W1S"    ,	   0x10701000a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP1_IP4_GPIO_W1S"    ,	   0x10701002a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP2_IP4_GPIO_W1S"    ,	   0x10701004a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP3_IP4_GPIO_W1S"    ,	   0x10701006a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP4_IP4_GPIO_W1S"    ,	   0x10701008a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP5_IP4_GPIO_W1S"    ,	   0x1070100aa7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP6_IP4_GPIO_W1S"    ,	   0x1070100ca7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP7_IP4_GPIO_W1S"    ,	   0x1070100ea7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP8_IP4_GPIO_W1S"    ,	   0x10701010a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP9_IP4_GPIO_W1S"    ,	   0x10701012a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP10_IP4_GPIO_W1S"   ,	   0x10701014a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP11_IP4_GPIO_W1S"   ,	   0x10701016a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP12_IP4_GPIO_W1S"   ,	   0x10701018a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP13_IP4_GPIO_W1S"   ,	   0x1070101aa7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP14_IP4_GPIO_W1S"   ,	   0x1070101ca7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP15_IP4_GPIO_W1S"   ,	   0x1070101ea7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP16_IP4_GPIO_W1S"   ,	   0x10701020a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP17_IP4_GPIO_W1S"   ,	   0x10701022a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP18_IP4_GPIO_W1S"   ,	   0x10701024a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP19_IP4_GPIO_W1S"   ,	   0x10701026a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP20_IP4_GPIO_W1S"   ,	   0x10701028a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP21_IP4_GPIO_W1S"   ,	   0x1070102aa7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP22_IP4_GPIO_W1S"   ,	   0x1070102ca7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP23_IP4_GPIO_W1S"   ,	   0x1070102ea7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP24_IP4_GPIO_W1S"   ,	   0x10701030a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP25_IP4_GPIO_W1S"   ,	   0x10701032a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP26_IP4_GPIO_W1S"   ,	   0x10701034a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP27_IP4_GPIO_W1S"   ,	   0x10701036a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP28_IP4_GPIO_W1S"   ,	   0x10701038a7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP29_IP4_GPIO_W1S"   ,	   0x1070103aa7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP30_IP4_GPIO_W1S"   ,	   0x1070103ca7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP31_IP4_GPIO_W1S"   ,	   0x1070103ea7400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"CIU2_EN_PP0_IP4_IO"          ,	   0x1070100094400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP1_IP4_IO"          ,	   0x1070100294400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP2_IP4_IO"          ,	   0x1070100494400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP3_IP4_IO"          ,	   0x1070100694400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP4_IP4_IO"          ,	   0x1070100894400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP5_IP4_IO"          ,	   0x1070100a94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP6_IP4_IO"          ,	   0x1070100c94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP7_IP4_IO"          ,	   0x1070100e94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP8_IP4_IO"          ,	   0x1070101094400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP9_IP4_IO"          ,	   0x1070101294400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP10_IP4_IO"         ,	   0x1070101494400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP11_IP4_IO"         ,	   0x1070101694400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP12_IP4_IO"         ,	   0x1070101894400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP13_IP4_IO"         ,	   0x1070101a94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP14_IP4_IO"         ,	   0x1070101c94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP15_IP4_IO"         ,	   0x1070101e94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP16_IP4_IO"         ,	   0x1070102094400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP17_IP4_IO"         ,	   0x1070102294400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP18_IP4_IO"         ,	   0x1070102494400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP19_IP4_IO"         ,	   0x1070102694400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP20_IP4_IO"         ,	   0x1070102894400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP21_IP4_IO"         ,	   0x1070102a94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP22_IP4_IO"         ,	   0x1070102c94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP23_IP4_IO"         ,	   0x1070102e94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP24_IP4_IO"         ,	   0x1070103094400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP25_IP4_IO"         ,	   0x1070103294400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP26_IP4_IO"         ,	   0x1070103494400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP27_IP4_IO"         ,	   0x1070103694400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP28_IP4_IO"         ,	   0x1070103894400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP29_IP4_IO"         ,	   0x1070103a94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP30_IP4_IO"         ,	   0x1070103c94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP31_IP4_IO"         ,	   0x1070103e94400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"CIU2_EN_PP0_IP4_IO_W1C"      ,	   0x10701000b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP1_IP4_IO_W1C"      ,	   0x10701002b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP2_IP4_IO_W1C"      ,	   0x10701004b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP3_IP4_IO_W1C"      ,	   0x10701006b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP4_IP4_IO_W1C"      ,	   0x10701008b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP5_IP4_IO_W1C"      ,	   0x1070100ab4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP6_IP4_IO_W1C"      ,	   0x1070100cb4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP7_IP4_IO_W1C"      ,	   0x1070100eb4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP8_IP4_IO_W1C"      ,	   0x10701010b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP9_IP4_IO_W1C"      ,	   0x10701012b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP10_IP4_IO_W1C"     ,	   0x10701014b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP11_IP4_IO_W1C"     ,	   0x10701016b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP12_IP4_IO_W1C"     ,	   0x10701018b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP13_IP4_IO_W1C"     ,	   0x1070101ab4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP14_IP4_IO_W1C"     ,	   0x1070101cb4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP15_IP4_IO_W1C"     ,	   0x1070101eb4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP16_IP4_IO_W1C"     ,	   0x10701020b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP17_IP4_IO_W1C"     ,	   0x10701022b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP18_IP4_IO_W1C"     ,	   0x10701024b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP19_IP4_IO_W1C"     ,	   0x10701026b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP20_IP4_IO_W1C"     ,	   0x10701028b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP21_IP4_IO_W1C"     ,	   0x1070102ab4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP22_IP4_IO_W1C"     ,	   0x1070102cb4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP23_IP4_IO_W1C"     ,	   0x1070102eb4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP24_IP4_IO_W1C"     ,	   0x10701030b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP25_IP4_IO_W1C"     ,	   0x10701032b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP26_IP4_IO_W1C"     ,	   0x10701034b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP27_IP4_IO_W1C"     ,	   0x10701036b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP28_IP4_IO_W1C"     ,	   0x10701038b4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP29_IP4_IO_W1C"     ,	   0x1070103ab4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP30_IP4_IO_W1C"     ,	   0x1070103cb4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP31_IP4_IO_W1C"     ,	   0x1070103eb4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"CIU2_EN_PP0_IP4_IO_W1S"      ,	   0x10701000a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP1_IP4_IO_W1S"      ,	   0x10701002a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP2_IP4_IO_W1S"      ,	   0x10701004a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP3_IP4_IO_W1S"      ,	   0x10701006a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP4_IP4_IO_W1S"      ,	   0x10701008a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP5_IP4_IO_W1S"      ,	   0x1070100aa4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP6_IP4_IO_W1S"      ,	   0x1070100ca4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP7_IP4_IO_W1S"      ,	   0x1070100ea4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP8_IP4_IO_W1S"      ,	   0x10701010a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP9_IP4_IO_W1S"      ,	   0x10701012a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP10_IP4_IO_W1S"     ,	   0x10701014a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP11_IP4_IO_W1S"     ,	   0x10701016a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP12_IP4_IO_W1S"     ,	   0x10701018a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP13_IP4_IO_W1S"     ,	   0x1070101aa4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP14_IP4_IO_W1S"     ,	   0x1070101ca4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP15_IP4_IO_W1S"     ,	   0x1070101ea4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP16_IP4_IO_W1S"     ,	   0x10701020a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP17_IP4_IO_W1S"     ,	   0x10701022a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP18_IP4_IO_W1S"     ,	   0x10701024a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP19_IP4_IO_W1S"     ,	   0x10701026a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP20_IP4_IO_W1S"     ,	   0x10701028a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP21_IP4_IO_W1S"     ,	   0x1070102aa4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP22_IP4_IO_W1S"     ,	   0x1070102ca4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP23_IP4_IO_W1S"     ,	   0x1070102ea4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP24_IP4_IO_W1S"     ,	   0x10701030a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP25_IP4_IO_W1S"     ,	   0x10701032a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP26_IP4_IO_W1S"     ,	   0x10701034a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP27_IP4_IO_W1S"     ,	   0x10701036a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP28_IP4_IO_W1S"     ,	   0x10701038a4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP29_IP4_IO_W1S"     ,	   0x1070103aa4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP30_IP4_IO_W1S"     ,	   0x1070103ca4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP31_IP4_IO_W1S"     ,	   0x1070103ea4400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"CIU2_EN_PP0_IP4_MBOX"        ,	   0x1070100098400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP1_IP4_MBOX"        ,	   0x1070100298400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP2_IP4_MBOX"        ,	   0x1070100498400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP3_IP4_MBOX"        ,	   0x1070100698400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP4_IP4_MBOX"        ,	   0x1070100898400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP5_IP4_MBOX"        ,	   0x1070100a98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP6_IP4_MBOX"        ,	   0x1070100c98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP7_IP4_MBOX"        ,	   0x1070100e98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP8_IP4_MBOX"        ,	   0x1070101098400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP9_IP4_MBOX"        ,	   0x1070101298400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP10_IP4_MBOX"       ,	   0x1070101498400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP11_IP4_MBOX"       ,	   0x1070101698400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP12_IP4_MBOX"       ,	   0x1070101898400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP13_IP4_MBOX"       ,	   0x1070101a98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP14_IP4_MBOX"       ,	   0x1070101c98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP15_IP4_MBOX"       ,	   0x1070101e98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP16_IP4_MBOX"       ,	   0x1070102098400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP17_IP4_MBOX"       ,	   0x1070102298400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP18_IP4_MBOX"       ,	   0x1070102498400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP19_IP4_MBOX"       ,	   0x1070102698400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP20_IP4_MBOX"       ,	   0x1070102898400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP21_IP4_MBOX"       ,	   0x1070102a98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP22_IP4_MBOX"       ,	   0x1070102c98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP23_IP4_MBOX"       ,	   0x1070102e98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP24_IP4_MBOX"       ,	   0x1070103098400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP25_IP4_MBOX"       ,	   0x1070103298400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP26_IP4_MBOX"       ,	   0x1070103498400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP27_IP4_MBOX"       ,	   0x1070103698400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP28_IP4_MBOX"       ,	   0x1070103898400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP29_IP4_MBOX"       ,	   0x1070103a98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP30_IP4_MBOX"       ,	   0x1070103c98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP31_IP4_MBOX"       ,	   0x1070103e98400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"CIU2_EN_PP0_IP4_MBOX_W1C"    ,	   0x10701000b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP1_IP4_MBOX_W1C"    ,	   0x10701002b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP2_IP4_MBOX_W1C"    ,	   0x10701004b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP3_IP4_MBOX_W1C"    ,	   0x10701006b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP4_IP4_MBOX_W1C"    ,	   0x10701008b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP5_IP4_MBOX_W1C"    ,	   0x1070100ab8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP6_IP4_MBOX_W1C"    ,	   0x1070100cb8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP7_IP4_MBOX_W1C"    ,	   0x1070100eb8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP8_IP4_MBOX_W1C"    ,	   0x10701010b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP9_IP4_MBOX_W1C"    ,	   0x10701012b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP10_IP4_MBOX_W1C"   ,	   0x10701014b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP11_IP4_MBOX_W1C"   ,	   0x10701016b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP12_IP4_MBOX_W1C"   ,	   0x10701018b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP13_IP4_MBOX_W1C"   ,	   0x1070101ab8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP14_IP4_MBOX_W1C"   ,	   0x1070101cb8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP15_IP4_MBOX_W1C"   ,	   0x1070101eb8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP16_IP4_MBOX_W1C"   ,	   0x10701020b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP17_IP4_MBOX_W1C"   ,	   0x10701022b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP18_IP4_MBOX_W1C"   ,	   0x10701024b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP19_IP4_MBOX_W1C"   ,	   0x10701026b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP20_IP4_MBOX_W1C"   ,	   0x10701028b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP21_IP4_MBOX_W1C"   ,	   0x1070102ab8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP22_IP4_MBOX_W1C"   ,	   0x1070102cb8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP23_IP4_MBOX_W1C"   ,	   0x1070102eb8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP24_IP4_MBOX_W1C"   ,	   0x10701030b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP25_IP4_MBOX_W1C"   ,	   0x10701032b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP26_IP4_MBOX_W1C"   ,	   0x10701034b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP27_IP4_MBOX_W1C"   ,	   0x10701036b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP28_IP4_MBOX_W1C"   ,	   0x10701038b8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP29_IP4_MBOX_W1C"   ,	   0x1070103ab8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP30_IP4_MBOX_W1C"   ,	   0x1070103cb8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP31_IP4_MBOX_W1C"   ,	   0x1070103eb8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"CIU2_EN_PP0_IP4_MBOX_W1S"    ,	   0x10701000a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP1_IP4_MBOX_W1S"    ,	   0x10701002a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP2_IP4_MBOX_W1S"    ,	   0x10701004a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP3_IP4_MBOX_W1S"    ,	   0x10701006a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP4_IP4_MBOX_W1S"    ,	   0x10701008a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP5_IP4_MBOX_W1S"    ,	   0x1070100aa8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP6_IP4_MBOX_W1S"    ,	   0x1070100ca8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP7_IP4_MBOX_W1S"    ,	   0x1070100ea8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP8_IP4_MBOX_W1S"    ,	   0x10701010a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP9_IP4_MBOX_W1S"    ,	   0x10701012a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP10_IP4_MBOX_W1S"   ,	   0x10701014a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP11_IP4_MBOX_W1S"   ,	   0x10701016a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP12_IP4_MBOX_W1S"   ,	   0x10701018a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP13_IP4_MBOX_W1S"   ,	   0x1070101aa8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP14_IP4_MBOX_W1S"   ,	   0x1070101ca8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP15_IP4_MBOX_W1S"   ,	   0x1070101ea8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP16_IP4_MBOX_W1S"   ,	   0x10701020a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP17_IP4_MBOX_W1S"   ,	   0x10701022a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP18_IP4_MBOX_W1S"   ,	   0x10701024a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP19_IP4_MBOX_W1S"   ,	   0x10701026a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP20_IP4_MBOX_W1S"   ,	   0x10701028a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP21_IP4_MBOX_W1S"   ,	   0x1070102aa8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP22_IP4_MBOX_W1S"   ,	   0x1070102ca8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP23_IP4_MBOX_W1S"   ,	   0x1070102ea8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP24_IP4_MBOX_W1S"   ,	   0x10701030a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP25_IP4_MBOX_W1S"   ,	   0x10701032a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP26_IP4_MBOX_W1S"   ,	   0x10701034a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP27_IP4_MBOX_W1S"   ,	   0x10701036a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP28_IP4_MBOX_W1S"   ,	   0x10701038a8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP29_IP4_MBOX_W1S"   ,	   0x1070103aa8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP30_IP4_MBOX_W1S"   ,	   0x1070103ca8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP31_IP4_MBOX_W1S"   ,	   0x1070103ea8400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"CIU2_EN_PP0_IP4_MEM"         ,	   0x1070100095400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP1_IP4_MEM"         ,	   0x1070100295400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP2_IP4_MEM"         ,	   0x1070100495400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP3_IP4_MEM"         ,	   0x1070100695400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP4_IP4_MEM"         ,	   0x1070100895400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP5_IP4_MEM"         ,	   0x1070100a95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP6_IP4_MEM"         ,	   0x1070100c95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP7_IP4_MEM"         ,	   0x1070100e95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP8_IP4_MEM"         ,	   0x1070101095400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP9_IP4_MEM"         ,	   0x1070101295400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP10_IP4_MEM"        ,	   0x1070101495400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP11_IP4_MEM"        ,	   0x1070101695400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP12_IP4_MEM"        ,	   0x1070101895400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP13_IP4_MEM"        ,	   0x1070101a95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP14_IP4_MEM"        ,	   0x1070101c95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP15_IP4_MEM"        ,	   0x1070101e95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP16_IP4_MEM"        ,	   0x1070102095400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP17_IP4_MEM"        ,	   0x1070102295400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP18_IP4_MEM"        ,	   0x1070102495400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP19_IP4_MEM"        ,	   0x1070102695400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP20_IP4_MEM"        ,	   0x1070102895400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP21_IP4_MEM"        ,	   0x1070102a95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP22_IP4_MEM"        ,	   0x1070102c95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP23_IP4_MEM"        ,	   0x1070102e95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP24_IP4_MEM"        ,	   0x1070103095400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP25_IP4_MEM"        ,	   0x1070103295400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP26_IP4_MEM"        ,	   0x1070103495400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP27_IP4_MEM"        ,	   0x1070103695400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP28_IP4_MEM"        ,	   0x1070103895400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP29_IP4_MEM"        ,	   0x1070103a95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP30_IP4_MEM"        ,	   0x1070103c95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP31_IP4_MEM"        ,	   0x1070103e95400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"CIU2_EN_PP0_IP4_MEM_W1C"     ,	   0x10701000b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP1_IP4_MEM_W1C"     ,	   0x10701002b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP2_IP4_MEM_W1C"     ,	   0x10701004b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP3_IP4_MEM_W1C"     ,	   0x10701006b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP4_IP4_MEM_W1C"     ,	   0x10701008b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP5_IP4_MEM_W1C"     ,	   0x1070100ab5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP6_IP4_MEM_W1C"     ,	   0x1070100cb5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP7_IP4_MEM_W1C"     ,	   0x1070100eb5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP8_IP4_MEM_W1C"     ,	   0x10701010b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP9_IP4_MEM_W1C"     ,	   0x10701012b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP10_IP4_MEM_W1C"    ,	   0x10701014b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP11_IP4_MEM_W1C"    ,	   0x10701016b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP12_IP4_MEM_W1C"    ,	   0x10701018b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP13_IP4_MEM_W1C"    ,	   0x1070101ab5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP14_IP4_MEM_W1C"    ,	   0x1070101cb5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP15_IP4_MEM_W1C"    ,	   0x1070101eb5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP16_IP4_MEM_W1C"    ,	   0x10701020b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP17_IP4_MEM_W1C"    ,	   0x10701022b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP18_IP4_MEM_W1C"    ,	   0x10701024b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP19_IP4_MEM_W1C"    ,	   0x10701026b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP20_IP4_MEM_W1C"    ,	   0x10701028b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP21_IP4_MEM_W1C"    ,	   0x1070102ab5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP22_IP4_MEM_W1C"    ,	   0x1070102cb5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP23_IP4_MEM_W1C"    ,	   0x1070102eb5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP24_IP4_MEM_W1C"    ,	   0x10701030b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP25_IP4_MEM_W1C"    ,	   0x10701032b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP26_IP4_MEM_W1C"    ,	   0x10701034b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP27_IP4_MEM_W1C"    ,	   0x10701036b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP28_IP4_MEM_W1C"    ,	   0x10701038b5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP29_IP4_MEM_W1C"    ,	   0x1070103ab5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP30_IP4_MEM_W1C"    ,	   0x1070103cb5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP31_IP4_MEM_W1C"    ,	   0x1070103eb5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"CIU2_EN_PP0_IP4_MEM_W1S"     ,	   0x10701000a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP1_IP4_MEM_W1S"     ,	   0x10701002a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP2_IP4_MEM_W1S"     ,	   0x10701004a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP3_IP4_MEM_W1S"     ,	   0x10701006a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP4_IP4_MEM_W1S"     ,	   0x10701008a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP5_IP4_MEM_W1S"     ,	   0x1070100aa5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP6_IP4_MEM_W1S"     ,	   0x1070100ca5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP7_IP4_MEM_W1S"     ,	   0x1070100ea5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP8_IP4_MEM_W1S"     ,	   0x10701010a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP9_IP4_MEM_W1S"     ,	   0x10701012a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP10_IP4_MEM_W1S"    ,	   0x10701014a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP11_IP4_MEM_W1S"    ,	   0x10701016a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP12_IP4_MEM_W1S"    ,	   0x10701018a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP13_IP4_MEM_W1S"    ,	   0x1070101aa5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP14_IP4_MEM_W1S"    ,	   0x1070101ca5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP15_IP4_MEM_W1S"    ,	   0x1070101ea5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP16_IP4_MEM_W1S"    ,	   0x10701020a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP17_IP4_MEM_W1S"    ,	   0x10701022a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP18_IP4_MEM_W1S"    ,	   0x10701024a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP19_IP4_MEM_W1S"    ,	   0x10701026a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP20_IP4_MEM_W1S"    ,	   0x10701028a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP21_IP4_MEM_W1S"    ,	   0x1070102aa5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP22_IP4_MEM_W1S"    ,	   0x1070102ca5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP23_IP4_MEM_W1S"    ,	   0x1070102ea5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP24_IP4_MEM_W1S"    ,	   0x10701030a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP25_IP4_MEM_W1S"    ,	   0x10701032a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP26_IP4_MEM_W1S"    ,	   0x10701034a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP27_IP4_MEM_W1S"    ,	   0x10701036a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP28_IP4_MEM_W1S"    ,	   0x10701038a5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP29_IP4_MEM_W1S"    ,	   0x1070103aa5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP30_IP4_MEM_W1S"    ,	   0x1070103ca5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP31_IP4_MEM_W1S"    ,	   0x1070103ea5400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"CIU2_EN_PP0_IP4_MIO"         ,	   0x1070100093400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP1_IP4_MIO"         ,	   0x1070100293400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP2_IP4_MIO"         ,	   0x1070100493400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP3_IP4_MIO"         ,	   0x1070100693400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP4_IP4_MIO"         ,	   0x1070100893400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP5_IP4_MIO"         ,	   0x1070100a93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP6_IP4_MIO"         ,	   0x1070100c93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP7_IP4_MIO"         ,	   0x1070100e93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP8_IP4_MIO"         ,	   0x1070101093400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP9_IP4_MIO"         ,	   0x1070101293400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP10_IP4_MIO"        ,	   0x1070101493400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP11_IP4_MIO"        ,	   0x1070101693400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP12_IP4_MIO"        ,	   0x1070101893400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP13_IP4_MIO"        ,	   0x1070101a93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP14_IP4_MIO"        ,	   0x1070101c93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP15_IP4_MIO"        ,	   0x1070101e93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP16_IP4_MIO"        ,	   0x1070102093400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP17_IP4_MIO"        ,	   0x1070102293400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP18_IP4_MIO"        ,	   0x1070102493400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP19_IP4_MIO"        ,	   0x1070102693400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP20_IP4_MIO"        ,	   0x1070102893400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP21_IP4_MIO"        ,	   0x1070102a93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP22_IP4_MIO"        ,	   0x1070102c93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP23_IP4_MIO"        ,	   0x1070102e93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP24_IP4_MIO"        ,	   0x1070103093400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP25_IP4_MIO"        ,	   0x1070103293400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP26_IP4_MIO"        ,	   0x1070103493400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP27_IP4_MIO"        ,	   0x1070103693400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP28_IP4_MIO"        ,	   0x1070103893400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP29_IP4_MIO"        ,	   0x1070103a93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP30_IP4_MIO"        ,	   0x1070103c93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP31_IP4_MIO"        ,	   0x1070103e93400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"CIU2_EN_PP0_IP4_MIO_W1C"     ,	   0x10701000b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP1_IP4_MIO_W1C"     ,	   0x10701002b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP2_IP4_MIO_W1C"     ,	   0x10701004b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP3_IP4_MIO_W1C"     ,	   0x10701006b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP4_IP4_MIO_W1C"     ,	   0x10701008b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP5_IP4_MIO_W1C"     ,	   0x1070100ab3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP6_IP4_MIO_W1C"     ,	   0x1070100cb3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP7_IP4_MIO_W1C"     ,	   0x1070100eb3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP8_IP4_MIO_W1C"     ,	   0x10701010b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP9_IP4_MIO_W1C"     ,	   0x10701012b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP10_IP4_MIO_W1C"    ,	   0x10701014b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP11_IP4_MIO_W1C"    ,	   0x10701016b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP12_IP4_MIO_W1C"    ,	   0x10701018b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP13_IP4_MIO_W1C"    ,	   0x1070101ab3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP14_IP4_MIO_W1C"    ,	   0x1070101cb3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP15_IP4_MIO_W1C"    ,	   0x1070101eb3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP16_IP4_MIO_W1C"    ,	   0x10701020b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP17_IP4_MIO_W1C"    ,	   0x10701022b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP18_IP4_MIO_W1C"    ,	   0x10701024b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP19_IP4_MIO_W1C"    ,	   0x10701026b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP20_IP4_MIO_W1C"    ,	   0x10701028b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP21_IP4_MIO_W1C"    ,	   0x1070102ab3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP22_IP4_MIO_W1C"    ,	   0x1070102cb3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP23_IP4_MIO_W1C"    ,	   0x1070102eb3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP24_IP4_MIO_W1C"    ,	   0x10701030b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP25_IP4_MIO_W1C"    ,	   0x10701032b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP26_IP4_MIO_W1C"    ,	   0x10701034b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP27_IP4_MIO_W1C"    ,	   0x10701036b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP28_IP4_MIO_W1C"    ,	   0x10701038b3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP29_IP4_MIO_W1C"    ,	   0x1070103ab3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP30_IP4_MIO_W1C"    ,	   0x1070103cb3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP31_IP4_MIO_W1C"    ,	   0x1070103eb3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"CIU2_EN_PP0_IP4_MIO_W1S"     ,	   0x10701000a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP1_IP4_MIO_W1S"     ,	   0x10701002a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP2_IP4_MIO_W1S"     ,	   0x10701004a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP3_IP4_MIO_W1S"     ,	   0x10701006a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP4_IP4_MIO_W1S"     ,	   0x10701008a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP5_IP4_MIO_W1S"     ,	   0x1070100aa3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP6_IP4_MIO_W1S"     ,	   0x1070100ca3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP7_IP4_MIO_W1S"     ,	   0x1070100ea3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP8_IP4_MIO_W1S"     ,	   0x10701010a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP9_IP4_MIO_W1S"     ,	   0x10701012a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP10_IP4_MIO_W1S"    ,	   0x10701014a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP11_IP4_MIO_W1S"    ,	   0x10701016a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP12_IP4_MIO_W1S"    ,	   0x10701018a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP13_IP4_MIO_W1S"    ,	   0x1070101aa3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP14_IP4_MIO_W1S"    ,	   0x1070101ca3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP15_IP4_MIO_W1S"    ,	   0x1070101ea3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP16_IP4_MIO_W1S"    ,	   0x10701020a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP17_IP4_MIO_W1S"    ,	   0x10701022a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP18_IP4_MIO_W1S"    ,	   0x10701024a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP19_IP4_MIO_W1S"    ,	   0x10701026a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP20_IP4_MIO_W1S"    ,	   0x10701028a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP21_IP4_MIO_W1S"    ,	   0x1070102aa3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP22_IP4_MIO_W1S"    ,	   0x1070102ca3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP23_IP4_MIO_W1S"    ,	   0x1070102ea3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP24_IP4_MIO_W1S"    ,	   0x10701030a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP25_IP4_MIO_W1S"    ,	   0x10701032a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP26_IP4_MIO_W1S"    ,	   0x10701034a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP27_IP4_MIO_W1S"    ,	   0x10701036a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP28_IP4_MIO_W1S"    ,	   0x10701038a3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP29_IP4_MIO_W1S"    ,	   0x1070103aa3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP30_IP4_MIO_W1S"    ,	   0x1070103ca3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP31_IP4_MIO_W1S"    ,	   0x1070103ea3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"CIU2_EN_PP0_IP4_PKT"         ,	   0x1070100096400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP1_IP4_PKT"         ,	   0x1070100296400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP2_IP4_PKT"         ,	   0x1070100496400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP3_IP4_PKT"         ,	   0x1070100696400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP4_IP4_PKT"         ,	   0x1070100896400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP5_IP4_PKT"         ,	   0x1070100a96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP6_IP4_PKT"         ,	   0x1070100c96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP7_IP4_PKT"         ,	   0x1070100e96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP8_IP4_PKT"         ,	   0x1070101096400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP9_IP4_PKT"         ,	   0x1070101296400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP10_IP4_PKT"        ,	   0x1070101496400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP11_IP4_PKT"        ,	   0x1070101696400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP12_IP4_PKT"        ,	   0x1070101896400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP13_IP4_PKT"        ,	   0x1070101a96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP14_IP4_PKT"        ,	   0x1070101c96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP15_IP4_PKT"        ,	   0x1070101e96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP16_IP4_PKT"        ,	   0x1070102096400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP17_IP4_PKT"        ,	   0x1070102296400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP18_IP4_PKT"        ,	   0x1070102496400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP19_IP4_PKT"        ,	   0x1070102696400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP20_IP4_PKT"        ,	   0x1070102896400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP21_IP4_PKT"        ,	   0x1070102a96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP22_IP4_PKT"        ,	   0x1070102c96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP23_IP4_PKT"        ,	   0x1070102e96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP24_IP4_PKT"        ,	   0x1070103096400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP25_IP4_PKT"        ,	   0x1070103296400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP26_IP4_PKT"        ,	   0x1070103496400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP27_IP4_PKT"        ,	   0x1070103696400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP28_IP4_PKT"        ,	   0x1070103896400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP29_IP4_PKT"        ,	   0x1070103a96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP30_IP4_PKT"        ,	   0x1070103c96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP31_IP4_PKT"        ,	   0x1070103e96400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"CIU2_EN_PP0_IP4_PKT_W1C"     ,	   0x10701000b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP1_IP4_PKT_W1C"     ,	   0x10701002b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP2_IP4_PKT_W1C"     ,	   0x10701004b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP3_IP4_PKT_W1C"     ,	   0x10701006b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP4_IP4_PKT_W1C"     ,	   0x10701008b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP5_IP4_PKT_W1C"     ,	   0x1070100ab6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP6_IP4_PKT_W1C"     ,	   0x1070100cb6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP7_IP4_PKT_W1C"     ,	   0x1070100eb6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP8_IP4_PKT_W1C"     ,	   0x10701010b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP9_IP4_PKT_W1C"     ,	   0x10701012b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP10_IP4_PKT_W1C"    ,	   0x10701014b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP11_IP4_PKT_W1C"    ,	   0x10701016b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP12_IP4_PKT_W1C"    ,	   0x10701018b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP13_IP4_PKT_W1C"    ,	   0x1070101ab6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP14_IP4_PKT_W1C"    ,	   0x1070101cb6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP15_IP4_PKT_W1C"    ,	   0x1070101eb6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP16_IP4_PKT_W1C"    ,	   0x10701020b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP17_IP4_PKT_W1C"    ,	   0x10701022b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP18_IP4_PKT_W1C"    ,	   0x10701024b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP19_IP4_PKT_W1C"    ,	   0x10701026b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP20_IP4_PKT_W1C"    ,	   0x10701028b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP21_IP4_PKT_W1C"    ,	   0x1070102ab6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP22_IP4_PKT_W1C"    ,	   0x1070102cb6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP23_IP4_PKT_W1C"    ,	   0x1070102eb6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP24_IP4_PKT_W1C"    ,	   0x10701030b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP25_IP4_PKT_W1C"    ,	   0x10701032b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP26_IP4_PKT_W1C"    ,	   0x10701034b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP27_IP4_PKT_W1C"    ,	   0x10701036b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP28_IP4_PKT_W1C"    ,	   0x10701038b6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP29_IP4_PKT_W1C"    ,	   0x1070103ab6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP30_IP4_PKT_W1C"    ,	   0x1070103cb6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP31_IP4_PKT_W1C"    ,	   0x1070103eb6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"CIU2_EN_PP0_IP4_PKT_W1S"     ,	   0x10701000a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP1_IP4_PKT_W1S"     ,	   0x10701002a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP2_IP4_PKT_W1S"     ,	   0x10701004a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP3_IP4_PKT_W1S"     ,	   0x10701006a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP4_IP4_PKT_W1S"     ,	   0x10701008a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP5_IP4_PKT_W1S"     ,	   0x1070100aa6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP6_IP4_PKT_W1S"     ,	   0x1070100ca6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP7_IP4_PKT_W1S"     ,	   0x1070100ea6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP8_IP4_PKT_W1S"     ,	   0x10701010a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP9_IP4_PKT_W1S"     ,	   0x10701012a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP10_IP4_PKT_W1S"    ,	   0x10701014a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP11_IP4_PKT_W1S"    ,	   0x10701016a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP12_IP4_PKT_W1S"    ,	   0x10701018a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP13_IP4_PKT_W1S"    ,	   0x1070101aa6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP14_IP4_PKT_W1S"    ,	   0x1070101ca6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP15_IP4_PKT_W1S"    ,	   0x1070101ea6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP16_IP4_PKT_W1S"    ,	   0x10701020a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP17_IP4_PKT_W1S"    ,	   0x10701022a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP18_IP4_PKT_W1S"    ,	   0x10701024a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP19_IP4_PKT_W1S"    ,	   0x10701026a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP20_IP4_PKT_W1S"    ,	   0x10701028a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP21_IP4_PKT_W1S"    ,	   0x1070102aa6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP22_IP4_PKT_W1S"    ,	   0x1070102ca6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP23_IP4_PKT_W1S"    ,	   0x1070102ea6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP24_IP4_PKT_W1S"    ,	   0x10701030a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP25_IP4_PKT_W1S"    ,	   0x10701032a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP26_IP4_PKT_W1S"    ,	   0x10701034a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP27_IP4_PKT_W1S"    ,	   0x10701036a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP28_IP4_PKT_W1S"    ,	   0x10701038a6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP29_IP4_PKT_W1S"    ,	   0x1070103aa6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP30_IP4_PKT_W1S"    ,	   0x1070103ca6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP31_IP4_PKT_W1S"    ,	   0x1070103ea6400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"CIU2_EN_PP0_IP4_RML"         ,	   0x1070100092400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP1_IP4_RML"         ,	   0x1070100292400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP2_IP4_RML"         ,	   0x1070100492400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP3_IP4_RML"         ,	   0x1070100692400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP4_IP4_RML"         ,	   0x1070100892400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP5_IP4_RML"         ,	   0x1070100a92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP6_IP4_RML"         ,	   0x1070100c92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP7_IP4_RML"         ,	   0x1070100e92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP8_IP4_RML"         ,	   0x1070101092400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP9_IP4_RML"         ,	   0x1070101292400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP10_IP4_RML"        ,	   0x1070101492400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP11_IP4_RML"        ,	   0x1070101692400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP12_IP4_RML"        ,	   0x1070101892400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP13_IP4_RML"        ,	   0x1070101a92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP14_IP4_RML"        ,	   0x1070101c92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP15_IP4_RML"        ,	   0x1070101e92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP16_IP4_RML"        ,	   0x1070102092400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP17_IP4_RML"        ,	   0x1070102292400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP18_IP4_RML"        ,	   0x1070102492400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP19_IP4_RML"        ,	   0x1070102692400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP20_IP4_RML"        ,	   0x1070102892400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP21_IP4_RML"        ,	   0x1070102a92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP22_IP4_RML"        ,	   0x1070102c92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP23_IP4_RML"        ,	   0x1070102e92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP24_IP4_RML"        ,	   0x1070103092400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP25_IP4_RML"        ,	   0x1070103292400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP26_IP4_RML"        ,	   0x1070103492400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP27_IP4_RML"        ,	   0x1070103692400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP28_IP4_RML"        ,	   0x1070103892400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP29_IP4_RML"        ,	   0x1070103a92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP30_IP4_RML"        ,	   0x1070103c92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP31_IP4_RML"        ,	   0x1070103e92400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"CIU2_EN_PP0_IP4_RML_W1C"     ,	   0x10701000b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP1_IP4_RML_W1C"     ,	   0x10701002b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP2_IP4_RML_W1C"     ,	   0x10701004b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP3_IP4_RML_W1C"     ,	   0x10701006b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP4_IP4_RML_W1C"     ,	   0x10701008b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP5_IP4_RML_W1C"     ,	   0x1070100ab2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP6_IP4_RML_W1C"     ,	   0x1070100cb2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP7_IP4_RML_W1C"     ,	   0x1070100eb2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP8_IP4_RML_W1C"     ,	   0x10701010b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP9_IP4_RML_W1C"     ,	   0x10701012b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP10_IP4_RML_W1C"    ,	   0x10701014b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP11_IP4_RML_W1C"    ,	   0x10701016b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP12_IP4_RML_W1C"    ,	   0x10701018b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP13_IP4_RML_W1C"    ,	   0x1070101ab2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP14_IP4_RML_W1C"    ,	   0x1070101cb2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP15_IP4_RML_W1C"    ,	   0x1070101eb2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP16_IP4_RML_W1C"    ,	   0x10701020b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP17_IP4_RML_W1C"    ,	   0x10701022b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP18_IP4_RML_W1C"    ,	   0x10701024b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP19_IP4_RML_W1C"    ,	   0x10701026b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP20_IP4_RML_W1C"    ,	   0x10701028b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP21_IP4_RML_W1C"    ,	   0x1070102ab2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP22_IP4_RML_W1C"    ,	   0x1070102cb2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP23_IP4_RML_W1C"    ,	   0x1070102eb2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP24_IP4_RML_W1C"    ,	   0x10701030b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP25_IP4_RML_W1C"    ,	   0x10701032b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP26_IP4_RML_W1C"    ,	   0x10701034b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP27_IP4_RML_W1C"    ,	   0x10701036b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP28_IP4_RML_W1C"    ,	   0x10701038b2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP29_IP4_RML_W1C"    ,	   0x1070103ab2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP30_IP4_RML_W1C"    ,	   0x1070103cb2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP31_IP4_RML_W1C"    ,	   0x1070103eb2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"CIU2_EN_PP0_IP4_RML_W1S"     ,	   0x10701000a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP1_IP4_RML_W1S"     ,	   0x10701002a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP2_IP4_RML_W1S"     ,	   0x10701004a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP3_IP4_RML_W1S"     ,	   0x10701006a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP4_IP4_RML_W1S"     ,	   0x10701008a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP5_IP4_RML_W1S"     ,	   0x1070100aa2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP6_IP4_RML_W1S"     ,	   0x1070100ca2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP7_IP4_RML_W1S"     ,	   0x1070100ea2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP8_IP4_RML_W1S"     ,	   0x10701010a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP9_IP4_RML_W1S"     ,	   0x10701012a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP10_IP4_RML_W1S"    ,	   0x10701014a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP11_IP4_RML_W1S"    ,	   0x10701016a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP12_IP4_RML_W1S"    ,	   0x10701018a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP13_IP4_RML_W1S"    ,	   0x1070101aa2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP14_IP4_RML_W1S"    ,	   0x1070101ca2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP15_IP4_RML_W1S"    ,	   0x1070101ea2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP16_IP4_RML_W1S"    ,	   0x10701020a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP17_IP4_RML_W1S"    ,	   0x10701022a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP18_IP4_RML_W1S"    ,	   0x10701024a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP19_IP4_RML_W1S"    ,	   0x10701026a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP20_IP4_RML_W1S"    ,	   0x10701028a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP21_IP4_RML_W1S"    ,	   0x1070102aa2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP22_IP4_RML_W1S"    ,	   0x1070102ca2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP23_IP4_RML_W1S"    ,	   0x1070102ea2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP24_IP4_RML_W1S"    ,	   0x10701030a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP25_IP4_RML_W1S"    ,	   0x10701032a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP26_IP4_RML_W1S"    ,	   0x10701034a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP27_IP4_RML_W1S"    ,	   0x10701036a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP28_IP4_RML_W1S"    ,	   0x10701038a2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP29_IP4_RML_W1S"    ,	   0x1070103aa2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP30_IP4_RML_W1S"    ,	   0x1070103ca2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP31_IP4_RML_W1S"    ,	   0x1070103ea2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"CIU2_EN_PP0_IP4_WDOG"        ,	   0x1070100091400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP1_IP4_WDOG"        ,	   0x1070100291400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP2_IP4_WDOG"        ,	   0x1070100491400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP3_IP4_WDOG"        ,	   0x1070100691400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP4_IP4_WDOG"        ,	   0x1070100891400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP5_IP4_WDOG"        ,	   0x1070100a91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP6_IP4_WDOG"        ,	   0x1070100c91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP7_IP4_WDOG"        ,	   0x1070100e91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP8_IP4_WDOG"        ,	   0x1070101091400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP9_IP4_WDOG"        ,	   0x1070101291400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP10_IP4_WDOG"       ,	   0x1070101491400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP11_IP4_WDOG"       ,	   0x1070101691400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP12_IP4_WDOG"       ,	   0x1070101891400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP13_IP4_WDOG"       ,	   0x1070101a91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP14_IP4_WDOG"       ,	   0x1070101c91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP15_IP4_WDOG"       ,	   0x1070101e91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP16_IP4_WDOG"       ,	   0x1070102091400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP17_IP4_WDOG"       ,	   0x1070102291400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP18_IP4_WDOG"       ,	   0x1070102491400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP19_IP4_WDOG"       ,	   0x1070102691400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP20_IP4_WDOG"       ,	   0x1070102891400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP21_IP4_WDOG"       ,	   0x1070102a91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP22_IP4_WDOG"       ,	   0x1070102c91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP23_IP4_WDOG"       ,	   0x1070102e91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP24_IP4_WDOG"       ,	   0x1070103091400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP25_IP4_WDOG"       ,	   0x1070103291400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP26_IP4_WDOG"       ,	   0x1070103491400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP27_IP4_WDOG"       ,	   0x1070103691400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP28_IP4_WDOG"       ,	   0x1070103891400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP29_IP4_WDOG"       ,	   0x1070103a91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP30_IP4_WDOG"       ,	   0x1070103c91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP31_IP4_WDOG"       ,	   0x1070103e91400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"CIU2_EN_PP0_IP4_WDOG_W1C"    ,	   0x10701000b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP1_IP4_WDOG_W1C"    ,	   0x10701002b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP2_IP4_WDOG_W1C"    ,	   0x10701004b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP3_IP4_WDOG_W1C"    ,	   0x10701006b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP4_IP4_WDOG_W1C"    ,	   0x10701008b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP5_IP4_WDOG_W1C"    ,	   0x1070100ab1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP6_IP4_WDOG_W1C"    ,	   0x1070100cb1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP7_IP4_WDOG_W1C"    ,	   0x1070100eb1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP8_IP4_WDOG_W1C"    ,	   0x10701010b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP9_IP4_WDOG_W1C"    ,	   0x10701012b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP10_IP4_WDOG_W1C"   ,	   0x10701014b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP11_IP4_WDOG_W1C"   ,	   0x10701016b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP12_IP4_WDOG_W1C"   ,	   0x10701018b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP13_IP4_WDOG_W1C"   ,	   0x1070101ab1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP14_IP4_WDOG_W1C"   ,	   0x1070101cb1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP15_IP4_WDOG_W1C"   ,	   0x1070101eb1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP16_IP4_WDOG_W1C"   ,	   0x10701020b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP17_IP4_WDOG_W1C"   ,	   0x10701022b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP18_IP4_WDOG_W1C"   ,	   0x10701024b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP19_IP4_WDOG_W1C"   ,	   0x10701026b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP20_IP4_WDOG_W1C"   ,	   0x10701028b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP21_IP4_WDOG_W1C"   ,	   0x1070102ab1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP22_IP4_WDOG_W1C"   ,	   0x1070102cb1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP23_IP4_WDOG_W1C"   ,	   0x1070102eb1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP24_IP4_WDOG_W1C"   ,	   0x10701030b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP25_IP4_WDOG_W1C"   ,	   0x10701032b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP26_IP4_WDOG_W1C"   ,	   0x10701034b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP27_IP4_WDOG_W1C"   ,	   0x10701036b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP28_IP4_WDOG_W1C"   ,	   0x10701038b1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP29_IP4_WDOG_W1C"   ,	   0x1070103ab1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP30_IP4_WDOG_W1C"   ,	   0x1070103cb1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP31_IP4_WDOG_W1C"   ,	   0x1070103eb1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"CIU2_EN_PP0_IP4_WDOG_W1S"    ,	   0x10701000a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP1_IP4_WDOG_W1S"    ,	   0x10701002a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP2_IP4_WDOG_W1S"    ,	   0x10701004a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP3_IP4_WDOG_W1S"    ,	   0x10701006a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP4_IP4_WDOG_W1S"    ,	   0x10701008a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP5_IP4_WDOG_W1S"    ,	   0x1070100aa1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP6_IP4_WDOG_W1S"    ,	   0x1070100ca1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP7_IP4_WDOG_W1S"    ,	   0x1070100ea1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP8_IP4_WDOG_W1S"    ,	   0x10701010a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP9_IP4_WDOG_W1S"    ,	   0x10701012a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP10_IP4_WDOG_W1S"   ,	   0x10701014a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP11_IP4_WDOG_W1S"   ,	   0x10701016a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP12_IP4_WDOG_W1S"   ,	   0x10701018a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP13_IP4_WDOG_W1S"   ,	   0x1070101aa1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP14_IP4_WDOG_W1S"   ,	   0x1070101ca1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP15_IP4_WDOG_W1S"   ,	   0x1070101ea1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP16_IP4_WDOG_W1S"   ,	   0x10701020a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP17_IP4_WDOG_W1S"   ,	   0x10701022a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP18_IP4_WDOG_W1S"   ,	   0x10701024a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP19_IP4_WDOG_W1S"   ,	   0x10701026a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP20_IP4_WDOG_W1S"   ,	   0x10701028a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP21_IP4_WDOG_W1S"   ,	   0x1070102aa1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP22_IP4_WDOG_W1S"   ,	   0x1070102ca1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP23_IP4_WDOG_W1S"   ,	   0x1070102ea1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP24_IP4_WDOG_W1S"   ,	   0x10701030a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP25_IP4_WDOG_W1S"   ,	   0x10701032a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP26_IP4_WDOG_W1S"   ,	   0x10701034a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP27_IP4_WDOG_W1S"   ,	   0x10701036a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP28_IP4_WDOG_W1S"   ,	   0x10701038a1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP29_IP4_WDOG_W1S"   ,	   0x1070103aa1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP30_IP4_WDOG_W1S"   ,	   0x1070103ca1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP31_IP4_WDOG_W1S"   ,	   0x1070103ea1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"CIU2_EN_PP0_IP4_WRKQ"        ,	   0x1070100090400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP1_IP4_WRKQ"        ,	   0x1070100290400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP2_IP4_WRKQ"        ,	   0x1070100490400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP3_IP4_WRKQ"        ,	   0x1070100690400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP4_IP4_WRKQ"        ,	   0x1070100890400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP5_IP4_WRKQ"        ,	   0x1070100a90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP6_IP4_WRKQ"        ,	   0x1070100c90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP7_IP4_WRKQ"        ,	   0x1070100e90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP8_IP4_WRKQ"        ,	   0x1070101090400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP9_IP4_WRKQ"        ,	   0x1070101290400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP10_IP4_WRKQ"       ,	   0x1070101490400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP11_IP4_WRKQ"       ,	   0x1070101690400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP12_IP4_WRKQ"       ,	   0x1070101890400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP13_IP4_WRKQ"       ,	   0x1070101a90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP14_IP4_WRKQ"       ,	   0x1070101c90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP15_IP4_WRKQ"       ,	   0x1070101e90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP16_IP4_WRKQ"       ,	   0x1070102090400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP17_IP4_WRKQ"       ,	   0x1070102290400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP18_IP4_WRKQ"       ,	   0x1070102490400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP19_IP4_WRKQ"       ,	   0x1070102690400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP20_IP4_WRKQ"       ,	   0x1070102890400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP21_IP4_WRKQ"       ,	   0x1070102a90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP22_IP4_WRKQ"       ,	   0x1070102c90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP23_IP4_WRKQ"       ,	   0x1070102e90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP24_IP4_WRKQ"       ,	   0x1070103090400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP25_IP4_WRKQ"       ,	   0x1070103290400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP26_IP4_WRKQ"       ,	   0x1070103490400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP27_IP4_WRKQ"       ,	   0x1070103690400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP28_IP4_WRKQ"       ,	   0x1070103890400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP29_IP4_WRKQ"       ,	   0x1070103a90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP30_IP4_WRKQ"       ,	   0x1070103c90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP31_IP4_WRKQ"       ,	   0x1070103e90400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"CIU2_EN_PP0_IP4_WRKQ_W1C"    ,	   0x10701000b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP1_IP4_WRKQ_W1C"    ,	   0x10701002b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP2_IP4_WRKQ_W1C"    ,	   0x10701004b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP3_IP4_WRKQ_W1C"    ,	   0x10701006b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP4_IP4_WRKQ_W1C"    ,	   0x10701008b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP5_IP4_WRKQ_W1C"    ,	   0x1070100ab0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP6_IP4_WRKQ_W1C"    ,	   0x1070100cb0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP7_IP4_WRKQ_W1C"    ,	   0x1070100eb0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP8_IP4_WRKQ_W1C"    ,	   0x10701010b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP9_IP4_WRKQ_W1C"    ,	   0x10701012b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP10_IP4_WRKQ_W1C"   ,	   0x10701014b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP11_IP4_WRKQ_W1C"   ,	   0x10701016b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP12_IP4_WRKQ_W1C"   ,	   0x10701018b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP13_IP4_WRKQ_W1C"   ,	   0x1070101ab0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP14_IP4_WRKQ_W1C"   ,	   0x1070101cb0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP15_IP4_WRKQ_W1C"   ,	   0x1070101eb0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP16_IP4_WRKQ_W1C"   ,	   0x10701020b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP17_IP4_WRKQ_W1C"   ,	   0x10701022b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP18_IP4_WRKQ_W1C"   ,	   0x10701024b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP19_IP4_WRKQ_W1C"   ,	   0x10701026b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP20_IP4_WRKQ_W1C"   ,	   0x10701028b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP21_IP4_WRKQ_W1C"   ,	   0x1070102ab0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP22_IP4_WRKQ_W1C"   ,	   0x1070102cb0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP23_IP4_WRKQ_W1C"   ,	   0x1070102eb0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP24_IP4_WRKQ_W1C"   ,	   0x10701030b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP25_IP4_WRKQ_W1C"   ,	   0x10701032b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP26_IP4_WRKQ_W1C"   ,	   0x10701034b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP27_IP4_WRKQ_W1C"   ,	   0x10701036b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP28_IP4_WRKQ_W1C"   ,	   0x10701038b0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP29_IP4_WRKQ_W1C"   ,	   0x1070103ab0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP30_IP4_WRKQ_W1C"   ,	   0x1070103cb0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP31_IP4_WRKQ_W1C"   ,	   0x1070103eb0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"CIU2_EN_PP0_IP4_WRKQ_W1S"    ,	   0x10701000a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP1_IP4_WRKQ_W1S"    ,	   0x10701002a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP2_IP4_WRKQ_W1S"    ,	   0x10701004a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP3_IP4_WRKQ_W1S"    ,	   0x10701006a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP4_IP4_WRKQ_W1S"    ,	   0x10701008a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP5_IP4_WRKQ_W1S"    ,	   0x1070100aa0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP6_IP4_WRKQ_W1S"    ,	   0x1070100ca0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP7_IP4_WRKQ_W1S"    ,	   0x1070100ea0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP8_IP4_WRKQ_W1S"    ,	   0x10701010a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP9_IP4_WRKQ_W1S"    ,	   0x10701012a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP10_IP4_WRKQ_W1S"   ,	   0x10701014a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP11_IP4_WRKQ_W1S"   ,	   0x10701016a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP12_IP4_WRKQ_W1S"   ,	   0x10701018a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP13_IP4_WRKQ_W1S"   ,	   0x1070101aa0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP14_IP4_WRKQ_W1S"   ,	   0x1070101ca0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP15_IP4_WRKQ_W1S"   ,	   0x1070101ea0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP16_IP4_WRKQ_W1S"   ,	   0x10701020a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP17_IP4_WRKQ_W1S"   ,	   0x10701022a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP18_IP4_WRKQ_W1S"   ,	   0x10701024a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP19_IP4_WRKQ_W1S"   ,	   0x10701026a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP20_IP4_WRKQ_W1S"   ,	   0x10701028a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP21_IP4_WRKQ_W1S"   ,	   0x1070102aa0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP22_IP4_WRKQ_W1S"   ,	   0x1070102ca0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP23_IP4_WRKQ_W1S"   ,	   0x1070102ea0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP24_IP4_WRKQ_W1S"   ,	   0x10701030a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP25_IP4_WRKQ_W1S"   ,	   0x10701032a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP26_IP4_WRKQ_W1S"   ,	   0x10701034a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP27_IP4_WRKQ_W1S"   ,	   0x10701036a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP28_IP4_WRKQ_W1S"   ,	   0x10701038a0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP29_IP4_WRKQ_W1S"   ,	   0x1070103aa0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP30_IP4_WRKQ_W1S"   ,	   0x1070103ca0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_EN_PP31_IP4_WRKQ_W1S"   ,	   0x1070103ea0400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"CIU2_INTR_CIU_READY"         ,	   0x1070100102008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"CIU2_INTR_RAM_ECC_CTL"       ,	   0x1070100102010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	185},
+	{"CIU2_INTR_RAM_ECC_ST"        ,	   0x1070100102018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	186},
+	{"CIU2_INTR_SLOWDOWN"          ,	   0x1070100102000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	187},
+	{"CIU2_MSI_RCV0"               ,	   0x10701000c2000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV1"               ,	   0x10701000c2008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV2"               ,	   0x10701000c2010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV3"               ,	   0x10701000c2018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV4"               ,	   0x10701000c2020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV5"               ,	   0x10701000c2028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV6"               ,	   0x10701000c2030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV7"               ,	   0x10701000c2038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV8"               ,	   0x10701000c2040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV9"               ,	   0x10701000c2048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV10"              ,	   0x10701000c2050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV11"              ,	   0x10701000c2058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV12"              ,	   0x10701000c2060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV13"              ,	   0x10701000c2068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV14"              ,	   0x10701000c2070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV15"              ,	   0x10701000c2078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV16"              ,	   0x10701000c2080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV17"              ,	   0x10701000c2088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV18"              ,	   0x10701000c2090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV19"              ,	   0x10701000c2098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV20"              ,	   0x10701000c20a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV21"              ,	   0x10701000c20a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV22"              ,	   0x10701000c20b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV23"              ,	   0x10701000c20b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV24"              ,	   0x10701000c20c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV25"              ,	   0x10701000c20c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV26"              ,	   0x10701000c20d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV27"              ,	   0x10701000c20d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV28"              ,	   0x10701000c20e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV29"              ,	   0x10701000c20e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV30"              ,	   0x10701000c20f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV31"              ,	   0x10701000c20f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV32"              ,	   0x10701000c2100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV33"              ,	   0x10701000c2108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV34"              ,	   0x10701000c2110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV35"              ,	   0x10701000c2118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV36"              ,	   0x10701000c2120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV37"              ,	   0x10701000c2128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV38"              ,	   0x10701000c2130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV39"              ,	   0x10701000c2138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV40"              ,	   0x10701000c2140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV41"              ,	   0x10701000c2148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV42"              ,	   0x10701000c2150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV43"              ,	   0x10701000c2158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV44"              ,	   0x10701000c2160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV45"              ,	   0x10701000c2168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV46"              ,	   0x10701000c2170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV47"              ,	   0x10701000c2178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV48"              ,	   0x10701000c2180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV49"              ,	   0x10701000c2188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV50"              ,	   0x10701000c2190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV51"              ,	   0x10701000c2198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV52"              ,	   0x10701000c21a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV53"              ,	   0x10701000c21a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV54"              ,	   0x10701000c21b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV55"              ,	   0x10701000c21b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV56"              ,	   0x10701000c21c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV57"              ,	   0x10701000c21c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV58"              ,	   0x10701000c21d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV59"              ,	   0x10701000c21d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV60"              ,	   0x10701000c21e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV61"              ,	   0x10701000c21e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV62"              ,	   0x10701000c21f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV63"              ,	   0x10701000c21f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV64"              ,	   0x10701000c2200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV65"              ,	   0x10701000c2208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV66"              ,	   0x10701000c2210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV67"              ,	   0x10701000c2218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV68"              ,	   0x10701000c2220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV69"              ,	   0x10701000c2228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV70"              ,	   0x10701000c2230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV71"              ,	   0x10701000c2238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV72"              ,	   0x10701000c2240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV73"              ,	   0x10701000c2248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV74"              ,	   0x10701000c2250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV75"              ,	   0x10701000c2258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV76"              ,	   0x10701000c2260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV77"              ,	   0x10701000c2268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV78"              ,	   0x10701000c2270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV79"              ,	   0x10701000c2278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV80"              ,	   0x10701000c2280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV81"              ,	   0x10701000c2288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV82"              ,	   0x10701000c2290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV83"              ,	   0x10701000c2298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV84"              ,	   0x10701000c22a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV85"              ,	   0x10701000c22a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV86"              ,	   0x10701000c22b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV87"              ,	   0x10701000c22b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV88"              ,	   0x10701000c22c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV89"              ,	   0x10701000c22c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV90"              ,	   0x10701000c22d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV91"              ,	   0x10701000c22d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV92"              ,	   0x10701000c22e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV93"              ,	   0x10701000c22e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV94"              ,	   0x10701000c22f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV95"              ,	   0x10701000c22f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV96"              ,	   0x10701000c2300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV97"              ,	   0x10701000c2308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV98"              ,	   0x10701000c2310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV99"              ,	   0x10701000c2318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV100"             ,	   0x10701000c2320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV101"             ,	   0x10701000c2328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV102"             ,	   0x10701000c2330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV103"             ,	   0x10701000c2338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV104"             ,	   0x10701000c2340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV105"             ,	   0x10701000c2348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV106"             ,	   0x10701000c2350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV107"             ,	   0x10701000c2358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV108"             ,	   0x10701000c2360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV109"             ,	   0x10701000c2368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV110"             ,	   0x10701000c2370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV111"             ,	   0x10701000c2378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV112"             ,	   0x10701000c2380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV113"             ,	   0x10701000c2388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV114"             ,	   0x10701000c2390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV115"             ,	   0x10701000c2398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV116"             ,	   0x10701000c23a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV117"             ,	   0x10701000c23a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV118"             ,	   0x10701000c23b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV119"             ,	   0x10701000c23b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV120"             ,	   0x10701000c23c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV121"             ,	   0x10701000c23c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV122"             ,	   0x10701000c23d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV123"             ,	   0x10701000c23d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV124"             ,	   0x10701000c23e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV125"             ,	   0x10701000c23e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV126"             ,	   0x10701000c23f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV127"             ,	   0x10701000c23f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV128"             ,	   0x10701000c2400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV129"             ,	   0x10701000c2408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV130"             ,	   0x10701000c2410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV131"             ,	   0x10701000c2418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV132"             ,	   0x10701000c2420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV133"             ,	   0x10701000c2428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV134"             ,	   0x10701000c2430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV135"             ,	   0x10701000c2438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV136"             ,	   0x10701000c2440ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV137"             ,	   0x10701000c2448ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV138"             ,	   0x10701000c2450ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV139"             ,	   0x10701000c2458ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV140"             ,	   0x10701000c2460ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV141"             ,	   0x10701000c2468ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV142"             ,	   0x10701000c2470ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV143"             ,	   0x10701000c2478ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV144"             ,	   0x10701000c2480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV145"             ,	   0x10701000c2488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV146"             ,	   0x10701000c2490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV147"             ,	   0x10701000c2498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV148"             ,	   0x10701000c24a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV149"             ,	   0x10701000c24a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV150"             ,	   0x10701000c24b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV151"             ,	   0x10701000c24b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV152"             ,	   0x10701000c24c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV153"             ,	   0x10701000c24c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV154"             ,	   0x10701000c24d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV155"             ,	   0x10701000c24d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV156"             ,	   0x10701000c24e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV157"             ,	   0x10701000c24e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV158"             ,	   0x10701000c24f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV159"             ,	   0x10701000c24f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV160"             ,	   0x10701000c2500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV161"             ,	   0x10701000c2508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV162"             ,	   0x10701000c2510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV163"             ,	   0x10701000c2518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV164"             ,	   0x10701000c2520ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV165"             ,	   0x10701000c2528ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV166"             ,	   0x10701000c2530ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV167"             ,	   0x10701000c2538ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV168"             ,	   0x10701000c2540ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV169"             ,	   0x10701000c2548ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV170"             ,	   0x10701000c2550ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV171"             ,	   0x10701000c2558ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV172"             ,	   0x10701000c2560ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV173"             ,	   0x10701000c2568ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV174"             ,	   0x10701000c2570ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV175"             ,	   0x10701000c2578ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV176"             ,	   0x10701000c2580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV177"             ,	   0x10701000c2588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV178"             ,	   0x10701000c2590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV179"             ,	   0x10701000c2598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV180"             ,	   0x10701000c25a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV181"             ,	   0x10701000c25a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV182"             ,	   0x10701000c25b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV183"             ,	   0x10701000c25b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV184"             ,	   0x10701000c25c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV185"             ,	   0x10701000c25c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV186"             ,	   0x10701000c25d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV187"             ,	   0x10701000c25d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV188"             ,	   0x10701000c25e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV189"             ,	   0x10701000c25e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV190"             ,	   0x10701000c25f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV191"             ,	   0x10701000c25f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV192"             ,	   0x10701000c2600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV193"             ,	   0x10701000c2608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV194"             ,	   0x10701000c2610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV195"             ,	   0x10701000c2618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV196"             ,	   0x10701000c2620ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV197"             ,	   0x10701000c2628ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV198"             ,	   0x10701000c2630ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV199"             ,	   0x10701000c2638ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV200"             ,	   0x10701000c2640ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV201"             ,	   0x10701000c2648ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV202"             ,	   0x10701000c2650ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV203"             ,	   0x10701000c2658ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV204"             ,	   0x10701000c2660ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV205"             ,	   0x10701000c2668ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV206"             ,	   0x10701000c2670ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV207"             ,	   0x10701000c2678ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV208"             ,	   0x10701000c2680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV209"             ,	   0x10701000c2688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV210"             ,	   0x10701000c2690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV211"             ,	   0x10701000c2698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV212"             ,	   0x10701000c26a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV213"             ,	   0x10701000c26a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV214"             ,	   0x10701000c26b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV215"             ,	   0x10701000c26b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV216"             ,	   0x10701000c26c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV217"             ,	   0x10701000c26c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV218"             ,	   0x10701000c26d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV219"             ,	   0x10701000c26d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV220"             ,	   0x10701000c26e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV221"             ,	   0x10701000c26e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV222"             ,	   0x10701000c26f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV223"             ,	   0x10701000c26f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV224"             ,	   0x10701000c2700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV225"             ,	   0x10701000c2708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV226"             ,	   0x10701000c2710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV227"             ,	   0x10701000c2718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV228"             ,	   0x10701000c2720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV229"             ,	   0x10701000c2728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV230"             ,	   0x10701000c2730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV231"             ,	   0x10701000c2738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV232"             ,	   0x10701000c2740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV233"             ,	   0x10701000c2748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV234"             ,	   0x10701000c2750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV235"             ,	   0x10701000c2758ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV236"             ,	   0x10701000c2760ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV237"             ,	   0x10701000c2768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV238"             ,	   0x10701000c2770ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV239"             ,	   0x10701000c2778ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV240"             ,	   0x10701000c2780ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV241"             ,	   0x10701000c2788ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV242"             ,	   0x10701000c2790ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV243"             ,	   0x10701000c2798ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV244"             ,	   0x10701000c27a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV245"             ,	   0x10701000c27a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV246"             ,	   0x10701000c27b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV247"             ,	   0x10701000c27b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV248"             ,	   0x10701000c27c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV249"             ,	   0x10701000c27c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV250"             ,	   0x10701000c27d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV251"             ,	   0x10701000c27d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV252"             ,	   0x10701000c27e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV253"             ,	   0x10701000c27e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV254"             ,	   0x10701000c27f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_RCV255"             ,	   0x10701000c27f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"CIU2_MSI_SEL0"               ,	   0x10701000c3000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL1"               ,	   0x10701000c3008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL2"               ,	   0x10701000c3010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL3"               ,	   0x10701000c3018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL4"               ,	   0x10701000c3020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL5"               ,	   0x10701000c3028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL6"               ,	   0x10701000c3030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL7"               ,	   0x10701000c3038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL8"               ,	   0x10701000c3040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL9"               ,	   0x10701000c3048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL10"              ,	   0x10701000c3050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL11"              ,	   0x10701000c3058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL12"              ,	   0x10701000c3060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL13"              ,	   0x10701000c3068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL14"              ,	   0x10701000c3070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL15"              ,	   0x10701000c3078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL16"              ,	   0x10701000c3080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL17"              ,	   0x10701000c3088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL18"              ,	   0x10701000c3090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL19"              ,	   0x10701000c3098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL20"              ,	   0x10701000c30a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL21"              ,	   0x10701000c30a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL22"              ,	   0x10701000c30b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL23"              ,	   0x10701000c30b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL24"              ,	   0x10701000c30c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL25"              ,	   0x10701000c30c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL26"              ,	   0x10701000c30d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL27"              ,	   0x10701000c30d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL28"              ,	   0x10701000c30e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL29"              ,	   0x10701000c30e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL30"              ,	   0x10701000c30f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL31"              ,	   0x10701000c30f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL32"              ,	   0x10701000c3100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL33"              ,	   0x10701000c3108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL34"              ,	   0x10701000c3110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL35"              ,	   0x10701000c3118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL36"              ,	   0x10701000c3120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL37"              ,	   0x10701000c3128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL38"              ,	   0x10701000c3130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL39"              ,	   0x10701000c3138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL40"              ,	   0x10701000c3140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL41"              ,	   0x10701000c3148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL42"              ,	   0x10701000c3150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL43"              ,	   0x10701000c3158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL44"              ,	   0x10701000c3160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL45"              ,	   0x10701000c3168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL46"              ,	   0x10701000c3170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL47"              ,	   0x10701000c3178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL48"              ,	   0x10701000c3180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL49"              ,	   0x10701000c3188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL50"              ,	   0x10701000c3190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL51"              ,	   0x10701000c3198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL52"              ,	   0x10701000c31a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL53"              ,	   0x10701000c31a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL54"              ,	   0x10701000c31b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL55"              ,	   0x10701000c31b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL56"              ,	   0x10701000c31c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL57"              ,	   0x10701000c31c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL58"              ,	   0x10701000c31d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL59"              ,	   0x10701000c31d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL60"              ,	   0x10701000c31e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL61"              ,	   0x10701000c31e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL62"              ,	   0x10701000c31f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL63"              ,	   0x10701000c31f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL64"              ,	   0x10701000c3200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL65"              ,	   0x10701000c3208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL66"              ,	   0x10701000c3210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL67"              ,	   0x10701000c3218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL68"              ,	   0x10701000c3220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL69"              ,	   0x10701000c3228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL70"              ,	   0x10701000c3230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL71"              ,	   0x10701000c3238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL72"              ,	   0x10701000c3240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL73"              ,	   0x10701000c3248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL74"              ,	   0x10701000c3250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL75"              ,	   0x10701000c3258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL76"              ,	   0x10701000c3260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL77"              ,	   0x10701000c3268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL78"              ,	   0x10701000c3270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL79"              ,	   0x10701000c3278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL80"              ,	   0x10701000c3280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL81"              ,	   0x10701000c3288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL82"              ,	   0x10701000c3290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL83"              ,	   0x10701000c3298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL84"              ,	   0x10701000c32a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL85"              ,	   0x10701000c32a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL86"              ,	   0x10701000c32b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL87"              ,	   0x10701000c32b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL88"              ,	   0x10701000c32c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL89"              ,	   0x10701000c32c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL90"              ,	   0x10701000c32d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL91"              ,	   0x10701000c32d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL92"              ,	   0x10701000c32e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL93"              ,	   0x10701000c32e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL94"              ,	   0x10701000c32f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL95"              ,	   0x10701000c32f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL96"              ,	   0x10701000c3300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL97"              ,	   0x10701000c3308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL98"              ,	   0x10701000c3310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL99"              ,	   0x10701000c3318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL100"             ,	   0x10701000c3320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL101"             ,	   0x10701000c3328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL102"             ,	   0x10701000c3330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL103"             ,	   0x10701000c3338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL104"             ,	   0x10701000c3340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL105"             ,	   0x10701000c3348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL106"             ,	   0x10701000c3350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL107"             ,	   0x10701000c3358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL108"             ,	   0x10701000c3360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL109"             ,	   0x10701000c3368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL110"             ,	   0x10701000c3370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL111"             ,	   0x10701000c3378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL112"             ,	   0x10701000c3380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL113"             ,	   0x10701000c3388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL114"             ,	   0x10701000c3390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL115"             ,	   0x10701000c3398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL116"             ,	   0x10701000c33a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL117"             ,	   0x10701000c33a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL118"             ,	   0x10701000c33b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL119"             ,	   0x10701000c33b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL120"             ,	   0x10701000c33c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL121"             ,	   0x10701000c33c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL122"             ,	   0x10701000c33d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL123"             ,	   0x10701000c33d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL124"             ,	   0x10701000c33e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL125"             ,	   0x10701000c33e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL126"             ,	   0x10701000c33f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL127"             ,	   0x10701000c33f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL128"             ,	   0x10701000c3400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL129"             ,	   0x10701000c3408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL130"             ,	   0x10701000c3410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL131"             ,	   0x10701000c3418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL132"             ,	   0x10701000c3420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL133"             ,	   0x10701000c3428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL134"             ,	   0x10701000c3430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL135"             ,	   0x10701000c3438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL136"             ,	   0x10701000c3440ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL137"             ,	   0x10701000c3448ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL138"             ,	   0x10701000c3450ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL139"             ,	   0x10701000c3458ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL140"             ,	   0x10701000c3460ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL141"             ,	   0x10701000c3468ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL142"             ,	   0x10701000c3470ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL143"             ,	   0x10701000c3478ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL144"             ,	   0x10701000c3480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL145"             ,	   0x10701000c3488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL146"             ,	   0x10701000c3490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL147"             ,	   0x10701000c3498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL148"             ,	   0x10701000c34a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL149"             ,	   0x10701000c34a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL150"             ,	   0x10701000c34b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL151"             ,	   0x10701000c34b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL152"             ,	   0x10701000c34c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL153"             ,	   0x10701000c34c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL154"             ,	   0x10701000c34d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL155"             ,	   0x10701000c34d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL156"             ,	   0x10701000c34e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL157"             ,	   0x10701000c34e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL158"             ,	   0x10701000c34f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL159"             ,	   0x10701000c34f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL160"             ,	   0x10701000c3500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL161"             ,	   0x10701000c3508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL162"             ,	   0x10701000c3510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL163"             ,	   0x10701000c3518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL164"             ,	   0x10701000c3520ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL165"             ,	   0x10701000c3528ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL166"             ,	   0x10701000c3530ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL167"             ,	   0x10701000c3538ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL168"             ,	   0x10701000c3540ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL169"             ,	   0x10701000c3548ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL170"             ,	   0x10701000c3550ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL171"             ,	   0x10701000c3558ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL172"             ,	   0x10701000c3560ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL173"             ,	   0x10701000c3568ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL174"             ,	   0x10701000c3570ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL175"             ,	   0x10701000c3578ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL176"             ,	   0x10701000c3580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL177"             ,	   0x10701000c3588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL178"             ,	   0x10701000c3590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL179"             ,	   0x10701000c3598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL180"             ,	   0x10701000c35a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL181"             ,	   0x10701000c35a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL182"             ,	   0x10701000c35b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL183"             ,	   0x10701000c35b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL184"             ,	   0x10701000c35c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL185"             ,	   0x10701000c35c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL186"             ,	   0x10701000c35d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL187"             ,	   0x10701000c35d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL188"             ,	   0x10701000c35e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL189"             ,	   0x10701000c35e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL190"             ,	   0x10701000c35f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL191"             ,	   0x10701000c35f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL192"             ,	   0x10701000c3600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL193"             ,	   0x10701000c3608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL194"             ,	   0x10701000c3610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL195"             ,	   0x10701000c3618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL196"             ,	   0x10701000c3620ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL197"             ,	   0x10701000c3628ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL198"             ,	   0x10701000c3630ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL199"             ,	   0x10701000c3638ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL200"             ,	   0x10701000c3640ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL201"             ,	   0x10701000c3648ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL202"             ,	   0x10701000c3650ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL203"             ,	   0x10701000c3658ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL204"             ,	   0x10701000c3660ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL205"             ,	   0x10701000c3668ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL206"             ,	   0x10701000c3670ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL207"             ,	   0x10701000c3678ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL208"             ,	   0x10701000c3680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL209"             ,	   0x10701000c3688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL210"             ,	   0x10701000c3690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL211"             ,	   0x10701000c3698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL212"             ,	   0x10701000c36a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL213"             ,	   0x10701000c36a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL214"             ,	   0x10701000c36b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL215"             ,	   0x10701000c36b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL216"             ,	   0x10701000c36c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL217"             ,	   0x10701000c36c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL218"             ,	   0x10701000c36d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL219"             ,	   0x10701000c36d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL220"             ,	   0x10701000c36e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL221"             ,	   0x10701000c36e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL222"             ,	   0x10701000c36f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL223"             ,	   0x10701000c36f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL224"             ,	   0x10701000c3700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL225"             ,	   0x10701000c3708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL226"             ,	   0x10701000c3710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL227"             ,	   0x10701000c3718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL228"             ,	   0x10701000c3720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL229"             ,	   0x10701000c3728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL230"             ,	   0x10701000c3730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL231"             ,	   0x10701000c3738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL232"             ,	   0x10701000c3740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL233"             ,	   0x10701000c3748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL234"             ,	   0x10701000c3750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL235"             ,	   0x10701000c3758ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL236"             ,	   0x10701000c3760ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL237"             ,	   0x10701000c3768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL238"             ,	   0x10701000c3770ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL239"             ,	   0x10701000c3778ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL240"             ,	   0x10701000c3780ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL241"             ,	   0x10701000c3788ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL242"             ,	   0x10701000c3790ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL243"             ,	   0x10701000c3798ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL244"             ,	   0x10701000c37a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL245"             ,	   0x10701000c37a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL246"             ,	   0x10701000c37b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL247"             ,	   0x10701000c37b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL248"             ,	   0x10701000c37c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL249"             ,	   0x10701000c37c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL250"             ,	   0x10701000c37d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL251"             ,	   0x10701000c37d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL252"             ,	   0x10701000c37e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL253"             ,	   0x10701000c37e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL254"             ,	   0x10701000c37f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSI_SEL255"             ,	   0x10701000c37f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"CIU2_MSIRED_PP0_IP2"         ,	   0x10701000c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP1_IP2"         ,	   0x10701002c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP2_IP2"         ,	   0x10701004c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP3_IP2"         ,	   0x10701006c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP4_IP2"         ,	   0x10701008c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP5_IP2"         ,	   0x1070100ac1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP6_IP2"         ,	   0x1070100cc1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP7_IP2"         ,	   0x1070100ec1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP8_IP2"         ,	   0x10701010c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP9_IP2"         ,	   0x10701012c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP10_IP2"        ,	   0x10701014c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP11_IP2"        ,	   0x10701016c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP12_IP2"        ,	   0x10701018c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP13_IP2"        ,	   0x1070101ac1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP14_IP2"        ,	   0x1070101cc1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP15_IP2"        ,	   0x1070101ec1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP16_IP2"        ,	   0x10701020c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP17_IP2"        ,	   0x10701022c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP18_IP2"        ,	   0x10701024c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP19_IP2"        ,	   0x10701026c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP20_IP2"        ,	   0x10701028c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP21_IP2"        ,	   0x1070102ac1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP22_IP2"        ,	   0x1070102cc1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP23_IP2"        ,	   0x1070102ec1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP24_IP2"        ,	   0x10701030c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP25_IP2"        ,	   0x10701032c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP26_IP2"        ,	   0x10701034c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP27_IP2"        ,	   0x10701036c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP28_IP2"        ,	   0x10701038c1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP29_IP2"        ,	   0x1070103ac1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP30_IP2"        ,	   0x1070103cc1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP31_IP2"        ,	   0x1070103ec1000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"CIU2_MSIRED_PP0_IP3"         ,	   0x10701000c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP1_IP3"         ,	   0x10701002c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP2_IP3"         ,	   0x10701004c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP3_IP3"         ,	   0x10701006c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP4_IP3"         ,	   0x10701008c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP5_IP3"         ,	   0x1070100ac1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP6_IP3"         ,	   0x1070100cc1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP7_IP3"         ,	   0x1070100ec1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP8_IP3"         ,	   0x10701010c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP9_IP3"         ,	   0x10701012c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP10_IP3"        ,	   0x10701014c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP11_IP3"        ,	   0x10701016c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP12_IP3"        ,	   0x10701018c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP13_IP3"        ,	   0x1070101ac1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP14_IP3"        ,	   0x1070101cc1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP15_IP3"        ,	   0x1070101ec1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP16_IP3"        ,	   0x10701020c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP17_IP3"        ,	   0x10701022c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP18_IP3"        ,	   0x10701024c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP19_IP3"        ,	   0x10701026c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP20_IP3"        ,	   0x10701028c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP21_IP3"        ,	   0x1070102ac1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP22_IP3"        ,	   0x1070102cc1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP23_IP3"        ,	   0x1070102ec1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP24_IP3"        ,	   0x10701030c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP25_IP3"        ,	   0x10701032c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP26_IP3"        ,	   0x10701034c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP27_IP3"        ,	   0x10701036c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP28_IP3"        ,	   0x10701038c1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP29_IP3"        ,	   0x1070103ac1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP30_IP3"        ,	   0x1070103cc1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP31_IP3"        ,	   0x1070103ec1200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"CIU2_MSIRED_PP0_IP4"         ,	   0x10701000c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP1_IP4"         ,	   0x10701002c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP2_IP4"         ,	   0x10701004c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP3_IP4"         ,	   0x10701006c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP4_IP4"         ,	   0x10701008c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP5_IP4"         ,	   0x1070100ac1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP6_IP4"         ,	   0x1070100cc1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP7_IP4"         ,	   0x1070100ec1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP8_IP4"         ,	   0x10701010c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP9_IP4"         ,	   0x10701012c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP10_IP4"        ,	   0x10701014c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP11_IP4"        ,	   0x10701016c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP12_IP4"        ,	   0x10701018c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP13_IP4"        ,	   0x1070101ac1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP14_IP4"        ,	   0x1070101cc1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP15_IP4"        ,	   0x1070101ec1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP16_IP4"        ,	   0x10701020c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP17_IP4"        ,	   0x10701022c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP18_IP4"        ,	   0x10701024c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP19_IP4"        ,	   0x10701026c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP20_IP4"        ,	   0x10701028c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP21_IP4"        ,	   0x1070102ac1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP22_IP4"        ,	   0x1070102cc1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP23_IP4"        ,	   0x1070102ec1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP24_IP4"        ,	   0x10701030c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP25_IP4"        ,	   0x10701032c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP26_IP4"        ,	   0x10701034c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP27_IP4"        ,	   0x10701036c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP28_IP4"        ,	   0x10701038c1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP29_IP4"        ,	   0x1070103ac1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP30_IP4"        ,	   0x1070103cc1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_MSIRED_PP31_IP4"        ,	   0x1070103ec1400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"CIU2_RAW_IO0_INT_GPIO"       ,	   0x1070108047800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	193},
+	{"CIU2_RAW_IO1_INT_GPIO"       ,	   0x1070108247800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	193},
+	{"CIU2_RAW_IO0_INT_IO"         ,	   0x1070108044800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"CIU2_RAW_IO1_INT_IO"         ,	   0x1070108244800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"CIU2_RAW_IO0_INT_MEM"        ,	   0x1070108045800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"CIU2_RAW_IO1_INT_MEM"        ,	   0x1070108245800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"CIU2_RAW_IO0_INT_MIO"        ,	   0x1070108043800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"CIU2_RAW_IO1_INT_MIO"        ,	   0x1070108243800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"CIU2_RAW_IO0_INT_PKT"        ,	   0x1070108046800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"CIU2_RAW_IO1_INT_PKT"        ,	   0x1070108246800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"CIU2_RAW_IO0_INT_RML"        ,	   0x1070108042800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"CIU2_RAW_IO1_INT_RML"        ,	   0x1070108242800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"CIU2_RAW_IO0_INT_WDOG"       ,	   0x1070108041800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"CIU2_RAW_IO1_INT_WDOG"       ,	   0x1070108241800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"CIU2_RAW_IO0_INT_WRKQ"       ,	   0x1070108040800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"CIU2_RAW_IO1_INT_WRKQ"       ,	   0x1070108240800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"CIU2_RAW_PP0_IP2_GPIO"       ,	   0x1070100047000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP1_IP2_GPIO"       ,	   0x1070100247000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP2_IP2_GPIO"       ,	   0x1070100447000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP3_IP2_GPIO"       ,	   0x1070100647000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP4_IP2_GPIO"       ,	   0x1070100847000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP5_IP2_GPIO"       ,	   0x1070100a47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP6_IP2_GPIO"       ,	   0x1070100c47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP7_IP2_GPIO"       ,	   0x1070100e47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP8_IP2_GPIO"       ,	   0x1070101047000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP9_IP2_GPIO"       ,	   0x1070101247000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP10_IP2_GPIO"      ,	   0x1070101447000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP11_IP2_GPIO"      ,	   0x1070101647000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP12_IP2_GPIO"      ,	   0x1070101847000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP13_IP2_GPIO"      ,	   0x1070101a47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP14_IP2_GPIO"      ,	   0x1070101c47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP15_IP2_GPIO"      ,	   0x1070101e47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP16_IP2_GPIO"      ,	   0x1070102047000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP17_IP2_GPIO"      ,	   0x1070102247000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP18_IP2_GPIO"      ,	   0x1070102447000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP19_IP2_GPIO"      ,	   0x1070102647000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP20_IP2_GPIO"      ,	   0x1070102847000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP21_IP2_GPIO"      ,	   0x1070102a47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP22_IP2_GPIO"      ,	   0x1070102c47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP23_IP2_GPIO"      ,	   0x1070102e47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP24_IP2_GPIO"      ,	   0x1070103047000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP25_IP2_GPIO"      ,	   0x1070103247000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP26_IP2_GPIO"      ,	   0x1070103447000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP27_IP2_GPIO"      ,	   0x1070103647000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP28_IP2_GPIO"      ,	   0x1070103847000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP29_IP2_GPIO"      ,	   0x1070103a47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP30_IP2_GPIO"      ,	   0x1070103c47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP31_IP2_GPIO"      ,	   0x1070103e47000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"CIU2_RAW_PP0_IP2_IO"         ,	   0x1070100044000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP1_IP2_IO"         ,	   0x1070100244000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP2_IP2_IO"         ,	   0x1070100444000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP3_IP2_IO"         ,	   0x1070100644000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP4_IP2_IO"         ,	   0x1070100844000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP5_IP2_IO"         ,	   0x1070100a44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP6_IP2_IO"         ,	   0x1070100c44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP7_IP2_IO"         ,	   0x1070100e44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP8_IP2_IO"         ,	   0x1070101044000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP9_IP2_IO"         ,	   0x1070101244000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP10_IP2_IO"        ,	   0x1070101444000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP11_IP2_IO"        ,	   0x1070101644000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP12_IP2_IO"        ,	   0x1070101844000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP13_IP2_IO"        ,	   0x1070101a44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP14_IP2_IO"        ,	   0x1070101c44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP15_IP2_IO"        ,	   0x1070101e44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP16_IP2_IO"        ,	   0x1070102044000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP17_IP2_IO"        ,	   0x1070102244000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP18_IP2_IO"        ,	   0x1070102444000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP19_IP2_IO"        ,	   0x1070102644000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP20_IP2_IO"        ,	   0x1070102844000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP21_IP2_IO"        ,	   0x1070102a44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP22_IP2_IO"        ,	   0x1070102c44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP23_IP2_IO"        ,	   0x1070102e44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP24_IP2_IO"        ,	   0x1070103044000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP25_IP2_IO"        ,	   0x1070103244000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP26_IP2_IO"        ,	   0x1070103444000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP27_IP2_IO"        ,	   0x1070103644000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP28_IP2_IO"        ,	   0x1070103844000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP29_IP2_IO"        ,	   0x1070103a44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP30_IP2_IO"        ,	   0x1070103c44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP31_IP2_IO"        ,	   0x1070103e44000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"CIU2_RAW_PP0_IP2_MEM"        ,	   0x1070100045000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP1_IP2_MEM"        ,	   0x1070100245000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP2_IP2_MEM"        ,	   0x1070100445000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP3_IP2_MEM"        ,	   0x1070100645000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP4_IP2_MEM"        ,	   0x1070100845000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP5_IP2_MEM"        ,	   0x1070100a45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP6_IP2_MEM"        ,	   0x1070100c45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP7_IP2_MEM"        ,	   0x1070100e45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP8_IP2_MEM"        ,	   0x1070101045000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP9_IP2_MEM"        ,	   0x1070101245000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP10_IP2_MEM"       ,	   0x1070101445000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP11_IP2_MEM"       ,	   0x1070101645000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP12_IP2_MEM"       ,	   0x1070101845000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP13_IP2_MEM"       ,	   0x1070101a45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP14_IP2_MEM"       ,	   0x1070101c45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP15_IP2_MEM"       ,	   0x1070101e45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP16_IP2_MEM"       ,	   0x1070102045000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP17_IP2_MEM"       ,	   0x1070102245000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP18_IP2_MEM"       ,	   0x1070102445000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP19_IP2_MEM"       ,	   0x1070102645000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP20_IP2_MEM"       ,	   0x1070102845000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP21_IP2_MEM"       ,	   0x1070102a45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP22_IP2_MEM"       ,	   0x1070102c45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP23_IP2_MEM"       ,	   0x1070102e45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP24_IP2_MEM"       ,	   0x1070103045000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP25_IP2_MEM"       ,	   0x1070103245000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP26_IP2_MEM"       ,	   0x1070103445000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP27_IP2_MEM"       ,	   0x1070103645000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP28_IP2_MEM"       ,	   0x1070103845000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP29_IP2_MEM"       ,	   0x1070103a45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP30_IP2_MEM"       ,	   0x1070103c45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP31_IP2_MEM"       ,	   0x1070103e45000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"CIU2_RAW_PP0_IP2_MIO"        ,	   0x1070100043000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP1_IP2_MIO"        ,	   0x1070100243000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP2_IP2_MIO"        ,	   0x1070100443000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP3_IP2_MIO"        ,	   0x1070100643000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP4_IP2_MIO"        ,	   0x1070100843000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP5_IP2_MIO"        ,	   0x1070100a43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP6_IP2_MIO"        ,	   0x1070100c43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP7_IP2_MIO"        ,	   0x1070100e43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP8_IP2_MIO"        ,	   0x1070101043000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP9_IP2_MIO"        ,	   0x1070101243000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP10_IP2_MIO"       ,	   0x1070101443000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP11_IP2_MIO"       ,	   0x1070101643000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP12_IP2_MIO"       ,	   0x1070101843000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP13_IP2_MIO"       ,	   0x1070101a43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP14_IP2_MIO"       ,	   0x1070101c43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP15_IP2_MIO"       ,	   0x1070101e43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP16_IP2_MIO"       ,	   0x1070102043000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP17_IP2_MIO"       ,	   0x1070102243000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP18_IP2_MIO"       ,	   0x1070102443000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP19_IP2_MIO"       ,	   0x1070102643000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP20_IP2_MIO"       ,	   0x1070102843000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP21_IP2_MIO"       ,	   0x1070102a43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP22_IP2_MIO"       ,	   0x1070102c43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP23_IP2_MIO"       ,	   0x1070102e43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP24_IP2_MIO"       ,	   0x1070103043000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP25_IP2_MIO"       ,	   0x1070103243000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP26_IP2_MIO"       ,	   0x1070103443000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP27_IP2_MIO"       ,	   0x1070103643000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP28_IP2_MIO"       ,	   0x1070103843000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP29_IP2_MIO"       ,	   0x1070103a43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP30_IP2_MIO"       ,	   0x1070103c43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP31_IP2_MIO"       ,	   0x1070103e43000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"CIU2_RAW_PP0_IP2_PKT"        ,	   0x1070100046000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP1_IP2_PKT"        ,	   0x1070100246000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP2_IP2_PKT"        ,	   0x1070100446000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP3_IP2_PKT"        ,	   0x1070100646000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP4_IP2_PKT"        ,	   0x1070100846000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP5_IP2_PKT"        ,	   0x1070100a46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP6_IP2_PKT"        ,	   0x1070100c46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP7_IP2_PKT"        ,	   0x1070100e46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP8_IP2_PKT"        ,	   0x1070101046000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP9_IP2_PKT"        ,	   0x1070101246000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP10_IP2_PKT"       ,	   0x1070101446000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP11_IP2_PKT"       ,	   0x1070101646000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP12_IP2_PKT"       ,	   0x1070101846000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP13_IP2_PKT"       ,	   0x1070101a46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP14_IP2_PKT"       ,	   0x1070101c46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP15_IP2_PKT"       ,	   0x1070101e46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP16_IP2_PKT"       ,	   0x1070102046000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP17_IP2_PKT"       ,	   0x1070102246000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP18_IP2_PKT"       ,	   0x1070102446000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP19_IP2_PKT"       ,	   0x1070102646000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP20_IP2_PKT"       ,	   0x1070102846000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP21_IP2_PKT"       ,	   0x1070102a46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP22_IP2_PKT"       ,	   0x1070102c46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP23_IP2_PKT"       ,	   0x1070102e46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP24_IP2_PKT"       ,	   0x1070103046000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP25_IP2_PKT"       ,	   0x1070103246000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP26_IP2_PKT"       ,	   0x1070103446000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP27_IP2_PKT"       ,	   0x1070103646000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP28_IP2_PKT"       ,	   0x1070103846000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP29_IP2_PKT"       ,	   0x1070103a46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP30_IP2_PKT"       ,	   0x1070103c46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP31_IP2_PKT"       ,	   0x1070103e46000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"CIU2_RAW_PP0_IP2_RML"        ,	   0x1070100042000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP1_IP2_RML"        ,	   0x1070100242000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP2_IP2_RML"        ,	   0x1070100442000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP3_IP2_RML"        ,	   0x1070100642000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP4_IP2_RML"        ,	   0x1070100842000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP5_IP2_RML"        ,	   0x1070100a42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP6_IP2_RML"        ,	   0x1070100c42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP7_IP2_RML"        ,	   0x1070100e42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP8_IP2_RML"        ,	   0x1070101042000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP9_IP2_RML"        ,	   0x1070101242000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP10_IP2_RML"       ,	   0x1070101442000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP11_IP2_RML"       ,	   0x1070101642000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP12_IP2_RML"       ,	   0x1070101842000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP13_IP2_RML"       ,	   0x1070101a42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP14_IP2_RML"       ,	   0x1070101c42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP15_IP2_RML"       ,	   0x1070101e42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP16_IP2_RML"       ,	   0x1070102042000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP17_IP2_RML"       ,	   0x1070102242000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP18_IP2_RML"       ,	   0x1070102442000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP19_IP2_RML"       ,	   0x1070102642000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP20_IP2_RML"       ,	   0x1070102842000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP21_IP2_RML"       ,	   0x1070102a42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP22_IP2_RML"       ,	   0x1070102c42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP23_IP2_RML"       ,	   0x1070102e42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP24_IP2_RML"       ,	   0x1070103042000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP25_IP2_RML"       ,	   0x1070103242000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP26_IP2_RML"       ,	   0x1070103442000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP27_IP2_RML"       ,	   0x1070103642000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP28_IP2_RML"       ,	   0x1070103842000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP29_IP2_RML"       ,	   0x1070103a42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP30_IP2_RML"       ,	   0x1070103c42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP31_IP2_RML"       ,	   0x1070103e42000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"CIU2_RAW_PP0_IP2_WDOG"       ,	   0x1070100041000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP1_IP2_WDOG"       ,	   0x1070100241000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP2_IP2_WDOG"       ,	   0x1070100441000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP3_IP2_WDOG"       ,	   0x1070100641000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP4_IP2_WDOG"       ,	   0x1070100841000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP5_IP2_WDOG"       ,	   0x1070100a41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP6_IP2_WDOG"       ,	   0x1070100c41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP7_IP2_WDOG"       ,	   0x1070100e41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP8_IP2_WDOG"       ,	   0x1070101041000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP9_IP2_WDOG"       ,	   0x1070101241000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP10_IP2_WDOG"      ,	   0x1070101441000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP11_IP2_WDOG"      ,	   0x1070101641000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP12_IP2_WDOG"      ,	   0x1070101841000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP13_IP2_WDOG"      ,	   0x1070101a41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP14_IP2_WDOG"      ,	   0x1070101c41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP15_IP2_WDOG"      ,	   0x1070101e41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP16_IP2_WDOG"      ,	   0x1070102041000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP17_IP2_WDOG"      ,	   0x1070102241000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP18_IP2_WDOG"      ,	   0x1070102441000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP19_IP2_WDOG"      ,	   0x1070102641000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP20_IP2_WDOG"      ,	   0x1070102841000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP21_IP2_WDOG"      ,	   0x1070102a41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP22_IP2_WDOG"      ,	   0x1070102c41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP23_IP2_WDOG"      ,	   0x1070102e41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP24_IP2_WDOG"      ,	   0x1070103041000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP25_IP2_WDOG"      ,	   0x1070103241000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP26_IP2_WDOG"      ,	   0x1070103441000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP27_IP2_WDOG"      ,	   0x1070103641000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP28_IP2_WDOG"      ,	   0x1070103841000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP29_IP2_WDOG"      ,	   0x1070103a41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP30_IP2_WDOG"      ,	   0x1070103c41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP31_IP2_WDOG"      ,	   0x1070103e41000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"CIU2_RAW_PP0_IP2_WRKQ"       ,	   0x1070100040000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP1_IP2_WRKQ"       ,	   0x1070100240000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP2_IP2_WRKQ"       ,	   0x1070100440000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP3_IP2_WRKQ"       ,	   0x1070100640000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP4_IP2_WRKQ"       ,	   0x1070100840000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP5_IP2_WRKQ"       ,	   0x1070100a40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP6_IP2_WRKQ"       ,	   0x1070100c40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP7_IP2_WRKQ"       ,	   0x1070100e40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP8_IP2_WRKQ"       ,	   0x1070101040000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP9_IP2_WRKQ"       ,	   0x1070101240000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP10_IP2_WRKQ"      ,	   0x1070101440000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP11_IP2_WRKQ"      ,	   0x1070101640000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP12_IP2_WRKQ"      ,	   0x1070101840000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP13_IP2_WRKQ"      ,	   0x1070101a40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP14_IP2_WRKQ"      ,	   0x1070101c40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP15_IP2_WRKQ"      ,	   0x1070101e40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP16_IP2_WRKQ"      ,	   0x1070102040000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP17_IP2_WRKQ"      ,	   0x1070102240000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP18_IP2_WRKQ"      ,	   0x1070102440000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP19_IP2_WRKQ"      ,	   0x1070102640000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP20_IP2_WRKQ"      ,	   0x1070102840000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP21_IP2_WRKQ"      ,	   0x1070102a40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP22_IP2_WRKQ"      ,	   0x1070102c40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP23_IP2_WRKQ"      ,	   0x1070102e40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP24_IP2_WRKQ"      ,	   0x1070103040000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP25_IP2_WRKQ"      ,	   0x1070103240000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP26_IP2_WRKQ"      ,	   0x1070103440000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP27_IP2_WRKQ"      ,	   0x1070103640000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP28_IP2_WRKQ"      ,	   0x1070103840000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP29_IP2_WRKQ"      ,	   0x1070103a40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP30_IP2_WRKQ"      ,	   0x1070103c40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP31_IP2_WRKQ"      ,	   0x1070103e40000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"CIU2_RAW_PP0_IP3_GPIO"       ,	   0x1070100047200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP1_IP3_GPIO"       ,	   0x1070100247200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP2_IP3_GPIO"       ,	   0x1070100447200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP3_IP3_GPIO"       ,	   0x1070100647200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP4_IP3_GPIO"       ,	   0x1070100847200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP5_IP3_GPIO"       ,	   0x1070100a47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP6_IP3_GPIO"       ,	   0x1070100c47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP7_IP3_GPIO"       ,	   0x1070100e47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP8_IP3_GPIO"       ,	   0x1070101047200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP9_IP3_GPIO"       ,	   0x1070101247200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP10_IP3_GPIO"      ,	   0x1070101447200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP11_IP3_GPIO"      ,	   0x1070101647200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP12_IP3_GPIO"      ,	   0x1070101847200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP13_IP3_GPIO"      ,	   0x1070101a47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP14_IP3_GPIO"      ,	   0x1070101c47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP15_IP3_GPIO"      ,	   0x1070101e47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP16_IP3_GPIO"      ,	   0x1070102047200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP17_IP3_GPIO"      ,	   0x1070102247200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP18_IP3_GPIO"      ,	   0x1070102447200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP19_IP3_GPIO"      ,	   0x1070102647200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP20_IP3_GPIO"      ,	   0x1070102847200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP21_IP3_GPIO"      ,	   0x1070102a47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP22_IP3_GPIO"      ,	   0x1070102c47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP23_IP3_GPIO"      ,	   0x1070102e47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP24_IP3_GPIO"      ,	   0x1070103047200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP25_IP3_GPIO"      ,	   0x1070103247200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP26_IP3_GPIO"      ,	   0x1070103447200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP27_IP3_GPIO"      ,	   0x1070103647200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP28_IP3_GPIO"      ,	   0x1070103847200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP29_IP3_GPIO"      ,	   0x1070103a47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP30_IP3_GPIO"      ,	   0x1070103c47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP31_IP3_GPIO"      ,	   0x1070103e47200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"CIU2_RAW_PP0_IP3_IO"         ,	   0x1070100044200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP1_IP3_IO"         ,	   0x1070100244200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP2_IP3_IO"         ,	   0x1070100444200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP3_IP3_IO"         ,	   0x1070100644200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP4_IP3_IO"         ,	   0x1070100844200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP5_IP3_IO"         ,	   0x1070100a44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP6_IP3_IO"         ,	   0x1070100c44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP7_IP3_IO"         ,	   0x1070100e44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP8_IP3_IO"         ,	   0x1070101044200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP9_IP3_IO"         ,	   0x1070101244200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP10_IP3_IO"        ,	   0x1070101444200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP11_IP3_IO"        ,	   0x1070101644200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP12_IP3_IO"        ,	   0x1070101844200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP13_IP3_IO"        ,	   0x1070101a44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP14_IP3_IO"        ,	   0x1070101c44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP15_IP3_IO"        ,	   0x1070101e44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP16_IP3_IO"        ,	   0x1070102044200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP17_IP3_IO"        ,	   0x1070102244200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP18_IP3_IO"        ,	   0x1070102444200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP19_IP3_IO"        ,	   0x1070102644200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP20_IP3_IO"        ,	   0x1070102844200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP21_IP3_IO"        ,	   0x1070102a44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP22_IP3_IO"        ,	   0x1070102c44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP23_IP3_IO"        ,	   0x1070102e44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP24_IP3_IO"        ,	   0x1070103044200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP25_IP3_IO"        ,	   0x1070103244200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP26_IP3_IO"        ,	   0x1070103444200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP27_IP3_IO"        ,	   0x1070103644200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP28_IP3_IO"        ,	   0x1070103844200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP29_IP3_IO"        ,	   0x1070103a44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP30_IP3_IO"        ,	   0x1070103c44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP31_IP3_IO"        ,	   0x1070103e44200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"CIU2_RAW_PP0_IP3_MEM"        ,	   0x1070100045200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP1_IP3_MEM"        ,	   0x1070100245200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP2_IP3_MEM"        ,	   0x1070100445200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP3_IP3_MEM"        ,	   0x1070100645200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP4_IP3_MEM"        ,	   0x1070100845200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP5_IP3_MEM"        ,	   0x1070100a45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP6_IP3_MEM"        ,	   0x1070100c45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP7_IP3_MEM"        ,	   0x1070100e45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP8_IP3_MEM"        ,	   0x1070101045200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP9_IP3_MEM"        ,	   0x1070101245200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP10_IP3_MEM"       ,	   0x1070101445200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP11_IP3_MEM"       ,	   0x1070101645200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP12_IP3_MEM"       ,	   0x1070101845200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP13_IP3_MEM"       ,	   0x1070101a45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP14_IP3_MEM"       ,	   0x1070101c45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP15_IP3_MEM"       ,	   0x1070101e45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP16_IP3_MEM"       ,	   0x1070102045200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP17_IP3_MEM"       ,	   0x1070102245200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP18_IP3_MEM"       ,	   0x1070102445200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP19_IP3_MEM"       ,	   0x1070102645200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP20_IP3_MEM"       ,	   0x1070102845200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP21_IP3_MEM"       ,	   0x1070102a45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP22_IP3_MEM"       ,	   0x1070102c45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP23_IP3_MEM"       ,	   0x1070102e45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP24_IP3_MEM"       ,	   0x1070103045200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP25_IP3_MEM"       ,	   0x1070103245200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP26_IP3_MEM"       ,	   0x1070103445200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP27_IP3_MEM"       ,	   0x1070103645200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP28_IP3_MEM"       ,	   0x1070103845200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP29_IP3_MEM"       ,	   0x1070103a45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP30_IP3_MEM"       ,	   0x1070103c45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP31_IP3_MEM"       ,	   0x1070103e45200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"CIU2_RAW_PP0_IP3_MIO"        ,	   0x1070100043200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP1_IP3_MIO"        ,	   0x1070100243200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP2_IP3_MIO"        ,	   0x1070100443200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP3_IP3_MIO"        ,	   0x1070100643200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP4_IP3_MIO"        ,	   0x1070100843200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP5_IP3_MIO"        ,	   0x1070100a43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP6_IP3_MIO"        ,	   0x1070100c43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP7_IP3_MIO"        ,	   0x1070100e43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP8_IP3_MIO"        ,	   0x1070101043200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP9_IP3_MIO"        ,	   0x1070101243200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP10_IP3_MIO"       ,	   0x1070101443200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP11_IP3_MIO"       ,	   0x1070101643200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP12_IP3_MIO"       ,	   0x1070101843200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP13_IP3_MIO"       ,	   0x1070101a43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP14_IP3_MIO"       ,	   0x1070101c43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP15_IP3_MIO"       ,	   0x1070101e43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP16_IP3_MIO"       ,	   0x1070102043200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP17_IP3_MIO"       ,	   0x1070102243200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP18_IP3_MIO"       ,	   0x1070102443200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP19_IP3_MIO"       ,	   0x1070102643200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP20_IP3_MIO"       ,	   0x1070102843200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP21_IP3_MIO"       ,	   0x1070102a43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP22_IP3_MIO"       ,	   0x1070102c43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP23_IP3_MIO"       ,	   0x1070102e43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP24_IP3_MIO"       ,	   0x1070103043200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP25_IP3_MIO"       ,	   0x1070103243200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP26_IP3_MIO"       ,	   0x1070103443200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP27_IP3_MIO"       ,	   0x1070103643200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP28_IP3_MIO"       ,	   0x1070103843200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP29_IP3_MIO"       ,	   0x1070103a43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP30_IP3_MIO"       ,	   0x1070103c43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP31_IP3_MIO"       ,	   0x1070103e43200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"CIU2_RAW_PP0_IP3_PKT"        ,	   0x1070100046200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP1_IP3_PKT"        ,	   0x1070100246200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP2_IP3_PKT"        ,	   0x1070100446200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP3_IP3_PKT"        ,	   0x1070100646200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP4_IP3_PKT"        ,	   0x1070100846200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP5_IP3_PKT"        ,	   0x1070100a46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP6_IP3_PKT"        ,	   0x1070100c46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP7_IP3_PKT"        ,	   0x1070100e46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP8_IP3_PKT"        ,	   0x1070101046200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP9_IP3_PKT"        ,	   0x1070101246200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP10_IP3_PKT"       ,	   0x1070101446200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP11_IP3_PKT"       ,	   0x1070101646200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP12_IP3_PKT"       ,	   0x1070101846200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP13_IP3_PKT"       ,	   0x1070101a46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP14_IP3_PKT"       ,	   0x1070101c46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP15_IP3_PKT"       ,	   0x1070101e46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP16_IP3_PKT"       ,	   0x1070102046200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP17_IP3_PKT"       ,	   0x1070102246200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP18_IP3_PKT"       ,	   0x1070102446200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP19_IP3_PKT"       ,	   0x1070102646200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP20_IP3_PKT"       ,	   0x1070102846200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP21_IP3_PKT"       ,	   0x1070102a46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP22_IP3_PKT"       ,	   0x1070102c46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP23_IP3_PKT"       ,	   0x1070102e46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP24_IP3_PKT"       ,	   0x1070103046200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP25_IP3_PKT"       ,	   0x1070103246200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP26_IP3_PKT"       ,	   0x1070103446200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP27_IP3_PKT"       ,	   0x1070103646200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP28_IP3_PKT"       ,	   0x1070103846200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP29_IP3_PKT"       ,	   0x1070103a46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP30_IP3_PKT"       ,	   0x1070103c46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP31_IP3_PKT"       ,	   0x1070103e46200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"CIU2_RAW_PP0_IP3_RML"        ,	   0x1070100042200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP1_IP3_RML"        ,	   0x1070100242200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP2_IP3_RML"        ,	   0x1070100442200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP3_IP3_RML"        ,	   0x1070100642200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP4_IP3_RML"        ,	   0x1070100842200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP5_IP3_RML"        ,	   0x1070100a42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP6_IP3_RML"        ,	   0x1070100c42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP7_IP3_RML"        ,	   0x1070100e42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP8_IP3_RML"        ,	   0x1070101042200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP9_IP3_RML"        ,	   0x1070101242200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP10_IP3_RML"       ,	   0x1070101442200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP11_IP3_RML"       ,	   0x1070101642200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP12_IP3_RML"       ,	   0x1070101842200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP13_IP3_RML"       ,	   0x1070101a42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP14_IP3_RML"       ,	   0x1070101c42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP15_IP3_RML"       ,	   0x1070101e42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP16_IP3_RML"       ,	   0x1070102042200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP17_IP3_RML"       ,	   0x1070102242200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP18_IP3_RML"       ,	   0x1070102442200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP19_IP3_RML"       ,	   0x1070102642200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP20_IP3_RML"       ,	   0x1070102842200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP21_IP3_RML"       ,	   0x1070102a42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP22_IP3_RML"       ,	   0x1070102c42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP23_IP3_RML"       ,	   0x1070102e42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP24_IP3_RML"       ,	   0x1070103042200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP25_IP3_RML"       ,	   0x1070103242200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP26_IP3_RML"       ,	   0x1070103442200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP27_IP3_RML"       ,	   0x1070103642200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP28_IP3_RML"       ,	   0x1070103842200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP29_IP3_RML"       ,	   0x1070103a42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP30_IP3_RML"       ,	   0x1070103c42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP31_IP3_RML"       ,	   0x1070103e42200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"CIU2_RAW_PP0_IP3_WDOG"       ,	   0x1070100041200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP1_IP3_WDOG"       ,	   0x1070100241200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP2_IP3_WDOG"       ,	   0x1070100441200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP3_IP3_WDOG"       ,	   0x1070100641200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP4_IP3_WDOG"       ,	   0x1070100841200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP5_IP3_WDOG"       ,	   0x1070100a41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP6_IP3_WDOG"       ,	   0x1070100c41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP7_IP3_WDOG"       ,	   0x1070100e41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP8_IP3_WDOG"       ,	   0x1070101041200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP9_IP3_WDOG"       ,	   0x1070101241200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP10_IP3_WDOG"      ,	   0x1070101441200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP11_IP3_WDOG"      ,	   0x1070101641200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP12_IP3_WDOG"      ,	   0x1070101841200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP13_IP3_WDOG"      ,	   0x1070101a41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP14_IP3_WDOG"      ,	   0x1070101c41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP15_IP3_WDOG"      ,	   0x1070101e41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP16_IP3_WDOG"      ,	   0x1070102041200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP17_IP3_WDOG"      ,	   0x1070102241200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP18_IP3_WDOG"      ,	   0x1070102441200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP19_IP3_WDOG"      ,	   0x1070102641200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP20_IP3_WDOG"      ,	   0x1070102841200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP21_IP3_WDOG"      ,	   0x1070102a41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP22_IP3_WDOG"      ,	   0x1070102c41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP23_IP3_WDOG"      ,	   0x1070102e41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP24_IP3_WDOG"      ,	   0x1070103041200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP25_IP3_WDOG"      ,	   0x1070103241200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP26_IP3_WDOG"      ,	   0x1070103441200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP27_IP3_WDOG"      ,	   0x1070103641200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP28_IP3_WDOG"      ,	   0x1070103841200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP29_IP3_WDOG"      ,	   0x1070103a41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP30_IP3_WDOG"      ,	   0x1070103c41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP31_IP3_WDOG"      ,	   0x1070103e41200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"CIU2_RAW_PP0_IP3_WRKQ"       ,	   0x1070100040200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP1_IP3_WRKQ"       ,	   0x1070100240200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP2_IP3_WRKQ"       ,	   0x1070100440200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP3_IP3_WRKQ"       ,	   0x1070100640200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP4_IP3_WRKQ"       ,	   0x1070100840200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP5_IP3_WRKQ"       ,	   0x1070100a40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP6_IP3_WRKQ"       ,	   0x1070100c40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP7_IP3_WRKQ"       ,	   0x1070100e40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP8_IP3_WRKQ"       ,	   0x1070101040200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP9_IP3_WRKQ"       ,	   0x1070101240200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP10_IP3_WRKQ"      ,	   0x1070101440200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP11_IP3_WRKQ"      ,	   0x1070101640200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP12_IP3_WRKQ"      ,	   0x1070101840200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP13_IP3_WRKQ"      ,	   0x1070101a40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP14_IP3_WRKQ"      ,	   0x1070101c40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP15_IP3_WRKQ"      ,	   0x1070101e40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP16_IP3_WRKQ"      ,	   0x1070102040200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP17_IP3_WRKQ"      ,	   0x1070102240200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP18_IP3_WRKQ"      ,	   0x1070102440200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP19_IP3_WRKQ"      ,	   0x1070102640200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP20_IP3_WRKQ"      ,	   0x1070102840200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP21_IP3_WRKQ"      ,	   0x1070102a40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP22_IP3_WRKQ"      ,	   0x1070102c40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP23_IP3_WRKQ"      ,	   0x1070102e40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP24_IP3_WRKQ"      ,	   0x1070103040200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP25_IP3_WRKQ"      ,	   0x1070103240200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP26_IP3_WRKQ"      ,	   0x1070103440200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP27_IP3_WRKQ"      ,	   0x1070103640200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP28_IP3_WRKQ"      ,	   0x1070103840200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP29_IP3_WRKQ"      ,	   0x1070103a40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP30_IP3_WRKQ"      ,	   0x1070103c40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP31_IP3_WRKQ"      ,	   0x1070103e40200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"CIU2_RAW_PP0_IP4_GPIO"       ,	   0x1070100047400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP1_IP4_GPIO"       ,	   0x1070100247400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP2_IP4_GPIO"       ,	   0x1070100447400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP3_IP4_GPIO"       ,	   0x1070100647400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP4_IP4_GPIO"       ,	   0x1070100847400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP5_IP4_GPIO"       ,	   0x1070100a47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP6_IP4_GPIO"       ,	   0x1070100c47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP7_IP4_GPIO"       ,	   0x1070100e47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP8_IP4_GPIO"       ,	   0x1070101047400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP9_IP4_GPIO"       ,	   0x1070101247400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP10_IP4_GPIO"      ,	   0x1070101447400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP11_IP4_GPIO"      ,	   0x1070101647400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP12_IP4_GPIO"      ,	   0x1070101847400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP13_IP4_GPIO"      ,	   0x1070101a47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP14_IP4_GPIO"      ,	   0x1070101c47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP15_IP4_GPIO"      ,	   0x1070101e47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP16_IP4_GPIO"      ,	   0x1070102047400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP17_IP4_GPIO"      ,	   0x1070102247400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP18_IP4_GPIO"      ,	   0x1070102447400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP19_IP4_GPIO"      ,	   0x1070102647400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP20_IP4_GPIO"      ,	   0x1070102847400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP21_IP4_GPIO"      ,	   0x1070102a47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP22_IP4_GPIO"      ,	   0x1070102c47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP23_IP4_GPIO"      ,	   0x1070102e47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP24_IP4_GPIO"      ,	   0x1070103047400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP25_IP4_GPIO"      ,	   0x1070103247400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP26_IP4_GPIO"      ,	   0x1070103447400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP27_IP4_GPIO"      ,	   0x1070103647400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP28_IP4_GPIO"      ,	   0x1070103847400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP29_IP4_GPIO"      ,	   0x1070103a47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP30_IP4_GPIO"      ,	   0x1070103c47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP31_IP4_GPIO"      ,	   0x1070103e47400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"CIU2_RAW_PP0_IP4_IO"         ,	   0x1070100044400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP1_IP4_IO"         ,	   0x1070100244400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP2_IP4_IO"         ,	   0x1070100444400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP3_IP4_IO"         ,	   0x1070100644400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP4_IP4_IO"         ,	   0x1070100844400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP5_IP4_IO"         ,	   0x1070100a44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP6_IP4_IO"         ,	   0x1070100c44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP7_IP4_IO"         ,	   0x1070100e44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP8_IP4_IO"         ,	   0x1070101044400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP9_IP4_IO"         ,	   0x1070101244400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP10_IP4_IO"        ,	   0x1070101444400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP11_IP4_IO"        ,	   0x1070101644400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP12_IP4_IO"        ,	   0x1070101844400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP13_IP4_IO"        ,	   0x1070101a44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP14_IP4_IO"        ,	   0x1070101c44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP15_IP4_IO"        ,	   0x1070101e44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP16_IP4_IO"        ,	   0x1070102044400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP17_IP4_IO"        ,	   0x1070102244400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP18_IP4_IO"        ,	   0x1070102444400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP19_IP4_IO"        ,	   0x1070102644400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP20_IP4_IO"        ,	   0x1070102844400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP21_IP4_IO"        ,	   0x1070102a44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP22_IP4_IO"        ,	   0x1070102c44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP23_IP4_IO"        ,	   0x1070102e44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP24_IP4_IO"        ,	   0x1070103044400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP25_IP4_IO"        ,	   0x1070103244400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP26_IP4_IO"        ,	   0x1070103444400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP27_IP4_IO"        ,	   0x1070103644400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP28_IP4_IO"        ,	   0x1070103844400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP29_IP4_IO"        ,	   0x1070103a44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP30_IP4_IO"        ,	   0x1070103c44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP31_IP4_IO"        ,	   0x1070103e44400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"CIU2_RAW_PP0_IP4_MEM"        ,	   0x1070100045400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP1_IP4_MEM"        ,	   0x1070100245400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP2_IP4_MEM"        ,	   0x1070100445400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP3_IP4_MEM"        ,	   0x1070100645400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP4_IP4_MEM"        ,	   0x1070100845400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP5_IP4_MEM"        ,	   0x1070100a45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP6_IP4_MEM"        ,	   0x1070100c45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP7_IP4_MEM"        ,	   0x1070100e45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP8_IP4_MEM"        ,	   0x1070101045400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP9_IP4_MEM"        ,	   0x1070101245400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP10_IP4_MEM"       ,	   0x1070101445400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP11_IP4_MEM"       ,	   0x1070101645400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP12_IP4_MEM"       ,	   0x1070101845400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP13_IP4_MEM"       ,	   0x1070101a45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP14_IP4_MEM"       ,	   0x1070101c45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP15_IP4_MEM"       ,	   0x1070101e45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP16_IP4_MEM"       ,	   0x1070102045400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP17_IP4_MEM"       ,	   0x1070102245400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP18_IP4_MEM"       ,	   0x1070102445400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP19_IP4_MEM"       ,	   0x1070102645400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP20_IP4_MEM"       ,	   0x1070102845400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP21_IP4_MEM"       ,	   0x1070102a45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP22_IP4_MEM"       ,	   0x1070102c45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP23_IP4_MEM"       ,	   0x1070102e45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP24_IP4_MEM"       ,	   0x1070103045400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP25_IP4_MEM"       ,	   0x1070103245400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP26_IP4_MEM"       ,	   0x1070103445400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP27_IP4_MEM"       ,	   0x1070103645400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP28_IP4_MEM"       ,	   0x1070103845400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP29_IP4_MEM"       ,	   0x1070103a45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP30_IP4_MEM"       ,	   0x1070103c45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP31_IP4_MEM"       ,	   0x1070103e45400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"CIU2_RAW_PP0_IP4_MIO"        ,	   0x1070100043400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP1_IP4_MIO"        ,	   0x1070100243400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP2_IP4_MIO"        ,	   0x1070100443400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP3_IP4_MIO"        ,	   0x1070100643400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP4_IP4_MIO"        ,	   0x1070100843400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP5_IP4_MIO"        ,	   0x1070100a43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP6_IP4_MIO"        ,	   0x1070100c43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP7_IP4_MIO"        ,	   0x1070100e43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP8_IP4_MIO"        ,	   0x1070101043400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP9_IP4_MIO"        ,	   0x1070101243400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP10_IP4_MIO"       ,	   0x1070101443400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP11_IP4_MIO"       ,	   0x1070101643400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP12_IP4_MIO"       ,	   0x1070101843400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP13_IP4_MIO"       ,	   0x1070101a43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP14_IP4_MIO"       ,	   0x1070101c43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP15_IP4_MIO"       ,	   0x1070101e43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP16_IP4_MIO"       ,	   0x1070102043400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP17_IP4_MIO"       ,	   0x1070102243400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP18_IP4_MIO"       ,	   0x1070102443400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP19_IP4_MIO"       ,	   0x1070102643400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP20_IP4_MIO"       ,	   0x1070102843400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP21_IP4_MIO"       ,	   0x1070102a43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP22_IP4_MIO"       ,	   0x1070102c43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP23_IP4_MIO"       ,	   0x1070102e43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP24_IP4_MIO"       ,	   0x1070103043400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP25_IP4_MIO"       ,	   0x1070103243400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP26_IP4_MIO"       ,	   0x1070103443400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP27_IP4_MIO"       ,	   0x1070103643400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP28_IP4_MIO"       ,	   0x1070103843400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP29_IP4_MIO"       ,	   0x1070103a43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP30_IP4_MIO"       ,	   0x1070103c43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP31_IP4_MIO"       ,	   0x1070103e43400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"CIU2_RAW_PP0_IP4_PKT"        ,	   0x1070100046400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP1_IP4_PKT"        ,	   0x1070100246400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP2_IP4_PKT"        ,	   0x1070100446400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP3_IP4_PKT"        ,	   0x1070100646400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP4_IP4_PKT"        ,	   0x1070100846400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP5_IP4_PKT"        ,	   0x1070100a46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP6_IP4_PKT"        ,	   0x1070100c46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP7_IP4_PKT"        ,	   0x1070100e46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP8_IP4_PKT"        ,	   0x1070101046400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP9_IP4_PKT"        ,	   0x1070101246400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP10_IP4_PKT"       ,	   0x1070101446400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP11_IP4_PKT"       ,	   0x1070101646400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP12_IP4_PKT"       ,	   0x1070101846400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP13_IP4_PKT"       ,	   0x1070101a46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP14_IP4_PKT"       ,	   0x1070101c46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP15_IP4_PKT"       ,	   0x1070101e46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP16_IP4_PKT"       ,	   0x1070102046400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP17_IP4_PKT"       ,	   0x1070102246400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP18_IP4_PKT"       ,	   0x1070102446400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP19_IP4_PKT"       ,	   0x1070102646400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP20_IP4_PKT"       ,	   0x1070102846400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP21_IP4_PKT"       ,	   0x1070102a46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP22_IP4_PKT"       ,	   0x1070102c46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP23_IP4_PKT"       ,	   0x1070102e46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP24_IP4_PKT"       ,	   0x1070103046400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP25_IP4_PKT"       ,	   0x1070103246400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP26_IP4_PKT"       ,	   0x1070103446400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP27_IP4_PKT"       ,	   0x1070103646400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP28_IP4_PKT"       ,	   0x1070103846400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP29_IP4_PKT"       ,	   0x1070103a46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP30_IP4_PKT"       ,	   0x1070103c46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP31_IP4_PKT"       ,	   0x1070103e46400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"CIU2_RAW_PP0_IP4_RML"        ,	   0x1070100042400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP1_IP4_RML"        ,	   0x1070100242400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP2_IP4_RML"        ,	   0x1070100442400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP3_IP4_RML"        ,	   0x1070100642400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP4_IP4_RML"        ,	   0x1070100842400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP5_IP4_RML"        ,	   0x1070100a42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP6_IP4_RML"        ,	   0x1070100c42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP7_IP4_RML"        ,	   0x1070100e42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP8_IP4_RML"        ,	   0x1070101042400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP9_IP4_RML"        ,	   0x1070101242400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP10_IP4_RML"       ,	   0x1070101442400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP11_IP4_RML"       ,	   0x1070101642400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP12_IP4_RML"       ,	   0x1070101842400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP13_IP4_RML"       ,	   0x1070101a42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP14_IP4_RML"       ,	   0x1070101c42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP15_IP4_RML"       ,	   0x1070101e42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP16_IP4_RML"       ,	   0x1070102042400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP17_IP4_RML"       ,	   0x1070102242400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP18_IP4_RML"       ,	   0x1070102442400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP19_IP4_RML"       ,	   0x1070102642400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP20_IP4_RML"       ,	   0x1070102842400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP21_IP4_RML"       ,	   0x1070102a42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP22_IP4_RML"       ,	   0x1070102c42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP23_IP4_RML"       ,	   0x1070102e42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP24_IP4_RML"       ,	   0x1070103042400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP25_IP4_RML"       ,	   0x1070103242400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP26_IP4_RML"       ,	   0x1070103442400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP27_IP4_RML"       ,	   0x1070103642400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP28_IP4_RML"       ,	   0x1070103842400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP29_IP4_RML"       ,	   0x1070103a42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP30_IP4_RML"       ,	   0x1070103c42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP31_IP4_RML"       ,	   0x1070103e42400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"CIU2_RAW_PP0_IP4_WDOG"       ,	   0x1070100041400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP1_IP4_WDOG"       ,	   0x1070100241400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP2_IP4_WDOG"       ,	   0x1070100441400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP3_IP4_WDOG"       ,	   0x1070100641400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP4_IP4_WDOG"       ,	   0x1070100841400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP5_IP4_WDOG"       ,	   0x1070100a41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP6_IP4_WDOG"       ,	   0x1070100c41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP7_IP4_WDOG"       ,	   0x1070100e41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP8_IP4_WDOG"       ,	   0x1070101041400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP9_IP4_WDOG"       ,	   0x1070101241400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP10_IP4_WDOG"      ,	   0x1070101441400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP11_IP4_WDOG"      ,	   0x1070101641400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP12_IP4_WDOG"      ,	   0x1070101841400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP13_IP4_WDOG"      ,	   0x1070101a41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP14_IP4_WDOG"      ,	   0x1070101c41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP15_IP4_WDOG"      ,	   0x1070101e41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP16_IP4_WDOG"      ,	   0x1070102041400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP17_IP4_WDOG"      ,	   0x1070102241400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP18_IP4_WDOG"      ,	   0x1070102441400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP19_IP4_WDOG"      ,	   0x1070102641400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP20_IP4_WDOG"      ,	   0x1070102841400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP21_IP4_WDOG"      ,	   0x1070102a41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP22_IP4_WDOG"      ,	   0x1070102c41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP23_IP4_WDOG"      ,	   0x1070102e41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP24_IP4_WDOG"      ,	   0x1070103041400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP25_IP4_WDOG"      ,	   0x1070103241400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP26_IP4_WDOG"      ,	   0x1070103441400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP27_IP4_WDOG"      ,	   0x1070103641400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP28_IP4_WDOG"      ,	   0x1070103841400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP29_IP4_WDOG"      ,	   0x1070103a41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP30_IP4_WDOG"      ,	   0x1070103c41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP31_IP4_WDOG"      ,	   0x1070103e41400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"CIU2_RAW_PP0_IP4_WRKQ"       ,	   0x1070100040400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP1_IP4_WRKQ"       ,	   0x1070100240400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP2_IP4_WRKQ"       ,	   0x1070100440400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP3_IP4_WRKQ"       ,	   0x1070100640400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP4_IP4_WRKQ"       ,	   0x1070100840400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP5_IP4_WRKQ"       ,	   0x1070100a40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP6_IP4_WRKQ"       ,	   0x1070100c40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP7_IP4_WRKQ"       ,	   0x1070100e40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP8_IP4_WRKQ"       ,	   0x1070101040400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP9_IP4_WRKQ"       ,	   0x1070101240400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP10_IP4_WRKQ"      ,	   0x1070101440400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP11_IP4_WRKQ"      ,	   0x1070101640400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP12_IP4_WRKQ"      ,	   0x1070101840400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP13_IP4_WRKQ"      ,	   0x1070101a40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP14_IP4_WRKQ"      ,	   0x1070101c40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP15_IP4_WRKQ"      ,	   0x1070101e40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP16_IP4_WRKQ"      ,	   0x1070102040400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP17_IP4_WRKQ"      ,	   0x1070102240400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP18_IP4_WRKQ"      ,	   0x1070102440400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP19_IP4_WRKQ"      ,	   0x1070102640400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP20_IP4_WRKQ"      ,	   0x1070102840400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP21_IP4_WRKQ"      ,	   0x1070102a40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP22_IP4_WRKQ"      ,	   0x1070102c40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP23_IP4_WRKQ"      ,	   0x1070102e40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP24_IP4_WRKQ"      ,	   0x1070103040400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP25_IP4_WRKQ"      ,	   0x1070103240400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP26_IP4_WRKQ"      ,	   0x1070103440400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP27_IP4_WRKQ"      ,	   0x1070103640400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP28_IP4_WRKQ"      ,	   0x1070103840400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP29_IP4_WRKQ"      ,	   0x1070103a40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP30_IP4_WRKQ"      ,	   0x1070103c40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_RAW_PP31_IP4_WRKQ"      ,	   0x1070103e40400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"CIU2_SRC_IO0_INT_GPIO"       ,	   0x1070108087800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	225},
+	{"CIU2_SRC_IO1_INT_GPIO"       ,	   0x1070108287800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	225},
+	{"CIU2_SRC_IO0_INT_IO"         ,	   0x1070108084800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	226},
+	{"CIU2_SRC_IO1_INT_IO"         ,	   0x1070108284800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	226},
+	{"CIU2_SRC_IO0_INT_MBOX"       ,	   0x1070108088800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	227},
+	{"CIU2_SRC_IO1_INT_MBOX"       ,	   0x1070108288800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	227},
+	{"CIU2_SRC_IO0_INT_MEM"        ,	   0x1070108085800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	228},
+	{"CIU2_SRC_IO1_INT_MEM"        ,	   0x1070108285800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	228},
+	{"CIU2_SRC_IO0_INT_MIO"        ,	   0x1070108083800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	229},
+	{"CIU2_SRC_IO1_INT_MIO"        ,	   0x1070108283800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	229},
+	{"CIU2_SRC_IO0_INT_PKT"        ,	   0x1070108086800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	230},
+	{"CIU2_SRC_IO1_INT_PKT"        ,	   0x1070108286800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	230},
+	{"CIU2_SRC_IO0_INT_RML"        ,	   0x1070108082800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"CIU2_SRC_IO1_INT_RML"        ,	   0x1070108282800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"CIU2_SRC_IO0_INT_WDOG"       ,	   0x1070108081800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"CIU2_SRC_IO1_INT_WDOG"       ,	   0x1070108281800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"CIU2_SRC_IO0_INT_WRKQ"       ,	   0x1070108080800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"CIU2_SRC_IO1_INT_WRKQ"       ,	   0x1070108280800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"CIU2_SRC_PP0_IP2_GPIO"       ,	   0x1070100087000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP1_IP2_GPIO"       ,	   0x1070100287000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP2_IP2_GPIO"       ,	   0x1070100487000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP3_IP2_GPIO"       ,	   0x1070100687000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP4_IP2_GPIO"       ,	   0x1070100887000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP5_IP2_GPIO"       ,	   0x1070100a87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP6_IP2_GPIO"       ,	   0x1070100c87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP7_IP2_GPIO"       ,	   0x1070100e87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP8_IP2_GPIO"       ,	   0x1070101087000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP9_IP2_GPIO"       ,	   0x1070101287000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP10_IP2_GPIO"      ,	   0x1070101487000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP11_IP2_GPIO"      ,	   0x1070101687000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP12_IP2_GPIO"      ,	   0x1070101887000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP13_IP2_GPIO"      ,	   0x1070101a87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP14_IP2_GPIO"      ,	   0x1070101c87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP15_IP2_GPIO"      ,	   0x1070101e87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP16_IP2_GPIO"      ,	   0x1070102087000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP17_IP2_GPIO"      ,	   0x1070102287000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP18_IP2_GPIO"      ,	   0x1070102487000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP19_IP2_GPIO"      ,	   0x1070102687000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP20_IP2_GPIO"      ,	   0x1070102887000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP21_IP2_GPIO"      ,	   0x1070102a87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP22_IP2_GPIO"      ,	   0x1070102c87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP23_IP2_GPIO"      ,	   0x1070102e87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP24_IP2_GPIO"      ,	   0x1070103087000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP25_IP2_GPIO"      ,	   0x1070103287000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP26_IP2_GPIO"      ,	   0x1070103487000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP27_IP2_GPIO"      ,	   0x1070103687000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP28_IP2_GPIO"      ,	   0x1070103887000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP29_IP2_GPIO"      ,	   0x1070103a87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP30_IP2_GPIO"      ,	   0x1070103c87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP31_IP2_GPIO"      ,	   0x1070103e87000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"CIU2_SRC_PP0_IP2_IO"         ,	   0x1070100084000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP1_IP2_IO"         ,	   0x1070100284000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP2_IP2_IO"         ,	   0x1070100484000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP3_IP2_IO"         ,	   0x1070100684000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP4_IP2_IO"         ,	   0x1070100884000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP5_IP2_IO"         ,	   0x1070100a84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP6_IP2_IO"         ,	   0x1070100c84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP7_IP2_IO"         ,	   0x1070100e84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP8_IP2_IO"         ,	   0x1070101084000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP9_IP2_IO"         ,	   0x1070101284000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP10_IP2_IO"        ,	   0x1070101484000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP11_IP2_IO"        ,	   0x1070101684000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP12_IP2_IO"        ,	   0x1070101884000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP13_IP2_IO"        ,	   0x1070101a84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP14_IP2_IO"        ,	   0x1070101c84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP15_IP2_IO"        ,	   0x1070101e84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP16_IP2_IO"        ,	   0x1070102084000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP17_IP2_IO"        ,	   0x1070102284000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP18_IP2_IO"        ,	   0x1070102484000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP19_IP2_IO"        ,	   0x1070102684000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP20_IP2_IO"        ,	   0x1070102884000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP21_IP2_IO"        ,	   0x1070102a84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP22_IP2_IO"        ,	   0x1070102c84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP23_IP2_IO"        ,	   0x1070102e84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP24_IP2_IO"        ,	   0x1070103084000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP25_IP2_IO"        ,	   0x1070103284000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP26_IP2_IO"        ,	   0x1070103484000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP27_IP2_IO"        ,	   0x1070103684000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP28_IP2_IO"        ,	   0x1070103884000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP29_IP2_IO"        ,	   0x1070103a84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP30_IP2_IO"        ,	   0x1070103c84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP31_IP2_IO"        ,	   0x1070103e84000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"CIU2_SRC_PP0_IP2_MBOX"       ,	   0x1070100088000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP1_IP2_MBOX"       ,	   0x1070100288000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP2_IP2_MBOX"       ,	   0x1070100488000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP3_IP2_MBOX"       ,	   0x1070100688000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP4_IP2_MBOX"       ,	   0x1070100888000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP5_IP2_MBOX"       ,	   0x1070100a88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP6_IP2_MBOX"       ,	   0x1070100c88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP7_IP2_MBOX"       ,	   0x1070100e88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP8_IP2_MBOX"       ,	   0x1070101088000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP9_IP2_MBOX"       ,	   0x1070101288000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP10_IP2_MBOX"      ,	   0x1070101488000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP11_IP2_MBOX"      ,	   0x1070101688000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP12_IP2_MBOX"      ,	   0x1070101888000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP13_IP2_MBOX"      ,	   0x1070101a88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP14_IP2_MBOX"      ,	   0x1070101c88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP15_IP2_MBOX"      ,	   0x1070101e88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP16_IP2_MBOX"      ,	   0x1070102088000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP17_IP2_MBOX"      ,	   0x1070102288000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP18_IP2_MBOX"      ,	   0x1070102488000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP19_IP2_MBOX"      ,	   0x1070102688000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP20_IP2_MBOX"      ,	   0x1070102888000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP21_IP2_MBOX"      ,	   0x1070102a88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP22_IP2_MBOX"      ,	   0x1070102c88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP23_IP2_MBOX"      ,	   0x1070102e88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP24_IP2_MBOX"      ,	   0x1070103088000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP25_IP2_MBOX"      ,	   0x1070103288000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP26_IP2_MBOX"      ,	   0x1070103488000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP27_IP2_MBOX"      ,	   0x1070103688000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP28_IP2_MBOX"      ,	   0x1070103888000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP29_IP2_MBOX"      ,	   0x1070103a88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP30_IP2_MBOX"      ,	   0x1070103c88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP31_IP2_MBOX"      ,	   0x1070103e88000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"CIU2_SRC_PP0_IP2_MEM"        ,	   0x1070100085000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP1_IP2_MEM"        ,	   0x1070100285000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP2_IP2_MEM"        ,	   0x1070100485000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP3_IP2_MEM"        ,	   0x1070100685000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP4_IP2_MEM"        ,	   0x1070100885000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP5_IP2_MEM"        ,	   0x1070100a85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP6_IP2_MEM"        ,	   0x1070100c85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP7_IP2_MEM"        ,	   0x1070100e85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP8_IP2_MEM"        ,	   0x1070101085000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP9_IP2_MEM"        ,	   0x1070101285000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP10_IP2_MEM"       ,	   0x1070101485000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP11_IP2_MEM"       ,	   0x1070101685000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP12_IP2_MEM"       ,	   0x1070101885000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP13_IP2_MEM"       ,	   0x1070101a85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP14_IP2_MEM"       ,	   0x1070101c85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP15_IP2_MEM"       ,	   0x1070101e85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP16_IP2_MEM"       ,	   0x1070102085000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP17_IP2_MEM"       ,	   0x1070102285000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP18_IP2_MEM"       ,	   0x1070102485000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP19_IP2_MEM"       ,	   0x1070102685000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP20_IP2_MEM"       ,	   0x1070102885000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP21_IP2_MEM"       ,	   0x1070102a85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP22_IP2_MEM"       ,	   0x1070102c85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP23_IP2_MEM"       ,	   0x1070102e85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP24_IP2_MEM"       ,	   0x1070103085000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP25_IP2_MEM"       ,	   0x1070103285000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP26_IP2_MEM"       ,	   0x1070103485000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP27_IP2_MEM"       ,	   0x1070103685000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP28_IP2_MEM"       ,	   0x1070103885000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP29_IP2_MEM"       ,	   0x1070103a85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP30_IP2_MEM"       ,	   0x1070103c85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP31_IP2_MEM"       ,	   0x1070103e85000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"CIU2_SRC_PP0_IP2_MIO"        ,	   0x1070100083000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP1_IP2_MIO"        ,	   0x1070100283000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP2_IP2_MIO"        ,	   0x1070100483000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP3_IP2_MIO"        ,	   0x1070100683000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP4_IP2_MIO"        ,	   0x1070100883000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP5_IP2_MIO"        ,	   0x1070100a83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP6_IP2_MIO"        ,	   0x1070100c83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP7_IP2_MIO"        ,	   0x1070100e83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP8_IP2_MIO"        ,	   0x1070101083000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP9_IP2_MIO"        ,	   0x1070101283000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP10_IP2_MIO"       ,	   0x1070101483000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP11_IP2_MIO"       ,	   0x1070101683000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP12_IP2_MIO"       ,	   0x1070101883000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP13_IP2_MIO"       ,	   0x1070101a83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP14_IP2_MIO"       ,	   0x1070101c83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP15_IP2_MIO"       ,	   0x1070101e83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP16_IP2_MIO"       ,	   0x1070102083000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP17_IP2_MIO"       ,	   0x1070102283000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP18_IP2_MIO"       ,	   0x1070102483000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP19_IP2_MIO"       ,	   0x1070102683000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP20_IP2_MIO"       ,	   0x1070102883000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP21_IP2_MIO"       ,	   0x1070102a83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP22_IP2_MIO"       ,	   0x1070102c83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP23_IP2_MIO"       ,	   0x1070102e83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP24_IP2_MIO"       ,	   0x1070103083000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP25_IP2_MIO"       ,	   0x1070103283000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP26_IP2_MIO"       ,	   0x1070103483000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP27_IP2_MIO"       ,	   0x1070103683000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP28_IP2_MIO"       ,	   0x1070103883000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP29_IP2_MIO"       ,	   0x1070103a83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP30_IP2_MIO"       ,	   0x1070103c83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP31_IP2_MIO"       ,	   0x1070103e83000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"CIU2_SRC_PP0_IP2_PKT"        ,	   0x1070100086000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP1_IP2_PKT"        ,	   0x1070100286000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP2_IP2_PKT"        ,	   0x1070100486000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP3_IP2_PKT"        ,	   0x1070100686000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP4_IP2_PKT"        ,	   0x1070100886000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP5_IP2_PKT"        ,	   0x1070100a86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP6_IP2_PKT"        ,	   0x1070100c86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP7_IP2_PKT"        ,	   0x1070100e86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP8_IP2_PKT"        ,	   0x1070101086000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP9_IP2_PKT"        ,	   0x1070101286000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP10_IP2_PKT"       ,	   0x1070101486000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP11_IP2_PKT"       ,	   0x1070101686000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP12_IP2_PKT"       ,	   0x1070101886000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP13_IP2_PKT"       ,	   0x1070101a86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP14_IP2_PKT"       ,	   0x1070101c86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP15_IP2_PKT"       ,	   0x1070101e86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP16_IP2_PKT"       ,	   0x1070102086000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP17_IP2_PKT"       ,	   0x1070102286000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP18_IP2_PKT"       ,	   0x1070102486000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP19_IP2_PKT"       ,	   0x1070102686000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP20_IP2_PKT"       ,	   0x1070102886000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP21_IP2_PKT"       ,	   0x1070102a86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP22_IP2_PKT"       ,	   0x1070102c86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP23_IP2_PKT"       ,	   0x1070102e86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP24_IP2_PKT"       ,	   0x1070103086000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP25_IP2_PKT"       ,	   0x1070103286000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP26_IP2_PKT"       ,	   0x1070103486000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP27_IP2_PKT"       ,	   0x1070103686000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP28_IP2_PKT"       ,	   0x1070103886000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP29_IP2_PKT"       ,	   0x1070103a86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP30_IP2_PKT"       ,	   0x1070103c86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP31_IP2_PKT"       ,	   0x1070103e86000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"CIU2_SRC_PP0_IP2_RML"        ,	   0x1070100082000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP1_IP2_RML"        ,	   0x1070100282000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP2_IP2_RML"        ,	   0x1070100482000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP3_IP2_RML"        ,	   0x1070100682000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP4_IP2_RML"        ,	   0x1070100882000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP5_IP2_RML"        ,	   0x1070100a82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP6_IP2_RML"        ,	   0x1070100c82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP7_IP2_RML"        ,	   0x1070100e82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP8_IP2_RML"        ,	   0x1070101082000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP9_IP2_RML"        ,	   0x1070101282000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP10_IP2_RML"       ,	   0x1070101482000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP11_IP2_RML"       ,	   0x1070101682000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP12_IP2_RML"       ,	   0x1070101882000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP13_IP2_RML"       ,	   0x1070101a82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP14_IP2_RML"       ,	   0x1070101c82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP15_IP2_RML"       ,	   0x1070101e82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP16_IP2_RML"       ,	   0x1070102082000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP17_IP2_RML"       ,	   0x1070102282000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP18_IP2_RML"       ,	   0x1070102482000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP19_IP2_RML"       ,	   0x1070102682000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP20_IP2_RML"       ,	   0x1070102882000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP21_IP2_RML"       ,	   0x1070102a82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP22_IP2_RML"       ,	   0x1070102c82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP23_IP2_RML"       ,	   0x1070102e82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP24_IP2_RML"       ,	   0x1070103082000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP25_IP2_RML"       ,	   0x1070103282000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP26_IP2_RML"       ,	   0x1070103482000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP27_IP2_RML"       ,	   0x1070103682000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP28_IP2_RML"       ,	   0x1070103882000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP29_IP2_RML"       ,	   0x1070103a82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP30_IP2_RML"       ,	   0x1070103c82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP31_IP2_RML"       ,	   0x1070103e82000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"CIU2_SRC_PP0_IP2_WDOG"       ,	   0x1070100081000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP1_IP2_WDOG"       ,	   0x1070100281000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP2_IP2_WDOG"       ,	   0x1070100481000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP3_IP2_WDOG"       ,	   0x1070100681000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP4_IP2_WDOG"       ,	   0x1070100881000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP5_IP2_WDOG"       ,	   0x1070100a81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP6_IP2_WDOG"       ,	   0x1070100c81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP7_IP2_WDOG"       ,	   0x1070100e81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP8_IP2_WDOG"       ,	   0x1070101081000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP9_IP2_WDOG"       ,	   0x1070101281000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP10_IP2_WDOG"      ,	   0x1070101481000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP11_IP2_WDOG"      ,	   0x1070101681000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP12_IP2_WDOG"      ,	   0x1070101881000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP13_IP2_WDOG"      ,	   0x1070101a81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP14_IP2_WDOG"      ,	   0x1070101c81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP15_IP2_WDOG"      ,	   0x1070101e81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP16_IP2_WDOG"      ,	   0x1070102081000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP17_IP2_WDOG"      ,	   0x1070102281000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP18_IP2_WDOG"      ,	   0x1070102481000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP19_IP2_WDOG"      ,	   0x1070102681000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP20_IP2_WDOG"      ,	   0x1070102881000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP21_IP2_WDOG"      ,	   0x1070102a81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP22_IP2_WDOG"      ,	   0x1070102c81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP23_IP2_WDOG"      ,	   0x1070102e81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP24_IP2_WDOG"      ,	   0x1070103081000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP25_IP2_WDOG"      ,	   0x1070103281000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP26_IP2_WDOG"      ,	   0x1070103481000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP27_IP2_WDOG"      ,	   0x1070103681000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP28_IP2_WDOG"      ,	   0x1070103881000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP29_IP2_WDOG"      ,	   0x1070103a81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP30_IP2_WDOG"      ,	   0x1070103c81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP31_IP2_WDOG"      ,	   0x1070103e81000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"CIU2_SRC_PP0_IP2_WRKQ"       ,	   0x1070100080000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP1_IP2_WRKQ"       ,	   0x1070100280000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP2_IP2_WRKQ"       ,	   0x1070100480000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP3_IP2_WRKQ"       ,	   0x1070100680000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP4_IP2_WRKQ"       ,	   0x1070100880000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP5_IP2_WRKQ"       ,	   0x1070100a80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP6_IP2_WRKQ"       ,	   0x1070100c80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP7_IP2_WRKQ"       ,	   0x1070100e80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP8_IP2_WRKQ"       ,	   0x1070101080000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP9_IP2_WRKQ"       ,	   0x1070101280000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP10_IP2_WRKQ"      ,	   0x1070101480000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP11_IP2_WRKQ"      ,	   0x1070101680000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP12_IP2_WRKQ"      ,	   0x1070101880000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP13_IP2_WRKQ"      ,	   0x1070101a80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP14_IP2_WRKQ"      ,	   0x1070101c80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP15_IP2_WRKQ"      ,	   0x1070101e80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP16_IP2_WRKQ"      ,	   0x1070102080000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP17_IP2_WRKQ"      ,	   0x1070102280000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP18_IP2_WRKQ"      ,	   0x1070102480000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP19_IP2_WRKQ"      ,	   0x1070102680000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP20_IP2_WRKQ"      ,	   0x1070102880000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP21_IP2_WRKQ"      ,	   0x1070102a80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP22_IP2_WRKQ"      ,	   0x1070102c80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP23_IP2_WRKQ"      ,	   0x1070102e80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP24_IP2_WRKQ"      ,	   0x1070103080000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP25_IP2_WRKQ"      ,	   0x1070103280000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP26_IP2_WRKQ"      ,	   0x1070103480000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP27_IP2_WRKQ"      ,	   0x1070103680000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP28_IP2_WRKQ"      ,	   0x1070103880000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP29_IP2_WRKQ"      ,	   0x1070103a80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP30_IP2_WRKQ"      ,	   0x1070103c80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP31_IP2_WRKQ"      ,	   0x1070103e80000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"CIU2_SRC_PP0_IP3_GPIO"       ,	   0x1070100087200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP1_IP3_GPIO"       ,	   0x1070100287200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP2_IP3_GPIO"       ,	   0x1070100487200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP3_IP3_GPIO"       ,	   0x1070100687200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP4_IP3_GPIO"       ,	   0x1070100887200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP5_IP3_GPIO"       ,	   0x1070100a87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP6_IP3_GPIO"       ,	   0x1070100c87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP7_IP3_GPIO"       ,	   0x1070100e87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP8_IP3_GPIO"       ,	   0x1070101087200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP9_IP3_GPIO"       ,	   0x1070101287200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP10_IP3_GPIO"      ,	   0x1070101487200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP11_IP3_GPIO"      ,	   0x1070101687200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP12_IP3_GPIO"      ,	   0x1070101887200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP13_IP3_GPIO"      ,	   0x1070101a87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP14_IP3_GPIO"      ,	   0x1070101c87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP15_IP3_GPIO"      ,	   0x1070101e87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP16_IP3_GPIO"      ,	   0x1070102087200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP17_IP3_GPIO"      ,	   0x1070102287200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP18_IP3_GPIO"      ,	   0x1070102487200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP19_IP3_GPIO"      ,	   0x1070102687200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP20_IP3_GPIO"      ,	   0x1070102887200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP21_IP3_GPIO"      ,	   0x1070102a87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP22_IP3_GPIO"      ,	   0x1070102c87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP23_IP3_GPIO"      ,	   0x1070102e87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP24_IP3_GPIO"      ,	   0x1070103087200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP25_IP3_GPIO"      ,	   0x1070103287200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP26_IP3_GPIO"      ,	   0x1070103487200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP27_IP3_GPIO"      ,	   0x1070103687200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP28_IP3_GPIO"      ,	   0x1070103887200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP29_IP3_GPIO"      ,	   0x1070103a87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP30_IP3_GPIO"      ,	   0x1070103c87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP31_IP3_GPIO"      ,	   0x1070103e87200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"CIU2_SRC_PP0_IP3_IO"         ,	   0x1070100084200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP1_IP3_IO"         ,	   0x1070100284200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP2_IP3_IO"         ,	   0x1070100484200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP3_IP3_IO"         ,	   0x1070100684200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP4_IP3_IO"         ,	   0x1070100884200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP5_IP3_IO"         ,	   0x1070100a84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP6_IP3_IO"         ,	   0x1070100c84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP7_IP3_IO"         ,	   0x1070100e84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP8_IP3_IO"         ,	   0x1070101084200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP9_IP3_IO"         ,	   0x1070101284200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP10_IP3_IO"        ,	   0x1070101484200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP11_IP3_IO"        ,	   0x1070101684200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP12_IP3_IO"        ,	   0x1070101884200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP13_IP3_IO"        ,	   0x1070101a84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP14_IP3_IO"        ,	   0x1070101c84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP15_IP3_IO"        ,	   0x1070101e84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP16_IP3_IO"        ,	   0x1070102084200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP17_IP3_IO"        ,	   0x1070102284200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP18_IP3_IO"        ,	   0x1070102484200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP19_IP3_IO"        ,	   0x1070102684200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP20_IP3_IO"        ,	   0x1070102884200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP21_IP3_IO"        ,	   0x1070102a84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP22_IP3_IO"        ,	   0x1070102c84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP23_IP3_IO"        ,	   0x1070102e84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP24_IP3_IO"        ,	   0x1070103084200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP25_IP3_IO"        ,	   0x1070103284200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP26_IP3_IO"        ,	   0x1070103484200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP27_IP3_IO"        ,	   0x1070103684200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP28_IP3_IO"        ,	   0x1070103884200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP29_IP3_IO"        ,	   0x1070103a84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP30_IP3_IO"        ,	   0x1070103c84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP31_IP3_IO"        ,	   0x1070103e84200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"CIU2_SRC_PP0_IP3_MBOX"       ,	   0x1070100088200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP1_IP3_MBOX"       ,	   0x1070100288200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP2_IP3_MBOX"       ,	   0x1070100488200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP3_IP3_MBOX"       ,	   0x1070100688200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP4_IP3_MBOX"       ,	   0x1070100888200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP5_IP3_MBOX"       ,	   0x1070100a88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP6_IP3_MBOX"       ,	   0x1070100c88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP7_IP3_MBOX"       ,	   0x1070100e88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP8_IP3_MBOX"       ,	   0x1070101088200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP9_IP3_MBOX"       ,	   0x1070101288200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP10_IP3_MBOX"      ,	   0x1070101488200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP11_IP3_MBOX"      ,	   0x1070101688200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP12_IP3_MBOX"      ,	   0x1070101888200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP13_IP3_MBOX"      ,	   0x1070101a88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP14_IP3_MBOX"      ,	   0x1070101c88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP15_IP3_MBOX"      ,	   0x1070101e88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP16_IP3_MBOX"      ,	   0x1070102088200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP17_IP3_MBOX"      ,	   0x1070102288200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP18_IP3_MBOX"      ,	   0x1070102488200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP19_IP3_MBOX"      ,	   0x1070102688200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP20_IP3_MBOX"      ,	   0x1070102888200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP21_IP3_MBOX"      ,	   0x1070102a88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP22_IP3_MBOX"      ,	   0x1070102c88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP23_IP3_MBOX"      ,	   0x1070102e88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP24_IP3_MBOX"      ,	   0x1070103088200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP25_IP3_MBOX"      ,	   0x1070103288200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP26_IP3_MBOX"      ,	   0x1070103488200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP27_IP3_MBOX"      ,	   0x1070103688200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP28_IP3_MBOX"      ,	   0x1070103888200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP29_IP3_MBOX"      ,	   0x1070103a88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP30_IP3_MBOX"      ,	   0x1070103c88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP31_IP3_MBOX"      ,	   0x1070103e88200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"CIU2_SRC_PP0_IP3_MEM"        ,	   0x1070100085200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP1_IP3_MEM"        ,	   0x1070100285200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP2_IP3_MEM"        ,	   0x1070100485200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP3_IP3_MEM"        ,	   0x1070100685200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP4_IP3_MEM"        ,	   0x1070100885200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP5_IP3_MEM"        ,	   0x1070100a85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP6_IP3_MEM"        ,	   0x1070100c85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP7_IP3_MEM"        ,	   0x1070100e85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP8_IP3_MEM"        ,	   0x1070101085200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP9_IP3_MEM"        ,	   0x1070101285200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP10_IP3_MEM"       ,	   0x1070101485200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP11_IP3_MEM"       ,	   0x1070101685200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP12_IP3_MEM"       ,	   0x1070101885200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP13_IP3_MEM"       ,	   0x1070101a85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP14_IP3_MEM"       ,	   0x1070101c85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP15_IP3_MEM"       ,	   0x1070101e85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP16_IP3_MEM"       ,	   0x1070102085200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP17_IP3_MEM"       ,	   0x1070102285200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP18_IP3_MEM"       ,	   0x1070102485200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP19_IP3_MEM"       ,	   0x1070102685200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP20_IP3_MEM"       ,	   0x1070102885200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP21_IP3_MEM"       ,	   0x1070102a85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP22_IP3_MEM"       ,	   0x1070102c85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP23_IP3_MEM"       ,	   0x1070102e85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP24_IP3_MEM"       ,	   0x1070103085200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP25_IP3_MEM"       ,	   0x1070103285200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP26_IP3_MEM"       ,	   0x1070103485200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP27_IP3_MEM"       ,	   0x1070103685200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP28_IP3_MEM"       ,	   0x1070103885200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP29_IP3_MEM"       ,	   0x1070103a85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP30_IP3_MEM"       ,	   0x1070103c85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP31_IP3_MEM"       ,	   0x1070103e85200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"CIU2_SRC_PP0_IP3_MIO"        ,	   0x1070100083200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP1_IP3_MIO"        ,	   0x1070100283200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP2_IP3_MIO"        ,	   0x1070100483200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP3_IP3_MIO"        ,	   0x1070100683200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP4_IP3_MIO"        ,	   0x1070100883200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP5_IP3_MIO"        ,	   0x1070100a83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP6_IP3_MIO"        ,	   0x1070100c83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP7_IP3_MIO"        ,	   0x1070100e83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP8_IP3_MIO"        ,	   0x1070101083200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP9_IP3_MIO"        ,	   0x1070101283200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP10_IP3_MIO"       ,	   0x1070101483200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP11_IP3_MIO"       ,	   0x1070101683200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP12_IP3_MIO"       ,	   0x1070101883200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP13_IP3_MIO"       ,	   0x1070101a83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP14_IP3_MIO"       ,	   0x1070101c83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP15_IP3_MIO"       ,	   0x1070101e83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP16_IP3_MIO"       ,	   0x1070102083200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP17_IP3_MIO"       ,	   0x1070102283200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP18_IP3_MIO"       ,	   0x1070102483200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP19_IP3_MIO"       ,	   0x1070102683200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP20_IP3_MIO"       ,	   0x1070102883200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP21_IP3_MIO"       ,	   0x1070102a83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP22_IP3_MIO"       ,	   0x1070102c83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP23_IP3_MIO"       ,	   0x1070102e83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP24_IP3_MIO"       ,	   0x1070103083200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP25_IP3_MIO"       ,	   0x1070103283200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP26_IP3_MIO"       ,	   0x1070103483200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP27_IP3_MIO"       ,	   0x1070103683200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP28_IP3_MIO"       ,	   0x1070103883200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP29_IP3_MIO"       ,	   0x1070103a83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP30_IP3_MIO"       ,	   0x1070103c83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP31_IP3_MIO"       ,	   0x1070103e83200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"CIU2_SRC_PP0_IP3_PKT"        ,	   0x1070100086200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP1_IP3_PKT"        ,	   0x1070100286200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP2_IP3_PKT"        ,	   0x1070100486200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP3_IP3_PKT"        ,	   0x1070100686200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP4_IP3_PKT"        ,	   0x1070100886200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP5_IP3_PKT"        ,	   0x1070100a86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP6_IP3_PKT"        ,	   0x1070100c86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP7_IP3_PKT"        ,	   0x1070100e86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP8_IP3_PKT"        ,	   0x1070101086200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP9_IP3_PKT"        ,	   0x1070101286200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP10_IP3_PKT"       ,	   0x1070101486200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP11_IP3_PKT"       ,	   0x1070101686200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP12_IP3_PKT"       ,	   0x1070101886200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP13_IP3_PKT"       ,	   0x1070101a86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP14_IP3_PKT"       ,	   0x1070101c86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP15_IP3_PKT"       ,	   0x1070101e86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP16_IP3_PKT"       ,	   0x1070102086200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP17_IP3_PKT"       ,	   0x1070102286200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP18_IP3_PKT"       ,	   0x1070102486200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP19_IP3_PKT"       ,	   0x1070102686200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP20_IP3_PKT"       ,	   0x1070102886200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP21_IP3_PKT"       ,	   0x1070102a86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP22_IP3_PKT"       ,	   0x1070102c86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP23_IP3_PKT"       ,	   0x1070102e86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP24_IP3_PKT"       ,	   0x1070103086200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP25_IP3_PKT"       ,	   0x1070103286200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP26_IP3_PKT"       ,	   0x1070103486200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP27_IP3_PKT"       ,	   0x1070103686200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP28_IP3_PKT"       ,	   0x1070103886200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP29_IP3_PKT"       ,	   0x1070103a86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP30_IP3_PKT"       ,	   0x1070103c86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP31_IP3_PKT"       ,	   0x1070103e86200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"CIU2_SRC_PP0_IP3_RML"        ,	   0x1070100082200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP1_IP3_RML"        ,	   0x1070100282200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP2_IP3_RML"        ,	   0x1070100482200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP3_IP3_RML"        ,	   0x1070100682200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP4_IP3_RML"        ,	   0x1070100882200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP5_IP3_RML"        ,	   0x1070100a82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP6_IP3_RML"        ,	   0x1070100c82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP7_IP3_RML"        ,	   0x1070100e82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP8_IP3_RML"        ,	   0x1070101082200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP9_IP3_RML"        ,	   0x1070101282200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP10_IP3_RML"       ,	   0x1070101482200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP11_IP3_RML"       ,	   0x1070101682200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP12_IP3_RML"       ,	   0x1070101882200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP13_IP3_RML"       ,	   0x1070101a82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP14_IP3_RML"       ,	   0x1070101c82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP15_IP3_RML"       ,	   0x1070101e82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP16_IP3_RML"       ,	   0x1070102082200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP17_IP3_RML"       ,	   0x1070102282200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP18_IP3_RML"       ,	   0x1070102482200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP19_IP3_RML"       ,	   0x1070102682200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP20_IP3_RML"       ,	   0x1070102882200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP21_IP3_RML"       ,	   0x1070102a82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP22_IP3_RML"       ,	   0x1070102c82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP23_IP3_RML"       ,	   0x1070102e82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP24_IP3_RML"       ,	   0x1070103082200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP25_IP3_RML"       ,	   0x1070103282200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP26_IP3_RML"       ,	   0x1070103482200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP27_IP3_RML"       ,	   0x1070103682200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP28_IP3_RML"       ,	   0x1070103882200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP29_IP3_RML"       ,	   0x1070103a82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP30_IP3_RML"       ,	   0x1070103c82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP31_IP3_RML"       ,	   0x1070103e82200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"CIU2_SRC_PP0_IP3_WDOG"       ,	   0x1070100081200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP1_IP3_WDOG"       ,	   0x1070100281200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP2_IP3_WDOG"       ,	   0x1070100481200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP3_IP3_WDOG"       ,	   0x1070100681200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP4_IP3_WDOG"       ,	   0x1070100881200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP5_IP3_WDOG"       ,	   0x1070100a81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP6_IP3_WDOG"       ,	   0x1070100c81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP7_IP3_WDOG"       ,	   0x1070100e81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP8_IP3_WDOG"       ,	   0x1070101081200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP9_IP3_WDOG"       ,	   0x1070101281200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP10_IP3_WDOG"      ,	   0x1070101481200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP11_IP3_WDOG"      ,	   0x1070101681200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP12_IP3_WDOG"      ,	   0x1070101881200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP13_IP3_WDOG"      ,	   0x1070101a81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP14_IP3_WDOG"      ,	   0x1070101c81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP15_IP3_WDOG"      ,	   0x1070101e81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP16_IP3_WDOG"      ,	   0x1070102081200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP17_IP3_WDOG"      ,	   0x1070102281200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP18_IP3_WDOG"      ,	   0x1070102481200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP19_IP3_WDOG"      ,	   0x1070102681200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP20_IP3_WDOG"      ,	   0x1070102881200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP21_IP3_WDOG"      ,	   0x1070102a81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP22_IP3_WDOG"      ,	   0x1070102c81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP23_IP3_WDOG"      ,	   0x1070102e81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP24_IP3_WDOG"      ,	   0x1070103081200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP25_IP3_WDOG"      ,	   0x1070103281200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP26_IP3_WDOG"      ,	   0x1070103481200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP27_IP3_WDOG"      ,	   0x1070103681200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP28_IP3_WDOG"      ,	   0x1070103881200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP29_IP3_WDOG"      ,	   0x1070103a81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP30_IP3_WDOG"      ,	   0x1070103c81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP31_IP3_WDOG"      ,	   0x1070103e81200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"CIU2_SRC_PP0_IP3_WRKQ"       ,	   0x1070100080200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP1_IP3_WRKQ"       ,	   0x1070100280200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP2_IP3_WRKQ"       ,	   0x1070100480200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP3_IP3_WRKQ"       ,	   0x1070100680200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP4_IP3_WRKQ"       ,	   0x1070100880200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP5_IP3_WRKQ"       ,	   0x1070100a80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP6_IP3_WRKQ"       ,	   0x1070100c80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP7_IP3_WRKQ"       ,	   0x1070100e80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP8_IP3_WRKQ"       ,	   0x1070101080200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP9_IP3_WRKQ"       ,	   0x1070101280200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP10_IP3_WRKQ"      ,	   0x1070101480200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP11_IP3_WRKQ"      ,	   0x1070101680200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP12_IP3_WRKQ"      ,	   0x1070101880200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP13_IP3_WRKQ"      ,	   0x1070101a80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP14_IP3_WRKQ"      ,	   0x1070101c80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP15_IP3_WRKQ"      ,	   0x1070101e80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP16_IP3_WRKQ"      ,	   0x1070102080200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP17_IP3_WRKQ"      ,	   0x1070102280200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP18_IP3_WRKQ"      ,	   0x1070102480200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP19_IP3_WRKQ"      ,	   0x1070102680200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP20_IP3_WRKQ"      ,	   0x1070102880200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP21_IP3_WRKQ"      ,	   0x1070102a80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP22_IP3_WRKQ"      ,	   0x1070102c80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP23_IP3_WRKQ"      ,	   0x1070102e80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP24_IP3_WRKQ"      ,	   0x1070103080200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP25_IP3_WRKQ"      ,	   0x1070103280200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP26_IP3_WRKQ"      ,	   0x1070103480200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP27_IP3_WRKQ"      ,	   0x1070103680200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP28_IP3_WRKQ"      ,	   0x1070103880200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP29_IP3_WRKQ"      ,	   0x1070103a80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP30_IP3_WRKQ"      ,	   0x1070103c80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP31_IP3_WRKQ"      ,	   0x1070103e80200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"CIU2_SRC_PP0_IP4_GPIO"       ,	   0x1070100087400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP1_IP4_GPIO"       ,	   0x1070100287400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP2_IP4_GPIO"       ,	   0x1070100487400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP3_IP4_GPIO"       ,	   0x1070100687400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP4_IP4_GPIO"       ,	   0x1070100887400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP5_IP4_GPIO"       ,	   0x1070100a87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP6_IP4_GPIO"       ,	   0x1070100c87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP7_IP4_GPIO"       ,	   0x1070100e87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP8_IP4_GPIO"       ,	   0x1070101087400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP9_IP4_GPIO"       ,	   0x1070101287400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP10_IP4_GPIO"      ,	   0x1070101487400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP11_IP4_GPIO"      ,	   0x1070101687400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP12_IP4_GPIO"      ,	   0x1070101887400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP13_IP4_GPIO"      ,	   0x1070101a87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP14_IP4_GPIO"      ,	   0x1070101c87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP15_IP4_GPIO"      ,	   0x1070101e87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP16_IP4_GPIO"      ,	   0x1070102087400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP17_IP4_GPIO"      ,	   0x1070102287400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP18_IP4_GPIO"      ,	   0x1070102487400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP19_IP4_GPIO"      ,	   0x1070102687400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP20_IP4_GPIO"      ,	   0x1070102887400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP21_IP4_GPIO"      ,	   0x1070102a87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP22_IP4_GPIO"      ,	   0x1070102c87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP23_IP4_GPIO"      ,	   0x1070102e87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP24_IP4_GPIO"      ,	   0x1070103087400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP25_IP4_GPIO"      ,	   0x1070103287400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP26_IP4_GPIO"      ,	   0x1070103487400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP27_IP4_GPIO"      ,	   0x1070103687400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP28_IP4_GPIO"      ,	   0x1070103887400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP29_IP4_GPIO"      ,	   0x1070103a87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP30_IP4_GPIO"      ,	   0x1070103c87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP31_IP4_GPIO"      ,	   0x1070103e87400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"CIU2_SRC_PP0_IP4_IO"         ,	   0x1070100084400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP1_IP4_IO"         ,	   0x1070100284400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP2_IP4_IO"         ,	   0x1070100484400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP3_IP4_IO"         ,	   0x1070100684400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP4_IP4_IO"         ,	   0x1070100884400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP5_IP4_IO"         ,	   0x1070100a84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP6_IP4_IO"         ,	   0x1070100c84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP7_IP4_IO"         ,	   0x1070100e84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP8_IP4_IO"         ,	   0x1070101084400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP9_IP4_IO"         ,	   0x1070101284400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP10_IP4_IO"        ,	   0x1070101484400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP11_IP4_IO"        ,	   0x1070101684400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP12_IP4_IO"        ,	   0x1070101884400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP13_IP4_IO"        ,	   0x1070101a84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP14_IP4_IO"        ,	   0x1070101c84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP15_IP4_IO"        ,	   0x1070101e84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP16_IP4_IO"        ,	   0x1070102084400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP17_IP4_IO"        ,	   0x1070102284400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP18_IP4_IO"        ,	   0x1070102484400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP19_IP4_IO"        ,	   0x1070102684400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP20_IP4_IO"        ,	   0x1070102884400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP21_IP4_IO"        ,	   0x1070102a84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP22_IP4_IO"        ,	   0x1070102c84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP23_IP4_IO"        ,	   0x1070102e84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP24_IP4_IO"        ,	   0x1070103084400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP25_IP4_IO"        ,	   0x1070103284400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP26_IP4_IO"        ,	   0x1070103484400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP27_IP4_IO"        ,	   0x1070103684400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP28_IP4_IO"        ,	   0x1070103884400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP29_IP4_IO"        ,	   0x1070103a84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP30_IP4_IO"        ,	   0x1070103c84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP31_IP4_IO"        ,	   0x1070103e84400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"CIU2_SRC_PP0_IP4_MBOX"       ,	   0x1070100088400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP1_IP4_MBOX"       ,	   0x1070100288400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP2_IP4_MBOX"       ,	   0x1070100488400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP3_IP4_MBOX"       ,	   0x1070100688400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP4_IP4_MBOX"       ,	   0x1070100888400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP5_IP4_MBOX"       ,	   0x1070100a88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP6_IP4_MBOX"       ,	   0x1070100c88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP7_IP4_MBOX"       ,	   0x1070100e88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP8_IP4_MBOX"       ,	   0x1070101088400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP9_IP4_MBOX"       ,	   0x1070101288400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP10_IP4_MBOX"      ,	   0x1070101488400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP11_IP4_MBOX"      ,	   0x1070101688400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP12_IP4_MBOX"      ,	   0x1070101888400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP13_IP4_MBOX"      ,	   0x1070101a88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP14_IP4_MBOX"      ,	   0x1070101c88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP15_IP4_MBOX"      ,	   0x1070101e88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP16_IP4_MBOX"      ,	   0x1070102088400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP17_IP4_MBOX"      ,	   0x1070102288400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP18_IP4_MBOX"      ,	   0x1070102488400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP19_IP4_MBOX"      ,	   0x1070102688400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP20_IP4_MBOX"      ,	   0x1070102888400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP21_IP4_MBOX"      ,	   0x1070102a88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP22_IP4_MBOX"      ,	   0x1070102c88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP23_IP4_MBOX"      ,	   0x1070102e88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP24_IP4_MBOX"      ,	   0x1070103088400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP25_IP4_MBOX"      ,	   0x1070103288400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP26_IP4_MBOX"      ,	   0x1070103488400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP27_IP4_MBOX"      ,	   0x1070103688400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP28_IP4_MBOX"      ,	   0x1070103888400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP29_IP4_MBOX"      ,	   0x1070103a88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP30_IP4_MBOX"      ,	   0x1070103c88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP31_IP4_MBOX"      ,	   0x1070103e88400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"CIU2_SRC_PP0_IP4_MEM"        ,	   0x1070100085400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP1_IP4_MEM"        ,	   0x1070100285400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP2_IP4_MEM"        ,	   0x1070100485400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP3_IP4_MEM"        ,	   0x1070100685400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP4_IP4_MEM"        ,	   0x1070100885400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP5_IP4_MEM"        ,	   0x1070100a85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP6_IP4_MEM"        ,	   0x1070100c85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP7_IP4_MEM"        ,	   0x1070100e85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP8_IP4_MEM"        ,	   0x1070101085400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP9_IP4_MEM"        ,	   0x1070101285400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP10_IP4_MEM"       ,	   0x1070101485400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP11_IP4_MEM"       ,	   0x1070101685400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP12_IP4_MEM"       ,	   0x1070101885400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP13_IP4_MEM"       ,	   0x1070101a85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP14_IP4_MEM"       ,	   0x1070101c85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP15_IP4_MEM"       ,	   0x1070101e85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP16_IP4_MEM"       ,	   0x1070102085400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP17_IP4_MEM"       ,	   0x1070102285400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP18_IP4_MEM"       ,	   0x1070102485400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP19_IP4_MEM"       ,	   0x1070102685400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP20_IP4_MEM"       ,	   0x1070102885400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP21_IP4_MEM"       ,	   0x1070102a85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP22_IP4_MEM"       ,	   0x1070102c85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP23_IP4_MEM"       ,	   0x1070102e85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP24_IP4_MEM"       ,	   0x1070103085400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP25_IP4_MEM"       ,	   0x1070103285400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP26_IP4_MEM"       ,	   0x1070103485400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP27_IP4_MEM"       ,	   0x1070103685400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP28_IP4_MEM"       ,	   0x1070103885400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP29_IP4_MEM"       ,	   0x1070103a85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP30_IP4_MEM"       ,	   0x1070103c85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP31_IP4_MEM"       ,	   0x1070103e85400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"CIU2_SRC_PP0_IP4_MIO"        ,	   0x1070100083400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP1_IP4_MIO"        ,	   0x1070100283400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP2_IP4_MIO"        ,	   0x1070100483400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP3_IP4_MIO"        ,	   0x1070100683400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP4_IP4_MIO"        ,	   0x1070100883400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP5_IP4_MIO"        ,	   0x1070100a83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP6_IP4_MIO"        ,	   0x1070100c83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP7_IP4_MIO"        ,	   0x1070100e83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP8_IP4_MIO"        ,	   0x1070101083400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP9_IP4_MIO"        ,	   0x1070101283400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP10_IP4_MIO"       ,	   0x1070101483400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP11_IP4_MIO"       ,	   0x1070101683400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP12_IP4_MIO"       ,	   0x1070101883400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP13_IP4_MIO"       ,	   0x1070101a83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP14_IP4_MIO"       ,	   0x1070101c83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP15_IP4_MIO"       ,	   0x1070101e83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP16_IP4_MIO"       ,	   0x1070102083400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP17_IP4_MIO"       ,	   0x1070102283400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP18_IP4_MIO"       ,	   0x1070102483400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP19_IP4_MIO"       ,	   0x1070102683400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP20_IP4_MIO"       ,	   0x1070102883400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP21_IP4_MIO"       ,	   0x1070102a83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP22_IP4_MIO"       ,	   0x1070102c83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP23_IP4_MIO"       ,	   0x1070102e83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP24_IP4_MIO"       ,	   0x1070103083400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP25_IP4_MIO"       ,	   0x1070103283400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP26_IP4_MIO"       ,	   0x1070103483400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP27_IP4_MIO"       ,	   0x1070103683400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP28_IP4_MIO"       ,	   0x1070103883400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP29_IP4_MIO"       ,	   0x1070103a83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP30_IP4_MIO"       ,	   0x1070103c83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP31_IP4_MIO"       ,	   0x1070103e83400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"CIU2_SRC_PP0_IP4_PKT"        ,	   0x1070100086400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP1_IP4_PKT"        ,	   0x1070100286400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP2_IP4_PKT"        ,	   0x1070100486400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP3_IP4_PKT"        ,	   0x1070100686400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP4_IP4_PKT"        ,	   0x1070100886400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP5_IP4_PKT"        ,	   0x1070100a86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP6_IP4_PKT"        ,	   0x1070100c86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP7_IP4_PKT"        ,	   0x1070100e86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP8_IP4_PKT"        ,	   0x1070101086400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP9_IP4_PKT"        ,	   0x1070101286400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP10_IP4_PKT"       ,	   0x1070101486400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP11_IP4_PKT"       ,	   0x1070101686400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP12_IP4_PKT"       ,	   0x1070101886400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP13_IP4_PKT"       ,	   0x1070101a86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP14_IP4_PKT"       ,	   0x1070101c86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP15_IP4_PKT"       ,	   0x1070101e86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP16_IP4_PKT"       ,	   0x1070102086400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP17_IP4_PKT"       ,	   0x1070102286400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP18_IP4_PKT"       ,	   0x1070102486400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP19_IP4_PKT"       ,	   0x1070102686400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP20_IP4_PKT"       ,	   0x1070102886400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP21_IP4_PKT"       ,	   0x1070102a86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP22_IP4_PKT"       ,	   0x1070102c86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP23_IP4_PKT"       ,	   0x1070102e86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP24_IP4_PKT"       ,	   0x1070103086400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP25_IP4_PKT"       ,	   0x1070103286400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP26_IP4_PKT"       ,	   0x1070103486400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP27_IP4_PKT"       ,	   0x1070103686400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP28_IP4_PKT"       ,	   0x1070103886400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP29_IP4_PKT"       ,	   0x1070103a86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP30_IP4_PKT"       ,	   0x1070103c86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP31_IP4_PKT"       ,	   0x1070103e86400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"CIU2_SRC_PP0_IP4_RML"        ,	   0x1070100082400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP1_IP4_RML"        ,	   0x1070100282400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP2_IP4_RML"        ,	   0x1070100482400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP3_IP4_RML"        ,	   0x1070100682400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP4_IP4_RML"        ,	   0x1070100882400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP5_IP4_RML"        ,	   0x1070100a82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP6_IP4_RML"        ,	   0x1070100c82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP7_IP4_RML"        ,	   0x1070100e82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP8_IP4_RML"        ,	   0x1070101082400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP9_IP4_RML"        ,	   0x1070101282400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP10_IP4_RML"       ,	   0x1070101482400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP11_IP4_RML"       ,	   0x1070101682400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP12_IP4_RML"       ,	   0x1070101882400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP13_IP4_RML"       ,	   0x1070101a82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP14_IP4_RML"       ,	   0x1070101c82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP15_IP4_RML"       ,	   0x1070101e82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP16_IP4_RML"       ,	   0x1070102082400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP17_IP4_RML"       ,	   0x1070102282400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP18_IP4_RML"       ,	   0x1070102482400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP19_IP4_RML"       ,	   0x1070102682400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP20_IP4_RML"       ,	   0x1070102882400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP21_IP4_RML"       ,	   0x1070102a82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP22_IP4_RML"       ,	   0x1070102c82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP23_IP4_RML"       ,	   0x1070102e82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP24_IP4_RML"       ,	   0x1070103082400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP25_IP4_RML"       ,	   0x1070103282400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP26_IP4_RML"       ,	   0x1070103482400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP27_IP4_RML"       ,	   0x1070103682400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP28_IP4_RML"       ,	   0x1070103882400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP29_IP4_RML"       ,	   0x1070103a82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP30_IP4_RML"       ,	   0x1070103c82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP31_IP4_RML"       ,	   0x1070103e82400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"CIU2_SRC_PP0_IP4_WDOG"       ,	   0x1070100081400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP1_IP4_WDOG"       ,	   0x1070100281400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP2_IP4_WDOG"       ,	   0x1070100481400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP3_IP4_WDOG"       ,	   0x1070100681400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP4_IP4_WDOG"       ,	   0x1070100881400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP5_IP4_WDOG"       ,	   0x1070100a81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP6_IP4_WDOG"       ,	   0x1070100c81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP7_IP4_WDOG"       ,	   0x1070100e81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP8_IP4_WDOG"       ,	   0x1070101081400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP9_IP4_WDOG"       ,	   0x1070101281400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP10_IP4_WDOG"      ,	   0x1070101481400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP11_IP4_WDOG"      ,	   0x1070101681400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP12_IP4_WDOG"      ,	   0x1070101881400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP13_IP4_WDOG"      ,	   0x1070101a81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP14_IP4_WDOG"      ,	   0x1070101c81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP15_IP4_WDOG"      ,	   0x1070101e81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP16_IP4_WDOG"      ,	   0x1070102081400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP17_IP4_WDOG"      ,	   0x1070102281400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP18_IP4_WDOG"      ,	   0x1070102481400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP19_IP4_WDOG"      ,	   0x1070102681400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP20_IP4_WDOG"      ,	   0x1070102881400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP21_IP4_WDOG"      ,	   0x1070102a81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP22_IP4_WDOG"      ,	   0x1070102c81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP23_IP4_WDOG"      ,	   0x1070102e81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP24_IP4_WDOG"      ,	   0x1070103081400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP25_IP4_WDOG"      ,	   0x1070103281400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP26_IP4_WDOG"      ,	   0x1070103481400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP27_IP4_WDOG"      ,	   0x1070103681400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP28_IP4_WDOG"      ,	   0x1070103881400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP29_IP4_WDOG"      ,	   0x1070103a81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP30_IP4_WDOG"      ,	   0x1070103c81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP31_IP4_WDOG"      ,	   0x1070103e81400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"CIU2_SRC_PP0_IP4_WRKQ"       ,	   0x1070100080400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP1_IP4_WRKQ"       ,	   0x1070100280400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP2_IP4_WRKQ"       ,	   0x1070100480400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP3_IP4_WRKQ"       ,	   0x1070100680400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP4_IP4_WRKQ"       ,	   0x1070100880400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP5_IP4_WRKQ"       ,	   0x1070100a80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP6_IP4_WRKQ"       ,	   0x1070100c80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP7_IP4_WRKQ"       ,	   0x1070100e80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP8_IP4_WRKQ"       ,	   0x1070101080400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP9_IP4_WRKQ"       ,	   0x1070101280400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP10_IP4_WRKQ"      ,	   0x1070101480400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP11_IP4_WRKQ"      ,	   0x1070101680400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP12_IP4_WRKQ"      ,	   0x1070101880400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP13_IP4_WRKQ"      ,	   0x1070101a80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP14_IP4_WRKQ"      ,	   0x1070101c80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP15_IP4_WRKQ"      ,	   0x1070101e80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP16_IP4_WRKQ"      ,	   0x1070102080400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP17_IP4_WRKQ"      ,	   0x1070102280400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP18_IP4_WRKQ"      ,	   0x1070102480400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP19_IP4_WRKQ"      ,	   0x1070102680400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP20_IP4_WRKQ"      ,	   0x1070102880400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP21_IP4_WRKQ"      ,	   0x1070102a80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP22_IP4_WRKQ"      ,	   0x1070102c80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP23_IP4_WRKQ"      ,	   0x1070102e80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP24_IP4_WRKQ"      ,	   0x1070103080400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP25_IP4_WRKQ"      ,	   0x1070103280400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP26_IP4_WRKQ"      ,	   0x1070103480400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP27_IP4_WRKQ"      ,	   0x1070103680400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP28_IP4_WRKQ"      ,	   0x1070103880400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP29_IP4_WRKQ"      ,	   0x1070103a80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP30_IP4_WRKQ"      ,	   0x1070103c80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SRC_PP31_IP4_WRKQ"      ,	   0x1070103e80400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"CIU2_SUM_IO0_INT"            ,	   0x1070100000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"CIU2_SUM_IO1_INT"            ,	   0x1070100000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"CIU2_SUM_PP0_IP2"            ,	   0x1070100000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP1_IP2"            ,	   0x1070100000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP2_IP2"            ,	   0x1070100000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP3_IP2"            ,	   0x1070100000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP4_IP2"            ,	   0x1070100000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP5_IP2"            ,	   0x1070100000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP6_IP2"            ,	   0x1070100000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP7_IP2"            ,	   0x1070100000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP8_IP2"            ,	   0x1070100000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP9_IP2"            ,	   0x1070100000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP10_IP2"           ,	   0x1070100000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP11_IP2"           ,	   0x1070100000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP12_IP2"           ,	   0x1070100000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP13_IP2"           ,	   0x1070100000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP14_IP2"           ,	   0x1070100000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP15_IP2"           ,	   0x1070100000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP16_IP2"           ,	   0x1070100000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP17_IP2"           ,	   0x1070100000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP18_IP2"           ,	   0x1070100000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP19_IP2"           ,	   0x1070100000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP20_IP2"           ,	   0x10701000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP21_IP2"           ,	   0x10701000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP22_IP2"           ,	   0x10701000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP23_IP2"           ,	   0x10701000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP24_IP2"           ,	   0x10701000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP25_IP2"           ,	   0x10701000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP26_IP2"           ,	   0x10701000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP27_IP2"           ,	   0x10701000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP28_IP2"           ,	   0x10701000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP29_IP2"           ,	   0x10701000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP30_IP2"           ,	   0x10701000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP31_IP2"           ,	   0x10701000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"CIU2_SUM_PP0_IP3"            ,	   0x1070100000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP1_IP3"            ,	   0x1070100000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP2_IP3"            ,	   0x1070100000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP3_IP3"            ,	   0x1070100000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP4_IP3"            ,	   0x1070100000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP5_IP3"            ,	   0x1070100000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP6_IP3"            ,	   0x1070100000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP7_IP3"            ,	   0x1070100000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP8_IP3"            ,	   0x1070100000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP9_IP3"            ,	   0x1070100000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP10_IP3"           ,	   0x1070100000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP11_IP3"           ,	   0x1070100000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP12_IP3"           ,	   0x1070100000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP13_IP3"           ,	   0x1070100000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP14_IP3"           ,	   0x1070100000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP15_IP3"           ,	   0x1070100000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP16_IP3"           ,	   0x1070100000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP17_IP3"           ,	   0x1070100000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP18_IP3"           ,	   0x1070100000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP19_IP3"           ,	   0x1070100000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP20_IP3"           ,	   0x10701000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP21_IP3"           ,	   0x10701000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP22_IP3"           ,	   0x10701000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP23_IP3"           ,	   0x10701000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP24_IP3"           ,	   0x10701000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP25_IP3"           ,	   0x10701000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP26_IP3"           ,	   0x10701000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP27_IP3"           ,	   0x10701000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP28_IP3"           ,	   0x10701000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP29_IP3"           ,	   0x10701000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP30_IP3"           ,	   0x10701000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP31_IP3"           ,	   0x10701000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"CIU2_SUM_PP0_IP4"            ,	   0x1070100000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP1_IP4"            ,	   0x1070100000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP2_IP4"            ,	   0x1070100000410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP3_IP4"            ,	   0x1070100000418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP4_IP4"            ,	   0x1070100000420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP5_IP4"            ,	   0x1070100000428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP6_IP4"            ,	   0x1070100000430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP7_IP4"            ,	   0x1070100000438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP8_IP4"            ,	   0x1070100000440ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP9_IP4"            ,	   0x1070100000448ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP10_IP4"           ,	   0x1070100000450ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP11_IP4"           ,	   0x1070100000458ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP12_IP4"           ,	   0x1070100000460ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP13_IP4"           ,	   0x1070100000468ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP14_IP4"           ,	   0x1070100000470ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP15_IP4"           ,	   0x1070100000478ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP16_IP4"           ,	   0x1070100000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP17_IP4"           ,	   0x1070100000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP18_IP4"           ,	   0x1070100000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP19_IP4"           ,	   0x1070100000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP20_IP4"           ,	   0x10701000004a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP21_IP4"           ,	   0x10701000004a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP22_IP4"           ,	   0x10701000004b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP23_IP4"           ,	   0x10701000004b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP24_IP4"           ,	   0x10701000004c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP25_IP4"           ,	   0x10701000004c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP26_IP4"           ,	   0x10701000004d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP27_IP4"           ,	   0x10701000004d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP28_IP4"           ,	   0x10701000004e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP29_IP4"           ,	   0x10701000004e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP30_IP4"           ,	   0x10701000004f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU2_SUM_PP31_IP4"           ,	   0x10701000004f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	265},
+	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	266},
+	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	267},
+	{"CIU_GSTOP"                   ,	   0x1070000000710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
+	{"CIU_INT_DBG_SEL"             ,	   0x10700000007d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	269},
+	{"CIU_MBOX_CLR0"               ,	   0x1070100100600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR1"               ,	   0x1070100100608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR2"               ,	   0x1070100100610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR3"               ,	   0x1070100100618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR4"               ,	   0x1070100100620ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR5"               ,	   0x1070100100628ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR6"               ,	   0x1070100100630ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR7"               ,	   0x1070100100638ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR8"               ,	   0x1070100100640ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR9"               ,	   0x1070100100648ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR10"              ,	   0x1070100100650ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR11"              ,	   0x1070100100658ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR12"              ,	   0x1070100100660ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR13"              ,	   0x1070100100668ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR14"              ,	   0x1070100100670ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR15"              ,	   0x1070100100678ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR16"              ,	   0x1070100100680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR17"              ,	   0x1070100100688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR18"              ,	   0x1070100100690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR19"              ,	   0x1070100100698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR20"              ,	   0x10701001006a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR21"              ,	   0x10701001006a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR22"              ,	   0x10701001006b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR23"              ,	   0x10701001006b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR24"              ,	   0x10701001006c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR25"              ,	   0x10701001006c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR26"              ,	   0x10701001006d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR27"              ,	   0x10701001006d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR28"              ,	   0x10701001006e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR29"              ,	   0x10701001006e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR30"              ,	   0x10701001006f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_CLR31"              ,	   0x10701001006f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"CIU_MBOX_SET0"               ,	   0x1070100100400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET1"               ,	   0x1070100100408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET2"               ,	   0x1070100100410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET3"               ,	   0x1070100100418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET4"               ,	   0x1070100100420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET5"               ,	   0x1070100100428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET6"               ,	   0x1070100100430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET7"               ,	   0x1070100100438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET8"               ,	   0x1070100100440ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET9"               ,	   0x1070100100448ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET10"              ,	   0x1070100100450ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET11"              ,	   0x1070100100458ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET12"              ,	   0x1070100100460ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET13"              ,	   0x1070100100468ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET14"              ,	   0x1070100100470ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET15"              ,	   0x1070100100478ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET16"              ,	   0x1070100100480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET17"              ,	   0x1070100100488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET18"              ,	   0x1070100100490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET19"              ,	   0x1070100100498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET20"              ,	   0x10701001004a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET21"              ,	   0x10701001004a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET22"              ,	   0x10701001004b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET23"              ,	   0x10701001004b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET24"              ,	   0x10701001004c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET25"              ,	   0x10701001004c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET26"              ,	   0x10701001004d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET27"              ,	   0x10701001004d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET28"              ,	   0x10701001004e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET29"              ,	   0x10701001004e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET30"              ,	   0x10701001004f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_MBOX_SET31"              ,	   0x10701001004f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"CIU_NMI"                     ,	   0x1070000000718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	272},
+	{"CIU_PCI_INTA"                ,	   0x1070000000750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	273},
+	{"CIU_PP_BIST_STAT"            ,	   0x10700000007e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	274},
+	{"CIU_PP_DBG"                  ,	   0x1070000000708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	275},
+	{"CIU_PP_POKE0"                ,	   0x1070100100200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE1"                ,	   0x1070100100208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE2"                ,	   0x1070100100210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE3"                ,	   0x1070100100218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE4"                ,	   0x1070100100220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE5"                ,	   0x1070100100228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE6"                ,	   0x1070100100230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE7"                ,	   0x1070100100238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE8"                ,	   0x1070100100240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE9"                ,	   0x1070100100248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE10"               ,	   0x1070100100250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE11"               ,	   0x1070100100258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE12"               ,	   0x1070100100260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE13"               ,	   0x1070100100268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE14"               ,	   0x1070100100270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE15"               ,	   0x1070100100278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE16"               ,	   0x1070100100280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE17"               ,	   0x1070100100288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE18"               ,	   0x1070100100290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE19"               ,	   0x1070100100298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE20"               ,	   0x10701001002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE21"               ,	   0x10701001002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE22"               ,	   0x10701001002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE23"               ,	   0x10701001002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE24"               ,	   0x10701001002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE25"               ,	   0x10701001002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE26"               ,	   0x10701001002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE27"               ,	   0x10701001002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE28"               ,	   0x10701001002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE29"               ,	   0x10701001002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE30"               ,	   0x10701001002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_POKE31"               ,	   0x10701001002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
+	{"CIU_QLM0"                    ,	   0x1070000000780ull,	CVMX_CSR_DB_TYPE_NCB,	64,	278},
+	{"CIU_QLM1"                    ,	   0x1070000000788ull,	CVMX_CSR_DB_TYPE_NCB,	64,	279},
+	{"CIU_QLM2"                    ,	   0x1070000000790ull,	CVMX_CSR_DB_TYPE_NCB,	64,	280},
+	{"CIU_QLM3"                    ,	   0x1070000000798ull,	CVMX_CSR_DB_TYPE_NCB,	64,	281},
+	{"CIU_QLM4"                    ,	   0x10700000007a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	282},
+	{"CIU_QLM_JTGC"                ,	   0x1070000000768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	283},
+	{"CIU_QLM_JTGD"                ,	   0x1070000000770ull,	CVMX_CSR_DB_TYPE_NCB,	64,	284},
+	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	285},
+	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"CIU_SOFT_PRST1"              ,	   0x1070000000758ull,	CVMX_CSR_DB_TYPE_NCB,	64,	287},
+	{"CIU_SOFT_RST"                ,	   0x1070000000740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	288},
+	{"CIU_TIM0"                    ,	   0x1070000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"CIU_TIM1"                    ,	   0x1070000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"CIU_WDOG0"                   ,	   0x1070100100000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG1"                   ,	   0x1070100100008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG2"                   ,	   0x1070100100010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG3"                   ,	   0x1070100100018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG4"                   ,	   0x1070100100020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG5"                   ,	   0x1070100100028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG6"                   ,	   0x1070100100030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG7"                   ,	   0x1070100100038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG8"                   ,	   0x1070100100040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG9"                   ,	   0x1070100100048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG10"                  ,	   0x1070100100050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG11"                  ,	   0x1070100100058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG12"                  ,	   0x1070100100060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG13"                  ,	   0x1070100100068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG14"                  ,	   0x1070100100070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG15"                  ,	   0x1070100100078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG16"                  ,	   0x1070100100080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG17"                  ,	   0x1070100100088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG18"                  ,	   0x1070100100090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG19"                  ,	   0x1070100100098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG20"                  ,	   0x10701001000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG21"                  ,	   0x10701001000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG22"                  ,	   0x10701001000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG23"                  ,	   0x10701001000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG24"                  ,	   0x10701001000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG25"                  ,	   0x10701001000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG26"                  ,	   0x10701001000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG27"                  ,	   0x10701001000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG28"                  ,	   0x10701001000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG29"                  ,	   0x10701001000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG30"                  ,	   0x10701001000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"CIU_WDOG31"                  ,	   0x10701001000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"DFA_BIST0"                   ,	   0x11800370007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"DFA_BIST1"                   ,	   0x11800370007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"DFA_CONFIG"                  ,	   0x1180037000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"DFA_CONTROL"                 ,	   0x1180037000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"DFA_DBELL"                   ,	   0x1370000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"DFA_DEBUG0"                  ,	   0x1180037000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"DFA_DEBUG1"                  ,	   0x1180037000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"DFA_DEBUG2"                  ,	   0x1180037000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"DFA_DEBUG3"                  ,	   0x1180037000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"DFA_DIFCTL"                  ,	   0x1370600000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	300},
+	{"DFA_DIFRDPTR"                ,	   0x1370200000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	301},
+	{"DFA_DTCFADR"                 ,	   0x1180037000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"DFA_ERROR"                   ,	   0x1180037000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"DFA_INTMSK"                  ,	   0x1180037000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"DFA_MEMHIDAT"                ,	   0x1370700000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	305},
+	{"DFA_PFC0_CNT"                ,	   0x1180037000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"DFA_PFC0_CTL"                ,	   0x1180037000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"DFA_PFC1_CNT"                ,	   0x11800370000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"DFA_PFC1_CTL"                ,	   0x1180037000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"DFA_PFC2_CNT"                ,	   0x11800370000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"DFA_PFC2_CTL"                ,	   0x11800370000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"DFA_PFC3_CNT"                ,	   0x11800370000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"DFA_PFC3_CTL"                ,	   0x11800370000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"DFA_PFC_GCTL"                ,	   0x1180037000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"DPI_BIST_STATUS"             ,	   0x1df0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	315},
+	{"DPI_CTL"                     ,	   0x1df0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	316},
+	{"DPI_DMA0_COUNTS"             ,	   0x1df0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"DPI_DMA1_COUNTS"             ,	   0x1df0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"DPI_DMA2_COUNTS"             ,	   0x1df0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"DPI_DMA3_COUNTS"             ,	   0x1df0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"DPI_DMA4_COUNTS"             ,	   0x1df0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"DPI_DMA5_COUNTS"             ,	   0x1df0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"DPI_DMA6_COUNTS"             ,	   0x1df0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"DPI_DMA7_COUNTS"             ,	   0x1df0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"DPI_DMA0_DBELL"              ,	   0x1df0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"DPI_DMA1_DBELL"              ,	   0x1df0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"DPI_DMA2_DBELL"              ,	   0x1df0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"DPI_DMA3_DBELL"              ,	   0x1df0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"DPI_DMA4_DBELL"              ,	   0x1df0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"DPI_DMA5_DBELL"              ,	   0x1df0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"DPI_DMA6_DBELL"              ,	   0x1df0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"DPI_DMA7_DBELL"              ,	   0x1df0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"DPI_DMA0_ERR_RSP_STATUS"     ,	   0x1df0000000a80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"DPI_DMA1_ERR_RSP_STATUS"     ,	   0x1df0000000a88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"DPI_DMA2_ERR_RSP_STATUS"     ,	   0x1df0000000a90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"DPI_DMA3_ERR_RSP_STATUS"     ,	   0x1df0000000a98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"DPI_DMA4_ERR_RSP_STATUS"     ,	   0x1df0000000aa0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"DPI_DMA5_ERR_RSP_STATUS"     ,	   0x1df0000000aa8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"DPI_DMA6_ERR_RSP_STATUS"     ,	   0x1df0000000ab0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"DPI_DMA7_ERR_RSP_STATUS"     ,	   0x1df0000000ab8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"DPI_DMA0_IBUFF_SADDR"        ,	   0x1df0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"DPI_DMA1_IBUFF_SADDR"        ,	   0x1df0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"DPI_DMA2_IBUFF_SADDR"        ,	   0x1df0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"DPI_DMA3_IBUFF_SADDR"        ,	   0x1df0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"DPI_DMA4_IBUFF_SADDR"        ,	   0x1df00000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"DPI_DMA5_IBUFF_SADDR"        ,	   0x1df00000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"DPI_DMA6_IBUFF_SADDR"        ,	   0x1df00000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"DPI_DMA7_IBUFF_SADDR"        ,	   0x1df00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"DPI_DMA0_IFLIGHT"            ,	   0x1df0000000a00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"DPI_DMA1_IFLIGHT"            ,	   0x1df0000000a08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"DPI_DMA2_IFLIGHT"            ,	   0x1df0000000a10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"DPI_DMA3_IFLIGHT"            ,	   0x1df0000000a18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"DPI_DMA4_IFLIGHT"            ,	   0x1df0000000a20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"DPI_DMA5_IFLIGHT"            ,	   0x1df0000000a28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"DPI_DMA6_IFLIGHT"            ,	   0x1df0000000a30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"DPI_DMA7_IFLIGHT"            ,	   0x1df0000000a38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"DPI_DMA0_NADDR"              ,	   0x1df0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"DPI_DMA1_NADDR"              ,	   0x1df0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"DPI_DMA2_NADDR"              ,	   0x1df0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"DPI_DMA3_NADDR"              ,	   0x1df0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"DPI_DMA4_NADDR"              ,	   0x1df00000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"DPI_DMA5_NADDR"              ,	   0x1df00000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"DPI_DMA6_NADDR"              ,	   0x1df00000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"DPI_DMA7_NADDR"              ,	   0x1df00000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"DPI_DMA0_REQBNK0"            ,	   0x1df0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"DPI_DMA1_REQBNK0"            ,	   0x1df0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"DPI_DMA2_REQBNK0"            ,	   0x1df0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"DPI_DMA3_REQBNK0"            ,	   0x1df0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"DPI_DMA4_REQBNK0"            ,	   0x1df0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"DPI_DMA5_REQBNK0"            ,	   0x1df0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"DPI_DMA6_REQBNK0"            ,	   0x1df0000000430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"DPI_DMA7_REQBNK0"            ,	   0x1df0000000438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"DPI_DMA0_REQBNK1"            ,	   0x1df0000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"DPI_DMA1_REQBNK1"            ,	   0x1df0000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"DPI_DMA2_REQBNK1"            ,	   0x1df0000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"DPI_DMA3_REQBNK1"            ,	   0x1df0000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"DPI_DMA4_REQBNK1"            ,	   0x1df00000004a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"DPI_DMA5_REQBNK1"            ,	   0x1df00000004a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"DPI_DMA6_REQBNK1"            ,	   0x1df00000004b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"DPI_DMA7_REQBNK1"            ,	   0x1df00000004b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"DPI_DMA_CONTROL"             ,	   0x1df0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	325},
+	{"DPI_DMA_ENG0_EN"             ,	   0x1df0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"DPI_DMA_ENG1_EN"             ,	   0x1df0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"DPI_DMA_ENG2_EN"             ,	   0x1df0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"DPI_DMA_ENG3_EN"             ,	   0x1df0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"DPI_DMA_ENG4_EN"             ,	   0x1df00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"DPI_DMA_ENG5_EN"             ,	   0x1df00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"DPI_DMA_PP0_CNT"             ,	   0x1df0000000b00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP1_CNT"             ,	   0x1df0000000b08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP2_CNT"             ,	   0x1df0000000b10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP3_CNT"             ,	   0x1df0000000b18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP4_CNT"             ,	   0x1df0000000b20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP5_CNT"             ,	   0x1df0000000b28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP6_CNT"             ,	   0x1df0000000b30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP7_CNT"             ,	   0x1df0000000b38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP8_CNT"             ,	   0x1df0000000b40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP9_CNT"             ,	   0x1df0000000b48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP10_CNT"            ,	   0x1df0000000b50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP11_CNT"            ,	   0x1df0000000b58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP12_CNT"            ,	   0x1df0000000b60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP13_CNT"            ,	   0x1df0000000b68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP14_CNT"            ,	   0x1df0000000b70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP15_CNT"            ,	   0x1df0000000b78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP16_CNT"            ,	   0x1df0000000b80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP17_CNT"            ,	   0x1df0000000b88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP18_CNT"            ,	   0x1df0000000b90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP19_CNT"            ,	   0x1df0000000b98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP20_CNT"            ,	   0x1df0000000ba0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP21_CNT"            ,	   0x1df0000000ba8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP22_CNT"            ,	   0x1df0000000bb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP23_CNT"            ,	   0x1df0000000bb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP24_CNT"            ,	   0x1df0000000bc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP25_CNT"            ,	   0x1df0000000bc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP26_CNT"            ,	   0x1df0000000bd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP27_CNT"            ,	   0x1df0000000bd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP28_CNT"            ,	   0x1df0000000be0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP29_CNT"            ,	   0x1df0000000be8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP30_CNT"            ,	   0x1df0000000bf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_DMA_PP31_CNT"            ,	   0x1df0000000bf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"DPI_ENG0_BUF"                ,	   0x1df0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
+	{"DPI_ENG1_BUF"                ,	   0x1df0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
+	{"DPI_ENG2_BUF"                ,	   0x1df0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
+	{"DPI_ENG3_BUF"                ,	   0x1df0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
+	{"DPI_ENG4_BUF"                ,	   0x1df00000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
+	{"DPI_ENG5_BUF"                ,	   0x1df00000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
+	{"DPI_INFO_REG"                ,	   0x1df0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
+	{"DPI_INT_EN"                  ,	   0x1df0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	330},
+	{"DPI_INT_REG"                 ,	   0x1df0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	331},
+	{"DPI_NCB0_CFG"                ,	   0x1df0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
+	{"DPI_PINT_INFO"               ,	   0x1df0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	333},
+	{"DPI_PKT_ERR_RSP"             ,	   0x1df0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"DPI_REQ_ERR_RSP"             ,	   0x1df0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"DPI_REQ_ERR_RSP_EN"          ,	   0x1df0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"DPI_REQ_ERR_RST"             ,	   0x1df0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"DPI_REQ_ERR_RST_EN"          ,	   0x1df0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"DPI_REQ_ERR_SKIP_COMP"       ,	   0x1df0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"DPI_REQ_GBL_EN"              ,	   0x1df0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"DPI_SLI_PRT0_CFG"            ,	   0x1df0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"DPI_SLI_PRT1_CFG"            ,	   0x1df0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"DPI_SLI_PRT0_ERR"            ,	   0x1df0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"DPI_SLI_PRT1_ERR"            ,	   0x1df0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"DPI_SLI_PRT0_ERR_INFO"       ,	   0x1df0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"DPI_SLI_PRT1_ERR_INFO"       ,	   0x1df0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"FPA_ADDR_RANGE_ERROR"        ,	   0x1180028000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"FPA_FPF3_MARKS"              ,	   0x1180028000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"FPA_FPF4_MARKS"              ,	   0x1180028000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"FPA_FPF5_MARKS"              ,	   0x1180028000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"FPA_FPF6_MARKS"              ,	   0x1180028000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"FPA_FPF7_MARKS"              ,	   0x1180028000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"FPA_FPF1_SIZE"               ,	   0x1180028000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
+	{"FPA_FPF2_SIZE"               ,	   0x1180028000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
+	{"FPA_FPF3_SIZE"               ,	   0x1180028000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
+	{"FPA_FPF4_SIZE"               ,	   0x1180028000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
+	{"FPA_FPF5_SIZE"               ,	   0x1180028000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
+	{"FPA_FPF6_SIZE"               ,	   0x1180028000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
+	{"FPA_FPF7_SIZE"               ,	   0x1180028000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
+	{"FPA_FPF0_MARKS"              ,	   0x1180028000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"FPA_FPF0_SIZE"               ,	   0x1180028000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"FPA_FPF8_MARKS"              ,	   0x1180028000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
+	{"FPA_FPF8_SIZE"               ,	   0x1180028000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
+	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	353},
+	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"FPA_PACKET_THRESHOLD"        ,	   0x1180028000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"FPA_POOL0_END_ADDR"          ,	   0x1180028000358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"FPA_POOL1_END_ADDR"          ,	   0x1180028000360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"FPA_POOL2_END_ADDR"          ,	   0x1180028000368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"FPA_POOL3_END_ADDR"          ,	   0x1180028000370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"FPA_POOL4_END_ADDR"          ,	   0x1180028000378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"FPA_POOL5_END_ADDR"          ,	   0x1180028000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"FPA_POOL6_END_ADDR"          ,	   0x1180028000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"FPA_POOL7_END_ADDR"          ,	   0x1180028000390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"FPA_POOL8_END_ADDR"          ,	   0x1180028000398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"FPA_POOL0_START_ADDR"        ,	   0x1180028000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"FPA_POOL1_START_ADDR"        ,	   0x1180028000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"FPA_POOL2_START_ADDR"        ,	   0x1180028000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"FPA_POOL3_START_ADDR"        ,	   0x1180028000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"FPA_POOL4_START_ADDR"        ,	   0x1180028000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"FPA_POOL5_START_ADDR"        ,	   0x1180028000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"FPA_POOL6_START_ADDR"        ,	   0x1180028000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"FPA_POOL7_START_ADDR"        ,	   0x1180028000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"FPA_POOL8_START_ADDR"        ,	   0x1180028000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"FPA_POOL0_THRESHOLD"         ,	   0x1180028000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"FPA_POOL1_THRESHOLD"         ,	   0x1180028000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"FPA_POOL2_THRESHOLD"         ,	   0x1180028000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"FPA_POOL3_THRESHOLD"         ,	   0x1180028000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"FPA_POOL4_THRESHOLD"         ,	   0x1180028000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"FPA_POOL5_THRESHOLD"         ,	   0x1180028000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"FPA_POOL6_THRESHOLD"         ,	   0x1180028000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"FPA_POOL7_THRESHOLD"         ,	   0x1180028000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"FPA_POOL8_THRESHOLD"         ,	   0x1180028000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"FPA_QUE8_AVAILABLE"          ,	   0x11800280000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"FPA_QUE5_PAGE_INDEX"         ,	   0x1180028000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"FPA_QUE6_PAGE_INDEX"         ,	   0x1180028000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"FPA_QUE8_PAGE_INDEX"         ,	   0x1180028000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	361},
+	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	362},
+	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"FPA_WQE_THRESHOLD"           ,	   0x1180028000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
+	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX1_BAD_REG"                ,	   0x1180009000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX2_BAD_REG"                ,	   0x118000a000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX3_BAD_REG"                ,	   0x118000b000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX4_BAD_REG"                ,	   0x118000c000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"GMX1_BIST"                   ,	   0x1180009000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"GMX2_BIST"                   ,	   0x118000a000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"GMX3_BIST"                   ,	   0x118000b000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"GMX4_BIST"                   ,	   0x118000c000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"GMX0_BPID_MAP000"            ,	   0x1180008000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_BPID_MAP001"            ,	   0x1180008000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_BPID_MAP002"            ,	   0x1180008000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_BPID_MAP003"            ,	   0x1180008000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_BPID_MAP004"            ,	   0x11800080006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_BPID_MAP005"            ,	   0x11800080006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_BPID_MAP006"            ,	   0x11800080006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_BPID_MAP007"            ,	   0x11800080006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_BPID_MAP008"            ,	   0x11800080006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_BPID_MAP009"            ,	   0x11800080006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_BPID_MAP010"            ,	   0x11800080006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_BPID_MAP011"            ,	   0x11800080006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_BPID_MAP012"            ,	   0x11800080006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_BPID_MAP013"            ,	   0x11800080006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_BPID_MAP014"            ,	   0x11800080006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_BPID_MAP015"            ,	   0x11800080006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX1_BPID_MAP000"            ,	   0x1180009000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX1_BPID_MAP001"            ,	   0x1180009000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX1_BPID_MAP002"            ,	   0x1180009000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX1_BPID_MAP003"            ,	   0x1180009000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX1_BPID_MAP004"            ,	   0x11800090006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX1_BPID_MAP005"            ,	   0x11800090006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX1_BPID_MAP006"            ,	   0x11800090006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX1_BPID_MAP007"            ,	   0x11800090006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX1_BPID_MAP008"            ,	   0x11800090006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX1_BPID_MAP009"            ,	   0x11800090006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX1_BPID_MAP010"            ,	   0x11800090006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX1_BPID_MAP011"            ,	   0x11800090006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX1_BPID_MAP012"            ,	   0x11800090006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX1_BPID_MAP013"            ,	   0x11800090006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX1_BPID_MAP014"            ,	   0x11800090006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX1_BPID_MAP015"            ,	   0x11800090006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX2_BPID_MAP000"            ,	   0x118000a000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX2_BPID_MAP001"            ,	   0x118000a000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX2_BPID_MAP002"            ,	   0x118000a000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX2_BPID_MAP003"            ,	   0x118000a000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX2_BPID_MAP004"            ,	   0x118000a0006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX2_BPID_MAP005"            ,	   0x118000a0006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX2_BPID_MAP006"            ,	   0x118000a0006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX2_BPID_MAP007"            ,	   0x118000a0006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX2_BPID_MAP008"            ,	   0x118000a0006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX2_BPID_MAP009"            ,	   0x118000a0006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX2_BPID_MAP010"            ,	   0x118000a0006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX2_BPID_MAP011"            ,	   0x118000a0006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX2_BPID_MAP012"            ,	   0x118000a0006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX2_BPID_MAP013"            ,	   0x118000a0006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX2_BPID_MAP014"            ,	   0x118000a0006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX2_BPID_MAP015"            ,	   0x118000a0006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX3_BPID_MAP000"            ,	   0x118000b000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX3_BPID_MAP001"            ,	   0x118000b000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX3_BPID_MAP002"            ,	   0x118000b000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX3_BPID_MAP003"            ,	   0x118000b000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX3_BPID_MAP004"            ,	   0x118000b0006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX3_BPID_MAP005"            ,	   0x118000b0006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX3_BPID_MAP006"            ,	   0x118000b0006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX3_BPID_MAP007"            ,	   0x118000b0006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX3_BPID_MAP008"            ,	   0x118000b0006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX3_BPID_MAP009"            ,	   0x118000b0006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX3_BPID_MAP010"            ,	   0x118000b0006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX3_BPID_MAP011"            ,	   0x118000b0006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX3_BPID_MAP012"            ,	   0x118000b0006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX3_BPID_MAP013"            ,	   0x118000b0006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX3_BPID_MAP014"            ,	   0x118000b0006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX3_BPID_MAP015"            ,	   0x118000b0006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX4_BPID_MAP000"            ,	   0x118000c000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX4_BPID_MAP001"            ,	   0x118000c000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX4_BPID_MAP002"            ,	   0x118000c000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX4_BPID_MAP003"            ,	   0x118000c000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX4_BPID_MAP004"            ,	   0x118000c0006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX4_BPID_MAP005"            ,	   0x118000c0006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX4_BPID_MAP006"            ,	   0x118000c0006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX4_BPID_MAP007"            ,	   0x118000c0006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX4_BPID_MAP008"            ,	   0x118000c0006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX4_BPID_MAP009"            ,	   0x118000c0006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX4_BPID_MAP010"            ,	   0x118000c0006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX4_BPID_MAP011"            ,	   0x118000c0006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX4_BPID_MAP012"            ,	   0x118000c0006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX4_BPID_MAP013"            ,	   0x118000c0006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX4_BPID_MAP014"            ,	   0x118000c0006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX4_BPID_MAP015"            ,	   0x118000c0006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_BPID_MSK"               ,	   0x1180008000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"GMX1_BPID_MSK"               ,	   0x1180009000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"GMX2_BPID_MSK"               ,	   0x118000a000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"GMX3_BPID_MSK"               ,	   0x118000b000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"GMX4_BPID_MSK"               ,	   0x118000c000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"GMX0_CLK_EN"                 ,	   0x11800080007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"GMX1_CLK_EN"                 ,	   0x11800090007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"GMX2_CLK_EN"                 ,	   0x118000a0007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"GMX3_CLK_EN"                 ,	   0x118000b0007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"GMX4_CLK_EN"                 ,	   0x118000c0007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"GMX0_EBP_DIS"                ,	   0x1180008000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"GMX1_EBP_DIS"                ,	   0x1180009000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"GMX2_EBP_DIS"                ,	   0x118000a000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"GMX3_EBP_DIS"                ,	   0x118000b000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"GMX4_EBP_DIS"                ,	   0x118000c000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"GMX0_EBP_MSK"                ,	   0x1180008000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"GMX1_EBP_MSK"                ,	   0x1180009000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"GMX2_EBP_MSK"                ,	   0x118000a000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"GMX3_EBP_MSK"                ,	   0x118000b000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"GMX4_EBP_MSK"                ,	   0x118000c000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"GMX0_HG2_CONTROL"            ,	   0x1180008000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"GMX1_HG2_CONTROL"            ,	   0x1180009000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"GMX2_HG2_CONTROL"            ,	   0x118000a000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"GMX3_HG2_CONTROL"            ,	   0x118000b000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"GMX4_HG2_CONTROL"            ,	   0x118000c000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"GMX0_INF_MODE"               ,	   0x11800080007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"GMX1_INF_MODE"               ,	   0x11800090007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"GMX2_INF_MODE"               ,	   0x118000a0007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"GMX3_INF_MODE"               ,	   0x118000b0007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"GMX4_INF_MODE"               ,	   0x118000c0007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"GMX1_NXA_ADR"                ,	   0x1180009000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"GMX2_NXA_ADR"                ,	   0x118000a000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"GMX3_NXA_ADR"                ,	   0x118000b000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"GMX4_NXA_ADR"                ,	   0x118000c000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"GMX0_PIPE_STATUS"            ,	   0x1180008000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX1_PIPE_STATUS"            ,	   0x1180009000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX2_PIPE_STATUS"            ,	   0x118000a000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX3_PIPE_STATUS"            ,	   0x118000b000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX4_PIPE_STATUS"            ,	   0x118000c000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX0_PRT000_CBFC_CTL"        ,	   0x1180008000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX1_PRT000_CBFC_CTL"        ,	   0x1180009000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX2_PRT000_CBFC_CTL"        ,	   0x118000a000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX3_PRT000_CBFC_CTL"        ,	   0x118000b000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX4_PRT000_CBFC_CTL"        ,	   0x118000c000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX0_PRT002_CFG"             ,	   0x1180008001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX0_PRT003_CFG"             ,	   0x1180008001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX1_PRT000_CFG"             ,	   0x1180009000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX1_PRT001_CFG"             ,	   0x1180009000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX1_PRT002_CFG"             ,	   0x1180009001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX1_PRT003_CFG"             ,	   0x1180009001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX2_PRT000_CFG"             ,	   0x118000a000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX2_PRT001_CFG"             ,	   0x118000a000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX2_PRT002_CFG"             ,	   0x118000a001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX2_PRT003_CFG"             ,	   0x118000a001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX3_PRT000_CFG"             ,	   0x118000b000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX3_PRT001_CFG"             ,	   0x118000b000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX3_PRT002_CFG"             ,	   0x118000b001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX3_PRT003_CFG"             ,	   0x118000b001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX4_PRT000_CFG"             ,	   0x118000c000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX4_PRT001_CFG"             ,	   0x118000c000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX4_PRT002_CFG"             ,	   0x118000c001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX4_PRT003_CFG"             ,	   0x118000c001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX0_RX000_ADR_CAM0"         ,	   0x1180008000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX0_RX001_ADR_CAM0"         ,	   0x1180008000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX0_RX002_ADR_CAM0"         ,	   0x1180008001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX0_RX003_ADR_CAM0"         ,	   0x1180008001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX1_RX000_ADR_CAM0"         ,	   0x1180009000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX1_RX001_ADR_CAM0"         ,	   0x1180009000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX1_RX002_ADR_CAM0"         ,	   0x1180009001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX1_RX003_ADR_CAM0"         ,	   0x1180009001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX2_RX000_ADR_CAM0"         ,	   0x118000a000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX2_RX001_ADR_CAM0"         ,	   0x118000a000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX2_RX002_ADR_CAM0"         ,	   0x118000a001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX2_RX003_ADR_CAM0"         ,	   0x118000a001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX3_RX000_ADR_CAM0"         ,	   0x118000b000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX3_RX001_ADR_CAM0"         ,	   0x118000b000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX3_RX002_ADR_CAM0"         ,	   0x118000b001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX3_RX003_ADR_CAM0"         ,	   0x118000b001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX4_RX000_ADR_CAM0"         ,	   0x118000c000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX4_RX001_ADR_CAM0"         ,	   0x118000c000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX4_RX002_ADR_CAM0"         ,	   0x118000c001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX4_RX003_ADR_CAM0"         ,	   0x118000c001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX0_RX000_ADR_CAM1"         ,	   0x1180008000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX0_RX001_ADR_CAM1"         ,	   0x1180008000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX0_RX002_ADR_CAM1"         ,	   0x1180008001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX0_RX003_ADR_CAM1"         ,	   0x1180008001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX1_RX000_ADR_CAM1"         ,	   0x1180009000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX1_RX001_ADR_CAM1"         ,	   0x1180009000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX1_RX002_ADR_CAM1"         ,	   0x1180009001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX1_RX003_ADR_CAM1"         ,	   0x1180009001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX2_RX000_ADR_CAM1"         ,	   0x118000a000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX2_RX001_ADR_CAM1"         ,	   0x118000a000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX2_RX002_ADR_CAM1"         ,	   0x118000a001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX2_RX003_ADR_CAM1"         ,	   0x118000a001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX3_RX000_ADR_CAM1"         ,	   0x118000b000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX3_RX001_ADR_CAM1"         ,	   0x118000b000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX3_RX002_ADR_CAM1"         ,	   0x118000b001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX3_RX003_ADR_CAM1"         ,	   0x118000b001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX4_RX000_ADR_CAM1"         ,	   0x118000c000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX4_RX001_ADR_CAM1"         ,	   0x118000c000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX4_RX002_ADR_CAM1"         ,	   0x118000c001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX4_RX003_ADR_CAM1"         ,	   0x118000c001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX0_RX000_ADR_CAM2"         ,	   0x1180008000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX0_RX001_ADR_CAM2"         ,	   0x1180008000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX0_RX002_ADR_CAM2"         ,	   0x1180008001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX0_RX003_ADR_CAM2"         ,	   0x1180008001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX1_RX000_ADR_CAM2"         ,	   0x1180009000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX1_RX001_ADR_CAM2"         ,	   0x1180009000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX1_RX002_ADR_CAM2"         ,	   0x1180009001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX1_RX003_ADR_CAM2"         ,	   0x1180009001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX2_RX000_ADR_CAM2"         ,	   0x118000a000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX2_RX001_ADR_CAM2"         ,	   0x118000a000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX2_RX002_ADR_CAM2"         ,	   0x118000a001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX2_RX003_ADR_CAM2"         ,	   0x118000a001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX3_RX000_ADR_CAM2"         ,	   0x118000b000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX3_RX001_ADR_CAM2"         ,	   0x118000b000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX3_RX002_ADR_CAM2"         ,	   0x118000b001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX3_RX003_ADR_CAM2"         ,	   0x118000b001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX4_RX000_ADR_CAM2"         ,	   0x118000c000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX4_RX001_ADR_CAM2"         ,	   0x118000c000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX4_RX002_ADR_CAM2"         ,	   0x118000c001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX4_RX003_ADR_CAM2"         ,	   0x118000c001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX0_RX003_ADR_CAM3"         ,	   0x1180008001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX1_RX000_ADR_CAM3"         ,	   0x1180009000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX1_RX001_ADR_CAM3"         ,	   0x1180009000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX1_RX002_ADR_CAM3"         ,	   0x1180009001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX1_RX003_ADR_CAM3"         ,	   0x1180009001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX2_RX000_ADR_CAM3"         ,	   0x118000a000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX2_RX001_ADR_CAM3"         ,	   0x118000a000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX2_RX002_ADR_CAM3"         ,	   0x118000a001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX2_RX003_ADR_CAM3"         ,	   0x118000a001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX3_RX000_ADR_CAM3"         ,	   0x118000b000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX3_RX001_ADR_CAM3"         ,	   0x118000b000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX3_RX002_ADR_CAM3"         ,	   0x118000b001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX3_RX003_ADR_CAM3"         ,	   0x118000b001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX4_RX000_ADR_CAM3"         ,	   0x118000c000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX4_RX001_ADR_CAM3"         ,	   0x118000c000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX4_RX002_ADR_CAM3"         ,	   0x118000c001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX4_RX003_ADR_CAM3"         ,	   0x118000c001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800090001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800090009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800090011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800090019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX2_RX000_ADR_CAM4"         ,	   0x118000a0001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX2_RX001_ADR_CAM4"         ,	   0x118000a0009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX2_RX002_ADR_CAM4"         ,	   0x118000a0011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX2_RX003_ADR_CAM4"         ,	   0x118000a0019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX3_RX000_ADR_CAM4"         ,	   0x118000b0001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX3_RX001_ADR_CAM4"         ,	   0x118000b0009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX3_RX002_ADR_CAM4"         ,	   0x118000b0011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX3_RX003_ADR_CAM4"         ,	   0x118000b0019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX4_RX000_ADR_CAM4"         ,	   0x118000c0001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX4_RX001_ADR_CAM4"         ,	   0x118000c0009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX4_RX002_ADR_CAM4"         ,	   0x118000c0011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX4_RX003_ADR_CAM4"         ,	   0x118000c0019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800090001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800090009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800090011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800090019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX2_RX000_ADR_CAM5"         ,	   0x118000a0001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX2_RX001_ADR_CAM5"         ,	   0x118000a0009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX2_RX002_ADR_CAM5"         ,	   0x118000a0011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX2_RX003_ADR_CAM5"         ,	   0x118000a0019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX3_RX000_ADR_CAM5"         ,	   0x118000b0001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX3_RX001_ADR_CAM5"         ,	   0x118000b0009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX3_RX002_ADR_CAM5"         ,	   0x118000b0011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX3_RX003_ADR_CAM5"         ,	   0x118000b0019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX4_RX000_ADR_CAM5"         ,	   0x118000c0001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX4_RX001_ADR_CAM5"         ,	   0x118000c0009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX4_RX002_ADR_CAM5"         ,	   0x118000c0011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX4_RX003_ADR_CAM5"         ,	   0x118000c0019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX0_RX000_ADR_CAM_ALL_EN"   ,	   0x1180008000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX0_RX001_ADR_CAM_ALL_EN"   ,	   0x1180008000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX0_RX002_ADR_CAM_ALL_EN"   ,	   0x1180008001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX0_RX003_ADR_CAM_ALL_EN"   ,	   0x1180008001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX1_RX000_ADR_CAM_ALL_EN"   ,	   0x1180009000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX1_RX001_ADR_CAM_ALL_EN"   ,	   0x1180009000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX1_RX002_ADR_CAM_ALL_EN"   ,	   0x1180009001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX1_RX003_ADR_CAM_ALL_EN"   ,	   0x1180009001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX2_RX000_ADR_CAM_ALL_EN"   ,	   0x118000a000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX2_RX001_ADR_CAM_ALL_EN"   ,	   0x118000a000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX2_RX002_ADR_CAM_ALL_EN"   ,	   0x118000a001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX2_RX003_ADR_CAM_ALL_EN"   ,	   0x118000a001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX3_RX000_ADR_CAM_ALL_EN"   ,	   0x118000b000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX3_RX001_ADR_CAM_ALL_EN"   ,	   0x118000b000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX3_RX002_ADR_CAM_ALL_EN"   ,	   0x118000b001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX3_RX003_ADR_CAM_ALL_EN"   ,	   0x118000b001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX4_RX000_ADR_CAM_ALL_EN"   ,	   0x118000c000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX4_RX001_ADR_CAM_ALL_EN"   ,	   0x118000c000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX4_RX002_ADR_CAM_ALL_EN"   ,	   0x118000c001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX4_RX003_ADR_CAM_ALL_EN"   ,	   0x118000c001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX0_RX003_ADR_CAM_EN"       ,	   0x1180008001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX1_RX000_ADR_CAM_EN"       ,	   0x1180009000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX1_RX001_ADR_CAM_EN"       ,	   0x1180009000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX1_RX002_ADR_CAM_EN"       ,	   0x1180009001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX1_RX003_ADR_CAM_EN"       ,	   0x1180009001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX2_RX000_ADR_CAM_EN"       ,	   0x118000a000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX2_RX001_ADR_CAM_EN"       ,	   0x118000a000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX2_RX002_ADR_CAM_EN"       ,	   0x118000a001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX2_RX003_ADR_CAM_EN"       ,	   0x118000a001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX3_RX000_ADR_CAM_EN"       ,	   0x118000b000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX3_RX001_ADR_CAM_EN"       ,	   0x118000b000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX3_RX002_ADR_CAM_EN"       ,	   0x118000b001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX3_RX003_ADR_CAM_EN"       ,	   0x118000b001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX4_RX000_ADR_CAM_EN"       ,	   0x118000c000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX4_RX001_ADR_CAM_EN"       ,	   0x118000c000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX4_RX002_ADR_CAM_EN"       ,	   0x118000c001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX4_RX003_ADR_CAM_EN"       ,	   0x118000c001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX0_RX000_ADR_CTL"          ,	   0x1180008000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX0_RX001_ADR_CTL"          ,	   0x1180008000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX0_RX002_ADR_CTL"          ,	   0x1180008001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX0_RX003_ADR_CTL"          ,	   0x1180008001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX1_RX000_ADR_CTL"          ,	   0x1180009000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX1_RX001_ADR_CTL"          ,	   0x1180009000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX1_RX002_ADR_CTL"          ,	   0x1180009001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX1_RX003_ADR_CTL"          ,	   0x1180009001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX2_RX000_ADR_CTL"          ,	   0x118000a000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX2_RX001_ADR_CTL"          ,	   0x118000a000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX2_RX002_ADR_CTL"          ,	   0x118000a001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX2_RX003_ADR_CTL"          ,	   0x118000a001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX3_RX000_ADR_CTL"          ,	   0x118000b000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX3_RX001_ADR_CTL"          ,	   0x118000b000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX3_RX002_ADR_CTL"          ,	   0x118000b001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX3_RX003_ADR_CTL"          ,	   0x118000b001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX4_RX000_ADR_CTL"          ,	   0x118000c000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX4_RX001_ADR_CTL"          ,	   0x118000c000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX4_RX002_ADR_CTL"          ,	   0x118000c001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX4_RX003_ADR_CTL"          ,	   0x118000c001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX0_RX000_DECISION"         ,	   0x1180008000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX0_RX001_DECISION"         ,	   0x1180008000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX0_RX002_DECISION"         ,	   0x1180008001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX0_RX003_DECISION"         ,	   0x1180008001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX1_RX000_DECISION"         ,	   0x1180009000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX1_RX001_DECISION"         ,	   0x1180009000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX1_RX002_DECISION"         ,	   0x1180009001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX1_RX003_DECISION"         ,	   0x1180009001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX2_RX000_DECISION"         ,	   0x118000a000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX2_RX001_DECISION"         ,	   0x118000a000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX2_RX002_DECISION"         ,	   0x118000a001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX2_RX003_DECISION"         ,	   0x118000a001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX3_RX000_DECISION"         ,	   0x118000b000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX3_RX001_DECISION"         ,	   0x118000b000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX3_RX002_DECISION"         ,	   0x118000b001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX3_RX003_DECISION"         ,	   0x118000b001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX4_RX000_DECISION"         ,	   0x118000c000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX4_RX001_DECISION"         ,	   0x118000c000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX4_RX002_DECISION"         ,	   0x118000c001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX4_RX003_DECISION"         ,	   0x118000c001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX0_RX000_FRM_CHK"          ,	   0x1180008000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX0_RX001_FRM_CHK"          ,	   0x1180008000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX0_RX002_FRM_CHK"          ,	   0x1180008001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX0_RX003_FRM_CHK"          ,	   0x1180008001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX1_RX000_FRM_CHK"          ,	   0x1180009000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX1_RX001_FRM_CHK"          ,	   0x1180009000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX1_RX002_FRM_CHK"          ,	   0x1180009001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX1_RX003_FRM_CHK"          ,	   0x1180009001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX2_RX000_FRM_CHK"          ,	   0x118000a000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX2_RX001_FRM_CHK"          ,	   0x118000a000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX2_RX002_FRM_CHK"          ,	   0x118000a001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX2_RX003_FRM_CHK"          ,	   0x118000a001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX3_RX000_FRM_CHK"          ,	   0x118000b000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX3_RX001_FRM_CHK"          ,	   0x118000b000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX3_RX002_FRM_CHK"          ,	   0x118000b001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX3_RX003_FRM_CHK"          ,	   0x118000b001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX4_RX000_FRM_CHK"          ,	   0x118000c000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX4_RX001_FRM_CHK"          ,	   0x118000c000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX4_RX002_FRM_CHK"          ,	   0x118000c001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX4_RX003_FRM_CHK"          ,	   0x118000c001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX0_RX000_FRM_CTL"          ,	   0x1180008000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX0_RX001_FRM_CTL"          ,	   0x1180008000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX0_RX002_FRM_CTL"          ,	   0x1180008001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX0_RX003_FRM_CTL"          ,	   0x1180008001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX1_RX000_FRM_CTL"          ,	   0x1180009000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX1_RX001_FRM_CTL"          ,	   0x1180009000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX1_RX002_FRM_CTL"          ,	   0x1180009001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX1_RX003_FRM_CTL"          ,	   0x1180009001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX2_RX000_FRM_CTL"          ,	   0x118000a000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX2_RX001_FRM_CTL"          ,	   0x118000a000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX2_RX002_FRM_CTL"          ,	   0x118000a001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX2_RX003_FRM_CTL"          ,	   0x118000a001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX3_RX000_FRM_CTL"          ,	   0x118000b000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX3_RX001_FRM_CTL"          ,	   0x118000b000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX3_RX002_FRM_CTL"          ,	   0x118000b001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX3_RX003_FRM_CTL"          ,	   0x118000b001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX4_RX000_FRM_CTL"          ,	   0x118000c000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX4_RX001_FRM_CTL"          ,	   0x118000c000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX4_RX002_FRM_CTL"          ,	   0x118000c001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX4_RX003_FRM_CTL"          ,	   0x118000c001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX0_RX000_IFG"              ,	   0x1180008000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX0_RX001_IFG"              ,	   0x1180008000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX0_RX002_IFG"              ,	   0x1180008001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX0_RX003_IFG"              ,	   0x1180008001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX1_RX000_IFG"              ,	   0x1180009000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX1_RX001_IFG"              ,	   0x1180009000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX1_RX002_IFG"              ,	   0x1180009001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX1_RX003_IFG"              ,	   0x1180009001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX2_RX000_IFG"              ,	   0x118000a000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX2_RX001_IFG"              ,	   0x118000a000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX2_RX002_IFG"              ,	   0x118000a001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX2_RX003_IFG"              ,	   0x118000a001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX3_RX000_IFG"              ,	   0x118000b000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX3_RX001_IFG"              ,	   0x118000b000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX3_RX002_IFG"              ,	   0x118000b001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX3_RX003_IFG"              ,	   0x118000b001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX4_RX000_IFG"              ,	   0x118000c000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX4_RX001_IFG"              ,	   0x118000c000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX4_RX002_IFG"              ,	   0x118000c001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX4_RX003_IFG"              ,	   0x118000c001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX0_RX000_INT_EN"           ,	   0x1180008000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX0_RX001_INT_EN"           ,	   0x1180008000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX0_RX002_INT_EN"           ,	   0x1180008001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX0_RX003_INT_EN"           ,	   0x1180008001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX1_RX000_INT_EN"           ,	   0x1180009000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX1_RX001_INT_EN"           ,	   0x1180009000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX1_RX002_INT_EN"           ,	   0x1180009001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX1_RX003_INT_EN"           ,	   0x1180009001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX2_RX000_INT_EN"           ,	   0x118000a000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX2_RX001_INT_EN"           ,	   0x118000a000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX2_RX002_INT_EN"           ,	   0x118000a001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX2_RX003_INT_EN"           ,	   0x118000a001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX3_RX000_INT_EN"           ,	   0x118000b000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX3_RX001_INT_EN"           ,	   0x118000b000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX3_RX002_INT_EN"           ,	   0x118000b001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX3_RX003_INT_EN"           ,	   0x118000b001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX4_RX000_INT_EN"           ,	   0x118000c000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX4_RX001_INT_EN"           ,	   0x118000c000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX4_RX002_INT_EN"           ,	   0x118000c001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX4_RX003_INT_EN"           ,	   0x118000c001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX0_RX000_INT_REG"          ,	   0x1180008000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX0_RX001_INT_REG"          ,	   0x1180008000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX0_RX002_INT_REG"          ,	   0x1180008001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX0_RX003_INT_REG"          ,	   0x1180008001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX1_RX000_INT_REG"          ,	   0x1180009000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX1_RX001_INT_REG"          ,	   0x1180009000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX1_RX002_INT_REG"          ,	   0x1180009001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX1_RX003_INT_REG"          ,	   0x1180009001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX2_RX000_INT_REG"          ,	   0x118000a000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX2_RX001_INT_REG"          ,	   0x118000a000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX2_RX002_INT_REG"          ,	   0x118000a001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX2_RX003_INT_REG"          ,	   0x118000a001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX3_RX000_INT_REG"          ,	   0x118000b000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX3_RX001_INT_REG"          ,	   0x118000b000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX3_RX002_INT_REG"          ,	   0x118000b001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX3_RX003_INT_REG"          ,	   0x118000b001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX4_RX000_INT_REG"          ,	   0x118000c000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX4_RX001_INT_REG"          ,	   0x118000c000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX4_RX002_INT_REG"          ,	   0x118000c001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX4_RX003_INT_REG"          ,	   0x118000c001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX0_RX000_JABBER"           ,	   0x1180008000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX0_RX001_JABBER"           ,	   0x1180008000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX0_RX002_JABBER"           ,	   0x1180008001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX0_RX003_JABBER"           ,	   0x1180008001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX1_RX000_JABBER"           ,	   0x1180009000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX1_RX001_JABBER"           ,	   0x1180009000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX1_RX002_JABBER"           ,	   0x1180009001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX1_RX003_JABBER"           ,	   0x1180009001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX2_RX000_JABBER"           ,	   0x118000a000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX2_RX001_JABBER"           ,	   0x118000a000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX2_RX002_JABBER"           ,	   0x118000a001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX2_RX003_JABBER"           ,	   0x118000a001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX3_RX000_JABBER"           ,	   0x118000b000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX3_RX001_JABBER"           ,	   0x118000b000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX3_RX002_JABBER"           ,	   0x118000b001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX3_RX003_JABBER"           ,	   0x118000b001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX4_RX000_JABBER"           ,	   0x118000c000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX4_RX001_JABBER"           ,	   0x118000c000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX4_RX002_JABBER"           ,	   0x118000c001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX4_RX003_JABBER"           ,	   0x118000c001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX0_RX000_PAUSE_DROP_TIME"  ,	   0x1180008000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX0_RX001_PAUSE_DROP_TIME"  ,	   0x1180008000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX0_RX002_PAUSE_DROP_TIME"  ,	   0x1180008001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX0_RX003_PAUSE_DROP_TIME"  ,	   0x1180008001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX1_RX000_PAUSE_DROP_TIME"  ,	   0x1180009000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX1_RX001_PAUSE_DROP_TIME"  ,	   0x1180009000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX1_RX002_PAUSE_DROP_TIME"  ,	   0x1180009001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX1_RX003_PAUSE_DROP_TIME"  ,	   0x1180009001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX2_RX000_PAUSE_DROP_TIME"  ,	   0x118000a000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX2_RX001_PAUSE_DROP_TIME"  ,	   0x118000a000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX2_RX002_PAUSE_DROP_TIME"  ,	   0x118000a001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX2_RX003_PAUSE_DROP_TIME"  ,	   0x118000a001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX3_RX000_PAUSE_DROP_TIME"  ,	   0x118000b000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX3_RX001_PAUSE_DROP_TIME"  ,	   0x118000b000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX3_RX002_PAUSE_DROP_TIME"  ,	   0x118000b001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX3_RX003_PAUSE_DROP_TIME"  ,	   0x118000b001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX4_RX000_PAUSE_DROP_TIME"  ,	   0x118000c000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX4_RX001_PAUSE_DROP_TIME"  ,	   0x118000c000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX4_RX002_PAUSE_DROP_TIME"  ,	   0x118000c001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX4_RX003_PAUSE_DROP_TIME"  ,	   0x118000c001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX0_RX000_STATS_CTL"        ,	   0x1180008000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX0_RX001_STATS_CTL"        ,	   0x1180008000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX0_RX002_STATS_CTL"        ,	   0x1180008001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX0_RX003_STATS_CTL"        ,	   0x1180008001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX1_RX000_STATS_CTL"        ,	   0x1180009000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX1_RX001_STATS_CTL"        ,	   0x1180009000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX1_RX002_STATS_CTL"        ,	   0x1180009001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX1_RX003_STATS_CTL"        ,	   0x1180009001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX2_RX000_STATS_CTL"        ,	   0x118000a000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX2_RX001_STATS_CTL"        ,	   0x118000a000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX2_RX002_STATS_CTL"        ,	   0x118000a001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX2_RX003_STATS_CTL"        ,	   0x118000a001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX3_RX000_STATS_CTL"        ,	   0x118000b000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX3_RX001_STATS_CTL"        ,	   0x118000b000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX3_RX002_STATS_CTL"        ,	   0x118000b001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX3_RX003_STATS_CTL"        ,	   0x118000b001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX4_RX000_STATS_CTL"        ,	   0x118000c000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX4_RX001_STATS_CTL"        ,	   0x118000c000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX4_RX002_STATS_CTL"        ,	   0x118000c001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX4_RX003_STATS_CTL"        ,	   0x118000c001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX0_RX000_STATS_OCTS"       ,	   0x1180008000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX0_RX001_STATS_OCTS"       ,	   0x1180008000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX0_RX002_STATS_OCTS"       ,	   0x1180008001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX0_RX003_STATS_OCTS"       ,	   0x1180008001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX1_RX000_STATS_OCTS"       ,	   0x1180009000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX1_RX001_STATS_OCTS"       ,	   0x1180009000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX1_RX002_STATS_OCTS"       ,	   0x1180009001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX1_RX003_STATS_OCTS"       ,	   0x1180009001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX2_RX000_STATS_OCTS"       ,	   0x118000a000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX2_RX001_STATS_OCTS"       ,	   0x118000a000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX2_RX002_STATS_OCTS"       ,	   0x118000a001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX2_RX003_STATS_OCTS"       ,	   0x118000a001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX3_RX000_STATS_OCTS"       ,	   0x118000b000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX3_RX001_STATS_OCTS"       ,	   0x118000b000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX3_RX002_STATS_OCTS"       ,	   0x118000b001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX3_RX003_STATS_OCTS"       ,	   0x118000b001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX4_RX000_STATS_OCTS"       ,	   0x118000c000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX4_RX001_STATS_OCTS"       ,	   0x118000c000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX4_RX002_STATS_OCTS"       ,	   0x118000c001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX4_RX003_STATS_OCTS"       ,	   0x118000c001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX0_RX003_STATS_OCTS_CTL"   ,	   0x1180008001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX1_RX000_STATS_OCTS_CTL"   ,	   0x1180009000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX1_RX001_STATS_OCTS_CTL"   ,	   0x1180009000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX1_RX002_STATS_OCTS_CTL"   ,	   0x1180009001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX1_RX003_STATS_OCTS_CTL"   ,	   0x1180009001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX2_RX000_STATS_OCTS_CTL"   ,	   0x118000a000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX2_RX001_STATS_OCTS_CTL"   ,	   0x118000a000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX2_RX002_STATS_OCTS_CTL"   ,	   0x118000a001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX2_RX003_STATS_OCTS_CTL"   ,	   0x118000a001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX3_RX000_STATS_OCTS_CTL"   ,	   0x118000b000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX3_RX001_STATS_OCTS_CTL"   ,	   0x118000b000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX3_RX002_STATS_OCTS_CTL"   ,	   0x118000b001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX3_RX003_STATS_OCTS_CTL"   ,	   0x118000b001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX4_RX000_STATS_OCTS_CTL"   ,	   0x118000c000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX4_RX001_STATS_OCTS_CTL"   ,	   0x118000c000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX4_RX002_STATS_OCTS_CTL"   ,	   0x118000c001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX4_RX003_STATS_OCTS_CTL"   ,	   0x118000c001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800090000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800090008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800090010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800090018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX2_RX000_STATS_OCTS_DMAC"  ,	   0x118000a0000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX2_RX001_STATS_OCTS_DMAC"  ,	   0x118000a0008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX2_RX002_STATS_OCTS_DMAC"  ,	   0x118000a0010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX2_RX003_STATS_OCTS_DMAC"  ,	   0x118000a0018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX3_RX000_STATS_OCTS_DMAC"  ,	   0x118000b0000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX3_RX001_STATS_OCTS_DMAC"  ,	   0x118000b0008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX3_RX002_STATS_OCTS_DMAC"  ,	   0x118000b0010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX3_RX003_STATS_OCTS_DMAC"  ,	   0x118000b0018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX4_RX000_STATS_OCTS_DMAC"  ,	   0x118000c0000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX4_RX001_STATS_OCTS_DMAC"  ,	   0x118000c0008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX4_RX002_STATS_OCTS_DMAC"  ,	   0x118000c0010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX4_RX003_STATS_OCTS_DMAC"  ,	   0x118000c0018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800090000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800090008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800090010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800090018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX2_RX000_STATS_OCTS_DRP"   ,	   0x118000a0000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX2_RX001_STATS_OCTS_DRP"   ,	   0x118000a0008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX2_RX002_STATS_OCTS_DRP"   ,	   0x118000a0010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX2_RX003_STATS_OCTS_DRP"   ,	   0x118000a0018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX3_RX000_STATS_OCTS_DRP"   ,	   0x118000b0000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX3_RX001_STATS_OCTS_DRP"   ,	   0x118000b0008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX3_RX002_STATS_OCTS_DRP"   ,	   0x118000b0010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX3_RX003_STATS_OCTS_DRP"   ,	   0x118000b0018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX4_RX000_STATS_OCTS_DRP"   ,	   0x118000c0000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX4_RX001_STATS_OCTS_DRP"   ,	   0x118000c0008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX4_RX002_STATS_OCTS_DRP"   ,	   0x118000c0010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX4_RX003_STATS_OCTS_DRP"   ,	   0x118000c0018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX0_RX003_STATS_PKTS"       ,	   0x1180008001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX1_RX000_STATS_PKTS"       ,	   0x1180009000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX1_RX001_STATS_PKTS"       ,	   0x1180009000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX1_RX002_STATS_PKTS"       ,	   0x1180009001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX1_RX003_STATS_PKTS"       ,	   0x1180009001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX2_RX000_STATS_PKTS"       ,	   0x118000a000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX2_RX001_STATS_PKTS"       ,	   0x118000a000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX2_RX002_STATS_PKTS"       ,	   0x118000a001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX2_RX003_STATS_PKTS"       ,	   0x118000a001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX3_RX000_STATS_PKTS"       ,	   0x118000b000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX3_RX001_STATS_PKTS"       ,	   0x118000b000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX3_RX002_STATS_PKTS"       ,	   0x118000b001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX3_RX003_STATS_PKTS"       ,	   0x118000b001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX4_RX000_STATS_PKTS"       ,	   0x118000c000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX4_RX001_STATS_PKTS"       ,	   0x118000c000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX4_RX002_STATS_PKTS"       ,	   0x118000c001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX4_RX003_STATS_PKTS"       ,	   0x118000c001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800090000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800090008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800090010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800090018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX2_RX000_STATS_PKTS_BAD"   ,	   0x118000a0000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX2_RX001_STATS_PKTS_BAD"   ,	   0x118000a0008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX2_RX002_STATS_PKTS_BAD"   ,	   0x118000a0010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX2_RX003_STATS_PKTS_BAD"   ,	   0x118000a0018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX3_RX000_STATS_PKTS_BAD"   ,	   0x118000b0000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX3_RX001_STATS_PKTS_BAD"   ,	   0x118000b0008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX3_RX002_STATS_PKTS_BAD"   ,	   0x118000b0010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX3_RX003_STATS_PKTS_BAD"   ,	   0x118000b0018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX4_RX000_STATS_PKTS_BAD"   ,	   0x118000c0000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX4_RX001_STATS_PKTS_BAD"   ,	   0x118000c0008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX4_RX002_STATS_PKTS_BAD"   ,	   0x118000c0010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX4_RX003_STATS_PKTS_BAD"   ,	   0x118000c0018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX0_RX003_STATS_PKTS_CTL"   ,	   0x1180008001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX1_RX000_STATS_PKTS_CTL"   ,	   0x1180009000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX1_RX001_STATS_PKTS_CTL"   ,	   0x1180009000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX1_RX002_STATS_PKTS_CTL"   ,	   0x1180009001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX1_RX003_STATS_PKTS_CTL"   ,	   0x1180009001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX2_RX000_STATS_PKTS_CTL"   ,	   0x118000a000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX2_RX001_STATS_PKTS_CTL"   ,	   0x118000a000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX2_RX002_STATS_PKTS_CTL"   ,	   0x118000a001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX2_RX003_STATS_PKTS_CTL"   ,	   0x118000a001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX3_RX000_STATS_PKTS_CTL"   ,	   0x118000b000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX3_RX001_STATS_PKTS_CTL"   ,	   0x118000b000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX3_RX002_STATS_PKTS_CTL"   ,	   0x118000b001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX3_RX003_STATS_PKTS_CTL"   ,	   0x118000b001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX4_RX000_STATS_PKTS_CTL"   ,	   0x118000c000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX4_RX001_STATS_PKTS_CTL"   ,	   0x118000c000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX4_RX002_STATS_PKTS_CTL"   ,	   0x118000c001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX4_RX003_STATS_PKTS_CTL"   ,	   0x118000c001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800090000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800090008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800090010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800090018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX2_RX000_STATS_PKTS_DMAC"  ,	   0x118000a0000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX2_RX001_STATS_PKTS_DMAC"  ,	   0x118000a0008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX2_RX002_STATS_PKTS_DMAC"  ,	   0x118000a0010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX2_RX003_STATS_PKTS_DMAC"  ,	   0x118000a0018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX3_RX000_STATS_PKTS_DMAC"  ,	   0x118000b0000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX3_RX001_STATS_PKTS_DMAC"  ,	   0x118000b0008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX3_RX002_STATS_PKTS_DMAC"  ,	   0x118000b0010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX3_RX003_STATS_PKTS_DMAC"  ,	   0x118000b0018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX4_RX000_STATS_PKTS_DMAC"  ,	   0x118000c0000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX4_RX001_STATS_PKTS_DMAC"  ,	   0x118000c0008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX4_RX002_STATS_PKTS_DMAC"  ,	   0x118000c0010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX4_RX003_STATS_PKTS_DMAC"  ,	   0x118000c0018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800090000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800090008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800090010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800090018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX2_RX000_STATS_PKTS_DRP"   ,	   0x118000a0000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX2_RX001_STATS_PKTS_DRP"   ,	   0x118000a0008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX2_RX002_STATS_PKTS_DRP"   ,	   0x118000a0010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX2_RX003_STATS_PKTS_DRP"   ,	   0x118000a0018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX3_RX000_STATS_PKTS_DRP"   ,	   0x118000b0000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX3_RX001_STATS_PKTS_DRP"   ,	   0x118000b0008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX3_RX002_STATS_PKTS_DRP"   ,	   0x118000b0010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX3_RX003_STATS_PKTS_DRP"   ,	   0x118000b0018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX4_RX000_STATS_PKTS_DRP"   ,	   0x118000c0000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX4_RX001_STATS_PKTS_DRP"   ,	   0x118000c0008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX4_RX002_STATS_PKTS_DRP"   ,	   0x118000c0010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX4_RX003_STATS_PKTS_DRP"   ,	   0x118000c0018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX0_RX003_UDD_SKP"          ,	   0x1180008001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX1_RX000_UDD_SKP"          ,	   0x1180009000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX1_RX001_UDD_SKP"          ,	   0x1180009000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX1_RX002_UDD_SKP"          ,	   0x1180009001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX1_RX003_UDD_SKP"          ,	   0x1180009001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX2_RX000_UDD_SKP"          ,	   0x118000a000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX2_RX001_UDD_SKP"          ,	   0x118000a000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX2_RX002_UDD_SKP"          ,	   0x118000a001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX2_RX003_UDD_SKP"          ,	   0x118000a001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX3_RX000_UDD_SKP"          ,	   0x118000b000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX3_RX001_UDD_SKP"          ,	   0x118000b000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX3_RX002_UDD_SKP"          ,	   0x118000b001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX3_RX003_UDD_SKP"          ,	   0x118000b001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX4_RX000_UDD_SKP"          ,	   0x118000c000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX4_RX001_UDD_SKP"          ,	   0x118000c000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX4_RX002_UDD_SKP"          ,	   0x118000c001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX4_RX003_UDD_SKP"          ,	   0x118000c001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"GMX0_RX_BP_DROP000"          ,	   0x1180008000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX0_RX_BP_DROP001"          ,	   0x1180008000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX0_RX_BP_DROP002"          ,	   0x1180008000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX0_RX_BP_DROP003"          ,	   0x1180008000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX1_RX_BP_DROP000"          ,	   0x1180009000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX1_RX_BP_DROP001"          ,	   0x1180009000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX1_RX_BP_DROP002"          ,	   0x1180009000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX1_RX_BP_DROP003"          ,	   0x1180009000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX2_RX_BP_DROP000"          ,	   0x118000a000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX2_RX_BP_DROP001"          ,	   0x118000a000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX2_RX_BP_DROP002"          ,	   0x118000a000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX2_RX_BP_DROP003"          ,	   0x118000a000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX3_RX_BP_DROP000"          ,	   0x118000b000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX3_RX_BP_DROP001"          ,	   0x118000b000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX3_RX_BP_DROP002"          ,	   0x118000b000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX3_RX_BP_DROP003"          ,	   0x118000b000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX4_RX_BP_DROP000"          ,	   0x118000c000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX4_RX_BP_DROP001"          ,	   0x118000c000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX4_RX_BP_DROP002"          ,	   0x118000c000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX4_RX_BP_DROP003"          ,	   0x118000c000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"GMX0_RX_BP_OFF000"           ,	   0x1180008000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX0_RX_BP_OFF001"           ,	   0x1180008000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX0_RX_BP_OFF002"           ,	   0x1180008000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX0_RX_BP_OFF003"           ,	   0x1180008000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX1_RX_BP_OFF000"           ,	   0x1180009000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX1_RX_BP_OFF001"           ,	   0x1180009000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX1_RX_BP_OFF002"           ,	   0x1180009000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX1_RX_BP_OFF003"           ,	   0x1180009000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX2_RX_BP_OFF000"           ,	   0x118000a000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX2_RX_BP_OFF001"           ,	   0x118000a000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX2_RX_BP_OFF002"           ,	   0x118000a000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX2_RX_BP_OFF003"           ,	   0x118000a000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX3_RX_BP_OFF000"           ,	   0x118000b000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX3_RX_BP_OFF001"           ,	   0x118000b000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX3_RX_BP_OFF002"           ,	   0x118000b000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX3_RX_BP_OFF003"           ,	   0x118000b000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX4_RX_BP_OFF000"           ,	   0x118000c000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX4_RX_BP_OFF001"           ,	   0x118000c000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX4_RX_BP_OFF002"           ,	   0x118000c000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX4_RX_BP_OFF003"           ,	   0x118000c000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX0_RX_BP_ON003"            ,	   0x1180008000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX1_RX_BP_ON000"            ,	   0x1180009000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX1_RX_BP_ON001"            ,	   0x1180009000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX1_RX_BP_ON002"            ,	   0x1180009000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX1_RX_BP_ON003"            ,	   0x1180009000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX2_RX_BP_ON000"            ,	   0x118000a000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX2_RX_BP_ON001"            ,	   0x118000a000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX2_RX_BP_ON002"            ,	   0x118000a000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX2_RX_BP_ON003"            ,	   0x118000a000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX3_RX_BP_ON000"            ,	   0x118000b000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX3_RX_BP_ON001"            ,	   0x118000b000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX3_RX_BP_ON002"            ,	   0x118000b000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX3_RX_BP_ON003"            ,	   0x118000b000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX4_RX_BP_ON000"            ,	   0x118000c000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX4_RX_BP_ON001"            ,	   0x118000c000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX4_RX_BP_ON002"            ,	   0x118000c000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX4_RX_BP_ON003"            ,	   0x118000c000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"GMX0_RX_HG2_STATUS"          ,	   0x1180008000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"GMX1_RX_HG2_STATUS"          ,	   0x1180009000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"GMX2_RX_HG2_STATUS"          ,	   0x118000a000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"GMX3_RX_HG2_STATUS"          ,	   0x118000b000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"GMX4_RX_HG2_STATUS"          ,	   0x118000c000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"GMX1_RX_PRT_INFO"            ,	   0x11800090004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"GMX2_RX_PRT_INFO"            ,	   0x118000a0004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"GMX3_RX_PRT_INFO"            ,	   0x118000b0004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"GMX4_RX_PRT_INFO"            ,	   0x118000c0004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"GMX1_RX_PRTS"                ,	   0x1180009000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"GMX2_RX_PRTS"                ,	   0x118000a000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"GMX3_RX_PRTS"                ,	   0x118000b000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"GMX4_RX_PRTS"                ,	   0x118000c000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"GMX0_RX_XAUI_BAD_COL"        ,	   0x1180008000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX1_RX_XAUI_BAD_COL"        ,	   0x1180009000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX2_RX_XAUI_BAD_COL"        ,	   0x118000a000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX3_RX_XAUI_BAD_COL"        ,	   0x118000b000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX4_RX_XAUI_BAD_COL"        ,	   0x118000c000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"GMX0_RX_XAUI_CTL"            ,	   0x1180008000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"GMX1_RX_XAUI_CTL"            ,	   0x1180009000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"GMX2_RX_XAUI_CTL"            ,	   0x118000a000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"GMX3_RX_XAUI_CTL"            ,	   0x118000b000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"GMX4_RX_XAUI_CTL"            ,	   0x118000c000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"GMX0_RXAUI_CTL"              ,	   0x1180008000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"GMX1_RXAUI_CTL"              ,	   0x1180009000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"GMX2_RXAUI_CTL"              ,	   0x118000a000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"GMX3_RXAUI_CTL"              ,	   0x118000b000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"GMX4_RXAUI_CTL"              ,	   0x118000c000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX0_SMAC001"                ,	   0x1180008000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX0_SMAC003"                ,	   0x1180008001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX1_SMAC000"                ,	   0x1180009000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX1_SMAC001"                ,	   0x1180009000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX1_SMAC002"                ,	   0x1180009001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX1_SMAC003"                ,	   0x1180009001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX2_SMAC000"                ,	   0x118000a000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX2_SMAC001"                ,	   0x118000a000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX2_SMAC002"                ,	   0x118000a001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX2_SMAC003"                ,	   0x118000a001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX3_SMAC000"                ,	   0x118000b000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX3_SMAC001"                ,	   0x118000b000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX3_SMAC002"                ,	   0x118000b001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX3_SMAC003"                ,	   0x118000b001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX4_SMAC000"                ,	   0x118000c000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX4_SMAC001"                ,	   0x118000c000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX4_SMAC002"                ,	   0x118000c001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX4_SMAC003"                ,	   0x118000c001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"GMX0_SOFT_BIST"              ,	   0x11800080007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX1_SOFT_BIST"              ,	   0x11800090007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX2_SOFT_BIST"              ,	   0x118000a0007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX3_SOFT_BIST"              ,	   0x118000b0007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX4_SOFT_BIST"              ,	   0x118000c0007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"GMX1_STAT_BP"                ,	   0x1180009000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"GMX2_STAT_BP"                ,	   0x118000a000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"GMX3_STAT_BP"                ,	   0x118000b000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"GMX4_STAT_BP"                ,	   0x118000c000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"GMX0_TB_REG"                 ,	   0x11800080007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"GMX1_TB_REG"                 ,	   0x11800090007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"GMX2_TB_REG"                 ,	   0x118000a0007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"GMX3_TB_REG"                 ,	   0x118000b0007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"GMX4_TB_REG"                 ,	   0x118000c0007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX1_TX000_APPEND"           ,	   0x1180009000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX1_TX001_APPEND"           ,	   0x1180009000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX1_TX002_APPEND"           ,	   0x1180009001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX1_TX003_APPEND"           ,	   0x1180009001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX2_TX000_APPEND"           ,	   0x118000a000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX2_TX001_APPEND"           ,	   0x118000a000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX2_TX002_APPEND"           ,	   0x118000a001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX2_TX003_APPEND"           ,	   0x118000a001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX3_TX000_APPEND"           ,	   0x118000b000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX3_TX001_APPEND"           ,	   0x118000b000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX3_TX002_APPEND"           ,	   0x118000b001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX3_TX003_APPEND"           ,	   0x118000b001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX4_TX000_APPEND"           ,	   0x118000c000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX4_TX001_APPEND"           ,	   0x118000c000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX4_TX002_APPEND"           ,	   0x118000c001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX4_TX003_APPEND"           ,	   0x118000c001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX1_TX000_BURST"            ,	   0x1180009000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX1_TX001_BURST"            ,	   0x1180009000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX1_TX002_BURST"            ,	   0x1180009001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX1_TX003_BURST"            ,	   0x1180009001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX2_TX000_BURST"            ,	   0x118000a000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX2_TX001_BURST"            ,	   0x118000a000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX2_TX002_BURST"            ,	   0x118000a001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX2_TX003_BURST"            ,	   0x118000a001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX3_TX000_BURST"            ,	   0x118000b000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX3_TX001_BURST"            ,	   0x118000b000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX3_TX002_BURST"            ,	   0x118000b001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX3_TX003_BURST"            ,	   0x118000b001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX4_TX000_BURST"            ,	   0x118000c000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX4_TX001_BURST"            ,	   0x118000c000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX4_TX002_BURST"            ,	   0x118000c001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX4_TX003_BURST"            ,	   0x118000c001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"GMX0_TX000_CBFC_XOFF"        ,	   0x11800080005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX1_TX000_CBFC_XOFF"        ,	   0x11800090005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX2_TX000_CBFC_XOFF"        ,	   0x118000a0005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX3_TX000_CBFC_XOFF"        ,	   0x118000b0005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX4_TX000_CBFC_XOFF"        ,	   0x118000c0005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"GMX0_TX000_CBFC_XON"         ,	   0x11800080005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX1_TX000_CBFC_XON"         ,	   0x11800090005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX2_TX000_CBFC_XON"         ,	   0x118000a0005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX3_TX000_CBFC_XON"         ,	   0x118000b0005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX4_TX000_CBFC_XON"         ,	   0x118000c0005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX1_TX000_CTL"              ,	   0x1180009000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX1_TX001_CTL"              ,	   0x1180009000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX1_TX002_CTL"              ,	   0x1180009001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX1_TX003_CTL"              ,	   0x1180009001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX2_TX000_CTL"              ,	   0x118000a000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX2_TX001_CTL"              ,	   0x118000a000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX2_TX002_CTL"              ,	   0x118000a001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX2_TX003_CTL"              ,	   0x118000a001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX3_TX000_CTL"              ,	   0x118000b000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX3_TX001_CTL"              ,	   0x118000b000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX3_TX002_CTL"              ,	   0x118000b001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX3_TX003_CTL"              ,	   0x118000b001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX4_TX000_CTL"              ,	   0x118000c000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX4_TX001_CTL"              ,	   0x118000c000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX4_TX002_CTL"              ,	   0x118000c001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX4_TX003_CTL"              ,	   0x118000c001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX1_TX000_MIN_PKT"          ,	   0x1180009000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX1_TX001_MIN_PKT"          ,	   0x1180009000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX1_TX002_MIN_PKT"          ,	   0x1180009001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX1_TX003_MIN_PKT"          ,	   0x1180009001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX2_TX000_MIN_PKT"          ,	   0x118000a000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX2_TX001_MIN_PKT"          ,	   0x118000a000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX2_TX002_MIN_PKT"          ,	   0x118000a001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX2_TX003_MIN_PKT"          ,	   0x118000a001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX3_TX000_MIN_PKT"          ,	   0x118000b000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX3_TX001_MIN_PKT"          ,	   0x118000b000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX3_TX002_MIN_PKT"          ,	   0x118000b001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX3_TX003_MIN_PKT"          ,	   0x118000b001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX4_TX000_MIN_PKT"          ,	   0x118000c000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX4_TX001_MIN_PKT"          ,	   0x118000c000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX4_TX002_MIN_PKT"          ,	   0x118000c001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX4_TX003_MIN_PKT"          ,	   0x118000c001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX1_TX000_PAUSE_PKT_INTERVAL",	   0x1180009000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180009000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX1_TX002_PAUSE_PKT_INTERVAL",	   0x1180009001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180009001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX2_TX000_PAUSE_PKT_INTERVAL",	   0x118000a000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX2_TX001_PAUSE_PKT_INTERVAL",	   0x118000a000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX2_TX002_PAUSE_PKT_INTERVAL",	   0x118000a001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX2_TX003_PAUSE_PKT_INTERVAL",	   0x118000a001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX3_TX000_PAUSE_PKT_INTERVAL",	   0x118000b000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX3_TX001_PAUSE_PKT_INTERVAL",	   0x118000b000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX3_TX002_PAUSE_PKT_INTERVAL",	   0x118000b001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX3_TX003_PAUSE_PKT_INTERVAL",	   0x118000b001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX4_TX000_PAUSE_PKT_INTERVAL",	   0x118000c000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX4_TX001_PAUSE_PKT_INTERVAL",	   0x118000c000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX4_TX002_PAUSE_PKT_INTERVAL",	   0x118000c001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX4_TX003_PAUSE_PKT_INTERVAL",	   0x118000c001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX1_TX000_PAUSE_PKT_TIME"   ,	   0x1180009000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180009000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX1_TX002_PAUSE_PKT_TIME"   ,	   0x1180009001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180009001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX2_TX000_PAUSE_PKT_TIME"   ,	   0x118000a000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX2_TX001_PAUSE_PKT_TIME"   ,	   0x118000a000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX2_TX002_PAUSE_PKT_TIME"   ,	   0x118000a001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX2_TX003_PAUSE_PKT_TIME"   ,	   0x118000a001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX3_TX000_PAUSE_PKT_TIME"   ,	   0x118000b000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX3_TX001_PAUSE_PKT_TIME"   ,	   0x118000b000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX3_TX002_PAUSE_PKT_TIME"   ,	   0x118000b001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX3_TX003_PAUSE_PKT_TIME"   ,	   0x118000b001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX4_TX000_PAUSE_PKT_TIME"   ,	   0x118000c000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX4_TX001_PAUSE_PKT_TIME"   ,	   0x118000c000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX4_TX002_PAUSE_PKT_TIME"   ,	   0x118000c001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX4_TX003_PAUSE_PKT_TIME"   ,	   0x118000c001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX1_TX000_PAUSE_TOGO"       ,	   0x1180009000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180009000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX1_TX002_PAUSE_TOGO"       ,	   0x1180009001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180009001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX2_TX000_PAUSE_TOGO"       ,	   0x118000a000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX2_TX001_PAUSE_TOGO"       ,	   0x118000a000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX2_TX002_PAUSE_TOGO"       ,	   0x118000a001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX2_TX003_PAUSE_TOGO"       ,	   0x118000a001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX3_TX000_PAUSE_TOGO"       ,	   0x118000b000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX3_TX001_PAUSE_TOGO"       ,	   0x118000b000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX3_TX002_PAUSE_TOGO"       ,	   0x118000b001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX3_TX003_PAUSE_TOGO"       ,	   0x118000b001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX4_TX000_PAUSE_TOGO"       ,	   0x118000c000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX4_TX001_PAUSE_TOGO"       ,	   0x118000c000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX4_TX002_PAUSE_TOGO"       ,	   0x118000c001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX4_TX003_PAUSE_TOGO"       ,	   0x118000c001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX1_TX000_PAUSE_ZERO"       ,	   0x1180009000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180009000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX1_TX002_PAUSE_ZERO"       ,	   0x1180009001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180009001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX2_TX000_PAUSE_ZERO"       ,	   0x118000a000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX2_TX001_PAUSE_ZERO"       ,	   0x118000a000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX2_TX002_PAUSE_ZERO"       ,	   0x118000a001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX2_TX003_PAUSE_ZERO"       ,	   0x118000a001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX3_TX000_PAUSE_ZERO"       ,	   0x118000b000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX3_TX001_PAUSE_ZERO"       ,	   0x118000b000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX3_TX002_PAUSE_ZERO"       ,	   0x118000b001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX3_TX003_PAUSE_ZERO"       ,	   0x118000b001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX4_TX000_PAUSE_ZERO"       ,	   0x118000c000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX4_TX001_PAUSE_ZERO"       ,	   0x118000c000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX4_TX002_PAUSE_ZERO"       ,	   0x118000c001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX4_TX003_PAUSE_ZERO"       ,	   0x118000c001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"GMX0_TX000_PIPE"             ,	   0x1180008000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX0_TX001_PIPE"             ,	   0x1180008000b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX0_TX002_PIPE"             ,	   0x1180008001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX0_TX003_PIPE"             ,	   0x1180008001b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX1_TX000_PIPE"             ,	   0x1180009000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX1_TX001_PIPE"             ,	   0x1180009000b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX1_TX002_PIPE"             ,	   0x1180009001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX1_TX003_PIPE"             ,	   0x1180009001b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX2_TX000_PIPE"             ,	   0x118000a000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX2_TX001_PIPE"             ,	   0x118000a000b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX2_TX002_PIPE"             ,	   0x118000a001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX2_TX003_PIPE"             ,	   0x118000a001b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX3_TX000_PIPE"             ,	   0x118000b000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX3_TX001_PIPE"             ,	   0x118000b000b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX3_TX002_PIPE"             ,	   0x118000b001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX3_TX003_PIPE"             ,	   0x118000b001b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX4_TX000_PIPE"             ,	   0x118000c000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX4_TX001_PIPE"             ,	   0x118000c000b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX4_TX002_PIPE"             ,	   0x118000c001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX4_TX003_PIPE"             ,	   0x118000c001b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"GMX0_TX000_SGMII_CTL"        ,	   0x1180008000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX0_TX002_SGMII_CTL"        ,	   0x1180008001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX0_TX003_SGMII_CTL"        ,	   0x1180008001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX1_TX000_SGMII_CTL"        ,	   0x1180009000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX1_TX001_SGMII_CTL"        ,	   0x1180009000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX1_TX002_SGMII_CTL"        ,	   0x1180009001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX1_TX003_SGMII_CTL"        ,	   0x1180009001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX2_TX000_SGMII_CTL"        ,	   0x118000a000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX2_TX001_SGMII_CTL"        ,	   0x118000a000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX2_TX002_SGMII_CTL"        ,	   0x118000a001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX2_TX003_SGMII_CTL"        ,	   0x118000a001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX3_TX000_SGMII_CTL"        ,	   0x118000b000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX3_TX001_SGMII_CTL"        ,	   0x118000b000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX3_TX002_SGMII_CTL"        ,	   0x118000b001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX3_TX003_SGMII_CTL"        ,	   0x118000b001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX4_TX000_SGMII_CTL"        ,	   0x118000c000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX4_TX001_SGMII_CTL"        ,	   0x118000c000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX4_TX002_SGMII_CTL"        ,	   0x118000c001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX4_TX003_SGMII_CTL"        ,	   0x118000c001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX1_TX000_SLOT"             ,	   0x1180009000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX1_TX001_SLOT"             ,	   0x1180009000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX1_TX002_SLOT"             ,	   0x1180009001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX1_TX003_SLOT"             ,	   0x1180009001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX2_TX000_SLOT"             ,	   0x118000a000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX2_TX001_SLOT"             ,	   0x118000a000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX2_TX002_SLOT"             ,	   0x118000a001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX2_TX003_SLOT"             ,	   0x118000a001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX3_TX000_SLOT"             ,	   0x118000b000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX3_TX001_SLOT"             ,	   0x118000b000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX3_TX002_SLOT"             ,	   0x118000b001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX3_TX003_SLOT"             ,	   0x118000b001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX4_TX000_SLOT"             ,	   0x118000c000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX4_TX001_SLOT"             ,	   0x118000c000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX4_TX002_SLOT"             ,	   0x118000c001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX4_TX003_SLOT"             ,	   0x118000c001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX1_TX000_SOFT_PAUSE"       ,	   0x1180009000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180009000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX1_TX002_SOFT_PAUSE"       ,	   0x1180009001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180009001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX2_TX000_SOFT_PAUSE"       ,	   0x118000a000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX2_TX001_SOFT_PAUSE"       ,	   0x118000a000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX2_TX002_SOFT_PAUSE"       ,	   0x118000a001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX2_TX003_SOFT_PAUSE"       ,	   0x118000a001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX3_TX000_SOFT_PAUSE"       ,	   0x118000b000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX3_TX001_SOFT_PAUSE"       ,	   0x118000b000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX3_TX002_SOFT_PAUSE"       ,	   0x118000b001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX3_TX003_SOFT_PAUSE"       ,	   0x118000b001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX4_TX000_SOFT_PAUSE"       ,	   0x118000c000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX4_TX001_SOFT_PAUSE"       ,	   0x118000c000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX4_TX002_SOFT_PAUSE"       ,	   0x118000c001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX4_TX003_SOFT_PAUSE"       ,	   0x118000c001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX1_TX000_STAT0"            ,	   0x1180009000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX1_TX001_STAT0"            ,	   0x1180009000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX1_TX002_STAT0"            ,	   0x1180009001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX1_TX003_STAT0"            ,	   0x1180009001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX2_TX000_STAT0"            ,	   0x118000a000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX2_TX001_STAT0"            ,	   0x118000a000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX2_TX002_STAT0"            ,	   0x118000a001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX2_TX003_STAT0"            ,	   0x118000a001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX3_TX000_STAT0"            ,	   0x118000b000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX3_TX001_STAT0"            ,	   0x118000b000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX3_TX002_STAT0"            ,	   0x118000b001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX3_TX003_STAT0"            ,	   0x118000b001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX4_TX000_STAT0"            ,	   0x118000c000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX4_TX001_STAT0"            ,	   0x118000c000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX4_TX002_STAT0"            ,	   0x118000c001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX4_TX003_STAT0"            ,	   0x118000c001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX1_TX000_STAT1"            ,	   0x1180009000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX1_TX001_STAT1"            ,	   0x1180009000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX1_TX002_STAT1"            ,	   0x1180009001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX1_TX003_STAT1"            ,	   0x1180009001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX2_TX000_STAT1"            ,	   0x118000a000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX2_TX001_STAT1"            ,	   0x118000a000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX2_TX002_STAT1"            ,	   0x118000a001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX2_TX003_STAT1"            ,	   0x118000a001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX3_TX000_STAT1"            ,	   0x118000b000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX3_TX001_STAT1"            ,	   0x118000b000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX3_TX002_STAT1"            ,	   0x118000b001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX3_TX003_STAT1"            ,	   0x118000b001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX4_TX000_STAT1"            ,	   0x118000c000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX4_TX001_STAT1"            ,	   0x118000c000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX4_TX002_STAT1"            ,	   0x118000c001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX4_TX003_STAT1"            ,	   0x118000c001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX1_TX000_STAT2"            ,	   0x1180009000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX1_TX001_STAT2"            ,	   0x1180009000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX1_TX002_STAT2"            ,	   0x1180009001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX1_TX003_STAT2"            ,	   0x1180009001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX2_TX000_STAT2"            ,	   0x118000a000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX2_TX001_STAT2"            ,	   0x118000a000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX2_TX002_STAT2"            ,	   0x118000a001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX2_TX003_STAT2"            ,	   0x118000a001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX3_TX000_STAT2"            ,	   0x118000b000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX3_TX001_STAT2"            ,	   0x118000b000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX3_TX002_STAT2"            ,	   0x118000b001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX3_TX003_STAT2"            ,	   0x118000b001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX4_TX000_STAT2"            ,	   0x118000c000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX4_TX001_STAT2"            ,	   0x118000c000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX4_TX002_STAT2"            ,	   0x118000c001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX4_TX003_STAT2"            ,	   0x118000c001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX1_TX000_STAT3"            ,	   0x1180009000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX1_TX001_STAT3"            ,	   0x1180009000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX1_TX002_STAT3"            ,	   0x1180009001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX1_TX003_STAT3"            ,	   0x1180009001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX2_TX000_STAT3"            ,	   0x118000a000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX2_TX001_STAT3"            ,	   0x118000a000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX2_TX002_STAT3"            ,	   0x118000a001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX2_TX003_STAT3"            ,	   0x118000a001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX3_TX000_STAT3"            ,	   0x118000b000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX3_TX001_STAT3"            ,	   0x118000b000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX3_TX002_STAT3"            ,	   0x118000b001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX3_TX003_STAT3"            ,	   0x118000b001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX4_TX000_STAT3"            ,	   0x118000c000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX4_TX001_STAT3"            ,	   0x118000c000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX4_TX002_STAT3"            ,	   0x118000c001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX4_TX003_STAT3"            ,	   0x118000c001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX1_TX000_STAT4"            ,	   0x11800090002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX1_TX001_STAT4"            ,	   0x1180009000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX1_TX002_STAT4"            ,	   0x11800090012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX1_TX003_STAT4"            ,	   0x1180009001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX2_TX000_STAT4"            ,	   0x118000a0002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX2_TX001_STAT4"            ,	   0x118000a000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX2_TX002_STAT4"            ,	   0x118000a0012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX2_TX003_STAT4"            ,	   0x118000a001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX3_TX000_STAT4"            ,	   0x118000b0002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX3_TX001_STAT4"            ,	   0x118000b000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX3_TX002_STAT4"            ,	   0x118000b0012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX3_TX003_STAT4"            ,	   0x118000b001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX4_TX000_STAT4"            ,	   0x118000c0002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX4_TX001_STAT4"            ,	   0x118000c000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX4_TX002_STAT4"            ,	   0x118000c0012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX4_TX003_STAT4"            ,	   0x118000c001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX1_TX000_STAT5"            ,	   0x11800090002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX1_TX001_STAT5"            ,	   0x1180009000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX1_TX002_STAT5"            ,	   0x11800090012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX1_TX003_STAT5"            ,	   0x1180009001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX2_TX000_STAT5"            ,	   0x118000a0002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX2_TX001_STAT5"            ,	   0x118000a000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX2_TX002_STAT5"            ,	   0x118000a0012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX2_TX003_STAT5"            ,	   0x118000a001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX3_TX000_STAT5"            ,	   0x118000b0002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX3_TX001_STAT5"            ,	   0x118000b000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX3_TX002_STAT5"            ,	   0x118000b0012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX3_TX003_STAT5"            ,	   0x118000b001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX4_TX000_STAT5"            ,	   0x118000c0002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX4_TX001_STAT5"            ,	   0x118000c000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX4_TX002_STAT5"            ,	   0x118000c0012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX4_TX003_STAT5"            ,	   0x118000c001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX1_TX000_STAT6"            ,	   0x11800090002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX1_TX001_STAT6"            ,	   0x1180009000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX1_TX002_STAT6"            ,	   0x11800090012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX1_TX003_STAT6"            ,	   0x1180009001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX2_TX000_STAT6"            ,	   0x118000a0002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX2_TX001_STAT6"            ,	   0x118000a000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX2_TX002_STAT6"            ,	   0x118000a0012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX2_TX003_STAT6"            ,	   0x118000a001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX3_TX000_STAT6"            ,	   0x118000b0002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX3_TX001_STAT6"            ,	   0x118000b000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX3_TX002_STAT6"            ,	   0x118000b0012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX3_TX003_STAT6"            ,	   0x118000b001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX4_TX000_STAT6"            ,	   0x118000c0002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX4_TX001_STAT6"            ,	   0x118000c000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX4_TX002_STAT6"            ,	   0x118000c0012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX4_TX003_STAT6"            ,	   0x118000c001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX1_TX000_STAT7"            ,	   0x11800090002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX1_TX001_STAT7"            ,	   0x1180009000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX1_TX002_STAT7"            ,	   0x11800090012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX1_TX003_STAT7"            ,	   0x1180009001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX2_TX000_STAT7"            ,	   0x118000a0002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX2_TX001_STAT7"            ,	   0x118000a000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX2_TX002_STAT7"            ,	   0x118000a0012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX2_TX003_STAT7"            ,	   0x118000a001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX3_TX000_STAT7"            ,	   0x118000b0002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX3_TX001_STAT7"            ,	   0x118000b000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX3_TX002_STAT7"            ,	   0x118000b0012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX3_TX003_STAT7"            ,	   0x118000b001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX4_TX000_STAT7"            ,	   0x118000c0002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX4_TX001_STAT7"            ,	   0x118000c000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX4_TX002_STAT7"            ,	   0x118000c0012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX4_TX003_STAT7"            ,	   0x118000c001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX1_TX000_STAT8"            ,	   0x11800090002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX1_TX001_STAT8"            ,	   0x1180009000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX1_TX002_STAT8"            ,	   0x11800090012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX1_TX003_STAT8"            ,	   0x1180009001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX2_TX000_STAT8"            ,	   0x118000a0002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX2_TX001_STAT8"            ,	   0x118000a000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX2_TX002_STAT8"            ,	   0x118000a0012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX2_TX003_STAT8"            ,	   0x118000a001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX3_TX000_STAT8"            ,	   0x118000b0002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX3_TX001_STAT8"            ,	   0x118000b000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX3_TX002_STAT8"            ,	   0x118000b0012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX3_TX003_STAT8"            ,	   0x118000b001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX4_TX000_STAT8"            ,	   0x118000c0002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX4_TX001_STAT8"            ,	   0x118000c000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX4_TX002_STAT8"            ,	   0x118000c0012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX4_TX003_STAT8"            ,	   0x118000c001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX1_TX000_STAT9"            ,	   0x11800090002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX1_TX001_STAT9"            ,	   0x1180009000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX1_TX002_STAT9"            ,	   0x11800090012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX1_TX003_STAT9"            ,	   0x1180009001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX2_TX000_STAT9"            ,	   0x118000a0002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX2_TX001_STAT9"            ,	   0x118000a000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX2_TX002_STAT9"            ,	   0x118000a0012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX2_TX003_STAT9"            ,	   0x118000a001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX3_TX000_STAT9"            ,	   0x118000b0002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX3_TX001_STAT9"            ,	   0x118000b000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX3_TX002_STAT9"            ,	   0x118000b0012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX3_TX003_STAT9"            ,	   0x118000b001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX4_TX000_STAT9"            ,	   0x118000c0002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX4_TX001_STAT9"            ,	   0x118000c000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX4_TX002_STAT9"            ,	   0x118000c0012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX4_TX003_STAT9"            ,	   0x118000c001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX1_TX000_STATS_CTL"        ,	   0x1180009000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX1_TX001_STATS_CTL"        ,	   0x1180009000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX1_TX002_STATS_CTL"        ,	   0x1180009001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX1_TX003_STATS_CTL"        ,	   0x1180009001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX2_TX000_STATS_CTL"        ,	   0x118000a000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX2_TX001_STATS_CTL"        ,	   0x118000a000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX2_TX002_STATS_CTL"        ,	   0x118000a001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX2_TX003_STATS_CTL"        ,	   0x118000a001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX3_TX000_STATS_CTL"        ,	   0x118000b000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX3_TX001_STATS_CTL"        ,	   0x118000b000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX3_TX002_STATS_CTL"        ,	   0x118000b001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX3_TX003_STATS_CTL"        ,	   0x118000b001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX4_TX000_STATS_CTL"        ,	   0x118000c000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX4_TX001_STATS_CTL"        ,	   0x118000c000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX4_TX002_STATS_CTL"        ,	   0x118000c001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX4_TX003_STATS_CTL"        ,	   0x118000c001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX1_TX000_THRESH"           ,	   0x1180009000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX1_TX001_THRESH"           ,	   0x1180009000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX1_TX002_THRESH"           ,	   0x1180009001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX1_TX003_THRESH"           ,	   0x1180009001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX2_TX000_THRESH"           ,	   0x118000a000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX2_TX001_THRESH"           ,	   0x118000a000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX2_TX002_THRESH"           ,	   0x118000a001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX2_TX003_THRESH"           ,	   0x118000a001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX3_TX000_THRESH"           ,	   0x118000b000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX3_TX001_THRESH"           ,	   0x118000b000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX3_TX002_THRESH"           ,	   0x118000b001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX3_TX003_THRESH"           ,	   0x118000b001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX4_TX000_THRESH"           ,	   0x118000c000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX4_TX001_THRESH"           ,	   0x118000c000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX4_TX002_THRESH"           ,	   0x118000c001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX4_TX003_THRESH"           ,	   0x118000c001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"GMX0_TX_BP"                  ,	   0x11800080004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"GMX1_TX_BP"                  ,	   0x11800090004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"GMX2_TX_BP"                  ,	   0x118000a0004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"GMX3_TX_BP"                  ,	   0x118000b0004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"GMX4_TX_BP"                  ,	   0x118000c0004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"GMX1_TX_COL_ATTEMPT"         ,	   0x1180009000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"GMX2_TX_COL_ATTEMPT"         ,	   0x118000a000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"GMX3_TX_COL_ATTEMPT"         ,	   0x118000b000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"GMX4_TX_COL_ATTEMPT"         ,	   0x118000c000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"GMX1_TX_CORRUPT"             ,	   0x11800090004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"GMX2_TX_CORRUPT"             ,	   0x118000a0004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"GMX3_TX_CORRUPT"             ,	   0x118000b0004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"GMX4_TX_CORRUPT"             ,	   0x118000c0004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"GMX0_TX_HG2_REG1"            ,	   0x1180008000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"GMX1_TX_HG2_REG1"            ,	   0x1180009000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"GMX2_TX_HG2_REG1"            ,	   0x118000a000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"GMX3_TX_HG2_REG1"            ,	   0x118000b000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"GMX4_TX_HG2_REG1"            ,	   0x118000c000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"GMX0_TX_HG2_REG2"            ,	   0x1180008000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"GMX1_TX_HG2_REG2"            ,	   0x1180009000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"GMX2_TX_HG2_REG2"            ,	   0x118000a000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"GMX3_TX_HG2_REG2"            ,	   0x118000b000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"GMX4_TX_HG2_REG2"            ,	   0x118000c000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"GMX1_TX_IFG"                 ,	   0x1180009000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"GMX2_TX_IFG"                 ,	   0x118000a000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"GMX3_TX_IFG"                 ,	   0x118000b000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"GMX4_TX_IFG"                 ,	   0x118000c000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"GMX1_TX_INT_EN"              ,	   0x1180009000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"GMX2_TX_INT_EN"              ,	   0x118000a000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"GMX3_TX_INT_EN"              ,	   0x118000b000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"GMX4_TX_INT_EN"              ,	   0x118000c000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"GMX1_TX_INT_REG"             ,	   0x1180009000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"GMX2_TX_INT_REG"             ,	   0x118000a000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"GMX3_TX_INT_REG"             ,	   0x118000b000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"GMX4_TX_INT_REG"             ,	   0x118000c000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"GMX1_TX_JAM"                 ,	   0x1180009000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"GMX2_TX_JAM"                 ,	   0x118000a000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"GMX3_TX_JAM"                 ,	   0x118000b000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"GMX4_TX_JAM"                 ,	   0x118000c000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"GMX1_TX_LFSR"                ,	   0x11800090004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"GMX2_TX_LFSR"                ,	   0x118000a0004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"GMX3_TX_LFSR"                ,	   0x118000b0004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"GMX4_TX_LFSR"                ,	   0x118000c0004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"GMX1_TX_OVR_BP"              ,	   0x11800090004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"GMX2_TX_OVR_BP"              ,	   0x118000a0004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"GMX3_TX_OVR_BP"              ,	   0x118000b0004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"GMX4_TX_OVR_BP"              ,	   0x118000c0004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800090004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"GMX2_TX_PAUSE_PKT_DMAC"      ,	   0x118000a0004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"GMX3_TX_PAUSE_PKT_DMAC"      ,	   0x118000b0004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"GMX4_TX_PAUSE_PKT_DMAC"      ,	   0x118000c0004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800090004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"GMX2_TX_PAUSE_PKT_TYPE"      ,	   0x118000a0004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"GMX3_TX_PAUSE_PKT_TYPE"      ,	   0x118000b0004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"GMX4_TX_PAUSE_PKT_TYPE"      ,	   0x118000c0004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"GMX1_TX_PRTS"                ,	   0x1180009000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"GMX2_TX_PRTS"                ,	   0x118000a000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"GMX3_TX_PRTS"                ,	   0x118000b000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"GMX4_TX_PRTS"                ,	   0x118000c000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"GMX0_TX_XAUI_CTL"            ,	   0x1180008000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"GMX1_TX_XAUI_CTL"            ,	   0x1180009000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"GMX2_TX_XAUI_CTL"            ,	   0x118000a000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"GMX3_TX_XAUI_CTL"            ,	   0x118000b000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"GMX4_TX_XAUI_CTL"            ,	   0x118000c000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"GMX0_XAUI_EXT_LOOPBACK"      ,	   0x1180008000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"GMX1_XAUI_EXT_LOOPBACK"      ,	   0x1180009000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"GMX2_XAUI_EXT_LOOPBACK"      ,	   0x118000a000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"GMX3_XAUI_EXT_LOOPBACK"      ,	   0x118000b000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"GMX4_XAUI_EXT_LOOPBACK"      ,	   0x118000c000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"GPIO_BIT_CFG3"               ,	   0x1070000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"GPIO_BIT_CFG4"               ,	   0x1070000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"GPIO_BIT_CFG5"               ,	   0x1070000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"GPIO_BIT_CFG6"               ,	   0x1070000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"GPIO_BIT_CFG7"               ,	   0x1070000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"GPIO_BIT_CFG8"               ,	   0x1070000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"GPIO_BIT_CFG9"               ,	   0x1070000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"GPIO_BIT_CFG10"              ,	   0x1070000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"GPIO_BIT_CFG11"              ,	   0x1070000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"GPIO_BIT_CFG12"              ,	   0x1070000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"GPIO_CLK_GEN0"               ,	   0x10700000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
+	{"GPIO_CLK_GEN1"               ,	   0x10700000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
+	{"GPIO_CLK_GEN2"               ,	   0x10700000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
+	{"GPIO_CLK_GEN3"               ,	   0x10700000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
+	{"GPIO_CLK_QLM0"               ,	   0x10700000008e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	463},
+	{"GPIO_CLK_QLM1"               ,	   0x10700000008e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	463},
+	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	464},
+	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	465},
+	{"GPIO_TIM_CTL"                ,	   0x10700000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	466},
+	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	467},
+	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	468},
+	{"ILK_BIST_SUM"                ,	   0x1180014000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"ILK_GBL_CFG"                 ,	   0x1180014000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"ILK_GBL_INT"                 ,	   0x1180014000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"ILK_GBL_INT_EN"              ,	   0x1180014000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"ILK_INT_SUM"                 ,	   0x1180014000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	473},
+	{"ILK_LNE_DBG"                 ,	   0x1180014030008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	474},
+	{"ILK_LNE_STS_MSG"             ,	   0x1180014030000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	475},
+	{"ILK_RX0_CFG0"                ,	   0x1180014020000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	476},
+	{"ILK_RX1_CFG0"                ,	   0x1180014024000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	476},
+	{"ILK_RX0_CFG1"                ,	   0x1180014020008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	477},
+	{"ILK_RX1_CFG1"                ,	   0x1180014024008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	477},
+	{"ILK_RX0_FLOW_CTL0"           ,	   0x1180014020090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	478},
+	{"ILK_RX1_FLOW_CTL0"           ,	   0x1180014024090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	478},
+	{"ILK_RX0_FLOW_CTL1"           ,	   0x1180014020098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"ILK_RX1_FLOW_CTL1"           ,	   0x1180014024098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"ILK_RX0_IDX_CAL"             ,	   0x11800140200a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	480},
+	{"ILK_RX1_IDX_CAL"             ,	   0x11800140240a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	480},
+	{"ILK_RX0_IDX_STAT0"           ,	   0x1180014020070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"ILK_RX1_IDX_STAT0"           ,	   0x1180014024070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"ILK_RX0_IDX_STAT1"           ,	   0x1180014020078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	482},
+	{"ILK_RX1_IDX_STAT1"           ,	   0x1180014024078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	482},
+	{"ILK_RX0_INT"                 ,	   0x1180014020010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	483},
+	{"ILK_RX1_INT"                 ,	   0x1180014024010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	483},
+	{"ILK_RX0_INT_EN"              ,	   0x1180014020018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	484},
+	{"ILK_RX1_INT_EN"              ,	   0x1180014024018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	484},
+	{"ILK_RX0_JABBER"              ,	   0x11800140200b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	485},
+	{"ILK_RX1_JABBER"              ,	   0x11800140240b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	485},
+	{"ILK_RX0_MEM_CAL0"            ,	   0x11800140200a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	486},
+	{"ILK_RX1_MEM_CAL0"            ,	   0x11800140240a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	486},
+	{"ILK_RX0_MEM_CAL1"            ,	   0x11800140200b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	487},
+	{"ILK_RX1_MEM_CAL1"            ,	   0x11800140240b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	487},
+	{"ILK_RX0_MEM_STAT0"           ,	   0x1180014020080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	488},
+	{"ILK_RX1_MEM_STAT0"           ,	   0x1180014024080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	488},
+	{"ILK_RX0_MEM_STAT1"           ,	   0x1180014020088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	489},
+	{"ILK_RX1_MEM_STAT1"           ,	   0x1180014024088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	489},
+	{"ILK_RX0_RID"                 ,	   0x11800140200c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	490},
+	{"ILK_RX1_RID"                 ,	   0x11800140240c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	490},
+	{"ILK_RX0_STAT0"               ,	   0x1180014020020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
+	{"ILK_RX1_STAT0"               ,	   0x1180014024020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
+	{"ILK_RX0_STAT1"               ,	   0x1180014020028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	492},
+	{"ILK_RX1_STAT1"               ,	   0x1180014024028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	492},
+	{"ILK_RX0_STAT2"               ,	   0x1180014020030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	493},
+	{"ILK_RX1_STAT2"               ,	   0x1180014024030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	493},
+	{"ILK_RX0_STAT3"               ,	   0x1180014020038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	494},
+	{"ILK_RX1_STAT3"               ,	   0x1180014024038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	494},
+	{"ILK_RX0_STAT4"               ,	   0x1180014020040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	495},
+	{"ILK_RX1_STAT4"               ,	   0x1180014024040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	495},
+	{"ILK_RX0_STAT5"               ,	   0x1180014020048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"ILK_RX1_STAT5"               ,	   0x1180014024048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"ILK_RX0_STAT6"               ,	   0x1180014020050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"ILK_RX1_STAT6"               ,	   0x1180014024050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"ILK_RX0_STAT7"               ,	   0x1180014020058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"ILK_RX1_STAT7"               ,	   0x1180014024058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"ILK_RX0_STAT8"               ,	   0x1180014020060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"ILK_RX1_STAT8"               ,	   0x1180014024060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"ILK_RX0_STAT9"               ,	   0x1180014020068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"ILK_RX1_STAT9"               ,	   0x1180014024068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"ILK_RX_LNE0_CFG"             ,	   0x1180014038000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"ILK_RX_LNE1_CFG"             ,	   0x1180014038400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"ILK_RX_LNE2_CFG"             ,	   0x1180014038800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"ILK_RX_LNE3_CFG"             ,	   0x1180014038c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"ILK_RX_LNE4_CFG"             ,	   0x1180014039000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"ILK_RX_LNE5_CFG"             ,	   0x1180014039400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"ILK_RX_LNE6_CFG"             ,	   0x1180014039800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"ILK_RX_LNE7_CFG"             ,	   0x1180014039c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"ILK_RX_LNE0_INT"             ,	   0x1180014038008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"ILK_RX_LNE1_INT"             ,	   0x1180014038408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"ILK_RX_LNE2_INT"             ,	   0x1180014038808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"ILK_RX_LNE3_INT"             ,	   0x1180014038c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"ILK_RX_LNE4_INT"             ,	   0x1180014039008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"ILK_RX_LNE5_INT"             ,	   0x1180014039408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"ILK_RX_LNE6_INT"             ,	   0x1180014039808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"ILK_RX_LNE7_INT"             ,	   0x1180014039c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"ILK_RX_LNE0_INT_EN"          ,	   0x1180014038010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"ILK_RX_LNE1_INT_EN"          ,	   0x1180014038410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"ILK_RX_LNE2_INT_EN"          ,	   0x1180014038810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"ILK_RX_LNE3_INT_EN"          ,	   0x1180014038c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"ILK_RX_LNE4_INT_EN"          ,	   0x1180014039010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"ILK_RX_LNE5_INT_EN"          ,	   0x1180014039410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"ILK_RX_LNE6_INT_EN"          ,	   0x1180014039810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"ILK_RX_LNE7_INT_EN"          ,	   0x1180014039c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"ILK_RX_LNE0_STAT0"           ,	   0x1180014038018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"ILK_RX_LNE1_STAT0"           ,	   0x1180014038418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"ILK_RX_LNE2_STAT0"           ,	   0x1180014038818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"ILK_RX_LNE3_STAT0"           ,	   0x1180014038c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"ILK_RX_LNE4_STAT0"           ,	   0x1180014039018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"ILK_RX_LNE5_STAT0"           ,	   0x1180014039418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"ILK_RX_LNE6_STAT0"           ,	   0x1180014039818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"ILK_RX_LNE7_STAT0"           ,	   0x1180014039c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"ILK_RX_LNE0_STAT1"           ,	   0x1180014038020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"ILK_RX_LNE1_STAT1"           ,	   0x1180014038420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"ILK_RX_LNE2_STAT1"           ,	   0x1180014038820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"ILK_RX_LNE3_STAT1"           ,	   0x1180014038c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"ILK_RX_LNE4_STAT1"           ,	   0x1180014039020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"ILK_RX_LNE5_STAT1"           ,	   0x1180014039420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"ILK_RX_LNE6_STAT1"           ,	   0x1180014039820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"ILK_RX_LNE7_STAT1"           ,	   0x1180014039c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"ILK_RX_LNE0_STAT2"           ,	   0x1180014038028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"ILK_RX_LNE1_STAT2"           ,	   0x1180014038428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"ILK_RX_LNE2_STAT2"           ,	   0x1180014038828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"ILK_RX_LNE3_STAT2"           ,	   0x1180014038c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"ILK_RX_LNE4_STAT2"           ,	   0x1180014039028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"ILK_RX_LNE5_STAT2"           ,	   0x1180014039428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"ILK_RX_LNE6_STAT2"           ,	   0x1180014039828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"ILK_RX_LNE7_STAT2"           ,	   0x1180014039c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"ILK_RX_LNE0_STAT3"           ,	   0x1180014038030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"ILK_RX_LNE1_STAT3"           ,	   0x1180014038430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"ILK_RX_LNE2_STAT3"           ,	   0x1180014038830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"ILK_RX_LNE3_STAT3"           ,	   0x1180014038c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"ILK_RX_LNE4_STAT3"           ,	   0x1180014039030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"ILK_RX_LNE5_STAT3"           ,	   0x1180014039430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"ILK_RX_LNE6_STAT3"           ,	   0x1180014039830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"ILK_RX_LNE7_STAT3"           ,	   0x1180014039c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"ILK_RX_LNE0_STAT4"           ,	   0x1180014038038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"ILK_RX_LNE1_STAT4"           ,	   0x1180014038438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"ILK_RX_LNE2_STAT4"           ,	   0x1180014038838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"ILK_RX_LNE3_STAT4"           ,	   0x1180014038c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"ILK_RX_LNE4_STAT4"           ,	   0x1180014039038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"ILK_RX_LNE5_STAT4"           ,	   0x1180014039438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"ILK_RX_LNE6_STAT4"           ,	   0x1180014039838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"ILK_RX_LNE7_STAT4"           ,	   0x1180014039c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"ILK_RX_LNE0_STAT5"           ,	   0x1180014038040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"ILK_RX_LNE1_STAT5"           ,	   0x1180014038440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"ILK_RX_LNE2_STAT5"           ,	   0x1180014038840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"ILK_RX_LNE3_STAT5"           ,	   0x1180014038c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"ILK_RX_LNE4_STAT5"           ,	   0x1180014039040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"ILK_RX_LNE5_STAT5"           ,	   0x1180014039440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"ILK_RX_LNE6_STAT5"           ,	   0x1180014039840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"ILK_RX_LNE7_STAT5"           ,	   0x1180014039c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"ILK_RX_LNE0_STAT6"           ,	   0x1180014038048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"ILK_RX_LNE1_STAT6"           ,	   0x1180014038448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"ILK_RX_LNE2_STAT6"           ,	   0x1180014038848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"ILK_RX_LNE3_STAT6"           ,	   0x1180014038c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"ILK_RX_LNE4_STAT6"           ,	   0x1180014039048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"ILK_RX_LNE5_STAT6"           ,	   0x1180014039448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"ILK_RX_LNE6_STAT6"           ,	   0x1180014039848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"ILK_RX_LNE7_STAT6"           ,	   0x1180014039c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"ILK_RX_LNE0_STAT7"           ,	   0x1180014038050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"ILK_RX_LNE1_STAT7"           ,	   0x1180014038450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"ILK_RX_LNE2_STAT7"           ,	   0x1180014038850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"ILK_RX_LNE3_STAT7"           ,	   0x1180014038c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"ILK_RX_LNE4_STAT7"           ,	   0x1180014039050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"ILK_RX_LNE5_STAT7"           ,	   0x1180014039450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"ILK_RX_LNE6_STAT7"           ,	   0x1180014039850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"ILK_RX_LNE7_STAT7"           ,	   0x1180014039c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"ILK_RX_LNE0_STAT8"           ,	   0x1180014038058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"ILK_RX_LNE1_STAT8"           ,	   0x1180014038458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"ILK_RX_LNE2_STAT8"           ,	   0x1180014038858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"ILK_RX_LNE3_STAT8"           ,	   0x1180014038c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"ILK_RX_LNE4_STAT8"           ,	   0x1180014039058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"ILK_RX_LNE5_STAT8"           ,	   0x1180014039458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"ILK_RX_LNE6_STAT8"           ,	   0x1180014039858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"ILK_RX_LNE7_STAT8"           ,	   0x1180014039c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"ILK_RX_LNE0_STAT9"           ,	   0x1180014038060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"ILK_RX_LNE1_STAT9"           ,	   0x1180014038460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"ILK_RX_LNE2_STAT9"           ,	   0x1180014038860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"ILK_RX_LNE3_STAT9"           ,	   0x1180014038c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"ILK_RX_LNE4_STAT9"           ,	   0x1180014039060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"ILK_RX_LNE5_STAT9"           ,	   0x1180014039460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"ILK_RX_LNE6_STAT9"           ,	   0x1180014039860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"ILK_RX_LNE7_STAT9"           ,	   0x1180014039c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"ILK_RXF_IDX_PMAP"            ,	   0x1180014000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"ILK_RXF_MEM_PMAP"            ,	   0x1180014000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
+	{"ILK_SER_CFG"                 ,	   0x1180014000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	516},
+	{"ILK_TX0_CFG0"                ,	   0x1180014010000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	517},
+	{"ILK_TX1_CFG0"                ,	   0x1180014014000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	517},
+	{"ILK_TX0_CFG1"                ,	   0x1180014010008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	518},
+	{"ILK_TX1_CFG1"                ,	   0x1180014014008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	518},
+	{"ILK_TX0_DBG"                 ,	   0x1180014010070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
+	{"ILK_TX1_DBG"                 ,	   0x1180014014070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
+	{"ILK_TX0_FLOW_CTL0"           ,	   0x1180014010048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
+	{"ILK_TX1_FLOW_CTL0"           ,	   0x1180014014048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
+	{"ILK_TX0_FLOW_CTL1"           ,	   0x1180014010050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"ILK_TX1_FLOW_CTL1"           ,	   0x1180014014050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"ILK_TX0_IDX_CAL"             ,	   0x1180014010058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
+	{"ILK_TX1_IDX_CAL"             ,	   0x1180014014058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
+	{"ILK_TX0_IDX_PMAP"            ,	   0x1180014010010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
+	{"ILK_TX1_IDX_PMAP"            ,	   0x1180014014010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
+	{"ILK_TX0_IDX_STAT0"           ,	   0x1180014010020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
+	{"ILK_TX1_IDX_STAT0"           ,	   0x1180014014020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
+	{"ILK_TX0_IDX_STAT1"           ,	   0x1180014010028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
+	{"ILK_TX1_IDX_STAT1"           ,	   0x1180014014028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
+	{"ILK_TX0_INT"                 ,	   0x1180014010078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
+	{"ILK_TX1_INT"                 ,	   0x1180014014078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
+	{"ILK_TX0_INT_EN"              ,	   0x1180014010080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	527},
+	{"ILK_TX1_INT_EN"              ,	   0x1180014014080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	527},
+	{"ILK_TX0_MEM_CAL0"            ,	   0x1180014010060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
+	{"ILK_TX1_MEM_CAL0"            ,	   0x1180014014060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
+	{"ILK_TX0_MEM_CAL1"            ,	   0x1180014010068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	529},
+	{"ILK_TX1_MEM_CAL1"            ,	   0x1180014014068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	529},
+	{"ILK_TX0_MEM_PMAP"            ,	   0x1180014010018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
+	{"ILK_TX1_MEM_PMAP"            ,	   0x1180014014018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
+	{"ILK_TX0_MEM_STAT0"           ,	   0x1180014010030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	531},
+	{"ILK_TX1_MEM_STAT0"           ,	   0x1180014014030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	531},
+	{"ILK_TX0_MEM_STAT1"           ,	   0x1180014010038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"ILK_TX1_MEM_STAT1"           ,	   0x1180014014038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"ILK_TX0_PIPE"                ,	   0x1180014010088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	533},
+	{"ILK_TX1_PIPE"                ,	   0x1180014014088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	533},
+	{"ILK_TX0_RMATCH"              ,	   0x1180014010040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	534},
+	{"ILK_TX1_RMATCH"              ,	   0x1180014014040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	534},
+	{"IOB1_BIST_STATUS"            ,	   0x11800f00107f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	535},
+	{"IOB1_CTL_STATUS"             ,	   0x11800f0010050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	536},
+	{"IOB1_TO_CMB_CREDITS"         ,	   0x11800f00100b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	537},
+	{"IOB_BIST_STATUS"             ,	   0x11800f00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	538},
+	{"IOB_CTL_STATUS"              ,	   0x11800f0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	539},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800f0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800f0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800f0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	542},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800f0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	543},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800f0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	544},
+	{"IOB_INT_ENB"                 ,	   0x11800f0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"IOB_INT_SUM"                 ,	   0x11800f0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800f0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800f0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	548},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800f00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	549},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800f0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	550},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800f00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	551},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800f0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	552},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800f0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
+	{"IOB_TO_CMB_CREDITS"          ,	   0x11800f00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
+	{"IOB_TO_NCB_DID_00_CREDITS"   ,	   0x11800f0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"IOB_TO_NCB_DID_111_CREDITS"  ,	   0x11800f0000b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
+	{"IOB_TO_NCB_DID_223_CREDITS"  ,	   0x11800f0000ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
+	{"IOB_TO_NCB_DID_24_CREDITS"   ,	   0x11800f00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"IOB_TO_NCB_DID_32_CREDITS"   ,	   0x11800f0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
+	{"IOB_TO_NCB_DID_40_CREDITS"   ,	   0x11800f0000940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
+	{"IOB_TO_NCB_DID_55_CREDITS"   ,	   0x11800f00009b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
+	{"IOB_TO_NCB_DID_64_CREDITS"   ,	   0x11800f0000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
+	{"IOB_TO_NCB_DID_79_CREDITS"   ,	   0x11800f0000a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
+	{"IOB_TO_NCB_DID_96_CREDITS"   ,	   0x11800f0000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
+	{"IOB_TO_NCB_DID_98_CREDITS"   ,	   0x11800f0000b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	567},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	568},
+	{"IPD_BIST_STATUS"             ,	   0x14f00000007f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	569},
+	{"IPD_BPID0_MBUF_TH"           ,	   0x14f0000002000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID1_MBUF_TH"           ,	   0x14f0000002008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID2_MBUF_TH"           ,	   0x14f0000002010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID3_MBUF_TH"           ,	   0x14f0000002018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID4_MBUF_TH"           ,	   0x14f0000002020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID5_MBUF_TH"           ,	   0x14f0000002028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID6_MBUF_TH"           ,	   0x14f0000002030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID7_MBUF_TH"           ,	   0x14f0000002038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID8_MBUF_TH"           ,	   0x14f0000002040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID9_MBUF_TH"           ,	   0x14f0000002048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID10_MBUF_TH"          ,	   0x14f0000002050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID11_MBUF_TH"          ,	   0x14f0000002058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID12_MBUF_TH"          ,	   0x14f0000002060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID13_MBUF_TH"          ,	   0x14f0000002068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID14_MBUF_TH"          ,	   0x14f0000002070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID15_MBUF_TH"          ,	   0x14f0000002078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID16_MBUF_TH"          ,	   0x14f0000002080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID17_MBUF_TH"          ,	   0x14f0000002088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID18_MBUF_TH"          ,	   0x14f0000002090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID19_MBUF_TH"          ,	   0x14f0000002098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID20_MBUF_TH"          ,	   0x14f00000020a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID21_MBUF_TH"          ,	   0x14f00000020a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID22_MBUF_TH"          ,	   0x14f00000020b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID23_MBUF_TH"          ,	   0x14f00000020b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID24_MBUF_TH"          ,	   0x14f00000020c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID25_MBUF_TH"          ,	   0x14f00000020c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID26_MBUF_TH"          ,	   0x14f00000020d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID27_MBUF_TH"          ,	   0x14f00000020d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID28_MBUF_TH"          ,	   0x14f00000020e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID29_MBUF_TH"          ,	   0x14f00000020e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID30_MBUF_TH"          ,	   0x14f00000020f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID31_MBUF_TH"          ,	   0x14f00000020f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID32_MBUF_TH"          ,	   0x14f0000002100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID33_MBUF_TH"          ,	   0x14f0000002108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID34_MBUF_TH"          ,	   0x14f0000002110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID35_MBUF_TH"          ,	   0x14f0000002118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID36_MBUF_TH"          ,	   0x14f0000002120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID37_MBUF_TH"          ,	   0x14f0000002128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID38_MBUF_TH"          ,	   0x14f0000002130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID39_MBUF_TH"          ,	   0x14f0000002138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID40_MBUF_TH"          ,	   0x14f0000002140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID41_MBUF_TH"          ,	   0x14f0000002148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID42_MBUF_TH"          ,	   0x14f0000002150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID43_MBUF_TH"          ,	   0x14f0000002158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID44_MBUF_TH"          ,	   0x14f0000002160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID45_MBUF_TH"          ,	   0x14f0000002168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID46_MBUF_TH"          ,	   0x14f0000002170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID47_MBUF_TH"          ,	   0x14f0000002178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID48_MBUF_TH"          ,	   0x14f0000002180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID49_MBUF_TH"          ,	   0x14f0000002188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID50_MBUF_TH"          ,	   0x14f0000002190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID51_MBUF_TH"          ,	   0x14f0000002198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID52_MBUF_TH"          ,	   0x14f00000021a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID53_MBUF_TH"          ,	   0x14f00000021a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID54_MBUF_TH"          ,	   0x14f00000021b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID55_MBUF_TH"          ,	   0x14f00000021b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID56_MBUF_TH"          ,	   0x14f00000021c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID57_MBUF_TH"          ,	   0x14f00000021c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID58_MBUF_TH"          ,	   0x14f00000021d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID59_MBUF_TH"          ,	   0x14f00000021d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID60_MBUF_TH"          ,	   0x14f00000021e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID61_MBUF_TH"          ,	   0x14f00000021e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID62_MBUF_TH"          ,	   0x14f00000021f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID63_MBUF_TH"          ,	   0x14f00000021f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"IPD_BPID_BP_COUNTER0"        ,	   0x14f0000003000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER1"        ,	   0x14f0000003008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER2"        ,	   0x14f0000003010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER3"        ,	   0x14f0000003018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER4"        ,	   0x14f0000003020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER5"        ,	   0x14f0000003028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER6"        ,	   0x14f0000003030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER7"        ,	   0x14f0000003038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER8"        ,	   0x14f0000003040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER9"        ,	   0x14f0000003048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER10"       ,	   0x14f0000003050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER11"       ,	   0x14f0000003058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER12"       ,	   0x14f0000003060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER13"       ,	   0x14f0000003068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER14"       ,	   0x14f0000003070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER15"       ,	   0x14f0000003078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER16"       ,	   0x14f0000003080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER17"       ,	   0x14f0000003088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER18"       ,	   0x14f0000003090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER19"       ,	   0x14f0000003098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER20"       ,	   0x14f00000030a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER21"       ,	   0x14f00000030a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER22"       ,	   0x14f00000030b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER23"       ,	   0x14f00000030b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER24"       ,	   0x14f00000030c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER25"       ,	   0x14f00000030c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER26"       ,	   0x14f00000030d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER27"       ,	   0x14f00000030d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER28"       ,	   0x14f00000030e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER29"       ,	   0x14f00000030e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER30"       ,	   0x14f00000030f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER31"       ,	   0x14f00000030f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER32"       ,	   0x14f0000003100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER33"       ,	   0x14f0000003108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER34"       ,	   0x14f0000003110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER35"       ,	   0x14f0000003118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER36"       ,	   0x14f0000003120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER37"       ,	   0x14f0000003128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER38"       ,	   0x14f0000003130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER39"       ,	   0x14f0000003138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER40"       ,	   0x14f0000003140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER41"       ,	   0x14f0000003148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER42"       ,	   0x14f0000003150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER43"       ,	   0x14f0000003158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER44"       ,	   0x14f0000003160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER45"       ,	   0x14f0000003168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER46"       ,	   0x14f0000003170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER47"       ,	   0x14f0000003178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER48"       ,	   0x14f0000003180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER49"       ,	   0x14f0000003188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER50"       ,	   0x14f0000003190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER51"       ,	   0x14f0000003198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER52"       ,	   0x14f00000031a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER53"       ,	   0x14f00000031a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER54"       ,	   0x14f00000031b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER55"       ,	   0x14f00000031b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER56"       ,	   0x14f00000031c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER57"       ,	   0x14f00000031c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER58"       ,	   0x14f00000031d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER59"       ,	   0x14f00000031d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER60"       ,	   0x14f00000031e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER61"       ,	   0x14f00000031e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER62"       ,	   0x14f00000031f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_BPID_BP_COUNTER63"       ,	   0x14f00000031f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"IPD_CLK_COUNT"               ,	   0x14f0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	572},
+	{"IPD_CREDITS"                 ,	   0x14f0000004410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	573},
+	{"IPD_CTL_STATUS"              ,	   0x14f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	574},
+	{"IPD_ECC_CTL"                 ,	   0x14f0000004408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	575},
+	{"IPD_FREE_PTR_FIFO_CTL"       ,	   0x14f0000000780ull,	CVMX_CSR_DB_TYPE_NCB,	64,	576},
+	{"IPD_FREE_PTR_VALUE"          ,	   0x14f0000000788ull,	CVMX_CSR_DB_TYPE_NCB,	64,	577},
+	{"IPD_HOLD_PTR_FIFO_CTL"       ,	   0x14f0000000790ull,	CVMX_CSR_DB_TYPE_NCB,	64,	578},
+	{"IPD_INT_ENB"                 ,	   0x14f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	579},
+	{"IPD_INT_SUM"                 ,	   0x14f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	580},
+	{"IPD_NEXT_PKT_PTR"            ,	   0x14f00000007a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	581},
+	{"IPD_NEXT_WQE_PTR"            ,	   0x14f00000007a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	582},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"IPD_ON_BP_DROP_PKT0"         ,	   0x14f0000004100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	584},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	585},
+	{"IPD_PKT_ERR"                 ,	   0x14f00000003f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	586},
+	{"IPD_PORT_PTR_FIFO_CTL"       ,	   0x14f0000000798ull,	CVMX_CSR_DB_TYPE_NCB,	64,	587},
+	{"IPD_PORT_QOS_0_CNT"          ,	   0x14f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_1_CNT"          ,	   0x14f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_2_CNT"          ,	   0x14f0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_3_CNT"          ,	   0x14f00000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_4_CNT"          ,	   0x14f00000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_5_CNT"          ,	   0x14f00000008b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_6_CNT"          ,	   0x14f00000008b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_7_CNT"          ,	   0x14f00000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_8_CNT"          ,	   0x14f00000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_9_CNT"          ,	   0x14f00000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_10_CNT"         ,	   0x14f00000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_11_CNT"         ,	   0x14f00000008e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_12_CNT"         ,	   0x14f00000008e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_13_CNT"         ,	   0x14f00000008f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_14_CNT"         ,	   0x14f00000008f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_15_CNT"         ,	   0x14f0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_16_CNT"         ,	   0x14f0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_17_CNT"         ,	   0x14f0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_18_CNT"         ,	   0x14f0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_19_CNT"         ,	   0x14f0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_20_CNT"         ,	   0x14f0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_21_CNT"         ,	   0x14f0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_22_CNT"         ,	   0x14f0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_23_CNT"         ,	   0x14f0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_24_CNT"         ,	   0x14f0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_25_CNT"         ,	   0x14f0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_26_CNT"         ,	   0x14f0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_27_CNT"         ,	   0x14f0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_28_CNT"         ,	   0x14f0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_29_CNT"         ,	   0x14f0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_30_CNT"         ,	   0x14f0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_31_CNT"         ,	   0x14f0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_32_CNT"         ,	   0x14f0000000988ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_33_CNT"         ,	   0x14f0000000990ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_34_CNT"         ,	   0x14f0000000998ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_35_CNT"         ,	   0x14f00000009a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_36_CNT"         ,	   0x14f00000009a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_37_CNT"         ,	   0x14f00000009b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_38_CNT"         ,	   0x14f00000009b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_39_CNT"         ,	   0x14f00000009c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_40_CNT"         ,	   0x14f00000009c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_41_CNT"         ,	   0x14f00000009d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_42_CNT"         ,	   0x14f00000009d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_43_CNT"         ,	   0x14f00000009e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_44_CNT"         ,	   0x14f00000009e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_45_CNT"         ,	   0x14f00000009f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_46_CNT"         ,	   0x14f00000009f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_47_CNT"         ,	   0x14f0000000a00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_48_CNT"         ,	   0x14f0000000a08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_49_CNT"         ,	   0x14f0000000a10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_50_CNT"         ,	   0x14f0000000a18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_51_CNT"         ,	   0x14f0000000a20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_52_CNT"         ,	   0x14f0000000a28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_53_CNT"         ,	   0x14f0000000a30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_54_CNT"         ,	   0x14f0000000a38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_55_CNT"         ,	   0x14f0000000a40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_56_CNT"         ,	   0x14f0000000a48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_57_CNT"         ,	   0x14f0000000a50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_58_CNT"         ,	   0x14f0000000a58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_59_CNT"         ,	   0x14f0000000a60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_60_CNT"         ,	   0x14f0000000a68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_61_CNT"         ,	   0x14f0000000a70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_62_CNT"         ,	   0x14f0000000a78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_63_CNT"         ,	   0x14f0000000a80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_64_CNT"         ,	   0x14f0000000a88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_65_CNT"         ,	   0x14f0000000a90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_66_CNT"         ,	   0x14f0000000a98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_67_CNT"         ,	   0x14f0000000aa0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_68_CNT"         ,	   0x14f0000000aa8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_69_CNT"         ,	   0x14f0000000ab0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_70_CNT"         ,	   0x14f0000000ab8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_71_CNT"         ,	   0x14f0000000ac0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_72_CNT"         ,	   0x14f0000000ac8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_73_CNT"         ,	   0x14f0000000ad0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_74_CNT"         ,	   0x14f0000000ad8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_75_CNT"         ,	   0x14f0000000ae0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_76_CNT"         ,	   0x14f0000000ae8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_77_CNT"         ,	   0x14f0000000af0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_78_CNT"         ,	   0x14f0000000af8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_79_CNT"         ,	   0x14f0000000b00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_80_CNT"         ,	   0x14f0000000b08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_81_CNT"         ,	   0x14f0000000b10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_82_CNT"         ,	   0x14f0000000b18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_83_CNT"         ,	   0x14f0000000b20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_84_CNT"         ,	   0x14f0000000b28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_85_CNT"         ,	   0x14f0000000b30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_86_CNT"         ,	   0x14f0000000b38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_87_CNT"         ,	   0x14f0000000b40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_88_CNT"         ,	   0x14f0000000b48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_89_CNT"         ,	   0x14f0000000b50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_90_CNT"         ,	   0x14f0000000b58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_91_CNT"         ,	   0x14f0000000b60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_92_CNT"         ,	   0x14f0000000b68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_93_CNT"         ,	   0x14f0000000b70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_94_CNT"         ,	   0x14f0000000b78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_95_CNT"         ,	   0x14f0000000b80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_96_CNT"         ,	   0x14f0000000b88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_97_CNT"         ,	   0x14f0000000b90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_98_CNT"         ,	   0x14f0000000b98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_99_CNT"         ,	   0x14f0000000ba0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_100_CNT"        ,	   0x14f0000000ba8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_101_CNT"        ,	   0x14f0000000bb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_102_CNT"        ,	   0x14f0000000bb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_103_CNT"        ,	   0x14f0000000bc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_104_CNT"        ,	   0x14f0000000bc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_105_CNT"        ,	   0x14f0000000bd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_106_CNT"        ,	   0x14f0000000bd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_107_CNT"        ,	   0x14f0000000be0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_108_CNT"        ,	   0x14f0000000be8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_109_CNT"        ,	   0x14f0000000bf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_110_CNT"        ,	   0x14f0000000bf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_111_CNT"        ,	   0x14f0000000c00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_112_CNT"        ,	   0x14f0000000c08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_113_CNT"        ,	   0x14f0000000c10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_114_CNT"        ,	   0x14f0000000c18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_115_CNT"        ,	   0x14f0000000c20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_116_CNT"        ,	   0x14f0000000c28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_117_CNT"        ,	   0x14f0000000c30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_118_CNT"        ,	   0x14f0000000c38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_119_CNT"        ,	   0x14f0000000c40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_120_CNT"        ,	   0x14f0000000c48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_121_CNT"        ,	   0x14f0000000c50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_122_CNT"        ,	   0x14f0000000c58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_123_CNT"        ,	   0x14f0000000c60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_124_CNT"        ,	   0x14f0000000c68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_125_CNT"        ,	   0x14f0000000c70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_126_CNT"        ,	   0x14f0000000c78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_127_CNT"        ,	   0x14f0000000c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_128_CNT"        ,	   0x14f0000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_129_CNT"        ,	   0x14f0000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_130_CNT"        ,	   0x14f0000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_131_CNT"        ,	   0x14f0000000ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_132_CNT"        ,	   0x14f0000000ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_133_CNT"        ,	   0x14f0000000cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_134_CNT"        ,	   0x14f0000000cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_135_CNT"        ,	   0x14f0000000cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_136_CNT"        ,	   0x14f0000000cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_137_CNT"        ,	   0x14f0000000cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_138_CNT"        ,	   0x14f0000000cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_139_CNT"        ,	   0x14f0000000ce0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_140_CNT"        ,	   0x14f0000000ce8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_141_CNT"        ,	   0x14f0000000cf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_142_CNT"        ,	   0x14f0000000cf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_143_CNT"        ,	   0x14f0000000d00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_144_CNT"        ,	   0x14f0000000d08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_145_CNT"        ,	   0x14f0000000d10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_146_CNT"        ,	   0x14f0000000d18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_147_CNT"        ,	   0x14f0000000d20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_148_CNT"        ,	   0x14f0000000d28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_149_CNT"        ,	   0x14f0000000d30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_150_CNT"        ,	   0x14f0000000d38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_151_CNT"        ,	   0x14f0000000d40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_152_CNT"        ,	   0x14f0000000d48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_153_CNT"        ,	   0x14f0000000d50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_154_CNT"        ,	   0x14f0000000d58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_155_CNT"        ,	   0x14f0000000d60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_156_CNT"        ,	   0x14f0000000d68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_157_CNT"        ,	   0x14f0000000d70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_158_CNT"        ,	   0x14f0000000d78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_159_CNT"        ,	   0x14f0000000d80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_160_CNT"        ,	   0x14f0000000d88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_161_CNT"        ,	   0x14f0000000d90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_162_CNT"        ,	   0x14f0000000d98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_163_CNT"        ,	   0x14f0000000da0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_164_CNT"        ,	   0x14f0000000da8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_165_CNT"        ,	   0x14f0000000db0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_166_CNT"        ,	   0x14f0000000db8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_167_CNT"        ,	   0x14f0000000dc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_168_CNT"        ,	   0x14f0000000dc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_169_CNT"        ,	   0x14f0000000dd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_170_CNT"        ,	   0x14f0000000dd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_171_CNT"        ,	   0x14f0000000de0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_172_CNT"        ,	   0x14f0000000de8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_173_CNT"        ,	   0x14f0000000df0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_174_CNT"        ,	   0x14f0000000df8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_175_CNT"        ,	   0x14f0000000e00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_176_CNT"        ,	   0x14f0000000e08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_177_CNT"        ,	   0x14f0000000e10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_178_CNT"        ,	   0x14f0000000e18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_179_CNT"        ,	   0x14f0000000e20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_180_CNT"        ,	   0x14f0000000e28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_181_CNT"        ,	   0x14f0000000e30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_182_CNT"        ,	   0x14f0000000e38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_183_CNT"        ,	   0x14f0000000e40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_184_CNT"        ,	   0x14f0000000e48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_185_CNT"        ,	   0x14f0000000e50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_186_CNT"        ,	   0x14f0000000e58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_187_CNT"        ,	   0x14f0000000e60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_188_CNT"        ,	   0x14f0000000e68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_189_CNT"        ,	   0x14f0000000e70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_190_CNT"        ,	   0x14f0000000e78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_191_CNT"        ,	   0x14f0000000e80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_192_CNT"        ,	   0x14f0000000e88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_193_CNT"        ,	   0x14f0000000e90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_194_CNT"        ,	   0x14f0000000e98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_195_CNT"        ,	   0x14f0000000ea0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_196_CNT"        ,	   0x14f0000000ea8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_197_CNT"        ,	   0x14f0000000eb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_198_CNT"        ,	   0x14f0000000eb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_199_CNT"        ,	   0x14f0000000ec0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_200_CNT"        ,	   0x14f0000000ec8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_201_CNT"        ,	   0x14f0000000ed0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_202_CNT"        ,	   0x14f0000000ed8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_203_CNT"        ,	   0x14f0000000ee0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_204_CNT"        ,	   0x14f0000000ee8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_205_CNT"        ,	   0x14f0000000ef0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_206_CNT"        ,	   0x14f0000000ef8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_207_CNT"        ,	   0x14f0000000f00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_208_CNT"        ,	   0x14f0000000f08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_209_CNT"        ,	   0x14f0000000f10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_210_CNT"        ,	   0x14f0000000f18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_211_CNT"        ,	   0x14f0000000f20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_212_CNT"        ,	   0x14f0000000f28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_213_CNT"        ,	   0x14f0000000f30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_214_CNT"        ,	   0x14f0000000f38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_215_CNT"        ,	   0x14f0000000f40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_216_CNT"        ,	   0x14f0000000f48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_217_CNT"        ,	   0x14f0000000f50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_218_CNT"        ,	   0x14f0000000f58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_219_CNT"        ,	   0x14f0000000f60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_220_CNT"        ,	   0x14f0000000f68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_221_CNT"        ,	   0x14f0000000f70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_222_CNT"        ,	   0x14f0000000f78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_223_CNT"        ,	   0x14f0000000f80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_224_CNT"        ,	   0x14f0000000f88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_225_CNT"        ,	   0x14f0000000f90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_226_CNT"        ,	   0x14f0000000f98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_227_CNT"        ,	   0x14f0000000fa0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_228_CNT"        ,	   0x14f0000000fa8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_229_CNT"        ,	   0x14f0000000fb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_230_CNT"        ,	   0x14f0000000fb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_231_CNT"        ,	   0x14f0000000fc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_232_CNT"        ,	   0x14f0000000fc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_233_CNT"        ,	   0x14f0000000fd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_234_CNT"        ,	   0x14f0000000fd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_235_CNT"        ,	   0x14f0000000fe0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_236_CNT"        ,	   0x14f0000000fe8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_237_CNT"        ,	   0x14f0000000ff0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_238_CNT"        ,	   0x14f0000000ff8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_239_CNT"        ,	   0x14f0000001000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_240_CNT"        ,	   0x14f0000001008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_241_CNT"        ,	   0x14f0000001010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_242_CNT"        ,	   0x14f0000001018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_243_CNT"        ,	   0x14f0000001020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_244_CNT"        ,	   0x14f0000001028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_245_CNT"        ,	   0x14f0000001030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_246_CNT"        ,	   0x14f0000001038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_247_CNT"        ,	   0x14f0000001040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_248_CNT"        ,	   0x14f0000001048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_249_CNT"        ,	   0x14f0000001050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_250_CNT"        ,	   0x14f0000001058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_251_CNT"        ,	   0x14f0000001060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_252_CNT"        ,	   0x14f0000001068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_253_CNT"        ,	   0x14f0000001070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_254_CNT"        ,	   0x14f0000001078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_255_CNT"        ,	   0x14f0000001080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_256_CNT"        ,	   0x14f0000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_257_CNT"        ,	   0x14f0000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_258_CNT"        ,	   0x14f0000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_259_CNT"        ,	   0x14f00000010a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_260_CNT"        ,	   0x14f00000010a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_261_CNT"        ,	   0x14f00000010b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_262_CNT"        ,	   0x14f00000010b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_263_CNT"        ,	   0x14f00000010c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_264_CNT"        ,	   0x14f00000010c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_265_CNT"        ,	   0x14f00000010d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_266_CNT"        ,	   0x14f00000010d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_267_CNT"        ,	   0x14f00000010e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_268_CNT"        ,	   0x14f00000010e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_269_CNT"        ,	   0x14f00000010f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_270_CNT"        ,	   0x14f00000010f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_271_CNT"        ,	   0x14f0000001100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_272_CNT"        ,	   0x14f0000001108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_273_CNT"        ,	   0x14f0000001110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_274_CNT"        ,	   0x14f0000001118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_275_CNT"        ,	   0x14f0000001120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_276_CNT"        ,	   0x14f0000001128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_277_CNT"        ,	   0x14f0000001130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_278_CNT"        ,	   0x14f0000001138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_279_CNT"        ,	   0x14f0000001140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_280_CNT"        ,	   0x14f0000001148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_281_CNT"        ,	   0x14f0000001150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_282_CNT"        ,	   0x14f0000001158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_283_CNT"        ,	   0x14f0000001160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_284_CNT"        ,	   0x14f0000001168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_285_CNT"        ,	   0x14f0000001170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_286_CNT"        ,	   0x14f0000001178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_287_CNT"        ,	   0x14f0000001180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_288_CNT"        ,	   0x14f0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_289_CNT"        ,	   0x14f0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_290_CNT"        ,	   0x14f0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_291_CNT"        ,	   0x14f00000011a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_292_CNT"        ,	   0x14f00000011a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_293_CNT"        ,	   0x14f00000011b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_294_CNT"        ,	   0x14f00000011b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_295_CNT"        ,	   0x14f00000011c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_296_CNT"        ,	   0x14f00000011c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_297_CNT"        ,	   0x14f00000011d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_298_CNT"        ,	   0x14f00000011d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_299_CNT"        ,	   0x14f00000011e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_300_CNT"        ,	   0x14f00000011e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_301_CNT"        ,	   0x14f00000011f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_302_CNT"        ,	   0x14f00000011f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_303_CNT"        ,	   0x14f0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_304_CNT"        ,	   0x14f0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_305_CNT"        ,	   0x14f0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_306_CNT"        ,	   0x14f0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_307_CNT"        ,	   0x14f0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_308_CNT"        ,	   0x14f0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_309_CNT"        ,	   0x14f0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_310_CNT"        ,	   0x14f0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_311_CNT"        ,	   0x14f0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_312_CNT"        ,	   0x14f0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_313_CNT"        ,	   0x14f0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_314_CNT"        ,	   0x14f0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_315_CNT"        ,	   0x14f0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_316_CNT"        ,	   0x14f0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_317_CNT"        ,	   0x14f0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_318_CNT"        ,	   0x14f0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_319_CNT"        ,	   0x14f0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_320_CNT"        ,	   0x14f0000001288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_321_CNT"        ,	   0x14f0000001290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_322_CNT"        ,	   0x14f0000001298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_323_CNT"        ,	   0x14f00000012a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_324_CNT"        ,	   0x14f00000012a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_325_CNT"        ,	   0x14f00000012b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_326_CNT"        ,	   0x14f00000012b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_327_CNT"        ,	   0x14f00000012c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_328_CNT"        ,	   0x14f00000012c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_329_CNT"        ,	   0x14f00000012d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_330_CNT"        ,	   0x14f00000012d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_331_CNT"        ,	   0x14f00000012e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_332_CNT"        ,	   0x14f00000012e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_333_CNT"        ,	   0x14f00000012f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_334_CNT"        ,	   0x14f00000012f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_335_CNT"        ,	   0x14f0000001300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_336_CNT"        ,	   0x14f0000001308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_337_CNT"        ,	   0x14f0000001310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_338_CNT"        ,	   0x14f0000001318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_339_CNT"        ,	   0x14f0000001320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_340_CNT"        ,	   0x14f0000001328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_341_CNT"        ,	   0x14f0000001330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_342_CNT"        ,	   0x14f0000001338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_343_CNT"        ,	   0x14f0000001340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_344_CNT"        ,	   0x14f0000001348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_345_CNT"        ,	   0x14f0000001350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_346_CNT"        ,	   0x14f0000001358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_347_CNT"        ,	   0x14f0000001360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_348_CNT"        ,	   0x14f0000001368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_349_CNT"        ,	   0x14f0000001370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_350_CNT"        ,	   0x14f0000001378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_351_CNT"        ,	   0x14f0000001380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_352_CNT"        ,	   0x14f0000001388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_353_CNT"        ,	   0x14f0000001390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_354_CNT"        ,	   0x14f0000001398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_355_CNT"        ,	   0x14f00000013a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_356_CNT"        ,	   0x14f00000013a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_357_CNT"        ,	   0x14f00000013b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_358_CNT"        ,	   0x14f00000013b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_359_CNT"        ,	   0x14f00000013c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_360_CNT"        ,	   0x14f00000013c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_361_CNT"        ,	   0x14f00000013d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_362_CNT"        ,	   0x14f00000013d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_363_CNT"        ,	   0x14f00000013e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_364_CNT"        ,	   0x14f00000013e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_365_CNT"        ,	   0x14f00000013f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_366_CNT"        ,	   0x14f00000013f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_367_CNT"        ,	   0x14f0000001400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_368_CNT"        ,	   0x14f0000001408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_369_CNT"        ,	   0x14f0000001410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_370_CNT"        ,	   0x14f0000001418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_371_CNT"        ,	   0x14f0000001420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_372_CNT"        ,	   0x14f0000001428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_373_CNT"        ,	   0x14f0000001430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_374_CNT"        ,	   0x14f0000001438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_375_CNT"        ,	   0x14f0000001440ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_376_CNT"        ,	   0x14f0000001448ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_377_CNT"        ,	   0x14f0000001450ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_378_CNT"        ,	   0x14f0000001458ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_379_CNT"        ,	   0x14f0000001460ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_380_CNT"        ,	   0x14f0000001468ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_381_CNT"        ,	   0x14f0000001470ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_382_CNT"        ,	   0x14f0000001478ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_383_CNT"        ,	   0x14f0000001480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_384_CNT"        ,	   0x14f0000001488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_385_CNT"        ,	   0x14f0000001490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_386_CNT"        ,	   0x14f0000001498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_387_CNT"        ,	   0x14f00000014a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_388_CNT"        ,	   0x14f00000014a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_389_CNT"        ,	   0x14f00000014b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_390_CNT"        ,	   0x14f00000014b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_391_CNT"        ,	   0x14f00000014c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_392_CNT"        ,	   0x14f00000014c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_393_CNT"        ,	   0x14f00000014d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_394_CNT"        ,	   0x14f00000014d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_395_CNT"        ,	   0x14f00000014e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_396_CNT"        ,	   0x14f00000014e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_397_CNT"        ,	   0x14f00000014f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_398_CNT"        ,	   0x14f00000014f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_399_CNT"        ,	   0x14f0000001500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_400_CNT"        ,	   0x14f0000001508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_401_CNT"        ,	   0x14f0000001510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_402_CNT"        ,	   0x14f0000001518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_403_CNT"        ,	   0x14f0000001520ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_404_CNT"        ,	   0x14f0000001528ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_405_CNT"        ,	   0x14f0000001530ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_406_CNT"        ,	   0x14f0000001538ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_407_CNT"        ,	   0x14f0000001540ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_408_CNT"        ,	   0x14f0000001548ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_409_CNT"        ,	   0x14f0000001550ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_410_CNT"        ,	   0x14f0000001558ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_411_CNT"        ,	   0x14f0000001560ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_412_CNT"        ,	   0x14f0000001568ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_413_CNT"        ,	   0x14f0000001570ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_414_CNT"        ,	   0x14f0000001578ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_415_CNT"        ,	   0x14f0000001580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_416_CNT"        ,	   0x14f0000001588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_417_CNT"        ,	   0x14f0000001590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_418_CNT"        ,	   0x14f0000001598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_419_CNT"        ,	   0x14f00000015a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_420_CNT"        ,	   0x14f00000015a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_421_CNT"        ,	   0x14f00000015b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_422_CNT"        ,	   0x14f00000015b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_423_CNT"        ,	   0x14f00000015c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_424_CNT"        ,	   0x14f00000015c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_425_CNT"        ,	   0x14f00000015d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_426_CNT"        ,	   0x14f00000015d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_427_CNT"        ,	   0x14f00000015e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_428_CNT"        ,	   0x14f00000015e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_429_CNT"        ,	   0x14f00000015f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_430_CNT"        ,	   0x14f00000015f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_431_CNT"        ,	   0x14f0000001600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_432_CNT"        ,	   0x14f0000001608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_433_CNT"        ,	   0x14f0000001610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_434_CNT"        ,	   0x14f0000001618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_435_CNT"        ,	   0x14f0000001620ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_436_CNT"        ,	   0x14f0000001628ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_437_CNT"        ,	   0x14f0000001630ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_438_CNT"        ,	   0x14f0000001638ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_439_CNT"        ,	   0x14f0000001640ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_440_CNT"        ,	   0x14f0000001648ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_441_CNT"        ,	   0x14f0000001650ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_442_CNT"        ,	   0x14f0000001658ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_443_CNT"        ,	   0x14f0000001660ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_444_CNT"        ,	   0x14f0000001668ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_445_CNT"        ,	   0x14f0000001670ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_446_CNT"        ,	   0x14f0000001678ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_447_CNT"        ,	   0x14f0000001680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_448_CNT"        ,	   0x14f0000001688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_449_CNT"        ,	   0x14f0000001690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_450_CNT"        ,	   0x14f0000001698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_451_CNT"        ,	   0x14f00000016a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_452_CNT"        ,	   0x14f00000016a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_453_CNT"        ,	   0x14f00000016b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_454_CNT"        ,	   0x14f00000016b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_455_CNT"        ,	   0x14f00000016c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_456_CNT"        ,	   0x14f00000016c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_457_CNT"        ,	   0x14f00000016d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_458_CNT"        ,	   0x14f00000016d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_459_CNT"        ,	   0x14f00000016e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_460_CNT"        ,	   0x14f00000016e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_461_CNT"        ,	   0x14f00000016f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_462_CNT"        ,	   0x14f00000016f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_463_CNT"        ,	   0x14f0000001700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_464_CNT"        ,	   0x14f0000001708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_465_CNT"        ,	   0x14f0000001710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_466_CNT"        ,	   0x14f0000001718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_467_CNT"        ,	   0x14f0000001720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_468_CNT"        ,	   0x14f0000001728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_469_CNT"        ,	   0x14f0000001730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_470_CNT"        ,	   0x14f0000001738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_471_CNT"        ,	   0x14f0000001740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_472_CNT"        ,	   0x14f0000001748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_473_CNT"        ,	   0x14f0000001750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_474_CNT"        ,	   0x14f0000001758ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_475_CNT"        ,	   0x14f0000001760ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_476_CNT"        ,	   0x14f0000001768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_477_CNT"        ,	   0x14f0000001770ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_478_CNT"        ,	   0x14f0000001778ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_479_CNT"        ,	   0x14f0000001780ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_480_CNT"        ,	   0x14f0000001788ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_481_CNT"        ,	   0x14f0000001790ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_482_CNT"        ,	   0x14f0000001798ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_483_CNT"        ,	   0x14f00000017a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_484_CNT"        ,	   0x14f00000017a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_485_CNT"        ,	   0x14f00000017b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_486_CNT"        ,	   0x14f00000017b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_487_CNT"        ,	   0x14f00000017c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_488_CNT"        ,	   0x14f00000017c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_489_CNT"        ,	   0x14f00000017d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_490_CNT"        ,	   0x14f00000017d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_491_CNT"        ,	   0x14f00000017e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_492_CNT"        ,	   0x14f00000017e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_493_CNT"        ,	   0x14f00000017f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_494_CNT"        ,	   0x14f00000017f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_495_CNT"        ,	   0x14f0000001800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_496_CNT"        ,	   0x14f0000001808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_497_CNT"        ,	   0x14f0000001810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_498_CNT"        ,	   0x14f0000001818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_499_CNT"        ,	   0x14f0000001820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_500_CNT"        ,	   0x14f0000001828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_501_CNT"        ,	   0x14f0000001830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_502_CNT"        ,	   0x14f0000001838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_503_CNT"        ,	   0x14f0000001840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_504_CNT"        ,	   0x14f0000001848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_505_CNT"        ,	   0x14f0000001850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_506_CNT"        ,	   0x14f0000001858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_507_CNT"        ,	   0x14f0000001860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_508_CNT"        ,	   0x14f0000001868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_509_CNT"        ,	   0x14f0000001870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_510_CNT"        ,	   0x14f0000001878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_511_CNT"        ,	   0x14f0000001880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"IPD_PORT_QOS_INT0"           ,	   0x14f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	589},
+	{"IPD_PORT_QOS_INT1"           ,	   0x14f0000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	589},
+	{"IPD_PORT_QOS_INT2"           ,	   0x14f0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	589},
+	{"IPD_PORT_QOS_INT3"           ,	   0x14f0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	589},
+	{"IPD_PORT_QOS_INT4"           ,	   0x14f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	589},
+	{"IPD_PORT_QOS_INT5"           ,	   0x14f0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	589},
+	{"IPD_PORT_QOS_INT6"           ,	   0x14f0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	589},
+	{"IPD_PORT_QOS_INT7"           ,	   0x14f0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	589},
+	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	590},
+	{"IPD_PORT_QOS_INT_ENB1"       ,	   0x14f0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	590},
+	{"IPD_PORT_QOS_INT_ENB2"       ,	   0x14f0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	590},
+	{"IPD_PORT_QOS_INT_ENB3"       ,	   0x14f0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	590},
+	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	590},
+	{"IPD_PORT_QOS_INT_ENB5"       ,	   0x14f0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	590},
+	{"IPD_PORT_QOS_INT_ENB6"       ,	   0x14f0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	590},
+	{"IPD_PORT_QOS_INT_ENB7"       ,	   0x14f0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	590},
+	{"IPD_PORT_SOP0"               ,	   0x14f0000004400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	591},
+	{"IPD_PTR_COUNT"               ,	   0x14f0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	592},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	593},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	593},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	593},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	593},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	593},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	593},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	593},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	593},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14f0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	594},
+	{"IPD_RED_BPID_ENABLE0"        ,	   0x14f0000004200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	595},
+	{"IPD_RED_DELAY"               ,	   0x14f0000004300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	596},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14f00000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	597},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14f00000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	597},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14f00000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	597},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14f00000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	597},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14f0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	597},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14f0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	597},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14f0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	597},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14f0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	597},
+	{"IPD_REQ_WGT"                 ,	   0x14f0000004418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	598},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	599},
+	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	600},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	601},
+	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	602},
+	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	603},
+	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	604},
+	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"L2C_BIG_CTL"                 ,	   0x1180080800030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	606},
+	{"L2C_BST"                     ,	   0x11800808007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"L2C_BST_MEM0"                ,	   0x1180080c007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	608},
+	{"L2C_BST_MEM1"                ,	   0x1180080c407f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	608},
+	{"L2C_BST_MEM2"                ,	   0x1180080c807f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	608},
+	{"L2C_BST_MEM3"                ,	   0x1180080cc07f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	608},
+	{"L2C_BST_TDT0"                ,	   0x1180080a007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	609},
+	{"L2C_BST_TDT1"                ,	   0x1180080a407f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	609},
+	{"L2C_BST_TDT2"                ,	   0x1180080a807f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	609},
+	{"L2C_BST_TDT3"                ,	   0x1180080ac07f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	609},
+	{"L2C_BST_TTG0"                ,	   0x1180080a007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	610},
+	{"L2C_BST_TTG1"                ,	   0x1180080a407f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	610},
+	{"L2C_BST_TTG2"                ,	   0x1180080a807f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	610},
+	{"L2C_BST_TTG3"                ,	   0x1180080ac07f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	610},
+	{"L2C_COP0_MAP0"               ,	   0x1180080940000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1"               ,	   0x1180080940008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2"               ,	   0x1180080940010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3"               ,	   0x1180080940018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4"               ,	   0x1180080940020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5"               ,	   0x1180080940028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6"               ,	   0x1180080940030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7"               ,	   0x1180080940038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8"               ,	   0x1180080940040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP9"               ,	   0x1180080940048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP10"              ,	   0x1180080940050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP11"              ,	   0x1180080940058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP12"              ,	   0x1180080940060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP13"              ,	   0x1180080940068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP14"              ,	   0x1180080940070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP15"              ,	   0x1180080940078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16"              ,	   0x1180080940080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP17"              ,	   0x1180080940088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP18"              ,	   0x1180080940090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP19"              ,	   0x1180080940098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP20"              ,	   0x11800809400a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP21"              ,	   0x11800809400a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP22"              ,	   0x11800809400b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP23"              ,	   0x11800809400b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP24"              ,	   0x11800809400c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP25"              ,	   0x11800809400c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP26"              ,	   0x11800809400d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP27"              ,	   0x11800809400d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP28"              ,	   0x11800809400e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP29"              ,	   0x11800809400e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP30"              ,	   0x11800809400f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP31"              ,	   0x11800809400f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP32"              ,	   0x1180080940100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP33"              ,	   0x1180080940108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP34"              ,	   0x1180080940110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP35"              ,	   0x1180080940118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP36"              ,	   0x1180080940120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP37"              ,	   0x1180080940128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP38"              ,	   0x1180080940130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP39"              ,	   0x1180080940138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP40"              ,	   0x1180080940140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP41"              ,	   0x1180080940148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP42"              ,	   0x1180080940150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP43"              ,	   0x1180080940158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP44"              ,	   0x1180080940160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP45"              ,	   0x1180080940168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP46"              ,	   0x1180080940170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP47"              ,	   0x1180080940178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP48"              ,	   0x1180080940180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP49"              ,	   0x1180080940188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP50"              ,	   0x1180080940190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP51"              ,	   0x1180080940198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP52"              ,	   0x11800809401a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP53"              ,	   0x11800809401a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP54"              ,	   0x11800809401b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP55"              ,	   0x11800809401b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP56"              ,	   0x11800809401c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP57"              ,	   0x11800809401c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP58"              ,	   0x11800809401d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP59"              ,	   0x11800809401d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP60"              ,	   0x11800809401e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP61"              ,	   0x11800809401e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP62"              ,	   0x11800809401f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP63"              ,	   0x11800809401f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP64"              ,	   0x1180080940200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP65"              ,	   0x1180080940208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP66"              ,	   0x1180080940210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP67"              ,	   0x1180080940218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP68"              ,	   0x1180080940220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP69"              ,	   0x1180080940228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP70"              ,	   0x1180080940230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP71"              ,	   0x1180080940238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP72"              ,	   0x1180080940240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP73"              ,	   0x1180080940248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP74"              ,	   0x1180080940250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP75"              ,	   0x1180080940258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP76"              ,	   0x1180080940260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP77"              ,	   0x1180080940268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP78"              ,	   0x1180080940270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP79"              ,	   0x1180080940278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP80"              ,	   0x1180080940280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP81"              ,	   0x1180080940288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP82"              ,	   0x1180080940290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP83"              ,	   0x1180080940298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP84"              ,	   0x11800809402a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP85"              ,	   0x11800809402a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP86"              ,	   0x11800809402b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP87"              ,	   0x11800809402b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP88"              ,	   0x11800809402c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP89"              ,	   0x11800809402c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP90"              ,	   0x11800809402d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP91"              ,	   0x11800809402d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP92"              ,	   0x11800809402e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP93"              ,	   0x11800809402e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP94"              ,	   0x11800809402f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP95"              ,	   0x11800809402f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP96"              ,	   0x1180080940300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP97"              ,	   0x1180080940308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP98"              ,	   0x1180080940310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP99"              ,	   0x1180080940318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP100"             ,	   0x1180080940320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP101"             ,	   0x1180080940328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP102"             ,	   0x1180080940330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP103"             ,	   0x1180080940338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP104"             ,	   0x1180080940340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP105"             ,	   0x1180080940348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP106"             ,	   0x1180080940350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP107"             ,	   0x1180080940358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP108"             ,	   0x1180080940360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP109"             ,	   0x1180080940368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP110"             ,	   0x1180080940370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP111"             ,	   0x1180080940378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP112"             ,	   0x1180080940380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP113"             ,	   0x1180080940388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP114"             ,	   0x1180080940390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP115"             ,	   0x1180080940398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP116"             ,	   0x11800809403a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP117"             ,	   0x11800809403a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP118"             ,	   0x11800809403b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP119"             ,	   0x11800809403b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP120"             ,	   0x11800809403c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP121"             ,	   0x11800809403c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP122"             ,	   0x11800809403d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP123"             ,	   0x11800809403d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP124"             ,	   0x11800809403e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP125"             ,	   0x11800809403e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP126"             ,	   0x11800809403f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP127"             ,	   0x11800809403f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP128"             ,	   0x1180080940400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP129"             ,	   0x1180080940408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP130"             ,	   0x1180080940410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP131"             ,	   0x1180080940418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP132"             ,	   0x1180080940420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP133"             ,	   0x1180080940428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP134"             ,	   0x1180080940430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP135"             ,	   0x1180080940438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP136"             ,	   0x1180080940440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP137"             ,	   0x1180080940448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP138"             ,	   0x1180080940450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP139"             ,	   0x1180080940458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP140"             ,	   0x1180080940460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP141"             ,	   0x1180080940468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP142"             ,	   0x1180080940470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP143"             ,	   0x1180080940478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP144"             ,	   0x1180080940480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP145"             ,	   0x1180080940488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP146"             ,	   0x1180080940490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP147"             ,	   0x1180080940498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP148"             ,	   0x11800809404a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP149"             ,	   0x11800809404a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP150"             ,	   0x11800809404b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP151"             ,	   0x11800809404b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP152"             ,	   0x11800809404c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP153"             ,	   0x11800809404c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP154"             ,	   0x11800809404d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP155"             ,	   0x11800809404d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP156"             ,	   0x11800809404e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP157"             ,	   0x11800809404e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP158"             ,	   0x11800809404f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP159"             ,	   0x11800809404f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP160"             ,	   0x1180080940500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP161"             ,	   0x1180080940508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP162"             ,	   0x1180080940510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP163"             ,	   0x1180080940518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP164"             ,	   0x1180080940520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP165"             ,	   0x1180080940528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP166"             ,	   0x1180080940530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP167"             ,	   0x1180080940538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP168"             ,	   0x1180080940540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP169"             ,	   0x1180080940548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP170"             ,	   0x1180080940550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP171"             ,	   0x1180080940558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP172"             ,	   0x1180080940560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP173"             ,	   0x1180080940568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP174"             ,	   0x1180080940570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP175"             ,	   0x1180080940578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP176"             ,	   0x1180080940580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP177"             ,	   0x1180080940588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP178"             ,	   0x1180080940590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP179"             ,	   0x1180080940598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP180"             ,	   0x11800809405a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP181"             ,	   0x11800809405a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP182"             ,	   0x11800809405b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP183"             ,	   0x11800809405b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP184"             ,	   0x11800809405c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP185"             ,	   0x11800809405c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP186"             ,	   0x11800809405d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP187"             ,	   0x11800809405d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP188"             ,	   0x11800809405e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP189"             ,	   0x11800809405e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP190"             ,	   0x11800809405f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP191"             ,	   0x11800809405f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP192"             ,	   0x1180080940600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP193"             ,	   0x1180080940608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP194"             ,	   0x1180080940610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP195"             ,	   0x1180080940618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP196"             ,	   0x1180080940620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP197"             ,	   0x1180080940628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP198"             ,	   0x1180080940630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP199"             ,	   0x1180080940638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP200"             ,	   0x1180080940640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP201"             ,	   0x1180080940648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP202"             ,	   0x1180080940650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP203"             ,	   0x1180080940658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP204"             ,	   0x1180080940660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP205"             ,	   0x1180080940668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP206"             ,	   0x1180080940670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP207"             ,	   0x1180080940678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP208"             ,	   0x1180080940680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP209"             ,	   0x1180080940688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP210"             ,	   0x1180080940690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP211"             ,	   0x1180080940698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP212"             ,	   0x11800809406a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP213"             ,	   0x11800809406a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP214"             ,	   0x11800809406b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP215"             ,	   0x11800809406b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP216"             ,	   0x11800809406c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP217"             ,	   0x11800809406c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP218"             ,	   0x11800809406d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP219"             ,	   0x11800809406d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP220"             ,	   0x11800809406e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP221"             ,	   0x11800809406e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP222"             ,	   0x11800809406f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP223"             ,	   0x11800809406f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP224"             ,	   0x1180080940700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP225"             ,	   0x1180080940708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP226"             ,	   0x1180080940710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP227"             ,	   0x1180080940718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP228"             ,	   0x1180080940720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP229"             ,	   0x1180080940728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP230"             ,	   0x1180080940730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP231"             ,	   0x1180080940738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP232"             ,	   0x1180080940740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP233"             ,	   0x1180080940748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP234"             ,	   0x1180080940750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP235"             ,	   0x1180080940758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP236"             ,	   0x1180080940760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP237"             ,	   0x1180080940768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP238"             ,	   0x1180080940770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP239"             ,	   0x1180080940778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP240"             ,	   0x1180080940780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP241"             ,	   0x1180080940788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP242"             ,	   0x1180080940790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP243"             ,	   0x1180080940798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP244"             ,	   0x11800809407a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP245"             ,	   0x11800809407a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP246"             ,	   0x11800809407b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP247"             ,	   0x11800809407b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP248"             ,	   0x11800809407c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP249"             ,	   0x11800809407c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP250"             ,	   0x11800809407d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP251"             ,	   0x11800809407d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP252"             ,	   0x11800809407e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP253"             ,	   0x11800809407e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP254"             ,	   0x11800809407f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP255"             ,	   0x11800809407f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP256"             ,	   0x1180080940800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP257"             ,	   0x1180080940808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP258"             ,	   0x1180080940810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP259"             ,	   0x1180080940818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP260"             ,	   0x1180080940820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP261"             ,	   0x1180080940828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP262"             ,	   0x1180080940830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP263"             ,	   0x1180080940838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP264"             ,	   0x1180080940840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP265"             ,	   0x1180080940848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP266"             ,	   0x1180080940850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP267"             ,	   0x1180080940858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP268"             ,	   0x1180080940860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP269"             ,	   0x1180080940868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP270"             ,	   0x1180080940870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP271"             ,	   0x1180080940878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP272"             ,	   0x1180080940880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP273"             ,	   0x1180080940888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP274"             ,	   0x1180080940890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP275"             ,	   0x1180080940898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP276"             ,	   0x11800809408a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP277"             ,	   0x11800809408a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP278"             ,	   0x11800809408b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP279"             ,	   0x11800809408b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP280"             ,	   0x11800809408c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP281"             ,	   0x11800809408c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP282"             ,	   0x11800809408d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP283"             ,	   0x11800809408d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP284"             ,	   0x11800809408e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP285"             ,	   0x11800809408e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP286"             ,	   0x11800809408f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP287"             ,	   0x11800809408f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP288"             ,	   0x1180080940900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP289"             ,	   0x1180080940908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP290"             ,	   0x1180080940910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP291"             ,	   0x1180080940918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP292"             ,	   0x1180080940920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP293"             ,	   0x1180080940928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP294"             ,	   0x1180080940930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP295"             ,	   0x1180080940938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP296"             ,	   0x1180080940940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP297"             ,	   0x1180080940948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP298"             ,	   0x1180080940950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP299"             ,	   0x1180080940958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP300"             ,	   0x1180080940960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP301"             ,	   0x1180080940968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP302"             ,	   0x1180080940970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP303"             ,	   0x1180080940978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP304"             ,	   0x1180080940980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP305"             ,	   0x1180080940988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP306"             ,	   0x1180080940990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP307"             ,	   0x1180080940998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP308"             ,	   0x11800809409a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP309"             ,	   0x11800809409a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP310"             ,	   0x11800809409b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP311"             ,	   0x11800809409b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP312"             ,	   0x11800809409c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP313"             ,	   0x11800809409c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP314"             ,	   0x11800809409d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP315"             ,	   0x11800809409d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP316"             ,	   0x11800809409e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP317"             ,	   0x11800809409e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP318"             ,	   0x11800809409f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP319"             ,	   0x11800809409f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP320"             ,	   0x1180080940a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP321"             ,	   0x1180080940a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP322"             ,	   0x1180080940a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP323"             ,	   0x1180080940a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP324"             ,	   0x1180080940a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP325"             ,	   0x1180080940a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP326"             ,	   0x1180080940a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP327"             ,	   0x1180080940a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP328"             ,	   0x1180080940a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP329"             ,	   0x1180080940a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP330"             ,	   0x1180080940a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP331"             ,	   0x1180080940a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP332"             ,	   0x1180080940a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP333"             ,	   0x1180080940a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP334"             ,	   0x1180080940a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP335"             ,	   0x1180080940a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP336"             ,	   0x1180080940a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP337"             ,	   0x1180080940a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP338"             ,	   0x1180080940a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP339"             ,	   0x1180080940a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP340"             ,	   0x1180080940aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP341"             ,	   0x1180080940aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP342"             ,	   0x1180080940ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP343"             ,	   0x1180080940ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP344"             ,	   0x1180080940ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP345"             ,	   0x1180080940ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP346"             ,	   0x1180080940ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP347"             ,	   0x1180080940ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP348"             ,	   0x1180080940ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP349"             ,	   0x1180080940ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP350"             ,	   0x1180080940af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP351"             ,	   0x1180080940af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP352"             ,	   0x1180080940b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP353"             ,	   0x1180080940b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP354"             ,	   0x1180080940b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP355"             ,	   0x1180080940b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP356"             ,	   0x1180080940b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP357"             ,	   0x1180080940b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP358"             ,	   0x1180080940b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP359"             ,	   0x1180080940b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP360"             ,	   0x1180080940b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP361"             ,	   0x1180080940b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP362"             ,	   0x1180080940b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP363"             ,	   0x1180080940b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP364"             ,	   0x1180080940b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP365"             ,	   0x1180080940b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP366"             ,	   0x1180080940b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP367"             ,	   0x1180080940b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP368"             ,	   0x1180080940b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP369"             ,	   0x1180080940b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP370"             ,	   0x1180080940b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP371"             ,	   0x1180080940b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP372"             ,	   0x1180080940ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP373"             ,	   0x1180080940ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP374"             ,	   0x1180080940bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP375"             ,	   0x1180080940bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP376"             ,	   0x1180080940bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP377"             ,	   0x1180080940bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP378"             ,	   0x1180080940bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP379"             ,	   0x1180080940bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP380"             ,	   0x1180080940be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP381"             ,	   0x1180080940be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP382"             ,	   0x1180080940bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP383"             ,	   0x1180080940bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP384"             ,	   0x1180080940c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP385"             ,	   0x1180080940c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP386"             ,	   0x1180080940c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP387"             ,	   0x1180080940c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP388"             ,	   0x1180080940c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP389"             ,	   0x1180080940c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP390"             ,	   0x1180080940c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP391"             ,	   0x1180080940c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP392"             ,	   0x1180080940c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP393"             ,	   0x1180080940c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP394"             ,	   0x1180080940c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP395"             ,	   0x1180080940c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP396"             ,	   0x1180080940c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP397"             ,	   0x1180080940c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP398"             ,	   0x1180080940c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP399"             ,	   0x1180080940c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP400"             ,	   0x1180080940c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP401"             ,	   0x1180080940c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP402"             ,	   0x1180080940c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP403"             ,	   0x1180080940c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP404"             ,	   0x1180080940ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP405"             ,	   0x1180080940ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP406"             ,	   0x1180080940cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP407"             ,	   0x1180080940cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP408"             ,	   0x1180080940cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP409"             ,	   0x1180080940cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP410"             ,	   0x1180080940cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP411"             ,	   0x1180080940cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP412"             ,	   0x1180080940ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP413"             ,	   0x1180080940ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP414"             ,	   0x1180080940cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP415"             ,	   0x1180080940cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP416"             ,	   0x1180080940d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP417"             ,	   0x1180080940d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP418"             ,	   0x1180080940d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP419"             ,	   0x1180080940d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP420"             ,	   0x1180080940d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP421"             ,	   0x1180080940d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP422"             ,	   0x1180080940d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP423"             ,	   0x1180080940d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP424"             ,	   0x1180080940d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP425"             ,	   0x1180080940d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP426"             ,	   0x1180080940d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP427"             ,	   0x1180080940d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP428"             ,	   0x1180080940d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP429"             ,	   0x1180080940d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP430"             ,	   0x1180080940d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP431"             ,	   0x1180080940d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP432"             ,	   0x1180080940d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP433"             ,	   0x1180080940d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP434"             ,	   0x1180080940d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP435"             ,	   0x1180080940d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP436"             ,	   0x1180080940da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP437"             ,	   0x1180080940da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP438"             ,	   0x1180080940db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP439"             ,	   0x1180080940db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP440"             ,	   0x1180080940dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP441"             ,	   0x1180080940dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP442"             ,	   0x1180080940dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP443"             ,	   0x1180080940dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP444"             ,	   0x1180080940de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP445"             ,	   0x1180080940de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP446"             ,	   0x1180080940df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP447"             ,	   0x1180080940df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP448"             ,	   0x1180080940e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP449"             ,	   0x1180080940e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP450"             ,	   0x1180080940e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP451"             ,	   0x1180080940e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP452"             ,	   0x1180080940e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP453"             ,	   0x1180080940e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP454"             ,	   0x1180080940e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP455"             ,	   0x1180080940e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP456"             ,	   0x1180080940e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP457"             ,	   0x1180080940e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP458"             ,	   0x1180080940e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP459"             ,	   0x1180080940e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP460"             ,	   0x1180080940e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP461"             ,	   0x1180080940e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP462"             ,	   0x1180080940e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP463"             ,	   0x1180080940e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP464"             ,	   0x1180080940e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP465"             ,	   0x1180080940e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP466"             ,	   0x1180080940e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP467"             ,	   0x1180080940e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP468"             ,	   0x1180080940ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP469"             ,	   0x1180080940ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP470"             ,	   0x1180080940eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP471"             ,	   0x1180080940eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP472"             ,	   0x1180080940ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP473"             ,	   0x1180080940ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP474"             ,	   0x1180080940ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP475"             ,	   0x1180080940ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP476"             ,	   0x1180080940ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP477"             ,	   0x1180080940ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP478"             ,	   0x1180080940ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP479"             ,	   0x1180080940ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP480"             ,	   0x1180080940f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP481"             ,	   0x1180080940f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP482"             ,	   0x1180080940f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP483"             ,	   0x1180080940f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP484"             ,	   0x1180080940f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP485"             ,	   0x1180080940f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP486"             ,	   0x1180080940f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP487"             ,	   0x1180080940f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP488"             ,	   0x1180080940f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP489"             ,	   0x1180080940f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP490"             ,	   0x1180080940f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP491"             ,	   0x1180080940f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP492"             ,	   0x1180080940f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP493"             ,	   0x1180080940f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP494"             ,	   0x1180080940f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP495"             ,	   0x1180080940f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP496"             ,	   0x1180080940f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP497"             ,	   0x1180080940f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP498"             ,	   0x1180080940f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP499"             ,	   0x1180080940f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP500"             ,	   0x1180080940fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP501"             ,	   0x1180080940fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP502"             ,	   0x1180080940fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP503"             ,	   0x1180080940fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP504"             ,	   0x1180080940fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP505"             ,	   0x1180080940fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP506"             ,	   0x1180080940fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP507"             ,	   0x1180080940fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP508"             ,	   0x1180080940fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP509"             ,	   0x1180080940fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP510"             ,	   0x1180080940ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP511"             ,	   0x1180080940ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP512"             ,	   0x1180080941000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP513"             ,	   0x1180080941008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP514"             ,	   0x1180080941010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP515"             ,	   0x1180080941018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP516"             ,	   0x1180080941020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP517"             ,	   0x1180080941028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP518"             ,	   0x1180080941030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP519"             ,	   0x1180080941038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP520"             ,	   0x1180080941040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP521"             ,	   0x1180080941048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP522"             ,	   0x1180080941050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP523"             ,	   0x1180080941058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP524"             ,	   0x1180080941060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP525"             ,	   0x1180080941068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP526"             ,	   0x1180080941070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP527"             ,	   0x1180080941078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP528"             ,	   0x1180080941080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP529"             ,	   0x1180080941088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP530"             ,	   0x1180080941090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP531"             ,	   0x1180080941098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP532"             ,	   0x11800809410a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP533"             ,	   0x11800809410a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP534"             ,	   0x11800809410b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP535"             ,	   0x11800809410b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP536"             ,	   0x11800809410c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP537"             ,	   0x11800809410c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP538"             ,	   0x11800809410d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP539"             ,	   0x11800809410d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP540"             ,	   0x11800809410e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP541"             ,	   0x11800809410e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP542"             ,	   0x11800809410f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP543"             ,	   0x11800809410f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP544"             ,	   0x1180080941100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP545"             ,	   0x1180080941108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP546"             ,	   0x1180080941110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP547"             ,	   0x1180080941118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP548"             ,	   0x1180080941120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP549"             ,	   0x1180080941128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP550"             ,	   0x1180080941130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP551"             ,	   0x1180080941138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP552"             ,	   0x1180080941140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP553"             ,	   0x1180080941148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP554"             ,	   0x1180080941150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP555"             ,	   0x1180080941158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP556"             ,	   0x1180080941160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP557"             ,	   0x1180080941168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP558"             ,	   0x1180080941170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP559"             ,	   0x1180080941178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP560"             ,	   0x1180080941180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP561"             ,	   0x1180080941188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP562"             ,	   0x1180080941190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP563"             ,	   0x1180080941198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP564"             ,	   0x11800809411a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP565"             ,	   0x11800809411a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP566"             ,	   0x11800809411b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP567"             ,	   0x11800809411b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP568"             ,	   0x11800809411c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP569"             ,	   0x11800809411c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP570"             ,	   0x11800809411d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP571"             ,	   0x11800809411d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP572"             ,	   0x11800809411e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP573"             ,	   0x11800809411e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP574"             ,	   0x11800809411f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP575"             ,	   0x11800809411f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP576"             ,	   0x1180080941200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP577"             ,	   0x1180080941208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP578"             ,	   0x1180080941210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP579"             ,	   0x1180080941218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP580"             ,	   0x1180080941220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP581"             ,	   0x1180080941228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP582"             ,	   0x1180080941230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP583"             ,	   0x1180080941238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP584"             ,	   0x1180080941240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP585"             ,	   0x1180080941248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP586"             ,	   0x1180080941250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP587"             ,	   0x1180080941258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP588"             ,	   0x1180080941260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP589"             ,	   0x1180080941268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP590"             ,	   0x1180080941270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP591"             ,	   0x1180080941278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP592"             ,	   0x1180080941280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP593"             ,	   0x1180080941288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP594"             ,	   0x1180080941290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP595"             ,	   0x1180080941298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP596"             ,	   0x11800809412a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP597"             ,	   0x11800809412a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP598"             ,	   0x11800809412b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP599"             ,	   0x11800809412b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP600"             ,	   0x11800809412c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP601"             ,	   0x11800809412c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP602"             ,	   0x11800809412d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP603"             ,	   0x11800809412d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP604"             ,	   0x11800809412e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP605"             ,	   0x11800809412e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP606"             ,	   0x11800809412f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP607"             ,	   0x11800809412f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP608"             ,	   0x1180080941300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP609"             ,	   0x1180080941308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP610"             ,	   0x1180080941310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP611"             ,	   0x1180080941318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP612"             ,	   0x1180080941320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP613"             ,	   0x1180080941328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP614"             ,	   0x1180080941330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP615"             ,	   0x1180080941338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP616"             ,	   0x1180080941340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP617"             ,	   0x1180080941348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP618"             ,	   0x1180080941350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP619"             ,	   0x1180080941358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP620"             ,	   0x1180080941360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP621"             ,	   0x1180080941368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP622"             ,	   0x1180080941370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP623"             ,	   0x1180080941378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP624"             ,	   0x1180080941380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP625"             ,	   0x1180080941388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP626"             ,	   0x1180080941390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP627"             ,	   0x1180080941398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP628"             ,	   0x11800809413a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP629"             ,	   0x11800809413a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP630"             ,	   0x11800809413b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP631"             ,	   0x11800809413b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP632"             ,	   0x11800809413c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP633"             ,	   0x11800809413c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP634"             ,	   0x11800809413d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP635"             ,	   0x11800809413d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP636"             ,	   0x11800809413e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP637"             ,	   0x11800809413e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP638"             ,	   0x11800809413f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP639"             ,	   0x11800809413f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP640"             ,	   0x1180080941400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP641"             ,	   0x1180080941408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP642"             ,	   0x1180080941410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP643"             ,	   0x1180080941418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP644"             ,	   0x1180080941420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP645"             ,	   0x1180080941428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP646"             ,	   0x1180080941430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP647"             ,	   0x1180080941438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP648"             ,	   0x1180080941440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP649"             ,	   0x1180080941448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP650"             ,	   0x1180080941450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP651"             ,	   0x1180080941458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP652"             ,	   0x1180080941460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP653"             ,	   0x1180080941468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP654"             ,	   0x1180080941470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP655"             ,	   0x1180080941478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP656"             ,	   0x1180080941480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP657"             ,	   0x1180080941488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP658"             ,	   0x1180080941490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP659"             ,	   0x1180080941498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP660"             ,	   0x11800809414a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP661"             ,	   0x11800809414a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP662"             ,	   0x11800809414b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP663"             ,	   0x11800809414b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP664"             ,	   0x11800809414c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP665"             ,	   0x11800809414c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP666"             ,	   0x11800809414d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP667"             ,	   0x11800809414d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP668"             ,	   0x11800809414e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP669"             ,	   0x11800809414e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP670"             ,	   0x11800809414f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP671"             ,	   0x11800809414f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP672"             ,	   0x1180080941500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP673"             ,	   0x1180080941508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP674"             ,	   0x1180080941510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP675"             ,	   0x1180080941518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP676"             ,	   0x1180080941520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP677"             ,	   0x1180080941528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP678"             ,	   0x1180080941530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP679"             ,	   0x1180080941538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP680"             ,	   0x1180080941540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP681"             ,	   0x1180080941548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP682"             ,	   0x1180080941550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP683"             ,	   0x1180080941558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP684"             ,	   0x1180080941560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP685"             ,	   0x1180080941568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP686"             ,	   0x1180080941570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP687"             ,	   0x1180080941578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP688"             ,	   0x1180080941580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP689"             ,	   0x1180080941588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP690"             ,	   0x1180080941590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP691"             ,	   0x1180080941598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP692"             ,	   0x11800809415a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP693"             ,	   0x11800809415a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP694"             ,	   0x11800809415b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP695"             ,	   0x11800809415b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP696"             ,	   0x11800809415c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP697"             ,	   0x11800809415c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP698"             ,	   0x11800809415d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP699"             ,	   0x11800809415d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP700"             ,	   0x11800809415e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP701"             ,	   0x11800809415e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP702"             ,	   0x11800809415f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP703"             ,	   0x11800809415f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP704"             ,	   0x1180080941600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP705"             ,	   0x1180080941608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP706"             ,	   0x1180080941610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP707"             ,	   0x1180080941618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP708"             ,	   0x1180080941620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP709"             ,	   0x1180080941628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP710"             ,	   0x1180080941630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP711"             ,	   0x1180080941638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP712"             ,	   0x1180080941640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP713"             ,	   0x1180080941648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP714"             ,	   0x1180080941650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP715"             ,	   0x1180080941658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP716"             ,	   0x1180080941660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP717"             ,	   0x1180080941668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP718"             ,	   0x1180080941670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP719"             ,	   0x1180080941678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP720"             ,	   0x1180080941680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP721"             ,	   0x1180080941688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP722"             ,	   0x1180080941690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP723"             ,	   0x1180080941698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP724"             ,	   0x11800809416a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP725"             ,	   0x11800809416a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP726"             ,	   0x11800809416b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP727"             ,	   0x11800809416b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP728"             ,	   0x11800809416c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP729"             ,	   0x11800809416c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP730"             ,	   0x11800809416d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP731"             ,	   0x11800809416d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP732"             ,	   0x11800809416e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP733"             ,	   0x11800809416e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP734"             ,	   0x11800809416f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP735"             ,	   0x11800809416f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP736"             ,	   0x1180080941700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP737"             ,	   0x1180080941708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP738"             ,	   0x1180080941710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP739"             ,	   0x1180080941718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP740"             ,	   0x1180080941720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP741"             ,	   0x1180080941728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP742"             ,	   0x1180080941730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP743"             ,	   0x1180080941738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP744"             ,	   0x1180080941740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP745"             ,	   0x1180080941748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP746"             ,	   0x1180080941750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP747"             ,	   0x1180080941758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP748"             ,	   0x1180080941760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP749"             ,	   0x1180080941768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP750"             ,	   0x1180080941770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP751"             ,	   0x1180080941778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP752"             ,	   0x1180080941780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP753"             ,	   0x1180080941788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP754"             ,	   0x1180080941790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP755"             ,	   0x1180080941798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP756"             ,	   0x11800809417a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP757"             ,	   0x11800809417a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP758"             ,	   0x11800809417b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP759"             ,	   0x11800809417b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP760"             ,	   0x11800809417c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP761"             ,	   0x11800809417c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP762"             ,	   0x11800809417d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP763"             ,	   0x11800809417d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP764"             ,	   0x11800809417e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP765"             ,	   0x11800809417e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP766"             ,	   0x11800809417f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP767"             ,	   0x11800809417f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP768"             ,	   0x1180080941800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP769"             ,	   0x1180080941808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP770"             ,	   0x1180080941810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP771"             ,	   0x1180080941818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP772"             ,	   0x1180080941820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP773"             ,	   0x1180080941828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP774"             ,	   0x1180080941830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP775"             ,	   0x1180080941838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP776"             ,	   0x1180080941840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP777"             ,	   0x1180080941848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP778"             ,	   0x1180080941850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP779"             ,	   0x1180080941858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP780"             ,	   0x1180080941860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP781"             ,	   0x1180080941868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP782"             ,	   0x1180080941870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP783"             ,	   0x1180080941878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP784"             ,	   0x1180080941880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP785"             ,	   0x1180080941888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP786"             ,	   0x1180080941890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP787"             ,	   0x1180080941898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP788"             ,	   0x11800809418a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP789"             ,	   0x11800809418a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP790"             ,	   0x11800809418b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP791"             ,	   0x11800809418b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP792"             ,	   0x11800809418c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP793"             ,	   0x11800809418c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP794"             ,	   0x11800809418d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP795"             ,	   0x11800809418d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP796"             ,	   0x11800809418e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP797"             ,	   0x11800809418e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP798"             ,	   0x11800809418f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP799"             ,	   0x11800809418f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP800"             ,	   0x1180080941900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP801"             ,	   0x1180080941908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP802"             ,	   0x1180080941910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP803"             ,	   0x1180080941918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP804"             ,	   0x1180080941920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP805"             ,	   0x1180080941928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP806"             ,	   0x1180080941930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP807"             ,	   0x1180080941938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP808"             ,	   0x1180080941940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP809"             ,	   0x1180080941948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP810"             ,	   0x1180080941950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP811"             ,	   0x1180080941958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP812"             ,	   0x1180080941960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP813"             ,	   0x1180080941968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP814"             ,	   0x1180080941970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP815"             ,	   0x1180080941978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP816"             ,	   0x1180080941980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP817"             ,	   0x1180080941988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP818"             ,	   0x1180080941990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP819"             ,	   0x1180080941998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP820"             ,	   0x11800809419a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP821"             ,	   0x11800809419a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP822"             ,	   0x11800809419b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP823"             ,	   0x11800809419b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP824"             ,	   0x11800809419c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP825"             ,	   0x11800809419c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP826"             ,	   0x11800809419d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP827"             ,	   0x11800809419d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP828"             ,	   0x11800809419e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP829"             ,	   0x11800809419e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP830"             ,	   0x11800809419f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP831"             ,	   0x11800809419f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP832"             ,	   0x1180080941a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP833"             ,	   0x1180080941a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP834"             ,	   0x1180080941a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP835"             ,	   0x1180080941a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP836"             ,	   0x1180080941a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP837"             ,	   0x1180080941a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP838"             ,	   0x1180080941a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP839"             ,	   0x1180080941a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP840"             ,	   0x1180080941a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP841"             ,	   0x1180080941a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP842"             ,	   0x1180080941a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP843"             ,	   0x1180080941a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP844"             ,	   0x1180080941a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP845"             ,	   0x1180080941a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP846"             ,	   0x1180080941a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP847"             ,	   0x1180080941a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP848"             ,	   0x1180080941a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP849"             ,	   0x1180080941a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP850"             ,	   0x1180080941a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP851"             ,	   0x1180080941a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP852"             ,	   0x1180080941aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP853"             ,	   0x1180080941aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP854"             ,	   0x1180080941ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP855"             ,	   0x1180080941ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP856"             ,	   0x1180080941ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP857"             ,	   0x1180080941ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP858"             ,	   0x1180080941ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP859"             ,	   0x1180080941ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP860"             ,	   0x1180080941ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP861"             ,	   0x1180080941ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP862"             ,	   0x1180080941af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP863"             ,	   0x1180080941af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP864"             ,	   0x1180080941b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP865"             ,	   0x1180080941b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP866"             ,	   0x1180080941b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP867"             ,	   0x1180080941b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP868"             ,	   0x1180080941b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP869"             ,	   0x1180080941b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP870"             ,	   0x1180080941b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP871"             ,	   0x1180080941b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP872"             ,	   0x1180080941b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP873"             ,	   0x1180080941b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP874"             ,	   0x1180080941b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP875"             ,	   0x1180080941b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP876"             ,	   0x1180080941b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP877"             ,	   0x1180080941b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP878"             ,	   0x1180080941b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP879"             ,	   0x1180080941b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP880"             ,	   0x1180080941b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP881"             ,	   0x1180080941b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP882"             ,	   0x1180080941b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP883"             ,	   0x1180080941b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP884"             ,	   0x1180080941ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP885"             ,	   0x1180080941ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP886"             ,	   0x1180080941bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP887"             ,	   0x1180080941bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP888"             ,	   0x1180080941bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP889"             ,	   0x1180080941bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP890"             ,	   0x1180080941bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP891"             ,	   0x1180080941bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP892"             ,	   0x1180080941be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP893"             ,	   0x1180080941be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP894"             ,	   0x1180080941bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP895"             ,	   0x1180080941bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP896"             ,	   0x1180080941c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP897"             ,	   0x1180080941c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP898"             ,	   0x1180080941c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP899"             ,	   0x1180080941c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP900"             ,	   0x1180080941c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP901"             ,	   0x1180080941c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP902"             ,	   0x1180080941c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP903"             ,	   0x1180080941c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP904"             ,	   0x1180080941c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP905"             ,	   0x1180080941c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP906"             ,	   0x1180080941c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP907"             ,	   0x1180080941c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP908"             ,	   0x1180080941c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP909"             ,	   0x1180080941c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP910"             ,	   0x1180080941c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP911"             ,	   0x1180080941c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP912"             ,	   0x1180080941c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP913"             ,	   0x1180080941c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP914"             ,	   0x1180080941c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP915"             ,	   0x1180080941c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP916"             ,	   0x1180080941ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP917"             ,	   0x1180080941ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP918"             ,	   0x1180080941cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP919"             ,	   0x1180080941cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP920"             ,	   0x1180080941cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP921"             ,	   0x1180080941cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP922"             ,	   0x1180080941cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP923"             ,	   0x1180080941cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP924"             ,	   0x1180080941ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP925"             ,	   0x1180080941ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP926"             ,	   0x1180080941cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP927"             ,	   0x1180080941cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP928"             ,	   0x1180080941d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP929"             ,	   0x1180080941d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP930"             ,	   0x1180080941d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP931"             ,	   0x1180080941d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP932"             ,	   0x1180080941d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP933"             ,	   0x1180080941d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP934"             ,	   0x1180080941d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP935"             ,	   0x1180080941d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP936"             ,	   0x1180080941d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP937"             ,	   0x1180080941d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP938"             ,	   0x1180080941d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP939"             ,	   0x1180080941d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP940"             ,	   0x1180080941d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP941"             ,	   0x1180080941d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP942"             ,	   0x1180080941d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP943"             ,	   0x1180080941d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP944"             ,	   0x1180080941d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP945"             ,	   0x1180080941d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP946"             ,	   0x1180080941d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP947"             ,	   0x1180080941d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP948"             ,	   0x1180080941da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP949"             ,	   0x1180080941da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP950"             ,	   0x1180080941db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP951"             ,	   0x1180080941db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP952"             ,	   0x1180080941dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP953"             ,	   0x1180080941dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP954"             ,	   0x1180080941dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP955"             ,	   0x1180080941dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP956"             ,	   0x1180080941de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP957"             ,	   0x1180080941de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP958"             ,	   0x1180080941df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP959"             ,	   0x1180080941df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP960"             ,	   0x1180080941e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP961"             ,	   0x1180080941e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP962"             ,	   0x1180080941e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP963"             ,	   0x1180080941e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP964"             ,	   0x1180080941e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP965"             ,	   0x1180080941e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP966"             ,	   0x1180080941e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP967"             ,	   0x1180080941e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP968"             ,	   0x1180080941e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP969"             ,	   0x1180080941e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP970"             ,	   0x1180080941e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP971"             ,	   0x1180080941e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP972"             ,	   0x1180080941e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP973"             ,	   0x1180080941e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP974"             ,	   0x1180080941e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP975"             ,	   0x1180080941e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP976"             ,	   0x1180080941e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP977"             ,	   0x1180080941e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP978"             ,	   0x1180080941e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP979"             ,	   0x1180080941e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP980"             ,	   0x1180080941ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP981"             ,	   0x1180080941ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP982"             ,	   0x1180080941eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP983"             ,	   0x1180080941eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP984"             ,	   0x1180080941ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP985"             ,	   0x1180080941ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP986"             ,	   0x1180080941ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP987"             ,	   0x1180080941ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP988"             ,	   0x1180080941ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP989"             ,	   0x1180080941ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP990"             ,	   0x1180080941ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP991"             ,	   0x1180080941ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP992"             ,	   0x1180080941f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP993"             ,	   0x1180080941f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP994"             ,	   0x1180080941f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP995"             ,	   0x1180080941f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP996"             ,	   0x1180080941f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP997"             ,	   0x1180080941f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP998"             ,	   0x1180080941f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP999"             ,	   0x1180080941f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1000"            ,	   0x1180080941f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1001"            ,	   0x1180080941f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1002"            ,	   0x1180080941f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1003"            ,	   0x1180080941f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1004"            ,	   0x1180080941f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1005"            ,	   0x1180080941f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1006"            ,	   0x1180080941f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1007"            ,	   0x1180080941f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1008"            ,	   0x1180080941f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1009"            ,	   0x1180080941f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1010"            ,	   0x1180080941f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1011"            ,	   0x1180080941f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1012"            ,	   0x1180080941fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1013"            ,	   0x1180080941fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1014"            ,	   0x1180080941fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1015"            ,	   0x1180080941fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1016"            ,	   0x1180080941fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1017"            ,	   0x1180080941fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1018"            ,	   0x1180080941fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1019"            ,	   0x1180080941fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1020"            ,	   0x1180080941fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1021"            ,	   0x1180080941fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1022"            ,	   0x1180080941ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1023"            ,	   0x1180080941ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1024"            ,	   0x1180080942000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1025"            ,	   0x1180080942008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1026"            ,	   0x1180080942010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1027"            ,	   0x1180080942018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1028"            ,	   0x1180080942020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1029"            ,	   0x1180080942028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1030"            ,	   0x1180080942030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1031"            ,	   0x1180080942038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1032"            ,	   0x1180080942040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1033"            ,	   0x1180080942048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1034"            ,	   0x1180080942050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1035"            ,	   0x1180080942058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1036"            ,	   0x1180080942060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1037"            ,	   0x1180080942068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1038"            ,	   0x1180080942070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1039"            ,	   0x1180080942078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1040"            ,	   0x1180080942080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1041"            ,	   0x1180080942088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1042"            ,	   0x1180080942090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1043"            ,	   0x1180080942098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1044"            ,	   0x11800809420a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1045"            ,	   0x11800809420a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1046"            ,	   0x11800809420b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1047"            ,	   0x11800809420b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1048"            ,	   0x11800809420c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1049"            ,	   0x11800809420c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1050"            ,	   0x11800809420d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1051"            ,	   0x11800809420d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1052"            ,	   0x11800809420e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1053"            ,	   0x11800809420e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1054"            ,	   0x11800809420f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1055"            ,	   0x11800809420f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1056"            ,	   0x1180080942100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1057"            ,	   0x1180080942108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1058"            ,	   0x1180080942110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1059"            ,	   0x1180080942118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1060"            ,	   0x1180080942120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1061"            ,	   0x1180080942128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1062"            ,	   0x1180080942130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1063"            ,	   0x1180080942138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1064"            ,	   0x1180080942140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1065"            ,	   0x1180080942148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1066"            ,	   0x1180080942150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1067"            ,	   0x1180080942158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1068"            ,	   0x1180080942160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1069"            ,	   0x1180080942168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1070"            ,	   0x1180080942170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1071"            ,	   0x1180080942178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1072"            ,	   0x1180080942180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1073"            ,	   0x1180080942188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1074"            ,	   0x1180080942190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1075"            ,	   0x1180080942198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1076"            ,	   0x11800809421a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1077"            ,	   0x11800809421a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1078"            ,	   0x11800809421b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1079"            ,	   0x11800809421b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1080"            ,	   0x11800809421c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1081"            ,	   0x11800809421c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1082"            ,	   0x11800809421d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1083"            ,	   0x11800809421d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1084"            ,	   0x11800809421e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1085"            ,	   0x11800809421e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1086"            ,	   0x11800809421f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1087"            ,	   0x11800809421f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1088"            ,	   0x1180080942200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1089"            ,	   0x1180080942208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1090"            ,	   0x1180080942210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1091"            ,	   0x1180080942218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1092"            ,	   0x1180080942220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1093"            ,	   0x1180080942228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1094"            ,	   0x1180080942230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1095"            ,	   0x1180080942238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1096"            ,	   0x1180080942240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1097"            ,	   0x1180080942248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1098"            ,	   0x1180080942250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1099"            ,	   0x1180080942258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1100"            ,	   0x1180080942260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1101"            ,	   0x1180080942268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1102"            ,	   0x1180080942270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1103"            ,	   0x1180080942278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1104"            ,	   0x1180080942280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1105"            ,	   0x1180080942288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1106"            ,	   0x1180080942290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1107"            ,	   0x1180080942298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1108"            ,	   0x11800809422a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1109"            ,	   0x11800809422a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1110"            ,	   0x11800809422b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1111"            ,	   0x11800809422b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1112"            ,	   0x11800809422c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1113"            ,	   0x11800809422c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1114"            ,	   0x11800809422d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1115"            ,	   0x11800809422d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1116"            ,	   0x11800809422e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1117"            ,	   0x11800809422e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1118"            ,	   0x11800809422f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1119"            ,	   0x11800809422f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1120"            ,	   0x1180080942300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1121"            ,	   0x1180080942308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1122"            ,	   0x1180080942310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1123"            ,	   0x1180080942318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1124"            ,	   0x1180080942320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1125"            ,	   0x1180080942328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1126"            ,	   0x1180080942330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1127"            ,	   0x1180080942338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1128"            ,	   0x1180080942340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1129"            ,	   0x1180080942348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1130"            ,	   0x1180080942350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1131"            ,	   0x1180080942358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1132"            ,	   0x1180080942360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1133"            ,	   0x1180080942368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1134"            ,	   0x1180080942370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1135"            ,	   0x1180080942378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1136"            ,	   0x1180080942380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1137"            ,	   0x1180080942388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1138"            ,	   0x1180080942390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1139"            ,	   0x1180080942398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1140"            ,	   0x11800809423a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1141"            ,	   0x11800809423a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1142"            ,	   0x11800809423b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1143"            ,	   0x11800809423b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1144"            ,	   0x11800809423c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1145"            ,	   0x11800809423c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1146"            ,	   0x11800809423d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1147"            ,	   0x11800809423d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1148"            ,	   0x11800809423e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1149"            ,	   0x11800809423e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1150"            ,	   0x11800809423f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1151"            ,	   0x11800809423f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1152"            ,	   0x1180080942400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1153"            ,	   0x1180080942408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1154"            ,	   0x1180080942410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1155"            ,	   0x1180080942418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1156"            ,	   0x1180080942420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1157"            ,	   0x1180080942428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1158"            ,	   0x1180080942430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1159"            ,	   0x1180080942438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1160"            ,	   0x1180080942440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1161"            ,	   0x1180080942448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1162"            ,	   0x1180080942450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1163"            ,	   0x1180080942458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1164"            ,	   0x1180080942460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1165"            ,	   0x1180080942468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1166"            ,	   0x1180080942470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1167"            ,	   0x1180080942478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1168"            ,	   0x1180080942480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1169"            ,	   0x1180080942488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1170"            ,	   0x1180080942490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1171"            ,	   0x1180080942498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1172"            ,	   0x11800809424a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1173"            ,	   0x11800809424a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1174"            ,	   0x11800809424b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1175"            ,	   0x11800809424b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1176"            ,	   0x11800809424c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1177"            ,	   0x11800809424c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1178"            ,	   0x11800809424d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1179"            ,	   0x11800809424d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1180"            ,	   0x11800809424e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1181"            ,	   0x11800809424e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1182"            ,	   0x11800809424f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1183"            ,	   0x11800809424f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1184"            ,	   0x1180080942500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1185"            ,	   0x1180080942508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1186"            ,	   0x1180080942510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1187"            ,	   0x1180080942518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1188"            ,	   0x1180080942520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1189"            ,	   0x1180080942528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1190"            ,	   0x1180080942530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1191"            ,	   0x1180080942538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1192"            ,	   0x1180080942540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1193"            ,	   0x1180080942548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1194"            ,	   0x1180080942550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1195"            ,	   0x1180080942558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1196"            ,	   0x1180080942560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1197"            ,	   0x1180080942568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1198"            ,	   0x1180080942570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1199"            ,	   0x1180080942578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1200"            ,	   0x1180080942580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1201"            ,	   0x1180080942588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1202"            ,	   0x1180080942590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1203"            ,	   0x1180080942598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1204"            ,	   0x11800809425a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1205"            ,	   0x11800809425a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1206"            ,	   0x11800809425b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1207"            ,	   0x11800809425b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1208"            ,	   0x11800809425c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1209"            ,	   0x11800809425c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1210"            ,	   0x11800809425d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1211"            ,	   0x11800809425d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1212"            ,	   0x11800809425e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1213"            ,	   0x11800809425e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1214"            ,	   0x11800809425f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1215"            ,	   0x11800809425f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1216"            ,	   0x1180080942600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1217"            ,	   0x1180080942608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1218"            ,	   0x1180080942610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1219"            ,	   0x1180080942618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1220"            ,	   0x1180080942620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1221"            ,	   0x1180080942628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1222"            ,	   0x1180080942630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1223"            ,	   0x1180080942638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1224"            ,	   0x1180080942640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1225"            ,	   0x1180080942648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1226"            ,	   0x1180080942650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1227"            ,	   0x1180080942658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1228"            ,	   0x1180080942660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1229"            ,	   0x1180080942668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1230"            ,	   0x1180080942670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1231"            ,	   0x1180080942678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1232"            ,	   0x1180080942680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1233"            ,	   0x1180080942688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1234"            ,	   0x1180080942690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1235"            ,	   0x1180080942698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1236"            ,	   0x11800809426a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1237"            ,	   0x11800809426a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1238"            ,	   0x11800809426b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1239"            ,	   0x11800809426b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1240"            ,	   0x11800809426c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1241"            ,	   0x11800809426c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1242"            ,	   0x11800809426d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1243"            ,	   0x11800809426d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1244"            ,	   0x11800809426e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1245"            ,	   0x11800809426e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1246"            ,	   0x11800809426f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1247"            ,	   0x11800809426f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1248"            ,	   0x1180080942700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1249"            ,	   0x1180080942708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1250"            ,	   0x1180080942710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1251"            ,	   0x1180080942718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1252"            ,	   0x1180080942720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1253"            ,	   0x1180080942728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1254"            ,	   0x1180080942730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1255"            ,	   0x1180080942738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1256"            ,	   0x1180080942740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1257"            ,	   0x1180080942748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1258"            ,	   0x1180080942750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1259"            ,	   0x1180080942758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1260"            ,	   0x1180080942760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1261"            ,	   0x1180080942768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1262"            ,	   0x1180080942770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1263"            ,	   0x1180080942778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1264"            ,	   0x1180080942780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1265"            ,	   0x1180080942788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1266"            ,	   0x1180080942790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1267"            ,	   0x1180080942798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1268"            ,	   0x11800809427a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1269"            ,	   0x11800809427a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1270"            ,	   0x11800809427b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1271"            ,	   0x11800809427b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1272"            ,	   0x11800809427c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1273"            ,	   0x11800809427c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1274"            ,	   0x11800809427d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1275"            ,	   0x11800809427d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1276"            ,	   0x11800809427e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1277"            ,	   0x11800809427e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1278"            ,	   0x11800809427f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1279"            ,	   0x11800809427f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1280"            ,	   0x1180080942800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1281"            ,	   0x1180080942808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1282"            ,	   0x1180080942810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1283"            ,	   0x1180080942818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1284"            ,	   0x1180080942820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1285"            ,	   0x1180080942828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1286"            ,	   0x1180080942830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1287"            ,	   0x1180080942838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1288"            ,	   0x1180080942840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1289"            ,	   0x1180080942848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1290"            ,	   0x1180080942850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1291"            ,	   0x1180080942858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1292"            ,	   0x1180080942860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1293"            ,	   0x1180080942868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1294"            ,	   0x1180080942870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1295"            ,	   0x1180080942878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1296"            ,	   0x1180080942880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1297"            ,	   0x1180080942888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1298"            ,	   0x1180080942890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1299"            ,	   0x1180080942898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1300"            ,	   0x11800809428a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1301"            ,	   0x11800809428a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1302"            ,	   0x11800809428b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1303"            ,	   0x11800809428b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1304"            ,	   0x11800809428c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1305"            ,	   0x11800809428c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1306"            ,	   0x11800809428d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1307"            ,	   0x11800809428d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1308"            ,	   0x11800809428e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1309"            ,	   0x11800809428e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1310"            ,	   0x11800809428f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1311"            ,	   0x11800809428f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1312"            ,	   0x1180080942900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1313"            ,	   0x1180080942908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1314"            ,	   0x1180080942910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1315"            ,	   0x1180080942918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1316"            ,	   0x1180080942920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1317"            ,	   0x1180080942928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1318"            ,	   0x1180080942930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1319"            ,	   0x1180080942938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1320"            ,	   0x1180080942940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1321"            ,	   0x1180080942948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1322"            ,	   0x1180080942950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1323"            ,	   0x1180080942958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1324"            ,	   0x1180080942960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1325"            ,	   0x1180080942968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1326"            ,	   0x1180080942970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1327"            ,	   0x1180080942978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1328"            ,	   0x1180080942980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1329"            ,	   0x1180080942988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1330"            ,	   0x1180080942990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1331"            ,	   0x1180080942998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1332"            ,	   0x11800809429a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1333"            ,	   0x11800809429a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1334"            ,	   0x11800809429b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1335"            ,	   0x11800809429b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1336"            ,	   0x11800809429c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1337"            ,	   0x11800809429c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1338"            ,	   0x11800809429d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1339"            ,	   0x11800809429d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1340"            ,	   0x11800809429e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1341"            ,	   0x11800809429e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1342"            ,	   0x11800809429f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1343"            ,	   0x11800809429f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1344"            ,	   0x1180080942a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1345"            ,	   0x1180080942a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1346"            ,	   0x1180080942a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1347"            ,	   0x1180080942a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1348"            ,	   0x1180080942a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1349"            ,	   0x1180080942a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1350"            ,	   0x1180080942a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1351"            ,	   0x1180080942a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1352"            ,	   0x1180080942a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1353"            ,	   0x1180080942a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1354"            ,	   0x1180080942a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1355"            ,	   0x1180080942a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1356"            ,	   0x1180080942a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1357"            ,	   0x1180080942a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1358"            ,	   0x1180080942a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1359"            ,	   0x1180080942a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1360"            ,	   0x1180080942a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1361"            ,	   0x1180080942a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1362"            ,	   0x1180080942a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1363"            ,	   0x1180080942a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1364"            ,	   0x1180080942aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1365"            ,	   0x1180080942aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1366"            ,	   0x1180080942ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1367"            ,	   0x1180080942ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1368"            ,	   0x1180080942ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1369"            ,	   0x1180080942ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1370"            ,	   0x1180080942ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1371"            ,	   0x1180080942ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1372"            ,	   0x1180080942ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1373"            ,	   0x1180080942ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1374"            ,	   0x1180080942af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1375"            ,	   0x1180080942af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1376"            ,	   0x1180080942b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1377"            ,	   0x1180080942b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1378"            ,	   0x1180080942b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1379"            ,	   0x1180080942b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1380"            ,	   0x1180080942b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1381"            ,	   0x1180080942b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1382"            ,	   0x1180080942b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1383"            ,	   0x1180080942b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1384"            ,	   0x1180080942b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1385"            ,	   0x1180080942b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1386"            ,	   0x1180080942b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1387"            ,	   0x1180080942b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1388"            ,	   0x1180080942b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1389"            ,	   0x1180080942b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1390"            ,	   0x1180080942b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1391"            ,	   0x1180080942b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1392"            ,	   0x1180080942b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1393"            ,	   0x1180080942b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1394"            ,	   0x1180080942b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1395"            ,	   0x1180080942b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1396"            ,	   0x1180080942ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1397"            ,	   0x1180080942ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1398"            ,	   0x1180080942bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1399"            ,	   0x1180080942bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1400"            ,	   0x1180080942bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1401"            ,	   0x1180080942bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1402"            ,	   0x1180080942bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1403"            ,	   0x1180080942bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1404"            ,	   0x1180080942be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1405"            ,	   0x1180080942be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1406"            ,	   0x1180080942bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1407"            ,	   0x1180080942bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1408"            ,	   0x1180080942c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1409"            ,	   0x1180080942c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1410"            ,	   0x1180080942c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1411"            ,	   0x1180080942c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1412"            ,	   0x1180080942c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1413"            ,	   0x1180080942c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1414"            ,	   0x1180080942c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1415"            ,	   0x1180080942c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1416"            ,	   0x1180080942c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1417"            ,	   0x1180080942c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1418"            ,	   0x1180080942c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1419"            ,	   0x1180080942c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1420"            ,	   0x1180080942c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1421"            ,	   0x1180080942c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1422"            ,	   0x1180080942c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1423"            ,	   0x1180080942c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1424"            ,	   0x1180080942c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1425"            ,	   0x1180080942c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1426"            ,	   0x1180080942c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1427"            ,	   0x1180080942c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1428"            ,	   0x1180080942ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1429"            ,	   0x1180080942ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1430"            ,	   0x1180080942cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1431"            ,	   0x1180080942cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1432"            ,	   0x1180080942cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1433"            ,	   0x1180080942cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1434"            ,	   0x1180080942cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1435"            ,	   0x1180080942cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1436"            ,	   0x1180080942ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1437"            ,	   0x1180080942ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1438"            ,	   0x1180080942cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1439"            ,	   0x1180080942cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1440"            ,	   0x1180080942d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1441"            ,	   0x1180080942d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1442"            ,	   0x1180080942d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1443"            ,	   0x1180080942d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1444"            ,	   0x1180080942d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1445"            ,	   0x1180080942d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1446"            ,	   0x1180080942d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1447"            ,	   0x1180080942d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1448"            ,	   0x1180080942d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1449"            ,	   0x1180080942d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1450"            ,	   0x1180080942d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1451"            ,	   0x1180080942d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1452"            ,	   0x1180080942d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1453"            ,	   0x1180080942d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1454"            ,	   0x1180080942d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1455"            ,	   0x1180080942d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1456"            ,	   0x1180080942d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1457"            ,	   0x1180080942d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1458"            ,	   0x1180080942d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1459"            ,	   0x1180080942d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1460"            ,	   0x1180080942da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1461"            ,	   0x1180080942da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1462"            ,	   0x1180080942db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1463"            ,	   0x1180080942db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1464"            ,	   0x1180080942dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1465"            ,	   0x1180080942dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1466"            ,	   0x1180080942dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1467"            ,	   0x1180080942dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1468"            ,	   0x1180080942de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1469"            ,	   0x1180080942de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1470"            ,	   0x1180080942df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1471"            ,	   0x1180080942df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1472"            ,	   0x1180080942e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1473"            ,	   0x1180080942e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1474"            ,	   0x1180080942e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1475"            ,	   0x1180080942e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1476"            ,	   0x1180080942e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1477"            ,	   0x1180080942e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1478"            ,	   0x1180080942e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1479"            ,	   0x1180080942e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1480"            ,	   0x1180080942e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1481"            ,	   0x1180080942e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1482"            ,	   0x1180080942e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1483"            ,	   0x1180080942e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1484"            ,	   0x1180080942e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1485"            ,	   0x1180080942e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1486"            ,	   0x1180080942e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1487"            ,	   0x1180080942e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1488"            ,	   0x1180080942e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1489"            ,	   0x1180080942e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1490"            ,	   0x1180080942e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1491"            ,	   0x1180080942e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1492"            ,	   0x1180080942ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1493"            ,	   0x1180080942ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1494"            ,	   0x1180080942eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1495"            ,	   0x1180080942eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1496"            ,	   0x1180080942ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1497"            ,	   0x1180080942ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1498"            ,	   0x1180080942ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1499"            ,	   0x1180080942ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1500"            ,	   0x1180080942ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1501"            ,	   0x1180080942ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1502"            ,	   0x1180080942ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1503"            ,	   0x1180080942ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1504"            ,	   0x1180080942f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1505"            ,	   0x1180080942f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1506"            ,	   0x1180080942f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1507"            ,	   0x1180080942f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1508"            ,	   0x1180080942f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1509"            ,	   0x1180080942f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1510"            ,	   0x1180080942f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1511"            ,	   0x1180080942f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1512"            ,	   0x1180080942f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1513"            ,	   0x1180080942f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1514"            ,	   0x1180080942f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1515"            ,	   0x1180080942f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1516"            ,	   0x1180080942f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1517"            ,	   0x1180080942f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1518"            ,	   0x1180080942f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1519"            ,	   0x1180080942f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1520"            ,	   0x1180080942f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1521"            ,	   0x1180080942f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1522"            ,	   0x1180080942f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1523"            ,	   0x1180080942f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1524"            ,	   0x1180080942fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1525"            ,	   0x1180080942fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1526"            ,	   0x1180080942fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1527"            ,	   0x1180080942fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1528"            ,	   0x1180080942fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1529"            ,	   0x1180080942fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1530"            ,	   0x1180080942fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1531"            ,	   0x1180080942fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1532"            ,	   0x1180080942fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1533"            ,	   0x1180080942fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1534"            ,	   0x1180080942ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1535"            ,	   0x1180080942ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1536"            ,	   0x1180080943000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1537"            ,	   0x1180080943008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1538"            ,	   0x1180080943010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1539"            ,	   0x1180080943018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1540"            ,	   0x1180080943020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1541"            ,	   0x1180080943028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1542"            ,	   0x1180080943030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1543"            ,	   0x1180080943038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1544"            ,	   0x1180080943040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1545"            ,	   0x1180080943048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1546"            ,	   0x1180080943050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1547"            ,	   0x1180080943058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1548"            ,	   0x1180080943060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1549"            ,	   0x1180080943068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1550"            ,	   0x1180080943070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1551"            ,	   0x1180080943078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1552"            ,	   0x1180080943080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1553"            ,	   0x1180080943088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1554"            ,	   0x1180080943090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1555"            ,	   0x1180080943098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1556"            ,	   0x11800809430a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1557"            ,	   0x11800809430a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1558"            ,	   0x11800809430b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1559"            ,	   0x11800809430b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1560"            ,	   0x11800809430c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1561"            ,	   0x11800809430c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1562"            ,	   0x11800809430d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1563"            ,	   0x11800809430d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1564"            ,	   0x11800809430e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1565"            ,	   0x11800809430e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1566"            ,	   0x11800809430f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1567"            ,	   0x11800809430f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1568"            ,	   0x1180080943100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1569"            ,	   0x1180080943108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1570"            ,	   0x1180080943110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1571"            ,	   0x1180080943118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1572"            ,	   0x1180080943120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1573"            ,	   0x1180080943128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1574"            ,	   0x1180080943130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1575"            ,	   0x1180080943138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1576"            ,	   0x1180080943140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1577"            ,	   0x1180080943148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1578"            ,	   0x1180080943150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1579"            ,	   0x1180080943158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1580"            ,	   0x1180080943160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1581"            ,	   0x1180080943168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1582"            ,	   0x1180080943170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1583"            ,	   0x1180080943178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1584"            ,	   0x1180080943180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1585"            ,	   0x1180080943188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1586"            ,	   0x1180080943190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1587"            ,	   0x1180080943198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1588"            ,	   0x11800809431a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1589"            ,	   0x11800809431a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1590"            ,	   0x11800809431b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1591"            ,	   0x11800809431b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1592"            ,	   0x11800809431c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1593"            ,	   0x11800809431c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1594"            ,	   0x11800809431d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1595"            ,	   0x11800809431d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1596"            ,	   0x11800809431e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1597"            ,	   0x11800809431e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1598"            ,	   0x11800809431f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1599"            ,	   0x11800809431f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1600"            ,	   0x1180080943200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1601"            ,	   0x1180080943208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1602"            ,	   0x1180080943210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1603"            ,	   0x1180080943218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1604"            ,	   0x1180080943220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1605"            ,	   0x1180080943228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1606"            ,	   0x1180080943230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1607"            ,	   0x1180080943238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1608"            ,	   0x1180080943240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1609"            ,	   0x1180080943248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1610"            ,	   0x1180080943250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1611"            ,	   0x1180080943258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1612"            ,	   0x1180080943260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1613"            ,	   0x1180080943268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1614"            ,	   0x1180080943270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1615"            ,	   0x1180080943278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1616"            ,	   0x1180080943280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1617"            ,	   0x1180080943288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1618"            ,	   0x1180080943290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1619"            ,	   0x1180080943298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1620"            ,	   0x11800809432a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1621"            ,	   0x11800809432a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1622"            ,	   0x11800809432b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1623"            ,	   0x11800809432b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1624"            ,	   0x11800809432c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1625"            ,	   0x11800809432c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1626"            ,	   0x11800809432d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1627"            ,	   0x11800809432d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1628"            ,	   0x11800809432e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1629"            ,	   0x11800809432e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1630"            ,	   0x11800809432f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1631"            ,	   0x11800809432f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1632"            ,	   0x1180080943300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1633"            ,	   0x1180080943308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1634"            ,	   0x1180080943310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1635"            ,	   0x1180080943318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1636"            ,	   0x1180080943320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1637"            ,	   0x1180080943328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1638"            ,	   0x1180080943330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1639"            ,	   0x1180080943338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1640"            ,	   0x1180080943340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1641"            ,	   0x1180080943348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1642"            ,	   0x1180080943350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1643"            ,	   0x1180080943358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1644"            ,	   0x1180080943360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1645"            ,	   0x1180080943368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1646"            ,	   0x1180080943370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1647"            ,	   0x1180080943378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1648"            ,	   0x1180080943380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1649"            ,	   0x1180080943388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1650"            ,	   0x1180080943390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1651"            ,	   0x1180080943398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1652"            ,	   0x11800809433a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1653"            ,	   0x11800809433a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1654"            ,	   0x11800809433b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1655"            ,	   0x11800809433b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1656"            ,	   0x11800809433c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1657"            ,	   0x11800809433c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1658"            ,	   0x11800809433d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1659"            ,	   0x11800809433d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1660"            ,	   0x11800809433e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1661"            ,	   0x11800809433e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1662"            ,	   0x11800809433f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1663"            ,	   0x11800809433f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1664"            ,	   0x1180080943400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1665"            ,	   0x1180080943408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1666"            ,	   0x1180080943410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1667"            ,	   0x1180080943418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1668"            ,	   0x1180080943420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1669"            ,	   0x1180080943428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1670"            ,	   0x1180080943430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1671"            ,	   0x1180080943438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1672"            ,	   0x1180080943440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1673"            ,	   0x1180080943448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1674"            ,	   0x1180080943450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1675"            ,	   0x1180080943458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1676"            ,	   0x1180080943460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1677"            ,	   0x1180080943468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1678"            ,	   0x1180080943470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1679"            ,	   0x1180080943478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1680"            ,	   0x1180080943480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1681"            ,	   0x1180080943488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1682"            ,	   0x1180080943490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1683"            ,	   0x1180080943498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1684"            ,	   0x11800809434a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1685"            ,	   0x11800809434a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1686"            ,	   0x11800809434b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1687"            ,	   0x11800809434b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1688"            ,	   0x11800809434c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1689"            ,	   0x11800809434c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1690"            ,	   0x11800809434d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1691"            ,	   0x11800809434d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1692"            ,	   0x11800809434e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1693"            ,	   0x11800809434e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1694"            ,	   0x11800809434f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1695"            ,	   0x11800809434f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1696"            ,	   0x1180080943500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1697"            ,	   0x1180080943508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1698"            ,	   0x1180080943510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1699"            ,	   0x1180080943518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1700"            ,	   0x1180080943520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1701"            ,	   0x1180080943528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1702"            ,	   0x1180080943530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1703"            ,	   0x1180080943538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1704"            ,	   0x1180080943540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1705"            ,	   0x1180080943548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1706"            ,	   0x1180080943550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1707"            ,	   0x1180080943558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1708"            ,	   0x1180080943560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1709"            ,	   0x1180080943568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1710"            ,	   0x1180080943570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1711"            ,	   0x1180080943578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1712"            ,	   0x1180080943580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1713"            ,	   0x1180080943588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1714"            ,	   0x1180080943590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1715"            ,	   0x1180080943598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1716"            ,	   0x11800809435a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1717"            ,	   0x11800809435a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1718"            ,	   0x11800809435b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1719"            ,	   0x11800809435b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1720"            ,	   0x11800809435c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1721"            ,	   0x11800809435c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1722"            ,	   0x11800809435d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1723"            ,	   0x11800809435d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1724"            ,	   0x11800809435e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1725"            ,	   0x11800809435e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1726"            ,	   0x11800809435f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1727"            ,	   0x11800809435f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1728"            ,	   0x1180080943600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1729"            ,	   0x1180080943608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1730"            ,	   0x1180080943610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1731"            ,	   0x1180080943618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1732"            ,	   0x1180080943620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1733"            ,	   0x1180080943628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1734"            ,	   0x1180080943630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1735"            ,	   0x1180080943638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1736"            ,	   0x1180080943640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1737"            ,	   0x1180080943648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1738"            ,	   0x1180080943650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1739"            ,	   0x1180080943658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1740"            ,	   0x1180080943660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1741"            ,	   0x1180080943668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1742"            ,	   0x1180080943670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1743"            ,	   0x1180080943678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1744"            ,	   0x1180080943680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1745"            ,	   0x1180080943688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1746"            ,	   0x1180080943690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1747"            ,	   0x1180080943698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1748"            ,	   0x11800809436a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1749"            ,	   0x11800809436a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1750"            ,	   0x11800809436b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1751"            ,	   0x11800809436b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1752"            ,	   0x11800809436c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1753"            ,	   0x11800809436c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1754"            ,	   0x11800809436d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1755"            ,	   0x11800809436d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1756"            ,	   0x11800809436e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1757"            ,	   0x11800809436e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1758"            ,	   0x11800809436f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1759"            ,	   0x11800809436f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1760"            ,	   0x1180080943700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1761"            ,	   0x1180080943708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1762"            ,	   0x1180080943710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1763"            ,	   0x1180080943718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1764"            ,	   0x1180080943720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1765"            ,	   0x1180080943728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1766"            ,	   0x1180080943730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1767"            ,	   0x1180080943738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1768"            ,	   0x1180080943740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1769"            ,	   0x1180080943748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1770"            ,	   0x1180080943750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1771"            ,	   0x1180080943758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1772"            ,	   0x1180080943760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1773"            ,	   0x1180080943768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1774"            ,	   0x1180080943770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1775"            ,	   0x1180080943778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1776"            ,	   0x1180080943780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1777"            ,	   0x1180080943788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1778"            ,	   0x1180080943790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1779"            ,	   0x1180080943798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1780"            ,	   0x11800809437a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1781"            ,	   0x11800809437a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1782"            ,	   0x11800809437b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1783"            ,	   0x11800809437b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1784"            ,	   0x11800809437c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1785"            ,	   0x11800809437c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1786"            ,	   0x11800809437d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1787"            ,	   0x11800809437d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1788"            ,	   0x11800809437e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1789"            ,	   0x11800809437e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1790"            ,	   0x11800809437f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1791"            ,	   0x11800809437f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1792"            ,	   0x1180080943800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1793"            ,	   0x1180080943808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1794"            ,	   0x1180080943810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1795"            ,	   0x1180080943818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1796"            ,	   0x1180080943820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1797"            ,	   0x1180080943828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1798"            ,	   0x1180080943830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1799"            ,	   0x1180080943838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1800"            ,	   0x1180080943840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1801"            ,	   0x1180080943848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1802"            ,	   0x1180080943850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1803"            ,	   0x1180080943858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1804"            ,	   0x1180080943860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1805"            ,	   0x1180080943868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1806"            ,	   0x1180080943870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1807"            ,	   0x1180080943878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1808"            ,	   0x1180080943880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1809"            ,	   0x1180080943888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1810"            ,	   0x1180080943890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1811"            ,	   0x1180080943898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1812"            ,	   0x11800809438a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1813"            ,	   0x11800809438a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1814"            ,	   0x11800809438b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1815"            ,	   0x11800809438b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1816"            ,	   0x11800809438c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1817"            ,	   0x11800809438c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1818"            ,	   0x11800809438d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1819"            ,	   0x11800809438d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1820"            ,	   0x11800809438e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1821"            ,	   0x11800809438e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1822"            ,	   0x11800809438f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1823"            ,	   0x11800809438f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1824"            ,	   0x1180080943900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1825"            ,	   0x1180080943908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1826"            ,	   0x1180080943910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1827"            ,	   0x1180080943918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1828"            ,	   0x1180080943920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1829"            ,	   0x1180080943928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1830"            ,	   0x1180080943930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1831"            ,	   0x1180080943938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1832"            ,	   0x1180080943940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1833"            ,	   0x1180080943948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1834"            ,	   0x1180080943950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1835"            ,	   0x1180080943958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1836"            ,	   0x1180080943960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1837"            ,	   0x1180080943968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1838"            ,	   0x1180080943970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1839"            ,	   0x1180080943978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1840"            ,	   0x1180080943980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1841"            ,	   0x1180080943988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1842"            ,	   0x1180080943990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1843"            ,	   0x1180080943998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1844"            ,	   0x11800809439a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1845"            ,	   0x11800809439a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1846"            ,	   0x11800809439b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1847"            ,	   0x11800809439b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1848"            ,	   0x11800809439c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1849"            ,	   0x11800809439c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1850"            ,	   0x11800809439d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1851"            ,	   0x11800809439d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1852"            ,	   0x11800809439e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1853"            ,	   0x11800809439e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1854"            ,	   0x11800809439f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1855"            ,	   0x11800809439f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1856"            ,	   0x1180080943a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1857"            ,	   0x1180080943a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1858"            ,	   0x1180080943a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1859"            ,	   0x1180080943a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1860"            ,	   0x1180080943a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1861"            ,	   0x1180080943a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1862"            ,	   0x1180080943a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1863"            ,	   0x1180080943a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1864"            ,	   0x1180080943a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1865"            ,	   0x1180080943a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1866"            ,	   0x1180080943a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1867"            ,	   0x1180080943a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1868"            ,	   0x1180080943a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1869"            ,	   0x1180080943a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1870"            ,	   0x1180080943a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1871"            ,	   0x1180080943a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1872"            ,	   0x1180080943a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1873"            ,	   0x1180080943a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1874"            ,	   0x1180080943a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1875"            ,	   0x1180080943a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1876"            ,	   0x1180080943aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1877"            ,	   0x1180080943aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1878"            ,	   0x1180080943ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1879"            ,	   0x1180080943ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1880"            ,	   0x1180080943ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1881"            ,	   0x1180080943ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1882"            ,	   0x1180080943ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1883"            ,	   0x1180080943ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1884"            ,	   0x1180080943ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1885"            ,	   0x1180080943ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1886"            ,	   0x1180080943af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1887"            ,	   0x1180080943af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1888"            ,	   0x1180080943b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1889"            ,	   0x1180080943b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1890"            ,	   0x1180080943b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1891"            ,	   0x1180080943b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1892"            ,	   0x1180080943b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1893"            ,	   0x1180080943b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1894"            ,	   0x1180080943b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1895"            ,	   0x1180080943b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1896"            ,	   0x1180080943b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1897"            ,	   0x1180080943b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1898"            ,	   0x1180080943b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1899"            ,	   0x1180080943b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1900"            ,	   0x1180080943b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1901"            ,	   0x1180080943b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1902"            ,	   0x1180080943b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1903"            ,	   0x1180080943b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1904"            ,	   0x1180080943b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1905"            ,	   0x1180080943b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1906"            ,	   0x1180080943b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1907"            ,	   0x1180080943b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1908"            ,	   0x1180080943ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1909"            ,	   0x1180080943ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1910"            ,	   0x1180080943bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1911"            ,	   0x1180080943bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1912"            ,	   0x1180080943bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1913"            ,	   0x1180080943bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1914"            ,	   0x1180080943bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1915"            ,	   0x1180080943bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1916"            ,	   0x1180080943be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1917"            ,	   0x1180080943be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1918"            ,	   0x1180080943bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1919"            ,	   0x1180080943bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1920"            ,	   0x1180080943c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1921"            ,	   0x1180080943c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1922"            ,	   0x1180080943c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1923"            ,	   0x1180080943c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1924"            ,	   0x1180080943c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1925"            ,	   0x1180080943c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1926"            ,	   0x1180080943c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1927"            ,	   0x1180080943c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1928"            ,	   0x1180080943c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1929"            ,	   0x1180080943c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1930"            ,	   0x1180080943c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1931"            ,	   0x1180080943c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1932"            ,	   0x1180080943c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1933"            ,	   0x1180080943c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1934"            ,	   0x1180080943c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1935"            ,	   0x1180080943c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1936"            ,	   0x1180080943c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1937"            ,	   0x1180080943c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1938"            ,	   0x1180080943c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1939"            ,	   0x1180080943c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1940"            ,	   0x1180080943ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1941"            ,	   0x1180080943ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1942"            ,	   0x1180080943cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1943"            ,	   0x1180080943cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1944"            ,	   0x1180080943cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1945"            ,	   0x1180080943cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1946"            ,	   0x1180080943cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1947"            ,	   0x1180080943cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1948"            ,	   0x1180080943ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1949"            ,	   0x1180080943ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1950"            ,	   0x1180080943cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1951"            ,	   0x1180080943cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1952"            ,	   0x1180080943d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1953"            ,	   0x1180080943d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1954"            ,	   0x1180080943d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1955"            ,	   0x1180080943d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1956"            ,	   0x1180080943d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1957"            ,	   0x1180080943d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1958"            ,	   0x1180080943d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1959"            ,	   0x1180080943d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1960"            ,	   0x1180080943d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1961"            ,	   0x1180080943d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1962"            ,	   0x1180080943d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1963"            ,	   0x1180080943d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1964"            ,	   0x1180080943d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1965"            ,	   0x1180080943d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1966"            ,	   0x1180080943d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1967"            ,	   0x1180080943d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1968"            ,	   0x1180080943d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1969"            ,	   0x1180080943d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1970"            ,	   0x1180080943d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1971"            ,	   0x1180080943d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1972"            ,	   0x1180080943da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1973"            ,	   0x1180080943da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1974"            ,	   0x1180080943db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1975"            ,	   0x1180080943db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1976"            ,	   0x1180080943dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1977"            ,	   0x1180080943dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1978"            ,	   0x1180080943dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1979"            ,	   0x1180080943dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1980"            ,	   0x1180080943de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1981"            ,	   0x1180080943de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1982"            ,	   0x1180080943df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1983"            ,	   0x1180080943df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1984"            ,	   0x1180080943e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1985"            ,	   0x1180080943e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1986"            ,	   0x1180080943e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1987"            ,	   0x1180080943e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1988"            ,	   0x1180080943e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1989"            ,	   0x1180080943e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1990"            ,	   0x1180080943e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1991"            ,	   0x1180080943e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1992"            ,	   0x1180080943e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1993"            ,	   0x1180080943e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1994"            ,	   0x1180080943e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1995"            ,	   0x1180080943e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1996"            ,	   0x1180080943e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1997"            ,	   0x1180080943e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1998"            ,	   0x1180080943e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP1999"            ,	   0x1180080943e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2000"            ,	   0x1180080943e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2001"            ,	   0x1180080943e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2002"            ,	   0x1180080943e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2003"            ,	   0x1180080943e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2004"            ,	   0x1180080943ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2005"            ,	   0x1180080943ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2006"            ,	   0x1180080943eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2007"            ,	   0x1180080943eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2008"            ,	   0x1180080943ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2009"            ,	   0x1180080943ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2010"            ,	   0x1180080943ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2011"            ,	   0x1180080943ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2012"            ,	   0x1180080943ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2013"            ,	   0x1180080943ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2014"            ,	   0x1180080943ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2015"            ,	   0x1180080943ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2016"            ,	   0x1180080943f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2017"            ,	   0x1180080943f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2018"            ,	   0x1180080943f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2019"            ,	   0x1180080943f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2020"            ,	   0x1180080943f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2021"            ,	   0x1180080943f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2022"            ,	   0x1180080943f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2023"            ,	   0x1180080943f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2024"            ,	   0x1180080943f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2025"            ,	   0x1180080943f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2026"            ,	   0x1180080943f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2027"            ,	   0x1180080943f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2028"            ,	   0x1180080943f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2029"            ,	   0x1180080943f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2030"            ,	   0x1180080943f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2031"            ,	   0x1180080943f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2032"            ,	   0x1180080943f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2033"            ,	   0x1180080943f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2034"            ,	   0x1180080943f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2035"            ,	   0x1180080943f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2036"            ,	   0x1180080943fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2037"            ,	   0x1180080943fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2038"            ,	   0x1180080943fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2039"            ,	   0x1180080943fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2040"            ,	   0x1180080943fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2041"            ,	   0x1180080943fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2042"            ,	   0x1180080943fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2043"            ,	   0x1180080943fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2044"            ,	   0x1180080943fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2045"            ,	   0x1180080943fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2046"            ,	   0x1180080943ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2047"            ,	   0x1180080943ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2048"            ,	   0x1180080944000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2049"            ,	   0x1180080944008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2050"            ,	   0x1180080944010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2051"            ,	   0x1180080944018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2052"            ,	   0x1180080944020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2053"            ,	   0x1180080944028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2054"            ,	   0x1180080944030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2055"            ,	   0x1180080944038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2056"            ,	   0x1180080944040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2057"            ,	   0x1180080944048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2058"            ,	   0x1180080944050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2059"            ,	   0x1180080944058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2060"            ,	   0x1180080944060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2061"            ,	   0x1180080944068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2062"            ,	   0x1180080944070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2063"            ,	   0x1180080944078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2064"            ,	   0x1180080944080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2065"            ,	   0x1180080944088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2066"            ,	   0x1180080944090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2067"            ,	   0x1180080944098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2068"            ,	   0x11800809440a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2069"            ,	   0x11800809440a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2070"            ,	   0x11800809440b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2071"            ,	   0x11800809440b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2072"            ,	   0x11800809440c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2073"            ,	   0x11800809440c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2074"            ,	   0x11800809440d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2075"            ,	   0x11800809440d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2076"            ,	   0x11800809440e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2077"            ,	   0x11800809440e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2078"            ,	   0x11800809440f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2079"            ,	   0x11800809440f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2080"            ,	   0x1180080944100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2081"            ,	   0x1180080944108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2082"            ,	   0x1180080944110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2083"            ,	   0x1180080944118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2084"            ,	   0x1180080944120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2085"            ,	   0x1180080944128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2086"            ,	   0x1180080944130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2087"            ,	   0x1180080944138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2088"            ,	   0x1180080944140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2089"            ,	   0x1180080944148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2090"            ,	   0x1180080944150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2091"            ,	   0x1180080944158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2092"            ,	   0x1180080944160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2093"            ,	   0x1180080944168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2094"            ,	   0x1180080944170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2095"            ,	   0x1180080944178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2096"            ,	   0x1180080944180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2097"            ,	   0x1180080944188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2098"            ,	   0x1180080944190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2099"            ,	   0x1180080944198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2100"            ,	   0x11800809441a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2101"            ,	   0x11800809441a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2102"            ,	   0x11800809441b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2103"            ,	   0x11800809441b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2104"            ,	   0x11800809441c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2105"            ,	   0x11800809441c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2106"            ,	   0x11800809441d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2107"            ,	   0x11800809441d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2108"            ,	   0x11800809441e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2109"            ,	   0x11800809441e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2110"            ,	   0x11800809441f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2111"            ,	   0x11800809441f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2112"            ,	   0x1180080944200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2113"            ,	   0x1180080944208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2114"            ,	   0x1180080944210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2115"            ,	   0x1180080944218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2116"            ,	   0x1180080944220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2117"            ,	   0x1180080944228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2118"            ,	   0x1180080944230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2119"            ,	   0x1180080944238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2120"            ,	   0x1180080944240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2121"            ,	   0x1180080944248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2122"            ,	   0x1180080944250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2123"            ,	   0x1180080944258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2124"            ,	   0x1180080944260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2125"            ,	   0x1180080944268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2126"            ,	   0x1180080944270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2127"            ,	   0x1180080944278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2128"            ,	   0x1180080944280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2129"            ,	   0x1180080944288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2130"            ,	   0x1180080944290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2131"            ,	   0x1180080944298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2132"            ,	   0x11800809442a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2133"            ,	   0x11800809442a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2134"            ,	   0x11800809442b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2135"            ,	   0x11800809442b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2136"            ,	   0x11800809442c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2137"            ,	   0x11800809442c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2138"            ,	   0x11800809442d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2139"            ,	   0x11800809442d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2140"            ,	   0x11800809442e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2141"            ,	   0x11800809442e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2142"            ,	   0x11800809442f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2143"            ,	   0x11800809442f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2144"            ,	   0x1180080944300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2145"            ,	   0x1180080944308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2146"            ,	   0x1180080944310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2147"            ,	   0x1180080944318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2148"            ,	   0x1180080944320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2149"            ,	   0x1180080944328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2150"            ,	   0x1180080944330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2151"            ,	   0x1180080944338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2152"            ,	   0x1180080944340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2153"            ,	   0x1180080944348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2154"            ,	   0x1180080944350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2155"            ,	   0x1180080944358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2156"            ,	   0x1180080944360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2157"            ,	   0x1180080944368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2158"            ,	   0x1180080944370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2159"            ,	   0x1180080944378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2160"            ,	   0x1180080944380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2161"            ,	   0x1180080944388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2162"            ,	   0x1180080944390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2163"            ,	   0x1180080944398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2164"            ,	   0x11800809443a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2165"            ,	   0x11800809443a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2166"            ,	   0x11800809443b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2167"            ,	   0x11800809443b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2168"            ,	   0x11800809443c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2169"            ,	   0x11800809443c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2170"            ,	   0x11800809443d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2171"            ,	   0x11800809443d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2172"            ,	   0x11800809443e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2173"            ,	   0x11800809443e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2174"            ,	   0x11800809443f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2175"            ,	   0x11800809443f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2176"            ,	   0x1180080944400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2177"            ,	   0x1180080944408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2178"            ,	   0x1180080944410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2179"            ,	   0x1180080944418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2180"            ,	   0x1180080944420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2181"            ,	   0x1180080944428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2182"            ,	   0x1180080944430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2183"            ,	   0x1180080944438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2184"            ,	   0x1180080944440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2185"            ,	   0x1180080944448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2186"            ,	   0x1180080944450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2187"            ,	   0x1180080944458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2188"            ,	   0x1180080944460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2189"            ,	   0x1180080944468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2190"            ,	   0x1180080944470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2191"            ,	   0x1180080944478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2192"            ,	   0x1180080944480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2193"            ,	   0x1180080944488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2194"            ,	   0x1180080944490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2195"            ,	   0x1180080944498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2196"            ,	   0x11800809444a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2197"            ,	   0x11800809444a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2198"            ,	   0x11800809444b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2199"            ,	   0x11800809444b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2200"            ,	   0x11800809444c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2201"            ,	   0x11800809444c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2202"            ,	   0x11800809444d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2203"            ,	   0x11800809444d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2204"            ,	   0x11800809444e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2205"            ,	   0x11800809444e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2206"            ,	   0x11800809444f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2207"            ,	   0x11800809444f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2208"            ,	   0x1180080944500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2209"            ,	   0x1180080944508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2210"            ,	   0x1180080944510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2211"            ,	   0x1180080944518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2212"            ,	   0x1180080944520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2213"            ,	   0x1180080944528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2214"            ,	   0x1180080944530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2215"            ,	   0x1180080944538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2216"            ,	   0x1180080944540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2217"            ,	   0x1180080944548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2218"            ,	   0x1180080944550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2219"            ,	   0x1180080944558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2220"            ,	   0x1180080944560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2221"            ,	   0x1180080944568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2222"            ,	   0x1180080944570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2223"            ,	   0x1180080944578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2224"            ,	   0x1180080944580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2225"            ,	   0x1180080944588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2226"            ,	   0x1180080944590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2227"            ,	   0x1180080944598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2228"            ,	   0x11800809445a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2229"            ,	   0x11800809445a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2230"            ,	   0x11800809445b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2231"            ,	   0x11800809445b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2232"            ,	   0x11800809445c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2233"            ,	   0x11800809445c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2234"            ,	   0x11800809445d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2235"            ,	   0x11800809445d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2236"            ,	   0x11800809445e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2237"            ,	   0x11800809445e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2238"            ,	   0x11800809445f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2239"            ,	   0x11800809445f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2240"            ,	   0x1180080944600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2241"            ,	   0x1180080944608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2242"            ,	   0x1180080944610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2243"            ,	   0x1180080944618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2244"            ,	   0x1180080944620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2245"            ,	   0x1180080944628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2246"            ,	   0x1180080944630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2247"            ,	   0x1180080944638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2248"            ,	   0x1180080944640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2249"            ,	   0x1180080944648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2250"            ,	   0x1180080944650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2251"            ,	   0x1180080944658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2252"            ,	   0x1180080944660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2253"            ,	   0x1180080944668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2254"            ,	   0x1180080944670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2255"            ,	   0x1180080944678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2256"            ,	   0x1180080944680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2257"            ,	   0x1180080944688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2258"            ,	   0x1180080944690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2259"            ,	   0x1180080944698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2260"            ,	   0x11800809446a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2261"            ,	   0x11800809446a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2262"            ,	   0x11800809446b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2263"            ,	   0x11800809446b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2264"            ,	   0x11800809446c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2265"            ,	   0x11800809446c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2266"            ,	   0x11800809446d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2267"            ,	   0x11800809446d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2268"            ,	   0x11800809446e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2269"            ,	   0x11800809446e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2270"            ,	   0x11800809446f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2271"            ,	   0x11800809446f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2272"            ,	   0x1180080944700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2273"            ,	   0x1180080944708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2274"            ,	   0x1180080944710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2275"            ,	   0x1180080944718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2276"            ,	   0x1180080944720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2277"            ,	   0x1180080944728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2278"            ,	   0x1180080944730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2279"            ,	   0x1180080944738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2280"            ,	   0x1180080944740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2281"            ,	   0x1180080944748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2282"            ,	   0x1180080944750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2283"            ,	   0x1180080944758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2284"            ,	   0x1180080944760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2285"            ,	   0x1180080944768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2286"            ,	   0x1180080944770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2287"            ,	   0x1180080944778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2288"            ,	   0x1180080944780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2289"            ,	   0x1180080944788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2290"            ,	   0x1180080944790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2291"            ,	   0x1180080944798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2292"            ,	   0x11800809447a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2293"            ,	   0x11800809447a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2294"            ,	   0x11800809447b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2295"            ,	   0x11800809447b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2296"            ,	   0x11800809447c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2297"            ,	   0x11800809447c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2298"            ,	   0x11800809447d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2299"            ,	   0x11800809447d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2300"            ,	   0x11800809447e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2301"            ,	   0x11800809447e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2302"            ,	   0x11800809447f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2303"            ,	   0x11800809447f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2304"            ,	   0x1180080944800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2305"            ,	   0x1180080944808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2306"            ,	   0x1180080944810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2307"            ,	   0x1180080944818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2308"            ,	   0x1180080944820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2309"            ,	   0x1180080944828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2310"            ,	   0x1180080944830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2311"            ,	   0x1180080944838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2312"            ,	   0x1180080944840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2313"            ,	   0x1180080944848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2314"            ,	   0x1180080944850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2315"            ,	   0x1180080944858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2316"            ,	   0x1180080944860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2317"            ,	   0x1180080944868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2318"            ,	   0x1180080944870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2319"            ,	   0x1180080944878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2320"            ,	   0x1180080944880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2321"            ,	   0x1180080944888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2322"            ,	   0x1180080944890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2323"            ,	   0x1180080944898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2324"            ,	   0x11800809448a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2325"            ,	   0x11800809448a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2326"            ,	   0x11800809448b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2327"            ,	   0x11800809448b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2328"            ,	   0x11800809448c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2329"            ,	   0x11800809448c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2330"            ,	   0x11800809448d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2331"            ,	   0x11800809448d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2332"            ,	   0x11800809448e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2333"            ,	   0x11800809448e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2334"            ,	   0x11800809448f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2335"            ,	   0x11800809448f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2336"            ,	   0x1180080944900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2337"            ,	   0x1180080944908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2338"            ,	   0x1180080944910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2339"            ,	   0x1180080944918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2340"            ,	   0x1180080944920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2341"            ,	   0x1180080944928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2342"            ,	   0x1180080944930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2343"            ,	   0x1180080944938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2344"            ,	   0x1180080944940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2345"            ,	   0x1180080944948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2346"            ,	   0x1180080944950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2347"            ,	   0x1180080944958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2348"            ,	   0x1180080944960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2349"            ,	   0x1180080944968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2350"            ,	   0x1180080944970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2351"            ,	   0x1180080944978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2352"            ,	   0x1180080944980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2353"            ,	   0x1180080944988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2354"            ,	   0x1180080944990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2355"            ,	   0x1180080944998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2356"            ,	   0x11800809449a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2357"            ,	   0x11800809449a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2358"            ,	   0x11800809449b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2359"            ,	   0x11800809449b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2360"            ,	   0x11800809449c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2361"            ,	   0x11800809449c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2362"            ,	   0x11800809449d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2363"            ,	   0x11800809449d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2364"            ,	   0x11800809449e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2365"            ,	   0x11800809449e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2366"            ,	   0x11800809449f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2367"            ,	   0x11800809449f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2368"            ,	   0x1180080944a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2369"            ,	   0x1180080944a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2370"            ,	   0x1180080944a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2371"            ,	   0x1180080944a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2372"            ,	   0x1180080944a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2373"            ,	   0x1180080944a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2374"            ,	   0x1180080944a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2375"            ,	   0x1180080944a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2376"            ,	   0x1180080944a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2377"            ,	   0x1180080944a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2378"            ,	   0x1180080944a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2379"            ,	   0x1180080944a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2380"            ,	   0x1180080944a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2381"            ,	   0x1180080944a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2382"            ,	   0x1180080944a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2383"            ,	   0x1180080944a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2384"            ,	   0x1180080944a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2385"            ,	   0x1180080944a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2386"            ,	   0x1180080944a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2387"            ,	   0x1180080944a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2388"            ,	   0x1180080944aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2389"            ,	   0x1180080944aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2390"            ,	   0x1180080944ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2391"            ,	   0x1180080944ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2392"            ,	   0x1180080944ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2393"            ,	   0x1180080944ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2394"            ,	   0x1180080944ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2395"            ,	   0x1180080944ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2396"            ,	   0x1180080944ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2397"            ,	   0x1180080944ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2398"            ,	   0x1180080944af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2399"            ,	   0x1180080944af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2400"            ,	   0x1180080944b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2401"            ,	   0x1180080944b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2402"            ,	   0x1180080944b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2403"            ,	   0x1180080944b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2404"            ,	   0x1180080944b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2405"            ,	   0x1180080944b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2406"            ,	   0x1180080944b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2407"            ,	   0x1180080944b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2408"            ,	   0x1180080944b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2409"            ,	   0x1180080944b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2410"            ,	   0x1180080944b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2411"            ,	   0x1180080944b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2412"            ,	   0x1180080944b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2413"            ,	   0x1180080944b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2414"            ,	   0x1180080944b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2415"            ,	   0x1180080944b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2416"            ,	   0x1180080944b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2417"            ,	   0x1180080944b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2418"            ,	   0x1180080944b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2419"            ,	   0x1180080944b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2420"            ,	   0x1180080944ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2421"            ,	   0x1180080944ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2422"            ,	   0x1180080944bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2423"            ,	   0x1180080944bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2424"            ,	   0x1180080944bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2425"            ,	   0x1180080944bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2426"            ,	   0x1180080944bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2427"            ,	   0x1180080944bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2428"            ,	   0x1180080944be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2429"            ,	   0x1180080944be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2430"            ,	   0x1180080944bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2431"            ,	   0x1180080944bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2432"            ,	   0x1180080944c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2433"            ,	   0x1180080944c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2434"            ,	   0x1180080944c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2435"            ,	   0x1180080944c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2436"            ,	   0x1180080944c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2437"            ,	   0x1180080944c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2438"            ,	   0x1180080944c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2439"            ,	   0x1180080944c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2440"            ,	   0x1180080944c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2441"            ,	   0x1180080944c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2442"            ,	   0x1180080944c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2443"            ,	   0x1180080944c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2444"            ,	   0x1180080944c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2445"            ,	   0x1180080944c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2446"            ,	   0x1180080944c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2447"            ,	   0x1180080944c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2448"            ,	   0x1180080944c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2449"            ,	   0x1180080944c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2450"            ,	   0x1180080944c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2451"            ,	   0x1180080944c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2452"            ,	   0x1180080944ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2453"            ,	   0x1180080944ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2454"            ,	   0x1180080944cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2455"            ,	   0x1180080944cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2456"            ,	   0x1180080944cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2457"            ,	   0x1180080944cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2458"            ,	   0x1180080944cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2459"            ,	   0x1180080944cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2460"            ,	   0x1180080944ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2461"            ,	   0x1180080944ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2462"            ,	   0x1180080944cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2463"            ,	   0x1180080944cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2464"            ,	   0x1180080944d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2465"            ,	   0x1180080944d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2466"            ,	   0x1180080944d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2467"            ,	   0x1180080944d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2468"            ,	   0x1180080944d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2469"            ,	   0x1180080944d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2470"            ,	   0x1180080944d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2471"            ,	   0x1180080944d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2472"            ,	   0x1180080944d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2473"            ,	   0x1180080944d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2474"            ,	   0x1180080944d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2475"            ,	   0x1180080944d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2476"            ,	   0x1180080944d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2477"            ,	   0x1180080944d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2478"            ,	   0x1180080944d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2479"            ,	   0x1180080944d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2480"            ,	   0x1180080944d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2481"            ,	   0x1180080944d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2482"            ,	   0x1180080944d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2483"            ,	   0x1180080944d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2484"            ,	   0x1180080944da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2485"            ,	   0x1180080944da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2486"            ,	   0x1180080944db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2487"            ,	   0x1180080944db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2488"            ,	   0x1180080944dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2489"            ,	   0x1180080944dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2490"            ,	   0x1180080944dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2491"            ,	   0x1180080944dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2492"            ,	   0x1180080944de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2493"            ,	   0x1180080944de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2494"            ,	   0x1180080944df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2495"            ,	   0x1180080944df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2496"            ,	   0x1180080944e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2497"            ,	   0x1180080944e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2498"            ,	   0x1180080944e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2499"            ,	   0x1180080944e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2500"            ,	   0x1180080944e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2501"            ,	   0x1180080944e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2502"            ,	   0x1180080944e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2503"            ,	   0x1180080944e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2504"            ,	   0x1180080944e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2505"            ,	   0x1180080944e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2506"            ,	   0x1180080944e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2507"            ,	   0x1180080944e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2508"            ,	   0x1180080944e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2509"            ,	   0x1180080944e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2510"            ,	   0x1180080944e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2511"            ,	   0x1180080944e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2512"            ,	   0x1180080944e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2513"            ,	   0x1180080944e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2514"            ,	   0x1180080944e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2515"            ,	   0x1180080944e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2516"            ,	   0x1180080944ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2517"            ,	   0x1180080944ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2518"            ,	   0x1180080944eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2519"            ,	   0x1180080944eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2520"            ,	   0x1180080944ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2521"            ,	   0x1180080944ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2522"            ,	   0x1180080944ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2523"            ,	   0x1180080944ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2524"            ,	   0x1180080944ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2525"            ,	   0x1180080944ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2526"            ,	   0x1180080944ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2527"            ,	   0x1180080944ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2528"            ,	   0x1180080944f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2529"            ,	   0x1180080944f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2530"            ,	   0x1180080944f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2531"            ,	   0x1180080944f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2532"            ,	   0x1180080944f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2533"            ,	   0x1180080944f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2534"            ,	   0x1180080944f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2535"            ,	   0x1180080944f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2536"            ,	   0x1180080944f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2537"            ,	   0x1180080944f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2538"            ,	   0x1180080944f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2539"            ,	   0x1180080944f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2540"            ,	   0x1180080944f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2541"            ,	   0x1180080944f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2542"            ,	   0x1180080944f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2543"            ,	   0x1180080944f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2544"            ,	   0x1180080944f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2545"            ,	   0x1180080944f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2546"            ,	   0x1180080944f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2547"            ,	   0x1180080944f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2548"            ,	   0x1180080944fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2549"            ,	   0x1180080944fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2550"            ,	   0x1180080944fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2551"            ,	   0x1180080944fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2552"            ,	   0x1180080944fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2553"            ,	   0x1180080944fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2554"            ,	   0x1180080944fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2555"            ,	   0x1180080944fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2556"            ,	   0x1180080944fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2557"            ,	   0x1180080944fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2558"            ,	   0x1180080944ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2559"            ,	   0x1180080944ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2560"            ,	   0x1180080945000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2561"            ,	   0x1180080945008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2562"            ,	   0x1180080945010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2563"            ,	   0x1180080945018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2564"            ,	   0x1180080945020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2565"            ,	   0x1180080945028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2566"            ,	   0x1180080945030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2567"            ,	   0x1180080945038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2568"            ,	   0x1180080945040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2569"            ,	   0x1180080945048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2570"            ,	   0x1180080945050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2571"            ,	   0x1180080945058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2572"            ,	   0x1180080945060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2573"            ,	   0x1180080945068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2574"            ,	   0x1180080945070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2575"            ,	   0x1180080945078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2576"            ,	   0x1180080945080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2577"            ,	   0x1180080945088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2578"            ,	   0x1180080945090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2579"            ,	   0x1180080945098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2580"            ,	   0x11800809450a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2581"            ,	   0x11800809450a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2582"            ,	   0x11800809450b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2583"            ,	   0x11800809450b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2584"            ,	   0x11800809450c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2585"            ,	   0x11800809450c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2586"            ,	   0x11800809450d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2587"            ,	   0x11800809450d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2588"            ,	   0x11800809450e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2589"            ,	   0x11800809450e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2590"            ,	   0x11800809450f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2591"            ,	   0x11800809450f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2592"            ,	   0x1180080945100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2593"            ,	   0x1180080945108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2594"            ,	   0x1180080945110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2595"            ,	   0x1180080945118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2596"            ,	   0x1180080945120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2597"            ,	   0x1180080945128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2598"            ,	   0x1180080945130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2599"            ,	   0x1180080945138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2600"            ,	   0x1180080945140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2601"            ,	   0x1180080945148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2602"            ,	   0x1180080945150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2603"            ,	   0x1180080945158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2604"            ,	   0x1180080945160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2605"            ,	   0x1180080945168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2606"            ,	   0x1180080945170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2607"            ,	   0x1180080945178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2608"            ,	   0x1180080945180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2609"            ,	   0x1180080945188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2610"            ,	   0x1180080945190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2611"            ,	   0x1180080945198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2612"            ,	   0x11800809451a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2613"            ,	   0x11800809451a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2614"            ,	   0x11800809451b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2615"            ,	   0x11800809451b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2616"            ,	   0x11800809451c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2617"            ,	   0x11800809451c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2618"            ,	   0x11800809451d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2619"            ,	   0x11800809451d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2620"            ,	   0x11800809451e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2621"            ,	   0x11800809451e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2622"            ,	   0x11800809451f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2623"            ,	   0x11800809451f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2624"            ,	   0x1180080945200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2625"            ,	   0x1180080945208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2626"            ,	   0x1180080945210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2627"            ,	   0x1180080945218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2628"            ,	   0x1180080945220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2629"            ,	   0x1180080945228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2630"            ,	   0x1180080945230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2631"            ,	   0x1180080945238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2632"            ,	   0x1180080945240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2633"            ,	   0x1180080945248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2634"            ,	   0x1180080945250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2635"            ,	   0x1180080945258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2636"            ,	   0x1180080945260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2637"            ,	   0x1180080945268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2638"            ,	   0x1180080945270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2639"            ,	   0x1180080945278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2640"            ,	   0x1180080945280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2641"            ,	   0x1180080945288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2642"            ,	   0x1180080945290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2643"            ,	   0x1180080945298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2644"            ,	   0x11800809452a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2645"            ,	   0x11800809452a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2646"            ,	   0x11800809452b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2647"            ,	   0x11800809452b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2648"            ,	   0x11800809452c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2649"            ,	   0x11800809452c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2650"            ,	   0x11800809452d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2651"            ,	   0x11800809452d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2652"            ,	   0x11800809452e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2653"            ,	   0x11800809452e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2654"            ,	   0x11800809452f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2655"            ,	   0x11800809452f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2656"            ,	   0x1180080945300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2657"            ,	   0x1180080945308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2658"            ,	   0x1180080945310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2659"            ,	   0x1180080945318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2660"            ,	   0x1180080945320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2661"            ,	   0x1180080945328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2662"            ,	   0x1180080945330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2663"            ,	   0x1180080945338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2664"            ,	   0x1180080945340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2665"            ,	   0x1180080945348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2666"            ,	   0x1180080945350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2667"            ,	   0x1180080945358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2668"            ,	   0x1180080945360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2669"            ,	   0x1180080945368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2670"            ,	   0x1180080945370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2671"            ,	   0x1180080945378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2672"            ,	   0x1180080945380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2673"            ,	   0x1180080945388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2674"            ,	   0x1180080945390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2675"            ,	   0x1180080945398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2676"            ,	   0x11800809453a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2677"            ,	   0x11800809453a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2678"            ,	   0x11800809453b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2679"            ,	   0x11800809453b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2680"            ,	   0x11800809453c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2681"            ,	   0x11800809453c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2682"            ,	   0x11800809453d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2683"            ,	   0x11800809453d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2684"            ,	   0x11800809453e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2685"            ,	   0x11800809453e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2686"            ,	   0x11800809453f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2687"            ,	   0x11800809453f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2688"            ,	   0x1180080945400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2689"            ,	   0x1180080945408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2690"            ,	   0x1180080945410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2691"            ,	   0x1180080945418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2692"            ,	   0x1180080945420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2693"            ,	   0x1180080945428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2694"            ,	   0x1180080945430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2695"            ,	   0x1180080945438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2696"            ,	   0x1180080945440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2697"            ,	   0x1180080945448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2698"            ,	   0x1180080945450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2699"            ,	   0x1180080945458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2700"            ,	   0x1180080945460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2701"            ,	   0x1180080945468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2702"            ,	   0x1180080945470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2703"            ,	   0x1180080945478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2704"            ,	   0x1180080945480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2705"            ,	   0x1180080945488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2706"            ,	   0x1180080945490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2707"            ,	   0x1180080945498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2708"            ,	   0x11800809454a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2709"            ,	   0x11800809454a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2710"            ,	   0x11800809454b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2711"            ,	   0x11800809454b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2712"            ,	   0x11800809454c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2713"            ,	   0x11800809454c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2714"            ,	   0x11800809454d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2715"            ,	   0x11800809454d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2716"            ,	   0x11800809454e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2717"            ,	   0x11800809454e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2718"            ,	   0x11800809454f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2719"            ,	   0x11800809454f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2720"            ,	   0x1180080945500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2721"            ,	   0x1180080945508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2722"            ,	   0x1180080945510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2723"            ,	   0x1180080945518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2724"            ,	   0x1180080945520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2725"            ,	   0x1180080945528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2726"            ,	   0x1180080945530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2727"            ,	   0x1180080945538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2728"            ,	   0x1180080945540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2729"            ,	   0x1180080945548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2730"            ,	   0x1180080945550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2731"            ,	   0x1180080945558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2732"            ,	   0x1180080945560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2733"            ,	   0x1180080945568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2734"            ,	   0x1180080945570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2735"            ,	   0x1180080945578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2736"            ,	   0x1180080945580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2737"            ,	   0x1180080945588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2738"            ,	   0x1180080945590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2739"            ,	   0x1180080945598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2740"            ,	   0x11800809455a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2741"            ,	   0x11800809455a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2742"            ,	   0x11800809455b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2743"            ,	   0x11800809455b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2744"            ,	   0x11800809455c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2745"            ,	   0x11800809455c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2746"            ,	   0x11800809455d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2747"            ,	   0x11800809455d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2748"            ,	   0x11800809455e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2749"            ,	   0x11800809455e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2750"            ,	   0x11800809455f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2751"            ,	   0x11800809455f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2752"            ,	   0x1180080945600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2753"            ,	   0x1180080945608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2754"            ,	   0x1180080945610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2755"            ,	   0x1180080945618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2756"            ,	   0x1180080945620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2757"            ,	   0x1180080945628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2758"            ,	   0x1180080945630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2759"            ,	   0x1180080945638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2760"            ,	   0x1180080945640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2761"            ,	   0x1180080945648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2762"            ,	   0x1180080945650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2763"            ,	   0x1180080945658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2764"            ,	   0x1180080945660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2765"            ,	   0x1180080945668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2766"            ,	   0x1180080945670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2767"            ,	   0x1180080945678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2768"            ,	   0x1180080945680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2769"            ,	   0x1180080945688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2770"            ,	   0x1180080945690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2771"            ,	   0x1180080945698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2772"            ,	   0x11800809456a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2773"            ,	   0x11800809456a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2774"            ,	   0x11800809456b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2775"            ,	   0x11800809456b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2776"            ,	   0x11800809456c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2777"            ,	   0x11800809456c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2778"            ,	   0x11800809456d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2779"            ,	   0x11800809456d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2780"            ,	   0x11800809456e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2781"            ,	   0x11800809456e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2782"            ,	   0x11800809456f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2783"            ,	   0x11800809456f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2784"            ,	   0x1180080945700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2785"            ,	   0x1180080945708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2786"            ,	   0x1180080945710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2787"            ,	   0x1180080945718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2788"            ,	   0x1180080945720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2789"            ,	   0x1180080945728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2790"            ,	   0x1180080945730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2791"            ,	   0x1180080945738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2792"            ,	   0x1180080945740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2793"            ,	   0x1180080945748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2794"            ,	   0x1180080945750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2795"            ,	   0x1180080945758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2796"            ,	   0x1180080945760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2797"            ,	   0x1180080945768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2798"            ,	   0x1180080945770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2799"            ,	   0x1180080945778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2800"            ,	   0x1180080945780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2801"            ,	   0x1180080945788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2802"            ,	   0x1180080945790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2803"            ,	   0x1180080945798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2804"            ,	   0x11800809457a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2805"            ,	   0x11800809457a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2806"            ,	   0x11800809457b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2807"            ,	   0x11800809457b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2808"            ,	   0x11800809457c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2809"            ,	   0x11800809457c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2810"            ,	   0x11800809457d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2811"            ,	   0x11800809457d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2812"            ,	   0x11800809457e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2813"            ,	   0x11800809457e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2814"            ,	   0x11800809457f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2815"            ,	   0x11800809457f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2816"            ,	   0x1180080945800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2817"            ,	   0x1180080945808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2818"            ,	   0x1180080945810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2819"            ,	   0x1180080945818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2820"            ,	   0x1180080945820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2821"            ,	   0x1180080945828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2822"            ,	   0x1180080945830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2823"            ,	   0x1180080945838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2824"            ,	   0x1180080945840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2825"            ,	   0x1180080945848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2826"            ,	   0x1180080945850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2827"            ,	   0x1180080945858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2828"            ,	   0x1180080945860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2829"            ,	   0x1180080945868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2830"            ,	   0x1180080945870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2831"            ,	   0x1180080945878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2832"            ,	   0x1180080945880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2833"            ,	   0x1180080945888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2834"            ,	   0x1180080945890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2835"            ,	   0x1180080945898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2836"            ,	   0x11800809458a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2837"            ,	   0x11800809458a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2838"            ,	   0x11800809458b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2839"            ,	   0x11800809458b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2840"            ,	   0x11800809458c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2841"            ,	   0x11800809458c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2842"            ,	   0x11800809458d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2843"            ,	   0x11800809458d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2844"            ,	   0x11800809458e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2845"            ,	   0x11800809458e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2846"            ,	   0x11800809458f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2847"            ,	   0x11800809458f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2848"            ,	   0x1180080945900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2849"            ,	   0x1180080945908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2850"            ,	   0x1180080945910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2851"            ,	   0x1180080945918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2852"            ,	   0x1180080945920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2853"            ,	   0x1180080945928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2854"            ,	   0x1180080945930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2855"            ,	   0x1180080945938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2856"            ,	   0x1180080945940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2857"            ,	   0x1180080945948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2858"            ,	   0x1180080945950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2859"            ,	   0x1180080945958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2860"            ,	   0x1180080945960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2861"            ,	   0x1180080945968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2862"            ,	   0x1180080945970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2863"            ,	   0x1180080945978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2864"            ,	   0x1180080945980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2865"            ,	   0x1180080945988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2866"            ,	   0x1180080945990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2867"            ,	   0x1180080945998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2868"            ,	   0x11800809459a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2869"            ,	   0x11800809459a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2870"            ,	   0x11800809459b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2871"            ,	   0x11800809459b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2872"            ,	   0x11800809459c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2873"            ,	   0x11800809459c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2874"            ,	   0x11800809459d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2875"            ,	   0x11800809459d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2876"            ,	   0x11800809459e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2877"            ,	   0x11800809459e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2878"            ,	   0x11800809459f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2879"            ,	   0x11800809459f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2880"            ,	   0x1180080945a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2881"            ,	   0x1180080945a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2882"            ,	   0x1180080945a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2883"            ,	   0x1180080945a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2884"            ,	   0x1180080945a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2885"            ,	   0x1180080945a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2886"            ,	   0x1180080945a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2887"            ,	   0x1180080945a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2888"            ,	   0x1180080945a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2889"            ,	   0x1180080945a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2890"            ,	   0x1180080945a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2891"            ,	   0x1180080945a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2892"            ,	   0x1180080945a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2893"            ,	   0x1180080945a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2894"            ,	   0x1180080945a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2895"            ,	   0x1180080945a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2896"            ,	   0x1180080945a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2897"            ,	   0x1180080945a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2898"            ,	   0x1180080945a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2899"            ,	   0x1180080945a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2900"            ,	   0x1180080945aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2901"            ,	   0x1180080945aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2902"            ,	   0x1180080945ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2903"            ,	   0x1180080945ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2904"            ,	   0x1180080945ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2905"            ,	   0x1180080945ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2906"            ,	   0x1180080945ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2907"            ,	   0x1180080945ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2908"            ,	   0x1180080945ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2909"            ,	   0x1180080945ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2910"            ,	   0x1180080945af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2911"            ,	   0x1180080945af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2912"            ,	   0x1180080945b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2913"            ,	   0x1180080945b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2914"            ,	   0x1180080945b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2915"            ,	   0x1180080945b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2916"            ,	   0x1180080945b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2917"            ,	   0x1180080945b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2918"            ,	   0x1180080945b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2919"            ,	   0x1180080945b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2920"            ,	   0x1180080945b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2921"            ,	   0x1180080945b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2922"            ,	   0x1180080945b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2923"            ,	   0x1180080945b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2924"            ,	   0x1180080945b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2925"            ,	   0x1180080945b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2926"            ,	   0x1180080945b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2927"            ,	   0x1180080945b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2928"            ,	   0x1180080945b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2929"            ,	   0x1180080945b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2930"            ,	   0x1180080945b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2931"            ,	   0x1180080945b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2932"            ,	   0x1180080945ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2933"            ,	   0x1180080945ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2934"            ,	   0x1180080945bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2935"            ,	   0x1180080945bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2936"            ,	   0x1180080945bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2937"            ,	   0x1180080945bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2938"            ,	   0x1180080945bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2939"            ,	   0x1180080945bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2940"            ,	   0x1180080945be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2941"            ,	   0x1180080945be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2942"            ,	   0x1180080945bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2943"            ,	   0x1180080945bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2944"            ,	   0x1180080945c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2945"            ,	   0x1180080945c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2946"            ,	   0x1180080945c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2947"            ,	   0x1180080945c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2948"            ,	   0x1180080945c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2949"            ,	   0x1180080945c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2950"            ,	   0x1180080945c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2951"            ,	   0x1180080945c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2952"            ,	   0x1180080945c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2953"            ,	   0x1180080945c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2954"            ,	   0x1180080945c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2955"            ,	   0x1180080945c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2956"            ,	   0x1180080945c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2957"            ,	   0x1180080945c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2958"            ,	   0x1180080945c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2959"            ,	   0x1180080945c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2960"            ,	   0x1180080945c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2961"            ,	   0x1180080945c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2962"            ,	   0x1180080945c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2963"            ,	   0x1180080945c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2964"            ,	   0x1180080945ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2965"            ,	   0x1180080945ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2966"            ,	   0x1180080945cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2967"            ,	   0x1180080945cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2968"            ,	   0x1180080945cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2969"            ,	   0x1180080945cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2970"            ,	   0x1180080945cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2971"            ,	   0x1180080945cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2972"            ,	   0x1180080945ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2973"            ,	   0x1180080945ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2974"            ,	   0x1180080945cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2975"            ,	   0x1180080945cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2976"            ,	   0x1180080945d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2977"            ,	   0x1180080945d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2978"            ,	   0x1180080945d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2979"            ,	   0x1180080945d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2980"            ,	   0x1180080945d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2981"            ,	   0x1180080945d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2982"            ,	   0x1180080945d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2983"            ,	   0x1180080945d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2984"            ,	   0x1180080945d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2985"            ,	   0x1180080945d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2986"            ,	   0x1180080945d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2987"            ,	   0x1180080945d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2988"            ,	   0x1180080945d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2989"            ,	   0x1180080945d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2990"            ,	   0x1180080945d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2991"            ,	   0x1180080945d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2992"            ,	   0x1180080945d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2993"            ,	   0x1180080945d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2994"            ,	   0x1180080945d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2995"            ,	   0x1180080945d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2996"            ,	   0x1180080945da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2997"            ,	   0x1180080945da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2998"            ,	   0x1180080945db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP2999"            ,	   0x1180080945db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3000"            ,	   0x1180080945dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3001"            ,	   0x1180080945dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3002"            ,	   0x1180080945dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3003"            ,	   0x1180080945dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3004"            ,	   0x1180080945de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3005"            ,	   0x1180080945de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3006"            ,	   0x1180080945df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3007"            ,	   0x1180080945df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3008"            ,	   0x1180080945e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3009"            ,	   0x1180080945e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3010"            ,	   0x1180080945e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3011"            ,	   0x1180080945e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3012"            ,	   0x1180080945e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3013"            ,	   0x1180080945e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3014"            ,	   0x1180080945e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3015"            ,	   0x1180080945e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3016"            ,	   0x1180080945e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3017"            ,	   0x1180080945e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3018"            ,	   0x1180080945e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3019"            ,	   0x1180080945e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3020"            ,	   0x1180080945e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3021"            ,	   0x1180080945e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3022"            ,	   0x1180080945e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3023"            ,	   0x1180080945e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3024"            ,	   0x1180080945e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3025"            ,	   0x1180080945e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3026"            ,	   0x1180080945e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3027"            ,	   0x1180080945e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3028"            ,	   0x1180080945ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3029"            ,	   0x1180080945ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3030"            ,	   0x1180080945eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3031"            ,	   0x1180080945eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3032"            ,	   0x1180080945ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3033"            ,	   0x1180080945ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3034"            ,	   0x1180080945ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3035"            ,	   0x1180080945ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3036"            ,	   0x1180080945ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3037"            ,	   0x1180080945ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3038"            ,	   0x1180080945ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3039"            ,	   0x1180080945ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3040"            ,	   0x1180080945f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3041"            ,	   0x1180080945f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3042"            ,	   0x1180080945f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3043"            ,	   0x1180080945f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3044"            ,	   0x1180080945f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3045"            ,	   0x1180080945f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3046"            ,	   0x1180080945f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3047"            ,	   0x1180080945f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3048"            ,	   0x1180080945f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3049"            ,	   0x1180080945f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3050"            ,	   0x1180080945f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3051"            ,	   0x1180080945f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3052"            ,	   0x1180080945f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3053"            ,	   0x1180080945f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3054"            ,	   0x1180080945f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3055"            ,	   0x1180080945f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3056"            ,	   0x1180080945f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3057"            ,	   0x1180080945f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3058"            ,	   0x1180080945f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3059"            ,	   0x1180080945f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3060"            ,	   0x1180080945fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3061"            ,	   0x1180080945fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3062"            ,	   0x1180080945fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3063"            ,	   0x1180080945fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3064"            ,	   0x1180080945fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3065"            ,	   0x1180080945fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3066"            ,	   0x1180080945fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3067"            ,	   0x1180080945fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3068"            ,	   0x1180080945fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3069"            ,	   0x1180080945fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3070"            ,	   0x1180080945ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3071"            ,	   0x1180080945ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3072"            ,	   0x1180080946000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3073"            ,	   0x1180080946008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3074"            ,	   0x1180080946010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3075"            ,	   0x1180080946018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3076"            ,	   0x1180080946020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3077"            ,	   0x1180080946028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3078"            ,	   0x1180080946030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3079"            ,	   0x1180080946038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3080"            ,	   0x1180080946040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3081"            ,	   0x1180080946048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3082"            ,	   0x1180080946050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3083"            ,	   0x1180080946058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3084"            ,	   0x1180080946060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3085"            ,	   0x1180080946068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3086"            ,	   0x1180080946070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3087"            ,	   0x1180080946078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3088"            ,	   0x1180080946080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3089"            ,	   0x1180080946088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3090"            ,	   0x1180080946090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3091"            ,	   0x1180080946098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3092"            ,	   0x11800809460a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3093"            ,	   0x11800809460a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3094"            ,	   0x11800809460b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3095"            ,	   0x11800809460b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3096"            ,	   0x11800809460c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3097"            ,	   0x11800809460c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3098"            ,	   0x11800809460d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3099"            ,	   0x11800809460d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3100"            ,	   0x11800809460e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3101"            ,	   0x11800809460e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3102"            ,	   0x11800809460f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3103"            ,	   0x11800809460f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3104"            ,	   0x1180080946100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3105"            ,	   0x1180080946108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3106"            ,	   0x1180080946110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3107"            ,	   0x1180080946118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3108"            ,	   0x1180080946120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3109"            ,	   0x1180080946128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3110"            ,	   0x1180080946130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3111"            ,	   0x1180080946138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3112"            ,	   0x1180080946140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3113"            ,	   0x1180080946148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3114"            ,	   0x1180080946150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3115"            ,	   0x1180080946158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3116"            ,	   0x1180080946160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3117"            ,	   0x1180080946168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3118"            ,	   0x1180080946170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3119"            ,	   0x1180080946178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3120"            ,	   0x1180080946180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3121"            ,	   0x1180080946188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3122"            ,	   0x1180080946190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3123"            ,	   0x1180080946198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3124"            ,	   0x11800809461a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3125"            ,	   0x11800809461a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3126"            ,	   0x11800809461b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3127"            ,	   0x11800809461b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3128"            ,	   0x11800809461c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3129"            ,	   0x11800809461c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3130"            ,	   0x11800809461d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3131"            ,	   0x11800809461d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3132"            ,	   0x11800809461e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3133"            ,	   0x11800809461e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3134"            ,	   0x11800809461f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3135"            ,	   0x11800809461f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3136"            ,	   0x1180080946200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3137"            ,	   0x1180080946208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3138"            ,	   0x1180080946210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3139"            ,	   0x1180080946218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3140"            ,	   0x1180080946220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3141"            ,	   0x1180080946228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3142"            ,	   0x1180080946230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3143"            ,	   0x1180080946238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3144"            ,	   0x1180080946240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3145"            ,	   0x1180080946248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3146"            ,	   0x1180080946250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3147"            ,	   0x1180080946258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3148"            ,	   0x1180080946260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3149"            ,	   0x1180080946268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3150"            ,	   0x1180080946270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3151"            ,	   0x1180080946278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3152"            ,	   0x1180080946280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3153"            ,	   0x1180080946288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3154"            ,	   0x1180080946290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3155"            ,	   0x1180080946298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3156"            ,	   0x11800809462a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3157"            ,	   0x11800809462a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3158"            ,	   0x11800809462b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3159"            ,	   0x11800809462b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3160"            ,	   0x11800809462c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3161"            ,	   0x11800809462c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3162"            ,	   0x11800809462d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3163"            ,	   0x11800809462d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3164"            ,	   0x11800809462e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3165"            ,	   0x11800809462e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3166"            ,	   0x11800809462f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3167"            ,	   0x11800809462f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3168"            ,	   0x1180080946300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3169"            ,	   0x1180080946308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3170"            ,	   0x1180080946310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3171"            ,	   0x1180080946318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3172"            ,	   0x1180080946320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3173"            ,	   0x1180080946328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3174"            ,	   0x1180080946330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3175"            ,	   0x1180080946338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3176"            ,	   0x1180080946340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3177"            ,	   0x1180080946348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3178"            ,	   0x1180080946350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3179"            ,	   0x1180080946358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3180"            ,	   0x1180080946360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3181"            ,	   0x1180080946368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3182"            ,	   0x1180080946370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3183"            ,	   0x1180080946378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3184"            ,	   0x1180080946380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3185"            ,	   0x1180080946388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3186"            ,	   0x1180080946390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3187"            ,	   0x1180080946398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3188"            ,	   0x11800809463a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3189"            ,	   0x11800809463a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3190"            ,	   0x11800809463b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3191"            ,	   0x11800809463b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3192"            ,	   0x11800809463c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3193"            ,	   0x11800809463c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3194"            ,	   0x11800809463d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3195"            ,	   0x11800809463d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3196"            ,	   0x11800809463e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3197"            ,	   0x11800809463e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3198"            ,	   0x11800809463f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3199"            ,	   0x11800809463f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3200"            ,	   0x1180080946400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3201"            ,	   0x1180080946408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3202"            ,	   0x1180080946410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3203"            ,	   0x1180080946418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3204"            ,	   0x1180080946420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3205"            ,	   0x1180080946428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3206"            ,	   0x1180080946430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3207"            ,	   0x1180080946438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3208"            ,	   0x1180080946440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3209"            ,	   0x1180080946448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3210"            ,	   0x1180080946450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3211"            ,	   0x1180080946458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3212"            ,	   0x1180080946460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3213"            ,	   0x1180080946468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3214"            ,	   0x1180080946470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3215"            ,	   0x1180080946478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3216"            ,	   0x1180080946480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3217"            ,	   0x1180080946488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3218"            ,	   0x1180080946490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3219"            ,	   0x1180080946498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3220"            ,	   0x11800809464a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3221"            ,	   0x11800809464a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3222"            ,	   0x11800809464b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3223"            ,	   0x11800809464b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3224"            ,	   0x11800809464c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3225"            ,	   0x11800809464c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3226"            ,	   0x11800809464d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3227"            ,	   0x11800809464d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3228"            ,	   0x11800809464e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3229"            ,	   0x11800809464e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3230"            ,	   0x11800809464f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3231"            ,	   0x11800809464f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3232"            ,	   0x1180080946500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3233"            ,	   0x1180080946508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3234"            ,	   0x1180080946510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3235"            ,	   0x1180080946518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3236"            ,	   0x1180080946520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3237"            ,	   0x1180080946528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3238"            ,	   0x1180080946530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3239"            ,	   0x1180080946538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3240"            ,	   0x1180080946540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3241"            ,	   0x1180080946548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3242"            ,	   0x1180080946550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3243"            ,	   0x1180080946558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3244"            ,	   0x1180080946560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3245"            ,	   0x1180080946568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3246"            ,	   0x1180080946570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3247"            ,	   0x1180080946578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3248"            ,	   0x1180080946580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3249"            ,	   0x1180080946588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3250"            ,	   0x1180080946590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3251"            ,	   0x1180080946598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3252"            ,	   0x11800809465a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3253"            ,	   0x11800809465a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3254"            ,	   0x11800809465b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3255"            ,	   0x11800809465b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3256"            ,	   0x11800809465c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3257"            ,	   0x11800809465c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3258"            ,	   0x11800809465d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3259"            ,	   0x11800809465d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3260"            ,	   0x11800809465e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3261"            ,	   0x11800809465e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3262"            ,	   0x11800809465f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3263"            ,	   0x11800809465f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3264"            ,	   0x1180080946600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3265"            ,	   0x1180080946608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3266"            ,	   0x1180080946610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3267"            ,	   0x1180080946618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3268"            ,	   0x1180080946620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3269"            ,	   0x1180080946628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3270"            ,	   0x1180080946630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3271"            ,	   0x1180080946638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3272"            ,	   0x1180080946640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3273"            ,	   0x1180080946648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3274"            ,	   0x1180080946650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3275"            ,	   0x1180080946658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3276"            ,	   0x1180080946660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3277"            ,	   0x1180080946668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3278"            ,	   0x1180080946670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3279"            ,	   0x1180080946678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3280"            ,	   0x1180080946680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3281"            ,	   0x1180080946688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3282"            ,	   0x1180080946690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3283"            ,	   0x1180080946698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3284"            ,	   0x11800809466a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3285"            ,	   0x11800809466a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3286"            ,	   0x11800809466b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3287"            ,	   0x11800809466b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3288"            ,	   0x11800809466c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3289"            ,	   0x11800809466c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3290"            ,	   0x11800809466d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3291"            ,	   0x11800809466d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3292"            ,	   0x11800809466e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3293"            ,	   0x11800809466e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3294"            ,	   0x11800809466f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3295"            ,	   0x11800809466f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3296"            ,	   0x1180080946700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3297"            ,	   0x1180080946708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3298"            ,	   0x1180080946710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3299"            ,	   0x1180080946718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3300"            ,	   0x1180080946720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3301"            ,	   0x1180080946728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3302"            ,	   0x1180080946730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3303"            ,	   0x1180080946738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3304"            ,	   0x1180080946740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3305"            ,	   0x1180080946748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3306"            ,	   0x1180080946750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3307"            ,	   0x1180080946758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3308"            ,	   0x1180080946760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3309"            ,	   0x1180080946768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3310"            ,	   0x1180080946770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3311"            ,	   0x1180080946778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3312"            ,	   0x1180080946780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3313"            ,	   0x1180080946788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3314"            ,	   0x1180080946790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3315"            ,	   0x1180080946798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3316"            ,	   0x11800809467a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3317"            ,	   0x11800809467a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3318"            ,	   0x11800809467b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3319"            ,	   0x11800809467b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3320"            ,	   0x11800809467c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3321"            ,	   0x11800809467c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3322"            ,	   0x11800809467d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3323"            ,	   0x11800809467d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3324"            ,	   0x11800809467e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3325"            ,	   0x11800809467e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3326"            ,	   0x11800809467f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3327"            ,	   0x11800809467f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3328"            ,	   0x1180080946800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3329"            ,	   0x1180080946808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3330"            ,	   0x1180080946810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3331"            ,	   0x1180080946818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3332"            ,	   0x1180080946820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3333"            ,	   0x1180080946828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3334"            ,	   0x1180080946830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3335"            ,	   0x1180080946838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3336"            ,	   0x1180080946840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3337"            ,	   0x1180080946848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3338"            ,	   0x1180080946850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3339"            ,	   0x1180080946858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3340"            ,	   0x1180080946860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3341"            ,	   0x1180080946868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3342"            ,	   0x1180080946870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3343"            ,	   0x1180080946878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3344"            ,	   0x1180080946880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3345"            ,	   0x1180080946888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3346"            ,	   0x1180080946890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3347"            ,	   0x1180080946898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3348"            ,	   0x11800809468a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3349"            ,	   0x11800809468a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3350"            ,	   0x11800809468b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3351"            ,	   0x11800809468b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3352"            ,	   0x11800809468c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3353"            ,	   0x11800809468c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3354"            ,	   0x11800809468d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3355"            ,	   0x11800809468d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3356"            ,	   0x11800809468e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3357"            ,	   0x11800809468e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3358"            ,	   0x11800809468f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3359"            ,	   0x11800809468f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3360"            ,	   0x1180080946900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3361"            ,	   0x1180080946908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3362"            ,	   0x1180080946910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3363"            ,	   0x1180080946918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3364"            ,	   0x1180080946920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3365"            ,	   0x1180080946928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3366"            ,	   0x1180080946930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3367"            ,	   0x1180080946938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3368"            ,	   0x1180080946940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3369"            ,	   0x1180080946948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3370"            ,	   0x1180080946950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3371"            ,	   0x1180080946958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3372"            ,	   0x1180080946960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3373"            ,	   0x1180080946968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3374"            ,	   0x1180080946970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3375"            ,	   0x1180080946978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3376"            ,	   0x1180080946980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3377"            ,	   0x1180080946988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3378"            ,	   0x1180080946990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3379"            ,	   0x1180080946998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3380"            ,	   0x11800809469a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3381"            ,	   0x11800809469a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3382"            ,	   0x11800809469b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3383"            ,	   0x11800809469b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3384"            ,	   0x11800809469c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3385"            ,	   0x11800809469c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3386"            ,	   0x11800809469d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3387"            ,	   0x11800809469d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3388"            ,	   0x11800809469e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3389"            ,	   0x11800809469e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3390"            ,	   0x11800809469f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3391"            ,	   0x11800809469f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3392"            ,	   0x1180080946a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3393"            ,	   0x1180080946a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3394"            ,	   0x1180080946a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3395"            ,	   0x1180080946a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3396"            ,	   0x1180080946a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3397"            ,	   0x1180080946a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3398"            ,	   0x1180080946a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3399"            ,	   0x1180080946a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3400"            ,	   0x1180080946a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3401"            ,	   0x1180080946a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3402"            ,	   0x1180080946a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3403"            ,	   0x1180080946a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3404"            ,	   0x1180080946a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3405"            ,	   0x1180080946a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3406"            ,	   0x1180080946a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3407"            ,	   0x1180080946a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3408"            ,	   0x1180080946a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3409"            ,	   0x1180080946a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3410"            ,	   0x1180080946a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3411"            ,	   0x1180080946a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3412"            ,	   0x1180080946aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3413"            ,	   0x1180080946aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3414"            ,	   0x1180080946ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3415"            ,	   0x1180080946ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3416"            ,	   0x1180080946ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3417"            ,	   0x1180080946ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3418"            ,	   0x1180080946ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3419"            ,	   0x1180080946ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3420"            ,	   0x1180080946ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3421"            ,	   0x1180080946ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3422"            ,	   0x1180080946af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3423"            ,	   0x1180080946af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3424"            ,	   0x1180080946b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3425"            ,	   0x1180080946b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3426"            ,	   0x1180080946b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3427"            ,	   0x1180080946b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3428"            ,	   0x1180080946b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3429"            ,	   0x1180080946b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3430"            ,	   0x1180080946b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3431"            ,	   0x1180080946b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3432"            ,	   0x1180080946b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3433"            ,	   0x1180080946b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3434"            ,	   0x1180080946b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3435"            ,	   0x1180080946b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3436"            ,	   0x1180080946b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3437"            ,	   0x1180080946b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3438"            ,	   0x1180080946b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3439"            ,	   0x1180080946b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3440"            ,	   0x1180080946b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3441"            ,	   0x1180080946b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3442"            ,	   0x1180080946b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3443"            ,	   0x1180080946b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3444"            ,	   0x1180080946ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3445"            ,	   0x1180080946ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3446"            ,	   0x1180080946bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3447"            ,	   0x1180080946bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3448"            ,	   0x1180080946bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3449"            ,	   0x1180080946bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3450"            ,	   0x1180080946bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3451"            ,	   0x1180080946bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3452"            ,	   0x1180080946be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3453"            ,	   0x1180080946be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3454"            ,	   0x1180080946bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3455"            ,	   0x1180080946bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3456"            ,	   0x1180080946c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3457"            ,	   0x1180080946c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3458"            ,	   0x1180080946c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3459"            ,	   0x1180080946c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3460"            ,	   0x1180080946c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3461"            ,	   0x1180080946c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3462"            ,	   0x1180080946c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3463"            ,	   0x1180080946c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3464"            ,	   0x1180080946c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3465"            ,	   0x1180080946c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3466"            ,	   0x1180080946c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3467"            ,	   0x1180080946c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3468"            ,	   0x1180080946c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3469"            ,	   0x1180080946c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3470"            ,	   0x1180080946c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3471"            ,	   0x1180080946c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3472"            ,	   0x1180080946c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3473"            ,	   0x1180080946c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3474"            ,	   0x1180080946c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3475"            ,	   0x1180080946c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3476"            ,	   0x1180080946ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3477"            ,	   0x1180080946ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3478"            ,	   0x1180080946cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3479"            ,	   0x1180080946cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3480"            ,	   0x1180080946cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3481"            ,	   0x1180080946cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3482"            ,	   0x1180080946cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3483"            ,	   0x1180080946cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3484"            ,	   0x1180080946ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3485"            ,	   0x1180080946ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3486"            ,	   0x1180080946cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3487"            ,	   0x1180080946cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3488"            ,	   0x1180080946d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3489"            ,	   0x1180080946d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3490"            ,	   0x1180080946d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3491"            ,	   0x1180080946d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3492"            ,	   0x1180080946d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3493"            ,	   0x1180080946d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3494"            ,	   0x1180080946d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3495"            ,	   0x1180080946d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3496"            ,	   0x1180080946d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3497"            ,	   0x1180080946d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3498"            ,	   0x1180080946d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3499"            ,	   0x1180080946d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3500"            ,	   0x1180080946d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3501"            ,	   0x1180080946d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3502"            ,	   0x1180080946d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3503"            ,	   0x1180080946d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3504"            ,	   0x1180080946d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3505"            ,	   0x1180080946d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3506"            ,	   0x1180080946d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3507"            ,	   0x1180080946d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3508"            ,	   0x1180080946da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3509"            ,	   0x1180080946da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3510"            ,	   0x1180080946db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3511"            ,	   0x1180080946db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3512"            ,	   0x1180080946dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3513"            ,	   0x1180080946dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3514"            ,	   0x1180080946dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3515"            ,	   0x1180080946dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3516"            ,	   0x1180080946de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3517"            ,	   0x1180080946de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3518"            ,	   0x1180080946df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3519"            ,	   0x1180080946df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3520"            ,	   0x1180080946e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3521"            ,	   0x1180080946e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3522"            ,	   0x1180080946e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3523"            ,	   0x1180080946e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3524"            ,	   0x1180080946e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3525"            ,	   0x1180080946e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3526"            ,	   0x1180080946e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3527"            ,	   0x1180080946e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3528"            ,	   0x1180080946e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3529"            ,	   0x1180080946e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3530"            ,	   0x1180080946e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3531"            ,	   0x1180080946e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3532"            ,	   0x1180080946e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3533"            ,	   0x1180080946e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3534"            ,	   0x1180080946e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3535"            ,	   0x1180080946e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3536"            ,	   0x1180080946e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3537"            ,	   0x1180080946e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3538"            ,	   0x1180080946e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3539"            ,	   0x1180080946e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3540"            ,	   0x1180080946ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3541"            ,	   0x1180080946ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3542"            ,	   0x1180080946eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3543"            ,	   0x1180080946eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3544"            ,	   0x1180080946ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3545"            ,	   0x1180080946ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3546"            ,	   0x1180080946ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3547"            ,	   0x1180080946ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3548"            ,	   0x1180080946ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3549"            ,	   0x1180080946ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3550"            ,	   0x1180080946ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3551"            ,	   0x1180080946ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3552"            ,	   0x1180080946f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3553"            ,	   0x1180080946f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3554"            ,	   0x1180080946f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3555"            ,	   0x1180080946f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3556"            ,	   0x1180080946f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3557"            ,	   0x1180080946f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3558"            ,	   0x1180080946f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3559"            ,	   0x1180080946f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3560"            ,	   0x1180080946f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3561"            ,	   0x1180080946f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3562"            ,	   0x1180080946f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3563"            ,	   0x1180080946f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3564"            ,	   0x1180080946f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3565"            ,	   0x1180080946f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3566"            ,	   0x1180080946f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3567"            ,	   0x1180080946f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3568"            ,	   0x1180080946f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3569"            ,	   0x1180080946f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3570"            ,	   0x1180080946f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3571"            ,	   0x1180080946f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3572"            ,	   0x1180080946fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3573"            ,	   0x1180080946fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3574"            ,	   0x1180080946fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3575"            ,	   0x1180080946fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3576"            ,	   0x1180080946fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3577"            ,	   0x1180080946fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3578"            ,	   0x1180080946fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3579"            ,	   0x1180080946fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3580"            ,	   0x1180080946fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3581"            ,	   0x1180080946fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3582"            ,	   0x1180080946ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3583"            ,	   0x1180080946ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3584"            ,	   0x1180080947000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3585"            ,	   0x1180080947008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3586"            ,	   0x1180080947010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3587"            ,	   0x1180080947018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3588"            ,	   0x1180080947020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3589"            ,	   0x1180080947028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3590"            ,	   0x1180080947030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3591"            ,	   0x1180080947038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3592"            ,	   0x1180080947040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3593"            ,	   0x1180080947048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3594"            ,	   0x1180080947050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3595"            ,	   0x1180080947058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3596"            ,	   0x1180080947060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3597"            ,	   0x1180080947068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3598"            ,	   0x1180080947070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3599"            ,	   0x1180080947078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3600"            ,	   0x1180080947080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3601"            ,	   0x1180080947088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3602"            ,	   0x1180080947090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3603"            ,	   0x1180080947098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3604"            ,	   0x11800809470a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3605"            ,	   0x11800809470a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3606"            ,	   0x11800809470b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3607"            ,	   0x11800809470b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3608"            ,	   0x11800809470c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3609"            ,	   0x11800809470c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3610"            ,	   0x11800809470d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3611"            ,	   0x11800809470d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3612"            ,	   0x11800809470e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3613"            ,	   0x11800809470e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3614"            ,	   0x11800809470f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3615"            ,	   0x11800809470f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3616"            ,	   0x1180080947100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3617"            ,	   0x1180080947108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3618"            ,	   0x1180080947110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3619"            ,	   0x1180080947118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3620"            ,	   0x1180080947120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3621"            ,	   0x1180080947128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3622"            ,	   0x1180080947130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3623"            ,	   0x1180080947138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3624"            ,	   0x1180080947140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3625"            ,	   0x1180080947148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3626"            ,	   0x1180080947150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3627"            ,	   0x1180080947158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3628"            ,	   0x1180080947160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3629"            ,	   0x1180080947168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3630"            ,	   0x1180080947170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3631"            ,	   0x1180080947178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3632"            ,	   0x1180080947180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3633"            ,	   0x1180080947188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3634"            ,	   0x1180080947190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3635"            ,	   0x1180080947198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3636"            ,	   0x11800809471a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3637"            ,	   0x11800809471a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3638"            ,	   0x11800809471b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3639"            ,	   0x11800809471b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3640"            ,	   0x11800809471c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3641"            ,	   0x11800809471c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3642"            ,	   0x11800809471d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3643"            ,	   0x11800809471d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3644"            ,	   0x11800809471e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3645"            ,	   0x11800809471e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3646"            ,	   0x11800809471f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3647"            ,	   0x11800809471f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3648"            ,	   0x1180080947200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3649"            ,	   0x1180080947208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3650"            ,	   0x1180080947210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3651"            ,	   0x1180080947218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3652"            ,	   0x1180080947220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3653"            ,	   0x1180080947228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3654"            ,	   0x1180080947230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3655"            ,	   0x1180080947238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3656"            ,	   0x1180080947240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3657"            ,	   0x1180080947248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3658"            ,	   0x1180080947250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3659"            ,	   0x1180080947258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3660"            ,	   0x1180080947260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3661"            ,	   0x1180080947268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3662"            ,	   0x1180080947270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3663"            ,	   0x1180080947278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3664"            ,	   0x1180080947280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3665"            ,	   0x1180080947288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3666"            ,	   0x1180080947290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3667"            ,	   0x1180080947298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3668"            ,	   0x11800809472a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3669"            ,	   0x11800809472a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3670"            ,	   0x11800809472b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3671"            ,	   0x11800809472b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3672"            ,	   0x11800809472c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3673"            ,	   0x11800809472c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3674"            ,	   0x11800809472d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3675"            ,	   0x11800809472d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3676"            ,	   0x11800809472e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3677"            ,	   0x11800809472e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3678"            ,	   0x11800809472f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3679"            ,	   0x11800809472f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3680"            ,	   0x1180080947300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3681"            ,	   0x1180080947308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3682"            ,	   0x1180080947310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3683"            ,	   0x1180080947318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3684"            ,	   0x1180080947320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3685"            ,	   0x1180080947328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3686"            ,	   0x1180080947330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3687"            ,	   0x1180080947338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3688"            ,	   0x1180080947340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3689"            ,	   0x1180080947348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3690"            ,	   0x1180080947350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3691"            ,	   0x1180080947358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3692"            ,	   0x1180080947360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3693"            ,	   0x1180080947368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3694"            ,	   0x1180080947370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3695"            ,	   0x1180080947378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3696"            ,	   0x1180080947380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3697"            ,	   0x1180080947388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3698"            ,	   0x1180080947390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3699"            ,	   0x1180080947398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3700"            ,	   0x11800809473a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3701"            ,	   0x11800809473a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3702"            ,	   0x11800809473b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3703"            ,	   0x11800809473b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3704"            ,	   0x11800809473c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3705"            ,	   0x11800809473c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3706"            ,	   0x11800809473d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3707"            ,	   0x11800809473d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3708"            ,	   0x11800809473e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3709"            ,	   0x11800809473e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3710"            ,	   0x11800809473f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3711"            ,	   0x11800809473f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3712"            ,	   0x1180080947400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3713"            ,	   0x1180080947408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3714"            ,	   0x1180080947410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3715"            ,	   0x1180080947418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3716"            ,	   0x1180080947420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3717"            ,	   0x1180080947428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3718"            ,	   0x1180080947430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3719"            ,	   0x1180080947438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3720"            ,	   0x1180080947440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3721"            ,	   0x1180080947448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3722"            ,	   0x1180080947450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3723"            ,	   0x1180080947458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3724"            ,	   0x1180080947460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3725"            ,	   0x1180080947468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3726"            ,	   0x1180080947470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3727"            ,	   0x1180080947478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3728"            ,	   0x1180080947480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3729"            ,	   0x1180080947488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3730"            ,	   0x1180080947490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3731"            ,	   0x1180080947498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3732"            ,	   0x11800809474a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3733"            ,	   0x11800809474a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3734"            ,	   0x11800809474b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3735"            ,	   0x11800809474b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3736"            ,	   0x11800809474c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3737"            ,	   0x11800809474c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3738"            ,	   0x11800809474d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3739"            ,	   0x11800809474d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3740"            ,	   0x11800809474e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3741"            ,	   0x11800809474e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3742"            ,	   0x11800809474f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3743"            ,	   0x11800809474f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3744"            ,	   0x1180080947500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3745"            ,	   0x1180080947508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3746"            ,	   0x1180080947510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3747"            ,	   0x1180080947518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3748"            ,	   0x1180080947520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3749"            ,	   0x1180080947528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3750"            ,	   0x1180080947530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3751"            ,	   0x1180080947538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3752"            ,	   0x1180080947540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3753"            ,	   0x1180080947548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3754"            ,	   0x1180080947550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3755"            ,	   0x1180080947558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3756"            ,	   0x1180080947560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3757"            ,	   0x1180080947568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3758"            ,	   0x1180080947570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3759"            ,	   0x1180080947578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3760"            ,	   0x1180080947580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3761"            ,	   0x1180080947588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3762"            ,	   0x1180080947590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3763"            ,	   0x1180080947598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3764"            ,	   0x11800809475a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3765"            ,	   0x11800809475a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3766"            ,	   0x11800809475b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3767"            ,	   0x11800809475b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3768"            ,	   0x11800809475c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3769"            ,	   0x11800809475c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3770"            ,	   0x11800809475d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3771"            ,	   0x11800809475d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3772"            ,	   0x11800809475e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3773"            ,	   0x11800809475e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3774"            ,	   0x11800809475f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3775"            ,	   0x11800809475f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3776"            ,	   0x1180080947600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3777"            ,	   0x1180080947608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3778"            ,	   0x1180080947610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3779"            ,	   0x1180080947618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3780"            ,	   0x1180080947620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3781"            ,	   0x1180080947628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3782"            ,	   0x1180080947630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3783"            ,	   0x1180080947638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3784"            ,	   0x1180080947640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3785"            ,	   0x1180080947648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3786"            ,	   0x1180080947650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3787"            ,	   0x1180080947658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3788"            ,	   0x1180080947660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3789"            ,	   0x1180080947668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3790"            ,	   0x1180080947670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3791"            ,	   0x1180080947678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3792"            ,	   0x1180080947680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3793"            ,	   0x1180080947688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3794"            ,	   0x1180080947690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3795"            ,	   0x1180080947698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3796"            ,	   0x11800809476a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3797"            ,	   0x11800809476a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3798"            ,	   0x11800809476b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3799"            ,	   0x11800809476b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3800"            ,	   0x11800809476c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3801"            ,	   0x11800809476c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3802"            ,	   0x11800809476d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3803"            ,	   0x11800809476d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3804"            ,	   0x11800809476e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3805"            ,	   0x11800809476e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3806"            ,	   0x11800809476f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3807"            ,	   0x11800809476f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3808"            ,	   0x1180080947700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3809"            ,	   0x1180080947708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3810"            ,	   0x1180080947710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3811"            ,	   0x1180080947718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3812"            ,	   0x1180080947720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3813"            ,	   0x1180080947728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3814"            ,	   0x1180080947730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3815"            ,	   0x1180080947738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3816"            ,	   0x1180080947740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3817"            ,	   0x1180080947748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3818"            ,	   0x1180080947750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3819"            ,	   0x1180080947758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3820"            ,	   0x1180080947760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3821"            ,	   0x1180080947768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3822"            ,	   0x1180080947770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3823"            ,	   0x1180080947778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3824"            ,	   0x1180080947780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3825"            ,	   0x1180080947788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3826"            ,	   0x1180080947790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3827"            ,	   0x1180080947798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3828"            ,	   0x11800809477a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3829"            ,	   0x11800809477a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3830"            ,	   0x11800809477b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3831"            ,	   0x11800809477b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3832"            ,	   0x11800809477c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3833"            ,	   0x11800809477c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3834"            ,	   0x11800809477d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3835"            ,	   0x11800809477d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3836"            ,	   0x11800809477e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3837"            ,	   0x11800809477e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3838"            ,	   0x11800809477f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3839"            ,	   0x11800809477f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3840"            ,	   0x1180080947800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3841"            ,	   0x1180080947808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3842"            ,	   0x1180080947810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3843"            ,	   0x1180080947818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3844"            ,	   0x1180080947820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3845"            ,	   0x1180080947828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3846"            ,	   0x1180080947830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3847"            ,	   0x1180080947838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3848"            ,	   0x1180080947840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3849"            ,	   0x1180080947848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3850"            ,	   0x1180080947850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3851"            ,	   0x1180080947858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3852"            ,	   0x1180080947860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3853"            ,	   0x1180080947868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3854"            ,	   0x1180080947870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3855"            ,	   0x1180080947878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3856"            ,	   0x1180080947880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3857"            ,	   0x1180080947888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3858"            ,	   0x1180080947890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3859"            ,	   0x1180080947898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3860"            ,	   0x11800809478a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3861"            ,	   0x11800809478a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3862"            ,	   0x11800809478b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3863"            ,	   0x11800809478b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3864"            ,	   0x11800809478c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3865"            ,	   0x11800809478c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3866"            ,	   0x11800809478d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3867"            ,	   0x11800809478d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3868"            ,	   0x11800809478e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3869"            ,	   0x11800809478e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3870"            ,	   0x11800809478f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3871"            ,	   0x11800809478f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3872"            ,	   0x1180080947900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3873"            ,	   0x1180080947908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3874"            ,	   0x1180080947910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3875"            ,	   0x1180080947918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3876"            ,	   0x1180080947920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3877"            ,	   0x1180080947928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3878"            ,	   0x1180080947930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3879"            ,	   0x1180080947938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3880"            ,	   0x1180080947940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3881"            ,	   0x1180080947948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3882"            ,	   0x1180080947950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3883"            ,	   0x1180080947958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3884"            ,	   0x1180080947960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3885"            ,	   0x1180080947968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3886"            ,	   0x1180080947970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3887"            ,	   0x1180080947978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3888"            ,	   0x1180080947980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3889"            ,	   0x1180080947988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3890"            ,	   0x1180080947990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3891"            ,	   0x1180080947998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3892"            ,	   0x11800809479a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3893"            ,	   0x11800809479a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3894"            ,	   0x11800809479b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3895"            ,	   0x11800809479b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3896"            ,	   0x11800809479c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3897"            ,	   0x11800809479c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3898"            ,	   0x11800809479d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3899"            ,	   0x11800809479d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3900"            ,	   0x11800809479e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3901"            ,	   0x11800809479e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3902"            ,	   0x11800809479f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3903"            ,	   0x11800809479f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3904"            ,	   0x1180080947a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3905"            ,	   0x1180080947a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3906"            ,	   0x1180080947a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3907"            ,	   0x1180080947a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3908"            ,	   0x1180080947a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3909"            ,	   0x1180080947a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3910"            ,	   0x1180080947a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3911"            ,	   0x1180080947a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3912"            ,	   0x1180080947a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3913"            ,	   0x1180080947a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3914"            ,	   0x1180080947a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3915"            ,	   0x1180080947a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3916"            ,	   0x1180080947a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3917"            ,	   0x1180080947a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3918"            ,	   0x1180080947a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3919"            ,	   0x1180080947a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3920"            ,	   0x1180080947a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3921"            ,	   0x1180080947a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3922"            ,	   0x1180080947a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3923"            ,	   0x1180080947a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3924"            ,	   0x1180080947aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3925"            ,	   0x1180080947aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3926"            ,	   0x1180080947ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3927"            ,	   0x1180080947ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3928"            ,	   0x1180080947ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3929"            ,	   0x1180080947ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3930"            ,	   0x1180080947ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3931"            ,	   0x1180080947ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3932"            ,	   0x1180080947ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3933"            ,	   0x1180080947ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3934"            ,	   0x1180080947af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3935"            ,	   0x1180080947af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3936"            ,	   0x1180080947b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3937"            ,	   0x1180080947b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3938"            ,	   0x1180080947b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3939"            ,	   0x1180080947b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3940"            ,	   0x1180080947b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3941"            ,	   0x1180080947b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3942"            ,	   0x1180080947b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3943"            ,	   0x1180080947b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3944"            ,	   0x1180080947b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3945"            ,	   0x1180080947b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3946"            ,	   0x1180080947b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3947"            ,	   0x1180080947b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3948"            ,	   0x1180080947b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3949"            ,	   0x1180080947b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3950"            ,	   0x1180080947b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3951"            ,	   0x1180080947b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3952"            ,	   0x1180080947b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3953"            ,	   0x1180080947b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3954"            ,	   0x1180080947b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3955"            ,	   0x1180080947b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3956"            ,	   0x1180080947ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3957"            ,	   0x1180080947ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3958"            ,	   0x1180080947bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3959"            ,	   0x1180080947bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3960"            ,	   0x1180080947bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3961"            ,	   0x1180080947bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3962"            ,	   0x1180080947bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3963"            ,	   0x1180080947bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3964"            ,	   0x1180080947be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3965"            ,	   0x1180080947be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3966"            ,	   0x1180080947bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3967"            ,	   0x1180080947bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3968"            ,	   0x1180080947c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3969"            ,	   0x1180080947c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3970"            ,	   0x1180080947c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3971"            ,	   0x1180080947c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3972"            ,	   0x1180080947c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3973"            ,	   0x1180080947c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3974"            ,	   0x1180080947c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3975"            ,	   0x1180080947c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3976"            ,	   0x1180080947c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3977"            ,	   0x1180080947c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3978"            ,	   0x1180080947c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3979"            ,	   0x1180080947c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3980"            ,	   0x1180080947c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3981"            ,	   0x1180080947c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3982"            ,	   0x1180080947c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3983"            ,	   0x1180080947c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3984"            ,	   0x1180080947c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3985"            ,	   0x1180080947c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3986"            ,	   0x1180080947c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3987"            ,	   0x1180080947c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3988"            ,	   0x1180080947ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3989"            ,	   0x1180080947ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3990"            ,	   0x1180080947cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3991"            ,	   0x1180080947cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3992"            ,	   0x1180080947cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3993"            ,	   0x1180080947cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3994"            ,	   0x1180080947cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3995"            ,	   0x1180080947cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3996"            ,	   0x1180080947ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3997"            ,	   0x1180080947ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3998"            ,	   0x1180080947cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP3999"            ,	   0x1180080947cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4000"            ,	   0x1180080947d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4001"            ,	   0x1180080947d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4002"            ,	   0x1180080947d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4003"            ,	   0x1180080947d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4004"            ,	   0x1180080947d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4005"            ,	   0x1180080947d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4006"            ,	   0x1180080947d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4007"            ,	   0x1180080947d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4008"            ,	   0x1180080947d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4009"            ,	   0x1180080947d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4010"            ,	   0x1180080947d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4011"            ,	   0x1180080947d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4012"            ,	   0x1180080947d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4013"            ,	   0x1180080947d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4014"            ,	   0x1180080947d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4015"            ,	   0x1180080947d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4016"            ,	   0x1180080947d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4017"            ,	   0x1180080947d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4018"            ,	   0x1180080947d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4019"            ,	   0x1180080947d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4020"            ,	   0x1180080947da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4021"            ,	   0x1180080947da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4022"            ,	   0x1180080947db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4023"            ,	   0x1180080947db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4024"            ,	   0x1180080947dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4025"            ,	   0x1180080947dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4026"            ,	   0x1180080947dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4027"            ,	   0x1180080947dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4028"            ,	   0x1180080947de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4029"            ,	   0x1180080947de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4030"            ,	   0x1180080947df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4031"            ,	   0x1180080947df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4032"            ,	   0x1180080947e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4033"            ,	   0x1180080947e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4034"            ,	   0x1180080947e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4035"            ,	   0x1180080947e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4036"            ,	   0x1180080947e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4037"            ,	   0x1180080947e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4038"            ,	   0x1180080947e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4039"            ,	   0x1180080947e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4040"            ,	   0x1180080947e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4041"            ,	   0x1180080947e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4042"            ,	   0x1180080947e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4043"            ,	   0x1180080947e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4044"            ,	   0x1180080947e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4045"            ,	   0x1180080947e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4046"            ,	   0x1180080947e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4047"            ,	   0x1180080947e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4048"            ,	   0x1180080947e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4049"            ,	   0x1180080947e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4050"            ,	   0x1180080947e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4051"            ,	   0x1180080947e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4052"            ,	   0x1180080947ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4053"            ,	   0x1180080947ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4054"            ,	   0x1180080947eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4055"            ,	   0x1180080947eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4056"            ,	   0x1180080947ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4057"            ,	   0x1180080947ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4058"            ,	   0x1180080947ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4059"            ,	   0x1180080947ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4060"            ,	   0x1180080947ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4061"            ,	   0x1180080947ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4062"            ,	   0x1180080947ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4063"            ,	   0x1180080947ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4064"            ,	   0x1180080947f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4065"            ,	   0x1180080947f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4066"            ,	   0x1180080947f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4067"            ,	   0x1180080947f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4068"            ,	   0x1180080947f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4069"            ,	   0x1180080947f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4070"            ,	   0x1180080947f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4071"            ,	   0x1180080947f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4072"            ,	   0x1180080947f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4073"            ,	   0x1180080947f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4074"            ,	   0x1180080947f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4075"            ,	   0x1180080947f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4076"            ,	   0x1180080947f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4077"            ,	   0x1180080947f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4078"            ,	   0x1180080947f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4079"            ,	   0x1180080947f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4080"            ,	   0x1180080947f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4081"            ,	   0x1180080947f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4082"            ,	   0x1180080947f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4083"            ,	   0x1180080947f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4084"            ,	   0x1180080947fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4085"            ,	   0x1180080947fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4086"            ,	   0x1180080947fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4087"            ,	   0x1180080947fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4088"            ,	   0x1180080947fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4089"            ,	   0x1180080947fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4090"            ,	   0x1180080947fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4091"            ,	   0x1180080947fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4092"            ,	   0x1180080947fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4093"            ,	   0x1180080947fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4094"            ,	   0x1180080947ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4095"            ,	   0x1180080947ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4096"            ,	   0x1180080948000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4097"            ,	   0x1180080948008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4098"            ,	   0x1180080948010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4099"            ,	   0x1180080948018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4100"            ,	   0x1180080948020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4101"            ,	   0x1180080948028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4102"            ,	   0x1180080948030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4103"            ,	   0x1180080948038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4104"            ,	   0x1180080948040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4105"            ,	   0x1180080948048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4106"            ,	   0x1180080948050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4107"            ,	   0x1180080948058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4108"            ,	   0x1180080948060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4109"            ,	   0x1180080948068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4110"            ,	   0x1180080948070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4111"            ,	   0x1180080948078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4112"            ,	   0x1180080948080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4113"            ,	   0x1180080948088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4114"            ,	   0x1180080948090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4115"            ,	   0x1180080948098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4116"            ,	   0x11800809480a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4117"            ,	   0x11800809480a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4118"            ,	   0x11800809480b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4119"            ,	   0x11800809480b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4120"            ,	   0x11800809480c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4121"            ,	   0x11800809480c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4122"            ,	   0x11800809480d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4123"            ,	   0x11800809480d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4124"            ,	   0x11800809480e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4125"            ,	   0x11800809480e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4126"            ,	   0x11800809480f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4127"            ,	   0x11800809480f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4128"            ,	   0x1180080948100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4129"            ,	   0x1180080948108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4130"            ,	   0x1180080948110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4131"            ,	   0x1180080948118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4132"            ,	   0x1180080948120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4133"            ,	   0x1180080948128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4134"            ,	   0x1180080948130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4135"            ,	   0x1180080948138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4136"            ,	   0x1180080948140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4137"            ,	   0x1180080948148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4138"            ,	   0x1180080948150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4139"            ,	   0x1180080948158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4140"            ,	   0x1180080948160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4141"            ,	   0x1180080948168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4142"            ,	   0x1180080948170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4143"            ,	   0x1180080948178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4144"            ,	   0x1180080948180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4145"            ,	   0x1180080948188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4146"            ,	   0x1180080948190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4147"            ,	   0x1180080948198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4148"            ,	   0x11800809481a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4149"            ,	   0x11800809481a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4150"            ,	   0x11800809481b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4151"            ,	   0x11800809481b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4152"            ,	   0x11800809481c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4153"            ,	   0x11800809481c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4154"            ,	   0x11800809481d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4155"            ,	   0x11800809481d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4156"            ,	   0x11800809481e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4157"            ,	   0x11800809481e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4158"            ,	   0x11800809481f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4159"            ,	   0x11800809481f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4160"            ,	   0x1180080948200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4161"            ,	   0x1180080948208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4162"            ,	   0x1180080948210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4163"            ,	   0x1180080948218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4164"            ,	   0x1180080948220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4165"            ,	   0x1180080948228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4166"            ,	   0x1180080948230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4167"            ,	   0x1180080948238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4168"            ,	   0x1180080948240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4169"            ,	   0x1180080948248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4170"            ,	   0x1180080948250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4171"            ,	   0x1180080948258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4172"            ,	   0x1180080948260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4173"            ,	   0x1180080948268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4174"            ,	   0x1180080948270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4175"            ,	   0x1180080948278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4176"            ,	   0x1180080948280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4177"            ,	   0x1180080948288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4178"            ,	   0x1180080948290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4179"            ,	   0x1180080948298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4180"            ,	   0x11800809482a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4181"            ,	   0x11800809482a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4182"            ,	   0x11800809482b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4183"            ,	   0x11800809482b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4184"            ,	   0x11800809482c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4185"            ,	   0x11800809482c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4186"            ,	   0x11800809482d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4187"            ,	   0x11800809482d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4188"            ,	   0x11800809482e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4189"            ,	   0x11800809482e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4190"            ,	   0x11800809482f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4191"            ,	   0x11800809482f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4192"            ,	   0x1180080948300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4193"            ,	   0x1180080948308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4194"            ,	   0x1180080948310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4195"            ,	   0x1180080948318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4196"            ,	   0x1180080948320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4197"            ,	   0x1180080948328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4198"            ,	   0x1180080948330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4199"            ,	   0x1180080948338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4200"            ,	   0x1180080948340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4201"            ,	   0x1180080948348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4202"            ,	   0x1180080948350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4203"            ,	   0x1180080948358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4204"            ,	   0x1180080948360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4205"            ,	   0x1180080948368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4206"            ,	   0x1180080948370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4207"            ,	   0x1180080948378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4208"            ,	   0x1180080948380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4209"            ,	   0x1180080948388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4210"            ,	   0x1180080948390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4211"            ,	   0x1180080948398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4212"            ,	   0x11800809483a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4213"            ,	   0x11800809483a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4214"            ,	   0x11800809483b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4215"            ,	   0x11800809483b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4216"            ,	   0x11800809483c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4217"            ,	   0x11800809483c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4218"            ,	   0x11800809483d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4219"            ,	   0x11800809483d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4220"            ,	   0x11800809483e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4221"            ,	   0x11800809483e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4222"            ,	   0x11800809483f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4223"            ,	   0x11800809483f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4224"            ,	   0x1180080948400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4225"            ,	   0x1180080948408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4226"            ,	   0x1180080948410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4227"            ,	   0x1180080948418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4228"            ,	   0x1180080948420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4229"            ,	   0x1180080948428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4230"            ,	   0x1180080948430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4231"            ,	   0x1180080948438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4232"            ,	   0x1180080948440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4233"            ,	   0x1180080948448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4234"            ,	   0x1180080948450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4235"            ,	   0x1180080948458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4236"            ,	   0x1180080948460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4237"            ,	   0x1180080948468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4238"            ,	   0x1180080948470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4239"            ,	   0x1180080948478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4240"            ,	   0x1180080948480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4241"            ,	   0x1180080948488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4242"            ,	   0x1180080948490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4243"            ,	   0x1180080948498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4244"            ,	   0x11800809484a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4245"            ,	   0x11800809484a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4246"            ,	   0x11800809484b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4247"            ,	   0x11800809484b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4248"            ,	   0x11800809484c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4249"            ,	   0x11800809484c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4250"            ,	   0x11800809484d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4251"            ,	   0x11800809484d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4252"            ,	   0x11800809484e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4253"            ,	   0x11800809484e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4254"            ,	   0x11800809484f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4255"            ,	   0x11800809484f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4256"            ,	   0x1180080948500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4257"            ,	   0x1180080948508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4258"            ,	   0x1180080948510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4259"            ,	   0x1180080948518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4260"            ,	   0x1180080948520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4261"            ,	   0x1180080948528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4262"            ,	   0x1180080948530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4263"            ,	   0x1180080948538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4264"            ,	   0x1180080948540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4265"            ,	   0x1180080948548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4266"            ,	   0x1180080948550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4267"            ,	   0x1180080948558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4268"            ,	   0x1180080948560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4269"            ,	   0x1180080948568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4270"            ,	   0x1180080948570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4271"            ,	   0x1180080948578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4272"            ,	   0x1180080948580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4273"            ,	   0x1180080948588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4274"            ,	   0x1180080948590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4275"            ,	   0x1180080948598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4276"            ,	   0x11800809485a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4277"            ,	   0x11800809485a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4278"            ,	   0x11800809485b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4279"            ,	   0x11800809485b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4280"            ,	   0x11800809485c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4281"            ,	   0x11800809485c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4282"            ,	   0x11800809485d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4283"            ,	   0x11800809485d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4284"            ,	   0x11800809485e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4285"            ,	   0x11800809485e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4286"            ,	   0x11800809485f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4287"            ,	   0x11800809485f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4288"            ,	   0x1180080948600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4289"            ,	   0x1180080948608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4290"            ,	   0x1180080948610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4291"            ,	   0x1180080948618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4292"            ,	   0x1180080948620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4293"            ,	   0x1180080948628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4294"            ,	   0x1180080948630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4295"            ,	   0x1180080948638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4296"            ,	   0x1180080948640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4297"            ,	   0x1180080948648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4298"            ,	   0x1180080948650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4299"            ,	   0x1180080948658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4300"            ,	   0x1180080948660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4301"            ,	   0x1180080948668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4302"            ,	   0x1180080948670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4303"            ,	   0x1180080948678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4304"            ,	   0x1180080948680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4305"            ,	   0x1180080948688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4306"            ,	   0x1180080948690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4307"            ,	   0x1180080948698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4308"            ,	   0x11800809486a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4309"            ,	   0x11800809486a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4310"            ,	   0x11800809486b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4311"            ,	   0x11800809486b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4312"            ,	   0x11800809486c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4313"            ,	   0x11800809486c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4314"            ,	   0x11800809486d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4315"            ,	   0x11800809486d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4316"            ,	   0x11800809486e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4317"            ,	   0x11800809486e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4318"            ,	   0x11800809486f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4319"            ,	   0x11800809486f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4320"            ,	   0x1180080948700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4321"            ,	   0x1180080948708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4322"            ,	   0x1180080948710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4323"            ,	   0x1180080948718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4324"            ,	   0x1180080948720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4325"            ,	   0x1180080948728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4326"            ,	   0x1180080948730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4327"            ,	   0x1180080948738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4328"            ,	   0x1180080948740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4329"            ,	   0x1180080948748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4330"            ,	   0x1180080948750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4331"            ,	   0x1180080948758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4332"            ,	   0x1180080948760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4333"            ,	   0x1180080948768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4334"            ,	   0x1180080948770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4335"            ,	   0x1180080948778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4336"            ,	   0x1180080948780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4337"            ,	   0x1180080948788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4338"            ,	   0x1180080948790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4339"            ,	   0x1180080948798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4340"            ,	   0x11800809487a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4341"            ,	   0x11800809487a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4342"            ,	   0x11800809487b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4343"            ,	   0x11800809487b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4344"            ,	   0x11800809487c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4345"            ,	   0x11800809487c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4346"            ,	   0x11800809487d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4347"            ,	   0x11800809487d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4348"            ,	   0x11800809487e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4349"            ,	   0x11800809487e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4350"            ,	   0x11800809487f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4351"            ,	   0x11800809487f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4352"            ,	   0x1180080948800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4353"            ,	   0x1180080948808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4354"            ,	   0x1180080948810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4355"            ,	   0x1180080948818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4356"            ,	   0x1180080948820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4357"            ,	   0x1180080948828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4358"            ,	   0x1180080948830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4359"            ,	   0x1180080948838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4360"            ,	   0x1180080948840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4361"            ,	   0x1180080948848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4362"            ,	   0x1180080948850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4363"            ,	   0x1180080948858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4364"            ,	   0x1180080948860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4365"            ,	   0x1180080948868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4366"            ,	   0x1180080948870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4367"            ,	   0x1180080948878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4368"            ,	   0x1180080948880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4369"            ,	   0x1180080948888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4370"            ,	   0x1180080948890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4371"            ,	   0x1180080948898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4372"            ,	   0x11800809488a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4373"            ,	   0x11800809488a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4374"            ,	   0x11800809488b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4375"            ,	   0x11800809488b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4376"            ,	   0x11800809488c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4377"            ,	   0x11800809488c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4378"            ,	   0x11800809488d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4379"            ,	   0x11800809488d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4380"            ,	   0x11800809488e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4381"            ,	   0x11800809488e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4382"            ,	   0x11800809488f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4383"            ,	   0x11800809488f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4384"            ,	   0x1180080948900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4385"            ,	   0x1180080948908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4386"            ,	   0x1180080948910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4387"            ,	   0x1180080948918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4388"            ,	   0x1180080948920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4389"            ,	   0x1180080948928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4390"            ,	   0x1180080948930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4391"            ,	   0x1180080948938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4392"            ,	   0x1180080948940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4393"            ,	   0x1180080948948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4394"            ,	   0x1180080948950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4395"            ,	   0x1180080948958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4396"            ,	   0x1180080948960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4397"            ,	   0x1180080948968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4398"            ,	   0x1180080948970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4399"            ,	   0x1180080948978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4400"            ,	   0x1180080948980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4401"            ,	   0x1180080948988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4402"            ,	   0x1180080948990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4403"            ,	   0x1180080948998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4404"            ,	   0x11800809489a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4405"            ,	   0x11800809489a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4406"            ,	   0x11800809489b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4407"            ,	   0x11800809489b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4408"            ,	   0x11800809489c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4409"            ,	   0x11800809489c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4410"            ,	   0x11800809489d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4411"            ,	   0x11800809489d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4412"            ,	   0x11800809489e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4413"            ,	   0x11800809489e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4414"            ,	   0x11800809489f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4415"            ,	   0x11800809489f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4416"            ,	   0x1180080948a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4417"            ,	   0x1180080948a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4418"            ,	   0x1180080948a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4419"            ,	   0x1180080948a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4420"            ,	   0x1180080948a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4421"            ,	   0x1180080948a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4422"            ,	   0x1180080948a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4423"            ,	   0x1180080948a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4424"            ,	   0x1180080948a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4425"            ,	   0x1180080948a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4426"            ,	   0x1180080948a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4427"            ,	   0x1180080948a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4428"            ,	   0x1180080948a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4429"            ,	   0x1180080948a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4430"            ,	   0x1180080948a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4431"            ,	   0x1180080948a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4432"            ,	   0x1180080948a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4433"            ,	   0x1180080948a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4434"            ,	   0x1180080948a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4435"            ,	   0x1180080948a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4436"            ,	   0x1180080948aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4437"            ,	   0x1180080948aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4438"            ,	   0x1180080948ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4439"            ,	   0x1180080948ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4440"            ,	   0x1180080948ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4441"            ,	   0x1180080948ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4442"            ,	   0x1180080948ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4443"            ,	   0x1180080948ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4444"            ,	   0x1180080948ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4445"            ,	   0x1180080948ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4446"            ,	   0x1180080948af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4447"            ,	   0x1180080948af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4448"            ,	   0x1180080948b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4449"            ,	   0x1180080948b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4450"            ,	   0x1180080948b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4451"            ,	   0x1180080948b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4452"            ,	   0x1180080948b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4453"            ,	   0x1180080948b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4454"            ,	   0x1180080948b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4455"            ,	   0x1180080948b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4456"            ,	   0x1180080948b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4457"            ,	   0x1180080948b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4458"            ,	   0x1180080948b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4459"            ,	   0x1180080948b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4460"            ,	   0x1180080948b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4461"            ,	   0x1180080948b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4462"            ,	   0x1180080948b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4463"            ,	   0x1180080948b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4464"            ,	   0x1180080948b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4465"            ,	   0x1180080948b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4466"            ,	   0x1180080948b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4467"            ,	   0x1180080948b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4468"            ,	   0x1180080948ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4469"            ,	   0x1180080948ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4470"            ,	   0x1180080948bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4471"            ,	   0x1180080948bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4472"            ,	   0x1180080948bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4473"            ,	   0x1180080948bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4474"            ,	   0x1180080948bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4475"            ,	   0x1180080948bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4476"            ,	   0x1180080948be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4477"            ,	   0x1180080948be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4478"            ,	   0x1180080948bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4479"            ,	   0x1180080948bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4480"            ,	   0x1180080948c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4481"            ,	   0x1180080948c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4482"            ,	   0x1180080948c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4483"            ,	   0x1180080948c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4484"            ,	   0x1180080948c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4485"            ,	   0x1180080948c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4486"            ,	   0x1180080948c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4487"            ,	   0x1180080948c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4488"            ,	   0x1180080948c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4489"            ,	   0x1180080948c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4490"            ,	   0x1180080948c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4491"            ,	   0x1180080948c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4492"            ,	   0x1180080948c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4493"            ,	   0x1180080948c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4494"            ,	   0x1180080948c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4495"            ,	   0x1180080948c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4496"            ,	   0x1180080948c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4497"            ,	   0x1180080948c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4498"            ,	   0x1180080948c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4499"            ,	   0x1180080948c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4500"            ,	   0x1180080948ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4501"            ,	   0x1180080948ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4502"            ,	   0x1180080948cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4503"            ,	   0x1180080948cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4504"            ,	   0x1180080948cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4505"            ,	   0x1180080948cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4506"            ,	   0x1180080948cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4507"            ,	   0x1180080948cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4508"            ,	   0x1180080948ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4509"            ,	   0x1180080948ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4510"            ,	   0x1180080948cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4511"            ,	   0x1180080948cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4512"            ,	   0x1180080948d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4513"            ,	   0x1180080948d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4514"            ,	   0x1180080948d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4515"            ,	   0x1180080948d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4516"            ,	   0x1180080948d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4517"            ,	   0x1180080948d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4518"            ,	   0x1180080948d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4519"            ,	   0x1180080948d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4520"            ,	   0x1180080948d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4521"            ,	   0x1180080948d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4522"            ,	   0x1180080948d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4523"            ,	   0x1180080948d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4524"            ,	   0x1180080948d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4525"            ,	   0x1180080948d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4526"            ,	   0x1180080948d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4527"            ,	   0x1180080948d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4528"            ,	   0x1180080948d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4529"            ,	   0x1180080948d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4530"            ,	   0x1180080948d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4531"            ,	   0x1180080948d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4532"            ,	   0x1180080948da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4533"            ,	   0x1180080948da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4534"            ,	   0x1180080948db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4535"            ,	   0x1180080948db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4536"            ,	   0x1180080948dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4537"            ,	   0x1180080948dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4538"            ,	   0x1180080948dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4539"            ,	   0x1180080948dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4540"            ,	   0x1180080948de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4541"            ,	   0x1180080948de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4542"            ,	   0x1180080948df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4543"            ,	   0x1180080948df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4544"            ,	   0x1180080948e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4545"            ,	   0x1180080948e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4546"            ,	   0x1180080948e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4547"            ,	   0x1180080948e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4548"            ,	   0x1180080948e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4549"            ,	   0x1180080948e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4550"            ,	   0x1180080948e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4551"            ,	   0x1180080948e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4552"            ,	   0x1180080948e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4553"            ,	   0x1180080948e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4554"            ,	   0x1180080948e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4555"            ,	   0x1180080948e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4556"            ,	   0x1180080948e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4557"            ,	   0x1180080948e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4558"            ,	   0x1180080948e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4559"            ,	   0x1180080948e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4560"            ,	   0x1180080948e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4561"            ,	   0x1180080948e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4562"            ,	   0x1180080948e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4563"            ,	   0x1180080948e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4564"            ,	   0x1180080948ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4565"            ,	   0x1180080948ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4566"            ,	   0x1180080948eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4567"            ,	   0x1180080948eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4568"            ,	   0x1180080948ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4569"            ,	   0x1180080948ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4570"            ,	   0x1180080948ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4571"            ,	   0x1180080948ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4572"            ,	   0x1180080948ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4573"            ,	   0x1180080948ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4574"            ,	   0x1180080948ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4575"            ,	   0x1180080948ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4576"            ,	   0x1180080948f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4577"            ,	   0x1180080948f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4578"            ,	   0x1180080948f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4579"            ,	   0x1180080948f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4580"            ,	   0x1180080948f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4581"            ,	   0x1180080948f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4582"            ,	   0x1180080948f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4583"            ,	   0x1180080948f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4584"            ,	   0x1180080948f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4585"            ,	   0x1180080948f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4586"            ,	   0x1180080948f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4587"            ,	   0x1180080948f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4588"            ,	   0x1180080948f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4589"            ,	   0x1180080948f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4590"            ,	   0x1180080948f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4591"            ,	   0x1180080948f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4592"            ,	   0x1180080948f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4593"            ,	   0x1180080948f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4594"            ,	   0x1180080948f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4595"            ,	   0x1180080948f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4596"            ,	   0x1180080948fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4597"            ,	   0x1180080948fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4598"            ,	   0x1180080948fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4599"            ,	   0x1180080948fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4600"            ,	   0x1180080948fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4601"            ,	   0x1180080948fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4602"            ,	   0x1180080948fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4603"            ,	   0x1180080948fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4604"            ,	   0x1180080948fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4605"            ,	   0x1180080948fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4606"            ,	   0x1180080948ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4607"            ,	   0x1180080948ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4608"            ,	   0x1180080949000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4609"            ,	   0x1180080949008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4610"            ,	   0x1180080949010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4611"            ,	   0x1180080949018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4612"            ,	   0x1180080949020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4613"            ,	   0x1180080949028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4614"            ,	   0x1180080949030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4615"            ,	   0x1180080949038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4616"            ,	   0x1180080949040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4617"            ,	   0x1180080949048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4618"            ,	   0x1180080949050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4619"            ,	   0x1180080949058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4620"            ,	   0x1180080949060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4621"            ,	   0x1180080949068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4622"            ,	   0x1180080949070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4623"            ,	   0x1180080949078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4624"            ,	   0x1180080949080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4625"            ,	   0x1180080949088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4626"            ,	   0x1180080949090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4627"            ,	   0x1180080949098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4628"            ,	   0x11800809490a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4629"            ,	   0x11800809490a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4630"            ,	   0x11800809490b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4631"            ,	   0x11800809490b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4632"            ,	   0x11800809490c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4633"            ,	   0x11800809490c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4634"            ,	   0x11800809490d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4635"            ,	   0x11800809490d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4636"            ,	   0x11800809490e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4637"            ,	   0x11800809490e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4638"            ,	   0x11800809490f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4639"            ,	   0x11800809490f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4640"            ,	   0x1180080949100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4641"            ,	   0x1180080949108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4642"            ,	   0x1180080949110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4643"            ,	   0x1180080949118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4644"            ,	   0x1180080949120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4645"            ,	   0x1180080949128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4646"            ,	   0x1180080949130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4647"            ,	   0x1180080949138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4648"            ,	   0x1180080949140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4649"            ,	   0x1180080949148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4650"            ,	   0x1180080949150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4651"            ,	   0x1180080949158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4652"            ,	   0x1180080949160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4653"            ,	   0x1180080949168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4654"            ,	   0x1180080949170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4655"            ,	   0x1180080949178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4656"            ,	   0x1180080949180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4657"            ,	   0x1180080949188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4658"            ,	   0x1180080949190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4659"            ,	   0x1180080949198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4660"            ,	   0x11800809491a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4661"            ,	   0x11800809491a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4662"            ,	   0x11800809491b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4663"            ,	   0x11800809491b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4664"            ,	   0x11800809491c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4665"            ,	   0x11800809491c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4666"            ,	   0x11800809491d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4667"            ,	   0x11800809491d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4668"            ,	   0x11800809491e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4669"            ,	   0x11800809491e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4670"            ,	   0x11800809491f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4671"            ,	   0x11800809491f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4672"            ,	   0x1180080949200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4673"            ,	   0x1180080949208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4674"            ,	   0x1180080949210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4675"            ,	   0x1180080949218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4676"            ,	   0x1180080949220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4677"            ,	   0x1180080949228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4678"            ,	   0x1180080949230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4679"            ,	   0x1180080949238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4680"            ,	   0x1180080949240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4681"            ,	   0x1180080949248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4682"            ,	   0x1180080949250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4683"            ,	   0x1180080949258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4684"            ,	   0x1180080949260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4685"            ,	   0x1180080949268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4686"            ,	   0x1180080949270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4687"            ,	   0x1180080949278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4688"            ,	   0x1180080949280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4689"            ,	   0x1180080949288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4690"            ,	   0x1180080949290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4691"            ,	   0x1180080949298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4692"            ,	   0x11800809492a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4693"            ,	   0x11800809492a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4694"            ,	   0x11800809492b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4695"            ,	   0x11800809492b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4696"            ,	   0x11800809492c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4697"            ,	   0x11800809492c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4698"            ,	   0x11800809492d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4699"            ,	   0x11800809492d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4700"            ,	   0x11800809492e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4701"            ,	   0x11800809492e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4702"            ,	   0x11800809492f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4703"            ,	   0x11800809492f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4704"            ,	   0x1180080949300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4705"            ,	   0x1180080949308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4706"            ,	   0x1180080949310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4707"            ,	   0x1180080949318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4708"            ,	   0x1180080949320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4709"            ,	   0x1180080949328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4710"            ,	   0x1180080949330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4711"            ,	   0x1180080949338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4712"            ,	   0x1180080949340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4713"            ,	   0x1180080949348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4714"            ,	   0x1180080949350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4715"            ,	   0x1180080949358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4716"            ,	   0x1180080949360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4717"            ,	   0x1180080949368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4718"            ,	   0x1180080949370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4719"            ,	   0x1180080949378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4720"            ,	   0x1180080949380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4721"            ,	   0x1180080949388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4722"            ,	   0x1180080949390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4723"            ,	   0x1180080949398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4724"            ,	   0x11800809493a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4725"            ,	   0x11800809493a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4726"            ,	   0x11800809493b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4727"            ,	   0x11800809493b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4728"            ,	   0x11800809493c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4729"            ,	   0x11800809493c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4730"            ,	   0x11800809493d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4731"            ,	   0x11800809493d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4732"            ,	   0x11800809493e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4733"            ,	   0x11800809493e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4734"            ,	   0x11800809493f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4735"            ,	   0x11800809493f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4736"            ,	   0x1180080949400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4737"            ,	   0x1180080949408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4738"            ,	   0x1180080949410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4739"            ,	   0x1180080949418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4740"            ,	   0x1180080949420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4741"            ,	   0x1180080949428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4742"            ,	   0x1180080949430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4743"            ,	   0x1180080949438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4744"            ,	   0x1180080949440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4745"            ,	   0x1180080949448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4746"            ,	   0x1180080949450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4747"            ,	   0x1180080949458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4748"            ,	   0x1180080949460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4749"            ,	   0x1180080949468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4750"            ,	   0x1180080949470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4751"            ,	   0x1180080949478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4752"            ,	   0x1180080949480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4753"            ,	   0x1180080949488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4754"            ,	   0x1180080949490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4755"            ,	   0x1180080949498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4756"            ,	   0x11800809494a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4757"            ,	   0x11800809494a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4758"            ,	   0x11800809494b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4759"            ,	   0x11800809494b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4760"            ,	   0x11800809494c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4761"            ,	   0x11800809494c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4762"            ,	   0x11800809494d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4763"            ,	   0x11800809494d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4764"            ,	   0x11800809494e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4765"            ,	   0x11800809494e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4766"            ,	   0x11800809494f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4767"            ,	   0x11800809494f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4768"            ,	   0x1180080949500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4769"            ,	   0x1180080949508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4770"            ,	   0x1180080949510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4771"            ,	   0x1180080949518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4772"            ,	   0x1180080949520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4773"            ,	   0x1180080949528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4774"            ,	   0x1180080949530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4775"            ,	   0x1180080949538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4776"            ,	   0x1180080949540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4777"            ,	   0x1180080949548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4778"            ,	   0x1180080949550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4779"            ,	   0x1180080949558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4780"            ,	   0x1180080949560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4781"            ,	   0x1180080949568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4782"            ,	   0x1180080949570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4783"            ,	   0x1180080949578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4784"            ,	   0x1180080949580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4785"            ,	   0x1180080949588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4786"            ,	   0x1180080949590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4787"            ,	   0x1180080949598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4788"            ,	   0x11800809495a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4789"            ,	   0x11800809495a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4790"            ,	   0x11800809495b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4791"            ,	   0x11800809495b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4792"            ,	   0x11800809495c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4793"            ,	   0x11800809495c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4794"            ,	   0x11800809495d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4795"            ,	   0x11800809495d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4796"            ,	   0x11800809495e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4797"            ,	   0x11800809495e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4798"            ,	   0x11800809495f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4799"            ,	   0x11800809495f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4800"            ,	   0x1180080949600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4801"            ,	   0x1180080949608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4802"            ,	   0x1180080949610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4803"            ,	   0x1180080949618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4804"            ,	   0x1180080949620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4805"            ,	   0x1180080949628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4806"            ,	   0x1180080949630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4807"            ,	   0x1180080949638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4808"            ,	   0x1180080949640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4809"            ,	   0x1180080949648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4810"            ,	   0x1180080949650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4811"            ,	   0x1180080949658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4812"            ,	   0x1180080949660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4813"            ,	   0x1180080949668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4814"            ,	   0x1180080949670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4815"            ,	   0x1180080949678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4816"            ,	   0x1180080949680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4817"            ,	   0x1180080949688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4818"            ,	   0x1180080949690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4819"            ,	   0x1180080949698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4820"            ,	   0x11800809496a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4821"            ,	   0x11800809496a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4822"            ,	   0x11800809496b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4823"            ,	   0x11800809496b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4824"            ,	   0x11800809496c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4825"            ,	   0x11800809496c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4826"            ,	   0x11800809496d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4827"            ,	   0x11800809496d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4828"            ,	   0x11800809496e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4829"            ,	   0x11800809496e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4830"            ,	   0x11800809496f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4831"            ,	   0x11800809496f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4832"            ,	   0x1180080949700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4833"            ,	   0x1180080949708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4834"            ,	   0x1180080949710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4835"            ,	   0x1180080949718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4836"            ,	   0x1180080949720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4837"            ,	   0x1180080949728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4838"            ,	   0x1180080949730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4839"            ,	   0x1180080949738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4840"            ,	   0x1180080949740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4841"            ,	   0x1180080949748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4842"            ,	   0x1180080949750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4843"            ,	   0x1180080949758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4844"            ,	   0x1180080949760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4845"            ,	   0x1180080949768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4846"            ,	   0x1180080949770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4847"            ,	   0x1180080949778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4848"            ,	   0x1180080949780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4849"            ,	   0x1180080949788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4850"            ,	   0x1180080949790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4851"            ,	   0x1180080949798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4852"            ,	   0x11800809497a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4853"            ,	   0x11800809497a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4854"            ,	   0x11800809497b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4855"            ,	   0x11800809497b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4856"            ,	   0x11800809497c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4857"            ,	   0x11800809497c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4858"            ,	   0x11800809497d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4859"            ,	   0x11800809497d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4860"            ,	   0x11800809497e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4861"            ,	   0x11800809497e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4862"            ,	   0x11800809497f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4863"            ,	   0x11800809497f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4864"            ,	   0x1180080949800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4865"            ,	   0x1180080949808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4866"            ,	   0x1180080949810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4867"            ,	   0x1180080949818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4868"            ,	   0x1180080949820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4869"            ,	   0x1180080949828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4870"            ,	   0x1180080949830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4871"            ,	   0x1180080949838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4872"            ,	   0x1180080949840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4873"            ,	   0x1180080949848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4874"            ,	   0x1180080949850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4875"            ,	   0x1180080949858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4876"            ,	   0x1180080949860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4877"            ,	   0x1180080949868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4878"            ,	   0x1180080949870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4879"            ,	   0x1180080949878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4880"            ,	   0x1180080949880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4881"            ,	   0x1180080949888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4882"            ,	   0x1180080949890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4883"            ,	   0x1180080949898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4884"            ,	   0x11800809498a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4885"            ,	   0x11800809498a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4886"            ,	   0x11800809498b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4887"            ,	   0x11800809498b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4888"            ,	   0x11800809498c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4889"            ,	   0x11800809498c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4890"            ,	   0x11800809498d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4891"            ,	   0x11800809498d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4892"            ,	   0x11800809498e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4893"            ,	   0x11800809498e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4894"            ,	   0x11800809498f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4895"            ,	   0x11800809498f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4896"            ,	   0x1180080949900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4897"            ,	   0x1180080949908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4898"            ,	   0x1180080949910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4899"            ,	   0x1180080949918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4900"            ,	   0x1180080949920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4901"            ,	   0x1180080949928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4902"            ,	   0x1180080949930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4903"            ,	   0x1180080949938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4904"            ,	   0x1180080949940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4905"            ,	   0x1180080949948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4906"            ,	   0x1180080949950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4907"            ,	   0x1180080949958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4908"            ,	   0x1180080949960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4909"            ,	   0x1180080949968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4910"            ,	   0x1180080949970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4911"            ,	   0x1180080949978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4912"            ,	   0x1180080949980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4913"            ,	   0x1180080949988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4914"            ,	   0x1180080949990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4915"            ,	   0x1180080949998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4916"            ,	   0x11800809499a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4917"            ,	   0x11800809499a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4918"            ,	   0x11800809499b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4919"            ,	   0x11800809499b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4920"            ,	   0x11800809499c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4921"            ,	   0x11800809499c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4922"            ,	   0x11800809499d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4923"            ,	   0x11800809499d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4924"            ,	   0x11800809499e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4925"            ,	   0x11800809499e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4926"            ,	   0x11800809499f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4927"            ,	   0x11800809499f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4928"            ,	   0x1180080949a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4929"            ,	   0x1180080949a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4930"            ,	   0x1180080949a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4931"            ,	   0x1180080949a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4932"            ,	   0x1180080949a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4933"            ,	   0x1180080949a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4934"            ,	   0x1180080949a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4935"            ,	   0x1180080949a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4936"            ,	   0x1180080949a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4937"            ,	   0x1180080949a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4938"            ,	   0x1180080949a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4939"            ,	   0x1180080949a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4940"            ,	   0x1180080949a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4941"            ,	   0x1180080949a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4942"            ,	   0x1180080949a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4943"            ,	   0x1180080949a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4944"            ,	   0x1180080949a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4945"            ,	   0x1180080949a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4946"            ,	   0x1180080949a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4947"            ,	   0x1180080949a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4948"            ,	   0x1180080949aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4949"            ,	   0x1180080949aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4950"            ,	   0x1180080949ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4951"            ,	   0x1180080949ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4952"            ,	   0x1180080949ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4953"            ,	   0x1180080949ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4954"            ,	   0x1180080949ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4955"            ,	   0x1180080949ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4956"            ,	   0x1180080949ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4957"            ,	   0x1180080949ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4958"            ,	   0x1180080949af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4959"            ,	   0x1180080949af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4960"            ,	   0x1180080949b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4961"            ,	   0x1180080949b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4962"            ,	   0x1180080949b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4963"            ,	   0x1180080949b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4964"            ,	   0x1180080949b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4965"            ,	   0x1180080949b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4966"            ,	   0x1180080949b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4967"            ,	   0x1180080949b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4968"            ,	   0x1180080949b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4969"            ,	   0x1180080949b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4970"            ,	   0x1180080949b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4971"            ,	   0x1180080949b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4972"            ,	   0x1180080949b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4973"            ,	   0x1180080949b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4974"            ,	   0x1180080949b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4975"            ,	   0x1180080949b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4976"            ,	   0x1180080949b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4977"            ,	   0x1180080949b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4978"            ,	   0x1180080949b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4979"            ,	   0x1180080949b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4980"            ,	   0x1180080949ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4981"            ,	   0x1180080949ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4982"            ,	   0x1180080949bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4983"            ,	   0x1180080949bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4984"            ,	   0x1180080949bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4985"            ,	   0x1180080949bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4986"            ,	   0x1180080949bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4987"            ,	   0x1180080949bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4988"            ,	   0x1180080949be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4989"            ,	   0x1180080949be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4990"            ,	   0x1180080949bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4991"            ,	   0x1180080949bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4992"            ,	   0x1180080949c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4993"            ,	   0x1180080949c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4994"            ,	   0x1180080949c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4995"            ,	   0x1180080949c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4996"            ,	   0x1180080949c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4997"            ,	   0x1180080949c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4998"            ,	   0x1180080949c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP4999"            ,	   0x1180080949c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5000"            ,	   0x1180080949c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5001"            ,	   0x1180080949c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5002"            ,	   0x1180080949c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5003"            ,	   0x1180080949c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5004"            ,	   0x1180080949c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5005"            ,	   0x1180080949c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5006"            ,	   0x1180080949c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5007"            ,	   0x1180080949c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5008"            ,	   0x1180080949c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5009"            ,	   0x1180080949c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5010"            ,	   0x1180080949c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5011"            ,	   0x1180080949c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5012"            ,	   0x1180080949ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5013"            ,	   0x1180080949ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5014"            ,	   0x1180080949cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5015"            ,	   0x1180080949cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5016"            ,	   0x1180080949cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5017"            ,	   0x1180080949cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5018"            ,	   0x1180080949cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5019"            ,	   0x1180080949cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5020"            ,	   0x1180080949ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5021"            ,	   0x1180080949ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5022"            ,	   0x1180080949cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5023"            ,	   0x1180080949cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5024"            ,	   0x1180080949d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5025"            ,	   0x1180080949d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5026"            ,	   0x1180080949d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5027"            ,	   0x1180080949d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5028"            ,	   0x1180080949d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5029"            ,	   0x1180080949d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5030"            ,	   0x1180080949d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5031"            ,	   0x1180080949d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5032"            ,	   0x1180080949d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5033"            ,	   0x1180080949d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5034"            ,	   0x1180080949d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5035"            ,	   0x1180080949d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5036"            ,	   0x1180080949d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5037"            ,	   0x1180080949d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5038"            ,	   0x1180080949d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5039"            ,	   0x1180080949d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5040"            ,	   0x1180080949d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5041"            ,	   0x1180080949d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5042"            ,	   0x1180080949d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5043"            ,	   0x1180080949d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5044"            ,	   0x1180080949da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5045"            ,	   0x1180080949da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5046"            ,	   0x1180080949db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5047"            ,	   0x1180080949db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5048"            ,	   0x1180080949dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5049"            ,	   0x1180080949dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5050"            ,	   0x1180080949dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5051"            ,	   0x1180080949dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5052"            ,	   0x1180080949de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5053"            ,	   0x1180080949de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5054"            ,	   0x1180080949df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5055"            ,	   0x1180080949df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5056"            ,	   0x1180080949e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5057"            ,	   0x1180080949e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5058"            ,	   0x1180080949e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5059"            ,	   0x1180080949e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5060"            ,	   0x1180080949e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5061"            ,	   0x1180080949e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5062"            ,	   0x1180080949e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5063"            ,	   0x1180080949e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5064"            ,	   0x1180080949e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5065"            ,	   0x1180080949e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5066"            ,	   0x1180080949e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5067"            ,	   0x1180080949e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5068"            ,	   0x1180080949e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5069"            ,	   0x1180080949e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5070"            ,	   0x1180080949e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5071"            ,	   0x1180080949e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5072"            ,	   0x1180080949e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5073"            ,	   0x1180080949e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5074"            ,	   0x1180080949e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5075"            ,	   0x1180080949e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5076"            ,	   0x1180080949ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5077"            ,	   0x1180080949ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5078"            ,	   0x1180080949eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5079"            ,	   0x1180080949eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5080"            ,	   0x1180080949ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5081"            ,	   0x1180080949ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5082"            ,	   0x1180080949ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5083"            ,	   0x1180080949ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5084"            ,	   0x1180080949ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5085"            ,	   0x1180080949ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5086"            ,	   0x1180080949ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5087"            ,	   0x1180080949ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5088"            ,	   0x1180080949f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5089"            ,	   0x1180080949f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5090"            ,	   0x1180080949f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5091"            ,	   0x1180080949f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5092"            ,	   0x1180080949f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5093"            ,	   0x1180080949f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5094"            ,	   0x1180080949f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5095"            ,	   0x1180080949f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5096"            ,	   0x1180080949f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5097"            ,	   0x1180080949f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5098"            ,	   0x1180080949f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5099"            ,	   0x1180080949f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5100"            ,	   0x1180080949f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5101"            ,	   0x1180080949f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5102"            ,	   0x1180080949f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5103"            ,	   0x1180080949f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5104"            ,	   0x1180080949f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5105"            ,	   0x1180080949f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5106"            ,	   0x1180080949f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5107"            ,	   0x1180080949f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5108"            ,	   0x1180080949fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5109"            ,	   0x1180080949fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5110"            ,	   0x1180080949fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5111"            ,	   0x1180080949fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5112"            ,	   0x1180080949fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5113"            ,	   0x1180080949fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5114"            ,	   0x1180080949fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5115"            ,	   0x1180080949fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5116"            ,	   0x1180080949fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5117"            ,	   0x1180080949fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5118"            ,	   0x1180080949ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5119"            ,	   0x1180080949ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5120"            ,	   0x118008094a000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5121"            ,	   0x118008094a008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5122"            ,	   0x118008094a010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5123"            ,	   0x118008094a018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5124"            ,	   0x118008094a020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5125"            ,	   0x118008094a028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5126"            ,	   0x118008094a030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5127"            ,	   0x118008094a038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5128"            ,	   0x118008094a040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5129"            ,	   0x118008094a048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5130"            ,	   0x118008094a050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5131"            ,	   0x118008094a058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5132"            ,	   0x118008094a060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5133"            ,	   0x118008094a068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5134"            ,	   0x118008094a070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5135"            ,	   0x118008094a078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5136"            ,	   0x118008094a080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5137"            ,	   0x118008094a088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5138"            ,	   0x118008094a090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5139"            ,	   0x118008094a098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5140"            ,	   0x118008094a0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5141"            ,	   0x118008094a0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5142"            ,	   0x118008094a0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5143"            ,	   0x118008094a0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5144"            ,	   0x118008094a0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5145"            ,	   0x118008094a0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5146"            ,	   0x118008094a0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5147"            ,	   0x118008094a0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5148"            ,	   0x118008094a0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5149"            ,	   0x118008094a0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5150"            ,	   0x118008094a0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5151"            ,	   0x118008094a0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5152"            ,	   0x118008094a100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5153"            ,	   0x118008094a108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5154"            ,	   0x118008094a110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5155"            ,	   0x118008094a118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5156"            ,	   0x118008094a120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5157"            ,	   0x118008094a128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5158"            ,	   0x118008094a130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5159"            ,	   0x118008094a138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5160"            ,	   0x118008094a140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5161"            ,	   0x118008094a148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5162"            ,	   0x118008094a150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5163"            ,	   0x118008094a158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5164"            ,	   0x118008094a160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5165"            ,	   0x118008094a168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5166"            ,	   0x118008094a170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5167"            ,	   0x118008094a178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5168"            ,	   0x118008094a180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5169"            ,	   0x118008094a188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5170"            ,	   0x118008094a190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5171"            ,	   0x118008094a198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5172"            ,	   0x118008094a1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5173"            ,	   0x118008094a1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5174"            ,	   0x118008094a1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5175"            ,	   0x118008094a1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5176"            ,	   0x118008094a1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5177"            ,	   0x118008094a1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5178"            ,	   0x118008094a1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5179"            ,	   0x118008094a1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5180"            ,	   0x118008094a1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5181"            ,	   0x118008094a1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5182"            ,	   0x118008094a1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5183"            ,	   0x118008094a1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5184"            ,	   0x118008094a200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5185"            ,	   0x118008094a208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5186"            ,	   0x118008094a210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5187"            ,	   0x118008094a218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5188"            ,	   0x118008094a220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5189"            ,	   0x118008094a228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5190"            ,	   0x118008094a230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5191"            ,	   0x118008094a238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5192"            ,	   0x118008094a240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5193"            ,	   0x118008094a248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5194"            ,	   0x118008094a250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5195"            ,	   0x118008094a258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5196"            ,	   0x118008094a260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5197"            ,	   0x118008094a268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5198"            ,	   0x118008094a270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5199"            ,	   0x118008094a278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5200"            ,	   0x118008094a280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5201"            ,	   0x118008094a288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5202"            ,	   0x118008094a290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5203"            ,	   0x118008094a298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5204"            ,	   0x118008094a2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5205"            ,	   0x118008094a2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5206"            ,	   0x118008094a2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5207"            ,	   0x118008094a2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5208"            ,	   0x118008094a2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5209"            ,	   0x118008094a2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5210"            ,	   0x118008094a2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5211"            ,	   0x118008094a2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5212"            ,	   0x118008094a2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5213"            ,	   0x118008094a2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5214"            ,	   0x118008094a2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5215"            ,	   0x118008094a2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5216"            ,	   0x118008094a300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5217"            ,	   0x118008094a308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5218"            ,	   0x118008094a310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5219"            ,	   0x118008094a318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5220"            ,	   0x118008094a320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5221"            ,	   0x118008094a328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5222"            ,	   0x118008094a330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5223"            ,	   0x118008094a338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5224"            ,	   0x118008094a340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5225"            ,	   0x118008094a348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5226"            ,	   0x118008094a350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5227"            ,	   0x118008094a358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5228"            ,	   0x118008094a360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5229"            ,	   0x118008094a368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5230"            ,	   0x118008094a370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5231"            ,	   0x118008094a378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5232"            ,	   0x118008094a380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5233"            ,	   0x118008094a388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5234"            ,	   0x118008094a390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5235"            ,	   0x118008094a398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5236"            ,	   0x118008094a3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5237"            ,	   0x118008094a3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5238"            ,	   0x118008094a3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5239"            ,	   0x118008094a3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5240"            ,	   0x118008094a3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5241"            ,	   0x118008094a3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5242"            ,	   0x118008094a3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5243"            ,	   0x118008094a3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5244"            ,	   0x118008094a3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5245"            ,	   0x118008094a3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5246"            ,	   0x118008094a3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5247"            ,	   0x118008094a3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5248"            ,	   0x118008094a400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5249"            ,	   0x118008094a408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5250"            ,	   0x118008094a410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5251"            ,	   0x118008094a418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5252"            ,	   0x118008094a420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5253"            ,	   0x118008094a428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5254"            ,	   0x118008094a430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5255"            ,	   0x118008094a438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5256"            ,	   0x118008094a440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5257"            ,	   0x118008094a448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5258"            ,	   0x118008094a450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5259"            ,	   0x118008094a458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5260"            ,	   0x118008094a460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5261"            ,	   0x118008094a468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5262"            ,	   0x118008094a470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5263"            ,	   0x118008094a478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5264"            ,	   0x118008094a480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5265"            ,	   0x118008094a488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5266"            ,	   0x118008094a490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5267"            ,	   0x118008094a498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5268"            ,	   0x118008094a4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5269"            ,	   0x118008094a4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5270"            ,	   0x118008094a4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5271"            ,	   0x118008094a4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5272"            ,	   0x118008094a4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5273"            ,	   0x118008094a4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5274"            ,	   0x118008094a4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5275"            ,	   0x118008094a4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5276"            ,	   0x118008094a4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5277"            ,	   0x118008094a4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5278"            ,	   0x118008094a4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5279"            ,	   0x118008094a4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5280"            ,	   0x118008094a500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5281"            ,	   0x118008094a508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5282"            ,	   0x118008094a510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5283"            ,	   0x118008094a518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5284"            ,	   0x118008094a520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5285"            ,	   0x118008094a528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5286"            ,	   0x118008094a530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5287"            ,	   0x118008094a538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5288"            ,	   0x118008094a540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5289"            ,	   0x118008094a548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5290"            ,	   0x118008094a550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5291"            ,	   0x118008094a558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5292"            ,	   0x118008094a560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5293"            ,	   0x118008094a568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5294"            ,	   0x118008094a570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5295"            ,	   0x118008094a578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5296"            ,	   0x118008094a580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5297"            ,	   0x118008094a588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5298"            ,	   0x118008094a590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5299"            ,	   0x118008094a598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5300"            ,	   0x118008094a5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5301"            ,	   0x118008094a5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5302"            ,	   0x118008094a5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5303"            ,	   0x118008094a5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5304"            ,	   0x118008094a5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5305"            ,	   0x118008094a5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5306"            ,	   0x118008094a5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5307"            ,	   0x118008094a5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5308"            ,	   0x118008094a5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5309"            ,	   0x118008094a5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5310"            ,	   0x118008094a5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5311"            ,	   0x118008094a5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5312"            ,	   0x118008094a600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5313"            ,	   0x118008094a608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5314"            ,	   0x118008094a610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5315"            ,	   0x118008094a618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5316"            ,	   0x118008094a620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5317"            ,	   0x118008094a628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5318"            ,	   0x118008094a630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5319"            ,	   0x118008094a638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5320"            ,	   0x118008094a640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5321"            ,	   0x118008094a648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5322"            ,	   0x118008094a650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5323"            ,	   0x118008094a658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5324"            ,	   0x118008094a660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5325"            ,	   0x118008094a668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5326"            ,	   0x118008094a670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5327"            ,	   0x118008094a678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5328"            ,	   0x118008094a680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5329"            ,	   0x118008094a688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5330"            ,	   0x118008094a690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5331"            ,	   0x118008094a698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5332"            ,	   0x118008094a6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5333"            ,	   0x118008094a6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5334"            ,	   0x118008094a6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5335"            ,	   0x118008094a6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5336"            ,	   0x118008094a6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5337"            ,	   0x118008094a6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5338"            ,	   0x118008094a6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5339"            ,	   0x118008094a6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5340"            ,	   0x118008094a6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5341"            ,	   0x118008094a6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5342"            ,	   0x118008094a6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5343"            ,	   0x118008094a6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5344"            ,	   0x118008094a700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5345"            ,	   0x118008094a708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5346"            ,	   0x118008094a710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5347"            ,	   0x118008094a718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5348"            ,	   0x118008094a720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5349"            ,	   0x118008094a728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5350"            ,	   0x118008094a730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5351"            ,	   0x118008094a738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5352"            ,	   0x118008094a740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5353"            ,	   0x118008094a748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5354"            ,	   0x118008094a750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5355"            ,	   0x118008094a758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5356"            ,	   0x118008094a760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5357"            ,	   0x118008094a768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5358"            ,	   0x118008094a770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5359"            ,	   0x118008094a778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5360"            ,	   0x118008094a780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5361"            ,	   0x118008094a788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5362"            ,	   0x118008094a790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5363"            ,	   0x118008094a798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5364"            ,	   0x118008094a7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5365"            ,	   0x118008094a7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5366"            ,	   0x118008094a7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5367"            ,	   0x118008094a7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5368"            ,	   0x118008094a7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5369"            ,	   0x118008094a7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5370"            ,	   0x118008094a7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5371"            ,	   0x118008094a7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5372"            ,	   0x118008094a7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5373"            ,	   0x118008094a7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5374"            ,	   0x118008094a7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5375"            ,	   0x118008094a7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5376"            ,	   0x118008094a800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5377"            ,	   0x118008094a808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5378"            ,	   0x118008094a810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5379"            ,	   0x118008094a818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5380"            ,	   0x118008094a820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5381"            ,	   0x118008094a828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5382"            ,	   0x118008094a830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5383"            ,	   0x118008094a838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5384"            ,	   0x118008094a840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5385"            ,	   0x118008094a848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5386"            ,	   0x118008094a850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5387"            ,	   0x118008094a858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5388"            ,	   0x118008094a860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5389"            ,	   0x118008094a868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5390"            ,	   0x118008094a870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5391"            ,	   0x118008094a878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5392"            ,	   0x118008094a880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5393"            ,	   0x118008094a888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5394"            ,	   0x118008094a890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5395"            ,	   0x118008094a898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5396"            ,	   0x118008094a8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5397"            ,	   0x118008094a8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5398"            ,	   0x118008094a8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5399"            ,	   0x118008094a8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5400"            ,	   0x118008094a8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5401"            ,	   0x118008094a8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5402"            ,	   0x118008094a8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5403"            ,	   0x118008094a8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5404"            ,	   0x118008094a8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5405"            ,	   0x118008094a8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5406"            ,	   0x118008094a8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5407"            ,	   0x118008094a8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5408"            ,	   0x118008094a900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5409"            ,	   0x118008094a908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5410"            ,	   0x118008094a910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5411"            ,	   0x118008094a918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5412"            ,	   0x118008094a920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5413"            ,	   0x118008094a928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5414"            ,	   0x118008094a930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5415"            ,	   0x118008094a938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5416"            ,	   0x118008094a940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5417"            ,	   0x118008094a948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5418"            ,	   0x118008094a950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5419"            ,	   0x118008094a958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5420"            ,	   0x118008094a960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5421"            ,	   0x118008094a968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5422"            ,	   0x118008094a970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5423"            ,	   0x118008094a978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5424"            ,	   0x118008094a980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5425"            ,	   0x118008094a988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5426"            ,	   0x118008094a990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5427"            ,	   0x118008094a998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5428"            ,	   0x118008094a9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5429"            ,	   0x118008094a9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5430"            ,	   0x118008094a9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5431"            ,	   0x118008094a9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5432"            ,	   0x118008094a9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5433"            ,	   0x118008094a9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5434"            ,	   0x118008094a9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5435"            ,	   0x118008094a9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5436"            ,	   0x118008094a9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5437"            ,	   0x118008094a9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5438"            ,	   0x118008094a9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5439"            ,	   0x118008094a9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5440"            ,	   0x118008094aa00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5441"            ,	   0x118008094aa08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5442"            ,	   0x118008094aa10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5443"            ,	   0x118008094aa18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5444"            ,	   0x118008094aa20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5445"            ,	   0x118008094aa28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5446"            ,	   0x118008094aa30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5447"            ,	   0x118008094aa38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5448"            ,	   0x118008094aa40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5449"            ,	   0x118008094aa48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5450"            ,	   0x118008094aa50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5451"            ,	   0x118008094aa58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5452"            ,	   0x118008094aa60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5453"            ,	   0x118008094aa68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5454"            ,	   0x118008094aa70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5455"            ,	   0x118008094aa78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5456"            ,	   0x118008094aa80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5457"            ,	   0x118008094aa88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5458"            ,	   0x118008094aa90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5459"            ,	   0x118008094aa98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5460"            ,	   0x118008094aaa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5461"            ,	   0x118008094aaa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5462"            ,	   0x118008094aab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5463"            ,	   0x118008094aab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5464"            ,	   0x118008094aac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5465"            ,	   0x118008094aac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5466"            ,	   0x118008094aad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5467"            ,	   0x118008094aad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5468"            ,	   0x118008094aae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5469"            ,	   0x118008094aae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5470"            ,	   0x118008094aaf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5471"            ,	   0x118008094aaf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5472"            ,	   0x118008094ab00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5473"            ,	   0x118008094ab08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5474"            ,	   0x118008094ab10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5475"            ,	   0x118008094ab18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5476"            ,	   0x118008094ab20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5477"            ,	   0x118008094ab28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5478"            ,	   0x118008094ab30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5479"            ,	   0x118008094ab38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5480"            ,	   0x118008094ab40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5481"            ,	   0x118008094ab48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5482"            ,	   0x118008094ab50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5483"            ,	   0x118008094ab58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5484"            ,	   0x118008094ab60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5485"            ,	   0x118008094ab68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5486"            ,	   0x118008094ab70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5487"            ,	   0x118008094ab78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5488"            ,	   0x118008094ab80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5489"            ,	   0x118008094ab88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5490"            ,	   0x118008094ab90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5491"            ,	   0x118008094ab98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5492"            ,	   0x118008094aba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5493"            ,	   0x118008094aba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5494"            ,	   0x118008094abb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5495"            ,	   0x118008094abb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5496"            ,	   0x118008094abc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5497"            ,	   0x118008094abc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5498"            ,	   0x118008094abd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5499"            ,	   0x118008094abd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5500"            ,	   0x118008094abe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5501"            ,	   0x118008094abe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5502"            ,	   0x118008094abf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5503"            ,	   0x118008094abf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5504"            ,	   0x118008094ac00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5505"            ,	   0x118008094ac08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5506"            ,	   0x118008094ac10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5507"            ,	   0x118008094ac18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5508"            ,	   0x118008094ac20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5509"            ,	   0x118008094ac28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5510"            ,	   0x118008094ac30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5511"            ,	   0x118008094ac38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5512"            ,	   0x118008094ac40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5513"            ,	   0x118008094ac48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5514"            ,	   0x118008094ac50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5515"            ,	   0x118008094ac58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5516"            ,	   0x118008094ac60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5517"            ,	   0x118008094ac68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5518"            ,	   0x118008094ac70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5519"            ,	   0x118008094ac78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5520"            ,	   0x118008094ac80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5521"            ,	   0x118008094ac88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5522"            ,	   0x118008094ac90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5523"            ,	   0x118008094ac98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5524"            ,	   0x118008094aca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5525"            ,	   0x118008094aca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5526"            ,	   0x118008094acb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5527"            ,	   0x118008094acb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5528"            ,	   0x118008094acc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5529"            ,	   0x118008094acc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5530"            ,	   0x118008094acd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5531"            ,	   0x118008094acd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5532"            ,	   0x118008094ace0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5533"            ,	   0x118008094ace8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5534"            ,	   0x118008094acf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5535"            ,	   0x118008094acf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5536"            ,	   0x118008094ad00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5537"            ,	   0x118008094ad08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5538"            ,	   0x118008094ad10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5539"            ,	   0x118008094ad18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5540"            ,	   0x118008094ad20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5541"            ,	   0x118008094ad28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5542"            ,	   0x118008094ad30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5543"            ,	   0x118008094ad38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5544"            ,	   0x118008094ad40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5545"            ,	   0x118008094ad48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5546"            ,	   0x118008094ad50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5547"            ,	   0x118008094ad58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5548"            ,	   0x118008094ad60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5549"            ,	   0x118008094ad68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5550"            ,	   0x118008094ad70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5551"            ,	   0x118008094ad78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5552"            ,	   0x118008094ad80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5553"            ,	   0x118008094ad88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5554"            ,	   0x118008094ad90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5555"            ,	   0x118008094ad98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5556"            ,	   0x118008094ada0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5557"            ,	   0x118008094ada8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5558"            ,	   0x118008094adb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5559"            ,	   0x118008094adb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5560"            ,	   0x118008094adc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5561"            ,	   0x118008094adc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5562"            ,	   0x118008094add0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5563"            ,	   0x118008094add8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5564"            ,	   0x118008094ade0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5565"            ,	   0x118008094ade8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5566"            ,	   0x118008094adf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5567"            ,	   0x118008094adf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5568"            ,	   0x118008094ae00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5569"            ,	   0x118008094ae08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5570"            ,	   0x118008094ae10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5571"            ,	   0x118008094ae18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5572"            ,	   0x118008094ae20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5573"            ,	   0x118008094ae28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5574"            ,	   0x118008094ae30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5575"            ,	   0x118008094ae38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5576"            ,	   0x118008094ae40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5577"            ,	   0x118008094ae48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5578"            ,	   0x118008094ae50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5579"            ,	   0x118008094ae58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5580"            ,	   0x118008094ae60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5581"            ,	   0x118008094ae68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5582"            ,	   0x118008094ae70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5583"            ,	   0x118008094ae78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5584"            ,	   0x118008094ae80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5585"            ,	   0x118008094ae88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5586"            ,	   0x118008094ae90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5587"            ,	   0x118008094ae98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5588"            ,	   0x118008094aea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5589"            ,	   0x118008094aea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5590"            ,	   0x118008094aeb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5591"            ,	   0x118008094aeb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5592"            ,	   0x118008094aec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5593"            ,	   0x118008094aec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5594"            ,	   0x118008094aed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5595"            ,	   0x118008094aed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5596"            ,	   0x118008094aee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5597"            ,	   0x118008094aee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5598"            ,	   0x118008094aef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5599"            ,	   0x118008094aef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5600"            ,	   0x118008094af00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5601"            ,	   0x118008094af08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5602"            ,	   0x118008094af10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5603"            ,	   0x118008094af18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5604"            ,	   0x118008094af20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5605"            ,	   0x118008094af28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5606"            ,	   0x118008094af30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5607"            ,	   0x118008094af38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5608"            ,	   0x118008094af40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5609"            ,	   0x118008094af48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5610"            ,	   0x118008094af50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5611"            ,	   0x118008094af58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5612"            ,	   0x118008094af60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5613"            ,	   0x118008094af68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5614"            ,	   0x118008094af70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5615"            ,	   0x118008094af78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5616"            ,	   0x118008094af80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5617"            ,	   0x118008094af88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5618"            ,	   0x118008094af90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5619"            ,	   0x118008094af98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5620"            ,	   0x118008094afa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5621"            ,	   0x118008094afa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5622"            ,	   0x118008094afb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5623"            ,	   0x118008094afb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5624"            ,	   0x118008094afc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5625"            ,	   0x118008094afc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5626"            ,	   0x118008094afd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5627"            ,	   0x118008094afd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5628"            ,	   0x118008094afe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5629"            ,	   0x118008094afe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5630"            ,	   0x118008094aff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5631"            ,	   0x118008094aff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5632"            ,	   0x118008094b000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5633"            ,	   0x118008094b008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5634"            ,	   0x118008094b010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5635"            ,	   0x118008094b018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5636"            ,	   0x118008094b020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5637"            ,	   0x118008094b028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5638"            ,	   0x118008094b030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5639"            ,	   0x118008094b038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5640"            ,	   0x118008094b040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5641"            ,	   0x118008094b048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5642"            ,	   0x118008094b050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5643"            ,	   0x118008094b058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5644"            ,	   0x118008094b060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5645"            ,	   0x118008094b068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5646"            ,	   0x118008094b070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5647"            ,	   0x118008094b078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5648"            ,	   0x118008094b080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5649"            ,	   0x118008094b088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5650"            ,	   0x118008094b090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5651"            ,	   0x118008094b098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5652"            ,	   0x118008094b0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5653"            ,	   0x118008094b0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5654"            ,	   0x118008094b0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5655"            ,	   0x118008094b0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5656"            ,	   0x118008094b0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5657"            ,	   0x118008094b0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5658"            ,	   0x118008094b0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5659"            ,	   0x118008094b0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5660"            ,	   0x118008094b0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5661"            ,	   0x118008094b0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5662"            ,	   0x118008094b0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5663"            ,	   0x118008094b0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5664"            ,	   0x118008094b100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5665"            ,	   0x118008094b108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5666"            ,	   0x118008094b110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5667"            ,	   0x118008094b118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5668"            ,	   0x118008094b120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5669"            ,	   0x118008094b128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5670"            ,	   0x118008094b130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5671"            ,	   0x118008094b138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5672"            ,	   0x118008094b140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5673"            ,	   0x118008094b148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5674"            ,	   0x118008094b150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5675"            ,	   0x118008094b158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5676"            ,	   0x118008094b160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5677"            ,	   0x118008094b168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5678"            ,	   0x118008094b170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5679"            ,	   0x118008094b178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5680"            ,	   0x118008094b180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5681"            ,	   0x118008094b188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5682"            ,	   0x118008094b190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5683"            ,	   0x118008094b198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5684"            ,	   0x118008094b1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5685"            ,	   0x118008094b1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5686"            ,	   0x118008094b1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5687"            ,	   0x118008094b1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5688"            ,	   0x118008094b1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5689"            ,	   0x118008094b1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5690"            ,	   0x118008094b1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5691"            ,	   0x118008094b1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5692"            ,	   0x118008094b1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5693"            ,	   0x118008094b1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5694"            ,	   0x118008094b1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5695"            ,	   0x118008094b1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5696"            ,	   0x118008094b200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5697"            ,	   0x118008094b208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5698"            ,	   0x118008094b210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5699"            ,	   0x118008094b218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5700"            ,	   0x118008094b220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5701"            ,	   0x118008094b228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5702"            ,	   0x118008094b230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5703"            ,	   0x118008094b238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5704"            ,	   0x118008094b240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5705"            ,	   0x118008094b248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5706"            ,	   0x118008094b250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5707"            ,	   0x118008094b258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5708"            ,	   0x118008094b260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5709"            ,	   0x118008094b268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5710"            ,	   0x118008094b270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5711"            ,	   0x118008094b278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5712"            ,	   0x118008094b280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5713"            ,	   0x118008094b288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5714"            ,	   0x118008094b290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5715"            ,	   0x118008094b298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5716"            ,	   0x118008094b2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5717"            ,	   0x118008094b2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5718"            ,	   0x118008094b2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5719"            ,	   0x118008094b2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5720"            ,	   0x118008094b2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5721"            ,	   0x118008094b2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5722"            ,	   0x118008094b2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5723"            ,	   0x118008094b2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5724"            ,	   0x118008094b2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5725"            ,	   0x118008094b2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5726"            ,	   0x118008094b2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5727"            ,	   0x118008094b2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5728"            ,	   0x118008094b300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5729"            ,	   0x118008094b308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5730"            ,	   0x118008094b310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5731"            ,	   0x118008094b318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5732"            ,	   0x118008094b320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5733"            ,	   0x118008094b328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5734"            ,	   0x118008094b330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5735"            ,	   0x118008094b338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5736"            ,	   0x118008094b340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5737"            ,	   0x118008094b348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5738"            ,	   0x118008094b350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5739"            ,	   0x118008094b358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5740"            ,	   0x118008094b360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5741"            ,	   0x118008094b368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5742"            ,	   0x118008094b370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5743"            ,	   0x118008094b378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5744"            ,	   0x118008094b380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5745"            ,	   0x118008094b388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5746"            ,	   0x118008094b390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5747"            ,	   0x118008094b398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5748"            ,	   0x118008094b3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5749"            ,	   0x118008094b3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5750"            ,	   0x118008094b3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5751"            ,	   0x118008094b3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5752"            ,	   0x118008094b3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5753"            ,	   0x118008094b3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5754"            ,	   0x118008094b3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5755"            ,	   0x118008094b3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5756"            ,	   0x118008094b3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5757"            ,	   0x118008094b3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5758"            ,	   0x118008094b3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5759"            ,	   0x118008094b3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5760"            ,	   0x118008094b400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5761"            ,	   0x118008094b408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5762"            ,	   0x118008094b410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5763"            ,	   0x118008094b418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5764"            ,	   0x118008094b420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5765"            ,	   0x118008094b428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5766"            ,	   0x118008094b430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5767"            ,	   0x118008094b438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5768"            ,	   0x118008094b440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5769"            ,	   0x118008094b448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5770"            ,	   0x118008094b450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5771"            ,	   0x118008094b458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5772"            ,	   0x118008094b460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5773"            ,	   0x118008094b468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5774"            ,	   0x118008094b470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5775"            ,	   0x118008094b478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5776"            ,	   0x118008094b480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5777"            ,	   0x118008094b488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5778"            ,	   0x118008094b490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5779"            ,	   0x118008094b498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5780"            ,	   0x118008094b4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5781"            ,	   0x118008094b4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5782"            ,	   0x118008094b4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5783"            ,	   0x118008094b4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5784"            ,	   0x118008094b4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5785"            ,	   0x118008094b4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5786"            ,	   0x118008094b4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5787"            ,	   0x118008094b4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5788"            ,	   0x118008094b4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5789"            ,	   0x118008094b4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5790"            ,	   0x118008094b4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5791"            ,	   0x118008094b4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5792"            ,	   0x118008094b500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5793"            ,	   0x118008094b508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5794"            ,	   0x118008094b510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5795"            ,	   0x118008094b518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5796"            ,	   0x118008094b520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5797"            ,	   0x118008094b528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5798"            ,	   0x118008094b530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5799"            ,	   0x118008094b538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5800"            ,	   0x118008094b540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5801"            ,	   0x118008094b548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5802"            ,	   0x118008094b550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5803"            ,	   0x118008094b558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5804"            ,	   0x118008094b560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5805"            ,	   0x118008094b568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5806"            ,	   0x118008094b570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5807"            ,	   0x118008094b578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5808"            ,	   0x118008094b580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5809"            ,	   0x118008094b588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5810"            ,	   0x118008094b590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5811"            ,	   0x118008094b598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5812"            ,	   0x118008094b5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5813"            ,	   0x118008094b5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5814"            ,	   0x118008094b5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5815"            ,	   0x118008094b5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5816"            ,	   0x118008094b5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5817"            ,	   0x118008094b5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5818"            ,	   0x118008094b5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5819"            ,	   0x118008094b5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5820"            ,	   0x118008094b5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5821"            ,	   0x118008094b5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5822"            ,	   0x118008094b5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5823"            ,	   0x118008094b5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5824"            ,	   0x118008094b600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5825"            ,	   0x118008094b608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5826"            ,	   0x118008094b610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5827"            ,	   0x118008094b618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5828"            ,	   0x118008094b620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5829"            ,	   0x118008094b628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5830"            ,	   0x118008094b630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5831"            ,	   0x118008094b638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5832"            ,	   0x118008094b640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5833"            ,	   0x118008094b648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5834"            ,	   0x118008094b650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5835"            ,	   0x118008094b658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5836"            ,	   0x118008094b660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5837"            ,	   0x118008094b668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5838"            ,	   0x118008094b670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5839"            ,	   0x118008094b678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5840"            ,	   0x118008094b680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5841"            ,	   0x118008094b688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5842"            ,	   0x118008094b690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5843"            ,	   0x118008094b698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5844"            ,	   0x118008094b6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5845"            ,	   0x118008094b6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5846"            ,	   0x118008094b6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5847"            ,	   0x118008094b6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5848"            ,	   0x118008094b6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5849"            ,	   0x118008094b6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5850"            ,	   0x118008094b6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5851"            ,	   0x118008094b6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5852"            ,	   0x118008094b6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5853"            ,	   0x118008094b6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5854"            ,	   0x118008094b6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5855"            ,	   0x118008094b6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5856"            ,	   0x118008094b700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5857"            ,	   0x118008094b708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5858"            ,	   0x118008094b710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5859"            ,	   0x118008094b718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5860"            ,	   0x118008094b720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5861"            ,	   0x118008094b728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5862"            ,	   0x118008094b730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5863"            ,	   0x118008094b738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5864"            ,	   0x118008094b740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5865"            ,	   0x118008094b748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5866"            ,	   0x118008094b750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5867"            ,	   0x118008094b758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5868"            ,	   0x118008094b760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5869"            ,	   0x118008094b768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5870"            ,	   0x118008094b770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5871"            ,	   0x118008094b778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5872"            ,	   0x118008094b780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5873"            ,	   0x118008094b788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5874"            ,	   0x118008094b790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5875"            ,	   0x118008094b798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5876"            ,	   0x118008094b7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5877"            ,	   0x118008094b7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5878"            ,	   0x118008094b7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5879"            ,	   0x118008094b7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5880"            ,	   0x118008094b7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5881"            ,	   0x118008094b7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5882"            ,	   0x118008094b7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5883"            ,	   0x118008094b7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5884"            ,	   0x118008094b7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5885"            ,	   0x118008094b7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5886"            ,	   0x118008094b7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5887"            ,	   0x118008094b7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5888"            ,	   0x118008094b800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5889"            ,	   0x118008094b808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5890"            ,	   0x118008094b810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5891"            ,	   0x118008094b818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5892"            ,	   0x118008094b820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5893"            ,	   0x118008094b828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5894"            ,	   0x118008094b830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5895"            ,	   0x118008094b838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5896"            ,	   0x118008094b840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5897"            ,	   0x118008094b848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5898"            ,	   0x118008094b850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5899"            ,	   0x118008094b858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5900"            ,	   0x118008094b860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5901"            ,	   0x118008094b868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5902"            ,	   0x118008094b870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5903"            ,	   0x118008094b878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5904"            ,	   0x118008094b880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5905"            ,	   0x118008094b888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5906"            ,	   0x118008094b890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5907"            ,	   0x118008094b898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5908"            ,	   0x118008094b8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5909"            ,	   0x118008094b8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5910"            ,	   0x118008094b8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5911"            ,	   0x118008094b8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5912"            ,	   0x118008094b8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5913"            ,	   0x118008094b8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5914"            ,	   0x118008094b8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5915"            ,	   0x118008094b8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5916"            ,	   0x118008094b8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5917"            ,	   0x118008094b8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5918"            ,	   0x118008094b8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5919"            ,	   0x118008094b8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5920"            ,	   0x118008094b900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5921"            ,	   0x118008094b908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5922"            ,	   0x118008094b910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5923"            ,	   0x118008094b918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5924"            ,	   0x118008094b920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5925"            ,	   0x118008094b928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5926"            ,	   0x118008094b930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5927"            ,	   0x118008094b938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5928"            ,	   0x118008094b940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5929"            ,	   0x118008094b948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5930"            ,	   0x118008094b950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5931"            ,	   0x118008094b958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5932"            ,	   0x118008094b960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5933"            ,	   0x118008094b968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5934"            ,	   0x118008094b970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5935"            ,	   0x118008094b978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5936"            ,	   0x118008094b980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5937"            ,	   0x118008094b988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5938"            ,	   0x118008094b990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5939"            ,	   0x118008094b998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5940"            ,	   0x118008094b9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5941"            ,	   0x118008094b9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5942"            ,	   0x118008094b9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5943"            ,	   0x118008094b9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5944"            ,	   0x118008094b9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5945"            ,	   0x118008094b9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5946"            ,	   0x118008094b9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5947"            ,	   0x118008094b9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5948"            ,	   0x118008094b9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5949"            ,	   0x118008094b9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5950"            ,	   0x118008094b9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5951"            ,	   0x118008094b9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5952"            ,	   0x118008094ba00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5953"            ,	   0x118008094ba08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5954"            ,	   0x118008094ba10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5955"            ,	   0x118008094ba18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5956"            ,	   0x118008094ba20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5957"            ,	   0x118008094ba28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5958"            ,	   0x118008094ba30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5959"            ,	   0x118008094ba38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5960"            ,	   0x118008094ba40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5961"            ,	   0x118008094ba48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5962"            ,	   0x118008094ba50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5963"            ,	   0x118008094ba58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5964"            ,	   0x118008094ba60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5965"            ,	   0x118008094ba68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5966"            ,	   0x118008094ba70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5967"            ,	   0x118008094ba78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5968"            ,	   0x118008094ba80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5969"            ,	   0x118008094ba88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5970"            ,	   0x118008094ba90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5971"            ,	   0x118008094ba98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5972"            ,	   0x118008094baa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5973"            ,	   0x118008094baa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5974"            ,	   0x118008094bab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5975"            ,	   0x118008094bab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5976"            ,	   0x118008094bac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5977"            ,	   0x118008094bac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5978"            ,	   0x118008094bad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5979"            ,	   0x118008094bad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5980"            ,	   0x118008094bae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5981"            ,	   0x118008094bae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5982"            ,	   0x118008094baf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5983"            ,	   0x118008094baf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5984"            ,	   0x118008094bb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5985"            ,	   0x118008094bb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5986"            ,	   0x118008094bb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5987"            ,	   0x118008094bb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5988"            ,	   0x118008094bb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5989"            ,	   0x118008094bb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5990"            ,	   0x118008094bb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5991"            ,	   0x118008094bb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5992"            ,	   0x118008094bb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5993"            ,	   0x118008094bb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5994"            ,	   0x118008094bb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5995"            ,	   0x118008094bb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5996"            ,	   0x118008094bb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5997"            ,	   0x118008094bb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5998"            ,	   0x118008094bb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP5999"            ,	   0x118008094bb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6000"            ,	   0x118008094bb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6001"            ,	   0x118008094bb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6002"            ,	   0x118008094bb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6003"            ,	   0x118008094bb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6004"            ,	   0x118008094bba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6005"            ,	   0x118008094bba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6006"            ,	   0x118008094bbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6007"            ,	   0x118008094bbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6008"            ,	   0x118008094bbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6009"            ,	   0x118008094bbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6010"            ,	   0x118008094bbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6011"            ,	   0x118008094bbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6012"            ,	   0x118008094bbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6013"            ,	   0x118008094bbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6014"            ,	   0x118008094bbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6015"            ,	   0x118008094bbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6016"            ,	   0x118008094bc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6017"            ,	   0x118008094bc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6018"            ,	   0x118008094bc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6019"            ,	   0x118008094bc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6020"            ,	   0x118008094bc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6021"            ,	   0x118008094bc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6022"            ,	   0x118008094bc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6023"            ,	   0x118008094bc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6024"            ,	   0x118008094bc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6025"            ,	   0x118008094bc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6026"            ,	   0x118008094bc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6027"            ,	   0x118008094bc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6028"            ,	   0x118008094bc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6029"            ,	   0x118008094bc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6030"            ,	   0x118008094bc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6031"            ,	   0x118008094bc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6032"            ,	   0x118008094bc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6033"            ,	   0x118008094bc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6034"            ,	   0x118008094bc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6035"            ,	   0x118008094bc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6036"            ,	   0x118008094bca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6037"            ,	   0x118008094bca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6038"            ,	   0x118008094bcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6039"            ,	   0x118008094bcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6040"            ,	   0x118008094bcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6041"            ,	   0x118008094bcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6042"            ,	   0x118008094bcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6043"            ,	   0x118008094bcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6044"            ,	   0x118008094bce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6045"            ,	   0x118008094bce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6046"            ,	   0x118008094bcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6047"            ,	   0x118008094bcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6048"            ,	   0x118008094bd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6049"            ,	   0x118008094bd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6050"            ,	   0x118008094bd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6051"            ,	   0x118008094bd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6052"            ,	   0x118008094bd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6053"            ,	   0x118008094bd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6054"            ,	   0x118008094bd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6055"            ,	   0x118008094bd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6056"            ,	   0x118008094bd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6057"            ,	   0x118008094bd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6058"            ,	   0x118008094bd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6059"            ,	   0x118008094bd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6060"            ,	   0x118008094bd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6061"            ,	   0x118008094bd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6062"            ,	   0x118008094bd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6063"            ,	   0x118008094bd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6064"            ,	   0x118008094bd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6065"            ,	   0x118008094bd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6066"            ,	   0x118008094bd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6067"            ,	   0x118008094bd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6068"            ,	   0x118008094bda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6069"            ,	   0x118008094bda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6070"            ,	   0x118008094bdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6071"            ,	   0x118008094bdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6072"            ,	   0x118008094bdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6073"            ,	   0x118008094bdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6074"            ,	   0x118008094bdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6075"            ,	   0x118008094bdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6076"            ,	   0x118008094bde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6077"            ,	   0x118008094bde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6078"            ,	   0x118008094bdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6079"            ,	   0x118008094bdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6080"            ,	   0x118008094be00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6081"            ,	   0x118008094be08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6082"            ,	   0x118008094be10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6083"            ,	   0x118008094be18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6084"            ,	   0x118008094be20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6085"            ,	   0x118008094be28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6086"            ,	   0x118008094be30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6087"            ,	   0x118008094be38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6088"            ,	   0x118008094be40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6089"            ,	   0x118008094be48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6090"            ,	   0x118008094be50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6091"            ,	   0x118008094be58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6092"            ,	   0x118008094be60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6093"            ,	   0x118008094be68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6094"            ,	   0x118008094be70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6095"            ,	   0x118008094be78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6096"            ,	   0x118008094be80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6097"            ,	   0x118008094be88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6098"            ,	   0x118008094be90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6099"            ,	   0x118008094be98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6100"            ,	   0x118008094bea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6101"            ,	   0x118008094bea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6102"            ,	   0x118008094beb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6103"            ,	   0x118008094beb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6104"            ,	   0x118008094bec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6105"            ,	   0x118008094bec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6106"            ,	   0x118008094bed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6107"            ,	   0x118008094bed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6108"            ,	   0x118008094bee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6109"            ,	   0x118008094bee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6110"            ,	   0x118008094bef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6111"            ,	   0x118008094bef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6112"            ,	   0x118008094bf00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6113"            ,	   0x118008094bf08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6114"            ,	   0x118008094bf10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6115"            ,	   0x118008094bf18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6116"            ,	   0x118008094bf20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6117"            ,	   0x118008094bf28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6118"            ,	   0x118008094bf30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6119"            ,	   0x118008094bf38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6120"            ,	   0x118008094bf40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6121"            ,	   0x118008094bf48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6122"            ,	   0x118008094bf50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6123"            ,	   0x118008094bf58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6124"            ,	   0x118008094bf60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6125"            ,	   0x118008094bf68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6126"            ,	   0x118008094bf70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6127"            ,	   0x118008094bf78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6128"            ,	   0x118008094bf80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6129"            ,	   0x118008094bf88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6130"            ,	   0x118008094bf90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6131"            ,	   0x118008094bf98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6132"            ,	   0x118008094bfa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6133"            ,	   0x118008094bfa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6134"            ,	   0x118008094bfb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6135"            ,	   0x118008094bfb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6136"            ,	   0x118008094bfc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6137"            ,	   0x118008094bfc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6138"            ,	   0x118008094bfd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6139"            ,	   0x118008094bfd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6140"            ,	   0x118008094bfe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6141"            ,	   0x118008094bfe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6142"            ,	   0x118008094bff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6143"            ,	   0x118008094bff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6144"            ,	   0x118008094c000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6145"            ,	   0x118008094c008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6146"            ,	   0x118008094c010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6147"            ,	   0x118008094c018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6148"            ,	   0x118008094c020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6149"            ,	   0x118008094c028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6150"            ,	   0x118008094c030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6151"            ,	   0x118008094c038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6152"            ,	   0x118008094c040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6153"            ,	   0x118008094c048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6154"            ,	   0x118008094c050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6155"            ,	   0x118008094c058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6156"            ,	   0x118008094c060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6157"            ,	   0x118008094c068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6158"            ,	   0x118008094c070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6159"            ,	   0x118008094c078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6160"            ,	   0x118008094c080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6161"            ,	   0x118008094c088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6162"            ,	   0x118008094c090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6163"            ,	   0x118008094c098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6164"            ,	   0x118008094c0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6165"            ,	   0x118008094c0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6166"            ,	   0x118008094c0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6167"            ,	   0x118008094c0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6168"            ,	   0x118008094c0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6169"            ,	   0x118008094c0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6170"            ,	   0x118008094c0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6171"            ,	   0x118008094c0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6172"            ,	   0x118008094c0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6173"            ,	   0x118008094c0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6174"            ,	   0x118008094c0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6175"            ,	   0x118008094c0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6176"            ,	   0x118008094c100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6177"            ,	   0x118008094c108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6178"            ,	   0x118008094c110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6179"            ,	   0x118008094c118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6180"            ,	   0x118008094c120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6181"            ,	   0x118008094c128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6182"            ,	   0x118008094c130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6183"            ,	   0x118008094c138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6184"            ,	   0x118008094c140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6185"            ,	   0x118008094c148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6186"            ,	   0x118008094c150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6187"            ,	   0x118008094c158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6188"            ,	   0x118008094c160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6189"            ,	   0x118008094c168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6190"            ,	   0x118008094c170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6191"            ,	   0x118008094c178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6192"            ,	   0x118008094c180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6193"            ,	   0x118008094c188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6194"            ,	   0x118008094c190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6195"            ,	   0x118008094c198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6196"            ,	   0x118008094c1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6197"            ,	   0x118008094c1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6198"            ,	   0x118008094c1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6199"            ,	   0x118008094c1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6200"            ,	   0x118008094c1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6201"            ,	   0x118008094c1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6202"            ,	   0x118008094c1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6203"            ,	   0x118008094c1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6204"            ,	   0x118008094c1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6205"            ,	   0x118008094c1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6206"            ,	   0x118008094c1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6207"            ,	   0x118008094c1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6208"            ,	   0x118008094c200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6209"            ,	   0x118008094c208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6210"            ,	   0x118008094c210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6211"            ,	   0x118008094c218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6212"            ,	   0x118008094c220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6213"            ,	   0x118008094c228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6214"            ,	   0x118008094c230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6215"            ,	   0x118008094c238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6216"            ,	   0x118008094c240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6217"            ,	   0x118008094c248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6218"            ,	   0x118008094c250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6219"            ,	   0x118008094c258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6220"            ,	   0x118008094c260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6221"            ,	   0x118008094c268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6222"            ,	   0x118008094c270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6223"            ,	   0x118008094c278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6224"            ,	   0x118008094c280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6225"            ,	   0x118008094c288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6226"            ,	   0x118008094c290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6227"            ,	   0x118008094c298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6228"            ,	   0x118008094c2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6229"            ,	   0x118008094c2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6230"            ,	   0x118008094c2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6231"            ,	   0x118008094c2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6232"            ,	   0x118008094c2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6233"            ,	   0x118008094c2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6234"            ,	   0x118008094c2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6235"            ,	   0x118008094c2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6236"            ,	   0x118008094c2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6237"            ,	   0x118008094c2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6238"            ,	   0x118008094c2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6239"            ,	   0x118008094c2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6240"            ,	   0x118008094c300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6241"            ,	   0x118008094c308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6242"            ,	   0x118008094c310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6243"            ,	   0x118008094c318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6244"            ,	   0x118008094c320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6245"            ,	   0x118008094c328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6246"            ,	   0x118008094c330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6247"            ,	   0x118008094c338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6248"            ,	   0x118008094c340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6249"            ,	   0x118008094c348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6250"            ,	   0x118008094c350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6251"            ,	   0x118008094c358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6252"            ,	   0x118008094c360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6253"            ,	   0x118008094c368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6254"            ,	   0x118008094c370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6255"            ,	   0x118008094c378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6256"            ,	   0x118008094c380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6257"            ,	   0x118008094c388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6258"            ,	   0x118008094c390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6259"            ,	   0x118008094c398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6260"            ,	   0x118008094c3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6261"            ,	   0x118008094c3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6262"            ,	   0x118008094c3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6263"            ,	   0x118008094c3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6264"            ,	   0x118008094c3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6265"            ,	   0x118008094c3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6266"            ,	   0x118008094c3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6267"            ,	   0x118008094c3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6268"            ,	   0x118008094c3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6269"            ,	   0x118008094c3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6270"            ,	   0x118008094c3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6271"            ,	   0x118008094c3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6272"            ,	   0x118008094c400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6273"            ,	   0x118008094c408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6274"            ,	   0x118008094c410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6275"            ,	   0x118008094c418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6276"            ,	   0x118008094c420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6277"            ,	   0x118008094c428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6278"            ,	   0x118008094c430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6279"            ,	   0x118008094c438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6280"            ,	   0x118008094c440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6281"            ,	   0x118008094c448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6282"            ,	   0x118008094c450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6283"            ,	   0x118008094c458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6284"            ,	   0x118008094c460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6285"            ,	   0x118008094c468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6286"            ,	   0x118008094c470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6287"            ,	   0x118008094c478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6288"            ,	   0x118008094c480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6289"            ,	   0x118008094c488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6290"            ,	   0x118008094c490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6291"            ,	   0x118008094c498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6292"            ,	   0x118008094c4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6293"            ,	   0x118008094c4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6294"            ,	   0x118008094c4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6295"            ,	   0x118008094c4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6296"            ,	   0x118008094c4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6297"            ,	   0x118008094c4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6298"            ,	   0x118008094c4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6299"            ,	   0x118008094c4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6300"            ,	   0x118008094c4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6301"            ,	   0x118008094c4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6302"            ,	   0x118008094c4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6303"            ,	   0x118008094c4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6304"            ,	   0x118008094c500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6305"            ,	   0x118008094c508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6306"            ,	   0x118008094c510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6307"            ,	   0x118008094c518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6308"            ,	   0x118008094c520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6309"            ,	   0x118008094c528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6310"            ,	   0x118008094c530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6311"            ,	   0x118008094c538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6312"            ,	   0x118008094c540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6313"            ,	   0x118008094c548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6314"            ,	   0x118008094c550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6315"            ,	   0x118008094c558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6316"            ,	   0x118008094c560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6317"            ,	   0x118008094c568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6318"            ,	   0x118008094c570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6319"            ,	   0x118008094c578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6320"            ,	   0x118008094c580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6321"            ,	   0x118008094c588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6322"            ,	   0x118008094c590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6323"            ,	   0x118008094c598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6324"            ,	   0x118008094c5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6325"            ,	   0x118008094c5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6326"            ,	   0x118008094c5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6327"            ,	   0x118008094c5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6328"            ,	   0x118008094c5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6329"            ,	   0x118008094c5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6330"            ,	   0x118008094c5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6331"            ,	   0x118008094c5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6332"            ,	   0x118008094c5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6333"            ,	   0x118008094c5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6334"            ,	   0x118008094c5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6335"            ,	   0x118008094c5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6336"            ,	   0x118008094c600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6337"            ,	   0x118008094c608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6338"            ,	   0x118008094c610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6339"            ,	   0x118008094c618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6340"            ,	   0x118008094c620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6341"            ,	   0x118008094c628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6342"            ,	   0x118008094c630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6343"            ,	   0x118008094c638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6344"            ,	   0x118008094c640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6345"            ,	   0x118008094c648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6346"            ,	   0x118008094c650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6347"            ,	   0x118008094c658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6348"            ,	   0x118008094c660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6349"            ,	   0x118008094c668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6350"            ,	   0x118008094c670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6351"            ,	   0x118008094c678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6352"            ,	   0x118008094c680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6353"            ,	   0x118008094c688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6354"            ,	   0x118008094c690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6355"            ,	   0x118008094c698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6356"            ,	   0x118008094c6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6357"            ,	   0x118008094c6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6358"            ,	   0x118008094c6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6359"            ,	   0x118008094c6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6360"            ,	   0x118008094c6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6361"            ,	   0x118008094c6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6362"            ,	   0x118008094c6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6363"            ,	   0x118008094c6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6364"            ,	   0x118008094c6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6365"            ,	   0x118008094c6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6366"            ,	   0x118008094c6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6367"            ,	   0x118008094c6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6368"            ,	   0x118008094c700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6369"            ,	   0x118008094c708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6370"            ,	   0x118008094c710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6371"            ,	   0x118008094c718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6372"            ,	   0x118008094c720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6373"            ,	   0x118008094c728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6374"            ,	   0x118008094c730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6375"            ,	   0x118008094c738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6376"            ,	   0x118008094c740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6377"            ,	   0x118008094c748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6378"            ,	   0x118008094c750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6379"            ,	   0x118008094c758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6380"            ,	   0x118008094c760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6381"            ,	   0x118008094c768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6382"            ,	   0x118008094c770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6383"            ,	   0x118008094c778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6384"            ,	   0x118008094c780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6385"            ,	   0x118008094c788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6386"            ,	   0x118008094c790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6387"            ,	   0x118008094c798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6388"            ,	   0x118008094c7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6389"            ,	   0x118008094c7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6390"            ,	   0x118008094c7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6391"            ,	   0x118008094c7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6392"            ,	   0x118008094c7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6393"            ,	   0x118008094c7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6394"            ,	   0x118008094c7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6395"            ,	   0x118008094c7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6396"            ,	   0x118008094c7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6397"            ,	   0x118008094c7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6398"            ,	   0x118008094c7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6399"            ,	   0x118008094c7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6400"            ,	   0x118008094c800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6401"            ,	   0x118008094c808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6402"            ,	   0x118008094c810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6403"            ,	   0x118008094c818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6404"            ,	   0x118008094c820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6405"            ,	   0x118008094c828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6406"            ,	   0x118008094c830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6407"            ,	   0x118008094c838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6408"            ,	   0x118008094c840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6409"            ,	   0x118008094c848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6410"            ,	   0x118008094c850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6411"            ,	   0x118008094c858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6412"            ,	   0x118008094c860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6413"            ,	   0x118008094c868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6414"            ,	   0x118008094c870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6415"            ,	   0x118008094c878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6416"            ,	   0x118008094c880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6417"            ,	   0x118008094c888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6418"            ,	   0x118008094c890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6419"            ,	   0x118008094c898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6420"            ,	   0x118008094c8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6421"            ,	   0x118008094c8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6422"            ,	   0x118008094c8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6423"            ,	   0x118008094c8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6424"            ,	   0x118008094c8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6425"            ,	   0x118008094c8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6426"            ,	   0x118008094c8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6427"            ,	   0x118008094c8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6428"            ,	   0x118008094c8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6429"            ,	   0x118008094c8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6430"            ,	   0x118008094c8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6431"            ,	   0x118008094c8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6432"            ,	   0x118008094c900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6433"            ,	   0x118008094c908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6434"            ,	   0x118008094c910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6435"            ,	   0x118008094c918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6436"            ,	   0x118008094c920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6437"            ,	   0x118008094c928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6438"            ,	   0x118008094c930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6439"            ,	   0x118008094c938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6440"            ,	   0x118008094c940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6441"            ,	   0x118008094c948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6442"            ,	   0x118008094c950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6443"            ,	   0x118008094c958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6444"            ,	   0x118008094c960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6445"            ,	   0x118008094c968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6446"            ,	   0x118008094c970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6447"            ,	   0x118008094c978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6448"            ,	   0x118008094c980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6449"            ,	   0x118008094c988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6450"            ,	   0x118008094c990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6451"            ,	   0x118008094c998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6452"            ,	   0x118008094c9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6453"            ,	   0x118008094c9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6454"            ,	   0x118008094c9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6455"            ,	   0x118008094c9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6456"            ,	   0x118008094c9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6457"            ,	   0x118008094c9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6458"            ,	   0x118008094c9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6459"            ,	   0x118008094c9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6460"            ,	   0x118008094c9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6461"            ,	   0x118008094c9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6462"            ,	   0x118008094c9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6463"            ,	   0x118008094c9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6464"            ,	   0x118008094ca00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6465"            ,	   0x118008094ca08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6466"            ,	   0x118008094ca10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6467"            ,	   0x118008094ca18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6468"            ,	   0x118008094ca20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6469"            ,	   0x118008094ca28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6470"            ,	   0x118008094ca30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6471"            ,	   0x118008094ca38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6472"            ,	   0x118008094ca40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6473"            ,	   0x118008094ca48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6474"            ,	   0x118008094ca50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6475"            ,	   0x118008094ca58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6476"            ,	   0x118008094ca60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6477"            ,	   0x118008094ca68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6478"            ,	   0x118008094ca70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6479"            ,	   0x118008094ca78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6480"            ,	   0x118008094ca80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6481"            ,	   0x118008094ca88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6482"            ,	   0x118008094ca90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6483"            ,	   0x118008094ca98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6484"            ,	   0x118008094caa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6485"            ,	   0x118008094caa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6486"            ,	   0x118008094cab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6487"            ,	   0x118008094cab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6488"            ,	   0x118008094cac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6489"            ,	   0x118008094cac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6490"            ,	   0x118008094cad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6491"            ,	   0x118008094cad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6492"            ,	   0x118008094cae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6493"            ,	   0x118008094cae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6494"            ,	   0x118008094caf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6495"            ,	   0x118008094caf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6496"            ,	   0x118008094cb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6497"            ,	   0x118008094cb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6498"            ,	   0x118008094cb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6499"            ,	   0x118008094cb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6500"            ,	   0x118008094cb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6501"            ,	   0x118008094cb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6502"            ,	   0x118008094cb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6503"            ,	   0x118008094cb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6504"            ,	   0x118008094cb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6505"            ,	   0x118008094cb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6506"            ,	   0x118008094cb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6507"            ,	   0x118008094cb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6508"            ,	   0x118008094cb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6509"            ,	   0x118008094cb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6510"            ,	   0x118008094cb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6511"            ,	   0x118008094cb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6512"            ,	   0x118008094cb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6513"            ,	   0x118008094cb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6514"            ,	   0x118008094cb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6515"            ,	   0x118008094cb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6516"            ,	   0x118008094cba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6517"            ,	   0x118008094cba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6518"            ,	   0x118008094cbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6519"            ,	   0x118008094cbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6520"            ,	   0x118008094cbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6521"            ,	   0x118008094cbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6522"            ,	   0x118008094cbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6523"            ,	   0x118008094cbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6524"            ,	   0x118008094cbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6525"            ,	   0x118008094cbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6526"            ,	   0x118008094cbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6527"            ,	   0x118008094cbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6528"            ,	   0x118008094cc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6529"            ,	   0x118008094cc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6530"            ,	   0x118008094cc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6531"            ,	   0x118008094cc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6532"            ,	   0x118008094cc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6533"            ,	   0x118008094cc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6534"            ,	   0x118008094cc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6535"            ,	   0x118008094cc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6536"            ,	   0x118008094cc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6537"            ,	   0x118008094cc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6538"            ,	   0x118008094cc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6539"            ,	   0x118008094cc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6540"            ,	   0x118008094cc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6541"            ,	   0x118008094cc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6542"            ,	   0x118008094cc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6543"            ,	   0x118008094cc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6544"            ,	   0x118008094cc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6545"            ,	   0x118008094cc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6546"            ,	   0x118008094cc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6547"            ,	   0x118008094cc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6548"            ,	   0x118008094cca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6549"            ,	   0x118008094cca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6550"            ,	   0x118008094ccb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6551"            ,	   0x118008094ccb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6552"            ,	   0x118008094ccc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6553"            ,	   0x118008094ccc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6554"            ,	   0x118008094ccd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6555"            ,	   0x118008094ccd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6556"            ,	   0x118008094cce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6557"            ,	   0x118008094cce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6558"            ,	   0x118008094ccf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6559"            ,	   0x118008094ccf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6560"            ,	   0x118008094cd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6561"            ,	   0x118008094cd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6562"            ,	   0x118008094cd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6563"            ,	   0x118008094cd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6564"            ,	   0x118008094cd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6565"            ,	   0x118008094cd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6566"            ,	   0x118008094cd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6567"            ,	   0x118008094cd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6568"            ,	   0x118008094cd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6569"            ,	   0x118008094cd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6570"            ,	   0x118008094cd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6571"            ,	   0x118008094cd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6572"            ,	   0x118008094cd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6573"            ,	   0x118008094cd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6574"            ,	   0x118008094cd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6575"            ,	   0x118008094cd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6576"            ,	   0x118008094cd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6577"            ,	   0x118008094cd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6578"            ,	   0x118008094cd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6579"            ,	   0x118008094cd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6580"            ,	   0x118008094cda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6581"            ,	   0x118008094cda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6582"            ,	   0x118008094cdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6583"            ,	   0x118008094cdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6584"            ,	   0x118008094cdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6585"            ,	   0x118008094cdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6586"            ,	   0x118008094cdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6587"            ,	   0x118008094cdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6588"            ,	   0x118008094cde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6589"            ,	   0x118008094cde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6590"            ,	   0x118008094cdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6591"            ,	   0x118008094cdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6592"            ,	   0x118008094ce00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6593"            ,	   0x118008094ce08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6594"            ,	   0x118008094ce10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6595"            ,	   0x118008094ce18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6596"            ,	   0x118008094ce20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6597"            ,	   0x118008094ce28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6598"            ,	   0x118008094ce30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6599"            ,	   0x118008094ce38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6600"            ,	   0x118008094ce40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6601"            ,	   0x118008094ce48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6602"            ,	   0x118008094ce50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6603"            ,	   0x118008094ce58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6604"            ,	   0x118008094ce60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6605"            ,	   0x118008094ce68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6606"            ,	   0x118008094ce70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6607"            ,	   0x118008094ce78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6608"            ,	   0x118008094ce80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6609"            ,	   0x118008094ce88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6610"            ,	   0x118008094ce90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6611"            ,	   0x118008094ce98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6612"            ,	   0x118008094cea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6613"            ,	   0x118008094cea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6614"            ,	   0x118008094ceb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6615"            ,	   0x118008094ceb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6616"            ,	   0x118008094cec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6617"            ,	   0x118008094cec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6618"            ,	   0x118008094ced0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6619"            ,	   0x118008094ced8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6620"            ,	   0x118008094cee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6621"            ,	   0x118008094cee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6622"            ,	   0x118008094cef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6623"            ,	   0x118008094cef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6624"            ,	   0x118008094cf00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6625"            ,	   0x118008094cf08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6626"            ,	   0x118008094cf10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6627"            ,	   0x118008094cf18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6628"            ,	   0x118008094cf20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6629"            ,	   0x118008094cf28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6630"            ,	   0x118008094cf30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6631"            ,	   0x118008094cf38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6632"            ,	   0x118008094cf40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6633"            ,	   0x118008094cf48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6634"            ,	   0x118008094cf50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6635"            ,	   0x118008094cf58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6636"            ,	   0x118008094cf60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6637"            ,	   0x118008094cf68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6638"            ,	   0x118008094cf70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6639"            ,	   0x118008094cf78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6640"            ,	   0x118008094cf80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6641"            ,	   0x118008094cf88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6642"            ,	   0x118008094cf90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6643"            ,	   0x118008094cf98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6644"            ,	   0x118008094cfa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6645"            ,	   0x118008094cfa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6646"            ,	   0x118008094cfb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6647"            ,	   0x118008094cfb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6648"            ,	   0x118008094cfc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6649"            ,	   0x118008094cfc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6650"            ,	   0x118008094cfd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6651"            ,	   0x118008094cfd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6652"            ,	   0x118008094cfe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6653"            ,	   0x118008094cfe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6654"            ,	   0x118008094cff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6655"            ,	   0x118008094cff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6656"            ,	   0x118008094d000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6657"            ,	   0x118008094d008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6658"            ,	   0x118008094d010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6659"            ,	   0x118008094d018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6660"            ,	   0x118008094d020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6661"            ,	   0x118008094d028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6662"            ,	   0x118008094d030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6663"            ,	   0x118008094d038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6664"            ,	   0x118008094d040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6665"            ,	   0x118008094d048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6666"            ,	   0x118008094d050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6667"            ,	   0x118008094d058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6668"            ,	   0x118008094d060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6669"            ,	   0x118008094d068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6670"            ,	   0x118008094d070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6671"            ,	   0x118008094d078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6672"            ,	   0x118008094d080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6673"            ,	   0x118008094d088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6674"            ,	   0x118008094d090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6675"            ,	   0x118008094d098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6676"            ,	   0x118008094d0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6677"            ,	   0x118008094d0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6678"            ,	   0x118008094d0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6679"            ,	   0x118008094d0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6680"            ,	   0x118008094d0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6681"            ,	   0x118008094d0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6682"            ,	   0x118008094d0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6683"            ,	   0x118008094d0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6684"            ,	   0x118008094d0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6685"            ,	   0x118008094d0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6686"            ,	   0x118008094d0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6687"            ,	   0x118008094d0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6688"            ,	   0x118008094d100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6689"            ,	   0x118008094d108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6690"            ,	   0x118008094d110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6691"            ,	   0x118008094d118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6692"            ,	   0x118008094d120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6693"            ,	   0x118008094d128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6694"            ,	   0x118008094d130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6695"            ,	   0x118008094d138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6696"            ,	   0x118008094d140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6697"            ,	   0x118008094d148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6698"            ,	   0x118008094d150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6699"            ,	   0x118008094d158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6700"            ,	   0x118008094d160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6701"            ,	   0x118008094d168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6702"            ,	   0x118008094d170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6703"            ,	   0x118008094d178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6704"            ,	   0x118008094d180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6705"            ,	   0x118008094d188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6706"            ,	   0x118008094d190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6707"            ,	   0x118008094d198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6708"            ,	   0x118008094d1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6709"            ,	   0x118008094d1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6710"            ,	   0x118008094d1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6711"            ,	   0x118008094d1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6712"            ,	   0x118008094d1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6713"            ,	   0x118008094d1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6714"            ,	   0x118008094d1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6715"            ,	   0x118008094d1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6716"            ,	   0x118008094d1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6717"            ,	   0x118008094d1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6718"            ,	   0x118008094d1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6719"            ,	   0x118008094d1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6720"            ,	   0x118008094d200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6721"            ,	   0x118008094d208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6722"            ,	   0x118008094d210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6723"            ,	   0x118008094d218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6724"            ,	   0x118008094d220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6725"            ,	   0x118008094d228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6726"            ,	   0x118008094d230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6727"            ,	   0x118008094d238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6728"            ,	   0x118008094d240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6729"            ,	   0x118008094d248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6730"            ,	   0x118008094d250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6731"            ,	   0x118008094d258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6732"            ,	   0x118008094d260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6733"            ,	   0x118008094d268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6734"            ,	   0x118008094d270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6735"            ,	   0x118008094d278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6736"            ,	   0x118008094d280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6737"            ,	   0x118008094d288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6738"            ,	   0x118008094d290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6739"            ,	   0x118008094d298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6740"            ,	   0x118008094d2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6741"            ,	   0x118008094d2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6742"            ,	   0x118008094d2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6743"            ,	   0x118008094d2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6744"            ,	   0x118008094d2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6745"            ,	   0x118008094d2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6746"            ,	   0x118008094d2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6747"            ,	   0x118008094d2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6748"            ,	   0x118008094d2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6749"            ,	   0x118008094d2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6750"            ,	   0x118008094d2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6751"            ,	   0x118008094d2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6752"            ,	   0x118008094d300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6753"            ,	   0x118008094d308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6754"            ,	   0x118008094d310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6755"            ,	   0x118008094d318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6756"            ,	   0x118008094d320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6757"            ,	   0x118008094d328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6758"            ,	   0x118008094d330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6759"            ,	   0x118008094d338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6760"            ,	   0x118008094d340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6761"            ,	   0x118008094d348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6762"            ,	   0x118008094d350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6763"            ,	   0x118008094d358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6764"            ,	   0x118008094d360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6765"            ,	   0x118008094d368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6766"            ,	   0x118008094d370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6767"            ,	   0x118008094d378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6768"            ,	   0x118008094d380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6769"            ,	   0x118008094d388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6770"            ,	   0x118008094d390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6771"            ,	   0x118008094d398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6772"            ,	   0x118008094d3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6773"            ,	   0x118008094d3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6774"            ,	   0x118008094d3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6775"            ,	   0x118008094d3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6776"            ,	   0x118008094d3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6777"            ,	   0x118008094d3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6778"            ,	   0x118008094d3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6779"            ,	   0x118008094d3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6780"            ,	   0x118008094d3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6781"            ,	   0x118008094d3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6782"            ,	   0x118008094d3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6783"            ,	   0x118008094d3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6784"            ,	   0x118008094d400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6785"            ,	   0x118008094d408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6786"            ,	   0x118008094d410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6787"            ,	   0x118008094d418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6788"            ,	   0x118008094d420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6789"            ,	   0x118008094d428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6790"            ,	   0x118008094d430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6791"            ,	   0x118008094d438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6792"            ,	   0x118008094d440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6793"            ,	   0x118008094d448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6794"            ,	   0x118008094d450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6795"            ,	   0x118008094d458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6796"            ,	   0x118008094d460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6797"            ,	   0x118008094d468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6798"            ,	   0x118008094d470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6799"            ,	   0x118008094d478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6800"            ,	   0x118008094d480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6801"            ,	   0x118008094d488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6802"            ,	   0x118008094d490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6803"            ,	   0x118008094d498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6804"            ,	   0x118008094d4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6805"            ,	   0x118008094d4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6806"            ,	   0x118008094d4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6807"            ,	   0x118008094d4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6808"            ,	   0x118008094d4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6809"            ,	   0x118008094d4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6810"            ,	   0x118008094d4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6811"            ,	   0x118008094d4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6812"            ,	   0x118008094d4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6813"            ,	   0x118008094d4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6814"            ,	   0x118008094d4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6815"            ,	   0x118008094d4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6816"            ,	   0x118008094d500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6817"            ,	   0x118008094d508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6818"            ,	   0x118008094d510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6819"            ,	   0x118008094d518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6820"            ,	   0x118008094d520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6821"            ,	   0x118008094d528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6822"            ,	   0x118008094d530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6823"            ,	   0x118008094d538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6824"            ,	   0x118008094d540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6825"            ,	   0x118008094d548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6826"            ,	   0x118008094d550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6827"            ,	   0x118008094d558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6828"            ,	   0x118008094d560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6829"            ,	   0x118008094d568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6830"            ,	   0x118008094d570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6831"            ,	   0x118008094d578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6832"            ,	   0x118008094d580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6833"            ,	   0x118008094d588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6834"            ,	   0x118008094d590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6835"            ,	   0x118008094d598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6836"            ,	   0x118008094d5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6837"            ,	   0x118008094d5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6838"            ,	   0x118008094d5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6839"            ,	   0x118008094d5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6840"            ,	   0x118008094d5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6841"            ,	   0x118008094d5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6842"            ,	   0x118008094d5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6843"            ,	   0x118008094d5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6844"            ,	   0x118008094d5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6845"            ,	   0x118008094d5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6846"            ,	   0x118008094d5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6847"            ,	   0x118008094d5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6848"            ,	   0x118008094d600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6849"            ,	   0x118008094d608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6850"            ,	   0x118008094d610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6851"            ,	   0x118008094d618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6852"            ,	   0x118008094d620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6853"            ,	   0x118008094d628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6854"            ,	   0x118008094d630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6855"            ,	   0x118008094d638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6856"            ,	   0x118008094d640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6857"            ,	   0x118008094d648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6858"            ,	   0x118008094d650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6859"            ,	   0x118008094d658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6860"            ,	   0x118008094d660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6861"            ,	   0x118008094d668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6862"            ,	   0x118008094d670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6863"            ,	   0x118008094d678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6864"            ,	   0x118008094d680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6865"            ,	   0x118008094d688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6866"            ,	   0x118008094d690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6867"            ,	   0x118008094d698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6868"            ,	   0x118008094d6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6869"            ,	   0x118008094d6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6870"            ,	   0x118008094d6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6871"            ,	   0x118008094d6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6872"            ,	   0x118008094d6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6873"            ,	   0x118008094d6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6874"            ,	   0x118008094d6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6875"            ,	   0x118008094d6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6876"            ,	   0x118008094d6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6877"            ,	   0x118008094d6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6878"            ,	   0x118008094d6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6879"            ,	   0x118008094d6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6880"            ,	   0x118008094d700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6881"            ,	   0x118008094d708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6882"            ,	   0x118008094d710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6883"            ,	   0x118008094d718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6884"            ,	   0x118008094d720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6885"            ,	   0x118008094d728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6886"            ,	   0x118008094d730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6887"            ,	   0x118008094d738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6888"            ,	   0x118008094d740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6889"            ,	   0x118008094d748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6890"            ,	   0x118008094d750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6891"            ,	   0x118008094d758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6892"            ,	   0x118008094d760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6893"            ,	   0x118008094d768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6894"            ,	   0x118008094d770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6895"            ,	   0x118008094d778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6896"            ,	   0x118008094d780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6897"            ,	   0x118008094d788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6898"            ,	   0x118008094d790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6899"            ,	   0x118008094d798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6900"            ,	   0x118008094d7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6901"            ,	   0x118008094d7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6902"            ,	   0x118008094d7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6903"            ,	   0x118008094d7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6904"            ,	   0x118008094d7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6905"            ,	   0x118008094d7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6906"            ,	   0x118008094d7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6907"            ,	   0x118008094d7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6908"            ,	   0x118008094d7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6909"            ,	   0x118008094d7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6910"            ,	   0x118008094d7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6911"            ,	   0x118008094d7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6912"            ,	   0x118008094d800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6913"            ,	   0x118008094d808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6914"            ,	   0x118008094d810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6915"            ,	   0x118008094d818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6916"            ,	   0x118008094d820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6917"            ,	   0x118008094d828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6918"            ,	   0x118008094d830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6919"            ,	   0x118008094d838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6920"            ,	   0x118008094d840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6921"            ,	   0x118008094d848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6922"            ,	   0x118008094d850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6923"            ,	   0x118008094d858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6924"            ,	   0x118008094d860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6925"            ,	   0x118008094d868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6926"            ,	   0x118008094d870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6927"            ,	   0x118008094d878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6928"            ,	   0x118008094d880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6929"            ,	   0x118008094d888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6930"            ,	   0x118008094d890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6931"            ,	   0x118008094d898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6932"            ,	   0x118008094d8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6933"            ,	   0x118008094d8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6934"            ,	   0x118008094d8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6935"            ,	   0x118008094d8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6936"            ,	   0x118008094d8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6937"            ,	   0x118008094d8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6938"            ,	   0x118008094d8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6939"            ,	   0x118008094d8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6940"            ,	   0x118008094d8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6941"            ,	   0x118008094d8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6942"            ,	   0x118008094d8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6943"            ,	   0x118008094d8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6944"            ,	   0x118008094d900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6945"            ,	   0x118008094d908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6946"            ,	   0x118008094d910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6947"            ,	   0x118008094d918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6948"            ,	   0x118008094d920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6949"            ,	   0x118008094d928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6950"            ,	   0x118008094d930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6951"            ,	   0x118008094d938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6952"            ,	   0x118008094d940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6953"            ,	   0x118008094d948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6954"            ,	   0x118008094d950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6955"            ,	   0x118008094d958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6956"            ,	   0x118008094d960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6957"            ,	   0x118008094d968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6958"            ,	   0x118008094d970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6959"            ,	   0x118008094d978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6960"            ,	   0x118008094d980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6961"            ,	   0x118008094d988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6962"            ,	   0x118008094d990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6963"            ,	   0x118008094d998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6964"            ,	   0x118008094d9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6965"            ,	   0x118008094d9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6966"            ,	   0x118008094d9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6967"            ,	   0x118008094d9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6968"            ,	   0x118008094d9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6969"            ,	   0x118008094d9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6970"            ,	   0x118008094d9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6971"            ,	   0x118008094d9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6972"            ,	   0x118008094d9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6973"            ,	   0x118008094d9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6974"            ,	   0x118008094d9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6975"            ,	   0x118008094d9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6976"            ,	   0x118008094da00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6977"            ,	   0x118008094da08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6978"            ,	   0x118008094da10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6979"            ,	   0x118008094da18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6980"            ,	   0x118008094da20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6981"            ,	   0x118008094da28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6982"            ,	   0x118008094da30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6983"            ,	   0x118008094da38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6984"            ,	   0x118008094da40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6985"            ,	   0x118008094da48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6986"            ,	   0x118008094da50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6987"            ,	   0x118008094da58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6988"            ,	   0x118008094da60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6989"            ,	   0x118008094da68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6990"            ,	   0x118008094da70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6991"            ,	   0x118008094da78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6992"            ,	   0x118008094da80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6993"            ,	   0x118008094da88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6994"            ,	   0x118008094da90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6995"            ,	   0x118008094da98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6996"            ,	   0x118008094daa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6997"            ,	   0x118008094daa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6998"            ,	   0x118008094dab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP6999"            ,	   0x118008094dab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7000"            ,	   0x118008094dac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7001"            ,	   0x118008094dac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7002"            ,	   0x118008094dad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7003"            ,	   0x118008094dad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7004"            ,	   0x118008094dae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7005"            ,	   0x118008094dae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7006"            ,	   0x118008094daf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7007"            ,	   0x118008094daf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7008"            ,	   0x118008094db00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7009"            ,	   0x118008094db08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7010"            ,	   0x118008094db10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7011"            ,	   0x118008094db18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7012"            ,	   0x118008094db20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7013"            ,	   0x118008094db28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7014"            ,	   0x118008094db30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7015"            ,	   0x118008094db38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7016"            ,	   0x118008094db40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7017"            ,	   0x118008094db48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7018"            ,	   0x118008094db50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7019"            ,	   0x118008094db58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7020"            ,	   0x118008094db60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7021"            ,	   0x118008094db68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7022"            ,	   0x118008094db70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7023"            ,	   0x118008094db78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7024"            ,	   0x118008094db80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7025"            ,	   0x118008094db88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7026"            ,	   0x118008094db90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7027"            ,	   0x118008094db98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7028"            ,	   0x118008094dba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7029"            ,	   0x118008094dba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7030"            ,	   0x118008094dbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7031"            ,	   0x118008094dbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7032"            ,	   0x118008094dbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7033"            ,	   0x118008094dbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7034"            ,	   0x118008094dbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7035"            ,	   0x118008094dbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7036"            ,	   0x118008094dbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7037"            ,	   0x118008094dbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7038"            ,	   0x118008094dbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7039"            ,	   0x118008094dbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7040"            ,	   0x118008094dc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7041"            ,	   0x118008094dc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7042"            ,	   0x118008094dc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7043"            ,	   0x118008094dc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7044"            ,	   0x118008094dc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7045"            ,	   0x118008094dc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7046"            ,	   0x118008094dc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7047"            ,	   0x118008094dc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7048"            ,	   0x118008094dc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7049"            ,	   0x118008094dc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7050"            ,	   0x118008094dc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7051"            ,	   0x118008094dc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7052"            ,	   0x118008094dc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7053"            ,	   0x118008094dc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7054"            ,	   0x118008094dc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7055"            ,	   0x118008094dc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7056"            ,	   0x118008094dc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7057"            ,	   0x118008094dc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7058"            ,	   0x118008094dc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7059"            ,	   0x118008094dc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7060"            ,	   0x118008094dca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7061"            ,	   0x118008094dca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7062"            ,	   0x118008094dcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7063"            ,	   0x118008094dcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7064"            ,	   0x118008094dcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7065"            ,	   0x118008094dcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7066"            ,	   0x118008094dcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7067"            ,	   0x118008094dcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7068"            ,	   0x118008094dce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7069"            ,	   0x118008094dce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7070"            ,	   0x118008094dcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7071"            ,	   0x118008094dcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7072"            ,	   0x118008094dd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7073"            ,	   0x118008094dd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7074"            ,	   0x118008094dd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7075"            ,	   0x118008094dd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7076"            ,	   0x118008094dd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7077"            ,	   0x118008094dd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7078"            ,	   0x118008094dd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7079"            ,	   0x118008094dd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7080"            ,	   0x118008094dd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7081"            ,	   0x118008094dd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7082"            ,	   0x118008094dd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7083"            ,	   0x118008094dd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7084"            ,	   0x118008094dd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7085"            ,	   0x118008094dd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7086"            ,	   0x118008094dd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7087"            ,	   0x118008094dd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7088"            ,	   0x118008094dd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7089"            ,	   0x118008094dd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7090"            ,	   0x118008094dd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7091"            ,	   0x118008094dd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7092"            ,	   0x118008094dda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7093"            ,	   0x118008094dda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7094"            ,	   0x118008094ddb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7095"            ,	   0x118008094ddb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7096"            ,	   0x118008094ddc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7097"            ,	   0x118008094ddc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7098"            ,	   0x118008094ddd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7099"            ,	   0x118008094ddd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7100"            ,	   0x118008094dde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7101"            ,	   0x118008094dde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7102"            ,	   0x118008094ddf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7103"            ,	   0x118008094ddf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7104"            ,	   0x118008094de00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7105"            ,	   0x118008094de08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7106"            ,	   0x118008094de10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7107"            ,	   0x118008094de18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7108"            ,	   0x118008094de20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7109"            ,	   0x118008094de28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7110"            ,	   0x118008094de30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7111"            ,	   0x118008094de38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7112"            ,	   0x118008094de40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7113"            ,	   0x118008094de48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7114"            ,	   0x118008094de50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7115"            ,	   0x118008094de58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7116"            ,	   0x118008094de60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7117"            ,	   0x118008094de68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7118"            ,	   0x118008094de70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7119"            ,	   0x118008094de78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7120"            ,	   0x118008094de80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7121"            ,	   0x118008094de88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7122"            ,	   0x118008094de90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7123"            ,	   0x118008094de98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7124"            ,	   0x118008094dea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7125"            ,	   0x118008094dea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7126"            ,	   0x118008094deb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7127"            ,	   0x118008094deb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7128"            ,	   0x118008094dec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7129"            ,	   0x118008094dec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7130"            ,	   0x118008094ded0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7131"            ,	   0x118008094ded8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7132"            ,	   0x118008094dee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7133"            ,	   0x118008094dee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7134"            ,	   0x118008094def0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7135"            ,	   0x118008094def8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7136"            ,	   0x118008094df00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7137"            ,	   0x118008094df08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7138"            ,	   0x118008094df10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7139"            ,	   0x118008094df18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7140"            ,	   0x118008094df20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7141"            ,	   0x118008094df28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7142"            ,	   0x118008094df30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7143"            ,	   0x118008094df38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7144"            ,	   0x118008094df40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7145"            ,	   0x118008094df48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7146"            ,	   0x118008094df50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7147"            ,	   0x118008094df58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7148"            ,	   0x118008094df60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7149"            ,	   0x118008094df68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7150"            ,	   0x118008094df70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7151"            ,	   0x118008094df78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7152"            ,	   0x118008094df80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7153"            ,	   0x118008094df88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7154"            ,	   0x118008094df90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7155"            ,	   0x118008094df98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7156"            ,	   0x118008094dfa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7157"            ,	   0x118008094dfa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7158"            ,	   0x118008094dfb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7159"            ,	   0x118008094dfb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7160"            ,	   0x118008094dfc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7161"            ,	   0x118008094dfc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7162"            ,	   0x118008094dfd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7163"            ,	   0x118008094dfd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7164"            ,	   0x118008094dfe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7165"            ,	   0x118008094dfe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7166"            ,	   0x118008094dff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7167"            ,	   0x118008094dff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7168"            ,	   0x118008094e000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7169"            ,	   0x118008094e008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7170"            ,	   0x118008094e010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7171"            ,	   0x118008094e018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7172"            ,	   0x118008094e020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7173"            ,	   0x118008094e028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7174"            ,	   0x118008094e030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7175"            ,	   0x118008094e038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7176"            ,	   0x118008094e040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7177"            ,	   0x118008094e048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7178"            ,	   0x118008094e050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7179"            ,	   0x118008094e058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7180"            ,	   0x118008094e060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7181"            ,	   0x118008094e068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7182"            ,	   0x118008094e070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7183"            ,	   0x118008094e078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7184"            ,	   0x118008094e080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7185"            ,	   0x118008094e088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7186"            ,	   0x118008094e090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7187"            ,	   0x118008094e098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7188"            ,	   0x118008094e0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7189"            ,	   0x118008094e0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7190"            ,	   0x118008094e0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7191"            ,	   0x118008094e0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7192"            ,	   0x118008094e0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7193"            ,	   0x118008094e0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7194"            ,	   0x118008094e0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7195"            ,	   0x118008094e0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7196"            ,	   0x118008094e0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7197"            ,	   0x118008094e0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7198"            ,	   0x118008094e0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7199"            ,	   0x118008094e0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7200"            ,	   0x118008094e100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7201"            ,	   0x118008094e108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7202"            ,	   0x118008094e110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7203"            ,	   0x118008094e118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7204"            ,	   0x118008094e120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7205"            ,	   0x118008094e128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7206"            ,	   0x118008094e130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7207"            ,	   0x118008094e138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7208"            ,	   0x118008094e140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7209"            ,	   0x118008094e148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7210"            ,	   0x118008094e150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7211"            ,	   0x118008094e158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7212"            ,	   0x118008094e160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7213"            ,	   0x118008094e168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7214"            ,	   0x118008094e170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7215"            ,	   0x118008094e178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7216"            ,	   0x118008094e180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7217"            ,	   0x118008094e188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7218"            ,	   0x118008094e190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7219"            ,	   0x118008094e198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7220"            ,	   0x118008094e1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7221"            ,	   0x118008094e1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7222"            ,	   0x118008094e1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7223"            ,	   0x118008094e1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7224"            ,	   0x118008094e1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7225"            ,	   0x118008094e1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7226"            ,	   0x118008094e1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7227"            ,	   0x118008094e1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7228"            ,	   0x118008094e1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7229"            ,	   0x118008094e1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7230"            ,	   0x118008094e1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7231"            ,	   0x118008094e1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7232"            ,	   0x118008094e200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7233"            ,	   0x118008094e208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7234"            ,	   0x118008094e210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7235"            ,	   0x118008094e218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7236"            ,	   0x118008094e220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7237"            ,	   0x118008094e228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7238"            ,	   0x118008094e230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7239"            ,	   0x118008094e238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7240"            ,	   0x118008094e240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7241"            ,	   0x118008094e248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7242"            ,	   0x118008094e250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7243"            ,	   0x118008094e258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7244"            ,	   0x118008094e260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7245"            ,	   0x118008094e268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7246"            ,	   0x118008094e270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7247"            ,	   0x118008094e278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7248"            ,	   0x118008094e280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7249"            ,	   0x118008094e288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7250"            ,	   0x118008094e290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7251"            ,	   0x118008094e298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7252"            ,	   0x118008094e2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7253"            ,	   0x118008094e2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7254"            ,	   0x118008094e2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7255"            ,	   0x118008094e2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7256"            ,	   0x118008094e2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7257"            ,	   0x118008094e2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7258"            ,	   0x118008094e2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7259"            ,	   0x118008094e2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7260"            ,	   0x118008094e2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7261"            ,	   0x118008094e2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7262"            ,	   0x118008094e2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7263"            ,	   0x118008094e2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7264"            ,	   0x118008094e300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7265"            ,	   0x118008094e308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7266"            ,	   0x118008094e310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7267"            ,	   0x118008094e318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7268"            ,	   0x118008094e320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7269"            ,	   0x118008094e328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7270"            ,	   0x118008094e330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7271"            ,	   0x118008094e338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7272"            ,	   0x118008094e340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7273"            ,	   0x118008094e348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7274"            ,	   0x118008094e350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7275"            ,	   0x118008094e358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7276"            ,	   0x118008094e360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7277"            ,	   0x118008094e368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7278"            ,	   0x118008094e370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7279"            ,	   0x118008094e378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7280"            ,	   0x118008094e380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7281"            ,	   0x118008094e388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7282"            ,	   0x118008094e390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7283"            ,	   0x118008094e398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7284"            ,	   0x118008094e3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7285"            ,	   0x118008094e3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7286"            ,	   0x118008094e3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7287"            ,	   0x118008094e3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7288"            ,	   0x118008094e3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7289"            ,	   0x118008094e3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7290"            ,	   0x118008094e3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7291"            ,	   0x118008094e3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7292"            ,	   0x118008094e3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7293"            ,	   0x118008094e3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7294"            ,	   0x118008094e3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7295"            ,	   0x118008094e3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7296"            ,	   0x118008094e400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7297"            ,	   0x118008094e408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7298"            ,	   0x118008094e410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7299"            ,	   0x118008094e418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7300"            ,	   0x118008094e420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7301"            ,	   0x118008094e428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7302"            ,	   0x118008094e430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7303"            ,	   0x118008094e438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7304"            ,	   0x118008094e440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7305"            ,	   0x118008094e448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7306"            ,	   0x118008094e450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7307"            ,	   0x118008094e458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7308"            ,	   0x118008094e460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7309"            ,	   0x118008094e468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7310"            ,	   0x118008094e470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7311"            ,	   0x118008094e478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7312"            ,	   0x118008094e480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7313"            ,	   0x118008094e488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7314"            ,	   0x118008094e490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7315"            ,	   0x118008094e498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7316"            ,	   0x118008094e4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7317"            ,	   0x118008094e4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7318"            ,	   0x118008094e4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7319"            ,	   0x118008094e4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7320"            ,	   0x118008094e4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7321"            ,	   0x118008094e4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7322"            ,	   0x118008094e4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7323"            ,	   0x118008094e4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7324"            ,	   0x118008094e4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7325"            ,	   0x118008094e4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7326"            ,	   0x118008094e4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7327"            ,	   0x118008094e4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7328"            ,	   0x118008094e500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7329"            ,	   0x118008094e508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7330"            ,	   0x118008094e510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7331"            ,	   0x118008094e518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7332"            ,	   0x118008094e520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7333"            ,	   0x118008094e528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7334"            ,	   0x118008094e530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7335"            ,	   0x118008094e538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7336"            ,	   0x118008094e540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7337"            ,	   0x118008094e548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7338"            ,	   0x118008094e550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7339"            ,	   0x118008094e558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7340"            ,	   0x118008094e560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7341"            ,	   0x118008094e568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7342"            ,	   0x118008094e570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7343"            ,	   0x118008094e578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7344"            ,	   0x118008094e580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7345"            ,	   0x118008094e588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7346"            ,	   0x118008094e590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7347"            ,	   0x118008094e598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7348"            ,	   0x118008094e5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7349"            ,	   0x118008094e5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7350"            ,	   0x118008094e5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7351"            ,	   0x118008094e5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7352"            ,	   0x118008094e5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7353"            ,	   0x118008094e5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7354"            ,	   0x118008094e5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7355"            ,	   0x118008094e5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7356"            ,	   0x118008094e5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7357"            ,	   0x118008094e5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7358"            ,	   0x118008094e5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7359"            ,	   0x118008094e5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7360"            ,	   0x118008094e600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7361"            ,	   0x118008094e608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7362"            ,	   0x118008094e610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7363"            ,	   0x118008094e618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7364"            ,	   0x118008094e620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7365"            ,	   0x118008094e628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7366"            ,	   0x118008094e630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7367"            ,	   0x118008094e638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7368"            ,	   0x118008094e640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7369"            ,	   0x118008094e648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7370"            ,	   0x118008094e650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7371"            ,	   0x118008094e658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7372"            ,	   0x118008094e660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7373"            ,	   0x118008094e668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7374"            ,	   0x118008094e670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7375"            ,	   0x118008094e678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7376"            ,	   0x118008094e680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7377"            ,	   0x118008094e688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7378"            ,	   0x118008094e690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7379"            ,	   0x118008094e698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7380"            ,	   0x118008094e6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7381"            ,	   0x118008094e6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7382"            ,	   0x118008094e6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7383"            ,	   0x118008094e6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7384"            ,	   0x118008094e6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7385"            ,	   0x118008094e6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7386"            ,	   0x118008094e6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7387"            ,	   0x118008094e6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7388"            ,	   0x118008094e6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7389"            ,	   0x118008094e6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7390"            ,	   0x118008094e6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7391"            ,	   0x118008094e6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7392"            ,	   0x118008094e700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7393"            ,	   0x118008094e708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7394"            ,	   0x118008094e710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7395"            ,	   0x118008094e718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7396"            ,	   0x118008094e720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7397"            ,	   0x118008094e728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7398"            ,	   0x118008094e730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7399"            ,	   0x118008094e738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7400"            ,	   0x118008094e740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7401"            ,	   0x118008094e748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7402"            ,	   0x118008094e750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7403"            ,	   0x118008094e758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7404"            ,	   0x118008094e760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7405"            ,	   0x118008094e768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7406"            ,	   0x118008094e770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7407"            ,	   0x118008094e778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7408"            ,	   0x118008094e780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7409"            ,	   0x118008094e788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7410"            ,	   0x118008094e790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7411"            ,	   0x118008094e798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7412"            ,	   0x118008094e7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7413"            ,	   0x118008094e7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7414"            ,	   0x118008094e7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7415"            ,	   0x118008094e7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7416"            ,	   0x118008094e7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7417"            ,	   0x118008094e7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7418"            ,	   0x118008094e7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7419"            ,	   0x118008094e7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7420"            ,	   0x118008094e7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7421"            ,	   0x118008094e7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7422"            ,	   0x118008094e7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7423"            ,	   0x118008094e7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7424"            ,	   0x118008094e800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7425"            ,	   0x118008094e808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7426"            ,	   0x118008094e810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7427"            ,	   0x118008094e818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7428"            ,	   0x118008094e820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7429"            ,	   0x118008094e828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7430"            ,	   0x118008094e830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7431"            ,	   0x118008094e838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7432"            ,	   0x118008094e840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7433"            ,	   0x118008094e848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7434"            ,	   0x118008094e850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7435"            ,	   0x118008094e858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7436"            ,	   0x118008094e860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7437"            ,	   0x118008094e868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7438"            ,	   0x118008094e870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7439"            ,	   0x118008094e878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7440"            ,	   0x118008094e880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7441"            ,	   0x118008094e888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7442"            ,	   0x118008094e890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7443"            ,	   0x118008094e898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7444"            ,	   0x118008094e8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7445"            ,	   0x118008094e8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7446"            ,	   0x118008094e8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7447"            ,	   0x118008094e8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7448"            ,	   0x118008094e8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7449"            ,	   0x118008094e8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7450"            ,	   0x118008094e8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7451"            ,	   0x118008094e8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7452"            ,	   0x118008094e8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7453"            ,	   0x118008094e8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7454"            ,	   0x118008094e8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7455"            ,	   0x118008094e8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7456"            ,	   0x118008094e900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7457"            ,	   0x118008094e908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7458"            ,	   0x118008094e910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7459"            ,	   0x118008094e918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7460"            ,	   0x118008094e920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7461"            ,	   0x118008094e928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7462"            ,	   0x118008094e930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7463"            ,	   0x118008094e938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7464"            ,	   0x118008094e940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7465"            ,	   0x118008094e948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7466"            ,	   0x118008094e950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7467"            ,	   0x118008094e958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7468"            ,	   0x118008094e960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7469"            ,	   0x118008094e968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7470"            ,	   0x118008094e970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7471"            ,	   0x118008094e978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7472"            ,	   0x118008094e980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7473"            ,	   0x118008094e988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7474"            ,	   0x118008094e990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7475"            ,	   0x118008094e998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7476"            ,	   0x118008094e9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7477"            ,	   0x118008094e9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7478"            ,	   0x118008094e9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7479"            ,	   0x118008094e9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7480"            ,	   0x118008094e9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7481"            ,	   0x118008094e9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7482"            ,	   0x118008094e9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7483"            ,	   0x118008094e9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7484"            ,	   0x118008094e9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7485"            ,	   0x118008094e9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7486"            ,	   0x118008094e9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7487"            ,	   0x118008094e9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7488"            ,	   0x118008094ea00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7489"            ,	   0x118008094ea08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7490"            ,	   0x118008094ea10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7491"            ,	   0x118008094ea18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7492"            ,	   0x118008094ea20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7493"            ,	   0x118008094ea28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7494"            ,	   0x118008094ea30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7495"            ,	   0x118008094ea38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7496"            ,	   0x118008094ea40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7497"            ,	   0x118008094ea48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7498"            ,	   0x118008094ea50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7499"            ,	   0x118008094ea58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7500"            ,	   0x118008094ea60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7501"            ,	   0x118008094ea68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7502"            ,	   0x118008094ea70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7503"            ,	   0x118008094ea78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7504"            ,	   0x118008094ea80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7505"            ,	   0x118008094ea88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7506"            ,	   0x118008094ea90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7507"            ,	   0x118008094ea98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7508"            ,	   0x118008094eaa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7509"            ,	   0x118008094eaa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7510"            ,	   0x118008094eab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7511"            ,	   0x118008094eab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7512"            ,	   0x118008094eac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7513"            ,	   0x118008094eac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7514"            ,	   0x118008094ead0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7515"            ,	   0x118008094ead8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7516"            ,	   0x118008094eae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7517"            ,	   0x118008094eae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7518"            ,	   0x118008094eaf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7519"            ,	   0x118008094eaf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7520"            ,	   0x118008094eb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7521"            ,	   0x118008094eb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7522"            ,	   0x118008094eb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7523"            ,	   0x118008094eb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7524"            ,	   0x118008094eb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7525"            ,	   0x118008094eb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7526"            ,	   0x118008094eb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7527"            ,	   0x118008094eb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7528"            ,	   0x118008094eb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7529"            ,	   0x118008094eb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7530"            ,	   0x118008094eb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7531"            ,	   0x118008094eb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7532"            ,	   0x118008094eb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7533"            ,	   0x118008094eb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7534"            ,	   0x118008094eb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7535"            ,	   0x118008094eb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7536"            ,	   0x118008094eb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7537"            ,	   0x118008094eb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7538"            ,	   0x118008094eb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7539"            ,	   0x118008094eb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7540"            ,	   0x118008094eba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7541"            ,	   0x118008094eba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7542"            ,	   0x118008094ebb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7543"            ,	   0x118008094ebb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7544"            ,	   0x118008094ebc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7545"            ,	   0x118008094ebc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7546"            ,	   0x118008094ebd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7547"            ,	   0x118008094ebd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7548"            ,	   0x118008094ebe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7549"            ,	   0x118008094ebe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7550"            ,	   0x118008094ebf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7551"            ,	   0x118008094ebf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7552"            ,	   0x118008094ec00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7553"            ,	   0x118008094ec08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7554"            ,	   0x118008094ec10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7555"            ,	   0x118008094ec18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7556"            ,	   0x118008094ec20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7557"            ,	   0x118008094ec28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7558"            ,	   0x118008094ec30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7559"            ,	   0x118008094ec38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7560"            ,	   0x118008094ec40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7561"            ,	   0x118008094ec48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7562"            ,	   0x118008094ec50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7563"            ,	   0x118008094ec58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7564"            ,	   0x118008094ec60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7565"            ,	   0x118008094ec68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7566"            ,	   0x118008094ec70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7567"            ,	   0x118008094ec78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7568"            ,	   0x118008094ec80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7569"            ,	   0x118008094ec88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7570"            ,	   0x118008094ec90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7571"            ,	   0x118008094ec98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7572"            ,	   0x118008094eca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7573"            ,	   0x118008094eca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7574"            ,	   0x118008094ecb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7575"            ,	   0x118008094ecb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7576"            ,	   0x118008094ecc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7577"            ,	   0x118008094ecc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7578"            ,	   0x118008094ecd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7579"            ,	   0x118008094ecd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7580"            ,	   0x118008094ece0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7581"            ,	   0x118008094ece8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7582"            ,	   0x118008094ecf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7583"            ,	   0x118008094ecf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7584"            ,	   0x118008094ed00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7585"            ,	   0x118008094ed08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7586"            ,	   0x118008094ed10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7587"            ,	   0x118008094ed18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7588"            ,	   0x118008094ed20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7589"            ,	   0x118008094ed28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7590"            ,	   0x118008094ed30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7591"            ,	   0x118008094ed38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7592"            ,	   0x118008094ed40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7593"            ,	   0x118008094ed48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7594"            ,	   0x118008094ed50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7595"            ,	   0x118008094ed58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7596"            ,	   0x118008094ed60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7597"            ,	   0x118008094ed68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7598"            ,	   0x118008094ed70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7599"            ,	   0x118008094ed78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7600"            ,	   0x118008094ed80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7601"            ,	   0x118008094ed88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7602"            ,	   0x118008094ed90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7603"            ,	   0x118008094ed98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7604"            ,	   0x118008094eda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7605"            ,	   0x118008094eda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7606"            ,	   0x118008094edb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7607"            ,	   0x118008094edb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7608"            ,	   0x118008094edc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7609"            ,	   0x118008094edc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7610"            ,	   0x118008094edd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7611"            ,	   0x118008094edd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7612"            ,	   0x118008094ede0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7613"            ,	   0x118008094ede8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7614"            ,	   0x118008094edf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7615"            ,	   0x118008094edf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7616"            ,	   0x118008094ee00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7617"            ,	   0x118008094ee08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7618"            ,	   0x118008094ee10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7619"            ,	   0x118008094ee18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7620"            ,	   0x118008094ee20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7621"            ,	   0x118008094ee28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7622"            ,	   0x118008094ee30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7623"            ,	   0x118008094ee38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7624"            ,	   0x118008094ee40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7625"            ,	   0x118008094ee48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7626"            ,	   0x118008094ee50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7627"            ,	   0x118008094ee58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7628"            ,	   0x118008094ee60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7629"            ,	   0x118008094ee68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7630"            ,	   0x118008094ee70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7631"            ,	   0x118008094ee78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7632"            ,	   0x118008094ee80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7633"            ,	   0x118008094ee88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7634"            ,	   0x118008094ee90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7635"            ,	   0x118008094ee98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7636"            ,	   0x118008094eea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7637"            ,	   0x118008094eea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7638"            ,	   0x118008094eeb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7639"            ,	   0x118008094eeb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7640"            ,	   0x118008094eec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7641"            ,	   0x118008094eec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7642"            ,	   0x118008094eed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7643"            ,	   0x118008094eed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7644"            ,	   0x118008094eee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7645"            ,	   0x118008094eee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7646"            ,	   0x118008094eef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7647"            ,	   0x118008094eef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7648"            ,	   0x118008094ef00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7649"            ,	   0x118008094ef08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7650"            ,	   0x118008094ef10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7651"            ,	   0x118008094ef18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7652"            ,	   0x118008094ef20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7653"            ,	   0x118008094ef28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7654"            ,	   0x118008094ef30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7655"            ,	   0x118008094ef38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7656"            ,	   0x118008094ef40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7657"            ,	   0x118008094ef48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7658"            ,	   0x118008094ef50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7659"            ,	   0x118008094ef58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7660"            ,	   0x118008094ef60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7661"            ,	   0x118008094ef68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7662"            ,	   0x118008094ef70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7663"            ,	   0x118008094ef78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7664"            ,	   0x118008094ef80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7665"            ,	   0x118008094ef88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7666"            ,	   0x118008094ef90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7667"            ,	   0x118008094ef98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7668"            ,	   0x118008094efa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7669"            ,	   0x118008094efa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7670"            ,	   0x118008094efb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7671"            ,	   0x118008094efb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7672"            ,	   0x118008094efc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7673"            ,	   0x118008094efc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7674"            ,	   0x118008094efd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7675"            ,	   0x118008094efd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7676"            ,	   0x118008094efe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7677"            ,	   0x118008094efe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7678"            ,	   0x118008094eff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7679"            ,	   0x118008094eff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7680"            ,	   0x118008094f000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7681"            ,	   0x118008094f008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7682"            ,	   0x118008094f010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7683"            ,	   0x118008094f018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7684"            ,	   0x118008094f020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7685"            ,	   0x118008094f028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7686"            ,	   0x118008094f030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7687"            ,	   0x118008094f038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7688"            ,	   0x118008094f040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7689"            ,	   0x118008094f048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7690"            ,	   0x118008094f050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7691"            ,	   0x118008094f058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7692"            ,	   0x118008094f060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7693"            ,	   0x118008094f068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7694"            ,	   0x118008094f070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7695"            ,	   0x118008094f078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7696"            ,	   0x118008094f080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7697"            ,	   0x118008094f088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7698"            ,	   0x118008094f090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7699"            ,	   0x118008094f098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7700"            ,	   0x118008094f0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7701"            ,	   0x118008094f0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7702"            ,	   0x118008094f0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7703"            ,	   0x118008094f0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7704"            ,	   0x118008094f0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7705"            ,	   0x118008094f0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7706"            ,	   0x118008094f0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7707"            ,	   0x118008094f0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7708"            ,	   0x118008094f0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7709"            ,	   0x118008094f0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7710"            ,	   0x118008094f0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7711"            ,	   0x118008094f0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7712"            ,	   0x118008094f100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7713"            ,	   0x118008094f108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7714"            ,	   0x118008094f110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7715"            ,	   0x118008094f118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7716"            ,	   0x118008094f120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7717"            ,	   0x118008094f128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7718"            ,	   0x118008094f130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7719"            ,	   0x118008094f138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7720"            ,	   0x118008094f140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7721"            ,	   0x118008094f148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7722"            ,	   0x118008094f150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7723"            ,	   0x118008094f158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7724"            ,	   0x118008094f160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7725"            ,	   0x118008094f168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7726"            ,	   0x118008094f170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7727"            ,	   0x118008094f178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7728"            ,	   0x118008094f180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7729"            ,	   0x118008094f188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7730"            ,	   0x118008094f190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7731"            ,	   0x118008094f198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7732"            ,	   0x118008094f1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7733"            ,	   0x118008094f1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7734"            ,	   0x118008094f1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7735"            ,	   0x118008094f1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7736"            ,	   0x118008094f1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7737"            ,	   0x118008094f1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7738"            ,	   0x118008094f1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7739"            ,	   0x118008094f1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7740"            ,	   0x118008094f1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7741"            ,	   0x118008094f1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7742"            ,	   0x118008094f1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7743"            ,	   0x118008094f1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7744"            ,	   0x118008094f200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7745"            ,	   0x118008094f208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7746"            ,	   0x118008094f210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7747"            ,	   0x118008094f218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7748"            ,	   0x118008094f220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7749"            ,	   0x118008094f228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7750"            ,	   0x118008094f230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7751"            ,	   0x118008094f238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7752"            ,	   0x118008094f240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7753"            ,	   0x118008094f248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7754"            ,	   0x118008094f250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7755"            ,	   0x118008094f258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7756"            ,	   0x118008094f260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7757"            ,	   0x118008094f268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7758"            ,	   0x118008094f270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7759"            ,	   0x118008094f278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7760"            ,	   0x118008094f280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7761"            ,	   0x118008094f288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7762"            ,	   0x118008094f290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7763"            ,	   0x118008094f298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7764"            ,	   0x118008094f2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7765"            ,	   0x118008094f2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7766"            ,	   0x118008094f2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7767"            ,	   0x118008094f2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7768"            ,	   0x118008094f2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7769"            ,	   0x118008094f2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7770"            ,	   0x118008094f2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7771"            ,	   0x118008094f2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7772"            ,	   0x118008094f2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7773"            ,	   0x118008094f2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7774"            ,	   0x118008094f2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7775"            ,	   0x118008094f2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7776"            ,	   0x118008094f300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7777"            ,	   0x118008094f308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7778"            ,	   0x118008094f310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7779"            ,	   0x118008094f318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7780"            ,	   0x118008094f320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7781"            ,	   0x118008094f328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7782"            ,	   0x118008094f330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7783"            ,	   0x118008094f338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7784"            ,	   0x118008094f340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7785"            ,	   0x118008094f348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7786"            ,	   0x118008094f350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7787"            ,	   0x118008094f358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7788"            ,	   0x118008094f360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7789"            ,	   0x118008094f368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7790"            ,	   0x118008094f370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7791"            ,	   0x118008094f378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7792"            ,	   0x118008094f380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7793"            ,	   0x118008094f388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7794"            ,	   0x118008094f390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7795"            ,	   0x118008094f398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7796"            ,	   0x118008094f3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7797"            ,	   0x118008094f3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7798"            ,	   0x118008094f3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7799"            ,	   0x118008094f3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7800"            ,	   0x118008094f3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7801"            ,	   0x118008094f3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7802"            ,	   0x118008094f3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7803"            ,	   0x118008094f3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7804"            ,	   0x118008094f3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7805"            ,	   0x118008094f3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7806"            ,	   0x118008094f3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7807"            ,	   0x118008094f3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7808"            ,	   0x118008094f400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7809"            ,	   0x118008094f408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7810"            ,	   0x118008094f410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7811"            ,	   0x118008094f418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7812"            ,	   0x118008094f420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7813"            ,	   0x118008094f428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7814"            ,	   0x118008094f430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7815"            ,	   0x118008094f438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7816"            ,	   0x118008094f440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7817"            ,	   0x118008094f448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7818"            ,	   0x118008094f450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7819"            ,	   0x118008094f458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7820"            ,	   0x118008094f460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7821"            ,	   0x118008094f468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7822"            ,	   0x118008094f470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7823"            ,	   0x118008094f478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7824"            ,	   0x118008094f480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7825"            ,	   0x118008094f488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7826"            ,	   0x118008094f490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7827"            ,	   0x118008094f498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7828"            ,	   0x118008094f4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7829"            ,	   0x118008094f4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7830"            ,	   0x118008094f4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7831"            ,	   0x118008094f4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7832"            ,	   0x118008094f4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7833"            ,	   0x118008094f4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7834"            ,	   0x118008094f4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7835"            ,	   0x118008094f4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7836"            ,	   0x118008094f4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7837"            ,	   0x118008094f4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7838"            ,	   0x118008094f4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7839"            ,	   0x118008094f4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7840"            ,	   0x118008094f500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7841"            ,	   0x118008094f508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7842"            ,	   0x118008094f510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7843"            ,	   0x118008094f518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7844"            ,	   0x118008094f520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7845"            ,	   0x118008094f528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7846"            ,	   0x118008094f530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7847"            ,	   0x118008094f538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7848"            ,	   0x118008094f540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7849"            ,	   0x118008094f548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7850"            ,	   0x118008094f550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7851"            ,	   0x118008094f558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7852"            ,	   0x118008094f560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7853"            ,	   0x118008094f568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7854"            ,	   0x118008094f570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7855"            ,	   0x118008094f578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7856"            ,	   0x118008094f580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7857"            ,	   0x118008094f588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7858"            ,	   0x118008094f590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7859"            ,	   0x118008094f598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7860"            ,	   0x118008094f5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7861"            ,	   0x118008094f5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7862"            ,	   0x118008094f5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7863"            ,	   0x118008094f5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7864"            ,	   0x118008094f5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7865"            ,	   0x118008094f5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7866"            ,	   0x118008094f5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7867"            ,	   0x118008094f5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7868"            ,	   0x118008094f5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7869"            ,	   0x118008094f5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7870"            ,	   0x118008094f5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7871"            ,	   0x118008094f5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7872"            ,	   0x118008094f600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7873"            ,	   0x118008094f608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7874"            ,	   0x118008094f610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7875"            ,	   0x118008094f618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7876"            ,	   0x118008094f620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7877"            ,	   0x118008094f628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7878"            ,	   0x118008094f630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7879"            ,	   0x118008094f638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7880"            ,	   0x118008094f640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7881"            ,	   0x118008094f648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7882"            ,	   0x118008094f650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7883"            ,	   0x118008094f658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7884"            ,	   0x118008094f660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7885"            ,	   0x118008094f668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7886"            ,	   0x118008094f670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7887"            ,	   0x118008094f678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7888"            ,	   0x118008094f680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7889"            ,	   0x118008094f688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7890"            ,	   0x118008094f690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7891"            ,	   0x118008094f698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7892"            ,	   0x118008094f6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7893"            ,	   0x118008094f6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7894"            ,	   0x118008094f6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7895"            ,	   0x118008094f6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7896"            ,	   0x118008094f6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7897"            ,	   0x118008094f6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7898"            ,	   0x118008094f6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7899"            ,	   0x118008094f6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7900"            ,	   0x118008094f6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7901"            ,	   0x118008094f6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7902"            ,	   0x118008094f6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7903"            ,	   0x118008094f6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7904"            ,	   0x118008094f700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7905"            ,	   0x118008094f708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7906"            ,	   0x118008094f710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7907"            ,	   0x118008094f718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7908"            ,	   0x118008094f720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7909"            ,	   0x118008094f728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7910"            ,	   0x118008094f730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7911"            ,	   0x118008094f738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7912"            ,	   0x118008094f740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7913"            ,	   0x118008094f748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7914"            ,	   0x118008094f750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7915"            ,	   0x118008094f758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7916"            ,	   0x118008094f760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7917"            ,	   0x118008094f768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7918"            ,	   0x118008094f770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7919"            ,	   0x118008094f778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7920"            ,	   0x118008094f780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7921"            ,	   0x118008094f788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7922"            ,	   0x118008094f790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7923"            ,	   0x118008094f798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7924"            ,	   0x118008094f7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7925"            ,	   0x118008094f7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7926"            ,	   0x118008094f7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7927"            ,	   0x118008094f7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7928"            ,	   0x118008094f7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7929"            ,	   0x118008094f7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7930"            ,	   0x118008094f7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7931"            ,	   0x118008094f7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7932"            ,	   0x118008094f7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7933"            ,	   0x118008094f7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7934"            ,	   0x118008094f7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7935"            ,	   0x118008094f7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7936"            ,	   0x118008094f800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7937"            ,	   0x118008094f808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7938"            ,	   0x118008094f810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7939"            ,	   0x118008094f818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7940"            ,	   0x118008094f820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7941"            ,	   0x118008094f828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7942"            ,	   0x118008094f830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7943"            ,	   0x118008094f838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7944"            ,	   0x118008094f840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7945"            ,	   0x118008094f848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7946"            ,	   0x118008094f850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7947"            ,	   0x118008094f858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7948"            ,	   0x118008094f860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7949"            ,	   0x118008094f868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7950"            ,	   0x118008094f870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7951"            ,	   0x118008094f878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7952"            ,	   0x118008094f880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7953"            ,	   0x118008094f888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7954"            ,	   0x118008094f890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7955"            ,	   0x118008094f898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7956"            ,	   0x118008094f8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7957"            ,	   0x118008094f8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7958"            ,	   0x118008094f8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7959"            ,	   0x118008094f8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7960"            ,	   0x118008094f8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7961"            ,	   0x118008094f8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7962"            ,	   0x118008094f8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7963"            ,	   0x118008094f8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7964"            ,	   0x118008094f8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7965"            ,	   0x118008094f8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7966"            ,	   0x118008094f8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7967"            ,	   0x118008094f8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7968"            ,	   0x118008094f900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7969"            ,	   0x118008094f908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7970"            ,	   0x118008094f910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7971"            ,	   0x118008094f918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7972"            ,	   0x118008094f920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7973"            ,	   0x118008094f928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7974"            ,	   0x118008094f930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7975"            ,	   0x118008094f938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7976"            ,	   0x118008094f940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7977"            ,	   0x118008094f948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7978"            ,	   0x118008094f950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7979"            ,	   0x118008094f958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7980"            ,	   0x118008094f960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7981"            ,	   0x118008094f968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7982"            ,	   0x118008094f970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7983"            ,	   0x118008094f978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7984"            ,	   0x118008094f980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7985"            ,	   0x118008094f988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7986"            ,	   0x118008094f990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7987"            ,	   0x118008094f998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7988"            ,	   0x118008094f9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7989"            ,	   0x118008094f9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7990"            ,	   0x118008094f9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7991"            ,	   0x118008094f9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7992"            ,	   0x118008094f9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7993"            ,	   0x118008094f9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7994"            ,	   0x118008094f9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7995"            ,	   0x118008094f9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7996"            ,	   0x118008094f9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7997"            ,	   0x118008094f9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7998"            ,	   0x118008094f9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP7999"            ,	   0x118008094f9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8000"            ,	   0x118008094fa00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8001"            ,	   0x118008094fa08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8002"            ,	   0x118008094fa10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8003"            ,	   0x118008094fa18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8004"            ,	   0x118008094fa20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8005"            ,	   0x118008094fa28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8006"            ,	   0x118008094fa30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8007"            ,	   0x118008094fa38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8008"            ,	   0x118008094fa40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8009"            ,	   0x118008094fa48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8010"            ,	   0x118008094fa50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8011"            ,	   0x118008094fa58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8012"            ,	   0x118008094fa60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8013"            ,	   0x118008094fa68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8014"            ,	   0x118008094fa70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8015"            ,	   0x118008094fa78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8016"            ,	   0x118008094fa80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8017"            ,	   0x118008094fa88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8018"            ,	   0x118008094fa90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8019"            ,	   0x118008094fa98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8020"            ,	   0x118008094faa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8021"            ,	   0x118008094faa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8022"            ,	   0x118008094fab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8023"            ,	   0x118008094fab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8024"            ,	   0x118008094fac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8025"            ,	   0x118008094fac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8026"            ,	   0x118008094fad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8027"            ,	   0x118008094fad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8028"            ,	   0x118008094fae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8029"            ,	   0x118008094fae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8030"            ,	   0x118008094faf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8031"            ,	   0x118008094faf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8032"            ,	   0x118008094fb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8033"            ,	   0x118008094fb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8034"            ,	   0x118008094fb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8035"            ,	   0x118008094fb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8036"            ,	   0x118008094fb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8037"            ,	   0x118008094fb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8038"            ,	   0x118008094fb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8039"            ,	   0x118008094fb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8040"            ,	   0x118008094fb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8041"            ,	   0x118008094fb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8042"            ,	   0x118008094fb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8043"            ,	   0x118008094fb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8044"            ,	   0x118008094fb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8045"            ,	   0x118008094fb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8046"            ,	   0x118008094fb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8047"            ,	   0x118008094fb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8048"            ,	   0x118008094fb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8049"            ,	   0x118008094fb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8050"            ,	   0x118008094fb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8051"            ,	   0x118008094fb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8052"            ,	   0x118008094fba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8053"            ,	   0x118008094fba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8054"            ,	   0x118008094fbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8055"            ,	   0x118008094fbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8056"            ,	   0x118008094fbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8057"            ,	   0x118008094fbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8058"            ,	   0x118008094fbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8059"            ,	   0x118008094fbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8060"            ,	   0x118008094fbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8061"            ,	   0x118008094fbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8062"            ,	   0x118008094fbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8063"            ,	   0x118008094fbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8064"            ,	   0x118008094fc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8065"            ,	   0x118008094fc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8066"            ,	   0x118008094fc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8067"            ,	   0x118008094fc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8068"            ,	   0x118008094fc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8069"            ,	   0x118008094fc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8070"            ,	   0x118008094fc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8071"            ,	   0x118008094fc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8072"            ,	   0x118008094fc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8073"            ,	   0x118008094fc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8074"            ,	   0x118008094fc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8075"            ,	   0x118008094fc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8076"            ,	   0x118008094fc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8077"            ,	   0x118008094fc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8078"            ,	   0x118008094fc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8079"            ,	   0x118008094fc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8080"            ,	   0x118008094fc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8081"            ,	   0x118008094fc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8082"            ,	   0x118008094fc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8083"            ,	   0x118008094fc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8084"            ,	   0x118008094fca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8085"            ,	   0x118008094fca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8086"            ,	   0x118008094fcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8087"            ,	   0x118008094fcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8088"            ,	   0x118008094fcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8089"            ,	   0x118008094fcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8090"            ,	   0x118008094fcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8091"            ,	   0x118008094fcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8092"            ,	   0x118008094fce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8093"            ,	   0x118008094fce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8094"            ,	   0x118008094fcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8095"            ,	   0x118008094fcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8096"            ,	   0x118008094fd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8097"            ,	   0x118008094fd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8098"            ,	   0x118008094fd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8099"            ,	   0x118008094fd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8100"            ,	   0x118008094fd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8101"            ,	   0x118008094fd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8102"            ,	   0x118008094fd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8103"            ,	   0x118008094fd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8104"            ,	   0x118008094fd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8105"            ,	   0x118008094fd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8106"            ,	   0x118008094fd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8107"            ,	   0x118008094fd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8108"            ,	   0x118008094fd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8109"            ,	   0x118008094fd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8110"            ,	   0x118008094fd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8111"            ,	   0x118008094fd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8112"            ,	   0x118008094fd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8113"            ,	   0x118008094fd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8114"            ,	   0x118008094fd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8115"            ,	   0x118008094fd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8116"            ,	   0x118008094fda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8117"            ,	   0x118008094fda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8118"            ,	   0x118008094fdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8119"            ,	   0x118008094fdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8120"            ,	   0x118008094fdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8121"            ,	   0x118008094fdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8122"            ,	   0x118008094fdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8123"            ,	   0x118008094fdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8124"            ,	   0x118008094fde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8125"            ,	   0x118008094fde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8126"            ,	   0x118008094fdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8127"            ,	   0x118008094fdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8128"            ,	   0x118008094fe00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8129"            ,	   0x118008094fe08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8130"            ,	   0x118008094fe10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8131"            ,	   0x118008094fe18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8132"            ,	   0x118008094fe20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8133"            ,	   0x118008094fe28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8134"            ,	   0x118008094fe30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8135"            ,	   0x118008094fe38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8136"            ,	   0x118008094fe40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8137"            ,	   0x118008094fe48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8138"            ,	   0x118008094fe50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8139"            ,	   0x118008094fe58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8140"            ,	   0x118008094fe60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8141"            ,	   0x118008094fe68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8142"            ,	   0x118008094fe70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8143"            ,	   0x118008094fe78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8144"            ,	   0x118008094fe80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8145"            ,	   0x118008094fe88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8146"            ,	   0x118008094fe90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8147"            ,	   0x118008094fe98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8148"            ,	   0x118008094fea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8149"            ,	   0x118008094fea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8150"            ,	   0x118008094feb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8151"            ,	   0x118008094feb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8152"            ,	   0x118008094fec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8153"            ,	   0x118008094fec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8154"            ,	   0x118008094fed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8155"            ,	   0x118008094fed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8156"            ,	   0x118008094fee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8157"            ,	   0x118008094fee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8158"            ,	   0x118008094fef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8159"            ,	   0x118008094fef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8160"            ,	   0x118008094ff00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8161"            ,	   0x118008094ff08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8162"            ,	   0x118008094ff10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8163"            ,	   0x118008094ff18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8164"            ,	   0x118008094ff20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8165"            ,	   0x118008094ff28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8166"            ,	   0x118008094ff30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8167"            ,	   0x118008094ff38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8168"            ,	   0x118008094ff40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8169"            ,	   0x118008094ff48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8170"            ,	   0x118008094ff50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8171"            ,	   0x118008094ff58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8172"            ,	   0x118008094ff60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8173"            ,	   0x118008094ff68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8174"            ,	   0x118008094ff70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8175"            ,	   0x118008094ff78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8176"            ,	   0x118008094ff80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8177"            ,	   0x118008094ff88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8178"            ,	   0x118008094ff90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8179"            ,	   0x118008094ff98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8180"            ,	   0x118008094ffa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8181"            ,	   0x118008094ffa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8182"            ,	   0x118008094ffb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8183"            ,	   0x118008094ffb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8184"            ,	   0x118008094ffc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8185"            ,	   0x118008094ffc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8186"            ,	   0x118008094ffd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8187"            ,	   0x118008094ffd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8188"            ,	   0x118008094ffe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8189"            ,	   0x118008094ffe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8190"            ,	   0x118008094fff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP8191"            ,	   0x118008094fff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16128"           ,	   0x118008095f800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16129"           ,	   0x118008095f808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16130"           ,	   0x118008095f810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16131"           ,	   0x118008095f818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16132"           ,	   0x118008095f820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16133"           ,	   0x118008095f828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16134"           ,	   0x118008095f830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16135"           ,	   0x118008095f838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16136"           ,	   0x118008095f840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16137"           ,	   0x118008095f848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16138"           ,	   0x118008095f850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16139"           ,	   0x118008095f858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16140"           ,	   0x118008095f860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16141"           ,	   0x118008095f868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16142"           ,	   0x118008095f870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16143"           ,	   0x118008095f878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16144"           ,	   0x118008095f880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16145"           ,	   0x118008095f888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16146"           ,	   0x118008095f890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16147"           ,	   0x118008095f898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16148"           ,	   0x118008095f8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16149"           ,	   0x118008095f8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16150"           ,	   0x118008095f8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16151"           ,	   0x118008095f8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16152"           ,	   0x118008095f8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16153"           ,	   0x118008095f8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16154"           ,	   0x118008095f8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16155"           ,	   0x118008095f8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16156"           ,	   0x118008095f8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16157"           ,	   0x118008095f8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16158"           ,	   0x118008095f8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16159"           ,	   0x118008095f8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16160"           ,	   0x118008095f900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16161"           ,	   0x118008095f908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16162"           ,	   0x118008095f910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16163"           ,	   0x118008095f918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16164"           ,	   0x118008095f920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16165"           ,	   0x118008095f928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16166"           ,	   0x118008095f930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16167"           ,	   0x118008095f938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16168"           ,	   0x118008095f940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16169"           ,	   0x118008095f948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16170"           ,	   0x118008095f950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16171"           ,	   0x118008095f958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16172"           ,	   0x118008095f960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16173"           ,	   0x118008095f968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16174"           ,	   0x118008095f970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16175"           ,	   0x118008095f978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16176"           ,	   0x118008095f980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16177"           ,	   0x118008095f988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16178"           ,	   0x118008095f990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16179"           ,	   0x118008095f998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16180"           ,	   0x118008095f9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16181"           ,	   0x118008095f9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16182"           ,	   0x118008095f9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16183"           ,	   0x118008095f9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16184"           ,	   0x118008095f9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16185"           ,	   0x118008095f9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16186"           ,	   0x118008095f9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16187"           ,	   0x118008095f9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16188"           ,	   0x118008095f9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16189"           ,	   0x118008095f9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16190"           ,	   0x118008095f9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16191"           ,	   0x118008095f9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16192"           ,	   0x118008095fa00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16193"           ,	   0x118008095fa08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16194"           ,	   0x118008095fa10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16195"           ,	   0x118008095fa18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16196"           ,	   0x118008095fa20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16197"           ,	   0x118008095fa28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16198"           ,	   0x118008095fa30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16199"           ,	   0x118008095fa38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16200"           ,	   0x118008095fa40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16201"           ,	   0x118008095fa48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16202"           ,	   0x118008095fa50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16203"           ,	   0x118008095fa58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16204"           ,	   0x118008095fa60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16205"           ,	   0x118008095fa68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16206"           ,	   0x118008095fa70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16207"           ,	   0x118008095fa78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16208"           ,	   0x118008095fa80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16209"           ,	   0x118008095fa88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16210"           ,	   0x118008095fa90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16211"           ,	   0x118008095fa98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16212"           ,	   0x118008095faa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16213"           ,	   0x118008095faa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16214"           ,	   0x118008095fab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16215"           ,	   0x118008095fab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16216"           ,	   0x118008095fac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16217"           ,	   0x118008095fac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16218"           ,	   0x118008095fad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16219"           ,	   0x118008095fad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16220"           ,	   0x118008095fae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16221"           ,	   0x118008095fae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16222"           ,	   0x118008095faf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16223"           ,	   0x118008095faf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16224"           ,	   0x118008095fb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16225"           ,	   0x118008095fb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16226"           ,	   0x118008095fb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16227"           ,	   0x118008095fb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16228"           ,	   0x118008095fb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16229"           ,	   0x118008095fb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16230"           ,	   0x118008095fb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16231"           ,	   0x118008095fb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16232"           ,	   0x118008095fb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16233"           ,	   0x118008095fb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16234"           ,	   0x118008095fb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16235"           ,	   0x118008095fb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16236"           ,	   0x118008095fb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16237"           ,	   0x118008095fb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16238"           ,	   0x118008095fb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16239"           ,	   0x118008095fb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16240"           ,	   0x118008095fb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16241"           ,	   0x118008095fb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16242"           ,	   0x118008095fb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16243"           ,	   0x118008095fb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16244"           ,	   0x118008095fba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16245"           ,	   0x118008095fba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16246"           ,	   0x118008095fbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16247"           ,	   0x118008095fbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16248"           ,	   0x118008095fbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16249"           ,	   0x118008095fbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16250"           ,	   0x118008095fbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16251"           ,	   0x118008095fbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16252"           ,	   0x118008095fbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16253"           ,	   0x118008095fbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16254"           ,	   0x118008095fbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16255"           ,	   0x118008095fbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16256"           ,	   0x118008095fc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16257"           ,	   0x118008095fc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16258"           ,	   0x118008095fc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16259"           ,	   0x118008095fc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16260"           ,	   0x118008095fc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16261"           ,	   0x118008095fc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16262"           ,	   0x118008095fc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16263"           ,	   0x118008095fc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16264"           ,	   0x118008095fc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16265"           ,	   0x118008095fc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16266"           ,	   0x118008095fc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16267"           ,	   0x118008095fc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16268"           ,	   0x118008095fc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16269"           ,	   0x118008095fc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16270"           ,	   0x118008095fc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16271"           ,	   0x118008095fc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16272"           ,	   0x118008095fc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16273"           ,	   0x118008095fc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16274"           ,	   0x118008095fc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16275"           ,	   0x118008095fc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16276"           ,	   0x118008095fca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16277"           ,	   0x118008095fca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16278"           ,	   0x118008095fcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16279"           ,	   0x118008095fcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16280"           ,	   0x118008095fcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16281"           ,	   0x118008095fcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16282"           ,	   0x118008095fcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16283"           ,	   0x118008095fcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16284"           ,	   0x118008095fce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16285"           ,	   0x118008095fce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16286"           ,	   0x118008095fcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16287"           ,	   0x118008095fcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16288"           ,	   0x118008095fd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16289"           ,	   0x118008095fd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16290"           ,	   0x118008095fd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16291"           ,	   0x118008095fd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16292"           ,	   0x118008095fd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16293"           ,	   0x118008095fd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16294"           ,	   0x118008095fd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16295"           ,	   0x118008095fd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16296"           ,	   0x118008095fd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16297"           ,	   0x118008095fd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16298"           ,	   0x118008095fd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16299"           ,	   0x118008095fd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16300"           ,	   0x118008095fd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16301"           ,	   0x118008095fd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16302"           ,	   0x118008095fd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16303"           ,	   0x118008095fd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16304"           ,	   0x118008095fd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16305"           ,	   0x118008095fd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16306"           ,	   0x118008095fd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16307"           ,	   0x118008095fd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16308"           ,	   0x118008095fda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16309"           ,	   0x118008095fda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16310"           ,	   0x118008095fdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16311"           ,	   0x118008095fdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16312"           ,	   0x118008095fdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16313"           ,	   0x118008095fdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16314"           ,	   0x118008095fdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16315"           ,	   0x118008095fdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16316"           ,	   0x118008095fde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16317"           ,	   0x118008095fde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16318"           ,	   0x118008095fdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16319"           ,	   0x118008095fdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16320"           ,	   0x118008095fe00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16321"           ,	   0x118008095fe08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16322"           ,	   0x118008095fe10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16323"           ,	   0x118008095fe18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16324"           ,	   0x118008095fe20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16325"           ,	   0x118008095fe28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16326"           ,	   0x118008095fe30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16327"           ,	   0x118008095fe38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16328"           ,	   0x118008095fe40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16329"           ,	   0x118008095fe48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16330"           ,	   0x118008095fe50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16331"           ,	   0x118008095fe58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16332"           ,	   0x118008095fe60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16333"           ,	   0x118008095fe68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16334"           ,	   0x118008095fe70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16335"           ,	   0x118008095fe78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16336"           ,	   0x118008095fe80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16337"           ,	   0x118008095fe88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16338"           ,	   0x118008095fe90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16339"           ,	   0x118008095fe98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16340"           ,	   0x118008095fea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16341"           ,	   0x118008095fea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16342"           ,	   0x118008095feb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16343"           ,	   0x118008095feb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16344"           ,	   0x118008095fec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16345"           ,	   0x118008095fec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16346"           ,	   0x118008095fed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16347"           ,	   0x118008095fed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16348"           ,	   0x118008095fee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16349"           ,	   0x118008095fee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16350"           ,	   0x118008095fef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16351"           ,	   0x118008095fef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16352"           ,	   0x118008095ff00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16353"           ,	   0x118008095ff08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16354"           ,	   0x118008095ff10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16355"           ,	   0x118008095ff18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16356"           ,	   0x118008095ff20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16357"           ,	   0x118008095ff28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16358"           ,	   0x118008095ff30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16359"           ,	   0x118008095ff38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16360"           ,	   0x118008095ff40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16361"           ,	   0x118008095ff48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16362"           ,	   0x118008095ff50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16363"           ,	   0x118008095ff58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16364"           ,	   0x118008095ff60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16365"           ,	   0x118008095ff68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16366"           ,	   0x118008095ff70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16367"           ,	   0x118008095ff78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16368"           ,	   0x118008095ff80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16369"           ,	   0x118008095ff88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16370"           ,	   0x118008095ff90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16371"           ,	   0x118008095ff98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16372"           ,	   0x118008095ffa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16373"           ,	   0x118008095ffa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16374"           ,	   0x118008095ffb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16375"           ,	   0x118008095ffb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16376"           ,	   0x118008095ffc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16377"           ,	   0x118008095ffc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16378"           ,	   0x118008095ffd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16379"           ,	   0x118008095ffd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16380"           ,	   0x118008095ffe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16381"           ,	   0x118008095ffe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16382"           ,	   0x118008095fff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_COP0_MAP16383"           ,	   0x118008095fff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"L2C_CTL"                     ,	   0x1180080800000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	612},
+	{"L2C_DUT_MAP0"                ,	   0x1180080e00000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1"                ,	   0x1180080e00008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2"                ,	   0x1180080e00010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3"                ,	   0x1180080e00018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4"                ,	   0x1180080e00020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5"                ,	   0x1180080e00028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6"                ,	   0x1180080e00030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7"                ,	   0x1180080e00038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8"                ,	   0x1180080e00040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP9"                ,	   0x1180080e00048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP10"               ,	   0x1180080e00050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP11"               ,	   0x1180080e00058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP12"               ,	   0x1180080e00060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP13"               ,	   0x1180080e00068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP14"               ,	   0x1180080e00070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP15"               ,	   0x1180080e00078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP16"               ,	   0x1180080e00080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP17"               ,	   0x1180080e00088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP18"               ,	   0x1180080e00090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP19"               ,	   0x1180080e00098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP20"               ,	   0x1180080e000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP21"               ,	   0x1180080e000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP22"               ,	   0x1180080e000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP23"               ,	   0x1180080e000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP24"               ,	   0x1180080e000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP25"               ,	   0x1180080e000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP26"               ,	   0x1180080e000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP27"               ,	   0x1180080e000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP28"               ,	   0x1180080e000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP29"               ,	   0x1180080e000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP30"               ,	   0x1180080e000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP31"               ,	   0x1180080e000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP32"               ,	   0x1180080e00100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP33"               ,	   0x1180080e00108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP34"               ,	   0x1180080e00110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP35"               ,	   0x1180080e00118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP36"               ,	   0x1180080e00120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP37"               ,	   0x1180080e00128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP38"               ,	   0x1180080e00130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP39"               ,	   0x1180080e00138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP40"               ,	   0x1180080e00140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP41"               ,	   0x1180080e00148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP42"               ,	   0x1180080e00150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP43"               ,	   0x1180080e00158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP44"               ,	   0x1180080e00160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP45"               ,	   0x1180080e00168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP46"               ,	   0x1180080e00170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP47"               ,	   0x1180080e00178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP48"               ,	   0x1180080e00180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP49"               ,	   0x1180080e00188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP50"               ,	   0x1180080e00190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP51"               ,	   0x1180080e00198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP52"               ,	   0x1180080e001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP53"               ,	   0x1180080e001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP54"               ,	   0x1180080e001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP55"               ,	   0x1180080e001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP56"               ,	   0x1180080e001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP57"               ,	   0x1180080e001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP58"               ,	   0x1180080e001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP59"               ,	   0x1180080e001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP60"               ,	   0x1180080e001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP61"               ,	   0x1180080e001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP62"               ,	   0x1180080e001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP63"               ,	   0x1180080e001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP64"               ,	   0x1180080e00200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP65"               ,	   0x1180080e00208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP66"               ,	   0x1180080e00210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP67"               ,	   0x1180080e00218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP68"               ,	   0x1180080e00220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP69"               ,	   0x1180080e00228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP70"               ,	   0x1180080e00230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP71"               ,	   0x1180080e00238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP72"               ,	   0x1180080e00240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP73"               ,	   0x1180080e00248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP74"               ,	   0x1180080e00250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP75"               ,	   0x1180080e00258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP76"               ,	   0x1180080e00260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP77"               ,	   0x1180080e00268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP78"               ,	   0x1180080e00270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP79"               ,	   0x1180080e00278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP80"               ,	   0x1180080e00280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP81"               ,	   0x1180080e00288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP82"               ,	   0x1180080e00290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP83"               ,	   0x1180080e00298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP84"               ,	   0x1180080e002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP85"               ,	   0x1180080e002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP86"               ,	   0x1180080e002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP87"               ,	   0x1180080e002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP88"               ,	   0x1180080e002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP89"               ,	   0x1180080e002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP90"               ,	   0x1180080e002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP91"               ,	   0x1180080e002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP92"               ,	   0x1180080e002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP93"               ,	   0x1180080e002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP94"               ,	   0x1180080e002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP95"               ,	   0x1180080e002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP96"               ,	   0x1180080e00300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP97"               ,	   0x1180080e00308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP98"               ,	   0x1180080e00310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP99"               ,	   0x1180080e00318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP100"              ,	   0x1180080e00320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP101"              ,	   0x1180080e00328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP102"              ,	   0x1180080e00330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP103"              ,	   0x1180080e00338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP104"              ,	   0x1180080e00340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP105"              ,	   0x1180080e00348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP106"              ,	   0x1180080e00350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP107"              ,	   0x1180080e00358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP108"              ,	   0x1180080e00360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP109"              ,	   0x1180080e00368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP110"              ,	   0x1180080e00370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP111"              ,	   0x1180080e00378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP112"              ,	   0x1180080e00380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP113"              ,	   0x1180080e00388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP114"              ,	   0x1180080e00390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP115"              ,	   0x1180080e00398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP116"              ,	   0x1180080e003a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP117"              ,	   0x1180080e003a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP118"              ,	   0x1180080e003b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP119"              ,	   0x1180080e003b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP120"              ,	   0x1180080e003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP121"              ,	   0x1180080e003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP122"              ,	   0x1180080e003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP123"              ,	   0x1180080e003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP124"              ,	   0x1180080e003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP125"              ,	   0x1180080e003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP126"              ,	   0x1180080e003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP127"              ,	   0x1180080e003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP128"              ,	   0x1180080e00400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP129"              ,	   0x1180080e00408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP130"              ,	   0x1180080e00410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP131"              ,	   0x1180080e00418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP132"              ,	   0x1180080e00420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP133"              ,	   0x1180080e00428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP134"              ,	   0x1180080e00430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP135"              ,	   0x1180080e00438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP136"              ,	   0x1180080e00440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP137"              ,	   0x1180080e00448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP138"              ,	   0x1180080e00450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP139"              ,	   0x1180080e00458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP140"              ,	   0x1180080e00460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP141"              ,	   0x1180080e00468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP142"              ,	   0x1180080e00470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP143"              ,	   0x1180080e00478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP144"              ,	   0x1180080e00480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP145"              ,	   0x1180080e00488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP146"              ,	   0x1180080e00490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP147"              ,	   0x1180080e00498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP148"              ,	   0x1180080e004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP149"              ,	   0x1180080e004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP150"              ,	   0x1180080e004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP151"              ,	   0x1180080e004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP152"              ,	   0x1180080e004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP153"              ,	   0x1180080e004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP154"              ,	   0x1180080e004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP155"              ,	   0x1180080e004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP156"              ,	   0x1180080e004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP157"              ,	   0x1180080e004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP158"              ,	   0x1180080e004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP159"              ,	   0x1180080e004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP160"              ,	   0x1180080e00500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP161"              ,	   0x1180080e00508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP162"              ,	   0x1180080e00510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP163"              ,	   0x1180080e00518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP164"              ,	   0x1180080e00520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP165"              ,	   0x1180080e00528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP166"              ,	   0x1180080e00530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP167"              ,	   0x1180080e00538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP168"              ,	   0x1180080e00540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP169"              ,	   0x1180080e00548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP170"              ,	   0x1180080e00550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP171"              ,	   0x1180080e00558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP172"              ,	   0x1180080e00560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP173"              ,	   0x1180080e00568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP174"              ,	   0x1180080e00570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP175"              ,	   0x1180080e00578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP176"              ,	   0x1180080e00580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP177"              ,	   0x1180080e00588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP178"              ,	   0x1180080e00590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP179"              ,	   0x1180080e00598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP180"              ,	   0x1180080e005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP181"              ,	   0x1180080e005a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP182"              ,	   0x1180080e005b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP183"              ,	   0x1180080e005b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP184"              ,	   0x1180080e005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP185"              ,	   0x1180080e005c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP186"              ,	   0x1180080e005d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP187"              ,	   0x1180080e005d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP188"              ,	   0x1180080e005e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP189"              ,	   0x1180080e005e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP190"              ,	   0x1180080e005f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP191"              ,	   0x1180080e005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP192"              ,	   0x1180080e00600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP193"              ,	   0x1180080e00608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP194"              ,	   0x1180080e00610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP195"              ,	   0x1180080e00618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP196"              ,	   0x1180080e00620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP197"              ,	   0x1180080e00628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP198"              ,	   0x1180080e00630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP199"              ,	   0x1180080e00638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP200"              ,	   0x1180080e00640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP201"              ,	   0x1180080e00648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP202"              ,	   0x1180080e00650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP203"              ,	   0x1180080e00658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP204"              ,	   0x1180080e00660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP205"              ,	   0x1180080e00668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP206"              ,	   0x1180080e00670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP207"              ,	   0x1180080e00678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP208"              ,	   0x1180080e00680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP209"              ,	   0x1180080e00688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP210"              ,	   0x1180080e00690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP211"              ,	   0x1180080e00698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP212"              ,	   0x1180080e006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP213"              ,	   0x1180080e006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP214"              ,	   0x1180080e006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP215"              ,	   0x1180080e006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP216"              ,	   0x1180080e006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP217"              ,	   0x1180080e006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP218"              ,	   0x1180080e006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP219"              ,	   0x1180080e006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP220"              ,	   0x1180080e006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP221"              ,	   0x1180080e006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP222"              ,	   0x1180080e006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP223"              ,	   0x1180080e006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP224"              ,	   0x1180080e00700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP225"              ,	   0x1180080e00708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP226"              ,	   0x1180080e00710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP227"              ,	   0x1180080e00718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP228"              ,	   0x1180080e00720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP229"              ,	   0x1180080e00728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP230"              ,	   0x1180080e00730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP231"              ,	   0x1180080e00738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP232"              ,	   0x1180080e00740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP233"              ,	   0x1180080e00748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP234"              ,	   0x1180080e00750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP235"              ,	   0x1180080e00758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP236"              ,	   0x1180080e00760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP237"              ,	   0x1180080e00768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP238"              ,	   0x1180080e00770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP239"              ,	   0x1180080e00778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP240"              ,	   0x1180080e00780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP241"              ,	   0x1180080e00788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP242"              ,	   0x1180080e00790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP243"              ,	   0x1180080e00798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP244"              ,	   0x1180080e007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP245"              ,	   0x1180080e007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP246"              ,	   0x1180080e007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP247"              ,	   0x1180080e007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP248"              ,	   0x1180080e007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP249"              ,	   0x1180080e007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP250"              ,	   0x1180080e007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP251"              ,	   0x1180080e007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP252"              ,	   0x1180080e007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP253"              ,	   0x1180080e007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP254"              ,	   0x1180080e007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP255"              ,	   0x1180080e007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP256"              ,	   0x1180080e00800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP257"              ,	   0x1180080e00808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP258"              ,	   0x1180080e00810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP259"              ,	   0x1180080e00818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP260"              ,	   0x1180080e00820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP261"              ,	   0x1180080e00828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP262"              ,	   0x1180080e00830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP263"              ,	   0x1180080e00838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP264"              ,	   0x1180080e00840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP265"              ,	   0x1180080e00848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP266"              ,	   0x1180080e00850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP267"              ,	   0x1180080e00858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP268"              ,	   0x1180080e00860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP269"              ,	   0x1180080e00868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP270"              ,	   0x1180080e00870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP271"              ,	   0x1180080e00878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP272"              ,	   0x1180080e00880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP273"              ,	   0x1180080e00888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP274"              ,	   0x1180080e00890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP275"              ,	   0x1180080e00898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP276"              ,	   0x1180080e008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP277"              ,	   0x1180080e008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP278"              ,	   0x1180080e008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP279"              ,	   0x1180080e008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP280"              ,	   0x1180080e008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP281"              ,	   0x1180080e008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP282"              ,	   0x1180080e008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP283"              ,	   0x1180080e008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP284"              ,	   0x1180080e008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP285"              ,	   0x1180080e008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP286"              ,	   0x1180080e008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP287"              ,	   0x1180080e008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP288"              ,	   0x1180080e00900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP289"              ,	   0x1180080e00908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP290"              ,	   0x1180080e00910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP291"              ,	   0x1180080e00918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP292"              ,	   0x1180080e00920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP293"              ,	   0x1180080e00928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP294"              ,	   0x1180080e00930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP295"              ,	   0x1180080e00938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP296"              ,	   0x1180080e00940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP297"              ,	   0x1180080e00948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP298"              ,	   0x1180080e00950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP299"              ,	   0x1180080e00958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP300"              ,	   0x1180080e00960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP301"              ,	   0x1180080e00968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP302"              ,	   0x1180080e00970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP303"              ,	   0x1180080e00978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP304"              ,	   0x1180080e00980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP305"              ,	   0x1180080e00988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP306"              ,	   0x1180080e00990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP307"              ,	   0x1180080e00998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP308"              ,	   0x1180080e009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP309"              ,	   0x1180080e009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP310"              ,	   0x1180080e009b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP311"              ,	   0x1180080e009b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP312"              ,	   0x1180080e009c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP313"              ,	   0x1180080e009c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP314"              ,	   0x1180080e009d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP315"              ,	   0x1180080e009d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP316"              ,	   0x1180080e009e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP317"              ,	   0x1180080e009e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP318"              ,	   0x1180080e009f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP319"              ,	   0x1180080e009f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP320"              ,	   0x1180080e00a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP321"              ,	   0x1180080e00a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP322"              ,	   0x1180080e00a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP323"              ,	   0x1180080e00a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP324"              ,	   0x1180080e00a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP325"              ,	   0x1180080e00a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP326"              ,	   0x1180080e00a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP327"              ,	   0x1180080e00a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP328"              ,	   0x1180080e00a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP329"              ,	   0x1180080e00a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP330"              ,	   0x1180080e00a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP331"              ,	   0x1180080e00a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP332"              ,	   0x1180080e00a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP333"              ,	   0x1180080e00a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP334"              ,	   0x1180080e00a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP335"              ,	   0x1180080e00a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP336"              ,	   0x1180080e00a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP337"              ,	   0x1180080e00a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP338"              ,	   0x1180080e00a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP339"              ,	   0x1180080e00a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP340"              ,	   0x1180080e00aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP341"              ,	   0x1180080e00aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP342"              ,	   0x1180080e00ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP343"              ,	   0x1180080e00ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP344"              ,	   0x1180080e00ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP345"              ,	   0x1180080e00ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP346"              ,	   0x1180080e00ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP347"              ,	   0x1180080e00ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP348"              ,	   0x1180080e00ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP349"              ,	   0x1180080e00ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP350"              ,	   0x1180080e00af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP351"              ,	   0x1180080e00af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP352"              ,	   0x1180080e00b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP353"              ,	   0x1180080e00b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP354"              ,	   0x1180080e00b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP355"              ,	   0x1180080e00b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP356"              ,	   0x1180080e00b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP357"              ,	   0x1180080e00b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP358"              ,	   0x1180080e00b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP359"              ,	   0x1180080e00b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP360"              ,	   0x1180080e00b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP361"              ,	   0x1180080e00b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP362"              ,	   0x1180080e00b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP363"              ,	   0x1180080e00b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP364"              ,	   0x1180080e00b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP365"              ,	   0x1180080e00b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP366"              ,	   0x1180080e00b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP367"              ,	   0x1180080e00b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP368"              ,	   0x1180080e00b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP369"              ,	   0x1180080e00b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP370"              ,	   0x1180080e00b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP371"              ,	   0x1180080e00b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP372"              ,	   0x1180080e00ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP373"              ,	   0x1180080e00ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP374"              ,	   0x1180080e00bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP375"              ,	   0x1180080e00bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP376"              ,	   0x1180080e00bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP377"              ,	   0x1180080e00bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP378"              ,	   0x1180080e00bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP379"              ,	   0x1180080e00bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP380"              ,	   0x1180080e00be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP381"              ,	   0x1180080e00be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP382"              ,	   0x1180080e00bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP383"              ,	   0x1180080e00bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP384"              ,	   0x1180080e00c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP385"              ,	   0x1180080e00c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP386"              ,	   0x1180080e00c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP387"              ,	   0x1180080e00c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP388"              ,	   0x1180080e00c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP389"              ,	   0x1180080e00c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP390"              ,	   0x1180080e00c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP391"              ,	   0x1180080e00c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP392"              ,	   0x1180080e00c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP393"              ,	   0x1180080e00c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP394"              ,	   0x1180080e00c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP395"              ,	   0x1180080e00c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP396"              ,	   0x1180080e00c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP397"              ,	   0x1180080e00c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP398"              ,	   0x1180080e00c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP399"              ,	   0x1180080e00c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP400"              ,	   0x1180080e00c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP401"              ,	   0x1180080e00c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP402"              ,	   0x1180080e00c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP403"              ,	   0x1180080e00c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP404"              ,	   0x1180080e00ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP405"              ,	   0x1180080e00ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP406"              ,	   0x1180080e00cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP407"              ,	   0x1180080e00cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP408"              ,	   0x1180080e00cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP409"              ,	   0x1180080e00cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP410"              ,	   0x1180080e00cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP411"              ,	   0x1180080e00cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP412"              ,	   0x1180080e00ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP413"              ,	   0x1180080e00ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP414"              ,	   0x1180080e00cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP415"              ,	   0x1180080e00cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP416"              ,	   0x1180080e00d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP417"              ,	   0x1180080e00d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP418"              ,	   0x1180080e00d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP419"              ,	   0x1180080e00d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP420"              ,	   0x1180080e00d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP421"              ,	   0x1180080e00d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP422"              ,	   0x1180080e00d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP423"              ,	   0x1180080e00d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP424"              ,	   0x1180080e00d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP425"              ,	   0x1180080e00d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP426"              ,	   0x1180080e00d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP427"              ,	   0x1180080e00d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP428"              ,	   0x1180080e00d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP429"              ,	   0x1180080e00d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP430"              ,	   0x1180080e00d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP431"              ,	   0x1180080e00d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP432"              ,	   0x1180080e00d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP433"              ,	   0x1180080e00d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP434"              ,	   0x1180080e00d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP435"              ,	   0x1180080e00d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP436"              ,	   0x1180080e00da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP437"              ,	   0x1180080e00da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP438"              ,	   0x1180080e00db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP439"              ,	   0x1180080e00db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP440"              ,	   0x1180080e00dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP441"              ,	   0x1180080e00dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP442"              ,	   0x1180080e00dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP443"              ,	   0x1180080e00dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP444"              ,	   0x1180080e00de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP445"              ,	   0x1180080e00de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP446"              ,	   0x1180080e00df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP447"              ,	   0x1180080e00df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP448"              ,	   0x1180080e00e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP449"              ,	   0x1180080e00e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP450"              ,	   0x1180080e00e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP451"              ,	   0x1180080e00e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP452"              ,	   0x1180080e00e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP453"              ,	   0x1180080e00e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP454"              ,	   0x1180080e00e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP455"              ,	   0x1180080e00e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP456"              ,	   0x1180080e00e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP457"              ,	   0x1180080e00e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP458"              ,	   0x1180080e00e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP459"              ,	   0x1180080e00e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP460"              ,	   0x1180080e00e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP461"              ,	   0x1180080e00e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP462"              ,	   0x1180080e00e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP463"              ,	   0x1180080e00e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP464"              ,	   0x1180080e00e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP465"              ,	   0x1180080e00e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP466"              ,	   0x1180080e00e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP467"              ,	   0x1180080e00e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP468"              ,	   0x1180080e00ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP469"              ,	   0x1180080e00ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP470"              ,	   0x1180080e00eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP471"              ,	   0x1180080e00eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP472"              ,	   0x1180080e00ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP473"              ,	   0x1180080e00ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP474"              ,	   0x1180080e00ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP475"              ,	   0x1180080e00ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP476"              ,	   0x1180080e00ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP477"              ,	   0x1180080e00ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP478"              ,	   0x1180080e00ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP479"              ,	   0x1180080e00ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP480"              ,	   0x1180080e00f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP481"              ,	   0x1180080e00f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP482"              ,	   0x1180080e00f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP483"              ,	   0x1180080e00f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP484"              ,	   0x1180080e00f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP485"              ,	   0x1180080e00f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP486"              ,	   0x1180080e00f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP487"              ,	   0x1180080e00f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP488"              ,	   0x1180080e00f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP489"              ,	   0x1180080e00f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP490"              ,	   0x1180080e00f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP491"              ,	   0x1180080e00f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP492"              ,	   0x1180080e00f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP493"              ,	   0x1180080e00f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP494"              ,	   0x1180080e00f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP495"              ,	   0x1180080e00f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP496"              ,	   0x1180080e00f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP497"              ,	   0x1180080e00f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP498"              ,	   0x1180080e00f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP499"              ,	   0x1180080e00f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP500"              ,	   0x1180080e00fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP501"              ,	   0x1180080e00fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP502"              ,	   0x1180080e00fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP503"              ,	   0x1180080e00fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP504"              ,	   0x1180080e00fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP505"              ,	   0x1180080e00fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP506"              ,	   0x1180080e00fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP507"              ,	   0x1180080e00fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP508"              ,	   0x1180080e00fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP509"              ,	   0x1180080e00fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP510"              ,	   0x1180080e00ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP511"              ,	   0x1180080e00ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP512"              ,	   0x1180080e01000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP513"              ,	   0x1180080e01008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP514"              ,	   0x1180080e01010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP515"              ,	   0x1180080e01018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP516"              ,	   0x1180080e01020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP517"              ,	   0x1180080e01028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP518"              ,	   0x1180080e01030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP519"              ,	   0x1180080e01038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP520"              ,	   0x1180080e01040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP521"              ,	   0x1180080e01048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP522"              ,	   0x1180080e01050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP523"              ,	   0x1180080e01058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP524"              ,	   0x1180080e01060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP525"              ,	   0x1180080e01068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP526"              ,	   0x1180080e01070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP527"              ,	   0x1180080e01078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP528"              ,	   0x1180080e01080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP529"              ,	   0x1180080e01088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP530"              ,	   0x1180080e01090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP531"              ,	   0x1180080e01098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP532"              ,	   0x1180080e010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP533"              ,	   0x1180080e010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP534"              ,	   0x1180080e010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP535"              ,	   0x1180080e010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP536"              ,	   0x1180080e010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP537"              ,	   0x1180080e010c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP538"              ,	   0x1180080e010d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP539"              ,	   0x1180080e010d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP540"              ,	   0x1180080e010e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP541"              ,	   0x1180080e010e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP542"              ,	   0x1180080e010f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP543"              ,	   0x1180080e010f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP544"              ,	   0x1180080e01100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP545"              ,	   0x1180080e01108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP546"              ,	   0x1180080e01110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP547"              ,	   0x1180080e01118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP548"              ,	   0x1180080e01120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP549"              ,	   0x1180080e01128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP550"              ,	   0x1180080e01130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP551"              ,	   0x1180080e01138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP552"              ,	   0x1180080e01140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP553"              ,	   0x1180080e01148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP554"              ,	   0x1180080e01150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP555"              ,	   0x1180080e01158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP556"              ,	   0x1180080e01160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP557"              ,	   0x1180080e01168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP558"              ,	   0x1180080e01170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP559"              ,	   0x1180080e01178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP560"              ,	   0x1180080e01180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP561"              ,	   0x1180080e01188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP562"              ,	   0x1180080e01190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP563"              ,	   0x1180080e01198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP564"              ,	   0x1180080e011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP565"              ,	   0x1180080e011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP566"              ,	   0x1180080e011b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP567"              ,	   0x1180080e011b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP568"              ,	   0x1180080e011c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP569"              ,	   0x1180080e011c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP570"              ,	   0x1180080e011d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP571"              ,	   0x1180080e011d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP572"              ,	   0x1180080e011e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP573"              ,	   0x1180080e011e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP574"              ,	   0x1180080e011f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP575"              ,	   0x1180080e011f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP576"              ,	   0x1180080e01200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP577"              ,	   0x1180080e01208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP578"              ,	   0x1180080e01210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP579"              ,	   0x1180080e01218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP580"              ,	   0x1180080e01220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP581"              ,	   0x1180080e01228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP582"              ,	   0x1180080e01230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP583"              ,	   0x1180080e01238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP584"              ,	   0x1180080e01240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP585"              ,	   0x1180080e01248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP586"              ,	   0x1180080e01250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP587"              ,	   0x1180080e01258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP588"              ,	   0x1180080e01260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP589"              ,	   0x1180080e01268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP590"              ,	   0x1180080e01270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP591"              ,	   0x1180080e01278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP592"              ,	   0x1180080e01280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP593"              ,	   0x1180080e01288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP594"              ,	   0x1180080e01290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP595"              ,	   0x1180080e01298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP596"              ,	   0x1180080e012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP597"              ,	   0x1180080e012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP598"              ,	   0x1180080e012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP599"              ,	   0x1180080e012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP600"              ,	   0x1180080e012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP601"              ,	   0x1180080e012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP602"              ,	   0x1180080e012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP603"              ,	   0x1180080e012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP604"              ,	   0x1180080e012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP605"              ,	   0x1180080e012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP606"              ,	   0x1180080e012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP607"              ,	   0x1180080e012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP608"              ,	   0x1180080e01300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP609"              ,	   0x1180080e01308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP610"              ,	   0x1180080e01310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP611"              ,	   0x1180080e01318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP612"              ,	   0x1180080e01320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP613"              ,	   0x1180080e01328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP614"              ,	   0x1180080e01330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP615"              ,	   0x1180080e01338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP616"              ,	   0x1180080e01340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP617"              ,	   0x1180080e01348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP618"              ,	   0x1180080e01350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP619"              ,	   0x1180080e01358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP620"              ,	   0x1180080e01360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP621"              ,	   0x1180080e01368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP622"              ,	   0x1180080e01370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP623"              ,	   0x1180080e01378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP624"              ,	   0x1180080e01380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP625"              ,	   0x1180080e01388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP626"              ,	   0x1180080e01390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP627"              ,	   0x1180080e01398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP628"              ,	   0x1180080e013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP629"              ,	   0x1180080e013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP630"              ,	   0x1180080e013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP631"              ,	   0x1180080e013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP632"              ,	   0x1180080e013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP633"              ,	   0x1180080e013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP634"              ,	   0x1180080e013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP635"              ,	   0x1180080e013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP636"              ,	   0x1180080e013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP637"              ,	   0x1180080e013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP638"              ,	   0x1180080e013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP639"              ,	   0x1180080e013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP640"              ,	   0x1180080e01400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP641"              ,	   0x1180080e01408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP642"              ,	   0x1180080e01410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP643"              ,	   0x1180080e01418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP644"              ,	   0x1180080e01420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP645"              ,	   0x1180080e01428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP646"              ,	   0x1180080e01430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP647"              ,	   0x1180080e01438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP648"              ,	   0x1180080e01440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP649"              ,	   0x1180080e01448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP650"              ,	   0x1180080e01450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP651"              ,	   0x1180080e01458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP652"              ,	   0x1180080e01460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP653"              ,	   0x1180080e01468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP654"              ,	   0x1180080e01470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP655"              ,	   0x1180080e01478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP656"              ,	   0x1180080e01480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP657"              ,	   0x1180080e01488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP658"              ,	   0x1180080e01490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP659"              ,	   0x1180080e01498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP660"              ,	   0x1180080e014a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP661"              ,	   0x1180080e014a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP662"              ,	   0x1180080e014b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP663"              ,	   0x1180080e014b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP664"              ,	   0x1180080e014c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP665"              ,	   0x1180080e014c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP666"              ,	   0x1180080e014d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP667"              ,	   0x1180080e014d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP668"              ,	   0x1180080e014e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP669"              ,	   0x1180080e014e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP670"              ,	   0x1180080e014f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP671"              ,	   0x1180080e014f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP672"              ,	   0x1180080e01500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP673"              ,	   0x1180080e01508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP674"              ,	   0x1180080e01510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP675"              ,	   0x1180080e01518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP676"              ,	   0x1180080e01520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP677"              ,	   0x1180080e01528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP678"              ,	   0x1180080e01530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP679"              ,	   0x1180080e01538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP680"              ,	   0x1180080e01540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP681"              ,	   0x1180080e01548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP682"              ,	   0x1180080e01550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP683"              ,	   0x1180080e01558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP684"              ,	   0x1180080e01560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP685"              ,	   0x1180080e01568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP686"              ,	   0x1180080e01570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP687"              ,	   0x1180080e01578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP688"              ,	   0x1180080e01580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP689"              ,	   0x1180080e01588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP690"              ,	   0x1180080e01590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP691"              ,	   0x1180080e01598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP692"              ,	   0x1180080e015a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP693"              ,	   0x1180080e015a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP694"              ,	   0x1180080e015b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP695"              ,	   0x1180080e015b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP696"              ,	   0x1180080e015c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP697"              ,	   0x1180080e015c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP698"              ,	   0x1180080e015d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP699"              ,	   0x1180080e015d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP700"              ,	   0x1180080e015e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP701"              ,	   0x1180080e015e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP702"              ,	   0x1180080e015f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP703"              ,	   0x1180080e015f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP704"              ,	   0x1180080e01600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP705"              ,	   0x1180080e01608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP706"              ,	   0x1180080e01610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP707"              ,	   0x1180080e01618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP708"              ,	   0x1180080e01620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP709"              ,	   0x1180080e01628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP710"              ,	   0x1180080e01630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP711"              ,	   0x1180080e01638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP712"              ,	   0x1180080e01640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP713"              ,	   0x1180080e01648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP714"              ,	   0x1180080e01650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP715"              ,	   0x1180080e01658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP716"              ,	   0x1180080e01660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP717"              ,	   0x1180080e01668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP718"              ,	   0x1180080e01670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP719"              ,	   0x1180080e01678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP720"              ,	   0x1180080e01680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP721"              ,	   0x1180080e01688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP722"              ,	   0x1180080e01690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP723"              ,	   0x1180080e01698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP724"              ,	   0x1180080e016a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP725"              ,	   0x1180080e016a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP726"              ,	   0x1180080e016b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP727"              ,	   0x1180080e016b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP728"              ,	   0x1180080e016c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP729"              ,	   0x1180080e016c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP730"              ,	   0x1180080e016d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP731"              ,	   0x1180080e016d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP732"              ,	   0x1180080e016e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP733"              ,	   0x1180080e016e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP734"              ,	   0x1180080e016f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP735"              ,	   0x1180080e016f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP736"              ,	   0x1180080e01700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP737"              ,	   0x1180080e01708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP738"              ,	   0x1180080e01710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP739"              ,	   0x1180080e01718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP740"              ,	   0x1180080e01720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP741"              ,	   0x1180080e01728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP742"              ,	   0x1180080e01730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP743"              ,	   0x1180080e01738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP744"              ,	   0x1180080e01740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP745"              ,	   0x1180080e01748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP746"              ,	   0x1180080e01750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP747"              ,	   0x1180080e01758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP748"              ,	   0x1180080e01760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP749"              ,	   0x1180080e01768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP750"              ,	   0x1180080e01770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP751"              ,	   0x1180080e01778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP752"              ,	   0x1180080e01780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP753"              ,	   0x1180080e01788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP754"              ,	   0x1180080e01790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP755"              ,	   0x1180080e01798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP756"              ,	   0x1180080e017a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP757"              ,	   0x1180080e017a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP758"              ,	   0x1180080e017b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP759"              ,	   0x1180080e017b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP760"              ,	   0x1180080e017c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP761"              ,	   0x1180080e017c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP762"              ,	   0x1180080e017d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP763"              ,	   0x1180080e017d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP764"              ,	   0x1180080e017e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP765"              ,	   0x1180080e017e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP766"              ,	   0x1180080e017f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP767"              ,	   0x1180080e017f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP768"              ,	   0x1180080e01800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP769"              ,	   0x1180080e01808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP770"              ,	   0x1180080e01810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP771"              ,	   0x1180080e01818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP772"              ,	   0x1180080e01820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP773"              ,	   0x1180080e01828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP774"              ,	   0x1180080e01830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP775"              ,	   0x1180080e01838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP776"              ,	   0x1180080e01840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP777"              ,	   0x1180080e01848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP778"              ,	   0x1180080e01850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP779"              ,	   0x1180080e01858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP780"              ,	   0x1180080e01860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP781"              ,	   0x1180080e01868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP782"              ,	   0x1180080e01870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP783"              ,	   0x1180080e01878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP784"              ,	   0x1180080e01880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP785"              ,	   0x1180080e01888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP786"              ,	   0x1180080e01890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP787"              ,	   0x1180080e01898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP788"              ,	   0x1180080e018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP789"              ,	   0x1180080e018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP790"              ,	   0x1180080e018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP791"              ,	   0x1180080e018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP792"              ,	   0x1180080e018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP793"              ,	   0x1180080e018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP794"              ,	   0x1180080e018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP795"              ,	   0x1180080e018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP796"              ,	   0x1180080e018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP797"              ,	   0x1180080e018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP798"              ,	   0x1180080e018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP799"              ,	   0x1180080e018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP800"              ,	   0x1180080e01900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP801"              ,	   0x1180080e01908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP802"              ,	   0x1180080e01910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP803"              ,	   0x1180080e01918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP804"              ,	   0x1180080e01920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP805"              ,	   0x1180080e01928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP806"              ,	   0x1180080e01930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP807"              ,	   0x1180080e01938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP808"              ,	   0x1180080e01940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP809"              ,	   0x1180080e01948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP810"              ,	   0x1180080e01950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP811"              ,	   0x1180080e01958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP812"              ,	   0x1180080e01960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP813"              ,	   0x1180080e01968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP814"              ,	   0x1180080e01970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP815"              ,	   0x1180080e01978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP816"              ,	   0x1180080e01980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP817"              ,	   0x1180080e01988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP818"              ,	   0x1180080e01990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP819"              ,	   0x1180080e01998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP820"              ,	   0x1180080e019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP821"              ,	   0x1180080e019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP822"              ,	   0x1180080e019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP823"              ,	   0x1180080e019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP824"              ,	   0x1180080e019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP825"              ,	   0x1180080e019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP826"              ,	   0x1180080e019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP827"              ,	   0x1180080e019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP828"              ,	   0x1180080e019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP829"              ,	   0x1180080e019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP830"              ,	   0x1180080e019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP831"              ,	   0x1180080e019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP832"              ,	   0x1180080e01a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP833"              ,	   0x1180080e01a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP834"              ,	   0x1180080e01a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP835"              ,	   0x1180080e01a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP836"              ,	   0x1180080e01a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP837"              ,	   0x1180080e01a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP838"              ,	   0x1180080e01a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP839"              ,	   0x1180080e01a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP840"              ,	   0x1180080e01a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP841"              ,	   0x1180080e01a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP842"              ,	   0x1180080e01a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP843"              ,	   0x1180080e01a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP844"              ,	   0x1180080e01a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP845"              ,	   0x1180080e01a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP846"              ,	   0x1180080e01a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP847"              ,	   0x1180080e01a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP848"              ,	   0x1180080e01a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP849"              ,	   0x1180080e01a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP850"              ,	   0x1180080e01a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP851"              ,	   0x1180080e01a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP852"              ,	   0x1180080e01aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP853"              ,	   0x1180080e01aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP854"              ,	   0x1180080e01ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP855"              ,	   0x1180080e01ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP856"              ,	   0x1180080e01ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP857"              ,	   0x1180080e01ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP858"              ,	   0x1180080e01ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP859"              ,	   0x1180080e01ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP860"              ,	   0x1180080e01ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP861"              ,	   0x1180080e01ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP862"              ,	   0x1180080e01af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP863"              ,	   0x1180080e01af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP864"              ,	   0x1180080e01b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP865"              ,	   0x1180080e01b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP866"              ,	   0x1180080e01b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP867"              ,	   0x1180080e01b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP868"              ,	   0x1180080e01b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP869"              ,	   0x1180080e01b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP870"              ,	   0x1180080e01b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP871"              ,	   0x1180080e01b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP872"              ,	   0x1180080e01b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP873"              ,	   0x1180080e01b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP874"              ,	   0x1180080e01b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP875"              ,	   0x1180080e01b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP876"              ,	   0x1180080e01b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP877"              ,	   0x1180080e01b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP878"              ,	   0x1180080e01b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP879"              ,	   0x1180080e01b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP880"              ,	   0x1180080e01b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP881"              ,	   0x1180080e01b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP882"              ,	   0x1180080e01b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP883"              ,	   0x1180080e01b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP884"              ,	   0x1180080e01ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP885"              ,	   0x1180080e01ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP886"              ,	   0x1180080e01bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP887"              ,	   0x1180080e01bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP888"              ,	   0x1180080e01bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP889"              ,	   0x1180080e01bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP890"              ,	   0x1180080e01bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP891"              ,	   0x1180080e01bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP892"              ,	   0x1180080e01be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP893"              ,	   0x1180080e01be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP894"              ,	   0x1180080e01bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP895"              ,	   0x1180080e01bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP896"              ,	   0x1180080e01c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP897"              ,	   0x1180080e01c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP898"              ,	   0x1180080e01c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP899"              ,	   0x1180080e01c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP900"              ,	   0x1180080e01c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP901"              ,	   0x1180080e01c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP902"              ,	   0x1180080e01c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP903"              ,	   0x1180080e01c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP904"              ,	   0x1180080e01c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP905"              ,	   0x1180080e01c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP906"              ,	   0x1180080e01c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP907"              ,	   0x1180080e01c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP908"              ,	   0x1180080e01c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP909"              ,	   0x1180080e01c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP910"              ,	   0x1180080e01c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP911"              ,	   0x1180080e01c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP912"              ,	   0x1180080e01c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP913"              ,	   0x1180080e01c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP914"              ,	   0x1180080e01c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP915"              ,	   0x1180080e01c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP916"              ,	   0x1180080e01ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP917"              ,	   0x1180080e01ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP918"              ,	   0x1180080e01cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP919"              ,	   0x1180080e01cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP920"              ,	   0x1180080e01cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP921"              ,	   0x1180080e01cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP922"              ,	   0x1180080e01cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP923"              ,	   0x1180080e01cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP924"              ,	   0x1180080e01ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP925"              ,	   0x1180080e01ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP926"              ,	   0x1180080e01cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP927"              ,	   0x1180080e01cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP928"              ,	   0x1180080e01d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP929"              ,	   0x1180080e01d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP930"              ,	   0x1180080e01d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP931"              ,	   0x1180080e01d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP932"              ,	   0x1180080e01d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP933"              ,	   0x1180080e01d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP934"              ,	   0x1180080e01d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP935"              ,	   0x1180080e01d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP936"              ,	   0x1180080e01d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP937"              ,	   0x1180080e01d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP938"              ,	   0x1180080e01d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP939"              ,	   0x1180080e01d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP940"              ,	   0x1180080e01d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP941"              ,	   0x1180080e01d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP942"              ,	   0x1180080e01d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP943"              ,	   0x1180080e01d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP944"              ,	   0x1180080e01d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP945"              ,	   0x1180080e01d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP946"              ,	   0x1180080e01d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP947"              ,	   0x1180080e01d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP948"              ,	   0x1180080e01da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP949"              ,	   0x1180080e01da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP950"              ,	   0x1180080e01db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP951"              ,	   0x1180080e01db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP952"              ,	   0x1180080e01dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP953"              ,	   0x1180080e01dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP954"              ,	   0x1180080e01dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP955"              ,	   0x1180080e01dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP956"              ,	   0x1180080e01de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP957"              ,	   0x1180080e01de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP958"              ,	   0x1180080e01df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP959"              ,	   0x1180080e01df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP960"              ,	   0x1180080e01e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP961"              ,	   0x1180080e01e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP962"              ,	   0x1180080e01e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP963"              ,	   0x1180080e01e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP964"              ,	   0x1180080e01e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP965"              ,	   0x1180080e01e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP966"              ,	   0x1180080e01e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP967"              ,	   0x1180080e01e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP968"              ,	   0x1180080e01e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP969"              ,	   0x1180080e01e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP970"              ,	   0x1180080e01e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP971"              ,	   0x1180080e01e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP972"              ,	   0x1180080e01e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP973"              ,	   0x1180080e01e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP974"              ,	   0x1180080e01e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP975"              ,	   0x1180080e01e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP976"              ,	   0x1180080e01e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP977"              ,	   0x1180080e01e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP978"              ,	   0x1180080e01e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP979"              ,	   0x1180080e01e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP980"              ,	   0x1180080e01ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP981"              ,	   0x1180080e01ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP982"              ,	   0x1180080e01eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP983"              ,	   0x1180080e01eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP984"              ,	   0x1180080e01ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP985"              ,	   0x1180080e01ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP986"              ,	   0x1180080e01ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP987"              ,	   0x1180080e01ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP988"              ,	   0x1180080e01ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP989"              ,	   0x1180080e01ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP990"              ,	   0x1180080e01ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP991"              ,	   0x1180080e01ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP992"              ,	   0x1180080e01f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP993"              ,	   0x1180080e01f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP994"              ,	   0x1180080e01f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP995"              ,	   0x1180080e01f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP996"              ,	   0x1180080e01f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP997"              ,	   0x1180080e01f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP998"              ,	   0x1180080e01f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP999"              ,	   0x1180080e01f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1000"             ,	   0x1180080e01f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1001"             ,	   0x1180080e01f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1002"             ,	   0x1180080e01f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1003"             ,	   0x1180080e01f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1004"             ,	   0x1180080e01f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1005"             ,	   0x1180080e01f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1006"             ,	   0x1180080e01f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1007"             ,	   0x1180080e01f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1008"             ,	   0x1180080e01f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1009"             ,	   0x1180080e01f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1010"             ,	   0x1180080e01f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1011"             ,	   0x1180080e01f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1012"             ,	   0x1180080e01fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1013"             ,	   0x1180080e01fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1014"             ,	   0x1180080e01fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1015"             ,	   0x1180080e01fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1016"             ,	   0x1180080e01fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1017"             ,	   0x1180080e01fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1018"             ,	   0x1180080e01fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1019"             ,	   0x1180080e01fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1020"             ,	   0x1180080e01fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1021"             ,	   0x1180080e01fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1022"             ,	   0x1180080e01ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1023"             ,	   0x1180080e01ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1024"             ,	   0x1180080e02000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1025"             ,	   0x1180080e02008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1026"             ,	   0x1180080e02010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1027"             ,	   0x1180080e02018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1028"             ,	   0x1180080e02020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1029"             ,	   0x1180080e02028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1030"             ,	   0x1180080e02030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1031"             ,	   0x1180080e02038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1032"             ,	   0x1180080e02040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1033"             ,	   0x1180080e02048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1034"             ,	   0x1180080e02050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1035"             ,	   0x1180080e02058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1036"             ,	   0x1180080e02060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1037"             ,	   0x1180080e02068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1038"             ,	   0x1180080e02070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1039"             ,	   0x1180080e02078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1040"             ,	   0x1180080e02080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1041"             ,	   0x1180080e02088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1042"             ,	   0x1180080e02090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1043"             ,	   0x1180080e02098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1044"             ,	   0x1180080e020a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1045"             ,	   0x1180080e020a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1046"             ,	   0x1180080e020b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1047"             ,	   0x1180080e020b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1048"             ,	   0x1180080e020c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1049"             ,	   0x1180080e020c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1050"             ,	   0x1180080e020d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1051"             ,	   0x1180080e020d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1052"             ,	   0x1180080e020e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1053"             ,	   0x1180080e020e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1054"             ,	   0x1180080e020f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1055"             ,	   0x1180080e020f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1056"             ,	   0x1180080e02100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1057"             ,	   0x1180080e02108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1058"             ,	   0x1180080e02110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1059"             ,	   0x1180080e02118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1060"             ,	   0x1180080e02120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1061"             ,	   0x1180080e02128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1062"             ,	   0x1180080e02130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1063"             ,	   0x1180080e02138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1064"             ,	   0x1180080e02140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1065"             ,	   0x1180080e02148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1066"             ,	   0x1180080e02150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1067"             ,	   0x1180080e02158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1068"             ,	   0x1180080e02160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1069"             ,	   0x1180080e02168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1070"             ,	   0x1180080e02170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1071"             ,	   0x1180080e02178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1072"             ,	   0x1180080e02180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1073"             ,	   0x1180080e02188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1074"             ,	   0x1180080e02190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1075"             ,	   0x1180080e02198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1076"             ,	   0x1180080e021a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1077"             ,	   0x1180080e021a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1078"             ,	   0x1180080e021b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1079"             ,	   0x1180080e021b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1080"             ,	   0x1180080e021c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1081"             ,	   0x1180080e021c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1082"             ,	   0x1180080e021d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1083"             ,	   0x1180080e021d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1084"             ,	   0x1180080e021e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1085"             ,	   0x1180080e021e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1086"             ,	   0x1180080e021f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1087"             ,	   0x1180080e021f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1088"             ,	   0x1180080e02200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1089"             ,	   0x1180080e02208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1090"             ,	   0x1180080e02210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1091"             ,	   0x1180080e02218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1092"             ,	   0x1180080e02220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1093"             ,	   0x1180080e02228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1094"             ,	   0x1180080e02230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1095"             ,	   0x1180080e02238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1096"             ,	   0x1180080e02240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1097"             ,	   0x1180080e02248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1098"             ,	   0x1180080e02250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1099"             ,	   0x1180080e02258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1100"             ,	   0x1180080e02260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1101"             ,	   0x1180080e02268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1102"             ,	   0x1180080e02270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1103"             ,	   0x1180080e02278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1104"             ,	   0x1180080e02280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1105"             ,	   0x1180080e02288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1106"             ,	   0x1180080e02290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1107"             ,	   0x1180080e02298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1108"             ,	   0x1180080e022a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1109"             ,	   0x1180080e022a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1110"             ,	   0x1180080e022b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1111"             ,	   0x1180080e022b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1112"             ,	   0x1180080e022c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1113"             ,	   0x1180080e022c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1114"             ,	   0x1180080e022d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1115"             ,	   0x1180080e022d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1116"             ,	   0x1180080e022e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1117"             ,	   0x1180080e022e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1118"             ,	   0x1180080e022f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1119"             ,	   0x1180080e022f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1120"             ,	   0x1180080e02300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1121"             ,	   0x1180080e02308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1122"             ,	   0x1180080e02310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1123"             ,	   0x1180080e02318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1124"             ,	   0x1180080e02320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1125"             ,	   0x1180080e02328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1126"             ,	   0x1180080e02330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1127"             ,	   0x1180080e02338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1128"             ,	   0x1180080e02340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1129"             ,	   0x1180080e02348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1130"             ,	   0x1180080e02350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1131"             ,	   0x1180080e02358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1132"             ,	   0x1180080e02360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1133"             ,	   0x1180080e02368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1134"             ,	   0x1180080e02370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1135"             ,	   0x1180080e02378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1136"             ,	   0x1180080e02380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1137"             ,	   0x1180080e02388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1138"             ,	   0x1180080e02390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1139"             ,	   0x1180080e02398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1140"             ,	   0x1180080e023a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1141"             ,	   0x1180080e023a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1142"             ,	   0x1180080e023b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1143"             ,	   0x1180080e023b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1144"             ,	   0x1180080e023c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1145"             ,	   0x1180080e023c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1146"             ,	   0x1180080e023d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1147"             ,	   0x1180080e023d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1148"             ,	   0x1180080e023e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1149"             ,	   0x1180080e023e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1150"             ,	   0x1180080e023f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1151"             ,	   0x1180080e023f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1152"             ,	   0x1180080e02400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1153"             ,	   0x1180080e02408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1154"             ,	   0x1180080e02410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1155"             ,	   0x1180080e02418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1156"             ,	   0x1180080e02420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1157"             ,	   0x1180080e02428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1158"             ,	   0x1180080e02430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1159"             ,	   0x1180080e02438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1160"             ,	   0x1180080e02440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1161"             ,	   0x1180080e02448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1162"             ,	   0x1180080e02450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1163"             ,	   0x1180080e02458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1164"             ,	   0x1180080e02460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1165"             ,	   0x1180080e02468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1166"             ,	   0x1180080e02470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1167"             ,	   0x1180080e02478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1168"             ,	   0x1180080e02480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1169"             ,	   0x1180080e02488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1170"             ,	   0x1180080e02490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1171"             ,	   0x1180080e02498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1172"             ,	   0x1180080e024a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1173"             ,	   0x1180080e024a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1174"             ,	   0x1180080e024b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1175"             ,	   0x1180080e024b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1176"             ,	   0x1180080e024c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1177"             ,	   0x1180080e024c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1178"             ,	   0x1180080e024d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1179"             ,	   0x1180080e024d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1180"             ,	   0x1180080e024e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1181"             ,	   0x1180080e024e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1182"             ,	   0x1180080e024f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1183"             ,	   0x1180080e024f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1184"             ,	   0x1180080e02500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1185"             ,	   0x1180080e02508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1186"             ,	   0x1180080e02510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1187"             ,	   0x1180080e02518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1188"             ,	   0x1180080e02520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1189"             ,	   0x1180080e02528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1190"             ,	   0x1180080e02530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1191"             ,	   0x1180080e02538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1192"             ,	   0x1180080e02540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1193"             ,	   0x1180080e02548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1194"             ,	   0x1180080e02550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1195"             ,	   0x1180080e02558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1196"             ,	   0x1180080e02560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1197"             ,	   0x1180080e02568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1198"             ,	   0x1180080e02570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1199"             ,	   0x1180080e02578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1200"             ,	   0x1180080e02580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1201"             ,	   0x1180080e02588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1202"             ,	   0x1180080e02590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1203"             ,	   0x1180080e02598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1204"             ,	   0x1180080e025a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1205"             ,	   0x1180080e025a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1206"             ,	   0x1180080e025b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1207"             ,	   0x1180080e025b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1208"             ,	   0x1180080e025c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1209"             ,	   0x1180080e025c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1210"             ,	   0x1180080e025d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1211"             ,	   0x1180080e025d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1212"             ,	   0x1180080e025e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1213"             ,	   0x1180080e025e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1214"             ,	   0x1180080e025f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1215"             ,	   0x1180080e025f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1216"             ,	   0x1180080e02600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1217"             ,	   0x1180080e02608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1218"             ,	   0x1180080e02610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1219"             ,	   0x1180080e02618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1220"             ,	   0x1180080e02620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1221"             ,	   0x1180080e02628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1222"             ,	   0x1180080e02630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1223"             ,	   0x1180080e02638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1224"             ,	   0x1180080e02640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1225"             ,	   0x1180080e02648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1226"             ,	   0x1180080e02650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1227"             ,	   0x1180080e02658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1228"             ,	   0x1180080e02660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1229"             ,	   0x1180080e02668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1230"             ,	   0x1180080e02670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1231"             ,	   0x1180080e02678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1232"             ,	   0x1180080e02680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1233"             ,	   0x1180080e02688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1234"             ,	   0x1180080e02690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1235"             ,	   0x1180080e02698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1236"             ,	   0x1180080e026a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1237"             ,	   0x1180080e026a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1238"             ,	   0x1180080e026b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1239"             ,	   0x1180080e026b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1240"             ,	   0x1180080e026c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1241"             ,	   0x1180080e026c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1242"             ,	   0x1180080e026d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1243"             ,	   0x1180080e026d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1244"             ,	   0x1180080e026e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1245"             ,	   0x1180080e026e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1246"             ,	   0x1180080e026f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1247"             ,	   0x1180080e026f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1248"             ,	   0x1180080e02700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1249"             ,	   0x1180080e02708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1250"             ,	   0x1180080e02710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1251"             ,	   0x1180080e02718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1252"             ,	   0x1180080e02720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1253"             ,	   0x1180080e02728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1254"             ,	   0x1180080e02730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1255"             ,	   0x1180080e02738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1256"             ,	   0x1180080e02740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1257"             ,	   0x1180080e02748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1258"             ,	   0x1180080e02750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1259"             ,	   0x1180080e02758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1260"             ,	   0x1180080e02760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1261"             ,	   0x1180080e02768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1262"             ,	   0x1180080e02770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1263"             ,	   0x1180080e02778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1264"             ,	   0x1180080e02780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1265"             ,	   0x1180080e02788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1266"             ,	   0x1180080e02790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1267"             ,	   0x1180080e02798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1268"             ,	   0x1180080e027a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1269"             ,	   0x1180080e027a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1270"             ,	   0x1180080e027b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1271"             ,	   0x1180080e027b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1272"             ,	   0x1180080e027c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1273"             ,	   0x1180080e027c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1274"             ,	   0x1180080e027d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1275"             ,	   0x1180080e027d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1276"             ,	   0x1180080e027e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1277"             ,	   0x1180080e027e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1278"             ,	   0x1180080e027f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1279"             ,	   0x1180080e027f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1280"             ,	   0x1180080e02800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1281"             ,	   0x1180080e02808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1282"             ,	   0x1180080e02810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1283"             ,	   0x1180080e02818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1284"             ,	   0x1180080e02820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1285"             ,	   0x1180080e02828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1286"             ,	   0x1180080e02830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1287"             ,	   0x1180080e02838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1288"             ,	   0x1180080e02840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1289"             ,	   0x1180080e02848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1290"             ,	   0x1180080e02850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1291"             ,	   0x1180080e02858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1292"             ,	   0x1180080e02860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1293"             ,	   0x1180080e02868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1294"             ,	   0x1180080e02870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1295"             ,	   0x1180080e02878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1296"             ,	   0x1180080e02880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1297"             ,	   0x1180080e02888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1298"             ,	   0x1180080e02890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1299"             ,	   0x1180080e02898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1300"             ,	   0x1180080e028a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1301"             ,	   0x1180080e028a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1302"             ,	   0x1180080e028b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1303"             ,	   0x1180080e028b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1304"             ,	   0x1180080e028c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1305"             ,	   0x1180080e028c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1306"             ,	   0x1180080e028d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1307"             ,	   0x1180080e028d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1308"             ,	   0x1180080e028e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1309"             ,	   0x1180080e028e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1310"             ,	   0x1180080e028f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1311"             ,	   0x1180080e028f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1312"             ,	   0x1180080e02900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1313"             ,	   0x1180080e02908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1314"             ,	   0x1180080e02910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1315"             ,	   0x1180080e02918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1316"             ,	   0x1180080e02920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1317"             ,	   0x1180080e02928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1318"             ,	   0x1180080e02930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1319"             ,	   0x1180080e02938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1320"             ,	   0x1180080e02940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1321"             ,	   0x1180080e02948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1322"             ,	   0x1180080e02950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1323"             ,	   0x1180080e02958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1324"             ,	   0x1180080e02960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1325"             ,	   0x1180080e02968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1326"             ,	   0x1180080e02970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1327"             ,	   0x1180080e02978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1328"             ,	   0x1180080e02980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1329"             ,	   0x1180080e02988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1330"             ,	   0x1180080e02990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1331"             ,	   0x1180080e02998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1332"             ,	   0x1180080e029a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1333"             ,	   0x1180080e029a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1334"             ,	   0x1180080e029b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1335"             ,	   0x1180080e029b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1336"             ,	   0x1180080e029c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1337"             ,	   0x1180080e029c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1338"             ,	   0x1180080e029d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1339"             ,	   0x1180080e029d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1340"             ,	   0x1180080e029e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1341"             ,	   0x1180080e029e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1342"             ,	   0x1180080e029f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1343"             ,	   0x1180080e029f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1344"             ,	   0x1180080e02a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1345"             ,	   0x1180080e02a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1346"             ,	   0x1180080e02a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1347"             ,	   0x1180080e02a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1348"             ,	   0x1180080e02a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1349"             ,	   0x1180080e02a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1350"             ,	   0x1180080e02a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1351"             ,	   0x1180080e02a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1352"             ,	   0x1180080e02a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1353"             ,	   0x1180080e02a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1354"             ,	   0x1180080e02a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1355"             ,	   0x1180080e02a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1356"             ,	   0x1180080e02a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1357"             ,	   0x1180080e02a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1358"             ,	   0x1180080e02a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1359"             ,	   0x1180080e02a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1360"             ,	   0x1180080e02a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1361"             ,	   0x1180080e02a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1362"             ,	   0x1180080e02a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1363"             ,	   0x1180080e02a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1364"             ,	   0x1180080e02aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1365"             ,	   0x1180080e02aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1366"             ,	   0x1180080e02ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1367"             ,	   0x1180080e02ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1368"             ,	   0x1180080e02ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1369"             ,	   0x1180080e02ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1370"             ,	   0x1180080e02ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1371"             ,	   0x1180080e02ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1372"             ,	   0x1180080e02ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1373"             ,	   0x1180080e02ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1374"             ,	   0x1180080e02af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1375"             ,	   0x1180080e02af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1376"             ,	   0x1180080e02b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1377"             ,	   0x1180080e02b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1378"             ,	   0x1180080e02b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1379"             ,	   0x1180080e02b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1380"             ,	   0x1180080e02b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1381"             ,	   0x1180080e02b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1382"             ,	   0x1180080e02b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1383"             ,	   0x1180080e02b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1384"             ,	   0x1180080e02b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1385"             ,	   0x1180080e02b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1386"             ,	   0x1180080e02b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1387"             ,	   0x1180080e02b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1388"             ,	   0x1180080e02b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1389"             ,	   0x1180080e02b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1390"             ,	   0x1180080e02b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1391"             ,	   0x1180080e02b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1392"             ,	   0x1180080e02b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1393"             ,	   0x1180080e02b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1394"             ,	   0x1180080e02b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1395"             ,	   0x1180080e02b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1396"             ,	   0x1180080e02ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1397"             ,	   0x1180080e02ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1398"             ,	   0x1180080e02bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1399"             ,	   0x1180080e02bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1400"             ,	   0x1180080e02bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1401"             ,	   0x1180080e02bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1402"             ,	   0x1180080e02bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1403"             ,	   0x1180080e02bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1404"             ,	   0x1180080e02be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1405"             ,	   0x1180080e02be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1406"             ,	   0x1180080e02bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1407"             ,	   0x1180080e02bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1408"             ,	   0x1180080e02c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1409"             ,	   0x1180080e02c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1410"             ,	   0x1180080e02c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1411"             ,	   0x1180080e02c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1412"             ,	   0x1180080e02c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1413"             ,	   0x1180080e02c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1414"             ,	   0x1180080e02c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1415"             ,	   0x1180080e02c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1416"             ,	   0x1180080e02c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1417"             ,	   0x1180080e02c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1418"             ,	   0x1180080e02c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1419"             ,	   0x1180080e02c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1420"             ,	   0x1180080e02c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1421"             ,	   0x1180080e02c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1422"             ,	   0x1180080e02c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1423"             ,	   0x1180080e02c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1424"             ,	   0x1180080e02c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1425"             ,	   0x1180080e02c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1426"             ,	   0x1180080e02c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1427"             ,	   0x1180080e02c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1428"             ,	   0x1180080e02ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1429"             ,	   0x1180080e02ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1430"             ,	   0x1180080e02cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1431"             ,	   0x1180080e02cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1432"             ,	   0x1180080e02cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1433"             ,	   0x1180080e02cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1434"             ,	   0x1180080e02cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1435"             ,	   0x1180080e02cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1436"             ,	   0x1180080e02ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1437"             ,	   0x1180080e02ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1438"             ,	   0x1180080e02cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1439"             ,	   0x1180080e02cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1440"             ,	   0x1180080e02d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1441"             ,	   0x1180080e02d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1442"             ,	   0x1180080e02d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1443"             ,	   0x1180080e02d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1444"             ,	   0x1180080e02d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1445"             ,	   0x1180080e02d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1446"             ,	   0x1180080e02d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1447"             ,	   0x1180080e02d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1448"             ,	   0x1180080e02d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1449"             ,	   0x1180080e02d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1450"             ,	   0x1180080e02d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1451"             ,	   0x1180080e02d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1452"             ,	   0x1180080e02d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1453"             ,	   0x1180080e02d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1454"             ,	   0x1180080e02d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1455"             ,	   0x1180080e02d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1456"             ,	   0x1180080e02d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1457"             ,	   0x1180080e02d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1458"             ,	   0x1180080e02d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1459"             ,	   0x1180080e02d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1460"             ,	   0x1180080e02da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1461"             ,	   0x1180080e02da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1462"             ,	   0x1180080e02db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1463"             ,	   0x1180080e02db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1464"             ,	   0x1180080e02dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1465"             ,	   0x1180080e02dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1466"             ,	   0x1180080e02dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1467"             ,	   0x1180080e02dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1468"             ,	   0x1180080e02de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1469"             ,	   0x1180080e02de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1470"             ,	   0x1180080e02df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1471"             ,	   0x1180080e02df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1472"             ,	   0x1180080e02e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1473"             ,	   0x1180080e02e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1474"             ,	   0x1180080e02e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1475"             ,	   0x1180080e02e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1476"             ,	   0x1180080e02e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1477"             ,	   0x1180080e02e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1478"             ,	   0x1180080e02e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1479"             ,	   0x1180080e02e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1480"             ,	   0x1180080e02e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1481"             ,	   0x1180080e02e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1482"             ,	   0x1180080e02e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1483"             ,	   0x1180080e02e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1484"             ,	   0x1180080e02e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1485"             ,	   0x1180080e02e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1486"             ,	   0x1180080e02e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1487"             ,	   0x1180080e02e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1488"             ,	   0x1180080e02e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1489"             ,	   0x1180080e02e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1490"             ,	   0x1180080e02e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1491"             ,	   0x1180080e02e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1492"             ,	   0x1180080e02ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1493"             ,	   0x1180080e02ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1494"             ,	   0x1180080e02eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1495"             ,	   0x1180080e02eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1496"             ,	   0x1180080e02ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1497"             ,	   0x1180080e02ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1498"             ,	   0x1180080e02ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1499"             ,	   0x1180080e02ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1500"             ,	   0x1180080e02ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1501"             ,	   0x1180080e02ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1502"             ,	   0x1180080e02ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1503"             ,	   0x1180080e02ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1504"             ,	   0x1180080e02f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1505"             ,	   0x1180080e02f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1506"             ,	   0x1180080e02f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1507"             ,	   0x1180080e02f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1508"             ,	   0x1180080e02f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1509"             ,	   0x1180080e02f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1510"             ,	   0x1180080e02f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1511"             ,	   0x1180080e02f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1512"             ,	   0x1180080e02f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1513"             ,	   0x1180080e02f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1514"             ,	   0x1180080e02f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1515"             ,	   0x1180080e02f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1516"             ,	   0x1180080e02f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1517"             ,	   0x1180080e02f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1518"             ,	   0x1180080e02f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1519"             ,	   0x1180080e02f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1520"             ,	   0x1180080e02f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1521"             ,	   0x1180080e02f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1522"             ,	   0x1180080e02f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1523"             ,	   0x1180080e02f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1524"             ,	   0x1180080e02fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1525"             ,	   0x1180080e02fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1526"             ,	   0x1180080e02fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1527"             ,	   0x1180080e02fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1528"             ,	   0x1180080e02fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1529"             ,	   0x1180080e02fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1530"             ,	   0x1180080e02fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1531"             ,	   0x1180080e02fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1532"             ,	   0x1180080e02fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1533"             ,	   0x1180080e02fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1534"             ,	   0x1180080e02ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1535"             ,	   0x1180080e02ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1536"             ,	   0x1180080e03000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1537"             ,	   0x1180080e03008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1538"             ,	   0x1180080e03010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1539"             ,	   0x1180080e03018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1540"             ,	   0x1180080e03020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1541"             ,	   0x1180080e03028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1542"             ,	   0x1180080e03030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1543"             ,	   0x1180080e03038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1544"             ,	   0x1180080e03040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1545"             ,	   0x1180080e03048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1546"             ,	   0x1180080e03050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1547"             ,	   0x1180080e03058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1548"             ,	   0x1180080e03060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1549"             ,	   0x1180080e03068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1550"             ,	   0x1180080e03070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1551"             ,	   0x1180080e03078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1552"             ,	   0x1180080e03080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1553"             ,	   0x1180080e03088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1554"             ,	   0x1180080e03090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1555"             ,	   0x1180080e03098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1556"             ,	   0x1180080e030a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1557"             ,	   0x1180080e030a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1558"             ,	   0x1180080e030b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1559"             ,	   0x1180080e030b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1560"             ,	   0x1180080e030c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1561"             ,	   0x1180080e030c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1562"             ,	   0x1180080e030d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1563"             ,	   0x1180080e030d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1564"             ,	   0x1180080e030e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1565"             ,	   0x1180080e030e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1566"             ,	   0x1180080e030f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1567"             ,	   0x1180080e030f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1568"             ,	   0x1180080e03100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1569"             ,	   0x1180080e03108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1570"             ,	   0x1180080e03110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1571"             ,	   0x1180080e03118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1572"             ,	   0x1180080e03120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1573"             ,	   0x1180080e03128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1574"             ,	   0x1180080e03130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1575"             ,	   0x1180080e03138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1576"             ,	   0x1180080e03140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1577"             ,	   0x1180080e03148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1578"             ,	   0x1180080e03150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1579"             ,	   0x1180080e03158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1580"             ,	   0x1180080e03160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1581"             ,	   0x1180080e03168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1582"             ,	   0x1180080e03170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1583"             ,	   0x1180080e03178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1584"             ,	   0x1180080e03180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1585"             ,	   0x1180080e03188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1586"             ,	   0x1180080e03190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1587"             ,	   0x1180080e03198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1588"             ,	   0x1180080e031a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1589"             ,	   0x1180080e031a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1590"             ,	   0x1180080e031b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1591"             ,	   0x1180080e031b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1592"             ,	   0x1180080e031c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1593"             ,	   0x1180080e031c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1594"             ,	   0x1180080e031d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1595"             ,	   0x1180080e031d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1596"             ,	   0x1180080e031e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1597"             ,	   0x1180080e031e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1598"             ,	   0x1180080e031f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1599"             ,	   0x1180080e031f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1600"             ,	   0x1180080e03200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1601"             ,	   0x1180080e03208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1602"             ,	   0x1180080e03210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1603"             ,	   0x1180080e03218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1604"             ,	   0x1180080e03220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1605"             ,	   0x1180080e03228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1606"             ,	   0x1180080e03230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1607"             ,	   0x1180080e03238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1608"             ,	   0x1180080e03240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1609"             ,	   0x1180080e03248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1610"             ,	   0x1180080e03250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1611"             ,	   0x1180080e03258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1612"             ,	   0x1180080e03260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1613"             ,	   0x1180080e03268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1614"             ,	   0x1180080e03270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1615"             ,	   0x1180080e03278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1616"             ,	   0x1180080e03280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1617"             ,	   0x1180080e03288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1618"             ,	   0x1180080e03290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1619"             ,	   0x1180080e03298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1620"             ,	   0x1180080e032a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1621"             ,	   0x1180080e032a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1622"             ,	   0x1180080e032b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1623"             ,	   0x1180080e032b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1624"             ,	   0x1180080e032c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1625"             ,	   0x1180080e032c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1626"             ,	   0x1180080e032d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1627"             ,	   0x1180080e032d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1628"             ,	   0x1180080e032e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1629"             ,	   0x1180080e032e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1630"             ,	   0x1180080e032f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1631"             ,	   0x1180080e032f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1632"             ,	   0x1180080e03300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1633"             ,	   0x1180080e03308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1634"             ,	   0x1180080e03310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1635"             ,	   0x1180080e03318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1636"             ,	   0x1180080e03320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1637"             ,	   0x1180080e03328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1638"             ,	   0x1180080e03330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1639"             ,	   0x1180080e03338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1640"             ,	   0x1180080e03340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1641"             ,	   0x1180080e03348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1642"             ,	   0x1180080e03350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1643"             ,	   0x1180080e03358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1644"             ,	   0x1180080e03360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1645"             ,	   0x1180080e03368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1646"             ,	   0x1180080e03370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1647"             ,	   0x1180080e03378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1648"             ,	   0x1180080e03380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1649"             ,	   0x1180080e03388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1650"             ,	   0x1180080e03390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1651"             ,	   0x1180080e03398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1652"             ,	   0x1180080e033a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1653"             ,	   0x1180080e033a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1654"             ,	   0x1180080e033b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1655"             ,	   0x1180080e033b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1656"             ,	   0x1180080e033c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1657"             ,	   0x1180080e033c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1658"             ,	   0x1180080e033d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1659"             ,	   0x1180080e033d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1660"             ,	   0x1180080e033e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1661"             ,	   0x1180080e033e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1662"             ,	   0x1180080e033f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1663"             ,	   0x1180080e033f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1664"             ,	   0x1180080e03400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1665"             ,	   0x1180080e03408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1666"             ,	   0x1180080e03410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1667"             ,	   0x1180080e03418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1668"             ,	   0x1180080e03420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1669"             ,	   0x1180080e03428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1670"             ,	   0x1180080e03430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1671"             ,	   0x1180080e03438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1672"             ,	   0x1180080e03440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1673"             ,	   0x1180080e03448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1674"             ,	   0x1180080e03450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1675"             ,	   0x1180080e03458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1676"             ,	   0x1180080e03460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1677"             ,	   0x1180080e03468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1678"             ,	   0x1180080e03470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1679"             ,	   0x1180080e03478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1680"             ,	   0x1180080e03480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1681"             ,	   0x1180080e03488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1682"             ,	   0x1180080e03490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1683"             ,	   0x1180080e03498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1684"             ,	   0x1180080e034a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1685"             ,	   0x1180080e034a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1686"             ,	   0x1180080e034b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1687"             ,	   0x1180080e034b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1688"             ,	   0x1180080e034c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1689"             ,	   0x1180080e034c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1690"             ,	   0x1180080e034d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1691"             ,	   0x1180080e034d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1692"             ,	   0x1180080e034e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1693"             ,	   0x1180080e034e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1694"             ,	   0x1180080e034f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1695"             ,	   0x1180080e034f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1696"             ,	   0x1180080e03500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1697"             ,	   0x1180080e03508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1698"             ,	   0x1180080e03510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1699"             ,	   0x1180080e03518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1700"             ,	   0x1180080e03520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1701"             ,	   0x1180080e03528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1702"             ,	   0x1180080e03530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1703"             ,	   0x1180080e03538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1704"             ,	   0x1180080e03540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1705"             ,	   0x1180080e03548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1706"             ,	   0x1180080e03550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1707"             ,	   0x1180080e03558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1708"             ,	   0x1180080e03560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1709"             ,	   0x1180080e03568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1710"             ,	   0x1180080e03570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1711"             ,	   0x1180080e03578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1712"             ,	   0x1180080e03580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1713"             ,	   0x1180080e03588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1714"             ,	   0x1180080e03590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1715"             ,	   0x1180080e03598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1716"             ,	   0x1180080e035a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1717"             ,	   0x1180080e035a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1718"             ,	   0x1180080e035b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1719"             ,	   0x1180080e035b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1720"             ,	   0x1180080e035c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1721"             ,	   0x1180080e035c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1722"             ,	   0x1180080e035d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1723"             ,	   0x1180080e035d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1724"             ,	   0x1180080e035e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1725"             ,	   0x1180080e035e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1726"             ,	   0x1180080e035f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1727"             ,	   0x1180080e035f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1728"             ,	   0x1180080e03600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1729"             ,	   0x1180080e03608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1730"             ,	   0x1180080e03610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1731"             ,	   0x1180080e03618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1732"             ,	   0x1180080e03620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1733"             ,	   0x1180080e03628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1734"             ,	   0x1180080e03630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1735"             ,	   0x1180080e03638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1736"             ,	   0x1180080e03640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1737"             ,	   0x1180080e03648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1738"             ,	   0x1180080e03650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1739"             ,	   0x1180080e03658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1740"             ,	   0x1180080e03660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1741"             ,	   0x1180080e03668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1742"             ,	   0x1180080e03670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1743"             ,	   0x1180080e03678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1744"             ,	   0x1180080e03680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1745"             ,	   0x1180080e03688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1746"             ,	   0x1180080e03690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1747"             ,	   0x1180080e03698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1748"             ,	   0x1180080e036a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1749"             ,	   0x1180080e036a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1750"             ,	   0x1180080e036b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1751"             ,	   0x1180080e036b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1752"             ,	   0x1180080e036c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1753"             ,	   0x1180080e036c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1754"             ,	   0x1180080e036d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1755"             ,	   0x1180080e036d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1756"             ,	   0x1180080e036e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1757"             ,	   0x1180080e036e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1758"             ,	   0x1180080e036f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1759"             ,	   0x1180080e036f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1760"             ,	   0x1180080e03700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1761"             ,	   0x1180080e03708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1762"             ,	   0x1180080e03710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1763"             ,	   0x1180080e03718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1764"             ,	   0x1180080e03720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1765"             ,	   0x1180080e03728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1766"             ,	   0x1180080e03730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1767"             ,	   0x1180080e03738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1768"             ,	   0x1180080e03740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1769"             ,	   0x1180080e03748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1770"             ,	   0x1180080e03750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1771"             ,	   0x1180080e03758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1772"             ,	   0x1180080e03760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1773"             ,	   0x1180080e03768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1774"             ,	   0x1180080e03770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1775"             ,	   0x1180080e03778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1776"             ,	   0x1180080e03780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1777"             ,	   0x1180080e03788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1778"             ,	   0x1180080e03790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1779"             ,	   0x1180080e03798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1780"             ,	   0x1180080e037a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1781"             ,	   0x1180080e037a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1782"             ,	   0x1180080e037b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1783"             ,	   0x1180080e037b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1784"             ,	   0x1180080e037c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1785"             ,	   0x1180080e037c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1786"             ,	   0x1180080e037d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1787"             ,	   0x1180080e037d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1788"             ,	   0x1180080e037e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1789"             ,	   0x1180080e037e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1790"             ,	   0x1180080e037f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1791"             ,	   0x1180080e037f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1792"             ,	   0x1180080e03800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1793"             ,	   0x1180080e03808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1794"             ,	   0x1180080e03810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1795"             ,	   0x1180080e03818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1796"             ,	   0x1180080e03820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1797"             ,	   0x1180080e03828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1798"             ,	   0x1180080e03830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1799"             ,	   0x1180080e03838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1800"             ,	   0x1180080e03840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1801"             ,	   0x1180080e03848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1802"             ,	   0x1180080e03850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1803"             ,	   0x1180080e03858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1804"             ,	   0x1180080e03860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1805"             ,	   0x1180080e03868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1806"             ,	   0x1180080e03870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1807"             ,	   0x1180080e03878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1808"             ,	   0x1180080e03880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1809"             ,	   0x1180080e03888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1810"             ,	   0x1180080e03890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1811"             ,	   0x1180080e03898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1812"             ,	   0x1180080e038a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1813"             ,	   0x1180080e038a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1814"             ,	   0x1180080e038b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1815"             ,	   0x1180080e038b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1816"             ,	   0x1180080e038c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1817"             ,	   0x1180080e038c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1818"             ,	   0x1180080e038d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1819"             ,	   0x1180080e038d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1820"             ,	   0x1180080e038e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1821"             ,	   0x1180080e038e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1822"             ,	   0x1180080e038f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1823"             ,	   0x1180080e038f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1824"             ,	   0x1180080e03900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1825"             ,	   0x1180080e03908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1826"             ,	   0x1180080e03910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1827"             ,	   0x1180080e03918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1828"             ,	   0x1180080e03920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1829"             ,	   0x1180080e03928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1830"             ,	   0x1180080e03930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1831"             ,	   0x1180080e03938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1832"             ,	   0x1180080e03940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1833"             ,	   0x1180080e03948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1834"             ,	   0x1180080e03950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1835"             ,	   0x1180080e03958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1836"             ,	   0x1180080e03960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1837"             ,	   0x1180080e03968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1838"             ,	   0x1180080e03970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1839"             ,	   0x1180080e03978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1840"             ,	   0x1180080e03980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1841"             ,	   0x1180080e03988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1842"             ,	   0x1180080e03990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1843"             ,	   0x1180080e03998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1844"             ,	   0x1180080e039a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1845"             ,	   0x1180080e039a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1846"             ,	   0x1180080e039b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1847"             ,	   0x1180080e039b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1848"             ,	   0x1180080e039c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1849"             ,	   0x1180080e039c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1850"             ,	   0x1180080e039d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1851"             ,	   0x1180080e039d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1852"             ,	   0x1180080e039e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1853"             ,	   0x1180080e039e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1854"             ,	   0x1180080e039f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1855"             ,	   0x1180080e039f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1856"             ,	   0x1180080e03a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1857"             ,	   0x1180080e03a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1858"             ,	   0x1180080e03a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1859"             ,	   0x1180080e03a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1860"             ,	   0x1180080e03a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1861"             ,	   0x1180080e03a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1862"             ,	   0x1180080e03a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1863"             ,	   0x1180080e03a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1864"             ,	   0x1180080e03a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1865"             ,	   0x1180080e03a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1866"             ,	   0x1180080e03a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1867"             ,	   0x1180080e03a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1868"             ,	   0x1180080e03a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1869"             ,	   0x1180080e03a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1870"             ,	   0x1180080e03a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1871"             ,	   0x1180080e03a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1872"             ,	   0x1180080e03a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1873"             ,	   0x1180080e03a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1874"             ,	   0x1180080e03a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1875"             ,	   0x1180080e03a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1876"             ,	   0x1180080e03aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1877"             ,	   0x1180080e03aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1878"             ,	   0x1180080e03ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1879"             ,	   0x1180080e03ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1880"             ,	   0x1180080e03ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1881"             ,	   0x1180080e03ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1882"             ,	   0x1180080e03ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1883"             ,	   0x1180080e03ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1884"             ,	   0x1180080e03ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1885"             ,	   0x1180080e03ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1886"             ,	   0x1180080e03af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1887"             ,	   0x1180080e03af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1888"             ,	   0x1180080e03b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1889"             ,	   0x1180080e03b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1890"             ,	   0x1180080e03b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1891"             ,	   0x1180080e03b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1892"             ,	   0x1180080e03b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1893"             ,	   0x1180080e03b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1894"             ,	   0x1180080e03b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1895"             ,	   0x1180080e03b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1896"             ,	   0x1180080e03b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1897"             ,	   0x1180080e03b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1898"             ,	   0x1180080e03b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1899"             ,	   0x1180080e03b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1900"             ,	   0x1180080e03b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1901"             ,	   0x1180080e03b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1902"             ,	   0x1180080e03b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1903"             ,	   0x1180080e03b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1904"             ,	   0x1180080e03b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1905"             ,	   0x1180080e03b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1906"             ,	   0x1180080e03b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1907"             ,	   0x1180080e03b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1908"             ,	   0x1180080e03ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1909"             ,	   0x1180080e03ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1910"             ,	   0x1180080e03bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1911"             ,	   0x1180080e03bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1912"             ,	   0x1180080e03bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1913"             ,	   0x1180080e03bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1914"             ,	   0x1180080e03bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1915"             ,	   0x1180080e03bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1916"             ,	   0x1180080e03be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1917"             ,	   0x1180080e03be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1918"             ,	   0x1180080e03bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1919"             ,	   0x1180080e03bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1920"             ,	   0x1180080e03c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1921"             ,	   0x1180080e03c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1922"             ,	   0x1180080e03c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1923"             ,	   0x1180080e03c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1924"             ,	   0x1180080e03c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1925"             ,	   0x1180080e03c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1926"             ,	   0x1180080e03c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1927"             ,	   0x1180080e03c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1928"             ,	   0x1180080e03c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1929"             ,	   0x1180080e03c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1930"             ,	   0x1180080e03c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1931"             ,	   0x1180080e03c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1932"             ,	   0x1180080e03c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1933"             ,	   0x1180080e03c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1934"             ,	   0x1180080e03c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1935"             ,	   0x1180080e03c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1936"             ,	   0x1180080e03c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1937"             ,	   0x1180080e03c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1938"             ,	   0x1180080e03c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1939"             ,	   0x1180080e03c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1940"             ,	   0x1180080e03ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1941"             ,	   0x1180080e03ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1942"             ,	   0x1180080e03cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1943"             ,	   0x1180080e03cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1944"             ,	   0x1180080e03cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1945"             ,	   0x1180080e03cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1946"             ,	   0x1180080e03cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1947"             ,	   0x1180080e03cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1948"             ,	   0x1180080e03ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1949"             ,	   0x1180080e03ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1950"             ,	   0x1180080e03cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1951"             ,	   0x1180080e03cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1952"             ,	   0x1180080e03d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1953"             ,	   0x1180080e03d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1954"             ,	   0x1180080e03d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1955"             ,	   0x1180080e03d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1956"             ,	   0x1180080e03d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1957"             ,	   0x1180080e03d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1958"             ,	   0x1180080e03d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1959"             ,	   0x1180080e03d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1960"             ,	   0x1180080e03d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1961"             ,	   0x1180080e03d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1962"             ,	   0x1180080e03d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1963"             ,	   0x1180080e03d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1964"             ,	   0x1180080e03d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1965"             ,	   0x1180080e03d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1966"             ,	   0x1180080e03d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1967"             ,	   0x1180080e03d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1968"             ,	   0x1180080e03d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1969"             ,	   0x1180080e03d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1970"             ,	   0x1180080e03d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1971"             ,	   0x1180080e03d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1972"             ,	   0x1180080e03da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1973"             ,	   0x1180080e03da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1974"             ,	   0x1180080e03db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1975"             ,	   0x1180080e03db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1976"             ,	   0x1180080e03dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1977"             ,	   0x1180080e03dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1978"             ,	   0x1180080e03dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1979"             ,	   0x1180080e03dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1980"             ,	   0x1180080e03de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1981"             ,	   0x1180080e03de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1982"             ,	   0x1180080e03df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1983"             ,	   0x1180080e03df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1984"             ,	   0x1180080e03e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1985"             ,	   0x1180080e03e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1986"             ,	   0x1180080e03e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1987"             ,	   0x1180080e03e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1988"             ,	   0x1180080e03e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1989"             ,	   0x1180080e03e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1990"             ,	   0x1180080e03e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1991"             ,	   0x1180080e03e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1992"             ,	   0x1180080e03e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1993"             ,	   0x1180080e03e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1994"             ,	   0x1180080e03e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1995"             ,	   0x1180080e03e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1996"             ,	   0x1180080e03e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1997"             ,	   0x1180080e03e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1998"             ,	   0x1180080e03e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP1999"             ,	   0x1180080e03e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2000"             ,	   0x1180080e03e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2001"             ,	   0x1180080e03e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2002"             ,	   0x1180080e03e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2003"             ,	   0x1180080e03e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2004"             ,	   0x1180080e03ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2005"             ,	   0x1180080e03ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2006"             ,	   0x1180080e03eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2007"             ,	   0x1180080e03eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2008"             ,	   0x1180080e03ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2009"             ,	   0x1180080e03ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2010"             ,	   0x1180080e03ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2011"             ,	   0x1180080e03ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2012"             ,	   0x1180080e03ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2013"             ,	   0x1180080e03ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2014"             ,	   0x1180080e03ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2015"             ,	   0x1180080e03ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2016"             ,	   0x1180080e03f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2017"             ,	   0x1180080e03f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2018"             ,	   0x1180080e03f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2019"             ,	   0x1180080e03f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2020"             ,	   0x1180080e03f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2021"             ,	   0x1180080e03f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2022"             ,	   0x1180080e03f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2023"             ,	   0x1180080e03f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2024"             ,	   0x1180080e03f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2025"             ,	   0x1180080e03f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2026"             ,	   0x1180080e03f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2027"             ,	   0x1180080e03f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2028"             ,	   0x1180080e03f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2029"             ,	   0x1180080e03f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2030"             ,	   0x1180080e03f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2031"             ,	   0x1180080e03f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2032"             ,	   0x1180080e03f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2033"             ,	   0x1180080e03f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2034"             ,	   0x1180080e03f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2035"             ,	   0x1180080e03f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2036"             ,	   0x1180080e03fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2037"             ,	   0x1180080e03fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2038"             ,	   0x1180080e03fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2039"             ,	   0x1180080e03fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2040"             ,	   0x1180080e03fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2041"             ,	   0x1180080e03fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2042"             ,	   0x1180080e03fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2043"             ,	   0x1180080e03fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2044"             ,	   0x1180080e03fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2045"             ,	   0x1180080e03fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2046"             ,	   0x1180080e03ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2047"             ,	   0x1180080e03ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2048"             ,	   0x1180080e04000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2049"             ,	   0x1180080e04008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2050"             ,	   0x1180080e04010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2051"             ,	   0x1180080e04018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2052"             ,	   0x1180080e04020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2053"             ,	   0x1180080e04028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2054"             ,	   0x1180080e04030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2055"             ,	   0x1180080e04038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2056"             ,	   0x1180080e04040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2057"             ,	   0x1180080e04048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2058"             ,	   0x1180080e04050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2059"             ,	   0x1180080e04058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2060"             ,	   0x1180080e04060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2061"             ,	   0x1180080e04068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2062"             ,	   0x1180080e04070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2063"             ,	   0x1180080e04078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2064"             ,	   0x1180080e04080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2065"             ,	   0x1180080e04088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2066"             ,	   0x1180080e04090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2067"             ,	   0x1180080e04098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2068"             ,	   0x1180080e040a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2069"             ,	   0x1180080e040a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2070"             ,	   0x1180080e040b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2071"             ,	   0x1180080e040b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2072"             ,	   0x1180080e040c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2073"             ,	   0x1180080e040c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2074"             ,	   0x1180080e040d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2075"             ,	   0x1180080e040d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2076"             ,	   0x1180080e040e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2077"             ,	   0x1180080e040e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2078"             ,	   0x1180080e040f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2079"             ,	   0x1180080e040f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2080"             ,	   0x1180080e04100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2081"             ,	   0x1180080e04108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2082"             ,	   0x1180080e04110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2083"             ,	   0x1180080e04118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2084"             ,	   0x1180080e04120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2085"             ,	   0x1180080e04128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2086"             ,	   0x1180080e04130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2087"             ,	   0x1180080e04138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2088"             ,	   0x1180080e04140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2089"             ,	   0x1180080e04148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2090"             ,	   0x1180080e04150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2091"             ,	   0x1180080e04158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2092"             ,	   0x1180080e04160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2093"             ,	   0x1180080e04168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2094"             ,	   0x1180080e04170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2095"             ,	   0x1180080e04178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2096"             ,	   0x1180080e04180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2097"             ,	   0x1180080e04188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2098"             ,	   0x1180080e04190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2099"             ,	   0x1180080e04198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2100"             ,	   0x1180080e041a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2101"             ,	   0x1180080e041a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2102"             ,	   0x1180080e041b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2103"             ,	   0x1180080e041b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2104"             ,	   0x1180080e041c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2105"             ,	   0x1180080e041c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2106"             ,	   0x1180080e041d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2107"             ,	   0x1180080e041d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2108"             ,	   0x1180080e041e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2109"             ,	   0x1180080e041e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2110"             ,	   0x1180080e041f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2111"             ,	   0x1180080e041f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2112"             ,	   0x1180080e04200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2113"             ,	   0x1180080e04208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2114"             ,	   0x1180080e04210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2115"             ,	   0x1180080e04218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2116"             ,	   0x1180080e04220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2117"             ,	   0x1180080e04228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2118"             ,	   0x1180080e04230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2119"             ,	   0x1180080e04238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2120"             ,	   0x1180080e04240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2121"             ,	   0x1180080e04248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2122"             ,	   0x1180080e04250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2123"             ,	   0x1180080e04258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2124"             ,	   0x1180080e04260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2125"             ,	   0x1180080e04268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2126"             ,	   0x1180080e04270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2127"             ,	   0x1180080e04278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2128"             ,	   0x1180080e04280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2129"             ,	   0x1180080e04288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2130"             ,	   0x1180080e04290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2131"             ,	   0x1180080e04298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2132"             ,	   0x1180080e042a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2133"             ,	   0x1180080e042a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2134"             ,	   0x1180080e042b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2135"             ,	   0x1180080e042b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2136"             ,	   0x1180080e042c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2137"             ,	   0x1180080e042c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2138"             ,	   0x1180080e042d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2139"             ,	   0x1180080e042d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2140"             ,	   0x1180080e042e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2141"             ,	   0x1180080e042e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2142"             ,	   0x1180080e042f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2143"             ,	   0x1180080e042f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2144"             ,	   0x1180080e04300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2145"             ,	   0x1180080e04308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2146"             ,	   0x1180080e04310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2147"             ,	   0x1180080e04318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2148"             ,	   0x1180080e04320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2149"             ,	   0x1180080e04328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2150"             ,	   0x1180080e04330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2151"             ,	   0x1180080e04338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2152"             ,	   0x1180080e04340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2153"             ,	   0x1180080e04348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2154"             ,	   0x1180080e04350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2155"             ,	   0x1180080e04358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2156"             ,	   0x1180080e04360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2157"             ,	   0x1180080e04368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2158"             ,	   0x1180080e04370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2159"             ,	   0x1180080e04378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2160"             ,	   0x1180080e04380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2161"             ,	   0x1180080e04388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2162"             ,	   0x1180080e04390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2163"             ,	   0x1180080e04398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2164"             ,	   0x1180080e043a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2165"             ,	   0x1180080e043a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2166"             ,	   0x1180080e043b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2167"             ,	   0x1180080e043b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2168"             ,	   0x1180080e043c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2169"             ,	   0x1180080e043c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2170"             ,	   0x1180080e043d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2171"             ,	   0x1180080e043d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2172"             ,	   0x1180080e043e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2173"             ,	   0x1180080e043e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2174"             ,	   0x1180080e043f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2175"             ,	   0x1180080e043f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2176"             ,	   0x1180080e04400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2177"             ,	   0x1180080e04408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2178"             ,	   0x1180080e04410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2179"             ,	   0x1180080e04418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2180"             ,	   0x1180080e04420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2181"             ,	   0x1180080e04428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2182"             ,	   0x1180080e04430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2183"             ,	   0x1180080e04438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2184"             ,	   0x1180080e04440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2185"             ,	   0x1180080e04448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2186"             ,	   0x1180080e04450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2187"             ,	   0x1180080e04458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2188"             ,	   0x1180080e04460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2189"             ,	   0x1180080e04468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2190"             ,	   0x1180080e04470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2191"             ,	   0x1180080e04478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2192"             ,	   0x1180080e04480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2193"             ,	   0x1180080e04488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2194"             ,	   0x1180080e04490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2195"             ,	   0x1180080e04498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2196"             ,	   0x1180080e044a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2197"             ,	   0x1180080e044a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2198"             ,	   0x1180080e044b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2199"             ,	   0x1180080e044b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2200"             ,	   0x1180080e044c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2201"             ,	   0x1180080e044c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2202"             ,	   0x1180080e044d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2203"             ,	   0x1180080e044d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2204"             ,	   0x1180080e044e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2205"             ,	   0x1180080e044e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2206"             ,	   0x1180080e044f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2207"             ,	   0x1180080e044f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2208"             ,	   0x1180080e04500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2209"             ,	   0x1180080e04508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2210"             ,	   0x1180080e04510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2211"             ,	   0x1180080e04518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2212"             ,	   0x1180080e04520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2213"             ,	   0x1180080e04528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2214"             ,	   0x1180080e04530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2215"             ,	   0x1180080e04538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2216"             ,	   0x1180080e04540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2217"             ,	   0x1180080e04548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2218"             ,	   0x1180080e04550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2219"             ,	   0x1180080e04558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2220"             ,	   0x1180080e04560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2221"             ,	   0x1180080e04568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2222"             ,	   0x1180080e04570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2223"             ,	   0x1180080e04578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2224"             ,	   0x1180080e04580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2225"             ,	   0x1180080e04588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2226"             ,	   0x1180080e04590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2227"             ,	   0x1180080e04598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2228"             ,	   0x1180080e045a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2229"             ,	   0x1180080e045a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2230"             ,	   0x1180080e045b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2231"             ,	   0x1180080e045b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2232"             ,	   0x1180080e045c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2233"             ,	   0x1180080e045c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2234"             ,	   0x1180080e045d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2235"             ,	   0x1180080e045d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2236"             ,	   0x1180080e045e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2237"             ,	   0x1180080e045e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2238"             ,	   0x1180080e045f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2239"             ,	   0x1180080e045f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2240"             ,	   0x1180080e04600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2241"             ,	   0x1180080e04608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2242"             ,	   0x1180080e04610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2243"             ,	   0x1180080e04618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2244"             ,	   0x1180080e04620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2245"             ,	   0x1180080e04628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2246"             ,	   0x1180080e04630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2247"             ,	   0x1180080e04638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2248"             ,	   0x1180080e04640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2249"             ,	   0x1180080e04648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2250"             ,	   0x1180080e04650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2251"             ,	   0x1180080e04658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2252"             ,	   0x1180080e04660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2253"             ,	   0x1180080e04668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2254"             ,	   0x1180080e04670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2255"             ,	   0x1180080e04678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2256"             ,	   0x1180080e04680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2257"             ,	   0x1180080e04688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2258"             ,	   0x1180080e04690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2259"             ,	   0x1180080e04698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2260"             ,	   0x1180080e046a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2261"             ,	   0x1180080e046a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2262"             ,	   0x1180080e046b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2263"             ,	   0x1180080e046b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2264"             ,	   0x1180080e046c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2265"             ,	   0x1180080e046c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2266"             ,	   0x1180080e046d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2267"             ,	   0x1180080e046d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2268"             ,	   0x1180080e046e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2269"             ,	   0x1180080e046e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2270"             ,	   0x1180080e046f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2271"             ,	   0x1180080e046f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2272"             ,	   0x1180080e04700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2273"             ,	   0x1180080e04708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2274"             ,	   0x1180080e04710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2275"             ,	   0x1180080e04718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2276"             ,	   0x1180080e04720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2277"             ,	   0x1180080e04728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2278"             ,	   0x1180080e04730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2279"             ,	   0x1180080e04738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2280"             ,	   0x1180080e04740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2281"             ,	   0x1180080e04748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2282"             ,	   0x1180080e04750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2283"             ,	   0x1180080e04758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2284"             ,	   0x1180080e04760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2285"             ,	   0x1180080e04768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2286"             ,	   0x1180080e04770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2287"             ,	   0x1180080e04778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2288"             ,	   0x1180080e04780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2289"             ,	   0x1180080e04788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2290"             ,	   0x1180080e04790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2291"             ,	   0x1180080e04798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2292"             ,	   0x1180080e047a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2293"             ,	   0x1180080e047a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2294"             ,	   0x1180080e047b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2295"             ,	   0x1180080e047b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2296"             ,	   0x1180080e047c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2297"             ,	   0x1180080e047c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2298"             ,	   0x1180080e047d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2299"             ,	   0x1180080e047d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2300"             ,	   0x1180080e047e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2301"             ,	   0x1180080e047e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2302"             ,	   0x1180080e047f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2303"             ,	   0x1180080e047f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2304"             ,	   0x1180080e04800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2305"             ,	   0x1180080e04808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2306"             ,	   0x1180080e04810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2307"             ,	   0x1180080e04818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2308"             ,	   0x1180080e04820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2309"             ,	   0x1180080e04828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2310"             ,	   0x1180080e04830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2311"             ,	   0x1180080e04838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2312"             ,	   0x1180080e04840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2313"             ,	   0x1180080e04848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2314"             ,	   0x1180080e04850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2315"             ,	   0x1180080e04858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2316"             ,	   0x1180080e04860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2317"             ,	   0x1180080e04868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2318"             ,	   0x1180080e04870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2319"             ,	   0x1180080e04878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2320"             ,	   0x1180080e04880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2321"             ,	   0x1180080e04888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2322"             ,	   0x1180080e04890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2323"             ,	   0x1180080e04898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2324"             ,	   0x1180080e048a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2325"             ,	   0x1180080e048a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2326"             ,	   0x1180080e048b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2327"             ,	   0x1180080e048b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2328"             ,	   0x1180080e048c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2329"             ,	   0x1180080e048c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2330"             ,	   0x1180080e048d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2331"             ,	   0x1180080e048d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2332"             ,	   0x1180080e048e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2333"             ,	   0x1180080e048e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2334"             ,	   0x1180080e048f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2335"             ,	   0x1180080e048f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2336"             ,	   0x1180080e04900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2337"             ,	   0x1180080e04908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2338"             ,	   0x1180080e04910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2339"             ,	   0x1180080e04918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2340"             ,	   0x1180080e04920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2341"             ,	   0x1180080e04928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2342"             ,	   0x1180080e04930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2343"             ,	   0x1180080e04938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2344"             ,	   0x1180080e04940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2345"             ,	   0x1180080e04948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2346"             ,	   0x1180080e04950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2347"             ,	   0x1180080e04958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2348"             ,	   0x1180080e04960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2349"             ,	   0x1180080e04968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2350"             ,	   0x1180080e04970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2351"             ,	   0x1180080e04978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2352"             ,	   0x1180080e04980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2353"             ,	   0x1180080e04988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2354"             ,	   0x1180080e04990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2355"             ,	   0x1180080e04998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2356"             ,	   0x1180080e049a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2357"             ,	   0x1180080e049a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2358"             ,	   0x1180080e049b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2359"             ,	   0x1180080e049b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2360"             ,	   0x1180080e049c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2361"             ,	   0x1180080e049c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2362"             ,	   0x1180080e049d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2363"             ,	   0x1180080e049d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2364"             ,	   0x1180080e049e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2365"             ,	   0x1180080e049e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2366"             ,	   0x1180080e049f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2367"             ,	   0x1180080e049f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2368"             ,	   0x1180080e04a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2369"             ,	   0x1180080e04a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2370"             ,	   0x1180080e04a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2371"             ,	   0x1180080e04a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2372"             ,	   0x1180080e04a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2373"             ,	   0x1180080e04a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2374"             ,	   0x1180080e04a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2375"             ,	   0x1180080e04a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2376"             ,	   0x1180080e04a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2377"             ,	   0x1180080e04a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2378"             ,	   0x1180080e04a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2379"             ,	   0x1180080e04a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2380"             ,	   0x1180080e04a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2381"             ,	   0x1180080e04a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2382"             ,	   0x1180080e04a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2383"             ,	   0x1180080e04a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2384"             ,	   0x1180080e04a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2385"             ,	   0x1180080e04a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2386"             ,	   0x1180080e04a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2387"             ,	   0x1180080e04a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2388"             ,	   0x1180080e04aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2389"             ,	   0x1180080e04aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2390"             ,	   0x1180080e04ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2391"             ,	   0x1180080e04ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2392"             ,	   0x1180080e04ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2393"             ,	   0x1180080e04ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2394"             ,	   0x1180080e04ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2395"             ,	   0x1180080e04ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2396"             ,	   0x1180080e04ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2397"             ,	   0x1180080e04ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2398"             ,	   0x1180080e04af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2399"             ,	   0x1180080e04af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2400"             ,	   0x1180080e04b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2401"             ,	   0x1180080e04b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2402"             ,	   0x1180080e04b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2403"             ,	   0x1180080e04b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2404"             ,	   0x1180080e04b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2405"             ,	   0x1180080e04b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2406"             ,	   0x1180080e04b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2407"             ,	   0x1180080e04b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2408"             ,	   0x1180080e04b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2409"             ,	   0x1180080e04b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2410"             ,	   0x1180080e04b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2411"             ,	   0x1180080e04b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2412"             ,	   0x1180080e04b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2413"             ,	   0x1180080e04b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2414"             ,	   0x1180080e04b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2415"             ,	   0x1180080e04b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2416"             ,	   0x1180080e04b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2417"             ,	   0x1180080e04b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2418"             ,	   0x1180080e04b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2419"             ,	   0x1180080e04b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2420"             ,	   0x1180080e04ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2421"             ,	   0x1180080e04ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2422"             ,	   0x1180080e04bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2423"             ,	   0x1180080e04bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2424"             ,	   0x1180080e04bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2425"             ,	   0x1180080e04bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2426"             ,	   0x1180080e04bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2427"             ,	   0x1180080e04bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2428"             ,	   0x1180080e04be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2429"             ,	   0x1180080e04be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2430"             ,	   0x1180080e04bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2431"             ,	   0x1180080e04bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2432"             ,	   0x1180080e04c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2433"             ,	   0x1180080e04c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2434"             ,	   0x1180080e04c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2435"             ,	   0x1180080e04c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2436"             ,	   0x1180080e04c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2437"             ,	   0x1180080e04c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2438"             ,	   0x1180080e04c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2439"             ,	   0x1180080e04c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2440"             ,	   0x1180080e04c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2441"             ,	   0x1180080e04c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2442"             ,	   0x1180080e04c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2443"             ,	   0x1180080e04c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2444"             ,	   0x1180080e04c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2445"             ,	   0x1180080e04c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2446"             ,	   0x1180080e04c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2447"             ,	   0x1180080e04c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2448"             ,	   0x1180080e04c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2449"             ,	   0x1180080e04c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2450"             ,	   0x1180080e04c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2451"             ,	   0x1180080e04c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2452"             ,	   0x1180080e04ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2453"             ,	   0x1180080e04ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2454"             ,	   0x1180080e04cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2455"             ,	   0x1180080e04cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2456"             ,	   0x1180080e04cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2457"             ,	   0x1180080e04cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2458"             ,	   0x1180080e04cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2459"             ,	   0x1180080e04cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2460"             ,	   0x1180080e04ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2461"             ,	   0x1180080e04ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2462"             ,	   0x1180080e04cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2463"             ,	   0x1180080e04cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2464"             ,	   0x1180080e04d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2465"             ,	   0x1180080e04d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2466"             ,	   0x1180080e04d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2467"             ,	   0x1180080e04d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2468"             ,	   0x1180080e04d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2469"             ,	   0x1180080e04d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2470"             ,	   0x1180080e04d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2471"             ,	   0x1180080e04d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2472"             ,	   0x1180080e04d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2473"             ,	   0x1180080e04d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2474"             ,	   0x1180080e04d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2475"             ,	   0x1180080e04d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2476"             ,	   0x1180080e04d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2477"             ,	   0x1180080e04d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2478"             ,	   0x1180080e04d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2479"             ,	   0x1180080e04d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2480"             ,	   0x1180080e04d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2481"             ,	   0x1180080e04d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2482"             ,	   0x1180080e04d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2483"             ,	   0x1180080e04d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2484"             ,	   0x1180080e04da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2485"             ,	   0x1180080e04da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2486"             ,	   0x1180080e04db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2487"             ,	   0x1180080e04db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2488"             ,	   0x1180080e04dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2489"             ,	   0x1180080e04dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2490"             ,	   0x1180080e04dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2491"             ,	   0x1180080e04dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2492"             ,	   0x1180080e04de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2493"             ,	   0x1180080e04de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2494"             ,	   0x1180080e04df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2495"             ,	   0x1180080e04df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2496"             ,	   0x1180080e04e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2497"             ,	   0x1180080e04e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2498"             ,	   0x1180080e04e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2499"             ,	   0x1180080e04e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2500"             ,	   0x1180080e04e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2501"             ,	   0x1180080e04e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2502"             ,	   0x1180080e04e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2503"             ,	   0x1180080e04e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2504"             ,	   0x1180080e04e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2505"             ,	   0x1180080e04e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2506"             ,	   0x1180080e04e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2507"             ,	   0x1180080e04e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2508"             ,	   0x1180080e04e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2509"             ,	   0x1180080e04e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2510"             ,	   0x1180080e04e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2511"             ,	   0x1180080e04e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2512"             ,	   0x1180080e04e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2513"             ,	   0x1180080e04e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2514"             ,	   0x1180080e04e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2515"             ,	   0x1180080e04e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2516"             ,	   0x1180080e04ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2517"             ,	   0x1180080e04ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2518"             ,	   0x1180080e04eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2519"             ,	   0x1180080e04eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2520"             ,	   0x1180080e04ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2521"             ,	   0x1180080e04ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2522"             ,	   0x1180080e04ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2523"             ,	   0x1180080e04ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2524"             ,	   0x1180080e04ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2525"             ,	   0x1180080e04ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2526"             ,	   0x1180080e04ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2527"             ,	   0x1180080e04ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2528"             ,	   0x1180080e04f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2529"             ,	   0x1180080e04f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2530"             ,	   0x1180080e04f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2531"             ,	   0x1180080e04f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2532"             ,	   0x1180080e04f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2533"             ,	   0x1180080e04f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2534"             ,	   0x1180080e04f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2535"             ,	   0x1180080e04f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2536"             ,	   0x1180080e04f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2537"             ,	   0x1180080e04f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2538"             ,	   0x1180080e04f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2539"             ,	   0x1180080e04f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2540"             ,	   0x1180080e04f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2541"             ,	   0x1180080e04f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2542"             ,	   0x1180080e04f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2543"             ,	   0x1180080e04f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2544"             ,	   0x1180080e04f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2545"             ,	   0x1180080e04f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2546"             ,	   0x1180080e04f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2547"             ,	   0x1180080e04f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2548"             ,	   0x1180080e04fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2549"             ,	   0x1180080e04fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2550"             ,	   0x1180080e04fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2551"             ,	   0x1180080e04fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2552"             ,	   0x1180080e04fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2553"             ,	   0x1180080e04fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2554"             ,	   0x1180080e04fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2555"             ,	   0x1180080e04fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2556"             ,	   0x1180080e04fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2557"             ,	   0x1180080e04fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2558"             ,	   0x1180080e04ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2559"             ,	   0x1180080e04ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2560"             ,	   0x1180080e05000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2561"             ,	   0x1180080e05008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2562"             ,	   0x1180080e05010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2563"             ,	   0x1180080e05018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2564"             ,	   0x1180080e05020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2565"             ,	   0x1180080e05028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2566"             ,	   0x1180080e05030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2567"             ,	   0x1180080e05038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2568"             ,	   0x1180080e05040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2569"             ,	   0x1180080e05048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2570"             ,	   0x1180080e05050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2571"             ,	   0x1180080e05058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2572"             ,	   0x1180080e05060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2573"             ,	   0x1180080e05068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2574"             ,	   0x1180080e05070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2575"             ,	   0x1180080e05078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2576"             ,	   0x1180080e05080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2577"             ,	   0x1180080e05088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2578"             ,	   0x1180080e05090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2579"             ,	   0x1180080e05098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2580"             ,	   0x1180080e050a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2581"             ,	   0x1180080e050a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2582"             ,	   0x1180080e050b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2583"             ,	   0x1180080e050b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2584"             ,	   0x1180080e050c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2585"             ,	   0x1180080e050c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2586"             ,	   0x1180080e050d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2587"             ,	   0x1180080e050d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2588"             ,	   0x1180080e050e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2589"             ,	   0x1180080e050e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2590"             ,	   0x1180080e050f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2591"             ,	   0x1180080e050f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2592"             ,	   0x1180080e05100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2593"             ,	   0x1180080e05108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2594"             ,	   0x1180080e05110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2595"             ,	   0x1180080e05118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2596"             ,	   0x1180080e05120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2597"             ,	   0x1180080e05128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2598"             ,	   0x1180080e05130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2599"             ,	   0x1180080e05138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2600"             ,	   0x1180080e05140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2601"             ,	   0x1180080e05148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2602"             ,	   0x1180080e05150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2603"             ,	   0x1180080e05158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2604"             ,	   0x1180080e05160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2605"             ,	   0x1180080e05168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2606"             ,	   0x1180080e05170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2607"             ,	   0x1180080e05178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2608"             ,	   0x1180080e05180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2609"             ,	   0x1180080e05188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2610"             ,	   0x1180080e05190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2611"             ,	   0x1180080e05198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2612"             ,	   0x1180080e051a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2613"             ,	   0x1180080e051a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2614"             ,	   0x1180080e051b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2615"             ,	   0x1180080e051b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2616"             ,	   0x1180080e051c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2617"             ,	   0x1180080e051c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2618"             ,	   0x1180080e051d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2619"             ,	   0x1180080e051d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2620"             ,	   0x1180080e051e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2621"             ,	   0x1180080e051e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2622"             ,	   0x1180080e051f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2623"             ,	   0x1180080e051f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2624"             ,	   0x1180080e05200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2625"             ,	   0x1180080e05208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2626"             ,	   0x1180080e05210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2627"             ,	   0x1180080e05218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2628"             ,	   0x1180080e05220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2629"             ,	   0x1180080e05228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2630"             ,	   0x1180080e05230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2631"             ,	   0x1180080e05238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2632"             ,	   0x1180080e05240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2633"             ,	   0x1180080e05248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2634"             ,	   0x1180080e05250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2635"             ,	   0x1180080e05258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2636"             ,	   0x1180080e05260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2637"             ,	   0x1180080e05268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2638"             ,	   0x1180080e05270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2639"             ,	   0x1180080e05278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2640"             ,	   0x1180080e05280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2641"             ,	   0x1180080e05288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2642"             ,	   0x1180080e05290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2643"             ,	   0x1180080e05298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2644"             ,	   0x1180080e052a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2645"             ,	   0x1180080e052a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2646"             ,	   0x1180080e052b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2647"             ,	   0x1180080e052b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2648"             ,	   0x1180080e052c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2649"             ,	   0x1180080e052c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2650"             ,	   0x1180080e052d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2651"             ,	   0x1180080e052d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2652"             ,	   0x1180080e052e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2653"             ,	   0x1180080e052e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2654"             ,	   0x1180080e052f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2655"             ,	   0x1180080e052f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2656"             ,	   0x1180080e05300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2657"             ,	   0x1180080e05308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2658"             ,	   0x1180080e05310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2659"             ,	   0x1180080e05318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2660"             ,	   0x1180080e05320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2661"             ,	   0x1180080e05328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2662"             ,	   0x1180080e05330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2663"             ,	   0x1180080e05338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2664"             ,	   0x1180080e05340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2665"             ,	   0x1180080e05348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2666"             ,	   0x1180080e05350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2667"             ,	   0x1180080e05358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2668"             ,	   0x1180080e05360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2669"             ,	   0x1180080e05368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2670"             ,	   0x1180080e05370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2671"             ,	   0x1180080e05378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2672"             ,	   0x1180080e05380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2673"             ,	   0x1180080e05388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2674"             ,	   0x1180080e05390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2675"             ,	   0x1180080e05398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2676"             ,	   0x1180080e053a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2677"             ,	   0x1180080e053a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2678"             ,	   0x1180080e053b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2679"             ,	   0x1180080e053b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2680"             ,	   0x1180080e053c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2681"             ,	   0x1180080e053c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2682"             ,	   0x1180080e053d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2683"             ,	   0x1180080e053d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2684"             ,	   0x1180080e053e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2685"             ,	   0x1180080e053e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2686"             ,	   0x1180080e053f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2687"             ,	   0x1180080e053f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2688"             ,	   0x1180080e05400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2689"             ,	   0x1180080e05408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2690"             ,	   0x1180080e05410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2691"             ,	   0x1180080e05418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2692"             ,	   0x1180080e05420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2693"             ,	   0x1180080e05428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2694"             ,	   0x1180080e05430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2695"             ,	   0x1180080e05438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2696"             ,	   0x1180080e05440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2697"             ,	   0x1180080e05448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2698"             ,	   0x1180080e05450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2699"             ,	   0x1180080e05458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2700"             ,	   0x1180080e05460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2701"             ,	   0x1180080e05468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2702"             ,	   0x1180080e05470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2703"             ,	   0x1180080e05478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2704"             ,	   0x1180080e05480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2705"             ,	   0x1180080e05488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2706"             ,	   0x1180080e05490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2707"             ,	   0x1180080e05498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2708"             ,	   0x1180080e054a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2709"             ,	   0x1180080e054a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2710"             ,	   0x1180080e054b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2711"             ,	   0x1180080e054b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2712"             ,	   0x1180080e054c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2713"             ,	   0x1180080e054c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2714"             ,	   0x1180080e054d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2715"             ,	   0x1180080e054d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2716"             ,	   0x1180080e054e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2717"             ,	   0x1180080e054e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2718"             ,	   0x1180080e054f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2719"             ,	   0x1180080e054f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2720"             ,	   0x1180080e05500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2721"             ,	   0x1180080e05508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2722"             ,	   0x1180080e05510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2723"             ,	   0x1180080e05518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2724"             ,	   0x1180080e05520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2725"             ,	   0x1180080e05528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2726"             ,	   0x1180080e05530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2727"             ,	   0x1180080e05538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2728"             ,	   0x1180080e05540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2729"             ,	   0x1180080e05548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2730"             ,	   0x1180080e05550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2731"             ,	   0x1180080e05558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2732"             ,	   0x1180080e05560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2733"             ,	   0x1180080e05568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2734"             ,	   0x1180080e05570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2735"             ,	   0x1180080e05578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2736"             ,	   0x1180080e05580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2737"             ,	   0x1180080e05588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2738"             ,	   0x1180080e05590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2739"             ,	   0x1180080e05598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2740"             ,	   0x1180080e055a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2741"             ,	   0x1180080e055a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2742"             ,	   0x1180080e055b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2743"             ,	   0x1180080e055b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2744"             ,	   0x1180080e055c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2745"             ,	   0x1180080e055c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2746"             ,	   0x1180080e055d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2747"             ,	   0x1180080e055d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2748"             ,	   0x1180080e055e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2749"             ,	   0x1180080e055e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2750"             ,	   0x1180080e055f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2751"             ,	   0x1180080e055f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2752"             ,	   0x1180080e05600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2753"             ,	   0x1180080e05608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2754"             ,	   0x1180080e05610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2755"             ,	   0x1180080e05618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2756"             ,	   0x1180080e05620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2757"             ,	   0x1180080e05628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2758"             ,	   0x1180080e05630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2759"             ,	   0x1180080e05638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2760"             ,	   0x1180080e05640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2761"             ,	   0x1180080e05648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2762"             ,	   0x1180080e05650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2763"             ,	   0x1180080e05658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2764"             ,	   0x1180080e05660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2765"             ,	   0x1180080e05668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2766"             ,	   0x1180080e05670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2767"             ,	   0x1180080e05678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2768"             ,	   0x1180080e05680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2769"             ,	   0x1180080e05688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2770"             ,	   0x1180080e05690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2771"             ,	   0x1180080e05698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2772"             ,	   0x1180080e056a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2773"             ,	   0x1180080e056a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2774"             ,	   0x1180080e056b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2775"             ,	   0x1180080e056b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2776"             ,	   0x1180080e056c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2777"             ,	   0x1180080e056c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2778"             ,	   0x1180080e056d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2779"             ,	   0x1180080e056d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2780"             ,	   0x1180080e056e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2781"             ,	   0x1180080e056e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2782"             ,	   0x1180080e056f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2783"             ,	   0x1180080e056f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2784"             ,	   0x1180080e05700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2785"             ,	   0x1180080e05708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2786"             ,	   0x1180080e05710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2787"             ,	   0x1180080e05718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2788"             ,	   0x1180080e05720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2789"             ,	   0x1180080e05728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2790"             ,	   0x1180080e05730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2791"             ,	   0x1180080e05738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2792"             ,	   0x1180080e05740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2793"             ,	   0x1180080e05748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2794"             ,	   0x1180080e05750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2795"             ,	   0x1180080e05758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2796"             ,	   0x1180080e05760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2797"             ,	   0x1180080e05768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2798"             ,	   0x1180080e05770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2799"             ,	   0x1180080e05778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2800"             ,	   0x1180080e05780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2801"             ,	   0x1180080e05788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2802"             ,	   0x1180080e05790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2803"             ,	   0x1180080e05798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2804"             ,	   0x1180080e057a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2805"             ,	   0x1180080e057a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2806"             ,	   0x1180080e057b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2807"             ,	   0x1180080e057b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2808"             ,	   0x1180080e057c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2809"             ,	   0x1180080e057c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2810"             ,	   0x1180080e057d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2811"             ,	   0x1180080e057d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2812"             ,	   0x1180080e057e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2813"             ,	   0x1180080e057e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2814"             ,	   0x1180080e057f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2815"             ,	   0x1180080e057f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2816"             ,	   0x1180080e05800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2817"             ,	   0x1180080e05808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2818"             ,	   0x1180080e05810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2819"             ,	   0x1180080e05818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2820"             ,	   0x1180080e05820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2821"             ,	   0x1180080e05828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2822"             ,	   0x1180080e05830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2823"             ,	   0x1180080e05838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2824"             ,	   0x1180080e05840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2825"             ,	   0x1180080e05848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2826"             ,	   0x1180080e05850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2827"             ,	   0x1180080e05858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2828"             ,	   0x1180080e05860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2829"             ,	   0x1180080e05868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2830"             ,	   0x1180080e05870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2831"             ,	   0x1180080e05878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2832"             ,	   0x1180080e05880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2833"             ,	   0x1180080e05888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2834"             ,	   0x1180080e05890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2835"             ,	   0x1180080e05898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2836"             ,	   0x1180080e058a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2837"             ,	   0x1180080e058a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2838"             ,	   0x1180080e058b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2839"             ,	   0x1180080e058b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2840"             ,	   0x1180080e058c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2841"             ,	   0x1180080e058c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2842"             ,	   0x1180080e058d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2843"             ,	   0x1180080e058d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2844"             ,	   0x1180080e058e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2845"             ,	   0x1180080e058e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2846"             ,	   0x1180080e058f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2847"             ,	   0x1180080e058f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2848"             ,	   0x1180080e05900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2849"             ,	   0x1180080e05908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2850"             ,	   0x1180080e05910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2851"             ,	   0x1180080e05918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2852"             ,	   0x1180080e05920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2853"             ,	   0x1180080e05928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2854"             ,	   0x1180080e05930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2855"             ,	   0x1180080e05938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2856"             ,	   0x1180080e05940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2857"             ,	   0x1180080e05948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2858"             ,	   0x1180080e05950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2859"             ,	   0x1180080e05958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2860"             ,	   0x1180080e05960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2861"             ,	   0x1180080e05968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2862"             ,	   0x1180080e05970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2863"             ,	   0x1180080e05978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2864"             ,	   0x1180080e05980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2865"             ,	   0x1180080e05988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2866"             ,	   0x1180080e05990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2867"             ,	   0x1180080e05998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2868"             ,	   0x1180080e059a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2869"             ,	   0x1180080e059a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2870"             ,	   0x1180080e059b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2871"             ,	   0x1180080e059b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2872"             ,	   0x1180080e059c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2873"             ,	   0x1180080e059c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2874"             ,	   0x1180080e059d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2875"             ,	   0x1180080e059d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2876"             ,	   0x1180080e059e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2877"             ,	   0x1180080e059e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2878"             ,	   0x1180080e059f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2879"             ,	   0x1180080e059f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2880"             ,	   0x1180080e05a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2881"             ,	   0x1180080e05a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2882"             ,	   0x1180080e05a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2883"             ,	   0x1180080e05a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2884"             ,	   0x1180080e05a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2885"             ,	   0x1180080e05a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2886"             ,	   0x1180080e05a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2887"             ,	   0x1180080e05a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2888"             ,	   0x1180080e05a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2889"             ,	   0x1180080e05a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2890"             ,	   0x1180080e05a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2891"             ,	   0x1180080e05a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2892"             ,	   0x1180080e05a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2893"             ,	   0x1180080e05a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2894"             ,	   0x1180080e05a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2895"             ,	   0x1180080e05a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2896"             ,	   0x1180080e05a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2897"             ,	   0x1180080e05a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2898"             ,	   0x1180080e05a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2899"             ,	   0x1180080e05a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2900"             ,	   0x1180080e05aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2901"             ,	   0x1180080e05aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2902"             ,	   0x1180080e05ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2903"             ,	   0x1180080e05ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2904"             ,	   0x1180080e05ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2905"             ,	   0x1180080e05ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2906"             ,	   0x1180080e05ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2907"             ,	   0x1180080e05ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2908"             ,	   0x1180080e05ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2909"             ,	   0x1180080e05ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2910"             ,	   0x1180080e05af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2911"             ,	   0x1180080e05af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2912"             ,	   0x1180080e05b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2913"             ,	   0x1180080e05b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2914"             ,	   0x1180080e05b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2915"             ,	   0x1180080e05b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2916"             ,	   0x1180080e05b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2917"             ,	   0x1180080e05b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2918"             ,	   0x1180080e05b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2919"             ,	   0x1180080e05b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2920"             ,	   0x1180080e05b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2921"             ,	   0x1180080e05b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2922"             ,	   0x1180080e05b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2923"             ,	   0x1180080e05b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2924"             ,	   0x1180080e05b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2925"             ,	   0x1180080e05b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2926"             ,	   0x1180080e05b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2927"             ,	   0x1180080e05b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2928"             ,	   0x1180080e05b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2929"             ,	   0x1180080e05b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2930"             ,	   0x1180080e05b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2931"             ,	   0x1180080e05b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2932"             ,	   0x1180080e05ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2933"             ,	   0x1180080e05ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2934"             ,	   0x1180080e05bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2935"             ,	   0x1180080e05bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2936"             ,	   0x1180080e05bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2937"             ,	   0x1180080e05bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2938"             ,	   0x1180080e05bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2939"             ,	   0x1180080e05bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2940"             ,	   0x1180080e05be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2941"             ,	   0x1180080e05be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2942"             ,	   0x1180080e05bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2943"             ,	   0x1180080e05bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2944"             ,	   0x1180080e05c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2945"             ,	   0x1180080e05c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2946"             ,	   0x1180080e05c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2947"             ,	   0x1180080e05c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2948"             ,	   0x1180080e05c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2949"             ,	   0x1180080e05c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2950"             ,	   0x1180080e05c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2951"             ,	   0x1180080e05c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2952"             ,	   0x1180080e05c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2953"             ,	   0x1180080e05c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2954"             ,	   0x1180080e05c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2955"             ,	   0x1180080e05c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2956"             ,	   0x1180080e05c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2957"             ,	   0x1180080e05c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2958"             ,	   0x1180080e05c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2959"             ,	   0x1180080e05c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2960"             ,	   0x1180080e05c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2961"             ,	   0x1180080e05c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2962"             ,	   0x1180080e05c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2963"             ,	   0x1180080e05c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2964"             ,	   0x1180080e05ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2965"             ,	   0x1180080e05ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2966"             ,	   0x1180080e05cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2967"             ,	   0x1180080e05cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2968"             ,	   0x1180080e05cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2969"             ,	   0x1180080e05cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2970"             ,	   0x1180080e05cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2971"             ,	   0x1180080e05cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2972"             ,	   0x1180080e05ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2973"             ,	   0x1180080e05ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2974"             ,	   0x1180080e05cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2975"             ,	   0x1180080e05cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2976"             ,	   0x1180080e05d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2977"             ,	   0x1180080e05d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2978"             ,	   0x1180080e05d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2979"             ,	   0x1180080e05d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2980"             ,	   0x1180080e05d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2981"             ,	   0x1180080e05d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2982"             ,	   0x1180080e05d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2983"             ,	   0x1180080e05d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2984"             ,	   0x1180080e05d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2985"             ,	   0x1180080e05d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2986"             ,	   0x1180080e05d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2987"             ,	   0x1180080e05d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2988"             ,	   0x1180080e05d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2989"             ,	   0x1180080e05d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2990"             ,	   0x1180080e05d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2991"             ,	   0x1180080e05d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2992"             ,	   0x1180080e05d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2993"             ,	   0x1180080e05d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2994"             ,	   0x1180080e05d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2995"             ,	   0x1180080e05d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2996"             ,	   0x1180080e05da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2997"             ,	   0x1180080e05da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2998"             ,	   0x1180080e05db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP2999"             ,	   0x1180080e05db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3000"             ,	   0x1180080e05dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3001"             ,	   0x1180080e05dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3002"             ,	   0x1180080e05dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3003"             ,	   0x1180080e05dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3004"             ,	   0x1180080e05de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3005"             ,	   0x1180080e05de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3006"             ,	   0x1180080e05df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3007"             ,	   0x1180080e05df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3008"             ,	   0x1180080e05e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3009"             ,	   0x1180080e05e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3010"             ,	   0x1180080e05e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3011"             ,	   0x1180080e05e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3012"             ,	   0x1180080e05e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3013"             ,	   0x1180080e05e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3014"             ,	   0x1180080e05e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3015"             ,	   0x1180080e05e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3016"             ,	   0x1180080e05e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3017"             ,	   0x1180080e05e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3018"             ,	   0x1180080e05e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3019"             ,	   0x1180080e05e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3020"             ,	   0x1180080e05e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3021"             ,	   0x1180080e05e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3022"             ,	   0x1180080e05e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3023"             ,	   0x1180080e05e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3024"             ,	   0x1180080e05e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3025"             ,	   0x1180080e05e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3026"             ,	   0x1180080e05e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3027"             ,	   0x1180080e05e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3028"             ,	   0x1180080e05ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3029"             ,	   0x1180080e05ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3030"             ,	   0x1180080e05eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3031"             ,	   0x1180080e05eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3032"             ,	   0x1180080e05ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3033"             ,	   0x1180080e05ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3034"             ,	   0x1180080e05ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3035"             ,	   0x1180080e05ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3036"             ,	   0x1180080e05ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3037"             ,	   0x1180080e05ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3038"             ,	   0x1180080e05ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3039"             ,	   0x1180080e05ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3040"             ,	   0x1180080e05f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3041"             ,	   0x1180080e05f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3042"             ,	   0x1180080e05f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3043"             ,	   0x1180080e05f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3044"             ,	   0x1180080e05f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3045"             ,	   0x1180080e05f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3046"             ,	   0x1180080e05f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3047"             ,	   0x1180080e05f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3048"             ,	   0x1180080e05f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3049"             ,	   0x1180080e05f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3050"             ,	   0x1180080e05f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3051"             ,	   0x1180080e05f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3052"             ,	   0x1180080e05f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3053"             ,	   0x1180080e05f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3054"             ,	   0x1180080e05f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3055"             ,	   0x1180080e05f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3056"             ,	   0x1180080e05f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3057"             ,	   0x1180080e05f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3058"             ,	   0x1180080e05f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3059"             ,	   0x1180080e05f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3060"             ,	   0x1180080e05fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3061"             ,	   0x1180080e05fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3062"             ,	   0x1180080e05fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3063"             ,	   0x1180080e05fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3064"             ,	   0x1180080e05fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3065"             ,	   0x1180080e05fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3066"             ,	   0x1180080e05fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3067"             ,	   0x1180080e05fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3068"             ,	   0x1180080e05fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3069"             ,	   0x1180080e05fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3070"             ,	   0x1180080e05ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3071"             ,	   0x1180080e05ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3072"             ,	   0x1180080e06000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3073"             ,	   0x1180080e06008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3074"             ,	   0x1180080e06010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3075"             ,	   0x1180080e06018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3076"             ,	   0x1180080e06020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3077"             ,	   0x1180080e06028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3078"             ,	   0x1180080e06030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3079"             ,	   0x1180080e06038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3080"             ,	   0x1180080e06040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3081"             ,	   0x1180080e06048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3082"             ,	   0x1180080e06050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3083"             ,	   0x1180080e06058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3084"             ,	   0x1180080e06060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3085"             ,	   0x1180080e06068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3086"             ,	   0x1180080e06070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3087"             ,	   0x1180080e06078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3088"             ,	   0x1180080e06080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3089"             ,	   0x1180080e06088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3090"             ,	   0x1180080e06090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3091"             ,	   0x1180080e06098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3092"             ,	   0x1180080e060a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3093"             ,	   0x1180080e060a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3094"             ,	   0x1180080e060b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3095"             ,	   0x1180080e060b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3096"             ,	   0x1180080e060c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3097"             ,	   0x1180080e060c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3098"             ,	   0x1180080e060d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3099"             ,	   0x1180080e060d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3100"             ,	   0x1180080e060e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3101"             ,	   0x1180080e060e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3102"             ,	   0x1180080e060f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3103"             ,	   0x1180080e060f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3104"             ,	   0x1180080e06100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3105"             ,	   0x1180080e06108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3106"             ,	   0x1180080e06110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3107"             ,	   0x1180080e06118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3108"             ,	   0x1180080e06120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3109"             ,	   0x1180080e06128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3110"             ,	   0x1180080e06130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3111"             ,	   0x1180080e06138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3112"             ,	   0x1180080e06140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3113"             ,	   0x1180080e06148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3114"             ,	   0x1180080e06150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3115"             ,	   0x1180080e06158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3116"             ,	   0x1180080e06160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3117"             ,	   0x1180080e06168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3118"             ,	   0x1180080e06170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3119"             ,	   0x1180080e06178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3120"             ,	   0x1180080e06180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3121"             ,	   0x1180080e06188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3122"             ,	   0x1180080e06190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3123"             ,	   0x1180080e06198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3124"             ,	   0x1180080e061a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3125"             ,	   0x1180080e061a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3126"             ,	   0x1180080e061b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3127"             ,	   0x1180080e061b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3128"             ,	   0x1180080e061c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3129"             ,	   0x1180080e061c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3130"             ,	   0x1180080e061d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3131"             ,	   0x1180080e061d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3132"             ,	   0x1180080e061e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3133"             ,	   0x1180080e061e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3134"             ,	   0x1180080e061f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3135"             ,	   0x1180080e061f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3136"             ,	   0x1180080e06200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3137"             ,	   0x1180080e06208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3138"             ,	   0x1180080e06210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3139"             ,	   0x1180080e06218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3140"             ,	   0x1180080e06220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3141"             ,	   0x1180080e06228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3142"             ,	   0x1180080e06230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3143"             ,	   0x1180080e06238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3144"             ,	   0x1180080e06240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3145"             ,	   0x1180080e06248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3146"             ,	   0x1180080e06250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3147"             ,	   0x1180080e06258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3148"             ,	   0x1180080e06260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3149"             ,	   0x1180080e06268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3150"             ,	   0x1180080e06270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3151"             ,	   0x1180080e06278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3152"             ,	   0x1180080e06280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3153"             ,	   0x1180080e06288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3154"             ,	   0x1180080e06290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3155"             ,	   0x1180080e06298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3156"             ,	   0x1180080e062a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3157"             ,	   0x1180080e062a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3158"             ,	   0x1180080e062b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3159"             ,	   0x1180080e062b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3160"             ,	   0x1180080e062c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3161"             ,	   0x1180080e062c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3162"             ,	   0x1180080e062d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3163"             ,	   0x1180080e062d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3164"             ,	   0x1180080e062e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3165"             ,	   0x1180080e062e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3166"             ,	   0x1180080e062f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3167"             ,	   0x1180080e062f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3168"             ,	   0x1180080e06300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3169"             ,	   0x1180080e06308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3170"             ,	   0x1180080e06310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3171"             ,	   0x1180080e06318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3172"             ,	   0x1180080e06320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3173"             ,	   0x1180080e06328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3174"             ,	   0x1180080e06330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3175"             ,	   0x1180080e06338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3176"             ,	   0x1180080e06340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3177"             ,	   0x1180080e06348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3178"             ,	   0x1180080e06350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3179"             ,	   0x1180080e06358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3180"             ,	   0x1180080e06360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3181"             ,	   0x1180080e06368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3182"             ,	   0x1180080e06370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3183"             ,	   0x1180080e06378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3184"             ,	   0x1180080e06380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3185"             ,	   0x1180080e06388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3186"             ,	   0x1180080e06390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3187"             ,	   0x1180080e06398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3188"             ,	   0x1180080e063a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3189"             ,	   0x1180080e063a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3190"             ,	   0x1180080e063b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3191"             ,	   0x1180080e063b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3192"             ,	   0x1180080e063c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3193"             ,	   0x1180080e063c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3194"             ,	   0x1180080e063d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3195"             ,	   0x1180080e063d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3196"             ,	   0x1180080e063e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3197"             ,	   0x1180080e063e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3198"             ,	   0x1180080e063f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3199"             ,	   0x1180080e063f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3200"             ,	   0x1180080e06400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3201"             ,	   0x1180080e06408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3202"             ,	   0x1180080e06410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3203"             ,	   0x1180080e06418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3204"             ,	   0x1180080e06420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3205"             ,	   0x1180080e06428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3206"             ,	   0x1180080e06430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3207"             ,	   0x1180080e06438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3208"             ,	   0x1180080e06440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3209"             ,	   0x1180080e06448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3210"             ,	   0x1180080e06450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3211"             ,	   0x1180080e06458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3212"             ,	   0x1180080e06460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3213"             ,	   0x1180080e06468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3214"             ,	   0x1180080e06470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3215"             ,	   0x1180080e06478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3216"             ,	   0x1180080e06480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3217"             ,	   0x1180080e06488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3218"             ,	   0x1180080e06490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3219"             ,	   0x1180080e06498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3220"             ,	   0x1180080e064a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3221"             ,	   0x1180080e064a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3222"             ,	   0x1180080e064b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3223"             ,	   0x1180080e064b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3224"             ,	   0x1180080e064c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3225"             ,	   0x1180080e064c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3226"             ,	   0x1180080e064d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3227"             ,	   0x1180080e064d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3228"             ,	   0x1180080e064e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3229"             ,	   0x1180080e064e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3230"             ,	   0x1180080e064f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3231"             ,	   0x1180080e064f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3232"             ,	   0x1180080e06500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3233"             ,	   0x1180080e06508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3234"             ,	   0x1180080e06510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3235"             ,	   0x1180080e06518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3236"             ,	   0x1180080e06520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3237"             ,	   0x1180080e06528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3238"             ,	   0x1180080e06530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3239"             ,	   0x1180080e06538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3240"             ,	   0x1180080e06540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3241"             ,	   0x1180080e06548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3242"             ,	   0x1180080e06550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3243"             ,	   0x1180080e06558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3244"             ,	   0x1180080e06560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3245"             ,	   0x1180080e06568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3246"             ,	   0x1180080e06570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3247"             ,	   0x1180080e06578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3248"             ,	   0x1180080e06580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3249"             ,	   0x1180080e06588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3250"             ,	   0x1180080e06590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3251"             ,	   0x1180080e06598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3252"             ,	   0x1180080e065a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3253"             ,	   0x1180080e065a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3254"             ,	   0x1180080e065b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3255"             ,	   0x1180080e065b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3256"             ,	   0x1180080e065c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3257"             ,	   0x1180080e065c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3258"             ,	   0x1180080e065d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3259"             ,	   0x1180080e065d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3260"             ,	   0x1180080e065e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3261"             ,	   0x1180080e065e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3262"             ,	   0x1180080e065f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3263"             ,	   0x1180080e065f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3264"             ,	   0x1180080e06600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3265"             ,	   0x1180080e06608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3266"             ,	   0x1180080e06610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3267"             ,	   0x1180080e06618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3268"             ,	   0x1180080e06620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3269"             ,	   0x1180080e06628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3270"             ,	   0x1180080e06630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3271"             ,	   0x1180080e06638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3272"             ,	   0x1180080e06640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3273"             ,	   0x1180080e06648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3274"             ,	   0x1180080e06650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3275"             ,	   0x1180080e06658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3276"             ,	   0x1180080e06660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3277"             ,	   0x1180080e06668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3278"             ,	   0x1180080e06670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3279"             ,	   0x1180080e06678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3280"             ,	   0x1180080e06680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3281"             ,	   0x1180080e06688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3282"             ,	   0x1180080e06690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3283"             ,	   0x1180080e06698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3284"             ,	   0x1180080e066a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3285"             ,	   0x1180080e066a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3286"             ,	   0x1180080e066b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3287"             ,	   0x1180080e066b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3288"             ,	   0x1180080e066c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3289"             ,	   0x1180080e066c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3290"             ,	   0x1180080e066d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3291"             ,	   0x1180080e066d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3292"             ,	   0x1180080e066e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3293"             ,	   0x1180080e066e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3294"             ,	   0x1180080e066f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3295"             ,	   0x1180080e066f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3296"             ,	   0x1180080e06700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3297"             ,	   0x1180080e06708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3298"             ,	   0x1180080e06710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3299"             ,	   0x1180080e06718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3300"             ,	   0x1180080e06720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3301"             ,	   0x1180080e06728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3302"             ,	   0x1180080e06730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3303"             ,	   0x1180080e06738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3304"             ,	   0x1180080e06740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3305"             ,	   0x1180080e06748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3306"             ,	   0x1180080e06750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3307"             ,	   0x1180080e06758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3308"             ,	   0x1180080e06760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3309"             ,	   0x1180080e06768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3310"             ,	   0x1180080e06770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3311"             ,	   0x1180080e06778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3312"             ,	   0x1180080e06780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3313"             ,	   0x1180080e06788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3314"             ,	   0x1180080e06790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3315"             ,	   0x1180080e06798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3316"             ,	   0x1180080e067a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3317"             ,	   0x1180080e067a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3318"             ,	   0x1180080e067b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3319"             ,	   0x1180080e067b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3320"             ,	   0x1180080e067c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3321"             ,	   0x1180080e067c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3322"             ,	   0x1180080e067d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3323"             ,	   0x1180080e067d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3324"             ,	   0x1180080e067e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3325"             ,	   0x1180080e067e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3326"             ,	   0x1180080e067f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3327"             ,	   0x1180080e067f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3328"             ,	   0x1180080e06800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3329"             ,	   0x1180080e06808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3330"             ,	   0x1180080e06810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3331"             ,	   0x1180080e06818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3332"             ,	   0x1180080e06820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3333"             ,	   0x1180080e06828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3334"             ,	   0x1180080e06830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3335"             ,	   0x1180080e06838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3336"             ,	   0x1180080e06840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3337"             ,	   0x1180080e06848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3338"             ,	   0x1180080e06850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3339"             ,	   0x1180080e06858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3340"             ,	   0x1180080e06860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3341"             ,	   0x1180080e06868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3342"             ,	   0x1180080e06870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3343"             ,	   0x1180080e06878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3344"             ,	   0x1180080e06880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3345"             ,	   0x1180080e06888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3346"             ,	   0x1180080e06890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3347"             ,	   0x1180080e06898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3348"             ,	   0x1180080e068a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3349"             ,	   0x1180080e068a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3350"             ,	   0x1180080e068b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3351"             ,	   0x1180080e068b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3352"             ,	   0x1180080e068c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3353"             ,	   0x1180080e068c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3354"             ,	   0x1180080e068d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3355"             ,	   0x1180080e068d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3356"             ,	   0x1180080e068e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3357"             ,	   0x1180080e068e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3358"             ,	   0x1180080e068f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3359"             ,	   0x1180080e068f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3360"             ,	   0x1180080e06900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3361"             ,	   0x1180080e06908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3362"             ,	   0x1180080e06910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3363"             ,	   0x1180080e06918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3364"             ,	   0x1180080e06920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3365"             ,	   0x1180080e06928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3366"             ,	   0x1180080e06930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3367"             ,	   0x1180080e06938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3368"             ,	   0x1180080e06940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3369"             ,	   0x1180080e06948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3370"             ,	   0x1180080e06950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3371"             ,	   0x1180080e06958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3372"             ,	   0x1180080e06960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3373"             ,	   0x1180080e06968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3374"             ,	   0x1180080e06970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3375"             ,	   0x1180080e06978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3376"             ,	   0x1180080e06980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3377"             ,	   0x1180080e06988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3378"             ,	   0x1180080e06990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3379"             ,	   0x1180080e06998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3380"             ,	   0x1180080e069a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3381"             ,	   0x1180080e069a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3382"             ,	   0x1180080e069b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3383"             ,	   0x1180080e069b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3384"             ,	   0x1180080e069c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3385"             ,	   0x1180080e069c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3386"             ,	   0x1180080e069d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3387"             ,	   0x1180080e069d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3388"             ,	   0x1180080e069e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3389"             ,	   0x1180080e069e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3390"             ,	   0x1180080e069f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3391"             ,	   0x1180080e069f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3392"             ,	   0x1180080e06a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3393"             ,	   0x1180080e06a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3394"             ,	   0x1180080e06a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3395"             ,	   0x1180080e06a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3396"             ,	   0x1180080e06a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3397"             ,	   0x1180080e06a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3398"             ,	   0x1180080e06a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3399"             ,	   0x1180080e06a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3400"             ,	   0x1180080e06a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3401"             ,	   0x1180080e06a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3402"             ,	   0x1180080e06a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3403"             ,	   0x1180080e06a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3404"             ,	   0x1180080e06a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3405"             ,	   0x1180080e06a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3406"             ,	   0x1180080e06a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3407"             ,	   0x1180080e06a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3408"             ,	   0x1180080e06a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3409"             ,	   0x1180080e06a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3410"             ,	   0x1180080e06a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3411"             ,	   0x1180080e06a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3412"             ,	   0x1180080e06aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3413"             ,	   0x1180080e06aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3414"             ,	   0x1180080e06ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3415"             ,	   0x1180080e06ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3416"             ,	   0x1180080e06ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3417"             ,	   0x1180080e06ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3418"             ,	   0x1180080e06ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3419"             ,	   0x1180080e06ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3420"             ,	   0x1180080e06ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3421"             ,	   0x1180080e06ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3422"             ,	   0x1180080e06af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3423"             ,	   0x1180080e06af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3424"             ,	   0x1180080e06b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3425"             ,	   0x1180080e06b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3426"             ,	   0x1180080e06b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3427"             ,	   0x1180080e06b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3428"             ,	   0x1180080e06b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3429"             ,	   0x1180080e06b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3430"             ,	   0x1180080e06b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3431"             ,	   0x1180080e06b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3432"             ,	   0x1180080e06b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3433"             ,	   0x1180080e06b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3434"             ,	   0x1180080e06b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3435"             ,	   0x1180080e06b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3436"             ,	   0x1180080e06b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3437"             ,	   0x1180080e06b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3438"             ,	   0x1180080e06b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3439"             ,	   0x1180080e06b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3440"             ,	   0x1180080e06b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3441"             ,	   0x1180080e06b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3442"             ,	   0x1180080e06b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3443"             ,	   0x1180080e06b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3444"             ,	   0x1180080e06ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3445"             ,	   0x1180080e06ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3446"             ,	   0x1180080e06bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3447"             ,	   0x1180080e06bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3448"             ,	   0x1180080e06bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3449"             ,	   0x1180080e06bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3450"             ,	   0x1180080e06bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3451"             ,	   0x1180080e06bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3452"             ,	   0x1180080e06be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3453"             ,	   0x1180080e06be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3454"             ,	   0x1180080e06bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3455"             ,	   0x1180080e06bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3456"             ,	   0x1180080e06c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3457"             ,	   0x1180080e06c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3458"             ,	   0x1180080e06c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3459"             ,	   0x1180080e06c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3460"             ,	   0x1180080e06c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3461"             ,	   0x1180080e06c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3462"             ,	   0x1180080e06c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3463"             ,	   0x1180080e06c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3464"             ,	   0x1180080e06c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3465"             ,	   0x1180080e06c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3466"             ,	   0x1180080e06c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3467"             ,	   0x1180080e06c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3468"             ,	   0x1180080e06c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3469"             ,	   0x1180080e06c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3470"             ,	   0x1180080e06c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3471"             ,	   0x1180080e06c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3472"             ,	   0x1180080e06c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3473"             ,	   0x1180080e06c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3474"             ,	   0x1180080e06c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3475"             ,	   0x1180080e06c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3476"             ,	   0x1180080e06ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3477"             ,	   0x1180080e06ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3478"             ,	   0x1180080e06cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3479"             ,	   0x1180080e06cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3480"             ,	   0x1180080e06cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3481"             ,	   0x1180080e06cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3482"             ,	   0x1180080e06cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3483"             ,	   0x1180080e06cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3484"             ,	   0x1180080e06ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3485"             ,	   0x1180080e06ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3486"             ,	   0x1180080e06cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3487"             ,	   0x1180080e06cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3488"             ,	   0x1180080e06d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3489"             ,	   0x1180080e06d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3490"             ,	   0x1180080e06d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3491"             ,	   0x1180080e06d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3492"             ,	   0x1180080e06d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3493"             ,	   0x1180080e06d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3494"             ,	   0x1180080e06d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3495"             ,	   0x1180080e06d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3496"             ,	   0x1180080e06d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3497"             ,	   0x1180080e06d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3498"             ,	   0x1180080e06d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3499"             ,	   0x1180080e06d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3500"             ,	   0x1180080e06d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3501"             ,	   0x1180080e06d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3502"             ,	   0x1180080e06d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3503"             ,	   0x1180080e06d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3504"             ,	   0x1180080e06d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3505"             ,	   0x1180080e06d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3506"             ,	   0x1180080e06d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3507"             ,	   0x1180080e06d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3508"             ,	   0x1180080e06da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3509"             ,	   0x1180080e06da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3510"             ,	   0x1180080e06db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3511"             ,	   0x1180080e06db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3512"             ,	   0x1180080e06dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3513"             ,	   0x1180080e06dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3514"             ,	   0x1180080e06dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3515"             ,	   0x1180080e06dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3516"             ,	   0x1180080e06de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3517"             ,	   0x1180080e06de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3518"             ,	   0x1180080e06df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3519"             ,	   0x1180080e06df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3520"             ,	   0x1180080e06e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3521"             ,	   0x1180080e06e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3522"             ,	   0x1180080e06e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3523"             ,	   0x1180080e06e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3524"             ,	   0x1180080e06e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3525"             ,	   0x1180080e06e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3526"             ,	   0x1180080e06e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3527"             ,	   0x1180080e06e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3528"             ,	   0x1180080e06e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3529"             ,	   0x1180080e06e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3530"             ,	   0x1180080e06e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3531"             ,	   0x1180080e06e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3532"             ,	   0x1180080e06e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3533"             ,	   0x1180080e06e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3534"             ,	   0x1180080e06e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3535"             ,	   0x1180080e06e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3536"             ,	   0x1180080e06e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3537"             ,	   0x1180080e06e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3538"             ,	   0x1180080e06e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3539"             ,	   0x1180080e06e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3540"             ,	   0x1180080e06ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3541"             ,	   0x1180080e06ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3542"             ,	   0x1180080e06eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3543"             ,	   0x1180080e06eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3544"             ,	   0x1180080e06ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3545"             ,	   0x1180080e06ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3546"             ,	   0x1180080e06ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3547"             ,	   0x1180080e06ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3548"             ,	   0x1180080e06ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3549"             ,	   0x1180080e06ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3550"             ,	   0x1180080e06ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3551"             ,	   0x1180080e06ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3552"             ,	   0x1180080e06f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3553"             ,	   0x1180080e06f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3554"             ,	   0x1180080e06f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3555"             ,	   0x1180080e06f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3556"             ,	   0x1180080e06f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3557"             ,	   0x1180080e06f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3558"             ,	   0x1180080e06f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3559"             ,	   0x1180080e06f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3560"             ,	   0x1180080e06f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3561"             ,	   0x1180080e06f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3562"             ,	   0x1180080e06f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3563"             ,	   0x1180080e06f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3564"             ,	   0x1180080e06f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3565"             ,	   0x1180080e06f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3566"             ,	   0x1180080e06f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3567"             ,	   0x1180080e06f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3568"             ,	   0x1180080e06f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3569"             ,	   0x1180080e06f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3570"             ,	   0x1180080e06f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3571"             ,	   0x1180080e06f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3572"             ,	   0x1180080e06fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3573"             ,	   0x1180080e06fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3574"             ,	   0x1180080e06fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3575"             ,	   0x1180080e06fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3576"             ,	   0x1180080e06fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3577"             ,	   0x1180080e06fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3578"             ,	   0x1180080e06fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3579"             ,	   0x1180080e06fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3580"             ,	   0x1180080e06fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3581"             ,	   0x1180080e06fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3582"             ,	   0x1180080e06ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3583"             ,	   0x1180080e06ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3584"             ,	   0x1180080e07000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3585"             ,	   0x1180080e07008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3586"             ,	   0x1180080e07010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3587"             ,	   0x1180080e07018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3588"             ,	   0x1180080e07020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3589"             ,	   0x1180080e07028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3590"             ,	   0x1180080e07030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3591"             ,	   0x1180080e07038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3592"             ,	   0x1180080e07040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3593"             ,	   0x1180080e07048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3594"             ,	   0x1180080e07050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3595"             ,	   0x1180080e07058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3596"             ,	   0x1180080e07060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3597"             ,	   0x1180080e07068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3598"             ,	   0x1180080e07070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3599"             ,	   0x1180080e07078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3600"             ,	   0x1180080e07080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3601"             ,	   0x1180080e07088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3602"             ,	   0x1180080e07090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3603"             ,	   0x1180080e07098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3604"             ,	   0x1180080e070a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3605"             ,	   0x1180080e070a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3606"             ,	   0x1180080e070b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3607"             ,	   0x1180080e070b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3608"             ,	   0x1180080e070c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3609"             ,	   0x1180080e070c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3610"             ,	   0x1180080e070d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3611"             ,	   0x1180080e070d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3612"             ,	   0x1180080e070e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3613"             ,	   0x1180080e070e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3614"             ,	   0x1180080e070f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3615"             ,	   0x1180080e070f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3616"             ,	   0x1180080e07100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3617"             ,	   0x1180080e07108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3618"             ,	   0x1180080e07110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3619"             ,	   0x1180080e07118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3620"             ,	   0x1180080e07120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3621"             ,	   0x1180080e07128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3622"             ,	   0x1180080e07130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3623"             ,	   0x1180080e07138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3624"             ,	   0x1180080e07140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3625"             ,	   0x1180080e07148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3626"             ,	   0x1180080e07150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3627"             ,	   0x1180080e07158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3628"             ,	   0x1180080e07160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3629"             ,	   0x1180080e07168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3630"             ,	   0x1180080e07170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3631"             ,	   0x1180080e07178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3632"             ,	   0x1180080e07180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3633"             ,	   0x1180080e07188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3634"             ,	   0x1180080e07190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3635"             ,	   0x1180080e07198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3636"             ,	   0x1180080e071a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3637"             ,	   0x1180080e071a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3638"             ,	   0x1180080e071b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3639"             ,	   0x1180080e071b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3640"             ,	   0x1180080e071c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3641"             ,	   0x1180080e071c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3642"             ,	   0x1180080e071d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3643"             ,	   0x1180080e071d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3644"             ,	   0x1180080e071e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3645"             ,	   0x1180080e071e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3646"             ,	   0x1180080e071f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3647"             ,	   0x1180080e071f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3648"             ,	   0x1180080e07200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3649"             ,	   0x1180080e07208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3650"             ,	   0x1180080e07210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3651"             ,	   0x1180080e07218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3652"             ,	   0x1180080e07220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3653"             ,	   0x1180080e07228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3654"             ,	   0x1180080e07230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3655"             ,	   0x1180080e07238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3656"             ,	   0x1180080e07240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3657"             ,	   0x1180080e07248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3658"             ,	   0x1180080e07250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3659"             ,	   0x1180080e07258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3660"             ,	   0x1180080e07260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3661"             ,	   0x1180080e07268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3662"             ,	   0x1180080e07270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3663"             ,	   0x1180080e07278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3664"             ,	   0x1180080e07280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3665"             ,	   0x1180080e07288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3666"             ,	   0x1180080e07290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3667"             ,	   0x1180080e07298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3668"             ,	   0x1180080e072a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3669"             ,	   0x1180080e072a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3670"             ,	   0x1180080e072b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3671"             ,	   0x1180080e072b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3672"             ,	   0x1180080e072c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3673"             ,	   0x1180080e072c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3674"             ,	   0x1180080e072d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3675"             ,	   0x1180080e072d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3676"             ,	   0x1180080e072e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3677"             ,	   0x1180080e072e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3678"             ,	   0x1180080e072f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3679"             ,	   0x1180080e072f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3680"             ,	   0x1180080e07300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3681"             ,	   0x1180080e07308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3682"             ,	   0x1180080e07310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3683"             ,	   0x1180080e07318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3684"             ,	   0x1180080e07320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3685"             ,	   0x1180080e07328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3686"             ,	   0x1180080e07330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3687"             ,	   0x1180080e07338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3688"             ,	   0x1180080e07340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3689"             ,	   0x1180080e07348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3690"             ,	   0x1180080e07350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3691"             ,	   0x1180080e07358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3692"             ,	   0x1180080e07360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3693"             ,	   0x1180080e07368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3694"             ,	   0x1180080e07370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3695"             ,	   0x1180080e07378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3696"             ,	   0x1180080e07380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3697"             ,	   0x1180080e07388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3698"             ,	   0x1180080e07390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3699"             ,	   0x1180080e07398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3700"             ,	   0x1180080e073a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3701"             ,	   0x1180080e073a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3702"             ,	   0x1180080e073b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3703"             ,	   0x1180080e073b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3704"             ,	   0x1180080e073c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3705"             ,	   0x1180080e073c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3706"             ,	   0x1180080e073d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3707"             ,	   0x1180080e073d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3708"             ,	   0x1180080e073e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3709"             ,	   0x1180080e073e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3710"             ,	   0x1180080e073f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3711"             ,	   0x1180080e073f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3712"             ,	   0x1180080e07400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3713"             ,	   0x1180080e07408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3714"             ,	   0x1180080e07410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3715"             ,	   0x1180080e07418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3716"             ,	   0x1180080e07420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3717"             ,	   0x1180080e07428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3718"             ,	   0x1180080e07430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3719"             ,	   0x1180080e07438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3720"             ,	   0x1180080e07440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3721"             ,	   0x1180080e07448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3722"             ,	   0x1180080e07450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3723"             ,	   0x1180080e07458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3724"             ,	   0x1180080e07460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3725"             ,	   0x1180080e07468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3726"             ,	   0x1180080e07470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3727"             ,	   0x1180080e07478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3728"             ,	   0x1180080e07480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3729"             ,	   0x1180080e07488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3730"             ,	   0x1180080e07490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3731"             ,	   0x1180080e07498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3732"             ,	   0x1180080e074a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3733"             ,	   0x1180080e074a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3734"             ,	   0x1180080e074b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3735"             ,	   0x1180080e074b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3736"             ,	   0x1180080e074c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3737"             ,	   0x1180080e074c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3738"             ,	   0x1180080e074d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3739"             ,	   0x1180080e074d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3740"             ,	   0x1180080e074e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3741"             ,	   0x1180080e074e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3742"             ,	   0x1180080e074f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3743"             ,	   0x1180080e074f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3744"             ,	   0x1180080e07500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3745"             ,	   0x1180080e07508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3746"             ,	   0x1180080e07510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3747"             ,	   0x1180080e07518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3748"             ,	   0x1180080e07520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3749"             ,	   0x1180080e07528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3750"             ,	   0x1180080e07530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3751"             ,	   0x1180080e07538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3752"             ,	   0x1180080e07540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3753"             ,	   0x1180080e07548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3754"             ,	   0x1180080e07550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3755"             ,	   0x1180080e07558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3756"             ,	   0x1180080e07560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3757"             ,	   0x1180080e07568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3758"             ,	   0x1180080e07570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3759"             ,	   0x1180080e07578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3760"             ,	   0x1180080e07580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3761"             ,	   0x1180080e07588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3762"             ,	   0x1180080e07590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3763"             ,	   0x1180080e07598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3764"             ,	   0x1180080e075a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3765"             ,	   0x1180080e075a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3766"             ,	   0x1180080e075b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3767"             ,	   0x1180080e075b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3768"             ,	   0x1180080e075c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3769"             ,	   0x1180080e075c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3770"             ,	   0x1180080e075d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3771"             ,	   0x1180080e075d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3772"             ,	   0x1180080e075e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3773"             ,	   0x1180080e075e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3774"             ,	   0x1180080e075f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3775"             ,	   0x1180080e075f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3776"             ,	   0x1180080e07600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3777"             ,	   0x1180080e07608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3778"             ,	   0x1180080e07610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3779"             ,	   0x1180080e07618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3780"             ,	   0x1180080e07620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3781"             ,	   0x1180080e07628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3782"             ,	   0x1180080e07630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3783"             ,	   0x1180080e07638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3784"             ,	   0x1180080e07640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3785"             ,	   0x1180080e07648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3786"             ,	   0x1180080e07650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3787"             ,	   0x1180080e07658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3788"             ,	   0x1180080e07660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3789"             ,	   0x1180080e07668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3790"             ,	   0x1180080e07670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3791"             ,	   0x1180080e07678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3792"             ,	   0x1180080e07680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3793"             ,	   0x1180080e07688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3794"             ,	   0x1180080e07690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3795"             ,	   0x1180080e07698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3796"             ,	   0x1180080e076a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3797"             ,	   0x1180080e076a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3798"             ,	   0x1180080e076b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3799"             ,	   0x1180080e076b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3800"             ,	   0x1180080e076c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3801"             ,	   0x1180080e076c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3802"             ,	   0x1180080e076d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3803"             ,	   0x1180080e076d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3804"             ,	   0x1180080e076e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3805"             ,	   0x1180080e076e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3806"             ,	   0x1180080e076f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3807"             ,	   0x1180080e076f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3808"             ,	   0x1180080e07700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3809"             ,	   0x1180080e07708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3810"             ,	   0x1180080e07710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3811"             ,	   0x1180080e07718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3812"             ,	   0x1180080e07720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3813"             ,	   0x1180080e07728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3814"             ,	   0x1180080e07730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3815"             ,	   0x1180080e07738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3816"             ,	   0x1180080e07740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3817"             ,	   0x1180080e07748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3818"             ,	   0x1180080e07750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3819"             ,	   0x1180080e07758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3820"             ,	   0x1180080e07760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3821"             ,	   0x1180080e07768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3822"             ,	   0x1180080e07770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3823"             ,	   0x1180080e07778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3824"             ,	   0x1180080e07780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3825"             ,	   0x1180080e07788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3826"             ,	   0x1180080e07790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3827"             ,	   0x1180080e07798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3828"             ,	   0x1180080e077a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3829"             ,	   0x1180080e077a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3830"             ,	   0x1180080e077b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3831"             ,	   0x1180080e077b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3832"             ,	   0x1180080e077c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3833"             ,	   0x1180080e077c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3834"             ,	   0x1180080e077d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3835"             ,	   0x1180080e077d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3836"             ,	   0x1180080e077e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3837"             ,	   0x1180080e077e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3838"             ,	   0x1180080e077f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3839"             ,	   0x1180080e077f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3840"             ,	   0x1180080e07800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3841"             ,	   0x1180080e07808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3842"             ,	   0x1180080e07810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3843"             ,	   0x1180080e07818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3844"             ,	   0x1180080e07820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3845"             ,	   0x1180080e07828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3846"             ,	   0x1180080e07830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3847"             ,	   0x1180080e07838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3848"             ,	   0x1180080e07840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3849"             ,	   0x1180080e07848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3850"             ,	   0x1180080e07850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3851"             ,	   0x1180080e07858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3852"             ,	   0x1180080e07860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3853"             ,	   0x1180080e07868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3854"             ,	   0x1180080e07870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3855"             ,	   0x1180080e07878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3856"             ,	   0x1180080e07880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3857"             ,	   0x1180080e07888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3858"             ,	   0x1180080e07890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3859"             ,	   0x1180080e07898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3860"             ,	   0x1180080e078a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3861"             ,	   0x1180080e078a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3862"             ,	   0x1180080e078b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3863"             ,	   0x1180080e078b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3864"             ,	   0x1180080e078c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3865"             ,	   0x1180080e078c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3866"             ,	   0x1180080e078d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3867"             ,	   0x1180080e078d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3868"             ,	   0x1180080e078e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3869"             ,	   0x1180080e078e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3870"             ,	   0x1180080e078f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3871"             ,	   0x1180080e078f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3872"             ,	   0x1180080e07900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3873"             ,	   0x1180080e07908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3874"             ,	   0x1180080e07910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3875"             ,	   0x1180080e07918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3876"             ,	   0x1180080e07920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3877"             ,	   0x1180080e07928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3878"             ,	   0x1180080e07930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3879"             ,	   0x1180080e07938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3880"             ,	   0x1180080e07940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3881"             ,	   0x1180080e07948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3882"             ,	   0x1180080e07950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3883"             ,	   0x1180080e07958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3884"             ,	   0x1180080e07960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3885"             ,	   0x1180080e07968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3886"             ,	   0x1180080e07970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3887"             ,	   0x1180080e07978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3888"             ,	   0x1180080e07980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3889"             ,	   0x1180080e07988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3890"             ,	   0x1180080e07990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3891"             ,	   0x1180080e07998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3892"             ,	   0x1180080e079a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3893"             ,	   0x1180080e079a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3894"             ,	   0x1180080e079b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3895"             ,	   0x1180080e079b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3896"             ,	   0x1180080e079c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3897"             ,	   0x1180080e079c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3898"             ,	   0x1180080e079d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3899"             ,	   0x1180080e079d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3900"             ,	   0x1180080e079e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3901"             ,	   0x1180080e079e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3902"             ,	   0x1180080e079f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3903"             ,	   0x1180080e079f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3904"             ,	   0x1180080e07a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3905"             ,	   0x1180080e07a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3906"             ,	   0x1180080e07a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3907"             ,	   0x1180080e07a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3908"             ,	   0x1180080e07a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3909"             ,	   0x1180080e07a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3910"             ,	   0x1180080e07a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3911"             ,	   0x1180080e07a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3912"             ,	   0x1180080e07a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3913"             ,	   0x1180080e07a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3914"             ,	   0x1180080e07a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3915"             ,	   0x1180080e07a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3916"             ,	   0x1180080e07a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3917"             ,	   0x1180080e07a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3918"             ,	   0x1180080e07a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3919"             ,	   0x1180080e07a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3920"             ,	   0x1180080e07a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3921"             ,	   0x1180080e07a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3922"             ,	   0x1180080e07a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3923"             ,	   0x1180080e07a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3924"             ,	   0x1180080e07aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3925"             ,	   0x1180080e07aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3926"             ,	   0x1180080e07ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3927"             ,	   0x1180080e07ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3928"             ,	   0x1180080e07ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3929"             ,	   0x1180080e07ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3930"             ,	   0x1180080e07ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3931"             ,	   0x1180080e07ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3932"             ,	   0x1180080e07ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3933"             ,	   0x1180080e07ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3934"             ,	   0x1180080e07af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3935"             ,	   0x1180080e07af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3936"             ,	   0x1180080e07b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3937"             ,	   0x1180080e07b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3938"             ,	   0x1180080e07b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3939"             ,	   0x1180080e07b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3940"             ,	   0x1180080e07b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3941"             ,	   0x1180080e07b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3942"             ,	   0x1180080e07b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3943"             ,	   0x1180080e07b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3944"             ,	   0x1180080e07b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3945"             ,	   0x1180080e07b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3946"             ,	   0x1180080e07b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3947"             ,	   0x1180080e07b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3948"             ,	   0x1180080e07b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3949"             ,	   0x1180080e07b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3950"             ,	   0x1180080e07b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3951"             ,	   0x1180080e07b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3952"             ,	   0x1180080e07b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3953"             ,	   0x1180080e07b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3954"             ,	   0x1180080e07b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3955"             ,	   0x1180080e07b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3956"             ,	   0x1180080e07ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3957"             ,	   0x1180080e07ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3958"             ,	   0x1180080e07bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3959"             ,	   0x1180080e07bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3960"             ,	   0x1180080e07bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3961"             ,	   0x1180080e07bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3962"             ,	   0x1180080e07bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3963"             ,	   0x1180080e07bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3964"             ,	   0x1180080e07be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3965"             ,	   0x1180080e07be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3966"             ,	   0x1180080e07bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3967"             ,	   0x1180080e07bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3968"             ,	   0x1180080e07c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3969"             ,	   0x1180080e07c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3970"             ,	   0x1180080e07c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3971"             ,	   0x1180080e07c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3972"             ,	   0x1180080e07c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3973"             ,	   0x1180080e07c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3974"             ,	   0x1180080e07c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3975"             ,	   0x1180080e07c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3976"             ,	   0x1180080e07c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3977"             ,	   0x1180080e07c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3978"             ,	   0x1180080e07c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3979"             ,	   0x1180080e07c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3980"             ,	   0x1180080e07c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3981"             ,	   0x1180080e07c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3982"             ,	   0x1180080e07c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3983"             ,	   0x1180080e07c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3984"             ,	   0x1180080e07c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3985"             ,	   0x1180080e07c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3986"             ,	   0x1180080e07c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3987"             ,	   0x1180080e07c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3988"             ,	   0x1180080e07ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3989"             ,	   0x1180080e07ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3990"             ,	   0x1180080e07cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3991"             ,	   0x1180080e07cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3992"             ,	   0x1180080e07cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3993"             ,	   0x1180080e07cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3994"             ,	   0x1180080e07cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3995"             ,	   0x1180080e07cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3996"             ,	   0x1180080e07ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3997"             ,	   0x1180080e07ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3998"             ,	   0x1180080e07cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP3999"             ,	   0x1180080e07cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4000"             ,	   0x1180080e07d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4001"             ,	   0x1180080e07d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4002"             ,	   0x1180080e07d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4003"             ,	   0x1180080e07d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4004"             ,	   0x1180080e07d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4005"             ,	   0x1180080e07d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4006"             ,	   0x1180080e07d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4007"             ,	   0x1180080e07d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4008"             ,	   0x1180080e07d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4009"             ,	   0x1180080e07d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4010"             ,	   0x1180080e07d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4011"             ,	   0x1180080e07d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4012"             ,	   0x1180080e07d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4013"             ,	   0x1180080e07d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4014"             ,	   0x1180080e07d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4015"             ,	   0x1180080e07d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4016"             ,	   0x1180080e07d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4017"             ,	   0x1180080e07d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4018"             ,	   0x1180080e07d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4019"             ,	   0x1180080e07d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4020"             ,	   0x1180080e07da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4021"             ,	   0x1180080e07da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4022"             ,	   0x1180080e07db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4023"             ,	   0x1180080e07db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4024"             ,	   0x1180080e07dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4025"             ,	   0x1180080e07dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4026"             ,	   0x1180080e07dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4027"             ,	   0x1180080e07dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4028"             ,	   0x1180080e07de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4029"             ,	   0x1180080e07de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4030"             ,	   0x1180080e07df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4031"             ,	   0x1180080e07df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4032"             ,	   0x1180080e07e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4033"             ,	   0x1180080e07e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4034"             ,	   0x1180080e07e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4035"             ,	   0x1180080e07e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4036"             ,	   0x1180080e07e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4037"             ,	   0x1180080e07e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4038"             ,	   0x1180080e07e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4039"             ,	   0x1180080e07e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4040"             ,	   0x1180080e07e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4041"             ,	   0x1180080e07e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4042"             ,	   0x1180080e07e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4043"             ,	   0x1180080e07e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4044"             ,	   0x1180080e07e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4045"             ,	   0x1180080e07e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4046"             ,	   0x1180080e07e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4047"             ,	   0x1180080e07e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4048"             ,	   0x1180080e07e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4049"             ,	   0x1180080e07e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4050"             ,	   0x1180080e07e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4051"             ,	   0x1180080e07e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4052"             ,	   0x1180080e07ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4053"             ,	   0x1180080e07ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4054"             ,	   0x1180080e07eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4055"             ,	   0x1180080e07eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4056"             ,	   0x1180080e07ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4057"             ,	   0x1180080e07ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4058"             ,	   0x1180080e07ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4059"             ,	   0x1180080e07ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4060"             ,	   0x1180080e07ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4061"             ,	   0x1180080e07ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4062"             ,	   0x1180080e07ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4063"             ,	   0x1180080e07ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4064"             ,	   0x1180080e07f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4065"             ,	   0x1180080e07f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4066"             ,	   0x1180080e07f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4067"             ,	   0x1180080e07f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4068"             ,	   0x1180080e07f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4069"             ,	   0x1180080e07f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4070"             ,	   0x1180080e07f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4071"             ,	   0x1180080e07f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4072"             ,	   0x1180080e07f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4073"             ,	   0x1180080e07f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4074"             ,	   0x1180080e07f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4075"             ,	   0x1180080e07f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4076"             ,	   0x1180080e07f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4077"             ,	   0x1180080e07f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4078"             ,	   0x1180080e07f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4079"             ,	   0x1180080e07f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4080"             ,	   0x1180080e07f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4081"             ,	   0x1180080e07f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4082"             ,	   0x1180080e07f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4083"             ,	   0x1180080e07f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4084"             ,	   0x1180080e07fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4085"             ,	   0x1180080e07fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4086"             ,	   0x1180080e07fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4087"             ,	   0x1180080e07fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4088"             ,	   0x1180080e07fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4089"             ,	   0x1180080e07fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4090"             ,	   0x1180080e07fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4091"             ,	   0x1180080e07fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4092"             ,	   0x1180080e07fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4093"             ,	   0x1180080e07fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4094"             ,	   0x1180080e07ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4095"             ,	   0x1180080e07ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4096"             ,	   0x1180080e08000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4097"             ,	   0x1180080e08008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4098"             ,	   0x1180080e08010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4099"             ,	   0x1180080e08018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4100"             ,	   0x1180080e08020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4101"             ,	   0x1180080e08028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4102"             ,	   0x1180080e08030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4103"             ,	   0x1180080e08038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4104"             ,	   0x1180080e08040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4105"             ,	   0x1180080e08048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4106"             ,	   0x1180080e08050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4107"             ,	   0x1180080e08058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4108"             ,	   0x1180080e08060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4109"             ,	   0x1180080e08068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4110"             ,	   0x1180080e08070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4111"             ,	   0x1180080e08078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4112"             ,	   0x1180080e08080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4113"             ,	   0x1180080e08088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4114"             ,	   0x1180080e08090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4115"             ,	   0x1180080e08098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4116"             ,	   0x1180080e080a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4117"             ,	   0x1180080e080a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4118"             ,	   0x1180080e080b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4119"             ,	   0x1180080e080b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4120"             ,	   0x1180080e080c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4121"             ,	   0x1180080e080c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4122"             ,	   0x1180080e080d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4123"             ,	   0x1180080e080d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4124"             ,	   0x1180080e080e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4125"             ,	   0x1180080e080e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4126"             ,	   0x1180080e080f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4127"             ,	   0x1180080e080f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4128"             ,	   0x1180080e08100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4129"             ,	   0x1180080e08108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4130"             ,	   0x1180080e08110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4131"             ,	   0x1180080e08118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4132"             ,	   0x1180080e08120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4133"             ,	   0x1180080e08128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4134"             ,	   0x1180080e08130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4135"             ,	   0x1180080e08138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4136"             ,	   0x1180080e08140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4137"             ,	   0x1180080e08148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4138"             ,	   0x1180080e08150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4139"             ,	   0x1180080e08158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4140"             ,	   0x1180080e08160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4141"             ,	   0x1180080e08168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4142"             ,	   0x1180080e08170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4143"             ,	   0x1180080e08178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4144"             ,	   0x1180080e08180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4145"             ,	   0x1180080e08188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4146"             ,	   0x1180080e08190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4147"             ,	   0x1180080e08198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4148"             ,	   0x1180080e081a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4149"             ,	   0x1180080e081a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4150"             ,	   0x1180080e081b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4151"             ,	   0x1180080e081b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4152"             ,	   0x1180080e081c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4153"             ,	   0x1180080e081c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4154"             ,	   0x1180080e081d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4155"             ,	   0x1180080e081d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4156"             ,	   0x1180080e081e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4157"             ,	   0x1180080e081e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4158"             ,	   0x1180080e081f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4159"             ,	   0x1180080e081f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4160"             ,	   0x1180080e08200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4161"             ,	   0x1180080e08208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4162"             ,	   0x1180080e08210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4163"             ,	   0x1180080e08218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4164"             ,	   0x1180080e08220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4165"             ,	   0x1180080e08228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4166"             ,	   0x1180080e08230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4167"             ,	   0x1180080e08238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4168"             ,	   0x1180080e08240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4169"             ,	   0x1180080e08248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4170"             ,	   0x1180080e08250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4171"             ,	   0x1180080e08258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4172"             ,	   0x1180080e08260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4173"             ,	   0x1180080e08268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4174"             ,	   0x1180080e08270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4175"             ,	   0x1180080e08278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4176"             ,	   0x1180080e08280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4177"             ,	   0x1180080e08288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4178"             ,	   0x1180080e08290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4179"             ,	   0x1180080e08298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4180"             ,	   0x1180080e082a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4181"             ,	   0x1180080e082a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4182"             ,	   0x1180080e082b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4183"             ,	   0x1180080e082b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4184"             ,	   0x1180080e082c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4185"             ,	   0x1180080e082c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4186"             ,	   0x1180080e082d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4187"             ,	   0x1180080e082d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4188"             ,	   0x1180080e082e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4189"             ,	   0x1180080e082e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4190"             ,	   0x1180080e082f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4191"             ,	   0x1180080e082f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4192"             ,	   0x1180080e08300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4193"             ,	   0x1180080e08308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4194"             ,	   0x1180080e08310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4195"             ,	   0x1180080e08318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4196"             ,	   0x1180080e08320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4197"             ,	   0x1180080e08328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4198"             ,	   0x1180080e08330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4199"             ,	   0x1180080e08338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4200"             ,	   0x1180080e08340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4201"             ,	   0x1180080e08348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4202"             ,	   0x1180080e08350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4203"             ,	   0x1180080e08358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4204"             ,	   0x1180080e08360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4205"             ,	   0x1180080e08368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4206"             ,	   0x1180080e08370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4207"             ,	   0x1180080e08378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4208"             ,	   0x1180080e08380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4209"             ,	   0x1180080e08388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4210"             ,	   0x1180080e08390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4211"             ,	   0x1180080e08398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4212"             ,	   0x1180080e083a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4213"             ,	   0x1180080e083a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4214"             ,	   0x1180080e083b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4215"             ,	   0x1180080e083b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4216"             ,	   0x1180080e083c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4217"             ,	   0x1180080e083c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4218"             ,	   0x1180080e083d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4219"             ,	   0x1180080e083d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4220"             ,	   0x1180080e083e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4221"             ,	   0x1180080e083e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4222"             ,	   0x1180080e083f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4223"             ,	   0x1180080e083f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4224"             ,	   0x1180080e08400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4225"             ,	   0x1180080e08408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4226"             ,	   0x1180080e08410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4227"             ,	   0x1180080e08418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4228"             ,	   0x1180080e08420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4229"             ,	   0x1180080e08428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4230"             ,	   0x1180080e08430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4231"             ,	   0x1180080e08438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4232"             ,	   0x1180080e08440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4233"             ,	   0x1180080e08448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4234"             ,	   0x1180080e08450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4235"             ,	   0x1180080e08458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4236"             ,	   0x1180080e08460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4237"             ,	   0x1180080e08468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4238"             ,	   0x1180080e08470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4239"             ,	   0x1180080e08478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4240"             ,	   0x1180080e08480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4241"             ,	   0x1180080e08488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4242"             ,	   0x1180080e08490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4243"             ,	   0x1180080e08498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4244"             ,	   0x1180080e084a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4245"             ,	   0x1180080e084a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4246"             ,	   0x1180080e084b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4247"             ,	   0x1180080e084b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4248"             ,	   0x1180080e084c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4249"             ,	   0x1180080e084c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4250"             ,	   0x1180080e084d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4251"             ,	   0x1180080e084d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4252"             ,	   0x1180080e084e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4253"             ,	   0x1180080e084e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4254"             ,	   0x1180080e084f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4255"             ,	   0x1180080e084f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4256"             ,	   0x1180080e08500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4257"             ,	   0x1180080e08508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4258"             ,	   0x1180080e08510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4259"             ,	   0x1180080e08518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4260"             ,	   0x1180080e08520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4261"             ,	   0x1180080e08528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4262"             ,	   0x1180080e08530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4263"             ,	   0x1180080e08538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4264"             ,	   0x1180080e08540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4265"             ,	   0x1180080e08548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4266"             ,	   0x1180080e08550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4267"             ,	   0x1180080e08558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4268"             ,	   0x1180080e08560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4269"             ,	   0x1180080e08568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4270"             ,	   0x1180080e08570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4271"             ,	   0x1180080e08578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4272"             ,	   0x1180080e08580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4273"             ,	   0x1180080e08588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4274"             ,	   0x1180080e08590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4275"             ,	   0x1180080e08598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4276"             ,	   0x1180080e085a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4277"             ,	   0x1180080e085a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4278"             ,	   0x1180080e085b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4279"             ,	   0x1180080e085b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4280"             ,	   0x1180080e085c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4281"             ,	   0x1180080e085c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4282"             ,	   0x1180080e085d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4283"             ,	   0x1180080e085d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4284"             ,	   0x1180080e085e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4285"             ,	   0x1180080e085e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4286"             ,	   0x1180080e085f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4287"             ,	   0x1180080e085f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4288"             ,	   0x1180080e08600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4289"             ,	   0x1180080e08608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4290"             ,	   0x1180080e08610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4291"             ,	   0x1180080e08618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4292"             ,	   0x1180080e08620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4293"             ,	   0x1180080e08628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4294"             ,	   0x1180080e08630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4295"             ,	   0x1180080e08638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4296"             ,	   0x1180080e08640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4297"             ,	   0x1180080e08648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4298"             ,	   0x1180080e08650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4299"             ,	   0x1180080e08658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4300"             ,	   0x1180080e08660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4301"             ,	   0x1180080e08668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4302"             ,	   0x1180080e08670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4303"             ,	   0x1180080e08678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4304"             ,	   0x1180080e08680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4305"             ,	   0x1180080e08688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4306"             ,	   0x1180080e08690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4307"             ,	   0x1180080e08698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4308"             ,	   0x1180080e086a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4309"             ,	   0x1180080e086a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4310"             ,	   0x1180080e086b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4311"             ,	   0x1180080e086b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4312"             ,	   0x1180080e086c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4313"             ,	   0x1180080e086c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4314"             ,	   0x1180080e086d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4315"             ,	   0x1180080e086d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4316"             ,	   0x1180080e086e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4317"             ,	   0x1180080e086e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4318"             ,	   0x1180080e086f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4319"             ,	   0x1180080e086f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4320"             ,	   0x1180080e08700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4321"             ,	   0x1180080e08708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4322"             ,	   0x1180080e08710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4323"             ,	   0x1180080e08718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4324"             ,	   0x1180080e08720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4325"             ,	   0x1180080e08728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4326"             ,	   0x1180080e08730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4327"             ,	   0x1180080e08738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4328"             ,	   0x1180080e08740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4329"             ,	   0x1180080e08748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4330"             ,	   0x1180080e08750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4331"             ,	   0x1180080e08758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4332"             ,	   0x1180080e08760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4333"             ,	   0x1180080e08768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4334"             ,	   0x1180080e08770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4335"             ,	   0x1180080e08778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4336"             ,	   0x1180080e08780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4337"             ,	   0x1180080e08788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4338"             ,	   0x1180080e08790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4339"             ,	   0x1180080e08798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4340"             ,	   0x1180080e087a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4341"             ,	   0x1180080e087a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4342"             ,	   0x1180080e087b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4343"             ,	   0x1180080e087b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4344"             ,	   0x1180080e087c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4345"             ,	   0x1180080e087c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4346"             ,	   0x1180080e087d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4347"             ,	   0x1180080e087d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4348"             ,	   0x1180080e087e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4349"             ,	   0x1180080e087e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4350"             ,	   0x1180080e087f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4351"             ,	   0x1180080e087f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4352"             ,	   0x1180080e08800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4353"             ,	   0x1180080e08808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4354"             ,	   0x1180080e08810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4355"             ,	   0x1180080e08818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4356"             ,	   0x1180080e08820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4357"             ,	   0x1180080e08828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4358"             ,	   0x1180080e08830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4359"             ,	   0x1180080e08838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4360"             ,	   0x1180080e08840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4361"             ,	   0x1180080e08848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4362"             ,	   0x1180080e08850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4363"             ,	   0x1180080e08858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4364"             ,	   0x1180080e08860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4365"             ,	   0x1180080e08868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4366"             ,	   0x1180080e08870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4367"             ,	   0x1180080e08878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4368"             ,	   0x1180080e08880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4369"             ,	   0x1180080e08888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4370"             ,	   0x1180080e08890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4371"             ,	   0x1180080e08898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4372"             ,	   0x1180080e088a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4373"             ,	   0x1180080e088a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4374"             ,	   0x1180080e088b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4375"             ,	   0x1180080e088b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4376"             ,	   0x1180080e088c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4377"             ,	   0x1180080e088c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4378"             ,	   0x1180080e088d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4379"             ,	   0x1180080e088d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4380"             ,	   0x1180080e088e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4381"             ,	   0x1180080e088e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4382"             ,	   0x1180080e088f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4383"             ,	   0x1180080e088f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4384"             ,	   0x1180080e08900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4385"             ,	   0x1180080e08908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4386"             ,	   0x1180080e08910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4387"             ,	   0x1180080e08918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4388"             ,	   0x1180080e08920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4389"             ,	   0x1180080e08928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4390"             ,	   0x1180080e08930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4391"             ,	   0x1180080e08938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4392"             ,	   0x1180080e08940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4393"             ,	   0x1180080e08948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4394"             ,	   0x1180080e08950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4395"             ,	   0x1180080e08958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4396"             ,	   0x1180080e08960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4397"             ,	   0x1180080e08968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4398"             ,	   0x1180080e08970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4399"             ,	   0x1180080e08978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4400"             ,	   0x1180080e08980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4401"             ,	   0x1180080e08988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4402"             ,	   0x1180080e08990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4403"             ,	   0x1180080e08998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4404"             ,	   0x1180080e089a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4405"             ,	   0x1180080e089a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4406"             ,	   0x1180080e089b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4407"             ,	   0x1180080e089b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4408"             ,	   0x1180080e089c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4409"             ,	   0x1180080e089c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4410"             ,	   0x1180080e089d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4411"             ,	   0x1180080e089d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4412"             ,	   0x1180080e089e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4413"             ,	   0x1180080e089e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4414"             ,	   0x1180080e089f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4415"             ,	   0x1180080e089f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4416"             ,	   0x1180080e08a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4417"             ,	   0x1180080e08a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4418"             ,	   0x1180080e08a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4419"             ,	   0x1180080e08a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4420"             ,	   0x1180080e08a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4421"             ,	   0x1180080e08a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4422"             ,	   0x1180080e08a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4423"             ,	   0x1180080e08a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4424"             ,	   0x1180080e08a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4425"             ,	   0x1180080e08a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4426"             ,	   0x1180080e08a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4427"             ,	   0x1180080e08a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4428"             ,	   0x1180080e08a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4429"             ,	   0x1180080e08a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4430"             ,	   0x1180080e08a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4431"             ,	   0x1180080e08a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4432"             ,	   0x1180080e08a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4433"             ,	   0x1180080e08a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4434"             ,	   0x1180080e08a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4435"             ,	   0x1180080e08a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4436"             ,	   0x1180080e08aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4437"             ,	   0x1180080e08aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4438"             ,	   0x1180080e08ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4439"             ,	   0x1180080e08ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4440"             ,	   0x1180080e08ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4441"             ,	   0x1180080e08ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4442"             ,	   0x1180080e08ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4443"             ,	   0x1180080e08ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4444"             ,	   0x1180080e08ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4445"             ,	   0x1180080e08ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4446"             ,	   0x1180080e08af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4447"             ,	   0x1180080e08af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4448"             ,	   0x1180080e08b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4449"             ,	   0x1180080e08b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4450"             ,	   0x1180080e08b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4451"             ,	   0x1180080e08b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4452"             ,	   0x1180080e08b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4453"             ,	   0x1180080e08b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4454"             ,	   0x1180080e08b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4455"             ,	   0x1180080e08b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4456"             ,	   0x1180080e08b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4457"             ,	   0x1180080e08b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4458"             ,	   0x1180080e08b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4459"             ,	   0x1180080e08b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4460"             ,	   0x1180080e08b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4461"             ,	   0x1180080e08b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4462"             ,	   0x1180080e08b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4463"             ,	   0x1180080e08b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4464"             ,	   0x1180080e08b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4465"             ,	   0x1180080e08b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4466"             ,	   0x1180080e08b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4467"             ,	   0x1180080e08b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4468"             ,	   0x1180080e08ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4469"             ,	   0x1180080e08ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4470"             ,	   0x1180080e08bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4471"             ,	   0x1180080e08bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4472"             ,	   0x1180080e08bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4473"             ,	   0x1180080e08bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4474"             ,	   0x1180080e08bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4475"             ,	   0x1180080e08bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4476"             ,	   0x1180080e08be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4477"             ,	   0x1180080e08be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4478"             ,	   0x1180080e08bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4479"             ,	   0x1180080e08bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4480"             ,	   0x1180080e08c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4481"             ,	   0x1180080e08c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4482"             ,	   0x1180080e08c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4483"             ,	   0x1180080e08c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4484"             ,	   0x1180080e08c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4485"             ,	   0x1180080e08c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4486"             ,	   0x1180080e08c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4487"             ,	   0x1180080e08c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4488"             ,	   0x1180080e08c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4489"             ,	   0x1180080e08c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4490"             ,	   0x1180080e08c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4491"             ,	   0x1180080e08c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4492"             ,	   0x1180080e08c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4493"             ,	   0x1180080e08c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4494"             ,	   0x1180080e08c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4495"             ,	   0x1180080e08c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4496"             ,	   0x1180080e08c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4497"             ,	   0x1180080e08c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4498"             ,	   0x1180080e08c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4499"             ,	   0x1180080e08c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4500"             ,	   0x1180080e08ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4501"             ,	   0x1180080e08ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4502"             ,	   0x1180080e08cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4503"             ,	   0x1180080e08cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4504"             ,	   0x1180080e08cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4505"             ,	   0x1180080e08cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4506"             ,	   0x1180080e08cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4507"             ,	   0x1180080e08cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4508"             ,	   0x1180080e08ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4509"             ,	   0x1180080e08ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4510"             ,	   0x1180080e08cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4511"             ,	   0x1180080e08cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4512"             ,	   0x1180080e08d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4513"             ,	   0x1180080e08d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4514"             ,	   0x1180080e08d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4515"             ,	   0x1180080e08d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4516"             ,	   0x1180080e08d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4517"             ,	   0x1180080e08d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4518"             ,	   0x1180080e08d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4519"             ,	   0x1180080e08d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4520"             ,	   0x1180080e08d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4521"             ,	   0x1180080e08d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4522"             ,	   0x1180080e08d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4523"             ,	   0x1180080e08d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4524"             ,	   0x1180080e08d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4525"             ,	   0x1180080e08d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4526"             ,	   0x1180080e08d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4527"             ,	   0x1180080e08d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4528"             ,	   0x1180080e08d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4529"             ,	   0x1180080e08d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4530"             ,	   0x1180080e08d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4531"             ,	   0x1180080e08d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4532"             ,	   0x1180080e08da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4533"             ,	   0x1180080e08da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4534"             ,	   0x1180080e08db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4535"             ,	   0x1180080e08db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4536"             ,	   0x1180080e08dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4537"             ,	   0x1180080e08dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4538"             ,	   0x1180080e08dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4539"             ,	   0x1180080e08dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4540"             ,	   0x1180080e08de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4541"             ,	   0x1180080e08de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4542"             ,	   0x1180080e08df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4543"             ,	   0x1180080e08df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4544"             ,	   0x1180080e08e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4545"             ,	   0x1180080e08e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4546"             ,	   0x1180080e08e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4547"             ,	   0x1180080e08e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4548"             ,	   0x1180080e08e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4549"             ,	   0x1180080e08e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4550"             ,	   0x1180080e08e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4551"             ,	   0x1180080e08e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4552"             ,	   0x1180080e08e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4553"             ,	   0x1180080e08e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4554"             ,	   0x1180080e08e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4555"             ,	   0x1180080e08e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4556"             ,	   0x1180080e08e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4557"             ,	   0x1180080e08e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4558"             ,	   0x1180080e08e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4559"             ,	   0x1180080e08e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4560"             ,	   0x1180080e08e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4561"             ,	   0x1180080e08e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4562"             ,	   0x1180080e08e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4563"             ,	   0x1180080e08e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4564"             ,	   0x1180080e08ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4565"             ,	   0x1180080e08ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4566"             ,	   0x1180080e08eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4567"             ,	   0x1180080e08eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4568"             ,	   0x1180080e08ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4569"             ,	   0x1180080e08ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4570"             ,	   0x1180080e08ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4571"             ,	   0x1180080e08ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4572"             ,	   0x1180080e08ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4573"             ,	   0x1180080e08ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4574"             ,	   0x1180080e08ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4575"             ,	   0x1180080e08ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4576"             ,	   0x1180080e08f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4577"             ,	   0x1180080e08f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4578"             ,	   0x1180080e08f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4579"             ,	   0x1180080e08f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4580"             ,	   0x1180080e08f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4581"             ,	   0x1180080e08f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4582"             ,	   0x1180080e08f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4583"             ,	   0x1180080e08f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4584"             ,	   0x1180080e08f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4585"             ,	   0x1180080e08f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4586"             ,	   0x1180080e08f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4587"             ,	   0x1180080e08f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4588"             ,	   0x1180080e08f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4589"             ,	   0x1180080e08f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4590"             ,	   0x1180080e08f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4591"             ,	   0x1180080e08f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4592"             ,	   0x1180080e08f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4593"             ,	   0x1180080e08f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4594"             ,	   0x1180080e08f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4595"             ,	   0x1180080e08f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4596"             ,	   0x1180080e08fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4597"             ,	   0x1180080e08fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4598"             ,	   0x1180080e08fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4599"             ,	   0x1180080e08fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4600"             ,	   0x1180080e08fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4601"             ,	   0x1180080e08fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4602"             ,	   0x1180080e08fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4603"             ,	   0x1180080e08fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4604"             ,	   0x1180080e08fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4605"             ,	   0x1180080e08fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4606"             ,	   0x1180080e08ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4607"             ,	   0x1180080e08ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4608"             ,	   0x1180080e09000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4609"             ,	   0x1180080e09008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4610"             ,	   0x1180080e09010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4611"             ,	   0x1180080e09018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4612"             ,	   0x1180080e09020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4613"             ,	   0x1180080e09028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4614"             ,	   0x1180080e09030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4615"             ,	   0x1180080e09038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4616"             ,	   0x1180080e09040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4617"             ,	   0x1180080e09048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4618"             ,	   0x1180080e09050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4619"             ,	   0x1180080e09058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4620"             ,	   0x1180080e09060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4621"             ,	   0x1180080e09068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4622"             ,	   0x1180080e09070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4623"             ,	   0x1180080e09078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4624"             ,	   0x1180080e09080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4625"             ,	   0x1180080e09088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4626"             ,	   0x1180080e09090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4627"             ,	   0x1180080e09098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4628"             ,	   0x1180080e090a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4629"             ,	   0x1180080e090a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4630"             ,	   0x1180080e090b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4631"             ,	   0x1180080e090b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4632"             ,	   0x1180080e090c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4633"             ,	   0x1180080e090c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4634"             ,	   0x1180080e090d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4635"             ,	   0x1180080e090d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4636"             ,	   0x1180080e090e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4637"             ,	   0x1180080e090e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4638"             ,	   0x1180080e090f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4639"             ,	   0x1180080e090f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4640"             ,	   0x1180080e09100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4641"             ,	   0x1180080e09108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4642"             ,	   0x1180080e09110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4643"             ,	   0x1180080e09118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4644"             ,	   0x1180080e09120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4645"             ,	   0x1180080e09128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4646"             ,	   0x1180080e09130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4647"             ,	   0x1180080e09138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4648"             ,	   0x1180080e09140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4649"             ,	   0x1180080e09148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4650"             ,	   0x1180080e09150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4651"             ,	   0x1180080e09158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4652"             ,	   0x1180080e09160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4653"             ,	   0x1180080e09168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4654"             ,	   0x1180080e09170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4655"             ,	   0x1180080e09178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4656"             ,	   0x1180080e09180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4657"             ,	   0x1180080e09188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4658"             ,	   0x1180080e09190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4659"             ,	   0x1180080e09198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4660"             ,	   0x1180080e091a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4661"             ,	   0x1180080e091a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4662"             ,	   0x1180080e091b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4663"             ,	   0x1180080e091b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4664"             ,	   0x1180080e091c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4665"             ,	   0x1180080e091c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4666"             ,	   0x1180080e091d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4667"             ,	   0x1180080e091d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4668"             ,	   0x1180080e091e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4669"             ,	   0x1180080e091e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4670"             ,	   0x1180080e091f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4671"             ,	   0x1180080e091f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4672"             ,	   0x1180080e09200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4673"             ,	   0x1180080e09208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4674"             ,	   0x1180080e09210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4675"             ,	   0x1180080e09218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4676"             ,	   0x1180080e09220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4677"             ,	   0x1180080e09228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4678"             ,	   0x1180080e09230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4679"             ,	   0x1180080e09238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4680"             ,	   0x1180080e09240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4681"             ,	   0x1180080e09248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4682"             ,	   0x1180080e09250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4683"             ,	   0x1180080e09258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4684"             ,	   0x1180080e09260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4685"             ,	   0x1180080e09268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4686"             ,	   0x1180080e09270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4687"             ,	   0x1180080e09278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4688"             ,	   0x1180080e09280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4689"             ,	   0x1180080e09288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4690"             ,	   0x1180080e09290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4691"             ,	   0x1180080e09298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4692"             ,	   0x1180080e092a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4693"             ,	   0x1180080e092a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4694"             ,	   0x1180080e092b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4695"             ,	   0x1180080e092b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4696"             ,	   0x1180080e092c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4697"             ,	   0x1180080e092c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4698"             ,	   0x1180080e092d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4699"             ,	   0x1180080e092d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4700"             ,	   0x1180080e092e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4701"             ,	   0x1180080e092e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4702"             ,	   0x1180080e092f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4703"             ,	   0x1180080e092f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4704"             ,	   0x1180080e09300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4705"             ,	   0x1180080e09308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4706"             ,	   0x1180080e09310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4707"             ,	   0x1180080e09318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4708"             ,	   0x1180080e09320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4709"             ,	   0x1180080e09328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4710"             ,	   0x1180080e09330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4711"             ,	   0x1180080e09338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4712"             ,	   0x1180080e09340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4713"             ,	   0x1180080e09348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4714"             ,	   0x1180080e09350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4715"             ,	   0x1180080e09358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4716"             ,	   0x1180080e09360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4717"             ,	   0x1180080e09368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4718"             ,	   0x1180080e09370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4719"             ,	   0x1180080e09378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4720"             ,	   0x1180080e09380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4721"             ,	   0x1180080e09388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4722"             ,	   0x1180080e09390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4723"             ,	   0x1180080e09398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4724"             ,	   0x1180080e093a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4725"             ,	   0x1180080e093a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4726"             ,	   0x1180080e093b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4727"             ,	   0x1180080e093b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4728"             ,	   0x1180080e093c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4729"             ,	   0x1180080e093c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4730"             ,	   0x1180080e093d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4731"             ,	   0x1180080e093d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4732"             ,	   0x1180080e093e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4733"             ,	   0x1180080e093e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4734"             ,	   0x1180080e093f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4735"             ,	   0x1180080e093f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4736"             ,	   0x1180080e09400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4737"             ,	   0x1180080e09408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4738"             ,	   0x1180080e09410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4739"             ,	   0x1180080e09418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4740"             ,	   0x1180080e09420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4741"             ,	   0x1180080e09428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4742"             ,	   0x1180080e09430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4743"             ,	   0x1180080e09438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4744"             ,	   0x1180080e09440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4745"             ,	   0x1180080e09448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4746"             ,	   0x1180080e09450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4747"             ,	   0x1180080e09458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4748"             ,	   0x1180080e09460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4749"             ,	   0x1180080e09468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4750"             ,	   0x1180080e09470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4751"             ,	   0x1180080e09478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4752"             ,	   0x1180080e09480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4753"             ,	   0x1180080e09488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4754"             ,	   0x1180080e09490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4755"             ,	   0x1180080e09498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4756"             ,	   0x1180080e094a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4757"             ,	   0x1180080e094a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4758"             ,	   0x1180080e094b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4759"             ,	   0x1180080e094b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4760"             ,	   0x1180080e094c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4761"             ,	   0x1180080e094c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4762"             ,	   0x1180080e094d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4763"             ,	   0x1180080e094d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4764"             ,	   0x1180080e094e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4765"             ,	   0x1180080e094e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4766"             ,	   0x1180080e094f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4767"             ,	   0x1180080e094f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4768"             ,	   0x1180080e09500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4769"             ,	   0x1180080e09508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4770"             ,	   0x1180080e09510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4771"             ,	   0x1180080e09518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4772"             ,	   0x1180080e09520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4773"             ,	   0x1180080e09528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4774"             ,	   0x1180080e09530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4775"             ,	   0x1180080e09538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4776"             ,	   0x1180080e09540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4777"             ,	   0x1180080e09548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4778"             ,	   0x1180080e09550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4779"             ,	   0x1180080e09558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4780"             ,	   0x1180080e09560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4781"             ,	   0x1180080e09568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4782"             ,	   0x1180080e09570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4783"             ,	   0x1180080e09578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4784"             ,	   0x1180080e09580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4785"             ,	   0x1180080e09588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4786"             ,	   0x1180080e09590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4787"             ,	   0x1180080e09598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4788"             ,	   0x1180080e095a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4789"             ,	   0x1180080e095a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4790"             ,	   0x1180080e095b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4791"             ,	   0x1180080e095b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4792"             ,	   0x1180080e095c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4793"             ,	   0x1180080e095c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4794"             ,	   0x1180080e095d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4795"             ,	   0x1180080e095d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4796"             ,	   0x1180080e095e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4797"             ,	   0x1180080e095e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4798"             ,	   0x1180080e095f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4799"             ,	   0x1180080e095f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4800"             ,	   0x1180080e09600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4801"             ,	   0x1180080e09608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4802"             ,	   0x1180080e09610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4803"             ,	   0x1180080e09618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4804"             ,	   0x1180080e09620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4805"             ,	   0x1180080e09628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4806"             ,	   0x1180080e09630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4807"             ,	   0x1180080e09638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4808"             ,	   0x1180080e09640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4809"             ,	   0x1180080e09648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4810"             ,	   0x1180080e09650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4811"             ,	   0x1180080e09658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4812"             ,	   0x1180080e09660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4813"             ,	   0x1180080e09668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4814"             ,	   0x1180080e09670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4815"             ,	   0x1180080e09678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4816"             ,	   0x1180080e09680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4817"             ,	   0x1180080e09688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4818"             ,	   0x1180080e09690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4819"             ,	   0x1180080e09698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4820"             ,	   0x1180080e096a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4821"             ,	   0x1180080e096a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4822"             ,	   0x1180080e096b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4823"             ,	   0x1180080e096b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4824"             ,	   0x1180080e096c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4825"             ,	   0x1180080e096c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4826"             ,	   0x1180080e096d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4827"             ,	   0x1180080e096d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4828"             ,	   0x1180080e096e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4829"             ,	   0x1180080e096e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4830"             ,	   0x1180080e096f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4831"             ,	   0x1180080e096f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4832"             ,	   0x1180080e09700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4833"             ,	   0x1180080e09708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4834"             ,	   0x1180080e09710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4835"             ,	   0x1180080e09718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4836"             ,	   0x1180080e09720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4837"             ,	   0x1180080e09728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4838"             ,	   0x1180080e09730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4839"             ,	   0x1180080e09738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4840"             ,	   0x1180080e09740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4841"             ,	   0x1180080e09748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4842"             ,	   0x1180080e09750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4843"             ,	   0x1180080e09758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4844"             ,	   0x1180080e09760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4845"             ,	   0x1180080e09768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4846"             ,	   0x1180080e09770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4847"             ,	   0x1180080e09778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4848"             ,	   0x1180080e09780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4849"             ,	   0x1180080e09788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4850"             ,	   0x1180080e09790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4851"             ,	   0x1180080e09798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4852"             ,	   0x1180080e097a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4853"             ,	   0x1180080e097a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4854"             ,	   0x1180080e097b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4855"             ,	   0x1180080e097b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4856"             ,	   0x1180080e097c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4857"             ,	   0x1180080e097c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4858"             ,	   0x1180080e097d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4859"             ,	   0x1180080e097d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4860"             ,	   0x1180080e097e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4861"             ,	   0x1180080e097e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4862"             ,	   0x1180080e097f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4863"             ,	   0x1180080e097f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4864"             ,	   0x1180080e09800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4865"             ,	   0x1180080e09808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4866"             ,	   0x1180080e09810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4867"             ,	   0x1180080e09818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4868"             ,	   0x1180080e09820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4869"             ,	   0x1180080e09828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4870"             ,	   0x1180080e09830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4871"             ,	   0x1180080e09838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4872"             ,	   0x1180080e09840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4873"             ,	   0x1180080e09848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4874"             ,	   0x1180080e09850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4875"             ,	   0x1180080e09858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4876"             ,	   0x1180080e09860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4877"             ,	   0x1180080e09868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4878"             ,	   0x1180080e09870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4879"             ,	   0x1180080e09878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4880"             ,	   0x1180080e09880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4881"             ,	   0x1180080e09888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4882"             ,	   0x1180080e09890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4883"             ,	   0x1180080e09898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4884"             ,	   0x1180080e098a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4885"             ,	   0x1180080e098a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4886"             ,	   0x1180080e098b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4887"             ,	   0x1180080e098b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4888"             ,	   0x1180080e098c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4889"             ,	   0x1180080e098c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4890"             ,	   0x1180080e098d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4891"             ,	   0x1180080e098d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4892"             ,	   0x1180080e098e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4893"             ,	   0x1180080e098e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4894"             ,	   0x1180080e098f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4895"             ,	   0x1180080e098f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4896"             ,	   0x1180080e09900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4897"             ,	   0x1180080e09908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4898"             ,	   0x1180080e09910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4899"             ,	   0x1180080e09918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4900"             ,	   0x1180080e09920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4901"             ,	   0x1180080e09928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4902"             ,	   0x1180080e09930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4903"             ,	   0x1180080e09938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4904"             ,	   0x1180080e09940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4905"             ,	   0x1180080e09948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4906"             ,	   0x1180080e09950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4907"             ,	   0x1180080e09958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4908"             ,	   0x1180080e09960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4909"             ,	   0x1180080e09968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4910"             ,	   0x1180080e09970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4911"             ,	   0x1180080e09978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4912"             ,	   0x1180080e09980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4913"             ,	   0x1180080e09988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4914"             ,	   0x1180080e09990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4915"             ,	   0x1180080e09998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4916"             ,	   0x1180080e099a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4917"             ,	   0x1180080e099a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4918"             ,	   0x1180080e099b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4919"             ,	   0x1180080e099b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4920"             ,	   0x1180080e099c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4921"             ,	   0x1180080e099c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4922"             ,	   0x1180080e099d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4923"             ,	   0x1180080e099d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4924"             ,	   0x1180080e099e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4925"             ,	   0x1180080e099e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4926"             ,	   0x1180080e099f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4927"             ,	   0x1180080e099f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4928"             ,	   0x1180080e09a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4929"             ,	   0x1180080e09a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4930"             ,	   0x1180080e09a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4931"             ,	   0x1180080e09a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4932"             ,	   0x1180080e09a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4933"             ,	   0x1180080e09a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4934"             ,	   0x1180080e09a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4935"             ,	   0x1180080e09a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4936"             ,	   0x1180080e09a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4937"             ,	   0x1180080e09a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4938"             ,	   0x1180080e09a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4939"             ,	   0x1180080e09a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4940"             ,	   0x1180080e09a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4941"             ,	   0x1180080e09a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4942"             ,	   0x1180080e09a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4943"             ,	   0x1180080e09a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4944"             ,	   0x1180080e09a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4945"             ,	   0x1180080e09a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4946"             ,	   0x1180080e09a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4947"             ,	   0x1180080e09a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4948"             ,	   0x1180080e09aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4949"             ,	   0x1180080e09aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4950"             ,	   0x1180080e09ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4951"             ,	   0x1180080e09ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4952"             ,	   0x1180080e09ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4953"             ,	   0x1180080e09ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4954"             ,	   0x1180080e09ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4955"             ,	   0x1180080e09ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4956"             ,	   0x1180080e09ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4957"             ,	   0x1180080e09ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4958"             ,	   0x1180080e09af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4959"             ,	   0x1180080e09af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4960"             ,	   0x1180080e09b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4961"             ,	   0x1180080e09b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4962"             ,	   0x1180080e09b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4963"             ,	   0x1180080e09b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4964"             ,	   0x1180080e09b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4965"             ,	   0x1180080e09b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4966"             ,	   0x1180080e09b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4967"             ,	   0x1180080e09b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4968"             ,	   0x1180080e09b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4969"             ,	   0x1180080e09b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4970"             ,	   0x1180080e09b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4971"             ,	   0x1180080e09b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4972"             ,	   0x1180080e09b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4973"             ,	   0x1180080e09b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4974"             ,	   0x1180080e09b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4975"             ,	   0x1180080e09b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4976"             ,	   0x1180080e09b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4977"             ,	   0x1180080e09b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4978"             ,	   0x1180080e09b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4979"             ,	   0x1180080e09b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4980"             ,	   0x1180080e09ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4981"             ,	   0x1180080e09ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4982"             ,	   0x1180080e09bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4983"             ,	   0x1180080e09bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4984"             ,	   0x1180080e09bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4985"             ,	   0x1180080e09bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4986"             ,	   0x1180080e09bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4987"             ,	   0x1180080e09bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4988"             ,	   0x1180080e09be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4989"             ,	   0x1180080e09be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4990"             ,	   0x1180080e09bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4991"             ,	   0x1180080e09bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4992"             ,	   0x1180080e09c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4993"             ,	   0x1180080e09c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4994"             ,	   0x1180080e09c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4995"             ,	   0x1180080e09c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4996"             ,	   0x1180080e09c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4997"             ,	   0x1180080e09c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4998"             ,	   0x1180080e09c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP4999"             ,	   0x1180080e09c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5000"             ,	   0x1180080e09c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5001"             ,	   0x1180080e09c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5002"             ,	   0x1180080e09c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5003"             ,	   0x1180080e09c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5004"             ,	   0x1180080e09c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5005"             ,	   0x1180080e09c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5006"             ,	   0x1180080e09c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5007"             ,	   0x1180080e09c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5008"             ,	   0x1180080e09c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5009"             ,	   0x1180080e09c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5010"             ,	   0x1180080e09c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5011"             ,	   0x1180080e09c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5012"             ,	   0x1180080e09ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5013"             ,	   0x1180080e09ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5014"             ,	   0x1180080e09cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5015"             ,	   0x1180080e09cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5016"             ,	   0x1180080e09cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5017"             ,	   0x1180080e09cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5018"             ,	   0x1180080e09cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5019"             ,	   0x1180080e09cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5020"             ,	   0x1180080e09ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5021"             ,	   0x1180080e09ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5022"             ,	   0x1180080e09cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5023"             ,	   0x1180080e09cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5024"             ,	   0x1180080e09d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5025"             ,	   0x1180080e09d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5026"             ,	   0x1180080e09d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5027"             ,	   0x1180080e09d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5028"             ,	   0x1180080e09d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5029"             ,	   0x1180080e09d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5030"             ,	   0x1180080e09d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5031"             ,	   0x1180080e09d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5032"             ,	   0x1180080e09d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5033"             ,	   0x1180080e09d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5034"             ,	   0x1180080e09d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5035"             ,	   0x1180080e09d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5036"             ,	   0x1180080e09d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5037"             ,	   0x1180080e09d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5038"             ,	   0x1180080e09d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5039"             ,	   0x1180080e09d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5040"             ,	   0x1180080e09d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5041"             ,	   0x1180080e09d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5042"             ,	   0x1180080e09d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5043"             ,	   0x1180080e09d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5044"             ,	   0x1180080e09da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5045"             ,	   0x1180080e09da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5046"             ,	   0x1180080e09db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5047"             ,	   0x1180080e09db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5048"             ,	   0x1180080e09dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5049"             ,	   0x1180080e09dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5050"             ,	   0x1180080e09dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5051"             ,	   0x1180080e09dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5052"             ,	   0x1180080e09de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5053"             ,	   0x1180080e09de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5054"             ,	   0x1180080e09df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5055"             ,	   0x1180080e09df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5056"             ,	   0x1180080e09e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5057"             ,	   0x1180080e09e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5058"             ,	   0x1180080e09e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5059"             ,	   0x1180080e09e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5060"             ,	   0x1180080e09e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5061"             ,	   0x1180080e09e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5062"             ,	   0x1180080e09e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5063"             ,	   0x1180080e09e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5064"             ,	   0x1180080e09e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5065"             ,	   0x1180080e09e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5066"             ,	   0x1180080e09e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5067"             ,	   0x1180080e09e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5068"             ,	   0x1180080e09e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5069"             ,	   0x1180080e09e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5070"             ,	   0x1180080e09e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5071"             ,	   0x1180080e09e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5072"             ,	   0x1180080e09e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5073"             ,	   0x1180080e09e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5074"             ,	   0x1180080e09e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5075"             ,	   0x1180080e09e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5076"             ,	   0x1180080e09ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5077"             ,	   0x1180080e09ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5078"             ,	   0x1180080e09eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5079"             ,	   0x1180080e09eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5080"             ,	   0x1180080e09ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5081"             ,	   0x1180080e09ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5082"             ,	   0x1180080e09ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5083"             ,	   0x1180080e09ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5084"             ,	   0x1180080e09ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5085"             ,	   0x1180080e09ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5086"             ,	   0x1180080e09ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5087"             ,	   0x1180080e09ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5088"             ,	   0x1180080e09f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5089"             ,	   0x1180080e09f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5090"             ,	   0x1180080e09f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5091"             ,	   0x1180080e09f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5092"             ,	   0x1180080e09f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5093"             ,	   0x1180080e09f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5094"             ,	   0x1180080e09f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5095"             ,	   0x1180080e09f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5096"             ,	   0x1180080e09f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5097"             ,	   0x1180080e09f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5098"             ,	   0x1180080e09f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5099"             ,	   0x1180080e09f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5100"             ,	   0x1180080e09f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5101"             ,	   0x1180080e09f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5102"             ,	   0x1180080e09f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5103"             ,	   0x1180080e09f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5104"             ,	   0x1180080e09f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5105"             ,	   0x1180080e09f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5106"             ,	   0x1180080e09f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5107"             ,	   0x1180080e09f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5108"             ,	   0x1180080e09fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5109"             ,	   0x1180080e09fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5110"             ,	   0x1180080e09fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5111"             ,	   0x1180080e09fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5112"             ,	   0x1180080e09fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5113"             ,	   0x1180080e09fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5114"             ,	   0x1180080e09fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5115"             ,	   0x1180080e09fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5116"             ,	   0x1180080e09fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5117"             ,	   0x1180080e09fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5118"             ,	   0x1180080e09ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5119"             ,	   0x1180080e09ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5120"             ,	   0x1180080e0a000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5121"             ,	   0x1180080e0a008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5122"             ,	   0x1180080e0a010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5123"             ,	   0x1180080e0a018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5124"             ,	   0x1180080e0a020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5125"             ,	   0x1180080e0a028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5126"             ,	   0x1180080e0a030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5127"             ,	   0x1180080e0a038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5128"             ,	   0x1180080e0a040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5129"             ,	   0x1180080e0a048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5130"             ,	   0x1180080e0a050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5131"             ,	   0x1180080e0a058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5132"             ,	   0x1180080e0a060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5133"             ,	   0x1180080e0a068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5134"             ,	   0x1180080e0a070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5135"             ,	   0x1180080e0a078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5136"             ,	   0x1180080e0a080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5137"             ,	   0x1180080e0a088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5138"             ,	   0x1180080e0a090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5139"             ,	   0x1180080e0a098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5140"             ,	   0x1180080e0a0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5141"             ,	   0x1180080e0a0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5142"             ,	   0x1180080e0a0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5143"             ,	   0x1180080e0a0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5144"             ,	   0x1180080e0a0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5145"             ,	   0x1180080e0a0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5146"             ,	   0x1180080e0a0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5147"             ,	   0x1180080e0a0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5148"             ,	   0x1180080e0a0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5149"             ,	   0x1180080e0a0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5150"             ,	   0x1180080e0a0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5151"             ,	   0x1180080e0a0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5152"             ,	   0x1180080e0a100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5153"             ,	   0x1180080e0a108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5154"             ,	   0x1180080e0a110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5155"             ,	   0x1180080e0a118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5156"             ,	   0x1180080e0a120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5157"             ,	   0x1180080e0a128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5158"             ,	   0x1180080e0a130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5159"             ,	   0x1180080e0a138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5160"             ,	   0x1180080e0a140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5161"             ,	   0x1180080e0a148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5162"             ,	   0x1180080e0a150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5163"             ,	   0x1180080e0a158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5164"             ,	   0x1180080e0a160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5165"             ,	   0x1180080e0a168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5166"             ,	   0x1180080e0a170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5167"             ,	   0x1180080e0a178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5168"             ,	   0x1180080e0a180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5169"             ,	   0x1180080e0a188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5170"             ,	   0x1180080e0a190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5171"             ,	   0x1180080e0a198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5172"             ,	   0x1180080e0a1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5173"             ,	   0x1180080e0a1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5174"             ,	   0x1180080e0a1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5175"             ,	   0x1180080e0a1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5176"             ,	   0x1180080e0a1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5177"             ,	   0x1180080e0a1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5178"             ,	   0x1180080e0a1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5179"             ,	   0x1180080e0a1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5180"             ,	   0x1180080e0a1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5181"             ,	   0x1180080e0a1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5182"             ,	   0x1180080e0a1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5183"             ,	   0x1180080e0a1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5184"             ,	   0x1180080e0a200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5185"             ,	   0x1180080e0a208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5186"             ,	   0x1180080e0a210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5187"             ,	   0x1180080e0a218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5188"             ,	   0x1180080e0a220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5189"             ,	   0x1180080e0a228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5190"             ,	   0x1180080e0a230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5191"             ,	   0x1180080e0a238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5192"             ,	   0x1180080e0a240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5193"             ,	   0x1180080e0a248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5194"             ,	   0x1180080e0a250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5195"             ,	   0x1180080e0a258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5196"             ,	   0x1180080e0a260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5197"             ,	   0x1180080e0a268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5198"             ,	   0x1180080e0a270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5199"             ,	   0x1180080e0a278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5200"             ,	   0x1180080e0a280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5201"             ,	   0x1180080e0a288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5202"             ,	   0x1180080e0a290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5203"             ,	   0x1180080e0a298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5204"             ,	   0x1180080e0a2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5205"             ,	   0x1180080e0a2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5206"             ,	   0x1180080e0a2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5207"             ,	   0x1180080e0a2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5208"             ,	   0x1180080e0a2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5209"             ,	   0x1180080e0a2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5210"             ,	   0x1180080e0a2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5211"             ,	   0x1180080e0a2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5212"             ,	   0x1180080e0a2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5213"             ,	   0x1180080e0a2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5214"             ,	   0x1180080e0a2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5215"             ,	   0x1180080e0a2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5216"             ,	   0x1180080e0a300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5217"             ,	   0x1180080e0a308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5218"             ,	   0x1180080e0a310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5219"             ,	   0x1180080e0a318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5220"             ,	   0x1180080e0a320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5221"             ,	   0x1180080e0a328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5222"             ,	   0x1180080e0a330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5223"             ,	   0x1180080e0a338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5224"             ,	   0x1180080e0a340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5225"             ,	   0x1180080e0a348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5226"             ,	   0x1180080e0a350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5227"             ,	   0x1180080e0a358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5228"             ,	   0x1180080e0a360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5229"             ,	   0x1180080e0a368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5230"             ,	   0x1180080e0a370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5231"             ,	   0x1180080e0a378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5232"             ,	   0x1180080e0a380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5233"             ,	   0x1180080e0a388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5234"             ,	   0x1180080e0a390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5235"             ,	   0x1180080e0a398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5236"             ,	   0x1180080e0a3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5237"             ,	   0x1180080e0a3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5238"             ,	   0x1180080e0a3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5239"             ,	   0x1180080e0a3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5240"             ,	   0x1180080e0a3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5241"             ,	   0x1180080e0a3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5242"             ,	   0x1180080e0a3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5243"             ,	   0x1180080e0a3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5244"             ,	   0x1180080e0a3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5245"             ,	   0x1180080e0a3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5246"             ,	   0x1180080e0a3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5247"             ,	   0x1180080e0a3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5248"             ,	   0x1180080e0a400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5249"             ,	   0x1180080e0a408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5250"             ,	   0x1180080e0a410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5251"             ,	   0x1180080e0a418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5252"             ,	   0x1180080e0a420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5253"             ,	   0x1180080e0a428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5254"             ,	   0x1180080e0a430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5255"             ,	   0x1180080e0a438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5256"             ,	   0x1180080e0a440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5257"             ,	   0x1180080e0a448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5258"             ,	   0x1180080e0a450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5259"             ,	   0x1180080e0a458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5260"             ,	   0x1180080e0a460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5261"             ,	   0x1180080e0a468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5262"             ,	   0x1180080e0a470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5263"             ,	   0x1180080e0a478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5264"             ,	   0x1180080e0a480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5265"             ,	   0x1180080e0a488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5266"             ,	   0x1180080e0a490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5267"             ,	   0x1180080e0a498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5268"             ,	   0x1180080e0a4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5269"             ,	   0x1180080e0a4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5270"             ,	   0x1180080e0a4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5271"             ,	   0x1180080e0a4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5272"             ,	   0x1180080e0a4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5273"             ,	   0x1180080e0a4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5274"             ,	   0x1180080e0a4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5275"             ,	   0x1180080e0a4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5276"             ,	   0x1180080e0a4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5277"             ,	   0x1180080e0a4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5278"             ,	   0x1180080e0a4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5279"             ,	   0x1180080e0a4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5280"             ,	   0x1180080e0a500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5281"             ,	   0x1180080e0a508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5282"             ,	   0x1180080e0a510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5283"             ,	   0x1180080e0a518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5284"             ,	   0x1180080e0a520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5285"             ,	   0x1180080e0a528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5286"             ,	   0x1180080e0a530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5287"             ,	   0x1180080e0a538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5288"             ,	   0x1180080e0a540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5289"             ,	   0x1180080e0a548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5290"             ,	   0x1180080e0a550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5291"             ,	   0x1180080e0a558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5292"             ,	   0x1180080e0a560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5293"             ,	   0x1180080e0a568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5294"             ,	   0x1180080e0a570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5295"             ,	   0x1180080e0a578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5296"             ,	   0x1180080e0a580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5297"             ,	   0x1180080e0a588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5298"             ,	   0x1180080e0a590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5299"             ,	   0x1180080e0a598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5300"             ,	   0x1180080e0a5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5301"             ,	   0x1180080e0a5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5302"             ,	   0x1180080e0a5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5303"             ,	   0x1180080e0a5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5304"             ,	   0x1180080e0a5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5305"             ,	   0x1180080e0a5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5306"             ,	   0x1180080e0a5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5307"             ,	   0x1180080e0a5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5308"             ,	   0x1180080e0a5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5309"             ,	   0x1180080e0a5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5310"             ,	   0x1180080e0a5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5311"             ,	   0x1180080e0a5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5312"             ,	   0x1180080e0a600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5313"             ,	   0x1180080e0a608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5314"             ,	   0x1180080e0a610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5315"             ,	   0x1180080e0a618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5316"             ,	   0x1180080e0a620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5317"             ,	   0x1180080e0a628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5318"             ,	   0x1180080e0a630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5319"             ,	   0x1180080e0a638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5320"             ,	   0x1180080e0a640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5321"             ,	   0x1180080e0a648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5322"             ,	   0x1180080e0a650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5323"             ,	   0x1180080e0a658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5324"             ,	   0x1180080e0a660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5325"             ,	   0x1180080e0a668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5326"             ,	   0x1180080e0a670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5327"             ,	   0x1180080e0a678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5328"             ,	   0x1180080e0a680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5329"             ,	   0x1180080e0a688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5330"             ,	   0x1180080e0a690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5331"             ,	   0x1180080e0a698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5332"             ,	   0x1180080e0a6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5333"             ,	   0x1180080e0a6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5334"             ,	   0x1180080e0a6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5335"             ,	   0x1180080e0a6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5336"             ,	   0x1180080e0a6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5337"             ,	   0x1180080e0a6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5338"             ,	   0x1180080e0a6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5339"             ,	   0x1180080e0a6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5340"             ,	   0x1180080e0a6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5341"             ,	   0x1180080e0a6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5342"             ,	   0x1180080e0a6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5343"             ,	   0x1180080e0a6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5344"             ,	   0x1180080e0a700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5345"             ,	   0x1180080e0a708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5346"             ,	   0x1180080e0a710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5347"             ,	   0x1180080e0a718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5348"             ,	   0x1180080e0a720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5349"             ,	   0x1180080e0a728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5350"             ,	   0x1180080e0a730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5351"             ,	   0x1180080e0a738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5352"             ,	   0x1180080e0a740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5353"             ,	   0x1180080e0a748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5354"             ,	   0x1180080e0a750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5355"             ,	   0x1180080e0a758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5356"             ,	   0x1180080e0a760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5357"             ,	   0x1180080e0a768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5358"             ,	   0x1180080e0a770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5359"             ,	   0x1180080e0a778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5360"             ,	   0x1180080e0a780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5361"             ,	   0x1180080e0a788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5362"             ,	   0x1180080e0a790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5363"             ,	   0x1180080e0a798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5364"             ,	   0x1180080e0a7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5365"             ,	   0x1180080e0a7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5366"             ,	   0x1180080e0a7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5367"             ,	   0x1180080e0a7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5368"             ,	   0x1180080e0a7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5369"             ,	   0x1180080e0a7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5370"             ,	   0x1180080e0a7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5371"             ,	   0x1180080e0a7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5372"             ,	   0x1180080e0a7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5373"             ,	   0x1180080e0a7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5374"             ,	   0x1180080e0a7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5375"             ,	   0x1180080e0a7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5376"             ,	   0x1180080e0a800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5377"             ,	   0x1180080e0a808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5378"             ,	   0x1180080e0a810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5379"             ,	   0x1180080e0a818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5380"             ,	   0x1180080e0a820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5381"             ,	   0x1180080e0a828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5382"             ,	   0x1180080e0a830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5383"             ,	   0x1180080e0a838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5384"             ,	   0x1180080e0a840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5385"             ,	   0x1180080e0a848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5386"             ,	   0x1180080e0a850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5387"             ,	   0x1180080e0a858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5388"             ,	   0x1180080e0a860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5389"             ,	   0x1180080e0a868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5390"             ,	   0x1180080e0a870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5391"             ,	   0x1180080e0a878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5392"             ,	   0x1180080e0a880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5393"             ,	   0x1180080e0a888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5394"             ,	   0x1180080e0a890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5395"             ,	   0x1180080e0a898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5396"             ,	   0x1180080e0a8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5397"             ,	   0x1180080e0a8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5398"             ,	   0x1180080e0a8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5399"             ,	   0x1180080e0a8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5400"             ,	   0x1180080e0a8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5401"             ,	   0x1180080e0a8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5402"             ,	   0x1180080e0a8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5403"             ,	   0x1180080e0a8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5404"             ,	   0x1180080e0a8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5405"             ,	   0x1180080e0a8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5406"             ,	   0x1180080e0a8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5407"             ,	   0x1180080e0a8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5408"             ,	   0x1180080e0a900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5409"             ,	   0x1180080e0a908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5410"             ,	   0x1180080e0a910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5411"             ,	   0x1180080e0a918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5412"             ,	   0x1180080e0a920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5413"             ,	   0x1180080e0a928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5414"             ,	   0x1180080e0a930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5415"             ,	   0x1180080e0a938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5416"             ,	   0x1180080e0a940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5417"             ,	   0x1180080e0a948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5418"             ,	   0x1180080e0a950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5419"             ,	   0x1180080e0a958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5420"             ,	   0x1180080e0a960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5421"             ,	   0x1180080e0a968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5422"             ,	   0x1180080e0a970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5423"             ,	   0x1180080e0a978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5424"             ,	   0x1180080e0a980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5425"             ,	   0x1180080e0a988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5426"             ,	   0x1180080e0a990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5427"             ,	   0x1180080e0a998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5428"             ,	   0x1180080e0a9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5429"             ,	   0x1180080e0a9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5430"             ,	   0x1180080e0a9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5431"             ,	   0x1180080e0a9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5432"             ,	   0x1180080e0a9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5433"             ,	   0x1180080e0a9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5434"             ,	   0x1180080e0a9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5435"             ,	   0x1180080e0a9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5436"             ,	   0x1180080e0a9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5437"             ,	   0x1180080e0a9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5438"             ,	   0x1180080e0a9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5439"             ,	   0x1180080e0a9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5440"             ,	   0x1180080e0aa00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5441"             ,	   0x1180080e0aa08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5442"             ,	   0x1180080e0aa10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5443"             ,	   0x1180080e0aa18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5444"             ,	   0x1180080e0aa20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5445"             ,	   0x1180080e0aa28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5446"             ,	   0x1180080e0aa30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5447"             ,	   0x1180080e0aa38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5448"             ,	   0x1180080e0aa40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5449"             ,	   0x1180080e0aa48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5450"             ,	   0x1180080e0aa50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5451"             ,	   0x1180080e0aa58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5452"             ,	   0x1180080e0aa60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5453"             ,	   0x1180080e0aa68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5454"             ,	   0x1180080e0aa70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5455"             ,	   0x1180080e0aa78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5456"             ,	   0x1180080e0aa80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5457"             ,	   0x1180080e0aa88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5458"             ,	   0x1180080e0aa90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5459"             ,	   0x1180080e0aa98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5460"             ,	   0x1180080e0aaa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5461"             ,	   0x1180080e0aaa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5462"             ,	   0x1180080e0aab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5463"             ,	   0x1180080e0aab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5464"             ,	   0x1180080e0aac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5465"             ,	   0x1180080e0aac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5466"             ,	   0x1180080e0aad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5467"             ,	   0x1180080e0aad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5468"             ,	   0x1180080e0aae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5469"             ,	   0x1180080e0aae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5470"             ,	   0x1180080e0aaf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5471"             ,	   0x1180080e0aaf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5472"             ,	   0x1180080e0ab00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5473"             ,	   0x1180080e0ab08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5474"             ,	   0x1180080e0ab10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5475"             ,	   0x1180080e0ab18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5476"             ,	   0x1180080e0ab20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5477"             ,	   0x1180080e0ab28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5478"             ,	   0x1180080e0ab30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5479"             ,	   0x1180080e0ab38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5480"             ,	   0x1180080e0ab40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5481"             ,	   0x1180080e0ab48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5482"             ,	   0x1180080e0ab50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5483"             ,	   0x1180080e0ab58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5484"             ,	   0x1180080e0ab60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5485"             ,	   0x1180080e0ab68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5486"             ,	   0x1180080e0ab70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5487"             ,	   0x1180080e0ab78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5488"             ,	   0x1180080e0ab80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5489"             ,	   0x1180080e0ab88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5490"             ,	   0x1180080e0ab90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5491"             ,	   0x1180080e0ab98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5492"             ,	   0x1180080e0aba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5493"             ,	   0x1180080e0aba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5494"             ,	   0x1180080e0abb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5495"             ,	   0x1180080e0abb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5496"             ,	   0x1180080e0abc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5497"             ,	   0x1180080e0abc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5498"             ,	   0x1180080e0abd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5499"             ,	   0x1180080e0abd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5500"             ,	   0x1180080e0abe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5501"             ,	   0x1180080e0abe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5502"             ,	   0x1180080e0abf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5503"             ,	   0x1180080e0abf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5504"             ,	   0x1180080e0ac00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5505"             ,	   0x1180080e0ac08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5506"             ,	   0x1180080e0ac10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5507"             ,	   0x1180080e0ac18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5508"             ,	   0x1180080e0ac20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5509"             ,	   0x1180080e0ac28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5510"             ,	   0x1180080e0ac30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5511"             ,	   0x1180080e0ac38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5512"             ,	   0x1180080e0ac40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5513"             ,	   0x1180080e0ac48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5514"             ,	   0x1180080e0ac50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5515"             ,	   0x1180080e0ac58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5516"             ,	   0x1180080e0ac60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5517"             ,	   0x1180080e0ac68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5518"             ,	   0x1180080e0ac70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5519"             ,	   0x1180080e0ac78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5520"             ,	   0x1180080e0ac80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5521"             ,	   0x1180080e0ac88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5522"             ,	   0x1180080e0ac90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5523"             ,	   0x1180080e0ac98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5524"             ,	   0x1180080e0aca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5525"             ,	   0x1180080e0aca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5526"             ,	   0x1180080e0acb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5527"             ,	   0x1180080e0acb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5528"             ,	   0x1180080e0acc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5529"             ,	   0x1180080e0acc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5530"             ,	   0x1180080e0acd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5531"             ,	   0x1180080e0acd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5532"             ,	   0x1180080e0ace0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5533"             ,	   0x1180080e0ace8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5534"             ,	   0x1180080e0acf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5535"             ,	   0x1180080e0acf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5536"             ,	   0x1180080e0ad00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5537"             ,	   0x1180080e0ad08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5538"             ,	   0x1180080e0ad10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5539"             ,	   0x1180080e0ad18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5540"             ,	   0x1180080e0ad20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5541"             ,	   0x1180080e0ad28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5542"             ,	   0x1180080e0ad30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5543"             ,	   0x1180080e0ad38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5544"             ,	   0x1180080e0ad40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5545"             ,	   0x1180080e0ad48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5546"             ,	   0x1180080e0ad50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5547"             ,	   0x1180080e0ad58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5548"             ,	   0x1180080e0ad60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5549"             ,	   0x1180080e0ad68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5550"             ,	   0x1180080e0ad70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5551"             ,	   0x1180080e0ad78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5552"             ,	   0x1180080e0ad80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5553"             ,	   0x1180080e0ad88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5554"             ,	   0x1180080e0ad90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5555"             ,	   0x1180080e0ad98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5556"             ,	   0x1180080e0ada0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5557"             ,	   0x1180080e0ada8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5558"             ,	   0x1180080e0adb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5559"             ,	   0x1180080e0adb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5560"             ,	   0x1180080e0adc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5561"             ,	   0x1180080e0adc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5562"             ,	   0x1180080e0add0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5563"             ,	   0x1180080e0add8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5564"             ,	   0x1180080e0ade0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5565"             ,	   0x1180080e0ade8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5566"             ,	   0x1180080e0adf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5567"             ,	   0x1180080e0adf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5568"             ,	   0x1180080e0ae00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5569"             ,	   0x1180080e0ae08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5570"             ,	   0x1180080e0ae10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5571"             ,	   0x1180080e0ae18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5572"             ,	   0x1180080e0ae20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5573"             ,	   0x1180080e0ae28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5574"             ,	   0x1180080e0ae30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5575"             ,	   0x1180080e0ae38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5576"             ,	   0x1180080e0ae40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5577"             ,	   0x1180080e0ae48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5578"             ,	   0x1180080e0ae50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5579"             ,	   0x1180080e0ae58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5580"             ,	   0x1180080e0ae60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5581"             ,	   0x1180080e0ae68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5582"             ,	   0x1180080e0ae70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5583"             ,	   0x1180080e0ae78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5584"             ,	   0x1180080e0ae80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5585"             ,	   0x1180080e0ae88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5586"             ,	   0x1180080e0ae90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5587"             ,	   0x1180080e0ae98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5588"             ,	   0x1180080e0aea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5589"             ,	   0x1180080e0aea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5590"             ,	   0x1180080e0aeb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5591"             ,	   0x1180080e0aeb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5592"             ,	   0x1180080e0aec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5593"             ,	   0x1180080e0aec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5594"             ,	   0x1180080e0aed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5595"             ,	   0x1180080e0aed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5596"             ,	   0x1180080e0aee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5597"             ,	   0x1180080e0aee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5598"             ,	   0x1180080e0aef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5599"             ,	   0x1180080e0aef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5600"             ,	   0x1180080e0af00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5601"             ,	   0x1180080e0af08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5602"             ,	   0x1180080e0af10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5603"             ,	   0x1180080e0af18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5604"             ,	   0x1180080e0af20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5605"             ,	   0x1180080e0af28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5606"             ,	   0x1180080e0af30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5607"             ,	   0x1180080e0af38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5608"             ,	   0x1180080e0af40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5609"             ,	   0x1180080e0af48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5610"             ,	   0x1180080e0af50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5611"             ,	   0x1180080e0af58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5612"             ,	   0x1180080e0af60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5613"             ,	   0x1180080e0af68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5614"             ,	   0x1180080e0af70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5615"             ,	   0x1180080e0af78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5616"             ,	   0x1180080e0af80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5617"             ,	   0x1180080e0af88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5618"             ,	   0x1180080e0af90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5619"             ,	   0x1180080e0af98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5620"             ,	   0x1180080e0afa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5621"             ,	   0x1180080e0afa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5622"             ,	   0x1180080e0afb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5623"             ,	   0x1180080e0afb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5624"             ,	   0x1180080e0afc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5625"             ,	   0x1180080e0afc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5626"             ,	   0x1180080e0afd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5627"             ,	   0x1180080e0afd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5628"             ,	   0x1180080e0afe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5629"             ,	   0x1180080e0afe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5630"             ,	   0x1180080e0aff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5631"             ,	   0x1180080e0aff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5632"             ,	   0x1180080e0b000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5633"             ,	   0x1180080e0b008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5634"             ,	   0x1180080e0b010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5635"             ,	   0x1180080e0b018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5636"             ,	   0x1180080e0b020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5637"             ,	   0x1180080e0b028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5638"             ,	   0x1180080e0b030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5639"             ,	   0x1180080e0b038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5640"             ,	   0x1180080e0b040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5641"             ,	   0x1180080e0b048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5642"             ,	   0x1180080e0b050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5643"             ,	   0x1180080e0b058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5644"             ,	   0x1180080e0b060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5645"             ,	   0x1180080e0b068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5646"             ,	   0x1180080e0b070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5647"             ,	   0x1180080e0b078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5648"             ,	   0x1180080e0b080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5649"             ,	   0x1180080e0b088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5650"             ,	   0x1180080e0b090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5651"             ,	   0x1180080e0b098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5652"             ,	   0x1180080e0b0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5653"             ,	   0x1180080e0b0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5654"             ,	   0x1180080e0b0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5655"             ,	   0x1180080e0b0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5656"             ,	   0x1180080e0b0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5657"             ,	   0x1180080e0b0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5658"             ,	   0x1180080e0b0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5659"             ,	   0x1180080e0b0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5660"             ,	   0x1180080e0b0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5661"             ,	   0x1180080e0b0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5662"             ,	   0x1180080e0b0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5663"             ,	   0x1180080e0b0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5664"             ,	   0x1180080e0b100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5665"             ,	   0x1180080e0b108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5666"             ,	   0x1180080e0b110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5667"             ,	   0x1180080e0b118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5668"             ,	   0x1180080e0b120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5669"             ,	   0x1180080e0b128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5670"             ,	   0x1180080e0b130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5671"             ,	   0x1180080e0b138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5672"             ,	   0x1180080e0b140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5673"             ,	   0x1180080e0b148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5674"             ,	   0x1180080e0b150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5675"             ,	   0x1180080e0b158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5676"             ,	   0x1180080e0b160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5677"             ,	   0x1180080e0b168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5678"             ,	   0x1180080e0b170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5679"             ,	   0x1180080e0b178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5680"             ,	   0x1180080e0b180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5681"             ,	   0x1180080e0b188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5682"             ,	   0x1180080e0b190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5683"             ,	   0x1180080e0b198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5684"             ,	   0x1180080e0b1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5685"             ,	   0x1180080e0b1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5686"             ,	   0x1180080e0b1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5687"             ,	   0x1180080e0b1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5688"             ,	   0x1180080e0b1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5689"             ,	   0x1180080e0b1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5690"             ,	   0x1180080e0b1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5691"             ,	   0x1180080e0b1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5692"             ,	   0x1180080e0b1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5693"             ,	   0x1180080e0b1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5694"             ,	   0x1180080e0b1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5695"             ,	   0x1180080e0b1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5696"             ,	   0x1180080e0b200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5697"             ,	   0x1180080e0b208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5698"             ,	   0x1180080e0b210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5699"             ,	   0x1180080e0b218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5700"             ,	   0x1180080e0b220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5701"             ,	   0x1180080e0b228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5702"             ,	   0x1180080e0b230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5703"             ,	   0x1180080e0b238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5704"             ,	   0x1180080e0b240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5705"             ,	   0x1180080e0b248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5706"             ,	   0x1180080e0b250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5707"             ,	   0x1180080e0b258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5708"             ,	   0x1180080e0b260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5709"             ,	   0x1180080e0b268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5710"             ,	   0x1180080e0b270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5711"             ,	   0x1180080e0b278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5712"             ,	   0x1180080e0b280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5713"             ,	   0x1180080e0b288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5714"             ,	   0x1180080e0b290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5715"             ,	   0x1180080e0b298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5716"             ,	   0x1180080e0b2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5717"             ,	   0x1180080e0b2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5718"             ,	   0x1180080e0b2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5719"             ,	   0x1180080e0b2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5720"             ,	   0x1180080e0b2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5721"             ,	   0x1180080e0b2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5722"             ,	   0x1180080e0b2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5723"             ,	   0x1180080e0b2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5724"             ,	   0x1180080e0b2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5725"             ,	   0x1180080e0b2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5726"             ,	   0x1180080e0b2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5727"             ,	   0x1180080e0b2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5728"             ,	   0x1180080e0b300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5729"             ,	   0x1180080e0b308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5730"             ,	   0x1180080e0b310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5731"             ,	   0x1180080e0b318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5732"             ,	   0x1180080e0b320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5733"             ,	   0x1180080e0b328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5734"             ,	   0x1180080e0b330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5735"             ,	   0x1180080e0b338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5736"             ,	   0x1180080e0b340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5737"             ,	   0x1180080e0b348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5738"             ,	   0x1180080e0b350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5739"             ,	   0x1180080e0b358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5740"             ,	   0x1180080e0b360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5741"             ,	   0x1180080e0b368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5742"             ,	   0x1180080e0b370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5743"             ,	   0x1180080e0b378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5744"             ,	   0x1180080e0b380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5745"             ,	   0x1180080e0b388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5746"             ,	   0x1180080e0b390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5747"             ,	   0x1180080e0b398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5748"             ,	   0x1180080e0b3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5749"             ,	   0x1180080e0b3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5750"             ,	   0x1180080e0b3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5751"             ,	   0x1180080e0b3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5752"             ,	   0x1180080e0b3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5753"             ,	   0x1180080e0b3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5754"             ,	   0x1180080e0b3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5755"             ,	   0x1180080e0b3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5756"             ,	   0x1180080e0b3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5757"             ,	   0x1180080e0b3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5758"             ,	   0x1180080e0b3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5759"             ,	   0x1180080e0b3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5760"             ,	   0x1180080e0b400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5761"             ,	   0x1180080e0b408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5762"             ,	   0x1180080e0b410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5763"             ,	   0x1180080e0b418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5764"             ,	   0x1180080e0b420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5765"             ,	   0x1180080e0b428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5766"             ,	   0x1180080e0b430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5767"             ,	   0x1180080e0b438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5768"             ,	   0x1180080e0b440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5769"             ,	   0x1180080e0b448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5770"             ,	   0x1180080e0b450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5771"             ,	   0x1180080e0b458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5772"             ,	   0x1180080e0b460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5773"             ,	   0x1180080e0b468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5774"             ,	   0x1180080e0b470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5775"             ,	   0x1180080e0b478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5776"             ,	   0x1180080e0b480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5777"             ,	   0x1180080e0b488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5778"             ,	   0x1180080e0b490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5779"             ,	   0x1180080e0b498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5780"             ,	   0x1180080e0b4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5781"             ,	   0x1180080e0b4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5782"             ,	   0x1180080e0b4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5783"             ,	   0x1180080e0b4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5784"             ,	   0x1180080e0b4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5785"             ,	   0x1180080e0b4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5786"             ,	   0x1180080e0b4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5787"             ,	   0x1180080e0b4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5788"             ,	   0x1180080e0b4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5789"             ,	   0x1180080e0b4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5790"             ,	   0x1180080e0b4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5791"             ,	   0x1180080e0b4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5792"             ,	   0x1180080e0b500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5793"             ,	   0x1180080e0b508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5794"             ,	   0x1180080e0b510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5795"             ,	   0x1180080e0b518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5796"             ,	   0x1180080e0b520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5797"             ,	   0x1180080e0b528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5798"             ,	   0x1180080e0b530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5799"             ,	   0x1180080e0b538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5800"             ,	   0x1180080e0b540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5801"             ,	   0x1180080e0b548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5802"             ,	   0x1180080e0b550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5803"             ,	   0x1180080e0b558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5804"             ,	   0x1180080e0b560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5805"             ,	   0x1180080e0b568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5806"             ,	   0x1180080e0b570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5807"             ,	   0x1180080e0b578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5808"             ,	   0x1180080e0b580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5809"             ,	   0x1180080e0b588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5810"             ,	   0x1180080e0b590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5811"             ,	   0x1180080e0b598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5812"             ,	   0x1180080e0b5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5813"             ,	   0x1180080e0b5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5814"             ,	   0x1180080e0b5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5815"             ,	   0x1180080e0b5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5816"             ,	   0x1180080e0b5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5817"             ,	   0x1180080e0b5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5818"             ,	   0x1180080e0b5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5819"             ,	   0x1180080e0b5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5820"             ,	   0x1180080e0b5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5821"             ,	   0x1180080e0b5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5822"             ,	   0x1180080e0b5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5823"             ,	   0x1180080e0b5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5824"             ,	   0x1180080e0b600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5825"             ,	   0x1180080e0b608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5826"             ,	   0x1180080e0b610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5827"             ,	   0x1180080e0b618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5828"             ,	   0x1180080e0b620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5829"             ,	   0x1180080e0b628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5830"             ,	   0x1180080e0b630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5831"             ,	   0x1180080e0b638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5832"             ,	   0x1180080e0b640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5833"             ,	   0x1180080e0b648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5834"             ,	   0x1180080e0b650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5835"             ,	   0x1180080e0b658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5836"             ,	   0x1180080e0b660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5837"             ,	   0x1180080e0b668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5838"             ,	   0x1180080e0b670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5839"             ,	   0x1180080e0b678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5840"             ,	   0x1180080e0b680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5841"             ,	   0x1180080e0b688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5842"             ,	   0x1180080e0b690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5843"             ,	   0x1180080e0b698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5844"             ,	   0x1180080e0b6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5845"             ,	   0x1180080e0b6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5846"             ,	   0x1180080e0b6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5847"             ,	   0x1180080e0b6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5848"             ,	   0x1180080e0b6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5849"             ,	   0x1180080e0b6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5850"             ,	   0x1180080e0b6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5851"             ,	   0x1180080e0b6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5852"             ,	   0x1180080e0b6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5853"             ,	   0x1180080e0b6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5854"             ,	   0x1180080e0b6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5855"             ,	   0x1180080e0b6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5856"             ,	   0x1180080e0b700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5857"             ,	   0x1180080e0b708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5858"             ,	   0x1180080e0b710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5859"             ,	   0x1180080e0b718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5860"             ,	   0x1180080e0b720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5861"             ,	   0x1180080e0b728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5862"             ,	   0x1180080e0b730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5863"             ,	   0x1180080e0b738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5864"             ,	   0x1180080e0b740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5865"             ,	   0x1180080e0b748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5866"             ,	   0x1180080e0b750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5867"             ,	   0x1180080e0b758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5868"             ,	   0x1180080e0b760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5869"             ,	   0x1180080e0b768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5870"             ,	   0x1180080e0b770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5871"             ,	   0x1180080e0b778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5872"             ,	   0x1180080e0b780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5873"             ,	   0x1180080e0b788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5874"             ,	   0x1180080e0b790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5875"             ,	   0x1180080e0b798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5876"             ,	   0x1180080e0b7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5877"             ,	   0x1180080e0b7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5878"             ,	   0x1180080e0b7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5879"             ,	   0x1180080e0b7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5880"             ,	   0x1180080e0b7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5881"             ,	   0x1180080e0b7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5882"             ,	   0x1180080e0b7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5883"             ,	   0x1180080e0b7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5884"             ,	   0x1180080e0b7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5885"             ,	   0x1180080e0b7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5886"             ,	   0x1180080e0b7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5887"             ,	   0x1180080e0b7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5888"             ,	   0x1180080e0b800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5889"             ,	   0x1180080e0b808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5890"             ,	   0x1180080e0b810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5891"             ,	   0x1180080e0b818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5892"             ,	   0x1180080e0b820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5893"             ,	   0x1180080e0b828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5894"             ,	   0x1180080e0b830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5895"             ,	   0x1180080e0b838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5896"             ,	   0x1180080e0b840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5897"             ,	   0x1180080e0b848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5898"             ,	   0x1180080e0b850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5899"             ,	   0x1180080e0b858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5900"             ,	   0x1180080e0b860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5901"             ,	   0x1180080e0b868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5902"             ,	   0x1180080e0b870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5903"             ,	   0x1180080e0b878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5904"             ,	   0x1180080e0b880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5905"             ,	   0x1180080e0b888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5906"             ,	   0x1180080e0b890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5907"             ,	   0x1180080e0b898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5908"             ,	   0x1180080e0b8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5909"             ,	   0x1180080e0b8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5910"             ,	   0x1180080e0b8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5911"             ,	   0x1180080e0b8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5912"             ,	   0x1180080e0b8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5913"             ,	   0x1180080e0b8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5914"             ,	   0x1180080e0b8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5915"             ,	   0x1180080e0b8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5916"             ,	   0x1180080e0b8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5917"             ,	   0x1180080e0b8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5918"             ,	   0x1180080e0b8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5919"             ,	   0x1180080e0b8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5920"             ,	   0x1180080e0b900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5921"             ,	   0x1180080e0b908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5922"             ,	   0x1180080e0b910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5923"             ,	   0x1180080e0b918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5924"             ,	   0x1180080e0b920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5925"             ,	   0x1180080e0b928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5926"             ,	   0x1180080e0b930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5927"             ,	   0x1180080e0b938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5928"             ,	   0x1180080e0b940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5929"             ,	   0x1180080e0b948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5930"             ,	   0x1180080e0b950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5931"             ,	   0x1180080e0b958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5932"             ,	   0x1180080e0b960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5933"             ,	   0x1180080e0b968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5934"             ,	   0x1180080e0b970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5935"             ,	   0x1180080e0b978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5936"             ,	   0x1180080e0b980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5937"             ,	   0x1180080e0b988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5938"             ,	   0x1180080e0b990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5939"             ,	   0x1180080e0b998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5940"             ,	   0x1180080e0b9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5941"             ,	   0x1180080e0b9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5942"             ,	   0x1180080e0b9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5943"             ,	   0x1180080e0b9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5944"             ,	   0x1180080e0b9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5945"             ,	   0x1180080e0b9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5946"             ,	   0x1180080e0b9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5947"             ,	   0x1180080e0b9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5948"             ,	   0x1180080e0b9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5949"             ,	   0x1180080e0b9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5950"             ,	   0x1180080e0b9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5951"             ,	   0x1180080e0b9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5952"             ,	   0x1180080e0ba00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5953"             ,	   0x1180080e0ba08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5954"             ,	   0x1180080e0ba10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5955"             ,	   0x1180080e0ba18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5956"             ,	   0x1180080e0ba20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5957"             ,	   0x1180080e0ba28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5958"             ,	   0x1180080e0ba30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5959"             ,	   0x1180080e0ba38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5960"             ,	   0x1180080e0ba40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5961"             ,	   0x1180080e0ba48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5962"             ,	   0x1180080e0ba50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5963"             ,	   0x1180080e0ba58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5964"             ,	   0x1180080e0ba60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5965"             ,	   0x1180080e0ba68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5966"             ,	   0x1180080e0ba70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5967"             ,	   0x1180080e0ba78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5968"             ,	   0x1180080e0ba80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5969"             ,	   0x1180080e0ba88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5970"             ,	   0x1180080e0ba90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5971"             ,	   0x1180080e0ba98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5972"             ,	   0x1180080e0baa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5973"             ,	   0x1180080e0baa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5974"             ,	   0x1180080e0bab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5975"             ,	   0x1180080e0bab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5976"             ,	   0x1180080e0bac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5977"             ,	   0x1180080e0bac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5978"             ,	   0x1180080e0bad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5979"             ,	   0x1180080e0bad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5980"             ,	   0x1180080e0bae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5981"             ,	   0x1180080e0bae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5982"             ,	   0x1180080e0baf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5983"             ,	   0x1180080e0baf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5984"             ,	   0x1180080e0bb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5985"             ,	   0x1180080e0bb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5986"             ,	   0x1180080e0bb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5987"             ,	   0x1180080e0bb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5988"             ,	   0x1180080e0bb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5989"             ,	   0x1180080e0bb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5990"             ,	   0x1180080e0bb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5991"             ,	   0x1180080e0bb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5992"             ,	   0x1180080e0bb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5993"             ,	   0x1180080e0bb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5994"             ,	   0x1180080e0bb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5995"             ,	   0x1180080e0bb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5996"             ,	   0x1180080e0bb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5997"             ,	   0x1180080e0bb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5998"             ,	   0x1180080e0bb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP5999"             ,	   0x1180080e0bb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6000"             ,	   0x1180080e0bb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6001"             ,	   0x1180080e0bb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6002"             ,	   0x1180080e0bb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6003"             ,	   0x1180080e0bb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6004"             ,	   0x1180080e0bba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6005"             ,	   0x1180080e0bba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6006"             ,	   0x1180080e0bbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6007"             ,	   0x1180080e0bbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6008"             ,	   0x1180080e0bbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6009"             ,	   0x1180080e0bbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6010"             ,	   0x1180080e0bbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6011"             ,	   0x1180080e0bbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6012"             ,	   0x1180080e0bbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6013"             ,	   0x1180080e0bbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6014"             ,	   0x1180080e0bbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6015"             ,	   0x1180080e0bbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6016"             ,	   0x1180080e0bc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6017"             ,	   0x1180080e0bc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6018"             ,	   0x1180080e0bc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6019"             ,	   0x1180080e0bc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6020"             ,	   0x1180080e0bc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6021"             ,	   0x1180080e0bc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6022"             ,	   0x1180080e0bc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6023"             ,	   0x1180080e0bc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6024"             ,	   0x1180080e0bc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6025"             ,	   0x1180080e0bc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6026"             ,	   0x1180080e0bc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6027"             ,	   0x1180080e0bc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6028"             ,	   0x1180080e0bc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6029"             ,	   0x1180080e0bc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6030"             ,	   0x1180080e0bc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6031"             ,	   0x1180080e0bc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6032"             ,	   0x1180080e0bc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6033"             ,	   0x1180080e0bc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6034"             ,	   0x1180080e0bc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6035"             ,	   0x1180080e0bc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6036"             ,	   0x1180080e0bca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6037"             ,	   0x1180080e0bca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6038"             ,	   0x1180080e0bcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6039"             ,	   0x1180080e0bcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6040"             ,	   0x1180080e0bcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6041"             ,	   0x1180080e0bcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6042"             ,	   0x1180080e0bcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6043"             ,	   0x1180080e0bcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6044"             ,	   0x1180080e0bce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6045"             ,	   0x1180080e0bce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6046"             ,	   0x1180080e0bcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6047"             ,	   0x1180080e0bcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6048"             ,	   0x1180080e0bd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6049"             ,	   0x1180080e0bd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6050"             ,	   0x1180080e0bd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6051"             ,	   0x1180080e0bd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6052"             ,	   0x1180080e0bd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6053"             ,	   0x1180080e0bd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6054"             ,	   0x1180080e0bd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6055"             ,	   0x1180080e0bd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6056"             ,	   0x1180080e0bd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6057"             ,	   0x1180080e0bd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6058"             ,	   0x1180080e0bd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6059"             ,	   0x1180080e0bd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6060"             ,	   0x1180080e0bd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6061"             ,	   0x1180080e0bd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6062"             ,	   0x1180080e0bd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6063"             ,	   0x1180080e0bd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6064"             ,	   0x1180080e0bd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6065"             ,	   0x1180080e0bd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6066"             ,	   0x1180080e0bd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6067"             ,	   0x1180080e0bd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6068"             ,	   0x1180080e0bda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6069"             ,	   0x1180080e0bda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6070"             ,	   0x1180080e0bdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6071"             ,	   0x1180080e0bdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6072"             ,	   0x1180080e0bdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6073"             ,	   0x1180080e0bdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6074"             ,	   0x1180080e0bdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6075"             ,	   0x1180080e0bdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6076"             ,	   0x1180080e0bde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6077"             ,	   0x1180080e0bde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6078"             ,	   0x1180080e0bdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6079"             ,	   0x1180080e0bdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6080"             ,	   0x1180080e0be00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6081"             ,	   0x1180080e0be08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6082"             ,	   0x1180080e0be10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6083"             ,	   0x1180080e0be18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6084"             ,	   0x1180080e0be20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6085"             ,	   0x1180080e0be28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6086"             ,	   0x1180080e0be30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6087"             ,	   0x1180080e0be38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6088"             ,	   0x1180080e0be40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6089"             ,	   0x1180080e0be48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6090"             ,	   0x1180080e0be50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6091"             ,	   0x1180080e0be58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6092"             ,	   0x1180080e0be60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6093"             ,	   0x1180080e0be68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6094"             ,	   0x1180080e0be70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6095"             ,	   0x1180080e0be78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6096"             ,	   0x1180080e0be80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6097"             ,	   0x1180080e0be88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6098"             ,	   0x1180080e0be90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6099"             ,	   0x1180080e0be98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6100"             ,	   0x1180080e0bea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6101"             ,	   0x1180080e0bea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6102"             ,	   0x1180080e0beb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6103"             ,	   0x1180080e0beb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6104"             ,	   0x1180080e0bec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6105"             ,	   0x1180080e0bec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6106"             ,	   0x1180080e0bed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6107"             ,	   0x1180080e0bed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6108"             ,	   0x1180080e0bee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6109"             ,	   0x1180080e0bee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6110"             ,	   0x1180080e0bef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6111"             ,	   0x1180080e0bef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6112"             ,	   0x1180080e0bf00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6113"             ,	   0x1180080e0bf08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6114"             ,	   0x1180080e0bf10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6115"             ,	   0x1180080e0bf18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6116"             ,	   0x1180080e0bf20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6117"             ,	   0x1180080e0bf28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6118"             ,	   0x1180080e0bf30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6119"             ,	   0x1180080e0bf38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6120"             ,	   0x1180080e0bf40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6121"             ,	   0x1180080e0bf48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6122"             ,	   0x1180080e0bf50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6123"             ,	   0x1180080e0bf58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6124"             ,	   0x1180080e0bf60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6125"             ,	   0x1180080e0bf68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6126"             ,	   0x1180080e0bf70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6127"             ,	   0x1180080e0bf78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6128"             ,	   0x1180080e0bf80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6129"             ,	   0x1180080e0bf88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6130"             ,	   0x1180080e0bf90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6131"             ,	   0x1180080e0bf98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6132"             ,	   0x1180080e0bfa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6133"             ,	   0x1180080e0bfa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6134"             ,	   0x1180080e0bfb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6135"             ,	   0x1180080e0bfb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6136"             ,	   0x1180080e0bfc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6137"             ,	   0x1180080e0bfc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6138"             ,	   0x1180080e0bfd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6139"             ,	   0x1180080e0bfd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6140"             ,	   0x1180080e0bfe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6141"             ,	   0x1180080e0bfe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6142"             ,	   0x1180080e0bff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6143"             ,	   0x1180080e0bff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6144"             ,	   0x1180080e0c000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6145"             ,	   0x1180080e0c008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6146"             ,	   0x1180080e0c010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6147"             ,	   0x1180080e0c018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6148"             ,	   0x1180080e0c020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6149"             ,	   0x1180080e0c028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6150"             ,	   0x1180080e0c030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6151"             ,	   0x1180080e0c038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6152"             ,	   0x1180080e0c040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6153"             ,	   0x1180080e0c048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6154"             ,	   0x1180080e0c050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6155"             ,	   0x1180080e0c058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6156"             ,	   0x1180080e0c060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6157"             ,	   0x1180080e0c068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6158"             ,	   0x1180080e0c070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6159"             ,	   0x1180080e0c078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6160"             ,	   0x1180080e0c080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6161"             ,	   0x1180080e0c088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6162"             ,	   0x1180080e0c090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6163"             ,	   0x1180080e0c098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6164"             ,	   0x1180080e0c0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6165"             ,	   0x1180080e0c0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6166"             ,	   0x1180080e0c0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6167"             ,	   0x1180080e0c0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6168"             ,	   0x1180080e0c0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6169"             ,	   0x1180080e0c0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6170"             ,	   0x1180080e0c0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6171"             ,	   0x1180080e0c0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6172"             ,	   0x1180080e0c0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6173"             ,	   0x1180080e0c0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6174"             ,	   0x1180080e0c0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6175"             ,	   0x1180080e0c0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6176"             ,	   0x1180080e0c100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6177"             ,	   0x1180080e0c108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6178"             ,	   0x1180080e0c110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6179"             ,	   0x1180080e0c118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6180"             ,	   0x1180080e0c120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6181"             ,	   0x1180080e0c128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6182"             ,	   0x1180080e0c130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6183"             ,	   0x1180080e0c138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6184"             ,	   0x1180080e0c140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6185"             ,	   0x1180080e0c148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6186"             ,	   0x1180080e0c150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6187"             ,	   0x1180080e0c158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6188"             ,	   0x1180080e0c160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6189"             ,	   0x1180080e0c168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6190"             ,	   0x1180080e0c170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6191"             ,	   0x1180080e0c178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6192"             ,	   0x1180080e0c180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6193"             ,	   0x1180080e0c188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6194"             ,	   0x1180080e0c190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6195"             ,	   0x1180080e0c198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6196"             ,	   0x1180080e0c1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6197"             ,	   0x1180080e0c1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6198"             ,	   0x1180080e0c1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6199"             ,	   0x1180080e0c1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6200"             ,	   0x1180080e0c1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6201"             ,	   0x1180080e0c1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6202"             ,	   0x1180080e0c1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6203"             ,	   0x1180080e0c1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6204"             ,	   0x1180080e0c1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6205"             ,	   0x1180080e0c1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6206"             ,	   0x1180080e0c1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6207"             ,	   0x1180080e0c1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6208"             ,	   0x1180080e0c200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6209"             ,	   0x1180080e0c208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6210"             ,	   0x1180080e0c210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6211"             ,	   0x1180080e0c218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6212"             ,	   0x1180080e0c220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6213"             ,	   0x1180080e0c228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6214"             ,	   0x1180080e0c230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6215"             ,	   0x1180080e0c238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6216"             ,	   0x1180080e0c240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6217"             ,	   0x1180080e0c248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6218"             ,	   0x1180080e0c250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6219"             ,	   0x1180080e0c258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6220"             ,	   0x1180080e0c260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6221"             ,	   0x1180080e0c268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6222"             ,	   0x1180080e0c270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6223"             ,	   0x1180080e0c278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6224"             ,	   0x1180080e0c280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6225"             ,	   0x1180080e0c288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6226"             ,	   0x1180080e0c290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6227"             ,	   0x1180080e0c298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6228"             ,	   0x1180080e0c2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6229"             ,	   0x1180080e0c2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6230"             ,	   0x1180080e0c2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6231"             ,	   0x1180080e0c2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6232"             ,	   0x1180080e0c2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6233"             ,	   0x1180080e0c2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6234"             ,	   0x1180080e0c2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6235"             ,	   0x1180080e0c2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6236"             ,	   0x1180080e0c2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6237"             ,	   0x1180080e0c2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6238"             ,	   0x1180080e0c2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6239"             ,	   0x1180080e0c2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6240"             ,	   0x1180080e0c300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6241"             ,	   0x1180080e0c308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6242"             ,	   0x1180080e0c310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6243"             ,	   0x1180080e0c318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6244"             ,	   0x1180080e0c320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6245"             ,	   0x1180080e0c328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6246"             ,	   0x1180080e0c330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6247"             ,	   0x1180080e0c338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6248"             ,	   0x1180080e0c340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6249"             ,	   0x1180080e0c348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6250"             ,	   0x1180080e0c350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6251"             ,	   0x1180080e0c358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6252"             ,	   0x1180080e0c360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6253"             ,	   0x1180080e0c368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6254"             ,	   0x1180080e0c370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6255"             ,	   0x1180080e0c378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6256"             ,	   0x1180080e0c380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6257"             ,	   0x1180080e0c388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6258"             ,	   0x1180080e0c390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6259"             ,	   0x1180080e0c398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6260"             ,	   0x1180080e0c3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6261"             ,	   0x1180080e0c3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6262"             ,	   0x1180080e0c3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6263"             ,	   0x1180080e0c3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6264"             ,	   0x1180080e0c3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6265"             ,	   0x1180080e0c3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6266"             ,	   0x1180080e0c3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6267"             ,	   0x1180080e0c3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6268"             ,	   0x1180080e0c3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6269"             ,	   0x1180080e0c3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6270"             ,	   0x1180080e0c3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6271"             ,	   0x1180080e0c3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6272"             ,	   0x1180080e0c400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6273"             ,	   0x1180080e0c408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6274"             ,	   0x1180080e0c410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6275"             ,	   0x1180080e0c418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6276"             ,	   0x1180080e0c420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6277"             ,	   0x1180080e0c428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6278"             ,	   0x1180080e0c430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6279"             ,	   0x1180080e0c438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6280"             ,	   0x1180080e0c440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6281"             ,	   0x1180080e0c448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6282"             ,	   0x1180080e0c450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6283"             ,	   0x1180080e0c458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6284"             ,	   0x1180080e0c460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6285"             ,	   0x1180080e0c468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6286"             ,	   0x1180080e0c470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6287"             ,	   0x1180080e0c478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6288"             ,	   0x1180080e0c480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6289"             ,	   0x1180080e0c488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6290"             ,	   0x1180080e0c490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6291"             ,	   0x1180080e0c498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6292"             ,	   0x1180080e0c4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6293"             ,	   0x1180080e0c4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6294"             ,	   0x1180080e0c4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6295"             ,	   0x1180080e0c4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6296"             ,	   0x1180080e0c4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6297"             ,	   0x1180080e0c4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6298"             ,	   0x1180080e0c4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6299"             ,	   0x1180080e0c4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6300"             ,	   0x1180080e0c4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6301"             ,	   0x1180080e0c4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6302"             ,	   0x1180080e0c4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6303"             ,	   0x1180080e0c4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6304"             ,	   0x1180080e0c500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6305"             ,	   0x1180080e0c508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6306"             ,	   0x1180080e0c510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6307"             ,	   0x1180080e0c518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6308"             ,	   0x1180080e0c520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6309"             ,	   0x1180080e0c528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6310"             ,	   0x1180080e0c530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6311"             ,	   0x1180080e0c538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6312"             ,	   0x1180080e0c540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6313"             ,	   0x1180080e0c548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6314"             ,	   0x1180080e0c550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6315"             ,	   0x1180080e0c558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6316"             ,	   0x1180080e0c560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6317"             ,	   0x1180080e0c568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6318"             ,	   0x1180080e0c570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6319"             ,	   0x1180080e0c578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6320"             ,	   0x1180080e0c580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6321"             ,	   0x1180080e0c588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6322"             ,	   0x1180080e0c590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6323"             ,	   0x1180080e0c598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6324"             ,	   0x1180080e0c5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6325"             ,	   0x1180080e0c5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6326"             ,	   0x1180080e0c5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6327"             ,	   0x1180080e0c5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6328"             ,	   0x1180080e0c5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6329"             ,	   0x1180080e0c5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6330"             ,	   0x1180080e0c5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6331"             ,	   0x1180080e0c5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6332"             ,	   0x1180080e0c5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6333"             ,	   0x1180080e0c5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6334"             ,	   0x1180080e0c5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6335"             ,	   0x1180080e0c5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6336"             ,	   0x1180080e0c600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6337"             ,	   0x1180080e0c608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6338"             ,	   0x1180080e0c610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6339"             ,	   0x1180080e0c618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6340"             ,	   0x1180080e0c620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6341"             ,	   0x1180080e0c628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6342"             ,	   0x1180080e0c630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6343"             ,	   0x1180080e0c638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6344"             ,	   0x1180080e0c640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6345"             ,	   0x1180080e0c648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6346"             ,	   0x1180080e0c650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6347"             ,	   0x1180080e0c658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6348"             ,	   0x1180080e0c660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6349"             ,	   0x1180080e0c668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6350"             ,	   0x1180080e0c670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6351"             ,	   0x1180080e0c678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6352"             ,	   0x1180080e0c680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6353"             ,	   0x1180080e0c688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6354"             ,	   0x1180080e0c690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6355"             ,	   0x1180080e0c698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6356"             ,	   0x1180080e0c6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6357"             ,	   0x1180080e0c6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6358"             ,	   0x1180080e0c6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6359"             ,	   0x1180080e0c6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6360"             ,	   0x1180080e0c6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6361"             ,	   0x1180080e0c6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6362"             ,	   0x1180080e0c6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6363"             ,	   0x1180080e0c6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6364"             ,	   0x1180080e0c6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6365"             ,	   0x1180080e0c6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6366"             ,	   0x1180080e0c6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6367"             ,	   0x1180080e0c6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6368"             ,	   0x1180080e0c700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6369"             ,	   0x1180080e0c708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6370"             ,	   0x1180080e0c710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6371"             ,	   0x1180080e0c718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6372"             ,	   0x1180080e0c720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6373"             ,	   0x1180080e0c728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6374"             ,	   0x1180080e0c730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6375"             ,	   0x1180080e0c738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6376"             ,	   0x1180080e0c740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6377"             ,	   0x1180080e0c748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6378"             ,	   0x1180080e0c750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6379"             ,	   0x1180080e0c758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6380"             ,	   0x1180080e0c760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6381"             ,	   0x1180080e0c768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6382"             ,	   0x1180080e0c770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6383"             ,	   0x1180080e0c778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6384"             ,	   0x1180080e0c780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6385"             ,	   0x1180080e0c788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6386"             ,	   0x1180080e0c790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6387"             ,	   0x1180080e0c798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6388"             ,	   0x1180080e0c7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6389"             ,	   0x1180080e0c7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6390"             ,	   0x1180080e0c7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6391"             ,	   0x1180080e0c7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6392"             ,	   0x1180080e0c7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6393"             ,	   0x1180080e0c7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6394"             ,	   0x1180080e0c7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6395"             ,	   0x1180080e0c7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6396"             ,	   0x1180080e0c7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6397"             ,	   0x1180080e0c7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6398"             ,	   0x1180080e0c7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6399"             ,	   0x1180080e0c7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6400"             ,	   0x1180080e0c800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6401"             ,	   0x1180080e0c808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6402"             ,	   0x1180080e0c810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6403"             ,	   0x1180080e0c818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6404"             ,	   0x1180080e0c820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6405"             ,	   0x1180080e0c828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6406"             ,	   0x1180080e0c830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6407"             ,	   0x1180080e0c838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6408"             ,	   0x1180080e0c840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6409"             ,	   0x1180080e0c848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6410"             ,	   0x1180080e0c850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6411"             ,	   0x1180080e0c858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6412"             ,	   0x1180080e0c860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6413"             ,	   0x1180080e0c868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6414"             ,	   0x1180080e0c870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6415"             ,	   0x1180080e0c878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6416"             ,	   0x1180080e0c880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6417"             ,	   0x1180080e0c888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6418"             ,	   0x1180080e0c890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6419"             ,	   0x1180080e0c898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6420"             ,	   0x1180080e0c8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6421"             ,	   0x1180080e0c8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6422"             ,	   0x1180080e0c8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6423"             ,	   0x1180080e0c8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6424"             ,	   0x1180080e0c8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6425"             ,	   0x1180080e0c8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6426"             ,	   0x1180080e0c8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6427"             ,	   0x1180080e0c8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6428"             ,	   0x1180080e0c8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6429"             ,	   0x1180080e0c8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6430"             ,	   0x1180080e0c8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6431"             ,	   0x1180080e0c8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6432"             ,	   0x1180080e0c900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6433"             ,	   0x1180080e0c908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6434"             ,	   0x1180080e0c910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6435"             ,	   0x1180080e0c918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6436"             ,	   0x1180080e0c920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6437"             ,	   0x1180080e0c928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6438"             ,	   0x1180080e0c930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6439"             ,	   0x1180080e0c938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6440"             ,	   0x1180080e0c940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6441"             ,	   0x1180080e0c948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6442"             ,	   0x1180080e0c950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6443"             ,	   0x1180080e0c958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6444"             ,	   0x1180080e0c960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6445"             ,	   0x1180080e0c968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6446"             ,	   0x1180080e0c970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6447"             ,	   0x1180080e0c978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6448"             ,	   0x1180080e0c980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6449"             ,	   0x1180080e0c988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6450"             ,	   0x1180080e0c990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6451"             ,	   0x1180080e0c998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6452"             ,	   0x1180080e0c9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6453"             ,	   0x1180080e0c9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6454"             ,	   0x1180080e0c9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6455"             ,	   0x1180080e0c9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6456"             ,	   0x1180080e0c9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6457"             ,	   0x1180080e0c9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6458"             ,	   0x1180080e0c9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6459"             ,	   0x1180080e0c9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6460"             ,	   0x1180080e0c9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6461"             ,	   0x1180080e0c9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6462"             ,	   0x1180080e0c9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6463"             ,	   0x1180080e0c9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6464"             ,	   0x1180080e0ca00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6465"             ,	   0x1180080e0ca08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6466"             ,	   0x1180080e0ca10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6467"             ,	   0x1180080e0ca18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6468"             ,	   0x1180080e0ca20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6469"             ,	   0x1180080e0ca28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6470"             ,	   0x1180080e0ca30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6471"             ,	   0x1180080e0ca38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6472"             ,	   0x1180080e0ca40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6473"             ,	   0x1180080e0ca48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6474"             ,	   0x1180080e0ca50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6475"             ,	   0x1180080e0ca58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6476"             ,	   0x1180080e0ca60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6477"             ,	   0x1180080e0ca68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6478"             ,	   0x1180080e0ca70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6479"             ,	   0x1180080e0ca78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6480"             ,	   0x1180080e0ca80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6481"             ,	   0x1180080e0ca88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6482"             ,	   0x1180080e0ca90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6483"             ,	   0x1180080e0ca98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6484"             ,	   0x1180080e0caa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6485"             ,	   0x1180080e0caa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6486"             ,	   0x1180080e0cab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6487"             ,	   0x1180080e0cab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6488"             ,	   0x1180080e0cac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6489"             ,	   0x1180080e0cac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6490"             ,	   0x1180080e0cad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6491"             ,	   0x1180080e0cad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6492"             ,	   0x1180080e0cae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6493"             ,	   0x1180080e0cae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6494"             ,	   0x1180080e0caf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6495"             ,	   0x1180080e0caf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6496"             ,	   0x1180080e0cb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6497"             ,	   0x1180080e0cb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6498"             ,	   0x1180080e0cb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6499"             ,	   0x1180080e0cb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6500"             ,	   0x1180080e0cb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6501"             ,	   0x1180080e0cb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6502"             ,	   0x1180080e0cb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6503"             ,	   0x1180080e0cb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6504"             ,	   0x1180080e0cb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6505"             ,	   0x1180080e0cb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6506"             ,	   0x1180080e0cb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6507"             ,	   0x1180080e0cb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6508"             ,	   0x1180080e0cb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6509"             ,	   0x1180080e0cb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6510"             ,	   0x1180080e0cb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6511"             ,	   0x1180080e0cb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6512"             ,	   0x1180080e0cb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6513"             ,	   0x1180080e0cb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6514"             ,	   0x1180080e0cb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6515"             ,	   0x1180080e0cb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6516"             ,	   0x1180080e0cba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6517"             ,	   0x1180080e0cba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6518"             ,	   0x1180080e0cbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6519"             ,	   0x1180080e0cbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6520"             ,	   0x1180080e0cbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6521"             ,	   0x1180080e0cbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6522"             ,	   0x1180080e0cbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6523"             ,	   0x1180080e0cbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6524"             ,	   0x1180080e0cbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6525"             ,	   0x1180080e0cbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6526"             ,	   0x1180080e0cbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6527"             ,	   0x1180080e0cbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6528"             ,	   0x1180080e0cc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6529"             ,	   0x1180080e0cc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6530"             ,	   0x1180080e0cc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6531"             ,	   0x1180080e0cc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6532"             ,	   0x1180080e0cc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6533"             ,	   0x1180080e0cc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6534"             ,	   0x1180080e0cc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6535"             ,	   0x1180080e0cc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6536"             ,	   0x1180080e0cc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6537"             ,	   0x1180080e0cc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6538"             ,	   0x1180080e0cc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6539"             ,	   0x1180080e0cc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6540"             ,	   0x1180080e0cc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6541"             ,	   0x1180080e0cc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6542"             ,	   0x1180080e0cc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6543"             ,	   0x1180080e0cc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6544"             ,	   0x1180080e0cc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6545"             ,	   0x1180080e0cc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6546"             ,	   0x1180080e0cc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6547"             ,	   0x1180080e0cc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6548"             ,	   0x1180080e0cca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6549"             ,	   0x1180080e0cca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6550"             ,	   0x1180080e0ccb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6551"             ,	   0x1180080e0ccb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6552"             ,	   0x1180080e0ccc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6553"             ,	   0x1180080e0ccc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6554"             ,	   0x1180080e0ccd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6555"             ,	   0x1180080e0ccd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6556"             ,	   0x1180080e0cce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6557"             ,	   0x1180080e0cce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6558"             ,	   0x1180080e0ccf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6559"             ,	   0x1180080e0ccf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6560"             ,	   0x1180080e0cd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6561"             ,	   0x1180080e0cd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6562"             ,	   0x1180080e0cd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6563"             ,	   0x1180080e0cd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6564"             ,	   0x1180080e0cd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6565"             ,	   0x1180080e0cd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6566"             ,	   0x1180080e0cd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6567"             ,	   0x1180080e0cd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6568"             ,	   0x1180080e0cd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6569"             ,	   0x1180080e0cd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6570"             ,	   0x1180080e0cd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6571"             ,	   0x1180080e0cd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6572"             ,	   0x1180080e0cd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6573"             ,	   0x1180080e0cd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6574"             ,	   0x1180080e0cd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6575"             ,	   0x1180080e0cd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6576"             ,	   0x1180080e0cd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6577"             ,	   0x1180080e0cd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6578"             ,	   0x1180080e0cd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6579"             ,	   0x1180080e0cd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6580"             ,	   0x1180080e0cda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6581"             ,	   0x1180080e0cda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6582"             ,	   0x1180080e0cdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6583"             ,	   0x1180080e0cdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6584"             ,	   0x1180080e0cdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6585"             ,	   0x1180080e0cdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6586"             ,	   0x1180080e0cdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6587"             ,	   0x1180080e0cdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6588"             ,	   0x1180080e0cde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6589"             ,	   0x1180080e0cde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6590"             ,	   0x1180080e0cdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6591"             ,	   0x1180080e0cdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6592"             ,	   0x1180080e0ce00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6593"             ,	   0x1180080e0ce08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6594"             ,	   0x1180080e0ce10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6595"             ,	   0x1180080e0ce18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6596"             ,	   0x1180080e0ce20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6597"             ,	   0x1180080e0ce28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6598"             ,	   0x1180080e0ce30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6599"             ,	   0x1180080e0ce38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6600"             ,	   0x1180080e0ce40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6601"             ,	   0x1180080e0ce48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6602"             ,	   0x1180080e0ce50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6603"             ,	   0x1180080e0ce58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6604"             ,	   0x1180080e0ce60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6605"             ,	   0x1180080e0ce68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6606"             ,	   0x1180080e0ce70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6607"             ,	   0x1180080e0ce78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6608"             ,	   0x1180080e0ce80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6609"             ,	   0x1180080e0ce88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6610"             ,	   0x1180080e0ce90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6611"             ,	   0x1180080e0ce98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6612"             ,	   0x1180080e0cea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6613"             ,	   0x1180080e0cea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6614"             ,	   0x1180080e0ceb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6615"             ,	   0x1180080e0ceb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6616"             ,	   0x1180080e0cec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6617"             ,	   0x1180080e0cec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6618"             ,	   0x1180080e0ced0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6619"             ,	   0x1180080e0ced8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6620"             ,	   0x1180080e0cee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6621"             ,	   0x1180080e0cee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6622"             ,	   0x1180080e0cef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6623"             ,	   0x1180080e0cef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6624"             ,	   0x1180080e0cf00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6625"             ,	   0x1180080e0cf08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6626"             ,	   0x1180080e0cf10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6627"             ,	   0x1180080e0cf18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6628"             ,	   0x1180080e0cf20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6629"             ,	   0x1180080e0cf28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6630"             ,	   0x1180080e0cf30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6631"             ,	   0x1180080e0cf38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6632"             ,	   0x1180080e0cf40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6633"             ,	   0x1180080e0cf48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6634"             ,	   0x1180080e0cf50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6635"             ,	   0x1180080e0cf58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6636"             ,	   0x1180080e0cf60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6637"             ,	   0x1180080e0cf68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6638"             ,	   0x1180080e0cf70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6639"             ,	   0x1180080e0cf78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6640"             ,	   0x1180080e0cf80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6641"             ,	   0x1180080e0cf88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6642"             ,	   0x1180080e0cf90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6643"             ,	   0x1180080e0cf98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6644"             ,	   0x1180080e0cfa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6645"             ,	   0x1180080e0cfa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6646"             ,	   0x1180080e0cfb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6647"             ,	   0x1180080e0cfb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6648"             ,	   0x1180080e0cfc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6649"             ,	   0x1180080e0cfc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6650"             ,	   0x1180080e0cfd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6651"             ,	   0x1180080e0cfd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6652"             ,	   0x1180080e0cfe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6653"             ,	   0x1180080e0cfe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6654"             ,	   0x1180080e0cff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6655"             ,	   0x1180080e0cff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6656"             ,	   0x1180080e0d000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6657"             ,	   0x1180080e0d008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6658"             ,	   0x1180080e0d010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6659"             ,	   0x1180080e0d018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6660"             ,	   0x1180080e0d020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6661"             ,	   0x1180080e0d028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6662"             ,	   0x1180080e0d030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6663"             ,	   0x1180080e0d038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6664"             ,	   0x1180080e0d040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6665"             ,	   0x1180080e0d048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6666"             ,	   0x1180080e0d050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6667"             ,	   0x1180080e0d058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6668"             ,	   0x1180080e0d060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6669"             ,	   0x1180080e0d068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6670"             ,	   0x1180080e0d070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6671"             ,	   0x1180080e0d078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6672"             ,	   0x1180080e0d080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6673"             ,	   0x1180080e0d088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6674"             ,	   0x1180080e0d090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6675"             ,	   0x1180080e0d098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6676"             ,	   0x1180080e0d0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6677"             ,	   0x1180080e0d0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6678"             ,	   0x1180080e0d0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6679"             ,	   0x1180080e0d0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6680"             ,	   0x1180080e0d0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6681"             ,	   0x1180080e0d0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6682"             ,	   0x1180080e0d0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6683"             ,	   0x1180080e0d0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6684"             ,	   0x1180080e0d0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6685"             ,	   0x1180080e0d0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6686"             ,	   0x1180080e0d0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6687"             ,	   0x1180080e0d0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6688"             ,	   0x1180080e0d100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6689"             ,	   0x1180080e0d108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6690"             ,	   0x1180080e0d110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6691"             ,	   0x1180080e0d118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6692"             ,	   0x1180080e0d120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6693"             ,	   0x1180080e0d128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6694"             ,	   0x1180080e0d130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6695"             ,	   0x1180080e0d138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6696"             ,	   0x1180080e0d140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6697"             ,	   0x1180080e0d148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6698"             ,	   0x1180080e0d150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6699"             ,	   0x1180080e0d158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6700"             ,	   0x1180080e0d160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6701"             ,	   0x1180080e0d168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6702"             ,	   0x1180080e0d170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6703"             ,	   0x1180080e0d178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6704"             ,	   0x1180080e0d180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6705"             ,	   0x1180080e0d188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6706"             ,	   0x1180080e0d190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6707"             ,	   0x1180080e0d198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6708"             ,	   0x1180080e0d1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6709"             ,	   0x1180080e0d1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6710"             ,	   0x1180080e0d1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6711"             ,	   0x1180080e0d1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6712"             ,	   0x1180080e0d1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6713"             ,	   0x1180080e0d1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6714"             ,	   0x1180080e0d1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6715"             ,	   0x1180080e0d1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6716"             ,	   0x1180080e0d1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6717"             ,	   0x1180080e0d1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6718"             ,	   0x1180080e0d1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6719"             ,	   0x1180080e0d1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6720"             ,	   0x1180080e0d200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6721"             ,	   0x1180080e0d208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6722"             ,	   0x1180080e0d210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6723"             ,	   0x1180080e0d218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6724"             ,	   0x1180080e0d220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6725"             ,	   0x1180080e0d228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6726"             ,	   0x1180080e0d230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6727"             ,	   0x1180080e0d238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6728"             ,	   0x1180080e0d240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6729"             ,	   0x1180080e0d248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6730"             ,	   0x1180080e0d250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6731"             ,	   0x1180080e0d258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6732"             ,	   0x1180080e0d260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6733"             ,	   0x1180080e0d268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6734"             ,	   0x1180080e0d270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6735"             ,	   0x1180080e0d278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6736"             ,	   0x1180080e0d280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6737"             ,	   0x1180080e0d288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6738"             ,	   0x1180080e0d290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6739"             ,	   0x1180080e0d298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6740"             ,	   0x1180080e0d2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6741"             ,	   0x1180080e0d2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6742"             ,	   0x1180080e0d2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6743"             ,	   0x1180080e0d2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6744"             ,	   0x1180080e0d2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6745"             ,	   0x1180080e0d2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6746"             ,	   0x1180080e0d2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6747"             ,	   0x1180080e0d2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6748"             ,	   0x1180080e0d2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6749"             ,	   0x1180080e0d2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6750"             ,	   0x1180080e0d2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6751"             ,	   0x1180080e0d2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6752"             ,	   0x1180080e0d300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6753"             ,	   0x1180080e0d308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6754"             ,	   0x1180080e0d310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6755"             ,	   0x1180080e0d318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6756"             ,	   0x1180080e0d320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6757"             ,	   0x1180080e0d328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6758"             ,	   0x1180080e0d330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6759"             ,	   0x1180080e0d338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6760"             ,	   0x1180080e0d340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6761"             ,	   0x1180080e0d348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6762"             ,	   0x1180080e0d350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6763"             ,	   0x1180080e0d358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6764"             ,	   0x1180080e0d360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6765"             ,	   0x1180080e0d368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6766"             ,	   0x1180080e0d370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6767"             ,	   0x1180080e0d378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6768"             ,	   0x1180080e0d380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6769"             ,	   0x1180080e0d388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6770"             ,	   0x1180080e0d390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6771"             ,	   0x1180080e0d398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6772"             ,	   0x1180080e0d3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6773"             ,	   0x1180080e0d3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6774"             ,	   0x1180080e0d3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6775"             ,	   0x1180080e0d3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6776"             ,	   0x1180080e0d3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6777"             ,	   0x1180080e0d3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6778"             ,	   0x1180080e0d3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6779"             ,	   0x1180080e0d3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6780"             ,	   0x1180080e0d3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6781"             ,	   0x1180080e0d3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6782"             ,	   0x1180080e0d3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6783"             ,	   0x1180080e0d3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6784"             ,	   0x1180080e0d400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6785"             ,	   0x1180080e0d408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6786"             ,	   0x1180080e0d410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6787"             ,	   0x1180080e0d418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6788"             ,	   0x1180080e0d420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6789"             ,	   0x1180080e0d428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6790"             ,	   0x1180080e0d430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6791"             ,	   0x1180080e0d438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6792"             ,	   0x1180080e0d440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6793"             ,	   0x1180080e0d448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6794"             ,	   0x1180080e0d450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6795"             ,	   0x1180080e0d458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6796"             ,	   0x1180080e0d460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6797"             ,	   0x1180080e0d468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6798"             ,	   0x1180080e0d470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6799"             ,	   0x1180080e0d478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6800"             ,	   0x1180080e0d480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6801"             ,	   0x1180080e0d488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6802"             ,	   0x1180080e0d490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6803"             ,	   0x1180080e0d498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6804"             ,	   0x1180080e0d4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6805"             ,	   0x1180080e0d4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6806"             ,	   0x1180080e0d4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6807"             ,	   0x1180080e0d4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6808"             ,	   0x1180080e0d4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6809"             ,	   0x1180080e0d4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6810"             ,	   0x1180080e0d4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6811"             ,	   0x1180080e0d4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6812"             ,	   0x1180080e0d4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6813"             ,	   0x1180080e0d4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6814"             ,	   0x1180080e0d4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6815"             ,	   0x1180080e0d4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6816"             ,	   0x1180080e0d500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6817"             ,	   0x1180080e0d508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6818"             ,	   0x1180080e0d510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6819"             ,	   0x1180080e0d518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6820"             ,	   0x1180080e0d520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6821"             ,	   0x1180080e0d528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6822"             ,	   0x1180080e0d530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6823"             ,	   0x1180080e0d538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6824"             ,	   0x1180080e0d540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6825"             ,	   0x1180080e0d548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6826"             ,	   0x1180080e0d550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6827"             ,	   0x1180080e0d558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6828"             ,	   0x1180080e0d560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6829"             ,	   0x1180080e0d568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6830"             ,	   0x1180080e0d570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6831"             ,	   0x1180080e0d578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6832"             ,	   0x1180080e0d580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6833"             ,	   0x1180080e0d588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6834"             ,	   0x1180080e0d590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6835"             ,	   0x1180080e0d598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6836"             ,	   0x1180080e0d5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6837"             ,	   0x1180080e0d5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6838"             ,	   0x1180080e0d5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6839"             ,	   0x1180080e0d5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6840"             ,	   0x1180080e0d5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6841"             ,	   0x1180080e0d5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6842"             ,	   0x1180080e0d5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6843"             ,	   0x1180080e0d5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6844"             ,	   0x1180080e0d5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6845"             ,	   0x1180080e0d5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6846"             ,	   0x1180080e0d5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6847"             ,	   0x1180080e0d5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6848"             ,	   0x1180080e0d600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6849"             ,	   0x1180080e0d608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6850"             ,	   0x1180080e0d610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6851"             ,	   0x1180080e0d618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6852"             ,	   0x1180080e0d620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6853"             ,	   0x1180080e0d628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6854"             ,	   0x1180080e0d630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6855"             ,	   0x1180080e0d638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6856"             ,	   0x1180080e0d640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6857"             ,	   0x1180080e0d648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6858"             ,	   0x1180080e0d650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6859"             ,	   0x1180080e0d658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6860"             ,	   0x1180080e0d660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6861"             ,	   0x1180080e0d668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6862"             ,	   0x1180080e0d670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6863"             ,	   0x1180080e0d678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6864"             ,	   0x1180080e0d680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6865"             ,	   0x1180080e0d688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6866"             ,	   0x1180080e0d690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6867"             ,	   0x1180080e0d698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6868"             ,	   0x1180080e0d6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6869"             ,	   0x1180080e0d6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6870"             ,	   0x1180080e0d6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6871"             ,	   0x1180080e0d6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6872"             ,	   0x1180080e0d6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6873"             ,	   0x1180080e0d6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6874"             ,	   0x1180080e0d6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6875"             ,	   0x1180080e0d6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6876"             ,	   0x1180080e0d6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6877"             ,	   0x1180080e0d6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6878"             ,	   0x1180080e0d6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6879"             ,	   0x1180080e0d6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6880"             ,	   0x1180080e0d700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6881"             ,	   0x1180080e0d708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6882"             ,	   0x1180080e0d710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6883"             ,	   0x1180080e0d718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6884"             ,	   0x1180080e0d720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6885"             ,	   0x1180080e0d728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6886"             ,	   0x1180080e0d730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6887"             ,	   0x1180080e0d738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6888"             ,	   0x1180080e0d740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6889"             ,	   0x1180080e0d748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6890"             ,	   0x1180080e0d750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6891"             ,	   0x1180080e0d758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6892"             ,	   0x1180080e0d760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6893"             ,	   0x1180080e0d768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6894"             ,	   0x1180080e0d770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6895"             ,	   0x1180080e0d778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6896"             ,	   0x1180080e0d780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6897"             ,	   0x1180080e0d788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6898"             ,	   0x1180080e0d790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6899"             ,	   0x1180080e0d798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6900"             ,	   0x1180080e0d7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6901"             ,	   0x1180080e0d7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6902"             ,	   0x1180080e0d7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6903"             ,	   0x1180080e0d7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6904"             ,	   0x1180080e0d7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6905"             ,	   0x1180080e0d7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6906"             ,	   0x1180080e0d7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6907"             ,	   0x1180080e0d7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6908"             ,	   0x1180080e0d7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6909"             ,	   0x1180080e0d7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6910"             ,	   0x1180080e0d7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6911"             ,	   0x1180080e0d7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6912"             ,	   0x1180080e0d800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6913"             ,	   0x1180080e0d808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6914"             ,	   0x1180080e0d810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6915"             ,	   0x1180080e0d818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6916"             ,	   0x1180080e0d820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6917"             ,	   0x1180080e0d828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6918"             ,	   0x1180080e0d830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6919"             ,	   0x1180080e0d838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6920"             ,	   0x1180080e0d840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6921"             ,	   0x1180080e0d848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6922"             ,	   0x1180080e0d850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6923"             ,	   0x1180080e0d858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6924"             ,	   0x1180080e0d860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6925"             ,	   0x1180080e0d868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6926"             ,	   0x1180080e0d870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6927"             ,	   0x1180080e0d878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6928"             ,	   0x1180080e0d880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6929"             ,	   0x1180080e0d888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6930"             ,	   0x1180080e0d890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6931"             ,	   0x1180080e0d898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6932"             ,	   0x1180080e0d8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6933"             ,	   0x1180080e0d8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6934"             ,	   0x1180080e0d8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6935"             ,	   0x1180080e0d8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6936"             ,	   0x1180080e0d8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6937"             ,	   0x1180080e0d8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6938"             ,	   0x1180080e0d8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6939"             ,	   0x1180080e0d8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6940"             ,	   0x1180080e0d8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6941"             ,	   0x1180080e0d8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6942"             ,	   0x1180080e0d8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6943"             ,	   0x1180080e0d8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6944"             ,	   0x1180080e0d900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6945"             ,	   0x1180080e0d908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6946"             ,	   0x1180080e0d910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6947"             ,	   0x1180080e0d918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6948"             ,	   0x1180080e0d920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6949"             ,	   0x1180080e0d928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6950"             ,	   0x1180080e0d930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6951"             ,	   0x1180080e0d938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6952"             ,	   0x1180080e0d940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6953"             ,	   0x1180080e0d948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6954"             ,	   0x1180080e0d950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6955"             ,	   0x1180080e0d958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6956"             ,	   0x1180080e0d960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6957"             ,	   0x1180080e0d968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6958"             ,	   0x1180080e0d970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6959"             ,	   0x1180080e0d978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6960"             ,	   0x1180080e0d980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6961"             ,	   0x1180080e0d988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6962"             ,	   0x1180080e0d990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6963"             ,	   0x1180080e0d998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6964"             ,	   0x1180080e0d9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6965"             ,	   0x1180080e0d9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6966"             ,	   0x1180080e0d9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6967"             ,	   0x1180080e0d9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6968"             ,	   0x1180080e0d9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6969"             ,	   0x1180080e0d9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6970"             ,	   0x1180080e0d9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6971"             ,	   0x1180080e0d9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6972"             ,	   0x1180080e0d9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6973"             ,	   0x1180080e0d9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6974"             ,	   0x1180080e0d9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6975"             ,	   0x1180080e0d9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6976"             ,	   0x1180080e0da00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6977"             ,	   0x1180080e0da08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6978"             ,	   0x1180080e0da10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6979"             ,	   0x1180080e0da18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6980"             ,	   0x1180080e0da20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6981"             ,	   0x1180080e0da28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6982"             ,	   0x1180080e0da30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6983"             ,	   0x1180080e0da38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6984"             ,	   0x1180080e0da40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6985"             ,	   0x1180080e0da48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6986"             ,	   0x1180080e0da50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6987"             ,	   0x1180080e0da58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6988"             ,	   0x1180080e0da60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6989"             ,	   0x1180080e0da68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6990"             ,	   0x1180080e0da70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6991"             ,	   0x1180080e0da78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6992"             ,	   0x1180080e0da80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6993"             ,	   0x1180080e0da88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6994"             ,	   0x1180080e0da90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6995"             ,	   0x1180080e0da98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6996"             ,	   0x1180080e0daa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6997"             ,	   0x1180080e0daa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6998"             ,	   0x1180080e0dab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP6999"             ,	   0x1180080e0dab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7000"             ,	   0x1180080e0dac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7001"             ,	   0x1180080e0dac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7002"             ,	   0x1180080e0dad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7003"             ,	   0x1180080e0dad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7004"             ,	   0x1180080e0dae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7005"             ,	   0x1180080e0dae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7006"             ,	   0x1180080e0daf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7007"             ,	   0x1180080e0daf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7008"             ,	   0x1180080e0db00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7009"             ,	   0x1180080e0db08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7010"             ,	   0x1180080e0db10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7011"             ,	   0x1180080e0db18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7012"             ,	   0x1180080e0db20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7013"             ,	   0x1180080e0db28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7014"             ,	   0x1180080e0db30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7015"             ,	   0x1180080e0db38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7016"             ,	   0x1180080e0db40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7017"             ,	   0x1180080e0db48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7018"             ,	   0x1180080e0db50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7019"             ,	   0x1180080e0db58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7020"             ,	   0x1180080e0db60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7021"             ,	   0x1180080e0db68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7022"             ,	   0x1180080e0db70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7023"             ,	   0x1180080e0db78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7024"             ,	   0x1180080e0db80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7025"             ,	   0x1180080e0db88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7026"             ,	   0x1180080e0db90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7027"             ,	   0x1180080e0db98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7028"             ,	   0x1180080e0dba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7029"             ,	   0x1180080e0dba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7030"             ,	   0x1180080e0dbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7031"             ,	   0x1180080e0dbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7032"             ,	   0x1180080e0dbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7033"             ,	   0x1180080e0dbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7034"             ,	   0x1180080e0dbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7035"             ,	   0x1180080e0dbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7036"             ,	   0x1180080e0dbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7037"             ,	   0x1180080e0dbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7038"             ,	   0x1180080e0dbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7039"             ,	   0x1180080e0dbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7040"             ,	   0x1180080e0dc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7041"             ,	   0x1180080e0dc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7042"             ,	   0x1180080e0dc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7043"             ,	   0x1180080e0dc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7044"             ,	   0x1180080e0dc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7045"             ,	   0x1180080e0dc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7046"             ,	   0x1180080e0dc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7047"             ,	   0x1180080e0dc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7048"             ,	   0x1180080e0dc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7049"             ,	   0x1180080e0dc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7050"             ,	   0x1180080e0dc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7051"             ,	   0x1180080e0dc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7052"             ,	   0x1180080e0dc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7053"             ,	   0x1180080e0dc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7054"             ,	   0x1180080e0dc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7055"             ,	   0x1180080e0dc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7056"             ,	   0x1180080e0dc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7057"             ,	   0x1180080e0dc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7058"             ,	   0x1180080e0dc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7059"             ,	   0x1180080e0dc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7060"             ,	   0x1180080e0dca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7061"             ,	   0x1180080e0dca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7062"             ,	   0x1180080e0dcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7063"             ,	   0x1180080e0dcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7064"             ,	   0x1180080e0dcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7065"             ,	   0x1180080e0dcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7066"             ,	   0x1180080e0dcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7067"             ,	   0x1180080e0dcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7068"             ,	   0x1180080e0dce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7069"             ,	   0x1180080e0dce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7070"             ,	   0x1180080e0dcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7071"             ,	   0x1180080e0dcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7072"             ,	   0x1180080e0dd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7073"             ,	   0x1180080e0dd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7074"             ,	   0x1180080e0dd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7075"             ,	   0x1180080e0dd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7076"             ,	   0x1180080e0dd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7077"             ,	   0x1180080e0dd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7078"             ,	   0x1180080e0dd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7079"             ,	   0x1180080e0dd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7080"             ,	   0x1180080e0dd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7081"             ,	   0x1180080e0dd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7082"             ,	   0x1180080e0dd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7083"             ,	   0x1180080e0dd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7084"             ,	   0x1180080e0dd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7085"             ,	   0x1180080e0dd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7086"             ,	   0x1180080e0dd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7087"             ,	   0x1180080e0dd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7088"             ,	   0x1180080e0dd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7089"             ,	   0x1180080e0dd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7090"             ,	   0x1180080e0dd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7091"             ,	   0x1180080e0dd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7092"             ,	   0x1180080e0dda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7093"             ,	   0x1180080e0dda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7094"             ,	   0x1180080e0ddb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7095"             ,	   0x1180080e0ddb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7096"             ,	   0x1180080e0ddc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7097"             ,	   0x1180080e0ddc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7098"             ,	   0x1180080e0ddd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7099"             ,	   0x1180080e0ddd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7100"             ,	   0x1180080e0dde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7101"             ,	   0x1180080e0dde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7102"             ,	   0x1180080e0ddf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7103"             ,	   0x1180080e0ddf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7104"             ,	   0x1180080e0de00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7105"             ,	   0x1180080e0de08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7106"             ,	   0x1180080e0de10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7107"             ,	   0x1180080e0de18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7108"             ,	   0x1180080e0de20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7109"             ,	   0x1180080e0de28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7110"             ,	   0x1180080e0de30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7111"             ,	   0x1180080e0de38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7112"             ,	   0x1180080e0de40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7113"             ,	   0x1180080e0de48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7114"             ,	   0x1180080e0de50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7115"             ,	   0x1180080e0de58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7116"             ,	   0x1180080e0de60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7117"             ,	   0x1180080e0de68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7118"             ,	   0x1180080e0de70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7119"             ,	   0x1180080e0de78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7120"             ,	   0x1180080e0de80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7121"             ,	   0x1180080e0de88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7122"             ,	   0x1180080e0de90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7123"             ,	   0x1180080e0de98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7124"             ,	   0x1180080e0dea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7125"             ,	   0x1180080e0dea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7126"             ,	   0x1180080e0deb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7127"             ,	   0x1180080e0deb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7128"             ,	   0x1180080e0dec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7129"             ,	   0x1180080e0dec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7130"             ,	   0x1180080e0ded0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7131"             ,	   0x1180080e0ded8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7132"             ,	   0x1180080e0dee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7133"             ,	   0x1180080e0dee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7134"             ,	   0x1180080e0def0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7135"             ,	   0x1180080e0def8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7136"             ,	   0x1180080e0df00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7137"             ,	   0x1180080e0df08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7138"             ,	   0x1180080e0df10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7139"             ,	   0x1180080e0df18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7140"             ,	   0x1180080e0df20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7141"             ,	   0x1180080e0df28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7142"             ,	   0x1180080e0df30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7143"             ,	   0x1180080e0df38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7144"             ,	   0x1180080e0df40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7145"             ,	   0x1180080e0df48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7146"             ,	   0x1180080e0df50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7147"             ,	   0x1180080e0df58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7148"             ,	   0x1180080e0df60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7149"             ,	   0x1180080e0df68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7150"             ,	   0x1180080e0df70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7151"             ,	   0x1180080e0df78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7152"             ,	   0x1180080e0df80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7153"             ,	   0x1180080e0df88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7154"             ,	   0x1180080e0df90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7155"             ,	   0x1180080e0df98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7156"             ,	   0x1180080e0dfa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7157"             ,	   0x1180080e0dfa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7158"             ,	   0x1180080e0dfb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7159"             ,	   0x1180080e0dfb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7160"             ,	   0x1180080e0dfc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7161"             ,	   0x1180080e0dfc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7162"             ,	   0x1180080e0dfd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7163"             ,	   0x1180080e0dfd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7164"             ,	   0x1180080e0dfe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7165"             ,	   0x1180080e0dfe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7166"             ,	   0x1180080e0dff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7167"             ,	   0x1180080e0dff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7168"             ,	   0x1180080e0e000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7169"             ,	   0x1180080e0e008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7170"             ,	   0x1180080e0e010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7171"             ,	   0x1180080e0e018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7172"             ,	   0x1180080e0e020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7173"             ,	   0x1180080e0e028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7174"             ,	   0x1180080e0e030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7175"             ,	   0x1180080e0e038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7176"             ,	   0x1180080e0e040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7177"             ,	   0x1180080e0e048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7178"             ,	   0x1180080e0e050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7179"             ,	   0x1180080e0e058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7180"             ,	   0x1180080e0e060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7181"             ,	   0x1180080e0e068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7182"             ,	   0x1180080e0e070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7183"             ,	   0x1180080e0e078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7184"             ,	   0x1180080e0e080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7185"             ,	   0x1180080e0e088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7186"             ,	   0x1180080e0e090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7187"             ,	   0x1180080e0e098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7188"             ,	   0x1180080e0e0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7189"             ,	   0x1180080e0e0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7190"             ,	   0x1180080e0e0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7191"             ,	   0x1180080e0e0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7192"             ,	   0x1180080e0e0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7193"             ,	   0x1180080e0e0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7194"             ,	   0x1180080e0e0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7195"             ,	   0x1180080e0e0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7196"             ,	   0x1180080e0e0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7197"             ,	   0x1180080e0e0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7198"             ,	   0x1180080e0e0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7199"             ,	   0x1180080e0e0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7200"             ,	   0x1180080e0e100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7201"             ,	   0x1180080e0e108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7202"             ,	   0x1180080e0e110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7203"             ,	   0x1180080e0e118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7204"             ,	   0x1180080e0e120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7205"             ,	   0x1180080e0e128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7206"             ,	   0x1180080e0e130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7207"             ,	   0x1180080e0e138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7208"             ,	   0x1180080e0e140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7209"             ,	   0x1180080e0e148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7210"             ,	   0x1180080e0e150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7211"             ,	   0x1180080e0e158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7212"             ,	   0x1180080e0e160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7213"             ,	   0x1180080e0e168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7214"             ,	   0x1180080e0e170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7215"             ,	   0x1180080e0e178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7216"             ,	   0x1180080e0e180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7217"             ,	   0x1180080e0e188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7218"             ,	   0x1180080e0e190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7219"             ,	   0x1180080e0e198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7220"             ,	   0x1180080e0e1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7221"             ,	   0x1180080e0e1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7222"             ,	   0x1180080e0e1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7223"             ,	   0x1180080e0e1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7224"             ,	   0x1180080e0e1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7225"             ,	   0x1180080e0e1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7226"             ,	   0x1180080e0e1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7227"             ,	   0x1180080e0e1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7228"             ,	   0x1180080e0e1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7229"             ,	   0x1180080e0e1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7230"             ,	   0x1180080e0e1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7231"             ,	   0x1180080e0e1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7232"             ,	   0x1180080e0e200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7233"             ,	   0x1180080e0e208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7234"             ,	   0x1180080e0e210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7235"             ,	   0x1180080e0e218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7236"             ,	   0x1180080e0e220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7237"             ,	   0x1180080e0e228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7238"             ,	   0x1180080e0e230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7239"             ,	   0x1180080e0e238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7240"             ,	   0x1180080e0e240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7241"             ,	   0x1180080e0e248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7242"             ,	   0x1180080e0e250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7243"             ,	   0x1180080e0e258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7244"             ,	   0x1180080e0e260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7245"             ,	   0x1180080e0e268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7246"             ,	   0x1180080e0e270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7247"             ,	   0x1180080e0e278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7248"             ,	   0x1180080e0e280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7249"             ,	   0x1180080e0e288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7250"             ,	   0x1180080e0e290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7251"             ,	   0x1180080e0e298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7252"             ,	   0x1180080e0e2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7253"             ,	   0x1180080e0e2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7254"             ,	   0x1180080e0e2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7255"             ,	   0x1180080e0e2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7256"             ,	   0x1180080e0e2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7257"             ,	   0x1180080e0e2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7258"             ,	   0x1180080e0e2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7259"             ,	   0x1180080e0e2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7260"             ,	   0x1180080e0e2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7261"             ,	   0x1180080e0e2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7262"             ,	   0x1180080e0e2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7263"             ,	   0x1180080e0e2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7264"             ,	   0x1180080e0e300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7265"             ,	   0x1180080e0e308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7266"             ,	   0x1180080e0e310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7267"             ,	   0x1180080e0e318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7268"             ,	   0x1180080e0e320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7269"             ,	   0x1180080e0e328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7270"             ,	   0x1180080e0e330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7271"             ,	   0x1180080e0e338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7272"             ,	   0x1180080e0e340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7273"             ,	   0x1180080e0e348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7274"             ,	   0x1180080e0e350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7275"             ,	   0x1180080e0e358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7276"             ,	   0x1180080e0e360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7277"             ,	   0x1180080e0e368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7278"             ,	   0x1180080e0e370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7279"             ,	   0x1180080e0e378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7280"             ,	   0x1180080e0e380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7281"             ,	   0x1180080e0e388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7282"             ,	   0x1180080e0e390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7283"             ,	   0x1180080e0e398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7284"             ,	   0x1180080e0e3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7285"             ,	   0x1180080e0e3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7286"             ,	   0x1180080e0e3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7287"             ,	   0x1180080e0e3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7288"             ,	   0x1180080e0e3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7289"             ,	   0x1180080e0e3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7290"             ,	   0x1180080e0e3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7291"             ,	   0x1180080e0e3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7292"             ,	   0x1180080e0e3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7293"             ,	   0x1180080e0e3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7294"             ,	   0x1180080e0e3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7295"             ,	   0x1180080e0e3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7296"             ,	   0x1180080e0e400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7297"             ,	   0x1180080e0e408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7298"             ,	   0x1180080e0e410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7299"             ,	   0x1180080e0e418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7300"             ,	   0x1180080e0e420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7301"             ,	   0x1180080e0e428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7302"             ,	   0x1180080e0e430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7303"             ,	   0x1180080e0e438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7304"             ,	   0x1180080e0e440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7305"             ,	   0x1180080e0e448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7306"             ,	   0x1180080e0e450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7307"             ,	   0x1180080e0e458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7308"             ,	   0x1180080e0e460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7309"             ,	   0x1180080e0e468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7310"             ,	   0x1180080e0e470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7311"             ,	   0x1180080e0e478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7312"             ,	   0x1180080e0e480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7313"             ,	   0x1180080e0e488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7314"             ,	   0x1180080e0e490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7315"             ,	   0x1180080e0e498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7316"             ,	   0x1180080e0e4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7317"             ,	   0x1180080e0e4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7318"             ,	   0x1180080e0e4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7319"             ,	   0x1180080e0e4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7320"             ,	   0x1180080e0e4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7321"             ,	   0x1180080e0e4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7322"             ,	   0x1180080e0e4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7323"             ,	   0x1180080e0e4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7324"             ,	   0x1180080e0e4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7325"             ,	   0x1180080e0e4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7326"             ,	   0x1180080e0e4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7327"             ,	   0x1180080e0e4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7328"             ,	   0x1180080e0e500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7329"             ,	   0x1180080e0e508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7330"             ,	   0x1180080e0e510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7331"             ,	   0x1180080e0e518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7332"             ,	   0x1180080e0e520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7333"             ,	   0x1180080e0e528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7334"             ,	   0x1180080e0e530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7335"             ,	   0x1180080e0e538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7336"             ,	   0x1180080e0e540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7337"             ,	   0x1180080e0e548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7338"             ,	   0x1180080e0e550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7339"             ,	   0x1180080e0e558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7340"             ,	   0x1180080e0e560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7341"             ,	   0x1180080e0e568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7342"             ,	   0x1180080e0e570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7343"             ,	   0x1180080e0e578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7344"             ,	   0x1180080e0e580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7345"             ,	   0x1180080e0e588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7346"             ,	   0x1180080e0e590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7347"             ,	   0x1180080e0e598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7348"             ,	   0x1180080e0e5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7349"             ,	   0x1180080e0e5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7350"             ,	   0x1180080e0e5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7351"             ,	   0x1180080e0e5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7352"             ,	   0x1180080e0e5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7353"             ,	   0x1180080e0e5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7354"             ,	   0x1180080e0e5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7355"             ,	   0x1180080e0e5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7356"             ,	   0x1180080e0e5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7357"             ,	   0x1180080e0e5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7358"             ,	   0x1180080e0e5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7359"             ,	   0x1180080e0e5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7360"             ,	   0x1180080e0e600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7361"             ,	   0x1180080e0e608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7362"             ,	   0x1180080e0e610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7363"             ,	   0x1180080e0e618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7364"             ,	   0x1180080e0e620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7365"             ,	   0x1180080e0e628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7366"             ,	   0x1180080e0e630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7367"             ,	   0x1180080e0e638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7368"             ,	   0x1180080e0e640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7369"             ,	   0x1180080e0e648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7370"             ,	   0x1180080e0e650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7371"             ,	   0x1180080e0e658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7372"             ,	   0x1180080e0e660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7373"             ,	   0x1180080e0e668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7374"             ,	   0x1180080e0e670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7375"             ,	   0x1180080e0e678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7376"             ,	   0x1180080e0e680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7377"             ,	   0x1180080e0e688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7378"             ,	   0x1180080e0e690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7379"             ,	   0x1180080e0e698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7380"             ,	   0x1180080e0e6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7381"             ,	   0x1180080e0e6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7382"             ,	   0x1180080e0e6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7383"             ,	   0x1180080e0e6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7384"             ,	   0x1180080e0e6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7385"             ,	   0x1180080e0e6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7386"             ,	   0x1180080e0e6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7387"             ,	   0x1180080e0e6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7388"             ,	   0x1180080e0e6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7389"             ,	   0x1180080e0e6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7390"             ,	   0x1180080e0e6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7391"             ,	   0x1180080e0e6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7392"             ,	   0x1180080e0e700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7393"             ,	   0x1180080e0e708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7394"             ,	   0x1180080e0e710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7395"             ,	   0x1180080e0e718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7396"             ,	   0x1180080e0e720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7397"             ,	   0x1180080e0e728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7398"             ,	   0x1180080e0e730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7399"             ,	   0x1180080e0e738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7400"             ,	   0x1180080e0e740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7401"             ,	   0x1180080e0e748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7402"             ,	   0x1180080e0e750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7403"             ,	   0x1180080e0e758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7404"             ,	   0x1180080e0e760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7405"             ,	   0x1180080e0e768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7406"             ,	   0x1180080e0e770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7407"             ,	   0x1180080e0e778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7408"             ,	   0x1180080e0e780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7409"             ,	   0x1180080e0e788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7410"             ,	   0x1180080e0e790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7411"             ,	   0x1180080e0e798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7412"             ,	   0x1180080e0e7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7413"             ,	   0x1180080e0e7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7414"             ,	   0x1180080e0e7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7415"             ,	   0x1180080e0e7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7416"             ,	   0x1180080e0e7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7417"             ,	   0x1180080e0e7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7418"             ,	   0x1180080e0e7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7419"             ,	   0x1180080e0e7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7420"             ,	   0x1180080e0e7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7421"             ,	   0x1180080e0e7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7422"             ,	   0x1180080e0e7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7423"             ,	   0x1180080e0e7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7424"             ,	   0x1180080e0e800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7425"             ,	   0x1180080e0e808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7426"             ,	   0x1180080e0e810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7427"             ,	   0x1180080e0e818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7428"             ,	   0x1180080e0e820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7429"             ,	   0x1180080e0e828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7430"             ,	   0x1180080e0e830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7431"             ,	   0x1180080e0e838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7432"             ,	   0x1180080e0e840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7433"             ,	   0x1180080e0e848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7434"             ,	   0x1180080e0e850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7435"             ,	   0x1180080e0e858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7436"             ,	   0x1180080e0e860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7437"             ,	   0x1180080e0e868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7438"             ,	   0x1180080e0e870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7439"             ,	   0x1180080e0e878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7440"             ,	   0x1180080e0e880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7441"             ,	   0x1180080e0e888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7442"             ,	   0x1180080e0e890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7443"             ,	   0x1180080e0e898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7444"             ,	   0x1180080e0e8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7445"             ,	   0x1180080e0e8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7446"             ,	   0x1180080e0e8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7447"             ,	   0x1180080e0e8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7448"             ,	   0x1180080e0e8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7449"             ,	   0x1180080e0e8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7450"             ,	   0x1180080e0e8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7451"             ,	   0x1180080e0e8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7452"             ,	   0x1180080e0e8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7453"             ,	   0x1180080e0e8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7454"             ,	   0x1180080e0e8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7455"             ,	   0x1180080e0e8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7456"             ,	   0x1180080e0e900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7457"             ,	   0x1180080e0e908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7458"             ,	   0x1180080e0e910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7459"             ,	   0x1180080e0e918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7460"             ,	   0x1180080e0e920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7461"             ,	   0x1180080e0e928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7462"             ,	   0x1180080e0e930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7463"             ,	   0x1180080e0e938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7464"             ,	   0x1180080e0e940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7465"             ,	   0x1180080e0e948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7466"             ,	   0x1180080e0e950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7467"             ,	   0x1180080e0e958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7468"             ,	   0x1180080e0e960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7469"             ,	   0x1180080e0e968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7470"             ,	   0x1180080e0e970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7471"             ,	   0x1180080e0e978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7472"             ,	   0x1180080e0e980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7473"             ,	   0x1180080e0e988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7474"             ,	   0x1180080e0e990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7475"             ,	   0x1180080e0e998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7476"             ,	   0x1180080e0e9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7477"             ,	   0x1180080e0e9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7478"             ,	   0x1180080e0e9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7479"             ,	   0x1180080e0e9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7480"             ,	   0x1180080e0e9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7481"             ,	   0x1180080e0e9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7482"             ,	   0x1180080e0e9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7483"             ,	   0x1180080e0e9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7484"             ,	   0x1180080e0e9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7485"             ,	   0x1180080e0e9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7486"             ,	   0x1180080e0e9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7487"             ,	   0x1180080e0e9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7488"             ,	   0x1180080e0ea00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7489"             ,	   0x1180080e0ea08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7490"             ,	   0x1180080e0ea10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7491"             ,	   0x1180080e0ea18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7492"             ,	   0x1180080e0ea20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7493"             ,	   0x1180080e0ea28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7494"             ,	   0x1180080e0ea30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7495"             ,	   0x1180080e0ea38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7496"             ,	   0x1180080e0ea40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7497"             ,	   0x1180080e0ea48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7498"             ,	   0x1180080e0ea50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7499"             ,	   0x1180080e0ea58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7500"             ,	   0x1180080e0ea60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7501"             ,	   0x1180080e0ea68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7502"             ,	   0x1180080e0ea70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7503"             ,	   0x1180080e0ea78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7504"             ,	   0x1180080e0ea80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7505"             ,	   0x1180080e0ea88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7506"             ,	   0x1180080e0ea90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7507"             ,	   0x1180080e0ea98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7508"             ,	   0x1180080e0eaa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7509"             ,	   0x1180080e0eaa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7510"             ,	   0x1180080e0eab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7511"             ,	   0x1180080e0eab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7512"             ,	   0x1180080e0eac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7513"             ,	   0x1180080e0eac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7514"             ,	   0x1180080e0ead0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7515"             ,	   0x1180080e0ead8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7516"             ,	   0x1180080e0eae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7517"             ,	   0x1180080e0eae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7518"             ,	   0x1180080e0eaf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7519"             ,	   0x1180080e0eaf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7520"             ,	   0x1180080e0eb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7521"             ,	   0x1180080e0eb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7522"             ,	   0x1180080e0eb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7523"             ,	   0x1180080e0eb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7524"             ,	   0x1180080e0eb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7525"             ,	   0x1180080e0eb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7526"             ,	   0x1180080e0eb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7527"             ,	   0x1180080e0eb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7528"             ,	   0x1180080e0eb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7529"             ,	   0x1180080e0eb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7530"             ,	   0x1180080e0eb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7531"             ,	   0x1180080e0eb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7532"             ,	   0x1180080e0eb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7533"             ,	   0x1180080e0eb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7534"             ,	   0x1180080e0eb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7535"             ,	   0x1180080e0eb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7536"             ,	   0x1180080e0eb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7537"             ,	   0x1180080e0eb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7538"             ,	   0x1180080e0eb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7539"             ,	   0x1180080e0eb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7540"             ,	   0x1180080e0eba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7541"             ,	   0x1180080e0eba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7542"             ,	   0x1180080e0ebb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7543"             ,	   0x1180080e0ebb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7544"             ,	   0x1180080e0ebc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7545"             ,	   0x1180080e0ebc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7546"             ,	   0x1180080e0ebd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7547"             ,	   0x1180080e0ebd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7548"             ,	   0x1180080e0ebe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7549"             ,	   0x1180080e0ebe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7550"             ,	   0x1180080e0ebf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7551"             ,	   0x1180080e0ebf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7552"             ,	   0x1180080e0ec00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7553"             ,	   0x1180080e0ec08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7554"             ,	   0x1180080e0ec10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7555"             ,	   0x1180080e0ec18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7556"             ,	   0x1180080e0ec20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7557"             ,	   0x1180080e0ec28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7558"             ,	   0x1180080e0ec30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7559"             ,	   0x1180080e0ec38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7560"             ,	   0x1180080e0ec40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7561"             ,	   0x1180080e0ec48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7562"             ,	   0x1180080e0ec50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7563"             ,	   0x1180080e0ec58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7564"             ,	   0x1180080e0ec60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7565"             ,	   0x1180080e0ec68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7566"             ,	   0x1180080e0ec70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7567"             ,	   0x1180080e0ec78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7568"             ,	   0x1180080e0ec80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7569"             ,	   0x1180080e0ec88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7570"             ,	   0x1180080e0ec90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7571"             ,	   0x1180080e0ec98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7572"             ,	   0x1180080e0eca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7573"             ,	   0x1180080e0eca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7574"             ,	   0x1180080e0ecb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7575"             ,	   0x1180080e0ecb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7576"             ,	   0x1180080e0ecc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7577"             ,	   0x1180080e0ecc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7578"             ,	   0x1180080e0ecd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7579"             ,	   0x1180080e0ecd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7580"             ,	   0x1180080e0ece0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7581"             ,	   0x1180080e0ece8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7582"             ,	   0x1180080e0ecf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7583"             ,	   0x1180080e0ecf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7584"             ,	   0x1180080e0ed00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7585"             ,	   0x1180080e0ed08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7586"             ,	   0x1180080e0ed10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7587"             ,	   0x1180080e0ed18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7588"             ,	   0x1180080e0ed20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7589"             ,	   0x1180080e0ed28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7590"             ,	   0x1180080e0ed30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7591"             ,	   0x1180080e0ed38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7592"             ,	   0x1180080e0ed40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7593"             ,	   0x1180080e0ed48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7594"             ,	   0x1180080e0ed50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7595"             ,	   0x1180080e0ed58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7596"             ,	   0x1180080e0ed60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7597"             ,	   0x1180080e0ed68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7598"             ,	   0x1180080e0ed70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7599"             ,	   0x1180080e0ed78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7600"             ,	   0x1180080e0ed80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7601"             ,	   0x1180080e0ed88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7602"             ,	   0x1180080e0ed90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7603"             ,	   0x1180080e0ed98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7604"             ,	   0x1180080e0eda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7605"             ,	   0x1180080e0eda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7606"             ,	   0x1180080e0edb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7607"             ,	   0x1180080e0edb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7608"             ,	   0x1180080e0edc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7609"             ,	   0x1180080e0edc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7610"             ,	   0x1180080e0edd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7611"             ,	   0x1180080e0edd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7612"             ,	   0x1180080e0ede0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7613"             ,	   0x1180080e0ede8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7614"             ,	   0x1180080e0edf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7615"             ,	   0x1180080e0edf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7616"             ,	   0x1180080e0ee00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7617"             ,	   0x1180080e0ee08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7618"             ,	   0x1180080e0ee10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7619"             ,	   0x1180080e0ee18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7620"             ,	   0x1180080e0ee20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7621"             ,	   0x1180080e0ee28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7622"             ,	   0x1180080e0ee30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7623"             ,	   0x1180080e0ee38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7624"             ,	   0x1180080e0ee40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7625"             ,	   0x1180080e0ee48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7626"             ,	   0x1180080e0ee50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7627"             ,	   0x1180080e0ee58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7628"             ,	   0x1180080e0ee60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7629"             ,	   0x1180080e0ee68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7630"             ,	   0x1180080e0ee70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7631"             ,	   0x1180080e0ee78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7632"             ,	   0x1180080e0ee80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7633"             ,	   0x1180080e0ee88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7634"             ,	   0x1180080e0ee90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7635"             ,	   0x1180080e0ee98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7636"             ,	   0x1180080e0eea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7637"             ,	   0x1180080e0eea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7638"             ,	   0x1180080e0eeb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7639"             ,	   0x1180080e0eeb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7640"             ,	   0x1180080e0eec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7641"             ,	   0x1180080e0eec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7642"             ,	   0x1180080e0eed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7643"             ,	   0x1180080e0eed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7644"             ,	   0x1180080e0eee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7645"             ,	   0x1180080e0eee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7646"             ,	   0x1180080e0eef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7647"             ,	   0x1180080e0eef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7648"             ,	   0x1180080e0ef00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7649"             ,	   0x1180080e0ef08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7650"             ,	   0x1180080e0ef10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7651"             ,	   0x1180080e0ef18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7652"             ,	   0x1180080e0ef20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7653"             ,	   0x1180080e0ef28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7654"             ,	   0x1180080e0ef30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7655"             ,	   0x1180080e0ef38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7656"             ,	   0x1180080e0ef40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7657"             ,	   0x1180080e0ef48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7658"             ,	   0x1180080e0ef50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7659"             ,	   0x1180080e0ef58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7660"             ,	   0x1180080e0ef60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7661"             ,	   0x1180080e0ef68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7662"             ,	   0x1180080e0ef70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7663"             ,	   0x1180080e0ef78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7664"             ,	   0x1180080e0ef80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7665"             ,	   0x1180080e0ef88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7666"             ,	   0x1180080e0ef90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7667"             ,	   0x1180080e0ef98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7668"             ,	   0x1180080e0efa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7669"             ,	   0x1180080e0efa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7670"             ,	   0x1180080e0efb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7671"             ,	   0x1180080e0efb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7672"             ,	   0x1180080e0efc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7673"             ,	   0x1180080e0efc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7674"             ,	   0x1180080e0efd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7675"             ,	   0x1180080e0efd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7676"             ,	   0x1180080e0efe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7677"             ,	   0x1180080e0efe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7678"             ,	   0x1180080e0eff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7679"             ,	   0x1180080e0eff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7680"             ,	   0x1180080e0f000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7681"             ,	   0x1180080e0f008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7682"             ,	   0x1180080e0f010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7683"             ,	   0x1180080e0f018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7684"             ,	   0x1180080e0f020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7685"             ,	   0x1180080e0f028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7686"             ,	   0x1180080e0f030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7687"             ,	   0x1180080e0f038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7688"             ,	   0x1180080e0f040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7689"             ,	   0x1180080e0f048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7690"             ,	   0x1180080e0f050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7691"             ,	   0x1180080e0f058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7692"             ,	   0x1180080e0f060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7693"             ,	   0x1180080e0f068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7694"             ,	   0x1180080e0f070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7695"             ,	   0x1180080e0f078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7696"             ,	   0x1180080e0f080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7697"             ,	   0x1180080e0f088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7698"             ,	   0x1180080e0f090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7699"             ,	   0x1180080e0f098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7700"             ,	   0x1180080e0f0a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7701"             ,	   0x1180080e0f0a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7702"             ,	   0x1180080e0f0b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7703"             ,	   0x1180080e0f0b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7704"             ,	   0x1180080e0f0c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7705"             ,	   0x1180080e0f0c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7706"             ,	   0x1180080e0f0d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7707"             ,	   0x1180080e0f0d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7708"             ,	   0x1180080e0f0e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7709"             ,	   0x1180080e0f0e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7710"             ,	   0x1180080e0f0f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7711"             ,	   0x1180080e0f0f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7712"             ,	   0x1180080e0f100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7713"             ,	   0x1180080e0f108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7714"             ,	   0x1180080e0f110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7715"             ,	   0x1180080e0f118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7716"             ,	   0x1180080e0f120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7717"             ,	   0x1180080e0f128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7718"             ,	   0x1180080e0f130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7719"             ,	   0x1180080e0f138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7720"             ,	   0x1180080e0f140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7721"             ,	   0x1180080e0f148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7722"             ,	   0x1180080e0f150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7723"             ,	   0x1180080e0f158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7724"             ,	   0x1180080e0f160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7725"             ,	   0x1180080e0f168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7726"             ,	   0x1180080e0f170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7727"             ,	   0x1180080e0f178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7728"             ,	   0x1180080e0f180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7729"             ,	   0x1180080e0f188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7730"             ,	   0x1180080e0f190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7731"             ,	   0x1180080e0f198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7732"             ,	   0x1180080e0f1a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7733"             ,	   0x1180080e0f1a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7734"             ,	   0x1180080e0f1b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7735"             ,	   0x1180080e0f1b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7736"             ,	   0x1180080e0f1c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7737"             ,	   0x1180080e0f1c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7738"             ,	   0x1180080e0f1d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7739"             ,	   0x1180080e0f1d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7740"             ,	   0x1180080e0f1e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7741"             ,	   0x1180080e0f1e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7742"             ,	   0x1180080e0f1f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7743"             ,	   0x1180080e0f1f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7744"             ,	   0x1180080e0f200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7745"             ,	   0x1180080e0f208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7746"             ,	   0x1180080e0f210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7747"             ,	   0x1180080e0f218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7748"             ,	   0x1180080e0f220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7749"             ,	   0x1180080e0f228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7750"             ,	   0x1180080e0f230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7751"             ,	   0x1180080e0f238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7752"             ,	   0x1180080e0f240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7753"             ,	   0x1180080e0f248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7754"             ,	   0x1180080e0f250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7755"             ,	   0x1180080e0f258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7756"             ,	   0x1180080e0f260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7757"             ,	   0x1180080e0f268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7758"             ,	   0x1180080e0f270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7759"             ,	   0x1180080e0f278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7760"             ,	   0x1180080e0f280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7761"             ,	   0x1180080e0f288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7762"             ,	   0x1180080e0f290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7763"             ,	   0x1180080e0f298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7764"             ,	   0x1180080e0f2a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7765"             ,	   0x1180080e0f2a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7766"             ,	   0x1180080e0f2b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7767"             ,	   0x1180080e0f2b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7768"             ,	   0x1180080e0f2c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7769"             ,	   0x1180080e0f2c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7770"             ,	   0x1180080e0f2d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7771"             ,	   0x1180080e0f2d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7772"             ,	   0x1180080e0f2e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7773"             ,	   0x1180080e0f2e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7774"             ,	   0x1180080e0f2f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7775"             ,	   0x1180080e0f2f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7776"             ,	   0x1180080e0f300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7777"             ,	   0x1180080e0f308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7778"             ,	   0x1180080e0f310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7779"             ,	   0x1180080e0f318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7780"             ,	   0x1180080e0f320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7781"             ,	   0x1180080e0f328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7782"             ,	   0x1180080e0f330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7783"             ,	   0x1180080e0f338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7784"             ,	   0x1180080e0f340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7785"             ,	   0x1180080e0f348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7786"             ,	   0x1180080e0f350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7787"             ,	   0x1180080e0f358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7788"             ,	   0x1180080e0f360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7789"             ,	   0x1180080e0f368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7790"             ,	   0x1180080e0f370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7791"             ,	   0x1180080e0f378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7792"             ,	   0x1180080e0f380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7793"             ,	   0x1180080e0f388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7794"             ,	   0x1180080e0f390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7795"             ,	   0x1180080e0f398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7796"             ,	   0x1180080e0f3a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7797"             ,	   0x1180080e0f3a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7798"             ,	   0x1180080e0f3b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7799"             ,	   0x1180080e0f3b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7800"             ,	   0x1180080e0f3c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7801"             ,	   0x1180080e0f3c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7802"             ,	   0x1180080e0f3d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7803"             ,	   0x1180080e0f3d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7804"             ,	   0x1180080e0f3e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7805"             ,	   0x1180080e0f3e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7806"             ,	   0x1180080e0f3f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7807"             ,	   0x1180080e0f3f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7808"             ,	   0x1180080e0f400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7809"             ,	   0x1180080e0f408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7810"             ,	   0x1180080e0f410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7811"             ,	   0x1180080e0f418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7812"             ,	   0x1180080e0f420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7813"             ,	   0x1180080e0f428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7814"             ,	   0x1180080e0f430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7815"             ,	   0x1180080e0f438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7816"             ,	   0x1180080e0f440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7817"             ,	   0x1180080e0f448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7818"             ,	   0x1180080e0f450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7819"             ,	   0x1180080e0f458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7820"             ,	   0x1180080e0f460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7821"             ,	   0x1180080e0f468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7822"             ,	   0x1180080e0f470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7823"             ,	   0x1180080e0f478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7824"             ,	   0x1180080e0f480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7825"             ,	   0x1180080e0f488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7826"             ,	   0x1180080e0f490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7827"             ,	   0x1180080e0f498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7828"             ,	   0x1180080e0f4a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7829"             ,	   0x1180080e0f4a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7830"             ,	   0x1180080e0f4b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7831"             ,	   0x1180080e0f4b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7832"             ,	   0x1180080e0f4c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7833"             ,	   0x1180080e0f4c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7834"             ,	   0x1180080e0f4d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7835"             ,	   0x1180080e0f4d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7836"             ,	   0x1180080e0f4e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7837"             ,	   0x1180080e0f4e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7838"             ,	   0x1180080e0f4f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7839"             ,	   0x1180080e0f4f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7840"             ,	   0x1180080e0f500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7841"             ,	   0x1180080e0f508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7842"             ,	   0x1180080e0f510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7843"             ,	   0x1180080e0f518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7844"             ,	   0x1180080e0f520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7845"             ,	   0x1180080e0f528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7846"             ,	   0x1180080e0f530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7847"             ,	   0x1180080e0f538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7848"             ,	   0x1180080e0f540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7849"             ,	   0x1180080e0f548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7850"             ,	   0x1180080e0f550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7851"             ,	   0x1180080e0f558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7852"             ,	   0x1180080e0f560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7853"             ,	   0x1180080e0f568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7854"             ,	   0x1180080e0f570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7855"             ,	   0x1180080e0f578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7856"             ,	   0x1180080e0f580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7857"             ,	   0x1180080e0f588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7858"             ,	   0x1180080e0f590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7859"             ,	   0x1180080e0f598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7860"             ,	   0x1180080e0f5a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7861"             ,	   0x1180080e0f5a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7862"             ,	   0x1180080e0f5b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7863"             ,	   0x1180080e0f5b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7864"             ,	   0x1180080e0f5c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7865"             ,	   0x1180080e0f5c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7866"             ,	   0x1180080e0f5d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7867"             ,	   0x1180080e0f5d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7868"             ,	   0x1180080e0f5e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7869"             ,	   0x1180080e0f5e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7870"             ,	   0x1180080e0f5f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7871"             ,	   0x1180080e0f5f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7872"             ,	   0x1180080e0f600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7873"             ,	   0x1180080e0f608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7874"             ,	   0x1180080e0f610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7875"             ,	   0x1180080e0f618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7876"             ,	   0x1180080e0f620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7877"             ,	   0x1180080e0f628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7878"             ,	   0x1180080e0f630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7879"             ,	   0x1180080e0f638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7880"             ,	   0x1180080e0f640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7881"             ,	   0x1180080e0f648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7882"             ,	   0x1180080e0f650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7883"             ,	   0x1180080e0f658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7884"             ,	   0x1180080e0f660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7885"             ,	   0x1180080e0f668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7886"             ,	   0x1180080e0f670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7887"             ,	   0x1180080e0f678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7888"             ,	   0x1180080e0f680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7889"             ,	   0x1180080e0f688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7890"             ,	   0x1180080e0f690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7891"             ,	   0x1180080e0f698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7892"             ,	   0x1180080e0f6a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7893"             ,	   0x1180080e0f6a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7894"             ,	   0x1180080e0f6b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7895"             ,	   0x1180080e0f6b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7896"             ,	   0x1180080e0f6c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7897"             ,	   0x1180080e0f6c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7898"             ,	   0x1180080e0f6d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7899"             ,	   0x1180080e0f6d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7900"             ,	   0x1180080e0f6e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7901"             ,	   0x1180080e0f6e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7902"             ,	   0x1180080e0f6f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7903"             ,	   0x1180080e0f6f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7904"             ,	   0x1180080e0f700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7905"             ,	   0x1180080e0f708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7906"             ,	   0x1180080e0f710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7907"             ,	   0x1180080e0f718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7908"             ,	   0x1180080e0f720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7909"             ,	   0x1180080e0f728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7910"             ,	   0x1180080e0f730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7911"             ,	   0x1180080e0f738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7912"             ,	   0x1180080e0f740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7913"             ,	   0x1180080e0f748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7914"             ,	   0x1180080e0f750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7915"             ,	   0x1180080e0f758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7916"             ,	   0x1180080e0f760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7917"             ,	   0x1180080e0f768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7918"             ,	   0x1180080e0f770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7919"             ,	   0x1180080e0f778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7920"             ,	   0x1180080e0f780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7921"             ,	   0x1180080e0f788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7922"             ,	   0x1180080e0f790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7923"             ,	   0x1180080e0f798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7924"             ,	   0x1180080e0f7a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7925"             ,	   0x1180080e0f7a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7926"             ,	   0x1180080e0f7b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7927"             ,	   0x1180080e0f7b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7928"             ,	   0x1180080e0f7c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7929"             ,	   0x1180080e0f7c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7930"             ,	   0x1180080e0f7d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7931"             ,	   0x1180080e0f7d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7932"             ,	   0x1180080e0f7e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7933"             ,	   0x1180080e0f7e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7934"             ,	   0x1180080e0f7f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7935"             ,	   0x1180080e0f7f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7936"             ,	   0x1180080e0f800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7937"             ,	   0x1180080e0f808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7938"             ,	   0x1180080e0f810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7939"             ,	   0x1180080e0f818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7940"             ,	   0x1180080e0f820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7941"             ,	   0x1180080e0f828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7942"             ,	   0x1180080e0f830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7943"             ,	   0x1180080e0f838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7944"             ,	   0x1180080e0f840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7945"             ,	   0x1180080e0f848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7946"             ,	   0x1180080e0f850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7947"             ,	   0x1180080e0f858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7948"             ,	   0x1180080e0f860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7949"             ,	   0x1180080e0f868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7950"             ,	   0x1180080e0f870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7951"             ,	   0x1180080e0f878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7952"             ,	   0x1180080e0f880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7953"             ,	   0x1180080e0f888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7954"             ,	   0x1180080e0f890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7955"             ,	   0x1180080e0f898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7956"             ,	   0x1180080e0f8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7957"             ,	   0x1180080e0f8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7958"             ,	   0x1180080e0f8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7959"             ,	   0x1180080e0f8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7960"             ,	   0x1180080e0f8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7961"             ,	   0x1180080e0f8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7962"             ,	   0x1180080e0f8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7963"             ,	   0x1180080e0f8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7964"             ,	   0x1180080e0f8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7965"             ,	   0x1180080e0f8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7966"             ,	   0x1180080e0f8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7967"             ,	   0x1180080e0f8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7968"             ,	   0x1180080e0f900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7969"             ,	   0x1180080e0f908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7970"             ,	   0x1180080e0f910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7971"             ,	   0x1180080e0f918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7972"             ,	   0x1180080e0f920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7973"             ,	   0x1180080e0f928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7974"             ,	   0x1180080e0f930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7975"             ,	   0x1180080e0f938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7976"             ,	   0x1180080e0f940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7977"             ,	   0x1180080e0f948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7978"             ,	   0x1180080e0f950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7979"             ,	   0x1180080e0f958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7980"             ,	   0x1180080e0f960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7981"             ,	   0x1180080e0f968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7982"             ,	   0x1180080e0f970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7983"             ,	   0x1180080e0f978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7984"             ,	   0x1180080e0f980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7985"             ,	   0x1180080e0f988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7986"             ,	   0x1180080e0f990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7987"             ,	   0x1180080e0f998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7988"             ,	   0x1180080e0f9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7989"             ,	   0x1180080e0f9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7990"             ,	   0x1180080e0f9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7991"             ,	   0x1180080e0f9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7992"             ,	   0x1180080e0f9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7993"             ,	   0x1180080e0f9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7994"             ,	   0x1180080e0f9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7995"             ,	   0x1180080e0f9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7996"             ,	   0x1180080e0f9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7997"             ,	   0x1180080e0f9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7998"             ,	   0x1180080e0f9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP7999"             ,	   0x1180080e0f9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8000"             ,	   0x1180080e0fa00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8001"             ,	   0x1180080e0fa08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8002"             ,	   0x1180080e0fa10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8003"             ,	   0x1180080e0fa18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8004"             ,	   0x1180080e0fa20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8005"             ,	   0x1180080e0fa28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8006"             ,	   0x1180080e0fa30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8007"             ,	   0x1180080e0fa38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8008"             ,	   0x1180080e0fa40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8009"             ,	   0x1180080e0fa48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8010"             ,	   0x1180080e0fa50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8011"             ,	   0x1180080e0fa58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8012"             ,	   0x1180080e0fa60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8013"             ,	   0x1180080e0fa68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8014"             ,	   0x1180080e0fa70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8015"             ,	   0x1180080e0fa78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8016"             ,	   0x1180080e0fa80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8017"             ,	   0x1180080e0fa88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8018"             ,	   0x1180080e0fa90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8019"             ,	   0x1180080e0fa98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8020"             ,	   0x1180080e0faa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8021"             ,	   0x1180080e0faa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8022"             ,	   0x1180080e0fab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8023"             ,	   0x1180080e0fab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8024"             ,	   0x1180080e0fac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8025"             ,	   0x1180080e0fac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8026"             ,	   0x1180080e0fad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8027"             ,	   0x1180080e0fad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8028"             ,	   0x1180080e0fae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8029"             ,	   0x1180080e0fae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8030"             ,	   0x1180080e0faf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8031"             ,	   0x1180080e0faf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8032"             ,	   0x1180080e0fb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8033"             ,	   0x1180080e0fb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8034"             ,	   0x1180080e0fb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8035"             ,	   0x1180080e0fb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8036"             ,	   0x1180080e0fb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8037"             ,	   0x1180080e0fb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8038"             ,	   0x1180080e0fb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8039"             ,	   0x1180080e0fb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8040"             ,	   0x1180080e0fb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8041"             ,	   0x1180080e0fb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8042"             ,	   0x1180080e0fb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8043"             ,	   0x1180080e0fb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8044"             ,	   0x1180080e0fb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8045"             ,	   0x1180080e0fb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8046"             ,	   0x1180080e0fb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8047"             ,	   0x1180080e0fb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8048"             ,	   0x1180080e0fb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8049"             ,	   0x1180080e0fb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8050"             ,	   0x1180080e0fb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8051"             ,	   0x1180080e0fb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8052"             ,	   0x1180080e0fba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8053"             ,	   0x1180080e0fba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8054"             ,	   0x1180080e0fbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8055"             ,	   0x1180080e0fbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8056"             ,	   0x1180080e0fbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8057"             ,	   0x1180080e0fbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8058"             ,	   0x1180080e0fbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8059"             ,	   0x1180080e0fbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8060"             ,	   0x1180080e0fbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8061"             ,	   0x1180080e0fbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8062"             ,	   0x1180080e0fbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8063"             ,	   0x1180080e0fbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8064"             ,	   0x1180080e0fc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8065"             ,	   0x1180080e0fc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8066"             ,	   0x1180080e0fc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8067"             ,	   0x1180080e0fc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8068"             ,	   0x1180080e0fc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8069"             ,	   0x1180080e0fc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8070"             ,	   0x1180080e0fc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8071"             ,	   0x1180080e0fc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8072"             ,	   0x1180080e0fc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8073"             ,	   0x1180080e0fc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8074"             ,	   0x1180080e0fc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8075"             ,	   0x1180080e0fc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8076"             ,	   0x1180080e0fc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8077"             ,	   0x1180080e0fc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8078"             ,	   0x1180080e0fc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8079"             ,	   0x1180080e0fc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8080"             ,	   0x1180080e0fc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8081"             ,	   0x1180080e0fc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8082"             ,	   0x1180080e0fc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8083"             ,	   0x1180080e0fc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8084"             ,	   0x1180080e0fca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8085"             ,	   0x1180080e0fca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8086"             ,	   0x1180080e0fcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8087"             ,	   0x1180080e0fcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8088"             ,	   0x1180080e0fcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8089"             ,	   0x1180080e0fcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8090"             ,	   0x1180080e0fcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8091"             ,	   0x1180080e0fcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8092"             ,	   0x1180080e0fce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8093"             ,	   0x1180080e0fce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8094"             ,	   0x1180080e0fcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8095"             ,	   0x1180080e0fcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8096"             ,	   0x1180080e0fd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8097"             ,	   0x1180080e0fd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8098"             ,	   0x1180080e0fd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8099"             ,	   0x1180080e0fd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8100"             ,	   0x1180080e0fd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8101"             ,	   0x1180080e0fd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8102"             ,	   0x1180080e0fd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8103"             ,	   0x1180080e0fd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8104"             ,	   0x1180080e0fd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8105"             ,	   0x1180080e0fd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8106"             ,	   0x1180080e0fd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8107"             ,	   0x1180080e0fd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8108"             ,	   0x1180080e0fd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8109"             ,	   0x1180080e0fd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8110"             ,	   0x1180080e0fd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8111"             ,	   0x1180080e0fd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8112"             ,	   0x1180080e0fd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8113"             ,	   0x1180080e0fd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8114"             ,	   0x1180080e0fd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8115"             ,	   0x1180080e0fd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8116"             ,	   0x1180080e0fda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8117"             ,	   0x1180080e0fda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8118"             ,	   0x1180080e0fdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8119"             ,	   0x1180080e0fdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8120"             ,	   0x1180080e0fdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8121"             ,	   0x1180080e0fdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8122"             ,	   0x1180080e0fdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8123"             ,	   0x1180080e0fdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8124"             ,	   0x1180080e0fde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8125"             ,	   0x1180080e0fde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8126"             ,	   0x1180080e0fdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8127"             ,	   0x1180080e0fdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8128"             ,	   0x1180080e0fe00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8129"             ,	   0x1180080e0fe08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8130"             ,	   0x1180080e0fe10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8131"             ,	   0x1180080e0fe18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8132"             ,	   0x1180080e0fe20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8133"             ,	   0x1180080e0fe28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8134"             ,	   0x1180080e0fe30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8135"             ,	   0x1180080e0fe38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8136"             ,	   0x1180080e0fe40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8137"             ,	   0x1180080e0fe48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8138"             ,	   0x1180080e0fe50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8139"             ,	   0x1180080e0fe58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8140"             ,	   0x1180080e0fe60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8141"             ,	   0x1180080e0fe68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8142"             ,	   0x1180080e0fe70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8143"             ,	   0x1180080e0fe78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8144"             ,	   0x1180080e0fe80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8145"             ,	   0x1180080e0fe88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8146"             ,	   0x1180080e0fe90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8147"             ,	   0x1180080e0fe98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8148"             ,	   0x1180080e0fea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8149"             ,	   0x1180080e0fea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8150"             ,	   0x1180080e0feb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8151"             ,	   0x1180080e0feb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8152"             ,	   0x1180080e0fec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8153"             ,	   0x1180080e0fec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8154"             ,	   0x1180080e0fed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8155"             ,	   0x1180080e0fed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8156"             ,	   0x1180080e0fee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8157"             ,	   0x1180080e0fee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8158"             ,	   0x1180080e0fef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8159"             ,	   0x1180080e0fef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8160"             ,	   0x1180080e0ff00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8161"             ,	   0x1180080e0ff08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8162"             ,	   0x1180080e0ff10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8163"             ,	   0x1180080e0ff18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8164"             ,	   0x1180080e0ff20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8165"             ,	   0x1180080e0ff28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8166"             ,	   0x1180080e0ff30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8167"             ,	   0x1180080e0ff38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8168"             ,	   0x1180080e0ff40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8169"             ,	   0x1180080e0ff48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8170"             ,	   0x1180080e0ff50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8171"             ,	   0x1180080e0ff58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8172"             ,	   0x1180080e0ff60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8173"             ,	   0x1180080e0ff68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8174"             ,	   0x1180080e0ff70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8175"             ,	   0x1180080e0ff78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8176"             ,	   0x1180080e0ff80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8177"             ,	   0x1180080e0ff88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8178"             ,	   0x1180080e0ff90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8179"             ,	   0x1180080e0ff98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8180"             ,	   0x1180080e0ffa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8181"             ,	   0x1180080e0ffa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8182"             ,	   0x1180080e0ffb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8183"             ,	   0x1180080e0ffb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8184"             ,	   0x1180080e0ffc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8185"             ,	   0x1180080e0ffc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8186"             ,	   0x1180080e0ffd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8187"             ,	   0x1180080e0ffd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8188"             ,	   0x1180080e0ffe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8189"             ,	   0x1180080e0ffe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8190"             ,	   0x1180080e0fff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_DUT_MAP8191"             ,	   0x1180080e0fff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"L2C_ERR_TDT0"                ,	   0x1180080a007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	614},
+	{"L2C_ERR_TDT1"                ,	   0x1180080a407e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	614},
+	{"L2C_ERR_TDT2"                ,	   0x1180080a807e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	614},
+	{"L2C_ERR_TDT3"                ,	   0x1180080ac07e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	614},
+	{"L2C_ERR_TTG0"                ,	   0x1180080a007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	615},
+	{"L2C_ERR_TTG1"                ,	   0x1180080a407e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	615},
+	{"L2C_ERR_TTG2"                ,	   0x1180080a807e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	615},
+	{"L2C_ERR_TTG3"                ,	   0x1180080ac07e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	615},
+	{"L2C_ERR_VBF0"                ,	   0x1180080c007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"L2C_ERR_VBF1"                ,	   0x1180080c407f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"L2C_ERR_VBF2"                ,	   0x1180080c807f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"L2C_ERR_VBF3"                ,	   0x1180080cc07f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"L2C_ERR_XMC"                 ,	   0x11800808007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"L2C_INT_ENA"                 ,	   0x1180080800020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
+	{"L2C_INT_REG"                 ,	   0x1180080800018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"L2C_IOC0_PFC"                ,	   0x1180080800420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"L2C_IOR0_PFC"                ,	   0x1180080800428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"L2C_QOS_IOB0"                ,	   0x1180080880200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"L2C_QOS_IOB1"                ,	   0x1180080880208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"L2C_QOS_PP0"                 ,	   0x1180080880000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP1"                 ,	   0x1180080880008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP2"                 ,	   0x1180080880010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP3"                 ,	   0x1180080880018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP4"                 ,	   0x1180080880020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP5"                 ,	   0x1180080880028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP6"                 ,	   0x1180080880030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP7"                 ,	   0x1180080880038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP8"                 ,	   0x1180080880040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP9"                 ,	   0x1180080880048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP10"                ,	   0x1180080880050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP11"                ,	   0x1180080880058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP12"                ,	   0x1180080880060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP13"                ,	   0x1180080880068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP14"                ,	   0x1180080880070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP15"                ,	   0x1180080880078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP16"                ,	   0x1180080880080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP17"                ,	   0x1180080880088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP18"                ,	   0x1180080880090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP19"                ,	   0x1180080880098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP20"                ,	   0x11800808800a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP21"                ,	   0x11800808800a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP22"                ,	   0x11800808800b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP23"                ,	   0x11800808800b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP24"                ,	   0x11800808800c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP25"                ,	   0x11800808800c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP26"                ,	   0x11800808800d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP27"                ,	   0x11800808800d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP28"                ,	   0x11800808800e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP29"                ,	   0x11800808800e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP30"                ,	   0x11800808800f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_PP31"                ,	   0x11800808800f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"L2C_QOS_WGT"                 ,	   0x1180080800008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"L2C_RSC0_PFC"                ,	   0x1180080800410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"L2C_RSC1_PFC"                ,	   0x1180080800450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"L2C_RSC2_PFC"                ,	   0x1180080800490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"L2C_RSC3_PFC"                ,	   0x11800808004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"L2C_RSD0_PFC"                ,	   0x1180080800418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"L2C_RSD1_PFC"                ,	   0x1180080800458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"L2C_RSD2_PFC"                ,	   0x1180080800498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"L2C_RSD3_PFC"                ,	   0x11800808004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"L2C_TAD0_ECC0"               ,	   0x1180080a00018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"L2C_TAD1_ECC0"               ,	   0x1180080a40018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"L2C_TAD2_ECC0"               ,	   0x1180080a80018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"L2C_TAD3_ECC0"               ,	   0x1180080ac0018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"L2C_TAD0_ECC1"               ,	   0x1180080a00020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"L2C_TAD1_ECC1"               ,	   0x1180080a40020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"L2C_TAD2_ECC1"               ,	   0x1180080a80020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"L2C_TAD3_ECC1"               ,	   0x1180080ac0020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"L2C_TAD0_IEN"                ,	   0x1180080a00000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"L2C_TAD1_IEN"                ,	   0x1180080a40000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"L2C_TAD2_IEN"                ,	   0x1180080a80000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"L2C_TAD3_IEN"                ,	   0x1180080ac0000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"L2C_TAD0_INT"                ,	   0x1180080a00028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"L2C_TAD1_INT"                ,	   0x1180080a40028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"L2C_TAD2_INT"                ,	   0x1180080a80028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"L2C_TAD3_INT"                ,	   0x1180080ac0028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"L2C_TAD0_PFC0"               ,	   0x1180080a00400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"L2C_TAD1_PFC0"               ,	   0x1180080a40400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"L2C_TAD2_PFC0"               ,	   0x1180080a80400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"L2C_TAD3_PFC0"               ,	   0x1180080ac0400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"L2C_TAD0_PFC1"               ,	   0x1180080a00408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"L2C_TAD1_PFC1"               ,	   0x1180080a40408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"L2C_TAD2_PFC1"               ,	   0x1180080a80408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"L2C_TAD3_PFC1"               ,	   0x1180080ac0408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"L2C_TAD0_PFC2"               ,	   0x1180080a00410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
+	{"L2C_TAD1_PFC2"               ,	   0x1180080a40410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
+	{"L2C_TAD2_PFC2"               ,	   0x1180080a80410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
+	{"L2C_TAD3_PFC2"               ,	   0x1180080ac0410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
+	{"L2C_TAD0_PFC3"               ,	   0x1180080a00418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
+	{"L2C_TAD1_PFC3"               ,	   0x1180080a40418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
+	{"L2C_TAD2_PFC3"               ,	   0x1180080a80418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
+	{"L2C_TAD3_PFC3"               ,	   0x1180080ac0418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
+	{"L2C_TAD0_PRF"                ,	   0x1180080a00008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"L2C_TAD1_PRF"                ,	   0x1180080a40008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"L2C_TAD2_PRF"                ,	   0x1180080a80008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"L2C_TAD3_PRF"                ,	   0x1180080ac0008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"L2C_TAD0_TAG"                ,	   0x1180080a00010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_TAD1_TAG"                ,	   0x1180080a40010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_TAD2_TAG"                ,	   0x1180080a80010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_TAD3_TAG"                ,	   0x1180080ac0010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"L2C_VER_ID"                  ,	   0x11800808007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
+	{"L2C_VER_IOB"                 ,	   0x11800808007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"L2C_VER_MSC"                 ,	   0x11800808007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
+	{"L2C_VER_PP"                  ,	   0x11800808007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"L2C_VIRTID_IOB0"             ,	   0x11800808c0200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
+	{"L2C_VIRTID_IOB1"             ,	   0x11800808c0208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
+	{"L2C_VIRTID_PP0"              ,	   0x11800808c0000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP1"              ,	   0x11800808c0008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP2"              ,	   0x11800808c0010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP3"              ,	   0x11800808c0018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP4"              ,	   0x11800808c0020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP5"              ,	   0x11800808c0028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP6"              ,	   0x11800808c0030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP7"              ,	   0x11800808c0038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP8"              ,	   0x11800808c0040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP9"              ,	   0x11800808c0048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP10"             ,	   0x11800808c0050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP11"             ,	   0x11800808c0058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP12"             ,	   0x11800808c0060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP13"             ,	   0x11800808c0068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP14"             ,	   0x11800808c0070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP15"             ,	   0x11800808c0078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP16"             ,	   0x11800808c0080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP17"             ,	   0x11800808c0088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP18"             ,	   0x11800808c0090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP19"             ,	   0x11800808c0098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP20"             ,	   0x11800808c00a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP21"             ,	   0x11800808c00a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP22"             ,	   0x11800808c00b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP23"             ,	   0x11800808c00b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP24"             ,	   0x11800808c00c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP25"             ,	   0x11800808c00c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP26"             ,	   0x11800808c00d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP27"             ,	   0x11800808c00d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP28"             ,	   0x11800808c00e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP29"             ,	   0x11800808c00e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP30"             ,	   0x11800808c00f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VIRTID_PP31"             ,	   0x11800808c00f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"L2C_VRT_CTL"                 ,	   0x1180080800010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	643},
+	{"L2C_VRT_MEM0"                ,	   0x1180080900000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1"                ,	   0x1180080900008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM2"                ,	   0x1180080900010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM3"                ,	   0x1180080900018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM4"                ,	   0x1180080900020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM5"                ,	   0x1180080900028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM6"                ,	   0x1180080900030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM7"                ,	   0x1180080900038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM8"                ,	   0x1180080900040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM9"                ,	   0x1180080900048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM10"               ,	   0x1180080900050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM11"               ,	   0x1180080900058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM12"               ,	   0x1180080900060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM13"               ,	   0x1180080900068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM14"               ,	   0x1180080900070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM15"               ,	   0x1180080900078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM16"               ,	   0x1180080900080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM17"               ,	   0x1180080900088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM18"               ,	   0x1180080900090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM19"               ,	   0x1180080900098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM20"               ,	   0x11800809000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM21"               ,	   0x11800809000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM22"               ,	   0x11800809000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM23"               ,	   0x11800809000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM24"               ,	   0x11800809000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM25"               ,	   0x11800809000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM26"               ,	   0x11800809000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM27"               ,	   0x11800809000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM28"               ,	   0x11800809000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM29"               ,	   0x11800809000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM30"               ,	   0x11800809000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM31"               ,	   0x11800809000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM32"               ,	   0x1180080900100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM33"               ,	   0x1180080900108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM34"               ,	   0x1180080900110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM35"               ,	   0x1180080900118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM36"               ,	   0x1180080900120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM37"               ,	   0x1180080900128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM38"               ,	   0x1180080900130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM39"               ,	   0x1180080900138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM40"               ,	   0x1180080900140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM41"               ,	   0x1180080900148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM42"               ,	   0x1180080900150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM43"               ,	   0x1180080900158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM44"               ,	   0x1180080900160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM45"               ,	   0x1180080900168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM46"               ,	   0x1180080900170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM47"               ,	   0x1180080900178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM48"               ,	   0x1180080900180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM49"               ,	   0x1180080900188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM50"               ,	   0x1180080900190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM51"               ,	   0x1180080900198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM52"               ,	   0x11800809001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM53"               ,	   0x11800809001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM54"               ,	   0x11800809001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM55"               ,	   0x11800809001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM56"               ,	   0x11800809001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM57"               ,	   0x11800809001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM58"               ,	   0x11800809001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM59"               ,	   0x11800809001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM60"               ,	   0x11800809001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM61"               ,	   0x11800809001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM62"               ,	   0x11800809001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM63"               ,	   0x11800809001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM64"               ,	   0x1180080900200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM65"               ,	   0x1180080900208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM66"               ,	   0x1180080900210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM67"               ,	   0x1180080900218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM68"               ,	   0x1180080900220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM69"               ,	   0x1180080900228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM70"               ,	   0x1180080900230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM71"               ,	   0x1180080900238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM72"               ,	   0x1180080900240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM73"               ,	   0x1180080900248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM74"               ,	   0x1180080900250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM75"               ,	   0x1180080900258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM76"               ,	   0x1180080900260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM77"               ,	   0x1180080900268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM78"               ,	   0x1180080900270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM79"               ,	   0x1180080900278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM80"               ,	   0x1180080900280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM81"               ,	   0x1180080900288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM82"               ,	   0x1180080900290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM83"               ,	   0x1180080900298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM84"               ,	   0x11800809002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM85"               ,	   0x11800809002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM86"               ,	   0x11800809002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM87"               ,	   0x11800809002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM88"               ,	   0x11800809002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM89"               ,	   0x11800809002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM90"               ,	   0x11800809002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM91"               ,	   0x11800809002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM92"               ,	   0x11800809002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM93"               ,	   0x11800809002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM94"               ,	   0x11800809002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM95"               ,	   0x11800809002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM96"               ,	   0x1180080900300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM97"               ,	   0x1180080900308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM98"               ,	   0x1180080900310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM99"               ,	   0x1180080900318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM100"              ,	   0x1180080900320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM101"              ,	   0x1180080900328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM102"              ,	   0x1180080900330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM103"              ,	   0x1180080900338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM104"              ,	   0x1180080900340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM105"              ,	   0x1180080900348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM106"              ,	   0x1180080900350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM107"              ,	   0x1180080900358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM108"              ,	   0x1180080900360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM109"              ,	   0x1180080900368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM110"              ,	   0x1180080900370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM111"              ,	   0x1180080900378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM112"              ,	   0x1180080900380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM113"              ,	   0x1180080900388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM114"              ,	   0x1180080900390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM115"              ,	   0x1180080900398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM116"              ,	   0x11800809003a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM117"              ,	   0x11800809003a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM118"              ,	   0x11800809003b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM119"              ,	   0x11800809003b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM120"              ,	   0x11800809003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM121"              ,	   0x11800809003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM122"              ,	   0x11800809003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM123"              ,	   0x11800809003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM124"              ,	   0x11800809003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM125"              ,	   0x11800809003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM126"              ,	   0x11800809003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM127"              ,	   0x11800809003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM128"              ,	   0x1180080900400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM129"              ,	   0x1180080900408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM130"              ,	   0x1180080900410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM131"              ,	   0x1180080900418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM132"              ,	   0x1180080900420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM133"              ,	   0x1180080900428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM134"              ,	   0x1180080900430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM135"              ,	   0x1180080900438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM136"              ,	   0x1180080900440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM137"              ,	   0x1180080900448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM138"              ,	   0x1180080900450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM139"              ,	   0x1180080900458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM140"              ,	   0x1180080900460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM141"              ,	   0x1180080900468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM142"              ,	   0x1180080900470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM143"              ,	   0x1180080900478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM144"              ,	   0x1180080900480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM145"              ,	   0x1180080900488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM146"              ,	   0x1180080900490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM147"              ,	   0x1180080900498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM148"              ,	   0x11800809004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM149"              ,	   0x11800809004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM150"              ,	   0x11800809004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM151"              ,	   0x11800809004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM152"              ,	   0x11800809004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM153"              ,	   0x11800809004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM154"              ,	   0x11800809004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM155"              ,	   0x11800809004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM156"              ,	   0x11800809004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM157"              ,	   0x11800809004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM158"              ,	   0x11800809004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM159"              ,	   0x11800809004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM160"              ,	   0x1180080900500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM161"              ,	   0x1180080900508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM162"              ,	   0x1180080900510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM163"              ,	   0x1180080900518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM164"              ,	   0x1180080900520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM165"              ,	   0x1180080900528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM166"              ,	   0x1180080900530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM167"              ,	   0x1180080900538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM168"              ,	   0x1180080900540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM169"              ,	   0x1180080900548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM170"              ,	   0x1180080900550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM171"              ,	   0x1180080900558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM172"              ,	   0x1180080900560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM173"              ,	   0x1180080900568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM174"              ,	   0x1180080900570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM175"              ,	   0x1180080900578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM176"              ,	   0x1180080900580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM177"              ,	   0x1180080900588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM178"              ,	   0x1180080900590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM179"              ,	   0x1180080900598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM180"              ,	   0x11800809005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM181"              ,	   0x11800809005a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM182"              ,	   0x11800809005b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM183"              ,	   0x11800809005b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM184"              ,	   0x11800809005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM185"              ,	   0x11800809005c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM186"              ,	   0x11800809005d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM187"              ,	   0x11800809005d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM188"              ,	   0x11800809005e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM189"              ,	   0x11800809005e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM190"              ,	   0x11800809005f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM191"              ,	   0x11800809005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM192"              ,	   0x1180080900600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM193"              ,	   0x1180080900608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM194"              ,	   0x1180080900610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM195"              ,	   0x1180080900618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM196"              ,	   0x1180080900620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM197"              ,	   0x1180080900628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM198"              ,	   0x1180080900630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM199"              ,	   0x1180080900638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM200"              ,	   0x1180080900640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM201"              ,	   0x1180080900648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM202"              ,	   0x1180080900650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM203"              ,	   0x1180080900658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM204"              ,	   0x1180080900660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM205"              ,	   0x1180080900668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM206"              ,	   0x1180080900670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM207"              ,	   0x1180080900678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM208"              ,	   0x1180080900680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM209"              ,	   0x1180080900688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM210"              ,	   0x1180080900690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM211"              ,	   0x1180080900698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM212"              ,	   0x11800809006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM213"              ,	   0x11800809006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM214"              ,	   0x11800809006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM215"              ,	   0x11800809006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM216"              ,	   0x11800809006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM217"              ,	   0x11800809006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM218"              ,	   0x11800809006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM219"              ,	   0x11800809006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM220"              ,	   0x11800809006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM221"              ,	   0x11800809006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM222"              ,	   0x11800809006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM223"              ,	   0x11800809006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM224"              ,	   0x1180080900700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM225"              ,	   0x1180080900708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM226"              ,	   0x1180080900710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM227"              ,	   0x1180080900718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM228"              ,	   0x1180080900720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM229"              ,	   0x1180080900728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM230"              ,	   0x1180080900730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM231"              ,	   0x1180080900738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM232"              ,	   0x1180080900740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM233"              ,	   0x1180080900748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM234"              ,	   0x1180080900750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM235"              ,	   0x1180080900758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM236"              ,	   0x1180080900760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM237"              ,	   0x1180080900768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM238"              ,	   0x1180080900770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM239"              ,	   0x1180080900778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM240"              ,	   0x1180080900780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM241"              ,	   0x1180080900788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM242"              ,	   0x1180080900790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM243"              ,	   0x1180080900798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM244"              ,	   0x11800809007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM245"              ,	   0x11800809007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM246"              ,	   0x11800809007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM247"              ,	   0x11800809007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM248"              ,	   0x11800809007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM249"              ,	   0x11800809007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM250"              ,	   0x11800809007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM251"              ,	   0x11800809007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM252"              ,	   0x11800809007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM253"              ,	   0x11800809007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM254"              ,	   0x11800809007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM255"              ,	   0x11800809007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM256"              ,	   0x1180080900800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM257"              ,	   0x1180080900808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM258"              ,	   0x1180080900810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM259"              ,	   0x1180080900818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM260"              ,	   0x1180080900820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM261"              ,	   0x1180080900828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM262"              ,	   0x1180080900830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM263"              ,	   0x1180080900838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM264"              ,	   0x1180080900840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM265"              ,	   0x1180080900848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM266"              ,	   0x1180080900850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM267"              ,	   0x1180080900858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM268"              ,	   0x1180080900860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM269"              ,	   0x1180080900868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM270"              ,	   0x1180080900870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM271"              ,	   0x1180080900878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM272"              ,	   0x1180080900880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM273"              ,	   0x1180080900888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM274"              ,	   0x1180080900890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM275"              ,	   0x1180080900898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM276"              ,	   0x11800809008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM277"              ,	   0x11800809008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM278"              ,	   0x11800809008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM279"              ,	   0x11800809008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM280"              ,	   0x11800809008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM281"              ,	   0x11800809008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM282"              ,	   0x11800809008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM283"              ,	   0x11800809008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM284"              ,	   0x11800809008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM285"              ,	   0x11800809008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM286"              ,	   0x11800809008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM287"              ,	   0x11800809008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM288"              ,	   0x1180080900900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM289"              ,	   0x1180080900908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM290"              ,	   0x1180080900910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM291"              ,	   0x1180080900918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM292"              ,	   0x1180080900920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM293"              ,	   0x1180080900928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM294"              ,	   0x1180080900930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM295"              ,	   0x1180080900938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM296"              ,	   0x1180080900940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM297"              ,	   0x1180080900948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM298"              ,	   0x1180080900950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM299"              ,	   0x1180080900958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM300"              ,	   0x1180080900960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM301"              ,	   0x1180080900968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM302"              ,	   0x1180080900970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM303"              ,	   0x1180080900978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM304"              ,	   0x1180080900980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM305"              ,	   0x1180080900988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM306"              ,	   0x1180080900990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM307"              ,	   0x1180080900998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM308"              ,	   0x11800809009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM309"              ,	   0x11800809009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM310"              ,	   0x11800809009b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM311"              ,	   0x11800809009b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM312"              ,	   0x11800809009c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM313"              ,	   0x11800809009c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM314"              ,	   0x11800809009d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM315"              ,	   0x11800809009d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM316"              ,	   0x11800809009e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM317"              ,	   0x11800809009e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM318"              ,	   0x11800809009f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM319"              ,	   0x11800809009f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM320"              ,	   0x1180080900a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM321"              ,	   0x1180080900a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM322"              ,	   0x1180080900a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM323"              ,	   0x1180080900a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM324"              ,	   0x1180080900a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM325"              ,	   0x1180080900a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM326"              ,	   0x1180080900a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM327"              ,	   0x1180080900a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM328"              ,	   0x1180080900a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM329"              ,	   0x1180080900a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM330"              ,	   0x1180080900a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM331"              ,	   0x1180080900a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM332"              ,	   0x1180080900a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM333"              ,	   0x1180080900a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM334"              ,	   0x1180080900a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM335"              ,	   0x1180080900a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM336"              ,	   0x1180080900a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM337"              ,	   0x1180080900a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM338"              ,	   0x1180080900a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM339"              ,	   0x1180080900a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM340"              ,	   0x1180080900aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM341"              ,	   0x1180080900aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM342"              ,	   0x1180080900ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM343"              ,	   0x1180080900ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM344"              ,	   0x1180080900ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM345"              ,	   0x1180080900ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM346"              ,	   0x1180080900ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM347"              ,	   0x1180080900ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM348"              ,	   0x1180080900ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM349"              ,	   0x1180080900ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM350"              ,	   0x1180080900af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM351"              ,	   0x1180080900af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM352"              ,	   0x1180080900b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM353"              ,	   0x1180080900b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM354"              ,	   0x1180080900b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM355"              ,	   0x1180080900b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM356"              ,	   0x1180080900b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM357"              ,	   0x1180080900b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM358"              ,	   0x1180080900b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM359"              ,	   0x1180080900b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM360"              ,	   0x1180080900b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM361"              ,	   0x1180080900b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM362"              ,	   0x1180080900b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM363"              ,	   0x1180080900b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM364"              ,	   0x1180080900b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM365"              ,	   0x1180080900b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM366"              ,	   0x1180080900b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM367"              ,	   0x1180080900b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM368"              ,	   0x1180080900b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM369"              ,	   0x1180080900b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM370"              ,	   0x1180080900b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM371"              ,	   0x1180080900b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM372"              ,	   0x1180080900ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM373"              ,	   0x1180080900ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM374"              ,	   0x1180080900bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM375"              ,	   0x1180080900bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM376"              ,	   0x1180080900bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM377"              ,	   0x1180080900bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM378"              ,	   0x1180080900bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM379"              ,	   0x1180080900bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM380"              ,	   0x1180080900be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM381"              ,	   0x1180080900be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM382"              ,	   0x1180080900bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM383"              ,	   0x1180080900bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM384"              ,	   0x1180080900c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM385"              ,	   0x1180080900c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM386"              ,	   0x1180080900c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM387"              ,	   0x1180080900c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM388"              ,	   0x1180080900c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM389"              ,	   0x1180080900c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM390"              ,	   0x1180080900c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM391"              ,	   0x1180080900c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM392"              ,	   0x1180080900c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM393"              ,	   0x1180080900c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM394"              ,	   0x1180080900c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM395"              ,	   0x1180080900c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM396"              ,	   0x1180080900c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM397"              ,	   0x1180080900c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM398"              ,	   0x1180080900c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM399"              ,	   0x1180080900c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM400"              ,	   0x1180080900c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM401"              ,	   0x1180080900c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM402"              ,	   0x1180080900c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM403"              ,	   0x1180080900c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM404"              ,	   0x1180080900ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM405"              ,	   0x1180080900ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM406"              ,	   0x1180080900cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM407"              ,	   0x1180080900cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM408"              ,	   0x1180080900cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM409"              ,	   0x1180080900cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM410"              ,	   0x1180080900cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM411"              ,	   0x1180080900cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM412"              ,	   0x1180080900ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM413"              ,	   0x1180080900ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM414"              ,	   0x1180080900cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM415"              ,	   0x1180080900cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM416"              ,	   0x1180080900d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM417"              ,	   0x1180080900d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM418"              ,	   0x1180080900d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM419"              ,	   0x1180080900d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM420"              ,	   0x1180080900d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM421"              ,	   0x1180080900d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM422"              ,	   0x1180080900d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM423"              ,	   0x1180080900d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM424"              ,	   0x1180080900d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM425"              ,	   0x1180080900d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM426"              ,	   0x1180080900d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM427"              ,	   0x1180080900d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM428"              ,	   0x1180080900d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM429"              ,	   0x1180080900d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM430"              ,	   0x1180080900d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM431"              ,	   0x1180080900d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM432"              ,	   0x1180080900d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM433"              ,	   0x1180080900d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM434"              ,	   0x1180080900d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM435"              ,	   0x1180080900d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM436"              ,	   0x1180080900da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM437"              ,	   0x1180080900da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM438"              ,	   0x1180080900db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM439"              ,	   0x1180080900db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM440"              ,	   0x1180080900dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM441"              ,	   0x1180080900dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM442"              ,	   0x1180080900dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM443"              ,	   0x1180080900dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM444"              ,	   0x1180080900de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM445"              ,	   0x1180080900de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM446"              ,	   0x1180080900df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM447"              ,	   0x1180080900df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM448"              ,	   0x1180080900e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM449"              ,	   0x1180080900e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM450"              ,	   0x1180080900e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM451"              ,	   0x1180080900e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM452"              ,	   0x1180080900e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM453"              ,	   0x1180080900e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM454"              ,	   0x1180080900e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM455"              ,	   0x1180080900e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM456"              ,	   0x1180080900e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM457"              ,	   0x1180080900e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM458"              ,	   0x1180080900e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM459"              ,	   0x1180080900e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM460"              ,	   0x1180080900e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM461"              ,	   0x1180080900e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM462"              ,	   0x1180080900e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM463"              ,	   0x1180080900e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM464"              ,	   0x1180080900e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM465"              ,	   0x1180080900e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM466"              ,	   0x1180080900e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM467"              ,	   0x1180080900e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM468"              ,	   0x1180080900ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM469"              ,	   0x1180080900ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM470"              ,	   0x1180080900eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM471"              ,	   0x1180080900eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM472"              ,	   0x1180080900ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM473"              ,	   0x1180080900ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM474"              ,	   0x1180080900ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM475"              ,	   0x1180080900ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM476"              ,	   0x1180080900ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM477"              ,	   0x1180080900ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM478"              ,	   0x1180080900ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM479"              ,	   0x1180080900ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM480"              ,	   0x1180080900f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM481"              ,	   0x1180080900f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM482"              ,	   0x1180080900f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM483"              ,	   0x1180080900f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM484"              ,	   0x1180080900f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM485"              ,	   0x1180080900f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM486"              ,	   0x1180080900f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM487"              ,	   0x1180080900f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM488"              ,	   0x1180080900f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM489"              ,	   0x1180080900f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM490"              ,	   0x1180080900f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM491"              ,	   0x1180080900f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM492"              ,	   0x1180080900f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM493"              ,	   0x1180080900f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM494"              ,	   0x1180080900f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM495"              ,	   0x1180080900f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM496"              ,	   0x1180080900f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM497"              ,	   0x1180080900f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM498"              ,	   0x1180080900f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM499"              ,	   0x1180080900f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM500"              ,	   0x1180080900fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM501"              ,	   0x1180080900fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM502"              ,	   0x1180080900fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM503"              ,	   0x1180080900fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM504"              ,	   0x1180080900fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM505"              ,	   0x1180080900fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM506"              ,	   0x1180080900fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM507"              ,	   0x1180080900fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM508"              ,	   0x1180080900fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM509"              ,	   0x1180080900fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM510"              ,	   0x1180080900ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM511"              ,	   0x1180080900ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM512"              ,	   0x1180080901000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM513"              ,	   0x1180080901008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM514"              ,	   0x1180080901010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM515"              ,	   0x1180080901018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM516"              ,	   0x1180080901020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM517"              ,	   0x1180080901028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM518"              ,	   0x1180080901030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM519"              ,	   0x1180080901038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM520"              ,	   0x1180080901040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM521"              ,	   0x1180080901048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM522"              ,	   0x1180080901050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM523"              ,	   0x1180080901058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM524"              ,	   0x1180080901060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM525"              ,	   0x1180080901068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM526"              ,	   0x1180080901070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM527"              ,	   0x1180080901078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM528"              ,	   0x1180080901080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM529"              ,	   0x1180080901088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM530"              ,	   0x1180080901090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM531"              ,	   0x1180080901098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM532"              ,	   0x11800809010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM533"              ,	   0x11800809010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM534"              ,	   0x11800809010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM535"              ,	   0x11800809010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM536"              ,	   0x11800809010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM537"              ,	   0x11800809010c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM538"              ,	   0x11800809010d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM539"              ,	   0x11800809010d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM540"              ,	   0x11800809010e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM541"              ,	   0x11800809010e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM542"              ,	   0x11800809010f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM543"              ,	   0x11800809010f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM544"              ,	   0x1180080901100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM545"              ,	   0x1180080901108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM546"              ,	   0x1180080901110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM547"              ,	   0x1180080901118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM548"              ,	   0x1180080901120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM549"              ,	   0x1180080901128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM550"              ,	   0x1180080901130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM551"              ,	   0x1180080901138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM552"              ,	   0x1180080901140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM553"              ,	   0x1180080901148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM554"              ,	   0x1180080901150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM555"              ,	   0x1180080901158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM556"              ,	   0x1180080901160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM557"              ,	   0x1180080901168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM558"              ,	   0x1180080901170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM559"              ,	   0x1180080901178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM560"              ,	   0x1180080901180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM561"              ,	   0x1180080901188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM562"              ,	   0x1180080901190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM563"              ,	   0x1180080901198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM564"              ,	   0x11800809011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM565"              ,	   0x11800809011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM566"              ,	   0x11800809011b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM567"              ,	   0x11800809011b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM568"              ,	   0x11800809011c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM569"              ,	   0x11800809011c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM570"              ,	   0x11800809011d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM571"              ,	   0x11800809011d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM572"              ,	   0x11800809011e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM573"              ,	   0x11800809011e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM574"              ,	   0x11800809011f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM575"              ,	   0x11800809011f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM576"              ,	   0x1180080901200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM577"              ,	   0x1180080901208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM578"              ,	   0x1180080901210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM579"              ,	   0x1180080901218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM580"              ,	   0x1180080901220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM581"              ,	   0x1180080901228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM582"              ,	   0x1180080901230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM583"              ,	   0x1180080901238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM584"              ,	   0x1180080901240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM585"              ,	   0x1180080901248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM586"              ,	   0x1180080901250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM587"              ,	   0x1180080901258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM588"              ,	   0x1180080901260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM589"              ,	   0x1180080901268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM590"              ,	   0x1180080901270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM591"              ,	   0x1180080901278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM592"              ,	   0x1180080901280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM593"              ,	   0x1180080901288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM594"              ,	   0x1180080901290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM595"              ,	   0x1180080901298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM596"              ,	   0x11800809012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM597"              ,	   0x11800809012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM598"              ,	   0x11800809012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM599"              ,	   0x11800809012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM600"              ,	   0x11800809012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM601"              ,	   0x11800809012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM602"              ,	   0x11800809012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM603"              ,	   0x11800809012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM604"              ,	   0x11800809012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM605"              ,	   0x11800809012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM606"              ,	   0x11800809012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM607"              ,	   0x11800809012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM608"              ,	   0x1180080901300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM609"              ,	   0x1180080901308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM610"              ,	   0x1180080901310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM611"              ,	   0x1180080901318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM612"              ,	   0x1180080901320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM613"              ,	   0x1180080901328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM614"              ,	   0x1180080901330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM615"              ,	   0x1180080901338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM616"              ,	   0x1180080901340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM617"              ,	   0x1180080901348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM618"              ,	   0x1180080901350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM619"              ,	   0x1180080901358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM620"              ,	   0x1180080901360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM621"              ,	   0x1180080901368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM622"              ,	   0x1180080901370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM623"              ,	   0x1180080901378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM624"              ,	   0x1180080901380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM625"              ,	   0x1180080901388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM626"              ,	   0x1180080901390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM627"              ,	   0x1180080901398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM628"              ,	   0x11800809013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM629"              ,	   0x11800809013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM630"              ,	   0x11800809013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM631"              ,	   0x11800809013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM632"              ,	   0x11800809013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM633"              ,	   0x11800809013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM634"              ,	   0x11800809013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM635"              ,	   0x11800809013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM636"              ,	   0x11800809013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM637"              ,	   0x11800809013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM638"              ,	   0x11800809013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM639"              ,	   0x11800809013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM640"              ,	   0x1180080901400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM641"              ,	   0x1180080901408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM642"              ,	   0x1180080901410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM643"              ,	   0x1180080901418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM644"              ,	   0x1180080901420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM645"              ,	   0x1180080901428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM646"              ,	   0x1180080901430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM647"              ,	   0x1180080901438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM648"              ,	   0x1180080901440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM649"              ,	   0x1180080901448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM650"              ,	   0x1180080901450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM651"              ,	   0x1180080901458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM652"              ,	   0x1180080901460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM653"              ,	   0x1180080901468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM654"              ,	   0x1180080901470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM655"              ,	   0x1180080901478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM656"              ,	   0x1180080901480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM657"              ,	   0x1180080901488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM658"              ,	   0x1180080901490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM659"              ,	   0x1180080901498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM660"              ,	   0x11800809014a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM661"              ,	   0x11800809014a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM662"              ,	   0x11800809014b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM663"              ,	   0x11800809014b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM664"              ,	   0x11800809014c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM665"              ,	   0x11800809014c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM666"              ,	   0x11800809014d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM667"              ,	   0x11800809014d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM668"              ,	   0x11800809014e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM669"              ,	   0x11800809014e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM670"              ,	   0x11800809014f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM671"              ,	   0x11800809014f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM672"              ,	   0x1180080901500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM673"              ,	   0x1180080901508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM674"              ,	   0x1180080901510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM675"              ,	   0x1180080901518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM676"              ,	   0x1180080901520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM677"              ,	   0x1180080901528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM678"              ,	   0x1180080901530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM679"              ,	   0x1180080901538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM680"              ,	   0x1180080901540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM681"              ,	   0x1180080901548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM682"              ,	   0x1180080901550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM683"              ,	   0x1180080901558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM684"              ,	   0x1180080901560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM685"              ,	   0x1180080901568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM686"              ,	   0x1180080901570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM687"              ,	   0x1180080901578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM688"              ,	   0x1180080901580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM689"              ,	   0x1180080901588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM690"              ,	   0x1180080901590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM691"              ,	   0x1180080901598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM692"              ,	   0x11800809015a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM693"              ,	   0x11800809015a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM694"              ,	   0x11800809015b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM695"              ,	   0x11800809015b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM696"              ,	   0x11800809015c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM697"              ,	   0x11800809015c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM698"              ,	   0x11800809015d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM699"              ,	   0x11800809015d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM700"              ,	   0x11800809015e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM701"              ,	   0x11800809015e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM702"              ,	   0x11800809015f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM703"              ,	   0x11800809015f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM704"              ,	   0x1180080901600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM705"              ,	   0x1180080901608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM706"              ,	   0x1180080901610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM707"              ,	   0x1180080901618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM708"              ,	   0x1180080901620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM709"              ,	   0x1180080901628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM710"              ,	   0x1180080901630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM711"              ,	   0x1180080901638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM712"              ,	   0x1180080901640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM713"              ,	   0x1180080901648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM714"              ,	   0x1180080901650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM715"              ,	   0x1180080901658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM716"              ,	   0x1180080901660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM717"              ,	   0x1180080901668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM718"              ,	   0x1180080901670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM719"              ,	   0x1180080901678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM720"              ,	   0x1180080901680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM721"              ,	   0x1180080901688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM722"              ,	   0x1180080901690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM723"              ,	   0x1180080901698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM724"              ,	   0x11800809016a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM725"              ,	   0x11800809016a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM726"              ,	   0x11800809016b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM727"              ,	   0x11800809016b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM728"              ,	   0x11800809016c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM729"              ,	   0x11800809016c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM730"              ,	   0x11800809016d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM731"              ,	   0x11800809016d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM732"              ,	   0x11800809016e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM733"              ,	   0x11800809016e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM734"              ,	   0x11800809016f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM735"              ,	   0x11800809016f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM736"              ,	   0x1180080901700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM737"              ,	   0x1180080901708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM738"              ,	   0x1180080901710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM739"              ,	   0x1180080901718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM740"              ,	   0x1180080901720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM741"              ,	   0x1180080901728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM742"              ,	   0x1180080901730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM743"              ,	   0x1180080901738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM744"              ,	   0x1180080901740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM745"              ,	   0x1180080901748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM746"              ,	   0x1180080901750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM747"              ,	   0x1180080901758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM748"              ,	   0x1180080901760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM749"              ,	   0x1180080901768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM750"              ,	   0x1180080901770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM751"              ,	   0x1180080901778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM752"              ,	   0x1180080901780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM753"              ,	   0x1180080901788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM754"              ,	   0x1180080901790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM755"              ,	   0x1180080901798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM756"              ,	   0x11800809017a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM757"              ,	   0x11800809017a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM758"              ,	   0x11800809017b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM759"              ,	   0x11800809017b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM760"              ,	   0x11800809017c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM761"              ,	   0x11800809017c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM762"              ,	   0x11800809017d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM763"              ,	   0x11800809017d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM764"              ,	   0x11800809017e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM765"              ,	   0x11800809017e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM766"              ,	   0x11800809017f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM767"              ,	   0x11800809017f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM768"              ,	   0x1180080901800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM769"              ,	   0x1180080901808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM770"              ,	   0x1180080901810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM771"              ,	   0x1180080901818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM772"              ,	   0x1180080901820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM773"              ,	   0x1180080901828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM774"              ,	   0x1180080901830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM775"              ,	   0x1180080901838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM776"              ,	   0x1180080901840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM777"              ,	   0x1180080901848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM778"              ,	   0x1180080901850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM779"              ,	   0x1180080901858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM780"              ,	   0x1180080901860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM781"              ,	   0x1180080901868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM782"              ,	   0x1180080901870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM783"              ,	   0x1180080901878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM784"              ,	   0x1180080901880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM785"              ,	   0x1180080901888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM786"              ,	   0x1180080901890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM787"              ,	   0x1180080901898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM788"              ,	   0x11800809018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM789"              ,	   0x11800809018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM790"              ,	   0x11800809018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM791"              ,	   0x11800809018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM792"              ,	   0x11800809018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM793"              ,	   0x11800809018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM794"              ,	   0x11800809018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM795"              ,	   0x11800809018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM796"              ,	   0x11800809018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM797"              ,	   0x11800809018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM798"              ,	   0x11800809018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM799"              ,	   0x11800809018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM800"              ,	   0x1180080901900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM801"              ,	   0x1180080901908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM802"              ,	   0x1180080901910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM803"              ,	   0x1180080901918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM804"              ,	   0x1180080901920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM805"              ,	   0x1180080901928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM806"              ,	   0x1180080901930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM807"              ,	   0x1180080901938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM808"              ,	   0x1180080901940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM809"              ,	   0x1180080901948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM810"              ,	   0x1180080901950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM811"              ,	   0x1180080901958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM812"              ,	   0x1180080901960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM813"              ,	   0x1180080901968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM814"              ,	   0x1180080901970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM815"              ,	   0x1180080901978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM816"              ,	   0x1180080901980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM817"              ,	   0x1180080901988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM818"              ,	   0x1180080901990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM819"              ,	   0x1180080901998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM820"              ,	   0x11800809019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM821"              ,	   0x11800809019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM822"              ,	   0x11800809019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM823"              ,	   0x11800809019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM824"              ,	   0x11800809019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM825"              ,	   0x11800809019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM826"              ,	   0x11800809019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM827"              ,	   0x11800809019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM828"              ,	   0x11800809019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM829"              ,	   0x11800809019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM830"              ,	   0x11800809019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM831"              ,	   0x11800809019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM832"              ,	   0x1180080901a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM833"              ,	   0x1180080901a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM834"              ,	   0x1180080901a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM835"              ,	   0x1180080901a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM836"              ,	   0x1180080901a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM837"              ,	   0x1180080901a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM838"              ,	   0x1180080901a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM839"              ,	   0x1180080901a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM840"              ,	   0x1180080901a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM841"              ,	   0x1180080901a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM842"              ,	   0x1180080901a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM843"              ,	   0x1180080901a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM844"              ,	   0x1180080901a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM845"              ,	   0x1180080901a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM846"              ,	   0x1180080901a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM847"              ,	   0x1180080901a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM848"              ,	   0x1180080901a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM849"              ,	   0x1180080901a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM850"              ,	   0x1180080901a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM851"              ,	   0x1180080901a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM852"              ,	   0x1180080901aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM853"              ,	   0x1180080901aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM854"              ,	   0x1180080901ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM855"              ,	   0x1180080901ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM856"              ,	   0x1180080901ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM857"              ,	   0x1180080901ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM858"              ,	   0x1180080901ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM859"              ,	   0x1180080901ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM860"              ,	   0x1180080901ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM861"              ,	   0x1180080901ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM862"              ,	   0x1180080901af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM863"              ,	   0x1180080901af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM864"              ,	   0x1180080901b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM865"              ,	   0x1180080901b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM866"              ,	   0x1180080901b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM867"              ,	   0x1180080901b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM868"              ,	   0x1180080901b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM869"              ,	   0x1180080901b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM870"              ,	   0x1180080901b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM871"              ,	   0x1180080901b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM872"              ,	   0x1180080901b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM873"              ,	   0x1180080901b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM874"              ,	   0x1180080901b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM875"              ,	   0x1180080901b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM876"              ,	   0x1180080901b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM877"              ,	   0x1180080901b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM878"              ,	   0x1180080901b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM879"              ,	   0x1180080901b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM880"              ,	   0x1180080901b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM881"              ,	   0x1180080901b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM882"              ,	   0x1180080901b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM883"              ,	   0x1180080901b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM884"              ,	   0x1180080901ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM885"              ,	   0x1180080901ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM886"              ,	   0x1180080901bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM887"              ,	   0x1180080901bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM888"              ,	   0x1180080901bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM889"              ,	   0x1180080901bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM890"              ,	   0x1180080901bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM891"              ,	   0x1180080901bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM892"              ,	   0x1180080901be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM893"              ,	   0x1180080901be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM894"              ,	   0x1180080901bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM895"              ,	   0x1180080901bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM896"              ,	   0x1180080901c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM897"              ,	   0x1180080901c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM898"              ,	   0x1180080901c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM899"              ,	   0x1180080901c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM900"              ,	   0x1180080901c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM901"              ,	   0x1180080901c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM902"              ,	   0x1180080901c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM903"              ,	   0x1180080901c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM904"              ,	   0x1180080901c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM905"              ,	   0x1180080901c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM906"              ,	   0x1180080901c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM907"              ,	   0x1180080901c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM908"              ,	   0x1180080901c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM909"              ,	   0x1180080901c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM910"              ,	   0x1180080901c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM911"              ,	   0x1180080901c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM912"              ,	   0x1180080901c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM913"              ,	   0x1180080901c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM914"              ,	   0x1180080901c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM915"              ,	   0x1180080901c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM916"              ,	   0x1180080901ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM917"              ,	   0x1180080901ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM918"              ,	   0x1180080901cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM919"              ,	   0x1180080901cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM920"              ,	   0x1180080901cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM921"              ,	   0x1180080901cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM922"              ,	   0x1180080901cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM923"              ,	   0x1180080901cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM924"              ,	   0x1180080901ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM925"              ,	   0x1180080901ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM926"              ,	   0x1180080901cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM927"              ,	   0x1180080901cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM928"              ,	   0x1180080901d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM929"              ,	   0x1180080901d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM930"              ,	   0x1180080901d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM931"              ,	   0x1180080901d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM932"              ,	   0x1180080901d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM933"              ,	   0x1180080901d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM934"              ,	   0x1180080901d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM935"              ,	   0x1180080901d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM936"              ,	   0x1180080901d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM937"              ,	   0x1180080901d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM938"              ,	   0x1180080901d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM939"              ,	   0x1180080901d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM940"              ,	   0x1180080901d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM941"              ,	   0x1180080901d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM942"              ,	   0x1180080901d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM943"              ,	   0x1180080901d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM944"              ,	   0x1180080901d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM945"              ,	   0x1180080901d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM946"              ,	   0x1180080901d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM947"              ,	   0x1180080901d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM948"              ,	   0x1180080901da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM949"              ,	   0x1180080901da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM950"              ,	   0x1180080901db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM951"              ,	   0x1180080901db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM952"              ,	   0x1180080901dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM953"              ,	   0x1180080901dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM954"              ,	   0x1180080901dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM955"              ,	   0x1180080901dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM956"              ,	   0x1180080901de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM957"              ,	   0x1180080901de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM958"              ,	   0x1180080901df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM959"              ,	   0x1180080901df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM960"              ,	   0x1180080901e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM961"              ,	   0x1180080901e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM962"              ,	   0x1180080901e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM963"              ,	   0x1180080901e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM964"              ,	   0x1180080901e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM965"              ,	   0x1180080901e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM966"              ,	   0x1180080901e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM967"              ,	   0x1180080901e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM968"              ,	   0x1180080901e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM969"              ,	   0x1180080901e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM970"              ,	   0x1180080901e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM971"              ,	   0x1180080901e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM972"              ,	   0x1180080901e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM973"              ,	   0x1180080901e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM974"              ,	   0x1180080901e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM975"              ,	   0x1180080901e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM976"              ,	   0x1180080901e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM977"              ,	   0x1180080901e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM978"              ,	   0x1180080901e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM979"              ,	   0x1180080901e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM980"              ,	   0x1180080901ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM981"              ,	   0x1180080901ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM982"              ,	   0x1180080901eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM983"              ,	   0x1180080901eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM984"              ,	   0x1180080901ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM985"              ,	   0x1180080901ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM986"              ,	   0x1180080901ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM987"              ,	   0x1180080901ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM988"              ,	   0x1180080901ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM989"              ,	   0x1180080901ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM990"              ,	   0x1180080901ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM991"              ,	   0x1180080901ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM992"              ,	   0x1180080901f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM993"              ,	   0x1180080901f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM994"              ,	   0x1180080901f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM995"              ,	   0x1180080901f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM996"              ,	   0x1180080901f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM997"              ,	   0x1180080901f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM998"              ,	   0x1180080901f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM999"              ,	   0x1180080901f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1000"             ,	   0x1180080901f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1001"             ,	   0x1180080901f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1002"             ,	   0x1180080901f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1003"             ,	   0x1180080901f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1004"             ,	   0x1180080901f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1005"             ,	   0x1180080901f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1006"             ,	   0x1180080901f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1007"             ,	   0x1180080901f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1008"             ,	   0x1180080901f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1009"             ,	   0x1180080901f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1010"             ,	   0x1180080901f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1011"             ,	   0x1180080901f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1012"             ,	   0x1180080901fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1013"             ,	   0x1180080901fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1014"             ,	   0x1180080901fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1015"             ,	   0x1180080901fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1016"             ,	   0x1180080901fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1017"             ,	   0x1180080901fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1018"             ,	   0x1180080901fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1019"             ,	   0x1180080901fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1020"             ,	   0x1180080901fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1021"             ,	   0x1180080901fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1022"             ,	   0x1180080901ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_VRT_MEM1023"             ,	   0x1180080901ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"L2C_WPAR_IOB0"               ,	   0x1180080840200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
+	{"L2C_WPAR_IOB1"               ,	   0x1180080840208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
+	{"L2C_WPAR_PP0"                ,	   0x1180080840000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP1"                ,	   0x1180080840008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP2"                ,	   0x1180080840010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP3"                ,	   0x1180080840018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP4"                ,	   0x1180080840020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP5"                ,	   0x1180080840028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP6"                ,	   0x1180080840030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP7"                ,	   0x1180080840038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP8"                ,	   0x1180080840040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP9"                ,	   0x1180080840048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP10"               ,	   0x1180080840050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP11"               ,	   0x1180080840058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP12"               ,	   0x1180080840060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP13"               ,	   0x1180080840068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP14"               ,	   0x1180080840070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP15"               ,	   0x1180080840078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP16"               ,	   0x1180080840080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP17"               ,	   0x1180080840088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP18"               ,	   0x1180080840090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP19"               ,	   0x1180080840098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP20"               ,	   0x11800808400a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP21"               ,	   0x11800808400a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP22"               ,	   0x11800808400b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP23"               ,	   0x11800808400b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP24"               ,	   0x11800808400c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP25"               ,	   0x11800808400c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP26"               ,	   0x11800808400d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP27"               ,	   0x11800808400d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP28"               ,	   0x11800808400e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP29"               ,	   0x11800808400e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP30"               ,	   0x11800808400f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_WPAR_PP31"               ,	   0x11800808400f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"L2C_XMC0_PFC"                ,	   0x1180080800400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
+	{"L2C_XMC1_PFC"                ,	   0x1180080800440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
+	{"L2C_XMC2_PFC"                ,	   0x1180080800480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
+	{"L2C_XMC3_PFC"                ,	   0x11800808004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
+	{"L2C_XMC_CMD"                 ,	   0x1180080800028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	648},
+	{"L2C_XMD0_PFC"                ,	   0x1180080800408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
+	{"L2C_XMD1_PFC"                ,	   0x1180080800448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
+	{"L2C_XMD2_PFC"                ,	   0x1180080800488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
+	{"L2C_XMD3_PFC"                ,	   0x11800808004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
+	{"LMC0_CHAR_CTL"               ,	   0x1180088000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
+	{"LMC1_CHAR_CTL"               ,	   0x1180089000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
+	{"LMC2_CHAR_CTL"               ,	   0x118008a000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
+	{"LMC3_CHAR_CTL"               ,	   0x118008b000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
+	{"LMC0_CHAR_MASK0"             ,	   0x1180088000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
+	{"LMC1_CHAR_MASK0"             ,	   0x1180089000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
+	{"LMC2_CHAR_MASK0"             ,	   0x118008a000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
+	{"LMC3_CHAR_MASK0"             ,	   0x118008b000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
+	{"LMC0_CHAR_MASK1"             ,	   0x1180088000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
+	{"LMC1_CHAR_MASK1"             ,	   0x1180089000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
+	{"LMC2_CHAR_MASK1"             ,	   0x118008a000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
+	{"LMC3_CHAR_MASK1"             ,	   0x118008b000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
+	{"LMC0_CHAR_MASK2"             ,	   0x1180088000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
+	{"LMC1_CHAR_MASK2"             ,	   0x1180089000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
+	{"LMC2_CHAR_MASK2"             ,	   0x118008a000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
+	{"LMC3_CHAR_MASK2"             ,	   0x118008b000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
+	{"LMC0_CHAR_MASK3"             ,	   0x1180088000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
+	{"LMC1_CHAR_MASK3"             ,	   0x1180089000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
+	{"LMC2_CHAR_MASK3"             ,	   0x118008a000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
+	{"LMC3_CHAR_MASK3"             ,	   0x118008b000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
+	{"LMC0_CHAR_MASK4"             ,	   0x1180088000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"LMC1_CHAR_MASK4"             ,	   0x1180089000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"LMC2_CHAR_MASK4"             ,	   0x118008a000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"LMC3_CHAR_MASK4"             ,	   0x118008b000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"LMC0_COMP_CTL2"              ,	   0x11800880001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
+	{"LMC1_COMP_CTL2"              ,	   0x11800890001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
+	{"LMC2_COMP_CTL2"              ,	   0x118008a0001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
+	{"LMC3_COMP_CTL2"              ,	   0x118008b0001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
+	{"LMC0_CONFIG"                 ,	   0x1180088000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
+	{"LMC1_CONFIG"                 ,	   0x1180089000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
+	{"LMC2_CONFIG"                 ,	   0x118008a000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
+	{"LMC3_CONFIG"                 ,	   0x118008b000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
+	{"LMC0_CONTROL"                ,	   0x1180088000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
+	{"LMC1_CONTROL"                ,	   0x1180089000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
+	{"LMC2_CONTROL"                ,	   0x118008a000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
+	{"LMC3_CONTROL"                ,	   0x118008b000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
+	{"LMC0_DCLK_CNT"               ,	   0x11800880001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
+	{"LMC1_DCLK_CNT"               ,	   0x11800890001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
+	{"LMC2_DCLK_CNT"               ,	   0x118008a0001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
+	{"LMC3_DCLK_CNT"               ,	   0x118008b0001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
+	{"LMC0_DDR_PLL_CTL"            ,	   0x1180088000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
+	{"LMC1_DDR_PLL_CTL"            ,	   0x1180089000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
+	{"LMC2_DDR_PLL_CTL"            ,	   0x118008a000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
+	{"LMC3_DDR_PLL_CTL"            ,	   0x118008b000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
+	{"LMC0_DIMM000_PARAMS"         ,	   0x1180088000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"LMC0_DIMM001_PARAMS"         ,	   0x1180088000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"LMC1_DIMM000_PARAMS"         ,	   0x1180089000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"LMC1_DIMM001_PARAMS"         ,	   0x1180089000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"LMC2_DIMM000_PARAMS"         ,	   0x118008a000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"LMC2_DIMM001_PARAMS"         ,	   0x118008a000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"LMC3_DIMM000_PARAMS"         ,	   0x118008b000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"LMC3_DIMM001_PARAMS"         ,	   0x118008b000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"LMC0_DIMM_CTL"               ,	   0x1180088000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"LMC1_DIMM_CTL"               ,	   0x1180089000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"LMC2_DIMM_CTL"               ,	   0x118008a000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"LMC3_DIMM_CTL"               ,	   0x118008b000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"LMC0_DLL_CTL2"               ,	   0x11800880001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
+	{"LMC1_DLL_CTL2"               ,	   0x11800890001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
+	{"LMC2_DLL_CTL2"               ,	   0x118008a0001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
+	{"LMC3_DLL_CTL2"               ,	   0x118008b0001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
+	{"LMC0_DLL_CTL3"               ,	   0x1180088000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
+	{"LMC1_DLL_CTL3"               ,	   0x1180089000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
+	{"LMC2_DLL_CTL3"               ,	   0x118008a000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
+	{"LMC3_DLL_CTL3"               ,	   0x118008b000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
+	{"LMC0_DUAL_MEMCFG"            ,	   0x1180088000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
+	{"LMC1_DUAL_MEMCFG"            ,	   0x1180089000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
+	{"LMC2_DUAL_MEMCFG"            ,	   0x118008a000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
+	{"LMC3_DUAL_MEMCFG"            ,	   0x118008b000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
+	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"LMC1_ECC_SYND"               ,	   0x1180089000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"LMC2_ECC_SYND"               ,	   0x118008a000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"LMC3_ECC_SYND"               ,	   0x118008b000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
+	{"LMC1_FADR"                   ,	   0x1180089000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
+	{"LMC2_FADR"                   ,	   0x118008a000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
+	{"LMC3_FADR"                   ,	   0x118008b000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
+	{"LMC0_IFB_CNT"                ,	   0x11800880001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"LMC1_IFB_CNT"                ,	   0x11800890001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"LMC2_IFB_CNT"                ,	   0x118008a0001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"LMC3_IFB_CNT"                ,	   0x118008b0001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"LMC0_INT"                    ,	   0x11800880001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"LMC1_INT"                    ,	   0x11800890001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"LMC2_INT"                    ,	   0x118008a0001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"LMC3_INT"                    ,	   0x118008b0001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"LMC0_INT_EN"                 ,	   0x11800880001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	670},
+	{"LMC1_INT_EN"                 ,	   0x11800890001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	670},
+	{"LMC2_INT_EN"                 ,	   0x118008a0001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	670},
+	{"LMC3_INT_EN"                 ,	   0x118008b0001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	670},
+	{"LMC0_MODEREG_PARAMS0"        ,	   0x11800880001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	671},
+	{"LMC1_MODEREG_PARAMS0"        ,	   0x11800890001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	671},
+	{"LMC2_MODEREG_PARAMS0"        ,	   0x118008a0001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	671},
+	{"LMC3_MODEREG_PARAMS0"        ,	   0x118008b0001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	671},
+	{"LMC0_MODEREG_PARAMS1"        ,	   0x1180088000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
+	{"LMC1_MODEREG_PARAMS1"        ,	   0x1180089000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
+	{"LMC2_MODEREG_PARAMS1"        ,	   0x118008a000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
+	{"LMC3_MODEREG_PARAMS1"        ,	   0x118008b000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
+	{"LMC0_NXM"                    ,	   0x11800880000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC1_NXM"                    ,	   0x11800890000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC2_NXM"                    ,	   0x118008a0000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC3_NXM"                    ,	   0x118008b0000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"LMC0_OPS_CNT"                ,	   0x11800880001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"LMC1_OPS_CNT"                ,	   0x11800890001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"LMC2_OPS_CNT"                ,	   0x118008a0001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"LMC3_OPS_CNT"                ,	   0x118008b0001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"LMC0_PHY_CTL"                ,	   0x1180088000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"LMC1_PHY_CTL"                ,	   0x1180089000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"LMC2_PHY_CTL"                ,	   0x118008a000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"LMC3_PHY_CTL"                ,	   0x118008b000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"LMC0_RESET_CTL"              ,	   0x1180088000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"LMC1_RESET_CTL"              ,	   0x1180089000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"LMC2_RESET_CTL"              ,	   0x118008a000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"LMC3_RESET_CTL"              ,	   0x118008b000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"LMC0_RLEVEL_CTL"             ,	   0x11800880002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"LMC1_RLEVEL_CTL"             ,	   0x11800890002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"LMC2_RLEVEL_CTL"             ,	   0x118008a0002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"LMC3_RLEVEL_CTL"             ,	   0x118008b0002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"LMC0_RLEVEL_DBG"             ,	   0x11800880002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	678},
+	{"LMC1_RLEVEL_DBG"             ,	   0x11800890002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	678},
+	{"LMC2_RLEVEL_DBG"             ,	   0x118008a0002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	678},
+	{"LMC3_RLEVEL_DBG"             ,	   0x118008b0002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	678},
+	{"LMC0_RLEVEL_RANK000"         ,	   0x1180088000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC0_RLEVEL_RANK001"         ,	   0x1180088000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC0_RLEVEL_RANK002"         ,	   0x1180088000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC0_RLEVEL_RANK003"         ,	   0x1180088000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC1_RLEVEL_RANK000"         ,	   0x1180089000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC1_RLEVEL_RANK001"         ,	   0x1180089000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC1_RLEVEL_RANK002"         ,	   0x1180089000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC1_RLEVEL_RANK003"         ,	   0x1180089000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC2_RLEVEL_RANK000"         ,	   0x118008a000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC2_RLEVEL_RANK001"         ,	   0x118008a000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC2_RLEVEL_RANK002"         ,	   0x118008a000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC2_RLEVEL_RANK003"         ,	   0x118008a000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC3_RLEVEL_RANK000"         ,	   0x118008b000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC3_RLEVEL_RANK001"         ,	   0x118008b000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC3_RLEVEL_RANK002"         ,	   0x118008b000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC3_RLEVEL_RANK003"         ,	   0x118008b000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"LMC0_RODT_MASK"              ,	   0x1180088000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"LMC1_RODT_MASK"              ,	   0x1180089000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"LMC2_RODT_MASK"              ,	   0x118008a000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"LMC3_RODT_MASK"              ,	   0x118008b000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"LMC0_SLOT_CTL0"              ,	   0x11800880001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"LMC1_SLOT_CTL0"              ,	   0x11800890001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"LMC2_SLOT_CTL0"              ,	   0x118008a0001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"LMC3_SLOT_CTL0"              ,	   0x118008b0001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"LMC0_SLOT_CTL1"              ,	   0x1180088000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"LMC1_SLOT_CTL1"              ,	   0x1180089000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"LMC2_SLOT_CTL1"              ,	   0x118008a000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"LMC3_SLOT_CTL1"              ,	   0x118008b000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"LMC0_SLOT_CTL2"              ,	   0x1180088000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"LMC1_SLOT_CTL2"              ,	   0x1180089000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"LMC2_SLOT_CTL2"              ,	   0x118008a000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"LMC3_SLOT_CTL2"              ,	   0x118008b000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"LMC0_TIMING_PARAMS0"         ,	   0x1180088000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC1_TIMING_PARAMS0"         ,	   0x1180089000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC2_TIMING_PARAMS0"         ,	   0x118008a000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC3_TIMING_PARAMS0"         ,	   0x118008b000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"LMC0_TIMING_PARAMS1"         ,	   0x11800880001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"LMC1_TIMING_PARAMS1"         ,	   0x11800890001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"LMC2_TIMING_PARAMS1"         ,	   0x118008a0001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"LMC3_TIMING_PARAMS1"         ,	   0x118008b0001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"LMC0_TRO_CTL"                ,	   0x1180088000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"LMC1_TRO_CTL"                ,	   0x1180089000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"LMC2_TRO_CTL"                ,	   0x118008a000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"LMC3_TRO_CTL"                ,	   0x118008b000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"LMC0_TRO_STAT"               ,	   0x1180088000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"LMC1_TRO_STAT"               ,	   0x1180089000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"LMC2_TRO_STAT"               ,	   0x118008a000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"LMC3_TRO_STAT"               ,	   0x118008b000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"LMC0_WLEVEL_CTL"             ,	   0x1180088000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"LMC1_WLEVEL_CTL"             ,	   0x1180089000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"LMC2_WLEVEL_CTL"             ,	   0x118008a000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"LMC3_WLEVEL_CTL"             ,	   0x118008b000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"LMC0_WLEVEL_DBG"             ,	   0x1180088000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"LMC1_WLEVEL_DBG"             ,	   0x1180089000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"LMC2_WLEVEL_DBG"             ,	   0x118008a000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"LMC3_WLEVEL_DBG"             ,	   0x118008b000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"LMC0_WLEVEL_RANK000"         ,	   0x11800880002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"LMC0_WLEVEL_RANK001"         ,	   0x11800880002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"LMC0_WLEVEL_RANK002"         ,	   0x11800880002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"LMC0_WLEVEL_RANK003"         ,	   0x11800880002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"LMC1_WLEVEL_RANK000"         ,	   0x11800890002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"LMC1_WLEVEL_RANK001"         ,	   0x11800890002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"LMC1_WLEVEL_RANK002"         ,	   0x11800890002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"LMC1_WLEVEL_RANK003"         ,	   0x11800890002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"LMC2_WLEVEL_RANK000"         ,	   0x118008a0002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"LMC2_WLEVEL_RANK001"         ,	   0x118008a0002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"LMC2_WLEVEL_RANK002"         ,	   0x118008a0002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"LMC2_WLEVEL_RANK003"         ,	   0x118008a0002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"LMC3_WLEVEL_RANK000"         ,	   0x118008b0002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"LMC3_WLEVEL_RANK001"         ,	   0x118008b0002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"LMC3_WLEVEL_RANK002"         ,	   0x118008b0002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"LMC3_WLEVEL_RANK003"         ,	   0x118008b0002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"LMC0_WODT_MASK"              ,	   0x11800880001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"LMC1_WODT_MASK"              ,	   0x11800890001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"LMC2_WODT_MASK"              ,	   0x118008a0001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"LMC3_WODT_MASK"              ,	   0x118008b0001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"MIO_BOOT_COMP"               ,	   0x11800000000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"MIO_BOOT_DMA_CFG0"           ,	   0x1180000000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"MIO_BOOT_DMA_CFG1"           ,	   0x1180000000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"MIO_BOOT_DMA_INT0"           ,	   0x1180000000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"MIO_BOOT_DMA_INT1"           ,	   0x1180000000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"MIO_BOOT_DMA_INT_EN0"        ,	   0x1180000000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"MIO_BOOT_DMA_INT_EN1"        ,	   0x1180000000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"MIO_BOOT_DMA_TIM0"           ,	   0x1180000000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"MIO_BOOT_DMA_TIM1"           ,	   0x1180000000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"MIO_BOOT_INT"                ,	   0x11800000000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"MIO_BOOT_PIN_DEFS"           ,	   0x11800000000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"MIO_BOOT_REG_CFG3"           ,	   0x1180000000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"MIO_BOOT_REG_CFG4"           ,	   0x1180000000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"MIO_BOOT_REG_CFG5"           ,	   0x1180000000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"MIO_BOOT_REG_CFG6"           ,	   0x1180000000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"MIO_BOOT_REG_CFG7"           ,	   0x1180000000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"MIO_BOOT_REG_TIM0"           ,	   0x1180000000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"MIO_BOOT_REG_TIM1"           ,	   0x1180000000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"MIO_BOOT_REG_TIM2"           ,	   0x1180000000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"MIO_BOOT_REG_TIM3"           ,	   0x1180000000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"MIO_BOOT_REG_TIM4"           ,	   0x1180000000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"MIO_BOOT_THR"                ,	   0x11800000000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"MIO_FUS_DAT3"                ,	   0x1180000001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"MIO_FUS_EMA"                 ,	   0x1180000001550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"MIO_FUS_PDF"                 ,	   0x1180000001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"MIO_FUS_PLL"                 ,	   0x1180000001580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"MIO_FUS_PROG"                ,	   0x1180000001510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
+	{"MIO_FUS_PROG_TIMES"          ,	   0x1180000001518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
+	{"MIO_FUS_RCMD"                ,	   0x1180000001500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
+	{"MIO_FUS_READ_TIMES"          ,	   0x1180000001570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
+	{"MIO_FUS_REPAIR_RES0"         ,	   0x1180000001558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
+	{"MIO_FUS_REPAIR_RES1"         ,	   0x1180000001560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
+	{"MIO_FUS_REPAIR_RES2"         ,	   0x1180000001568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
+	{"MIO_FUS_SPR_REPAIR_RES"      ,	   0x1180000001548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
+	{"MIO_FUS_SPR_REPAIR_SUM"      ,	   0x1180000001540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	723},
+	{"MIO_FUS_WADR"                ,	   0x1180000001508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"MIO_GPIO_COMP"               ,	   0x11800000000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"MIO_NDF_DMA_CFG"             ,	   0x1180000000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
+	{"MIO_NDF_DMA_INT"             ,	   0x1180000000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	727},
+	{"MIO_NDF_DMA_INT_EN"          ,	   0x1180000000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	728},
+	{"MIO_PTP_CKOUT_HI_INCR"       ,	   0x1070000000f40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	729},
+	{"MIO_PTP_CKOUT_LO_INCR"       ,	   0x1070000000f48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	730},
+	{"MIO_PTP_CKOUT_THRESH_HI"     ,	   0x1070000000f38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	731},
+	{"MIO_PTP_CKOUT_THRESH_LO"     ,	   0x1070000000f30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	732},
+	{"MIO_PTP_CLOCK_CFG"           ,	   0x1070000000f00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	733},
+	{"MIO_PTP_CLOCK_COMP"          ,	   0x1070000000f18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	734},
+	{"MIO_PTP_CLOCK_HI"            ,	   0x1070000000f10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	735},
+	{"MIO_PTP_CLOCK_LO"            ,	   0x1070000000f08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	736},
+	{"MIO_PTP_EVT_CNT"             ,	   0x1070000000f28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	737},
+	{"MIO_PTP_PPS_HI_INCR"         ,	   0x1070000000f60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	738},
+	{"MIO_PTP_PPS_LO_INCR"         ,	   0x1070000000f68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	739},
+	{"MIO_PTP_PPS_THRESH_HI"       ,	   0x1070000000f58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	740},
+	{"MIO_PTP_PPS_THRESH_LO"       ,	   0x1070000000f50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	741},
+	{"MIO_PTP_TIMESTAMP"           ,	   0x1070000000f20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	742},
+	{"MIO_QLM0_CFG"                ,	   0x1180000001590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"MIO_QLM1_CFG"                ,	   0x1180000001598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"MIO_QLM2_CFG"                ,	   0x11800000015a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"MIO_QLM3_CFG"                ,	   0x11800000015a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"MIO_QLM4_CFG"                ,	   0x11800000015b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"MIO_RST_BOOT"                ,	   0x1180000001600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	744},
+	{"MIO_RST_CFG"                 ,	   0x1180000001610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	745},
+	{"MIO_RST_CNTL0"               ,	   0x1180000001648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"MIO_RST_CNTL1"               ,	   0x1180000001650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"MIO_RST_CTL0"                ,	   0x1180000001618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"MIO_RST_CTL1"                ,	   0x1180000001620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"MIO_RST_DELAY"               ,	   0x1180000001608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"MIO_RST_INT"                 ,	   0x1180000001628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"MIO_RST_INT_EN"              ,	   0x1180000001630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"MIO_TWS0_INT"                ,	   0x1180000001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"MIO_TWS1_INT"                ,	   0x1180000001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"MIO_TWS0_SW_TWSI"            ,	   0x1180000001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"MIO_TWS1_SW_TWSI"            ,	   0x1180000001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"MIO_TWS1_SW_TWSI_EXT"        ,	   0x1180000001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"MIO_TWS1_TWSI_SW"            ,	   0x1180000001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"MIO_UART1_DLH"               ,	   0x1180000000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"MIO_UART1_DLL"               ,	   0x1180000000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"MIO_UART1_FAR"               ,	   0x1180000000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"MIO_UART1_FCR"               ,	   0x1180000000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"MIO_UART0_HTX"               ,	   0x1180000000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"MIO_UART1_HTX"               ,	   0x1180000000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"MIO_UART1_IER"               ,	   0x1180000000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"MIO_UART1_IIR"               ,	   0x1180000000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"MIO_UART1_LCR"               ,	   0x1180000000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"MIO_UART1_LSR"               ,	   0x1180000000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"MIO_UART1_MCR"               ,	   0x1180000000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"MIO_UART1_MSR"               ,	   0x1180000000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"MIO_UART1_RBR"               ,	   0x1180000000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"MIO_UART0_RFL"               ,	   0x1180000000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"MIO_UART1_RFL"               ,	   0x1180000000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"MIO_UART1_RFW"               ,	   0x1180000000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"MIO_UART1_SCR"               ,	   0x1180000000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"MIO_UART0_SFE"               ,	   0x1180000000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"MIO_UART1_SFE"               ,	   0x1180000000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"MIO_UART0_SRR"               ,	   0x1180000000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"MIO_UART1_SRR"               ,	   0x1180000000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"MIO_UART0_SRT"               ,	   0x1180000000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"MIO_UART1_SRT"               ,	   0x1180000000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"MIO_UART0_STT"               ,	   0x1180000000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"MIO_UART1_STT"               ,	   0x1180000000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"MIO_UART0_TFL"               ,	   0x1180000000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"MIO_UART1_TFL"               ,	   0x1180000000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"MIO_UART1_TFR"               ,	   0x1180000000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"MIO_UART1_THR"               ,	   0x1180000000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"MIO_UART1_USR"               ,	   0x1180000000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"MIX0_BIST"                   ,	   0x1070000100078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	780},
+	{"MIX0_CTL"                    ,	   0x1070000100020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	781},
+	{"MIX0_INTENA"                 ,	   0x1070000100050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	782},
+	{"MIX0_IRCNT"                  ,	   0x1070000100030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	783},
+	{"MIX0_IRHWM"                  ,	   0x1070000100028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	784},
+	{"MIX0_IRING1"                 ,	   0x1070000100010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	785},
+	{"MIX0_IRING2"                 ,	   0x1070000100018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	786},
+	{"MIX0_ISR"                    ,	   0x1070000100048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	787},
+	{"MIX0_ORCNT"                  ,	   0x1070000100040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	788},
+	{"MIX0_ORHWM"                  ,	   0x1070000100038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	789},
+	{"MIX0_ORING1"                 ,	   0x1070000100000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	790},
+	{"MIX0_ORING2"                 ,	   0x1070000100008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	791},
+	{"MIX0_REMCNT"                 ,	   0x1070000100058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	792},
+	{"MIX0_TSCTL"                  ,	   0x1070000100068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	793},
+	{"MIX0_TSTAMP"                 ,	   0x1070000100060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	794},
+	{"NDF_BT_PG_INFO"              ,	   0x1070001000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	795},
+	{"NDF_CMD"                     ,	   0x1070001000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	796},
+	{"NDF_DRBELL"                  ,	   0x1070001000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	797},
+	{"NDF_ECC_CNT"                 ,	   0x1070001000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	798},
+	{"NDF_INT"                     ,	   0x1070001000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	799},
+	{"NDF_INT_EN"                  ,	   0x1070001000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	800},
+	{"NDF_MISC"                    ,	   0x1070001000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	801},
+	{"NDF_ST_REG"                  ,	   0x1070001000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	802},
+	{"PCIEEP0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	803},
+	{"PCIEEP1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	803},
+	{"PCIEEP0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	804},
+	{"PCIEEP1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	804},
+	{"PCIEEP0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	805},
+	{"PCIEEP1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	805},
+	{"PCIEEP0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	806},
+	{"PCIEEP1_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	806},
+	{"PCIEEP0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	807},
+	{"PCIEEP1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	807},
+	{"PCIEEP0_CFG004_MASK"         ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	808},
+	{"PCIEEP1_CFG004_MASK"         ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	808},
+	{"PCIEEP0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	809},
+	{"PCIEEP1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	809},
+	{"PCIEEP0_CFG005_MASK"         ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	810},
+	{"PCIEEP1_CFG005_MASK"         ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	810},
+	{"PCIEEP0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	811},
+	{"PCIEEP1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	811},
+	{"PCIEEP0_CFG006_MASK"         ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	812},
+	{"PCIEEP1_CFG006_MASK"         ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	812},
+	{"PCIEEP0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	813},
+	{"PCIEEP1_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	813},
+	{"PCIEEP0_CFG007_MASK"         ,	        0x8000001cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	814},
+	{"PCIEEP1_CFG007_MASK"         ,	        0x8000001cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	814},
+	{"PCIEEP0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	815},
+	{"PCIEEP1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	815},
+	{"PCIEEP0_CFG008_MASK"         ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	816},
+	{"PCIEEP1_CFG008_MASK"         ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	816},
+	{"PCIEEP0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	817},
+	{"PCIEEP1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	817},
+	{"PCIEEP0_CFG009_MASK"         ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	818},
+	{"PCIEEP1_CFG009_MASK"         ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	818},
+	{"PCIEEP0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	819},
+	{"PCIEEP1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	819},
+	{"PCIEEP0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	820},
+	{"PCIEEP1_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	820},
+	{"PCIEEP0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	821},
+	{"PCIEEP1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	821},
+	{"PCIEEP0_CFG012_MASK"         ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	822},
+	{"PCIEEP1_CFG012_MASK"         ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	822},
+	{"PCIEEP0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	823},
+	{"PCIEEP1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	823},
+	{"PCIEEP0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	824},
+	{"PCIEEP1_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	824},
+	{"PCIEEP0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	825},
+	{"PCIEEP1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	825},
+	{"PCIEEP0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	826},
+	{"PCIEEP1_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	826},
+	{"PCIEEP0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	827},
+	{"PCIEEP1_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	827},
+	{"PCIEEP0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	828},
+	{"PCIEEP1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	828},
+	{"PCIEEP0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	829},
+	{"PCIEEP1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	829},
+	{"PCIEEP0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	830},
+	{"PCIEEP1_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	830},
+	{"PCIEEP0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	831},
+	{"PCIEEP1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	831},
+	{"PCIEEP0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	832},
+	{"PCIEEP1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	832},
+	{"PCIEEP0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	833},
+	{"PCIEEP1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	833},
+	{"PCIEEP0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	834},
+	{"PCIEEP1_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	834},
+	{"PCIEEP0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	835},
+	{"PCIEEP1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	835},
+	{"PCIEEP0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	836},
+	{"PCIEEP1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	836},
+	{"PCIEEP0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	837},
+	{"PCIEEP1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	837},
+	{"PCIEEP0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	838},
+	{"PCIEEP1_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	838},
+	{"PCIEEP0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	839},
+	{"PCIEEP1_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	839},
+	{"PCIEEP0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	840},
+	{"PCIEEP1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	840},
+	{"PCIEEP0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	841},
+	{"PCIEEP1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	841},
+	{"PCIEEP0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	842},
+	{"PCIEEP1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	842},
+	{"PCIEEP0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	843},
+	{"PCIEEP1_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	843},
+	{"PCIEEP0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	844},
+	{"PCIEEP1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	844},
+	{"PCIEEP0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	845},
+	{"PCIEEP1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	845},
+	{"PCIEEP0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	846},
+	{"PCIEEP1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	846},
+	{"PCIEEP0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	847},
+	{"PCIEEP1_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	847},
+	{"PCIEEP0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	848},
+	{"PCIEEP1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	848},
+	{"PCIEEP0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	849},
+	{"PCIEEP1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	849},
+	{"PCIEEP0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	850},
+	{"PCIEEP1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	850},
+	{"PCIEEP0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	851},
+	{"PCIEEP1_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	851},
+	{"PCIEEP0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	852},
+	{"PCIEEP1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	852},
+	{"PCIEEP0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	853},
+	{"PCIEEP1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	853},
+	{"PCIEEP0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	854},
+	{"PCIEEP1_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	854},
+	{"PCIEEP0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	855},
+	{"PCIEEP1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	855},
+	{"PCIEEP0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	856},
+	{"PCIEEP1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	856},
+	{"PCIEEP0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	857},
+	{"PCIEEP1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	857},
+	{"PCIEEP0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	858},
+	{"PCIEEP1_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	858},
+	{"PCIEEP0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	859},
+	{"PCIEEP1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	859},
+	{"PCIEEP0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	860},
+	{"PCIEEP1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	860},
+	{"PCIEEP0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	861},
+	{"PCIEEP1_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	861},
+	{"PCIEEP0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	862},
+	{"PCIEEP1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	862},
+	{"PCIEEP0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	863},
+	{"PCIEEP1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	863},
+	{"PCIEEP0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	864},
+	{"PCIEEP1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	864},
+	{"PCIEEP0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	865},
+	{"PCIEEP1_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	865},
+	{"PCIEEP0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	866},
+	{"PCIEEP1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	866},
+	{"PCIEEP0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	867},
+	{"PCIEEP1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	867},
+	{"PCIEEP0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	868},
+	{"PCIEEP1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	868},
+	{"PCIEEP0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	869},
+	{"PCIEEP1_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	869},
+	{"PCIEEP0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	870},
+	{"PCIEEP1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	870},
+	{"PCIEEP0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	871},
+	{"PCIEEP1_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	871},
+	{"PCIEEP0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	872},
+	{"PCIEEP1_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	872},
+	{"PCIEEP0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	873},
+	{"PCIEEP1_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	873},
+	{"PCIEEP0_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	874},
+	{"PCIEEP1_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	874},
+	{"PCIEEP0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	875},
+	{"PCIEEP1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	875},
+	{"PCIEEP0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	876},
+	{"PCIEEP1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	876},
+	{"PCIERC0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	877},
+	{"PCIERC1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	877},
+	{"PCIERC0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	878},
+	{"PCIERC1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	878},
+	{"PCIERC0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	879},
+	{"PCIERC1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	879},
+	{"PCIERC0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	880},
+	{"PCIERC1_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	880},
+	{"PCIERC0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	881},
+	{"PCIERC1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	881},
+	{"PCIERC0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	882},
+	{"PCIERC1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	882},
+	{"PCIERC0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	883},
+	{"PCIERC1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	883},
+	{"PCIERC0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	884},
+	{"PCIERC1_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	884},
+	{"PCIERC0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	885},
+	{"PCIERC1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	885},
+	{"PCIERC0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	886},
+	{"PCIERC1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	886},
+	{"PCIERC0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	887},
+	{"PCIERC1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	887},
+	{"PCIERC0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	888},
+	{"PCIERC1_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	888},
+	{"PCIERC0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	889},
+	{"PCIERC1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	889},
+	{"PCIERC0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	890},
+	{"PCIERC1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	890},
+	{"PCIERC0_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	891},
+	{"PCIERC1_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	891},
+	{"PCIERC0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	892},
+	{"PCIERC1_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	892},
+	{"PCIERC0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	893},
+	{"PCIERC1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	893},
+	{"PCIERC0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	894},
+	{"PCIERC1_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	894},
+	{"PCIERC0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	895},
+	{"PCIERC1_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	895},
+	{"PCIERC0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	896},
+	{"PCIERC1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	896},
+	{"PCIERC0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	897},
+	{"PCIERC1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	897},
+	{"PCIERC0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	898},
+	{"PCIERC1_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	898},
+	{"PCIERC0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	899},
+	{"PCIERC1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	899},
+	{"PCIERC0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	900},
+	{"PCIERC1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	900},
+	{"PCIERC0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	901},
+	{"PCIERC1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	901},
+	{"PCIERC0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	902},
+	{"PCIERC1_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	902},
+	{"PCIERC0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	903},
+	{"PCIERC1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	903},
+	{"PCIERC0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	904},
+	{"PCIERC1_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	904},
+	{"PCIERC0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	905},
+	{"PCIERC1_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	905},
+	{"PCIERC0_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	906},
+	{"PCIERC1_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	906},
+	{"PCIERC0_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	907},
+	{"PCIERC1_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	907},
+	{"PCIERC0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	908},
+	{"PCIERC1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	908},
+	{"PCIERC0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	909},
+	{"PCIERC1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	909},
+	{"PCIERC0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	910},
+	{"PCIERC1_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	910},
+	{"PCIERC0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	911},
+	{"PCIERC1_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	911},
+	{"PCIERC0_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	912},
+	{"PCIERC1_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	912},
+	{"PCIERC0_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	913},
+	{"PCIERC1_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	913},
+	{"PCIERC0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	914},
+	{"PCIERC1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	914},
+	{"PCIERC0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	915},
+	{"PCIERC1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	915},
+	{"PCIERC0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	916},
+	{"PCIERC1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	916},
+	{"PCIERC0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	917},
+	{"PCIERC1_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	917},
+	{"PCIERC0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	918},
+	{"PCIERC1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	918},
+	{"PCIERC0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	919},
+	{"PCIERC1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	919},
+	{"PCIERC0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	920},
+	{"PCIERC1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	920},
+	{"PCIERC0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	921},
+	{"PCIERC1_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	921},
+	{"PCIERC0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	922},
+	{"PCIERC1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	922},
+	{"PCIERC0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	923},
+	{"PCIERC1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	923},
+	{"PCIERC0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	924},
+	{"PCIERC1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	924},
+	{"PCIERC0_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	925},
+	{"PCIERC1_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	925},
+	{"PCIERC0_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	926},
+	{"PCIERC1_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	926},
+	{"PCIERC0_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	927},
+	{"PCIERC1_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	927},
+	{"PCIERC0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	928},
+	{"PCIERC1_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	928},
+	{"PCIERC0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	929},
+	{"PCIERC1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	929},
+	{"PCIERC0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	930},
+	{"PCIERC1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	930},
+	{"PCIERC0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	931},
+	{"PCIERC1_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	931},
+	{"PCIERC0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	932},
+	{"PCIERC1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	932},
+	{"PCIERC0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	933},
+	{"PCIERC1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	933},
+	{"PCIERC0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	934},
+	{"PCIERC1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	934},
+	{"PCIERC0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	935},
+	{"PCIERC1_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	935},
+	{"PCIERC0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	936},
+	{"PCIERC1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	936},
+	{"PCIERC0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	937},
+	{"PCIERC1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	937},
+	{"PCIERC0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	938},
+	{"PCIERC1_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	938},
+	{"PCIERC0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	939},
+	{"PCIERC1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	939},
+	{"PCIERC0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	940},
+	{"PCIERC1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	940},
+	{"PCIERC0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	941},
+	{"PCIERC1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	941},
+	{"PCIERC0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	942},
+	{"PCIERC1_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	942},
+	{"PCIERC0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	943},
+	{"PCIERC1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	943},
+	{"PCIERC0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	944},
+	{"PCIERC1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	944},
+	{"PCIERC0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	945},
+	{"PCIERC1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	945},
+	{"PCIERC0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	946},
+	{"PCIERC1_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	946},
+	{"PCIERC0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	947},
+	{"PCIERC1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	947},
+	{"PCIERC0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	948},
+	{"PCIERC1_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	948},
+	{"PCIERC0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	949},
+	{"PCIERC1_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	949},
+	{"PCIERC0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	950},
+	{"PCIERC1_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	950},
+	{"PCIERC0_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	951},
+	{"PCIERC1_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	951},
+	{"PCIERC0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	952},
+	{"PCIERC1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	952},
+	{"PCIERC0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	953},
+	{"PCIERC1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	953},
+	{"PCS0_AN000_ADV_REG"          ,	   0x11800b0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS0_AN001_ADV_REG"          ,	   0x11800b0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS0_AN002_ADV_REG"          ,	   0x11800b0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS0_AN003_ADV_REG"          ,	   0x11800b0001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS1_AN000_ADV_REG"          ,	   0x11800b1001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS1_AN001_ADV_REG"          ,	   0x11800b1001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS1_AN002_ADV_REG"          ,	   0x11800b1001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS1_AN003_ADV_REG"          ,	   0x11800b1001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS2_AN000_ADV_REG"          ,	   0x11800b2001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS2_AN001_ADV_REG"          ,	   0x11800b2001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS2_AN002_ADV_REG"          ,	   0x11800b2001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS2_AN003_ADV_REG"          ,	   0x11800b2001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS3_AN000_ADV_REG"          ,	   0x11800b3001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS3_AN001_ADV_REG"          ,	   0x11800b3001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS3_AN002_ADV_REG"          ,	   0x11800b3001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS3_AN003_ADV_REG"          ,	   0x11800b3001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS4_AN000_ADV_REG"          ,	   0x11800b4001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS4_AN001_ADV_REG"          ,	   0x11800b4001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS4_AN002_ADV_REG"          ,	   0x11800b4001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS4_AN003_ADV_REG"          ,	   0x11800b4001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800b0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800b0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS0_AN002_EXT_ST_REG"       ,	   0x11800b0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS0_AN003_EXT_ST_REG"       ,	   0x11800b0001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS1_AN000_EXT_ST_REG"       ,	   0x11800b1001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS1_AN001_EXT_ST_REG"       ,	   0x11800b1001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS1_AN002_EXT_ST_REG"       ,	   0x11800b1001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS1_AN003_EXT_ST_REG"       ,	   0x11800b1001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS2_AN000_EXT_ST_REG"       ,	   0x11800b2001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS2_AN001_EXT_ST_REG"       ,	   0x11800b2001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS2_AN002_EXT_ST_REG"       ,	   0x11800b2001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS2_AN003_EXT_ST_REG"       ,	   0x11800b2001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS3_AN000_EXT_ST_REG"       ,	   0x11800b3001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS3_AN001_EXT_ST_REG"       ,	   0x11800b3001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS3_AN002_EXT_ST_REG"       ,	   0x11800b3001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS3_AN003_EXT_ST_REG"       ,	   0x11800b3001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS4_AN000_EXT_ST_REG"       ,	   0x11800b4001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS4_AN001_EXT_ST_REG"       ,	   0x11800b4001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS4_AN002_EXT_ST_REG"       ,	   0x11800b4001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS4_AN003_EXT_ST_REG"       ,	   0x11800b4001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800b0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800b0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS0_AN002_LP_ABIL_REG"      ,	   0x11800b0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS0_AN003_LP_ABIL_REG"      ,	   0x11800b0001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS1_AN000_LP_ABIL_REG"      ,	   0x11800b1001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS1_AN001_LP_ABIL_REG"      ,	   0x11800b1001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS1_AN002_LP_ABIL_REG"      ,	   0x11800b1001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS1_AN003_LP_ABIL_REG"      ,	   0x11800b1001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS2_AN000_LP_ABIL_REG"      ,	   0x11800b2001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS2_AN001_LP_ABIL_REG"      ,	   0x11800b2001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS2_AN002_LP_ABIL_REG"      ,	   0x11800b2001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS2_AN003_LP_ABIL_REG"      ,	   0x11800b2001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS3_AN000_LP_ABIL_REG"      ,	   0x11800b3001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS3_AN001_LP_ABIL_REG"      ,	   0x11800b3001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS3_AN002_LP_ABIL_REG"      ,	   0x11800b3001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS3_AN003_LP_ABIL_REG"      ,	   0x11800b3001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS4_AN000_LP_ABIL_REG"      ,	   0x11800b4001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS4_AN001_LP_ABIL_REG"      ,	   0x11800b4001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS4_AN002_LP_ABIL_REG"      ,	   0x11800b4001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS4_AN003_LP_ABIL_REG"      ,	   0x11800b4001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800b0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800b0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS0_AN002_RESULTS_REG"      ,	   0x11800b0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS0_AN003_RESULTS_REG"      ,	   0x11800b0001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS1_AN000_RESULTS_REG"      ,	   0x11800b1001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS1_AN001_RESULTS_REG"      ,	   0x11800b1001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS1_AN002_RESULTS_REG"      ,	   0x11800b1001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS1_AN003_RESULTS_REG"      ,	   0x11800b1001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS2_AN000_RESULTS_REG"      ,	   0x11800b2001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS2_AN001_RESULTS_REG"      ,	   0x11800b2001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS2_AN002_RESULTS_REG"      ,	   0x11800b2001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS2_AN003_RESULTS_REG"      ,	   0x11800b2001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS3_AN000_RESULTS_REG"      ,	   0x11800b3001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS3_AN001_RESULTS_REG"      ,	   0x11800b3001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS3_AN002_RESULTS_REG"      ,	   0x11800b3001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS3_AN003_RESULTS_REG"      ,	   0x11800b3001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS4_AN000_RESULTS_REG"      ,	   0x11800b4001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS4_AN001_RESULTS_REG"      ,	   0x11800b4001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS4_AN002_RESULTS_REG"      ,	   0x11800b4001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS4_AN003_RESULTS_REG"      ,	   0x11800b4001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PCS0_INT000_EN_REG"          ,	   0x11800b0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS0_INT001_EN_REG"          ,	   0x11800b0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS0_INT002_EN_REG"          ,	   0x11800b0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS0_INT003_EN_REG"          ,	   0x11800b0001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS1_INT000_EN_REG"          ,	   0x11800b1001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS1_INT001_EN_REG"          ,	   0x11800b1001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS1_INT002_EN_REG"          ,	   0x11800b1001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS1_INT003_EN_REG"          ,	   0x11800b1001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS2_INT000_EN_REG"          ,	   0x11800b2001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS2_INT001_EN_REG"          ,	   0x11800b2001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS2_INT002_EN_REG"          ,	   0x11800b2001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS2_INT003_EN_REG"          ,	   0x11800b2001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS3_INT000_EN_REG"          ,	   0x11800b3001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS3_INT001_EN_REG"          ,	   0x11800b3001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS3_INT002_EN_REG"          ,	   0x11800b3001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS3_INT003_EN_REG"          ,	   0x11800b3001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS4_INT000_EN_REG"          ,	   0x11800b4001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS4_INT001_EN_REG"          ,	   0x11800b4001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS4_INT002_EN_REG"          ,	   0x11800b4001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS4_INT003_EN_REG"          ,	   0x11800b4001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PCS0_INT000_REG"             ,	   0x11800b0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS0_INT001_REG"             ,	   0x11800b0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS0_INT002_REG"             ,	   0x11800b0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS0_INT003_REG"             ,	   0x11800b0001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS1_INT000_REG"             ,	   0x11800b1001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS1_INT001_REG"             ,	   0x11800b1001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS1_INT002_REG"             ,	   0x11800b1001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS1_INT003_REG"             ,	   0x11800b1001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS2_INT000_REG"             ,	   0x11800b2001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS2_INT001_REG"             ,	   0x11800b2001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS2_INT002_REG"             ,	   0x11800b2001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS2_INT003_REG"             ,	   0x11800b2001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS3_INT000_REG"             ,	   0x11800b3001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS3_INT001_REG"             ,	   0x11800b3001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS3_INT002_REG"             ,	   0x11800b3001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS3_INT003_REG"             ,	   0x11800b3001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS4_INT000_REG"             ,	   0x11800b4001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS4_INT001_REG"             ,	   0x11800b4001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS4_INT002_REG"             ,	   0x11800b4001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS4_INT003_REG"             ,	   0x11800b4001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800b0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800b0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS0_LINK002_TIMER_COUNT_REG",	   0x11800b0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS0_LINK003_TIMER_COUNT_REG",	   0x11800b0001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS1_LINK000_TIMER_COUNT_REG",	   0x11800b1001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS1_LINK001_TIMER_COUNT_REG",	   0x11800b1001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS1_LINK002_TIMER_COUNT_REG",	   0x11800b1001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS1_LINK003_TIMER_COUNT_REG",	   0x11800b1001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS2_LINK000_TIMER_COUNT_REG",	   0x11800b2001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS2_LINK001_TIMER_COUNT_REG",	   0x11800b2001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS2_LINK002_TIMER_COUNT_REG",	   0x11800b2001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS2_LINK003_TIMER_COUNT_REG",	   0x11800b2001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS3_LINK000_TIMER_COUNT_REG",	   0x11800b3001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS3_LINK001_TIMER_COUNT_REG",	   0x11800b3001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS3_LINK002_TIMER_COUNT_REG",	   0x11800b3001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS3_LINK003_TIMER_COUNT_REG",	   0x11800b3001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS4_LINK000_TIMER_COUNT_REG",	   0x11800b4001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS4_LINK001_TIMER_COUNT_REG",	   0x11800b4001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS4_LINK002_TIMER_COUNT_REG",	   0x11800b4001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS4_LINK003_TIMER_COUNT_REG",	   0x11800b4001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PCS0_LOG_ANL000_REG"         ,	   0x11800b0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS0_LOG_ANL001_REG"         ,	   0x11800b0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS0_LOG_ANL002_REG"         ,	   0x11800b0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS0_LOG_ANL003_REG"         ,	   0x11800b0001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS1_LOG_ANL000_REG"         ,	   0x11800b1001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS1_LOG_ANL001_REG"         ,	   0x11800b1001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS1_LOG_ANL002_REG"         ,	   0x11800b1001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS1_LOG_ANL003_REG"         ,	   0x11800b1001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS2_LOG_ANL000_REG"         ,	   0x11800b2001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS2_LOG_ANL001_REG"         ,	   0x11800b2001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS2_LOG_ANL002_REG"         ,	   0x11800b2001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS2_LOG_ANL003_REG"         ,	   0x11800b2001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS3_LOG_ANL000_REG"         ,	   0x11800b3001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS3_LOG_ANL001_REG"         ,	   0x11800b3001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS3_LOG_ANL002_REG"         ,	   0x11800b3001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS3_LOG_ANL003_REG"         ,	   0x11800b3001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS4_LOG_ANL000_REG"         ,	   0x11800b4001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS4_LOG_ANL001_REG"         ,	   0x11800b4001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS4_LOG_ANL002_REG"         ,	   0x11800b4001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS4_LOG_ANL003_REG"         ,	   0x11800b4001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PCS0_MISC000_CTL_REG"        ,	   0x11800b0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS0_MISC001_CTL_REG"        ,	   0x11800b0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS0_MISC002_CTL_REG"        ,	   0x11800b0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS0_MISC003_CTL_REG"        ,	   0x11800b0001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS1_MISC000_CTL_REG"        ,	   0x11800b1001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS1_MISC001_CTL_REG"        ,	   0x11800b1001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS1_MISC002_CTL_REG"        ,	   0x11800b1001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS1_MISC003_CTL_REG"        ,	   0x11800b1001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS2_MISC000_CTL_REG"        ,	   0x11800b2001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS2_MISC001_CTL_REG"        ,	   0x11800b2001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS2_MISC002_CTL_REG"        ,	   0x11800b2001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS2_MISC003_CTL_REG"        ,	   0x11800b2001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS3_MISC000_CTL_REG"        ,	   0x11800b3001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS3_MISC001_CTL_REG"        ,	   0x11800b3001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS3_MISC002_CTL_REG"        ,	   0x11800b3001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS3_MISC003_CTL_REG"        ,	   0x11800b3001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS4_MISC000_CTL_REG"        ,	   0x11800b4001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS4_MISC001_CTL_REG"        ,	   0x11800b4001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS4_MISC002_CTL_REG"        ,	   0x11800b4001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS4_MISC003_CTL_REG"        ,	   0x11800b4001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800b0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800b0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS0_MR002_CONTROL_REG"      ,	   0x11800b0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS0_MR003_CONTROL_REG"      ,	   0x11800b0001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS1_MR000_CONTROL_REG"      ,	   0x11800b1001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS1_MR001_CONTROL_REG"      ,	   0x11800b1001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS1_MR002_CONTROL_REG"      ,	   0x11800b1001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS1_MR003_CONTROL_REG"      ,	   0x11800b1001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS2_MR000_CONTROL_REG"      ,	   0x11800b2001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS2_MR001_CONTROL_REG"      ,	   0x11800b2001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS2_MR002_CONTROL_REG"      ,	   0x11800b2001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS2_MR003_CONTROL_REG"      ,	   0x11800b2001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS3_MR000_CONTROL_REG"      ,	   0x11800b3001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS3_MR001_CONTROL_REG"      ,	   0x11800b3001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS3_MR002_CONTROL_REG"      ,	   0x11800b3001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS3_MR003_CONTROL_REG"      ,	   0x11800b3001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS4_MR000_CONTROL_REG"      ,	   0x11800b4001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS4_MR001_CONTROL_REG"      ,	   0x11800b4001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS4_MR002_CONTROL_REG"      ,	   0x11800b4001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS4_MR003_CONTROL_REG"      ,	   0x11800b4001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PCS0_MR000_STATUS_REG"       ,	   0x11800b0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS0_MR001_STATUS_REG"       ,	   0x11800b0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS0_MR002_STATUS_REG"       ,	   0x11800b0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS0_MR003_STATUS_REG"       ,	   0x11800b0001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS1_MR000_STATUS_REG"       ,	   0x11800b1001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS1_MR001_STATUS_REG"       ,	   0x11800b1001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS1_MR002_STATUS_REG"       ,	   0x11800b1001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS1_MR003_STATUS_REG"       ,	   0x11800b1001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS2_MR000_STATUS_REG"       ,	   0x11800b2001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS2_MR001_STATUS_REG"       ,	   0x11800b2001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS2_MR002_STATUS_REG"       ,	   0x11800b2001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS2_MR003_STATUS_REG"       ,	   0x11800b2001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS3_MR000_STATUS_REG"       ,	   0x11800b3001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS3_MR001_STATUS_REG"       ,	   0x11800b3001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS3_MR002_STATUS_REG"       ,	   0x11800b3001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS3_MR003_STATUS_REG"       ,	   0x11800b3001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS4_MR000_STATUS_REG"       ,	   0x11800b4001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS4_MR001_STATUS_REG"       ,	   0x11800b4001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS4_MR002_STATUS_REG"       ,	   0x11800b4001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS4_MR003_STATUS_REG"       ,	   0x11800b4001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PCS0_RX000_STATES_REG"       ,	   0x11800b0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS0_RX001_STATES_REG"       ,	   0x11800b0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS0_RX002_STATES_REG"       ,	   0x11800b0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS0_RX003_STATES_REG"       ,	   0x11800b0001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS1_RX000_STATES_REG"       ,	   0x11800b1001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS1_RX001_STATES_REG"       ,	   0x11800b1001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS1_RX002_STATES_REG"       ,	   0x11800b1001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS1_RX003_STATES_REG"       ,	   0x11800b1001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS2_RX000_STATES_REG"       ,	   0x11800b2001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS2_RX001_STATES_REG"       ,	   0x11800b2001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS2_RX002_STATES_REG"       ,	   0x11800b2001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS2_RX003_STATES_REG"       ,	   0x11800b2001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS3_RX000_STATES_REG"       ,	   0x11800b3001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS3_RX001_STATES_REG"       ,	   0x11800b3001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS3_RX002_STATES_REG"       ,	   0x11800b3001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS3_RX003_STATES_REG"       ,	   0x11800b3001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS4_RX000_STATES_REG"       ,	   0x11800b4001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS4_RX001_STATES_REG"       ,	   0x11800b4001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS4_RX002_STATES_REG"       ,	   0x11800b4001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS4_RX003_STATES_REG"       ,	   0x11800b4001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PCS0_RX000_SYNC_REG"         ,	   0x11800b0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS0_RX001_SYNC_REG"         ,	   0x11800b0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS0_RX002_SYNC_REG"         ,	   0x11800b0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS0_RX003_SYNC_REG"         ,	   0x11800b0001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS1_RX000_SYNC_REG"         ,	   0x11800b1001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS1_RX001_SYNC_REG"         ,	   0x11800b1001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS1_RX002_SYNC_REG"         ,	   0x11800b1001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS1_RX003_SYNC_REG"         ,	   0x11800b1001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS2_RX000_SYNC_REG"         ,	   0x11800b2001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS2_RX001_SYNC_REG"         ,	   0x11800b2001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS2_RX002_SYNC_REG"         ,	   0x11800b2001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS2_RX003_SYNC_REG"         ,	   0x11800b2001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS3_RX000_SYNC_REG"         ,	   0x11800b3001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS3_RX001_SYNC_REG"         ,	   0x11800b3001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS3_RX002_SYNC_REG"         ,	   0x11800b3001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS3_RX003_SYNC_REG"         ,	   0x11800b3001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS4_RX000_SYNC_REG"         ,	   0x11800b4001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS4_RX001_SYNC_REG"         ,	   0x11800b4001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS4_RX002_SYNC_REG"         ,	   0x11800b4001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS4_RX003_SYNC_REG"         ,	   0x11800b4001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800b0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800b0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS0_SGM002_AN_ADV_REG"      ,	   0x11800b0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS0_SGM003_AN_ADV_REG"      ,	   0x11800b0001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS1_SGM000_AN_ADV_REG"      ,	   0x11800b1001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS1_SGM001_AN_ADV_REG"      ,	   0x11800b1001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS1_SGM002_AN_ADV_REG"      ,	   0x11800b1001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS1_SGM003_AN_ADV_REG"      ,	   0x11800b1001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS2_SGM000_AN_ADV_REG"      ,	   0x11800b2001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS2_SGM001_AN_ADV_REG"      ,	   0x11800b2001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS2_SGM002_AN_ADV_REG"      ,	   0x11800b2001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS2_SGM003_AN_ADV_REG"      ,	   0x11800b2001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS3_SGM000_AN_ADV_REG"      ,	   0x11800b3001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS3_SGM001_AN_ADV_REG"      ,	   0x11800b3001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS3_SGM002_AN_ADV_REG"      ,	   0x11800b3001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS3_SGM003_AN_ADV_REG"      ,	   0x11800b3001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS4_SGM000_AN_ADV_REG"      ,	   0x11800b4001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS4_SGM001_AN_ADV_REG"      ,	   0x11800b4001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS4_SGM002_AN_ADV_REG"      ,	   0x11800b4001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS4_SGM003_AN_ADV_REG"      ,	   0x11800b4001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800b0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800b0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS0_SGM002_LP_ADV_REG"      ,	   0x11800b0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS0_SGM003_LP_ADV_REG"      ,	   0x11800b0001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS1_SGM000_LP_ADV_REG"      ,	   0x11800b1001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS1_SGM001_LP_ADV_REG"      ,	   0x11800b1001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS1_SGM002_LP_ADV_REG"      ,	   0x11800b1001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS1_SGM003_LP_ADV_REG"      ,	   0x11800b1001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS2_SGM000_LP_ADV_REG"      ,	   0x11800b2001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS2_SGM001_LP_ADV_REG"      ,	   0x11800b2001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS2_SGM002_LP_ADV_REG"      ,	   0x11800b2001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS2_SGM003_LP_ADV_REG"      ,	   0x11800b2001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS3_SGM000_LP_ADV_REG"      ,	   0x11800b3001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS3_SGM001_LP_ADV_REG"      ,	   0x11800b3001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS3_SGM002_LP_ADV_REG"      ,	   0x11800b3001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS3_SGM003_LP_ADV_REG"      ,	   0x11800b3001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS4_SGM000_LP_ADV_REG"      ,	   0x11800b4001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS4_SGM001_LP_ADV_REG"      ,	   0x11800b4001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS4_SGM002_LP_ADV_REG"      ,	   0x11800b4001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS4_SGM003_LP_ADV_REG"      ,	   0x11800b4001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PCS0_TX000_STATES_REG"       ,	   0x11800b0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS0_TX001_STATES_REG"       ,	   0x11800b0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS0_TX002_STATES_REG"       ,	   0x11800b0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS0_TX003_STATES_REG"       ,	   0x11800b0001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS1_TX000_STATES_REG"       ,	   0x11800b1001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS1_TX001_STATES_REG"       ,	   0x11800b1001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS1_TX002_STATES_REG"       ,	   0x11800b1001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS1_TX003_STATES_REG"       ,	   0x11800b1001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS2_TX000_STATES_REG"       ,	   0x11800b2001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS2_TX001_STATES_REG"       ,	   0x11800b2001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS2_TX002_STATES_REG"       ,	   0x11800b2001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS2_TX003_STATES_REG"       ,	   0x11800b2001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS3_TX000_STATES_REG"       ,	   0x11800b3001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS3_TX001_STATES_REG"       ,	   0x11800b3001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS3_TX002_STATES_REG"       ,	   0x11800b3001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS3_TX003_STATES_REG"       ,	   0x11800b3001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS4_TX000_STATES_REG"       ,	   0x11800b4001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS4_TX001_STATES_REG"       ,	   0x11800b4001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS4_TX002_STATES_REG"       ,	   0x11800b4001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS4_TX003_STATES_REG"       ,	   0x11800b4001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800b0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800b0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS0_TX_RX002_POLARITY_REG"  ,	   0x11800b0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS0_TX_RX003_POLARITY_REG"  ,	   0x11800b0001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS1_TX_RX000_POLARITY_REG"  ,	   0x11800b1001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS1_TX_RX001_POLARITY_REG"  ,	   0x11800b1001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS1_TX_RX002_POLARITY_REG"  ,	   0x11800b1001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS1_TX_RX003_POLARITY_REG"  ,	   0x11800b1001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS2_TX_RX000_POLARITY_REG"  ,	   0x11800b2001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS2_TX_RX001_POLARITY_REG"  ,	   0x11800b2001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS2_TX_RX002_POLARITY_REG"  ,	   0x11800b2001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS2_TX_RX003_POLARITY_REG"  ,	   0x11800b2001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS3_TX_RX000_POLARITY_REG"  ,	   0x11800b3001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS3_TX_RX001_POLARITY_REG"  ,	   0x11800b3001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS3_TX_RX002_POLARITY_REG"  ,	   0x11800b3001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS3_TX_RX003_POLARITY_REG"  ,	   0x11800b3001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS4_TX_RX000_POLARITY_REG"  ,	   0x11800b4001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS4_TX_RX001_POLARITY_REG"  ,	   0x11800b4001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS4_TX_RX002_POLARITY_REG"  ,	   0x11800b4001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCS4_TX_RX003_POLARITY_REG"  ,	   0x11800b4001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PCSX0_10GBX_STATUS_REG"      ,	   0x11800b0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PCSX1_10GBX_STATUS_REG"      ,	   0x11800b1000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PCSX2_10GBX_STATUS_REG"      ,	   0x11800b2000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PCSX3_10GBX_STATUS_REG"      ,	   0x11800b3000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PCSX4_10GBX_STATUS_REG"      ,	   0x11800b4000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PCSX0_BIST_STATUS_REG"       ,	   0x11800b0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	972},
+	{"PCSX1_BIST_STATUS_REG"       ,	   0x11800b1000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	972},
+	{"PCSX2_BIST_STATUS_REG"       ,	   0x11800b2000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	972},
+	{"PCSX3_BIST_STATUS_REG"       ,	   0x11800b3000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	972},
+	{"PCSX4_BIST_STATUS_REG"       ,	   0x11800b4000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	972},
+	{"PCSX0_BIT_LOCK_STATUS_REG"   ,	   0x11800b0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	973},
+	{"PCSX1_BIT_LOCK_STATUS_REG"   ,	   0x11800b1000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	973},
+	{"PCSX2_BIT_LOCK_STATUS_REG"   ,	   0x11800b2000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	973},
+	{"PCSX3_BIT_LOCK_STATUS_REG"   ,	   0x11800b3000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	973},
+	{"PCSX4_BIT_LOCK_STATUS_REG"   ,	   0x11800b4000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	973},
+	{"PCSX0_CONTROL1_REG"          ,	   0x11800b0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	974},
+	{"PCSX1_CONTROL1_REG"          ,	   0x11800b1000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	974},
+	{"PCSX2_CONTROL1_REG"          ,	   0x11800b2000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	974},
+	{"PCSX3_CONTROL1_REG"          ,	   0x11800b3000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	974},
+	{"PCSX4_CONTROL1_REG"          ,	   0x11800b4000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	974},
+	{"PCSX0_CONTROL2_REG"          ,	   0x11800b0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	975},
+	{"PCSX1_CONTROL2_REG"          ,	   0x11800b1000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	975},
+	{"PCSX2_CONTROL2_REG"          ,	   0x11800b2000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	975},
+	{"PCSX3_CONTROL2_REG"          ,	   0x11800b3000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	975},
+	{"PCSX4_CONTROL2_REG"          ,	   0x11800b4000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	975},
+	{"PCSX0_INT_EN_REG"            ,	   0x11800b0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	976},
+	{"PCSX1_INT_EN_REG"            ,	   0x11800b1000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	976},
+	{"PCSX2_INT_EN_REG"            ,	   0x11800b2000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	976},
+	{"PCSX3_INT_EN_REG"            ,	   0x11800b3000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	976},
+	{"PCSX4_INT_EN_REG"            ,	   0x11800b4000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	976},
+	{"PCSX0_INT_REG"               ,	   0x11800b0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	977},
+	{"PCSX1_INT_REG"               ,	   0x11800b1000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	977},
+	{"PCSX2_INT_REG"               ,	   0x11800b2000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	977},
+	{"PCSX3_INT_REG"               ,	   0x11800b3000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	977},
+	{"PCSX4_INT_REG"               ,	   0x11800b4000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	977},
+	{"PCSX0_LOG_ANL_REG"           ,	   0x11800b0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	978},
+	{"PCSX1_LOG_ANL_REG"           ,	   0x11800b1000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	978},
+	{"PCSX2_LOG_ANL_REG"           ,	   0x11800b2000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	978},
+	{"PCSX3_LOG_ANL_REG"           ,	   0x11800b3000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	978},
+	{"PCSX4_LOG_ANL_REG"           ,	   0x11800b4000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	978},
+	{"PCSX0_MISC_CTL_REG"          ,	   0x11800b0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	979},
+	{"PCSX1_MISC_CTL_REG"          ,	   0x11800b1000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	979},
+	{"PCSX2_MISC_CTL_REG"          ,	   0x11800b2000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	979},
+	{"PCSX3_MISC_CTL_REG"          ,	   0x11800b3000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	979},
+	{"PCSX4_MISC_CTL_REG"          ,	   0x11800b4000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	979},
+	{"PCSX0_RX_SYNC_STATES_REG"    ,	   0x11800b0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	980},
+	{"PCSX1_RX_SYNC_STATES_REG"    ,	   0x11800b1000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	980},
+	{"PCSX2_RX_SYNC_STATES_REG"    ,	   0x11800b2000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	980},
+	{"PCSX3_RX_SYNC_STATES_REG"    ,	   0x11800b3000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	980},
+	{"PCSX4_RX_SYNC_STATES_REG"    ,	   0x11800b4000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	980},
+	{"PCSX0_SPD_ABIL_REG"          ,	   0x11800b0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	981},
+	{"PCSX1_SPD_ABIL_REG"          ,	   0x11800b1000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	981},
+	{"PCSX2_SPD_ABIL_REG"          ,	   0x11800b2000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	981},
+	{"PCSX3_SPD_ABIL_REG"          ,	   0x11800b3000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	981},
+	{"PCSX4_SPD_ABIL_REG"          ,	   0x11800b4000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	981},
+	{"PCSX0_STATUS1_REG"           ,	   0x11800b0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	982},
+	{"PCSX1_STATUS1_REG"           ,	   0x11800b1000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	982},
+	{"PCSX2_STATUS1_REG"           ,	   0x11800b2000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	982},
+	{"PCSX3_STATUS1_REG"           ,	   0x11800b3000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	982},
+	{"PCSX4_STATUS1_REG"           ,	   0x11800b4000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	982},
+	{"PCSX0_STATUS2_REG"           ,	   0x11800b0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	983},
+	{"PCSX1_STATUS2_REG"           ,	   0x11800b1000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	983},
+	{"PCSX2_STATUS2_REG"           ,	   0x11800b2000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	983},
+	{"PCSX3_STATUS2_REG"           ,	   0x11800b3000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	983},
+	{"PCSX4_STATUS2_REG"           ,	   0x11800b4000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	983},
+	{"PCSX0_TX_RX_POLARITY_REG"    ,	   0x11800b0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	984},
+	{"PCSX1_TX_RX_POLARITY_REG"    ,	   0x11800b1000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	984},
+	{"PCSX2_TX_RX_POLARITY_REG"    ,	   0x11800b2000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	984},
+	{"PCSX3_TX_RX_POLARITY_REG"    ,	   0x11800b3000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	984},
+	{"PCSX4_TX_RX_POLARITY_REG"    ,	   0x11800b4000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	984},
+	{"PCSX0_TX_RX_STATES_REG"      ,	   0x11800b0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	985},
+	{"PCSX1_TX_RX_STATES_REG"      ,	   0x11800b1000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	985},
+	{"PCSX2_TX_RX_STATES_REG"      ,	   0x11800b2000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	985},
+	{"PCSX3_TX_RX_STATES_REG"      ,	   0x11800b3000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	985},
+	{"PCSX4_TX_RX_STATES_REG"      ,	   0x11800b4000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	985},
+	{"PEM0_BAR1_INDEX000"          ,	   0x11800c00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM0_BAR1_INDEX001"          ,	   0x11800c00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM0_BAR1_INDEX002"          ,	   0x11800c00000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM0_BAR1_INDEX003"          ,	   0x11800c00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM0_BAR1_INDEX004"          ,	   0x11800c00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM0_BAR1_INDEX005"          ,	   0x11800c00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM0_BAR1_INDEX006"          ,	   0x11800c00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM0_BAR1_INDEX007"          ,	   0x11800c00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM0_BAR1_INDEX008"          ,	   0x11800c00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM0_BAR1_INDEX009"          ,	   0x11800c00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM0_BAR1_INDEX010"          ,	   0x11800c00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM0_BAR1_INDEX011"          ,	   0x11800c0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM0_BAR1_INDEX012"          ,	   0x11800c0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM0_BAR1_INDEX013"          ,	   0x11800c0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM0_BAR1_INDEX014"          ,	   0x11800c0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM0_BAR1_INDEX015"          ,	   0x11800c0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM1_BAR1_INDEX000"          ,	   0x11800c10000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM1_BAR1_INDEX001"          ,	   0x11800c10000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM1_BAR1_INDEX002"          ,	   0x11800c10000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM1_BAR1_INDEX003"          ,	   0x11800c10000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM1_BAR1_INDEX004"          ,	   0x11800c10000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM1_BAR1_INDEX005"          ,	   0x11800c10000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM1_BAR1_INDEX006"          ,	   0x11800c10000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM1_BAR1_INDEX007"          ,	   0x11800c10000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM1_BAR1_INDEX008"          ,	   0x11800c10000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM1_BAR1_INDEX009"          ,	   0x11800c10000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM1_BAR1_INDEX010"          ,	   0x11800c10000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM1_BAR1_INDEX011"          ,	   0x11800c1000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM1_BAR1_INDEX012"          ,	   0x11800c1000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM1_BAR1_INDEX013"          ,	   0x11800c1000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM1_BAR1_INDEX014"          ,	   0x11800c1000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM1_BAR1_INDEX015"          ,	   0x11800c1000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"PEM0_BAR2_MASK"              ,	   0x11800c0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	987},
+	{"PEM1_BAR2_MASK"              ,	   0x11800c1000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	987},
+	{"PEM0_BAR_CTL"                ,	   0x11800c0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"PEM1_BAR_CTL"                ,	   0x11800c1000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"PEM0_BIST_STATUS"            ,	   0x11800c0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"PEM1_BIST_STATUS"            ,	   0x11800c1000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"PEM0_BIST_STATUS2"           ,	   0x11800c0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	990},
+	{"PEM1_BIST_STATUS2"           ,	   0x11800c1000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	990},
+	{"PEM0_CFG_RD"                 ,	   0x11800c0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	991},
+	{"PEM1_CFG_RD"                 ,	   0x11800c1000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	991},
+	{"PEM0_CFG_WR"                 ,	   0x11800c0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	992},
+	{"PEM1_CFG_WR"                 ,	   0x11800c1000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	992},
+	{"PEM0_CPL_LUT_VALID"          ,	   0x11800c0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	993},
+	{"PEM1_CPL_LUT_VALID"          ,	   0x11800c1000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	993},
+	{"PEM0_CTL_STATUS"             ,	   0x11800c0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"PEM1_CTL_STATUS"             ,	   0x11800c1000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"PEM0_DBG_INFO"               ,	   0x11800c0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"PEM1_DBG_INFO"               ,	   0x11800c1000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"PEM0_DBG_INFO_EN"            ,	   0x11800c00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	996},
+	{"PEM1_DBG_INFO_EN"            ,	   0x11800c10000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	996},
+	{"PEM0_DIAG_STATUS"            ,	   0x11800c0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
+	{"PEM1_DIAG_STATUS"            ,	   0x11800c1000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
+	{"PEM0_INB_READ_CREDITS"       ,	   0x11800c0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"PEM1_INB_READ_CREDITS"       ,	   0x11800c1000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"PEM0_INT_ENB"                ,	   0x11800c0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"PEM1_INT_ENB"                ,	   0x11800c1000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"PEM0_INT_ENB_INT"            ,	   0x11800c0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1000},
+	{"PEM1_INT_ENB_INT"            ,	   0x11800c1000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1000},
+	{"PEM0_INT_SUM"                ,	   0x11800c0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1001},
+	{"PEM1_INT_SUM"                ,	   0x11800c1000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1001},
+	{"PEM0_P2N_BAR0_START"         ,	   0x11800c0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
+	{"PEM1_P2N_BAR0_START"         ,	   0x11800c1000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
+	{"PEM0_P2N_BAR1_START"         ,	   0x11800c0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
+	{"PEM1_P2N_BAR1_START"         ,	   0x11800c1000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
+	{"PEM0_P2N_BAR2_START"         ,	   0x11800c0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PEM1_P2N_BAR2_START"         ,	   0x11800c1000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"PEM0_P2P_BAR000_END"         ,	   0x11800c0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PEM0_P2P_BAR001_END"         ,	   0x11800c0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PEM0_P2P_BAR002_END"         ,	   0x11800c0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PEM0_P2P_BAR003_END"         ,	   0x11800c0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PEM1_P2P_BAR000_END"         ,	   0x11800c1000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PEM1_P2P_BAR001_END"         ,	   0x11800c1000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PEM1_P2P_BAR002_END"         ,	   0x11800c1000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PEM1_P2P_BAR003_END"         ,	   0x11800c1000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"PEM0_P2P_BAR000_START"       ,	   0x11800c0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PEM0_P2P_BAR001_START"       ,	   0x11800c0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PEM0_P2P_BAR002_START"       ,	   0x11800c0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PEM0_P2P_BAR003_START"       ,	   0x11800c0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PEM1_P2P_BAR000_START"       ,	   0x11800c1000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PEM1_P2P_BAR001_START"       ,	   0x11800c1000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PEM1_P2P_BAR002_START"       ,	   0x11800c1000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PEM1_P2P_BAR003_START"       ,	   0x11800c1000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"PEM0_TLP_CREDITS"            ,	   0x11800c0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PEM1_TLP_CREDITS"            ,	   0x11800c1000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"PIP_ALT_SKIP_CFG0"           ,	   0x11800a0002a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"PIP_ALT_SKIP_CFG1"           ,	   0x11800a0002a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"PIP_ALT_SKIP_CFG2"           ,	   0x11800a0002a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"PIP_ALT_SKIP_CFG3"           ,	   0x11800a0002a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"PIP_BCK_PRS"                 ,	   0x11800a0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1009},
+	{"PIP_BIST_STATUS"             ,	   0x11800a0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"PIP_BSEL_EXT_CFG0"           ,	   0x11800a0002800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_BSEL_EXT_CFG1"           ,	   0x11800a0002810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_BSEL_EXT_CFG2"           ,	   0x11800a0002820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_BSEL_EXT_CFG3"           ,	   0x11800a0002830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"PIP_BSEL_EXT_POS0"           ,	   0x11800a0002808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_BSEL_EXT_POS1"           ,	   0x11800a0002818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_BSEL_EXT_POS2"           ,	   0x11800a0002828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_BSEL_EXT_POS3"           ,	   0x11800a0002838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"PIP_BSEL_TBL_ENT0"           ,	   0x11800a0003000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT1"           ,	   0x11800a0003008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT2"           ,	   0x11800a0003010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT3"           ,	   0x11800a0003018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT4"           ,	   0x11800a0003020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT5"           ,	   0x11800a0003028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT6"           ,	   0x11800a0003030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT7"           ,	   0x11800a0003038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT8"           ,	   0x11800a0003040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT9"           ,	   0x11800a0003048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT10"          ,	   0x11800a0003050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT11"          ,	   0x11800a0003058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT12"          ,	   0x11800a0003060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT13"          ,	   0x11800a0003068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT14"          ,	   0x11800a0003070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT15"          ,	   0x11800a0003078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT16"          ,	   0x11800a0003080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT17"          ,	   0x11800a0003088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT18"          ,	   0x11800a0003090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT19"          ,	   0x11800a0003098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT20"          ,	   0x11800a00030a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT21"          ,	   0x11800a00030a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT22"          ,	   0x11800a00030b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT23"          ,	   0x11800a00030b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT24"          ,	   0x11800a00030c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT25"          ,	   0x11800a00030c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT26"          ,	   0x11800a00030d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT27"          ,	   0x11800a00030d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT28"          ,	   0x11800a00030e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT29"          ,	   0x11800a00030e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT30"          ,	   0x11800a00030f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT31"          ,	   0x11800a00030f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT32"          ,	   0x11800a0003100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT33"          ,	   0x11800a0003108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT34"          ,	   0x11800a0003110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT35"          ,	   0x11800a0003118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT36"          ,	   0x11800a0003120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT37"          ,	   0x11800a0003128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT38"          ,	   0x11800a0003130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT39"          ,	   0x11800a0003138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT40"          ,	   0x11800a0003140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT41"          ,	   0x11800a0003148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT42"          ,	   0x11800a0003150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT43"          ,	   0x11800a0003158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT44"          ,	   0x11800a0003160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT45"          ,	   0x11800a0003168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT46"          ,	   0x11800a0003170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT47"          ,	   0x11800a0003178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT48"          ,	   0x11800a0003180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT49"          ,	   0x11800a0003188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT50"          ,	   0x11800a0003190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT51"          ,	   0x11800a0003198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT52"          ,	   0x11800a00031a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT53"          ,	   0x11800a00031a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT54"          ,	   0x11800a00031b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT55"          ,	   0x11800a00031b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT56"          ,	   0x11800a00031c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT57"          ,	   0x11800a00031c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT58"          ,	   0x11800a00031d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT59"          ,	   0x11800a00031d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT60"          ,	   0x11800a00031e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT61"          ,	   0x11800a00031e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT62"          ,	   0x11800a00031f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT63"          ,	   0x11800a00031f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT64"          ,	   0x11800a0003200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT65"          ,	   0x11800a0003208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT66"          ,	   0x11800a0003210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT67"          ,	   0x11800a0003218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT68"          ,	   0x11800a0003220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT69"          ,	   0x11800a0003228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT70"          ,	   0x11800a0003230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT71"          ,	   0x11800a0003238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT72"          ,	   0x11800a0003240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT73"          ,	   0x11800a0003248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT74"          ,	   0x11800a0003250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT75"          ,	   0x11800a0003258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT76"          ,	   0x11800a0003260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT77"          ,	   0x11800a0003268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT78"          ,	   0x11800a0003270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT79"          ,	   0x11800a0003278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT80"          ,	   0x11800a0003280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT81"          ,	   0x11800a0003288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT82"          ,	   0x11800a0003290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT83"          ,	   0x11800a0003298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT84"          ,	   0x11800a00032a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT85"          ,	   0x11800a00032a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT86"          ,	   0x11800a00032b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT87"          ,	   0x11800a00032b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT88"          ,	   0x11800a00032c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT89"          ,	   0x11800a00032c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT90"          ,	   0x11800a00032d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT91"          ,	   0x11800a00032d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT92"          ,	   0x11800a00032e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT93"          ,	   0x11800a00032e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT94"          ,	   0x11800a00032f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT95"          ,	   0x11800a00032f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT96"          ,	   0x11800a0003300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT97"          ,	   0x11800a0003308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT98"          ,	   0x11800a0003310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT99"          ,	   0x11800a0003318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT100"         ,	   0x11800a0003320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT101"         ,	   0x11800a0003328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT102"         ,	   0x11800a0003330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT103"         ,	   0x11800a0003338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT104"         ,	   0x11800a0003340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT105"         ,	   0x11800a0003348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT106"         ,	   0x11800a0003350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT107"         ,	   0x11800a0003358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT108"         ,	   0x11800a0003360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT109"         ,	   0x11800a0003368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT110"         ,	   0x11800a0003370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT111"         ,	   0x11800a0003378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT112"         ,	   0x11800a0003380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT113"         ,	   0x11800a0003388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT114"         ,	   0x11800a0003390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT115"         ,	   0x11800a0003398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT116"         ,	   0x11800a00033a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT117"         ,	   0x11800a00033a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT118"         ,	   0x11800a00033b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT119"         ,	   0x11800a00033b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT120"         ,	   0x11800a00033c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT121"         ,	   0x11800a00033c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT122"         ,	   0x11800a00033d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT123"         ,	   0x11800a00033d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT124"         ,	   0x11800a00033e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT125"         ,	   0x11800a00033e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT126"         ,	   0x11800a00033f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT127"         ,	   0x11800a00033f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT128"         ,	   0x11800a0003400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT129"         ,	   0x11800a0003408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT130"         ,	   0x11800a0003410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT131"         ,	   0x11800a0003418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT132"         ,	   0x11800a0003420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT133"         ,	   0x11800a0003428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT134"         ,	   0x11800a0003430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT135"         ,	   0x11800a0003438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT136"         ,	   0x11800a0003440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT137"         ,	   0x11800a0003448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT138"         ,	   0x11800a0003450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT139"         ,	   0x11800a0003458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT140"         ,	   0x11800a0003460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT141"         ,	   0x11800a0003468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT142"         ,	   0x11800a0003470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT143"         ,	   0x11800a0003478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT144"         ,	   0x11800a0003480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT145"         ,	   0x11800a0003488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT146"         ,	   0x11800a0003490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT147"         ,	   0x11800a0003498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT148"         ,	   0x11800a00034a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT149"         ,	   0x11800a00034a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT150"         ,	   0x11800a00034b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT151"         ,	   0x11800a00034b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT152"         ,	   0x11800a00034c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT153"         ,	   0x11800a00034c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT154"         ,	   0x11800a00034d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT155"         ,	   0x11800a00034d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT156"         ,	   0x11800a00034e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT157"         ,	   0x11800a00034e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT158"         ,	   0x11800a00034f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT159"         ,	   0x11800a00034f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT160"         ,	   0x11800a0003500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT161"         ,	   0x11800a0003508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT162"         ,	   0x11800a0003510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT163"         ,	   0x11800a0003518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT164"         ,	   0x11800a0003520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT165"         ,	   0x11800a0003528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT166"         ,	   0x11800a0003530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT167"         ,	   0x11800a0003538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT168"         ,	   0x11800a0003540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT169"         ,	   0x11800a0003548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT170"         ,	   0x11800a0003550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT171"         ,	   0x11800a0003558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT172"         ,	   0x11800a0003560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT173"         ,	   0x11800a0003568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT174"         ,	   0x11800a0003570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT175"         ,	   0x11800a0003578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT176"         ,	   0x11800a0003580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT177"         ,	   0x11800a0003588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT178"         ,	   0x11800a0003590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT179"         ,	   0x11800a0003598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT180"         ,	   0x11800a00035a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT181"         ,	   0x11800a00035a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT182"         ,	   0x11800a00035b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT183"         ,	   0x11800a00035b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT184"         ,	   0x11800a00035c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT185"         ,	   0x11800a00035c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT186"         ,	   0x11800a00035d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT187"         ,	   0x11800a00035d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT188"         ,	   0x11800a00035e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT189"         ,	   0x11800a00035e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT190"         ,	   0x11800a00035f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT191"         ,	   0x11800a00035f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT192"         ,	   0x11800a0003600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT193"         ,	   0x11800a0003608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT194"         ,	   0x11800a0003610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT195"         ,	   0x11800a0003618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT196"         ,	   0x11800a0003620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT197"         ,	   0x11800a0003628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT198"         ,	   0x11800a0003630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT199"         ,	   0x11800a0003638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT200"         ,	   0x11800a0003640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT201"         ,	   0x11800a0003648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT202"         ,	   0x11800a0003650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT203"         ,	   0x11800a0003658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT204"         ,	   0x11800a0003660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT205"         ,	   0x11800a0003668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT206"         ,	   0x11800a0003670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT207"         ,	   0x11800a0003678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT208"         ,	   0x11800a0003680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT209"         ,	   0x11800a0003688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT210"         ,	   0x11800a0003690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT211"         ,	   0x11800a0003698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT212"         ,	   0x11800a00036a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT213"         ,	   0x11800a00036a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT214"         ,	   0x11800a00036b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT215"         ,	   0x11800a00036b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT216"         ,	   0x11800a00036c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT217"         ,	   0x11800a00036c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT218"         ,	   0x11800a00036d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT219"         ,	   0x11800a00036d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT220"         ,	   0x11800a00036e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT221"         ,	   0x11800a00036e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT222"         ,	   0x11800a00036f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT223"         ,	   0x11800a00036f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT224"         ,	   0x11800a0003700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT225"         ,	   0x11800a0003708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT226"         ,	   0x11800a0003710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT227"         ,	   0x11800a0003718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT228"         ,	   0x11800a0003720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT229"         ,	   0x11800a0003728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT230"         ,	   0x11800a0003730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT231"         ,	   0x11800a0003738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT232"         ,	   0x11800a0003740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT233"         ,	   0x11800a0003748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT234"         ,	   0x11800a0003750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT235"         ,	   0x11800a0003758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT236"         ,	   0x11800a0003760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT237"         ,	   0x11800a0003768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT238"         ,	   0x11800a0003770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT239"         ,	   0x11800a0003778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT240"         ,	   0x11800a0003780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT241"         ,	   0x11800a0003788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT242"         ,	   0x11800a0003790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT243"         ,	   0x11800a0003798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT244"         ,	   0x11800a00037a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT245"         ,	   0x11800a00037a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT246"         ,	   0x11800a00037b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT247"         ,	   0x11800a00037b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT248"         ,	   0x11800a00037c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT249"         ,	   0x11800a00037c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT250"         ,	   0x11800a00037d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT251"         ,	   0x11800a00037d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT252"         ,	   0x11800a00037e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT253"         ,	   0x11800a00037e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT254"         ,	   0x11800a00037f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT255"         ,	   0x11800a00037f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT256"         ,	   0x11800a0003800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT257"         ,	   0x11800a0003808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT258"         ,	   0x11800a0003810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT259"         ,	   0x11800a0003818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT260"         ,	   0x11800a0003820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT261"         ,	   0x11800a0003828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT262"         ,	   0x11800a0003830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT263"         ,	   0x11800a0003838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT264"         ,	   0x11800a0003840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT265"         ,	   0x11800a0003848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT266"         ,	   0x11800a0003850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT267"         ,	   0x11800a0003858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT268"         ,	   0x11800a0003860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT269"         ,	   0x11800a0003868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT270"         ,	   0x11800a0003870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT271"         ,	   0x11800a0003878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT272"         ,	   0x11800a0003880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT273"         ,	   0x11800a0003888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT274"         ,	   0x11800a0003890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT275"         ,	   0x11800a0003898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT276"         ,	   0x11800a00038a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT277"         ,	   0x11800a00038a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT278"         ,	   0x11800a00038b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT279"         ,	   0x11800a00038b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT280"         ,	   0x11800a00038c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT281"         ,	   0x11800a00038c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT282"         ,	   0x11800a00038d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT283"         ,	   0x11800a00038d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT284"         ,	   0x11800a00038e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT285"         ,	   0x11800a00038e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT286"         ,	   0x11800a00038f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT287"         ,	   0x11800a00038f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT288"         ,	   0x11800a0003900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT289"         ,	   0x11800a0003908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT290"         ,	   0x11800a0003910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT291"         ,	   0x11800a0003918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT292"         ,	   0x11800a0003920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT293"         ,	   0x11800a0003928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT294"         ,	   0x11800a0003930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT295"         ,	   0x11800a0003938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT296"         ,	   0x11800a0003940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT297"         ,	   0x11800a0003948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT298"         ,	   0x11800a0003950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT299"         ,	   0x11800a0003958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT300"         ,	   0x11800a0003960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT301"         ,	   0x11800a0003968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT302"         ,	   0x11800a0003970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT303"         ,	   0x11800a0003978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT304"         ,	   0x11800a0003980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT305"         ,	   0x11800a0003988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT306"         ,	   0x11800a0003990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT307"         ,	   0x11800a0003998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT308"         ,	   0x11800a00039a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT309"         ,	   0x11800a00039a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT310"         ,	   0x11800a00039b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT311"         ,	   0x11800a00039b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT312"         ,	   0x11800a00039c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT313"         ,	   0x11800a00039c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT314"         ,	   0x11800a00039d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT315"         ,	   0x11800a00039d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT316"         ,	   0x11800a00039e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT317"         ,	   0x11800a00039e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT318"         ,	   0x11800a00039f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT319"         ,	   0x11800a00039f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT320"         ,	   0x11800a0003a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT321"         ,	   0x11800a0003a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT322"         ,	   0x11800a0003a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT323"         ,	   0x11800a0003a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT324"         ,	   0x11800a0003a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT325"         ,	   0x11800a0003a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT326"         ,	   0x11800a0003a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT327"         ,	   0x11800a0003a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT328"         ,	   0x11800a0003a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT329"         ,	   0x11800a0003a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT330"         ,	   0x11800a0003a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT331"         ,	   0x11800a0003a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT332"         ,	   0x11800a0003a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT333"         ,	   0x11800a0003a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT334"         ,	   0x11800a0003a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT335"         ,	   0x11800a0003a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT336"         ,	   0x11800a0003a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT337"         ,	   0x11800a0003a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT338"         ,	   0x11800a0003a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT339"         ,	   0x11800a0003a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT340"         ,	   0x11800a0003aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT341"         ,	   0x11800a0003aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT342"         ,	   0x11800a0003ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT343"         ,	   0x11800a0003ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT344"         ,	   0x11800a0003ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT345"         ,	   0x11800a0003ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT346"         ,	   0x11800a0003ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT347"         ,	   0x11800a0003ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT348"         ,	   0x11800a0003ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT349"         ,	   0x11800a0003ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT350"         ,	   0x11800a0003af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT351"         ,	   0x11800a0003af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT352"         ,	   0x11800a0003b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT353"         ,	   0x11800a0003b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT354"         ,	   0x11800a0003b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT355"         ,	   0x11800a0003b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT356"         ,	   0x11800a0003b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT357"         ,	   0x11800a0003b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT358"         ,	   0x11800a0003b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT359"         ,	   0x11800a0003b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT360"         ,	   0x11800a0003b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT361"         ,	   0x11800a0003b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT362"         ,	   0x11800a0003b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT363"         ,	   0x11800a0003b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT364"         ,	   0x11800a0003b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT365"         ,	   0x11800a0003b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT366"         ,	   0x11800a0003b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT367"         ,	   0x11800a0003b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT368"         ,	   0x11800a0003b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT369"         ,	   0x11800a0003b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT370"         ,	   0x11800a0003b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT371"         ,	   0x11800a0003b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT372"         ,	   0x11800a0003ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT373"         ,	   0x11800a0003ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT374"         ,	   0x11800a0003bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT375"         ,	   0x11800a0003bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT376"         ,	   0x11800a0003bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT377"         ,	   0x11800a0003bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT378"         ,	   0x11800a0003bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT379"         ,	   0x11800a0003bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT380"         ,	   0x11800a0003be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT381"         ,	   0x11800a0003be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT382"         ,	   0x11800a0003bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT383"         ,	   0x11800a0003bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT384"         ,	   0x11800a0003c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT385"         ,	   0x11800a0003c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT386"         ,	   0x11800a0003c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT387"         ,	   0x11800a0003c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT388"         ,	   0x11800a0003c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT389"         ,	   0x11800a0003c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT390"         ,	   0x11800a0003c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT391"         ,	   0x11800a0003c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT392"         ,	   0x11800a0003c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT393"         ,	   0x11800a0003c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT394"         ,	   0x11800a0003c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT395"         ,	   0x11800a0003c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT396"         ,	   0x11800a0003c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT397"         ,	   0x11800a0003c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT398"         ,	   0x11800a0003c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT399"         ,	   0x11800a0003c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT400"         ,	   0x11800a0003c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT401"         ,	   0x11800a0003c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT402"         ,	   0x11800a0003c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT403"         ,	   0x11800a0003c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT404"         ,	   0x11800a0003ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT405"         ,	   0x11800a0003ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT406"         ,	   0x11800a0003cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT407"         ,	   0x11800a0003cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT408"         ,	   0x11800a0003cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT409"         ,	   0x11800a0003cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT410"         ,	   0x11800a0003cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT411"         ,	   0x11800a0003cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT412"         ,	   0x11800a0003ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT413"         ,	   0x11800a0003ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT414"         ,	   0x11800a0003cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT415"         ,	   0x11800a0003cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT416"         ,	   0x11800a0003d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT417"         ,	   0x11800a0003d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT418"         ,	   0x11800a0003d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT419"         ,	   0x11800a0003d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT420"         ,	   0x11800a0003d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT421"         ,	   0x11800a0003d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT422"         ,	   0x11800a0003d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT423"         ,	   0x11800a0003d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT424"         ,	   0x11800a0003d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT425"         ,	   0x11800a0003d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT426"         ,	   0x11800a0003d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT427"         ,	   0x11800a0003d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT428"         ,	   0x11800a0003d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT429"         ,	   0x11800a0003d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT430"         ,	   0x11800a0003d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT431"         ,	   0x11800a0003d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT432"         ,	   0x11800a0003d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT433"         ,	   0x11800a0003d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT434"         ,	   0x11800a0003d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT435"         ,	   0x11800a0003d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT436"         ,	   0x11800a0003da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT437"         ,	   0x11800a0003da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT438"         ,	   0x11800a0003db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT439"         ,	   0x11800a0003db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT440"         ,	   0x11800a0003dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT441"         ,	   0x11800a0003dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT442"         ,	   0x11800a0003dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT443"         ,	   0x11800a0003dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT444"         ,	   0x11800a0003de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT445"         ,	   0x11800a0003de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT446"         ,	   0x11800a0003df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT447"         ,	   0x11800a0003df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT448"         ,	   0x11800a0003e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT449"         ,	   0x11800a0003e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT450"         ,	   0x11800a0003e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT451"         ,	   0x11800a0003e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT452"         ,	   0x11800a0003e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT453"         ,	   0x11800a0003e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT454"         ,	   0x11800a0003e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT455"         ,	   0x11800a0003e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT456"         ,	   0x11800a0003e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT457"         ,	   0x11800a0003e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT458"         ,	   0x11800a0003e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT459"         ,	   0x11800a0003e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT460"         ,	   0x11800a0003e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT461"         ,	   0x11800a0003e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT462"         ,	   0x11800a0003e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT463"         ,	   0x11800a0003e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT464"         ,	   0x11800a0003e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT465"         ,	   0x11800a0003e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT466"         ,	   0x11800a0003e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT467"         ,	   0x11800a0003e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT468"         ,	   0x11800a0003ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT469"         ,	   0x11800a0003ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT470"         ,	   0x11800a0003eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT471"         ,	   0x11800a0003eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT472"         ,	   0x11800a0003ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT473"         ,	   0x11800a0003ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT474"         ,	   0x11800a0003ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT475"         ,	   0x11800a0003ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT476"         ,	   0x11800a0003ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT477"         ,	   0x11800a0003ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT478"         ,	   0x11800a0003ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT479"         ,	   0x11800a0003ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT480"         ,	   0x11800a0003f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT481"         ,	   0x11800a0003f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT482"         ,	   0x11800a0003f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT483"         ,	   0x11800a0003f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT484"         ,	   0x11800a0003f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT485"         ,	   0x11800a0003f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT486"         ,	   0x11800a0003f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT487"         ,	   0x11800a0003f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT488"         ,	   0x11800a0003f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT489"         ,	   0x11800a0003f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT490"         ,	   0x11800a0003f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT491"         ,	   0x11800a0003f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT492"         ,	   0x11800a0003f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT493"         ,	   0x11800a0003f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT494"         ,	   0x11800a0003f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT495"         ,	   0x11800a0003f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT496"         ,	   0x11800a0003f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT497"         ,	   0x11800a0003f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT498"         ,	   0x11800a0003f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT499"         ,	   0x11800a0003f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT500"         ,	   0x11800a0003fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT501"         ,	   0x11800a0003fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT502"         ,	   0x11800a0003fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT503"         ,	   0x11800a0003fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT504"         ,	   0x11800a0003fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT505"         ,	   0x11800a0003fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT506"         ,	   0x11800a0003fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT507"         ,	   0x11800a0003fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT508"         ,	   0x11800a0003fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT509"         ,	   0x11800a0003fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT510"         ,	   0x11800a0003ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_BSEL_TBL_ENT511"         ,	   0x11800a0003ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"PIP_CLKEN"                   ,	   0x11800a0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800a0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800a0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800a0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800a0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"PIP_DSA_SRC_GRP"             ,	   0x11800a0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"PIP_DSA_VID_GRP"             ,	   0x11800a0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"PIP_FRM_LEN_CHK0"            ,	   0x11800a0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_FRM_LEN_CHK1"            ,	   0x11800a0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"PIP_GBL_CFG"                 ,	   0x11800a0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"PIP_GBL_CTL"                 ,	   0x11800a0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"PIP_INT_EN"                  ,	   0x11800a0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"PIP_INT_REG"                 ,	   0x11800a0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"PIP_IP_OFFSET"               ,	   0x11800a0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1023},
+	{"PIP_PRI_TBL0"                ,	   0x11800a0004000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL1"                ,	   0x11800a0004008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL2"                ,	   0x11800a0004010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL3"                ,	   0x11800a0004018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL4"                ,	   0x11800a0004020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL5"                ,	   0x11800a0004028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL6"                ,	   0x11800a0004030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL7"                ,	   0x11800a0004038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL8"                ,	   0x11800a0004040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL9"                ,	   0x11800a0004048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL10"               ,	   0x11800a0004050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL11"               ,	   0x11800a0004058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL12"               ,	   0x11800a0004060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL13"               ,	   0x11800a0004068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL14"               ,	   0x11800a0004070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL15"               ,	   0x11800a0004078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL16"               ,	   0x11800a0004080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL17"               ,	   0x11800a0004088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL18"               ,	   0x11800a0004090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL19"               ,	   0x11800a0004098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL20"               ,	   0x11800a00040a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL21"               ,	   0x11800a00040a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL22"               ,	   0x11800a00040b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL23"               ,	   0x11800a00040b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL24"               ,	   0x11800a00040c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL25"               ,	   0x11800a00040c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL26"               ,	   0x11800a00040d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL27"               ,	   0x11800a00040d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL28"               ,	   0x11800a00040e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL29"               ,	   0x11800a00040e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL30"               ,	   0x11800a00040f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL31"               ,	   0x11800a00040f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL32"               ,	   0x11800a0004100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL33"               ,	   0x11800a0004108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL34"               ,	   0x11800a0004110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL35"               ,	   0x11800a0004118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL36"               ,	   0x11800a0004120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL37"               ,	   0x11800a0004128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL38"               ,	   0x11800a0004130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL39"               ,	   0x11800a0004138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL40"               ,	   0x11800a0004140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL41"               ,	   0x11800a0004148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL42"               ,	   0x11800a0004150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL43"               ,	   0x11800a0004158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL44"               ,	   0x11800a0004160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL45"               ,	   0x11800a0004168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL46"               ,	   0x11800a0004170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL47"               ,	   0x11800a0004178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL48"               ,	   0x11800a0004180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL49"               ,	   0x11800a0004188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL50"               ,	   0x11800a0004190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL51"               ,	   0x11800a0004198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL52"               ,	   0x11800a00041a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL53"               ,	   0x11800a00041a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL54"               ,	   0x11800a00041b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL55"               ,	   0x11800a00041b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL56"               ,	   0x11800a00041c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL57"               ,	   0x11800a00041c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL58"               ,	   0x11800a00041d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL59"               ,	   0x11800a00041d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL60"               ,	   0x11800a00041e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL61"               ,	   0x11800a00041e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL62"               ,	   0x11800a00041f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL63"               ,	   0x11800a00041f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL64"               ,	   0x11800a0004200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL65"               ,	   0x11800a0004208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL66"               ,	   0x11800a0004210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL67"               ,	   0x11800a0004218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL68"               ,	   0x11800a0004220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL69"               ,	   0x11800a0004228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL70"               ,	   0x11800a0004230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL71"               ,	   0x11800a0004238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL72"               ,	   0x11800a0004240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL73"               ,	   0x11800a0004248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL74"               ,	   0x11800a0004250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL75"               ,	   0x11800a0004258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL76"               ,	   0x11800a0004260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL77"               ,	   0x11800a0004268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL78"               ,	   0x11800a0004270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL79"               ,	   0x11800a0004278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL80"               ,	   0x11800a0004280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL81"               ,	   0x11800a0004288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL82"               ,	   0x11800a0004290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL83"               ,	   0x11800a0004298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL84"               ,	   0x11800a00042a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL85"               ,	   0x11800a00042a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL86"               ,	   0x11800a00042b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL87"               ,	   0x11800a00042b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL88"               ,	   0x11800a00042c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL89"               ,	   0x11800a00042c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL90"               ,	   0x11800a00042d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL91"               ,	   0x11800a00042d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL92"               ,	   0x11800a00042e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL93"               ,	   0x11800a00042e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL94"               ,	   0x11800a00042f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL95"               ,	   0x11800a00042f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL96"               ,	   0x11800a0004300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL97"               ,	   0x11800a0004308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL98"               ,	   0x11800a0004310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL99"               ,	   0x11800a0004318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL100"              ,	   0x11800a0004320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL101"              ,	   0x11800a0004328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL102"              ,	   0x11800a0004330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL103"              ,	   0x11800a0004338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL104"              ,	   0x11800a0004340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL105"              ,	   0x11800a0004348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL106"              ,	   0x11800a0004350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL107"              ,	   0x11800a0004358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL108"              ,	   0x11800a0004360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL109"              ,	   0x11800a0004368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL110"              ,	   0x11800a0004370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL111"              ,	   0x11800a0004378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL112"              ,	   0x11800a0004380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL113"              ,	   0x11800a0004388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL114"              ,	   0x11800a0004390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL115"              ,	   0x11800a0004398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL116"              ,	   0x11800a00043a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL117"              ,	   0x11800a00043a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL118"              ,	   0x11800a00043b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL119"              ,	   0x11800a00043b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL120"              ,	   0x11800a00043c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL121"              ,	   0x11800a00043c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL122"              ,	   0x11800a00043d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL123"              ,	   0x11800a00043d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL124"              ,	   0x11800a00043e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL125"              ,	   0x11800a00043e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL126"              ,	   0x11800a00043f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL127"              ,	   0x11800a00043f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL128"              ,	   0x11800a0004400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL129"              ,	   0x11800a0004408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL130"              ,	   0x11800a0004410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL131"              ,	   0x11800a0004418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL132"              ,	   0x11800a0004420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL133"              ,	   0x11800a0004428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL134"              ,	   0x11800a0004430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL135"              ,	   0x11800a0004438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL136"              ,	   0x11800a0004440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL137"              ,	   0x11800a0004448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL138"              ,	   0x11800a0004450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL139"              ,	   0x11800a0004458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL140"              ,	   0x11800a0004460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL141"              ,	   0x11800a0004468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL142"              ,	   0x11800a0004470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL143"              ,	   0x11800a0004478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL144"              ,	   0x11800a0004480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL145"              ,	   0x11800a0004488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL146"              ,	   0x11800a0004490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL147"              ,	   0x11800a0004498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL148"              ,	   0x11800a00044a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL149"              ,	   0x11800a00044a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL150"              ,	   0x11800a00044b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL151"              ,	   0x11800a00044b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL152"              ,	   0x11800a00044c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL153"              ,	   0x11800a00044c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL154"              ,	   0x11800a00044d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL155"              ,	   0x11800a00044d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL156"              ,	   0x11800a00044e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL157"              ,	   0x11800a00044e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL158"              ,	   0x11800a00044f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL159"              ,	   0x11800a00044f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL160"              ,	   0x11800a0004500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL161"              ,	   0x11800a0004508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL162"              ,	   0x11800a0004510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL163"              ,	   0x11800a0004518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL164"              ,	   0x11800a0004520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL165"              ,	   0x11800a0004528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL166"              ,	   0x11800a0004530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL167"              ,	   0x11800a0004538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL168"              ,	   0x11800a0004540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL169"              ,	   0x11800a0004548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL170"              ,	   0x11800a0004550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL171"              ,	   0x11800a0004558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL172"              ,	   0x11800a0004560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL173"              ,	   0x11800a0004568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL174"              ,	   0x11800a0004570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL175"              ,	   0x11800a0004578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL176"              ,	   0x11800a0004580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL177"              ,	   0x11800a0004588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL178"              ,	   0x11800a0004590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL179"              ,	   0x11800a0004598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL180"              ,	   0x11800a00045a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL181"              ,	   0x11800a00045a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL182"              ,	   0x11800a00045b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL183"              ,	   0x11800a00045b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL184"              ,	   0x11800a00045c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL185"              ,	   0x11800a00045c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL186"              ,	   0x11800a00045d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL187"              ,	   0x11800a00045d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL188"              ,	   0x11800a00045e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL189"              ,	   0x11800a00045e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL190"              ,	   0x11800a00045f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL191"              ,	   0x11800a00045f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL192"              ,	   0x11800a0004600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL193"              ,	   0x11800a0004608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL194"              ,	   0x11800a0004610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL195"              ,	   0x11800a0004618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL196"              ,	   0x11800a0004620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL197"              ,	   0x11800a0004628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL198"              ,	   0x11800a0004630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL199"              ,	   0x11800a0004638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL200"              ,	   0x11800a0004640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL201"              ,	   0x11800a0004648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL202"              ,	   0x11800a0004650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL203"              ,	   0x11800a0004658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL204"              ,	   0x11800a0004660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL205"              ,	   0x11800a0004668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL206"              ,	   0x11800a0004670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL207"              ,	   0x11800a0004678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL208"              ,	   0x11800a0004680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL209"              ,	   0x11800a0004688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL210"              ,	   0x11800a0004690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL211"              ,	   0x11800a0004698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL212"              ,	   0x11800a00046a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL213"              ,	   0x11800a00046a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL214"              ,	   0x11800a00046b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL215"              ,	   0x11800a00046b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL216"              ,	   0x11800a00046c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL217"              ,	   0x11800a00046c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL218"              ,	   0x11800a00046d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL219"              ,	   0x11800a00046d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL220"              ,	   0x11800a00046e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL221"              ,	   0x11800a00046e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL222"              ,	   0x11800a00046f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL223"              ,	   0x11800a00046f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL224"              ,	   0x11800a0004700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL225"              ,	   0x11800a0004708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL226"              ,	   0x11800a0004710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL227"              ,	   0x11800a0004718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL228"              ,	   0x11800a0004720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL229"              ,	   0x11800a0004728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL230"              ,	   0x11800a0004730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL231"              ,	   0x11800a0004738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL232"              ,	   0x11800a0004740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL233"              ,	   0x11800a0004748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL234"              ,	   0x11800a0004750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL235"              ,	   0x11800a0004758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL236"              ,	   0x11800a0004760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL237"              ,	   0x11800a0004768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL238"              ,	   0x11800a0004770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL239"              ,	   0x11800a0004778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL240"              ,	   0x11800a0004780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL241"              ,	   0x11800a0004788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL242"              ,	   0x11800a0004790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL243"              ,	   0x11800a0004798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL244"              ,	   0x11800a00047a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL245"              ,	   0x11800a00047a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL246"              ,	   0x11800a00047b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL247"              ,	   0x11800a00047b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL248"              ,	   0x11800a00047c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL249"              ,	   0x11800a00047c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL250"              ,	   0x11800a00047d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL251"              ,	   0x11800a00047d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL252"              ,	   0x11800a00047e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL253"              ,	   0x11800a00047e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL254"              ,	   0x11800a00047f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRI_TBL255"              ,	   0x11800a00047f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"PIP_PRT_CFG0"                ,	   0x11800a0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG1"                ,	   0x11800a0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG2"                ,	   0x11800a0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG3"                ,	   0x11800a0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG4"                ,	   0x11800a0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG5"                ,	   0x11800a0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG6"                ,	   0x11800a0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG7"                ,	   0x11800a0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG8"                ,	   0x11800a0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG9"                ,	   0x11800a0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG10"               ,	   0x11800a0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG11"               ,	   0x11800a0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG12"               ,	   0x11800a0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG13"               ,	   0x11800a0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG14"               ,	   0x11800a0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG15"               ,	   0x11800a0000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG16"               ,	   0x11800a0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG17"               ,	   0x11800a0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG18"               ,	   0x11800a0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG19"               ,	   0x11800a0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG20"               ,	   0x11800a00002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG21"               ,	   0x11800a00002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG22"               ,	   0x11800a00002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG23"               ,	   0x11800a00002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG24"               ,	   0x11800a00002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG25"               ,	   0x11800a00002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG26"               ,	   0x11800a00002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG27"               ,	   0x11800a00002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG28"               ,	   0x11800a00002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG29"               ,	   0x11800a00002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG30"               ,	   0x11800a00002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG31"               ,	   0x11800a00002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG32"               ,	   0x11800a0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG33"               ,	   0x11800a0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG34"               ,	   0x11800a0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG35"               ,	   0x11800a0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG36"               ,	   0x11800a0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG37"               ,	   0x11800a0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG38"               ,	   0x11800a0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG39"               ,	   0x11800a0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG40"               ,	   0x11800a0000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG41"               ,	   0x11800a0000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG42"               ,	   0x11800a0000350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG43"               ,	   0x11800a0000358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG44"               ,	   0x11800a0000360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG45"               ,	   0x11800a0000368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG46"               ,	   0x11800a0000370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG47"               ,	   0x11800a0000378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG48"               ,	   0x11800a0000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG49"               ,	   0x11800a0000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG50"               ,	   0x11800a0000390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG51"               ,	   0x11800a0000398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG52"               ,	   0x11800a00003a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG53"               ,	   0x11800a00003a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG54"               ,	   0x11800a00003b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG55"               ,	   0x11800a00003b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG56"               ,	   0x11800a00003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG57"               ,	   0x11800a00003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG58"               ,	   0x11800a00003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG59"               ,	   0x11800a00003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG60"               ,	   0x11800a00003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG61"               ,	   0x11800a00003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG62"               ,	   0x11800a00003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFG63"               ,	   0x11800a00003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"PIP_PRT_CFGB0"               ,	   0x11800a0008000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB1"               ,	   0x11800a0008008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB2"               ,	   0x11800a0008010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB3"               ,	   0x11800a0008018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB4"               ,	   0x11800a0008020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB5"               ,	   0x11800a0008028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB6"               ,	   0x11800a0008030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB7"               ,	   0x11800a0008038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB8"               ,	   0x11800a0008040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB9"               ,	   0x11800a0008048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB10"              ,	   0x11800a0008050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB11"              ,	   0x11800a0008058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB12"              ,	   0x11800a0008060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB13"              ,	   0x11800a0008068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB14"              ,	   0x11800a0008070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB15"              ,	   0x11800a0008078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB16"              ,	   0x11800a0008080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB17"              ,	   0x11800a0008088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB18"              ,	   0x11800a0008090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB19"              ,	   0x11800a0008098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB20"              ,	   0x11800a00080a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB21"              ,	   0x11800a00080a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB22"              ,	   0x11800a00080b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB23"              ,	   0x11800a00080b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB24"              ,	   0x11800a00080c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB25"              ,	   0x11800a00080c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB26"              ,	   0x11800a00080d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB27"              ,	   0x11800a00080d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB28"              ,	   0x11800a00080e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB29"              ,	   0x11800a00080e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB30"              ,	   0x11800a00080f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB31"              ,	   0x11800a00080f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB32"              ,	   0x11800a0008100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB33"              ,	   0x11800a0008108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB34"              ,	   0x11800a0008110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB35"              ,	   0x11800a0008118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB36"              ,	   0x11800a0008120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB37"              ,	   0x11800a0008128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB38"              ,	   0x11800a0008130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB39"              ,	   0x11800a0008138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB40"              ,	   0x11800a0008140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB41"              ,	   0x11800a0008148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB42"              ,	   0x11800a0008150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB43"              ,	   0x11800a0008158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB44"              ,	   0x11800a0008160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB45"              ,	   0x11800a0008168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB46"              ,	   0x11800a0008170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB47"              ,	   0x11800a0008178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB48"              ,	   0x11800a0008180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB49"              ,	   0x11800a0008188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB50"              ,	   0x11800a0008190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB51"              ,	   0x11800a0008198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB52"              ,	   0x11800a00081a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB53"              ,	   0x11800a00081a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB54"              ,	   0x11800a00081b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB55"              ,	   0x11800a00081b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB56"              ,	   0x11800a00081c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB57"              ,	   0x11800a00081c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB58"              ,	   0x11800a00081d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB59"              ,	   0x11800a00081d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB60"              ,	   0x11800a00081e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB61"              ,	   0x11800a00081e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB62"              ,	   0x11800a00081f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_CFGB63"              ,	   0x11800a00081f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"PIP_PRT_TAG0"                ,	   0x11800a0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG1"                ,	   0x11800a0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG2"                ,	   0x11800a0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG3"                ,	   0x11800a0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG4"                ,	   0x11800a0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG5"                ,	   0x11800a0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG6"                ,	   0x11800a0000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG7"                ,	   0x11800a0000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG8"                ,	   0x11800a0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG9"                ,	   0x11800a0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG10"               ,	   0x11800a0000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG11"               ,	   0x11800a0000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG12"               ,	   0x11800a0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG13"               ,	   0x11800a0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG14"               ,	   0x11800a0000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG15"               ,	   0x11800a0000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG16"               ,	   0x11800a0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG17"               ,	   0x11800a0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG18"               ,	   0x11800a0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG19"               ,	   0x11800a0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG20"               ,	   0x11800a00004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG21"               ,	   0x11800a00004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG22"               ,	   0x11800a00004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG23"               ,	   0x11800a00004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG24"               ,	   0x11800a00004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG25"               ,	   0x11800a00004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG26"               ,	   0x11800a00004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG27"               ,	   0x11800a00004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG28"               ,	   0x11800a00004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG29"               ,	   0x11800a00004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG30"               ,	   0x11800a00004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG31"               ,	   0x11800a00004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG32"               ,	   0x11800a0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG33"               ,	   0x11800a0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG34"               ,	   0x11800a0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG35"               ,	   0x11800a0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG36"               ,	   0x11800a0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG37"               ,	   0x11800a0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG38"               ,	   0x11800a0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG39"               ,	   0x11800a0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG40"               ,	   0x11800a0000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG41"               ,	   0x11800a0000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG42"               ,	   0x11800a0000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG43"               ,	   0x11800a0000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG44"               ,	   0x11800a0000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG45"               ,	   0x11800a0000568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG46"               ,	   0x11800a0000570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG47"               ,	   0x11800a0000578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG48"               ,	   0x11800a0000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG49"               ,	   0x11800a0000588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG50"               ,	   0x11800a0000590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG51"               ,	   0x11800a0000598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG52"               ,	   0x11800a00005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG53"               ,	   0x11800a00005a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG54"               ,	   0x11800a00005b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG55"               ,	   0x11800a00005b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG56"               ,	   0x11800a00005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG57"               ,	   0x11800a00005c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG58"               ,	   0x11800a00005d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG59"               ,	   0x11800a00005d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG60"               ,	   0x11800a00005e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG61"               ,	   0x11800a00005e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG62"               ,	   0x11800a00005f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_PRT_TAG63"               ,	   0x11800a00005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"PIP_QOS_WATCH0"              ,	   0x11800a0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_QOS_WATCH1"              ,	   0x11800a0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_QOS_WATCH2"              ,	   0x11800a0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_QOS_WATCH3"              ,	   0x11800a0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_QOS_WATCH4"              ,	   0x11800a0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_QOS_WATCH5"              ,	   0x11800a0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_QOS_WATCH6"              ,	   0x11800a0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_QOS_WATCH7"              ,	   0x11800a0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"PIP_RAW_WORD"                ,	   0x11800a00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1029},
+	{"PIP_SFT_RST"                 ,	   0x11800a0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1030},
+	{"PIP_STAT0_0"                 ,	   0x11800a0040000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_1"                 ,	   0x11800a0040080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_2"                 ,	   0x11800a0040100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_3"                 ,	   0x11800a0040180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_4"                 ,	   0x11800a0040200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_5"                 ,	   0x11800a0040280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_6"                 ,	   0x11800a0040300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_7"                 ,	   0x11800a0040380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_8"                 ,	   0x11800a0040400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_9"                 ,	   0x11800a0040480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_10"                ,	   0x11800a0040500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_11"                ,	   0x11800a0040580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_12"                ,	   0x11800a0040600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_13"                ,	   0x11800a0040680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_14"                ,	   0x11800a0040700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_15"                ,	   0x11800a0040780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_16"                ,	   0x11800a0040800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_17"                ,	   0x11800a0040880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_18"                ,	   0x11800a0040900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_19"                ,	   0x11800a0040980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_20"                ,	   0x11800a0040a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_21"                ,	   0x11800a0040a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_22"                ,	   0x11800a0040b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_23"                ,	   0x11800a0040b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_24"                ,	   0x11800a0040c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_25"                ,	   0x11800a0040c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_26"                ,	   0x11800a0040d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_27"                ,	   0x11800a0040d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_28"                ,	   0x11800a0040e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_29"                ,	   0x11800a0040e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_30"                ,	   0x11800a0040f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_31"                ,	   0x11800a0040f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_32"                ,	   0x11800a0041000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_33"                ,	   0x11800a0041080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_34"                ,	   0x11800a0041100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_35"                ,	   0x11800a0041180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_36"                ,	   0x11800a0041200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_37"                ,	   0x11800a0041280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_38"                ,	   0x11800a0041300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_39"                ,	   0x11800a0041380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_40"                ,	   0x11800a0041400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_41"                ,	   0x11800a0041480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_42"                ,	   0x11800a0041500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_43"                ,	   0x11800a0041580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_44"                ,	   0x11800a0041600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_45"                ,	   0x11800a0041680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_46"                ,	   0x11800a0041700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_47"                ,	   0x11800a0041780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_48"                ,	   0x11800a0041800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_49"                ,	   0x11800a0041880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_50"                ,	   0x11800a0041900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_51"                ,	   0x11800a0041980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_52"                ,	   0x11800a0041a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_53"                ,	   0x11800a0041a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_54"                ,	   0x11800a0041b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_55"                ,	   0x11800a0041b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_56"                ,	   0x11800a0041c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_57"                ,	   0x11800a0041c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_58"                ,	   0x11800a0041d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_59"                ,	   0x11800a0041d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_60"                ,	   0x11800a0041e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_61"                ,	   0x11800a0041e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_62"                ,	   0x11800a0041f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT0_63"                ,	   0x11800a0041f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"PIP_STAT10_0"                ,	   0x11800a0040050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_1"                ,	   0x11800a00400d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_2"                ,	   0x11800a0040150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_3"                ,	   0x11800a00401d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_4"                ,	   0x11800a0040250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_5"                ,	   0x11800a00402d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_6"                ,	   0x11800a0040350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_7"                ,	   0x11800a00403d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_8"                ,	   0x11800a0040450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_9"                ,	   0x11800a00404d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_10"               ,	   0x11800a0040550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_11"               ,	   0x11800a00405d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_12"               ,	   0x11800a0040650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_13"               ,	   0x11800a00406d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_14"               ,	   0x11800a0040750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_15"               ,	   0x11800a00407d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_16"               ,	   0x11800a0040850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_17"               ,	   0x11800a00408d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_18"               ,	   0x11800a0040950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_19"               ,	   0x11800a00409d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_20"               ,	   0x11800a0040a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_21"               ,	   0x11800a0040ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_22"               ,	   0x11800a0040b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_23"               ,	   0x11800a0040bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_24"               ,	   0x11800a0040c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_25"               ,	   0x11800a0040cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_26"               ,	   0x11800a0040d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_27"               ,	   0x11800a0040dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_28"               ,	   0x11800a0040e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_29"               ,	   0x11800a0040ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_30"               ,	   0x11800a0040f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_31"               ,	   0x11800a0040fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_32"               ,	   0x11800a0041050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_33"               ,	   0x11800a00410d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_34"               ,	   0x11800a0041150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_35"               ,	   0x11800a00411d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_36"               ,	   0x11800a0041250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_37"               ,	   0x11800a00412d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_38"               ,	   0x11800a0041350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_39"               ,	   0x11800a00413d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_40"               ,	   0x11800a0041450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_41"               ,	   0x11800a00414d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_42"               ,	   0x11800a0041550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_43"               ,	   0x11800a00415d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_44"               ,	   0x11800a0041650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_45"               ,	   0x11800a00416d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_46"               ,	   0x11800a0041750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_47"               ,	   0x11800a00417d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_48"               ,	   0x11800a0041850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_49"               ,	   0x11800a00418d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_50"               ,	   0x11800a0041950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_51"               ,	   0x11800a00419d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_52"               ,	   0x11800a0041a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_53"               ,	   0x11800a0041ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_54"               ,	   0x11800a0041b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_55"               ,	   0x11800a0041bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_56"               ,	   0x11800a0041c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_57"               ,	   0x11800a0041cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_58"               ,	   0x11800a0041d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_59"               ,	   0x11800a0041dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_60"               ,	   0x11800a0041e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_61"               ,	   0x11800a0041ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_62"               ,	   0x11800a0041f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT10_63"               ,	   0x11800a0041fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"PIP_STAT11_0"                ,	   0x11800a0040058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_1"                ,	   0x11800a00400d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_2"                ,	   0x11800a0040158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_3"                ,	   0x11800a00401d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_4"                ,	   0x11800a0040258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_5"                ,	   0x11800a00402d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_6"                ,	   0x11800a0040358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_7"                ,	   0x11800a00403d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_8"                ,	   0x11800a0040458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_9"                ,	   0x11800a00404d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_10"               ,	   0x11800a0040558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_11"               ,	   0x11800a00405d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_12"               ,	   0x11800a0040658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_13"               ,	   0x11800a00406d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_14"               ,	   0x11800a0040758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_15"               ,	   0x11800a00407d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_16"               ,	   0x11800a0040858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_17"               ,	   0x11800a00408d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_18"               ,	   0x11800a0040958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_19"               ,	   0x11800a00409d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_20"               ,	   0x11800a0040a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_21"               ,	   0x11800a0040ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_22"               ,	   0x11800a0040b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_23"               ,	   0x11800a0040bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_24"               ,	   0x11800a0040c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_25"               ,	   0x11800a0040cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_26"               ,	   0x11800a0040d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_27"               ,	   0x11800a0040dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_28"               ,	   0x11800a0040e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_29"               ,	   0x11800a0040ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_30"               ,	   0x11800a0040f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_31"               ,	   0x11800a0040fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_32"               ,	   0x11800a0041058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_33"               ,	   0x11800a00410d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_34"               ,	   0x11800a0041158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_35"               ,	   0x11800a00411d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_36"               ,	   0x11800a0041258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_37"               ,	   0x11800a00412d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_38"               ,	   0x11800a0041358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_39"               ,	   0x11800a00413d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_40"               ,	   0x11800a0041458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_41"               ,	   0x11800a00414d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_42"               ,	   0x11800a0041558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_43"               ,	   0x11800a00415d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_44"               ,	   0x11800a0041658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_45"               ,	   0x11800a00416d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_46"               ,	   0x11800a0041758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_47"               ,	   0x11800a00417d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_48"               ,	   0x11800a0041858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_49"               ,	   0x11800a00418d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_50"               ,	   0x11800a0041958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_51"               ,	   0x11800a00419d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_52"               ,	   0x11800a0041a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_53"               ,	   0x11800a0041ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_54"               ,	   0x11800a0041b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_55"               ,	   0x11800a0041bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_56"               ,	   0x11800a0041c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_57"               ,	   0x11800a0041cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_58"               ,	   0x11800a0041d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_59"               ,	   0x11800a0041dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_60"               ,	   0x11800a0041e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_61"               ,	   0x11800a0041ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_62"               ,	   0x11800a0041f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT11_63"               ,	   0x11800a0041fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"PIP_STAT1_0"                 ,	   0x11800a0040008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_1"                 ,	   0x11800a0040088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_2"                 ,	   0x11800a0040108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_3"                 ,	   0x11800a0040188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_4"                 ,	   0x11800a0040208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_5"                 ,	   0x11800a0040288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_6"                 ,	   0x11800a0040308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_7"                 ,	   0x11800a0040388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_8"                 ,	   0x11800a0040408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_9"                 ,	   0x11800a0040488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_10"                ,	   0x11800a0040508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_11"                ,	   0x11800a0040588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_12"                ,	   0x11800a0040608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_13"                ,	   0x11800a0040688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_14"                ,	   0x11800a0040708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_15"                ,	   0x11800a0040788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_16"                ,	   0x11800a0040808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_17"                ,	   0x11800a0040888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_18"                ,	   0x11800a0040908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_19"                ,	   0x11800a0040988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_20"                ,	   0x11800a0040a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_21"                ,	   0x11800a0040a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_22"                ,	   0x11800a0040b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_23"                ,	   0x11800a0040b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_24"                ,	   0x11800a0040c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_25"                ,	   0x11800a0040c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_26"                ,	   0x11800a0040d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_27"                ,	   0x11800a0040d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_28"                ,	   0x11800a0040e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_29"                ,	   0x11800a0040e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_30"                ,	   0x11800a0040f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_31"                ,	   0x11800a0040f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_32"                ,	   0x11800a0041008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_33"                ,	   0x11800a0041088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_34"                ,	   0x11800a0041108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_35"                ,	   0x11800a0041188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_36"                ,	   0x11800a0041208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_37"                ,	   0x11800a0041288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_38"                ,	   0x11800a0041308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_39"                ,	   0x11800a0041388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_40"                ,	   0x11800a0041408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_41"                ,	   0x11800a0041488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_42"                ,	   0x11800a0041508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_43"                ,	   0x11800a0041588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_44"                ,	   0x11800a0041608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_45"                ,	   0x11800a0041688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_46"                ,	   0x11800a0041708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_47"                ,	   0x11800a0041788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_48"                ,	   0x11800a0041808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_49"                ,	   0x11800a0041888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_50"                ,	   0x11800a0041908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_51"                ,	   0x11800a0041988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_52"                ,	   0x11800a0041a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_53"                ,	   0x11800a0041a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_54"                ,	   0x11800a0041b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_55"                ,	   0x11800a0041b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_56"                ,	   0x11800a0041c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_57"                ,	   0x11800a0041c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_58"                ,	   0x11800a0041d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_59"                ,	   0x11800a0041d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_60"                ,	   0x11800a0041e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_61"                ,	   0x11800a0041e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_62"                ,	   0x11800a0041f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT1_63"                ,	   0x11800a0041f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"PIP_STAT2_0"                 ,	   0x11800a0040010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_1"                 ,	   0x11800a0040090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_2"                 ,	   0x11800a0040110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_3"                 ,	   0x11800a0040190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_4"                 ,	   0x11800a0040210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_5"                 ,	   0x11800a0040290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_6"                 ,	   0x11800a0040310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_7"                 ,	   0x11800a0040390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_8"                 ,	   0x11800a0040410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_9"                 ,	   0x11800a0040490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_10"                ,	   0x11800a0040510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_11"                ,	   0x11800a0040590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_12"                ,	   0x11800a0040610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_13"                ,	   0x11800a0040690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_14"                ,	   0x11800a0040710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_15"                ,	   0x11800a0040790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_16"                ,	   0x11800a0040810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_17"                ,	   0x11800a0040890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_18"                ,	   0x11800a0040910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_19"                ,	   0x11800a0040990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_20"                ,	   0x11800a0040a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_21"                ,	   0x11800a0040a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_22"                ,	   0x11800a0040b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_23"                ,	   0x11800a0040b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_24"                ,	   0x11800a0040c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_25"                ,	   0x11800a0040c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_26"                ,	   0x11800a0040d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_27"                ,	   0x11800a0040d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_28"                ,	   0x11800a0040e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_29"                ,	   0x11800a0040e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_30"                ,	   0x11800a0040f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_31"                ,	   0x11800a0040f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_32"                ,	   0x11800a0041010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_33"                ,	   0x11800a0041090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_34"                ,	   0x11800a0041110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_35"                ,	   0x11800a0041190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_36"                ,	   0x11800a0041210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_37"                ,	   0x11800a0041290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_38"                ,	   0x11800a0041310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_39"                ,	   0x11800a0041390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_40"                ,	   0x11800a0041410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_41"                ,	   0x11800a0041490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_42"                ,	   0x11800a0041510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_43"                ,	   0x11800a0041590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_44"                ,	   0x11800a0041610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_45"                ,	   0x11800a0041690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_46"                ,	   0x11800a0041710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_47"                ,	   0x11800a0041790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_48"                ,	   0x11800a0041810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_49"                ,	   0x11800a0041890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_50"                ,	   0x11800a0041910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_51"                ,	   0x11800a0041990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_52"                ,	   0x11800a0041a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_53"                ,	   0x11800a0041a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_54"                ,	   0x11800a0041b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_55"                ,	   0x11800a0041b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_56"                ,	   0x11800a0041c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_57"                ,	   0x11800a0041c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_58"                ,	   0x11800a0041d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_59"                ,	   0x11800a0041d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_60"                ,	   0x11800a0041e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_61"                ,	   0x11800a0041e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_62"                ,	   0x11800a0041f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT2_63"                ,	   0x11800a0041f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"PIP_STAT3_0"                 ,	   0x11800a0040018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_1"                 ,	   0x11800a0040098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_2"                 ,	   0x11800a0040118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_3"                 ,	   0x11800a0040198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_4"                 ,	   0x11800a0040218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_5"                 ,	   0x11800a0040298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_6"                 ,	   0x11800a0040318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_7"                 ,	   0x11800a0040398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_8"                 ,	   0x11800a0040418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_9"                 ,	   0x11800a0040498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_10"                ,	   0x11800a0040518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_11"                ,	   0x11800a0040598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_12"                ,	   0x11800a0040618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_13"                ,	   0x11800a0040698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_14"                ,	   0x11800a0040718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_15"                ,	   0x11800a0040798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_16"                ,	   0x11800a0040818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_17"                ,	   0x11800a0040898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_18"                ,	   0x11800a0040918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_19"                ,	   0x11800a0040998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_20"                ,	   0x11800a0040a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_21"                ,	   0x11800a0040a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_22"                ,	   0x11800a0040b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_23"                ,	   0x11800a0040b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_24"                ,	   0x11800a0040c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_25"                ,	   0x11800a0040c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_26"                ,	   0x11800a0040d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_27"                ,	   0x11800a0040d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_28"                ,	   0x11800a0040e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_29"                ,	   0x11800a0040e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_30"                ,	   0x11800a0040f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_31"                ,	   0x11800a0040f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_32"                ,	   0x11800a0041018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_33"                ,	   0x11800a0041098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_34"                ,	   0x11800a0041118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_35"                ,	   0x11800a0041198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_36"                ,	   0x11800a0041218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_37"                ,	   0x11800a0041298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_38"                ,	   0x11800a0041318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_39"                ,	   0x11800a0041398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_40"                ,	   0x11800a0041418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_41"                ,	   0x11800a0041498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_42"                ,	   0x11800a0041518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_43"                ,	   0x11800a0041598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_44"                ,	   0x11800a0041618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_45"                ,	   0x11800a0041698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_46"                ,	   0x11800a0041718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_47"                ,	   0x11800a0041798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_48"                ,	   0x11800a0041818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_49"                ,	   0x11800a0041898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_50"                ,	   0x11800a0041918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_51"                ,	   0x11800a0041998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_52"                ,	   0x11800a0041a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_53"                ,	   0x11800a0041a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_54"                ,	   0x11800a0041b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_55"                ,	   0x11800a0041b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_56"                ,	   0x11800a0041c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_57"                ,	   0x11800a0041c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_58"                ,	   0x11800a0041d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_59"                ,	   0x11800a0041d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_60"                ,	   0x11800a0041e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_61"                ,	   0x11800a0041e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_62"                ,	   0x11800a0041f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT3_63"                ,	   0x11800a0041f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"PIP_STAT4_0"                 ,	   0x11800a0040020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_1"                 ,	   0x11800a00400a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_2"                 ,	   0x11800a0040120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_3"                 ,	   0x11800a00401a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_4"                 ,	   0x11800a0040220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_5"                 ,	   0x11800a00402a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_6"                 ,	   0x11800a0040320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_7"                 ,	   0x11800a00403a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_8"                 ,	   0x11800a0040420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_9"                 ,	   0x11800a00404a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_10"                ,	   0x11800a0040520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_11"                ,	   0x11800a00405a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_12"                ,	   0x11800a0040620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_13"                ,	   0x11800a00406a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_14"                ,	   0x11800a0040720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_15"                ,	   0x11800a00407a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_16"                ,	   0x11800a0040820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_17"                ,	   0x11800a00408a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_18"                ,	   0x11800a0040920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_19"                ,	   0x11800a00409a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_20"                ,	   0x11800a0040a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_21"                ,	   0x11800a0040aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_22"                ,	   0x11800a0040b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_23"                ,	   0x11800a0040ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_24"                ,	   0x11800a0040c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_25"                ,	   0x11800a0040ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_26"                ,	   0x11800a0040d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_27"                ,	   0x11800a0040da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_28"                ,	   0x11800a0040e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_29"                ,	   0x11800a0040ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_30"                ,	   0x11800a0040f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_31"                ,	   0x11800a0040fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_32"                ,	   0x11800a0041020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_33"                ,	   0x11800a00410a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_34"                ,	   0x11800a0041120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_35"                ,	   0x11800a00411a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_36"                ,	   0x11800a0041220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_37"                ,	   0x11800a00412a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_38"                ,	   0x11800a0041320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_39"                ,	   0x11800a00413a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_40"                ,	   0x11800a0041420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_41"                ,	   0x11800a00414a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_42"                ,	   0x11800a0041520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_43"                ,	   0x11800a00415a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_44"                ,	   0x11800a0041620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_45"                ,	   0x11800a00416a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_46"                ,	   0x11800a0041720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_47"                ,	   0x11800a00417a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_48"                ,	   0x11800a0041820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_49"                ,	   0x11800a00418a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_50"                ,	   0x11800a0041920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_51"                ,	   0x11800a00419a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_52"                ,	   0x11800a0041a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_53"                ,	   0x11800a0041aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_54"                ,	   0x11800a0041b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_55"                ,	   0x11800a0041ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_56"                ,	   0x11800a0041c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_57"                ,	   0x11800a0041ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_58"                ,	   0x11800a0041d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_59"                ,	   0x11800a0041da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_60"                ,	   0x11800a0041e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_61"                ,	   0x11800a0041ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_62"                ,	   0x11800a0041f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT4_63"                ,	   0x11800a0041fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1037},
+	{"PIP_STAT5_0"                 ,	   0x11800a0040028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_1"                 ,	   0x11800a00400a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_2"                 ,	   0x11800a0040128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_3"                 ,	   0x11800a00401a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_4"                 ,	   0x11800a0040228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_5"                 ,	   0x11800a00402a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_6"                 ,	   0x11800a0040328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_7"                 ,	   0x11800a00403a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_8"                 ,	   0x11800a0040428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_9"                 ,	   0x11800a00404a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_10"                ,	   0x11800a0040528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_11"                ,	   0x11800a00405a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_12"                ,	   0x11800a0040628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_13"                ,	   0x11800a00406a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_14"                ,	   0x11800a0040728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_15"                ,	   0x11800a00407a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_16"                ,	   0x11800a0040828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_17"                ,	   0x11800a00408a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_18"                ,	   0x11800a0040928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_19"                ,	   0x11800a00409a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_20"                ,	   0x11800a0040a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_21"                ,	   0x11800a0040aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_22"                ,	   0x11800a0040b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_23"                ,	   0x11800a0040ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_24"                ,	   0x11800a0040c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_25"                ,	   0x11800a0040ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_26"                ,	   0x11800a0040d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_27"                ,	   0x11800a0040da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_28"                ,	   0x11800a0040e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_29"                ,	   0x11800a0040ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_30"                ,	   0x11800a0040f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_31"                ,	   0x11800a0040fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_32"                ,	   0x11800a0041028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_33"                ,	   0x11800a00410a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_34"                ,	   0x11800a0041128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_35"                ,	   0x11800a00411a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_36"                ,	   0x11800a0041228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_37"                ,	   0x11800a00412a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_38"                ,	   0x11800a0041328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_39"                ,	   0x11800a00413a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_40"                ,	   0x11800a0041428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_41"                ,	   0x11800a00414a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_42"                ,	   0x11800a0041528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_43"                ,	   0x11800a00415a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_44"                ,	   0x11800a0041628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_45"                ,	   0x11800a00416a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_46"                ,	   0x11800a0041728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_47"                ,	   0x11800a00417a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_48"                ,	   0x11800a0041828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_49"                ,	   0x11800a00418a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_50"                ,	   0x11800a0041928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_51"                ,	   0x11800a00419a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_52"                ,	   0x11800a0041a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_53"                ,	   0x11800a0041aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_54"                ,	   0x11800a0041b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_55"                ,	   0x11800a0041ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_56"                ,	   0x11800a0041c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_57"                ,	   0x11800a0041ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_58"                ,	   0x11800a0041d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_59"                ,	   0x11800a0041da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_60"                ,	   0x11800a0041e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_61"                ,	   0x11800a0041ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_62"                ,	   0x11800a0041f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT5_63"                ,	   0x11800a0041fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1038},
+	{"PIP_STAT6_0"                 ,	   0x11800a0040030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_1"                 ,	   0x11800a00400b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_2"                 ,	   0x11800a0040130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_3"                 ,	   0x11800a00401b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_4"                 ,	   0x11800a0040230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_5"                 ,	   0x11800a00402b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_6"                 ,	   0x11800a0040330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_7"                 ,	   0x11800a00403b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_8"                 ,	   0x11800a0040430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_9"                 ,	   0x11800a00404b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_10"                ,	   0x11800a0040530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_11"                ,	   0x11800a00405b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_12"                ,	   0x11800a0040630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_13"                ,	   0x11800a00406b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_14"                ,	   0x11800a0040730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_15"                ,	   0x11800a00407b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_16"                ,	   0x11800a0040830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_17"                ,	   0x11800a00408b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_18"                ,	   0x11800a0040930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_19"                ,	   0x11800a00409b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_20"                ,	   0x11800a0040a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_21"                ,	   0x11800a0040ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_22"                ,	   0x11800a0040b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_23"                ,	   0x11800a0040bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_24"                ,	   0x11800a0040c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_25"                ,	   0x11800a0040cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_26"                ,	   0x11800a0040d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_27"                ,	   0x11800a0040db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_28"                ,	   0x11800a0040e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_29"                ,	   0x11800a0040eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_30"                ,	   0x11800a0040f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_31"                ,	   0x11800a0040fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_32"                ,	   0x11800a0041030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_33"                ,	   0x11800a00410b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_34"                ,	   0x11800a0041130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_35"                ,	   0x11800a00411b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_36"                ,	   0x11800a0041230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_37"                ,	   0x11800a00412b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_38"                ,	   0x11800a0041330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_39"                ,	   0x11800a00413b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_40"                ,	   0x11800a0041430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_41"                ,	   0x11800a00414b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_42"                ,	   0x11800a0041530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_43"                ,	   0x11800a00415b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_44"                ,	   0x11800a0041630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_45"                ,	   0x11800a00416b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_46"                ,	   0x11800a0041730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_47"                ,	   0x11800a00417b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_48"                ,	   0x11800a0041830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_49"                ,	   0x11800a00418b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_50"                ,	   0x11800a0041930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_51"                ,	   0x11800a00419b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_52"                ,	   0x11800a0041a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_53"                ,	   0x11800a0041ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_54"                ,	   0x11800a0041b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_55"                ,	   0x11800a0041bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_56"                ,	   0x11800a0041c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_57"                ,	   0x11800a0041cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_58"                ,	   0x11800a0041d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_59"                ,	   0x11800a0041db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_60"                ,	   0x11800a0041e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_61"                ,	   0x11800a0041eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_62"                ,	   0x11800a0041f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT6_63"                ,	   0x11800a0041fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1039},
+	{"PIP_STAT7_0"                 ,	   0x11800a0040038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_1"                 ,	   0x11800a00400b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_2"                 ,	   0x11800a0040138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_3"                 ,	   0x11800a00401b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_4"                 ,	   0x11800a0040238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_5"                 ,	   0x11800a00402b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_6"                 ,	   0x11800a0040338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_7"                 ,	   0x11800a00403b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_8"                 ,	   0x11800a0040438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_9"                 ,	   0x11800a00404b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_10"                ,	   0x11800a0040538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_11"                ,	   0x11800a00405b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_12"                ,	   0x11800a0040638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_13"                ,	   0x11800a00406b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_14"                ,	   0x11800a0040738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_15"                ,	   0x11800a00407b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_16"                ,	   0x11800a0040838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_17"                ,	   0x11800a00408b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_18"                ,	   0x11800a0040938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_19"                ,	   0x11800a00409b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_20"                ,	   0x11800a0040a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_21"                ,	   0x11800a0040ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_22"                ,	   0x11800a0040b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_23"                ,	   0x11800a0040bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_24"                ,	   0x11800a0040c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_25"                ,	   0x11800a0040cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_26"                ,	   0x11800a0040d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_27"                ,	   0x11800a0040db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_28"                ,	   0x11800a0040e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_29"                ,	   0x11800a0040eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_30"                ,	   0x11800a0040f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_31"                ,	   0x11800a0040fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_32"                ,	   0x11800a0041038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_33"                ,	   0x11800a00410b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_34"                ,	   0x11800a0041138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_35"                ,	   0x11800a00411b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_36"                ,	   0x11800a0041238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_37"                ,	   0x11800a00412b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_38"                ,	   0x11800a0041338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_39"                ,	   0x11800a00413b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_40"                ,	   0x11800a0041438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_41"                ,	   0x11800a00414b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_42"                ,	   0x11800a0041538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_43"                ,	   0x11800a00415b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_44"                ,	   0x11800a0041638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_45"                ,	   0x11800a00416b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_46"                ,	   0x11800a0041738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_47"                ,	   0x11800a00417b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_48"                ,	   0x11800a0041838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_49"                ,	   0x11800a00418b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_50"                ,	   0x11800a0041938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_51"                ,	   0x11800a00419b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_52"                ,	   0x11800a0041a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_53"                ,	   0x11800a0041ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_54"                ,	   0x11800a0041b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_55"                ,	   0x11800a0041bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_56"                ,	   0x11800a0041c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_57"                ,	   0x11800a0041cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_58"                ,	   0x11800a0041d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_59"                ,	   0x11800a0041db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_60"                ,	   0x11800a0041e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_61"                ,	   0x11800a0041eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_62"                ,	   0x11800a0041f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT7_63"                ,	   0x11800a0041fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1040},
+	{"PIP_STAT8_0"                 ,	   0x11800a0040040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_1"                 ,	   0x11800a00400c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_2"                 ,	   0x11800a0040140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_3"                 ,	   0x11800a00401c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_4"                 ,	   0x11800a0040240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_5"                 ,	   0x11800a00402c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_6"                 ,	   0x11800a0040340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_7"                 ,	   0x11800a00403c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_8"                 ,	   0x11800a0040440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_9"                 ,	   0x11800a00404c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_10"                ,	   0x11800a0040540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_11"                ,	   0x11800a00405c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_12"                ,	   0x11800a0040640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_13"                ,	   0x11800a00406c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_14"                ,	   0x11800a0040740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_15"                ,	   0x11800a00407c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_16"                ,	   0x11800a0040840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_17"                ,	   0x11800a00408c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_18"                ,	   0x11800a0040940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_19"                ,	   0x11800a00409c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_20"                ,	   0x11800a0040a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_21"                ,	   0x11800a0040ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_22"                ,	   0x11800a0040b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_23"                ,	   0x11800a0040bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_24"                ,	   0x11800a0040c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_25"                ,	   0x11800a0040cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_26"                ,	   0x11800a0040d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_27"                ,	   0x11800a0040dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_28"                ,	   0x11800a0040e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_29"                ,	   0x11800a0040ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_30"                ,	   0x11800a0040f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_31"                ,	   0x11800a0040fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_32"                ,	   0x11800a0041040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_33"                ,	   0x11800a00410c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_34"                ,	   0x11800a0041140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_35"                ,	   0x11800a00411c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_36"                ,	   0x11800a0041240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_37"                ,	   0x11800a00412c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_38"                ,	   0x11800a0041340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_39"                ,	   0x11800a00413c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_40"                ,	   0x11800a0041440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_41"                ,	   0x11800a00414c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_42"                ,	   0x11800a0041540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_43"                ,	   0x11800a00415c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_44"                ,	   0x11800a0041640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_45"                ,	   0x11800a00416c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_46"                ,	   0x11800a0041740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_47"                ,	   0x11800a00417c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_48"                ,	   0x11800a0041840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_49"                ,	   0x11800a00418c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_50"                ,	   0x11800a0041940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_51"                ,	   0x11800a00419c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_52"                ,	   0x11800a0041a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_53"                ,	   0x11800a0041ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_54"                ,	   0x11800a0041b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_55"                ,	   0x11800a0041bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_56"                ,	   0x11800a0041c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_57"                ,	   0x11800a0041cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_58"                ,	   0x11800a0041d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_59"                ,	   0x11800a0041dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_60"                ,	   0x11800a0041e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_61"                ,	   0x11800a0041ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_62"                ,	   0x11800a0041f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT8_63"                ,	   0x11800a0041fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1041},
+	{"PIP_STAT9_0"                 ,	   0x11800a0040048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_1"                 ,	   0x11800a00400c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_2"                 ,	   0x11800a0040148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_3"                 ,	   0x11800a00401c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_4"                 ,	   0x11800a0040248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_5"                 ,	   0x11800a00402c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_6"                 ,	   0x11800a0040348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_7"                 ,	   0x11800a00403c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_8"                 ,	   0x11800a0040448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_9"                 ,	   0x11800a00404c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_10"                ,	   0x11800a0040548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_11"                ,	   0x11800a00405c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_12"                ,	   0x11800a0040648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_13"                ,	   0x11800a00406c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_14"                ,	   0x11800a0040748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_15"                ,	   0x11800a00407c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_16"                ,	   0x11800a0040848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_17"                ,	   0x11800a00408c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_18"                ,	   0x11800a0040948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_19"                ,	   0x11800a00409c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_20"                ,	   0x11800a0040a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_21"                ,	   0x11800a0040ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_22"                ,	   0x11800a0040b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_23"                ,	   0x11800a0040bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_24"                ,	   0x11800a0040c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_25"                ,	   0x11800a0040cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_26"                ,	   0x11800a0040d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_27"                ,	   0x11800a0040dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_28"                ,	   0x11800a0040e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_29"                ,	   0x11800a0040ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_30"                ,	   0x11800a0040f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_31"                ,	   0x11800a0040fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_32"                ,	   0x11800a0041048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_33"                ,	   0x11800a00410c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_34"                ,	   0x11800a0041148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_35"                ,	   0x11800a00411c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_36"                ,	   0x11800a0041248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_37"                ,	   0x11800a00412c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_38"                ,	   0x11800a0041348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_39"                ,	   0x11800a00413c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_40"                ,	   0x11800a0041448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_41"                ,	   0x11800a00414c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_42"                ,	   0x11800a0041548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_43"                ,	   0x11800a00415c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_44"                ,	   0x11800a0041648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_45"                ,	   0x11800a00416c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_46"                ,	   0x11800a0041748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_47"                ,	   0x11800a00417c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_48"                ,	   0x11800a0041848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_49"                ,	   0x11800a00418c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_50"                ,	   0x11800a0041948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_51"                ,	   0x11800a00419c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_52"                ,	   0x11800a0041a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_53"                ,	   0x11800a0041ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_54"                ,	   0x11800a0041b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_55"                ,	   0x11800a0041bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_56"                ,	   0x11800a0041c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_57"                ,	   0x11800a0041cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_58"                ,	   0x11800a0041d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_59"                ,	   0x11800a0041dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_60"                ,	   0x11800a0041e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_61"                ,	   0x11800a0041ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_62"                ,	   0x11800a0041f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT9_63"                ,	   0x11800a0041fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1042},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1043},
+	{"PIP_STAT_INB_ERRS_PKND0"     ,	   0x11800a0020010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND1"     ,	   0x11800a0020030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND2"     ,	   0x11800a0020050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND3"     ,	   0x11800a0020070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND4"     ,	   0x11800a0020090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND5"     ,	   0x11800a00200b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND6"     ,	   0x11800a00200d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND7"     ,	   0x11800a00200f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND8"     ,	   0x11800a0020110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND9"     ,	   0x11800a0020130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND10"    ,	   0x11800a0020150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND11"    ,	   0x11800a0020170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND12"    ,	   0x11800a0020190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND13"    ,	   0x11800a00201b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND14"    ,	   0x11800a00201d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND15"    ,	   0x11800a00201f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND16"    ,	   0x11800a0020210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND17"    ,	   0x11800a0020230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND18"    ,	   0x11800a0020250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND19"    ,	   0x11800a0020270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND20"    ,	   0x11800a0020290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND21"    ,	   0x11800a00202b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND22"    ,	   0x11800a00202d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND23"    ,	   0x11800a00202f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND24"    ,	   0x11800a0020310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND25"    ,	   0x11800a0020330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND26"    ,	   0x11800a0020350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND27"    ,	   0x11800a0020370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND28"    ,	   0x11800a0020390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND29"    ,	   0x11800a00203b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND30"    ,	   0x11800a00203d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND31"    ,	   0x11800a00203f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND32"    ,	   0x11800a0020410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND33"    ,	   0x11800a0020430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND34"    ,	   0x11800a0020450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND35"    ,	   0x11800a0020470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND36"    ,	   0x11800a0020490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND37"    ,	   0x11800a00204b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND38"    ,	   0x11800a00204d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND39"    ,	   0x11800a00204f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND40"    ,	   0x11800a0020510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND41"    ,	   0x11800a0020530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND42"    ,	   0x11800a0020550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND43"    ,	   0x11800a0020570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND44"    ,	   0x11800a0020590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND45"    ,	   0x11800a00205b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND46"    ,	   0x11800a00205d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND47"    ,	   0x11800a00205f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND48"    ,	   0x11800a0020610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND49"    ,	   0x11800a0020630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND50"    ,	   0x11800a0020650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND51"    ,	   0x11800a0020670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND52"    ,	   0x11800a0020690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND53"    ,	   0x11800a00206b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND54"    ,	   0x11800a00206d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND55"    ,	   0x11800a00206f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND56"    ,	   0x11800a0020710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND57"    ,	   0x11800a0020730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND58"    ,	   0x11800a0020750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND59"    ,	   0x11800a0020770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND60"    ,	   0x11800a0020790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND61"    ,	   0x11800a00207b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND62"    ,	   0x11800a00207d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_ERRS_PKND63"    ,	   0x11800a00207f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1044},
+	{"PIP_STAT_INB_OCTS_PKND0"     ,	   0x11800a0020008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND1"     ,	   0x11800a0020028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND2"     ,	   0x11800a0020048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND3"     ,	   0x11800a0020068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND4"     ,	   0x11800a0020088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND5"     ,	   0x11800a00200a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND6"     ,	   0x11800a00200c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND7"     ,	   0x11800a00200e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND8"     ,	   0x11800a0020108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND9"     ,	   0x11800a0020128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND10"    ,	   0x11800a0020148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND11"    ,	   0x11800a0020168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND12"    ,	   0x11800a0020188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND13"    ,	   0x11800a00201a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND14"    ,	   0x11800a00201c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND15"    ,	   0x11800a00201e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND16"    ,	   0x11800a0020208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND17"    ,	   0x11800a0020228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND18"    ,	   0x11800a0020248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND19"    ,	   0x11800a0020268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND20"    ,	   0x11800a0020288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND21"    ,	   0x11800a00202a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND22"    ,	   0x11800a00202c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND23"    ,	   0x11800a00202e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND24"    ,	   0x11800a0020308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND25"    ,	   0x11800a0020328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND26"    ,	   0x11800a0020348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND27"    ,	   0x11800a0020368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND28"    ,	   0x11800a0020388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND29"    ,	   0x11800a00203a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND30"    ,	   0x11800a00203c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND31"    ,	   0x11800a00203e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND32"    ,	   0x11800a0020408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND33"    ,	   0x11800a0020428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND34"    ,	   0x11800a0020448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND35"    ,	   0x11800a0020468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND36"    ,	   0x11800a0020488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND37"    ,	   0x11800a00204a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND38"    ,	   0x11800a00204c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND39"    ,	   0x11800a00204e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND40"    ,	   0x11800a0020508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND41"    ,	   0x11800a0020528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND42"    ,	   0x11800a0020548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND43"    ,	   0x11800a0020568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND44"    ,	   0x11800a0020588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND45"    ,	   0x11800a00205a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND46"    ,	   0x11800a00205c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND47"    ,	   0x11800a00205e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND48"    ,	   0x11800a0020608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND49"    ,	   0x11800a0020628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND50"    ,	   0x11800a0020648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND51"    ,	   0x11800a0020668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND52"    ,	   0x11800a0020688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND53"    ,	   0x11800a00206a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND54"    ,	   0x11800a00206c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND55"    ,	   0x11800a00206e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND56"    ,	   0x11800a0020708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND57"    ,	   0x11800a0020728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND58"    ,	   0x11800a0020748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND59"    ,	   0x11800a0020768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND60"    ,	   0x11800a0020788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND61"    ,	   0x11800a00207a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND62"    ,	   0x11800a00207c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_OCTS_PKND63"    ,	   0x11800a00207e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1045},
+	{"PIP_STAT_INB_PKTS_PKND0"     ,	   0x11800a0020000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND1"     ,	   0x11800a0020020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND2"     ,	   0x11800a0020040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND3"     ,	   0x11800a0020060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND4"     ,	   0x11800a0020080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND5"     ,	   0x11800a00200a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND6"     ,	   0x11800a00200c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND7"     ,	   0x11800a00200e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND8"     ,	   0x11800a0020100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND9"     ,	   0x11800a0020120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND10"    ,	   0x11800a0020140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND11"    ,	   0x11800a0020160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND12"    ,	   0x11800a0020180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND13"    ,	   0x11800a00201a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND14"    ,	   0x11800a00201c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND15"    ,	   0x11800a00201e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND16"    ,	   0x11800a0020200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND17"    ,	   0x11800a0020220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND18"    ,	   0x11800a0020240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND19"    ,	   0x11800a0020260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND20"    ,	   0x11800a0020280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND21"    ,	   0x11800a00202a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND22"    ,	   0x11800a00202c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND23"    ,	   0x11800a00202e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND24"    ,	   0x11800a0020300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND25"    ,	   0x11800a0020320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND26"    ,	   0x11800a0020340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND27"    ,	   0x11800a0020360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND28"    ,	   0x11800a0020380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND29"    ,	   0x11800a00203a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND30"    ,	   0x11800a00203c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND31"    ,	   0x11800a00203e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND32"    ,	   0x11800a0020400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND33"    ,	   0x11800a0020420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND34"    ,	   0x11800a0020440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND35"    ,	   0x11800a0020460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND36"    ,	   0x11800a0020480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND37"    ,	   0x11800a00204a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND38"    ,	   0x11800a00204c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND39"    ,	   0x11800a00204e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND40"    ,	   0x11800a0020500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND41"    ,	   0x11800a0020520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND42"    ,	   0x11800a0020540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND43"    ,	   0x11800a0020560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND44"    ,	   0x11800a0020580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND45"    ,	   0x11800a00205a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND46"    ,	   0x11800a00205c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND47"    ,	   0x11800a00205e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND48"    ,	   0x11800a0020600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND49"    ,	   0x11800a0020620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND50"    ,	   0x11800a0020640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND51"    ,	   0x11800a0020660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND52"    ,	   0x11800a0020680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND53"    ,	   0x11800a00206a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND54"    ,	   0x11800a00206c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND55"    ,	   0x11800a00206e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND56"    ,	   0x11800a0020700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND57"    ,	   0x11800a0020720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND58"    ,	   0x11800a0020740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND59"    ,	   0x11800a0020760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND60"    ,	   0x11800a0020780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND61"    ,	   0x11800a00207a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND62"    ,	   0x11800a00207c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_STAT_INB_PKTS_PKND63"    ,	   0x11800a00207e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1046},
+	{"PIP_SUB_PKIND_FCS0"          ,	   0x11800a0080000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1047},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1048},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1049},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1050},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1051},
+	{"PIP_VLAN_ETYPES0"            ,	   0x11800a00001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1052},
+	{"PIP_VLAN_ETYPES1"            ,	   0x11800a00001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1052},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1053},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1054},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1055},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1056},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1057},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1058},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1059},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1060},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1061},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1062},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1063},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1064},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1065},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1066},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1067},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1068},
+	{"PKO_MEM_IPORT_PTRS"          ,	   0x1180050001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1069},
+	{"PKO_MEM_IPORT_QOS"           ,	   0x1180050001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1070},
+	{"PKO_MEM_IQUEUE_PTRS"         ,	   0x1180050001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1071},
+	{"PKO_MEM_IQUEUE_QOS"          ,	   0x1180050001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1072},
+	{"PKO_MEM_PORT_RATE0"          ,	   0x1180050001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1073},
+	{"PKO_MEM_PORT_RATE1"          ,	   0x1180050001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1074},
+	{"PKO_MEM_THROTTLE_INT"        ,	   0x1180050001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1075},
+	{"PKO_MEM_THROTTLE_PIPE"       ,	   0x1180050001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1076},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1077},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1078},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1079},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1080},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1081},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1082},
+	{"PKO_REG_DEBUG4"              ,	   0x11800500000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1083},
+	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1084},
+	{"PKO_REG_ENGINE_INFLIGHT1"    ,	   0x1180050000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1085},
+	{"PKO_REG_ENGINE_STORAGE0"     ,	   0x1180050000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1086},
+	{"PKO_REG_ENGINE_STORAGE1"     ,	   0x1180050000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1086},
+	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1087},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1088},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1089},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1090},
+	{"PKO_REG_LOOPBACK_BPID"       ,	   0x1180050000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"PKO_REG_LOOPBACK_PKIND"      ,	   0x1180050000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1092},
+	{"PKO_REG_MIN_PKT"             ,	   0x1180050000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1093},
+	{"PKO_REG_PREEMPT"             ,	   0x1180050000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1094},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1095},
+	{"PKO_REG_QUEUE_PREEMPT"       ,	   0x1180050000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1096},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1097},
+	{"PKO_REG_THROTTLE"            ,	   0x1180050000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1098},
+	{"PKO_REG_TIMESTAMP"           ,	   0x1180050000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1099},
+	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1100},
+	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1101},
+	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1102},
+	{"RAD_REG_BIST_RESULT"         ,	   0x1180070000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1103},
+	{"RAD_REG_CMD_BUF"             ,	   0x1180070000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1104},
+	{"RAD_REG_CTL"                 ,	   0x1180070000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1105},
+	{"RAD_REG_DEBUG0"              ,	   0x1180070000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1106},
+	{"RAD_REG_DEBUG1"              ,	   0x1180070000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1107},
+	{"RAD_REG_DEBUG10"             ,	   0x1180070000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1108},
+	{"RAD_REG_DEBUG11"             ,	   0x1180070000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1109},
+	{"RAD_REG_DEBUG12"             ,	   0x1180070000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1110},
+	{"RAD_REG_DEBUG2"              ,	   0x1180070000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1111},
+	{"RAD_REG_DEBUG3"              ,	   0x1180070000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1112},
+	{"RAD_REG_DEBUG4"              ,	   0x1180070000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1113},
+	{"RAD_REG_DEBUG5"              ,	   0x1180070000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1114},
+	{"RAD_REG_DEBUG6"              ,	   0x1180070000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1115},
+	{"RAD_REG_DEBUG7"              ,	   0x1180070000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1116},
+	{"RAD_REG_DEBUG8"              ,	   0x1180070000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1117},
+	{"RAD_REG_DEBUG9"              ,	   0x1180070000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1118},
+	{"RAD_REG_ERROR"               ,	   0x1180070000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1119},
+	{"RAD_REG_INT_MASK"            ,	   0x1180070000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1120},
+	{"RAD_REG_POLYNOMIAL"          ,	   0x1180070000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1121},
+	{"RAD_REG_READ_IDX"            ,	   0x1180070000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1122},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1123},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1124},
+	{"RNM_EER_DBG"                 ,	   0x1180040000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1125},
+	{"RNM_EER_KEY"                 ,	   0x1180040000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1126},
+	{"RNM_SERIAL_NUM"              ,	   0x1180040000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1127},
+	{"SLI_BIST_STATUS"             ,	   0x11f0000010580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1128},
+	{"SLI_CTL_PORT0"               ,	   0x11f0000010050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1129},
+	{"SLI_CTL_PORT1"               ,	   0x11f0000010060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1129},
+	{"SLI_CTL_STATUS"              ,	   0x11f0000010570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1130},
+	{"SLI_DATA_OUT_CNT"            ,	   0x11f00000105f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1131},
+	{"SLI_DBG_DATA"                ,	   0x11f0000010310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1132},
+	{"SLI_DBG_SELECT"              ,	   0x11f0000010300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1133},
+	{"SLI_DMA0_CNT"                ,	   0x11f0000010400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1134},
+	{"SLI_DMA1_CNT"                ,	   0x11f0000010410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1134},
+	{"SLI_DMA0_INT_LEVEL"          ,	   0x11f00000103e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1135},
+	{"SLI_DMA1_INT_LEVEL"          ,	   0x11f00000103f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1135},
+	{"SLI_DMA0_TIM"                ,	   0x11f0000010420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1136},
+	{"SLI_DMA1_TIM"                ,	   0x11f0000010430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1136},
+	{"SLI_INT_ENB_CIU"             ,	   0x11f0000013cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1137},
+	{"SLI_INT_ENB_PORT0"           ,	   0x11f0000010340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1138},
+	{"SLI_INT_ENB_PORT1"           ,	   0x11f0000010350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1138},
+	{"SLI_INT_SUM"                 ,	   0x11f0000010330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1139},
+	{"SLI_LAST_WIN_RDATA0"         ,	   0x11f0000010600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1140},
+	{"SLI_LAST_WIN_RDATA1"         ,	   0x11f0000010610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1141},
+	{"SLI_MAC_CREDIT_CNT"          ,	   0x11f0000013d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1142},
+	{"SLI_MAC_NUMBER"              ,	            0x3e00ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1143},
+	{"SLI_MEM_ACCESS_CTL"          ,	   0x11f00000102f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1144},
+	{"SLI_MEM_ACCESS_SUBID12"      ,	   0x11f00000100e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1145},
+	{"SLI_MEM_ACCESS_SUBID13"      ,	   0x11f00000100f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1145},
+	{"SLI_MEM_ACCESS_SUBID14"      ,	   0x11f0000010100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1145},
+	{"SLI_MEM_ACCESS_SUBID15"      ,	   0x11f0000010110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1145},
+	{"SLI_MEM_ACCESS_SUBID16"      ,	   0x11f0000010120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1145},
+	{"SLI_MEM_ACCESS_SUBID17"      ,	   0x11f0000010130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1145},
+	{"SLI_MEM_ACCESS_SUBID18"      ,	   0x11f0000010140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1145},
+	{"SLI_MEM_ACCESS_SUBID19"      ,	   0x11f0000010150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1145},
+	{"SLI_MEM_ACCESS_SUBID20"      ,	   0x11f0000010160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1145},
+	{"SLI_MEM_ACCESS_SUBID21"      ,	   0x11f0000010170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1145},
+	{"SLI_MEM_ACCESS_SUBID22"      ,	   0x11f0000010180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1145},
+	{"SLI_MEM_ACCESS_SUBID23"      ,	   0x11f0000010190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1145},
+	{"SLI_MEM_ACCESS_SUBID24"      ,	   0x11f00000101a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1145},
+	{"SLI_MEM_ACCESS_SUBID25"      ,	   0x11f00000101b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1145},
+	{"SLI_MEM_ACCESS_SUBID26"      ,	   0x11f00000101c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1145},
+	{"SLI_MEM_ACCESS_SUBID27"      ,	   0x11f00000101d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1145},
+	{"SLI_MSI_ENB0"                ,	   0x11f0000013c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1146},
+	{"SLI_MSI_ENB1"                ,	   0x11f0000013c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1147},
+	{"SLI_MSI_ENB2"                ,	   0x11f0000013c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1148},
+	{"SLI_MSI_ENB3"                ,	   0x11f0000013c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1149},
+	{"SLI_MSI_RCV0"                ,	   0x11f0000013c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1150},
+	{"SLI_MSI_RCV1"                ,	   0x11f0000013c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1151},
+	{"SLI_MSI_RCV2"                ,	   0x11f0000013c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1152},
+	{"SLI_MSI_RCV3"                ,	   0x11f0000013c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1153},
+	{"SLI_MSI_RD_MAP"              ,	   0x11f0000013ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1154},
+	{"SLI_MSI_W1C_ENB0"            ,	   0x11f0000013cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1155},
+	{"SLI_MSI_W1C_ENB1"            ,	   0x11f0000013d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1156},
+	{"SLI_MSI_W1C_ENB2"            ,	   0x11f0000013d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1157},
+	{"SLI_MSI_W1C_ENB3"            ,	   0x11f0000013d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1158},
+	{"SLI_MSI_W1S_ENB0"            ,	   0x11f0000013d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1159},
+	{"SLI_MSI_W1S_ENB1"            ,	   0x11f0000013d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1160},
+	{"SLI_MSI_W1S_ENB2"            ,	   0x11f0000013d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1161},
+	{"SLI_MSI_W1S_ENB3"            ,	   0x11f0000013d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1162},
+	{"SLI_MSI_WR_MAP"              ,	   0x11f0000013c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1163},
+	{"SLI_PCIE_MSI_RCV"            ,	   0x11f0000013cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1164},
+	{"SLI_PCIE_MSI_RCV_B1"         ,	   0x11f0000010650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1165},
+	{"SLI_PCIE_MSI_RCV_B2"         ,	   0x11f0000010660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1166},
+	{"SLI_PCIE_MSI_RCV_B3"         ,	   0x11f0000010670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1167},
+	{"SLI_PKT0_CNTS"               ,	   0x11f0000012400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT1_CNTS"               ,	   0x11f0000012410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT2_CNTS"               ,	   0x11f0000012420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT3_CNTS"               ,	   0x11f0000012430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT4_CNTS"               ,	   0x11f0000012440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT5_CNTS"               ,	   0x11f0000012450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT6_CNTS"               ,	   0x11f0000012460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT7_CNTS"               ,	   0x11f0000012470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT8_CNTS"               ,	   0x11f0000012480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT9_CNTS"               ,	   0x11f0000012490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT10_CNTS"              ,	   0x11f00000124a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT11_CNTS"              ,	   0x11f00000124b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT12_CNTS"              ,	   0x11f00000124c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT13_CNTS"              ,	   0x11f00000124d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT14_CNTS"              ,	   0x11f00000124e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT15_CNTS"              ,	   0x11f00000124f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT16_CNTS"              ,	   0x11f0000012500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT17_CNTS"              ,	   0x11f0000012510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT18_CNTS"              ,	   0x11f0000012520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT19_CNTS"              ,	   0x11f0000012530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT20_CNTS"              ,	   0x11f0000012540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT21_CNTS"              ,	   0x11f0000012550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT22_CNTS"              ,	   0x11f0000012560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT23_CNTS"              ,	   0x11f0000012570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT24_CNTS"              ,	   0x11f0000012580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT25_CNTS"              ,	   0x11f0000012590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT26_CNTS"              ,	   0x11f00000125a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT27_CNTS"              ,	   0x11f00000125b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT28_CNTS"              ,	   0x11f00000125c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT29_CNTS"              ,	   0x11f00000125d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT30_CNTS"              ,	   0x11f00000125e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT31_CNTS"              ,	   0x11f00000125f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1168},
+	{"SLI_PKT0_INSTR_BADDR"        ,	   0x11f0000012800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT1_INSTR_BADDR"        ,	   0x11f0000012810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT2_INSTR_BADDR"        ,	   0x11f0000012820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT3_INSTR_BADDR"        ,	   0x11f0000012830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT4_INSTR_BADDR"        ,	   0x11f0000012840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT5_INSTR_BADDR"        ,	   0x11f0000012850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT6_INSTR_BADDR"        ,	   0x11f0000012860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT7_INSTR_BADDR"        ,	   0x11f0000012870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT8_INSTR_BADDR"        ,	   0x11f0000012880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT9_INSTR_BADDR"        ,	   0x11f0000012890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT10_INSTR_BADDR"       ,	   0x11f00000128a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT11_INSTR_BADDR"       ,	   0x11f00000128b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT12_INSTR_BADDR"       ,	   0x11f00000128c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT13_INSTR_BADDR"       ,	   0x11f00000128d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT14_INSTR_BADDR"       ,	   0x11f00000128e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT15_INSTR_BADDR"       ,	   0x11f00000128f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT16_INSTR_BADDR"       ,	   0x11f0000012900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT17_INSTR_BADDR"       ,	   0x11f0000012910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT18_INSTR_BADDR"       ,	   0x11f0000012920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT19_INSTR_BADDR"       ,	   0x11f0000012930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT20_INSTR_BADDR"       ,	   0x11f0000012940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT21_INSTR_BADDR"       ,	   0x11f0000012950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT22_INSTR_BADDR"       ,	   0x11f0000012960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT23_INSTR_BADDR"       ,	   0x11f0000012970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT24_INSTR_BADDR"       ,	   0x11f0000012980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT25_INSTR_BADDR"       ,	   0x11f0000012990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT26_INSTR_BADDR"       ,	   0x11f00000129a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT27_INSTR_BADDR"       ,	   0x11f00000129b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT28_INSTR_BADDR"       ,	   0x11f00000129c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT29_INSTR_BADDR"       ,	   0x11f00000129d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT30_INSTR_BADDR"       ,	   0x11f00000129e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT31_INSTR_BADDR"       ,	   0x11f00000129f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1169},
+	{"SLI_PKT0_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT1_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT2_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT3_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT4_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT5_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT6_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT7_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT8_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT9_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT10_INSTR_BAOFF_DBELL" ,	   0x11f0000012ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT11_INSTR_BAOFF_DBELL" ,	   0x11f0000012cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT12_INSTR_BAOFF_DBELL" ,	   0x11f0000012cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT13_INSTR_BAOFF_DBELL" ,	   0x11f0000012cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT14_INSTR_BAOFF_DBELL" ,	   0x11f0000012ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT15_INSTR_BAOFF_DBELL" ,	   0x11f0000012cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT16_INSTR_BAOFF_DBELL" ,	   0x11f0000012d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT17_INSTR_BAOFF_DBELL" ,	   0x11f0000012d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT18_INSTR_BAOFF_DBELL" ,	   0x11f0000012d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT19_INSTR_BAOFF_DBELL" ,	   0x11f0000012d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT20_INSTR_BAOFF_DBELL" ,	   0x11f0000012d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT21_INSTR_BAOFF_DBELL" ,	   0x11f0000012d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT22_INSTR_BAOFF_DBELL" ,	   0x11f0000012d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT23_INSTR_BAOFF_DBELL" ,	   0x11f0000012d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT24_INSTR_BAOFF_DBELL" ,	   0x11f0000012d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT25_INSTR_BAOFF_DBELL" ,	   0x11f0000012d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT26_INSTR_BAOFF_DBELL" ,	   0x11f0000012da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT27_INSTR_BAOFF_DBELL" ,	   0x11f0000012db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT28_INSTR_BAOFF_DBELL" ,	   0x11f0000012dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT29_INSTR_BAOFF_DBELL" ,	   0x11f0000012dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT30_INSTR_BAOFF_DBELL" ,	   0x11f0000012de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT31_INSTR_BAOFF_DBELL" ,	   0x11f0000012df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1170},
+	{"SLI_PKT0_INSTR_FIFO_RSIZE"   ,	   0x11f0000013000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT1_INSTR_FIFO_RSIZE"   ,	   0x11f0000013010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT2_INSTR_FIFO_RSIZE"   ,	   0x11f0000013020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT3_INSTR_FIFO_RSIZE"   ,	   0x11f0000013030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT4_INSTR_FIFO_RSIZE"   ,	   0x11f0000013040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT5_INSTR_FIFO_RSIZE"   ,	   0x11f0000013050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT6_INSTR_FIFO_RSIZE"   ,	   0x11f0000013060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT7_INSTR_FIFO_RSIZE"   ,	   0x11f0000013070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT8_INSTR_FIFO_RSIZE"   ,	   0x11f0000013080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT9_INSTR_FIFO_RSIZE"   ,	   0x11f0000013090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT10_INSTR_FIFO_RSIZE"  ,	   0x11f00000130a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT11_INSTR_FIFO_RSIZE"  ,	   0x11f00000130b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT12_INSTR_FIFO_RSIZE"  ,	   0x11f00000130c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT13_INSTR_FIFO_RSIZE"  ,	   0x11f00000130d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT14_INSTR_FIFO_RSIZE"  ,	   0x11f00000130e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT15_INSTR_FIFO_RSIZE"  ,	   0x11f00000130f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT16_INSTR_FIFO_RSIZE"  ,	   0x11f0000013100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT17_INSTR_FIFO_RSIZE"  ,	   0x11f0000013110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT18_INSTR_FIFO_RSIZE"  ,	   0x11f0000013120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT19_INSTR_FIFO_RSIZE"  ,	   0x11f0000013130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT20_INSTR_FIFO_RSIZE"  ,	   0x11f0000013140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT21_INSTR_FIFO_RSIZE"  ,	   0x11f0000013150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT22_INSTR_FIFO_RSIZE"  ,	   0x11f0000013160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT23_INSTR_FIFO_RSIZE"  ,	   0x11f0000013170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT24_INSTR_FIFO_RSIZE"  ,	   0x11f0000013180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT25_INSTR_FIFO_RSIZE"  ,	   0x11f0000013190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT26_INSTR_FIFO_RSIZE"  ,	   0x11f00000131a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT27_INSTR_FIFO_RSIZE"  ,	   0x11f00000131b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT28_INSTR_FIFO_RSIZE"  ,	   0x11f00000131c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT29_INSTR_FIFO_RSIZE"  ,	   0x11f00000131d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT30_INSTR_FIFO_RSIZE"  ,	   0x11f00000131e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT31_INSTR_FIFO_RSIZE"  ,	   0x11f00000131f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1171},
+	{"SLI_PKT0_INSTR_HEADER"       ,	   0x11f0000013400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT1_INSTR_HEADER"       ,	   0x11f0000013410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT2_INSTR_HEADER"       ,	   0x11f0000013420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT3_INSTR_HEADER"       ,	   0x11f0000013430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT4_INSTR_HEADER"       ,	   0x11f0000013440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT5_INSTR_HEADER"       ,	   0x11f0000013450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT6_INSTR_HEADER"       ,	   0x11f0000013460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT7_INSTR_HEADER"       ,	   0x11f0000013470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT8_INSTR_HEADER"       ,	   0x11f0000013480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT9_INSTR_HEADER"       ,	   0x11f0000013490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT10_INSTR_HEADER"      ,	   0x11f00000134a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT11_INSTR_HEADER"      ,	   0x11f00000134b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT12_INSTR_HEADER"      ,	   0x11f00000134c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT13_INSTR_HEADER"      ,	   0x11f00000134d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT14_INSTR_HEADER"      ,	   0x11f00000134e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT15_INSTR_HEADER"      ,	   0x11f00000134f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT16_INSTR_HEADER"      ,	   0x11f0000013500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT17_INSTR_HEADER"      ,	   0x11f0000013510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT18_INSTR_HEADER"      ,	   0x11f0000013520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT19_INSTR_HEADER"      ,	   0x11f0000013530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT20_INSTR_HEADER"      ,	   0x11f0000013540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT21_INSTR_HEADER"      ,	   0x11f0000013550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT22_INSTR_HEADER"      ,	   0x11f0000013560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT23_INSTR_HEADER"      ,	   0x11f0000013570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT24_INSTR_HEADER"      ,	   0x11f0000013580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT25_INSTR_HEADER"      ,	   0x11f0000013590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT26_INSTR_HEADER"      ,	   0x11f00000135a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT27_INSTR_HEADER"      ,	   0x11f00000135b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT28_INSTR_HEADER"      ,	   0x11f00000135c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT29_INSTR_HEADER"      ,	   0x11f00000135d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT30_INSTR_HEADER"      ,	   0x11f00000135e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT31_INSTR_HEADER"      ,	   0x11f00000135f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1172},
+	{"SLI_PKT0_OUT_SIZE"           ,	   0x11f0000010c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT1_OUT_SIZE"           ,	   0x11f0000010c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT2_OUT_SIZE"           ,	   0x11f0000010c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT3_OUT_SIZE"           ,	   0x11f0000010c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT4_OUT_SIZE"           ,	   0x11f0000010c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT5_OUT_SIZE"           ,	   0x11f0000010c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT6_OUT_SIZE"           ,	   0x11f0000010c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT7_OUT_SIZE"           ,	   0x11f0000010c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT8_OUT_SIZE"           ,	   0x11f0000010c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT9_OUT_SIZE"           ,	   0x11f0000010c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT10_OUT_SIZE"          ,	   0x11f0000010ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT11_OUT_SIZE"          ,	   0x11f0000010cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT12_OUT_SIZE"          ,	   0x11f0000010cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT13_OUT_SIZE"          ,	   0x11f0000010cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT14_OUT_SIZE"          ,	   0x11f0000010ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT15_OUT_SIZE"          ,	   0x11f0000010cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT16_OUT_SIZE"          ,	   0x11f0000010d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT17_OUT_SIZE"          ,	   0x11f0000010d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT18_OUT_SIZE"          ,	   0x11f0000010d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT19_OUT_SIZE"          ,	   0x11f0000010d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT20_OUT_SIZE"          ,	   0x11f0000010d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT21_OUT_SIZE"          ,	   0x11f0000010d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT22_OUT_SIZE"          ,	   0x11f0000010d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT23_OUT_SIZE"          ,	   0x11f0000010d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT24_OUT_SIZE"          ,	   0x11f0000010d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT25_OUT_SIZE"          ,	   0x11f0000010d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT26_OUT_SIZE"          ,	   0x11f0000010da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT27_OUT_SIZE"          ,	   0x11f0000010db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT28_OUT_SIZE"          ,	   0x11f0000010dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT29_OUT_SIZE"          ,	   0x11f0000010dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT30_OUT_SIZE"          ,	   0x11f0000010de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT31_OUT_SIZE"          ,	   0x11f0000010df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1173},
+	{"SLI_PKT0_SLIST_BADDR"        ,	   0x11f0000011400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT1_SLIST_BADDR"        ,	   0x11f0000011410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT2_SLIST_BADDR"        ,	   0x11f0000011420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT3_SLIST_BADDR"        ,	   0x11f0000011430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT4_SLIST_BADDR"        ,	   0x11f0000011440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT5_SLIST_BADDR"        ,	   0x11f0000011450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT6_SLIST_BADDR"        ,	   0x11f0000011460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT7_SLIST_BADDR"        ,	   0x11f0000011470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT8_SLIST_BADDR"        ,	   0x11f0000011480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT9_SLIST_BADDR"        ,	   0x11f0000011490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT10_SLIST_BADDR"       ,	   0x11f00000114a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT11_SLIST_BADDR"       ,	   0x11f00000114b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT12_SLIST_BADDR"       ,	   0x11f00000114c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT13_SLIST_BADDR"       ,	   0x11f00000114d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT14_SLIST_BADDR"       ,	   0x11f00000114e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT15_SLIST_BADDR"       ,	   0x11f00000114f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT16_SLIST_BADDR"       ,	   0x11f0000011500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT17_SLIST_BADDR"       ,	   0x11f0000011510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT18_SLIST_BADDR"       ,	   0x11f0000011520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT19_SLIST_BADDR"       ,	   0x11f0000011530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT20_SLIST_BADDR"       ,	   0x11f0000011540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT21_SLIST_BADDR"       ,	   0x11f0000011550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT22_SLIST_BADDR"       ,	   0x11f0000011560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT23_SLIST_BADDR"       ,	   0x11f0000011570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT24_SLIST_BADDR"       ,	   0x11f0000011580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT25_SLIST_BADDR"       ,	   0x11f0000011590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT26_SLIST_BADDR"       ,	   0x11f00000115a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT27_SLIST_BADDR"       ,	   0x11f00000115b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT28_SLIST_BADDR"       ,	   0x11f00000115c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT29_SLIST_BADDR"       ,	   0x11f00000115d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT30_SLIST_BADDR"       ,	   0x11f00000115e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT31_SLIST_BADDR"       ,	   0x11f00000115f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1174},
+	{"SLI_PKT0_SLIST_BAOFF_DBELL"  ,	   0x11f0000011800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT1_SLIST_BAOFF_DBELL"  ,	   0x11f0000011810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT2_SLIST_BAOFF_DBELL"  ,	   0x11f0000011820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT3_SLIST_BAOFF_DBELL"  ,	   0x11f0000011830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT4_SLIST_BAOFF_DBELL"  ,	   0x11f0000011840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT5_SLIST_BAOFF_DBELL"  ,	   0x11f0000011850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT6_SLIST_BAOFF_DBELL"  ,	   0x11f0000011860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT7_SLIST_BAOFF_DBELL"  ,	   0x11f0000011870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT8_SLIST_BAOFF_DBELL"  ,	   0x11f0000011880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT9_SLIST_BAOFF_DBELL"  ,	   0x11f0000011890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT10_SLIST_BAOFF_DBELL" ,	   0x11f00000118a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT11_SLIST_BAOFF_DBELL" ,	   0x11f00000118b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT12_SLIST_BAOFF_DBELL" ,	   0x11f00000118c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT13_SLIST_BAOFF_DBELL" ,	   0x11f00000118d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT14_SLIST_BAOFF_DBELL" ,	   0x11f00000118e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT15_SLIST_BAOFF_DBELL" ,	   0x11f00000118f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT16_SLIST_BAOFF_DBELL" ,	   0x11f0000011900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT17_SLIST_BAOFF_DBELL" ,	   0x11f0000011910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT18_SLIST_BAOFF_DBELL" ,	   0x11f0000011920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT19_SLIST_BAOFF_DBELL" ,	   0x11f0000011930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT20_SLIST_BAOFF_DBELL" ,	   0x11f0000011940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT21_SLIST_BAOFF_DBELL" ,	   0x11f0000011950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT22_SLIST_BAOFF_DBELL" ,	   0x11f0000011960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT23_SLIST_BAOFF_DBELL" ,	   0x11f0000011970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT24_SLIST_BAOFF_DBELL" ,	   0x11f0000011980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT25_SLIST_BAOFF_DBELL" ,	   0x11f0000011990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT26_SLIST_BAOFF_DBELL" ,	   0x11f00000119a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT27_SLIST_BAOFF_DBELL" ,	   0x11f00000119b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT28_SLIST_BAOFF_DBELL" ,	   0x11f00000119c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT29_SLIST_BAOFF_DBELL" ,	   0x11f00000119d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT30_SLIST_BAOFF_DBELL" ,	   0x11f00000119e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT31_SLIST_BAOFF_DBELL" ,	   0x11f00000119f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1175},
+	{"SLI_PKT0_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT1_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT2_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT3_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT4_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT5_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT6_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT7_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT8_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT9_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT10_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT11_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT12_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT13_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT14_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT15_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT16_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT17_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT18_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT19_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT20_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT21_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT22_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT23_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT24_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT25_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT26_SLIST_FIFO_RSIZE"  ,	   0x11f0000011da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT27_SLIST_FIFO_RSIZE"  ,	   0x11f0000011db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT28_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT29_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT30_SLIST_FIFO_RSIZE"  ,	   0x11f0000011de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT31_SLIST_FIFO_RSIZE"  ,	   0x11f0000011df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1176},
+	{"SLI_PKT_CNT_INT"             ,	   0x11f0000011130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1177},
+	{"SLI_PKT_CNT_INT_ENB"         ,	   0x11f0000011150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1178},
+	{"SLI_PKT_CTL"                 ,	   0x11f0000011220ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1179},
+	{"SLI_PKT_DATA_OUT_ES"         ,	   0x11f00000110b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1180},
+	{"SLI_PKT_DATA_OUT_NS"         ,	   0x11f00000110a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1181},
+	{"SLI_PKT_DATA_OUT_ROR"        ,	   0x11f0000011090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1182},
+	{"SLI_PKT_DPADDR"              ,	   0x11f0000011080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1183},
+	{"SLI_PKT_IN_DONE0_CNTS"       ,	   0x11f0000012000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE1_CNTS"       ,	   0x11f0000012010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE2_CNTS"       ,	   0x11f0000012020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE3_CNTS"       ,	   0x11f0000012030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE4_CNTS"       ,	   0x11f0000012040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE5_CNTS"       ,	   0x11f0000012050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE6_CNTS"       ,	   0x11f0000012060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE7_CNTS"       ,	   0x11f0000012070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE8_CNTS"       ,	   0x11f0000012080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE9_CNTS"       ,	   0x11f0000012090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE10_CNTS"      ,	   0x11f00000120a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE11_CNTS"      ,	   0x11f00000120b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE12_CNTS"      ,	   0x11f00000120c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE13_CNTS"      ,	   0x11f00000120d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE14_CNTS"      ,	   0x11f00000120e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE15_CNTS"      ,	   0x11f00000120f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE16_CNTS"      ,	   0x11f0000012100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE17_CNTS"      ,	   0x11f0000012110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE18_CNTS"      ,	   0x11f0000012120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE19_CNTS"      ,	   0x11f0000012130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE20_CNTS"      ,	   0x11f0000012140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE21_CNTS"      ,	   0x11f0000012150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE22_CNTS"      ,	   0x11f0000012160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE23_CNTS"      ,	   0x11f0000012170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE24_CNTS"      ,	   0x11f0000012180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE25_CNTS"      ,	   0x11f0000012190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE26_CNTS"      ,	   0x11f00000121a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE27_CNTS"      ,	   0x11f00000121b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE28_CNTS"      ,	   0x11f00000121c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE29_CNTS"      ,	   0x11f00000121d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE30_CNTS"      ,	   0x11f00000121e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_DONE31_CNTS"      ,	   0x11f00000121f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1184},
+	{"SLI_PKT_IN_INSTR_COUNTS"     ,	   0x11f0000011200ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1185},
+	{"SLI_PKT_IN_PCIE_PORT"        ,	   0x11f00000111b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1186},
+	{"SLI_PKT_INPUT_CONTROL"       ,	   0x11f0000011170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1187},
+	{"SLI_PKT_INSTR_ENB"           ,	   0x11f0000011000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1188},
+	{"SLI_PKT_INSTR_RD_SIZE"       ,	   0x11f00000111a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1189},
+	{"SLI_PKT_INSTR_SIZE"          ,	   0x11f0000011020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1190},
+	{"SLI_PKT_INT_LEVELS"          ,	   0x11f0000011120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1191},
+	{"SLI_PKT_IPTR"                ,	   0x11f0000011070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1192},
+	{"SLI_PKT_OUT_BMODE"           ,	   0x11f00000110d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1193},
+	{"SLI_PKT_OUT_BP_EN"           ,	   0x11f0000011240ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1194},
+	{"SLI_PKT_OUT_ENB"             ,	   0x11f0000011010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1195},
+	{"SLI_PKT_OUTPUT_WMARK"        ,	   0x11f0000011180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1196},
+	{"SLI_PKT_PCIE_PORT"           ,	   0x11f00000110e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1197},
+	{"SLI_PKT_PORT_IN_RST"         ,	   0x11f00000111f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1198},
+	{"SLI_PKT_SLIST_ES"            ,	   0x11f0000011050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1199},
+	{"SLI_PKT_SLIST_NS"            ,	   0x11f0000011040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1200},
+	{"SLI_PKT_SLIST_ROR"           ,	   0x11f0000011030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1201},
+	{"SLI_PKT_TIME_INT"            ,	   0x11f0000011140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1202},
+	{"SLI_PKT_TIME_INT_ENB"        ,	   0x11f0000011160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1203},
+	{"SLI_PORT0_PKIND"             ,	   0x11f0000010800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT1_PKIND"             ,	   0x11f0000010810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT2_PKIND"             ,	   0x11f0000010820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT3_PKIND"             ,	   0x11f0000010830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT4_PKIND"             ,	   0x11f0000010840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT5_PKIND"             ,	   0x11f0000010850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT6_PKIND"             ,	   0x11f0000010860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT7_PKIND"             ,	   0x11f0000010870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT8_PKIND"             ,	   0x11f0000010880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT9_PKIND"             ,	   0x11f0000010890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT10_PKIND"            ,	   0x11f00000108a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT11_PKIND"            ,	   0x11f00000108b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT12_PKIND"            ,	   0x11f00000108c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT13_PKIND"            ,	   0x11f00000108d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT14_PKIND"            ,	   0x11f00000108e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT15_PKIND"            ,	   0x11f00000108f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT16_PKIND"            ,	   0x11f0000010900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT17_PKIND"            ,	   0x11f0000010910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT18_PKIND"            ,	   0x11f0000010920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT19_PKIND"            ,	   0x11f0000010930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT20_PKIND"            ,	   0x11f0000010940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT21_PKIND"            ,	   0x11f0000010950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT22_PKIND"            ,	   0x11f0000010960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT23_PKIND"            ,	   0x11f0000010970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT24_PKIND"            ,	   0x11f0000010980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT25_PKIND"            ,	   0x11f0000010990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT26_PKIND"            ,	   0x11f00000109a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT27_PKIND"            ,	   0x11f00000109b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT28_PKIND"            ,	   0x11f00000109c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT29_PKIND"            ,	   0x11f00000109d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT30_PKIND"            ,	   0x11f00000109e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_PORT31_PKIND"            ,	   0x11f00000109f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1204},
+	{"SLI_S2M_PORT0_CTL"           ,	   0x11f0000013d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1205},
+	{"SLI_S2M_PORT1_CTL"           ,	   0x11f0000013d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1205},
+	{"SLI_SCRATCH_1"               ,	   0x11f00000103c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1206},
+	{"SLI_SCRATCH_2"               ,	   0x11f00000103d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1207},
+	{"SLI_STATE1"                  ,	   0x11f0000010620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1208},
+	{"SLI_STATE2"                  ,	   0x11f0000010630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1209},
+	{"SLI_STATE3"                  ,	   0x11f0000010640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1210},
+	{"SLI_TX_PIPE"                 ,	   0x11f0000011230ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1211},
+	{"SLI_WIN_RD_ADDR"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1212},
+	{"SLI_WIN_RD_DATA"             ,	              0x40ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1213},
+	{"SLI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1214},
+	{"SLI_WIN_WR_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1215},
+	{"SLI_WIN_WR_MASK"             ,	              0x30ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1216},
+	{"SLI_WINDOW_CTL"              ,	   0x11f00000102e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1217},
+	{"SMI0_CLK"                    ,	   0x1180000003818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1218},
+	{"SMI1_CLK"                    ,	   0x1180000003898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1218},
+	{"SMI2_CLK"                    ,	   0x1180000003918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1218},
+	{"SMI3_CLK"                    ,	   0x1180000003998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1218},
+	{"SMI0_CMD"                    ,	   0x1180000003800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1219},
+	{"SMI1_CMD"                    ,	   0x1180000003880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1219},
+	{"SMI2_CMD"                    ,	   0x1180000003900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1219},
+	{"SMI3_CMD"                    ,	   0x1180000003980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1219},
+	{"SMI0_EN"                     ,	   0x1180000003820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1220},
+	{"SMI1_EN"                     ,	   0x11800000038a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1220},
+	{"SMI2_EN"                     ,	   0x1180000003920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1220},
+	{"SMI3_EN"                     ,	   0x11800000039a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1220},
+	{"SMI0_RD_DAT"                 ,	   0x1180000003810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1221},
+	{"SMI1_RD_DAT"                 ,	   0x1180000003890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1221},
+	{"SMI2_RD_DAT"                 ,	   0x1180000003910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1221},
+	{"SMI3_RD_DAT"                 ,	   0x1180000003990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1221},
+	{"SMI0_WR_DAT"                 ,	   0x1180000003808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1222},
+	{"SMI1_WR_DAT"                 ,	   0x1180000003888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1222},
+	{"SMI2_WR_DAT"                 ,	   0x1180000003908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1222},
+	{"SMI3_WR_DAT"                 ,	   0x1180000003988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1222},
+	{"SMI_DRV_CTL"                 ,	   0x1180000001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1223},
+	{"SSO_ACTIVE_CYCLES"           ,	   0x16700000010e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1224},
+	{"SSO_BIST_STAT"               ,	   0x1670000001078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1225},
+	{"SSO_CFG"                     ,	   0x1670000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1226},
+	{"SSO_DS_PC"                   ,	   0x1670000001070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1227},
+	{"SSO_ERR"                     ,	   0x1670000001038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1228},
+	{"SSO_ERR_ENB"                 ,	   0x1670000001030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1229},
+	{"SSO_FIDX_ECC_CTL"            ,	   0x16700000010d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1230},
+	{"SSO_FIDX_ECC_ST"             ,	   0x16700000010d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1231},
+	{"SSO_FPAGE_CNT"               ,	   0x1670000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1232},
+	{"SSO_GWE_CFG"                 ,	   0x1670000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1233},
+	{"SSO_IDX_ECC_CTL"             ,	   0x16700000010c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1234},
+	{"SSO_IDX_ECC_ST"              ,	   0x16700000010c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1235},
+	{"SSO_IQ_CNT0"                 ,	   0x1670000009000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1236},
+	{"SSO_IQ_CNT1"                 ,	   0x1670000009008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1236},
+	{"SSO_IQ_CNT2"                 ,	   0x1670000009010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1236},
+	{"SSO_IQ_CNT3"                 ,	   0x1670000009018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1236},
+	{"SSO_IQ_CNT4"                 ,	   0x1670000009020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1236},
+	{"SSO_IQ_CNT5"                 ,	   0x1670000009028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1236},
+	{"SSO_IQ_CNT6"                 ,	   0x1670000009030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1236},
+	{"SSO_IQ_CNT7"                 ,	   0x1670000009038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1236},
+	{"SSO_IQ_COM_CNT"              ,	   0x1670000001058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1237},
+	{"SSO_IQ_INT"                  ,	   0x1670000001048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1238},
+	{"SSO_IQ_INT_EN"               ,	   0x1670000001050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1239},
+	{"SSO_IQ_THR0"                 ,	   0x167000000a000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1240},
+	{"SSO_IQ_THR1"                 ,	   0x167000000a008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1240},
+	{"SSO_IQ_THR2"                 ,	   0x167000000a010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1240},
+	{"SSO_IQ_THR3"                 ,	   0x167000000a018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1240},
+	{"SSO_IQ_THR4"                 ,	   0x167000000a020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1240},
+	{"SSO_IQ_THR5"                 ,	   0x167000000a028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1240},
+	{"SSO_IQ_THR6"                 ,	   0x167000000a030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1240},
+	{"SSO_IQ_THR7"                 ,	   0x167000000a038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1240},
+	{"SSO_NOS_CNT"                 ,	   0x1670000001040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1241},
+	{"SSO_NW_TIM"                  ,	   0x1670000001028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1242},
+	{"SSO_OTH_ECC_CTL"             ,	   0x16700000010b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1243},
+	{"SSO_OTH_ECC_ST"              ,	   0x16700000010b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1244},
+	{"SSO_PND_ECC_CTL"             ,	   0x16700000010a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1245},
+	{"SSO_PND_ECC_ST"              ,	   0x16700000010a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1246},
+	{"SSO_PP0_GRP_MSK"             ,	   0x1670000006000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP1_GRP_MSK"             ,	   0x1670000006008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP2_GRP_MSK"             ,	   0x1670000006010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP3_GRP_MSK"             ,	   0x1670000006018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP4_GRP_MSK"             ,	   0x1670000006020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP5_GRP_MSK"             ,	   0x1670000006028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP6_GRP_MSK"             ,	   0x1670000006030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP7_GRP_MSK"             ,	   0x1670000006038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP8_GRP_MSK"             ,	   0x1670000006040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP9_GRP_MSK"             ,	   0x1670000006048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP10_GRP_MSK"            ,	   0x1670000006050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP11_GRP_MSK"            ,	   0x1670000006058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP12_GRP_MSK"            ,	   0x1670000006060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP13_GRP_MSK"            ,	   0x1670000006068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP14_GRP_MSK"            ,	   0x1670000006070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP15_GRP_MSK"            ,	   0x1670000006078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP16_GRP_MSK"            ,	   0x1670000006080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP17_GRP_MSK"            ,	   0x1670000006088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP18_GRP_MSK"            ,	   0x1670000006090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP19_GRP_MSK"            ,	   0x1670000006098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP20_GRP_MSK"            ,	   0x16700000060a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP21_GRP_MSK"            ,	   0x16700000060a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP22_GRP_MSK"            ,	   0x16700000060b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP23_GRP_MSK"            ,	   0x16700000060b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP24_GRP_MSK"            ,	   0x16700000060c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP25_GRP_MSK"            ,	   0x16700000060c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP26_GRP_MSK"            ,	   0x16700000060d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP27_GRP_MSK"            ,	   0x16700000060d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP28_GRP_MSK"            ,	   0x16700000060e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP29_GRP_MSK"            ,	   0x16700000060e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP30_GRP_MSK"            ,	   0x16700000060f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP31_GRP_MSK"            ,	   0x16700000060f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1247},
+	{"SSO_PP0_QOS_PRI"             ,	   0x1670000003000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP1_QOS_PRI"             ,	   0x1670000003008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP2_QOS_PRI"             ,	   0x1670000003010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP3_QOS_PRI"             ,	   0x1670000003018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP4_QOS_PRI"             ,	   0x1670000003020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP5_QOS_PRI"             ,	   0x1670000003028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP6_QOS_PRI"             ,	   0x1670000003030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP7_QOS_PRI"             ,	   0x1670000003038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP8_QOS_PRI"             ,	   0x1670000003040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP9_QOS_PRI"             ,	   0x1670000003048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP10_QOS_PRI"            ,	   0x1670000003050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP11_QOS_PRI"            ,	   0x1670000003058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP12_QOS_PRI"            ,	   0x1670000003060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP13_QOS_PRI"            ,	   0x1670000003068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP14_QOS_PRI"            ,	   0x1670000003070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP15_QOS_PRI"            ,	   0x1670000003078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP16_QOS_PRI"            ,	   0x1670000003080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP17_QOS_PRI"            ,	   0x1670000003088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP18_QOS_PRI"            ,	   0x1670000003090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP19_QOS_PRI"            ,	   0x1670000003098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP20_QOS_PRI"            ,	   0x16700000030a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP21_QOS_PRI"            ,	   0x16700000030a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP22_QOS_PRI"            ,	   0x16700000030b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP23_QOS_PRI"            ,	   0x16700000030b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP24_QOS_PRI"            ,	   0x16700000030c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP25_QOS_PRI"            ,	   0x16700000030c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP26_QOS_PRI"            ,	   0x16700000030d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP27_QOS_PRI"            ,	   0x16700000030d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP28_QOS_PRI"            ,	   0x16700000030e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP29_QOS_PRI"            ,	   0x16700000030e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP30_QOS_PRI"            ,	   0x16700000030f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP31_QOS_PRI"            ,	   0x16700000030f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1248},
+	{"SSO_PP_STRICT"               ,	   0x16700000010e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1249},
+	{"SSO_QOS0_RND"                ,	   0x1670000002000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1250},
+	{"SSO_QOS1_RND"                ,	   0x1670000002008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1250},
+	{"SSO_QOS2_RND"                ,	   0x1670000002010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1250},
+	{"SSO_QOS3_RND"                ,	   0x1670000002018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1250},
+	{"SSO_QOS4_RND"                ,	   0x1670000002020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1250},
+	{"SSO_QOS5_RND"                ,	   0x1670000002028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1250},
+	{"SSO_QOS6_RND"                ,	   0x1670000002030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1250},
+	{"SSO_QOS7_RND"                ,	   0x1670000002038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1250},
+	{"SSO_QOS_THR0"                ,	   0x167000000b000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1251},
+	{"SSO_QOS_THR1"                ,	   0x167000000b008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1251},
+	{"SSO_QOS_THR2"                ,	   0x167000000b010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1251},
+	{"SSO_QOS_THR3"                ,	   0x167000000b018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1251},
+	{"SSO_QOS_THR4"                ,	   0x167000000b020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1251},
+	{"SSO_QOS_THR5"                ,	   0x167000000b028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1251},
+	{"SSO_QOS_THR6"                ,	   0x167000000b030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1251},
+	{"SSO_QOS_THR7"                ,	   0x167000000b038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1251},
+	{"SSO_QOS_WE"                  ,	   0x1670000001080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1252},
+	{"SSO_RESET"                   ,	   0x16700000010f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1253},
+	{"SSO_RWQ_HEAD_PTR0"           ,	   0x167000000c000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1254},
+	{"SSO_RWQ_HEAD_PTR1"           ,	   0x167000000c008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1254},
+	{"SSO_RWQ_HEAD_PTR2"           ,	   0x167000000c010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1254},
+	{"SSO_RWQ_HEAD_PTR3"           ,	   0x167000000c018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1254},
+	{"SSO_RWQ_HEAD_PTR4"           ,	   0x167000000c020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1254},
+	{"SSO_RWQ_HEAD_PTR5"           ,	   0x167000000c028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1254},
+	{"SSO_RWQ_HEAD_PTR6"           ,	   0x167000000c030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1254},
+	{"SSO_RWQ_HEAD_PTR7"           ,	   0x167000000c038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1254},
+	{"SSO_RWQ_POP_FPTR"            ,	   0x167000000c408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1255},
+	{"SSO_RWQ_PSH_FPTR"            ,	   0x167000000c400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1256},
+	{"SSO_RWQ_TAIL_PTR0"           ,	   0x167000000c200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1257},
+	{"SSO_RWQ_TAIL_PTR1"           ,	   0x167000000c208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1257},
+	{"SSO_RWQ_TAIL_PTR2"           ,	   0x167000000c210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1257},
+	{"SSO_RWQ_TAIL_PTR3"           ,	   0x167000000c218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1257},
+	{"SSO_RWQ_TAIL_PTR4"           ,	   0x167000000c220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1257},
+	{"SSO_RWQ_TAIL_PTR5"           ,	   0x167000000c228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1257},
+	{"SSO_RWQ_TAIL_PTR6"           ,	   0x167000000c230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1257},
+	{"SSO_RWQ_TAIL_PTR7"           ,	   0x167000000c238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1257},
+	{"SSO_TS_PC"                   ,	   0x1670000001068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1258},
+	{"SSO_WA_COM_PC"               ,	   0x1670000001060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1259},
+	{"SSO_WA_PC0"                  ,	   0x1670000005000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1260},
+	{"SSO_WA_PC1"                  ,	   0x1670000005008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1260},
+	{"SSO_WA_PC2"                  ,	   0x1670000005010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1260},
+	{"SSO_WA_PC3"                  ,	   0x1670000005018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1260},
+	{"SSO_WA_PC4"                  ,	   0x1670000005020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1260},
+	{"SSO_WA_PC5"                  ,	   0x1670000005028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1260},
+	{"SSO_WA_PC6"                  ,	   0x1670000005030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1260},
+	{"SSO_WA_PC7"                  ,	   0x1670000005038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1260},
+	{"SSO_WQ_INT"                  ,	   0x1670000001000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1261},
+	{"SSO_WQ_INT_CNT0"             ,	   0x1670000008000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT1"             ,	   0x1670000008008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT2"             ,	   0x1670000008010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT3"             ,	   0x1670000008018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT4"             ,	   0x1670000008020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT5"             ,	   0x1670000008028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT6"             ,	   0x1670000008030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT7"             ,	   0x1670000008038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT8"             ,	   0x1670000008040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT9"             ,	   0x1670000008048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT10"            ,	   0x1670000008050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT11"            ,	   0x1670000008058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT12"            ,	   0x1670000008060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT13"            ,	   0x1670000008068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT14"            ,	   0x1670000008070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT15"            ,	   0x1670000008078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT16"            ,	   0x1670000008080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT17"            ,	   0x1670000008088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT18"            ,	   0x1670000008090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT19"            ,	   0x1670000008098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT20"            ,	   0x16700000080a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT21"            ,	   0x16700000080a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT22"            ,	   0x16700000080b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT23"            ,	   0x16700000080b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT24"            ,	   0x16700000080c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT25"            ,	   0x16700000080c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT26"            ,	   0x16700000080d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT27"            ,	   0x16700000080d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT28"            ,	   0x16700000080e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT29"            ,	   0x16700000080e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT30"            ,	   0x16700000080f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT31"            ,	   0x16700000080f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT32"            ,	   0x1670000008100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT33"            ,	   0x1670000008108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT34"            ,	   0x1670000008110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT35"            ,	   0x1670000008118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT36"            ,	   0x1670000008120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT37"            ,	   0x1670000008128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT38"            ,	   0x1670000008130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT39"            ,	   0x1670000008138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT40"            ,	   0x1670000008140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT41"            ,	   0x1670000008148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT42"            ,	   0x1670000008150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT43"            ,	   0x1670000008158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT44"            ,	   0x1670000008160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT45"            ,	   0x1670000008168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT46"            ,	   0x1670000008170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT47"            ,	   0x1670000008178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT48"            ,	   0x1670000008180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT49"            ,	   0x1670000008188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT50"            ,	   0x1670000008190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT51"            ,	   0x1670000008198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT52"            ,	   0x16700000081a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT53"            ,	   0x16700000081a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT54"            ,	   0x16700000081b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT55"            ,	   0x16700000081b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT56"            ,	   0x16700000081c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT57"            ,	   0x16700000081c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT58"            ,	   0x16700000081d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT59"            ,	   0x16700000081d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT60"            ,	   0x16700000081e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT61"            ,	   0x16700000081e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT62"            ,	   0x16700000081f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_CNT63"            ,	   0x16700000081f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1262},
+	{"SSO_WQ_INT_PC"               ,	   0x1670000001020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1263},
+	{"SSO_WQ_INT_THR0"             ,	   0x1670000007000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR1"             ,	   0x1670000007008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR2"             ,	   0x1670000007010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR3"             ,	   0x1670000007018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR4"             ,	   0x1670000007020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR5"             ,	   0x1670000007028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR6"             ,	   0x1670000007030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR7"             ,	   0x1670000007038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR8"             ,	   0x1670000007040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR9"             ,	   0x1670000007048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR10"            ,	   0x1670000007050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR11"            ,	   0x1670000007058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR12"            ,	   0x1670000007060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR13"            ,	   0x1670000007068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR14"            ,	   0x1670000007070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR15"            ,	   0x1670000007078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR16"            ,	   0x1670000007080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR17"            ,	   0x1670000007088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR18"            ,	   0x1670000007090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR19"            ,	   0x1670000007098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR20"            ,	   0x16700000070a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR21"            ,	   0x16700000070a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR22"            ,	   0x16700000070b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR23"            ,	   0x16700000070b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR24"            ,	   0x16700000070c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR25"            ,	   0x16700000070c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR26"            ,	   0x16700000070d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR27"            ,	   0x16700000070d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR28"            ,	   0x16700000070e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR29"            ,	   0x16700000070e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR30"            ,	   0x16700000070f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR31"            ,	   0x16700000070f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR32"            ,	   0x1670000007100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR33"            ,	   0x1670000007108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR34"            ,	   0x1670000007110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR35"            ,	   0x1670000007118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR36"            ,	   0x1670000007120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR37"            ,	   0x1670000007128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR38"            ,	   0x1670000007130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR39"            ,	   0x1670000007138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR40"            ,	   0x1670000007140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR41"            ,	   0x1670000007148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR42"            ,	   0x1670000007150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR43"            ,	   0x1670000007158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR44"            ,	   0x1670000007160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR45"            ,	   0x1670000007168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR46"            ,	   0x1670000007170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR47"            ,	   0x1670000007178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR48"            ,	   0x1670000007180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR49"            ,	   0x1670000007188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR50"            ,	   0x1670000007190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR51"            ,	   0x1670000007198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR52"            ,	   0x16700000071a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR53"            ,	   0x16700000071a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR54"            ,	   0x16700000071b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR55"            ,	   0x16700000071b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR56"            ,	   0x16700000071c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR57"            ,	   0x16700000071c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR58"            ,	   0x16700000071d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR59"            ,	   0x16700000071d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR60"            ,	   0x16700000071e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR61"            ,	   0x16700000071e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR62"            ,	   0x16700000071f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_INT_THR63"            ,	   0x16700000071f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1264},
+	{"SSO_WQ_IQ_DIS"               ,	   0x1670000001010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1265},
+	{"SSO_WS_PC0"                  ,	   0x1670000004000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC1"                  ,	   0x1670000004008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC2"                  ,	   0x1670000004010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC3"                  ,	   0x1670000004018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC4"                  ,	   0x1670000004020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC5"                  ,	   0x1670000004028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC6"                  ,	   0x1670000004030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC7"                  ,	   0x1670000004038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC8"                  ,	   0x1670000004040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC9"                  ,	   0x1670000004048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC10"                 ,	   0x1670000004050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC11"                 ,	   0x1670000004058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC12"                 ,	   0x1670000004060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC13"                 ,	   0x1670000004068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC14"                 ,	   0x1670000004070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC15"                 ,	   0x1670000004078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC16"                 ,	   0x1670000004080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC17"                 ,	   0x1670000004088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC18"                 ,	   0x1670000004090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC19"                 ,	   0x1670000004098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC20"                 ,	   0x16700000040a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC21"                 ,	   0x16700000040a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC22"                 ,	   0x16700000040b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC23"                 ,	   0x16700000040b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC24"                 ,	   0x16700000040c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC25"                 ,	   0x16700000040c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC26"                 ,	   0x16700000040d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC27"                 ,	   0x16700000040d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC28"                 ,	   0x16700000040e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC29"                 ,	   0x16700000040e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC30"                 ,	   0x16700000040f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC31"                 ,	   0x16700000040f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC32"                 ,	   0x1670000004100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC33"                 ,	   0x1670000004108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC34"                 ,	   0x1670000004110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC35"                 ,	   0x1670000004118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC36"                 ,	   0x1670000004120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC37"                 ,	   0x1670000004128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC38"                 ,	   0x1670000004130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC39"                 ,	   0x1670000004138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC40"                 ,	   0x1670000004140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC41"                 ,	   0x1670000004148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC42"                 ,	   0x1670000004150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC43"                 ,	   0x1670000004158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC44"                 ,	   0x1670000004160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC45"                 ,	   0x1670000004168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC46"                 ,	   0x1670000004170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC47"                 ,	   0x1670000004178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC48"                 ,	   0x1670000004180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC49"                 ,	   0x1670000004188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC50"                 ,	   0x1670000004190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC51"                 ,	   0x1670000004198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC52"                 ,	   0x16700000041a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC53"                 ,	   0x16700000041a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC54"                 ,	   0x16700000041b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC55"                 ,	   0x16700000041b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC56"                 ,	   0x16700000041c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC57"                 ,	   0x16700000041c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC58"                 ,	   0x16700000041d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC59"                 ,	   0x16700000041d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC60"                 ,	   0x16700000041e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC61"                 ,	   0x16700000041e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC62"                 ,	   0x16700000041f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"SSO_WS_PC63"                 ,	   0x16700000041f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1266},
+	{"TIM_BIST_RESULT"             ,	   0x1180058000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1267},
+	{"TIM_DBG2"                    ,	   0x11800580000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1268},
+	{"TIM_DBG3"                    ,	   0x11800580000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1269},
+	{"TIM_ECC_CFG"                 ,	   0x1180058000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1270},
+	{"TIM_FR_RN_TT"                ,	   0x1180058000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1271},
+	{"TIM_GPIO_EN"                 ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1272},
+	{"TIM_INT0"                    ,	   0x1180058000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1273},
+	{"TIM_INT0_EN"                 ,	   0x1180058000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1274},
+	{"TIM_INT0_EVENT"              ,	   0x1180058000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1275},
+	{"TIM_INT_ECCERR"              ,	   0x1180058000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1276},
+	{"TIM_INT_ECCERR_EN"           ,	   0x1180058000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1277},
+	{"TIM_INT_ECCERR_EVENT0"       ,	   0x1180058000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1278},
+	{"TIM_INT_ECCERR_EVENT1"       ,	   0x1180058000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1279},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1280},
+	{"TIM_RING0_CTL0"              ,	   0x1180058002000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING1_CTL0"              ,	   0x1180058002008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING2_CTL0"              ,	   0x1180058002010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING3_CTL0"              ,	   0x1180058002018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING4_CTL0"              ,	   0x1180058002020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING5_CTL0"              ,	   0x1180058002028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING6_CTL0"              ,	   0x1180058002030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING7_CTL0"              ,	   0x1180058002038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING8_CTL0"              ,	   0x1180058002040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING9_CTL0"              ,	   0x1180058002048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING10_CTL0"             ,	   0x1180058002050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING11_CTL0"             ,	   0x1180058002058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING12_CTL0"             ,	   0x1180058002060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING13_CTL0"             ,	   0x1180058002068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING14_CTL0"             ,	   0x1180058002070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING15_CTL0"             ,	   0x1180058002078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING16_CTL0"             ,	   0x1180058002080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING17_CTL0"             ,	   0x1180058002088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING18_CTL0"             ,	   0x1180058002090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING19_CTL0"             ,	   0x1180058002098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING20_CTL0"             ,	   0x11800580020a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING21_CTL0"             ,	   0x11800580020a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING22_CTL0"             ,	   0x11800580020b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING23_CTL0"             ,	   0x11800580020b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING24_CTL0"             ,	   0x11800580020c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING25_CTL0"             ,	   0x11800580020c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING26_CTL0"             ,	   0x11800580020d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING27_CTL0"             ,	   0x11800580020d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING28_CTL0"             ,	   0x11800580020e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING29_CTL0"             ,	   0x11800580020e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING30_CTL0"             ,	   0x11800580020f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING31_CTL0"             ,	   0x11800580020f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING32_CTL0"             ,	   0x1180058002100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING33_CTL0"             ,	   0x1180058002108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING34_CTL0"             ,	   0x1180058002110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING35_CTL0"             ,	   0x1180058002118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING36_CTL0"             ,	   0x1180058002120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING37_CTL0"             ,	   0x1180058002128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING38_CTL0"             ,	   0x1180058002130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING39_CTL0"             ,	   0x1180058002138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING40_CTL0"             ,	   0x1180058002140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING41_CTL0"             ,	   0x1180058002148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING42_CTL0"             ,	   0x1180058002150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING43_CTL0"             ,	   0x1180058002158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING44_CTL0"             ,	   0x1180058002160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING45_CTL0"             ,	   0x1180058002168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING46_CTL0"             ,	   0x1180058002170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING47_CTL0"             ,	   0x1180058002178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING48_CTL0"             ,	   0x1180058002180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING49_CTL0"             ,	   0x1180058002188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING50_CTL0"             ,	   0x1180058002190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING51_CTL0"             ,	   0x1180058002198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING52_CTL0"             ,	   0x11800580021a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING53_CTL0"             ,	   0x11800580021a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING54_CTL0"             ,	   0x11800580021b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING55_CTL0"             ,	   0x11800580021b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING56_CTL0"             ,	   0x11800580021c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING57_CTL0"             ,	   0x11800580021c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING58_CTL0"             ,	   0x11800580021d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING59_CTL0"             ,	   0x11800580021d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING60_CTL0"             ,	   0x11800580021e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING61_CTL0"             ,	   0x11800580021e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING62_CTL0"             ,	   0x11800580021f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING63_CTL0"             ,	   0x11800580021f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1281},
+	{"TIM_RING0_CTL1"              ,	   0x1180058002400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING1_CTL1"              ,	   0x1180058002408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING2_CTL1"              ,	   0x1180058002410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING3_CTL1"              ,	   0x1180058002418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING4_CTL1"              ,	   0x1180058002420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING5_CTL1"              ,	   0x1180058002428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING6_CTL1"              ,	   0x1180058002430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING7_CTL1"              ,	   0x1180058002438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING8_CTL1"              ,	   0x1180058002440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING9_CTL1"              ,	   0x1180058002448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING10_CTL1"             ,	   0x1180058002450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING11_CTL1"             ,	   0x1180058002458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING12_CTL1"             ,	   0x1180058002460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING13_CTL1"             ,	   0x1180058002468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING14_CTL1"             ,	   0x1180058002470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING15_CTL1"             ,	   0x1180058002478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING16_CTL1"             ,	   0x1180058002480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING17_CTL1"             ,	   0x1180058002488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING18_CTL1"             ,	   0x1180058002490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING19_CTL1"             ,	   0x1180058002498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING20_CTL1"             ,	   0x11800580024a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING21_CTL1"             ,	   0x11800580024a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING22_CTL1"             ,	   0x11800580024b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING23_CTL1"             ,	   0x11800580024b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING24_CTL1"             ,	   0x11800580024c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING25_CTL1"             ,	   0x11800580024c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING26_CTL1"             ,	   0x11800580024d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING27_CTL1"             ,	   0x11800580024d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING28_CTL1"             ,	   0x11800580024e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING29_CTL1"             ,	   0x11800580024e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING30_CTL1"             ,	   0x11800580024f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING31_CTL1"             ,	   0x11800580024f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING32_CTL1"             ,	   0x1180058002500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING33_CTL1"             ,	   0x1180058002508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING34_CTL1"             ,	   0x1180058002510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING35_CTL1"             ,	   0x1180058002518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING36_CTL1"             ,	   0x1180058002520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING37_CTL1"             ,	   0x1180058002528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING38_CTL1"             ,	   0x1180058002530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING39_CTL1"             ,	   0x1180058002538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING40_CTL1"             ,	   0x1180058002540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING41_CTL1"             ,	   0x1180058002548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING42_CTL1"             ,	   0x1180058002550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING43_CTL1"             ,	   0x1180058002558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING44_CTL1"             ,	   0x1180058002560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING45_CTL1"             ,	   0x1180058002568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING46_CTL1"             ,	   0x1180058002570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING47_CTL1"             ,	   0x1180058002578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING48_CTL1"             ,	   0x1180058002580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING49_CTL1"             ,	   0x1180058002588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING50_CTL1"             ,	   0x1180058002590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING51_CTL1"             ,	   0x1180058002598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING52_CTL1"             ,	   0x11800580025a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING53_CTL1"             ,	   0x11800580025a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING54_CTL1"             ,	   0x11800580025b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING55_CTL1"             ,	   0x11800580025b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING56_CTL1"             ,	   0x11800580025c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING57_CTL1"             ,	   0x11800580025c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING58_CTL1"             ,	   0x11800580025d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING59_CTL1"             ,	   0x11800580025d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING60_CTL1"             ,	   0x11800580025e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING61_CTL1"             ,	   0x11800580025e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING62_CTL1"             ,	   0x11800580025f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING63_CTL1"             ,	   0x11800580025f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1282},
+	{"TIM_RING0_CTL2"              ,	   0x1180058002800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING1_CTL2"              ,	   0x1180058002808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING2_CTL2"              ,	   0x1180058002810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING3_CTL2"              ,	   0x1180058002818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING4_CTL2"              ,	   0x1180058002820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING5_CTL2"              ,	   0x1180058002828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING6_CTL2"              ,	   0x1180058002830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING7_CTL2"              ,	   0x1180058002838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING8_CTL2"              ,	   0x1180058002840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING9_CTL2"              ,	   0x1180058002848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING10_CTL2"             ,	   0x1180058002850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING11_CTL2"             ,	   0x1180058002858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING12_CTL2"             ,	   0x1180058002860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING13_CTL2"             ,	   0x1180058002868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING14_CTL2"             ,	   0x1180058002870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING15_CTL2"             ,	   0x1180058002878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING16_CTL2"             ,	   0x1180058002880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING17_CTL2"             ,	   0x1180058002888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING18_CTL2"             ,	   0x1180058002890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING19_CTL2"             ,	   0x1180058002898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING20_CTL2"             ,	   0x11800580028a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING21_CTL2"             ,	   0x11800580028a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING22_CTL2"             ,	   0x11800580028b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING23_CTL2"             ,	   0x11800580028b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING24_CTL2"             ,	   0x11800580028c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING25_CTL2"             ,	   0x11800580028c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING26_CTL2"             ,	   0x11800580028d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING27_CTL2"             ,	   0x11800580028d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING28_CTL2"             ,	   0x11800580028e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING29_CTL2"             ,	   0x11800580028e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING30_CTL2"             ,	   0x11800580028f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING31_CTL2"             ,	   0x11800580028f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING32_CTL2"             ,	   0x1180058002900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING33_CTL2"             ,	   0x1180058002908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING34_CTL2"             ,	   0x1180058002910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING35_CTL2"             ,	   0x1180058002918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING36_CTL2"             ,	   0x1180058002920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING37_CTL2"             ,	   0x1180058002928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING38_CTL2"             ,	   0x1180058002930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING39_CTL2"             ,	   0x1180058002938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING40_CTL2"             ,	   0x1180058002940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING41_CTL2"             ,	   0x1180058002948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING42_CTL2"             ,	   0x1180058002950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING43_CTL2"             ,	   0x1180058002958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING44_CTL2"             ,	   0x1180058002960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING45_CTL2"             ,	   0x1180058002968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING46_CTL2"             ,	   0x1180058002970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING47_CTL2"             ,	   0x1180058002978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING48_CTL2"             ,	   0x1180058002980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING49_CTL2"             ,	   0x1180058002988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING50_CTL2"             ,	   0x1180058002990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING51_CTL2"             ,	   0x1180058002998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING52_CTL2"             ,	   0x11800580029a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING53_CTL2"             ,	   0x11800580029a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING54_CTL2"             ,	   0x11800580029b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING55_CTL2"             ,	   0x11800580029b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING56_CTL2"             ,	   0x11800580029c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING57_CTL2"             ,	   0x11800580029c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING58_CTL2"             ,	   0x11800580029d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING59_CTL2"             ,	   0x11800580029d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING60_CTL2"             ,	   0x11800580029e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING61_CTL2"             ,	   0x11800580029e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING62_CTL2"             ,	   0x11800580029f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING63_CTL2"             ,	   0x11800580029f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1283},
+	{"TIM_RING0_DBG0"              ,	   0x1180058003000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING1_DBG0"              ,	   0x1180058003008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING2_DBG0"              ,	   0x1180058003010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING3_DBG0"              ,	   0x1180058003018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING4_DBG0"              ,	   0x1180058003020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING5_DBG0"              ,	   0x1180058003028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING6_DBG0"              ,	   0x1180058003030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING7_DBG0"              ,	   0x1180058003038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING8_DBG0"              ,	   0x1180058003040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING9_DBG0"              ,	   0x1180058003048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING10_DBG0"             ,	   0x1180058003050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING11_DBG0"             ,	   0x1180058003058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING12_DBG0"             ,	   0x1180058003060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING13_DBG0"             ,	   0x1180058003068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING14_DBG0"             ,	   0x1180058003070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING15_DBG0"             ,	   0x1180058003078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING16_DBG0"             ,	   0x1180058003080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING17_DBG0"             ,	   0x1180058003088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING18_DBG0"             ,	   0x1180058003090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING19_DBG0"             ,	   0x1180058003098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING20_DBG0"             ,	   0x11800580030a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING21_DBG0"             ,	   0x11800580030a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING22_DBG0"             ,	   0x11800580030b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING23_DBG0"             ,	   0x11800580030b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING24_DBG0"             ,	   0x11800580030c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING25_DBG0"             ,	   0x11800580030c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING26_DBG0"             ,	   0x11800580030d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING27_DBG0"             ,	   0x11800580030d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING28_DBG0"             ,	   0x11800580030e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING29_DBG0"             ,	   0x11800580030e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING30_DBG0"             ,	   0x11800580030f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING31_DBG0"             ,	   0x11800580030f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING32_DBG0"             ,	   0x1180058003100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING33_DBG0"             ,	   0x1180058003108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING34_DBG0"             ,	   0x1180058003110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING35_DBG0"             ,	   0x1180058003118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING36_DBG0"             ,	   0x1180058003120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING37_DBG0"             ,	   0x1180058003128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING38_DBG0"             ,	   0x1180058003130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING39_DBG0"             ,	   0x1180058003138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING40_DBG0"             ,	   0x1180058003140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING41_DBG0"             ,	   0x1180058003148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING42_DBG0"             ,	   0x1180058003150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING43_DBG0"             ,	   0x1180058003158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING44_DBG0"             ,	   0x1180058003160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING45_DBG0"             ,	   0x1180058003168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING46_DBG0"             ,	   0x1180058003170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING47_DBG0"             ,	   0x1180058003178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING48_DBG0"             ,	   0x1180058003180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING49_DBG0"             ,	   0x1180058003188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING50_DBG0"             ,	   0x1180058003190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING51_DBG0"             ,	   0x1180058003198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING52_DBG0"             ,	   0x11800580031a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING53_DBG0"             ,	   0x11800580031a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING54_DBG0"             ,	   0x11800580031b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING55_DBG0"             ,	   0x11800580031b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING56_DBG0"             ,	   0x11800580031c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING57_DBG0"             ,	   0x11800580031c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING58_DBG0"             ,	   0x11800580031d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING59_DBG0"             ,	   0x11800580031d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING60_DBG0"             ,	   0x11800580031e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING61_DBG0"             ,	   0x11800580031e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING62_DBG0"             ,	   0x11800580031f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING63_DBG0"             ,	   0x11800580031f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1284},
+	{"TIM_RING0_DBG1"              ,	   0x1180058001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING1_DBG1"              ,	   0x1180058001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING2_DBG1"              ,	   0x1180058001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING3_DBG1"              ,	   0x1180058001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING4_DBG1"              ,	   0x1180058001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING5_DBG1"              ,	   0x1180058001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING6_DBG1"              ,	   0x1180058001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING7_DBG1"              ,	   0x1180058001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING8_DBG1"              ,	   0x1180058001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING9_DBG1"              ,	   0x1180058001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING10_DBG1"             ,	   0x1180058001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING11_DBG1"             ,	   0x1180058001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING12_DBG1"             ,	   0x1180058001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING13_DBG1"             ,	   0x1180058001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING14_DBG1"             ,	   0x1180058001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING15_DBG1"             ,	   0x1180058001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING16_DBG1"             ,	   0x1180058001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING17_DBG1"             ,	   0x1180058001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING18_DBG1"             ,	   0x1180058001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING19_DBG1"             ,	   0x1180058001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING20_DBG1"             ,	   0x11800580012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING21_DBG1"             ,	   0x11800580012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING22_DBG1"             ,	   0x11800580012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING23_DBG1"             ,	   0x11800580012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING24_DBG1"             ,	   0x11800580012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING25_DBG1"             ,	   0x11800580012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING26_DBG1"             ,	   0x11800580012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING27_DBG1"             ,	   0x11800580012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING28_DBG1"             ,	   0x11800580012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING29_DBG1"             ,	   0x11800580012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING30_DBG1"             ,	   0x11800580012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING31_DBG1"             ,	   0x11800580012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING32_DBG1"             ,	   0x1180058001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING33_DBG1"             ,	   0x1180058001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING34_DBG1"             ,	   0x1180058001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING35_DBG1"             ,	   0x1180058001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING36_DBG1"             ,	   0x1180058001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING37_DBG1"             ,	   0x1180058001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING38_DBG1"             ,	   0x1180058001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING39_DBG1"             ,	   0x1180058001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING40_DBG1"             ,	   0x1180058001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING41_DBG1"             ,	   0x1180058001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING42_DBG1"             ,	   0x1180058001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING43_DBG1"             ,	   0x1180058001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING44_DBG1"             ,	   0x1180058001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING45_DBG1"             ,	   0x1180058001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING46_DBG1"             ,	   0x1180058001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING47_DBG1"             ,	   0x1180058001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING48_DBG1"             ,	   0x1180058001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING49_DBG1"             ,	   0x1180058001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING50_DBG1"             ,	   0x1180058001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING51_DBG1"             ,	   0x1180058001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING52_DBG1"             ,	   0x11800580013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING53_DBG1"             ,	   0x11800580013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING54_DBG1"             ,	   0x11800580013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING55_DBG1"             ,	   0x11800580013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING56_DBG1"             ,	   0x11800580013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING57_DBG1"             ,	   0x11800580013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING58_DBG1"             ,	   0x11800580013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING59_DBG1"             ,	   0x11800580013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING60_DBG1"             ,	   0x11800580013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING61_DBG1"             ,	   0x11800580013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING62_DBG1"             ,	   0x11800580013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TIM_RING63_DBG1"             ,	   0x11800580013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1285},
+	{"TRA0_BIST_STATUS"            ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1286},
+	{"TRA1_BIST_STATUS"            ,	   0x11800a8100010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1286},
+	{"TRA2_BIST_STATUS"            ,	   0x11800a8200010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1286},
+	{"TRA3_BIST_STATUS"            ,	   0x11800a8300010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1286},
+	{"TRA0_CTL"                    ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1287},
+	{"TRA1_CTL"                    ,	   0x11800a8100000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1287},
+	{"TRA2_CTL"                    ,	   0x11800a8200000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1287},
+	{"TRA3_CTL"                    ,	   0x11800a8300000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1287},
+	{"TRA0_CYCLES_SINCE"           ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1288},
+	{"TRA1_CYCLES_SINCE"           ,	   0x11800a8100018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1288},
+	{"TRA2_CYCLES_SINCE"           ,	   0x11800a8200018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1288},
+	{"TRA3_CYCLES_SINCE"           ,	   0x11800a8300018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1288},
+	{"TRA0_CYCLES_SINCE1"          ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1289},
+	{"TRA1_CYCLES_SINCE1"          ,	   0x11800a8100028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1289},
+	{"TRA2_CYCLES_SINCE1"          ,	   0x11800a8200028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1289},
+	{"TRA3_CYCLES_SINCE1"          ,	   0x11800a8300028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1289},
+	{"TRA0_FILT_ADR_ADR"           ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1290},
+	{"TRA1_FILT_ADR_ADR"           ,	   0x11800a8100058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1290},
+	{"TRA2_FILT_ADR_ADR"           ,	   0x11800a8200058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1290},
+	{"TRA3_FILT_ADR_ADR"           ,	   0x11800a8300058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1290},
+	{"TRA0_FILT_ADR_MSK"           ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1291},
+	{"TRA1_FILT_ADR_MSK"           ,	   0x11800a8100060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1291},
+	{"TRA2_FILT_ADR_MSK"           ,	   0x11800a8200060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1291},
+	{"TRA3_FILT_ADR_MSK"           ,	   0x11800a8300060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1291},
+	{"TRA0_FILT_CMD"               ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1292},
+	{"TRA1_FILT_CMD"               ,	   0x11800a8100040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1292},
+	{"TRA2_FILT_CMD"               ,	   0x11800a8200040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1292},
+	{"TRA3_FILT_CMD"               ,	   0x11800a8300040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1292},
+	{"TRA0_FILT_DID"               ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1293},
+	{"TRA1_FILT_DID"               ,	   0x11800a8100050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1293},
+	{"TRA2_FILT_DID"               ,	   0x11800a8200050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1293},
+	{"TRA3_FILT_DID"               ,	   0x11800a8300050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1293},
+	{"TRA0_FILT_SID"               ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1294},
+	{"TRA1_FILT_SID"               ,	   0x11800a8100048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1294},
+	{"TRA2_FILT_SID"               ,	   0x11800a8200048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1294},
+	{"TRA3_FILT_SID"               ,	   0x11800a8300048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1294},
+	{"TRA0_INT_STATUS"             ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1295},
+	{"TRA1_INT_STATUS"             ,	   0x11800a8100008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1295},
+	{"TRA2_INT_STATUS"             ,	   0x11800a8200008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1295},
+	{"TRA3_INT_STATUS"             ,	   0x11800a8300008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1295},
+	{"TRA0_READ_DAT"               ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1296},
+	{"TRA1_READ_DAT"               ,	   0x11800a8100020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1296},
+	{"TRA2_READ_DAT"               ,	   0x11800a8200020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1296},
+	{"TRA3_READ_DAT"               ,	   0x11800a8300020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1296},
+	{"TRA0_READ_DAT_HI"            ,	   0x11800a8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1297},
+	{"TRA1_READ_DAT_HI"            ,	   0x11800a8100030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1297},
+	{"TRA2_READ_DAT_HI"            ,	   0x11800a8200030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1297},
+	{"TRA3_READ_DAT_HI"            ,	   0x11800a8300030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1297},
+	{"TRA0_TRIG0_ADR_ADR"          ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1298},
+	{"TRA1_TRIG0_ADR_ADR"          ,	   0x11800a8100098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1298},
+	{"TRA2_TRIG0_ADR_ADR"          ,	   0x11800a8200098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1298},
+	{"TRA3_TRIG0_ADR_ADR"          ,	   0x11800a8300098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1298},
+	{"TRA0_TRIG0_ADR_MSK"          ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1299},
+	{"TRA1_TRIG0_ADR_MSK"          ,	   0x11800a81000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1299},
+	{"TRA2_TRIG0_ADR_MSK"          ,	   0x11800a82000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1299},
+	{"TRA3_TRIG0_ADR_MSK"          ,	   0x11800a83000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1299},
+	{"TRA0_TRIG0_CMD"              ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1300},
+	{"TRA1_TRIG0_CMD"              ,	   0x11800a8100080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1300},
+	{"TRA2_TRIG0_CMD"              ,	   0x11800a8200080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1300},
+	{"TRA3_TRIG0_CMD"              ,	   0x11800a8300080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1300},
+	{"TRA0_TRIG0_DID"              ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1301},
+	{"TRA1_TRIG0_DID"              ,	   0x11800a8100090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1301},
+	{"TRA2_TRIG0_DID"              ,	   0x11800a8200090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1301},
+	{"TRA3_TRIG0_DID"              ,	   0x11800a8300090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1301},
+	{"TRA0_TRIG0_SID"              ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1302},
+	{"TRA1_TRIG0_SID"              ,	   0x11800a8100088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1302},
+	{"TRA2_TRIG0_SID"              ,	   0x11800a8200088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1302},
+	{"TRA3_TRIG0_SID"              ,	   0x11800a8300088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1302},
+	{"TRA0_TRIG1_ADR_ADR"          ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1303},
+	{"TRA1_TRIG1_ADR_ADR"          ,	   0x11800a81000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1303},
+	{"TRA2_TRIG1_ADR_ADR"          ,	   0x11800a82000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1303},
+	{"TRA3_TRIG1_ADR_ADR"          ,	   0x11800a83000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1303},
+	{"TRA0_TRIG1_ADR_MSK"          ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1304},
+	{"TRA1_TRIG1_ADR_MSK"          ,	   0x11800a81000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1304},
+	{"TRA2_TRIG1_ADR_MSK"          ,	   0x11800a82000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1304},
+	{"TRA3_TRIG1_ADR_MSK"          ,	   0x11800a83000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1304},
+	{"TRA0_TRIG1_CMD"              ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1305},
+	{"TRA1_TRIG1_CMD"              ,	   0x11800a81000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1305},
+	{"TRA2_TRIG1_CMD"              ,	   0x11800a82000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1305},
+	{"TRA3_TRIG1_CMD"              ,	   0x11800a83000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1305},
+	{"TRA0_TRIG1_DID"              ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1306},
+	{"TRA1_TRIG1_DID"              ,	   0x11800a81000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1306},
+	{"TRA2_TRIG1_DID"              ,	   0x11800a82000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1306},
+	{"TRA3_TRIG1_DID"              ,	   0x11800a83000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1306},
+	{"TRA0_TRIG1_SID"              ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1307},
+	{"TRA1_TRIG1_SID"              ,	   0x11800a81000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1307},
+	{"TRA2_TRIG1_SID"              ,	   0x11800a82000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1307},
+	{"TRA3_TRIG1_SID"              ,	   0x11800a83000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1307},
+	{"UAHC0_EHCI_ASYNCLISTADDR"    ,	   0x16f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1308},
+	{"UAHC0_EHCI_CONFIGFLAG"       ,	   0x16f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1309},
+	{"UAHC0_EHCI_CTRLDSSEGMENT"    ,	   0x16f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1310},
+	{"UAHC0_EHCI_FRINDEX"          ,	   0x16f000000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1311},
+	{"UAHC0_EHCI_HCCAPBASE"        ,	   0x16f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1312},
+	{"UAHC0_EHCI_HCCPARAMS"        ,	   0x16f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1313},
+	{"UAHC0_EHCI_HCSPARAMS"        ,	   0x16f0000000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1314},
+	{"UAHC0_EHCI_INSNREG00"        ,	   0x16f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1315},
+	{"UAHC0_EHCI_INSNREG03"        ,	   0x16f000000009cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1316},
+	{"UAHC0_EHCI_INSNREG04"        ,	   0x16f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1317},
+	{"UAHC0_EHCI_INSNREG06"        ,	   0x16f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1318},
+	{"UAHC0_EHCI_INSNREG07"        ,	   0x16f00000000ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	1319},
+	{"UAHC0_EHCI_PERIODICLISTBASE" ,	   0x16f0000000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1320},
+	{"UAHC0_EHCI_PORTSC001"        ,	   0x16f0000000054ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1321},
+	{"UAHC0_EHCI_PORTSC002"        ,	   0x16f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1321},
+	{"UAHC0_EHCI_USBCMD"           ,	   0x16f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1322},
+	{"UAHC0_EHCI_USBINTR"          ,	   0x16f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1323},
+	{"UAHC0_EHCI_USBSTS"           ,	   0x16f0000000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1324},
+	{"UAHC0_OHCI0_HCBULKCURRENTED" ,	   0x16f000000042cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1325},
+	{"UAHC0_OHCI0_HCBULKHEADED"    ,	   0x16f0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1326},
+	{"UAHC0_OHCI0_HCCOMMANDSTATUS" ,	   0x16f0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1327},
+	{"UAHC0_OHCI0_HCCONTROL"       ,	   0x16f0000000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1328},
+	{"UAHC0_OHCI0_HCCONTROLCURRENTED",	   0x16f0000000424ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1329},
+	{"UAHC0_OHCI0_HCCONTROLHEADED" ,	   0x16f0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1330},
+	{"UAHC0_OHCI0_HCDONEHEAD"      ,	   0x16f0000000430ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1331},
+	{"UAHC0_OHCI0_HCFMINTERVAL"    ,	   0x16f0000000434ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1332},
+	{"UAHC0_OHCI0_HCFMNUMBER"      ,	   0x16f000000043cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1333},
+	{"UAHC0_OHCI0_HCFMREMAINING"   ,	   0x16f0000000438ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1334},
+	{"UAHC0_OHCI0_HCHCCA"          ,	   0x16f0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1335},
+	{"UAHC0_OHCI0_HCINTERRUPTDISABLE",	   0x16f0000000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1336},
+	{"UAHC0_OHCI0_HCINTERRUPTENABLE",	   0x16f0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1337},
+	{"UAHC0_OHCI0_HCINTERRUPTSTATUS",	   0x16f000000040cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1338},
+	{"UAHC0_OHCI0_HCLSTHRESHOLD"   ,	   0x16f0000000444ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1339},
+	{"UAHC0_OHCI0_HCPERIODCURRENTED",	   0x16f000000041cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1340},
+	{"UAHC0_OHCI0_HCPERIODICSTART" ,	   0x16f0000000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1341},
+	{"UAHC0_OHCI0_HCREVISION"      ,	   0x16f0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1342},
+	{"UAHC0_OHCI0_HCRHDESCRIPTORA" ,	   0x16f0000000448ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1343},
+	{"UAHC0_OHCI0_HCRHDESCRIPTORB" ,	   0x16f000000044cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1344},
+	{"UAHC0_OHCI0_HCRHPORTSTATUS001",	   0x16f0000000454ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1345},
+	{"UAHC0_OHCI0_HCRHPORTSTATUS002",	   0x16f0000000458ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1345},
+	{"UAHC0_OHCI0_HCRHSTATUS"      ,	   0x16f0000000450ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1346},
+	{"UAHC0_OHCI0_INSNREG06"       ,	   0x16f0000000498ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1347},
+	{"UAHC0_OHCI0_INSNREG07"       ,	   0x16f000000049cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1348},
+	{"UCTL0_BIST_STATUS"           ,	   0x118006f0000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1349},
+	{"UCTL0_CLK_RST_CTL"           ,	   0x118006f000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1350},
+	{"UCTL0_EHCI_CTL"              ,	   0x118006f000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1351},
+	{"UCTL0_EHCI_FLA"              ,	   0x118006f0000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1352},
+	{"UCTL0_ERTO_CTL"              ,	   0x118006f000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1353},
+	{"UCTL0_IF_ENA"                ,	   0x118006f000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1354},
+	{"UCTL0_INT_ENA"               ,	   0x118006f000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1355},
+	{"UCTL0_INT_REG"               ,	   0x118006f000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1356},
+	{"UCTL0_OHCI_CTL"              ,	   0x118006f000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1357},
+	{"UCTL0_ORTO_CTL"              ,	   0x118006f000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1358},
+	{"UCTL0_UPHY_CTL_STATUS"       ,	   0x118006f000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1359},
+	{"UCTL0_UPHY_PORT000_CTL_STATUS",	   0x118006f000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1360},
+	{"UCTL0_UPHY_PORT001_CTL_STATUS",	   0x118006f000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1360},
+	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1361},
+	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1362},
+	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1363},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1364},
+	{"ZIP_CORE0_BIST_STATUS"       ,	   0x1180038000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1365},
+	{"ZIP_CORE1_BIST_STATUS"       ,	   0x1180038000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1365},
+	{"ZIP_CTL_BIST_STATUS"         ,	   0x1180038000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1366},
+	{"ZIP_CTL_CFG"                 ,	   0x1180038000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1367},
+	{"ZIP_DBG_CORE0_INST"          ,	   0x1180038000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1368},
+	{"ZIP_DBG_CORE1_INST"          ,	   0x1180038000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1368},
+	{"ZIP_DBG_CORE0_STA"           ,	   0x1180038000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1369},
+	{"ZIP_DBG_CORE1_STA"           ,	   0x1180038000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1369},
+	{"ZIP_DBG_QUE0_STA"            ,	   0x1180038000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1370},
+	{"ZIP_DBG_QUE1_STA"            ,	   0x1180038000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1370},
+	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1371},
+	{"ZIP_ECC_CTL"                 ,	   0x1180038000568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1372},
+	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1373},
+	{"ZIP_INT_ENA"                 ,	   0x1180038000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1374},
+	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1375},
+	{"ZIP_INT_REG"                 ,	   0x1180038000570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1376},
+	{"ZIP_QUE0_BUF"                ,	   0x1180038000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1377},
+	{"ZIP_QUE1_BUF"                ,	   0x1180038000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1377},
+	{"ZIP_QUE0_ECC_ERR_STA"        ,	   0x1180038000590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1378},
+	{"ZIP_QUE1_ECC_ERR_STA"        ,	   0x1180038000598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1378},
+	{"ZIP_QUE0_MAP"                ,	   0x1180038000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1379},
+	{"ZIP_QUE1_MAP"                ,	   0x1180038000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1379},
+	{"ZIP_QUE_ENA"                 ,	   0x1180038000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1380},
+	{"ZIP_QUE_PRI"                 ,	   0x1180038000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1381},
+	{"ZIP_THROTTLE"                ,	   0x1180038000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1382},
+	{NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn68xx[] = {
+	/* name                        ,	bit,	width,	csr,	type,	rst un,	typ un,	reset,	typical */
+	{"RESERVED_0_1"                ,	0,	2,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OUT_OVR"                     ,	2,	2,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_21"               ,	4,	18,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LOSTSTAT"                    ,	22,	2,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_25"              ,	24,	2,	0,	"RAZ",	1,	1,	0,	0},
+	{"STATOVR"                     ,	26,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_31"              ,	27,	5,	0,	"RAZ",	1,	1,	0,	0},
+	{"OVRFLW"                      ,	32,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP"                       ,	33,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH"                       ,	34,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRFLW1"                     ,	35,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP1"                      ,	36,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH1"                      ,	37,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	0,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	25,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	2,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	2,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	2,	"R/W",	0,	1,	1ull,	0},
+	{"RX_EN"                       ,	4,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"TX_EN"                       ,	5,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"BURST"                       ,	6,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	2,	"RAZ",	1,	1,	0,	0},
+	{"SPEED_MSB"                   ,	8,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	2,	"RAZ",	1,	1,	0,	0},
+	{"RX_IDLE"                     ,	12,	1,	2,	"RO",	0,	1,	1ull,	0},
+	{"TX_IDLE"                     ,	13,	1,	2,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	2,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	3,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	4,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	5,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	6,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	7,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	8,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	9,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	9,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	10,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	10,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	10,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	10,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	11,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	11,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR"                      ,	2,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"JABBER"                      ,	3,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALNERR"                      ,	5,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR"                      ,	6,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"RCVERR"                      ,	7,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"NIBERR"                      ,	9,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	12,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	13,	"RO",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	7,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	8,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_ALIGN"                   ,	9,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"NULL_DIS"                    ,	10,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	13,	"RAZ",	1,	1,	0,	0},
+	{"PTP_MODE"                    ,	12,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	13,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	14,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_16_63"              ,	16,	48,	14,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	15,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_16_63"              ,	16,	48,	15,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	16,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	16,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	17,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	18,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	19,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	19,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	20,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	20,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	1,	21,	"RO",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	2,	21,	"RO",	0,	1,	0ull,	0},
+	{"DUPLEX"                      ,	3,	1,	21,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	21,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	22,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	22,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	23,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	23,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	24,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	24,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	25,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	25,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	26,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	26,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	27,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	27,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	28,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	28,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	29,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	29,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	30,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	30,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	31,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	31,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	32,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	32,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	32,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	32,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	33,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	33,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	34,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	34,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	35,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_9_63"               ,	9,	55,	35,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	2,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_15"               ,	2,	14,	36,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	2,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	36,	"RAZ",	1,	1,	0,	0},
+	{"RX"                          ,	0,	2,	37,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	37,	"RAZ",	1,	1,	0,	0},
+	{"TX"                          ,	4,	2,	37,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	37,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	38,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	38,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	39,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	39,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	40,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	6,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_63"               ,	6,	58,	41,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	42,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	43,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	43,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	44,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	44,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	45,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	45,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	46,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	46,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	47,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	47,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	48,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	48,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	51,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	51,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	52,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	52,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	59,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	6,	60,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	60,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	2,	61,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	61,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	62,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	62,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	63,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	63,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	63,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	64,	"RAZ",	1,	1,	0,	0},
+	{"UNDFLW"                      ,	2,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	64,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	8,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"XSDEF"                       ,	12,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"LATE_COL"                    ,	16,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"PTP_LOST"                    ,	20,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	64,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	65,	"RAZ",	1,	1,	0,	0},
+	{"UNDFLW"                      ,	2,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	65,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	8,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"XSDEF"                       ,	12,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"LATE_COL"                    ,	16,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"PTP_LOST"                    ,	20,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	65,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	66,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	66,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	67,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	67,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	68,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	4,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	68,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	8,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	68,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	69,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	69,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	70,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	70,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	1,	71,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKRST"                      ,	1,	1,	71,	"R/W",	0,	0,	1ull,	0ull},
+	{"ENABLE"                      ,	2,	1,	71,	"R/W",	0,	0,	1ull,	1ull},
+	{"COMP"                        ,	3,	1,	71,	"R/W",	0,	0,	0ull,	1ull},
+	{"DLLRST"                      ,	4,	1,	71,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	71,	"RAZ",	1,	1,	0,	0},
+	{"CLKTX_SET"                   ,	8,	5,	71,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_14"              ,	13,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CLKTX_BYP"                   ,	15,	1,	71,	"R/W",	0,	1,	1ull,	0},
+	{"CLKRX_SET"                   ,	16,	5,	71,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_22"              ,	21,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CLKRX_BYP"                   ,	23,	1,	71,	"R/W",	0,	1,	0ull,	0},
+	{"CLK_SET"                     ,	24,	5,	71,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_31"              ,	29,	3,	71,	"RAZ",	1,	1,	0,	0},
+	{"DRV_NCTL"                    ,	32,	6,	71,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_38_39"              ,	38,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"DRV_PCTL"                    ,	40,	6,	71,	"R/W",	0,	1,	19ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CMP_NCTL"                    ,	48,	6,	71,	"RO",	1,	1,	0,	0},
+	{"RESERVED_54_55"              ,	54,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CMP_PCTL"                    ,	56,	6,	71,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	71,	"RAZ",	1,	1,	0,	0},
+	{"DRV_BYP"                     ,	63,	1,	71,	"R/W",	0,	0,	1ull,	0ull},
+	{"ACK"                         ,	0,	1,	72,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	72,	"RAZ",	1,	1,	0,	0},
+	{"ACK"                         ,	0,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	73,	"RAZ",	1,	1,	0,	0},
+	{"ACK"                         ,	0,	1,	74,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	74,	"RAZ",	1,	1,	0,	0},
+	{"ACK"                         ,	0,	1,	75,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	75,	"RAZ",	1,	1,	0,	0},
+	{"GPIO"                        ,	0,	16,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	76,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	77,	"RAZ",	1,	0,	0,	0ull},
+	{"GPIO"                        ,	0,	16,	78,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	78,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	79,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	79,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	79,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	79,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	79,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	79,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	79,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	79,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	79,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTR"                    ,	0,	4,	80,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	80,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	80,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	80,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	80,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	80,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	80,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	80,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	80,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTR"                    ,	0,	4,	81,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	81,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	81,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	81,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	81,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	81,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	81,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	81,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	81,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	82,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	82,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	0,	4,	83,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	83,	"RAZ",	1,	0,	0,	0ull},
+	{"MBOX"                        ,	0,	4,	84,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	84,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	0,	4,	85,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	85,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	86,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	86,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	87,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	87,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	88,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	88,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	88,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	88,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	88,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	88,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	88,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	88,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	88,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	0,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	89,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	89,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	89,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	89,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	89,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	89,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	89,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	89,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	0,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	90,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	90,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	90,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	90,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	90,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	90,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	90,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	90,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	90,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	91,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	91,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	91,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	91,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	91,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	91,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	91,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	91,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	91,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	91,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	91,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	91,	"RAZ",	1,	1,	0,	0},
+	{"AGX"                         ,	0,	5,	92,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	92,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	92,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	92,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	92,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	92,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	92,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	92,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	92,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	92,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	92,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	92,	"RAZ",	1,	1,	0,	0},
+	{"AGX"                         ,	0,	5,	93,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	93,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	93,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	93,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	93,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	93,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	93,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	93,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	93,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	93,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	93,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	93,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	94,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	94,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	94,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	94,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	94,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	94,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	94,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	94,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	94,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	94,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	95,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	95,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	95,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	95,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	95,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	95,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	95,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	95,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	95,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	95,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	95,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	96,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	96,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	96,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	96,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	96,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	96,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	96,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	96,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	96,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	96,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	96,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	97,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	32,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	98,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	32,	99,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	99,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	102,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	103,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	103,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	104,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	104,	"RAZ",	1,	0,	0,	0ull},
+	{"GPIO"                        ,	0,	16,	105,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	105,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	106,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	106,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	106,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	106,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	106,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	106,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	106,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	106,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	106,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTR"                    ,	0,	4,	107,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	107,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	107,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	107,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	107,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	107,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	107,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	107,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	107,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTR"                    ,	0,	4,	108,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	108,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	108,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	108,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	108,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	108,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	108,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	108,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	108,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	109,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	109,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	0,	4,	110,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	110,	"RAZ",	1,	0,	0,	0ull},
+	{"MBOX"                        ,	0,	4,	111,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	111,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	0,	4,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	112,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	113,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	114,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	114,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	115,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	115,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	115,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	115,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	115,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	115,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	115,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	115,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	0,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	116,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	116,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	116,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	116,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	116,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	116,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	116,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	116,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	0,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	117,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	117,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	117,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	117,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	117,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	117,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	117,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	117,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	117,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	118,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	118,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	118,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	118,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	118,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	118,	"RAZ",	1,	1,	0,	0},
+	{"AGX"                         ,	0,	5,	119,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	119,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	119,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	119,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	119,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	119,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	119,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	119,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	119,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	119,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	119,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	119,	"RAZ",	1,	1,	0,	0},
+	{"AGX"                         ,	0,	5,	120,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	120,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	120,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	120,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	120,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	120,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	120,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	120,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	120,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	120,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	120,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	120,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	121,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	121,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	121,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	121,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	121,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	121,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	121,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	121,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	121,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	121,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	122,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	122,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	122,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	122,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	122,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	122,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	122,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	122,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	122,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	122,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	122,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	123,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	123,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	123,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	123,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	123,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	123,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	123,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	123,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	123,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	123,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	123,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	124,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	32,	125,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	125,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	32,	126,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	126,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	129,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	130,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	131,	"RAZ",	1,	0,	0,	0ull},
+	{"GPIO"                        ,	0,	16,	132,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	132,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	133,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	133,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	133,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	133,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	133,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	133,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	133,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	133,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	133,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTR"                    ,	0,	4,	134,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	134,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	134,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	134,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	134,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	134,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	134,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	134,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	134,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTR"                    ,	0,	4,	135,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	135,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	135,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	135,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	135,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	135,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	135,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	135,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	135,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	136,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	0,	4,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	137,	"RAZ",	1,	0,	0,	0ull},
+	{"MBOX"                        ,	0,	4,	138,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	138,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	0,	4,	139,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	139,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	140,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	140,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	141,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	141,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	142,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	142,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	142,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	142,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	142,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	142,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	142,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	142,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	0,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	143,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	143,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	143,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	143,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	143,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	143,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	143,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	143,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	143,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	0,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	144,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	144,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	144,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	144,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	144,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	144,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	144,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	144,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	144,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	145,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	145,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	145,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	145,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	145,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	145,	"RAZ",	1,	1,	0,	0},
+	{"AGX"                         ,	0,	5,	146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	146,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	146,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	146,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	146,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	146,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	146,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	146,	"RAZ",	1,	1,	0,	0},
+	{"AGX"                         ,	0,	5,	147,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	147,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	147,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	147,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	147,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	147,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	147,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	147,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	147,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	147,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	147,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	147,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	148,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	148,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	148,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	148,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	148,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	148,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	148,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	148,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	148,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	148,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	149,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	149,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	149,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	149,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	149,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	149,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	149,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	149,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	149,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	149,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	150,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	150,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	150,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	150,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	150,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	150,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	150,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	150,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	150,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	150,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	150,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	151,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	32,	152,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	152,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	32,	153,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	153,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	154,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	155,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	156,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	157,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	157,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	158,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	158,	"RAZ",	1,	0,	0,	0ull},
+	{"GPIO"                        ,	0,	16,	159,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	159,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	160,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	160,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	160,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	160,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTR"                    ,	0,	4,	161,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	161,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	161,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	161,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	161,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	161,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	161,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	161,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	161,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTR"                    ,	0,	4,	162,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	162,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	162,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	162,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	162,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	162,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	162,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	162,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	162,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	163,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	163,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	0,	4,	164,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	164,	"RAZ",	1,	0,	0,	0ull},
+	{"MBOX"                        ,	0,	4,	165,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	165,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	0,	4,	166,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	166,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	167,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	167,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	168,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	168,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	169,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	169,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	169,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	169,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	169,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	169,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	169,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	169,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	0,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	170,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	170,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	170,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	170,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	170,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	170,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	170,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	170,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	170,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	0,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	171,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	171,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	171,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	171,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	171,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	171,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	171,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	171,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	171,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	172,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	172,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	172,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	172,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	172,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	172,	"RAZ",	1,	1,	0,	0},
+	{"AGX"                         ,	0,	5,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	173,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	173,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	173,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	173,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	173,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	173,	"RAZ",	1,	1,	0,	0},
+	{"AGX"                         ,	0,	5,	174,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	174,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	174,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	174,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	174,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	174,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	174,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	174,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	174,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	174,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	174,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	174,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	175,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	175,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	175,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	175,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	175,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	175,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	175,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	175,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	175,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	175,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	176,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	176,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	176,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	176,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	176,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	176,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	176,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	176,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	176,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	176,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	177,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	177,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	177,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	177,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	177,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	177,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	177,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	177,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	177,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	177,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	177,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	178,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	178,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	32,	179,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	179,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	32,	180,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	180,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	183,	"R/W1",	0,	0,	0ull,	0ull},
+	{"READY"                       ,	0,	1,	184,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	184,	"RAZ",	1,	1,	0,	0},
+	{"ECC_ENA"                     ,	0,	1,	185,	"R/W",	0,	0,	1ull,	1ull},
+	{"FLIP_SYND"                   ,	1,	2,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	185,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	186,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	186,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	186,	"RAZ",	1,	1,	0,	0},
+	{"SYNDROM"                     ,	4,	9,	186,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	186,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	16,	7,	186,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	186,	"RAZ",	1,	1,	0,	0},
+	{"CTL"                         ,	0,	3,	187,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	187,	"RAZ",	1,	1,	0,	0},
+	{"MSI_RCV"                     ,	0,	1,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	188,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	189,	"RAZ",	1,	1,	0,	0},
+	{"IP_NUM"                      ,	4,	2,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	189,	"RAZ",	1,	1,	0,	0},
+	{"PP_NUM"                      ,	8,	5,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	189,	"RAZ",	1,	1,	0,	0},
+	{"MSI_NUM"                     ,	0,	8,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	190,	"RAZ",	1,	1,	0,	0},
+	{"NEWINT"                      ,	16,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	190,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	20,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	190,	"RAZ",	1,	1,	0,	0},
+	{"MSI_NUM"                     ,	0,	8,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	191,	"RAZ",	1,	1,	0,	0},
+	{"NEWINT"                      ,	16,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	191,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	20,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	191,	"RAZ",	1,	1,	0,	0},
+	{"MSI_NUM"                     ,	0,	8,	192,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	192,	"RAZ",	1,	1,	0,	0},
+	{"NEWINT"                      ,	16,	1,	192,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	192,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	20,	1,	192,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	192,	"RAZ",	1,	1,	0,	0},
+	{"GPIO"                        ,	0,	16,	193,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	193,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	194,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	194,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	194,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	194,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	195,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	195,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	196,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	196,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	196,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	196,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	196,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	196,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	196,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	196,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	196,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	196,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	196,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	197,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	197,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	197,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	197,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	197,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	197,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	197,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	197,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	198,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	198,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	198,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	198,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	198,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	198,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	198,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	198,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	198,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	198,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	199,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	200,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	201,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	201,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	202,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	202,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	202,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	202,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	202,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	202,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	202,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	202,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	202,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	203,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	203,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	204,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	204,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	204,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	204,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	204,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	204,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	204,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	204,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	205,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	205,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	205,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	205,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	205,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	205,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	205,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	205,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	206,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	206,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	206,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	206,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	206,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	206,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	206,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	206,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	206,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	206,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	207,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	207,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	209,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	209,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	210,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	210,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	210,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	210,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	211,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	211,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	212,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	212,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	212,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	212,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	212,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	212,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	212,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	212,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	212,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	212,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	212,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	213,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	213,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	213,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	213,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	213,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	213,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	213,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	213,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	213,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	213,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	213,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	213,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	214,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	214,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	214,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	214,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	214,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	214,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	214,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	214,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	214,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	214,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	215,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	215,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	216,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	217,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	217,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	218,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	218,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	218,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	218,	"RAZ",	1,	1,	0,	0},
+	{"LMC"                         ,	0,	4,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	219,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	220,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	220,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	220,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	220,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	220,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	220,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	220,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	220,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	220,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	220,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	220,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	221,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	221,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	221,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	221,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	221,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	221,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	221,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	221,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	221,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	221,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	221,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	221,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	222,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	222,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	222,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	222,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	222,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	222,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	222,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	222,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	222,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	222,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	223,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	223,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	224,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	225,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	225,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	226,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	226,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	226,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	226,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	227,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	0,	4,	228,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	228,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	229,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	229,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	229,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	229,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	229,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	229,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	229,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	229,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	230,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	230,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	230,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	230,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	230,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	230,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	230,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	230,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	230,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	230,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	230,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	230,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	231,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	231,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	231,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	231,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	231,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	231,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	231,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	231,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	231,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	231,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	232,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	232,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	233,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	234,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	235,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	235,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	235,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	235,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	236,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	0,	4,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	237,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	238,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	238,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	238,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	238,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	238,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	238,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	238,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	238,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	239,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	239,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	239,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	239,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	239,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	239,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	239,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	239,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	239,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	239,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	239,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	239,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	240,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	240,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	240,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	240,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	240,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	240,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	240,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	240,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	240,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	240,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	241,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	242,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	243,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	243,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	244,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	244,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	244,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	244,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	245,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	245,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	0,	4,	246,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	246,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	247,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	247,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	247,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	247,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	247,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	247,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	247,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	247,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	248,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	248,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	248,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	248,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	248,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	248,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	249,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	249,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	249,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	249,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	249,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	249,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	249,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	249,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	249,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	249,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	250,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	250,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	251,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	0,	16,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	252,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCI_INTR"                    ,	0,	4,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	253,	"RAZ",	1,	1,	0,	0},
+	{"PCI_MSI"                     ,	8,	4,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIRED"                      ,	12,	1,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	253,	"RAZ",	1,	1,	0,	0},
+	{"PCI_INTA"                    ,	16,	2,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	253,	"RAZ",	1,	1,	0,	0},
+	{"PEM"                         ,	32,	2,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	253,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	254,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	254,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	0,	4,	255,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	255,	"RAZ",	1,	1,	0,	0},
+	{"IPDPPTHR"                    ,	0,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"SSOIQ"                       ,	1,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	2,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	256,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	8,	4,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	256,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	16,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	17,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	18,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	256,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	32,	2,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	256,	"RAZ",	1,	1,	0,	0},
+	{"UART"                        ,	36,	2,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	256,	"RAZ",	1,	1,	0,	0},
+	{"USB_UCTL"                    ,	40,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_43"              ,	41,	3,	256,	"RAZ",	1,	1,	0,	0},
+	{"USB_HCI"                     ,	44,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	256,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	48,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_62"              ,	49,	14,	256,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX"                         ,	0,	5,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	257,	"RAZ",	1,	1,	0,	0},
+	{"GMX_DRP"                     ,	8,	5,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	257,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	32,	1,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_39"              ,	33,	7,	257,	"RAZ",	1,	1,	0,	0},
+	{"MII"                         ,	40,	1,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	257,	"RAZ",	1,	1,	0,	0},
+	{"ILK"                         ,	48,	1,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	257,	"RAZ",	1,	1,	0,	0},
+	{"ILK_DRP"                     ,	52,	2,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	257,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	0,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	258,	"RAZ",	1,	1,	0,	0},
+	{"FPA"                         ,	4,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	5,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	6,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	7,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	258,	"RAZ",	1,	1,	0,	0},
+	{"SSO"                         ,	16,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	258,	"RAZ",	1,	1,	0,	0},
+	{"ZIP"                         ,	24,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	258,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	28,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	29,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	30,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	258,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	32,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	33,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	258,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	36,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	258,	"RAZ",	1,	1,	0,	0},
+	{"DFA"                         ,	40,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_47"              ,	41,	7,	258,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	48,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_51"              ,	49,	3,	258,	"RAZ",	1,	1,	0,	0},
+	{"TRACE"                       ,	52,	4,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	258,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	32,	259,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	259,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	64,	260,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	1,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	1,	1,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	2,	1,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	3,	1,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"IO"                          ,	4,	1,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM"                         ,	5,	1,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT"                         ,	6,	1,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	7,	1,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_59"               ,	8,	52,	261,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	60,	4,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	1,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	1,	1,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	2,	1,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	3,	1,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"IO"                          ,	4,	1,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM"                         ,	5,	1,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT"                         ,	6,	1,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	7,	1,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_59"               ,	8,	52,	262,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	60,	4,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	1,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	1,	1,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	2,	1,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	3,	1,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"IO"                          ,	4,	1,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM"                         ,	5,	1,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT"                         ,	6,	1,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	7,	1,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_59"               ,	8,	52,	263,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	60,	4,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	1,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	2,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	3,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"IO"                          ,	4,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM"                         ,	5,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT"                         ,	6,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	7,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_59"               ,	8,	52,	264,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	60,	4,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	7,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	265,	"RAZ",	1,	1,	0,	0},
+	{"DINT"                        ,	0,	32,	266,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	266,	"RAZ",	1,	1,	0,	0},
+	{"FUSE"                        ,	0,	32,	267,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	267,	"RAZ",	1,	1,	0,	0},
+	{"GSTOP"                       ,	0,	1,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	268,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	0,	5,	269,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	269,	"RAZ",	1,	1,	0,	0},
+	{"IRQ"                         ,	8,	2,	269,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	269,	"RAZ",	1,	1,	0,	0},
+	{"SEL"                         ,	16,	3,	269,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_19_63"              ,	19,	45,	269,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	270,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	270,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	271,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	271,	"RAZ",	1,	1,	0,	0},
+	{"NMI"                         ,	0,	32,	272,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	272,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	2,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	273,	"RAZ",	1,	1,	0,	0},
+	{"PP_BIST"                     ,	0,	32,	274,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	274,	"RAZ",	1,	1,	0,	0},
+	{"PPDBG"                       ,	0,	32,	275,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	275,	"RAZ",	1,	1,	0,	0},
+	{"POKE"                        ,	0,	64,	276,	"R/W",	1,	1,	0,	0},
+	{"RST0"                        ,	0,	1,	277,	"R/W",	1,	1,	0,	0},
+	{"RST"                         ,	1,	31,	277,	"R/W",	0,	0,	2147483647ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	277,	"RAZ",	1,	1,	0,	0},
+	{"LANE_EN"                     ,	0,	4,	278,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	278,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	278,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	278,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	278,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	278,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	278,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	278,	"RAZ",	1,	1,	0,	0},
+	{"LANE_EN"                     ,	0,	4,	279,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	279,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	279,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	279,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	279,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	279,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	279,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_39"              ,	32,	8,	279,	"RAZ",	1,	1,	0,	0},
+	{"G2MARGIN"                    ,	40,	5,	279,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	279,	"RAZ",	1,	1,	0,	0},
+	{"G2DEEMPH"                    ,	48,	5,	279,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_53_62"              ,	53,	10,	279,	"RAZ",	1,	1,	0,	0},
+	{"G2BYPASS"                    ,	63,	1,	279,	"R/W",	0,	1,	0ull,	0},
+	{"LANE_EN"                     ,	0,	4,	280,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	280,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	280,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	280,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	280,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	280,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	280,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_39"              ,	32,	8,	280,	"RAZ",	1,	1,	0,	0},
+	{"G2MARGIN"                    ,	40,	5,	280,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	280,	"RAZ",	1,	1,	0,	0},
+	{"G2DEEMPH"                    ,	48,	5,	280,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_53_62"              ,	53,	10,	280,	"RAZ",	1,	1,	0,	0},
+	{"G2BYPASS"                    ,	63,	1,	280,	"R/W",	0,	1,	0ull,	0},
+	{"LANE_EN"                     ,	0,	4,	281,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	281,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	281,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	281,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	281,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	281,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	281,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_39"              ,	32,	8,	281,	"RAZ",	1,	1,	0,	0},
+	{"G2MARGIN"                    ,	40,	5,	281,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	281,	"RAZ",	1,	1,	0,	0},
+	{"G2DEEMPH"                    ,	48,	5,	281,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_53_62"              ,	53,	10,	281,	"RAZ",	1,	1,	0,	0},
+	{"G2BYPASS"                    ,	63,	1,	281,	"R/W",	0,	1,	0ull,	0},
+	{"LANE_EN"                     ,	0,	4,	282,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	282,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	282,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	282,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	282,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	282,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	282,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_39"              ,	32,	8,	282,	"RAZ",	1,	1,	0,	0},
+	{"G2MARGIN"                    ,	40,	5,	282,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	282,	"RAZ",	1,	1,	0,	0},
+	{"G2DEEMPH"                    ,	48,	5,	282,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_53_62"              ,	53,	10,	282,	"RAZ",	1,	1,	0,	0},
+	{"G2BYPASS"                    ,	63,	1,	282,	"R/W",	0,	1,	0ull,	0},
+	{"BYPASS"                      ,	0,	4,	283,	"R/W",	0,	1,	0ull,	0},
+	{"MUX_SEL"                     ,	4,	3,	283,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	283,	"RAZ",	1,	1,	0,	0},
+	{"CLK_DIV"                     ,	8,	3,	283,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_15"              ,	11,	5,	283,	"RAZ",	1,	1,	0,	0},
+	{"BYPASS_EXT"                  ,	16,	1,	283,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	283,	"RAZ",	1,	1,	0,	0},
+	{"SHFT_REG"                    ,	0,	32,	284,	"R/W",	0,	1,	0ull,	0},
+	{"SHFT_CNT"                    ,	32,	5,	284,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_37_39"              ,	37,	3,	284,	"RAZ",	1,	1,	0,	0},
+	{"SELECT"                      ,	40,	5,	284,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_60"              ,	45,	16,	284,	"RAZ",	1,	1,	0,	0},
+	{"UPDATE"                      ,	61,	1,	284,	"R/W",	0,	1,	0ull,	0},
+	{"SHIFT"                       ,	62,	1,	284,	"R/W",	0,	1,	0ull,	0},
+	{"CAPTURE"                     ,	63,	1,	284,	"R/W",	0,	1,	0ull,	0},
+	{"SOFT_BIST"                   ,	0,	1,	285,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	285,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	286,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	286,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	287,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	287,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST"                    ,	0,	1,	288,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	288,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	36,	289,	"R/W",	0,	0,	0ull,	0ull},
+	{"ONE_SHOT"                    ,	36,	1,	289,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	289,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	2,	2,	290,	"RO",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	4,	16,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	20,	24,	290,	"RO",	0,	0,	0ull,	0ull},
+	{"DSTOP"                       ,	44,	1,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSTOPEN"                     ,	45,	1,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	290,	"RAZ",	1,	1,	0,	0},
+	{"PDB"                         ,	0,	3,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	291,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RDF"                         ,	4,	3,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	291,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTX"                         ,	8,	2,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"DTX1"                        ,	10,	2,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"DTX2"                        ,	12,	2,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	291,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STX"                         ,	16,	2,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"STX1"                        ,	18,	2,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"STX2"                        ,	20,	2,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	291,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GFB"                         ,	24,	3,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	291,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MRP"                         ,	28,	2,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_63"              ,	30,	34,	291,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GFU"                         ,	0,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"GIB"                         ,	1,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"GIF"                         ,	2,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"NCD"                         ,	3,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"GUTP"                        ,	4,	3,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	292,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GUTV"                        ,	8,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"CRQ"                         ,	9,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"RAM1"                        ,	10,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"RAM2"                        ,	11,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"RAM3"                        ,	12,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"DC1RAM1"                     ,	13,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"DC1RAM2"                     ,	14,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"DC1RAM3"                     ,	15,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"DC2RAM1"                     ,	16,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"DC2RAM2"                     ,	17,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"DC2RAM3"                     ,	18,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"DLC0RAM"                     ,	19,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"DLC1RAM"                     ,	20,	1,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	292,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTECLKDIS"                   ,	0,	1,	293,	"R/W",	0,	0,	1ull,	0ull},
+	{"CLDTECRIP"                   ,	1,	3,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLMSKCRIP"                   ,	4,	4,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"REPL_ENA"                    ,	8,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLCSTART_BIST"               ,	9,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLCCLEAR_BIST"               ,	10,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	293,	"RAZ",	1,	1,	0,	0},
+	{"IMODE"                       ,	0,	1,	294,	"R/W",	0,	0,	1ull,	1ull},
+	{"QMODE"                       ,	1,	1,	294,	"R/W",	0,	0,	1ull,	1ull},
+	{"PMODE"                       ,	2,	1,	294,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_4"                ,	3,	2,	294,	"RAZ",	1,	1,	0,	0},
+	{"SBDLCK"                      ,	5,	1,	294,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBDNUM"                      ,	6,	6,	294,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	294,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	20,	295,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	295,	"RAZ",	1,	1,	0,	0},
+	{"SBD0"                        ,	0,	64,	296,	"RO",	1,	1,	0,	0},
+	{"SBD1"                        ,	0,	64,	297,	"RO",	1,	1,	0,	0},
+	{"SBD2"                        ,	0,	64,	298,	"RO",	1,	1,	0,	0},
+	{"SBD3"                        ,	0,	64,	299,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	9,	300,	"R/W",	0,	1,	3ull,	0},
+	{"POOL"                        ,	9,	3,	300,	"R/W",	0,	1,	0ull,	0},
+	{"DWBCNT"                      ,	12,	8,	300,	"R/W",	0,	1,	1ull,	0},
+	{"MSEGBASE"                    ,	20,	6,	300,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	300,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	301,	"RAZ",	1,	1,	0,	0},
+	{"RDPTR"                       ,	5,	35,	301,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	301,	"RAZ",	1,	1,	0,	0},
+	{"RAM1FADR"                    ,	0,	14,	302,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	302,	"RAZ",	1,	1,	0,	0},
+	{"RAM2FADR"                    ,	16,	9,	302,	"RO",	1,	1,	0,	0},
+	{"RESERVED_25_31"              ,	25,	7,	302,	"RAZ",	1,	1,	0,	0},
+	{"RAM3FADR"                    ,	32,	12,	302,	"RO",	1,	1,	0,	0},
+	{"RESERVED_44_63"              ,	44,	20,	302,	"RAZ",	1,	1,	0,	0},
+	{"DBLOVF"                      ,	0,	1,	303,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC0PERR"                     ,	1,	3,	303,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC1PERR"                     ,	4,	3,	303,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC2PERR"                     ,	7,	3,	303,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_12"              ,	10,	3,	303,	"RAZ",	1,	1,	0,	0},
+	{"DLC0_OVFERR"                 ,	13,	1,	303,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DLC1_OVFERR"                 ,	14,	1,	303,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	303,	"RAZ",	1,	1,	0,	0},
+	{"CNDRD"                       ,	16,	1,	303,	"RO",	0,	0,	0ull,	0ull},
+	{"DFANXM"                      ,	17,	1,	303,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REPLERR"                     ,	18,	1,	303,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	303,	"RAZ",	1,	1,	0,	0},
+	{"DBLINA"                      ,	0,	1,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC0PENA"                     ,	1,	3,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC1PENA"                     ,	4,	3,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC2PENA"                     ,	7,	3,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_12"              ,	10,	3,	304,	"RAZ",	1,	1,	0,	0},
+	{"DLC0_OVFENA"                 ,	13,	1,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLC1_OVFENA"                 ,	14,	1,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_16"              ,	15,	2,	304,	"RAZ",	1,	1,	0,	0},
+	{"DFANXMENA"                   ,	17,	1,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"REPLERRENA"                  ,	18,	1,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	304,	"RAZ",	1,	1,	0,	0},
+	{"HIDAT"                       ,	0,	64,	305,	"R/W",	1,	1,	0,	0},
+	{"PFCNT0"                      ,	0,	64,	306,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	307,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	307,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	307,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	307,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	307,	"RAZ",	1,	1,	0,	0},
+	{"PFCNT1"                      ,	0,	64,	308,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	309,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	309,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	309,	"RAZ",	1,	1,	0,	0},
+	{"PFCNT2"                      ,	0,	64,	310,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	311,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	311,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	311,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	311,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	311,	"RAZ",	1,	1,	0,	0},
+	{"PFCNT3"                      ,	0,	64,	312,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	313,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	313,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	313,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	313,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	313,	"RAZ",	1,	1,	0,	0},
+	{"CNT0ENA"                     ,	0,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1ENA"                     ,	1,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2ENA"                     ,	2,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3ENA"                     ,	3,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0WCLR"                    ,	4,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1WCLR"                    ,	5,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2WCLR"                    ,	6,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3WCLR"                    ,	7,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0RCLR"                    ,	8,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1RCLR"                    ,	9,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2RCLR"                    ,	10,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3RCLR"                    ,	11,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"SNODE"                       ,	12,	3,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENODE"                       ,	15,	3,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"EDNODE"                      ,	18,	2,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMODE"                       ,	20,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGID"                        ,	21,	8,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	314,	"RAZ",	1,	1,	0,	0},
+	{"BIST"                        ,	0,	45,	315,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_63"              ,	45,	19,	315,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	316,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLK"                         ,	1,	1,	316,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	316,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	317,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	317,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	317,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	318,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	318,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	6,	319,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	319,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_6"                ,	0,	7,	320,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	7,	33,	320,	"R/W",	0,	1,	0ull,	0},
+	{"IDLE"                        ,	40,	1,	320,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_41_47"              ,	41,	7,	320,	"RAZ",	1,	1,	0,	0},
+	{"CSIZE"                       ,	48,	14,	320,	"R/W",	0,	1,	64ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	320,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	3,	321,	"R/W",	0,	0,	6ull,	6ull},
+	{"RESERVED_3_63"               ,	3,	61,	321,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	40,	322,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	322,	"RAZ",	1,	1,	0,	0},
+	{"STATE"                       ,	0,	64,	323,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	0,	64,	324,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_13"               ,	0,	14,	325,	"RAZ",	1,	1,	0,	0},
+	{"O_MODE"                      ,	14,	1,	325,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ES"                        ,	15,	2,	325,	"R/W",	0,	1,	0ull,	0},
+	{"O_NS"                        ,	17,	1,	325,	"R/W",	0,	1,	0ull,	0},
+	{"O_RO"                        ,	18,	1,	325,	"R/W",	0,	1,	0ull,	0},
+	{"O_ADD1"                      ,	19,	1,	325,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA_QUE"                     ,	20,	3,	325,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_ICHK"                    ,	23,	9,	325,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_DENB"                    ,	32,	1,	325,	"R/W",	0,	0,	0ull,	1ull},
+	{"B0_LEND"                     ,	33,	1,	325,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_47"              ,	34,	14,	325,	"RAZ",	1,	1,	0,	0},
+	{"DMA_ENB"                     ,	48,	6,	325,	"R/W",	0,	0,	0ull,	63ull},
+	{"RESERVED_54_55"              ,	54,	2,	325,	"RAZ",	1,	1,	0,	0},
+	{"PKT_EN"                      ,	56,	1,	325,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_HP"                      ,	57,	1,	325,	"RO",	0,	0,	0ull,	0ull},
+	{"COMMIT_MODE"                 ,	58,	1,	325,	"R/W",	0,	0,	0ull,	1ull},
+	{"FFP_DIS"                     ,	59,	1,	325,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_EN1"                     ,	60,	1,	325,	"R/W",	0,	1,	0ull,	0},
+	{"DICI_MODE"                   ,	61,	1,	325,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	325,	"RAZ",	1,	1,	0,	0},
+	{"QEN"                         ,	0,	8,	326,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	326,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	327,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	327,	"RAZ",	1,	1,	0,	0},
+	{"BLKS"                        ,	0,	4,	328,	"R/W",	0,	1,	2ull,	0},
+	{"BASE"                        ,	4,	5,	328,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_31"               ,	9,	23,	328,	"RAZ",	1,	1,	0,	0},
+	{"COMPBLKS"                    ,	32,	5,	328,	"RO",	1,	1,	0,	0},
+	{"RESERVED_37_63"              ,	37,	27,	328,	"RAZ",	1,	1,	0,	0},
+	{"RSL"                         ,	0,	1,	329,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NCB"                         ,	1,	1,	329,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	329,	"RAZ",	1,	1,	0,	0},
+	{"FFP"                         ,	4,	4,	329,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	329,	"RAZ",	1,	1,	0,	0},
+	{"NDERR"                       ,	0,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFOVR"                       ,	1,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMADBO"                      ,	8,	8,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADADR"                  ,	16,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADLEN"                  ,	17,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_OVRFLW"                  ,	18,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_UNDFLW"                  ,	19,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_ANULL"                   ,	20,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_INULL"                   ,	21,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADFIL"                  ,	22,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	330,	"R/W",	1,	1,	0,	0},
+	{"SPRT0_RST"                   ,	24,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_RST"                   ,	25,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_63"              ,	26,	38,	330,	"R/W",	1,	1,	0,	0},
+	{"NDERR"                       ,	0,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFOVR"                       ,	1,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	331,	"RAZ",	1,	1,	0,	0},
+	{"DMADBO"                      ,	8,	8,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADADR"                  ,	16,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADLEN"                  ,	17,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_OVRFLW"                  ,	18,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_UNDFLW"                  ,	19,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_ANULL"                   ,	20,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_INULL"                   ,	21,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADFIL"                  ,	22,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	331,	"RAZ",	1,	1,	0,	0},
+	{"SPRT0_RST"                   ,	24,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT1_RST"                   ,	25,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_63"              ,	26,	38,	331,	"RAZ",	1,	1,	0,	0},
+	{"MOLR"                        ,	0,	6,	332,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	332,	"RAZ",	1,	1,	0,	0},
+	{"SINFO"                       ,	0,	6,	333,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	333,	"RAZ",	1,	1,	0,	0},
+	{"IINFO"                       ,	8,	6,	333,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	333,	"RAZ",	1,	1,	0,	0},
+	{"PKTERR"                      ,	0,	1,	334,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	334,	"RAZ",	1,	1,	0,	0},
+	{"QERR"                        ,	0,	8,	335,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	335,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	336,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	336,	"RAZ",	1,	1,	0,	0},
+	{"QERR"                        ,	0,	8,	337,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	337,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	338,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	338,	"RAZ",	1,	1,	0,	0},
+	{"EN_RSP"                      ,	0,	8,	339,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	339,	"RAZ",	1,	1,	0,	0},
+	{"EN_RST"                      ,	16,	8,	339,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	339,	"RAZ",	1,	1,	0,	0},
+	{"QEN"                         ,	0,	8,	340,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	340,	"RAZ",	1,	1,	0,	0},
+	{"MRRS"                        ,	0,	2,	341,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	341,	"RAZ",	1,	1,	0,	0},
+	{"MRRS_LIM"                    ,	3,	1,	341,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPS"                         ,	4,	1,	341,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	341,	"RAZ",	1,	1,	0,	0},
+	{"MPS_LIM"                     ,	7,	1,	341,	"R/W",	0,	0,	0ull,	0ull},
+	{"MOLR"                        ,	8,	6,	341,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_14_15"              ,	14,	2,	341,	"RAZ",	1,	1,	0,	0},
+	{"RD_MODE"                     ,	16,	1,	341,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	341,	"RAZ",	1,	1,	0,	0},
+	{"QLM_CFG"                     ,	20,	1,	341,	"RO",	1,	1,	0,	0},
+	{"RESERVED_21_23"              ,	21,	3,	341,	"RAZ",	1,	1,	0,	0},
+	{"HALT"                        ,	24,	1,	341,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	341,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	342,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	61,	342,	"RO",	0,	1,	0ull,	0},
+	{"REQQ"                        ,	0,	3,	343,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	343,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	4,	1,	343,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	343,	"RAZ",	1,	1,	0,	0},
+	{"LOCK"                        ,	8,	1,	343,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	343,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	33,	344,	"RO",	0,	1,	0ull,	0},
+	{"POOL"                        ,	33,	5,	344,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	344,	"RAZ",	1,	1,	0,	0},
+	{"FDR"                         ,	0,	1,	345,	"RO",	0,	0,	0ull,	0ull},
+	{"FFR"                         ,	1,	1,	345,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF1"                        ,	2,	1,	345,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF0"                        ,	3,	1,	345,	"RO",	0,	0,	0ull,	0ull},
+	{"FRD"                         ,	4,	1,	345,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	345,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	346,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	346,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	14,	1,	346,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_STT"                     ,	15,	1,	346,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_LDT"                     ,	16,	1,	346,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	346,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_OFF"                     ,	18,	1,	346,	"R/W",	0,	0,	0ull,	0ull},
+	{"RET_OFF"                     ,	19,	1,	346,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE_EN"                     ,	20,	1,	346,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	346,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	11,	347,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	11,	11,	347,	"R/W",	0,	0,	164ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	347,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	11,	348,	"R/W",	0,	0,	224ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	348,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	12,	349,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	12,	12,	349,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	349,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	12,	350,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	350,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	11,	351,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	11,	11,	351,	"R/W",	0,	0,	164ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	351,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	12,	352,	"R/W",	0,	0,	224ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	352,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL0TH"                     ,	28,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL1TH"                     ,	29,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL2TH"                     ,	30,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL3TH"                     ,	31,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL4TH"                     ,	32,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL5TH"                     ,	33,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL6TH"                     ,	34,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL7TH"                     ,	35,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE0"                       ,	36,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE1"                       ,	37,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE2"                       ,	38,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE3"                       ,	39,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE4"                       ,	40,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE5"                       ,	41,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE6"                       ,	42,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE7"                       ,	43,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE8"                       ,	44,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q8_UND"                      ,	45,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q8_COFF"                     ,	46,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q8_PERR"                     ,	47,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL8TH"                     ,	48,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"PADDR_E"                     ,	49,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_63"              ,	50,	14,	353,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL0TH"                     ,	28,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL1TH"                     ,	29,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL2TH"                     ,	30,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL3TH"                     ,	31,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL4TH"                     ,	32,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL5TH"                     ,	33,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL6TH"                     ,	34,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL7TH"                     ,	35,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE0"                       ,	36,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE1"                       ,	37,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE2"                       ,	38,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE3"                       ,	39,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE4"                       ,	40,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE5"                       ,	41,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE6"                       ,	42,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE7"                       ,	43,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE8"                       ,	44,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q8_UND"                      ,	45,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q8_COFF"                     ,	46,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q8_PERR"                     ,	47,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL8TH"                     ,	48,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PADDR_E"                     ,	49,	1,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_63"              ,	50,	14,	354,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	32,	355,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	355,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	33,	356,	"R/W",	0,	1,	8589934591ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	356,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	33,	357,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	357,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	32,	358,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	358,	"RAZ",	1,	1,	0,	0},
+	{"QUE_SIZ"                     ,	0,	32,	359,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	359,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	360,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	360,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	361,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	361,	"RAZ",	1,	1,	0,	0},
+	{"ACT_INDX"                    ,	0,	26,	362,	"RO",	0,	1,	0ull,	0},
+	{"ACT_QUE"                     ,	26,	3,	362,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	362,	"RO",	0,	0,	0ull,	7ull},
+	{"EXP_INDX"                    ,	0,	26,	363,	"RO",	0,	1,	0ull,	0},
+	{"EXP_QUE"                     ,	26,	3,	363,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	363,	"RO",	0,	0,	0ull,	7ull},
+	{"THRESH"                      ,	0,	32,	364,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	364,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	365,	"RAZ",	1,	1,	0,	0},
+	{"OUT_OVR"                     ,	2,	4,	365,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_21"               ,	6,	16,	365,	"RAZ",	1,	1,	0,	0},
+	{"LOSTSTAT"                    ,	22,	4,	365,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	365,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INB_NXA"                     ,	27,	4,	365,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	365,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	25,	366,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	366,	"RAZ",	1,	1,	0,	0},
+	{"BPID"                        ,	0,	6,	367,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	367,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	8,	1,	367,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_15"               ,	9,	7,	367,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	16,	1,	367,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	367,	"RAZ",	1,	1,	0,	0},
+	{"MSK_AND"                     ,	0,	16,	368,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	368,	"RAZ",	1,	1,	0,	0},
+	{"MSK_OR"                      ,	32,	16,	368,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	368,	"RAZ",	1,	1,	0,	0},
+	{"CLK_EN"                      ,	0,	1,	369,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	369,	"RAZ",	1,	1,	0,	0},
+	{"DIS"                         ,	0,	16,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	370,	"RAZ",	1,	1,	0,	0},
+	{"MSK"                         ,	0,	16,	371,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	371,	"RAZ",	1,	1,	0,	0},
+	{"LOGL_EN"                     ,	0,	16,	372,	"R/W",	0,	1,	65535ull,	0},
+	{"PHYS_EN"                     ,	16,	1,	372,	"R/W",	0,	1,	1ull,	0},
+	{"HG2RX_EN"                    ,	17,	1,	372,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2TX_EN"                    ,	18,	1,	372,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	372,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	1,	373,	"RO",	0,	1,	0ull,	0},
+	{"EN"                          ,	1,	1,	373,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_3"                ,	2,	2,	373,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	4,	3,	373,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	373,	"RAZ",	1,	1,	0,	0},
+	{"SPEED"                       ,	8,	4,	373,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	373,	"RAZ",	1,	1,	0,	0},
+	{"PRT"                         ,	0,	6,	374,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_15"               ,	6,	10,	374,	"RAZ",	1,	1,	0,	0},
+	{"PIPE"                        ,	16,	7,	374,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	374,	"RAZ",	1,	1,	0,	0},
+	{"STOP"                        ,	0,	4,	375,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	375,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	8,	4,	375,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	375,	"RAZ",	1,	1,	0,	0},
+	{"OVR"                         ,	16,	4,	375,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	375,	"RAZ",	1,	1,	0,	0},
+	{"RX_EN"                       ,	0,	1,	376,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_EN"                       ,	1,	1,	376,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRP_EN"                      ,	2,	1,	376,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCK_EN"                      ,	3,	1,	376,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	376,	"RAZ",	1,	1,	0,	0},
+	{"PHYS_BP"                     ,	16,	16,	376,	"R/W",	0,	1,	65535ull,	0},
+	{"LOGL_EN"                     ,	32,	16,	376,	"R/W",	0,	0,	255ull,	255ull},
+	{"PHYS_EN"                     ,	48,	16,	376,	"R/W",	0,	0,	255ull,	255ull},
+	{"EN"                          ,	0,	1,	377,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	377,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	377,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	377,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	377,	"RAZ",	1,	1,	0,	0},
+	{"SPEED_MSB"                   ,	8,	1,	377,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	377,	"RAZ",	1,	1,	0,	0},
+	{"RX_IDLE"                     ,	12,	1,	377,	"RO",	0,	1,	1ull,	0},
+	{"TX_IDLE"                     ,	13,	1,	377,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	377,	"RAZ",	1,	1,	0,	0},
+	{"PKND"                        ,	16,	6,	377,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_63"              ,	22,	42,	377,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	378,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	379,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	380,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	381,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	382,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	383,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	32,	384,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	384,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	385,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	385,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	386,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	386,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	386,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	386,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	387,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	387,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	388,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	388,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_2"                ,	2,	1,	388,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	388,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	388,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_6"                ,	5,	2,	388,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	388,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	388,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	388,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	389,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	389,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	389,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	389,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	389,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	389,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_8"                ,	7,	2,	389,	"RAZ",	1,	1,	0,	0},
+	{"PRE_ALIGN"                   ,	9,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"NULL_DIS"                    ,	10,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	389,	"RAZ",	1,	1,	0,	0},
+	{"PTP_MODE"                    ,	12,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	389,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	390,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	390,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	391,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	391,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	391,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	391,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	391,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	392,	"R/W1C",	0,	1,	0ull,	0},
+	{"CAREXT"                      ,	1,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	392,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	392,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	392,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	392,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	392,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	393,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	393,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	394,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	394,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	395,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	395,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	396,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	396,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	397,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	397,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	398,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	398,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	399,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	399,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	400,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	400,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	401,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	401,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	402,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	402,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	403,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	403,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	404,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	404,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	405,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	405,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	406,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	406,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	407,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	407,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	11,	408,	"R/W",	0,	0,	128ull,	128ull},
+	{"RESERVED_11_63"              ,	11,	53,	408,	"RAZ",	1,	1,	0,	0},
+	{"LGTIM2GO"                    ,	0,	16,	409,	"RO",	0,	1,	0ull,	0},
+	{"XOF"                         ,	16,	16,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PHTIM2GO"                    ,	32,	16,	409,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	409,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	4,	410,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	410,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	4,	410,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	410,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	3,	411,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_3_63"               ,	3,	61,	411,	"RAZ",	1,	1,	0,	0},
+	{"LANE_RXD"                    ,	0,	32,	412,	"RO",	0,	1,	0ull,	0},
+	{"LANE_RXC"                    ,	32,	4,	412,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	3,	412,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	39,	1,	412,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	412,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	2,	413,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	413,	"RAZ",	1,	1,	0,	0},
+	{"DISPARITY"                   ,	0,	1,	414,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	414,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	415,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	415,	"RAZ",	1,	1,	0,	0},
+	{"CLEAR_BIST"                  ,	0,	1,	416,	"R/W",	0,	1,	0ull,	0},
+	{"START_BIST"                  ,	1,	1,	416,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	416,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	417,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	417,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	417,	"RAZ",	1,	1,	0,	0},
+	{"WR_MAGIC"                    ,	0,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	418,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	419,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	419,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	419,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	419,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	419,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	16,	420,	"R/W",	0,	0,	8192ull,	8192ull},
+	{"RESERVED_16_63"              ,	16,	48,	420,	"RAZ",	1,	1,	0,	0},
+	{"XOFF"                        ,	0,	16,	421,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	421,	"RAZ",	1,	1,	0,	0},
+	{"XON"                         ,	0,	16,	422,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	422,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	423,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	423,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	423,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	424,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	424,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	425,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	425,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	426,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	426,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	427,	"RO",	1,	1,	0,	0},
+	{"MSG_TIME"                    ,	16,	16,	427,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	427,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	428,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	428,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	7,	429,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_15"               ,	7,	9,	429,	"RAZ",	1,	1,	0,	0},
+	{"NUMP"                        ,	16,	5,	429,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_31"              ,	21,	11,	429,	"RAZ",	1,	1,	0,	0},
+	{"IGN_BP"                      ,	32,	1,	429,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	429,	"RAZ",	1,	1,	0,	0},
+	{"ALIGN"                       ,	0,	1,	430,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	430,	"RAZ",	1,	1,	0,	0},
+	{"SLOT"                        ,	0,	10,	431,	"R/W",	0,	0,	512ull,	512ull},
+	{"RESERVED_10_63"              ,	10,	54,	431,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	432,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	432,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	433,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	433,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	434,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	434,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	435,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	435,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	436,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	436,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	437,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	437,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	438,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	438,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	439,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	439,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	440,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	440,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	441,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	441,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	442,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	442,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	443,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	443,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	10,	444,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_10_63"              ,	10,	54,	444,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	4,	445,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	445,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	446,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	446,	"RAZ",	1,	1,	0,	0},
+	{"CORRUPT"                     ,	0,	4,	447,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_4_63"               ,	4,	60,	447,	"RAZ",	1,	1,	0,	0},
+	{"TX_XOF"                      ,	0,	16,	448,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	448,	"RAZ",	1,	1,	0,	0},
+	{"TX_XON"                      ,	0,	16,	449,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	449,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	450,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	450,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	450,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO_NXP"                     ,	1,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	451,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTP_LOST"                    ,	20,	4,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"XCHANGE"                     ,	24,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	451,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	452,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO_NXP"                     ,	1,	1,	452,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	452,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	452,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	452,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	452,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	452,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTP_LOST"                    ,	20,	4,	452,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XCHANGE"                     ,	24,	1,	452,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	452,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	453,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	453,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	454,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	454,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	4,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	4,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	4,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	455,	"RAZ",	1,	1,	0,	0},
+	{"TX_PRT_BP"                   ,	32,	16,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	455,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	456,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	456,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	457,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	457,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	5,	458,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	458,	"RAZ",	1,	1,	0,	0},
+	{"DIC_EN"                      ,	0,	1,	459,	"R/W",	0,	0,	0ull,	1ull},
+	{"UNI_EN"                      ,	1,	1,	459,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	459,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	4,	2,	459,	"R/W",	0,	0,	0ull,	0ull},
+	{"LS_BYP"                      ,	6,	1,	459,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	459,	"RAZ",	1,	1,	0,	0},
+	{"HG_EN"                       ,	8,	1,	459,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_PAUSE_HGI"                ,	9,	2,	459,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_11_63"              ,	11,	53,	459,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	4,	460,	"R/W",	0,	0,	6ull,	6ull},
+	{"EN"                          ,	4,	1,	460,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	460,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	461,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	461,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	461,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	461,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	461,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	461,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_SEL"                     ,	12,	2,	461,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_GEN"                     ,	14,	1,	461,	"R/W",	0,	0,	0ull,	0ull},
+	{"SYNCE_SEL"                   ,	15,	2,	461,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	461,	"RAZ",	1,	1,	0,	0},
+	{"N"                           ,	0,	32,	462,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	462,	"RAZ",	1,	1,	0,	0},
+	{"LANE_SEL"                    ,	0,	2,	463,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIV"                         ,	2,	1,	463,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	463,	"RAZ",	1,	1,	0,	0},
+	{"QLM_SEL"                     ,	8,	3,	463,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	463,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	464,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	464,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	465,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	465,	"RAZ",	1,	1,	0,	0},
+	{"SEL"                         ,	0,	4,	466,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	466,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	16,	467,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	467,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	16,	468,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	468,	"RAZ",	1,	1,	0,	0},
+	{"TLK0_TXF0"                   ,	0,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"TLK0_TXF1"                   ,	1,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"TLK0_TXF2"                   ,	2,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"TLK0_STAT0"                  ,	3,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"TLK0_FWC"                    ,	4,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"TLK0_STAT1"                  ,	5,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"TLK1_TXF0"                   ,	6,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"TLK1_TXF1"                   ,	7,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"TLK1_TXF2"                   ,	8,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"TLK1_STAT0"                  ,	9,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"TLK1_FWC"                    ,	10,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"TLK1_STAT1"                  ,	11,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLK0_STAT"                   ,	12,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLK0_FWC"                    ,	13,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLK0_STAT1"                  ,	14,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	469,	"RAZ",	0,	1,	0ull,	0},
+	{"RLK1_STAT"                   ,	16,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLK1_FWC"                    ,	17,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLK1_STAT1"                  ,	18,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_19_19"              ,	19,	1,	469,	"RAZ",	0,	1,	0ull,	0},
+	{"RLE0_DSK0"                   ,	20,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE0_DSK1"                   ,	21,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE1_DSK0"                   ,	22,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE1_DSK1"                   ,	23,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE2_DSK0"                   ,	24,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE2_DSK1"                   ,	25,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE3_DSK0"                   ,	26,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE3_DSK1"                   ,	27,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE4_DSK0"                   ,	28,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE4_DSK1"                   ,	29,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE5_DSK0"                   ,	30,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE5_DSK1"                   ,	31,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE6_DSK0"                   ,	32,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE6_DSK1"                   ,	33,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE7_DSK0"                   ,	34,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RLE7_DSK1"                   ,	35,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_51"              ,	36,	16,	469,	"RAZ",	0,	1,	0ull,	0},
+	{"RXF_MEM0"                    ,	52,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RXF_MEM1"                    ,	53,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RXF_MEM2"                    ,	54,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RXF_PMAP"                    ,	55,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RXF_X2P0"                    ,	56,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RXF_X2P1"                    ,	57,	1,	469,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	469,	"RAZ",	0,	1,	0ull,	0},
+	{"RXF_XLINK"                   ,	0,	1,	470,	"R/W",	0,	1,	0ull,	0},
+	{"CCLK_DIS"                    ,	1,	1,	470,	"R/W",	0,	1,	0ull,	0},
+	{"RESET"                       ,	2,	1,	470,	"R/W",	0,	1,	0ull,	0},
+	{"RID_RSTDIS"                  ,	3,	1,	470,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	470,	"RAZ",	0,	1,	0ull,	0},
+	{"RXF_LNK0_PERR"               ,	0,	1,	471,	"R/W1C",	0,	1,	0ull,	0},
+	{"RXF_LNK1_PERR"               ,	1,	1,	471,	"R/W1C",	0,	1,	0ull,	0},
+	{"RXF_CTL_PERR"                ,	2,	1,	471,	"R/W1C",	0,	1,	0ull,	0},
+	{"RXF_POP_EMPTY"               ,	3,	1,	471,	"R/W1C",	0,	1,	0ull,	0},
+	{"RXF_PUSH_FULL"               ,	4,	1,	471,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	471,	"RAZ",	0,	1,	0ull,	0},
+	{"RXF_LNK0_PERR"               ,	0,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"RXF_LNK1_PERR"               ,	1,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"RXF_CTL_PERR"                ,	2,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"RXF_POP_EMPTY"               ,	3,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"RXF_PUSH_FULL"               ,	4,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	472,	"RAZ",	0,	1,	0ull,	0},
+	{"GBL_INT"                     ,	0,	1,	473,	"RO",	0,	1,	0ull,	0},
+	{"TLK0_INT"                    ,	1,	1,	473,	"RO",	0,	1,	0ull,	0},
+	{"TLK1_INT"                    ,	2,	1,	473,	"RO",	0,	1,	0ull,	0},
+	{"RLK0_INT"                    ,	3,	1,	473,	"RO",	0,	1,	0ull,	0},
+	{"RLK1_INT"                    ,	4,	1,	473,	"RO",	0,	1,	0ull,	0},
+	{"RLE0_INT"                    ,	5,	1,	473,	"RO",	0,	1,	0ull,	0},
+	{"RLE1_INT"                    ,	6,	1,	473,	"RO",	0,	1,	0ull,	0},
+	{"RLE2_INT"                    ,	7,	1,	473,	"RO",	0,	1,	0ull,	0},
+	{"RLE3_INT"                    ,	8,	1,	473,	"RO",	0,	1,	0ull,	0},
+	{"RLE4_INT"                    ,	9,	1,	473,	"RO",	0,	1,	0ull,	0},
+	{"RLE5_INT"                    ,	10,	1,	473,	"RO",	0,	1,	0ull,	0},
+	{"RLE6_INT"                    ,	11,	1,	473,	"RO",	0,	1,	0ull,	0},
+	{"RLE7_INT"                    ,	12,	1,	473,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_13_63"              ,	13,	51,	473,	"RAZ",	0,	1,	0ull,	0},
+	{"TX_DIS_SCRAM"                ,	0,	8,	474,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	474,	"RAZ",	0,	1,	0ull,	0},
+	{"TX_DIS_DISPR"                ,	16,	8,	474,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_31"              ,	24,	8,	474,	"RAZ",	0,	1,	0ull,	0},
+	{"TX_BAD_LANE_SEL"             ,	32,	8,	474,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_47"              ,	40,	8,	474,	"RAZ",	0,	1,	0ull,	0},
+	{"TX_BAD_SCRAM_CNT"            ,	48,	3,	474,	"R/W",	0,	1,	0ull,	0},
+	{"TX_BAD_SYNC_CNT"             ,	51,	3,	474,	"R/W",	0,	1,	0ull,	0},
+	{"TX_BAD_6467_CNT"             ,	54,	5,	474,	"R/W",	0,	1,	0ull,	0},
+	{"TX_BAD_CRC32"                ,	59,	1,	474,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	474,	"RAZ",	0,	1,	0ull,	0},
+	{"TX_LNE_STAT"                 ,	0,	8,	475,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	475,	"RAZ",	0,	1,	0ull,	0},
+	{"TX_LNK_STAT"                 ,	16,	8,	475,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_24_31"              ,	24,	8,	475,	"RAZ",	0,	1,	0ull,	0},
+	{"RX_LNE_STAT"                 ,	32,	8,	475,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_40_47"              ,	40,	8,	475,	"RAZ",	0,	1,	0ull,	0},
+	{"RX_LNK_STAT"                 ,	48,	8,	475,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	475,	"RAZ",	0,	1,	0ull,	0},
+	{"LANE_ENA"                    ,	0,	8,	476,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	476,	"RAZ",	0,	1,	0ull,	0},
+	{"CAL_DEPTH"                   ,	16,	9,	476,	"R/W",	0,	1,	144ull,	0},
+	{"RESERVED_25_25"              ,	25,	1,	476,	"RAZ",	0,	1,	0ull,	0},
+	{"BRST_MAX"                    ,	26,	5,	476,	"R/W",	0,	1,	4ull,	0},
+	{"LANE_REV"                    ,	31,	1,	476,	"R/W",	0,	1,	0ull,	0},
+	{"BRST_SHRT"                   ,	32,	7,	476,	"R/W",	0,	1,	4ull,	0},
+	{"MFRM_LEN"                    ,	39,	13,	476,	"R/W",	0,	1,	1024ull,	0},
+	{"CAL_ENA"                     ,	52,	1,	476,	"R/W",	0,	1,	0ull,	0},
+	{"MLTUSE_FC_ENA"               ,	53,	1,	476,	"R/W",	0,	1,	0ull,	0},
+	{"LNK_STATS_ENA"               ,	54,	1,	476,	"R/W",	0,	1,	0ull,	0},
+	{"LNK_STATS_RDCLR"             ,	55,	1,	476,	"R/W",	0,	1,	0ull,	0},
+	{"PTRN_MODE"                   ,	56,	1,	476,	"RAZ",	0,	1,	0ull,	0},
+	{"MPROTO_IGN"                  ,	57,	1,	476,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCW_PUSH"                    ,	58,	1,	476,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_STATS_WRAP"              ,	59,	1,	476,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_61"              ,	60,	2,	476,	"RAZ",	0,	1,	0ull,	0},
+	{"EXT_LPBK"                    ,	62,	1,	476,	"R/W",	0,	1,	0ull,	0},
+	{"EXT_LPBK_FC"                 ,	63,	1,	476,	"R/W",	0,	1,	0ull,	0},
+	{"RX_BDRY_LOCK_ENA"            ,	0,	8,	477,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	477,	"RAZ",	0,	1,	0ull,	0},
+	{"RX_ALIGN_ENA"                ,	16,	1,	477,	"R/W",	0,	1,	0ull,	0},
+	{"RX_LINK_FC"                  ,	17,	1,	477,	"RO",	0,	1,	0ull,	0},
+	{"TX_LINK_FC"                  ,	18,	1,	477,	"RO",	0,	1,	0ull,	0},
+	{"LA_MODE"                     ,	19,	1,	477,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_ENA"                     ,	20,	1,	477,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_FLUSH"                   ,	21,	1,	477,	"WR0",	0,	1,	0ull,	0},
+	{"RX_FIFO_MAX"                 ,	22,	12,	477,	"R/W",	0,	1,	1024ull,	0},
+	{"RESERVED_34_35"              ,	34,	2,	477,	"RAZ",	0,	1,	0ull,	0},
+	{"RX_FIFO_HWM"                 ,	36,	12,	477,	"R/W",	0,	1,	512ull,	0},
+	{"RESERVED_48_49"              ,	48,	2,	477,	"RAZ",	0,	1,	0ull,	0},
+	{"RX_FIFO_CNT"                 ,	50,	12,	477,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	477,	"RAZ",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	0,	64,	478,	"RO",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	0,	64,	479,	"RO",	0,	1,	0ull,	0},
+	{"INDEX"                       ,	0,	6,	480,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	480,	"RAZ",	0,	1,	0ull,	0},
+	{"INC"                         ,	8,	6,	480,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	480,	"RAZ",	0,	1,	0ull,	0},
+	{"INDEX"                       ,	0,	8,	481,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	481,	"RAZ",	0,	1,	0ull,	0},
+	{"INC"                         ,	16,	8,	481,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_30"              ,	24,	7,	481,	"RAZ",	0,	1,	0ull,	0},
+	{"CLR"                         ,	31,	1,	481,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	481,	"RAZ",	0,	1,	0ull,	0},
+	{"INDEX"                       ,	0,	8,	482,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	482,	"RAZ",	0,	1,	0ull,	0},
+	{"INC"                         ,	16,	8,	482,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_30"              ,	24,	7,	482,	"RAZ",	0,	1,	0ull,	0},
+	{"CLR"                         ,	31,	1,	482,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	482,	"RAZ",	0,	1,	0ull,	0},
+	{"LANE_ALIGN_FAIL"             ,	0,	1,	483,	"R/W1C",	0,	1,	0ull,	0},
+	{"CRC24_ERR"                   ,	1,	1,	483,	"R/W1C",	0,	1,	0ull,	0},
+	{"WORD_SYNC_DONE"              ,	2,	1,	483,	"R/W1C",	0,	1,	0ull,	0},
+	{"LANE_ALIGN_DONE"             ,	3,	1,	483,	"R/W1C",	0,	1,	0ull,	0},
+	{"STAT_CNT_OVFL"               ,	4,	1,	483,	"R/W1C",	0,	1,	0ull,	0},
+	{"LANE_BAD_WORD"               ,	5,	1,	483,	"R/W1C",	0,	1,	0ull,	0},
+	{"PKT_DROP_RXF"                ,	6,	1,	483,	"R/W1C",	0,	1,	0ull,	0},
+	{"PKT_DROP_RID"                ,	7,	1,	483,	"R/W1C",	0,	1,	0ull,	0},
+	{"PKT_DROP_SOP"                ,	8,	1,	483,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	483,	"RAZ",	0,	1,	0ull,	0},
+	{"LANE_ALIGN_FAIL"             ,	0,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"CRC24_ERR"                   ,	1,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"WORD_SYNC_DONE"              ,	2,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"LANE_ALIGN_DONE"             ,	3,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"STAT_CNT_OVFL"               ,	4,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"LANE_BAD_WORD"               ,	5,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_DROP_RXF"                ,	6,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_DROP_RID"                ,	7,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_DROP_SOP"                ,	8,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	484,	"RAZ",	0,	1,	0ull,	0},
+	{"CNT"                         ,	0,	16,	485,	"R/W",	0,	1,	10240ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	485,	"RAZ",	0,	1,	0ull,	0},
+	{"PORT_PIPE0"                  ,	0,	7,	486,	"R/W",	0,	1,	0ull,	0},
+	{"ENTRY_CTL0"                  ,	7,	2,	486,	"R/W",	0,	1,	0ull,	0},
+	{"PORT_PIPE1"                  ,	9,	7,	486,	"R/W",	0,	1,	0ull,	0},
+	{"ENTRY_CTL1"                  ,	16,	2,	486,	"R/W",	0,	1,	0ull,	0},
+	{"PORT_PIPE2"                  ,	18,	7,	486,	"R/W",	0,	1,	0ull,	0},
+	{"ENTRY_CTL2"                  ,	25,	2,	486,	"R/W",	0,	1,	0ull,	0},
+	{"PORT_PIPE3"                  ,	27,	7,	486,	"R/W",	0,	1,	0ull,	0},
+	{"ENTRY_CTL3"                  ,	34,	2,	486,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	486,	"RAZ",	0,	1,	0ull,	0},
+	{"PORT_PIPE4"                  ,	0,	7,	487,	"R/W",	0,	1,	0ull,	0},
+	{"ENTRY_CTL4"                  ,	7,	2,	487,	"R/W",	0,	1,	0ull,	0},
+	{"PORT_PIPE5"                  ,	9,	7,	487,	"R/W",	0,	1,	0ull,	0},
+	{"ENTRY_CTL5"                  ,	16,	2,	487,	"R/W",	0,	1,	0ull,	0},
+	{"PORT_PIPE6"                  ,	18,	7,	487,	"R/W",	0,	1,	0ull,	0},
+	{"ENTRY_CTL6"                  ,	25,	2,	487,	"R/W",	0,	1,	0ull,	0},
+	{"PORT_PIPE7"                  ,	27,	7,	487,	"R/W",	0,	1,	0ull,	0},
+	{"ENTRY_CTL7"                  ,	34,	2,	487,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	487,	"RAZ",	0,	1,	0ull,	0},
+	{"RX_PKT"                      ,	0,	28,	488,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	488,	"RAZ",	0,	1,	0ull,	0},
+	{"RX_BYTES"                    ,	0,	36,	489,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	489,	"RAZ",	0,	1,	0ull,	0},
+	{"MAX_CNT"                     ,	0,	6,	490,	"R/W",	0,	1,	45ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	490,	"RAZ",	0,	1,	0ull,	0},
+	{"CRC24_MATCH_CNT"             ,	0,	33,	491,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	491,	"RAZ",	0,	1,	0ull,	0},
+	{"CRC24_ERR_CNT"               ,	0,	18,	492,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	492,	"RAZ",	0,	1,	0ull,	0},
+	{"BRST_CNT"                    ,	0,	28,	493,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	493,	"RAZ",	0,	1,	0ull,	0},
+	{"BRST_NOT_FULL_CNT"           ,	32,	16,	493,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	493,	"RAZ",	0,	1,	0ull,	0},
+	{"BRST_MAX_ERR_CNT"            ,	0,	16,	494,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	494,	"RAZ",	0,	1,	0ull,	0},
+	{"BRST_SHRT_ERR_CNT"           ,	0,	16,	495,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	495,	"RAZ",	0,	1,	0ull,	0},
+	{"ALIGN_CNT"                   ,	0,	23,	496,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	496,	"RAZ",	0,	1,	0ull,	0},
+	{"ALIGN_ERR_CNT"               ,	0,	16,	497,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	497,	"RAZ",	0,	1,	0ull,	0},
+	{"BAD_64B67B_CNT"              ,	0,	16,	498,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	498,	"RAZ",	0,	1,	0ull,	0},
+	{"PKT_DROP_RXF_CNT"            ,	0,	16,	499,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_DROP_RID_CNT"            ,	16,	16,	499,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	499,	"RAZ",	0,	1,	0ull,	0},
+	{"RESERVED_0_63"               ,	0,	64,	500,	"RAZ",	0,	1,	0ull,	0},
+	{"STAT_ENA"                    ,	0,	1,	501,	"R/W",	0,	1,	0ull,	0},
+	{"STAT_RDCLR"                  ,	1,	1,	501,	"R/W",	0,	1,	0ull,	0},
+	{"RX_DIS_SCRAM"                ,	2,	1,	501,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_DIS_UKWN"                 ,	3,	1,	501,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_BDRY_SYNC"                ,	4,	1,	501,	"RO",	0,	1,	0ull,	0},
+	{"RX_SCRM_SYNC"                ,	5,	1,	501,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	501,	"RAZ",	0,	1,	0ull,	0},
+	{"RX_DIS_PSH_SKIP"             ,	8,	1,	501,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	501,	"RAZ",	0,	1,	0ull,	0},
+	{"SERDES_LOCK_LOSS"            ,	0,	1,	502,	"R/W1C",	0,	1,	0ull,	0},
+	{"BDRY_SYNC_LOSS"              ,	1,	1,	502,	"R/W1C",	0,	1,	0ull,	0},
+	{"CRC32_ERR"                   ,	2,	1,	502,	"R/W1C",	0,	1,	0ull,	0},
+	{"UKWN_CNTL_WORD"              ,	3,	1,	502,	"R/W1C",	0,	1,	0ull,	0},
+	{"SCRM_SYNC_LOSS"              ,	4,	1,	502,	"R/W1C",	0,	1,	0ull,	0},
+	{"DSKEW_FIFO_OVFL"             ,	5,	1,	502,	"R/W1C",	0,	1,	0ull,	0},
+	{"STAT_MSG"                    ,	6,	1,	502,	"R/W1C",	0,	1,	0ull,	0},
+	{"STAT_CNT_OVFL"               ,	7,	1,	502,	"R/W1C",	0,	1,	0ull,	0},
+	{"BAD_64B67B"                  ,	8,	1,	502,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	502,	"RAZ",	0,	1,	0ull,	0},
+	{"SERDES_LOCK_LOSS"            ,	0,	1,	503,	"R/W",	0,	1,	0ull,	0},
+	{"BDRY_SYNC_LOSS"              ,	1,	1,	503,	"R/W",	0,	1,	0ull,	0},
+	{"CRC32_ERR"                   ,	2,	1,	503,	"R/W",	0,	1,	0ull,	0},
+	{"UKWN_CNTL_WORD"              ,	3,	1,	503,	"R/W",	0,	1,	0ull,	0},
+	{"SCRM_SYNC_LOSS"              ,	4,	1,	503,	"R/W",	0,	1,	0ull,	0},
+	{"DSKEW_FIFO_OVFL"             ,	5,	1,	503,	"R/W",	0,	1,	0ull,	0},
+	{"STAT_MSG"                    ,	6,	1,	503,	"R/W",	0,	1,	0ull,	0},
+	{"STAT_CNT_OVFL"               ,	7,	1,	503,	"R/W",	0,	1,	0ull,	0},
+	{"BAD_64B67B"                  ,	8,	1,	503,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	503,	"RAZ",	0,	1,	0ull,	0},
+	{"SER_LOCK_LOSS_CNT"           ,	0,	18,	504,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	504,	"RAZ",	0,	1,	0ull,	0},
+	{"BDRY_SYNC_LOSS_CNT"          ,	0,	18,	505,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	505,	"RAZ",	0,	1,	0ull,	0},
+	{"SYNCW_BAD_CNT"               ,	0,	18,	506,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_31"              ,	18,	14,	506,	"RAZ",	0,	1,	0ull,	0},
+	{"SYNCW_GOOD_CNT"              ,	32,	18,	506,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_50_63"              ,	50,	14,	506,	"RAZ",	0,	1,	0ull,	0},
+	{"BAD_64B67B_CNT"              ,	0,	18,	507,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	507,	"RAZ",	0,	1,	0ull,	0},
+	{"DATA_WORD_CNT"               ,	0,	27,	508,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_27_31"              ,	27,	5,	508,	"RAZ",	0,	1,	0ull,	0},
+	{"CNTL_WORD_CNT"               ,	32,	27,	508,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_59_63"              ,	59,	5,	508,	"RAZ",	0,	1,	0ull,	0},
+	{"UNKWN_WORD_CNT"              ,	0,	18,	509,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	509,	"RAZ",	0,	1,	0ull,	0},
+	{"SCRM_SYNC_LOSS_CNT"          ,	0,	18,	510,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	510,	"RAZ",	0,	1,	0ull,	0},
+	{"SCRM_MATCH_CNT"              ,	0,	18,	511,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	511,	"RAZ",	0,	1,	0ull,	0},
+	{"SKIPW_GOOD_CNT"              ,	0,	18,	512,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	512,	"RAZ",	0,	1,	0ull,	0},
+	{"CRC32_MATCH_CNT"             ,	0,	27,	513,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_27_31"              ,	27,	5,	513,	"RAZ",	0,	1,	0ull,	0},
+	{"CRC32_ERR_CNT"               ,	32,	18,	513,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_50_63"              ,	50,	14,	513,	"RAZ",	0,	1,	0ull,	0},
+	{"INDEX"                       ,	0,	9,	514,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_15"               ,	9,	7,	514,	"RAZ",	0,	1,	0ull,	0},
+	{"INC"                         ,	16,	9,	514,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	514,	"RAZ",	0,	1,	0ull,	0},
+	{"PORT_KIND"                   ,	0,	6,	515,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	515,	"RAZ",	0,	1,	0ull,	0},
+	{"SER_HAUL"                    ,	0,	2,	516,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_3"                ,	2,	2,	516,	"RAZ",	0,	1,	0ull,	0},
+	{"SER_PWRUP"                   ,	4,	2,	516,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	516,	"RAZ",	0,	1,	0ull,	0},
+	{"SER_RESET_N"                 ,	8,	8,	516,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_23"              ,	16,	8,	516,	"RAZ",	0,	1,	0ull,	0},
+	{"SER_TXPOL"                   ,	24,	8,	516,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_39"              ,	32,	8,	516,	"RAZ",	0,	1,	0ull,	0},
+	{"SER_RXPOL"                   ,	40,	8,	516,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_55"              ,	48,	8,	516,	"RAZ",	0,	1,	0ull,	0},
+	{"SER_RXPOL_AUTO"              ,	56,	1,	516,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_57_63"              ,	57,	7,	516,	"RAZ",	0,	1,	0ull,	0},
+	{"LANE_ENA"                    ,	0,	8,	517,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	517,	"RAZ",	0,	1,	0ull,	0},
+	{"CAL_DEPTH"                   ,	16,	9,	517,	"R/W",	0,	1,	72ull,	0},
+	{"RESERVED_25_25"              ,	25,	1,	517,	"RAZ",	0,	1,	0ull,	0},
+	{"BRST_MAX"                    ,	26,	5,	517,	"R/W",	0,	1,	4ull,	0},
+	{"LANE_REV"                    ,	31,	1,	517,	"R/W",	0,	1,	0ull,	0},
+	{"BRST_SHRT"                   ,	32,	7,	517,	"R/W",	0,	1,	4ull,	0},
+	{"MFRM_LEN"                    ,	39,	13,	517,	"R/W",	0,	1,	1024ull,	0},
+	{"CAL_ENA"                     ,	52,	1,	517,	"R/W",	0,	1,	0ull,	0},
+	{"MLTUSE_FC_ENA"               ,	53,	1,	517,	"R/W",	0,	1,	0ull,	0},
+	{"LNK_STATS_ENA"               ,	54,	1,	517,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_55_55"              ,	55,	1,	517,	"RAZ",	0,	1,	0ull,	0},
+	{"PTRN_MODE"                   ,	56,	1,	517,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_57_60"              ,	57,	4,	517,	"RAZ",	0,	1,	0ull,	0},
+	{"INT_LPBK"                    ,	61,	1,	517,	"R/W",	0,	1,	0ull,	0},
+	{"EXT_LPBK"                    ,	62,	1,	517,	"R/W",	0,	1,	0ull,	0},
+	{"EXT_LPBK_FC"                 ,	63,	1,	517,	"R/W",	0,	1,	0ull,	0},
+	{"TX_MLTUSE"                   ,	0,	8,	518,	"R/W",	0,	1,	0ull,	0},
+	{"RMATCH"                      ,	8,	1,	518,	"R/W",	0,	1,	0ull,	0},
+	{"RX_LINK_FC_IGN"              ,	9,	1,	518,	"R/W",	0,	1,	0ull,	0},
+	{"RX_LINK_FC_PKT"              ,	10,	1,	518,	"R/W",	0,	1,	0ull,	0},
+	{"TX_LINK_FC_JAM"              ,	11,	1,	518,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_16"              ,	12,	5,	518,	"RAZ",	0,	1,	0ull,	0},
+	{"RX_LINK_FC"                  ,	17,	1,	518,	"RO",	0,	1,	0ull,	0},
+	{"TX_LINK_FC"                  ,	18,	1,	518,	"RO",	0,	1,	0ull,	0},
+	{"LA_MODE"                     ,	19,	1,	518,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_ENA"                     ,	20,	1,	518,	"R/W",	0,	1,	1ull,	0},
+	{"PKT_FLUSH"                   ,	21,	1,	518,	"R/W",	0,	1,	0ull,	0},
+	{"SKIP_CNT"                    ,	22,	4,	518,	"R/W",	0,	1,	1ull,	0},
+	{"PTP_DELAY"                   ,	26,	5,	518,	"R/W",	0,	1,	26ull,	0},
+	{"PIPE_CRD_DIS"                ,	31,	1,	518,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_BUSY"                    ,	32,	1,	518,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	518,	"RAZ",	0,	1,	0ull,	0},
+	{"TX_BAD_CTLW1"                ,	0,	1,	519,	"R/W",	0,	1,	0ull,	0},
+	{"TX_BAD_CTLW2"                ,	1,	1,	519,	"R/W",	0,	1,	0ull,	0},
+	{"TX_BAD_CRC24"                ,	2,	1,	519,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	519,	"RAZ",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	0,	64,	520,	"RO",	0,	1,	18446744073709551615ull,	0},
+	{"RESERVED_0_63"               ,	0,	64,	521,	"RAZ",	0,	1,	0ull,	0},
+	{"INDEX"                       ,	0,	6,	522,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	522,	"RAZ",	0,	1,	0ull,	0},
+	{"INC"                         ,	8,	6,	522,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	522,	"RAZ",	0,	1,	0ull,	0},
+	{"INDEX"                       ,	0,	7,	523,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_15"               ,	7,	9,	523,	"RAZ",	0,	1,	0ull,	0},
+	{"INC"                         ,	16,	7,	523,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	523,	"RAZ",	0,	1,	0ull,	0},
+	{"INDEX"                       ,	0,	8,	524,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	524,	"RAZ",	0,	1,	0ull,	0},
+	{"INC"                         ,	16,	8,	524,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_30"              ,	24,	7,	524,	"RAZ",	0,	1,	0ull,	0},
+	{"CLR"                         ,	31,	1,	524,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	524,	"RAZ",	0,	1,	0ull,	0},
+	{"INDEX"                       ,	0,	8,	525,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	525,	"RAZ",	0,	1,	0ull,	0},
+	{"INC"                         ,	16,	8,	525,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_30"              ,	24,	7,	525,	"RAZ",	0,	1,	0ull,	0},
+	{"CLR"                         ,	31,	1,	525,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	525,	"RAZ",	0,	1,	0ull,	0},
+	{"TXF_ERR"                     ,	0,	1,	526,	"R/W1C",	0,	1,	0ull,	0},
+	{"BAD_SEQ"                     ,	1,	1,	526,	"R/W1C",	0,	1,	0ull,	0},
+	{"BAD_PIPE"                    ,	2,	1,	526,	"R/W1C",	0,	1,	0ull,	0},
+	{"STAT_CNT_OVFL"               ,	3,	1,	526,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	526,	"RAZ",	0,	1,	0ull,	0},
+	{"TXF_ERR"                     ,	0,	1,	527,	"R/W",	0,	1,	0ull,	0},
+	{"BAD_SEQ"                     ,	1,	1,	527,	"R/W",	0,	1,	0ull,	0},
+	{"BAD_PIPE"                    ,	2,	1,	527,	"R/W",	0,	1,	0ull,	0},
+	{"STAT_CNT_OVFL"               ,	3,	1,	527,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	527,	"RAZ",	0,	1,	0ull,	0},
+	{"BPID0"                       ,	0,	6,	528,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_6"                ,	6,	1,	528,	"RAZ",	0,	1,	0ull,	0},
+	{"ENTRY_CTL0"                  ,	7,	2,	528,	"R/W",	0,	1,	0ull,	0},
+	{"BPID1"                       ,	9,	6,	528,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	528,	"RAZ",	0,	1,	0ull,	0},
+	{"ENTRY_CTL1"                  ,	16,	2,	528,	"R/W",	0,	1,	0ull,	0},
+	{"BPID2"                       ,	18,	6,	528,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_24"              ,	24,	1,	528,	"RAZ",	0,	1,	0ull,	0},
+	{"ENTRY_CTL2"                  ,	25,	2,	528,	"R/W",	0,	1,	0ull,	0},
+	{"BPID3"                       ,	27,	6,	528,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_33"              ,	33,	1,	528,	"RAZ",	0,	1,	0ull,	0},
+	{"ENTRY_CTL3"                  ,	34,	2,	528,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	528,	"RAZ",	0,	1,	0ull,	0},
+	{"BPID4"                       ,	0,	6,	529,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_6"                ,	6,	1,	529,	"RAZ",	0,	1,	0ull,	0},
+	{"ENTRY_CTL4"                  ,	7,	2,	529,	"R/W",	0,	1,	0ull,	0},
+	{"BPID5"                       ,	9,	6,	529,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	529,	"RAZ",	0,	1,	0ull,	0},
+	{"ENTRY_CTL5"                  ,	16,	2,	529,	"R/W",	0,	1,	0ull,	0},
+	{"BPID6"                       ,	18,	6,	529,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_24"              ,	24,	1,	529,	"RAZ",	0,	1,	0ull,	0},
+	{"ENTRY_CTL6"                  ,	25,	2,	529,	"R/W",	0,	1,	0ull,	0},
+	{"BPID7"                       ,	27,	6,	529,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_33"              ,	33,	1,	529,	"RAZ",	0,	1,	0ull,	0},
+	{"ENTRY_CTL7"                  ,	34,	2,	529,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	529,	"RAZ",	0,	1,	0ull,	0},
+	{"CHANNEL"                     ,	0,	8,	530,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	530,	"RAZ",	0,	1,	0ull,	0},
+	{"REMAP"                       ,	16,	1,	530,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	530,	"RAZ",	0,	1,	0ull,	0},
+	{"TX_PKT"                      ,	0,	28,	531,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	531,	"RAZ",	0,	1,	0ull,	0},
+	{"TX_BYTES"                    ,	0,	36,	532,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	532,	"RAZ",	0,	1,	0ull,	0},
+	{"BASE"                        ,	0,	7,	533,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_15"               ,	7,	9,	533,	"RAZ",	0,	1,	0ull,	0},
+	{"NUMP"                        ,	16,	8,	533,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	533,	"RAZ",	0,	1,	0ull,	0},
+	{"RATE_LIMIT"                  ,	0,	16,	534,	"R/W",	0,	1,	1024ull,	0},
+	{"TIME_LIMIT"                  ,	16,	16,	534,	"R/W",	0,	1,	256ull,	0},
+	{"BRST_LIMIT"                  ,	32,	16,	534,	"R/W",	0,	1,	1024ull,	0},
+	{"GRNLRTY"                     ,	48,	2,	534,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_50_63"              ,	50,	14,	534,	"RAZ",	0,	1,	0ull,	0},
+	{"ICRP1"                       ,	0,	1,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP0"                       ,	1,	1,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	535,	"RAZ",	1,	1,	0,	0},
+	{"IOCFIF"                      ,	4,	1,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"RSDFIF"                      ,	5,	1,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"IORFIF"                      ,	6,	1,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"XMCFIF"                      ,	7,	1,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"XMDFIF"                      ,	8,	1,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	535,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_5"                ,	0,	6,	536,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XMC_PER"                     ,	6,	4,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIF_DLY"                     ,	10,	1,	536,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	536,	"RAZ",	1,	1,	0,	0},
+	{"NCB_WR"                      ,	0,	3,	537,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_5"                ,	3,	3,	537,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO_RD"                      ,	6,	4,	537,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	537,	"RAZ",	1,	1,	0,	0},
+	{"ICD"                         ,	0,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"IBD"                         ,	1,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN1"                       ,	2,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN0"                       ,	3,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ1"                       ,	4,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ0"                       ,	5,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRT"                       ,	6,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR1"                        ,	7,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR0"                        ,	8,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR0"                       ,	9,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR1"                        ,	10,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR0"                        ,	11,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRCB"                      ,	12,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"IOCFIF"                      ,	13,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"RSDFIF"                      ,	14,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"IORFIF"                      ,	15,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"XMCFIF"                      ,	16,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"XMDFIF"                      ,	17,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	538,	"RAZ",	1,	1,	0,	0},
+	{"FAU_END"                     ,	0,	1,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB_ENB"                     ,	1,	1,	539,	"R/W",	0,	0,	1ull,	1ull},
+	{"PKO_ENB"                     ,	2,	1,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"INB_MAT"                     ,	3,	1,	539,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTB_MAT"                    ,	4,	1,	539,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVR5"                       ,	5,	1,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"XMC_PER"                     ,	6,	4,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIF_DLY"                     ,	10,	1,	539,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	539,	"RAZ",	1,	1,	0,	0},
+	{"TOUT_VAL"                    ,	0,	12,	540,	"R/W",	0,	0,	4ull,	4ull},
+	{"TOUT_ENB"                    ,	12,	1,	540,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	540,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	541,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	541,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	541,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	541,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	541,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	542,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	542,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	542,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	542,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	542,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	543,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	544,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_63"               ,	0,	64,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_63"               ,	0,	64,	546,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	547,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	547,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	547,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	548,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	548,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	548,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	548,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	548,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	549,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	549,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	549,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	549,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	549,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	550,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	551,	"R/W",	0,	1,	0ull,	0},
+	{"CNT_VAL"                     ,	0,	15,	552,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	552,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	552,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	553,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	553,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	553,	"RAZ",	1,	1,	0,	0},
+	{"NCB_WR"                      ,	0,	3,	554,	"R/W",	0,	1,	0ull,	0},
+	{"NCB_RD"                      ,	3,	3,	554,	"R/W",	0,	1,	0ull,	0},
+	{"DWB"                         ,	6,	3,	554,	"R/W",	0,	1,	2ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	554,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	555,	"R/W",	0,	1,	13ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	555,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	556,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	556,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	557,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	557,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	558,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	558,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	559,	"R/W",	0,	1,	12ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	559,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	560,	"R/W",	0,	1,	40ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	560,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	561,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	561,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	562,	"R/W",	0,	1,	8ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	562,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	563,	"R/W",	0,	1,	8ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	563,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	564,	"R/W",	0,	1,	24ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	564,	"RAZ",	1,	1,	0,	0},
+	{"CRD"                         ,	0,	7,	565,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	565,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	566,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	567,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	568,	"RAZ",	1,	1,	0,	0},
+	{"PWP"                         ,	0,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_NEW"                     ,	1,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_OLD"                     ,	2,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"PRC_OFF"                     ,	3,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ0"                        ,	4,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ1"                        ,	5,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM_WORD"                    ,	6,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM0"                        ,	7,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM1"                        ,	8,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM2"                        ,	9,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM3"                        ,	10,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE0"                    ,	11,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE1"                    ,	12,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_POW"                     ,	13,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WP1"                     ,	14,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WQED"                    ,	15,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_NCMD"                    ,	16,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_MEM"                     ,	17,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM4"                        ,	18,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"IIO0"                        ,	19,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"IIO1"                        ,	20,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"IIWO0"                       ,	21,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"IIWO1"                       ,	22,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	569,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	570,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	571,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	571,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	64,	572,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB_WR"                      ,	0,	8,	573,	"R/W",	0,	0,	8ull,	8ull},
+	{"IOB_WRC"                     ,	8,	8,	573,	"RO",	0,	1,	8ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	573,	"RAZ",	1,	1,	0,	0},
+	{"IPD_EN"                      ,	0,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC_MODE"                    ,	1,	2,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBP_EN"                      ,	3,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"WQE_LEND"                    ,	4,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_LEND"                    ,	5,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"NADDBUF"                     ,	6,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDPKT"                      ,	7,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	8,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_M8"                      ,	9,	1,	574,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKT_OFF"                     ,	10,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_FULL"                    ,	11,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_NABUF"                    ,	12,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_APKT"                     ,	13,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"NO_WPTR"                     ,	14,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKEN"                       ,	15,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"RST_DONE"                    ,	16,	1,	574,	"RO",	0,	0,	1ull,	0ull},
+	{"USE_SOP"                     ,	17,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	574,	"RAZ",	1,	1,	0,	0},
+	{"PM0_SYN"                     ,	0,	2,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM1_SYN"                     ,	2,	2,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM2_SYN"                     ,	4,	2,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM3_SYN"                     ,	6,	2,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	575,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	8,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	8,	1,	576,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRADDR"                      ,	9,	8,	576,	"RO",	1,	1,	0,	0},
+	{"WRADDR"                      ,	17,	8,	576,	"RO",	1,	1,	0,	0},
+	{"MAX_CNTS"                    ,	25,	7,	576,	"RO",	0,	0,	64ull,	64ull},
+	{"RESERVED_32_63"              ,	32,	32,	576,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	577,	"RO",	1,	1,	0,	0},
+	{"RESERVED_33_63"              ,	33,	31,	577,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	3,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	3,	1,	578,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRADDR"                      ,	4,	3,	578,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	7,	3,	578,	"RO",	0,	0,	5ull,	5ull},
+	{"PTR"                         ,	10,	33,	578,	"RO",	1,	1,	0,	0},
+	{"RESERVED_43_63"              ,	43,	21,	578,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"SOP"                         ,	12,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"EOP"                         ,	13,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"DAT"                         ,	14,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"PW0_SBE"                     ,	15,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"PW0_DBE"                     ,	16,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"PW1_SBE"                     ,	17,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"PW1_DBE"                     ,	18,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"PW2_SBE"                     ,	19,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"PW2_DBE"                     ,	20,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"PW3_SBE"                     ,	21,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"PW3_DBE"                     ,	22,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	579,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SOP"                         ,	12,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EOP"                         ,	13,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DAT"                         ,	14,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PW0_SBE"                     ,	15,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PW0_DBE"                     ,	16,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PW1_SBE"                     ,	17,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PW1_DBE"                     ,	18,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PW2_SBE"                     ,	19,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PW2_DBE"                     ,	20,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PW3_SBE"                     ,	21,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PW3_DBE"                     ,	22,	1,	580,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	580,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	581,	"RO",	1,	1,	0,	0},
+	{"RESERVED_33_63"              ,	33,	31,	581,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	582,	"RO",	1,	1,	0,	0},
+	{"RESERVED_33_63"              ,	33,	31,	582,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	583,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	64,	584,	"R/W",	0,	0,	0ull,	0ull},
+	{"MB_SIZE"                     ,	0,	12,	585,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_12_63"              ,	12,	52,	585,	"RAZ",	1,	1,	0,	0},
+	{"REASM"                       ,	0,	6,	586,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	586,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	7,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	7,	1,	587,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAX_PKT"                     ,	8,	7,	587,	"RO",	0,	0,	64ull,	64ull},
+	{"PTR"                         ,	15,	33,	587,	"RO",	1,	1,	0,	0},
+	{"RESERVED_48_63"              ,	48,	16,	587,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	588,	"RO",	0,	1,	0ull,	0},
+	{"WMARK"                       ,	32,	32,	588,	"R/W",	0,	1,	4294967295ull,	0},
+	{"INTR"                        ,	0,	64,	589,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	64,	590,	"R/W",	0,	0,	0ull,	1ull},
+	{"SOP"                         ,	0,	64,	591,	"RO",	0,	1,	0ull,	0},
+	{"WQE_PCNT"                    ,	0,	7,	592,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PCNT"                    ,	7,	7,	592,	"RO",	0,	0,	0ull,	0ull},
+	{"PFIF_CNT"                    ,	14,	3,	592,	"RO",	0,	0,	0ull,	0ull},
+	{"WQEV_CNT"                    ,	17,	1,	592,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTV_CNT"                    ,	18,	1,	592,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	592,	"RAZ",	1,	1,	0,	0},
+	{"PASS"                        ,	0,	32,	593,	"R/W",	0,	1,	0ull,	0},
+	{"DROP"                        ,	32,	32,	593,	"R/W",	0,	1,	0ull,	0},
+	{"Q0_PCNT"                     ,	0,	32,	594,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	594,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	64,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"AVG_DLY"                     ,	0,	14,	596,	"R/W",	0,	1,	0ull,	0},
+	{"PRB_DLY"                     ,	14,	14,	596,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	596,	"RAZ",	1,	1,	0,	0},
+	{"PRB_CON"                     ,	0,	32,	597,	"R/W",	0,	1,	0ull,	0},
+	{"AVG_CON"                     ,	32,	8,	597,	"R/W",	0,	1,	0ull,	0},
+	{"NEW_CON"                     ,	40,	8,	597,	"R/W",	0,	1,	0ull,	0},
+	{"USE_PCNT"                    ,	48,	1,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	597,	"RAZ",	1,	1,	0,	0},
+	{"WGT0"                        ,	0,	8,	598,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT1"                        ,	8,	8,	598,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT2"                        ,	16,	8,	598,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT3"                        ,	24,	8,	598,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT4"                        ,	32,	8,	598,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT5"                        ,	40,	8,	598,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT6"                        ,	48,	8,	598,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT7"                        ,	56,	8,	598,	"R/W",	0,	0,	255ull,	255ull},
+	{"PAGE_CNT"                    ,	0,	25,	599,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	25,	6,	599,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	599,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	600,	"R/W",	1,	0,	0,	0ull},
+	{"PORT_QOS"                    ,	32,	9,	600,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_41_63"              ,	41,	23,	600,	"RAZ",	1,	1,	0,	0},
+	{"WQE_POOL"                    ,	0,	3,	601,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	601,	"RAZ",	1,	1,	0,	0},
+	{"MEM0"                        ,	0,	1,	602,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM1"                        ,	1,	1,	602,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	2,	1,	602,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	602,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	603,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	603,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	603,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	604,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	604,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	604,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	604,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	604,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	605,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	605,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	605,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	605,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	605,	"RAZ",	1,	1,	0,	0},
+	{"DISABLE"                     ,	0,	1,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	606,	"RAZ",	1,	1,	0,	0},
+	{"MAXDRAM"                     ,	4,	4,	606,	"R/W",	0,	0,	9ull,	9ull},
+	{"RESERVED_8_63"               ,	8,	56,	606,	"RAZ",	1,	1,	0,	0},
+	{"TDFFL"                       ,	0,	4,	607,	"RO",	1,	0,	0,	0ull},
+	{"VRTFL"                       ,	4,	4,	607,	"RO",	1,	0,	0,	0ull},
+	{"DUTRESFL"                    ,	8,	4,	607,	"RO",	1,	0,	0,	0ull},
+	{"IOCDATFL"                    ,	12,	4,	607,	"RO",	1,	0,	0,	0ull},
+	{"IOCCMDFL"                    ,	16,	4,	607,	"RO",	1,	0,	0,	0ull},
+	{"TDPFL"                       ,	20,	4,	607,	"RO",	1,	0,	0,	0ull},
+	{"XBFFL"                       ,	24,	4,	607,	"RO",	1,	0,	0,	0ull},
+	{"RBFFL"                       ,	28,	4,	607,	"RO",	1,	0,	0,	0ull},
+	{"DUTFL"                       ,	32,	32,	607,	"RO",	1,	0,	0,	0ull},
+	{"VBFFL"                       ,	0,	4,	608,	"RO",	1,	0,	0,	0ull},
+	{"RDFFL"                       ,	4,	1,	608,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_5_61"               ,	5,	57,	608,	"RAZ",	1,	1,	0,	0},
+	{"CLEAR_BIST"                  ,	62,	1,	608,	"R/W",	0,	0,	0ull,	0ull},
+	{"START_BIST"                  ,	63,	1,	608,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFL"                       ,	0,	8,	609,	"RO",	1,	0,	0,	0ull},
+	{"FBFFL"                       ,	8,	8,	609,	"RO",	1,	0,	0,	0ull},
+	{"SBFFL"                       ,	16,	8,	609,	"RO",	1,	0,	0,	0ull},
+	{"FBFRSPFL"                    ,	24,	8,	609,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	609,	"RAZ",	1,	1,	0,	0},
+	{"TAGFL"                       ,	0,	16,	610,	"RO",	1,	0,	0,	0ull},
+	{"LRUFL"                       ,	16,	1,	610,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	610,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	611,	"R/W",	1,	1,	0,	0},
+	{"DISIDXALIAS"                 ,	0,	1,	612,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISECC"                      ,	1,	1,	612,	"R/W",	0,	0,	0ull,	0ull},
+	{"VAB_THRESH"                  ,	2,	4,	612,	"R/W",	0,	0,	0ull,	0ull},
+	{"EF_CNT"                      ,	6,	7,	612,	"R/W",	0,	0,	0ull,	4ull},
+	{"EF_ENA"                      ,	13,	1,	612,	"R/W",	0,	0,	0ull,	1ull},
+	{"XMC_ARB_MODE"                ,	14,	1,	612,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSP_ARB_MODE"                ,	15,	1,	612,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXLFB"                      ,	16,	4,	612,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXVAB"                      ,	20,	4,	612,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISCCLK"                     ,	24,	1,	612,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFDBE"                     ,	25,	1,	612,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFSBE"                     ,	26,	1,	612,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISSTGL2I"                   ,	27,	1,	612,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDF_FAST"                    ,	28,	1,	612,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEPCMT"                      ,	29,	1,	612,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_63"              ,	30,	34,	612,	"RAZ",	1,	1,	0,	0},
+	{"VALID"                       ,	0,	1,	613,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_9"                ,	1,	9,	613,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	10,	28,	613,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	613,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	2,	614,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	614,	"RAZ",	1,	1,	0,	0},
+	{"WAYIDX"                      ,	4,	18,	614,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_22_49"              ,	22,	28,	614,	"RAZ",	1,	1,	0,	0},
+	{"SYN"                         ,	50,	10,	614,	"RO",	0,	0,	0ull,	0ull},
+	{"VSBE"                        ,	60,	1,	614,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VDBE"                        ,	61,	1,	614,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE"                         ,	62,	1,	614,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	63,	1,	614,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TYPE"                        ,	0,	2,	615,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_6"                ,	2,	5,	615,	"RAZ",	1,	1,	0,	0},
+	{"WAYIDX"                      ,	7,	15,	615,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_22_49"              ,	22,	28,	615,	"RAZ",	1,	1,	0,	0},
+	{"SYN"                         ,	50,	6,	615,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_60"              ,	56,	5,	615,	"RAZ",	1,	1,	0,	0},
+	{"NOWAY"                       ,	61,	1,	615,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE"                         ,	62,	1,	615,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	63,	1,	615,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TYPE"                        ,	0,	2,	616,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_49"               ,	2,	48,	616,	"RAZ",	1,	1,	0,	0},
+	{"VSYN"                        ,	50,	10,	616,	"RO",	0,	0,	0ull,	0ull},
+	{"VSBE"                        ,	60,	1,	616,	"RO",	0,	0,	0ull,	0ull},
+	{"VDBE"                        ,	61,	1,	616,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	616,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	38,	617,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_47"              ,	38,	10,	617,	"RAZ",	1,	1,	0,	0},
+	{"SID"                         ,	48,	6,	617,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_54_57"              ,	54,	4,	617,	"RAZ",	1,	1,	0,	0},
+	{"CMD"                         ,	58,	6,	617,	"RO",	0,	1,	0ull,	0},
+	{"HOLERD"                      ,	0,	1,	618,	"R/W",	0,	0,	0ull,	1ull},
+	{"HOLEWR"                      ,	1,	1,	618,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTWR"                       ,	2,	1,	618,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTIDRNG"                    ,	3,	1,	618,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTADRNG"                    ,	4,	1,	618,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTPE"                       ,	5,	1,	618,	"R/W",	0,	0,	0ull,	1ull},
+	{"BIGWR"                       ,	6,	1,	618,	"R/W",	0,	0,	0ull,	1ull},
+	{"BIGRD"                       ,	7,	1,	618,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_8_63"               ,	8,	56,	618,	"RAZ",	1,	1,	0,	0},
+	{"HOLERD"                      ,	0,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HOLEWR"                      ,	1,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTWR"                       ,	2,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTIDRNG"                    ,	3,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTADRNG"                    ,	4,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTPE"                       ,	5,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BIGWR"                       ,	6,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BIGRD"                       ,	7,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	619,	"RAZ",	1,	1,	0,	0},
+	{"TAD0"                        ,	16,	1,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"TAD1"                        ,	17,	1,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"TAD2"                        ,	18,	1,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"TAD3"                        ,	19,	1,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	619,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	620,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	621,	"R/W",	0,	1,	0ull,	0},
+	{"LVL"                         ,	0,	3,	622,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	622,	"RAZ",	1,	1,	0,	0},
+	{"DWBLVL"                      ,	4,	3,	622,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	622,	"RAZ",	1,	1,	0,	0},
+	{"LVL"                         ,	0,	3,	623,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	623,	"RAZ",	1,	1,	0,	0},
+	{"WGT0"                        ,	0,	8,	624,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT1"                        ,	8,	8,	624,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT2"                        ,	16,	8,	624,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT3"                        ,	24,	8,	624,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT4"                        ,	32,	8,	624,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT5"                        ,	40,	8,	624,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT6"                        ,	48,	8,	624,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT7"                        ,	56,	8,	624,	"R/W",	0,	0,	255ull,	255ull},
+	{"COUNT"                       ,	0,	64,	625,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	626,	"R/W",	0,	1,	0ull,	0},
+	{"OW0ECC"                      ,	0,	10,	627,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	627,	"RAZ",	1,	1,	0,	0},
+	{"OW1ECC"                      ,	16,	10,	627,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_31"              ,	26,	6,	627,	"RAZ",	1,	1,	0,	0},
+	{"OW2ECC"                      ,	32,	10,	627,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	627,	"RAZ",	1,	1,	0,	0},
+	{"OW3ECC"                      ,	48,	10,	627,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	627,	"RAZ",	1,	1,	0,	0},
+	{"OW4ECC"                      ,	0,	10,	628,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	628,	"RAZ",	1,	1,	0,	0},
+	{"OW5ECC"                      ,	16,	10,	628,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_31"              ,	26,	6,	628,	"RAZ",	1,	1,	0,	0},
+	{"OW6ECC"                      ,	32,	10,	628,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	628,	"RAZ",	1,	1,	0,	0},
+	{"OW7ECC"                      ,	48,	10,	628,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	628,	"RAZ",	1,	1,	0,	0},
+	{"L2DSBE"                      ,	0,	1,	629,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2DDBE"                      ,	1,	1,	629,	"R/W",	0,	0,	0ull,	1ull},
+	{"TAGSBE"                      ,	2,	1,	629,	"R/W",	0,	0,	0ull,	1ull},
+	{"TAGDBE"                      ,	3,	1,	629,	"R/W",	0,	0,	0ull,	1ull},
+	{"VBFSBE"                      ,	4,	1,	629,	"R/W",	0,	0,	0ull,	1ull},
+	{"VBFDBE"                      ,	5,	1,	629,	"R/W",	0,	0,	0ull,	1ull},
+	{"NOWAY"                       ,	6,	1,	629,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDDISLMC"                    ,	7,	1,	629,	"R/W",	0,	0,	0ull,	1ull},
+	{"WRDISLMC"                    ,	8,	1,	629,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	629,	"RAZ",	1,	1,	0,	0},
+	{"L2DSBE"                      ,	0,	1,	630,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"L2DDBE"                      ,	1,	1,	630,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"TAGSBE"                      ,	2,	1,	630,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"TAGDBE"                      ,	3,	1,	630,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"VBFSBE"                      ,	4,	1,	630,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"VBFDBE"                      ,	5,	1,	630,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"NOWAY"                       ,	6,	1,	630,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDDISLMC"                    ,	7,	1,	630,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WRDISLMC"                    ,	8,	1,	630,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	630,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	631,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	632,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	633,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	634,	"R/W",	0,	1,	0ull,	0},
+	{"CNT0SEL"                     ,	0,	8,	635,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT1SEL"                     ,	8,	8,	635,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT2SEL"                     ,	16,	8,	635,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT3SEL"                     ,	24,	8,	635,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	635,	"RAZ",	1,	1,	0,	0},
+	{"LOCK"                        ,	0,	1,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIRTY"                       ,	1,	1,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"VALID"                       ,	2,	1,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE"                         ,	3,	1,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_16"               ,	4,	13,	636,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	17,	19,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_39"              ,	36,	4,	636,	"RAZ",	1,	1,	0,	0},
+	{"ECC"                         ,	40,	6,	636,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_46_63"              ,	46,	18,	636,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	637,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MASK"                        ,	0,	2,	638,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	638,	"RAZ",	1,	1,	0,	0},
+	{"DWB"                         ,	0,	1,	639,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	1,	1,	639,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	639,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	32,	640,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	640,	"RAZ",	1,	1,	0,	0},
+	{"ID"                          ,	0,	6,	641,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	641,	"RAZ",	1,	1,	0,	0},
+	{"DWBID"                       ,	8,	6,	641,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	641,	"RAZ",	1,	1,	0,	0},
+	{"ID"                          ,	0,	6,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	642,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	1,	643,	"R/W",	0,	0,	0ull,	1ull},
+	{"NUMID"                       ,	1,	3,	643,	"R/W",	0,	0,	5ull,	5ull},
+	{"MEMSZ"                       ,	4,	3,	643,	"R/W",	0,	0,	5ull,	5ull},
+	{"RESERVED_7_7"                ,	7,	1,	643,	"RAZ",	1,	1,	0,	0},
+	{"OOBERR"                      ,	8,	1,	643,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	643,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	32,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"PARITY"                      ,	32,	4,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	644,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	645,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	646,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	647,	"R/W",	0,	1,	0ull,	0},
+	{"ADDR"                        ,	0,	38,	648,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_38_56"              ,	38,	19,	648,	"RAZ",	1,	1,	0,	0},
+	{"CMD"                         ,	57,	6,	648,	"R/W",	1,	1,	0,	0},
+	{"INUSE"                       ,	63,	1,	648,	"RO",	0,	0,	0ull,	0ull},
+	{"COUNT"                       ,	0,	64,	649,	"R/W",	0,	1,	0ull,	0},
+	{"PRBS"                        ,	0,	32,	650,	"R/W",	1,	1,	0,	0},
+	{"PROG"                        ,	32,	8,	650,	"R/W",	1,	1,	0,	0},
+	{"SEL"                         ,	40,	1,	650,	"R/W",	1,	1,	0,	0},
+	{"EN"                          ,	41,	1,	650,	"R/W",	1,	1,	0,	0},
+	{"SKEW_ON"                     ,	42,	1,	650,	"R/W",	1,	1,	0,	0},
+	{"DR"                          ,	43,	1,	650,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_44_63"              ,	44,	20,	650,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	651,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	8,	652,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	652,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	653,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	8,	654,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	654,	"R/W",	1,	1,	0,	0},
+	{"CKE_MASK"                    ,	0,	2,	655,	"R/W",	1,	1,	0,	0},
+	{"CS0_N_MASK"                  ,	2,	2,	655,	"R/W",	1,	1,	0,	0},
+	{"CS1_N_MASK"                  ,	4,	2,	655,	"R/W",	1,	1,	0,	0},
+	{"ODT0_MASK"                   ,	6,	2,	655,	"R/W",	1,	1,	0,	0},
+	{"ODT1_MASK"                   ,	8,	2,	655,	"R/W",	1,	1,	0,	0},
+	{"RAS_N_MASK"                  ,	10,	1,	655,	"R/W",	1,	1,	0,	0},
+	{"CAS_N_MASK"                  ,	11,	1,	655,	"R/W",	1,	1,	0,	0},
+	{"WE_N_MASK"                   ,	12,	1,	655,	"R/W",	1,	1,	0,	0},
+	{"BA_MASK"                     ,	13,	3,	655,	"R/W",	1,	1,	0,	0},
+	{"A_MASK"                      ,	16,	16,	655,	"R/W",	1,	1,	0,	0},
+	{"RESET_N_MASK"                ,	32,	1,	655,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_33_63"              ,	33,	31,	655,	"R/W",	1,	1,	0,	0},
+	{"DQX_CTL"                     ,	0,	4,	656,	"R/W",	0,	1,	4ull,	0},
+	{"CK_CTL"                      ,	4,	4,	656,	"R/W",	0,	1,	4ull,	0},
+	{"CMD_CTL"                     ,	8,	4,	656,	"R/W",	0,	1,	4ull,	0},
+	{"RODT_CTL"                    ,	12,	4,	656,	"R/W",	0,	1,	0ull,	0},
+	{"NTUNE"                       ,	16,	4,	656,	"R/W",	0,	1,	0ull,	0},
+	{"PTUNE"                       ,	20,	4,	656,	"R/W",	0,	1,	0ull,	0},
+	{"BYP"                         ,	24,	1,	656,	"R/W",	0,	1,	0ull,	0},
+	{"M180"                        ,	25,	1,	656,	"R/W",	0,	1,	0ull,	0},
+	{"DDR__NTUNE"                  ,	26,	4,	656,	"RO",	1,	1,	0,	0},
+	{"DDR__PTUNE"                  ,	30,	4,	656,	"RO",	1,	1,	0,	0},
+	{"RESERVED_34_63"              ,	34,	30,	656,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	657,	"WR0",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	657,	"R/W",	0,	0,	0ull,	1ull},
+	{"ROW_LSB"                     ,	2,	3,	657,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	657,	"R/W",	0,	1,	5ull,	0},
+	{"IDLEPOWER"                   ,	9,	3,	657,	"R/W",	0,	0,	0ull,	6ull},
+	{"FORCEWRITE"                  ,	12,	4,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ADR"                     ,	16,	1,	657,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESET"                       ,	17,	1,	657,	"R/W",	0,	1,	0ull,	0},
+	{"REF_ZQCS_INT"                ,	18,	19,	657,	"R/W",	1,	1,	0,	0},
+	{"SEQUENCE"                    ,	37,	3,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"EARLY_DQX"                   ,	40,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"SREF_WITH_DLL"               ,	41,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"RANK_ENA"                    ,	42,	1,	657,	"R/W",	0,	1,	0ull,	0},
+	{"RANKMASK"                    ,	43,	4,	657,	"R/W",	0,	1,	0ull,	0},
+	{"MIRRMASK"                    ,	47,	4,	657,	"R/W",	0,	1,	0ull,	0},
+	{"INIT_STATUS"                 ,	51,	4,	657,	"R/W1",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D0_R0"          ,	55,	1,	657,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D0_R1"          ,	56,	1,	657,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D1_R0"          ,	57,	1,	657,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D1_R1"          ,	58,	1,	657,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_59_63"              ,	59,	5,	657,	"RAZ",	1,	1,	0,	0},
+	{"RDIMM_ENA"                   ,	0,	1,	658,	"R/W",	0,	1,	0ull,	0},
+	{"BWCNT"                       ,	1,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	2,	1,	658,	"R/W",	0,	0,	0ull,	1ull},
+	{"POCAS"                       ,	3,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPRCH2"                      ,	4,	2,	658,	"R/W",	0,	0,	0ull,	1ull},
+	{"THROTTLE_RD"                 ,	6,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"THROTTLE_WR"                 ,	7,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_RD"                  ,	8,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_WR"                  ,	9,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"ELEV_PRIO_DIS"               ,	10,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"NXM_WRITE_EN"                ,	11,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	12,	4,	658,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	16,	1,	658,	"R/W",	0,	0,	0ull,	1ull},
+	{"AUTO_DCLKDIS"                ,	17,	1,	658,	"R/W",	0,	0,	0ull,	1ull},
+	{"INT_ZQCS_DIS"                ,	18,	1,	658,	"R/W",	0,	0,	1ull,	0ull},
+	{"EXT_ZQCS_DIS"                ,	19,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"BPRCH"                       ,	20,	2,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"WODT_BPRCH"                  ,	22,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_BPRCH"                  ,	23,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRM_MAX"                     ,	24,	5,	658,	"R/W",	0,	0,	31ull,	31ull},
+	{"CRM_THR"                     ,	29,	5,	658,	"R/W",	0,	0,	0ull,	8ull},
+	{"CRM_CNT"                     ,	34,	5,	658,	"RO",	0,	0,	0ull,	0ull},
+	{"THRMAX"                      ,	39,	4,	658,	"R/W",	0,	0,	15ull,	2ull},
+	{"PERSUB"                      ,	43,	8,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"THRCNT"                      ,	51,	12,	658,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_63_63"              ,	63,	1,	658,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT"                     ,	0,	64,	659,	"RO",	0,	1,	0ull,	0},
+	{"CLKF"                        ,	0,	7,	660,	"R/W",	0,	1,	48ull,	0},
+	{"RESET_N"                     ,	7,	1,	660,	"R/W",	0,	0,	0ull,	1ull},
+	{"CPB"                         ,	8,	3,	660,	"R/W",	0,	0,	0ull,	1ull},
+	{"CPS"                         ,	11,	3,	660,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIFFAMP"                     ,	14,	4,	660,	"R/W",	0,	0,	0ull,	1ull},
+	{"DDR_PS_EN"                   ,	18,	3,	660,	"R/W",	0,	1,	2ull,	0},
+	{"DDR_DIV_RESET"               ,	21,	1,	660,	"R/W",	0,	0,	1ull,	0ull},
+	{"DFM_PS_EN"                   ,	22,	3,	660,	"R/W",	0,	1,	2ull,	0},
+	{"DFM_DIV_RESET"               ,	25,	1,	660,	"R/W",	0,	0,	1ull,	0ull},
+	{"JTG_TEST_MODE"               ,	26,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	660,	"RAZ",	1,	1,	0,	0},
+	{"RC0"                         ,	0,	4,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC1"                         ,	4,	4,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC2"                         ,	8,	4,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC3"                         ,	12,	4,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC4"                         ,	16,	4,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC5"                         ,	20,	4,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC6"                         ,	24,	4,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC7"                         ,	28,	4,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC8"                         ,	32,	4,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC9"                         ,	36,	4,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC10"                        ,	40,	4,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC11"                        ,	44,	4,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC12"                        ,	48,	4,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC13"                        ,	52,	4,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC14"                        ,	56,	4,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC15"                        ,	60,	4,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIMM0_WMASK"                 ,	0,	16,	662,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"DIMM1_WMASK"                 ,	16,	16,	662,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"TCWS"                        ,	32,	13,	662,	"R/W",	0,	0,	1248ull,	1248ull},
+	{"PARITY"                      ,	45,	1,	662,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	662,	"RAZ",	1,	1,	0,	0},
+	{"BYP_SETTING"                 ,	0,	8,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYP_SEL"                     ,	8,	4,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"QUAD_DLL_ENA"                ,	12,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	13,	1,	663,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLL_BRINGUP"                 ,	14,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTF_EN"                     ,	15,	1,	663,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	663,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	6,	664,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYTE_SEL"                    ,	6,	4,	664,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE_SEL"                    ,	10,	2,	664,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOAD_OFFSET"                 ,	12,	1,	664,	"WR0",	0,	0,	0ull,	0ull},
+	{"OFFSET_ENA"                  ,	13,	1,	664,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYTE_SEL"              ,	14,	4,	664,	"R/W",	0,	0,	1ull,	1ull},
+	{"DLL_MODE"                    ,	18,	1,	664,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINE_TUNE_MODE"              ,	19,	1,	664,	"R/W",	0,	0,	0ull,	1ull},
+	{"DLL90_SETTING"               ,	20,	8,	664,	"RO",	1,	1,	0,	0},
+	{"DLL_FAST"                    ,	28,	1,	664,	"RO",	1,	1,	0,	0},
+	{"DCLK90_BYP_SETTING"          ,	29,	8,	664,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCLK90_BYP_SEL"              ,	37,	1,	664,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCLK90_RECAL_DIS"            ,	38,	1,	664,	"R/W",	0,	0,	0ull,	1ull},
+	{"DDR_90_DLY_BYP"              ,	39,	1,	664,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCLK90_FWD"                  ,	40,	1,	664,	"WR0",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_63"              ,	41,	23,	664,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	665,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	665,	"RAZ",	1,	1,	0,	0},
+	{"ROW_LSB"                     ,	16,	3,	665,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_19_63"              ,	19,	45,	665,	"RAZ",	1,	1,	0,	0},
+	{"MRDSYN0"                     ,	0,	8,	666,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN1"                     ,	8,	8,	666,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN2"                     ,	16,	8,	666,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN3"                     ,	24,	8,	666,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	666,	"RAZ",	1,	1,	0,	0},
+	{"FCOL"                        ,	0,	14,	667,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	14,	16,	667,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	30,	3,	667,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	33,	1,	667,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	34,	2,	667,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	667,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT"                      ,	0,	64,	668,	"RO",	0,	1,	1ull,	0},
+	{"NXM_WR_ERR"                  ,	0,	1,	669,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SEC_ERR"                     ,	1,	4,	669,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	5,	4,	669,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	669,	"RAZ",	1,	1,	0,	0},
+	{"INTR_NXM_WR_ENA"             ,	0,	1,	670,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_SEC_ENA"                ,	1,	1,	670,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_DED_ENA"                ,	2,	1,	670,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	670,	"RAZ",	1,	1,	0,	0},
+	{"CWL"                         ,	0,	3,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPRLOC"                      ,	3,	2,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPR"                         ,	5,	1,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL"                         ,	6,	1,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"AL"                          ,	7,	2,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"WLEV"                        ,	9,	1,	671,	"RO",	0,	0,	0ull,	0ull},
+	{"TDQS"                        ,	10,	1,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOFF"                        ,	11,	1,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"BL"                          ,	12,	2,	671,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	14,	4,	671,	"R/W",	0,	0,	2ull,	2ull},
+	{"RBT"                         ,	18,	1,	671,	"RO",	0,	0,	1ull,	1ull},
+	{"TM"                          ,	19,	1,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLR"                        ,	20,	1,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRP"                         ,	21,	3,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPD"                         ,	24,	1,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	671,	"RAZ",	1,	1,	0,	0},
+	{"PASR_00"                     ,	0,	3,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_00"                      ,	3,	1,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_00"                      ,	4,	1,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_00"                   ,	5,	2,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_00"                      ,	7,	2,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_00"                  ,	9,	3,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_01"                     ,	12,	3,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_01"                      ,	15,	1,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_01"                      ,	16,	1,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_01"                   ,	17,	2,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_01"                      ,	19,	2,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_01"                  ,	21,	3,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_10"                     ,	24,	3,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_10"                      ,	27,	1,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_10"                      ,	28,	1,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_10"                   ,	29,	2,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_10"                      ,	31,	2,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_10"                  ,	33,	3,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_11"                     ,	36,	3,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_11"                      ,	39,	1,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_11"                      ,	40,	1,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_11"                   ,	41,	2,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_11"                      ,	43,	2,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_11"                  ,	45,	3,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	672,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	673,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D0_R0"               ,	8,	4,	673,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D0_R1"               ,	12,	4,	673,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D1_R0"               ,	16,	4,	673,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D1_R1"               ,	20,	4,	673,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D2_R0"               ,	24,	4,	673,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D2_R1"               ,	28,	4,	673,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D3_R0"               ,	32,	4,	673,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D3_R1"               ,	36,	4,	673,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	673,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT"                      ,	0,	64,	674,	"RO",	0,	1,	1ull,	0},
+	{"TS_STAGGER"                  ,	0,	1,	675,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK_POS"                ,	1,	1,	675,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK"                    ,	2,	1,	675,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT0"                  ,	3,	4,	675,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE0"                    ,	7,	1,	675,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT1"                  ,	8,	4,	675,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE1"                    ,	12,	1,	675,	"R/W",	0,	1,	0ull,	0},
+	{"LV_MODE"                     ,	13,	1,	675,	"R/W",	0,	1,	0ull,	0},
+	{"RX_ALWAYS_ON"                ,	14,	1,	675,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	675,	"RAZ",	1,	1,	0,	0},
+	{"DDR3RST"                     ,	0,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PWARM"                   ,	1,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSOFT"                   ,	2,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSV"                     ,	3,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	676,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	677,	"R/W",	0,	1,	0ull,	0},
+	{"OFFSET"                      ,	4,	4,	677,	"R/W",	0,	0,	2ull,	2ull},
+	{"OFFSET_EN"                   ,	8,	1,	677,	"R/W",	0,	0,	1ull,	1ull},
+	{"OR_DIS"                      ,	9,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	10,	8,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_0"              ,	18,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_1"              ,	19,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_2"              ,	20,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_3"              ,	21,	1,	677,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	677,	"RAZ",	1,	1,	0,	0},
+	{"BITMASK"                     ,	0,	64,	678,	"RO",	0,	0,	0ull,	0ull},
+	{"BYTE0"                       ,	0,	6,	679,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	6,	6,	679,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE2"                       ,	12,	6,	679,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE3"                       ,	18,	6,	679,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE4"                       ,	24,	6,	679,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE5"                       ,	30,	6,	679,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE6"                       ,	36,	6,	679,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE7"                       ,	42,	6,	679,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE8"                       ,	48,	6,	679,	"R/W",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	54,	2,	679,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	679,	"RAZ",	1,	1,	0,	0},
+	{"RODT_D0_R0"                  ,	0,	8,	680,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D0_R1"                  ,	8,	8,	680,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D1_R0"                  ,	16,	8,	680,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D1_R1"                  ,	24,	8,	680,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D2_R0"                  ,	32,	8,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D2_R1"                  ,	40,	8,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R0"                  ,	48,	8,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R1"                  ,	56,	8,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"R2R_INIT"                    ,	0,	6,	681,	"R/W",	0,	1,	1ull,	0},
+	{"R2W_INIT"                    ,	6,	6,	681,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_INIT"                    ,	12,	6,	681,	"R/W",	0,	1,	9ull,	0},
+	{"W2W_INIT"                    ,	18,	6,	681,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	681,	"RAZ",	1,	1,	0,	0},
+	{"R2R_XRANK_INIT"              ,	0,	6,	682,	"R/W",	0,	1,	3ull,	0},
+	{"R2W_XRANK_INIT"              ,	6,	6,	682,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_XRANK_INIT"              ,	12,	6,	682,	"R/W",	0,	1,	4ull,	0},
+	{"W2W_XRANK_INIT"              ,	18,	6,	682,	"R/W",	0,	1,	5ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	682,	"RAZ",	1,	1,	0,	0},
+	{"R2R_XDIMM_INIT"              ,	0,	6,	683,	"R/W",	0,	1,	4ull,	0},
+	{"R2W_XDIMM_INIT"              ,	6,	6,	683,	"R/W",	0,	1,	7ull,	0},
+	{"W2R_XDIMM_INIT"              ,	12,	6,	683,	"R/W",	0,	1,	4ull,	0},
+	{"W2W_XDIMM_INIT"              ,	18,	6,	683,	"R/W",	0,	1,	6ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	683,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_9"                ,	0,	10,	684,	"RAZ",	1,	1,	0,	0},
+	{"TZQCS"                       ,	10,	4,	684,	"R/W",	0,	0,	4ull,	4ull},
+	{"TCKE"                        ,	14,	4,	684,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPR"                        ,	18,	4,	684,	"R/W",	0,	0,	5ull,	5ull},
+	{"TMRD"                        ,	22,	4,	684,	"R/W",	0,	0,	4ull,	4ull},
+	{"TMOD"                        ,	26,	4,	684,	"R/W",	0,	0,	12ull,	12ull},
+	{"TDLLK"                       ,	30,	4,	684,	"R/W",	0,	0,	2ull,	2ull},
+	{"TZQINIT"                     ,	34,	4,	684,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	38,	4,	684,	"R/W",	0,	0,	6ull,	6ull},
+	{"TCKSRE"                      ,	42,	4,	684,	"R/W",	0,	0,	5ull,	5ull},
+	{"TRP_EXT"                     ,	46,	1,	684,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	684,	"RAZ",	1,	1,	0,	0},
+	{"TMPRR"                       ,	0,	4,	685,	"R/W",	0,	0,	1ull,	1ull},
+	{"TRAS"                        ,	4,	5,	685,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	9,	4,	685,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	13,	4,	685,	"R/W",	0,	0,	2ull,	3ull},
+	{"TRFC"                        ,	17,	5,	685,	"R/W",	0,	0,	6ull,	7ull},
+	{"TRRD"                        ,	22,	3,	685,	"R/W",	0,	0,	2ull,	2ull},
+	{"TXP"                         ,	25,	3,	685,	"R/W",	0,	0,	3ull,	3ull},
+	{"TWLMRD"                      ,	28,	4,	685,	"R/W",	0,	0,	10ull,	10ull},
+	{"TWLDQSEN"                    ,	32,	4,	685,	"R/W",	0,	0,	7ull,	7ull},
+	{"TFAW"                        ,	36,	5,	685,	"R/W",	0,	0,	0ull,	9ull},
+	{"TXPDLL"                      ,	41,	5,	685,	"R/W",	0,	0,	0ull,	10ull},
+	{"TRAS_EXT"                    ,	46,	1,	685,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	685,	"RAZ",	1,	1,	0,	0},
+	{"TRESET"                      ,	0,	1,	686,	"R/W",	0,	1,	1ull,	0},
+	{"RCLK_CNT"                    ,	1,	32,	686,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	686,	"RAZ",	1,	1,	0,	0},
+	{"RING_CNT"                    ,	0,	32,	687,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	687,	"RAZ",	1,	1,	0,	0},
+	{"LANEMASK"                    ,	0,	9,	688,	"R/W",	0,	1,	0ull,	0},
+	{"SSET"                        ,	9,	1,	688,	"R/W",	0,	1,	0ull,	0},
+	{"OR_DIS"                      ,	10,	1,	688,	"R/W",	0,	1,	0ull,	0},
+	{"BITMASK"                     ,	11,	8,	688,	"R/W",	0,	1,	0ull,	0},
+	{"RTT_NOM"                     ,	19,	3,	688,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	688,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	689,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	4,	8,	689,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	689,	"RAZ",	1,	1,	0,	0},
+	{"BYTE0"                       ,	0,	5,	690,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	5,	5,	690,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE2"                       ,	10,	5,	690,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE3"                       ,	15,	5,	690,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE4"                       ,	20,	5,	690,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE5"                       ,	25,	5,	690,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE6"                       ,	30,	5,	690,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE7"                       ,	35,	5,	690,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE8"                       ,	40,	5,	690,	"R/W",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	45,	2,	690,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_47_63"              ,	47,	17,	690,	"RAZ",	1,	1,	0,	0},
+	{"WODT_D0_R0"                  ,	0,	8,	691,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D0_R1"                  ,	8,	8,	691,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D1_R0"                  ,	16,	8,	691,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D1_R1"                  ,	24,	8,	691,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D2_R0"                  ,	32,	8,	691,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D2_R1"                  ,	40,	8,	691,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D3_R0"                  ,	48,	8,	691,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D3_R1"                  ,	56,	8,	691,	"R/W",	0,	0,	255ull,	0ull},
+	{"STAT"                        ,	0,	10,	692,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	692,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	693,	"R/W",	1,	1,	0,	0},
+	{"PCTL"                        ,	6,	6,	693,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	693,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	694,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	694,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	694,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	694,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	694,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	694,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	694,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	694,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	694,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	694,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	695,	"R/W1C",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	695,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	695,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	696,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	696,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	696,	"RAZ",	1,	1,	0,	0},
+	{"DMARQ"                       ,	0,	6,	697,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_S"                     ,	6,	6,	697,	"R/W",	0,	1,	63ull,	0},
+	{"OE_A"                        ,	12,	6,	697,	"R/W",	0,	1,	63ull,	0},
+	{"OE_N"                        ,	18,	6,	697,	"R/W",	0,	1,	63ull,	0},
+	{"WE_A"                        ,	24,	6,	697,	"R/W",	0,	1,	63ull,	0},
+	{"WE_N"                        ,	30,	6,	697,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_H"                     ,	36,	6,	697,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	42,	6,	697,	"R/W",	0,	1,	63ull,	0},
+	{"RESERVED_48_54"              ,	48,	7,	697,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	55,	1,	697,	"R/W",	0,	1,	0ull,	0},
+	{"DDR"                         ,	56,	1,	697,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	57,	3,	697,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	60,	2,	697,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ_PI"                    ,	62,	1,	697,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK_PI"                    ,	63,	1,	697,	"R/W",	0,	1,	0ull,	0},
+	{"ADR_ERR"                     ,	0,	1,	698,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WAIT_ERR"                    ,	1,	1,	698,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	698,	"RAZ",	1,	1,	0,	0},
+	{"ADR_INT"                     ,	0,	1,	699,	"R/W",	0,	1,	0ull,	0},
+	{"WAIT_INT"                    ,	1,	1,	699,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	699,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	700,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	3,	5,	700,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	700,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	701,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	3,	25,	701,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_30"              ,	28,	3,	701,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	31,	1,	701,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	701,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	702,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	703,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	8,	1,	703,	"RO",	1,	1,	0,	0},
+	{"TERM"                        ,	9,	2,	703,	"RO",	1,	1,	0,	0},
+	{"DMACK_P0"                    ,	11,	1,	703,	"RO",	1,	1,	0,	0},
+	{"DMACK_P1"                    ,	12,	1,	703,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_13"              ,	13,	1,	703,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	14,	1,	703,	"RO",	1,	1,	0,	0},
+	{"ALE"                         ,	15,	1,	703,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	703,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	16,	704,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	16,	12,	704,	"R/W",	0,	1,	0ull,	0},
+	{"WIDTH"                       ,	28,	1,	704,	"R/W",	0,	1,	0ull,	0},
+	{"ALE"                         ,	29,	1,	704,	"R/W",	0,	1,	0ull,	0},
+	{"ORBIT"                       ,	30,	1,	704,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	31,	1,	704,	"R/W",	0,	1,	0ull,	0},
+	{"OE_EXT"                      ,	32,	2,	704,	"R/W",	0,	1,	0ull,	0},
+	{"WE_EXT"                      ,	34,	2,	704,	"R/W",	0,	1,	0ull,	0},
+	{"SAM"                         ,	36,	1,	704,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	37,	3,	704,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	40,	2,	704,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK"                       ,	42,	2,	704,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	704,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	6,	705,	"R/W",	0,	1,	63ull,	0},
+	{"CE"                          ,	6,	6,	705,	"R/W",	0,	1,	63ull,	0},
+	{"OE"                          ,	12,	6,	705,	"R/W",	0,	1,	63ull,	0},
+	{"WE"                          ,	18,	6,	705,	"R/W",	0,	1,	63ull,	0},
+	{"RD_HLD"                      ,	24,	6,	705,	"R/W",	0,	1,	63ull,	0},
+	{"WR_HLD"                      ,	30,	6,	705,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	36,	6,	705,	"R/W",	0,	1,	63ull,	0},
+	{"WAIT"                        ,	42,	6,	705,	"R/W",	0,	1,	63ull,	0},
+	{"PAGE"                        ,	48,	6,	705,	"R/W",	0,	1,	63ull,	0},
+	{"ALE"                         ,	54,	6,	705,	"R/W",	0,	1,	63ull,	0},
+	{"PAGES"                       ,	60,	2,	705,	"R/W",	0,	1,	0ull,	0},
+	{"WAITM"                       ,	62,	1,	705,	"R/W",	0,	1,	0ull,	0},
+	{"PAGEM"                       ,	63,	1,	705,	"R/W",	0,	1,	0ull,	0},
+	{"FIF_THR"                     ,	0,	6,	706,	"R/W",	0,	0,	25ull,	25ull},
+	{"RESERVED_6_7"                ,	6,	2,	706,	"RAZ",	1,	1,	0,	0},
+	{"FIF_CNT"                     ,	8,	6,	706,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	706,	"RAZ",	1,	1,	0,	0},
+	{"DMA_THR"                     ,	16,	6,	706,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_63"              ,	22,	42,	706,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	707,	"R/W",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	708,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	708,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	709,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	709,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	710,	"RO",	1,	1,	0,	0},
+	{"CHIP_ID"                     ,	16,	8,	710,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_25"              ,	24,	2,	710,	"RO",	1,	1,	0,	0},
+	{"NOCRYPTO"                    ,	26,	1,	710,	"RO",	1,	1,	0,	0},
+	{"NOMUL"                       ,	27,	1,	710,	"RO",	1,	1,	0,	0},
+	{"NODFA_CP2"                   ,	28,	1,	710,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_31"              ,	29,	3,	710,	"RO",	1,	1,	0,	0},
+	{"RAID_EN"                     ,	32,	1,	710,	"RO",	1,	1,	0,	0},
+	{"FUS318"                      ,	33,	1,	710,	"RO",	1,	1,	0,	0},
+	{"DORM_CRYPTO"                 ,	34,	1,	710,	"RO",	1,	1,	0,	0},
+	{"POWER_LIMIT"                 ,	35,	2,	710,	"RO",	1,	1,	0,	0},
+	{"RESERVED_37_63"              ,	37,	27,	710,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	711,	"RAZ",	1,	1,	0,	0},
+	{"NODFA_DTE"                   ,	24,	1,	711,	"RO",	1,	1,	0,	0},
+	{"NOZIP"                       ,	25,	1,	711,	"RO",	1,	1,	0,	0},
+	{"EFUS_IGN"                    ,	26,	1,	711,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK"                    ,	27,	1,	711,	"RO",	1,	1,	0,	0},
+	{"BAR2_EN"                     ,	28,	1,	711,	"RO",	1,	1,	0,	0},
+	{"ZIP_INFO"                    ,	29,	2,	711,	"RO",	1,	1,	0,	0},
+	{"RESERVED_31_31"              ,	31,	1,	711,	"RAZ",	1,	1,	0,	0},
+	{"L2C_CRIP"                    ,	32,	3,	711,	"RO",	1,	1,	0,	0},
+	{"PLL_HALF_DIS"                ,	35,	1,	711,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK_MAN"                ,	36,	1,	711,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK_RSV"                ,	37,	1,	711,	"RO",	1,	1,	0,	0},
+	{"EMA"                         ,	38,	2,	711,	"RO",	1,	1,	0,	0},
+	{"RESERVED_40_40"              ,	40,	1,	711,	"RAZ",	1,	1,	0,	0},
+	{"DFA_INFO_CLM"                ,	41,	4,	711,	"RO",	1,	1,	0,	0},
+	{"DFA_INFO_DTE"                ,	45,	3,	711,	"RO",	1,	1,	0,	0},
+	{"PLL_CTL"                     ,	48,	10,	711,	"RO",	1,	1,	0,	0},
+	{"RESERVED_58_63"              ,	58,	6,	711,	"RAZ",	1,	1,	0,	0},
+	{"EMA"                         ,	0,	3,	712,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_3_3"                ,	3,	1,	712,	"RAZ",	1,	1,	0,	0},
+	{"EFF_EMA"                     ,	4,	3,	712,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_7_63"               ,	7,	57,	712,	"RAZ",	1,	1,	0,	0},
+	{"PDF"                         ,	0,	64,	713,	"RO",	1,	1,	0,	0},
+	{"FBSLIP"                      ,	0,	1,	714,	"RAZ",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	714,	"RAZ",	0,	1,	0ull,	0},
+	{"PNR_COUT_SEL"                ,	2,	2,	714,	"R/W",	0,	1,	0ull,	0},
+	{"PNR_COUT_RST"                ,	4,	1,	714,	"R/W",	0,	1,	0ull,	0},
+	{"C_COUT_SEL"                  ,	5,	2,	714,	"R/W",	0,	1,	0ull,	0},
+	{"C_COUT_RST"                  ,	7,	1,	714,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_31"               ,	8,	24,	714,	"RAZ",	1,	1,	0,	0},
+	{"RCLK_ALIGN_L"                ,	32,	8,	714,	"RO",	1,	1,	0,	0},
+	{"RCLK_ALIGN_R"                ,	40,	8,	714,	"RO",	1,	1,	0,	0},
+	{"RESERVED_48_63"              ,	48,	16,	714,	"RO",	1,	1,	0,	0},
+	{"PROG"                        ,	0,	1,	715,	"R/W",	1,	1,	0,	0},
+	{"SOFT"                        ,	1,	1,	715,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	715,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	6,	716,	"R/W",	0,	1,	1ull,	0},
+	{"SCLK_HI"                     ,	6,	15,	716,	"R/W",	0,	1,	5000ull,	0},
+	{"SCLK_LO"                     ,	21,	4,	716,	"R/W",	0,	1,	1ull,	0},
+	{"OUT"                         ,	25,	7,	716,	"R/W",	0,	1,	1ull,	0},
+	{"PROG_PIN"                    ,	32,	1,	716,	"RO",	0,	0,	0ull,	0ull},
+	{"FSRC_PIN"                    ,	33,	1,	716,	"RO",	0,	0,	0ull,	0ull},
+	{"VGATE_PIN"                   ,	34,	1,	716,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	716,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	8,	717,	"R/W",	0,	0,	0ull,	0ull},
+	{"EFUSE"                       ,	8,	1,	717,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	717,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	12,	1,	717,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	717,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	16,	8,	717,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_63"              ,	24,	40,	717,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	10,	718,	"R/W",	0,	1,	999ull,	0},
+	{"SDH"                         ,	10,	4,	718,	"R/W",	0,	1,	0ull,	0},
+	{"PRH"                         ,	14,	4,	718,	"R/W",	0,	1,	6ull,	0},
+	{"FSH"                         ,	18,	4,	718,	"R/W",	0,	1,	15ull,	0},
+	{"SCH"                         ,	22,	4,	718,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	718,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	18,	719,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR1"                     ,	18,	18,	719,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR2"                     ,	36,	18,	719,	"RO",	0,	0,	0ull,	0ull},
+	{"TOO_MANY"                    ,	54,	1,	719,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	719,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR3"                     ,	0,	18,	720,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR4"                     ,	18,	18,	720,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR5"                     ,	36,	18,	720,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	720,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR6"                     ,	0,	18,	721,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	721,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	14,	722,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR1"                     ,	14,	14,	722,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR2"                     ,	28,	14,	722,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_42_63"              ,	42,	22,	722,	"RAZ",	1,	1,	0,	0},
+	{"TOO_MANY"                    ,	0,	1,	723,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	723,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	4,	724,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_4_63"               ,	4,	60,	724,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	725,	"R/W",	0,	1,	15ull,	0},
+	{"PCTL"                        ,	6,	6,	725,	"R/W",	0,	1,	19ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	725,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	726,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	726,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	726,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	726,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	726,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	726,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	726,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	726,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	726,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	726,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	727,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	727,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	728,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	728,	"RAZ",	1,	1,	0,	0},
+	{"FRNANOSEC"                   ,	0,	32,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	0,	64,	731,	"R/W",	0,	0,	18446744073709551615ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	732,	"R/W",	0,	0,	4294967295ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	732,	"RAZ",	1,	1,	0,	0},
+	{"PTP_EN"                      ,	0,	1,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_CLK_EN"                  ,	1,	1,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_CLK_IN"                  ,	2,	6,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_EN"                    ,	8,	1,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_EDGE"                  ,	9,	1,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_IN"                    ,	10,	6,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_EN"                    ,	16,	1,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_EDGE"                  ,	17,	1,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_IN"                    ,	18,	6,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT_EN"                    ,	24,	1,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT_INV"                   ,	25,	1,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT_OUT"                   ,	26,	4,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS_EN"                      ,	30,	1,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS_INV"                     ,	31,	1,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS_OUT"                     ,	32,	5,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT_OUT4"                  ,	37,	1,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_CLK_EDGE"                ,	38,	2,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT"                       ,	40,	1,	733,	"RO",	1,	0,	0,	0ull},
+	{"PPS"                         ,	41,	1,	733,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	733,	"RAZ",	1,	1,	0,	0},
+	{"FRNANOSEC"                   ,	0,	32,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	0,	64,	735,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	736,	"RAZ",	1,	1,	0,	0},
+	{"CNTR"                        ,	0,	64,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	738,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	738,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	0,	64,	740,	"R/W",	0,	0,	18446744073709551615ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	741,	"R/W",	0,	0,	4294967295ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	741,	"RAZ",	1,	1,	0,	0},
+	{"NANOSEC"                     ,	0,	64,	742,	"R/W",	0,	0,	0ull,	0ull},
+	{"QLM_CFG"                     ,	0,	3,	743,	"RO",	1,	1,	0,	0},
+	{"RESERVED_3_7"                ,	3,	5,	743,	"RAZ",	1,	1,	0,	0},
+	{"QLM_SPD"                     ,	8,	4,	743,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	743,	"RAZ",	1,	1,	0,	0},
+	{"RBOOT_PIN"                   ,	0,	1,	744,	"RO",	1,	1,	0,	0},
+	{"RBOOT"                       ,	1,	1,	744,	"R/W",	1,	1,	0,	0},
+	{"LBOOT"                       ,	2,	10,	744,	"R/W1C",	1,	1,	0,	0},
+	{"QLM0_SPD"                    ,	12,	4,	744,	"RO",	1,	1,	0,	0},
+	{"QLM1_SPD"                    ,	16,	4,	744,	"RO",	1,	1,	0,	0},
+	{"QLM2_SPD"                    ,	20,	4,	744,	"RO",	1,	1,	0,	0},
+	{"PNR_MUL"                     ,	24,	6,	744,	"RO",	1,	1,	0,	0},
+	{"C_MUL"                       ,	30,	6,	744,	"RO",	1,	1,	0,	0},
+	{"QLM3_SPD"                    ,	36,	4,	744,	"RO",	1,	1,	0,	0},
+	{"QLM4_SPD"                    ,	40,	4,	744,	"RO",	1,	1,	0,	0},
+	{"RESERVED_44_57"              ,	44,	14,	744,	"RAZ",	1,	1,	0,	0},
+	{"JT_TSTMODE"                  ,	58,	1,	744,	"RO",	1,	1,	0,	0},
+	{"RESERVED_59_63"              ,	59,	5,	744,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_CLR_BIST"               ,	0,	1,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"WARM_CLR_BIST"               ,	1,	1,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNTL_CLR_BIST"               ,	2,	1,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	745,	"RAZ",	1,	1,	0,	0},
+	{"BIST_DELAY"                  ,	8,	56,	745,	"RO",	1,	1,	0,	0},
+	{"RST_VAL"                     ,	0,	1,	746,	"RO",	1,	1,	0,	0},
+	{"RST_CHIP"                    ,	1,	1,	746,	"R/W",	0,	1,	0ull,	0},
+	{"RST_RCV"                     ,	2,	1,	746,	"R/W",	1,	1,	0,	0},
+	{"RST_DRV"                     ,	3,	1,	746,	"R/W",	1,	1,	0,	0},
+	{"PRTMODE"                     ,	4,	2,	746,	"R/W",	1,	1,	0,	0},
+	{"HOST_MODE"                   ,	6,	1,	746,	"RO",	1,	1,	0,	0},
+	{"RST_LINK"                    ,	7,	1,	746,	"R/W",	1,	1,	0,	0},
+	{"RST_DONE"                    ,	8,	1,	746,	"RO",	1,	1,	0,	0},
+	{"PRST_LINK"                   ,	9,	1,	746,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	746,	"RAZ",	1,	1,	0,	0},
+	{"RST_VAL"                     ,	0,	1,	747,	"RO",	1,	1,	0,	0},
+	{"RST_CHIP"                    ,	1,	1,	747,	"R/W",	0,	1,	0ull,	0},
+	{"RST_RCV"                     ,	2,	1,	747,	"R/W",	1,	1,	0,	0},
+	{"RST_DRV"                     ,	3,	1,	747,	"R/W",	1,	1,	0,	0},
+	{"PRTMODE"                     ,	4,	2,	747,	"R/W",	1,	1,	0,	0},
+	{"HOST_MODE"                   ,	6,	1,	747,	"RO",	1,	1,	0,	0},
+	{"RST_LINK"                    ,	7,	1,	747,	"R/W",	1,	1,	0,	0},
+	{"RST_DONE"                    ,	8,	1,	747,	"RO",	1,	1,	0,	0},
+	{"PRST_LINK"                   ,	9,	1,	747,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	747,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST_DLY"                ,	0,	16,	748,	"R/W",	0,	1,	2047ull,	0},
+	{"WARM_RST_DLY"                ,	16,	16,	748,	"R/W",	0,	1,	2047ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	748,	"RAZ",	1,	1,	0,	0},
+	{"RST_LINK0"                   ,	0,	1,	749,	"R/W1C",	0,	1,	0ull,	0},
+	{"RST_LINK1"                   ,	1,	1,	749,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_7"                ,	2,	6,	749,	"RAZ",	1,	1,	0,	0},
+	{"PERST0"                      ,	8,	1,	749,	"R/W1C",	0,	1,	0ull,	0},
+	{"PERST1"                      ,	9,	1,	749,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	749,	"RAZ",	1,	1,	0,	0},
+	{"RST_LINK0"                   ,	0,	1,	750,	"R/W",	0,	1,	0ull,	0},
+	{"RST_LINK1"                   ,	1,	1,	750,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_7"                ,	2,	6,	750,	"RAZ",	1,	1,	0,	0},
+	{"PERST0"                      ,	8,	1,	750,	"R/W",	0,	1,	0ull,	0},
+	{"PERST1"                      ,	9,	1,	750,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	750,	"RAZ",	1,	1,	0,	0},
+	{"ST_INT"                      ,	0,	1,	751,	"R/W1C",	0,	1,	0ull,	0},
+	{"TS_INT"                      ,	1,	1,	751,	"R/W1C",	0,	1,	0ull,	0},
+	{"CORE_INT"                    ,	2,	1,	751,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	751,	"RAZ",	1,	1,	0,	0},
+	{"ST_EN"                       ,	4,	1,	751,	"R/W",	0,	1,	0ull,	0},
+	{"TS_EN"                       ,	5,	1,	751,	"R/W",	0,	1,	0ull,	0},
+	{"CORE_EN"                     ,	6,	1,	751,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	751,	"RAZ",	1,	1,	0,	0},
+	{"SDA_OVR"                     ,	8,	1,	751,	"R/W",	0,	1,	0ull,	0},
+	{"SCL_OVR"                     ,	9,	1,	751,	"R/W",	0,	1,	0ull,	0},
+	{"SDA"                         ,	10,	1,	751,	"RO",	1,	1,	0,	0},
+	{"SCL"                         ,	11,	1,	751,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	751,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	752,	"R/W",	0,	1,	0ull,	0},
+	{"EOP_IA"                      ,	32,	3,	752,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	35,	5,	752,	"R/W",	0,	1,	0ull,	0},
+	{"A"                           ,	40,	10,	752,	"R/W",	0,	1,	0ull,	0},
+	{"SCR"                         ,	50,	2,	752,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	52,	3,	752,	"R/W",	0,	1,	0ull,	0},
+	{"SOVR"                        ,	55,	1,	752,	"R/W",	0,	1,	0ull,	0},
+	{"R"                           ,	56,	1,	752,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	57,	4,	752,	"R/W",	0,	1,	0ull,	0},
+	{"EIA"                         ,	61,	1,	752,	"R/W",	0,	1,	0ull,	0},
+	{"SLONLY"                      ,	62,	1,	752,	"R/W",	0,	1,	0ull,	0},
+	{"V"                           ,	63,	1,	752,	"RC/W",	0,	1,	0ull,	0},
+	{"D"                           ,	0,	32,	753,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	32,	8,	753,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	753,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	754,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_32_61"              ,	32,	30,	754,	"RAZ",	1,	1,	0,	0},
+	{"V"                           ,	62,	2,	754,	"RC/W",	0,	1,	0ull,	0},
+	{"DLH"                         ,	0,	8,	755,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	755,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	756,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	756,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	757,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	757,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	758,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	758,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	758,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	758,	"RAZ",	1,	1,	0,	0},
+	{"TXTRIG"                      ,	4,	2,	758,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	758,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	758,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	759,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	759,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	760,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	760,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	760,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	760,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	760,	"RAZ",	1,	1,	0,	0},
+	{"PTIME"                       ,	7,	1,	760,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	760,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	761,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	761,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	761,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	761,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	762,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	762,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	762,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	762,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	762,	"RAZ",	1,	1,	0,	0},
+	{"BRK"                         ,	6,	1,	762,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	762,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	762,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	763,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	763,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	763,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	763,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	763,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	763,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	763,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	763,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	763,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	764,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	764,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	764,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	764,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	764,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	764,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	764,	"RAZ",	1,	1,	0,	0},
+	{"DCTS"                        ,	0,	1,	765,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	765,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	765,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	765,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	765,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	765,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	765,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	765,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	765,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	766,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	766,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	767,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	767,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	768,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	768,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	768,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	768,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	769,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	769,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	770,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	770,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	771,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	771,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	772,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	772,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	772,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	772,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	773,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	773,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	774,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	774,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	775,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	775,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	776,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	776,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	777,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	777,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	778,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	778,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	779,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	779,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	779,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	779,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	779,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	779,	"RAZ",	1,	1,	0,	0},
+	{"ORFDAT"                      ,	0,	1,	780,	"RO",	0,	0,	0ull,	0ull},
+	{"IRFDAT"                      ,	1,	1,	780,	"RO",	0,	0,	0ull,	0ull},
+	{"IPFDAT"                      ,	2,	1,	780,	"RO",	0,	0,	0ull,	0ull},
+	{"MRQDAT"                      ,	3,	1,	780,	"RO",	0,	0,	0ull,	0ull},
+	{"MRGDAT"                      ,	4,	1,	780,	"RO",	0,	0,	0ull,	0ull},
+	{"OPFDAT"                      ,	5,	1,	780,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	780,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MRQ_HWM"                     ,	0,	2,	781,	"R/W",	0,	0,	0ull,	1ull},
+	{"NBTARB"                      ,	2,	1,	781,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENDIAN"                     ,	3,	1,	781,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	4,	1,	781,	"R/W",	0,	0,	1ull,	0ull},
+	{"EN"                          ,	5,	1,	781,	"R/W",	0,	0,	0ull,	0ull},
+	{"BUSY"                        ,	6,	1,	781,	"RO",	0,	0,	0ull,	0ull},
+	{"CRC_STRIP"                   ,	7,	1,	781,	"R/W",	0,	0,	0ull,	0ull},
+	{"TS_THRESH"                   ,	8,	4,	781,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	781,	"RAZ",	1,	1,	0,	0},
+	{"OVFENA"                      ,	0,	1,	782,	"R/W",	0,	0,	0ull,	0ull},
+	{"IVFENA"                      ,	1,	1,	782,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTHENA"                      ,	2,	1,	782,	"R/W",	0,	0,	0ull,	0ull},
+	{"ITHENA"                      ,	3,	1,	782,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_DRPENA"                 ,	4,	1,	782,	"R/W",	0,	0,	0ull,	0ull},
+	{"IRUNENA"                     ,	5,	1,	782,	"R/W",	0,	0,	0ull,	0ull},
+	{"ORUNENA"                     ,	6,	1,	782,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSENA"                       ,	7,	1,	782,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	782,	"RAZ",	1,	1,	0,	0},
+	{"IRCNT"                       ,	0,	20,	783,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	783,	"RAZ",	1,	1,	0,	0},
+	{"IRHWM"                       ,	0,	20,	784,	"R/W",	0,	0,	0ull,	0ull},
+	{"IBPLWM"                      ,	20,	20,	784,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	784,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	785,	"RAZ",	1,	1,	0,	0},
+	{"IBASE"                       ,	3,	37,	785,	"R/W",	0,	1,	0ull,	0},
+	{"ISIZE"                       ,	40,	20,	785,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	785,	"RAZ",	1,	1,	0,	0},
+	{"IDBELL"                      ,	0,	20,	786,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	786,	"RAZ",	1,	1,	0,	0},
+	{"ITLPTR"                      ,	32,	20,	786,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	786,	"RAZ",	1,	1,	0,	0},
+	{"ODBLOVF"                     ,	0,	1,	787,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IDBLOVF"                     ,	1,	1,	787,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORTHRESH"                    ,	2,	1,	787,	"RO",	0,	0,	0ull,	0ull},
+	{"IRTHRESH"                    ,	3,	1,	787,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_DRP"                    ,	4,	1,	787,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IRUN"                        ,	5,	1,	787,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORUN"                        ,	6,	1,	787,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TS"                          ,	7,	1,	787,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	787,	"RAZ",	1,	1,	0,	0},
+	{"ORCNT"                       ,	0,	20,	788,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	788,	"RAZ",	1,	1,	0,	0},
+	{"ORHWM"                       ,	0,	20,	789,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	789,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	790,	"RAZ",	1,	1,	0,	0},
+	{"OBASE"                       ,	3,	37,	790,	"R/W",	0,	1,	0ull,	0},
+	{"OSIZE"                       ,	40,	20,	790,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	790,	"RAZ",	1,	1,	0,	0},
+	{"ODBELL"                      ,	0,	20,	791,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	791,	"RAZ",	1,	1,	0,	0},
+	{"OTLPTR"                      ,	32,	20,	791,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	791,	"RAZ",	1,	1,	0,	0},
+	{"OREMCNT"                     ,	0,	20,	792,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	792,	"RAZ",	1,	1,	0,	0},
+	{"IREMCNT"                     ,	32,	20,	792,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_52_63"              ,	52,	12,	792,	"RAZ",	1,	1,	0,	0},
+	{"TSCNT"                       ,	0,	5,	793,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	793,	"RAZ",	1,	1,	0,	0},
+	{"TSTOT"                       ,	8,	5,	793,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	793,	"RAZ",	1,	1,	0,	0},
+	{"TSAVL"                       ,	16,	5,	793,	"RO",	0,	0,	4ull,	4ull},
+	{"RESERVED_21_63"              ,	21,	43,	793,	"RAZ",	1,	1,	0,	0},
+	{"TSTAMP"                      ,	0,	64,	794,	"RO",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	3,	795,	"R/W",	0,	1,	0ull,	0},
+	{"ADR_CYC"                     ,	3,	4,	795,	"R/W",	0,	1,	8ull,	0},
+	{"T_MULT"                      ,	7,	4,	795,	"R/W",	0,	1,	9ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	795,	"RAZ",	1,	1,	0,	0},
+	{"NF_CMD"                      ,	0,	64,	796,	"R/W",	0,	1,	0ull,	0},
+	{"CNT"                         ,	0,	8,	797,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	797,	"RAZ",	1,	1,	0,	0},
+	{"ECC_ERR"                     ,	0,	8,	798,	"RO",	0,	1,	0ull,	0},
+	{"XOR_ECC"                     ,	8,	24,	798,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	798,	"RAZ",	1,	1,	0,	0},
+	{"EMPTY"                       ,	0,	1,	799,	"R/W1C",	0,	1,	0ull,	0},
+	{"FULL"                        ,	1,	1,	799,	"R/W1C",	0,	1,	0ull,	0},
+	{"WDOG"                        ,	2,	1,	799,	"R/W1C",	0,	1,	0ull,	0},
+	{"SM_BAD"                      ,	3,	1,	799,	"R/W1C",	0,	1,	0ull,	0},
+	{"ECC_1BIT"                    ,	4,	1,	799,	"R/W1C",	0,	1,	0ull,	0},
+	{"ECC_MULT"                    ,	5,	1,	799,	"R/W1C",	0,	1,	0ull,	0},
+	{"OVRF"                        ,	6,	1,	799,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	799,	"RAZ",	1,	1,	0,	0},
+	{"EMPTY"                       ,	0,	1,	800,	"R/W",	0,	1,	0ull,	0},
+	{"FULL"                        ,	1,	1,	800,	"R/W",	0,	1,	0ull,	0},
+	{"WDOG"                        ,	2,	1,	800,	"R/W",	0,	1,	0ull,	0},
+	{"SM_BAD"                      ,	3,	1,	800,	"R/W",	0,	1,	0ull,	0},
+	{"ECC_1BIT"                    ,	4,	1,	800,	"R/W",	0,	1,	0ull,	0},
+	{"ECC_MULT"                    ,	5,	1,	800,	"R/W",	0,	1,	0ull,	0},
+	{"OVRF"                        ,	6,	1,	800,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	800,	"RAZ",	1,	1,	0,	0},
+	{"RST_FF"                      ,	0,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"EX_DIS"                      ,	1,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"BT_DIS"                      ,	2,	1,	801,	"R/W",	0,	0,	0ull,	1ull},
+	{"BT_DMA"                      ,	3,	1,	801,	"R/W",	0,	1,	0ull,	0},
+	{"RD_CMD"                      ,	4,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD_VAL"                      ,	5,	1,	801,	"RO",	0,	1,	0ull,	0},
+	{"RD_DONE"                     ,	6,	1,	801,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FR_BYT"                      ,	7,	11,	801,	"RO",	0,	1,	0ull,	0},
+	{"WAIT_CNT"                    ,	18,	6,	801,	"R/W",	0,	1,	20ull,	0},
+	{"NBR_HWM"                     ,	24,	3,	801,	"R/W",	0,	0,	3ull,	3ull},
+	{"MB_DIS"                      ,	27,	1,	801,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	801,	"RAZ",	1,	1,	0,	0},
+	{"MAIN_SM"                     ,	0,	3,	802,	"RO",	0,	1,	0ull,	0},
+	{"MAIN_BAD"                    ,	3,	1,	802,	"RO",	0,	1,	0ull,	0},
+	{"RD_FF"                       ,	4,	2,	802,	"RO",	0,	1,	0ull,	0},
+	{"RD_FF_BAD"                   ,	6,	1,	802,	"RO",	0,	1,	0ull,	0},
+	{"BT_SM"                       ,	7,	4,	802,	"RO",	0,	1,	0ull,	0},
+	{"EXE_SM"                      ,	11,	4,	802,	"RO",	0,	1,	0ull,	0},
+	{"EXE_IDLE"                    ,	15,	1,	802,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	802,	"RAZ",	1,	1,	0,	0},
+	{"VENDID"                      ,	0,	16,	803,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	803,	"RO/WRSL",	0,	0,	145ull,	145ull},
+	{"ISAE"                        ,	0,	1,	804,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	804,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	804,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	804,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	804,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	804,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	804,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	804,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	804,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	804,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	804,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	804,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	804,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	804,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	804,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	804,	"RAZ",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	804,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	804,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	804,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	804,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	804,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	804,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	804,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	804,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	805,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PI"                          ,	8,	8,	805,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	805,	"RO/WRSL",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	805,	"RO/WRSL",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	806,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	806,	"RO",	0,	0,	0ull,	0ull},
+	{"MFD"                         ,	23,	1,	806,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	806,	"RO",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	807,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	807,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	807,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_13"               ,	4,	10,	807,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	14,	18,	807,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	808,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	808,	"WORSL",	0,	0,	8191ull,	8191ull},
+	{"UBAB"                        ,	0,	32,	809,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	810,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	811,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	811,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	811,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_25"               ,	4,	22,	811,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	26,	6,	811,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	812,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	812,	"WORSL",	0,	0,	33554431ull,	33554431ull},
+	{"UBAB"                        ,	0,	32,	813,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	814,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	815,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	815,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	815,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_31"               ,	4,	28,	815,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	1,	816,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	816,	"WORSL",	0,	0,	2147483647ull,	2147483647ull},
+	{"RESERVED_0_8"                ,	0,	9,	817,	"RAZ",	1,	1,	0,	0},
+	{"UBAB"                        ,	9,	23,	817,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	818,	"WORSL",	0,	0,	511ull,	511ull},
+	{"CISP"                        ,	0,	32,	819,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SSVID"                       ,	0,	16,	820,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"SSID"                        ,	16,	16,	820,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"ER_EN"                       ,	0,	1,	821,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_15"               ,	1,	15,	821,	"RAZ",	1,	1,	0,	0},
+	{"ERADDR"                      ,	16,	16,	821,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	822,	"WORSL",	0,	0,	1ull,	1ull},
+	{"MASK"                        ,	1,	31,	822,	"WORSL",	0,	0,	32767ull,	32767ull},
+	{"CP"                          ,	0,	8,	823,	"RO/WRSL",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	823,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	824,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	824,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"MG"                          ,	16,	8,	824,	"RO",	0,	0,	0ull,	0ull},
+	{"ML"                          ,	24,	8,	824,	"RO",	0,	0,	0ull,	0ull},
+	{"PMCID"                       ,	0,	8,	825,	"RO",	0,	0,	1ull,	0ull},
+	{"NCP"                         ,	8,	8,	825,	"RO/WRSL",	0,	0,	80ull,	0ull},
+	{"PMSV"                        ,	16,	3,	825,	"RO/WRSL",	0,	0,	3ull,	0ull},
+	{"PME_CLOCK"                   ,	19,	1,	825,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	825,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	825,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	825,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	825,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	825,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	825,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	826,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	826,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	826,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	826,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	826,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	826,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	826,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	826,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	826,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	826,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	827,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	827,	"RO/WRSL",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	827,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	827,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"PVM"                         ,	24,	1,	827,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	827,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	828,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	829,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	830,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	831,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	831,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	831,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	831,	"RO",	0,	0,	0ull,	0ull},
+	{"SI"                          ,	24,	1,	831,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	831,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	831,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	832,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	832,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	832,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	832,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"EL1AL"                       ,	9,	3,	832,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"RESERVED_12_14"              ,	12,	3,	832,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	832,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	832,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	832,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	832,	"RO",	0,	0,	0ull,	0ull},
+	{"FLR"                         ,	28,	1,	832,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	832,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	833,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	833,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	833,	"R/W",	0,	0,	2ull,	2ull},
+	{"I_FLR"                       ,	15,	1,	833,	"RO",	0,	0,	0ull,	0ull},
+	{"CE_D"                        ,	16,	1,	833,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	833,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	833,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	833,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	833,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	833,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	833,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	834,	"RO/WRSL",	1,	1,	0,	0},
+	{"MLW"                         ,	4,	6,	834,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"ASLPMS"                      ,	10,	2,	834,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	834,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	834,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	834,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	834,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	834,	"RO",	0,	0,	0ull,	0ull},
+	{"LBNC"                        ,	21,	1,	834,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPM"                        ,	22,	1,	834,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_23_23"              ,	23,	1,	834,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	834,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	835,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	835,	"RO",	0,	0,	0ull,	0ull},
+	{"LD"                          ,	4,	1,	835,	"RO",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	835,	"RO",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	835,	"RO",	0,	0,	0ull,	0ull},
+	{"LBM_INT_ENB"                 ,	10,	1,	835,	"RO",	0,	0,	0ull,	0ull},
+	{"LAB_INT_ENB"                 ,	11,	1,	835,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	835,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	835,	"RO",	0,	0,	1ull,	1ull},
+	{"NLW"                         ,	20,	6,	835,	"RO",	0,	0,	0ull,	8ull},
+	{"RESERVED_26_26"              ,	26,	1,	835,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	835,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	835,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"DLLA"                        ,	29,	1,	835,	"RO",	0,	0,	0ull,	0ull},
+	{"LBM"                         ,	30,	1,	835,	"RO",	0,	0,	0ull,	0ull},
+	{"LAB"                         ,	31,	1,	835,	"RO",	0,	0,	0ull,	0ull},
+	{"CTRS"                        ,	0,	4,	836,	"RO",	0,	0,	15ull,	15ull},
+	{"CTDS"                        ,	4,	1,	836,	"RO",	0,	0,	1ull,	1ull},
+	{"ARI"                         ,	5,	1,	836,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OPS"                    ,	6,	1,	836,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM32S"                     ,	7,	1,	836,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM64S"                     ,	8,	1,	836,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM128S"                    ,	9,	1,	836,	"RO",	0,	0,	0ull,	0ull},
+	{"NOROPRPR"                    ,	10,	1,	836,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	836,	"RAZ",	1,	1,	0,	0},
+	{"TPH"                         ,	12,	2,	836,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	836,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	837,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	837,	"R/W",	0,	0,	0ull,	0ull},
+	{"ARI"                         ,	5,	1,	837,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP"                     ,	6,	1,	837,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP_EB"                  ,	7,	1,	837,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_RQ"                      ,	8,	1,	837,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_CP"                      ,	9,	1,	837,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_31"              ,	10,	22,	837,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	838,	"RAZ",	1,	1,	0,	0},
+	{"SLSV"                        ,	1,	7,	838,	"RO/WRSL",	1,	1,	0,	0},
+	{"CLS"                         ,	8,	1,	838,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	838,	"RAZ",	1,	1,	0,	0},
+	{"TLS"                         ,	0,	4,	839,	"R/W",	1,	0,	0,	2ull},
+	{"EC"                          ,	4,	1,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"HASD"                        ,	5,	1,	839,	"RO",	0,	0,	0ull,	0ull},
+	{"SDE"                         ,	6,	1,	839,	"RO",	0,	0,	0ull,	0ull},
+	{"TM"                          ,	7,	3,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMC"                         ,	10,	1,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSOS"                        ,	11,	1,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDE"                         ,	12,	1,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	839,	"RAZ",	1,	1,	0,	0},
+	{"CDL"                         ,	16,	1,	839,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	839,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	840,	"RO",	0,	0,	1ull,	1ull},
+	{"CV"                          ,	16,	4,	840,	"RO",	0,	0,	2ull,	2ull},
+	{"NCO"                         ,	20,	12,	840,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	841,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	841,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	841,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	841,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	841,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	841,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	841,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	841,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	841,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	841,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	841,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	841,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	841,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	841,	"RAZ",	1,	1,	0,	0},
+	{"UATOMBS"                     ,	24,	1,	841,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	841,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	842,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	842,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	842,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	842,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	842,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	842,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	842,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	842,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	842,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	842,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	842,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	842,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	842,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	842,	"RAZ",	1,	1,	0,	0},
+	{"UATOMBM"                     ,	24,	1,	842,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	842,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	843,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	843,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	843,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	843,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	843,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	843,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	843,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	843,	"RO",	0,	0,	2ull,	2ull},
+	{"UATOMBS"                     ,	24,	1,	843,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	843,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	844,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	844,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	844,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	845,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	845,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	845,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	845,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	845,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	845,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	845,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	845,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	845,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	846,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	846,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	846,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	846,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	846,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	846,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	847,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	848,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	849,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	850,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	851,	"R/W",	0,	1,	4143ull,	0},
+	{"RTL"                         ,	16,	16,	851,	"R/W",	0,	1,	12429ull,	0},
+	{"OMR"                         ,	0,	32,	852,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	853,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_14"               ,	8,	7,	853,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	853,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	853,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	853,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	853,	"R/W",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	854,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	854,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	854,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	854,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	854,	"R/W",	0,	0,	3ull,	3ull},
+	{"EASPML1"                     ,	30,	1,	854,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	854,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	855,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	855,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	855,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	855,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	855,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	855,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	855,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	855,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	855,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	855,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_22_31"              ,	22,	10,	855,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	856,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	856,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	856,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	856,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	856,	"R/W",	0,	0,	0ull,	0ull},
+	{"MFUNCN"                      ,	0,	8,	857,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_13"               ,	8,	6,	857,	"RO",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	857,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	857,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	857,	"R/W",	0,	0,	0ull,	0ull},
+	{"CX_NFUNC"                    ,	29,	3,	857,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPIV"                       ,	0,	11,	858,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	858,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	858,	"R/W",	0,	0,	1ull,	1ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_DABORT_4UCPL"              ,	2,	1,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_HANDLE_FLUSH"              ,	3,	1,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_31"               ,	4,	28,	859,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	860,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	861,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	862,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	862,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	862,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	863,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	863,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	863,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	864,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	864,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	864,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	865,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	866,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	866,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	866,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	866,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	867,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	867,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	867,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	867,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	868,	"RO/WRSL",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	868,	"RO/WRSL",	0,	0,	96ull,	96ull},
+	{"RESERVED_20_20"              ,	20,	1,	868,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	868,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	868,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	868,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	868,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	869,	"RO/WRSL",	0,	0,	32ull,	32ull},
+	{"HEADER_CREDITS"              ,	12,	8,	869,	"RO/WRSL",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_20"              ,	20,	1,	869,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	869,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	869,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	870,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HEADER_CREDITS"              ,	12,	8,	870,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	870,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	870,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	870,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	871,	"RO/WRSL",	0,	0,	392ull,	392ull},
+	{"RESERVED_14_15"              ,	14,	2,	871,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	871,	"RO/WRSL",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	871,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	872,	"RO/WRSL",	0,	0,	136ull,	136ull},
+	{"RESERVED_14_15"              ,	14,	2,	872,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	872,	"RO/WRSL",	0,	0,	38ull,	38ull},
+	{"RESERVED_26_31"              ,	26,	6,	872,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	873,	"RO/WRSL",	0,	0,	679ull,	679ull},
+	{"RESERVED_14_15"              ,	14,	2,	873,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	873,	"RO/WRSL",	0,	0,	133ull,	133ull},
+	{"RESERVED_26_31"              ,	26,	6,	873,	"RAZ",	1,	1,	0,	0},
+	{"N_FTS"                       ,	0,	8,	874,	"R/W",	0,	0,	128ull,	128ull},
+	{"LE"                          ,	8,	9,	874,	"R/W",	0,	0,	8ull,	8ull},
+	{"DSC"                         ,	17,	1,	874,	"R/W",	0,	0,	0ull,	0ull},
+	{"CPYTS"                       ,	18,	1,	874,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTCRB"                       ,	19,	1,	874,	"R/W",	0,	0,	0ull,	0ull},
+	{"S_D_E"                       ,	20,	1,	874,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	874,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	875,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	876,	"R/W",	0,	0,	0ull,	0ull},
+	{"VENDID"                      ,	0,	16,	877,	"R/W",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	877,	"R/W",	0,	0,	145ull,	145ull},
+	{"ISAE"                        ,	0,	1,	878,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	878,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	878,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	878,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	878,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	878,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	878,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	878,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	878,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	878,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	878,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	878,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	878,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	878,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	878,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	878,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	878,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	878,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	878,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	878,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	878,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	878,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	878,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	878,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	879,	"R/W",	0,	0,	0ull,	0ull},
+	{"PI"                          ,	8,	8,	879,	"R/W",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	879,	"R/W",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	879,	"R/W",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	880,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	880,	"RO",	0,	0,	1ull,	1ull},
+	{"MFD"                         ,	23,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	880,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_31"               ,	0,	32,	881,	"RO",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	882,	"RO",	1,	1,	0,	0},
+	{"PBNUM"                       ,	0,	8,	883,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBNUM"                       ,	8,	8,	883,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUBBNUM"                     ,	16,	8,	883,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLT"                         ,	24,	8,	883,	"RO",	0,	0,	0ull,	0ull},
+	{"IO32A"                       ,	0,	1,	884,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	884,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_BASE"                    ,	4,	4,	884,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO32B"                       ,	8,	1,	884,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_11"               ,	9,	3,	884,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_LIMI"                    ,	12,	4,	884,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_20"              ,	16,	5,	884,	"RAZ",	1,	1,	0,	0},
+	{"M66"                         ,	21,	1,	884,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	884,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	884,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	884,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	884,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	884,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	884,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	884,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	884,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	884,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	885,	"RO",	1,	1,	0,	0},
+	{"MB_ADDR"                     ,	4,	12,	885,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_19"              ,	16,	4,	885,	"RO",	1,	1,	0,	0},
+	{"ML_ADDR"                     ,	20,	12,	885,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64A"                      ,	0,	1,	886,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	886,	"RO",	1,	1,	0,	0},
+	{"LMEM_BASE"                   ,	4,	12,	886,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64B"                      ,	16,	1,	886,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_17_19"              ,	17,	3,	886,	"RO",	1,	1,	0,	0},
+	{"LMEM_LIMIT"                  ,	20,	12,	886,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_BASE"                   ,	0,	32,	887,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_LIMIT"                  ,	0,	32,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_BASE"                    ,	0,	16,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_LIMIT"                   ,	16,	16,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP"                          ,	0,	8,	890,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	890,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	891,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	892,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	892,	"R/W",	0,	0,	1ull,	1ull},
+	{"PERE"                        ,	16,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	17,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"ISAE"                        ,	18,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGAE"                        ,	19,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGA16D"                      ,	20,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAM"                         ,	21,	1,	892,	"RO",	0,	0,	0ull,	0ull},
+	{"SBRST"                       ,	22,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	23,	1,	892,	"RO",	0,	0,	0ull,	0ull},
+	{"PDT"                         ,	24,	1,	892,	"RO",	0,	0,	0ull,	0ull},
+	{"SDT"                         ,	25,	1,	892,	"RO",	0,	0,	0ull,	0ull},
+	{"DTS"                         ,	26,	1,	892,	"RO",	0,	0,	0ull,	0ull},
+	{"DTSEES"                      ,	27,	1,	892,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	892,	"RO",	1,	1,	0,	0},
+	{"PMCID"                       ,	0,	8,	893,	"RO",	0,	0,	1ull,	1ull},
+	{"NCP"                         ,	8,	8,	893,	"R/W",	0,	0,	80ull,	80ull},
+	{"PMSV"                        ,	16,	3,	893,	"R/W",	0,	0,	3ull,	3ull},
+	{"PME_CLOCK"                   ,	19,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	893,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	893,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	893,	"R/W",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	893,	"R/W",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	893,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	893,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	894,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	894,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	894,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	894,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	894,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	894,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	894,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	894,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	894,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	895,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	895,	"R/W",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	895,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	895,	"R/W",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	895,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	895,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	895,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	896,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	898,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	898,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	899,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	899,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	899,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	899,	"RO",	0,	0,	4ull,	4ull},
+	{"SI"                          ,	24,	1,	899,	"R/W",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	899,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	899,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	900,	"R/W",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL1AL"                       ,	9,	3,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_14"              ,	12,	3,	900,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	900,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	900,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	900,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	900,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	900,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	901,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	901,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	901,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_15_15"              ,	15,	1,	901,	"RAZ",	1,	1,	0,	0},
+	{"CE_D"                        ,	16,	1,	901,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	901,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	901,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	901,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	901,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	901,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	901,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	902,	"R/W",	1,	1,	0,	0},
+	{"MLW"                         ,	4,	6,	902,	"R/W",	0,	0,	8ull,	8ull},
+	{"ASLPMS"                      ,	10,	2,	902,	"R/W",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	902,	"R/W",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	902,	"R/W",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	902,	"RO",	0,	0,	1ull,	1ull},
+	{"LBNC"                        ,	21,	1,	902,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"ASPM"                        ,	22,	1,	902,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_23_23"              ,	23,	1,	902,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	902,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	903,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	903,	"R/W",	0,	0,	1ull,	1ull},
+	{"LD"                          ,	4,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"LBM_INT_ENB"                 ,	10,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAB_INT_ENB"                 ,	11,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	903,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	903,	"RO",	1,	1,	0,	0},
+	{"NLW"                         ,	20,	6,	903,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_26"              ,	26,	1,	903,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	903,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	903,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLLA"                        ,	29,	1,	903,	"RO",	0,	0,	0ull,	1ull},
+	{"LBM"                         ,	30,	1,	903,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LAB"                         ,	31,	1,	903,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ABP"                         ,	0,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCP"                         ,	1,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLSP"                       ,	2,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIP"                         ,	3,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	4,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_S"                        ,	5,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_C"                        ,	6,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LV"                       ,	7,	8,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LS"                       ,	15,	2,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIP"                        ,	17,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"NCCS"                        ,	18,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS_NUM"                      ,	19,	13,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABP_EN"                      ,	0,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	1,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLS_EN"                     ,	2,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"PD_EN"                       ,	3,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCINT_EN"                    ,	4,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"HPINT_EN"                    ,	5,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIC"                         ,	6,	2,	905,	"R/W",	0,	0,	3ull,	3ull},
+	{"PIC"                         ,	8,	2,	905,	"R/W",	0,	0,	3ull,	3ull},
+	{"PCC"                         ,	10,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIC"                        ,	11,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLS_EN"                     ,	12,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	905,	"RAZ",	1,	1,	0,	0},
+	{"ABP_D"                       ,	16,	1,	905,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PF_D"                        ,	17,	1,	905,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLS_C"                      ,	18,	1,	905,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PD_C"                        ,	19,	1,	905,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CCINT_D"                     ,	20,	1,	905,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLSS"                       ,	21,	1,	905,	"RO",	0,	0,	0ull,	0ull},
+	{"PDS"                         ,	22,	1,	905,	"RO",	0,	0,	1ull,	1ull},
+	{"EMIS"                        ,	23,	1,	905,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLS_C"                      ,	24,	1,	905,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	905,	"RAZ",	1,	1,	0,	0},
+	{"SECEE"                       ,	0,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"SENFEE"                      ,	1,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEFEE"                       ,	2,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMEIE"                       ,	3,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRSSVE"                      ,	4,	1,	906,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_15"               ,	5,	11,	906,	"RAZ",	1,	1,	0,	0},
+	{"CRSSV"                       ,	16,	1,	906,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	906,	"RAZ",	1,	1,	0,	0},
+	{"PME_RID"                     ,	0,	16,	907,	"RO",	0,	0,	0ull,	0ull},
+	{"PME_STAT"                    ,	16,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PME_PEND"                    ,	17,	1,	907,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	907,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTRS"                        ,	0,	4,	908,	"RO",	0,	0,	15ull,	15ull},
+	{"CTDS"                        ,	4,	1,	908,	"RO",	0,	0,	1ull,	1ull},
+	{"ARI"                         ,	5,	1,	908,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OPS"                    ,	6,	1,	908,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM32S"                     ,	7,	1,	908,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM64S"                     ,	8,	1,	908,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM128S"                    ,	9,	1,	908,	"RO",	0,	0,	0ull,	0ull},
+	{"NOROPRPR"                    ,	10,	1,	908,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_11_11"              ,	11,	1,	908,	"RAZ",	1,	1,	0,	0},
+	{"TPH"                         ,	12,	2,	908,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	908,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	909,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"ARI"                         ,	5,	1,	909,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP"                     ,	6,	1,	909,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP_EB"                  ,	7,	1,	909,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_RQ"                      ,	8,	1,	909,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_CP"                      ,	9,	1,	909,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_31"              ,	10,	22,	909,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	910,	"RAZ",	1,	1,	0,	0},
+	{"SLSV"                        ,	1,	7,	910,	"RO/WRSL",	1,	1,	0,	0},
+	{"CLS"                         ,	8,	1,	910,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	910,	"RAZ",	1,	1,	0,	0},
+	{"TLS"                         ,	0,	4,	911,	"R/W",	1,	1,	0,	0},
+	{"EC"                          ,	4,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"HASD"                        ,	5,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDE"                         ,	6,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"TM"                          ,	7,	3,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMC"                         ,	10,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSOS"                        ,	11,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDE"                         ,	12,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	911,	"RAZ",	1,	1,	0,	0},
+	{"CDL"                         ,	16,	1,	911,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	911,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	912,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	913,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	914,	"RO",	0,	0,	1ull,	1ull},
+	{"CV"                          ,	16,	4,	914,	"RO",	0,	0,	2ull,	2ull},
+	{"NCO"                         ,	20,	12,	914,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	915,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	915,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	915,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	915,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	915,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	915,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	915,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	915,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	915,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	915,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	915,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	915,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	915,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	915,	"RAZ",	1,	1,	0,	0},
+	{"UATOMBS"                     ,	24,	1,	915,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	915,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	916,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	916,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	916,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	916,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	916,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	916,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	916,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	916,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	916,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	916,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	916,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	916,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	916,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	916,	"RAZ",	1,	1,	0,	0},
+	{"UATOMBM"                     ,	24,	1,	916,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	916,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	917,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	917,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	917,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	917,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	917,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	917,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	917,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	917,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	917,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	917,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	917,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	917,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	917,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	917,	"RO",	0,	0,	2ull,	2ull},
+	{"UATOMBS"                     ,	24,	1,	917,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	917,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	918,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	918,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	918,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	918,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	918,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	918,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	918,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	918,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	918,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	919,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	919,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	919,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	919,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	919,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	919,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	919,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	919,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	919,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	920,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	920,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	920,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	920,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	921,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	922,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	923,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	924,	"RO",	0,	0,	0ull,	0ull},
+	{"CERE"                        ,	0,	1,	925,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFERE"                       ,	1,	1,	925,	"R/W",	0,	0,	0ull,	0ull},
+	{"FERE"                        ,	2,	1,	925,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	925,	"RAZ",	1,	1,	0,	0},
+	{"ECR"                         ,	0,	1,	926,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_ECR"                   ,	1,	1,	926,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EFNFR"                       ,	2,	1,	926,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_EFNFR"                 ,	3,	1,	926,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FUF"                         ,	4,	1,	926,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFEMR"                       ,	5,	1,	926,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEMR"                        ,	6,	1,	926,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_26"               ,	7,	20,	926,	"RAZ",	1,	1,	0,	0},
+	{"AEIMN"                       ,	27,	5,	926,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECSI"                        ,	0,	16,	927,	"RO",	0,	0,	0ull,	0ull},
+	{"EFNFSI"                      ,	16,	16,	927,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	928,	"R/W",	0,	1,	4143ull,	0},
+	{"RTL"                         ,	16,	16,	928,	"R/W",	0,	1,	12429ull,	0},
+	{"OMR"                         ,	0,	32,	929,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	930,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_8_14"               ,	8,	7,	930,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	930,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	930,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	930,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	930,	"RO",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	931,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	931,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	931,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	931,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	931,	"R/W",	0,	0,	3ull,	3ull},
+	{"EASPML1"                     ,	30,	1,	931,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	931,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	932,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	932,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	932,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	932,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	932,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	932,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	932,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	932,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	932,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	932,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_22_31"              ,	22,	10,	932,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	933,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	933,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	933,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	933,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	933,	"R/W",	0,	0,	0ull,	0ull},
+	{"MFUNCN"                      ,	0,	8,	934,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_13"               ,	8,	6,	934,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	934,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	934,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	934,	"R/W",	0,	0,	0ull,	0ull},
+	{"CX_NFUNC"                    ,	29,	3,	934,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPIV"                       ,	0,	11,	935,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	935,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	935,	"R/W",	0,	0,	1ull,	1ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	936,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	936,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_DABORT_4UCPL"              ,	2,	1,	936,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_HANDLE_FLUSH"              ,	3,	1,	936,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_31"               ,	4,	28,	936,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	937,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	938,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	939,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	939,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	939,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	940,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	940,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	940,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	941,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	941,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	941,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	942,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	942,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	942,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	942,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	943,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	943,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	943,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	943,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	944,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	944,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	944,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	944,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	945,	"R/W",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	945,	"R/W",	0,	0,	96ull,	96ull},
+	{"RESERVED_20_20"              ,	20,	1,	945,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	945,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	945,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	945,	"R/W",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	945,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	946,	"R/W",	0,	0,	32ull,	32ull},
+	{"HEADER_CREDITS"              ,	12,	8,	946,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_20"              ,	20,	1,	946,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	946,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	946,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	947,	"R/W",	0,	0,	256ull,	256ull},
+	{"HEADER_CREDITS"              ,	12,	8,	947,	"R/W",	0,	0,	127ull,	127ull},
+	{"RESERVED_20_20"              ,	20,	1,	947,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	947,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	947,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	948,	"R/W",	0,	0,	392ull,	392ull},
+	{"RESERVED_14_15"              ,	14,	2,	948,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	948,	"R/W",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	948,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	949,	"R/W",	0,	0,	136ull,	136ull},
+	{"RESERVED_14_15"              ,	14,	2,	949,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	949,	"R/W",	0,	0,	38ull,	38ull},
+	{"RESERVED_26_31"              ,	26,	6,	949,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	950,	"R/W",	0,	0,	679ull,	679ull},
+	{"RESERVED_14_15"              ,	14,	2,	950,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	950,	"R/W",	0,	0,	133ull,	133ull},
+	{"RESERVED_26_31"              ,	26,	6,	950,	"RAZ",	1,	1,	0,	0},
+	{"N_FTS"                       ,	0,	8,	951,	"R/W",	0,	0,	128ull,	128ull},
+	{"LE"                          ,	8,	9,	951,	"R/W",	0,	0,	8ull,	8ull},
+	{"DSC"                         ,	17,	1,	951,	"R/W",	0,	0,	0ull,	0ull},
+	{"CPYTS"                       ,	18,	1,	951,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTCRB"                       ,	19,	1,	951,	"R/W",	0,	0,	0ull,	0ull},
+	{"S_D_E"                       ,	20,	1,	951,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	951,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	952,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	953,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	954,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	954,	"R/W",	0,	0,	1ull,	1ull},
+	{"HFD"                         ,	6,	1,	954,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAUSE"                       ,	7,	2,	954,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	954,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	954,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	954,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NP"                          ,	15,	1,	954,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	954,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_11"               ,	0,	12,	955,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_THD"                    ,	12,	1,	955,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_TFD"                    ,	13,	1,	955,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_XHD"                    ,	14,	1,	955,	"RO",	0,	0,	1ull,	1ull},
+	{"THOU_XFD"                    ,	15,	1,	955,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	955,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	956,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	956,	"RO",	0,	0,	0ull,	0ull},
+	{"HFD"                         ,	6,	1,	956,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	7,	2,	956,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	956,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	956,	"RO",	0,	0,	0ull,	0ull},
+	{"ACK"                         ,	14,	1,	956,	"RO",	0,	1,	0ull,	0},
+	{"NP"                          ,	15,	1,	956,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	956,	"RAZ",	1,	1,	0,	0},
+	{"LINK_OK"                     ,	0,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	1,	1,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	2,	1,	957,	"RO",	0,	0,	0ull,	1ull},
+	{"SPD"                         ,	3,	2,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	5,	2,	957,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	957,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD_EN"                   ,	0,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"XMIT_EN"                     ,	1,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_ERR_EN"                   ,	2,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFU_EN"                   ,	3,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFO_EN"                   ,	4,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXBAD_EN"                    ,	5,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXERR_EN"                    ,	6,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	7,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXLOCK_EN"                   ,	8,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_BAD_EN"                   ,	9,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNC_BAD_EN"                 ,	10,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"DUP"                         ,	11,	1,	958,	"R/W",	0,	0,	0ull,	1ull},
+	{"DBG_SYNC_EN"                 ,	12,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	958,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD"                      ,	0,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	1,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_ERR"                      ,	2,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFU"                      ,	3,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFO"                      ,	4,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXBAD"                       ,	5,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXERR"                       ,	6,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	7,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXLOCK"                      ,	8,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	9,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	10,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	11,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBG_SYNC"                    ,	12,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	959,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	16,	960,	"R/W",	0,	1,	1094ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	960,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	961,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	961,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	961,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	961,	"RAZ",	1,	1,	0,	0},
+	{"SAMP_PT"                     ,	0,	7,	962,	"R/W",	0,	1,	1ull,	0},
+	{"AN_OVRD"                     ,	7,	1,	962,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE"                        ,	8,	1,	962,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAC_PHY"                     ,	9,	1,	962,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK2"                    ,	10,	1,	962,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMXENO"                      ,	11,	1,	962,	"R/W",	0,	0,	0ull,	0ull},
+	{"SGMII"                       ,	12,	1,	962,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	962,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	963,	"RAZ",	1,	1,	0,	0},
+	{"UNI"                         ,	5,	1,	963,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDMSB"                      ,	6,	1,	963,	"R/W",	0,	0,	1ull,	1ull},
+	{"COLTST"                      ,	7,	1,	963,	"R/W",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	8,	1,	963,	"R/W",	0,	0,	1ull,	1ull},
+	{"RST_AN"                      ,	9,	1,	963,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	963,	"RAZ",	1,	1,	0,	0},
+	{"PWR_DN"                      ,	11,	1,	963,	"R/W",	0,	0,	1ull,	0ull},
+	{"AN_EN"                       ,	12,	1,	963,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDLSB"                      ,	13,	1,	963,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK1"                    ,	14,	1,	963,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	963,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	963,	"RAZ",	1,	1,	0,	0},
+	{"EXTND"                       ,	0,	1,	964,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	964,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LNK_ST"                      ,	2,	1,	964,	"RO",	0,	0,	0ull,	1ull},
+	{"AN_ABIL"                     ,	3,	1,	964,	"RO",	0,	0,	1ull,	1ull},
+	{"RM_FLT"                      ,	4,	1,	964,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	5,	1,	964,	"RO",	0,	0,	0ull,	0ull},
+	{"PRB_SUP"                     ,	6,	1,	964,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_7"                ,	7,	1,	964,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EXT_ST"                      ,	8,	1,	964,	"RO",	0,	0,	1ull,	1ull},
+	{"HUN_T2HD"                    ,	9,	1,	964,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T2FD"                    ,	10,	1,	964,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_HD"                      ,	11,	1,	964,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_FD"                      ,	12,	1,	964,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XHD"                     ,	13,	1,	964,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XFD"                     ,	14,	1,	964,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T4"                      ,	15,	1,	964,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	964,	"RAZ",	1,	1,	0,	0},
+	{"AN_ST"                       ,	0,	4,	965,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	4,	1,	965,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	5,	4,	965,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	9,	1,	965,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_ST"                       ,	10,	5,	965,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_BAD"                      ,	15,	1,	965,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	965,	"RAZ",	1,	1,	0,	0},
+	{"BIT_LOCK"                    ,	0,	1,	966,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	1,	1,	966,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	966,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	967,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	967,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	967,	"R/W",	0,	0,	2ull,	2ull},
+	{"DUP"                         ,	12,	1,	967,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_13"              ,	13,	1,	967,	"RAZ",	0,	1,	0ull,	0},
+	{"ACK"                         ,	14,	1,	967,	"RO",	0,	0,	0ull,	0ull},
+	{"LINK"                        ,	15,	1,	967,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	967,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	968,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	968,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	968,	"RO",	0,	0,	0ull,	2ull},
+	{"DUP"                         ,	12,	1,	968,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_14"              ,	13,	2,	968,	"RAZ",	0,	1,	0ull,	0},
+	{"LINK"                        ,	15,	1,	968,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	968,	"RAZ",	1,	1,	0,	0},
+	{"ORD_ST"                      ,	0,	4,	969,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_BAD"                      ,	4,	1,	969,	"RO",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	5,	2,	969,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	969,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	970,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	970,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTORXPL"                    ,	2,	1,	970,	"RO",	0,	0,	0ull,	0ull},
+	{"RXOVRD"                      ,	3,	1,	970,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	970,	"RAZ",	1,	1,	0,	0},
+	{"L0SYNC"                      ,	0,	1,	971,	"RO",	0,	0,	0ull,	1ull},
+	{"L1SYNC"                      ,	1,	1,	971,	"RO",	0,	0,	0ull,	1ull},
+	{"L2SYNC"                      ,	2,	1,	971,	"RO",	0,	0,	0ull,	1ull},
+	{"L3SYNC"                      ,	3,	1,	971,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_10"               ,	4,	7,	971,	"RAZ",	1,	1,	0,	0},
+	{"PATTST"                      ,	11,	1,	971,	"RO",	0,	0,	0ull,	0ull},
+	{"ALIGND"                      ,	12,	1,	971,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_63"              ,	13,	51,	971,	"RAZ",	1,	1,	0,	0},
+	{"BIST_STATUS"                 ,	0,	1,	972,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	972,	"RAZ",	1,	1,	0,	0},
+	{"BITLCK0"                     ,	0,	1,	973,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK1"                     ,	1,	1,	973,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK2"                     ,	2,	1,	973,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK3"                     ,	3,	1,	973,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	973,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	974,	"RAZ",	1,	1,	0,	0},
+	{"SPD"                         ,	2,	4,	974,	"RO",	0,	0,	0ull,	0ull},
+	{"SPDSEL0"                     ,	6,	1,	974,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_10"               ,	7,	4,	974,	"RAZ",	1,	1,	0,	0},
+	{"LO_PWR"                      ,	11,	1,	974,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_12_12"              ,	12,	1,	974,	"RAZ",	1,	1,	0,	0},
+	{"SPDSEL1"                     ,	13,	1,	974,	"RO",	0,	0,	1ull,	1ull},
+	{"LOOPBCK1"                    ,	14,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	974,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	974,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	2,	975,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	975,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT_EN"                    ,	0,	1,	976,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	1,	1,	976,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXSYNBAD_EN"                 ,	2,	1,	976,	"R/W",	0,	0,	0ull,	1ull},
+	{"BITLCKLS_EN"                 ,	3,	1,	976,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNLOS_EN"                   ,	4,	1,	976,	"R/W",	0,	0,	0ull,	1ull},
+	{"ALGNLOS_EN"                  ,	5,	1,	976,	"R/W",	0,	0,	0ull,	1ull},
+	{"DBG_SYNC_EN"                 ,	6,	1,	976,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	976,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT"                       ,	0,	1,	977,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	1,	1,	977,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXSYNBAD"                    ,	2,	1,	977,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BITLCKLS"                    ,	3,	1,	977,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNLOS"                      ,	4,	1,	977,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALGNLOS"                     ,	5,	1,	977,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBG_SYNC"                    ,	6,	1,	977,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	977,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	978,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	978,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	978,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DROP_LN"                     ,	4,	2,	978,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENC_MODE"                    ,	6,	1,	978,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	978,	"RAZ",	1,	1,	0,	0},
+	{"GMXENO"                      ,	0,	1,	979,	"R/W",	0,	0,	0ull,	0ull},
+	{"XAUI"                        ,	1,	1,	979,	"RO",	1,	1,	0,	0},
+	{"RX_SWAP"                     ,	2,	1,	979,	"R/W",	0,	1,	0ull,	0},
+	{"TX_SWAP"                     ,	3,	1,	979,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	979,	"RAZ",	1,	1,	0,	0},
+	{"SYNC0ST"                     ,	0,	4,	980,	"RO",	0,	1,	0ull,	0},
+	{"SYNC1ST"                     ,	4,	4,	980,	"RO",	0,	1,	0ull,	0},
+	{"SYNC2ST"                     ,	8,	4,	980,	"RO",	0,	1,	0ull,	0},
+	{"SYNC3ST"                     ,	12,	4,	980,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	980,	"RAZ",	1,	1,	0,	0},
+	{"TENGB"                       ,	0,	1,	981,	"RO",	0,	0,	1ull,	1ull},
+	{"TENPASST"                    ,	1,	1,	981,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	981,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	982,	"RAZ",	1,	1,	0,	0},
+	{"LPABLE"                      ,	1,	1,	982,	"RO",	0,	0,	1ull,	1ull},
+	{"RCV_LNK"                     ,	2,	1,	982,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_6"                ,	3,	4,	982,	"RAZ",	1,	1,	0,	0},
+	{"FLT"                         ,	7,	1,	982,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	982,	"RAZ",	1,	1,	0,	0},
+	{"TENGB_R"                     ,	0,	1,	983,	"RO",	0,	0,	0ull,	0ull},
+	{"TENGB_X"                     ,	1,	1,	983,	"RO",	0,	0,	1ull,	1ull},
+	{"TENGB_W"                     ,	2,	1,	983,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_9"                ,	3,	7,	983,	"RAZ",	1,	1,	0,	0},
+	{"RCVFLT"                      ,	10,	1,	983,	"RC",	0,	0,	0ull,	0ull},
+	{"XMTFLT"                      ,	11,	1,	983,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_13"              ,	12,	2,	983,	"RAZ",	1,	1,	0,	0},
+	{"DEV"                         ,	14,	2,	983,	"RO",	0,	0,	2ull,	2ull},
+	{"RESERVED_16_63"              ,	16,	48,	983,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	984,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	984,	"R/W",	0,	0,	0ull,	0ull},
+	{"XOR_TXPLRT"                  ,	2,	4,	984,	"R/W",	0,	0,	0ull,	0ull},
+	{"XOR_RXPLRT"                  ,	6,	4,	984,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	984,	"RAZ",	1,	1,	0,	0},
+	{"TX_ST"                       ,	0,	3,	985,	"RO",	0,	1,	0ull,	0},
+	{"RX_ST"                       ,	3,	2,	985,	"RO",	0,	1,	0ull,	0},
+	{"ALGN_ST"                     ,	5,	3,	985,	"RO",	0,	1,	0ull,	0},
+	{"RXBAD"                       ,	8,	1,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN0BAD"                     ,	9,	1,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN1BAD"                     ,	10,	1,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN2BAD"                     ,	11,	1,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN3BAD"                     ,	12,	1,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"TERM_ERR"                    ,	13,	1,	985,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	985,	"RAZ",	1,	1,	0,	0},
+	{"ADDR_V"                      ,	0,	1,	986,	"R/W",	0,	1,	0ull,	0},
+	{"END_SWP"                     ,	1,	2,	986,	"R/W",	0,	1,	0ull,	0},
+	{"CA"                          ,	3,	1,	986,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR_IDX"                    ,	4,	16,	986,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	986,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	987,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	3,	35,	987,	"R/W",	0,	0,	34359738367ull,	34359738367ull},
+	{"RESERVED_38_63"              ,	38,	26,	987,	"RAZ",	1,	1,	0,	0},
+	{"BAR2_CAX"                    ,	0,	1,	988,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	1,	2,	988,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	3,	1,	988,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR1_SIZ"                    ,	4,	3,	988,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_63"               ,	7,	57,	988,	"RAZ",	1,	1,	0,	0},
+	{"SOT"                         ,	0,	1,	989,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR0"                      ,	1,	1,	989,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR1"                      ,	2,	1,	989,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA3"                     ,	3,	1,	989,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA2"                     ,	4,	1,	989,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA1"                     ,	5,	1,	989,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA0"                     ,	6,	1,	989,	"RO",	0,	0,	0ull,	0ull},
+	{"RETRY"                       ,	7,	1,	989,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	989,	"RAZ",	1,	1,	0,	0},
+	{"PPF"                         ,	0,	1,	990,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TC0"                     ,	1,	1,	990,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TCF1"                    ,	2,	1,	990,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TNF"                     ,	3,	1,	990,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF0"                    ,	4,	1,	990,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF1"                    ,	5,	1,	990,	"RO",	0,	0,	0ull,	0ull},
+	{"PEAI_P2E"                    ,	6,	1,	990,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_P"                       ,	7,	1,	990,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_N"                       ,	8,	1,	990,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_CPL"                     ,	9,	1,	990,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	990,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	32,	991,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	991,	"R/W",	0,	1,	0ull,	0},
+	{"ADDR"                        ,	0,	32,	992,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	992,	"R/W",	0,	1,	0ull,	0},
+	{"TAG"                         ,	0,	32,	993,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	993,	"RAZ",	1,	1,	0,	0},
+	{"INV_LCRC"                    ,	0,	1,	994,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_ECRC"                    ,	1,	1,	994,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAST_LM"                     ,	2,	1,	994,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_CTLP"                     ,	3,	1,	994,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_ENB"                     ,	4,	1,	994,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLY_ONE"                     ,	5,	1,	994,	"R/W",	0,	0,	0ull,	0ull},
+	{"NF_ECRC"                     ,	6,	1,	994,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_8"                ,	7,	2,	994,	"R/W",	0,	0,	0ull,	0ull},
+	{"OB_P_CMD"                    ,	9,	1,	994,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XPME"                     ,	10,	1,	994,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XTOFF"                    ,	11,	1,	994,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	994,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CFG_RTRY"                    ,	16,	16,	994,	"R/W",	0,	0,	0ull,	32ull},
+	{"RESERVED_32_33"              ,	32,	2,	994,	"RAZ",	1,	1,	0,	0},
+	{"PBUS"                        ,	34,	8,	994,	"RO",	1,	1,	0,	0},
+	{"DNUM"                        ,	42,	5,	994,	"RO",	1,	1,	0,	0},
+	{"AUTO_SD"                     ,	47,	1,	994,	"RO",	1,	1,	0,	0},
+	{"RESERVED_48_63"              ,	48,	16,	994,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	995,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	995,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	996,	"RAZ",	1,	1,	0,	0},
+	{"AUX_EN"                      ,	0,	1,	997,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_EN"                       ,	1,	1,	997,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_STAT"                     ,	2,	1,	997,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_DST"                      ,	3,	1,	997,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	997,	"RO",	1,	1,	0,	0},
+	{"NUM"                         ,	0,	6,	998,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	998,	"RAZ",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	999,	"R/W",	0,	0,	0ull,	1ull},
+	{"SE"                          ,	1,	1,	999,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEI"                        ,	2,	1,	999,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEM"                        ,	3,	1,	999,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B1"                       ,	4,	1,	999,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B2"                       ,	5,	1,	999,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_BX"                       ,	6,	1,	999,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B1"                       ,	7,	1,	999,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B2"                       ,	8,	1,	999,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_BX"                       ,	9,	1,	999,	"R/W",	0,	0,	0ull,	1ull},
+	{"EXC"                         ,	10,	1,	999,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDLK"                        ,	11,	1,	999,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_ER"                      ,	12,	1,	999,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_DR"                      ,	13,	1,	999,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_14_63"              ,	14,	50,	999,	"RAZ",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	1000,	"R/W",	0,	0,	0ull,	1ull},
+	{"SE"                          ,	1,	1,	1000,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEI"                        ,	2,	1,	1000,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEM"                        ,	3,	1,	1000,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B1"                       ,	4,	1,	1000,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B2"                       ,	5,	1,	1000,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_BX"                       ,	6,	1,	1000,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B1"                       ,	7,	1,	1000,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B2"                       ,	8,	1,	1000,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_BX"                       ,	9,	1,	1000,	"R/W",	0,	0,	0ull,	1ull},
+	{"EXC"                         ,	10,	1,	1000,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDLK"                        ,	11,	1,	1000,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_ER"                      ,	12,	1,	1000,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_DR"                      ,	13,	1,	1000,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_14_63"              ,	14,	50,	1000,	"RAZ",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"SE"                          ,	1,	1,	1001,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PMEI"                        ,	2,	1,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEM"                        ,	3,	1,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"UP_B1"                       ,	4,	1,	1001,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UP_B2"                       ,	5,	1,	1001,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UP_BX"                       ,	6,	1,	1001,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_B1"                       ,	7,	1,	1001,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_B2"                       ,	8,	1,	1001,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_BX"                       ,	9,	1,	1001,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EXC"                         ,	10,	1,	1001,	"RO",	0,	0,	0ull,	0ull},
+	{"RDLK"                        ,	11,	1,	1001,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS_ER"                      ,	12,	1,	1001,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS_DR"                      ,	13,	1,	1001,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	1001,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_13"               ,	0,	14,	1002,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	14,	50,	1002,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_25"               ,	0,	26,	1003,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	26,	38,	1003,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_40"               ,	0,	41,	1004,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	41,	23,	1004,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_11"               ,	0,	12,	1005,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	12,	52,	1005,	"R/W",	0,	1,	4503599627370495ull,	0},
+	{"RESERVED_0_11"               ,	0,	12,	1006,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	12,	52,	1006,	"R/W",	0,	1,	4503599627370495ull,	0},
+	{"SLI_P"                       ,	0,	8,	1007,	"R/W",	0,	0,	128ull,	128ull},
+	{"SLI_NP"                      ,	8,	8,	1007,	"R/W",	0,	0,	16ull,	16ull},
+	{"SLI_CPL"                     ,	16,	8,	1007,	"R/W",	0,	0,	128ull,	128ull},
+	{"PEM_P"                       ,	24,	8,	1007,	"R/W",	0,	0,	128ull,	128ull},
+	{"PEM_NP"                      ,	32,	8,	1007,	"R/W",	0,	0,	16ull,	16ull},
+	{"PEM_CPL"                     ,	40,	8,	1007,	"R/W",	0,	0,	128ull,	128ull},
+	{"PEAI_PPF"                    ,	48,	8,	1007,	"R/W",	0,	0,	128ull,	128ull},
+	{"RESERVED_56_63"              ,	56,	8,	1007,	"RAZ",	1,	1,	0,	0},
+	{"SKIP1"                       ,	0,	7,	1008,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	1008,	"RAZ",	1,	1,	0,	0},
+	{"SKIP2"                       ,	8,	7,	1008,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	1008,	"RAZ",	1,	1,	0,	0},
+	{"SKIP3"                       ,	16,	7,	1008,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_31"              ,	23,	9,	1008,	"RAZ",	1,	1,	0,	0},
+	{"BIT0"                        ,	32,	6,	1008,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_39"              ,	38,	2,	1008,	"RAZ",	1,	1,	0,	0},
+	{"BIT1"                        ,	40,	6,	1008,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_46_55"              ,	46,	10,	1008,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	56,	1,	1008,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_57_63"              ,	57,	7,	1008,	"RAZ",	1,	1,	0,	0},
+	{"LOWATER"                     ,	0,	5,	1009,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_5_7"                ,	5,	3,	1009,	"RAZ",	0,	1,	0ull,	0},
+	{"HIWATER"                     ,	8,	5,	1009,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_13_62"              ,	13,	50,	1009,	"RAZ",	0,	1,	0ull,	0},
+	{"BCKPRS"                      ,	63,	1,	1009,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	22,	1010,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	1010,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	1011,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_15"               ,	7,	9,	1011,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	16,	9,	1011,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_25_31"              ,	25,	7,	1011,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	32,	8,	1011,	"R/W",	0,	1,	0ull,	0},
+	{"UPPER_TAG"                   ,	40,	16,	1011,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	1011,	"RAZ",	1,	1,	0,	0},
+	{"POS0"                        ,	0,	7,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"POS0_VAL"                    ,	7,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"POS1"                        ,	8,	7,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"POS1_VAL"                    ,	15,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"POS2"                        ,	16,	7,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"POS2_VAL"                    ,	23,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"POS3"                        ,	24,	7,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"POS3_VAL"                    ,	31,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"POS4"                        ,	32,	7,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"POS4_VAL"                    ,	39,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"POS5"                        ,	40,	7,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"POS5_VAL"                    ,	47,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"POS6"                        ,	48,	7,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"POS6_VAL"                    ,	55,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"POS7"                        ,	56,	7,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"POS7_VAL"                    ,	63,	1,	1012,	"R/W",	0,	1,	0ull,	0},
+	{"QOS"                         ,	0,	3,	1013,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_7"                ,	3,	5,	1013,	"RAZ",	1,	1,	0,	0},
+	{"TT"                          ,	8,	2,	1013,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	1013,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	16,	6,	1013,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_31"              ,	22,	10,	1013,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	32,	8,	1013,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_59"              ,	40,	20,	1013,	"RAZ",	1,	1,	0,	0},
+	{"QOS_EN"                      ,	60,	1,	1013,	"R/W",	0,	1,	0ull,	0},
+	{"TT_EN"                       ,	61,	1,	1013,	"R/W",	0,	1,	0ull,	0},
+	{"GRP_EN"                      ,	62,	1,	1013,	"R/W",	0,	1,	0ull,	0},
+	{"TAG_EN"                      ,	63,	1,	1013,	"R/W",	0,	1,	0ull,	0},
+	{"CLKEN"                       ,	0,	1,	1014,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1014,	"RAZ",	0,	1,	0ull,	0},
+	{"DPRT"                        ,	0,	16,	1015,	"R/W",	0,	0,	0ull,	0ull},
+	{"UDP"                         ,	16,	1,	1015,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP"                         ,	17,	1,	1015,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	1015,	"RAZ",	1,	1,	0,	0},
+	{"MAP0"                        ,	0,	4,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	1016,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP0"                        ,	0,	4,	1017,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	1017,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	1017,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	1017,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	1017,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	1017,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	1017,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	1017,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	1017,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	1017,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	1017,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	1017,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	1017,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	1017,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	1017,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	1017,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINLEN"                      ,	0,	16,	1018,	"R/W",	0,	0,	64ull,	64ull},
+	{"MAXLEN"                      ,	16,	16,	1018,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_32_63"              ,	32,	32,	1018,	"RAZ",	1,	1,	0,	0},
+	{"NIP_SHF"                     ,	0,	3,	1019,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	1019,	"RAZ",	1,	1,	0,	0},
+	{"RAW_SHF"                     ,	8,	3,	1019,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	1019,	"RAZ",	1,	1,	0,	0},
+	{"MAX_L2"                      ,	16,	1,	1019,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_UDP"                     ,	17,	1,	1019,	"R/W",	0,	0,	1ull,	1ull},
+	{"TAG_SYN"                     ,	18,	1,	1019,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	1019,	"RAZ",	1,	1,	0,	0},
+	{"IP_CHK"                      ,	0,	1,	1020,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_MAL"                      ,	1,	1,	1020,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_HOP"                      ,	2,	1,	1020,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP4_OPTS"                    ,	3,	1,	1020,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP6_EEXT"                    ,	4,	2,	1020,	"R/W",	0,	0,	1ull,	3ull},
+	{"RESERVED_6_7"                ,	6,	2,	1020,	"RAZ",	1,	1,	0,	0},
+	{"L4_MAL"                      ,	8,	1,	1020,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_PRT"                      ,	9,	1,	1020,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_CHK"                      ,	10,	1,	1020,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_LEN"                      ,	11,	1,	1020,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCP_FLAG"                    ,	12,	1,	1020,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2_MAL"                      ,	13,	1,	1020,	"R/W",	0,	0,	1ull,	1ull},
+	{"VS_QOS"                      ,	14,	1,	1020,	"R/W",	0,	0,	0ull,	0ull},
+	{"VS_WQE"                      ,	15,	1,	1020,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNRS"                       ,	16,	1,	1020,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_23"              ,	17,	7,	1020,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_SID"                 ,	24,	1,	1020,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_SCMD"                ,	25,	1,	1020,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_TVID"                ,	26,	1,	1020,	"R/W",	0,	0,	0ull,	0ull},
+	{"IHMSK_DIS"                   ,	27,	1,	1020,	"R/W",	0,	0,	0ull,	0ull},
+	{"EGRP_DIS"                    ,	28,	1,	1020,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	1020,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	1021,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	1022,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	1022,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	1022,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	1022,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	1022,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	1022,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	1022,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	1022,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	1022,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	1022,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	1022,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	1022,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	1022,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	1022,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	3,	1023,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	1023,	"RAZ",	1,	1,	0,	0},
+	{"VLAN2_QOS"                   ,	0,	3,	1024,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1024,	"RAZ",	1,	1,	0,	0},
+	{"HG2_QOS"                     ,	4,	3,	1024,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	1024,	"RAZ",	1,	1,	0,	0},
+	{"DIFF2_QOS"                   ,	8,	3,	1024,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	1024,	"RAZ",	1,	1,	0,	0},
+	{"VLAN2_BPID"                  ,	16,	6,	1024,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1024,	"RAZ",	1,	1,	0,	0},
+	{"HG2_BPID"                    ,	24,	6,	1024,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	1024,	"RAZ",	1,	1,	0,	0},
+	{"DIFF2_BPID"                  ,	32,	6,	1024,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_39"              ,	38,	2,	1024,	"RAZ",	1,	1,	0,	0},
+	{"VLAN2_PADD"                  ,	40,	8,	1024,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2_PADD"                    ,	48,	8,	1024,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIFF2_PADD"                  ,	56,	8,	1024,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKIP"                        ,	0,	7,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	1025,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	2,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_EN"                      ,	10,	1,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"HIGIG_EN"                    ,	11,	1,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRC_EN"                      ,	12,	1,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	1025,	"RAZ",	1,	1,	0,	0},
+	{"QOS_VLAN"                    ,	16,	1,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_DIFF"                    ,	17,	1,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VOD"                     ,	18,	1,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	1025,	"RAZ",	0,	0,	0ull,	0ull},
+	{"QOS_WAT"                     ,	20,	4,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS"                         ,	24,	3,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_QOS"                      ,	27,	1,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT"                     ,	28,	4,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"INST_HDR"                    ,	32,	1,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"DYN_RS"                      ,	33,	1,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_INC"                     ,	34,	2,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWDRP"                      ,	36,	1,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	1025,	"RAZ",	1,	1,	0,	0},
+	{"QOS_WAT_47"                  ,	40,	4,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT_47"                  ,	44,	4,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR_EN"                   ,	48,	1,	1025,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR_EN"                   ,	49,	1,	1025,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR_EN"                   ,	50,	1,	1025,	"R/W",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	51,	1,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	52,	1,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_CHK_SEL"                 ,	53,	1,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"IH_PRI"                      ,	54,	1,	1025,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	1025,	"RAZ",	1,	1,	0,	0},
+	{"BPID"                        ,	0,	6,	1026,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_15"               ,	6,	10,	1026,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	16,	8,	1026,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1026,	"RAZ",	1,	1,	0,	0},
+	{"BSEL_EN"                     ,	32,	1,	1026,	"R/W",	0,	0,	0ull,	0ull},
+	{"BSEL_NUM"                    ,	33,	2,	1026,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_35"              ,	35,	1,	1026,	"RAZ",	1,	1,	0,	0},
+	{"ALT_SKP_EN"                  ,	36,	1,	1026,	"R/W",	0,	1,	0ull,	0},
+	{"ALT_SKP_SEL"                 ,	37,	2,	1026,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_39_63"              ,	39,	25,	1026,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	0,	4,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"NON_TAG_TYPE"                ,	4,	2,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_TAG_TYPE"                ,	6,	2,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_TAG_TYPE"                ,	8,	2,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP4_TAG_TYPE"               ,	10,	2,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP6_TAG_TYPE"               ,	12,	2,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SRC_FLAG"                ,	14,	1,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SRC_FLAG"                ,	15,	1,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DST_FLAG"                ,	16,	1,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DST_FLAG"                ,	17,	1,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_PCTL_FLAG"               ,	18,	1,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_NXTH_FLAG"               ,	19,	1,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SPRT_FLAG"               ,	20,	1,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SPRT_FLAG"               ,	21,	1,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DPRT_FLAG"               ,	22,	1,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DPRT_FLAG"               ,	23,	1,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_PRT_FLAG"                ,	24,	1,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VLAN"                    ,	25,	1,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VS"                      ,	26,	2,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_MODE"                    ,	28,	2,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG_MSKIP"                ,	30,	1,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG"                      ,	31,	1,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGMASK"                  ,	32,	4,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGBASE"                  ,	36,	4,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_MSB"                     ,	40,	2,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_43"              ,	42,	2,	1027,	"RAZ",	1,	1,	0,	0},
+	{"GRPTAGMASK_MSB"              ,	44,	2,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_47"              ,	46,	2,	1027,	"RAZ",	1,	1,	0,	0},
+	{"GRPTAGBASE_MSB"              ,	48,	2,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	1027,	"RAZ",	1,	1,	0,	0},
+	{"INC_HWCHK"                   ,	52,	1,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORTADD_EN"                  ,	53,	1,	1027,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	1027,	"RAZ",	1,	1,	0,	0},
+	{"MATCH_VALUE"                 ,	0,	16,	1028,	"R/W",	0,	0,	0ull,	0ull},
+	{"MATCH_TYPE"                  ,	16,	3,	1028,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	1028,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	20,	3,	1028,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	1028,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	24,	6,	1028,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	1028,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	32,	16,	1028,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1028,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	0,	56,	1029,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	1029,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	0,	1,	1030,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1030,	"RAZ",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	1031,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	1031,	"R/W",	0,	1,	0ull,	0},
+	{"MCAST"                       ,	0,	32,	1032,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	1032,	"R/W",	0,	1,	0ull,	0},
+	{"MCAST"                       ,	0,	32,	1033,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	1033,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	1034,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	1034,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	1035,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	1035,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	1036,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	1036,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	1037,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	1037,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	1038,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	1038,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	1039,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	1039,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	1040,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	1040,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	1041,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	1041,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	1042,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	1042,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	1043,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_7"                ,	1,	7,	1043,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	1,	1043,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	1043,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	1044,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	1044,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	1045,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	1045,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	1046,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1046,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT"                    ,	0,	64,	1047,	"R/W",	0,	0,	18446744073709551615ull,	18446744073709551615ull},
+	{"EN"                          ,	0,	8,	1048,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1048,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1049,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	1050,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	1050,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1050,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	1051,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	1051,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	1051,	"RO",	1,	1,	0,	0},
+	{"TYPE0"                       ,	0,	16,	1052,	"R/W",	0,	0,	33024ull,	33024ull},
+	{"TYPE1"                       ,	16,	16,	1052,	"R/W",	0,	0,	33024ull,	33024ull},
+	{"TYPE2"                       ,	32,	16,	1052,	"R/W",	0,	0,	33024ull,	33024ull},
+	{"TYPE3"                       ,	48,	16,	1052,	"R/W",	0,	0,	33024ull,	33024ull},
+	{"COUNT"                       ,	0,	32,	1053,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1053,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	1054,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1054,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	1055,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	1055,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	1055,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	1055,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	1056,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	1056,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	1056,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	1056,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	1056,	"RO",	1,	0,	0,	0ull},
+	{"PTRS2"                       ,	0,	17,	1057,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	1057,	"RO",	1,	1,	0,	0},
+	{"PTRS1"                       ,	32,	17,	1057,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	1057,	"RO",	1,	1,	0,	0},
+	{"MOD"                         ,	0,	3,	1058,	"RO",	1,	0,	0,	0ull},
+	{"CNT"                         ,	3,	13,	1058,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	16,	1,	1058,	"RO",	1,	0,	0,	0ull},
+	{"LEN"                         ,	17,	1,	1058,	"RO",	1,	0,	0,	0ull},
+	{"SOP"                         ,	18,	1,	1058,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	19,	3,	1058,	"RO",	1,	0,	0,	0ull},
+	{"MAJ"                         ,	22,	1,	1058,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	1058,	"RO",	1,	1,	0,	0},
+	{"STATE"                       ,	0,	64,	1059,	"RO",	1,	1,	0,	0},
+	{"STATE"                       ,	0,	64,	1060,	"RO",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	1061,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	1061,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	1061,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	1061,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	1061,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	1062,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	3,	1063,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	3,	2,	1063,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	5,	1,	1063,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	6,	1,	1063,	"RO",	1,	0,	0,	0ull},
+	{"CHK_ONCE"                    ,	7,	1,	1063,	"RO",	1,	0,	0,	0ull},
+	{"INIT_DWRITE"                 ,	8,	1,	1063,	"RO",	1,	0,	0,	0ull},
+	{"DREAD_SOP"                   ,	9,	1,	1063,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	10,	2,	1063,	"RO",	1,	0,	0,	0ull},
+	{"CMND_OFF"                    ,	12,	6,	1063,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	18,	16,	1063,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	34,	6,	1063,	"RO",	1,	0,	0,	0ull},
+	{"CURR_OFF"                    ,	40,	16,	1063,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	56,	8,	1063,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	0,	8,	1064,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	8,	40,	1064,	"RO",	1,	0,	0,	0ull},
+	{"NXT_INFLT"                   ,	48,	6,	1064,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR_3"                     ,	54,	1,	1064,	"RO",	1,	0,	0,	0ull},
+	{"PTP"                         ,	55,	1,	1064,	"RO",	1,	0,	0,	0ull},
+	{"UID_2"                       ,	56,	1,	1064,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_57_63"              ,	57,	7,	1064,	"RO",	1,	1,	0,	0},
+	{"QID_BASE"                    ,	0,	8,	1065,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	8,	4,	1065,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFMAX"                  ,	12,	4,	1065,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	16,	5,	1065,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	21,	3,	1065,	"RO",	1,	0,	0,	0ull},
+	{"STATC"                       ,	24,	1,	1065,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	25,	1,	1065,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTED"                   ,	26,	1,	1065,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	27,	1,	1065,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	1065,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFTHS"                  ,	29,	4,	1065,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFRES"                  ,	33,	4,	1065,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	1065,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	7,	1066,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	7,	7,	1066,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	14,	33,	1066,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	47,	13,	1066,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	60,	1,	1066,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	61,	3,	1066,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	5,	1067,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	5,	1,	1067,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	6,	1,	1067,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	7,	1,	1067,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	8,	1,	1067,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_9_15"               ,	9,	7,	1067,	"RO",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	16,	20,	1067,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	36,	1,	1067,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	1067,	"RO",	1,	1,	0,	0},
+	{"PTRS3"                       ,	0,	17,	1068,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	1068,	"RO",	1,	1,	0,	0},
+	{"PTRS0"                       ,	32,	17,	1068,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	1068,	"RO",	1,	1,	0,	0},
+	{"IPID"                        ,	0,	7,	1069,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_7_7"                ,	7,	1,	1069,	"RAZ",	1,	1,	0,	0},
+	{"EID"                         ,	8,	5,	1069,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_13_15"              ,	13,	3,	1069,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	16,	5,	1069,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_21_23"              ,	21,	3,	1069,	"RAZ",	1,	1,	0,	0},
+	{"PIPE"                        ,	24,	7,	1069,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_31_49"              ,	31,	19,	1069,	"RAZ",	1,	1,	0,	0},
+	{"MIN_PKT"                     ,	50,	3,	1069,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	1069,	"R/W",	1,	1,	0,	0},
+	{"STATIC_P"                    ,	61,	1,	1069,	"R/W",	1,	0,	0,	0ull},
+	{"CRC"                         ,	62,	1,	1069,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_63_63"              ,	63,	1,	1069,	"R/W",	1,	0,	0,	0ull},
+	{"IPID"                        ,	0,	7,	1070,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_7_7"                ,	7,	1,	1070,	"RAZ",	1,	1,	0,	0},
+	{"EID"                         ,	8,	5,	1070,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_13_52"              ,	13,	40,	1070,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	1070,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_61_63"              ,	61,	3,	1070,	"RAZ",	1,	1,	0,	0},
+	{"QID"                         ,	0,	8,	1071,	"R/W",	1,	0,	0,	0ull},
+	{"IPID"                        ,	8,	7,	1071,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	1071,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	16,	5,	1071,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	21,	1,	1071,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	22,	31,	1071,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	1071,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	1071,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	1071,	"R/W",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	1071,	"R/W",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	8,	1072,	"R/W",	1,	0,	0,	0ull},
+	{"IPID"                        ,	8,	7,	1072,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_15_52"              ,	15,	38,	1072,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	1072,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	1072,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	7,	1073,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	1073,	"RAZ",	1,	1,	0,	0},
+	{"RATE_PKT"                    ,	8,	24,	1073,	"R/W",	1,	0,	0,	0ull},
+	{"RATE_WORD"                   ,	32,	19,	1073,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	1073,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	7,	1074,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	1074,	"RAZ",	1,	1,	0,	0},
+	{"RATE_LIM"                    ,	8,	24,	1074,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1074,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	5,	1075,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	1075,	"RAZ",	1,	1,	0,	0},
+	{"PACKET"                      ,	8,	6,	1075,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	1075,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	32,	15,	1075,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	1075,	"RAZ",	1,	1,	0,	0},
+	{"PIPE"                        ,	0,	7,	1076,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	1076,	"RAZ",	1,	1,	0,	0},
+	{"PACKET"                      ,	8,	6,	1076,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	1076,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	32,	15,	1076,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	1076,	"RAZ",	1,	1,	0,	0},
+	{"DAT_PTR"                     ,	0,	4,	1077,	"RO",	1,	0,	0,	0ull},
+	{"DAT_DAT"                     ,	4,	2,	1077,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CTL"                     ,	6,	2,	1077,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QSB"                     ,	8,	3,	1077,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QCB"                     ,	11,	2,	1077,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	13,	2,	1077,	"RO",	1,	0,	0,	0ull},
+	{"PRT_PSB"                     ,	15,	6,	1077,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_21_21"              ,	21,	1,	1077,	"RAZ",	1,	1,	0,	0},
+	{"PRT_PSB7"                    ,	22,	1,	1077,	"RO",	1,	0,	0,	0ull},
+	{"PRT_NXT"                     ,	23,	1,	1077,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CHK"                     ,	24,	3,	1077,	"RO",	1,	0,	0,	0ull},
+	{"OUT_WIF"                     ,	27,	1,	1077,	"RO",	1,	0,	0,	0ull},
+	{"OUT_STA"                     ,	28,	1,	1077,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CTL"                     ,	29,	2,	1077,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1077,	"RAZ",	1,	1,	0,	0},
+	{"OUT_DAT"                     ,	32,	1,	1077,	"RO",	1,	0,	0,	0ull},
+	{"IOB"                         ,	33,	1,	1077,	"RO",	1,	0,	0,	0ull},
+	{"CSR"                         ,	34,	1,	1077,	"RO",	1,	0,	0,	0ull},
+	{"CRC"                         ,	35,	1,	1077,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	1077,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	13,	1078,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	1078,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	1078,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	1078,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	64,	1079,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	1080,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	1081,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	1082,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	1083,	"RO",	0,	0,	0ull,	0ull},
+	{"ENGINE0"                     ,	0,	4,	1084,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE1"                     ,	4,	4,	1084,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE2"                     ,	8,	4,	1084,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE3"                     ,	12,	4,	1084,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE4"                     ,	16,	4,	1084,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE5"                     ,	20,	4,	1084,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE6"                     ,	24,	4,	1084,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE7"                     ,	28,	4,	1084,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE8"                     ,	32,	4,	1084,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE9"                     ,	36,	4,	1084,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE10"                    ,	40,	4,	1084,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE11"                    ,	44,	4,	1084,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE12"                    ,	48,	4,	1084,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE13"                    ,	52,	4,	1084,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE14"                    ,	56,	4,	1084,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE15"                    ,	60,	4,	1084,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE16"                    ,	0,	4,	1085,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE17"                    ,	4,	4,	1085,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE18"                    ,	8,	4,	1085,	"R/W",	0,	0,	8ull,	8ull},
+	{"ENGINE19"                    ,	12,	4,	1085,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_16_63"              ,	16,	48,	1085,	"RAZ",	1,	1,	0,	0},
+	{"ENGINE0"                     ,	0,	4,	1086,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE1"                     ,	4,	4,	1086,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE2"                     ,	8,	4,	1086,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE3"                     ,	12,	4,	1086,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE4"                     ,	16,	4,	1086,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE5"                     ,	20,	4,	1086,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE6"                     ,	24,	4,	1086,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE7"                     ,	28,	4,	1086,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE8"                     ,	32,	4,	1086,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE9"                     ,	36,	4,	1086,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE10"                    ,	40,	4,	1086,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE11"                    ,	44,	4,	1086,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE12"                    ,	48,	4,	1086,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE13"                    ,	52,	4,	1086,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE14"                    ,	56,	4,	1086,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENGINE15"                    ,	60,	4,	1086,	"R/W",	0,	0,	1ull,	1ull},
+	{"MASK"                        ,	0,	20,	1087,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1087,	"RAZ",	1,	1,	0,	0},
+	{"PARITY"                      ,	0,	1,	1088,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	1088,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	1088,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LOOPBACK"                    ,	3,	1,	1088,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1088,	"RAZ",	1,	1,	0,	0},
+	{"ENA_PKO"                     ,	0,	1,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	1089,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA_THROTTLE"                ,	4,	1,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIS_PERF0"                   ,	5,	1,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIS_PERF1"                   ,	6,	1,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIS_PERF2"                   ,	7,	1,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIS_PERF3"                   ,	8,	1,	1089,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	1089,	"RAZ",	1,	1,	0,	0},
+	{"PARITY"                      ,	0,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBACK"                    ,	3,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1090,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1091,	"RAZ",	1,	1,	0,	0},
+	{"BPID0"                       ,	4,	6,	1091,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	1091,	"RAZ",	1,	1,	0,	0},
+	{"BPID1"                       ,	11,	6,	1091,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_17"              ,	17,	1,	1091,	"RAZ",	1,	1,	0,	0},
+	{"BPID2"                       ,	18,	6,	1091,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_24"              ,	24,	1,	1091,	"RAZ",	1,	1,	0,	0},
+	{"BPID3"                       ,	25,	6,	1091,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1091,	"RAZ",	1,	1,	0,	0},
+	{"BPID4"                       ,	32,	6,	1091,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_38"              ,	38,	1,	1091,	"RAZ",	1,	1,	0,	0},
+	{"BPID5"                       ,	39,	6,	1091,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_45"              ,	45,	1,	1091,	"RAZ",	1,	1,	0,	0},
+	{"BPID6"                       ,	46,	6,	1091,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_52_52"              ,	52,	1,	1091,	"RAZ",	1,	1,	0,	0},
+	{"BPID7"                       ,	53,	6,	1091,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_59_63"              ,	59,	5,	1091,	"RAZ",	1,	1,	0,	0},
+	{"NUM_PORTS"                   ,	0,	4,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKIND0"                      ,	4,	6,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	1092,	"RAZ",	1,	1,	0,	0},
+	{"PKIND1"                      ,	11,	6,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_17"              ,	17,	1,	1092,	"RAZ",	1,	1,	0,	0},
+	{"PKIND2"                      ,	18,	6,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_24"              ,	24,	1,	1092,	"RAZ",	1,	1,	0,	0},
+	{"PKIND3"                      ,	25,	6,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1092,	"RAZ",	1,	1,	0,	0},
+	{"PKIND4"                      ,	32,	6,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_38"              ,	38,	1,	1092,	"RAZ",	1,	1,	0,	0},
+	{"PKIND5"                      ,	39,	6,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_45"              ,	45,	1,	1092,	"RAZ",	1,	1,	0,	0},
+	{"PKIND6"                      ,	46,	6,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_52_52"              ,	52,	1,	1092,	"RAZ",	1,	1,	0,	0},
+	{"PKIND7"                      ,	53,	6,	1092,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_59_63"              ,	59,	5,	1092,	"RAZ",	1,	1,	0,	0},
+	{"SIZE0"                       ,	0,	8,	1093,	"RO",	0,	0,	0ull,	0ull},
+	{"SIZE1"                       ,	8,	8,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE2"                       ,	16,	8,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE3"                       ,	24,	8,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE4"                       ,	32,	8,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE5"                       ,	40,	8,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE6"                       ,	48,	8,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE7"                       ,	56,	8,	1093,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIN_SIZE"                    ,	0,	16,	1094,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1094,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	1095,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1095,	"RAZ",	1,	1,	0,	0},
+	{"PREEMPTER"                   ,	0,	1,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"PREEMPTEE"                   ,	1,	1,	1096,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1096,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	1097,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	1097,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1097,	"RAZ",	1,	1,	0,	0},
+	{"INT_MASK"                    ,	0,	32,	1098,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1098,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WQE_WORD"                    ,	0,	4,	1099,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_4_63"               ,	4,	60,	1099,	"RAZ",	1,	1,	0,	0},
+	{"IWORD"                       ,	0,	64,	1100,	"RO",	1,	1,	0,	0},
+	{"P_DAT"                       ,	0,	64,	1101,	"RO",	1,	1,	0,	0},
+	{"Q_DAT"                       ,	0,	64,	1102,	"RO",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	2,	1103,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	2,	2,	1103,	"RO",	1,	0,	0,	0ull},
+	{"NCB_OUB"                     ,	4,	1,	1103,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	5,	1,	1103,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1103,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	1104,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	33,	13,	1104,	"R/W",	0,	1,	0ull,	0},
+	{"POOL"                        ,	46,	3,	1104,	"R/W",	0,	1,	0ull,	0},
+	{"DWB"                         ,	49,	9,	1104,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	1104,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	1105,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STORE_LE"                    ,	1,	1,	1105,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_READ"                    ,	2,	4,	1105,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_6_63"               ,	6,	58,	1105,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	0,	5,	1106,	"RO",	1,	1,	0,	0},
+	{"COMMIT"                      ,	5,	1,	1106,	"RO",	1,	1,	0,	0},
+	{"OWORDPV"                     ,	6,	1,	1106,	"RO",	1,	1,	0,	0},
+	{"OWORDQV"                     ,	7,	1,	1106,	"RO",	1,	1,	0,	0},
+	{"IWIDX"                       ,	8,	6,	1106,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	1106,	"RO",	1,	1,	0,	0},
+	{"IRIDX"                       ,	16,	6,	1106,	"RO",	1,	1,	0,	0},
+	{"RESERVED_22_31"              ,	22,	10,	1106,	"RO",	1,	1,	0,	0},
+	{"LOOP"                        ,	32,	25,	1106,	"RO",	1,	1,	0,	0},
+	{"RESERVED_57_63"              ,	57,	7,	1106,	"RO",	1,	1,	0,	0},
+	{"CWORD"                       ,	0,	64,	1107,	"RO",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	1108,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	1108,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	1108,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	1109,	"RO",	1,	1,	0,	0},
+	{"SOD"                         ,	8,	1,	1109,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	9,	1,	1109,	"RO",	1,	1,	0,	0},
+	{"WC"                          ,	10,	1,	1109,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	11,	1,	1109,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	12,	1,	1109,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	1109,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	15,	1110,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	1110,	"RAZ",	1,	1,	0,	0},
+	{"OWORDP"                      ,	0,	64,	1111,	"RO",	1,	1,	0,	0},
+	{"OWORDQ"                      ,	0,	64,	1112,	"RO",	1,	1,	0,	0},
+	{"RWORD"                       ,	0,	64,	1113,	"RO",	1,	1,	0,	0},
+	{"N0CREDS"                     ,	0,	4,	1114,	"RO",	0,	0,	8ull,	0ull},
+	{"N1CREDS"                     ,	4,	4,	1114,	"RO",	0,	0,	8ull,	0ull},
+	{"POWCREDS"                    ,	8,	2,	1114,	"RO",	0,	0,	2ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	1114,	"RAZ",	1,	1,	0,	0},
+	{"FPACREDS"                    ,	12,	2,	1114,	"RO",	0,	0,	1ull,	0ull},
+	{"WCCREDS"                     ,	14,	2,	1114,	"RO",	0,	0,	0ull,	0ull},
+	{"NIWIDX0"                     ,	16,	4,	1114,	"RO",	1,	1,	0,	0},
+	{"NIRIDX0"                     ,	20,	4,	1114,	"RO",	1,	1,	0,	0},
+	{"NIWIDX1"                     ,	24,	4,	1114,	"RO",	1,	1,	0,	0},
+	{"NIRIDX1"                     ,	28,	4,	1114,	"RO",	1,	1,	0,	0},
+	{"NIRVAL6"                     ,	32,	5,	1114,	"RO",	1,	1,	0,	0},
+	{"NIRARB6"                     ,	37,	1,	1114,	"RO",	1,	1,	0,	0},
+	{"NIRQUE6"                     ,	38,	2,	1114,	"RO",	1,	1,	0,	0},
+	{"NIROPC6"                     ,	40,	3,	1114,	"RO",	1,	1,	0,	0},
+	{"NIRVAL7"                     ,	43,	5,	1114,	"RO",	1,	1,	0,	0},
+	{"NIRQUE7"                     ,	48,	2,	1114,	"RO",	1,	1,	0,	0},
+	{"NIROPC7"                     ,	50,	3,	1114,	"RO",	1,	1,	0,	0},
+	{"RESERVED_53_63"              ,	53,	11,	1114,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	1115,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	1115,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	56,	8,	1115,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	15,	1116,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	1116,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	1117,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	1117,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	1117,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	1118,	"RO",	1,	1,	0,	0},
+	{"MUL"                         ,	8,	8,	1118,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	16,	1,	1118,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	17,	1,	1118,	"RO",	1,	1,	0,	0},
+	{"INI"                         ,	18,	1,	1118,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	19,	1,	1118,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_63"              ,	20,	44,	1118,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1119,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1119,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1120,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1120,	"RAZ",	1,	1,	0,	0},
+	{"COEFFS"                      ,	0,	8,	1121,	"R/W",	0,	0,	29ull,	29ull},
+	{"RESERVED_8_63"               ,	8,	56,	1121,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	0,	16,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	16,	16,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1122,	"RAZ",	1,	1,	0,	0},
+	{"MEM"                         ,	0,	1,	1123,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	1123,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1123,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXP_ENT"                     ,	4,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENT_SEL"                     ,	5,	4,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"EER_VAL"                     ,	9,	1,	1124,	"RO",	0,	0,	0ull,	0ull},
+	{"EER_LCK"                     ,	10,	1,	1124,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	1124,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	1125,	"RO",	1,	1,	0,	0},
+	{"KEY"                         ,	0,	64,	1126,	"WO",	0,	0,	0ull,	0ull},
+	{"DAT"                         ,	0,	64,	1127,	"RO",	1,	1,	0,	0},
+	{"NCB_CMD"                     ,	0,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"MSI"                         ,	1,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI0_0"                      ,	2,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI0_1"                      ,	3,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI1_0"                      ,	4,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI1_1"                      ,	5,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_8"                ,	6,	3,	1128,	"RAZ",	1,	1,	0,	0},
+	{"P2N1_P1"                     ,	9,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_P0"                     ,	10,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_N"                      ,	11,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C1"                     ,	12,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C0"                     ,	13,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P1"                     ,	14,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P0"                     ,	15,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_N"                      ,	16,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C1"                     ,	17,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C0"                     ,	18,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_24"              ,	19,	6,	1128,	"RAZ",	1,	1,	0,	0},
+	{"CPL_P1"                      ,	25,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"CPL_P0"                      ,	26,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_O"                      ,	27,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_C"                      ,	28,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_O"                      ,	29,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_C"                      ,	30,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"NCB_REQ"                     ,	31,	1,	1128,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1128,	"RAZ",	1,	1,	0,	0},
+	{"WAIT_COM"                    ,	0,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_4"                ,	1,	4,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTLP_RO"                     ,	5,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTLP_RO"                     ,	7,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTA_MAP"                    ,	8,	2,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTB_MAP"                    ,	10,	2,	1129,	"R/W",	0,	0,	1ull,	1ull},
+	{"INTC_MAP"                    ,	12,	2,	1129,	"R/W",	0,	0,	2ull,	2ull},
+	{"INTD_MAP"                    ,	14,	2,	1129,	"R/W",	0,	0,	3ull,	3ull},
+	{"WAITL_COM"                   ,	16,	1,	1129,	"R/W",	0,	1,	0ull,	0},
+	{"DIS_PORT"                    ,	17,	1,	1129,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTA"                        ,	18,	1,	1129,	"RO",	0,	0,	1ull,	1ull},
+	{"INTB"                        ,	19,	1,	1129,	"RO",	0,	0,	1ull,	1ull},
+	{"INTC"                        ,	20,	1,	1129,	"RO",	0,	0,	1ull,	1ull},
+	{"INTD"                        ,	21,	1,	1129,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	1129,	"RAZ",	1,	1,	0,	0},
+	{"CHIP_REV"                    ,	0,	8,	1130,	"RO",	1,	1,	0,	0},
+	{"P0_NTAGS"                    ,	8,	6,	1130,	"R/W",	0,	0,	32ull,	32ull},
+	{"P1_NTAGS"                    ,	14,	6,	1130,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_63"              ,	20,	44,	1130,	"RAZ",	1,	1,	0,	0},
+	{"P0_FCNT"                     ,	0,	6,	1131,	"RO",	0,	1,	0ull,	0},
+	{"P0_UCNT"                     ,	6,	16,	1131,	"RO",	0,	1,	0ull,	0},
+	{"P1_FCNT"                     ,	22,	6,	1131,	"RO",	0,	1,	0ull,	0},
+	{"P1_UCNT"                     ,	28,	16,	1131,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	1131,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	1132,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	1132,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	1132,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	32,	1133,	"R/W",	0,	1,	0ull,	0},
+	{"ADBG_SEL"                    ,	32,	1,	1133,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	1133,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1134,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1134,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1135,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	32,	1135,	"R/W",	0,	1,	0ull,	0},
+	{"TIM"                         ,	0,	32,	1136,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1136,	"RAZ",	1,	1,	0,	0},
+	{"RML_TO"                      ,	0,	1,	1137,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	1137,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	1137,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	1137,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	4,	1,	1137,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	5,	1,	1137,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	1137,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UP_WI"                    ,	9,	1,	1137,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_B0"                    ,	10,	1,	1137,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_WI"                    ,	11,	1,	1137,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_B0"                    ,	12,	1,	1137,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_WI"                    ,	13,	1,	1137,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_B0"                    ,	14,	1,	1137,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_WI"                    ,	15,	1,	1137,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT0"                    ,	16,	1,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO_INT1"                    ,	17,	1,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAFI"                       ,	32,	2,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	48,	1,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_59"              ,	58,	2,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIPE_ERR"                    ,	61,	1,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML_TO"                      ,	0,	1,	1138,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	1138,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	1138,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	1138,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	4,	1,	1138,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	5,	1,	1138,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	1138,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UP_WI"                    ,	9,	1,	1138,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_B0"                    ,	10,	1,	1138,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_WI"                    ,	11,	1,	1138,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_B0"                    ,	12,	1,	1138,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_WI"                    ,	13,	1,	1138,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_B0"                    ,	14,	1,	1138,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_WI"                    ,	15,	1,	1138,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT0"                    ,	16,	1,	1138,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT1"                    ,	17,	1,	1138,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC0_INT"                    ,	18,	1,	1138,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC1_INT"                    ,	19,	1,	1138,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_31"              ,	20,	12,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAFI"                       ,	32,	2,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	48,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_59"              ,	58,	2,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIPE_ERR"                    ,	61,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML_TO"                      ,	0,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAR0_TO"                     ,	2,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB2BIG"                     ,	3,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT"                        ,	4,	1,	1139,	"RO",	0,	0,	0ull,	0ull},
+	{"PTIME"                       ,	5,	1,	1139,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UP_WI"                    ,	9,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UN_B0"                    ,	10,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UN_WI"                    ,	11,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UP_B0"                    ,	12,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UP_WI"                    ,	13,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UN_B0"                    ,	14,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UN_WI"                    ,	15,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO_INT0"                    ,	16,	1,	1139,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO_INT1"                    ,	17,	1,	1139,	"RO",	0,	0,	0ull,	0ull},
+	{"MAC0_INT"                    ,	18,	1,	1139,	"RO",	0,	0,	0ull,	0ull},
+	{"MAC1_INT"                    ,	19,	1,	1139,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	1139,	"RAZ",	1,	1,	0,	0},
+	{"DMAFI"                       ,	32,	2,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	1139,	"RO",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	1139,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	1139,	"RAZ",	1,	1,	0,	0},
+	{"PIDBOF"                      ,	48,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	1139,	"RAZ",	1,	1,	0,	0},
+	{"PGL_ERR"                     ,	52,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_59"              ,	58,	2,	1139,	"RAZ",	1,	1,	0,	0},
+	{"ILL_PAD"                     ,	60,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIPE_ERR"                    ,	61,	1,	1139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	1139,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	1140,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	1141,	"RO",	0,	1,	0ull,	0},
+	{"P0_PCNT"                     ,	0,	8,	1142,	"R/W",	0,	0,	128ull,	128ull},
+	{"P0_NCNT"                     ,	8,	8,	1142,	"R/W",	0,	0,	16ull,	16ull},
+	{"P0_CCNT"                     ,	16,	8,	1142,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_PCNT"                     ,	24,	8,	1142,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_NCNT"                     ,	32,	8,	1142,	"R/W",	0,	0,	16ull,	16ull},
+	{"P1_CCNT"                     ,	40,	8,	1142,	"R/W",	0,	0,	128ull,	128ull},
+	{"P0_P_D"                      ,	48,	1,	1142,	"R/W",	0,	0,	1ull,	1ull},
+	{"P0_N_D"                      ,	49,	1,	1142,	"R/W",	0,	0,	1ull,	1ull},
+	{"P0_C_D"                      ,	50,	1,	1142,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_P_D"                      ,	51,	1,	1142,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_N_D"                      ,	52,	1,	1142,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_C_D"                      ,	53,	1,	1142,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_54_63"              ,	54,	10,	1142,	"RAZ",	1,	1,	0,	0},
+	{"NUM"                         ,	0,	8,	1143,	"RO",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	1143,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	10,	1144,	"R/W",	0,	0,	0ull,	50ull},
+	{"MAX_WORD"                    ,	10,	4,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	1144,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"BA"                          ,	2,	28,	1145,	"R/W",	0,	1,	0ull,	0},
+	{"RTYPE"                       ,	30,	2,	1145,	"R/W",	0,	1,	0ull,	0},
+	{"WTYPE"                       ,	32,	2,	1145,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	34,	2,	1145,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	36,	2,	1145,	"R/W",	0,	1,	0ull,	0},
+	{"NMERGE"                      ,	38,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORT"                        ,	39,	3,	1145,	"R/W",	0,	1,	0ull,	0},
+	{"ZERO"                        ,	42,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	1145,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	64,	1146,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	1147,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	1148,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	1149,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"INTR"                        ,	0,	64,	1150,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	1151,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	1152,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	1153,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	1154,	"R/W",	0,	1,	0ull,	0},
+	{"RD_INT"                      ,	8,	8,	1154,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	1154,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	64,	1155,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	1156,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	1157,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	1158,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	1159,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	1160,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	1161,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	1162,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	1163,	"R/W",	0,	1,	0ull,	0},
+	{"CIU_INT"                     ,	8,	8,	1163,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	1163,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	8,	1164,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	1164,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1165,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	8,	8,	1165,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	1165,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	1166,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	16,	8,	1166,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	1166,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	1167,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	24,	8,	1167,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1167,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1168,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	32,	22,	1168,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	1168,	"RO",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	1169,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	61,	1169,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	1170,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	1170,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	1171,	"R/W",	0,	1,	0ull,	0},
+	{"FCNT"                        ,	32,	5,	1171,	"RO",	0,	1,	0ull,	0},
+	{"WRP"                         ,	37,	9,	1171,	"RO",	0,	1,	0ull,	0},
+	{"RRP"                         ,	46,	9,	1171,	"RO",	0,	1,	0ull,	0},
+	{"MAX"                         ,	55,	9,	1171,	"RO",	0,	1,	16ull,	0},
+	{"NTAG"                        ,	0,	1,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"NTT"                         ,	1,	1,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"NGRP"                        ,	2,	1,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"NQOS"                        ,	3,	1,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"NGRPEXT"                     ,	4,	2,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_13"              ,	13,	1,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_20"              ,	16,	5,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"RNTAG"                       ,	22,	1,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"RNTT"                        ,	23,	1,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"RNGRP"                       ,	24,	1,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"RNQOS"                       ,	25,	1,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"RNGRPEXT"                    ,	26,	2,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_35_35"              ,	35,	1,	1172,	"RAZ",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_42"              ,	38,	5,	1172,	"RAZ",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	1172,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	16,	1173,	"R/W",	0,	1,	0ull,	0},
+	{"ISIZE"                       ,	16,	7,	1173,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	1173,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1174,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	4,	60,	1174,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	1175,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	1175,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	1176,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1176,	"RO",	0,	1,	0ull,	0},
+	{"PORT"                        ,	0,	32,	1177,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1177,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	1178,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1178,	"RAZ",	1,	1,	0,	0},
+	{"PKT_BP"                      ,	0,	4,	1179,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RING_EN"                     ,	4,	1,	1179,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	1179,	"RAZ",	1,	1,	0,	0},
+	{"ES"                          ,	0,	64,	1180,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	1181,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1181,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	1182,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1182,	"RAZ",	1,	1,	0,	0},
+	{"DPTR"                        ,	0,	32,	1183,	"R/W",	0,	0,	0ull,	4294967295ull},
+	{"RESERVED_32_63"              ,	32,	32,	1183,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1184,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1184,	"RO",	0,	1,	0ull,	0},
+	{"RD_CNT"                      ,	0,	32,	1185,	"RO",	0,	1,	0ull,	0},
+	{"WR_CNT"                      ,	32,	32,	1185,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	0,	64,	1186,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	0,	1,	1187,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	1,	2,	1187,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	3,	1,	1187,	"R/W",	0,	1,	0ull,	0},
+	{"USE_CSR"                     ,	4,	1,	1187,	"R/W",	0,	0,	0ull,	1ull},
+	{"D_ROR"                       ,	5,	1,	1187,	"R/W",	0,	1,	0ull,	0},
+	{"D_ESR"                       ,	6,	2,	1187,	"R/W",	0,	1,	0ull,	0},
+	{"D_NSR"                       ,	8,	1,	1187,	"R/W",	0,	1,	0ull,	0},
+	{"PBP_DHI"                     ,	9,	13,	1187,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_RR"                      ,	22,	1,	1187,	"R/W",	0,	0,	0ull,	1ull},
+	{"PIN_RST"                     ,	23,	1,	1187,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_39"              ,	24,	16,	1187,	"RAZ",	1,	1,	0,	0},
+	{"PRC_IDLE"                    ,	40,	1,	1187,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_41_47"              ,	41,	7,	1187,	"RAZ",	1,	1,	0,	0},
+	{"GII_RDS"                     ,	48,	7,	1187,	"RO",	0,	1,	0ull,	0},
+	{"GII_ERST"                    ,	55,	1,	1187,	"RO",	0,	1,	0ull,	0},
+	{"PRD_RDS"                     ,	56,	7,	1187,	"RO",	0,	1,	0ull,	0},
+	{"PRD_ERST"                    ,	63,	1,	1187,	"RO",	0,	1,	0ull,	0},
+	{"ENB"                         ,	0,	32,	1188,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1188,	"RAZ",	1,	1,	0,	0},
+	{"RDSIZE"                      ,	0,	64,	1189,	"R/W",	0,	1,	0ull,	0},
+	{"IS_64B"                      ,	0,	32,	1190,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1190,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1191,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	22,	1191,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_54_63"              ,	54,	10,	1191,	"RAZ",	1,	1,	0,	0},
+	{"IPTR"                        ,	0,	32,	1192,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1192,	"RAZ",	1,	1,	0,	0},
+	{"BMODE"                       ,	0,	32,	1193,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1193,	"RAZ",	1,	1,	0,	0},
+	{"BP_EN"                       ,	0,	32,	1194,	"R/W",	0,	0,	4294967295ull,	4294967295ull},
+	{"RESERVED_32_63"              ,	32,	32,	1194,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	32,	1195,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1195,	"RAZ",	1,	1,	0,	0},
+	{"WMARK"                       ,	0,	32,	1196,	"R/W",	0,	0,	0ull,	14ull},
+	{"RESERVED_32_63"              ,	32,	32,	1196,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	0,	64,	1197,	"R/W",	0,	1,	0ull,	0},
+	{"OUT_RST"                     ,	0,	32,	1198,	"RO",	0,	1,	0ull,	0},
+	{"IN_RST"                      ,	32,	32,	1198,	"RO",	0,	1,	0ull,	0},
+	{"ES"                          ,	0,	64,	1199,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	1200,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1200,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	1201,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1201,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	1202,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1202,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	1203,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1203,	"RAZ",	1,	1,	0,	0},
+	{"PKIND"                       ,	0,	6,	1204,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	1204,	"RAZ",	1,	1,	0,	0},
+	{"BPKIND"                      ,	8,	6,	1204,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	1204,	"RAZ",	1,	1,	0,	0},
+	{"PKINDR"                      ,	16,	6,	1204,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_23"              ,	22,	2,	1204,	"RAZ",	1,	1,	0,	0},
+	{"RPK_ENB"                     ,	24,	1,	1204,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	1204,	"RAZ",	1,	1,	0,	0},
+	{"MRRS"                        ,	0,	3,	1205,	"R/W",	0,	0,	2ull,	2ull},
+	{"BAR0_D"                      ,	3,	1,	1205,	"R/W",	0,	0,	0ull,	0ull},
+	{"WIND_D"                      ,	4,	1,	1205,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	1205,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	1206,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	1207,	"R/W",	0,	1,	0ull,	0},
+	{"CSR"                         ,	0,	39,	1208,	"RO",	0,	1,	1ull,	0},
+	{"ARB"                         ,	39,	1,	1208,	"RO",	0,	1,	0ull,	0},
+	{"CPL0"                        ,	40,	12,	1208,	"RO",	0,	1,	1ull,	0},
+	{"CPL1"                        ,	52,	12,	1208,	"RO",	0,	1,	1ull,	0},
+	{"NND"                         ,	0,	8,	1209,	"RO",	0,	1,	1ull,	0},
+	{"NNP0"                        ,	8,	8,	1209,	"RO",	0,	1,	1ull,	0},
+	{"CSM0"                        ,	16,	15,	1209,	"RO",	0,	1,	1ull,	0},
+	{"CSM1"                        ,	31,	15,	1209,	"RO",	0,	1,	1ull,	0},
+	{"RAC"                         ,	46,	1,	1209,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	1209,	"RAZ",	1,	1,	0,	0},
+	{"NNP1"                        ,	48,	8,	1209,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	1209,	"RAZ",	1,	1,	0,	0},
+	{"NSM0"                        ,	0,	13,	1210,	"RO",	0,	1,	1ull,	0},
+	{"NSM1"                        ,	13,	13,	1210,	"RO",	0,	1,	1ull,	0},
+	{"PSM0"                        ,	26,	15,	1210,	"RO",	0,	1,	1ull,	0},
+	{"PSM1"                        ,	41,	15,	1210,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	1210,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	7,	1211,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_15"               ,	7,	9,	1211,	"RAZ",	1,	1,	0,	0},
+	{"NUMP"                        ,	16,	8,	1211,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	1211,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	0,	48,	1212,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	1212,	"R/W",	0,	0,	0ull,	0ull},
+	{"LD_CMD"                      ,	49,	2,	1212,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_51_63"              ,	51,	13,	1212,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	1213,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	1214,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	3,	45,	1214,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	1214,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	1214,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	1215,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	1216,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1216,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	1217,	"R/W",	0,	0,	0ull,	2097152ull},
+	{"RESERVED_32_63"              ,	32,	32,	1217,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	1218,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	1218,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	1218,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	1218,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	1218,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	1218,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	1218,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	1218,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	24,	1,	1218,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1218,	"RAZ",	1,	1,	0,	0},
+	{"REG_ADR"                     ,	0,	5,	1219,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1219,	"RAZ",	1,	1,	0,	0},
+	{"PHY_ADR"                     ,	8,	5,	1219,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	1219,	"RAZ",	1,	1,	0,	0},
+	{"PHY_OP"                      ,	16,	2,	1219,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	1219,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	1220,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	1220,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	1221,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	1221,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	1221,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	1221,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	1222,	"R/W",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	1222,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	1222,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	1222,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	1223,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_6_7"                ,	6,	2,	1223,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	8,	6,	1223,	"R/W",	0,	0,	19ull,	19ull},
+	{"RESERVED_14_63"              ,	14,	50,	1223,	"RAZ",	1,	1,	0,	0},
+	{"ACT_CYC"                     ,	0,	64,	1224,	"RO",	0,	1,	0ull,	0},
+	{"OTH"                         ,	0,	2,	1225,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	1225,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	8,	2,	1225,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	1225,	"RAZ",	1,	1,	0,	0},
+	{"FIDX"                        ,	16,	1,	1225,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	1225,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	20,	1,	1225,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	1225,	"RAZ",	1,	1,	0,	0},
+	{"NCBO"                        ,	24,	4,	1225,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_30"              ,	28,	3,	1225,	"RAZ",	1,	1,	0,	0},
+	{"SOC"                         ,	31,	1,	1225,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_33"              ,	32,	2,	1225,	"RAZ",	1,	1,	0,	0},
+	{"RWI_DAT"                     ,	34,	1,	1225,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_41"              ,	35,	7,	1225,	"RAZ",	1,	1,	0,	0},
+	{"RWO"                         ,	42,	2,	1225,	"RO",	0,	0,	0ull,	0ull},
+	{"RWO_DAT"                     ,	44,	1,	1225,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_51"              ,	45,	7,	1225,	"RAZ",	1,	1,	0,	0},
+	{"FPTR"                        ,	52,	2,	1225,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_59"              ,	54,	6,	1225,	"RAZ",	1,	1,	0,	0},
+	{"ODU_PREF"                    ,	60,	2,	1225,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	1225,	"RAZ",	1,	1,	0,	0},
+	{"RWEN"                        ,	0,	1,	1226,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	1,	1,	1226,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDT"                         ,	2,	1,	1226,	"R/W",	0,	0,	1ull,	1ull},
+	{"STT"                         ,	3,	1,	1226,	"R/W",	0,	0,	1ull,	1ull},
+	{"RWQ_BYP_DIS"                 ,	4,	1,	1226,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWIO_BYP_DIS"                ,	5,	1,	1226,	"R/W",	0,	0,	0ull,	0ull},
+	{"WFE_THR"                     ,	6,	1,	1226,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWO_FLUSH"                   ,	7,	1,	1226,	"WR0",	0,	0,	0ull,	0ull},
+	{"SSO_CCLK_DIS"                ,	8,	1,	1226,	"R/W",	0,	0,	0ull,	0ull},
+	{"SOC_CCAM_DIS"                ,	9,	1,	1226,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWQ_ALLOC_DIS"               ,	10,	1,	1226,	"R/W",	0,	0,	0ull,	0ull},
+	{"QCK_SW_DIS"                  ,	11,	1,	1226,	"R/W",	0,	0,	0ull,	0ull},
+	{"QCK_GW_RSP_DIS"              ,	12,	1,	1226,	"R/W",	0,	0,	0ull,	0ull},
+	{"QCK_GW_RSP_ADJ"              ,	13,	3,	1226,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1226,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	64,	1227,	"R/W",	0,	1,	0ull,	0},
+	{"FIDX_SBE"                    ,	0,	1,	1228,	"R/W1C",	0,	1,	0ull,	0},
+	{"FIDX_DBE"                    ,	1,	1,	1228,	"R/W1C",	0,	1,	0ull,	0},
+	{"IDX_SBE"                     ,	2,	1,	1228,	"R/W1C",	0,	1,	0ull,	0},
+	{"IDX_DBE"                     ,	3,	1,	1228,	"R/W1C",	0,	1,	0ull,	0},
+	{"OTH_SBE1"                    ,	4,	1,	1228,	"R/W1C",	0,	1,	0ull,	0},
+	{"OTH_DBE1"                    ,	5,	1,	1228,	"R/W1C",	0,	1,	0ull,	0},
+	{"OTH_SBE0"                    ,	6,	1,	1228,	"R/W1C",	0,	1,	0ull,	0},
+	{"OTH_DBE0"                    ,	7,	1,	1228,	"R/W1C",	0,	1,	0ull,	0},
+	{"PND_SBE1"                    ,	8,	1,	1228,	"R/W1C",	0,	1,	0ull,	0},
+	{"PND_DBE1"                    ,	9,	1,	1228,	"R/W1C",	0,	1,	0ull,	0},
+	{"PND_SBE0"                    ,	10,	1,	1228,	"R/W1C",	0,	1,	0ull,	0},
+	{"PND_DBE0"                    ,	11,	1,	1228,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_12_31"              ,	12,	20,	1228,	"RAZ",	1,	1,	0,	0},
+	{"IOP"                         ,	32,	11,	1228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_44"              ,	43,	2,	1228,	"RAZ",	1,	1,	0,	0},
+	{"FPE"                         ,	45,	1,	1228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AWE"                         ,	46,	1,	1228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BFP"                         ,	47,	1,	1228,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1228,	"RAZ",	1,	1,	0,	0},
+	{"FIDX_SBE_IE"                 ,	0,	1,	1229,	"R/W",	0,	1,	0ull,	0},
+	{"FIDX_DBE_IE"                 ,	1,	1,	1229,	"R/W",	0,	1,	0ull,	0},
+	{"IDX_SBE_IE"                  ,	2,	1,	1229,	"R/W",	0,	1,	0ull,	0},
+	{"IDX_DBE_IE"                  ,	3,	1,	1229,	"R/W",	0,	1,	0ull,	0},
+	{"OTH_SBE1_IE"                 ,	4,	1,	1229,	"R/W",	0,	1,	0ull,	0},
+	{"OTH_DBE1_IE"                 ,	5,	1,	1229,	"R/W",	0,	1,	0ull,	0},
+	{"OTH_SBE0_IE"                 ,	6,	1,	1229,	"R/W",	0,	1,	0ull,	0},
+	{"OTH_DBE0_IE"                 ,	7,	1,	1229,	"R/W",	0,	1,	0ull,	0},
+	{"PND_SBE1_IE"                 ,	8,	1,	1229,	"R/W",	0,	1,	0ull,	0},
+	{"PND_DBE1_IE"                 ,	9,	1,	1229,	"R/W",	0,	1,	0ull,	0},
+	{"PND_SBE0_IE"                 ,	10,	1,	1229,	"R/W",	0,	1,	0ull,	0},
+	{"PND_DBE0_IE"                 ,	11,	1,	1229,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_31"              ,	12,	20,	1229,	"RAZ",	1,	1,	0,	0},
+	{"IOP_IE"                      ,	32,	11,	1229,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_43_44"              ,	43,	2,	1229,	"RAZ",	1,	1,	0,	0},
+	{"FPE_IE"                      ,	45,	1,	1229,	"R/W",	0,	1,	0ull,	0},
+	{"AWE_IE"                      ,	46,	1,	1229,	"R/W",	0,	1,	0ull,	0},
+	{"BFP_IE"                      ,	47,	1,	1229,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	1229,	"RAZ",	1,	1,	0,	0},
+	{"ECC_ENA"                     ,	0,	1,	1230,	"R/W",	0,	0,	1ull,	1ull},
+	{"FLIP_SYND"                   ,	1,	2,	1230,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	1230,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1231,	"RAZ",	1,	1,	0,	0},
+	{"SYNDROM"                     ,	4,	5,	1231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_15"               ,	9,	7,	1231,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	16,	11,	1231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	1231,	"RAZ",	1,	1,	0,	0},
+	{"FPAGE_CNT"                   ,	0,	32,	1232,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1232,	"RAZ",	1,	1,	0,	0},
+	{"GWE_DIS"                     ,	0,	1,	1233,	"R/W",	0,	0,	0ull,	0ull},
+	{"GWE_RAH"                     ,	1,	1,	1233,	"R/W",	0,	0,	0ull,	0ull},
+	{"GWE_FPOR"                    ,	2,	1,	1233,	"R/W",	0,	0,	0ull,	0ull},
+	{"GWE_POE"                     ,	3,	1,	1233,	"R/W",	0,	0,	0ull,	0ull},
+	{"GWE_HVY_DIS"                 ,	4,	1,	1233,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	1233,	"RAZ",	1,	1,	0,	0},
+	{"ODU_BMP_DIS"                 ,	8,	1,	1233,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODU_PRF_DIS"                 ,	9,	1,	1233,	"R/W",	0,	0,	0ull,	0ull},
+	{"GWE_RFPGW_DIS"               ,	10,	1,	1233,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODU_FFPGW_DIS"               ,	11,	1,	1233,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	1233,	"RAZ",	1,	1,	0,	0},
+	{"ECC_ENA"                     ,	0,	1,	1234,	"R/W",	0,	0,	1ull,	1ull},
+	{"FLIP_SYND"                   ,	1,	2,	1234,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	1234,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1235,	"RAZ",	1,	1,	0,	0},
+	{"SYNDROM"                     ,	4,	5,	1235,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_15"               ,	9,	7,	1235,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	16,	11,	1235,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	1235,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	1236,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1236,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	1237,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1237,	"RAZ",	1,	1,	0,	0},
+	{"IQ_INT"                      ,	0,	8,	1238,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	1238,	"RAZ",	1,	1,	0,	0},
+	{"INT_EN"                      ,	0,	8,	1239,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	1239,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	32,	1240,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1240,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	12,	1241,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	1241,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	1242,	"R/W",	0,	0,	0ull,	4ull},
+	{"RESERVED_10_63"              ,	10,	54,	1242,	"RAZ",	1,	1,	0,	0},
+	{"ECC_ENA0"                    ,	0,	1,	1243,	"R/W",	0,	0,	1ull,	1ull},
+	{"FLIP_SYND0"                  ,	1,	2,	1243,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ENA1"                    ,	3,	1,	1243,	"R/W",	0,	0,	1ull,	1ull},
+	{"FLIP_SYND1"                  ,	4,	2,	1243,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1243,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1244,	"RAZ",	1,	1,	0,	0},
+	{"SYNDROM0"                    ,	4,	7,	1244,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	1244,	"RAZ",	1,	1,	0,	0},
+	{"ADDR0"                       ,	16,	11,	1244,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_35"              ,	27,	9,	1244,	"RAZ",	1,	1,	0,	0},
+	{"SYNDROM1"                    ,	36,	7,	1244,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_47"              ,	43,	5,	1244,	"RAZ",	1,	1,	0,	0},
+	{"ADDR1"                       ,	48,	11,	1244,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_59_63"              ,	59,	5,	1244,	"RAZ",	1,	1,	0,	0},
+	{"ECC_ENA0"                    ,	0,	1,	1245,	"R/W",	0,	0,	1ull,	1ull},
+	{"FLIP_SYND0"                  ,	1,	2,	1245,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ENA1"                    ,	3,	1,	1245,	"R/W",	0,	0,	1ull,	1ull},
+	{"FLIP_SYND1"                  ,	4,	2,	1245,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1245,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1246,	"RAZ",	1,	1,	0,	0},
+	{"SYNDROM0"                    ,	4,	7,	1246,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	1246,	"RAZ",	1,	1,	0,	0},
+	{"ADDR0"                       ,	16,	11,	1246,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_35"              ,	27,	9,	1246,	"RAZ",	1,	1,	0,	0},
+	{"SYNDROM1"                    ,	36,	7,	1246,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_47"              ,	43,	5,	1246,	"RAZ",	1,	1,	0,	0},
+	{"ADDR1"                       ,	48,	11,	1246,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_59_63"              ,	59,	5,	1246,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	64,	1247,	"R/W",	0,	0,	18446744073709551615ull,	18446744073709551615ull},
+	{"QOS0_PRI"                    ,	0,	4,	1248,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	1248,	"RAZ",	1,	1,	0,	0},
+	{"QOS1_PRI"                    ,	8,	4,	1248,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_15"              ,	12,	4,	1248,	"RAZ",	1,	1,	0,	0},
+	{"QOS2_PRI"                    ,	16,	4,	1248,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_23"              ,	20,	4,	1248,	"RAZ",	1,	1,	0,	0},
+	{"QOS3_PRI"                    ,	24,	4,	1248,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	1248,	"RAZ",	1,	1,	0,	0},
+	{"QOS4_PRI"                    ,	32,	4,	1248,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	1248,	"RAZ",	1,	1,	0,	0},
+	{"QOS5_PRI"                    ,	40,	4,	1248,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_47"              ,	44,	4,	1248,	"RAZ",	1,	1,	0,	0},
+	{"QOS6_PRI"                    ,	48,	4,	1248,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_52_55"              ,	52,	4,	1248,	"RAZ",	1,	1,	0,	0},
+	{"QOS7_PRI"                    ,	56,	4,	1248,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	1248,	"RAZ",	1,	1,	0,	0},
+	{"PP_STRICT"                   ,	0,	32,	1249,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1249,	"RAZ",	1,	1,	0,	0},
+	{"RNDS_QOS"                    ,	0,	8,	1250,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	1250,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	12,	1251,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_13"              ,	12,	2,	1251,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	14,	12,	1251,	"R/W",	0,	1,	241ull,	0},
+	{"RESERVED_26_27"              ,	26,	2,	1251,	"RAZ",	1,	1,	0,	0},
+	{"BUF_CNT"                     ,	28,	12,	1251,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	1251,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	0,	12,	1252,	"RO",	0,	1,	2000ull,	0},
+	{"RESERVED_12_13"              ,	12,	2,	1252,	"RAZ",	1,	1,	0,	0},
+	{"DES_CNT"                     ,	14,	12,	1252,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	1252,	"RAZ",	1,	1,	0,	0},
+	{"RESET"                       ,	0,	1,	1253,	"WR0",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1253,	"RAZ",	1,	1,	0,	0},
+	{"RCTR"                        ,	0,	5,	1254,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_6"                ,	5,	2,	1254,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	7,	31,	1254,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1254,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_6"                ,	0,	7,	1255,	"RAZ",	1,	1,	0,	0},
+	{"FPTR"                        ,	7,	31,	1255,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_56"              ,	38,	19,	1255,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	57,	6,	1255,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	63,	1,	1255,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_6"                ,	0,	7,	1256,	"RAZ",	1,	1,	0,	0},
+	{"FPTR"                        ,	7,	31,	1256,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_38_58"              ,	38,	21,	1256,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	59,	4,	1256,	"RO",	0,	1,	0ull,	0},
+	{"FULL"                        ,	63,	1,	1256,	"RO",	0,	1,	0ull,	0},
+	{"RCTR"                        ,	0,	5,	1257,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_6"                ,	5,	2,	1257,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	7,	31,	1257,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1257,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	64,	1258,	"R/W",	0,	1,	0ull,	0},
+	{"WA_PC"                       ,	0,	64,	1259,	"R/W",	0,	1,	0ull,	0},
+	{"WA_PC"                       ,	0,	64,	1260,	"R/W",	0,	1,	0ull,	0},
+	{"WQ_INT"                      ,	0,	64,	1261,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_CNT"                      ,	0,	12,	1262,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_13"              ,	12,	2,	1262,	"RAZ",	1,	1,	0,	0},
+	{"DS_CNT"                      ,	14,	12,	1262,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_27"              ,	26,	2,	1262,	"RAZ",	1,	1,	0,	0},
+	{"TC_CNT"                      ,	28,	4,	1262,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1262,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1263,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	1263,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	1263,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	1263,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	1263,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	12,	1264,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_13"              ,	12,	2,	1264,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	14,	12,	1264,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_27"              ,	26,	2,	1264,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	28,	4,	1264,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	32,	1,	1264,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	1264,	"RAZ",	1,	1,	0,	0},
+	{"IQ_DIS"                      ,	0,	64,	1265,	"R/W1",	0,	1,	0ull,	0},
+	{"WS_PC"                       ,	0,	64,	1266,	"R/W",	0,	1,	0ull,	0},
+	{"RDS_MEM"                     ,	0,	1,	1267,	"RO",	1,	0,	0,	0ull},
+	{"LSLR_FIFO"                   ,	1,	1,	1267,	"RO",	1,	0,	0,	0ull},
+	{"WQE_FIFO"                    ,	2,	1,	1267,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	1267,	"RAZ",	1,	1,	0,	0},
+	{"FSM0_STATE"                  ,	0,	4,	1268,	"RO",	0,	0,	0ull,	0ull},
+	{"FSM1_STATE"                  ,	4,	4,	1268,	"RO",	0,	0,	0ull,	0ull},
+	{"FSM2_STATE"                  ,	8,	4,	1268,	"RO",	0,	0,	0ull,	0ull},
+	{"FSM3_STATE"                  ,	12,	4,	1268,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1268,	"RAZ",	1,	1,	0,	0},
+	{"WQE_FIFO_LEVEL"              ,	32,	8,	1268,	"RO",	0,	0,	0ull,	0ull},
+	{"RWF_FIFO_LEVEL"              ,	40,	5,	1268,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_47"              ,	45,	3,	1268,	"RAZ",	1,	1,	0,	0},
+	{"GNT_FIFO_LEVEL"              ,	48,	3,	1268,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_55"              ,	51,	5,	1268,	"RAZ",	1,	1,	0,	0},
+	{"MEM_ALLOC_REG"               ,	56,	8,	1268,	"RO",	0,	0,	0ull,	0ull},
+	{"RINGS_PENDING_VEC"           ,	0,	64,	1269,	"RO",	0,	0,	0ull,	0ull},
+	{"ECC_EN"                      ,	0,	1,	1270,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECC_FLP_SYN"                 ,	1,	2,	1270,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	1270,	"RAZ",	1,	1,	0,	0},
+	{"FR_RN_TT"                    ,	0,	22,	1271,	"R/W",	0,	0,	1024ull,	1024ull},
+	{"RESERVED_22_31"              ,	22,	10,	1271,	"RAZ",	1,	1,	0,	0},
+	{"THLD_GP"                     ,	32,	22,	1271,	"R/W",	0,	0,	1024ull,	1024ull},
+	{"RESERVED_54_63"              ,	54,	10,	1271,	"RAZ",	1,	1,	0,	0},
+	{"GPIO_EN"                     ,	0,	64,	1272,	"RO",	0,	0,	0ull,	0ull},
+	{"INT0"                        ,	0,	64,	1273,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INT0_EN"                     ,	0,	64,	1274,	"R/W",	0,	0,	0ull,	0ull},
+	{"RING_ID"                     ,	0,	6,	1275,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1275,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	1276,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	1276,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1276,	"RAZ",	1,	1,	0,	0},
+	{"SBE_EN"                      ,	0,	1,	1277,	"R/W",	0,	0,	0ull,	0ull},
+	{"DBE_EN"                      ,	1,	1,	1277,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1277,	"RAZ",	1,	1,	0,	0},
+	{"ADD"                         ,	0,	8,	1278,	"RO",	0,	0,	0ull,	0ull},
+	{"SYND"                        ,	8,	7,	1278,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	1278,	"RAZ",	1,	1,	0,	0},
+	{"ORG_RDS_DAT"                 ,	0,	48,	1279,	"RO",	0,	0,	0ull,	0ull},
+	{"ORG_ECC"                     ,	48,	7,	1279,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	1279,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE_TIMERS"               ,	0,	1,	1280,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	1280,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	2,	1,	1280,	"WO",	0,	0,	0ull,	0ull},
+	{"ENA_DFB"                     ,	3,	1,	1280,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_GPIO"                    ,	4,	1,	1280,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO_EDGE"                   ,	5,	2,	1280,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	1280,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	22,	1281,	"R/W",	1,	0,	0,	0ull},
+	{"TIMERCOUNT"                  ,	22,	22,	1281,	"R/W",	1,	0,	0,	0ull},
+	{"INTC"                        ,	44,	2,	1281,	"R/W",	1,	0,	0,	0ull},
+	{"ENA"                         ,	46,	1,	1281,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	1281,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	20,	1282,	"R/W",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	20,	20,	1282,	"R/W",	1,	0,	0,	0ull},
+	{"CPOOL"                       ,	40,	3,	1282,	"R/W",	1,	0,	0,	0ull},
+	{"ENA_DFB"                     ,	43,	1,	1282,	"R/W",	1,	0,	0,	0ull},
+	{"ENA_DWB"                     ,	44,	1,	1282,	"R/W",	1,	0,	0,	0ull},
+	{"ENA_PRD"                     ,	45,	1,	1282,	"R/W",	1,	0,	0,	0ull},
+	{"ENA_GPIO"                    ,	46,	1,	1282,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	1282,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	31,	1283,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_33"              ,	31,	3,	1283,	"RAZ",	1,	1,	0,	0},
+	{"CSIZE"                       ,	34,	13,	1283,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	1283,	"RAZ",	1,	1,	0,	0},
+	{"CUR_BUCKET"                  ,	0,	20,	1284,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMERCOUNT"                  ,	20,	22,	1284,	"RO",	0,	0,	4096ull,	0ull},
+	{"FR_RN_HT"                    ,	42,	22,	1284,	"RO",	0,	0,	0ull,	0ull},
+	{"RING_ESR"                    ,	0,	2,	1285,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1285,	"RAZ",	1,	1,	0,	0},
+	{"TDF"                         ,	0,	1,	1286,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1286,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	1287,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRAP"                        ,	1,	1,	1287,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRIG_CTL"                    ,	2,	2,	1287,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIME_GRN"                    ,	4,	3,	1287,	"R/W",	0,	0,	0ull,	0ull},
+	{"FULL_THR"                    ,	7,	2,	1287,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	9,	1,	1287,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	10,	1,	1287,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	11,	1,	1287,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	12,	1,	1287,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_ENA"                    ,	13,	1,	1287,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNORE_O"                    ,	14,	1,	1287,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKALWAYS"                   ,	15,	1,	1287,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDAT_MD"                     ,	16,	1,	1287,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	1287,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	8,	1288,	"RO",	0,	0,	0ull,	0ull},
+	{"RPTR"                        ,	8,	8,	1288,	"RO",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	16,	48,	1288,	"RO",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	10,	1289,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	1289,	"RAZ",	1,	1,	0,	0},
+	{"RPTR"                        ,	12,	10,	1289,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1289,	"RAZ",	1,	1,	0,	0},
+	{"CYCLES"                      ,	24,	40,	1289,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1290,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1290,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1291,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1291,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1292,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1292,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1292,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1292,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1292,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1292,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1293,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1293,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1293,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1293,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1293,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1293,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1293,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1293,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1293,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1293,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1293,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1293,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1293,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1293,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1293,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1293,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1293,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1293,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1293,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1293,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	8,	1294,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1294,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1294,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1294,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1294,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1294,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1294,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	0,	1,	1295,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	1,	1,	1295,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	2,	1,	1295,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	3,	1,	1295,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1295,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	1296,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	5,	1297,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	1297,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1298,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1298,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1299,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1299,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1300,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1300,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1300,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1300,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1300,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1300,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1301,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1301,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1301,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1301,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1301,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1301,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1301,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1301,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1301,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1301,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1301,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1301,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1301,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1301,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1301,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1301,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1301,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1301,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1301,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1301,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	8,	1302,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1302,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1302,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1302,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1302,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1302,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1302,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1303,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1303,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1304,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1304,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1305,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1305,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1305,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1305,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1305,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1305,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1306,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1306,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1306,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1306,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1306,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1306,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1306,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1306,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1306,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1306,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1306,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1306,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1306,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1306,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1306,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1306,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1306,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1306,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1306,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1306,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	8,	1307,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1307,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1307,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1307,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1307,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1307,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1307,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	1308,	"R/W",	0,	1,	0ull,	0},
+	{"LPL"                         ,	5,	27,	1308,	"R/W",	0,	1,	0ull,	0},
+	{"CF"                          ,	0,	1,	1309,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_31"               ,	1,	31,	1309,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTRLDSSEG"                   ,	0,	32,	1310,	"R/W",	0,	1,	0ull,	0},
+	{"FI"                          ,	0,	14,	1311,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_31"              ,	14,	18,	1311,	"RO",	0,	0,	0ull,	0ull},
+	{"CAPLENGTH"                   ,	0,	8,	1312,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_8_15"               ,	8,	8,	1312,	"RO",	0,	0,	0ull,	0ull},
+	{"HCIVERSION"                  ,	16,	16,	1312,	"RO",	0,	0,	256ull,	256ull},
+	{"AC64"                        ,	0,	1,	1313,	"RO",	0,	0,	1ull,	1ull},
+	{"PFLF"                        ,	1,	1,	1313,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPC"                        ,	2,	1,	1313,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1313,	"RO",	0,	0,	0ull,	0ull},
+	{"IST"                         ,	4,	4,	1313,	"RO",	0,	0,	2ull,	2ull},
+	{"EECP"                        ,	8,	8,	1313,	"RO",	0,	0,	160ull,	160ull},
+	{"RESERVED_16_31"              ,	16,	16,	1313,	"RO",	0,	0,	0ull,	0ull},
+	{"N_PORTS"                     ,	0,	4,	1314,	"RO",	0,	0,	2ull,	2ull},
+	{"PPC"                         ,	4,	1,	1314,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	1314,	"RO",	0,	0,	0ull,	0ull},
+	{"PRR"                         ,	7,	1,	1314,	"RO",	0,	0,	0ull,	0ull},
+	{"N_PCC"                       ,	8,	4,	1314,	"RO",	0,	0,	2ull,	2ull},
+	{"N_CC"                        ,	12,	4,	1314,	"RO",	0,	0,	1ull,	1ull},
+	{"P_INDICATOR"                 ,	16,	1,	1314,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	1314,	"RO",	0,	0,	0ull,	0ull},
+	{"DPN"                         ,	20,	4,	1314,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1314,	"RO",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	0,	1,	1315,	"R/W",	0,	0,	0ull,	0ull},
+	{"MFMC"                        ,	1,	13,	1315,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	1315,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_0"                ,	0,	1,	1316,	"R/W",	0,	0,	0ull,	0ull},
+	{"TA_OFF"                      ,	1,	8,	1316,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	1316,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXTX_TADAO"                  ,	10,	3,	1316,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	1316,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCP_RW"                      ,	0,	1,	1317,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCP_FW"                      ,	1,	1,	1317,	"R/W",	0,	0,	0ull,	0ull},
+	{"PESD"                        ,	2,	1,	1317,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1317,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NAKRF_DIS"                   ,	4,	1,	1317,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTO_DIS"                    ,	5,	1,	1317,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	1317,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_30"               ,	0,	31,	1318,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	31,	1,	1318,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_ADDR"                    ,	0,	32,	1319,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_11"               ,	0,	12,	1320,	"R/W",	0,	1,	0ull,	0},
+	{"BADDR"                       ,	12,	20,	1320,	"R/W",	0,	1,	0ull,	0},
+	{"CCS"                         ,	0,	1,	1321,	"RO",	0,	0,	0ull,	0ull},
+	{"CSC"                         ,	1,	1,	1321,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PED"                         ,	2,	1,	1321,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEDC"                        ,	3,	1,	1321,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OCA"                         ,	4,	1,	1321,	"RO",	0,	0,	0ull,	0ull},
+	{"OCC"                         ,	5,	1,	1321,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPR"                         ,	6,	1,	1321,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPD"                         ,	7,	1,	1321,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRST"                        ,	8,	1,	1321,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	1321,	"RO",	0,	0,	0ull,	0ull},
+	{"LSTS"                        ,	10,	2,	1321,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	12,	1,	1321,	"RO",	0,	0,	1ull,	1ull},
+	{"PO"                          ,	13,	1,	1321,	"R/W",	0,	0,	1ull,	0ull},
+	{"PIC"                         ,	14,	2,	1321,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTC"                         ,	16,	4,	1321,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKCNNT_E"                    ,	20,	1,	1321,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKDSCNNT_E"                  ,	21,	1,	1321,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKOC_E"                      ,	22,	1,	1321,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	1321,	"RO",	0,	0,	0ull,	0ull},
+	{"RS"                          ,	0,	1,	1322,	"R/W",	0,	0,	0ull,	1ull},
+	{"HCRESET"                     ,	1,	1,	1322,	"R/W",	0,	0,	0ull,	0ull},
+	{"FLS"                         ,	2,	2,	1322,	"RO",	0,	0,	0ull,	0ull},
+	{"PS_EN"                       ,	4,	1,	1322,	"R/W",	0,	0,	0ull,	0ull},
+	{"AS_EN"                       ,	5,	1,	1322,	"R/W",	0,	0,	0ull,	0ull},
+	{"IAA_DB"                      ,	6,	1,	1322,	"R/W",	0,	0,	0ull,	0ull},
+	{"LHCR"                        ,	7,	1,	1322,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASPMC"                       ,	8,	2,	1322,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	1322,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPM_EN"                     ,	11,	1,	1322,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	1322,	"RO",	0,	0,	0ull,	0ull},
+	{"ITC"                         ,	16,	8,	1322,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_24_31"              ,	24,	8,	1322,	"RO",	0,	0,	0ull,	0ull},
+	{"USBINT_EN"                   ,	0,	1,	1323,	"R/W",	0,	1,	0ull,	0},
+	{"USBERRINT_EN"                ,	1,	1,	1323,	"R/W",	0,	1,	0ull,	0},
+	{"PCI_EN"                      ,	2,	1,	1323,	"R/W",	0,	1,	0ull,	0},
+	{"FLRO_EN"                     ,	3,	1,	1323,	"R/W",	0,	1,	0ull,	0},
+	{"HSERR_EN"                    ,	4,	1,	1323,	"R/W",	0,	1,	0ull,	0},
+	{"IOAA_EN"                     ,	5,	1,	1323,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_31"               ,	6,	26,	1323,	"RO",	0,	0,	0ull,	0ull},
+	{"USBINT"                      ,	0,	1,	1324,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBERRINT"                   ,	1,	1,	1324,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCD"                         ,	2,	1,	1324,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FLRO"                        ,	3,	1,	1324,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HSYSERR"                     ,	4,	1,	1324,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOAA"                        ,	5,	1,	1324,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	1324,	"RO",	0,	0,	0ull,	0ull},
+	{"HCHTD"                       ,	12,	1,	1324,	"RO",	0,	0,	1ull,	0ull},
+	{"RECLM"                       ,	13,	1,	1324,	"RO",	0,	0,	0ull,	0ull},
+	{"PSS"                         ,	14,	1,	1324,	"RO",	0,	0,	0ull,	0ull},
+	{"ASS"                         ,	15,	1,	1324,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1324,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1325,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCED"                        ,	4,	28,	1325,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1326,	"R/W",	0,	0,	0ull,	0ull},
+	{"BHED"                        ,	4,	28,	1326,	"R/W",	0,	1,	0ull,	0},
+	{"HCR"                         ,	0,	1,	1327,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLF"                         ,	1,	1,	1327,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLF"                         ,	2,	1,	1327,	"R/W",	0,	0,	0ull,	0ull},
+	{"OCR"                         ,	3,	1,	1327,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	1327,	"RO",	0,	0,	0ull,	0ull},
+	{"SOC"                         ,	16,	2,	1327,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	1327,	"RO",	0,	0,	0ull,	0ull},
+	{"CBSR"                        ,	0,	2,	1328,	"R/W",	0,	1,	0ull,	0},
+	{"PLE"                         ,	2,	1,	1328,	"R/W",	0,	0,	0ull,	0ull},
+	{"IE"                          ,	3,	1,	1328,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLE"                         ,	4,	1,	1328,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLE"                         ,	5,	1,	1328,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCFS"                        ,	6,	2,	1328,	"R/W",	0,	0,	0ull,	0ull},
+	{"IR"                          ,	8,	1,	1328,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWC"                         ,	9,	1,	1328,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWE"                         ,	10,	1,	1328,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	1328,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1329,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCED"                        ,	4,	28,	1329,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1330,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHED"                        ,	4,	28,	1330,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1331,	"RO",	0,	0,	0ull,	0ull},
+	{"DH"                          ,	4,	28,	1331,	"RO",	0,	1,	0ull,	0},
+	{"FI"                          ,	0,	14,	1332,	"R/W",	0,	1,	11999ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	1332,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSMPS"                       ,	16,	15,	1332,	"R/W",	0,	1,	0ull,	0},
+	{"FIT"                         ,	31,	1,	1332,	"R/W",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	0,	16,	1333,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	1333,	"RO",	0,	0,	0ull,	0ull},
+	{"FR"                          ,	0,	14,	1334,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_30"              ,	14,	17,	1334,	"RO",	0,	0,	0ull,	0ull},
+	{"FRT"                         ,	31,	1,	1334,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	1335,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCCA"                        ,	8,	24,	1335,	"R/W",	0,	1,	0ull,	0},
+	{"SO"                          ,	0,	1,	1336,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1336,	"R/W",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1336,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1336,	"R/W",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1336,	"R/W",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1336,	"R/W",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1336,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1336,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1336,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIE"                         ,	31,	1,	1336,	"R/W",	0,	0,	0ull,	0ull},
+	{"SO"                          ,	0,	1,	1337,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1337,	"R/W",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1337,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1337,	"R/W",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1337,	"R/W",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1337,	"R/W",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1337,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1337,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1337,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIE"                         ,	31,	1,	1337,	"R/W",	0,	0,	0ull,	0ull},
+	{"SO"                          ,	0,	1,	1338,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1338,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1338,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1338,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1338,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1338,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1338,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1338,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1338,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1338,	"RO",	0,	0,	0ull,	0ull},
+	{"LST"                         ,	0,	12,	1339,	"R/W",	0,	1,	1576ull,	0},
+	{"RESERVED_12_31"              ,	12,	20,	1339,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1340,	"RO",	0,	0,	0ull,	0ull},
+	{"PCED"                        ,	4,	28,	1340,	"RO",	0,	1,	0ull,	0},
+	{"PS"                          ,	0,	14,	1341,	"R/W",	0,	0,	0ull,	15975ull},
+	{"RESERVED_14_31"              ,	14,	18,	1341,	"R/W",	0,	0,	0ull,	0ull},
+	{"REV"                         ,	0,	8,	1342,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_8_31"               ,	8,	24,	1342,	"RO",	0,	0,	0ull,	0ull},
+	{"NDP"                         ,	0,	8,	1343,	"RO",	0,	0,	2ull,	2ull},
+	{"NPS"                         ,	8,	1,	1343,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSM"                         ,	9,	1,	1343,	"R/W",	0,	0,	1ull,	1ull},
+	{"DT"                          ,	10,	1,	1343,	"RO",	0,	0,	0ull,	0ull},
+	{"OCPM"                        ,	11,	1,	1343,	"R/W",	1,	1,	0,	0},
+	{"NOCP"                        ,	12,	1,	1343,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_23"              ,	13,	11,	1343,	"RO",	0,	0,	0ull,	0ull},
+	{"POTPGT"                      ,	24,	8,	1343,	"R/W",	0,	0,	1ull,	1ull},
+	{"DR"                          ,	0,	16,	1344,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPCM"                        ,	16,	16,	1344,	"R/W",	0,	1,	0ull,	0},
+	{"CCS"                         ,	0,	1,	1345,	"R/W",	0,	1,	0ull,	0},
+	{"PES"                         ,	1,	1,	1345,	"R/W",	0,	1,	0ull,	0},
+	{"PSS"                         ,	2,	1,	1345,	"R/W",	0,	1,	0ull,	0},
+	{"POCI"                        ,	3,	1,	1345,	"R/W",	0,	1,	0ull,	0},
+	{"PRS"                         ,	4,	1,	1345,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1345,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS"                         ,	8,	1,	1345,	"R/W",	0,	1,	0ull,	0},
+	{"LSDA"                        ,	9,	1,	1345,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_10_15"              ,	10,	6,	1345,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSC"                         ,	16,	1,	1345,	"R/W",	0,	1,	0ull,	0},
+	{"PESC"                        ,	17,	1,	1345,	"R/W",	0,	1,	0ull,	0},
+	{"PSSC"                        ,	18,	1,	1345,	"R/W",	0,	1,	0ull,	0},
+	{"OCIC"                        ,	19,	1,	1345,	"R/W",	0,	1,	0ull,	0},
+	{"PRSC"                        ,	20,	1,	1345,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_31"              ,	21,	11,	1345,	"R/W",	0,	0,	0ull,	0ull},
+	{"LPS"                         ,	0,	1,	1346,	"R/W",	0,	0,	0ull,	0ull},
+	{"OCI"                         ,	1,	1,	1346,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_14"               ,	2,	13,	1346,	"RO",	0,	0,	0ull,	0ull},
+	{"DRWE"                        ,	15,	1,	1346,	"R/W",	0,	1,	0ull,	0},
+	{"LPSC"                        ,	16,	1,	1346,	"R/W",	0,	1,	0ull,	0},
+	{"CCIC"                        ,	17,	1,	1346,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_18_30"              ,	18,	13,	1346,	"RO",	0,	0,	0ull,	0ull},
+	{"CRWE"                        ,	31,	1,	1346,	"WO",	1,	1,	0,	0},
+	{"RESERVED_0_30"               ,	0,	31,	1347,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	31,	1,	1347,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_ADDR"                    ,	0,	32,	1348,	"RO",	0,	0,	0ull,	0ull},
+	{"PPAF_BIS"                    ,	0,	1,	1349,	"RO",	0,	0,	0ull,	0ull},
+	{"WRBM_BIS"                    ,	1,	1,	1349,	"RO",	0,	0,	0ull,	0ull},
+	{"ORBM_BIS"                    ,	2,	1,	1349,	"RO",	0,	0,	0ull,	0ull},
+	{"ERBM_BIS"                    ,	3,	1,	1349,	"RO",	0,	0,	0ull,	0ull},
+	{"DESC_BIS"                    ,	4,	1,	1349,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_BIS"                    ,	5,	1,	1349,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1349,	"RO",	1,	1,	0,	0},
+	{"HRST"                        ,	0,	1,	1350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_PRST"                      ,	1,	1,	1350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_POR"                       ,	2,	1,	1350,	"R/W",	0,	0,	1ull,	0ull},
+	{"P_COM_ON"                    ,	3,	1,	1350,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	1350,	"R/W",	0,	1,	0ull,	0},
+	{"P_REFCLK_DIV"                ,	5,	2,	1350,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_REFCLK_SEL"                ,	7,	2,	1350,	"R/W",	0,	0,	0ull,	0ull},
+	{"H_DIV"                       ,	9,	4,	1350,	"R/W",	0,	0,	6ull,	6ull},
+	{"O_CLKDIV_EN"                 ,	13,	1,	1350,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_EN"                 ,	14,	1,	1350,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_RST"                ,	15,	1,	1350,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_BYP"                ,	16,	1,	1350,	"R/W",	0,	0,	0ull,	0ull},
+	{"O_CLKDIV_RST"                ,	17,	1,	1350,	"R/W",	0,	0,	0ull,	1ull},
+	{"APP_START_CLK"               ,	18,	1,	1350,	"R/W",	0,	0,	0ull,	0ull},
+	{"OHCI_SUSP_LGCY"              ,	19,	1,	1350,	"R/W",	0,	0,	1ull,	1ull},
+	{"OHCI_SM"                     ,	20,	1,	1350,	"R/W",	0,	0,	0ull,	0ull},
+	{"OHCI_CLKCKTRST"              ,	21,	1,	1350,	"R/W",	0,	0,	1ull,	1ull},
+	{"EHCI_SM"                     ,	22,	1,	1350,	"R/W",	0,	0,	0ull,	0ull},
+	{"START_BIST"                  ,	23,	1,	1350,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLEAR_BIST"                  ,	24,	1,	1350,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1350,	"RAZ",	1,	1,	0,	0},
+	{"L2C_ADDR_MSB"                ,	0,	8,	1351,	"R/W",	0,	1,	0ull,	0},
+	{"EHCI_64B_ADDR_EN"            ,	8,	1,	1351,	"R/W",	0,	0,	1ull,	1ull},
+	{"INV_REG_A2"                  ,	9,	1,	1351,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DESC_EMOD"               ,	10,	2,	1351,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BUFF_EMOD"               ,	12,	2,	1351,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2C_STT"                     ,	14,	1,	1351,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_0PAG"                    ,	15,	1,	1351,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BC"                      ,	16,	1,	1351,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DC"                      ,	17,	1,	1351,	"R/W",	0,	0,	1ull,	1ull},
+	{"REG_NB"                      ,	18,	1,	1351,	"R/W",	0,	0,	0ull,	0ull},
+	{"DESC_RBM"                    ,	19,	1,	1351,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1351,	"RAZ",	1,	1,	0,	0},
+	{"FLA"                         ,	0,	6,	1352,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	1352,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	1353,	"RAZ",	1,	1,	0,	0},
+	{"TO_VAL"                      ,	5,	27,	1353,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1353,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	1354,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	1354,	"RAZ",	1,	1,	0,	0},
+	{"PP_PSH_F"                    ,	0,	1,	1355,	"R/W",	0,	0,	0ull,	0ull},
+	{"ER_PSH_F"                    ,	1,	1,	1355,	"R/W",	0,	0,	0ull,	0ull},
+	{"OR_PSH_F"                    ,	2,	1,	1355,	"R/W",	0,	0,	0ull,	0ull},
+	{"CF_PSH_F"                    ,	3,	1,	1355,	"R/W",	0,	0,	0ull,	0ull},
+	{"WB_PSH_F"                    ,	4,	1,	1355,	"R/W",	0,	0,	0ull,	0ull},
+	{"WB_POP_E"                    ,	5,	1,	1355,	"R/W",	0,	0,	0ull,	0ull},
+	{"OC_OVF_E"                    ,	6,	1,	1355,	"R/W",	0,	0,	0ull,	0ull},
+	{"EC_OVF_E"                    ,	7,	1,	1355,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1355,	"RAZ",	1,	1,	0,	0},
+	{"PP_PSH_F"                    ,	0,	1,	1356,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ER_PSH_F"                    ,	1,	1,	1356,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OR_PSH_F"                    ,	2,	1,	1356,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CF_PSH_F"                    ,	3,	1,	1356,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WB_PSH_F"                    ,	4,	1,	1356,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WB_POP_E"                    ,	5,	1,	1356,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OC_OVF_E"                    ,	6,	1,	1356,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EC_OVF_E"                    ,	7,	1,	1356,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1356,	"RAZ",	1,	1,	0,	0},
+	{"L2C_ADDR_MSB"                ,	0,	8,	1357,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_8"                ,	8,	1,	1357,	"RAZ",	1,	1,	0,	0},
+	{"INV_REG_A2"                  ,	9,	1,	1357,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DESC_EMOD"               ,	10,	2,	1357,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BUFF_EMOD"               ,	12,	2,	1357,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2C_STT"                     ,	14,	1,	1357,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_0PAG"                    ,	15,	1,	1357,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BC"                      ,	16,	1,	1357,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DC"                      ,	17,	1,	1357,	"R/W",	0,	0,	1ull,	1ull},
+	{"REG_NB"                      ,	18,	1,	1357,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	1357,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1358,	"RAZ",	1,	1,	0,	0},
+	{"TO_VAL"                      ,	8,	24,	1358,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1358,	"RAZ",	1,	1,	0,	0},
+	{"ATE_RESET"                   ,	0,	1,	1359,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_EN"                     ,	1,	1,	1359,	"R/W",	0,	0,	0ull,	0ull},
+	{"UPHY_BIST"                   ,	2,	1,	1359,	"R/W",	0,	0,	0ull,	0ull},
+	{"VTEST_EN"                    ,	3,	1,	1359,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIDDQ"                       ,	4,	1,	1359,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBIST"                      ,	5,	1,	1359,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSBIST"                      ,	6,	1,	1359,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSBIST"                      ,	7,	1,	1359,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_ERR"                    ,	8,	1,	1359,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST_DONE"                   ,	9,	1,	1359,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1359,	"RAZ",	1,	1,	0,	0},
+	{"TDATA_IN"                    ,	0,	8,	1360,	"R/W",	0,	0,	0ull,	0ull},
+	{"TADDR_IN"                    ,	8,	4,	1360,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_SEL"                   ,	12,	1,	1360,	"R/W",	0,	0,	1ull,	0ull},
+	{"TCLK"                        ,	13,	1,	1360,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOP_EN"                     ,	14,	1,	1360,	"R/W",	0,	0,	0ull,	0ull},
+	{"COMPDISTUNE"                 ,	15,	3,	1360,	"R/W",	0,	0,	4ull,	4ull},
+	{"SQRXTUNE"                    ,	18,	3,	1360,	"R/W",	0,	0,	4ull,	4ull},
+	{"TXFSLSTUNE"                  ,	21,	4,	1360,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPREEMPHASISTUNE"           ,	25,	1,	1360,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXRISETUNE"                  ,	26,	1,	1360,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXVREFTUNE"                  ,	27,	4,	1360,	"R/W",	0,	0,	5ull,	15ull},
+	{"TXHSVXTUNE"                  ,	31,	2,	1360,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORTRESET"                   ,	33,	1,	1360,	"R/W",	0,	0,	0ull,	0ull},
+	{"VBUSVLDEXT"                  ,	34,	1,	1360,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPPULLDOWN"                  ,	35,	1,	1360,	"R/W",	0,	0,	1ull,	1ull},
+	{"DMPULLDOWN"                  ,	36,	1,	1360,	"R/W",	0,	0,	1ull,	1ull},
+	{"TXBISTSTUFFEN"               ,	37,	1,	1360,	"R/W",	0,	0,	1ull,	1ull},
+	{"TXBISTSTUFFENH"              ,	38,	1,	1360,	"R/W",	0,	0,	1ull,	1ull},
+	{"TDATA_OUT"                   ,	39,	4,	1360,	"RO",	1,	1,	0,	0},
+	{"RESERVED_43_63"              ,	43,	21,	1360,	"RAZ",	1,	1,	0,	0},
+	{"ZIP_CTL"                     ,	0,	4,	1361,	"RO",	1,	0,	0,	0ull},
+	{"ZIP_CORE"                    ,	4,	53,	1361,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_57_63"              ,	57,	7,	1361,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	1362,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	33,	13,	1362,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	46,	3,	1362,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	49,	9,	1362,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	1362,	"RAZ",	1,	1,	0,	0},
+	{"RESET"                       ,	0,	1,	1363,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FORCECLK"                    ,	1,	1,	1363,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1363,	"RAZ",	1,	1,	0,	0},
+	{"DISABLED"                    ,	0,	1,	1364,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	1364,	"RAZ",	1,	1,	0,	0},
+	{"CTXSIZE"                     ,	8,	12,	1364,	"RO",	0,	0,	1536ull,	1536ull},
+	{"ONFSIZE"                     ,	20,	12,	1364,	"RO",	0,	0,	512ull,	512ull},
+	{"DEPTH"                       ,	32,	16,	1364,	"RO",	0,	0,	31744ull,	31744ull},
+	{"SYNCFLUSH_CAPABLE"           ,	48,	1,	1364,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_49_55"              ,	49,	7,	1364,	"RAZ",	1,	1,	0,	0},
+	{"NEXEC"                       ,	56,	8,	1364,	"RO",	0,	0,	2ull,	2ull},
+	{"BSTATUS"                     ,	0,	53,	1365,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_53_63"              ,	53,	11,	1365,	"RAZ",	1,	1,	0,	0},
+	{"BSTATUS"                     ,	0,	7,	1366,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	1366,	"RAZ",	1,	1,	0,	0},
+	{"LMOD"                        ,	0,	1,	1367,	"R/W",	0,	0,	0ull,	0ull},
+	{"BUSY"                        ,	1,	1,	1367,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_2_3"                ,	2,	2,	1367,	"RAZ",	1,	0,	0,	0ull},
+	{"WKQF"                        ,	4,	2,	1367,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_7"                ,	6,	2,	1367,	"RAZ",	1,	0,	0,	0ull},
+	{"LDF"                         ,	8,	3,	1367,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_11_11"              ,	11,	1,	1367,	"RAZ",	1,	0,	0,	0ull},
+	{"STCF"                        ,	12,	3,	1367,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_15_15"              ,	15,	1,	1367,	"RAZ",	1,	0,	0,	0ull},
+	{"GSTF"                        ,	16,	3,	1367,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_19_19"              ,	19,	1,	1367,	"RAZ",	1,	0,	0,	0ull},
+	{"IPRF"                        ,	20,	2,	1367,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_22_23"              ,	22,	2,	1367,	"RAZ",	1,	0,	0,	0ull},
+	{"ILDF"                        ,	24,	3,	1367,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_27_63"              ,	27,	37,	1367,	"RAZ",	1,	0,	0,	0ull},
+	{"IID"                         ,	0,	32,	1368,	"RO",	0,	1,	0ull,	0},
+	{"QID"                         ,	32,	1,	1368,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_33_62"              ,	33,	30,	1368,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	63,	1,	1368,	"RO",	0,	1,	0ull,	0},
+	{"NIE"                         ,	0,	32,	1369,	"RO",	0,	1,	0ull,	0},
+	{"IST"                         ,	32,	5,	1369,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_37_62"              ,	37,	26,	1369,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	63,	1,	1369,	"RO",	0,	1,	0ull,	0},
+	{"NII"                         ,	0,	32,	1370,	"RO",	0,	1,	0ull,	0},
+	{"CDBC"                        ,	32,	20,	1370,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_62"              ,	52,	11,	1370,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	63,	1,	1370,	"RO",	0,	1,	0ull,	0},
+	{"ASSERTS"                     ,	0,	30,	1371,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_63"              ,	30,	34,	1371,	"RAZ",	1,	1,	0,	0},
+	{"IBEN"                        ,	0,	1,	1372,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_31"               ,	1,	31,	1372,	"RAZ",	1,	1,	0,	0},
+	{"IBGE"                        ,	32,	2,	1372,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	1372,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1373,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1373,	"RAZ",	1,	1,	0,	0},
+	{"FIFE"                        ,	0,	1,	1374,	"R/W",	0,	0,	0ull,	0ull},
+	{"IBSBE"                       ,	1,	1,	1374,	"R/W",	0,	0,	0ull,	0ull},
+	{"IBDBE"                       ,	2,	1,	1374,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	1374,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL0"                   ,	8,	1,	1374,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL1"                   ,	9,	1,	1374,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1374,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1375,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1375,	"RAZ",	1,	1,	0,	0},
+	{"FIFE"                        ,	0,	1,	1376,	"RO",	0,	0,	0ull,	0ull},
+	{"IBSBE"                       ,	1,	1,	1376,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IBDBE"                       ,	2,	1,	1376,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	1376,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL0"                   ,	8,	1,	1376,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL1"                   ,	9,	1,	1376,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1376,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	1377,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	33,	13,	1377,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	46,	3,	1377,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	49,	9,	1377,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	1377,	"RAZ",	1,	1,	0,	0},
+	{"INUM"                        ,	0,	32,	1378,	"RO",	0,	0,	0ull,	0ull},
+	{"WNUM"                        ,	32,	3,	1378,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	1378,	"RAZ",	1,	1,	0,	0},
+	{"ZCE"                         ,	0,	2,	1379,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_2_63"               ,	2,	62,	1379,	"RAZ",	1,	1,	0,	0},
+	{"ENA"                         ,	0,	2,	1380,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_2_63"               ,	2,	62,	1380,	"RAZ",	1,	1,	0,	0},
+	{"PRI"                         ,	0,	2,	1381,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1381,	"RAZ",	1,	1,	0,	0},
+	{"MAX_INFL"                    ,	0,	5,	1382,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	1382,	"RAZ",	1,	1,	0,	0},
+	{NULL,0,0,0,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cnf71xx[] = {
+	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
+	{"cvmx_ciu_bist"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	0,	2,	0},
+	{"cvmx_ciu_block_int"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1,	29,	2},
+	{"cvmx_ciu_dint"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	2,	2,	31},
+	{"cvmx_ciu_en2_io#_int"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	3,	6,	33},
+	{"cvmx_ciu_en2_io#_int_w1c"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	5,	6,	39},
+	{"cvmx_ciu_en2_io#_int_w1s"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	7,	6,	45},
+	{"cvmx_ciu_en2_pp#_ip2"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	9,	6,	51},
+	{"cvmx_ciu_en2_pp#_ip2_w1c"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	13,	6,	57},
+	{"cvmx_ciu_en2_pp#_ip2_w1s"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	17,	6,	63},
+	{"cvmx_ciu_en2_pp#_ip3"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	21,	6,	69},
+	{"cvmx_ciu_en2_pp#_ip3_w1c"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	25,	6,	75},
+	{"cvmx_ciu_en2_pp#_ip3_w1s"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	29,	6,	81},
+	{"cvmx_ciu_en2_pp#_ip4"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	33,	6,	87},
+	{"cvmx_ciu_en2_pp#_ip4_w1c"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	37,	6,	93},
+	{"cvmx_ciu_en2_pp#_ip4_w1s"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	41,	6,	99},
+	{"cvmx_ciu_fuse"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	45,	2,	105},
+	{"cvmx_ciu_gstop"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	46,	2,	107},
+	{"cvmx_ciu_int#_en0"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	47,	23,	109},
+	{"cvmx_ciu_int#_en0_w1c"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	57,	23,	132},
+	{"cvmx_ciu_int#_en0_w1s"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	67,	23,	155},
+	{"cvmx_ciu_int#_en1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	77,	30,	178},
+	{"cvmx_ciu_int#_en1_w1c"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	87,	30,	208},
+	{"cvmx_ciu_int#_en1_w1s"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	97,	30,	238},
+	{"cvmx_ciu_int#_en4_0"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	107,	23,	268},
+	{"cvmx_ciu_int#_en4_0_w1c"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	111,	23,	291},
+	{"cvmx_ciu_int#_en4_0_w1s"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	115,	23,	314},
+	{"cvmx_ciu_int#_en4_1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	119,	30,	337},
+	{"cvmx_ciu_int#_en4_1_w1c"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	123,	30,	367},
+	{"cvmx_ciu_int#_en4_1_w1s"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	127,	30,	397},
+	{"cvmx_ciu_int#_sum0"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	131,	23,	427},
+	{"cvmx_ciu_int#_sum4"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	140,	23,	450},
+	{"cvmx_ciu_int33_sum0"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	144,	23,	473},
+	{"cvmx_ciu_int_dbg_sel"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	145,	6,	496},
+	{"cvmx_ciu_int_sum1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	146,	28,	502},
+	{"cvmx_ciu_mbox_clr#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	147,	2,	530},
+	{"cvmx_ciu_mbox_set#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	151,	2,	532},
+	{"cvmx_ciu_nmi"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	155,	2,	534},
+	{"cvmx_ciu_pci_inta"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	156,	2,	536},
+	{"cvmx_ciu_pp_dbg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	157,	2,	538},
+	{"cvmx_ciu_pp_poke#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	158,	1,	540},
+	{"cvmx_ciu_pp_rst"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	162,	3,	541},
+	{"cvmx_ciu_qlm0"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	163,	13,	544},
+	{"cvmx_ciu_qlm1"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	164,	13,	557},
+	{"cvmx_ciu_qlm2"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	165,	8,	570},
+	{"cvmx_ciu_qlm_jtgc"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	166,	6,	578},
+	{"cvmx_ciu_qlm_jtgd"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	167,	8,	584},
+	{"cvmx_ciu_soft_bist"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	168,	2,	592},
+	{"cvmx_ciu_soft_prst"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	169,	2,	594},
+	{"cvmx_ciu_soft_prst1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	170,	2,	596},
+	{"cvmx_ciu_soft_rst"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	171,	2,	598},
+	{"cvmx_ciu_sum1_io#_int"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	172,	30,	600},
+	{"cvmx_ciu_sum1_pp#_ip2"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	174,	30,	630},
+	{"cvmx_ciu_sum1_pp#_ip3"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	178,	30,	660},
+	{"cvmx_ciu_sum1_pp#_ip4"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	182,	30,	690},
+	{"cvmx_ciu_sum2_io#_int"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	186,	6,	720},
+	{"cvmx_ciu_sum2_pp#_ip2"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	188,	6,	726},
+	{"cvmx_ciu_sum2_pp#_ip3"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	192,	6,	732},
+	{"cvmx_ciu_sum2_pp#_ip4"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	196,	6,	738},
+	{"cvmx_ciu_tim#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	200,	3,	744},
+	{"cvmx_ciu_tim_multi_cast"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	210,	2,	747},
+	{"cvmx_ciu_wdog#"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	211,	7,	749},
+	{"cvmx_dpi_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	215,	2,	756},
+	{"cvmx_dpi_ctl"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	216,	2,	758},
+	{"cvmx_dpi_dma#_counts"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	217,	3,	760},
+	{"cvmx_dpi_dma#_dbell"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	225,	2,	763},
+	{"cvmx_dpi_dma#_err_rsp_status",	CVMX_CSR_DB_TYPE_NCB,	64,	233,	2,	765},
+	{"cvmx_dpi_dma#_ibuff_saddr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	241,	7,	767},
+	{"cvmx_dpi_dma#_iflight"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	249,	2,	774},
+	{"cvmx_dpi_dma#_naddr"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	257,	2,	776},
+	{"cvmx_dpi_dma#_reqbnk0"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	265,	1,	778},
+	{"cvmx_dpi_dma#_reqbnk1"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	273,	1,	779},
+	{"cvmx_dpi_dma_control"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	281,	20,	780},
+	{"cvmx_dpi_dma_eng#_en"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	282,	2,	800},
+	{"cvmx_dpi_dma_pp#_cnt"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	288,	2,	802},
+	{"cvmx_dpi_eng#_buf"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	292,	5,	804},
+	{"cvmx_dpi_info_reg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	298,	5,	809},
+	{"cvmx_dpi_int_en"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	299,	17,	814},
+	{"cvmx_dpi_int_reg"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	300,	17,	831},
+	{"cvmx_dpi_ncb#_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	301,	2,	848},
+	{"cvmx_dpi_pint_info"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	302,	4,	850},
+	{"cvmx_dpi_pkt_err_rsp"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	303,	2,	854},
+	{"cvmx_dpi_req_err_rsp"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	304,	2,	856},
+	{"cvmx_dpi_req_err_rsp_en"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	305,	2,	858},
+	{"cvmx_dpi_req_err_rst"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	306,	2,	860},
+	{"cvmx_dpi_req_err_rst_en"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	307,	2,	862},
+	{"cvmx_dpi_req_err_skip_comp"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	308,	4,	864},
+	{"cvmx_dpi_req_gbl_en"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	309,	2,	868},
+	{"cvmx_dpi_sli_prt#_cfg"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	310,	13,	870},
+	{"cvmx_dpi_sli_prt#_err"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	312,	2,	883},
+	{"cvmx_dpi_sli_prt#_err_info"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	314,	6,	885},
+	{"cvmx_endor_adma_auto_clk_gate",	CVMX_CSR_DB_TYPE_NCB,	32,	316,	2,	891},
+	{"cvmx_endor_adma_axi_rspcode" ,	CVMX_CSR_DB_TYPE_NCB,	32,	317,	9,	893},
+	{"cvmx_endor_adma_axi_signal"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	318,	6,	902},
+	{"cvmx_endor_adma_axierr_intr" ,	CVMX_CSR_DB_TYPE_NCB,	32,	319,	2,	908},
+	{"cvmx_endor_adma_dma#_addr_hi",	CVMX_CSR_DB_TYPE_NCB,	32,	320,	2,	910},
+	{"cvmx_endor_adma_dma#_addr_lo",	CVMX_CSR_DB_TYPE_NCB,	32,	328,	1,	912},
+	{"cvmx_endor_adma_dma#_cfg"    ,	CVMX_CSR_DB_TYPE_NCB,	32,	336,	12,	913},
+	{"cvmx_endor_adma_dma#_size"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	344,	2,	925},
+	{"cvmx_endor_adma_dma_priority",	CVMX_CSR_DB_TYPE_NCB,	32,	352,	4,	927},
+	{"cvmx_endor_adma_dma_reset"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	353,	2,	931},
+	{"cvmx_endor_adma_dmadone_intr",	CVMX_CSR_DB_TYPE_NCB,	32,	354,	2,	933},
+	{"cvmx_endor_adma_intr_dis"    ,	CVMX_CSR_DB_TYPE_NCB,	32,	355,	3,	935},
+	{"cvmx_endor_adma_intr_enb"    ,	CVMX_CSR_DB_TYPE_NCB,	32,	356,	3,	938},
+	{"cvmx_endor_adma_module_status",	CVMX_CSR_DB_TYPE_NCB,	32,	357,	4,	941},
+	{"cvmx_endor_intc_cntl_hi#"    ,	CVMX_CSR_DB_TYPE_NCB,	32,	358,	2,	945},
+	{"cvmx_endor_intc_cntl_lo#"    ,	CVMX_CSR_DB_TYPE_NCB,	32,	360,	2,	947},
+	{"cvmx_endor_intc_index_hi#"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	362,	2,	949},
+	{"cvmx_endor_intc_index_lo#"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	364,	2,	951},
+	{"cvmx_endor_intc_misc_idx_hi#",	CVMX_CSR_DB_TYPE_NCB,	32,	366,	2,	953},
+	{"cvmx_endor_intc_misc_idx_lo#",	CVMX_CSR_DB_TYPE_NCB,	32,	368,	2,	955},
+	{"cvmx_endor_intc_misc_mask_hi#",	CVMX_CSR_DB_TYPE_NCB,	32,	370,	25,	957},
+	{"cvmx_endor_intc_misc_mask_lo#",	CVMX_CSR_DB_TYPE_NCB,	32,	372,	25,	982},
+	{"cvmx_endor_intc_misc_rint"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	374,	25,	1007},
+	{"cvmx_endor_intc_misc_status_hi#",	CVMX_CSR_DB_TYPE_NCB,	32,	375,	25,	1032},
+	{"cvmx_endor_intc_misc_status_lo#",	CVMX_CSR_DB_TYPE_NCB,	32,	377,	25,	1057},
+	{"cvmx_endor_intc_rd_idx_hi#"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	379,	2,	1082},
+	{"cvmx_endor_intc_rd_idx_lo#"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	381,	2,	1084},
+	{"cvmx_endor_intc_rd_mask_hi#" ,	CVMX_CSR_DB_TYPE_NCB,	32,	383,	25,	1086},
+	{"cvmx_endor_intc_rd_mask_lo#" ,	CVMX_CSR_DB_TYPE_NCB,	32,	385,	25,	1111},
+	{"cvmx_endor_intc_rd_rint"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	387,	25,	1136},
+	{"cvmx_endor_intc_rd_status_hi#",	CVMX_CSR_DB_TYPE_NCB,	32,	388,	25,	1161},
+	{"cvmx_endor_intc_rd_status_lo#",	CVMX_CSR_DB_TYPE_NCB,	32,	390,	25,	1186},
+	{"cvmx_endor_intc_rdq_idx_hi#" ,	CVMX_CSR_DB_TYPE_NCB,	32,	392,	2,	1211},
+	{"cvmx_endor_intc_rdq_idx_lo#" ,	CVMX_CSR_DB_TYPE_NCB,	32,	394,	2,	1213},
+	{"cvmx_endor_intc_rdq_mask_hi#",	CVMX_CSR_DB_TYPE_NCB,	32,	396,	25,	1215},
+	{"cvmx_endor_intc_rdq_mask_lo#",	CVMX_CSR_DB_TYPE_NCB,	32,	398,	25,	1240},
+	{"cvmx_endor_intc_rdq_rint"    ,	CVMX_CSR_DB_TYPE_NCB,	32,	400,	25,	1265},
+	{"cvmx_endor_intc_rdq_status_hi#",	CVMX_CSR_DB_TYPE_NCB,	32,	401,	25,	1290},
+	{"cvmx_endor_intc_rdq_status_lo#",	CVMX_CSR_DB_TYPE_NCB,	32,	403,	25,	1315},
+	{"cvmx_endor_intc_stat_hi#"    ,	CVMX_CSR_DB_TYPE_NCB,	32,	405,	7,	1340},
+	{"cvmx_endor_intc_stat_lo#"    ,	CVMX_CSR_DB_TYPE_NCB,	32,	407,	7,	1347},
+	{"cvmx_endor_intc_sw_idx_hi#"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	409,	2,	1354},
+	{"cvmx_endor_intc_sw_idx_lo#"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	411,	2,	1356},
+	{"cvmx_endor_intc_sw_mask_hi#" ,	CVMX_CSR_DB_TYPE_NCB,	32,	413,	1,	1358},
+	{"cvmx_endor_intc_sw_mask_lo#" ,	CVMX_CSR_DB_TYPE_NCB,	32,	415,	1,	1359},
+	{"cvmx_endor_intc_sw_rint"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	417,	1,	1360},
+	{"cvmx_endor_intc_sw_status_hi#",	CVMX_CSR_DB_TYPE_NCB,	32,	418,	1,	1361},
+	{"cvmx_endor_intc_sw_status_lo#",	CVMX_CSR_DB_TYPE_NCB,	32,	420,	1,	1362},
+	{"cvmx_endor_intc_swclr"       ,	CVMX_CSR_DB_TYPE_NCB,	32,	422,	1,	1363},
+	{"cvmx_endor_intc_swset"       ,	CVMX_CSR_DB_TYPE_NCB,	32,	423,	1,	1364},
+	{"cvmx_endor_intc_wr_idx_hi#"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	424,	2,	1365},
+	{"cvmx_endor_intc_wr_idx_lo#"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	426,	2,	1367},
+	{"cvmx_endor_intc_wr_mask_hi#" ,	CVMX_CSR_DB_TYPE_NCB,	32,	428,	30,	1369},
+	{"cvmx_endor_intc_wr_mask_lo#" ,	CVMX_CSR_DB_TYPE_NCB,	32,	430,	30,	1399},
+	{"cvmx_endor_intc_wr_rint"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	432,	30,	1429},
+	{"cvmx_endor_intc_wr_status_hi#",	CVMX_CSR_DB_TYPE_NCB,	32,	433,	30,	1459},
+	{"cvmx_endor_intc_wr_status_lo#",	CVMX_CSR_DB_TYPE_NCB,	32,	435,	30,	1489},
+	{"cvmx_endor_intc_wrq_idx_hi#" ,	CVMX_CSR_DB_TYPE_NCB,	32,	437,	2,	1519},
+	{"cvmx_endor_intc_wrq_idx_lo#" ,	CVMX_CSR_DB_TYPE_NCB,	32,	439,	2,	1521},
+	{"cvmx_endor_intc_wrq_mask_hi#",	CVMX_CSR_DB_TYPE_NCB,	32,	441,	24,	1523},
+	{"cvmx_endor_intc_wrq_mask_lo#",	CVMX_CSR_DB_TYPE_NCB,	32,	443,	24,	1547},
+	{"cvmx_endor_intc_wrq_rint"    ,	CVMX_CSR_DB_TYPE_NCB,	32,	445,	24,	1571},
+	{"cvmx_endor_intc_wrq_status_hi#",	CVMX_CSR_DB_TYPE_NCB,	32,	446,	24,	1595},
+	{"cvmx_endor_intc_wrq_status_lo#",	CVMX_CSR_DB_TYPE_NCB,	32,	448,	24,	1619},
+	{"cvmx_endor_ofs_hmm_cbuf_end_addr0",	CVMX_CSR_DB_TYPE_NCB,	32,	450,	2,	1643},
+	{"cvmx_endor_ofs_hmm_cbuf_end_addr1",	CVMX_CSR_DB_TYPE_NCB,	32,	451,	2,	1645},
+	{"cvmx_endor_ofs_hmm_cbuf_end_addr2",	CVMX_CSR_DB_TYPE_NCB,	32,	452,	2,	1647},
+	{"cvmx_endor_ofs_hmm_cbuf_end_addr3",	CVMX_CSR_DB_TYPE_NCB,	32,	453,	2,	1649},
+	{"cvmx_endor_ofs_hmm_cbuf_start_addr0",	CVMX_CSR_DB_TYPE_NCB,	32,	454,	2,	1651},
+	{"cvmx_endor_ofs_hmm_cbuf_start_addr1",	CVMX_CSR_DB_TYPE_NCB,	32,	455,	2,	1653},
+	{"cvmx_endor_ofs_hmm_cbuf_start_addr2",	CVMX_CSR_DB_TYPE_NCB,	32,	456,	2,	1655},
+	{"cvmx_endor_ofs_hmm_cbuf_start_addr3",	CVMX_CSR_DB_TYPE_NCB,	32,	457,	2,	1657},
+	{"cvmx_endor_ofs_hmm_intr_clear",	CVMX_CSR_DB_TYPE_NCB,	32,	458,	3,	1659},
+	{"cvmx_endor_ofs_hmm_intr_enb" ,	CVMX_CSR_DB_TYPE_NCB,	32,	459,	3,	1662},
+	{"cvmx_endor_ofs_hmm_intr_rstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	460,	3,	1665},
+	{"cvmx_endor_ofs_hmm_intr_status",	CVMX_CSR_DB_TYPE_NCB,	32,	461,	3,	1668},
+	{"cvmx_endor_ofs_hmm_intr_test",	CVMX_CSR_DB_TYPE_NCB,	32,	462,	3,	1671},
+	{"cvmx_endor_ofs_hmm_mode"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	463,	5,	1674},
+	{"cvmx_endor_ofs_hmm_start_addr0",	CVMX_CSR_DB_TYPE_NCB,	32,	464,	2,	1679},
+	{"cvmx_endor_ofs_hmm_start_addr1",	CVMX_CSR_DB_TYPE_NCB,	32,	465,	2,	1681},
+	{"cvmx_endor_ofs_hmm_start_addr2",	CVMX_CSR_DB_TYPE_NCB,	32,	466,	2,	1683},
+	{"cvmx_endor_ofs_hmm_start_addr3",	CVMX_CSR_DB_TYPE_NCB,	32,	467,	2,	1685},
+	{"cvmx_endor_ofs_hmm_status"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	468,	1,	1687},
+	{"cvmx_endor_ofs_hmm_xfer_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	32,	469,	5,	1688},
+	{"cvmx_endor_ofs_hmm_xfer_q_status",	CVMX_CSR_DB_TYPE_NCB,	32,	470,	1,	1693},
+	{"cvmx_endor_ofs_hmm_xfer_start",	CVMX_CSR_DB_TYPE_NCB,	32,	471,	2,	1694},
+	{"cvmx_endor_rfif_1pps_gen_cfg",	CVMX_CSR_DB_TYPE_NCB,	32,	472,	2,	1696},
+	{"cvmx_endor_rfif_1pps_sample_cnt_offset",	CVMX_CSR_DB_TYPE_NCB,	32,	473,	2,	1698},
+	{"cvmx_endor_rfif_1pps_verif_gen_en",	CVMX_CSR_DB_TYPE_NCB,	32,	474,	2,	1700},
+	{"cvmx_endor_rfif_1pps_verif_scnt",	CVMX_CSR_DB_TYPE_NCB,	32,	475,	2,	1702},
+	{"cvmx_endor_rfif_conf"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	476,	19,	1704},
+	{"cvmx_endor_rfif_conf2"       ,	CVMX_CSR_DB_TYPE_NCB,	32,	477,	4,	1723},
+	{"cvmx_endor_rfif_dsp1_gpio"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	478,	2,	1727},
+	{"cvmx_endor_rfif_dsp_rx_his"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	479,	1,	1729},
+	{"cvmx_endor_rfif_dsp_rx_ism"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	480,	3,	1730},
+	{"cvmx_endor_rfif_firs_enable" ,	CVMX_CSR_DB_TYPE_NCB,	32,	481,	5,	1733},
+	{"cvmx_endor_rfif_frame_cnt"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	482,	2,	1738},
+	{"cvmx_endor_rfif_frame_l"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	483,	2,	1740},
+	{"cvmx_endor_rfif_gpio_#"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	484,	4,	1742},
+	{"cvmx_endor_rfif_max_sample_adj",	CVMX_CSR_DB_TYPE_NCB,	32,	488,	2,	1746},
+	{"cvmx_endor_rfif_min_sample_adj",	CVMX_CSR_DB_TYPE_NCB,	32,	489,	2,	1748},
+	{"cvmx_endor_rfif_num_rx_win"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	490,	2,	1750},
+	{"cvmx_endor_rfif_pwm_enable"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	491,	2,	1752},
+	{"cvmx_endor_rfif_pwm_high_time",	CVMX_CSR_DB_TYPE_NCB,	32,	492,	2,	1754},
+	{"cvmx_endor_rfif_pwm_low_time",	CVMX_CSR_DB_TYPE_NCB,	32,	493,	2,	1756},
+	{"cvmx_endor_rfif_rd_timer64_lsb",	CVMX_CSR_DB_TYPE_NCB,	32,	494,	1,	1758},
+	{"cvmx_endor_rfif_rd_timer64_msb",	CVMX_CSR_DB_TYPE_NCB,	32,	495,	1,	1759},
+	{"cvmx_endor_rfif_real_time_timer",	CVMX_CSR_DB_TYPE_NCB,	32,	496,	1,	1760},
+	{"cvmx_endor_rfif_rf_clk_timer",	CVMX_CSR_DB_TYPE_NCB,	32,	497,	1,	1761},
+	{"cvmx_endor_rfif_rf_clk_timer_en",	CVMX_CSR_DB_TYPE_NCB,	32,	498,	2,	1762},
+	{"cvmx_endor_rfif_rx_correct_adj",	CVMX_CSR_DB_TYPE_NCB,	32,	499,	2,	1764},
+	{"cvmx_endor_rfif_rx_div_status",	CVMX_CSR_DB_TYPE_NCB,	32,	500,	11,	1766},
+	{"cvmx_endor_rfif_rx_fifo_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	32,	501,	2,	1777},
+	{"cvmx_endor_rfif_rx_if_cfg"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	502,	4,	1779},
+	{"cvmx_endor_rfif_rx_lead_lag" ,	CVMX_CSR_DB_TYPE_NCB,	32,	503,	3,	1783},
+	{"cvmx_endor_rfif_rx_load_cfg" ,	CVMX_CSR_DB_TYPE_NCB,	32,	504,	8,	1786},
+	{"cvmx_endor_rfif_rx_offset"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	505,	2,	1794},
+	{"cvmx_endor_rfif_rx_offset_adj_scnt",	CVMX_CSR_DB_TYPE_NCB,	32,	506,	2,	1796},
+	{"cvmx_endor_rfif_rx_status"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	507,	11,	1798},
+	{"cvmx_endor_rfif_rx_sync_scnt",	CVMX_CSR_DB_TYPE_NCB,	32,	508,	2,	1809},
+	{"cvmx_endor_rfif_rx_sync_value",	CVMX_CSR_DB_TYPE_NCB,	32,	509,	2,	1811},
+	{"cvmx_endor_rfif_rx_th"       ,	CVMX_CSR_DB_TYPE_NCB,	32,	510,	2,	1813},
+	{"cvmx_endor_rfif_rx_transfer_size",	CVMX_CSR_DB_TYPE_NCB,	32,	511,	2,	1815},
+	{"cvmx_endor_rfif_rx_w_e#"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	512,	2,	1817},
+	{"cvmx_endor_rfif_rx_w_s#"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	516,	2,	1819},
+	{"cvmx_endor_rfif_sample_adj_cfg",	CVMX_CSR_DB_TYPE_NCB,	32,	520,	2,	1821},
+	{"cvmx_endor_rfif_sample_adj_error",	CVMX_CSR_DB_TYPE_NCB,	32,	521,	1,	1823},
+	{"cvmx_endor_rfif_sample_cnt"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	522,	2,	1824},
+	{"cvmx_endor_rfif_skip_frm_cnt_bits",	CVMX_CSR_DB_TYPE_NCB,	32,	523,	2,	1826},
+	{"cvmx_endor_rfif_spi_#_ll"    ,	CVMX_CSR_DB_TYPE_NCB,	32,	524,	2,	1828},
+	{"cvmx_endor_rfif_spi_cmd_attr#",	CVMX_CSR_DB_TYPE_NCB,	32,	528,	5,	1830},
+	{"cvmx_endor_rfif_spi_cmds#"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	592,	2,	1835},
+	{"cvmx_endor_rfif_spi_conf0"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	656,	5,	1837},
+	{"cvmx_endor_rfif_spi_conf1"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	657,	5,	1842},
+	{"cvmx_endor_rfif_spi_ctrl"    ,	CVMX_CSR_DB_TYPE_NCB,	32,	658,	1,	1847},
+	{"cvmx_endor_rfif_spi_din#"    ,	CVMX_CSR_DB_TYPE_NCB,	32,	659,	2,	1848},
+	{"cvmx_endor_rfif_spi_rx_data" ,	CVMX_CSR_DB_TYPE_NCB,	32,	723,	1,	1850},
+	{"cvmx_endor_rfif_spi_status"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	724,	4,	1851},
+	{"cvmx_endor_rfif_spi_tx_data" ,	CVMX_CSR_DB_TYPE_NCB,	32,	725,	5,	1855},
+	{"cvmx_endor_rfif_timer64_cfg" ,	CVMX_CSR_DB_TYPE_NCB,	32,	726,	2,	1860},
+	{"cvmx_endor_rfif_timer64_en"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	727,	2,	1862},
+	{"cvmx_endor_rfif_tti_scnt_int#",	CVMX_CSR_DB_TYPE_NCB,	32,	728,	2,	1864},
+	{"cvmx_endor_rfif_tti_scnt_int_clr",	CVMX_CSR_DB_TYPE_NCB,	32,	736,	2,	1866},
+	{"cvmx_endor_rfif_tti_scnt_int_en",	CVMX_CSR_DB_TYPE_NCB,	32,	737,	2,	1868},
+	{"cvmx_endor_rfif_tti_scnt_int_map",	CVMX_CSR_DB_TYPE_NCB,	32,	738,	2,	1870},
+	{"cvmx_endor_rfif_tti_scnt_int_stat",	CVMX_CSR_DB_TYPE_NCB,	32,	739,	2,	1872},
+	{"cvmx_endor_rfif_tx_div_status",	CVMX_CSR_DB_TYPE_NCB,	32,	740,	11,	1874},
+	{"cvmx_endor_rfif_tx_if_cfg"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	741,	4,	1885},
+	{"cvmx_endor_rfif_tx_lead_lag" ,	CVMX_CSR_DB_TYPE_NCB,	32,	742,	3,	1889},
+	{"cvmx_endor_rfif_tx_offset"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	743,	2,	1892},
+	{"cvmx_endor_rfif_tx_offset_adj_scnt",	CVMX_CSR_DB_TYPE_NCB,	32,	744,	2,	1894},
+	{"cvmx_endor_rfif_tx_status"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	745,	11,	1896},
+	{"cvmx_endor_rfif_tx_th"       ,	CVMX_CSR_DB_TYPE_NCB,	32,	746,	2,	1907},
+	{"cvmx_endor_rfif_win_en"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	747,	2,	1909},
+	{"cvmx_endor_rfif_win_upd_scnt",	CVMX_CSR_DB_TYPE_NCB,	32,	748,	2,	1911},
+	{"cvmx_endor_rfif_wr_timer64_lsb",	CVMX_CSR_DB_TYPE_NCB,	32,	749,	1,	1913},
+	{"cvmx_endor_rfif_wr_timer64_msb",	CVMX_CSR_DB_TYPE_NCB,	32,	750,	1,	1914},
+	{"cvmx_endor_rstclk_clkenb0_clr",	CVMX_CSR_DB_TYPE_NCB,	32,	751,	14,	1915},
+	{"cvmx_endor_rstclk_clkenb0_set",	CVMX_CSR_DB_TYPE_NCB,	32,	752,	14,	1929},
+	{"cvmx_endor_rstclk_clkenb0_state",	CVMX_CSR_DB_TYPE_NCB,	32,	753,	14,	1943},
+	{"cvmx_endor_rstclk_clkenb1_clr",	CVMX_CSR_DB_TYPE_NCB,	32,	754,	8,	1957},
+	{"cvmx_endor_rstclk_clkenb1_set",	CVMX_CSR_DB_TYPE_NCB,	32,	755,	8,	1965},
+	{"cvmx_endor_rstclk_clkenb1_state",	CVMX_CSR_DB_TYPE_NCB,	32,	756,	8,	1973},
+	{"cvmx_endor_rstclk_dspstall_clr",	CVMX_CSR_DB_TYPE_NCB,	32,	757,	7,	1981},
+	{"cvmx_endor_rstclk_dspstall_set",	CVMX_CSR_DB_TYPE_NCB,	32,	758,	7,	1988},
+	{"cvmx_endor_rstclk_dspstall_state",	CVMX_CSR_DB_TYPE_NCB,	32,	759,	7,	1995},
+	{"cvmx_endor_rstclk_intr0_clrmask",	CVMX_CSR_DB_TYPE_NCB,	32,	760,	2,	2002},
+	{"cvmx_endor_rstclk_intr0_mask",	CVMX_CSR_DB_TYPE_NCB,	32,	761,	2,	2004},
+	{"cvmx_endor_rstclk_intr0_setmask",	CVMX_CSR_DB_TYPE_NCB,	32,	762,	2,	2006},
+	{"cvmx_endor_rstclk_intr0_status",	CVMX_CSR_DB_TYPE_NCB,	32,	763,	1,	2008},
+	{"cvmx_endor_rstclk_intr1_clrmask",	CVMX_CSR_DB_TYPE_NCB,	32,	764,	1,	2009},
+	{"cvmx_endor_rstclk_intr1_mask",	CVMX_CSR_DB_TYPE_NCB,	32,	765,	1,	2010},
+	{"cvmx_endor_rstclk_intr1_setmask",	CVMX_CSR_DB_TYPE_NCB,	32,	766,	1,	2011},
+	{"cvmx_endor_rstclk_intr1_status",	CVMX_CSR_DB_TYPE_NCB,	32,	767,	1,	2012},
+	{"cvmx_endor_rstclk_phy_config",	CVMX_CSR_DB_TYPE_NCB,	32,	768,	7,	2013},
+	{"cvmx_endor_rstclk_proc_mon"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	769,	3,	2020},
+	{"cvmx_endor_rstclk_proc_mon_count",	CVMX_CSR_DB_TYPE_NCB,	32,	770,	2,	2023},
+	{"cvmx_endor_rstclk_reset0_clr",	CVMX_CSR_DB_TYPE_NCB,	32,	771,	14,	2025},
+	{"cvmx_endor_rstclk_reset0_set",	CVMX_CSR_DB_TYPE_NCB,	32,	772,	14,	2039},
+	{"cvmx_endor_rstclk_reset0_state",	CVMX_CSR_DB_TYPE_NCB,	32,	773,	14,	2053},
+	{"cvmx_endor_rstclk_reset1_clr",	CVMX_CSR_DB_TYPE_NCB,	32,	774,	8,	2067},
+	{"cvmx_endor_rstclk_reset1_set",	CVMX_CSR_DB_TYPE_NCB,	32,	775,	8,	2075},
+	{"cvmx_endor_rstclk_reset1_state",	CVMX_CSR_DB_TYPE_NCB,	32,	776,	8,	2083},
+	{"cvmx_endor_rstclk_sw_intr_clr",	CVMX_CSR_DB_TYPE_NCB,	32,	777,	2,	2091},
+	{"cvmx_endor_rstclk_sw_intr_set",	CVMX_CSR_DB_TYPE_NCB,	32,	778,	2,	2093},
+	{"cvmx_endor_rstclk_sw_intr_status",	CVMX_CSR_DB_TYPE_NCB,	32,	779,	2,	2095},
+	{"cvmx_endor_rstclk_time#_thrd",	CVMX_CSR_DB_TYPE_NCB,	32,	780,	2,	2097},
+	{"cvmx_endor_rstclk_timer_ctl" ,	CVMX_CSR_DB_TYPE_NCB,	32,	788,	6,	2099},
+	{"cvmx_endor_rstclk_timer_intr_clr",	CVMX_CSR_DB_TYPE_NCB,	32,	789,	2,	2105},
+	{"cvmx_endor_rstclk_timer_intr_status",	CVMX_CSR_DB_TYPE_NCB,	32,	790,	2,	2107},
+	{"cvmx_endor_rstclk_timer_max" ,	CVMX_CSR_DB_TYPE_NCB,	32,	791,	1,	2109},
+	{"cvmx_endor_rstclk_timer_value",	CVMX_CSR_DB_TYPE_NCB,	32,	792,	1,	2110},
+	{"cvmx_endor_rstclk_version"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	793,	3,	2111},
+	{"cvmx_eoi_bist_ctl_sta"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	794,	7,	2114},
+	{"cvmx_eoi_ctl_sta"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	795,	7,	2121},
+	{"cvmx_eoi_def_sta0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	796,	4,	2128},
+	{"cvmx_eoi_def_sta1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	797,	4,	2132},
+	{"cvmx_eoi_def_sta2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	798,	4,	2136},
+	{"cvmx_eoi_ecc_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	799,	3,	2140},
+	{"cvmx_eoi_endor_bistr_ctl_sta",	CVMX_CSR_DB_TYPE_RSL,	64,	800,	7,	2143},
+	{"cvmx_eoi_endor_clk_ctl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	801,	12,	2150},
+	{"cvmx_eoi_endor_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	802,	9,	2162},
+	{"cvmx_eoi_int_ena"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	803,	3,	2171},
+	{"cvmx_eoi_int_sta"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	804,	3,	2174},
+	{"cvmx_eoi_io_drv"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	805,	5,	2177},
+	{"cvmx_eoi_throttle_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	806,	6,	2182},
+	{"cvmx_fpa_addr_range_error"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	807,	3,	2188},
+	{"cvmx_fpa_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	808,	6,	2191},
+	{"cvmx_fpa_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	809,	10,	2197},
+	{"cvmx_fpa_fpf#_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	810,	3,	2207},
+	{"cvmx_fpa_fpf#_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	817,	2,	2210},
+	{"cvmx_fpa_fpf0_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	824,	3,	2212},
+	{"cvmx_fpa_fpf0_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	825,	2,	2215},
+	{"cvmx_fpa_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	826,	47,	2217},
+	{"cvmx_fpa_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	827,	47,	2264},
+	{"cvmx_fpa_packet_threshold"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	828,	2,	2311},
+	{"cvmx_fpa_pool#_end_addr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	829,	2,	2313},
+	{"cvmx_fpa_pool#_start_addr"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	837,	2,	2315},
+	{"cvmx_fpa_pool#_threshold"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	845,	2,	2317},
+	{"cvmx_fpa_que#_available"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	853,	2,	2319},
+	{"cvmx_fpa_que#_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	861,	2,	2321},
+	{"cvmx_fpa_que_act"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	869,	3,	2323},
+	{"cvmx_fpa_que_exp"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	870,	3,	2326},
+	{"cvmx_fpa_wqe_threshold"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	871,	2,	2329},
+	{"cvmx_gmx#_bad_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	872,	7,	2331},
+	{"cvmx_gmx#_bist"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	873,	2,	2338},
+	{"cvmx_gmx#_clk_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	874,	2,	2340},
+	{"cvmx_gmx#_hg2_control"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	875,	5,	2342},
+	{"cvmx_gmx#_inf_mode"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	876,	7,	2347},
+	{"cvmx_gmx#_nxa_adr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	877,	2,	2354},
+	{"cvmx_gmx#_prt#_cbfc_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	878,	8,	2356},
+	{"cvmx_gmx#_prt#_cfg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	879,	10,	2364},
+	{"cvmx_gmx#_rx#_adr_cam0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	881,	1,	2374},
+	{"cvmx_gmx#_rx#_adr_cam1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	885,	1,	2375},
+	{"cvmx_gmx#_rx#_adr_cam2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	889,	1,	2376},
+	{"cvmx_gmx#_rx#_adr_cam3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	893,	1,	2377},
+	{"cvmx_gmx#_rx#_adr_cam4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	897,	1,	2378},
+	{"cvmx_gmx#_rx#_adr_cam5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	901,	1,	2379},
+	{"cvmx_gmx#_rx#_adr_cam_all_en",	CVMX_CSR_DB_TYPE_RSL,	64,	905,	2,	2380},
+	{"cvmx_gmx#_rx#_adr_cam_en"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	907,	2,	2382},
+	{"cvmx_gmx#_rx#_adr_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	909,	4,	2384},
+	{"cvmx_gmx#_rx#_decision"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	911,	2,	2388},
+	{"cvmx_gmx#_rx#_frm_chk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	913,	9,	2390},
+	{"cvmx_gmx#_rx#_frm_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	915,	13,	2399},
+	{"cvmx_gmx#_rx#_ifg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	917,	2,	2412},
+	{"cvmx_gmx#_rx#_int_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	919,	27,	2414},
+	{"cvmx_gmx#_rx#_int_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	921,	27,	2441},
+	{"cvmx_gmx#_rx#_jabber"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	923,	2,	2468},
+	{"cvmx_gmx#_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	925,	2,	2470},
+	{"cvmx_gmx#_rx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	927,	2,	2472},
+	{"cvmx_gmx#_rx#_stats_octs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	929,	2,	2474},
+	{"cvmx_gmx#_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	931,	2,	2476},
+	{"cvmx_gmx#_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	933,	2,	2478},
+	{"cvmx_gmx#_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	935,	2,	2480},
+	{"cvmx_gmx#_rx#_stats_pkts"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	937,	2,	2482},
+	{"cvmx_gmx#_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	939,	2,	2484},
+	{"cvmx_gmx#_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	941,	2,	2486},
+	{"cvmx_gmx#_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	943,	2,	2488},
+	{"cvmx_gmx#_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	945,	2,	2490},
+	{"cvmx_gmx#_rx#_udd_skp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	947,	4,	2492},
+	{"cvmx_gmx#_rx_bp_drop#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	949,	2,	2496},
+	{"cvmx_gmx#_rx_bp_off#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	951,	2,	2498},
+	{"cvmx_gmx#_rx_bp_on#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	953,	2,	2500},
+	{"cvmx_gmx#_rx_hg2_status"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	955,	4,	2502},
+	{"cvmx_gmx#_rx_prt_info"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	956,	4,	2506},
+	{"cvmx_gmx#_rx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	957,	2,	2510},
+	{"cvmx_gmx#_rx_xaui_bad_col"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	958,	5,	2512},
+	{"cvmx_gmx#_rx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	959,	2,	2517},
+	{"cvmx_gmx#_smac#"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	960,	2,	2519},
+	{"cvmx_gmx#_stat_bp"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	962,	3,	2521},
+	{"cvmx_gmx#_tb_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	963,	2,	2524},
+	{"cvmx_gmx#_tx#_append"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	964,	5,	2526},
+	{"cvmx_gmx#_tx#_burst"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	966,	2,	2531},
+	{"cvmx_gmx#_tx#_cbfc_xoff"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	968,	2,	2533},
+	{"cvmx_gmx#_tx#_cbfc_xon"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	969,	2,	2535},
+	{"cvmx_gmx#_tx#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	970,	3,	2537},
+	{"cvmx_gmx#_tx#_min_pkt"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	972,	2,	2540},
+	{"cvmx_gmx#_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	974,	2,	2542},
+	{"cvmx_gmx#_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	976,	2,	2544},
+	{"cvmx_gmx#_tx#_pause_togo"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	978,	3,	2546},
+	{"cvmx_gmx#_tx#_pause_zero"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	980,	2,	2549},
+	{"cvmx_gmx#_tx#_sgmii_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	982,	2,	2551},
+	{"cvmx_gmx#_tx#_slot"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	984,	2,	2553},
+	{"cvmx_gmx#_tx#_soft_pause"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	986,	2,	2555},
+	{"cvmx_gmx#_tx#_stat0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	988,	2,	2557},
+	{"cvmx_gmx#_tx#_stat1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	990,	2,	2559},
+	{"cvmx_gmx#_tx#_stat2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	992,	2,	2561},
+	{"cvmx_gmx#_tx#_stat3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	994,	2,	2563},
+	{"cvmx_gmx#_tx#_stat4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	996,	2,	2565},
+	{"cvmx_gmx#_tx#_stat5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	998,	2,	2567},
+	{"cvmx_gmx#_tx#_stat6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1000,	2,	2569},
+	{"cvmx_gmx#_tx#_stat7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1002,	2,	2571},
+	{"cvmx_gmx#_tx#_stat8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1004,	2,	2573},
+	{"cvmx_gmx#_tx#_stat9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1006,	2,	2575},
+	{"cvmx_gmx#_tx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1008,	2,	2577},
+	{"cvmx_gmx#_tx#_thresh"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1010,	2,	2579},
+	{"cvmx_gmx#_tx_bp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1012,	2,	2581},
+	{"cvmx_gmx#_tx_col_attempt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1013,	2,	2583},
+	{"cvmx_gmx#_tx_corrupt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1014,	2,	2585},
+	{"cvmx_gmx#_tx_hg2_reg1"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1015,	2,	2587},
+	{"cvmx_gmx#_tx_hg2_reg2"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1016,	2,	2589},
+	{"cvmx_gmx#_tx_ifg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1017,	3,	2591},
+	{"cvmx_gmx#_tx_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1018,	14,	2594},
+	{"cvmx_gmx#_tx_int_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1019,	14,	2608},
+	{"cvmx_gmx#_tx_jam"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1020,	2,	2622},
+	{"cvmx_gmx#_tx_lfsr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1021,	2,	2624},
+	{"cvmx_gmx#_tx_ovr_bp"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1022,	8,	2626},
+	{"cvmx_gmx#_tx_pause_pkt_dmac" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1023,	2,	2634},
+	{"cvmx_gmx#_tx_pause_pkt_type" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1024,	2,	2636},
+	{"cvmx_gmx#_tx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1025,	2,	2638},
+	{"cvmx_gmx#_tx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1026,	9,	2640},
+	{"cvmx_gmx#_xaui_ext_loopback" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1027,	3,	2649},
+	{"cvmx_gpio_bit_cfg#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1028,	10,	2652},
+	{"cvmx_gpio_clk_gen#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1044,	2,	2662},
+	{"cvmx_gpio_clk_qlm#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1048,	5,	2664},
+	{"cvmx_gpio_int_clr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1050,	2,	2669},
+	{"cvmx_gpio_multi_cast"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1051,	2,	2671},
+	{"cvmx_gpio_rx_dat"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1052,	2,	2673},
+	{"cvmx_gpio_tx_clr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1053,	2,	2675},
+	{"cvmx_gpio_tx_set"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1054,	2,	2677},
+	{"cvmx_gpio_xbit_cfg#"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1055,	10,	2679},
+	{"cvmx_iob_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1059,	24,	2689},
+	{"cvmx_iob_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1060,	9,	2713},
+	{"cvmx_iob_dwb_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1061,	3,	2722},
+	{"cvmx_iob_fau_timeout"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1062,	3,	2725},
+	{"cvmx_iob_i2c_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1063,	3,	2728},
+	{"cvmx_iob_inb_control_match"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1064,	5,	2731},
+	{"cvmx_iob_inb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	1065,	5,	2736},
+	{"cvmx_iob_inb_data_match"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1066,	1,	2741},
+	{"cvmx_iob_inb_data_match_enb" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1067,	1,	2742},
+	{"cvmx_iob_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1068,	7,	2743},
+	{"cvmx_iob_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1069,	7,	2750},
+	{"cvmx_iob_n2c_l2c_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1070,	3,	2757},
+	{"cvmx_iob_n2c_rsp_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1071,	3,	2760},
+	{"cvmx_iob_outb_com_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1072,	3,	2763},
+	{"cvmx_iob_outb_control_match" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1073,	5,	2766},
+	{"cvmx_iob_outb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	1074,	5,	2771},
+	{"cvmx_iob_outb_data_match"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1075,	1,	2776},
+	{"cvmx_iob_outb_data_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	1076,	1,	2777},
+	{"cvmx_iob_outb_fpa_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1077,	3,	2778},
+	{"cvmx_iob_outb_req_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1078,	3,	2781},
+	{"cvmx_iob_p2c_req_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1079,	3,	2784},
+	{"cvmx_iob_pkt_err"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1080,	3,	2787},
+	{"cvmx_iob_to_cmb_credits"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1081,	4,	2790},
+	{"cvmx_ipd_1st_mbuff_skip"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1082,	2,	2794},
+	{"cvmx_ipd_1st_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1083,	2,	2796},
+	{"cvmx_ipd_2nd_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1084,	2,	2798},
+	{"cvmx_ipd_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1085,	19,	2800},
+	{"cvmx_ipd_bp_prt_red_end"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1086,	2,	2819},
+	{"cvmx_ipd_clk_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1087,	1,	2821},
+	{"cvmx_ipd_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1088,	18,	2822},
+	{"cvmx_ipd_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1089,	13,	2840},
+	{"cvmx_ipd_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1090,	13,	2853},
+	{"cvmx_ipd_not_1st_mbuff_skip" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1091,	2,	2866},
+	{"cvmx_ipd_packet_mbuff_size"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1092,	2,	2868},
+	{"cvmx_ipd_pkt_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1093,	2,	2870},
+	{"cvmx_ipd_port#_bp_page_cnt"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1094,	3,	2872},
+	{"cvmx_ipd_port#_bp_page_cnt2" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1106,	3,	2875},
+	{"cvmx_ipd_port#_bp_page_cnt3" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1110,	3,	2878},
+	{"cvmx_ipd_port_bp_counters2_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	1118,	2,	2881},
+	{"cvmx_ipd_port_bp_counters3_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	1122,	2,	2883},
+	{"cvmx_ipd_port_bp_counters4_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	1126,	2,	2885},
+	{"cvmx_ipd_port_bp_counters_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	1130,	2,	2887},
+	{"cvmx_ipd_port_qos_#_cnt"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1142,	2,	2889},
+	{"cvmx_ipd_port_qos_int#"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1334,	1,	2891},
+	{"cvmx_ipd_port_qos_int_enb#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1338,	1,	2892},
+	{"cvmx_ipd_prc_hold_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	1342,	6,	2893},
+	{"cvmx_ipd_prc_port_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	1343,	5,	2899},
+	{"cvmx_ipd_ptr_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1344,	6,	2904},
+	{"cvmx_ipd_pwp_ptr_fifo_ctl"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1345,	7,	2910},
+	{"cvmx_ipd_qos#_red_marks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1346,	2,	2917},
+	{"cvmx_ipd_que0_free_page_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1354,	2,	2919},
+	{"cvmx_ipd_red_port_enable"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1355,	3,	2921},
+	{"cvmx_ipd_red_port_enable2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1356,	2,	2924},
+	{"cvmx_ipd_red_que#_param"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1357,	5,	2926},
+	{"cvmx_ipd_sub_port_bp_page_cnt",	CVMX_CSR_DB_TYPE_NCB,	64,	1365,	3,	2931},
+	{"cvmx_ipd_sub_port_fcs"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1366,	4,	2934},
+	{"cvmx_ipd_sub_port_qos_cnt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1367,	3,	2938},
+	{"cvmx_ipd_wqe_fpa_queue"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1368,	2,	2941},
+	{"cvmx_ipd_wqe_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1369,	2,	2943},
+	{"cvmx_key_bist_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1370,	4,	2945},
+	{"cvmx_key_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1371,	3,	2949},
+	{"cvmx_key_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1372,	5,	2952},
+	{"cvmx_key_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1373,	5,	2957},
+	{"cvmx_l2c_big_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1374,	4,	2962},
+	{"cvmx_l2c_bst"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1375,	12,	2966},
+	{"cvmx_l2c_bst_mem#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1376,	5,	2978},
+	{"cvmx_l2c_bst_tdt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1377,	5,	2983},
+	{"cvmx_l2c_bst_ttg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1378,	3,	2988},
+	{"cvmx_l2c_cop0_map#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1379,	1,	2991},
+	{"cvmx_l2c_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2659,	15,	2992},
+	{"cvmx_l2c_dut_map#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2660,	4,	3007},
+	{"cvmx_l2c_err_tdt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3684,	9,	3011},
+	{"cvmx_l2c_err_ttg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3685,	9,	3020},
+	{"cvmx_l2c_err_vbf#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3686,	6,	3029},
+	{"cvmx_l2c_err_xmc"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	3687,	5,	3035},
+	{"cvmx_l2c_int_ena"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	3688,	9,	3040},
+	{"cvmx_l2c_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	3689,	11,	3049},
+	{"cvmx_l2c_ioc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3690,	1,	3060},
+	{"cvmx_l2c_ior#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3691,	1,	3061},
+	{"cvmx_l2c_qos_iob#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3692,	4,	3062},
+	{"cvmx_l2c_qos_pp#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	3693,	2,	3066},
+	{"cvmx_l2c_qos_wgt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	3697,	5,	3068},
+	{"cvmx_l2c_rsc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3698,	1,	3073},
+	{"cvmx_l2c_rsd#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3699,	1,	3074},
+	{"cvmx_l2c_tad#_ecc0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	3700,	8,	3075},
+	{"cvmx_l2c_tad#_ecc1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	3701,	8,	3083},
+	{"cvmx_l2c_tad#_ien"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3702,	10,	3091},
+	{"cvmx_l2c_tad#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3703,	10,	3101},
+	{"cvmx_l2c_tad#_pfc0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	3704,	1,	3111},
+	{"cvmx_l2c_tad#_pfc1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	3705,	1,	3112},
+	{"cvmx_l2c_tad#_pfc2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	3706,	1,	3113},
+	{"cvmx_l2c_tad#_pfc3"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	3707,	1,	3114},
+	{"cvmx_l2c_tad#_prf"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3708,	5,	3115},
+	{"cvmx_l2c_tad#_tag"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3709,	9,	3120},
+	{"cvmx_l2c_ver_id"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	3710,	1,	3129},
+	{"cvmx_l2c_ver_iob"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	3711,	2,	3130},
+	{"cvmx_l2c_ver_msc"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	3712,	3,	3132},
+	{"cvmx_l2c_ver_pp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	3713,	2,	3135},
+	{"cvmx_l2c_virtid_iob#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	3714,	4,	3137},
+	{"cvmx_l2c_virtid_pp#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	3715,	2,	3141},
+	{"cvmx_l2c_vrt_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	3719,	6,	3143},
+	{"cvmx_l2c_vrt_mem#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3720,	3,	3149},
+	{"cvmx_l2c_wpar_iob#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4744,	2,	3152},
+	{"cvmx_l2c_wpar_pp#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4745,	2,	3154},
+	{"cvmx_l2c_xmc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4749,	1,	3156},
+	{"cvmx_l2c_xmc_cmd"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4750,	4,	3157},
+	{"cvmx_l2c_xmd#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4751,	1,	3161},
+	{"cvmx_lmc#_char_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4752,	7,	3162},
+	{"cvmx_lmc#_char_mask0"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4753,	1,	3169},
+	{"cvmx_lmc#_char_mask1"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4754,	2,	3170},
+	{"cvmx_lmc#_char_mask2"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4755,	1,	3172},
+	{"cvmx_lmc#_char_mask3"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4756,	2,	3173},
+	{"cvmx_lmc#_char_mask4"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4757,	12,	3175},
+	{"cvmx_lmc#_comp_ctl2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4758,	11,	3187},
+	{"cvmx_lmc#_config"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4759,	23,	3198},
+	{"cvmx_lmc#_control"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4760,	21,	3221},
+	{"cvmx_lmc#_dclk_cnt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4761,	1,	3242},
+	{"cvmx_lmc#_ddr_pll_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4762,	11,	3243},
+	{"cvmx_lmc#_dimm#_params"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4763,	16,	3254},
+	{"cvmx_lmc#_dimm_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4765,	5,	3270},
+	{"cvmx_lmc#_dll_ctl2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4766,	7,	3275},
+	{"cvmx_lmc#_dll_ctl3"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4767,	16,	3282},
+	{"cvmx_lmc#_dual_memcfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4768,	4,	3298},
+	{"cvmx_lmc#_ecc_synd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4769,	5,	3302},
+	{"cvmx_lmc#_fadr"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	4770,	6,	3307},
+	{"cvmx_lmc#_ifb_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4771,	1,	3313},
+	{"cvmx_lmc#_int"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	4772,	4,	3314},
+	{"cvmx_lmc#_int_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4773,	4,	3318},
+	{"cvmx_lmc#_modereg_params0"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	4774,	16,	3322},
+	{"cvmx_lmc#_modereg_params1"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	4775,	25,	3338},
+	{"cvmx_lmc#_nxm"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	4776,	10,	3363},
+	{"cvmx_lmc#_ops_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4777,	1,	3373},
+	{"cvmx_lmc#_phy_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4778,	10,	3374},
+	{"cvmx_lmc#_reset_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4779,	5,	3384},
+	{"cvmx_lmc#_rlevel_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4780,	10,	3389},
+	{"cvmx_lmc#_rlevel_dbg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4781,	1,	3399},
+	{"cvmx_lmc#_rlevel_rank#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4782,	11,	3400},
+	{"cvmx_lmc#_rodt_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4786,	8,	3411},
+	{"cvmx_lmc#_scramble_cfg0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	4787,	1,	3419},
+	{"cvmx_lmc#_scramble_cfg1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	4788,	1,	3420},
+	{"cvmx_lmc#_scrambled_fadr"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	4789,	6,	3421},
+	{"cvmx_lmc#_slot_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4790,	5,	3427},
+	{"cvmx_lmc#_slot_ctl1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4791,	5,	3432},
+	{"cvmx_lmc#_slot_ctl2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4792,	5,	3437},
+	{"cvmx_lmc#_timing_params0"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	4793,	12,	3442},
+	{"cvmx_lmc#_timing_params1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	4794,	13,	3454},
+	{"cvmx_lmc#_tro_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4795,	3,	3467},
+	{"cvmx_lmc#_tro_stat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4796,	2,	3470},
+	{"cvmx_lmc#_wlevel_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4797,	6,	3472},
+	{"cvmx_lmc#_wlevel_dbg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4798,	3,	3478},
+	{"cvmx_lmc#_wlevel_rank#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4799,	11,	3481},
+	{"cvmx_lmc#_wodt_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4803,	8,	3492},
+	{"cvmx_mio_boot_bist_stat"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	4804,	2,	3500},
+	{"cvmx_mio_boot_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4805,	3,	3502},
+	{"cvmx_mio_boot_dma_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4806,	10,	3505},
+	{"cvmx_mio_boot_dma_int#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4808,	3,	3515},
+	{"cvmx_mio_boot_dma_int_en#"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	4810,	3,	3518},
+	{"cvmx_mio_boot_dma_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4812,	15,	3521},
+	{"cvmx_mio_boot_err"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4814,	3,	3536},
+	{"cvmx_mio_boot_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4815,	3,	3539},
+	{"cvmx_mio_boot_loc_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4816,	3,	3542},
+	{"cvmx_mio_boot_loc_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4817,	5,	3545},
+	{"cvmx_mio_boot_loc_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4819,	1,	3550},
+	{"cvmx_mio_boot_pin_defs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4820,	10,	3551},
+	{"cvmx_mio_boot_reg_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4821,	13,	3561},
+	{"cvmx_mio_boot_reg_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	4829,	13,	3574},
+	{"cvmx_mio_boot_thr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4837,	6,	3587},
+	{"cvmx_mio_emm_buf_dat"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4838,	1,	3593},
+	{"cvmx_mio_emm_buf_idx"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4839,	5,	3594},
+	{"cvmx_mio_emm_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4840,	4,	3599},
+	{"cvmx_mio_emm_cmd"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4841,	11,	3603},
+	{"cvmx_mio_emm_dma"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4842,	11,	3614},
+	{"cvmx_mio_emm_int"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4843,	8,	3625},
+	{"cvmx_mio_emm_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4844,	8,	3633},
+	{"cvmx_mio_emm_mode#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4845,	8,	3641},
+	{"cvmx_mio_emm_rca"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4849,	2,	3649},
+	{"cvmx_mio_emm_rsp_hi"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4850,	1,	3651},
+	{"cvmx_mio_emm_rsp_lo"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4851,	1,	3652},
+	{"cvmx_mio_emm_rsp_sts"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4852,	25,	3653},
+	{"cvmx_mio_emm_sample"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4853,	4,	3678},
+	{"cvmx_mio_emm_sts_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4854,	2,	3682},
+	{"cvmx_mio_emm_switch"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4855,	14,	3684},
+	{"cvmx_mio_emm_wdog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4856,	2,	3698},
+	{"cvmx_mio_fus_bnk_dat#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4857,	1,	3700},
+	{"cvmx_mio_fus_dat0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4859,	2,	3701},
+	{"cvmx_mio_fus_dat1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4860,	2,	3703},
+	{"cvmx_mio_fus_dat2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4861,	15,	3705},
+	{"cvmx_mio_fus_dat3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4862,	18,	3720},
+	{"cvmx_mio_fus_ema"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4863,	4,	3738},
+	{"cvmx_mio_fus_pdf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4864,	1,	3742},
+	{"cvmx_mio_fus_pll"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4865,	7,	3743},
+	{"cvmx_mio_fus_prog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4866,	3,	3750},
+	{"cvmx_mio_fus_prog_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	4867,	8,	3753},
+	{"cvmx_mio_fus_rcmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4868,	7,	3761},
+	{"cvmx_mio_fus_read_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	4869,	6,	3768},
+	{"cvmx_mio_fus_repair_res0"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	4870,	5,	3774},
+	{"cvmx_mio_fus_repair_res1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	4871,	4,	3779},
+	{"cvmx_mio_fus_repair_res2"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	4872,	2,	3783},
+	{"cvmx_mio_fus_spr_repair_res" ,	CVMX_CSR_DB_TYPE_RSL,	64,	4873,	4,	3785},
+	{"cvmx_mio_fus_spr_repair_sum" ,	CVMX_CSR_DB_TYPE_RSL,	64,	4874,	2,	3789},
+	{"cvmx_mio_fus_tgg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4875,	2,	3791},
+	{"cvmx_mio_fus_wadr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4876,	2,	3793},
+	{"cvmx_mio_gpio_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4877,	3,	3795},
+	{"cvmx_mio_ndf_dma_cfg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4878,	10,	3798},
+	{"cvmx_mio_ndf_dma_int"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4879,	2,	3808},
+	{"cvmx_mio_ndf_dma_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	4880,	2,	3810},
+	{"cvmx_mio_ptp_ckout_hi_incr"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4881,	2,	3812},
+	{"cvmx_mio_ptp_ckout_lo_incr"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4882,	2,	3814},
+	{"cvmx_mio_ptp_ckout_thresh_hi",	CVMX_CSR_DB_TYPE_NCB,	64,	4883,	1,	3816},
+	{"cvmx_mio_ptp_ckout_thresh_lo",	CVMX_CSR_DB_TYPE_NCB,	64,	4884,	2,	3817},
+	{"cvmx_mio_ptp_clock_cfg"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	4885,	20,	3819},
+	{"cvmx_mio_ptp_clock_comp"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	4886,	2,	3839},
+	{"cvmx_mio_ptp_clock_hi"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	4887,	1,	3841},
+	{"cvmx_mio_ptp_clock_lo"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	4888,	2,	3842},
+	{"cvmx_mio_ptp_evt_cnt"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	4889,	1,	3844},
+	{"cvmx_mio_ptp_phy_1pps_in"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	4890,	2,	3845},
+	{"cvmx_mio_ptp_pps_hi_incr"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	4891,	2,	3847},
+	{"cvmx_mio_ptp_pps_lo_incr"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	4892,	2,	3849},
+	{"cvmx_mio_ptp_pps_thresh_hi"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4893,	1,	3851},
+	{"cvmx_mio_ptp_pps_thresh_lo"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	4894,	2,	3852},
+	{"cvmx_mio_ptp_timestamp"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	4895,	1,	3854},
+	{"cvmx_mio_qlm#_cfg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4896,	6,	3855},
+	{"cvmx_mio_rst_boot"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4898,	17,	3861},
+	{"cvmx_mio_rst_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4899,	5,	3878},
+	{"cvmx_mio_rst_ckill"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4900,	2,	3883},
+	{"cvmx_mio_rst_cntl#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4901,	13,	3885},
+	{"cvmx_mio_rst_ctl#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4903,	13,	3898},
+	{"cvmx_mio_rst_delay"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4905,	3,	3911},
+	{"cvmx_mio_rst_int"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4906,	6,	3914},
+	{"cvmx_mio_rst_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4907,	6,	3920},
+	{"cvmx_mio_tws#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4908,	13,	3926},
+	{"cvmx_mio_tws#_sw_twsi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4910,	12,	3939},
+	{"cvmx_mio_tws#_sw_twsi_ext"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	4912,	3,	3951},
+	{"cvmx_mio_tws#_twsi_sw"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4914,	3,	3954},
+	{"cvmx_mio_uart#_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4916,	2,	3957},
+	{"cvmx_mio_uart#_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4918,	2,	3959},
+	{"cvmx_mio_uart#_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4920,	2,	3961},
+	{"cvmx_mio_uart#_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4922,	7,	3963},
+	{"cvmx_mio_uart#_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4924,	2,	3970},
+	{"cvmx_mio_uart#_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4926,	7,	3972},
+	{"cvmx_mio_uart#_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4928,	4,	3979},
+	{"cvmx_mio_uart#_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4930,	8,	3983},
+	{"cvmx_mio_uart#_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4932,	9,	3991},
+	{"cvmx_mio_uart#_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4934,	7,	4000},
+	{"cvmx_mio_uart#_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4936,	9,	4007},
+	{"cvmx_mio_uart#_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4938,	2,	4016},
+	{"cvmx_mio_uart#_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4940,	2,	4018},
+	{"cvmx_mio_uart#_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4942,	4,	4020},
+	{"cvmx_mio_uart#_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4944,	2,	4024},
+	{"cvmx_mio_uart#_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4946,	2,	4026},
+	{"cvmx_mio_uart#_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4948,	2,	4028},
+	{"cvmx_mio_uart#_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4950,	4,	4030},
+	{"cvmx_mio_uart#_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4952,	2,	4034},
+	{"cvmx_mio_uart#_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4954,	2,	4036},
+	{"cvmx_mio_uart#_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4956,	2,	4038},
+	{"cvmx_mio_uart#_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4958,	2,	4040},
+	{"cvmx_mio_uart#_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4960,	2,	4042},
+	{"cvmx_mio_uart#_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4962,	2,	4044},
+	{"cvmx_mio_uart#_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4964,	6,	4046},
+	{"cvmx_mpi_cfg"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	4966,	16,	4052},
+	{"cvmx_mpi_dat#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	4967,	2,	4068},
+	{"cvmx_mpi_sts"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	4976,	4,	4070},
+	{"cvmx_mpi_tx"                 ,	CVMX_CSR_DB_TYPE_NCB,	64,	4977,	8,	4074},
+	{"cvmx_pcieep#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	4978,	2,	4082},
+	{"cvmx_pcieep#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	4980,	24,	4084},
+	{"cvmx_pcieep#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	4982,	4,	4108},
+	{"cvmx_pcieep#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	4984,	5,	4112},
+	{"cvmx_pcieep#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	4986,	5,	4117},
+	{"cvmx_pcieep#_cfg004_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	4988,	2,	4122},
+	{"cvmx_pcieep#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	4990,	1,	4124},
+	{"cvmx_pcieep#_cfg005_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	4992,	1,	4125},
+	{"cvmx_pcieep#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	4994,	5,	4126},
+	{"cvmx_pcieep#_cfg006_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	4996,	2,	4131},
+	{"cvmx_pcieep#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	4998,	1,	4133},
+	{"cvmx_pcieep#_cfg007_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5000,	1,	4134},
+	{"cvmx_pcieep#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5002,	4,	4135},
+	{"cvmx_pcieep#_cfg008_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5004,	2,	4139},
+	{"cvmx_pcieep#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5006,	2,	4141},
+	{"cvmx_pcieep#_cfg009_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5008,	1,	4143},
+	{"cvmx_pcieep#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5010,	1,	4144},
+	{"cvmx_pcieep#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5012,	2,	4145},
+	{"cvmx_pcieep#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5014,	3,	4147},
+	{"cvmx_pcieep#_cfg012_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5016,	2,	4150},
+	{"cvmx_pcieep#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5018,	2,	4152},
+	{"cvmx_pcieep#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5020,	4,	4154},
+	{"cvmx_pcieep#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5022,	10,	4158},
+	{"cvmx_pcieep#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5024,	12,	4168},
+	{"cvmx_pcieep#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5026,	8,	4180},
+	{"cvmx_pcieep#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5028,	2,	4188},
+	{"cvmx_pcieep#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5030,	1,	4190},
+	{"cvmx_pcieep#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5032,	2,	4191},
+	{"cvmx_pcieep#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5034,	7,	4193},
+	{"cvmx_pcieep#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5036,	12,	4200},
+	{"cvmx_pcieep#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5038,	19,	4212},
+	{"cvmx_pcieep#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5040,	12,	4231},
+	{"cvmx_pcieep#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5042,	20,	4243},
+	{"cvmx_pcieep#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5044,	13,	4263},
+	{"cvmx_pcieep#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5046,	11,	4276},
+	{"cvmx_pcieep#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5048,	4,	4287},
+	{"cvmx_pcieep#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5050,	11,	4291},
+	{"cvmx_pcieep#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5052,	3,	4302},
+	{"cvmx_pcieep#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5054,	17,	4305},
+	{"cvmx_pcieep#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5056,	17,	4322},
+	{"cvmx_pcieep#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5058,	17,	4339},
+	{"cvmx_pcieep#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5060,	10,	4356},
+	{"cvmx_pcieep#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5062,	10,	4366},
+	{"cvmx_pcieep#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5064,	6,	4376},
+	{"cvmx_pcieep#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5066,	1,	4382},
+	{"cvmx_pcieep#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5068,	1,	4383},
+	{"cvmx_pcieep#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5070,	1,	4384},
+	{"cvmx_pcieep#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5072,	1,	4385},
+	{"cvmx_pcieep#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5074,	2,	4386},
+	{"cvmx_pcieep#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5076,	1,	4388},
+	{"cvmx_pcieep#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5078,	6,	4389},
+	{"cvmx_pcieep#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5080,	7,	4395},
+	{"cvmx_pcieep#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5082,	11,	4402},
+	{"cvmx_pcieep#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5084,	5,	4413},
+	{"cvmx_pcieep#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5086,	6,	4418},
+	{"cvmx_pcieep#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5088,	19,	4424},
+	{"cvmx_pcieep#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5090,	5,	4443},
+	{"cvmx_pcieep#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5092,	1,	4448},
+	{"cvmx_pcieep#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5094,	1,	4449},
+	{"cvmx_pcieep#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5096,	3,	4450},
+	{"cvmx_pcieep#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5098,	3,	4453},
+	{"cvmx_pcieep#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5100,	3,	4456},
+	{"cvmx_pcieep#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5102,	4,	4459},
+	{"cvmx_pcieep#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5104,	4,	4463},
+	{"cvmx_pcieep#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5106,	4,	4467},
+	{"cvmx_pcieep#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5108,	7,	4471},
+	{"cvmx_pcieep#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5110,	5,	4478},
+	{"cvmx_pcieep#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5112,	5,	4483},
+	{"cvmx_pcieep#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5114,	4,	4488},
+	{"cvmx_pcieep#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5116,	4,	4492},
+	{"cvmx_pcieep#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5118,	4,	4496},
+	{"cvmx_pcieep#_cfg515"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5120,	7,	4500},
+	{"cvmx_pcieep#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5122,	1,	4507},
+	{"cvmx_pcieep#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5124,	1,	4508},
+	{"cvmx_pcierc#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5126,	2,	4509},
+	{"cvmx_pcierc#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5128,	24,	4511},
+	{"cvmx_pcierc#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5130,	4,	4535},
+	{"cvmx_pcierc#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5132,	5,	4539},
+	{"cvmx_pcierc#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5134,	1,	4544},
+	{"cvmx_pcierc#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5136,	1,	4545},
+	{"cvmx_pcierc#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5138,	4,	4546},
+	{"cvmx_pcierc#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5140,	17,	4550},
+	{"cvmx_pcierc#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5142,	4,	4567},
+	{"cvmx_pcierc#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5144,	6,	4571},
+	{"cvmx_pcierc#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5146,	1,	4577},
+	{"cvmx_pcierc#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5148,	1,	4578},
+	{"cvmx_pcierc#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5150,	2,	4579},
+	{"cvmx_pcierc#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5152,	2,	4581},
+	{"cvmx_pcierc#_cfg014"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5154,	1,	4583},
+	{"cvmx_pcierc#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5156,	15,	4584},
+	{"cvmx_pcierc#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5158,	10,	4599},
+	{"cvmx_pcierc#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5160,	12,	4609},
+	{"cvmx_pcierc#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5162,	8,	4621},
+	{"cvmx_pcierc#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5164,	2,	4629},
+	{"cvmx_pcierc#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5166,	1,	4631},
+	{"cvmx_pcierc#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5168,	2,	4632},
+	{"cvmx_pcierc#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5170,	7,	4634},
+	{"cvmx_pcierc#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5172,	11,	4641},
+	{"cvmx_pcierc#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5174,	19,	4652},
+	{"cvmx_pcierc#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5176,	12,	4671},
+	{"cvmx_pcierc#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5178,	20,	4683},
+	{"cvmx_pcierc#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5180,	12,	4703},
+	{"cvmx_pcierc#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5182,	22,	4715},
+	{"cvmx_pcierc#_cfg035"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5184,	8,	4737},
+	{"cvmx_pcierc#_cfg036"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5186,	4,	4745},
+	{"cvmx_pcierc#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5188,	13,	4749},
+	{"cvmx_pcierc#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5190,	11,	4762},
+	{"cvmx_pcierc#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5192,	4,	4773},
+	{"cvmx_pcierc#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5194,	11,	4777},
+	{"cvmx_pcierc#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5196,	1,	4788},
+	{"cvmx_pcierc#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5198,	1,	4789},
+	{"cvmx_pcierc#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5200,	3,	4790},
+	{"cvmx_pcierc#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5202,	18,	4793},
+	{"cvmx_pcierc#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5204,	18,	4811},
+	{"cvmx_pcierc#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5206,	18,	4829},
+	{"cvmx_pcierc#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5208,	10,	4847},
+	{"cvmx_pcierc#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5210,	10,	4857},
+	{"cvmx_pcierc#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5212,	6,	4867},
+	{"cvmx_pcierc#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5214,	1,	4873},
+	{"cvmx_pcierc#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5216,	1,	4874},
+	{"cvmx_pcierc#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5218,	1,	4875},
+	{"cvmx_pcierc#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5220,	1,	4876},
+	{"cvmx_pcierc#_cfg075"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5222,	4,	4877},
+	{"cvmx_pcierc#_cfg076"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5224,	9,	4881},
+	{"cvmx_pcierc#_cfg077"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5226,	2,	4890},
+	{"cvmx_pcierc#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5228,	2,	4892},
+	{"cvmx_pcierc#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5230,	1,	4894},
+	{"cvmx_pcierc#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5232,	6,	4895},
+	{"cvmx_pcierc#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5234,	7,	4901},
+	{"cvmx_pcierc#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5236,	11,	4908},
+	{"cvmx_pcierc#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5238,	5,	4919},
+	{"cvmx_pcierc#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5240,	6,	4924},
+	{"cvmx_pcierc#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5242,	19,	4930},
+	{"cvmx_pcierc#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5244,	5,	4949},
+	{"cvmx_pcierc#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5246,	1,	4954},
+	{"cvmx_pcierc#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5248,	1,	4955},
+	{"cvmx_pcierc#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5250,	3,	4956},
+	{"cvmx_pcierc#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5252,	3,	4959},
+	{"cvmx_pcierc#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5254,	3,	4962},
+	{"cvmx_pcierc#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5256,	4,	4965},
+	{"cvmx_pcierc#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5258,	4,	4969},
+	{"cvmx_pcierc#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5260,	4,	4973},
+	{"cvmx_pcierc#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5262,	7,	4977},
+	{"cvmx_pcierc#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5264,	5,	4984},
+	{"cvmx_pcierc#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5266,	5,	4989},
+	{"cvmx_pcierc#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5268,	4,	4994},
+	{"cvmx_pcierc#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5270,	4,	4998},
+	{"cvmx_pcierc#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5272,	4,	5002},
+	{"cvmx_pcierc#_cfg515"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5274,	7,	5006},
+	{"cvmx_pcierc#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5276,	1,	5013},
+	{"cvmx_pcierc#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5278,	1,	5014},
+	{"cvmx_pcm#_dma_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5280,	12,	5015},
+	{"cvmx_pcm#_int_ena"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5284,	9,	5027},
+	{"cvmx_pcm#_int_sum"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5288,	9,	5036},
+	{"cvmx_pcm#_rxaddr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5292,	2,	5045},
+	{"cvmx_pcm#_rxcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5296,	2,	5047},
+	{"cvmx_pcm#_rxmsk0"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5300,	1,	5049},
+	{"cvmx_pcm#_rxmsk1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5304,	1,	5050},
+	{"cvmx_pcm#_rxmsk2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5308,	1,	5051},
+	{"cvmx_pcm#_rxmsk3"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5312,	1,	5052},
+	{"cvmx_pcm#_rxmsk4"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5316,	1,	5053},
+	{"cvmx_pcm#_rxmsk5"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5320,	1,	5054},
+	{"cvmx_pcm#_rxmsk6"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5324,	1,	5055},
+	{"cvmx_pcm#_rxmsk7"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5328,	1,	5056},
+	{"cvmx_pcm#_rxstart"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5332,	3,	5057},
+	{"cvmx_pcm#_tdm_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5336,	6,	5060},
+	{"cvmx_pcm#_tdm_dbg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5340,	1,	5066},
+	{"cvmx_pcm#_txaddr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5344,	3,	5067},
+	{"cvmx_pcm#_txcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5348,	2,	5070},
+	{"cvmx_pcm#_txmsk0"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5352,	1,	5072},
+	{"cvmx_pcm#_txmsk1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5356,	1,	5073},
+	{"cvmx_pcm#_txmsk2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5360,	1,	5074},
+	{"cvmx_pcm#_txmsk3"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5364,	1,	5075},
+	{"cvmx_pcm#_txmsk4"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5368,	1,	5076},
+	{"cvmx_pcm#_txmsk5"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5372,	1,	5077},
+	{"cvmx_pcm#_txmsk6"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5376,	1,	5078},
+	{"cvmx_pcm#_txmsk7"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5380,	1,	5079},
+	{"cvmx_pcm#_txstart"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5384,	3,	5080},
+	{"cvmx_pcm_clk#_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5388,	12,	5083},
+	{"cvmx_pcm_clk#_dbg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5390,	1,	5095},
+	{"cvmx_pcm_clk#_gen"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	5392,	3,	5096},
+	{"cvmx_pcs#_an#_adv_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5394,	9,	5099},
+	{"cvmx_pcs#_an#_ext_st_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5396,	6,	5108},
+	{"cvmx_pcs#_an#_lp_abil_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5398,	9,	5114},
+	{"cvmx_pcs#_an#_results_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5400,	6,	5123},
+	{"cvmx_pcs#_int#_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5402,	14,	5129},
+	{"cvmx_pcs#_int#_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5404,	14,	5143},
+	{"cvmx_pcs#_link#_timer_count_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	5406,	2,	5157},
+	{"cvmx_pcs#_log_anl#_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5408,	4,	5159},
+	{"cvmx_pcs#_misc#_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5410,	8,	5163},
+	{"cvmx_pcs#_mr#_control_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5412,	13,	5171},
+	{"cvmx_pcs#_mr#_status_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5414,	17,	5184},
+	{"cvmx_pcs#_rx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5416,	7,	5201},
+	{"cvmx_pcs#_rx#_sync_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5418,	3,	5208},
+	{"cvmx_pcs#_sgm#_an_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5420,	8,	5211},
+	{"cvmx_pcs#_sgm#_lp_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5422,	7,	5219},
+	{"cvmx_pcs#_tx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5424,	4,	5226},
+	{"cvmx_pcs#_tx_rx#_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	5426,	5,	5230},
+	{"cvmx_pem#_bar1_index#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5428,	5,	5235},
+	{"cvmx_pem#_bar2_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5460,	3,	5240},
+	{"cvmx_pem#_bar_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5462,	5,	5243},
+	{"cvmx_pem#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5464,	9,	5248},
+	{"cvmx_pem#_bist_status2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5466,	11,	5257},
+	{"cvmx_pem#_cfg_rd"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5468,	2,	5268},
+	{"cvmx_pem#_cfg_wr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5470,	2,	5270},
+	{"cvmx_pem#_cpl_lut_valid"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5472,	2,	5272},
+	{"cvmx_pem#_ctl_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5474,	18,	5274},
+	{"cvmx_pem#_dbg_info"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5476,	32,	5292},
+	{"cvmx_pem#_dbg_info_en"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5478,	32,	5324},
+	{"cvmx_pem#_diag_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5480,	5,	5356},
+	{"cvmx_pem#_inb_read_credits"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	5482,	2,	5361},
+	{"cvmx_pem#_int_enb"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5484,	15,	5363},
+	{"cvmx_pem#_int_enb_int"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5486,	15,	5378},
+	{"cvmx_pem#_int_sum"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5488,	15,	5393},
+	{"cvmx_pem#_p2n_bar0_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5490,	2,	5408},
+	{"cvmx_pem#_p2n_bar1_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5492,	2,	5410},
+	{"cvmx_pem#_p2n_bar2_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5494,	2,	5412},
+	{"cvmx_pem#_tlp_credits"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5496,	6,	5414},
+	{"cvmx_pip_alt_skip_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5498,	12,	5420},
+	{"cvmx_pip_bck_prs"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5502,	5,	5432},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5503,	2,	5437},
+	{"cvmx_pip_bsel_ext_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5504,	7,	5439},
+	{"cvmx_pip_bsel_ext_pos#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5508,	16,	5446},
+	{"cvmx_pip_bsel_tbl_ent#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5512,	12,	5462},
+	{"cvmx_pip_clken"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	6024,	2,	5474},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6025,	4,	5476},
+	{"cvmx_pip_dsa_src_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6029,	16,	5480},
+	{"cvmx_pip_dsa_vid_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6030,	16,	5496},
+	{"cvmx_pip_frm_len_chk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6031,	3,	5512},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6032,	8,	5515},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6033,	23,	5523},
+	{"cvmx_pip_hg_pri_qos"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6034,	6,	5546},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	6035,	14,	5552},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6036,	14,	5566},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6037,	2,	5580},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6038,	28,	5582},
+	{"cvmx_pip_prt_cfgb#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6048,	7,	5610},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6064,	25,	5617},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6074,	2,	5642},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6138,	4,	5644},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6146,	9,	5648},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6154,	2,	5657},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6155,	2,	5659},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6156,	2,	5661},
+	{"cvmx_pip_stat10_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6166,	2,	5663},
+	{"cvmx_pip_stat11_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6176,	2,	5665},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6186,	2,	5667},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6196,	2,	5669},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6206,	2,	5671},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6216,	2,	5673},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6226,	2,	5675},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6236,	2,	5677},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6246,	2,	5679},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6256,	2,	5681},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6266,	2,	5683},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6276,	2,	5685},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6277,	2,	5687},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6287,	2,	5689},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6297,	2,	5691},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6307,	2,	5693},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6371,	2,	5695},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6372,	3,	5697},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6373,	3,	5700},
+	{"cvmx_pip_vlan_etypes#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6374,	4,	5703},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6376,	2,	5707},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6377,	2,	5709},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6378,	4,	5711},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6379,	5,	5715},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6380,	4,	5720},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6381,	8,	5724},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6382,	4,	5732},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6383,	5,	5736},
+	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6384,	1,	5741},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6385,	5,	5742},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6386,	1,	5747},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6387,	13,	5748},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6388,	6,	5761},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6389,	13,	5767},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6390,	6,	5780},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6391,	12,	5786},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6392,	4,	5798},
+	{"cvmx_pko_mem_port_ptrs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6393,	7,	5802},
+	{"cvmx_pko_mem_port_qos"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6394,	5,	5809},
+	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6395,	5,	5814},
+	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6396,	4,	5819},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6397,	9,	5823},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6398,	5,	5832},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6399,	16,	5837},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6400,	4,	5853},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6401,	1,	5857},
+	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6402,	1,	5858},
+	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6403,	1,	5859},
+	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6404,	1,	5860},
+	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	6405,	15,	5861},
+	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6406,	2,	5876},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6407,	4,	5878},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6408,	8,	5882},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6409,	3,	5890},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6410,	4,	5893},
+	{"cvmx_pko_reg_preempt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6411,	2,	5897},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6412,	2,	5899},
+	{"cvmx_pko_reg_queue_preempt"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6413,	3,	5901},
+	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6414,	3,	5904},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6415,	3,	5907},
+	{"cvmx_pko_reg_timestamp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6416,	2,	5910},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6417,	10,	5912},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	6418,	2,	5922},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6419,	13,	5924},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6420,	3,	5937},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6421,	2,	5940},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	6429,	2,	5942},
+	{"cvmx_pow_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6430,	2,	5944},
+	{"cvmx_pow_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6431,	2,	5946},
+	{"cvmx_pow_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6432,	2,	5948},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6440,	2,	5950},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6441,	2,	5952},
+	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	6442,	2,	5954},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6443,	10,	5956},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	6447,	5,	5966},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	6455,	10,	5971},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	6463,	2,	5981},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6464,	2,	5983},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6465,	2,	5985},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6473,	3,	5987},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6474,	6,	5990},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6490,	5,	5996},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6491,	7,	6001},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6507,	2,	6008},
+	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6523,	1,	6010},
+	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6524,	1,	6011},
+	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6525,	1,	6012},
+	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6526,	5,	6013},
+	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6527,	5,	6018},
+	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6528,	4,	6023},
+	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6529,	10,	6027},
+	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6530,	1,	6037},
+	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6531,	3,	6038},
+	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6532,	7,	6041},
+	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6533,	2,	6048},
+	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6534,	1,	6050},
+	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6535,	1,	6051},
+	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6536,	1,	6052},
+	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6537,	18,	6053},
+	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6538,	3,	6071},
+	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6539,	2,	6074},
+	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6540,	3,	6076},
+	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6541,	7,	6079},
+	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6542,	2,	6086},
+	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6543,	2,	6088},
+	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6544,	2,	6090},
+	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6545,	3,	6092},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6546,	3,	6095},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6547,	10,	6098},
+	{"cvmx_rnm_eer_dbg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6548,	1,	6108},
+	{"cvmx_rnm_eer_key"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6549,	1,	6109},
+	{"cvmx_rnm_serial_num"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6550,	1,	6110},
+	{"cvmx_sli_bist_status"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6551,	24,	6111},
+	{"cvmx_sli_ctl_port#"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6552,	16,	6135},
+	{"cvmx_sli_ctl_status"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6554,	3,	6151},
+	{"cvmx_sli_data_out_cnt"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6555,	5,	6154},
+	{"cvmx_sli_dbg_data"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6556,	3,	6159},
+	{"cvmx_sli_dbg_select"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6557,	3,	6162},
+	{"cvmx_sli_dma#_cnt"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6558,	2,	6165},
+	{"cvmx_sli_dma#_int_level"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6560,	2,	6167},
+	{"cvmx_sli_dma#_tim"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6562,	2,	6169},
+	{"cvmx_sli_int_enb_ciu"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6564,	45,	6171},
+	{"cvmx_sli_int_enb_port#"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6565,	46,	6216},
+	{"cvmx_sli_int_sum"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6567,	46,	6262},
+	{"cvmx_sli_last_win_rdata0"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6568,	1,	6308},
+	{"cvmx_sli_last_win_rdata1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6569,	1,	6309},
+	{"cvmx_sli_last_win_rdata2"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6570,	1,	6310},
+	{"cvmx_sli_last_win_rdata3"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6571,	1,	6311},
+	{"cvmx_sli_mac_credit_cnt"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6572,	13,	6312},
+	{"cvmx_sli_mac_credit_cnt2"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6573,	13,	6325},
+	{"cvmx_sli_mac_number"         ,	CVMX_CSR_DB_TYPE_PEXP,	64,	6574,	3,	6338},
+	{"cvmx_sli_mem_access_ctl"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6575,	3,	6341},
+	{"cvmx_sli_mem_access_subid#"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6576,	9,	6344},
+	{"cvmx_sli_msi_enb0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6592,	1,	6353},
+	{"cvmx_sli_msi_enb1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6593,	1,	6354},
+	{"cvmx_sli_msi_enb2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6594,	1,	6355},
+	{"cvmx_sli_msi_enb3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6595,	1,	6356},
+	{"cvmx_sli_msi_rcv0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6596,	1,	6357},
+	{"cvmx_sli_msi_rcv1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6597,	1,	6358},
+	{"cvmx_sli_msi_rcv2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6598,	1,	6359},
+	{"cvmx_sli_msi_rcv3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6599,	1,	6360},
+	{"cvmx_sli_msi_rd_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6600,	3,	6361},
+	{"cvmx_sli_msi_w1c_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6601,	1,	6364},
+	{"cvmx_sli_msi_w1c_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6602,	1,	6365},
+	{"cvmx_sli_msi_w1c_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6603,	1,	6366},
+	{"cvmx_sli_msi_w1c_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6604,	1,	6367},
+	{"cvmx_sli_msi_w1s_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6605,	1,	6368},
+	{"cvmx_sli_msi_w1s_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6606,	1,	6369},
+	{"cvmx_sli_msi_w1s_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6607,	1,	6370},
+	{"cvmx_sli_msi_w1s_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6608,	1,	6371},
+	{"cvmx_sli_msi_wr_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6609,	3,	6372},
+	{"cvmx_sli_pcie_msi_rcv"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6610,	2,	6375},
+	{"cvmx_sli_pcie_msi_rcv_b1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6611,	3,	6377},
+	{"cvmx_sli_pcie_msi_rcv_b2"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6612,	3,	6380},
+	{"cvmx_sli_pcie_msi_rcv_b3"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6613,	3,	6383},
+	{"cvmx_sli_pkt#_cnts"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6614,	3,	6386},
+	{"cvmx_sli_pkt#_in_bp"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6646,	2,	6389},
+	{"cvmx_sli_pkt#_instr_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6678,	2,	6391},
+	{"cvmx_sli_pkt#_instr_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6710,	2,	6393},
+	{"cvmx_sli_pkt#_instr_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6742,	5,	6395},
+	{"cvmx_sli_pkt#_instr_header"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6774,	21,	6400},
+	{"cvmx_sli_pkt#_out_size"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6806,	3,	6421},
+	{"cvmx_sli_pkt#_slist_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6838,	2,	6424},
+	{"cvmx_sli_pkt#_slist_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6870,	2,	6426},
+	{"cvmx_sli_pkt#_slist_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6902,	2,	6428},
+	{"cvmx_sli_pkt_cnt_int"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6934,	2,	6430},
+	{"cvmx_sli_pkt_cnt_int_enb"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6935,	2,	6432},
+	{"cvmx_sli_pkt_ctl"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6936,	3,	6434},
+	{"cvmx_sli_pkt_data_out_es"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6937,	1,	6437},
+	{"cvmx_sli_pkt_data_out_ns"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6938,	2,	6438},
+	{"cvmx_sli_pkt_data_out_ror"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6939,	2,	6440},
+	{"cvmx_sli_pkt_dpaddr"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6940,	2,	6442},
+	{"cvmx_sli_pkt_in_bp"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6941,	2,	6444},
+	{"cvmx_sli_pkt_in_done#_cnts"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6942,	2,	6446},
+	{"cvmx_sli_pkt_in_instr_counts",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6974,	2,	6448},
+	{"cvmx_sli_pkt_in_pcie_port"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6975,	1,	6450},
+	{"cvmx_sli_pkt_input_control"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6976,	17,	6451},
+	{"cvmx_sli_pkt_instr_enb"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6977,	2,	6468},
+	{"cvmx_sli_pkt_instr_rd_size"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6978,	1,	6470},
+	{"cvmx_sli_pkt_instr_size"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6979,	2,	6471},
+	{"cvmx_sli_pkt_int_levels"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6980,	3,	6473},
+	{"cvmx_sli_pkt_iptr"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6981,	2,	6476},
+	{"cvmx_sli_pkt_out_bmode"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6982,	2,	6478},
+	{"cvmx_sli_pkt_out_enb"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6983,	2,	6480},
+	{"cvmx_sli_pkt_output_wmark"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6984,	2,	6482},
+	{"cvmx_sli_pkt_pcie_port"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6985,	1,	6484},
+	{"cvmx_sli_pkt_port_in_rst"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6986,	2,	6485},
+	{"cvmx_sli_pkt_slist_es"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6987,	1,	6487},
+	{"cvmx_sli_pkt_slist_ns"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6988,	2,	6488},
+	{"cvmx_sli_pkt_slist_ror"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6989,	2,	6490},
+	{"cvmx_sli_pkt_time_int"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6990,	2,	6492},
+	{"cvmx_sli_pkt_time_int_enb"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6991,	2,	6494},
+	{"cvmx_sli_s2m_port#_ctl"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6992,	4,	6496},
+	{"cvmx_sli_scratch_1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6994,	1,	6500},
+	{"cvmx_sli_scratch_2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6995,	1,	6501},
+	{"cvmx_sli_state1"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6996,	4,	6502},
+	{"cvmx_sli_state2"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6997,	8,	6506},
+	{"cvmx_sli_state3"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6998,	5,	6514},
+	{"cvmx_sli_win_rd_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	6999,	4,	6519},
+	{"cvmx_sli_win_rd_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7000,	1,	6523},
+	{"cvmx_sli_win_wr_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7001,	4,	6524},
+	{"cvmx_sli_win_wr_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7002,	1,	6528},
+	{"cvmx_sli_win_wr_mask"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7003,	2,	6529},
+	{"cvmx_sli_window_ctl"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7004,	2,	6531},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7005,	10,	6533},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7007,	6,	6543},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	7009,	2,	6549},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7011,	4,	6551},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7013,	4,	6555},
+	{"cvmx_smi_drv_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7015,	4,	6559},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7016,	6,	6563},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7017,	3,	6569},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7018,	5,	6572},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7019,	4,	6577},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7020,	6,	6581},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7021,	4,	6587},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7022,	2,	6591},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7023,	4,	6593},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7024,	2,	6597},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7025,	3,	6599},
+	{"cvmx_tra#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7026,	2,	6602},
+	{"cvmx_tra#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7027,	14,	6604},
+	{"cvmx_tra#_cycles_since"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7028,	3,	6618},
+	{"cvmx_tra#_cycles_since1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7029,	5,	6621},
+	{"cvmx_tra#_filt_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7030,	2,	6626},
+	{"cvmx_tra#_filt_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7031,	2,	6628},
+	{"cvmx_tra#_filt_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7032,	57,	6630},
+	{"cvmx_tra#_filt_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7033,	20,	6687},
+	{"cvmx_tra#_filt_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7034,	7,	6707},
+	{"cvmx_tra#_int_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7035,	5,	6714},
+	{"cvmx_tra#_read_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7036,	1,	6719},
+	{"cvmx_tra#_read_dat_hi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7037,	2,	6720},
+	{"cvmx_tra#_trig0_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7038,	2,	6722},
+	{"cvmx_tra#_trig0_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7039,	2,	6724},
+	{"cvmx_tra#_trig0_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7040,	57,	6726},
+	{"cvmx_tra#_trig0_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7041,	20,	6783},
+	{"cvmx_tra#_trig0_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7042,	7,	6803},
+	{"cvmx_tra#_trig1_adr_adr"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7043,	2,	6810},
+	{"cvmx_tra#_trig1_adr_msk"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7044,	2,	6812},
+	{"cvmx_tra#_trig1_cmd"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7045,	57,	6814},
+	{"cvmx_tra#_trig1_did"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7046,	20,	6871},
+	{"cvmx_tra#_trig1_sid"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7047,	7,	6891},
+	{"cvmx_uahc#_ehci_asynclistaddr",	CVMX_CSR_DB_TYPE_NCB,	32,	7048,	2,	6898},
+	{"cvmx_uahc#_ehci_configflag"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7049,	2,	6900},
+	{"cvmx_uahc#_ehci_ctrldssegment",	CVMX_CSR_DB_TYPE_NCB,	32,	7050,	1,	6902},
+	{"cvmx_uahc#_ehci_frindex"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7051,	2,	6903},
+	{"cvmx_uahc#_ehci_hccapbase"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7052,	3,	6905},
+	{"cvmx_uahc#_ehci_hccparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7053,	7,	6908},
+	{"cvmx_uahc#_ehci_hcsparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7054,	10,	6915},
+	{"cvmx_uahc#_ehci_insnreg00"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7055,	3,	6925},
+	{"cvmx_uahc#_ehci_insnreg03"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7056,	5,	6928},
+	{"cvmx_uahc#_ehci_insnreg04"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7057,	7,	6933},
+	{"cvmx_uahc#_ehci_insnreg06"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7058,	2,	6940},
+	{"cvmx_uahc#_ehci_insnreg07"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7059,	1,	6942},
+	{"cvmx_uahc#_ehci_periodiclistbase",	CVMX_CSR_DB_TYPE_NCB,	32,	7060,	2,	6943},
+	{"cvmx_uahc#_ehci_portsc#"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7061,	19,	6945},
+	{"cvmx_uahc#_ehci_usbcmd"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	7063,	13,	6964},
+	{"cvmx_uahc#_ehci_usbintr"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7064,	7,	6977},
+	{"cvmx_uahc#_ehci_usbsts"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	7065,	12,	6984},
+	{"cvmx_uahc#_ohci0_hcbulkcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7066,	2,	6996},
+	{"cvmx_uahc#_ohci0_hcbulkheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	7067,	2,	6998},
+	{"cvmx_uahc#_ohci0_hccommandstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	7068,	7,	7000},
+	{"cvmx_uahc#_ohci0_hccontrol"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7069,	10,	7007},
+	{"cvmx_uahc#_ohci0_hccontrolcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7070,	2,	7017},
+	{"cvmx_uahc#_ohci0_hccontrolheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	7071,	2,	7019},
+	{"cvmx_uahc#_ohci0_hcdonehead" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7072,	2,	7021},
+	{"cvmx_uahc#_ohci0_hcfminterval",	CVMX_CSR_DB_TYPE_NCB,	32,	7073,	4,	7023},
+	{"cvmx_uahc#_ohci0_hcfmnumber" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7074,	2,	7027},
+	{"cvmx_uahc#_ohci0_hcfmremaining",	CVMX_CSR_DB_TYPE_NCB,	32,	7075,	3,	7029},
+	{"cvmx_uahc#_ohci0_hchcca"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7076,	2,	7032},
+	{"cvmx_uahc#_ohci0_hcinterruptdisable",	CVMX_CSR_DB_TYPE_NCB,	32,	7077,	10,	7034},
+	{"cvmx_uahc#_ohci0_hcinterruptenable",	CVMX_CSR_DB_TYPE_NCB,	32,	7078,	10,	7044},
+	{"cvmx_uahc#_ohci0_hcinterruptstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	7079,	10,	7054},
+	{"cvmx_uahc#_ohci0_hclsthreshold",	CVMX_CSR_DB_TYPE_NCB,	32,	7080,	2,	7064},
+	{"cvmx_uahc#_ohci0_hcperiodcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7081,	2,	7066},
+	{"cvmx_uahc#_ohci0_hcperiodicstart",	CVMX_CSR_DB_TYPE_NCB,	32,	7082,	2,	7068},
+	{"cvmx_uahc#_ohci0_hcrevision" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7083,	2,	7070},
+	{"cvmx_uahc#_ohci0_hcrhdescriptora",	CVMX_CSR_DB_TYPE_NCB,	32,	7084,	8,	7072},
+	{"cvmx_uahc#_ohci0_hcrhdescriptorb",	CVMX_CSR_DB_TYPE_NCB,	32,	7085,	2,	7080},
+	{"cvmx_uahc#_ohci0_hcrhportstatus#",	CVMX_CSR_DB_TYPE_NCB,	32,	7086,	15,	7082},
+	{"cvmx_uahc#_ohci0_hcrhstatus" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7088,	8,	7097},
+	{"cvmx_uahc#_ohci0_insnreg06"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7089,	2,	7105},
+	{"cvmx_uahc#_ohci0_insnreg07"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7090,	1,	7107},
+	{"cvmx_uctl#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7091,	7,	7108},
+	{"cvmx_uctl#_clk_rst_ctl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7092,	21,	7115},
+	{"cvmx_uctl#_ehci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7093,	12,	7136},
+	{"cvmx_uctl#_ehci_fla"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7094,	2,	7148},
+	{"cvmx_uctl#_erto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7095,	3,	7150},
+	{"cvmx_uctl#_if_ena"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7096,	2,	7153},
+	{"cvmx_uctl#_int_ena"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7097,	9,	7155},
+	{"cvmx_uctl#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7098,	9,	7164},
+	{"cvmx_uctl#_ohci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7099,	11,	7173},
+	{"cvmx_uctl#_orto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7100,	3,	7184},
+	{"cvmx_uctl#_ppaf_wm"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7101,	2,	7187},
+	{"cvmx_uctl#_uphy_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	7102,	11,	7189},
+	{"cvmx_uctl#_uphy_port#_ctl_status",	CVMX_CSR_DB_TYPE_RSL,	64,	7103,	20,	7200},
+	{NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cnf71xx[] = {
+	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
+	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	0},
+	{"CIU_BLOCK_INT"               ,	   0x10700000007c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1},
+	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	2},
+	{"CIU_EN2_IO0_INT"             ,	   0x107000000a600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	3},
+	{"CIU_EN2_IO1_INT"             ,	   0x107000000a608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	3},
+	{"CIU_EN2_IO0_INT_W1C"         ,	   0x107000000ce00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	4},
+	{"CIU_EN2_IO1_INT_W1C"         ,	   0x107000000ce08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	4},
+	{"CIU_EN2_IO0_INT_W1S"         ,	   0x107000000ae00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	5},
+	{"CIU_EN2_IO1_INT_W1S"         ,	   0x107000000ae08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	5},
+	{"CIU_EN2_PP0_IP2"             ,	   0x107000000a000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	6},
+	{"CIU_EN2_PP1_IP2"             ,	   0x107000000a008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	6},
+	{"CIU_EN2_PP2_IP2"             ,	   0x107000000a010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	6},
+	{"CIU_EN2_PP3_IP2"             ,	   0x107000000a018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	6},
+	{"CIU_EN2_PP0_IP2_W1C"         ,	   0x107000000c800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	7},
+	{"CIU_EN2_PP1_IP2_W1C"         ,	   0x107000000c808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	7},
+	{"CIU_EN2_PP2_IP2_W1C"         ,	   0x107000000c810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	7},
+	{"CIU_EN2_PP3_IP2_W1C"         ,	   0x107000000c818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	7},
+	{"CIU_EN2_PP0_IP2_W1S"         ,	   0x107000000a800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	8},
+	{"CIU_EN2_PP1_IP2_W1S"         ,	   0x107000000a808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	8},
+	{"CIU_EN2_PP2_IP2_W1S"         ,	   0x107000000a810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	8},
+	{"CIU_EN2_PP3_IP2_W1S"         ,	   0x107000000a818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	8},
+	{"CIU_EN2_PP0_IP3"             ,	   0x107000000a200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	9},
+	{"CIU_EN2_PP1_IP3"             ,	   0x107000000a208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	9},
+	{"CIU_EN2_PP2_IP3"             ,	   0x107000000a210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	9},
+	{"CIU_EN2_PP3_IP3"             ,	   0x107000000a218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	9},
+	{"CIU_EN2_PP0_IP3_W1C"         ,	   0x107000000ca00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	10},
+	{"CIU_EN2_PP1_IP3_W1C"         ,	   0x107000000ca08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	10},
+	{"CIU_EN2_PP2_IP3_W1C"         ,	   0x107000000ca10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	10},
+	{"CIU_EN2_PP3_IP3_W1C"         ,	   0x107000000ca18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	10},
+	{"CIU_EN2_PP0_IP3_W1S"         ,	   0x107000000aa00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	11},
+	{"CIU_EN2_PP1_IP3_W1S"         ,	   0x107000000aa08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	11},
+	{"CIU_EN2_PP2_IP3_W1S"         ,	   0x107000000aa10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	11},
+	{"CIU_EN2_PP3_IP3_W1S"         ,	   0x107000000aa18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	11},
+	{"CIU_EN2_PP0_IP4"             ,	   0x107000000a400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	12},
+	{"CIU_EN2_PP1_IP4"             ,	   0x107000000a408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	12},
+	{"CIU_EN2_PP2_IP4"             ,	   0x107000000a410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	12},
+	{"CIU_EN2_PP3_IP4"             ,	   0x107000000a418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	12},
+	{"CIU_EN2_PP0_IP4_W1C"         ,	   0x107000000cc00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	13},
+	{"CIU_EN2_PP1_IP4_W1C"         ,	   0x107000000cc08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	13},
+	{"CIU_EN2_PP2_IP4_W1C"         ,	   0x107000000cc10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	13},
+	{"CIU_EN2_PP3_IP4_W1C"         ,	   0x107000000cc18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	13},
+	{"CIU_EN2_PP0_IP4_W1S"         ,	   0x107000000ac00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	14},
+	{"CIU_EN2_PP1_IP4_W1S"         ,	   0x107000000ac08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	14},
+	{"CIU_EN2_PP2_IP4_W1S"         ,	   0x107000000ac10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	14},
+	{"CIU_EN2_PP3_IP4_W1S"         ,	   0x107000000ac18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	14},
+	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	15},
+	{"CIU_GSTOP"                   ,	   0x1070000000710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	16},
+	{"CIU_INT0_EN0"                ,	   0x1070000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT1_EN0"                ,	   0x1070000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT2_EN0"                ,	   0x1070000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT3_EN0"                ,	   0x1070000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT4_EN0"                ,	   0x1070000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT5_EN0"                ,	   0x1070000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT6_EN0"                ,	   0x1070000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT33_EN0"               ,	   0x1070000000410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT0_EN0_W1C"            ,	   0x1070000002200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
+	{"CIU_INT1_EN0_W1C"            ,	   0x1070000002210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
+	{"CIU_INT2_EN0_W1C"            ,	   0x1070000002220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
+	{"CIU_INT3_EN0_W1C"            ,	   0x1070000002230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
+	{"CIU_INT4_EN0_W1C"            ,	   0x1070000002240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
+	{"CIU_INT5_EN0_W1C"            ,	   0x1070000002250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
+	{"CIU_INT6_EN0_W1C"            ,	   0x1070000002260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
+	{"CIU_INT7_EN0_W1C"            ,	   0x1070000002270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
+	{"CIU_INT32_EN0_W1C"           ,	   0x1070000002400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
+	{"CIU_INT33_EN0_W1C"           ,	   0x1070000002410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
+	{"CIU_INT0_EN0_W1S"            ,	   0x1070000006200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
+	{"CIU_INT1_EN0_W1S"            ,	   0x1070000006210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
+	{"CIU_INT2_EN0_W1S"            ,	   0x1070000006220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
+	{"CIU_INT3_EN0_W1S"            ,	   0x1070000006230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
+	{"CIU_INT4_EN0_W1S"            ,	   0x1070000006240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
+	{"CIU_INT5_EN0_W1S"            ,	   0x1070000006250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
+	{"CIU_INT6_EN0_W1S"            ,	   0x1070000006260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
+	{"CIU_INT7_EN0_W1S"            ,	   0x1070000006270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
+	{"CIU_INT32_EN0_W1S"           ,	   0x1070000006400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
+	{"CIU_INT33_EN0_W1S"           ,	   0x1070000006410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
+	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_INT2_EN1"                ,	   0x1070000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_INT3_EN1"                ,	   0x1070000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_INT4_EN1"                ,	   0x1070000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_INT5_EN1"                ,	   0x1070000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_INT6_EN1"                ,	   0x1070000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_INT33_EN1"               ,	   0x1070000000418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_INT0_EN1_W1C"            ,	   0x1070000002208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
+	{"CIU_INT1_EN1_W1C"            ,	   0x1070000002218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
+	{"CIU_INT2_EN1_W1C"            ,	   0x1070000002228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
+	{"CIU_INT3_EN1_W1C"            ,	   0x1070000002238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
+	{"CIU_INT4_EN1_W1C"            ,	   0x1070000002248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
+	{"CIU_INT5_EN1_W1C"            ,	   0x1070000002258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
+	{"CIU_INT6_EN1_W1C"            ,	   0x1070000002268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
+	{"CIU_INT7_EN1_W1C"            ,	   0x1070000002278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
+	{"CIU_INT32_EN1_W1C"           ,	   0x1070000002408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
+	{"CIU_INT33_EN1_W1C"           ,	   0x1070000002418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
+	{"CIU_INT0_EN1_W1S"            ,	   0x1070000006208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	22},
+	{"CIU_INT1_EN1_W1S"            ,	   0x1070000006218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	22},
+	{"CIU_INT2_EN1_W1S"            ,	   0x1070000006228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	22},
+	{"CIU_INT3_EN1_W1S"            ,	   0x1070000006238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	22},
+	{"CIU_INT4_EN1_W1S"            ,	   0x1070000006248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	22},
+	{"CIU_INT5_EN1_W1S"            ,	   0x1070000006258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	22},
+	{"CIU_INT6_EN1_W1S"            ,	   0x1070000006268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	22},
+	{"CIU_INT7_EN1_W1S"            ,	   0x1070000006278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	22},
+	{"CIU_INT32_EN1_W1S"           ,	   0x1070000006408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	22},
+	{"CIU_INT33_EN1_W1S"           ,	   0x1070000006418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	22},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	23},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	23},
+	{"CIU_INT2_EN4_0"              ,	   0x1070000000ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	23},
+	{"CIU_INT3_EN4_0"              ,	   0x1070000000cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	23},
+	{"CIU_INT0_EN4_0_W1C"          ,	   0x1070000002c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT1_EN4_0_W1C"          ,	   0x1070000002c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT2_EN4_0_W1C"          ,	   0x1070000002ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT3_EN4_0_W1C"          ,	   0x1070000002cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT0_EN4_0_W1S"          ,	   0x1070000006c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT1_EN4_0_W1S"          ,	   0x1070000006c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT2_EN4_0_W1S"          ,	   0x1070000006ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT3_EN4_0_W1S"          ,	   0x1070000006cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT2_EN4_1"              ,	   0x1070000000ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT3_EN4_1"              ,	   0x1070000000cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT0_EN4_1_W1C"          ,	   0x1070000002c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT1_EN4_1_W1C"          ,	   0x1070000002c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT2_EN4_1_W1C"          ,	   0x1070000002ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT3_EN4_1_W1C"          ,	   0x1070000002cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT0_EN4_1_W1S"          ,	   0x1070000006c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT1_EN4_1_W1S"          ,	   0x1070000006c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT2_EN4_1_W1S"          ,	   0x1070000006ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT3_EN4_1_W1S"          ,	   0x1070000006cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT3_SUM0"               ,	   0x1070000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT4_SUM0"               ,	   0x1070000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT5_SUM0"               ,	   0x1070000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT6_SUM0"               ,	   0x1070000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT7_SUM0"               ,	   0x1070000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000c00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000c08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT2_SUM4"               ,	   0x1070000000c10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT3_SUM4"               ,	   0x1070000000c18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT33_SUM0"              ,	   0x1070000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT_DBG_SEL"             ,	   0x10700000007d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_MBOX_SET3"               ,	   0x1070000000618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_NMI"                     ,	   0x1070000000718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PCI_INTA"                ,	   0x1070000000750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_PP_DBG"                  ,	   0x1070000000708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE0"                ,	   0x1070000000580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_QLM0"                    ,	   0x1070000000780ull,	CVMX_CSR_DB_TYPE_NCB,	64,	41},
+	{"CIU_QLM1"                    ,	   0x1070000000788ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_QLM2"                    ,	   0x1070000000790ull,	CVMX_CSR_DB_TYPE_NCB,	64,	43},
+	{"CIU_QLM_JTGC"                ,	   0x1070000000768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_QLM_JTGD"                ,	   0x1070000000770ull,	CVMX_CSR_DB_TYPE_NCB,	64,	45},
+	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	46},
+	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	47},
+	{"CIU_SOFT_PRST1"              ,	   0x1070000000758ull,	CVMX_CSR_DB_TYPE_NCB,	64,	48},
+	{"CIU_SOFT_RST"                ,	   0x1070000000740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	49},
+	{"CIU_SUM1_IO0_INT"            ,	   0x1070000008600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"CIU_SUM1_IO1_INT"            ,	   0x1070000008608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"CIU_SUM1_PP0_IP2"            ,	   0x1070000008000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	51},
+	{"CIU_SUM1_PP1_IP2"            ,	   0x1070000008008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	51},
+	{"CIU_SUM1_PP2_IP2"            ,	   0x1070000008010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	51},
+	{"CIU_SUM1_PP3_IP2"            ,	   0x1070000008018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	51},
+	{"CIU_SUM1_PP0_IP3"            ,	   0x1070000008200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	52},
+	{"CIU_SUM1_PP1_IP3"            ,	   0x1070000008208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	52},
+	{"CIU_SUM1_PP2_IP3"            ,	   0x1070000008210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	52},
+	{"CIU_SUM1_PP3_IP3"            ,	   0x1070000008218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	52},
+	{"CIU_SUM1_PP0_IP4"            ,	   0x1070000008400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	53},
+	{"CIU_SUM1_PP1_IP4"            ,	   0x1070000008408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	53},
+	{"CIU_SUM1_PP2_IP4"            ,	   0x1070000008410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	53},
+	{"CIU_SUM1_PP3_IP4"            ,	   0x1070000008418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	53},
+	{"CIU_SUM2_IO0_INT"            ,	   0x1070000008e00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	54},
+	{"CIU_SUM2_IO1_INT"            ,	   0x1070000008e08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	54},
+	{"CIU_SUM2_PP0_IP2"            ,	   0x1070000008800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	55},
+	{"CIU_SUM2_PP1_IP2"            ,	   0x1070000008808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	55},
+	{"CIU_SUM2_PP2_IP2"            ,	   0x1070000008810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	55},
+	{"CIU_SUM2_PP3_IP2"            ,	   0x1070000008818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	55},
+	{"CIU_SUM2_PP0_IP3"            ,	   0x1070000008a00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	56},
+	{"CIU_SUM2_PP1_IP3"            ,	   0x1070000008a08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	56},
+	{"CIU_SUM2_PP2_IP3"            ,	   0x1070000008a10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	56},
+	{"CIU_SUM2_PP3_IP3"            ,	   0x1070000008a18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	56},
+	{"CIU_SUM2_PP0_IP4"            ,	   0x1070000008c00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	57},
+	{"CIU_SUM2_PP1_IP4"            ,	   0x1070000008c08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	57},
+	{"CIU_SUM2_PP2_IP4"            ,	   0x1070000008c10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	57},
+	{"CIU_SUM2_PP3_IP4"            ,	   0x1070000008c18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	57},
+	{"CIU_TIM0"                    ,	   0x1070000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	58},
+	{"CIU_TIM1"                    ,	   0x1070000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	58},
+	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	58},
+	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	58},
+	{"CIU_TIM4"                    ,	   0x10700000004a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	58},
+	{"CIU_TIM5"                    ,	   0x10700000004a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	58},
+	{"CIU_TIM6"                    ,	   0x10700000004b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	58},
+	{"CIU_TIM7"                    ,	   0x10700000004b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	58},
+	{"CIU_TIM8"                    ,	   0x10700000004c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	58},
+	{"CIU_TIM9"                    ,	   0x10700000004c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	58},
+	{"CIU_TIM_MULTI_CAST"          ,	   0x107000000c200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	59},
+	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	60},
+	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	60},
+	{"CIU_WDOG2"                   ,	   0x1070000000510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	60},
+	{"CIU_WDOG3"                   ,	   0x1070000000518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	60},
+	{"DPI_BIST_STATUS"             ,	   0x1df0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	61},
+	{"DPI_CTL"                     ,	   0x1df0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	62},
+	{"DPI_DMA0_COUNTS"             ,	   0x1df0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	63},
+	{"DPI_DMA1_COUNTS"             ,	   0x1df0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	63},
+	{"DPI_DMA2_COUNTS"             ,	   0x1df0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	63},
+	{"DPI_DMA3_COUNTS"             ,	   0x1df0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	63},
+	{"DPI_DMA4_COUNTS"             ,	   0x1df0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	63},
+	{"DPI_DMA5_COUNTS"             ,	   0x1df0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	63},
+	{"DPI_DMA6_COUNTS"             ,	   0x1df0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	63},
+	{"DPI_DMA7_COUNTS"             ,	   0x1df0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	63},
+	{"DPI_DMA0_DBELL"              ,	   0x1df0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	64},
+	{"DPI_DMA1_DBELL"              ,	   0x1df0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	64},
+	{"DPI_DMA2_DBELL"              ,	   0x1df0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	64},
+	{"DPI_DMA3_DBELL"              ,	   0x1df0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	64},
+	{"DPI_DMA4_DBELL"              ,	   0x1df0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	64},
+	{"DPI_DMA5_DBELL"              ,	   0x1df0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	64},
+	{"DPI_DMA6_DBELL"              ,	   0x1df0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	64},
+	{"DPI_DMA7_DBELL"              ,	   0x1df0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	64},
+	{"DPI_DMA0_ERR_RSP_STATUS"     ,	   0x1df0000000a80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	65},
+	{"DPI_DMA1_ERR_RSP_STATUS"     ,	   0x1df0000000a88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	65},
+	{"DPI_DMA2_ERR_RSP_STATUS"     ,	   0x1df0000000a90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	65},
+	{"DPI_DMA3_ERR_RSP_STATUS"     ,	   0x1df0000000a98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	65},
+	{"DPI_DMA4_ERR_RSP_STATUS"     ,	   0x1df0000000aa0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	65},
+	{"DPI_DMA5_ERR_RSP_STATUS"     ,	   0x1df0000000aa8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	65},
+	{"DPI_DMA6_ERR_RSP_STATUS"     ,	   0x1df0000000ab0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	65},
+	{"DPI_DMA7_ERR_RSP_STATUS"     ,	   0x1df0000000ab8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	65},
+	{"DPI_DMA0_IBUFF_SADDR"        ,	   0x1df0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	66},
+	{"DPI_DMA1_IBUFF_SADDR"        ,	   0x1df0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	66},
+	{"DPI_DMA2_IBUFF_SADDR"        ,	   0x1df0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	66},
+	{"DPI_DMA3_IBUFF_SADDR"        ,	   0x1df0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	66},
+	{"DPI_DMA4_IBUFF_SADDR"        ,	   0x1df00000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	66},
+	{"DPI_DMA5_IBUFF_SADDR"        ,	   0x1df00000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	66},
+	{"DPI_DMA6_IBUFF_SADDR"        ,	   0x1df00000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	66},
+	{"DPI_DMA7_IBUFF_SADDR"        ,	   0x1df00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	66},
+	{"DPI_DMA0_IFLIGHT"            ,	   0x1df0000000a00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	67},
+	{"DPI_DMA1_IFLIGHT"            ,	   0x1df0000000a08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	67},
+	{"DPI_DMA2_IFLIGHT"            ,	   0x1df0000000a10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	67},
+	{"DPI_DMA3_IFLIGHT"            ,	   0x1df0000000a18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	67},
+	{"DPI_DMA4_IFLIGHT"            ,	   0x1df0000000a20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	67},
+	{"DPI_DMA5_IFLIGHT"            ,	   0x1df0000000a28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	67},
+	{"DPI_DMA6_IFLIGHT"            ,	   0x1df0000000a30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	67},
+	{"DPI_DMA7_IFLIGHT"            ,	   0x1df0000000a38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	67},
+	{"DPI_DMA0_NADDR"              ,	   0x1df0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	68},
+	{"DPI_DMA1_NADDR"              ,	   0x1df0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	68},
+	{"DPI_DMA2_NADDR"              ,	   0x1df0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	68},
+	{"DPI_DMA3_NADDR"              ,	   0x1df0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	68},
+	{"DPI_DMA4_NADDR"              ,	   0x1df00000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	68},
+	{"DPI_DMA5_NADDR"              ,	   0x1df00000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	68},
+	{"DPI_DMA6_NADDR"              ,	   0x1df00000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	68},
+	{"DPI_DMA7_NADDR"              ,	   0x1df00000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	68},
+	{"DPI_DMA0_REQBNK0"            ,	   0x1df0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	69},
+	{"DPI_DMA1_REQBNK0"            ,	   0x1df0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	69},
+	{"DPI_DMA2_REQBNK0"            ,	   0x1df0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	69},
+	{"DPI_DMA3_REQBNK0"            ,	   0x1df0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	69},
+	{"DPI_DMA4_REQBNK0"            ,	   0x1df0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	69},
+	{"DPI_DMA5_REQBNK0"            ,	   0x1df0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	69},
+	{"DPI_DMA6_REQBNK0"            ,	   0x1df0000000430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	69},
+	{"DPI_DMA7_REQBNK0"            ,	   0x1df0000000438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	69},
+	{"DPI_DMA0_REQBNK1"            ,	   0x1df0000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	70},
+	{"DPI_DMA1_REQBNK1"            ,	   0x1df0000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	70},
+	{"DPI_DMA2_REQBNK1"            ,	   0x1df0000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	70},
+	{"DPI_DMA3_REQBNK1"            ,	   0x1df0000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	70},
+	{"DPI_DMA4_REQBNK1"            ,	   0x1df00000004a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	70},
+	{"DPI_DMA5_REQBNK1"            ,	   0x1df00000004a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	70},
+	{"DPI_DMA6_REQBNK1"            ,	   0x1df00000004b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	70},
+	{"DPI_DMA7_REQBNK1"            ,	   0x1df00000004b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	70},
+	{"DPI_DMA_CONTROL"             ,	   0x1df0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	71},
+	{"DPI_DMA_ENG0_EN"             ,	   0x1df0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
+	{"DPI_DMA_ENG1_EN"             ,	   0x1df0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
+	{"DPI_DMA_ENG2_EN"             ,	   0x1df0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
+	{"DPI_DMA_ENG3_EN"             ,	   0x1df0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
+	{"DPI_DMA_ENG4_EN"             ,	   0x1df00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
+	{"DPI_DMA_ENG5_EN"             ,	   0x1df00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
+	{"DPI_DMA_PP0_CNT"             ,	   0x1df0000000b00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"DPI_DMA_PP1_CNT"             ,	   0x1df0000000b08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"DPI_DMA_PP2_CNT"             ,	   0x1df0000000b10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"DPI_DMA_PP3_CNT"             ,	   0x1df0000000b18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"DPI_ENG0_BUF"                ,	   0x1df0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"DPI_ENG1_BUF"                ,	   0x1df0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"DPI_ENG2_BUF"                ,	   0x1df0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"DPI_ENG3_BUF"                ,	   0x1df0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"DPI_ENG4_BUF"                ,	   0x1df00000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"DPI_ENG5_BUF"                ,	   0x1df00000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"DPI_INFO_REG"                ,	   0x1df0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"DPI_INT_EN"                  ,	   0x1df0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"DPI_INT_REG"                 ,	   0x1df0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"DPI_NCB0_CFG"                ,	   0x1df0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"DPI_PINT_INFO"               ,	   0x1df0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"DPI_PKT_ERR_RSP"             ,	   0x1df0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"DPI_REQ_ERR_RSP"             ,	   0x1df0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"DPI_REQ_ERR_RSP_EN"          ,	   0x1df0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"DPI_REQ_ERR_RST"             ,	   0x1df0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"DPI_REQ_ERR_RST_EN"          ,	   0x1df0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"DPI_REQ_ERR_SKIP_COMP"       ,	   0x1df0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"DPI_REQ_GBL_EN"              ,	   0x1df0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"DPI_SLI_PRT0_CFG"            ,	   0x1df0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"DPI_SLI_PRT1_CFG"            ,	   0x1df0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"DPI_SLI_PRT0_ERR"            ,	   0x1df0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"DPI_SLI_PRT1_ERR"            ,	   0x1df0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"DPI_SLI_PRT0_ERR_INFO"       ,	   0x1df0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"DPI_SLI_PRT1_ERR_INFO"       ,	   0x1df0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"ENDOR_ADMA_AUTO_CLK_GATE"    ,	   0x10f0000844004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	90},
+	{"ENDOR_ADMA_AXI_RSPCODE"      ,	   0x10f0000844050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	91},
+	{"ENDOR_ADMA_AXI_SIGNAL"       ,	   0x10f0000844084ull,	CVMX_CSR_DB_TYPE_NCB,	32,	92},
+	{"ENDOR_ADMA_AXIERR_INTR"      ,	   0x10f0000844044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	93},
+	{"ENDOR_ADMA_DMA0_ADDR_HI"     ,	   0x10f000084410cull,	CVMX_CSR_DB_TYPE_NCB,	32,	94},
+	{"ENDOR_ADMA_DMA1_ADDR_HI"     ,	   0x10f000084411cull,	CVMX_CSR_DB_TYPE_NCB,	32,	94},
+	{"ENDOR_ADMA_DMA2_ADDR_HI"     ,	   0x10f000084412cull,	CVMX_CSR_DB_TYPE_NCB,	32,	94},
+	{"ENDOR_ADMA_DMA3_ADDR_HI"     ,	   0x10f000084413cull,	CVMX_CSR_DB_TYPE_NCB,	32,	94},
+	{"ENDOR_ADMA_DMA4_ADDR_HI"     ,	   0x10f000084414cull,	CVMX_CSR_DB_TYPE_NCB,	32,	94},
+	{"ENDOR_ADMA_DMA5_ADDR_HI"     ,	   0x10f000084415cull,	CVMX_CSR_DB_TYPE_NCB,	32,	94},
+	{"ENDOR_ADMA_DMA6_ADDR_HI"     ,	   0x10f000084416cull,	CVMX_CSR_DB_TYPE_NCB,	32,	94},
+	{"ENDOR_ADMA_DMA7_ADDR_HI"     ,	   0x10f000084417cull,	CVMX_CSR_DB_TYPE_NCB,	32,	94},
+	{"ENDOR_ADMA_DMA0_ADDR_LO"     ,	   0x10f0000844108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	95},
+	{"ENDOR_ADMA_DMA1_ADDR_LO"     ,	   0x10f0000844118ull,	CVMX_CSR_DB_TYPE_NCB,	32,	95},
+	{"ENDOR_ADMA_DMA2_ADDR_LO"     ,	   0x10f0000844128ull,	CVMX_CSR_DB_TYPE_NCB,	32,	95},
+	{"ENDOR_ADMA_DMA3_ADDR_LO"     ,	   0x10f0000844138ull,	CVMX_CSR_DB_TYPE_NCB,	32,	95},
+	{"ENDOR_ADMA_DMA4_ADDR_LO"     ,	   0x10f0000844148ull,	CVMX_CSR_DB_TYPE_NCB,	32,	95},
+	{"ENDOR_ADMA_DMA5_ADDR_LO"     ,	   0x10f0000844158ull,	CVMX_CSR_DB_TYPE_NCB,	32,	95},
+	{"ENDOR_ADMA_DMA6_ADDR_LO"     ,	   0x10f0000844168ull,	CVMX_CSR_DB_TYPE_NCB,	32,	95},
+	{"ENDOR_ADMA_DMA7_ADDR_LO"     ,	   0x10f0000844178ull,	CVMX_CSR_DB_TYPE_NCB,	32,	95},
+	{"ENDOR_ADMA_DMA0_CFG"         ,	   0x10f0000844100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	96},
+	{"ENDOR_ADMA_DMA1_CFG"         ,	   0x10f0000844110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	96},
+	{"ENDOR_ADMA_DMA2_CFG"         ,	   0x10f0000844120ull,	CVMX_CSR_DB_TYPE_NCB,	32,	96},
+	{"ENDOR_ADMA_DMA3_CFG"         ,	   0x10f0000844130ull,	CVMX_CSR_DB_TYPE_NCB,	32,	96},
+	{"ENDOR_ADMA_DMA4_CFG"         ,	   0x10f0000844140ull,	CVMX_CSR_DB_TYPE_NCB,	32,	96},
+	{"ENDOR_ADMA_DMA5_CFG"         ,	   0x10f0000844150ull,	CVMX_CSR_DB_TYPE_NCB,	32,	96},
+	{"ENDOR_ADMA_DMA6_CFG"         ,	   0x10f0000844160ull,	CVMX_CSR_DB_TYPE_NCB,	32,	96},
+	{"ENDOR_ADMA_DMA7_CFG"         ,	   0x10f0000844170ull,	CVMX_CSR_DB_TYPE_NCB,	32,	96},
+	{"ENDOR_ADMA_DMA0_SIZE"        ,	   0x10f0000844104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	97},
+	{"ENDOR_ADMA_DMA1_SIZE"        ,	   0x10f0000844114ull,	CVMX_CSR_DB_TYPE_NCB,	32,	97},
+	{"ENDOR_ADMA_DMA2_SIZE"        ,	   0x10f0000844124ull,	CVMX_CSR_DB_TYPE_NCB,	32,	97},
+	{"ENDOR_ADMA_DMA3_SIZE"        ,	   0x10f0000844134ull,	CVMX_CSR_DB_TYPE_NCB,	32,	97},
+	{"ENDOR_ADMA_DMA4_SIZE"        ,	   0x10f0000844144ull,	CVMX_CSR_DB_TYPE_NCB,	32,	97},
+	{"ENDOR_ADMA_DMA5_SIZE"        ,	   0x10f0000844154ull,	CVMX_CSR_DB_TYPE_NCB,	32,	97},
+	{"ENDOR_ADMA_DMA6_SIZE"        ,	   0x10f0000844164ull,	CVMX_CSR_DB_TYPE_NCB,	32,	97},
+	{"ENDOR_ADMA_DMA7_SIZE"        ,	   0x10f0000844174ull,	CVMX_CSR_DB_TYPE_NCB,	32,	97},
+	{"ENDOR_ADMA_DMA_PRIORITY"     ,	   0x10f0000844080ull,	CVMX_CSR_DB_TYPE_NCB,	32,	98},
+	{"ENDOR_ADMA_DMA_RESET"        ,	   0x10f0000844008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	99},
+	{"ENDOR_ADMA_DMADONE_INTR"     ,	   0x10f0000844040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	100},
+	{"ENDOR_ADMA_INTR_DIS"         ,	   0x10f000084404cull,	CVMX_CSR_DB_TYPE_NCB,	32,	101},
+	{"ENDOR_ADMA_INTR_ENB"         ,	   0x10f0000844048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	102},
+	{"ENDOR_ADMA_MODULE_STATUS"    ,	   0x10f0000844000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	103},
+	{"ENDOR_INTC_CNTL_HI0"         ,	   0x10f00008201e4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	104},
+	{"ENDOR_INTC_CNTL_HI1"         ,	   0x10f00008201ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	104},
+	{"ENDOR_INTC_CNTL_LO0"         ,	   0x10f00008201e0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	105},
+	{"ENDOR_INTC_CNTL_LO1"         ,	   0x10f00008201e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	105},
+	{"ENDOR_INTC_INDEX_HI0"        ,	   0x10f00008201a4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	106},
+	{"ENDOR_INTC_INDEX_HI1"        ,	   0x10f00008201acull,	CVMX_CSR_DB_TYPE_NCB,	32,	106},
+	{"ENDOR_INTC_INDEX_LO0"        ,	   0x10f00008201a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	107},
+	{"ENDOR_INTC_INDEX_LO1"        ,	   0x10f00008201a8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	107},
+	{"ENDOR_INTC_MISC_IDX_HI0"     ,	   0x10f0000820134ull,	CVMX_CSR_DB_TYPE_NCB,	32,	108},
+	{"ENDOR_INTC_MISC_IDX_HI1"     ,	   0x10f0000820174ull,	CVMX_CSR_DB_TYPE_NCB,	32,	108},
+	{"ENDOR_INTC_MISC_IDX_LO0"     ,	   0x10f0000820114ull,	CVMX_CSR_DB_TYPE_NCB,	32,	109},
+	{"ENDOR_INTC_MISC_IDX_LO1"     ,	   0x10f0000820154ull,	CVMX_CSR_DB_TYPE_NCB,	32,	109},
+	{"ENDOR_INTC_MISC_MASK_HI0"    ,	   0x10f0000820034ull,	CVMX_CSR_DB_TYPE_NCB,	32,	110},
+	{"ENDOR_INTC_MISC_MASK_HI1"    ,	   0x10f0000820074ull,	CVMX_CSR_DB_TYPE_NCB,	32,	110},
+	{"ENDOR_INTC_MISC_MASK_LO0"    ,	   0x10f0000820014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	111},
+	{"ENDOR_INTC_MISC_MASK_LO1"    ,	   0x10f0000820054ull,	CVMX_CSR_DB_TYPE_NCB,	32,	111},
+	{"ENDOR_INTC_MISC_RINT"        ,	   0x10f0000820194ull,	CVMX_CSR_DB_TYPE_NCB,	32,	112},
+	{"ENDOR_INTC_MISC_STATUS_HI0"  ,	   0x10f00008200b4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	113},
+	{"ENDOR_INTC_MISC_STATUS_HI1"  ,	   0x10f00008200f4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	113},
+	{"ENDOR_INTC_MISC_STATUS_LO0"  ,	   0x10f0000820094ull,	CVMX_CSR_DB_TYPE_NCB,	32,	114},
+	{"ENDOR_INTC_MISC_STATUS_LO1"  ,	   0x10f00008200d4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	114},
+	{"ENDOR_INTC_RD_IDX_HI0"       ,	   0x10f0000820124ull,	CVMX_CSR_DB_TYPE_NCB,	32,	115},
+	{"ENDOR_INTC_RD_IDX_HI1"       ,	   0x10f0000820164ull,	CVMX_CSR_DB_TYPE_NCB,	32,	115},
+	{"ENDOR_INTC_RD_IDX_LO0"       ,	   0x10f0000820104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	116},
+	{"ENDOR_INTC_RD_IDX_LO1"       ,	   0x10f0000820144ull,	CVMX_CSR_DB_TYPE_NCB,	32,	116},
+	{"ENDOR_INTC_RD_MASK_HI0"      ,	   0x10f0000820024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	117},
+	{"ENDOR_INTC_RD_MASK_HI1"      ,	   0x10f0000820064ull,	CVMX_CSR_DB_TYPE_NCB,	32,	117},
+	{"ENDOR_INTC_RD_MASK_LO0"      ,	   0x10f0000820004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	118},
+	{"ENDOR_INTC_RD_MASK_LO1"      ,	   0x10f0000820044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	118},
+	{"ENDOR_INTC_RD_RINT"          ,	   0x10f0000820184ull,	CVMX_CSR_DB_TYPE_NCB,	32,	119},
+	{"ENDOR_INTC_RD_STATUS_HI0"    ,	   0x10f00008200a4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	120},
+	{"ENDOR_INTC_RD_STATUS_HI1"    ,	   0x10f00008200e4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	120},
+	{"ENDOR_INTC_RD_STATUS_LO0"    ,	   0x10f0000820084ull,	CVMX_CSR_DB_TYPE_NCB,	32,	121},
+	{"ENDOR_INTC_RD_STATUS_LO1"    ,	   0x10f00008200c4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	121},
+	{"ENDOR_INTC_RDQ_IDX_HI0"      ,	   0x10f000082012cull,	CVMX_CSR_DB_TYPE_NCB,	32,	122},
+	{"ENDOR_INTC_RDQ_IDX_HI1"      ,	   0x10f000082016cull,	CVMX_CSR_DB_TYPE_NCB,	32,	122},
+	{"ENDOR_INTC_RDQ_IDX_LO0"      ,	   0x10f000082010cull,	CVMX_CSR_DB_TYPE_NCB,	32,	123},
+	{"ENDOR_INTC_RDQ_IDX_LO1"      ,	   0x10f000082014cull,	CVMX_CSR_DB_TYPE_NCB,	32,	123},
+	{"ENDOR_INTC_RDQ_MASK_HI0"     ,	   0x10f000082002cull,	CVMX_CSR_DB_TYPE_NCB,	32,	124},
+	{"ENDOR_INTC_RDQ_MASK_HI1"     ,	   0x10f000082006cull,	CVMX_CSR_DB_TYPE_NCB,	32,	124},
+	{"ENDOR_INTC_RDQ_MASK_LO0"     ,	   0x10f000082000cull,	CVMX_CSR_DB_TYPE_NCB,	32,	125},
+	{"ENDOR_INTC_RDQ_MASK_LO1"     ,	   0x10f000082004cull,	CVMX_CSR_DB_TYPE_NCB,	32,	125},
+	{"ENDOR_INTC_RDQ_RINT"         ,	   0x10f000082018cull,	CVMX_CSR_DB_TYPE_NCB,	32,	126},
+	{"ENDOR_INTC_RDQ_STATUS_HI0"   ,	   0x10f00008200acull,	CVMX_CSR_DB_TYPE_NCB,	32,	127},
+	{"ENDOR_INTC_RDQ_STATUS_HI1"   ,	   0x10f00008200ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	127},
+	{"ENDOR_INTC_RDQ_STATUS_LO0"   ,	   0x10f000082008cull,	CVMX_CSR_DB_TYPE_NCB,	32,	128},
+	{"ENDOR_INTC_RDQ_STATUS_LO1"   ,	   0x10f00008200ccull,	CVMX_CSR_DB_TYPE_NCB,	32,	128},
+	{"ENDOR_INTC_STAT_HI0"         ,	   0x10f00008201c4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	129},
+	{"ENDOR_INTC_STAT_HI1"         ,	   0x10f00008201ccull,	CVMX_CSR_DB_TYPE_NCB,	32,	129},
+	{"ENDOR_INTC_STAT_LO0"         ,	   0x10f00008201c0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	130},
+	{"ENDOR_INTC_STAT_LO1"         ,	   0x10f00008201c8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	130},
+	{"ENDOR_INTC_SW_IDX_HI0"       ,	   0x10f0000820130ull,	CVMX_CSR_DB_TYPE_NCB,	32,	131},
+	{"ENDOR_INTC_SW_IDX_HI1"       ,	   0x10f0000820170ull,	CVMX_CSR_DB_TYPE_NCB,	32,	131},
+	{"ENDOR_INTC_SW_IDX_LO0"       ,	   0x10f0000820110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	132},
+	{"ENDOR_INTC_SW_IDX_LO1"       ,	   0x10f0000820150ull,	CVMX_CSR_DB_TYPE_NCB,	32,	132},
+	{"ENDOR_INTC_SW_MASK_HI0"      ,	   0x10f0000820030ull,	CVMX_CSR_DB_TYPE_NCB,	32,	133},
+	{"ENDOR_INTC_SW_MASK_HI1"      ,	   0x10f0000820070ull,	CVMX_CSR_DB_TYPE_NCB,	32,	133},
+	{"ENDOR_INTC_SW_MASK_LO0"      ,	   0x10f0000820010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	134},
+	{"ENDOR_INTC_SW_MASK_LO1"      ,	   0x10f0000820050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	134},
+	{"ENDOR_INTC_SW_RINT"          ,	   0x10f0000820190ull,	CVMX_CSR_DB_TYPE_NCB,	32,	135},
+	{"ENDOR_INTC_SW_STATUS_HI0"    ,	   0x10f00008200b0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	136},
+	{"ENDOR_INTC_SW_STATUS_HI1"    ,	   0x10f00008200f0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	136},
+	{"ENDOR_INTC_SW_STATUS_LO0"    ,	   0x10f0000820090ull,	CVMX_CSR_DB_TYPE_NCB,	32,	137},
+	{"ENDOR_INTC_SW_STATUS_LO1"    ,	   0x10f00008200d0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	137},
+	{"ENDOR_INTC_SWCLR"            ,	   0x10f0000820204ull,	CVMX_CSR_DB_TYPE_NCB,	32,	138},
+	{"ENDOR_INTC_SWSET"            ,	   0x10f0000820200ull,	CVMX_CSR_DB_TYPE_NCB,	32,	139},
+	{"ENDOR_INTC_WR_IDX_HI0"       ,	   0x10f0000820120ull,	CVMX_CSR_DB_TYPE_NCB,	32,	140},
+	{"ENDOR_INTC_WR_IDX_HI1"       ,	   0x10f0000820160ull,	CVMX_CSR_DB_TYPE_NCB,	32,	140},
+	{"ENDOR_INTC_WR_IDX_LO0"       ,	   0x10f0000820100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	141},
+	{"ENDOR_INTC_WR_IDX_LO1"       ,	   0x10f0000820140ull,	CVMX_CSR_DB_TYPE_NCB,	32,	141},
+	{"ENDOR_INTC_WR_MASK_HI0"      ,	   0x10f0000820020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	142},
+	{"ENDOR_INTC_WR_MASK_HI1"      ,	   0x10f0000820060ull,	CVMX_CSR_DB_TYPE_NCB,	32,	142},
+	{"ENDOR_INTC_WR_MASK_LO0"      ,	   0x10f0000820000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	143},
+	{"ENDOR_INTC_WR_MASK_LO1"      ,	   0x10f0000820040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	143},
+	{"ENDOR_INTC_WR_RINT"          ,	   0x10f0000820180ull,	CVMX_CSR_DB_TYPE_NCB,	32,	144},
+	{"ENDOR_INTC_WR_STATUS_HI0"    ,	   0x10f00008200a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	145},
+	{"ENDOR_INTC_WR_STATUS_HI1"    ,	   0x10f00008200e0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	145},
+	{"ENDOR_INTC_WR_STATUS_LO0"    ,	   0x10f0000820080ull,	CVMX_CSR_DB_TYPE_NCB,	32,	146},
+	{"ENDOR_INTC_WR_STATUS_LO1"    ,	   0x10f00008200c0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	146},
+	{"ENDOR_INTC_WRQ_IDX_HI0"      ,	   0x10f0000820128ull,	CVMX_CSR_DB_TYPE_NCB,	32,	147},
+	{"ENDOR_INTC_WRQ_IDX_HI1"      ,	   0x10f0000820168ull,	CVMX_CSR_DB_TYPE_NCB,	32,	147},
+	{"ENDOR_INTC_WRQ_IDX_LO0"      ,	   0x10f0000820108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	148},
+	{"ENDOR_INTC_WRQ_IDX_LO1"      ,	   0x10f0000820148ull,	CVMX_CSR_DB_TYPE_NCB,	32,	148},
+	{"ENDOR_INTC_WRQ_MASK_HI0"     ,	   0x10f0000820028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	149},
+	{"ENDOR_INTC_WRQ_MASK_HI1"     ,	   0x10f0000820068ull,	CVMX_CSR_DB_TYPE_NCB,	32,	149},
+	{"ENDOR_INTC_WRQ_MASK_LO0"     ,	   0x10f0000820008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	150},
+	{"ENDOR_INTC_WRQ_MASK_LO1"     ,	   0x10f0000820048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	150},
+	{"ENDOR_INTC_WRQ_RINT"         ,	   0x10f0000820188ull,	CVMX_CSR_DB_TYPE_NCB,	32,	151},
+	{"ENDOR_INTC_WRQ_STATUS_HI0"   ,	   0x10f00008200a8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	152},
+	{"ENDOR_INTC_WRQ_STATUS_HI1"   ,	   0x10f00008200e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	152},
+	{"ENDOR_INTC_WRQ_STATUS_LO0"   ,	   0x10f0000820088ull,	CVMX_CSR_DB_TYPE_NCB,	32,	153},
+	{"ENDOR_INTC_WRQ_STATUS_LO1"   ,	   0x10f00008200c8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	153},
+	{"ENDOR_OFS_HMM_CBUF_END_ADDR0",	   0x10f0000832054ull,	CVMX_CSR_DB_TYPE_NCB,	32,	154},
+	{"ENDOR_OFS_HMM_CBUF_END_ADDR1",	   0x10f000083205cull,	CVMX_CSR_DB_TYPE_NCB,	32,	155},
+	{"ENDOR_OFS_HMM_CBUF_END_ADDR2",	   0x10f0000832064ull,	CVMX_CSR_DB_TYPE_NCB,	32,	156},
+	{"ENDOR_OFS_HMM_CBUF_END_ADDR3",	   0x10f000083206cull,	CVMX_CSR_DB_TYPE_NCB,	32,	157},
+	{"ENDOR_OFS_HMM_CBUF_START_ADDR0",	   0x10f0000832050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	158},
+	{"ENDOR_OFS_HMM_CBUF_START_ADDR1",	   0x10f0000832058ull,	CVMX_CSR_DB_TYPE_NCB,	32,	159},
+	{"ENDOR_OFS_HMM_CBUF_START_ADDR2",	   0x10f0000832060ull,	CVMX_CSR_DB_TYPE_NCB,	32,	160},
+	{"ENDOR_OFS_HMM_CBUF_START_ADDR3",	   0x10f0000832068ull,	CVMX_CSR_DB_TYPE_NCB,	32,	161},
+	{"ENDOR_OFS_HMM_INTR_CLEAR"    ,	   0x10f0000832018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	162},
+	{"ENDOR_OFS_HMM_INTR_ENB"      ,	   0x10f000083201cull,	CVMX_CSR_DB_TYPE_NCB,	32,	163},
+	{"ENDOR_OFS_HMM_INTR_RSTATUS"  ,	   0x10f0000832014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	164},
+	{"ENDOR_OFS_HMM_INTR_STATUS"   ,	   0x10f0000832010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	165},
+	{"ENDOR_OFS_HMM_INTR_TEST"     ,	   0x10f0000832020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	166},
+	{"ENDOR_OFS_HMM_MODE"          ,	   0x10f0000832004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	167},
+	{"ENDOR_OFS_HMM_START_ADDR0"   ,	   0x10f0000832030ull,	CVMX_CSR_DB_TYPE_NCB,	32,	168},
+	{"ENDOR_OFS_HMM_START_ADDR1"   ,	   0x10f0000832034ull,	CVMX_CSR_DB_TYPE_NCB,	32,	169},
+	{"ENDOR_OFS_HMM_START_ADDR2"   ,	   0x10f0000832038ull,	CVMX_CSR_DB_TYPE_NCB,	32,	170},
+	{"ENDOR_OFS_HMM_START_ADDR3"   ,	   0x10f000083203cull,	CVMX_CSR_DB_TYPE_NCB,	32,	171},
+	{"ENDOR_OFS_HMM_STATUS"        ,	   0x10f0000832000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	172},
+	{"ENDOR_OFS_HMM_XFER_CNT"      ,	   0x10f000083202cull,	CVMX_CSR_DB_TYPE_NCB,	32,	173},
+	{"ENDOR_OFS_HMM_XFER_Q_STATUS" ,	   0x10f000083200cull,	CVMX_CSR_DB_TYPE_NCB,	32,	174},
+	{"ENDOR_OFS_HMM_XFER_START"    ,	   0x10f0000832028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	175},
+	{"ENDOR_RFIF_1PPS_GEN_CFG"     ,	   0x10f00008680ccull,	CVMX_CSR_DB_TYPE_NCB,	32,	176},
+	{"ENDOR_RFIF_1PPS_SAMPLE_CNT_OFFSET",	   0x10f0000868104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	177},
+	{"ENDOR_RFIF_1PPS_VERIF_GEN_EN",	   0x10f0000868110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	178},
+	{"ENDOR_RFIF_1PPS_VERIF_SCNT"  ,	   0x10f0000868114ull,	CVMX_CSR_DB_TYPE_NCB,	32,	179},
+	{"ENDOR_RFIF_CONF"             ,	   0x10f0000868010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	180},
+	{"ENDOR_RFIF_CONF2"            ,	   0x10f000086801cull,	CVMX_CSR_DB_TYPE_NCB,	32,	181},
+	{"ENDOR_RFIF_DSP1_GPIO"        ,	   0x10f00008684c0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	182},
+	{"ENDOR_RFIF_DSP_RX_HIS"       ,	   0x10f000086840cull,	CVMX_CSR_DB_TYPE_NCB,	32,	183},
+	{"ENDOR_RFIF_DSP_RX_ISM"       ,	   0x10f0000868400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	184},
+	{"ENDOR_RFIF_FIRS_ENABLE"      ,	   0x10f00008684c4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	185},
+	{"ENDOR_RFIF_FRAME_CNT"        ,	   0x10f0000868030ull,	CVMX_CSR_DB_TYPE_NCB,	32,	186},
+	{"ENDOR_RFIF_FRAME_L"          ,	   0x10f0000868014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	187},
+	{"ENDOR_RFIF_GPIO_0"           ,	   0x10f0000868418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	188},
+	{"ENDOR_RFIF_GPIO_1"           ,	   0x10f000086841cull,	CVMX_CSR_DB_TYPE_NCB,	32,	188},
+	{"ENDOR_RFIF_GPIO_2"           ,	   0x10f0000868420ull,	CVMX_CSR_DB_TYPE_NCB,	32,	188},
+	{"ENDOR_RFIF_GPIO_3"           ,	   0x10f0000868424ull,	CVMX_CSR_DB_TYPE_NCB,	32,	188},
+	{"ENDOR_RFIF_MAX_SAMPLE_ADJ"   ,	   0x10f00008680dcull,	CVMX_CSR_DB_TYPE_NCB,	32,	189},
+	{"ENDOR_RFIF_MIN_SAMPLE_ADJ"   ,	   0x10f00008680e0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	190},
+	{"ENDOR_RFIF_NUM_RX_WIN"       ,	   0x10f0000868018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	191},
+	{"ENDOR_RFIF_PWM_ENABLE"       ,	   0x10f0000868180ull,	CVMX_CSR_DB_TYPE_NCB,	32,	192},
+	{"ENDOR_RFIF_PWM_HIGH_TIME"    ,	   0x10f0000868184ull,	CVMX_CSR_DB_TYPE_NCB,	32,	193},
+	{"ENDOR_RFIF_PWM_LOW_TIME"     ,	   0x10f0000868188ull,	CVMX_CSR_DB_TYPE_NCB,	32,	194},
+	{"ENDOR_RFIF_RD_TIMER64_LSB"   ,	   0x10f00008681acull,	CVMX_CSR_DB_TYPE_NCB,	32,	195},
+	{"ENDOR_RFIF_RD_TIMER64_MSB"   ,	   0x10f00008681b0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	196},
+	{"ENDOR_RFIF_REAL_TIME_TIMER"  ,	   0x10f00008680c8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	197},
+	{"ENDOR_RFIF_RF_CLK_TIMER"     ,	   0x10f0000868194ull,	CVMX_CSR_DB_TYPE_NCB,	32,	198},
+	{"ENDOR_RFIF_RF_CLK_TIMER_EN"  ,	   0x10f0000868198ull,	CVMX_CSR_DB_TYPE_NCB,	32,	199},
+	{"ENDOR_RFIF_RX_CORRECT_ADJ"   ,	   0x10f00008680e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	200},
+	{"ENDOR_RFIF_RX_DIV_STATUS"    ,	   0x10f0000868004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	201},
+	{"ENDOR_RFIF_RX_FIFO_CNT"      ,	   0x10f0000868500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	202},
+	{"ENDOR_RFIF_RX_IF_CFG"        ,	   0x10f0000868038ull,	CVMX_CSR_DB_TYPE_NCB,	32,	203},
+	{"ENDOR_RFIF_RX_LEAD_LAG"      ,	   0x10f0000868020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	204},
+	{"ENDOR_RFIF_RX_LOAD_CFG"      ,	   0x10f0000868508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	205},
+	{"ENDOR_RFIF_RX_OFFSET"        ,	   0x10f00008680d4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	206},
+	{"ENDOR_RFIF_RX_OFFSET_ADJ_SCNT",	   0x10f0000868108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	207},
+	{"ENDOR_RFIF_RX_STATUS"        ,	   0x10f0000868000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	208},
+	{"ENDOR_RFIF_RX_SYNC_SCNT"     ,	   0x10f00008680c4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	209},
+	{"ENDOR_RFIF_RX_SYNC_VALUE"    ,	   0x10f00008680c0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	210},
+	{"ENDOR_RFIF_RX_TH"            ,	   0x10f0000868410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	211},
+	{"ENDOR_RFIF_RX_TRANSFER_SIZE" ,	   0x10f000086850cull,	CVMX_CSR_DB_TYPE_NCB,	32,	212},
+	{"ENDOR_RFIF_RX_W_E0"          ,	   0x10f0000868084ull,	CVMX_CSR_DB_TYPE_NCB,	32,	213},
+	{"ENDOR_RFIF_RX_W_E1"          ,	   0x10f0000868088ull,	CVMX_CSR_DB_TYPE_NCB,	32,	213},
+	{"ENDOR_RFIF_RX_W_E2"          ,	   0x10f000086808cull,	CVMX_CSR_DB_TYPE_NCB,	32,	213},
+	{"ENDOR_RFIF_RX_W_E3"          ,	   0x10f0000868090ull,	CVMX_CSR_DB_TYPE_NCB,	32,	213},
+	{"ENDOR_RFIF_RX_W_S0"          ,	   0x10f0000868044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	214},
+	{"ENDOR_RFIF_RX_W_S1"          ,	   0x10f0000868048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	214},
+	{"ENDOR_RFIF_RX_W_S2"          ,	   0x10f000086804cull,	CVMX_CSR_DB_TYPE_NCB,	32,	214},
+	{"ENDOR_RFIF_RX_W_S3"          ,	   0x10f0000868050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	214},
+	{"ENDOR_RFIF_SAMPLE_ADJ_CFG"   ,	   0x10f00008680e4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	215},
+	{"ENDOR_RFIF_SAMPLE_ADJ_ERROR" ,	   0x10f0000868100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	216},
+	{"ENDOR_RFIF_SAMPLE_CNT"       ,	   0x10f0000868028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	217},
+	{"ENDOR_RFIF_SKIP_FRM_CNT_BITS",	   0x10f0000868444ull,	CVMX_CSR_DB_TYPE_NCB,	32,	218},
+	{"ENDOR_RFIF_SPI_0_LL"         ,	   0x10f0000868430ull,	CVMX_CSR_DB_TYPE_NCB,	32,	219},
+	{"ENDOR_RFIF_SPI_1_LL"         ,	   0x10f0000868434ull,	CVMX_CSR_DB_TYPE_NCB,	32,	219},
+	{"ENDOR_RFIF_SPI_2_LL"         ,	   0x10f0000868438ull,	CVMX_CSR_DB_TYPE_NCB,	32,	219},
+	{"ENDOR_RFIF_SPI_3_LL"         ,	   0x10f000086843cull,	CVMX_CSR_DB_TYPE_NCB,	32,	219},
+	{"ENDOR_RFIF_SPI_CMD_ATTR0"    ,	   0x10f0000868a00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR1"    ,	   0x10f0000868a04ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR2"    ,	   0x10f0000868a08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR3"    ,	   0x10f0000868a0cull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR4"    ,	   0x10f0000868a10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR5"    ,	   0x10f0000868a14ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR6"    ,	   0x10f0000868a18ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR7"    ,	   0x10f0000868a1cull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR8"    ,	   0x10f0000868a20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR9"    ,	   0x10f0000868a24ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR10"   ,	   0x10f0000868a28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR11"   ,	   0x10f0000868a2cull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR12"   ,	   0x10f0000868a30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR13"   ,	   0x10f0000868a34ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR14"   ,	   0x10f0000868a38ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR15"   ,	   0x10f0000868a3cull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR16"   ,	   0x10f0000868a40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR17"   ,	   0x10f0000868a44ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR18"   ,	   0x10f0000868a48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR19"   ,	   0x10f0000868a4cull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR20"   ,	   0x10f0000868a50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR21"   ,	   0x10f0000868a54ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR22"   ,	   0x10f0000868a58ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR23"   ,	   0x10f0000868a5cull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR24"   ,	   0x10f0000868a60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR25"   ,	   0x10f0000868a64ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR26"   ,	   0x10f0000868a68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR27"   ,	   0x10f0000868a6cull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR28"   ,	   0x10f0000868a70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR29"   ,	   0x10f0000868a74ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR30"   ,	   0x10f0000868a78ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR31"   ,	   0x10f0000868a7cull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR32"   ,	   0x10f0000868a80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR33"   ,	   0x10f0000868a84ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR34"   ,	   0x10f0000868a88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR35"   ,	   0x10f0000868a8cull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR36"   ,	   0x10f0000868a90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR37"   ,	   0x10f0000868a94ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR38"   ,	   0x10f0000868a98ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR39"   ,	   0x10f0000868a9cull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR40"   ,	   0x10f0000868aa0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR41"   ,	   0x10f0000868aa4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR42"   ,	   0x10f0000868aa8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR43"   ,	   0x10f0000868aacull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR44"   ,	   0x10f0000868ab0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR45"   ,	   0x10f0000868ab4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR46"   ,	   0x10f0000868ab8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR47"   ,	   0x10f0000868abcull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR48"   ,	   0x10f0000868ac0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR49"   ,	   0x10f0000868ac4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR50"   ,	   0x10f0000868ac8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR51"   ,	   0x10f0000868accull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR52"   ,	   0x10f0000868ad0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR53"   ,	   0x10f0000868ad4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR54"   ,	   0x10f0000868ad8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR55"   ,	   0x10f0000868adcull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR56"   ,	   0x10f0000868ae0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR57"   ,	   0x10f0000868ae4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR58"   ,	   0x10f0000868ae8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR59"   ,	   0x10f0000868aecull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR60"   ,	   0x10f0000868af0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR61"   ,	   0x10f0000868af4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR62"   ,	   0x10f0000868af8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMD_ATTR63"   ,	   0x10f0000868afcull,	CVMX_CSR_DB_TYPE_NCB,	32,	220},
+	{"ENDOR_RFIF_SPI_CMDS0"        ,	   0x10f0000868800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS1"        ,	   0x10f0000868804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS2"        ,	   0x10f0000868808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS3"        ,	   0x10f000086880cull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS4"        ,	   0x10f0000868810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS5"        ,	   0x10f0000868814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS6"        ,	   0x10f0000868818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS7"        ,	   0x10f000086881cull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS8"        ,	   0x10f0000868820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS9"        ,	   0x10f0000868824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS10"       ,	   0x10f0000868828ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS11"       ,	   0x10f000086882cull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS12"       ,	   0x10f0000868830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS13"       ,	   0x10f0000868834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS14"       ,	   0x10f0000868838ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS15"       ,	   0x10f000086883cull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS16"       ,	   0x10f0000868840ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS17"       ,	   0x10f0000868844ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS18"       ,	   0x10f0000868848ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS19"       ,	   0x10f000086884cull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS20"       ,	   0x10f0000868850ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS21"       ,	   0x10f0000868854ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS22"       ,	   0x10f0000868858ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS23"       ,	   0x10f000086885cull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS24"       ,	   0x10f0000868860ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS25"       ,	   0x10f0000868864ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS26"       ,	   0x10f0000868868ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS27"       ,	   0x10f000086886cull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS28"       ,	   0x10f0000868870ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS29"       ,	   0x10f0000868874ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS30"       ,	   0x10f0000868878ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS31"       ,	   0x10f000086887cull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS32"       ,	   0x10f0000868880ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS33"       ,	   0x10f0000868884ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS34"       ,	   0x10f0000868888ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS35"       ,	   0x10f000086888cull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS36"       ,	   0x10f0000868890ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS37"       ,	   0x10f0000868894ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS38"       ,	   0x10f0000868898ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS39"       ,	   0x10f000086889cull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS40"       ,	   0x10f00008688a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS41"       ,	   0x10f00008688a4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS42"       ,	   0x10f00008688a8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS43"       ,	   0x10f00008688acull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS44"       ,	   0x10f00008688b0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS45"       ,	   0x10f00008688b4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS46"       ,	   0x10f00008688b8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS47"       ,	   0x10f00008688bcull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS48"       ,	   0x10f00008688c0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS49"       ,	   0x10f00008688c4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS50"       ,	   0x10f00008688c8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS51"       ,	   0x10f00008688ccull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS52"       ,	   0x10f00008688d0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS53"       ,	   0x10f00008688d4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS54"       ,	   0x10f00008688d8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS55"       ,	   0x10f00008688dcull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS56"       ,	   0x10f00008688e0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS57"       ,	   0x10f00008688e4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS58"       ,	   0x10f00008688e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS59"       ,	   0x10f00008688ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS60"       ,	   0x10f00008688f0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS61"       ,	   0x10f00008688f4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS62"       ,	   0x10f00008688f8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CMDS63"       ,	   0x10f00008688fcull,	CVMX_CSR_DB_TYPE_NCB,	32,	221},
+	{"ENDOR_RFIF_SPI_CONF0"        ,	   0x10f0000868428ull,	CVMX_CSR_DB_TYPE_NCB,	32,	222},
+	{"ENDOR_RFIF_SPI_CONF1"        ,	   0x10f000086842cull,	CVMX_CSR_DB_TYPE_NCB,	32,	223},
+	{"ENDOR_RFIF_SPI_CTRL"         ,	   0x10f0000866008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	224},
+	{"ENDOR_RFIF_SPI_DIN0"         ,	   0x10f0000868900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN1"         ,	   0x10f0000868904ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN2"         ,	   0x10f0000868908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN3"         ,	   0x10f000086890cull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN4"         ,	   0x10f0000868910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN5"         ,	   0x10f0000868914ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN6"         ,	   0x10f0000868918ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN7"         ,	   0x10f000086891cull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN8"         ,	   0x10f0000868920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN9"         ,	   0x10f0000868924ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN10"        ,	   0x10f0000868928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN11"        ,	   0x10f000086892cull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN12"        ,	   0x10f0000868930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN13"        ,	   0x10f0000868934ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN14"        ,	   0x10f0000868938ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN15"        ,	   0x10f000086893cull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN16"        ,	   0x10f0000868940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN17"        ,	   0x10f0000868944ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN18"        ,	   0x10f0000868948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN19"        ,	   0x10f000086894cull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN20"        ,	   0x10f0000868950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN21"        ,	   0x10f0000868954ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN22"        ,	   0x10f0000868958ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN23"        ,	   0x10f000086895cull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN24"        ,	   0x10f0000868960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN25"        ,	   0x10f0000868964ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN26"        ,	   0x10f0000868968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN27"        ,	   0x10f000086896cull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN28"        ,	   0x10f0000868970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN29"        ,	   0x10f0000868974ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN30"        ,	   0x10f0000868978ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN31"        ,	   0x10f000086897cull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN32"        ,	   0x10f0000868980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN33"        ,	   0x10f0000868984ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN34"        ,	   0x10f0000868988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN35"        ,	   0x10f000086898cull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN36"        ,	   0x10f0000868990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN37"        ,	   0x10f0000868994ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN38"        ,	   0x10f0000868998ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN39"        ,	   0x10f000086899cull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN40"        ,	   0x10f00008689a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN41"        ,	   0x10f00008689a4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN42"        ,	   0x10f00008689a8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN43"        ,	   0x10f00008689acull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN44"        ,	   0x10f00008689b0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN45"        ,	   0x10f00008689b4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN46"        ,	   0x10f00008689b8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN47"        ,	   0x10f00008689bcull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN48"        ,	   0x10f00008689c0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN49"        ,	   0x10f00008689c4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN50"        ,	   0x10f00008689c8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN51"        ,	   0x10f00008689ccull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN52"        ,	   0x10f00008689d0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN53"        ,	   0x10f00008689d4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN54"        ,	   0x10f00008689d8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN55"        ,	   0x10f00008689dcull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN56"        ,	   0x10f00008689e0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN57"        ,	   0x10f00008689e4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN58"        ,	   0x10f00008689e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN59"        ,	   0x10f00008689ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN60"        ,	   0x10f00008689f0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN61"        ,	   0x10f00008689f4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN62"        ,	   0x10f00008689f8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_DIN63"        ,	   0x10f00008689fcull,	CVMX_CSR_DB_TYPE_NCB,	32,	225},
+	{"ENDOR_RFIF_SPI_RX_DATA"      ,	   0x10f0000866000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	226},
+	{"ENDOR_RFIF_SPI_STATUS"       ,	   0x10f0000866010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	227},
+	{"ENDOR_RFIF_SPI_TX_DATA"      ,	   0x10f0000866004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	228},
+	{"ENDOR_RFIF_TIMER64_CFG"      ,	   0x10f00008681a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	229},
+	{"ENDOR_RFIF_TIMER64_EN"       ,	   0x10f000086819cull,	CVMX_CSR_DB_TYPE_NCB,	32,	230},
+	{"ENDOR_RFIF_TTI_SCNT_INT0"    ,	   0x10f0000868140ull,	CVMX_CSR_DB_TYPE_NCB,	32,	231},
+	{"ENDOR_RFIF_TTI_SCNT_INT1"    ,	   0x10f0000868144ull,	CVMX_CSR_DB_TYPE_NCB,	32,	231},
+	{"ENDOR_RFIF_TTI_SCNT_INT2"    ,	   0x10f0000868148ull,	CVMX_CSR_DB_TYPE_NCB,	32,	231},
+	{"ENDOR_RFIF_TTI_SCNT_INT3"    ,	   0x10f000086814cull,	CVMX_CSR_DB_TYPE_NCB,	32,	231},
+	{"ENDOR_RFIF_TTI_SCNT_INT4"    ,	   0x10f0000868150ull,	CVMX_CSR_DB_TYPE_NCB,	32,	231},
+	{"ENDOR_RFIF_TTI_SCNT_INT5"    ,	   0x10f0000868154ull,	CVMX_CSR_DB_TYPE_NCB,	32,	231},
+	{"ENDOR_RFIF_TTI_SCNT_INT6"    ,	   0x10f0000868158ull,	CVMX_CSR_DB_TYPE_NCB,	32,	231},
+	{"ENDOR_RFIF_TTI_SCNT_INT7"    ,	   0x10f000086815cull,	CVMX_CSR_DB_TYPE_NCB,	32,	231},
+	{"ENDOR_RFIF_TTI_SCNT_INT_CLR" ,	   0x10f0000868118ull,	CVMX_CSR_DB_TYPE_NCB,	32,	232},
+	{"ENDOR_RFIF_TTI_SCNT_INT_EN"  ,	   0x10f0000868124ull,	CVMX_CSR_DB_TYPE_NCB,	32,	233},
+	{"ENDOR_RFIF_TTI_SCNT_INT_MAP" ,	   0x10f0000868120ull,	CVMX_CSR_DB_TYPE_NCB,	32,	234},
+	{"ENDOR_RFIF_TTI_SCNT_INT_STAT",	   0x10f000086811cull,	CVMX_CSR_DB_TYPE_NCB,	32,	235},
+	{"ENDOR_RFIF_TX_DIV_STATUS"    ,	   0x10f000086800cull,	CVMX_CSR_DB_TYPE_NCB,	32,	236},
+	{"ENDOR_RFIF_TX_IF_CFG"        ,	   0x10f0000868034ull,	CVMX_CSR_DB_TYPE_NCB,	32,	237},
+	{"ENDOR_RFIF_TX_LEAD_LAG"      ,	   0x10f0000868024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	238},
+	{"ENDOR_RFIF_TX_OFFSET"        ,	   0x10f00008680d8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	239},
+	{"ENDOR_RFIF_TX_OFFSET_ADJ_SCNT",	   0x10f000086810cull,	CVMX_CSR_DB_TYPE_NCB,	32,	240},
+	{"ENDOR_RFIF_TX_STATUS"        ,	   0x10f0000868008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	241},
+	{"ENDOR_RFIF_TX_TH"            ,	   0x10f0000868414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	242},
+	{"ENDOR_RFIF_WIN_EN"           ,	   0x10f0000868040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	243},
+	{"ENDOR_RFIF_WIN_UPD_SCNT"     ,	   0x10f000086803cull,	CVMX_CSR_DB_TYPE_NCB,	32,	244},
+	{"ENDOR_RFIF_WR_TIMER64_LSB"   ,	   0x10f00008681a4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	245},
+	{"ENDOR_RFIF_WR_TIMER64_MSB"   ,	   0x10f00008681a8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	246},
+	{"ENDOR_RSTCLK_CLKENB0_CLR"    ,	   0x10f0000844428ull,	CVMX_CSR_DB_TYPE_NCB,	32,	247},
+	{"ENDOR_RSTCLK_CLKENB0_SET"    ,	   0x10f0000844424ull,	CVMX_CSR_DB_TYPE_NCB,	32,	248},
+	{"ENDOR_RSTCLK_CLKENB0_STATE"  ,	   0x10f0000844420ull,	CVMX_CSR_DB_TYPE_NCB,	32,	249},
+	{"ENDOR_RSTCLK_CLKENB1_CLR"    ,	   0x10f0000844438ull,	CVMX_CSR_DB_TYPE_NCB,	32,	250},
+	{"ENDOR_RSTCLK_CLKENB1_SET"    ,	   0x10f0000844434ull,	CVMX_CSR_DB_TYPE_NCB,	32,	251},
+	{"ENDOR_RSTCLK_CLKENB1_STATE"  ,	   0x10f0000844430ull,	CVMX_CSR_DB_TYPE_NCB,	32,	252},
+	{"ENDOR_RSTCLK_DSPSTALL_CLR"   ,	   0x10f0000844448ull,	CVMX_CSR_DB_TYPE_NCB,	32,	253},
+	{"ENDOR_RSTCLK_DSPSTALL_SET"   ,	   0x10f0000844444ull,	CVMX_CSR_DB_TYPE_NCB,	32,	254},
+	{"ENDOR_RSTCLK_DSPSTALL_STATE" ,	   0x10f0000844440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	255},
+	{"ENDOR_RSTCLK_INTR0_CLRMASK"  ,	   0x10f0000844598ull,	CVMX_CSR_DB_TYPE_NCB,	32,	256},
+	{"ENDOR_RSTCLK_INTR0_MASK"     ,	   0x10f0000844590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	257},
+	{"ENDOR_RSTCLK_INTR0_SETMASK"  ,	   0x10f0000844594ull,	CVMX_CSR_DB_TYPE_NCB,	32,	258},
+	{"ENDOR_RSTCLK_INTR0_STATUS"   ,	   0x10f000084459cull,	CVMX_CSR_DB_TYPE_NCB,	32,	259},
+	{"ENDOR_RSTCLK_INTR1_CLRMASK"  ,	   0x10f00008445a8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	260},
+	{"ENDOR_RSTCLK_INTR1_MASK"     ,	   0x10f00008445a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	261},
+	{"ENDOR_RSTCLK_INTR1_SETMASK"  ,	   0x10f00008445a4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	262},
+	{"ENDOR_RSTCLK_INTR1_STATUS"   ,	   0x10f00008445acull,	CVMX_CSR_DB_TYPE_NCB,	32,	263},
+	{"ENDOR_RSTCLK_PHY_CONFIG"     ,	   0x10f0000844450ull,	CVMX_CSR_DB_TYPE_NCB,	32,	264},
+	{"ENDOR_RSTCLK_PROC_MON"       ,	   0x10f00008445b0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	265},
+	{"ENDOR_RSTCLK_PROC_MON_COUNT" ,	   0x10f00008445b4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	266},
+	{"ENDOR_RSTCLK_RESET0_CLR"     ,	   0x10f0000844408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	267},
+	{"ENDOR_RSTCLK_RESET0_SET"     ,	   0x10f0000844404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	268},
+	{"ENDOR_RSTCLK_RESET0_STATE"   ,	   0x10f0000844400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	269},
+	{"ENDOR_RSTCLK_RESET1_CLR"     ,	   0x10f0000844418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	270},
+	{"ENDOR_RSTCLK_RESET1_SET"     ,	   0x10f0000844414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	271},
+	{"ENDOR_RSTCLK_RESET1_STATE"   ,	   0x10f0000844410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	272},
+	{"ENDOR_RSTCLK_SW_INTR_CLR"    ,	   0x10f0000844588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	273},
+	{"ENDOR_RSTCLK_SW_INTR_SET"    ,	   0x10f0000844584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	274},
+	{"ENDOR_RSTCLK_SW_INTR_STATUS" ,	   0x10f0000844580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	275},
+	{"ENDOR_RSTCLK_TIME0_THRD"     ,	   0x10f0000844510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	276},
+	{"ENDOR_RSTCLK_TIME1_THRD"     ,	   0x10f0000844514ull,	CVMX_CSR_DB_TYPE_NCB,	32,	276},
+	{"ENDOR_RSTCLK_TIME2_THRD"     ,	   0x10f0000844518ull,	CVMX_CSR_DB_TYPE_NCB,	32,	276},
+	{"ENDOR_RSTCLK_TIME3_THRD"     ,	   0x10f000084451cull,	CVMX_CSR_DB_TYPE_NCB,	32,	276},
+	{"ENDOR_RSTCLK_TIME4_THRD"     ,	   0x10f0000844520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	276},
+	{"ENDOR_RSTCLK_TIME5_THRD"     ,	   0x10f0000844524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	276},
+	{"ENDOR_RSTCLK_TIME6_THRD"     ,	   0x10f0000844528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	276},
+	{"ENDOR_RSTCLK_TIME7_THRD"     ,	   0x10f000084452cull,	CVMX_CSR_DB_TYPE_NCB,	32,	276},
+	{"ENDOR_RSTCLK_TIMER_CTL"      ,	   0x10f0000844500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	277},
+	{"ENDOR_RSTCLK_TIMER_INTR_CLR" ,	   0x10f0000844534ull,	CVMX_CSR_DB_TYPE_NCB,	32,	278},
+	{"ENDOR_RSTCLK_TIMER_INTR_STATUS",	   0x10f0000844530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	279},
+	{"ENDOR_RSTCLK_TIMER_MAX"      ,	   0x10f0000844508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	280},
+	{"ENDOR_RSTCLK_TIMER_VALUE"    ,	   0x10f0000844504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	281},
+	{"ENDOR_RSTCLK_VERSION"        ,	   0x10f0000844570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	282},
+	{"EOI_BIST_CTL_STA"            ,	   0x1180013000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"EOI_CTL_STA"                 ,	   0x1180013000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"EOI_DEF_STA0"                ,	   0x1180013000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"EOI_DEF_STA1"                ,	   0x1180013000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"EOI_DEF_STA2"                ,	   0x1180013000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"EOI_ECC_CTL"                 ,	   0x1180013000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"EOI_ENDOR_BISTR_CTL_STA"     ,	   0x1180013000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
+	{"EOI_ENDOR_CLK_CTL"           ,	   0x1180013000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"EOI_ENDOR_CTL"               ,	   0x1180013000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"EOI_INT_ENA"                 ,	   0x1180013000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"EOI_INT_STA"                 ,	   0x1180013000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"EOI_IO_DRV"                  ,	   0x1180013000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"EOI_THROTTLE_CTL"            ,	   0x1180013000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"FPA_ADDR_RANGE_ERROR"        ,	   0x1180028000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"FPA_FPF3_MARKS"              ,	   0x1180028000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"FPA_FPF4_MARKS"              ,	   0x1180028000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"FPA_FPF5_MARKS"              ,	   0x1180028000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"FPA_FPF6_MARKS"              ,	   0x1180028000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"FPA_FPF7_MARKS"              ,	   0x1180028000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"FPA_FPF1_SIZE"               ,	   0x1180028000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"FPA_FPF2_SIZE"               ,	   0x1180028000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"FPA_FPF3_SIZE"               ,	   0x1180028000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"FPA_FPF4_SIZE"               ,	   0x1180028000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"FPA_FPF5_SIZE"               ,	   0x1180028000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"FPA_FPF6_SIZE"               ,	   0x1180028000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"FPA_FPF7_SIZE"               ,	   0x1180028000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"FPA_FPF0_MARKS"              ,	   0x1180028000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"FPA_FPF0_SIZE"               ,	   0x1180028000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"FPA_PACKET_THRESHOLD"        ,	   0x1180028000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"FPA_POOL0_END_ADDR"          ,	   0x1180028000358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"FPA_POOL1_END_ADDR"          ,	   0x1180028000360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"FPA_POOL2_END_ADDR"          ,	   0x1180028000368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"FPA_POOL3_END_ADDR"          ,	   0x1180028000370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"FPA_POOL4_END_ADDR"          ,	   0x1180028000378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"FPA_POOL5_END_ADDR"          ,	   0x1180028000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"FPA_POOL6_END_ADDR"          ,	   0x1180028000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"FPA_POOL7_END_ADDR"          ,	   0x1180028000390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"FPA_POOL0_START_ADDR"        ,	   0x1180028000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"FPA_POOL1_START_ADDR"        ,	   0x1180028000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"FPA_POOL2_START_ADDR"        ,	   0x1180028000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"FPA_POOL3_START_ADDR"        ,	   0x1180028000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"FPA_POOL4_START_ADDR"        ,	   0x1180028000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"FPA_POOL5_START_ADDR"        ,	   0x1180028000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"FPA_POOL6_START_ADDR"        ,	   0x1180028000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"FPA_POOL7_START_ADDR"        ,	   0x1180028000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"FPA_POOL0_THRESHOLD"         ,	   0x1180028000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"FPA_POOL1_THRESHOLD"         ,	   0x1180028000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"FPA_POOL2_THRESHOLD"         ,	   0x1180028000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"FPA_POOL3_THRESHOLD"         ,	   0x1180028000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"FPA_POOL4_THRESHOLD"         ,	   0x1180028000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"FPA_POOL5_THRESHOLD"         ,	   0x1180028000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"FPA_POOL6_THRESHOLD"         ,	   0x1180028000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"FPA_POOL7_THRESHOLD"         ,	   0x1180028000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"FPA_QUE5_PAGE_INDEX"         ,	   0x1180028000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"FPA_QUE6_PAGE_INDEX"         ,	   0x1180028000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"FPA_WQE_THRESHOLD"           ,	   0x1180028000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"GMX0_CLK_EN"                 ,	   0x11800080007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"GMX0_HG2_CONTROL"            ,	   0x1180008000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"GMX0_INF_MODE"               ,	   0x11800080007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"GMX0_PRT000_CBFC_CTL"        ,	   0x1180008000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"GMX0_RX000_ADR_CAM0"         ,	   0x1180008000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"GMX0_RX001_ADR_CAM0"         ,	   0x1180008000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"GMX0_RX002_ADR_CAM0"         ,	   0x1180008001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"GMX0_RX003_ADR_CAM0"         ,	   0x1180008001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"GMX0_RX000_ADR_CAM1"         ,	   0x1180008000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"GMX0_RX001_ADR_CAM1"         ,	   0x1180008000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"GMX0_RX002_ADR_CAM1"         ,	   0x1180008001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"GMX0_RX003_ADR_CAM1"         ,	   0x1180008001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"GMX0_RX000_ADR_CAM2"         ,	   0x1180008000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"GMX0_RX001_ADR_CAM2"         ,	   0x1180008000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"GMX0_RX002_ADR_CAM2"         ,	   0x1180008001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"GMX0_RX003_ADR_CAM2"         ,	   0x1180008001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"GMX0_RX003_ADR_CAM3"         ,	   0x1180008001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"GMX0_RX000_ADR_CAM_ALL_EN"   ,	   0x1180008000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
+	{"GMX0_RX001_ADR_CAM_ALL_EN"   ,	   0x1180008000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
+	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"GMX0_RX000_ADR_CTL"          ,	   0x1180008000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"GMX0_RX001_ADR_CTL"          ,	   0x1180008000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"GMX0_RX000_DECISION"         ,	   0x1180008000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"GMX0_RX001_DECISION"         ,	   0x1180008000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"GMX0_RX000_FRM_CHK"          ,	   0x1180008000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"GMX0_RX001_FRM_CHK"          ,	   0x1180008000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"GMX0_RX000_FRM_CTL"          ,	   0x1180008000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"GMX0_RX001_FRM_CTL"          ,	   0x1180008000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"GMX0_RX000_IFG"              ,	   0x1180008000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"GMX0_RX001_IFG"              ,	   0x1180008000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"GMX0_RX000_INT_EN"           ,	   0x1180008000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
+	{"GMX0_RX001_INT_EN"           ,	   0x1180008000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
+	{"GMX0_RX000_INT_REG"          ,	   0x1180008000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
+	{"GMX0_RX001_INT_REG"          ,	   0x1180008000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
+	{"GMX0_RX000_JABBER"           ,	   0x1180008000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
+	{"GMX0_RX001_JABBER"           ,	   0x1180008000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
+	{"GMX0_RX000_PAUSE_DROP_TIME"  ,	   0x1180008000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
+	{"GMX0_RX001_PAUSE_DROP_TIME"  ,	   0x1180008000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
+	{"GMX0_RX000_STATS_CTL"        ,	   0x1180008000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
+	{"GMX0_RX001_STATS_CTL"        ,	   0x1180008000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
+	{"GMX0_RX000_STATS_OCTS"       ,	   0x1180008000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
+	{"GMX0_RX001_STATS_OCTS"       ,	   0x1180008000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
+	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
+	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
+	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"GMX0_RX_BP_DROP000"          ,	   0x1180008000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"GMX0_RX_BP_DROP001"          ,	   0x1180008000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"GMX0_RX_BP_OFF000"           ,	   0x1180008000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
+	{"GMX0_RX_BP_OFF001"           ,	   0x1180008000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
+	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
+	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
+	{"GMX0_RX_HG2_STATUS"          ,	   0x1180008000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	353},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"GMX0_RX_XAUI_BAD_COL"        ,	   0x1180008000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"GMX0_RX_XAUI_CTL"            ,	   0x1180008000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"GMX0_SMAC001"                ,	   0x1180008000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"GMX0_TB_REG"                 ,	   0x11800080007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	361},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	361},
+	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	362},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	362},
+	{"GMX0_TX000_CBFC_XOFF"        ,	   0x11800080005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"GMX0_TX000_CBFC_XON"         ,	   0x11800080005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
+	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"GMX0_TX000_SGMII_CTL"        ,	   0x1180008000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"GMX0_TX_BP"                  ,	   0x11800080004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"GMX0_TX_HG2_REG1"            ,	   0x1180008000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"GMX0_TX_HG2_REG2"            ,	   0x1180008000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"GMX0_TX_XAUI_CTL"            ,	   0x1180008000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"GMX0_XAUI_EXT_LOOPBACK"      ,	   0x1180008000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"GPIO_BIT_CFG3"               ,	   0x1070000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"GPIO_BIT_CFG4"               ,	   0x1070000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"GPIO_BIT_CFG5"               ,	   0x1070000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"GPIO_BIT_CFG6"               ,	   0x1070000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"GPIO_BIT_CFG7"               ,	   0x1070000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"GPIO_BIT_CFG8"               ,	   0x1070000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"GPIO_BIT_CFG9"               ,	   0x1070000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"GPIO_BIT_CFG10"              ,	   0x1070000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"GPIO_BIT_CFG11"              ,	   0x1070000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"GPIO_BIT_CFG12"              ,	   0x1070000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"GPIO_CLK_GEN0"               ,	   0x10700000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
+	{"GPIO_CLK_GEN1"               ,	   0x10700000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
+	{"GPIO_CLK_GEN2"               ,	   0x10700000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
+	{"GPIO_CLK_GEN3"               ,	   0x10700000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
+	{"GPIO_CLK_QLM0"               ,	   0x10700000008e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
+	{"GPIO_CLK_QLM1"               ,	   0x10700000008e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
+	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	405},
+	{"GPIO_MULTI_CAST"             ,	   0x10700000008b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	406},
+	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	407},
+	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	408},
+	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	409},
+	{"GPIO_XBIT_CFG16"             ,	   0x1070000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	410},
+	{"GPIO_XBIT_CFG17"             ,	   0x1070000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	410},
+	{"GPIO_XBIT_CFG18"             ,	   0x1070000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	410},
+	{"GPIO_XBIT_CFG19"             ,	   0x1070000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	410},
+	{"IOB_BIST_STATUS"             ,	   0x11800f00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"IOB_CTL_STATUS"              ,	   0x11800f0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800f0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800f0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800f0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800f0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800f0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800f0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800f0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"IOB_INT_ENB"                 ,	   0x11800f0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"IOB_INT_SUM"                 ,	   0x11800f0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800f0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800f0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800f0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800f0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800f00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800f0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800f00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800f0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800f0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800f0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"IOB_PKT_ERR"                 ,	   0x11800f0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"IOB_TO_CMB_CREDITS"          ,	   0x11800f00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	434},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	435},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	436},
+	{"IPD_BIST_STATUS"             ,	   0x14f00000007f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	437},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14f0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	438},
+	{"IPD_CLK_COUNT"               ,	   0x14f0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	439},
+	{"IPD_CTL_STATUS"              ,	   0x14f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	440},
+	{"IPD_INT_ENB"                 ,	   0x14f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	441},
+	{"IPD_INT_SUM"                 ,	   0x14f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	442},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	443},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	444},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14f0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	445},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	446},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	446},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	446},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	446},
+	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14f00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	446},
+	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14f00000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	446},
+	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14f00000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	446},
+	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14f00000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	446},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	446},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	446},
+	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14f0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	446},
+	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14f0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	446},
+	{"IPD_PORT36_BP_PAGE_CNT2"     ,	   0x14f0000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	447},
+	{"IPD_PORT37_BP_PAGE_CNT2"     ,	   0x14f0000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	447},
+	{"IPD_PORT38_BP_PAGE_CNT2"     ,	   0x14f0000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	447},
+	{"IPD_PORT39_BP_PAGE_CNT2"     ,	   0x14f0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	447},
+	{"IPD_PORT40_BP_PAGE_CNT3"     ,	   0x14f00000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	448},
+	{"IPD_PORT41_BP_PAGE_CNT3"     ,	   0x14f00000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	448},
+	{"IPD_PORT42_BP_PAGE_CNT3"     ,	   0x14f00000003e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	448},
+	{"IPD_PORT43_BP_PAGE_CNT3"     ,	   0x14f00000003e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	448},
+	{"IPD_PORT44_BP_PAGE_CNT3"     ,	   0x14f00000003f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	448},
+	{"IPD_PORT45_BP_PAGE_CNT3"     ,	   0x14f00000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	448},
+	{"IPD_PORT46_BP_PAGE_CNT3"     ,	   0x14f0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	448},
+	{"IPD_PORT47_BP_PAGE_CNT3"     ,	   0x14f0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	448},
+	{"IPD_PORT_BP_COUNTERS2_PAIR36",	   0x14f0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	449},
+	{"IPD_PORT_BP_COUNTERS2_PAIR37",	   0x14f0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	449},
+	{"IPD_PORT_BP_COUNTERS2_PAIR38",	   0x14f0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	449},
+	{"IPD_PORT_BP_COUNTERS2_PAIR39",	   0x14f00000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	449},
+	{"IPD_PORT_BP_COUNTERS3_PAIR40",	   0x14f00000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	450},
+	{"IPD_PORT_BP_COUNTERS3_PAIR41",	   0x14f00000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	450},
+	{"IPD_PORT_BP_COUNTERS3_PAIR42",	   0x14f00000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	450},
+	{"IPD_PORT_BP_COUNTERS3_PAIR43",	   0x14f00000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	450},
+	{"IPD_PORT_BP_COUNTERS4_PAIR44",	   0x14f0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	451},
+	{"IPD_PORT_BP_COUNTERS4_PAIR45",	   0x14f0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	451},
+	{"IPD_PORT_BP_COUNTERS4_PAIR46",	   0x14f0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	451},
+	{"IPD_PORT_BP_COUNTERS4_PAIR47",	   0x14f0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	451},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	452},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	452},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	452},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14f00000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	452},
+	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14f0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	452},
+	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14f0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	452},
+	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14f0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	452},
+	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14f0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	452},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14f00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	452},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14f00000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	452},
+	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14f00000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	452},
+	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14f00000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	452},
+	{"IPD_PORT_QOS_0_CNT"          ,	   0x14f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_1_CNT"          ,	   0x14f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_2_CNT"          ,	   0x14f0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_3_CNT"          ,	   0x14f00000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_4_CNT"          ,	   0x14f00000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_5_CNT"          ,	   0x14f00000008b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_6_CNT"          ,	   0x14f00000008b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_7_CNT"          ,	   0x14f00000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_8_CNT"          ,	   0x14f00000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_9_CNT"          ,	   0x14f00000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_10_CNT"         ,	   0x14f00000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_11_CNT"         ,	   0x14f00000008e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_12_CNT"         ,	   0x14f00000008e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_13_CNT"         ,	   0x14f00000008f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_14_CNT"         ,	   0x14f00000008f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_15_CNT"         ,	   0x14f0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_16_CNT"         ,	   0x14f0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_17_CNT"         ,	   0x14f0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_18_CNT"         ,	   0x14f0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_19_CNT"         ,	   0x14f0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_20_CNT"         ,	   0x14f0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_21_CNT"         ,	   0x14f0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_22_CNT"         ,	   0x14f0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_23_CNT"         ,	   0x14f0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_24_CNT"         ,	   0x14f0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_25_CNT"         ,	   0x14f0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_26_CNT"         ,	   0x14f0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_27_CNT"         ,	   0x14f0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_28_CNT"         ,	   0x14f0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_29_CNT"         ,	   0x14f0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_30_CNT"         ,	   0x14f0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_31_CNT"         ,	   0x14f0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_128_CNT"        ,	   0x14f0000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_129_CNT"        ,	   0x14f0000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_130_CNT"        ,	   0x14f0000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_131_CNT"        ,	   0x14f0000000ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_132_CNT"        ,	   0x14f0000000ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_133_CNT"        ,	   0x14f0000000cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_134_CNT"        ,	   0x14f0000000cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_135_CNT"        ,	   0x14f0000000cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_136_CNT"        ,	   0x14f0000000cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_137_CNT"        ,	   0x14f0000000cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_138_CNT"        ,	   0x14f0000000cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_139_CNT"        ,	   0x14f0000000ce0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_140_CNT"        ,	   0x14f0000000ce8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_141_CNT"        ,	   0x14f0000000cf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_142_CNT"        ,	   0x14f0000000cf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_143_CNT"        ,	   0x14f0000000d00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_144_CNT"        ,	   0x14f0000000d08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_145_CNT"        ,	   0x14f0000000d10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_146_CNT"        ,	   0x14f0000000d18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_147_CNT"        ,	   0x14f0000000d20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_148_CNT"        ,	   0x14f0000000d28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_149_CNT"        ,	   0x14f0000000d30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_150_CNT"        ,	   0x14f0000000d38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_151_CNT"        ,	   0x14f0000000d40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_152_CNT"        ,	   0x14f0000000d48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_153_CNT"        ,	   0x14f0000000d50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_154_CNT"        ,	   0x14f0000000d58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_155_CNT"        ,	   0x14f0000000d60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_156_CNT"        ,	   0x14f0000000d68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_157_CNT"        ,	   0x14f0000000d70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_158_CNT"        ,	   0x14f0000000d78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_159_CNT"        ,	   0x14f0000000d80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_256_CNT"        ,	   0x14f0000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_257_CNT"        ,	   0x14f0000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_258_CNT"        ,	   0x14f0000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_259_CNT"        ,	   0x14f00000010a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_260_CNT"        ,	   0x14f00000010a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_261_CNT"        ,	   0x14f00000010b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_262_CNT"        ,	   0x14f00000010b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_263_CNT"        ,	   0x14f00000010c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_264_CNT"        ,	   0x14f00000010c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_265_CNT"        ,	   0x14f00000010d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_266_CNT"        ,	   0x14f00000010d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_267_CNT"        ,	   0x14f00000010e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_268_CNT"        ,	   0x14f00000010e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_269_CNT"        ,	   0x14f00000010f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_270_CNT"        ,	   0x14f00000010f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_271_CNT"        ,	   0x14f0000001100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_272_CNT"        ,	   0x14f0000001108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_273_CNT"        ,	   0x14f0000001110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_274_CNT"        ,	   0x14f0000001118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_275_CNT"        ,	   0x14f0000001120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_276_CNT"        ,	   0x14f0000001128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_277_CNT"        ,	   0x14f0000001130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_278_CNT"        ,	   0x14f0000001138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_279_CNT"        ,	   0x14f0000001140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_280_CNT"        ,	   0x14f0000001148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_281_CNT"        ,	   0x14f0000001150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_282_CNT"        ,	   0x14f0000001158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_283_CNT"        ,	   0x14f0000001160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_284_CNT"        ,	   0x14f0000001168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_285_CNT"        ,	   0x14f0000001170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_286_CNT"        ,	   0x14f0000001178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_287_CNT"        ,	   0x14f0000001180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_288_CNT"        ,	   0x14f0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_289_CNT"        ,	   0x14f0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_290_CNT"        ,	   0x14f0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_291_CNT"        ,	   0x14f00000011a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_292_CNT"        ,	   0x14f00000011a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_293_CNT"        ,	   0x14f00000011b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_294_CNT"        ,	   0x14f00000011b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_295_CNT"        ,	   0x14f00000011c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_296_CNT"        ,	   0x14f00000011c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_297_CNT"        ,	   0x14f00000011d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_298_CNT"        ,	   0x14f00000011d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_299_CNT"        ,	   0x14f00000011e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_300_CNT"        ,	   0x14f00000011e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_301_CNT"        ,	   0x14f00000011f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_302_CNT"        ,	   0x14f00000011f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_303_CNT"        ,	   0x14f0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_304_CNT"        ,	   0x14f0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_305_CNT"        ,	   0x14f0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_306_CNT"        ,	   0x14f0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_307_CNT"        ,	   0x14f0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_308_CNT"        ,	   0x14f0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_309_CNT"        ,	   0x14f0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_310_CNT"        ,	   0x14f0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_311_CNT"        ,	   0x14f0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_312_CNT"        ,	   0x14f0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_313_CNT"        ,	   0x14f0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_314_CNT"        ,	   0x14f0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_315_CNT"        ,	   0x14f0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_316_CNT"        ,	   0x14f0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_317_CNT"        ,	   0x14f0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_318_CNT"        ,	   0x14f0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_319_CNT"        ,	   0x14f0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_320_CNT"        ,	   0x14f0000001288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_321_CNT"        ,	   0x14f0000001290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_322_CNT"        ,	   0x14f0000001298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_323_CNT"        ,	   0x14f00000012a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_324_CNT"        ,	   0x14f00000012a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_325_CNT"        ,	   0x14f00000012b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_326_CNT"        ,	   0x14f00000012b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_327_CNT"        ,	   0x14f00000012c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_328_CNT"        ,	   0x14f00000012c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_329_CNT"        ,	   0x14f00000012d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_330_CNT"        ,	   0x14f00000012d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_331_CNT"        ,	   0x14f00000012e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_332_CNT"        ,	   0x14f00000012e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_333_CNT"        ,	   0x14f00000012f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_334_CNT"        ,	   0x14f00000012f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_335_CNT"        ,	   0x14f0000001300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_336_CNT"        ,	   0x14f0000001308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_337_CNT"        ,	   0x14f0000001310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_338_CNT"        ,	   0x14f0000001318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_339_CNT"        ,	   0x14f0000001320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_340_CNT"        ,	   0x14f0000001328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_341_CNT"        ,	   0x14f0000001330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_342_CNT"        ,	   0x14f0000001338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_343_CNT"        ,	   0x14f0000001340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_344_CNT"        ,	   0x14f0000001348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_345_CNT"        ,	   0x14f0000001350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_346_CNT"        ,	   0x14f0000001358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_347_CNT"        ,	   0x14f0000001360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_348_CNT"        ,	   0x14f0000001368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_349_CNT"        ,	   0x14f0000001370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_350_CNT"        ,	   0x14f0000001378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_351_CNT"        ,	   0x14f0000001380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_352_CNT"        ,	   0x14f0000001388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_353_CNT"        ,	   0x14f0000001390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_354_CNT"        ,	   0x14f0000001398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_355_CNT"        ,	   0x14f00000013a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_356_CNT"        ,	   0x14f00000013a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_357_CNT"        ,	   0x14f00000013b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_358_CNT"        ,	   0x14f00000013b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_359_CNT"        ,	   0x14f00000013c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_360_CNT"        ,	   0x14f00000013c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_361_CNT"        ,	   0x14f00000013d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_362_CNT"        ,	   0x14f00000013d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_363_CNT"        ,	   0x14f00000013e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_364_CNT"        ,	   0x14f00000013e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_365_CNT"        ,	   0x14f00000013f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_366_CNT"        ,	   0x14f00000013f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_367_CNT"        ,	   0x14f0000001400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_368_CNT"        ,	   0x14f0000001408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_369_CNT"        ,	   0x14f0000001410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_370_CNT"        ,	   0x14f0000001418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_371_CNT"        ,	   0x14f0000001420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_372_CNT"        ,	   0x14f0000001428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_373_CNT"        ,	   0x14f0000001430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_374_CNT"        ,	   0x14f0000001438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_375_CNT"        ,	   0x14f0000001440ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_376_CNT"        ,	   0x14f0000001448ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_377_CNT"        ,	   0x14f0000001450ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_378_CNT"        ,	   0x14f0000001458ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_379_CNT"        ,	   0x14f0000001460ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_380_CNT"        ,	   0x14f0000001468ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_381_CNT"        ,	   0x14f0000001470ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_382_CNT"        ,	   0x14f0000001478ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_383_CNT"        ,	   0x14f0000001480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"IPD_PORT_QOS_INT0"           ,	   0x14f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	454},
+	{"IPD_PORT_QOS_INT2"           ,	   0x14f0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	454},
+	{"IPD_PORT_QOS_INT4"           ,	   0x14f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	454},
+	{"IPD_PORT_QOS_INT5"           ,	   0x14f0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	454},
+	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	455},
+	{"IPD_PORT_QOS_INT_ENB2"       ,	   0x14f0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	455},
+	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	455},
+	{"IPD_PORT_QOS_INT_ENB5"       ,	   0x14f0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	455},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14f0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	456},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14f0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	457},
+	{"IPD_PTR_COUNT"               ,	   0x14f0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	458},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14f0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	459},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	460},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	460},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	460},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	460},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	460},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	460},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	460},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	460},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14f0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14f00000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
+	{"IPD_RED_PORT_ENABLE2"        ,	   0x14f00000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	463},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14f00000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	464},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14f00000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	464},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14f00000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	464},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14f00000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	464},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14f0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	464},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14f0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	464},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14f0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	464},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14f0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	464},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	465},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	466},
+	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	467},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	468},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14f0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	473},
+	{"L2C_BIG_CTL"                 ,	   0x1180080800030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	474},
+	{"L2C_BST"                     ,	   0x11800808007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	475},
+	{"L2C_BST_MEM0"                ,	   0x1180080c007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	476},
+	{"L2C_BST_TDT0"                ,	   0x1180080a007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	477},
+	{"L2C_BST_TTG0"                ,	   0x1180080a007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	478},
+	{"L2C_COP0_MAP0"               ,	   0x1180080940000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1"               ,	   0x1180080940008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP2"               ,	   0x1180080940010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP3"               ,	   0x1180080940018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP4"               ,	   0x1180080940020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP5"               ,	   0x1180080940028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP6"               ,	   0x1180080940030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP7"               ,	   0x1180080940038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP8"               ,	   0x1180080940040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP9"               ,	   0x1180080940048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP10"              ,	   0x1180080940050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP11"              ,	   0x1180080940058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP12"              ,	   0x1180080940060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP13"              ,	   0x1180080940068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP14"              ,	   0x1180080940070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP15"              ,	   0x1180080940078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16"              ,	   0x1180080940080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP17"              ,	   0x1180080940088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP18"              ,	   0x1180080940090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP19"              ,	   0x1180080940098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP20"              ,	   0x11800809400a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP21"              ,	   0x11800809400a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP22"              ,	   0x11800809400b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP23"              ,	   0x11800809400b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP24"              ,	   0x11800809400c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP25"              ,	   0x11800809400c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP26"              ,	   0x11800809400d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP27"              ,	   0x11800809400d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP28"              ,	   0x11800809400e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP29"              ,	   0x11800809400e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP30"              ,	   0x11800809400f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP31"              ,	   0x11800809400f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP32"              ,	   0x1180080940100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP33"              ,	   0x1180080940108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP34"              ,	   0x1180080940110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP35"              ,	   0x1180080940118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP36"              ,	   0x1180080940120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP37"              ,	   0x1180080940128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP38"              ,	   0x1180080940130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP39"              ,	   0x1180080940138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP40"              ,	   0x1180080940140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP41"              ,	   0x1180080940148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP42"              ,	   0x1180080940150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP43"              ,	   0x1180080940158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP44"              ,	   0x1180080940160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP45"              ,	   0x1180080940168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP46"              ,	   0x1180080940170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP47"              ,	   0x1180080940178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP48"              ,	   0x1180080940180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP49"              ,	   0x1180080940188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP50"              ,	   0x1180080940190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP51"              ,	   0x1180080940198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP52"              ,	   0x11800809401a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP53"              ,	   0x11800809401a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP54"              ,	   0x11800809401b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP55"              ,	   0x11800809401b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP56"              ,	   0x11800809401c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP57"              ,	   0x11800809401c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP58"              ,	   0x11800809401d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP59"              ,	   0x11800809401d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP60"              ,	   0x11800809401e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP61"              ,	   0x11800809401e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP62"              ,	   0x11800809401f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP63"              ,	   0x11800809401f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP64"              ,	   0x1180080940200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP65"              ,	   0x1180080940208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP66"              ,	   0x1180080940210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP67"              ,	   0x1180080940218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP68"              ,	   0x1180080940220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP69"              ,	   0x1180080940228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP70"              ,	   0x1180080940230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP71"              ,	   0x1180080940238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP72"              ,	   0x1180080940240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP73"              ,	   0x1180080940248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP74"              ,	   0x1180080940250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP75"              ,	   0x1180080940258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP76"              ,	   0x1180080940260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP77"              ,	   0x1180080940268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP78"              ,	   0x1180080940270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP79"              ,	   0x1180080940278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP80"              ,	   0x1180080940280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP81"              ,	   0x1180080940288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP82"              ,	   0x1180080940290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP83"              ,	   0x1180080940298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP84"              ,	   0x11800809402a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP85"              ,	   0x11800809402a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP86"              ,	   0x11800809402b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP87"              ,	   0x11800809402b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP88"              ,	   0x11800809402c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP89"              ,	   0x11800809402c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP90"              ,	   0x11800809402d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP91"              ,	   0x11800809402d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP92"              ,	   0x11800809402e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP93"              ,	   0x11800809402e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP94"              ,	   0x11800809402f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP95"              ,	   0x11800809402f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP96"              ,	   0x1180080940300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP97"              ,	   0x1180080940308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP98"              ,	   0x1180080940310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP99"              ,	   0x1180080940318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP100"             ,	   0x1180080940320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP101"             ,	   0x1180080940328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP102"             ,	   0x1180080940330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP103"             ,	   0x1180080940338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP104"             ,	   0x1180080940340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP105"             ,	   0x1180080940348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP106"             ,	   0x1180080940350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP107"             ,	   0x1180080940358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP108"             ,	   0x1180080940360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP109"             ,	   0x1180080940368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP110"             ,	   0x1180080940370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP111"             ,	   0x1180080940378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP112"             ,	   0x1180080940380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP113"             ,	   0x1180080940388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP114"             ,	   0x1180080940390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP115"             ,	   0x1180080940398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP116"             ,	   0x11800809403a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP117"             ,	   0x11800809403a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP118"             ,	   0x11800809403b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP119"             ,	   0x11800809403b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP120"             ,	   0x11800809403c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP121"             ,	   0x11800809403c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP122"             ,	   0x11800809403d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP123"             ,	   0x11800809403d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP124"             ,	   0x11800809403e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP125"             ,	   0x11800809403e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP126"             ,	   0x11800809403f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP127"             ,	   0x11800809403f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP128"             ,	   0x1180080940400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP129"             ,	   0x1180080940408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP130"             ,	   0x1180080940410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP131"             ,	   0x1180080940418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP132"             ,	   0x1180080940420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP133"             ,	   0x1180080940428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP134"             ,	   0x1180080940430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP135"             ,	   0x1180080940438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP136"             ,	   0x1180080940440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP137"             ,	   0x1180080940448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP138"             ,	   0x1180080940450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP139"             ,	   0x1180080940458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP140"             ,	   0x1180080940460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP141"             ,	   0x1180080940468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP142"             ,	   0x1180080940470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP143"             ,	   0x1180080940478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP144"             ,	   0x1180080940480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP145"             ,	   0x1180080940488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP146"             ,	   0x1180080940490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP147"             ,	   0x1180080940498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP148"             ,	   0x11800809404a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP149"             ,	   0x11800809404a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP150"             ,	   0x11800809404b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP151"             ,	   0x11800809404b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP152"             ,	   0x11800809404c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP153"             ,	   0x11800809404c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP154"             ,	   0x11800809404d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP155"             ,	   0x11800809404d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP156"             ,	   0x11800809404e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP157"             ,	   0x11800809404e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP158"             ,	   0x11800809404f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP159"             ,	   0x11800809404f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP160"             ,	   0x1180080940500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP161"             ,	   0x1180080940508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP162"             ,	   0x1180080940510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP163"             ,	   0x1180080940518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP164"             ,	   0x1180080940520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP165"             ,	   0x1180080940528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP166"             ,	   0x1180080940530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP167"             ,	   0x1180080940538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP168"             ,	   0x1180080940540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP169"             ,	   0x1180080940548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP170"             ,	   0x1180080940550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP171"             ,	   0x1180080940558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP172"             ,	   0x1180080940560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP173"             ,	   0x1180080940568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP174"             ,	   0x1180080940570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP175"             ,	   0x1180080940578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP176"             ,	   0x1180080940580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP177"             ,	   0x1180080940588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP178"             ,	   0x1180080940590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP179"             ,	   0x1180080940598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP180"             ,	   0x11800809405a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP181"             ,	   0x11800809405a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP182"             ,	   0x11800809405b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP183"             ,	   0x11800809405b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP184"             ,	   0x11800809405c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP185"             ,	   0x11800809405c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP186"             ,	   0x11800809405d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP187"             ,	   0x11800809405d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP188"             ,	   0x11800809405e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP189"             ,	   0x11800809405e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP190"             ,	   0x11800809405f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP191"             ,	   0x11800809405f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP192"             ,	   0x1180080940600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP193"             ,	   0x1180080940608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP194"             ,	   0x1180080940610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP195"             ,	   0x1180080940618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP196"             ,	   0x1180080940620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP197"             ,	   0x1180080940628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP198"             ,	   0x1180080940630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP199"             ,	   0x1180080940638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP200"             ,	   0x1180080940640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP201"             ,	   0x1180080940648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP202"             ,	   0x1180080940650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP203"             ,	   0x1180080940658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP204"             ,	   0x1180080940660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP205"             ,	   0x1180080940668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP206"             ,	   0x1180080940670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP207"             ,	   0x1180080940678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP208"             ,	   0x1180080940680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP209"             ,	   0x1180080940688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP210"             ,	   0x1180080940690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP211"             ,	   0x1180080940698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP212"             ,	   0x11800809406a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP213"             ,	   0x11800809406a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP214"             ,	   0x11800809406b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP215"             ,	   0x11800809406b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP216"             ,	   0x11800809406c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP217"             ,	   0x11800809406c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP218"             ,	   0x11800809406d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP219"             ,	   0x11800809406d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP220"             ,	   0x11800809406e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP221"             ,	   0x11800809406e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP222"             ,	   0x11800809406f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP223"             ,	   0x11800809406f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP224"             ,	   0x1180080940700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP225"             ,	   0x1180080940708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP226"             ,	   0x1180080940710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP227"             ,	   0x1180080940718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP228"             ,	   0x1180080940720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP229"             ,	   0x1180080940728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP230"             ,	   0x1180080940730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP231"             ,	   0x1180080940738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP232"             ,	   0x1180080940740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP233"             ,	   0x1180080940748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP234"             ,	   0x1180080940750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP235"             ,	   0x1180080940758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP236"             ,	   0x1180080940760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP237"             ,	   0x1180080940768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP238"             ,	   0x1180080940770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP239"             ,	   0x1180080940778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP240"             ,	   0x1180080940780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP241"             ,	   0x1180080940788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP242"             ,	   0x1180080940790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP243"             ,	   0x1180080940798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP244"             ,	   0x11800809407a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP245"             ,	   0x11800809407a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP246"             ,	   0x11800809407b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP247"             ,	   0x11800809407b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP248"             ,	   0x11800809407c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP249"             ,	   0x11800809407c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP250"             ,	   0x11800809407d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP251"             ,	   0x11800809407d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP252"             ,	   0x11800809407e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP253"             ,	   0x11800809407e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP254"             ,	   0x11800809407f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP255"             ,	   0x11800809407f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP256"             ,	   0x1180080940800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP257"             ,	   0x1180080940808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP258"             ,	   0x1180080940810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP259"             ,	   0x1180080940818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP260"             ,	   0x1180080940820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP261"             ,	   0x1180080940828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP262"             ,	   0x1180080940830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP263"             ,	   0x1180080940838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP264"             ,	   0x1180080940840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP265"             ,	   0x1180080940848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP266"             ,	   0x1180080940850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP267"             ,	   0x1180080940858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP268"             ,	   0x1180080940860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP269"             ,	   0x1180080940868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP270"             ,	   0x1180080940870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP271"             ,	   0x1180080940878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP272"             ,	   0x1180080940880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP273"             ,	   0x1180080940888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP274"             ,	   0x1180080940890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP275"             ,	   0x1180080940898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP276"             ,	   0x11800809408a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP277"             ,	   0x11800809408a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP278"             ,	   0x11800809408b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP279"             ,	   0x11800809408b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP280"             ,	   0x11800809408c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP281"             ,	   0x11800809408c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP282"             ,	   0x11800809408d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP283"             ,	   0x11800809408d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP284"             ,	   0x11800809408e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP285"             ,	   0x11800809408e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP286"             ,	   0x11800809408f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP287"             ,	   0x11800809408f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP288"             ,	   0x1180080940900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP289"             ,	   0x1180080940908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP290"             ,	   0x1180080940910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP291"             ,	   0x1180080940918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP292"             ,	   0x1180080940920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP293"             ,	   0x1180080940928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP294"             ,	   0x1180080940930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP295"             ,	   0x1180080940938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP296"             ,	   0x1180080940940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP297"             ,	   0x1180080940948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP298"             ,	   0x1180080940950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP299"             ,	   0x1180080940958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP300"             ,	   0x1180080940960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP301"             ,	   0x1180080940968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP302"             ,	   0x1180080940970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP303"             ,	   0x1180080940978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP304"             ,	   0x1180080940980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP305"             ,	   0x1180080940988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP306"             ,	   0x1180080940990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP307"             ,	   0x1180080940998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP308"             ,	   0x11800809409a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP309"             ,	   0x11800809409a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP310"             ,	   0x11800809409b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP311"             ,	   0x11800809409b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP312"             ,	   0x11800809409c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP313"             ,	   0x11800809409c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP314"             ,	   0x11800809409d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP315"             ,	   0x11800809409d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP316"             ,	   0x11800809409e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP317"             ,	   0x11800809409e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP318"             ,	   0x11800809409f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP319"             ,	   0x11800809409f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP320"             ,	   0x1180080940a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP321"             ,	   0x1180080940a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP322"             ,	   0x1180080940a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP323"             ,	   0x1180080940a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP324"             ,	   0x1180080940a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP325"             ,	   0x1180080940a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP326"             ,	   0x1180080940a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP327"             ,	   0x1180080940a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP328"             ,	   0x1180080940a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP329"             ,	   0x1180080940a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP330"             ,	   0x1180080940a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP331"             ,	   0x1180080940a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP332"             ,	   0x1180080940a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP333"             ,	   0x1180080940a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP334"             ,	   0x1180080940a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP335"             ,	   0x1180080940a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP336"             ,	   0x1180080940a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP337"             ,	   0x1180080940a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP338"             ,	   0x1180080940a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP339"             ,	   0x1180080940a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP340"             ,	   0x1180080940aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP341"             ,	   0x1180080940aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP342"             ,	   0x1180080940ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP343"             ,	   0x1180080940ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP344"             ,	   0x1180080940ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP345"             ,	   0x1180080940ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP346"             ,	   0x1180080940ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP347"             ,	   0x1180080940ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP348"             ,	   0x1180080940ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP349"             ,	   0x1180080940ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP350"             ,	   0x1180080940af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP351"             ,	   0x1180080940af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP352"             ,	   0x1180080940b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP353"             ,	   0x1180080940b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP354"             ,	   0x1180080940b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP355"             ,	   0x1180080940b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP356"             ,	   0x1180080940b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP357"             ,	   0x1180080940b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP358"             ,	   0x1180080940b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP359"             ,	   0x1180080940b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP360"             ,	   0x1180080940b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP361"             ,	   0x1180080940b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP362"             ,	   0x1180080940b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP363"             ,	   0x1180080940b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP364"             ,	   0x1180080940b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP365"             ,	   0x1180080940b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP366"             ,	   0x1180080940b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP367"             ,	   0x1180080940b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP368"             ,	   0x1180080940b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP369"             ,	   0x1180080940b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP370"             ,	   0x1180080940b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP371"             ,	   0x1180080940b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP372"             ,	   0x1180080940ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP373"             ,	   0x1180080940ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP374"             ,	   0x1180080940bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP375"             ,	   0x1180080940bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP376"             ,	   0x1180080940bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP377"             ,	   0x1180080940bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP378"             ,	   0x1180080940bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP379"             ,	   0x1180080940bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP380"             ,	   0x1180080940be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP381"             ,	   0x1180080940be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP382"             ,	   0x1180080940bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP383"             ,	   0x1180080940bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP384"             ,	   0x1180080940c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP385"             ,	   0x1180080940c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP386"             ,	   0x1180080940c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP387"             ,	   0x1180080940c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP388"             ,	   0x1180080940c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP389"             ,	   0x1180080940c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP390"             ,	   0x1180080940c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP391"             ,	   0x1180080940c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP392"             ,	   0x1180080940c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP393"             ,	   0x1180080940c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP394"             ,	   0x1180080940c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP395"             ,	   0x1180080940c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP396"             ,	   0x1180080940c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP397"             ,	   0x1180080940c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP398"             ,	   0x1180080940c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP399"             ,	   0x1180080940c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP400"             ,	   0x1180080940c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP401"             ,	   0x1180080940c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP402"             ,	   0x1180080940c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP403"             ,	   0x1180080940c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP404"             ,	   0x1180080940ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP405"             ,	   0x1180080940ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP406"             ,	   0x1180080940cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP407"             ,	   0x1180080940cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP408"             ,	   0x1180080940cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP409"             ,	   0x1180080940cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP410"             ,	   0x1180080940cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP411"             ,	   0x1180080940cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP412"             ,	   0x1180080940ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP413"             ,	   0x1180080940ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP414"             ,	   0x1180080940cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP415"             ,	   0x1180080940cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP416"             ,	   0x1180080940d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP417"             ,	   0x1180080940d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP418"             ,	   0x1180080940d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP419"             ,	   0x1180080940d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP420"             ,	   0x1180080940d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP421"             ,	   0x1180080940d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP422"             ,	   0x1180080940d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP423"             ,	   0x1180080940d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP424"             ,	   0x1180080940d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP425"             ,	   0x1180080940d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP426"             ,	   0x1180080940d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP427"             ,	   0x1180080940d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP428"             ,	   0x1180080940d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP429"             ,	   0x1180080940d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP430"             ,	   0x1180080940d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP431"             ,	   0x1180080940d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP432"             ,	   0x1180080940d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP433"             ,	   0x1180080940d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP434"             ,	   0x1180080940d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP435"             ,	   0x1180080940d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP436"             ,	   0x1180080940da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP437"             ,	   0x1180080940da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP438"             ,	   0x1180080940db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP439"             ,	   0x1180080940db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP440"             ,	   0x1180080940dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP441"             ,	   0x1180080940dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP442"             ,	   0x1180080940dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP443"             ,	   0x1180080940dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP444"             ,	   0x1180080940de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP445"             ,	   0x1180080940de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP446"             ,	   0x1180080940df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP447"             ,	   0x1180080940df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP448"             ,	   0x1180080940e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP449"             ,	   0x1180080940e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP450"             ,	   0x1180080940e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP451"             ,	   0x1180080940e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP452"             ,	   0x1180080940e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP453"             ,	   0x1180080940e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP454"             ,	   0x1180080940e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP455"             ,	   0x1180080940e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP456"             ,	   0x1180080940e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP457"             ,	   0x1180080940e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP458"             ,	   0x1180080940e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP459"             ,	   0x1180080940e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP460"             ,	   0x1180080940e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP461"             ,	   0x1180080940e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP462"             ,	   0x1180080940e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP463"             ,	   0x1180080940e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP464"             ,	   0x1180080940e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP465"             ,	   0x1180080940e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP466"             ,	   0x1180080940e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP467"             ,	   0x1180080940e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP468"             ,	   0x1180080940ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP469"             ,	   0x1180080940ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP470"             ,	   0x1180080940eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP471"             ,	   0x1180080940eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP472"             ,	   0x1180080940ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP473"             ,	   0x1180080940ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP474"             ,	   0x1180080940ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP475"             ,	   0x1180080940ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP476"             ,	   0x1180080940ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP477"             ,	   0x1180080940ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP478"             ,	   0x1180080940ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP479"             ,	   0x1180080940ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP480"             ,	   0x1180080940f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP481"             ,	   0x1180080940f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP482"             ,	   0x1180080940f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP483"             ,	   0x1180080940f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP484"             ,	   0x1180080940f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP485"             ,	   0x1180080940f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP486"             ,	   0x1180080940f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP487"             ,	   0x1180080940f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP488"             ,	   0x1180080940f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP489"             ,	   0x1180080940f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP490"             ,	   0x1180080940f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP491"             ,	   0x1180080940f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP492"             ,	   0x1180080940f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP493"             ,	   0x1180080940f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP494"             ,	   0x1180080940f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP495"             ,	   0x1180080940f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP496"             ,	   0x1180080940f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP497"             ,	   0x1180080940f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP498"             ,	   0x1180080940f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP499"             ,	   0x1180080940f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP500"             ,	   0x1180080940fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP501"             ,	   0x1180080940fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP502"             ,	   0x1180080940fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP503"             ,	   0x1180080940fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP504"             ,	   0x1180080940fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP505"             ,	   0x1180080940fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP506"             ,	   0x1180080940fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP507"             ,	   0x1180080940fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP508"             ,	   0x1180080940fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP509"             ,	   0x1180080940fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP510"             ,	   0x1180080940ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP511"             ,	   0x1180080940ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP512"             ,	   0x1180080941000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP513"             ,	   0x1180080941008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP514"             ,	   0x1180080941010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP515"             ,	   0x1180080941018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP516"             ,	   0x1180080941020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP517"             ,	   0x1180080941028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP518"             ,	   0x1180080941030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP519"             ,	   0x1180080941038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP520"             ,	   0x1180080941040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP521"             ,	   0x1180080941048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP522"             ,	   0x1180080941050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP523"             ,	   0x1180080941058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP524"             ,	   0x1180080941060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP525"             ,	   0x1180080941068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP526"             ,	   0x1180080941070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP527"             ,	   0x1180080941078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP528"             ,	   0x1180080941080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP529"             ,	   0x1180080941088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP530"             ,	   0x1180080941090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP531"             ,	   0x1180080941098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP532"             ,	   0x11800809410a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP533"             ,	   0x11800809410a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP534"             ,	   0x11800809410b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP535"             ,	   0x11800809410b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP536"             ,	   0x11800809410c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP537"             ,	   0x11800809410c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP538"             ,	   0x11800809410d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP539"             ,	   0x11800809410d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP540"             ,	   0x11800809410e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP541"             ,	   0x11800809410e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP542"             ,	   0x11800809410f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP543"             ,	   0x11800809410f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP544"             ,	   0x1180080941100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP545"             ,	   0x1180080941108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP546"             ,	   0x1180080941110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP547"             ,	   0x1180080941118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP548"             ,	   0x1180080941120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP549"             ,	   0x1180080941128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP550"             ,	   0x1180080941130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP551"             ,	   0x1180080941138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP552"             ,	   0x1180080941140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP553"             ,	   0x1180080941148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP554"             ,	   0x1180080941150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP555"             ,	   0x1180080941158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP556"             ,	   0x1180080941160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP557"             ,	   0x1180080941168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP558"             ,	   0x1180080941170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP559"             ,	   0x1180080941178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP560"             ,	   0x1180080941180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP561"             ,	   0x1180080941188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP562"             ,	   0x1180080941190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP563"             ,	   0x1180080941198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP564"             ,	   0x11800809411a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP565"             ,	   0x11800809411a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP566"             ,	   0x11800809411b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP567"             ,	   0x11800809411b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP568"             ,	   0x11800809411c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP569"             ,	   0x11800809411c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP570"             ,	   0x11800809411d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP571"             ,	   0x11800809411d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP572"             ,	   0x11800809411e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP573"             ,	   0x11800809411e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP574"             ,	   0x11800809411f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP575"             ,	   0x11800809411f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP576"             ,	   0x1180080941200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP577"             ,	   0x1180080941208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP578"             ,	   0x1180080941210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP579"             ,	   0x1180080941218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP580"             ,	   0x1180080941220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP581"             ,	   0x1180080941228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP582"             ,	   0x1180080941230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP583"             ,	   0x1180080941238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP584"             ,	   0x1180080941240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP585"             ,	   0x1180080941248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP586"             ,	   0x1180080941250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP587"             ,	   0x1180080941258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP588"             ,	   0x1180080941260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP589"             ,	   0x1180080941268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP590"             ,	   0x1180080941270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP591"             ,	   0x1180080941278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP592"             ,	   0x1180080941280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP593"             ,	   0x1180080941288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP594"             ,	   0x1180080941290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP595"             ,	   0x1180080941298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP596"             ,	   0x11800809412a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP597"             ,	   0x11800809412a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP598"             ,	   0x11800809412b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP599"             ,	   0x11800809412b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP600"             ,	   0x11800809412c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP601"             ,	   0x11800809412c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP602"             ,	   0x11800809412d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP603"             ,	   0x11800809412d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP604"             ,	   0x11800809412e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP605"             ,	   0x11800809412e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP606"             ,	   0x11800809412f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP607"             ,	   0x11800809412f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP608"             ,	   0x1180080941300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP609"             ,	   0x1180080941308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP610"             ,	   0x1180080941310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP611"             ,	   0x1180080941318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP612"             ,	   0x1180080941320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP613"             ,	   0x1180080941328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP614"             ,	   0x1180080941330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP615"             ,	   0x1180080941338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP616"             ,	   0x1180080941340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP617"             ,	   0x1180080941348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP618"             ,	   0x1180080941350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP619"             ,	   0x1180080941358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP620"             ,	   0x1180080941360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP621"             ,	   0x1180080941368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP622"             ,	   0x1180080941370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP623"             ,	   0x1180080941378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP624"             ,	   0x1180080941380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP625"             ,	   0x1180080941388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP626"             ,	   0x1180080941390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP627"             ,	   0x1180080941398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP628"             ,	   0x11800809413a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP629"             ,	   0x11800809413a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP630"             ,	   0x11800809413b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP631"             ,	   0x11800809413b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP632"             ,	   0x11800809413c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP633"             ,	   0x11800809413c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP634"             ,	   0x11800809413d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP635"             ,	   0x11800809413d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP636"             ,	   0x11800809413e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP637"             ,	   0x11800809413e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP638"             ,	   0x11800809413f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP639"             ,	   0x11800809413f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP640"             ,	   0x1180080941400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP641"             ,	   0x1180080941408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP642"             ,	   0x1180080941410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP643"             ,	   0x1180080941418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP644"             ,	   0x1180080941420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP645"             ,	   0x1180080941428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP646"             ,	   0x1180080941430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP647"             ,	   0x1180080941438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP648"             ,	   0x1180080941440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP649"             ,	   0x1180080941448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP650"             ,	   0x1180080941450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP651"             ,	   0x1180080941458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP652"             ,	   0x1180080941460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP653"             ,	   0x1180080941468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP654"             ,	   0x1180080941470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP655"             ,	   0x1180080941478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP656"             ,	   0x1180080941480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP657"             ,	   0x1180080941488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP658"             ,	   0x1180080941490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP659"             ,	   0x1180080941498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP660"             ,	   0x11800809414a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP661"             ,	   0x11800809414a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP662"             ,	   0x11800809414b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP663"             ,	   0x11800809414b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP664"             ,	   0x11800809414c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP665"             ,	   0x11800809414c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP666"             ,	   0x11800809414d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP667"             ,	   0x11800809414d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP668"             ,	   0x11800809414e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP669"             ,	   0x11800809414e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP670"             ,	   0x11800809414f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP671"             ,	   0x11800809414f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP672"             ,	   0x1180080941500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP673"             ,	   0x1180080941508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP674"             ,	   0x1180080941510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP675"             ,	   0x1180080941518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP676"             ,	   0x1180080941520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP677"             ,	   0x1180080941528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP678"             ,	   0x1180080941530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP679"             ,	   0x1180080941538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP680"             ,	   0x1180080941540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP681"             ,	   0x1180080941548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP682"             ,	   0x1180080941550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP683"             ,	   0x1180080941558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP684"             ,	   0x1180080941560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP685"             ,	   0x1180080941568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP686"             ,	   0x1180080941570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP687"             ,	   0x1180080941578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP688"             ,	   0x1180080941580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP689"             ,	   0x1180080941588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP690"             ,	   0x1180080941590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP691"             ,	   0x1180080941598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP692"             ,	   0x11800809415a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP693"             ,	   0x11800809415a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP694"             ,	   0x11800809415b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP695"             ,	   0x11800809415b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP696"             ,	   0x11800809415c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP697"             ,	   0x11800809415c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP698"             ,	   0x11800809415d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP699"             ,	   0x11800809415d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP700"             ,	   0x11800809415e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP701"             ,	   0x11800809415e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP702"             ,	   0x11800809415f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP703"             ,	   0x11800809415f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP704"             ,	   0x1180080941600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP705"             ,	   0x1180080941608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP706"             ,	   0x1180080941610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP707"             ,	   0x1180080941618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP708"             ,	   0x1180080941620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP709"             ,	   0x1180080941628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP710"             ,	   0x1180080941630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP711"             ,	   0x1180080941638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP712"             ,	   0x1180080941640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP713"             ,	   0x1180080941648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP714"             ,	   0x1180080941650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP715"             ,	   0x1180080941658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP716"             ,	   0x1180080941660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP717"             ,	   0x1180080941668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP718"             ,	   0x1180080941670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP719"             ,	   0x1180080941678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP720"             ,	   0x1180080941680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP721"             ,	   0x1180080941688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP722"             ,	   0x1180080941690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP723"             ,	   0x1180080941698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP724"             ,	   0x11800809416a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP725"             ,	   0x11800809416a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP726"             ,	   0x11800809416b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP727"             ,	   0x11800809416b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP728"             ,	   0x11800809416c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP729"             ,	   0x11800809416c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP730"             ,	   0x11800809416d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP731"             ,	   0x11800809416d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP732"             ,	   0x11800809416e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP733"             ,	   0x11800809416e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP734"             ,	   0x11800809416f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP735"             ,	   0x11800809416f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP736"             ,	   0x1180080941700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP737"             ,	   0x1180080941708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP738"             ,	   0x1180080941710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP739"             ,	   0x1180080941718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP740"             ,	   0x1180080941720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP741"             ,	   0x1180080941728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP742"             ,	   0x1180080941730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP743"             ,	   0x1180080941738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP744"             ,	   0x1180080941740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP745"             ,	   0x1180080941748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP746"             ,	   0x1180080941750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP747"             ,	   0x1180080941758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP748"             ,	   0x1180080941760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP749"             ,	   0x1180080941768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP750"             ,	   0x1180080941770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP751"             ,	   0x1180080941778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP752"             ,	   0x1180080941780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP753"             ,	   0x1180080941788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP754"             ,	   0x1180080941790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP755"             ,	   0x1180080941798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP756"             ,	   0x11800809417a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP757"             ,	   0x11800809417a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP758"             ,	   0x11800809417b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP759"             ,	   0x11800809417b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP760"             ,	   0x11800809417c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP761"             ,	   0x11800809417c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP762"             ,	   0x11800809417d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP763"             ,	   0x11800809417d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP764"             ,	   0x11800809417e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP765"             ,	   0x11800809417e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP766"             ,	   0x11800809417f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP767"             ,	   0x11800809417f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP768"             ,	   0x1180080941800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP769"             ,	   0x1180080941808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP770"             ,	   0x1180080941810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP771"             ,	   0x1180080941818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP772"             ,	   0x1180080941820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP773"             ,	   0x1180080941828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP774"             ,	   0x1180080941830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP775"             ,	   0x1180080941838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP776"             ,	   0x1180080941840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP777"             ,	   0x1180080941848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP778"             ,	   0x1180080941850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP779"             ,	   0x1180080941858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP780"             ,	   0x1180080941860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP781"             ,	   0x1180080941868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP782"             ,	   0x1180080941870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP783"             ,	   0x1180080941878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP784"             ,	   0x1180080941880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP785"             ,	   0x1180080941888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP786"             ,	   0x1180080941890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP787"             ,	   0x1180080941898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP788"             ,	   0x11800809418a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP789"             ,	   0x11800809418a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP790"             ,	   0x11800809418b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP791"             ,	   0x11800809418b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP792"             ,	   0x11800809418c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP793"             ,	   0x11800809418c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP794"             ,	   0x11800809418d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP795"             ,	   0x11800809418d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP796"             ,	   0x11800809418e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP797"             ,	   0x11800809418e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP798"             ,	   0x11800809418f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP799"             ,	   0x11800809418f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP800"             ,	   0x1180080941900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP801"             ,	   0x1180080941908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP802"             ,	   0x1180080941910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP803"             ,	   0x1180080941918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP804"             ,	   0x1180080941920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP805"             ,	   0x1180080941928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP806"             ,	   0x1180080941930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP807"             ,	   0x1180080941938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP808"             ,	   0x1180080941940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP809"             ,	   0x1180080941948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP810"             ,	   0x1180080941950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP811"             ,	   0x1180080941958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP812"             ,	   0x1180080941960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP813"             ,	   0x1180080941968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP814"             ,	   0x1180080941970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP815"             ,	   0x1180080941978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP816"             ,	   0x1180080941980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP817"             ,	   0x1180080941988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP818"             ,	   0x1180080941990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP819"             ,	   0x1180080941998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP820"             ,	   0x11800809419a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP821"             ,	   0x11800809419a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP822"             ,	   0x11800809419b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP823"             ,	   0x11800809419b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP824"             ,	   0x11800809419c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP825"             ,	   0x11800809419c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP826"             ,	   0x11800809419d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP827"             ,	   0x11800809419d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP828"             ,	   0x11800809419e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP829"             ,	   0x11800809419e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP830"             ,	   0x11800809419f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP831"             ,	   0x11800809419f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP832"             ,	   0x1180080941a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP833"             ,	   0x1180080941a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP834"             ,	   0x1180080941a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP835"             ,	   0x1180080941a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP836"             ,	   0x1180080941a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP837"             ,	   0x1180080941a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP838"             ,	   0x1180080941a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP839"             ,	   0x1180080941a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP840"             ,	   0x1180080941a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP841"             ,	   0x1180080941a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP842"             ,	   0x1180080941a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP843"             ,	   0x1180080941a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP844"             ,	   0x1180080941a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP845"             ,	   0x1180080941a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP846"             ,	   0x1180080941a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP847"             ,	   0x1180080941a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP848"             ,	   0x1180080941a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP849"             ,	   0x1180080941a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP850"             ,	   0x1180080941a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP851"             ,	   0x1180080941a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP852"             ,	   0x1180080941aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP853"             ,	   0x1180080941aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP854"             ,	   0x1180080941ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP855"             ,	   0x1180080941ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP856"             ,	   0x1180080941ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP857"             ,	   0x1180080941ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP858"             ,	   0x1180080941ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP859"             ,	   0x1180080941ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP860"             ,	   0x1180080941ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP861"             ,	   0x1180080941ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP862"             ,	   0x1180080941af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP863"             ,	   0x1180080941af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP864"             ,	   0x1180080941b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP865"             ,	   0x1180080941b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP866"             ,	   0x1180080941b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP867"             ,	   0x1180080941b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP868"             ,	   0x1180080941b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP869"             ,	   0x1180080941b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP870"             ,	   0x1180080941b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP871"             ,	   0x1180080941b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP872"             ,	   0x1180080941b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP873"             ,	   0x1180080941b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP874"             ,	   0x1180080941b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP875"             ,	   0x1180080941b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP876"             ,	   0x1180080941b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP877"             ,	   0x1180080941b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP878"             ,	   0x1180080941b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP879"             ,	   0x1180080941b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP880"             ,	   0x1180080941b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP881"             ,	   0x1180080941b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP882"             ,	   0x1180080941b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP883"             ,	   0x1180080941b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP884"             ,	   0x1180080941ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP885"             ,	   0x1180080941ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP886"             ,	   0x1180080941bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP887"             ,	   0x1180080941bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP888"             ,	   0x1180080941bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP889"             ,	   0x1180080941bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP890"             ,	   0x1180080941bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP891"             ,	   0x1180080941bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP892"             ,	   0x1180080941be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP893"             ,	   0x1180080941be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP894"             ,	   0x1180080941bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP895"             ,	   0x1180080941bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP896"             ,	   0x1180080941c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP897"             ,	   0x1180080941c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP898"             ,	   0x1180080941c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP899"             ,	   0x1180080941c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP900"             ,	   0x1180080941c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP901"             ,	   0x1180080941c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP902"             ,	   0x1180080941c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP903"             ,	   0x1180080941c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP904"             ,	   0x1180080941c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP905"             ,	   0x1180080941c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP906"             ,	   0x1180080941c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP907"             ,	   0x1180080941c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP908"             ,	   0x1180080941c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP909"             ,	   0x1180080941c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP910"             ,	   0x1180080941c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP911"             ,	   0x1180080941c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP912"             ,	   0x1180080941c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP913"             ,	   0x1180080941c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP914"             ,	   0x1180080941c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP915"             ,	   0x1180080941c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP916"             ,	   0x1180080941ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP917"             ,	   0x1180080941ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP918"             ,	   0x1180080941cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP919"             ,	   0x1180080941cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP920"             ,	   0x1180080941cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP921"             ,	   0x1180080941cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP922"             ,	   0x1180080941cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP923"             ,	   0x1180080941cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP924"             ,	   0x1180080941ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP925"             ,	   0x1180080941ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP926"             ,	   0x1180080941cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP927"             ,	   0x1180080941cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP928"             ,	   0x1180080941d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP929"             ,	   0x1180080941d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP930"             ,	   0x1180080941d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP931"             ,	   0x1180080941d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP932"             ,	   0x1180080941d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP933"             ,	   0x1180080941d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP934"             ,	   0x1180080941d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP935"             ,	   0x1180080941d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP936"             ,	   0x1180080941d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP937"             ,	   0x1180080941d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP938"             ,	   0x1180080941d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP939"             ,	   0x1180080941d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP940"             ,	   0x1180080941d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP941"             ,	   0x1180080941d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP942"             ,	   0x1180080941d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP943"             ,	   0x1180080941d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP944"             ,	   0x1180080941d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP945"             ,	   0x1180080941d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP946"             ,	   0x1180080941d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP947"             ,	   0x1180080941d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP948"             ,	   0x1180080941da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP949"             ,	   0x1180080941da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP950"             ,	   0x1180080941db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP951"             ,	   0x1180080941db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP952"             ,	   0x1180080941dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP953"             ,	   0x1180080941dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP954"             ,	   0x1180080941dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP955"             ,	   0x1180080941dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP956"             ,	   0x1180080941de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP957"             ,	   0x1180080941de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP958"             ,	   0x1180080941df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP959"             ,	   0x1180080941df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP960"             ,	   0x1180080941e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP961"             ,	   0x1180080941e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP962"             ,	   0x1180080941e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP963"             ,	   0x1180080941e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP964"             ,	   0x1180080941e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP965"             ,	   0x1180080941e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP966"             ,	   0x1180080941e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP967"             ,	   0x1180080941e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP968"             ,	   0x1180080941e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP969"             ,	   0x1180080941e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP970"             ,	   0x1180080941e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP971"             ,	   0x1180080941e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP972"             ,	   0x1180080941e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP973"             ,	   0x1180080941e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP974"             ,	   0x1180080941e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP975"             ,	   0x1180080941e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP976"             ,	   0x1180080941e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP977"             ,	   0x1180080941e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP978"             ,	   0x1180080941e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP979"             ,	   0x1180080941e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP980"             ,	   0x1180080941ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP981"             ,	   0x1180080941ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP982"             ,	   0x1180080941eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP983"             ,	   0x1180080941eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP984"             ,	   0x1180080941ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP985"             ,	   0x1180080941ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP986"             ,	   0x1180080941ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP987"             ,	   0x1180080941ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP988"             ,	   0x1180080941ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP989"             ,	   0x1180080941ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP990"             ,	   0x1180080941ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP991"             ,	   0x1180080941ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP992"             ,	   0x1180080941f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP993"             ,	   0x1180080941f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP994"             ,	   0x1180080941f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP995"             ,	   0x1180080941f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP996"             ,	   0x1180080941f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP997"             ,	   0x1180080941f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP998"             ,	   0x1180080941f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP999"             ,	   0x1180080941f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1000"            ,	   0x1180080941f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1001"            ,	   0x1180080941f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1002"            ,	   0x1180080941f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1003"            ,	   0x1180080941f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1004"            ,	   0x1180080941f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1005"            ,	   0x1180080941f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1006"            ,	   0x1180080941f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1007"            ,	   0x1180080941f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1008"            ,	   0x1180080941f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1009"            ,	   0x1180080941f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1010"            ,	   0x1180080941f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1011"            ,	   0x1180080941f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1012"            ,	   0x1180080941fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1013"            ,	   0x1180080941fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1014"            ,	   0x1180080941fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1015"            ,	   0x1180080941fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1016"            ,	   0x1180080941fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1017"            ,	   0x1180080941fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1018"            ,	   0x1180080941fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1019"            ,	   0x1180080941fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1020"            ,	   0x1180080941fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1021"            ,	   0x1180080941fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1022"            ,	   0x1180080941ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP1023"            ,	   0x1180080941ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16128"           ,	   0x118008095f800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16129"           ,	   0x118008095f808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16130"           ,	   0x118008095f810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16131"           ,	   0x118008095f818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16132"           ,	   0x118008095f820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16133"           ,	   0x118008095f828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16134"           ,	   0x118008095f830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16135"           ,	   0x118008095f838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16136"           ,	   0x118008095f840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16137"           ,	   0x118008095f848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16138"           ,	   0x118008095f850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16139"           ,	   0x118008095f858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16140"           ,	   0x118008095f860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16141"           ,	   0x118008095f868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16142"           ,	   0x118008095f870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16143"           ,	   0x118008095f878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16144"           ,	   0x118008095f880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16145"           ,	   0x118008095f888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16146"           ,	   0x118008095f890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16147"           ,	   0x118008095f898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16148"           ,	   0x118008095f8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16149"           ,	   0x118008095f8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16150"           ,	   0x118008095f8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16151"           ,	   0x118008095f8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16152"           ,	   0x118008095f8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16153"           ,	   0x118008095f8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16154"           ,	   0x118008095f8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16155"           ,	   0x118008095f8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16156"           ,	   0x118008095f8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16157"           ,	   0x118008095f8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16158"           ,	   0x118008095f8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16159"           ,	   0x118008095f8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16160"           ,	   0x118008095f900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16161"           ,	   0x118008095f908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16162"           ,	   0x118008095f910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16163"           ,	   0x118008095f918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16164"           ,	   0x118008095f920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16165"           ,	   0x118008095f928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16166"           ,	   0x118008095f930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16167"           ,	   0x118008095f938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16168"           ,	   0x118008095f940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16169"           ,	   0x118008095f948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16170"           ,	   0x118008095f950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16171"           ,	   0x118008095f958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16172"           ,	   0x118008095f960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16173"           ,	   0x118008095f968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16174"           ,	   0x118008095f970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16175"           ,	   0x118008095f978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16176"           ,	   0x118008095f980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16177"           ,	   0x118008095f988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16178"           ,	   0x118008095f990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16179"           ,	   0x118008095f998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16180"           ,	   0x118008095f9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16181"           ,	   0x118008095f9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16182"           ,	   0x118008095f9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16183"           ,	   0x118008095f9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16184"           ,	   0x118008095f9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16185"           ,	   0x118008095f9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16186"           ,	   0x118008095f9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16187"           ,	   0x118008095f9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16188"           ,	   0x118008095f9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16189"           ,	   0x118008095f9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16190"           ,	   0x118008095f9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16191"           ,	   0x118008095f9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16192"           ,	   0x118008095fa00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16193"           ,	   0x118008095fa08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16194"           ,	   0x118008095fa10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16195"           ,	   0x118008095fa18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16196"           ,	   0x118008095fa20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16197"           ,	   0x118008095fa28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16198"           ,	   0x118008095fa30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16199"           ,	   0x118008095fa38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16200"           ,	   0x118008095fa40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16201"           ,	   0x118008095fa48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16202"           ,	   0x118008095fa50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16203"           ,	   0x118008095fa58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16204"           ,	   0x118008095fa60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16205"           ,	   0x118008095fa68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16206"           ,	   0x118008095fa70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16207"           ,	   0x118008095fa78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16208"           ,	   0x118008095fa80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16209"           ,	   0x118008095fa88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16210"           ,	   0x118008095fa90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16211"           ,	   0x118008095fa98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16212"           ,	   0x118008095faa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16213"           ,	   0x118008095faa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16214"           ,	   0x118008095fab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16215"           ,	   0x118008095fab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16216"           ,	   0x118008095fac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16217"           ,	   0x118008095fac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16218"           ,	   0x118008095fad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16219"           ,	   0x118008095fad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16220"           ,	   0x118008095fae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16221"           ,	   0x118008095fae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16222"           ,	   0x118008095faf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16223"           ,	   0x118008095faf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16224"           ,	   0x118008095fb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16225"           ,	   0x118008095fb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16226"           ,	   0x118008095fb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16227"           ,	   0x118008095fb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16228"           ,	   0x118008095fb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16229"           ,	   0x118008095fb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16230"           ,	   0x118008095fb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16231"           ,	   0x118008095fb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16232"           ,	   0x118008095fb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16233"           ,	   0x118008095fb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16234"           ,	   0x118008095fb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16235"           ,	   0x118008095fb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16236"           ,	   0x118008095fb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16237"           ,	   0x118008095fb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16238"           ,	   0x118008095fb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16239"           ,	   0x118008095fb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16240"           ,	   0x118008095fb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16241"           ,	   0x118008095fb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16242"           ,	   0x118008095fb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16243"           ,	   0x118008095fb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16244"           ,	   0x118008095fba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16245"           ,	   0x118008095fba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16246"           ,	   0x118008095fbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16247"           ,	   0x118008095fbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16248"           ,	   0x118008095fbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16249"           ,	   0x118008095fbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16250"           ,	   0x118008095fbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16251"           ,	   0x118008095fbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16252"           ,	   0x118008095fbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16253"           ,	   0x118008095fbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16254"           ,	   0x118008095fbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16255"           ,	   0x118008095fbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16256"           ,	   0x118008095fc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16257"           ,	   0x118008095fc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16258"           ,	   0x118008095fc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16259"           ,	   0x118008095fc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16260"           ,	   0x118008095fc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16261"           ,	   0x118008095fc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16262"           ,	   0x118008095fc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16263"           ,	   0x118008095fc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16264"           ,	   0x118008095fc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16265"           ,	   0x118008095fc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16266"           ,	   0x118008095fc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16267"           ,	   0x118008095fc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16268"           ,	   0x118008095fc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16269"           ,	   0x118008095fc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16270"           ,	   0x118008095fc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16271"           ,	   0x118008095fc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16272"           ,	   0x118008095fc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16273"           ,	   0x118008095fc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16274"           ,	   0x118008095fc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16275"           ,	   0x118008095fc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16276"           ,	   0x118008095fca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16277"           ,	   0x118008095fca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16278"           ,	   0x118008095fcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16279"           ,	   0x118008095fcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16280"           ,	   0x118008095fcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16281"           ,	   0x118008095fcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16282"           ,	   0x118008095fcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16283"           ,	   0x118008095fcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16284"           ,	   0x118008095fce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16285"           ,	   0x118008095fce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16286"           ,	   0x118008095fcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16287"           ,	   0x118008095fcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16288"           ,	   0x118008095fd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16289"           ,	   0x118008095fd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16290"           ,	   0x118008095fd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16291"           ,	   0x118008095fd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16292"           ,	   0x118008095fd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16293"           ,	   0x118008095fd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16294"           ,	   0x118008095fd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16295"           ,	   0x118008095fd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16296"           ,	   0x118008095fd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16297"           ,	   0x118008095fd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16298"           ,	   0x118008095fd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16299"           ,	   0x118008095fd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16300"           ,	   0x118008095fd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16301"           ,	   0x118008095fd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16302"           ,	   0x118008095fd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16303"           ,	   0x118008095fd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16304"           ,	   0x118008095fd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16305"           ,	   0x118008095fd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16306"           ,	   0x118008095fd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16307"           ,	   0x118008095fd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16308"           ,	   0x118008095fda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16309"           ,	   0x118008095fda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16310"           ,	   0x118008095fdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16311"           ,	   0x118008095fdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16312"           ,	   0x118008095fdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16313"           ,	   0x118008095fdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16314"           ,	   0x118008095fdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16315"           ,	   0x118008095fdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16316"           ,	   0x118008095fde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16317"           ,	   0x118008095fde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16318"           ,	   0x118008095fdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16319"           ,	   0x118008095fdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16320"           ,	   0x118008095fe00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16321"           ,	   0x118008095fe08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16322"           ,	   0x118008095fe10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16323"           ,	   0x118008095fe18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16324"           ,	   0x118008095fe20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16325"           ,	   0x118008095fe28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16326"           ,	   0x118008095fe30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16327"           ,	   0x118008095fe38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16328"           ,	   0x118008095fe40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16329"           ,	   0x118008095fe48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16330"           ,	   0x118008095fe50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16331"           ,	   0x118008095fe58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16332"           ,	   0x118008095fe60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16333"           ,	   0x118008095fe68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16334"           ,	   0x118008095fe70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16335"           ,	   0x118008095fe78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16336"           ,	   0x118008095fe80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16337"           ,	   0x118008095fe88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16338"           ,	   0x118008095fe90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16339"           ,	   0x118008095fe98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16340"           ,	   0x118008095fea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16341"           ,	   0x118008095fea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16342"           ,	   0x118008095feb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16343"           ,	   0x118008095feb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16344"           ,	   0x118008095fec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16345"           ,	   0x118008095fec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16346"           ,	   0x118008095fed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16347"           ,	   0x118008095fed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16348"           ,	   0x118008095fee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16349"           ,	   0x118008095fee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16350"           ,	   0x118008095fef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16351"           ,	   0x118008095fef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16352"           ,	   0x118008095ff00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16353"           ,	   0x118008095ff08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16354"           ,	   0x118008095ff10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16355"           ,	   0x118008095ff18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16356"           ,	   0x118008095ff20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16357"           ,	   0x118008095ff28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16358"           ,	   0x118008095ff30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16359"           ,	   0x118008095ff38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16360"           ,	   0x118008095ff40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16361"           ,	   0x118008095ff48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16362"           ,	   0x118008095ff50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16363"           ,	   0x118008095ff58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16364"           ,	   0x118008095ff60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16365"           ,	   0x118008095ff68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16366"           ,	   0x118008095ff70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16367"           ,	   0x118008095ff78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16368"           ,	   0x118008095ff80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16369"           ,	   0x118008095ff88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16370"           ,	   0x118008095ff90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16371"           ,	   0x118008095ff98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16372"           ,	   0x118008095ffa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16373"           ,	   0x118008095ffa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16374"           ,	   0x118008095ffb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16375"           ,	   0x118008095ffb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16376"           ,	   0x118008095ffc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16377"           ,	   0x118008095ffc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16378"           ,	   0x118008095ffd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16379"           ,	   0x118008095ffd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16380"           ,	   0x118008095ffe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16381"           ,	   0x118008095ffe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16382"           ,	   0x118008095fff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_COP0_MAP16383"           ,	   0x118008095fff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"L2C_CTL"                     ,	   0x1180080800000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	480},
+	{"L2C_DUT_MAP0"                ,	   0x1180080e00000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1"                ,	   0x1180080e00008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP2"                ,	   0x1180080e00010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP3"                ,	   0x1180080e00018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP4"                ,	   0x1180080e00020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP5"                ,	   0x1180080e00028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP6"                ,	   0x1180080e00030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP7"                ,	   0x1180080e00038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP8"                ,	   0x1180080e00040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP9"                ,	   0x1180080e00048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP10"               ,	   0x1180080e00050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP11"               ,	   0x1180080e00058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP12"               ,	   0x1180080e00060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP13"               ,	   0x1180080e00068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP14"               ,	   0x1180080e00070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP15"               ,	   0x1180080e00078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP16"               ,	   0x1180080e00080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP17"               ,	   0x1180080e00088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP18"               ,	   0x1180080e00090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP19"               ,	   0x1180080e00098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP20"               ,	   0x1180080e000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP21"               ,	   0x1180080e000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP22"               ,	   0x1180080e000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP23"               ,	   0x1180080e000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP24"               ,	   0x1180080e000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP25"               ,	   0x1180080e000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP26"               ,	   0x1180080e000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP27"               ,	   0x1180080e000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP28"               ,	   0x1180080e000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP29"               ,	   0x1180080e000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP30"               ,	   0x1180080e000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP31"               ,	   0x1180080e000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP32"               ,	   0x1180080e00100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP33"               ,	   0x1180080e00108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP34"               ,	   0x1180080e00110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP35"               ,	   0x1180080e00118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP36"               ,	   0x1180080e00120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP37"               ,	   0x1180080e00128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP38"               ,	   0x1180080e00130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP39"               ,	   0x1180080e00138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP40"               ,	   0x1180080e00140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP41"               ,	   0x1180080e00148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP42"               ,	   0x1180080e00150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP43"               ,	   0x1180080e00158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP44"               ,	   0x1180080e00160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP45"               ,	   0x1180080e00168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP46"               ,	   0x1180080e00170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP47"               ,	   0x1180080e00178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP48"               ,	   0x1180080e00180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP49"               ,	   0x1180080e00188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP50"               ,	   0x1180080e00190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP51"               ,	   0x1180080e00198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP52"               ,	   0x1180080e001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP53"               ,	   0x1180080e001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP54"               ,	   0x1180080e001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP55"               ,	   0x1180080e001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP56"               ,	   0x1180080e001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP57"               ,	   0x1180080e001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP58"               ,	   0x1180080e001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP59"               ,	   0x1180080e001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP60"               ,	   0x1180080e001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP61"               ,	   0x1180080e001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP62"               ,	   0x1180080e001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP63"               ,	   0x1180080e001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP64"               ,	   0x1180080e00200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP65"               ,	   0x1180080e00208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP66"               ,	   0x1180080e00210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP67"               ,	   0x1180080e00218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP68"               ,	   0x1180080e00220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP69"               ,	   0x1180080e00228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP70"               ,	   0x1180080e00230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP71"               ,	   0x1180080e00238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP72"               ,	   0x1180080e00240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP73"               ,	   0x1180080e00248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP74"               ,	   0x1180080e00250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP75"               ,	   0x1180080e00258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP76"               ,	   0x1180080e00260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP77"               ,	   0x1180080e00268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP78"               ,	   0x1180080e00270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP79"               ,	   0x1180080e00278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP80"               ,	   0x1180080e00280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP81"               ,	   0x1180080e00288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP82"               ,	   0x1180080e00290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP83"               ,	   0x1180080e00298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP84"               ,	   0x1180080e002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP85"               ,	   0x1180080e002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP86"               ,	   0x1180080e002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP87"               ,	   0x1180080e002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP88"               ,	   0x1180080e002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP89"               ,	   0x1180080e002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP90"               ,	   0x1180080e002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP91"               ,	   0x1180080e002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP92"               ,	   0x1180080e002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP93"               ,	   0x1180080e002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP94"               ,	   0x1180080e002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP95"               ,	   0x1180080e002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP96"               ,	   0x1180080e00300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP97"               ,	   0x1180080e00308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP98"               ,	   0x1180080e00310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP99"               ,	   0x1180080e00318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP100"              ,	   0x1180080e00320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP101"              ,	   0x1180080e00328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP102"              ,	   0x1180080e00330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP103"              ,	   0x1180080e00338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP104"              ,	   0x1180080e00340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP105"              ,	   0x1180080e00348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP106"              ,	   0x1180080e00350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP107"              ,	   0x1180080e00358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP108"              ,	   0x1180080e00360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP109"              ,	   0x1180080e00368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP110"              ,	   0x1180080e00370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP111"              ,	   0x1180080e00378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP112"              ,	   0x1180080e00380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP113"              ,	   0x1180080e00388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP114"              ,	   0x1180080e00390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP115"              ,	   0x1180080e00398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP116"              ,	   0x1180080e003a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP117"              ,	   0x1180080e003a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP118"              ,	   0x1180080e003b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP119"              ,	   0x1180080e003b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP120"              ,	   0x1180080e003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP121"              ,	   0x1180080e003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP122"              ,	   0x1180080e003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP123"              ,	   0x1180080e003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP124"              ,	   0x1180080e003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP125"              ,	   0x1180080e003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP126"              ,	   0x1180080e003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP127"              ,	   0x1180080e003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP128"              ,	   0x1180080e00400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP129"              ,	   0x1180080e00408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP130"              ,	   0x1180080e00410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP131"              ,	   0x1180080e00418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP132"              ,	   0x1180080e00420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP133"              ,	   0x1180080e00428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP134"              ,	   0x1180080e00430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP135"              ,	   0x1180080e00438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP136"              ,	   0x1180080e00440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP137"              ,	   0x1180080e00448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP138"              ,	   0x1180080e00450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP139"              ,	   0x1180080e00458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP140"              ,	   0x1180080e00460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP141"              ,	   0x1180080e00468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP142"              ,	   0x1180080e00470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP143"              ,	   0x1180080e00478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP144"              ,	   0x1180080e00480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP145"              ,	   0x1180080e00488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP146"              ,	   0x1180080e00490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP147"              ,	   0x1180080e00498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP148"              ,	   0x1180080e004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP149"              ,	   0x1180080e004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP150"              ,	   0x1180080e004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP151"              ,	   0x1180080e004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP152"              ,	   0x1180080e004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP153"              ,	   0x1180080e004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP154"              ,	   0x1180080e004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP155"              ,	   0x1180080e004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP156"              ,	   0x1180080e004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP157"              ,	   0x1180080e004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP158"              ,	   0x1180080e004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP159"              ,	   0x1180080e004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP160"              ,	   0x1180080e00500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP161"              ,	   0x1180080e00508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP162"              ,	   0x1180080e00510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP163"              ,	   0x1180080e00518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP164"              ,	   0x1180080e00520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP165"              ,	   0x1180080e00528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP166"              ,	   0x1180080e00530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP167"              ,	   0x1180080e00538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP168"              ,	   0x1180080e00540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP169"              ,	   0x1180080e00548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP170"              ,	   0x1180080e00550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP171"              ,	   0x1180080e00558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP172"              ,	   0x1180080e00560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP173"              ,	   0x1180080e00568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP174"              ,	   0x1180080e00570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP175"              ,	   0x1180080e00578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP176"              ,	   0x1180080e00580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP177"              ,	   0x1180080e00588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP178"              ,	   0x1180080e00590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP179"              ,	   0x1180080e00598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP180"              ,	   0x1180080e005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP181"              ,	   0x1180080e005a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP182"              ,	   0x1180080e005b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP183"              ,	   0x1180080e005b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP184"              ,	   0x1180080e005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP185"              ,	   0x1180080e005c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP186"              ,	   0x1180080e005d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP187"              ,	   0x1180080e005d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP188"              ,	   0x1180080e005e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP189"              ,	   0x1180080e005e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP190"              ,	   0x1180080e005f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP191"              ,	   0x1180080e005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP192"              ,	   0x1180080e00600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP193"              ,	   0x1180080e00608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP194"              ,	   0x1180080e00610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP195"              ,	   0x1180080e00618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP196"              ,	   0x1180080e00620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP197"              ,	   0x1180080e00628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP198"              ,	   0x1180080e00630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP199"              ,	   0x1180080e00638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP200"              ,	   0x1180080e00640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP201"              ,	   0x1180080e00648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP202"              ,	   0x1180080e00650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP203"              ,	   0x1180080e00658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP204"              ,	   0x1180080e00660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP205"              ,	   0x1180080e00668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP206"              ,	   0x1180080e00670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP207"              ,	   0x1180080e00678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP208"              ,	   0x1180080e00680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP209"              ,	   0x1180080e00688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP210"              ,	   0x1180080e00690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP211"              ,	   0x1180080e00698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP212"              ,	   0x1180080e006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP213"              ,	   0x1180080e006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP214"              ,	   0x1180080e006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP215"              ,	   0x1180080e006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP216"              ,	   0x1180080e006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP217"              ,	   0x1180080e006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP218"              ,	   0x1180080e006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP219"              ,	   0x1180080e006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP220"              ,	   0x1180080e006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP221"              ,	   0x1180080e006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP222"              ,	   0x1180080e006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP223"              ,	   0x1180080e006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP224"              ,	   0x1180080e00700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP225"              ,	   0x1180080e00708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP226"              ,	   0x1180080e00710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP227"              ,	   0x1180080e00718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP228"              ,	   0x1180080e00720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP229"              ,	   0x1180080e00728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP230"              ,	   0x1180080e00730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP231"              ,	   0x1180080e00738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP232"              ,	   0x1180080e00740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP233"              ,	   0x1180080e00748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP234"              ,	   0x1180080e00750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP235"              ,	   0x1180080e00758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP236"              ,	   0x1180080e00760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP237"              ,	   0x1180080e00768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP238"              ,	   0x1180080e00770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP239"              ,	   0x1180080e00778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP240"              ,	   0x1180080e00780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP241"              ,	   0x1180080e00788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP242"              ,	   0x1180080e00790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP243"              ,	   0x1180080e00798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP244"              ,	   0x1180080e007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP245"              ,	   0x1180080e007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP246"              ,	   0x1180080e007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP247"              ,	   0x1180080e007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP248"              ,	   0x1180080e007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP249"              ,	   0x1180080e007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP250"              ,	   0x1180080e007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP251"              ,	   0x1180080e007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP252"              ,	   0x1180080e007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP253"              ,	   0x1180080e007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP254"              ,	   0x1180080e007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP255"              ,	   0x1180080e007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP256"              ,	   0x1180080e00800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP257"              ,	   0x1180080e00808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP258"              ,	   0x1180080e00810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP259"              ,	   0x1180080e00818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP260"              ,	   0x1180080e00820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP261"              ,	   0x1180080e00828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP262"              ,	   0x1180080e00830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP263"              ,	   0x1180080e00838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP264"              ,	   0x1180080e00840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP265"              ,	   0x1180080e00848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP266"              ,	   0x1180080e00850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP267"              ,	   0x1180080e00858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP268"              ,	   0x1180080e00860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP269"              ,	   0x1180080e00868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP270"              ,	   0x1180080e00870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP271"              ,	   0x1180080e00878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP272"              ,	   0x1180080e00880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP273"              ,	   0x1180080e00888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP274"              ,	   0x1180080e00890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP275"              ,	   0x1180080e00898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP276"              ,	   0x1180080e008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP277"              ,	   0x1180080e008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP278"              ,	   0x1180080e008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP279"              ,	   0x1180080e008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP280"              ,	   0x1180080e008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP281"              ,	   0x1180080e008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP282"              ,	   0x1180080e008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP283"              ,	   0x1180080e008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP284"              ,	   0x1180080e008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP285"              ,	   0x1180080e008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP286"              ,	   0x1180080e008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP287"              ,	   0x1180080e008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP288"              ,	   0x1180080e00900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP289"              ,	   0x1180080e00908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP290"              ,	   0x1180080e00910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP291"              ,	   0x1180080e00918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP292"              ,	   0x1180080e00920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP293"              ,	   0x1180080e00928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP294"              ,	   0x1180080e00930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP295"              ,	   0x1180080e00938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP296"              ,	   0x1180080e00940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP297"              ,	   0x1180080e00948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP298"              ,	   0x1180080e00950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP299"              ,	   0x1180080e00958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP300"              ,	   0x1180080e00960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP301"              ,	   0x1180080e00968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP302"              ,	   0x1180080e00970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP303"              ,	   0x1180080e00978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP304"              ,	   0x1180080e00980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP305"              ,	   0x1180080e00988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP306"              ,	   0x1180080e00990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP307"              ,	   0x1180080e00998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP308"              ,	   0x1180080e009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP309"              ,	   0x1180080e009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP310"              ,	   0x1180080e009b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP311"              ,	   0x1180080e009b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP312"              ,	   0x1180080e009c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP313"              ,	   0x1180080e009c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP314"              ,	   0x1180080e009d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP315"              ,	   0x1180080e009d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP316"              ,	   0x1180080e009e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP317"              ,	   0x1180080e009e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP318"              ,	   0x1180080e009f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP319"              ,	   0x1180080e009f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP320"              ,	   0x1180080e00a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP321"              ,	   0x1180080e00a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP322"              ,	   0x1180080e00a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP323"              ,	   0x1180080e00a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP324"              ,	   0x1180080e00a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP325"              ,	   0x1180080e00a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP326"              ,	   0x1180080e00a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP327"              ,	   0x1180080e00a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP328"              ,	   0x1180080e00a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP329"              ,	   0x1180080e00a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP330"              ,	   0x1180080e00a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP331"              ,	   0x1180080e00a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP332"              ,	   0x1180080e00a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP333"              ,	   0x1180080e00a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP334"              ,	   0x1180080e00a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP335"              ,	   0x1180080e00a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP336"              ,	   0x1180080e00a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP337"              ,	   0x1180080e00a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP338"              ,	   0x1180080e00a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP339"              ,	   0x1180080e00a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP340"              ,	   0x1180080e00aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP341"              ,	   0x1180080e00aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP342"              ,	   0x1180080e00ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP343"              ,	   0x1180080e00ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP344"              ,	   0x1180080e00ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP345"              ,	   0x1180080e00ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP346"              ,	   0x1180080e00ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP347"              ,	   0x1180080e00ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP348"              ,	   0x1180080e00ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP349"              ,	   0x1180080e00ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP350"              ,	   0x1180080e00af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP351"              ,	   0x1180080e00af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP352"              ,	   0x1180080e00b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP353"              ,	   0x1180080e00b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP354"              ,	   0x1180080e00b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP355"              ,	   0x1180080e00b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP356"              ,	   0x1180080e00b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP357"              ,	   0x1180080e00b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP358"              ,	   0x1180080e00b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP359"              ,	   0x1180080e00b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP360"              ,	   0x1180080e00b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP361"              ,	   0x1180080e00b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP362"              ,	   0x1180080e00b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP363"              ,	   0x1180080e00b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP364"              ,	   0x1180080e00b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP365"              ,	   0x1180080e00b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP366"              ,	   0x1180080e00b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP367"              ,	   0x1180080e00b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP368"              ,	   0x1180080e00b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP369"              ,	   0x1180080e00b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP370"              ,	   0x1180080e00b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP371"              ,	   0x1180080e00b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP372"              ,	   0x1180080e00ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP373"              ,	   0x1180080e00ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP374"              ,	   0x1180080e00bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP375"              ,	   0x1180080e00bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP376"              ,	   0x1180080e00bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP377"              ,	   0x1180080e00bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP378"              ,	   0x1180080e00bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP379"              ,	   0x1180080e00bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP380"              ,	   0x1180080e00be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP381"              ,	   0x1180080e00be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP382"              ,	   0x1180080e00bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP383"              ,	   0x1180080e00bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP384"              ,	   0x1180080e00c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP385"              ,	   0x1180080e00c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP386"              ,	   0x1180080e00c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP387"              ,	   0x1180080e00c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP388"              ,	   0x1180080e00c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP389"              ,	   0x1180080e00c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP390"              ,	   0x1180080e00c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP391"              ,	   0x1180080e00c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP392"              ,	   0x1180080e00c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP393"              ,	   0x1180080e00c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP394"              ,	   0x1180080e00c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP395"              ,	   0x1180080e00c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP396"              ,	   0x1180080e00c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP397"              ,	   0x1180080e00c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP398"              ,	   0x1180080e00c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP399"              ,	   0x1180080e00c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP400"              ,	   0x1180080e00c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP401"              ,	   0x1180080e00c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP402"              ,	   0x1180080e00c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP403"              ,	   0x1180080e00c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP404"              ,	   0x1180080e00ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP405"              ,	   0x1180080e00ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP406"              ,	   0x1180080e00cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP407"              ,	   0x1180080e00cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP408"              ,	   0x1180080e00cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP409"              ,	   0x1180080e00cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP410"              ,	   0x1180080e00cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP411"              ,	   0x1180080e00cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP412"              ,	   0x1180080e00ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP413"              ,	   0x1180080e00ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP414"              ,	   0x1180080e00cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP415"              ,	   0x1180080e00cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP416"              ,	   0x1180080e00d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP417"              ,	   0x1180080e00d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP418"              ,	   0x1180080e00d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP419"              ,	   0x1180080e00d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP420"              ,	   0x1180080e00d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP421"              ,	   0x1180080e00d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP422"              ,	   0x1180080e00d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP423"              ,	   0x1180080e00d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP424"              ,	   0x1180080e00d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP425"              ,	   0x1180080e00d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP426"              ,	   0x1180080e00d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP427"              ,	   0x1180080e00d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP428"              ,	   0x1180080e00d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP429"              ,	   0x1180080e00d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP430"              ,	   0x1180080e00d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP431"              ,	   0x1180080e00d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP432"              ,	   0x1180080e00d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP433"              ,	   0x1180080e00d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP434"              ,	   0x1180080e00d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP435"              ,	   0x1180080e00d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP436"              ,	   0x1180080e00da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP437"              ,	   0x1180080e00da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP438"              ,	   0x1180080e00db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP439"              ,	   0x1180080e00db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP440"              ,	   0x1180080e00dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP441"              ,	   0x1180080e00dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP442"              ,	   0x1180080e00dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP443"              ,	   0x1180080e00dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP444"              ,	   0x1180080e00de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP445"              ,	   0x1180080e00de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP446"              ,	   0x1180080e00df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP447"              ,	   0x1180080e00df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP448"              ,	   0x1180080e00e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP449"              ,	   0x1180080e00e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP450"              ,	   0x1180080e00e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP451"              ,	   0x1180080e00e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP452"              ,	   0x1180080e00e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP453"              ,	   0x1180080e00e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP454"              ,	   0x1180080e00e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP455"              ,	   0x1180080e00e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP456"              ,	   0x1180080e00e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP457"              ,	   0x1180080e00e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP458"              ,	   0x1180080e00e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP459"              ,	   0x1180080e00e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP460"              ,	   0x1180080e00e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP461"              ,	   0x1180080e00e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP462"              ,	   0x1180080e00e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP463"              ,	   0x1180080e00e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP464"              ,	   0x1180080e00e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP465"              ,	   0x1180080e00e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP466"              ,	   0x1180080e00e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP467"              ,	   0x1180080e00e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP468"              ,	   0x1180080e00ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP469"              ,	   0x1180080e00ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP470"              ,	   0x1180080e00eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP471"              ,	   0x1180080e00eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP472"              ,	   0x1180080e00ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP473"              ,	   0x1180080e00ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP474"              ,	   0x1180080e00ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP475"              ,	   0x1180080e00ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP476"              ,	   0x1180080e00ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP477"              ,	   0x1180080e00ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP478"              ,	   0x1180080e00ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP479"              ,	   0x1180080e00ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP480"              ,	   0x1180080e00f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP481"              ,	   0x1180080e00f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP482"              ,	   0x1180080e00f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP483"              ,	   0x1180080e00f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP484"              ,	   0x1180080e00f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP485"              ,	   0x1180080e00f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP486"              ,	   0x1180080e00f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP487"              ,	   0x1180080e00f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP488"              ,	   0x1180080e00f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP489"              ,	   0x1180080e00f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP490"              ,	   0x1180080e00f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP491"              ,	   0x1180080e00f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP492"              ,	   0x1180080e00f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP493"              ,	   0x1180080e00f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP494"              ,	   0x1180080e00f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP495"              ,	   0x1180080e00f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP496"              ,	   0x1180080e00f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP497"              ,	   0x1180080e00f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP498"              ,	   0x1180080e00f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP499"              ,	   0x1180080e00f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP500"              ,	   0x1180080e00fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP501"              ,	   0x1180080e00fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP502"              ,	   0x1180080e00fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP503"              ,	   0x1180080e00fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP504"              ,	   0x1180080e00fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP505"              ,	   0x1180080e00fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP506"              ,	   0x1180080e00fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP507"              ,	   0x1180080e00fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP508"              ,	   0x1180080e00fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP509"              ,	   0x1180080e00fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP510"              ,	   0x1180080e00ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP511"              ,	   0x1180080e00ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP512"              ,	   0x1180080e01000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP513"              ,	   0x1180080e01008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP514"              ,	   0x1180080e01010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP515"              ,	   0x1180080e01018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP516"              ,	   0x1180080e01020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP517"              ,	   0x1180080e01028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP518"              ,	   0x1180080e01030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP519"              ,	   0x1180080e01038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP520"              ,	   0x1180080e01040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP521"              ,	   0x1180080e01048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP522"              ,	   0x1180080e01050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP523"              ,	   0x1180080e01058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP524"              ,	   0x1180080e01060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP525"              ,	   0x1180080e01068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP526"              ,	   0x1180080e01070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP527"              ,	   0x1180080e01078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP528"              ,	   0x1180080e01080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP529"              ,	   0x1180080e01088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP530"              ,	   0x1180080e01090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP531"              ,	   0x1180080e01098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP532"              ,	   0x1180080e010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP533"              ,	   0x1180080e010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP534"              ,	   0x1180080e010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP535"              ,	   0x1180080e010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP536"              ,	   0x1180080e010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP537"              ,	   0x1180080e010c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP538"              ,	   0x1180080e010d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP539"              ,	   0x1180080e010d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP540"              ,	   0x1180080e010e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP541"              ,	   0x1180080e010e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP542"              ,	   0x1180080e010f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP543"              ,	   0x1180080e010f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP544"              ,	   0x1180080e01100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP545"              ,	   0x1180080e01108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP546"              ,	   0x1180080e01110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP547"              ,	   0x1180080e01118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP548"              ,	   0x1180080e01120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP549"              ,	   0x1180080e01128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP550"              ,	   0x1180080e01130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP551"              ,	   0x1180080e01138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP552"              ,	   0x1180080e01140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP553"              ,	   0x1180080e01148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP554"              ,	   0x1180080e01150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP555"              ,	   0x1180080e01158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP556"              ,	   0x1180080e01160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP557"              ,	   0x1180080e01168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP558"              ,	   0x1180080e01170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP559"              ,	   0x1180080e01178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP560"              ,	   0x1180080e01180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP561"              ,	   0x1180080e01188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP562"              ,	   0x1180080e01190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP563"              ,	   0x1180080e01198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP564"              ,	   0x1180080e011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP565"              ,	   0x1180080e011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP566"              ,	   0x1180080e011b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP567"              ,	   0x1180080e011b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP568"              ,	   0x1180080e011c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP569"              ,	   0x1180080e011c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP570"              ,	   0x1180080e011d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP571"              ,	   0x1180080e011d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP572"              ,	   0x1180080e011e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP573"              ,	   0x1180080e011e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP574"              ,	   0x1180080e011f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP575"              ,	   0x1180080e011f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP576"              ,	   0x1180080e01200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP577"              ,	   0x1180080e01208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP578"              ,	   0x1180080e01210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP579"              ,	   0x1180080e01218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP580"              ,	   0x1180080e01220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP581"              ,	   0x1180080e01228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP582"              ,	   0x1180080e01230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP583"              ,	   0x1180080e01238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP584"              ,	   0x1180080e01240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP585"              ,	   0x1180080e01248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP586"              ,	   0x1180080e01250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP587"              ,	   0x1180080e01258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP588"              ,	   0x1180080e01260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP589"              ,	   0x1180080e01268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP590"              ,	   0x1180080e01270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP591"              ,	   0x1180080e01278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP592"              ,	   0x1180080e01280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP593"              ,	   0x1180080e01288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP594"              ,	   0x1180080e01290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP595"              ,	   0x1180080e01298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP596"              ,	   0x1180080e012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP597"              ,	   0x1180080e012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP598"              ,	   0x1180080e012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP599"              ,	   0x1180080e012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP600"              ,	   0x1180080e012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP601"              ,	   0x1180080e012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP602"              ,	   0x1180080e012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP603"              ,	   0x1180080e012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP604"              ,	   0x1180080e012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP605"              ,	   0x1180080e012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP606"              ,	   0x1180080e012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP607"              ,	   0x1180080e012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP608"              ,	   0x1180080e01300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP609"              ,	   0x1180080e01308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP610"              ,	   0x1180080e01310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP611"              ,	   0x1180080e01318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP612"              ,	   0x1180080e01320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP613"              ,	   0x1180080e01328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP614"              ,	   0x1180080e01330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP615"              ,	   0x1180080e01338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP616"              ,	   0x1180080e01340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP617"              ,	   0x1180080e01348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP618"              ,	   0x1180080e01350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP619"              ,	   0x1180080e01358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP620"              ,	   0x1180080e01360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP621"              ,	   0x1180080e01368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP622"              ,	   0x1180080e01370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP623"              ,	   0x1180080e01378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP624"              ,	   0x1180080e01380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP625"              ,	   0x1180080e01388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP626"              ,	   0x1180080e01390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP627"              ,	   0x1180080e01398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP628"              ,	   0x1180080e013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP629"              ,	   0x1180080e013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP630"              ,	   0x1180080e013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP631"              ,	   0x1180080e013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP632"              ,	   0x1180080e013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP633"              ,	   0x1180080e013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP634"              ,	   0x1180080e013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP635"              ,	   0x1180080e013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP636"              ,	   0x1180080e013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP637"              ,	   0x1180080e013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP638"              ,	   0x1180080e013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP639"              ,	   0x1180080e013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP640"              ,	   0x1180080e01400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP641"              ,	   0x1180080e01408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP642"              ,	   0x1180080e01410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP643"              ,	   0x1180080e01418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP644"              ,	   0x1180080e01420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP645"              ,	   0x1180080e01428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP646"              ,	   0x1180080e01430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP647"              ,	   0x1180080e01438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP648"              ,	   0x1180080e01440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP649"              ,	   0x1180080e01448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP650"              ,	   0x1180080e01450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP651"              ,	   0x1180080e01458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP652"              ,	   0x1180080e01460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP653"              ,	   0x1180080e01468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP654"              ,	   0x1180080e01470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP655"              ,	   0x1180080e01478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP656"              ,	   0x1180080e01480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP657"              ,	   0x1180080e01488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP658"              ,	   0x1180080e01490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP659"              ,	   0x1180080e01498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP660"              ,	   0x1180080e014a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP661"              ,	   0x1180080e014a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP662"              ,	   0x1180080e014b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP663"              ,	   0x1180080e014b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP664"              ,	   0x1180080e014c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP665"              ,	   0x1180080e014c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP666"              ,	   0x1180080e014d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP667"              ,	   0x1180080e014d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP668"              ,	   0x1180080e014e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP669"              ,	   0x1180080e014e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP670"              ,	   0x1180080e014f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP671"              ,	   0x1180080e014f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP672"              ,	   0x1180080e01500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP673"              ,	   0x1180080e01508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP674"              ,	   0x1180080e01510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP675"              ,	   0x1180080e01518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP676"              ,	   0x1180080e01520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP677"              ,	   0x1180080e01528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP678"              ,	   0x1180080e01530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP679"              ,	   0x1180080e01538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP680"              ,	   0x1180080e01540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP681"              ,	   0x1180080e01548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP682"              ,	   0x1180080e01550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP683"              ,	   0x1180080e01558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP684"              ,	   0x1180080e01560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP685"              ,	   0x1180080e01568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP686"              ,	   0x1180080e01570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP687"              ,	   0x1180080e01578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP688"              ,	   0x1180080e01580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP689"              ,	   0x1180080e01588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP690"              ,	   0x1180080e01590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP691"              ,	   0x1180080e01598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP692"              ,	   0x1180080e015a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP693"              ,	   0x1180080e015a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP694"              ,	   0x1180080e015b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP695"              ,	   0x1180080e015b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP696"              ,	   0x1180080e015c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP697"              ,	   0x1180080e015c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP698"              ,	   0x1180080e015d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP699"              ,	   0x1180080e015d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP700"              ,	   0x1180080e015e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP701"              ,	   0x1180080e015e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP702"              ,	   0x1180080e015f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP703"              ,	   0x1180080e015f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP704"              ,	   0x1180080e01600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP705"              ,	   0x1180080e01608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP706"              ,	   0x1180080e01610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP707"              ,	   0x1180080e01618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP708"              ,	   0x1180080e01620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP709"              ,	   0x1180080e01628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP710"              ,	   0x1180080e01630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP711"              ,	   0x1180080e01638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP712"              ,	   0x1180080e01640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP713"              ,	   0x1180080e01648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP714"              ,	   0x1180080e01650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP715"              ,	   0x1180080e01658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP716"              ,	   0x1180080e01660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP717"              ,	   0x1180080e01668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP718"              ,	   0x1180080e01670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP719"              ,	   0x1180080e01678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP720"              ,	   0x1180080e01680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP721"              ,	   0x1180080e01688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP722"              ,	   0x1180080e01690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP723"              ,	   0x1180080e01698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP724"              ,	   0x1180080e016a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP725"              ,	   0x1180080e016a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP726"              ,	   0x1180080e016b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP727"              ,	   0x1180080e016b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP728"              ,	   0x1180080e016c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP729"              ,	   0x1180080e016c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP730"              ,	   0x1180080e016d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP731"              ,	   0x1180080e016d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP732"              ,	   0x1180080e016e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP733"              ,	   0x1180080e016e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP734"              ,	   0x1180080e016f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP735"              ,	   0x1180080e016f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP736"              ,	   0x1180080e01700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP737"              ,	   0x1180080e01708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP738"              ,	   0x1180080e01710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP739"              ,	   0x1180080e01718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP740"              ,	   0x1180080e01720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP741"              ,	   0x1180080e01728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP742"              ,	   0x1180080e01730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP743"              ,	   0x1180080e01738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP744"              ,	   0x1180080e01740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP745"              ,	   0x1180080e01748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP746"              ,	   0x1180080e01750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP747"              ,	   0x1180080e01758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP748"              ,	   0x1180080e01760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP749"              ,	   0x1180080e01768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP750"              ,	   0x1180080e01770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP751"              ,	   0x1180080e01778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP752"              ,	   0x1180080e01780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP753"              ,	   0x1180080e01788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP754"              ,	   0x1180080e01790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP755"              ,	   0x1180080e01798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP756"              ,	   0x1180080e017a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP757"              ,	   0x1180080e017a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP758"              ,	   0x1180080e017b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP759"              ,	   0x1180080e017b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP760"              ,	   0x1180080e017c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP761"              ,	   0x1180080e017c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP762"              ,	   0x1180080e017d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP763"              ,	   0x1180080e017d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP764"              ,	   0x1180080e017e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP765"              ,	   0x1180080e017e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP766"              ,	   0x1180080e017f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP767"              ,	   0x1180080e017f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP768"              ,	   0x1180080e01800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP769"              ,	   0x1180080e01808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP770"              ,	   0x1180080e01810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP771"              ,	   0x1180080e01818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP772"              ,	   0x1180080e01820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP773"              ,	   0x1180080e01828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP774"              ,	   0x1180080e01830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP775"              ,	   0x1180080e01838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP776"              ,	   0x1180080e01840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP777"              ,	   0x1180080e01848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP778"              ,	   0x1180080e01850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP779"              ,	   0x1180080e01858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP780"              ,	   0x1180080e01860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP781"              ,	   0x1180080e01868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP782"              ,	   0x1180080e01870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP783"              ,	   0x1180080e01878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP784"              ,	   0x1180080e01880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP785"              ,	   0x1180080e01888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP786"              ,	   0x1180080e01890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP787"              ,	   0x1180080e01898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP788"              ,	   0x1180080e018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP789"              ,	   0x1180080e018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP790"              ,	   0x1180080e018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP791"              ,	   0x1180080e018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP792"              ,	   0x1180080e018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP793"              ,	   0x1180080e018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP794"              ,	   0x1180080e018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP795"              ,	   0x1180080e018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP796"              ,	   0x1180080e018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP797"              ,	   0x1180080e018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP798"              ,	   0x1180080e018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP799"              ,	   0x1180080e018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP800"              ,	   0x1180080e01900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP801"              ,	   0x1180080e01908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP802"              ,	   0x1180080e01910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP803"              ,	   0x1180080e01918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP804"              ,	   0x1180080e01920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP805"              ,	   0x1180080e01928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP806"              ,	   0x1180080e01930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP807"              ,	   0x1180080e01938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP808"              ,	   0x1180080e01940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP809"              ,	   0x1180080e01948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP810"              ,	   0x1180080e01950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP811"              ,	   0x1180080e01958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP812"              ,	   0x1180080e01960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP813"              ,	   0x1180080e01968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP814"              ,	   0x1180080e01970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP815"              ,	   0x1180080e01978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP816"              ,	   0x1180080e01980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP817"              ,	   0x1180080e01988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP818"              ,	   0x1180080e01990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP819"              ,	   0x1180080e01998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP820"              ,	   0x1180080e019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP821"              ,	   0x1180080e019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP822"              ,	   0x1180080e019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP823"              ,	   0x1180080e019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP824"              ,	   0x1180080e019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP825"              ,	   0x1180080e019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP826"              ,	   0x1180080e019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP827"              ,	   0x1180080e019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP828"              ,	   0x1180080e019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP829"              ,	   0x1180080e019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP830"              ,	   0x1180080e019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP831"              ,	   0x1180080e019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP832"              ,	   0x1180080e01a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP833"              ,	   0x1180080e01a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP834"              ,	   0x1180080e01a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP835"              ,	   0x1180080e01a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP836"              ,	   0x1180080e01a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP837"              ,	   0x1180080e01a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP838"              ,	   0x1180080e01a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP839"              ,	   0x1180080e01a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP840"              ,	   0x1180080e01a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP841"              ,	   0x1180080e01a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP842"              ,	   0x1180080e01a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP843"              ,	   0x1180080e01a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP844"              ,	   0x1180080e01a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP845"              ,	   0x1180080e01a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP846"              ,	   0x1180080e01a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP847"              ,	   0x1180080e01a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP848"              ,	   0x1180080e01a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP849"              ,	   0x1180080e01a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP850"              ,	   0x1180080e01a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP851"              ,	   0x1180080e01a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP852"              ,	   0x1180080e01aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP853"              ,	   0x1180080e01aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP854"              ,	   0x1180080e01ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP855"              ,	   0x1180080e01ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP856"              ,	   0x1180080e01ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP857"              ,	   0x1180080e01ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP858"              ,	   0x1180080e01ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP859"              ,	   0x1180080e01ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP860"              ,	   0x1180080e01ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP861"              ,	   0x1180080e01ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP862"              ,	   0x1180080e01af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP863"              ,	   0x1180080e01af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP864"              ,	   0x1180080e01b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP865"              ,	   0x1180080e01b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP866"              ,	   0x1180080e01b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP867"              ,	   0x1180080e01b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP868"              ,	   0x1180080e01b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP869"              ,	   0x1180080e01b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP870"              ,	   0x1180080e01b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP871"              ,	   0x1180080e01b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP872"              ,	   0x1180080e01b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP873"              ,	   0x1180080e01b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP874"              ,	   0x1180080e01b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP875"              ,	   0x1180080e01b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP876"              ,	   0x1180080e01b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP877"              ,	   0x1180080e01b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP878"              ,	   0x1180080e01b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP879"              ,	   0x1180080e01b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP880"              ,	   0x1180080e01b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP881"              ,	   0x1180080e01b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP882"              ,	   0x1180080e01b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP883"              ,	   0x1180080e01b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP884"              ,	   0x1180080e01ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP885"              ,	   0x1180080e01ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP886"              ,	   0x1180080e01bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP887"              ,	   0x1180080e01bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP888"              ,	   0x1180080e01bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP889"              ,	   0x1180080e01bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP890"              ,	   0x1180080e01bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP891"              ,	   0x1180080e01bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP892"              ,	   0x1180080e01be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP893"              ,	   0x1180080e01be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP894"              ,	   0x1180080e01bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP895"              ,	   0x1180080e01bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP896"              ,	   0x1180080e01c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP897"              ,	   0x1180080e01c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP898"              ,	   0x1180080e01c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP899"              ,	   0x1180080e01c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP900"              ,	   0x1180080e01c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP901"              ,	   0x1180080e01c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP902"              ,	   0x1180080e01c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP903"              ,	   0x1180080e01c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP904"              ,	   0x1180080e01c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP905"              ,	   0x1180080e01c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP906"              ,	   0x1180080e01c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP907"              ,	   0x1180080e01c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP908"              ,	   0x1180080e01c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP909"              ,	   0x1180080e01c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP910"              ,	   0x1180080e01c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP911"              ,	   0x1180080e01c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP912"              ,	   0x1180080e01c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP913"              ,	   0x1180080e01c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP914"              ,	   0x1180080e01c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP915"              ,	   0x1180080e01c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP916"              ,	   0x1180080e01ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP917"              ,	   0x1180080e01ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP918"              ,	   0x1180080e01cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP919"              ,	   0x1180080e01cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP920"              ,	   0x1180080e01cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP921"              ,	   0x1180080e01cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP922"              ,	   0x1180080e01cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP923"              ,	   0x1180080e01cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP924"              ,	   0x1180080e01ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP925"              ,	   0x1180080e01ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP926"              ,	   0x1180080e01cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP927"              ,	   0x1180080e01cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP928"              ,	   0x1180080e01d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP929"              ,	   0x1180080e01d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP930"              ,	   0x1180080e01d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP931"              ,	   0x1180080e01d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP932"              ,	   0x1180080e01d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP933"              ,	   0x1180080e01d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP934"              ,	   0x1180080e01d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP935"              ,	   0x1180080e01d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP936"              ,	   0x1180080e01d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP937"              ,	   0x1180080e01d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP938"              ,	   0x1180080e01d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP939"              ,	   0x1180080e01d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP940"              ,	   0x1180080e01d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP941"              ,	   0x1180080e01d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP942"              ,	   0x1180080e01d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP943"              ,	   0x1180080e01d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP944"              ,	   0x1180080e01d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP945"              ,	   0x1180080e01d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP946"              ,	   0x1180080e01d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP947"              ,	   0x1180080e01d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP948"              ,	   0x1180080e01da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP949"              ,	   0x1180080e01da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP950"              ,	   0x1180080e01db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP951"              ,	   0x1180080e01db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP952"              ,	   0x1180080e01dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP953"              ,	   0x1180080e01dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP954"              ,	   0x1180080e01dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP955"              ,	   0x1180080e01dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP956"              ,	   0x1180080e01de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP957"              ,	   0x1180080e01de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP958"              ,	   0x1180080e01df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP959"              ,	   0x1180080e01df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP960"              ,	   0x1180080e01e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP961"              ,	   0x1180080e01e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP962"              ,	   0x1180080e01e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP963"              ,	   0x1180080e01e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP964"              ,	   0x1180080e01e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP965"              ,	   0x1180080e01e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP966"              ,	   0x1180080e01e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP967"              ,	   0x1180080e01e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP968"              ,	   0x1180080e01e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP969"              ,	   0x1180080e01e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP970"              ,	   0x1180080e01e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP971"              ,	   0x1180080e01e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP972"              ,	   0x1180080e01e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP973"              ,	   0x1180080e01e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP974"              ,	   0x1180080e01e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP975"              ,	   0x1180080e01e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP976"              ,	   0x1180080e01e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP977"              ,	   0x1180080e01e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP978"              ,	   0x1180080e01e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP979"              ,	   0x1180080e01e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP980"              ,	   0x1180080e01ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP981"              ,	   0x1180080e01ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP982"              ,	   0x1180080e01eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP983"              ,	   0x1180080e01eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP984"              ,	   0x1180080e01ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP985"              ,	   0x1180080e01ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP986"              ,	   0x1180080e01ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP987"              ,	   0x1180080e01ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP988"              ,	   0x1180080e01ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP989"              ,	   0x1180080e01ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP990"              ,	   0x1180080e01ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP991"              ,	   0x1180080e01ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP992"              ,	   0x1180080e01f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP993"              ,	   0x1180080e01f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP994"              ,	   0x1180080e01f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP995"              ,	   0x1180080e01f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP996"              ,	   0x1180080e01f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP997"              ,	   0x1180080e01f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP998"              ,	   0x1180080e01f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP999"              ,	   0x1180080e01f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1000"             ,	   0x1180080e01f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1001"             ,	   0x1180080e01f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1002"             ,	   0x1180080e01f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1003"             ,	   0x1180080e01f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1004"             ,	   0x1180080e01f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1005"             ,	   0x1180080e01f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1006"             ,	   0x1180080e01f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1007"             ,	   0x1180080e01f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1008"             ,	   0x1180080e01f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1009"             ,	   0x1180080e01f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1010"             ,	   0x1180080e01f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1011"             ,	   0x1180080e01f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1012"             ,	   0x1180080e01fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1013"             ,	   0x1180080e01fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1014"             ,	   0x1180080e01fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1015"             ,	   0x1180080e01fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1016"             ,	   0x1180080e01fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1017"             ,	   0x1180080e01fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1018"             ,	   0x1180080e01fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1019"             ,	   0x1180080e01fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1020"             ,	   0x1180080e01fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1021"             ,	   0x1180080e01fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1022"             ,	   0x1180080e01ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_DUT_MAP1023"             ,	   0x1180080e01ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"L2C_ERR_TDT0"                ,	   0x1180080a007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	482},
+	{"L2C_ERR_TTG0"                ,	   0x1180080a007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	483},
+	{"L2C_ERR_VBF0"                ,	   0x1180080c007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	484},
+	{"L2C_ERR_XMC"                 ,	   0x11800808007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	485},
+	{"L2C_INT_ENA"                 ,	   0x1180080800020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	486},
+	{"L2C_INT_REG"                 ,	   0x1180080800018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	487},
+	{"L2C_IOC0_PFC"                ,	   0x1180080800420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	488},
+	{"L2C_IOR0_PFC"                ,	   0x1180080800428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	489},
+	{"L2C_QOS_IOB0"                ,	   0x1180080880200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	490},
+	{"L2C_QOS_PP0"                 ,	   0x1180080880000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
+	{"L2C_QOS_PP1"                 ,	   0x1180080880008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
+	{"L2C_QOS_PP2"                 ,	   0x1180080880010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
+	{"L2C_QOS_PP3"                 ,	   0x1180080880018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
+	{"L2C_QOS_WGT"                 ,	   0x1180080800008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	492},
+	{"L2C_RSC0_PFC"                ,	   0x1180080800410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	493},
+	{"L2C_RSD0_PFC"                ,	   0x1180080800418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	494},
+	{"L2C_TAD0_ECC0"               ,	   0x1180080a00018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	495},
+	{"L2C_TAD0_ECC1"               ,	   0x1180080a00020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"L2C_TAD0_IEN"                ,	   0x1180080a00000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"L2C_TAD0_INT"                ,	   0x1180080a00028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"L2C_TAD0_PFC0"               ,	   0x1180080a00400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"L2C_TAD0_PFC1"               ,	   0x1180080a00408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"L2C_TAD0_PFC2"               ,	   0x1180080a00410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"L2C_TAD0_PFC3"               ,	   0x1180080a00418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"L2C_TAD0_PRF"                ,	   0x1180080a00008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"L2C_TAD0_TAG"                ,	   0x1180080a00010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"L2C_VER_ID"                  ,	   0x11800808007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"L2C_VER_IOB"                 ,	   0x11800808007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"L2C_VER_MSC"                 ,	   0x11800808007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"L2C_VER_PP"                  ,	   0x11800808007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"L2C_VIRTID_IOB0"             ,	   0x11800808c0200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"L2C_VIRTID_PP0"              ,	   0x11800808c0000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"L2C_VIRTID_PP1"              ,	   0x11800808c0008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"L2C_VIRTID_PP2"              ,	   0x11800808c0010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"L2C_VIRTID_PP3"              ,	   0x11800808c0018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"L2C_VRT_CTL"                 ,	   0x1180080800010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"L2C_VRT_MEM0"                ,	   0x1180080900000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1"                ,	   0x1180080900008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM2"                ,	   0x1180080900010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM3"                ,	   0x1180080900018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM4"                ,	   0x1180080900020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM5"                ,	   0x1180080900028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM6"                ,	   0x1180080900030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM7"                ,	   0x1180080900038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM8"                ,	   0x1180080900040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM9"                ,	   0x1180080900048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM10"               ,	   0x1180080900050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM11"               ,	   0x1180080900058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM12"               ,	   0x1180080900060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM13"               ,	   0x1180080900068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM14"               ,	   0x1180080900070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM15"               ,	   0x1180080900078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM16"               ,	   0x1180080900080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM17"               ,	   0x1180080900088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM18"               ,	   0x1180080900090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM19"               ,	   0x1180080900098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM20"               ,	   0x11800809000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM21"               ,	   0x11800809000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM22"               ,	   0x11800809000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM23"               ,	   0x11800809000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM24"               ,	   0x11800809000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM25"               ,	   0x11800809000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM26"               ,	   0x11800809000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM27"               ,	   0x11800809000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM28"               ,	   0x11800809000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM29"               ,	   0x11800809000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM30"               ,	   0x11800809000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM31"               ,	   0x11800809000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM32"               ,	   0x1180080900100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM33"               ,	   0x1180080900108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM34"               ,	   0x1180080900110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM35"               ,	   0x1180080900118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM36"               ,	   0x1180080900120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM37"               ,	   0x1180080900128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM38"               ,	   0x1180080900130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM39"               ,	   0x1180080900138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM40"               ,	   0x1180080900140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM41"               ,	   0x1180080900148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM42"               ,	   0x1180080900150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM43"               ,	   0x1180080900158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM44"               ,	   0x1180080900160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM45"               ,	   0x1180080900168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM46"               ,	   0x1180080900170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM47"               ,	   0x1180080900178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM48"               ,	   0x1180080900180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM49"               ,	   0x1180080900188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM50"               ,	   0x1180080900190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM51"               ,	   0x1180080900198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM52"               ,	   0x11800809001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM53"               ,	   0x11800809001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM54"               ,	   0x11800809001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM55"               ,	   0x11800809001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM56"               ,	   0x11800809001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM57"               ,	   0x11800809001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM58"               ,	   0x11800809001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM59"               ,	   0x11800809001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM60"               ,	   0x11800809001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM61"               ,	   0x11800809001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM62"               ,	   0x11800809001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM63"               ,	   0x11800809001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM64"               ,	   0x1180080900200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM65"               ,	   0x1180080900208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM66"               ,	   0x1180080900210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM67"               ,	   0x1180080900218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM68"               ,	   0x1180080900220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM69"               ,	   0x1180080900228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM70"               ,	   0x1180080900230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM71"               ,	   0x1180080900238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM72"               ,	   0x1180080900240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM73"               ,	   0x1180080900248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM74"               ,	   0x1180080900250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM75"               ,	   0x1180080900258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM76"               ,	   0x1180080900260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM77"               ,	   0x1180080900268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM78"               ,	   0x1180080900270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM79"               ,	   0x1180080900278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM80"               ,	   0x1180080900280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM81"               ,	   0x1180080900288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM82"               ,	   0x1180080900290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM83"               ,	   0x1180080900298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM84"               ,	   0x11800809002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM85"               ,	   0x11800809002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM86"               ,	   0x11800809002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM87"               ,	   0x11800809002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM88"               ,	   0x11800809002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM89"               ,	   0x11800809002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM90"               ,	   0x11800809002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM91"               ,	   0x11800809002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM92"               ,	   0x11800809002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM93"               ,	   0x11800809002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM94"               ,	   0x11800809002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM95"               ,	   0x11800809002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM96"               ,	   0x1180080900300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM97"               ,	   0x1180080900308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM98"               ,	   0x1180080900310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM99"               ,	   0x1180080900318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM100"              ,	   0x1180080900320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM101"              ,	   0x1180080900328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM102"              ,	   0x1180080900330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM103"              ,	   0x1180080900338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM104"              ,	   0x1180080900340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM105"              ,	   0x1180080900348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM106"              ,	   0x1180080900350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM107"              ,	   0x1180080900358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM108"              ,	   0x1180080900360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM109"              ,	   0x1180080900368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM110"              ,	   0x1180080900370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM111"              ,	   0x1180080900378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM112"              ,	   0x1180080900380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM113"              ,	   0x1180080900388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM114"              ,	   0x1180080900390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM115"              ,	   0x1180080900398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM116"              ,	   0x11800809003a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM117"              ,	   0x11800809003a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM118"              ,	   0x11800809003b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM119"              ,	   0x11800809003b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM120"              ,	   0x11800809003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM121"              ,	   0x11800809003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM122"              ,	   0x11800809003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM123"              ,	   0x11800809003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM124"              ,	   0x11800809003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM125"              ,	   0x11800809003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM126"              ,	   0x11800809003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM127"              ,	   0x11800809003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM128"              ,	   0x1180080900400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM129"              ,	   0x1180080900408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM130"              ,	   0x1180080900410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM131"              ,	   0x1180080900418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM132"              ,	   0x1180080900420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM133"              ,	   0x1180080900428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM134"              ,	   0x1180080900430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM135"              ,	   0x1180080900438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM136"              ,	   0x1180080900440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM137"              ,	   0x1180080900448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM138"              ,	   0x1180080900450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM139"              ,	   0x1180080900458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM140"              ,	   0x1180080900460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM141"              ,	   0x1180080900468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM142"              ,	   0x1180080900470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM143"              ,	   0x1180080900478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM144"              ,	   0x1180080900480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM145"              ,	   0x1180080900488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM146"              ,	   0x1180080900490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM147"              ,	   0x1180080900498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM148"              ,	   0x11800809004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM149"              ,	   0x11800809004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM150"              ,	   0x11800809004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM151"              ,	   0x11800809004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM152"              ,	   0x11800809004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM153"              ,	   0x11800809004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM154"              ,	   0x11800809004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM155"              ,	   0x11800809004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM156"              ,	   0x11800809004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM157"              ,	   0x11800809004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM158"              ,	   0x11800809004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM159"              ,	   0x11800809004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM160"              ,	   0x1180080900500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM161"              ,	   0x1180080900508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM162"              ,	   0x1180080900510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM163"              ,	   0x1180080900518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM164"              ,	   0x1180080900520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM165"              ,	   0x1180080900528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM166"              ,	   0x1180080900530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM167"              ,	   0x1180080900538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM168"              ,	   0x1180080900540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM169"              ,	   0x1180080900548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM170"              ,	   0x1180080900550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM171"              ,	   0x1180080900558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM172"              ,	   0x1180080900560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM173"              ,	   0x1180080900568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM174"              ,	   0x1180080900570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM175"              ,	   0x1180080900578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM176"              ,	   0x1180080900580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM177"              ,	   0x1180080900588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM178"              ,	   0x1180080900590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM179"              ,	   0x1180080900598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM180"              ,	   0x11800809005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM181"              ,	   0x11800809005a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM182"              ,	   0x11800809005b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM183"              ,	   0x11800809005b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM184"              ,	   0x11800809005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM185"              ,	   0x11800809005c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM186"              ,	   0x11800809005d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM187"              ,	   0x11800809005d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM188"              ,	   0x11800809005e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM189"              ,	   0x11800809005e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM190"              ,	   0x11800809005f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM191"              ,	   0x11800809005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM192"              ,	   0x1180080900600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM193"              ,	   0x1180080900608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM194"              ,	   0x1180080900610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM195"              ,	   0x1180080900618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM196"              ,	   0x1180080900620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM197"              ,	   0x1180080900628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM198"              ,	   0x1180080900630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM199"              ,	   0x1180080900638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM200"              ,	   0x1180080900640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM201"              ,	   0x1180080900648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM202"              ,	   0x1180080900650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM203"              ,	   0x1180080900658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM204"              ,	   0x1180080900660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM205"              ,	   0x1180080900668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM206"              ,	   0x1180080900670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM207"              ,	   0x1180080900678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM208"              ,	   0x1180080900680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM209"              ,	   0x1180080900688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM210"              ,	   0x1180080900690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM211"              ,	   0x1180080900698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM212"              ,	   0x11800809006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM213"              ,	   0x11800809006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM214"              ,	   0x11800809006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM215"              ,	   0x11800809006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM216"              ,	   0x11800809006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM217"              ,	   0x11800809006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM218"              ,	   0x11800809006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM219"              ,	   0x11800809006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM220"              ,	   0x11800809006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM221"              ,	   0x11800809006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM222"              ,	   0x11800809006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM223"              ,	   0x11800809006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM224"              ,	   0x1180080900700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM225"              ,	   0x1180080900708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM226"              ,	   0x1180080900710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM227"              ,	   0x1180080900718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM228"              ,	   0x1180080900720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM229"              ,	   0x1180080900728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM230"              ,	   0x1180080900730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM231"              ,	   0x1180080900738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM232"              ,	   0x1180080900740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM233"              ,	   0x1180080900748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM234"              ,	   0x1180080900750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM235"              ,	   0x1180080900758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM236"              ,	   0x1180080900760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM237"              ,	   0x1180080900768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM238"              ,	   0x1180080900770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM239"              ,	   0x1180080900778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM240"              ,	   0x1180080900780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM241"              ,	   0x1180080900788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM242"              ,	   0x1180080900790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM243"              ,	   0x1180080900798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM244"              ,	   0x11800809007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM245"              ,	   0x11800809007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM246"              ,	   0x11800809007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM247"              ,	   0x11800809007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM248"              ,	   0x11800809007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM249"              ,	   0x11800809007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM250"              ,	   0x11800809007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM251"              ,	   0x11800809007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM252"              ,	   0x11800809007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM253"              ,	   0x11800809007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM254"              ,	   0x11800809007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM255"              ,	   0x11800809007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM256"              ,	   0x1180080900800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM257"              ,	   0x1180080900808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM258"              ,	   0x1180080900810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM259"              ,	   0x1180080900818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM260"              ,	   0x1180080900820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM261"              ,	   0x1180080900828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM262"              ,	   0x1180080900830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM263"              ,	   0x1180080900838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM264"              ,	   0x1180080900840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM265"              ,	   0x1180080900848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM266"              ,	   0x1180080900850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM267"              ,	   0x1180080900858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM268"              ,	   0x1180080900860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM269"              ,	   0x1180080900868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM270"              ,	   0x1180080900870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM271"              ,	   0x1180080900878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM272"              ,	   0x1180080900880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM273"              ,	   0x1180080900888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM274"              ,	   0x1180080900890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM275"              ,	   0x1180080900898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM276"              ,	   0x11800809008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM277"              ,	   0x11800809008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM278"              ,	   0x11800809008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM279"              ,	   0x11800809008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM280"              ,	   0x11800809008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM281"              ,	   0x11800809008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM282"              ,	   0x11800809008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM283"              ,	   0x11800809008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM284"              ,	   0x11800809008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM285"              ,	   0x11800809008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM286"              ,	   0x11800809008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM287"              ,	   0x11800809008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM288"              ,	   0x1180080900900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM289"              ,	   0x1180080900908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM290"              ,	   0x1180080900910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM291"              ,	   0x1180080900918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM292"              ,	   0x1180080900920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM293"              ,	   0x1180080900928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM294"              ,	   0x1180080900930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM295"              ,	   0x1180080900938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM296"              ,	   0x1180080900940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM297"              ,	   0x1180080900948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM298"              ,	   0x1180080900950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM299"              ,	   0x1180080900958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM300"              ,	   0x1180080900960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM301"              ,	   0x1180080900968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM302"              ,	   0x1180080900970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM303"              ,	   0x1180080900978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM304"              ,	   0x1180080900980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM305"              ,	   0x1180080900988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM306"              ,	   0x1180080900990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM307"              ,	   0x1180080900998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM308"              ,	   0x11800809009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM309"              ,	   0x11800809009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM310"              ,	   0x11800809009b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM311"              ,	   0x11800809009b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM312"              ,	   0x11800809009c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM313"              ,	   0x11800809009c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM314"              ,	   0x11800809009d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM315"              ,	   0x11800809009d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM316"              ,	   0x11800809009e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM317"              ,	   0x11800809009e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM318"              ,	   0x11800809009f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM319"              ,	   0x11800809009f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM320"              ,	   0x1180080900a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM321"              ,	   0x1180080900a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM322"              ,	   0x1180080900a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM323"              ,	   0x1180080900a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM324"              ,	   0x1180080900a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM325"              ,	   0x1180080900a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM326"              ,	   0x1180080900a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM327"              ,	   0x1180080900a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM328"              ,	   0x1180080900a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM329"              ,	   0x1180080900a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM330"              ,	   0x1180080900a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM331"              ,	   0x1180080900a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM332"              ,	   0x1180080900a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM333"              ,	   0x1180080900a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM334"              ,	   0x1180080900a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM335"              ,	   0x1180080900a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM336"              ,	   0x1180080900a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM337"              ,	   0x1180080900a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM338"              ,	   0x1180080900a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM339"              ,	   0x1180080900a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM340"              ,	   0x1180080900aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM341"              ,	   0x1180080900aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM342"              ,	   0x1180080900ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM343"              ,	   0x1180080900ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM344"              ,	   0x1180080900ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM345"              ,	   0x1180080900ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM346"              ,	   0x1180080900ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM347"              ,	   0x1180080900ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM348"              ,	   0x1180080900ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM349"              ,	   0x1180080900ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM350"              ,	   0x1180080900af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM351"              ,	   0x1180080900af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM352"              ,	   0x1180080900b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM353"              ,	   0x1180080900b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM354"              ,	   0x1180080900b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM355"              ,	   0x1180080900b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM356"              ,	   0x1180080900b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM357"              ,	   0x1180080900b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM358"              ,	   0x1180080900b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM359"              ,	   0x1180080900b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM360"              ,	   0x1180080900b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM361"              ,	   0x1180080900b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM362"              ,	   0x1180080900b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM363"              ,	   0x1180080900b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM364"              ,	   0x1180080900b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM365"              ,	   0x1180080900b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM366"              ,	   0x1180080900b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM367"              ,	   0x1180080900b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM368"              ,	   0x1180080900b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM369"              ,	   0x1180080900b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM370"              ,	   0x1180080900b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM371"              ,	   0x1180080900b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM372"              ,	   0x1180080900ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM373"              ,	   0x1180080900ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM374"              ,	   0x1180080900bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM375"              ,	   0x1180080900bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM376"              ,	   0x1180080900bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM377"              ,	   0x1180080900bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM378"              ,	   0x1180080900bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM379"              ,	   0x1180080900bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM380"              ,	   0x1180080900be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM381"              ,	   0x1180080900be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM382"              ,	   0x1180080900bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM383"              ,	   0x1180080900bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM384"              ,	   0x1180080900c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM385"              ,	   0x1180080900c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM386"              ,	   0x1180080900c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM387"              ,	   0x1180080900c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM388"              ,	   0x1180080900c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM389"              ,	   0x1180080900c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM390"              ,	   0x1180080900c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM391"              ,	   0x1180080900c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM392"              ,	   0x1180080900c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM393"              ,	   0x1180080900c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM394"              ,	   0x1180080900c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM395"              ,	   0x1180080900c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM396"              ,	   0x1180080900c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM397"              ,	   0x1180080900c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM398"              ,	   0x1180080900c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM399"              ,	   0x1180080900c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM400"              ,	   0x1180080900c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM401"              ,	   0x1180080900c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM402"              ,	   0x1180080900c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM403"              ,	   0x1180080900c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM404"              ,	   0x1180080900ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM405"              ,	   0x1180080900ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM406"              ,	   0x1180080900cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM407"              ,	   0x1180080900cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM408"              ,	   0x1180080900cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM409"              ,	   0x1180080900cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM410"              ,	   0x1180080900cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM411"              ,	   0x1180080900cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM412"              ,	   0x1180080900ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM413"              ,	   0x1180080900ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM414"              ,	   0x1180080900cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM415"              ,	   0x1180080900cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM416"              ,	   0x1180080900d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM417"              ,	   0x1180080900d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM418"              ,	   0x1180080900d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM419"              ,	   0x1180080900d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM420"              ,	   0x1180080900d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM421"              ,	   0x1180080900d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM422"              ,	   0x1180080900d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM423"              ,	   0x1180080900d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM424"              ,	   0x1180080900d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM425"              ,	   0x1180080900d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM426"              ,	   0x1180080900d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM427"              ,	   0x1180080900d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM428"              ,	   0x1180080900d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM429"              ,	   0x1180080900d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM430"              ,	   0x1180080900d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM431"              ,	   0x1180080900d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM432"              ,	   0x1180080900d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM433"              ,	   0x1180080900d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM434"              ,	   0x1180080900d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM435"              ,	   0x1180080900d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM436"              ,	   0x1180080900da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM437"              ,	   0x1180080900da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM438"              ,	   0x1180080900db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM439"              ,	   0x1180080900db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM440"              ,	   0x1180080900dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM441"              ,	   0x1180080900dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM442"              ,	   0x1180080900dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM443"              ,	   0x1180080900dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM444"              ,	   0x1180080900de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM445"              ,	   0x1180080900de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM446"              ,	   0x1180080900df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM447"              ,	   0x1180080900df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM448"              ,	   0x1180080900e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM449"              ,	   0x1180080900e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM450"              ,	   0x1180080900e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM451"              ,	   0x1180080900e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM452"              ,	   0x1180080900e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM453"              ,	   0x1180080900e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM454"              ,	   0x1180080900e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM455"              ,	   0x1180080900e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM456"              ,	   0x1180080900e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM457"              ,	   0x1180080900e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM458"              ,	   0x1180080900e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM459"              ,	   0x1180080900e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM460"              ,	   0x1180080900e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM461"              ,	   0x1180080900e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM462"              ,	   0x1180080900e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM463"              ,	   0x1180080900e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM464"              ,	   0x1180080900e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM465"              ,	   0x1180080900e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM466"              ,	   0x1180080900e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM467"              ,	   0x1180080900e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM468"              ,	   0x1180080900ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM469"              ,	   0x1180080900ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM470"              ,	   0x1180080900eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM471"              ,	   0x1180080900eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM472"              ,	   0x1180080900ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM473"              ,	   0x1180080900ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM474"              ,	   0x1180080900ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM475"              ,	   0x1180080900ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM476"              ,	   0x1180080900ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM477"              ,	   0x1180080900ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM478"              ,	   0x1180080900ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM479"              ,	   0x1180080900ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM480"              ,	   0x1180080900f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM481"              ,	   0x1180080900f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM482"              ,	   0x1180080900f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM483"              ,	   0x1180080900f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM484"              ,	   0x1180080900f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM485"              ,	   0x1180080900f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM486"              ,	   0x1180080900f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM487"              ,	   0x1180080900f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM488"              ,	   0x1180080900f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM489"              ,	   0x1180080900f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM490"              ,	   0x1180080900f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM491"              ,	   0x1180080900f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM492"              ,	   0x1180080900f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM493"              ,	   0x1180080900f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM494"              ,	   0x1180080900f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM495"              ,	   0x1180080900f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM496"              ,	   0x1180080900f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM497"              ,	   0x1180080900f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM498"              ,	   0x1180080900f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM499"              ,	   0x1180080900f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM500"              ,	   0x1180080900fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM501"              ,	   0x1180080900fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM502"              ,	   0x1180080900fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM503"              ,	   0x1180080900fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM504"              ,	   0x1180080900fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM505"              ,	   0x1180080900fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM506"              ,	   0x1180080900fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM507"              ,	   0x1180080900fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM508"              ,	   0x1180080900fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM509"              ,	   0x1180080900fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM510"              ,	   0x1180080900ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM511"              ,	   0x1180080900ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM512"              ,	   0x1180080901000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM513"              ,	   0x1180080901008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM514"              ,	   0x1180080901010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM515"              ,	   0x1180080901018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM516"              ,	   0x1180080901020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM517"              ,	   0x1180080901028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM518"              ,	   0x1180080901030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM519"              ,	   0x1180080901038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM520"              ,	   0x1180080901040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM521"              ,	   0x1180080901048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM522"              ,	   0x1180080901050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM523"              ,	   0x1180080901058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM524"              ,	   0x1180080901060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM525"              ,	   0x1180080901068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM526"              ,	   0x1180080901070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM527"              ,	   0x1180080901078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM528"              ,	   0x1180080901080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM529"              ,	   0x1180080901088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM530"              ,	   0x1180080901090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM531"              ,	   0x1180080901098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM532"              ,	   0x11800809010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM533"              ,	   0x11800809010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM534"              ,	   0x11800809010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM535"              ,	   0x11800809010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM536"              ,	   0x11800809010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM537"              ,	   0x11800809010c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM538"              ,	   0x11800809010d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM539"              ,	   0x11800809010d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM540"              ,	   0x11800809010e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM541"              ,	   0x11800809010e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM542"              ,	   0x11800809010f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM543"              ,	   0x11800809010f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM544"              ,	   0x1180080901100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM545"              ,	   0x1180080901108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM546"              ,	   0x1180080901110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM547"              ,	   0x1180080901118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM548"              ,	   0x1180080901120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM549"              ,	   0x1180080901128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM550"              ,	   0x1180080901130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM551"              ,	   0x1180080901138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM552"              ,	   0x1180080901140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM553"              ,	   0x1180080901148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM554"              ,	   0x1180080901150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM555"              ,	   0x1180080901158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM556"              ,	   0x1180080901160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM557"              ,	   0x1180080901168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM558"              ,	   0x1180080901170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM559"              ,	   0x1180080901178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM560"              ,	   0x1180080901180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM561"              ,	   0x1180080901188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM562"              ,	   0x1180080901190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM563"              ,	   0x1180080901198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM564"              ,	   0x11800809011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM565"              ,	   0x11800809011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM566"              ,	   0x11800809011b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM567"              ,	   0x11800809011b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM568"              ,	   0x11800809011c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM569"              ,	   0x11800809011c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM570"              ,	   0x11800809011d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM571"              ,	   0x11800809011d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM572"              ,	   0x11800809011e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM573"              ,	   0x11800809011e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM574"              ,	   0x11800809011f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM575"              ,	   0x11800809011f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM576"              ,	   0x1180080901200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM577"              ,	   0x1180080901208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM578"              ,	   0x1180080901210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM579"              ,	   0x1180080901218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM580"              ,	   0x1180080901220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM581"              ,	   0x1180080901228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM582"              ,	   0x1180080901230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM583"              ,	   0x1180080901238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM584"              ,	   0x1180080901240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM585"              ,	   0x1180080901248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM586"              ,	   0x1180080901250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM587"              ,	   0x1180080901258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM588"              ,	   0x1180080901260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM589"              ,	   0x1180080901268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM590"              ,	   0x1180080901270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM591"              ,	   0x1180080901278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM592"              ,	   0x1180080901280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM593"              ,	   0x1180080901288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM594"              ,	   0x1180080901290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM595"              ,	   0x1180080901298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM596"              ,	   0x11800809012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM597"              ,	   0x11800809012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM598"              ,	   0x11800809012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM599"              ,	   0x11800809012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM600"              ,	   0x11800809012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM601"              ,	   0x11800809012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM602"              ,	   0x11800809012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM603"              ,	   0x11800809012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM604"              ,	   0x11800809012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM605"              ,	   0x11800809012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM606"              ,	   0x11800809012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM607"              ,	   0x11800809012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM608"              ,	   0x1180080901300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM609"              ,	   0x1180080901308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM610"              ,	   0x1180080901310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM611"              ,	   0x1180080901318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM612"              ,	   0x1180080901320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM613"              ,	   0x1180080901328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM614"              ,	   0x1180080901330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM615"              ,	   0x1180080901338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM616"              ,	   0x1180080901340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM617"              ,	   0x1180080901348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM618"              ,	   0x1180080901350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM619"              ,	   0x1180080901358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM620"              ,	   0x1180080901360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM621"              ,	   0x1180080901368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM622"              ,	   0x1180080901370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM623"              ,	   0x1180080901378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM624"              ,	   0x1180080901380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM625"              ,	   0x1180080901388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM626"              ,	   0x1180080901390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM627"              ,	   0x1180080901398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM628"              ,	   0x11800809013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM629"              ,	   0x11800809013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM630"              ,	   0x11800809013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM631"              ,	   0x11800809013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM632"              ,	   0x11800809013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM633"              ,	   0x11800809013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM634"              ,	   0x11800809013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM635"              ,	   0x11800809013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM636"              ,	   0x11800809013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM637"              ,	   0x11800809013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM638"              ,	   0x11800809013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM639"              ,	   0x11800809013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM640"              ,	   0x1180080901400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM641"              ,	   0x1180080901408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM642"              ,	   0x1180080901410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM643"              ,	   0x1180080901418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM644"              ,	   0x1180080901420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM645"              ,	   0x1180080901428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM646"              ,	   0x1180080901430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM647"              ,	   0x1180080901438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM648"              ,	   0x1180080901440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM649"              ,	   0x1180080901448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM650"              ,	   0x1180080901450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM651"              ,	   0x1180080901458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM652"              ,	   0x1180080901460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM653"              ,	   0x1180080901468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM654"              ,	   0x1180080901470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM655"              ,	   0x1180080901478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM656"              ,	   0x1180080901480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM657"              ,	   0x1180080901488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM658"              ,	   0x1180080901490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM659"              ,	   0x1180080901498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM660"              ,	   0x11800809014a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM661"              ,	   0x11800809014a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM662"              ,	   0x11800809014b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM663"              ,	   0x11800809014b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM664"              ,	   0x11800809014c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM665"              ,	   0x11800809014c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM666"              ,	   0x11800809014d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM667"              ,	   0x11800809014d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM668"              ,	   0x11800809014e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM669"              ,	   0x11800809014e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM670"              ,	   0x11800809014f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM671"              ,	   0x11800809014f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM672"              ,	   0x1180080901500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM673"              ,	   0x1180080901508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM674"              ,	   0x1180080901510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM675"              ,	   0x1180080901518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM676"              ,	   0x1180080901520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM677"              ,	   0x1180080901528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM678"              ,	   0x1180080901530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM679"              ,	   0x1180080901538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM680"              ,	   0x1180080901540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM681"              ,	   0x1180080901548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM682"              ,	   0x1180080901550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM683"              ,	   0x1180080901558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM684"              ,	   0x1180080901560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM685"              ,	   0x1180080901568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM686"              ,	   0x1180080901570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM687"              ,	   0x1180080901578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM688"              ,	   0x1180080901580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM689"              ,	   0x1180080901588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM690"              ,	   0x1180080901590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM691"              ,	   0x1180080901598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM692"              ,	   0x11800809015a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM693"              ,	   0x11800809015a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM694"              ,	   0x11800809015b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM695"              ,	   0x11800809015b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM696"              ,	   0x11800809015c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM697"              ,	   0x11800809015c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM698"              ,	   0x11800809015d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM699"              ,	   0x11800809015d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM700"              ,	   0x11800809015e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM701"              ,	   0x11800809015e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM702"              ,	   0x11800809015f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM703"              ,	   0x11800809015f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM704"              ,	   0x1180080901600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM705"              ,	   0x1180080901608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM706"              ,	   0x1180080901610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM707"              ,	   0x1180080901618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM708"              ,	   0x1180080901620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM709"              ,	   0x1180080901628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM710"              ,	   0x1180080901630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM711"              ,	   0x1180080901638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM712"              ,	   0x1180080901640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM713"              ,	   0x1180080901648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM714"              ,	   0x1180080901650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM715"              ,	   0x1180080901658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM716"              ,	   0x1180080901660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM717"              ,	   0x1180080901668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM718"              ,	   0x1180080901670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM719"              ,	   0x1180080901678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM720"              ,	   0x1180080901680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM721"              ,	   0x1180080901688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM722"              ,	   0x1180080901690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM723"              ,	   0x1180080901698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM724"              ,	   0x11800809016a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM725"              ,	   0x11800809016a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM726"              ,	   0x11800809016b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM727"              ,	   0x11800809016b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM728"              ,	   0x11800809016c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM729"              ,	   0x11800809016c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM730"              ,	   0x11800809016d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM731"              ,	   0x11800809016d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM732"              ,	   0x11800809016e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM733"              ,	   0x11800809016e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM734"              ,	   0x11800809016f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM735"              ,	   0x11800809016f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM736"              ,	   0x1180080901700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM737"              ,	   0x1180080901708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM738"              ,	   0x1180080901710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM739"              ,	   0x1180080901718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM740"              ,	   0x1180080901720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM741"              ,	   0x1180080901728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM742"              ,	   0x1180080901730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM743"              ,	   0x1180080901738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM744"              ,	   0x1180080901740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM745"              ,	   0x1180080901748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM746"              ,	   0x1180080901750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM747"              ,	   0x1180080901758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM748"              ,	   0x1180080901760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM749"              ,	   0x1180080901768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM750"              ,	   0x1180080901770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM751"              ,	   0x1180080901778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM752"              ,	   0x1180080901780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM753"              ,	   0x1180080901788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM754"              ,	   0x1180080901790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM755"              ,	   0x1180080901798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM756"              ,	   0x11800809017a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM757"              ,	   0x11800809017a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM758"              ,	   0x11800809017b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM759"              ,	   0x11800809017b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM760"              ,	   0x11800809017c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM761"              ,	   0x11800809017c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM762"              ,	   0x11800809017d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM763"              ,	   0x11800809017d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM764"              ,	   0x11800809017e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM765"              ,	   0x11800809017e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM766"              ,	   0x11800809017f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM767"              ,	   0x11800809017f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM768"              ,	   0x1180080901800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM769"              ,	   0x1180080901808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM770"              ,	   0x1180080901810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM771"              ,	   0x1180080901818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM772"              ,	   0x1180080901820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM773"              ,	   0x1180080901828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM774"              ,	   0x1180080901830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM775"              ,	   0x1180080901838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM776"              ,	   0x1180080901840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM777"              ,	   0x1180080901848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM778"              ,	   0x1180080901850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM779"              ,	   0x1180080901858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM780"              ,	   0x1180080901860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM781"              ,	   0x1180080901868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM782"              ,	   0x1180080901870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM783"              ,	   0x1180080901878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM784"              ,	   0x1180080901880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM785"              ,	   0x1180080901888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM786"              ,	   0x1180080901890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM787"              ,	   0x1180080901898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM788"              ,	   0x11800809018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM789"              ,	   0x11800809018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM790"              ,	   0x11800809018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM791"              ,	   0x11800809018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM792"              ,	   0x11800809018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM793"              ,	   0x11800809018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM794"              ,	   0x11800809018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM795"              ,	   0x11800809018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM796"              ,	   0x11800809018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM797"              ,	   0x11800809018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM798"              ,	   0x11800809018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM799"              ,	   0x11800809018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM800"              ,	   0x1180080901900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM801"              ,	   0x1180080901908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM802"              ,	   0x1180080901910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM803"              ,	   0x1180080901918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM804"              ,	   0x1180080901920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM805"              ,	   0x1180080901928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM806"              ,	   0x1180080901930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM807"              ,	   0x1180080901938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM808"              ,	   0x1180080901940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM809"              ,	   0x1180080901948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM810"              ,	   0x1180080901950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM811"              ,	   0x1180080901958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM812"              ,	   0x1180080901960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM813"              ,	   0x1180080901968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM814"              ,	   0x1180080901970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM815"              ,	   0x1180080901978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM816"              ,	   0x1180080901980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM817"              ,	   0x1180080901988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM818"              ,	   0x1180080901990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM819"              ,	   0x1180080901998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM820"              ,	   0x11800809019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM821"              ,	   0x11800809019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM822"              ,	   0x11800809019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM823"              ,	   0x11800809019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM824"              ,	   0x11800809019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM825"              ,	   0x11800809019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM826"              ,	   0x11800809019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM827"              ,	   0x11800809019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM828"              ,	   0x11800809019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM829"              ,	   0x11800809019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM830"              ,	   0x11800809019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM831"              ,	   0x11800809019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM832"              ,	   0x1180080901a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM833"              ,	   0x1180080901a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM834"              ,	   0x1180080901a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM835"              ,	   0x1180080901a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM836"              ,	   0x1180080901a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM837"              ,	   0x1180080901a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM838"              ,	   0x1180080901a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM839"              ,	   0x1180080901a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM840"              ,	   0x1180080901a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM841"              ,	   0x1180080901a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM842"              ,	   0x1180080901a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM843"              ,	   0x1180080901a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM844"              ,	   0x1180080901a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM845"              ,	   0x1180080901a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM846"              ,	   0x1180080901a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM847"              ,	   0x1180080901a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM848"              ,	   0x1180080901a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM849"              ,	   0x1180080901a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM850"              ,	   0x1180080901a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM851"              ,	   0x1180080901a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM852"              ,	   0x1180080901aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM853"              ,	   0x1180080901aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM854"              ,	   0x1180080901ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM855"              ,	   0x1180080901ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM856"              ,	   0x1180080901ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM857"              ,	   0x1180080901ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM858"              ,	   0x1180080901ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM859"              ,	   0x1180080901ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM860"              ,	   0x1180080901ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM861"              ,	   0x1180080901ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM862"              ,	   0x1180080901af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM863"              ,	   0x1180080901af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM864"              ,	   0x1180080901b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM865"              ,	   0x1180080901b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM866"              ,	   0x1180080901b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM867"              ,	   0x1180080901b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM868"              ,	   0x1180080901b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM869"              ,	   0x1180080901b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM870"              ,	   0x1180080901b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM871"              ,	   0x1180080901b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM872"              ,	   0x1180080901b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM873"              ,	   0x1180080901b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM874"              ,	   0x1180080901b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM875"              ,	   0x1180080901b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM876"              ,	   0x1180080901b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM877"              ,	   0x1180080901b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM878"              ,	   0x1180080901b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM879"              ,	   0x1180080901b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM880"              ,	   0x1180080901b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM881"              ,	   0x1180080901b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM882"              ,	   0x1180080901b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM883"              ,	   0x1180080901b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM884"              ,	   0x1180080901ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM885"              ,	   0x1180080901ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM886"              ,	   0x1180080901bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM887"              ,	   0x1180080901bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM888"              ,	   0x1180080901bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM889"              ,	   0x1180080901bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM890"              ,	   0x1180080901bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM891"              ,	   0x1180080901bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM892"              ,	   0x1180080901be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM893"              ,	   0x1180080901be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM894"              ,	   0x1180080901bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM895"              ,	   0x1180080901bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM896"              ,	   0x1180080901c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM897"              ,	   0x1180080901c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM898"              ,	   0x1180080901c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM899"              ,	   0x1180080901c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM900"              ,	   0x1180080901c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM901"              ,	   0x1180080901c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM902"              ,	   0x1180080901c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM903"              ,	   0x1180080901c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM904"              ,	   0x1180080901c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM905"              ,	   0x1180080901c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM906"              ,	   0x1180080901c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM907"              ,	   0x1180080901c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM908"              ,	   0x1180080901c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM909"              ,	   0x1180080901c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM910"              ,	   0x1180080901c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM911"              ,	   0x1180080901c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM912"              ,	   0x1180080901c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM913"              ,	   0x1180080901c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM914"              ,	   0x1180080901c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM915"              ,	   0x1180080901c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM916"              ,	   0x1180080901ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM917"              ,	   0x1180080901ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM918"              ,	   0x1180080901cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM919"              ,	   0x1180080901cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM920"              ,	   0x1180080901cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM921"              ,	   0x1180080901cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM922"              ,	   0x1180080901cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM923"              ,	   0x1180080901cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM924"              ,	   0x1180080901ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM925"              ,	   0x1180080901ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM926"              ,	   0x1180080901cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM927"              ,	   0x1180080901cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM928"              ,	   0x1180080901d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM929"              ,	   0x1180080901d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM930"              ,	   0x1180080901d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM931"              ,	   0x1180080901d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM932"              ,	   0x1180080901d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM933"              ,	   0x1180080901d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM934"              ,	   0x1180080901d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM935"              ,	   0x1180080901d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM936"              ,	   0x1180080901d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM937"              ,	   0x1180080901d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM938"              ,	   0x1180080901d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM939"              ,	   0x1180080901d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM940"              ,	   0x1180080901d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM941"              ,	   0x1180080901d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM942"              ,	   0x1180080901d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM943"              ,	   0x1180080901d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM944"              ,	   0x1180080901d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM945"              ,	   0x1180080901d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM946"              ,	   0x1180080901d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM947"              ,	   0x1180080901d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM948"              ,	   0x1180080901da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM949"              ,	   0x1180080901da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM950"              ,	   0x1180080901db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM951"              ,	   0x1180080901db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM952"              ,	   0x1180080901dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM953"              ,	   0x1180080901dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM954"              ,	   0x1180080901dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM955"              ,	   0x1180080901dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM956"              ,	   0x1180080901de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM957"              ,	   0x1180080901de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM958"              ,	   0x1180080901df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM959"              ,	   0x1180080901df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM960"              ,	   0x1180080901e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM961"              ,	   0x1180080901e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM962"              ,	   0x1180080901e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM963"              ,	   0x1180080901e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM964"              ,	   0x1180080901e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM965"              ,	   0x1180080901e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM966"              ,	   0x1180080901e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM967"              ,	   0x1180080901e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM968"              ,	   0x1180080901e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM969"              ,	   0x1180080901e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM970"              ,	   0x1180080901e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM971"              ,	   0x1180080901e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM972"              ,	   0x1180080901e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM973"              ,	   0x1180080901e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM974"              ,	   0x1180080901e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM975"              ,	   0x1180080901e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM976"              ,	   0x1180080901e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM977"              ,	   0x1180080901e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM978"              ,	   0x1180080901e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM979"              ,	   0x1180080901e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM980"              ,	   0x1180080901ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM981"              ,	   0x1180080901ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM982"              ,	   0x1180080901eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM983"              ,	   0x1180080901eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM984"              ,	   0x1180080901ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM985"              ,	   0x1180080901ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM986"              ,	   0x1180080901ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM987"              ,	   0x1180080901ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM988"              ,	   0x1180080901ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM989"              ,	   0x1180080901ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM990"              ,	   0x1180080901ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM991"              ,	   0x1180080901ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM992"              ,	   0x1180080901f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM993"              ,	   0x1180080901f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM994"              ,	   0x1180080901f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM995"              ,	   0x1180080901f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM996"              ,	   0x1180080901f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM997"              ,	   0x1180080901f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM998"              ,	   0x1180080901f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM999"              ,	   0x1180080901f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1000"             ,	   0x1180080901f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1001"             ,	   0x1180080901f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1002"             ,	   0x1180080901f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1003"             ,	   0x1180080901f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1004"             ,	   0x1180080901f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1005"             ,	   0x1180080901f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1006"             ,	   0x1180080901f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1007"             ,	   0x1180080901f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1008"             ,	   0x1180080901f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1009"             ,	   0x1180080901f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1010"             ,	   0x1180080901f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1011"             ,	   0x1180080901f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1012"             ,	   0x1180080901fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1013"             ,	   0x1180080901fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1014"             ,	   0x1180080901fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1015"             ,	   0x1180080901fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1016"             ,	   0x1180080901fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1017"             ,	   0x1180080901fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1018"             ,	   0x1180080901fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1019"             ,	   0x1180080901fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1020"             ,	   0x1180080901fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1021"             ,	   0x1180080901fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1022"             ,	   0x1180080901ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_VRT_MEM1023"             ,	   0x1180080901ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"L2C_WPAR_IOB0"               ,	   0x1180080840200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"L2C_WPAR_PP0"                ,	   0x1180080840000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"L2C_WPAR_PP1"                ,	   0x1180080840008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"L2C_WPAR_PP2"                ,	   0x1180080840010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"L2C_WPAR_PP3"                ,	   0x1180080840018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"L2C_XMC0_PFC"                ,	   0x1180080800400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
+	{"L2C_XMC_CMD"                 ,	   0x1180080800028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	516},
+	{"L2C_XMD0_PFC"                ,	   0x1180080800408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	517},
+	{"LMC0_CHAR_CTL"               ,	   0x1180088000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	518},
+	{"LMC0_CHAR_MASK0"             ,	   0x1180088000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
+	{"LMC0_CHAR_MASK1"             ,	   0x1180088000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
+	{"LMC0_CHAR_MASK2"             ,	   0x1180088000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"LMC0_CHAR_MASK3"             ,	   0x1180088000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
+	{"LMC0_CHAR_MASK4"             ,	   0x1180088000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
+	{"LMC0_COMP_CTL2"              ,	   0x11800880001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
+	{"LMC0_CONFIG"                 ,	   0x1180088000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
+	{"LMC0_CONTROL"                ,	   0x1180088000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
+	{"LMC0_DCLK_CNT"               ,	   0x11800880001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	527},
+	{"LMC0_DDR_PLL_CTL"            ,	   0x1180088000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
+	{"LMC0_DIMM000_PARAMS"         ,	   0x1180088000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	529},
+	{"LMC0_DIMM001_PARAMS"         ,	   0x1180088000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	529},
+	{"LMC0_DIMM_CTL"               ,	   0x1180088000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
+	{"LMC0_DLL_CTL2"               ,	   0x11800880001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	531},
+	{"LMC0_DLL_CTL3"               ,	   0x1180088000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"LMC0_DUAL_MEMCFG"            ,	   0x1180088000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	533},
+	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	534},
+	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	535},
+	{"LMC0_IFB_CNT"                ,	   0x11800880001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	536},
+	{"LMC0_INT"                    ,	   0x11800880001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	537},
+	{"LMC0_INT_EN"                 ,	   0x11800880001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	538},
+	{"LMC0_MODEREG_PARAMS0"        ,	   0x11800880001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	539},
+	{"LMC0_MODEREG_PARAMS1"        ,	   0x1180088000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
+	{"LMC0_NXM"                    ,	   0x11800880000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
+	{"LMC0_OPS_CNT"                ,	   0x11800880001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	542},
+	{"LMC0_PHY_CTL"                ,	   0x1180088000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	543},
+	{"LMC0_RESET_CTL"              ,	   0x1180088000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	544},
+	{"LMC0_RLEVEL_CTL"             ,	   0x11800880002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"LMC0_RLEVEL_DBG"             ,	   0x11800880002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
+	{"LMC0_RLEVEL_RANK000"         ,	   0x1180088000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
+	{"LMC0_RLEVEL_RANK001"         ,	   0x1180088000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
+	{"LMC0_RLEVEL_RANK002"         ,	   0x1180088000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
+	{"LMC0_RLEVEL_RANK003"         ,	   0x1180088000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
+	{"LMC0_RODT_MASK"              ,	   0x1180088000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	548},
+	{"LMC0_SCRAMBLE_CFG0"          ,	   0x1180088000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	549},
+	{"LMC0_SCRAMBLE_CFG1"          ,	   0x1180088000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	550},
+	{"LMC0_SCRAMBLED_FADR"         ,	   0x1180088000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	551},
+	{"LMC0_SLOT_CTL0"              ,	   0x11800880001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	552},
+	{"LMC0_SLOT_CTL1"              ,	   0x1180088000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
+	{"LMC0_SLOT_CTL2"              ,	   0x1180088000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
+	{"LMC0_TIMING_PARAMS0"         ,	   0x1180088000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"LMC0_TIMING_PARAMS1"         ,	   0x11800880001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
+	{"LMC0_TRO_CTL"                ,	   0x1180088000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
+	{"LMC0_TRO_STAT"               ,	   0x1180088000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"LMC0_WLEVEL_CTL"             ,	   0x1180088000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
+	{"LMC0_WLEVEL_DBG"             ,	   0x1180088000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
+	{"LMC0_WLEVEL_RANK000"         ,	   0x11800880002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
+	{"LMC0_WLEVEL_RANK001"         ,	   0x11800880002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
+	{"LMC0_WLEVEL_RANK002"         ,	   0x11800880002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
+	{"LMC0_WLEVEL_RANK003"         ,	   0x11800880002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
+	{"LMC0_WODT_MASK"              ,	   0x11800880001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
+	{"MIO_BOOT_COMP"               ,	   0x11800000000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
+	{"MIO_BOOT_DMA_CFG0"           ,	   0x1180000000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
+	{"MIO_BOOT_DMA_CFG1"           ,	   0x1180000000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
+	{"MIO_BOOT_DMA_INT0"           ,	   0x1180000000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
+	{"MIO_BOOT_DMA_INT1"           ,	   0x1180000000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
+	{"MIO_BOOT_DMA_INT_EN0"        ,	   0x1180000000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
+	{"MIO_BOOT_DMA_INT_EN1"        ,	   0x1180000000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
+	{"MIO_BOOT_DMA_TIM0"           ,	   0x1180000000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"MIO_BOOT_DMA_TIM1"           ,	   0x1180000000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	569},
+	{"MIO_BOOT_INT"                ,	   0x11800000000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	570},
+	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	571},
+	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	572},
+	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	572},
+	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	573},
+	{"MIO_BOOT_PIN_DEFS"           ,	   0x11800000000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	574},
+	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
+	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
+	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
+	{"MIO_BOOT_REG_CFG3"           ,	   0x1180000000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
+	{"MIO_BOOT_REG_CFG4"           ,	   0x1180000000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
+	{"MIO_BOOT_REG_CFG5"           ,	   0x1180000000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
+	{"MIO_BOOT_REG_CFG6"           ,	   0x1180000000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
+	{"MIO_BOOT_REG_CFG7"           ,	   0x1180000000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
+	{"MIO_BOOT_REG_TIM0"           ,	   0x1180000000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
+	{"MIO_BOOT_REG_TIM1"           ,	   0x1180000000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
+	{"MIO_BOOT_REG_TIM2"           ,	   0x1180000000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
+	{"MIO_BOOT_REG_TIM3"           ,	   0x1180000000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
+	{"MIO_BOOT_REG_TIM4"           ,	   0x1180000000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
+	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
+	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
+	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
+	{"MIO_BOOT_THR"                ,	   0x11800000000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	577},
+	{"MIO_EMM_BUF_DAT"             ,	   0x11800000020e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	578},
+	{"MIO_EMM_BUF_IDX"             ,	   0x11800000020e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	579},
+	{"MIO_EMM_CFG"                 ,	   0x1180000002000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	580},
+	{"MIO_EMM_CMD"                 ,	   0x1180000002058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	581},
+	{"MIO_EMM_DMA"                 ,	   0x1180000002050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	582},
+	{"MIO_EMM_INT"                 ,	   0x1180000002078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	583},
+	{"MIO_EMM_INT_EN"              ,	   0x1180000002080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	584},
+	{"MIO_EMM_MODE0"               ,	   0x1180000002008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	585},
+	{"MIO_EMM_MODE1"               ,	   0x1180000002010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	585},
+	{"MIO_EMM_MODE2"               ,	   0x1180000002018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	585},
+	{"MIO_EMM_MODE3"               ,	   0x1180000002020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	585},
+	{"MIO_EMM_RCA"                 ,	   0x11800000020a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	586},
+	{"MIO_EMM_RSP_HI"              ,	   0x1180000002070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	587},
+	{"MIO_EMM_RSP_LO"              ,	   0x1180000002068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	588},
+	{"MIO_EMM_RSP_STS"             ,	   0x1180000002060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	589},
+	{"MIO_EMM_SAMPLE"              ,	   0x1180000002090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	590},
+	{"MIO_EMM_STS_MASK"            ,	   0x1180000002098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	591},
+	{"MIO_EMM_SWITCH"              ,	   0x1180000002048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	592},
+	{"MIO_EMM_WDOG"                ,	   0x1180000002088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	593},
+	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	594},
+	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	594},
+	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	595},
+	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	596},
+	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	597},
+	{"MIO_FUS_DAT3"                ,	   0x1180000001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	598},
+	{"MIO_FUS_EMA"                 ,	   0x1180000001550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	599},
+	{"MIO_FUS_PDF"                 ,	   0x1180000001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	600},
+	{"MIO_FUS_PLL"                 ,	   0x1180000001580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	601},
+	{"MIO_FUS_PROG"                ,	   0x1180000001510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	602},
+	{"MIO_FUS_PROG_TIMES"          ,	   0x1180000001518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	603},
+	{"MIO_FUS_RCMD"                ,	   0x1180000001500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	604},
+	{"MIO_FUS_READ_TIMES"          ,	   0x1180000001570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"MIO_FUS_REPAIR_RES0"         ,	   0x1180000001558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	606},
+	{"MIO_FUS_REPAIR_RES1"         ,	   0x1180000001560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"MIO_FUS_REPAIR_RES2"         ,	   0x1180000001568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	608},
+	{"MIO_FUS_SPR_REPAIR_RES"      ,	   0x1180000001548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	609},
+	{"MIO_FUS_SPR_REPAIR_SUM"      ,	   0x1180000001540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	610},
+	{"MIO_FUS_TGG"                 ,	   0x1180000001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"MIO_FUS_WADR"                ,	   0x1180000001508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	612},
+	{"MIO_GPIO_COMP"               ,	   0x11800000000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	613},
+	{"MIO_NDF_DMA_CFG"             ,	   0x1180000000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	614},
+	{"MIO_NDF_DMA_INT"             ,	   0x1180000000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	615},
+	{"MIO_NDF_DMA_INT_EN"          ,	   0x1180000000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"MIO_PTP_CKOUT_HI_INCR"       ,	   0x1070000000f40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	617},
+	{"MIO_PTP_CKOUT_LO_INCR"       ,	   0x1070000000f48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	618},
+	{"MIO_PTP_CKOUT_THRESH_HI"     ,	   0x1070000000f38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	619},
+	{"MIO_PTP_CKOUT_THRESH_LO"     ,	   0x1070000000f30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	620},
+	{"MIO_PTP_CLOCK_CFG"           ,	   0x1070000000f00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	621},
+	{"MIO_PTP_CLOCK_COMP"          ,	   0x1070000000f18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	622},
+	{"MIO_PTP_CLOCK_HI"            ,	   0x1070000000f10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	623},
+	{"MIO_PTP_CLOCK_LO"            ,	   0x1070000000f08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	624},
+	{"MIO_PTP_EVT_CNT"             ,	   0x1070000000f28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	625},
+	{"MIO_PTP_PHY_1PPS_IN"         ,	   0x1070000000f70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	626},
+	{"MIO_PTP_PPS_HI_INCR"         ,	   0x1070000000f60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	627},
+	{"MIO_PTP_PPS_LO_INCR"         ,	   0x1070000000f68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	628},
+	{"MIO_PTP_PPS_THRESH_HI"       ,	   0x1070000000f58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	629},
+	{"MIO_PTP_PPS_THRESH_LO"       ,	   0x1070000000f50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	630},
+	{"MIO_PTP_TIMESTAMP"           ,	   0x1070000000f20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	631},
+	{"MIO_QLM0_CFG"                ,	   0x1180000001590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"MIO_QLM1_CFG"                ,	   0x1180000001598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"MIO_RST_BOOT"                ,	   0x1180000001600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
+	{"MIO_RST_CFG"                 ,	   0x1180000001610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
+	{"MIO_RST_CKILL"               ,	   0x1180000001638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"MIO_RST_CNTL0"               ,	   0x1180000001648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"MIO_RST_CNTL1"               ,	   0x1180000001650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"MIO_RST_CTL0"                ,	   0x1180000001618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
+	{"MIO_RST_CTL1"                ,	   0x1180000001620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
+	{"MIO_RST_DELAY"               ,	   0x1180000001608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"MIO_RST_INT"                 ,	   0x1180000001628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
+	{"MIO_RST_INT_EN"              ,	   0x1180000001630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"MIO_TWS0_INT"                ,	   0x1180000001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
+	{"MIO_TWS1_INT"                ,	   0x1180000001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
+	{"MIO_TWS0_SW_TWSI"            ,	   0x1180000001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"MIO_TWS1_SW_TWSI"            ,	   0x1180000001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	643},
+	{"MIO_TWS1_SW_TWSI_EXT"        ,	   0x1180000001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	643},
+	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"MIO_TWS1_TWSI_SW"            ,	   0x1180000001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
+	{"MIO_UART1_DLH"               ,	   0x1180000000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
+	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"MIO_UART1_DLL"               ,	   0x1180000000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
+	{"MIO_UART1_FAR"               ,	   0x1180000000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
+	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	648},
+	{"MIO_UART1_FCR"               ,	   0x1180000000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	648},
+	{"MIO_UART0_HTX"               ,	   0x1180000000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
+	{"MIO_UART1_HTX"               ,	   0x1180000000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
+	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
+	{"MIO_UART1_IER"               ,	   0x1180000000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
+	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
+	{"MIO_UART1_IIR"               ,	   0x1180000000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
+	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
+	{"MIO_UART1_LCR"               ,	   0x1180000000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
+	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
+	{"MIO_UART1_LSR"               ,	   0x1180000000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
+	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
+	{"MIO_UART1_MCR"               ,	   0x1180000000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
+	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"MIO_UART1_MSR"               ,	   0x1180000000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
+	{"MIO_UART1_RBR"               ,	   0x1180000000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
+	{"MIO_UART0_RFL"               ,	   0x1180000000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
+	{"MIO_UART1_RFL"               ,	   0x1180000000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
+	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
+	{"MIO_UART1_RFW"               ,	   0x1180000000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
+	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
+	{"MIO_UART1_SCR"               ,	   0x1180000000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
+	{"MIO_UART0_SFE"               ,	   0x1180000000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"MIO_UART1_SFE"               ,	   0x1180000000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"MIO_UART0_SRR"               ,	   0x1180000000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"MIO_UART1_SRR"               ,	   0x1180000000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"MIO_UART0_SRT"               ,	   0x1180000000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
+	{"MIO_UART1_SRT"               ,	   0x1180000000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
+	{"MIO_UART0_STT"               ,	   0x1180000000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
+	{"MIO_UART1_STT"               ,	   0x1180000000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
+	{"MIO_UART0_TFL"               ,	   0x1180000000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"MIO_UART1_TFL"               ,	   0x1180000000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
+	{"MIO_UART1_TFR"               ,	   0x1180000000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
+	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"MIO_UART1_THR"               ,	   0x1180000000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"MIO_UART1_USR"               ,	   0x1180000000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"MPI_CFG"                     ,	   0x1070000001000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	670},
+	{"MPI_DAT0"                    ,	   0x1070000001080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	671},
+	{"MPI_DAT1"                    ,	   0x1070000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	671},
+	{"MPI_DAT2"                    ,	   0x1070000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	671},
+	{"MPI_DAT3"                    ,	   0x1070000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	671},
+	{"MPI_DAT4"                    ,	   0x10700000010a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	671},
+	{"MPI_DAT5"                    ,	   0x10700000010a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	671},
+	{"MPI_DAT6"                    ,	   0x10700000010b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	671},
+	{"MPI_DAT7"                    ,	   0x10700000010b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	671},
+	{"MPI_DAT8"                    ,	   0x10700000010c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	671},
+	{"MPI_STS"                     ,	   0x1070000001008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	672},
+	{"MPI_TX"                      ,	   0x1070000001010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	673},
+	{"PCIEEP0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	674},
+	{"PCIEEP1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	674},
+	{"PCIEEP0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	675},
+	{"PCIEEP1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	675},
+	{"PCIEEP0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	676},
+	{"PCIEEP1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	676},
+	{"PCIEEP0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	677},
+	{"PCIEEP1_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	677},
+	{"PCIEEP0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	678},
+	{"PCIEEP1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	678},
+	{"PCIEEP0_CFG004_MASK"         ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	679},
+	{"PCIEEP1_CFG004_MASK"         ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	679},
+	{"PCIEEP0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	680},
+	{"PCIEEP1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	680},
+	{"PCIEEP0_CFG005_MASK"         ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	681},
+	{"PCIEEP1_CFG005_MASK"         ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	681},
+	{"PCIEEP0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	682},
+	{"PCIEEP1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	682},
+	{"PCIEEP0_CFG006_MASK"         ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	683},
+	{"PCIEEP1_CFG006_MASK"         ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	683},
+	{"PCIEEP0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	684},
+	{"PCIEEP1_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	684},
+	{"PCIEEP0_CFG007_MASK"         ,	        0x8000001cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	685},
+	{"PCIEEP1_CFG007_MASK"         ,	        0x8000001cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	685},
+	{"PCIEEP0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	686},
+	{"PCIEEP1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	686},
+	{"PCIEEP0_CFG008_MASK"         ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	687},
+	{"PCIEEP1_CFG008_MASK"         ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	687},
+	{"PCIEEP0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	688},
+	{"PCIEEP1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	688},
+	{"PCIEEP0_CFG009_MASK"         ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	689},
+	{"PCIEEP1_CFG009_MASK"         ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	689},
+	{"PCIEEP0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	690},
+	{"PCIEEP1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	690},
+	{"PCIEEP0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	691},
+	{"PCIEEP1_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	691},
+	{"PCIEEP0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	692},
+	{"PCIEEP1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	692},
+	{"PCIEEP0_CFG012_MASK"         ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	693},
+	{"PCIEEP1_CFG012_MASK"         ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	693},
+	{"PCIEEP0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	694},
+	{"PCIEEP1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	694},
+	{"PCIEEP0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	695},
+	{"PCIEEP1_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	695},
+	{"PCIEEP0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	696},
+	{"PCIEEP1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	696},
+	{"PCIEEP0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	697},
+	{"PCIEEP1_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	697},
+	{"PCIEEP0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	698},
+	{"PCIEEP1_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	698},
+	{"PCIEEP0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	699},
+	{"PCIEEP1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	699},
+	{"PCIEEP0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	700},
+	{"PCIEEP1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	700},
+	{"PCIEEP0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	701},
+	{"PCIEEP1_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	701},
+	{"PCIEEP0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	702},
+	{"PCIEEP1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	702},
+	{"PCIEEP0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	703},
+	{"PCIEEP1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	703},
+	{"PCIEEP0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	704},
+	{"PCIEEP1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	704},
+	{"PCIEEP0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	705},
+	{"PCIEEP1_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	705},
+	{"PCIEEP0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	706},
+	{"PCIEEP1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	706},
+	{"PCIEEP0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	707},
+	{"PCIEEP1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	707},
+	{"PCIEEP0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	708},
+	{"PCIEEP1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	708},
+	{"PCIEEP0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	709},
+	{"PCIEEP1_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	709},
+	{"PCIEEP0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	710},
+	{"PCIEEP1_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	710},
+	{"PCIEEP0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	711},
+	{"PCIEEP1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	711},
+	{"PCIEEP0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	712},
+	{"PCIEEP1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	712},
+	{"PCIEEP0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	713},
+	{"PCIEEP1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	713},
+	{"PCIEEP0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	714},
+	{"PCIEEP1_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	714},
+	{"PCIEEP0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	715},
+	{"PCIEEP1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	715},
+	{"PCIEEP0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	716},
+	{"PCIEEP1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	716},
+	{"PCIEEP0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	717},
+	{"PCIEEP1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	717},
+	{"PCIEEP0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	718},
+	{"PCIEEP1_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	718},
+	{"PCIEEP0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	719},
+	{"PCIEEP1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	719},
+	{"PCIEEP0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	720},
+	{"PCIEEP1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	720},
+	{"PCIEEP0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	721},
+	{"PCIEEP1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	721},
+	{"PCIEEP0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	722},
+	{"PCIEEP1_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	722},
+	{"PCIEEP0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	723},
+	{"PCIEEP1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	723},
+	{"PCIEEP0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	724},
+	{"PCIEEP1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	724},
+	{"PCIEEP0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	725},
+	{"PCIEEP1_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	725},
+	{"PCIEEP0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	726},
+	{"PCIEEP1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	726},
+	{"PCIEEP0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	727},
+	{"PCIEEP1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	727},
+	{"PCIEEP0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	728},
+	{"PCIEEP1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	728},
+	{"PCIEEP0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	729},
+	{"PCIEEP1_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	729},
+	{"PCIEEP0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	730},
+	{"PCIEEP1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	730},
+	{"PCIEEP0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	731},
+	{"PCIEEP1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	731},
+	{"PCIEEP0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	732},
+	{"PCIEEP1_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	732},
+	{"PCIEEP0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	733},
+	{"PCIEEP1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	733},
+	{"PCIEEP0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	734},
+	{"PCIEEP1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	734},
+	{"PCIEEP0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	735},
+	{"PCIEEP1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	735},
+	{"PCIEEP0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	736},
+	{"PCIEEP1_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	736},
+	{"PCIEEP0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	737},
+	{"PCIEEP1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	737},
+	{"PCIEEP0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	738},
+	{"PCIEEP1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	738},
+	{"PCIEEP0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	739},
+	{"PCIEEP1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	739},
+	{"PCIEEP0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	740},
+	{"PCIEEP1_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	740},
+	{"PCIEEP0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	741},
+	{"PCIEEP1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	741},
+	{"PCIEEP0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	742},
+	{"PCIEEP1_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	742},
+	{"PCIEEP0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	743},
+	{"PCIEEP1_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	743},
+	{"PCIEEP0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	744},
+	{"PCIEEP1_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	744},
+	{"PCIEEP0_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	745},
+	{"PCIEEP1_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	745},
+	{"PCIEEP0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	746},
+	{"PCIEEP1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	746},
+	{"PCIEEP0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	747},
+	{"PCIEEP1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	747},
+	{"PCIERC0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	748},
+	{"PCIERC1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	748},
+	{"PCIERC0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	749},
+	{"PCIERC1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	749},
+	{"PCIERC0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	750},
+	{"PCIERC1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	750},
+	{"PCIERC0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	751},
+	{"PCIERC1_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	751},
+	{"PCIERC0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	752},
+	{"PCIERC1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	752},
+	{"PCIERC0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	753},
+	{"PCIERC1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	753},
+	{"PCIERC0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	754},
+	{"PCIERC1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	754},
+	{"PCIERC0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	755},
+	{"PCIERC1_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	755},
+	{"PCIERC0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	756},
+	{"PCIERC1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	756},
+	{"PCIERC0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	757},
+	{"PCIERC1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	757},
+	{"PCIERC0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	758},
+	{"PCIERC1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	758},
+	{"PCIERC0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	759},
+	{"PCIERC1_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	759},
+	{"PCIERC0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	760},
+	{"PCIERC1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	760},
+	{"PCIERC0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	761},
+	{"PCIERC1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	761},
+	{"PCIERC0_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	762},
+	{"PCIERC1_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	762},
+	{"PCIERC0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	763},
+	{"PCIERC1_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	763},
+	{"PCIERC0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	764},
+	{"PCIERC1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	764},
+	{"PCIERC0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	765},
+	{"PCIERC1_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	765},
+	{"PCIERC0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	766},
+	{"PCIERC1_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	766},
+	{"PCIERC0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	767},
+	{"PCIERC1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	767},
+	{"PCIERC0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	768},
+	{"PCIERC1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	768},
+	{"PCIERC0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	769},
+	{"PCIERC1_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	769},
+	{"PCIERC0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	770},
+	{"PCIERC1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	770},
+	{"PCIERC0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	771},
+	{"PCIERC1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	771},
+	{"PCIERC0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	772},
+	{"PCIERC1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	772},
+	{"PCIERC0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	773},
+	{"PCIERC1_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	773},
+	{"PCIERC0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	774},
+	{"PCIERC1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	774},
+	{"PCIERC0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	775},
+	{"PCIERC1_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	775},
+	{"PCIERC0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	776},
+	{"PCIERC1_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	776},
+	{"PCIERC0_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	777},
+	{"PCIERC1_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	777},
+	{"PCIERC0_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	778},
+	{"PCIERC1_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	778},
+	{"PCIERC0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	779},
+	{"PCIERC1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	779},
+	{"PCIERC0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	780},
+	{"PCIERC1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	780},
+	{"PCIERC0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	781},
+	{"PCIERC1_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	781},
+	{"PCIERC0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	782},
+	{"PCIERC1_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	782},
+	{"PCIERC0_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	783},
+	{"PCIERC1_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	783},
+	{"PCIERC0_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	784},
+	{"PCIERC1_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	784},
+	{"PCIERC0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	785},
+	{"PCIERC1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	785},
+	{"PCIERC0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	786},
+	{"PCIERC1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	786},
+	{"PCIERC0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	787},
+	{"PCIERC1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	787},
+	{"PCIERC0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	788},
+	{"PCIERC1_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	788},
+	{"PCIERC0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	789},
+	{"PCIERC1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	789},
+	{"PCIERC0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	790},
+	{"PCIERC1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	790},
+	{"PCIERC0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	791},
+	{"PCIERC1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	791},
+	{"PCIERC0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	792},
+	{"PCIERC1_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	792},
+	{"PCIERC0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	793},
+	{"PCIERC1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	793},
+	{"PCIERC0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	794},
+	{"PCIERC1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	794},
+	{"PCIERC0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	795},
+	{"PCIERC1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	795},
+	{"PCIERC0_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	796},
+	{"PCIERC1_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	796},
+	{"PCIERC0_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	797},
+	{"PCIERC1_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	797},
+	{"PCIERC0_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	798},
+	{"PCIERC1_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	798},
+	{"PCIERC0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	799},
+	{"PCIERC1_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	799},
+	{"PCIERC0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	800},
+	{"PCIERC1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	800},
+	{"PCIERC0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	801},
+	{"PCIERC1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	801},
+	{"PCIERC0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	802},
+	{"PCIERC1_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	802},
+	{"PCIERC0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	803},
+	{"PCIERC1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	803},
+	{"PCIERC0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	804},
+	{"PCIERC1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	804},
+	{"PCIERC0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	805},
+	{"PCIERC1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	805},
+	{"PCIERC0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	806},
+	{"PCIERC1_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	806},
+	{"PCIERC0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	807},
+	{"PCIERC1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	807},
+	{"PCIERC0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	808},
+	{"PCIERC1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	808},
+	{"PCIERC0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	809},
+	{"PCIERC1_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	809},
+	{"PCIERC0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	810},
+	{"PCIERC1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	810},
+	{"PCIERC0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	811},
+	{"PCIERC1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	811},
+	{"PCIERC0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	812},
+	{"PCIERC1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	812},
+	{"PCIERC0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	813},
+	{"PCIERC1_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	813},
+	{"PCIERC0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	814},
+	{"PCIERC1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	814},
+	{"PCIERC0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	815},
+	{"PCIERC1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	815},
+	{"PCIERC0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	816},
+	{"PCIERC1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	816},
+	{"PCIERC0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	817},
+	{"PCIERC1_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	817},
+	{"PCIERC0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	818},
+	{"PCIERC1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	818},
+	{"PCIERC0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	819},
+	{"PCIERC1_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	819},
+	{"PCIERC0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	820},
+	{"PCIERC1_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	820},
+	{"PCIERC0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	821},
+	{"PCIERC1_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	821},
+	{"PCIERC0_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	822},
+	{"PCIERC1_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	822},
+	{"PCIERC0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	823},
+	{"PCIERC1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	823},
+	{"PCIERC0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	824},
+	{"PCIERC1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	824},
+	{"PCM0_DMA_CFG"                ,	   0x1070000010018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	825},
+	{"PCM1_DMA_CFG"                ,	   0x1070000014018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	825},
+	{"PCM2_DMA_CFG"                ,	   0x1070000018018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	825},
+	{"PCM3_DMA_CFG"                ,	   0x107000001c018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	825},
+	{"PCM0_INT_ENA"                ,	   0x1070000010020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	826},
+	{"PCM1_INT_ENA"                ,	   0x1070000014020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	826},
+	{"PCM2_INT_ENA"                ,	   0x1070000018020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	826},
+	{"PCM3_INT_ENA"                ,	   0x107000001c020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	826},
+	{"PCM0_INT_SUM"                ,	   0x1070000010028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	827},
+	{"PCM1_INT_SUM"                ,	   0x1070000014028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	827},
+	{"PCM2_INT_SUM"                ,	   0x1070000018028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	827},
+	{"PCM3_INT_SUM"                ,	   0x107000001c028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	827},
+	{"PCM0_RXADDR"                 ,	   0x1070000010068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	828},
+	{"PCM1_RXADDR"                 ,	   0x1070000014068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	828},
+	{"PCM2_RXADDR"                 ,	   0x1070000018068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	828},
+	{"PCM3_RXADDR"                 ,	   0x107000001c068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	828},
+	{"PCM0_RXCNT"                  ,	   0x1070000010060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"PCM1_RXCNT"                  ,	   0x1070000014060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"PCM2_RXCNT"                  ,	   0x1070000018060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"PCM3_RXCNT"                  ,	   0x107000001c060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"PCM0_RXMSK0"                 ,	   0x10700000100c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
+	{"PCM1_RXMSK0"                 ,	   0x10700000140c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
+	{"PCM2_RXMSK0"                 ,	   0x10700000180c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
+	{"PCM3_RXMSK0"                 ,	   0x107000001c0c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
+	{"PCM0_RXMSK1"                 ,	   0x10700000100c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	831},
+	{"PCM1_RXMSK1"                 ,	   0x10700000140c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	831},
+	{"PCM2_RXMSK1"                 ,	   0x10700000180c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	831},
+	{"PCM3_RXMSK1"                 ,	   0x107000001c0c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	831},
+	{"PCM0_RXMSK2"                 ,	   0x10700000100d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	832},
+	{"PCM1_RXMSK2"                 ,	   0x10700000140d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	832},
+	{"PCM2_RXMSK2"                 ,	   0x10700000180d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	832},
+	{"PCM3_RXMSK2"                 ,	   0x107000001c0d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	832},
+	{"PCM0_RXMSK3"                 ,	   0x10700000100d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	833},
+	{"PCM1_RXMSK3"                 ,	   0x10700000140d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	833},
+	{"PCM2_RXMSK3"                 ,	   0x10700000180d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	833},
+	{"PCM3_RXMSK3"                 ,	   0x107000001c0d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	833},
+	{"PCM0_RXMSK4"                 ,	   0x10700000100e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	834},
+	{"PCM1_RXMSK4"                 ,	   0x10700000140e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	834},
+	{"PCM2_RXMSK4"                 ,	   0x10700000180e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	834},
+	{"PCM3_RXMSK4"                 ,	   0x107000001c0e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	834},
+	{"PCM0_RXMSK5"                 ,	   0x10700000100e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"PCM1_RXMSK5"                 ,	   0x10700000140e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"PCM2_RXMSK5"                 ,	   0x10700000180e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"PCM3_RXMSK5"                 ,	   0x107000001c0e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"PCM0_RXMSK6"                 ,	   0x10700000100f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	836},
+	{"PCM1_RXMSK6"                 ,	   0x10700000140f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	836},
+	{"PCM2_RXMSK6"                 ,	   0x10700000180f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	836},
+	{"PCM3_RXMSK6"                 ,	   0x107000001c0f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	836},
+	{"PCM0_RXMSK7"                 ,	   0x10700000100f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"PCM1_RXMSK7"                 ,	   0x10700000140f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"PCM2_RXMSK7"                 ,	   0x10700000180f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"PCM3_RXMSK7"                 ,	   0x107000001c0f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"PCM0_RXSTART"                ,	   0x1070000010058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"PCM1_RXSTART"                ,	   0x1070000014058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"PCM2_RXSTART"                ,	   0x1070000018058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"PCM3_RXSTART"                ,	   0x107000001c058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"PCM0_TDM_CFG"                ,	   0x1070000010010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	839},
+	{"PCM1_TDM_CFG"                ,	   0x1070000014010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	839},
+	{"PCM2_TDM_CFG"                ,	   0x1070000018010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	839},
+	{"PCM3_TDM_CFG"                ,	   0x107000001c010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	839},
+	{"PCM0_TDM_DBG"                ,	   0x1070000010030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	840},
+	{"PCM1_TDM_DBG"                ,	   0x1070000014030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	840},
+	{"PCM2_TDM_DBG"                ,	   0x1070000018030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	840},
+	{"PCM3_TDM_DBG"                ,	   0x107000001c030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	840},
+	{"PCM0_TXADDR"                 ,	   0x1070000010050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
+	{"PCM1_TXADDR"                 ,	   0x1070000014050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
+	{"PCM2_TXADDR"                 ,	   0x1070000018050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
+	{"PCM3_TXADDR"                 ,	   0x107000001c050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
+	{"PCM0_TXCNT"                  ,	   0x1070000010048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	842},
+	{"PCM1_TXCNT"                  ,	   0x1070000014048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	842},
+	{"PCM2_TXCNT"                  ,	   0x1070000018048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	842},
+	{"PCM3_TXCNT"                  ,	   0x107000001c048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	842},
+	{"PCM0_TXMSK0"                 ,	   0x1070000010080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	843},
+	{"PCM1_TXMSK0"                 ,	   0x1070000014080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	843},
+	{"PCM2_TXMSK0"                 ,	   0x1070000018080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	843},
+	{"PCM3_TXMSK0"                 ,	   0x107000001c080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	843},
+	{"PCM0_TXMSK1"                 ,	   0x1070000010088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	844},
+	{"PCM1_TXMSK1"                 ,	   0x1070000014088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	844},
+	{"PCM2_TXMSK1"                 ,	   0x1070000018088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	844},
+	{"PCM3_TXMSK1"                 ,	   0x107000001c088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	844},
+	{"PCM0_TXMSK2"                 ,	   0x1070000010090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
+	{"PCM1_TXMSK2"                 ,	   0x1070000014090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
+	{"PCM2_TXMSK2"                 ,	   0x1070000018090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
+	{"PCM3_TXMSK2"                 ,	   0x107000001c090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
+	{"PCM0_TXMSK3"                 ,	   0x1070000010098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	846},
+	{"PCM1_TXMSK3"                 ,	   0x1070000014098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	846},
+	{"PCM2_TXMSK3"                 ,	   0x1070000018098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	846},
+	{"PCM3_TXMSK3"                 ,	   0x107000001c098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	846},
+	{"PCM0_TXMSK4"                 ,	   0x10700000100a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	847},
+	{"PCM1_TXMSK4"                 ,	   0x10700000140a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	847},
+	{"PCM2_TXMSK4"                 ,	   0x10700000180a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	847},
+	{"PCM3_TXMSK4"                 ,	   0x107000001c0a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	847},
+	{"PCM0_TXMSK5"                 ,	   0x10700000100a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	848},
+	{"PCM1_TXMSK5"                 ,	   0x10700000140a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	848},
+	{"PCM2_TXMSK5"                 ,	   0x10700000180a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	848},
+	{"PCM3_TXMSK5"                 ,	   0x107000001c0a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	848},
+	{"PCM0_TXMSK6"                 ,	   0x10700000100b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"PCM1_TXMSK6"                 ,	   0x10700000140b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"PCM2_TXMSK6"                 ,	   0x10700000180b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"PCM3_TXMSK6"                 ,	   0x107000001c0b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"PCM0_TXMSK7"                 ,	   0x10700000100b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
+	{"PCM1_TXMSK7"                 ,	   0x10700000140b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
+	{"PCM2_TXMSK7"                 ,	   0x10700000180b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
+	{"PCM3_TXMSK7"                 ,	   0x107000001c0b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
+	{"PCM0_TXSTART"                ,	   0x1070000010040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"PCM1_TXSTART"                ,	   0x1070000014040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"PCM2_TXSTART"                ,	   0x1070000018040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"PCM3_TXSTART"                ,	   0x107000001c040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"PCM_CLK0_CFG"                ,	   0x1070000010000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	852},
+	{"PCM_CLK1_CFG"                ,	   0x1070000014000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	852},
+	{"PCM_CLK0_DBG"                ,	   0x1070000010038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
+	{"PCM_CLK1_DBG"                ,	   0x1070000014038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
+	{"PCM_CLK0_GEN"                ,	   0x1070000010008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
+	{"PCM_CLK1_GEN"                ,	   0x1070000014008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
+	{"PCS0_AN000_ADV_REG"          ,	   0x11800b0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	855},
+	{"PCS0_AN001_ADV_REG"          ,	   0x11800b0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	855},
+	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800b0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	856},
+	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800b0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	856},
+	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800b0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	857},
+	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800b0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	857},
+	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800b0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	858},
+	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800b0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	858},
+	{"PCS0_INT000_EN_REG"          ,	   0x11800b0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	859},
+	{"PCS0_INT001_EN_REG"          ,	   0x11800b0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	859},
+	{"PCS0_INT000_REG"             ,	   0x11800b0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	860},
+	{"PCS0_INT001_REG"             ,	   0x11800b0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	860},
+	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800b0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	861},
+	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800b0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	861},
+	{"PCS0_LOG_ANL000_REG"         ,	   0x11800b0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	862},
+	{"PCS0_LOG_ANL001_REG"         ,	   0x11800b0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	862},
+	{"PCS0_MISC000_CTL_REG"        ,	   0x11800b0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	863},
+	{"PCS0_MISC001_CTL_REG"        ,	   0x11800b0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	863},
+	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800b0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	864},
+	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800b0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	864},
+	{"PCS0_MR000_STATUS_REG"       ,	   0x11800b0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	865},
+	{"PCS0_MR001_STATUS_REG"       ,	   0x11800b0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	865},
+	{"PCS0_RX000_STATES_REG"       ,	   0x11800b0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	866},
+	{"PCS0_RX001_STATES_REG"       ,	   0x11800b0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	866},
+	{"PCS0_RX000_SYNC_REG"         ,	   0x11800b0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	867},
+	{"PCS0_RX001_SYNC_REG"         ,	   0x11800b0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	867},
+	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800b0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	868},
+	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800b0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	868},
+	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800b0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	869},
+	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800b0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	869},
+	{"PCS0_TX000_STATES_REG"       ,	   0x11800b0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	870},
+	{"PCS0_TX001_STATES_REG"       ,	   0x11800b0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	870},
+	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800b0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	871},
+	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800b0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	871},
+	{"PEM0_BAR1_INDEX000"          ,	   0x11800c00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM0_BAR1_INDEX001"          ,	   0x11800c00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM0_BAR1_INDEX002"          ,	   0x11800c00000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM0_BAR1_INDEX003"          ,	   0x11800c00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM0_BAR1_INDEX004"          ,	   0x11800c00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM0_BAR1_INDEX005"          ,	   0x11800c00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM0_BAR1_INDEX006"          ,	   0x11800c00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM0_BAR1_INDEX007"          ,	   0x11800c00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM0_BAR1_INDEX008"          ,	   0x11800c00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM0_BAR1_INDEX009"          ,	   0x11800c00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM0_BAR1_INDEX010"          ,	   0x11800c00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM0_BAR1_INDEX011"          ,	   0x11800c0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM0_BAR1_INDEX012"          ,	   0x11800c0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM0_BAR1_INDEX013"          ,	   0x11800c0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM0_BAR1_INDEX014"          ,	   0x11800c0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM0_BAR1_INDEX015"          ,	   0x11800c0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM1_BAR1_INDEX000"          ,	   0x11800c10000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM1_BAR1_INDEX001"          ,	   0x11800c10000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM1_BAR1_INDEX002"          ,	   0x11800c10000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM1_BAR1_INDEX003"          ,	   0x11800c10000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM1_BAR1_INDEX004"          ,	   0x11800c10000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM1_BAR1_INDEX005"          ,	   0x11800c10000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM1_BAR1_INDEX006"          ,	   0x11800c10000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM1_BAR1_INDEX007"          ,	   0x11800c10000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM1_BAR1_INDEX008"          ,	   0x11800c10000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM1_BAR1_INDEX009"          ,	   0x11800c10000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM1_BAR1_INDEX010"          ,	   0x11800c10000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM1_BAR1_INDEX011"          ,	   0x11800c1000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM1_BAR1_INDEX012"          ,	   0x11800c1000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM1_BAR1_INDEX013"          ,	   0x11800c1000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM1_BAR1_INDEX014"          ,	   0x11800c1000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM1_BAR1_INDEX015"          ,	   0x11800c1000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"PEM0_BAR2_MASK"              ,	   0x11800c0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	873},
+	{"PEM1_BAR2_MASK"              ,	   0x11800c1000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	873},
+	{"PEM0_BAR_CTL"                ,	   0x11800c0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	874},
+	{"PEM1_BAR_CTL"                ,	   0x11800c1000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	874},
+	{"PEM0_BIST_STATUS"            ,	   0x11800c0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	875},
+	{"PEM1_BIST_STATUS"            ,	   0x11800c1000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	875},
+	{"PEM0_BIST_STATUS2"           ,	   0x11800c0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	876},
+	{"PEM1_BIST_STATUS2"           ,	   0x11800c1000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	876},
+	{"PEM0_CFG_RD"                 ,	   0x11800c0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	877},
+	{"PEM1_CFG_RD"                 ,	   0x11800c1000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	877},
+	{"PEM0_CFG_WR"                 ,	   0x11800c0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	878},
+	{"PEM1_CFG_WR"                 ,	   0x11800c1000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	878},
+	{"PEM0_CPL_LUT_VALID"          ,	   0x11800c0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
+	{"PEM1_CPL_LUT_VALID"          ,	   0x11800c1000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
+	{"PEM0_CTL_STATUS"             ,	   0x11800c0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
+	{"PEM1_CTL_STATUS"             ,	   0x11800c1000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
+	{"PEM0_DBG_INFO"               ,	   0x11800c0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
+	{"PEM1_DBG_INFO"               ,	   0x11800c1000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
+	{"PEM0_DBG_INFO_EN"            ,	   0x11800c00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
+	{"PEM1_DBG_INFO_EN"            ,	   0x11800c10000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
+	{"PEM0_DIAG_STATUS"            ,	   0x11800c0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
+	{"PEM1_DIAG_STATUS"            ,	   0x11800c1000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
+	{"PEM0_INB_READ_CREDITS"       ,	   0x11800c0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
+	{"PEM1_INB_READ_CREDITS"       ,	   0x11800c1000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
+	{"PEM0_INT_ENB"                ,	   0x11800c0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
+	{"PEM1_INT_ENB"                ,	   0x11800c1000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
+	{"PEM0_INT_ENB_INT"            ,	   0x11800c0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	886},
+	{"PEM1_INT_ENB_INT"            ,	   0x11800c1000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	886},
+	{"PEM0_INT_SUM"                ,	   0x11800c0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	887},
+	{"PEM1_INT_SUM"                ,	   0x11800c1000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	887},
+	{"PEM0_P2N_BAR0_START"         ,	   0x11800c0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	888},
+	{"PEM1_P2N_BAR0_START"         ,	   0x11800c1000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	888},
+	{"PEM0_P2N_BAR1_START"         ,	   0x11800c0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	889},
+	{"PEM1_P2N_BAR1_START"         ,	   0x11800c1000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	889},
+	{"PEM0_P2N_BAR2_START"         ,	   0x11800c0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	890},
+	{"PEM1_P2N_BAR2_START"         ,	   0x11800c1000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	890},
+	{"PEM0_TLP_CREDITS"            ,	   0x11800c0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	891},
+	{"PEM1_TLP_CREDITS"            ,	   0x11800c1000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	891},
+	{"PIP_ALT_SKIP_CFG0"           ,	   0x11800a0002a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	892},
+	{"PIP_ALT_SKIP_CFG1"           ,	   0x11800a0002a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	892},
+	{"PIP_ALT_SKIP_CFG2"           ,	   0x11800a0002a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	892},
+	{"PIP_ALT_SKIP_CFG3"           ,	   0x11800a0002a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	892},
+	{"PIP_BCK_PRS"                 ,	   0x11800a0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	893},
+	{"PIP_BIST_STATUS"             ,	   0x11800a0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	894},
+	{"PIP_BSEL_EXT_CFG0"           ,	   0x11800a0002800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	895},
+	{"PIP_BSEL_EXT_CFG1"           ,	   0x11800a0002810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	895},
+	{"PIP_BSEL_EXT_CFG2"           ,	   0x11800a0002820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	895},
+	{"PIP_BSEL_EXT_CFG3"           ,	   0x11800a0002830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	895},
+	{"PIP_BSEL_EXT_POS0"           ,	   0x11800a0002808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	896},
+	{"PIP_BSEL_EXT_POS1"           ,	   0x11800a0002818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	896},
+	{"PIP_BSEL_EXT_POS2"           ,	   0x11800a0002828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	896},
+	{"PIP_BSEL_EXT_POS3"           ,	   0x11800a0002838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	896},
+	{"PIP_BSEL_TBL_ENT0"           ,	   0x11800a0003000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT1"           ,	   0x11800a0003008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT2"           ,	   0x11800a0003010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT3"           ,	   0x11800a0003018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT4"           ,	   0x11800a0003020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT5"           ,	   0x11800a0003028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT6"           ,	   0x11800a0003030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT7"           ,	   0x11800a0003038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT8"           ,	   0x11800a0003040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT9"           ,	   0x11800a0003048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT10"          ,	   0x11800a0003050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT11"          ,	   0x11800a0003058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT12"          ,	   0x11800a0003060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT13"          ,	   0x11800a0003068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT14"          ,	   0x11800a0003070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT15"          ,	   0x11800a0003078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT16"          ,	   0x11800a0003080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT17"          ,	   0x11800a0003088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT18"          ,	   0x11800a0003090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT19"          ,	   0x11800a0003098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT20"          ,	   0x11800a00030a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT21"          ,	   0x11800a00030a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT22"          ,	   0x11800a00030b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT23"          ,	   0x11800a00030b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT24"          ,	   0x11800a00030c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT25"          ,	   0x11800a00030c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT26"          ,	   0x11800a00030d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT27"          ,	   0x11800a00030d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT28"          ,	   0x11800a00030e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT29"          ,	   0x11800a00030e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT30"          ,	   0x11800a00030f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT31"          ,	   0x11800a00030f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT32"          ,	   0x11800a0003100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT33"          ,	   0x11800a0003108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT34"          ,	   0x11800a0003110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT35"          ,	   0x11800a0003118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT36"          ,	   0x11800a0003120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT37"          ,	   0x11800a0003128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT38"          ,	   0x11800a0003130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT39"          ,	   0x11800a0003138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT40"          ,	   0x11800a0003140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT41"          ,	   0x11800a0003148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT42"          ,	   0x11800a0003150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT43"          ,	   0x11800a0003158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT44"          ,	   0x11800a0003160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT45"          ,	   0x11800a0003168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT46"          ,	   0x11800a0003170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT47"          ,	   0x11800a0003178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT48"          ,	   0x11800a0003180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT49"          ,	   0x11800a0003188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT50"          ,	   0x11800a0003190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT51"          ,	   0x11800a0003198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT52"          ,	   0x11800a00031a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT53"          ,	   0x11800a00031a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT54"          ,	   0x11800a00031b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT55"          ,	   0x11800a00031b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT56"          ,	   0x11800a00031c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT57"          ,	   0x11800a00031c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT58"          ,	   0x11800a00031d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT59"          ,	   0x11800a00031d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT60"          ,	   0x11800a00031e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT61"          ,	   0x11800a00031e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT62"          ,	   0x11800a00031f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT63"          ,	   0x11800a00031f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT64"          ,	   0x11800a0003200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT65"          ,	   0x11800a0003208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT66"          ,	   0x11800a0003210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT67"          ,	   0x11800a0003218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT68"          ,	   0x11800a0003220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT69"          ,	   0x11800a0003228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT70"          ,	   0x11800a0003230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT71"          ,	   0x11800a0003238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT72"          ,	   0x11800a0003240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT73"          ,	   0x11800a0003248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT74"          ,	   0x11800a0003250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT75"          ,	   0x11800a0003258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT76"          ,	   0x11800a0003260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT77"          ,	   0x11800a0003268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT78"          ,	   0x11800a0003270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT79"          ,	   0x11800a0003278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT80"          ,	   0x11800a0003280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT81"          ,	   0x11800a0003288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT82"          ,	   0x11800a0003290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT83"          ,	   0x11800a0003298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT84"          ,	   0x11800a00032a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT85"          ,	   0x11800a00032a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT86"          ,	   0x11800a00032b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT87"          ,	   0x11800a00032b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT88"          ,	   0x11800a00032c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT89"          ,	   0x11800a00032c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT90"          ,	   0x11800a00032d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT91"          ,	   0x11800a00032d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT92"          ,	   0x11800a00032e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT93"          ,	   0x11800a00032e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT94"          ,	   0x11800a00032f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT95"          ,	   0x11800a00032f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT96"          ,	   0x11800a0003300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT97"          ,	   0x11800a0003308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT98"          ,	   0x11800a0003310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT99"          ,	   0x11800a0003318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT100"         ,	   0x11800a0003320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT101"         ,	   0x11800a0003328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT102"         ,	   0x11800a0003330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT103"         ,	   0x11800a0003338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT104"         ,	   0x11800a0003340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT105"         ,	   0x11800a0003348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT106"         ,	   0x11800a0003350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT107"         ,	   0x11800a0003358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT108"         ,	   0x11800a0003360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT109"         ,	   0x11800a0003368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT110"         ,	   0x11800a0003370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT111"         ,	   0x11800a0003378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT112"         ,	   0x11800a0003380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT113"         ,	   0x11800a0003388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT114"         ,	   0x11800a0003390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT115"         ,	   0x11800a0003398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT116"         ,	   0x11800a00033a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT117"         ,	   0x11800a00033a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT118"         ,	   0x11800a00033b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT119"         ,	   0x11800a00033b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT120"         ,	   0x11800a00033c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT121"         ,	   0x11800a00033c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT122"         ,	   0x11800a00033d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT123"         ,	   0x11800a00033d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT124"         ,	   0x11800a00033e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT125"         ,	   0x11800a00033e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT126"         ,	   0x11800a00033f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT127"         ,	   0x11800a00033f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT128"         ,	   0x11800a0003400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT129"         ,	   0x11800a0003408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT130"         ,	   0x11800a0003410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT131"         ,	   0x11800a0003418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT132"         ,	   0x11800a0003420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT133"         ,	   0x11800a0003428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT134"         ,	   0x11800a0003430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT135"         ,	   0x11800a0003438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT136"         ,	   0x11800a0003440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT137"         ,	   0x11800a0003448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT138"         ,	   0x11800a0003450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT139"         ,	   0x11800a0003458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT140"         ,	   0x11800a0003460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT141"         ,	   0x11800a0003468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT142"         ,	   0x11800a0003470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT143"         ,	   0x11800a0003478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT144"         ,	   0x11800a0003480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT145"         ,	   0x11800a0003488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT146"         ,	   0x11800a0003490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT147"         ,	   0x11800a0003498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT148"         ,	   0x11800a00034a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT149"         ,	   0x11800a00034a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT150"         ,	   0x11800a00034b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT151"         ,	   0x11800a00034b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT152"         ,	   0x11800a00034c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT153"         ,	   0x11800a00034c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT154"         ,	   0x11800a00034d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT155"         ,	   0x11800a00034d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT156"         ,	   0x11800a00034e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT157"         ,	   0x11800a00034e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT158"         ,	   0x11800a00034f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT159"         ,	   0x11800a00034f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT160"         ,	   0x11800a0003500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT161"         ,	   0x11800a0003508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT162"         ,	   0x11800a0003510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT163"         ,	   0x11800a0003518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT164"         ,	   0x11800a0003520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT165"         ,	   0x11800a0003528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT166"         ,	   0x11800a0003530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT167"         ,	   0x11800a0003538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT168"         ,	   0x11800a0003540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT169"         ,	   0x11800a0003548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT170"         ,	   0x11800a0003550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT171"         ,	   0x11800a0003558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT172"         ,	   0x11800a0003560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT173"         ,	   0x11800a0003568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT174"         ,	   0x11800a0003570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT175"         ,	   0x11800a0003578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT176"         ,	   0x11800a0003580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT177"         ,	   0x11800a0003588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT178"         ,	   0x11800a0003590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT179"         ,	   0x11800a0003598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT180"         ,	   0x11800a00035a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT181"         ,	   0x11800a00035a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT182"         ,	   0x11800a00035b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT183"         ,	   0x11800a00035b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT184"         ,	   0x11800a00035c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT185"         ,	   0x11800a00035c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT186"         ,	   0x11800a00035d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT187"         ,	   0x11800a00035d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT188"         ,	   0x11800a00035e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT189"         ,	   0x11800a00035e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT190"         ,	   0x11800a00035f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT191"         ,	   0x11800a00035f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT192"         ,	   0x11800a0003600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT193"         ,	   0x11800a0003608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT194"         ,	   0x11800a0003610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT195"         ,	   0x11800a0003618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT196"         ,	   0x11800a0003620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT197"         ,	   0x11800a0003628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT198"         ,	   0x11800a0003630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT199"         ,	   0x11800a0003638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT200"         ,	   0x11800a0003640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT201"         ,	   0x11800a0003648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT202"         ,	   0x11800a0003650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT203"         ,	   0x11800a0003658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT204"         ,	   0x11800a0003660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT205"         ,	   0x11800a0003668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT206"         ,	   0x11800a0003670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT207"         ,	   0x11800a0003678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT208"         ,	   0x11800a0003680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT209"         ,	   0x11800a0003688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT210"         ,	   0x11800a0003690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT211"         ,	   0x11800a0003698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT212"         ,	   0x11800a00036a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT213"         ,	   0x11800a00036a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT214"         ,	   0x11800a00036b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT215"         ,	   0x11800a00036b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT216"         ,	   0x11800a00036c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT217"         ,	   0x11800a00036c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT218"         ,	   0x11800a00036d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT219"         ,	   0x11800a00036d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT220"         ,	   0x11800a00036e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT221"         ,	   0x11800a00036e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT222"         ,	   0x11800a00036f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT223"         ,	   0x11800a00036f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT224"         ,	   0x11800a0003700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT225"         ,	   0x11800a0003708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT226"         ,	   0x11800a0003710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT227"         ,	   0x11800a0003718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT228"         ,	   0x11800a0003720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT229"         ,	   0x11800a0003728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT230"         ,	   0x11800a0003730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT231"         ,	   0x11800a0003738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT232"         ,	   0x11800a0003740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT233"         ,	   0x11800a0003748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT234"         ,	   0x11800a0003750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT235"         ,	   0x11800a0003758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT236"         ,	   0x11800a0003760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT237"         ,	   0x11800a0003768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT238"         ,	   0x11800a0003770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT239"         ,	   0x11800a0003778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT240"         ,	   0x11800a0003780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT241"         ,	   0x11800a0003788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT242"         ,	   0x11800a0003790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT243"         ,	   0x11800a0003798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT244"         ,	   0x11800a00037a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT245"         ,	   0x11800a00037a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT246"         ,	   0x11800a00037b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT247"         ,	   0x11800a00037b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT248"         ,	   0x11800a00037c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT249"         ,	   0x11800a00037c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT250"         ,	   0x11800a00037d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT251"         ,	   0x11800a00037d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT252"         ,	   0x11800a00037e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT253"         ,	   0x11800a00037e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT254"         ,	   0x11800a00037f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT255"         ,	   0x11800a00037f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT256"         ,	   0x11800a0003800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT257"         ,	   0x11800a0003808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT258"         ,	   0x11800a0003810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT259"         ,	   0x11800a0003818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT260"         ,	   0x11800a0003820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT261"         ,	   0x11800a0003828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT262"         ,	   0x11800a0003830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT263"         ,	   0x11800a0003838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT264"         ,	   0x11800a0003840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT265"         ,	   0x11800a0003848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT266"         ,	   0x11800a0003850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT267"         ,	   0x11800a0003858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT268"         ,	   0x11800a0003860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT269"         ,	   0x11800a0003868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT270"         ,	   0x11800a0003870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT271"         ,	   0x11800a0003878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT272"         ,	   0x11800a0003880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT273"         ,	   0x11800a0003888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT274"         ,	   0x11800a0003890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT275"         ,	   0x11800a0003898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT276"         ,	   0x11800a00038a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT277"         ,	   0x11800a00038a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT278"         ,	   0x11800a00038b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT279"         ,	   0x11800a00038b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT280"         ,	   0x11800a00038c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT281"         ,	   0x11800a00038c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT282"         ,	   0x11800a00038d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT283"         ,	   0x11800a00038d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT284"         ,	   0x11800a00038e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT285"         ,	   0x11800a00038e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT286"         ,	   0x11800a00038f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT287"         ,	   0x11800a00038f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT288"         ,	   0x11800a0003900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT289"         ,	   0x11800a0003908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT290"         ,	   0x11800a0003910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT291"         ,	   0x11800a0003918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT292"         ,	   0x11800a0003920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT293"         ,	   0x11800a0003928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT294"         ,	   0x11800a0003930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT295"         ,	   0x11800a0003938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT296"         ,	   0x11800a0003940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT297"         ,	   0x11800a0003948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT298"         ,	   0x11800a0003950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT299"         ,	   0x11800a0003958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT300"         ,	   0x11800a0003960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT301"         ,	   0x11800a0003968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT302"         ,	   0x11800a0003970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT303"         ,	   0x11800a0003978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT304"         ,	   0x11800a0003980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT305"         ,	   0x11800a0003988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT306"         ,	   0x11800a0003990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT307"         ,	   0x11800a0003998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT308"         ,	   0x11800a00039a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT309"         ,	   0x11800a00039a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT310"         ,	   0x11800a00039b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT311"         ,	   0x11800a00039b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT312"         ,	   0x11800a00039c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT313"         ,	   0x11800a00039c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT314"         ,	   0x11800a00039d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT315"         ,	   0x11800a00039d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT316"         ,	   0x11800a00039e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT317"         ,	   0x11800a00039e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT318"         ,	   0x11800a00039f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT319"         ,	   0x11800a00039f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT320"         ,	   0x11800a0003a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT321"         ,	   0x11800a0003a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT322"         ,	   0x11800a0003a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT323"         ,	   0x11800a0003a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT324"         ,	   0x11800a0003a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT325"         ,	   0x11800a0003a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT326"         ,	   0x11800a0003a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT327"         ,	   0x11800a0003a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT328"         ,	   0x11800a0003a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT329"         ,	   0x11800a0003a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT330"         ,	   0x11800a0003a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT331"         ,	   0x11800a0003a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT332"         ,	   0x11800a0003a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT333"         ,	   0x11800a0003a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT334"         ,	   0x11800a0003a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT335"         ,	   0x11800a0003a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT336"         ,	   0x11800a0003a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT337"         ,	   0x11800a0003a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT338"         ,	   0x11800a0003a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT339"         ,	   0x11800a0003a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT340"         ,	   0x11800a0003aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT341"         ,	   0x11800a0003aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT342"         ,	   0x11800a0003ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT343"         ,	   0x11800a0003ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT344"         ,	   0x11800a0003ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT345"         ,	   0x11800a0003ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT346"         ,	   0x11800a0003ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT347"         ,	   0x11800a0003ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT348"         ,	   0x11800a0003ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT349"         ,	   0x11800a0003ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT350"         ,	   0x11800a0003af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT351"         ,	   0x11800a0003af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT352"         ,	   0x11800a0003b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT353"         ,	   0x11800a0003b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT354"         ,	   0x11800a0003b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT355"         ,	   0x11800a0003b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT356"         ,	   0x11800a0003b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT357"         ,	   0x11800a0003b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT358"         ,	   0x11800a0003b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT359"         ,	   0x11800a0003b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT360"         ,	   0x11800a0003b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT361"         ,	   0x11800a0003b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT362"         ,	   0x11800a0003b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT363"         ,	   0x11800a0003b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT364"         ,	   0x11800a0003b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT365"         ,	   0x11800a0003b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT366"         ,	   0x11800a0003b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT367"         ,	   0x11800a0003b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT368"         ,	   0x11800a0003b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT369"         ,	   0x11800a0003b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT370"         ,	   0x11800a0003b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT371"         ,	   0x11800a0003b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT372"         ,	   0x11800a0003ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT373"         ,	   0x11800a0003ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT374"         ,	   0x11800a0003bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT375"         ,	   0x11800a0003bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT376"         ,	   0x11800a0003bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT377"         ,	   0x11800a0003bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT378"         ,	   0x11800a0003bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT379"         ,	   0x11800a0003bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT380"         ,	   0x11800a0003be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT381"         ,	   0x11800a0003be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT382"         ,	   0x11800a0003bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT383"         ,	   0x11800a0003bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT384"         ,	   0x11800a0003c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT385"         ,	   0x11800a0003c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT386"         ,	   0x11800a0003c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT387"         ,	   0x11800a0003c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT388"         ,	   0x11800a0003c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT389"         ,	   0x11800a0003c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT390"         ,	   0x11800a0003c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT391"         ,	   0x11800a0003c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT392"         ,	   0x11800a0003c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT393"         ,	   0x11800a0003c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT394"         ,	   0x11800a0003c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT395"         ,	   0x11800a0003c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT396"         ,	   0x11800a0003c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT397"         ,	   0x11800a0003c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT398"         ,	   0x11800a0003c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT399"         ,	   0x11800a0003c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT400"         ,	   0x11800a0003c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT401"         ,	   0x11800a0003c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT402"         ,	   0x11800a0003c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT403"         ,	   0x11800a0003c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT404"         ,	   0x11800a0003ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT405"         ,	   0x11800a0003ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT406"         ,	   0x11800a0003cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT407"         ,	   0x11800a0003cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT408"         ,	   0x11800a0003cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT409"         ,	   0x11800a0003cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT410"         ,	   0x11800a0003cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT411"         ,	   0x11800a0003cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT412"         ,	   0x11800a0003ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT413"         ,	   0x11800a0003ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT414"         ,	   0x11800a0003cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT415"         ,	   0x11800a0003cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT416"         ,	   0x11800a0003d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT417"         ,	   0x11800a0003d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT418"         ,	   0x11800a0003d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT419"         ,	   0x11800a0003d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT420"         ,	   0x11800a0003d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT421"         ,	   0x11800a0003d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT422"         ,	   0x11800a0003d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT423"         ,	   0x11800a0003d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT424"         ,	   0x11800a0003d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT425"         ,	   0x11800a0003d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT426"         ,	   0x11800a0003d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT427"         ,	   0x11800a0003d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT428"         ,	   0x11800a0003d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT429"         ,	   0x11800a0003d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT430"         ,	   0x11800a0003d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT431"         ,	   0x11800a0003d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT432"         ,	   0x11800a0003d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT433"         ,	   0x11800a0003d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT434"         ,	   0x11800a0003d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT435"         ,	   0x11800a0003d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT436"         ,	   0x11800a0003da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT437"         ,	   0x11800a0003da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT438"         ,	   0x11800a0003db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT439"         ,	   0x11800a0003db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT440"         ,	   0x11800a0003dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT441"         ,	   0x11800a0003dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT442"         ,	   0x11800a0003dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT443"         ,	   0x11800a0003dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT444"         ,	   0x11800a0003de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT445"         ,	   0x11800a0003de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT446"         ,	   0x11800a0003df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT447"         ,	   0x11800a0003df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT448"         ,	   0x11800a0003e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT449"         ,	   0x11800a0003e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT450"         ,	   0x11800a0003e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT451"         ,	   0x11800a0003e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT452"         ,	   0x11800a0003e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT453"         ,	   0x11800a0003e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT454"         ,	   0x11800a0003e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT455"         ,	   0x11800a0003e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT456"         ,	   0x11800a0003e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT457"         ,	   0x11800a0003e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT458"         ,	   0x11800a0003e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT459"         ,	   0x11800a0003e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT460"         ,	   0x11800a0003e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT461"         ,	   0x11800a0003e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT462"         ,	   0x11800a0003e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT463"         ,	   0x11800a0003e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT464"         ,	   0x11800a0003e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT465"         ,	   0x11800a0003e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT466"         ,	   0x11800a0003e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT467"         ,	   0x11800a0003e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT468"         ,	   0x11800a0003ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT469"         ,	   0x11800a0003ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT470"         ,	   0x11800a0003eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT471"         ,	   0x11800a0003eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT472"         ,	   0x11800a0003ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT473"         ,	   0x11800a0003ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT474"         ,	   0x11800a0003ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT475"         ,	   0x11800a0003ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT476"         ,	   0x11800a0003ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT477"         ,	   0x11800a0003ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT478"         ,	   0x11800a0003ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT479"         ,	   0x11800a0003ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT480"         ,	   0x11800a0003f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT481"         ,	   0x11800a0003f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT482"         ,	   0x11800a0003f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT483"         ,	   0x11800a0003f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT484"         ,	   0x11800a0003f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT485"         ,	   0x11800a0003f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT486"         ,	   0x11800a0003f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT487"         ,	   0x11800a0003f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT488"         ,	   0x11800a0003f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT489"         ,	   0x11800a0003f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT490"         ,	   0x11800a0003f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT491"         ,	   0x11800a0003f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT492"         ,	   0x11800a0003f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT493"         ,	   0x11800a0003f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT494"         ,	   0x11800a0003f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT495"         ,	   0x11800a0003f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT496"         ,	   0x11800a0003f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT497"         ,	   0x11800a0003f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT498"         ,	   0x11800a0003f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT499"         ,	   0x11800a0003f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT500"         ,	   0x11800a0003fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT501"         ,	   0x11800a0003fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT502"         ,	   0x11800a0003fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT503"         ,	   0x11800a0003fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT504"         ,	   0x11800a0003fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT505"         ,	   0x11800a0003fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT506"         ,	   0x11800a0003fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT507"         ,	   0x11800a0003fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT508"         ,	   0x11800a0003fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT509"         ,	   0x11800a0003fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT510"         ,	   0x11800a0003ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_BSEL_TBL_ENT511"         ,	   0x11800a0003ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"PIP_CLKEN"                   ,	   0x11800a0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	898},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800a0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	899},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800a0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	899},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800a0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	899},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800a0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	899},
+	{"PIP_DSA_SRC_GRP"             ,	   0x11800a0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	900},
+	{"PIP_DSA_VID_GRP"             ,	   0x11800a0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	901},
+	{"PIP_FRM_LEN_CHK0"            ,	   0x11800a0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	902},
+	{"PIP_GBL_CFG"                 ,	   0x11800a0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	903},
+	{"PIP_GBL_CTL"                 ,	   0x11800a0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	904},
+	{"PIP_HG_PRI_QOS"              ,	   0x11800a00001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	905},
+	{"PIP_INT_EN"                  ,	   0x11800a0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	906},
+	{"PIP_INT_REG"                 ,	   0x11800a0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	907},
+	{"PIP_IP_OFFSET"               ,	   0x11800a0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	908},
+	{"PIP_PRT_CFG0"                ,	   0x11800a0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	909},
+	{"PIP_PRT_CFG1"                ,	   0x11800a0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	909},
+	{"PIP_PRT_CFG32"               ,	   0x11800a0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	909},
+	{"PIP_PRT_CFG33"               ,	   0x11800a0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	909},
+	{"PIP_PRT_CFG34"               ,	   0x11800a0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	909},
+	{"PIP_PRT_CFG35"               ,	   0x11800a0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	909},
+	{"PIP_PRT_CFG36"               ,	   0x11800a0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	909},
+	{"PIP_PRT_CFG37"               ,	   0x11800a0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	909},
+	{"PIP_PRT_CFG38"               ,	   0x11800a0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	909},
+	{"PIP_PRT_CFG39"               ,	   0x11800a0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	909},
+	{"PIP_PRT_CFGB0"               ,	   0x11800a0008000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	910},
+	{"PIP_PRT_CFGB1"               ,	   0x11800a0008008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	910},
+	{"PIP_PRT_CFGB2"               ,	   0x11800a0008010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	910},
+	{"PIP_PRT_CFGB3"               ,	   0x11800a0008018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	910},
+	{"PIP_PRT_CFGB16"              ,	   0x11800a0008080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	910},
+	{"PIP_PRT_CFGB17"              ,	   0x11800a0008088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	910},
+	{"PIP_PRT_CFGB18"              ,	   0x11800a0008090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	910},
+	{"PIP_PRT_CFGB19"              ,	   0x11800a0008098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	910},
+	{"PIP_PRT_CFGB32"              ,	   0x11800a0008100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	910},
+	{"PIP_PRT_CFGB33"              ,	   0x11800a0008108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	910},
+	{"PIP_PRT_CFGB34"              ,	   0x11800a0008110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	910},
+	{"PIP_PRT_CFGB35"              ,	   0x11800a0008118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	910},
+	{"PIP_PRT_CFGB36"              ,	   0x11800a0008120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	910},
+	{"PIP_PRT_CFGB37"              ,	   0x11800a0008128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	910},
+	{"PIP_PRT_CFGB38"              ,	   0x11800a0008130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	910},
+	{"PIP_PRT_CFGB39"              ,	   0x11800a0008138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	910},
+	{"PIP_PRT_TAG0"                ,	   0x11800a0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	911},
+	{"PIP_PRT_TAG1"                ,	   0x11800a0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	911},
+	{"PIP_PRT_TAG32"               ,	   0x11800a0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	911},
+	{"PIP_PRT_TAG33"               ,	   0x11800a0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	911},
+	{"PIP_PRT_TAG34"               ,	   0x11800a0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	911},
+	{"PIP_PRT_TAG35"               ,	   0x11800a0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	911},
+	{"PIP_PRT_TAG36"               ,	   0x11800a0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	911},
+	{"PIP_PRT_TAG37"               ,	   0x11800a0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	911},
+	{"PIP_PRT_TAG38"               ,	   0x11800a0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	911},
+	{"PIP_PRT_TAG39"               ,	   0x11800a0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	911},
+	{"PIP_QOS_DIFF0"               ,	   0x11800a0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF1"               ,	   0x11800a0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF2"               ,	   0x11800a0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF3"               ,	   0x11800a0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF4"               ,	   0x11800a0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF5"               ,	   0x11800a0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF6"               ,	   0x11800a0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF7"               ,	   0x11800a0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF8"               ,	   0x11800a0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF9"               ,	   0x11800a0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF10"              ,	   0x11800a0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF11"              ,	   0x11800a0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF12"              ,	   0x11800a0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF13"              ,	   0x11800a0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF14"              ,	   0x11800a0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF15"              ,	   0x11800a0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF16"              ,	   0x11800a0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF17"              ,	   0x11800a0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF18"              ,	   0x11800a0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF19"              ,	   0x11800a0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF20"              ,	   0x11800a00006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF21"              ,	   0x11800a00006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF22"              ,	   0x11800a00006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF23"              ,	   0x11800a00006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF24"              ,	   0x11800a00006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF25"              ,	   0x11800a00006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF26"              ,	   0x11800a00006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF27"              ,	   0x11800a00006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF28"              ,	   0x11800a00006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF29"              ,	   0x11800a00006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF30"              ,	   0x11800a00006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF31"              ,	   0x11800a00006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF32"              ,	   0x11800a0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF33"              ,	   0x11800a0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF34"              ,	   0x11800a0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF35"              ,	   0x11800a0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF36"              ,	   0x11800a0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF37"              ,	   0x11800a0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF38"              ,	   0x11800a0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF39"              ,	   0x11800a0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF40"              ,	   0x11800a0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF41"              ,	   0x11800a0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF42"              ,	   0x11800a0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF43"              ,	   0x11800a0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF44"              ,	   0x11800a0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF45"              ,	   0x11800a0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF46"              ,	   0x11800a0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF47"              ,	   0x11800a0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF48"              ,	   0x11800a0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF49"              ,	   0x11800a0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF50"              ,	   0x11800a0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF51"              ,	   0x11800a0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF52"              ,	   0x11800a00007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF53"              ,	   0x11800a00007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF54"              ,	   0x11800a00007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF55"              ,	   0x11800a00007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF56"              ,	   0x11800a00007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF57"              ,	   0x11800a00007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF58"              ,	   0x11800a00007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF59"              ,	   0x11800a00007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF60"              ,	   0x11800a00007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF61"              ,	   0x11800a00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF62"              ,	   0x11800a00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_DIFF63"              ,	   0x11800a00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	912},
+	{"PIP_QOS_VLAN0"               ,	   0x11800a00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	913},
+	{"PIP_QOS_VLAN1"               ,	   0x11800a00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	913},
+	{"PIP_QOS_VLAN2"               ,	   0x11800a00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	913},
+	{"PIP_QOS_VLAN3"               ,	   0x11800a00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	913},
+	{"PIP_QOS_VLAN4"               ,	   0x11800a00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	913},
+	{"PIP_QOS_VLAN5"               ,	   0x11800a00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	913},
+	{"PIP_QOS_VLAN6"               ,	   0x11800a00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	913},
+	{"PIP_QOS_VLAN7"               ,	   0x11800a00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	913},
+	{"PIP_QOS_WATCH0"              ,	   0x11800a0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	914},
+	{"PIP_QOS_WATCH1"              ,	   0x11800a0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	914},
+	{"PIP_QOS_WATCH2"              ,	   0x11800a0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	914},
+	{"PIP_QOS_WATCH3"              ,	   0x11800a0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	914},
+	{"PIP_QOS_WATCH4"              ,	   0x11800a0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	914},
+	{"PIP_QOS_WATCH5"              ,	   0x11800a0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	914},
+	{"PIP_QOS_WATCH6"              ,	   0x11800a0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	914},
+	{"PIP_QOS_WATCH7"              ,	   0x11800a0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	914},
+	{"PIP_RAW_WORD"                ,	   0x11800a00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	915},
+	{"PIP_SFT_RST"                 ,	   0x11800a0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	916},
+	{"PIP_STAT0_PRT0"              ,	   0x11800a0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	917},
+	{"PIP_STAT0_PRT1"              ,	   0x11800a0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	917},
+	{"PIP_STAT0_PRT32"             ,	   0x11800a0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	917},
+	{"PIP_STAT0_PRT33"             ,	   0x11800a0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	917},
+	{"PIP_STAT0_PRT34"             ,	   0x11800a00012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	917},
+	{"PIP_STAT0_PRT35"             ,	   0x11800a00012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	917},
+	{"PIP_STAT0_PRT36"             ,	   0x11800a0001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	917},
+	{"PIP_STAT0_PRT37"             ,	   0x11800a0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	917},
+	{"PIP_STAT0_PRT38"             ,	   0x11800a00013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	917},
+	{"PIP_STAT0_PRT39"             ,	   0x11800a0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	917},
+	{"PIP_STAT10_PRT0"             ,	   0x11800a0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	918},
+	{"PIP_STAT10_PRT1"             ,	   0x11800a0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	918},
+	{"PIP_STAT10_PRT32"            ,	   0x11800a0001680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	918},
+	{"PIP_STAT10_PRT33"            ,	   0x11800a0001690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	918},
+	{"PIP_STAT10_PRT34"            ,	   0x11800a00016a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	918},
+	{"PIP_STAT10_PRT35"            ,	   0x11800a00016b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	918},
+	{"PIP_STAT10_PRT36"            ,	   0x11800a00016c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	918},
+	{"PIP_STAT10_PRT37"            ,	   0x11800a00016d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	918},
+	{"PIP_STAT10_PRT38"            ,	   0x11800a00016e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	918},
+	{"PIP_STAT10_PRT39"            ,	   0x11800a00016f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	918},
+	{"PIP_STAT11_PRT0"             ,	   0x11800a0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	919},
+	{"PIP_STAT11_PRT1"             ,	   0x11800a0001498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	919},
+	{"PIP_STAT11_PRT32"            ,	   0x11800a0001688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	919},
+	{"PIP_STAT11_PRT33"            ,	   0x11800a0001698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	919},
+	{"PIP_STAT11_PRT34"            ,	   0x11800a00016a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	919},
+	{"PIP_STAT11_PRT35"            ,	   0x11800a00016b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	919},
+	{"PIP_STAT11_PRT36"            ,	   0x11800a00016c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	919},
+	{"PIP_STAT11_PRT37"            ,	   0x11800a00016d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	919},
+	{"PIP_STAT11_PRT38"            ,	   0x11800a00016e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	919},
+	{"PIP_STAT11_PRT39"            ,	   0x11800a00016f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	919},
+	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	920},
+	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	920},
+	{"PIP_STAT1_PRT32"             ,	   0x11800a0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	920},
+	{"PIP_STAT1_PRT33"             ,	   0x11800a0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	920},
+	{"PIP_STAT1_PRT34"             ,	   0x11800a00012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	920},
+	{"PIP_STAT1_PRT35"             ,	   0x11800a00012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	920},
+	{"PIP_STAT1_PRT36"             ,	   0x11800a0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	920},
+	{"PIP_STAT1_PRT37"             ,	   0x11800a0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	920},
+	{"PIP_STAT1_PRT38"             ,	   0x11800a00013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	920},
+	{"PIP_STAT1_PRT39"             ,	   0x11800a0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	920},
+	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	921},
+	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	921},
+	{"PIP_STAT2_PRT32"             ,	   0x11800a0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	921},
+	{"PIP_STAT2_PRT33"             ,	   0x11800a0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	921},
+	{"PIP_STAT2_PRT34"             ,	   0x11800a00012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	921},
+	{"PIP_STAT2_PRT35"             ,	   0x11800a0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	921},
+	{"PIP_STAT2_PRT36"             ,	   0x11800a0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	921},
+	{"PIP_STAT2_PRT37"             ,	   0x11800a00013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	921},
+	{"PIP_STAT2_PRT38"             ,	   0x11800a00013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	921},
+	{"PIP_STAT2_PRT39"             ,	   0x11800a0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	921},
+	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	922},
+	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	922},
+	{"PIP_STAT3_PRT32"             ,	   0x11800a0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	922},
+	{"PIP_STAT3_PRT33"             ,	   0x11800a0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	922},
+	{"PIP_STAT3_PRT34"             ,	   0x11800a00012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	922},
+	{"PIP_STAT3_PRT35"             ,	   0x11800a0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	922},
+	{"PIP_STAT3_PRT36"             ,	   0x11800a0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	922},
+	{"PIP_STAT3_PRT37"             ,	   0x11800a00013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	922},
+	{"PIP_STAT3_PRT38"             ,	   0x11800a00013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	922},
+	{"PIP_STAT3_PRT39"             ,	   0x11800a0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	922},
+	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	923},
+	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	923},
+	{"PIP_STAT4_PRT32"             ,	   0x11800a0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	923},
+	{"PIP_STAT4_PRT33"             ,	   0x11800a0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	923},
+	{"PIP_STAT4_PRT34"             ,	   0x11800a00012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	923},
+	{"PIP_STAT4_PRT35"             ,	   0x11800a0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	923},
+	{"PIP_STAT4_PRT36"             ,	   0x11800a0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	923},
+	{"PIP_STAT4_PRT37"             ,	   0x11800a00013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	923},
+	{"PIP_STAT4_PRT38"             ,	   0x11800a0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	923},
+	{"PIP_STAT4_PRT39"             ,	   0x11800a0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	923},
+	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	924},
+	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	924},
+	{"PIP_STAT5_PRT32"             ,	   0x11800a0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	924},
+	{"PIP_STAT5_PRT33"             ,	   0x11800a0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	924},
+	{"PIP_STAT5_PRT34"             ,	   0x11800a00012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	924},
+	{"PIP_STAT5_PRT35"             ,	   0x11800a0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	924},
+	{"PIP_STAT5_PRT36"             ,	   0x11800a0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	924},
+	{"PIP_STAT5_PRT37"             ,	   0x11800a00013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	924},
+	{"PIP_STAT5_PRT38"             ,	   0x11800a0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	924},
+	{"PIP_STAT5_PRT39"             ,	   0x11800a0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	924},
+	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	925},
+	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	925},
+	{"PIP_STAT6_PRT32"             ,	   0x11800a0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	925},
+	{"PIP_STAT6_PRT33"             ,	   0x11800a0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	925},
+	{"PIP_STAT6_PRT34"             ,	   0x11800a00012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	925},
+	{"PIP_STAT6_PRT35"             ,	   0x11800a0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	925},
+	{"PIP_STAT6_PRT36"             ,	   0x11800a0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	925},
+	{"PIP_STAT6_PRT37"             ,	   0x11800a00013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	925},
+	{"PIP_STAT6_PRT38"             ,	   0x11800a0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	925},
+	{"PIP_STAT6_PRT39"             ,	   0x11800a0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	925},
+	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	926},
+	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	926},
+	{"PIP_STAT7_PRT32"             ,	   0x11800a0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	926},
+	{"PIP_STAT7_PRT33"             ,	   0x11800a0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	926},
+	{"PIP_STAT7_PRT34"             ,	   0x11800a00012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	926},
+	{"PIP_STAT7_PRT35"             ,	   0x11800a0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	926},
+	{"PIP_STAT7_PRT36"             ,	   0x11800a0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	926},
+	{"PIP_STAT7_PRT37"             ,	   0x11800a00013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	926},
+	{"PIP_STAT7_PRT38"             ,	   0x11800a0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	926},
+	{"PIP_STAT7_PRT39"             ,	   0x11800a0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	926},
+	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	927},
+	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	927},
+	{"PIP_STAT8_PRT32"             ,	   0x11800a0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	927},
+	{"PIP_STAT8_PRT33"             ,	   0x11800a0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	927},
+	{"PIP_STAT8_PRT34"             ,	   0x11800a00012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	927},
+	{"PIP_STAT8_PRT35"             ,	   0x11800a0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	927},
+	{"PIP_STAT8_PRT36"             ,	   0x11800a0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	927},
+	{"PIP_STAT8_PRT37"             ,	   0x11800a00013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	927},
+	{"PIP_STAT8_PRT38"             ,	   0x11800a0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	927},
+	{"PIP_STAT8_PRT39"             ,	   0x11800a0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	927},
+	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	928},
+	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	928},
+	{"PIP_STAT9_PRT32"             ,	   0x11800a0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	928},
+	{"PIP_STAT9_PRT33"             ,	   0x11800a0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	928},
+	{"PIP_STAT9_PRT34"             ,	   0x11800a00012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	928},
+	{"PIP_STAT9_PRT35"             ,	   0x11800a0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	928},
+	{"PIP_STAT9_PRT36"             ,	   0x11800a0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	928},
+	{"PIP_STAT9_PRT37"             ,	   0x11800a00013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	928},
+	{"PIP_STAT9_PRT38"             ,	   0x11800a0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	928},
+	{"PIP_STAT9_PRT39"             ,	   0x11800a0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	928},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	929},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	930},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	930},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800a0001e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	930},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800a0001e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	930},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800a0001e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	930},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800a0001e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	930},
+	{"PIP_STAT_INB_ERRS36"         ,	   0x11800a0001e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	930},
+	{"PIP_STAT_INB_ERRS37"         ,	   0x11800a0001eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	930},
+	{"PIP_STAT_INB_ERRS38"         ,	   0x11800a0001ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	930},
+	{"PIP_STAT_INB_ERRS39"         ,	   0x11800a0001ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	930},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	931},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	931},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800a0001e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	931},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800a0001e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	931},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800a0001e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	931},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800a0001e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	931},
+	{"PIP_STAT_INB_OCTS36"         ,	   0x11800a0001e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	931},
+	{"PIP_STAT_INB_OCTS37"         ,	   0x11800a0001ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	931},
+	{"PIP_STAT_INB_OCTS38"         ,	   0x11800a0001ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	931},
+	{"PIP_STAT_INB_OCTS39"         ,	   0x11800a0001ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	931},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	932},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	932},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800a0001e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	932},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800a0001e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	932},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800a0001e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	932},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800a0001e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	932},
+	{"PIP_STAT_INB_PKTS36"         ,	   0x11800a0001e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	932},
+	{"PIP_STAT_INB_PKTS37"         ,	   0x11800a0001ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	932},
+	{"PIP_STAT_INB_PKTS38"         ,	   0x11800a0001ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	932},
+	{"PIP_STAT_INB_PKTS39"         ,	   0x11800a0001ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	932},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	933},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	934},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	935},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	936},
+	{"PIP_VLAN_ETYPES0"            ,	   0x11800a00001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	937},
+	{"PIP_VLAN_ETYPES1"            ,	   0x11800a00001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	937},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	938},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	940},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	941},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	942},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	943},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	944},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	945},
+	{"PKO_MEM_DEBUG14"             ,	   0x1180050001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	946},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	947},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	948},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	949},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	950},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	951},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	954},
+	{"PKO_MEM_PORT_PTRS"           ,	   0x1180050001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	955},
+	{"PKO_MEM_PORT_QOS"            ,	   0x1180050001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	956},
+	{"PKO_MEM_PORT_RATE0"          ,	   0x1180050001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	957},
+	{"PKO_MEM_PORT_RATE1"          ,	   0x1180050001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	968},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	969},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	970},
+	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	971},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	972},
+	{"PKO_REG_PREEMPT"             ,	   0x1180050000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	973},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	974},
+	{"PKO_REG_QUEUE_PREEMPT"       ,	   0x1180050000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	975},
+	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	976},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	977},
+	{"PKO_REG_TIMESTAMP"           ,	   0x1180050000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	978},
+	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	979},
+	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	980},
+	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	981},
+	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	982},
+	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	983},
+	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	983},
+	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	983},
+	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	983},
+	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	983},
+	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	983},
+	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	983},
+	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	983},
+	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	984},
+	{"POW_IQ_INT"                  ,	   0x1670000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	985},
+	{"POW_IQ_INT_EN"               ,	   0x1670000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	986},
+	{"POW_IQ_THR0"                 ,	   0x16700000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	987},
+	{"POW_IQ_THR1"                 ,	   0x16700000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	987},
+	{"POW_IQ_THR2"                 ,	   0x16700000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	987},
+	{"POW_IQ_THR3"                 ,	   0x16700000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	987},
+	{"POW_IQ_THR4"                 ,	   0x16700000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	987},
+	{"POW_IQ_THR5"                 ,	   0x16700000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	987},
+	{"POW_IQ_THR6"                 ,	   0x16700000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	987},
+	{"POW_IQ_THR7"                 ,	   0x16700000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	987},
+	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	988},
+	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	989},
+	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	990},
+	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	991},
+	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	991},
+	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	991},
+	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	991},
+	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	992},
+	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	992},
+	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	992},
+	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	992},
+	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	992},
+	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	992},
+	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	992},
+	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	992},
+	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	993},
+	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	993},
+	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	993},
+	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	993},
+	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	993},
+	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	993},
+	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	993},
+	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	993},
+	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	994},
+	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	995},
+	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	996},
+	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	996},
+	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	996},
+	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	996},
+	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	996},
+	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	996},
+	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	996},
+	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	996},
+	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	997},
+	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	998},
+	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	998},
+	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	998},
+	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	998},
+	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	998},
+	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	998},
+	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	998},
+	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	998},
+	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	998},
+	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	998},
+	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	998},
+	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	998},
+	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	998},
+	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	998},
+	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	998},
+	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	998},
+	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	999},
+	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1000},
+	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1000},
+	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1000},
+	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1000},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1000},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1000},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1000},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1000},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1000},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1000},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1000},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1000},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1000},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1000},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1000},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1000},
+	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1001},
+	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1001},
+	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1001},
+	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1001},
+	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1001},
+	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1001},
+	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1001},
+	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1001},
+	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1001},
+	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1001},
+	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1001},
+	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1001},
+	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1001},
+	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1001},
+	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1001},
+	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	1001},
+	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
+	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
+	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"RAD_REG_BIST_RESULT"         ,	   0x1180070000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"RAD_REG_CMD_BUF"             ,	   0x1180070000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"RAD_REG_CTL"                 ,	   0x1180070000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"RAD_REG_DEBUG0"              ,	   0x1180070000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"RAD_REG_DEBUG1"              ,	   0x1180070000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1009},
+	{"RAD_REG_DEBUG10"             ,	   0x1180070000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"RAD_REG_DEBUG11"             ,	   0x1180070000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"RAD_REG_DEBUG12"             ,	   0x1180070000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"RAD_REG_DEBUG2"              ,	   0x1180070000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"RAD_REG_DEBUG3"              ,	   0x1180070000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"RAD_REG_DEBUG4"              ,	   0x1180070000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"RAD_REG_DEBUG5"              ,	   0x1180070000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"RAD_REG_DEBUG6"              ,	   0x1180070000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"RAD_REG_DEBUG7"              ,	   0x1180070000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"RAD_REG_DEBUG8"              ,	   0x1180070000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"RAD_REG_DEBUG9"              ,	   0x1180070000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"RAD_REG_ERROR"               ,	   0x1180070000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"RAD_REG_INT_MASK"            ,	   0x1180070000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"RAD_REG_POLYNOMIAL"          ,	   0x1180070000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1023},
+	{"RAD_REG_READ_IDX"            ,	   0x1180070000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"RNM_EER_DBG"                 ,	   0x1180040000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"RNM_EER_KEY"                 ,	   0x1180040000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"RNM_SERIAL_NUM"              ,	   0x1180040000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1029},
+	{"SLI_BIST_STATUS"             ,	   0x11f0000010580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1030},
+	{"SLI_CTL_PORT0"               ,	   0x11f0000010050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1031},
+	{"SLI_CTL_PORT1"               ,	   0x11f0000010060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1031},
+	{"SLI_CTL_STATUS"              ,	   0x11f0000010570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1032},
+	{"SLI_DATA_OUT_CNT"            ,	   0x11f00000105f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1033},
+	{"SLI_DBG_DATA"                ,	   0x11f0000010310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1034},
+	{"SLI_DBG_SELECT"              ,	   0x11f0000010300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1035},
+	{"SLI_DMA0_CNT"                ,	   0x11f0000010400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1036},
+	{"SLI_DMA1_CNT"                ,	   0x11f0000010410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1036},
+	{"SLI_DMA0_INT_LEVEL"          ,	   0x11f00000103e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1037},
+	{"SLI_DMA1_INT_LEVEL"          ,	   0x11f00000103f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1037},
+	{"SLI_DMA0_TIM"                ,	   0x11f0000010420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1038},
+	{"SLI_DMA1_TIM"                ,	   0x11f0000010430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1038},
+	{"SLI_INT_ENB_CIU"             ,	   0x11f0000013cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1039},
+	{"SLI_INT_ENB_PORT0"           ,	   0x11f0000010340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1040},
+	{"SLI_INT_ENB_PORT1"           ,	   0x11f0000010350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1040},
+	{"SLI_INT_SUM"                 ,	   0x11f0000010330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1041},
+	{"SLI_LAST_WIN_RDATA0"         ,	   0x11f0000010600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1042},
+	{"SLI_LAST_WIN_RDATA1"         ,	   0x11f0000010610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1043},
+	{"SLI_LAST_WIN_RDATA2"         ,	   0x11f00000106c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1044},
+	{"SLI_LAST_WIN_RDATA3"         ,	   0x11f00000106d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1045},
+	{"SLI_MAC_CREDIT_CNT"          ,	   0x11f0000013d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1046},
+	{"SLI_MAC_CREDIT_CNT2"         ,	   0x11f0000013e10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1047},
+	{"SLI_MAC_NUMBER"              ,	            0x3e00ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1048},
+	{"SLI_MEM_ACCESS_CTL"          ,	   0x11f00000102f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1049},
+	{"SLI_MEM_ACCESS_SUBID12"      ,	   0x11f00000100e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1050},
+	{"SLI_MEM_ACCESS_SUBID13"      ,	   0x11f00000100f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1050},
+	{"SLI_MEM_ACCESS_SUBID14"      ,	   0x11f0000010100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1050},
+	{"SLI_MEM_ACCESS_SUBID15"      ,	   0x11f0000010110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1050},
+	{"SLI_MEM_ACCESS_SUBID16"      ,	   0x11f0000010120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1050},
+	{"SLI_MEM_ACCESS_SUBID17"      ,	   0x11f0000010130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1050},
+	{"SLI_MEM_ACCESS_SUBID18"      ,	   0x11f0000010140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1050},
+	{"SLI_MEM_ACCESS_SUBID19"      ,	   0x11f0000010150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1050},
+	{"SLI_MEM_ACCESS_SUBID20"      ,	   0x11f0000010160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1050},
+	{"SLI_MEM_ACCESS_SUBID21"      ,	   0x11f0000010170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1050},
+	{"SLI_MEM_ACCESS_SUBID22"      ,	   0x11f0000010180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1050},
+	{"SLI_MEM_ACCESS_SUBID23"      ,	   0x11f0000010190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1050},
+	{"SLI_MEM_ACCESS_SUBID24"      ,	   0x11f00000101a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1050},
+	{"SLI_MEM_ACCESS_SUBID25"      ,	   0x11f00000101b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1050},
+	{"SLI_MEM_ACCESS_SUBID26"      ,	   0x11f00000101c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1050},
+	{"SLI_MEM_ACCESS_SUBID27"      ,	   0x11f00000101d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1050},
+	{"SLI_MSI_ENB0"                ,	   0x11f0000013c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1051},
+	{"SLI_MSI_ENB1"                ,	   0x11f0000013c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1052},
+	{"SLI_MSI_ENB2"                ,	   0x11f0000013c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1053},
+	{"SLI_MSI_ENB3"                ,	   0x11f0000013c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1054},
+	{"SLI_MSI_RCV0"                ,	   0x11f0000013c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1055},
+	{"SLI_MSI_RCV1"                ,	   0x11f0000013c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1056},
+	{"SLI_MSI_RCV2"                ,	   0x11f0000013c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1057},
+	{"SLI_MSI_RCV3"                ,	   0x11f0000013c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1058},
+	{"SLI_MSI_RD_MAP"              ,	   0x11f0000013ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1059},
+	{"SLI_MSI_W1C_ENB0"            ,	   0x11f0000013cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1060},
+	{"SLI_MSI_W1C_ENB1"            ,	   0x11f0000013d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1061},
+	{"SLI_MSI_W1C_ENB2"            ,	   0x11f0000013d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1062},
+	{"SLI_MSI_W1C_ENB3"            ,	   0x11f0000013d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1063},
+	{"SLI_MSI_W1S_ENB0"            ,	   0x11f0000013d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1064},
+	{"SLI_MSI_W1S_ENB1"            ,	   0x11f0000013d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1065},
+	{"SLI_MSI_W1S_ENB2"            ,	   0x11f0000013d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1066},
+	{"SLI_MSI_W1S_ENB3"            ,	   0x11f0000013d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1067},
+	{"SLI_MSI_WR_MAP"              ,	   0x11f0000013c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1068},
+	{"SLI_PCIE_MSI_RCV"            ,	   0x11f0000013cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1069},
+	{"SLI_PCIE_MSI_RCV_B1"         ,	   0x11f0000010650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1070},
+	{"SLI_PCIE_MSI_RCV_B2"         ,	   0x11f0000010660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1071},
+	{"SLI_PCIE_MSI_RCV_B3"         ,	   0x11f0000010670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1072},
+	{"SLI_PKT0_CNTS"               ,	   0x11f0000012400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT1_CNTS"               ,	   0x11f0000012410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT2_CNTS"               ,	   0x11f0000012420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT3_CNTS"               ,	   0x11f0000012430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT4_CNTS"               ,	   0x11f0000012440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT5_CNTS"               ,	   0x11f0000012450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT6_CNTS"               ,	   0x11f0000012460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT7_CNTS"               ,	   0x11f0000012470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT8_CNTS"               ,	   0x11f0000012480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT9_CNTS"               ,	   0x11f0000012490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT10_CNTS"              ,	   0x11f00000124a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT11_CNTS"              ,	   0x11f00000124b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT12_CNTS"              ,	   0x11f00000124c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT13_CNTS"              ,	   0x11f00000124d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT14_CNTS"              ,	   0x11f00000124e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT15_CNTS"              ,	   0x11f00000124f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT16_CNTS"              ,	   0x11f0000012500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT17_CNTS"              ,	   0x11f0000012510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT18_CNTS"              ,	   0x11f0000012520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT19_CNTS"              ,	   0x11f0000012530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT20_CNTS"              ,	   0x11f0000012540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT21_CNTS"              ,	   0x11f0000012550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT22_CNTS"              ,	   0x11f0000012560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT23_CNTS"              ,	   0x11f0000012570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT24_CNTS"              ,	   0x11f0000012580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT25_CNTS"              ,	   0x11f0000012590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT26_CNTS"              ,	   0x11f00000125a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT27_CNTS"              ,	   0x11f00000125b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT28_CNTS"              ,	   0x11f00000125c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT29_CNTS"              ,	   0x11f00000125d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT30_CNTS"              ,	   0x11f00000125e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT31_CNTS"              ,	   0x11f00000125f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1073},
+	{"SLI_PKT0_IN_BP"              ,	   0x11f0000013800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT1_IN_BP"              ,	   0x11f0000013810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT2_IN_BP"              ,	   0x11f0000013820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT3_IN_BP"              ,	   0x11f0000013830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT4_IN_BP"              ,	   0x11f0000013840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT5_IN_BP"              ,	   0x11f0000013850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT6_IN_BP"              ,	   0x11f0000013860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT7_IN_BP"              ,	   0x11f0000013870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT8_IN_BP"              ,	   0x11f0000013880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT9_IN_BP"              ,	   0x11f0000013890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT10_IN_BP"             ,	   0x11f00000138a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT11_IN_BP"             ,	   0x11f00000138b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT12_IN_BP"             ,	   0x11f00000138c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT13_IN_BP"             ,	   0x11f00000138d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT14_IN_BP"             ,	   0x11f00000138e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT15_IN_BP"             ,	   0x11f00000138f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT16_IN_BP"             ,	   0x11f0000013900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT17_IN_BP"             ,	   0x11f0000013910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT18_IN_BP"             ,	   0x11f0000013920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT19_IN_BP"             ,	   0x11f0000013930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT20_IN_BP"             ,	   0x11f0000013940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT21_IN_BP"             ,	   0x11f0000013950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT22_IN_BP"             ,	   0x11f0000013960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT23_IN_BP"             ,	   0x11f0000013970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT24_IN_BP"             ,	   0x11f0000013980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT25_IN_BP"             ,	   0x11f0000013990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT26_IN_BP"             ,	   0x11f00000139a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT27_IN_BP"             ,	   0x11f00000139b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT28_IN_BP"             ,	   0x11f00000139c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT29_IN_BP"             ,	   0x11f00000139d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT30_IN_BP"             ,	   0x11f00000139e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT31_IN_BP"             ,	   0x11f00000139f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1074},
+	{"SLI_PKT0_INSTR_BADDR"        ,	   0x11f0000012800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT1_INSTR_BADDR"        ,	   0x11f0000012810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT2_INSTR_BADDR"        ,	   0x11f0000012820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT3_INSTR_BADDR"        ,	   0x11f0000012830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT4_INSTR_BADDR"        ,	   0x11f0000012840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT5_INSTR_BADDR"        ,	   0x11f0000012850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT6_INSTR_BADDR"        ,	   0x11f0000012860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT7_INSTR_BADDR"        ,	   0x11f0000012870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT8_INSTR_BADDR"        ,	   0x11f0000012880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT9_INSTR_BADDR"        ,	   0x11f0000012890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT10_INSTR_BADDR"       ,	   0x11f00000128a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT11_INSTR_BADDR"       ,	   0x11f00000128b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT12_INSTR_BADDR"       ,	   0x11f00000128c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT13_INSTR_BADDR"       ,	   0x11f00000128d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT14_INSTR_BADDR"       ,	   0x11f00000128e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT15_INSTR_BADDR"       ,	   0x11f00000128f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT16_INSTR_BADDR"       ,	   0x11f0000012900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT17_INSTR_BADDR"       ,	   0x11f0000012910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT18_INSTR_BADDR"       ,	   0x11f0000012920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT19_INSTR_BADDR"       ,	   0x11f0000012930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT20_INSTR_BADDR"       ,	   0x11f0000012940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT21_INSTR_BADDR"       ,	   0x11f0000012950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT22_INSTR_BADDR"       ,	   0x11f0000012960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT23_INSTR_BADDR"       ,	   0x11f0000012970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT24_INSTR_BADDR"       ,	   0x11f0000012980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT25_INSTR_BADDR"       ,	   0x11f0000012990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT26_INSTR_BADDR"       ,	   0x11f00000129a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT27_INSTR_BADDR"       ,	   0x11f00000129b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT28_INSTR_BADDR"       ,	   0x11f00000129c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT29_INSTR_BADDR"       ,	   0x11f00000129d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT30_INSTR_BADDR"       ,	   0x11f00000129e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT31_INSTR_BADDR"       ,	   0x11f00000129f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1075},
+	{"SLI_PKT0_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT1_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT2_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT3_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT4_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT5_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT6_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT7_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT8_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT9_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT10_INSTR_BAOFF_DBELL" ,	   0x11f0000012ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT11_INSTR_BAOFF_DBELL" ,	   0x11f0000012cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT12_INSTR_BAOFF_DBELL" ,	   0x11f0000012cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT13_INSTR_BAOFF_DBELL" ,	   0x11f0000012cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT14_INSTR_BAOFF_DBELL" ,	   0x11f0000012ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT15_INSTR_BAOFF_DBELL" ,	   0x11f0000012cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT16_INSTR_BAOFF_DBELL" ,	   0x11f0000012d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT17_INSTR_BAOFF_DBELL" ,	   0x11f0000012d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT18_INSTR_BAOFF_DBELL" ,	   0x11f0000012d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT19_INSTR_BAOFF_DBELL" ,	   0x11f0000012d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT20_INSTR_BAOFF_DBELL" ,	   0x11f0000012d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT21_INSTR_BAOFF_DBELL" ,	   0x11f0000012d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT22_INSTR_BAOFF_DBELL" ,	   0x11f0000012d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT23_INSTR_BAOFF_DBELL" ,	   0x11f0000012d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT24_INSTR_BAOFF_DBELL" ,	   0x11f0000012d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT25_INSTR_BAOFF_DBELL" ,	   0x11f0000012d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT26_INSTR_BAOFF_DBELL" ,	   0x11f0000012da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT27_INSTR_BAOFF_DBELL" ,	   0x11f0000012db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT28_INSTR_BAOFF_DBELL" ,	   0x11f0000012dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT29_INSTR_BAOFF_DBELL" ,	   0x11f0000012dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT30_INSTR_BAOFF_DBELL" ,	   0x11f0000012de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT31_INSTR_BAOFF_DBELL" ,	   0x11f0000012df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1076},
+	{"SLI_PKT0_INSTR_FIFO_RSIZE"   ,	   0x11f0000013000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT1_INSTR_FIFO_RSIZE"   ,	   0x11f0000013010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT2_INSTR_FIFO_RSIZE"   ,	   0x11f0000013020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT3_INSTR_FIFO_RSIZE"   ,	   0x11f0000013030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT4_INSTR_FIFO_RSIZE"   ,	   0x11f0000013040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT5_INSTR_FIFO_RSIZE"   ,	   0x11f0000013050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT6_INSTR_FIFO_RSIZE"   ,	   0x11f0000013060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT7_INSTR_FIFO_RSIZE"   ,	   0x11f0000013070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT8_INSTR_FIFO_RSIZE"   ,	   0x11f0000013080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT9_INSTR_FIFO_RSIZE"   ,	   0x11f0000013090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT10_INSTR_FIFO_RSIZE"  ,	   0x11f00000130a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT11_INSTR_FIFO_RSIZE"  ,	   0x11f00000130b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT12_INSTR_FIFO_RSIZE"  ,	   0x11f00000130c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT13_INSTR_FIFO_RSIZE"  ,	   0x11f00000130d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT14_INSTR_FIFO_RSIZE"  ,	   0x11f00000130e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT15_INSTR_FIFO_RSIZE"  ,	   0x11f00000130f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT16_INSTR_FIFO_RSIZE"  ,	   0x11f0000013100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT17_INSTR_FIFO_RSIZE"  ,	   0x11f0000013110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT18_INSTR_FIFO_RSIZE"  ,	   0x11f0000013120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT19_INSTR_FIFO_RSIZE"  ,	   0x11f0000013130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT20_INSTR_FIFO_RSIZE"  ,	   0x11f0000013140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT21_INSTR_FIFO_RSIZE"  ,	   0x11f0000013150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT22_INSTR_FIFO_RSIZE"  ,	   0x11f0000013160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT23_INSTR_FIFO_RSIZE"  ,	   0x11f0000013170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT24_INSTR_FIFO_RSIZE"  ,	   0x11f0000013180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT25_INSTR_FIFO_RSIZE"  ,	   0x11f0000013190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT26_INSTR_FIFO_RSIZE"  ,	   0x11f00000131a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT27_INSTR_FIFO_RSIZE"  ,	   0x11f00000131b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT28_INSTR_FIFO_RSIZE"  ,	   0x11f00000131c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT29_INSTR_FIFO_RSIZE"  ,	   0x11f00000131d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT30_INSTR_FIFO_RSIZE"  ,	   0x11f00000131e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT31_INSTR_FIFO_RSIZE"  ,	   0x11f00000131f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077},
+	{"SLI_PKT0_INSTR_HEADER"       ,	   0x11f0000013400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT1_INSTR_HEADER"       ,	   0x11f0000013410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT2_INSTR_HEADER"       ,	   0x11f0000013420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT3_INSTR_HEADER"       ,	   0x11f0000013430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT4_INSTR_HEADER"       ,	   0x11f0000013440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT5_INSTR_HEADER"       ,	   0x11f0000013450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT6_INSTR_HEADER"       ,	   0x11f0000013460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT7_INSTR_HEADER"       ,	   0x11f0000013470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT8_INSTR_HEADER"       ,	   0x11f0000013480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT9_INSTR_HEADER"       ,	   0x11f0000013490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT10_INSTR_HEADER"      ,	   0x11f00000134a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT11_INSTR_HEADER"      ,	   0x11f00000134b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT12_INSTR_HEADER"      ,	   0x11f00000134c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT13_INSTR_HEADER"      ,	   0x11f00000134d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT14_INSTR_HEADER"      ,	   0x11f00000134e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT15_INSTR_HEADER"      ,	   0x11f00000134f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT16_INSTR_HEADER"      ,	   0x11f0000013500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT17_INSTR_HEADER"      ,	   0x11f0000013510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT18_INSTR_HEADER"      ,	   0x11f0000013520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT19_INSTR_HEADER"      ,	   0x11f0000013530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT20_INSTR_HEADER"      ,	   0x11f0000013540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT21_INSTR_HEADER"      ,	   0x11f0000013550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT22_INSTR_HEADER"      ,	   0x11f0000013560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT23_INSTR_HEADER"      ,	   0x11f0000013570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT24_INSTR_HEADER"      ,	   0x11f0000013580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT25_INSTR_HEADER"      ,	   0x11f0000013590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT26_INSTR_HEADER"      ,	   0x11f00000135a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT27_INSTR_HEADER"      ,	   0x11f00000135b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT28_INSTR_HEADER"      ,	   0x11f00000135c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT29_INSTR_HEADER"      ,	   0x11f00000135d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT30_INSTR_HEADER"      ,	   0x11f00000135e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT31_INSTR_HEADER"      ,	   0x11f00000135f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078},
+	{"SLI_PKT0_OUT_SIZE"           ,	   0x11f0000010c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT1_OUT_SIZE"           ,	   0x11f0000010c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT2_OUT_SIZE"           ,	   0x11f0000010c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT3_OUT_SIZE"           ,	   0x11f0000010c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT4_OUT_SIZE"           ,	   0x11f0000010c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT5_OUT_SIZE"           ,	   0x11f0000010c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT6_OUT_SIZE"           ,	   0x11f0000010c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT7_OUT_SIZE"           ,	   0x11f0000010c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT8_OUT_SIZE"           ,	   0x11f0000010c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT9_OUT_SIZE"           ,	   0x11f0000010c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT10_OUT_SIZE"          ,	   0x11f0000010ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT11_OUT_SIZE"          ,	   0x11f0000010cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT12_OUT_SIZE"          ,	   0x11f0000010cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT13_OUT_SIZE"          ,	   0x11f0000010cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT14_OUT_SIZE"          ,	   0x11f0000010ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT15_OUT_SIZE"          ,	   0x11f0000010cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT16_OUT_SIZE"          ,	   0x11f0000010d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT17_OUT_SIZE"          ,	   0x11f0000010d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT18_OUT_SIZE"          ,	   0x11f0000010d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT19_OUT_SIZE"          ,	   0x11f0000010d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT20_OUT_SIZE"          ,	   0x11f0000010d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT21_OUT_SIZE"          ,	   0x11f0000010d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT22_OUT_SIZE"          ,	   0x11f0000010d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT23_OUT_SIZE"          ,	   0x11f0000010d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT24_OUT_SIZE"          ,	   0x11f0000010d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT25_OUT_SIZE"          ,	   0x11f0000010d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT26_OUT_SIZE"          ,	   0x11f0000010da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT27_OUT_SIZE"          ,	   0x11f0000010db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT28_OUT_SIZE"          ,	   0x11f0000010dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT29_OUT_SIZE"          ,	   0x11f0000010dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT30_OUT_SIZE"          ,	   0x11f0000010de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT31_OUT_SIZE"          ,	   0x11f0000010df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079},
+	{"SLI_PKT0_SLIST_BADDR"        ,	   0x11f0000011400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT1_SLIST_BADDR"        ,	   0x11f0000011410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT2_SLIST_BADDR"        ,	   0x11f0000011420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT3_SLIST_BADDR"        ,	   0x11f0000011430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT4_SLIST_BADDR"        ,	   0x11f0000011440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT5_SLIST_BADDR"        ,	   0x11f0000011450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT6_SLIST_BADDR"        ,	   0x11f0000011460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT7_SLIST_BADDR"        ,	   0x11f0000011470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT8_SLIST_BADDR"        ,	   0x11f0000011480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT9_SLIST_BADDR"        ,	   0x11f0000011490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT10_SLIST_BADDR"       ,	   0x11f00000114a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT11_SLIST_BADDR"       ,	   0x11f00000114b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT12_SLIST_BADDR"       ,	   0x11f00000114c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT13_SLIST_BADDR"       ,	   0x11f00000114d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT14_SLIST_BADDR"       ,	   0x11f00000114e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT15_SLIST_BADDR"       ,	   0x11f00000114f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT16_SLIST_BADDR"       ,	   0x11f0000011500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT17_SLIST_BADDR"       ,	   0x11f0000011510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT18_SLIST_BADDR"       ,	   0x11f0000011520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT19_SLIST_BADDR"       ,	   0x11f0000011530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT20_SLIST_BADDR"       ,	   0x11f0000011540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT21_SLIST_BADDR"       ,	   0x11f0000011550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT22_SLIST_BADDR"       ,	   0x11f0000011560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT23_SLIST_BADDR"       ,	   0x11f0000011570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT24_SLIST_BADDR"       ,	   0x11f0000011580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT25_SLIST_BADDR"       ,	   0x11f0000011590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT26_SLIST_BADDR"       ,	   0x11f00000115a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT27_SLIST_BADDR"       ,	   0x11f00000115b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT28_SLIST_BADDR"       ,	   0x11f00000115c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT29_SLIST_BADDR"       ,	   0x11f00000115d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT30_SLIST_BADDR"       ,	   0x11f00000115e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT31_SLIST_BADDR"       ,	   0x11f00000115f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080},
+	{"SLI_PKT0_SLIST_BAOFF_DBELL"  ,	   0x11f0000011800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT1_SLIST_BAOFF_DBELL"  ,	   0x11f0000011810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT2_SLIST_BAOFF_DBELL"  ,	   0x11f0000011820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT3_SLIST_BAOFF_DBELL"  ,	   0x11f0000011830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT4_SLIST_BAOFF_DBELL"  ,	   0x11f0000011840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT5_SLIST_BAOFF_DBELL"  ,	   0x11f0000011850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT6_SLIST_BAOFF_DBELL"  ,	   0x11f0000011860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT7_SLIST_BAOFF_DBELL"  ,	   0x11f0000011870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT8_SLIST_BAOFF_DBELL"  ,	   0x11f0000011880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT9_SLIST_BAOFF_DBELL"  ,	   0x11f0000011890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT10_SLIST_BAOFF_DBELL" ,	   0x11f00000118a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT11_SLIST_BAOFF_DBELL" ,	   0x11f00000118b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT12_SLIST_BAOFF_DBELL" ,	   0x11f00000118c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT13_SLIST_BAOFF_DBELL" ,	   0x11f00000118d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT14_SLIST_BAOFF_DBELL" ,	   0x11f00000118e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT15_SLIST_BAOFF_DBELL" ,	   0x11f00000118f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT16_SLIST_BAOFF_DBELL" ,	   0x11f0000011900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT17_SLIST_BAOFF_DBELL" ,	   0x11f0000011910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT18_SLIST_BAOFF_DBELL" ,	   0x11f0000011920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT19_SLIST_BAOFF_DBELL" ,	   0x11f0000011930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT20_SLIST_BAOFF_DBELL" ,	   0x11f0000011940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT21_SLIST_BAOFF_DBELL" ,	   0x11f0000011950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT22_SLIST_BAOFF_DBELL" ,	   0x11f0000011960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT23_SLIST_BAOFF_DBELL" ,	   0x11f0000011970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT24_SLIST_BAOFF_DBELL" ,	   0x11f0000011980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT25_SLIST_BAOFF_DBELL" ,	   0x11f0000011990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT26_SLIST_BAOFF_DBELL" ,	   0x11f00000119a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT27_SLIST_BAOFF_DBELL" ,	   0x11f00000119b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT28_SLIST_BAOFF_DBELL" ,	   0x11f00000119c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT29_SLIST_BAOFF_DBELL" ,	   0x11f00000119d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT30_SLIST_BAOFF_DBELL" ,	   0x11f00000119e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT31_SLIST_BAOFF_DBELL" ,	   0x11f00000119f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081},
+	{"SLI_PKT0_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT1_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT2_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT3_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT4_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT5_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT6_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT7_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT8_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT9_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT10_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT11_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT12_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT13_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT14_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT15_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT16_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT17_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT18_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT19_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT20_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT21_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT22_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT23_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT24_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT25_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT26_SLIST_FIFO_RSIZE"  ,	   0x11f0000011da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT27_SLIST_FIFO_RSIZE"  ,	   0x11f0000011db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT28_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT29_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT30_SLIST_FIFO_RSIZE"  ,	   0x11f0000011de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT31_SLIST_FIFO_RSIZE"  ,	   0x11f0000011df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082},
+	{"SLI_PKT_CNT_INT"             ,	   0x11f0000011130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1083},
+	{"SLI_PKT_CNT_INT_ENB"         ,	   0x11f0000011150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1084},
+	{"SLI_PKT_CTL"                 ,	   0x11f0000011220ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1085},
+	{"SLI_PKT_DATA_OUT_ES"         ,	   0x11f00000110b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1086},
+	{"SLI_PKT_DATA_OUT_NS"         ,	   0x11f00000110a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1087},
+	{"SLI_PKT_DATA_OUT_ROR"        ,	   0x11f0000011090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1088},
+	{"SLI_PKT_DPADDR"              ,	   0x11f0000011080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1089},
+	{"SLI_PKT_IN_BP"               ,	   0x11f0000011210ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1090},
+	{"SLI_PKT_IN_DONE0_CNTS"       ,	   0x11f0000012000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE1_CNTS"       ,	   0x11f0000012010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE2_CNTS"       ,	   0x11f0000012020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE3_CNTS"       ,	   0x11f0000012030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE4_CNTS"       ,	   0x11f0000012040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE5_CNTS"       ,	   0x11f0000012050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE6_CNTS"       ,	   0x11f0000012060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE7_CNTS"       ,	   0x11f0000012070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE8_CNTS"       ,	   0x11f0000012080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE9_CNTS"       ,	   0x11f0000012090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE10_CNTS"      ,	   0x11f00000120a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE11_CNTS"      ,	   0x11f00000120b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE12_CNTS"      ,	   0x11f00000120c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE13_CNTS"      ,	   0x11f00000120d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE14_CNTS"      ,	   0x11f00000120e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE15_CNTS"      ,	   0x11f00000120f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE16_CNTS"      ,	   0x11f0000012100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE17_CNTS"      ,	   0x11f0000012110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE18_CNTS"      ,	   0x11f0000012120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE19_CNTS"      ,	   0x11f0000012130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE20_CNTS"      ,	   0x11f0000012140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE21_CNTS"      ,	   0x11f0000012150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE22_CNTS"      ,	   0x11f0000012160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE23_CNTS"      ,	   0x11f0000012170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE24_CNTS"      ,	   0x11f0000012180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE25_CNTS"      ,	   0x11f0000012190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE26_CNTS"      ,	   0x11f00000121a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE27_CNTS"      ,	   0x11f00000121b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE28_CNTS"      ,	   0x11f00000121c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE29_CNTS"      ,	   0x11f00000121d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE30_CNTS"      ,	   0x11f00000121e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_DONE31_CNTS"      ,	   0x11f00000121f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091},
+	{"SLI_PKT_IN_INSTR_COUNTS"     ,	   0x11f0000011200ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1092},
+	{"SLI_PKT_IN_PCIE_PORT"        ,	   0x11f00000111b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1093},
+	{"SLI_PKT_INPUT_CONTROL"       ,	   0x11f0000011170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1094},
+	{"SLI_PKT_INSTR_ENB"           ,	   0x11f0000011000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1095},
+	{"SLI_PKT_INSTR_RD_SIZE"       ,	   0x11f00000111a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1096},
+	{"SLI_PKT_INSTR_SIZE"          ,	   0x11f0000011020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1097},
+	{"SLI_PKT_INT_LEVELS"          ,	   0x11f0000011120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1098},
+	{"SLI_PKT_IPTR"                ,	   0x11f0000011070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1099},
+	{"SLI_PKT_OUT_BMODE"           ,	   0x11f00000110d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1100},
+	{"SLI_PKT_OUT_ENB"             ,	   0x11f0000011010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1101},
+	{"SLI_PKT_OUTPUT_WMARK"        ,	   0x11f0000011180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1102},
+	{"SLI_PKT_PCIE_PORT"           ,	   0x11f00000110e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1103},
+	{"SLI_PKT_PORT_IN_RST"         ,	   0x11f00000111f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1104},
+	{"SLI_PKT_SLIST_ES"            ,	   0x11f0000011050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1105},
+	{"SLI_PKT_SLIST_NS"            ,	   0x11f0000011040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1106},
+	{"SLI_PKT_SLIST_ROR"           ,	   0x11f0000011030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1107},
+	{"SLI_PKT_TIME_INT"            ,	   0x11f0000011140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1108},
+	{"SLI_PKT_TIME_INT_ENB"        ,	   0x11f0000011160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1109},
+	{"SLI_S2M_PORT0_CTL"           ,	   0x11f0000013d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1110},
+	{"SLI_S2M_PORT1_CTL"           ,	   0x11f0000013d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1110},
+	{"SLI_SCRATCH_1"               ,	   0x11f00000103c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1111},
+	{"SLI_SCRATCH_2"               ,	   0x11f00000103d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1112},
+	{"SLI_STATE1"                  ,	   0x11f0000010620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1113},
+	{"SLI_STATE2"                  ,	   0x11f0000010630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1114},
+	{"SLI_STATE3"                  ,	   0x11f0000010640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1115},
+	{"SLI_WIN_RD_ADDR"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1116},
+	{"SLI_WIN_RD_DATA"             ,	              0x40ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1117},
+	{"SLI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1118},
+	{"SLI_WIN_WR_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1119},
+	{"SLI_WIN_WR_MASK"             ,	              0x30ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	1120},
+	{"SLI_WINDOW_CTL"              ,	   0x11f00000102e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1121},
+	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1122},
+	{"SMI1_CLK"                    ,	   0x1180000001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1122},
+	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1123},
+	{"SMI1_CMD"                    ,	   0x1180000001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1123},
+	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1124},
+	{"SMI1_EN"                     ,	   0x1180000001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1124},
+	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1125},
+	{"SMI1_RD_DAT"                 ,	   0x1180000001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1125},
+	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1126},
+	{"SMI1_WR_DAT"                 ,	   0x1180000001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1126},
+	{"SMI_DRV_CTL"                 ,	   0x1180000001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1127},
+	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1128},
+	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1129},
+	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1130},
+	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1131},
+	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1132},
+	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1133},
+	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1134},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1135},
+	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1136},
+	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1137},
+	{"TRA0_BIST_STATUS"            ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1138},
+	{"TRA0_CTL"                    ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1139},
+	{"TRA0_CYCLES_SINCE"           ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1140},
+	{"TRA0_CYCLES_SINCE1"          ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1141},
+	{"TRA0_FILT_ADR_ADR"           ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1142},
+	{"TRA0_FILT_ADR_MSK"           ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1143},
+	{"TRA0_FILT_CMD"               ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1144},
+	{"TRA0_FILT_DID"               ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1145},
+	{"TRA0_FILT_SID"               ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1146},
+	{"TRA0_INT_STATUS"             ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1147},
+	{"TRA0_READ_DAT"               ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1148},
+	{"TRA0_READ_DAT_HI"            ,	   0x11800a8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1149},
+	{"TRA0_TRIG0_ADR_ADR"          ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1150},
+	{"TRA0_TRIG0_ADR_MSK"          ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1151},
+	{"TRA0_TRIG0_CMD"              ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1152},
+	{"TRA0_TRIG0_DID"              ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1153},
+	{"TRA0_TRIG0_SID"              ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1154},
+	{"TRA0_TRIG1_ADR_ADR"          ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1155},
+	{"TRA0_TRIG1_ADR_MSK"          ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1156},
+	{"TRA0_TRIG1_CMD"              ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1157},
+	{"TRA0_TRIG1_DID"              ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1158},
+	{"TRA0_TRIG1_SID"              ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1159},
+	{"UAHC0_EHCI_ASYNCLISTADDR"    ,	   0x16f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1160},
+	{"UAHC0_EHCI_CONFIGFLAG"       ,	   0x16f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1161},
+	{"UAHC0_EHCI_CTRLDSSEGMENT"    ,	   0x16f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1162},
+	{"UAHC0_EHCI_FRINDEX"          ,	   0x16f000000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1163},
+	{"UAHC0_EHCI_HCCAPBASE"        ,	   0x16f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1164},
+	{"UAHC0_EHCI_HCCPARAMS"        ,	   0x16f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1165},
+	{"UAHC0_EHCI_HCSPARAMS"        ,	   0x16f0000000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1166},
+	{"UAHC0_EHCI_INSNREG00"        ,	   0x16f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1167},
+	{"UAHC0_EHCI_INSNREG03"        ,	   0x16f000000009cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1168},
+	{"UAHC0_EHCI_INSNREG04"        ,	   0x16f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1169},
+	{"UAHC0_EHCI_INSNREG06"        ,	   0x16f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1170},
+	{"UAHC0_EHCI_INSNREG07"        ,	   0x16f00000000ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	1171},
+	{"UAHC0_EHCI_PERIODICLISTBASE" ,	   0x16f0000000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1172},
+	{"UAHC0_EHCI_PORTSC001"        ,	   0x16f0000000054ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1173},
+	{"UAHC0_EHCI_PORTSC002"        ,	   0x16f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1173},
+	{"UAHC0_EHCI_USBCMD"           ,	   0x16f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1174},
+	{"UAHC0_EHCI_USBINTR"          ,	   0x16f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1175},
+	{"UAHC0_EHCI_USBSTS"           ,	   0x16f0000000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1176},
+	{"UAHC0_OHCI0_HCBULKCURRENTED" ,	   0x16f000000042cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1177},
+	{"UAHC0_OHCI0_HCBULKHEADED"    ,	   0x16f0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1178},
+	{"UAHC0_OHCI0_HCCOMMANDSTATUS" ,	   0x16f0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1179},
+	{"UAHC0_OHCI0_HCCONTROL"       ,	   0x16f0000000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1180},
+	{"UAHC0_OHCI0_HCCONTROLCURRENTED",	   0x16f0000000424ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1181},
+	{"UAHC0_OHCI0_HCCONTROLHEADED" ,	   0x16f0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1182},
+	{"UAHC0_OHCI0_HCDONEHEAD"      ,	   0x16f0000000430ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1183},
+	{"UAHC0_OHCI0_HCFMINTERVAL"    ,	   0x16f0000000434ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1184},
+	{"UAHC0_OHCI0_HCFMNUMBER"      ,	   0x16f000000043cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1185},
+	{"UAHC0_OHCI0_HCFMREMAINING"   ,	   0x16f0000000438ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1186},
+	{"UAHC0_OHCI0_HCHCCA"          ,	   0x16f0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1187},
+	{"UAHC0_OHCI0_HCINTERRUPTDISABLE",	   0x16f0000000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1188},
+	{"UAHC0_OHCI0_HCINTERRUPTENABLE",	   0x16f0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1189},
+	{"UAHC0_OHCI0_HCINTERRUPTSTATUS",	   0x16f000000040cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1190},
+	{"UAHC0_OHCI0_HCLSTHRESHOLD"   ,	   0x16f0000000444ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1191},
+	{"UAHC0_OHCI0_HCPERIODCURRENTED",	   0x16f000000041cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1192},
+	{"UAHC0_OHCI0_HCPERIODICSTART" ,	   0x16f0000000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1193},
+	{"UAHC0_OHCI0_HCREVISION"      ,	   0x16f0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1194},
+	{"UAHC0_OHCI0_HCRHDESCRIPTORA" ,	   0x16f0000000448ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1195},
+	{"UAHC0_OHCI0_HCRHDESCRIPTORB" ,	   0x16f000000044cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1196},
+	{"UAHC0_OHCI0_HCRHPORTSTATUS001",	   0x16f0000000454ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1197},
+	{"UAHC0_OHCI0_HCRHPORTSTATUS002",	   0x16f0000000458ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1197},
+	{"UAHC0_OHCI0_HCRHSTATUS"      ,	   0x16f0000000450ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1198},
+	{"UAHC0_OHCI0_INSNREG06"       ,	   0x16f0000000498ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1199},
+	{"UAHC0_OHCI0_INSNREG07"       ,	   0x16f000000049cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1200},
+	{"UCTL0_BIST_STATUS"           ,	   0x118006f0000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1201},
+	{"UCTL0_CLK_RST_CTL"           ,	   0x118006f000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1202},
+	{"UCTL0_EHCI_CTL"              ,	   0x118006f000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1203},
+	{"UCTL0_EHCI_FLA"              ,	   0x118006f0000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1204},
+	{"UCTL0_ERTO_CTL"              ,	   0x118006f000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1205},
+	{"UCTL0_IF_ENA"                ,	   0x118006f000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1206},
+	{"UCTL0_INT_ENA"               ,	   0x118006f000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1207},
+	{"UCTL0_INT_REG"               ,	   0x118006f000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1208},
+	{"UCTL0_OHCI_CTL"              ,	   0x118006f000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1209},
+	{"UCTL0_ORTO_CTL"              ,	   0x118006f000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1210},
+	{"UCTL0_PPAF_WM"               ,	   0x118006f000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1211},
+	{"UCTL0_UPHY_CTL_STATUS"       ,	   0x118006f000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1212},
+	{"UCTL0_UPHY_PORT000_CTL_STATUS",	   0x118006f000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1213},
+	{"UCTL0_UPHY_PORT001_CTL_STATUS",	   0x118006f000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1213},
+	{NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cnf71xx[] = {
+	/* name                        ,	bit,	width,	csr,	type,	rst un,	typ un,	reset,	typical */
+	{"BIST"                        ,	0,	6,	0,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	0,	"RAZ",	1,	1,	0,	0},
+	{"MIO"                         ,	0,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX0"                        ,	1,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	3,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	4,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	5,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_8"                ,	6,	3,	1,	"RAZ",	1,	1,	0,	0},
+	{"IPD"                         ,	9,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	10,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	11,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	12,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	13,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	14,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	1,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	16,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	17,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	1,	"RAZ",	1,	1,	0,	0},
+	{"PIP"                         ,	20,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_21"              ,	21,	1,	1,	"RAZ",	1,	1,	0,	0},
+	{"ASXPCS0"                     ,	22,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_24"              ,	23,	2,	1,	"RAZ",	1,	1,	0,	0},
+	{"PEM0"                        ,	25,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	26,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_29"              ,	27,	3,	1,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	30,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_40"              ,	31,	10,	1,	"RAZ",	1,	1,	0,	0},
+	{"DPI"                         ,	41,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	42,	1,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	1,	"RAZ",	1,	1,	0,	0},
+	{"DINT"                        ,	0,	4,	2,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	2,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	3,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	3,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	3,	"RAZ",	1,	1,	0,	0},
+	{"EOI"                         ,	12,	1,	3,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENDOR"                       ,	13,	2,	3,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	3,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	4,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	4,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	4,	"RAZ",	1,	1,	0,	0},
+	{"EOI"                         ,	12,	1,	4,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENDOR"                       ,	13,	2,	4,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	4,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	5,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	5,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	5,	"RAZ",	1,	1,	0,	0},
+	{"EOI"                         ,	12,	1,	5,	"R/W1",	0,	0,	0ull,	0ull},
+	{"ENDOR"                       ,	13,	2,	5,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	5,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	6,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	6,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	6,	"RAZ",	1,	1,	0,	0},
+	{"EOI"                         ,	12,	1,	6,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENDOR"                       ,	13,	2,	6,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	6,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	7,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	7,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	7,	"RAZ",	1,	1,	0,	0},
+	{"EOI"                         ,	12,	1,	7,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENDOR"                       ,	13,	2,	7,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	7,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	8,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	8,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	8,	"RAZ",	1,	1,	0,	0},
+	{"EOI"                         ,	12,	1,	8,	"R/W1",	0,	0,	0ull,	0ull},
+	{"ENDOR"                       ,	13,	2,	8,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	8,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	9,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	9,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	9,	"RAZ",	1,	1,	0,	0},
+	{"EOI"                         ,	12,	1,	9,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENDOR"                       ,	13,	2,	9,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	9,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	10,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	10,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	10,	"RAZ",	1,	1,	0,	0},
+	{"EOI"                         ,	12,	1,	10,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENDOR"                       ,	13,	2,	10,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	10,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	11,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	11,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	11,	"RAZ",	1,	1,	0,	0},
+	{"EOI"                         ,	12,	1,	11,	"R/W1",	0,	0,	0ull,	0ull},
+	{"ENDOR"                       ,	13,	2,	11,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	11,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	12,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	12,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	12,	"RAZ",	1,	1,	0,	0},
+	{"EOI"                         ,	12,	1,	12,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENDOR"                       ,	13,	2,	12,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	12,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	13,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	13,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	13,	"RAZ",	1,	1,	0,	0},
+	{"EOI"                         ,	12,	1,	13,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENDOR"                       ,	13,	2,	13,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	13,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	14,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	14,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	14,	"RAZ",	1,	1,	0,	0},
+	{"EOI"                         ,	12,	1,	14,	"R/W1",	0,	0,	0ull,	0ull},
+	{"ENDOR"                       ,	13,	2,	14,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	14,	"RAZ",	1,	1,	0,	0},
+	{"FUSE"                        ,	0,	4,	15,	"RO",	1,	1,	0,	0},
+	{"RESERVED_4_63"               ,	4,	60,	15,	"RAZ",	1,	1,	0,	0},
+	{"GSTOP"                       ,	0,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	16,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	17,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	17,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	17,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	52,	4,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	17,	"RAZ",	1,	1,	0,	0},
+	{"BOOTDMA"                     ,	63,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	18,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	18,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	18,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	52,	4,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	18,	"RAZ",	1,	1,	0,	0},
+	{"BOOTDMA"                     ,	63,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	19,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	19,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	19,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	52,	4,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	19,	"RAZ",	1,	1,	0,	0},
+	{"BOOTDMA"                     ,	63,	1,	19,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_18"               ,	4,	15,	20,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	19,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_28"              ,	28,	1,	20,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	29,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_32"              ,	32,	1,	20,	"RAZ",	1,	1,	0,	0},
+	{"USB"                         ,	33,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	20,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	40,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_46"              ,	41,	6,	20,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	47,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	20,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	20,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	20,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_18"               ,	4,	15,	21,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	19,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_28"              ,	28,	1,	21,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	29,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_32"              ,	32,	1,	21,	"RAZ",	1,	1,	0,	0},
+	{"USB"                         ,	33,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	21,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	40,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_46"              ,	41,	6,	21,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	47,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	21,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	21,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_18"               ,	4,	15,	22,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	19,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_28"              ,	28,	1,	22,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	29,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_32"              ,	32,	1,	22,	"RAZ",	1,	1,	0,	0},
+	{"USB"                         ,	33,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	22,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	40,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_46"              ,	41,	6,	22,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	47,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	22,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	22,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	22,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	23,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	23,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	23,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	52,	4,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	23,	"RAZ",	1,	1,	0,	0},
+	{"BOOTDMA"                     ,	63,	1,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	24,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	24,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	24,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	52,	4,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	24,	"RAZ",	1,	1,	0,	0},
+	{"BOOTDMA"                     ,	63,	1,	24,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	25,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	25,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	25,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	52,	4,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	25,	"RAZ",	1,	1,	0,	0},
+	{"BOOTDMA"                     ,	63,	1,	25,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_18"               ,	4,	15,	26,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	19,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_28"              ,	28,	1,	26,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	29,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_32"              ,	32,	1,	26,	"RAZ",	1,	1,	0,	0},
+	{"USB"                         ,	33,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	26,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	40,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_46"              ,	41,	6,	26,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	47,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	26,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	26,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_18"               ,	4,	15,	27,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	19,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_28"              ,	28,	1,	27,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	29,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_32"              ,	32,	1,	27,	"RAZ",	1,	1,	0,	0},
+	{"USB"                         ,	33,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	27,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	40,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_46"              ,	41,	6,	27,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	47,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	27,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	27,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	27,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_18"               ,	4,	15,	28,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	19,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_28"              ,	28,	1,	28,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	29,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_32"              ,	32,	1,	28,	"RAZ",	1,	1,	0,	0},
+	{"USB"                         ,	33,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	28,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	40,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_46"              ,	41,	6,	28,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	47,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	28,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	28,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	28,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	29,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	29,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	29,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	29,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SUM2"                        ,	51,	1,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	29,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	29,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	29,	"RAZ",	1,	1,	0,	0},
+	{"BOOTDMA"                     ,	63,	1,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	30,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	30,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	30,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	30,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SUM2"                        ,	51,	1,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	30,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	30,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	30,	"RO",	1,	1,	0,	0},
+	{"BOOTDMA"                     ,	63,	1,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	31,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SUM2"                        ,	51,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	31,	"RAZ",	1,	1,	0,	0},
+	{"BOOTDMA"                     ,	63,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	4,	32,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	32,	"RAZ",	1,	1,	0,	0},
+	{"IRQ"                         ,	8,	2,	32,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	32,	"RAZ",	1,	1,	0,	0},
+	{"SEL"                         ,	16,	3,	32,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_19_63"              ,	19,	45,	32,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	4,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_18"               ,	4,	15,	33,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	19,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_28"              ,	28,	1,	33,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	29,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_32"              ,	32,	1,	33,	"RAZ",	1,	1,	0,	0},
+	{"USB"                         ,	33,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_46"              ,	37,	10,	33,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	47,	1,	33,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	33,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	33,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"BITS"                        ,	0,	32,	34,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	34,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	35,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	35,	"RAZ",	1,	1,	0,	0},
+	{"NMI"                         ,	0,	4,	36,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	36,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	2,	37,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	37,	"RAZ",	1,	1,	0,	0},
+	{"PPDBG"                       ,	0,	4,	38,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	38,	"RAZ",	1,	1,	0,	0},
+	{"POKE"                        ,	0,	64,	39,	"RAZ",	1,	1,	0,	0},
+	{"RST0"                        ,	0,	1,	40,	"R/W",	1,	1,	0,	0},
+	{"RST"                         ,	1,	3,	40,	"R/W",	0,	0,	7ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	40,	"RAZ",	1,	1,	0,	0},
+	{"LANE_EN"                     ,	0,	4,	41,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	41,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	41,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	41,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	41,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	41,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	41,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_39"              ,	32,	8,	41,	"RAZ",	1,	1,	0,	0},
+	{"G2MARGIN"                    ,	40,	5,	41,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	41,	"RAZ",	1,	1,	0,	0},
+	{"G2DEEMPH"                    ,	48,	5,	41,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_53_62"              ,	53,	10,	41,	"RAZ",	1,	1,	0,	0},
+	{"G2BYPASS"                    ,	63,	1,	41,	"R/W",	0,	1,	0ull,	0},
+	{"LANE_EN"                     ,	0,	4,	42,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	42,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	42,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	42,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	42,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	42,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	42,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_39"              ,	32,	8,	42,	"RAZ",	1,	1,	0,	0},
+	{"G2MARGIN"                    ,	40,	5,	42,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	42,	"RAZ",	1,	1,	0,	0},
+	{"G2DEEMPH"                    ,	48,	5,	42,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_53_62"              ,	53,	10,	42,	"RAZ",	1,	1,	0,	0},
+	{"G2BYPASS"                    ,	63,	1,	42,	"R/W",	0,	1,	0ull,	0},
+	{"LANE_EN"                     ,	0,	4,	43,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	43,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	43,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	43,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	43,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	43,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	43,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	43,	"RAZ",	1,	1,	0,	0},
+	{"BYPASS"                      ,	0,	3,	44,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	44,	"RAZ",	1,	1,	0,	0},
+	{"MUX_SEL"                     ,	4,	2,	44,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	44,	"RAZ",	1,	1,	0,	0},
+	{"CLK_DIV"                     ,	8,	3,	44,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	44,	"RAZ",	1,	1,	0,	0},
+	{"SHFT_REG"                    ,	0,	32,	45,	"R/W",	0,	1,	0ull,	0},
+	{"SHFT_CNT"                    ,	32,	5,	45,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_37_39"              ,	37,	3,	45,	"RAZ",	1,	1,	0,	0},
+	{"SELECT"                      ,	40,	3,	45,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_43_60"              ,	43,	18,	45,	"RAZ",	1,	1,	0,	0},
+	{"UPDATE"                      ,	61,	1,	45,	"R/W",	0,	1,	0ull,	0},
+	{"SHIFT"                       ,	62,	1,	45,	"R/W",	0,	1,	0ull,	0},
+	{"CAPTURE"                     ,	63,	1,	45,	"R/W",	0,	1,	0ull,	0},
+	{"SOFT_BIST"                   ,	0,	1,	46,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	46,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	47,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	47,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	48,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	48,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST"                    ,	0,	1,	49,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	49,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	4,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_18"               ,	4,	15,	50,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	19,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_28"              ,	28,	1,	50,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	29,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_32"              ,	32,	1,	50,	"RAZ",	1,	1,	0,	0},
+	{"USB"                         ,	33,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	50,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	40,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_46"              ,	41,	6,	50,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	47,	1,	50,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	50,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	50,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_18"               ,	4,	15,	51,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	19,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_28"              ,	28,	1,	51,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	29,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_32"              ,	32,	1,	51,	"RAZ",	1,	1,	0,	0},
+	{"USB"                         ,	33,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	51,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	40,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_46"              ,	41,	6,	51,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	47,	1,	51,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	51,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	51,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	51,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_18"               ,	4,	15,	52,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	19,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_28"              ,	28,	1,	52,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	29,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_32"              ,	32,	1,	52,	"RAZ",	1,	1,	0,	0},
+	{"USB"                         ,	33,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	52,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	40,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_46"              ,	41,	6,	52,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	47,	1,	52,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	52,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	52,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_18"               ,	4,	15,	53,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	19,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_28"              ,	28,	1,	53,	"RAZ",	1,	1,	0,	0},
+	{"TIM"                         ,	29,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_32"              ,	32,	1,	53,	"RAZ",	1,	1,	0,	0},
+	{"USB"                         ,	33,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	53,	"RAZ",	1,	1,	0,	0},
+	{"DPI_DMA"                     ,	40,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_46"              ,	41,	6,	53,	"RAZ",	1,	1,	0,	0},
+	{"PTP"                         ,	47,	1,	53,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_51"              ,	50,	2,	53,	"RAZ",	1,	1,	0,	0},
+	{"LMC0"                        ,	52,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_62"              ,	53,	10,	53,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	54,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	54,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	54,	"RAZ",	1,	1,	0,	0},
+	{"EOI"                         ,	12,	1,	54,	"RO",	0,	0,	0ull,	0ull},
+	{"ENDOR"                       ,	13,	2,	54,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	54,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	55,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	55,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	55,	"RAZ",	1,	1,	0,	0},
+	{"EOI"                         ,	12,	1,	55,	"RO",	0,	0,	0ull,	0ull},
+	{"ENDOR"                       ,	13,	2,	55,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	55,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	56,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	56,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	56,	"RAZ",	1,	1,	0,	0},
+	{"EOI"                         ,	12,	1,	56,	"RO",	0,	0,	0ull,	0ull},
+	{"ENDOR"                       ,	13,	2,	56,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	56,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	57,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	4,	6,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	57,	"RAZ",	1,	1,	0,	0},
+	{"EOI"                         ,	12,	1,	57,	"RO",	0,	0,	0ull,	0ull},
+	{"ENDOR"                       ,	13,	2,	57,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	57,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	36,	58,	"R/W",	0,	0,	0ull,	0ull},
+	{"ONE_SHOT"                    ,	36,	1,	58,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	58,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	59,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	60,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	2,	2,	60,	"RO",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	4,	16,	60,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	20,	24,	60,	"RO",	0,	0,	0ull,	0ull},
+	{"DSTOP"                       ,	44,	1,	60,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSTOPEN"                     ,	45,	1,	60,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	60,	"RAZ",	1,	1,	0,	0},
+	{"BIST"                        ,	0,	47,	61,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	61,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	62,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	62,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	63,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	63,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	63,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	64,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	64,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	6,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	65,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_6"                ,	0,	7,	66,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	7,	29,	66,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	66,	"RAZ",	1,	1,	0,	0},
+	{"IDLE"                        ,	40,	1,	66,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_41_47"              ,	41,	7,	66,	"RAZ",	1,	1,	0,	0},
+	{"CSIZE"                       ,	48,	14,	66,	"R/W",	0,	1,	64ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	66,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	3,	67,	"R/W",	0,	0,	6ull,	6ull},
+	{"RESERVED_3_63"               ,	3,	61,	67,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	68,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	68,	"RAZ",	1,	1,	0,	0},
+	{"STATE"                       ,	0,	64,	69,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	0,	64,	70,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_13"               ,	0,	14,	71,	"RAZ",	1,	1,	0,	0},
+	{"O_MODE"                      ,	14,	1,	71,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ES"                        ,	15,	2,	71,	"R/W",	0,	1,	0ull,	0},
+	{"O_NS"                        ,	17,	1,	71,	"R/W",	0,	1,	0ull,	0},
+	{"O_RO"                        ,	18,	1,	71,	"R/W",	0,	1,	0ull,	0},
+	{"O_ADD1"                      ,	19,	1,	71,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA_QUE"                     ,	20,	3,	71,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_ICHK"                    ,	23,	9,	71,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_DENB"                    ,	32,	1,	71,	"R/W",	0,	0,	0ull,	1ull},
+	{"B0_LEND"                     ,	33,	1,	71,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_47"              ,	34,	14,	71,	"RAZ",	1,	1,	0,	0},
+	{"DMA_ENB"                     ,	48,	6,	71,	"R/W",	0,	0,	0ull,	63ull},
+	{"RESERVED_54_55"              ,	54,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"PKT_EN"                      ,	56,	1,	71,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_HP"                      ,	57,	1,	71,	"RO",	0,	0,	0ull,	0ull},
+	{"COMMIT_MODE"                 ,	58,	1,	71,	"R/W",	0,	0,	0ull,	1ull},
+	{"FFP_DIS"                     ,	59,	1,	71,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_EN1"                     ,	60,	1,	71,	"R/W",	0,	1,	0ull,	0},
+	{"DICI_MODE"                   ,	61,	1,	71,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"QEN"                         ,	0,	8,	72,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	72,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	73,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	73,	"RAZ",	1,	1,	0,	0},
+	{"BLKS"                        ,	0,	4,	74,	"R/W",	0,	1,	2ull,	0},
+	{"BASE"                        ,	4,	5,	74,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_31"               ,	9,	23,	74,	"RAZ",	1,	1,	0,	0},
+	{"COMPBLKS"                    ,	32,	5,	74,	"RO",	1,	1,	0,	0},
+	{"RESERVED_37_63"              ,	37,	27,	74,	"RAZ",	1,	1,	0,	0},
+	{"RSL"                         ,	0,	1,	75,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NCB"                         ,	1,	1,	75,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	75,	"RAZ",	1,	1,	0,	0},
+	{"FFP"                         ,	4,	4,	75,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	75,	"RAZ",	1,	1,	0,	0},
+	{"NDERR"                       ,	0,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFOVR"                       ,	1,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMADBO"                      ,	8,	8,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADADR"                  ,	16,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADLEN"                  ,	17,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_OVRFLW"                  ,	18,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_UNDFLW"                  ,	19,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_ANULL"                   ,	20,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_INULL"                   ,	21,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADFIL"                  ,	22,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	76,	"R/W",	1,	1,	0,	0},
+	{"SPRT0_RST"                   ,	24,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_RST"                   ,	25,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT2_RST"                   ,	26,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT3_RST"                   ,	27,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	76,	"RAZ",	1,	1,	0,	0},
+	{"NDERR"                       ,	0,	1,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFOVR"                       ,	1,	1,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	77,	"RAZ",	1,	1,	0,	0},
+	{"DMADBO"                      ,	8,	8,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADADR"                  ,	16,	1,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADLEN"                  ,	17,	1,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_OVRFLW"                  ,	18,	1,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_UNDFLW"                  ,	19,	1,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_ANULL"                   ,	20,	1,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_INULL"                   ,	21,	1,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADFIL"                  ,	22,	1,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	77,	"RAZ",	1,	1,	0,	0},
+	{"SPRT0_RST"                   ,	24,	1,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT1_RST"                   ,	25,	1,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT2_RST"                   ,	26,	1,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT3_RST"                   ,	27,	1,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	77,	"RAZ",	1,	1,	0,	0},
+	{"MOLR"                        ,	0,	6,	78,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	78,	"RAZ",	1,	1,	0,	0},
+	{"SINFO"                       ,	0,	6,	79,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	79,	"RAZ",	1,	1,	0,	0},
+	{"IINFO"                       ,	8,	6,	79,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	79,	"RAZ",	1,	1,	0,	0},
+	{"PKTERR"                      ,	0,	1,	80,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	80,	"RAZ",	1,	1,	0,	0},
+	{"QERR"                        ,	0,	8,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	81,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	82,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	82,	"RAZ",	1,	1,	0,	0},
+	{"QERR"                        ,	0,	8,	83,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	83,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	84,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	84,	"RAZ",	1,	1,	0,	0},
+	{"EN_RSP"                      ,	0,	8,	85,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	85,	"RAZ",	1,	1,	0,	0},
+	{"EN_RST"                      ,	16,	8,	85,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	85,	"RAZ",	1,	1,	0,	0},
+	{"QEN"                         ,	0,	8,	86,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	86,	"RAZ",	1,	1,	0,	0},
+	{"MRRS"                        ,	0,	2,	87,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	87,	"RAZ",	1,	1,	0,	0},
+	{"MRRS_LIM"                    ,	3,	1,	87,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPS"                         ,	4,	1,	87,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	87,	"RAZ",	1,	1,	0,	0},
+	{"MPS_LIM"                     ,	7,	1,	87,	"R/W",	0,	0,	0ull,	0ull},
+	{"MOLR"                        ,	8,	6,	87,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	87,	"RAZ",	1,	1,	0,	0},
+	{"RD_MODE"                     ,	16,	1,	87,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	87,	"RAZ",	1,	1,	0,	0},
+	{"QLM_CFG"                     ,	20,	4,	87,	"RO",	1,	1,	0,	0},
+	{"HALT"                        ,	24,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	87,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	88,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	61,	88,	"RO",	0,	1,	0ull,	0},
+	{"REQQ"                        ,	0,	3,	89,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	89,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	4,	1,	89,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	89,	"RAZ",	1,	1,	0,	0},
+	{"LOCK"                        ,	8,	1,	89,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	89,	"RAZ",	1,	1,	0,	0},
+	{"AUTO_GATE"                   ,	0,	1,	90,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"CH0_AXI_RSPCODE"             ,	0,	2,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"CH1_AXI_RSPCODE"             ,	2,	2,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"CH2_AXI_RSPCODE"             ,	4,	2,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"CH3_AXI_RSPCODE"             ,	6,	2,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"CH4_AXI_RSPCODE"             ,	8,	2,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"CH5_AXI_RSPCODE"             ,	10,	2,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"CH6_AXI_RSPCODE"             ,	12,	2,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"CH7_AXI_RSPCODE"             ,	14,	2,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"ARLOCK"                      ,	0,	2,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"AWLOCK"                      ,	8,	2,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_23"              ,	10,	14,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"AWCOBUF"                     ,	24,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"AXI_ERR_INT"                 ,	0,	1,	93,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_31"               ,	1,	31,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"HI_ADDR"                     ,	0,	8,	94,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_31"               ,	8,	24,	94,	"RO",	0,	0,	0ull,	0ull},
+	{"LO_ADDR"                     ,	0,	32,	95,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	96,	"RO",	0,	0,	0ull,	0ull},
+	{"MAX_BSTLEN"                  ,	4,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"BST_BOUND"                   ,	5,	1,	96,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	96,	"RO",	0,	0,	0ull,	0ull},
+	{"AWCACHE"                     ,	8,	4,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"AWCACHE_LBM"                 ,	12,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	96,	"RO",	0,	0,	0ull,	0ull},
+	{"HMM_OFS"                     ,	16,	2,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_23"              ,	18,	6,	96,	"RO",	0,	0,	0ull,	0ull},
+	{"ENDIAN"                      ,	24,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	96,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA_SIZE"                    ,	0,	18,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	97,	"RO",	0,	0,	0ull,	0ull},
+	{"WDMA_FIX_PRTY"               ,	0,	4,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDMA_RR_PRTY"                ,	4,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDMA_RR_PRTY"                ,	5,	1,	98,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	98,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA_CH_RESET"                ,	0,	8,	99,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_31"               ,	8,	24,	99,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA_CH_DONE"                 ,	0,	8,	100,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_31"               ,	8,	24,	100,	"RO",	0,	0,	0ull,	0ull},
+	{"DMADONE_INTR_DIS"            ,	0,	16,	101,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXIERR_INTR_DIS"             ,	16,	1,	101,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"DMADONE_INTR_ENB"            ,	0,	16,	102,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXIERR_INTR_ENB"             ,	16,	1,	102,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA_CH_STT"                  ,	0,	14,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"NON_DMAWRCH_STT"             ,	14,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"NON_DMARDCH_STT"             ,	15,	1,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	103,	"RO",	0,	0,	0ull,	0ull},
+	{"ENAB"                        ,	0,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	104,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENAB"                        ,	0,	1,	105,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	105,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	0,	9,	106,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	106,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	0,	9,	107,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	107,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GRPIDX"                      ,	0,	6,	108,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	108,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GRPIDX"                      ,	0,	6,	109,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	109,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ULFE"                        ,	0,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACH"                        ,	1,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDMP"                      ,	2,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	3,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_DONE"                  ,	4,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_RDDONE"                ,	5,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"VDEC"                        ,	6,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC"                      ,	7,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"H3GENC"                      ,	8,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR"                    ,	9,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RFSPI"                       ,	10,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_BERR"                    ,	11,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"TTI_TIMER"                   ,	12,	8,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_FFTHRESH"              ,	20,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_FFFLAG"                ,	21,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RXD_FFTHRESH"             ,	22,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RXD_FFFLAG"               ,	23,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_STFRAME"               ,	24,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_STRX"                  ,	25,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI0"                     ,	26,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI1"                     ,	27,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI2"                     ,	28,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI3"                     ,	29,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_SPISKIP"               ,	30,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_PPSSYNC"               ,	31,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"ULFE"                        ,	0,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACH"                        ,	1,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDMP"                      ,	2,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	3,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_DONE"                  ,	4,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_RDDONE"                ,	5,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"VDEC"                        ,	6,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC"                      ,	7,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"H3GENC"                      ,	8,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR"                    ,	9,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RFSPI"                       ,	10,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_BERR"                    ,	11,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"TTI_TIMER"                   ,	12,	8,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_FFTHRESH"              ,	20,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_FFFLAG"                ,	21,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RXD_FFTHRESH"             ,	22,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RXD_FFFLAG"               ,	23,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_STFRAME"               ,	24,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_STRX"                  ,	25,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI0"                     ,	26,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI1"                     ,	27,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI2"                     ,	28,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI3"                     ,	29,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_SPISKIP"               ,	30,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_PPSSYNC"               ,	31,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"ULFE"                        ,	0,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACH"                        ,	1,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDMP"                      ,	2,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	3,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_DONE"                  ,	4,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_RDDONE"                ,	5,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"VDEC"                        ,	6,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC"                      ,	7,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"H3GENC"                      ,	8,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR"                    ,	9,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RFSPI"                       ,	10,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_BERR"                    ,	11,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"TTI_TIMER"                   ,	12,	8,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_FFTHRESH"              ,	20,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_FFFLAG"                ,	21,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RXD_FFTHRESH"             ,	22,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RXD_FFFLAG"               ,	23,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_STFRAME"               ,	24,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_STRX"                  ,	25,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI0"                     ,	26,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI1"                     ,	27,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI2"                     ,	28,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI3"                     ,	29,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_SPISKIP"               ,	30,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_PPSSYNC"               ,	31,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"ULFE"                        ,	0,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACH"                        ,	1,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDMP"                      ,	2,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	3,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_DONE"                  ,	4,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_RDDONE"                ,	5,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"VDEC"                        ,	6,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC"                      ,	7,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"H3GENC"                      ,	8,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR"                    ,	9,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RFSPI"                       ,	10,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_BERR"                    ,	11,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"TTI_TIMER"                   ,	12,	8,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_FFTHRESH"              ,	20,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_FFFLAG"                ,	21,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RXD_FFTHRESH"             ,	22,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RXD_FFFLAG"               ,	23,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_STFRAME"               ,	24,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_STRX"                  ,	25,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI0"                     ,	26,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI1"                     ,	27,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI2"                     ,	28,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI3"                     ,	29,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_SPISKIP"               ,	30,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_PPSSYNC"               ,	31,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"ULFE"                        ,	0,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACH"                        ,	1,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDMP"                      ,	2,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	3,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_DONE"                  ,	4,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_RDDONE"                ,	5,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"VDEC"                        ,	6,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC"                      ,	7,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"H3GENC"                      ,	8,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR"                    ,	9,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RFSPI"                       ,	10,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_BERR"                    ,	11,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"TTI_TIMER"                   ,	12,	8,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_FFTHRESH"              ,	20,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_FFFLAG"                ,	21,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RXD_FFTHRESH"             ,	22,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RXD_FFFLAG"               ,	23,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_STFRAME"               ,	24,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_STRX"                  ,	25,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI0"                     ,	26,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI1"                     ,	27,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI2"                     ,	28,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_SPI3"                     ,	29,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_SPISKIP"               ,	30,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RF_RX_PPSSYNC"               ,	31,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPIDX"                      ,	0,	6,	115,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	115,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GRPIDX"                      ,	0,	6,	116,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	116,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ULFE"                        ,	0,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF"                    ,	1,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	2,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	3,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	4,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	5,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	6,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	7,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	8,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	9,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_RM"                 ,	10,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	11,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	12,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	13,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	14,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	15,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	16,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	17,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_TX"                      ,	18,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX0"                     ,	19,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1"                     ,	20,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1_HARQ"                ,	21,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_0"                   ,	22,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_1"                   ,	23,	1,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	117,	"RAZ",	1,	1,	0,	0},
+	{"ULFE"                        ,	0,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF"                    ,	1,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	2,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	3,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	4,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	5,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	6,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	7,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	8,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	9,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_RM"                 ,	10,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	11,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	12,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	13,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	14,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	15,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	16,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	17,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_TX"                      ,	18,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX0"                     ,	19,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1"                     ,	20,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1_HARQ"                ,	21,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_0"                   ,	22,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_1"                   ,	23,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	118,	"RAZ",	1,	1,	0,	0},
+	{"ULFE"                        ,	0,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF"                    ,	1,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	2,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	3,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	4,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	5,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	6,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	7,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	8,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	9,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_RM"                 ,	10,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	11,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	12,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	13,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	14,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	15,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	16,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	17,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_TX"                      ,	18,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX0"                     ,	19,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1"                     ,	20,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1_HARQ"                ,	21,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_0"                   ,	22,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_1"                   ,	23,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	119,	"RAZ",	1,	1,	0,	0},
+	{"ULFE"                        ,	0,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF"                    ,	1,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	2,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	3,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	4,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	5,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	6,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	7,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	8,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	9,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_RM"                 ,	10,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	11,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	12,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	13,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	14,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	15,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	16,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	17,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_TX"                      ,	18,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX0"                     ,	19,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1"                     ,	20,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1_HARQ"                ,	21,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_0"                   ,	22,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_1"                   ,	23,	1,	120,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	120,	"RAZ",	1,	1,	0,	0},
+	{"ULFE"                        ,	0,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF"                    ,	1,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	2,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	3,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	4,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	5,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	6,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	7,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	8,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	9,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_RM"                 ,	10,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	11,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	12,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	13,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	14,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	15,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	16,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	17,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_TX"                      ,	18,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX0"                     ,	19,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1"                     ,	20,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1_HARQ"                ,	21,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_0"                   ,	22,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_1"                   ,	23,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	121,	"RAZ",	1,	1,	0,	0},
+	{"GRPIDX"                      ,	0,	6,	122,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	122,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GRPIDX"                      ,	0,	6,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	123,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ULFE"                        ,	0,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF"                    ,	1,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	2,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	3,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	4,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	5,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	6,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	7,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	8,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	9,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_RM"                 ,	10,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	11,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	12,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	13,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	14,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	15,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	16,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	17,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_TX"                      ,	18,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX0"                     ,	19,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1"                     ,	20,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1_HARQ"                ,	21,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_0"                   ,	22,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_1"                   ,	23,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	124,	"RAZ",	1,	1,	0,	0},
+	{"ULFE"                        ,	0,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF"                    ,	1,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	2,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	3,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	4,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	5,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	6,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	7,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	8,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	9,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_RM"                 ,	10,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	11,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	12,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	13,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	14,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	15,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	16,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	17,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_TX"                      ,	18,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX0"                     ,	19,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1"                     ,	20,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1_HARQ"                ,	21,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_0"                   ,	22,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_1"                   ,	23,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	125,	"RAZ",	1,	1,	0,	0},
+	{"ULFE"                        ,	0,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF"                    ,	1,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	2,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	3,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	4,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	5,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	6,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	7,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	8,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	9,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_RM"                 ,	10,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	11,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	12,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	13,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	14,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	15,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	16,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	17,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_TX"                      ,	18,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX0"                     ,	19,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1"                     ,	20,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1_HARQ"                ,	21,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_0"                   ,	22,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_1"                   ,	23,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	126,	"RAZ",	1,	1,	0,	0},
+	{"ULFE"                        ,	0,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF"                    ,	1,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	2,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	3,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	4,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	5,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	6,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	7,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	8,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	9,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_RM"                 ,	10,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	11,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	12,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	13,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	14,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	15,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	16,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	17,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_TX"                      ,	18,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX0"                     ,	19,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1"                     ,	20,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1_HARQ"                ,	21,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_0"                   ,	22,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_1"                   ,	23,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	127,	"RAZ",	1,	1,	0,	0},
+	{"ULFE"                        ,	0,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF"                    ,	1,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	2,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	3,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	4,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	5,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	6,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	7,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	8,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	9,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_RM"                 ,	10,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	11,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	12,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	13,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	14,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	15,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	16,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	17,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_TX"                      ,	18,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX0"                     ,	19,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1"                     ,	20,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1_HARQ"                ,	21,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_0"                   ,	22,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_RFIF_1"                   ,	23,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	128,	"RAZ",	1,	1,	0,	0},
+	{"WRDONE"                      ,	0,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"RDDONE"                      ,	1,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"RDQDONE"                     ,	2,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"WRQDONE"                     ,	3,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"SW"                          ,	4,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"MISC"                        ,	5,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	129,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WRDONE"                      ,	0,	1,	130,	"RO",	0,	0,	0ull,	0ull},
+	{"RDDONE"                      ,	1,	1,	130,	"RO",	0,	0,	0ull,	0ull},
+	{"RDQDONE"                     ,	2,	1,	130,	"RO",	0,	0,	0ull,	0ull},
+	{"WRQDONE"                     ,	3,	1,	130,	"RO",	0,	0,	0ull,	0ull},
+	{"SW"                          ,	4,	1,	130,	"RO",	0,	0,	0ull,	0ull},
+	{"MISC"                        ,	5,	1,	130,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	130,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GRPIDX"                      ,	0,	6,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	131,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GRPIDX"                      ,	0,	6,	132,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	132,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SWINT"                       ,	0,	32,	133,	"R/W",	0,	0,	0ull,	0ull},
+	{"SWINT"                       ,	0,	32,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"SWINT"                       ,	0,	32,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"SWINT"                       ,	0,	32,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"SWINT"                       ,	0,	32,	137,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	32,	138,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	32,	139,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GRPIDX"                      ,	0,	6,	140,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	140,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GRPIDX"                      ,	0,	6,	141,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	141,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ULFE"                        ,	0,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_0"                  ,	1,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_1"                  ,	2,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	3,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	4,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_SB"                    ,	5,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	6,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	7,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	8,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	9,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_CCH"                  ,	10,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	11,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	12,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	13,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	14,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INSTR"                    ,	15,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	16,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	17,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	18,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INSTR"                    ,	19,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	20,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	21,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INSTR"                    ,	22,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_TX"                      ,	23,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX0"                     ,	24,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1"                     ,	25,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1_HARQ"                ,	26,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_RFIF_0"                   ,	27,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_RFIF_1"                   ,	28,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	142,	"RAZ",	1,	1,	0,	0},
+	{"ULFE"                        ,	0,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_0"                  ,	1,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_1"                  ,	2,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	3,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	4,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_SB"                    ,	5,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	6,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	7,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	8,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	9,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_CCH"                  ,	10,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	11,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	12,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	13,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	14,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INSTR"                    ,	15,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	16,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	17,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	18,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INSTR"                    ,	19,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	20,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	21,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INSTR"                    ,	22,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_TX"                      ,	23,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX0"                     ,	24,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1"                     ,	25,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1_HARQ"                ,	26,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_RFIF_0"                   ,	27,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_RFIF_1"                   ,	28,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	143,	"RAZ",	1,	1,	0,	0},
+	{"ULFE"                        ,	0,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_0"                  ,	1,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_1"                  ,	2,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	3,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	4,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_SB"                    ,	5,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	6,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	7,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	8,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	9,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_CCH"                  ,	10,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	11,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	12,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	13,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	14,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INSTR"                    ,	15,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	16,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	17,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	18,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INSTR"                    ,	19,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	20,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	21,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INSTR"                    ,	22,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_TX"                      ,	23,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX0"                     ,	24,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1"                     ,	25,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1_HARQ"                ,	26,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_RFIF_0"                   ,	27,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_RFIF_1"                   ,	28,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	144,	"RAZ",	1,	1,	0,	0},
+	{"ULFE"                        ,	0,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_0"                  ,	1,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_1"                  ,	2,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	3,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	4,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_SB"                    ,	5,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	6,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	7,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	8,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	9,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_CCH"                  ,	10,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	11,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	12,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	13,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	14,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INSTR"                    ,	15,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	16,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	17,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	18,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INSTR"                    ,	19,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	20,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	21,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INSTR"                    ,	22,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_TX"                      ,	23,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX0"                     ,	24,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1"                     ,	25,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1_HARQ"                ,	26,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_RFIF_0"                   ,	27,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_RFIF_1"                   ,	28,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	145,	"RAZ",	1,	1,	0,	0},
+	{"ULFE"                        ,	0,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_0"                  ,	1,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_1"                  ,	2,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	3,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	4,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_SB"                    ,	5,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	6,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	7,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	8,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	9,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_CCH"                  ,	10,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	11,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	12,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	13,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	14,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INSTR"                    ,	15,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	16,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	17,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	18,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INSTR"                    ,	19,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	20,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	21,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INSTR"                    ,	22,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_TX"                      ,	23,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX0"                     ,	24,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1"                     ,	25,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"AXI_RX1_HARQ"                ,	26,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_RFIF_0"                   ,	27,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_RFIF_1"                   ,	28,	1,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	146,	"RAZ",	1,	1,	0,	0},
+	{"GRPIDX"                      ,	0,	6,	147,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	147,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GRPIDX"                      ,	0,	6,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	148,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ULFE"                        ,	0,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_0"                  ,	1,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_1"                  ,	2,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	3,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	4,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_SB"                    ,	5,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	6,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	7,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	8,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	9,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_CCH"                  ,	10,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	11,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	12,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	13,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	14,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INSTR"                    ,	15,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	16,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	17,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	18,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INSTR"                    ,	19,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	20,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	21,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INSTR"                    ,	22,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	149,	"RAZ",	1,	1,	0,	0},
+	{"ULFE"                        ,	0,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_0"                  ,	1,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_1"                  ,	2,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	3,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	4,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_SB"                    ,	5,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	6,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	7,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	8,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	9,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_CCH"                  ,	10,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	11,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	12,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	13,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	14,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INSTR"                    ,	15,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	16,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	17,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	18,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INSTR"                    ,	19,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	20,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	21,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INSTR"                    ,	22,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	150,	"RAZ",	1,	1,	0,	0},
+	{"ULFE"                        ,	0,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_0"                  ,	1,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_1"                  ,	2,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	3,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	4,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_SB"                    ,	5,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	6,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	7,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	8,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	9,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_CCH"                  ,	10,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	11,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	12,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	13,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	14,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INSTR"                    ,	15,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	16,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	17,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	18,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INSTR"                    ,	19,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	20,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	21,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INSTR"                    ,	22,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	151,	"RAZ",	1,	1,	0,	0},
+	{"ULFE"                        ,	0,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_0"                  ,	1,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_1"                  ,	2,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	3,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	4,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_SB"                    ,	5,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	6,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	7,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	8,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	9,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_CCH"                  ,	10,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	11,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	12,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	13,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	14,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INSTR"                    ,	15,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	16,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	17,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	18,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INSTR"                    ,	19,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	20,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	21,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INSTR"                    ,	22,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	152,	"RAZ",	1,	1,	0,	0},
+	{"ULFE"                        ,	0,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_0"                  ,	1,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACHSNIF_1"                  ,	2,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFTDM"                       ,	3,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO"                       ,	4,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_SB"                    ,	5,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"TURBO_HQ"                    ,	6,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"VITBDEC"                     ,	7,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB0"                  ,	8,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_TB1"                  ,	9,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTEENC_CCH"                  ,	10,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_0"                  ,	11,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR_1"                  ,	12,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_EXT"                      ,	13,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INT"                      ,	14,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1_INSTR"                    ,	15,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_EXT"                      ,	16,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INT"                      ,	17,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_HARQ"                     ,	18,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2_INSTR"                    ,	19,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_EXT"                      ,	20,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INT"                      ,	21,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3_INSTR"                    ,	22,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	153,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	24,	154,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	154,	"RO",	0,	0,	0ull,	0ull},
+	{"ADDR"                        ,	0,	24,	155,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	155,	"RO",	0,	0,	0ull,	0ull},
+	{"ADDR"                        ,	0,	24,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	156,	"RO",	0,	0,	0ull,	0ull},
+	{"ADDR"                        ,	0,	24,	157,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	157,	"RO",	0,	0,	0ull,	0ull},
+	{"ADDR"                        ,	0,	24,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	158,	"RO",	0,	0,	0ull,	0ull},
+	{"ADDR"                        ,	0,	24,	159,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	159,	"RO",	0,	0,	0ull,	0ull},
+	{"ADDR"                        ,	0,	24,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	160,	"RO",	0,	0,	0ull,	0ull},
+	{"ADDR"                        ,	0,	24,	161,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	161,	"RO",	0,	0,	0ull,	0ull},
+	{"XFER_COMPLETE"               ,	0,	1,	162,	"WO",	0,	0,	0ull,	0ull},
+	{"XFER_Q_EMPTY"                ,	1,	1,	162,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	162,	"RO",	0,	0,	0ull,	0ull},
+	{"XFER_COMPLETE"               ,	0,	1,	163,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFER_Q_EMPTY"                ,	1,	1,	163,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"XFER_COMPLETE"               ,	0,	1,	164,	"RO",	0,	0,	0ull,	0ull},
+	{"XFER_Q_EMPTY"                ,	1,	1,	164,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	164,	"RO",	0,	0,	0ull,	0ull},
+	{"XFER_COMPLETE"               ,	0,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"XFER_Q_EMPTY"                ,	1,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"XFER_COMPLETE"               ,	0,	1,	166,	"WO",	0,	0,	0ull,	0ull},
+	{"XFER_Q_EMPTY"                ,	1,	1,	166,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"AUTO_CLK_ENB"                ,	0,	1,	167,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM_CLR_ENB"                 ,	1,	1,	167,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	167,	"RO",	0,	0,	0ull,	0ull},
+	{"ITLV_BUFMODE"                ,	4,	2,	167,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	167,	"RO",	0,	0,	0ull,	0ull},
+	{"ADDR"                        ,	0,	24,	168,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	168,	"RO",	0,	0,	0ull,	0ull},
+	{"ADDR"                        ,	0,	24,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	169,	"RO",	0,	0,	0ull,	0ull},
+	{"ADDR"                        ,	0,	24,	170,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	170,	"RO",	0,	0,	0ull,	0ull},
+	{"ADDR"                        ,	0,	24,	171,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	171,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_31"               ,	0,	32,	172,	"RO",	0,	0,	0ull,	0ull},
+	{"WORDCNT"                     ,	0,	16,	173,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_28"              ,	16,	13,	173,	"RO",	0,	0,	0ull,	0ull},
+	{"CBUF_MODE"                   ,	29,	1,	173,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLICE_MODE"                  ,	30,	1,	173,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFER_COMP_INTR"              ,	31,	1,	173,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATUS"                      ,	0,	32,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"START"                       ,	0,	1,	175,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	175,	"RO",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	176,	"RO",	0,	0,	0ull,	0ull},
+	{"OFFSET"                      ,	0,	20,	177,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	177,	"RO",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	178,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	20,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	180,	"R/W",	0,	0,	0ull,	1ull},
+	{"MODE"                        ,	1,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV"                         ,	2,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"FLUSH"                       ,	3,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"WAVESAT_MODE"                ,	4,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR_FIFO_UR"                 ,	5,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR_FIFO_OF"                 ,	6,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADI_EN"                      ,	7,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSP_RX_INT_EN"               ,	8,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAN_CTRL"                    ,	9,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_CTRL"                    ,	10,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXNRX_CTRL"                  ,	11,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"PROD_TYPE"                   ,	12,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"DUPLEX"                      ,	13,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIVERSITY"                   ,	14,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"UPD_STYLE"                   ,	15,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"MOL"                         ,	16,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBACK"                    ,	17,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"BEHAVIOR"                    ,	0,	1,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"IQ_CFG"                      ,	1,	1,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"LATENCY"                     ,	2,	1,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	181,	"RO",	0,	0,	0ull,	0ull},
+	{"VAL"                         ,	0,	4,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_31"               ,	4,	28,	182,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_31"               ,	0,	32,	183,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_15"               ,	0,	16,	184,	"RO",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	16,	8,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	184,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_FIL"                      ,	0,	1,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_DIF_FIL"                  ,	1,	1,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_FIL"                      ,	2,	1,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_DIV_FIL"                  ,	3,	1,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_31"               ,	4,	28,	185,	"RO",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	20,	186,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	186,	"RO",	0,	0,	0ull,	0ull},
+	{"LENGTH"                      ,	0,	20,	187,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	187,	"RO",	0,	0,	0ull,	0ull},
+	{"SRC"                         ,	0,	2,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"RISE_VAL"                    ,	2,	11,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALL_VAL"                    ,	13,	11,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"NUM"                         ,	0,	10,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_31"              ,	10,	22,	189,	"RO",	0,	0,	0ull,	0ull},
+	{"NUM"                         ,	0,	10,	190,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_31"              ,	10,	22,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"NUM"                         ,	0,	3,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	192,	"RO",	0,	0,	0ull,	0ull},
+	{"HI_TIME"                     ,	0,	24,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	193,	"RO",	0,	0,	0ull,	0ull},
+	{"LO_TIME"                     ,	0,	24,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"VAL"                         ,	0,	32,	195,	"RO",	0,	0,	0ull,	0ull},
+	{"VAL"                         ,	0,	32,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	0,	32,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	0,	32,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"OFFSET"                      ,	0,	4,	200,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_31"               ,	4,	28,	200,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	201,	"RO",	0,	0,	0ull,	0ull},
+	{"HAB_REQ_SM"                  ,	8,	4,	201,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_SM"                       ,	12,	2,	201,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_SM"                       ,	14,	2,	201,	"RO",	0,	0,	0ull,	0ull},
+	{"FIFO_UR"                     ,	16,	1,	201,	"RO",	0,	0,	0ull,	0ull},
+	{"FIFO_OF"                     ,	17,	1,	201,	"RO",	0,	0,	0ull,	0ull},
+	{"THRESH_RCH"                  ,	18,	1,	201,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_20"              ,	19,	2,	201,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC_LATE"                   ,	21,	1,	201,	"RO",	0,	0,	0ull,	0ull},
+	{"RFIC_ENA"                    ,	22,	1,	201,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	201,	"RO",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	13,	202,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	202,	"RO",	0,	0,	0ull,	0ull},
+	{"CAP_LAT"                     ,	0,	4,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"HALF_LAT"                    ,	4,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"EORL"                        ,	5,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	203,	"RO",	0,	0,	0ull,	0ull},
+	{"LEAD"                        ,	0,	12,	204,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAG"                         ,	12,	12,	204,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"EXE1"                        ,	0,	1,	205,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EXE2"                        ,	1,	1,	205,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EXE3"                        ,	2,	1,	205,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"ALT_ANT"                     ,	8,	1,	205,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"HIDDEN"                      ,	12,	1,	205,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"OFFSET"                      ,	0,	20,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	20,	207,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	207,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"HAB_REQ_SM"                  ,	8,	4,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_SM"                       ,	12,	2,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_SM"                       ,	14,	2,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"FIFO_UR"                     ,	16,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"FIFO_OF"                     ,	17,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"THRESH_RCH"                  ,	18,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_20"              ,	19,	2,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC_LATE"                   ,	21,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"RFIC_ENA"                    ,	22,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	20,	209,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	209,	"RO",	0,	0,	0ull,	0ull},
+	{"VAL"                         ,	0,	20,	210,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"THR"                         ,	0,	12,	211,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	211,	"RO",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	13,	212,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"END_CNT"                     ,	0,	20,	213,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	213,	"RO",	0,	0,	0ull,	0ull},
+	{"START_PNT"                   ,	0,	20,	214,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"ADJ"                         ,	0,	1,	215,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	215,	"RO",	0,	0,	0ull,	0ull},
+	{"OFFSET"                      ,	0,	32,	216,	"RC",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	20,	217,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	217,	"RO",	0,	0,	0ull,	0ull},
+	{"BITS"                        ,	0,	2,	218,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"NUM"                         ,	0,	20,	219,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"RW"                          ,	0,	1,	220,	"R/W",	0,	0,	0ull,	0ull},
+	{"GEN_INT"                     ,	1,	1,	220,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYTES"                       ,	2,	1,	220,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLAVE"                       ,	3,	1,	220,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_31"               ,	4,	28,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"WORD"                        ,	0,	24,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	221,	"RO",	0,	0,	0ull,	0ull},
+	{"NUM_CMDS0"                   ,	0,	6,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_CMDS1"                   ,	6,	6,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_CMDS2"                   ,	12,	6,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_CMDS3"                   ,	18,	6,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"START0"                      ,	0,	6,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"START1"                      ,	6,	6,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"START2"                      ,	12,	6,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"START3"                      ,	18,	6,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	223,	"RO",	0,	0,	0ull,	0ull},
+	{"CTRL"                        ,	0,	32,	224,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	16,	225,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	225,	"RO",	0,	0,	0ull,	0ull},
+	{"RD_DATA"                     ,	0,	32,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_FIFO_LVL"                 ,	0,	4,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_FIFO_LVL"                 ,	4,	4,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"SR_STATE"                    ,	8,	4,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	228,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	8,	8,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR"                        ,	16,	9,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_30"              ,	25,	6,	228,	"RO",	0,	0,	0ull,	0ull},
+	{"WRITE"                       ,	31,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKS"                        ,	0,	8,	229,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_31"               ,	8,	24,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	230,	"RO",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	20,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	8,	232,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_31"               ,	8,	24,	232,	"RO",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	8,	233,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_31"               ,	8,	24,	233,	"RO",	0,	0,	0ull,	0ull},
+	{"MAP"                         ,	0,	8,	234,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_31"               ,	8,	24,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	8,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_31"               ,	8,	24,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"HAB_REQ_SM"                  ,	8,	4,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_SM"                       ,	12,	2,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_SM"                       ,	14,	2,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"FIFO_UR"                     ,	16,	1,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"FIFO_OF"                     ,	17,	1,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"THRESH_RCH"                  ,	18,	1,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_20"              ,	19,	2,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC_LATE"                   ,	21,	1,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"RFIC_ENA"                    ,	22,	1,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"ANTENNA"                     ,	0,	2,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIS_SCH"                     ,	2,	1,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE"                        ,	3,	1,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_31"               ,	4,	28,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"LEAD"                        ,	0,	12,	238,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAG"                         ,	12,	12,	238,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"OFFSET"                      ,	0,	20,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	239,	"RO",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	20,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"HAB_REQ_SM"                  ,	8,	4,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_SM"                       ,	12,	2,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_SM"                       ,	14,	2,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"FIFO_UR"                     ,	16,	1,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"FIFO_OF"                     ,	17,	1,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"THRESH_RCH"                  ,	18,	1,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_20"              ,	19,	2,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC_LATE"                   ,	21,	1,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"RFIC_ENA"                    ,	22,	1,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"THR"                         ,	0,	12,	242,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	242,	"RO",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	4,	243,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_31"               ,	4,	28,	243,	"RO",	0,	0,	0ull,	0ull},
+	{"SCNT"                        ,	0,	20,	244,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"VAL"                         ,	0,	32,	245,	"WO",	0,	0,	0ull,	0ull},
+	{"VAL"                         ,	0,	32,	246,	"WO",	0,	0,	0ull,	0ull},
+	{"ULFE"                        ,	0,	1,	247,	"WO",	0,	0,	0ull,	0ull},
+	{"RACHFE"                      ,	1,	1,	247,	"WO",	0,	0,	0ull,	0ull},
+	{"RX0SEQ"                      ,	2,	1,	247,	"WO",	0,	0,	0ull,	0ull},
+	{"DFTDMAP"                     ,	3,	1,	247,	"WO",	0,	0,	0ull,	0ull},
+	{"RX1SEQ"                      ,	4,	1,	247,	"WO",	0,	0,	0ull,	0ull},
+	{"TURBOPHY"                    ,	5,	1,	247,	"WO",	0,	0,	0ull,	0ull},
+	{"TURBODSP"                    ,	6,	1,	247,	"WO",	0,	0,	0ull,	0ull},
+	{"VDEC"                        ,	7,	1,	247,	"WO",	0,	0,	0ull,	0ull},
+	{"LTEENC"                      ,	8,	1,	247,	"WO",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR"                    ,	9,	1,	247,	"WO",	0,	0,	0ull,	0ull},
+	{"V3GENC"                      ,	10,	1,	247,	"WO",	0,	0,	0ull,	0ull},
+	{"TXSEQ"                       ,	11,	1,	247,	"WO",	0,	0,	0ull,	0ull},
+	{"AXIDMA"                      ,	12,	1,	247,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"ULFE"                        ,	0,	1,	248,	"WO",	0,	0,	0ull,	0ull},
+	{"RACHFE"                      ,	1,	1,	248,	"WO",	0,	0,	0ull,	0ull},
+	{"RX0SEQ"                      ,	2,	1,	248,	"WO",	0,	0,	0ull,	0ull},
+	{"DFTDMAP"                     ,	3,	1,	248,	"WO",	0,	0,	0ull,	0ull},
+	{"RX1SEQ"                      ,	4,	1,	248,	"WO",	0,	0,	0ull,	0ull},
+	{"TURBOPHY"                    ,	5,	1,	248,	"WO",	0,	0,	0ull,	0ull},
+	{"TURBODSP"                    ,	6,	1,	248,	"WO",	0,	0,	0ull,	0ull},
+	{"VDEC"                        ,	7,	1,	248,	"WO",	0,	0,	0ull,	0ull},
+	{"LTEENC"                      ,	8,	1,	248,	"WO",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR"                    ,	9,	1,	248,	"WO",	0,	0,	0ull,	0ull},
+	{"V3GENC"                      ,	10,	1,	248,	"WO",	0,	0,	0ull,	0ull},
+	{"TXSEQ"                       ,	11,	1,	248,	"WO",	0,	0,	0ull,	0ull},
+	{"AXIDMA"                      ,	12,	1,	248,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"ULFE"                        ,	0,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RACHFE"                      ,	1,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RX0SEQ"                      ,	2,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"DFTDMAP"                     ,	3,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RX1SEQ"                      ,	4,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"TURBOPHY"                    ,	5,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"TURBODSP"                    ,	6,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"VDEC"                        ,	7,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"LTEENC"                      ,	8,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR"                    ,	9,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"V3GENC"                      ,	10,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"TXSEQ"                       ,	11,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"AXIDMA"                      ,	12,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RFIF_RF"                     ,	0,	1,	250,	"WO",	0,	0,	0ull,	0ull},
+	{"RFIF_HAB"                    ,	1,	1,	250,	"WO",	0,	0,	0ull,	0ull},
+	{"RFSPI"                       ,	2,	1,	250,	"WO",	0,	0,	0ull,	0ull},
+	{"TILE1DSP"                    ,	3,	1,	250,	"WO",	0,	0,	0ull,	0ull},
+	{"TILE2DSP"                    ,	4,	1,	250,	"WO",	0,	0,	0ull,	0ull},
+	{"TILE3DSP"                    ,	5,	1,	250,	"WO",	0,	0,	0ull,	0ull},
+	{"TOKEN"                       ,	6,	1,	250,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	250,	"RO",	0,	0,	0ull,	0ull},
+	{"RFIF_RF"                     ,	0,	1,	251,	"WO",	0,	0,	0ull,	0ull},
+	{"RFIF_HAB"                    ,	1,	1,	251,	"WO",	0,	0,	0ull,	0ull},
+	{"RFSPI"                       ,	2,	1,	251,	"WO",	0,	0,	0ull,	0ull},
+	{"TILE1DSP"                    ,	3,	1,	251,	"WO",	0,	0,	0ull,	0ull},
+	{"TILE2DSP"                    ,	4,	1,	251,	"WO",	0,	0,	0ull,	0ull},
+	{"TILE3DSP"                    ,	5,	1,	251,	"WO",	0,	0,	0ull,	0ull},
+	{"TOKEN"                       ,	6,	1,	251,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	251,	"RO",	0,	0,	0ull,	0ull},
+	{"RFIF_RF"                     ,	0,	1,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"RFIF_HAB"                    ,	1,	1,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"RFSPI"                       ,	2,	1,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"TILE1DSP"                    ,	3,	1,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"TILE2DSP"                    ,	4,	1,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"TILE3DSP"                    ,	5,	1,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"TOKEN"                       ,	6,	1,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"RX0DSP0"                     ,	0,	1,	253,	"WO",	0,	0,	0ull,	0ull},
+	{"RX0DSP1"                     ,	1,	1,	253,	"WO",	0,	0,	0ull,	0ull},
+	{"RX1DSP0"                     ,	2,	1,	253,	"WO",	0,	0,	0ull,	0ull},
+	{"RX1DSP1"                     ,	3,	1,	253,	"WO",	0,	0,	0ull,	0ull},
+	{"TXDSP0"                      ,	4,	1,	253,	"WO",	0,	0,	0ull,	0ull},
+	{"TXDSP1"                      ,	5,	1,	253,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"RX0DSP0"                     ,	0,	1,	254,	"WO",	0,	0,	0ull,	0ull},
+	{"RX0DSP1"                     ,	1,	1,	254,	"WO",	0,	0,	0ull,	0ull},
+	{"RX1DSP0"                     ,	2,	1,	254,	"WO",	0,	0,	0ull,	0ull},
+	{"RX1DSP1"                     ,	3,	1,	254,	"WO",	0,	0,	0ull,	0ull},
+	{"TXDSP0"                      ,	4,	1,	254,	"WO",	0,	0,	0ull,	0ull},
+	{"TXDSP1"                      ,	5,	1,	254,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	254,	"RO",	0,	0,	0ull,	0ull},
+	{"RX0DSP0"                     ,	0,	1,	255,	"RO",	0,	0,	0ull,	0ull},
+	{"RX0DSP1"                     ,	1,	1,	255,	"RO",	0,	0,	0ull,	0ull},
+	{"RX1DSP0"                     ,	2,	1,	255,	"RO",	0,	0,	0ull,	0ull},
+	{"RX1DSP1"                     ,	3,	1,	255,	"RO",	0,	0,	0ull,	0ull},
+	{"TXDSP0"                      ,	4,	1,	255,	"RO",	0,	0,	0ull,	0ull},
+	{"TXDSP1"                      ,	5,	1,	255,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	255,	"RO",	0,	0,	0ull,	0ull},
+	{"SW_INTR"                     ,	0,	24,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMER_INTR"                  ,	24,	8,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"SW_INTR"                     ,	0,	24,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMER_INTR"                  ,	24,	8,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"SW_INTR"                     ,	0,	24,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMER_INTR"                  ,	24,	8,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"VALUE"                       ,	0,	32,	259,	"RO",	0,	0,	0ull,	0ull},
+	{"VALUE"                       ,	0,	32,	260,	"RO",	0,	0,	0ull,	0ull},
+	{"VALUE"                       ,	0,	32,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"VALUE"                       ,	0,	32,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"VALUE"                       ,	0,	32,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"T1IMEM_INITENB"              ,	0,	1,	264,	"R/W",	0,	0,	0ull,	0ull},
+	{"T1SMEM_INITENB"              ,	1,	1,	264,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2IMEM_INITENB"              ,	2,	1,	264,	"R/W",	0,	0,	0ull,	0ull},
+	{"T2SMEM_INITENB"              ,	3,	1,	264,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3IMEM_INITENB"              ,	4,	1,	264,	"R/W",	0,	0,	0ull,	0ull},
+	{"T3SMEM_INITENB"              ,	5,	1,	264,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"RINGOSC_COUNT"               ,	0,	16,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"TRANSISTOR_SEL"              ,	16,	2,	265,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"COUNT"                       ,	0,	24,	266,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	266,	"RO",	0,	0,	0ull,	0ull},
+	{"ULFE"                        ,	0,	1,	267,	"WO",	0,	0,	0ull,	0ull},
+	{"RACHFE"                      ,	1,	1,	267,	"WO",	0,	0,	0ull,	0ull},
+	{"RX0SEQ"                      ,	2,	1,	267,	"WO",	0,	0,	0ull,	0ull},
+	{"DFTDMAP"                     ,	3,	1,	267,	"WO",	0,	0,	0ull,	0ull},
+	{"RX1SEQ"                      ,	4,	1,	267,	"WO",	0,	0,	0ull,	0ull},
+	{"TURBOPHY"                    ,	5,	1,	267,	"WO",	0,	0,	0ull,	0ull},
+	{"TURBODSP"                    ,	6,	1,	267,	"WO",	0,	0,	0ull,	0ull},
+	{"VDEC"                        ,	7,	1,	267,	"WO",	0,	0,	0ull,	0ull},
+	{"LTEENC"                      ,	8,	1,	267,	"WO",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR"                    ,	9,	1,	267,	"WO",	0,	0,	0ull,	0ull},
+	{"V3GENC"                      ,	10,	1,	267,	"WO",	0,	0,	0ull,	0ull},
+	{"TXSEQ"                       ,	11,	1,	267,	"WO",	0,	0,	0ull,	0ull},
+	{"AXIDMA"                      ,	12,	1,	267,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	267,	"RO",	0,	0,	0ull,	0ull},
+	{"ULFE"                        ,	0,	1,	268,	"WO",	0,	0,	0ull,	0ull},
+	{"RACHFE"                      ,	1,	1,	268,	"WO",	0,	0,	0ull,	0ull},
+	{"RX0SEQ"                      ,	2,	1,	268,	"WO",	0,	0,	0ull,	0ull},
+	{"DFTDMAP"                     ,	3,	1,	268,	"WO",	0,	0,	0ull,	0ull},
+	{"RX1SEQ"                      ,	4,	1,	268,	"WO",	0,	0,	0ull,	0ull},
+	{"TURBOPHY"                    ,	5,	1,	268,	"WO",	0,	0,	0ull,	0ull},
+	{"TURBODSP"                    ,	6,	1,	268,	"WO",	0,	0,	0ull,	0ull},
+	{"VDEC"                        ,	7,	1,	268,	"WO",	0,	0,	0ull,	0ull},
+	{"LTEENC"                      ,	8,	1,	268,	"WO",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR"                    ,	9,	1,	268,	"WO",	0,	0,	0ull,	0ull},
+	{"V3GENC"                      ,	10,	1,	268,	"WO",	0,	0,	0ull,	0ull},
+	{"TXSEQ"                       ,	11,	1,	268,	"WO",	0,	0,	0ull,	0ull},
+	{"AXIDMA"                      ,	12,	1,	268,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	268,	"RO",	0,	0,	0ull,	0ull},
+	{"ULFE"                        ,	0,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"RACHFE"                      ,	1,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"RX0SEQ"                      ,	2,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"DFTDMAP"                     ,	3,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"RX1SEQ"                      ,	4,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"TURBOPHY"                    ,	5,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"TURBODSP"                    ,	6,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"VDEC"                        ,	7,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"LTEENC"                      ,	8,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"IFFTPAPR"                    ,	9,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"V3GENC"                      ,	10,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"TXSEQ"                       ,	11,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"AXIDMA"                      ,	12,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"RFIF_RF"                     ,	0,	1,	270,	"WO",	0,	0,	0ull,	0ull},
+	{"RFIF_HAB"                    ,	1,	1,	270,	"WO",	0,	0,	0ull,	0ull},
+	{"RFSPI"                       ,	2,	1,	270,	"WO",	0,	0,	0ull,	0ull},
+	{"TILE1DSP"                    ,	3,	1,	270,	"WO",	0,	0,	0ull,	0ull},
+	{"TILE2DSP"                    ,	4,	1,	270,	"WO",	0,	0,	0ull,	0ull},
+	{"TILE3DSP"                    ,	5,	1,	270,	"WO",	0,	0,	0ull,	0ull},
+	{"TOKEN"                       ,	6,	1,	270,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	270,	"RO",	0,	0,	0ull,	0ull},
+	{"RFIF_RF"                     ,	0,	1,	271,	"WO",	0,	0,	0ull,	0ull},
+	{"RFIF_HAB"                    ,	1,	1,	271,	"WO",	0,	0,	0ull,	0ull},
+	{"RFSPI"                       ,	2,	1,	271,	"WO",	0,	0,	0ull,	0ull},
+	{"TILE1DSP"                    ,	3,	1,	271,	"WO",	0,	0,	0ull,	0ull},
+	{"TILE2DSP"                    ,	4,	1,	271,	"WO",	0,	0,	0ull,	0ull},
+	{"TILE3DSP"                    ,	5,	1,	271,	"WO",	0,	0,	0ull,	0ull},
+	{"TOKEN"                       ,	6,	1,	271,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	271,	"RO",	0,	0,	0ull,	0ull},
+	{"RFIF_RF"                     ,	0,	1,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"RFIF_HAB"                    ,	1,	1,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"RFSPI"                       ,	2,	1,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"TILE1DSP"                    ,	3,	1,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"TILE2DSP"                    ,	4,	1,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"TILE3DSP"                    ,	5,	1,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"TOKEN"                       ,	6,	1,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"SW_INTR"                     ,	0,	24,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMER_INTR"                  ,	24,	8,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"SW_INTR"                     ,	0,	24,	274,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMER_INTR"                  ,	24,	8,	274,	"RO",	0,	0,	0ull,	0ull},
+	{"SW_INTR"                     ,	0,	24,	275,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMER_INTR"                  ,	24,	8,	275,	"RO",	0,	0,	0ull,	0ull},
+	{"VALUE"                       ,	0,	24,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	276,	"RO",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	1,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"CONT"                        ,	1,	1,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	2,	1,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"INTR_ENB"                    ,	8,	8,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	8,	278,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_31"               ,	8,	24,	278,	"RO",	0,	0,	0ull,	0ull},
+	{"STATUS"                      ,	0,	8,	279,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_31"               ,	8,	24,	279,	"RO",	0,	0,	0ull,	0ull},
+	{"VALUE"                       ,	0,	32,	280,	"RO",	0,	0,	0ull,	0ull},
+	{"VALUE"                       ,	0,	32,	281,	"RO",	0,	0,	0ull,	0ull},
+	{"MINOR"                       ,	0,	8,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"MAJOR"                       ,	8,	8,	282,	"RO",	0,	0,	0ull,	16ull},
+	{"RESERVED_16_31"              ,	16,	16,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"LDDF"                        ,	0,	1,	283,	"RO",	1,	0,	0,	0ull},
+	{"PPAF"                        ,	1,	1,	283,	"RO",	1,	0,	0,	0ull},
+	{"STDF"                        ,	2,	1,	283,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_3_15"               ,	3,	13,	283,	"RAZ",	1,	1,	0,	0},
+	{"START_BIST"                  ,	16,	1,	283,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLEAR_BIST"                  ,	17,	1,	283,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	283,	"RAZ",	1,	1,	0,	0},
+	{"RESET"                       ,	0,	1,	284,	"R/W",	0,	0,	1ull,	0ull},
+	{"ENA"                         ,	1,	1,	284,	"R/W",	0,	0,	1ull,	1ull},
+	{"RWAM"                        ,	2,	2,	284,	"R/W",	0,	0,	0ull,	0ull},
+	{"BUSY"                        ,	4,	1,	284,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	284,	"RAZ",	1,	1,	0,	0},
+	{"PPAF_WM"                     ,	8,	5,	284,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_13_63"              ,	13,	51,	284,	"RAZ",	1,	1,	0,	0},
+	{"ROUT0"                       ,	0,	18,	285,	"RO",	1,	0,	0,	0ull},
+	{"ROUT1"                       ,	18,	18,	285,	"RO",	1,	0,	0,	0ull},
+	{"ROUT2"                       ,	36,	18,	285,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	285,	"RAZ",	1,	1,	0,	0},
+	{"ROUT3"                       ,	0,	18,	286,	"RO",	1,	0,	0,	0ull},
+	{"ROUT4"                       ,	18,	18,	286,	"RO",	1,	0,	0,	0ull},
+	{"ROUT5"                       ,	36,	18,	286,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	286,	"RAZ",	1,	1,	0,	0},
+	{"ROUT6"                       ,	0,	18,	287,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_18_23"              ,	18,	6,	287,	"RAZ",	1,	1,	0,	0},
+	{"TOOMANY"                     ,	24,	1,	287,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	287,	"RAZ",	1,	1,	0,	0},
+	{"RBSF"                        ,	0,	2,	288,	"R/W",	0,	0,	0ull,	0ull},
+	{"RBEN"                        ,	2,	1,	288,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	288,	"RAZ",	1,	1,	0,	0},
+	{"START_BIST"                  ,	0,	1,	289,	"R/W",	0,	0,	0ull,	0ull},
+	{"BISR_DIR"                    ,	1,	1,	289,	"R/W",	0,	0,	0ull,	0ull},
+	{"BISR_HR"                     ,	2,	1,	289,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	289,	"RAZ",	1,	1,	0,	0},
+	{"FAILED"                      ,	8,	1,	289,	"RO",	1,	0,	0,	0ull},
+	{"BISR_DONE"                   ,	9,	1,	289,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	289,	"RAZ",	1,	1,	0,	0},
+	{"CLKF"                        ,	0,	7,	290,	"R/W",	0,	1,	32ull,	0},
+	{"RESET_N"                     ,	7,	1,	290,	"R/W",	0,	0,	0ull,	1ull},
+	{"CPB"                         ,	8,	3,	290,	"R/W",	0,	0,	0ull,	1ull},
+	{"CPS"                         ,	11,	3,	290,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIFFAMP"                     ,	14,	4,	290,	"R/W",	0,	0,	0ull,	1ull},
+	{"HAB_PS_EN"                   ,	18,	3,	290,	"R/W",	0,	1,	5ull,	0},
+	{"HAB_DIV_RESET"               ,	21,	1,	290,	"R/W",	0,	0,	1ull,	0ull},
+	{"DSP_PS_EN"                   ,	22,	3,	290,	"R/W",	0,	1,	4ull,	0},
+	{"DSP_DIV_RESET"               ,	25,	1,	290,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_26_26"              ,	26,	1,	290,	"RAZ",	1,	1,	0,	0},
+	{"HABCLK_SEL"                  ,	27,	1,	290,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	290,	"RAZ",	1,	1,	0,	0},
+	{"RESET"                       ,	0,	1,	291,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	291,	"RAZ",	1,	1,	0,	0},
+	{"INV_PP_WA2"                  ,	4,	1,	291,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_PP_RA2"                  ,	5,	1,	291,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_RSL_WA2"                 ,	6,	1,	291,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_RSL_RA2"                 ,	7,	1,	291,	"R/W",	0,	0,	0ull,	0ull},
+	{"W_EMOD"                      ,	8,	2,	291,	"R/W",	0,	0,	0ull,	0ull},
+	{"R_EMOD"                      ,	10,	2,	291,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	291,	"RAZ",	1,	1,	0,	0},
+	{"RB_SBE"                      ,	0,	1,	292,	"R/W",	0,	0,	1ull,	1ull},
+	{"RB_DBE"                      ,	1,	1,	292,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	292,	"RAZ",	1,	1,	0,	0},
+	{"RB_SBE"                      ,	0,	1,	293,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RB_DBE"                      ,	1,	1,	293,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	293,	"RAZ",	1,	1,	0,	0},
+	{"GPO_N"                       ,	0,	6,	294,	"R/W",	0,	0,	24ull,	24ull},
+	{"GPO_P"                       ,	6,	6,	294,	"R/W",	0,	0,	27ull,	27ull},
+	{"RFIF_N"                      ,	12,	6,	294,	"R/W",	0,	0,	24ull,	24ull},
+	{"RFIF_P"                      ,	18,	6,	294,	"R/W",	0,	0,	27ull,	27ull},
+	{"RESERVED_24_63"              ,	24,	40,	294,	"RAZ",	1,	1,	0,	0},
+	{"LDC"                         ,	0,	4,	295,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_7"                ,	4,	4,	295,	"RAZ",	1,	1,	0,	0},
+	{"STC"                         ,	8,	2,	295,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_10_15"              ,	10,	6,	295,	"RAZ",	1,	1,	0,	0},
+	{"STD"                         ,	16,	5,	295,	"R/W",	0,	0,	31ull,	31ull},
+	{"RESERVED_21_63"              ,	21,	43,	295,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	33,	296,	"RO",	0,	1,	0ull,	0},
+	{"POOL"                        ,	33,	5,	296,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	296,	"RAZ",	1,	1,	0,	0},
+	{"FDR"                         ,	0,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"FFR"                         ,	1,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF1"                        ,	2,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF0"                        ,	3,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"FRD"                         ,	4,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	297,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	298,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	298,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	14,	1,	298,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_STT"                     ,	15,	1,	298,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_LDT"                     ,	16,	1,	298,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	298,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_OFF"                     ,	18,	1,	298,	"R/W",	0,	0,	0ull,	0ull},
+	{"RET_OFF"                     ,	19,	1,	298,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE_EN"                     ,	20,	1,	298,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	298,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	11,	299,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	11,	11,	299,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	299,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	11,	300,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	300,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	12,	301,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	12,	12,	301,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	301,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	12,	302,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	302,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL0TH"                     ,	28,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL1TH"                     ,	29,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL2TH"                     ,	30,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL3TH"                     ,	31,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL4TH"                     ,	32,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL5TH"                     ,	33,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL6TH"                     ,	34,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL7TH"                     ,	35,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE0"                       ,	36,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE1"                       ,	37,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE2"                       ,	38,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE3"                       ,	39,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE4"                       ,	40,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE5"                       ,	41,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE6"                       ,	42,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE7"                       ,	43,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"RES_44"                      ,	44,	5,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"PADDR_E"                     ,	49,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_63"              ,	50,	14,	303,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL0TH"                     ,	28,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL1TH"                     ,	29,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL2TH"                     ,	30,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL3TH"                     ,	31,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL4TH"                     ,	32,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL5TH"                     ,	33,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL6TH"                     ,	34,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL7TH"                     ,	35,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE0"                       ,	36,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE1"                       ,	37,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE2"                       ,	38,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE3"                       ,	39,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE4"                       ,	40,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE5"                       ,	41,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE6"                       ,	42,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE7"                       ,	43,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_48"              ,	44,	5,	304,	"RAZ",	1,	1,	0,	0},
+	{"PADDR_E"                     ,	49,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_50_63"              ,	50,	14,	304,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	32,	305,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	305,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	33,	306,	"R/W",	0,	1,	8589934591ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	306,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	33,	307,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	307,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	29,	308,	"R/W",	0,	0,	536870911ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	308,	"RAZ",	1,	1,	0,	0},
+	{"QUE_SIZ"                     ,	0,	29,	309,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	309,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	310,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	310,	"RAZ",	1,	1,	0,	0},
+	{"ACT_INDX"                    ,	0,	26,	311,	"RO",	0,	1,	0ull,	0},
+	{"ACT_QUE"                     ,	26,	3,	311,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	311,	"RO",	0,	0,	0ull,	7ull},
+	{"EXP_INDX"                    ,	0,	26,	312,	"RO",	0,	1,	0ull,	0},
+	{"EXP_QUE"                     ,	26,	3,	312,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	312,	"RO",	0,	0,	0ull,	7ull},
+	{"THRESH"                      ,	0,	32,	313,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	313,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	314,	"RAZ",	1,	1,	0,	0},
+	{"OUT_OVR"                     ,	2,	4,	314,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_21"               ,	6,	16,	314,	"RAZ",	1,	1,	0,	0},
+	{"LOSTSTAT"                    ,	22,	4,	314,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	314,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INB_NXA"                     ,	27,	4,	314,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	314,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	25,	315,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	315,	"RAZ",	1,	1,	0,	0},
+	{"CLK_EN"                      ,	0,	1,	316,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	316,	"RAZ",	1,	1,	0,	0},
+	{"LOGL_EN"                     ,	0,	16,	317,	"R/W",	0,	1,	65535ull,	0},
+	{"PHYS_EN"                     ,	16,	1,	317,	"R/W",	0,	1,	1ull,	0},
+	{"HG2RX_EN"                    ,	17,	1,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2TX_EN"                    ,	18,	1,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	317,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	1,	318,	"RO",	0,	1,	0ull,	0},
+	{"EN"                          ,	1,	1,	318,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_3"                ,	2,	2,	318,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	4,	1,	318,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	318,	"RAZ",	1,	1,	0,	0},
+	{"SPEED"                       ,	8,	4,	318,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	318,	"RAZ",	1,	1,	0,	0},
+	{"PRT"                         ,	0,	6,	319,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	319,	"RAZ",	1,	1,	0,	0},
+	{"RX_EN"                       ,	0,	1,	320,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_EN"                       ,	1,	1,	320,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRP_EN"                      ,	2,	1,	320,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCK_EN"                      ,	3,	1,	320,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	320,	"RAZ",	1,	1,	0,	0},
+	{"PHYS_BP"                     ,	16,	16,	320,	"R/W",	0,	1,	65535ull,	0},
+	{"LOGL_EN"                     ,	32,	16,	320,	"R/W",	0,	0,	255ull,	255ull},
+	{"PHYS_EN"                     ,	48,	16,	320,	"R/W",	0,	0,	255ull,	255ull},
+	{"EN"                          ,	0,	1,	321,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	321,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	321,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	321,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	321,	"RAZ",	1,	1,	0,	0},
+	{"SPEED_MSB"                   ,	8,	1,	321,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	321,	"RAZ",	1,	1,	0,	0},
+	{"RX_IDLE"                     ,	12,	1,	321,	"RO",	0,	1,	1ull,	0},
+	{"TX_IDLE"                     ,	13,	1,	321,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	321,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	322,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	323,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	324,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	325,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	326,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	327,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	32,	328,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	328,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	329,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	329,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	330,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	330,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	330,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	330,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	331,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	331,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	332,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	332,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_2"                ,	2,	1,	332,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	332,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	332,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_6"                ,	5,	2,	332,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	332,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	332,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	332,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	333,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	333,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	333,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	333,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	333,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	333,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_8"                ,	7,	2,	333,	"RAZ",	1,	1,	0,	0},
+	{"PRE_ALIGN"                   ,	9,	1,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"NULL_DIS"                    ,	10,	1,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	333,	"RAZ",	1,	1,	0,	0},
+	{"PTP_MODE"                    ,	12,	1,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	333,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	334,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	334,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	335,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	335,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	335,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	335,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	335,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	335,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	336,	"R/W1C",	0,	1,	0ull,	0},
+	{"CAREXT"                      ,	1,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	336,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	336,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	336,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	336,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	336,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	337,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	337,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	338,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	338,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	339,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	339,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	340,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	340,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	341,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	341,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	342,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	342,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	343,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	343,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	344,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	344,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	345,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	345,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	346,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	346,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	347,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	347,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	348,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	348,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	349,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	349,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	349,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	349,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	350,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	350,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	351,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	351,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	352,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_9_63"               ,	9,	55,	352,	"RAZ",	1,	1,	0,	0},
+	{"LGTIM2GO"                    ,	0,	16,	353,	"RO",	0,	1,	0ull,	0},
+	{"XOF"                         ,	16,	16,	353,	"RO",	0,	0,	0ull,	0ull},
+	{"PHTIM2GO"                    ,	32,	16,	353,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	353,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	2,	354,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_15"               ,	2,	14,	354,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	2,	354,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	354,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	3,	355,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_3_63"               ,	3,	61,	355,	"RAZ",	1,	1,	0,	0},
+	{"LANE_RXD"                    ,	0,	32,	356,	"RO",	0,	1,	0ull,	0},
+	{"LANE_RXC"                    ,	32,	4,	356,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	3,	356,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	39,	1,	356,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	356,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	2,	357,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	357,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	358,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	358,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	359,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	359,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	359,	"RAZ",	1,	1,	0,	0},
+	{"WR_MAGIC"                    ,	0,	1,	360,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	360,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	361,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	361,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	361,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	361,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	361,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	16,	362,	"R/W",	0,	0,	8192ull,	8192ull},
+	{"RESERVED_16_63"              ,	16,	48,	362,	"RAZ",	1,	1,	0,	0},
+	{"XOFF"                        ,	0,	16,	363,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	363,	"RAZ",	1,	1,	0,	0},
+	{"XON"                         ,	0,	16,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	364,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	365,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	365,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	365,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	366,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	366,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	367,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	367,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	368,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	368,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	369,	"RO",	1,	1,	0,	0},
+	{"MSG_TIME"                    ,	16,	16,	369,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	369,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	370,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	370,	"RAZ",	1,	1,	0,	0},
+	{"ALIGN"                       ,	0,	1,	371,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	371,	"RAZ",	1,	1,	0,	0},
+	{"SLOT"                        ,	0,	10,	372,	"R/W",	0,	0,	512ull,	512ull},
+	{"RESERVED_10_63"              ,	10,	54,	372,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	373,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	373,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	374,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	374,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	375,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	375,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	376,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	376,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	377,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	377,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	378,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	378,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	379,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	379,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	380,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	380,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	381,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	381,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	382,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	382,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	383,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	383,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	384,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	384,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	9,	385,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_9_63"               ,	9,	55,	385,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	2,	386,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	386,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	387,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	387,	"RAZ",	1,	1,	0,	0},
+	{"CORRUPT"                     ,	0,	2,	388,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_2_63"               ,	2,	62,	388,	"RAZ",	1,	1,	0,	0},
+	{"TX_XOF"                      ,	0,	16,	389,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	389,	"RAZ",	1,	1,	0,	0},
+	{"TX_XON"                      ,	0,	16,	390,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	390,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	391,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	391,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	391,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	392,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	392,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	2,	392,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	392,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	8,	2,	392,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	392,	"RAZ",	1,	1,	0,	0},
+	{"XSDEF"                       ,	12,	2,	392,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	392,	"RAZ",	1,	1,	0,	0},
+	{"LATE_COL"                    ,	16,	2,	392,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	392,	"RAZ",	1,	1,	0,	0},
+	{"PTP_LOST"                    ,	20,	2,	392,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	392,	"RAZ",	1,	1,	0,	0},
+	{"XCHANGE"                     ,	24,	1,	392,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	392,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	393,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	2,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	393,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	8,	2,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	393,	"RAZ",	1,	1,	0,	0},
+	{"XSDEF"                       ,	12,	2,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	393,	"RAZ",	1,	1,	0,	0},
+	{"LATE_COL"                    ,	16,	2,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	393,	"RAZ",	1,	1,	0,	0},
+	{"PTP_LOST"                    ,	20,	2,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	393,	"RAZ",	1,	1,	0,	0},
+	{"XCHANGE"                     ,	24,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	393,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	394,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	394,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	395,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	395,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	2,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	396,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	4,	2,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	396,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	8,	2,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_31"              ,	10,	22,	396,	"RAZ",	1,	1,	0,	0},
+	{"TX_PRT_BP"                   ,	32,	16,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	396,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	397,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	397,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	398,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	398,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	5,	399,	"R/W",	0,	1,	2ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	399,	"RAZ",	1,	1,	0,	0},
+	{"DIC_EN"                      ,	0,	1,	400,	"R/W",	0,	0,	0ull,	1ull},
+	{"UNI_EN"                      ,	1,	1,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	400,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	4,	2,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"LS_BYP"                      ,	6,	1,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	400,	"RAZ",	1,	1,	0,	0},
+	{"HG_EN"                       ,	8,	1,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_PAUSE_HGI"                ,	9,	2,	400,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_11_63"              ,	11,	53,	400,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	4,	401,	"R/W",	0,	0,	6ull,	6ull},
+	{"EN"                          ,	4,	1,	401,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	401,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_SEL"                     ,	12,	2,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_GEN"                     ,	14,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"SYNCE_SEL"                   ,	15,	2,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	402,	"RAZ",	1,	1,	0,	0},
+	{"N"                           ,	0,	32,	403,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	403,	"RAZ",	1,	1,	0,	0},
+	{"LANE_SEL"                    ,	0,	2,	404,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIV"                         ,	2,	1,	404,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	404,	"RAZ",	1,	1,	0,	0},
+	{"QLM_SEL"                     ,	8,	2,	404,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	404,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	405,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	405,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	406,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	406,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	20,	407,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	407,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	20,	408,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	408,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	20,	409,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	409,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_SEL"                     ,	12,	2,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_GEN"                     ,	14,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"SYNCE_SEL"                   ,	15,	2,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	410,	"RAZ",	1,	1,	0,	0},
+	{"ICD"                         ,	0,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"IBD"                         ,	1,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP1"                       ,	2,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP0"                       ,	3,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN1"                       ,	4,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN0"                       ,	5,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ1"                       ,	6,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ0"                       ,	7,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRT"                       ,	8,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR1"                        ,	9,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR0"                        ,	10,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR1"                       ,	11,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR0"                       ,	12,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR0"                       ,	13,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR1"                       ,	14,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR1"                        ,	15,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR0"                        ,	16,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRCB"                      ,	17,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"IOCFIF"                      ,	18,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"RSDFIF"                      ,	19,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"IORFIF"                      ,	20,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"XMCFIF"                      ,	21,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"XMDFIF"                      ,	22,	1,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	411,	"RAZ",	1,	1,	0,	0},
+	{"FAU_END"                     ,	0,	1,	412,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB_ENB"                     ,	1,	1,	412,	"R/W",	0,	0,	1ull,	1ull},
+	{"PKO_ENB"                     ,	2,	1,	412,	"R/W",	0,	0,	0ull,	0ull},
+	{"INB_MAT"                     ,	3,	1,	412,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTB_MAT"                    ,	4,	1,	412,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RR_MODE"                     ,	5,	1,	412,	"R/W",	0,	0,	0ull,	0ull},
+	{"XMC_PER"                     ,	6,	4,	412,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIF_DLY"                     ,	10,	1,	412,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	412,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	413,	"RAZ",	1,	1,	0,	0},
+	{"TOUT_VAL"                    ,	0,	12,	414,	"R/W",	0,	0,	4ull,	4ull},
+	{"TOUT_ENB"                    ,	12,	1,	414,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	414,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	415,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	416,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	416,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	416,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	416,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	416,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	417,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	417,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	417,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	417,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	417,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	418,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	419,	"R/W",	0,	1,	0ull,	0},
+	{"NP_SOP"                      ,	0,	1,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	420,	"RAZ",	1,	1,	0,	0},
+	{"NP_SOP"                      ,	0,	1,	421,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	421,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	421,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	421,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	421,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	421,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	421,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	422,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	423,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	423,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	423,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	424,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	424,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	424,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	425,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	425,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	425,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	425,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	425,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	426,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	426,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	426,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	426,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	426,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	427,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	428,	"R/W",	0,	1,	0ull,	0},
+	{"CNT_VAL"                     ,	0,	15,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	429,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	430,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	431,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	6,	432,	"RO",	0,	1,	0ull,	0},
+	{"VPORT"                       ,	6,	6,	432,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	432,	"RAZ",	1,	1,	0,	0},
+	{"NCB_WR"                      ,	0,	3,	433,	"R/W",	0,	1,	0ull,	0},
+	{"NCB_RD"                      ,	3,	3,	433,	"R/W",	0,	1,	0ull,	0},
+	{"PKO_RD"                      ,	6,	3,	433,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	433,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	434,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	434,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	435,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	435,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	436,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	436,	"RAZ",	1,	1,	0,	0},
+	{"PWP"                         ,	0,	1,	437,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_NEW"                     ,	1,	1,	437,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_OLD"                     ,	2,	1,	437,	"RO",	0,	0,	0ull,	0ull},
+	{"PRC_OFF"                     ,	3,	1,	437,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ0"                        ,	4,	1,	437,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ1"                        ,	5,	1,	437,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM_WORD"                    ,	6,	1,	437,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM0"                        ,	7,	1,	437,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM1"                        ,	8,	1,	437,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM2"                        ,	9,	1,	437,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM3"                        ,	10,	1,	437,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE0"                    ,	11,	1,	437,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE1"                    ,	12,	1,	437,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_POW"                     ,	13,	1,	437,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WP1"                     ,	14,	1,	437,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WQED"                    ,	15,	1,	437,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_NCMD"                    ,	16,	1,	437,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_MEM"                     ,	17,	1,	437,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	437,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	48,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	438,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	64,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_EN"                      ,	0,	1,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC_MODE"                    ,	1,	2,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBP_EN"                      ,	3,	1,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"WQE_LEND"                    ,	4,	1,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_LEND"                    ,	5,	1,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"NADDBUF"                     ,	6,	1,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDPKT"                      ,	7,	1,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	8,	1,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_M8"                      ,	9,	1,	440,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKT_OFF"                     ,	10,	1,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_FULL"                    ,	11,	1,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_NABUF"                    ,	12,	1,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_APKT"                     ,	13,	1,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"NO_WPTR"                     ,	14,	1,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKEN"                       ,	15,	1,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"RST_DONE"                    ,	16,	1,	440,	"RO",	0,	0,	1ull,	0ull},
+	{"USE_SOP"                     ,	17,	1,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	440,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	441,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	442,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	442,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	442,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	442,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	442,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	442,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	442,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	442,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	442,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	442,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	442,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	442,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	442,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	443,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	443,	"RAZ",	1,	1,	0,	0},
+	{"MB_SIZE"                     ,	0,	12,	444,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_12_63"              ,	12,	52,	444,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	445,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	445,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	446,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	446,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	446,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	447,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	447,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	447,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	448,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	448,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	448,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	449,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	449,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	450,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	450,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	451,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	451,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	452,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	452,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	453,	"RO",	0,	1,	0ull,	0},
+	{"WMARK"                       ,	32,	32,	453,	"R/W",	0,	1,	4294967295ull,	0},
+	{"INTR"                        ,	0,	64,	454,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	64,	455,	"R/W",	0,	0,	0ull,	1ull},
+	{"RADDR"                       ,	0,	3,	456,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	3,	1,	456,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	4,	29,	456,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	33,	3,	456,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	36,	3,	456,	"RO",	0,	0,	5ull,	5ull},
+	{"RESERVED_39_63"              ,	39,	25,	456,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	7,	457,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	7,	1,	457,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	8,	29,	457,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	37,	7,	457,	"RO",	0,	0,	64ull,	64ull},
+	{"RESERVED_44_63"              ,	44,	20,	457,	"RAZ",	1,	1,	0,	0},
+	{"WQE_PCNT"                    ,	0,	7,	458,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PCNT"                    ,	7,	7,	458,	"RO",	0,	0,	0ull,	0ull},
+	{"PFIF_CNT"                    ,	14,	3,	458,	"RO",	0,	0,	0ull,	0ull},
+	{"WQEV_CNT"                    ,	17,	1,	458,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTV_CNT"                    ,	18,	1,	458,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	458,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	8,	459,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	8,	1,	459,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	9,	29,	459,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	38,	8,	459,	"RO",	1,	1,	0,	0},
+	{"WRADDR"                      ,	46,	8,	459,	"RO",	1,	1,	0,	0},
+	{"MAX_CNTS"                    ,	54,	7,	459,	"RO",	0,	0,	64ull,	64ull},
+	{"RESERVED_61_63"              ,	61,	3,	459,	"RAZ",	1,	1,	0,	0},
+	{"PASS"                        ,	0,	32,	460,	"R/W",	0,	1,	0ull,	0},
+	{"DROP"                        ,	32,	32,	460,	"R/W",	0,	1,	0ull,	0},
+	{"Q0_PCNT"                     ,	0,	32,	461,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	461,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	462,	"R/W",	0,	0,	0ull,	0ull},
+	{"AVG_DLY"                     ,	36,	14,	462,	"R/W",	0,	1,	0ull,	0},
+	{"PRB_DLY"                     ,	50,	14,	462,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRT_ENB"                     ,	0,	12,	463,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	463,	"RAZ",	1,	1,	0,	0},
+	{"PRB_CON"                     ,	0,	32,	464,	"R/W",	0,	1,	0ull,	0},
+	{"AVG_CON"                     ,	32,	8,	464,	"R/W",	0,	1,	0ull,	0},
+	{"NEW_CON"                     ,	40,	8,	464,	"R/W",	0,	1,	0ull,	0},
+	{"USE_PCNT"                    ,	48,	1,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	464,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	25,	465,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	25,	6,	465,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	465,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT"                    ,	0,	32,	466,	"R/W",	0,	0,	4294967295ull,	4294967295ull},
+	{"RESERVED_32_35"              ,	32,	4,	466,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT2"                   ,	36,	4,	466,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_40_63"              ,	40,	24,	466,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	467,	"R/W",	1,	0,	0,	0ull},
+	{"PORT_QOS"                    ,	32,	9,	467,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_41_63"              ,	41,	23,	467,	"RAZ",	1,	1,	0,	0},
+	{"WQE_POOL"                    ,	0,	3,	468,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	468,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	469,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	469,	"RAZ",	1,	1,	0,	0},
+	{"MEM0"                        ,	0,	1,	470,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM1"                        ,	1,	1,	470,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	2,	1,	470,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	470,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	471,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	471,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	471,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	472,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	472,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	472,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	472,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	472,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	473,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	473,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	473,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	473,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	473,	"RAZ",	1,	1,	0,	0},
+	{"DISABLE"                     ,	0,	1,	474,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	474,	"RAZ",	1,	1,	0,	0},
+	{"MAXDRAM"                     ,	4,	4,	474,	"R/W",	0,	0,	7ull,	7ull},
+	{"RESERVED_8_63"               ,	8,	56,	474,	"RAZ",	1,	1,	0,	0},
+	{"TDFFL"                       ,	0,	1,	475,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	475,	"RAZ",	1,	1,	0,	0},
+	{"VRTFL"                       ,	4,	1,	475,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	475,	"RAZ",	1,	1,	0,	0},
+	{"DUTRESFL"                    ,	8,	1,	475,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	475,	"RAZ",	1,	1,	0,	0},
+	{"IOCDATFL"                    ,	12,	1,	475,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	475,	"RAZ",	1,	1,	0,	0},
+	{"IOCCMDFL"                    ,	16,	1,	475,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	475,	"RAZ",	1,	1,	0,	0},
+	{"DUTFL"                       ,	32,	4,	475,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	475,	"RAZ",	1,	1,	0,	0},
+	{"VBFFL"                       ,	0,	4,	476,	"RO",	1,	0,	0,	0ull},
+	{"RDFFL"                       ,	4,	1,	476,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_5_61"               ,	5,	57,	476,	"RAZ",	1,	1,	0,	0},
+	{"CLEAR_BIST"                  ,	62,	1,	476,	"R/W",	0,	0,	0ull,	0ull},
+	{"START_BIST"                  ,	63,	1,	476,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFL"                       ,	0,	8,	477,	"RO",	1,	0,	0,	0ull},
+	{"FBFFL"                       ,	8,	8,	477,	"RO",	1,	0,	0,	0ull},
+	{"SBFFL"                       ,	16,	8,	477,	"RO",	1,	0,	0,	0ull},
+	{"FBFRSPFL"                    ,	24,	8,	477,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	477,	"RAZ",	1,	1,	0,	0},
+	{"TAGFL"                       ,	0,	16,	478,	"RO",	1,	0,	0,	0ull},
+	{"LRUFL"                       ,	16,	1,	478,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	478,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	479,	"R/W",	1,	1,	0,	0},
+	{"DISIDXALIAS"                 ,	0,	1,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISECC"                      ,	1,	1,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"VAB_THRESH"                  ,	2,	4,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"EF_CNT"                      ,	6,	7,	480,	"R/W",	0,	0,	0ull,	4ull},
+	{"EF_ENA"                      ,	13,	1,	480,	"R/W",	0,	0,	0ull,	1ull},
+	{"XMC_ARB_MODE"                ,	14,	1,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSP_ARB_MODE"                ,	15,	1,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXLFB"                      ,	16,	4,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXVAB"                      ,	20,	4,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISCCLK"                     ,	24,	1,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFDBE"                     ,	25,	1,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFSBE"                     ,	26,	1,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISSTGL2I"                   ,	27,	1,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDF_FAST"                    ,	28,	1,	480,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_29_63"              ,	29,	35,	480,	"RAZ",	1,	1,	0,	0},
+	{"VALID"                       ,	0,	1,	481,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_9"                ,	1,	9,	481,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	10,	28,	481,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	481,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	2,	482,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	482,	"RAZ",	1,	1,	0,	0},
+	{"WAYIDX"                      ,	4,	16,	482,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_20_49"              ,	20,	30,	482,	"RAZ",	1,	1,	0,	0},
+	{"SYN"                         ,	50,	10,	482,	"RO",	0,	0,	0ull,	0ull},
+	{"VSBE"                        ,	60,	1,	482,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VDBE"                        ,	61,	1,	482,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE"                         ,	62,	1,	482,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	63,	1,	482,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TYPE"                        ,	0,	2,	483,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_6"                ,	2,	5,	483,	"RAZ",	1,	1,	0,	0},
+	{"WAYIDX"                      ,	7,	13,	483,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_20_49"              ,	20,	30,	483,	"RAZ",	1,	1,	0,	0},
+	{"SYN"                         ,	50,	6,	483,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_60"              ,	56,	5,	483,	"RAZ",	1,	1,	0,	0},
+	{"NOWAY"                       ,	61,	1,	483,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE"                         ,	62,	1,	483,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	63,	1,	483,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TYPE"                        ,	0,	2,	484,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_49"               ,	2,	48,	484,	"RAZ",	1,	1,	0,	0},
+	{"VSYN"                        ,	50,	10,	484,	"RO",	0,	0,	0ull,	0ull},
+	{"VSBE"                        ,	60,	1,	484,	"RO",	0,	0,	0ull,	0ull},
+	{"VDBE"                        ,	61,	1,	484,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	484,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	38,	485,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_47"              ,	38,	10,	485,	"RAZ",	1,	1,	0,	0},
+	{"SID"                         ,	48,	4,	485,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_57"              ,	52,	6,	485,	"RAZ",	1,	1,	0,	0},
+	{"CMD"                         ,	58,	6,	485,	"RO",	0,	1,	0ull,	0},
+	{"HOLERD"                      ,	0,	1,	486,	"R/W",	0,	0,	0ull,	1ull},
+	{"HOLEWR"                      ,	1,	1,	486,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTWR"                       ,	2,	1,	486,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTIDRNG"                    ,	3,	1,	486,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTADRNG"                    ,	4,	1,	486,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTPE"                       ,	5,	1,	486,	"R/W",	0,	0,	0ull,	1ull},
+	{"BIGWR"                       ,	6,	1,	486,	"R/W",	0,	0,	0ull,	1ull},
+	{"BIGRD"                       ,	7,	1,	486,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_8_63"               ,	8,	56,	486,	"RAZ",	1,	1,	0,	0},
+	{"HOLERD"                      ,	0,	1,	487,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HOLEWR"                      ,	1,	1,	487,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTWR"                       ,	2,	1,	487,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTIDRNG"                    ,	3,	1,	487,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTADRNG"                    ,	4,	1,	487,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTPE"                       ,	5,	1,	487,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BIGWR"                       ,	6,	1,	487,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BIGRD"                       ,	7,	1,	487,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	487,	"RAZ",	1,	1,	0,	0},
+	{"TAD0"                        ,	16,	1,	487,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	487,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	488,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	489,	"R/W",	0,	1,	0ull,	0},
+	{"LVL"                         ,	0,	2,	490,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	490,	"RAZ",	1,	1,	0,	0},
+	{"DWBLVL"                      ,	4,	2,	490,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	490,	"RAZ",	1,	1,	0,	0},
+	{"LVL"                         ,	0,	2,	491,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	491,	"RAZ",	1,	1,	0,	0},
+	{"WGT0"                        ,	0,	8,	492,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT1"                        ,	8,	8,	492,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT2"                        ,	16,	8,	492,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT3"                        ,	24,	8,	492,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_32_63"              ,	32,	32,	492,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	493,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	494,	"R/W",	0,	1,	0ull,	0},
+	{"OW0ECC"                      ,	0,	10,	495,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	495,	"RAZ",	1,	1,	0,	0},
+	{"OW1ECC"                      ,	16,	10,	495,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_31"              ,	26,	6,	495,	"RAZ",	1,	1,	0,	0},
+	{"OW2ECC"                      ,	32,	10,	495,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	495,	"RAZ",	1,	1,	0,	0},
+	{"OW3ECC"                      ,	48,	10,	495,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	495,	"RAZ",	1,	1,	0,	0},
+	{"OW4ECC"                      ,	0,	10,	496,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	496,	"RAZ",	1,	1,	0,	0},
+	{"OW5ECC"                      ,	16,	10,	496,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_31"              ,	26,	6,	496,	"RAZ",	1,	1,	0,	0},
+	{"OW6ECC"                      ,	32,	10,	496,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	496,	"RAZ",	1,	1,	0,	0},
+	{"OW7ECC"                      ,	48,	10,	496,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	496,	"RAZ",	1,	1,	0,	0},
+	{"L2DSBE"                      ,	0,	1,	497,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2DDBE"                      ,	1,	1,	497,	"R/W",	0,	0,	0ull,	1ull},
+	{"TAGSBE"                      ,	2,	1,	497,	"R/W",	0,	0,	0ull,	1ull},
+	{"TAGDBE"                      ,	3,	1,	497,	"R/W",	0,	0,	0ull,	1ull},
+	{"VBFSBE"                      ,	4,	1,	497,	"R/W",	0,	0,	0ull,	1ull},
+	{"VBFDBE"                      ,	5,	1,	497,	"R/W",	0,	0,	0ull,	1ull},
+	{"NOWAY"                       ,	6,	1,	497,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDDISLMC"                    ,	7,	1,	497,	"R/W",	0,	0,	0ull,	1ull},
+	{"WRDISLMC"                    ,	8,	1,	497,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	497,	"RAZ",	1,	1,	0,	0},
+	{"L2DSBE"                      ,	0,	1,	498,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"L2DDBE"                      ,	1,	1,	498,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"TAGSBE"                      ,	2,	1,	498,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"TAGDBE"                      ,	3,	1,	498,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"VBFSBE"                      ,	4,	1,	498,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"VBFDBE"                      ,	5,	1,	498,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"NOWAY"                       ,	6,	1,	498,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDDISLMC"                    ,	7,	1,	498,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WRDISLMC"                    ,	8,	1,	498,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	498,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	499,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	500,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	501,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	502,	"R/W",	0,	1,	0ull,	0},
+	{"CNT0SEL"                     ,	0,	8,	503,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT1SEL"                     ,	8,	8,	503,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT2SEL"                     ,	16,	8,	503,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT3SEL"                     ,	24,	8,	503,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	503,	"RAZ",	1,	1,	0,	0},
+	{"LOCK"                        ,	0,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIRTY"                       ,	1,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"VALID"                       ,	2,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE"                         ,	3,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_16"               ,	4,	13,	504,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	17,	19,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_39"              ,	36,	4,	504,	"RAZ",	1,	1,	0,	0},
+	{"ECC"                         ,	40,	6,	504,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_46_63"              ,	46,	18,	504,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	505,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MASK"                        ,	0,	1,	506,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	506,	"RAZ",	1,	1,	0,	0},
+	{"DWB"                         ,	0,	1,	507,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	1,	1,	507,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	507,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	4,	508,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	508,	"RAZ",	1,	1,	0,	0},
+	{"ID"                          ,	0,	6,	509,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	509,	"RAZ",	1,	1,	0,	0},
+	{"DWBID"                       ,	8,	6,	509,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	509,	"RAZ",	1,	1,	0,	0},
+	{"ID"                          ,	0,	6,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	510,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	1,	511,	"R/W",	0,	0,	0ull,	1ull},
+	{"NUMID"                       ,	1,	3,	511,	"R/W",	0,	0,	5ull,	5ull},
+	{"MEMSZ"                       ,	4,	3,	511,	"R/W",	0,	0,	5ull,	5ull},
+	{"RESERVED_7_7"                ,	7,	1,	511,	"RAZ",	1,	1,	0,	0},
+	{"OOBERR"                      ,	8,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	511,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	32,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"PARITY"                      ,	32,	4,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	512,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	513,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	514,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	515,	"R/W",	0,	1,	0ull,	0},
+	{"ADDR"                        ,	0,	38,	516,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_38_56"              ,	38,	19,	516,	"RAZ",	1,	1,	0,	0},
+	{"CMD"                         ,	57,	6,	516,	"R/W",	1,	1,	0,	0},
+	{"INUSE"                       ,	63,	1,	516,	"RO",	0,	0,	0ull,	0ull},
+	{"COUNT"                       ,	0,	64,	517,	"R/W",	0,	1,	0ull,	0},
+	{"PRBS"                        ,	0,	32,	518,	"R/W",	1,	1,	0,	0},
+	{"PROG"                        ,	32,	8,	518,	"R/W",	1,	1,	0,	0},
+	{"SEL"                         ,	40,	1,	518,	"R/W",	1,	1,	0,	0},
+	{"EN"                          ,	41,	1,	518,	"R/W",	1,	1,	0,	0},
+	{"SKEW_ON"                     ,	42,	1,	518,	"R/W",	1,	1,	0,	0},
+	{"DR"                          ,	43,	1,	518,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_44_63"              ,	44,	20,	518,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	519,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	8,	520,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	520,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	521,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	8,	522,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	522,	"R/W",	1,	1,	0,	0},
+	{"CKE_MASK"                    ,	0,	2,	523,	"R/W",	1,	1,	0,	0},
+	{"CS0_N_MASK"                  ,	2,	2,	523,	"R/W",	1,	1,	0,	0},
+	{"CS1_N_MASK"                  ,	4,	2,	523,	"R/W",	1,	1,	0,	0},
+	{"ODT0_MASK"                   ,	6,	2,	523,	"R/W",	1,	1,	0,	0},
+	{"ODT1_MASK"                   ,	8,	2,	523,	"R/W",	1,	1,	0,	0},
+	{"RAS_N_MASK"                  ,	10,	1,	523,	"R/W",	1,	1,	0,	0},
+	{"CAS_N_MASK"                  ,	11,	1,	523,	"R/W",	1,	1,	0,	0},
+	{"WE_N_MASK"                   ,	12,	1,	523,	"R/W",	1,	1,	0,	0},
+	{"BA_MASK"                     ,	13,	3,	523,	"R/W",	1,	1,	0,	0},
+	{"A_MASK"                      ,	16,	16,	523,	"R/W",	1,	1,	0,	0},
+	{"RESET_N_MASK"                ,	32,	1,	523,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_33_63"              ,	33,	31,	523,	"R/W",	1,	1,	0,	0},
+	{"DQX_CTL"                     ,	0,	4,	524,	"R/W",	0,	1,	4ull,	0},
+	{"CK_CTL"                      ,	4,	4,	524,	"R/W",	0,	1,	4ull,	0},
+	{"CMD_CTL"                     ,	8,	4,	524,	"R/W",	0,	1,	4ull,	0},
+	{"RODT_CTL"                    ,	12,	4,	524,	"R/W",	0,	1,	0ull,	0},
+	{"NTUNE"                       ,	16,	4,	524,	"R/W",	0,	1,	0ull,	0},
+	{"PTUNE"                       ,	20,	4,	524,	"R/W",	0,	1,	0ull,	0},
+	{"BYP"                         ,	24,	1,	524,	"R/W",	0,	1,	0ull,	0},
+	{"M180"                        ,	25,	1,	524,	"R/W",	0,	1,	0ull,	0},
+	{"DDR__NTUNE"                  ,	26,	4,	524,	"RO",	1,	1,	0,	0},
+	{"DDR__PTUNE"                  ,	30,	4,	524,	"RO",	1,	1,	0,	0},
+	{"RESERVED_34_63"              ,	34,	30,	524,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	525,	"WR0",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	525,	"R/W",	0,	0,	0ull,	1ull},
+	{"ROW_LSB"                     ,	2,	3,	525,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	525,	"R/W",	0,	1,	5ull,	0},
+	{"IDLEPOWER"                   ,	9,	3,	525,	"R/W",	0,	0,	0ull,	6ull},
+	{"FORCEWRITE"                  ,	12,	4,	525,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ADR"                     ,	16,	1,	525,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESET"                       ,	17,	1,	525,	"R/W",	0,	1,	0ull,	0},
+	{"REF_ZQCS_INT"                ,	18,	19,	525,	"R/W",	1,	1,	0,	0},
+	{"SEQUENCE"                    ,	37,	3,	525,	"R/W",	0,	0,	0ull,	0ull},
+	{"EARLY_DQX"                   ,	40,	1,	525,	"R/W",	0,	0,	0ull,	0ull},
+	{"SREF_WITH_DLL"               ,	41,	1,	525,	"R/W",	0,	0,	0ull,	0ull},
+	{"RANK_ENA"                    ,	42,	1,	525,	"R/W",	0,	1,	0ull,	0},
+	{"RANKMASK"                    ,	43,	4,	525,	"R/W",	0,	1,	0ull,	0},
+	{"MIRRMASK"                    ,	47,	4,	525,	"R/W",	0,	1,	0ull,	0},
+	{"INIT_STATUS"                 ,	51,	4,	525,	"R/W1",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D0_R0"          ,	55,	1,	525,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D0_R1"          ,	56,	1,	525,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D1_R0"          ,	57,	1,	525,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D1_R1"          ,	58,	1,	525,	"R/W",	0,	1,	0ull,	0},
+	{"SCRZ"                        ,	59,	1,	525,	"R/W1",	0,	1,	0ull,	0},
+	{"MODE32B"                     ,	60,	1,	525,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	525,	"RAZ",	1,	1,	0,	0},
+	{"RDIMM_ENA"                   ,	0,	1,	526,	"R/W",	0,	1,	0ull,	0},
+	{"BWCNT"                       ,	1,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	2,	1,	526,	"R/W",	0,	0,	0ull,	1ull},
+	{"POCAS"                       ,	3,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPRCH2"                      ,	4,	2,	526,	"R/W",	0,	0,	0ull,	1ull},
+	{"THROTTLE_RD"                 ,	6,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"THROTTLE_WR"                 ,	7,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_RD"                  ,	8,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_WR"                  ,	9,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"ELEV_PRIO_DIS"               ,	10,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"NXM_WRITE_EN"                ,	11,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	12,	4,	526,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	16,	1,	526,	"R/W",	0,	0,	0ull,	1ull},
+	{"AUTO_DCLKDIS"                ,	17,	1,	526,	"R/W",	0,	0,	0ull,	1ull},
+	{"INT_ZQCS_DIS"                ,	18,	1,	526,	"R/W",	0,	0,	1ull,	0ull},
+	{"EXT_ZQCS_DIS"                ,	19,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"BPRCH"                       ,	20,	2,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"WODT_BPRCH"                  ,	22,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_BPRCH"                  ,	23,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_62"              ,	24,	39,	526,	"RAZ",	1,	1,	0,	0},
+	{"SCRAMBLE_ENA"                ,	63,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCLKCNT"                     ,	0,	64,	527,	"RO",	0,	1,	0ull,	0},
+	{"CLKF"                        ,	0,	7,	528,	"R/W",	0,	1,	48ull,	0},
+	{"RESET_N"                     ,	7,	1,	528,	"R/W",	0,	0,	0ull,	1ull},
+	{"CPB"                         ,	8,	3,	528,	"R/W",	0,	0,	0ull,	1ull},
+	{"CPS"                         ,	11,	3,	528,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIFFAMP"                     ,	14,	4,	528,	"R/W",	0,	0,	0ull,	1ull},
+	{"DDR_PS_EN"                   ,	18,	3,	528,	"R/W",	0,	1,	2ull,	0},
+	{"DDR_DIV_RESET"               ,	21,	1,	528,	"R/W",	0,	0,	1ull,	0ull},
+	{"DFM_PS_EN"                   ,	22,	3,	528,	"R/W",	0,	1,	2ull,	0},
+	{"DFM_DIV_RESET"               ,	25,	1,	528,	"R/W",	0,	0,	1ull,	0ull},
+	{"JTG_TEST_MODE"               ,	26,	1,	528,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	528,	"RAZ",	1,	1,	0,	0},
+	{"RC0"                         ,	0,	4,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC1"                         ,	4,	4,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC2"                         ,	8,	4,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC3"                         ,	12,	4,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC4"                         ,	16,	4,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC5"                         ,	20,	4,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC6"                         ,	24,	4,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC7"                         ,	28,	4,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC8"                         ,	32,	4,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC9"                         ,	36,	4,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC10"                        ,	40,	4,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC11"                        ,	44,	4,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC12"                        ,	48,	4,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC13"                        ,	52,	4,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC14"                        ,	56,	4,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC15"                        ,	60,	4,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIMM0_WMASK"                 ,	0,	16,	530,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"DIMM1_WMASK"                 ,	16,	16,	530,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"TCWS"                        ,	32,	13,	530,	"R/W",	0,	0,	1248ull,	1248ull},
+	{"PARITY"                      ,	45,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	530,	"RAZ",	1,	1,	0,	0},
+	{"BYP_SETTING"                 ,	0,	8,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYP_SEL"                     ,	8,	4,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"QUAD_DLL_ENA"                ,	12,	1,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	13,	1,	531,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLL_BRINGUP"                 ,	14,	1,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTF_EN"                     ,	15,	1,	531,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	531,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	6,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYTE_SEL"                    ,	6,	4,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE_SEL"                    ,	10,	2,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOAD_OFFSET"                 ,	12,	1,	532,	"WR0",	0,	0,	0ull,	0ull},
+	{"OFFSET_ENA"                  ,	13,	1,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYTE_SEL"              ,	14,	4,	532,	"R/W",	0,	0,	1ull,	1ull},
+	{"DLL_MODE"                    ,	18,	1,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINE_TUNE_MODE"              ,	19,	1,	532,	"R/W",	0,	0,	0ull,	1ull},
+	{"DLL90_SETTING"               ,	20,	8,	532,	"RO",	1,	1,	0,	0},
+	{"DLL_FAST"                    ,	28,	1,	532,	"RO",	1,	1,	0,	0},
+	{"DCLK90_BYP_SETTING"          ,	29,	8,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCLK90_BYP_SEL"              ,	37,	1,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCLK90_RECAL_DIS"            ,	38,	1,	532,	"R/W",	0,	0,	0ull,	1ull},
+	{"DDR_90_DLY_BYP"              ,	39,	1,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCLK90_FWD"                  ,	40,	1,	532,	"WR0",	0,	0,	0ull,	0ull},
+	{"RESERVED_41_63"              ,	41,	23,	532,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	533,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	533,	"RAZ",	1,	1,	0,	0},
+	{"ROW_LSB"                     ,	16,	3,	533,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_19_63"              ,	19,	45,	533,	"RAZ",	1,	1,	0,	0},
+	{"MRDSYN0"                     ,	0,	8,	534,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN1"                     ,	8,	8,	534,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN2"                     ,	16,	8,	534,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN3"                     ,	24,	8,	534,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	534,	"RAZ",	1,	1,	0,	0},
+	{"FCOL"                        ,	0,	14,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	14,	16,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	30,	3,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	33,	1,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	34,	2,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	535,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT"                      ,	0,	64,	536,	"RO",	0,	1,	1ull,	0},
+	{"NXM_WR_ERR"                  ,	0,	1,	537,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SEC_ERR"                     ,	1,	4,	537,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	5,	4,	537,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	537,	"RAZ",	1,	1,	0,	0},
+	{"INTR_NXM_WR_ENA"             ,	0,	1,	538,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_SEC_ENA"                ,	1,	1,	538,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_DED_ENA"                ,	2,	1,	538,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	538,	"RAZ",	1,	1,	0,	0},
+	{"CWL"                         ,	0,	3,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPRLOC"                      ,	3,	2,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPR"                         ,	5,	1,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL"                         ,	6,	1,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"AL"                          ,	7,	2,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"WLEV"                        ,	9,	1,	539,	"RO",	0,	0,	0ull,	0ull},
+	{"TDQS"                        ,	10,	1,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOFF"                        ,	11,	1,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"BL"                          ,	12,	2,	539,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	14,	4,	539,	"R/W",	0,	0,	2ull,	2ull},
+	{"RBT"                         ,	18,	1,	539,	"RO",	0,	0,	1ull,	1ull},
+	{"TM"                          ,	19,	1,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLR"                        ,	20,	1,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRP"                         ,	21,	3,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPD"                         ,	24,	1,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	539,	"RAZ",	1,	1,	0,	0},
+	{"PASR_00"                     ,	0,	3,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_00"                      ,	3,	1,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_00"                      ,	4,	1,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_00"                   ,	5,	2,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_00"                      ,	7,	2,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_00"                  ,	9,	3,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_01"                     ,	12,	3,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_01"                      ,	15,	1,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_01"                      ,	16,	1,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_01"                   ,	17,	2,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_01"                      ,	19,	2,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_01"                  ,	21,	3,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_10"                     ,	24,	3,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_10"                      ,	27,	1,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_10"                      ,	28,	1,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_10"                   ,	29,	2,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_10"                      ,	31,	2,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_10"                  ,	33,	3,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_11"                     ,	36,	3,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_11"                      ,	39,	1,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_11"                      ,	40,	1,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_11"                   ,	41,	2,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_11"                      ,	43,	2,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_11"                  ,	45,	3,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	540,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	541,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D0_R0"               ,	8,	4,	541,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D0_R1"               ,	12,	4,	541,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D1_R0"               ,	16,	4,	541,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D1_R1"               ,	20,	4,	541,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D2_R0"               ,	24,	4,	541,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D2_R1"               ,	28,	4,	541,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D3_R0"               ,	32,	4,	541,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D3_R1"               ,	36,	4,	541,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	541,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT"                      ,	0,	64,	542,	"RO",	0,	1,	1ull,	0},
+	{"TS_STAGGER"                  ,	0,	1,	543,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK_POS"                ,	1,	1,	543,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK"                    ,	2,	1,	543,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT0"                  ,	3,	4,	543,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE0"                    ,	7,	1,	543,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT1"                  ,	8,	4,	543,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE1"                    ,	12,	1,	543,	"R/W",	0,	1,	0ull,	0},
+	{"LV_MODE"                     ,	13,	1,	543,	"R/W",	0,	1,	0ull,	0},
+	{"RX_ALWAYS_ON"                ,	14,	1,	543,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	543,	"RAZ",	1,	1,	0,	0},
+	{"DDR3RST"                     ,	0,	1,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PWARM"                   ,	1,	1,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSOFT"                   ,	2,	1,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSV"                     ,	3,	1,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	544,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	545,	"R/W",	0,	1,	0ull,	0},
+	{"OFFSET"                      ,	4,	4,	545,	"R/W",	0,	0,	2ull,	2ull},
+	{"OFFSET_EN"                   ,	8,	1,	545,	"R/W",	0,	0,	1ull,	1ull},
+	{"OR_DIS"                      ,	9,	1,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	10,	8,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_0"              ,	18,	1,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_1"              ,	19,	1,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_2"              ,	20,	1,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_3"              ,	21,	1,	545,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	545,	"RAZ",	1,	1,	0,	0},
+	{"BITMASK"                     ,	0,	64,	546,	"RO",	0,	0,	0ull,	0ull},
+	{"BYTE0"                       ,	0,	6,	547,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	6,	6,	547,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE2"                       ,	12,	6,	547,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE3"                       ,	18,	6,	547,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE4"                       ,	24,	6,	547,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE5"                       ,	30,	6,	547,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE6"                       ,	36,	6,	547,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE7"                       ,	42,	6,	547,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE8"                       ,	48,	6,	547,	"R/W",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	54,	2,	547,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	547,	"RAZ",	1,	1,	0,	0},
+	{"RODT_D0_R0"                  ,	0,	8,	548,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D0_R1"                  ,	8,	8,	548,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D1_R0"                  ,	16,	8,	548,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D1_R1"                  ,	24,	8,	548,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D2_R0"                  ,	32,	8,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D2_R1"                  ,	40,	8,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R0"                  ,	48,	8,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R1"                  ,	56,	8,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	0,	64,	549,	"R/W",	0,	1,	0ull,	0},
+	{"KEY"                         ,	0,	64,	550,	"R/W",	0,	1,	0ull,	0},
+	{"FCOL"                        ,	0,	14,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	14,	16,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	30,	3,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	33,	1,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	34,	2,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	551,	"RAZ",	1,	1,	0,	0},
+	{"R2R_INIT"                    ,	0,	6,	552,	"R/W",	0,	1,	1ull,	0},
+	{"R2W_INIT"                    ,	6,	6,	552,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_INIT"                    ,	12,	6,	552,	"R/W",	0,	1,	9ull,	0},
+	{"W2W_INIT"                    ,	18,	6,	552,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	552,	"RAZ",	1,	1,	0,	0},
+	{"R2R_XRANK_INIT"              ,	0,	6,	553,	"R/W",	0,	1,	3ull,	0},
+	{"R2W_XRANK_INIT"              ,	6,	6,	553,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_XRANK_INIT"              ,	12,	6,	553,	"R/W",	0,	1,	4ull,	0},
+	{"W2W_XRANK_INIT"              ,	18,	6,	553,	"R/W",	0,	1,	5ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	553,	"RAZ",	1,	1,	0,	0},
+	{"R2R_XDIMM_INIT"              ,	0,	6,	554,	"R/W",	0,	1,	4ull,	0},
+	{"R2W_XDIMM_INIT"              ,	6,	6,	554,	"R/W",	0,	1,	7ull,	0},
+	{"W2R_XDIMM_INIT"              ,	12,	6,	554,	"R/W",	0,	1,	4ull,	0},
+	{"W2W_XDIMM_INIT"              ,	18,	6,	554,	"R/W",	0,	1,	6ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	554,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_9"                ,	0,	10,	555,	"RAZ",	1,	1,	0,	0},
+	{"TZQCS"                       ,	10,	4,	555,	"R/W",	0,	0,	4ull,	4ull},
+	{"TCKE"                        ,	14,	4,	555,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPR"                        ,	18,	4,	555,	"R/W",	0,	0,	5ull,	5ull},
+	{"TMRD"                        ,	22,	4,	555,	"R/W",	0,	0,	4ull,	4ull},
+	{"TMOD"                        ,	26,	4,	555,	"R/W",	0,	0,	12ull,	12ull},
+	{"TDLLK"                       ,	30,	4,	555,	"R/W",	0,	0,	2ull,	2ull},
+	{"TZQINIT"                     ,	34,	4,	555,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	38,	4,	555,	"R/W",	0,	0,	6ull,	6ull},
+	{"TCKSRE"                      ,	42,	4,	555,	"R/W",	0,	0,	5ull,	5ull},
+	{"TRP_EXT"                     ,	46,	1,	555,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	555,	"RAZ",	1,	1,	0,	0},
+	{"TMPRR"                       ,	0,	4,	556,	"R/W",	0,	0,	1ull,	1ull},
+	{"TRAS"                        ,	4,	5,	556,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	9,	4,	556,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	13,	4,	556,	"R/W",	0,	0,	2ull,	3ull},
+	{"TRFC"                        ,	17,	5,	556,	"R/W",	0,	0,	6ull,	7ull},
+	{"TRRD"                        ,	22,	3,	556,	"R/W",	0,	0,	2ull,	2ull},
+	{"TXP"                         ,	25,	3,	556,	"R/W",	0,	0,	3ull,	3ull},
+	{"TWLMRD"                      ,	28,	4,	556,	"R/W",	0,	0,	10ull,	10ull},
+	{"TWLDQSEN"                    ,	32,	4,	556,	"R/W",	0,	0,	7ull,	7ull},
+	{"TFAW"                        ,	36,	5,	556,	"R/W",	0,	0,	0ull,	9ull},
+	{"TXPDLL"                      ,	41,	5,	556,	"R/W",	0,	0,	0ull,	10ull},
+	{"TRAS_EXT"                    ,	46,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	556,	"RAZ",	1,	1,	0,	0},
+	{"TRESET"                      ,	0,	1,	557,	"R/W",	0,	1,	1ull,	0},
+	{"RCLK_CNT"                    ,	1,	32,	557,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	557,	"RAZ",	1,	1,	0,	0},
+	{"RING_CNT"                    ,	0,	32,	558,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	558,	"RAZ",	1,	1,	0,	0},
+	{"LANEMASK"                    ,	0,	9,	559,	"R/W",	0,	1,	0ull,	0},
+	{"SSET"                        ,	9,	1,	559,	"R/W",	0,	1,	0ull,	0},
+	{"OR_DIS"                      ,	10,	1,	559,	"R/W",	0,	1,	0ull,	0},
+	{"BITMASK"                     ,	11,	8,	559,	"R/W",	0,	1,	0ull,	0},
+	{"RTT_NOM"                     ,	19,	3,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	559,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	4,	8,	560,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	560,	"RAZ",	1,	1,	0,	0},
+	{"BYTE0"                       ,	0,	5,	561,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	5,	5,	561,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE2"                       ,	10,	5,	561,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE3"                       ,	15,	5,	561,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE4"                       ,	20,	5,	561,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE5"                       ,	25,	5,	561,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE6"                       ,	30,	5,	561,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE7"                       ,	35,	5,	561,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE8"                       ,	40,	5,	561,	"R/W",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	45,	2,	561,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_47_63"              ,	47,	17,	561,	"RAZ",	1,	1,	0,	0},
+	{"WODT_D0_R0"                  ,	0,	8,	562,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D0_R1"                  ,	8,	8,	562,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D1_R0"                  ,	16,	8,	562,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D1_R1"                  ,	24,	8,	562,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D2_R0"                  ,	32,	8,	562,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D2_R1"                  ,	40,	8,	562,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D3_R0"                  ,	48,	8,	562,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D3_R1"                  ,	56,	8,	562,	"R/W",	0,	0,	255ull,	0ull},
+	{"STAT"                        ,	0,	12,	563,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	563,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	564,	"R/W",	1,	1,	0,	0},
+	{"PCTL"                        ,	6,	6,	564,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	564,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	565,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	565,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	565,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	565,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	565,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	565,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	565,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	565,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	565,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	565,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	566,	"R/W1C",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	566,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	566,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	567,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	567,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	567,	"RAZ",	1,	1,	0,	0},
+	{"DMARQ"                       ,	0,	6,	568,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_S"                     ,	6,	6,	568,	"R/W",	0,	1,	63ull,	0},
+	{"OE_A"                        ,	12,	6,	568,	"R/W",	0,	1,	63ull,	0},
+	{"OE_N"                        ,	18,	6,	568,	"R/W",	0,	1,	63ull,	0},
+	{"WE_A"                        ,	24,	6,	568,	"R/W",	0,	1,	63ull,	0},
+	{"WE_N"                        ,	30,	6,	568,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_H"                     ,	36,	6,	568,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	42,	6,	568,	"R/W",	0,	1,	63ull,	0},
+	{"RESERVED_48_54"              ,	48,	7,	568,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	55,	1,	568,	"R/W",	0,	1,	0ull,	0},
+	{"DDR"                         ,	56,	1,	568,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	57,	3,	568,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	60,	2,	568,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ_PI"                    ,	62,	1,	568,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK_PI"                    ,	63,	1,	568,	"R/W",	0,	1,	0ull,	0},
+	{"ADR_ERR"                     ,	0,	1,	569,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WAIT_ERR"                    ,	1,	1,	569,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	569,	"RAZ",	1,	1,	0,	0},
+	{"ADR_INT"                     ,	0,	1,	570,	"R/W",	0,	1,	0ull,	0},
+	{"WAIT_INT"                    ,	1,	1,	570,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	570,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	571,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	3,	5,	571,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	571,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	572,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	3,	25,	572,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_30"              ,	28,	3,	572,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	31,	1,	572,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	572,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	573,	"R/W",	1,	1,	0,	0},
+	{"USER0"                       ,	0,	8,	574,	"RO",	1,	1,	0,	0},
+	{"NAND"                        ,	8,	1,	574,	"RO",	1,	1,	0,	0},
+	{"TERM"                        ,	9,	2,	574,	"RO",	1,	1,	0,	0},
+	{"DMACK_P0"                    ,	11,	1,	574,	"RO",	1,	1,	0,	0},
+	{"DMACK_P1"                    ,	12,	1,	574,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_13"              ,	13,	1,	574,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	14,	1,	574,	"RO",	1,	1,	0,	0},
+	{"ALE"                         ,	15,	1,	574,	"RO",	1,	1,	0,	0},
+	{"USER1"                       ,	16,	16,	574,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	574,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	16,	575,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	16,	12,	575,	"R/W",	0,	1,	0ull,	0},
+	{"WIDTH"                       ,	28,	1,	575,	"R/W",	0,	1,	0ull,	0},
+	{"ALE"                         ,	29,	1,	575,	"R/W",	0,	1,	0ull,	0},
+	{"ORBIT"                       ,	30,	1,	575,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	31,	1,	575,	"R/W",	0,	1,	0ull,	0},
+	{"OE_EXT"                      ,	32,	2,	575,	"R/W",	0,	1,	0ull,	0},
+	{"WE_EXT"                      ,	34,	2,	575,	"R/W",	0,	1,	0ull,	0},
+	{"SAM"                         ,	36,	1,	575,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	37,	3,	575,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	40,	2,	575,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK"                       ,	42,	2,	575,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	575,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	6,	576,	"R/W",	0,	1,	63ull,	0},
+	{"CE"                          ,	6,	6,	576,	"R/W",	0,	1,	63ull,	0},
+	{"OE"                          ,	12,	6,	576,	"R/W",	0,	1,	63ull,	0},
+	{"WE"                          ,	18,	6,	576,	"R/W",	0,	1,	63ull,	0},
+	{"RD_HLD"                      ,	24,	6,	576,	"R/W",	0,	1,	63ull,	0},
+	{"WR_HLD"                      ,	30,	6,	576,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	36,	6,	576,	"R/W",	0,	1,	63ull,	0},
+	{"WAIT"                        ,	42,	6,	576,	"R/W",	0,	1,	63ull,	0},
+	{"PAGE"                        ,	48,	6,	576,	"R/W",	0,	1,	63ull,	0},
+	{"ALE"                         ,	54,	6,	576,	"R/W",	0,	1,	63ull,	0},
+	{"PAGES"                       ,	60,	2,	576,	"R/W",	0,	1,	0ull,	0},
+	{"WAITM"                       ,	62,	1,	576,	"R/W",	0,	1,	0ull,	0},
+	{"PAGEM"                       ,	63,	1,	576,	"R/W",	0,	1,	0ull,	0},
+	{"FIF_THR"                     ,	0,	6,	577,	"R/W",	0,	0,	25ull,	25ull},
+	{"RESERVED_6_7"                ,	6,	2,	577,	"RAZ",	1,	1,	0,	0},
+	{"FIF_CNT"                     ,	8,	6,	577,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	577,	"RAZ",	1,	1,	0,	0},
+	{"DMA_THR"                     ,	16,	6,	577,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_63"              ,	22,	42,	577,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	578,	"R/W",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	6,	579,	"R/W",	0,	1,	0ull,	0},
+	{"BUF_NUM"                     ,	6,	1,	579,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_15"               ,	7,	9,	579,	"RAZ",	0,	1,	0ull,	0},
+	{"INC"                         ,	16,	1,	579,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	579,	"RAZ",	0,	1,	0ull,	0},
+	{"BUS_ENA"                     ,	0,	4,	580,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_15"               ,	4,	12,	580,	"RAZ",	0,	1,	0ull,	0},
+	{"BOOT_FAIL"                   ,	16,	1,	580,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	580,	"RAZ",	0,	1,	0ull,	0},
+	{"ARG"                         ,	0,	32,	581,	"R/W",	0,	1,	0ull,	0},
+	{"CMD_IDX"                     ,	32,	6,	581,	"R/W",	0,	1,	0ull,	0},
+	{"RTYPE_XOR"                   ,	38,	3,	581,	"R/W",	0,	1,	0ull,	0},
+	{"CTYPE_XOR"                   ,	41,	2,	581,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_43_48"              ,	43,	6,	581,	"RAZ",	0,	1,	0ull,	0},
+	{"OFFSET"                      ,	49,	6,	581,	"R/W",	0,	1,	0ull,	0},
+	{"DBUF"                        ,	55,	1,	581,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_56_58"              ,	56,	3,	581,	"RAZ",	0,	1,	0ull,	0},
+	{"CMD_VAL"                     ,	59,	1,	581,	"R/W",	1,	1,	0,	0},
+	{"BUS_ID"                      ,	60,	2,	581,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	581,	"RAZ",	0,	1,	0ull,	0},
+	{"CARD_ADDR"                   ,	0,	32,	582,	"R/W",	0,	1,	0ull,	0},
+	{"BLOCK_CNT"                   ,	32,	16,	582,	"R/W",	0,	1,	0ull,	0},
+	{"MULTI"                       ,	48,	1,	582,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	49,	1,	582,	"R/W",	0,	1,	0ull,	0},
+	{"REL_WR"                      ,	50,	1,	582,	"R/W",	0,	1,	0ull,	0},
+	{"THRES"                       ,	51,	6,	582,	"R/W",	0,	1,	0ull,	0},
+	{"DAT_NULL"                    ,	57,	1,	582,	"R/W",	0,	1,	0ull,	0},
+	{"SECTOR"                      ,	58,	1,	582,	"R/W",	0,	1,	0ull,	0},
+	{"DMA_VAL"                     ,	59,	1,	582,	"R/W",	0,	1,	0ull,	0},
+	{"BUS_ID"                      ,	60,	2,	582,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	582,	"RAZ",	0,	1,	0ull,	0},
+	{"BUF_DONE"                    ,	0,	1,	583,	"R/W1C",	1,	1,	0,	0},
+	{"CMD_DONE"                    ,	1,	1,	583,	"R/W1C",	1,	1,	0,	0},
+	{"DMA_DONE"                    ,	2,	1,	583,	"R/W1C",	1,	1,	0,	0},
+	{"CMD_ERR"                     ,	3,	1,	583,	"R/W1C",	1,	1,	0,	0},
+	{"DMA_ERR"                     ,	4,	1,	583,	"R/W1C",	1,	1,	0,	0},
+	{"SWITCH_DONE"                 ,	5,	1,	583,	"R/W1C",	1,	1,	0,	0},
+	{"SWITCH_ERR"                  ,	6,	1,	583,	"R/W1C",	1,	1,	0,	0},
+	{"RESERVED_7_63"               ,	7,	57,	583,	"RAZ",	0,	1,	0ull,	0},
+	{"BUF_DONE"                    ,	0,	1,	584,	"R/W",	1,	1,	0,	0},
+	{"CMD_DONE"                    ,	1,	1,	584,	"R/W",	1,	1,	0,	0},
+	{"DMA_DONE"                    ,	2,	1,	584,	"R/W",	1,	1,	0,	0},
+	{"CMD_ERR"                     ,	3,	1,	584,	"R/W",	1,	1,	0,	0},
+	{"DMA_ERR"                     ,	4,	1,	584,	"R/W",	1,	1,	0,	0},
+	{"SWITCH_DONE"                 ,	5,	1,	584,	"R/W",	1,	1,	0,	0},
+	{"SWITCH_ERR"                  ,	6,	1,	584,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_7_63"               ,	7,	57,	584,	"RAZ",	0,	1,	0ull,	0},
+	{"CLK_LO"                      ,	0,	16,	585,	"RO",	0,	1,	2500ull,	0},
+	{"CLK_HI"                      ,	16,	16,	585,	"RO",	0,	1,	2500ull,	0},
+	{"POWER_CLASS"                 ,	32,	4,	585,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	585,	"RAZ",	0,	1,	0ull,	0},
+	{"BUS_WIDTH"                   ,	40,	3,	585,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_43_47"              ,	43,	5,	585,	"RAZ",	0,	1,	0ull,	0},
+	{"HS_TIMING"                   ,	48,	1,	585,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_49_63"              ,	49,	15,	585,	"RAZ",	0,	1,	0ull,	0},
+	{"CARD_RCA"                    ,	0,	16,	586,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	586,	"RAZ",	0,	1,	0ull,	0},
+	{"DAT"                         ,	0,	64,	587,	"RO",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	588,	"RO",	1,	1,	0,	0},
+	{"CMD_DONE"                    ,	0,	1,	589,	"RO",	0,	1,	0ull,	0},
+	{"CMD_IDX"                     ,	1,	6,	589,	"RO",	0,	1,	0ull,	0},
+	{"CMD_TYPE"                    ,	7,	2,	589,	"RO",	0,	1,	0ull,	0},
+	{"RSP_TYPE"                    ,	9,	3,	589,	"RO",	0,	1,	0ull,	0},
+	{"RSP_VAL"                     ,	12,	1,	589,	"RO",	0,	1,	0ull,	0},
+	{"RSP_BAD_STS"                 ,	13,	1,	589,	"RO",	0,	1,	0ull,	0},
+	{"RSP_CRC_ERR"                 ,	14,	1,	589,	"RO",	0,	1,	0ull,	0},
+	{"RSP_TIMEOUT"                 ,	15,	1,	589,	"RO",	0,	1,	0ull,	0},
+	{"STP_VAL"                     ,	16,	1,	589,	"RO",	0,	1,	0ull,	0},
+	{"STP_BAD_STS"                 ,	17,	1,	589,	"RO",	0,	1,	0ull,	0},
+	{"STP_CRC_ERR"                 ,	18,	1,	589,	"RO",	0,	1,	0ull,	0},
+	{"STP_TIMEOUT"                 ,	19,	1,	589,	"RO",	0,	1,	0ull,	0},
+	{"RSP_BUSYBIT"                 ,	20,	1,	589,	"RO",	0,	1,	0ull,	0},
+	{"BLK_CRC_ERR"                 ,	21,	1,	589,	"RO",	0,	1,	0ull,	0},
+	{"BLK_TIMEOUT"                 ,	22,	1,	589,	"RO",	0,	1,	0ull,	0},
+	{"DBUF"                        ,	23,	1,	589,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_24_27"              ,	24,	4,	589,	"RAZ",	0,	1,	0ull,	0},
+	{"DBUF_ERR"                    ,	28,	1,	589,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_55"              ,	29,	27,	589,	"RAZ",	0,	1,	0ull,	0},
+	{"DMA_PEND"                    ,	56,	1,	589,	"RO",	0,	1,	0ull,	0},
+	{"DMA_VAL"                     ,	57,	1,	589,	"RO",	0,	1,	0ull,	0},
+	{"SWITCH_VAL"                  ,	58,	1,	589,	"RO",	0,	1,	0ull,	0},
+	{"CMD_VAL"                     ,	59,	1,	589,	"RO",	0,	1,	0ull,	0},
+	{"BUS_ID"                      ,	60,	2,	589,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	589,	"RAZ",	0,	1,	0ull,	0},
+	{"DAT_CNT"                     ,	0,	10,	590,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	590,	"RAZ",	0,	1,	0ull,	0},
+	{"CMD_CNT"                     ,	16,	10,	590,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_63"              ,	26,	38,	590,	"RAZ",	0,	1,	0ull,	0},
+	{"STS_MSK"                     ,	0,	32,	591,	"R/W",	0,	1,	3828940928ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	591,	"RAZ",	0,	1,	0ull,	0},
+	{"CLK_LO"                      ,	0,	16,	592,	"R/W",	0,	1,	2500ull,	0},
+	{"CLK_HI"                      ,	16,	16,	592,	"R/W",	0,	1,	2500ull,	0},
+	{"POWER_CLASS"                 ,	32,	4,	592,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	592,	"RAZ",	0,	1,	0ull,	0},
+	{"BUS_WIDTH"                   ,	40,	3,	592,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_43_47"              ,	43,	5,	592,	"RAZ",	0,	1,	0ull,	0},
+	{"HS_TIMING"                   ,	48,	1,	592,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_49_55"              ,	49,	7,	592,	"RAZ",	0,	1,	0ull,	0},
+	{"SWITCH_ERR2"                 ,	56,	1,	592,	"RO",	0,	1,	0ull,	0},
+	{"SWITCH_ERR1"                 ,	57,	1,	592,	"RO",	0,	1,	0ull,	0},
+	{"SWITCH_ERR0"                 ,	58,	1,	592,	"RO",	0,	1,	0ull,	0},
+	{"SWITCH_EXE"                  ,	59,	1,	592,	"R/W",	0,	1,	0ull,	0},
+	{"BUS_ID"                      ,	60,	2,	592,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	592,	"RAZ",	0,	1,	0ull,	0},
+	{"CLK_CNT"                     ,	0,	26,	593,	"R/W",	0,	1,	41855000ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	593,	"RAZ",	0,	1,	0ull,	0},
+	{"DAT"                         ,	0,	64,	594,	"R/W",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	595,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	595,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	596,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	596,	"RAZ",	1,	1,	0,	0},
+	{"PP_DIS"                      ,	0,	4,	597,	"RO",	1,	1,	0,	0},
+	{"RESERVED_4_15"               ,	4,	12,	597,	"RO",	1,	1,	0,	0},
+	{"CHIP_ID"                     ,	16,	8,	597,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_25"              ,	24,	2,	597,	"RO",	1,	1,	0,	0},
+	{"NOCRYPTO"                    ,	26,	1,	597,	"RO",	1,	1,	0,	0},
+	{"NOMUL"                       ,	27,	1,	597,	"RO",	1,	1,	0,	0},
+	{"NODFA_CP2"                   ,	28,	1,	597,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_31"              ,	29,	3,	597,	"RO",	1,	1,	0,	0},
+	{"RAID_EN"                     ,	32,	1,	597,	"RO",	1,	1,	0,	0},
+	{"FUS318"                      ,	33,	1,	597,	"RO",	1,	1,	0,	0},
+	{"DORM_CRYPTO"                 ,	34,	1,	597,	"RO",	1,	1,	0,	0},
+	{"POWER_LIMIT"                 ,	35,	2,	597,	"RO",	1,	1,	0,	0},
+	{"ROM_INFO"                    ,	37,	10,	597,	"RO",	1,	1,	0,	0},
+	{"FUS118"                      ,	47,	1,	597,	"RO",	1,	1,	0,	0},
+	{"RESERVED_48_63"              ,	48,	16,	597,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	598,	"RAZ",	1,	1,	0,	0},
+	{"NODFA_DTE"                   ,	24,	1,	598,	"RO",	1,	1,	0,	0},
+	{"NOZIP"                       ,	25,	1,	598,	"RO",	1,	1,	0,	0},
+	{"EFUS_IGN"                    ,	26,	1,	598,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK"                    ,	27,	1,	598,	"RO",	1,	1,	0,	0},
+	{"BAR2_EN"                     ,	28,	1,	598,	"RO",	1,	1,	0,	0},
+	{"ZIP_INFO"                    ,	29,	2,	598,	"RO",	1,	1,	0,	0},
+	{"RESERVED_31_31"              ,	31,	1,	598,	"RAZ",	1,	1,	0,	0},
+	{"L2C_CRIP"                    ,	32,	3,	598,	"RO",	1,	1,	0,	0},
+	{"PLL_HALF_DIS"                ,	35,	1,	598,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK_MAN"                ,	36,	1,	598,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK_RSV"                ,	37,	1,	598,	"RO",	1,	1,	0,	0},
+	{"EMA"                         ,	38,	2,	598,	"RO",	1,	1,	0,	0},
+	{"RESERVED_40_40"              ,	40,	1,	598,	"RAZ",	1,	1,	0,	0},
+	{"DFA_INFO_CLM"                ,	41,	4,	598,	"RO",	1,	1,	0,	0},
+	{"DFA_INFO_DTE"                ,	45,	3,	598,	"RO",	1,	1,	0,	0},
+	{"PLL_CTL"                     ,	48,	10,	598,	"RO",	1,	1,	0,	0},
+	{"RESERVED_58_63"              ,	58,	6,	598,	"RAZ",	1,	1,	0,	0},
+	{"EMA"                         ,	0,	3,	599,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_3_3"                ,	3,	1,	599,	"RAZ",	1,	1,	0,	0},
+	{"EFF_EMA"                     ,	4,	3,	599,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_7_63"               ,	7,	57,	599,	"RAZ",	1,	1,	0,	0},
+	{"PDF"                         ,	0,	64,	600,	"RO",	1,	1,	0,	0},
+	{"FBSLIP"                      ,	0,	1,	601,	"RAZ",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	601,	"RAZ",	0,	1,	0ull,	0},
+	{"PNR_COUT_SEL"                ,	2,	2,	601,	"R/W",	0,	1,	0ull,	0},
+	{"PNR_COUT_RST"                ,	4,	1,	601,	"R/W",	0,	1,	0ull,	0},
+	{"C_COUT_SEL"                  ,	5,	2,	601,	"R/W",	0,	1,	0ull,	0},
+	{"C_COUT_RST"                  ,	7,	1,	601,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	601,	"RAZ",	1,	1,	0,	0},
+	{"PROG"                        ,	0,	1,	602,	"R/W",	1,	1,	0,	0},
+	{"SOFT"                        ,	1,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	602,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	6,	603,	"R/W",	0,	1,	1ull,	0},
+	{"SCLK_HI"                     ,	6,	15,	603,	"R/W",	0,	1,	5000ull,	0},
+	{"SCLK_LO"                     ,	21,	4,	603,	"R/W",	0,	1,	1ull,	0},
+	{"OUT"                         ,	25,	7,	603,	"R/W",	0,	1,	1ull,	0},
+	{"PROG_PIN"                    ,	32,	1,	603,	"RO",	0,	0,	0ull,	0ull},
+	{"FSRC_PIN"                    ,	33,	1,	603,	"RO",	0,	0,	0ull,	0ull},
+	{"VGATE_PIN"                   ,	34,	1,	603,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	603,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	8,	604,	"R/W",	0,	0,	0ull,	0ull},
+	{"EFUSE"                       ,	8,	1,	604,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	604,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	12,	1,	604,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	604,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	16,	8,	604,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_63"              ,	24,	40,	604,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	10,	605,	"R/W",	0,	1,	999ull,	0},
+	{"SDH"                         ,	10,	4,	605,	"R/W",	0,	1,	0ull,	0},
+	{"PRH"                         ,	14,	4,	605,	"R/W",	0,	1,	6ull,	0},
+	{"FSH"                         ,	18,	4,	605,	"R/W",	0,	1,	15ull,	0},
+	{"SCH"                         ,	22,	4,	605,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	605,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	18,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR1"                     ,	18,	18,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR2"                     ,	36,	18,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"TOO_MANY"                    ,	54,	1,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	606,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR3"                     ,	0,	18,	607,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR4"                     ,	18,	18,	607,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR5"                     ,	36,	18,	607,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	607,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR6"                     ,	0,	18,	608,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	608,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	14,	609,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR1"                     ,	14,	14,	609,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR2"                     ,	28,	14,	609,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_42_63"              ,	42,	22,	609,	"RAZ",	1,	1,	0,	0},
+	{"TOO_MANY"                    ,	0,	1,	610,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	610,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	63,	611,	"RO",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	611,	"R/W",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	4,	612,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_4_63"               ,	4,	60,	612,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	613,	"R/W",	0,	1,	15ull,	0},
+	{"PCTL"                        ,	6,	6,	613,	"R/W",	0,	1,	19ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	613,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	614,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	614,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	614,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	614,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	614,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	614,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	614,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	614,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	614,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	614,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	615,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	615,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	616,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	616,	"RAZ",	1,	1,	0,	0},
+	{"FRNANOSEC"                   ,	0,	32,	617,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	617,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	618,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	618,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	0,	64,	619,	"R/W",	0,	0,	18446744073709551615ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	620,	"R/W",	0,	0,	4294967295ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	620,	"RAZ",	1,	1,	0,	0},
+	{"PTP_EN"                      ,	0,	1,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_CLK_EN"                  ,	1,	1,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_CLK_IN"                  ,	2,	6,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_EN"                    ,	8,	1,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_EDGE"                  ,	9,	1,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_IN"                    ,	10,	6,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_EN"                    ,	16,	1,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_EDGE"                  ,	17,	1,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_IN"                    ,	18,	6,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT_EN"                    ,	24,	1,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT_INV"                   ,	25,	1,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT_OUT"                   ,	26,	4,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS_EN"                      ,	30,	1,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS_INV"                     ,	31,	1,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS_OUT"                     ,	32,	5,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT_OUT4"                  ,	37,	1,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_CLK_EDGE"                ,	38,	2,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"CKOUT"                       ,	40,	1,	621,	"RO",	1,	0,	0,	0ull},
+	{"PPS"                         ,	41,	1,	621,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	621,	"RAZ",	1,	1,	0,	0},
+	{"FRNANOSEC"                   ,	0,	32,	622,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	622,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	0,	64,	623,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	624,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	624,	"RAZ",	1,	1,	0,	0},
+	{"CNTR"                        ,	0,	64,	625,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEL"                         ,	0,	5,	626,	"R/W",	0,	0,	31ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	626,	"RAZ",	1,	1,	0,	0},
+	{"FRNANOSEC"                   ,	0,	32,	627,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	627,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	628,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	628,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	0,	64,	629,	"R/W",	0,	0,	18446744073709551615ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	630,	"R/W",	0,	0,	4294967295ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	630,	"RAZ",	1,	1,	0,	0},
+	{"NANOSEC"                     ,	0,	64,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"QLM_CFG"                     ,	0,	2,	632,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_2_7"                ,	2,	6,	632,	"RAZ",	1,	1,	0,	0},
+	{"QLM_SPD"                     ,	8,	4,	632,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_12_13"              ,	12,	2,	632,	"RAZ",	1,	1,	0,	0},
+	{"PRTMODE"                     ,	14,	1,	632,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	632,	"RAZ",	1,	1,	0,	0},
+	{"RBOOT_PIN"                   ,	0,	1,	633,	"RO",	1,	1,	0,	0},
+	{"RBOOT"                       ,	1,	1,	633,	"R/W",	1,	1,	0,	0},
+	{"LBOOT"                       ,	2,	10,	633,	"R/W1C",	1,	1,	0,	0},
+	{"QLM0_SPD"                    ,	12,	4,	633,	"RO",	1,	1,	0,	0},
+	{"QLM1_SPD"                    ,	16,	4,	633,	"RO",	1,	1,	0,	0},
+	{"QLM2_SPD"                    ,	20,	4,	633,	"RO",	1,	1,	0,	0},
+	{"PNR_MUL"                     ,	24,	6,	633,	"RO",	1,	1,	0,	0},
+	{"C_MUL"                       ,	30,	6,	633,	"RO",	1,	1,	0,	0},
+	{"RESERVED_36_47"              ,	36,	12,	633,	"RAZ",	1,	1,	0,	0},
+	{"LBOOT_EXT"                   ,	48,	2,	633,	"R/W1C",	1,	1,	0,	0},
+	{"RESERVED_50_57"              ,	50,	8,	633,	"RAZ",	1,	1,	0,	0},
+	{"JT_TSTMODE"                  ,	58,	1,	633,	"RO",	1,	1,	0,	0},
+	{"CKILL_PPDIS"                 ,	59,	1,	633,	"R/W",	0,	1,	1ull,	0},
+	{"ROMEN"                       ,	60,	1,	633,	"R/W",	1,	1,	0,	0},
+	{"EJTAGDIS"                    ,	61,	1,	633,	"R/W",	1,	1,	0,	0},
+	{"JTCSRDIS"                    ,	62,	1,	633,	"R/W",	1,	1,	0,	0},
+	{"CHIPKILL"                    ,	63,	1,	633,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SOFT_CLR_BIST"               ,	0,	1,	634,	"R/W",	0,	0,	0ull,	0ull},
+	{"WARM_CLR_BIST"               ,	1,	1,	634,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNTL_CLR_BIST"               ,	2,	1,	634,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_5"                ,	3,	3,	634,	"RAZ",	1,	1,	0,	0},
+	{"BIST_DELAY"                  ,	6,	58,	634,	"RO",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	47,	635,	"R/W",	0,	1,	17179869183ull,	0},
+	{"RESERVED_47_63"              ,	47,	17,	635,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RST_VAL"                     ,	0,	1,	636,	"RO",	1,	1,	0,	0},
+	{"RST_CHIP"                    ,	1,	1,	636,	"R/W",	0,	1,	0ull,	0},
+	{"RST_RCV"                     ,	2,	1,	636,	"R/W",	1,	1,	0,	0},
+	{"RST_DRV"                     ,	3,	1,	636,	"R/W",	1,	1,	0,	0},
+	{"PRTMODE"                     ,	4,	2,	636,	"R/W",	1,	1,	0,	0},
+	{"HOST_MODE"                   ,	6,	1,	636,	"RO",	1,	1,	0,	0},
+	{"RST_LINK"                    ,	7,	1,	636,	"R/W",	1,	1,	0,	0},
+	{"RST_DONE"                    ,	8,	1,	636,	"RO",	1,	1,	0,	0},
+	{"PRST_LINK"                   ,	9,	1,	636,	"R/W",	0,	1,	0ull,	0},
+	{"GEN1_ONLY"                   ,	10,	1,	636,	"RO",	0,	1,	0ull,	0},
+	{"REV_LANES"                   ,	11,	1,	636,	"R/W",	1,	1,	0,	0},
+	{"IN_REV_LN"                   ,	12,	1,	636,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	636,	"RAZ",	1,	1,	0,	0},
+	{"RST_VAL"                     ,	0,	1,	637,	"RO",	1,	1,	0,	0},
+	{"RST_CHIP"                    ,	1,	1,	637,	"R/W",	0,	1,	0ull,	0},
+	{"RST_RCV"                     ,	2,	1,	637,	"R/W",	1,	1,	0,	0},
+	{"RST_DRV"                     ,	3,	1,	637,	"R/W",	1,	1,	0,	0},
+	{"PRTMODE"                     ,	4,	2,	637,	"R/W",	1,	1,	0,	0},
+	{"HOST_MODE"                   ,	6,	1,	637,	"RO",	1,	1,	0,	0},
+	{"RST_LINK"                    ,	7,	1,	637,	"R/W",	1,	1,	0,	0},
+	{"RST_DONE"                    ,	8,	1,	637,	"RO",	1,	1,	0,	0},
+	{"PRST_LINK"                   ,	9,	1,	637,	"R/W",	0,	1,	0ull,	0},
+	{"GEN1_ONLY"                   ,	10,	1,	637,	"RO",	0,	1,	0ull,	0},
+	{"REV_LANES"                   ,	11,	1,	637,	"R/W",	1,	1,	0,	0},
+	{"IN_REV_LN"                   ,	12,	1,	637,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	637,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST_DLY"                ,	0,	16,	638,	"R/W",	0,	1,	2047ull,	0},
+	{"WARM_RST_DLY"                ,	16,	16,	638,	"R/W",	0,	1,	2047ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	638,	"RAZ",	1,	1,	0,	0},
+	{"RST_LINK0"                   ,	0,	1,	639,	"R/W1C",	0,	1,	0ull,	0},
+	{"RST_LINK1"                   ,	1,	1,	639,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_7"                ,	2,	6,	639,	"RAZ",	1,	1,	0,	0},
+	{"PERST0"                      ,	8,	1,	639,	"R/W1C",	0,	1,	0ull,	0},
+	{"PERST1"                      ,	9,	1,	639,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	639,	"RAZ",	1,	1,	0,	0},
+	{"RST_LINK0"                   ,	0,	1,	640,	"R/W",	0,	1,	0ull,	0},
+	{"RST_LINK1"                   ,	1,	1,	640,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_7"                ,	2,	6,	640,	"RAZ",	1,	1,	0,	0},
+	{"PERST0"                      ,	8,	1,	640,	"R/W",	0,	1,	0ull,	0},
+	{"PERST1"                      ,	9,	1,	640,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	640,	"RAZ",	1,	1,	0,	0},
+	{"ST_INT"                      ,	0,	1,	641,	"R/W1C",	0,	1,	0ull,	0},
+	{"TS_INT"                      ,	1,	1,	641,	"R/W1C",	0,	1,	0ull,	0},
+	{"CORE_INT"                    ,	2,	1,	641,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	641,	"RAZ",	1,	1,	0,	0},
+	{"ST_EN"                       ,	4,	1,	641,	"R/W",	0,	1,	0ull,	0},
+	{"TS_EN"                       ,	5,	1,	641,	"R/W",	0,	1,	0ull,	0},
+	{"CORE_EN"                     ,	6,	1,	641,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	641,	"RAZ",	1,	1,	0,	0},
+	{"SDA_OVR"                     ,	8,	1,	641,	"R/W",	0,	1,	0ull,	0},
+	{"SCL_OVR"                     ,	9,	1,	641,	"R/W",	0,	1,	0ull,	0},
+	{"SDA"                         ,	10,	1,	641,	"RO",	1,	1,	0,	0},
+	{"SCL"                         ,	11,	1,	641,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	641,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	642,	"R/W",	0,	1,	0ull,	0},
+	{"EOP_IA"                      ,	32,	3,	642,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	35,	5,	642,	"R/W",	0,	1,	0ull,	0},
+	{"A"                           ,	40,	10,	642,	"R/W",	0,	1,	0ull,	0},
+	{"SCR"                         ,	50,	2,	642,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	52,	3,	642,	"R/W",	0,	1,	0ull,	0},
+	{"SOVR"                        ,	55,	1,	642,	"R/W",	0,	1,	0ull,	0},
+	{"R"                           ,	56,	1,	642,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	57,	4,	642,	"R/W",	0,	1,	0ull,	0},
+	{"EIA"                         ,	61,	1,	642,	"R/W",	0,	1,	0ull,	0},
+	{"SLONLY"                      ,	62,	1,	642,	"R/W",	0,	1,	0ull,	0},
+	{"V"                           ,	63,	1,	642,	"RC/W",	0,	1,	0ull,	0},
+	{"D"                           ,	0,	32,	643,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	32,	8,	643,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	643,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	644,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_32_61"              ,	32,	30,	644,	"RAZ",	1,	1,	0,	0},
+	{"V"                           ,	62,	2,	644,	"RC/W",	0,	1,	0ull,	0},
+	{"DLH"                         ,	0,	8,	645,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	645,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	646,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	646,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	647,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	647,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	648,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	648,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	648,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	648,	"RAZ",	1,	1,	0,	0},
+	{"TXTRIG"                      ,	4,	2,	648,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	648,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	648,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	649,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	649,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	650,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	650,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	650,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	650,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	650,	"RAZ",	1,	1,	0,	0},
+	{"PTIME"                       ,	7,	1,	650,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	650,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	651,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	651,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	651,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	651,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	652,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	652,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	652,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	652,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	652,	"RAZ",	1,	1,	0,	0},
+	{"BRK"                         ,	6,	1,	652,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	652,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	652,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	653,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	653,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	653,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	653,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	653,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	653,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	653,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	653,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	653,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	654,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	654,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	654,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	654,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	654,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	654,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	654,	"RAZ",	1,	1,	0,	0},
+	{"DCTS"                        ,	0,	1,	655,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	655,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	655,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	655,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	655,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	655,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	655,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	655,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	655,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	656,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	656,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	657,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	657,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	658,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	658,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	658,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	658,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	659,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	659,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	660,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	660,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	661,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	661,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	662,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	662,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	662,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	662,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	663,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	663,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	664,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	664,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	665,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	665,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	666,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	666,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	667,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	667,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	668,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	668,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	669,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	669,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	669,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	669,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	669,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	669,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDLELO"                      ,	1,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_CONT"                    ,	2,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"WIREOR"                      ,	3,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBFIRST"                    ,	4,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_ENA"                     ,	5,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	670,	"RAZ",	1,	1,	0,	0},
+	{"CSHI"                        ,	7,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDLECLKS"                    ,	8,	2,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRITX"                       ,	10,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSLATE"                      ,	11,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSENA0"                      ,	12,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSENA1"                      ,	13,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	670,	"RAZ",	1,	1,	0,	0},
+	{"CLKDIV"                      ,	16,	13,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	670,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	8,	671,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	671,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	672,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	672,	"RAZ",	1,	1,	0,	0},
+	{"RXNUM"                       ,	8,	5,	672,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	672,	"RAZ",	1,	1,	0,	0},
+	{"TOTNUM"                      ,	0,	5,	673,	"WO",	1,	0,	0,	2ull},
+	{"RESERVED_5_7"                ,	5,	3,	673,	"RAZ",	1,	1,	0,	0},
+	{"TXNUM"                       ,	8,	5,	673,	"WO",	1,	0,	0,	1ull},
+	{"RESERVED_13_15"              ,	13,	3,	673,	"RAZ",	1,	1,	0,	0},
+	{"LEAVECS"                     ,	16,	1,	673,	"WO",	1,	0,	0,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	673,	"RAZ",	1,	1,	0,	0},
+	{"CSID"                        ,	20,	1,	673,	"WO",	1,	0,	0,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	673,	"RAZ",	1,	1,	0,	0},
+	{"VENDID"                      ,	0,	16,	674,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	674,	"RO/WRSL",	0,	0,	148ull,	148ull},
+	{"ISAE"                        ,	0,	1,	675,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	675,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	675,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	675,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	675,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	675,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	675,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	675,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	675,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	675,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	675,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	675,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	675,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	675,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	675,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	675,	"RAZ",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	675,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	675,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	675,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	675,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	675,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	675,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	675,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	675,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	676,	"RO/WRSL",	0,	0,	8ull,	8ull},
+	{"PI"                          ,	8,	8,	676,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	676,	"RO/WRSL",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	676,	"RO/WRSL",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	677,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	677,	"RO",	0,	0,	0ull,	0ull},
+	{"MFD"                         ,	23,	1,	677,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	677,	"RO",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	678,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	678,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	678,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_13"               ,	4,	10,	678,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	14,	18,	678,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	679,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	679,	"WORSL",	0,	0,	8191ull,	8191ull},
+	{"UBAB"                        ,	0,	32,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	681,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	682,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	682,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	682,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_25"               ,	4,	22,	682,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	26,	6,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	683,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	683,	"WORSL",	0,	0,	33554431ull,	33554431ull},
+	{"UBAB"                        ,	0,	32,	684,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	685,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	686,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	686,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	686,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_31"               ,	4,	28,	686,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	1,	687,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	687,	"WORSL",	0,	0,	2147483647ull,	2147483647ull},
+	{"RESERVED_0_8"                ,	0,	9,	688,	"RAZ",	1,	1,	0,	0},
+	{"UBAB"                        ,	9,	23,	688,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	689,	"WORSL",	0,	0,	511ull,	511ull},
+	{"CISP"                        ,	0,	32,	690,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SSVID"                       ,	0,	16,	691,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"SSID"                        ,	16,	16,	691,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"ER_EN"                       ,	0,	1,	692,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_15"               ,	1,	15,	692,	"RAZ",	1,	1,	0,	0},
+	{"ERADDR"                      ,	16,	16,	692,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	693,	"WORSL",	0,	0,	1ull,	1ull},
+	{"MASK"                        ,	1,	31,	693,	"WORSL",	0,	0,	32767ull,	32767ull},
+	{"CP"                          ,	0,	8,	694,	"RO/WRSL",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	694,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	695,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	695,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"MG"                          ,	16,	8,	695,	"RO",	0,	0,	0ull,	0ull},
+	{"ML"                          ,	24,	8,	695,	"RO",	0,	0,	0ull,	0ull},
+	{"PMCID"                       ,	0,	8,	696,	"RO",	0,	0,	1ull,	0ull},
+	{"NCP"                         ,	8,	8,	696,	"RO/WRSL",	0,	0,	80ull,	0ull},
+	{"PMSV"                        ,	16,	3,	696,	"RO/WRSL",	0,	0,	3ull,	0ull},
+	{"PME_CLOCK"                   ,	19,	1,	696,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	696,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	696,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	696,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	696,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	696,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	696,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	697,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	697,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	697,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	697,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	697,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	697,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	697,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	697,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	697,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	697,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	697,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	697,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	698,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	698,	"RO/WRSL",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	698,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	698,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	698,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	698,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"PVM"                         ,	24,	1,	698,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	698,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	699,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	699,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	700,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	701,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	701,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	702,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	702,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	702,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	702,	"RO",	0,	0,	0ull,	0ull},
+	{"SI"                          ,	24,	1,	702,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	702,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	702,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	703,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	703,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	703,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	703,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"EL1AL"                       ,	9,	3,	703,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"RESERVED_12_14"              ,	12,	3,	703,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	703,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	703,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	703,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	703,	"RO",	0,	0,	0ull,	0ull},
+	{"FLR_CAP"                     ,	28,	1,	703,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	703,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	704,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	704,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	704,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	704,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	704,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	704,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	704,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	704,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	704,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	704,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	704,	"R/W",	0,	0,	2ull,	2ull},
+	{"I_FLR"                       ,	15,	1,	704,	"RO",	0,	0,	0ull,	0ull},
+	{"CE_D"                        ,	16,	1,	704,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	704,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	704,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	704,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	704,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	704,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	704,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	705,	"RO/WRSL",	1,	1,	0,	0},
+	{"MLW"                         ,	4,	6,	705,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"ASLPMS"                      ,	10,	2,	705,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	705,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	705,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	705,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	705,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	705,	"RO",	0,	0,	0ull,	0ull},
+	{"LBNC"                        ,	21,	1,	705,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPM"                        ,	22,	1,	705,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_23_23"              ,	23,	1,	705,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	705,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	706,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	706,	"RO",	0,	0,	0ull,	0ull},
+	{"LD"                          ,	4,	1,	706,	"RO",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	706,	"RO",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	706,	"RO",	0,	0,	0ull,	0ull},
+	{"LBM_INT_ENB"                 ,	10,	1,	706,	"RO",	0,	0,	0ull,	0ull},
+	{"LAB_INT_ENB"                 ,	11,	1,	706,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	706,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	706,	"RO",	0,	0,	1ull,	1ull},
+	{"NLW"                         ,	20,	6,	706,	"RO",	0,	0,	1ull,	4ull},
+	{"RESERVED_26_26"              ,	26,	1,	706,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	706,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	706,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"DLLA"                        ,	29,	1,	706,	"RO",	0,	0,	0ull,	0ull},
+	{"LBM"                         ,	30,	1,	706,	"RO",	0,	0,	0ull,	0ull},
+	{"LAB"                         ,	31,	1,	706,	"RO",	0,	0,	0ull,	0ull},
+	{"CTRS"                        ,	0,	4,	707,	"RO",	0,	0,	15ull,	15ull},
+	{"CTDS"                        ,	4,	1,	707,	"RO",	0,	0,	1ull,	1ull},
+	{"ARI"                         ,	5,	1,	707,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OPS"                    ,	6,	1,	707,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM32S"                     ,	7,	1,	707,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM64S"                     ,	8,	1,	707,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM128S"                    ,	9,	1,	707,	"RO",	0,	0,	0ull,	0ull},
+	{"NOROPRPR"                    ,	10,	1,	707,	"RO",	0,	0,	0ull,	0ull},
+	{"LTRS"                        ,	11,	1,	707,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHS"                        ,	12,	2,	707,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_17"              ,	14,	4,	707,	"RAZ",	1,	1,	0,	0},
+	{"OBFFS"                       ,	18,	2,	707,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	707,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	708,	"R/W",	0,	0,	0ull,	0ull},
+	{"ARI"                         ,	5,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP"                     ,	6,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP_EB"                  ,	7,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_RQ"                      ,	8,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_CP"                      ,	9,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"LTRE"                        ,	10,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_12"              ,	11,	2,	708,	"RAZ",	1,	1,	0,	0},
+	{"OBFFE"                       ,	13,	2,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_31"              ,	15,	17,	708,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	709,	"RAZ",	1,	1,	0,	0},
+	{"SLSV"                        ,	1,	7,	709,	"RO/WRSL",	1,	1,	0,	0},
+	{"CLS"                         ,	8,	1,	709,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	709,	"RAZ",	1,	1,	0,	0},
+	{"TLS"                         ,	0,	4,	710,	"R/W",	1,	0,	0,	2ull},
+	{"EC"                          ,	4,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"HASD"                        ,	5,	1,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"SDE"                         ,	6,	1,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"TM"                          ,	7,	3,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMC"                         ,	10,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSOS"                        ,	11,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDE"                         ,	12,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	710,	"RAZ",	1,	1,	0,	0},
+	{"CDL"                         ,	16,	1,	710,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_17_31"              ,	17,	15,	710,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	711,	"RO",	0,	0,	1ull,	1ull},
+	{"CV"                          ,	16,	4,	711,	"RO",	0,	0,	2ull,	2ull},
+	{"NCO"                         ,	20,	12,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	712,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	712,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_11"               ,	5,	7,	712,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	712,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	712,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	712,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	712,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	712,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	712,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	712,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	712,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	712,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_21"              ,	21,	1,	712,	"RAZ",	1,	1,	0,	0},
+	{"UCIES"                       ,	22,	1,	712,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	712,	"RAZ",	1,	1,	0,	0},
+	{"UATOMBS"                     ,	24,	1,	712,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	712,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	713,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_11"               ,	5,	7,	713,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_21"              ,	21,	1,	713,	"RAZ",	1,	1,	0,	0},
+	{"UCIEM"                       ,	22,	1,	713,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_23_23"              ,	23,	1,	713,	"RAZ",	1,	1,	0,	0},
+	{"UATOMBM"                     ,	24,	1,	713,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	713,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	714,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	714,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_11"               ,	5,	7,	714,	"RO",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	714,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	714,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	714,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	714,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	714,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	714,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	714,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	714,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	714,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_21"              ,	21,	1,	714,	"RO",	0,	0,	0ull,	0ull},
+	{"UCIES"                       ,	22,	1,	714,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_23_23"              ,	23,	1,	714,	"RO",	0,	0,	0ull,	0ull},
+	{"UATOMBS"                     ,	24,	1,	714,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	714,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	715,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	715,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	715,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	715,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	715,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	715,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	715,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	715,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CIES"                        ,	14,	1,	715,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_31"              ,	15,	17,	715,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	716,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	716,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	716,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	716,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	716,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	716,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	716,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	716,	"R/W",	0,	0,	1ull,	1ull},
+	{"CIEM"                        ,	14,	1,	716,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_15_31"              ,	15,	17,	716,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	717,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	717,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	717,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	717,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	717,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	717,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	718,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	719,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	720,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	721,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	722,	"R/W",	0,	1,	4143ull,	0},
+	{"RTL"                         ,	16,	16,	722,	"R/W",	0,	1,	12429ull,	0},
+	{"OMR"                         ,	0,	32,	723,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	724,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_14"               ,	8,	7,	724,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	724,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	724,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	724,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	724,	"R/W",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	725,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	725,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	725,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	725,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	725,	"R/W",	0,	0,	3ull,	3ull},
+	{"EASPML1"                     ,	30,	1,	725,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	725,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	726,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	726,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	726,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	726,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	726,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	726,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	726,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	726,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	726,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	726,	"R/W",	0,	0,	15ull,	1ull},
+	{"RESERVED_22_31"              ,	22,	10,	726,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	727,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	727,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	727,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	727,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	727,	"R/W",	0,	0,	0ull,	0ull},
+	{"MFUNCN"                      ,	0,	8,	728,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_13"               ,	8,	6,	728,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	728,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	728,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	728,	"R/W",	0,	0,	0ull,	0ull},
+	{"CX_NFUNC"                    ,	29,	3,	728,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPIV"                       ,	0,	11,	729,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	729,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	729,	"R/W",	0,	0,	1ull,	1ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_DABORT_4UCPL"              ,	2,	1,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_HANDLE_FLUSH"              ,	3,	1,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_31"               ,	4,	28,	730,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	731,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	732,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	733,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	733,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	733,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	734,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	734,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	734,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	735,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	735,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	735,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	736,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	736,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	736,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	736,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	737,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	737,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	737,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	737,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	738,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	738,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	738,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	738,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	739,	"RO/WRSL",	0,	0,	56ull,	56ull},
+	{"HEADER_CREDITS"              ,	12,	8,	739,	"RO/WRSL",	0,	0,	31ull,	31ull},
+	{"RESERVED_20_20"              ,	20,	1,	739,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	739,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	739,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	739,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	739,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	740,	"RO/WRSL",	0,	0,	13ull,	13ull},
+	{"HEADER_CREDITS"              ,	12,	8,	740,	"RO/WRSL",	0,	0,	31ull,	31ull},
+	{"RESERVED_20_20"              ,	20,	1,	740,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	740,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	740,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	741,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HEADER_CREDITS"              ,	12,	8,	741,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	741,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	741,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	741,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	742,	"RO/WRSL",	0,	0,	183ull,	183ull},
+	{"RESERVED_14_15"              ,	14,	2,	742,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	742,	"RO/WRSL",	0,	0,	37ull,	37ull},
+	{"RESERVED_26_31"              ,	26,	6,	742,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	743,	"RO/WRSL",	0,	0,	97ull,	97ull},
+	{"RESERVED_14_15"              ,	14,	2,	743,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	743,	"RO/WRSL",	0,	0,	37ull,	37ull},
+	{"RESERVED_26_31"              ,	26,	6,	743,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	744,	"RO/WRSL",	0,	0,	398ull,	398ull},
+	{"RESERVED_14_15"              ,	14,	2,	744,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	744,	"RO/WRSL",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	744,	"RAZ",	1,	1,	0,	0},
+	{"N_FTS"                       ,	0,	8,	745,	"R/W",	0,	0,	128ull,	128ull},
+	{"LE"                          ,	8,	9,	745,	"R/W",	0,	0,	8ull,	8ull},
+	{"DSC"                         ,	17,	1,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"CPYTS"                       ,	18,	1,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTCRB"                       ,	19,	1,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"S_D_E"                       ,	20,	1,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	745,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	746,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"VENDID"                      ,	0,	16,	748,	"R/W",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	748,	"R/W",	0,	0,	148ull,	148ull},
+	{"ISAE"                        ,	0,	1,	749,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	749,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	749,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	749,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	749,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	749,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	749,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	749,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	749,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	749,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	749,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	749,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	749,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	749,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	749,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	749,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	749,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	749,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	749,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	749,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	749,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	749,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	749,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	749,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	750,	"R/W",	0,	0,	8ull,	8ull},
+	{"PI"                          ,	8,	8,	750,	"R/W",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	750,	"R/W",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	750,	"R/W",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	751,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	751,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	751,	"RO",	0,	0,	1ull,	1ull},
+	{"MFD"                         ,	23,	1,	751,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	751,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_31"               ,	0,	32,	752,	"RO",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	753,	"RO",	1,	1,	0,	0},
+	{"PBNUM"                       ,	0,	8,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBNUM"                       ,	8,	8,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUBBNUM"                     ,	16,	8,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLT"                         ,	24,	8,	754,	"RO",	0,	0,	0ull,	0ull},
+	{"IO32A"                       ,	0,	1,	755,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	755,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_BASE"                    ,	4,	4,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO32B"                       ,	8,	1,	755,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_11"               ,	9,	3,	755,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_LIMI"                    ,	12,	4,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_20"              ,	16,	5,	755,	"RAZ",	1,	1,	0,	0},
+	{"M66"                         ,	21,	1,	755,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	755,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	755,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	755,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	755,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	755,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	755,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	755,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	755,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	755,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	756,	"RO",	1,	1,	0,	0},
+	{"MB_ADDR"                     ,	4,	12,	756,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_19"              ,	16,	4,	756,	"RO",	1,	1,	0,	0},
+	{"ML_ADDR"                     ,	20,	12,	756,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64A"                      ,	0,	1,	757,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	757,	"RO",	1,	1,	0,	0},
+	{"LMEM_BASE"                   ,	4,	12,	757,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64B"                      ,	16,	1,	757,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_17_19"              ,	17,	3,	757,	"RO",	1,	1,	0,	0},
+	{"LMEM_LIMIT"                  ,	20,	12,	757,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_BASE"                   ,	0,	32,	758,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_LIMIT"                  ,	0,	32,	759,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_BASE"                    ,	0,	16,	760,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_LIMIT"                   ,	16,	16,	760,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP"                          ,	0,	8,	761,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	761,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	762,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	763,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	763,	"R/W",	0,	0,	1ull,	1ull},
+	{"PERE"                        ,	16,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	17,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"ISAE"                        ,	18,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGAE"                        ,	19,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGA16D"                      ,	20,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAM"                         ,	21,	1,	763,	"RO",	0,	0,	0ull,	0ull},
+	{"SBRST"                       ,	22,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	23,	1,	763,	"RO",	0,	0,	0ull,	0ull},
+	{"PDT"                         ,	24,	1,	763,	"RO",	0,	0,	0ull,	0ull},
+	{"SDT"                         ,	25,	1,	763,	"RO",	0,	0,	0ull,	0ull},
+	{"DTS"                         ,	26,	1,	763,	"RO",	0,	0,	0ull,	0ull},
+	{"DTSEES"                      ,	27,	1,	763,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	763,	"RO",	1,	1,	0,	0},
+	{"PMCID"                       ,	0,	8,	764,	"RO",	0,	0,	1ull,	1ull},
+	{"NCP"                         ,	8,	8,	764,	"R/W",	0,	0,	80ull,	80ull},
+	{"PMSV"                        ,	16,	3,	764,	"R/W",	0,	0,	3ull,	3ull},
+	{"PME_CLOCK"                   ,	19,	1,	764,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	764,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	765,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	765,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	765,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	765,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	765,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	765,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	765,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	765,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	765,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	765,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	765,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	765,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	766,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	766,	"R/W",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	766,	"R/W",	0,	0,	1ull,	1ull},
+	{"PVM"                         ,	24,	1,	766,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	766,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	767,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	769,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	769,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	770,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	770,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	770,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	770,	"RO",	0,	0,	4ull,	4ull},
+	{"SI"                          ,	24,	1,	770,	"R/W",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	770,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	770,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	771,	"R/W",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL1AL"                       ,	9,	3,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_14"              ,	12,	3,	771,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	771,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	771,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	771,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	771,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	771,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	772,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	772,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	772,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_15_15"              ,	15,	1,	772,	"RAZ",	1,	1,	0,	0},
+	{"CE_D"                        ,	16,	1,	772,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	772,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	772,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	772,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	772,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	772,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	772,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	773,	"R/W",	1,	1,	0,	0},
+	{"MLW"                         ,	4,	6,	773,	"R/W",	1,	1,	0,	0},
+	{"ASLPMS"                      ,	10,	2,	773,	"R/W",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	773,	"R/W",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	773,	"R/W",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	773,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	773,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	773,	"RO",	0,	0,	1ull,	1ull},
+	{"LBNC"                        ,	21,	1,	773,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"ASPM"                        ,	22,	1,	773,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_23_23"              ,	23,	1,	773,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	773,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	774,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	774,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	774,	"R/W",	0,	0,	1ull,	1ull},
+	{"LD"                          ,	4,	1,	774,	"R/W",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	774,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	774,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	774,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	774,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	774,	"R/W",	0,	0,	0ull,	0ull},
+	{"LBM_INT_ENB"                 ,	10,	1,	774,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAB_INT_ENB"                 ,	11,	1,	774,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	774,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	774,	"RO",	1,	1,	0,	0},
+	{"NLW"                         ,	20,	6,	774,	"RO",	0,	0,	1ull,	4ull},
+	{"RESERVED_26_26"              ,	26,	1,	774,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	774,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	774,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLLA"                        ,	29,	1,	774,	"RO",	0,	0,	0ull,	1ull},
+	{"LBM"                         ,	30,	1,	774,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LAB"                         ,	31,	1,	774,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ABP"                         ,	0,	1,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCP"                         ,	1,	1,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLSP"                       ,	2,	1,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIP"                         ,	3,	1,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	4,	1,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_S"                        ,	5,	1,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_C"                        ,	6,	1,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LV"                       ,	7,	8,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LS"                       ,	15,	2,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIP"                        ,	17,	1,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"NCCS"                        ,	18,	1,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS_NUM"                      ,	19,	13,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABP_EN"                      ,	0,	1,	776,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	1,	1,	776,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLS_EN"                     ,	2,	1,	776,	"R/W",	0,	0,	0ull,	0ull},
+	{"PD_EN"                       ,	3,	1,	776,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCINT_EN"                    ,	4,	1,	776,	"R/W",	0,	0,	0ull,	0ull},
+	{"HPINT_EN"                    ,	5,	1,	776,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIC"                         ,	6,	2,	776,	"R/W",	0,	0,	3ull,	3ull},
+	{"PIC"                         ,	8,	2,	776,	"R/W",	0,	0,	3ull,	3ull},
+	{"PCC"                         ,	10,	1,	776,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIC"                        ,	11,	1,	776,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLS_EN"                     ,	12,	1,	776,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	776,	"RAZ",	1,	1,	0,	0},
+	{"ABP_D"                       ,	16,	1,	776,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PF_D"                        ,	17,	1,	776,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLS_C"                      ,	18,	1,	776,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PD_C"                        ,	19,	1,	776,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CCINT_D"                     ,	20,	1,	776,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLSS"                       ,	21,	1,	776,	"RO",	0,	0,	0ull,	0ull},
+	{"PDS"                         ,	22,	1,	776,	"RO",	0,	0,	1ull,	1ull},
+	{"EMIS"                        ,	23,	1,	776,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLS_C"                      ,	24,	1,	776,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	776,	"RAZ",	1,	1,	0,	0},
+	{"SECEE"                       ,	0,	1,	777,	"R/W",	0,	0,	0ull,	0ull},
+	{"SENFEE"                      ,	1,	1,	777,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEFEE"                       ,	2,	1,	777,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMEIE"                       ,	3,	1,	777,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRSSVE"                      ,	4,	1,	777,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_15"               ,	5,	11,	777,	"RAZ",	1,	1,	0,	0},
+	{"CRSSV"                       ,	16,	1,	777,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	777,	"RAZ",	1,	1,	0,	0},
+	{"PME_RID"                     ,	0,	16,	778,	"RO",	0,	0,	0ull,	0ull},
+	{"PME_STAT"                    ,	16,	1,	778,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PME_PEND"                    ,	17,	1,	778,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	778,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTRS"                        ,	0,	4,	779,	"RO",	0,	0,	15ull,	15ull},
+	{"CTDS"                        ,	4,	1,	779,	"RO",	0,	0,	1ull,	1ull},
+	{"ARI_FW"                      ,	5,	1,	779,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OPS"                    ,	6,	1,	779,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM32S"                     ,	7,	1,	779,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM64S"                     ,	8,	1,	779,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM128S"                    ,	9,	1,	779,	"RO",	0,	0,	0ull,	0ull},
+	{"NOROPRPR"                    ,	10,	1,	779,	"RO",	0,	0,	1ull,	1ull},
+	{"LTRS"                        ,	11,	1,	779,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHS"                        ,	12,	2,	779,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_17"              ,	14,	4,	779,	"RAZ",	1,	1,	0,	0},
+	{"OBFFS"                       ,	18,	2,	779,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	779,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	780,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	780,	"R/W",	0,	0,	0ull,	0ull},
+	{"ARI"                         ,	5,	1,	780,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP"                     ,	6,	1,	780,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_OP_EB"                  ,	7,	1,	780,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_RQ"                      ,	8,	1,	780,	"RO",	0,	0,	0ull,	0ull},
+	{"ID0_CP"                      ,	9,	1,	780,	"RO",	0,	0,	0ull,	0ull},
+	{"LTRE"                        ,	10,	1,	780,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_12"              ,	11,	2,	780,	"RAZ",	1,	1,	0,	0},
+	{"OBFFE"                       ,	13,	2,	780,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_31"              ,	15,	17,	780,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	781,	"RAZ",	1,	1,	0,	0},
+	{"SLSV"                        ,	1,	7,	781,	"RO/WRSL",	1,	1,	0,	0},
+	{"CLS"                         ,	8,	1,	781,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	781,	"RAZ",	1,	1,	0,	0},
+	{"TLS"                         ,	0,	4,	782,	"R/W",	1,	1,	0,	0},
+	{"EC"                          ,	4,	1,	782,	"R/W",	0,	0,	0ull,	0ull},
+	{"HASD"                        ,	5,	1,	782,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDE"                         ,	6,	1,	782,	"R/W",	0,	0,	0ull,	0ull},
+	{"TM"                          ,	7,	3,	782,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMC"                         ,	10,	1,	782,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSOS"                        ,	11,	1,	782,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDE"                         ,	12,	1,	782,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	782,	"RAZ",	1,	1,	0,	0},
+	{"CDL"                         ,	16,	1,	782,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_17_31"              ,	17,	15,	782,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	783,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	784,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	785,	"RO",	0,	0,	1ull,	1ull},
+	{"CV"                          ,	16,	4,	785,	"RO",	0,	0,	2ull,	2ull},
+	{"NCO"                         ,	20,	12,	785,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	786,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	786,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	786,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	786,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	786,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	786,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	786,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	786,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	786,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	786,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	786,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	786,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	786,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_21"              ,	21,	1,	786,	"RAZ",	1,	1,	0,	0},
+	{"UCIES"                       ,	22,	1,	786,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	786,	"RAZ",	1,	1,	0,	0},
+	{"UATOMBS"                     ,	24,	1,	786,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	786,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	787,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	787,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	787,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	787,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	787,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	787,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	787,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	787,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	787,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	787,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	787,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	787,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	787,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_21"              ,	21,	1,	787,	"RAZ",	1,	1,	0,	0},
+	{"UCIEM"                       ,	22,	1,	787,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_23_23"              ,	23,	1,	787,	"RAZ",	1,	1,	0,	0},
+	{"UATOMBM"                     ,	24,	1,	787,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	787,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	788,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	788,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	788,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	788,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	788,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	788,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	788,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	788,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	788,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	788,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	788,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	788,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	788,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_21"              ,	21,	1,	788,	"RO",	0,	0,	0ull,	0ull},
+	{"UCIES"                       ,	22,	1,	788,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_23_23"              ,	23,	1,	788,	"RO",	0,	0,	0ull,	0ull},
+	{"UATOMBS"                     ,	24,	1,	788,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	788,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	789,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	789,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	789,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	789,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	789,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	789,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	789,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	789,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CIES"                        ,	14,	1,	789,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_31"              ,	15,	17,	789,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	790,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	790,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	790,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	790,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	790,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	790,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	790,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	790,	"R/W",	0,	0,	1ull,	1ull},
+	{"CIEM"                        ,	14,	1,	790,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_15_31"              ,	15,	17,	790,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	791,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	791,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	791,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	791,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	791,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	791,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	792,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	793,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	794,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	795,	"RO",	0,	0,	0ull,	0ull},
+	{"CERE"                        ,	0,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFERE"                       ,	1,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"FERE"                        ,	2,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	796,	"RAZ",	1,	1,	0,	0},
+	{"ECR"                         ,	0,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_ECR"                   ,	1,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EFNFR"                       ,	2,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_EFNFR"                 ,	3,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FUF"                         ,	4,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFEMR"                       ,	5,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEMR"                        ,	6,	1,	797,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_26"               ,	7,	20,	797,	"RAZ",	1,	1,	0,	0},
+	{"AEIMN"                       ,	27,	5,	797,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECSI"                        ,	0,	16,	798,	"RO",	0,	0,	0ull,	0ull},
+	{"EFNFSI"                      ,	16,	16,	798,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	799,	"R/W",	0,	1,	4143ull,	0},
+	{"RTL"                         ,	16,	16,	799,	"R/W",	0,	1,	12429ull,	0},
+	{"OMR"                         ,	0,	32,	800,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	801,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_8_14"               ,	8,	7,	801,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	801,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	801,	"RO",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	802,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	802,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	802,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	802,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	802,	"R/W",	0,	0,	3ull,	3ull},
+	{"EASPML1"                     ,	30,	1,	802,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	802,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	803,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	803,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	803,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	803,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	803,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	803,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	803,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	803,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	803,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	803,	"R/W",	0,	0,	15ull,	3ull},
+	{"RESERVED_22_31"              ,	22,	10,	803,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	804,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	804,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	804,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	804,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	804,	"R/W",	0,	0,	0ull,	0ull},
+	{"MFUNCN"                      ,	0,	8,	805,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_13"               ,	8,	6,	805,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	805,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	805,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	805,	"R/W",	0,	0,	0ull,	0ull},
+	{"CX_NFUNC"                    ,	29,	3,	805,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPIV"                       ,	0,	11,	806,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	806,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	806,	"R/W",	0,	0,	1ull,	1ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	807,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	807,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_DABORT_4UCPL"              ,	2,	1,	807,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_HANDLE_FLUSH"              ,	3,	1,	807,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_31"               ,	4,	28,	807,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	808,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	809,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	810,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	810,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	810,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	811,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	811,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	811,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	812,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	812,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	812,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	813,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	813,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	813,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	813,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	814,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	814,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	814,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	814,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	815,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	815,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	815,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	815,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	816,	"R/W",	0,	0,	56ull,	56ull},
+	{"HEADER_CREDITS"              ,	12,	8,	816,	"R/W",	0,	0,	31ull,	31ull},
+	{"RESERVED_20_20"              ,	20,	1,	816,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	816,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	816,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	816,	"R/W",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	817,	"R/W",	0,	0,	13ull,	13ull},
+	{"HEADER_CREDITS"              ,	12,	8,	817,	"R/W",	0,	0,	31ull,	31ull},
+	{"RESERVED_20_20"              ,	20,	1,	817,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	817,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	817,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	818,	"R/W",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	818,	"R/W",	0,	0,	96ull,	96ull},
+	{"RESERVED_20_20"              ,	20,	1,	818,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	818,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	818,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	819,	"R/W",	0,	0,	183ull,	183ull},
+	{"RESERVED_14_15"              ,	14,	2,	819,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	819,	"R/W",	0,	0,	37ull,	37ull},
+	{"RESERVED_26_31"              ,	26,	6,	819,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	820,	"R/W",	0,	0,	97ull,	97ull},
+	{"RESERVED_14_15"              ,	14,	2,	820,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	820,	"R/W",	0,	0,	37ull,	37ull},
+	{"RESERVED_26_31"              ,	26,	6,	820,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	821,	"R/W",	0,	0,	398ull,	398ull},
+	{"RESERVED_14_15"              ,	14,	2,	821,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	821,	"R/W",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	821,	"RAZ",	1,	1,	0,	0},
+	{"N_FTS"                       ,	0,	8,	822,	"R/W",	0,	0,	128ull,	128ull},
+	{"LE"                          ,	8,	9,	822,	"R/W",	0,	0,	8ull,	8ull},
+	{"DSC"                         ,	17,	1,	822,	"R/W",	0,	0,	0ull,	0ull},
+	{"CPYTS"                       ,	18,	1,	822,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTCRB"                       ,	19,	1,	822,	"R/W",	0,	0,	0ull,	0ull},
+	{"S_D_E"                       ,	20,	1,	822,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	822,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	823,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"THRESH"                      ,	0,	4,	825,	"R/W",	0,	0,	0ull,	8ull},
+	{"FETCHSIZ"                    ,	4,	4,	825,	"R/W",	0,	0,	0ull,	7ull},
+	{"TXRD"                        ,	8,	10,	825,	"R/W",	0,	0,	0ull,	1ull},
+	{"USELDT"                      ,	18,	1,	825,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	825,	"RAZ",	1,	1,	0,	0},
+	{"RXST"                        ,	20,	10,	825,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_30_31"              ,	30,	2,	825,	"RAZ",	1,	1,	0,	0},
+	{"TXSLOTS"                     ,	32,	10,	825,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_42_43"              ,	42,	2,	825,	"RAZ",	1,	1,	0,	0},
+	{"RXSLOTS"                     ,	44,	10,	825,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_54_62"              ,	54,	9,	825,	"RAZ",	1,	1,	0,	0},
+	{"RDPEND"                      ,	63,	1,	825,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYNCMISSED"                 ,	0,	1,	826,	"R/W",	0,	0,	0ull,	1ull},
+	{"FSYNCEXTRA"                  ,	1,	1,	826,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXWRAP"                      ,	2,	1,	826,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXST"                        ,	3,	1,	826,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXWRAP"                      ,	4,	1,	826,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXRD"                        ,	5,	1,	826,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXEMPTY"                     ,	6,	1,	826,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXOVF"                       ,	7,	1,	826,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_8_63"               ,	8,	56,	826,	"RAZ",	1,	1,	0,	0},
+	{"FSYNCMISSED"                 ,	0,	1,	827,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FSYNCEXTRA"                  ,	1,	1,	827,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXWRAP"                      ,	2,	1,	827,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXST"                        ,	3,	1,	827,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXWRAP"                      ,	4,	1,	827,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXRD"                        ,	5,	1,	827,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXEMPTY"                     ,	6,	1,	827,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXOVF"                       ,	7,	1,	827,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	827,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	828,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	828,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	829,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	829,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	830,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	831,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	832,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	833,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	834,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	835,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	836,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	837,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	838,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	33,	838,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	838,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	1,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"USECLK1"                     ,	1,	1,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBFIRST"                    ,	2,	1,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	839,	"RAZ",	1,	1,	0,	0},
+	{"SAMPPT"                      ,	32,	16,	839,	"R/W",	0,	1,	0ull,	0},
+	{"DRVTIM"                      ,	48,	16,	839,	"R/W",	0,	1,	0ull,	0},
+	{"DEBUGINFO"                   ,	0,	64,	840,	"RO",	1,	1,	0,	0},
+	{"FRAM"                        ,	0,	3,	841,	"R/W",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	33,	841,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	841,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	842,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	842,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	843,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	844,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	845,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	846,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	847,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	848,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	849,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	850,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	851,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	33,	851,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	851,	"RAZ",	1,	1,	0,	0},
+	{"ENA"                         ,	0,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSYNCPOL"                    ,	1,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCLKPOL"                     ,	2,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITLEN"                      ,	3,	2,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXTRABIT"                    ,	5,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUMSLOTS"                    ,	6,	10,	852,	"R/W",	0,	1,	0ull,	0},
+	{"FSYNCLOC"                    ,	16,	5,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSYNCLEN"                    ,	21,	5,	852,	"R/W",	0,	0,	0ull,	2ull},
+	{"RESERVED_26_31"              ,	26,	6,	852,	"RAZ",	1,	1,	0,	0},
+	{"FSYNCSAMP"                   ,	32,	16,	852,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_62"              ,	48,	15,	852,	"RAZ",	1,	1,	0,	0},
+	{"FSYNCGOOD"                   ,	63,	1,	852,	"RO",	0,	0,	0ull,	1ull},
+	{"DEBUGINFO"                   ,	0,	64,	853,	"RO",	1,	1,	0,	0},
+	{"N"                           ,	0,	32,	854,	"R/W",	0,	1,	0ull,	0},
+	{"NUMSAMP"                     ,	32,	16,	854,	"R/W",	0,	1,	0ull,	0},
+	{"DELTASAMP"                   ,	48,	16,	854,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	855,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	855,	"R/W",	0,	0,	1ull,	1ull},
+	{"HFD"                         ,	6,	1,	855,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAUSE"                       ,	7,	2,	855,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	855,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	855,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	855,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NP"                          ,	15,	1,	855,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	855,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_11"               ,	0,	12,	856,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_THD"                    ,	12,	1,	856,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_TFD"                    ,	13,	1,	856,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_XHD"                    ,	14,	1,	856,	"RO",	0,	0,	1ull,	1ull},
+	{"THOU_XFD"                    ,	15,	1,	856,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	856,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	857,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	857,	"RO",	0,	0,	0ull,	0ull},
+	{"HFD"                         ,	6,	1,	857,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	7,	2,	857,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	857,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	857,	"RO",	0,	0,	0ull,	0ull},
+	{"ACK"                         ,	14,	1,	857,	"RO",	0,	1,	0ull,	0},
+	{"NP"                          ,	15,	1,	857,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	857,	"RAZ",	1,	1,	0,	0},
+	{"LINK_OK"                     ,	0,	1,	858,	"RO",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	1,	1,	858,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	2,	1,	858,	"RO",	0,	0,	0ull,	1ull},
+	{"SPD"                         ,	3,	2,	858,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	5,	2,	858,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	858,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD_EN"                   ,	0,	1,	859,	"R/W",	0,	0,	0ull,	1ull},
+	{"XMIT_EN"                     ,	1,	1,	859,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_ERR_EN"                   ,	2,	1,	859,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFU_EN"                   ,	3,	1,	859,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFO_EN"                   ,	4,	1,	859,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXBAD_EN"                    ,	5,	1,	859,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXERR_EN"                    ,	6,	1,	859,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	7,	1,	859,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXLOCK_EN"                   ,	8,	1,	859,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_BAD_EN"                   ,	9,	1,	859,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNC_BAD_EN"                 ,	10,	1,	859,	"R/W",	0,	0,	0ull,	1ull},
+	{"DUP"                         ,	11,	1,	859,	"R/W",	0,	0,	0ull,	1ull},
+	{"DBG_SYNC_EN"                 ,	12,	1,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	859,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD"                      ,	0,	1,	860,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	1,	1,	860,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_ERR"                      ,	2,	1,	860,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFU"                      ,	3,	1,	860,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFO"                      ,	4,	1,	860,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXBAD"                       ,	5,	1,	860,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXERR"                       ,	6,	1,	860,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	7,	1,	860,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXLOCK"                      ,	8,	1,	860,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	9,	1,	860,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	10,	1,	860,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	11,	1,	860,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBG_SYNC"                    ,	12,	1,	860,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	860,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	16,	861,	"R/W",	0,	1,	1094ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	861,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	862,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	862,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	862,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	862,	"RAZ",	1,	1,	0,	0},
+	{"SAMP_PT"                     ,	0,	7,	863,	"R/W",	0,	1,	1ull,	0},
+	{"AN_OVRD"                     ,	7,	1,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE"                        ,	8,	1,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAC_PHY"                     ,	9,	1,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK2"                    ,	10,	1,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMXENO"                      ,	11,	1,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"SGMII"                       ,	12,	1,	863,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	863,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	864,	"RAZ",	1,	1,	0,	0},
+	{"UNI"                         ,	5,	1,	864,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDMSB"                      ,	6,	1,	864,	"R/W",	0,	0,	1ull,	1ull},
+	{"COLTST"                      ,	7,	1,	864,	"R/W",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	8,	1,	864,	"R/W",	0,	0,	1ull,	1ull},
+	{"RST_AN"                      ,	9,	1,	864,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	864,	"RAZ",	1,	1,	0,	0},
+	{"PWR_DN"                      ,	11,	1,	864,	"R/W",	0,	0,	1ull,	0ull},
+	{"AN_EN"                       ,	12,	1,	864,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDLSB"                      ,	13,	1,	864,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK1"                    ,	14,	1,	864,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	864,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	864,	"RAZ",	1,	1,	0,	0},
+	{"EXTND"                       ,	0,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	865,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LNK_ST"                      ,	2,	1,	865,	"RO",	0,	0,	0ull,	1ull},
+	{"AN_ABIL"                     ,	3,	1,	865,	"RO",	0,	0,	1ull,	1ull},
+	{"RM_FLT"                      ,	4,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	5,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"PRB_SUP"                     ,	6,	1,	865,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_7"                ,	7,	1,	865,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EXT_ST"                      ,	8,	1,	865,	"RO",	0,	0,	1ull,	1ull},
+	{"HUN_T2HD"                    ,	9,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T2FD"                    ,	10,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_HD"                      ,	11,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_FD"                      ,	12,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XHD"                     ,	13,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XFD"                     ,	14,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T4"                      ,	15,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	865,	"RAZ",	1,	1,	0,	0},
+	{"AN_ST"                       ,	0,	4,	866,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	4,	1,	866,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	5,	4,	866,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	9,	1,	866,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_ST"                       ,	10,	5,	866,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_BAD"                      ,	15,	1,	866,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	866,	"RAZ",	1,	1,	0,	0},
+	{"BIT_LOCK"                    ,	0,	1,	867,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	1,	1,	867,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	867,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	868,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	868,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	868,	"R/W",	0,	0,	2ull,	2ull},
+	{"DUP"                         ,	12,	1,	868,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_13"              ,	13,	1,	868,	"RAZ",	0,	1,	0ull,	0},
+	{"ACK"                         ,	14,	1,	868,	"RO",	0,	0,	0ull,	0ull},
+	{"LINK"                        ,	15,	1,	868,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	868,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	869,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	869,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	869,	"RO",	0,	0,	0ull,	2ull},
+	{"DUP"                         ,	12,	1,	869,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_14"              ,	13,	2,	869,	"RAZ",	0,	1,	0ull,	0},
+	{"LINK"                        ,	15,	1,	869,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	869,	"RAZ",	1,	1,	0,	0},
+	{"ORD_ST"                      ,	0,	4,	870,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_BAD"                      ,	4,	1,	870,	"RO",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	5,	2,	870,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	870,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTORXPL"                    ,	2,	1,	871,	"RO",	0,	0,	0ull,	0ull},
+	{"RXOVRD"                      ,	3,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	871,	"RAZ",	1,	1,	0,	0},
+	{"ADDR_V"                      ,	0,	1,	872,	"R/W",	0,	1,	0ull,	0},
+	{"END_SWP"                     ,	1,	2,	872,	"R/W",	0,	1,	0ull,	0},
+	{"CA"                          ,	3,	1,	872,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR_IDX"                    ,	4,	16,	872,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	872,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	873,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	3,	35,	873,	"R/W",	0,	0,	34359738367ull,	34359738367ull},
+	{"RESERVED_38_63"              ,	38,	26,	873,	"RAZ",	1,	1,	0,	0},
+	{"BAR2_CAX"                    ,	0,	1,	874,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	1,	2,	874,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	3,	1,	874,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR1_SIZ"                    ,	4,	3,	874,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_63"               ,	7,	57,	874,	"RAZ",	1,	1,	0,	0},
+	{"SOT"                         ,	0,	1,	875,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR0"                      ,	1,	1,	875,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR1"                      ,	2,	1,	875,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA3"                     ,	3,	1,	875,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA2"                     ,	4,	1,	875,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA1"                     ,	5,	1,	875,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA0"                     ,	6,	1,	875,	"RO",	0,	0,	0ull,	0ull},
+	{"RETRY"                       ,	7,	1,	875,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	875,	"RAZ",	1,	1,	0,	0},
+	{"PPF"                         ,	0,	1,	876,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TC0"                     ,	1,	1,	876,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TCF1"                    ,	2,	1,	876,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TNF"                     ,	3,	1,	876,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF0"                    ,	4,	1,	876,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF1"                    ,	5,	1,	876,	"RO",	0,	0,	0ull,	0ull},
+	{"PEAI_P2E"                    ,	6,	1,	876,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_P"                       ,	7,	1,	876,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_N"                       ,	8,	1,	876,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_CPL"                     ,	9,	1,	876,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	876,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	32,	877,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	877,	"R/W",	0,	1,	0ull,	0},
+	{"ADDR"                        ,	0,	32,	878,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	878,	"R/W",	0,	1,	0ull,	0},
+	{"TAG"                         ,	0,	32,	879,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	879,	"RAZ",	1,	1,	0,	0},
+	{"INV_LCRC"                    ,	0,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_ECRC"                    ,	1,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAST_LM"                     ,	2,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_CTLP"                     ,	3,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_ENB"                     ,	4,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLY_ONE"                     ,	5,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"NF_ECRC"                     ,	6,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_8"                ,	7,	2,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"OB_P_CMD"                    ,	9,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XPME"                     ,	10,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XTOFF"                    ,	11,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	880,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CFG_RTRY"                    ,	16,	16,	880,	"R/W",	0,	0,	0ull,	32ull},
+	{"RESERVED_32_33"              ,	32,	2,	880,	"RAZ",	1,	1,	0,	0},
+	{"PBUS"                        ,	34,	8,	880,	"RO",	1,	1,	0,	0},
+	{"DNUM"                        ,	42,	5,	880,	"RO",	1,	1,	0,	0},
+	{"AUTO_SD"                     ,	47,	1,	880,	"RO",	1,	1,	0,	0},
+	{"RESERVED_48_63"              ,	48,	16,	880,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	881,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	881,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	882,	"RAZ",	1,	1,	0,	0},
+	{"AUX_EN"                      ,	0,	1,	883,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_EN"                       ,	1,	1,	883,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_STAT"                     ,	2,	1,	883,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_DST"                      ,	3,	1,	883,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	883,	"RO",	1,	1,	0,	0},
+	{"NUM"                         ,	0,	6,	884,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	884,	"RAZ",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"SE"                          ,	1,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEI"                        ,	2,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEM"                        ,	3,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B1"                       ,	4,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B2"                       ,	5,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_BX"                       ,	6,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B1"                       ,	7,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B2"                       ,	8,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_BX"                       ,	9,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"EXC"                         ,	10,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDLK"                        ,	11,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_ER"                      ,	12,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_DR"                      ,	13,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_14_63"              ,	14,	50,	885,	"RAZ",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"SE"                          ,	1,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEI"                        ,	2,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEM"                        ,	3,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B1"                       ,	4,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B2"                       ,	5,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_BX"                       ,	6,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B1"                       ,	7,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B2"                       ,	8,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_BX"                       ,	9,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"EXC"                         ,	10,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDLK"                        ,	11,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_ER"                      ,	12,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_DR"                      ,	13,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_14_63"              ,	14,	50,	886,	"RAZ",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"SE"                          ,	1,	1,	887,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PMEI"                        ,	2,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEM"                        ,	3,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"UP_B1"                       ,	4,	1,	887,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UP_B2"                       ,	5,	1,	887,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UP_BX"                       ,	6,	1,	887,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_B1"                       ,	7,	1,	887,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_B2"                       ,	8,	1,	887,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_BX"                       ,	9,	1,	887,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EXC"                         ,	10,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"RDLK"                        ,	11,	1,	887,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS_ER"                      ,	12,	1,	887,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS_DR"                      ,	13,	1,	887,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	887,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_13"               ,	0,	14,	888,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	14,	50,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_25"               ,	0,	26,	889,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	26,	38,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_40"               ,	0,	41,	890,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	41,	23,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLI_P"                       ,	0,	8,	891,	"R/W",	0,	0,	128ull,	128ull},
+	{"SLI_NP"                      ,	8,	8,	891,	"R/W",	0,	0,	16ull,	16ull},
+	{"SLI_CPL"                     ,	16,	8,	891,	"R/W",	0,	0,	128ull,	128ull},
+	{"RESERVED_24_47"              ,	24,	24,	891,	"RAZ",	1,	1,	0,	0},
+	{"PEAI_PPF"                    ,	48,	8,	891,	"R/W",	0,	0,	128ull,	128ull},
+	{"RESERVED_56_63"              ,	56,	8,	891,	"RAZ",	1,	1,	0,	0},
+	{"SKIP1"                       ,	0,	7,	892,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	892,	"RAZ",	1,	1,	0,	0},
+	{"SKIP2"                       ,	8,	7,	892,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	892,	"RAZ",	1,	1,	0,	0},
+	{"SKIP3"                       ,	16,	7,	892,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_31"              ,	23,	9,	892,	"RAZ",	1,	1,	0,	0},
+	{"BIT0"                        ,	32,	6,	892,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_39"              ,	38,	2,	892,	"RAZ",	1,	1,	0,	0},
+	{"BIT1"                        ,	40,	6,	892,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_46_55"              ,	46,	10,	892,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	56,	1,	892,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_57_63"              ,	57,	7,	892,	"RAZ",	1,	1,	0,	0},
+	{"LOWATER"                     ,	0,	5,	893,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_5_7"                ,	5,	3,	893,	"RAZ",	0,	1,	0ull,	0},
+	{"HIWATER"                     ,	8,	5,	893,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_13_62"              ,	13,	50,	893,	"RAZ",	0,	1,	0ull,	0},
+	{"BCKPRS"                      ,	63,	1,	893,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	20,	894,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	894,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	895,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_15"               ,	7,	9,	895,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	16,	9,	895,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_25_31"              ,	25,	7,	895,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	32,	8,	895,	"R/W",	0,	1,	0ull,	0},
+	{"UPPER_TAG"                   ,	40,	16,	895,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	895,	"RAZ",	1,	1,	0,	0},
+	{"POS0"                        ,	0,	7,	896,	"R/W",	0,	1,	0ull,	0},
+	{"POS0_VAL"                    ,	7,	1,	896,	"R/W",	0,	1,	0ull,	0},
+	{"POS1"                        ,	8,	7,	896,	"R/W",	0,	1,	0ull,	0},
+	{"POS1_VAL"                    ,	15,	1,	896,	"R/W",	0,	1,	0ull,	0},
+	{"POS2"                        ,	16,	7,	896,	"R/W",	0,	1,	0ull,	0},
+	{"POS2_VAL"                    ,	23,	1,	896,	"R/W",	0,	1,	0ull,	0},
+	{"POS3"                        ,	24,	7,	896,	"R/W",	0,	1,	0ull,	0},
+	{"POS3_VAL"                    ,	31,	1,	896,	"R/W",	0,	1,	0ull,	0},
+	{"POS4"                        ,	32,	7,	896,	"R/W",	0,	1,	0ull,	0},
+	{"POS4_VAL"                    ,	39,	1,	896,	"R/W",	0,	1,	0ull,	0},
+	{"POS5"                        ,	40,	7,	896,	"R/W",	0,	1,	0ull,	0},
+	{"POS5_VAL"                    ,	47,	1,	896,	"R/W",	0,	1,	0ull,	0},
+	{"POS6"                        ,	48,	7,	896,	"R/W",	0,	1,	0ull,	0},
+	{"POS6_VAL"                    ,	55,	1,	896,	"R/W",	0,	1,	0ull,	0},
+	{"POS7"                        ,	56,	7,	896,	"R/W",	0,	1,	0ull,	0},
+	{"POS7_VAL"                    ,	63,	1,	896,	"R/W",	0,	1,	0ull,	0},
+	{"QOS"                         ,	0,	3,	897,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_7"                ,	3,	5,	897,	"RAZ",	1,	1,	0,	0},
+	{"TT"                          ,	8,	2,	897,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	897,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	16,	4,	897,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	897,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	32,	8,	897,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_59"              ,	40,	20,	897,	"RAZ",	1,	1,	0,	0},
+	{"QOS_EN"                      ,	60,	1,	897,	"R/W",	0,	1,	0ull,	0},
+	{"TT_EN"                       ,	61,	1,	897,	"R/W",	0,	1,	0ull,	0},
+	{"GRP_EN"                      ,	62,	1,	897,	"R/W",	0,	1,	0ull,	0},
+	{"TAG_EN"                      ,	63,	1,	897,	"R/W",	0,	1,	0ull,	0},
+	{"CLKEN"                       ,	0,	1,	898,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	898,	"RAZ",	0,	1,	0ull,	0},
+	{"DPRT"                        ,	0,	16,	899,	"R/W",	0,	0,	0ull,	0ull},
+	{"UDP"                         ,	16,	1,	899,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP"                         ,	17,	1,	899,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	899,	"RAZ",	1,	1,	0,	0},
+	{"MAP0"                        ,	0,	4,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP0"                        ,	0,	4,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINLEN"                      ,	0,	16,	902,	"R/W",	0,	0,	64ull,	64ull},
+	{"MAXLEN"                      ,	16,	16,	902,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_32_63"              ,	32,	32,	902,	"RAZ",	1,	1,	0,	0},
+	{"NIP_SHF"                     ,	0,	3,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	903,	"RAZ",	1,	1,	0,	0},
+	{"RAW_SHF"                     ,	8,	3,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	903,	"RAZ",	1,	1,	0,	0},
+	{"MAX_L2"                      ,	16,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_UDP"                     ,	17,	1,	903,	"R/W",	0,	0,	1ull,	1ull},
+	{"TAG_SYN"                     ,	18,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	903,	"RAZ",	1,	1,	0,	0},
+	{"IP_CHK"                      ,	0,	1,	904,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_MAL"                      ,	1,	1,	904,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_HOP"                      ,	2,	1,	904,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP4_OPTS"                    ,	3,	1,	904,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP6_EEXT"                    ,	4,	2,	904,	"R/W",	0,	0,	1ull,	3ull},
+	{"RESERVED_6_7"                ,	6,	2,	904,	"RAZ",	1,	1,	0,	0},
+	{"L4_MAL"                      ,	8,	1,	904,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_PRT"                      ,	9,	1,	904,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_CHK"                      ,	10,	1,	904,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_LEN"                      ,	11,	1,	904,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCP_FLAG"                    ,	12,	1,	904,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2_MAL"                      ,	13,	1,	904,	"R/W",	0,	0,	1ull,	1ull},
+	{"VS_QOS"                      ,	14,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"VS_WQE"                      ,	15,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNRS"                       ,	16,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	904,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RING_EN"                     ,	20,	1,	904,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_21_23"              ,	21,	3,	904,	"RAZ",	1,	1,	0,	0},
+	{"DSA_GRP_SID"                 ,	24,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_SCMD"                ,	25,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_TVID"                ,	26,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"IHMSK_DIS"                   ,	27,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	904,	"RAZ",	1,	1,	0,	0},
+	{"PRI"                         ,	0,	6,	905,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	905,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	8,	3,	905,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	905,	"RAZ",	1,	1,	0,	0},
+	{"UP_QOS"                      ,	12,	1,	905,	"RAZ",	0,	1,	0ull,	0},
+	{"RESERVED_13_63"              ,	13,	51,	905,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	906,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	907,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	3,	908,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	908,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	909,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	2,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_EN"                      ,	10,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"HIGIG_EN"                    ,	11,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRC_EN"                      ,	12,	1,	909,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	909,	"RAZ",	1,	1,	0,	0},
+	{"QOS_VLAN"                    ,	16,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_DIFF"                    ,	17,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VOD"                     ,	18,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VSEL"                    ,	19,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_WAT"                     ,	20,	4,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS"                         ,	24,	3,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_QOS"                      ,	27,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT"                     ,	28,	4,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"INST_HDR"                    ,	32,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"DYN_RS"                      ,	33,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_INC"                     ,	34,	2,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWDRP"                      ,	36,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	909,	"RAZ",	1,	1,	0,	0},
+	{"QOS_WAT_47"                  ,	40,	4,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT_47"                  ,	44,	4,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR_EN"                   ,	48,	1,	909,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR_EN"                   ,	49,	1,	909,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR_EN"                   ,	50,	1,	909,	"R/W",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	51,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	52,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_63"              ,	53,	11,	909,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	910,	"RAZ",	1,	1,	0,	0},
+	{"BSEL_EN"                     ,	32,	1,	910,	"R/W",	0,	0,	0ull,	0ull},
+	{"BSEL_NUM"                    ,	33,	2,	910,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_35"              ,	35,	1,	910,	"RAZ",	1,	1,	0,	0},
+	{"ALT_SKP_EN"                  ,	36,	1,	910,	"R/W",	0,	1,	0ull,	0},
+	{"ALT_SKP_SEL"                 ,	37,	2,	910,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_39_63"              ,	39,	25,	910,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	0,	4,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"NON_TAG_TYPE"                ,	4,	2,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_TAG_TYPE"                ,	6,	2,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_TAG_TYPE"                ,	8,	2,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP4_TAG_TYPE"               ,	10,	2,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP6_TAG_TYPE"               ,	12,	2,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SRC_FLAG"                ,	14,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SRC_FLAG"                ,	15,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DST_FLAG"                ,	16,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DST_FLAG"                ,	17,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_PCTL_FLAG"               ,	18,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_NXTH_FLAG"               ,	19,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SPRT_FLAG"               ,	20,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SPRT_FLAG"               ,	21,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DPRT_FLAG"               ,	22,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DPRT_FLAG"               ,	23,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_PRT_FLAG"                ,	24,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VLAN"                    ,	25,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VS"                      ,	26,	2,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_MODE"                    ,	28,	2,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG_MSKIP"                ,	30,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG"                      ,	31,	1,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGMASK"                  ,	32,	4,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGBASE"                  ,	36,	4,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	911,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	912,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	913,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	913,	"RAZ",	1,	1,	0,	0},
+	{"QOS1"                        ,	4,	3,	913,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	913,	"RAZ",	1,	1,	0,	0},
+	{"MATCH_VALUE"                 ,	0,	16,	914,	"R/W",	0,	0,	0ull,	0ull},
+	{"MATCH_TYPE"                  ,	16,	3,	914,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	914,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	20,	3,	914,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	914,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	24,	4,	914,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	914,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	32,	16,	914,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	914,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	0,	56,	915,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	915,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	0,	1,	916,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	916,	"RAZ",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	917,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	917,	"R/W",	0,	1,	0ull,	0},
+	{"MCAST"                       ,	0,	32,	918,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	918,	"R/W",	0,	1,	0ull,	0},
+	{"MCAST"                       ,	0,	32,	919,	"R/W",	0,	1,	0ull,	0},
+	{"BCAST"                       ,	32,	32,	919,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	920,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	920,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	921,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	921,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	922,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	922,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	923,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	923,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	924,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	924,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	925,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	925,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	926,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	926,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	927,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	927,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	928,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	928,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	929,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	929,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	930,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	930,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	931,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	931,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	932,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	932,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	933,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	933,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	934,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	934,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	935,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	935,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	936,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	936,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	936,	"RO",	1,	1,	0,	0},
+	{"TYPE0"                       ,	0,	16,	937,	"R/W",	0,	0,	33024ull,	33024ull},
+	{"TYPE1"                       ,	16,	16,	937,	"R/W",	0,	0,	33024ull,	33024ull},
+	{"TYPE2"                       ,	32,	16,	937,	"R/W",	0,	0,	33024ull,	33024ull},
+	{"TYPE3"                       ,	48,	16,	937,	"R/W",	0,	0,	33024ull,	33024ull},
+	{"COUNT"                       ,	0,	32,	938,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	938,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	939,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	939,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	940,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	940,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	940,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	940,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	941,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	941,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	941,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	941,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	941,	"RO",	1,	0,	0,	0ull},
+	{"PTRS2"                       ,	0,	17,	942,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	942,	"RAZ",	1,	1,	0,	0},
+	{"PTRS1"                       ,	32,	17,	942,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	942,	"RAZ",	1,	1,	0,	0},
+	{"MOD"                         ,	0,	3,	943,	"RO",	1,	0,	0,	0ull},
+	{"CNT"                         ,	3,	13,	943,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	16,	1,	943,	"RO",	1,	0,	0,	0ull},
+	{"LEN"                         ,	17,	1,	943,	"RO",	1,	0,	0,	0ull},
+	{"SOP"                         ,	18,	1,	943,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	19,	3,	943,	"RO",	1,	0,	0,	0ull},
+	{"MAJ"                         ,	22,	1,	943,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	943,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	944,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	944,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	944,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	944,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	945,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	945,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	945,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	945,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	945,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	946,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	947,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	947,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	947,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	947,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	947,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	948,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	3,	949,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	3,	2,	949,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	5,	1,	949,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	6,	1,	949,	"RO",	1,	0,	0,	0ull},
+	{"CHK_ONCE"                    ,	7,	1,	949,	"RO",	1,	0,	0,	0ull},
+	{"INIT_DWRITE"                 ,	8,	1,	949,	"RO",	1,	0,	0,	0ull},
+	{"DREAD_SOP"                   ,	9,	1,	949,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	10,	2,	949,	"RO",	1,	0,	0,	0ull},
+	{"CMND_OFF"                    ,	12,	6,	949,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	18,	16,	949,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	34,	6,	949,	"RO",	1,	0,	0,	0ull},
+	{"CURR_OFF"                    ,	40,	16,	949,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	56,	8,	949,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	0,	8,	950,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	8,	40,	950,	"RO",	1,	0,	0,	0ull},
+	{"NXT_INFLT"                   ,	48,	6,	950,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR_3"                     ,	54,	1,	950,	"RO",	1,	0,	0,	0ull},
+	{"PTP"                         ,	55,	1,	950,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	950,	"RAZ",	1,	1,	0,	0},
+	{"QID_BASE"                    ,	0,	8,	951,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	8,	4,	951,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFMAX"                  ,	12,	4,	951,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	16,	5,	951,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	21,	3,	951,	"RO",	1,	0,	0,	0ull},
+	{"STATC"                       ,	24,	1,	951,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	25,	1,	951,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTED"                   ,	26,	1,	951,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	27,	1,	951,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	951,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFTHS"                  ,	29,	4,	951,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFRES"                  ,	33,	4,	951,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	951,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	6,	952,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	6,	6,	952,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	12,	33,	952,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	45,	13,	952,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	58,	1,	952,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	59,	5,	952,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	3,	953,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	3,	1,	953,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	4,	1,	953,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	5,	1,	953,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	6,	1,	953,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	953,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	8,	20,	953,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	953,	"RO",	1,	0,	0,	0ull},
+	{"QID_IDX"                     ,	29,	4,	953,	"RO",	1,	1,	0,	0},
+	{"RESERVED_33_33"              ,	33,	1,	953,	"RAZ",	1,	1,	0,	0},
+	{"QID_QQOS"                    ,	34,	8,	953,	"RO",	1,	1,	0,	0},
+	{"RESERVED_42_63"              ,	42,	22,	953,	"RAZ",	1,	1,	0,	0},
+	{"PTRS3"                       ,	0,	17,	954,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	954,	"RAZ",	1,	1,	0,	0},
+	{"PTRS0"                       ,	32,	17,	954,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	954,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	955,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	955,	"R/W",	1,	0,	0,	0ull},
+	{"BP_PORT"                     ,	10,	6,	955,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_52"              ,	16,	37,	955,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	955,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	61,	1,	955,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	955,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	956,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	956,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_10_52"              ,	10,	43,	956,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	956,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	956,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	957,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	957,	"RAZ",	1,	1,	0,	0},
+	{"RATE_PKT"                    ,	8,	24,	957,	"R/W",	1,	0,	0,	0ull},
+	{"RATE_WORD"                   ,	32,	19,	957,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	957,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	958,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	958,	"RAZ",	1,	1,	0,	0},
+	{"RATE_LIM"                    ,	8,	24,	958,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	958,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE"                       ,	0,	7,	959,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	7,	6,	959,	"WR0",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	13,	3,	959,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	16,	1,	959,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	17,	36,	959,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	959,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	959,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	959,	"R/W",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	959,	"R/W",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	7,	960,	"R/W",	1,	0,	0,	0ull},
+	{"PID"                         ,	7,	6,	960,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	960,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	960,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	960,	"RAZ",	1,	1,	0,	0},
+	{"DAT_PTR"                     ,	0,	4,	961,	"RO",	1,	0,	0,	0ull},
+	{"DAT_DAT"                     ,	4,	2,	961,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CTL"                     ,	6,	2,	961,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QSB"                     ,	8,	3,	961,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QCB"                     ,	11,	2,	961,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	13,	2,	961,	"RO",	1,	0,	0,	0ull},
+	{"PRT_PSB"                     ,	15,	8,	961,	"RO",	1,	0,	0,	0ull},
+	{"PRT_NXT"                     ,	23,	1,	961,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CHK"                     ,	24,	3,	961,	"RO",	1,	0,	0,	0ull},
+	{"OUT_WIF"                     ,	27,	1,	961,	"RO",	1,	0,	0,	0ull},
+	{"OUT_STA"                     ,	28,	1,	961,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CTL"                     ,	29,	3,	961,	"RO",	1,	0,	0,	0ull},
+	{"OUT_DAT"                     ,	32,	1,	961,	"RO",	1,	0,	0,	0ull},
+	{"IOB"                         ,	33,	1,	961,	"RO",	1,	0,	0,	0ull},
+	{"CSR"                         ,	34,	1,	961,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	961,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	13,	962,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	962,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	962,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	962,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	64,	963,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	964,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	965,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	966,	"RO",	0,	0,	0ull,	0ull},
+	{"ENGINE0"                     ,	0,	4,	967,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE1"                     ,	4,	4,	967,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE2"                     ,	8,	4,	967,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE3"                     ,	12,	4,	967,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE4"                     ,	16,	4,	967,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE5"                     ,	20,	4,	967,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE6"                     ,	24,	4,	967,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE7"                     ,	28,	4,	967,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE8"                     ,	32,	4,	967,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE9"                     ,	36,	4,	967,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE10"                    ,	40,	4,	967,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE11"                    ,	44,	4,	967,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE12"                    ,	48,	4,	967,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE13"                    ,	52,	4,	967,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_56_63"              ,	56,	8,	967,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	14,	968,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	968,	"RAZ",	1,	1,	0,	0},
+	{"PARITY"                      ,	0,	1,	969,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	969,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	969,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	969,	"RAZ",	1,	1,	0,	0},
+	{"ENA_PKO"                     ,	0,	1,	970,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	970,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	970,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	970,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_6"                ,	4,	3,	970,	"RAZ",	1,	1,	0,	0},
+	{"DIS_PERF2"                   ,	7,	1,	970,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIS_PERF3"                   ,	8,	1,	970,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	970,	"RAZ",	1,	1,	0,	0},
+	{"MODE0"                       ,	0,	3,	971,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE1"                       ,	3,	3,	971,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	971,	"RAZ",	1,	1,	0,	0},
+	{"PARITY"                      ,	0,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	972,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	16,	973,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	973,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	974,	"RAZ",	1,	1,	0,	0},
+	{"PREEMPTER"                   ,	0,	1,	975,	"R/W",	0,	0,	0ull,	0ull},
+	{"PREEMPTEE"                   ,	1,	1,	975,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	975,	"RAZ",	1,	1,	0,	0},
+	{"QID7"                        ,	0,	1,	976,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDX3"                        ,	1,	1,	976,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	976,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	977,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	977,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	977,	"RAZ",	1,	1,	0,	0},
+	{"WQE_WORD"                    ,	0,	4,	978,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_4_63"               ,	4,	60,	978,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	1,	979,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND"                        ,	1,	1,	979,	"RO",	0,	0,	0ull,	0ull},
+	{"FIDX"                        ,	2,	1,	979,	"RO",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	3,	1,	979,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT"                         ,	4,	4,	979,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR"                         ,	8,	3,	979,	"RO",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	11,	1,	979,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	979,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	16,	4,	979,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	979,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	32,	980,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	980,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	981,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	981,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE_IE"                      ,	2,	1,	981,	"R/W",	0,	1,	0ull,	0},
+	{"DBE_IE"                      ,	3,	1,	981,	"R/W",	0,	1,	0ull,	0},
+	{"SYN"                         ,	4,	5,	981,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_11"               ,	9,	3,	981,	"RAZ",	1,	1,	0,	0},
+	{"RPE"                         ,	12,	1,	981,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE_IE"                      ,	13,	1,	981,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	981,	"RAZ",	1,	1,	0,	0},
+	{"IOP"                         ,	16,	13,	981,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	981,	"RAZ",	1,	1,	0,	0},
+	{"IOP_IE"                      ,	32,	13,	981,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_63"              ,	45,	19,	981,	"RAZ",	1,	1,	0,	0},
+	{"NBR_THR"                     ,	0,	5,	982,	"R/W",	0,	0,	2ull,	2ull},
+	{"PFR_DIS"                     ,	5,	1,	982,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	982,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	983,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	983,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	984,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	984,	"RAZ",	1,	1,	0,	0},
+	{"IQ_INT"                      ,	0,	8,	985,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	985,	"RAZ",	1,	1,	0,	0},
+	{"INT_EN"                      ,	0,	8,	986,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	986,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	32,	987,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	987,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	10,	988,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	988,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	989,	"R/W",	0,	0,	0ull,	4ull},
+	{"RESERVED_10_63"              ,	10,	54,	989,	"RAZ",	1,	1,	0,	0},
+	{"RST_MSK"                     ,	0,	8,	990,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	990,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	16,	991,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"QOS0_PRI"                    ,	16,	4,	991,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1_PRI"                    ,	20,	4,	991,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2_PRI"                    ,	24,	4,	991,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3_PRI"                    ,	28,	4,	991,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4_PRI"                    ,	32,	4,	991,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5_PRI"                    ,	36,	4,	991,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6_PRI"                    ,	40,	4,	991,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7_PRI"                    ,	44,	4,	991,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	991,	"RAZ",	1,	1,	0,	0},
+	{"RND"                         ,	0,	8,	992,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P1"                      ,	8,	8,	992,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P2"                      ,	16,	8,	992,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P3"                      ,	24,	8,	992,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	992,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	9,	993,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	993,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	12,	9,	993,	"R/W",	0,	1,	511ull,	0},
+	{"RESERVED_21_23"              ,	21,	3,	993,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	24,	10,	993,	"RO",	0,	1,	503ull,	0},
+	{"RESERVED_34_35"              ,	34,	2,	993,	"RAZ",	1,	1,	0,	0},
+	{"BUF_CNT"                     ,	36,	10,	993,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	993,	"RAZ",	1,	1,	0,	0},
+	{"DES_CNT"                     ,	48,	10,	993,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	993,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	32,	994,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	994,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	995,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	995,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	996,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	996,	"RAZ",	1,	1,	0,	0},
+	{"WQ_INT"                      ,	0,	16,	997,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_DIS"                      ,	16,	16,	997,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	997,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	10,	998,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_11"              ,	10,	2,	998,	"RAZ",	1,	1,	0,	0},
+	{"DS_CNT"                      ,	12,	10,	998,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_22_23"              ,	22,	2,	998,	"RAZ",	1,	1,	0,	0},
+	{"TC_CNT"                      ,	24,	4,	998,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	998,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	999,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	999,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	999,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	999,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	999,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	9,	1000,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	1000,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	12,	9,	1000,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_23"              ,	21,	3,	1000,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	24,	4,	1000,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	28,	1,	1000,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	1000,	"RAZ",	1,	1,	0,	0},
+	{"WS_PC"                       ,	0,	32,	1001,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1001,	"RAZ",	1,	1,	0,	0},
+	{"IWORD"                       ,	0,	64,	1002,	"RO",	1,	1,	0,	0},
+	{"P_DAT"                       ,	0,	64,	1003,	"RO",	1,	1,	0,	0},
+	{"Q_DAT"                       ,	0,	64,	1004,	"RO",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	2,	1005,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	2,	2,	1005,	"RO",	1,	0,	0,	0ull},
+	{"NCB_OUB"                     ,	4,	1,	1005,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	5,	1,	1005,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1005,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	33,	13,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"POOL"                        ,	46,	3,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"DWB"                         ,	49,	9,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	1006,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	1007,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STORE_LE"                    ,	1,	1,	1007,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_READ"                    ,	2,	4,	1007,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_6_63"               ,	6,	58,	1007,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	0,	5,	1008,	"RO",	1,	1,	0,	0},
+	{"COMMIT"                      ,	5,	1,	1008,	"RO",	1,	1,	0,	0},
+	{"OWORDPV"                     ,	6,	1,	1008,	"RO",	1,	1,	0,	0},
+	{"OWORDQV"                     ,	7,	1,	1008,	"RO",	1,	1,	0,	0},
+	{"IWIDX"                       ,	8,	6,	1008,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	1008,	"RO",	1,	1,	0,	0},
+	{"IRIDX"                       ,	16,	6,	1008,	"RO",	1,	1,	0,	0},
+	{"RESERVED_22_31"              ,	22,	10,	1008,	"RO",	1,	1,	0,	0},
+	{"LOOP"                        ,	32,	25,	1008,	"RO",	1,	1,	0,	0},
+	{"RESERVED_57_63"              ,	57,	7,	1008,	"RO",	1,	1,	0,	0},
+	{"CWORD"                       ,	0,	64,	1009,	"RO",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	1010,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	1010,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	1010,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	1011,	"RO",	1,	1,	0,	0},
+	{"SOD"                         ,	8,	1,	1011,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	9,	1,	1011,	"RO",	1,	1,	0,	0},
+	{"WC"                          ,	10,	1,	1011,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	11,	1,	1011,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	12,	1,	1011,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	1011,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	15,	1012,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	1012,	"RAZ",	1,	1,	0,	0},
+	{"OWORDP"                      ,	0,	64,	1013,	"RO",	1,	1,	0,	0},
+	{"OWORDQ"                      ,	0,	64,	1014,	"RO",	1,	1,	0,	0},
+	{"RWORD"                       ,	0,	64,	1015,	"RO",	1,	1,	0,	0},
+	{"N0CREDS"                     ,	0,	4,	1016,	"RO",	0,	0,	8ull,	0ull},
+	{"N1CREDS"                     ,	4,	4,	1016,	"RO",	0,	0,	8ull,	0ull},
+	{"POWCREDS"                    ,	8,	2,	1016,	"RO",	0,	0,	2ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	1016,	"RAZ",	1,	1,	0,	0},
+	{"FPACREDS"                    ,	12,	2,	1016,	"RO",	0,	0,	1ull,	0ull},
+	{"WCCREDS"                     ,	14,	2,	1016,	"RO",	0,	0,	0ull,	0ull},
+	{"NIWIDX0"                     ,	16,	4,	1016,	"RO",	1,	1,	0,	0},
+	{"NIRIDX0"                     ,	20,	4,	1016,	"RO",	1,	1,	0,	0},
+	{"NIWIDX1"                     ,	24,	4,	1016,	"RO",	1,	1,	0,	0},
+	{"NIRIDX1"                     ,	28,	4,	1016,	"RO",	1,	1,	0,	0},
+	{"NIRVAL6"                     ,	32,	5,	1016,	"RO",	1,	1,	0,	0},
+	{"NIRARB6"                     ,	37,	1,	1016,	"RO",	1,	1,	0,	0},
+	{"NIRQUE6"                     ,	38,	2,	1016,	"RO",	1,	1,	0,	0},
+	{"NIROPC6"                     ,	40,	3,	1016,	"RO",	1,	1,	0,	0},
+	{"NIRVAL7"                     ,	43,	5,	1016,	"RO",	1,	1,	0,	0},
+	{"NIRQUE7"                     ,	48,	2,	1016,	"RO",	1,	1,	0,	0},
+	{"NIROPC7"                     ,	50,	3,	1016,	"RO",	1,	1,	0,	0},
+	{"RESERVED_53_63"              ,	53,	11,	1016,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	1017,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	1017,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	56,	8,	1017,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	15,	1018,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	1018,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	1019,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	1019,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	1019,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	1020,	"RO",	1,	1,	0,	0},
+	{"MUL"                         ,	8,	8,	1020,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	16,	1,	1020,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	17,	1,	1020,	"RO",	1,	1,	0,	0},
+	{"INI"                         ,	18,	1,	1020,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	19,	1,	1020,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_63"              ,	20,	44,	1020,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1021,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1021,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1022,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1022,	"RAZ",	1,	1,	0,	0},
+	{"COEFFS"                      ,	0,	8,	1023,	"R/W",	0,	0,	29ull,	29ull},
+	{"RESERVED_8_63"               ,	8,	56,	1023,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	0,	16,	1024,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	16,	16,	1024,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1024,	"RAZ",	1,	1,	0,	0},
+	{"MEM"                         ,	0,	1,	1025,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	1025,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1025,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	1026,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	1026,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	1026,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	1026,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXP_ENT"                     ,	4,	1,	1026,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENT_SEL"                     ,	5,	4,	1026,	"R/W",	0,	0,	0ull,	0ull},
+	{"EER_VAL"                     ,	9,	1,	1026,	"RO",	0,	0,	0ull,	0ull},
+	{"EER_LCK"                     ,	10,	1,	1026,	"RO",	0,	0,	0ull,	0ull},
+	{"DIS_MAK"                     ,	11,	1,	1026,	"R/W1",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	1026,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	1027,	"RO",	1,	1,	0,	0},
+	{"KEY"                         ,	0,	64,	1028,	"WO",	0,	0,	0ull,	0ull},
+	{"DAT"                         ,	0,	64,	1029,	"RO",	1,	1,	0,	0},
+	{"NCB_CMD"                     ,	0,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"MSI"                         ,	1,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI0_0"                      ,	2,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI0_1"                      ,	3,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI1_0"                      ,	4,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI1_1"                      ,	5,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_8"                ,	6,	3,	1030,	"RAZ",	1,	1,	0,	0},
+	{"P2N1_P1"                     ,	9,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_P0"                     ,	10,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_N"                      ,	11,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C1"                     ,	12,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C0"                     ,	13,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P1"                     ,	14,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P0"                     ,	15,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_N"                      ,	16,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C1"                     ,	17,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C0"                     ,	18,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_24"              ,	19,	6,	1030,	"RAZ",	1,	1,	0,	0},
+	{"CPL_P1"                      ,	25,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"CPL_P0"                      ,	26,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_28"              ,	27,	2,	1030,	"RAZ",	1,	1,	0,	0},
+	{"N2P0_O"                      ,	29,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_C"                      ,	30,	1,	1030,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	1030,	"RAZ",	1,	1,	0,	0},
+	{"WAIT_COM"                    ,	0,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_4"                ,	1,	4,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTLP_RO"                     ,	5,	1,	1031,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTLP_RO"                     ,	7,	1,	1031,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTA_MAP"                    ,	8,	2,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTB_MAP"                    ,	10,	2,	1031,	"R/W",	0,	0,	1ull,	1ull},
+	{"INTC_MAP"                    ,	12,	2,	1031,	"R/W",	0,	0,	2ull,	2ull},
+	{"INTD_MAP"                    ,	14,	2,	1031,	"R/W",	0,	0,	3ull,	3ull},
+	{"WAITL_COM"                   ,	16,	1,	1031,	"R/W",	0,	1,	0ull,	0},
+	{"DIS_PORT"                    ,	17,	1,	1031,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTA"                        ,	18,	1,	1031,	"RO",	0,	0,	1ull,	1ull},
+	{"INTB"                        ,	19,	1,	1031,	"RO",	0,	0,	1ull,	1ull},
+	{"INTC"                        ,	20,	1,	1031,	"RO",	0,	0,	1ull,	1ull},
+	{"INTD"                        ,	21,	1,	1031,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	1031,	"RAZ",	1,	1,	0,	0},
+	{"CHIP_REV"                    ,	0,	8,	1032,	"RO",	1,	1,	0,	0},
+	{"P0_NTAGS"                    ,	8,	6,	1032,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_14_63"              ,	14,	50,	1032,	"R/W",	0,	0,	32ull,	32ull},
+	{"P0_FCNT"                     ,	0,	6,	1033,	"RO",	0,	1,	0ull,	0},
+	{"P0_UCNT"                     ,	6,	16,	1033,	"RO",	0,	1,	0ull,	0},
+	{"P1_FCNT"                     ,	22,	6,	1033,	"RAZ",	0,	1,	0ull,	0},
+	{"P1_UCNT"                     ,	28,	16,	1033,	"RAZ",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	1033,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	1034,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	1034,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	1034,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	32,	1035,	"R/W",	0,	1,	0ull,	0},
+	{"ADBG_SEL"                    ,	32,	1,	1035,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	1035,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1036,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1036,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1037,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	32,	1037,	"R/W",	0,	1,	0ull,	0},
+	{"TIM"                         ,	0,	32,	1038,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1038,	"RAZ",	1,	1,	0,	0},
+	{"RML_TO"                      ,	0,	1,	1039,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	1039,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	1039,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	1039,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	4,	1,	1039,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	5,	1,	1039,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	1039,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UP_WI"                    ,	9,	1,	1039,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_B0"                    ,	10,	1,	1039,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_WI"                    ,	11,	1,	1039,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_B0"                    ,	12,	1,	1039,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_WI"                    ,	13,	1,	1039,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_B0"                    ,	14,	1,	1039,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_WI"                    ,	15,	1,	1039,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT0"                    ,	16,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO_INT1"                    ,	17,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"M2_UP_B0"                    ,	20,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"M2_UP_WI"                    ,	21,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"M2_UN_B0"                    ,	22,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"M2_UN_WI"                    ,	23,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"M3_UP_B0"                    ,	24,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"M3_UP_WI"                    ,	25,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"M3_UN_B0"                    ,	26,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"M3_UN_WI"                    ,	27,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAFI"                       ,	32,	2,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	48,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT2_ERR"                   ,	58,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT3_ERR"                   ,	59,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML_TO"                      ,	0,	1,	1040,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	1040,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	1040,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	1040,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	4,	1,	1040,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	5,	1,	1040,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	1040,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UP_WI"                    ,	9,	1,	1040,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_B0"                    ,	10,	1,	1040,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_WI"                    ,	11,	1,	1040,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_B0"                    ,	12,	1,	1040,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_WI"                    ,	13,	1,	1040,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_B0"                    ,	14,	1,	1040,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_WI"                    ,	15,	1,	1040,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT0"                    ,	16,	1,	1040,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT1"                    ,	17,	1,	1040,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC0_INT"                    ,	18,	1,	1040,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC1_INT"                    ,	19,	1,	1040,	"R/W",	0,	0,	0ull,	1ull},
+	{"M2_UP_B0"                    ,	20,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"M2_UP_WI"                    ,	21,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"M2_UN_B0"                    ,	22,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"M2_UN_WI"                    ,	23,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"M3_UP_B0"                    ,	24,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"M3_UP_WI"                    ,	25,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"M3_UN_B0"                    ,	26,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"M3_UN_WI"                    ,	27,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAFI"                       ,	32,	2,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	48,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT2_ERR"                   ,	58,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT3_ERR"                   ,	59,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML_TO"                      ,	0,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAR0_TO"                     ,	2,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB2BIG"                     ,	3,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT"                        ,	4,	1,	1041,	"RO",	0,	0,	0ull,	0ull},
+	{"PTIME"                       ,	5,	1,	1041,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UP_WI"                    ,	9,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UN_B0"                    ,	10,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UN_WI"                    ,	11,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UP_B0"                    ,	12,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UP_WI"                    ,	13,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UN_B0"                    ,	14,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UN_WI"                    ,	15,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO_INT0"                    ,	16,	1,	1041,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO_INT1"                    ,	17,	1,	1041,	"RO",	0,	0,	0ull,	0ull},
+	{"MAC0_INT"                    ,	18,	1,	1041,	"RO",	0,	0,	0ull,	0ull},
+	{"MAC1_INT"                    ,	19,	1,	1041,	"RO",	0,	0,	0ull,	0ull},
+	{"M2_UP_B0"                    ,	20,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M2_UP_WI"                    ,	21,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M2_UN_B0"                    ,	22,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M2_UN_WI"                    ,	23,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M3_UP_B0"                    ,	24,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M3_UP_WI"                    ,	25,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M3_UN_B0"                    ,	26,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M3_UN_WI"                    ,	27,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	1041,	"RAZ",	1,	1,	0,	0},
+	{"DMAFI"                       ,	32,	2,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	1041,	"RO",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	1041,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	1041,	"RAZ",	1,	1,	0,	0},
+	{"PIDBOF"                      ,	48,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT2_ERR"                   ,	58,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT3_ERR"                   ,	59,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	1041,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	1041,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	1042,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	1043,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	1044,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	1045,	"RO",	0,	1,	0ull,	0},
+	{"P0_PCNT"                     ,	0,	8,	1046,	"R/W",	0,	0,	128ull,	128ull},
+	{"P0_NCNT"                     ,	8,	8,	1046,	"R/W",	0,	0,	16ull,	16ull},
+	{"P0_CCNT"                     ,	16,	8,	1046,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_PCNT"                     ,	24,	8,	1046,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_NCNT"                     ,	32,	8,	1046,	"R/W",	0,	0,	16ull,	16ull},
+	{"P1_CCNT"                     ,	40,	8,	1046,	"R/W",	0,	0,	128ull,	128ull},
+	{"P0_P_D"                      ,	48,	1,	1046,	"R/W",	0,	0,	1ull,	1ull},
+	{"P0_N_D"                      ,	49,	1,	1046,	"R/W",	0,	0,	1ull,	1ull},
+	{"P0_C_D"                      ,	50,	1,	1046,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_P_D"                      ,	51,	1,	1046,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_N_D"                      ,	52,	1,	1046,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_C_D"                      ,	53,	1,	1046,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_54_63"              ,	54,	10,	1046,	"RAZ",	1,	1,	0,	0},
+	{"P2_PCNT"                     ,	0,	8,	1047,	"R/W",	0,	0,	128ull,	128ull},
+	{"P2_NCNT"                     ,	8,	8,	1047,	"R/W",	0,	0,	16ull,	16ull},
+	{"P2_CCNT"                     ,	16,	8,	1047,	"R/W",	0,	0,	128ull,	128ull},
+	{"P3_PCNT"                     ,	24,	8,	1047,	"R/W",	0,	0,	128ull,	128ull},
+	{"P3_NCNT"                     ,	32,	8,	1047,	"R/W",	0,	0,	16ull,	16ull},
+	{"P3_CCNT"                     ,	40,	8,	1047,	"R/W",	0,	0,	128ull,	128ull},
+	{"P2_P_D"                      ,	48,	1,	1047,	"R/W",	0,	0,	1ull,	1ull},
+	{"P2_N_D"                      ,	49,	1,	1047,	"R/W",	0,	0,	1ull,	1ull},
+	{"P2_C_D"                      ,	50,	1,	1047,	"R/W",	0,	0,	1ull,	1ull},
+	{"P3_P_D"                      ,	51,	1,	1047,	"R/W",	0,	0,	1ull,	1ull},
+	{"P3_N_D"                      ,	52,	1,	1047,	"R/W",	0,	0,	1ull,	1ull},
+	{"P3_C_D"                      ,	53,	1,	1047,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_54_63"              ,	54,	10,	1047,	"RAZ",	1,	1,	0,	0},
+	{"NUM"                         ,	0,	8,	1048,	"RO",	1,	1,	0,	0},
+	{"A_MODE"                      ,	8,	1,	1048,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_63"               ,	9,	55,	1048,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	10,	1049,	"R/W",	0,	0,	0ull,	50ull},
+	{"MAX_WORD"                    ,	10,	4,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	1049,	"RAZ",	1,	1,	0,	0},
+	{"BA"                          ,	0,	30,	1050,	"R/W",	0,	1,	0ull,	0},
+	{"RTYPE"                       ,	30,	2,	1050,	"R/W",	0,	1,	0ull,	0},
+	{"WTYPE"                       ,	32,	2,	1050,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	34,	2,	1050,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	36,	2,	1050,	"R/W",	0,	1,	0ull,	0},
+	{"NMERGE"                      ,	38,	1,	1050,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORT"                        ,	39,	3,	1050,	"R/W",	0,	1,	0ull,	0},
+	{"ZERO"                        ,	42,	1,	1050,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	1050,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	64,	1051,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	1052,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	1053,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	1054,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"INTR"                        ,	0,	64,	1055,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	1056,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	1057,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	1058,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	1059,	"R/W",	0,	1,	0ull,	0},
+	{"RD_INT"                      ,	8,	8,	1059,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	1059,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	64,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	1061,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	1062,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	1065,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	1066,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	1067,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	1068,	"R/W",	0,	1,	0ull,	0},
+	{"CIU_INT"                     ,	8,	8,	1068,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	1068,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	8,	1069,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	1069,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1070,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	8,	8,	1070,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	1070,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	1071,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	16,	8,	1071,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	1071,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	1072,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	24,	8,	1072,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1072,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1073,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	32,	22,	1073,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	1073,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1074,	"R/W",	0,	0,	0ull,	0ull},
+	{"WMARK"                       ,	32,	32,	1074,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	1075,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	61,	1075,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	1076,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	1076,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	1077,	"R/W",	0,	1,	0ull,	0},
+	{"FCNT"                        ,	32,	5,	1077,	"RO",	0,	1,	0ull,	0},
+	{"WRP"                         ,	37,	9,	1077,	"RO",	0,	1,	0ull,	0},
+	{"RRP"                         ,	46,	9,	1077,	"RO",	0,	1,	0ull,	0},
+	{"MAX"                         ,	55,	9,	1077,	"RO",	0,	1,	16ull,	0},
+	{"NTAG"                        ,	0,	1,	1078,	"R/W",	0,	1,	0ull,	0},
+	{"NTT"                         ,	1,	1,	1078,	"R/W",	0,	1,	0ull,	0},
+	{"NGRP"                        ,	2,	1,	1078,	"R/W",	0,	1,	0ull,	0},
+	{"NQOS"                        ,	3,	1,	1078,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	1078,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	1078,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_13"              ,	13,	1,	1078,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	1078,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_20"              ,	16,	5,	1078,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	1078,	"R/W",	0,	1,	0ull,	0},
+	{"RNTAG"                       ,	22,	1,	1078,	"R/W",	0,	1,	0ull,	0},
+	{"RNTT"                        ,	23,	1,	1078,	"R/W",	0,	1,	0ull,	0},
+	{"RNGRP"                       ,	24,	1,	1078,	"R/W",	0,	1,	0ull,	0},
+	{"RNQOS"                       ,	25,	1,	1078,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_27"              ,	26,	2,	1078,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	1078,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_35_35"              ,	35,	1,	1078,	"RAZ",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	1078,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_42"              ,	38,	5,	1078,	"RAZ",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	1078,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	1078,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	16,	1079,	"R/W",	0,	1,	0ull,	0},
+	{"ISIZE"                       ,	16,	7,	1079,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	1079,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1080,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	4,	60,	1080,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	1081,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	1081,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	1082,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1082,	"RO",	0,	1,	0ull,	0},
+	{"PORT"                        ,	0,	32,	1083,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1083,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	1084,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1084,	"RAZ",	1,	1,	0,	0},
+	{"PKT_BP"                      ,	0,	4,	1085,	"R/W",	0,	0,	15ull,	15ull},
+	{"RING_EN"                     ,	4,	1,	1085,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	1085,	"RAZ",	1,	1,	0,	0},
+	{"ES"                          ,	0,	64,	1086,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	1087,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1087,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	1088,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1088,	"RAZ",	1,	1,	0,	0},
+	{"DPTR"                        ,	0,	32,	1089,	"R/W",	0,	0,	0ull,	4294967295ull},
+	{"RESERVED_32_63"              ,	32,	32,	1089,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	32,	1090,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1090,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1091,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1091,	"RO",	0,	1,	0ull,	0},
+	{"RD_CNT"                      ,	0,	32,	1092,	"RO",	0,	1,	0ull,	0},
+	{"WR_CNT"                      ,	32,	32,	1092,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	0,	64,	1093,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	0,	1,	1094,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	1,	2,	1094,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	3,	1,	1094,	"R/W",	0,	1,	0ull,	0},
+	{"USE_CSR"                     ,	4,	1,	1094,	"R/W",	0,	0,	0ull,	1ull},
+	{"D_ROR"                       ,	5,	1,	1094,	"R/W",	0,	1,	0ull,	0},
+	{"D_ESR"                       ,	6,	2,	1094,	"R/W",	0,	1,	0ull,	0},
+	{"D_NSR"                       ,	8,	1,	1094,	"R/W",	0,	1,	0ull,	0},
+	{"PBP_DHI"                     ,	9,	13,	1094,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_RR"                      ,	22,	1,	1094,	"R/W",	0,	0,	0ull,	1ull},
+	{"PIN_RST"                     ,	23,	1,	1094,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_39"              ,	24,	16,	1094,	"RAZ",	1,	1,	0,	0},
+	{"PRC_IDLE"                    ,	40,	1,	1094,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_41_47"              ,	41,	7,	1094,	"RAZ",	1,	1,	0,	0},
+	{"GII_RDS"                     ,	48,	7,	1094,	"RO",	0,	1,	0ull,	0},
+	{"GII_ERST"                    ,	55,	1,	1094,	"RO",	0,	1,	0ull,	0},
+	{"PRD_RDS"                     ,	56,	7,	1094,	"RO",	0,	1,	0ull,	0},
+	{"PRD_ERST"                    ,	63,	1,	1094,	"RO",	0,	1,	0ull,	0},
+	{"ENB"                         ,	0,	32,	1095,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1095,	"RAZ",	1,	1,	0,	0},
+	{"RDSIZE"                      ,	0,	64,	1096,	"R/W",	0,	1,	0ull,	0},
+	{"IS_64B"                      ,	0,	32,	1097,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1097,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	1098,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	22,	1098,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_54_63"              ,	54,	10,	1098,	"RAZ",	1,	1,	0,	0},
+	{"IPTR"                        ,	0,	32,	1099,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1099,	"RAZ",	1,	1,	0,	0},
+	{"BMODE"                       ,	0,	32,	1100,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1100,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	32,	1101,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1101,	"RAZ",	1,	1,	0,	0},
+	{"WMARK"                       ,	0,	32,	1102,	"R/W",	0,	0,	0ull,	14ull},
+	{"RESERVED_32_63"              ,	32,	32,	1102,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	0,	64,	1103,	"R/W",	0,	1,	0ull,	0},
+	{"OUT_RST"                     ,	0,	32,	1104,	"RO",	0,	1,	0ull,	0},
+	{"IN_RST"                      ,	32,	32,	1104,	"RO",	0,	1,	0ull,	0},
+	{"ES"                          ,	0,	64,	1105,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	1106,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1106,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	1107,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1107,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	1108,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1108,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	1109,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1109,	"RAZ",	1,	1,	0,	0},
+	{"MRRS"                        ,	0,	3,	1110,	"R/W",	0,	0,	2ull,	2ull},
+	{"BAR0_D"                      ,	3,	1,	1110,	"R/W",	1,	1,	0,	0},
+	{"WIND_D"                      ,	4,	1,	1110,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_5_63"               ,	5,	59,	1110,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	1111,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	1112,	"R/W",	0,	1,	0ull,	0},
+	{"CSR"                         ,	0,	39,	1113,	"RO",	0,	1,	1ull,	0},
+	{"ARB"                         ,	39,	1,	1113,	"RO",	0,	1,	0ull,	0},
+	{"CPL0"                        ,	40,	12,	1113,	"RO",	0,	1,	1ull,	0},
+	{"CPL1"                        ,	52,	12,	1113,	"RO",	0,	1,	1ull,	0},
+	{"NND"                         ,	0,	8,	1114,	"RO",	0,	1,	1ull,	0},
+	{"NNP0"                        ,	8,	8,	1114,	"RO",	0,	1,	1ull,	0},
+	{"CSM0"                        ,	16,	15,	1114,	"RO",	0,	1,	1ull,	0},
+	{"CSM1"                        ,	31,	15,	1114,	"RO",	0,	1,	1ull,	0},
+	{"RAC"                         ,	46,	1,	1114,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	1114,	"RAZ",	1,	1,	0,	0},
+	{"NNP1"                        ,	48,	8,	1114,	"RAZ",	0,	1,	0ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	1114,	"RAZ",	1,	1,	0,	0},
+	{"NSM0"                        ,	0,	13,	1115,	"RO",	0,	1,	1ull,	0},
+	{"NSM1"                        ,	13,	13,	1115,	"RO",	0,	1,	1ull,	0},
+	{"PSM0"                        ,	26,	15,	1115,	"RO",	0,	1,	1ull,	0},
+	{"PSM1"                        ,	41,	15,	1115,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	1115,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	0,	48,	1116,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	1116,	"R/W",	0,	0,	0ull,	0ull},
+	{"LD_CMD"                      ,	49,	2,	1116,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_51_63"              ,	51,	13,	1116,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	1117,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	1118,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	3,	45,	1118,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	1118,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	1118,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	1119,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	1120,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1120,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	1121,	"R/W",	0,	0,	0ull,	2097152ull},
+	{"RESERVED_32_63"              ,	32,	32,	1121,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	1122,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	1122,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	1122,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	1122,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	1122,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	24,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1122,	"RAZ",	1,	1,	0,	0},
+	{"REG_ADR"                     ,	0,	5,	1123,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1123,	"RAZ",	1,	1,	0,	0},
+	{"PHY_ADR"                     ,	8,	5,	1123,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	1123,	"RAZ",	1,	1,	0,	0},
+	{"PHY_OP"                      ,	16,	2,	1123,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	1123,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	1124,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	1124,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	1125,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	1125,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	1125,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	1125,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	1126,	"R/W",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	1126,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	1126,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	1126,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	1127,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_6_7"                ,	6,	2,	1127,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	8,	6,	1127,	"R/W",	0,	0,	19ull,	19ull},
+	{"RESERVED_14_63"              ,	14,	50,	1127,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	22,	1128,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1128,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	24,	22,	1128,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	1128,	"RAZ",	1,	1,	0,	0},
+	{"ENA"                         ,	47,	1,	1128,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1128,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	20,	1129,	"RO",	1,	0,	0,	0ull},
+	{"BASE"                        ,	20,	31,	1129,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	51,	13,	1129,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	0,	7,	1130,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	1130,	"RO",	1,	0,	0,	0ull},
+	{"CSIZE"                       ,	8,	13,	1130,	"RO",	1,	0,	0,	0ull},
+	{"CPOOL"                       ,	21,	3,	1130,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	1130,	"RAZ",	1,	1,	0,	0},
+	{"RING"                        ,	0,	4,	1131,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_BUCKETS"                 ,	4,	20,	1131,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIRST_BUCKET"                ,	24,	31,	1131,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	1131,	"RAZ",	1,	1,	0,	0},
+	{"RING"                        ,	0,	4,	1132,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	4,	22,	1132,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORDS_PER_CHUNK"             ,	26,	13,	1132,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	39,	3,	1132,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	42,	1,	1132,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	1132,	"RAZ",	1,	1,	0,	0},
+	{"CTL"                         ,	0,	1,	1133,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	1,	1,	1133,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	2,	2,	1133,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1133,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	1134,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1134,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE_TIMERS"               ,	0,	1,	1135,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	1135,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	2,	1,	1135,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	1135,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	1136,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1136,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1137,	"RAZ",	1,	1,	0,	0},
+	{"TDF"                         ,	0,	1,	1138,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1138,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRAP"                        ,	1,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRIG_CTL"                    ,	2,	2,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIME_GRN"                    ,	4,	3,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"FULL_THR"                    ,	7,	2,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	9,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	10,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	11,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	12,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_ENA"                    ,	13,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNORE_O"                    ,	14,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKALWAYS"                   ,	15,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDAT_MD"                     ,	16,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	1139,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	8,	1140,	"RO",	0,	0,	0ull,	0ull},
+	{"RPTR"                        ,	8,	8,	1140,	"RO",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	16,	48,	1140,	"RO",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	10,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	1141,	"RAZ",	1,	1,	0,	0},
+	{"RPTR"                        ,	12,	10,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1141,	"RAZ",	1,	1,	0,	0},
+	{"CYCLES"                      ,	24,	40,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1142,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1142,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1143,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1143,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1144,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1145,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1145,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1145,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1145,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1145,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1145,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1145,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1145,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1145,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1145,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1145,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1145,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1145,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1145,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1145,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1145,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1145,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1145,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1145,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1145,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	4,	1146,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	1146,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1146,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1146,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1146,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1146,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1146,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	0,	1,	1147,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	1,	1,	1147,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	2,	1,	1147,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	3,	1,	1147,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1147,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	1148,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	5,	1149,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	1149,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1150,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1150,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1151,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1153,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1153,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1153,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1153,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1153,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1153,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1153,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1153,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1153,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1153,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1153,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1153,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1153,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1153,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1153,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1153,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1153,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1153,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1153,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1153,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	4,	1154,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	1154,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1154,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1154,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1154,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1154,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1154,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1155,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1155,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1156,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1156,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1157,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1157,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1157,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1157,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1157,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1157,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1158,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1158,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1158,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1158,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1158,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	4,	1159,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	1159,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1159,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1159,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1159,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1159,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1159,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	1160,	"R/W",	0,	1,	0ull,	0},
+	{"LPL"                         ,	5,	27,	1160,	"R/W",	0,	1,	0ull,	0},
+	{"CF"                          ,	0,	1,	1161,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_31"               ,	1,	31,	1161,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTRLDSSEG"                   ,	0,	32,	1162,	"R/W",	0,	1,	0ull,	0},
+	{"FI"                          ,	0,	14,	1163,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_31"              ,	14,	18,	1163,	"RO",	0,	0,	0ull,	0ull},
+	{"CAPLENGTH"                   ,	0,	8,	1164,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_8_15"               ,	8,	8,	1164,	"RO",	0,	0,	0ull,	0ull},
+	{"HCIVERSION"                  ,	16,	16,	1164,	"RO",	0,	0,	256ull,	256ull},
+	{"AC64"                        ,	0,	1,	1165,	"RO",	0,	0,	1ull,	1ull},
+	{"PFLF"                        ,	1,	1,	1165,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPC"                        ,	2,	1,	1165,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1165,	"RO",	0,	0,	0ull,	0ull},
+	{"IST"                         ,	4,	4,	1165,	"RO",	0,	0,	2ull,	2ull},
+	{"EECP"                        ,	8,	8,	1165,	"RO",	0,	0,	160ull,	160ull},
+	{"RESERVED_16_31"              ,	16,	16,	1165,	"RO",	0,	0,	0ull,	0ull},
+	{"N_PORTS"                     ,	0,	4,	1166,	"RO",	0,	0,	2ull,	2ull},
+	{"PPC"                         ,	4,	1,	1166,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	1166,	"RO",	0,	0,	0ull,	0ull},
+	{"PRR"                         ,	7,	1,	1166,	"RO",	0,	0,	0ull,	0ull},
+	{"N_PCC"                       ,	8,	4,	1166,	"RO",	0,	0,	2ull,	2ull},
+	{"N_CC"                        ,	12,	4,	1166,	"RO",	0,	0,	1ull,	1ull},
+	{"P_INDICATOR"                 ,	16,	1,	1166,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	1166,	"RO",	0,	0,	0ull,	0ull},
+	{"DPN"                         ,	20,	4,	1166,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1166,	"RO",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	0,	1,	1167,	"R/W",	0,	0,	0ull,	0ull},
+	{"MFMC"                        ,	1,	13,	1167,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	1167,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_0"                ,	0,	1,	1168,	"R/W",	0,	0,	0ull,	0ull},
+	{"TA_OFF"                      ,	1,	8,	1168,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	1168,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXTX_TADAO"                  ,	10,	3,	1168,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	1168,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCP_RW"                      ,	0,	1,	1169,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCP_FW"                      ,	1,	1,	1169,	"R/W",	0,	0,	0ull,	0ull},
+	{"PESD"                        ,	2,	1,	1169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1169,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NAKRF_DIS"                   ,	4,	1,	1169,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTO_DIS"                    ,	5,	1,	1169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	1169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_30"               ,	0,	31,	1170,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	31,	1,	1170,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_ADDR"                    ,	0,	32,	1171,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_11"               ,	0,	12,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"BADDR"                       ,	12,	20,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"CCS"                         ,	0,	1,	1173,	"RO",	0,	0,	0ull,	0ull},
+	{"CSC"                         ,	1,	1,	1173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PED"                         ,	2,	1,	1173,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEDC"                        ,	3,	1,	1173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OCA"                         ,	4,	1,	1173,	"RO",	0,	0,	0ull,	0ull},
+	{"OCC"                         ,	5,	1,	1173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPR"                         ,	6,	1,	1173,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPD"                         ,	7,	1,	1173,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRST"                        ,	8,	1,	1173,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	1173,	"RO",	0,	0,	0ull,	0ull},
+	{"LSTS"                        ,	10,	2,	1173,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	12,	1,	1173,	"RO",	0,	0,	1ull,	1ull},
+	{"PO"                          ,	13,	1,	1173,	"R/W",	0,	0,	1ull,	0ull},
+	{"PIC"                         ,	14,	2,	1173,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTC"                         ,	16,	4,	1173,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKCNNT_E"                    ,	20,	1,	1173,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKDSCNNT_E"                  ,	21,	1,	1173,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKOC_E"                      ,	22,	1,	1173,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	1173,	"RO",	0,	0,	0ull,	0ull},
+	{"RS"                          ,	0,	1,	1174,	"R/W",	0,	0,	0ull,	1ull},
+	{"HCRESET"                     ,	1,	1,	1174,	"R/W",	0,	0,	0ull,	0ull},
+	{"FLS"                         ,	2,	2,	1174,	"RO",	0,	0,	0ull,	0ull},
+	{"PS_EN"                       ,	4,	1,	1174,	"R/W",	0,	0,	0ull,	0ull},
+	{"AS_EN"                       ,	5,	1,	1174,	"R/W",	0,	0,	0ull,	0ull},
+	{"IAA_DB"                      ,	6,	1,	1174,	"R/W",	0,	0,	0ull,	0ull},
+	{"LHCR"                        ,	7,	1,	1174,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASPMC"                       ,	8,	2,	1174,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	1174,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPM_EN"                     ,	11,	1,	1174,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	1174,	"RO",	0,	0,	0ull,	0ull},
+	{"ITC"                         ,	16,	8,	1174,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_24_31"              ,	24,	8,	1174,	"RO",	0,	0,	0ull,	0ull},
+	{"USBINT_EN"                   ,	0,	1,	1175,	"R/W",	0,	1,	0ull,	0},
+	{"USBERRINT_EN"                ,	1,	1,	1175,	"R/W",	0,	1,	0ull,	0},
+	{"PCI_EN"                      ,	2,	1,	1175,	"R/W",	0,	1,	0ull,	0},
+	{"FLRO_EN"                     ,	3,	1,	1175,	"R/W",	0,	1,	0ull,	0},
+	{"HSERR_EN"                    ,	4,	1,	1175,	"R/W",	0,	1,	0ull,	0},
+	{"IOAA_EN"                     ,	5,	1,	1175,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_31"               ,	6,	26,	1175,	"RO",	0,	0,	0ull,	0ull},
+	{"USBINT"                      ,	0,	1,	1176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBERRINT"                   ,	1,	1,	1176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCD"                         ,	2,	1,	1176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FLRO"                        ,	3,	1,	1176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HSYSERR"                     ,	4,	1,	1176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOAA"                        ,	5,	1,	1176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	1176,	"RO",	0,	0,	0ull,	0ull},
+	{"HCHTD"                       ,	12,	1,	1176,	"RO",	0,	0,	1ull,	0ull},
+	{"RECLM"                       ,	13,	1,	1176,	"RO",	0,	0,	0ull,	0ull},
+	{"PSS"                         ,	14,	1,	1176,	"RO",	0,	0,	0ull,	0ull},
+	{"ASS"                         ,	15,	1,	1176,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1176,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1177,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCED"                        ,	4,	28,	1177,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1178,	"R/W",	0,	0,	0ull,	0ull},
+	{"BHED"                        ,	4,	28,	1178,	"R/W",	0,	1,	0ull,	0},
+	{"HCR"                         ,	0,	1,	1179,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLF"                         ,	1,	1,	1179,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLF"                         ,	2,	1,	1179,	"R/W",	0,	0,	0ull,	0ull},
+	{"OCR"                         ,	3,	1,	1179,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	1179,	"RO",	0,	0,	0ull,	0ull},
+	{"SOC"                         ,	16,	2,	1179,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	1179,	"RO",	0,	0,	0ull,	0ull},
+	{"CBSR"                        ,	0,	2,	1180,	"R/W",	0,	1,	0ull,	0},
+	{"PLE"                         ,	2,	1,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"IE"                          ,	3,	1,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLE"                         ,	4,	1,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLE"                         ,	5,	1,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCFS"                        ,	6,	2,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"IR"                          ,	8,	1,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWC"                         ,	9,	1,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWE"                         ,	10,	1,	1180,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	1180,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1181,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCED"                        ,	4,	28,	1181,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1182,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHED"                        ,	4,	28,	1182,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1183,	"RO",	0,	0,	0ull,	0ull},
+	{"DH"                          ,	4,	28,	1183,	"RO",	0,	1,	0ull,	0},
+	{"FI"                          ,	0,	14,	1184,	"R/W",	0,	1,	11999ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	1184,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSMPS"                       ,	16,	15,	1184,	"R/W",	0,	1,	0ull,	0},
+	{"FIT"                         ,	31,	1,	1184,	"R/W",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	0,	16,	1185,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	1185,	"RO",	0,	0,	0ull,	0ull},
+	{"FR"                          ,	0,	14,	1186,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_30"              ,	14,	17,	1186,	"RO",	0,	0,	0ull,	0ull},
+	{"FRT"                         ,	31,	1,	1186,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	1187,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCCA"                        ,	8,	24,	1187,	"R/W",	0,	1,	0ull,	0},
+	{"SO"                          ,	0,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1188,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIE"                         ,	31,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
+	{"SO"                          ,	0,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1189,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIE"                         ,	31,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"SO"                          ,	0,	1,	1190,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1190,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1190,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1190,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1190,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1190,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1190,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1190,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1190,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1190,	"RO",	0,	0,	0ull,	0ull},
+	{"LST"                         ,	0,	12,	1191,	"R/W",	0,	1,	1576ull,	0},
+	{"RESERVED_12_31"              ,	12,	20,	1191,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1192,	"RO",	0,	0,	0ull,	0ull},
+	{"PCED"                        ,	4,	28,	1192,	"RO",	0,	1,	0ull,	0},
+	{"PS"                          ,	0,	14,	1193,	"R/W",	0,	0,	0ull,	15975ull},
+	{"RESERVED_14_31"              ,	14,	18,	1193,	"R/W",	0,	0,	0ull,	0ull},
+	{"REV"                         ,	0,	8,	1194,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_8_31"               ,	8,	24,	1194,	"RO",	0,	0,	0ull,	0ull},
+	{"NDP"                         ,	0,	8,	1195,	"RO",	0,	0,	2ull,	2ull},
+	{"NPS"                         ,	8,	1,	1195,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSM"                         ,	9,	1,	1195,	"R/W",	0,	0,	1ull,	1ull},
+	{"DT"                          ,	10,	1,	1195,	"RO",	0,	0,	0ull,	0ull},
+	{"OCPM"                        ,	11,	1,	1195,	"R/W",	1,	1,	0,	0},
+	{"NOCP"                        ,	12,	1,	1195,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_23"              ,	13,	11,	1195,	"RO",	0,	0,	0ull,	0ull},
+	{"POTPGT"                      ,	24,	8,	1195,	"R/W",	0,	0,	1ull,	1ull},
+	{"DR"                          ,	0,	16,	1196,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPCM"                        ,	16,	16,	1196,	"R/W",	0,	1,	0ull,	0},
+	{"CCS"                         ,	0,	1,	1197,	"R/W",	0,	1,	0ull,	0},
+	{"PES"                         ,	1,	1,	1197,	"R/W",	0,	1,	0ull,	0},
+	{"PSS"                         ,	2,	1,	1197,	"R/W",	0,	1,	0ull,	0},
+	{"POCI"                        ,	3,	1,	1197,	"R/W",	0,	1,	0ull,	0},
+	{"PRS"                         ,	4,	1,	1197,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1197,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS"                         ,	8,	1,	1197,	"R/W",	0,	1,	0ull,	0},
+	{"LSDA"                        ,	9,	1,	1197,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_10_15"              ,	10,	6,	1197,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSC"                         ,	16,	1,	1197,	"R/W",	0,	1,	0ull,	0},
+	{"PESC"                        ,	17,	1,	1197,	"R/W",	0,	1,	0ull,	0},
+	{"PSSC"                        ,	18,	1,	1197,	"R/W",	0,	1,	0ull,	0},
+	{"OCIC"                        ,	19,	1,	1197,	"R/W",	0,	1,	0ull,	0},
+	{"PRSC"                        ,	20,	1,	1197,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_31"              ,	21,	11,	1197,	"R/W",	0,	0,	0ull,	0ull},
+	{"LPS"                         ,	0,	1,	1198,	"R/W",	0,	0,	0ull,	0ull},
+	{"OCI"                         ,	1,	1,	1198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_14"               ,	2,	13,	1198,	"RO",	0,	0,	0ull,	0ull},
+	{"DRWE"                        ,	15,	1,	1198,	"R/W",	0,	1,	0ull,	0},
+	{"LPSC"                        ,	16,	1,	1198,	"R/W",	0,	1,	0ull,	0},
+	{"CCIC"                        ,	17,	1,	1198,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_18_30"              ,	18,	13,	1198,	"RO",	0,	0,	0ull,	0ull},
+	{"CRWE"                        ,	31,	1,	1198,	"WO",	1,	1,	0,	0},
+	{"RESERVED_0_30"               ,	0,	31,	1199,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	31,	1,	1199,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_ADDR"                    ,	0,	32,	1200,	"RO",	0,	0,	0ull,	0ull},
+	{"PPAF_BIS"                    ,	0,	1,	1201,	"RO",	0,	0,	0ull,	0ull},
+	{"WRBM_BIS"                    ,	1,	1,	1201,	"RO",	0,	0,	0ull,	0ull},
+	{"ORBM_BIS"                    ,	2,	1,	1201,	"RO",	0,	0,	0ull,	0ull},
+	{"ERBM_BIS"                    ,	3,	1,	1201,	"RO",	0,	0,	0ull,	0ull},
+	{"DESC_BIS"                    ,	4,	1,	1201,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_BIS"                    ,	5,	1,	1201,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1201,	"RO",	1,	1,	0,	0},
+	{"HRST"                        ,	0,	1,	1202,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_PRST"                      ,	1,	1,	1202,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_POR"                       ,	2,	1,	1202,	"R/W",	0,	0,	1ull,	0ull},
+	{"P_COM_ON"                    ,	3,	1,	1202,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	1202,	"R/W",	0,	1,	0ull,	0},
+	{"P_REFCLK_DIV"                ,	5,	2,	1202,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_REFCLK_SEL"                ,	7,	2,	1202,	"R/W",	0,	0,	0ull,	0ull},
+	{"H_DIV"                       ,	9,	4,	1202,	"R/W",	0,	0,	6ull,	6ull},
+	{"O_CLKDIV_EN"                 ,	13,	1,	1202,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_EN"                 ,	14,	1,	1202,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_RST"                ,	15,	1,	1202,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_BYP"                ,	16,	1,	1202,	"R/W",	0,	0,	0ull,	0ull},
+	{"O_CLKDIV_RST"                ,	17,	1,	1202,	"R/W",	0,	0,	0ull,	1ull},
+	{"APP_START_CLK"               ,	18,	1,	1202,	"R/W",	0,	0,	0ull,	0ull},
+	{"OHCI_SUSP_LGCY"              ,	19,	1,	1202,	"R/W",	0,	0,	1ull,	1ull},
+	{"OHCI_SM"                     ,	20,	1,	1202,	"R/W",	0,	0,	0ull,	0ull},
+	{"OHCI_CLKCKTRST"              ,	21,	1,	1202,	"R/W",	0,	0,	1ull,	1ull},
+	{"EHCI_SM"                     ,	22,	1,	1202,	"R/W",	0,	0,	0ull,	0ull},
+	{"START_BIST"                  ,	23,	1,	1202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLEAR_BIST"                  ,	24,	1,	1202,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1202,	"RAZ",	1,	1,	0,	0},
+	{"L2C_ADDR_MSB"                ,	0,	8,	1203,	"R/W",	0,	1,	0ull,	0},
+	{"EHCI_64B_ADDR_EN"            ,	8,	1,	1203,	"R/W",	0,	0,	1ull,	1ull},
+	{"INV_REG_A2"                  ,	9,	1,	1203,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DESC_EMOD"               ,	10,	2,	1203,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BUFF_EMOD"               ,	12,	2,	1203,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2C_STT"                     ,	14,	1,	1203,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_0PAG"                    ,	15,	1,	1203,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BC"                      ,	16,	1,	1203,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DC"                      ,	17,	1,	1203,	"R/W",	0,	0,	1ull,	1ull},
+	{"REG_NB"                      ,	18,	1,	1203,	"R/W",	0,	0,	0ull,	0ull},
+	{"DESC_RBM"                    ,	19,	1,	1203,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1203,	"RAZ",	1,	1,	0,	0},
+	{"FLA"                         ,	0,	6,	1204,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	1204,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	1205,	"RAZ",	1,	1,	0,	0},
+	{"TO_VAL"                      ,	5,	27,	1205,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1205,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	1206,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	1206,	"RAZ",	1,	1,	0,	0},
+	{"PP_PSH_F"                    ,	0,	1,	1207,	"R/W",	0,	0,	0ull,	0ull},
+	{"ER_PSH_F"                    ,	1,	1,	1207,	"R/W",	0,	0,	0ull,	0ull},
+	{"OR_PSH_F"                    ,	2,	1,	1207,	"R/W",	0,	0,	0ull,	0ull},
+	{"CF_PSH_F"                    ,	3,	1,	1207,	"R/W",	0,	0,	0ull,	0ull},
+	{"WB_PSH_F"                    ,	4,	1,	1207,	"R/W",	0,	0,	0ull,	0ull},
+	{"WB_POP_E"                    ,	5,	1,	1207,	"R/W",	0,	0,	0ull,	0ull},
+	{"OC_OVF_E"                    ,	6,	1,	1207,	"R/W",	0,	0,	0ull,	0ull},
+	{"EC_OVF_E"                    ,	7,	1,	1207,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1207,	"RAZ",	1,	1,	0,	0},
+	{"PP_PSH_F"                    ,	0,	1,	1208,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ER_PSH_F"                    ,	1,	1,	1208,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OR_PSH_F"                    ,	2,	1,	1208,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CF_PSH_F"                    ,	3,	1,	1208,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WB_PSH_F"                    ,	4,	1,	1208,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WB_POP_E"                    ,	5,	1,	1208,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OC_OVF_E"                    ,	6,	1,	1208,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EC_OVF_E"                    ,	7,	1,	1208,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1208,	"RAZ",	1,	1,	0,	0},
+	{"L2C_ADDR_MSB"                ,	0,	8,	1209,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_8"                ,	8,	1,	1209,	"RAZ",	1,	1,	0,	0},
+	{"INV_REG_A2"                  ,	9,	1,	1209,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DESC_EMOD"               ,	10,	2,	1209,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BUFF_EMOD"               ,	12,	2,	1209,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2C_STT"                     ,	14,	1,	1209,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_0PAG"                    ,	15,	1,	1209,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BC"                      ,	16,	1,	1209,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DC"                      ,	17,	1,	1209,	"R/W",	0,	0,	1ull,	1ull},
+	{"REG_NB"                      ,	18,	1,	1209,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	1209,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1210,	"RAZ",	1,	1,	0,	0},
+	{"TO_VAL"                      ,	8,	24,	1210,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1210,	"RAZ",	1,	1,	0,	0},
+	{"WM"                          ,	0,	5,	1211,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_5_63"               ,	5,	59,	1211,	"RAZ",	1,	1,	0,	0},
+	{"ATE_RESET"                   ,	0,	1,	1212,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_EN"                     ,	1,	1,	1212,	"R/W",	0,	0,	0ull,	0ull},
+	{"UPHY_BIST"                   ,	2,	1,	1212,	"R/W",	0,	0,	0ull,	0ull},
+	{"VTEST_EN"                    ,	3,	1,	1212,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIDDQ"                       ,	4,	1,	1212,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBIST"                      ,	5,	1,	1212,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSBIST"                      ,	6,	1,	1212,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSBIST"                      ,	7,	1,	1212,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_ERR"                    ,	8,	1,	1212,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST_DONE"                   ,	9,	1,	1212,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1212,	"RAZ",	1,	1,	0,	0},
+	{"TDATA_IN"                    ,	0,	8,	1213,	"R/W",	0,	0,	0ull,	0ull},
+	{"TADDR_IN"                    ,	8,	4,	1213,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_SEL"                   ,	12,	1,	1213,	"R/W",	0,	0,	1ull,	0ull},
+	{"TCLK"                        ,	13,	1,	1213,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOP_EN"                     ,	14,	1,	1213,	"R/W",	0,	0,	0ull,	0ull},
+	{"COMPDISTUNE"                 ,	15,	3,	1213,	"R/W",	0,	0,	4ull,	4ull},
+	{"SQRXTUNE"                    ,	18,	3,	1213,	"R/W",	0,	0,	4ull,	4ull},
+	{"TXFSLSTUNE"                  ,	21,	4,	1213,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPREEMPHASISTUNE"           ,	25,	1,	1213,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXRISETUNE"                  ,	26,	1,	1213,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXVREFTUNE"                  ,	27,	4,	1213,	"R/W",	0,	0,	5ull,	15ull},
+	{"TXHSVXTUNE"                  ,	31,	2,	1213,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORTRESET"                   ,	33,	1,	1213,	"R/W",	0,	0,	0ull,	0ull},
+	{"VBUSVLDEXT"                  ,	34,	1,	1213,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPPULLDOWN"                  ,	35,	1,	1213,	"R/W",	0,	0,	1ull,	1ull},
+	{"DMPULLDOWN"                  ,	36,	1,	1213,	"R/W",	0,	0,	1ull,	1ull},
+	{"TXBISTSTUFFEN"               ,	37,	1,	1213,	"R/W",	0,	0,	1ull,	1ull},
+	{"TXBISTSTUFFENH"              ,	38,	1,	1213,	"R/W",	0,	0,	1ull,	1ull},
+	{"TDATA_OUT"                   ,	39,	4,	1213,	"RO",	1,	1,	0,	0},
+	{"RESERVED_43_63"              ,	43,	21,	1213,	"RAZ",	1,	1,	0,	0},
 	{NULL,0,0,0,0,0,0,0,0}
 };
 
@@ -105457,8 +234462,13 @@ const CVMX_CSR_DB_TYPE *cvmx_csr_db[] = {
 	cvmx_csr_db_cn50xx,
 	cvmx_csr_db_cn52xxp1,
 	cvmx_csr_db_cn52xx,
+	cvmx_csr_db_cn61xx,
 	cvmx_csr_db_cn63xxp1,
 	cvmx_csr_db_cn63xx,
+	cvmx_csr_db_cn66xx,
+	cvmx_csr_db_cn68xxp1,
+	cvmx_csr_db_cn68xx,
+	cvmx_csr_db_cnf71xx,
 	NULL
 };
 const CVMX_CSR_DB_ADDRESS_TYPE *cvmx_csr_db_addresses[] = {
@@ -105473,8 +234483,13 @@ const CVMX_CSR_DB_ADDRESS_TYPE *cvmx_csr_db_addresses[] = {
 	cvmx_csr_db_addresses_cn50xx,
 	cvmx_csr_db_addresses_cn52xxp1,
 	cvmx_csr_db_addresses_cn52xx,
+	cvmx_csr_db_addresses_cn61xx,
 	cvmx_csr_db_addresses_cn63xxp1,
 	cvmx_csr_db_addresses_cn63xx,
+	cvmx_csr_db_addresses_cn66xx,
+	cvmx_csr_db_addresses_cn68xxp1,
+	cvmx_csr_db_addresses_cn68xx,
+	cvmx_csr_db_addresses_cnf71xx,
 	NULL
 };
 const CVMX_CSR_DB_FIELD_TYPE *cvmx_csr_db_fields[] = {
@@ -105489,7 +234504,12 @@ const CVMX_CSR_DB_FIELD_TYPE *cvmx_csr_db_fields[] = {
 	cvmx_csr_db_fields_cn50xx,
 	cvmx_csr_db_fields_cn52xxp1,
 	cvmx_csr_db_fields_cn52xx,
+	cvmx_csr_db_fields_cn61xx,
 	cvmx_csr_db_fields_cn63xxp1,
 	cvmx_csr_db_fields_cn63xx,
+	cvmx_csr_db_fields_cn66xx,
+	cvmx_csr_db_fields_cn68xxp1,
+	cvmx_csr_db_fields_cn68xx,
+	cvmx_csr_db_fields_cnf71xx,
 	NULL
 };
diff --git a/sys/contrib/octeon-sdk/cvmx-csr-db.h b/sys/contrib/octeon-sdk/cvmx-csr-db.h
index b5e12df..bc042f3 100644
--- a/sys/contrib/octeon-sdk/cvmx-csr-db.h
+++ b/sys/contrib/octeon-sdk/cvmx-csr-db.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -50,7 +50,7 @@
  * Interface for the Octeon CSR database.
  *
  *
- * <hr>$Revision: 49507 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 #if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
diff --git a/sys/contrib/octeon-sdk/cvmx-csr-enums.h b/sys/contrib/octeon-sdk/cvmx-csr-enums.h
index 4813625..df69608 100644
--- a/sys/contrib/octeon-sdk/cvmx-csr-enums.h
+++ b/sys/contrib/octeon-sdk/cvmx-csr-enums.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -47,7 +47,7 @@
  * @file
  * Definitions for enumerations used with Octeon CSRs.
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 #ifndef __CVMX_CSR_ENUMS_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-csr-typedefs.h b/sys/contrib/octeon-sdk/cvmx-csr-typedefs.h
index 4354209..fd17bcc 100644
--- a/sys/contrib/octeon-sdk/cvmx-csr-typedefs.h
+++ b/sys/contrib/octeon-sdk/cvmx-csr-typedefs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -46,7 +46,7 @@
  *
  * This file is auto generated. Do not edit.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 69515 $<hr>
  *
  */
 #ifndef __CVMX_CSR_TYPEDEFS_H__
@@ -54,14 +54,19 @@
 #include "cvmx-agl-defs.h"
 #include "cvmx-asxx-defs.h"
 #include "cvmx-asx0-defs.h"
+#include "cvmx-ciu2-defs.h"
 #include "cvmx-ciu-defs.h"
 #include "cvmx-dbg-defs.h"
 #include "cvmx-dfa-defs.h"
 #include "cvmx-dfm-defs.h"
 #include "cvmx-dpi-defs.h"
+#include "cvmx-endor-defs.h"
+#include "cvmx-eoi-defs.h"
 #include "cvmx-fpa-defs.h"
 #include "cvmx-gmxx-defs.h"
 #include "cvmx-gpio-defs.h"
+#include "cvmx-ilk-defs.h"
+#include "cvmx-iob1-defs.h"
 #include "cvmx-iob-defs.h"
 #include "cvmx-ipd-defs.h"
 #include "cvmx-key-defs.h"
@@ -98,9 +103,10 @@
 #include "cvmx-sriox-defs.h"
 #include "cvmx-sriomaintx-defs.h"
 #include "cvmx-srxx-defs.h"
+#include "cvmx-sso-defs.h"
 #include "cvmx-stxx-defs.h"
 #include "cvmx-tim-defs.h"
-#include "cvmx-tra-defs.h"
+#include "cvmx-trax-defs.h"
 #include "cvmx-uahcx-defs.h"
 #include "cvmx-uctlx-defs.h"
 #include "cvmx-usbcx-defs.h"
diff --git a/sys/contrib/octeon-sdk/cvmx-csr.h b/sys/contrib/octeon-sdk/cvmx-csr.h
index 412662e..44400b3 100644
--- a/sys/contrib/octeon-sdk/cvmx-csr.h
+++ b/sys/contrib/octeon-sdk/cvmx-csr.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * Configuration and status register (CSR) address and type definitions for
  * Octoen.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 #ifndef __CVMX_CSR_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-dbg-defs.h b/sys/contrib/octeon-sdk/cvmx-dbg-defs.h
index e435deb..022c714 100644
--- a/sys/contrib/octeon-sdk/cvmx-dbg-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-dbg-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_DBG_TYPEDEFS_H__
-#define __CVMX_DBG_TYPEDEFS_H__
+#ifndef __CVMX_DBG_DEFS_H__
+#define __CVMX_DBG_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_DBG_DATA CVMX_DBG_DATA_FUNC()
@@ -71,12 +71,10 @@ static inline uint64_t CVMX_DBG_DATA_FUNC(void)
  *
  * Value returned on the debug-data lines from the RSLs
  */
-union cvmx_dbg_data
-{
+union cvmx_dbg_data {
 	uint64_t u64;
-	struct cvmx_dbg_data_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dbg_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_23_63               : 41;
 	uint64_t c_mul                        : 5;  /**< C_MUL pins sampled at DCOK assertion */
 	uint64_t dsel_ext                     : 1;  /**< Allows changes in the external pins to set the
@@ -89,9 +87,8 @@ union cvmx_dbg_data
 	uint64_t reserved_23_63               : 41;
 #endif
 	} s;
-	struct cvmx_dbg_data_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dbg_data_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t pll_mul                      : 3;  /**< pll_mul pins sampled at DCOK assertion */
 	uint64_t reserved_23_27               : 5;
@@ -109,9 +106,8 @@ union cvmx_dbg_data
 #endif
 	} cn30xx;
 	struct cvmx_dbg_data_cn30xx           cn31xx;
-	struct cvmx_dbg_data_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dbg_data_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t d_mul                        : 4;  /**< D_MUL pins sampled on DCOK assertion */
 	uint64_t dclk_mul2                    : 1;  /**< Should always be set for fast DDR-II operation */
@@ -132,9 +128,8 @@ union cvmx_dbg_data
 	} cn38xx;
 	struct cvmx_dbg_data_cn38xx           cn38xxp2;
 	struct cvmx_dbg_data_cn30xx           cn50xx;
-	struct cvmx_dbg_data_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dbg_data_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t rem                          : 6;  /**< Remaining debug_select pins sampled at DCOK */
 	uint64_t c_mul                        : 5;  /**< C_MUL pins sampled at DCOK assertion */
diff --git a/sys/contrib/octeon-sdk/cvmx-debug-handler.S b/sys/contrib/octeon-sdk/cvmx-debug-handler.S
index 35389cc..5465625 100644
--- a/sys/contrib/octeon-sdk/cvmx-debug-handler.S
+++ b/sys/contrib/octeon-sdk/cvmx-debug-handler.S
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights 
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights 
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.  
@@ -26,7 +26,7 @@
  * countries. 
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -52,12 +52,13 @@
 #include <asm/octeon/cvmx-asm.h>
 #include <asm/octeon/octeon-boot-info.h>
 #else
-#include "executive-config.h"
+
 #include "cvmx-asm.h"
 
-#ifndef __OCTEON_NEWLIB__
-#include "../../bootloader/u-boot/include/octeon_mem_map.h"
+#ifndef _OCTEON_TOOLCHAIN_RUNTIME
+#include <octeon_mem_map.h>
 #else
+#include "cvmx-platform.h"
 #include "octeon-boot-info.h"
 #endif
 
@@ -97,7 +98,7 @@
 	sd k1, 0(t0);		\
 	addi k0, -8
 
-#define REG_SAVE_BASE_DIV_4  (BOOTLOADER_DEBUG_REG_SAVE_BASE >> 2)
+#define REG_SAVE_BASE_DIV_8  (BOOTLOADER_DEBUG_REG_SAVE_BASE >> 3)
 
 
 #define HW_INSTRUCTION_BREAKPOINT_STATUS            (0xFFFFFFFFFF301000)
@@ -145,10 +146,14 @@ __cvmx_debug_handler_stage2:
         andi    k0, 0xff    // mask off core ID
         sll     k0, 12      // multiply by 4096 (512 dwords) DEBUG_NUMREGS
 
-        addiu   k0,  REG_SAVE_BASE_DIV_4    
-        addiu   k0,  REG_SAVE_BASE_DIV_4
-        addiu   k0,  REG_SAVE_BASE_DIV_4
-        addiu   k0,  REG_SAVE_BASE_DIV_4
+        addiu   k0,  REG_SAVE_BASE_DIV_8
+        addiu   k0,  REG_SAVE_BASE_DIV_8
+        addiu   k0,  REG_SAVE_BASE_DIV_8
+        addiu   k0,  REG_SAVE_BASE_DIV_8
+        addiu   k0,  REG_SAVE_BASE_DIV_8
+        addiu   k0,  REG_SAVE_BASE_DIV_8
+        addiu   k0,  REG_SAVE_BASE_DIV_8
+        addiu   k0,  REG_SAVE_BASE_DIV_8
 		// add base offset - after exeption vectors for all cores
 
         rotr    k0, k0, 31   // set bit 31 for kseg0 access
@@ -241,6 +246,8 @@ noexc:
 #else
 	ld	sp,0(sp)
 #endif
+	mflo	$4
+	mfhi	$5
 	jal	__cvmx_debug_handler_stage3
 	nop
 
diff --git a/sys/contrib/octeon-sdk/cvmx-debug-remote.c b/sys/contrib/octeon-sdk/cvmx-debug-remote.c
index b0808eb..842fb44 100644
--- a/sys/contrib/octeon-sdk/cvmx-debug-remote.c
+++ b/sys/contrib/octeon-sdk/cvmx-debug-remote.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -46,11 +46,10 @@
 #define cvmx_interrupt_in_isr 0
 
 #else
-#include "executive-config.h"
 #include "cvmx.h"
 #include "cvmx-debug.h"
 
-#ifndef __OCTEON_NEWLIB__
+#ifndef CVMX_BUILD_FOR_TOOLCHAIN
 extern int cvmx_interrupt_in_isr;
 #else
 #define cvmx_interrupt_in_isr 0
diff --git a/sys/contrib/octeon-sdk/cvmx-debug-uart.c b/sys/contrib/octeon-sdk/cvmx-debug-uart.c
index 47ca34e..4c80a86 100644
--- a/sys/contrib/octeon-sdk/cvmx-debug-uart.c
+++ b/sys/contrib/octeon-sdk/cvmx-debug-uart.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -55,17 +55,17 @@ int cvmx_debug_uart = 1;
 #include "cvmx-debug.h"
 #include "cvmx-uart.h"
 #include "cvmx-spinlock.h"
-
-#ifndef __OCTEON_NEWLIB__
-#include "../../bootloader/u-boot/include/octeon_mem_map.h"
-#else
 #include "octeon-boot-info.h"
 #endif
 
-#endif
+/* 
+ * NOTE: CARE SHOULD BE TAKEN USING STD C LIBRARY FUNCTIONS IN
+ * THIS FILE IF SOMEONE PUTS A BREAKPOINT ON THOSE FUNCTIONS
+ * DEBUGGING WILL FAIL.
+ */
 
 
-#ifdef __OCTEON_NEWLIB__
+#ifdef CVMX_BUILD_FOR_TOOLCHAIN
 #pragma weak cvmx_uart_enable_intr
 int cvmx_debug_uart = 1;
 #endif
@@ -127,13 +127,30 @@ static void cvmx_debug_uart_init(void)
 static void cvmx_debug_uart_install_break_handler(void)
 {
 #ifndef CVMX_BUILD_FOR_LINUX_KERNEL
-#ifdef __OCTEON_NEWLIB__
+#ifdef CVMX_BUILD_FOR_TOOLCHAIN
     if (cvmx_uart_enable_intr)
 #endif
         cvmx_uart_enable_intr(cvmx_debug_uart, cvmx_debug_uart_process_debug_interrupt);
 #endif
 }
 
+/**
+ * Routines to handle hex data
+ *
+ * @param ch
+ * @return
+ */
+static inline int cvmx_debug_uart_hex(char ch)
+{
+    if ((ch >= 'a') && (ch <= 'f'))
+        return(ch - 'a' + 10);
+    if ((ch >= '0') && (ch <= '9'))
+        return(ch - '0');
+    if ((ch >= 'A') && (ch <= 'F'))
+        return(ch - 'A' + 10);
+    return(-1);
+}
+
 /* Get a packet from the UART, return 0 on failure and 1 on success. */
 
 static int cvmx_debug_uart_getpacket(char *buffer, size_t size)
@@ -174,22 +191,33 @@ static int cvmx_debug_uart_getpacket(char *buffer, size_t size)
 
         if (ch == '#')
         {
-	    char csumchars[2];
+	    char csumchars0, csumchars1;
 	    unsigned xmitcsum;
-	    int n;
+	    int n0, n1;
 
-            csumchars[0] = cvmx_uart_read_byte(cvmx_debug_uart);
-            csumchars[1] = cvmx_uart_read_byte(cvmx_debug_uart);
-	    n = sscanf(csumchars, "%2x", &xmitcsum);
-	    if (n != 1)
-		return 1;
+            csumchars0 = cvmx_uart_read_byte(cvmx_debug_uart);
+            csumchars1 = cvmx_uart_read_byte(cvmx_debug_uart);
+            n0 = cvmx_debug_uart_hex(csumchars0);
+            n1 = cvmx_debug_uart_hex(csumchars1);
+	    if (n0 == -1 || n1 == -1)
+		return 0;
 
+            xmitcsum = (n0 << 4) | n1;
             return checksum == xmitcsum;
         }
     }
     return 0;
 }
 
+/* Put the hex value of t into str. */
+static void cvmx_debug_uart_strhex(char *str, unsigned char t)
+{
+  char hexchar[] = "0123456789ABCDEF";
+  str[0] = hexchar[(t>>4)];
+  str[1] = hexchar[t&0xF];
+  str[2] = 0;
+}
+
 static int cvmx_debug_uart_putpacket(char *packet)
 {
     size_t i;
@@ -199,7 +227,7 @@ static int cvmx_debug_uart_putpacket(char *packet)
 
     for (csum = 0, i = 0; ptr[i]; i++)
       csum += ptr[i];
-    sprintf(csumstr, "%02x", csum);
+    cvmx_debug_uart_strhex(csumstr, csum);
 
     cvmx_spinlock_lock(&cvmx_debug_uart_lock);
     cvmx_uart_write_byte(cvmx_debug_uart, '$');
@@ -217,12 +245,12 @@ static void cvmx_debug_uart_change_core(int oldcore, int newcore)
     cvmx_ciu_intx0_t irq_control;
 
     irq_control.u64 = cvmx_read_csr(CVMX_CIU_INTX_EN0(newcore * 2));
-    irq_control.s.uart |= (1<<cvmx_debug_uart);
+    irq_control.s.uart |= (1u<<cvmx_debug_uart);
     cvmx_write_csr(CVMX_CIU_INTX_EN0(newcore * 2), irq_control.u64);
 
     /* Disable interrupts to this core since he is about to die */
     irq_control.u64 = cvmx_read_csr(CVMX_CIU_INTX_EN0(oldcore * 2));
-    irq_control.s.uart &= ~(1<<cvmx_debug_uart);
+    irq_control.s.uart &= ~(1u<<cvmx_debug_uart);
     cvmx_write_csr(CVMX_CIU_INTX_EN0(oldcore* 2), irq_control.u64);
 #endif
 }
diff --git a/sys/contrib/octeon-sdk/cvmx-debug.c b/sys/contrib/octeon-sdk/cvmx-debug.c
index e615cbc..223f7eb 100644
--- a/sys/contrib/octeon-sdk/cvmx-debug.c
+++ b/sys/contrib/octeon-sdk/cvmx-debug.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -42,6 +42,9 @@
  * @file
  *
  * Interface to debug exception handler
+ * NOTE: CARE SHOULD BE TAKE WHEN USING STD C LIBRARY FUNCTIONS IN
+ * THIS FILE IF SOMEONE PUTS A BREAKPOINT ON THOSE FUNCTIONS
+ * DEBUGGING WILL FAIL.
  *
  * <hr>$Revision: 50060 $<hr>
  */
@@ -56,21 +59,14 @@
 #include <asm/octeon/octeon-boot-info.h>
 #else
 #include <stdint.h>
-#include "executive-config.h"
 #include "cvmx.h"
 #include "cvmx-debug.h"
 #include "cvmx-bootmem.h"
 #include "cvmx-core.h"
 #include "cvmx-coremask.h"
-
-#ifndef __OCTEON_NEWLIB__
-#include "../../bootloader/u-boot/include/octeon_mem_map.h"
-#else
 #include "octeon-boot-info.h"
 #endif
 
-#endif
-
 #ifdef CVMX_DEBUG_LOGGING
 # undef CVMX_DEBUG_LOGGING
 # define CVMX_DEBUG_LOGGING 1
@@ -119,33 +115,84 @@ volatile uint64_t __cvmx_debug_mode_exception_occured;
 static char cvmx_debug_stack[8*1024] __attribute ((aligned (16)));
 char *__cvmx_debug_stack_top = &cvmx_debug_stack[8*1024];
 
-#ifndef __OCTEON_NEWLIB__
+#ifndef CVMX_BUILD_FOR_TOOLCHAIN
 extern int cvmx_interrupt_in_isr;
 #else
 #define cvmx_interrupt_in_isr 0
 #endif
 
 #else
-uint64_t __cvmx_debug_save_regs_area_all[OCTEON_NUM_CORES][32];
+uint64_t __cvmx_debug_save_regs_area_all[CVMX_MAX_CORES][32];
 #define __cvmx_debug_save_regs_area __cvmx_debug_save_regs_area_all[cvmx_get_core_num()]
 
-volatile uint64_t __cvmx_debug_mode_exception_ignore_all[OCTEON_NUM_CORES];
+volatile uint64_t __cvmx_debug_mode_exception_ignore_all[CVMX_MAX_CORES];
 #define __cvmx_debug_mode_exception_ignore __cvmx_debug_mode_exception_ignore_all[cvmx_get_core_num()]
-volatile uint64_t __cvmx_debug_mode_exception_occured_all[OCTEON_NUM_CORES];
+volatile uint64_t __cvmx_debug_mode_exception_occured_all[CVMX_MAX_CORES];
 #define __cvmx_debug_mode_exception_occured __cvmx_debug_mode_exception_occured_all[cvmx_get_core_num()]
 
-static char cvmx_debug_stack_all[OCTEON_NUM_CORES][8*1024] __attribute ((aligned (16)));
-char *__cvmx_debug_stack_top_all[OCTEON_NUM_CORES];
+static char cvmx_debug_stack_all[CVMX_MAX_CORES][8*1024] __attribute ((aligned (16)));
+char *__cvmx_debug_stack_top_all[CVMX_MAX_CORES];
 
 #define cvmx_interrupt_in_isr 0
 
 #endif
 
 
+static size_t cvmx_debug_strlen (const char *str)
+{
+    size_t size = 0;
+    while (*str)
+    {
+        size++;
+        str++;
+    }
+    return size;
+}
+static void cvmx_debug_strcpy (char *dest, const char *src)
+{
+    while (*src)
+    {
+        *dest = *src;
+        src++;
+        dest++;
+    }
+    *dest = 0;
+}
+
+static void cvmx_debug_memcpy_align (void *dest, const void *src, int size) __attribute__ ((__noinline__));
+static void cvmx_debug_memcpy_align (void *dest, const void *src, int size)
+{
+  long long *dest1 = (long long*)dest;
+  const long long *src1 = (const long long*)src;
+  int i;
+  if (size == 40)
+  {
+    long long a0, a1, a2, a3, a4;
+    a0 = src1[0];
+    a1 = src1[1];
+    a2 = src1[2];
+    a3 = src1[3];
+    a4 = src1[4];
+    dest1[0] = a0;
+    dest1[1] = a1;
+    dest1[2] = a2;
+    dest1[3] = a3;
+    dest1[4] = a4;
+    return;
+  }
+  for(i = 0;i < size;i+=8)
+  {
+    *dest1 = *src1;
+    dest1++;
+    src1++;
+  }
+}
+
+
 static inline uint32_t cvmx_debug_core_mask(void)
 {
 #ifndef CVMX_BUILD_FOR_LINUX_KERNEL
-#ifdef __OCTEON_NEWLIB__
+#ifdef CVMX_BUILD_FOR_TOOLCHAIN
   extern int __octeon_core_mask;
   return __octeon_core_mask;
 #endif
@@ -157,13 +204,13 @@ return octeon_get_boot_coremask ();
 
 static inline void cvmx_debug_update_state(cvmx_debug_state_t state)
 {
-    memcpy(cvmx_debug_globals->state, &state, sizeof(cvmx_debug_state_t));
+    cvmx_debug_memcpy_align(cvmx_debug_globals->state, &state, sizeof(cvmx_debug_state_t));
 }
 
 static inline cvmx_debug_state_t cvmx_debug_get_state(void)
 {
     cvmx_debug_state_t state;
-    memcpy(&state, cvmx_debug_globals->state, sizeof(cvmx_debug_state_t));
+    cvmx_debug_memcpy_align(&state, cvmx_debug_globals->state, sizeof(cvmx_debug_state_t));
     return state;
 }
 
@@ -201,53 +248,31 @@ static int cvmx_debug_enabled(void)
     return cvmx_debug_booted() || CVMX_DEBUG_ATTACH;
 }
 
+static void cvmx_debug_init_global_ptr (void *ptr)
+{
+    uint64_t phys = cvmx_ptr_to_phys (ptr);
+    cvmx_debug_globals_t *p;
+    /* Since at this point, TLBs are not mapped 1 to 1, we should just use KSEG0 accesses. */
+    p = CASTPTR(cvmx_debug_globals_t, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, phys));
+    memset (p, 0, sizeof(cvmx_debug_globals_t));
+    p->version = CVMX_DEBUG_GLOBALS_VERSION;
+    p->tlb_entries = cvmx_core_get_tlb_entries();
+}
+
 static void cvmx_debug_init_globals(void)
 {
-    int toclear = 0;
     uint64_t phys;
-    void *a;
+    void *ptr;
 
     if (cvmx_debug_globals)
         return;
+    ptr = cvmx_bootmem_alloc_named_range_once(sizeof(cvmx_debug_globals_t), 0, /* KSEG0 max, 512MB=*/0/*1024*1024*512*/, 8,
+                                              CVMX_DEBUG_GLOBALS_BLOCK_NAME, cvmx_debug_init_global_ptr);
+    phys = cvmx_ptr_to_phys (ptr);
 
-    if (cvmx_get_core_num() != 0)
-    {
-        volatile size_t i;
-        /* Delay here just enough for the writing of the version. */
-        for(i = 0; i < sizeof(cvmx_debug_globals_t)/2 + 8; i++)
-          ;
-    }
-
-    a = cvmx_bootmem_alloc_named(sizeof(cvmx_debug_globals_t), 8, CVMX_DEBUG_GLOBALS_BLOCK_NAME);
-    if (a)
-    {
-       phys = cvmx_ptr_to_phys(a);
-       toclear = 1;
-    }
-    else
-    {
-        const cvmx_bootmem_named_block_desc_t *debug_globals_nblk;
-        debug_globals_nblk = cvmx_bootmem_find_named_block (CVMX_DEBUG_GLOBALS_BLOCK_NAME);
-        phys = debug_globals_nblk->base_addr;
-    }
+    /* Since TLBs are not always mapped 1 to 1, we should just use access via KSEG0. */
     cvmx_debug_globals = CASTPTR(cvmx_debug_globals_t, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, phys));
     cvmx_debug_printf("Debug named block at %p\n", cvmx_debug_globals);
-    if (toclear)
-        cvmx_debug_printf("Debug named block cleared\n");
-
-    if (toclear)
-    {
-        memset (cvmx_debug_globals, 0, sizeof(cvmx_debug_globals_t));
-        cvmx_debug_globals->version = CVMX_DEBUG_GLOBALS_VERSION;
-        cvmx_debug_globals->tlb_entries = cvmx_core_get_tlb_entries();
-    }
-    else
-    {
-        volatile size_t i;
-        /* Delay here just enough for the writing of the version. */
-        for(i = 0; i < sizeof(cvmx_debug_globals_t) + 8; i++)
-          ;
-    }
 }
 
 
@@ -265,7 +290,7 @@ static void cvmx_debug_globals_check_version(void)
 }
 
 static inline volatile cvmx_debug_core_context_t *cvmx_debug_core_context(void);
-static inline void cvmx_debug_save_core_context(volatile cvmx_debug_core_context_t *context);
+static inline void cvmx_debug_save_core_context(volatile cvmx_debug_core_context_t *context, uint64_t hi, uint64_t lo);
 
 void cvmx_debug_init(void)
 {
@@ -295,9 +320,9 @@ void cvmx_debug_init(void)
     /*  Install the debugger handler on the cores. */
     {
         int core1 = 0;
-        for (core1 = 0; core1 < OCTEON_NUM_CORES; core1++)
+        for (core1 = 0; core1 < CVMX_MAX_CORES; core1++)
         {
-            if ((1<<core1) & coremask)
+            if ((1u<<core1) & coremask)
                 cvmx_debug_install_handler(core1);
         }
     }
@@ -315,8 +340,8 @@ void cvmx_debug_init(void)
         state.known_cores |= coremask;
         state.core_finished &= ~coremask;
 #else
-        state.known_cores |= (1 << core);
-        state.core_finished &= ~(1 << core);
+        state.known_cores |= (1u << core);
+        state.core_finished &= ~(1u << core);
 #endif
         cvmx_debug_update_state(state);
         cvmx_spinlock_unlock(lock);
@@ -342,7 +367,7 @@ void cvmx_debug_init(void)
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
         {
             int i;
-            for (i = 0; i < OCTEON_NUM_CORES; i++)
+            for (i = 0; i < CVMX_MAX_CORES; i++)
                 __cvmx_debug_stack_top_all[i] = &cvmx_debug_stack_all[i][8*1024];
         }
 #endif
@@ -367,27 +392,34 @@ void cvmx_debug_init(void)
     }
 }
 
-static int cvmx_debug_putpacket_noformat(char *packet);
-
-static __attribute__ ((format (printf, 1, 2))) int cvmx_debug_putpacket(char *format, ...)
+static const char cvmx_debug_hexchar[] = "0123456789ABCDEF";
+/* Put the hex value of t into str. */
+static void cvmx_debug_int8_to_strhex(char *str, unsigned char t)
 {
-    va_list ap;
-    size_t n;
-    char packet[CVMX_DEBUG_MAX_RESPONSE_SIZE];
-
-    if (cvmx_debug_comms[cvmx_debug_globals->comm_type]->putpacket == NULL)
-        return 0;
-
-    va_start(ap, format);
-    n = vsnprintf(packet, sizeof(packet), format, ap);
-    va_end(ap);
+  str[0] = cvmx_debug_hexchar[(t>>4)&0xf];
+  str[1] = cvmx_debug_hexchar[t&0xF];
+  str[2] = 0;
+}
 
-    if (n >= sizeof(packet))
-    {
-        cvmx_debug_printf("packet truncated (needed %d bytes): %s\n", (int)n, packet);
-        return 0;
-    }
-    return cvmx_debug_putpacket_noformat(packet);
+static void cvmx_debug_int64_to_strhex(char *str, uint64_t t)
+{
+  str[0] = cvmx_debug_hexchar[(t>>60)&0xF];
+  str[1] = cvmx_debug_hexchar[(t>>56)&0xF];
+  str[2] = cvmx_debug_hexchar[(t>>52)&0xF];
+  str[3] = cvmx_debug_hexchar[(t>>48)&0xF];
+  str[4] = cvmx_debug_hexchar[(t>>44)&0xF];
+  str[5] = cvmx_debug_hexchar[(t>>40)&0xF];
+  str[6] = cvmx_debug_hexchar[(t>>36)&0xF];
+  str[7] = cvmx_debug_hexchar[(t>>32)&0xF];
+  str[8] = cvmx_debug_hexchar[(t>>28)&0xF];
+  str[9] = cvmx_debug_hexchar[(t>>24)&0xF];
+  str[10] = cvmx_debug_hexchar[(t>>20)&0xF];
+  str[11] = cvmx_debug_hexchar[(t>>16)&0xF];
+  str[12] = cvmx_debug_hexchar[(t>>12)&0xF];
+  str[13] = cvmx_debug_hexchar[(t>>8)&0xF];
+  str[14] = cvmx_debug_hexchar[(t>>4)&0xF];
+  str[15] = cvmx_debug_hexchar[(t>>0)&0xF];
+  str[16] = 0;
 }
 
 static int cvmx_debug_putpacket_noformat(char *packet)
@@ -398,9 +430,50 @@ static int cvmx_debug_putpacket_noformat(char *packet)
     return cvmx_debug_comms[cvmx_debug_globals->comm_type]->putpacket(packet);
 }
 
-static int cvmx_debug_active_core(cvmx_debug_state_t state, int core)
+static int cvmx_debug_putcorepacket(char *buf, int core)
 {
-    return state.active_cores & (1 << core);
+     char *tmp = "!Core XX ";
+     int tmpsize = cvmx_debug_strlen(tmp);
+     int bufsize = cvmx_debug_strlen(buf);
+     char *packet = __builtin_alloca(tmpsize + bufsize + 1);
+     cvmx_debug_strcpy(packet, tmp);
+     cvmx_debug_strcpy(&packet[tmpsize], buf);
+     if (core < 10)
+     {
+         packet[6] = ' ';
+         packet[7] = core + '0';
+     }
+     else if (core < 20)
+     {
+         packet[6] = '1';
+         packet[7] = core - 10 + '0';
+     }
+     else if (core < 30)
+     {
+         packet[6] = '2';
+         packet[7] = core - 20 + '0';
+     }
+     else
+     {
+         packet[6] = '3';
+         packet[7] = core - 30 + '0';
+     }
+     return cvmx_debug_putpacket_noformat(packet);
+}
+
+/* Put a buf followed by an integer formated as a hex.  */
+static int cvmx_debug_putpacket_hexint(char *buf, uint64_t value)
+{
+    size_t size = cvmx_debug_strlen(buf);
+    char *packet = __builtin_alloca(size + 16 + 1);
+    cvmx_debug_strcpy(packet, buf);
+    cvmx_debug_int64_to_strhex(&packet[size], value);
+    return cvmx_debug_putpacket_noformat(packet);
+}
+
+static int cvmx_debug_active_core(cvmx_debug_state_t state, unsigned core)
+{
+    return state.active_cores & (1u << core);
 }
 
 static volatile cvmx_debug_core_context_t *cvmx_debug_core_context(void)
@@ -470,22 +543,59 @@ static int cvmx_debug_probe_store(unsigned char *ptr)
     return ok;
 }
 
-/* Put the hex value of t into str. */
-static void strhex(char *str, unsigned char t)
+
+/**
+ * Routines to handle hex data
+ *
+ * @param ch
+ * @return
+ */
+static inline int cvmx_debug_hex(char ch)
 {
-  char a[] = "0123456789ABCDEF";
-  str[0] = a[(t>>4)];
-  str[1] = a[t&0xF];
-  str[2] = 0;
+    if ((ch >= 'a') && (ch <= 'f'))
+        return(ch - 'a' + 10);
+    if ((ch >= '0') && (ch <= '9'))
+        return(ch - '0');
+    if ((ch >= 'A') && (ch <= 'F'))
+        return(ch - 'A' + 10);
+    return(-1);
+}
+
+/**
+ * While we find nice hex chars, build an int.
+ * Return number of chars processed.
+ *
+ * @param ptr
+ * @param intValue
+ * @return
+ */
+static int cvmx_debug_hexToLong(const char **ptr, uint64_t *intValue)
+{
+    int numChars = 0;
+    long hexValue;
+
+    *intValue = 0;
+    while (**ptr)
+    {
+        hexValue = cvmx_debug_hex(**ptr);
+        if (hexValue < 0)
+            break;
+
+        *intValue = (*intValue << 4) | hexValue;
+        numChars ++;
+
+        (*ptr)++;
+    }
+
+    return(numChars);
 }
 
 /**
   * Initialize the performance counter control registers.
   *
   */
-static void cvmx_debug_set_perf_control_reg (int perf_event, int perf_counter)
+static void cvmx_debug_set_perf_control_reg (volatile cvmx_debug_core_context_t *context, int perf_event, int perf_counter)
 {
-    volatile cvmx_debug_core_context_t *context = cvmx_debug_core_context();
     cvmx_core_perf_control_t control;
 
     control.u32 = 0;
@@ -500,7 +610,7 @@ static void cvmx_debug_set_perf_control_reg (int perf_event, int perf_counter)
     context->cop0.perfctrl[perf_counter] = control.u32;
 }
 
-static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
+static cvmx_debug_command_t cvmx_debug_process_packet(const char *packet)
 {
     const char *buf = packet;
     cvmx_debug_command_t result = COMMAND_NOP;
@@ -519,18 +629,20 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
 
         case 'F':   /* Change the focus core */
         {
-            int core;
-            sscanf(buf, "%x", &core);
-
+            uint64_t core;
+            if (!cvmx_debug_hexToLong(&buf, &core))
+            {
+                cvmx_debug_putpacket_noformat("!Uknown core.  Focus not changed.");
+            }
             /* Only cores in the exception handler may become the focus.
-            If a core not in the exception handler got focus the
-            debugger would hang since nobody would talk to it.  */
-            if (state.handler_cores & (1 << core))
+               If a core not in the exception handler got focus the
+               debugger would hang since nobody would talk to it.  */
+            else if (state.handler_cores & (1u << core))
             {
                 /* Focus change reply must be sent before the focus
-                changes. Otherwise the new focus core will eat our ACK
-                from the debugger.  */
-                cvmx_debug_putpacket("F%02x", core);
+                   changes. Otherwise the new focus core will eat our ACK
+                   from the debugger.  */
+                cvmx_debug_putpacket_hexint("F", core);
                 cvmx_debug_comms[cvmx_debug_globals->comm_type]->change_core(state.focus_core, core);
                 state.focus_core = core;
                 cvmx_debug_update_state(state);
@@ -542,7 +654,7 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
         }
         /* fall through */
         case 'f':   /* Get the focus core */
-            cvmx_debug_putpacket("F%02x", (unsigned)state.focus_core);
+            cvmx_debug_putpacket_hexint("F", state.focus_core);
             break;
 
         case 'J': /* Set the flag for skip-over-isr in Single-Stepping mode */
@@ -557,14 +669,15 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
            same as the get step-isr command */
 
         case 'j':   /* Reply with step_isr status  */
-            cvmx_debug_putpacket("J%x", (unsigned)state.step_isr);
+            cvmx_debug_putpacket_hexint("J", (unsigned)state.step_isr);
             break;
 
 
         case 'I':   /* Set the active cores */
         {
-            long long active_cores;
-            sscanf(buf, "%llx", &active_cores);
+            uint64_t active_cores;
+            if (!cvmx_debug_hexToLong(&buf, &active_cores))
+                active_cores = 0;
             /* Limit the active mask to the known to exist cores */
             state.active_cores = active_cores & state.known_cores;
 
@@ -573,10 +686,10 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
                 state.active_cores = state.known_cores;
 
             /* The focus core must be in the active_cores mask */
-            if ((state.active_cores & (1 << state.focus_core)) == 0)
+            if ((state.active_cores & (1u << state.focus_core)) == 0)
             {
                 cvmx_debug_putpacket_noformat("!Focus core was added to the masked.");
-                state.active_cores |= 1 << state.focus_core;
+                state.active_cores |= 1u << state.focus_core;
             }
 
             cvmx_debug_update_state(state);
@@ -585,7 +698,7 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
            same as the get active cores command */
 
         case 'i':   /* Get the active cores */
-            cvmx_debug_putpacket("I%llx", (long long) state.active_cores);
+            cvmx_debug_putpacket_hexint("I", state.active_cores);
             break;
 
         case 'A':   /* Setting the step mode all or one */
@@ -600,34 +713,46 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
            same as the get step-all command */
 
         case 'a':   /* Getting the current step mode */
-            cvmx_debug_putpacket("A%x", (unsigned)state.step_all);
+            cvmx_debug_putpacket_hexint("A", state.step_all);
             break;
 
         case 'g':   /* read a register from global place. */
         {
             volatile cvmx_debug_core_context_t *context = cvmx_debug_core_context();
-            int regno;
+            uint64_t regno;
             volatile uint64_t *reg;
 
             /* Get the register number to read */
-            sscanf(buf, "%x", &regno);
+            if (!cvmx_debug_hexToLong(&buf, &regno))
+            {
+                cvmx_debug_printf("Register number cannot be read.\n");
+                cvmx_debug_putpacket_hexint("", 0xDEADBEEF);
+                break;
+            }
 
             reg = cvmx_debug_regnum_to_context_ref(regno, context);
             if (!reg)
-                cvmx_debug_printf("Register #%d is not valid\n", regno);
-            cvmx_debug_putpacket("%llx", (unsigned long long) *reg);
+            {
+                cvmx_debug_printf("Register #%d is not valid\n", (int)regno);
+                cvmx_debug_putpacket_hexint("", 0xDEADBEEF);
+                break;
+            }
+            cvmx_debug_putpacket_hexint("", *reg);
         }
         break;
 
         case 'G':   /* set the value of a register. */
         {
             volatile cvmx_debug_core_context_t *context = cvmx_debug_core_context();
-            int regno;
+            uint64_t regno;
             volatile uint64_t *reg;
-            long long value;
+            uint64_t value;
 
-            /* Get the register number to read */
-            if (sscanf(buf, "%x,%llx", &regno, &value) != 2)
+            /* Get the register number to write. It should be followed by
+               a comma */
+            if (!cvmx_debug_hexToLong(&buf, &regno)
+                || (*buf++ != ',')
+                || !cvmx_debug_hexToLong(&buf, &value))
             {
                 cvmx_debug_printf("G packet corrupt: %s\n", buf);
                 goto error_packet;
@@ -636,7 +761,7 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
             reg = cvmx_debug_regnum_to_context_ref(regno, context);
             if (!reg)
             {
-                cvmx_debug_printf("Register #%d is not valid\n", regno);
+                cvmx_debug_printf("Register #%d is not valid\n", (int)regno);
                 goto error_packet;
             }
             *reg = value;
@@ -645,18 +770,21 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
 
         case 'm':   /* Memory read. mAA..AA,LLLL  Read LLLL bytes at address AA..AA */
         {
-            long long addr, i, length;
+            uint64_t addr, i, length;
             unsigned char *ptr;
             char *reply;
 
-            if (sscanf(buf, "%llx,%llx", &addr, &length) != 2)
+            /* Get the memory address, a comma, and the length */
+            if (!cvmx_debug_hexToLong(&buf, &addr)
+                || (*buf++ != ',')
+                || !cvmx_debug_hexToLong(&buf, &length))
             {
                 cvmx_debug_printf("m packet corrupt: %s\n", buf);
                 goto error_packet;
             }
             if (length >= 1024)
             {
-                cvmx_debug_printf("m packet length out of range: %lld\n", length);
+                cvmx_debug_printf("m packet length out of range: %lld\n", (long long)length);
                 goto error_packet;
             }
 
@@ -668,7 +796,7 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
                 unsigned char t;
                 if (!cvmx_debug_probe_load(&ptr[i], &t))
                   goto error_packet;
-                strhex(&reply[i * 2], t);
+                cvmx_debug_int8_to_strhex(&reply[i * 2], t);
             }
             cvmx_debug_putpacket_noformat(reply);
         }
@@ -676,28 +804,31 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
 
         case 'M':   /* Memory write. MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */
         {
-            long long addr, i, length;
+            uint64_t addr, i, length;
             unsigned char *ptr;
-            char value[1024];
 
-            if (sscanf(buf, "%llx,%llx:%1024s", &addr, &length, value) != 3)
+            if (!cvmx_debug_hexToLong(&buf, &addr)
+                || *buf++ != ','
+                || !cvmx_debug_hexToLong(&buf, &length)
+                || *buf++ != ':')
             {
                 cvmx_debug_printf("M packet corrupt: %s\n", buf);
                 goto error_packet;
             }
-            
+
             ptr = (unsigned char *)(long)addr;
             for (i = 0; i < length; i++)
             {
-                int c;
-                int n;
-                char tempstr[3] = {0, 0, 0};
-                memcpy (tempstr, &value[i * 2], 2);
+                int n, n1;
+                unsigned char c;
+
+                n = cvmx_debug_hex(buf[i * 2]);
+                n1 = cvmx_debug_hex(buf[i * 2 + 1]);
+                c = (n << 4) | n1;
             
-                n = sscanf(tempstr, "%2x", &c);
-                if (n != 1)
+                if (n == -1 || n1 == -1)
                 {
-                    cvmx_debug_printf("M packet corrupt: %s\n", &value[i * 2]);
+                    cvmx_debug_printf("M packet corrupt: %s\n", &buf[i * 2]);
                     goto error_packet;
                 }
                 /* Probe memory.  If not accessible fail.   */
@@ -716,30 +847,38 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
                       is the performance counter to set X is the performance
                       event.  [34] is to get the same thing.  */
         {
-            int perf_event = 0;
-            int counter, encoded_counter;
+            uint64_t perf_event = 0;
+            char encoded_counter = *buf++;
+            uint64_t counter;
             volatile cvmx_debug_core_context_t *context = cvmx_debug_core_context();
-            sscanf(buf, "%1d%x", &encoded_counter, &perf_event);
+
+            /* Ignore errors from the packet. */
+            cvmx_debug_hexToLong(&buf, &perf_event);
 
             switch (encoded_counter)
             {
-                case 1: /* Set performance counter0 event. */
-                case 2: /* Set performance counter1 event. */
+                case '1': /* Set performance counter0 event. */
+                case '2': /* Set performance counter1 event. */
 
-                counter = encoded_counter - 1;
+                counter = encoded_counter - '1';
                 context->cop0.perfval[counter] = 0;
-                cvmx_debug_set_perf_control_reg(perf_event, counter);
+                cvmx_debug_set_perf_control_reg(context, perf_event, counter);
                 break;
 
-                case 3: /* Get performance counter0 event. */
-                case 4: /* Get performance counter1 event. */
+                case '3': /* Get performance counter0 event. */
+                case '4': /* Get performance counter1 event. */
                 {
                     cvmx_core_perf_control_t c;
-                    counter = encoded_counter - 3;
+                    char outpacket[16*2 +2];
+                    counter = encoded_counter - '3';
                     /* Pass performance counter0 event and counter to
                        the debugger.  */
                     c.u32 = context->cop0.perfctrl[counter];
-                    cvmx_debug_putpacket("%llx,%llx", (long long) context->cop0.perfval[counter], (long long) c.s.event);
+                    cvmx_debug_int64_to_strhex(outpacket, context->cop0.perfval[counter]);
+                    outpacket[16] = ',';
+                    cvmx_debug_int64_to_strhex(&outpacket[17], c.s.event);
+                    outpacket[33] = 0;
+                    cvmx_debug_putpacket_noformat(outpacket);
                 }
                 break;
             }
@@ -782,21 +921,27 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
                 WP_ACCESS = 3
             };
 
-            int num, size;
-            long long addr;
-            enum type type;
-            char bp_type;
+            uint64_t num, size;
+            uint64_t addr;
+            uint64_t type;
+            char bp_type = *buf++;
             const int BE = 1, TE = 4;
-            int n;
             volatile cvmx_debug_core_context_t *context = cvmx_debug_core_context();
 
-            n = sscanf(buf, "%c%x,%llx,%x,%x", &bp_type, &num, &addr, &size, &type);
+            if (!cvmx_debug_hexToLong(&buf, &num)
+                || *buf++ != ','
+                || !cvmx_debug_hexToLong(&buf, &addr))
+            {
+                cvmx_debug_printf("Z packet corrupt: %s\n", &packet[1]);
+                goto error_packet;
+            }
+
             switch (bp_type)
             {
                 case 'i':	// Instruction hardware breakpoint
-                    if (n != 3 || num > 4)
+                    if (num > 4)
                     {
-                        cvmx_debug_printf("Z packet corrupt: %s\n", buf);
+                        cvmx_debug_printf("Z packet corrupt: %s\n", &packet[1]);
                         goto error_packet;
                     }
 
@@ -810,9 +955,15 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
                 {
                     uint64_t dbc = 0xff0 | BE | TE;
                     uint64_t dbm;
-                    if (n != 5 || num > 4)
+                    if (num > 4
+                        || *buf++ != ','
+                        || !cvmx_debug_hexToLong(&buf, &size)
+                        || *buf++ != ','
+                        || !cvmx_debug_hexToLong(&buf, &type)
+                        || type > WP_ACCESS
+                        || type < WP_LOAD)
                     {
-                        cvmx_debug_printf("Z packet corrupt: %s\n", buf);
+                        cvmx_debug_printf("Z packet corrupt: %s\n", &packet[1]);
                         goto error_packet;
                     }
 
@@ -831,7 +982,7 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
                     break;
                 }
                 default:
-                    cvmx_debug_printf("z packet corrupt: %s\n", buf);
+                    cvmx_debug_printf("Z packet corrupt: %s\n", &packet[1]);
                     goto error_packet;
             }
         }
@@ -840,11 +991,11 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
         case 'z': /* Remove hardware breakpoint: z[di]NN..N remove NN..Nth
 breakpoint.  */
         {
-            int num;
-            char bp_type;
+            uint64_t num;
+            char bp_type = *buf++;
             volatile cvmx_debug_core_context_t *context = cvmx_debug_core_context();
 
-            if (sscanf(buf, "%c%x", &bp_type, &num) != 2 || num > 4)
+            if (!cvmx_debug_hexToLong(&buf, &num) || num > 4)
             {
                 cvmx_debug_printf("z packet corrupt: %s\n", buf);
                 goto error_packet;
@@ -919,7 +1070,7 @@ static int cvmx_debug_stop_core(cvmx_debug_state_t state, unsigned core, cvmx_de
         cvmx_debug_printf("Core #%d not in active cores, continuing.\n", core);
         return 0;
     }
-    if ((state.core_finished & (1<<core)) && proxy)
+    if ((state.core_finished & (1u<<core)) && proxy)
       return 0;
     return 1;
 }
@@ -936,7 +1087,7 @@ static int cvmx_debug_single_step_exc(cvmx_debug_register_t *debug_reg)
 static void cvmx_debug_set_focus_core(cvmx_debug_state_t *state, int core)
 {
     if (state->ever_been_in_debug)
-        cvmx_debug_putpacket("!Core %2x taking focus.", core);
+        cvmx_debug_putcorepacket("taking focus.", core);
     cvmx_debug_comms[cvmx_debug_globals->comm_type]->change_core (state->focus_core, core);
     state->focus_core = core;
 }
@@ -944,7 +1095,7 @@ static void cvmx_debug_set_focus_core(cvmx_debug_state_t *state, int core)
 static void cvmx_debug_may_elect_as_focus_core(cvmx_debug_state_t *state, int core, cvmx_debug_register_t *debug_reg)
 {
     /* If another core has already elected itself as the focus core, we're late.  */
-    if (state->handler_cores & (1 << state->focus_core))
+    if (state->handler_cores & (1u << state->focus_core))
         return;
 
     /* If we hit a breakpoint, elect ourselves.  */
@@ -954,7 +1105,7 @@ static void cvmx_debug_may_elect_as_focus_core(cvmx_debug_state_t *state, int co
     /* It is possible the focus core has completed processing and exited the
        program. When this happens the focus core will not be in
        known_cores. If this is the case we need to elect a new focus. */
-    if ((state->known_cores & (1 << state->focus_core)) == 0)
+    if ((state->known_cores & (1u << state->focus_core)) == 0)
         cvmx_debug_set_focus_core(state, core);
 }
 
@@ -962,7 +1113,7 @@ static void cvmx_debug_send_stop_reason(cvmx_debug_register_t *debug_reg, volati
 {
     /* Handle Debug Data Breakpoint Store/Load Exception. */
     if (debug_reg->s.ddbs || debug_reg->s.ddbl)
-        cvmx_debug_putpacket("T8:%x", (int) context->hw_dbp.status);
+        cvmx_debug_putpacket_hexint("T8:", (int) context->hw_dbp.status);
     else
         cvmx_debug_putpacket_noformat("T9");
 }
@@ -980,10 +1131,12 @@ static void cvmx_debug_clear_status(volatile cvmx_debug_core_context_t *context)
 
 static void cvmx_debug_sync_up_cores(void)
 {
-    cvmx_debug_state_t state;
+    /* NOTE this reads directly from the state array for speed reasons
+       and we don't change the array. */
     do {
-        state = cvmx_debug_get_state();
-    } while (state.step_all && state.handler_cores != 0);
+      asm("": : : "memory");
+    } while (cvmx_debug_globals->state[offsetof(cvmx_debug_state_t, step_all)/sizeof(uint32_t)]
+	     && cvmx_debug_globals->state[offsetof(cvmx_debug_state_t, handler_cores)/sizeof(uint32_t)] != 0);
 }
 
 /* Delay the focus core a little if it is likely another core needs to steal
@@ -993,7 +1146,7 @@ static void cvmx_debug_delay_focus_core(cvmx_debug_state_t state, unsigned core,
     volatile int i;
     if (debug_reg->s.dss || debug_reg->s.dbp || core != state.focus_core)
         return;
-    for (i = 0; i < 24000; i++)
+    for (i = 0; i < 2400; i++)
     {
         asm volatile (".set push		\n\t"
                       ".set noreorder		\n\t"
@@ -1086,7 +1239,7 @@ static int cvmx_debug_perform_proxy(cvmx_debug_register_t *debug_reg, volatile c
         cvmx_spinlock_lock(&cvmx_debug_globals->lock);
         state = cvmx_debug_get_state();
 
-        state.handler_cores |= (1 << core);
+        state.handler_cores |= (1u << core);
         cvmx_debug_may_elect_as_focus_core(&state, core, debug_reg);
 
 /* Push all updates before exiting the critical section */
@@ -1098,10 +1251,17 @@ static int cvmx_debug_perform_proxy(cvmx_debug_register_t *debug_reg, volatile c
         cvmx_debug_send_stop_reason(debug_reg, context);
 
     do {
+        unsigned oldfocus = state.focus_core;
         state = cvmx_debug_get_state();
         /* Note the focus core can change in this loop. */
         if (__cvmx_debug_in_focus(state, core))
         {
+            /* If the focus has changed and the old focus has exited, then send a signal
+               that we should stop if step_all is off.  */
+            if (oldfocus != state.focus_core && ((1u << oldfocus) & state.core_finished)
+                && !state.step_all)
+              cvmx_debug_send_stop_reason(debug_reg, context);
+
             command = cvmx_debug_process_next_packet();
             state = cvmx_debug_get_state();
             /* When resuming let the other cores resume as well with
@@ -1135,7 +1295,7 @@ static int cvmx_debug_perform_proxy(cvmx_debug_register_t *debug_reg, volatile c
     {
         cvmx_spinlock_lock(&cvmx_debug_globals->lock);
         state = cvmx_debug_get_state();
-        state.handler_cores ^= (1 << core);
+        state.handler_cores ^= (1u << core);
         cvmx_debug_update_state(state);
         cvmx_spinlock_unlock(&cvmx_debug_globals->lock);
     }
@@ -1153,12 +1313,12 @@ static int cvmx_debug_perform_proxy(cvmx_debug_register_t *debug_reg, volatile c
     return 0;
 }
 
-static void cvmx_debug_save_core_context(volatile cvmx_debug_core_context_t *context)
+static void cvmx_debug_save_core_context(volatile cvmx_debug_core_context_t *context, uint64_t hi, uint64_t lo)
 {
     unsigned i;
-    memcpy((char *) context->regs, __cvmx_debug_save_regs_area, sizeof(context->regs));
-    asm("mflo %0" : "=r"(context->lo));
-    asm("mfhi %0" : "=r"(context->hi));
+    cvmx_debug_memcpy_align ((char *) context->regs, __cvmx_debug_save_regs_area, sizeof(context->regs));
+    context->lo = lo;
+    context->hi = hi;
     CVMX_MF_COP0(context->cop0.index, COP0_INDEX);
     CVMX_MF_COP0(context->cop0.entrylo[0], COP0_ENTRYLO0);
     CVMX_MF_COP0(context->cop0.entrylo[1], COP0_ENTRYLO1);
@@ -1209,10 +1369,9 @@ static void cvmx_debug_save_core_context(volatile cvmx_debug_core_context_t *con
 
 static void cvmx_debug_restore_core_context(volatile cvmx_debug_core_context_t *context)
 {
+    uint64_t hi, lo;
     int i;
-    memcpy(__cvmx_debug_save_regs_area, (char *) context->regs, sizeof(context->regs));
-    asm("mtlo %0" :: "r"(context->lo));
-    asm("mthi %0" :: "r"(context->hi));
+    cvmx_debug_memcpy_align (__cvmx_debug_save_regs_area, (char *) context->regs, sizeof(context->regs));
     /* We don't change the TLB so no need to restore it.  */
     cvmx_write_csr(CVMX_DEBUG_HW_DATA_BREAKPOINT_STATUS, context->hw_dbp.status);
     for (i = 0; i < 4; i++)
@@ -1245,6 +1404,10 @@ static void cvmx_debug_restore_core_context(volatile cvmx_debug_core_context_t *
     CVMX_MT_COP0(context->cop0.perfctrl[1], COP0_PERFCONTROL1);
     CVMX_MT_COP0(context->cop0.depc, COP0_DEPC);
     CVMX_MT_COP0(context->cop0.desave, COP0_DESAVE);
+    lo = context->lo;
+    hi = context->hi;
+    asm("mtlo %0" :: "r"(lo));
+    asm("mthi %0" :: "r"(hi));
 }
 
 static inline void cvmx_debug_print_cause(volatile cvmx_debug_core_context_t *context)
@@ -1273,7 +1436,7 @@ static inline void cvmx_debug_print_cause(volatile cvmx_debug_core_context_t *co
         cvmx_dprintf("Debug Single Step (DSS) exception\n");
 }
 
-void __cvmx_debug_handler_stage3 (void)
+void __cvmx_debug_handler_stage3 (uint64_t lo, uint64_t hi)
 {
     volatile cvmx_debug_core_context_t *context;
     int comms_changed = 0;
@@ -1293,7 +1456,7 @@ void __cvmx_debug_handler_stage3 (void)
     }
 
     context = cvmx_debug_core_context();
-    cvmx_debug_save_core_context(context);
+    cvmx_debug_save_core_context(context, hi, lo);
 
     {
         cvmx_debug_state_t state;
@@ -1370,7 +1533,7 @@ void __cvmx_debug_handler_stage3 (void)
 void cvmx_debug_trigger_exception(void)
 {
   /* Set CVMX_CIU_DINT to enter debug exception handler.  */
-  cvmx_write_csr (CVMX_CIU_DINT, 1 << cvmx_get_core_num ());
+  cvmx_write_csr (CVMX_CIU_DINT, 1u << cvmx_get_core_num ());
   /* Perform an immediate read after every write to an RSL register to force
      the write to complete. It doesn't matter what RSL read we do, so we
      choose CVMX_MIO_BOOT_BIST_STAT because it is fast and harmless */
@@ -1387,6 +1550,7 @@ void cvmx_debug_finish(void)
     unsigned coreid = cvmx_get_core_num();
     cvmx_debug_state_t state;
 
+    if (!cvmx_debug_globals) return;
     cvmx_debug_printf ("Debug _exit reached!, core %d, cvmx_debug_globals = %p\n", coreid, cvmx_debug_globals);
 
 #ifndef CVMX_BUILD_FOR_LINUX_KERNEL
@@ -1396,13 +1560,13 @@ void cvmx_debug_finish(void)
 
     cvmx_spinlock_lock(&cvmx_debug_globals->lock);
     state = cvmx_debug_get_state();
-    state.known_cores ^= (1 << coreid);
-    state.core_finished |= (1<<coreid);
+    state.known_cores ^= (1u << coreid);
+    state.core_finished |= (1u <<coreid);
     cvmx_debug_update_state(state);
 
     /* Tell the user the core has finished. */
     if (state.ever_been_in_debug)
-        cvmx_debug_putpacket("!Core %d finish.", coreid);
+        cvmx_debug_putcorepacket("finished.", coreid);
 
     /* Notify the debugger if all cores have completed the program */
     if ((cvmx_debug_core_mask () & state.core_finished) == cvmx_debug_core_mask ())
@@ -1417,9 +1581,9 @@ void cvmx_debug_finish(void)
            Since we already check that known_cores is non zero, this
            should always find a core */
         unsigned newcore;
-        for (newcore = 0; newcore < CVMX_DEBUG_MAX_CORES; newcore++)
+        for (newcore = 0; newcore < CVMX_MAX_CORES; newcore++)
         {
-           if (state.known_cores & (1<<newcore))
+           if (state.known_cores & (1u<<newcore))
            {
                cvmx_debug_printf("Routing uart interrupts to Core #%u.\n", newcore);
                cvmx_debug_set_focus_core(&state, newcore);
diff --git a/sys/contrib/octeon-sdk/cvmx-debug.h b/sys/contrib/octeon-sdk/cvmx-debug.h
index 21472e1..b914e2b 100644
--- a/sys/contrib/octeon-sdk/cvmx-debug.h
+++ b/sys/contrib/octeon-sdk/cvmx-debug.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -67,7 +67,7 @@ void cvmx_debug_init(void);
 void cvmx_debug_finish(void);
 void cvmx_debug_trigger_exception(void);
 
-#ifdef __OCTEON_NEWLIB__
+#ifdef CVMX_BUILD_FOR_TOOLCHAIN
 extern int __octeon_debug_booted;
 
 static inline int cvmx_debug_booted(void)
@@ -247,9 +247,6 @@ typedef struct
 
 typedef int cvmx_debug_state_t_should_fit_inside_a_cache_block[sizeof(cvmx_debug_state_t)+sizeof(cvmx_spinlock_t)+4*sizeof(uint64_t) > 128 ? -1 : 1];
 
-/* Total number of cores in Octeon. */
-#define CVMX_DEBUG_MAX_CORES 16
-
 typedef struct cvmx_debug_globals_s
 {
     uint64_t version; /* This is always the first element of this struct */
@@ -260,7 +257,7 @@ typedef struct cvmx_debug_globals_s
     uint32_t state[sizeof(cvmx_debug_state_t)/sizeof(uint32_t)];
     cvmx_spinlock_t lock;
 
-    volatile cvmx_debug_core_context_t contextes[CVMX_DEBUG_MAX_CORES];
+    volatile cvmx_debug_core_context_t contextes[CVMX_MAX_CORES];
 } cvmx_debug_globals_t;
 
 typedef union
diff --git a/sys/contrib/octeon-sdk/cvmx-dfa-defs.h b/sys/contrib/octeon-sdk/cvmx-dfa-defs.h
index 42ee0c8..1db1273 100644
--- a/sys/contrib/octeon-sdk/cvmx-dfa-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-dfa-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,14 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_DFA_TYPEDEFS_H__
-#define __CVMX_DFA_TYPEDEFS_H__
+#ifndef __CVMX_DFA_DEFS_H__
+#define __CVMX_DFA_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_DFA_BIST0 CVMX_DFA_BIST0_FUNC()
 static inline uint64_t CVMX_DFA_BIST0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_BIST0 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800370007F0ull);
 }
@@ -67,7 +67,7 @@ static inline uint64_t CVMX_DFA_BIST0_FUNC(void)
 #define CVMX_DFA_BIST1 CVMX_DFA_BIST1_FUNC()
 static inline uint64_t CVMX_DFA_BIST1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_BIST1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800370007F8ull);
 }
@@ -111,7 +111,7 @@ static inline uint64_t CVMX_DFA_CFG_FUNC(void)
 #define CVMX_DFA_CONFIG CVMX_DFA_CONFIG_FUNC()
 static inline uint64_t CVMX_DFA_CONFIG_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_CONFIG not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180037000000ull);
 }
@@ -122,7 +122,7 @@ static inline uint64_t CVMX_DFA_CONFIG_FUNC(void)
 #define CVMX_DFA_CONTROL CVMX_DFA_CONTROL_FUNC()
 static inline uint64_t CVMX_DFA_CONTROL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_CONTROL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180037000020ull);
 }
@@ -133,7 +133,7 @@ static inline uint64_t CVMX_DFA_CONTROL_FUNC(void)
 #define CVMX_DFA_DBELL CVMX_DFA_DBELL_FUNC()
 static inline uint64_t CVMX_DFA_DBELL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_DBELL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001370000000000ull);
 }
@@ -254,7 +254,7 @@ static inline uint64_t CVMX_DFA_DDR2_TMG_FUNC(void)
 #define CVMX_DFA_DEBUG0 CVMX_DFA_DEBUG0_FUNC()
 static inline uint64_t CVMX_DFA_DEBUG0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_DEBUG0 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180037000040ull);
 }
@@ -265,7 +265,7 @@ static inline uint64_t CVMX_DFA_DEBUG0_FUNC(void)
 #define CVMX_DFA_DEBUG1 CVMX_DFA_DEBUG1_FUNC()
 static inline uint64_t CVMX_DFA_DEBUG1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_DEBUG1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180037000048ull);
 }
@@ -276,7 +276,7 @@ static inline uint64_t CVMX_DFA_DEBUG1_FUNC(void)
 #define CVMX_DFA_DEBUG2 CVMX_DFA_DEBUG2_FUNC()
 static inline uint64_t CVMX_DFA_DEBUG2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_DEBUG2 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180037000050ull);
 }
@@ -287,7 +287,7 @@ static inline uint64_t CVMX_DFA_DEBUG2_FUNC(void)
 #define CVMX_DFA_DEBUG3 CVMX_DFA_DEBUG3_FUNC()
 static inline uint64_t CVMX_DFA_DEBUG3_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_DEBUG3 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180037000058ull);
 }
@@ -298,7 +298,7 @@ static inline uint64_t CVMX_DFA_DEBUG3_FUNC(void)
 #define CVMX_DFA_DIFCTL CVMX_DFA_DIFCTL_FUNC()
 static inline uint64_t CVMX_DFA_DIFCTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_DIFCTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001370600000000ull);
 }
@@ -309,7 +309,7 @@ static inline uint64_t CVMX_DFA_DIFCTL_FUNC(void)
 #define CVMX_DFA_DIFRDPTR CVMX_DFA_DIFRDPTR_FUNC()
 static inline uint64_t CVMX_DFA_DIFRDPTR_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_DIFRDPTR not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001370200000000ull);
 }
@@ -320,7 +320,7 @@ static inline uint64_t CVMX_DFA_DIFRDPTR_FUNC(void)
 #define CVMX_DFA_DTCFADR CVMX_DFA_DTCFADR_FUNC()
 static inline uint64_t CVMX_DFA_DTCFADR_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_DTCFADR not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180037000060ull);
 }
@@ -353,7 +353,7 @@ static inline uint64_t CVMX_DFA_ERR_FUNC(void)
 #define CVMX_DFA_ERROR CVMX_DFA_ERROR_FUNC()
 static inline uint64_t CVMX_DFA_ERROR_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_ERROR not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180037000028ull);
 }
@@ -364,7 +364,7 @@ static inline uint64_t CVMX_DFA_ERROR_FUNC(void)
 #define CVMX_DFA_INTMSK CVMX_DFA_INTMSK_FUNC()
 static inline uint64_t CVMX_DFA_INTMSK_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_INTMSK not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180037000030ull);
 }
@@ -430,7 +430,7 @@ static inline uint64_t CVMX_DFA_MEMFCR_FUNC(void)
 #define CVMX_DFA_MEMHIDAT CVMX_DFA_MEMHIDAT_FUNC()
 static inline uint64_t CVMX_DFA_MEMHIDAT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_MEMHIDAT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001370700000000ull);
 }
@@ -463,7 +463,7 @@ static inline uint64_t CVMX_DFA_NCBCTL_FUNC(void)
 #define CVMX_DFA_PFC0_CNT CVMX_DFA_PFC0_CNT_FUNC()
 static inline uint64_t CVMX_DFA_PFC0_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_PFC0_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180037000090ull);
 }
@@ -474,7 +474,7 @@ static inline uint64_t CVMX_DFA_PFC0_CNT_FUNC(void)
 #define CVMX_DFA_PFC0_CTL CVMX_DFA_PFC0_CTL_FUNC()
 static inline uint64_t CVMX_DFA_PFC0_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_PFC0_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180037000088ull);
 }
@@ -485,7 +485,7 @@ static inline uint64_t CVMX_DFA_PFC0_CTL_FUNC(void)
 #define CVMX_DFA_PFC1_CNT CVMX_DFA_PFC1_CNT_FUNC()
 static inline uint64_t CVMX_DFA_PFC1_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_PFC1_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800370000A0ull);
 }
@@ -496,7 +496,7 @@ static inline uint64_t CVMX_DFA_PFC1_CNT_FUNC(void)
 #define CVMX_DFA_PFC1_CTL CVMX_DFA_PFC1_CTL_FUNC()
 static inline uint64_t CVMX_DFA_PFC1_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_PFC1_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180037000098ull);
 }
@@ -507,7 +507,7 @@ static inline uint64_t CVMX_DFA_PFC1_CTL_FUNC(void)
 #define CVMX_DFA_PFC2_CNT CVMX_DFA_PFC2_CNT_FUNC()
 static inline uint64_t CVMX_DFA_PFC2_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_PFC2_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800370000B0ull);
 }
@@ -518,7 +518,7 @@ static inline uint64_t CVMX_DFA_PFC2_CNT_FUNC(void)
 #define CVMX_DFA_PFC2_CTL CVMX_DFA_PFC2_CTL_FUNC()
 static inline uint64_t CVMX_DFA_PFC2_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_PFC2_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800370000A8ull);
 }
@@ -529,7 +529,7 @@ static inline uint64_t CVMX_DFA_PFC2_CTL_FUNC(void)
 #define CVMX_DFA_PFC3_CNT CVMX_DFA_PFC3_CNT_FUNC()
 static inline uint64_t CVMX_DFA_PFC3_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_PFC3_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800370000C0ull);
 }
@@ -540,7 +540,7 @@ static inline uint64_t CVMX_DFA_PFC3_CNT_FUNC(void)
 #define CVMX_DFA_PFC3_CTL CVMX_DFA_PFC3_CTL_FUNC()
 static inline uint64_t CVMX_DFA_PFC3_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_PFC3_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800370000B8ull);
 }
@@ -551,7 +551,7 @@ static inline uint64_t CVMX_DFA_PFC3_CTL_FUNC(void)
 #define CVMX_DFA_PFC_GCTL CVMX_DFA_PFC_GCTL_FUNC()
 static inline uint64_t CVMX_DFA_PFC_GCTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_DFA_PFC_GCTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180037000080ull);
 }
@@ -621,12 +621,96 @@ static inline uint64_t CVMX_DFA_SBD_DBG3_FUNC(void)
  *
  * Description:
  */
-union cvmx_dfa_bist0
-{
+union cvmx_dfa_bist0 {
 	uint64_t u64;
-	struct cvmx_dfa_bist0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_bist0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_27_63               : 37;
+	uint64_t gfb                          : 3;  /**< Bist Results for GFB RAM(s) (per-cluster)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_22_23               : 2;
+	uint64_t stx2                         : 2;  /**< Bist Results for STX2 RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t stx1                         : 2;  /**< Bist Results for STX1 RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t stx                          : 2;  /**< Bist Results for STX0 RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_14_15               : 2;
+	uint64_t dtx2                         : 2;  /**< Bist Results for DTX2 RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t dtx1                         : 2;  /**< Bist Results for DTX1 RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t dtx                          : 2;  /**< Bist Results for DTX0 RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t rdf                          : 3;  /**< Bist Results for RWB RAM(s) (per-cluster)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t pdb                          : 3;  /**< Bist Results for PDB RAM(s) (per-cluster)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t pdb                          : 3;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t rdf                          : 3;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t dtx                          : 2;
+	uint64_t dtx1                         : 2;
+	uint64_t dtx2                         : 2;
+	uint64_t reserved_14_15               : 2;
+	uint64_t stx                          : 2;
+	uint64_t stx1                         : 2;
+	uint64_t stx2                         : 2;
+	uint64_t reserved_22_23               : 2;
+	uint64_t gfb                          : 3;
+	uint64_t reserved_27_63               : 37;
+#endif
+	} s;
+	struct cvmx_dfa_bist0_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_25_63               : 39;
+	uint64_t gfb                          : 1;  /**< Bist Results for GFB RAM(s) (per-cluster)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_18_23               : 6;
+	uint64_t stx                          : 2;  /**< Bist Results for STX0 RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_10_15               : 6;
+	uint64_t dtx                          : 2;  /**< Bist Results for DTX0 RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t rdf                          : 1;  /**< Bist Results for RWB RAM(s) (per-cluster)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t pdb                          : 1;  /**< Bist Results for PDB RAM(s) (per-cluster)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t pdb                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t rdf                          : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t dtx                          : 2;
+	uint64_t reserved_10_15               : 6;
+	uint64_t stx                          : 2;
+	uint64_t reserved_18_23               : 6;
+	uint64_t gfb                          : 1;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} cn61xx;
+	struct cvmx_dfa_bist0_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t mwb                          : 1;  /**< Bist Results for MWB RAM(s)
                                                          - 0: GOOD (or bist in progress/never run)
@@ -665,9 +749,67 @@ union cvmx_dfa_bist0
 	uint64_t mwb                          : 1;
 	uint64_t reserved_29_63               : 35;
 #endif
-	} s;
-	struct cvmx_dfa_bist0_s               cn63xx;
-	struct cvmx_dfa_bist0_s               cn63xxp1;
+	} cn63xx;
+	struct cvmx_dfa_bist0_cn63xx          cn63xxp1;
+	struct cvmx_dfa_bist0_cn63xx          cn66xx;
+	struct cvmx_dfa_bist0_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_30_63               : 34;
+	uint64_t mrp                          : 2;  /**< Bist Results for MRP RAM(s) (per-DLC)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_27_27               : 1;
+	uint64_t gfb                          : 3;  /**< Bist Results for GFB RAM(s) (per-cluster)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_22_23               : 2;
+	uint64_t stx2                         : 2;  /**< Bist Results for STX2 RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t stx1                         : 2;  /**< Bist Results for STX1 RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t stx                          : 2;  /**< Bist Results for STX0 RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_14_15               : 2;
+	uint64_t dtx2                         : 2;  /**< Bist Results for DTX2 RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t dtx1                         : 2;  /**< Bist Results for DTX1 RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t dtx                          : 2;  /**< Bist Results for DTX0 RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t rdf                          : 3;  /**< Bist Results for RWB RAM(s) (per-cluster)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t pdb                          : 3;  /**< Bist Results for PDB RAM(s) (per-cluster)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t pdb                          : 3;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t rdf                          : 3;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t dtx                          : 2;
+	uint64_t dtx1                         : 2;
+	uint64_t dtx2                         : 2;
+	uint64_t reserved_14_15               : 2;
+	uint64_t stx                          : 2;
+	uint64_t stx1                         : 2;
+	uint64_t stx2                         : 2;
+	uint64_t reserved_22_23               : 2;
+	uint64_t gfb                          : 3;
+	uint64_t reserved_27_27               : 1;
+	uint64_t mrp                          : 2;
+	uint64_t reserved_30_63               : 34;
+#endif
+	} cn68xx;
+	struct cvmx_dfa_bist0_cn68xx          cn68xxp1;
 };
 typedef union cvmx_dfa_bist0 cvmx_dfa_bist0_t;
 
@@ -678,12 +820,146 @@ typedef union cvmx_dfa_bist0 cvmx_dfa_bist0_t;
  *
  * Description:
  */
-union cvmx_dfa_bist1
-{
+union cvmx_dfa_bist1 {
 	uint64_t u64;
-	struct cvmx_dfa_bist1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_bist1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_21_63               : 43;
+	uint64_t dlc1ram                      : 1;  /**< DLC1 Bist Results
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t dlc0ram                      : 1;  /**< DLC0 Bist Results
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t dc2ram3                      : 1;  /**< Cluster#2 Bist Results for RAM3 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t dc2ram2                      : 1;  /**< Cluster#2 Bist Results for RAM2 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t dc2ram1                      : 1;  /**< Cluster#2 Bist Results for RAM1 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t dc1ram3                      : 1;  /**< Cluster#1 Bist Results for RAM3 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t dc1ram2                      : 1;  /**< Cluster#1 Bist Results for RAM2 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t dc1ram1                      : 1;  /**< Cluster#1 Bist Results for RAM1 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t ram3                         : 1;  /**< Cluster#0 Bist Results for RAM3 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t ram2                         : 1;  /**< Cluster#0 Bist Results for RAM2 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t ram1                         : 1;  /**< Cluster#0 Bist Results for RAM1 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t crq                          : 1;  /**< Bist Results for CRQ RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t gutv                         : 1;  /**< Bist Results for GUTV RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t gutp                         : 3;  /**< Bist Results for GUTP RAMs (per-cluster)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t ncd                          : 1;  /**< Bist Results for NCD RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t gif                          : 1;  /**< Bist Results for GIF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t gib                          : 1;  /**< Bist Results for GIB RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t gfu                          : 1;  /**< Bist Results for GFU RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t gfu                          : 1;
+	uint64_t gib                          : 1;
+	uint64_t gif                          : 1;
+	uint64_t ncd                          : 1;
+	uint64_t gutp                         : 3;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t gutv                         : 1;
+	uint64_t crq                          : 1;
+	uint64_t ram1                         : 1;
+	uint64_t ram2                         : 1;
+	uint64_t ram3                         : 1;
+	uint64_t dc1ram1                      : 1;
+	uint64_t dc1ram2                      : 1;
+	uint64_t dc1ram3                      : 1;
+	uint64_t dc2ram1                      : 1;
+	uint64_t dc2ram2                      : 1;
+	uint64_t dc2ram3                      : 1;
+	uint64_t dlc0ram                      : 1;
+	uint64_t dlc1ram                      : 1;
+	uint64_t reserved_21_63               : 43;
+#endif
+	} s;
+	struct cvmx_dfa_bist1_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t dlc0ram                      : 1;  /**< DLC0 Bist Results
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_13_18               : 6;
+	uint64_t ram3                         : 1;  /**< Cluster#0 Bist Results for RAM3 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t ram2                         : 1;  /**< Cluster#0 Bist Results for RAM2 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t ram1                         : 1;  /**< Cluster#0 Bist Results for RAM1 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t crq                          : 1;  /**< Bist Results for CRQ RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t gutv                         : 1;  /**< Bist Results for GUTV RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gutp                         : 1;  /**< Bist Results for GUTP RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t ncd                          : 1;  /**< Bist Results for NCD RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t gif                          : 1;  /**< Bist Results for GIF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t gib                          : 1;  /**< Bist Results for GIB RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t gfu                          : 1;  /**< Bist Results for GFU RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t gfu                          : 1;
+	uint64_t gib                          : 1;
+	uint64_t gif                          : 1;
+	uint64_t ncd                          : 1;
+	uint64_t gutp                         : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gutv                         : 1;
+	uint64_t crq                          : 1;
+	uint64_t ram1                         : 1;
+	uint64_t ram2                         : 1;
+	uint64_t ram3                         : 1;
+	uint64_t reserved_13_18               : 6;
+	uint64_t dlc0ram                      : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn61xx;
+	struct cvmx_dfa_bist1_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t ram3                         : 1;  /**< Bist Results for RAM3 RAM
                                                          - 0: GOOD (or bist in progress/never run)
@@ -730,9 +1006,11 @@ union cvmx_dfa_bist1
 	uint64_t ram3                         : 1;
 	uint64_t reserved_13_63               : 51;
 #endif
-	} s;
-	struct cvmx_dfa_bist1_s               cn63xx;
-	struct cvmx_dfa_bist1_s               cn63xxp1;
+	} cn63xx;
+	struct cvmx_dfa_bist1_cn63xx          cn63xxp1;
+	struct cvmx_dfa_bist1_cn63xx          cn66xx;
+	struct cvmx_dfa_bist1_s               cn68xx;
+	struct cvmx_dfa_bist1_s               cn68xxp1;
 };
 typedef union cvmx_dfa_bist1 cvmx_dfa_bist1_t;
 
@@ -743,12 +1021,10 @@ typedef union cvmx_dfa_bist1 cvmx_dfa_bist1_t;
  *
  * Description:
  */
-union cvmx_dfa_bst0
-{
+union cvmx_dfa_bst0 {
 	uint64_t u64;
-	struct cvmx_dfa_bst0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_bst0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t rdf                          : 16; /**< Bist Results for RDF[3:0] RAM(s)
                                                          - 0: GOOD (or bist in progress/never run)
@@ -765,9 +1041,8 @@ union cvmx_dfa_bst0
 	struct cvmx_dfa_bst0_s                cn31xx;
 	struct cvmx_dfa_bst0_s                cn38xx;
 	struct cvmx_dfa_bst0_s                cn38xxp2;
-	struct cvmx_dfa_bst0_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_bst0_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t rdf                          : 4;  /**< Bist Results for RDF[3:0] RAM(s)
                                                          - 0: GOOD (or bist in progress/never run)
@@ -794,12 +1069,10 @@ typedef union cvmx_dfa_bst0 cvmx_dfa_bst0_t;
  *
  * Description:
  */
-union cvmx_dfa_bst1
-{
+union cvmx_dfa_bst1 {
 	uint64_t u64;
-	struct cvmx_dfa_bst1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_bst1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_23_63               : 41;
 	uint64_t crq                          : 1;  /**< Bist Results for CRQ RAM
                                                          - 0: GOOD (or bist in progress/never run)
@@ -841,9 +1114,8 @@ union cvmx_dfa_bst1
 	uint64_t reserved_23_63               : 41;
 #endif
 	} s;
-	struct cvmx_dfa_bst1_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_bst1_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_23_63               : 41;
 	uint64_t crq                          : 1;  /**< Bist Results for CRQ RAM
                                                          - 0: GOOD (or bist in progress/never run)
@@ -873,9 +1145,8 @@ union cvmx_dfa_bst1
 	} cn31xx;
 	struct cvmx_dfa_bst1_s                cn38xx;
 	struct cvmx_dfa_bst1_s                cn38xxp2;
-	struct cvmx_dfa_bst1_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_bst1_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_23_63               : 41;
 	uint64_t crq                          : 1;  /**< Bist Results for CRQ RAM
                                                          - 0: GOOD (or bist in progress/never run)
@@ -928,12 +1199,10 @@ typedef union cvmx_dfa_bst1 cvmx_dfa_bst1_t;
  *
  * Description:
  */
-union cvmx_dfa_cfg
-{
+union cvmx_dfa_cfg {
 	uint64_t u64;
-	struct cvmx_dfa_cfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t nrpl_ena                     : 1;  /**< When set, allows the per-node replication feature to be
                                                          enabled.
@@ -1011,9 +1280,8 @@ union cvmx_dfa_cfg
 #endif
 	} s;
 	struct cvmx_dfa_cfg_s                 cn38xx;
-	struct cvmx_dfa_cfg_cn38xxp2
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_cfg_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t sarb                         : 1;  /**< DFA Source Arbiter Mode
                                                          Selects the arbitration mode used to select DFA
@@ -1042,12 +1310,113 @@ typedef union cvmx_dfa_cfg cvmx_dfa_cfg_t;
  *
  * Description:
  */
-union cvmx_dfa_config
-{
+union cvmx_dfa_config {
 	uint64_t u64;
-	struct cvmx_dfa_config_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_config_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_11_63               : 53;
+	uint64_t dlcclear_bist                : 1;  /**< When DLCSTART_BIST is written 0->1, if DLCCLEAR_BIST=1, all
+                                                         previous DLC BiST state is cleared.
+                                                         NOTES:
+                                                         1) DLCCLEAR_BIST must be written to 1 before DLCSTART_BIST
+                                                         is written to 1 udsing a separate CSR write.
+                                                         2) DLCCLEAR_BIST must not be changed after writing DLCSTART_BIST
+                                                         0->1 until the BIST operation completes. */
+	uint64_t dlcstart_bist                : 1;  /**< When software writes DLCSTART_BIST=0->1, a BiST is executed
+                                                         for the DLC sub-block RAMs which contains DCLK domain
+                                                         asynchronous RAMs.
+                                                         NOTES:
+                                                         1) This bit should only be written after DCLK has been enabled
+                                                         by software and is stable.
+                                                         (see LMC initialization routine for details on how to enable
+                                                         the DDR3 memory (DCLK) - which requires LMC PLL init, clock
+                                                         divider and proper DLL initialization sequence). */
+	uint64_t repl_ena                     : 1;  /**< Replication Mode Enable
+                                                         *** o63-P2 NEW ***
+                                                         When set, enables replication mode performance enhancement
+                                                         feature. This enables the DFA to communicate address
+                                                         replication information during memory references to the
+                                                         memory controller.
+                                                         For o63-P2: This is used by the memory controller
+                                                         to support graph data in multiple banks (or bank sets), so that
+                                                         the least full bank can be selected to minimize the effects of
+                                                         DDR3 bank conflicts (ie: tRC=row cycle time).
+                                                         For o68: This is used by the memory controller to support graph
+                                                         data in multiple ports (or port sets), so that the least full
+                                                         port can be selected to minimize latency effects.
+                                                         SWNOTE: Using this mode requires the DFA SW compiler and DFA
+                                                         driver to be aware of the address replication changes.
+                                                         This involves changes to the MLOAD/GWALK DFA instruction format
+                                                         (see: IWORD2.SREPL), as well as changes to node arc and metadata
+                                                         definitions which now support an additional REPL field.
+                                                         When clear, replication mode is disabled, and DFA will interpret
+                                                         DFA instructions and node-arc formats which DO NOT have
+                                                         address replication information. */
+	uint64_t clmskcrip                    : 4;  /**< Cluster Cripple Mask
+                                                         A one in each bit of the mask represents which DTE cluster to
+                                                         cripple.
+                                                         NOTE: o63 has only a single Cluster (therefore CLMSKCRIP[0]
+                                                         is the only bit used.
+                                                         o2 has 4 clusters, where all CLMSKCRIP mask bits are used.
+                                                         SWNOTE: The MIO_FUS___DFA_CLMASK_CRIPPLE[3:0] fuse bits will
+                                                         be forced into this register at reset. Any fuse bits that
+                                                         contain '1' will be disallowed during a write and will always
+                                                         be read as '1'. */
+	uint64_t cldtecrip                    : 3;  /**< Encoding which represents \#of DTEs to cripple for each
+                                                         cluster. Typically DTE_CLCRIP=0 which enables all DTEs
+                                                         within each cluster. However, when the DFA performance
+                                                         counters are used, SW may want to limit the \#of DTEs
+                                                         per cluster available, as there are only 4 parallel
+                                                         performance counters.
+                                                            DTE_CLCRIP | \#DTEs crippled(per cluster)
+                                                         ------------+-----------------------------
+                                                                0    |  0      DTE[15:0]:ON
+                                                                1    |  1/2    DTE[15:8]:OFF  /DTE[7:0]:ON
+                                                                2    |  1/4    DTE[15:12]:OFF /DTE[11:0]:ON
+                                                                3    |  3/4    DTE[15:4]:OFF  /DTE[3:0]:ON
+                                                                4    |  1/8    DTE[15:14]:OFF /DTE[13:0]:ON
+                                                                5    |  5/8    DTE[15:6]:OFF  /DTE[5:0]:ON
+                                                                6    |  3/8    DTE[15:10]:OFF /DTE[9:0]:ON
+                                                                7    |  7/8    DTE[15:2]:OFF  /DTE[1:0]:ON
+                                                         NOTE: Higher numbered DTEs are crippled first. For instance,
+                                                         on o63 (with 16 DTEs/cluster), if DTE_CLCRIP=1(1/2), then
+                                                         DTE#s [15:8] within the cluster are crippled and only
+                                                         DTE#s [7:0] are available.
+                                                         IMPNOTE: The encodings are done in such a way as to later
+                                                         be used with fuses (for future o2 revisions which will disable
+                                                         some \#of DTEs). Blowing a fuse has the effect that there will
+                                                         always be fewer DTEs available. [ie: we never want a customer
+                                                         to blow additional fuses to get more DTEs].
+                                                         SWNOTE: The MIO_FUS___DFA_NUMDTE_CRIPPLE[2:0] fuse bits will
+                                                         be forced into this register at reset. Any fuse bits that
+                                                         contain '1' will be disallowed during a write and will always
+                                                         be read as '1'. */
+	uint64_t dteclkdis                    : 1;  /**< DFA Clock Disable Source
+                                                         When SET, the DFA clocks for DTE(thread engine)
+                                                         operation are disabled (to conserve overall chip clocking
+                                                         power when the DFA function is not used).
+                                                         NOTE: When SET, SW MUST NEVER issue NCB-Direct CSR
+                                                         operations to the DFA (will result in NCB Bus Timeout
+                                                         errors).
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         SWNOTE: The MIO_FUS___DFA_DTE_DISABLE fuse bit will
+                                                         be forced into this register at reset. If the fuse bit
+                                                         contains '1', writes to DTECLKDIS are disallowed and
+                                                         will always be read as '1'. */
+#else
+	uint64_t dteclkdis                    : 1;
+	uint64_t cldtecrip                    : 3;
+	uint64_t clmskcrip                    : 4;
+	uint64_t repl_ena                     : 1;
+	uint64_t dlcstart_bist                : 1;
+	uint64_t dlcclear_bist                : 1;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} s;
+	struct cvmx_dfa_config_s              cn61xx;
+	struct cvmx_dfa_config_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t repl_ena                     : 1;  /**< Replication Mode Enable
                                                          *** o63-P2 NEW ***
@@ -1125,11 +1494,9 @@ union cvmx_dfa_config
 	uint64_t repl_ena                     : 1;
 	uint64_t reserved_9_63                : 55;
 #endif
-	} s;
-	struct cvmx_dfa_config_s              cn63xx;
-	struct cvmx_dfa_config_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	} cn63xx;
+	struct cvmx_dfa_config_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t clmskcrip                    : 4;  /**< Cluster Cripple Mask
                                                          A one in each bit of the mask represents which DTE cluster to
@@ -1190,6 +1557,9 @@ union cvmx_dfa_config
 	uint64_t reserved_8_63                : 56;
 #endif
 	} cn63xxp1;
+	struct cvmx_dfa_config_cn63xx         cn66xx;
+	struct cvmx_dfa_config_s              cn68xx;
+	struct cvmx_dfa_config_s              cn68xxp1;
 };
 typedef union cvmx_dfa_config cvmx_dfa_config_t;
 
@@ -1200,17 +1570,55 @@ typedef union cvmx_dfa_config cvmx_dfa_config_t;
  *
  * Description:
  */
-union cvmx_dfa_control
-{
+union cvmx_dfa_control {
 	uint64_t u64;
-	struct cvmx_dfa_control_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_12_63               : 52;
+	uint64_t sbdnum                       : 6;  /**< SBD Debug Entry#
+                                                         *FOR INTERNAL USE ONLY*
+                                                         DFA Scoreboard debug control
+                                                         Selects which one of 48 DFA Scoreboard entries is
+                                                         latched into the DFA_SBD_DBG[0-3] registers. */
+	uint64_t sbdlck                       : 1;  /**< DFA Scoreboard LOCK Strobe
+                                                         *FOR INTERNAL USE ONLY*
+                                                         DFA Scoreboard debug control
+                                                         When written with a '1', the DFA Scoreboard Debug
+                                                         registers (DFA_SBD_DBG[0-3]) are all locked down.
+                                                         This allows SW to lock down the contents of the entire
+                                                         SBD for a single instant in time. All subsequent reads
+                                                         of the DFA scoreboard registers will return the data
+                                                         from that instant in time. */
+	uint64_t reserved_3_4                 : 2;
+	uint64_t pmode                        : 1;  /**< NCB-NRP Arbiter Mode
+                                                         (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t qmode                        : 1;  /**< NCB-NRQ Arbiter Mode
+                                                         (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t imode                        : 1;  /**< NCB-Inbound Arbiter
+                                                         (0=FP [LP=NRQ,HP=NRP], 1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+#else
+	uint64_t imode                        : 1;
+	uint64_t qmode                        : 1;
+	uint64_t pmode                        : 1;
+	uint64_t reserved_3_4                 : 2;
+	uint64_t sbdlck                       : 1;
+	uint64_t sbdnum                       : 6;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_dfa_control_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t sbdnum                       : 4;  /**< SBD Debug Entry#
                                                          *FOR INTERNAL USE ONLY*
                                                          DFA Scoreboard debug control
-                                                         Selects which one of 8 DFA Scoreboard entries is
+                                                         Selects which one of 16 DFA Scoreboard entries is
                                                          latched into the DFA_SBD_DBG[0-3] registers. */
 	uint64_t sbdlck                       : 1;  /**< DFA Scoreboard LOCK Strobe
                                                          *FOR INTERNAL USE ONLY*
@@ -1243,9 +1651,12 @@ union cvmx_dfa_control
 	uint64_t sbdnum                       : 4;
 	uint64_t reserved_10_63               : 54;
 #endif
-	} s;
-	struct cvmx_dfa_control_s             cn63xx;
-	struct cvmx_dfa_control_s             cn63xxp1;
+	} cn61xx;
+	struct cvmx_dfa_control_cn61xx        cn63xx;
+	struct cvmx_dfa_control_cn61xx        cn63xxp1;
+	struct cvmx_dfa_control_cn61xx        cn66xx;
+	struct cvmx_dfa_control_s             cn68xx;
+	struct cvmx_dfa_control_s             cn68xxp1;
 };
 typedef union cvmx_dfa_control cvmx_dfa_control_t;
 
@@ -1261,12 +1672,10 @@ typedef union cvmx_dfa_control cvmx_dfa_control_t;
  *  NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DBELL register do not take effect.
  *  NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_DBELL register do not take effect.
  */
-union cvmx_dfa_dbell
-{
+union cvmx_dfa_dbell {
 	uint64_t u64;
-	struct cvmx_dfa_dbell_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t dbell                        : 20; /**< Represents the cumulative total of pending
                                                          DFA instructions which SW has previously written
@@ -1290,8 +1699,12 @@ union cvmx_dfa_dbell
 	struct cvmx_dfa_dbell_s               cn38xxp2;
 	struct cvmx_dfa_dbell_s               cn58xx;
 	struct cvmx_dfa_dbell_s               cn58xxp1;
+	struct cvmx_dfa_dbell_s               cn61xx;
 	struct cvmx_dfa_dbell_s               cn63xx;
 	struct cvmx_dfa_dbell_s               cn63xxp1;
+	struct cvmx_dfa_dbell_s               cn66xx;
+	struct cvmx_dfa_dbell_s               cn68xx;
+	struct cvmx_dfa_dbell_s               cn68xxp1;
 };
 typedef union cvmx_dfa_dbell cvmx_dfa_dbell_t;
 
@@ -1304,12 +1717,10 @@ typedef union cvmx_dfa_dbell cvmx_dfa_dbell_t;
  * Description: The following registers are used to compose the DFA's DDR2 address into ROW/COL/BNK
  *              etc.
  */
-union cvmx_dfa_ddr2_addr
-{
+union cvmx_dfa_ddr2_addr {
 	uint64_t u64;
-	struct cvmx_dfa_ddr2_addr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_ddr2_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t rdimm_ena                    : 1;  /**< If there is a need to insert a register chip on the
                                                          system (the equivalent of a registered DIMM) to
@@ -1385,12 +1796,10 @@ typedef union cvmx_dfa_ddr2_addr cvmx_dfa_ddr2_addr_t;
  *              \#Cycles of Data Transfer/\#Cycles since init or
  *              \#Cycles of Data Transfer/\#Cycles that memory controller is active
  */
-union cvmx_dfa_ddr2_bus
-{
+union cvmx_dfa_ddr2_bus {
 	uint64_t u64;
-	struct cvmx_dfa_ddr2_bus_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_ddr2_bus_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_47_63               : 17;
 	uint64_t bus_cnt                      : 47; /**< Counter counts the \# cycles of Data transfer */
 #else
@@ -1409,12 +1818,10 @@ typedef union cvmx_dfa_ddr2_bus cvmx_dfa_ddr2_bus_t;
  *
  * Description:
  */
-union cvmx_dfa_ddr2_cfg
-{
+union cvmx_dfa_ddr2_cfg {
 	uint64_t u64;
-	struct cvmx_dfa_ddr2_cfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_ddr2_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_41_63               : 23;
 	uint64_t trfc                         : 5;  /**< Establishes tRFC(from DDR2 data sheets) in \# of
                                                          4 fclk intervals.
@@ -1611,12 +2018,10 @@ typedef union cvmx_dfa_ddr2_cfg cvmx_dfa_ddr2_cfg_t;
  *
  * Description: The following are registers to program the DDR2 PLL and DLL
  */
-union cvmx_dfa_ddr2_comp
-{
+union cvmx_dfa_ddr2_comp {
 	uint64_t u64;
-	struct cvmx_dfa_ddr2_comp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_ddr2_comp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t dfa__pctl                    : 4;  /**< DFA DDR pctl from compensation circuit
                                                          Internal DBG only */
 	uint64_t dfa__nctl                    : 4;  /**< DFA DDR nctl from compensation circuit
@@ -1652,12 +2057,10 @@ typedef union cvmx_dfa_ddr2_comp cvmx_dfa_ddr2_comp_t;
  * For DDR-II please consult your device's data sheet for further details:
  *
  */
-union cvmx_dfa_ddr2_emrs
-{
+union cvmx_dfa_ddr2_emrs {
 	uint64_t u64;
-	struct cvmx_dfa_ddr2_emrs_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_ddr2_emrs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t emrs1_ocd                    : 15; /**< Memory Address[14:0] during "EMRS1 (OCD Calibration)"
                                                          step \#12a "EMRS OCD Default Command" A[9:7]=111
@@ -1716,12 +2119,10 @@ typedef union cvmx_dfa_ddr2_emrs cvmx_dfa_ddr2_emrs_t;
  *
  * Description: This FCLK cycle counter gets going after memory has been initialized
  */
-union cvmx_dfa_ddr2_fcnt
-{
+union cvmx_dfa_ddr2_fcnt {
 	uint64_t u64;
-	struct cvmx_dfa_ddr2_fcnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_ddr2_fcnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_47_63               : 17;
 	uint64_t fcyc_cnt                     : 47; /**< Counter counts FCLK cycles or \# cycles that the memory
                                                          controller has requests queued up depending on FCNT_MODE
@@ -1751,12 +2152,10 @@ typedef union cvmx_dfa_ddr2_fcnt cvmx_dfa_ddr2_fcnt_t;
  * For DDR-II please consult your device's data sheet for further details:
  *
  */
-union cvmx_dfa_ddr2_mrs
-{
+union cvmx_dfa_ddr2_mrs {
 	uint64_t u64;
-	struct cvmx_dfa_ddr2_mrs_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_ddr2_mrs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t mrs                          : 15; /**< Memory Address[14:0] during "MRS without resetting
                                                          DLL A[8]=0" step of HW initialization sequence.
@@ -1802,12 +2201,10 @@ typedef union cvmx_dfa_ddr2_mrs cvmx_dfa_ddr2_mrs_t;
  *
  * Description: The following are registers to tweak certain parameters to boost performance
  */
-union cvmx_dfa_ddr2_opt
-{
+union cvmx_dfa_ddr2_opt {
 	uint64_t u64;
-	struct cvmx_dfa_ddr2_opt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_ddr2_opt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t max_read_batch               : 5;  /**< Maximum number of consecutive read to service before
                                                          allowing write to interrupt. */
@@ -1831,12 +2228,10 @@ typedef union cvmx_dfa_ddr2_opt cvmx_dfa_ddr2_opt_t;
  *
  * Description: The following are registers to program the DDR2 PLL and DLL
  */
-union cvmx_dfa_ddr2_pll
-{
+union cvmx_dfa_ddr2_pll {
 	uint64_t u64;
-	struct cvmx_dfa_ddr2_pll_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_ddr2_pll_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t pll_setting                  : 17; /**< Internal Debug Use Only */
 	uint64_t reserved_32_46               : 15;
 	uint64_t setting90                    : 5;  /**< Contains the setting of DDR DLL; Internal DBG only */
@@ -1892,12 +2287,10 @@ typedef union cvmx_dfa_ddr2_pll cvmx_dfa_ddr2_pll_t;
  *
  * Description: The following are registers to program the DDR2 memory timing parameters.
  */
-union cvmx_dfa_ddr2_tmg
-{
+union cvmx_dfa_ddr2_tmg {
 	uint64_t u64;
-	struct cvmx_dfa_ddr2_tmg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_ddr2_tmg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_47_63               : 17;
 	uint64_t fcnt_mode                    : 1;  /**< If FCNT_MODE = 0, this counter counts the \# FCLK cycles
                                                          If FCNT_MODE = 1, this counter counts the \# cycles the
@@ -2070,12 +2463,10 @@ typedef union cvmx_dfa_ddr2_tmg cvmx_dfa_ddr2_tmg_t;
  * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an
  * instruction.
  */
-union cvmx_dfa_debug0
-{
+union cvmx_dfa_debug0 {
 	uint64_t u64;
-	struct cvmx_dfa_debug0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_debug0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t sbd0                         : 64; /**< DFA ScoreBoard \#0 Data
                                                          (DFA Scoreboard Debug)
                                                             [63:38]   (26) rptr[28:3]: Result Base Pointer (QW-aligned)
@@ -2104,8 +2495,12 @@ union cvmx_dfa_debug0
 	uint64_t sbd0                         : 64;
 #endif
 	} s;
+	struct cvmx_dfa_debug0_s              cn61xx;
 	struct cvmx_dfa_debug0_s              cn63xx;
 	struct cvmx_dfa_debug0_s              cn63xxp1;
+	struct cvmx_dfa_debug0_s              cn66xx;
+	struct cvmx_dfa_debug0_s              cn68xx;
+	struct cvmx_dfa_debug0_s              cn68xxp1;
 };
 typedef union cvmx_dfa_debug0 cvmx_dfa_debug0_t;
 
@@ -2121,12 +2516,10 @@ typedef union cvmx_dfa_debug0 cvmx_dfa_debug0_t;
  * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an
  * instruction.
  */
-union cvmx_dfa_debug1
-{
+union cvmx_dfa_debug1 {
 	uint64_t u64;
-	struct cvmx_dfa_debug1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_debug1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t sbd1                         : 64; /**< DFA ScoreBoard \#1 Data
                                                          DFA Scoreboard Debug Data
                                                             [63:56]   (8) UNUSED
@@ -2136,8 +2529,12 @@ union cvmx_dfa_debug1
 	uint64_t sbd1                         : 64;
 #endif
 	} s;
+	struct cvmx_dfa_debug1_s              cn61xx;
 	struct cvmx_dfa_debug1_s              cn63xx;
 	struct cvmx_dfa_debug1_s              cn63xxp1;
+	struct cvmx_dfa_debug1_s              cn66xx;
+	struct cvmx_dfa_debug1_s              cn68xx;
+	struct cvmx_dfa_debug1_s              cn68xxp1;
 };
 typedef union cvmx_dfa_debug1 cvmx_dfa_debug1_t;
 
@@ -2153,12 +2550,10 @@ typedef union cvmx_dfa_debug1 cvmx_dfa_debug1_t;
  * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an
  * instruction.
  */
-union cvmx_dfa_debug2
-{
+union cvmx_dfa_debug2 {
 	uint64_t u64;
-	struct cvmx_dfa_debug2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_debug2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t sbd2                         : 64; /**< DFA ScoreBoard \#2 Data
                                                          [63:45] (19) UNUSED
                                                          [44:42]  (3) Instruction Type
@@ -2168,8 +2563,12 @@ union cvmx_dfa_debug2
 	uint64_t sbd2                         : 64;
 #endif
 	} s;
+	struct cvmx_dfa_debug2_s              cn61xx;
 	struct cvmx_dfa_debug2_s              cn63xx;
 	struct cvmx_dfa_debug2_s              cn63xxp1;
+	struct cvmx_dfa_debug2_s              cn66xx;
+	struct cvmx_dfa_debug2_s              cn68xx;
+	struct cvmx_dfa_debug2_s              cn68xxp1;
 };
 typedef union cvmx_dfa_debug2 cvmx_dfa_debug2_t;
 
@@ -2185,12 +2584,10 @@ typedef union cvmx_dfa_debug2 cvmx_dfa_debug2_t;
  * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an
  * instruction.
  */
-union cvmx_dfa_debug3
-{
+union cvmx_dfa_debug3 {
 	uint64_t u64;
-	struct cvmx_dfa_debug3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_debug3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t sbd3                         : 64; /**< DFA ScoreBoard \#3 Data
                                                          [63:52] (11) rptr[39:29]: Result Base Pointer (QW-aligned)
                                                          [52:16] (37) glptr[39:3]: Gather List Pointer
@@ -2199,8 +2596,12 @@ union cvmx_dfa_debug3
 	uint64_t sbd3                         : 64;
 #endif
 	} s;
+	struct cvmx_dfa_debug3_s              cn61xx;
 	struct cvmx_dfa_debug3_s              cn63xx;
 	struct cvmx_dfa_debug3_s              cn63xxp1;
+	struct cvmx_dfa_debug3_s              cn66xx;
+	struct cvmx_dfa_debug3_s              cn68xx;
+	struct cvmx_dfa_debug3_s              cn68xxp1;
 };
 typedef union cvmx_dfa_debug3 cvmx_dfa_debug3_t;
 
@@ -2219,12 +2620,72 @@ typedef union cvmx_dfa_debug3 cvmx_dfa_debug3_t;
  *  NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DIFCTL register do not take effect.
  *  NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_DIFCTL register do not take effect.
  */
-union cvmx_dfa_difctl
-{
+union cvmx_dfa_difctl {
 	uint64_t u64;
-	struct cvmx_dfa_difctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_difctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_26_63               : 38;
+	uint64_t msegbase                     : 6;  /**< Memory Segmentation Base Address
+                                                         For debug purposes, backdoor accesses to the DFA
+                                                         memory are supported via NCB-Direct CSR accesses to
+                                                         the DFA Memory REGION(if addr[34:32]=5. However due
+                                                         to the existing NCB address decoding scheme, the
+                                                         address only offers a 4GB extent into the DFA memory
+                                                         REGION. Therefore, the MSEGBASE CSR field provides
+                                                         the additional upper memory address bits to allow access
+                                                         to the full extent of memory (128GB MAX).
+                                                         For DFA Memory REGION read NCB-Direct CSR accesses, the
+                                                         38bit L2/DRAM memory byte address is generated as follows:
+                                                           memaddr[37:0] = [DFA_DIFCTL[MSEGBASE],ncb_addr[31:3],3'b0]
+                                                         NOTE: See the upper 6bits of the memory address are sourced
+                                                         from DFA_DIFCTL[MSEGBASE] CSR field. The lower 4GB address
+                                                         offset is directly referenced using the NCB address bits during
+                                                         the reference itself.
+                                                         NOTE: The DFA_DIFCTL[MSEGBASE] is shared amongst all references.
+                                                         As such, if multiple PPs are accessing different segments in memory,
+                                                         their must be a SW mutual exclusive lock during each DFA Memory
+                                                         REGION access to avoid collisions between PPs using the same MSEGBASE
+                                                         CSR field.
+                                                         NOTE: See also DFA_ERROR[DFANXM] programmable interrupt which is
+                                                         flagged if SW tries to access non-existent memory space (address hole
+                                                         or upper unused region of 38bit address space). */
+	uint64_t dwbcnt                       : 8;  /**< Represents the \# of cache lines in the instruction
+                                                         buffer that may be dirty and should not be
+                                                         written-back to memory when the instruction
+                                                         chunk is returned to the Free Page list.
+                                                         NOTE: Typically SW will want to mark all DFA
+                                                         Instruction memory returned to the Free Page list
+                                                         as DWB (Don't WriteBack), therefore SW should
+                                                         seed this register as:
+                                                           DFA_DIFCTL[DWBCNT] = (DFA_DIFCTL[SIZE] + 4)/4 */
+	uint64_t pool                         : 3;  /**< Represents the 3bit buffer pool-id  used by DFA HW
+                                                         when the DFA instruction chunk is recycled back
+                                                         to the Free Page List maintained by the FPA HW
+                                                         (once the DFA instruction has been issued). */
+	uint64_t size                         : 9;  /**< Represents the \# of 32B instructions contained
+                                                         within each DFA instruction chunk. At Power-on,
+                                                         SW will seed the SIZE register with a fixed
+                                                         chunk-size. (Must be at least 3)
+                                                         DFA HW uses this field to determine the size
+                                                         of each DFA instruction chunk, in order to:
+                                                            a) determine when to read the next DFA
+                                                               instruction chunk pointer which is
+                                                               written by SW at the end of the current
+                                                               DFA instruction chunk (see DFA description
+                                                               of next chunk buffer Ptr for format).
+                                                            b) determine when a DFA instruction chunk
+                                                               can be returned to the Free Page List
+                                                               maintained by the FPA HW. */
+#else
+	uint64_t size                         : 9;
+	uint64_t pool                         : 3;
+	uint64_t dwbcnt                       : 8;
+	uint64_t msegbase                     : 6;
+	uint64_t reserved_26_63               : 38;
+#endif
+	} s;
+	struct cvmx_dfa_difctl_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t dwbcnt                       : 8;  /**< Represents the \# of cache lines in the instruction
                                                          buffer that may be dirty and should not be
@@ -2259,14 +2720,17 @@ union cvmx_dfa_difctl
 	uint64_t dwbcnt                       : 8;
 	uint64_t reserved_20_63               : 44;
 #endif
-	} s;
-	struct cvmx_dfa_difctl_s              cn31xx;
-	struct cvmx_dfa_difctl_s              cn38xx;
-	struct cvmx_dfa_difctl_s              cn38xxp2;
-	struct cvmx_dfa_difctl_s              cn58xx;
-	struct cvmx_dfa_difctl_s              cn58xxp1;
-	struct cvmx_dfa_difctl_s              cn63xx;
-	struct cvmx_dfa_difctl_s              cn63xxp1;
+	} cn31xx;
+	struct cvmx_dfa_difctl_cn31xx         cn38xx;
+	struct cvmx_dfa_difctl_cn31xx         cn38xxp2;
+	struct cvmx_dfa_difctl_cn31xx         cn58xx;
+	struct cvmx_dfa_difctl_cn31xx         cn58xxp1;
+	struct cvmx_dfa_difctl_s              cn61xx;
+	struct cvmx_dfa_difctl_cn31xx         cn63xx;
+	struct cvmx_dfa_difctl_cn31xx         cn63xxp1;
+	struct cvmx_dfa_difctl_cn31xx         cn66xx;
+	struct cvmx_dfa_difctl_s              cn68xx;
+	struct cvmx_dfa_difctl_s              cn68xxp1;
 };
 typedef union cvmx_dfa_difctl cvmx_dfa_difctl_t;
 
@@ -2282,12 +2746,10 @@ typedef union cvmx_dfa_difctl cvmx_dfa_difctl_t;
  *  NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DIFRDPTR register do not take effect.
  *  NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_DIFRDPTR register do not take effect.
  */
-union cvmx_dfa_difrdptr
-{
+union cvmx_dfa_difrdptr {
 	uint64_t u64;
-	struct cvmx_dfa_difrdptr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_difrdptr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t rdptr                        : 35; /**< Represents the 32B-aligned address of the current
                                                          instruction in the DFA Instruction FIFO in main
@@ -2311,9 +2773,8 @@ union cvmx_dfa_difrdptr
 	uint64_t reserved_40_63               : 24;
 #endif
 	} s;
-	struct cvmx_dfa_difrdptr_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_difrdptr_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t rdptr                        : 31; /**< Represents the 32B-aligned address of the current
                                                          instruction in the DFA Instruction FIFO in main
@@ -2341,8 +2802,12 @@ union cvmx_dfa_difrdptr
 	struct cvmx_dfa_difrdptr_cn31xx       cn38xxp2;
 	struct cvmx_dfa_difrdptr_cn31xx       cn58xx;
 	struct cvmx_dfa_difrdptr_cn31xx       cn58xxp1;
+	struct cvmx_dfa_difrdptr_s            cn61xx;
 	struct cvmx_dfa_difrdptr_s            cn63xx;
 	struct cvmx_dfa_difrdptr_s            cn63xxp1;
+	struct cvmx_dfa_difrdptr_s            cn66xx;
+	struct cvmx_dfa_difrdptr_s            cn68xx;
+	struct cvmx_dfa_difrdptr_s            cn68xxp1;
 };
 typedef union cvmx_dfa_difrdptr cvmx_dfa_difrdptr_t;
 
@@ -2355,28 +2820,34 @@ typedef union cvmx_dfa_difrdptr cvmx_dfa_difrdptr_t;
  * This register contains useful information to help in isolating a Node Cache RAM failure.
  * NOTE: The first detected PERR failure is captured in DFA_DTCFADR (locked down), until the
  * corresponding PERR Interrupt is cleared by writing one (W1C). (see: DFA_ERR[DC0PERR[2:0]]).
+ * NOTE: In the rare event that multiple parity errors are detected in the same cycle from multiple
+ * clusters, the FADR register will be locked down for the least signicant cluster \# (0->3).
  */
-union cvmx_dfa_dtcfadr
-{
+union cvmx_dfa_dtcfadr {
 	uint64_t u64;
-	struct cvmx_dfa_dtcfadr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_dtcfadr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_44_63               : 20;
 	uint64_t ram3fadr                     : 12; /**< DFA RAM3 Failing Address
                                                          If DFA_ERR[DC0PERR<2>]=1, this field indicates the
                                                          failing RAM3 Address. The failing address is locked
-                                                         down until the DC0PERR<2> W1C occurs. */
+                                                         down until the DC0PERR<2> W1C occurs.
+                                                         NOTE: If multiple DC0PERR<0>=1 errors are detected,
+                                                         then the lsb cluster error information is captured. */
 	uint64_t reserved_25_31               : 7;
 	uint64_t ram2fadr                     : 9;  /**< DFA RAM2 Failing Address
                                                          If DFA_ERR[DC0PERR<1>]=1, this field indicates the
                                                          failing RAM2 Address. The failing address is locked
-                                                         down until the DC0PERR<1> W1C occurs. */
+                                                         down until the DC0PERR<1> W1C occurs.
+                                                         NOTE: If multiple DC0PERR<0>=1 errors are detected,
+                                                         then the lsb cluster error information is captured. */
 	uint64_t reserved_14_15               : 2;
 	uint64_t ram1fadr                     : 14; /**< DFA RAM1 Failing Address
                                                          If DFA_ERR[DC0PERR<0>]=1, this field indicates the
                                                          failing RAM1 Address. The failing address is locked
-                                                         down until the DC0PERR<0> W1C occurs. */
+                                                         down until the DC0PERR<0> W1C occurs.
+                                                         NOTE: If multiple DC0PERR<0>=1 errors are detected,
+                                                         then the lsb cluster error information is captured. */
 #else
 	uint64_t ram1fadr                     : 14;
 	uint64_t reserved_14_15               : 2;
@@ -2386,8 +2857,12 @@ union cvmx_dfa_dtcfadr
 	uint64_t reserved_44_63               : 20;
 #endif
 	} s;
+	struct cvmx_dfa_dtcfadr_s             cn61xx;
 	struct cvmx_dfa_dtcfadr_s             cn63xx;
 	struct cvmx_dfa_dtcfadr_s             cn63xxp1;
+	struct cvmx_dfa_dtcfadr_s             cn66xx;
+	struct cvmx_dfa_dtcfadr_s             cn68xx;
+	struct cvmx_dfa_dtcfadr_s             cn68xxp1;
 };
 typedef union cvmx_dfa_dtcfadr cvmx_dfa_dtcfadr_t;
 
@@ -2400,12 +2875,10 @@ typedef union cvmx_dfa_dtcfadr cvmx_dfa_dtcfadr_t;
  *
  * Description:
  */
-union cvmx_dfa_eclkcfg
-{
+union cvmx_dfa_eclkcfg {
 	uint64_t u64;
-	struct cvmx_dfa_eclkcfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_eclkcfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t sbdnum                       : 3;  /**< SBD Debug Entry#
                                                          For internal use only. (DFA Scoreboard debug)
@@ -2503,12 +2976,10 @@ typedef union cvmx_dfa_eclkcfg cvmx_dfa_eclkcfg_t;
  *
  * Description:
  */
-union cvmx_dfa_err
-{
+union cvmx_dfa_err {
 	uint64_t u64;
-	struct cvmx_dfa_err_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_err_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_33_63               : 31;
 	uint64_t dblina                       : 1;  /**< Doorbell Overflow Interrupt Enable bit.
                                                          When set, doorbell overflow conditions are reported. */
@@ -2689,12 +3160,206 @@ typedef union cvmx_dfa_err cvmx_dfa_err_t;
  *
  * Description:
  */
-union cvmx_dfa_error
-{
+union cvmx_dfa_error {
 	uint64_t u64;
-	struct cvmx_dfa_error_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_error_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_19_63               : 45;
+	uint64_t replerr                      : 1;  /**< DFA Illegal Replication Factor Error
+                                                         For o68: DFA only supports 1x, 2x, and 4x port replication.
+                                                         Legal configurations for memory are to support 2 port or
+                                                         4 port configurations.
+                                                         The REPLERR interrupt will be set in the following illegal
+                                                         configuration cases:
+                                                             1) An 8x replication factor is detected for any memory reference.
+                                                             2) A 4x replication factor is detected for any memory reference
+                                                                when only 2 memory ports are enabled.
+                                                         NOTE: If REPLERR is set during a DFA Graph Walk operation,
+                                                         then the walk will prematurely terminate with RWORD0[REA]=ERR.
+                                                         If REPLERR is set during a NCB-Direct CSR read access to DFA
+                                                         Memory REGION, then the CSR read response data is UNPREDICTABLE. */
+	uint64_t dfanxm                       : 1;  /**< DFA Non-existent Memory Access
+                                                         For o68: DTEs (and backdoor CSR DFA Memory REGION reads)
+                                                         have access to the following 38bit L2/DRAM address space
+                                                         which maps to a 37bit physical DDR3 SDRAM address space.
+                                                         see:
+                                                         DR0: 0x0 0000 0000 0000 to 0x0 0000 0FFF FFFF
+                                                                 maps to lower 256MB of physical DDR3 SDRAM
+                                                         DR1: 0x0 0000 2000 0000 to 0x0 0020 0FFF FFFF
+                                                                 maps to upper 127.75GB of DDR3 SDRAM
+                                                                    L2/DRAM address space                     Physical DDR3 SDRAM Address space
+                                                                      (38bit address)                           (37bit address)
+                                                                       +-----------+ 0x0020.0FFF.FFFF
+
+                                                                      ===   DR1   ===                          +-----------+ 0x001F.FFFF.FFFF
+                                                          (128GB-256MB)|           |
+                                                                       |           |                     =>    |           |  (128GB-256MB)
+                                                                       +-----------+ 0x0000.1FFF.FFFF          |   DR1
+                                                               256MB   |   HOLE    |   (DO NOT USE)
+                                                                       +-----------+ 0x0000.0FFF.FFFF          +-----------+ 0x0000.0FFF.FFFF
+                                                               256MB   |    DR0    |                           |   DR0     |   (256MB)
+                                                                       +-----------+ 0x0000.0000.0000          +-----------+ 0x0000.0000.0000
+                                                         In the event the DFA generates a reference to the L2/DRAM
+                                                         address hole (0x0000.0FFF.FFFF - 0x0000.1FFF.FFFF) or to
+                                                         an address above 0x0020.0FFF.FFFF, the DFANXM programmable
+                                                         interrupt bit will be set.
+                                                         SWNOTE: Both the 1) SW DFA Graph compiler and the 2) SW NCB-Direct CSR
+                                                         accesses to DFA Memory REGION MUST avoid making references
+                                                         to these non-existent memory regions.
+                                                         NOTE: If DFANXM is set during a DFA Graph Walk operation,
+                                                         then the walk will prematurely terminate with RWORD0[REA]=ERR.
+                                                         If DFANXM is set during a NCB-Direct CSR read access to DFA
+                                                         Memory REGION, then the CSR read response data is forced to
+                                                         128'hBADE_FEED_DEAD_BEEF_FACE_CAFE_BEAD_C0DE. (NOTE: the QW
+                                                         being accessed, either the upper or lower QW will be returned). */
+	uint64_t cndrd                        : 1;  /**< If Any of the cluster's detected a Parity error on RAM1
+                                                         this additional bit further specifies that the
+                                                         RAM1 parity error was detected during a CND-RD
+                                                         (Cache Node Metadata Read).
+
+                                                         For CNDRD Parity Error, the previous CNA arc fetch
+                                                         information is written to RWORD1+ as follows:
+                                                            RWORD1+[NTYPE]=MNODE
+                                                            RWORD1+[NDNID]=cna.ndnid
+                                                            RWORD1+[NHMSK]=cna.hmsk
+                                                            RWORD1+[NNPTR]=cna.nnptr[13:0]
+                                                         NOTE: This bit is set if ANY node cluster's RAM1 accesses
+                                                         detect a CNDRD error. */
+	uint64_t reserved_15_15               : 1;
+	uint64_t dlc1_ovferr                  : 1;  /**< DLC1 Fifo Overflow Error Detected
+                                                         This condition should NEVER architecturally occur, and
+                                                         is here in case HW credit/debit scheme is not working. */
+	uint64_t dlc0_ovferr                  : 1;  /**< DLC0 Fifo Overflow Error Detected
+                                                         This condition should NEVER architecturally occur, and
+                                                         is here in case HW credit/debit scheme is not working. */
+	uint64_t reserved_10_12               : 3;
+	uint64_t dc2perr                      : 3;  /**< Cluster#2 RAM[3:1] Parity Error Detected
+                                                         See also DFA_DTCFADR register which contains the
+                                                         failing addresses for the internal node cache RAMs. */
+	uint64_t dc1perr                      : 3;  /**< Cluster#1 RAM[3:1] Parity Error Detected
+                                                         See also DFA_DTCFADR register which contains the
+                                                         failing addresses for the internal node cache RAMs. */
+	uint64_t dc0perr                      : 3;  /**< Cluster#0 RAM[3:1] Parity Error Detected
+                                                         See also DFA_DTCFADR register which contains the
+                                                         failing addresses for the internal node cache RAMs. */
+	uint64_t dblovf                       : 1;  /**< Doorbell Overflow detected - Status bit
+                                                         When set, the 20b accumulated doorbell register
+                                                         had overflowed (SW wrote too many doorbell requests).
+                                                         If the DBLINA had previously been enabled(set),
+                                                         an interrupt will be posted. Software can clear
+                                                         the interrupt by writing a 1 to this register bit.
+                                                         NOTE: Detection of a Doorbell Register overflow
+                                                         is a catastrophic error which may leave the DFA
+                                                         HW in an unrecoverable state. */
+#else
+	uint64_t dblovf                       : 1;
+	uint64_t dc0perr                      : 3;
+	uint64_t dc1perr                      : 3;
+	uint64_t dc2perr                      : 3;
+	uint64_t reserved_10_12               : 3;
+	uint64_t dlc0_ovferr                  : 1;
+	uint64_t dlc1_ovferr                  : 1;
+	uint64_t reserved_15_15               : 1;
+	uint64_t cndrd                        : 1;
+	uint64_t dfanxm                       : 1;
+	uint64_t replerr                      : 1;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} s;
+	struct cvmx_dfa_error_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_19_63               : 45;
+	uint64_t replerr                      : 1;  /**< DFA Illegal Replication Factor Error
+                                                         For o68: DFA only supports 1x, 2x, and 4x port replication.
+                                                         Legal configurations for memory are to support 2 port or
+                                                         4 port configurations.
+                                                         The REPLERR interrupt will be set in the following illegal
+                                                         configuration cases:
+                                                             1) An 8x replication factor is detected for any memory reference.
+                                                             2) A 4x replication factor is detected for any memory reference
+                                                                when only 2 memory ports are enabled.
+                                                         NOTE: If REPLERR is set during a DFA Graph Walk operation,
+                                                         then the walk will prematurely terminate with RWORD0[REA]=ERR.
+                                                         If REPLERR is set during a NCB-Direct CSR read access to DFA
+                                                         Memory REGION, then the CSR read response data is UNPREDICTABLE. */
+	uint64_t dfanxm                       : 1;  /**< DFA Non-existent Memory Access
+                                                         For o68/o61: DTEs (and backdoor CSR DFA Memory REGION reads)
+                                                         have access to the following 38bit L2/DRAM address space
+                                                         which maps to a 37bit physical DDR3 SDRAM address space.
+                                                         see:
+                                                         DR0: 0x0 0000 0000 0000 to 0x0 0000 0FFF FFFF
+                                                                 maps to lower 256MB of physical DDR3 SDRAM
+                                                         DR1: 0x0 0000 2000 0000 to 0x0 0020 0FFF FFFF
+                                                                 maps to upper 127.75GB of DDR3 SDRAM
+                                                                    L2/DRAM address space                     Physical DDR3 SDRAM Address space
+                                                                      (38bit address)                           (37bit address)
+                                                                       +-----------+ 0x0020.0FFF.FFFF
+                                                                       |
+                                                                      ===   DR1   ===                          +-----------+ 0x001F.FFFF.FFFF
+                                                          (128GB-256MB)|           |                           |
+                                                                       |           |                     =>    |           |  (128GB-256MB)
+                                                                       +-----------+ 0x0000.1FFF.FFFF          |   DR1
+                                                               256MB   |   HOLE    |   (DO NOT USE)            |
+                                                                       +-----------+ 0x0000.0FFF.FFFF          +-----------+ 0x0000.0FFF.FFFF
+                                                               256MB   |    DR0    |                           |   DR0     |   (256MB)
+                                                                       +-----------+ 0x0000.0000.0000          +-----------+ 0x0000.0000.0000
+                                                         In the event the DFA generates a reference to the L2/DRAM
+                                                         address hole (0x0000.0FFF.FFFF - 0x0000.1FFF.FFFF) or to
+                                                         an address above 0x0020.0FFF.FFFF, the DFANXM programmable
+                                                         interrupt bit will be set.
+                                                         SWNOTE: Both the 1) SW DFA Graph compiler and the 2) SW NCB-Direct CSR
+                                                         accesses to DFA Memory REGION MUST avoid making references
+                                                         to these non-existent memory regions.
+                                                         NOTE: If DFANXM is set during a DFA Graph Walk operation,
+                                                         then the walk will prematurely terminate with RWORD0[REA]=ERR.
+                                                         If DFANXM is set during a NCB-Direct CSR read access to DFA
+                                                         Memory REGION, then the CSR read response data is forced to
+                                                         128'hBADE_FEED_DEAD_BEEF_FACE_CAFE_BEAD_C0DE. (NOTE: the QW
+                                                         being accessed, either the upper or lower QW will be returned). */
+	uint64_t cndrd                        : 1;  /**< If any of the cluster's detected a Parity error on RAM1
+                                                         this additional bit further specifies that the
+                                                         RAM1 parity error was detected during a CND-RD
+                                                         (Cache Node Metadata Read).
+
+                                                         For CNDRD Parity Error, the previous CNA arc fetch
+                                                         information is written to RWORD1+ as follows:
+                                                            RWORD1+[NTYPE]=MNODE
+                                                            RWORD1+[NDNID]=cna.ndnid
+                                                            RWORD1+[NHMSK]=cna.hmsk
+                                                            RWORD1+[NNPTR]=cna.nnptr[13:0]
+                                                         NOTE: This bit is set if ANY node cluster's RAM1 accesses
+                                                         detect a CNDRD error. */
+	uint64_t reserved_14_15               : 2;
+	uint64_t dlc0_ovferr                  : 1;  /**< DLC0 Fifo Overflow Error Detected
+                                                         This condition should NEVER architecturally occur, and
+                                                         is here in case HW credit/debit scheme is not working. */
+	uint64_t reserved_4_12                : 9;
+	uint64_t dc0perr                      : 3;  /**< Cluster#0 RAM[3:1] Parity Error Detected
+                                                         See also DFA_DTCFADR register which contains the
+                                                         failing addresses for the internal node cache RAMs. */
+	uint64_t dblovf                       : 1;  /**< Doorbell Overflow detected - Status bit
+                                                         When set, the 20b accumulated doorbell register
+                                                         had overflowed (SW wrote too many doorbell requests).
+                                                         If the DBLINA had previously been enabled(set),
+                                                         an interrupt will be posted. Software can clear
+                                                         the interrupt by writing a 1 to this register bit.
+                                                         NOTE: Detection of a Doorbell Register overflow
+                                                         is a catastrophic error which may leave the DFA
+                                                         HW in an unrecoverable state. */
+#else
+	uint64_t dblovf                       : 1;
+	uint64_t dc0perr                      : 3;
+	uint64_t reserved_4_12                : 9;
+	uint64_t dlc0_ovferr                  : 1;
+	uint64_t reserved_14_15               : 2;
+	uint64_t cndrd                        : 1;
+	uint64_t dfanxm                       : 1;
+	uint64_t replerr                      : 1;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} cn61xx;
+	struct cvmx_dfa_error_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t cndrd                        : 1;  /**< If DC0PERR[0]=1 indicating a RAM1 Parity error,
                                                          this additional bit further specifies that the
@@ -2727,9 +3392,11 @@ union cvmx_dfa_error
 	uint64_t cndrd                        : 1;
 	uint64_t reserved_17_63               : 47;
 #endif
-	} s;
-	struct cvmx_dfa_error_s               cn63xx;
-	struct cvmx_dfa_error_s               cn63xxp1;
+	} cn63xx;
+	struct cvmx_dfa_error_cn63xx          cn63xxp1;
+	struct cvmx_dfa_error_cn63xx          cn66xx;
+	struct cvmx_dfa_error_s               cn68xx;
+	struct cvmx_dfa_error_s               cn68xxp1;
 };
 typedef union cvmx_dfa_error cvmx_dfa_error_t;
 
@@ -2740,12 +3407,60 @@ typedef union cvmx_dfa_error cvmx_dfa_error_t;
  *
  * Description:
  */
-union cvmx_dfa_intmsk
-{
+union cvmx_dfa_intmsk {
 	uint64_t u64;
-	struct cvmx_dfa_intmsk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_intmsk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_19_63               : 45;
+	uint64_t replerrena                   : 1;  /**< DFA Illegal Replication Factor Interrupt Enable */
+	uint64_t dfanxmena                    : 1;  /**< DFA Non-existent Memory Access Interrupt Enable */
+	uint64_t reserved_15_16               : 2;
+	uint64_t dlc1_ovfena                  : 1;  /**< DLC1 Fifo Overflow Error Interrupt Enable */
+	uint64_t dlc0_ovfena                  : 1;  /**< DLC0 Fifo Overflow Error Interrupt Enable */
+	uint64_t reserved_10_12               : 3;
+	uint64_t dc2pena                      : 3;  /**< RAM[3:1] Parity Error Enabled Node Cluster \#2 */
+	uint64_t dc1pena                      : 3;  /**< RAM[3:1] Parity Error Enabled Node Cluster \#1 */
+	uint64_t dc0pena                      : 3;  /**< RAM[3:1] Parity Error Enabled Node Cluster \#0 */
+	uint64_t dblina                       : 1;  /**< Doorbell Overflow Interrupt Enable bit.
+                                                         When set, doorbell overflow conditions are reported. */
+#else
+	uint64_t dblina                       : 1;
+	uint64_t dc0pena                      : 3;
+	uint64_t dc1pena                      : 3;
+	uint64_t dc2pena                      : 3;
+	uint64_t reserved_10_12               : 3;
+	uint64_t dlc0_ovfena                  : 1;
+	uint64_t dlc1_ovfena                  : 1;
+	uint64_t reserved_15_16               : 2;
+	uint64_t dfanxmena                    : 1;
+	uint64_t replerrena                   : 1;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} s;
+	struct cvmx_dfa_intmsk_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_19_63               : 45;
+	uint64_t replerrena                   : 1;  /**< DFA Illegal Replication Factor Interrupt Enable */
+	uint64_t dfanxmena                    : 1;  /**< DFA Non-existent Memory Access Interrupt Enable */
+	uint64_t reserved_14_16               : 3;
+	uint64_t dlc0_ovfena                  : 1;  /**< DLC0 Fifo Overflow Error Interrupt Enable */
+	uint64_t reserved_4_12                : 9;
+	uint64_t dc0pena                      : 3;  /**< RAM[3:1] Parity Error Enabled Node Cluster \#0 */
+	uint64_t dblina                       : 1;  /**< Doorbell Overflow Interrupt Enable bit.
+                                                         When set, doorbell overflow conditions are reported. */
+#else
+	uint64_t dblina                       : 1;
+	uint64_t dc0pena                      : 3;
+	uint64_t reserved_4_12                : 9;
+	uint64_t dlc0_ovfena                  : 1;
+	uint64_t reserved_14_16               : 3;
+	uint64_t dfanxmena                    : 1;
+	uint64_t replerrena                   : 1;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} cn61xx;
+	struct cvmx_dfa_intmsk_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t dc0pena                      : 3;  /**< RAM[3:1] Parity Error Enabled Node Cluster \#0 */
 	uint64_t dblina                       : 1;  /**< Doorbell Overflow Interrupt Enable bit.
@@ -2755,9 +3470,11 @@ union cvmx_dfa_intmsk
 	uint64_t dc0pena                      : 3;
 	uint64_t reserved_4_63                : 60;
 #endif
-	} s;
-	struct cvmx_dfa_intmsk_s              cn63xx;
-	struct cvmx_dfa_intmsk_s              cn63xxp1;
+	} cn63xx;
+	struct cvmx_dfa_intmsk_cn63xx         cn63xxp1;
+	struct cvmx_dfa_intmsk_cn63xx         cn66xx;
+	struct cvmx_dfa_intmsk_s              cn68xx;
+	struct cvmx_dfa_intmsk_s              cn68xxp1;
 };
 typedef union cvmx_dfa_intmsk cvmx_dfa_intmsk_t;
 
@@ -2768,12 +3485,10 @@ typedef union cvmx_dfa_intmsk cvmx_dfa_intmsk_t;
  *
  * Description:
  */
-union cvmx_dfa_memcfg0
-{
+union cvmx_dfa_memcfg0 {
 	uint64_t u64;
-	struct cvmx_dfa_memcfg0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_memcfg0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t rldqck90_rst                 : 1;  /**< RLDCK90 and RLDQK90 DLL SW Reset
                                                          When written with a '1' the RLDCK90 and RLDQK90 DLL are
@@ -3062,9 +3777,8 @@ union cvmx_dfa_memcfg0
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
-	struct cvmx_dfa_memcfg0_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_memcfg0_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t lpp_ena                      : 1;  /**< PP Linear Port Addressing Mode Enable
                                                          When enabled, PP-core LLM accesses to the lower-512MB
@@ -3349,9 +4063,8 @@ union cvmx_dfa_memcfg0
 	uint64_t reserved_28_63               : 36;
 #endif
 	} cn38xx;
-	struct cvmx_dfa_memcfg0_cn38xxp2
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_memcfg0_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_27_63               : 37;
 	uint64_t bunk_init                    : 2;  /**< Controls the CS_N[1:0] during a) a HW Initialization
                                                          sequence (triggered by DFA_MEMCFG0[INIT_Px]) or
@@ -3618,12 +4331,10 @@ typedef union cvmx_dfa_memcfg0 cvmx_dfa_memcfg0_t;
  *
  * Description:
  */
-union cvmx_dfa_memcfg1
-{
+union cvmx_dfa_memcfg1 {
 	uint64_t u64;
-	struct cvmx_dfa_memcfg1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_memcfg1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t ref_intlo                    : 9;  /**< Burst Refresh Interval[8:0] (\#dclks)
                                                          For finer refresh interval granularity control.
@@ -3798,12 +4509,10 @@ typedef union cvmx_dfa_memcfg1 cvmx_dfa_memcfg1_t;
  *
  * Description: Additional Memory Configuration CSRs to support FCRAM-II/II+ and Network DRAM-II
  */
-union cvmx_dfa_memcfg2
-{
+union cvmx_dfa_memcfg2 {
 	uint64_t u64;
-	struct cvmx_dfa_memcfg2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_memcfg2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t dteclkdis                    : 1;  /**< DFA DTE Clock Disable
                                                          When SET, the DFA clocks for DTE(thread engine)
@@ -3864,12 +4573,10 @@ typedef union cvmx_dfa_memcfg2 cvmx_dfa_memcfg2_t;
  * via the FSRC field.
  * NOTE: If DFA_MEMCFG2[DTECLKDIS]=1, the contents of this register are UNDEFINED.
  */
-union cvmx_dfa_memfadr
-{
+union cvmx_dfa_memfadr {
 	uint64_t u64;
-	struct cvmx_dfa_memfadr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_memfadr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t maddr                        : 24; /**< Memory Address */
 #else
@@ -3877,9 +4584,8 @@ union cvmx_dfa_memfadr
 	uint64_t reserved_24_63               : 40;
 #endif
 	} s;
-	struct cvmx_dfa_memfadr_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_memfadr_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t fdst                         : 9;  /**< Fill-Destination
                                                             FSRC[1:0]    | FDST[8:0]
@@ -3913,9 +4619,8 @@ union cvmx_dfa_memfadr
 	uint64_t reserved_40_63               : 24;
 #endif
 	} cn31xx;
-	struct cvmx_dfa_memfadr_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_memfadr_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_39_63               : 25;
 	uint64_t fdst                         : 9;  /**< Fill-Destination
                                                             FSRC[1:0]    | FDST[8:0]
@@ -3999,12 +4704,10 @@ typedef union cvmx_dfa_memfadr cvmx_dfa_memfadr_t;
  *    A[2:0]      ODTDQ         On Die Termination (DQ)
  *                                 [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED]
  */
-union cvmx_dfa_memfcr
-{
+union cvmx_dfa_memfcr {
 	uint64_t u64;
-	struct cvmx_dfa_memfcr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_memfcr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_47_63               : 17;
 	uint64_t emrs2                        : 15; /**< Memory Address[14:0] during EMRS2(for FCRAM-II+)
                                                          *** CN58XX UNSUPPORTED *** */
@@ -4057,26 +4760,32 @@ typedef union cvmx_dfa_memfcr cvmx_dfa_memfcr_t;
  *
  *  NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_MEMHIDAT register do not take effect.
  *  NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_MEMHIDAT register do not take effect.
+ *
+ * NOTE: PLEASE REMOVE DEFINITION FROM o68 HRM
  */
-union cvmx_dfa_memhidat
-{
+union cvmx_dfa_memhidat {
 	uint64_t u64;
-	struct cvmx_dfa_memhidat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_memhidat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t hidat                        : 64; /**< DFA Hi-QW of Write data during NCB-Direct DFM DDR3
                                                          Memory accesses.
                                                          All DFM DDR3 memory accesses are OW(128b) references,
                                                          and since NCB-Direct Mode writes only support QW(64b),
                                                          the Hi QW of data must be sourced from a CSR register.
                                                          NOTE: This single register is 'shared' for ALL DFM
-                                                         DDR3 Memory writes. */
+                                                         DDR3 Memory writes.
+                                                         For o68: This register is UNUSED. Treat as spare bits.
+                                                         NOTE: PLEASE REMOVE DEFINITION FROM o68 HRM */
 #else
 	uint64_t hidat                        : 64;
 #endif
 	} s;
+	struct cvmx_dfa_memhidat_s            cn61xx;
 	struct cvmx_dfa_memhidat_s            cn63xx;
 	struct cvmx_dfa_memhidat_s            cn63xxp1;
+	struct cvmx_dfa_memhidat_s            cn66xx;
+	struct cvmx_dfa_memhidat_s            cn68xx;
+	struct cvmx_dfa_memhidat_s            cn68xxp1;
 };
 typedef union cvmx_dfa_memhidat cvmx_dfa_memhidat_t;
 
@@ -4087,12 +4796,10 @@ typedef union cvmx_dfa_memhidat cvmx_dfa_memhidat_t;
  *
  * Description:
  */
-union cvmx_dfa_memrld
-{
+union cvmx_dfa_memrld {
 	uint64_t u64;
-	struct cvmx_dfa_memrld_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_memrld_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_23_63               : 41;
 	uint64_t mrsdat                       : 23; /**< This field represents the data driven onto the
                                                          A[22:0] address lines during MRS(Mode Register Set)
@@ -4143,12 +4850,10 @@ typedef union cvmx_dfa_memrld cvmx_dfa_memrld_t;
  *
  * Description:
  */
-union cvmx_dfa_ncbctl
-{
+union cvmx_dfa_ncbctl {
 	uint64_t u64;
-	struct cvmx_dfa_ncbctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_ncbctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t sbdnum                       : 5;  /**< SBD Debug Entry#
                                                          For internal use only. (DFA Scoreboard debug)
@@ -4193,9 +4898,8 @@ union cvmx_dfa_ncbctl
 	uint64_t reserved_11_63               : 53;
 #endif
 	} s;
-	struct cvmx_dfa_ncbctl_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_ncbctl_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t sbdnum                       : 4;  /**< SBD Debug Entry#
                                                          For internal use only. (DFA Scoreboard debug)
@@ -4253,12 +4957,10 @@ typedef union cvmx_dfa_ncbctl cvmx_dfa_ncbctl_t;
  * *FOR INTERNAL USE ONLY*
  * Description:
  */
-union cvmx_dfa_pfc0_cnt
-{
+union cvmx_dfa_pfc0_cnt {
 	uint64_t u64;
-	struct cvmx_dfa_pfc0_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_pfc0_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t pfcnt0                       : 64; /**< Performance Counter \#0
                                                          When DFA_PFC_GCTL[CNT0ENA]=1, the event selected
                                                          by DFA_PFC0_CTL[EVSEL] is counted.
@@ -4269,8 +4971,12 @@ union cvmx_dfa_pfc0_cnt
 	uint64_t pfcnt0                       : 64;
 #endif
 	} s;
+	struct cvmx_dfa_pfc0_cnt_s            cn61xx;
 	struct cvmx_dfa_pfc0_cnt_s            cn63xx;
 	struct cvmx_dfa_pfc0_cnt_s            cn63xxp1;
+	struct cvmx_dfa_pfc0_cnt_s            cn66xx;
+	struct cvmx_dfa_pfc0_cnt_s            cn68xx;
+	struct cvmx_dfa_pfc0_cnt_s            cn68xxp1;
 };
 typedef union cvmx_dfa_pfc0_cnt cvmx_dfa_pfc0_cnt_t;
 
@@ -4281,12 +4987,10 @@ typedef union cvmx_dfa_pfc0_cnt cvmx_dfa_pfc0_cnt_t;
  * *FOR INTERNAL USE ONLY*
  * Description:
  */
-union cvmx_dfa_pfc0_ctl
-{
+union cvmx_dfa_pfc0_ctl {
 	uint64_t u64;
-	struct cvmx_dfa_pfc0_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_pfc0_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t evsel                        : 6;  /**< Performance Counter#0 Event Selector
                                                          // Events [0-31] are based on PMODE(0:per cluster-DTE 1:per graph)
@@ -4347,8 +5051,12 @@ union cvmx_dfa_pfc0_ctl
 	uint64_t reserved_14_63               : 50;
 #endif
 	} s;
+	struct cvmx_dfa_pfc0_ctl_s            cn61xx;
 	struct cvmx_dfa_pfc0_ctl_s            cn63xx;
 	struct cvmx_dfa_pfc0_ctl_s            cn63xxp1;
+	struct cvmx_dfa_pfc0_ctl_s            cn66xx;
+	struct cvmx_dfa_pfc0_ctl_s            cn68xx;
+	struct cvmx_dfa_pfc0_ctl_s            cn68xxp1;
 };
 typedef union cvmx_dfa_pfc0_ctl cvmx_dfa_pfc0_ctl_t;
 
@@ -4359,12 +5067,10 @@ typedef union cvmx_dfa_pfc0_ctl cvmx_dfa_pfc0_ctl_t;
  * *FOR INTERNAL USE ONLY*
  * Description:
  */
-union cvmx_dfa_pfc1_cnt
-{
+union cvmx_dfa_pfc1_cnt {
 	uint64_t u64;
-	struct cvmx_dfa_pfc1_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_pfc1_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t pfcnt1                       : 64; /**< Performance Counter \#1
                                                          When DFA_PFC_GCTL[CNT1ENA]=1, the event selected
                                                          by DFA_PFC1_CTL[EVSEL] is counted.
@@ -4375,8 +5081,12 @@ union cvmx_dfa_pfc1_cnt
 	uint64_t pfcnt1                       : 64;
 #endif
 	} s;
+	struct cvmx_dfa_pfc1_cnt_s            cn61xx;
 	struct cvmx_dfa_pfc1_cnt_s            cn63xx;
 	struct cvmx_dfa_pfc1_cnt_s            cn63xxp1;
+	struct cvmx_dfa_pfc1_cnt_s            cn66xx;
+	struct cvmx_dfa_pfc1_cnt_s            cn68xx;
+	struct cvmx_dfa_pfc1_cnt_s            cn68xxp1;
 };
 typedef union cvmx_dfa_pfc1_cnt cvmx_dfa_pfc1_cnt_t;
 
@@ -4387,12 +5097,10 @@ typedef union cvmx_dfa_pfc1_cnt cvmx_dfa_pfc1_cnt_t;
  * *FOR INTERNAL USE ONLY*
  * Description:
  */
-union cvmx_dfa_pfc1_ctl
-{
+union cvmx_dfa_pfc1_ctl {
 	uint64_t u64;
-	struct cvmx_dfa_pfc1_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_pfc1_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t evsel                        : 6;  /**< Performance Counter#1 Event Selector
                                                          - 0:  \#Cycles
@@ -4445,8 +5153,12 @@ union cvmx_dfa_pfc1_ctl
 	uint64_t reserved_14_63               : 50;
 #endif
 	} s;
+	struct cvmx_dfa_pfc1_ctl_s            cn61xx;
 	struct cvmx_dfa_pfc1_ctl_s            cn63xx;
 	struct cvmx_dfa_pfc1_ctl_s            cn63xxp1;
+	struct cvmx_dfa_pfc1_ctl_s            cn66xx;
+	struct cvmx_dfa_pfc1_ctl_s            cn68xx;
+	struct cvmx_dfa_pfc1_ctl_s            cn68xxp1;
 };
 typedef union cvmx_dfa_pfc1_ctl cvmx_dfa_pfc1_ctl_t;
 
@@ -4457,12 +5169,10 @@ typedef union cvmx_dfa_pfc1_ctl cvmx_dfa_pfc1_ctl_t;
  * *FOR INTERNAL USE ONLY*
  * Description:
  */
-union cvmx_dfa_pfc2_cnt
-{
+union cvmx_dfa_pfc2_cnt {
 	uint64_t u64;
-	struct cvmx_dfa_pfc2_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_pfc2_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t pfcnt2                       : 64; /**< Performance Counter \#2
                                                          When DFA_PFC_GCTL[CNT2ENA]=1, the event selected
                                                          by DFA_PFC2_CTL[EVSEL] is counted.
@@ -4473,8 +5183,12 @@ union cvmx_dfa_pfc2_cnt
 	uint64_t pfcnt2                       : 64;
 #endif
 	} s;
+	struct cvmx_dfa_pfc2_cnt_s            cn61xx;
 	struct cvmx_dfa_pfc2_cnt_s            cn63xx;
 	struct cvmx_dfa_pfc2_cnt_s            cn63xxp1;
+	struct cvmx_dfa_pfc2_cnt_s            cn66xx;
+	struct cvmx_dfa_pfc2_cnt_s            cn68xx;
+	struct cvmx_dfa_pfc2_cnt_s            cn68xxp1;
 };
 typedef union cvmx_dfa_pfc2_cnt cvmx_dfa_pfc2_cnt_t;
 
@@ -4485,12 +5199,10 @@ typedef union cvmx_dfa_pfc2_cnt cvmx_dfa_pfc2_cnt_t;
  * *FOR INTERNAL USE ONLY*
  * Description:
  */
-union cvmx_dfa_pfc2_ctl
-{
+union cvmx_dfa_pfc2_ctl {
 	uint64_t u64;
-	struct cvmx_dfa_pfc2_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_pfc2_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t evsel                        : 6;  /**< Performance Counter#2 Event Selector
                                                          - 0:  \#Cycles
@@ -4543,8 +5255,12 @@ union cvmx_dfa_pfc2_ctl
 	uint64_t reserved_14_63               : 50;
 #endif
 	} s;
+	struct cvmx_dfa_pfc2_ctl_s            cn61xx;
 	struct cvmx_dfa_pfc2_ctl_s            cn63xx;
 	struct cvmx_dfa_pfc2_ctl_s            cn63xxp1;
+	struct cvmx_dfa_pfc2_ctl_s            cn66xx;
+	struct cvmx_dfa_pfc2_ctl_s            cn68xx;
+	struct cvmx_dfa_pfc2_ctl_s            cn68xxp1;
 };
 typedef union cvmx_dfa_pfc2_ctl cvmx_dfa_pfc2_ctl_t;
 
@@ -4555,12 +5271,10 @@ typedef union cvmx_dfa_pfc2_ctl cvmx_dfa_pfc2_ctl_t;
  * *FOR INTERNAL USE ONLY*
  * Description:
  */
-union cvmx_dfa_pfc3_cnt
-{
+union cvmx_dfa_pfc3_cnt {
 	uint64_t u64;
-	struct cvmx_dfa_pfc3_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_pfc3_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t pfcnt3                       : 64; /**< Performance Counter \#3
                                                          When DFA_PFC_GCTL[CNT3ENA]=1, the event selected
                                                          by DFA_PFC3_CTL[EVSEL] is counted.
@@ -4571,8 +5285,12 @@ union cvmx_dfa_pfc3_cnt
 	uint64_t pfcnt3                       : 64;
 #endif
 	} s;
+	struct cvmx_dfa_pfc3_cnt_s            cn61xx;
 	struct cvmx_dfa_pfc3_cnt_s            cn63xx;
 	struct cvmx_dfa_pfc3_cnt_s            cn63xxp1;
+	struct cvmx_dfa_pfc3_cnt_s            cn66xx;
+	struct cvmx_dfa_pfc3_cnt_s            cn68xx;
+	struct cvmx_dfa_pfc3_cnt_s            cn68xxp1;
 };
 typedef union cvmx_dfa_pfc3_cnt cvmx_dfa_pfc3_cnt_t;
 
@@ -4583,12 +5301,10 @@ typedef union cvmx_dfa_pfc3_cnt cvmx_dfa_pfc3_cnt_t;
  * *FOR INTERNAL USE ONLY*
  * Description:
  */
-union cvmx_dfa_pfc3_ctl
-{
+union cvmx_dfa_pfc3_ctl {
 	uint64_t u64;
-	struct cvmx_dfa_pfc3_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_pfc3_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t evsel                        : 6;  /**< Performance Counter#3 Event Selector
                                                          - 0:  \#Cycles
@@ -4641,8 +5357,12 @@ union cvmx_dfa_pfc3_ctl
 	uint64_t reserved_14_63               : 50;
 #endif
 	} s;
+	struct cvmx_dfa_pfc3_ctl_s            cn61xx;
 	struct cvmx_dfa_pfc3_ctl_s            cn63xx;
 	struct cvmx_dfa_pfc3_ctl_s            cn63xxp1;
+	struct cvmx_dfa_pfc3_ctl_s            cn66xx;
+	struct cvmx_dfa_pfc3_ctl_s            cn68xx;
+	struct cvmx_dfa_pfc3_ctl_s            cn68xxp1;
 };
 typedef union cvmx_dfa_pfc3_ctl cvmx_dfa_pfc3_ctl_t;
 
@@ -4653,12 +5373,10 @@ typedef union cvmx_dfa_pfc3_ctl cvmx_dfa_pfc3_ctl_t;
  * *FOR INTERNAL USE ONLY*
  * Description:
  */
-union cvmx_dfa_pfc_gctl
-{
+union cvmx_dfa_pfc_gctl {
 	uint64_t u64;
-	struct cvmx_dfa_pfc_gctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_pfc_gctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t vgid                         : 8;  /**< Virtual Graph Id#
                                                          When PMODE=1(per-graph selector), this field is used
@@ -4776,8 +5494,12 @@ union cvmx_dfa_pfc_gctl
 	uint64_t reserved_29_63               : 35;
 #endif
 	} s;
+	struct cvmx_dfa_pfc_gctl_s            cn61xx;
 	struct cvmx_dfa_pfc_gctl_s            cn63xx;
 	struct cvmx_dfa_pfc_gctl_s            cn63xxp1;
+	struct cvmx_dfa_pfc_gctl_s            cn66xx;
+	struct cvmx_dfa_pfc_gctl_s            cn68xx;
+	struct cvmx_dfa_pfc_gctl_s            cn68xxp1;
 };
 typedef union cvmx_dfa_pfc_gctl cvmx_dfa_pfc_gctl_t;
 
@@ -4787,12 +5509,10 @@ typedef union cvmx_dfa_pfc_gctl cvmx_dfa_pfc_gctl_t;
  * DFA_RODT_COMP_CTL = DFA RLD Compensation control (For read "on die termination")
  *
  */
-union cvmx_dfa_rodt_comp_ctl
-{
+union cvmx_dfa_rodt_comp_ctl {
 	uint64_t u64;
-	struct cvmx_dfa_rodt_comp_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_rodt_comp_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t enable                       : 1;  /**< Read On Die Termination Enable
                                                          (0=disable, 1=enable) */
@@ -4826,12 +5546,10 @@ typedef union cvmx_dfa_rodt_comp_ctl cvmx_dfa_rodt_comp_ctl_t;
  * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
  * instruction.
  */
-union cvmx_dfa_sbd_dbg0
-{
+union cvmx_dfa_sbd_dbg0 {
 	uint64_t u64;
-	struct cvmx_dfa_sbd_dbg0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_sbd_dbg0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t sbd0                         : 64; /**< DFA ScoreBoard \#0 Data
                                                          For internal use only! (DFA Scoreboard Debug)
                                                          [63:40] rptr[26:3]: Result Base Pointer
@@ -4887,12 +5605,10 @@ typedef union cvmx_dfa_sbd_dbg0 cvmx_dfa_sbd_dbg0_t;
  * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
  * instruction.
  */
-union cvmx_dfa_sbd_dbg1
-{
+union cvmx_dfa_sbd_dbg1 {
 	uint64_t u64;
-	struct cvmx_dfa_sbd_dbg1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_sbd_dbg1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t sbd1                         : 64; /**< DFA ScoreBoard \#1 Data
                                                          For internal use only! (DFA Scoreboard Debug)
                                                          [63:61] wqptr[35:33]: Work Queue Pointer
@@ -4923,12 +5639,10 @@ typedef union cvmx_dfa_sbd_dbg1 cvmx_dfa_sbd_dbg1_t;
  * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
  * instruction.
  */
-union cvmx_dfa_sbd_dbg2
-{
+union cvmx_dfa_sbd_dbg2 {
 	uint64_t u64;
-	struct cvmx_dfa_sbd_dbg2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_sbd_dbg2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t sbd2                         : 64; /**< DFA ScoreBoard \#2 Data
                                                          [63:49] wqptr[17:3]: Work Queue Pointer
                                                          [48:16] rwptr[35:3]: Result Write Pointer
@@ -4957,12 +5671,10 @@ typedef union cvmx_dfa_sbd_dbg2 cvmx_dfa_sbd_dbg2_t;
  * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
  * instruction.
  */
-union cvmx_dfa_sbd_dbg3
-{
+union cvmx_dfa_sbd_dbg3 {
 	uint64_t u64;
-	struct cvmx_dfa_sbd_dbg3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfa_sbd_dbg3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t sbd3                         : 64; /**< DFA ScoreBoard \#3 Data
                                                          [63:49] wqptr[32:18]: Work Queue Pointer
                                                          [48:16] glptr[35:3]: Gather List Pointer
diff --git a/sys/contrib/octeon-sdk/cvmx-dfa.c b/sys/contrib/octeon-sdk/cvmx-dfa.c
index 8b2847b..8953886 100644
--- a/sys/contrib/octeon-sdk/cvmx-dfa.c
+++ b/sys/contrib/octeon-sdk/cvmx-dfa.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Support library for the CN31XX, CN38XX, and CN58XX hardware DFA engine.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #include "executive-config.h"
 #ifdef CVMX_ENABLE_DFA_FUNCTIONS
diff --git a/sys/contrib/octeon-sdk/cvmx-dfa.h b/sys/contrib/octeon-sdk/cvmx-dfa.h
index d1a3b14..a2d1602 100644
--- a/sys/contrib/octeon-sdk/cvmx-dfa.h
+++ b/sys/contrib/octeon-sdk/cvmx-dfa.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Interface to the CN31XX, CN38XX, and CN58XX hardware DFA engine.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_DFA_H__
@@ -486,7 +486,7 @@ typedef union
     uint64_t u64;
     struct {
 #define CVMX_DFA_STATE_TICKET_BIT_POS 16
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
 	// NOTE:  must clear LSB of base_address_div16 due to ticket overflow
 	uint32_t		base_address_div16;  /**< Current DFA instruction queue chunck base address/16 (clear LSB). */
 	uint8_t			ticket_loops;	     /**< bits [15:8] of total number of tickets requested. */
@@ -503,7 +503,7 @@ typedef union
 #endif
     } s;
     struct {	// a bitfield version of the same thing to extract base address while clearing carry.
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t		base_address_div32	: 31;	/**< Current DFA instruction queue chunck base address/32. */
 	uint64_t		carry			: 1;	/**< Carry out from total_tickets. */
 	uint64_t		total_tickets		: 16;	/**< Total tickets. */
diff --git a/sys/contrib/octeon-sdk/cvmx-dfm-defs.h b/sys/contrib/octeon-sdk/cvmx-dfm-defs.h
index bb324ad..6401906 100644
--- a/sys/contrib/octeon-sdk/cvmx-dfm-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-dfm-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,14 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_DFM_TYPEDEFS_H__
-#define __CVMX_DFM_TYPEDEFS_H__
+#ifndef __CVMX_DFM_DEFS_H__
+#define __CVMX_DFM_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_DFM_CHAR_CTL CVMX_DFM_CHAR_CTL_FUNC()
 static inline uint64_t CVMX_DFM_CHAR_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_CHAR_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000220ull);
 }
@@ -67,7 +67,7 @@ static inline uint64_t CVMX_DFM_CHAR_CTL_FUNC(void)
 #define CVMX_DFM_CHAR_MASK0 CVMX_DFM_CHAR_MASK0_FUNC()
 static inline uint64_t CVMX_DFM_CHAR_MASK0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_CHAR_MASK0 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000228ull);
 }
@@ -78,7 +78,7 @@ static inline uint64_t CVMX_DFM_CHAR_MASK0_FUNC(void)
 #define CVMX_DFM_CHAR_MASK2 CVMX_DFM_CHAR_MASK2_FUNC()
 static inline uint64_t CVMX_DFM_CHAR_MASK2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_CHAR_MASK2 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000238ull);
 }
@@ -89,7 +89,7 @@ static inline uint64_t CVMX_DFM_CHAR_MASK2_FUNC(void)
 #define CVMX_DFM_CHAR_MASK4 CVMX_DFM_CHAR_MASK4_FUNC()
 static inline uint64_t CVMX_DFM_CHAR_MASK4_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_CHAR_MASK4 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000318ull);
 }
@@ -100,7 +100,7 @@ static inline uint64_t CVMX_DFM_CHAR_MASK4_FUNC(void)
 #define CVMX_DFM_COMP_CTL2 CVMX_DFM_COMP_CTL2_FUNC()
 static inline uint64_t CVMX_DFM_COMP_CTL2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_COMP_CTL2 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D40001B8ull);
 }
@@ -111,7 +111,7 @@ static inline uint64_t CVMX_DFM_COMP_CTL2_FUNC(void)
 #define CVMX_DFM_CONFIG CVMX_DFM_CONFIG_FUNC()
 static inline uint64_t CVMX_DFM_CONFIG_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_CONFIG not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000188ull);
 }
@@ -122,7 +122,7 @@ static inline uint64_t CVMX_DFM_CONFIG_FUNC(void)
 #define CVMX_DFM_CONTROL CVMX_DFM_CONTROL_FUNC()
 static inline uint64_t CVMX_DFM_CONTROL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_CONTROL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000190ull);
 }
@@ -133,7 +133,7 @@ static inline uint64_t CVMX_DFM_CONTROL_FUNC(void)
 #define CVMX_DFM_DLL_CTL2 CVMX_DFM_DLL_CTL2_FUNC()
 static inline uint64_t CVMX_DFM_DLL_CTL2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_DLL_CTL2 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D40001C8ull);
 }
@@ -144,7 +144,7 @@ static inline uint64_t CVMX_DFM_DLL_CTL2_FUNC(void)
 #define CVMX_DFM_DLL_CTL3 CVMX_DFM_DLL_CTL3_FUNC()
 static inline uint64_t CVMX_DFM_DLL_CTL3_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_DLL_CTL3 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000218ull);
 }
@@ -155,7 +155,7 @@ static inline uint64_t CVMX_DFM_DLL_CTL3_FUNC(void)
 #define CVMX_DFM_FCLK_CNT CVMX_DFM_FCLK_CNT_FUNC()
 static inline uint64_t CVMX_DFM_FCLK_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_FCLK_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D40001E0ull);
 }
@@ -166,7 +166,7 @@ static inline uint64_t CVMX_DFM_FCLK_CNT_FUNC(void)
 #define CVMX_DFM_FNT_BIST CVMX_DFM_FNT_BIST_FUNC()
 static inline uint64_t CVMX_DFM_FNT_BIST_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_FNT_BIST not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D40007F8ull);
 }
@@ -177,7 +177,7 @@ static inline uint64_t CVMX_DFM_FNT_BIST_FUNC(void)
 #define CVMX_DFM_FNT_CTL CVMX_DFM_FNT_CTL_FUNC()
 static inline uint64_t CVMX_DFM_FNT_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_FNT_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000400ull);
 }
@@ -188,7 +188,7 @@ static inline uint64_t CVMX_DFM_FNT_CTL_FUNC(void)
 #define CVMX_DFM_FNT_IENA CVMX_DFM_FNT_IENA_FUNC()
 static inline uint64_t CVMX_DFM_FNT_IENA_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_FNT_IENA not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000410ull);
 }
@@ -199,7 +199,7 @@ static inline uint64_t CVMX_DFM_FNT_IENA_FUNC(void)
 #define CVMX_DFM_FNT_SCLK CVMX_DFM_FNT_SCLK_FUNC()
 static inline uint64_t CVMX_DFM_FNT_SCLK_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_FNT_SCLK not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000418ull);
 }
@@ -210,7 +210,7 @@ static inline uint64_t CVMX_DFM_FNT_SCLK_FUNC(void)
 #define CVMX_DFM_FNT_STAT CVMX_DFM_FNT_STAT_FUNC()
 static inline uint64_t CVMX_DFM_FNT_STAT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_FNT_STAT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000408ull);
 }
@@ -221,7 +221,7 @@ static inline uint64_t CVMX_DFM_FNT_STAT_FUNC(void)
 #define CVMX_DFM_IFB_CNT CVMX_DFM_IFB_CNT_FUNC()
 static inline uint64_t CVMX_DFM_IFB_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_IFB_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D40001D0ull);
 }
@@ -232,7 +232,7 @@ static inline uint64_t CVMX_DFM_IFB_CNT_FUNC(void)
 #define CVMX_DFM_MODEREG_PARAMS0 CVMX_DFM_MODEREG_PARAMS0_FUNC()
 static inline uint64_t CVMX_DFM_MODEREG_PARAMS0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_MODEREG_PARAMS0 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D40001A8ull);
 }
@@ -243,7 +243,7 @@ static inline uint64_t CVMX_DFM_MODEREG_PARAMS0_FUNC(void)
 #define CVMX_DFM_MODEREG_PARAMS1 CVMX_DFM_MODEREG_PARAMS1_FUNC()
 static inline uint64_t CVMX_DFM_MODEREG_PARAMS1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_MODEREG_PARAMS1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000260ull);
 }
@@ -254,7 +254,7 @@ static inline uint64_t CVMX_DFM_MODEREG_PARAMS1_FUNC(void)
 #define CVMX_DFM_OPS_CNT CVMX_DFM_OPS_CNT_FUNC()
 static inline uint64_t CVMX_DFM_OPS_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_OPS_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D40001D8ull);
 }
@@ -265,7 +265,7 @@ static inline uint64_t CVMX_DFM_OPS_CNT_FUNC(void)
 #define CVMX_DFM_PHY_CTL CVMX_DFM_PHY_CTL_FUNC()
 static inline uint64_t CVMX_DFM_PHY_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_PHY_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000210ull);
 }
@@ -276,7 +276,7 @@ static inline uint64_t CVMX_DFM_PHY_CTL_FUNC(void)
 #define CVMX_DFM_RESET_CTL CVMX_DFM_RESET_CTL_FUNC()
 static inline uint64_t CVMX_DFM_RESET_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_RESET_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000180ull);
 }
@@ -287,7 +287,7 @@ static inline uint64_t CVMX_DFM_RESET_CTL_FUNC(void)
 #define CVMX_DFM_RLEVEL_CTL CVMX_DFM_RLEVEL_CTL_FUNC()
 static inline uint64_t CVMX_DFM_RLEVEL_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_RLEVEL_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D40002A0ull);
 }
@@ -298,7 +298,7 @@ static inline uint64_t CVMX_DFM_RLEVEL_CTL_FUNC(void)
 #define CVMX_DFM_RLEVEL_DBG CVMX_DFM_RLEVEL_DBG_FUNC()
 static inline uint64_t CVMX_DFM_RLEVEL_DBG_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_RLEVEL_DBG not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D40002A8ull);
 }
@@ -309,7 +309,8 @@ static inline uint64_t CVMX_DFM_RLEVEL_DBG_FUNC(void)
 static inline uint64_t CVMX_DFM_RLEVEL_RANKX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_DFM_RLEVEL_RANKX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800D4000280ull) + ((offset) & 1) * 8;
 }
@@ -320,7 +321,7 @@ static inline uint64_t CVMX_DFM_RLEVEL_RANKX(unsigned long offset)
 #define CVMX_DFM_RODT_MASK CVMX_DFM_RODT_MASK_FUNC()
 static inline uint64_t CVMX_DFM_RODT_MASK_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_RODT_MASK not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000268ull);
 }
@@ -331,7 +332,7 @@ static inline uint64_t CVMX_DFM_RODT_MASK_FUNC(void)
 #define CVMX_DFM_SLOT_CTL0 CVMX_DFM_SLOT_CTL0_FUNC()
 static inline uint64_t CVMX_DFM_SLOT_CTL0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_SLOT_CTL0 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D40001F8ull);
 }
@@ -342,7 +343,7 @@ static inline uint64_t CVMX_DFM_SLOT_CTL0_FUNC(void)
 #define CVMX_DFM_SLOT_CTL1 CVMX_DFM_SLOT_CTL1_FUNC()
 static inline uint64_t CVMX_DFM_SLOT_CTL1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_SLOT_CTL1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000200ull);
 }
@@ -353,7 +354,7 @@ static inline uint64_t CVMX_DFM_SLOT_CTL1_FUNC(void)
 #define CVMX_DFM_TIMING_PARAMS0 CVMX_DFM_TIMING_PARAMS0_FUNC()
 static inline uint64_t CVMX_DFM_TIMING_PARAMS0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_TIMING_PARAMS0 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000198ull);
 }
@@ -364,7 +365,7 @@ static inline uint64_t CVMX_DFM_TIMING_PARAMS0_FUNC(void)
 #define CVMX_DFM_TIMING_PARAMS1 CVMX_DFM_TIMING_PARAMS1_FUNC()
 static inline uint64_t CVMX_DFM_TIMING_PARAMS1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_TIMING_PARAMS1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D40001A0ull);
 }
@@ -375,7 +376,7 @@ static inline uint64_t CVMX_DFM_TIMING_PARAMS1_FUNC(void)
 #define CVMX_DFM_WLEVEL_CTL CVMX_DFM_WLEVEL_CTL_FUNC()
 static inline uint64_t CVMX_DFM_WLEVEL_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_WLEVEL_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000300ull);
 }
@@ -386,7 +387,7 @@ static inline uint64_t CVMX_DFM_WLEVEL_CTL_FUNC(void)
 #define CVMX_DFM_WLEVEL_DBG CVMX_DFM_WLEVEL_DBG_FUNC()
 static inline uint64_t CVMX_DFM_WLEVEL_DBG_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_WLEVEL_DBG not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D4000308ull);
 }
@@ -397,7 +398,8 @@ static inline uint64_t CVMX_DFM_WLEVEL_DBG_FUNC(void)
 static inline uint64_t CVMX_DFM_WLEVEL_RANKX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_DFM_WLEVEL_RANKX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800D40002B0ull) + ((offset) & 1) * 8;
 }
@@ -408,7 +410,7 @@ static inline uint64_t CVMX_DFM_WLEVEL_RANKX(unsigned long offset)
 #define CVMX_DFM_WODT_MASK CVMX_DFM_WODT_MASK_FUNC()
 static inline uint64_t CVMX_DFM_WODT_MASK_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
 		cvmx_warn("CVMX_DFM_WODT_MASK not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800D40001B0ull);
 }
@@ -421,13 +423,36 @@ static inline uint64_t CVMX_DFM_WODT_MASK_FUNC(void)
  *
  * DFM_CHAR_CTL = DFM Characterization Control
  * This register is an assortment of various control fields needed to charecterize the DDR3 interface
+ *
+ * Notes:
+ * DR bit applies on the DQ port
+ *
  */
-union cvmx_dfm_char_ctl
-{
+union cvmx_dfm_char_ctl {
 	uint64_t u64;
-	struct cvmx_dfm_char_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_char_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_44_63               : 20;
+	uint64_t dr                           : 1;  /**< Pattern at Data Rate (not Clock Rate) */
+	uint64_t skew_on                      : 1;  /**< Skew adjacent bits */
+	uint64_t en                           : 1;  /**< Enable characterization */
+	uint64_t sel                          : 1;  /**< Pattern select
+                                                         0 = PRBS
+                                                         1 = Programmable pattern */
+	uint64_t prog                         : 8;  /**< Programmable pattern */
+	uint64_t prbs                         : 32; /**< PRBS Polynomial */
+#else
+	uint64_t prbs                         : 32;
+	uint64_t prog                         : 8;
+	uint64_t sel                          : 1;
+	uint64_t en                           : 1;
+	uint64_t skew_on                      : 1;
+	uint64_t dr                           : 1;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_dfm_char_ctl_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_42_63               : 22;
 	uint64_t en                           : 1;  /**< Enable characterization */
 	uint64_t sel                          : 1;  /**< Pattern select
@@ -442,9 +467,9 @@ union cvmx_dfm_char_ctl
 	uint64_t en                           : 1;
 	uint64_t reserved_42_63               : 22;
 #endif
-	} s;
-	struct cvmx_dfm_char_ctl_s            cn63xx;
-	struct cvmx_dfm_char_ctl_s            cn63xxp1;
+	} cn63xx;
+	struct cvmx_dfm_char_ctl_cn63xx       cn63xxp1;
+	struct cvmx_dfm_char_ctl_s            cn66xx;
 };
 typedef union cvmx_dfm_char_ctl cvmx_dfm_char_ctl_t;
 
@@ -454,12 +479,10 @@ typedef union cvmx_dfm_char_ctl cvmx_dfm_char_ctl_t;
  * DFM_CHAR_MASK0 = DFM Characterization Control Mask0
  * This register is an assortment of various control fields needed to charecterize the DDR3 interface
  */
-union cvmx_dfm_char_mask0
-{
+union cvmx_dfm_char_mask0 {
 	uint64_t u64;
-	struct cvmx_dfm_char_mask0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_char_mask0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t mask                         : 16; /**< Mask for DQ0[15:0] */
 #else
@@ -469,6 +492,7 @@ union cvmx_dfm_char_mask0
 	} s;
 	struct cvmx_dfm_char_mask0_s          cn63xx;
 	struct cvmx_dfm_char_mask0_s          cn63xxp1;
+	struct cvmx_dfm_char_mask0_s          cn66xx;
 };
 typedef union cvmx_dfm_char_mask0 cvmx_dfm_char_mask0_t;
 
@@ -478,12 +502,10 @@ typedef union cvmx_dfm_char_mask0 cvmx_dfm_char_mask0_t;
  * DFM_CHAR_MASK2 = DFM Characterization Control Mask2
  * This register is an assortment of various control fields needed to charecterize the DDR3 interface
  */
-union cvmx_dfm_char_mask2
-{
+union cvmx_dfm_char_mask2 {
 	uint64_t u64;
-	struct cvmx_dfm_char_mask2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_char_mask2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t mask                         : 16; /**< Mask for DQ1[15:0] */
 #else
@@ -493,6 +515,7 @@ union cvmx_dfm_char_mask2
 	} s;
 	struct cvmx_dfm_char_mask2_s          cn63xx;
 	struct cvmx_dfm_char_mask2_s          cn63xxp1;
+	struct cvmx_dfm_char_mask2_s          cn66xx;
 };
 typedef union cvmx_dfm_char_mask2 cvmx_dfm_char_mask2_t;
 
@@ -502,12 +525,10 @@ typedef union cvmx_dfm_char_mask2 cvmx_dfm_char_mask2_t;
  * DFM_CHAR_MASK4 = DFM Characterization Mask4
  * This register is an assortment of various control fields needed to charecterize the DDR3 interface
  */
-union cvmx_dfm_char_mask4
-{
+union cvmx_dfm_char_mask4 {
 	uint64_t u64;
-	struct cvmx_dfm_char_mask4_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_char_mask4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_33_63               : 31;
 	uint64_t reset_n_mask                 : 1;  /**< Mask for RESET_N */
 	uint64_t a_mask                       : 16; /**< Mask for A[15:0] */
@@ -539,6 +560,7 @@ union cvmx_dfm_char_mask4
 #endif
 	} s;
 	struct cvmx_dfm_char_mask4_s          cn63xx;
+	struct cvmx_dfm_char_mask4_s          cn66xx;
 };
 typedef union cvmx_dfm_char_mask4 cvmx_dfm_char_mask4_t;
 
@@ -548,12 +570,10 @@ typedef union cvmx_dfm_char_mask4 cvmx_dfm_char_mask4_t;
  * DFM_COMP_CTL2 = DFM Compensation control2
  *
  */
-union cvmx_dfm_comp_ctl2
-{
+union cvmx_dfm_comp_ctl2 {
 	uint64_t u64;
-	struct cvmx_dfm_comp_ctl2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_comp_ctl2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t ddr__ptune                   : 4;  /**< DDR pctl from compensation circuit
                                                          The encoded value provides debug information for the
@@ -617,6 +637,7 @@ union cvmx_dfm_comp_ctl2
 	} s;
 	struct cvmx_dfm_comp_ctl2_s           cn63xx;
 	struct cvmx_dfm_comp_ctl2_s           cn63xxp1;
+	struct cvmx_dfm_comp_ctl2_s           cn66xx;
 };
 typedef union cvmx_dfm_comp_ctl2 cvmx_dfm_comp_ctl2_t;
 
@@ -658,12 +679,10 @@ typedef union cvmx_dfm_comp_ctl2 cvmx_dfm_comp_ctl2_t;
  *       ]
  *    ]
  */
-union cvmx_dfm_config
-{
+union cvmx_dfm_config {
 	uint64_t u64;
-	struct cvmx_dfm_config_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_config_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_59_63               : 5;
 	uint64_t early_unload_d1_r1           : 1;  /**< Reserved */
 	uint64_t early_unload_d1_r0           : 1;  /**< Reserved */
@@ -893,9 +912,8 @@ union cvmx_dfm_config
 #endif
 	} s;
 	struct cvmx_dfm_config_s              cn63xx;
-	struct cvmx_dfm_config_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_config_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_55_63               : 9;
 	uint64_t init_status                  : 4;  /**< Indicates status of initialization
                                                          INIT_STATUS[n] = 1 implies rank n has been initialized
@@ -1098,6 +1116,7 @@ union cvmx_dfm_config
 	uint64_t reserved_55_63               : 9;
 #endif
 	} cn63xxp1;
+	struct cvmx_dfm_config_s              cn66xx;
 };
 typedef union cvmx_dfm_config cvmx_dfm_config_t;
 
@@ -1107,12 +1126,10 @@ typedef union cvmx_dfm_config cvmx_dfm_config_t;
  * DFM_CONTROL = DFM Control
  * This register is an assortment of various control fields needed by the memory controller
  */
-union cvmx_dfm_control
-{
+union cvmx_dfm_control {
 	uint64_t u64;
-	struct cvmx_dfm_control_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t rodt_bprch                   : 1;  /**< When set, the turn-off time for the ODT pin during a
                                                          RD cmd is delayed an additional DCLK cycle. */
@@ -1187,9 +1204,8 @@ union cvmx_dfm_control
 #endif
 	} s;
 	struct cvmx_dfm_control_s             cn63xx;
-	struct cvmx_dfm_control_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_control_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_22_63               : 42;
 	uint64_t bprch                        : 2;  /**< Back Porch Enable: When set, the turn-on time for
                                                          the default DDR_DQ/DQS drivers is delayed an additional BPRCH FCLK
@@ -1257,6 +1273,7 @@ union cvmx_dfm_control
 	uint64_t reserved_22_63               : 42;
 #endif
 	} cn63xxp1;
+	struct cvmx_dfm_control_s             cn66xx;
 };
 typedef union cvmx_dfm_control cvmx_dfm_control_t;
 
@@ -1284,12 +1301,10 @@ typedef union cvmx_dfm_control cvmx_dfm_control_t;
  * 8. Write 0 to DFM_DLL_CTL2[DRESET].  DFM_DLL_CTL2[DRESET] must not change after this point without restarting the DFM and/or
  *    DRESET initialization sequence.
  */
-union cvmx_dfm_dll_ctl2
-{
+union cvmx_dfm_dll_ctl2 {
 	uint64_t u64;
-	struct cvmx_dfm_dll_ctl2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_dll_ctl2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_15_63               : 49;
 	uint64_t dll_bringup                  : 1;  /**< DLL Bringup */
 	uint64_t dreset                       : 1;  /**< Fclk domain reset.  The reset signal that is used by the
@@ -1320,6 +1335,7 @@ union cvmx_dfm_dll_ctl2
 	} s;
 	struct cvmx_dfm_dll_ctl2_s            cn63xx;
 	struct cvmx_dfm_dll_ctl2_s            cn63xxp1;
+	struct cvmx_dfm_dll_ctl2_s            cn66xx;
 };
 typedef union cvmx_dfm_dll_ctl2 cvmx_dfm_dll_ctl2_t;
 
@@ -1329,12 +1345,10 @@ typedef union cvmx_dfm_dll_ctl2 cvmx_dfm_dll_ctl2_t;
  * DFM_DLL_CTL3 = DFM DLL control and FCLK reset
  *
  */
-union cvmx_dfm_dll_ctl3
-{
+union cvmx_dfm_dll_ctl3 {
 	uint64_t u64;
-	struct cvmx_dfm_dll_ctl3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_dll_ctl3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t dll_fast                     : 1;  /**< DLL lock
                                                          0 = DLL locked */
@@ -1387,6 +1401,7 @@ union cvmx_dfm_dll_ctl3
 	} s;
 	struct cvmx_dfm_dll_ctl3_s            cn63xx;
 	struct cvmx_dfm_dll_ctl3_s            cn63xxp1;
+	struct cvmx_dfm_dll_ctl3_s            cn66xx;
 };
 typedef union cvmx_dfm_dll_ctl3 cvmx_dfm_dll_ctl3_t;
 
@@ -1396,12 +1411,10 @@ typedef union cvmx_dfm_dll_ctl3 cvmx_dfm_dll_ctl3_t;
  * DFM_FCLK_CNT  = Performance Counters
  *
  */
-union cvmx_dfm_fclk_cnt
-{
+union cvmx_dfm_fclk_cnt {
 	uint64_t u64;
-	struct cvmx_dfm_fclk_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_fclk_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t fclkcnt                      : 64; /**< Performance Counter that counts fclks
                                                          64-bit counter. */
 #else
@@ -1410,6 +1423,7 @@ union cvmx_dfm_fclk_cnt
 	} s;
 	struct cvmx_dfm_fclk_cnt_s            cn63xx;
 	struct cvmx_dfm_fclk_cnt_s            cn63xxp1;
+	struct cvmx_dfm_fclk_cnt_s            cn66xx;
 };
 typedef union cvmx_dfm_fclk_cnt cvmx_dfm_fclk_cnt_t;
 
@@ -1420,12 +1434,10 @@ typedef union cvmx_dfm_fclk_cnt cvmx_dfm_fclk_cnt_t;
  *
  * This register contains Bist Status for DFM Front
  */
-union cvmx_dfm_fnt_bist
-{
+union cvmx_dfm_fnt_bist {
 	uint64_t u64;
-	struct cvmx_dfm_fnt_bist_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_fnt_bist_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t cab                          : 1;  /**< Bist Results for CAB RAM
                                                          - 0: GOOD (or bist in progress/never run)
@@ -1452,9 +1464,8 @@ union cvmx_dfm_fnt_bist
 #endif
 	} s;
 	struct cvmx_dfm_fnt_bist_s            cn63xx;
-	struct cvmx_dfm_fnt_bist_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_fnt_bist_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t mrq                          : 1;  /**< Bist Results for MRQ RAM
                                                          - 0: GOOD (or bist in progress/never run)
@@ -1476,6 +1487,7 @@ union cvmx_dfm_fnt_bist
 	uint64_t reserved_4_63                : 60;
 #endif
 	} cn63xxp1;
+	struct cvmx_dfm_fnt_bist_s            cn66xx;
 };
 typedef union cvmx_dfm_fnt_bist cvmx_dfm_fnt_bist_t;
 
@@ -1488,12 +1500,10 @@ typedef union cvmx_dfm_fnt_bist cvmx_dfm_fnt_bist_t;
  *
  * This register contains control registers for the DFM Front Section of Logic.
  */
-union cvmx_dfm_fnt_ctl
-{
+union cvmx_dfm_fnt_ctl {
 	uint64_t u64;
-	struct cvmx_dfm_fnt_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_fnt_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t sbe_ena                      : 1;  /**< If SBE_ENA=1 & RECC_ENA=1 then all single bit errors
                                                          which have been detected/corrected during GWALK reads,
@@ -1558,6 +1568,7 @@ union cvmx_dfm_fnt_ctl
 	} s;
 	struct cvmx_dfm_fnt_ctl_s             cn63xx;
 	struct cvmx_dfm_fnt_ctl_s             cn63xxp1;
+	struct cvmx_dfm_fnt_ctl_s             cn66xx;
 };
 typedef union cvmx_dfm_fnt_ctl cvmx_dfm_fnt_ctl_t;
 
@@ -1568,12 +1579,10 @@ typedef union cvmx_dfm_fnt_ctl cvmx_dfm_fnt_ctl_t;
  *
  * This register contains error interrupt enable information for the DFM Front Section of Logic.
  */
-union cvmx_dfm_fnt_iena
-{
+union cvmx_dfm_fnt_iena {
 	uint64_t u64;
-	struct cvmx_dfm_fnt_iena_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_fnt_iena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t dbe_intena                   : 1;  /**< OWECC Double Error Detected(DED) Interrupt Enable
                                                          When set, the memory controller raises a processor
@@ -1592,6 +1601,7 @@ union cvmx_dfm_fnt_iena
 	} s;
 	struct cvmx_dfm_fnt_iena_s            cn63xx;
 	struct cvmx_dfm_fnt_iena_s            cn63xxp1;
+	struct cvmx_dfm_fnt_iena_s            cn66xx;
 };
 typedef union cvmx_dfm_fnt_iena cvmx_dfm_fnt_iena_t;
 
@@ -1605,12 +1615,10 @@ typedef union cvmx_dfm_fnt_iena cvmx_dfm_fnt_iena_t;
  * to start a software BiST sequence for the DFM sub-block. (note: the DFM has conditional clocks which
  * prevent BiST to run under reset automatically).
  */
-union cvmx_dfm_fnt_sclk
-{
+union cvmx_dfm_fnt_sclk {
 	uint64_t u64;
-	struct cvmx_dfm_fnt_sclk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_fnt_sclk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t clear_bist                   : 1;  /**< When START_BIST is written 0->1, if CLEAR_BIST=1, all
                                                          previous BiST state is cleared.
@@ -1642,6 +1650,7 @@ union cvmx_dfm_fnt_sclk
 	} s;
 	struct cvmx_dfm_fnt_sclk_s            cn63xx;
 	struct cvmx_dfm_fnt_sclk_s            cn63xxp1;
+	struct cvmx_dfm_fnt_sclk_s            cn66xx;
 };
 typedef union cvmx_dfm_fnt_sclk cvmx_dfm_fnt_sclk_t;
 
@@ -1652,12 +1661,10 @@ typedef union cvmx_dfm_fnt_sclk cvmx_dfm_fnt_sclk_t;
  *
  * This register contains error status information for the DFM Front Section of Logic.
  */
-union cvmx_dfm_fnt_stat
-{
+union cvmx_dfm_fnt_stat {
 	uint64_t u64;
-	struct cvmx_dfm_fnt_stat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_fnt_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_42_63               : 22;
 	uint64_t fsyn                         : 10; /**< Failing Syndrome
                                                          If SBE_ERR=1, the FSYN code determines which bit was
@@ -1699,6 +1706,7 @@ union cvmx_dfm_fnt_stat
 	} s;
 	struct cvmx_dfm_fnt_stat_s            cn63xx;
 	struct cvmx_dfm_fnt_stat_s            cn63xxp1;
+	struct cvmx_dfm_fnt_stat_s            cn66xx;
 };
 typedef union cvmx_dfm_fnt_stat cvmx_dfm_fnt_stat_t;
 
@@ -1708,21 +1716,21 @@ typedef union cvmx_dfm_fnt_stat cvmx_dfm_fnt_stat_t;
  * DFM_IFB_CNT  = Performance Counters
  *
  */
-union cvmx_dfm_ifb_cnt
-{
+union cvmx_dfm_ifb_cnt {
 	uint64_t u64;
-	struct cvmx_dfm_ifb_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_ifb_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t ifbcnt                       : 64; /**< Performance Counter
                                                          64-bit counter that increments every
-                                                         cycle there is something in the in-flight buffer. */
+                                                         cycle there is something in the in-flight buffer.
+                                                         Before using, clear counter via DFM_CONTROL.BWCNT. */
 #else
 	uint64_t ifbcnt                       : 64;
 #endif
 	} s;
 	struct cvmx_dfm_ifb_cnt_s             cn63xx;
 	struct cvmx_dfm_ifb_cnt_s             cn63xxp1;
+	struct cvmx_dfm_ifb_cnt_s             cn66xx;
 };
 typedef union cvmx_dfm_ifb_cnt cvmx_dfm_ifb_cnt_t;
 
@@ -1733,12 +1741,10 @@ typedef union cvmx_dfm_ifb_cnt cvmx_dfm_ifb_cnt_t;
  * These parameters are written into the DDR3 MR0, MR1, MR2 and MR3 registers.
  *
  */
-union cvmx_dfm_modereg_params0
-{
+union cvmx_dfm_modereg_params0 {
 	uint64_t u64;
-	struct cvmx_dfm_modereg_params0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_modereg_params0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_25_63               : 39;
 	uint64_t ppd                          : 1;  /**< DLL Control for precharge powerdown
                                                          0 = Slow exit (DLL off)
@@ -1751,14 +1757,14 @@ union cvmx_dfm_modereg_params0
 	uint64_t wrp                          : 3;  /**< Write recovery for auto precharge
                                                          Should be programmed to be equal to or greater than
                                                          RNDUP[tWR(ns)/tCYC(ns)]
-                                                         000 = Reserved
+                                                         000 = 5
                                                          001 = 5
                                                          010 = 6
                                                          011 = 7
                                                          100 = 8
                                                          101 = 10
                                                          110 = 12
-                                                         111 = Reserved
+                                                         111 = 14
                                                          DFM writes this value to MR0[WR] in the selected DDR3 parts
                                                          during power-up/init instruction sequencing.
                                                          See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK].
@@ -1791,7 +1797,12 @@ union cvmx_dfm_modereg_params0
                                                          1010 = 9
                                                          1100 = 10
                                                          1110 = 11
-                                                         0000, ???1 = Reserved
+                                                         0001 = 12
+                                                         0011 = 13
+                                                         0101 = 14
+                                                         0111 = 15
+                                                         1001 = 16
+                                                         0000, 1011, 1101, 1111 = Reserved
                                                          DFM writes this value to MR0[CAS Latency / CL] in the selected DDR3 parts
                                                          during power-up/init instruction sequencing.
                                                          See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK].
@@ -1887,7 +1898,10 @@ union cvmx_dfm_modereg_params0
                                                          - 001: 6
                                                          - 010: 7
                                                          - 011: 8
-                                                         1xx: Reserved
+                                                         - 100: 9
+                                                         - 101: 10
+                                                         - 110: 11
+                                                         - 111: 12
                                                          DFM writes this value to MR2[CWL] in the selected DDR3 parts
                                                          during power-up/init instruction sequencing.
                                                          If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
@@ -1918,6 +1932,7 @@ union cvmx_dfm_modereg_params0
 	} s;
 	struct cvmx_dfm_modereg_params0_s     cn63xx;
 	struct cvmx_dfm_modereg_params0_s     cn63xxp1;
+	struct cvmx_dfm_modereg_params0_s     cn66xx;
 };
 typedef union cvmx_dfm_modereg_params0 cvmx_dfm_modereg_params0_t;
 
@@ -1928,12 +1943,10 @@ typedef union cvmx_dfm_modereg_params0 cvmx_dfm_modereg_params0_t;
  * These parameters are written into the DDR3 MR0, MR1, MR2 and MR3 registers.
  *
  */
-union cvmx_dfm_modereg_params1
-{
+union cvmx_dfm_modereg_params1 {
 	uint64_t u64;
-	struct cvmx_dfm_modereg_params1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_modereg_params1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t rtt_nom_11                   : 3;  /**< Must be zero */
 	uint64_t dic_11                       : 2;  /**< Must be zero */
@@ -2073,6 +2086,7 @@ union cvmx_dfm_modereg_params1
 	} s;
 	struct cvmx_dfm_modereg_params1_s     cn63xx;
 	struct cvmx_dfm_modereg_params1_s     cn63xxp1;
+	struct cvmx_dfm_modereg_params1_s     cn66xx;
 };
 typedef union cvmx_dfm_modereg_params1 cvmx_dfm_modereg_params1_t;
 
@@ -2082,15 +2096,14 @@ typedef union cvmx_dfm_modereg_params1 cvmx_dfm_modereg_params1_t;
  * DFM_OPS_CNT  = Performance Counters
  *
  */
-union cvmx_dfm_ops_cnt
-{
+union cvmx_dfm_ops_cnt {
 	uint64_t u64;
-	struct cvmx_dfm_ops_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_ops_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t opscnt                       : 64; /**< Performance Counter
                                                          64-bit counter that increments when the DDR3 data bus
-                                                         is being used.
+                                                         is being used.  Before using, clear counter via
+                                                         DFM_CONTROL.BWCNT
                                                            DRAM bus utilization = DFM_OPS_CNT/DFM_FCLK_CNT */
 #else
 	uint64_t opscnt                       : 64;
@@ -2098,6 +2111,7 @@ union cvmx_dfm_ops_cnt
 	} s;
 	struct cvmx_dfm_ops_cnt_s             cn63xx;
 	struct cvmx_dfm_ops_cnt_s             cn63xxp1;
+	struct cvmx_dfm_ops_cnt_s             cn66xx;
 };
 typedef union cvmx_dfm_ops_cnt cvmx_dfm_ops_cnt_t;
 
@@ -2107,12 +2121,10 @@ typedef union cvmx_dfm_ops_cnt cvmx_dfm_ops_cnt_t;
  * DFM_PHY_CTL = DFM PHY Control
  *
  */
-union cvmx_dfm_phy_ctl
-{
+union cvmx_dfm_phy_ctl {
 	uint64_t u64;
-	struct cvmx_dfm_phy_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_phy_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_15_63               : 49;
 	uint64_t rx_always_on                 : 1;  /**< Disable dynamic DDR3 IO Rx power gating */
 	uint64_t lv_mode                      : 1;  /**< Low Voltage Mode (1.35V) */
@@ -2149,9 +2161,8 @@ union cvmx_dfm_phy_ctl
 #endif
 	} s;
 	struct cvmx_dfm_phy_ctl_s             cn63xx;
-	struct cvmx_dfm_phy_ctl_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_phy_ctl_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t lv_mode                      : 1;  /**< Low Voltage Mode (1.35V) */
 	uint64_t ck_tune1                     : 1;  /**< Clock Tune
@@ -2185,6 +2196,7 @@ union cvmx_dfm_phy_ctl
 	uint64_t reserved_14_63               : 50;
 #endif
 	} cn63xxp1;
+	struct cvmx_dfm_phy_ctl_s             cn66xx;
 };
 typedef union cvmx_dfm_phy_ctl cvmx_dfm_phy_ctl_t;
 
@@ -2198,9 +2210,9 @@ typedef union cvmx_dfm_phy_ctl cvmx_dfm_phy_ctl_t;
  * DDR3RST - DDR3 DRAM parts have a new RESET#
  * pin that wasn't present in DDR2 parts. The
  * DDR3RST CSR field controls the assertion of
- * the new 63xx pin that attaches to RESET#.
- * When DDR3RST is set, 63xx asserts RESET#.
- * When DDR3RST is clear, 63xx de-asserts
+ * the new 6xxx pin that attaches to RESET#.
+ * When DDR3RST is set, 6xxx asserts RESET#.
+ * When DDR3RST is clear, 6xxx de-asserts
  * RESET#.
  *
  * DDR3RST is set on a cold reset. Warm and
@@ -2208,12 +2220,10 @@ typedef union cvmx_dfm_phy_ctl cvmx_dfm_phy_ctl_t;
  * value. Outside of cold reset, only software
  * CSR writes change the DDR3RST value.
  */
-union cvmx_dfm_reset_ctl
-{
+union cvmx_dfm_reset_ctl {
 	uint64_t u64;
-	struct cvmx_dfm_reset_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_reset_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t ddr3psv                      : 1;  /**< Must be zero */
 	uint64_t ddr3psoft                    : 1;  /**< Must be zero */
@@ -2231,18 +2241,17 @@ union cvmx_dfm_reset_ctl
 	} s;
 	struct cvmx_dfm_reset_ctl_s           cn63xx;
 	struct cvmx_dfm_reset_ctl_s           cn63xxp1;
+	struct cvmx_dfm_reset_ctl_s           cn66xx;
 };
 typedef union cvmx_dfm_reset_ctl cvmx_dfm_reset_ctl_t;
 
 /**
  * cvmx_dfm_rlevel_ctl
  */
-union cvmx_dfm_rlevel_ctl
-{
+union cvmx_dfm_rlevel_ctl {
 	uint64_t u64;
-	struct cvmx_dfm_rlevel_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_rlevel_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_22_63               : 42;
 	uint64_t delay_unload_3               : 1;  /**< When set, unload the PHY silo one cycle later
                                                          during read-leveling if DFM_RLEVEL_RANKi[BYTE*<1:0>] = 3
@@ -2283,9 +2292,8 @@ union cvmx_dfm_rlevel_ctl
 #endif
 	} s;
 	struct cvmx_dfm_rlevel_ctl_s          cn63xx;
-	struct cvmx_dfm_rlevel_ctl_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_rlevel_ctl_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t offset_en                    : 1;  /**< Use DFM_RLEVEL_CTL[OFFSET] to calibrate read
                                                          level dskew settings */
@@ -2302,6 +2310,7 @@ union cvmx_dfm_rlevel_ctl
 	uint64_t reserved_9_63                : 55;
 #endif
 	} cn63xxp1;
+	struct cvmx_dfm_rlevel_ctl_s          cn66xx;
 };
 typedef union cvmx_dfm_rlevel_ctl cvmx_dfm_rlevel_ctl_t;
 
@@ -2317,12 +2326,10 @@ typedef union cvmx_dfm_rlevel_ctl cvmx_dfm_rlevel_ctl_t;
  * if you run read-leveling separately for each rank, probing DFM_RLEVEL_DBG between each
  * read-leveling.
  */
-union cvmx_dfm_rlevel_dbg
-{
+union cvmx_dfm_rlevel_dbg {
 	uint64_t u64;
-	struct cvmx_dfm_rlevel_dbg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_rlevel_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bitmask                      : 64; /**< Bitmask generated during deskew settings sweep
                                                          BITMASK[n]=0 means deskew setting n failed
                                                          BITMASK[n]=1 means deskew setting n passed
@@ -2333,6 +2340,7 @@ union cvmx_dfm_rlevel_dbg
 	} s;
 	struct cvmx_dfm_rlevel_dbg_s          cn63xx;
 	struct cvmx_dfm_rlevel_dbg_s          cn63xxp1;
+	struct cvmx_dfm_rlevel_dbg_s          cn66xx;
 };
 typedef union cvmx_dfm_rlevel_dbg cvmx_dfm_rlevel_dbg_t;
 
@@ -2353,12 +2361,10 @@ typedef union cvmx_dfm_rlevel_dbg cvmx_dfm_rlevel_dbg_t;
  * SW initiates a HW read-leveling sequence by programming DFM_RLEVEL_CTL and writing INIT_START=1 with SEQUENCE=1 in DFM_CONFIG.
  * See DFM_RLEVEL_CTL.
  */
-union cvmx_dfm_rlevel_rankx
-{
+union cvmx_dfm_rlevel_rankx {
 	uint64_t u64;
-	struct cvmx_dfm_rlevel_rankx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_rlevel_rankx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_56_63               : 8;
 	uint64_t status                       : 2;  /**< Indicates status of the read-levelling and where
                                                          the BYTE* programmings in <35:0> came from:
@@ -2379,6 +2385,7 @@ union cvmx_dfm_rlevel_rankx
 	} s;
 	struct cvmx_dfm_rlevel_rankx_s        cn63xx;
 	struct cvmx_dfm_rlevel_rankx_s        cn63xxp1;
+	struct cvmx_dfm_rlevel_rankx_s        cn66xx;
 };
 typedef union cvmx_dfm_rlevel_rankx cvmx_dfm_rlevel_rankx_t;
 
@@ -2422,12 +2429,10 @@ typedef union cvmx_dfm_rlevel_rankx cvmx_dfm_rlevel_rankx_t;
  * Note that it may be necessary to force DFM to space back-to-back 128-bit reads
  * to different ranks apart by at least 6+DFM_CONTROL[RODT_BPRCH] CK's to prevent DDR3 ODTH8 violations.
  */
-union cvmx_dfm_rodt_mask
-{
+union cvmx_dfm_rodt_mask {
 	uint64_t u64;
-	struct cvmx_dfm_rodt_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_rodt_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rodt_d3_r1                   : 8;  /**< Must be zero. */
 	uint64_t rodt_d3_r0                   : 8;  /**< Must be zero. */
 	uint64_t rodt_d2_r1                   : 8;  /**< Must be zero. */
@@ -2453,6 +2458,7 @@ union cvmx_dfm_rodt_mask
 	} s;
 	struct cvmx_dfm_rodt_mask_s           cn63xx;
 	struct cvmx_dfm_rodt_mask_s           cn63xxp1;
+	struct cvmx_dfm_rodt_mask_s           cn66xx;
 };
 typedef union cvmx_dfm_rodt_mask cvmx_dfm_rodt_mask_t;
 
@@ -2468,12 +2474,10 @@ typedef union cvmx_dfm_rodt_mask cvmx_dfm_rodt_mask_t;
  * have valid data.
  * R2W_INIT has 1 extra CK cycle built in for odt settling/channel turnaround time.
  */
-union cvmx_dfm_slot_ctl0
-{
+union cvmx_dfm_slot_ctl0 {
 	uint64_t u64;
-	struct cvmx_dfm_slot_ctl0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_slot_ctl0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t w2w_init                     : 6;  /**< Write-to-write spacing control
                                                          for back to back accesses to the same rank and dimm */
@@ -2493,6 +2497,7 @@ union cvmx_dfm_slot_ctl0
 	} s;
 	struct cvmx_dfm_slot_ctl0_s           cn63xx;
 	struct cvmx_dfm_slot_ctl0_s           cn63xxp1;
+	struct cvmx_dfm_slot_ctl0_s           cn66xx;
 };
 typedef union cvmx_dfm_slot_ctl0 cvmx_dfm_slot_ctl0_t;
 
@@ -2508,12 +2513,10 @@ typedef union cvmx_dfm_slot_ctl0 cvmx_dfm_slot_ctl0_t;
  * have valid data.
  * R2W_XRANK_INIT, W2R_XRANK_INIT have 1 extra CK cycle built in for odt settling/channel turnaround time.
  */
-union cvmx_dfm_slot_ctl1
-{
+union cvmx_dfm_slot_ctl1 {
 	uint64_t u64;
-	struct cvmx_dfm_slot_ctl1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_slot_ctl1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t w2w_xrank_init               : 6;  /**< Write-to-write spacing control
                                                          for back to back accesses across ranks of the same dimm */
@@ -2533,18 +2536,17 @@ union cvmx_dfm_slot_ctl1
 	} s;
 	struct cvmx_dfm_slot_ctl1_s           cn63xx;
 	struct cvmx_dfm_slot_ctl1_s           cn63xxp1;
+	struct cvmx_dfm_slot_ctl1_s           cn66xx;
 };
 typedef union cvmx_dfm_slot_ctl1 cvmx_dfm_slot_ctl1_t;
 
 /**
  * cvmx_dfm_timing_params0
  */
-union cvmx_dfm_timing_params0
-{
+union cvmx_dfm_timing_params0 {
 	uint64_t u64;
-	struct cvmx_dfm_timing_params0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_timing_params0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_47_63               : 17;
 	uint64_t trp_ext                      : 1;  /**< Indicates tRP constraints.
                                                          Set [TRP_EXT[0:0], TRP[3:0]] (CSR field) = RNDUP[tRP(ns)/tCYC(ns)]
@@ -2559,7 +2561,7 @@ union cvmx_dfm_timing_params0
                                                          is the DDR clock frequency (not data rate).
                                                          TYP=max(5nCK, 10ns) */
 	uint64_t trp                          : 4;  /**< Indicates tRP constraints.
-                                                         Set TRP (CSR field) = RNDUP[tRP(ns)/tCYC(ns)]
+                                                         Set [TRP_EXT[0:0], TRP[3:0]] (CSR field) = RNDUP[tRP(ns)/tCYC(ns)]
                                                          + (RNDUP[tRTP(ns)/tCYC(ns)])-4)-1,
                                                          where tRP, tRTP are from the DDR3 spec, and tCYC(ns)
                                                          is the DDR clock frequency (not data rate).
@@ -2618,9 +2620,8 @@ union cvmx_dfm_timing_params0
 	uint64_t reserved_47_63               : 17;
 #endif
 	} s;
-	struct cvmx_dfm_timing_params0_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_timing_params0_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_47_63               : 17;
 	uint64_t trp_ext                      : 1;  /**< Indicates tRP constraints.
                                                          Set [TRP_EXT[0:0], TRP[3:0]] (CSR field) = RNDUP[tRP(ns)/tCYC(ns)]
@@ -2694,9 +2695,8 @@ union cvmx_dfm_timing_params0
 	uint64_t reserved_47_63               : 17;
 #endif
 	} cn63xx;
-	struct cvmx_dfm_timing_params0_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_timing_params0_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_46_63               : 18;
 	uint64_t tcksre                       : 4;  /**< Indicates tCKSRE constraints.
                                                          Set TCKSRE (CSR field) = RNDUP[tCKSRE(ns)/tCYC(ns)]-1,
@@ -2762,18 +2762,17 @@ union cvmx_dfm_timing_params0
 	uint64_t reserved_46_63               : 18;
 #endif
 	} cn63xxp1;
+	struct cvmx_dfm_timing_params0_cn63xx cn66xx;
 };
 typedef union cvmx_dfm_timing_params0 cvmx_dfm_timing_params0_t;
 
 /**
  * cvmx_dfm_timing_params1
  */
-union cvmx_dfm_timing_params1
-{
+union cvmx_dfm_timing_params1 {
 	uint64_t u64;
-	struct cvmx_dfm_timing_params1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_timing_params1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_47_63               : 17;
 	uint64_t tras_ext                     : 1;  /**< Indicates tRAS constraints.
                                                          Set [TRAS_EXT[0:0], TRAS[4:0]] (CSR field) = RNDUP[tRAS(ns)/tCYC(ns)]-1,
@@ -2857,15 +2856,15 @@ union cvmx_dfm_timing_params1
                                                          In 2T mode, make this register TRCD-1, not going
                                                          below 2. */
 	uint64_t tras                         : 5;  /**< Indicates tRAS constraints.
-                                                         Set TRAS (CSR field) = RNDUP[tRAS(ns)/tCYC(ns)]-1,
+                                                         Set [TRAS_EXT[0:0], TRAS[4:0]] (CSR field) = RNDUP[tRAS(ns)/tCYC(ns)]-1,
                                                          where tRAS is from the DDR3 spec, and tCYC(ns)
                                                          is the DDR clock frequency (not data rate).
                                                          TYP=35ns-9*tREFI
-                                                             - 00000: RESERVED
-                                                             - 00001: 2 tCYC
-                                                             - 00010: 3 tCYC
+                                                             - 000000: RESERVED
+                                                             - 000001: 2 tCYC
+                                                             - 000010: 3 tCYC
                                                              - ...
-                                                             - 11111: 32 tCYC */
+                                                             - 111111: 64 tCYC */
 	uint64_t tmprr                        : 4;  /**< Indicates tMPRR constraints.
                                                          Set TMPRR (CSR field) = RNDUP[tMPRR(ns)/tCYC(ns)]-1,
                                                          where tMPRR is from the DDR3 spec, and tCYC(ns)
@@ -2888,9 +2887,8 @@ union cvmx_dfm_timing_params1
 #endif
 	} s;
 	struct cvmx_dfm_timing_params1_s      cn63xx;
-	struct cvmx_dfm_timing_params1_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_timing_params1_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_46_63               : 18;
 	uint64_t txpdll                       : 5;  /**< Indicates tXPDLL constraints.
                                                          Set TXPDLL (CSR field) = RNDUP[tXPDLL(ns)/tCYC(ns)]-1,
@@ -2993,18 +2991,17 @@ union cvmx_dfm_timing_params1
 	uint64_t reserved_46_63               : 18;
 #endif
 	} cn63xxp1;
+	struct cvmx_dfm_timing_params1_s      cn66xx;
 };
 typedef union cvmx_dfm_timing_params1 cvmx_dfm_timing_params1_t;
 
 /**
  * cvmx_dfm_wlevel_ctl
  */
-union cvmx_dfm_wlevel_ctl
-{
+union cvmx_dfm_wlevel_ctl {
 	uint64_t u64;
-	struct cvmx_dfm_wlevel_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_wlevel_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_22_63               : 42;
 	uint64_t rtt_nom                      : 3;  /**< RTT_NOM
                                                          DFM writes a decoded value to MR1[Rtt_Nom] of the rank during
@@ -3039,9 +3036,8 @@ union cvmx_dfm_wlevel_ctl
 #endif
 	} s;
 	struct cvmx_dfm_wlevel_ctl_s          cn63xx;
-	struct cvmx_dfm_wlevel_ctl_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_wlevel_ctl_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t sset                         : 1;  /**< Run write-leveling on the current setting only. */
 	uint64_t lanemask                     : 9;  /**< One-hot mask to select byte lane to be leveled by
@@ -3055,6 +3051,7 @@ union cvmx_dfm_wlevel_ctl
 	uint64_t reserved_10_63               : 54;
 #endif
 	} cn63xxp1;
+	struct cvmx_dfm_wlevel_ctl_s          cn66xx;
 };
 typedef union cvmx_dfm_wlevel_ctl cvmx_dfm_wlevel_ctl_t;
 
@@ -3070,12 +3067,10 @@ typedef union cvmx_dfm_wlevel_ctl cvmx_dfm_wlevel_ctl_t;
  * if you run write-leveling separately for each rank, probing DFM_WLEVEL_DBG between each
  * write-leveling.
  */
-union cvmx_dfm_wlevel_dbg
-{
+union cvmx_dfm_wlevel_dbg {
 	uint64_t u64;
-	struct cvmx_dfm_wlevel_dbg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_wlevel_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t bitmask                      : 8;  /**< Bitmask generated during deskew settings sweep
                                                          if DFM_WLEVEL_CTL[SSET]=0
@@ -3096,6 +3091,7 @@ union cvmx_dfm_wlevel_dbg
 	} s;
 	struct cvmx_dfm_wlevel_dbg_s          cn63xx;
 	struct cvmx_dfm_wlevel_dbg_s          cn63xxp1;
+	struct cvmx_dfm_wlevel_dbg_s          cn66xx;
 };
 typedef union cvmx_dfm_wlevel_dbg cvmx_dfm_wlevel_dbg_t;
 
@@ -3121,12 +3117,10 @@ typedef union cvmx_dfm_wlevel_dbg cvmx_dfm_wlevel_dbg_t;
  * set DFM_WLEVEL_RANKn[BYTE*<2:0>] to 4.
  * See DFM_WLEVEL_CTL.
  */
-union cvmx_dfm_wlevel_rankx
-{
+union cvmx_dfm_wlevel_rankx {
 	uint64_t u64;
-	struct cvmx_dfm_wlevel_rankx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_wlevel_rankx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_47_63               : 17;
 	uint64_t status                       : 2;  /**< Indicates status of the write-leveling and where
                                                          the BYTE* programmings in <44:0> came from:
@@ -3150,6 +3144,7 @@ union cvmx_dfm_wlevel_rankx
 	} s;
 	struct cvmx_dfm_wlevel_rankx_s        cn63xx;
 	struct cvmx_dfm_wlevel_rankx_s        cn63xxp1;
+	struct cvmx_dfm_wlevel_rankx_s        cn66xx;
 };
 typedef union cvmx_dfm_wlevel_rankx cvmx_dfm_wlevel_rankx_t;
 
@@ -3188,12 +3183,10 @@ typedef union cvmx_dfm_wlevel_rankx cvmx_dfm_wlevel_rankx_t;
  * cycles of this second word write). Note that it may be necessary to force DFM to space back-to-back
  * word writes to different ranks apart by at least 6 cycles to prevent DDR3 ODTH8 violations.
  */
-union cvmx_dfm_wodt_mask
-{
+union cvmx_dfm_wodt_mask {
 	uint64_t u64;
-	struct cvmx_dfm_wodt_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dfm_wodt_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t wodt_d3_r1                   : 8;  /**< Not used by DFM. */
 	uint64_t wodt_d3_r0                   : 8;  /**< Not used by DFM. */
 	uint64_t wodt_d2_r1                   : 8;  /**< Not used by DFM. */
@@ -3218,6 +3211,7 @@ union cvmx_dfm_wodt_mask
 	} s;
 	struct cvmx_dfm_wodt_mask_s           cn63xx;
 	struct cvmx_dfm_wodt_mask_s           cn63xxp1;
+	struct cvmx_dfm_wodt_mask_s           cn66xx;
 };
 typedef union cvmx_dfm_wodt_mask cvmx_dfm_wodt_mask_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-dma-engine.c b/sys/contrib/octeon-sdk/cvmx-dma-engine.c
index a3718bd..053c372 100644
--- a/sys/contrib/octeon-sdk/cvmx-dma-engine.c
+++ b/sys/contrib/octeon-sdk/cvmx-dma-engine.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,13 +49,29 @@
  * Interface to the PCI / PCIe DMA engines. These are only avialable
  * on chips with PCI / PCIe.
  *
- * <hr>$Revision: 50126 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/octeon-model.h>
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-cmd-queue.h>
+#include <asm/octeon/cvmx-dma-engine.h>
+#include <asm/octeon/octeon-feature.h>
+#include <asm/octeon/cvmx-npi-defs.h>
+#include <asm/octeon/cvmx-npei-defs.h>
+#include <asm/octeon/cvmx-dpi-defs.h>
+#include <asm/octeon/cvmx-pexp-defs.h>
+#include <asm/octeon/cvmx-helper-cfg.h>
+#else
 #include "executive-config.h"
 #include "cvmx-config.h"
 #include "cvmx.h"
 #include "cvmx-cmd-queue.h"
 #include "cvmx-dma-engine.h"
+#include "cvmx-helper-cfg.h"
+#endif
 
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
 
@@ -153,6 +169,7 @@ int cvmx_dma_engine_initialize(void)
     else if (octeon_has_feature(OCTEON_FEATURE_PCIE))
     {
         cvmx_dpi_engx_buf_t dpi_engx_buf;
+        cvmx_dpi_dma_engx_en_t dpi_dma_engx_en;
         cvmx_dpi_dma_control_t dma_control;
         cvmx_dpi_ctl_t dpi_ctl;
 
@@ -172,11 +189,16 @@ int cvmx_dma_engine_initialize(void)
         dma_control.s.pkt_hp = 1;
         dma_control.s.pkt_en = 1;
         dma_control.s.dma_enb = 0x1f;
-        dma_control.s.dwb_denb = 1;
+        dma_control.s.dwb_denb = cvmx_helper_cfg_opt_get(CVMX_HELPER_CFG_OPT_USE_DWB);
         dma_control.s.dwb_ichk = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/128;
         dma_control.s.fpa_que = CVMX_FPA_OUTPUT_BUFFER_POOL;
         dma_control.s.o_mode = 1;
         cvmx_write_csr(CVMX_DPI_DMA_CONTROL, dma_control.u64);
+        /* When dma_control[pkt_en] = 1, engine 5 is used for packets and is not
+           available for DMA. */
+        dpi_dma_engx_en.u64 = cvmx_read_csr(CVMX_DPI_DMA_ENGX_EN(5));
+        dpi_dma_engx_en.s.qen = 0;
+        cvmx_write_csr(CVMX_DPI_DMA_ENGX_EN(5), dpi_dma_engx_en.u64);
         dpi_ctl.u64 = cvmx_read_csr(CVMX_DPI_CTL);
         dpi_ctl.s.en = 1;
         cvmx_write_csr(CVMX_DPI_CTL, dpi_ctl.u64);
@@ -197,10 +219,12 @@ int cvmx_dma_engine_initialize(void)
 
     return 0;
 }
-
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_dma_engine_initialize);
+#endif
 
 /**
- * Shutdown all DMA engines. The engeines must be idle when this
+ * Shutdown all DMA engines. The engines must be idle when this
  * function is called.
  *
  * @return Zero on success, negative on failure
@@ -270,16 +294,18 @@ int cvmx_dma_engine_shutdown(void)
 
     return 0;
 }
-
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_dma_engine_shutdown);
+#endif
 
 /**
- * Submit a series of DMA comamnd to the DMA engines.
+ * Submit a series of DMA command to the DMA engines.
  *
  * @param engine  Engine to submit to (0 to cvmx_dma_engine_get_num()-1)
  * @param header  Command header
  * @param num_buffers
  *                The number of data pointers
- * @param buffers Comamnd data pointers
+ * @param buffers Command data pointers
  *
  * @return Zero on success, negative on failure
  */
@@ -519,5 +545,7 @@ int cvmx_dma_engine_transfer(int engine, cvmx_dma_engine_header_t header,
     }
     return cvmx_dma_engine_submit(engine, header, words, buffers);
 }
-
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_dma_engine_transfer);
+#endif
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-dma-engine.h b/sys/contrib/octeon-sdk/cvmx-dma-engine.h
index c83b7c1..6f8d51c 100644
--- a/sys/contrib/octeon-sdk/cvmx-dma-engine.h
+++ b/sys/contrib/octeon-sdk/cvmx-dma-engine.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,12 +49,18 @@
  * Interface to the PCI / PCIe DMA engines. These are only avialable
  * on chips with PCI / PCIe.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_DMA_ENGINES_H__
 #define __CVMX_DMA_ENGINES_H__
 
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx-dpi-defs.h>
+#else
+#include "cvmx-dpi-defs.h"
+#endif
+
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -264,13 +270,13 @@ int cvmx_dma_engine_shutdown(void);
 int cvmx_dma_engine_get_num(void);
 
 /**
- * Submit a series of DMA comamnd to the DMA engines.
+ * Submit a series of DMA command to the DMA engines.
  *
  * @param engine  Engine to submit to (0 to cvmx_dma_engine_get_num()-1)
  * @param header  Command header
  * @param num_buffers
  *                The number of data pointers
- * @param buffers Comamnd data pointers
+ * @param buffers Command data pointers
  *
  * @return Zero on success, negative on failure
  */
@@ -327,6 +333,44 @@ static inline int cvmx_dma_engine_memcpy(int engine, void *dest, void *source, i
                                     cvmx_ptr_to_phys(dest), length);
 }
 
+/**
+ * Simplified interface to the DMA engines to emulate memcpy()
+ * When dici_mode is enabled, send zero byte.
+ *
+ * @param engine Engine to submit to (0 to cvmx_dma_engine_get_num()-1)
+ * @param dest   Pointer to the destination memory. cvmx_ptr_to_phys() will be
+ *               used to turn this into a physical address. It cannot be a local
+ *               or CVMX_SHARED block.
+ * @param source Pointer to the source memory.
+ *               cvmx_ptr_to_phys() will be used to turn this
+ *               into a physical address. It cannot be a local
+ *               or CVMX_SHARED block.
+ * @param length Number of bytes to copy
+ * @param core   core number for zero byte write
+ *
+ * @return Zero on success, negative on failure
+ */
+static inline int cvmx_dma_engine_memcpy_zero_byte(int engine, void *dest, void *source, int length, int core)
+{
+    cvmx_dma_engine_header_t header;
+    header.u64 = 0;
+    header.s.type = CVMX_DMA_ENGINE_TRANSFER_INTERNAL;
+    /* If dici_mode is set, DPI increments the DPI_DMA_PPn_CNT[CNT], where the
+       value of core n is PTR<5:0>-1 when WQP=0 and PTR != 0 && PTR < 64. */
+    if (octeon_has_feature(OCTEON_FEATURE_DICI_MODE))
+    {
+        cvmx_dpi_dma_control_t dma_control;
+        dma_control.u64 = cvmx_read_csr(CVMX_DPI_DMA_CONTROL);
+        if (dma_control.s.dici_mode)
+        {
+           header.s.wqp = 0;           // local memory pointer
+           header.s.addr = core + 1;
+        }
+    }
+    return cvmx_dma_engine_transfer(engine, header, cvmx_ptr_to_phys(source),
+                                    cvmx_ptr_to_phys(dest), length);
+}
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-dpi-defs.h b/sys/contrib/octeon-sdk/cvmx-dpi-defs.h
index 564f9b0..00198a4 100644
--- a/sys/contrib/octeon-sdk/cvmx-dpi-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-dpi-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,14 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_DPI_TYPEDEFS_H__
-#define __CVMX_DPI_TYPEDEFS_H__
+#ifndef __CVMX_DPI_DEFS_H__
+#define __CVMX_DPI_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_DPI_BIST_STATUS CVMX_DPI_BIST_STATUS_FUNC()
 static inline uint64_t CVMX_DPI_BIST_STATUS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_DPI_BIST_STATUS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001DF0000000000ull);
 }
@@ -67,7 +67,7 @@ static inline uint64_t CVMX_DPI_BIST_STATUS_FUNC(void)
 #define CVMX_DPI_CTL CVMX_DPI_CTL_FUNC()
 static inline uint64_t CVMX_DPI_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_DPI_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001DF0000000040ull);
 }
@@ -78,7 +78,11 @@ static inline uint64_t CVMX_DPI_CTL_FUNC(void)
 static inline uint64_t CVMX_DPI_DMAX_COUNTS(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_DPI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8;
 }
@@ -89,7 +93,11 @@ static inline uint64_t CVMX_DPI_DMAX_COUNTS(unsigned long offset)
 static inline uint64_t CVMX_DPI_DMAX_DBELL(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_DPI_DMAX_DBELL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8;
 }
@@ -97,10 +105,28 @@ static inline uint64_t CVMX_DPI_DMAX_DBELL(unsigned long offset)
 #define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_DPI_DMAX_ERR_RSP_STATUS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_DPI_DMAX_ERR_RSP_STATUS(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_DPI_DMAX_IBUFF_SADDR(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_DPI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8;
 }
@@ -108,10 +134,28 @@ static inline uint64_t CVMX_DPI_DMAX_IBUFF_SADDR(unsigned long offset)
 #define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_DPI_DMAX_IFLIGHT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_DPI_DMAX_IFLIGHT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_DPI_DMAX_NADDR(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_DPI_DMAX_NADDR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8;
 }
@@ -122,7 +166,11 @@ static inline uint64_t CVMX_DPI_DMAX_NADDR(unsigned long offset)
 static inline uint64_t CVMX_DPI_DMAX_REQBNK0(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_DPI_DMAX_REQBNK0(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8;
 }
@@ -133,7 +181,11 @@ static inline uint64_t CVMX_DPI_DMAX_REQBNK0(unsigned long offset)
 static inline uint64_t CVMX_DPI_DMAX_REQBNK1(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_DPI_DMAX_REQBNK1(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8;
 }
@@ -144,7 +196,7 @@ static inline uint64_t CVMX_DPI_DMAX_REQBNK1(unsigned long offset)
 #define CVMX_DPI_DMA_CONTROL CVMX_DPI_DMA_CONTROL_FUNC()
 static inline uint64_t CVMX_DPI_DMA_CONTROL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_DPI_DMA_CONTROL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001DF0000000048ull);
 }
@@ -155,7 +207,11 @@ static inline uint64_t CVMX_DPI_DMA_CONTROL_FUNC(void)
 static inline uint64_t CVMX_DPI_DMA_ENGX_EN(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 5)))))
 		cvmx_warn("CVMX_DPI_DMA_ENGX_EN(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8;
 }
@@ -163,10 +219,27 @@ static inline uint64_t CVMX_DPI_DMA_ENGX_EN(unsigned long offset)
 #define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_DPI_DMA_PPX_CNT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_DPI_DMA_PPX_CNT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8;
+}
+#else
+#define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_DPI_ENGX_BUF(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 5)))))
 		cvmx_warn("CVMX_DPI_ENGX_BUF(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8;
 }
@@ -177,7 +250,7 @@ static inline uint64_t CVMX_DPI_ENGX_BUF(unsigned long offset)
 #define CVMX_DPI_INFO_REG CVMX_DPI_INFO_REG_FUNC()
 static inline uint64_t CVMX_DPI_INFO_REG_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_DPI_INFO_REG not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001DF0000000980ull);
 }
@@ -188,7 +261,7 @@ static inline uint64_t CVMX_DPI_INFO_REG_FUNC(void)
 #define CVMX_DPI_INT_EN CVMX_DPI_INT_EN_FUNC()
 static inline uint64_t CVMX_DPI_INT_EN_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_DPI_INT_EN not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001DF0000000010ull);
 }
@@ -199,7 +272,7 @@ static inline uint64_t CVMX_DPI_INT_EN_FUNC(void)
 #define CVMX_DPI_INT_REG CVMX_DPI_INT_REG_FUNC()
 static inline uint64_t CVMX_DPI_INT_REG_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_DPI_INT_REG not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001DF0000000008ull);
 }
@@ -207,10 +280,24 @@ static inline uint64_t CVMX_DPI_INT_REG_FUNC(void)
 #define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_DPI_NCBX_CFG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_DPI_NCBX_CFG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001DF0000000800ull);
+}
+#else
+#define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_DPI_PINT_INFO CVMX_DPI_PINT_INFO_FUNC()
 static inline uint64_t CVMX_DPI_PINT_INFO_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_DPI_PINT_INFO not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001DF0000000830ull);
 }
@@ -221,7 +308,7 @@ static inline uint64_t CVMX_DPI_PINT_INFO_FUNC(void)
 #define CVMX_DPI_PKT_ERR_RSP CVMX_DPI_PKT_ERR_RSP_FUNC()
 static inline uint64_t CVMX_DPI_PKT_ERR_RSP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_DPI_PKT_ERR_RSP not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001DF0000000078ull);
 }
@@ -232,7 +319,7 @@ static inline uint64_t CVMX_DPI_PKT_ERR_RSP_FUNC(void)
 #define CVMX_DPI_REQ_ERR_RSP CVMX_DPI_REQ_ERR_RSP_FUNC()
 static inline uint64_t CVMX_DPI_REQ_ERR_RSP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_DPI_REQ_ERR_RSP not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001DF0000000058ull);
 }
@@ -243,7 +330,7 @@ static inline uint64_t CVMX_DPI_REQ_ERR_RSP_FUNC(void)
 #define CVMX_DPI_REQ_ERR_RSP_EN CVMX_DPI_REQ_ERR_RSP_EN_FUNC()
 static inline uint64_t CVMX_DPI_REQ_ERR_RSP_EN_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_DPI_REQ_ERR_RSP_EN not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001DF0000000068ull);
 }
@@ -254,7 +341,7 @@ static inline uint64_t CVMX_DPI_REQ_ERR_RSP_EN_FUNC(void)
 #define CVMX_DPI_REQ_ERR_RST CVMX_DPI_REQ_ERR_RST_FUNC()
 static inline uint64_t CVMX_DPI_REQ_ERR_RST_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_DPI_REQ_ERR_RST not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001DF0000000060ull);
 }
@@ -265,7 +352,7 @@ static inline uint64_t CVMX_DPI_REQ_ERR_RST_FUNC(void)
 #define CVMX_DPI_REQ_ERR_RST_EN CVMX_DPI_REQ_ERR_RST_EN_FUNC()
 static inline uint64_t CVMX_DPI_REQ_ERR_RST_EN_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_DPI_REQ_ERR_RST_EN not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001DF0000000070ull);
 }
@@ -273,10 +360,21 @@ static inline uint64_t CVMX_DPI_REQ_ERR_RST_EN_FUNC(void)
 #define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DPI_REQ_ERR_SKIP_COMP CVMX_DPI_REQ_ERR_SKIP_COMP_FUNC()
+static inline uint64_t CVMX_DPI_REQ_ERR_SKIP_COMP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_DPI_REQ_ERR_SKIP_COMP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001DF0000000838ull);
+}
+#else
+#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_DPI_REQ_GBL_EN CVMX_DPI_REQ_GBL_EN_FUNC()
 static inline uint64_t CVMX_DPI_REQ_GBL_EN_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_DPI_REQ_GBL_EN not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001DF0000000050ull);
 }
@@ -287,45 +385,90 @@ static inline uint64_t CVMX_DPI_REQ_GBL_EN_FUNC(void)
 static inline uint64_t CVMX_DPI_SLI_PRTX_CFG(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_DPI_SLI_PRTX_CFG(%lu) is invalid on this chip\n", offset);
-	return CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 1) * 8;
+	return CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8;
 }
 #else
-#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 1) * 8)
+#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
 #endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
-		cvmx_warn("CVMX_DPI_SLI_PRTX_ERR(%lu) is invalid on this chip\n", offset);
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 3))
+				return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 3) * 8;
+			break;
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+
+			if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1))
+			if ((offset <= 1))
+				return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + ((offset) & 1) * 8;
+			if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2))
+			if ((offset <= 1))
+				return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 1) * 8;			if ((offset <= 1))
+				return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 1) * 8;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 1))
+				return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + ((offset) & 1) * 8;
+			break;
+	}
+	cvmx_warn("CVMX_DPI_SLI_PRTX_ERR (offset = %lu) not supported on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 1) * 8;
 }
-#else
-#define CVMX_DPI_SLI_PRTX_ERR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 1) * 8)
-#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_DPI_SLI_PRTX_ERR_INFO(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_DPI_SLI_PRTX_ERR_INFO(%lu) is invalid on this chip\n", offset);
-	return CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 1) * 8;
+	return CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8;
 }
 #else
-#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 1) * 8)
+#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
 #endif
 
 /**
  * cvmx_dpi_bist_status
  */
-union cvmx_dpi_bist_status
-{
+union cvmx_dpi_bist_status {
 	uint64_t u64;
-	struct cvmx_dpi_bist_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_47_63               : 17;
+	uint64_t bist                         : 47; /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         BIST. */
+#else
+	uint64_t bist                         : 47;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} s;
+	struct cvmx_dpi_bist_status_s         cn61xx;
+	struct cvmx_dpi_bist_status_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_45_63               : 19;
+	uint64_t bist                         : 45; /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         BIST. */
+#else
+	uint64_t bist                         : 45;
+	uint64_t reserved_45_63               : 19;
+#endif
+	} cn63xx;
+	struct cvmx_dpi_bist_status_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_37_63               : 27;
 	uint64_t bist                         : 37; /**< BIST Results.
                                                          HW sets a bit in BIST for for memory that fails
@@ -334,21 +477,21 @@ union cvmx_dpi_bist_status
 	uint64_t bist                         : 37;
 	uint64_t reserved_37_63               : 27;
 #endif
-	} s;
-	struct cvmx_dpi_bist_status_s         cn63xx;
-	struct cvmx_dpi_bist_status_s         cn63xxp1;
+	} cn63xxp1;
+	struct cvmx_dpi_bist_status_s         cn66xx;
+	struct cvmx_dpi_bist_status_cn63xx    cn68xx;
+	struct cvmx_dpi_bist_status_cn63xx    cn68xxp1;
+	struct cvmx_dpi_bist_status_s         cnf71xx;
 };
 typedef union cvmx_dpi_bist_status cvmx_dpi_bist_status_t;
 
 /**
  * cvmx_dpi_ctl
  */
-union cvmx_dpi_ctl
-{
+union cvmx_dpi_ctl {
 	uint64_t u64;
-	struct cvmx_dpi_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t clk                          : 1;  /**< Status bit that indicates that the clks are running */
 	uint64_t en                           : 1;  /**< Turns on the DMA and Packet state machines */
@@ -358,8 +501,21 @@ union cvmx_dpi_ctl
 	uint64_t reserved_2_63                : 62;
 #endif
 	} s;
+	struct cvmx_dpi_ctl_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_1_63                : 63;
+	uint64_t en                           : 1;  /**< Turns on the DMA and Packet state machines */
+#else
+	uint64_t en                           : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} cn61xx;
 	struct cvmx_dpi_ctl_s                 cn63xx;
 	struct cvmx_dpi_ctl_s                 cn63xxp1;
+	struct cvmx_dpi_ctl_s                 cn66xx;
+	struct cvmx_dpi_ctl_s                 cn68xx;
+	struct cvmx_dpi_ctl_s                 cn68xxp1;
+	struct cvmx_dpi_ctl_cn61xx            cnf71xx;
 };
 typedef union cvmx_dpi_ctl cvmx_dpi_ctl_t;
 
@@ -370,12 +526,10 @@ typedef union cvmx_dpi_ctl cvmx_dpi_ctl_t;
  *
  * Values for determing the number of instructions for DMA[0..7] in the DPI.
  */
-union cvmx_dpi_dmax_counts
-{
+union cvmx_dpi_dmax_counts {
 	uint64_t u64;
-	struct cvmx_dpi_dmax_counts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_dmax_counts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_39_63               : 25;
 	uint64_t fcnt                         : 7;  /**< Number of words in the Instruction FIFO locally
                                                          cached within DPI. */
@@ -386,8 +540,13 @@ union cvmx_dpi_dmax_counts
 	uint64_t reserved_39_63               : 25;
 #endif
 	} s;
+	struct cvmx_dpi_dmax_counts_s         cn61xx;
 	struct cvmx_dpi_dmax_counts_s         cn63xx;
 	struct cvmx_dpi_dmax_counts_s         cn63xxp1;
+	struct cvmx_dpi_dmax_counts_s         cn66xx;
+	struct cvmx_dpi_dmax_counts_s         cn68xx;
+	struct cvmx_dpi_dmax_counts_s         cn68xxp1;
+	struct cvmx_dpi_dmax_counts_s         cnf71xx;
 };
 typedef union cvmx_dpi_dmax_counts cvmx_dpi_dmax_counts_t;
 
@@ -398,12 +557,10 @@ typedef union cvmx_dpi_dmax_counts cvmx_dpi_dmax_counts_t;
  *
  * The door bell register for DMA[0..7] queue.
  */
-union cvmx_dpi_dmax_dbell
-{
+union cvmx_dpi_dmax_dbell {
 	uint64_t u64;
-	struct cvmx_dpi_dmax_dbell_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_dmax_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t dbell                        : 16; /**< The value written to this register is added to the
                                                          number of 8byte words to be read and processes for
@@ -413,24 +570,83 @@ union cvmx_dpi_dmax_dbell
 	uint64_t reserved_16_63               : 48;
 #endif
 	} s;
+	struct cvmx_dpi_dmax_dbell_s          cn61xx;
 	struct cvmx_dpi_dmax_dbell_s          cn63xx;
 	struct cvmx_dpi_dmax_dbell_s          cn63xxp1;
+	struct cvmx_dpi_dmax_dbell_s          cn66xx;
+	struct cvmx_dpi_dmax_dbell_s          cn68xx;
+	struct cvmx_dpi_dmax_dbell_s          cn68xxp1;
+	struct cvmx_dpi_dmax_dbell_s          cnf71xx;
 };
 typedef union cvmx_dpi_dmax_dbell cvmx_dpi_dmax_dbell_t;
 
 /**
+ * cvmx_dpi_dma#_err_rsp_status
+ */
+union cvmx_dpi_dmax_err_rsp_status {
+	uint64_t u64;
+	struct cvmx_dpi_dmax_err_rsp_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_6_63                : 58;
+	uint64_t status                       : 6;  /**< QUE captures the ErrorResponse status of the last
+                                                         6 instructions for each instruction queue.
+                                                         STATUS<5> represents the status for first
+                                                         instruction in instruction order while STATUS<0>
+                                                         represents the last or most recent instruction.
+                                                         If STATUS<n> is set, then the nth instruction in
+                                                         the given queue experienced an ErrorResponse.
+                                                         Otherwise, it completed normally. */
+#else
+	uint64_t status                       : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_dpi_dmax_err_rsp_status_s cn61xx;
+	struct cvmx_dpi_dmax_err_rsp_status_s cn66xx;
+	struct cvmx_dpi_dmax_err_rsp_status_s cn68xx;
+	struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;
+	struct cvmx_dpi_dmax_err_rsp_status_s cnf71xx;
+};
+typedef union cvmx_dpi_dmax_err_rsp_status cvmx_dpi_dmax_err_rsp_status_t;
+
+/**
  * cvmx_dpi_dma#_ibuff_saddr
  *
  * DPI_DMA[0..7]_IBUFF_SADDR = DMA Instruction Buffer Starting Address
  *
  * The address to start reading Instructions from for DMA[0..7].
  */
-union cvmx_dpi_dmax_ibuff_saddr
-{
+union cvmx_dpi_dmax_ibuff_saddr {
 	uint64_t u64;
-	struct cvmx_dpi_dmax_ibuff_saddr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_dmax_ibuff_saddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_62_63               : 2;
+	uint64_t csize                        : 14; /**< The size in 8B words of the DMA Instruction Chunk.
+                                                         This value should only be written at known times
+                                                         in order to prevent corruption of the instruction
+                                                         queue.  The minimum CSIZE is 16 (one cacheblock). */
+	uint64_t reserved_41_47               : 7;
+	uint64_t idle                         : 1;  /**< DMA Request Queue is IDLE */
+	uint64_t saddr                        : 33; /**< The 128 byte aligned starting or chunk address.
+                                                         SADDR is address bit 35:7 of the starting
+                                                         instructions address. When new chunks are fetched
+                                                         by the HW, SADDR will be updated to reflect the
+                                                         address of the current chunk.
+                                                         A write to SADDR resets both the queue's doorbell
+                                                         (DPI_DMAx_COUNTS[DBELL) and its tail pointer
+                                                         (DPI_DMAx_NADDR[ADDR]). */
+	uint64_t reserved_0_6                 : 7;
+#else
+	uint64_t reserved_0_6                 : 7;
+	uint64_t saddr                        : 33;
+	uint64_t idle                         : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t csize                        : 14;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} s;
+	struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_62_63               : 2;
 	uint64_t csize                        : 14; /**< The size in 8B words of the DMA Instruction Chunk.
                                                          This value should only be written at known times
@@ -457,25 +673,61 @@ union cvmx_dpi_dmax_ibuff_saddr
 	uint64_t csize                        : 14;
 	uint64_t reserved_62_63               : 2;
 #endif
-	} s;
-	struct cvmx_dpi_dmax_ibuff_saddr_s    cn63xx;
-	struct cvmx_dpi_dmax_ibuff_saddr_s    cn63xxp1;
+	} cn61xx;
+	struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;
+	struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;
+	struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;
+	struct cvmx_dpi_dmax_ibuff_saddr_s    cn68xx;
+	struct cvmx_dpi_dmax_ibuff_saddr_s    cn68xxp1;
+	struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cnf71xx;
 };
 typedef union cvmx_dpi_dmax_ibuff_saddr cvmx_dpi_dmax_ibuff_saddr_t;
 
 /**
+ * cvmx_dpi_dma#_iflight
+ */
+union cvmx_dpi_dmax_iflight {
+	uint64_t u64;
+	struct cvmx_dpi_dmax_iflight_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_3_63                : 61;
+	uint64_t cnt                          : 3;  /**< The number of instructions from a given queue that
+                                                         can be inflight to the DMA engines at a time.
+                                                         Reset value matches the number of DMA engines. */
+#else
+	uint64_t cnt                          : 3;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_dpi_dmax_iflight_s        cn61xx;
+	struct cvmx_dpi_dmax_iflight_s        cn66xx;
+	struct cvmx_dpi_dmax_iflight_s        cn68xx;
+	struct cvmx_dpi_dmax_iflight_s        cn68xxp1;
+	struct cvmx_dpi_dmax_iflight_s        cnf71xx;
+};
+typedef union cvmx_dpi_dmax_iflight cvmx_dpi_dmax_iflight_t;
+
+/**
  * cvmx_dpi_dma#_naddr
  *
  * DPI_DMA[0..7]_NADDR = DMA Next Ichunk Address
  *
  * Place DPI will read the next Ichunk data from.
  */
-union cvmx_dpi_dmax_naddr
-{
+union cvmx_dpi_dmax_naddr {
 	uint64_t u64;
-	struct cvmx_dpi_dmax_naddr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_dmax_naddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_40_63               : 24;
+	uint64_t addr                         : 40; /**< The next L2C address to read DMA# instructions
+                                                         from. */
+#else
+	uint64_t addr                         : 40;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} s;
+	struct cvmx_dpi_dmax_naddr_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t addr                         : 36; /**< The next L2C address to read DMA# instructions
                                                          from. */
@@ -483,9 +735,13 @@ union cvmx_dpi_dmax_naddr
 	uint64_t addr                         : 36;
 	uint64_t reserved_36_63               : 28;
 #endif
-	} s;
-	struct cvmx_dpi_dmax_naddr_s          cn63xx;
-	struct cvmx_dpi_dmax_naddr_s          cn63xxp1;
+	} cn61xx;
+	struct cvmx_dpi_dmax_naddr_cn61xx     cn63xx;
+	struct cvmx_dpi_dmax_naddr_cn61xx     cn63xxp1;
+	struct cvmx_dpi_dmax_naddr_cn61xx     cn66xx;
+	struct cvmx_dpi_dmax_naddr_s          cn68xx;
+	struct cvmx_dpi_dmax_naddr_s          cn68xxp1;
+	struct cvmx_dpi_dmax_naddr_cn61xx     cnf71xx;
 };
 typedef union cvmx_dpi_dmax_naddr cvmx_dpi_dmax_naddr_t;
 
@@ -496,19 +752,22 @@ typedef union cvmx_dpi_dmax_naddr cvmx_dpi_dmax_naddr_t;
  *
  * Current contents of the request state machine - bank0
  */
-union cvmx_dpi_dmax_reqbnk0
-{
+union cvmx_dpi_dmax_reqbnk0 {
 	uint64_t u64;
-	struct cvmx_dpi_dmax_reqbnk0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_dmax_reqbnk0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t state                        : 64; /**< State */
 #else
 	uint64_t state                        : 64;
 #endif
 	} s;
+	struct cvmx_dpi_dmax_reqbnk0_s        cn61xx;
 	struct cvmx_dpi_dmax_reqbnk0_s        cn63xx;
 	struct cvmx_dpi_dmax_reqbnk0_s        cn63xxp1;
+	struct cvmx_dpi_dmax_reqbnk0_s        cn66xx;
+	struct cvmx_dpi_dmax_reqbnk0_s        cn68xx;
+	struct cvmx_dpi_dmax_reqbnk0_s        cn68xxp1;
+	struct cvmx_dpi_dmax_reqbnk0_s        cnf71xx;
 };
 typedef union cvmx_dpi_dmax_reqbnk0 cvmx_dpi_dmax_reqbnk0_t;
 
@@ -519,19 +778,22 @@ typedef union cvmx_dpi_dmax_reqbnk0 cvmx_dpi_dmax_reqbnk0_t;
  *
  * Current contents of the request state machine - bank1
  */
-union cvmx_dpi_dmax_reqbnk1
-{
+union cvmx_dpi_dmax_reqbnk1 {
 	uint64_t u64;
-	struct cvmx_dpi_dmax_reqbnk1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_dmax_reqbnk1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t state                        : 64; /**< State */
 #else
 	uint64_t state                        : 64;
 #endif
 	} s;
+	struct cvmx_dpi_dmax_reqbnk1_s        cn61xx;
 	struct cvmx_dpi_dmax_reqbnk1_s        cn63xx;
 	struct cvmx_dpi_dmax_reqbnk1_s        cn63xxp1;
+	struct cvmx_dpi_dmax_reqbnk1_s        cn66xx;
+	struct cvmx_dpi_dmax_reqbnk1_s        cn68xx;
+	struct cvmx_dpi_dmax_reqbnk1_s        cn68xxp1;
+	struct cvmx_dpi_dmax_reqbnk1_s        cnf71xx;
 };
 typedef union cvmx_dpi_dmax_reqbnk1 cvmx_dpi_dmax_reqbnk1_t;
 
@@ -542,12 +804,112 @@ typedef union cvmx_dpi_dmax_reqbnk1 cvmx_dpi_dmax_reqbnk1_t;
  *
  * Controls operation of the DMA IN/OUT.
  */
-union cvmx_dpi_dma_control
-{
+union cvmx_dpi_dma_control {
 	uint64_t u64;
-	struct cvmx_dpi_dma_control_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_dma_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_62_63               : 2;
+	uint64_t dici_mode                    : 1;  /**< DMA Instruction Completion Interrupt Mode
+                                                         turns on mode to increment DPI_DMA_PPx_CNT
+                                                         counters. */
+	uint64_t pkt_en1                      : 1;  /**< Enables the 2nd packet interface.
+                                                         When the packet interface is enabled, engine 4
+                                                         is used for packets and is not available for DMA.
+                                                         The packet interfaces must be enabled in order.
+                                                         When PKT_EN1=1, then PKT_EN=1.
+                                                         When PKT_EN1=1, then DMA_ENB<4>=0. */
+	uint64_t ffp_dis                      : 1;  /**< Force forward progress disable
+                                                         The DMA engines will compete for shared resources.
+                                                         If the HW detects that particular engines are not
+                                                         able to make requests to an interface, the HW
+                                                         will periodically trade-off throughput for
+                                                         fairness. */
+	uint64_t commit_mode                  : 1;  /**< DMA Engine Commit Mode
+
+                                                         When COMMIT_MODE=0, DPI considers an instruction
+                                                         complete when the HW internally generates the
+                                                         final write for the current instruction.
+
+                                                         When COMMIT_MODE=1, DPI additionally waits for
+                                                         the final write to reach the interface coherency
+                                                         point to declare the instructions complete.
+
+                                                         Please note: when COMMIT_MODE == 0, DPI may not
+                                                         follow the HRM ordering rules.
+
+                                                         DPI hardware performance may be better with
+                                                         COMMIT_MODE == 0 than with COMMIT_MODE == 1 due
+                                                         to the relaxed ordering rules.
+
+                                                         If the HRM ordering rules are required, set
+                                                         COMMIT_MODE == 1. */
+	uint64_t pkt_hp                       : 1;  /**< High-Priority Mode for Packet Interface.
+                                                         This mode has been deprecated. */
+	uint64_t pkt_en                       : 1;  /**< Enables 1st the packet interface.
+                                                         When the packet interface is enabled, engine 5
+                                                         is used for packets and is not available for DMA.
+                                                         When PKT_EN=1, then DMA_ENB<5>=0.
+                                                         When PKT_EN1=1, then PKT_EN=1. */
+	uint64_t reserved_54_55               : 2;
+	uint64_t dma_enb                      : 6;  /**< DMA engine enable. Enables the operation of the
+                                                         DMA engine. After being enabled an engine should
+                                                         not be disabled while processing instructions.
+                                                         When PKT_EN=1,  then DMA_ENB<5>=0.
+                                                         When PKT_EN1=1, then DMA_ENB<4>=0. */
+	uint64_t reserved_34_47               : 14;
+	uint64_t b0_lend                      : 1;  /**< When set '1' and the DPI is in the mode to write
+                                                         0 to L2C memory when a DMA is done, the address
+                                                         to be written to will be treated as a Little
+                                                         Endian address. */
+	uint64_t dwb_denb                     : 1;  /**< When set '1', DPI will send a value in the DWB
+                                                         field for a free page operation for the memory
+                                                         that contained the data. */
+	uint64_t dwb_ichk                     : 9;  /**< When Instruction Chunks for DMA operations are
+                                                         freed this value is used for the DWB field of the
+                                                         operation. */
+	uint64_t fpa_que                      : 3;  /**< The FPA queue that the instruction-chunk page will
+                                                         be returned to when used. */
+	uint64_t o_add1                       : 1;  /**< When set '1' 1 will be added to the SLI_DMAX_CNT
+                                                         DMA counters, if '0' then the number of bytes
+                                                         in the dma transfer will be added to the
+                                                         SLI_DMAX_CNT count register. */
+	uint64_t o_ro                         : 1;  /**< Relaxed Ordering Mode for DMA. */
+	uint64_t o_ns                         : 1;  /**< Nosnoop For DMA. */
+	uint64_t o_es                         : 2;  /**< Endian Swap Mode for DMA. */
+	uint64_t o_mode                       : 1;  /**< Select PCI_POINTER MODE to be used.
+                                                         0=DPTR format 1 is used
+                                                           use register values for address and pointer
+                                                           values for ES, NS, RO
+                                                         1=DPTR format 0 is used
+                                                           use pointer values for address and register
+                                                           values for ES, NS, RO */
+	uint64_t reserved_0_13                : 14;
+#else
+	uint64_t reserved_0_13                : 14;
+	uint64_t o_mode                       : 1;
+	uint64_t o_es                         : 2;
+	uint64_t o_ns                         : 1;
+	uint64_t o_ro                         : 1;
+	uint64_t o_add1                       : 1;
+	uint64_t fpa_que                      : 3;
+	uint64_t dwb_ichk                     : 9;
+	uint64_t dwb_denb                     : 1;
+	uint64_t b0_lend                      : 1;
+	uint64_t reserved_34_47               : 14;
+	uint64_t dma_enb                      : 6;
+	uint64_t reserved_54_55               : 2;
+	uint64_t pkt_en                       : 1;
+	uint64_t pkt_hp                       : 1;
+	uint64_t commit_mode                  : 1;
+	uint64_t ffp_dis                      : 1;
+	uint64_t pkt_en1                      : 1;
+	uint64_t dici_mode                    : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} s;
+	struct cvmx_dpi_dma_control_s         cn61xx;
+	struct cvmx_dpi_dma_control_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_61_63               : 3;
 	uint64_t pkt_en1                      : 1;  /**< Enables the 2nd packet interface.
                                                          When the packet interface is enabled, engine 4
@@ -581,19 +943,18 @@ union cvmx_dpi_dma_control
                                                          If the HRM ordering rules are required, set
                                                          COMMIT_MODE == 1. */
 	uint64_t pkt_hp                       : 1;  /**< High-Priority Mode for Packet Interface.
-                                                         Engine 5 will be serviced more frequently to
-                                                         deliver more bandwidth to packet interface.
-                                                         When PKT_EN=0, then PKT_HP=0. */
-	uint64_t pkt_en                       : 1;  /**< Enables the packet interface.
+                                                         This mode has been deprecated. */
+	uint64_t pkt_en                       : 1;  /**< Enables 1st the packet interface.
                                                          When the packet interface is enabled, engine 5
                                                          is used for packets and is not available for DMA.
                                                          When PKT_EN=1, then DMA_ENB<5>=0.
-                                                         When PKT_EN=0, then PKT_HP=0. */
+                                                         When PKT_EN1=1, then PKT_EN=1. */
 	uint64_t reserved_54_55               : 2;
 	uint64_t dma_enb                      : 6;  /**< DMA engine enable. Enables the operation of the
                                                          DMA engine. After being enabled an engine should
                                                          not be disabled while processing instructions.
-                                                         When PKT_EN=1, then DMA_ENB<5>=0. */
+                                                         When PKT_EN=1,  then DMA_ENB<5>=0.
+                                                         When PKT_EN1=1, then DMA_ENB<4>=0. */
 	uint64_t reserved_34_47               : 14;
 	uint64_t b0_lend                      : 1;  /**< When set '1' and the DPI is in the mode to write
                                                          0 to L2C memory when a DMA is done, the address
@@ -642,11 +1003,9 @@ union cvmx_dpi_dma_control
 	uint64_t pkt_en1                      : 1;
 	uint64_t reserved_61_63               : 3;
 #endif
-	} s;
-	struct cvmx_dpi_dma_control_s         cn63xx;
-	struct cvmx_dpi_dma_control_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	} cn63xx;
+	struct cvmx_dpi_dma_control_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_59_63               : 5;
 	uint64_t commit_mode                  : 1;  /**< DMA Engine Commit Mode
 
@@ -728,47 +1087,112 @@ union cvmx_dpi_dma_control
 	uint64_t reserved_59_63               : 5;
 #endif
 	} cn63xxp1;
+	struct cvmx_dpi_dma_control_cn63xx    cn66xx;
+	struct cvmx_dpi_dma_control_s         cn68xx;
+	struct cvmx_dpi_dma_control_cn63xx    cn68xxp1;
+	struct cvmx_dpi_dma_control_s         cnf71xx;
 };
 typedef union cvmx_dpi_dma_control cvmx_dpi_dma_control_t;
 
 /**
  * cvmx_dpi_dma_eng#_en
  */
-union cvmx_dpi_dma_engx_en
-{
+union cvmx_dpi_dma_engx_en {
 	uint64_t u64;
-	struct cvmx_dpi_dma_engx_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_dma_engx_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t qen                          : 8;  /**< Controls which logical instruction queues can be
                                                          serviced by the DMA engine. Setting QEN==0
                                                          effectively disables the engine.
                                                          When DPI_DMA_CONTROL[PKT_EN] = 1, then
-                                                         DPI_DMA_ENG5_EN[QEN] must be zero. */
+                                                         DPI_DMA_ENG5_EN[QEN] must be zero.
+                                                         When DPI_DMA_CONTROL[PKT_EN1] = 1, then
+                                                         DPI_DMA_ENG4_EN[QEN] must be zero. */
 #else
 	uint64_t qen                          : 8;
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
+	struct cvmx_dpi_dma_engx_en_s         cn61xx;
 	struct cvmx_dpi_dma_engx_en_s         cn63xx;
 	struct cvmx_dpi_dma_engx_en_s         cn63xxp1;
+	struct cvmx_dpi_dma_engx_en_s         cn66xx;
+	struct cvmx_dpi_dma_engx_en_s         cn68xx;
+	struct cvmx_dpi_dma_engx_en_s         cn68xxp1;
+	struct cvmx_dpi_dma_engx_en_s         cnf71xx;
 };
 typedef union cvmx_dpi_dma_engx_en cvmx_dpi_dma_engx_en_t;
 
 /**
+ * cvmx_dpi_dma_pp#_cnt
+ *
+ * DPI_DMA_PP[0..3]_CNT  = DMA per PP Instr Done Counter
+ *
+ * When DMA Instruction Completion Interrupt Mode DPI_DMA_CONTROL.DICI_MODE is enabled, every dma instruction
+ * that has the WQP=0 and a PTR value of 1..4 will incremrement DPI_DMA_PPx_CNT value-1 counter.
+ * Instructions with WQP=0 and PTR values higher then 0x3F will still send a zero byte write.
+ * Hardware reserves that values 5..63 for future use and will treat them as a PTR of 0 and do nothing.
+ */
+union cvmx_dpi_dma_ppx_cnt {
+	uint64_t u64;
+	struct cvmx_dpi_dma_ppx_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t cnt                          : 16; /**< Counter incremented according to conditions
+                                                         described above and decremented by values written
+                                                         to this field.  A CNT of non zero, will cause
+                                                         an interrupt in the CIU_SUM1_PPX_IPX register */
+#else
+	uint64_t cnt                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_dpi_dma_ppx_cnt_s         cn61xx;
+	struct cvmx_dpi_dma_ppx_cnt_s         cn68xx;
+	struct cvmx_dpi_dma_ppx_cnt_s         cnf71xx;
+};
+typedef union cvmx_dpi_dma_ppx_cnt cvmx_dpi_dma_ppx_cnt_t;
+
+/**
  * cvmx_dpi_eng#_buf
  *
  * Notes:
  * The total amount of storage allocated to the 6 DPI DMA engines (via DPI_ENG*_BUF[BLKS]) must not exceed 8KB.
  *
  */
-union cvmx_dpi_engx_buf
-{
+union cvmx_dpi_engx_buf {
 	uint64_t u64;
-	struct cvmx_dpi_engx_buf_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_engx_buf_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_37_63               : 27;
+	uint64_t compblks                     : 5;  /**< Computed engine block size */
+	uint64_t reserved_9_31                : 23;
+	uint64_t base                         : 5;  /**< The base address in 512B blocks of the engine fifo */
+	uint64_t blks                         : 4;  /**< The size of the engine fifo
+                                                         Legal values are 0-10.
+                                                         0  = Engine is disabled
+                                                         1  = 0.5KB buffer
+                                                         2  = 1.0KB buffer
+                                                         3  = 1.5KB buffer
+                                                         4  = 2.0KB buffer
+                                                         5  = 2.5KB buffer
+                                                         6  = 3.0KB buffer
+                                                         7  = 3.5KB buffer
+                                                         8  = 4.0KB buffer
+                                                         9  = 6.0KB buffer
+                                                         10 = 8.0KB buffer */
+#else
+	uint64_t blks                         : 4;
+	uint64_t base                         : 5;
+	uint64_t reserved_9_31                : 23;
+	uint64_t compblks                     : 5;
+	uint64_t reserved_37_63               : 27;
+#endif
+	} s;
+	struct cvmx_dpi_engx_buf_s            cn61xx;
+	struct cvmx_dpi_engx_buf_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t base                         : 4;  /**< The base address in 512B blocks of the engine fifo */
 	uint64_t blks                         : 4;  /**< The size in 512B blocks of the engine fifo
@@ -787,21 +1211,22 @@ union cvmx_dpi_engx_buf
 	uint64_t base                         : 4;
 	uint64_t reserved_8_63                : 56;
 #endif
-	} s;
-	struct cvmx_dpi_engx_buf_s            cn63xx;
-	struct cvmx_dpi_engx_buf_s            cn63xxp1;
+	} cn63xx;
+	struct cvmx_dpi_engx_buf_cn63xx       cn63xxp1;
+	struct cvmx_dpi_engx_buf_s            cn66xx;
+	struct cvmx_dpi_engx_buf_s            cn68xx;
+	struct cvmx_dpi_engx_buf_s            cn68xxp1;
+	struct cvmx_dpi_engx_buf_s            cnf71xx;
 };
 typedef union cvmx_dpi_engx_buf cvmx_dpi_engx_buf_t;
 
 /**
  * cvmx_dpi_info_reg
  */
-union cvmx_dpi_info_reg
-{
+union cvmx_dpi_info_reg {
 	uint64_t u64;
-	struct cvmx_dpi_info_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_info_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t ffp                          : 4;  /**< Force Forward Progress Indicator */
 	uint64_t reserved_2_3                 : 2;
@@ -821,10 +1246,10 @@ union cvmx_dpi_info_reg
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
+	struct cvmx_dpi_info_reg_s            cn61xx;
 	struct cvmx_dpi_info_reg_s            cn63xx;
-	struct cvmx_dpi_info_reg_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_info_reg_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t ncb                          : 1;  /**< NCB Register Access
                                                          This interrupt will fire in normal operation
@@ -840,18 +1265,68 @@ union cvmx_dpi_info_reg
 	uint64_t reserved_2_63                : 62;
 #endif
 	} cn63xxp1;
+	struct cvmx_dpi_info_reg_s            cn66xx;
+	struct cvmx_dpi_info_reg_s            cn68xx;
+	struct cvmx_dpi_info_reg_s            cn68xxp1;
+	struct cvmx_dpi_info_reg_s            cnf71xx;
 };
 typedef union cvmx_dpi_info_reg cvmx_dpi_info_reg_t;
 
 /**
  * cvmx_dpi_int_en
  */
-union cvmx_dpi_int_en
-{
+union cvmx_dpi_int_en {
 	uint64_t u64;
-	struct cvmx_dpi_int_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_28_63               : 36;
+	uint64_t sprt3_rst                    : 1;  /**< DMA instruction was dropped because the source or
+                                                          destination port was in reset.
+                                                         this bit is set. */
+	uint64_t sprt2_rst                    : 1;  /**< DMA instruction was dropped because the source or
+                                                          destination port was in reset.
+                                                         this bit is set. */
+	uint64_t sprt1_rst                    : 1;  /**< DMA instruction was dropped because the source or
+                                                          destination port was in reset.
+                                                         this bit is set. */
+	uint64_t sprt0_rst                    : 1;  /**< DMA instruction was dropped because the source or
+                                                          destination port was in reset.
+                                                         this bit is set. */
+	uint64_t reserved_23_23               : 1;
+	uint64_t req_badfil                   : 1;  /**< DMA instruction unexpected fill */
+	uint64_t req_inull                    : 1;  /**< DMA instruction filled with NULL pointer */
+	uint64_t req_anull                    : 1;  /**< DMA instruction filled with bad instruction */
+	uint64_t req_undflw                   : 1;  /**< DMA instruction FIFO underflow */
+	uint64_t req_ovrflw                   : 1;  /**< DMA instruction FIFO overflow */
+	uint64_t req_badlen                   : 1;  /**< DMA instruction fetch with length */
+	uint64_t req_badadr                   : 1;  /**< DMA instruction fetch with bad pointer */
+	uint64_t dmadbo                       : 8;  /**< DMAx doorbell overflow. */
+	uint64_t reserved_2_7                 : 6;
+	uint64_t nfovr                        : 1;  /**< CSR Fifo Overflow */
+	uint64_t nderr                        : 1;  /**< NCB Decode Error */
+#else
+	uint64_t nderr                        : 1;
+	uint64_t nfovr                        : 1;
+	uint64_t reserved_2_7                 : 6;
+	uint64_t dmadbo                       : 8;
+	uint64_t req_badadr                   : 1;
+	uint64_t req_badlen                   : 1;
+	uint64_t req_ovrflw                   : 1;
+	uint64_t req_undflw                   : 1;
+	uint64_t req_anull                    : 1;
+	uint64_t req_inull                    : 1;
+	uint64_t req_badfil                   : 1;
+	uint64_t reserved_23_23               : 1;
+	uint64_t sprt0_rst                    : 1;
+	uint64_t sprt1_rst                    : 1;
+	uint64_t sprt2_rst                    : 1;
+	uint64_t sprt3_rst                    : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} s;
+	struct cvmx_dpi_int_en_s              cn61xx;
+	struct cvmx_dpi_int_en_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_26_63               : 38;
 	uint64_t sprt1_rst                    : 1;  /**< DMA instruction was dropped because the source or
                                                           destination port was in reset.
@@ -888,21 +1363,89 @@ union cvmx_dpi_int_en
 	uint64_t sprt1_rst                    : 1;
 	uint64_t reserved_26_63               : 38;
 #endif
-	} s;
-	struct cvmx_dpi_int_en_s              cn63xx;
-	struct cvmx_dpi_int_en_s              cn63xxp1;
+	} cn63xx;
+	struct cvmx_dpi_int_en_cn63xx         cn63xxp1;
+	struct cvmx_dpi_int_en_s              cn66xx;
+	struct cvmx_dpi_int_en_cn63xx         cn68xx;
+	struct cvmx_dpi_int_en_cn63xx         cn68xxp1;
+	struct cvmx_dpi_int_en_s              cnf71xx;
 };
 typedef union cvmx_dpi_int_en cvmx_dpi_int_en_t;
 
 /**
  * cvmx_dpi_int_reg
  */
-union cvmx_dpi_int_reg
-{
+union cvmx_dpi_int_reg {
 	uint64_t u64;
-	struct cvmx_dpi_int_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_28_63               : 36;
+	uint64_t sprt3_rst                    : 1;  /**< DMA instruction was dropped because the source or
+                                                          destination port was in reset.
+                                                         this bit is set. */
+	uint64_t sprt2_rst                    : 1;  /**< DMA instruction was dropped because the source or
+                                                          destination port was in reset.
+                                                         this bit is set. */
+	uint64_t sprt1_rst                    : 1;  /**< DMA instruction was dropped because the source or
+                                                          destination port was in reset.
+                                                         this bit is set. */
+	uint64_t sprt0_rst                    : 1;  /**< DMA instruction was dropped because the source or
+                                                          destination port was in reset.
+                                                         this bit is set. */
+	uint64_t reserved_23_23               : 1;
+	uint64_t req_badfil                   : 1;  /**< DMA instruction unexpected fill
+                                                         Instruction fill when none outstanding. */
+	uint64_t req_inull                    : 1;  /**< DMA instruction filled with NULL pointer
+                                                         Next pointer was NULL. */
+	uint64_t req_anull                    : 1;  /**< DMA instruction filled with bad instruction
+                                                         Fetched instruction word was 0. */
+	uint64_t req_undflw                   : 1;  /**< DMA instruction FIFO underflow
+                                                         DPI tracks outstanding instructions fetches.
+                                                         Interrupt will fire when FIFO underflows. */
+	uint64_t req_ovrflw                   : 1;  /**< DMA instruction FIFO overflow
+                                                         DPI tracks outstanding instructions fetches.
+                                                         Interrupt will fire when FIFO overflows. */
+	uint64_t req_badlen                   : 1;  /**< DMA instruction fetch with length
+                                                         Interrupt will fire if DPI forms an instruction
+                                                         fetch with length of zero. */
+	uint64_t req_badadr                   : 1;  /**< DMA instruction fetch with bad pointer
+                                                         Interrupt will fire if DPI forms an instruction
+                                                         fetch to the NULL pointer. */
+	uint64_t dmadbo                       : 8;  /**< DMAx doorbell overflow.
+                                                         DPI has a 32-bit counter for each request's queue
+                                                         outstanding doorbell counts. Interrupt will fire
+                                                         if the count overflows. */
+	uint64_t reserved_2_7                 : 6;
+	uint64_t nfovr                        : 1;  /**< CSR Fifo Overflow
+                                                         DPI can store upto 16 CSR request.  The FIFO will
+                                                         overflow if that number is exceeded. */
+	uint64_t nderr                        : 1;  /**< NCB Decode Error
+                                                         DPI received a NCB transaction on the outbound
+                                                         bus to the DPI deviceID, but the command was not
+                                                         recognized. */
+#else
+	uint64_t nderr                        : 1;
+	uint64_t nfovr                        : 1;
+	uint64_t reserved_2_7                 : 6;
+	uint64_t dmadbo                       : 8;
+	uint64_t req_badadr                   : 1;
+	uint64_t req_badlen                   : 1;
+	uint64_t req_ovrflw                   : 1;
+	uint64_t req_undflw                   : 1;
+	uint64_t req_anull                    : 1;
+	uint64_t req_inull                    : 1;
+	uint64_t req_badfil                   : 1;
+	uint64_t reserved_23_23               : 1;
+	uint64_t sprt0_rst                    : 1;
+	uint64_t sprt1_rst                    : 1;
+	uint64_t sprt2_rst                    : 1;
+	uint64_t sprt3_rst                    : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} s;
+	struct cvmx_dpi_int_reg_s             cn61xx;
+	struct cvmx_dpi_int_reg_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_26_63               : 38;
 	uint64_t sprt1_rst                    : 1;  /**< DMA instruction was dropped because the source or
                                                           destination port was in reset.
@@ -958,25 +1501,52 @@ union cvmx_dpi_int_reg
 	uint64_t sprt1_rst                    : 1;
 	uint64_t reserved_26_63               : 38;
 #endif
-	} s;
-	struct cvmx_dpi_int_reg_s             cn63xx;
-	struct cvmx_dpi_int_reg_s             cn63xxp1;
+	} cn63xx;
+	struct cvmx_dpi_int_reg_cn63xx        cn63xxp1;
+	struct cvmx_dpi_int_reg_s             cn66xx;
+	struct cvmx_dpi_int_reg_cn63xx        cn68xx;
+	struct cvmx_dpi_int_reg_cn63xx        cn68xxp1;
+	struct cvmx_dpi_int_reg_s             cnf71xx;
 };
 typedef union cvmx_dpi_int_reg cvmx_dpi_int_reg_t;
 
 /**
+ * cvmx_dpi_ncb#_cfg
+ */
+union cvmx_dpi_ncbx_cfg {
+	uint64_t u64;
+	struct cvmx_dpi_ncbx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_6_63                : 58;
+	uint64_t molr                         : 6;  /**< Max Outstanding Load Requests
+                                                         Limits the number of oustanding load requests on
+                                                         the NCB interface.  This value can range from 1
+                                                         to 32. Setting a value of 0 will halt all read
+                                                         traffic to the NCB interface.  There are no
+                                                         restrictions on when this value can be changed. */
+#else
+	uint64_t molr                         : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_dpi_ncbx_cfg_s            cn61xx;
+	struct cvmx_dpi_ncbx_cfg_s            cn66xx;
+	struct cvmx_dpi_ncbx_cfg_s            cn68xx;
+	struct cvmx_dpi_ncbx_cfg_s            cnf71xx;
+};
+typedef union cvmx_dpi_ncbx_cfg cvmx_dpi_ncbx_cfg_t;
+
+/**
  * cvmx_dpi_pint_info
  *
  * DPI_PINT_INFO = DPI Packet Interrupt Info
  *
  * DPI Packet Interrupt Info.
  */
-union cvmx_dpi_pint_info
-{
+union cvmx_dpi_pint_info {
 	uint64_t u64;
-	struct cvmx_dpi_pint_info_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_pint_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t iinfo                        : 6;  /**< Packet Instruction Doorbell count overflow info */
 	uint64_t reserved_6_7                 : 2;
@@ -988,20 +1558,23 @@ union cvmx_dpi_pint_info
 	uint64_t reserved_14_63               : 50;
 #endif
 	} s;
+	struct cvmx_dpi_pint_info_s           cn61xx;
 	struct cvmx_dpi_pint_info_s           cn63xx;
 	struct cvmx_dpi_pint_info_s           cn63xxp1;
+	struct cvmx_dpi_pint_info_s           cn66xx;
+	struct cvmx_dpi_pint_info_s           cn68xx;
+	struct cvmx_dpi_pint_info_s           cn68xxp1;
+	struct cvmx_dpi_pint_info_s           cnf71xx;
 };
 typedef union cvmx_dpi_pint_info cvmx_dpi_pint_info_t;
 
 /**
  * cvmx_dpi_pkt_err_rsp
  */
-union cvmx_dpi_pkt_err_rsp
-{
+union cvmx_dpi_pkt_err_rsp {
 	uint64_t u64;
-	struct cvmx_dpi_pkt_err_rsp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_pkt_err_rsp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t pkterr                       : 1;  /**< Indicates that an ErrorResponse was received from
                                                          the I/O subsystem. */
@@ -1010,20 +1583,23 @@ union cvmx_dpi_pkt_err_rsp
 	uint64_t reserved_1_63                : 63;
 #endif
 	} s;
+	struct cvmx_dpi_pkt_err_rsp_s         cn61xx;
 	struct cvmx_dpi_pkt_err_rsp_s         cn63xx;
 	struct cvmx_dpi_pkt_err_rsp_s         cn63xxp1;
+	struct cvmx_dpi_pkt_err_rsp_s         cn66xx;
+	struct cvmx_dpi_pkt_err_rsp_s         cn68xx;
+	struct cvmx_dpi_pkt_err_rsp_s         cn68xxp1;
+	struct cvmx_dpi_pkt_err_rsp_s         cnf71xx;
 };
 typedef union cvmx_dpi_pkt_err_rsp cvmx_dpi_pkt_err_rsp_t;
 
 /**
  * cvmx_dpi_req_err_rsp
  */
-union cvmx_dpi_req_err_rsp
-{
+union cvmx_dpi_req_err_rsp {
 	uint64_t u64;
-	struct cvmx_dpi_req_err_rsp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_req_err_rsp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t qerr                         : 8;  /**< Indicates which instruction queue received an
                                                          ErrorResponse from the I/O subsystem.
@@ -1035,20 +1611,23 @@ union cvmx_dpi_req_err_rsp
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
+	struct cvmx_dpi_req_err_rsp_s         cn61xx;
 	struct cvmx_dpi_req_err_rsp_s         cn63xx;
 	struct cvmx_dpi_req_err_rsp_s         cn63xxp1;
+	struct cvmx_dpi_req_err_rsp_s         cn66xx;
+	struct cvmx_dpi_req_err_rsp_s         cn68xx;
+	struct cvmx_dpi_req_err_rsp_s         cn68xxp1;
+	struct cvmx_dpi_req_err_rsp_s         cnf71xx;
 };
 typedef union cvmx_dpi_req_err_rsp cvmx_dpi_req_err_rsp_t;
 
 /**
  * cvmx_dpi_req_err_rsp_en
  */
-union cvmx_dpi_req_err_rsp_en
-{
+union cvmx_dpi_req_err_rsp_en {
 	uint64_t u64;
-	struct cvmx_dpi_req_err_rsp_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_req_err_rsp_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t en                           : 8;  /**< Indicates which instruction queues should stop
                                                          dispatching instructions when an  ErrorResponse
@@ -1058,20 +1637,23 @@ union cvmx_dpi_req_err_rsp_en
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
+	struct cvmx_dpi_req_err_rsp_en_s      cn61xx;
 	struct cvmx_dpi_req_err_rsp_en_s      cn63xx;
 	struct cvmx_dpi_req_err_rsp_en_s      cn63xxp1;
+	struct cvmx_dpi_req_err_rsp_en_s      cn66xx;
+	struct cvmx_dpi_req_err_rsp_en_s      cn68xx;
+	struct cvmx_dpi_req_err_rsp_en_s      cn68xxp1;
+	struct cvmx_dpi_req_err_rsp_en_s      cnf71xx;
 };
 typedef union cvmx_dpi_req_err_rsp_en cvmx_dpi_req_err_rsp_en_t;
 
 /**
  * cvmx_dpi_req_err_rst
  */
-union cvmx_dpi_req_err_rst
-{
+union cvmx_dpi_req_err_rst {
 	uint64_t u64;
-	struct cvmx_dpi_req_err_rst_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_req_err_rst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t qerr                         : 8;  /**< Indicates which instruction queue dropped an
                                                          instruction because the source or destination
@@ -1084,20 +1666,23 @@ union cvmx_dpi_req_err_rst
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
+	struct cvmx_dpi_req_err_rst_s         cn61xx;
 	struct cvmx_dpi_req_err_rst_s         cn63xx;
 	struct cvmx_dpi_req_err_rst_s         cn63xxp1;
+	struct cvmx_dpi_req_err_rst_s         cn66xx;
+	struct cvmx_dpi_req_err_rst_s         cn68xx;
+	struct cvmx_dpi_req_err_rst_s         cn68xxp1;
+	struct cvmx_dpi_req_err_rst_s         cnf71xx;
 };
 typedef union cvmx_dpi_req_err_rst cvmx_dpi_req_err_rst_t;
 
 /**
  * cvmx_dpi_req_err_rst_en
  */
-union cvmx_dpi_req_err_rst_en
-{
+union cvmx_dpi_req_err_rst_en {
 	uint64_t u64;
-	struct cvmx_dpi_req_err_rst_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_req_err_rst_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t en                           : 8;  /**< Indicates which instruction queues should stop
                                                          dispatching instructions when an instruction
@@ -1108,20 +1693,63 @@ union cvmx_dpi_req_err_rst_en
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
+	struct cvmx_dpi_req_err_rst_en_s      cn61xx;
 	struct cvmx_dpi_req_err_rst_en_s      cn63xx;
 	struct cvmx_dpi_req_err_rst_en_s      cn63xxp1;
+	struct cvmx_dpi_req_err_rst_en_s      cn66xx;
+	struct cvmx_dpi_req_err_rst_en_s      cn68xx;
+	struct cvmx_dpi_req_err_rst_en_s      cn68xxp1;
+	struct cvmx_dpi_req_err_rst_en_s      cnf71xx;
 };
 typedef union cvmx_dpi_req_err_rst_en cvmx_dpi_req_err_rst_en_t;
 
 /**
+ * cvmx_dpi_req_err_skip_comp
+ */
+union cvmx_dpi_req_err_skip_comp {
+	uint64_t u64;
+	struct cvmx_dpi_req_err_skip_comp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_24_63               : 40;
+	uint64_t en_rst                       : 8;  /**< Indicates which instruction queue should skip the
+                                                         completion  phase once an port reset is
+                                                         detected as indicated by DPI_REQ_ERR_RST.  All
+                                                         completions to the effected instruction queue
+                                                         will be skipped as long as
+                                                         DPI_REQ_ERR_RSP[QERR<ique>] & EN_RSP<ique> or
+                                                         DPI_REQ_ERR_RST[QERR<ique>] & EN_RST<ique> are
+                                                         set. */
+	uint64_t reserved_8_15                : 8;
+	uint64_t en_rsp                       : 8;  /**< Indicates which instruction queue should skip the
+                                                         completion  phase once an ErrorResponse is
+                                                         detected as indicated by DPI_REQ_ERR_RSP.  All
+                                                         completions to the effected instruction queue
+                                                         will be skipped as long as
+                                                         DPI_REQ_ERR_RSP[QERR<ique>] & EN_RSP<ique> or
+                                                         DPI_REQ_ERR_RST[QERR<ique>] & EN_RST<ique> are
+                                                         set. */
+#else
+	uint64_t en_rsp                       : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t en_rst                       : 8;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_dpi_req_err_skip_comp_s   cn61xx;
+	struct cvmx_dpi_req_err_skip_comp_s   cn66xx;
+	struct cvmx_dpi_req_err_skip_comp_s   cn68xx;
+	struct cvmx_dpi_req_err_skip_comp_s   cn68xxp1;
+	struct cvmx_dpi_req_err_skip_comp_s   cnf71xx;
+};
+typedef union cvmx_dpi_req_err_skip_comp cvmx_dpi_req_err_skip_comp_t;
+
+/**
  * cvmx_dpi_req_gbl_en
  */
-union cvmx_dpi_req_gbl_en
-{
+union cvmx_dpi_req_gbl_en {
 	uint64_t u64;
-	struct cvmx_dpi_req_gbl_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_req_gbl_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t qen                          : 8;  /**< Indicates which instruction queues are enabled and
                                                          can dispatch instructions to a requesting engine. */
@@ -1130,8 +1758,13 @@ union cvmx_dpi_req_gbl_en
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
+	struct cvmx_dpi_req_gbl_en_s          cn61xx;
 	struct cvmx_dpi_req_gbl_en_s          cn63xx;
 	struct cvmx_dpi_req_gbl_en_s          cn63xxp1;
+	struct cvmx_dpi_req_gbl_en_s          cn66xx;
+	struct cvmx_dpi_req_gbl_en_s          cn68xx;
+	struct cvmx_dpi_req_gbl_en_s          cn68xxp1;
+	struct cvmx_dpi_req_gbl_en_s          cnf71xx;
 };
 typedef union cvmx_dpi_req_gbl_en cvmx_dpi_req_gbl_en_t;
 
@@ -1142,12 +1775,113 @@ typedef union cvmx_dpi_req_gbl_en cvmx_dpi_req_gbl_en_t;
  *
  * Configures the Max Read Request Size, Max Paylod Size, and Max Number of SLI Tags in use
  */
-union cvmx_dpi_sli_prtx_cfg
-{
+union cvmx_dpi_sli_prtx_cfg {
 	uint64_t u64;
-	struct cvmx_dpi_sli_prtx_cfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_sli_prtx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_25_63               : 39;
+	uint64_t halt                         : 1;  /**< When set, HALT indicates that the MAC has detected
+                                                         a reset condition. No further instructions that
+                                                         reference the MAC from any instruction Q will be
+                                                         issued until the MAC comes out of reset and HALT
+                                                         is cleared in SLI_CTL_PORTx[DIS_PORT]. */
+	uint64_t qlm_cfg                      : 4;  /**< QLM_CFG is a function of MIO_QLMx_CFG[QLM_CFG]
+                                                         QLM_CFG may contain values that are not normally
+                                                         used for DMA and/or packet operations.
+                                                         QLM_CFG does not indicate if a port is disabled.
+                                                         MIO_QLMx_CFG can be used for more complete QLM
+                                                         configuration information.
+                                                         0000 = MAC is PCIe 1x4 (QLM) or 1x2 (DLM)
+                                                         0001 = MAC is PCIe 2x1 (DLM only)
+                                                         0010 = MAC is SGMII
+                                                         0011 = MAC is XAUI
+                                                         all other encodings are RESERVED */
+	uint64_t reserved_17_19               : 3;
+	uint64_t rd_mode                      : 1;  /**< Read Mode
+                                                         0=Exact Read Mode
+                                                           If the port is a PCIe port, the HW reads on a
+                                                           4B granularity.  In this mode, the HW may break
+                                                           a given read into 3 operations to satisify
+                                                           PCIe rules.
+                                                           If the port is a SRIO port, the HW follows the
+                                                           SRIO read rules from the SRIO specification and
+                                                            only issues 32*n, 16, and 8 byte  operations
+                                                            on the SRIO bus.
+                                                         1=Block Mode
+                                                           The HW will read more data than requested in
+                                                           order to minimize the number of operations
+                                                           necessary to complete the operation.
+                                                           The memory region must be memory like. */
+	uint64_t reserved_14_15               : 2;
+	uint64_t molr                         : 6;  /**< Max Outstanding Load Requests
+                                                         Limits the number of oustanding load requests on
+                                                         the port by restricting the number of tags
+                                                         used by the SLI to track load responses.  This
+                                                         value can range from 1 to 32 depending on the MAC
+                                                         type and number of lanes.
+                                                         MAC == PCIe:           Max is 32
+                                                         MAC == sRio / 4 lanes: Max is 32
+                                                         MAC == sRio / 2 lanes: Max is 16
+                                                         MAC == sRio / 1 lane:  Max is  8
+                                                         Reset value is computed based on the MAC config.
+                                                         Setting MOLR to a value of 0 will halt all read
+                                                         traffic to the port.  There are no restrictions
+                                                         on when this value can be changed. */
+	uint64_t mps_lim                      : 1;  /**< MAC memory space write requests cannot cross the
+                                                         (naturally-aligned) MPS boundary.
+                                                         When clear, DPI is allowed to issue a MAC memory
+                                                         space read that crosses the naturally-aligned
+                                                         boundary of size defined by MPS. (DPI will still
+                                                         only cross the boundary when it would eliminate a
+                                                         write by doing so.)
+                                                         When set, DPI will never issue a MAC memory space
+                                                         write that crosses the naturally-aligned boundary
+                                                         of size defined by MPS. */
+	uint64_t reserved_5_6                 : 2;
+	uint64_t mps                          : 1;  /**< Max Payload Size
+                                                                 0 = 128B
+                                                                 1 = 256B
+                                                         For PCIe MACs, this MPS size must not exceed
+                                                               the size selected by PCIE*_CFG030[MPS].
+                                                         For sRIO MACs, all MPS values are allowed. */
+	uint64_t mrrs_lim                     : 1;  /**< MAC memory space read requests cannot cross the
+                                                         (naturally-aligned) MRRS boundary.
+                                                         When clear, DPI is allowed to issue a MAC memory
+                                                         space read that crosses the naturally-aligned
+                                                         boundary of size defined by MRRS. (DPI will still
+                                                         only cross the boundary when it would eliminate a
+                                                         read by doing so.)
+                                                         When set, DPI will never issue a MAC memory space
+                                                         read that crosses the naturally-aligned boundary
+                                                         of size defined by MRRS. */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t mrrs                         : 2;  /**< Max Read Request Size
+                                                                 0 = 128B
+                                                                 1 = 256B
+                                                                 2 = 512B
+                                                                 3 = 1024B
+                                                         For PCIe MACs, this MRRS size must not exceed
+                                                               the size selected by PCIE*_CFG030[MRRS].
+                                                         For sRIO MACs, this MRRS size must be <= 256B. */
+#else
+	uint64_t mrrs                         : 2;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t mrrs_lim                     : 1;
+	uint64_t mps                          : 1;
+	uint64_t reserved_5_6                 : 2;
+	uint64_t mps_lim                      : 1;
+	uint64_t molr                         : 6;
+	uint64_t reserved_14_15               : 2;
+	uint64_t rd_mode                      : 1;
+	uint64_t reserved_17_19               : 3;
+	uint64_t qlm_cfg                      : 4;
+	uint64_t halt                         : 1;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_dpi_sli_prtx_cfg_s        cn61xx;
+	struct cvmx_dpi_sli_prtx_cfg_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_25_63               : 39;
 	uint64_t halt                         : 1;  /**< When set, HALT indicates that the MAC has detected
                                                          a reset condition. No further instructions that
@@ -1156,6 +1890,10 @@ union cvmx_dpi_sli_prtx_cfg
                                                          is cleared in SLI_CTL_PORTx[DIS_PORT]. */
 	uint64_t reserved_21_23               : 3;
 	uint64_t qlm_cfg                      : 1;  /**< Read only copy of the QLM CFG pin
+                                                         Since QLM_CFG is simply a copy of the QLM CFG
+                                                         pins, it may reflect values that are not normal
+                                                         for DMA or packet operations. QLM_CFG does not
+                                                         indicate if a port is disabled.
                                                          0= MAC is PCIe
                                                          1= MAC is SRIO */
 	uint64_t reserved_17_19               : 3;
@@ -1235,9 +1973,12 @@ union cvmx_dpi_sli_prtx_cfg
 	uint64_t halt                         : 1;
 	uint64_t reserved_25_63               : 39;
 #endif
-	} s;
-	struct cvmx_dpi_sli_prtx_cfg_s        cn63xx;
-	struct cvmx_dpi_sli_prtx_cfg_s        cn63xxp1;
+	} cn63xx;
+	struct cvmx_dpi_sli_prtx_cfg_cn63xx   cn63xxp1;
+	struct cvmx_dpi_sli_prtx_cfg_s        cn66xx;
+	struct cvmx_dpi_sli_prtx_cfg_cn63xx   cn68xx;
+	struct cvmx_dpi_sli_prtx_cfg_cn63xx   cn68xxp1;
+	struct cvmx_dpi_sli_prtx_cfg_s        cnf71xx;
 };
 typedef union cvmx_dpi_sli_prtx_cfg cvmx_dpi_sli_prtx_cfg_t;
 
@@ -1248,21 +1989,28 @@ typedef union cvmx_dpi_sli_prtx_cfg cvmx_dpi_sli_prtx_cfg_t;
  *
  * Logs the Address and Request Queue associated with the reported SLI error response
  */
-union cvmx_dpi_sli_prtx_err
-{
+union cvmx_dpi_sli_prtx_err {
 	uint64_t u64;
-	struct cvmx_dpi_sli_prtx_err_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t addr                         : 61; /**< Address of the failed load request. */
+	struct cvmx_dpi_sli_prtx_err_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t addr                         : 61; /**< Address of the failed load request.
+                                                         Address is locked along with the
+                                                         DPI_SLI_PRTx_ERR_INFO register.
+                                                         See the DPI_SLI_PRTx_ERR_INFO[LOCK] description
+                                                         for further information. */
 	uint64_t reserved_0_2                 : 3;
 #else
 	uint64_t reserved_0_2                 : 3;
 	uint64_t addr                         : 61;
 #endif
 	} s;
+	struct cvmx_dpi_sli_prtx_err_s        cn61xx;
 	struct cvmx_dpi_sli_prtx_err_s        cn63xx;
 	struct cvmx_dpi_sli_prtx_err_s        cn63xxp1;
+	struct cvmx_dpi_sli_prtx_err_s        cn66xx;
+	struct cvmx_dpi_sli_prtx_err_s        cn68xx;
+	struct cvmx_dpi_sli_prtx_err_s        cn68xxp1;
+	struct cvmx_dpi_sli_prtx_err_s        cnf71xx;
 };
 typedef union cvmx_dpi_sli_prtx_err cvmx_dpi_sli_prtx_err_t;
 
@@ -1273,15 +2021,28 @@ typedef union cvmx_dpi_sli_prtx_err cvmx_dpi_sli_prtx_err_t;
  *
  * Logs the Address and Request Queue associated with the reported SLI error response
  */
-union cvmx_dpi_sli_prtx_err_info
-{
+union cvmx_dpi_sli_prtx_err_info {
 	uint64_t u64;
-	struct cvmx_dpi_sli_prtx_err_info_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dpi_sli_prtx_err_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t lock                         : 1;  /**< DPI_SLI_PRTx_ERR and DPI_SLI_PRTx_ERR_INFO have
-                                                         captured and locked contents. */
+                                                         captured and locked contents.
+                                                         When Octeon first detects an ErrorResponse, the
+                                                         TYPE, REQQ, and ADDR of the error is saved and an
+                                                         internal lock state is set so the data associated
+                                                         with the initial error is perserved.
+                                                         Subsequent ErrorResponses will optionally raise
+                                                         an interrupt, but will not modify the TYPE, REQQ,
+                                                         or ADDR fields until the internal lock state is
+                                                         cleared.
+                                                         SW can clear the internal lock state by writting
+                                                         a '1' to the appropriate bit in either
+                                                         DPI_REQ_ERR_RSP or DPI_PKT_ERR_RSP depending on
+                                                         the TYPE field.
+                                                         Once the internal lock state is cleared,
+                                                         the next ErrorResponse will set the TYPE, REQQ,
+                                                         and ADDR for the new transaction. */
 	uint64_t reserved_5_7                 : 3;
 	uint64_t type                         : 1;  /**< Type of transaction that caused the ErrorResponse.
                                                          0=DMA Instruction
@@ -1297,8 +2058,13 @@ union cvmx_dpi_sli_prtx_err_info
 	uint64_t reserved_9_63                : 55;
 #endif
 	} s;
+	struct cvmx_dpi_sli_prtx_err_info_s   cn61xx;
 	struct cvmx_dpi_sli_prtx_err_info_s   cn63xx;
 	struct cvmx_dpi_sli_prtx_err_info_s   cn63xxp1;
+	struct cvmx_dpi_sli_prtx_err_info_s   cn66xx;
+	struct cvmx_dpi_sli_prtx_err_info_s   cn68xx;
+	struct cvmx_dpi_sli_prtx_err_info_s   cn68xxp1;
+	struct cvmx_dpi_sli_prtx_err_info_s   cnf71xx;
 };
 typedef union cvmx_dpi_sli_prtx_err_info cvmx_dpi_sli_prtx_err_info_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-ebt3000.c b/sys/contrib/octeon-sdk/cvmx-ebt3000.c
index 5763fda..dbc93dd 100644
--- a/sys/contrib/octeon-sdk/cvmx-ebt3000.c
+++ b/sys/contrib/octeon-sdk/cvmx-ebt3000.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Interface to the EBT3000 specific devices
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-ebt3000.h b/sys/contrib/octeon-sdk/cvmx-ebt3000.h
index 60be6ce..beb5fce 100644
--- a/sys/contrib/octeon-sdk/cvmx-ebt3000.h
+++ b/sys/contrib/octeon-sdk/cvmx-ebt3000.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -51,7 +51,7 @@
  *
  * Interface to the EBT3000 specific devices
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-endor-defs.h b/sys/contrib/octeon-sdk/cvmx-endor-defs.h
new file mode 100644
index 0000000..36ac08d
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-endor-defs.h
@@ -0,0 +1,7826 @@
+/***********************license start***************
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-endor-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon endor.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision: 69515 $<hr>
+ *
+ */
+#ifndef __CVMX_ENDOR_DEFS_H__
+#define __CVMX_ENDOR_DEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_ADMA_AUTO_CLK_GATE CVMX_ENDOR_ADMA_AUTO_CLK_GATE_FUNC()
+static inline uint64_t CVMX_ENDOR_ADMA_AUTO_CLK_GATE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_ADMA_AUTO_CLK_GATE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844004ull);
+}
+#else
+#define CVMX_ENDOR_ADMA_AUTO_CLK_GATE (CVMX_ADD_IO_SEG(0x00010F0000844004ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_ADMA_AXIERR_INTR CVMX_ENDOR_ADMA_AXIERR_INTR_FUNC()
+static inline uint64_t CVMX_ENDOR_ADMA_AXIERR_INTR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_ADMA_AXIERR_INTR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844044ull);
+}
+#else
+#define CVMX_ENDOR_ADMA_AXIERR_INTR (CVMX_ADD_IO_SEG(0x00010F0000844044ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_ADMA_AXI_RSPCODE CVMX_ENDOR_ADMA_AXI_RSPCODE_FUNC()
+static inline uint64_t CVMX_ENDOR_ADMA_AXI_RSPCODE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_ADMA_AXI_RSPCODE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844050ull);
+}
+#else
+#define CVMX_ENDOR_ADMA_AXI_RSPCODE (CVMX_ADD_IO_SEG(0x00010F0000844050ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_ADMA_AXI_SIGNAL CVMX_ENDOR_ADMA_AXI_SIGNAL_FUNC()
+static inline uint64_t CVMX_ENDOR_ADMA_AXI_SIGNAL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_ADMA_AXI_SIGNAL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844084ull);
+}
+#else
+#define CVMX_ENDOR_ADMA_AXI_SIGNAL (CVMX_ADD_IO_SEG(0x00010F0000844084ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_ADMA_DMADONE_INTR CVMX_ENDOR_ADMA_DMADONE_INTR_FUNC()
+static inline uint64_t CVMX_ENDOR_ADMA_DMADONE_INTR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_ADMA_DMADONE_INTR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844040ull);
+}
+#else
+#define CVMX_ENDOR_ADMA_DMADONE_INTR (CVMX_ADD_IO_SEG(0x00010F0000844040ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_ADMA_DMAX_ADDR_HI(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ENDOR_ADMA_DMAX_ADDR_HI(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F000084410Cull) + ((offset) & 7) * 16;
+}
+#else
+#define CVMX_ENDOR_ADMA_DMAX_ADDR_HI(offset) (CVMX_ADD_IO_SEG(0x00010F000084410Cull) + ((offset) & 7) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_ADMA_DMAX_ADDR_LO(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ENDOR_ADMA_DMAX_ADDR_LO(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000844108ull) + ((offset) & 7) * 16;
+}
+#else
+#define CVMX_ENDOR_ADMA_DMAX_ADDR_LO(offset) (CVMX_ADD_IO_SEG(0x00010F0000844108ull) + ((offset) & 7) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_ADMA_DMAX_CFG(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ENDOR_ADMA_DMAX_CFG(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000844100ull) + ((offset) & 7) * 16;
+}
+#else
+#define CVMX_ENDOR_ADMA_DMAX_CFG(offset) (CVMX_ADD_IO_SEG(0x00010F0000844100ull) + ((offset) & 7) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_ADMA_DMAX_SIZE(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ENDOR_ADMA_DMAX_SIZE(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000844104ull) + ((offset) & 7) * 16;
+}
+#else
+#define CVMX_ENDOR_ADMA_DMAX_SIZE(offset) (CVMX_ADD_IO_SEG(0x00010F0000844104ull) + ((offset) & 7) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_ADMA_DMA_PRIORITY CVMX_ENDOR_ADMA_DMA_PRIORITY_FUNC()
+static inline uint64_t CVMX_ENDOR_ADMA_DMA_PRIORITY_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_ADMA_DMA_PRIORITY not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844080ull);
+}
+#else
+#define CVMX_ENDOR_ADMA_DMA_PRIORITY (CVMX_ADD_IO_SEG(0x00010F0000844080ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_ADMA_DMA_RESET CVMX_ENDOR_ADMA_DMA_RESET_FUNC()
+static inline uint64_t CVMX_ENDOR_ADMA_DMA_RESET_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_ADMA_DMA_RESET not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844008ull);
+}
+#else
+#define CVMX_ENDOR_ADMA_DMA_RESET (CVMX_ADD_IO_SEG(0x00010F0000844008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_ADMA_INTR_DIS CVMX_ENDOR_ADMA_INTR_DIS_FUNC()
+static inline uint64_t CVMX_ENDOR_ADMA_INTR_DIS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_ADMA_INTR_DIS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F000084404Cull);
+}
+#else
+#define CVMX_ENDOR_ADMA_INTR_DIS (CVMX_ADD_IO_SEG(0x00010F000084404Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_ADMA_INTR_ENB CVMX_ENDOR_ADMA_INTR_ENB_FUNC()
+static inline uint64_t CVMX_ENDOR_ADMA_INTR_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_ADMA_INTR_ENB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844048ull);
+}
+#else
+#define CVMX_ENDOR_ADMA_INTR_ENB (CVMX_ADD_IO_SEG(0x00010F0000844048ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_ADMA_MODULE_STATUS CVMX_ENDOR_ADMA_MODULE_STATUS_FUNC()
+static inline uint64_t CVMX_ENDOR_ADMA_MODULE_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_ADMA_MODULE_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844000ull);
+}
+#else
+#define CVMX_ENDOR_ADMA_MODULE_STATUS (CVMX_ADD_IO_SEG(0x00010F0000844000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_CNTL_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_CNTL_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F00008201E4ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_ENDOR_INTC_CNTL_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201E4ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_CNTL_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_CNTL_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F00008201E0ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_ENDOR_INTC_CNTL_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201E0ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_INDEX_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_INDEX_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F00008201A4ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_ENDOR_INTC_INDEX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201A4ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_INDEX_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_INDEX_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F00008201A0ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_ENDOR_INTC_INDEX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201A0ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_MISC_IDX_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_MISC_IDX_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820134ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_MISC_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820134ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_MISC_IDX_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_MISC_IDX_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820114ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_MISC_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820114ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_MISC_MASK_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_MISC_MASK_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820034ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_MISC_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820034ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_MISC_MASK_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_MISC_MASK_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820014ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_MISC_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820014ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_INTC_MISC_RINT CVMX_ENDOR_INTC_MISC_RINT_FUNC()
+static inline uint64_t CVMX_ENDOR_INTC_MISC_RINT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_INTC_MISC_RINT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000820194ull);
+}
+#else
+#define CVMX_ENDOR_INTC_MISC_RINT (CVMX_ADD_IO_SEG(0x00010F0000820194ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_MISC_STATUS_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_MISC_STATUS_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F00008200B4ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_MISC_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200B4ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_MISC_STATUS_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_MISC_STATUS_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820094ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_MISC_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820094ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_RDQ_IDX_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_RDQ_IDX_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F000082012Cull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_RDQ_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F000082012Cull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_RDQ_IDX_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_RDQ_IDX_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F000082010Cull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_RDQ_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F000082010Cull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_RDQ_MASK_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_RDQ_MASK_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F000082002Cull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_RDQ_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F000082002Cull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_RDQ_MASK_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_RDQ_MASK_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F000082000Cull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_RDQ_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F000082000Cull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_INTC_RDQ_RINT CVMX_ENDOR_INTC_RDQ_RINT_FUNC()
+static inline uint64_t CVMX_ENDOR_INTC_RDQ_RINT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_INTC_RDQ_RINT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F000082018Cull);
+}
+#else
+#define CVMX_ENDOR_INTC_RDQ_RINT (CVMX_ADD_IO_SEG(0x00010F000082018Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_RDQ_STATUS_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_RDQ_STATUS_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F00008200ACull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_RDQ_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200ACull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_RDQ_STATUS_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_RDQ_STATUS_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F000082008Cull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_RDQ_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F000082008Cull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_RD_IDX_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_RD_IDX_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820124ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_RD_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820124ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_RD_IDX_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_RD_IDX_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820104ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_RD_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820104ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_RD_MASK_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_RD_MASK_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820024ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_RD_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820024ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_RD_MASK_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_RD_MASK_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820004ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_RD_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820004ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_INTC_RD_RINT CVMX_ENDOR_INTC_RD_RINT_FUNC()
+static inline uint64_t CVMX_ENDOR_INTC_RD_RINT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_INTC_RD_RINT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000820184ull);
+}
+#else
+#define CVMX_ENDOR_INTC_RD_RINT (CVMX_ADD_IO_SEG(0x00010F0000820184ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_RD_STATUS_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_RD_STATUS_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F00008200A4ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_RD_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200A4ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_RD_STATUS_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_RD_STATUS_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820084ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_RD_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820084ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_STAT_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_STAT_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F00008201C4ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_ENDOR_INTC_STAT_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201C4ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_STAT_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_STAT_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F00008201C0ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_ENDOR_INTC_STAT_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201C0ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_INTC_SWCLR CVMX_ENDOR_INTC_SWCLR_FUNC()
+static inline uint64_t CVMX_ENDOR_INTC_SWCLR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_INTC_SWCLR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000820204ull);
+}
+#else
+#define CVMX_ENDOR_INTC_SWCLR (CVMX_ADD_IO_SEG(0x00010F0000820204ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_INTC_SWSET CVMX_ENDOR_INTC_SWSET_FUNC()
+static inline uint64_t CVMX_ENDOR_INTC_SWSET_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_INTC_SWSET not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000820200ull);
+}
+#else
+#define CVMX_ENDOR_INTC_SWSET (CVMX_ADD_IO_SEG(0x00010F0000820200ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_SW_IDX_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_SW_IDX_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820130ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_SW_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820130ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_SW_IDX_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_SW_IDX_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820110ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_SW_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820110ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_SW_MASK_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_SW_MASK_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820030ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_SW_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820030ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_SW_MASK_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_SW_MASK_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820010ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_SW_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820010ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_INTC_SW_RINT CVMX_ENDOR_INTC_SW_RINT_FUNC()
+static inline uint64_t CVMX_ENDOR_INTC_SW_RINT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_INTC_SW_RINT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000820190ull);
+}
+#else
+#define CVMX_ENDOR_INTC_SW_RINT (CVMX_ADD_IO_SEG(0x00010F0000820190ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_SW_STATUS_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_SW_STATUS_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F00008200B0ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_SW_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200B0ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_SW_STATUS_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_SW_STATUS_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820090ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_SW_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820090ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_WRQ_IDX_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_WRQ_IDX_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820128ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_WRQ_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820128ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_WRQ_IDX_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_WRQ_IDX_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820108ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_WRQ_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820108ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_WRQ_MASK_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_WRQ_MASK_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820028ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_WRQ_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820028ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_WRQ_MASK_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_WRQ_MASK_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820008ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_WRQ_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820008ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_INTC_WRQ_RINT CVMX_ENDOR_INTC_WRQ_RINT_FUNC()
+static inline uint64_t CVMX_ENDOR_INTC_WRQ_RINT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_INTC_WRQ_RINT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000820188ull);
+}
+#else
+#define CVMX_ENDOR_INTC_WRQ_RINT (CVMX_ADD_IO_SEG(0x00010F0000820188ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_WRQ_STATUS_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_WRQ_STATUS_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F00008200A8ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_WRQ_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200A8ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_WRQ_STATUS_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_WRQ_STATUS_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820088ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_WRQ_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820088ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_WR_IDX_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_WR_IDX_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820120ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_WR_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820120ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_WR_IDX_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_WR_IDX_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820100ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_WR_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820100ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_WR_MASK_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_WR_MASK_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820020ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_WR_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820020ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_WR_MASK_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_WR_MASK_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820000ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_WR_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820000ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_INTC_WR_RINT CVMX_ENDOR_INTC_WR_RINT_FUNC()
+static inline uint64_t CVMX_ENDOR_INTC_WR_RINT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_INTC_WR_RINT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000820180ull);
+}
+#else
+#define CVMX_ENDOR_INTC_WR_RINT (CVMX_ADD_IO_SEG(0x00010F0000820180ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_WR_STATUS_HIX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_WR_STATUS_HIX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F00008200A0ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_WR_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200A0ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_INTC_WR_STATUS_LOX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ENDOR_INTC_WR_STATUS_LOX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000820080ull) + ((offset) & 1) * 64;
+}
+#else
+#define CVMX_ENDOR_INTC_WR_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820080ull) + ((offset) & 1) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR0 CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR0_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000832054ull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR0 (CVMX_ADD_IO_SEG(0x00010F0000832054ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR1 CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR1_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F000083205Cull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR1 (CVMX_ADD_IO_SEG(0x00010F000083205Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR2 CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR2_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000832064ull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR2 (CVMX_ADD_IO_SEG(0x00010F0000832064ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR3 CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR3_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F000083206Cull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR3 (CVMX_ADD_IO_SEG(0x00010F000083206Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR0 CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR0_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000832050ull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR0 (CVMX_ADD_IO_SEG(0x00010F0000832050ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR1 CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR1_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000832058ull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR1 (CVMX_ADD_IO_SEG(0x00010F0000832058ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR2 CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR2_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000832060ull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR2 (CVMX_ADD_IO_SEG(0x00010F0000832060ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR3 CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR3_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000832068ull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR3 (CVMX_ADD_IO_SEG(0x00010F0000832068ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_INTR_CLEAR CVMX_ENDOR_OFS_HMM_INTR_CLEAR_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_INTR_CLEAR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_INTR_CLEAR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000832018ull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_INTR_CLEAR (CVMX_ADD_IO_SEG(0x00010F0000832018ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_INTR_ENB CVMX_ENDOR_OFS_HMM_INTR_ENB_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_INTR_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_INTR_ENB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F000083201Cull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_INTR_ENB (CVMX_ADD_IO_SEG(0x00010F000083201Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_INTR_RSTATUS CVMX_ENDOR_OFS_HMM_INTR_RSTATUS_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_INTR_RSTATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_INTR_RSTATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000832014ull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_INTR_RSTATUS (CVMX_ADD_IO_SEG(0x00010F0000832014ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_INTR_STATUS CVMX_ENDOR_OFS_HMM_INTR_STATUS_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_INTR_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_INTR_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000832010ull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_INTR_STATUS (CVMX_ADD_IO_SEG(0x00010F0000832010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_INTR_TEST CVMX_ENDOR_OFS_HMM_INTR_TEST_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_INTR_TEST_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_INTR_TEST not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000832020ull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_INTR_TEST (CVMX_ADD_IO_SEG(0x00010F0000832020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_MODE CVMX_ENDOR_OFS_HMM_MODE_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_MODE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_MODE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000832004ull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_MODE (CVMX_ADD_IO_SEG(0x00010F0000832004ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_START_ADDR0 CVMX_ENDOR_OFS_HMM_START_ADDR0_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_START_ADDR0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_START_ADDR0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000832030ull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_START_ADDR0 (CVMX_ADD_IO_SEG(0x00010F0000832030ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_START_ADDR1 CVMX_ENDOR_OFS_HMM_START_ADDR1_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_START_ADDR1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_START_ADDR1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000832034ull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_START_ADDR1 (CVMX_ADD_IO_SEG(0x00010F0000832034ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_START_ADDR2 CVMX_ENDOR_OFS_HMM_START_ADDR2_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_START_ADDR2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_START_ADDR2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000832038ull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_START_ADDR2 (CVMX_ADD_IO_SEG(0x00010F0000832038ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_START_ADDR3 CVMX_ENDOR_OFS_HMM_START_ADDR3_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_START_ADDR3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_START_ADDR3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F000083203Cull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_START_ADDR3 (CVMX_ADD_IO_SEG(0x00010F000083203Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_STATUS CVMX_ENDOR_OFS_HMM_STATUS_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000832000ull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_STATUS (CVMX_ADD_IO_SEG(0x00010F0000832000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_XFER_CNT CVMX_ENDOR_OFS_HMM_XFER_CNT_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_XFER_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_XFER_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F000083202Cull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_XFER_CNT (CVMX_ADD_IO_SEG(0x00010F000083202Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_XFER_Q_STATUS CVMX_ENDOR_OFS_HMM_XFER_Q_STATUS_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_XFER_Q_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_XFER_Q_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F000083200Cull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_XFER_Q_STATUS (CVMX_ADD_IO_SEG(0x00010F000083200Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_OFS_HMM_XFER_START CVMX_ENDOR_OFS_HMM_XFER_START_FUNC()
+static inline uint64_t CVMX_ENDOR_OFS_HMM_XFER_START_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_OFS_HMM_XFER_START not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000832028ull);
+}
+#else
+#define CVMX_ENDOR_OFS_HMM_XFER_START (CVMX_ADD_IO_SEG(0x00010F0000832028ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_1PPS_GEN_CFG CVMX_ENDOR_RFIF_1PPS_GEN_CFG_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_1PPS_GEN_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_1PPS_GEN_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008680CCull);
+}
+#else
+#define CVMX_ENDOR_RFIF_1PPS_GEN_CFG (CVMX_ADD_IO_SEG(0x00010F00008680CCull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_1PPS_SAMPLE_CNT_OFFSET CVMX_ENDOR_RFIF_1PPS_SAMPLE_CNT_OFFSET_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_1PPS_SAMPLE_CNT_OFFSET_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_1PPS_SAMPLE_CNT_OFFSET not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868104ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_1PPS_SAMPLE_CNT_OFFSET (CVMX_ADD_IO_SEG(0x00010F0000868104ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_1PPS_VERIF_GEN_EN CVMX_ENDOR_RFIF_1PPS_VERIF_GEN_EN_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_1PPS_VERIF_GEN_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_1PPS_VERIF_GEN_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868110ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_1PPS_VERIF_GEN_EN (CVMX_ADD_IO_SEG(0x00010F0000868110ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_1PPS_VERIF_SCNT CVMX_ENDOR_RFIF_1PPS_VERIF_SCNT_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_1PPS_VERIF_SCNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_1PPS_VERIF_SCNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868114ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_1PPS_VERIF_SCNT (CVMX_ADD_IO_SEG(0x00010F0000868114ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_CONF CVMX_ENDOR_RFIF_CONF_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_CONF_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_CONF not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868010ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_CONF (CVMX_ADD_IO_SEG(0x00010F0000868010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_CONF2 CVMX_ENDOR_RFIF_CONF2_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_CONF2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_CONF2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F000086801Cull);
+}
+#else
+#define CVMX_ENDOR_RFIF_CONF2 (CVMX_ADD_IO_SEG(0x00010F000086801Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_DSP1_GPIO CVMX_ENDOR_RFIF_DSP1_GPIO_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_DSP1_GPIO_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_DSP1_GPIO not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008684C0ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_DSP1_GPIO (CVMX_ADD_IO_SEG(0x00010F00008684C0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_DSP_RX_HIS CVMX_ENDOR_RFIF_DSP_RX_HIS_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_DSP_RX_HIS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_DSP_RX_HIS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F000086840Cull);
+}
+#else
+#define CVMX_ENDOR_RFIF_DSP_RX_HIS (CVMX_ADD_IO_SEG(0x00010F000086840Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_DSP_RX_ISM CVMX_ENDOR_RFIF_DSP_RX_ISM_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_DSP_RX_ISM_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_DSP_RX_ISM not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868400ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_DSP_RX_ISM (CVMX_ADD_IO_SEG(0x00010F0000868400ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_FIRS_ENABLE CVMX_ENDOR_RFIF_FIRS_ENABLE_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_FIRS_ENABLE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_FIRS_ENABLE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008684C4ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_FIRS_ENABLE (CVMX_ADD_IO_SEG(0x00010F00008684C4ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_FRAME_CNT CVMX_ENDOR_RFIF_FRAME_CNT_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_FRAME_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_FRAME_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868030ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_FRAME_CNT (CVMX_ADD_IO_SEG(0x00010F0000868030ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_FRAME_L CVMX_ENDOR_RFIF_FRAME_L_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_FRAME_L_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_FRAME_L not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868014ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_FRAME_L (CVMX_ADD_IO_SEG(0x00010F0000868014ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_RFIF_GPIO_X(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_ENDOR_RFIF_GPIO_X(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000868418ull) + ((offset) & 3) * 4;
+}
+#else
+#define CVMX_ENDOR_RFIF_GPIO_X(offset) (CVMX_ADD_IO_SEG(0x00010F0000868418ull) + ((offset) & 3) * 4)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_MAX_SAMPLE_ADJ CVMX_ENDOR_RFIF_MAX_SAMPLE_ADJ_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_MAX_SAMPLE_ADJ_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_MAX_SAMPLE_ADJ not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008680DCull);
+}
+#else
+#define CVMX_ENDOR_RFIF_MAX_SAMPLE_ADJ (CVMX_ADD_IO_SEG(0x00010F00008680DCull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_MIN_SAMPLE_ADJ CVMX_ENDOR_RFIF_MIN_SAMPLE_ADJ_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_MIN_SAMPLE_ADJ_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_MIN_SAMPLE_ADJ not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008680E0ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_MIN_SAMPLE_ADJ (CVMX_ADD_IO_SEG(0x00010F00008680E0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_NUM_RX_WIN CVMX_ENDOR_RFIF_NUM_RX_WIN_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_NUM_RX_WIN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_NUM_RX_WIN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868018ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_NUM_RX_WIN (CVMX_ADD_IO_SEG(0x00010F0000868018ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_PWM_ENABLE CVMX_ENDOR_RFIF_PWM_ENABLE_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_PWM_ENABLE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_PWM_ENABLE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868180ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_PWM_ENABLE (CVMX_ADD_IO_SEG(0x00010F0000868180ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_PWM_HIGH_TIME CVMX_ENDOR_RFIF_PWM_HIGH_TIME_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_PWM_HIGH_TIME_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_PWM_HIGH_TIME not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868184ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_PWM_HIGH_TIME (CVMX_ADD_IO_SEG(0x00010F0000868184ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_PWM_LOW_TIME CVMX_ENDOR_RFIF_PWM_LOW_TIME_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_PWM_LOW_TIME_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_PWM_LOW_TIME not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868188ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_PWM_LOW_TIME (CVMX_ADD_IO_SEG(0x00010F0000868188ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_RD_TIMER64_LSB CVMX_ENDOR_RFIF_RD_TIMER64_LSB_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_RD_TIMER64_LSB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_RD_TIMER64_LSB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008681ACull);
+}
+#else
+#define CVMX_ENDOR_RFIF_RD_TIMER64_LSB (CVMX_ADD_IO_SEG(0x00010F00008681ACull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_RD_TIMER64_MSB CVMX_ENDOR_RFIF_RD_TIMER64_MSB_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_RD_TIMER64_MSB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_RD_TIMER64_MSB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008681B0ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_RD_TIMER64_MSB (CVMX_ADD_IO_SEG(0x00010F00008681B0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_REAL_TIME_TIMER CVMX_ENDOR_RFIF_REAL_TIME_TIMER_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_REAL_TIME_TIMER_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_REAL_TIME_TIMER not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008680C8ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_REAL_TIME_TIMER (CVMX_ADD_IO_SEG(0x00010F00008680C8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_RF_CLK_TIMER CVMX_ENDOR_RFIF_RF_CLK_TIMER_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_RF_CLK_TIMER_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_RF_CLK_TIMER not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868194ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_RF_CLK_TIMER (CVMX_ADD_IO_SEG(0x00010F0000868194ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_RF_CLK_TIMER_EN CVMX_ENDOR_RFIF_RF_CLK_TIMER_EN_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_RF_CLK_TIMER_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_RF_CLK_TIMER_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868198ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_RF_CLK_TIMER_EN (CVMX_ADD_IO_SEG(0x00010F0000868198ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_RX_CORRECT_ADJ CVMX_ENDOR_RFIF_RX_CORRECT_ADJ_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_RX_CORRECT_ADJ_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_RX_CORRECT_ADJ not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008680E8ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_RX_CORRECT_ADJ (CVMX_ADD_IO_SEG(0x00010F00008680E8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_RX_DIV_STATUS CVMX_ENDOR_RFIF_RX_DIV_STATUS_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_RX_DIV_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_RX_DIV_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868004ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_RX_DIV_STATUS (CVMX_ADD_IO_SEG(0x00010F0000868004ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_RX_FIFO_CNT CVMX_ENDOR_RFIF_RX_FIFO_CNT_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_RX_FIFO_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_RX_FIFO_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868500ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_RX_FIFO_CNT (CVMX_ADD_IO_SEG(0x00010F0000868500ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_RX_IF_CFG CVMX_ENDOR_RFIF_RX_IF_CFG_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_RX_IF_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_RX_IF_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868038ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_RX_IF_CFG (CVMX_ADD_IO_SEG(0x00010F0000868038ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_RX_LEAD_LAG CVMX_ENDOR_RFIF_RX_LEAD_LAG_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_RX_LEAD_LAG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_RX_LEAD_LAG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868020ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_RX_LEAD_LAG (CVMX_ADD_IO_SEG(0x00010F0000868020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_RX_LOAD_CFG CVMX_ENDOR_RFIF_RX_LOAD_CFG_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_RX_LOAD_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_RX_LOAD_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868508ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_RX_LOAD_CFG (CVMX_ADD_IO_SEG(0x00010F0000868508ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_RX_OFFSET CVMX_ENDOR_RFIF_RX_OFFSET_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_RX_OFFSET_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_RX_OFFSET not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008680D4ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_RX_OFFSET (CVMX_ADD_IO_SEG(0x00010F00008680D4ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_RX_OFFSET_ADJ_SCNT CVMX_ENDOR_RFIF_RX_OFFSET_ADJ_SCNT_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_RX_OFFSET_ADJ_SCNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_RX_OFFSET_ADJ_SCNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868108ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_RX_OFFSET_ADJ_SCNT (CVMX_ADD_IO_SEG(0x00010F0000868108ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_RX_STATUS CVMX_ENDOR_RFIF_RX_STATUS_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_RX_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_RX_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868000ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_RX_STATUS (CVMX_ADD_IO_SEG(0x00010F0000868000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_RX_SYNC_SCNT CVMX_ENDOR_RFIF_RX_SYNC_SCNT_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_RX_SYNC_SCNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_RX_SYNC_SCNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008680C4ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_RX_SYNC_SCNT (CVMX_ADD_IO_SEG(0x00010F00008680C4ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_RX_SYNC_VALUE CVMX_ENDOR_RFIF_RX_SYNC_VALUE_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_RX_SYNC_VALUE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_RX_SYNC_VALUE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008680C0ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_RX_SYNC_VALUE (CVMX_ADD_IO_SEG(0x00010F00008680C0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_RX_TH CVMX_ENDOR_RFIF_RX_TH_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_RX_TH_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_RX_TH not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868410ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_RX_TH (CVMX_ADD_IO_SEG(0x00010F0000868410ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_RX_TRANSFER_SIZE CVMX_ENDOR_RFIF_RX_TRANSFER_SIZE_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_RX_TRANSFER_SIZE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_RX_TRANSFER_SIZE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F000086850Cull);
+}
+#else
+#define CVMX_ENDOR_RFIF_RX_TRANSFER_SIZE (CVMX_ADD_IO_SEG(0x00010F000086850Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_RFIF_RX_W_EX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_ENDOR_RFIF_RX_W_EX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000868084ull) + ((offset) & 3) * 4;
+}
+#else
+#define CVMX_ENDOR_RFIF_RX_W_EX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868084ull) + ((offset) & 3) * 4)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_RFIF_RX_W_SX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_ENDOR_RFIF_RX_W_SX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000868044ull) + ((offset) & 3) * 4;
+}
+#else
+#define CVMX_ENDOR_RFIF_RX_W_SX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868044ull) + ((offset) & 3) * 4)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_SAMPLE_ADJ_CFG CVMX_ENDOR_RFIF_SAMPLE_ADJ_CFG_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_SAMPLE_ADJ_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_SAMPLE_ADJ_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008680E4ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_SAMPLE_ADJ_CFG (CVMX_ADD_IO_SEG(0x00010F00008680E4ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_SAMPLE_ADJ_ERROR CVMX_ENDOR_RFIF_SAMPLE_ADJ_ERROR_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_SAMPLE_ADJ_ERROR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_SAMPLE_ADJ_ERROR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868100ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_SAMPLE_ADJ_ERROR (CVMX_ADD_IO_SEG(0x00010F0000868100ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_SAMPLE_CNT CVMX_ENDOR_RFIF_SAMPLE_CNT_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_SAMPLE_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_SAMPLE_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868028ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_SAMPLE_CNT (CVMX_ADD_IO_SEG(0x00010F0000868028ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_SKIP_FRM_CNT_BITS CVMX_ENDOR_RFIF_SKIP_FRM_CNT_BITS_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_SKIP_FRM_CNT_BITS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_SKIP_FRM_CNT_BITS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868444ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_SKIP_FRM_CNT_BITS (CVMX_ADD_IO_SEG(0x00010F0000868444ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_RFIF_SPI_CMDSX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_ENDOR_RFIF_SPI_CMDSX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000868800ull) + ((offset) & 63) * 4;
+}
+#else
+#define CVMX_ENDOR_RFIF_SPI_CMDSX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868800ull) + ((offset) & 63) * 4)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_RFIF_SPI_CMD_ATTRX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_ENDOR_RFIF_SPI_CMD_ATTRX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000868A00ull) + ((offset) & 63) * 4;
+}
+#else
+#define CVMX_ENDOR_RFIF_SPI_CMD_ATTRX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868A00ull) + ((offset) & 63) * 4)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_SPI_CONF0 CVMX_ENDOR_RFIF_SPI_CONF0_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_SPI_CONF0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_SPI_CONF0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868428ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_SPI_CONF0 (CVMX_ADD_IO_SEG(0x00010F0000868428ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_SPI_CONF1 CVMX_ENDOR_RFIF_SPI_CONF1_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_SPI_CONF1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_SPI_CONF1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F000086842Cull);
+}
+#else
+#define CVMX_ENDOR_RFIF_SPI_CONF1 (CVMX_ADD_IO_SEG(0x00010F000086842Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_SPI_CTRL CVMX_ENDOR_RFIF_SPI_CTRL_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_SPI_CTRL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_SPI_CTRL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000866008ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_SPI_CTRL (CVMX_ADD_IO_SEG(0x00010F0000866008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_RFIF_SPI_DINX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_ENDOR_RFIF_SPI_DINX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000868900ull) + ((offset) & 63) * 4;
+}
+#else
+#define CVMX_ENDOR_RFIF_SPI_DINX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868900ull) + ((offset) & 63) * 4)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_SPI_RX_DATA CVMX_ENDOR_RFIF_SPI_RX_DATA_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_SPI_RX_DATA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_SPI_RX_DATA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000866000ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_SPI_RX_DATA (CVMX_ADD_IO_SEG(0x00010F0000866000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_SPI_STATUS CVMX_ENDOR_RFIF_SPI_STATUS_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_SPI_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_SPI_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000866010ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_SPI_STATUS (CVMX_ADD_IO_SEG(0x00010F0000866010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_SPI_TX_DATA CVMX_ENDOR_RFIF_SPI_TX_DATA_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_SPI_TX_DATA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_SPI_TX_DATA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000866004ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_SPI_TX_DATA (CVMX_ADD_IO_SEG(0x00010F0000866004ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_RFIF_SPI_X_LL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_ENDOR_RFIF_SPI_X_LL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000868430ull) + ((offset) & 3) * 4;
+}
+#else
+#define CVMX_ENDOR_RFIF_SPI_X_LL(offset) (CVMX_ADD_IO_SEG(0x00010F0000868430ull) + ((offset) & 3) * 4)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_TIMER64_CFG CVMX_ENDOR_RFIF_TIMER64_CFG_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_TIMER64_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_TIMER64_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008681A0ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_TIMER64_CFG (CVMX_ADD_IO_SEG(0x00010F00008681A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_TIMER64_EN CVMX_ENDOR_RFIF_TIMER64_EN_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_TIMER64_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_TIMER64_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F000086819Cull);
+}
+#else
+#define CVMX_ENDOR_RFIF_TIMER64_EN (CVMX_ADD_IO_SEG(0x00010F000086819Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_RFIF_TTI_SCNT_INTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ENDOR_RFIF_TTI_SCNT_INTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000868140ull) + ((offset) & 7) * 4;
+}
+#else
+#define CVMX_ENDOR_RFIF_TTI_SCNT_INTX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868140ull) + ((offset) & 7) * 4)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_CLR CVMX_ENDOR_RFIF_TTI_SCNT_INT_CLR_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_TTI_SCNT_INT_CLR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_TTI_SCNT_INT_CLR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868118ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_CLR (CVMX_ADD_IO_SEG(0x00010F0000868118ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_EN CVMX_ENDOR_RFIF_TTI_SCNT_INT_EN_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_TTI_SCNT_INT_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_TTI_SCNT_INT_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868124ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_EN (CVMX_ADD_IO_SEG(0x00010F0000868124ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_MAP CVMX_ENDOR_RFIF_TTI_SCNT_INT_MAP_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_TTI_SCNT_INT_MAP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_TTI_SCNT_INT_MAP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868120ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_MAP (CVMX_ADD_IO_SEG(0x00010F0000868120ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_STAT CVMX_ENDOR_RFIF_TTI_SCNT_INT_STAT_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_TTI_SCNT_INT_STAT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_TTI_SCNT_INT_STAT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F000086811Cull);
+}
+#else
+#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_STAT (CVMX_ADD_IO_SEG(0x00010F000086811Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_TX_DIV_STATUS CVMX_ENDOR_RFIF_TX_DIV_STATUS_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_TX_DIV_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_TX_DIV_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F000086800Cull);
+}
+#else
+#define CVMX_ENDOR_RFIF_TX_DIV_STATUS (CVMX_ADD_IO_SEG(0x00010F000086800Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_TX_IF_CFG CVMX_ENDOR_RFIF_TX_IF_CFG_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_TX_IF_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_TX_IF_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868034ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_TX_IF_CFG (CVMX_ADD_IO_SEG(0x00010F0000868034ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_TX_LEAD_LAG CVMX_ENDOR_RFIF_TX_LEAD_LAG_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_TX_LEAD_LAG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_TX_LEAD_LAG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868024ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_TX_LEAD_LAG (CVMX_ADD_IO_SEG(0x00010F0000868024ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_TX_OFFSET CVMX_ENDOR_RFIF_TX_OFFSET_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_TX_OFFSET_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_TX_OFFSET not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008680D8ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_TX_OFFSET (CVMX_ADD_IO_SEG(0x00010F00008680D8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_TX_OFFSET_ADJ_SCNT CVMX_ENDOR_RFIF_TX_OFFSET_ADJ_SCNT_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_TX_OFFSET_ADJ_SCNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_TX_OFFSET_ADJ_SCNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F000086810Cull);
+}
+#else
+#define CVMX_ENDOR_RFIF_TX_OFFSET_ADJ_SCNT (CVMX_ADD_IO_SEG(0x00010F000086810Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_TX_STATUS CVMX_ENDOR_RFIF_TX_STATUS_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_TX_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_TX_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868008ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_TX_STATUS (CVMX_ADD_IO_SEG(0x00010F0000868008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_TX_TH CVMX_ENDOR_RFIF_TX_TH_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_TX_TH_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_TX_TH not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868414ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_TX_TH (CVMX_ADD_IO_SEG(0x00010F0000868414ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_WIN_EN CVMX_ENDOR_RFIF_WIN_EN_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_WIN_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_WIN_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000868040ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_WIN_EN (CVMX_ADD_IO_SEG(0x00010F0000868040ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_WIN_UPD_SCNT CVMX_ENDOR_RFIF_WIN_UPD_SCNT_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_WIN_UPD_SCNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_WIN_UPD_SCNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F000086803Cull);
+}
+#else
+#define CVMX_ENDOR_RFIF_WIN_UPD_SCNT (CVMX_ADD_IO_SEG(0x00010F000086803Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_WR_TIMER64_LSB CVMX_ENDOR_RFIF_WR_TIMER64_LSB_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_WR_TIMER64_LSB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_WR_TIMER64_LSB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008681A4ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_WR_TIMER64_LSB (CVMX_ADD_IO_SEG(0x00010F00008681A4ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RFIF_WR_TIMER64_MSB CVMX_ENDOR_RFIF_WR_TIMER64_MSB_FUNC()
+static inline uint64_t CVMX_ENDOR_RFIF_WR_TIMER64_MSB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RFIF_WR_TIMER64_MSB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008681A8ull);
+}
+#else
+#define CVMX_ENDOR_RFIF_WR_TIMER64_MSB (CVMX_ADD_IO_SEG(0x00010F00008681A8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_CLKENB0_CLR CVMX_ENDOR_RSTCLK_CLKENB0_CLR_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_CLKENB0_CLR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_CLKENB0_CLR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844428ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_CLKENB0_CLR (CVMX_ADD_IO_SEG(0x00010F0000844428ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_CLKENB0_SET CVMX_ENDOR_RSTCLK_CLKENB0_SET_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_CLKENB0_SET_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_CLKENB0_SET not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844424ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_CLKENB0_SET (CVMX_ADD_IO_SEG(0x00010F0000844424ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_CLKENB0_STATE CVMX_ENDOR_RSTCLK_CLKENB0_STATE_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_CLKENB0_STATE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_CLKENB0_STATE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844420ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_CLKENB0_STATE (CVMX_ADD_IO_SEG(0x00010F0000844420ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_CLKENB1_CLR CVMX_ENDOR_RSTCLK_CLKENB1_CLR_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_CLKENB1_CLR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_CLKENB1_CLR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844438ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_CLKENB1_CLR (CVMX_ADD_IO_SEG(0x00010F0000844438ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_CLKENB1_SET CVMX_ENDOR_RSTCLK_CLKENB1_SET_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_CLKENB1_SET_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_CLKENB1_SET not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844434ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_CLKENB1_SET (CVMX_ADD_IO_SEG(0x00010F0000844434ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_CLKENB1_STATE CVMX_ENDOR_RSTCLK_CLKENB1_STATE_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_CLKENB1_STATE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_CLKENB1_STATE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844430ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_CLKENB1_STATE (CVMX_ADD_IO_SEG(0x00010F0000844430ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_DSPSTALL_CLR CVMX_ENDOR_RSTCLK_DSPSTALL_CLR_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_DSPSTALL_CLR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_DSPSTALL_CLR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844448ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_DSPSTALL_CLR (CVMX_ADD_IO_SEG(0x00010F0000844448ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_DSPSTALL_SET CVMX_ENDOR_RSTCLK_DSPSTALL_SET_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_DSPSTALL_SET_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_DSPSTALL_SET not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844444ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_DSPSTALL_SET (CVMX_ADD_IO_SEG(0x00010F0000844444ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_DSPSTALL_STATE CVMX_ENDOR_RSTCLK_DSPSTALL_STATE_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_DSPSTALL_STATE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_DSPSTALL_STATE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844440ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_DSPSTALL_STATE (CVMX_ADD_IO_SEG(0x00010F0000844440ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_INTR0_CLRMASK CVMX_ENDOR_RSTCLK_INTR0_CLRMASK_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_INTR0_CLRMASK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_INTR0_CLRMASK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844598ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_INTR0_CLRMASK (CVMX_ADD_IO_SEG(0x00010F0000844598ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_INTR0_MASK CVMX_ENDOR_RSTCLK_INTR0_MASK_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_INTR0_MASK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_INTR0_MASK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844590ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_INTR0_MASK (CVMX_ADD_IO_SEG(0x00010F0000844590ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_INTR0_SETMASK CVMX_ENDOR_RSTCLK_INTR0_SETMASK_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_INTR0_SETMASK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_INTR0_SETMASK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844594ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_INTR0_SETMASK (CVMX_ADD_IO_SEG(0x00010F0000844594ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_INTR0_STATUS CVMX_ENDOR_RSTCLK_INTR0_STATUS_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_INTR0_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_INTR0_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F000084459Cull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_INTR0_STATUS (CVMX_ADD_IO_SEG(0x00010F000084459Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_INTR1_CLRMASK CVMX_ENDOR_RSTCLK_INTR1_CLRMASK_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_INTR1_CLRMASK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_INTR1_CLRMASK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008445A8ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_INTR1_CLRMASK (CVMX_ADD_IO_SEG(0x00010F00008445A8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_INTR1_MASK CVMX_ENDOR_RSTCLK_INTR1_MASK_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_INTR1_MASK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_INTR1_MASK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008445A0ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_INTR1_MASK (CVMX_ADD_IO_SEG(0x00010F00008445A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_INTR1_SETMASK CVMX_ENDOR_RSTCLK_INTR1_SETMASK_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_INTR1_SETMASK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_INTR1_SETMASK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008445A4ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_INTR1_SETMASK (CVMX_ADD_IO_SEG(0x00010F00008445A4ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_INTR1_STATUS CVMX_ENDOR_RSTCLK_INTR1_STATUS_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_INTR1_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_INTR1_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008445ACull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_INTR1_STATUS (CVMX_ADD_IO_SEG(0x00010F00008445ACull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_PHY_CONFIG CVMX_ENDOR_RSTCLK_PHY_CONFIG_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_PHY_CONFIG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_PHY_CONFIG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844450ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_PHY_CONFIG (CVMX_ADD_IO_SEG(0x00010F0000844450ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_PROC_MON CVMX_ENDOR_RSTCLK_PROC_MON_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_PROC_MON_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_PROC_MON not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008445B0ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_PROC_MON (CVMX_ADD_IO_SEG(0x00010F00008445B0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_PROC_MON_COUNT CVMX_ENDOR_RSTCLK_PROC_MON_COUNT_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_PROC_MON_COUNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_PROC_MON_COUNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F00008445B4ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_PROC_MON_COUNT (CVMX_ADD_IO_SEG(0x00010F00008445B4ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_RESET0_CLR CVMX_ENDOR_RSTCLK_RESET0_CLR_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_RESET0_CLR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_RESET0_CLR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844408ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_RESET0_CLR (CVMX_ADD_IO_SEG(0x00010F0000844408ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_RESET0_SET CVMX_ENDOR_RSTCLK_RESET0_SET_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_RESET0_SET_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_RESET0_SET not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844404ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_RESET0_SET (CVMX_ADD_IO_SEG(0x00010F0000844404ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_RESET0_STATE CVMX_ENDOR_RSTCLK_RESET0_STATE_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_RESET0_STATE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_RESET0_STATE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844400ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_RESET0_STATE (CVMX_ADD_IO_SEG(0x00010F0000844400ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_RESET1_CLR CVMX_ENDOR_RSTCLK_RESET1_CLR_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_RESET1_CLR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_RESET1_CLR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844418ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_RESET1_CLR (CVMX_ADD_IO_SEG(0x00010F0000844418ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_RESET1_SET CVMX_ENDOR_RSTCLK_RESET1_SET_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_RESET1_SET_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_RESET1_SET not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844414ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_RESET1_SET (CVMX_ADD_IO_SEG(0x00010F0000844414ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_RESET1_STATE CVMX_ENDOR_RSTCLK_RESET1_STATE_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_RESET1_STATE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_RESET1_STATE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844410ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_RESET1_STATE (CVMX_ADD_IO_SEG(0x00010F0000844410ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_SW_INTR_CLR CVMX_ENDOR_RSTCLK_SW_INTR_CLR_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_SW_INTR_CLR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_SW_INTR_CLR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844588ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_SW_INTR_CLR (CVMX_ADD_IO_SEG(0x00010F0000844588ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_SW_INTR_SET CVMX_ENDOR_RSTCLK_SW_INTR_SET_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_SW_INTR_SET_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_SW_INTR_SET not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844584ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_SW_INTR_SET (CVMX_ADD_IO_SEG(0x00010F0000844584ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_SW_INTR_STATUS CVMX_ENDOR_RSTCLK_SW_INTR_STATUS_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_SW_INTR_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_SW_INTR_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844580ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_SW_INTR_STATUS (CVMX_ADD_IO_SEG(0x00010F0000844580ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_TIMER_CTL CVMX_ENDOR_RSTCLK_TIMER_CTL_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_TIMER_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_TIMER_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844500ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_TIMER_CTL (CVMX_ADD_IO_SEG(0x00010F0000844500ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_TIMER_INTR_CLR CVMX_ENDOR_RSTCLK_TIMER_INTR_CLR_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_TIMER_INTR_CLR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_TIMER_INTR_CLR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844534ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_TIMER_INTR_CLR (CVMX_ADD_IO_SEG(0x00010F0000844534ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_TIMER_INTR_STATUS CVMX_ENDOR_RSTCLK_TIMER_INTR_STATUS_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_TIMER_INTR_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_TIMER_INTR_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844530ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_TIMER_INTR_STATUS (CVMX_ADD_IO_SEG(0x00010F0000844530ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_TIMER_MAX CVMX_ENDOR_RSTCLK_TIMER_MAX_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_TIMER_MAX_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_TIMER_MAX not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844508ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_TIMER_MAX (CVMX_ADD_IO_SEG(0x00010F0000844508ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_TIMER_VALUE CVMX_ENDOR_RSTCLK_TIMER_VALUE_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_TIMER_VALUE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_TIMER_VALUE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844504ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_TIMER_VALUE (CVMX_ADD_IO_SEG(0x00010F0000844504ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ENDOR_RSTCLK_TIMEX_THRD(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_TIMEX_THRD(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010F0000844510ull) + ((offset) & 7) * 4;
+}
+#else
+#define CVMX_ENDOR_RSTCLK_TIMEX_THRD(offset) (CVMX_ADD_IO_SEG(0x00010F0000844510ull) + ((offset) & 7) * 4)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENDOR_RSTCLK_VERSION CVMX_ENDOR_RSTCLK_VERSION_FUNC()
+static inline uint64_t CVMX_ENDOR_RSTCLK_VERSION_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_ENDOR_RSTCLK_VERSION not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010F0000844570ull);
+}
+#else
+#define CVMX_ENDOR_RSTCLK_VERSION (CVMX_ADD_IO_SEG(0x00010F0000844570ull))
+#endif
+
+/**
+ * cvmx_endor_adma_auto_clk_gate
+ */
+union cvmx_endor_adma_auto_clk_gate {
+	uint32_t u32;
+	struct cvmx_endor_adma_auto_clk_gate_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_1_31                : 31;
+	uint32_t auto_gate                    : 1;  /**< 1==enable auto-clock-gating */
+#else
+	uint32_t auto_gate                    : 1;
+	uint32_t reserved_1_31                : 31;
+#endif
+	} s;
+	struct cvmx_endor_adma_auto_clk_gate_s cnf71xx;
+};
+typedef union cvmx_endor_adma_auto_clk_gate cvmx_endor_adma_auto_clk_gate_t;
+
+/**
+ * cvmx_endor_adma_axi_rspcode
+ */
+union cvmx_endor_adma_axi_rspcode {
+	uint32_t u32;
+	struct cvmx_endor_adma_axi_rspcode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_16_31               : 16;
+	uint32_t ch7_axi_rspcode              : 2;  /**< dma \#7 AXI response code */
+	uint32_t ch6_axi_rspcode              : 2;  /**< dma \#6 AXI response code */
+	uint32_t ch5_axi_rspcode              : 2;  /**< dma \#5 AXI response code */
+	uint32_t ch4_axi_rspcode              : 2;  /**< dma \#4 AXI response code */
+	uint32_t ch3_axi_rspcode              : 2;  /**< dma \#3 AXI response code */
+	uint32_t ch2_axi_rspcode              : 2;  /**< dma \#2 AXI response code */
+	uint32_t ch1_axi_rspcode              : 2;  /**< dma \#1 AXI response code */
+	uint32_t ch0_axi_rspcode              : 2;  /**< dma \#0 AXI response code */
+#else
+	uint32_t ch0_axi_rspcode              : 2;
+	uint32_t ch1_axi_rspcode              : 2;
+	uint32_t ch2_axi_rspcode              : 2;
+	uint32_t ch3_axi_rspcode              : 2;
+	uint32_t ch4_axi_rspcode              : 2;
+	uint32_t ch5_axi_rspcode              : 2;
+	uint32_t ch6_axi_rspcode              : 2;
+	uint32_t ch7_axi_rspcode              : 2;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_endor_adma_axi_rspcode_s  cnf71xx;
+};
+typedef union cvmx_endor_adma_axi_rspcode cvmx_endor_adma_axi_rspcode_t;
+
+/**
+ * cvmx_endor_adma_axi_signal
+ */
+union cvmx_endor_adma_axi_signal {
+	uint32_t u32;
+	struct cvmx_endor_adma_axi_signal_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t awcobuf                      : 1;  /**< ADMA_COBUF */
+	uint32_t reserved_10_23               : 14;
+	uint32_t awlock                       : 2;  /**< ADMA_AWLOCK */
+	uint32_t reserved_2_7                 : 6;
+	uint32_t arlock                       : 2;  /**< ADMA_ARLOCK */
+#else
+	uint32_t arlock                       : 2;
+	uint32_t reserved_2_7                 : 6;
+	uint32_t awlock                       : 2;
+	uint32_t reserved_10_23               : 14;
+	uint32_t awcobuf                      : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} s;
+	struct cvmx_endor_adma_axi_signal_s   cnf71xx;
+};
+typedef union cvmx_endor_adma_axi_signal cvmx_endor_adma_axi_signal_t;
+
+/**
+ * cvmx_endor_adma_axierr_intr
+ */
+union cvmx_endor_adma_axierr_intr {
+	uint32_t u32;
+	struct cvmx_endor_adma_axierr_intr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_1_31                : 31;
+	uint32_t axi_err_int                  : 1;  /**< AXI Error interrupt */
+#else
+	uint32_t axi_err_int                  : 1;
+	uint32_t reserved_1_31                : 31;
+#endif
+	} s;
+	struct cvmx_endor_adma_axierr_intr_s  cnf71xx;
+};
+typedef union cvmx_endor_adma_axierr_intr cvmx_endor_adma_axierr_intr_t;
+
+/**
+ * cvmx_endor_adma_dma#_addr_hi
+ */
+union cvmx_endor_adma_dmax_addr_hi {
+	uint32_t u32;
+	struct cvmx_endor_adma_dmax_addr_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_8_31                : 24;
+	uint32_t hi_addr                      : 8;  /**< dma low address[63:32] */
+#else
+	uint32_t hi_addr                      : 8;
+	uint32_t reserved_8_31                : 24;
+#endif
+	} s;
+	struct cvmx_endor_adma_dmax_addr_hi_s cnf71xx;
+};
+typedef union cvmx_endor_adma_dmax_addr_hi cvmx_endor_adma_dmax_addr_hi_t;
+
+/**
+ * cvmx_endor_adma_dma#_addr_lo
+ */
+union cvmx_endor_adma_dmax_addr_lo {
+	uint32_t u32;
+	struct cvmx_endor_adma_dmax_addr_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t lo_addr                      : 32; /**< dma low address[31:0] */
+#else
+	uint32_t lo_addr                      : 32;
+#endif
+	} s;
+	struct cvmx_endor_adma_dmax_addr_lo_s cnf71xx;
+};
+typedef union cvmx_endor_adma_dmax_addr_lo cvmx_endor_adma_dmax_addr_lo_t;
+
+/**
+ * cvmx_endor_adma_dma#_cfg
+ */
+union cvmx_endor_adma_dmax_cfg {
+	uint32_t u32;
+	struct cvmx_endor_adma_dmax_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t endian                       : 1;  /**< 0==byte-swap, 1==word */
+	uint32_t reserved_18_23               : 6;
+	uint32_t hmm_ofs                      : 2;  /**< HMM memory byte offset */
+	uint32_t reserved_13_15               : 3;
+	uint32_t awcache_lbm                  : 1;  /**< AWCACHE last burst mode, 1==force 0 on the last write data */
+	uint32_t awcache                      : 4;  /**< ADMA_AWCACHE */
+	uint32_t reserved_6_7                 : 2;
+	uint32_t bst_bound                    : 1;  /**< burst boundary (0==4kB, 1==128 byte) */
+	uint32_t max_bstlen                   : 1;  /**< maximum burst length(0==8 dword) */
+	uint32_t reserved_1_3                 : 3;
+	uint32_t enable                       : 1;  /**< 1 == dma enable */
+#else
+	uint32_t enable                       : 1;
+	uint32_t reserved_1_3                 : 3;
+	uint32_t max_bstlen                   : 1;
+	uint32_t bst_bound                    : 1;
+	uint32_t reserved_6_7                 : 2;
+	uint32_t awcache                      : 4;
+	uint32_t awcache_lbm                  : 1;
+	uint32_t reserved_13_15               : 3;
+	uint32_t hmm_ofs                      : 2;
+	uint32_t reserved_18_23               : 6;
+	uint32_t endian                       : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} s;
+	struct cvmx_endor_adma_dmax_cfg_s     cnf71xx;
+};
+typedef union cvmx_endor_adma_dmax_cfg cvmx_endor_adma_dmax_cfg_t;
+
+/**
+ * cvmx_endor_adma_dma#_size
+ */
+union cvmx_endor_adma_dmax_size {
+	uint32_t u32;
+	struct cvmx_endor_adma_dmax_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_18_31               : 14;
+	uint32_t dma_size                     : 18; /**< dma transfer byte size */
+#else
+	uint32_t dma_size                     : 18;
+	uint32_t reserved_18_31               : 14;
+#endif
+	} s;
+	struct cvmx_endor_adma_dmax_size_s    cnf71xx;
+};
+typedef union cvmx_endor_adma_dmax_size cvmx_endor_adma_dmax_size_t;
+
+/**
+ * cvmx_endor_adma_dma_priority
+ */
+union cvmx_endor_adma_dma_priority {
+	uint32_t u32;
+	struct cvmx_endor_adma_dma_priority_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t rdma_rr_prty                 : 1;  /**< 1 == round-robin for DMA read channel */
+	uint32_t wdma_rr_prty                 : 1;  /**< 1 == round-robin for DMA write channel */
+	uint32_t wdma_fix_prty                : 4;  /**< dma fixed priority */
+#else
+	uint32_t wdma_fix_prty                : 4;
+	uint32_t wdma_rr_prty                 : 1;
+	uint32_t rdma_rr_prty                 : 1;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_adma_dma_priority_s cnf71xx;
+};
+typedef union cvmx_endor_adma_dma_priority cvmx_endor_adma_dma_priority_t;
+
+/**
+ * cvmx_endor_adma_dma_reset
+ */
+union cvmx_endor_adma_dma_reset {
+	uint32_t u32;
+	struct cvmx_endor_adma_dma_reset_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_8_31                : 24;
+	uint32_t dma_ch_reset                 : 8;  /**< dma channel reset */
+#else
+	uint32_t dma_ch_reset                 : 8;
+	uint32_t reserved_8_31                : 24;
+#endif
+	} s;
+	struct cvmx_endor_adma_dma_reset_s    cnf71xx;
+};
+typedef union cvmx_endor_adma_dma_reset cvmx_endor_adma_dma_reset_t;
+
+/**
+ * cvmx_endor_adma_dmadone_intr
+ */
+union cvmx_endor_adma_dmadone_intr {
+	uint32_t u32;
+	struct cvmx_endor_adma_dmadone_intr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_8_31                : 24;
+	uint32_t dma_ch_done                  : 8;  /**< done-interrupt status of the DMA channel */
+#else
+	uint32_t dma_ch_done                  : 8;
+	uint32_t reserved_8_31                : 24;
+#endif
+	} s;
+	struct cvmx_endor_adma_dmadone_intr_s cnf71xx;
+};
+typedef union cvmx_endor_adma_dmadone_intr cvmx_endor_adma_dmadone_intr_t;
+
+/**
+ * cvmx_endor_adma_intr_dis
+ */
+union cvmx_endor_adma_intr_dis {
+	uint32_t u32;
+	struct cvmx_endor_adma_intr_dis_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_17_31               : 15;
+	uint32_t axierr_intr_dis              : 1;  /**< AXI Error interrupt disable (1==enable) */
+	uint32_t dmadone_intr_dis             : 16; /**< dma done interrupt disable (1==enable) */
+#else
+	uint32_t dmadone_intr_dis             : 16;
+	uint32_t axierr_intr_dis              : 1;
+	uint32_t reserved_17_31               : 15;
+#endif
+	} s;
+	struct cvmx_endor_adma_intr_dis_s     cnf71xx;
+};
+typedef union cvmx_endor_adma_intr_dis cvmx_endor_adma_intr_dis_t;
+
+/**
+ * cvmx_endor_adma_intr_enb
+ */
+union cvmx_endor_adma_intr_enb {
+	uint32_t u32;
+	struct cvmx_endor_adma_intr_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_17_31               : 15;
+	uint32_t axierr_intr_enb              : 1;  /**< AXI Error interrupt enable (1==enable) */
+	uint32_t dmadone_intr_enb             : 16; /**< dma done interrupt enable (1==enable) */
+#else
+	uint32_t dmadone_intr_enb             : 16;
+	uint32_t axierr_intr_enb              : 1;
+	uint32_t reserved_17_31               : 15;
+#endif
+	} s;
+	struct cvmx_endor_adma_intr_enb_s     cnf71xx;
+};
+typedef union cvmx_endor_adma_intr_enb cvmx_endor_adma_intr_enb_t;
+
+/**
+ * cvmx_endor_adma_module_status
+ */
+union cvmx_endor_adma_module_status {
+	uint32_t u32;
+	struct cvmx_endor_adma_module_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_16_31               : 16;
+	uint32_t non_dmardch_stt              : 1;  /**< non-DMA read channel status */
+	uint32_t non_dmawrch_stt              : 1;  /**< non-DMA write channel status (1==transfer in progress) */
+	uint32_t dma_ch_stt                   : 14; /**< dma channel status (1==transfer in progress)
+                                                         blah, blah */
+#else
+	uint32_t dma_ch_stt                   : 14;
+	uint32_t non_dmawrch_stt              : 1;
+	uint32_t non_dmardch_stt              : 1;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_endor_adma_module_status_s cnf71xx;
+};
+typedef union cvmx_endor_adma_module_status cvmx_endor_adma_module_status_t;
+
+/**
+ * cvmx_endor_intc_cntl_hi#
+ *
+ * ENDOR_INTC_CNTL_HI - Interrupt Enable HI
+ *
+ */
+union cvmx_endor_intc_cntl_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_cntl_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_1_31                : 31;
+	uint32_t enab                         : 1;  /**< Interrupt Enable */
+#else
+	uint32_t enab                         : 1;
+	uint32_t reserved_1_31                : 31;
+#endif
+	} s;
+	struct cvmx_endor_intc_cntl_hix_s     cnf71xx;
+};
+typedef union cvmx_endor_intc_cntl_hix cvmx_endor_intc_cntl_hix_t;
+
+/**
+ * cvmx_endor_intc_cntl_lo#
+ *
+ * ENDOR_INTC_CNTL_LO - Interrupt Enable LO
+ *
+ */
+union cvmx_endor_intc_cntl_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_cntl_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_1_31                : 31;
+	uint32_t enab                         : 1;  /**< Interrupt Enable */
+#else
+	uint32_t enab                         : 1;
+	uint32_t reserved_1_31                : 31;
+#endif
+	} s;
+	struct cvmx_endor_intc_cntl_lox_s     cnf71xx;
+};
+typedef union cvmx_endor_intc_cntl_lox cvmx_endor_intc_cntl_lox_t;
+
+/**
+ * cvmx_endor_intc_index_hi#
+ *
+ * ENDOR_INTC_INDEX_HI - Overall Index HI
+ *
+ */
+union cvmx_endor_intc_index_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_index_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_9_31                : 23;
+	uint32_t index                        : 9;  /**< Overall Interrup Index */
+#else
+	uint32_t index                        : 9;
+	uint32_t reserved_9_31                : 23;
+#endif
+	} s;
+	struct cvmx_endor_intc_index_hix_s    cnf71xx;
+};
+typedef union cvmx_endor_intc_index_hix cvmx_endor_intc_index_hix_t;
+
+/**
+ * cvmx_endor_intc_index_lo#
+ *
+ * ENDOR_INTC_INDEX_LO - Overall Index LO
+ *
+ */
+union cvmx_endor_intc_index_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_index_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_9_31                : 23;
+	uint32_t index                        : 9;  /**< Overall Interrup Index */
+#else
+	uint32_t index                        : 9;
+	uint32_t reserved_9_31                : 23;
+#endif
+	} s;
+	struct cvmx_endor_intc_index_lox_s    cnf71xx;
+};
+typedef union cvmx_endor_intc_index_lox cvmx_endor_intc_index_lox_t;
+
+/**
+ * cvmx_endor_intc_misc_idx_hi#
+ *
+ * ENDOR_INTC_MISC_IDX_HI - Misc Group Index HI
+ *
+ */
+union cvmx_endor_intc_misc_idx_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_misc_idx_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t grpidx                       : 6;  /**< Misc Group Interrupt Index */
+#else
+	uint32_t grpidx                       : 6;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_intc_misc_idx_hix_s cnf71xx;
+};
+typedef union cvmx_endor_intc_misc_idx_hix cvmx_endor_intc_misc_idx_hix_t;
+
+/**
+ * cvmx_endor_intc_misc_idx_lo#
+ *
+ * ENDOR_INTC_MISC_IDX_LO - Misc Group Index LO
+ *
+ */
+union cvmx_endor_intc_misc_idx_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_misc_idx_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t grpidx                       : 6;  /**< Misc Group Interrupt Index */
+#else
+	uint32_t grpidx                       : 6;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_intc_misc_idx_lox_s cnf71xx;
+};
+typedef union cvmx_endor_intc_misc_idx_lox cvmx_endor_intc_misc_idx_lox_t;
+
+/**
+ * cvmx_endor_intc_misc_mask_hi#
+ *
+ * ENDOR_INTC_MISC_MASK_HI = Interrupt MISC Group Mask
+ *
+ */
+union cvmx_endor_intc_misc_mask_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_misc_mask_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t rf_rx_ppssync                : 1;  /**< RX PPS Sync Done */
+	uint32_t rf_rx_spiskip                : 1;  /**< RX SPI Event Skipped */
+	uint32_t rf_spi3                      : 1;  /**< SPI Transfer Done Event 3 */
+	uint32_t rf_spi2                      : 1;  /**< SPI Transfer Done Event 2 */
+	uint32_t rf_spi1                      : 1;  /**< SPI Transfer Done Event 1 */
+	uint32_t rf_spi0                      : 1;  /**< SPI Transfer Done Event 0 */
+	uint32_t rf_rx_strx                   : 1;  /**< RX Start RX */
+	uint32_t rf_rx_stframe                : 1;  /**< RX Start Frame */
+	uint32_t rf_rxd_ffflag                : 1;  /**< RX DIV FIFO flags asserted */
+	uint32_t rf_rxd_ffthresh              : 1;  /**< RX DIV FIFO Threshhold reached */
+	uint32_t rf_rx_ffflag                 : 1;  /**< RX FIFO flags asserted */
+	uint32_t rf_rx_ffthresh               : 1;  /**< RX FIFO Threshhold reached */
+	uint32_t tti_timer                    : 8;  /**< TTI Timer Interrupt */
+	uint32_t axi_berr                     : 1;  /**< AXI Bus Error */
+	uint32_t rfspi                        : 1;  /**< RFSPI Interrupt */
+	uint32_t ifftpapr                     : 1;  /**< IFFTPAPR HAB Interrupt */
+	uint32_t h3genc                       : 1;  /**< 3G Encoder HAB Interrupt */
+	uint32_t lteenc                       : 1;  /**< LTE Encoder HAB Interrupt */
+	uint32_t vdec                         : 1;  /**< Viterbi Decoder HAB Interrupt */
+	uint32_t turbo_rddone                 : 1;  /**< TURBO Decoder HAB Read Done */
+	uint32_t turbo_done                   : 1;  /**< TURBO Decoder HAB Done */
+	uint32_t turbo                        : 1;  /**< TURBO Decoder HAB Interrupt */
+	uint32_t dftdmp                       : 1;  /**< DFTDMP HAB Interrupt */
+	uint32_t rach                         : 1;  /**< RACH HAB Interrupt */
+	uint32_t ulfe                         : 1;  /**< ULFE HAB Interrupt */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rach                         : 1;
+	uint32_t dftdmp                       : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_done                   : 1;
+	uint32_t turbo_rddone                 : 1;
+	uint32_t vdec                         : 1;
+	uint32_t lteenc                       : 1;
+	uint32_t h3genc                       : 1;
+	uint32_t ifftpapr                     : 1;
+	uint32_t rfspi                        : 1;
+	uint32_t axi_berr                     : 1;
+	uint32_t tti_timer                    : 8;
+	uint32_t rf_rx_ffthresh               : 1;
+	uint32_t rf_rx_ffflag                 : 1;
+	uint32_t rf_rxd_ffthresh              : 1;
+	uint32_t rf_rxd_ffflag                : 1;
+	uint32_t rf_rx_stframe                : 1;
+	uint32_t rf_rx_strx                   : 1;
+	uint32_t rf_spi0                      : 1;
+	uint32_t rf_spi1                      : 1;
+	uint32_t rf_spi2                      : 1;
+	uint32_t rf_spi3                      : 1;
+	uint32_t rf_rx_spiskip                : 1;
+	uint32_t rf_rx_ppssync                : 1;
+#endif
+	} s;
+	struct cvmx_endor_intc_misc_mask_hix_s cnf71xx;
+};
+typedef union cvmx_endor_intc_misc_mask_hix cvmx_endor_intc_misc_mask_hix_t;
+
+/**
+ * cvmx_endor_intc_misc_mask_lo#
+ *
+ * ENDOR_INTC_MISC_MASK_LO = Interrupt MISC Group Mask
+ *
+ */
+union cvmx_endor_intc_misc_mask_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_misc_mask_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t rf_rx_ppssync                : 1;  /**< RX PPS Sync Done */
+	uint32_t rf_rx_spiskip                : 1;  /**< RX SPI Event Skipped */
+	uint32_t rf_spi3                      : 1;  /**< SPI Transfer Done Event 3 */
+	uint32_t rf_spi2                      : 1;  /**< SPI Transfer Done Event 2 */
+	uint32_t rf_spi1                      : 1;  /**< SPI Transfer Done Event 1 */
+	uint32_t rf_spi0                      : 1;  /**< SPI Transfer Done Event 0 */
+	uint32_t rf_rx_strx                   : 1;  /**< RX Start RX */
+	uint32_t rf_rx_stframe                : 1;  /**< RX Start Frame */
+	uint32_t rf_rxd_ffflag                : 1;  /**< RX DIV FIFO flags asserted */
+	uint32_t rf_rxd_ffthresh              : 1;  /**< RX DIV FIFO Threshhold reached */
+	uint32_t rf_rx_ffflag                 : 1;  /**< RX FIFO flags asserted */
+	uint32_t rf_rx_ffthresh               : 1;  /**< RX FIFO Threshhold reached */
+	uint32_t tti_timer                    : 8;  /**< TTI Timer Interrupt */
+	uint32_t axi_berr                     : 1;  /**< AXI Bus Error */
+	uint32_t rfspi                        : 1;  /**< RFSPI Interrupt */
+	uint32_t ifftpapr                     : 1;  /**< IFFTPAPR HAB Interrupt */
+	uint32_t h3genc                       : 1;  /**< 3G Encoder HAB Interrupt */
+	uint32_t lteenc                       : 1;  /**< LTE Encoder HAB Interrupt */
+	uint32_t vdec                         : 1;  /**< Viterbi Decoder HAB Interrupt */
+	uint32_t turbo_rddone                 : 1;  /**< TURBO Decoder HAB Read Done */
+	uint32_t turbo_done                   : 1;  /**< TURBO Decoder HAB Done */
+	uint32_t turbo                        : 1;  /**< TURBO Decoder HAB Interrupt */
+	uint32_t dftdmp                       : 1;  /**< DFTDMP HAB Interrupt */
+	uint32_t rach                         : 1;  /**< RACH HAB Interrupt */
+	uint32_t ulfe                         : 1;  /**< ULFE HAB Interrupt */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rach                         : 1;
+	uint32_t dftdmp                       : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_done                   : 1;
+	uint32_t turbo_rddone                 : 1;
+	uint32_t vdec                         : 1;
+	uint32_t lteenc                       : 1;
+	uint32_t h3genc                       : 1;
+	uint32_t ifftpapr                     : 1;
+	uint32_t rfspi                        : 1;
+	uint32_t axi_berr                     : 1;
+	uint32_t tti_timer                    : 8;
+	uint32_t rf_rx_ffthresh               : 1;
+	uint32_t rf_rx_ffflag                 : 1;
+	uint32_t rf_rxd_ffthresh              : 1;
+	uint32_t rf_rxd_ffflag                : 1;
+	uint32_t rf_rx_stframe                : 1;
+	uint32_t rf_rx_strx                   : 1;
+	uint32_t rf_spi0                      : 1;
+	uint32_t rf_spi1                      : 1;
+	uint32_t rf_spi2                      : 1;
+	uint32_t rf_spi3                      : 1;
+	uint32_t rf_rx_spiskip                : 1;
+	uint32_t rf_rx_ppssync                : 1;
+#endif
+	} s;
+	struct cvmx_endor_intc_misc_mask_lox_s cnf71xx;
+};
+typedef union cvmx_endor_intc_misc_mask_lox cvmx_endor_intc_misc_mask_lox_t;
+
+/**
+ * cvmx_endor_intc_misc_rint
+ *
+ * ENDOR_INTC_MISC_RINT - MISC Raw Interrupt Status
+ *
+ */
+union cvmx_endor_intc_misc_rint {
+	uint32_t u32;
+	struct cvmx_endor_intc_misc_rint_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t rf_rx_ppssync                : 1;  /**< RX PPS Sync Done */
+	uint32_t rf_rx_spiskip                : 1;  /**< RX SPI Event Skipped */
+	uint32_t rf_spi3                      : 1;  /**< SPI Transfer Done Event 3 */
+	uint32_t rf_spi2                      : 1;  /**< SPI Transfer Done Event 2 */
+	uint32_t rf_spi1                      : 1;  /**< SPI Transfer Done Event 1 */
+	uint32_t rf_spi0                      : 1;  /**< SPI Transfer Done Event 0 */
+	uint32_t rf_rx_strx                   : 1;  /**< RX Start RX */
+	uint32_t rf_rx_stframe                : 1;  /**< RX Start Frame */
+	uint32_t rf_rxd_ffflag                : 1;  /**< RX DIV FIFO flags asserted */
+	uint32_t rf_rxd_ffthresh              : 1;  /**< RX DIV FIFO Threshhold reached */
+	uint32_t rf_rx_ffflag                 : 1;  /**< RX FIFO flags asserted */
+	uint32_t rf_rx_ffthresh               : 1;  /**< RX FIFO Threshhold reached */
+	uint32_t tti_timer                    : 8;  /**< TTI Timer Interrupt */
+	uint32_t axi_berr                     : 1;  /**< AXI Bus Error */
+	uint32_t rfspi                        : 1;  /**< RFSPI Interrupt */
+	uint32_t ifftpapr                     : 1;  /**< IFFTPAPR HAB Interrupt */
+	uint32_t h3genc                       : 1;  /**< 3G Encoder HAB Interrupt */
+	uint32_t lteenc                       : 1;  /**< LTE Encoder HAB Interrupt */
+	uint32_t vdec                         : 1;  /**< Viterbi Decoder HAB Interrupt */
+	uint32_t turbo_rddone                 : 1;  /**< TURBO Decoder HAB Read Done */
+	uint32_t turbo_done                   : 1;  /**< TURBO Decoder HAB Done */
+	uint32_t turbo                        : 1;  /**< TURBO Decoder HAB Interrupt */
+	uint32_t dftdmp                       : 1;  /**< DFTDMP HAB Interrupt */
+	uint32_t rach                         : 1;  /**< RACH HAB Interrupt */
+	uint32_t ulfe                         : 1;  /**< ULFE HAB Interrupt */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rach                         : 1;
+	uint32_t dftdmp                       : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_done                   : 1;
+	uint32_t turbo_rddone                 : 1;
+	uint32_t vdec                         : 1;
+	uint32_t lteenc                       : 1;
+	uint32_t h3genc                       : 1;
+	uint32_t ifftpapr                     : 1;
+	uint32_t rfspi                        : 1;
+	uint32_t axi_berr                     : 1;
+	uint32_t tti_timer                    : 8;
+	uint32_t rf_rx_ffthresh               : 1;
+	uint32_t rf_rx_ffflag                 : 1;
+	uint32_t rf_rxd_ffthresh              : 1;
+	uint32_t rf_rxd_ffflag                : 1;
+	uint32_t rf_rx_stframe                : 1;
+	uint32_t rf_rx_strx                   : 1;
+	uint32_t rf_spi0                      : 1;
+	uint32_t rf_spi1                      : 1;
+	uint32_t rf_spi2                      : 1;
+	uint32_t rf_spi3                      : 1;
+	uint32_t rf_rx_spiskip                : 1;
+	uint32_t rf_rx_ppssync                : 1;
+#endif
+	} s;
+	struct cvmx_endor_intc_misc_rint_s    cnf71xx;
+};
+typedef union cvmx_endor_intc_misc_rint cvmx_endor_intc_misc_rint_t;
+
+/**
+ * cvmx_endor_intc_misc_status_hi#
+ *
+ * ENDOR_INTC_MISC_STATUS_HI = Interrupt MISC Group Mask
+ *
+ */
+union cvmx_endor_intc_misc_status_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_misc_status_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t rf_rx_ppssync                : 1;  /**< RX PPS Sync Done */
+	uint32_t rf_rx_spiskip                : 1;  /**< RX SPI Event Skipped */
+	uint32_t rf_spi3                      : 1;  /**< SPI Transfer Done Event 3 */
+	uint32_t rf_spi2                      : 1;  /**< SPI Transfer Done Event 2 */
+	uint32_t rf_spi1                      : 1;  /**< SPI Transfer Done Event 1 */
+	uint32_t rf_spi0                      : 1;  /**< SPI Transfer Done Event 0 */
+	uint32_t rf_rx_strx                   : 1;  /**< RX Start RX */
+	uint32_t rf_rx_stframe                : 1;  /**< RX Start Frame */
+	uint32_t rf_rxd_ffflag                : 1;  /**< RX DIV FIFO flags asserted */
+	uint32_t rf_rxd_ffthresh              : 1;  /**< RX DIV FIFO Threshhold reached */
+	uint32_t rf_rx_ffflag                 : 1;  /**< RX FIFO flags asserted */
+	uint32_t rf_rx_ffthresh               : 1;  /**< RX FIFO Threshhold reached */
+	uint32_t tti_timer                    : 8;  /**< TTI Timer Interrupt */
+	uint32_t axi_berr                     : 1;  /**< AXI Bus Error */
+	uint32_t rfspi                        : 1;  /**< RFSPI Interrupt */
+	uint32_t ifftpapr                     : 1;  /**< IFFTPAPR HAB Interrupt */
+	uint32_t h3genc                       : 1;  /**< 3G Encoder HAB Interrupt */
+	uint32_t lteenc                       : 1;  /**< LTE Encoder HAB Interrupt */
+	uint32_t vdec                         : 1;  /**< Viterbi Decoder HAB Interrupt */
+	uint32_t turbo_rddone                 : 1;  /**< TURBO Decoder HAB Read Done */
+	uint32_t turbo_done                   : 1;  /**< TURBO Decoder HAB Done */
+	uint32_t turbo                        : 1;  /**< TURBO Decoder HAB Interrupt */
+	uint32_t dftdmp                       : 1;  /**< DFTDMP HAB Interrupt */
+	uint32_t rach                         : 1;  /**< RACH HAB Interrupt */
+	uint32_t ulfe                         : 1;  /**< ULFE HAB Interrupt */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rach                         : 1;
+	uint32_t dftdmp                       : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_done                   : 1;
+	uint32_t turbo_rddone                 : 1;
+	uint32_t vdec                         : 1;
+	uint32_t lteenc                       : 1;
+	uint32_t h3genc                       : 1;
+	uint32_t ifftpapr                     : 1;
+	uint32_t rfspi                        : 1;
+	uint32_t axi_berr                     : 1;
+	uint32_t tti_timer                    : 8;
+	uint32_t rf_rx_ffthresh               : 1;
+	uint32_t rf_rx_ffflag                 : 1;
+	uint32_t rf_rxd_ffthresh              : 1;
+	uint32_t rf_rxd_ffflag                : 1;
+	uint32_t rf_rx_stframe                : 1;
+	uint32_t rf_rx_strx                   : 1;
+	uint32_t rf_spi0                      : 1;
+	uint32_t rf_spi1                      : 1;
+	uint32_t rf_spi2                      : 1;
+	uint32_t rf_spi3                      : 1;
+	uint32_t rf_rx_spiskip                : 1;
+	uint32_t rf_rx_ppssync                : 1;
+#endif
+	} s;
+	struct cvmx_endor_intc_misc_status_hix_s cnf71xx;
+};
+typedef union cvmx_endor_intc_misc_status_hix cvmx_endor_intc_misc_status_hix_t;
+
+/**
+ * cvmx_endor_intc_misc_status_lo#
+ *
+ * ENDOR_INTC_MISC_STATUS_LO = Interrupt MISC Group Mask
+ *
+ */
+union cvmx_endor_intc_misc_status_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_misc_status_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t rf_rx_ppssync                : 1;  /**< RX PPS Sync Done */
+	uint32_t rf_rx_spiskip                : 1;  /**< RX SPI Event Skipped */
+	uint32_t rf_spi3                      : 1;  /**< SPI Transfer Done Event 3 */
+	uint32_t rf_spi2                      : 1;  /**< SPI Transfer Done Event 2 */
+	uint32_t rf_spi1                      : 1;  /**< SPI Transfer Done Event 1 */
+	uint32_t rf_spi0                      : 1;  /**< SPI Transfer Done Event 0 */
+	uint32_t rf_rx_strx                   : 1;  /**< RX Start RX */
+	uint32_t rf_rx_stframe                : 1;  /**< RX Start Frame */
+	uint32_t rf_rxd_ffflag                : 1;  /**< RX DIV FIFO flags asserted */
+	uint32_t rf_rxd_ffthresh              : 1;  /**< RX DIV FIFO Threshhold reached */
+	uint32_t rf_rx_ffflag                 : 1;  /**< RX FIFO flags asserted */
+	uint32_t rf_rx_ffthresh               : 1;  /**< RX FIFO Threshhold reached */
+	uint32_t tti_timer                    : 8;  /**< TTI Timer Interrupt */
+	uint32_t axi_berr                     : 1;  /**< AXI Bus Error */
+	uint32_t rfspi                        : 1;  /**< RFSPI Interrupt */
+	uint32_t ifftpapr                     : 1;  /**< IFFTPAPR HAB Interrupt */
+	uint32_t h3genc                       : 1;  /**< 3G Encoder HAB Interrupt */
+	uint32_t lteenc                       : 1;  /**< LTE Encoder HAB Interrupt */
+	uint32_t vdec                         : 1;  /**< Viterbi Decoder HAB Interrupt */
+	uint32_t turbo_rddone                 : 1;  /**< TURBO Decoder HAB Read Done */
+	uint32_t turbo_done                   : 1;  /**< TURBO Decoder HAB Done */
+	uint32_t turbo                        : 1;  /**< TURBO Decoder HAB Interrupt */
+	uint32_t dftdmp                       : 1;  /**< DFTDMP HAB Interrupt */
+	uint32_t rach                         : 1;  /**< RACH HAB Interrupt */
+	uint32_t ulfe                         : 1;  /**< ULFE HAB Interrupt */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rach                         : 1;
+	uint32_t dftdmp                       : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_done                   : 1;
+	uint32_t turbo_rddone                 : 1;
+	uint32_t vdec                         : 1;
+	uint32_t lteenc                       : 1;
+	uint32_t h3genc                       : 1;
+	uint32_t ifftpapr                     : 1;
+	uint32_t rfspi                        : 1;
+	uint32_t axi_berr                     : 1;
+	uint32_t tti_timer                    : 8;
+	uint32_t rf_rx_ffthresh               : 1;
+	uint32_t rf_rx_ffflag                 : 1;
+	uint32_t rf_rxd_ffthresh              : 1;
+	uint32_t rf_rxd_ffflag                : 1;
+	uint32_t rf_rx_stframe                : 1;
+	uint32_t rf_rx_strx                   : 1;
+	uint32_t rf_spi0                      : 1;
+	uint32_t rf_spi1                      : 1;
+	uint32_t rf_spi2                      : 1;
+	uint32_t rf_spi3                      : 1;
+	uint32_t rf_rx_spiskip                : 1;
+	uint32_t rf_rx_ppssync                : 1;
+#endif
+	} s;
+	struct cvmx_endor_intc_misc_status_lox_s cnf71xx;
+};
+typedef union cvmx_endor_intc_misc_status_lox cvmx_endor_intc_misc_status_lox_t;
+
+/**
+ * cvmx_endor_intc_rd_idx_hi#
+ *
+ * ENDOR_INTC_RD_IDX_HI - Read Done Group Index HI
+ *
+ */
+union cvmx_endor_intc_rd_idx_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_rd_idx_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t grpidx                       : 6;  /**< Read Done Group Interrupt Index */
+#else
+	uint32_t grpidx                       : 6;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_intc_rd_idx_hix_s   cnf71xx;
+};
+typedef union cvmx_endor_intc_rd_idx_hix cvmx_endor_intc_rd_idx_hix_t;
+
+/**
+ * cvmx_endor_intc_rd_idx_lo#
+ *
+ * ENDOR_INTC_RD_IDX_LO - Read Done Group Index LO
+ *
+ */
+union cvmx_endor_intc_rd_idx_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_rd_idx_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t grpidx                       : 6;  /**< Read Done Group Interrupt Index */
+#else
+	uint32_t grpidx                       : 6;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_intc_rd_idx_lox_s   cnf71xx;
+};
+typedef union cvmx_endor_intc_rd_idx_lox cvmx_endor_intc_rd_idx_lox_t;
+
+/**
+ * cvmx_endor_intc_rd_mask_hi#
+ *
+ * ENDOR_INTC_RD_MASK_HI = Interrupt Read Done Group Mask
+ *
+ */
+union cvmx_endor_intc_rd_mask_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_rd_mask_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t t3_rfif_1                    : 1;  /**< RFIF_1 Read Done */
+	uint32_t t3_rfif_0                    : 1;  /**< RFIF_0 Read Done */
+	uint32_t axi_rx1_harq                 : 1;  /**< HARQ to Host Read Done */
+	uint32_t axi_rx1                      : 1;  /**< RX1 to Host Read Done */
+	uint32_t axi_rx0                      : 1;  /**< RX0 to Host Read Done */
+	uint32_t axi_tx                       : 1;  /**< TX to Host Read Done */
+	uint32_t t3_int                       : 1;  /**< TX to PHY Read Done */
+	uint32_t t3_ext                       : 1;  /**< TX to Host Read Done */
+	uint32_t t2_int                       : 1;  /**< RX1 to PHY Read Done */
+	uint32_t t2_harq                      : 1;  /**< HARQ to Host Read Done */
+	uint32_t t2_ext                       : 1;  /**< RX1 to Host Read Done */
+	uint32_t t1_int                       : 1;  /**< RX0 to PHY Read Done */
+	uint32_t t1_ext                       : 1;  /**< RX0 to Host Read Done */
+	uint32_t ifftpapr_rm                  : 1;  /**< IFFTPAPR_RM Read Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Read Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Read Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Read Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Read Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Read Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Read Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Read Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Read Done */
+	uint32_t rachsnif                     : 1;  /**< RACH Read Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Read Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif                     : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t ifftpapr_rm                  : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t axi_tx                       : 1;
+	uint32_t axi_rx0                      : 1;
+	uint32_t axi_rx1                      : 1;
+	uint32_t axi_rx1_harq                 : 1;
+	uint32_t t3_rfif_0                    : 1;
+	uint32_t t3_rfif_1                    : 1;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_intc_rd_mask_hix_s  cnf71xx;
+};
+typedef union cvmx_endor_intc_rd_mask_hix cvmx_endor_intc_rd_mask_hix_t;
+
+/**
+ * cvmx_endor_intc_rd_mask_lo#
+ *
+ * ENDOR_INTC_RD_MASK_LO = Interrupt Read Done Group Mask
+ *
+ */
+union cvmx_endor_intc_rd_mask_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_rd_mask_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t t3_rfif_1                    : 1;  /**< RFIF_1 Read Done */
+	uint32_t t3_rfif_0                    : 1;  /**< RFIF_0 Read Done */
+	uint32_t axi_rx1_harq                 : 1;  /**< HARQ to Host Read Done */
+	uint32_t axi_rx1                      : 1;  /**< RX1 to Host Read Done */
+	uint32_t axi_rx0                      : 1;  /**< RX0 to Host Read Done */
+	uint32_t axi_tx                       : 1;  /**< TX to Host Read Done */
+	uint32_t t3_int                       : 1;  /**< TX to PHY Read Done */
+	uint32_t t3_ext                       : 1;  /**< TX to Host Read Done */
+	uint32_t t2_int                       : 1;  /**< RX1 to PHY Read Done */
+	uint32_t t2_harq                      : 1;  /**< HARQ to Host Read Done */
+	uint32_t t2_ext                       : 1;  /**< RX1 to Host Read Done */
+	uint32_t t1_int                       : 1;  /**< RX0 to PHY Read Done */
+	uint32_t t1_ext                       : 1;  /**< RX0 to Host Read Done */
+	uint32_t ifftpapr_rm                  : 1;  /**< IFFTPAPR_RM Read Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Read Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Read Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Read Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Read Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Read Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Read Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Read Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Read Done */
+	uint32_t rachsnif                     : 1;  /**< RACH Read Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Read Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif                     : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t ifftpapr_rm                  : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t axi_tx                       : 1;
+	uint32_t axi_rx0                      : 1;
+	uint32_t axi_rx1                      : 1;
+	uint32_t axi_rx1_harq                 : 1;
+	uint32_t t3_rfif_0                    : 1;
+	uint32_t t3_rfif_1                    : 1;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_intc_rd_mask_lox_s  cnf71xx;
+};
+typedef union cvmx_endor_intc_rd_mask_lox cvmx_endor_intc_rd_mask_lox_t;
+
+/**
+ * cvmx_endor_intc_rd_rint
+ *
+ * ENDOR_INTC_RD_RINT - Read Done Group Raw Interrupt Status
+ *
+ */
+union cvmx_endor_intc_rd_rint {
+	uint32_t u32;
+	struct cvmx_endor_intc_rd_rint_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t t3_rfif_1                    : 1;  /**< RFIF_1 Read Done */
+	uint32_t t3_rfif_0                    : 1;  /**< RFIF_0 Read Done */
+	uint32_t axi_rx1_harq                 : 1;  /**< HARQ to Host Read Done */
+	uint32_t axi_rx1                      : 1;  /**< RX1 to Host Read Done */
+	uint32_t axi_rx0                      : 1;  /**< RX0 to Host Read Done */
+	uint32_t axi_tx                       : 1;  /**< TX to Host Read Done */
+	uint32_t t3_int                       : 1;  /**< TX to PHY Read Done */
+	uint32_t t3_ext                       : 1;  /**< TX to Host Read Done */
+	uint32_t t2_int                       : 1;  /**< RX1 to PHY Read Done */
+	uint32_t t2_harq                      : 1;  /**< HARQ to Host Read Done */
+	uint32_t t2_ext                       : 1;  /**< RX1 to Host Read Done */
+	uint32_t t1_int                       : 1;  /**< RX0 to PHY Read Done */
+	uint32_t t1_ext                       : 1;  /**< RX0 to Host Read Done */
+	uint32_t ifftpapr_rm                  : 1;  /**< IFFTPAPR_RM Read Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Read Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Read Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Read Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Read Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Read Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Read Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Read Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Read Done */
+	uint32_t rachsnif                     : 1;  /**< RACH Read Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Read Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif                     : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t ifftpapr_rm                  : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t axi_tx                       : 1;
+	uint32_t axi_rx0                      : 1;
+	uint32_t axi_rx1                      : 1;
+	uint32_t axi_rx1_harq                 : 1;
+	uint32_t t3_rfif_0                    : 1;
+	uint32_t t3_rfif_1                    : 1;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_intc_rd_rint_s      cnf71xx;
+};
+typedef union cvmx_endor_intc_rd_rint cvmx_endor_intc_rd_rint_t;
+
+/**
+ * cvmx_endor_intc_rd_status_hi#
+ *
+ * ENDOR_INTC_RD_STATUS_HI = Interrupt Read Done Group Mask
+ *
+ */
+union cvmx_endor_intc_rd_status_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_rd_status_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t t3_rfif_1                    : 1;  /**< RFIF_1 Read Done */
+	uint32_t t3_rfif_0                    : 1;  /**< RFIF_0 Read Done */
+	uint32_t axi_rx1_harq                 : 1;  /**< HARQ to Host Read Done */
+	uint32_t axi_rx1                      : 1;  /**< RX1 to Host Read Done */
+	uint32_t axi_rx0                      : 1;  /**< RX0 to Host Read Done */
+	uint32_t axi_tx                       : 1;  /**< TX to Host Read Done */
+	uint32_t t3_int                       : 1;  /**< TX to PHY Read Done */
+	uint32_t t3_ext                       : 1;  /**< TX to Host Read Done */
+	uint32_t t2_int                       : 1;  /**< RX1 to PHY Read Done */
+	uint32_t t2_harq                      : 1;  /**< HARQ to Host Read Done */
+	uint32_t t2_ext                       : 1;  /**< RX1 to Host Read Done */
+	uint32_t t1_int                       : 1;  /**< RX0 to PHY Read Done */
+	uint32_t t1_ext                       : 1;  /**< RX0 to Host Read Done */
+	uint32_t ifftpapr_rm                  : 1;  /**< IFFTPAPR_RM Read Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Read Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Read Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Read Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Read Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Read Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Read Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Read Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Read Done */
+	uint32_t rachsnif                     : 1;  /**< RACH Read Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Read Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif                     : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t ifftpapr_rm                  : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t axi_tx                       : 1;
+	uint32_t axi_rx0                      : 1;
+	uint32_t axi_rx1                      : 1;
+	uint32_t axi_rx1_harq                 : 1;
+	uint32_t t3_rfif_0                    : 1;
+	uint32_t t3_rfif_1                    : 1;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_intc_rd_status_hix_s cnf71xx;
+};
+typedef union cvmx_endor_intc_rd_status_hix cvmx_endor_intc_rd_status_hix_t;
+
+/**
+ * cvmx_endor_intc_rd_status_lo#
+ *
+ * ENDOR_INTC_RD_STATUS_LO = Interrupt Read Done Group Mask
+ *
+ */
+union cvmx_endor_intc_rd_status_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_rd_status_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t t3_rfif_1                    : 1;  /**< RFIF_1 Read Done */
+	uint32_t t3_rfif_0                    : 1;  /**< RFIF_0 Read Done */
+	uint32_t axi_rx1_harq                 : 1;  /**< HARQ to Host Read Done */
+	uint32_t axi_rx1                      : 1;  /**< RX1 to Host Read Done */
+	uint32_t axi_rx0                      : 1;  /**< RX0 to Host Read Done */
+	uint32_t axi_tx                       : 1;  /**< TX to Host Read Done */
+	uint32_t t3_int                       : 1;  /**< TX to PHY Read Done */
+	uint32_t t3_ext                       : 1;  /**< TX to Host Read Done */
+	uint32_t t2_int                       : 1;  /**< RX1 to PHY Read Done */
+	uint32_t t2_harq                      : 1;  /**< HARQ to Host Read Done */
+	uint32_t t2_ext                       : 1;  /**< RX1 to Host Read Done */
+	uint32_t t1_int                       : 1;  /**< RX0 to PHY Read Done */
+	uint32_t t1_ext                       : 1;  /**< RX0 to Host Read Done */
+	uint32_t ifftpapr_rm                  : 1;  /**< IFFTPAPR_RM Read Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Read Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Read Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Read Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Read Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Read Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Read Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Read Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Read Done */
+	uint32_t rachsnif                     : 1;  /**< RACH Read Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Read Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif                     : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t ifftpapr_rm                  : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t axi_tx                       : 1;
+	uint32_t axi_rx0                      : 1;
+	uint32_t axi_rx1                      : 1;
+	uint32_t axi_rx1_harq                 : 1;
+	uint32_t t3_rfif_0                    : 1;
+	uint32_t t3_rfif_1                    : 1;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_intc_rd_status_lox_s cnf71xx;
+};
+typedef union cvmx_endor_intc_rd_status_lox cvmx_endor_intc_rd_status_lox_t;
+
+/**
+ * cvmx_endor_intc_rdq_idx_hi#
+ *
+ * ENDOR_INTC_RDQ_IDX_HI - Read Queue Done Group Index HI
+ *
+ */
+union cvmx_endor_intc_rdq_idx_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_rdq_idx_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t grpidx                       : 6;  /**< Read Queue Done Group Interrupt Index */
+#else
+	uint32_t grpidx                       : 6;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_intc_rdq_idx_hix_s  cnf71xx;
+};
+typedef union cvmx_endor_intc_rdq_idx_hix cvmx_endor_intc_rdq_idx_hix_t;
+
+/**
+ * cvmx_endor_intc_rdq_idx_lo#
+ *
+ * ENDOR_INTC_RDQ_IDX_LO - Read Queue Done Group Index LO
+ *
+ */
+union cvmx_endor_intc_rdq_idx_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_rdq_idx_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t grpidx                       : 6;  /**< Read Queue Done Group Interrupt Index */
+#else
+	uint32_t grpidx                       : 6;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_intc_rdq_idx_lox_s  cnf71xx;
+};
+typedef union cvmx_endor_intc_rdq_idx_lox cvmx_endor_intc_rdq_idx_lox_t;
+
+/**
+ * cvmx_endor_intc_rdq_mask_hi#
+ *
+ * ENDOR_INTC_RDQ_MASK_HI = Interrupt Read Queue Done Group Mask
+ *
+ */
+union cvmx_endor_intc_rdq_mask_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_rdq_mask_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t t3_rfif_1                    : 1;  /**< RFIF_1 Read Done */
+	uint32_t t3_rfif_0                    : 1;  /**< RFIF_0 Read Done */
+	uint32_t axi_rx1_harq                 : 1;  /**< HARQ to Host Read Done */
+	uint32_t axi_rx1                      : 1;  /**< RX1 to Host Read Done */
+	uint32_t axi_rx0                      : 1;  /**< RX0 to Host Read Done */
+	uint32_t axi_tx                       : 1;  /**< TX to Host Read Done */
+	uint32_t t3_int                       : 1;  /**< TX to PHY Read Done */
+	uint32_t t3_ext                       : 1;  /**< TX to Host Read Done */
+	uint32_t t2_int                       : 1;  /**< RX1 to PHY Read Done */
+	uint32_t t2_harq                      : 1;  /**< HARQ to Host Read Done */
+	uint32_t t2_ext                       : 1;  /**< RX1 to Host Read Done */
+	uint32_t t1_int                       : 1;  /**< RX0 to PHY Read Done */
+	uint32_t t1_ext                       : 1;  /**< RX0 to Host Read Done */
+	uint32_t ifftpapr_rm                  : 1;  /**< IFFTPAPR_RM Read Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Read Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Read Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Read Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Read Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Read Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Read Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Read Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Read Done */
+	uint32_t rachsnif                     : 1;  /**< RACH Read Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Read Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif                     : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t ifftpapr_rm                  : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t axi_tx                       : 1;
+	uint32_t axi_rx0                      : 1;
+	uint32_t axi_rx1                      : 1;
+	uint32_t axi_rx1_harq                 : 1;
+	uint32_t t3_rfif_0                    : 1;
+	uint32_t t3_rfif_1                    : 1;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_intc_rdq_mask_hix_s cnf71xx;
+};
+typedef union cvmx_endor_intc_rdq_mask_hix cvmx_endor_intc_rdq_mask_hix_t;
+
+/**
+ * cvmx_endor_intc_rdq_mask_lo#
+ *
+ * ENDOR_INTC_RDQ_MASK_LO = Interrupt Read Queue Done Group Mask
+ *
+ */
+union cvmx_endor_intc_rdq_mask_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_rdq_mask_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t t3_rfif_1                    : 1;  /**< RFIF_1 Read Done */
+	uint32_t t3_rfif_0                    : 1;  /**< RFIF_0 Read Done */
+	uint32_t axi_rx1_harq                 : 1;  /**< HARQ to Host Read Done */
+	uint32_t axi_rx1                      : 1;  /**< RX1 to Host Read Done */
+	uint32_t axi_rx0                      : 1;  /**< RX0 to Host Read Done */
+	uint32_t axi_tx                       : 1;  /**< TX to Host Read Done */
+	uint32_t t3_int                       : 1;  /**< TX to PHY Read Done */
+	uint32_t t3_ext                       : 1;  /**< TX to Host Read Done */
+	uint32_t t2_int                       : 1;  /**< RX1 to PHY Read Done */
+	uint32_t t2_harq                      : 1;  /**< HARQ to Host Read Done */
+	uint32_t t2_ext                       : 1;  /**< RX1 to Host Read Done */
+	uint32_t t1_int                       : 1;  /**< RX0 to PHY Read Done */
+	uint32_t t1_ext                       : 1;  /**< RX0 to Host Read Done */
+	uint32_t ifftpapr_rm                  : 1;  /**< IFFTPAPR_RM Read Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Read Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Read Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Read Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Read Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Read Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Read Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Read Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Read Done */
+	uint32_t rachsnif                     : 1;  /**< RACH Read Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Read Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif                     : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t ifftpapr_rm                  : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t axi_tx                       : 1;
+	uint32_t axi_rx0                      : 1;
+	uint32_t axi_rx1                      : 1;
+	uint32_t axi_rx1_harq                 : 1;
+	uint32_t t3_rfif_0                    : 1;
+	uint32_t t3_rfif_1                    : 1;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_intc_rdq_mask_lox_s cnf71xx;
+};
+typedef union cvmx_endor_intc_rdq_mask_lox cvmx_endor_intc_rdq_mask_lox_t;
+
+/**
+ * cvmx_endor_intc_rdq_rint
+ *
+ * ENDOR_INTC_RDQ_RINT - Read Queue Done Group Raw Interrupt Status
+ *
+ */
+union cvmx_endor_intc_rdq_rint {
+	uint32_t u32;
+	struct cvmx_endor_intc_rdq_rint_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t t3_rfif_1                    : 1;  /**< RFIF_1 Read Done */
+	uint32_t t3_rfif_0                    : 1;  /**< RFIF_0 Read Done */
+	uint32_t axi_rx1_harq                 : 1;  /**< HARQ to Host Read Done */
+	uint32_t axi_rx1                      : 1;  /**< RX1 to Host Read Done */
+	uint32_t axi_rx0                      : 1;  /**< RX0 to Host Read Done */
+	uint32_t axi_tx                       : 1;  /**< TX to Host Read Done */
+	uint32_t t3_int                       : 1;  /**< TX to PHY Read Done */
+	uint32_t t3_ext                       : 1;  /**< TX to Host Read Done */
+	uint32_t t2_int                       : 1;  /**< RX1 to PHY Read Done */
+	uint32_t t2_harq                      : 1;  /**< HARQ to Host Read Done */
+	uint32_t t2_ext                       : 1;  /**< RX1 to Host Read Done */
+	uint32_t t1_int                       : 1;  /**< RX0 to PHY Read Done */
+	uint32_t t1_ext                       : 1;  /**< RX0 to Host Read Done */
+	uint32_t ifftpapr_rm                  : 1;  /**< IFFTPAPR_RM Read Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Read Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Read Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Read Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Read Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Read Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Read Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Read Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Read Done */
+	uint32_t rachsnif                     : 1;  /**< RACH Read Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Read Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif                     : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t ifftpapr_rm                  : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t axi_tx                       : 1;
+	uint32_t axi_rx0                      : 1;
+	uint32_t axi_rx1                      : 1;
+	uint32_t axi_rx1_harq                 : 1;
+	uint32_t t3_rfif_0                    : 1;
+	uint32_t t3_rfif_1                    : 1;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_intc_rdq_rint_s     cnf71xx;
+};
+typedef union cvmx_endor_intc_rdq_rint cvmx_endor_intc_rdq_rint_t;
+
+/**
+ * cvmx_endor_intc_rdq_status_hi#
+ *
+ * ENDOR_INTC_RDQ_STATUS_HI = Interrupt Read Queue Done Group Mask
+ *
+ */
+union cvmx_endor_intc_rdq_status_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_rdq_status_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t t3_rfif_1                    : 1;  /**< RFIF_1 Read Done */
+	uint32_t t3_rfif_0                    : 1;  /**< RFIF_0 Read Done */
+	uint32_t axi_rx1_harq                 : 1;  /**< HARQ to Host Read Done */
+	uint32_t axi_rx1                      : 1;  /**< RX1 to Host Read Done */
+	uint32_t axi_rx0                      : 1;  /**< RX0 to Host Read Done */
+	uint32_t axi_tx                       : 1;  /**< TX to Host Read Done */
+	uint32_t t3_int                       : 1;  /**< TX to PHY Read Done */
+	uint32_t t3_ext                       : 1;  /**< TX to Host Read Done */
+	uint32_t t2_int                       : 1;  /**< RX1 to PHY Read Done */
+	uint32_t t2_harq                      : 1;  /**< HARQ to Host Read Done */
+	uint32_t t2_ext                       : 1;  /**< RX1 to Host Read Done */
+	uint32_t t1_int                       : 1;  /**< RX0 to PHY Read Done */
+	uint32_t t1_ext                       : 1;  /**< RX0 to Host Read Done */
+	uint32_t ifftpapr_rm                  : 1;  /**< IFFTPAPR_RM Read Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Read Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Read Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Read Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Read Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Read Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Read Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Read Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Read Done */
+	uint32_t rachsnif                     : 1;  /**< RACH Read Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Read Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif                     : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t ifftpapr_rm                  : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t axi_tx                       : 1;
+	uint32_t axi_rx0                      : 1;
+	uint32_t axi_rx1                      : 1;
+	uint32_t axi_rx1_harq                 : 1;
+	uint32_t t3_rfif_0                    : 1;
+	uint32_t t3_rfif_1                    : 1;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_intc_rdq_status_hix_s cnf71xx;
+};
+typedef union cvmx_endor_intc_rdq_status_hix cvmx_endor_intc_rdq_status_hix_t;
+
+/**
+ * cvmx_endor_intc_rdq_status_lo#
+ *
+ * ENDOR_INTC_RDQ_STATUS_LO = Interrupt Read Queue Done Group Mask
+ *
+ */
+union cvmx_endor_intc_rdq_status_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_rdq_status_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t t3_rfif_1                    : 1;  /**< RFIF_1 Read Done */
+	uint32_t t3_rfif_0                    : 1;  /**< RFIF_0 Read Done */
+	uint32_t axi_rx1_harq                 : 1;  /**< HARQ to Host Read Done */
+	uint32_t axi_rx1                      : 1;  /**< RX1 to Host Read Done */
+	uint32_t axi_rx0                      : 1;  /**< RX0 to Host Read Done */
+	uint32_t axi_tx                       : 1;  /**< TX to Host Read Done */
+	uint32_t t3_int                       : 1;  /**< TX to PHY Read Done */
+	uint32_t t3_ext                       : 1;  /**< TX to Host Read Done */
+	uint32_t t2_int                       : 1;  /**< RX1 to PHY Read Done */
+	uint32_t t2_harq                      : 1;  /**< HARQ to Host Read Done */
+	uint32_t t2_ext                       : 1;  /**< RX1 to Host Read Done */
+	uint32_t t1_int                       : 1;  /**< RX0 to PHY Read Done */
+	uint32_t t1_ext                       : 1;  /**< RX0 to Host Read Done */
+	uint32_t ifftpapr_rm                  : 1;  /**< IFFTPAPR_RM Read Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Read Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Read Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Read Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Read Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Read Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Read Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Read Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Read Done */
+	uint32_t rachsnif                     : 1;  /**< RACH Read Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Read Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif                     : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t ifftpapr_rm                  : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t axi_tx                       : 1;
+	uint32_t axi_rx0                      : 1;
+	uint32_t axi_rx1                      : 1;
+	uint32_t axi_rx1_harq                 : 1;
+	uint32_t t3_rfif_0                    : 1;
+	uint32_t t3_rfif_1                    : 1;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_intc_rdq_status_lox_s cnf71xx;
+};
+typedef union cvmx_endor_intc_rdq_status_lox cvmx_endor_intc_rdq_status_lox_t;
+
+/**
+ * cvmx_endor_intc_stat_hi#
+ *
+ * ENDOR_INTC_STAT_HI - Grouped Interrupt Status HI
+ *
+ */
+union cvmx_endor_intc_stat_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_stat_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t misc                         : 1;  /**< Misc Group Interrupt */
+	uint32_t sw                           : 1;  /**< SW Group Interrupt */
+	uint32_t wrqdone                      : 1;  /**< Write  Queue Done Group Interrupt */
+	uint32_t rdqdone                      : 1;  /**< Read  Queue Done Group Interrupt */
+	uint32_t rddone                       : 1;  /**< Read  Done Group Interrupt */
+	uint32_t wrdone                       : 1;  /**< Write Done Group Interrupt */
+#else
+	uint32_t wrdone                       : 1;
+	uint32_t rddone                       : 1;
+	uint32_t rdqdone                      : 1;
+	uint32_t wrqdone                      : 1;
+	uint32_t sw                           : 1;
+	uint32_t misc                         : 1;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_intc_stat_hix_s     cnf71xx;
+};
+typedef union cvmx_endor_intc_stat_hix cvmx_endor_intc_stat_hix_t;
+
+/**
+ * cvmx_endor_intc_stat_lo#
+ *
+ * ENDOR_INTC_STAT_LO - Grouped Interrupt Status LO
+ *
+ */
+union cvmx_endor_intc_stat_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_stat_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t misc                         : 1;  /**< Misc Group Interrupt */
+	uint32_t sw                           : 1;  /**< SW Group Interrupt */
+	uint32_t wrqdone                      : 1;  /**< Write  Queue Done Group Interrupt */
+	uint32_t rdqdone                      : 1;  /**< Read  Queue Done Group Interrupt */
+	uint32_t rddone                       : 1;  /**< Read  Done Group Interrupt */
+	uint32_t wrdone                       : 1;  /**< Write Done Group Interrupt */
+#else
+	uint32_t wrdone                       : 1;
+	uint32_t rddone                       : 1;
+	uint32_t rdqdone                      : 1;
+	uint32_t wrqdone                      : 1;
+	uint32_t sw                           : 1;
+	uint32_t misc                         : 1;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_intc_stat_lox_s     cnf71xx;
+};
+typedef union cvmx_endor_intc_stat_lox cvmx_endor_intc_stat_lox_t;
+
+/**
+ * cvmx_endor_intc_sw_idx_hi#
+ *
+ * ENDOR_INTC_SW_IDX_HI - SW Group Index HI
+ *
+ */
+union cvmx_endor_intc_sw_idx_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_sw_idx_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t grpidx                       : 6;  /**< SW Group Interrupt Index */
+#else
+	uint32_t grpidx                       : 6;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_intc_sw_idx_hix_s   cnf71xx;
+};
+typedef union cvmx_endor_intc_sw_idx_hix cvmx_endor_intc_sw_idx_hix_t;
+
+/**
+ * cvmx_endor_intc_sw_idx_lo#
+ *
+ * ENDOR_INTC_SW_IDX_LO - SW Group Index LO
+ *
+ */
+union cvmx_endor_intc_sw_idx_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_sw_idx_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t grpidx                       : 6;  /**< SW Group Interrupt Index */
+#else
+	uint32_t grpidx                       : 6;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_intc_sw_idx_lox_s   cnf71xx;
+};
+typedef union cvmx_endor_intc_sw_idx_lox cvmx_endor_intc_sw_idx_lox_t;
+
+/**
+ * cvmx_endor_intc_sw_mask_hi#
+ *
+ * ENDOR_INTC_SW_MASK_HI = Interrupt SW Mask
+ *
+ */
+union cvmx_endor_intc_sw_mask_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_sw_mask_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t swint                        : 32; /**< ULFE Read Done */
+#else
+	uint32_t swint                        : 32;
+#endif
+	} s;
+	struct cvmx_endor_intc_sw_mask_hix_s  cnf71xx;
+};
+typedef union cvmx_endor_intc_sw_mask_hix cvmx_endor_intc_sw_mask_hix_t;
+
+/**
+ * cvmx_endor_intc_sw_mask_lo#
+ *
+ * ENDOR_INTC_SW_MASK_LO = Interrupt SW Mask
+ *
+ */
+union cvmx_endor_intc_sw_mask_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_sw_mask_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t swint                        : 32; /**< ULFE Read Done */
+#else
+	uint32_t swint                        : 32;
+#endif
+	} s;
+	struct cvmx_endor_intc_sw_mask_lox_s  cnf71xx;
+};
+typedef union cvmx_endor_intc_sw_mask_lox cvmx_endor_intc_sw_mask_lox_t;
+
+/**
+ * cvmx_endor_intc_sw_rint
+ *
+ * ENDOR_INTC_SW_RINT - SW Raw Interrupt Status
+ *
+ */
+union cvmx_endor_intc_sw_rint {
+	uint32_t u32;
+	struct cvmx_endor_intc_sw_rint_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t swint                        : 32; /**< ULFE Read Done */
+#else
+	uint32_t swint                        : 32;
+#endif
+	} s;
+	struct cvmx_endor_intc_sw_rint_s      cnf71xx;
+};
+typedef union cvmx_endor_intc_sw_rint cvmx_endor_intc_sw_rint_t;
+
+/**
+ * cvmx_endor_intc_sw_status_hi#
+ *
+ * ENDOR_INTC_SW_STATUS_HI = Interrupt SW Mask
+ *
+ */
+union cvmx_endor_intc_sw_status_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_sw_status_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t swint                        : 32; /**< ULFE Read Done */
+#else
+	uint32_t swint                        : 32;
+#endif
+	} s;
+	struct cvmx_endor_intc_sw_status_hix_s cnf71xx;
+};
+typedef union cvmx_endor_intc_sw_status_hix cvmx_endor_intc_sw_status_hix_t;
+
+/**
+ * cvmx_endor_intc_sw_status_lo#
+ *
+ * ENDOR_INTC_SW_STATUS_LO = Interrupt SW Mask
+ *
+ */
+union cvmx_endor_intc_sw_status_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_sw_status_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t swint                        : 32; /**< ULFE Read Done */
+#else
+	uint32_t swint                        : 32;
+#endif
+	} s;
+	struct cvmx_endor_intc_sw_status_lox_s cnf71xx;
+};
+typedef union cvmx_endor_intc_sw_status_lox cvmx_endor_intc_sw_status_lox_t;
+
+/**
+ * cvmx_endor_intc_swclr
+ *
+ * ENDOR_INTC_SWCLR- SW Interrupt Clear
+ *
+ */
+union cvmx_endor_intc_swclr {
+	uint32_t u32;
+	struct cvmx_endor_intc_swclr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t clr                          : 32; /**< Clear SW Interrupt bit */
+#else
+	uint32_t clr                          : 32;
+#endif
+	} s;
+	struct cvmx_endor_intc_swclr_s        cnf71xx;
+};
+typedef union cvmx_endor_intc_swclr cvmx_endor_intc_swclr_t;
+
+/**
+ * cvmx_endor_intc_swset
+ *
+ * ENDOR_INTC_SWSET - SW Interrupt Set
+ *
+ */
+union cvmx_endor_intc_swset {
+	uint32_t u32;
+	struct cvmx_endor_intc_swset_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t set                          : 32; /**< Set SW Interrupt bit */
+#else
+	uint32_t set                          : 32;
+#endif
+	} s;
+	struct cvmx_endor_intc_swset_s        cnf71xx;
+};
+typedef union cvmx_endor_intc_swset cvmx_endor_intc_swset_t;
+
+/**
+ * cvmx_endor_intc_wr_idx_hi#
+ *
+ * ENDOR_INTC_WR_IDX_HI - Write Done Group Index HI
+ *
+ */
+union cvmx_endor_intc_wr_idx_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_wr_idx_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t grpidx                       : 6;  /**< Write Done Group Interrupt Index */
+#else
+	uint32_t grpidx                       : 6;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_intc_wr_idx_hix_s   cnf71xx;
+};
+typedef union cvmx_endor_intc_wr_idx_hix cvmx_endor_intc_wr_idx_hix_t;
+
+/**
+ * cvmx_endor_intc_wr_idx_lo#
+ *
+ * ENDOR_INTC_WR_IDX_LO - Write Done Group Index LO
+ *
+ */
+union cvmx_endor_intc_wr_idx_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_wr_idx_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t grpidx                       : 6;  /**< Write Done Group Interrupt Index */
+#else
+	uint32_t grpidx                       : 6;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_intc_wr_idx_lox_s   cnf71xx;
+};
+typedef union cvmx_endor_intc_wr_idx_lox cvmx_endor_intc_wr_idx_lox_t;
+
+/**
+ * cvmx_endor_intc_wr_mask_hi#
+ *
+ * ENDOR_INTC_WR_MASK_HI = Interrupt Write Done Group Mask
+ *
+ */
+union cvmx_endor_intc_wr_mask_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_wr_mask_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_29_31               : 3;
+	uint32_t t1_rfif_1                    : 1;  /**< RFIF_1 Write Done */
+	uint32_t t1_rfif_0                    : 1;  /**< RFIF_0 Write Done */
+	uint32_t axi_rx1_harq                 : 1;  /**< HARQ to Host Write Done */
+	uint32_t axi_rx1                      : 1;  /**< RX1 to Host Write Done */
+	uint32_t axi_rx0                      : 1;  /**< RX0 to Host Write Done */
+	uint32_t axi_tx                       : 1;  /**< TX to Host Write Done */
+	uint32_t t3_instr                     : 1;  /**< TX Instr Write Done */
+	uint32_t t3_int                       : 1;  /**< PHY to TX Write Done */
+	uint32_t t3_ext                       : 1;  /**< Host to TX Write Done */
+	uint32_t t2_instr                     : 1;  /**< RX1 Instr Write Done */
+	uint32_t t2_harq                      : 1;  /**< Host to HARQ Write Done */
+	uint32_t t2_int                       : 1;  /**< PHY to RX1 Write Done */
+	uint32_t t2_ext                       : 1;  /**< Host to RX1 Write Done */
+	uint32_t t1_instr                     : 1;  /**< RX0 Instr Write Done */
+	uint32_t t1_int                       : 1;  /**< PHY to RX0 Write Done */
+	uint32_t t1_ext                       : 1;  /**< Host to RX0 Write Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Write Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Write Done */
+	uint32_t lteenc_cch                   : 1;  /**< LTE Encoder CCH Write Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Write Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Write Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Write Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Write Done */
+	uint32_t turbo_sb                     : 1;  /**< Turbo Decoder Soft Bits Write Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Write Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Write Done */
+	uint32_t rachsnif_1                   : 1;  /**< RACH_1 Write Done */
+	uint32_t rachsnif_0                   : 1;  /**< RACH_0 Write Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Write Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif_0                   : 1;
+	uint32_t rachsnif_1                   : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_sb                     : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t lteenc_cch                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t1_instr                     : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_instr                     : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t t3_instr                     : 1;
+	uint32_t axi_tx                       : 1;
+	uint32_t axi_rx0                      : 1;
+	uint32_t axi_rx1                      : 1;
+	uint32_t axi_rx1_harq                 : 1;
+	uint32_t t1_rfif_0                    : 1;
+	uint32_t t1_rfif_1                    : 1;
+	uint32_t reserved_29_31               : 3;
+#endif
+	} s;
+	struct cvmx_endor_intc_wr_mask_hix_s  cnf71xx;
+};
+typedef union cvmx_endor_intc_wr_mask_hix cvmx_endor_intc_wr_mask_hix_t;
+
+/**
+ * cvmx_endor_intc_wr_mask_lo#
+ *
+ * ENDOR_INTC_WR_MASK_LO = Interrupt Write Done Group Mask
+ *
+ */
+union cvmx_endor_intc_wr_mask_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_wr_mask_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_29_31               : 3;
+	uint32_t t1_rfif_1                    : 1;  /**< RFIF_1 Write Done */
+	uint32_t t1_rfif_0                    : 1;  /**< RFIF_0 Write Done */
+	uint32_t axi_rx1_harq                 : 1;  /**< HARQ to Host Write Done */
+	uint32_t axi_rx1                      : 1;  /**< RX1 to Host Write Done */
+	uint32_t axi_rx0                      : 1;  /**< RX0 to Host Write Done */
+	uint32_t axi_tx                       : 1;  /**< TX to Host Write Done */
+	uint32_t t3_instr                     : 1;  /**< TX Instr Write Done */
+	uint32_t t3_int                       : 1;  /**< PHY to TX Write Done */
+	uint32_t t3_ext                       : 1;  /**< Host to TX Write Done */
+	uint32_t t2_instr                     : 1;  /**< RX1 Instr Write Done */
+	uint32_t t2_harq                      : 1;  /**< Host to HARQ Write Done */
+	uint32_t t2_int                       : 1;  /**< PHY to RX1 Write Done */
+	uint32_t t2_ext                       : 1;  /**< Host to RX1 Write Done */
+	uint32_t t1_instr                     : 1;  /**< RX0 Instr Write Done */
+	uint32_t t1_int                       : 1;  /**< PHY to RX0 Write Done */
+	uint32_t t1_ext                       : 1;  /**< Host to RX0 Write Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Write Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Write Done */
+	uint32_t lteenc_cch                   : 1;  /**< LTE Encoder CCH Write Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Write Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Write Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Write Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Write Done */
+	uint32_t turbo_sb                     : 1;  /**< Turbo Decoder Soft Bits Write Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Write Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Write Done */
+	uint32_t rachsnif_1                   : 1;  /**< RACH_1 Write Done */
+	uint32_t rachsnif_0                   : 1;  /**< RACH_0 Write Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Write Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif_0                   : 1;
+	uint32_t rachsnif_1                   : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_sb                     : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t lteenc_cch                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t1_instr                     : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_instr                     : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t t3_instr                     : 1;
+	uint32_t axi_tx                       : 1;
+	uint32_t axi_rx0                      : 1;
+	uint32_t axi_rx1                      : 1;
+	uint32_t axi_rx1_harq                 : 1;
+	uint32_t t1_rfif_0                    : 1;
+	uint32_t t1_rfif_1                    : 1;
+	uint32_t reserved_29_31               : 3;
+#endif
+	} s;
+	struct cvmx_endor_intc_wr_mask_lox_s  cnf71xx;
+};
+typedef union cvmx_endor_intc_wr_mask_lox cvmx_endor_intc_wr_mask_lox_t;
+
+/**
+ * cvmx_endor_intc_wr_rint
+ *
+ * ENDOR_INTC_WR_RINT - Write Done Group Raw Interrupt Status
+ *
+ */
+union cvmx_endor_intc_wr_rint {
+	uint32_t u32;
+	struct cvmx_endor_intc_wr_rint_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_29_31               : 3;
+	uint32_t t1_rfif_1                    : 1;  /**< RFIF_1 Write Done */
+	uint32_t t1_rfif_0                    : 1;  /**< RFIF_0 Write Done */
+	uint32_t axi_rx1_harq                 : 1;  /**< HARQ to Host Write Done */
+	uint32_t axi_rx1                      : 1;  /**< RX1 to Host Write Done */
+	uint32_t axi_rx0                      : 1;  /**< RX0 to Host Write Done */
+	uint32_t axi_tx                       : 1;  /**< TX to Host Write Done */
+	uint32_t t3_instr                     : 1;  /**< TX Instr Write Done */
+	uint32_t t3_int                       : 1;  /**< PHY to TX Write Done */
+	uint32_t t3_ext                       : 1;  /**< Host to TX Write Done */
+	uint32_t t2_instr                     : 1;  /**< RX1 Instr Write Done */
+	uint32_t t2_harq                      : 1;  /**< Host to HARQ Write Done */
+	uint32_t t2_int                       : 1;  /**< PHY to RX1 Write Done */
+	uint32_t t2_ext                       : 1;  /**< Host to RX1 Write Done */
+	uint32_t t1_instr                     : 1;  /**< RX0 Instr Write Done */
+	uint32_t t1_int                       : 1;  /**< PHY to RX0 Write Done */
+	uint32_t t1_ext                       : 1;  /**< Host to RX0 Write Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Write Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Write Done */
+	uint32_t lteenc_cch                   : 1;  /**< LTE Encoder CCH Write Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Write Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Write Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Write Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Write Done */
+	uint32_t turbo_sb                     : 1;  /**< Turbo Decoder Soft Bits Write Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Write Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Write Done */
+	uint32_t rachsnif_1                   : 1;  /**< RACH_1 Write Done */
+	uint32_t rachsnif_0                   : 1;  /**< RACH_0 Write Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Write Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif_0                   : 1;
+	uint32_t rachsnif_1                   : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_sb                     : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t lteenc_cch                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t1_instr                     : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_instr                     : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t t3_instr                     : 1;
+	uint32_t axi_tx                       : 1;
+	uint32_t axi_rx0                      : 1;
+	uint32_t axi_rx1                      : 1;
+	uint32_t axi_rx1_harq                 : 1;
+	uint32_t t1_rfif_0                    : 1;
+	uint32_t t1_rfif_1                    : 1;
+	uint32_t reserved_29_31               : 3;
+#endif
+	} s;
+	struct cvmx_endor_intc_wr_rint_s      cnf71xx;
+};
+typedef union cvmx_endor_intc_wr_rint cvmx_endor_intc_wr_rint_t;
+
+/**
+ * cvmx_endor_intc_wr_status_hi#
+ *
+ * ENDOR_INTC_WR_STATUS_HI = Interrupt Write Done Group Mask
+ *
+ */
+union cvmx_endor_intc_wr_status_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_wr_status_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_29_31               : 3;
+	uint32_t t1_rfif_1                    : 1;  /**< RFIF_1 Write Done */
+	uint32_t t1_rfif_0                    : 1;  /**< RFIF_0 Write Done */
+	uint32_t axi_rx1_harq                 : 1;  /**< HARQ to Host Write Done */
+	uint32_t axi_rx1                      : 1;  /**< RX1 to Host Write Done */
+	uint32_t axi_rx0                      : 1;  /**< RX0 to Host Write Done */
+	uint32_t axi_tx                       : 1;  /**< TX to Host Write Done */
+	uint32_t t3_instr                     : 1;  /**< TX Instr Write Done */
+	uint32_t t3_int                       : 1;  /**< PHY to TX Write Done */
+	uint32_t t3_ext                       : 1;  /**< Host to TX Write Done */
+	uint32_t t2_instr                     : 1;  /**< RX1 Instr Write Done */
+	uint32_t t2_harq                      : 1;  /**< Host to HARQ Write Done */
+	uint32_t t2_int                       : 1;  /**< PHY to RX1 Write Done */
+	uint32_t t2_ext                       : 1;  /**< Host to RX1 Write Done */
+	uint32_t t1_instr                     : 1;  /**< RX0 Instr Write Done */
+	uint32_t t1_int                       : 1;  /**< PHY to RX0 Write Done */
+	uint32_t t1_ext                       : 1;  /**< Host to RX0 Write Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Write Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Write Done */
+	uint32_t lteenc_cch                   : 1;  /**< LTE Encoder CCH Write Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Write Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Write Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Write Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Write Done */
+	uint32_t turbo_sb                     : 1;  /**< Turbo Decoder Soft Bits Write Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Write Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Write Done */
+	uint32_t rachsnif_1                   : 1;  /**< RACH_1 Write Done */
+	uint32_t rachsnif_0                   : 1;  /**< RACH_0 Write Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Write Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif_0                   : 1;
+	uint32_t rachsnif_1                   : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_sb                     : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t lteenc_cch                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t1_instr                     : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_instr                     : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t t3_instr                     : 1;
+	uint32_t axi_tx                       : 1;
+	uint32_t axi_rx0                      : 1;
+	uint32_t axi_rx1                      : 1;
+	uint32_t axi_rx1_harq                 : 1;
+	uint32_t t1_rfif_0                    : 1;
+	uint32_t t1_rfif_1                    : 1;
+	uint32_t reserved_29_31               : 3;
+#endif
+	} s;
+	struct cvmx_endor_intc_wr_status_hix_s cnf71xx;
+};
+typedef union cvmx_endor_intc_wr_status_hix cvmx_endor_intc_wr_status_hix_t;
+
+/**
+ * cvmx_endor_intc_wr_status_lo#
+ *
+ * ENDOR_INTC_WR_STATUS_LO = Interrupt Write Done Group Mask
+ *
+ */
+union cvmx_endor_intc_wr_status_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_wr_status_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_29_31               : 3;
+	uint32_t t1_rfif_1                    : 1;  /**< RFIF_1 Write Done */
+	uint32_t t1_rfif_0                    : 1;  /**< RFIF_0 Write Done */
+	uint32_t axi_rx1_harq                 : 1;  /**< HARQ to Host Write Done */
+	uint32_t axi_rx1                      : 1;  /**< RX1 to Host Write Done */
+	uint32_t axi_rx0                      : 1;  /**< RX0 to Host Write Done */
+	uint32_t axi_tx                       : 1;  /**< TX to Host Write Done */
+	uint32_t t3_instr                     : 1;  /**< TX Instr Write Done */
+	uint32_t t3_int                       : 1;  /**< PHY to TX Write Done */
+	uint32_t t3_ext                       : 1;  /**< Host to TX Write Done */
+	uint32_t t2_instr                     : 1;  /**< RX1 Instr Write Done */
+	uint32_t t2_harq                      : 1;  /**< Host to HARQ Write Done */
+	uint32_t t2_int                       : 1;  /**< PHY to RX1 Write Done */
+	uint32_t t2_ext                       : 1;  /**< Host to RX1 Write Done */
+	uint32_t t1_instr                     : 1;  /**< RX0 Instr Write Done */
+	uint32_t t1_int                       : 1;  /**< PHY to RX0 Write Done */
+	uint32_t t1_ext                       : 1;  /**< Host to RX0 Write Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Write Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Write Done */
+	uint32_t lteenc_cch                   : 1;  /**< LTE Encoder CCH Write Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Write Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Write Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Write Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Write Done */
+	uint32_t turbo_sb                     : 1;  /**< Turbo Decoder Soft Bits Write Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Write Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Write Done */
+	uint32_t rachsnif_1                   : 1;  /**< RACH_1 Write Done */
+	uint32_t rachsnif_0                   : 1;  /**< RACH_0 Write Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Write Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif_0                   : 1;
+	uint32_t rachsnif_1                   : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_sb                     : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t lteenc_cch                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t1_instr                     : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_instr                     : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t t3_instr                     : 1;
+	uint32_t axi_tx                       : 1;
+	uint32_t axi_rx0                      : 1;
+	uint32_t axi_rx1                      : 1;
+	uint32_t axi_rx1_harq                 : 1;
+	uint32_t t1_rfif_0                    : 1;
+	uint32_t t1_rfif_1                    : 1;
+	uint32_t reserved_29_31               : 3;
+#endif
+	} s;
+	struct cvmx_endor_intc_wr_status_lox_s cnf71xx;
+};
+typedef union cvmx_endor_intc_wr_status_lox cvmx_endor_intc_wr_status_lox_t;
+
+/**
+ * cvmx_endor_intc_wrq_idx_hi#
+ *
+ * ENDOR_INTC_WRQ_IDX_HI - Write Queue Done Group Index HI
+ *
+ */
+union cvmx_endor_intc_wrq_idx_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_wrq_idx_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t grpidx                       : 6;  /**< Write Queue Done Group Interrupt Index */
+#else
+	uint32_t grpidx                       : 6;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_intc_wrq_idx_hix_s  cnf71xx;
+};
+typedef union cvmx_endor_intc_wrq_idx_hix cvmx_endor_intc_wrq_idx_hix_t;
+
+/**
+ * cvmx_endor_intc_wrq_idx_lo#
+ *
+ * ENDOR_INTC_WRQ_IDX_LO - Write Queue Done Group Index LO
+ *
+ */
+union cvmx_endor_intc_wrq_idx_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_wrq_idx_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t grpidx                       : 6;  /**< Write Queue Done Group Interrupt Index */
+#else
+	uint32_t grpidx                       : 6;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_intc_wrq_idx_lox_s  cnf71xx;
+};
+typedef union cvmx_endor_intc_wrq_idx_lox cvmx_endor_intc_wrq_idx_lox_t;
+
+/**
+ * cvmx_endor_intc_wrq_mask_hi#
+ *
+ * ENDOR_INTC_WRQ_MASK_HI = Interrupt Write Queue Done Group Mask
+ *
+ */
+union cvmx_endor_intc_wrq_mask_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_wrq_mask_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_23_31               : 9;
+	uint32_t t3_instr                     : 1;  /**< TX Instr Write Done */
+	uint32_t t3_int                       : 1;  /**< PHY to TX Write Done */
+	uint32_t t3_ext                       : 1;  /**< Host to TX Write Done */
+	uint32_t t2_instr                     : 1;  /**< RX1 Instr Write Done */
+	uint32_t t2_harq                      : 1;  /**< Host to HARQ Write Done */
+	uint32_t t2_int                       : 1;  /**< PHY to RX1 Write Done */
+	uint32_t t2_ext                       : 1;  /**< Host to RX1 Write Done */
+	uint32_t t1_instr                     : 1;  /**< RX0 Instr Write Done */
+	uint32_t t1_int                       : 1;  /**< PHY to RX0 Write Done */
+	uint32_t t1_ext                       : 1;  /**< Host to RX0 Write Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Write Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Write Done */
+	uint32_t lteenc_cch                   : 1;  /**< LTE Encoder CCH Write Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Write Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Write Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Write Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Write Done */
+	uint32_t turbo_sb                     : 1;  /**< Turbo Decoder Soft Bits Write Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Write Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Write Done */
+	uint32_t rachsnif_1                   : 1;  /**< RACH_1 Write Done */
+	uint32_t rachsnif_0                   : 1;  /**< RACH_0 Write Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Write Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif_0                   : 1;
+	uint32_t rachsnif_1                   : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_sb                     : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t lteenc_cch                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t1_instr                     : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_instr                     : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t t3_instr                     : 1;
+	uint32_t reserved_23_31               : 9;
+#endif
+	} s;
+	struct cvmx_endor_intc_wrq_mask_hix_s cnf71xx;
+};
+typedef union cvmx_endor_intc_wrq_mask_hix cvmx_endor_intc_wrq_mask_hix_t;
+
+/**
+ * cvmx_endor_intc_wrq_mask_lo#
+ *
+ * ENDOR_INTC_WRQ_MASK_LO = Interrupt Write Queue Done Group Mask
+ *
+ */
+union cvmx_endor_intc_wrq_mask_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_wrq_mask_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_23_31               : 9;
+	uint32_t t3_instr                     : 1;  /**< TX Instr Write Done */
+	uint32_t t3_int                       : 1;  /**< PHY to TX Write Done */
+	uint32_t t3_ext                       : 1;  /**< Host to TX Write Done */
+	uint32_t t2_instr                     : 1;  /**< RX1 Instr Write Done */
+	uint32_t t2_harq                      : 1;  /**< Host to HARQ Write Done */
+	uint32_t t2_int                       : 1;  /**< PHY to RX1 Write Done */
+	uint32_t t2_ext                       : 1;  /**< Host to RX1 Write Done */
+	uint32_t t1_instr                     : 1;  /**< RX0 Instr Write Done */
+	uint32_t t1_int                       : 1;  /**< PHY to RX0 Write Done */
+	uint32_t t1_ext                       : 1;  /**< Host to RX0 Write Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Write Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Write Done */
+	uint32_t lteenc_cch                   : 1;  /**< LTE Encoder CCH Write Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Write Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Write Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Write Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Write Done */
+	uint32_t turbo_sb                     : 1;  /**< Turbo Decoder Soft Bits Write Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Write Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Write Done */
+	uint32_t rachsnif_1                   : 1;  /**< RACH_1 Write Done */
+	uint32_t rachsnif_0                   : 1;  /**< RACH_0 Write Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Write Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif_0                   : 1;
+	uint32_t rachsnif_1                   : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_sb                     : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t lteenc_cch                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t1_instr                     : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_instr                     : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t t3_instr                     : 1;
+	uint32_t reserved_23_31               : 9;
+#endif
+	} s;
+	struct cvmx_endor_intc_wrq_mask_lox_s cnf71xx;
+};
+typedef union cvmx_endor_intc_wrq_mask_lox cvmx_endor_intc_wrq_mask_lox_t;
+
+/**
+ * cvmx_endor_intc_wrq_rint
+ *
+ * ENDOR_INTC_WRQ_RINT - Write Queue Done Group Raw Interrupt Status
+ *
+ */
+union cvmx_endor_intc_wrq_rint {
+	uint32_t u32;
+	struct cvmx_endor_intc_wrq_rint_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_23_31               : 9;
+	uint32_t t3_instr                     : 1;  /**< TX Instr Write Done */
+	uint32_t t3_int                       : 1;  /**< PHY to TX Write Done */
+	uint32_t t3_ext                       : 1;  /**< Host to TX Write Done */
+	uint32_t t2_instr                     : 1;  /**< RX1 Instr Write Done */
+	uint32_t t2_harq                      : 1;  /**< Host to HARQ Write Done */
+	uint32_t t2_int                       : 1;  /**< PHY to RX1 Write Done */
+	uint32_t t2_ext                       : 1;  /**< Host to RX1 Write Done */
+	uint32_t t1_instr                     : 1;  /**< RX0 Instr Write Done */
+	uint32_t t1_int                       : 1;  /**< PHY to RX0 Write Done */
+	uint32_t t1_ext                       : 1;  /**< Host to RX0 Write Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Write Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Write Done */
+	uint32_t lteenc_cch                   : 1;  /**< LTE Encoder CCH Write Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Write Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Write Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Write Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Write Done */
+	uint32_t turbo_sb                     : 1;  /**< Turbo Decoder Soft Bits Write Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Write Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Write Done */
+	uint32_t rachsnif_1                   : 1;  /**< RACH_1 Write Done */
+	uint32_t rachsnif_0                   : 1;  /**< RACH_0 Write Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Write Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif_0                   : 1;
+	uint32_t rachsnif_1                   : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_sb                     : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t lteenc_cch                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t1_instr                     : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_instr                     : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t t3_instr                     : 1;
+	uint32_t reserved_23_31               : 9;
+#endif
+	} s;
+	struct cvmx_endor_intc_wrq_rint_s     cnf71xx;
+};
+typedef union cvmx_endor_intc_wrq_rint cvmx_endor_intc_wrq_rint_t;
+
+/**
+ * cvmx_endor_intc_wrq_status_hi#
+ *
+ * ENDOR_INTC_WRQ_STATUS_HI = Interrupt Write Queue Done Group Mask
+ *
+ */
+union cvmx_endor_intc_wrq_status_hix {
+	uint32_t u32;
+	struct cvmx_endor_intc_wrq_status_hix_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_23_31               : 9;
+	uint32_t t3_instr                     : 1;  /**< TX Instr Write Done */
+	uint32_t t3_int                       : 1;  /**< PHY to TX Write Done */
+	uint32_t t3_ext                       : 1;  /**< Host to TX Write Done */
+	uint32_t t2_instr                     : 1;  /**< RX1 Instr Write Done */
+	uint32_t t2_harq                      : 1;  /**< Host to HARQ Write Done */
+	uint32_t t2_int                       : 1;  /**< PHY to RX1 Write Done */
+	uint32_t t2_ext                       : 1;  /**< Host to RX1 Write Done */
+	uint32_t t1_instr                     : 1;  /**< RX0 Instr Write Done */
+	uint32_t t1_int                       : 1;  /**< PHY to RX0 Write Done */
+	uint32_t t1_ext                       : 1;  /**< Host to RX0 Write Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Write Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Write Done */
+	uint32_t lteenc_cch                   : 1;  /**< LTE Encoder CCH Write Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Write Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Write Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Write Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Write Done */
+	uint32_t turbo_sb                     : 1;  /**< Turbo Decoder Soft Bits Write Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Write Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Write Done */
+	uint32_t rachsnif_1                   : 1;  /**< RACH_1 Write Done */
+	uint32_t rachsnif_0                   : 1;  /**< RACH_0 Write Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Write Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif_0                   : 1;
+	uint32_t rachsnif_1                   : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_sb                     : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t lteenc_cch                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t1_instr                     : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_instr                     : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t t3_instr                     : 1;
+	uint32_t reserved_23_31               : 9;
+#endif
+	} s;
+	struct cvmx_endor_intc_wrq_status_hix_s cnf71xx;
+};
+typedef union cvmx_endor_intc_wrq_status_hix cvmx_endor_intc_wrq_status_hix_t;
+
+/**
+ * cvmx_endor_intc_wrq_status_lo#
+ *
+ * ENDOR_INTC_WRQ_STATUS_LO = Interrupt Write Queue Done Group Mask
+ *
+ */
+union cvmx_endor_intc_wrq_status_lox {
+	uint32_t u32;
+	struct cvmx_endor_intc_wrq_status_lox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_23_31               : 9;
+	uint32_t t3_instr                     : 1;  /**< TX Instr Write Done */
+	uint32_t t3_int                       : 1;  /**< PHY to TX Write Done */
+	uint32_t t3_ext                       : 1;  /**< Host to TX Write Done */
+	uint32_t t2_instr                     : 1;  /**< RX1 Instr Write Done */
+	uint32_t t2_harq                      : 1;  /**< Host to HARQ Write Done */
+	uint32_t t2_int                       : 1;  /**< PHY to RX1 Write Done */
+	uint32_t t2_ext                       : 1;  /**< Host to RX1 Write Done */
+	uint32_t t1_instr                     : 1;  /**< RX0 Instr Write Done */
+	uint32_t t1_int                       : 1;  /**< PHY to RX0 Write Done */
+	uint32_t t1_ext                       : 1;  /**< Host to RX0 Write Done */
+	uint32_t ifftpapr_1                   : 1;  /**< IFFTPAPR_1 Write Done */
+	uint32_t ifftpapr_0                   : 1;  /**< IFFTPAPR_0 Write Done */
+	uint32_t lteenc_cch                   : 1;  /**< LTE Encoder CCH Write Done */
+	uint32_t lteenc_tb1                   : 1;  /**< LTE Encoder TB1 Write Done */
+	uint32_t lteenc_tb0                   : 1;  /**< LTE Encoder TB0 Write Done */
+	uint32_t vitbdec                      : 1;  /**< Viterbi Decoder Write Done */
+	uint32_t turbo_hq                     : 1;  /**< Turbo Decoder HARQ Write Done */
+	uint32_t turbo_sb                     : 1;  /**< Turbo Decoder Soft Bits Write Done */
+	uint32_t turbo                        : 1;  /**< Turbo Decoder Write Done */
+	uint32_t dftdm                        : 1;  /**< DFT/Demapper Write Done */
+	uint32_t rachsnif_1                   : 1;  /**< RACH_1 Write Done */
+	uint32_t rachsnif_0                   : 1;  /**< RACH_0 Write Done */
+	uint32_t ulfe                         : 1;  /**< ULFE Write Done */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachsnif_0                   : 1;
+	uint32_t rachsnif_1                   : 1;
+	uint32_t dftdm                        : 1;
+	uint32_t turbo                        : 1;
+	uint32_t turbo_sb                     : 1;
+	uint32_t turbo_hq                     : 1;
+	uint32_t vitbdec                      : 1;
+	uint32_t lteenc_tb0                   : 1;
+	uint32_t lteenc_tb1                   : 1;
+	uint32_t lteenc_cch                   : 1;
+	uint32_t ifftpapr_0                   : 1;
+	uint32_t ifftpapr_1                   : 1;
+	uint32_t t1_ext                       : 1;
+	uint32_t t1_int                       : 1;
+	uint32_t t1_instr                     : 1;
+	uint32_t t2_ext                       : 1;
+	uint32_t t2_int                       : 1;
+	uint32_t t2_harq                      : 1;
+	uint32_t t2_instr                     : 1;
+	uint32_t t3_ext                       : 1;
+	uint32_t t3_int                       : 1;
+	uint32_t t3_instr                     : 1;
+	uint32_t reserved_23_31               : 9;
+#endif
+	} s;
+	struct cvmx_endor_intc_wrq_status_lox_s cnf71xx;
+};
+typedef union cvmx_endor_intc_wrq_status_lox cvmx_endor_intc_wrq_status_lox_t;
+
+/**
+ * cvmx_endor_ofs_hmm_cbuf_end_addr0
+ */
+union cvmx_endor_ofs_hmm_cbuf_end_addr0 {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_cbuf_end_addr0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t addr                         : 24; /**< reserved. */
+#else
+	uint32_t addr                         : 24;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_cbuf_end_addr0_s cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_cbuf_end_addr0 cvmx_endor_ofs_hmm_cbuf_end_addr0_t;
+
+/**
+ * cvmx_endor_ofs_hmm_cbuf_end_addr1
+ */
+union cvmx_endor_ofs_hmm_cbuf_end_addr1 {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_cbuf_end_addr1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t addr                         : 24; /**< reserved. */
+#else
+	uint32_t addr                         : 24;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_cbuf_end_addr1_s cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_cbuf_end_addr1 cvmx_endor_ofs_hmm_cbuf_end_addr1_t;
+
+/**
+ * cvmx_endor_ofs_hmm_cbuf_end_addr2
+ */
+union cvmx_endor_ofs_hmm_cbuf_end_addr2 {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_cbuf_end_addr2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t addr                         : 24; /**< reserved. */
+#else
+	uint32_t addr                         : 24;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_cbuf_end_addr2_s cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_cbuf_end_addr2 cvmx_endor_ofs_hmm_cbuf_end_addr2_t;
+
+/**
+ * cvmx_endor_ofs_hmm_cbuf_end_addr3
+ */
+union cvmx_endor_ofs_hmm_cbuf_end_addr3 {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_cbuf_end_addr3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t addr                         : 24; /**< reserved. */
+#else
+	uint32_t addr                         : 24;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_cbuf_end_addr3_s cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_cbuf_end_addr3 cvmx_endor_ofs_hmm_cbuf_end_addr3_t;
+
+/**
+ * cvmx_endor_ofs_hmm_cbuf_start_addr0
+ */
+union cvmx_endor_ofs_hmm_cbuf_start_addr0 {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_cbuf_start_addr0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t addr                         : 24; /**< reserved. */
+#else
+	uint32_t addr                         : 24;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_cbuf_start_addr0_s cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_cbuf_start_addr0 cvmx_endor_ofs_hmm_cbuf_start_addr0_t;
+
+/**
+ * cvmx_endor_ofs_hmm_cbuf_start_addr1
+ */
+union cvmx_endor_ofs_hmm_cbuf_start_addr1 {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_cbuf_start_addr1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t addr                         : 24; /**< reserved. */
+#else
+	uint32_t addr                         : 24;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_cbuf_start_addr1_s cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_cbuf_start_addr1 cvmx_endor_ofs_hmm_cbuf_start_addr1_t;
+
+/**
+ * cvmx_endor_ofs_hmm_cbuf_start_addr2
+ */
+union cvmx_endor_ofs_hmm_cbuf_start_addr2 {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_cbuf_start_addr2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t addr                         : 24; /**< reserved. */
+#else
+	uint32_t addr                         : 24;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_cbuf_start_addr2_s cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_cbuf_start_addr2 cvmx_endor_ofs_hmm_cbuf_start_addr2_t;
+
+/**
+ * cvmx_endor_ofs_hmm_cbuf_start_addr3
+ */
+union cvmx_endor_ofs_hmm_cbuf_start_addr3 {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_cbuf_start_addr3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t addr                         : 24; /**< reserved. */
+#else
+	uint32_t addr                         : 24;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_cbuf_start_addr3_s cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_cbuf_start_addr3 cvmx_endor_ofs_hmm_cbuf_start_addr3_t;
+
+/**
+ * cvmx_endor_ofs_hmm_intr_clear
+ */
+union cvmx_endor_ofs_hmm_intr_clear {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_intr_clear_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_2_31                : 30;
+	uint32_t xfer_q_empty                 : 1;  /**< reserved. */
+	uint32_t xfer_complete                : 1;  /**< reserved. */
+#else
+	uint32_t xfer_complete                : 1;
+	uint32_t xfer_q_empty                 : 1;
+	uint32_t reserved_2_31                : 30;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_intr_clear_s cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_intr_clear cvmx_endor_ofs_hmm_intr_clear_t;
+
+/**
+ * cvmx_endor_ofs_hmm_intr_enb
+ */
+union cvmx_endor_ofs_hmm_intr_enb {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_intr_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_2_31                : 30;
+	uint32_t xfer_q_empty                 : 1;  /**< reserved. */
+	uint32_t xfer_complete                : 1;  /**< reserved. */
+#else
+	uint32_t xfer_complete                : 1;
+	uint32_t xfer_q_empty                 : 1;
+	uint32_t reserved_2_31                : 30;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_intr_enb_s  cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_intr_enb cvmx_endor_ofs_hmm_intr_enb_t;
+
+/**
+ * cvmx_endor_ofs_hmm_intr_rstatus
+ */
+union cvmx_endor_ofs_hmm_intr_rstatus {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_intr_rstatus_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_2_31                : 30;
+	uint32_t xfer_q_empty                 : 1;  /**< reserved. */
+	uint32_t xfer_complete                : 1;  /**< reserved. */
+#else
+	uint32_t xfer_complete                : 1;
+	uint32_t xfer_q_empty                 : 1;
+	uint32_t reserved_2_31                : 30;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_intr_rstatus_s cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_intr_rstatus cvmx_endor_ofs_hmm_intr_rstatus_t;
+
+/**
+ * cvmx_endor_ofs_hmm_intr_status
+ */
+union cvmx_endor_ofs_hmm_intr_status {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_intr_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_2_31                : 30;
+	uint32_t xfer_q_empty                 : 1;  /**< reserved. */
+	uint32_t xfer_complete                : 1;  /**< reserved. */
+#else
+	uint32_t xfer_complete                : 1;
+	uint32_t xfer_q_empty                 : 1;
+	uint32_t reserved_2_31                : 30;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_intr_status_s cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_intr_status cvmx_endor_ofs_hmm_intr_status_t;
+
+/**
+ * cvmx_endor_ofs_hmm_intr_test
+ */
+union cvmx_endor_ofs_hmm_intr_test {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_intr_test_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_2_31                : 30;
+	uint32_t xfer_q_empty                 : 1;  /**< reserved. */
+	uint32_t xfer_complete                : 1;  /**< reserved. */
+#else
+	uint32_t xfer_complete                : 1;
+	uint32_t xfer_q_empty                 : 1;
+	uint32_t reserved_2_31                : 30;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_intr_test_s cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_intr_test cvmx_endor_ofs_hmm_intr_test_t;
+
+/**
+ * cvmx_endor_ofs_hmm_mode
+ */
+union cvmx_endor_ofs_hmm_mode {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_mode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t itlv_bufmode                 : 2;  /**< interleave buffer : 0==1:1, 1==2:1, 2==4:1 */
+	uint32_t reserved_2_3                 : 2;
+	uint32_t mem_clr_enb                  : 1;  /**< reserved. */
+	uint32_t auto_clk_enb                 : 1;  /**< reserved. */
+#else
+	uint32_t auto_clk_enb                 : 1;
+	uint32_t mem_clr_enb                  : 1;
+	uint32_t reserved_2_3                 : 2;
+	uint32_t itlv_bufmode                 : 2;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_mode_s      cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_mode cvmx_endor_ofs_hmm_mode_t;
+
+/**
+ * cvmx_endor_ofs_hmm_start_addr0
+ */
+union cvmx_endor_ofs_hmm_start_addr0 {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_start_addr0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t addr                         : 24; /**< reserved. */
+#else
+	uint32_t addr                         : 24;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_start_addr0_s cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_start_addr0 cvmx_endor_ofs_hmm_start_addr0_t;
+
+/**
+ * cvmx_endor_ofs_hmm_start_addr1
+ */
+union cvmx_endor_ofs_hmm_start_addr1 {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_start_addr1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t addr                         : 24; /**< reserved. */
+#else
+	uint32_t addr                         : 24;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_start_addr1_s cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_start_addr1 cvmx_endor_ofs_hmm_start_addr1_t;
+
+/**
+ * cvmx_endor_ofs_hmm_start_addr2
+ */
+union cvmx_endor_ofs_hmm_start_addr2 {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_start_addr2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t addr                         : 24; /**< reserved. */
+#else
+	uint32_t addr                         : 24;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_start_addr2_s cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_start_addr2 cvmx_endor_ofs_hmm_start_addr2_t;
+
+/**
+ * cvmx_endor_ofs_hmm_start_addr3
+ */
+union cvmx_endor_ofs_hmm_start_addr3 {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_start_addr3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t addr                         : 24; /**< reserved. */
+#else
+	uint32_t addr                         : 24;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_start_addr3_s cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_start_addr3 cvmx_endor_ofs_hmm_start_addr3_t;
+
+/**
+ * cvmx_endor_ofs_hmm_status
+ */
+union cvmx_endor_ofs_hmm_status {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_0_31                : 32;
+#else
+	uint32_t reserved_0_31                : 32;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_status_s    cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_status cvmx_endor_ofs_hmm_status_t;
+
+/**
+ * cvmx_endor_ofs_hmm_xfer_cnt
+ */
+union cvmx_endor_ofs_hmm_xfer_cnt {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_xfer_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t xfer_comp_intr               : 1;  /**< transfer complete interrupt. */
+	uint32_t slice_mode                   : 1;  /**< reserved. */
+	uint32_t cbuf_mode                    : 1;  /**< reserved. */
+	uint32_t reserved_16_28               : 13;
+	uint32_t wordcnt                      : 16; /**< word count. */
+#else
+	uint32_t wordcnt                      : 16;
+	uint32_t reserved_16_28               : 13;
+	uint32_t cbuf_mode                    : 1;
+	uint32_t slice_mode                   : 1;
+	uint32_t xfer_comp_intr               : 1;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_xfer_cnt_s  cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_xfer_cnt cvmx_endor_ofs_hmm_xfer_cnt_t;
+
+/**
+ * cvmx_endor_ofs_hmm_xfer_q_status
+ */
+union cvmx_endor_ofs_hmm_xfer_q_status {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_xfer_q_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t status                       : 32; /**< number of slots to queue buffer transaction. */
+#else
+	uint32_t status                       : 32;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_xfer_q_status_s cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_xfer_q_status cvmx_endor_ofs_hmm_xfer_q_status_t;
+
+/**
+ * cvmx_endor_ofs_hmm_xfer_start
+ */
+union cvmx_endor_ofs_hmm_xfer_start {
+	uint32_t u32;
+	struct cvmx_endor_ofs_hmm_xfer_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_1_31                : 31;
+	uint32_t start                        : 1;  /**< reserved. */
+#else
+	uint32_t start                        : 1;
+	uint32_t reserved_1_31                : 31;
+#endif
+	} s;
+	struct cvmx_endor_ofs_hmm_xfer_start_s cnf71xx;
+};
+typedef union cvmx_endor_ofs_hmm_xfer_start cvmx_endor_ofs_hmm_xfer_start_t;
+
+/**
+ * cvmx_endor_rfif_1pps_gen_cfg
+ */
+union cvmx_endor_rfif_1pps_gen_cfg {
+	uint32_t u32;
+	struct cvmx_endor_rfif_1pps_gen_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_1_31                : 31;
+	uint32_t ena                          : 1;  /**< Enable 1PPS Generation and Tracking
+                                                         - 0: 1PPS signal not tracked or generated
+                                                         - 1: 1PPS signal generated and tracked */
+#else
+	uint32_t ena                          : 1;
+	uint32_t reserved_1_31                : 31;
+#endif
+	} s;
+	struct cvmx_endor_rfif_1pps_gen_cfg_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_1pps_gen_cfg cvmx_endor_rfif_1pps_gen_cfg_t;
+
+/**
+ * cvmx_endor_rfif_1pps_sample_cnt_offset
+ */
+union cvmx_endor_rfif_1pps_sample_cnt_offset {
+	uint32_t u32;
+	struct cvmx_endor_rfif_1pps_sample_cnt_offset_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t offset                       : 20; /**< This register holds the sample count at which the 1PPS
+                                                         was received.
+                                                         Upon reset, the sample counter starts at 0 when the
+                                                         first 1PPS is received and then increments to wrap
+                                                         around at FRAME_L-1. At each subsequent 1PPS, a
+                                                         snapshot of the sample counter is taken and the count
+                                                         is made available via this register. This enables
+                                                         software to monitor the RF clock drift relative to
+                                                         the 1PPS. */
+#else
+	uint32_t offset                       : 20;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_endor_rfif_1pps_sample_cnt_offset_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_1pps_sample_cnt_offset cvmx_endor_rfif_1pps_sample_cnt_offset_t;
+
+/**
+ * cvmx_endor_rfif_1pps_verif_gen_en
+ */
+union cvmx_endor_rfif_1pps_verif_gen_en {
+	uint32_t u32;
+	struct cvmx_endor_rfif_1pps_verif_gen_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_1_31                : 31;
+	uint32_t ena                          : 1;  /**< 1PPS generation for verification purposes
+                                                         - 0: Disabled (default)
+                                                         - 1: Enabled
+                                                          Note the external 1PPS is not considered, when this bit
+                                                          is set to 1. */
+#else
+	uint32_t ena                          : 1;
+	uint32_t reserved_1_31                : 31;
+#endif
+	} s;
+	struct cvmx_endor_rfif_1pps_verif_gen_en_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_1pps_verif_gen_en cvmx_endor_rfif_1pps_verif_gen_en_t;
+
+/**
+ * cvmx_endor_rfif_1pps_verif_scnt
+ */
+union cvmx_endor_rfif_1pps_verif_scnt {
+	uint32_t u32;
+	struct cvmx_endor_rfif_1pps_verif_scnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t cnt                          : 20; /**< Sample count at which the 1PPS is generated for
+                                                         verification purposes. */
+#else
+	uint32_t cnt                          : 20;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_endor_rfif_1pps_verif_scnt_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_1pps_verif_scnt cvmx_endor_rfif_1pps_verif_scnt_t;
+
+/**
+ * cvmx_endor_rfif_conf
+ */
+union cvmx_endor_rfif_conf {
+	uint32_t u32;
+	struct cvmx_endor_rfif_conf_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_18_31               : 14;
+	uint32_t loopback                     : 1;  /**< FDD loop back mode
+                                                         - 0: Not in loopback mode(default)
+                                                         - 1: loops back the tx ouput to the rx input inside the
+                                                          rf_if */
+	uint32_t mol                          : 1;  /**< Manual Override Lock */
+	uint32_t upd_style                    : 1;  /**< TX and RX Windows parameters update style (default:0)
+                                                         - 0: updated as written to the register (on the fly)
+                                                          (not fully verified but kept in case limitations are
+                                                          found with the other update scheme.)
+                                                         - 1: updated at the specified time by registers 00F and
+                                                          90F.
+                                                          Note the frame length is updated after the last TX
+                                                          window.
+                                                         - 1: eNB, enables using 1PPS synchronization scheme. */
+	uint32_t diversity                    : 1;  /**< RX diversity disable (Used to support FDD SISO with CLK
+                                                          4X)
+                                                         - 0: Data gets written to the diversity FIFO in MIMO mode
+                                                          (default).
+                                                         - 1: No data written to the diversity FIFO in MIMO mode. */
+	uint32_t duplex                       : 1;  /**< Division Duplex Mode
+                                                         - 0: TDD (default)
+                                                         - 1: FDD */
+	uint32_t prod_type                    : 1;  /**< Product Type
+                                                         - 0: UE (default), enables using sync and timing advance
+                                                          synchronization schemes. */
+	uint32_t txnrx_ctrl                   : 1;  /**< RFIC IF TXnRX signal pulse control. Changing the value
+                                                         of this bit generates a pulse on the TXNRX signal of
+                                                         the RFIC interface. This feature is enabled when bit
+                                                         9 has already been asserted. */
+	uint32_t ena_ctrl                     : 1;  /**< RFIC IF ENABLE signal pulse control. Changing the value
+                                                         of this bit generates a pulse on the ENABLE signal of
+                                                         the RFIC interface. This feature is enabled when bit 9
+                                                         has already been asserted. */
+	uint32_t man_ctrl                     : 1;  /**< RF IC Manual Control Enable. Setting this bit to 1
+                                                         enables manual control of the TXNRX and ENABLE signals.
+                                                         When set to 0 (default), the TXNRX and ENABLE signals
+                                                         are automatically controlled when opening and closing
+                                                         RX/TX windows. The manual mode is used to initialize
+                                                         the RFIC in alert mode. */
+	uint32_t dsp_rx_int_en                : 1;  /**< DSP RX interrupt mask enable
+                                                         - 0: DSP RX receives interrupts
+                                                         - 1: DSP RX doesn't receive interrupts, needs to poll
+                                                          ISRs */
+	uint32_t adi_en                       : 1;  /**< ADI enable signal pulsed or leveled behavior
+                                                         - 0: pulsed
+                                                         - 1: leveled */
+	uint32_t clr_fifo_of                  : 1;  /**< Clear RX FIFO overflow flag. */
+	uint32_t clr_fifo_ur                  : 1;  /**< Clear RX FIFO under run flag. */
+	uint32_t wavesat_mode                 : 1;  /**< AD9361 wavesat mode, where enable becomes rx_control
+                                                          and txnrx becomes tx_control. The wavesat mode permits
+                                                          an independent control of the rx and tx data flows.
+                                                         - 0: wavesat mode
+                                                         - 1: regular mode */
+	uint32_t flush                        : 1;  /**< Flush RX FIFO auto clear register. */
+	uint32_t inv                          : 1;  /**< Data inversion (bit 0 becomes bit 11, bit 1 becomes 10) */
+	uint32_t mode                         : 1;  /**< 0: SISO 1: MIMO */
+	uint32_t enable                       : 1;  /**< 1=enable, 0=disabled */
+#else
+	uint32_t enable                       : 1;
+	uint32_t mode                         : 1;
+	uint32_t inv                          : 1;
+	uint32_t flush                        : 1;
+	uint32_t wavesat_mode                 : 1;
+	uint32_t clr_fifo_ur                  : 1;
+	uint32_t clr_fifo_of                  : 1;
+	uint32_t adi_en                       : 1;
+	uint32_t dsp_rx_int_en                : 1;
+	uint32_t man_ctrl                     : 1;
+	uint32_t ena_ctrl                     : 1;
+	uint32_t txnrx_ctrl                   : 1;
+	uint32_t prod_type                    : 1;
+	uint32_t duplex                       : 1;
+	uint32_t diversity                    : 1;
+	uint32_t upd_style                    : 1;
+	uint32_t mol                          : 1;
+	uint32_t loopback                     : 1;
+	uint32_t reserved_18_31               : 14;
+#endif
+	} s;
+	struct cvmx_endor_rfif_conf_s         cnf71xx;
+};
+typedef union cvmx_endor_rfif_conf cvmx_endor_rfif_conf_t;
+
+/**
+ * cvmx_endor_rfif_conf2
+ */
+union cvmx_endor_rfif_conf2 {
+	uint32_t u32;
+	struct cvmx_endor_rfif_conf2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_3_31                : 29;
+	uint32_t latency                      : 1;  /**< RF DATA variable latency
+                                                         - 0: fixed latency (prior to AD9163)
+                                                         - 1: variable latency (starting with the AD9361) */
+	uint32_t iq_cfg                       : 1;  /**< IQ port configuration
+                                                         - 0: Single port (10Mhz BW and less)
+                                                         - 1: Dual ports (more then 10Mhz BW) */
+	uint32_t behavior                     : 1;  /**< RX and TX FRAME signals behavior:
+                                                         - 0: Pulsed every frame
+                                                         - 1: Leveled during the whole RX and TX periods */
+#else
+	uint32_t behavior                     : 1;
+	uint32_t iq_cfg                       : 1;
+	uint32_t latency                      : 1;
+	uint32_t reserved_3_31                : 29;
+#endif
+	} s;
+	struct cvmx_endor_rfif_conf2_s        cnf71xx;
+};
+typedef union cvmx_endor_rfif_conf2 cvmx_endor_rfif_conf2_t;
+
+/**
+ * cvmx_endor_rfif_dsp1_gpio
+ */
+union cvmx_endor_rfif_dsp1_gpio {
+	uint32_t u32;
+	struct cvmx_endor_rfif_dsp1_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_4_31                : 28;
+	uint32_t val                          : 4;  /**< Values to output to the DSP1_GPIO ports */
+#else
+	uint32_t val                          : 4;
+	uint32_t reserved_4_31                : 28;
+#endif
+	} s;
+	struct cvmx_endor_rfif_dsp1_gpio_s    cnf71xx;
+};
+typedef union cvmx_endor_rfif_dsp1_gpio cvmx_endor_rfif_dsp1_gpio_t;
+
+/**
+ * cvmx_endor_rfif_dsp_rx_his
+ */
+union cvmx_endor_rfif_dsp_rx_his {
+	uint32_t u32;
+	struct cvmx_endor_rfif_dsp_rx_his_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_0_31                : 32;
+#else
+	uint32_t reserved_0_31                : 32;
+#endif
+	} s;
+	struct cvmx_endor_rfif_dsp_rx_his_s   cnf71xx;
+};
+typedef union cvmx_endor_rfif_dsp_rx_his cvmx_endor_rfif_dsp_rx_his_t;
+
+/**
+ * cvmx_endor_rfif_dsp_rx_ism
+ */
+union cvmx_endor_rfif_dsp_rx_ism {
+	uint32_t u32;
+	struct cvmx_endor_rfif_dsp_rx_ism_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t ena                          : 8;  /**< Enable interrupt bits. Set to each bit to 1 to enable
+                                                         the interrupts listed in the table below. The default
+                                                         value is 0x0. */
+	uint32_t reserved_0_15                : 16;
+#else
+	uint32_t reserved_0_15                : 16;
+	uint32_t ena                          : 8;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_rfif_dsp_rx_ism_s   cnf71xx;
+};
+typedef union cvmx_endor_rfif_dsp_rx_ism cvmx_endor_rfif_dsp_rx_ism_t;
+
+/**
+ * cvmx_endor_rfif_firs_enable
+ */
+union cvmx_endor_rfif_firs_enable {
+	uint32_t u32;
+	struct cvmx_endor_rfif_firs_enable_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_4_31                : 28;
+	uint32_t tx_div_fil                   : 1;  /**< TX DIV filtering control bit
+                                                         - 0: TX DIV filtering disabled
+                                                         - 1: TX DIV filtering enabled */
+	uint32_t tx_fil                       : 1;  /**< TX filtering control bit
+                                                         - 0: TX filtering disabled
+                                                         - 1: TX filtering enabled */
+	uint32_t rx_dif_fil                   : 1;  /**< RX DIV filtering control bit
+                                                         - 0: RX DIV filtering disabled
+                                                         - 1: RX DIV filtering enabled */
+	uint32_t rx_fil                       : 1;  /**< RX filtering control bit
+                                                         - 0: RX filtering disabled
+                                                         - 1: RX filtering enabled */
+#else
+	uint32_t rx_fil                       : 1;
+	uint32_t rx_dif_fil                   : 1;
+	uint32_t tx_fil                       : 1;
+	uint32_t tx_div_fil                   : 1;
+	uint32_t reserved_4_31                : 28;
+#endif
+	} s;
+	struct cvmx_endor_rfif_firs_enable_s  cnf71xx;
+};
+typedef union cvmx_endor_rfif_firs_enable cvmx_endor_rfif_firs_enable_t;
+
+/**
+ * cvmx_endor_rfif_frame_cnt
+ */
+union cvmx_endor_rfif_frame_cnt {
+	uint32_t u32;
+	struct cvmx_endor_rfif_frame_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t cnt                          : 20; /**< Frame count (value wraps around 2**16) */
+#else
+	uint32_t cnt                          : 20;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_endor_rfif_frame_cnt_s    cnf71xx;
+};
+typedef union cvmx_endor_rfif_frame_cnt cvmx_endor_rfif_frame_cnt_t;
+
+/**
+ * cvmx_endor_rfif_frame_l
+ */
+union cvmx_endor_rfif_frame_l {
+	uint32_t u32;
+	struct cvmx_endor_rfif_frame_l_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t length                       : 20; /**< Frame length in terms of RF clock cycles:
+                                                         RFIC in single port modes
+                                                         TDD SISO ? FRAME_L = num_samples
+                                                         TDD MIMO ? FRAME_L = num_samples * 2
+                                                         FDD SISO ? FRAME_L = num_samples * 2
+                                                         FDD MIMO ? FRAME_L = num_samples * 4
+                                                         RFIC in dual ports modes
+                                                         TDD SISO ? FRAME_L = num_samples * 0.5
+                                                         TDD MIMO ? FRAME_L = num_samples
+                                                         FDD SISO ? FRAME_L = num_samples
+                                                         FDD MIMO ? FRAME_L = num_samples * 2 */
+#else
+	uint32_t length                       : 20;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_endor_rfif_frame_l_s      cnf71xx;
+};
+typedef union cvmx_endor_rfif_frame_l cvmx_endor_rfif_frame_l_t;
+
+/**
+ * cvmx_endor_rfif_gpio_#
+ */
+union cvmx_endor_rfif_gpio_x {
+	uint32_t u32;
+	struct cvmx_endor_rfif_gpio_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t fall_val                     : 11; /**< Signed value (lead/lag) on falling edge of level signal */
+	uint32_t rise_val                     : 11; /**< Signed value (lead/lag) on rising edge of level signal */
+	uint32_t src                          : 2;  /**< Signal active high source:
+                                                         - 00: idle
+                                                         - 01: RX
+                                                         - 10: TX
+                                                         - 11: idle */
+#else
+	uint32_t src                          : 2;
+	uint32_t rise_val                     : 11;
+	uint32_t fall_val                     : 11;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_rfif_gpio_x_s       cnf71xx;
+};
+typedef union cvmx_endor_rfif_gpio_x cvmx_endor_rfif_gpio_x_t;
+
+/**
+ * cvmx_endor_rfif_max_sample_adj
+ */
+union cvmx_endor_rfif_max_sample_adj {
+	uint32_t u32;
+	struct cvmx_endor_rfif_max_sample_adj_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_10_31               : 22;
+	uint32_t num                          : 10; /**< Indicates the maximum number of samples that can be
+                                                         adjusted per frame. Note the value to be programmed
+                                                         varies with the mode of operation as follow:
+                                                         MAX_SAMPLE_ADJ  = num_samples*MIMO*FDD*DP
+                                                         Where:
+                                                         MIMO = 2 in MIMO mode and 1 otherwise.
+                                                         FDD = 2 in FDD mode and 1 otherwise.
+                                                         DP = 0.5 in RF IF Dual Port mode, 1 otherwise. */
+#else
+	uint32_t num                          : 10;
+	uint32_t reserved_10_31               : 22;
+#endif
+	} s;
+	struct cvmx_endor_rfif_max_sample_adj_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_max_sample_adj cvmx_endor_rfif_max_sample_adj_t;
+
+/**
+ * cvmx_endor_rfif_min_sample_adj
+ */
+union cvmx_endor_rfif_min_sample_adj {
+	uint32_t u32;
+	struct cvmx_endor_rfif_min_sample_adj_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_10_31               : 22;
+	uint32_t num                          : 10; /**< Indicates the minimum number of samples that can be
+                                                         adjusted per frame. Note the value to be programmed
+                                                         varies with the mode of operation as follow:
+                                                         MIN_SAMPLE_ADJ  = num_samples*MIMO*FDD*DP
+                                                         Where:
+                                                         MIMO = 2 in MIMO mode and 1 otherwise.
+                                                         FDD = 2 in FDD mode and 1 otherwise.
+                                                         DP = 0.5 in RF IF Dual Port mode, 1 otherwise. */
+#else
+	uint32_t num                          : 10;
+	uint32_t reserved_10_31               : 22;
+#endif
+	} s;
+	struct cvmx_endor_rfif_min_sample_adj_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_min_sample_adj cvmx_endor_rfif_min_sample_adj_t;
+
+/**
+ * cvmx_endor_rfif_num_rx_win
+ */
+union cvmx_endor_rfif_num_rx_win {
+	uint32_t u32;
+	struct cvmx_endor_rfif_num_rx_win_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_3_31                : 29;
+	uint32_t num                          : 3;  /**< Number of RX windows
+                                                         - 0: No RX window
+                                                         - 1: One RX window
+                                                          - ...
+                                                         - 4: Four RX windows
+                                                          Other: Not defined */
+#else
+	uint32_t num                          : 3;
+	uint32_t reserved_3_31                : 29;
+#endif
+	} s;
+	struct cvmx_endor_rfif_num_rx_win_s   cnf71xx;
+};
+typedef union cvmx_endor_rfif_num_rx_win cvmx_endor_rfif_num_rx_win_t;
+
+/**
+ * cvmx_endor_rfif_pwm_enable
+ */
+union cvmx_endor_rfif_pwm_enable {
+	uint32_t u32;
+	struct cvmx_endor_rfif_pwm_enable_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_1_31                : 31;
+	uint32_t ena                          : 1;  /**< PWM signal generation enable:
+                                                         - 1: PWM enabled
+                                                         - 0: PWM disabled (default) */
+#else
+	uint32_t ena                          : 1;
+	uint32_t reserved_1_31                : 31;
+#endif
+	} s;
+	struct cvmx_endor_rfif_pwm_enable_s   cnf71xx;
+};
+typedef union cvmx_endor_rfif_pwm_enable cvmx_endor_rfif_pwm_enable_t;
+
+/**
+ * cvmx_endor_rfif_pwm_high_time
+ */
+union cvmx_endor_rfif_pwm_high_time {
+	uint32_t u32;
+	struct cvmx_endor_rfif_pwm_high_time_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t hi_time                      : 24; /**< PWM high time. The default is 0h00FFFF cycles. Program
+                                                         to n for n+1 high cycles. */
+#else
+	uint32_t hi_time                      : 24;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_rfif_pwm_high_time_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_pwm_high_time cvmx_endor_rfif_pwm_high_time_t;
+
+/**
+ * cvmx_endor_rfif_pwm_low_time
+ */
+union cvmx_endor_rfif_pwm_low_time {
+	uint32_t u32;
+	struct cvmx_endor_rfif_pwm_low_time_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t lo_time                      : 24; /**< PWM low time. The default is 0h00FFFF cycles. Program
+                                                         to n for n+1 low cycles. */
+#else
+	uint32_t lo_time                      : 24;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_rfif_pwm_low_time_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_pwm_low_time cvmx_endor_rfif_pwm_low_time_t;
+
+/**
+ * cvmx_endor_rfif_rd_timer64_lsb
+ */
+union cvmx_endor_rfif_rd_timer64_lsb {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rd_timer64_lsb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t val                          : 32; /**< 64-bit timer initial value of the 32 LSB.
+                                                         Note the value written in WR_TIMER64_LSB is not
+                                                         propagating until the timer64 is enabled. */
+#else
+	uint32_t val                          : 32;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rd_timer64_lsb_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_rd_timer64_lsb cvmx_endor_rfif_rd_timer64_lsb_t;
+
+/**
+ * cvmx_endor_rfif_rd_timer64_msb
+ */
+union cvmx_endor_rfif_rd_timer64_msb {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rd_timer64_msb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t val                          : 32; /**< 64-bit timer initial value of the 32 MSB.
+                                                         Note the value written in WR_TIMER64_MSB is not
+                                                         propagating until the timer64 is enabled. */
+#else
+	uint32_t val                          : 32;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rd_timer64_msb_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_rd_timer64_msb cvmx_endor_rfif_rd_timer64_msb_t;
+
+/**
+ * cvmx_endor_rfif_real_time_timer
+ */
+union cvmx_endor_rfif_real_time_timer {
+	uint32_t u32;
+	struct cvmx_endor_rfif_real_time_timer_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t timer                        : 32; /**< The full 32 bits of the real time timer fed from a core
+                                                         clock based counter. */
+#else
+	uint32_t timer                        : 32;
+#endif
+	} s;
+	struct cvmx_endor_rfif_real_time_timer_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_real_time_timer cvmx_endor_rfif_real_time_timer_t;
+
+/**
+ * cvmx_endor_rfif_rf_clk_timer
+ */
+union cvmx_endor_rfif_rf_clk_timer {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rf_clk_timer_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t timer                        : 32; /**< Timer running off the RF CLK.
+                                                         1- The counter is disabled by default;
+                                                         2- The counter is enabled by writing 1 to register 066;
+                                                         3- The counter waits for the 1PPS to start incrementing
+                                                         4- The 1PPS is received and the counter starts
+                                                         incrementing;
+                                                         5- The counter is reset after receiving the 30th 1PPS
+                                                         (after 30 seconds);
+                                                         6- The counter keeps incrementing and is reset as in 5,
+                                                         unless it is disabled. */
+#else
+	uint32_t timer                        : 32;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rf_clk_timer_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_rf_clk_timer cvmx_endor_rfif_rf_clk_timer_t;
+
+/**
+ * cvmx_endor_rfif_rf_clk_timer_en
+ */
+union cvmx_endor_rfif_rf_clk_timer_en {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rf_clk_timer_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_1_31                : 31;
+	uint32_t ena                          : 1;  /**< RF CLK based timer enable
+                                                         - 0: Disabled
+                                                         - 1: Enabled */
+#else
+	uint32_t ena                          : 1;
+	uint32_t reserved_1_31                : 31;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rf_clk_timer_en_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_rf_clk_timer_en cvmx_endor_rfif_rf_clk_timer_en_t;
+
+/**
+ * cvmx_endor_rfif_rx_correct_adj
+ */
+union cvmx_endor_rfif_rx_correct_adj {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rx_correct_adj_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_4_31                : 28;
+	uint32_t offset                       : 4;  /**< Indicates the sample counter offset for the last sample
+                                                         flag insertion, which determines when the rx samples
+                                                         are dropped or added. This register can take values
+                                                         from 0 to 15 and should be configured as follow:
+                                                         4, when MIN_SAMPLE_ADJ = 1
+                                                         5 , when MIN_SAMPLE_ADJ = 2
+                                                         6 , when MIN_SAMPLE_ADJ = 4 */
+#else
+	uint32_t offset                       : 4;
+	uint32_t reserved_4_31                : 28;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rx_correct_adj_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_rx_correct_adj cvmx_endor_rfif_rx_correct_adj_t;
+
+/**
+ * cvmx_endor_rfif_rx_div_status
+ *
+ * Notes:
+ * In TDD Mode, bits 15:12 are DDR state machine status.
+ *
+ */
+union cvmx_endor_rfif_rx_div_status {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rx_div_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_23_31               : 9;
+	uint32_t rfic_ena                     : 1;  /**< RFIC enabled (in alert state) */
+	uint32_t sync_late                    : 1;  /**< Sync late (Used for UE products). */
+	uint32_t reserved_19_20               : 2;
+	uint32_t thresh_rch                   : 1;  /**< Threshold Reached (RX/RX_div/TX) */
+	uint32_t fifo_of                      : 1;  /**< FIFO overflow */
+	uint32_t fifo_ur                      : 1;  /**< FIFO underrun */
+	uint32_t tx_sm                        : 2;  /**< TX state machine status */
+	uint32_t rx_sm                        : 2;  /**< RX state machine status */
+	uint32_t hab_req_sm                   : 4;  /**< HAB request manager SM
+                                                         - 0: idle
+                                                         - 1: wait_cs
+                                                         - 2: Term
+                                                         - 3: rd_fifo(RX)/ write fifo(TX)
+                                                         - 4: wait_th
+                                                          Others: not used */
+	uint32_t reserved_0_7                 : 8;
+#else
+	uint32_t reserved_0_7                 : 8;
+	uint32_t hab_req_sm                   : 4;
+	uint32_t rx_sm                        : 2;
+	uint32_t tx_sm                        : 2;
+	uint32_t fifo_ur                      : 1;
+	uint32_t fifo_of                      : 1;
+	uint32_t thresh_rch                   : 1;
+	uint32_t reserved_19_20               : 2;
+	uint32_t sync_late                    : 1;
+	uint32_t rfic_ena                     : 1;
+	uint32_t reserved_23_31               : 9;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rx_div_status_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_rx_div_status cvmx_endor_rfif_rx_div_status_t;
+
+/**
+ * cvmx_endor_rfif_rx_fifo_cnt
+ */
+union cvmx_endor_rfif_rx_fifo_cnt {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rx_fifo_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_13_31               : 19;
+	uint32_t cnt                          : 13; /**< RX FIFO fill level. This register can take values
+                                                         between 0 and 5136. */
+#else
+	uint32_t cnt                          : 13;
+	uint32_t reserved_13_31               : 19;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rx_fifo_cnt_s  cnf71xx;
+};
+typedef union cvmx_endor_rfif_rx_fifo_cnt cvmx_endor_rfif_rx_fifo_cnt_t;
+
+/**
+ * cvmx_endor_rfif_rx_if_cfg
+ */
+union cvmx_endor_rfif_rx_if_cfg {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rx_if_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t eorl                         : 1;  /**< Early or Late TX_FRAME
+                                                         - 0: The TX_FRAME asserts after the tx_lead and deasserts
+                                                          before the tx_lag
+                                                         - 1: The TX_FRAME asserts (3:0) cycles after the
+                                                          TX_ON/ENABLE and deasserts (3:0) cycles after the
+                                                          TX_ON/ENABLE signal. */
+	uint32_t half_lat                     : 1;  /**< Half cycle latency
+                                                         - 0: Captures I and Q on the falling and rising edge of
+                                                          the clock respectively.
+                                                         - 1: Captures I and Q on the rising and falling edge of
+                                                          the clock respectively. */
+	uint32_t cap_lat                      : 4;  /**< Enable to capture latency
+                                                          The data from the RF IC starts and stops being captured
+                                                          a number of cycles after the enable pulse.
+                                                         - 0: Invalid
+                                                         - 1: One cycle latency
+                                                         - 2: Two cycles of latency
+                                                         - 3: Three cycles of latency
+                                                          - ...
+                                                          - 15: Seven cycles of latency */
+#else
+	uint32_t cap_lat                      : 4;
+	uint32_t half_lat                     : 1;
+	uint32_t eorl                         : 1;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rx_if_cfg_s    cnf71xx;
+};
+typedef union cvmx_endor_rfif_rx_if_cfg cvmx_endor_rfif_rx_if_cfg_t;
+
+/**
+ * cvmx_endor_rfif_rx_lead_lag
+ */
+union cvmx_endor_rfif_rx_lead_lag {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rx_lead_lag_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t lag                          : 12; /**< unsigned value (lag) on end of window */
+	uint32_t lead                         : 12; /**< unsigned value (lead) on beginning of window */
+#else
+	uint32_t lead                         : 12;
+	uint32_t lag                          : 12;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rx_lead_lag_s  cnf71xx;
+};
+typedef union cvmx_endor_rfif_rx_lead_lag cvmx_endor_rfif_rx_lead_lag_t;
+
+/**
+ * cvmx_endor_rfif_rx_load_cfg
+ */
+union cvmx_endor_rfif_rx_load_cfg {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rx_load_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_13_31               : 19;
+	uint32_t hidden                       : 1;  /**< Hidden bit set to 1 during synthesis
+                                                         (set_case_analysis) if only one destination can be
+                                                         programmed at a time. In this case there is no need to
+                                                         gate the VLD with the RDYs, to ease timing closure. */
+	uint32_t reserved_9_11                : 3;
+	uint32_t alt_ant                      : 1;  /**< Send data alternating antenna 0 (first) and antenna 1
+                                                         (second) data on the RX HMI interface when set to 1.
+                                                         By default, only the data from antenna 0 is sent on
+                                                         this interface. */
+	uint32_t reserved_3_7                 : 5;
+	uint32_t exe3                         : 1;  /**< Setting this bit to 1 indicates the RF_IF to load
+                                                         and execute the programmed DMA transfer size (register
+                                                         RX_TRANSFER_SIZE) from the FIFO to destination 3. */
+	uint32_t exe2                         : 1;  /**< Setting this bit to 1 indicates the RF_IF to load
+                                                         and execute the programmed DMA transfer size (register
+                                                         RX_TRANSFER_SIZE) from the FIFO to destination 2. */
+	uint32_t exe1                         : 1;  /**< Setting this bit to 1 indicates the RF_IF to load
+                                                         and execute the programmed DMA transfer size (register
+                                                         RX_TRANSFER_SIZE) from the FIFO to destination 1. */
+#else
+	uint32_t exe1                         : 1;
+	uint32_t exe2                         : 1;
+	uint32_t exe3                         : 1;
+	uint32_t reserved_3_7                 : 5;
+	uint32_t alt_ant                      : 1;
+	uint32_t reserved_9_11                : 3;
+	uint32_t hidden                       : 1;
+	uint32_t reserved_13_31               : 19;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rx_load_cfg_s  cnf71xx;
+};
+typedef union cvmx_endor_rfif_rx_load_cfg cvmx_endor_rfif_rx_load_cfg_t;
+
+/**
+ * cvmx_endor_rfif_rx_offset
+ */
+union cvmx_endor_rfif_rx_offset {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rx_offset_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t offset                       : 20; /**< Indicates the number of RF clock cycles after the
+                                                         GPS/ETH 1PPS is received before the start of the RX
+                                                         frame. See description Figure 44. */
+#else
+	uint32_t offset                       : 20;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rx_offset_s    cnf71xx;
+};
+typedef union cvmx_endor_rfif_rx_offset cvmx_endor_rfif_rx_offset_t;
+
+/**
+ * cvmx_endor_rfif_rx_offset_adj_scnt
+ */
+union cvmx_endor_rfif_rx_offset_adj_scnt {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rx_offset_adj_scnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t cnt                          : 20; /**< Indicates the RX sample count at which the 1PPS
+                                                         incremental adjustments will be applied. */
+#else
+	uint32_t cnt                          : 20;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rx_offset_adj_scnt_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_rx_offset_adj_scnt cvmx_endor_rfif_rx_offset_adj_scnt_t;
+
+/**
+ * cvmx_endor_rfif_rx_status
+ *
+ * Notes:
+ * In TDD Mode, bits 15:12 are DDR state machine status.
+ *
+ */
+union cvmx_endor_rfif_rx_status {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rx_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_23_31               : 9;
+	uint32_t rfic_ena                     : 1;  /**< RFIC enabled (in alert state) */
+	uint32_t sync_late                    : 1;  /**< Sync late (Used for UE products). */
+	uint32_t reserved_19_20               : 2;
+	uint32_t thresh_rch                   : 1;  /**< Threshold Reached (RX/RX_div/TX) */
+	uint32_t fifo_of                      : 1;  /**< FIFO overflow */
+	uint32_t fifo_ur                      : 1;  /**< FIFO underrun */
+	uint32_t tx_sm                        : 2;  /**< TX state machine status */
+	uint32_t rx_sm                        : 2;  /**< RX state machine status */
+	uint32_t hab_req_sm                   : 4;  /**< HAB request manager SM
+                                                         - 0: idle
+                                                         - 1: wait_cs
+                                                         - 2: Term
+                                                         - 3: rd_fifo(RX)/ write fifo(TX)
+                                                         - 4: wait_th
+                                                          Others: not used */
+	uint32_t reserved_0_7                 : 8;
+#else
+	uint32_t reserved_0_7                 : 8;
+	uint32_t hab_req_sm                   : 4;
+	uint32_t rx_sm                        : 2;
+	uint32_t tx_sm                        : 2;
+	uint32_t fifo_ur                      : 1;
+	uint32_t fifo_of                      : 1;
+	uint32_t thresh_rch                   : 1;
+	uint32_t reserved_19_20               : 2;
+	uint32_t sync_late                    : 1;
+	uint32_t rfic_ena                     : 1;
+	uint32_t reserved_23_31               : 9;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rx_status_s    cnf71xx;
+};
+typedef union cvmx_endor_rfif_rx_status cvmx_endor_rfif_rx_status_t;
+
+/**
+ * cvmx_endor_rfif_rx_sync_scnt
+ */
+union cvmx_endor_rfif_rx_sync_scnt {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rx_sync_scnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t cnt                          : 20; /**< Sample count at which the start of frame reference will
+                                                         be modified as described with register 0x30. */
+#else
+	uint32_t cnt                          : 20;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rx_sync_scnt_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_rx_sync_scnt cvmx_endor_rfif_rx_sync_scnt_t;
+
+/**
+ * cvmx_endor_rfif_rx_sync_value
+ */
+union cvmx_endor_rfif_rx_sync_value {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rx_sync_value_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t val                          : 20; /**< RX Synchronization offset value. This register
+                                                         indicates the sample number at which the start of frame
+                                                         must be moved to. This value must be smaller than
+                                                         FRAME_L, but it cannot be negative. See below how the
+                                                         sample count gets updated based on registers 0x30 and
+                                                         0x31 at sample count RX_SYNC_VALUE.
+                                                         If RX_SYNC_SCNT >= RX_SYNC_VALUE
+                                                         sample_count = RX_SYNC_SCNT ? RX_SYNC_VALUE + 1
+                                                         Else
+                                                         sample_count = RX_SYNC_SCNT + FRAME_L ?
+                                                         RX_SYNC_VALUE + 1
+                                                         Note this is not used for eNB products, only for UE
+                                                         products.
+                                                         Note this register is cleared after the correction is
+                                                         applied. */
+#else
+	uint32_t val                          : 20;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rx_sync_value_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_rx_sync_value cvmx_endor_rfif_rx_sync_value_t;
+
+/**
+ * cvmx_endor_rfif_rx_th
+ */
+union cvmx_endor_rfif_rx_th {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rx_th_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_12_31               : 20;
+	uint32_t thr                          : 12; /**< FIFO level reached before granting a RX DMA request.
+                                                         This RX FIFO fill level threshold can be used
+                                                         in two ways:
+                                                              1- When the FIFO fill level reaches the threshold,
+                                                         there is enough data in the FIFO to start the data
+                                                         transfer, so it grants a DMA transfer from the RX FIFO
+                                                         to the HAB's memory.
+                                                              2- It can also be used to generate an interrupt to
+                                                         the DSP when the FIFO threshold is reached. */
+#else
+	uint32_t thr                          : 12;
+	uint32_t reserved_12_31               : 20;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rx_th_s        cnf71xx;
+};
+typedef union cvmx_endor_rfif_rx_th cvmx_endor_rfif_rx_th_t;
+
+/**
+ * cvmx_endor_rfif_rx_transfer_size
+ */
+union cvmx_endor_rfif_rx_transfer_size {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rx_transfer_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_13_31               : 19;
+	uint32_t size                         : 13; /**< Indicates the size of the DMA data transfer from the
+                                                         rf_if RX FIFO out via the HMI IF.
+                                                         The DMA transfers to the HAB1 and HAB2 */
+#else
+	uint32_t size                         : 13;
+	uint32_t reserved_13_31               : 19;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rx_transfer_size_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_rx_transfer_size cvmx_endor_rfif_rx_transfer_size_t;
+
+/**
+ * cvmx_endor_rfif_rx_w_e#
+ */
+union cvmx_endor_rfif_rx_w_ex {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rx_w_ex_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t end_cnt                      : 20; /**< End count for each of the 4 RX windows. The maximum
+                                                         value should be FRAME_L, unless the window must stay
+                                                         opened for ever. */
+#else
+	uint32_t end_cnt                      : 20;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rx_w_ex_s      cnf71xx;
+};
+typedef union cvmx_endor_rfif_rx_w_ex cvmx_endor_rfif_rx_w_ex_t;
+
+/**
+ * cvmx_endor_rfif_rx_w_s#
+ */
+union cvmx_endor_rfif_rx_w_sx {
+	uint32_t u32;
+	struct cvmx_endor_rfif_rx_w_sx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t start_pnt                    : 20; /**< Start points for each of the 4 RX windows
+                                                         Some restrictions applies to the start and end values:
+                                                         1- The first RX window must always start at the sample
+                                                         count 0.
+                                                         2- The other start point must be greater than rx_lead,
+                                                         refer to 0x008.
+                                                         3- All start point values must be smaller than the
+                                                         endpoints in TDD mode.
+                                                         4- RX windows have priorities over TX windows in TDD
+                                                         mode.
+                                                         5- There must be a minimum of 7 samples between
+                                                         closing a window and opening a new one. However, it is
+                                                         recommended to leave a 10 samples gap. Note that this
+                                                         number could increase with different RF ICs used. */
+#else
+	uint32_t start_pnt                    : 20;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_endor_rfif_rx_w_sx_s      cnf71xx;
+};
+typedef union cvmx_endor_rfif_rx_w_sx cvmx_endor_rfif_rx_w_sx_t;
+
+/**
+ * cvmx_endor_rfif_sample_adj_cfg
+ */
+union cvmx_endor_rfif_sample_adj_cfg {
+	uint32_t u32;
+	struct cvmx_endor_rfif_sample_adj_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_1_31                : 31;
+	uint32_t adj                          : 1;  /**< Indicates whether samples must be removed from the
+                                                          beginning or the end of the frame.
+                                                         - 1: add/remove samples from the beginning of the frame
+                                                         - 0: add/remove samples from the end of the frame
+                                                          (default) */
+#else
+	uint32_t adj                          : 1;
+	uint32_t reserved_1_31                : 31;
+#endif
+	} s;
+	struct cvmx_endor_rfif_sample_adj_cfg_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_sample_adj_cfg cvmx_endor_rfif_sample_adj_cfg_t;
+
+/**
+ * cvmx_endor_rfif_sample_adj_error
+ */
+union cvmx_endor_rfif_sample_adj_error {
+	uint32_t u32;
+	struct cvmx_endor_rfif_sample_adj_error_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t offset                       : 32; /**< Count of the number of times the TX FIFO did not have
+                                                         enough IQ samples to be dropped for a TX timing
+                                                         adjustment.
+                                                         0-7 = TX FIFO sample adjustment error
+                                                         - 16:23 = TX DIV sample adjustment error */
+#else
+	uint32_t offset                       : 32;
+#endif
+	} s;
+	struct cvmx_endor_rfif_sample_adj_error_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_sample_adj_error cvmx_endor_rfif_sample_adj_error_t;
+
+/**
+ * cvmx_endor_rfif_sample_cnt
+ */
+union cvmx_endor_rfif_sample_cnt {
+	uint32_t u32;
+	struct cvmx_endor_rfif_sample_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t cnt                          : 20; /**< Sample count modulo FRAME_L. The start of frame is
+                                                         aligned with count 0. */
+#else
+	uint32_t cnt                          : 20;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_endor_rfif_sample_cnt_s   cnf71xx;
+};
+typedef union cvmx_endor_rfif_sample_cnt cvmx_endor_rfif_sample_cnt_t;
+
+/**
+ * cvmx_endor_rfif_skip_frm_cnt_bits
+ */
+union cvmx_endor_rfif_skip_frm_cnt_bits {
+	uint32_t u32;
+	struct cvmx_endor_rfif_skip_frm_cnt_bits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_2_31                : 30;
+	uint32_t bits                         : 2;  /**< Indicates the number of sample count bits to skip, in
+                                                          order to reduce the sample count update frequency and
+                                                          permit a reliable clock crossing from the RF to the
+                                                          HAB clock domain.
+                                                         - 0: No bits are skipped
+                                                          - ...
+                                                         - 3: 3 bits are skipped */
+#else
+	uint32_t bits                         : 2;
+	uint32_t reserved_2_31                : 30;
+#endif
+	} s;
+	struct cvmx_endor_rfif_skip_frm_cnt_bits_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_skip_frm_cnt_bits cvmx_endor_rfif_skip_frm_cnt_bits_t;
+
+/**
+ * cvmx_endor_rfif_spi_#_ll
+ */
+union cvmx_endor_rfif_spi_x_ll {
+	uint32_t u32;
+	struct cvmx_endor_rfif_spi_x_ll_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t num                          : 20; /**< SPI event X start sample count */
+#else
+	uint32_t num                          : 20;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_endor_rfif_spi_x_ll_s     cnf71xx;
+};
+typedef union cvmx_endor_rfif_spi_x_ll cvmx_endor_rfif_spi_x_ll_t;
+
+/**
+ * cvmx_endor_rfif_spi_cmd_attr#
+ */
+union cvmx_endor_rfif_spi_cmd_attrx {
+	uint32_t u32;
+	struct cvmx_endor_rfif_spi_cmd_attrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_4_31                : 28;
+	uint32_t slave                        : 1;  /**< Slave select (in case there are 2 ADI chips)
+                                                         - 0: slave 1
+                                                         - 1: slave 2 */
+	uint32_t bytes                        : 1;  /**< Number of data bytes transfer
+                                                         - 0: 1 byte transfer mode
+                                                         - 1: 2 bytes transfer mode */
+	uint32_t gen_int                      : 1;  /**< Generate an interrupt upon the SPI event completion:
+                                                         - 0: no interrupt generated  1: interrupt generated */
+	uint32_t rw                           : 1;  /**< r/w: r:0 ; w:1. */
+#else
+	uint32_t rw                           : 1;
+	uint32_t gen_int                      : 1;
+	uint32_t bytes                        : 1;
+	uint32_t slave                        : 1;
+	uint32_t reserved_4_31                : 28;
+#endif
+	} s;
+	struct cvmx_endor_rfif_spi_cmd_attrx_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_spi_cmd_attrx cvmx_endor_rfif_spi_cmd_attrx_t;
+
+/**
+ * cvmx_endor_rfif_spi_cmds#
+ */
+union cvmx_endor_rfif_spi_cmdsx {
+	uint32_t u32;
+	struct cvmx_endor_rfif_spi_cmdsx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t word                         : 24; /**< Spi command word. */
+#else
+	uint32_t word                         : 24;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_rfif_spi_cmdsx_s    cnf71xx;
+};
+typedef union cvmx_endor_rfif_spi_cmdsx cvmx_endor_rfif_spi_cmdsx_t;
+
+/**
+ * cvmx_endor_rfif_spi_conf0
+ */
+union cvmx_endor_rfif_spi_conf0 {
+	uint32_t u32;
+	struct cvmx_endor_rfif_spi_conf0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t num_cmds3                    : 6;  /**< Number of SPI cmds to transfer for event 3 */
+	uint32_t num_cmds2                    : 6;  /**< Number of SPI cmds to transfer for event 2 */
+	uint32_t num_cmds1                    : 6;  /**< Number of SPI cmds to transfer for event 1 */
+	uint32_t num_cmds0                    : 6;  /**< Number of SPI cmds to transfer for event 0 */
+#else
+	uint32_t num_cmds0                    : 6;
+	uint32_t num_cmds1                    : 6;
+	uint32_t num_cmds2                    : 6;
+	uint32_t num_cmds3                    : 6;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_rfif_spi_conf0_s    cnf71xx;
+};
+typedef union cvmx_endor_rfif_spi_conf0 cvmx_endor_rfif_spi_conf0_t;
+
+/**
+ * cvmx_endor_rfif_spi_conf1
+ */
+union cvmx_endor_rfif_spi_conf1 {
+	uint32_t u32;
+	struct cvmx_endor_rfif_spi_conf1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t start3                       : 6;  /**< SPI commands start address for event 3 */
+	uint32_t start2                       : 6;  /**< SPI commands start address for event 2 */
+	uint32_t start1                       : 6;  /**< SPI commands start address for event 1 */
+	uint32_t start0                       : 6;  /**< SPI commands start address for event 0 */
+#else
+	uint32_t start0                       : 6;
+	uint32_t start1                       : 6;
+	uint32_t start2                       : 6;
+	uint32_t start3                       : 6;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_rfif_spi_conf1_s    cnf71xx;
+};
+typedef union cvmx_endor_rfif_spi_conf1 cvmx_endor_rfif_spi_conf1_t;
+
+/**
+ * cvmx_endor_rfif_spi_ctrl
+ */
+union cvmx_endor_rfif_spi_ctrl {
+	uint32_t u32;
+	struct cvmx_endor_rfif_spi_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t ctrl                         : 32; /**< Control */
+#else
+	uint32_t ctrl                         : 32;
+#endif
+	} s;
+	struct cvmx_endor_rfif_spi_ctrl_s     cnf71xx;
+};
+typedef union cvmx_endor_rfif_spi_ctrl cvmx_endor_rfif_spi_ctrl_t;
+
+/**
+ * cvmx_endor_rfif_spi_din#
+ */
+union cvmx_endor_rfif_spi_dinx {
+	uint32_t u32;
+	struct cvmx_endor_rfif_spi_dinx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_16_31               : 16;
+	uint32_t data                         : 16; /**< Data read back from spi commands. */
+#else
+	uint32_t data                         : 16;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_endor_rfif_spi_dinx_s     cnf71xx;
+};
+typedef union cvmx_endor_rfif_spi_dinx cvmx_endor_rfif_spi_dinx_t;
+
+/**
+ * cvmx_endor_rfif_spi_rx_data
+ */
+union cvmx_endor_rfif_spi_rx_data {
+	uint32_t u32;
+	struct cvmx_endor_rfif_spi_rx_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t rd_data                      : 32; /**< SPI Read Data */
+#else
+	uint32_t rd_data                      : 32;
+#endif
+	} s;
+	struct cvmx_endor_rfif_spi_rx_data_s  cnf71xx;
+};
+typedef union cvmx_endor_rfif_spi_rx_data cvmx_endor_rfif_spi_rx_data_t;
+
+/**
+ * cvmx_endor_rfif_spi_status
+ */
+union cvmx_endor_rfif_spi_status {
+	uint32_t u32;
+	struct cvmx_endor_rfif_spi_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_12_31               : 20;
+	uint32_t sr_state                     : 4;  /**< SPI State Machine
+                                                         1 : INIT
+                                                         2 : IDLE
+                                                         3 : WAIT_FIFO
+                                                         4 : READ_FIFO
+                                                         5 : LOAD_SR
+                                                         6 : SHIFT_SR
+                                                         7 : WAIT_CLK
+                                                         8 : WAIT_FOR_SS */
+	uint32_t rx_fifo_lvl                  : 4;  /**< Level of RX FIFO */
+	uint32_t tx_fifo_lvl                  : 4;  /**< Level of TX FIFO */
+#else
+	uint32_t tx_fifo_lvl                  : 4;
+	uint32_t rx_fifo_lvl                  : 4;
+	uint32_t sr_state                     : 4;
+	uint32_t reserved_12_31               : 20;
+#endif
+	} s;
+	struct cvmx_endor_rfif_spi_status_s   cnf71xx;
+};
+typedef union cvmx_endor_rfif_spi_status cvmx_endor_rfif_spi_status_t;
+
+/**
+ * cvmx_endor_rfif_spi_tx_data
+ */
+union cvmx_endor_rfif_spi_tx_data {
+	uint32_t u32;
+	struct cvmx_endor_rfif_spi_tx_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t write                        : 1;  /**< When set, execute write. Otherwise, read. */
+	uint32_t reserved_25_30               : 6;
+	uint32_t addr                         : 9;  /**< SPI Address */
+	uint32_t data                         : 8;  /**< SPI Data */
+	uint32_t reserved_0_7                 : 8;
+#else
+	uint32_t reserved_0_7                 : 8;
+	uint32_t data                         : 8;
+	uint32_t addr                         : 9;
+	uint32_t reserved_25_30               : 6;
+	uint32_t write                        : 1;
+#endif
+	} s;
+	struct cvmx_endor_rfif_spi_tx_data_s  cnf71xx;
+};
+typedef union cvmx_endor_rfif_spi_tx_data cvmx_endor_rfif_spi_tx_data_t;
+
+/**
+ * cvmx_endor_rfif_timer64_cfg
+ */
+union cvmx_endor_rfif_timer64_cfg {
+	uint32_t u32;
+	struct cvmx_endor_rfif_timer64_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_8_31                : 24;
+	uint32_t clks                         : 8;  /**< 7-0: Number of rf clock cycles per 64-bit timer
+                                                         increment. Set to n for n+1 cycles (default=0x7F for
+                                                         128 cycles).  The valid range for the register is 3 to
+                                                         255. */
+#else
+	uint32_t clks                         : 8;
+	uint32_t reserved_8_31                : 24;
+#endif
+	} s;
+	struct cvmx_endor_rfif_timer64_cfg_s  cnf71xx;
+};
+typedef union cvmx_endor_rfif_timer64_cfg cvmx_endor_rfif_timer64_cfg_t;
+
+/**
+ * cvmx_endor_rfif_timer64_en
+ *
+ * Notes:
+ * This is how the 64-bit timer works:
+ * 1- Configuration
+ *     - Write counter LSB (reg:0x69)
+ *     - Write counter MSB (reg:0x6A)
+ *     - Write config (reg:0x68)
+ * 2- Enable the counter
+ * 3- Wait for the 1PPS
+ * 4- Start incrementing the counter every n+1 rf clock cycles
+ * 5- Read the MSB and LSB registers (reg:0x6B and 0x6C)
+ *
+ * 6- There is no 64-bit snapshot mechanism. Software has to consider the
+ *    32 LSB might rollover and increment the 32 MSB between the LSB and the
+ *    MSB reads. You may want to use the following concatenation recipe:
+ *
+ * a) Read the 32 MSB (MSB1)
+ * b) Read the 32 LSB
+ * c) Read the 32 MSB again (MSB2)
+ * d) Concatenate the 32 MSB an 32 LSB
+ *      -If both 32 MSB are equal or LSB(31)=1, concatenate MSB1 and LSB
+ *      -Else concatenate the MSB2 and LSB
+ */
+union cvmx_endor_rfif_timer64_en {
+	uint32_t u32;
+	struct cvmx_endor_rfif_timer64_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_1_31                : 31;
+	uint32_t ena                          : 1;  /**< Enable for the 64-bit rf clock based timer.
+                                                         - 0: Disabled
+                                                         - 1: Enabled */
+#else
+	uint32_t ena                          : 1;
+	uint32_t reserved_1_31                : 31;
+#endif
+	} s;
+	struct cvmx_endor_rfif_timer64_en_s   cnf71xx;
+};
+typedef union cvmx_endor_rfif_timer64_en cvmx_endor_rfif_timer64_en_t;
+
+/**
+ * cvmx_endor_rfif_tti_scnt_int#
+ */
+union cvmx_endor_rfif_tti_scnt_intx {
+	uint32_t u32;
+	struct cvmx_endor_rfif_tti_scnt_intx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t intr                         : 20; /**< TTI Sample Count Interrupt:
+                                                         Indicates the sample count of the selected reference
+                                                         counter at which to generate an interrupt. */
+#else
+	uint32_t intr                         : 20;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_endor_rfif_tti_scnt_intx_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_tti_scnt_intx cvmx_endor_rfif_tti_scnt_intx_t;
+
+/**
+ * cvmx_endor_rfif_tti_scnt_int_clr
+ */
+union cvmx_endor_rfif_tti_scnt_int_clr {
+	uint32_t u32;
+	struct cvmx_endor_rfif_tti_scnt_int_clr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_8_31                : 24;
+	uint32_t cnt                          : 8;  /**< TTI Sample Count Interrupt Status register:
+                                                         Writing 0x1 to clear the TTI_SCNT_INT_STAT(0), writing
+                                                         0x2 to clear the TTI_SCNT_INT_STAT(1) and so on. */
+#else
+	uint32_t cnt                          : 8;
+	uint32_t reserved_8_31                : 24;
+#endif
+	} s;
+	struct cvmx_endor_rfif_tti_scnt_int_clr_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_tti_scnt_int_clr cvmx_endor_rfif_tti_scnt_int_clr_t;
+
+/**
+ * cvmx_endor_rfif_tti_scnt_int_en
+ */
+union cvmx_endor_rfif_tti_scnt_int_en {
+	uint32_t u32;
+	struct cvmx_endor_rfif_tti_scnt_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_8_31                : 24;
+	uint32_t ena                          : 8;  /**< TTI Sample Counter Interrupt Enable:
+                                                         Bit 0: 1  Enables TTI_SCNT_INT_0
+                                                         Bit 1: 1 Enables TTI_SCNT_INT_1
+                                                         - ...
+                                                         Bit 7: 1  Enables TTI_SCNT_INT_7
+                                                         Note these interrupts are disabled by default (=0x00). */
+#else
+	uint32_t ena                          : 8;
+	uint32_t reserved_8_31                : 24;
+#endif
+	} s;
+	struct cvmx_endor_rfif_tti_scnt_int_en_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_tti_scnt_int_en cvmx_endor_rfif_tti_scnt_int_en_t;
+
+/**
+ * cvmx_endor_rfif_tti_scnt_int_map
+ */
+union cvmx_endor_rfif_tti_scnt_int_map {
+	uint32_t u32;
+	struct cvmx_endor_rfif_tti_scnt_int_map_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_8_31                : 24;
+	uint32_t map                          : 8;  /**< TTI Sample Count Interrupt Mapping to a Reference
+                                                         Counter:
+                                                         Indicates the reference counter the TTI Sample Count
+                                                         Interrupts must be generated from. A value of 0
+                                                         indicates the RX reference counter (default) and a
+                                                         value of 1 indicates the TX reference counter. The
+                                                         bit 0 is associated with TTI_SCNT_INT_0, the bit 1
+                                                         is associated with TTI_SCNT_INT_1 and so on.
+                                                         Note that This register has not effect in TDD mode,
+                                                         only in FDD mode. */
+#else
+	uint32_t map                          : 8;
+	uint32_t reserved_8_31                : 24;
+#endif
+	} s;
+	struct cvmx_endor_rfif_tti_scnt_int_map_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_tti_scnt_int_map cvmx_endor_rfif_tti_scnt_int_map_t;
+
+/**
+ * cvmx_endor_rfif_tti_scnt_int_stat
+ */
+union cvmx_endor_rfif_tti_scnt_int_stat {
+	uint32_t u32;
+	struct cvmx_endor_rfif_tti_scnt_int_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_8_31                : 24;
+	uint32_t cnt                          : 8;  /**< TTI Sample Count Interrupt Status register:
+                                                         Indicates if a TTI_SCNT_INT_X occurred (1) or not (0).
+                                                         The bit 0 is associated with TTI_SCNT_INT_0 and so on
+                                                         incrementally. Writing a 1 will clear the interrupt
+                                                         bit. */
+#else
+	uint32_t cnt                          : 8;
+	uint32_t reserved_8_31                : 24;
+#endif
+	} s;
+	struct cvmx_endor_rfif_tti_scnt_int_stat_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_tti_scnt_int_stat cvmx_endor_rfif_tti_scnt_int_stat_t;
+
+/**
+ * cvmx_endor_rfif_tx_div_status
+ *
+ * Notes:
+ * In TDD Mode, bits 15:12 are DDR state machine status.
+ *
+ */
+union cvmx_endor_rfif_tx_div_status {
+	uint32_t u32;
+	struct cvmx_endor_rfif_tx_div_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_23_31               : 9;
+	uint32_t rfic_ena                     : 1;  /**< RFIC enabled (in alert state) */
+	uint32_t sync_late                    : 1;  /**< Sync late (Used for UE products). */
+	uint32_t reserved_19_20               : 2;
+	uint32_t thresh_rch                   : 1;  /**< Threshold Reached (RX/RX_div/TX) */
+	uint32_t fifo_of                      : 1;  /**< FIFO overflow */
+	uint32_t fifo_ur                      : 1;  /**< FIFO underrun */
+	uint32_t tx_sm                        : 2;  /**< TX state machine status */
+	uint32_t rx_sm                        : 2;  /**< RX state machine status */
+	uint32_t hab_req_sm                   : 4;  /**< HAB request manager SM
+                                                         - 0: idle
+                                                         - 1: wait_cs
+                                                         - 2: Term
+                                                         - 3: rd_fifo(RX)/ write fifo(TX)
+                                                         - 4: wait_th
+                                                          Others: not used */
+	uint32_t reserved_0_7                 : 8;
+#else
+	uint32_t reserved_0_7                 : 8;
+	uint32_t hab_req_sm                   : 4;
+	uint32_t rx_sm                        : 2;
+	uint32_t tx_sm                        : 2;
+	uint32_t fifo_ur                      : 1;
+	uint32_t fifo_of                      : 1;
+	uint32_t thresh_rch                   : 1;
+	uint32_t reserved_19_20               : 2;
+	uint32_t sync_late                    : 1;
+	uint32_t rfic_ena                     : 1;
+	uint32_t reserved_23_31               : 9;
+#endif
+	} s;
+	struct cvmx_endor_rfif_tx_div_status_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_tx_div_status cvmx_endor_rfif_tx_div_status_t;
+
+/**
+ * cvmx_endor_rfif_tx_if_cfg
+ */
+union cvmx_endor_rfif_tx_if_cfg {
+	uint32_t u32;
+	struct cvmx_endor_rfif_tx_if_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_4_31                : 28;
+	uint32_t mode                         : 1;  /**< TX communication mode
+                                                         - 0: TX SISO (default)
+                                                         - 1: TX MIMO */
+	uint32_t dis_sch                      : 1;  /**< Disabled antenna driving scheme (TX SISO/RX MIMO
+                                                          feature only)
+                                                         - 0: Constant 0 for debugging (default)
+                                                         - 1: Same as previous cycle to minimize IO switching */
+	uint32_t antenna                      : 2;  /**< Transmit on antenna A and/or B (TX SISO/RX MIMO
+                                                          feature only)
+                                                         - 0: Transmit on antenna A (default)
+                                                         - 1: Transmit on antenna B
+                                                         - 2: Transmit on A and B
+                                                         - 3: Reserved */
+#else
+	uint32_t antenna                      : 2;
+	uint32_t dis_sch                      : 1;
+	uint32_t mode                         : 1;
+	uint32_t reserved_4_31                : 28;
+#endif
+	} s;
+	struct cvmx_endor_rfif_tx_if_cfg_s    cnf71xx;
+};
+typedef union cvmx_endor_rfif_tx_if_cfg cvmx_endor_rfif_tx_if_cfg_t;
+
+/**
+ * cvmx_endor_rfif_tx_lead_lag
+ */
+union cvmx_endor_rfif_tx_lead_lag {
+	uint32_t u32;
+	struct cvmx_endor_rfif_tx_lead_lag_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t lag                          : 12; /**< unsigned value (lag) on end of window */
+	uint32_t lead                         : 12; /**< unsigned value (lead) on beginning of window */
+#else
+	uint32_t lead                         : 12;
+	uint32_t lag                          : 12;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_rfif_tx_lead_lag_s  cnf71xx;
+};
+typedef union cvmx_endor_rfif_tx_lead_lag cvmx_endor_rfif_tx_lead_lag_t;
+
+/**
+ * cvmx_endor_rfif_tx_offset
+ */
+union cvmx_endor_rfif_tx_offset {
+	uint32_t u32;
+	struct cvmx_endor_rfif_tx_offset_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t offset                       : 20; /**< Indicates the number of RF clock cycles after the
+                                                         GPS/ETH 1PPS is received before the start of the RX
+                                                         frame. See description Figure 44. */
+#else
+	uint32_t offset                       : 20;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_endor_rfif_tx_offset_s    cnf71xx;
+};
+typedef union cvmx_endor_rfif_tx_offset cvmx_endor_rfif_tx_offset_t;
+
+/**
+ * cvmx_endor_rfif_tx_offset_adj_scnt
+ */
+union cvmx_endor_rfif_tx_offset_adj_scnt {
+	uint32_t u32;
+	struct cvmx_endor_rfif_tx_offset_adj_scnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t cnt                          : 20; /**< Indicates the TX sample count at which the 1PPS
+                                                         incremental adjustments will be applied. */
+#else
+	uint32_t cnt                          : 20;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_endor_rfif_tx_offset_adj_scnt_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_tx_offset_adj_scnt cvmx_endor_rfif_tx_offset_adj_scnt_t;
+
+/**
+ * cvmx_endor_rfif_tx_status
+ *
+ * Notes:
+ * In TDD Mode, bits 15:12 are DDR state machine status.
+ *
+ */
+union cvmx_endor_rfif_tx_status {
+	uint32_t u32;
+	struct cvmx_endor_rfif_tx_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_23_31               : 9;
+	uint32_t rfic_ena                     : 1;  /**< RFIC enabled (in alert state) */
+	uint32_t sync_late                    : 1;  /**< Sync late (Used for UE products). */
+	uint32_t reserved_19_20               : 2;
+	uint32_t thresh_rch                   : 1;  /**< Threshold Reached (RX/RX_div/TX) */
+	uint32_t fifo_of                      : 1;  /**< FIFO overflow */
+	uint32_t fifo_ur                      : 1;  /**< FIFO underrun */
+	uint32_t tx_sm                        : 2;  /**< TX state machine status */
+	uint32_t rx_sm                        : 2;  /**< RX state machine status */
+	uint32_t hab_req_sm                   : 4;  /**< HAB request manager SM
+                                                         - 0: idle
+                                                         - 1: wait_cs
+                                                         - 2: Term
+                                                         - 3: rd_fifo(RX)/ write fifo(TX)
+                                                         - 4: wait_th
+                                                          Others: not used */
+	uint32_t reserved_0_7                 : 8;
+#else
+	uint32_t reserved_0_7                 : 8;
+	uint32_t hab_req_sm                   : 4;
+	uint32_t rx_sm                        : 2;
+	uint32_t tx_sm                        : 2;
+	uint32_t fifo_ur                      : 1;
+	uint32_t fifo_of                      : 1;
+	uint32_t thresh_rch                   : 1;
+	uint32_t reserved_19_20               : 2;
+	uint32_t sync_late                    : 1;
+	uint32_t rfic_ena                     : 1;
+	uint32_t reserved_23_31               : 9;
+#endif
+	} s;
+	struct cvmx_endor_rfif_tx_status_s    cnf71xx;
+};
+typedef union cvmx_endor_rfif_tx_status cvmx_endor_rfif_tx_status_t;
+
+/**
+ * cvmx_endor_rfif_tx_th
+ */
+union cvmx_endor_rfif_tx_th {
+	uint32_t u32;
+	struct cvmx_endor_rfif_tx_th_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_12_31               : 20;
+	uint32_t thr                          : 12; /**< FIFO level reached before granting a TX DMA request.
+                                                         This TX FIFO fill level threshold can be used
+                                                         in two ways:
+                                                              1- When the FIFO fill level reaches the threshold,
+                                                         there is enough data in the FIFO to start the data
+                                                         transfer, so it grants a DMA transfer from the TX FIFO
+                                                         to the HAB's memory.
+                                                              2- It can also be used to generate an interrupt to
+                                                         the DSP when the FIFO threshold is reached. */
+#else
+	uint32_t thr                          : 12;
+	uint32_t reserved_12_31               : 20;
+#endif
+	} s;
+	struct cvmx_endor_rfif_tx_th_s        cnf71xx;
+};
+typedef union cvmx_endor_rfif_tx_th cvmx_endor_rfif_tx_th_t;
+
+/**
+ * cvmx_endor_rfif_win_en
+ */
+union cvmx_endor_rfif_win_en {
+	uint32_t u32;
+	struct cvmx_endor_rfif_win_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_4_31                : 28;
+	uint32_t enable                       : 4;  /**< Receive windows enable (all enabled by default)
+                                                         Bit 0: 1 window 1 enabled, 0 window 1 disabled
+                                                         - ...
+                                                         Bit 3: 1 window 3 enabled, 0 window 3 disabled.
+                                                         Bits 23-4: not used */
+#else
+	uint32_t enable                       : 4;
+	uint32_t reserved_4_31                : 28;
+#endif
+	} s;
+	struct cvmx_endor_rfif_win_en_s       cnf71xx;
+};
+typedef union cvmx_endor_rfif_win_en cvmx_endor_rfif_win_en_t;
+
+/**
+ * cvmx_endor_rfif_win_upd_scnt
+ */
+union cvmx_endor_rfif_win_upd_scnt {
+	uint32_t u32;
+	struct cvmx_endor_rfif_win_upd_scnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t scnt                         : 20; /**< Receive window update sample count. This is the count
+                                                         at which the following registers newly programmed value
+                                                         will take effect. RX_WIN_EN(3-0), RX_W_S (19-0),
+                                                         RX_W_E(19-0), NUM_RX_WIN(3-0),  FRAME_L(19-0),
+                                                         RX_LEAD_LAG(23-0) */
+#else
+	uint32_t scnt                         : 20;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_endor_rfif_win_upd_scnt_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_win_upd_scnt cvmx_endor_rfif_win_upd_scnt_t;
+
+/**
+ * cvmx_endor_rfif_wr_timer64_lsb
+ */
+union cvmx_endor_rfif_wr_timer64_lsb {
+	uint32_t u32;
+	struct cvmx_endor_rfif_wr_timer64_lsb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t val                          : 32; /**< 64-bit timer initial value of the 32 LSB. */
+#else
+	uint32_t val                          : 32;
+#endif
+	} s;
+	struct cvmx_endor_rfif_wr_timer64_lsb_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_wr_timer64_lsb cvmx_endor_rfif_wr_timer64_lsb_t;
+
+/**
+ * cvmx_endor_rfif_wr_timer64_msb
+ */
+union cvmx_endor_rfif_wr_timer64_msb {
+	uint32_t u32;
+	struct cvmx_endor_rfif_wr_timer64_msb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t val                          : 32; /**< 64-bit timer initial value of the 32 MSB. */
+#else
+	uint32_t val                          : 32;
+#endif
+	} s;
+	struct cvmx_endor_rfif_wr_timer64_msb_s cnf71xx;
+};
+typedef union cvmx_endor_rfif_wr_timer64_msb cvmx_endor_rfif_wr_timer64_msb_t;
+
+/**
+ * cvmx_endor_rstclk_clkenb0_clr
+ */
+union cvmx_endor_rstclk_clkenb0_clr {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_clkenb0_clr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_13_31               : 19;
+	uint32_t axidma                       : 1;  /**< abc */
+	uint32_t txseq                        : 1;  /**< abc */
+	uint32_t v3genc                       : 1;  /**< abc */
+	uint32_t ifftpapr                     : 1;  /**< abc */
+	uint32_t lteenc                       : 1;  /**< abc */
+	uint32_t vdec                         : 1;  /**< abc */
+	uint32_t turbodsp                     : 1;  /**< abc */
+	uint32_t turbophy                     : 1;  /**< abc */
+	uint32_t rx1seq                       : 1;  /**< abc */
+	uint32_t dftdmap                      : 1;  /**< abc */
+	uint32_t rx0seq                       : 1;  /**< abc */
+	uint32_t rachfe                       : 1;  /**< abc */
+	uint32_t ulfe                         : 1;  /**< abc */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachfe                       : 1;
+	uint32_t rx0seq                       : 1;
+	uint32_t dftdmap                      : 1;
+	uint32_t rx1seq                       : 1;
+	uint32_t turbophy                     : 1;
+	uint32_t turbodsp                     : 1;
+	uint32_t vdec                         : 1;
+	uint32_t lteenc                       : 1;
+	uint32_t ifftpapr                     : 1;
+	uint32_t v3genc                       : 1;
+	uint32_t txseq                        : 1;
+	uint32_t axidma                       : 1;
+	uint32_t reserved_13_31               : 19;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_clkenb0_clr_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_clkenb0_clr cvmx_endor_rstclk_clkenb0_clr_t;
+
+/**
+ * cvmx_endor_rstclk_clkenb0_set
+ */
+union cvmx_endor_rstclk_clkenb0_set {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_clkenb0_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_13_31               : 19;
+	uint32_t axidma                       : 1;  /**< abc */
+	uint32_t txseq                        : 1;  /**< abc */
+	uint32_t v3genc                       : 1;  /**< abc */
+	uint32_t ifftpapr                     : 1;  /**< abc */
+	uint32_t lteenc                       : 1;  /**< abc */
+	uint32_t vdec                         : 1;  /**< abc */
+	uint32_t turbodsp                     : 1;  /**< abc */
+	uint32_t turbophy                     : 1;  /**< abc */
+	uint32_t rx1seq                       : 1;  /**< abc */
+	uint32_t dftdmap                      : 1;  /**< abc */
+	uint32_t rx0seq                       : 1;  /**< abc */
+	uint32_t rachfe                       : 1;  /**< abc */
+	uint32_t ulfe                         : 1;  /**< abc */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachfe                       : 1;
+	uint32_t rx0seq                       : 1;
+	uint32_t dftdmap                      : 1;
+	uint32_t rx1seq                       : 1;
+	uint32_t turbophy                     : 1;
+	uint32_t turbodsp                     : 1;
+	uint32_t vdec                         : 1;
+	uint32_t lteenc                       : 1;
+	uint32_t ifftpapr                     : 1;
+	uint32_t v3genc                       : 1;
+	uint32_t txseq                        : 1;
+	uint32_t axidma                       : 1;
+	uint32_t reserved_13_31               : 19;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_clkenb0_set_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_clkenb0_set cvmx_endor_rstclk_clkenb0_set_t;
+
+/**
+ * cvmx_endor_rstclk_clkenb0_state
+ */
+union cvmx_endor_rstclk_clkenb0_state {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_clkenb0_state_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_13_31               : 19;
+	uint32_t axidma                       : 1;  /**< abc */
+	uint32_t txseq                        : 1;  /**< abc */
+	uint32_t v3genc                       : 1;  /**< abc */
+	uint32_t ifftpapr                     : 1;  /**< abc */
+	uint32_t lteenc                       : 1;  /**< abc */
+	uint32_t vdec                         : 1;  /**< abc */
+	uint32_t turbodsp                     : 1;  /**< abc */
+	uint32_t turbophy                     : 1;  /**< abc */
+	uint32_t rx1seq                       : 1;  /**< abc */
+	uint32_t dftdmap                      : 1;  /**< abc */
+	uint32_t rx0seq                       : 1;  /**< abc */
+	uint32_t rachfe                       : 1;  /**< abc */
+	uint32_t ulfe                         : 1;  /**< abc */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachfe                       : 1;
+	uint32_t rx0seq                       : 1;
+	uint32_t dftdmap                      : 1;
+	uint32_t rx1seq                       : 1;
+	uint32_t turbophy                     : 1;
+	uint32_t turbodsp                     : 1;
+	uint32_t vdec                         : 1;
+	uint32_t lteenc                       : 1;
+	uint32_t ifftpapr                     : 1;
+	uint32_t v3genc                       : 1;
+	uint32_t txseq                        : 1;
+	uint32_t axidma                       : 1;
+	uint32_t reserved_13_31               : 19;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_clkenb0_state_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_clkenb0_state cvmx_endor_rstclk_clkenb0_state_t;
+
+/**
+ * cvmx_endor_rstclk_clkenb1_clr
+ */
+union cvmx_endor_rstclk_clkenb1_clr {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_clkenb1_clr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_7_31                : 25;
+	uint32_t token                        : 1;  /**< abc */
+	uint32_t tile3dsp                     : 1;  /**< abc */
+	uint32_t tile2dsp                     : 1;  /**< abc */
+	uint32_t tile1dsp                     : 1;  /**< abc */
+	uint32_t rfspi                        : 1;  /**< abc */
+	uint32_t rfif_hab                     : 1;  /**< abc */
+	uint32_t rfif_rf                      : 1;  /**< abc */
+#else
+	uint32_t rfif_rf                      : 1;
+	uint32_t rfif_hab                     : 1;
+	uint32_t rfspi                        : 1;
+	uint32_t tile1dsp                     : 1;
+	uint32_t tile2dsp                     : 1;
+	uint32_t tile3dsp                     : 1;
+	uint32_t token                        : 1;
+	uint32_t reserved_7_31                : 25;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_clkenb1_clr_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_clkenb1_clr cvmx_endor_rstclk_clkenb1_clr_t;
+
+/**
+ * cvmx_endor_rstclk_clkenb1_set
+ */
+union cvmx_endor_rstclk_clkenb1_set {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_clkenb1_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_7_31                : 25;
+	uint32_t token                        : 1;  /**< abc */
+	uint32_t tile3dsp                     : 1;  /**< abc */
+	uint32_t tile2dsp                     : 1;  /**< abc */
+	uint32_t tile1dsp                     : 1;  /**< abc */
+	uint32_t rfspi                        : 1;  /**< abc */
+	uint32_t rfif_hab                     : 1;  /**< abc */
+	uint32_t rfif_rf                      : 1;  /**< abc */
+#else
+	uint32_t rfif_rf                      : 1;
+	uint32_t rfif_hab                     : 1;
+	uint32_t rfspi                        : 1;
+	uint32_t tile1dsp                     : 1;
+	uint32_t tile2dsp                     : 1;
+	uint32_t tile3dsp                     : 1;
+	uint32_t token                        : 1;
+	uint32_t reserved_7_31                : 25;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_clkenb1_set_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_clkenb1_set cvmx_endor_rstclk_clkenb1_set_t;
+
+/**
+ * cvmx_endor_rstclk_clkenb1_state
+ */
+union cvmx_endor_rstclk_clkenb1_state {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_clkenb1_state_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_7_31                : 25;
+	uint32_t token                        : 1;  /**< abc */
+	uint32_t tile3dsp                     : 1;  /**< abc */
+	uint32_t tile2dsp                     : 1;  /**< abc */
+	uint32_t tile1dsp                     : 1;  /**< abc */
+	uint32_t rfspi                        : 1;  /**< abc */
+	uint32_t rfif_hab                     : 1;  /**< abc */
+	uint32_t rfif_rf                      : 1;  /**< abc */
+#else
+	uint32_t rfif_rf                      : 1;
+	uint32_t rfif_hab                     : 1;
+	uint32_t rfspi                        : 1;
+	uint32_t tile1dsp                     : 1;
+	uint32_t tile2dsp                     : 1;
+	uint32_t tile3dsp                     : 1;
+	uint32_t token                        : 1;
+	uint32_t reserved_7_31                : 25;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_clkenb1_state_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_clkenb1_state cvmx_endor_rstclk_clkenb1_state_t;
+
+/**
+ * cvmx_endor_rstclk_dspstall_clr
+ */
+union cvmx_endor_rstclk_dspstall_clr {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_dspstall_clr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t txdsp1                       : 1;  /**< abc */
+	uint32_t txdsp0                       : 1;  /**< abc */
+	uint32_t rx1dsp1                      : 1;  /**< abc */
+	uint32_t rx1dsp0                      : 1;  /**< abc */
+	uint32_t rx0dsp1                      : 1;  /**< abc */
+	uint32_t rx0dsp0                      : 1;  /**< abc */
+#else
+	uint32_t rx0dsp0                      : 1;
+	uint32_t rx0dsp1                      : 1;
+	uint32_t rx1dsp0                      : 1;
+	uint32_t rx1dsp1                      : 1;
+	uint32_t txdsp0                       : 1;
+	uint32_t txdsp1                       : 1;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_dspstall_clr_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_dspstall_clr cvmx_endor_rstclk_dspstall_clr_t;
+
+/**
+ * cvmx_endor_rstclk_dspstall_set
+ */
+union cvmx_endor_rstclk_dspstall_set {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_dspstall_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t txdsp1                       : 1;  /**< abc */
+	uint32_t txdsp0                       : 1;  /**< abc */
+	uint32_t rx1dsp1                      : 1;  /**< abc */
+	uint32_t rx1dsp0                      : 1;  /**< abc */
+	uint32_t rx0dsp1                      : 1;  /**< abc */
+	uint32_t rx0dsp0                      : 1;  /**< abc */
+#else
+	uint32_t rx0dsp0                      : 1;
+	uint32_t rx0dsp1                      : 1;
+	uint32_t rx1dsp0                      : 1;
+	uint32_t rx1dsp1                      : 1;
+	uint32_t txdsp0                       : 1;
+	uint32_t txdsp1                       : 1;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_dspstall_set_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_dspstall_set cvmx_endor_rstclk_dspstall_set_t;
+
+/**
+ * cvmx_endor_rstclk_dspstall_state
+ */
+union cvmx_endor_rstclk_dspstall_state {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_dspstall_state_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t txdsp1                       : 1;  /**< abc */
+	uint32_t txdsp0                       : 1;  /**< abc */
+	uint32_t rx1dsp1                      : 1;  /**< abc */
+	uint32_t rx1dsp0                      : 1;  /**< abc */
+	uint32_t rx0dsp1                      : 1;  /**< abc */
+	uint32_t rx0dsp0                      : 1;  /**< abc */
+#else
+	uint32_t rx0dsp0                      : 1;
+	uint32_t rx0dsp1                      : 1;
+	uint32_t rx1dsp0                      : 1;
+	uint32_t rx1dsp1                      : 1;
+	uint32_t txdsp0                       : 1;
+	uint32_t txdsp1                       : 1;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_dspstall_state_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_dspstall_state cvmx_endor_rstclk_dspstall_state_t;
+
+/**
+ * cvmx_endor_rstclk_intr0_clrmask
+ */
+union cvmx_endor_rstclk_intr0_clrmask {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_intr0_clrmask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t timer_intr                   : 8;  /**< reserved. */
+	uint32_t sw_intr                      : 24; /**< reserved. */
+#else
+	uint32_t sw_intr                      : 24;
+	uint32_t timer_intr                   : 8;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_intr0_clrmask_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_intr0_clrmask cvmx_endor_rstclk_intr0_clrmask_t;
+
+/**
+ * cvmx_endor_rstclk_intr0_mask
+ */
+union cvmx_endor_rstclk_intr0_mask {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_intr0_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t timer_intr                   : 8;  /**< reserved. */
+	uint32_t sw_intr                      : 24; /**< reserved. */
+#else
+	uint32_t sw_intr                      : 24;
+	uint32_t timer_intr                   : 8;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_intr0_mask_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_intr0_mask cvmx_endor_rstclk_intr0_mask_t;
+
+/**
+ * cvmx_endor_rstclk_intr0_setmask
+ */
+union cvmx_endor_rstclk_intr0_setmask {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_intr0_setmask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t timer_intr                   : 8;  /**< reserved. */
+	uint32_t sw_intr                      : 24; /**< reserved. */
+#else
+	uint32_t sw_intr                      : 24;
+	uint32_t timer_intr                   : 8;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_intr0_setmask_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_intr0_setmask cvmx_endor_rstclk_intr0_setmask_t;
+
+/**
+ * cvmx_endor_rstclk_intr0_status
+ */
+union cvmx_endor_rstclk_intr0_status {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_intr0_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t value                        : 32; /**< reserved. */
+#else
+	uint32_t value                        : 32;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_intr0_status_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_intr0_status cvmx_endor_rstclk_intr0_status_t;
+
+/**
+ * cvmx_endor_rstclk_intr1_clrmask
+ */
+union cvmx_endor_rstclk_intr1_clrmask {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_intr1_clrmask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t value                        : 32; /**< reserved. */
+#else
+	uint32_t value                        : 32;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_intr1_clrmask_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_intr1_clrmask cvmx_endor_rstclk_intr1_clrmask_t;
+
+/**
+ * cvmx_endor_rstclk_intr1_mask
+ */
+union cvmx_endor_rstclk_intr1_mask {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_intr1_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t value                        : 32; /**< reserved. */
+#else
+	uint32_t value                        : 32;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_intr1_mask_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_intr1_mask cvmx_endor_rstclk_intr1_mask_t;
+
+/**
+ * cvmx_endor_rstclk_intr1_setmask
+ */
+union cvmx_endor_rstclk_intr1_setmask {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_intr1_setmask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t value                        : 32; /**< reserved. */
+#else
+	uint32_t value                        : 32;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_intr1_setmask_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_intr1_setmask cvmx_endor_rstclk_intr1_setmask_t;
+
+/**
+ * cvmx_endor_rstclk_intr1_status
+ */
+union cvmx_endor_rstclk_intr1_status {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_intr1_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t value                        : 32; /**< reserved. */
+#else
+	uint32_t value                        : 32;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_intr1_status_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_intr1_status cvmx_endor_rstclk_intr1_status_t;
+
+/**
+ * cvmx_endor_rstclk_phy_config
+ */
+union cvmx_endor_rstclk_phy_config {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_phy_config_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_6_31                : 26;
+	uint32_t t3smem_initenb               : 1;  /**< abc */
+	uint32_t t3imem_initenb               : 1;  /**< abc */
+	uint32_t t2smem_initenb               : 1;  /**< abc */
+	uint32_t t2imem_initenb               : 1;  /**< abc */
+	uint32_t t1smem_initenb               : 1;  /**< abc */
+	uint32_t t1imem_initenb               : 1;  /**< abc */
+#else
+	uint32_t t1imem_initenb               : 1;
+	uint32_t t1smem_initenb               : 1;
+	uint32_t t2imem_initenb               : 1;
+	uint32_t t2smem_initenb               : 1;
+	uint32_t t3imem_initenb               : 1;
+	uint32_t t3smem_initenb               : 1;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_phy_config_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_phy_config cvmx_endor_rstclk_phy_config_t;
+
+/**
+ * cvmx_endor_rstclk_proc_mon
+ */
+union cvmx_endor_rstclk_proc_mon {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_proc_mon_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_18_31               : 14;
+	uint32_t transistor_sel               : 2;  /**< 01==RVT, 10==HVT. */
+	uint32_t ringosc_count                : 16; /**< reserved. */
+#else
+	uint32_t ringosc_count                : 16;
+	uint32_t transistor_sel               : 2;
+	uint32_t reserved_18_31               : 14;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_proc_mon_s   cnf71xx;
+};
+typedef union cvmx_endor_rstclk_proc_mon cvmx_endor_rstclk_proc_mon_t;
+
+/**
+ * cvmx_endor_rstclk_proc_mon_count
+ */
+union cvmx_endor_rstclk_proc_mon_count {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_proc_mon_count_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t count                        : 24; /**< reserved. */
+#else
+	uint32_t count                        : 24;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_proc_mon_count_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_proc_mon_count cvmx_endor_rstclk_proc_mon_count_t;
+
+/**
+ * cvmx_endor_rstclk_reset0_clr
+ */
+union cvmx_endor_rstclk_reset0_clr {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_reset0_clr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_13_31               : 19;
+	uint32_t axidma                       : 1;  /**< abc */
+	uint32_t txseq                        : 1;  /**< abc */
+	uint32_t v3genc                       : 1;  /**< abc */
+	uint32_t ifftpapr                     : 1;  /**< abc */
+	uint32_t lteenc                       : 1;  /**< abc */
+	uint32_t vdec                         : 1;  /**< abc */
+	uint32_t turbodsp                     : 1;  /**< abc */
+	uint32_t turbophy                     : 1;  /**< abc */
+	uint32_t rx1seq                       : 1;  /**< abc */
+	uint32_t dftdmap                      : 1;  /**< abc */
+	uint32_t rx0seq                       : 1;  /**< abc */
+	uint32_t rachfe                       : 1;  /**< abc */
+	uint32_t ulfe                         : 1;  /**< abc */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachfe                       : 1;
+	uint32_t rx0seq                       : 1;
+	uint32_t dftdmap                      : 1;
+	uint32_t rx1seq                       : 1;
+	uint32_t turbophy                     : 1;
+	uint32_t turbodsp                     : 1;
+	uint32_t vdec                         : 1;
+	uint32_t lteenc                       : 1;
+	uint32_t ifftpapr                     : 1;
+	uint32_t v3genc                       : 1;
+	uint32_t txseq                        : 1;
+	uint32_t axidma                       : 1;
+	uint32_t reserved_13_31               : 19;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_reset0_clr_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_reset0_clr cvmx_endor_rstclk_reset0_clr_t;
+
+/**
+ * cvmx_endor_rstclk_reset0_set
+ */
+union cvmx_endor_rstclk_reset0_set {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_reset0_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_13_31               : 19;
+	uint32_t axidma                       : 1;  /**< abc */
+	uint32_t txseq                        : 1;  /**< abc */
+	uint32_t v3genc                       : 1;  /**< abc */
+	uint32_t ifftpapr                     : 1;  /**< abc */
+	uint32_t lteenc                       : 1;  /**< abc */
+	uint32_t vdec                         : 1;  /**< abc */
+	uint32_t turbodsp                     : 1;  /**< abc */
+	uint32_t turbophy                     : 1;  /**< abc */
+	uint32_t rx1seq                       : 1;  /**< abc */
+	uint32_t dftdmap                      : 1;  /**< abc */
+	uint32_t rx0seq                       : 1;  /**< abc */
+	uint32_t rachfe                       : 1;  /**< abc */
+	uint32_t ulfe                         : 1;  /**< abc */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachfe                       : 1;
+	uint32_t rx0seq                       : 1;
+	uint32_t dftdmap                      : 1;
+	uint32_t rx1seq                       : 1;
+	uint32_t turbophy                     : 1;
+	uint32_t turbodsp                     : 1;
+	uint32_t vdec                         : 1;
+	uint32_t lteenc                       : 1;
+	uint32_t ifftpapr                     : 1;
+	uint32_t v3genc                       : 1;
+	uint32_t txseq                        : 1;
+	uint32_t axidma                       : 1;
+	uint32_t reserved_13_31               : 19;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_reset0_set_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_reset0_set cvmx_endor_rstclk_reset0_set_t;
+
+/**
+ * cvmx_endor_rstclk_reset0_state
+ */
+union cvmx_endor_rstclk_reset0_state {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_reset0_state_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_13_31               : 19;
+	uint32_t axidma                       : 1;  /**< abc */
+	uint32_t txseq                        : 1;  /**< abc */
+	uint32_t v3genc                       : 1;  /**< abc */
+	uint32_t ifftpapr                     : 1;  /**< abc */
+	uint32_t lteenc                       : 1;  /**< abc */
+	uint32_t vdec                         : 1;  /**< abc */
+	uint32_t turbodsp                     : 1;  /**< abc */
+	uint32_t turbophy                     : 1;  /**< abc */
+	uint32_t rx1seq                       : 1;  /**< abc */
+	uint32_t dftdmap                      : 1;  /**< abc */
+	uint32_t rx0seq                       : 1;  /**< abc */
+	uint32_t rachfe                       : 1;  /**< abc */
+	uint32_t ulfe                         : 1;  /**< abc */
+#else
+	uint32_t ulfe                         : 1;
+	uint32_t rachfe                       : 1;
+	uint32_t rx0seq                       : 1;
+	uint32_t dftdmap                      : 1;
+	uint32_t rx1seq                       : 1;
+	uint32_t turbophy                     : 1;
+	uint32_t turbodsp                     : 1;
+	uint32_t vdec                         : 1;
+	uint32_t lteenc                       : 1;
+	uint32_t ifftpapr                     : 1;
+	uint32_t v3genc                       : 1;
+	uint32_t txseq                        : 1;
+	uint32_t axidma                       : 1;
+	uint32_t reserved_13_31               : 19;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_reset0_state_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_reset0_state cvmx_endor_rstclk_reset0_state_t;
+
+/**
+ * cvmx_endor_rstclk_reset1_clr
+ */
+union cvmx_endor_rstclk_reset1_clr {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_reset1_clr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_7_31                : 25;
+	uint32_t token                        : 1;  /**< abc */
+	uint32_t tile3dsp                     : 1;  /**< abc */
+	uint32_t tile2dsp                     : 1;  /**< abc */
+	uint32_t tile1dsp                     : 1;  /**< abc */
+	uint32_t rfspi                        : 1;  /**< abc */
+	uint32_t rfif_hab                     : 1;  /**< abc */
+	uint32_t rfif_rf                      : 1;  /**< abc */
+#else
+	uint32_t rfif_rf                      : 1;
+	uint32_t rfif_hab                     : 1;
+	uint32_t rfspi                        : 1;
+	uint32_t tile1dsp                     : 1;
+	uint32_t tile2dsp                     : 1;
+	uint32_t tile3dsp                     : 1;
+	uint32_t token                        : 1;
+	uint32_t reserved_7_31                : 25;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_reset1_clr_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_reset1_clr cvmx_endor_rstclk_reset1_clr_t;
+
+/**
+ * cvmx_endor_rstclk_reset1_set
+ */
+union cvmx_endor_rstclk_reset1_set {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_reset1_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_7_31                : 25;
+	uint32_t token                        : 1;  /**< abc */
+	uint32_t tile3dsp                     : 1;  /**< abc */
+	uint32_t tile2dsp                     : 1;  /**< abc */
+	uint32_t tile1dsp                     : 1;  /**< abc */
+	uint32_t rfspi                        : 1;  /**< abc */
+	uint32_t rfif_hab                     : 1;  /**< abc */
+	uint32_t rfif_rf                      : 1;  /**< abc */
+#else
+	uint32_t rfif_rf                      : 1;
+	uint32_t rfif_hab                     : 1;
+	uint32_t rfspi                        : 1;
+	uint32_t tile1dsp                     : 1;
+	uint32_t tile2dsp                     : 1;
+	uint32_t tile3dsp                     : 1;
+	uint32_t token                        : 1;
+	uint32_t reserved_7_31                : 25;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_reset1_set_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_reset1_set cvmx_endor_rstclk_reset1_set_t;
+
+/**
+ * cvmx_endor_rstclk_reset1_state
+ */
+union cvmx_endor_rstclk_reset1_state {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_reset1_state_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_7_31                : 25;
+	uint32_t token                        : 1;  /**< abc */
+	uint32_t tile3dsp                     : 1;  /**< abc */
+	uint32_t tile2dsp                     : 1;  /**< abc */
+	uint32_t tile1dsp                     : 1;  /**< abc */
+	uint32_t rfspi                        : 1;  /**< abc */
+	uint32_t rfif_hab                     : 1;  /**< abc */
+	uint32_t rfif_rf                      : 1;  /**< abc */
+#else
+	uint32_t rfif_rf                      : 1;
+	uint32_t rfif_hab                     : 1;
+	uint32_t rfspi                        : 1;
+	uint32_t tile1dsp                     : 1;
+	uint32_t tile2dsp                     : 1;
+	uint32_t tile3dsp                     : 1;
+	uint32_t token                        : 1;
+	uint32_t reserved_7_31                : 25;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_reset1_state_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_reset1_state cvmx_endor_rstclk_reset1_state_t;
+
+/**
+ * cvmx_endor_rstclk_sw_intr_clr
+ */
+union cvmx_endor_rstclk_sw_intr_clr {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_sw_intr_clr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t timer_intr                   : 8;  /**< reserved. */
+	uint32_t sw_intr                      : 24; /**< reserved. */
+#else
+	uint32_t sw_intr                      : 24;
+	uint32_t timer_intr                   : 8;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_sw_intr_clr_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_sw_intr_clr cvmx_endor_rstclk_sw_intr_clr_t;
+
+/**
+ * cvmx_endor_rstclk_sw_intr_set
+ */
+union cvmx_endor_rstclk_sw_intr_set {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_sw_intr_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t timer_intr                   : 8;  /**< reserved. */
+	uint32_t sw_intr                      : 24; /**< reserved. */
+#else
+	uint32_t sw_intr                      : 24;
+	uint32_t timer_intr                   : 8;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_sw_intr_set_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_sw_intr_set cvmx_endor_rstclk_sw_intr_set_t;
+
+/**
+ * cvmx_endor_rstclk_sw_intr_status
+ */
+union cvmx_endor_rstclk_sw_intr_status {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_sw_intr_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t timer_intr                   : 8;  /**< reserved. */
+	uint32_t sw_intr                      : 24; /**< reserved. */
+#else
+	uint32_t sw_intr                      : 24;
+	uint32_t timer_intr                   : 8;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_sw_intr_status_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_sw_intr_status cvmx_endor_rstclk_sw_intr_status_t;
+
+/**
+ * cvmx_endor_rstclk_time#_thrd
+ */
+union cvmx_endor_rstclk_timex_thrd {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_timex_thrd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t value                        : 24; /**< abc */
+#else
+	uint32_t value                        : 24;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_timex_thrd_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_timex_thrd cvmx_endor_rstclk_timex_thrd_t;
+
+/**
+ * cvmx_endor_rstclk_timer_ctl
+ */
+union cvmx_endor_rstclk_timer_ctl {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_timer_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_16_31               : 16;
+	uint32_t intr_enb                     : 8;  /**< abc */
+	uint32_t reserved_3_7                 : 5;
+	uint32_t enb                          : 1;  /**< abc */
+	uint32_t cont                         : 1;  /**< abc */
+	uint32_t clr                          : 1;  /**< abc */
+#else
+	uint32_t clr                          : 1;
+	uint32_t cont                         : 1;
+	uint32_t enb                          : 1;
+	uint32_t reserved_3_7                 : 5;
+	uint32_t intr_enb                     : 8;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_timer_ctl_s  cnf71xx;
+};
+typedef union cvmx_endor_rstclk_timer_ctl cvmx_endor_rstclk_timer_ctl_t;
+
+/**
+ * cvmx_endor_rstclk_timer_intr_clr
+ */
+union cvmx_endor_rstclk_timer_intr_clr {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_timer_intr_clr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_8_31                : 24;
+	uint32_t clr                          : 8;  /**< reserved. */
+#else
+	uint32_t clr                          : 8;
+	uint32_t reserved_8_31                : 24;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_timer_intr_clr_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_timer_intr_clr cvmx_endor_rstclk_timer_intr_clr_t;
+
+/**
+ * cvmx_endor_rstclk_timer_intr_status
+ */
+union cvmx_endor_rstclk_timer_intr_status {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_timer_intr_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_8_31                : 24;
+	uint32_t status                       : 8;  /**< reserved. */
+#else
+	uint32_t status                       : 8;
+	uint32_t reserved_8_31                : 24;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_timer_intr_status_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_timer_intr_status cvmx_endor_rstclk_timer_intr_status_t;
+
+/**
+ * cvmx_endor_rstclk_timer_max
+ */
+union cvmx_endor_rstclk_timer_max {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_timer_max_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t value                        : 32; /**< reserved. */
+#else
+	uint32_t value                        : 32;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_timer_max_s  cnf71xx;
+};
+typedef union cvmx_endor_rstclk_timer_max cvmx_endor_rstclk_timer_max_t;
+
+/**
+ * cvmx_endor_rstclk_timer_value
+ */
+union cvmx_endor_rstclk_timer_value {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_timer_value_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t value                        : 32; /**< reserved. */
+#else
+	uint32_t value                        : 32;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_timer_value_s cnf71xx;
+};
+typedef union cvmx_endor_rstclk_timer_value cvmx_endor_rstclk_timer_value_t;
+
+/**
+ * cvmx_endor_rstclk_version
+ */
+union cvmx_endor_rstclk_version {
+	uint32_t u32;
+	struct cvmx_endor_rstclk_version_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_16_31               : 16;
+	uint32_t major                        : 8;  /**< reserved. */
+	uint32_t minor                        : 8;  /**< reserved. */
+#else
+	uint32_t minor                        : 8;
+	uint32_t major                        : 8;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_endor_rstclk_version_s    cnf71xx;
+};
+typedef union cvmx_endor_rstclk_version cvmx_endor_rstclk_version_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-eoi-defs.h b/sys/contrib/octeon-sdk/cvmx-eoi-defs.h
new file mode 100644
index 0000000..a530899
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-eoi-defs.h
@@ -0,0 +1,689 @@
+/***********************license start***************
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-eoi-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon eoi.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision: 69515 $<hr>
+ *
+ */
+#ifndef __CVMX_EOI_DEFS_H__
+#define __CVMX_EOI_DEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_BIST_CTL_STA CVMX_EOI_BIST_CTL_STA_FUNC()
+static inline uint64_t CVMX_EOI_BIST_CTL_STA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_BIST_CTL_STA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000118ull);
+}
+#else
+#define CVMX_EOI_BIST_CTL_STA (CVMX_ADD_IO_SEG(0x0001180013000118ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_CTL_STA CVMX_EOI_CTL_STA_FUNC()
+static inline uint64_t CVMX_EOI_CTL_STA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_CTL_STA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000000ull);
+}
+#else
+#define CVMX_EOI_CTL_STA (CVMX_ADD_IO_SEG(0x0001180013000000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_DEF_STA0 CVMX_EOI_DEF_STA0_FUNC()
+static inline uint64_t CVMX_EOI_DEF_STA0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_DEF_STA0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000020ull);
+}
+#else
+#define CVMX_EOI_DEF_STA0 (CVMX_ADD_IO_SEG(0x0001180013000020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_DEF_STA1 CVMX_EOI_DEF_STA1_FUNC()
+static inline uint64_t CVMX_EOI_DEF_STA1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_DEF_STA1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000028ull);
+}
+#else
+#define CVMX_EOI_DEF_STA1 (CVMX_ADD_IO_SEG(0x0001180013000028ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_DEF_STA2 CVMX_EOI_DEF_STA2_FUNC()
+static inline uint64_t CVMX_EOI_DEF_STA2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_DEF_STA2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000030ull);
+}
+#else
+#define CVMX_EOI_DEF_STA2 (CVMX_ADD_IO_SEG(0x0001180013000030ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_ECC_CTL CVMX_EOI_ECC_CTL_FUNC()
+static inline uint64_t CVMX_EOI_ECC_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_ECC_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000110ull);
+}
+#else
+#define CVMX_EOI_ECC_CTL (CVMX_ADD_IO_SEG(0x0001180013000110ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_ENDOR_BISTR_CTL_STA CVMX_EOI_ENDOR_BISTR_CTL_STA_FUNC()
+static inline uint64_t CVMX_EOI_ENDOR_BISTR_CTL_STA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_ENDOR_BISTR_CTL_STA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000120ull);
+}
+#else
+#define CVMX_EOI_ENDOR_BISTR_CTL_STA (CVMX_ADD_IO_SEG(0x0001180013000120ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_ENDOR_CLK_CTL CVMX_EOI_ENDOR_CLK_CTL_FUNC()
+static inline uint64_t CVMX_EOI_ENDOR_CLK_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_ENDOR_CLK_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000038ull);
+}
+#else
+#define CVMX_EOI_ENDOR_CLK_CTL (CVMX_ADD_IO_SEG(0x0001180013000038ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_ENDOR_CTL CVMX_EOI_ENDOR_CTL_FUNC()
+static inline uint64_t CVMX_EOI_ENDOR_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_ENDOR_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000100ull);
+}
+#else
+#define CVMX_EOI_ENDOR_CTL (CVMX_ADD_IO_SEG(0x0001180013000100ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_INT_ENA CVMX_EOI_INT_ENA_FUNC()
+static inline uint64_t CVMX_EOI_INT_ENA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_INT_ENA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000010ull);
+}
+#else
+#define CVMX_EOI_INT_ENA (CVMX_ADD_IO_SEG(0x0001180013000010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_INT_STA CVMX_EOI_INT_STA_FUNC()
+static inline uint64_t CVMX_EOI_INT_STA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_INT_STA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000008ull);
+}
+#else
+#define CVMX_EOI_INT_STA (CVMX_ADD_IO_SEG(0x0001180013000008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_IO_DRV CVMX_EOI_IO_DRV_FUNC()
+static inline uint64_t CVMX_EOI_IO_DRV_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_IO_DRV not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000018ull);
+}
+#else
+#define CVMX_EOI_IO_DRV (CVMX_ADD_IO_SEG(0x0001180013000018ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_THROTTLE_CTL CVMX_EOI_THROTTLE_CTL_FUNC()
+static inline uint64_t CVMX_EOI_THROTTLE_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_THROTTLE_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000108ull);
+}
+#else
+#define CVMX_EOI_THROTTLE_CTL (CVMX_ADD_IO_SEG(0x0001180013000108ull))
+#endif
+
+/**
+ * cvmx_eoi_bist_ctl_sta
+ *
+ * EOI_BIST_CTL_STA =  EOI BIST Status Register
+ *
+ * Description:
+ *   This register control EOI memory BIST and contains the bist result of EOI memories.
+ */
+union cvmx_eoi_bist_ctl_sta {
+	uint64_t u64;
+	struct cvmx_eoi_bist_ctl_sta_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_18_63               : 46;
+	uint64_t clear_bist                   : 1;  /**< Clear BIST on the HCLK memories */
+	uint64_t start_bist                   : 1;  /**< Starts BIST on the HCLK memories during 0-to-1
+                                                         transition. */
+	uint64_t reserved_3_15                : 13;
+	uint64_t stdf                         : 1;  /**< STDF Bist Status. */
+	uint64_t ppaf                         : 1;  /**< PPAF Bist Status. */
+	uint64_t lddf                         : 1;  /**< LDDF Bist Status. */
+#else
+	uint64_t lddf                         : 1;
+	uint64_t ppaf                         : 1;
+	uint64_t stdf                         : 1;
+	uint64_t reserved_3_15                : 13;
+	uint64_t start_bist                   : 1;
+	uint64_t clear_bist                   : 1;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_eoi_bist_ctl_sta_s        cnf71xx;
+};
+typedef union cvmx_eoi_bist_ctl_sta cvmx_eoi_bist_ctl_sta_t;
+
+/**
+ * cvmx_eoi_ctl_sta
+ *
+ * EOI_CTL_STA = EOI Configure Control Reigster
+ * This register configures EOI.
+ */
+union cvmx_eoi_ctl_sta {
+	uint64_t u64;
+	struct cvmx_eoi_ctl_sta_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_13_63               : 51;
+	uint64_t ppaf_wm                      : 5;  /**< Number of entries when PP Access FIFO will assert
+                                                         full (back pressure) */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t busy                         : 1;  /**< 1: EOI is busy; 0: EOI is idle */
+	uint64_t rwam                         : 2;  /**< Rread Write Aribitration Mode:
+                                                         - 10: Reads  have higher priority
+                                                         - 01: Writes have higher priority
+                                                         00,11: Round-Robin between Reads and Writes */
+	uint64_t ena                          : 1;  /**< When reset, all the inbound DMA accesses will be
+                                                         drop and all the outbound read response and write
+                                                         commits will be drop. It must be set to 1'b1 for
+                                                         normal access. */
+	uint64_t reset                        : 1;  /**< EOI block Software Reset. */
+#else
+	uint64_t reset                        : 1;
+	uint64_t ena                          : 1;
+	uint64_t rwam                         : 2;
+	uint64_t busy                         : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t ppaf_wm                      : 5;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_eoi_ctl_sta_s             cnf71xx;
+};
+typedef union cvmx_eoi_ctl_sta cvmx_eoi_ctl_sta_t;
+
+/**
+ * cvmx_eoi_def_sta0
+ *
+ * Note: Working settings tabulated for each corner.
+ * ================================
+ * Corner pctl    nctl
+ * ===============================
+ *     1   26      22
+ *     2   30      28
+ *     3   32      31
+ *     4   23      19
+ *     5   27      24
+ *     6   29      27
+ *     7   21      17
+ *     8   25      22
+ *     9   27      24
+ *    10   29      24
+ *    11   34      31
+ *    12   36      35
+ *    13   26      21
+ *    14   31      27
+ *    15   33      30
+ *    16   23      18
+ *    17   28      24
+ *    18   30      27
+ *    19   21      17
+ *    20   27      25
+ *    21   29      28
+ *    22   21      17
+ *    23   25      22
+ *    24   27      25
+ *    25   19      15
+ *    26   23      20
+ *    27   25      22
+ *    28   24      24
+ *    29   28      31
+ *    30   30      35
+ *    31   21      21
+ *    32   25      27
+ *    33   27      30
+ *    34   19      18
+ *    35   23      24
+ *    36   25      27
+ *    37   29      19
+ *    38   33      25
+ *    39   36      28
+ *    40   25      17
+ *    41   30      22
+ *    42   32      25
+ *    43   23      15
+ *    44   27      20
+ *    45   29      22
+ * ===============================
+ *
+ *                   EOI_DEF_STA0 = EOI Defect Status Register 0
+ *
+ *  Register to hold repairout 0/1/2
+ */
+union cvmx_eoi_def_sta0 {
+	uint64_t u64;
+	struct cvmx_eoi_def_sta0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t rout2                        : 18; /**< Repairout2 */
+	uint64_t rout1                        : 18; /**< Repairout1 */
+	uint64_t rout0                        : 18; /**< Repairout0 */
+#else
+	uint64_t rout0                        : 18;
+	uint64_t rout1                        : 18;
+	uint64_t rout2                        : 18;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_eoi_def_sta0_s            cnf71xx;
+};
+typedef union cvmx_eoi_def_sta0 cvmx_eoi_def_sta0_t;
+
+/**
+ * cvmx_eoi_def_sta1
+ *
+ * EOI_DEF_STA1 = EOI Defect Status Register 1
+ *
+ * Register to hold repairout 3/4/5
+ */
+union cvmx_eoi_def_sta1 {
+	uint64_t u64;
+	struct cvmx_eoi_def_sta1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t rout5                        : 18; /**< Repairout5 */
+	uint64_t rout4                        : 18; /**< Repairout4 */
+	uint64_t rout3                        : 18; /**< Repairout3 */
+#else
+	uint64_t rout3                        : 18;
+	uint64_t rout4                        : 18;
+	uint64_t rout5                        : 18;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_eoi_def_sta1_s            cnf71xx;
+};
+typedef union cvmx_eoi_def_sta1 cvmx_eoi_def_sta1_t;
+
+/**
+ * cvmx_eoi_def_sta2
+ *
+ * EOI_DEF_STA2 = EOI Defect Status Register 2
+ *
+ * Register to hold repairout 6 and toomanydefects.
+ */
+union cvmx_eoi_def_sta2 {
+	uint64_t u64;
+	struct cvmx_eoi_def_sta2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_25_63               : 39;
+	uint64_t toomany                      : 1;  /**< Toomanydefects */
+	uint64_t reserved_18_23               : 6;
+	uint64_t rout6                        : 18; /**< Repairout6 */
+#else
+	uint64_t rout6                        : 18;
+	uint64_t reserved_18_23               : 6;
+	uint64_t toomany                      : 1;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_eoi_def_sta2_s            cnf71xx;
+};
+typedef union cvmx_eoi_def_sta2 cvmx_eoi_def_sta2_t;
+
+/**
+ * cvmx_eoi_ecc_ctl
+ *
+ * EOI_ECC_CTL =  EOI ECC Control Register
+ *
+ * Description:
+ *   This register enables ECC for each individual internal memory that requires ECC. For debug purpose, it can also
+ *   control 1 or 2 bits be flipped in the ECC data.
+ */
+union cvmx_eoi_ecc_ctl {
+	uint64_t u64;
+	struct cvmx_eoi_ecc_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_3_63                : 61;
+	uint64_t rben                         : 1;  /**< 1: ECC Enable for read buffer
+                                                         - 0: ECC Enable for instruction buffer */
+	uint64_t rbsf                         : 2;  /**< read buffer ecc syndrome flip
+                                                         2'b00       : No Error Generation
+                                                         2'b10, 2'b01: Flip 1 bit
+                                                         2'b11       : Flip 2 bits */
+#else
+	uint64_t rbsf                         : 2;
+	uint64_t rben                         : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_eoi_ecc_ctl_s             cnf71xx;
+};
+typedef union cvmx_eoi_ecc_ctl cvmx_eoi_ecc_ctl_t;
+
+/**
+ * cvmx_eoi_endor_bistr_ctl_sta
+ *
+ * EOI_ENDOR_BISTR_CTL_STA =  EOI BIST/BISR Control Status Register
+ *
+ * Description:
+ *   This register the bist result of EOI memories.
+ */
+union cvmx_eoi_endor_bistr_ctl_sta {
+	uint64_t u64;
+	struct cvmx_eoi_endor_bistr_ctl_sta_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t bisr_done                    : 1;  /**< Endor DSP Memroy Bisr Done Status: 1 - done;
+                                                         0 - Not done. */
+	uint64_t failed                       : 1;  /**< Bist/Bisr Status: 1 - failed; 0 - Not failed. */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t bisr_hr                      : 1;  /**< BISR Hardrepair */
+	uint64_t bisr_dir                     : 1;  /**< BISR Direction: 0 = input repair packets;
+                                                         1 = output defect packets. */
+	uint64_t start_bist                   : 1;  /**< Start Bist */
+#else
+	uint64_t start_bist                   : 1;
+	uint64_t bisr_dir                     : 1;
+	uint64_t bisr_hr                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t failed                       : 1;
+	uint64_t bisr_done                    : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_eoi_endor_bistr_ctl_sta_s cnf71xx;
+};
+typedef union cvmx_eoi_endor_bistr_ctl_sta cvmx_eoi_endor_bistr_ctl_sta_t;
+
+/**
+ * cvmx_eoi_endor_clk_ctl
+ *
+ * EOI_ENDOR_CLK_CTL = EOI Endor Clock Control
+ *
+ * Register control the generation of Endor DSP and HAB clocks.
+ */
+union cvmx_eoi_endor_clk_ctl {
+	uint64_t u64;
+	struct cvmx_eoi_endor_clk_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_28_63               : 36;
+	uint64_t habclk_sel                   : 1;  /**< HAB CLK select
+                                                         0x0: HAB CLK select from PHY_PLL output from HAB PS
+                                                         0x1: HAB CLK select from DDR_PLL output from HAB PS */
+	uint64_t reserved_26_26               : 1;
+	uint64_t dsp_div_reset                : 1;  /**< DSP postscalar divider reset */
+	uint64_t dsp_ps_en                    : 3;  /**< DSP postscalar divide ratio
+                                                         Determines the DSP CK speed.
+                                                         0x0 : Divide DSP PLL output by 1
+                                                         0x1 : Divide DSP PLL output by 2
+                                                         0x2 : Divide DSP PLL output by 3
+                                                         0x3 : Divide DSP PLL output by 4
+                                                         0x4 : Divide DSP PLL output by 6
+                                                         0x5 : Divide DSP PLL output by 8
+                                                         0x6 : Divide DSP PLL output by 12
+                                                         0x7 : Divide DSP PLL output by 12
+                                                         DSP_PS_EN is not used when DSP_DIV_RESET = 1 */
+	uint64_t hab_div_reset                : 1;  /**< HAB postscalar divider reset */
+	uint64_t hab_ps_en                    : 3;  /**< HAB postscalar divide ratio
+                                                         Determines the LMC CK speed.
+                                                         0x0 : Divide HAB PLL output by 1
+                                                         0x1 : Divide HAB PLL output by 2
+                                                         0x2 : Divide HAB PLL output by 3
+                                                         0x3 : Divide HAB PLL output by 4
+                                                         0x4 : Divide HAB PLL output by 6
+                                                         0x5 : Divide HAB PLL output by 8
+                                                         0x6 : Divide HAB PLL output by 12
+                                                         0x7 : Divide HAB PLL output by 12
+                                                         HAB_PS_EN is not used when HAB_DIV_RESET = 1 */
+	uint64_t diffamp                      : 4;  /**< PLL diffamp input transconductance */
+	uint64_t cps                          : 3;  /**< PLL charge-pump current */
+	uint64_t cpb                          : 3;  /**< PLL charge-pump current */
+	uint64_t reset_n                      : 1;  /**< PLL reset */
+	uint64_t clkf                         : 7;  /**< Multiply reference by CLKF
+                                                         32 <= CLKF <= 64
+                                                         PHY PLL frequency = 50 * CLKF
+                                                         min = 1.6 GHz, max = 3.2 GHz */
+#else
+	uint64_t clkf                         : 7;
+	uint64_t reset_n                      : 1;
+	uint64_t cpb                          : 3;
+	uint64_t cps                          : 3;
+	uint64_t diffamp                      : 4;
+	uint64_t hab_ps_en                    : 3;
+	uint64_t hab_div_reset                : 1;
+	uint64_t dsp_ps_en                    : 3;
+	uint64_t dsp_div_reset                : 1;
+	uint64_t reserved_26_26               : 1;
+	uint64_t habclk_sel                   : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} s;
+	struct cvmx_eoi_endor_clk_ctl_s       cnf71xx;
+};
+typedef union cvmx_eoi_endor_clk_ctl cvmx_eoi_endor_clk_ctl_t;
+
+/**
+ * cvmx_eoi_endor_ctl
+ *
+ * EOI_ENDOR_CTL_STA = Endor Control Reigster
+ * This register controls Endor phy reset and access.
+ */
+union cvmx_eoi_endor_ctl {
+	uint64_t u64;
+	struct cvmx_eoi_endor_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_12_63               : 52;
+	uint64_t r_emod                       : 2;  /**< Endian format for data read from the L2C.
+                                                         IN:    A-B-C-D-E-F-G-H
+                                                         OUT0:  A-B-C-D-E-F-G-H
+                                                         OUT1:  H-G-F-E-D-C-B-A
+                                                         OUT2:  D-C-B-A-H-G-F-E
+                                                         OUT3:  E-F-G-H-A-B-C-D */
+	uint64_t w_emod                       : 2;  /**< Endian format for data written the L2C.
+                                                         IN:    A-B-C-D-E-F-G-H
+                                                         OUT0:  A-B-C-D-E-F-G-H
+                                                         OUT1:  H-G-F-E-D-C-B-A
+                                                         OUT2:  D-C-B-A-H-G-F-E
+                                                         OUT3:  E-F-G-H-A-B-C-D */
+	uint64_t inv_rsl_ra2                  : 1;  /**< Invert RSL CSR read  address bit 2. */
+	uint64_t inv_rsl_wa2                  : 1;  /**< Invert RSL CSR write address bit 2. */
+	uint64_t inv_pp_ra2                   : 1;  /**< Invert PP CSR read  address bit 2. */
+	uint64_t inv_pp_wa2                   : 1;  /**< Invert PP CSR write address bit 2. */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t reset                        : 1;  /**< Endor block software reset. After hardware reset,
+                                                         this bit is set to 1'b1 which put Endor into reset
+                                                         state. Software must clear this bit to use Endor. */
+#else
+	uint64_t reset                        : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t inv_pp_wa2                   : 1;
+	uint64_t inv_pp_ra2                   : 1;
+	uint64_t inv_rsl_wa2                  : 1;
+	uint64_t inv_rsl_ra2                  : 1;
+	uint64_t w_emod                       : 2;
+	uint64_t r_emod                       : 2;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_eoi_endor_ctl_s           cnf71xx;
+};
+typedef union cvmx_eoi_endor_ctl cvmx_eoi_endor_ctl_t;
+
+/**
+ * cvmx_eoi_int_ena
+ *
+ * EOI_INT_ENA = EOI Interrupt Enable Register
+ *
+ * Register to enable individual interrupt source in corresponding to EOI_INT_STA
+ */
+union cvmx_eoi_int_ena {
+	uint64_t u64;
+	struct cvmx_eoi_int_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_2_63                : 62;
+	uint64_t rb_dbe                       : 1;  /**< Read Buffer ECC DBE */
+	uint64_t rb_sbe                       : 1;  /**< Read Buffer ECC SBE */
+#else
+	uint64_t rb_sbe                       : 1;
+	uint64_t rb_dbe                       : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_eoi_int_ena_s             cnf71xx;
+};
+typedef union cvmx_eoi_int_ena cvmx_eoi_int_ena_t;
+
+/**
+ * cvmx_eoi_int_sta
+ *
+ * EOI_INT_STA = EOI Interrupt Status Register
+ *
+ * Summary of different bits of RSL interrupt status.
+ */
+union cvmx_eoi_int_sta {
+	uint64_t u64;
+	struct cvmx_eoi_int_sta_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_2_63                : 62;
+	uint64_t rb_dbe                       : 1;  /**< Read Buffer ECC DBE */
+	uint64_t rb_sbe                       : 1;  /**< Read Buffer ECC SBE */
+#else
+	uint64_t rb_sbe                       : 1;
+	uint64_t rb_dbe                       : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_eoi_int_sta_s             cnf71xx;
+};
+typedef union cvmx_eoi_int_sta cvmx_eoi_int_sta_t;
+
+/**
+ * cvmx_eoi_io_drv
+ *
+ * EOI_IO_DRV = EOI Endor IO Drive Control
+ *
+ * Register to control Endor Phy IOs
+ */
+union cvmx_eoi_io_drv {
+	uint64_t u64;
+	struct cvmx_eoi_io_drv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_24_63               : 40;
+	uint64_t rfif_p                       : 6;  /**< RFIF output driver P-Mos control */
+	uint64_t rfif_n                       : 6;  /**< RFIF output driver N-Mos control */
+	uint64_t gpo_p                        : 6;  /**< GPO  output driver P-Mos control */
+	uint64_t gpo_n                        : 6;  /**< GPO  output driver N-Mos control */
+#else
+	uint64_t gpo_n                        : 6;
+	uint64_t gpo_p                        : 6;
+	uint64_t rfif_n                       : 6;
+	uint64_t rfif_p                       : 6;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_eoi_io_drv_s              cnf71xx;
+};
+typedef union cvmx_eoi_io_drv cvmx_eoi_io_drv_t;
+
+/**
+ * cvmx_eoi_throttle_ctl
+ *
+ * EOI_THROTTLE_CTL = EOI THROTTLE Control Reigster
+ * This register controls number of outstanding EOI loads to L2C . It is in phy_clock domain.
+ */
+union cvmx_eoi_throttle_ctl {
+	uint64_t u64;
+	struct cvmx_eoi_throttle_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_21_63               : 43;
+	uint64_t std                          : 5;  /**< Number of outstanding store data accepted by EOI on
+                                                         AXI before backpressure ADMA. The value must be from
+                                                         from 16 to 31 inclusively. */
+	uint64_t reserved_10_15               : 6;
+	uint64_t stc                          : 2;  /**< Number of outstanding L2C store command accepted by
+                                                         EOI on AXI before backpressure ADMA. The value must be
+                                                         from 1 to 3 inclusively. */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t ldc                          : 4;  /**< Number of outstanding L2C loads. The value must be
+                                                         from 1 to 8 inclusively. */
+#else
+	uint64_t ldc                          : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t stc                          : 2;
+	uint64_t reserved_10_15               : 6;
+	uint64_t std                          : 5;
+	uint64_t reserved_21_63               : 43;
+#endif
+	} s;
+	struct cvmx_eoi_throttle_ctl_s        cnf71xx;
+};
+typedef union cvmx_eoi_throttle_ctl cvmx_eoi_throttle_ctl_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-error-custom.c b/sys/contrib/octeon-sdk/cvmx-error-custom.c
index 3aeaa0d..64768a6 100644
--- a/sys/contrib/octeon-sdk/cvmx-error-custom.c
+++ b/sys/contrib/octeon-sdk/cvmx-error-custom.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -58,6 +58,7 @@
 #include <asm/octeon/cvmx-gmxx-defs.h>
 #include <asm/octeon/cvmx-lmcx-defs.h>
 #include <asm/octeon/cvmx-pemx-defs.h>
+#include <asm/octeon/cvmx-sriox-defs.h>
 #define PRINT_ERROR(format, ...) cvmx_safe_printf("ERROR " format, ##__VA_ARGS__)
 #else
 #include "cvmx.h"
@@ -82,6 +83,21 @@ static int __cvmx_error_handle_gmxx_rxx_int_reg(const struct cvmx_error_info *in
 {
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
     int ipd_port = info->group_index;
+    switch(ipd_port)
+    {
+        case 0x800:
+            ipd_port = 0x840;
+            break;
+        case 0xa00:
+            ipd_port = 0xa40;
+            break;
+        case 0xb00:
+            ipd_port = 0xb40;
+            break;
+        case 0xc00:
+            ipd_port = 0xc40;
+            break;
+    }
     cvmx_helper_link_autoconf(ipd_port);
 #endif
     cvmx_write_csr(info->status_addr, info->status_mask);
@@ -140,6 +156,136 @@ static int __cvmx_error_handle_npei_int_sum_c1_ldwn(const struct cvmx_error_info
     return 1;
 }
 
+#define DECODE_FAILING_ADDRESS
+//#define DECODE_FAILING_BIT
+
+#ifdef DECODE_FAILING_BIT
+#define _Db(x) (x)              /* Data Bit */
+#define _Ec(x) (0x100+x)        /* ECC Bit */
+#define _Ad(x) (0x200+x)        /* Address Bit */
+#define _Bu(x) (0x400+x)        /* Burst */
+#define _Un()  (-1)             /* Unused */
+/* Use ECC Code as index to lookup corrected bit */
+const static short lmc_syndrome_bits[256] = {
+    /*        __ 0 __  __ 1 __  __ 2 __  __ 3 __  __ 4 __  __ 5 __  __ 6 __  __ 7 __  __ 8 __  __ 9 __  __ A __  __ B __  __ C __  __ D __  __ E __  __ F __ */
+    /* 00: */ _Un(  ), _Ec( 0), _Ec( 1), _Un(  ), _Ec( 2), _Un(  ), _Un(  ), _Un(  ), _Ec( 3), _Un(  ), _Un(  ), _Db(17), _Un(  ), _Un(  ), _Db(16), _Un(  ),    
+    /* 10: */ _Ec( 4), _Un(  ), _Un(  ), _Db(18), _Un(  ), _Db(19), _Db(20), _Un(  ), _Un(  ), _Db(21), _Db(22), _Un(  ), _Db(23), _Un(  ), _Un(  ), _Un(  ),    
+    /* 20: */ _Ec( 5), _Un(  ), _Un(  ), _Db( 8), _Un(  ), _Db( 9), _Db(10), _Un(  ), _Un(  ), _Db(11), _Db(12), _Un(  ), _Db(13), _Un(  ), _Un(  ), _Un(  ),    
+    /* 30: */ _Un(  ), _Db(14), _Un(  ), _Un(  ), _Db(15), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Ad(34), _Un(  ),    
+    /* 40: */ _Ec( 6), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Ad( 7), _Ad( 8), _Un(  ), _Un(  ), _Ad( 9), _Db(33), _Un(  ), _Ad(10), _Un(  ), _Un(  ), _Db(32),    
+    /* 50: */ _Un(  ), _Ad(11), _Db(34), _Un(  ), _Db(35), _Un(  ), _Un(  ), _Db(36), _Db(37), _Un(  ), _Un(  ), _Db(38), _Un(  ), _Db(39), _Ad(12), _Un(  ),    
+    /* 60: */ _Un(  ), _Ad(13), _Db(56), _Un(  ), _Db(57), _Un(  ), _Un(  ), _Db(58), _Db(59), _Un(  ), _Un(  ), _Db(60), _Un(  ), _Db(61), _Ad(14), _Un(  ),    
+    /* 70: */ _Db(62), _Un(  ), _Un(  ), _Ad(15), _Un(  ), _Db(63), _Ad(16), _Un(  ), _Un(  ), _Ad(17), _Ad(18), _Un(  ), _Ad(19), _Un(  ), _Ad(20), _Un(  ),    
+    /* 80: */ _Ec( 7), _Un(  ), _Un(  ), _Ad(21), _Un(  ), _Ad(22), _Ad(23), _Un(  ), _Un(  ), _Ad(24), _Db(49), _Un(  ), _Ad(25), _Un(  ), _Un(  ), _Db(48),    
+    /* 90: */ _Un(  ), _Ad(26), _Db(50), _Un(  ), _Db(51), _Un(  ), _Un(  ), _Db(52), _Db(53), _Un(  ), _Un(  ), _Db(54), _Un(  ), _Db(55), _Ad(27), _Un(  ),    
+    /* A0: */ _Un(  ), _Ad(28), _Db(40), _Un(  ), _Db(41), _Un(  ), _Un(  ), _Db(42), _Db(43), _Un(  ), _Un(  ), _Db(44), _Un(  ), _Db(45), _Ad(29), _Un(  ),    
+    /* B0: */ _Db(46), _Un(  ), _Un(  ), _Ad(30), _Un(  ), _Db(47), _Ad(31), _Un(  ), _Un(  ), _Ad(32), _Ad(33), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ),    
+    /* C0: */ _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Db( 1), _Un(  ), _Un(  ), _Db( 0), _Un(  ),    
+    /* D0: */ _Un(  ), _Un(  ), _Un(  ), _Db( 2), _Un(  ), _Db( 3), _Db( 4), _Un(  ), _Un(  ), _Db( 5), _Db( 6), _Un(  ), _Db( 7), _Un(  ), _Un(  ), _Un(  ),    
+    /* E0: */ _Un(  ), _Un(  ), _Un(  ), _Db(24), _Un(  ), _Db(25), _Db(26), _Un(  ), _Un(  ), _Db(27), _Db(28), _Un(  ), _Db(29), _Un(  ), _Un(  ), _Un(  ),    
+    /* F0: */ _Un(  ), _Db(30), _Un(  ), _Un(  ), _Db(31), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  )
+};
+#endif
+
+/**
+ * @INTERNAL
+ * This error bit handler clears the status and prints failure infomation.
+ *
+ * @param info   Error register to check
+ *
+ * @return
+ */
+static int __cvmx_cn6xxx_lmc_ecc_error_display(const cvmx_error_info_t *info)
+{
+#ifdef DECODE_FAILING_ADDRESS
+    cvmx_lmcx_config_t lmc_config;
+    uint64_t fadr_physical, fadr_data;
+#endif
+
+    int ddr_controller = info->group_index;
+    cvmx_lmcx_int_t lmc_int;
+    cvmx_lmcx_fadr_t fadr;
+    cvmx_lmcx_ecc_synd_t ecc_synd;
+    int sec_err;
+    int ded_err;
+    int syndrome = -1;
+    int phase;
+
+    lmc_int.u64 = cvmx_read_csr(CVMX_LMCX_INT(ddr_controller));
+    fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(ddr_controller));
+    ecc_synd.u64 = cvmx_read_csr(CVMX_LMCX_ECC_SYND(ddr_controller));
+    /* This assumes that all bits in the status register are RO or R/W1C */
+    cvmx_write_csr(info->status_addr, info->status_mask);
+
+#ifdef DECODE_FAILING_ADDRESS
+    lmc_config.u64 = cvmx_read_csr(CVMX_LMCX_CONFIG(ddr_controller));
+#endif
+
+    sec_err = lmc_int.s.sec_err;
+    ded_err = lmc_int.s.ded_err;
+
+    phase = ded_err ? ded_err : sec_err; /* Double bit errors take precedence. */
+
+    switch (phase) {
+    case 1:
+        syndrome = ecc_synd.cn63xx.mrdsyn0;
+        break;
+    case 2:
+        syndrome = ecc_synd.cn63xx.mrdsyn1;
+        break;
+    case 4:
+        syndrome = ecc_synd.cn63xx.mrdsyn2;
+        break;
+    case 8:
+        syndrome = ecc_synd.cn63xx.mrdsyn3;
+        break;
+    }
+
+#ifdef DECODE_FAILING_ADDRESS
+    fadr_physical  = (uint64_t)fadr.cn63xx.fdimm      << (lmc_config.s.pbank_lsb + 28);
+    fadr_physical |= (uint64_t)fadr.cn63xx.frow       << (lmc_config.s.row_lsb + 14);
+    fadr_physical |= (uint64_t)fadr.cn63xx.fbank      << 7;
+    fadr_physical |= (uint64_t)(fadr.cn63xx.fcol&0xf) << 3;
+    fadr_physical |= (uint64_t)(fadr.cn63xx.fcol>>4)  << 10;
+
+    fadr_data = *(uint64_t*)cvmx_phys_to_ptr(fadr_physical);
+#endif
+
+    PRINT_ERROR("LMC%d ECC: sec_err:%d ded_err:%d\n"
+                "LMC%d ECC:\tFailing dimm:   %u\n"
+                "LMC%d ECC:\tFailing rank:   %u\n"
+                "LMC%d ECC:\tFailing bank:   %u\n"
+                "LMC%d ECC:\tFailing row:    0x%x\n"
+                "LMC%d ECC:\tFailing column: 0x%x\n"
+                "LMC%d ECC:\tsyndrome: 0x%x"
+#ifdef DECODE_FAILING_BIT
+                ", bit: %d"
+#endif
+                "\n"
+#ifdef DECODE_FAILING_ADDRESS
+                "Failing  Address: 0x%016llx, Data: 0x%016llx\n"
+#endif
+                ,               /* Comma */
+                ddr_controller, sec_err, ded_err,
+                ddr_controller, fadr.cn63xx.fdimm,
+                ddr_controller, fadr.cn63xx.fbunk,
+                ddr_controller, fadr.cn63xx.fbank,
+                ddr_controller, fadr.cn63xx.frow,
+                ddr_controller, fadr.cn63xx.fcol,
+                ddr_controller, syndrome
+#ifdef DECODE_FAILING_BIT
+                ,               /* Comma */
+                lmc_syndrome_bits[syndrome]
+#endif
+#ifdef DECODE_FAILING_ADDRESS
+                ,               /* Comma */
+                (unsigned long long) fadr_physical, (unsigned long long) fadr_data
+#endif
+                );
+
+    return 1;
+}
+
 /**
  * @INTERNAL
  * Some errors require more complicated error handing functions than the
@@ -150,25 +296,60 @@ static int __cvmx_error_handle_npei_int_sum_c1_ldwn(const struct cvmx_error_info
  */
 int __cvmx_error_custom_initialize(void)
 {
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
     {
-        cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
-                            CVMX_GMXX_RXX_INT_REG(0,0), 1ull<<21 /* rem_fault */,
-                            __cvmx_error_handle_gmxx_rxx_int_reg, 0, NULL, NULL);
-        cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
-                            CVMX_GMXX_RXX_INT_REG(0,0), 1ull<<20 /* loc_fault */,
-                            __cvmx_error_handle_gmxx_rxx_int_reg, 0, NULL, NULL);
+        int lmc;
+        for (lmc = 0; lmc < CVMX_L2C_TADS; lmc++)
+        {
+            if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+            {
+                cvmx_lmcx_dll_ctl2_t ctl;
+                ctl.u64 = cvmx_read_csr(CVMX_LMCX_DLL_CTL2(lmc));
+                if (ctl.s.intf_en == 0)
+                    continue;
+            }
+            cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
+                    CVMX_LMCX_INT(lmc), 0xfull<<1 /* sec_err */,
+                    __cvmx_cn6xxx_lmc_ecc_error_display, 0, NULL, NULL);
+            cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
+                    CVMX_LMCX_INT(lmc), 0xfull<<5 /* ded_err */,
+                    __cvmx_cn6xxx_lmc_ecc_error_display, 0, NULL, NULL);
+            if (!OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+	    {
+	        int i;
+
+	        for (i = 0; i < 6; i++)
+                    cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
+                            CVMX_L2C_TADX_INT(lmc), (1ull << i),
+                            __cvmx_error_handle_63XX_l2_ecc, 0, NULL, NULL);
+            }
+	}
     }
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX)
+        || OCTEON_IS_MODEL(OCTEON_CN56XX)
+        || OCTEON_IS_MODEL(OCTEON_CN6XXX)
+        || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
     {
-        cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
-                            CVMX_GMXX_RXX_INT_REG(0,1), 1ull<<21 /* rem_fault */,
+        int i;
+
+        /* Install special handler for all the interfaces, these are
+           specific to XAUI interface */
+        for (i = 0; i < CVMX_HELPER_MAX_GMX; i++)
+        {
+            if ((OCTEON_IS_MODEL(OCTEON_CN63XX) 
+                 || OCTEON_IS_MODEL(OCTEON_CN52XX)
+                 || OCTEON_IS_MODEL(OCTEON_CNF71XX))
+                && i == 1)
+                continue;
+            cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
+                            CVMX_GMXX_RXX_INT_REG(0,i), 1ull<<21 /* rem_fault */,
                             __cvmx_error_handle_gmxx_rxx_int_reg, 0, NULL, NULL);
-        cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
-                            CVMX_GMXX_RXX_INT_REG(0,1), 1ull<<20 /* loc_fault */,
+            cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
+                            CVMX_GMXX_RXX_INT_REG(0,i), 1ull<<20 /* loc_fault */,
                             __cvmx_error_handle_gmxx_rxx_int_reg, 0, NULL, NULL);
+        }
     }
-    if (octeon_has_feature(OCTEON_FEATURE_NPEI))
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
     {
         cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
                             CVMX_PEXP_NPEI_INT_SUM, 1ull<<59 /* c0_ldwn */,
@@ -191,6 +372,14 @@ int __cvmx_error_custom_initialize(void)
         cvmx_error_disable(CVMX_ERROR_REGISTER_IO64, CVMX_PEMX_INT_SUM(1),
             1ull<<13);
     }
+    /* According to the workaround for errata SRIO-15282, clearing
+       SRIOx_INT_ENABLE[MAC_BUF]. */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0) && OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_1))
+    {
+        cvmx_error_disable(CVMX_ERROR_REGISTER_IO64, CVMX_SRIOX_INT_ENABLE(0), 1ull<<22);
+        cvmx_error_disable(CVMX_ERROR_REGISTER_IO64, CVMX_SRIOX_INT_ENABLE(1), 1ull<<22);
+    }
+
     return 0;
 }
 
@@ -622,3 +811,79 @@ int __cvmx_error_handle_pow_ecc_err_sbe(const struct cvmx_error_info *info)
 }
 
 
+/**
+ * @INTERNAL
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_63XX_l2_ecc(const struct cvmx_error_info *info)
+{
+    cvmx_l2c_err_tdtx_t l2c_err_tdt;
+    cvmx_l2c_err_ttgx_t l2c_err_ttg;
+    cvmx_l2c_err_vbfx_t l2c_err_vbf;
+    cvmx_l2c_tadx_int_t tadx_int;
+    tadx_int.u64 = cvmx_read_csr(CVMX_L2C_TADX_INT(0));
+    l2c_err_tdt.u64 = cvmx_read_csr(CVMX_L2C_ERR_TDTX(0));
+    l2c_err_ttg.u64 = cvmx_read_csr(CVMX_L2C_ERR_TTGX(0));
+    l2c_err_vbf.u64 = cvmx_read_csr(CVMX_L2C_ERR_VBFX(0));
+    cvmx_write_csr(CVMX_L2C_TADX_INT(0), tadx_int.u64);
+
+    if (tadx_int.cn63xx.l2ddbe ||  tadx_int.cn63xx.l2dsbe)
+    {
+	/* L2 Data error */
+
+
+	if (tadx_int.cn63xx.l2dsbe)
+        {
+            /* l2c_err_tdt.cn63xx.wayidx formated same as CACHE instruction arg */
+            CVMX_CACHE_WBIL2I((l2c_err_tdt.u64 & 0x1fff80) | (1ULL << 63), 0);
+            CVMX_SYNC;
+            PRINT_ERROR("L2C_TADX_INT(0)[L2DSBE]: Data Single-Bit Error\n");
+        }
+        if (tadx_int.cn63xx.l2ddbe)
+        {
+            /* TODO - fatal error, for now, flush so error cleared..... */
+            CVMX_CACHE_WBIL2I((l2c_err_tdt.u64 & 0x1fff80) | (1ULL << 63), 0);
+            CVMX_SYNC;
+	    PRINT_ERROR("L2C_TADX_INT(0)[L2DDBE]: Data Double-Bit Error\n");
+        }
+	PRINT_ERROR("CVMX_L2C_ERR_TDT: 0x%llx\n", (unsigned long long)l2c_err_tdt.u64);
+    }
+    if (tadx_int.cn63xx.tagdbe || tadx_int.cn63xx.tagsbe)
+    {
+	/* L2 Tag error */
+	if (tadx_int.cn63xx.tagsbe)
+        {
+            CVMX_CACHE_WBIL2I((l2c_err_ttg.u64 & 0x1fff80) | (1ULL << 63), 0);
+            CVMX_SYNC;
+	    PRINT_ERROR("L2C_TADX_INT(0)[TAGSBE]: Tag Single-Bit Error\n");
+        }
+	if (tadx_int.cn63xx.tagdbe)
+        {
+            /* TODO - fatal error, for now, flush so error cleared..... */
+            CVMX_CACHE_WBIL2I((l2c_err_ttg.u64 & 0x1fff80) | (1ULL << 63), 0);
+            CVMX_SYNC;
+	    PRINT_ERROR("L2C_TADX_INT(0)[TAGDBE]: Tag Double-Bit Error\n");
+        }
+	PRINT_ERROR("CVMX_L2C_ERR_TTG: 0x%llx\n", (unsigned long long)l2c_err_ttg.u64);
+    }
+    if (tadx_int.cn63xx.vbfdbe || tadx_int.cn63xx.vbfsbe)
+    {
+	/* L2 Victim buffer error */
+	if (tadx_int.cn63xx.vbfsbe)
+        {
+            /* No action here, hardware fixed up on write to DRAM */
+	    PRINT_ERROR("L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error\n");
+        }
+	if (tadx_int.cn63xx.vbfdbe)
+        {
+            /* TODO - fatal error.  Bad data written to DRAM. */
+	    PRINT_ERROR("L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error\n");
+        }
+	PRINT_ERROR("CVMX_L2C_ERR_VBF: 0x%llx\n", (unsigned long long)l2c_err_vbf.u64);
+    }
+
+    return 1;
+}
diff --git a/sys/contrib/octeon-sdk/cvmx-error-custom.h b/sys/contrib/octeon-sdk/cvmx-error-custom.h
index e6a13f0..019835e 100644
--- a/sys/contrib/octeon-sdk/cvmx-error-custom.h
+++ b/sys/contrib/octeon-sdk/cvmx-error-custom.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -83,6 +83,7 @@ int __cvmx_error_handle_pow_ecc_err_dbe(const struct cvmx_error_info *info);
 int __cvmx_error_handle_pow_ecc_err_iop(const struct cvmx_error_info *info);
 int __cvmx_error_handle_pow_ecc_err_rpe(const struct cvmx_error_info *info);
 int __cvmx_error_handle_pow_ecc_err_sbe(const struct cvmx_error_info *info);
+int __cvmx_error_handle_63XX_l2_ecc(const struct cvmx_error_info *info);
 
 #ifdef	__cplusplus
 }
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn30xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn30xx.c
index 79371dd..6e266740 100644
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn30xx.c
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn30xx.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn31xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn31xx.c
index 7d3f531..14592f2 100644
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn31xx.c
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn31xx.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn38xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn38xx.c
index 41582de..dd89451 100644
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn38xx.c
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn38xx.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn38xxp2.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn38xxp2.c
index 7d7c10c..d4d7244 100644
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn38xxp2.c
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn38xxp2.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn50xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn50xx.c
index ecd0ca1..f25fe7b 100644
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn50xx.c
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn50xx.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn52xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn52xx.c
index 9743995..0e83963 100644
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn52xx.c
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn52xx.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -102,7 +102,7 @@
  *     cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
  *     cvmx_usbn1_int_sum [label="USBNX_INT_SUM(1)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
  *     cvmx_npei_rsl_int_blocks:usb1:e -> cvmx_usbn1_int_sum [label="usb1"];
- *     cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_ldwn>c0_ldwn|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_ldwn>c1_ldwn|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<dma4dbo>dma4dbo|<c0_exc>c0_exc|<c1_exc>c1_exc"];
+ *     cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<dma4dbo>dma4dbo|<c0_exc>c0_exc|<c1_exc>c1_exc"];
  *     cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
  *     cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"];
  *     cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
@@ -120,7 +120,7 @@
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
  *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
  *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
  *     cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
@@ -2910,22 +2910,6 @@ int cvmx_error_initialize_cn52xx(void)
     /* CVMX_PEXP_NPEI_INT_SUM */
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
-    info.status_mask        = 1ull<<59 /* c0_ldwn */;
-    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
-    info.enable_mask        = 1ull<<59 /* c0_ldwn */;
-    info.flags              = 0;
-    info.group              = CVMX_ERROR_GROUP_PCI;
-    info.group_index        = 0;
-    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
-    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
-    info.parent.status_mask = 1ull<<3 /* npei */;
-    info.func               = __cvmx_error_display;
-    info.user_info          = (long)
-        "ERROR PEXP_NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n";
-    fail |= cvmx_error_add(&info);
-
-    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
     info.status_mask        = 1ull<<21 /* c0_se */;
     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
     info.enable_mask        = 1ull<<21 /* c0_se */;
@@ -3197,22 +3181,6 @@ int cvmx_error_initialize_cn52xx(void)
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
-    info.status_mask        = 1ull<<60 /* c1_ldwn */;
-    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
-    info.enable_mask        = 1ull<<60 /* c1_ldwn */;
-    info.flags              = 0;
-    info.group              = CVMX_ERROR_GROUP_PCI;
-    info.group_index        = 1;
-    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
-    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
-    info.parent.status_mask = 1ull<<3 /* npei */;
-    info.func               = __cvmx_error_display;
-    info.user_info          = (long)
-        "ERROR PEXP_NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n";
-    fail |= cvmx_error_add(&info);
-
-    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
     info.status_mask        = 1ull<<28 /* c1_se */;
     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
     info.enable_mask        = 1ull<<28 /* c1_se */;
@@ -5357,6 +5325,22 @@ int cvmx_error_initialize_cn52xx(void)
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
     info.status_mask        = 1ull<<4 /* synlos */;
     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
     info.enable_mask        = 1ull<<4 /* synlos_en */;
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn52xxp1.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn52xxp1.c
index a0f24b3..16ef44e 100644
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn52xxp1.c
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn52xxp1.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -100,7 +100,7 @@
  *     cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
  *     cvmx_usbn1_int_sum [label="USBNX_INT_SUM(1)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
  *     cvmx_npei_rsl_int_blocks:usb1:e -> cvmx_usbn1_int_sum [label="usb1"];
- *     cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_ldwn>c0_ldwn|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_ldwn>c1_ldwn|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<c0_exc>c0_exc|<c1_exc>c1_exc"];
+ *     cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<c0_exc>c0_exc|<c1_exc>c1_exc"];
  *     cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
  *     cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"];
  *     cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
@@ -118,7 +118,7 @@
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
  *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
  *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
  *     cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
@@ -2826,22 +2826,6 @@ int cvmx_error_initialize_cn52xxp1(void)
     /* CVMX_PEXP_NPEI_INT_SUM */
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
-    info.status_mask        = 1ull<<59 /* c0_ldwn */;
-    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
-    info.enable_mask        = 1ull<<59 /* c0_ldwn */;
-    info.flags              = 0;
-    info.group              = CVMX_ERROR_GROUP_PCI;
-    info.group_index        = 0;
-    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
-    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
-    info.parent.status_mask = 1ull<<3 /* npei */;
-    info.func               = __cvmx_error_display;
-    info.user_info          = (long)
-        "ERROR PEXP_NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n";
-    fail |= cvmx_error_add(&info);
-
-    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
     info.status_mask        = 1ull<<21 /* c0_se */;
     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
     info.enable_mask        = 1ull<<21 /* c0_se */;
@@ -3113,22 +3097,6 @@ int cvmx_error_initialize_cn52xxp1(void)
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
-    info.status_mask        = 1ull<<60 /* c1_ldwn */;
-    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
-    info.enable_mask        = 1ull<<60 /* c1_ldwn */;
-    info.flags              = 0;
-    info.group              = CVMX_ERROR_GROUP_PCI;
-    info.group_index        = 1;
-    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
-    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
-    info.parent.status_mask = 1ull<<3 /* npei */;
-    info.func               = __cvmx_error_display;
-    info.user_info          = (long)
-        "ERROR PEXP_NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n";
-    fail |= cvmx_error_add(&info);
-
-    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
     info.status_mask        = 1ull<<28 /* c1_se */;
     info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
     info.enable_mask        = 1ull<<28 /* c1_se */;
@@ -5256,6 +5224,22 @@ int cvmx_error_initialize_cn52xxp1(void)
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
     info.status_mask        = 1ull<<4 /* synlos */;
     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
     info.enable_mask        = 1ull<<4 /* synlos_en */;
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn56xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn56xx.c
index 75be2ce..d4ef2ce 100644
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn56xx.c
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn56xx.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -124,7 +124,7 @@
  *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int2_reg [label="asxpcs1"];
  *     cvmx_pcs1_int3_reg [label="PCSX_INTX_REG(3,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
  *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int3_reg [label="asxpcs1"];
- *     cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
+ *     cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos"];
  *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcsx1_int_reg [label="asxpcs1"];
  *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
@@ -134,7 +134,7 @@
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
  *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
  *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
  *     cvmx_npei_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
@@ -5554,6 +5554,22 @@ int cvmx_error_initialize_cn56xx(void)
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
     info.status_mask        = 1ull<<4 /* synlos */;
     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
     info.enable_mask        = 1ull<<4 /* synlos_en */;
@@ -6184,6 +6200,22 @@ int cvmx_error_initialize_cn56xx(void)
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
     info.status_mask        = 1ull<<4 /* synlos */;
     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
     info.enable_mask        = 1ull<<4 /* synlos_en */;
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn56xxp1.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn56xxp1.c
index 58c2671..557d8ab 100644
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn56xxp1.c
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn56xxp1.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -124,7 +124,7 @@
  *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int2_reg [label="asxpcs1"];
  *     cvmx_pcs1_int3_reg [label="PCSX_INTX_REG(3,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
  *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int3_reg [label="asxpcs1"];
- *     cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
+ *     cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos"];
  *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcsx1_int_reg [label="asxpcs1"];
  *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
@@ -134,7 +134,7 @@
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
  *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
  *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
  *     cvmx_npei_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
@@ -5122,6 +5122,22 @@ int cvmx_error_initialize_cn56xxp1(void)
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
     info.status_mask        = 1ull<<4 /* synlos */;
     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
     info.enable_mask        = 1ull<<4 /* synlos_en */;
@@ -5752,6 +5768,22 @@ int cvmx_error_initialize_cn56xxp1(void)
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
     info.status_mask        = 1ull<<4 /* synlos */;
     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
     info.enable_mask        = 1ull<<4 /* synlos_en */;
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn58xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn58xx.c
index 67db154..d2f6723 100644
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn58xx.c
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn58xx.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn58xxp1.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn58xxp1.c
index a754c11..756526c 100644
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn58xxp1.c
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn58xxp1.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn61xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn61xx.c
new file mode 100644
index 0000000..3d488ac
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn61xx.c
@@ -0,0 +1,9132 @@
+/***********************license start***************
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Automatically generated error messages for cn61xx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ * <hr><h2>Error tree for CN61XX</h2>
+ * @dot
+ * digraph cn61xx
+ * {
+ *     rankdir=LR;
+ *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
+ *     edge [fontsize=7, font=helvitica];
+ *     cvmx_root [label="ROOT|<root>root"];
+ *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<gpio>gpio|<mii>mii|<pcm>pcm"];
+ *     cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
+ *     cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
+ *     cvmx_pcm0_int_sum [label="PCMX_INT_SUM(0)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm0_int_sum [label="pcm"];
+ *     cvmx_pcm1_int_sum [label="PCMX_INT_SUM(1)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm1_int_sum [label="pcm"];
+ *     cvmx_pcm2_int_sum [label="PCMX_INT_SUM(2)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm2_int_sum [label="pcm"];
+ *     cvmx_pcm3_int_sum [label="PCMX_INT_SUM(3)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm3_int_sum [label="pcm"];
+ *     cvmx_pcm0_int_sum -> cvmx_pcm1_int_sum [style=invis];
+ *     cvmx_pcm1_int_sum -> cvmx_pcm2_int_sum [style=invis];
+ *     cvmx_pcm2_int_sum -> cvmx_pcm3_int_sum [style=invis];
+ *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
+ *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1"];
+ *     cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
+ *     cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
+ *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
+ *     cvmx_ciu_block_int [label="CIU_BLOCK_INT|<l2c>l2c|<ipd>ipd|<pow>pow|<rad>rad|<asxpcs1>asxpcs1|<asxpcs0>asxpcs0|<pip>pip|<pko>pko|<pem0>pem0|<pem1>pem1|<gmx0>gmx0|<gmx1>gmx1|<mio>mio|<tim>tim|<lmc0>lmc0|<key>key|<fpa>fpa|<iob>iob|<usb>usb|<agl>agl|<zip>zip|<dfa>dfa|<sli>sli|<dpi>dpi"];
+ *     cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<bigwr>bigwr|<bigrd>bigrd|<tad0>tad0"];
+ *     cvmx_l2c_tad0_int [label="L2C_TADX_INT(0)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_tad0_int [label="tad0"];
+ *     cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
+ *     cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
+ *     cvmx_ciu_block_int:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
+ *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
+ *     cvmx_ciu_block_int:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
+ *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
+ *     cvmx_ciu_block_int:pow:e -> cvmx_pow_ecc_err [label="pow"];
+ *     cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
+ *     cvmx_ciu_block_int:rad:e -> cvmx_rad_reg_error [label="rad"];
+ *     cvmx_pcs1_int0_reg [label="PCSX_INTX_REG(0,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int0_reg [label="asxpcs1"];
+ *     cvmx_pcs1_int1_reg [label="PCSX_INTX_REG(1,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int1_reg [label="asxpcs1"];
+ *     cvmx_pcs1_int2_reg [label="PCSX_INTX_REG(2,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int2_reg [label="asxpcs1"];
+ *     cvmx_pcs1_int3_reg [label="PCSX_INTX_REG(3,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int3_reg [label="asxpcs1"];
+ *     cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcsx1_int_reg [label="asxpcs1"];
+ *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
+ *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
+ *     cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
+ *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
+ *     cvmx_ciu_block_int:pko:e -> cvmx_pko_reg_error [label="pko"];
+ *     cvmx_pem0_int_sum [label="PEMX_INT_SUM(0)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
+ *     cvmx_pem0_dbg_info [label="PEMX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
+ *     cvmx_pem0_int_sum:exc:e -> cvmx_pem0_dbg_info [label="exc"];
+ *     cvmx_ciu_block_int:pem0:e -> cvmx_pem0_int_sum [label="pem0"];
+ *     cvmx_pem1_int_sum [label="PEMX_INT_SUM(1)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
+ *     cvmx_pem1_dbg_info [label="PEMX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
+ *     cvmx_pem1_int_sum:exc:e -> cvmx_pem1_dbg_info [label="exc"];
+ *     cvmx_ciu_block_int:pem1:e -> cvmx_pem1_int_sum [label="pem1"];
+ *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
+ *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
+ *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
+ *     cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
+ *     cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
+ *     cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
+ *     cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
+ *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
+ *     cvmx_ciu_block_int:mio:e -> cvmx_mio_boot_err [label="mio"];
+ *     cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<perst0>perst0|<perst1>perst1"];
+ *     cvmx_ciu_block_int:mio:e -> cvmx_mio_rst_int [label="mio"];
+ *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
+ *     cvmx_ciu_block_int:tim:e -> cvmx_tim_reg_error [label="tim"];
+ *     cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
+ *     cvmx_ciu_block_int:lmc0:e -> cvmx_lmc0_int [label="lmc0"];
+ *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
+ *     cvmx_ciu_block_int:key:e -> cvmx_key_int_sum [label="key"];
+ *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr|<pool0th>pool0th|<pool1th>pool1th|<pool2th>pool2th|<pool3th>pool3th|<pool4th>pool4th|<pool5th>pool5th|<pool6th>pool6th|<pool7th>pool7th|<free0>free0|<free1>free1|<free2>free2|<free3>free3|<free4>free4|<free5>free5|<free6>free6|<free7>free7|<paddr_e>paddr_e"];
+ *     cvmx_ciu_block_int:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
+ *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
+ *     cvmx_ciu_block_int:iob:e -> cvmx_iob_int_sum [label="iob"];
+ *     cvmx_uctl0_int_reg [label="UCTLX_INT_REG(0)|<pp_psh_f>pp_psh_f|<er_psh_f>er_psh_f|<or_psh_f>or_psh_f|<cf_psh_f>cf_psh_f|<wb_psh_f>wb_psh_f|<wb_pop_e>wb_pop_e|<oc_ovf_e>oc_ovf_e|<ec_ovf_e>ec_ovf_e"];
+ *     cvmx_ciu_block_int:usb:e -> cvmx_uctl0_int_reg [label="usb"];
+ *     cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
+ *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
+ *     cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
+ *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
+ *     cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
+ *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
+ *     cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
+ *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
+ *     cvmx_ciu_block_int:zip:e -> cvmx_zip_error [label="zip"];
+ *     cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr|<dlc0_ovferr>dlc0_ovferr|<dfanxm>dfanxm|<replerr>replerr"];
+ *     cvmx_ciu_block_int:dfa:e -> cvmx_dfa_error [label="dfa"];
+ *     cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<m2_up_b0>m2_up_b0|<m2_up_wi>m2_up_wi|<m2_un_b0>m2_un_b0|<m2_un_wi>m2_un_wi|<m3_up_b0>m3_up_b0|<m3_up_wi>m3_up_wi|<m3_un_b0>m3_un_b0|<m3_un_wi>m3_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pin_bp>pin_bp|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<sprt2_err>sprt2_err|<sprt3_err>sprt3_err|<ill_pad>ill_pad"];
+ *     cvmx_ciu_block_int:sli:e -> cvmx_sli_int_sum [label="sli"];
+ *     cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst|<sprt2_rst>sprt2_rst|<sprt3_rst>sprt3_rst"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
+ *     cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
+ *     cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
+ *     cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
+ *     cvmx_pcs1_int0_reg -> cvmx_pcs1_int1_reg [style=invis];
+ *     cvmx_pcs1_int1_reg -> cvmx_pcs1_int2_reg [style=invis];
+ *     cvmx_pcs1_int2_reg -> cvmx_pcs1_int3_reg [style=invis];
+ *     cvmx_pcs1_int3_reg -> cvmx_pcsx1_int_reg [style=invis];
+ *     cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
+ *     cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
+ *     cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
+ *     cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
+ *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
+ *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
+ *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
+ *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
+ *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
+ *     cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
+ *     cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
+ *     cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
+ *     cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
+ *     cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
+ *     cvmx_mio_boot_err -> cvmx_mio_rst_int [style=invis];
+ *     cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
+ *     cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
+ *     cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
+ *     cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
+ *     cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
+ *     cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
+ *     cvmx_root:root:e -> cvmx_ciu_block_int [label="root"];
+ * }
+ * @enddot
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-csr-typedefs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#endif
+
+int cvmx_error_initialize_cn61xx(void);
+
+int cvmx_error_initialize_cn61xx(void)
+{
+    cvmx_error_info_t info;
+    int fail = 0;
+
+    /* CVMX_CIU_INTX_SUM0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INTX_SUM0(0);
+    info.status_mask        = 0xffffull<<16 /* gpio */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR CIU_INTX_SUM0(0)[GPIO]: 16 GPIO interrupts\n"
+        "    When GPIO_MULTI_CAST[EN] == 1\n"
+        "    Write 1 to clear either the per PP or common GPIO\n"
+        "    edge-triggered interrupts,depending on mode.\n"
+        "    See GPIO_MULTI_CAST for all details.\n"
+        "    When GPIO_MULTI_CAST[EN] == 0\n"
+        "    Read Only, retain the same behavior as o63.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INTX_SUM0(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIXX_ISR(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<0 /* odblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<0 /* ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(OVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
+        "    future ODBELL writes don't exceed the size of the\n"
+        "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
+        "    SW must reclaim O-Ring Entries by writing to the\n"
+        "    MIX_ORCNT[ORCNT]. .\n"
+        "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the O-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<1 /* idblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<1 /* ivfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(IVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
+        "    future IDBELL writes don't exceed the size of the\n"
+        "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
+        "    SW must reclaim I-Ring Entries by keeping track of the\n"
+        "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
+        "    total #packets(not IRing Entries) and SW must further\n"
+        "    keep track of the # of I-Ring Entries associated with\n"
+        "    each packet as they are processed.\n"
+        "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the I-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<4 /* data_drp */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<4 /* data_drpena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
+        "    If this does occur, the DATA_DRP is set and the\n"
+        "    CIU_INTx_SUM0,4[MII] bits are set.\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
+        "    interrupt is reported for this event.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<5 /* irun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<5 /* irunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
+        "    NOTE: If an IRUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<6 /* orun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<6 /* orunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
+        "    NOTE: If an ORUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[FSYNCMISSED]: FSYNC missed interrupt occurred                 |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[FSYNCEXTRA]: FSYNC extra interrupt occurred                  |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[TXEMPTY]: TX byte was empty when sampled                  |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[RXOVF]: RX byte overflowed                              |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[FSYNCMISSED]: FSYNC missed interrupt occurred                 |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[FSYNCEXTRA]: FSYNC extra interrupt occurred                  |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[TXEMPTY]: TX byte was empty when sampled                  |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[RXOVF]: RX byte overflowed                              |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[FSYNCMISSED]: FSYNC missed interrupt occurred                 |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[FSYNCEXTRA]: FSYNC extra interrupt occurred                  |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[TXEMPTY]: TX byte was empty when sampled                  |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[RXOVF]: RX byte overflowed                              |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[FSYNCMISSED]: FSYNC missed interrupt occurred                 |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[FSYNCEXTRA]: FSYNC extra interrupt occurred                  |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[TXEMPTY]: TX byte was empty when sampled                  |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[RXOVF]: RX byte overflowed                              |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU_INT_SUM1 */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INT_SUM1;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIXX_ISR(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<0 /* odblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<0 /* ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(OVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
+        "    future ODBELL writes don't exceed the size of the\n"
+        "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
+        "    SW must reclaim O-Ring Entries by writing to the\n"
+        "    MIX_ORCNT[ORCNT]. .\n"
+        "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the O-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<1 /* idblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<1 /* ivfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(IVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
+        "    future IDBELL writes don't exceed the size of the\n"
+        "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
+        "    SW must reclaim I-Ring Entries by keeping track of the\n"
+        "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
+        "    total #packets(not IRing Entries) and SW must further\n"
+        "    keep track of the # of I-Ring Entries associated with\n"
+        "    each packet as they are processed.\n"
+        "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the I-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<4 /* data_drp */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<4 /* data_drpena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
+        "    If this does occur, the DATA_DRP is set and the\n"
+        "    CIU_INTx_SUM0,4[MII] bits are set.\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
+        "    interrupt is reported for this event.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<5 /* irun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<5 /* irunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
+        "    NOTE: If an IRUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<6 /* orun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<6 /* orunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
+        "    NOTE: If an ORUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU_BLOCK_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_BLOCK_INT;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<0 /* holerd */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<0 /* holerd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<1 /* holewr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<1 /* holewr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<2 /* vrtwr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<2 /* vrtwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
+        "    Set when L2C_VRT_MEM blocked a store.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<3 /* vrtidrng */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<3 /* vrtidrng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
+        "    Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
+        "    store.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<4 /* vrtadrng */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<4 /* vrtadrng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
+        "    Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
+        "    store.\n"
+        "    L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<5 /* vrtpe */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<5 /* vrtpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
+        "    Whenever an L2C_VRT_MEM read finds a parity error,\n"
+        "    that L2C_VRT_MEM cannot cause stores to be blocked.\n"
+        "    Software should correct the error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<6 /* bigwr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<6 /* bigwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[BIGWR]: Write reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<7 /* bigrd */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<7 /* bigrd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[BIGRD]: Read reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_TADX_INT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<0 /* l2dsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<0 /* l2dsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[L2DSBE]: L2D Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<1 /* l2ddbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<1 /* l2ddbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[L2DDBE]: L2D Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<2 /* tagsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<2 /* tagsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[TAGSBE]: TAG Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<3 /* tagdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<3 /* tagdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[TAGDBE]: TAG Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<4 /* vbfsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<4 /* vbfsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VSBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<5 /* vbfdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<5 /* vbfdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VDBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<6 /* noway */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<6 /* noway */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[NOWAY]: No way available interrupt\n"
+        "    Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<7 /* rddislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<7 /* rddislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[RDDISLMC]: Illegal Read  to Disabled LMC Error\n"
+        "    A DRAM read  arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<8 /* wrdislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<8 /* wrdislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
+        "    A DRAM write arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TDTX(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<60 /* vsbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<61 /* vdbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TTGX(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<61 /* noway */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
+        "    L2C sets NOWAY during its processing of a\n"
+        "    transaction whenever it needed/wanted to allocate\n"
+        "    a WAY in the L2 cache, but was unable to. NOWAY==1\n"
+        "    is (generally) not an indication that L2C failed to\n"
+        "    complete transactions. Rather, it is a hint of\n"
+        "    possible performance degradation. (For example, L2C\n"
+        "    must read-modify-write DRAM for every transaction\n"
+        "    that updates some, but not all, of the bytes in a\n"
+        "    cache block, misses in the L2 cache, and cannot\n"
+        "    allocate a WAY.) There is one \"failure\" case where\n"
+        "    L2C will set NOWAY: when it cannot leave a block\n"
+        "    locked in the L2 cache as part of a LCKL2\n"
+        "    transaction.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IPD_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<0 /* prc_par0 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* prc_par0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+        "    [31:0] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<1 /* prc_par1 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* prc_par1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+        "    [63:32] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<2 /* prc_par2 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* prc_par2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+        "    [95:64] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<3 /* prc_par3 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* prc_par3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+        "    [127:96] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<4 /* bp_sub */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* bp_sub */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+        "    supplied illegal value.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* dc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<6 /* cc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* cc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<7 /* c_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* c_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<8 /* d_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* d_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<9 /* bc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* bc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_POW_ECC_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<0 /* sbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<2 /* sbe_ie */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<1 /* dbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<3 /* dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<12 /* rpe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<13 /* rpe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 0x1fffull<<16 /* iop */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_iop;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_RAD_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_RAD_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_RAD_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<14 /* rad */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<6 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<6 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<6 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PIP_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<3 /* prtnxa */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<3 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<4 /* badtag */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<4 /* badtag */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<5 /* skprunt */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<5 /* skprunt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+        "    This interrupt can occur with received PARTIAL\n"
+        "    packets that are truncated to SKIP bytes or\n"
+        "    smaller.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<6 /* todoovr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<6 /* todoovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<7 /* feperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<7 /* feperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<8 /* beperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<8 /* beperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<12 /* punyerr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<12 /* punyerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
+        "    stripping in IPD is enable\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PKO_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* parity */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* parity */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<1 /* doorbell */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<1 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<2 /* currzero */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<2 /* currzero */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_INT_SUM(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<1 /* se */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<1 /* se */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[SE]: System Error, RC Mode Only.\n"
+        "    (cfg_sys_err_rc)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<4 /* up_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<4 /* up_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<5 /* up_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<5 /* up_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<6 /* up_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<6 /* up_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UP_BX]: Received P-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<7 /* un_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<7 /* un_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<8 /* un_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<8 /* un_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<9 /* un_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<9 /* un_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UN_BX]: Received N-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<11 /* rdlk */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<11 /* rdlk */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[RDLK]: Received Read Lock TLP.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<12 /* crs_er */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<12 /* crs_er */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<13 /* crs_dr */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<13 /* crs_dr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_DBG_INFO(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<0 /* spoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<0 /* spoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
+        "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<2 /* rtlplle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<2 /* rtlplle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
+        "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<3 /* recrce */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<3 /* recrce */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
+        "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<4 /* rpoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<4 /* rpoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
+        "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<5 /* rcemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<5 /* rcemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+        "    pedc_radm_correctable_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<6 /* rnfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<6 /* rnfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_nonfatal_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<7 /* rfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<7 /* rfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_fatal_err\n"
+        "    Bit set when a message with ERR_FATAL is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<8 /* rpmerc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<8 /* rpmerc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
+        "    pedc_radm_pm_pme\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<9 /* rptamrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<9 /* rptamrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+        "    (RC Mode only)\n"
+        "    pedc_radm_pm_to_ack\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<10 /* rumep */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<10 /* rumep */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+        "    pedc_radm_msg_unlock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<11 /* rvdm */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<11 /* rvdm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
+        "    pedc_radm_vendor_msg\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<12 /* acto */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<12 /* acto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
+        "    pedc_radm_cpl_timeout\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<13 /* rte */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<13 /* rte */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
+        "    xdlh_replay_timeout_err\n"
+        "    This bit is set when the REPLAY_TIMER expires in\n"
+        "    the PCIE core. The probability of this bit being\n"
+        "    set will increase with the traffic load.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<14 /* mre */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<14 /* mre */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
+        "    xdlh_replay_num_rlover_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<15 /* rdwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<15 /* rdwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+        "    rdlh_bad_dllp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<16 /* rtwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<16 /* rtwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
+        "    rdlh_bad_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<17 /* dpeoosd */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<17 /* dpeoosd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+        "    rdlh_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<18 /* fcpvwt */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<18 /* fcpvwt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+        "    rtlh_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<19 /* rpe */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<19 /* rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
+        "    (RxStatus = 3b100) or disparity error\n"
+        "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+        "    be asserted.\n"
+        "    rmlh_rcvd_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<20 /* fcuv */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<20 /* fcuv */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
+        "    int_xadm_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<21 /* rqo */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<21 /* rqo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
+        "    flow control advertisements are ignored\n"
+        "    radm_qoverflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<22 /* rauc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<22 /* rauc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
+        "    radm_unexp_cpl_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<23 /* racur */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<23 /* racur */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
+        "    radm_rcvd_cpl_ur\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<24 /* racca */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<24 /* racca */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
+        "    radm_rcvd_cpl_ca\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<25 /* caar */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<25 /* caar */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
+        "    radm_rcvd_ca_req\n"
+        "    This bit will never be set because Octeon does\n"
+        "    not generate Completer Aborts.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<26 /* rarwdns */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<26 /* rarwdns */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
+        "    radm_rcvd_ur_req\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<27 /* ramtlp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<27 /* ramtlp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
+        "    radm_mlf_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<28 /* racpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<28 /* racpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
+        "    radm_rcvd_cpl_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<29 /* rawwpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<29 /* rawwpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
+        "    radm_rcvd_wreq_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<30 /* ecrc_e */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<30 /* ecrc_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
+        "    radm_ecrc_err\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_INT_SUM(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<1 /* se */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<1 /* se */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[SE]: System Error, RC Mode Only.\n"
+        "    (cfg_sys_err_rc)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<4 /* up_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<4 /* up_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<5 /* up_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<5 /* up_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<6 /* up_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<6 /* up_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UP_BX]: Received P-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<7 /* un_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<7 /* un_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<8 /* un_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<8 /* un_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<9 /* un_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<9 /* un_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UN_BX]: Received N-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<11 /* rdlk */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<11 /* rdlk */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[RDLK]: Received Read Lock TLP.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<12 /* crs_er */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<12 /* crs_er */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<13 /* crs_dr */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<13 /* crs_dr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_DBG_INFO(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<0 /* spoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<0 /* spoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
+        "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<2 /* rtlplle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<2 /* rtlplle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
+        "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<3 /* recrce */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<3 /* recrce */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
+        "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<4 /* rpoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<4 /* rpoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
+        "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<5 /* rcemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<5 /* rcemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+        "    pedc_radm_correctable_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<6 /* rnfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<6 /* rnfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_nonfatal_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<7 /* rfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<7 /* rfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_fatal_err\n"
+        "    Bit set when a message with ERR_FATAL is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<8 /* rpmerc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<8 /* rpmerc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
+        "    pedc_radm_pm_pme\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<9 /* rptamrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<9 /* rptamrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+        "    (RC Mode only)\n"
+        "    pedc_radm_pm_to_ack\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<10 /* rumep */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<10 /* rumep */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+        "    pedc_radm_msg_unlock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<11 /* rvdm */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<11 /* rvdm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
+        "    pedc_radm_vendor_msg\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<12 /* acto */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<12 /* acto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
+        "    pedc_radm_cpl_timeout\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<13 /* rte */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<13 /* rte */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
+        "    xdlh_replay_timeout_err\n"
+        "    This bit is set when the REPLAY_TIMER expires in\n"
+        "    the PCIE core. The probability of this bit being\n"
+        "    set will increase with the traffic load.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<14 /* mre */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<14 /* mre */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
+        "    xdlh_replay_num_rlover_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<15 /* rdwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<15 /* rdwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+        "    rdlh_bad_dllp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<16 /* rtwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<16 /* rtwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
+        "    rdlh_bad_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<17 /* dpeoosd */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<17 /* dpeoosd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+        "    rdlh_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<18 /* fcpvwt */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<18 /* fcpvwt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+        "    rtlh_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<19 /* rpe */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<19 /* rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
+        "    (RxStatus = 3b100) or disparity error\n"
+        "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+        "    be asserted.\n"
+        "    rmlh_rcvd_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<20 /* fcuv */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<20 /* fcuv */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
+        "    int_xadm_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<21 /* rqo */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<21 /* rqo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
+        "    flow control advertisements are ignored\n"
+        "    radm_qoverflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<22 /* rauc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<22 /* rauc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
+        "    radm_unexp_cpl_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<23 /* racur */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<23 /* racur */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
+        "    radm_rcvd_cpl_ur\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<24 /* racca */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<24 /* racca */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
+        "    radm_rcvd_cpl_ca\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<25 /* caar */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<25 /* caar */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
+        "    radm_rcvd_ca_req\n"
+        "    This bit will never be set because Octeon does\n"
+        "    not generate Completer Aborts.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<26 /* rarwdns */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<26 /* rarwdns */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
+        "    radm_rcvd_ur_req\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<27 /* ramtlp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<27 /* ramtlp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
+        "    radm_mlf_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<28 /* racpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<28 /* racpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
+        "    radm_rcvd_cpl_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<29 /* rawwpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<29 /* rawwpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
+        "    radm_rcvd_wreq_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<30 /* ecrc_e */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<30 /* ecrc_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
+        "    radm_ecrc_err\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In SGMII, one bit per port\n"
+        "    In XAUI, only port0 is used\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
+        "    The common FIFO to SGMII and XAUI had an overflow\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<20 /* ptp_lost */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<20 /* ptp_lost */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n"
+        "    sent due to XSCOL\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In SGMII, one bit per port\n"
+        "    In XAUI, only port0 is used\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n"
+        "    The common FIFO to SGMII and XAUI had an overflow\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 0xfull<<20 /* ptp_lost */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 0xfull<<20 /* ptp_lost */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[PTP_LOST]: A packet with a PTP request was not able to be\n"
+        "    sent due to XSCOL\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_BOOT_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<0 /* adr_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<0 /* adr_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<1 /* wait_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<1 /* wait_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_RST_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<0 /* rst_link0 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<0 /* rst_link0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n"
+        "    MIO_RST_CTL0[RST_LINK]=0.  Software must assert\n"
+        "    then de-assert CIU_SOFT_PRST[SOFT_PRST]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<1 /* rst_link1 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<1 /* rst_link1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n"
+        "    MIO_RST_CTL1[RST_LINK]=0.  Software must assert\n"
+        "    then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<8 /* perst0 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<8 /* perst0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1\n"
+        "    and MIO_RST_CTL0[RST_CHIP]=0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<9 /* perst1 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<9 /* perst1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1\n"
+        "    and MIO_RST_CTL1[RST_CHIP]=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_TIM_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_TIM_REG_ERROR;
+    info.status_mask        = 0xffffull<<0 /* mask */;
+    info.enable_addr        = CVMX_TIM_REG_INT_MASK;
+    info.enable_mask        = 0xffffull<<0 /* mask */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<11 /* tim */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_INT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 0xfull<<1 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<1 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "     where _cC_pP denotes cycle C and phase P\n"
+        "     Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 1ull<<0 /* nxm_wr_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* intr_nxm_wr_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 0xfull<<5 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<2 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "     where _cC_pP denotes cycle C and phase P\n"
+        "     Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_KEY_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<0 /* ked0_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* ked0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<1 /* ked0_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* ked0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<2 /* ked1_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* ked1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<3 /* ked1_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* ked1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_FPA_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<0 /* fed0_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* fed0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<1 /* fed0_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* fed0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<2 /* fed1_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* fed1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<3 /* fed1_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* fed1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<4 /* q0_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* q0_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<5 /* q0_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* q0_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<6 /* q0_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* q0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<7 /* q1_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* q1_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<8 /* q1_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* q1_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<9 /* q1_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* q1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<10 /* q2_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* q2_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<11 /* q2_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* q2_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<12 /* q2_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* q2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<13 /* q3_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* q3_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<14 /* q3_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* q3_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<15 /* q3_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* q3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<16 /* q4_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* q4_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<17 /* q4_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* q4_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<18 /* q4_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* q4_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<19 /* q5_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* q5_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<20 /* q5_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* q5_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<21 /* q5_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* q5_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<22 /* q6_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* q6_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<23 /* q6_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* q6_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<24 /* q6_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* q6_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<25 /* q7_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* q7_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<26 /* q7_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* q7_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<27 /* q7_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* q7_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<28 /* pool0th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<28 /* pool0th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL0TH]: Set when FPA_QUE0_AVAILABLE is equal to\n"
+        "    FPA_POOL`_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<29 /* pool1th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<29 /* pool1th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL1TH]: Set when FPA_QUE1_AVAILABLE is equal to\n"
+        "    FPA_POOL1_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<30 /* pool2th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<30 /* pool2th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL2TH]: Set when FPA_QUE2_AVAILABLE is equal to\n"
+        "    FPA_POOL2_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<31 /* pool3th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<31 /* pool3th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL3TH]: Set when FPA_QUE3_AVAILABLE is equal to\n"
+        "    FPA_POOL3_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<32 /* pool4th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<32 /* pool4th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL4TH]: Set when FPA_QUE4_AVAILABLE is equal to\n"
+        "    FPA_POOL4_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<33 /* pool5th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<33 /* pool5th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL5TH]: Set when FPA_QUE5_AVAILABLE is equal to\n"
+        "    FPA_POOL5_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<34 /* pool6th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<34 /* pool6th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL6TH]: Set when FPA_QUE6_AVAILABLE is equal to\n"
+        "    FPA_POOL6_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<35 /* pool7th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<35 /* pool7th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL7TH]: Set when FPA_QUE7_AVAILABLE is equal to\n"
+        "    FPA_POOL7_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<36 /* free0 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<36 /* free0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE0]: When a pointer for POOL0 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<37 /* free1 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<37 /* free1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE1]: When a pointer for POOL1 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<38 /* free2 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<38 /* free2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE2]: When a pointer for POOL2 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<39 /* free3 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<39 /* free3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE3]: When a pointer for POOL3 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<40 /* free4 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<40 /* free4 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE4]: When a pointer for POOL4 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<41 /* free5 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<41 /* free5 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE5]: When a pointer for POOL5 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<42 /* free6 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<42 /* free6 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE6]: When a pointer for POOL6 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<43 /* free7 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<43 /* free7 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE7]: When a pointer for POOL7 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<49 /* paddr_e */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<49 /* paddr_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[PADDR_E]: Set when a pointer address does not fall in the\n"
+        "    address range for a pool specified by\n"
+        "    FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IOB_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<0 /* np_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* np_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<1 /* np_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* np_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<2 /* p_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* p_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<3 /* p_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* p_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<4 /* np_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* np_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<5 /* p_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* p_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_UCTLX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pp_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<0 /* pp_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[PP_PSH_F]: PP Access FIFO  Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* er_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<1 /* er_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[ER_PSH_F]: EHCI Read Buffer FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* or_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<2 /* or_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[OR_PSH_F]: OHCI Read Buffer FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* cf_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<3 /* cf_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[CF_PSH_F]: Command FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* wb_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<4 /* wb_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[WB_PSH_F]: Write Buffer FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* wb_pop_e */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<5 /* wb_pop_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[WB_POP_E]: Write Buffer FIFO Poped When Empty\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* oc_ovf_e */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<6 /* oc_ovf_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[OC_OVF_E]: Ohci Commit OVerFlow Error\n"
+        "    When the error happenes, the whole NCB system needs\n"
+        "    to be reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<7 /* ec_ovf_e */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<7 /* ec_ovf_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[EC_OVF_E]: Ehci Commit OVerFlow Error\n"
+        "    When the error happenes, the whole NCB system needs\n"
+        "    to be reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_BAD_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<32 /* ovrflw */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (RGMII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<33 /* txpop */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (RGMII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<34 /* txpsh */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (RGMII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<35 /* ovrflw1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (RGMII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<36 /* txpop1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (RGMII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<37 /* txpsh1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (RGMII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 0x3ull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 0x3ull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In RGMII, one bit per port\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_RXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_RXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_TX_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 0x3ull<<2 /* undflw */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 0x3ull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ZIP_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ZIP_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_ZIP_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<7 /* zip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DFA_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 1ull<<0 /* dblovf */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 1ull<<0 /* dblina */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
+        "    When set, the 20b accumulated doorbell register\n"
+        "    had overflowed (SW wrote too many doorbell requests).\n"
+        "    If the DBLINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    NOTE: Detection of a Doorbell Register overflow\n"
+        "    is a catastrophic error which may leave the DFA\n"
+        "    HW in an unrecoverable state.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 0x7ull<<1 /* dc0perr */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 0x7ull<<1 /* dc0pena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DC0PERR]: Cluster#0 RAM[3:1] Parity Error Detected\n"
+        "    See also DFA_DTCFADR register which contains the\n"
+        "    failing addresses for the internal node cache RAMs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 1ull<<13 /* dlc0_ovferr */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 1ull<<13 /* dlc0_ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DLC0_OVFERR]: DLC0 Fifo Overflow Error Detected\n"
+        "    This condition should NEVER architecturally occur, and\n"
+        "    is here in case HW credit/debit scheme is not working.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 1ull<<17 /* dfanxm */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 1ull<<17 /* dfanxmena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DFANXM]: DFA Non-existent Memory Access\n"
+        "    For o68/o61: DTEs (and backdoor CSR DFA Memory REGION reads)\n"
+        "    have access to the following 38bit L2/DRAM address space\n"
+        "    which maps to a 37bit physical DDR3 SDRAM address space.\n"
+        "    see:\n"
+        "    DR0: 0x0 0000 0000 0000 to 0x0 0000 0FFF FFFF\n"
+        "            maps to lower 256MB of physical DDR3 SDRAM\n"
+        "    DR1: 0x0 0000 2000 0000 to 0x0 0020 0FFF FFFF\n"
+        "            maps to upper 127.75GB of DDR3 SDRAM\n"
+        "               L2/DRAM address space                     Physical DDR3 SDRAM Address space\n"
+        "                 (38bit address)                           (37bit address)\n"
+        "                  +-----------+ 0x0020.0FFF.FFFF\n"
+        "                  |\n"
+        "                 ===   DR1   ===                          +-----------+ 0x001F.FFFF.FFFF\n"
+        "     (128GB-256MB)|           |                           |\n"
+        "                  |           |                     =>    |           |  (128GB-256MB)\n"
+        "                  +-----------+ 0x0000.1FFF.FFFF          |   DR1\n"
+        "          256MB   |   HOLE    |   (DO NOT USE)            |\n"
+        "                  +-----------+ 0x0000.0FFF.FFFF          +-----------+ 0x0000.0FFF.FFFF\n"
+        "          256MB   |    DR0    |                           |   DR0     |   (256MB)\n"
+        "                  +-----------+ 0x0000.0000.0000          +-----------+ 0x0000.0000.0000\n"
+        "    In the event the DFA generates a reference to the L2/DRAM\n"
+        "    address hole (0x0000.0FFF.FFFF - 0x0000.1FFF.FFFF) or to\n"
+        "    an address above 0x0020.0FFF.FFFF, the DFANXM programmable\n"
+        "    interrupt bit will be set.\n"
+        "    SWNOTE: Both the 1) SW DFA Graph compiler and the 2) SW NCB-Direct CSR\n"
+        "    accesses to DFA Memory REGION MUST avoid making references\n"
+        "    to these non-existent memory regions.\n"
+        "    NOTE: If DFANXM is set during a DFA Graph Walk operation,\n"
+        "    then the walk will prematurely terminate with RWORD0[REA]=ERR.\n"
+        "    If DFANXM is set during a NCB-Direct CSR read access to DFA\n"
+        "    Memory REGION, then the CSR read response data is forced to\n"
+        "    128'hBADE_FEED_DEAD_BEEF_FACE_CAFE_BEAD_C0DE. (NOTE: the QW\n"
+        "    being accessed, either the upper or lower QW will be returned).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 1ull<<18 /* replerr */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 1ull<<18 /* replerrena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[REPLERR]: DFA Illegal Replication Factor Error\n"
+        "    For o68: DFA only supports 1x, 2x, and 4x port replication.\n"
+        "    Legal configurations for memory are to support 2 port or\n"
+        "    4 port configurations.\n"
+        "    The REPLERR interrupt will be set in the following illegal\n"
+        "    configuration cases:\n"
+        "        1) An 8x replication factor is detected for any memory reference.\n"
+        "        2) A 4x replication factor is detected for any memory reference\n"
+        "           when only 2 memory ports are enabled.\n"
+        "    NOTE: If REPLERR is set during a DFA Graph Walk operation,\n"
+        "    then the walk will prematurely terminate with RWORD0[REA]=ERR.\n"
+        "    If REPLERR is set during a NCB-Direct CSR read access to DFA\n"
+        "    Memory REGION, then the CSR read response data is UNPREDICTABLE.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEXP_SLI_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<0 /* rml_to */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<0 /* rml_to */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n"
+        "    within 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<1 /* reserved_1_1 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<1 /* reserved_1_1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<2 /* bar0_to */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<2 /* bar0_to */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
+        "    read-data/commit in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<3 /* iob2big */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<3 /* iob2big */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 0x3ull<<6 /* reserved_6_7 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 0x3ull<<6 /* reserved_6_7 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<8 /* m0_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<8 /* m0_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<9 /* m0_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<9 /* m0_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n"
+        "    from MAC 0. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<10 /* m0_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<10 /* m0_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<11 /* m0_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<11 /* m0_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n"
+        "    from MAC 0. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<12 /* m1_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<12 /* m1_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<13 /* m1_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<13 /* m1_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n"
+        "    from MAC 1. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<14 /* m1_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<14 /* m1_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<15 /* m1_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<15 /* m1_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n"
+        "    from MAC 1. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<20 /* m2_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<20 /* m2_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M2_UP_B0]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<21 /* m2_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<21 /* m2_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M2_UP_WI]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<22 /* m2_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<22 /* m2_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M2_UN_B0]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<23 /* m2_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<23 /* m2_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M2_UN_WI]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<24 /* m3_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<24 /* m3_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M3_UP_B0]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<25 /* m3_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<25 /* m3_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M3_UP_WI]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<26 /* m3_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<26 /* m3_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M3_UN_B0]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<27 /* m3_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<27 /* m3_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M3_UN_WI]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<48 /* pidbof */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<48 /* pidbof */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
+        "    doorbell can be found in DPI_PINT_INFO[PIDBOF]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<49 /* psldbof */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<49 /* psldbof */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
+        "    doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<50 /* pout_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<50 /* pout_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n"
+        "    set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<51 /* pin_bp */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<51 /* pin_bp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PIN_BP]: Packet input count has exceeded the WMARK.\n"
+        "    See SLI_PKT_IN_BP\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<52 /* pgl_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<52 /* pgl_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n"
+        "    read this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<53 /* pdi_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<53 /* pdi_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<54 /* pop_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<54 /* pop_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n"
+        "    pointer pair this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<55 /* pins_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<55 /* pins_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<56 /* sprt0_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<56 /* sprt0_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<57 /* sprt1_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<57 /* sprt1_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<58 /* sprt2_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<58 /* sprt2_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT2_ERR]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<59 /* sprt3_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<59 /* sprt3_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT3_ERR]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<60 /* ill_pad */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<60 /* ill_pad */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n"
+        "    range of the Packet-CSR, but for an unused\n"
+        "    address.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<0 /* nderr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<0 /* nderr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n"
+        "    DPI received a NCB transaction on the outbound\n"
+        "    bus to the DPI deviceID, but the command was not\n"
+        "    recognized.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<1 /* nfovr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<1 /* nfovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n"
+        "    DPI can store upto 16 CSR request.  The FIFO will\n"
+        "    overflow if that number is exceeded.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 0xffull<<8 /* dmadbo */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 0xffull<<8 /* dmadbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n"
+        "    DPI has a 32-bit counter for each request's queue\n"
+        "    outstanding doorbell counts. Interrupt will fire\n"
+        "    if the count overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<16 /* req_badadr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<16 /* req_badadr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n"
+        "    Interrupt will fire if DPI forms an instruction\n"
+        "    fetch to the NULL pointer.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<17 /* req_badlen */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<17 /* req_badlen */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n"
+        "    Interrupt will fire if DPI forms an instruction\n"
+        "    fetch with length of zero.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<18 /* req_ovrflw */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<18 /* req_ovrflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n"
+        "    DPI tracks outstanding instructions fetches.\n"
+        "    Interrupt will fire when FIFO overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<19 /* req_undflw */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<19 /* req_undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n"
+        "    DPI tracks outstanding instructions fetches.\n"
+        "    Interrupt will fire when FIFO underflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<20 /* req_anull */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<20 /* req_anull */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n"
+        "    Fetched instruction word was 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<21 /* req_inull */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<21 /* req_inull */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n"
+        "    Next pointer was NULL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<22 /* req_badfil */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<22 /* req_badfil */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n"
+        "    Instruction fill when none outstanding.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<24 /* sprt0_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<24 /* sprt0_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<25 /* sprt1_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<25 /* sprt1_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<26 /* sprt2_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<26 /* sprt2_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT2_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<27 /* sprt3_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<27 /* sprt3_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT3_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_PKT_ERR_RSP */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_PKT_ERR_RSP;
+    info.status_mask        = 1ull<<0 /* pkterr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n"
+        "    the I/O subsystem.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_REQ_ERR_RSP */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_REQ_ERR_RSP;
+    info.status_mask        = 0xffull<<0 /* qerr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n"
+        "    ErrorResponse from the I/O subsystem.\n"
+        "    SW must clear the bit before the the cooresponding\n"
+        "    instruction queue will continue processing\n"
+        "    instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_REQ_ERR_RST */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_REQ_ERR_RST;
+    info.status_mask        = 0xffull<<0 /* qerr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n"
+        "    instruction because the source or destination\n"
+        "    was in reset.\n"
+        "    SW must clear the bit before the the cooresponding\n"
+        "    instruction queue will continue processing\n"
+        "    instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    return fail;
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn63xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn63xx.c
index 8370325..b019ac0 100644
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn63xx.c
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn63xx.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -67,10 +67,8 @@
  *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
  *     cvmx_ciu_block_int [label="CIU_BLOCK_INT|<l2c>l2c|<ipd>ipd|<pow>pow|<rad>rad|<asxpcs0>asxpcs0|<pip>pip|<pko>pko|<pem0>pem0|<pem1>pem1|<fpa>fpa|<usb>usb|<mio>mio|<dfm>dfm|<tim>tim|<lmc0>lmc0|<key>key|<gmx0>gmx0|<iob>iob|<agl>agl|<zip>zip|<dfa>dfa|<srio0>srio0|<srio1>srio1|<sli>sli|<dpi>dpi"];
  *     cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<bigwr>bigwr|<bigrd>bigrd|<tad0>tad0"];
- *     cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
- *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
- *     cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
- *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
+ *     cvmx_l2c_tad0_int [label="L2C_TADX_INT(0)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_tad0_int [label="tad0"];
  *     cvmx_ciu_block_int:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
  *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
  *     cvmx_ciu_block_int:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
@@ -86,7 +84,7 @@
  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
  *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
  *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
  *     cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
@@ -142,9 +140,9 @@
  *     cvmx_ciu_block_int:zip:e -> cvmx_zip_error [label="zip"];
  *     cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr"];
  *     cvmx_ciu_block_int:dfa:e -> cvmx_dfa_error [label="dfa"];
- *     cvmx_srio0_int_reg [label="SRIOX_INT_REG(0)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout"];
+ *     cvmx_srio0_int_reg [label="SRIOX_INT_REG(0)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout|<zero_pkt>zero_pkt"];
  *     cvmx_ciu_block_int:srio0:e -> cvmx_srio0_int_reg [label="srio0"];
- *     cvmx_srio1_int_reg [label="SRIOX_INT_REG(1)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout"];
+ *     cvmx_srio1_int_reg [label="SRIOX_INT_REG(1)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout|<zero_pkt>zero_pkt"];
  *     cvmx_ciu_block_int:srio1:e -> cvmx_srio1_int_reg [label="srio1"];
  *     cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pin_bp>pin_bp|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<ill_pad>ill_pad"];
  *     cvmx_ciu_block_int:sli:e -> cvmx_sli_int_sum [label="sli"];
@@ -769,12 +767,12 @@ int cvmx_error_initialize_cn63xx(void)
     info.user_info          = 0;
     fail |= cvmx_error_add(&info);
 
-    /* CVMX_L2C_ERR_TDTX(0) */
+    /* CVMX_L2C_TADX_INT(0) */
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
-    info.status_mask        = 1ull<<60 /* vsbe */;
-    info.enable_addr        = 0;
-    info.enable_mask        = 0;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<0 /* l2dsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<0 /* l2dsbe */;
     info.flags              = 0;
     info.group              = CVMX_ERROR_GROUP_INTERNAL;
     info.group_index        = 0;
@@ -783,14 +781,16 @@ int cvmx_error_initialize_cn63xx(void)
     info.parent.status_mask = 1ull<<16 /* tad0 */;
     info.func               = __cvmx_error_display;
     info.user_info          = (long)
-        "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
+        "ERROR L2C_TADX_INT(0)[L2DSBE]: L2D Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
     fail |= cvmx_error_add(&info);
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
-    info.status_mask        = 1ull<<61 /* vdbe */;
-    info.enable_addr        = 0;
-    info.enable_mask        = 0;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<1 /* l2ddbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<1 /* l2ddbe */;
     info.flags              = 0;
     info.group              = CVMX_ERROR_GROUP_INTERNAL;
     info.group_index        = 0;
@@ -799,14 +799,16 @@ int cvmx_error_initialize_cn63xx(void)
     info.parent.status_mask = 1ull<<16 /* tad0 */;
     info.func               = __cvmx_error_display;
     info.user_info          = (long)
-        "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
+        "ERROR L2C_TADX_INT(0)[L2DDBE]: L2D Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
     fail |= cvmx_error_add(&info);
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
-    info.status_mask        = 1ull<<62 /* sbe */;
-    info.enable_addr        = 0;
-    info.enable_mask        = 0;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<2 /* tagsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<2 /* tagsbe */;
     info.flags              = 0;
     info.group              = CVMX_ERROR_GROUP_INTERNAL;
     info.group_index        = 0;
@@ -815,14 +817,16 @@ int cvmx_error_initialize_cn63xx(void)
     info.parent.status_mask = 1ull<<16 /* tad0 */;
     info.func               = __cvmx_error_display;
     info.user_info          = (long)
-        "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
+        "ERROR L2C_TADX_INT(0)[TAGSBE]: TAG Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
     fail |= cvmx_error_add(&info);
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
-    info.status_mask        = 1ull<<63 /* dbe */;
-    info.enable_addr        = 0;
-    info.enable_mask        = 0;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<3 /* tagdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<3 /* tagdbe */;
     info.flags              = 0;
     info.group              = CVMX_ERROR_GROUP_INTERNAL;
     info.group_index        = 0;
@@ -831,15 +835,16 @@ int cvmx_error_initialize_cn63xx(void)
     info.parent.status_mask = 1ull<<16 /* tad0 */;
     info.func               = __cvmx_error_display;
     info.user_info          = (long)
-        "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
+        "ERROR L2C_TADX_INT(0)[TAGDBE]: TAG Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
     fail |= cvmx_error_add(&info);
 
-    /* CVMX_L2C_ERR_TTGX(0) */
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
-    info.status_mask        = 1ull<<61 /* noway */;
-    info.enable_addr        = 0;
-    info.enable_mask        = 0;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<4 /* vbfsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<4 /* vbfsbe */;
     info.flags              = 0;
     info.group              = CVMX_ERROR_GROUP_INTERNAL;
     info.group_index        = 0;
@@ -848,27 +853,16 @@ int cvmx_error_initialize_cn63xx(void)
     info.parent.status_mask = 1ull<<16 /* tad0 */;
     info.func               = __cvmx_error_display;
     info.user_info          = (long)
-        "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
-        "    L2C sets NOWAY during its processing of a\n"
-        "    transaction whenever it needed/wanted to allocate\n"
-        "    a WAY in the L2 cache, but was unable to. NOWAY==1\n"
-        "    is (generally) not an indication that L2C failed to\n"
-        "    complete transactions. Rather, it is a hint of\n"
-        "    possible performance degradation. (For example, L2C\n"
-        "    must read-modify-write DRAM for every transaction\n"
-        "    that updates some, but not all, of the bytes in a\n"
-        "    cache block, misses in the L2 cache, and cannot\n"
-        "    allocate a WAY.) There is one \"failure\" case where\n"
-        "    L2C will set NOWAY: when it cannot leave a block\n"
-        "    locked in the L2 cache as part of a LCKL2\n"
-        "    transaction.\n";
+        "ERROR L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VSBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
     fail |= cvmx_error_add(&info);
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
-    info.status_mask        = 1ull<<62 /* sbe */;
-    info.enable_addr        = 0;
-    info.enable_mask        = 0;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<5 /* vbfdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<5 /* vbfdbe */;
     info.flags              = 0;
     info.group              = CVMX_ERROR_GROUP_INTERNAL;
     info.group_index        = 0;
@@ -877,14 +871,16 @@ int cvmx_error_initialize_cn63xx(void)
     info.parent.status_mask = 1ull<<16 /* tad0 */;
     info.func               = __cvmx_error_display;
     info.user_info          = (long)
-        "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
+        "ERROR L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VDBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
     fail |= cvmx_error_add(&info);
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
-    info.status_mask        = 1ull<<63 /* dbe */;
-    info.enable_addr        = 0;
-    info.enable_mask        = 0;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<6 /* noway */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<6 /* noway */;
     info.flags              = 0;
     info.group              = CVMX_ERROR_GROUP_INTERNAL;
     info.group_index        = 0;
@@ -893,7 +889,43 @@ int cvmx_error_initialize_cn63xx(void)
     info.parent.status_mask = 1ull<<16 /* tad0 */;
     info.func               = __cvmx_error_display;
     info.user_info          = (long)
-        "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n";
+        "ERROR L2C_TADX_INT(0)[NOWAY]: No way available interrupt\n"
+        "    Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<7 /* rddislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<7 /* rddislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[RDDISLMC]: Illegal Read  to Disabled LMC Error\n"
+        "    A DRAM read  arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<8 /* wrdislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<8 /* wrdislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
+        "    A DRAM write arrived before the LMC(s) were enabled\n";
     fail |= cvmx_error_add(&info);
 
     /* CVMX_IPD_INT_SUM */
@@ -1810,6 +1842,22 @@ int cvmx_error_initialize_cn63xx(void)
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
     info.status_mask        = 1ull<<4 /* synlos */;
     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
     info.enable_mask        = 1ull<<4 /* synlos_en */;
@@ -4421,7 +4469,7 @@ int cvmx_error_initialize_cn63xx(void)
     info.enable_addr        = CVMX_DFM_FNT_IENA;
     info.enable_mask        = 1ull<<0 /* sbe_intena */;
     info.flags              = 0;
-    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group              = CVMX_ERROR_GROUP_DFM;
     info.group_index        = 0;
     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
@@ -4439,7 +4487,7 @@ int cvmx_error_initialize_cn63xx(void)
     info.enable_addr        = CVMX_DFM_FNT_IENA;
     info.enable_mask        = 1ull<<1 /* dbe_intena */;
     info.flags              = 0;
-    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group              = CVMX_ERROR_GROUP_DFM;
     info.group_index        = 0;
     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
@@ -6249,6 +6297,22 @@ int cvmx_error_initialize_cn63xx(void)
         "    See SRIOMAINT(0..1)_DROP_PACKET\n";
     fail |= cvmx_error_add(&info);
 
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<26 /* zero_pkt */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<26 /* zero_pkt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[ZERO_PKT]: Received Incoming SRIO Zero byte packet (Pass 2)\n";
+    fail |= cvmx_error_add(&info);
+
     /* CVMX_SRIOX_INT_REG(1) */
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_SRIOX_INT_REG(1);
@@ -6486,6 +6550,22 @@ int cvmx_error_initialize_cn63xx(void)
         "    See SRIOMAINT(0..1)_DROP_PACKET\n";
     fail |= cvmx_error_add(&info);
 
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<26 /* zero_pkt */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<26 /* zero_pkt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[ZERO_PKT]: Received Incoming SRIO Zero byte packet (Pass 2)\n";
+    fail |= cvmx_error_add(&info);
+
     /* CVMX_PEXP_SLI_INT_SUM */
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn63xxp1.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn63xxp1.c
index ce80164..092669e 100644
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn63xxp1.c
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn63xxp1.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -86,7 +86,7 @@
  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
  *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
  *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
  *     cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
@@ -1778,6 +1778,22 @@ int cvmx_error_initialize_cn63xxp1(void)
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
     info.status_mask        = 1ull<<4 /* synlos */;
     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
     info.enable_mask        = 1ull<<4 /* synlos_en */;
@@ -4117,7 +4133,7 @@ int cvmx_error_initialize_cn63xxp1(void)
     info.enable_addr        = CVMX_DFM_FNT_IENA;
     info.enable_mask        = 1ull<<0 /* sbe_intena */;
     info.flags              = 0;
-    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group              = CVMX_ERROR_GROUP_DFM;
     info.group_index        = 0;
     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
@@ -4135,7 +4151,7 @@ int cvmx_error_initialize_cn63xxp1(void)
     info.enable_addr        = CVMX_DFM_FNT_IENA;
     info.enable_mask        = 1ull<<1 /* dbe_intena */;
     info.flags              = 0;
-    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group              = CVMX_ERROR_GROUP_DFM;
     info.group_index        = 0;
     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn66xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn66xx.c
new file mode 100644
index 0000000..b8efcf5
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn66xx.c
@@ -0,0 +1,9166 @@
+/***********************license start***************
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Automatically generated error messages for cn66xx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ * <hr><h2>Error tree for CN66XX</h2>
+ * @dot
+ * digraph cn66xx
+ * {
+ *     rankdir=LR;
+ *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
+ *     edge [fontsize=7, font=helvitica];
+ *     cvmx_root [label="ROOT|<root>root"];
+ *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
+ *     cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
+ *     cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
+ *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
+ *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1|<nand>nand"];
+ *     cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
+ *     cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
+ *     cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"];
+ *     cvmx_ciu_int_sum1:nand:e -> cvmx_ndf_int [label="nand"];
+ *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
+ *     cvmx_ciu_block_int [label="CIU_BLOCK_INT|<l2c>l2c|<ipd>ipd|<pow>pow|<rad>rad|<asxpcs1>asxpcs1|<asxpcs0>asxpcs0|<pip>pip|<pko>pko|<pem0>pem0|<pem1>pem1|<fpa>fpa|<gmx1>gmx1|<mio>mio|<dfm>dfm|<tim>tim|<lmc0>lmc0|<key>key|<gmx0>gmx0|<iob>iob|<usb>usb|<agl>agl|<zip>zip|<dfa>dfa|<srio0>srio0|<sli>sli|<dpi>dpi"];
+ *     cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<bigwr>bigwr|<bigrd>bigrd|<tad0>tad0"];
+ *     cvmx_l2c_tad0_int [label="L2C_TADX_INT(0)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_tad0_int [label="tad0"];
+ *     cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
+ *     cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
+ *     cvmx_ciu_block_int:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
+ *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
+ *     cvmx_ciu_block_int:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
+ *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
+ *     cvmx_ciu_block_int:pow:e -> cvmx_pow_ecc_err [label="pow"];
+ *     cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
+ *     cvmx_ciu_block_int:rad:e -> cvmx_rad_reg_error [label="rad"];
+ *     cvmx_pcs1_int0_reg [label="PCSX_INTX_REG(0,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int0_reg [label="asxpcs1"];
+ *     cvmx_pcs1_int1_reg [label="PCSX_INTX_REG(1,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int1_reg [label="asxpcs1"];
+ *     cvmx_pcs1_int2_reg [label="PCSX_INTX_REG(2,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int2_reg [label="asxpcs1"];
+ *     cvmx_pcs1_int3_reg [label="PCSX_INTX_REG(3,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int3_reg [label="asxpcs1"];
+ *     cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcsx1_int_reg [label="asxpcs1"];
+ *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
+ *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
+ *     cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
+ *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
+ *     cvmx_ciu_block_int:pko:e -> cvmx_pko_reg_error [label="pko"];
+ *     cvmx_pem0_int_sum [label="PEMX_INT_SUM(0)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
+ *     cvmx_pem0_dbg_info [label="PEMX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
+ *     cvmx_pem0_int_sum:exc:e -> cvmx_pem0_dbg_info [label="exc"];
+ *     cvmx_ciu_block_int:pem0:e -> cvmx_pem0_int_sum [label="pem0"];
+ *     cvmx_pem1_int_sum [label="PEMX_INT_SUM(1)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
+ *     cvmx_pem1_dbg_info [label="PEMX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
+ *     cvmx_pem1_int_sum:exc:e -> cvmx_pem1_dbg_info [label="exc"];
+ *     cvmx_ciu_block_int:pem1:e -> cvmx_pem1_int_sum [label="pem1"];
+ *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr|<pool0th>pool0th|<pool1th>pool1th|<pool2th>pool2th|<pool3th>pool3th|<pool4th>pool4th|<pool5th>pool5th|<pool6th>pool6th|<pool7th>pool7th|<free0>free0|<free1>free1|<free2>free2|<free3>free3|<free4>free4|<free5>free5|<free6>free6|<free7>free7|<paddr_e>paddr_e"];
+ *     cvmx_ciu_block_int:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
+ *     cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
+ *     cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
+ *     cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
+ *     cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
+ *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
+ *     cvmx_ciu_block_int:mio:e -> cvmx_mio_boot_err [label="mio"];
+ *     cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<rst_link2>rst_link2|<rst_link3>rst_link3|<perst0>perst0|<perst1>perst1"];
+ *     cvmx_ciu_block_int:mio:e -> cvmx_mio_rst_int [label="mio"];
+ *     cvmx_dfm_fnt_stat [label="DFM_FNT_STAT|<sbe_err>sbe_err|<dbe_err>dbe_err"];
+ *     cvmx_ciu_block_int:dfm:e -> cvmx_dfm_fnt_stat [label="dfm"];
+ *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
+ *     cvmx_ciu_block_int:tim:e -> cvmx_tim_reg_error [label="tim"];
+ *     cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
+ *     cvmx_ciu_block_int:lmc0:e -> cvmx_lmc0_int [label="lmc0"];
+ *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
+ *     cvmx_ciu_block_int:key:e -> cvmx_key_int_sum [label="key"];
+ *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
+ *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
+ *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
+ *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
+ *     cvmx_ciu_block_int:iob:e -> cvmx_iob_int_sum [label="iob"];
+ *     cvmx_uctl0_int_reg [label="UCTLX_INT_REG(0)|<pp_psh_f>pp_psh_f|<er_psh_f>er_psh_f|<or_psh_f>or_psh_f|<cf_psh_f>cf_psh_f|<wb_psh_f>wb_psh_f|<wb_pop_e>wb_pop_e|<oc_ovf_e>oc_ovf_e|<ec_ovf_e>ec_ovf_e"];
+ *     cvmx_ciu_block_int:usb:e -> cvmx_uctl0_int_reg [label="usb"];
+ *     cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
+ *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
+ *     cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
+ *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
+ *     cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
+ *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
+ *     cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
+ *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
+ *     cvmx_ciu_block_int:zip:e -> cvmx_zip_error [label="zip"];
+ *     cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr"];
+ *     cvmx_ciu_block_int:dfa:e -> cvmx_dfa_error [label="dfa"];
+ *     cvmx_srio0_int_reg [label="SRIOX_INT_REG(0)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout|<zero_pkt>zero_pkt"];
+ *     cvmx_ciu_block_int:srio0:e -> cvmx_srio0_int_reg [label="srio0"];
+ *     cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<m2_up_b0>m2_up_b0|<m2_up_wi>m2_up_wi|<m2_un_b0>m2_un_b0|<m2_un_wi>m2_un_wi|<m3_up_b0>m3_up_b0|<m3_up_wi>m3_up_wi|<m3_un_b0>m3_un_b0|<m3_un_wi>m3_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pin_bp>pin_bp|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<sprt2_err>sprt2_err|<sprt3_err>sprt3_err|<ill_pad>ill_pad"];
+ *     cvmx_ciu_block_int:sli:e -> cvmx_sli_int_sum [label="sli"];
+ *     cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst|<sprt2_rst>sprt2_rst|<sprt3_rst>sprt3_rst"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
+ *     cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
+ *     cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
+ *     cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
+ *     cvmx_pcs1_int0_reg -> cvmx_pcs1_int1_reg [style=invis];
+ *     cvmx_pcs1_int1_reg -> cvmx_pcs1_int2_reg [style=invis];
+ *     cvmx_pcs1_int2_reg -> cvmx_pcs1_int3_reg [style=invis];
+ *     cvmx_pcs1_int3_reg -> cvmx_pcsx1_int_reg [style=invis];
+ *     cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
+ *     cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
+ *     cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
+ *     cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
+ *     cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
+ *     cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
+ *     cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
+ *     cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
+ *     cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
+ *     cvmx_mio_boot_err -> cvmx_mio_rst_int [style=invis];
+ *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
+ *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
+ *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
+ *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
+ *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
+ *     cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
+ *     cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
+ *     cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
+ *     cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
+ *     cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
+ *     cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
+ *     cvmx_root:root:e -> cvmx_ciu_block_int [label="root"];
+ * }
+ * @enddot
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-csr-typedefs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#endif
+
+int cvmx_error_initialize_cn66xx(void);
+
+int cvmx_error_initialize_cn66xx(void)
+{
+    cvmx_error_info_t info;
+    int fail = 0;
+
+    /* CVMX_CIU_INTX_SUM0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INTX_SUM0(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIXX_ISR(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<0 /* odblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<0 /* ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(OVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
+        "    future ODBELL writes don't exceed the size of the\n"
+        "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
+        "    SW must reclaim O-Ring Entries by writing to the\n"
+        "    MIX_ORCNT[ORCNT]. .\n"
+        "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the O-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<1 /* idblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<1 /* ivfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(IVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
+        "    future IDBELL writes don't exceed the size of the\n"
+        "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
+        "    SW must reclaim I-Ring Entries by keeping track of the\n"
+        "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
+        "    total #packets(not IRing Entries) and SW must further\n"
+        "    keep track of the # of I-Ring Entries associated with\n"
+        "    each packet as they are processed.\n"
+        "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the I-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<4 /* data_drp */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<4 /* data_drpena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
+        "    If this does occur, the DATA_DRP is set and the\n"
+        "    CIU_INTx_SUM0,4[MII] bits are set.\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
+        "    interrupt is reported for this event.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<5 /* irun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<5 /* irunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
+        "    NOTE: If an IRUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<6 /* orun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<6 /* orunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
+        "    NOTE: If an ORUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU_INT_SUM1 */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INT_SUM1;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIXX_ISR(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<0 /* odblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<0 /* ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(OVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
+        "    future ODBELL writes don't exceed the size of the\n"
+        "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
+        "    SW must reclaim O-Ring Entries by writing to the\n"
+        "    MIX_ORCNT[ORCNT]. .\n"
+        "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the O-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<1 /* idblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<1 /* ivfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(IVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
+        "    future IDBELL writes don't exceed the size of the\n"
+        "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
+        "    SW must reclaim I-Ring Entries by keeping track of the\n"
+        "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
+        "    total #packets(not IRing Entries) and SW must further\n"
+        "    keep track of the # of I-Ring Entries associated with\n"
+        "    each packet as they are processed.\n"
+        "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the I-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<4 /* data_drp */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<4 /* data_drpena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
+        "    If this does occur, the DATA_DRP is set and the\n"
+        "    CIU_INTx_SUM0,4[MII] bits are set.\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
+        "    interrupt is reported for this event.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<5 /* irun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<5 /* irunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
+        "    NOTE: If an IRUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<6 /* orun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<6 /* orunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
+        "    NOTE: If an ORUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NDF_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<2 /* wdog */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<2 /* wdog */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<3 /* sm_bad */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<3 /* sm_bad */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<4 /* ecc_1bit */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<4 /* ecc_1bit */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<5 /* ecc_mult */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<5 /* ecc_mult */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<6 /* ovrf */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<6 /* ovrf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n"
+        "    fatal error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU_BLOCK_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_BLOCK_INT;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<0 /* holerd */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<0 /* holerd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<1 /* holewr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<1 /* holewr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<2 /* vrtwr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<2 /* vrtwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
+        "    Set when L2C_VRT_MEM blocked a store.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<3 /* vrtidrng */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<3 /* vrtidrng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
+        "    Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
+        "    store.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<4 /* vrtadrng */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<4 /* vrtadrng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
+        "    Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
+        "    store.\n"
+        "    L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<5 /* vrtpe */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<5 /* vrtpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
+        "    Whenever an L2C_VRT_MEM read finds a parity error,\n"
+        "    that L2C_VRT_MEM cannot cause stores to be blocked.\n"
+        "    Software should correct the error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<6 /* bigwr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<6 /* bigwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[BIGWR]: Write reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<7 /* bigrd */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<7 /* bigrd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[BIGRD]: Read reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_TADX_INT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<0 /* l2dsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<0 /* l2dsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[L2DSBE]: L2D Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<1 /* l2ddbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<1 /* l2ddbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[L2DDBE]: L2D Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<2 /* tagsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<2 /* tagsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[TAGSBE]: TAG Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<3 /* tagdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<3 /* tagdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[TAGDBE]: TAG Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<4 /* vbfsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<4 /* vbfsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VSBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<5 /* vbfdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<5 /* vbfdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VDBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<6 /* noway */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<6 /* noway */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[NOWAY]: No way available interrupt\n"
+        "    Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<7 /* rddislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<7 /* rddislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[RDDISLMC]: Illegal Read  to Disabled LMC Error\n"
+        "    A DRAM read  arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<8 /* wrdislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<8 /* wrdislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
+        "    A DRAM write arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TDTX(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<60 /* vsbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<61 /* vdbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TTGX(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<61 /* noway */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
+        "    L2C sets NOWAY during its processing of a\n"
+        "    transaction whenever it needed/wanted to allocate\n"
+        "    a WAY in the L2 cache, but was unable to. NOWAY==1\n"
+        "    is (generally) not an indication that L2C failed to\n"
+        "    complete transactions. Rather, it is a hint of\n"
+        "    possible performance degradation. (For example, L2C\n"
+        "    must read-modify-write DRAM for every transaction\n"
+        "    that updates some, but not all, of the bytes in a\n"
+        "    cache block, misses in the L2 cache, and cannot\n"
+        "    allocate a WAY.) There is one \"failure\" case where\n"
+        "    L2C will set NOWAY: when it cannot leave a block\n"
+        "    locked in the L2 cache as part of a LCKL2\n"
+        "    transaction.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IPD_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<0 /* prc_par0 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* prc_par0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+        "    [31:0] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<1 /* prc_par1 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* prc_par1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+        "    [63:32] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<2 /* prc_par2 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* prc_par2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+        "    [95:64] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<3 /* prc_par3 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* prc_par3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+        "    [127:96] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<4 /* bp_sub */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* bp_sub */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+        "    supplied illegal value.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* dc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<6 /* cc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* cc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<7 /* c_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* c_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<8 /* d_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* d_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<9 /* bc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* bc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_POW_ECC_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<0 /* sbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<2 /* sbe_ie */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<1 /* dbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<3 /* dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<12 /* rpe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<13 /* rpe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 0x1fffull<<16 /* iop */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_iop;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_RAD_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_RAD_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_RAD_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<14 /* rad */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<6 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<6 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<6 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PIP_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<3 /* prtnxa */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<3 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<4 /* badtag */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<4 /* badtag */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<5 /* skprunt */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<5 /* skprunt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+        "    This interrupt can occur with received PARTIAL\n"
+        "    packets that are truncated to SKIP bytes or\n"
+        "    smaller.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<6 /* todoovr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<6 /* todoovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<7 /* feperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<7 /* feperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<8 /* beperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<8 /* beperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<12 /* punyerr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<12 /* punyerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
+        "    stripping in IPD is enable\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PKO_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* parity */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* parity */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<1 /* doorbell */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<1 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<2 /* currzero */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<2 /* currzero */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_INT_SUM(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<1 /* se */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<1 /* se */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[SE]: System Error, RC Mode Only.\n"
+        "    (cfg_sys_err_rc)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<4 /* up_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<4 /* up_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<5 /* up_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<5 /* up_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<6 /* up_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<6 /* up_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UP_BX]: Received P-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<7 /* un_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<7 /* un_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<8 /* un_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<8 /* un_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<9 /* un_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<9 /* un_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UN_BX]: Received N-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<11 /* rdlk */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<11 /* rdlk */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[RDLK]: Received Read Lock TLP.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<12 /* crs_er */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<12 /* crs_er */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<13 /* crs_dr */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<13 /* crs_dr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_DBG_INFO(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<0 /* spoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<0 /* spoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
+        "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<2 /* rtlplle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<2 /* rtlplle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
+        "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<3 /* recrce */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<3 /* recrce */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
+        "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<4 /* rpoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<4 /* rpoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
+        "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<5 /* rcemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<5 /* rcemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+        "    pedc_radm_correctable_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<6 /* rnfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<6 /* rnfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_nonfatal_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<7 /* rfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<7 /* rfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_fatal_err\n"
+        "    Bit set when a message with ERR_FATAL is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<8 /* rpmerc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<8 /* rpmerc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
+        "    pedc_radm_pm_pme\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<9 /* rptamrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<9 /* rptamrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+        "    (RC Mode only)\n"
+        "    pedc_radm_pm_to_ack\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<10 /* rumep */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<10 /* rumep */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+        "    pedc_radm_msg_unlock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<11 /* rvdm */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<11 /* rvdm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
+        "    pedc_radm_vendor_msg\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<12 /* acto */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<12 /* acto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
+        "    pedc_radm_cpl_timeout\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<13 /* rte */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<13 /* rte */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
+        "    xdlh_replay_timeout_err\n"
+        "    This bit is set when the REPLAY_TIMER expires in\n"
+        "    the PCIE core. The probability of this bit being\n"
+        "    set will increase with the traffic load.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<14 /* mre */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<14 /* mre */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
+        "    xdlh_replay_num_rlover_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<15 /* rdwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<15 /* rdwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+        "    rdlh_bad_dllp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<16 /* rtwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<16 /* rtwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
+        "    rdlh_bad_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<17 /* dpeoosd */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<17 /* dpeoosd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+        "    rdlh_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<18 /* fcpvwt */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<18 /* fcpvwt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+        "    rtlh_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<19 /* rpe */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<19 /* rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
+        "    (RxStatus = 3b100) or disparity error\n"
+        "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+        "    be asserted.\n"
+        "    rmlh_rcvd_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<20 /* fcuv */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<20 /* fcuv */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
+        "    int_xadm_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<21 /* rqo */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<21 /* rqo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
+        "    flow control advertisements are ignored\n"
+        "    radm_qoverflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<22 /* rauc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<22 /* rauc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
+        "    radm_unexp_cpl_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<23 /* racur */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<23 /* racur */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
+        "    radm_rcvd_cpl_ur\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<24 /* racca */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<24 /* racca */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
+        "    radm_rcvd_cpl_ca\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<25 /* caar */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<25 /* caar */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
+        "    radm_rcvd_ca_req\n"
+        "    This bit will never be set because Octeon does\n"
+        "    not generate Completer Aborts.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<26 /* rarwdns */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<26 /* rarwdns */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
+        "    radm_rcvd_ur_req\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<27 /* ramtlp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<27 /* ramtlp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
+        "    radm_mlf_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<28 /* racpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<28 /* racpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
+        "    radm_rcvd_cpl_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<29 /* rawwpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<29 /* rawwpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
+        "    radm_rcvd_wreq_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<30 /* ecrc_e */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<30 /* ecrc_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
+        "    radm_ecrc_err\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_INT_SUM(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<1 /* se */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<1 /* se */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[SE]: System Error, RC Mode Only.\n"
+        "    (cfg_sys_err_rc)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<4 /* up_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<4 /* up_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<5 /* up_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<5 /* up_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<6 /* up_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<6 /* up_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UP_BX]: Received P-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<7 /* un_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<7 /* un_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<8 /* un_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<8 /* un_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<9 /* un_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<9 /* un_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UN_BX]: Received N-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<11 /* rdlk */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<11 /* rdlk */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[RDLK]: Received Read Lock TLP.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<12 /* crs_er */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<12 /* crs_er */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<13 /* crs_dr */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<13 /* crs_dr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_DBG_INFO(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<0 /* spoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<0 /* spoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
+        "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<2 /* rtlplle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<2 /* rtlplle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
+        "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<3 /* recrce */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<3 /* recrce */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
+        "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<4 /* rpoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<4 /* rpoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
+        "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<5 /* rcemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<5 /* rcemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+        "    pedc_radm_correctable_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<6 /* rnfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<6 /* rnfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_nonfatal_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<7 /* rfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<7 /* rfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_fatal_err\n"
+        "    Bit set when a message with ERR_FATAL is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<8 /* rpmerc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<8 /* rpmerc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
+        "    pedc_radm_pm_pme\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<9 /* rptamrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<9 /* rptamrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+        "    (RC Mode only)\n"
+        "    pedc_radm_pm_to_ack\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<10 /* rumep */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<10 /* rumep */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+        "    pedc_radm_msg_unlock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<11 /* rvdm */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<11 /* rvdm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
+        "    pedc_radm_vendor_msg\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<12 /* acto */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<12 /* acto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
+        "    pedc_radm_cpl_timeout\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<13 /* rte */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<13 /* rte */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
+        "    xdlh_replay_timeout_err\n"
+        "    This bit is set when the REPLAY_TIMER expires in\n"
+        "    the PCIE core. The probability of this bit being\n"
+        "    set will increase with the traffic load.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<14 /* mre */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<14 /* mre */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
+        "    xdlh_replay_num_rlover_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<15 /* rdwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<15 /* rdwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+        "    rdlh_bad_dllp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<16 /* rtwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<16 /* rtwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
+        "    rdlh_bad_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<17 /* dpeoosd */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<17 /* dpeoosd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+        "    rdlh_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<18 /* fcpvwt */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<18 /* fcpvwt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+        "    rtlh_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<19 /* rpe */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<19 /* rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
+        "    (RxStatus = 3b100) or disparity error\n"
+        "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+        "    be asserted.\n"
+        "    rmlh_rcvd_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<20 /* fcuv */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<20 /* fcuv */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
+        "    int_xadm_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<21 /* rqo */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<21 /* rqo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
+        "    flow control advertisements are ignored\n"
+        "    radm_qoverflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<22 /* rauc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<22 /* rauc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
+        "    radm_unexp_cpl_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<23 /* racur */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<23 /* racur */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
+        "    radm_rcvd_cpl_ur\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<24 /* racca */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<24 /* racca */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
+        "    radm_rcvd_cpl_ca\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<25 /* caar */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<25 /* caar */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
+        "    radm_rcvd_ca_req\n"
+        "    This bit will never be set because Octeon does\n"
+        "    not generate Completer Aborts.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<26 /* rarwdns */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<26 /* rarwdns */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
+        "    radm_rcvd_ur_req\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<27 /* ramtlp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<27 /* ramtlp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
+        "    radm_mlf_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<28 /* racpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<28 /* racpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
+        "    radm_rcvd_cpl_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<29 /* rawwpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<29 /* rawwpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
+        "    radm_rcvd_wreq_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<30 /* ecrc_e */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<30 /* ecrc_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
+        "    radm_ecrc_err\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_FPA_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<0 /* fed0_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* fed0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<1 /* fed0_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* fed0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<2 /* fed1_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* fed1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<3 /* fed1_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* fed1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<4 /* q0_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* q0_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<5 /* q0_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* q0_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<6 /* q0_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* q0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<7 /* q1_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* q1_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<8 /* q1_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* q1_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<9 /* q1_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* q1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<10 /* q2_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* q2_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<11 /* q2_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* q2_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<12 /* q2_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* q2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<13 /* q3_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* q3_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<14 /* q3_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* q3_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<15 /* q3_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* q3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<16 /* q4_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* q4_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<17 /* q4_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* q4_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<18 /* q4_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* q4_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<19 /* q5_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* q5_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<20 /* q5_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* q5_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<21 /* q5_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* q5_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<22 /* q6_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* q6_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<23 /* q6_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* q6_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<24 /* q6_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* q6_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<25 /* q7_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* q7_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<26 /* q7_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* q7_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<27 /* q7_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* q7_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<28 /* pool0th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<28 /* pool0th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL0TH]: Set when FPA_QUE0_AVAILABLE is equal to\n"
+        "    FPA_POOL`_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<29 /* pool1th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<29 /* pool1th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL1TH]: Set when FPA_QUE1_AVAILABLE is equal to\n"
+        "    FPA_POOL1_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<30 /* pool2th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<30 /* pool2th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL2TH]: Set when FPA_QUE2_AVAILABLE is equal to\n"
+        "    FPA_POOL2_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<31 /* pool3th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<31 /* pool3th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL3TH]: Set when FPA_QUE3_AVAILABLE is equal to\n"
+        "    FPA_POOL3_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<32 /* pool4th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<32 /* pool4th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL4TH]: Set when FPA_QUE4_AVAILABLE is equal to\n"
+        "    FPA_POOL4_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<33 /* pool5th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<33 /* pool5th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL5TH]: Set when FPA_QUE5_AVAILABLE is equal to\n"
+        "    FPA_POOL5_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<34 /* pool6th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<34 /* pool6th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL6TH]: Set when FPA_QUE6_AVAILABLE is equal to\n"
+        "    FPA_POOL6_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<35 /* pool7th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<35 /* pool7th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL7TH]: Set when FPA_QUE7_AVAILABLE is equal to\n"
+        "    FPA_POOL7_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<36 /* free0 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<36 /* free0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE0]: When a pointer for POOL0 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<37 /* free1 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<37 /* free1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE1]: When a pointer for POOL1 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<38 /* free2 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<38 /* free2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE2]: When a pointer for POOL2 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<39 /* free3 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<39 /* free3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE3]: When a pointer for POOL3 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<40 /* free4 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<40 /* free4 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE4]: When a pointer for POOL4 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<41 /* free5 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<41 /* free5 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE5]: When a pointer for POOL5 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<42 /* free6 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<42 /* free6 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE6]: When a pointer for POOL6 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<43 /* free7 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<43 /* free7 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE7]: When a pointer for POOL7 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<49 /* paddr_e */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<49 /* paddr_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[PADDR_E]: Set when a pointer address does not fall in the\n"
+        "    address range for a pool specified by\n"
+        "    FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In SGMII, one bit per port\n"
+        "    In XAUI, only port0 is used\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n"
+        "    The common FIFO to SGMII and XAUI had an overflow\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 0xfull<<20 /* ptp_lost */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 0xfull<<20 /* ptp_lost */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[PTP_LOST]: A packet with a PTP request was not able to be\n"
+        "    sent due to XSCOL\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_BOOT_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<0 /* adr_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<0 /* adr_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<1 /* wait_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<1 /* wait_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_RST_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<0 /* rst_link0 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<0 /* rst_link0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n"
+        "    MIO_RST_CNTL0[RST_LINK]=0.  Software must assert\n"
+        "    then de-assert CIU_SOFT_PRST[SOFT_PRST]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<1 /* rst_link1 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<1 /* rst_link1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n"
+        "    MIO_RST_CNTL1[RST_LINK]=0.  Software must assert\n"
+        "    then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<2 /* rst_link2 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<2 /* rst_link2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[RST_LINK2]: A controller2 link-down/hot-reset occurred while\n"
+        "    MIO_RST_CNTL2[RST_LINK]=0.  Software must assert\n"
+        "    then de-assert CIU_SOFT_PRST2[SOFT_PRST]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<3 /* rst_link3 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<3 /* rst_link3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[RST_LINK3]: A controller3 link-down/hot-reset occurred while\n"
+        "    MIO_RST_CNTL3[RST_LINK]=0.  Software must assert\n"
+        "    then de-assert CIU_SOFT_PRST3[SOFT_PRST]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<8 /* perst0 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<8 /* perst0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CNTL0[RST_RCV]=1\n"
+        "    and MIO_RST_CNTL0[RST_CHIP]=0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<9 /* perst1 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<9 /* perst1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CNTL1[RST_RCV]=1\n"
+        "    and MIO_RST_CNTL1[RST_CHIP]=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DFM_FNT_STAT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFM_FNT_STAT;
+    info.status_mask        = 1ull<<0 /* sbe_err */;
+    info.enable_addr        = CVMX_DFM_FNT_IENA;
+    info.enable_mask        = 1ull<<0 /* sbe_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_DFM;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<40 /* dfm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFM_FNT_STAT[SBE_ERR]: Single bit error detected(corrected) during\n"
+        "    Memory Read.\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFM_FNT_STAT;
+    info.status_mask        = 1ull<<1 /* dbe_err */;
+    info.enable_addr        = CVMX_DFM_FNT_IENA;
+    info.enable_mask        = 1ull<<1 /* dbe_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_DFM;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<40 /* dfm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFM_FNT_STAT[DBE_ERR]: Double bit error detected(uncorrectable) during\n"
+        "    Memory Read.\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_TIM_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_TIM_REG_ERROR;
+    info.status_mask        = 0xffffull<<0 /* mask */;
+    info.enable_addr        = CVMX_TIM_REG_INT_MASK;
+    info.enable_mask        = 0xffffull<<0 /* mask */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<11 /* tim */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_INT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 0xfull<<1 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<1 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 1ull<<0 /* nxm_wr_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* intr_nxm_wr_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 0xfull<<5 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<2 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_KEY_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<0 /* ked0_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* ked0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<1 /* ked0_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* ked0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<2 /* ked1_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* ked1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<3 /* ked1_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* ked1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In SGMII, one bit per port\n"
+        "    In XAUI, only port0 is used\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
+        "    The common FIFO to SGMII and XAUI had an overflow\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<20 /* ptp_lost */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<20 /* ptp_lost */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n"
+        "    sent due to XSCOL\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IOB_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<0 /* np_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* np_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<1 /* np_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* np_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<2 /* p_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* p_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<3 /* p_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* p_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<4 /* np_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* np_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<5 /* p_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* p_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_UCTLX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pp_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<0 /* pp_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[PP_PSH_F]: PP Access FIFO  Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* er_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<1 /* er_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[ER_PSH_F]: EHCI Read Buffer FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* or_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<2 /* or_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[OR_PSH_F]: OHCI Read Buffer FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* cf_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<3 /* cf_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[CF_PSH_F]: Command FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* wb_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<4 /* wb_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[WB_PSH_F]: Write Buffer FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* wb_pop_e */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<5 /* wb_pop_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[WB_POP_E]: Write Buffer FIFO Poped When Empty\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* oc_ovf_e */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<6 /* oc_ovf_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[OC_OVF_E]: Ohci Commit OVerFlow Error\n"
+        "    When the error happenes, the whole NCB system needs\n"
+        "    to be reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<7 /* ec_ovf_e */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<7 /* ec_ovf_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[EC_OVF_E]: Ehci Commit OVerFlow Error\n"
+        "    When the error happenes, the whole NCB system needs\n"
+        "    to be reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_BAD_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<32 /* ovrflw */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<33 /* txpop */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<34 /* txpsh */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<35 /* ovrflw1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<36 /* txpop1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<37 /* txpsh1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 0x3ull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 0x3ull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In MII/RGMII, one bit per port\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_RXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_RXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_TX_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 0x3ull<<2 /* undflw */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 0x3ull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ZIP_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ZIP_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_ZIP_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<7 /* zip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DFA_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 1ull<<0 /* dblovf */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 1ull<<0 /* dblina */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
+        "    When set, the 20b accumulated doorbell register\n"
+        "    had overflowed (SW wrote too many doorbell requests).\n"
+        "    If the DBLINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    NOTE: Detection of a Doorbell Register overflow\n"
+        "    is a catastrophic error which may leave the DFA\n"
+        "    HW in an unrecoverable state.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 0x7ull<<1 /* dc0perr */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 0x7ull<<1 /* dc0pena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DC0PERR]: RAM[3:1] Parity Error Detected from Node Cluster #0\n"
+        "    See also DFA_DTCFADR register which contains the\n"
+        "    failing addresses for the internal node cache RAMs.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_SRIOX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* bar_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<4 /* bar_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* deny_wr */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<5 /* deny_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* sli_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<6 /* sli_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[SLI_ERR]: Unsupported S2M Transaction Received.\n"
+        "    See SRIO(0,2..3)_INT_INFO[1:0]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<9 /* mce_rx */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<9 /* mce_rx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[MCE_RX]: Incoming Multicast Event Symbol\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<12 /* log_erb */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<12 /* log_erb */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n"
+        "    See SRIOMAINT(0,2..3)_ERB_LT_ERR_DET\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<13 /* phy_erb */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<13 /* phy_erb */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[PHY_ERB]: Physical Layer Error detected in ERB\n"
+        "    See SRIOMAINT*_ERB_ATTR_CAPT\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<18 /* omsg_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<18 /* omsg_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n"
+        "    See SRIO(0,2..3)_INT_INFO2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<19 /* pko_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<19 /* pko_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[PKO_ERR]: Outbound Message Received PKO Error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<20 /* rtry_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<20 /* rtry_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n"
+        "    See SRIO(0,2..3)_INT_INFO3\n"
+        "    When one or more of the segments in an outgoing\n"
+        "    message have a RTRY_ERR, SRIO will not set\n"
+        "    OMSG* after the message \"transfer\".\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<21 /* f_error */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<21 /* f_error */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<22 /* mac_buf */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<22 /* mac_buf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[MAC_BUF]: SRIO MAC Buffer CRC Error\n"
+        "    See SRIO(0,2..3)_MAC_BUFFERS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<23 /* degrad */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<23 /* degrade */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[DEGRAD]: ERB Error Rate reached Degrade Count\n"
+        "    See SRIOMAINT(0,2..3)_ERB_ERR_RATE\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<24 /* fail */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<24 /* fail */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[FAIL]: ERB Error Rate reached Fail Count\n"
+        "    See SRIOMAINT(0,2..3)_ERB_ERR_RATE\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<25 /* ttl_tout */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<25 /* ttl_tout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[TTL_TOUT]: Outgoing Packet Time to Live Timeout\n"
+        "    See SRIOMAINT(0,2..3)_DROP_PACKET\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<26 /* zero_pkt */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<26 /* zero_pkt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[ZERO_PKT]: Received Incoming SRIO Zero byte packet\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEXP_SLI_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<0 /* rml_to */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<0 /* rml_to */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n"
+        "    within 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<1 /* reserved_1_1 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<1 /* reserved_1_1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<2 /* bar0_to */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<2 /* bar0_to */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
+        "    read-data/commit in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<3 /* iob2big */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<3 /* iob2big */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 0x3ull<<6 /* reserved_6_7 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 0x3ull<<6 /* reserved_6_7 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<8 /* m0_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<8 /* m0_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<9 /* m0_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<9 /* m0_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n"
+        "    from MAC 0. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<10 /* m0_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<10 /* m0_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<11 /* m0_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<11 /* m0_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n"
+        "    from MAC 0. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<12 /* m1_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<12 /* m1_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<13 /* m1_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<13 /* m1_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n"
+        "    from MAC 1. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<14 /* m1_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<14 /* m1_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<15 /* m1_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<15 /* m1_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n"
+        "    from MAC 1. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<20 /* m2_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<20 /* m2_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M2_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 2.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<21 /* m2_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<21 /* m2_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M2_UP_WI]: Received Unsupported P-TLP for Window Register\n"
+        "    from MAC 2. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<22 /* m2_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<22 /* m2_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M2_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 2.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<23 /* m2_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<23 /* m2_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M2_UN_WI]: Received Unsupported N-TLP for Window Register\n"
+        "    from MAC 2. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<24 /* m3_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<24 /* m3_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M3_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 3.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<25 /* m3_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<25 /* m3_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M3_UP_WI]: Received Unsupported P-TLP for Window Register\n"
+        "    from MAC 3. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<26 /* m3_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<26 /* m3_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M3_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 3.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<27 /* m3_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<27 /* m3_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M3_UN_WI]: Received Unsupported N-TLP for Window Register\n"
+        "    from MAC 3. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<48 /* pidbof */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<48 /* pidbof */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
+        "    doorbell can be found in DPI_PINT_INFO[PIDBOF]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<49 /* psldbof */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<49 /* psldbof */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
+        "    doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<50 /* pout_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<50 /* pout_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n"
+        "    set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<51 /* pin_bp */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<51 /* pin_bp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PIN_BP]: Packet input count has exceeded the WMARK.\n"
+        "    See SLI_PKT_IN_BP\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<52 /* pgl_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<52 /* pgl_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n"
+        "    read this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<53 /* pdi_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<53 /* pdi_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<54 /* pop_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<54 /* pop_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n"
+        "    pointer pair this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<55 /* pins_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<55 /* pins_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<56 /* sprt0_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<56 /* sprt0_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<57 /* sprt1_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<57 /* sprt1_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<58 /* sprt2_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<58 /* sprt2_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT2_ERR]: When an error response received on SLI port 2\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<59 /* sprt3_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<59 /* sprt3_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT3_ERR]: When an error response received on SLI port 3\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<60 /* ill_pad */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<60 /* ill_pad */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n"
+        "    range of the Packet-CSR, but for an unused\n"
+        "    address.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<0 /* nderr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<0 /* nderr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n"
+        "    DPI received a NCB transaction on the outbound\n"
+        "    bus to the DPI deviceID, but the command was not\n"
+        "    recognized.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<1 /* nfovr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<1 /* nfovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n"
+        "    DPI can store upto 16 CSR request.  The FIFO will\n"
+        "    overflow if that number is exceeded.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 0xffull<<8 /* dmadbo */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 0xffull<<8 /* dmadbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n"
+        "    DPI has a 32-bit counter for each request's queue\n"
+        "    outstanding doorbell counts. Interrupt will fire\n"
+        "    if the count overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<16 /* req_badadr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<16 /* req_badadr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n"
+        "    Interrupt will fire if DPI forms an instruction\n"
+        "    fetch to the NULL pointer.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<17 /* req_badlen */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<17 /* req_badlen */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n"
+        "    Interrupt will fire if DPI forms an instruction\n"
+        "    fetch with length of zero.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<18 /* req_ovrflw */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<18 /* req_ovrflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n"
+        "    DPI tracks outstanding instructions fetches.\n"
+        "    Interrupt will fire when FIFO overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<19 /* req_undflw */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<19 /* req_undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n"
+        "    DPI tracks outstanding instructions fetches.\n"
+        "    Interrupt will fire when FIFO underflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<20 /* req_anull */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<20 /* req_anull */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n"
+        "    Fetched instruction word was 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<21 /* req_inull */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<21 /* req_inull */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n"
+        "    Next pointer was NULL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<22 /* req_badfil */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<22 /* req_badfil */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n"
+        "    Instruction fill when none outstanding.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<24 /* sprt0_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<24 /* sprt0_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<25 /* sprt1_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<25 /* sprt1_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<26 /* sprt2_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<26 /* sprt2_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT2_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<27 /* sprt3_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<27 /* sprt3_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT3_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_PKT_ERR_RSP */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_PKT_ERR_RSP;
+    info.status_mask        = 1ull<<0 /* pkterr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n"
+        "    the I/O subsystem.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_REQ_ERR_RSP */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_REQ_ERR_RSP;
+    info.status_mask        = 0xffull<<0 /* qerr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n"
+        "    ErrorResponse from the I/O subsystem.\n"
+        "    SW must clear the bit before the the cooresponding\n"
+        "    instruction queue will continue processing\n"
+        "    instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_REQ_ERR_RST */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_REQ_ERR_RST;
+    info.status_mask        = 0xffull<<0 /* qerr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n"
+        "    instruction because the source or destination\n"
+        "    was in reset.\n"
+        "    SW must clear the bit before the the cooresponding\n"
+        "    instruction queue will continue processing\n"
+        "    instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    return fail;
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn68xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn68xx.c
new file mode 100644
index 0000000..aca3fdd
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn68xx.c
@@ -0,0 +1,14045 @@
+/***********************license start***************
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Automatically generated error messages for cn68xx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ * <hr><h2>Error tree for CN68XX</h2>
+ * @dot
+ * digraph cn68xx
+ * {
+ *     rankdir=LR;
+ *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
+ *     edge [fontsize=7, font=helvitica];
+ *     cvmx_root [label="ROOT|<root>root"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt [label="CIU2_SRC_PPX_IP2_PKT(0)|<mii>mii|<agl>agl|<ilk>ilk"];
+ *     cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:mii:e -> cvmx_mix0_isr [label="mii"];
+ *     cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
+ *     cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
+ *     cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
+ *     cvmx_ilk_gbl_int [label="ILK_GBL_INT|<rxf_lnk0_perr>rxf_lnk0_perr|<rxf_lnk1_perr>rxf_lnk1_perr|<rxf_ctl_perr>rxf_ctl_perr|<rxf_pop_empty>rxf_pop_empty|<rxf_push_full>rxf_push_full"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_gbl_int [label="ilk"];
+ *     cvmx_ilk_tx0_int [label="ILK_TXX_INT(0)|<txf_err>txf_err|<bad_seq>bad_seq|<bad_pipe>bad_pipe|<stat_cnt_ovfl>stat_cnt_ovfl"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_tx0_int [label="ilk"];
+ *     cvmx_ilk_tx1_int [label="ILK_TXX_INT(1)|<txf_err>txf_err|<bad_seq>bad_seq|<bad_pipe>bad_pipe|<stat_cnt_ovfl>stat_cnt_ovfl"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_tx1_int [label="ilk"];
+ *     cvmx_ilk_rx0_int [label="ILK_RXX_INT(0)|<lane_align_fail>lane_align_fail|<crc24_err>crc24_err|<word_sync_done>word_sync_done|<lane_align_done>lane_align_done|<stat_cnt_ovfl>stat_cnt_ovfl|<lane_bad_word>lane_bad_word|<pkt_drop_rxf>pkt_drop_rxf|<pkt_drop_rid>pkt_drop_rid|<pkt_drop_sop>pkt_drop_sop"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx0_int [label="ilk"];
+ *     cvmx_ilk_rx1_int [label="ILK_RXX_INT(1)|<lane_align_fail>lane_align_fail|<crc24_err>crc24_err|<word_sync_done>word_sync_done|<lane_align_done>lane_align_done|<stat_cnt_ovfl>stat_cnt_ovfl|<lane_bad_word>lane_bad_word|<pkt_drop_rxf>pkt_drop_rxf|<pkt_drop_rid>pkt_drop_rid|<pkt_drop_sop>pkt_drop_sop"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx1_int [label="ilk"];
+ *     cvmx_ilk_rx_lne0_int [label="ILK_RX_LNEX_INT(0)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne0_int [label="ilk"];
+ *     cvmx_ilk_rx_lne1_int [label="ILK_RX_LNEX_INT(1)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne1_int [label="ilk"];
+ *     cvmx_ilk_rx_lne2_int [label="ILK_RX_LNEX_INT(2)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne2_int [label="ilk"];
+ *     cvmx_ilk_rx_lne3_int [label="ILK_RX_LNEX_INT(3)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne3_int [label="ilk"];
+ *     cvmx_ilk_rx_lne4_int [label="ILK_RX_LNEX_INT(4)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne4_int [label="ilk"];
+ *     cvmx_ilk_rx_lne5_int [label="ILK_RX_LNEX_INT(5)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne5_int [label="ilk"];
+ *     cvmx_ilk_rx_lne6_int [label="ILK_RX_LNEX_INT(6)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne6_int [label="ilk"];
+ *     cvmx_ilk_rx_lne7_int [label="ILK_RX_LNEX_INT(7)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne7_int [label="ilk"];
+ *     cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
+ *     cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
+ *     cvmx_ilk_gbl_int -> cvmx_ilk_tx0_int [style=invis];
+ *     cvmx_ilk_tx0_int -> cvmx_ilk_tx1_int [style=invis];
+ *     cvmx_ilk_tx1_int -> cvmx_ilk_rx0_int [style=invis];
+ *     cvmx_ilk_rx0_int -> cvmx_ilk_rx1_int [style=invis];
+ *     cvmx_ilk_rx1_int -> cvmx_ilk_rx_lne0_int [style=invis];
+ *     cvmx_ilk_rx_lne0_int -> cvmx_ilk_rx_lne1_int [style=invis];
+ *     cvmx_ilk_rx_lne1_int -> cvmx_ilk_rx_lne2_int [style=invis];
+ *     cvmx_ilk_rx_lne2_int -> cvmx_ilk_rx_lne3_int [style=invis];
+ *     cvmx_ilk_rx_lne3_int -> cvmx_ilk_rx_lne4_int [style=invis];
+ *     cvmx_ilk_rx_lne4_int -> cvmx_ilk_rx_lne5_int [style=invis];
+ *     cvmx_ilk_rx_lne5_int -> cvmx_ilk_rx_lne6_int [style=invis];
+ *     cvmx_ilk_rx_lne6_int -> cvmx_ilk_rx_lne7_int [style=invis];
+ *     cvmx_root:root:e -> cvmx_ciu2_src_pp0_ip2_pkt [label="root"];
+ *     cvmx_ciu2_src_pp0_ip2_rml [label="CIU2_SRC_PPX_IP2_RML(0)|<l2c>l2c|<fpa>fpa|<zip>zip|<ipd>ipd|<rad>rad|<sso>sso|<sli>sli|<key>key|<pip>pip|<dfa>dfa|<pko>pko|<dpi>dpi"];
+ *     cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<bigwr>bigwr|<bigrd>bigrd|<tad1>tad1|<tad0>tad0|<tad3>tad3|<tad2>tad2"];
+ *     cvmx_l2c_tad1_int [label="L2C_TADX_INT(1)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
+ *     cvmx_l2c_int_reg:tad1:e -> cvmx_l2c_tad1_int [label="tad1"];
+ *     cvmx_l2c_err_tdt1 [label="L2C_ERR_TDTX(1)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad1:e -> cvmx_l2c_err_tdt1 [label="tad1"];
+ *     cvmx_l2c_err_ttg1 [label="L2C_ERR_TTGX(1)|<noway>noway|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad1:e -> cvmx_l2c_err_ttg1 [label="tad1"];
+ *     cvmx_l2c_tad0_int [label="L2C_TADX_INT(0)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_tad0_int [label="tad0"];
+ *     cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
+ *     cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
+ *     cvmx_l2c_tad3_int [label="L2C_TADX_INT(3)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
+ *     cvmx_l2c_int_reg:tad3:e -> cvmx_l2c_tad3_int [label="tad3"];
+ *     cvmx_l2c_err_tdt3 [label="L2C_ERR_TDTX(3)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad3:e -> cvmx_l2c_err_tdt3 [label="tad3"];
+ *     cvmx_l2c_err_ttg3 [label="L2C_ERR_TTGX(3)|<noway>noway|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad3:e -> cvmx_l2c_err_ttg3 [label="tad3"];
+ *     cvmx_l2c_tad2_int [label="L2C_TADX_INT(2)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
+ *     cvmx_l2c_int_reg:tad2:e -> cvmx_l2c_tad2_int [label="tad2"];
+ *     cvmx_l2c_err_tdt2 [label="L2C_ERR_TDTX(2)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad2:e -> cvmx_l2c_err_tdt2 [label="tad2"];
+ *     cvmx_l2c_err_ttg2 [label="L2C_ERR_TTGX(2)|<noway>noway|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad2:e -> cvmx_l2c_err_ttg2 [label="tad2"];
+ *     cvmx_l2c_tad0_int -> cvmx_l2c_err_tdt0 [style=invis];
+ *     cvmx_l2c_err_tdt0 -> cvmx_l2c_err_ttg0 [style=invis];
+ *     cvmx_l2c_tad3_int -> cvmx_l2c_err_tdt3 [style=invis];
+ *     cvmx_l2c_err_tdt3 -> cvmx_l2c_err_ttg3 [style=invis];
+ *     cvmx_l2c_tad2_int -> cvmx_l2c_err_tdt2 [style=invis];
+ *     cvmx_l2c_err_tdt2 -> cvmx_l2c_err_ttg2 [style=invis];
+ *     cvmx_ciu2_src_pp0_ip2_rml:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
+ *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr|<pool0th>pool0th|<pool1th>pool1th|<pool2th>pool2th|<pool3th>pool3th|<pool4th>pool4th|<pool5th>pool5th|<pool6th>pool6th|<pool7th>pool7th|<free0>free0|<free1>free1|<free2>free2|<free3>free3|<free4>free4|<free5>free5|<free6>free6|<free7>free7|<free8>free8|<q8_und>q8_und|<q8_coff>q8_coff|<q8_perr>q8_perr|<pool8th>pool8th|<paddr_e>paddr_e"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
+ *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:zip:e -> cvmx_zip_error [label="zip"];
+ *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr|<sop>sop|<eop>eop|<dat>dat|<pw0_sbe>pw0_sbe|<pw0_dbe>pw0_dbe|<pw1_sbe>pw1_sbe|<pw1_dbe>pw1_dbe|<pw2_sbe>pw2_sbe|<pw2_dbe>pw2_dbe|<pw3_sbe>pw3_sbe|<pw3_dbe>pw3_dbe"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
+ *     cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:rad:e -> cvmx_rad_reg_error [label="rad"];
+ *     cvmx_sso_err [label="SSO_ERR|<iop>iop|<fidx_dbe>fidx_dbe|<idx_sbe>idx_sbe|<pnd_dbe0>pnd_dbe0|<oth_sbe1>oth_sbe1|<oth_dbe1>oth_dbe1|<oth_sbe0>oth_sbe0|<oth_dbe0>oth_dbe0|<pnd_sbe1>pnd_sbe1|<pnd_dbe1>pnd_dbe1|<pnd_sbe0>pnd_sbe0|<fpe>fpe|<awe>awe|<bfp>bfp|<idx_dbe>idx_dbe|<fidx_sbe>fidx_sbe"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:sso:e -> cvmx_sso_err [label="sso"];
+ *     cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<ill_pad>ill_pad|<pipe_err>pipe_err"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:sli:e -> cvmx_sli_int_sum [label="sli"];
+ *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:key:e -> cvmx_key_int_sum [label="key"];
+ *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:pip:e -> cvmx_pip_int_reg [label="pip"];
+ *     cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr|<dc1perr>dc1perr|<dc2perr>dc2perr|<dlc0_ovferr>dlc0_ovferr|<dlc1_ovferr>dlc1_ovferr|<dfanxm>dfanxm|<replerr>replerr"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:dfa:e -> cvmx_dfa_error [label="dfa"];
+ *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero|<loopback>loopback"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:pko:e -> cvmx_pko_reg_error [label="pko"];
+ *     cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
+ *     cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
+ *     cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
+ *     cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
+ *     cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
+ *     cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
+ *     cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
+ *     cvmx_root:root:e -> cvmx_ciu2_src_pp0_ip2_rml [label="root"];
+ *     cvmx_ciu2_src_pp0_ip2_mio [label="CIU2_SRC_PPX_IP2_MIO(0)|<rst>rst|<nand>nand|<mio>mio"];
+ *     cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<perst0>perst0|<perst1>perst1"];
+ *     cvmx_ciu2_src_pp0_ip2_mio:rst:e -> cvmx_mio_rst_int [label="rst"];
+ *     cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"];
+ *     cvmx_ciu2_src_pp0_ip2_mio:nand:e -> cvmx_ndf_int [label="nand"];
+ *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
+ *     cvmx_ciu2_src_pp0_ip2_mio:mio:e -> cvmx_mio_boot_err [label="mio"];
+ *     cvmx_root:root:e -> cvmx_ciu2_src_pp0_ip2_mio [label="root"];
+ *     cvmx_ciu2_sum_pp0_ip2 [label="CIU2_SUM_PPX_IP2(0)|<mem>mem|<pkt>pkt"];
+ *     cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
+ *     cvmx_ciu2_sum_pp0_ip2:mem:e -> cvmx_lmc0_int [label="mem"];
+ *     cvmx_lmc1_int [label="LMCX_INT(1)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
+ *     cvmx_ciu2_sum_pp0_ip2:mem:e -> cvmx_lmc1_int [label="mem"];
+ *     cvmx_lmc2_int [label="LMCX_INT(2)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
+ *     cvmx_ciu2_sum_pp0_ip2:mem:e -> cvmx_lmc2_int [label="mem"];
+ *     cvmx_lmc3_int [label="LMCX_INT(3)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
+ *     cvmx_ciu2_sum_pp0_ip2:mem:e -> cvmx_lmc3_int [label="mem"];
+ *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_rx0_int_reg [label="pkt"];
+ *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_rx1_int_reg [label="pkt"];
+ *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_rx2_int_reg [label="pkt"];
+ *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_rx3_int_reg [label="pkt"];
+ *     cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx1_rx0_int_reg [label="pkt"];
+ *     cvmx_gmx2_rx0_int_reg [label="GMXX_RXX_INT_REG(0,2)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_rx0_int_reg [label="pkt"];
+ *     cvmx_gmx2_rx1_int_reg [label="GMXX_RXX_INT_REG(1,2)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_rx1_int_reg [label="pkt"];
+ *     cvmx_gmx2_rx2_int_reg [label="GMXX_RXX_INT_REG(2,2)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_rx2_int_reg [label="pkt"];
+ *     cvmx_gmx2_rx3_int_reg [label="GMXX_RXX_INT_REG(3,2)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_rx3_int_reg [label="pkt"];
+ *     cvmx_gmx3_rx0_int_reg [label="GMXX_RXX_INT_REG(0,3)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_rx0_int_reg [label="pkt"];
+ *     cvmx_gmx3_rx1_int_reg [label="GMXX_RXX_INT_REG(1,3)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_rx1_int_reg [label="pkt"];
+ *     cvmx_gmx3_rx2_int_reg [label="GMXX_RXX_INT_REG(2,3)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_rx2_int_reg [label="pkt"];
+ *     cvmx_gmx3_rx3_int_reg [label="GMXX_RXX_INT_REG(3,3)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_rx3_int_reg [label="pkt"];
+ *     cvmx_gmx4_rx0_int_reg [label="GMXX_RXX_INT_REG(0,4)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_rx0_int_reg [label="pkt"];
+ *     cvmx_gmx4_rx1_int_reg [label="GMXX_RXX_INT_REG(1,4)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_rx1_int_reg [label="pkt"];
+ *     cvmx_gmx4_rx2_int_reg [label="GMXX_RXX_INT_REG(2,4)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_rx2_int_reg [label="pkt"];
+ *     cvmx_gmx4_rx3_int_reg [label="GMXX_RXX_INT_REG(3,4)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_rx3_int_reg [label="pkt"];
+ *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_tx_int_reg [label="pkt"];
+ *     cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx1_tx_int_reg [label="pkt"];
+ *     cvmx_gmx2_tx_int_reg [label="GMXX_TX_INT_REG(2)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_tx_int_reg [label="pkt"];
+ *     cvmx_gmx3_tx_int_reg [label="GMXX_TX_INT_REG(3)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_tx_int_reg [label="pkt"];
+ *     cvmx_gmx4_tx_int_reg [label="GMXX_TX_INT_REG(4)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_tx_int_reg [label="pkt"];
+ *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs0_int0_reg [label="pkt"];
+ *     cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs0_int1_reg [label="pkt"];
+ *     cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs0_int2_reg [label="pkt"];
+ *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs0_int3_reg [label="pkt"];
+ *     cvmx_pcs1_int0_reg [label="PCSX_INTX_REG(0,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs1_int0_reg [label="pkt"];
+ *     cvmx_pcs2_int0_reg [label="PCSX_INTX_REG(0,2)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs2_int0_reg [label="pkt"];
+ *     cvmx_pcs2_int1_reg [label="PCSX_INTX_REG(1,2)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs2_int1_reg [label="pkt"];
+ *     cvmx_pcs2_int2_reg [label="PCSX_INTX_REG(2,2)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs2_int2_reg [label="pkt"];
+ *     cvmx_pcs2_int3_reg [label="PCSX_INTX_REG(3,2)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs2_int3_reg [label="pkt"];
+ *     cvmx_pcs3_int0_reg [label="PCSX_INTX_REG(0,3)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs3_int0_reg [label="pkt"];
+ *     cvmx_pcs3_int1_reg [label="PCSX_INTX_REG(1,3)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs3_int1_reg [label="pkt"];
+ *     cvmx_pcs3_int2_reg [label="PCSX_INTX_REG(2,3)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs3_int2_reg [label="pkt"];
+ *     cvmx_pcs3_int3_reg [label="PCSX_INTX_REG(3,3)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs3_int3_reg [label="pkt"];
+ *     cvmx_pcs4_int0_reg [label="PCSX_INTX_REG(0,4)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs4_int0_reg [label="pkt"];
+ *     cvmx_pcs4_int1_reg [label="PCSX_INTX_REG(1,4)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs4_int1_reg [label="pkt"];
+ *     cvmx_pcs4_int2_reg [label="PCSX_INTX_REG(2,4)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs4_int2_reg [label="pkt"];
+ *     cvmx_pcs4_int3_reg [label="PCSX_INTX_REG(3,4)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs4_int3_reg [label="pkt"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx0_int_reg [label="pkt"];
+ *     cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx1_int_reg [label="pkt"];
+ *     cvmx_pcsx2_int_reg [label="PCSXX_INT_REG(2)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx2_int_reg [label="pkt"];
+ *     cvmx_pcsx3_int_reg [label="PCSXX_INT_REG(3)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx3_int_reg [label="pkt"];
+ *     cvmx_pcsx4_int_reg [label="PCSXX_INT_REG(4)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx4_int_reg [label="pkt"];
+ *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
+ *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
+ *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
+ *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
+ *     cvmx_gmx1_rx0_int_reg -> cvmx_gmx2_rx0_int_reg [style=invis];
+ *     cvmx_gmx2_rx0_int_reg -> cvmx_gmx2_rx1_int_reg [style=invis];
+ *     cvmx_gmx2_rx1_int_reg -> cvmx_gmx2_rx2_int_reg [style=invis];
+ *     cvmx_gmx2_rx2_int_reg -> cvmx_gmx2_rx3_int_reg [style=invis];
+ *     cvmx_gmx2_rx3_int_reg -> cvmx_gmx3_rx0_int_reg [style=invis];
+ *     cvmx_gmx3_rx0_int_reg -> cvmx_gmx3_rx1_int_reg [style=invis];
+ *     cvmx_gmx3_rx1_int_reg -> cvmx_gmx3_rx2_int_reg [style=invis];
+ *     cvmx_gmx3_rx2_int_reg -> cvmx_gmx3_rx3_int_reg [style=invis];
+ *     cvmx_gmx3_rx3_int_reg -> cvmx_gmx4_rx0_int_reg [style=invis];
+ *     cvmx_gmx4_rx0_int_reg -> cvmx_gmx4_rx1_int_reg [style=invis];
+ *     cvmx_gmx4_rx1_int_reg -> cvmx_gmx4_rx2_int_reg [style=invis];
+ *     cvmx_gmx4_rx2_int_reg -> cvmx_gmx4_rx3_int_reg [style=invis];
+ *     cvmx_gmx4_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
+ *     cvmx_gmx0_tx_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
+ *     cvmx_gmx1_tx_int_reg -> cvmx_gmx2_tx_int_reg [style=invis];
+ *     cvmx_gmx2_tx_int_reg -> cvmx_gmx3_tx_int_reg [style=invis];
+ *     cvmx_gmx3_tx_int_reg -> cvmx_gmx4_tx_int_reg [style=invis];
+ *     cvmx_gmx4_tx_int_reg -> cvmx_pcs0_int0_reg [style=invis];
+ *     cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
+ *     cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
+ *     cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
+ *     cvmx_pcs0_int3_reg -> cvmx_pcs1_int0_reg [style=invis];
+ *     cvmx_pcs1_int0_reg -> cvmx_pcs2_int0_reg [style=invis];
+ *     cvmx_pcs2_int0_reg -> cvmx_pcs2_int1_reg [style=invis];
+ *     cvmx_pcs2_int1_reg -> cvmx_pcs2_int2_reg [style=invis];
+ *     cvmx_pcs2_int2_reg -> cvmx_pcs2_int3_reg [style=invis];
+ *     cvmx_pcs2_int3_reg -> cvmx_pcs3_int0_reg [style=invis];
+ *     cvmx_pcs3_int0_reg -> cvmx_pcs3_int1_reg [style=invis];
+ *     cvmx_pcs3_int1_reg -> cvmx_pcs3_int2_reg [style=invis];
+ *     cvmx_pcs3_int2_reg -> cvmx_pcs3_int3_reg [style=invis];
+ *     cvmx_pcs3_int3_reg -> cvmx_pcs4_int0_reg [style=invis];
+ *     cvmx_pcs4_int0_reg -> cvmx_pcs4_int1_reg [style=invis];
+ *     cvmx_pcs4_int1_reg -> cvmx_pcs4_int2_reg [style=invis];
+ *     cvmx_pcs4_int2_reg -> cvmx_pcs4_int3_reg [style=invis];
+ *     cvmx_pcs4_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
+ *     cvmx_pcsx0_int_reg -> cvmx_pcsx1_int_reg [style=invis];
+ *     cvmx_pcsx1_int_reg -> cvmx_pcsx2_int_reg [style=invis];
+ *     cvmx_pcsx2_int_reg -> cvmx_pcsx3_int_reg [style=invis];
+ *     cvmx_pcsx3_int_reg -> cvmx_pcsx4_int_reg [style=invis];
+ *     cvmx_root:root:e -> cvmx_ciu2_sum_pp0_ip2 [label="root"];
+ * }
+ * @enddot
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-csr-typedefs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#endif
+
+int cvmx_error_initialize_cn68xx(void);
+
+int cvmx_error_initialize_cn68xx(void)
+{
+    cvmx_error_info_t info;
+    int fail = 0;
+
+    /* CVMX_CIU2_SRC_PPX_IP2_PKT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIXX_ISR(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<0 /* odblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<0 /* ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<40 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU2_RAW_PKT[MII]\n"
+        "       bit is set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])\n"
+        "    and the local interrupt mask bit(OVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
+        "    future ODBELL writes don't exceed the size of the\n"
+        "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
+        "    SW must reclaim O-Ring Entries by writing to the\n"
+        "    MIX_ORCNT[ORCNT]. .\n"
+        "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the O-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<1 /* idblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<1 /* ivfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<40 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU2_RAW_PKT[MII]\n"
+        "       bit is set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])\n"
+        "    and the local interrupt mask bit(IVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
+        "    future IDBELL writes don't exceed the size of the\n"
+        "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
+        "    SW must reclaim I-Ring Entries by keeping track of the\n"
+        "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
+        "    total #packets(not IRing Entries) and SW must further\n"
+        "    keep track of the # of I-Ring Entries associated with\n"
+        "    each packet as they are processed.\n"
+        "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the I-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<4 /* data_drp */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<4 /* data_drpena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<40 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
+        "    If this does occur, the DATA_DRP is set and the\n"
+        "    CIU2_RAW_PKT[MII] bit is set.\n"
+        "    If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])\n"
+        "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
+        "    interrupt is reported for this event.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<5 /* irun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<5 /* irunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<40 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
+        "    NOTE: If an IRUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<6 /* orun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<6 /* orunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<40 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
+        "    NOTE: If an ORUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_BAD_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<32 /* ovrflw */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<33 /* txpop */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<34 /* txpsh */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<35 /* ovrflw1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<36 /* txpop1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<37 /* txpsh1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 0x3ull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 0x3ull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In MII/RGMII, one bit per port\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_RXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_TX_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 0x3ull<<2 /* undflw */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 0x3ull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_GBL_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_GBL_INT;
+    info.status_mask        = 1ull<<0 /* rxf_lnk0_perr */;
+    info.enable_addr        = CVMX_ILK_GBL_INT_EN;
+    info.enable_mask        = 1ull<<0 /* rxf_lnk0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_GBL_INT[RXF_LNK0_PERR]: RXF parity error occurred on RxLink0 packet data.  Packet will\n"
+        "    be marked with error at eop\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_GBL_INT;
+    info.status_mask        = 1ull<<1 /* rxf_lnk1_perr */;
+    info.enable_addr        = CVMX_ILK_GBL_INT_EN;
+    info.enable_mask        = 1ull<<1 /* rxf_lnk1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_GBL_INT[RXF_LNK1_PERR]: RXF parity error occurred on RxLink1 packet data\n"
+        "    Packet will be marked with error at eop\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_GBL_INT;
+    info.status_mask        = 1ull<<2 /* rxf_ctl_perr */;
+    info.enable_addr        = CVMX_ILK_GBL_INT_EN;
+    info.enable_mask        = 1ull<<2 /* rxf_ctl_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_GBL_INT[RXF_CTL_PERR]: RXF parity error occurred on sideband control signals.  Data\n"
+        "    cycle will be dropped.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_GBL_INT;
+    info.status_mask        = 1ull<<3 /* rxf_pop_empty */;
+    info.enable_addr        = CVMX_ILK_GBL_INT_EN;
+    info.enable_mask        = 1ull<<3 /* rxf_pop_empty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_GBL_INT[RXF_POP_EMPTY]: RXF underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_GBL_INT;
+    info.status_mask        = 1ull<<4 /* rxf_push_full */;
+    info.enable_addr        = CVMX_ILK_GBL_INT_EN;
+    info.enable_mask        = 1ull<<4 /* rxf_push_full */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_GBL_INT[RXF_PUSH_FULL]: RXF overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_TXX_INT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_TXX_INT(0);
+    info.status_mask        = 1ull<<0 /* txf_err */;
+    info.enable_addr        = CVMX_ILK_TXX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* txf_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_TXX_INT(0)[TXF_ERR]: TX fifo parity error occurred.  At EOP time, EOP_Format will\n"
+        "    reflect the error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_TXX_INT(0);
+    info.status_mask        = 1ull<<1 /* bad_seq */;
+    info.enable_addr        = CVMX_ILK_TXX_INT_EN(0);
+    info.enable_mask        = 1ull<<1 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_TXX_INT(0)[BAD_SEQ]: Received sequence is not SOP followed by 0 or more data cycles\n"
+        "    followed by EOP.  PKO config assigned multiple engines to the\n"
+        "    same ILK Tx Link.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_TXX_INT(0);
+    info.status_mask        = 1ull<<2 /* bad_pipe */;
+    info.enable_addr        = CVMX_ILK_TXX_INT_EN(0);
+    info.enable_mask        = 1ull<<2 /* bad_pipe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_TXX_INT(0)[BAD_PIPE]: Received a PKO port-pipe out of the range specified by\n"
+        "    ILK_TXX_PIPE\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_TXX_INT(0);
+    info.status_mask        = 1ull<<3 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_TXX_INT_EN(0);
+    info.enable_mask        = 1ull<<3 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_TXX_INT(0)[STAT_CNT_OVFL]: Statistics counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_TXX_INT(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_TXX_INT(1);
+    info.status_mask        = 1ull<<0 /* txf_err */;
+    info.enable_addr        = CVMX_ILK_TXX_INT_EN(1);
+    info.enable_mask        = 1ull<<0 /* txf_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_TXX_INT(1)[TXF_ERR]: TX fifo parity error occurred.  At EOP time, EOP_Format will\n"
+        "    reflect the error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_TXX_INT(1);
+    info.status_mask        = 1ull<<1 /* bad_seq */;
+    info.enable_addr        = CVMX_ILK_TXX_INT_EN(1);
+    info.enable_mask        = 1ull<<1 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_TXX_INT(1)[BAD_SEQ]: Received sequence is not SOP followed by 0 or more data cycles\n"
+        "    followed by EOP.  PKO config assigned multiple engines to the\n"
+        "    same ILK Tx Link.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_TXX_INT(1);
+    info.status_mask        = 1ull<<2 /* bad_pipe */;
+    info.enable_addr        = CVMX_ILK_TXX_INT_EN(1);
+    info.enable_mask        = 1ull<<2 /* bad_pipe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_TXX_INT(1)[BAD_PIPE]: Received a PKO port-pipe out of the range specified by\n"
+        "    ILK_TXX_PIPE\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_TXX_INT(1);
+    info.status_mask        = 1ull<<3 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_TXX_INT_EN(1);
+    info.enable_mask        = 1ull<<3 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_TXX_INT(1)[STAT_CNT_OVFL]: Statistics counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RXX_INT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(0);
+    info.status_mask        = 1ull<<0 /* lane_align_fail */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* lane_align_fail */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(0)[LANE_ALIGN_FAIL]: Lane Alignment fails (4 tries).  Hardware will repeat lane\n"
+        "    alignment until is succeeds or until ILK_RXx_CFG1[RX_ALIGN_ENA]\n"
+        "    is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(0);
+    info.status_mask        = 1ull<<1 /* crc24_err */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<1 /* crc24_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(0)[CRC24_ERR]: Burst CRC24 error.  All open packets will be receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(0);
+    info.status_mask        = 1ull<<2 /* word_sync_done */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<2 /* word_sync_done */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(0)[WORD_SYNC_DONE]: All enabled lanes have achieved word boundary lock and\n"
+        "    scrambler synchronization.  Lane alignment may now be enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(0);
+    info.status_mask        = 1ull<<3 /* lane_align_done */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<3 /* lane_align_done */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(0)[LANE_ALIGN_DONE]: Lane alignment successful\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(0);
+    info.status_mask        = 1ull<<4 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<4 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(0)[STAT_CNT_OVFL]: Statistics counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(0);
+    info.status_mask        = 1ull<<5 /* lane_bad_word */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<5 /* lane_bad_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(0)[LANE_BAD_WORD]: A lane encountered either a bad 64B/67B codeword or an unknown\n"
+        "    control word type.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(0);
+    info.status_mask        = 1ull<<6 /* pkt_drop_rxf */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<6 /* pkt_drop_rxf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(0)[PKT_DROP_RXF]: Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(0);
+    info.status_mask        = 1ull<<7 /* pkt_drop_rid */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<7 /* pkt_drop_rid */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(0)[PKT_DROP_RID]: Entire packet dropped due to the lack of reassembly-ids or\n"
+        "    because ILK_RXX_CFG1[PKT_ENA]=0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(0);
+    info.status_mask        = 1ull<<8 /* pkt_drop_sop */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<8 /* pkt_drop_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(0)[PKT_DROP_SOP]: Entire packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX,\n"
+        "    lack of reassembly-ids or because ILK_RXX_CFG1[PKT_ENA]=0      | $RW\n"
+        "    because ILK_RXX_CFG1[PKT_ENA]=0\n"
+        "    ***NOTE: Added in pass 2.0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RXX_INT(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(1);
+    info.status_mask        = 1ull<<0 /* lane_align_fail */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<0 /* lane_align_fail */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(1)[LANE_ALIGN_FAIL]: Lane Alignment fails (4 tries).  Hardware will repeat lane\n"
+        "    alignment until is succeeds or until ILK_RXx_CFG1[RX_ALIGN_ENA]\n"
+        "    is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(1);
+    info.status_mask        = 1ull<<1 /* crc24_err */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<1 /* crc24_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(1)[CRC24_ERR]: Burst CRC24 error.  All open packets will be receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(1);
+    info.status_mask        = 1ull<<2 /* word_sync_done */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<2 /* word_sync_done */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(1)[WORD_SYNC_DONE]: All enabled lanes have achieved word boundary lock and\n"
+        "    scrambler synchronization.  Lane alignment may now be enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(1);
+    info.status_mask        = 1ull<<3 /* lane_align_done */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<3 /* lane_align_done */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(1)[LANE_ALIGN_DONE]: Lane alignment successful\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(1);
+    info.status_mask        = 1ull<<4 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<4 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(1)[STAT_CNT_OVFL]: Statistics counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(1);
+    info.status_mask        = 1ull<<5 /* lane_bad_word */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<5 /* lane_bad_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(1)[LANE_BAD_WORD]: A lane encountered either a bad 64B/67B codeword or an unknown\n"
+        "    control word type.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(1);
+    info.status_mask        = 1ull<<6 /* pkt_drop_rxf */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<6 /* pkt_drop_rxf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(1)[PKT_DROP_RXF]: Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(1);
+    info.status_mask        = 1ull<<7 /* pkt_drop_rid */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<7 /* pkt_drop_rid */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(1)[PKT_DROP_RID]: Entire packet dropped due to the lack of reassembly-ids or\n"
+        "    because ILK_RXX_CFG1[PKT_ENA]=0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(1);
+    info.status_mask        = 1ull<<8 /* pkt_drop_sop */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<8 /* pkt_drop_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(1)[PKT_DROP_SOP]: Entire packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX,\n"
+        "    lack of reassembly-ids or because ILK_RXX_CFG1[PKT_ENA]=0      | $RW\n"
+        "    because ILK_RXX_CFG1[PKT_ENA]=0\n"
+        "    ***NOTE: Added in pass 2.0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RX_LNEX_INT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(0);
+    info.status_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(0)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(0);
+    info.status_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(0);
+    info.enable_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(0)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries).  Hardware will\n"
+        "    automatically attempt to regain word boundary sync\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(0);
+    info.status_mask        = 1ull<<2 /* crc32_err */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(0);
+    info.enable_mask        = 1ull<<2 /* crc32_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(0)[CRC32_ERR]: Diagnostic CRC32 errors\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(0);
+    info.status_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(0);
+    info.enable_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(0)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
+        "    (SYNC,SCRAM,SKIP,DIAG)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(0);
+    info.status_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(0);
+    info.enable_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(0)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
+        "    mismatches\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(0);
+    info.status_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(0);
+    info.enable_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(0)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(0);
+    info.status_mask        = 1ull<<6 /* stat_msg */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(0);
+    info.enable_mask        = 1ull<<6 /* stat_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(0)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
+        "    (healthy) to a '0' (problem)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(0);
+    info.status_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(0);
+    info.enable_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(0)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(0);
+    info.status_mask        = 1ull<<8 /* bad_64b67b */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(0);
+    info.enable_mask        = 1ull<<8 /* bad_64b67b */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(0)[BAD_64B67B]: Bad 64B/67B codeword encountered.  Once the bad word reaches\n"
+        "    the burst control unit (as deonted by\n"
+        "    ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
+        "    packets will receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RX_LNEX_INT(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(1);
+    info.status_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(1);
+    info.enable_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(1)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(1);
+    info.status_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(1);
+    info.enable_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(1)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries).  Hardware will\n"
+        "    automatically attempt to regain word boundary sync\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(1);
+    info.status_mask        = 1ull<<2 /* crc32_err */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(1);
+    info.enable_mask        = 1ull<<2 /* crc32_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(1)[CRC32_ERR]: Diagnostic CRC32 errors\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(1);
+    info.status_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(1);
+    info.enable_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(1)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
+        "    (SYNC,SCRAM,SKIP,DIAG)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(1);
+    info.status_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(1);
+    info.enable_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(1)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
+        "    mismatches\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(1);
+    info.status_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(1);
+    info.enable_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(1)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(1);
+    info.status_mask        = 1ull<<6 /* stat_msg */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(1);
+    info.enable_mask        = 1ull<<6 /* stat_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(1)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
+        "    (healthy) to a '0' (problem)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(1);
+    info.status_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(1);
+    info.enable_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(1)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(1);
+    info.status_mask        = 1ull<<8 /* bad_64b67b */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(1);
+    info.enable_mask        = 1ull<<8 /* bad_64b67b */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(1)[BAD_64B67B]: Bad 64B/67B codeword encountered.  Once the bad word reaches\n"
+        "    the burst control unit (as deonted by\n"
+        "    ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
+        "    packets will receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RX_LNEX_INT(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(2);
+    info.status_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(2);
+    info.enable_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(2)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(2);
+    info.status_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(2);
+    info.enable_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(2)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries).  Hardware will\n"
+        "    automatically attempt to regain word boundary sync\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(2);
+    info.status_mask        = 1ull<<2 /* crc32_err */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(2);
+    info.enable_mask        = 1ull<<2 /* crc32_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(2)[CRC32_ERR]: Diagnostic CRC32 errors\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(2);
+    info.status_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(2);
+    info.enable_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(2)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
+        "    (SYNC,SCRAM,SKIP,DIAG)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(2);
+    info.status_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(2);
+    info.enable_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(2)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
+        "    mismatches\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(2);
+    info.status_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(2);
+    info.enable_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(2)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(2);
+    info.status_mask        = 1ull<<6 /* stat_msg */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(2);
+    info.enable_mask        = 1ull<<6 /* stat_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(2)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
+        "    (healthy) to a '0' (problem)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(2);
+    info.status_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(2);
+    info.enable_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(2)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(2);
+    info.status_mask        = 1ull<<8 /* bad_64b67b */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(2);
+    info.enable_mask        = 1ull<<8 /* bad_64b67b */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(2)[BAD_64B67B]: Bad 64B/67B codeword encountered.  Once the bad word reaches\n"
+        "    the burst control unit (as deonted by\n"
+        "    ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
+        "    packets will receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RX_LNEX_INT(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(3);
+    info.status_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(3);
+    info.enable_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(3)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(3);
+    info.status_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(3);
+    info.enable_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(3)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries).  Hardware will\n"
+        "    automatically attempt to regain word boundary sync\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(3);
+    info.status_mask        = 1ull<<2 /* crc32_err */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(3);
+    info.enable_mask        = 1ull<<2 /* crc32_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(3)[CRC32_ERR]: Diagnostic CRC32 errors\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(3);
+    info.status_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(3);
+    info.enable_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(3)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
+        "    (SYNC,SCRAM,SKIP,DIAG)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(3);
+    info.status_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(3);
+    info.enable_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(3)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
+        "    mismatches\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(3);
+    info.status_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(3);
+    info.enable_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(3)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(3);
+    info.status_mask        = 1ull<<6 /* stat_msg */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(3);
+    info.enable_mask        = 1ull<<6 /* stat_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(3)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
+        "    (healthy) to a '0' (problem)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(3);
+    info.status_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(3);
+    info.enable_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(3)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(3);
+    info.status_mask        = 1ull<<8 /* bad_64b67b */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(3);
+    info.enable_mask        = 1ull<<8 /* bad_64b67b */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(3)[BAD_64B67B]: Bad 64B/67B codeword encountered.  Once the bad word reaches\n"
+        "    the burst control unit (as deonted by\n"
+        "    ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
+        "    packets will receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RX_LNEX_INT(4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(4);
+    info.status_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(4);
+    info.enable_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 4;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(4)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(4);
+    info.status_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(4);
+    info.enable_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 4;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(4)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries).  Hardware will\n"
+        "    automatically attempt to regain word boundary sync\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(4);
+    info.status_mask        = 1ull<<2 /* crc32_err */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(4);
+    info.enable_mask        = 1ull<<2 /* crc32_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 4;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(4)[CRC32_ERR]: Diagnostic CRC32 errors\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(4);
+    info.status_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(4);
+    info.enable_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 4;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(4)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
+        "    (SYNC,SCRAM,SKIP,DIAG)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(4);
+    info.status_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(4);
+    info.enable_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 4;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(4)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
+        "    mismatches\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(4);
+    info.status_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(4);
+    info.enable_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 4;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(4)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(4);
+    info.status_mask        = 1ull<<6 /* stat_msg */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(4);
+    info.enable_mask        = 1ull<<6 /* stat_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 4;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(4)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
+        "    (healthy) to a '0' (problem)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(4);
+    info.status_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(4);
+    info.enable_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 4;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(4)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(4);
+    info.status_mask        = 1ull<<8 /* bad_64b67b */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(4);
+    info.enable_mask        = 1ull<<8 /* bad_64b67b */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 4;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(4)[BAD_64B67B]: Bad 64B/67B codeword encountered.  Once the bad word reaches\n"
+        "    the burst control unit (as deonted by\n"
+        "    ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
+        "    packets will receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RX_LNEX_INT(5) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(5);
+    info.status_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(5);
+    info.enable_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 5;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(5)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(5);
+    info.status_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(5);
+    info.enable_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 5;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(5)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries).  Hardware will\n"
+        "    automatically attempt to regain word boundary sync\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(5);
+    info.status_mask        = 1ull<<2 /* crc32_err */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(5);
+    info.enable_mask        = 1ull<<2 /* crc32_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 5;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(5)[CRC32_ERR]: Diagnostic CRC32 errors\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(5);
+    info.status_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(5);
+    info.enable_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 5;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(5)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
+        "    (SYNC,SCRAM,SKIP,DIAG)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(5);
+    info.status_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(5);
+    info.enable_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 5;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(5)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
+        "    mismatches\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(5);
+    info.status_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(5);
+    info.enable_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 5;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(5)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(5);
+    info.status_mask        = 1ull<<6 /* stat_msg */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(5);
+    info.enable_mask        = 1ull<<6 /* stat_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 5;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(5)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
+        "    (healthy) to a '0' (problem)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(5);
+    info.status_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(5);
+    info.enable_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 5;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(5)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(5);
+    info.status_mask        = 1ull<<8 /* bad_64b67b */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(5);
+    info.enable_mask        = 1ull<<8 /* bad_64b67b */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 5;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(5)[BAD_64B67B]: Bad 64B/67B codeword encountered.  Once the bad word reaches\n"
+        "    the burst control unit (as deonted by\n"
+        "    ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
+        "    packets will receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RX_LNEX_INT(6) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(6);
+    info.status_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(6);
+    info.enable_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 6;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(6)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(6);
+    info.status_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(6);
+    info.enable_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 6;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(6)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries).  Hardware will\n"
+        "    automatically attempt to regain word boundary sync\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(6);
+    info.status_mask        = 1ull<<2 /* crc32_err */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(6);
+    info.enable_mask        = 1ull<<2 /* crc32_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 6;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(6)[CRC32_ERR]: Diagnostic CRC32 errors\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(6);
+    info.status_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(6);
+    info.enable_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 6;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(6)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
+        "    (SYNC,SCRAM,SKIP,DIAG)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(6);
+    info.status_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(6);
+    info.enable_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 6;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(6)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
+        "    mismatches\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(6);
+    info.status_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(6);
+    info.enable_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 6;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(6)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(6);
+    info.status_mask        = 1ull<<6 /* stat_msg */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(6);
+    info.enable_mask        = 1ull<<6 /* stat_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 6;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(6)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
+        "    (healthy) to a '0' (problem)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(6);
+    info.status_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(6);
+    info.enable_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 6;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(6)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(6);
+    info.status_mask        = 1ull<<8 /* bad_64b67b */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(6);
+    info.enable_mask        = 1ull<<8 /* bad_64b67b */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 6;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(6)[BAD_64B67B]: Bad 64B/67B codeword encountered.  Once the bad word reaches\n"
+        "    the burst control unit (as deonted by\n"
+        "    ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
+        "    packets will receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RX_LNEX_INT(7) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(7);
+    info.status_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(7);
+    info.enable_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 7;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(7)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(7);
+    info.status_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(7);
+    info.enable_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 7;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(7)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries).  Hardware will\n"
+        "    automatically attempt to regain word boundary sync\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(7);
+    info.status_mask        = 1ull<<2 /* crc32_err */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(7);
+    info.enable_mask        = 1ull<<2 /* crc32_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 7;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(7)[CRC32_ERR]: Diagnostic CRC32 errors\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(7);
+    info.status_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(7);
+    info.enable_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 7;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(7)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
+        "    (SYNC,SCRAM,SKIP,DIAG)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(7);
+    info.status_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(7);
+    info.enable_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 7;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(7)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
+        "    mismatches\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(7);
+    info.status_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(7);
+    info.enable_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 7;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(7)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(7);
+    info.status_mask        = 1ull<<6 /* stat_msg */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(7);
+    info.enable_mask        = 1ull<<6 /* stat_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 7;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(7)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
+        "    (healthy) to a '0' (problem)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(7);
+    info.status_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(7);
+    info.enable_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 7;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(7)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(7);
+    info.status_mask        = 1ull<<8 /* bad_64b67b */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(7);
+    info.enable_mask        = 1ull<<8 /* bad_64b67b */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 7;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(7)[BAD_64B67B]: Bad 64B/67B codeword encountered.  Once the bad word reaches\n"
+        "    the burst control unit (as deonted by\n"
+        "    ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
+        "    packets will receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU2_SRC_PPX_IP2_RML(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<0 /* holerd */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<0 /* holerd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<48 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<1 /* holewr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<1 /* holewr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<48 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<2 /* vrtwr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<2 /* vrtwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<48 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
+        "    Set when L2C_VRT_MEM blocked a store.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<3 /* vrtidrng */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<3 /* vrtidrng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<48 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
+        "    Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
+        "    store.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<4 /* vrtadrng */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<4 /* vrtadrng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<48 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
+        "    Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
+        "    store.\n"
+        "    L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<5 /* vrtpe */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<5 /* vrtpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<48 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
+        "    Whenever an L2C_VRT_MEM read finds a parity error,\n"
+        "    that L2C_VRT_MEM cannot cause stores to be blocked.\n"
+        "    Software should correct the error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<6 /* bigwr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<6 /* bigwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<48 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[BIGWR]: Write reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<7 /* bigrd */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<7 /* bigrd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<48 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[BIGRD]: Read reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<48 /* l2c */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_TADX_INT(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(1);
+    info.status_mask        = 1ull<<0 /* l2dsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(1);
+    info.enable_mask        = 1ull<<0 /* l2dsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(1)[L2DSBE]: L2D Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(1);
+    info.status_mask        = 1ull<<1 /* l2ddbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(1);
+    info.enable_mask        = 1ull<<1 /* l2ddbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(1)[L2DDBE]: L2D Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(1);
+    info.status_mask        = 1ull<<2 /* tagsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(1);
+    info.enable_mask        = 1ull<<2 /* tagsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(1)[TAGSBE]: TAG Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(1);
+    info.status_mask        = 1ull<<3 /* tagdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(1);
+    info.enable_mask        = 1ull<<3 /* tagdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(1)[TAGDBE]: TAG Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(1);
+    info.status_mask        = 1ull<<4 /* vbfsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(1);
+    info.enable_mask        = 1ull<<4 /* vbfsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(1)[VBFSBE]: VBF Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VSBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(1);
+    info.status_mask        = 1ull<<5 /* vbfdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(1);
+    info.enable_mask        = 1ull<<5 /* vbfdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(1)[VBFDBE]: VBF Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VDBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(1);
+    info.status_mask        = 1ull<<6 /* noway */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(1);
+    info.enable_mask        = 1ull<<6 /* noway */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(1)[NOWAY]: No way available interrupt\n"
+        "    Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(1);
+    info.status_mask        = 1ull<<7 /* rddislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(1);
+    info.enable_mask        = 1ull<<7 /* rddislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(1)[RDDISLMC]: Illegal Read  to Disabled LMC Error\n"
+        "    A DRAM read  arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(1);
+    info.status_mask        = 1ull<<8 /* wrdislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(1);
+    info.enable_mask        = 1ull<<8 /* wrdislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(1)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
+        "    A DRAM write arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TDTX(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(1);
+    info.status_mask        = 1ull<<60 /* vsbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(1)[VSBE]: VBF Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(1);
+    info.status_mask        = 1ull<<61 /* vdbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(1)[VDBE]: VBF Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(1);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(1)[SBE]: L2D Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(1);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(1)[DBE]: L2D Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TTGX(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(1);
+    info.status_mask        = 1ull<<61 /* noway */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(1)[NOWAY]: No way was available for allocation.\n"
+        "    L2C sets NOWAY during its processing of a\n"
+        "    transaction whenever it needed/wanted to allocate\n"
+        "    a WAY in the L2 cache, but was unable to. NOWAY==1\n"
+        "    is (generally) not an indication that L2C failed to\n"
+        "    complete transactions. Rather, it is a hint of\n"
+        "    possible performance degradation. (For example, L2C\n"
+        "    must read-modify-write DRAM for every transaction\n"
+        "    that updates some, but not all, of the bytes in a\n"
+        "    cache block, misses in the L2 cache, and cannot\n"
+        "    allocate a WAY.) There is one \"failure\" case where\n"
+        "    L2C will set NOWAY: when it cannot leave a block\n"
+        "    locked in the L2 cache as part of a LCKL2\n"
+        "    transaction.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(1);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(1)[SBE]: Single-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(1);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(1)[DBE]: Double-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_TADX_INT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<0 /* l2dsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<0 /* l2dsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[L2DSBE]: L2D Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<1 /* l2ddbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<1 /* l2ddbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[L2DDBE]: L2D Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<2 /* tagsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<2 /* tagsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[TAGSBE]: TAG Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<3 /* tagdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<3 /* tagdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[TAGDBE]: TAG Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<4 /* vbfsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<4 /* vbfsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VSBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<5 /* vbfdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<5 /* vbfdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VDBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<6 /* noway */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<6 /* noway */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[NOWAY]: No way available interrupt\n"
+        "    Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<7 /* rddislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<7 /* rddislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[RDDISLMC]: Illegal Read  to Disabled LMC Error\n"
+        "    A DRAM read  arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<8 /* wrdislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<8 /* wrdislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
+        "    A DRAM write arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TDTX(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<60 /* vsbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<61 /* vdbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TTGX(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<61 /* noway */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
+        "    L2C sets NOWAY during its processing of a\n"
+        "    transaction whenever it needed/wanted to allocate\n"
+        "    a WAY in the L2 cache, but was unable to. NOWAY==1\n"
+        "    is (generally) not an indication that L2C failed to\n"
+        "    complete transactions. Rather, it is a hint of\n"
+        "    possible performance degradation. (For example, L2C\n"
+        "    must read-modify-write DRAM for every transaction\n"
+        "    that updates some, but not all, of the bytes in a\n"
+        "    cache block, misses in the L2 cache, and cannot\n"
+        "    allocate a WAY.) There is one \"failure\" case where\n"
+        "    L2C will set NOWAY: when it cannot leave a block\n"
+        "    locked in the L2 cache as part of a LCKL2\n"
+        "    transaction.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_TADX_INT(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(3);
+    info.status_mask        = 1ull<<0 /* l2dsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(3);
+    info.enable_mask        = 1ull<<0 /* l2dsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(3)[L2DSBE]: L2D Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(3);
+    info.status_mask        = 1ull<<1 /* l2ddbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(3);
+    info.enable_mask        = 1ull<<1 /* l2ddbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(3)[L2DDBE]: L2D Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(3);
+    info.status_mask        = 1ull<<2 /* tagsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(3);
+    info.enable_mask        = 1ull<<2 /* tagsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(3)[TAGSBE]: TAG Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(3);
+    info.status_mask        = 1ull<<3 /* tagdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(3);
+    info.enable_mask        = 1ull<<3 /* tagdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(3)[TAGDBE]: TAG Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(3);
+    info.status_mask        = 1ull<<4 /* vbfsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(3);
+    info.enable_mask        = 1ull<<4 /* vbfsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(3)[VBFSBE]: VBF Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VSBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(3);
+    info.status_mask        = 1ull<<5 /* vbfdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(3);
+    info.enable_mask        = 1ull<<5 /* vbfdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(3)[VBFDBE]: VBF Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VDBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(3);
+    info.status_mask        = 1ull<<6 /* noway */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(3);
+    info.enable_mask        = 1ull<<6 /* noway */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(3)[NOWAY]: No way available interrupt\n"
+        "    Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(3);
+    info.status_mask        = 1ull<<7 /* rddislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(3);
+    info.enable_mask        = 1ull<<7 /* rddislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(3)[RDDISLMC]: Illegal Read  to Disabled LMC Error\n"
+        "    A DRAM read  arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(3);
+    info.status_mask        = 1ull<<8 /* wrdislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(3);
+    info.enable_mask        = 1ull<<8 /* wrdislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(3)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
+        "    A DRAM write arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TDTX(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(3);
+    info.status_mask        = 1ull<<60 /* vsbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(3)[VSBE]: VBF Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(3);
+    info.status_mask        = 1ull<<61 /* vdbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(3)[VDBE]: VBF Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(3);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(3)[SBE]: L2D Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(3);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(3)[DBE]: L2D Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TTGX(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(3);
+    info.status_mask        = 1ull<<61 /* noway */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(3)[NOWAY]: No way was available for allocation.\n"
+        "    L2C sets NOWAY during its processing of a\n"
+        "    transaction whenever it needed/wanted to allocate\n"
+        "    a WAY in the L2 cache, but was unable to. NOWAY==1\n"
+        "    is (generally) not an indication that L2C failed to\n"
+        "    complete transactions. Rather, it is a hint of\n"
+        "    possible performance degradation. (For example, L2C\n"
+        "    must read-modify-write DRAM for every transaction\n"
+        "    that updates some, but not all, of the bytes in a\n"
+        "    cache block, misses in the L2 cache, and cannot\n"
+        "    allocate a WAY.) There is one \"failure\" case where\n"
+        "    L2C will set NOWAY: when it cannot leave a block\n"
+        "    locked in the L2 cache as part of a LCKL2\n"
+        "    transaction.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(3);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(3)[SBE]: Single-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(3);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(3)[DBE]: Double-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_TADX_INT(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(2);
+    info.status_mask        = 1ull<<0 /* l2dsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(2);
+    info.enable_mask        = 1ull<<0 /* l2dsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(2)[L2DSBE]: L2D Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(2);
+    info.status_mask        = 1ull<<1 /* l2ddbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(2);
+    info.enable_mask        = 1ull<<1 /* l2ddbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(2)[L2DDBE]: L2D Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(2);
+    info.status_mask        = 1ull<<2 /* tagsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(2);
+    info.enable_mask        = 1ull<<2 /* tagsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(2)[TAGSBE]: TAG Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(2);
+    info.status_mask        = 1ull<<3 /* tagdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(2);
+    info.enable_mask        = 1ull<<3 /* tagdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(2)[TAGDBE]: TAG Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(2);
+    info.status_mask        = 1ull<<4 /* vbfsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(2);
+    info.enable_mask        = 1ull<<4 /* vbfsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(2)[VBFSBE]: VBF Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VSBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(2);
+    info.status_mask        = 1ull<<5 /* vbfdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(2);
+    info.enable_mask        = 1ull<<5 /* vbfdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(2)[VBFDBE]: VBF Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VDBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(2);
+    info.status_mask        = 1ull<<6 /* noway */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(2);
+    info.enable_mask        = 1ull<<6 /* noway */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(2)[NOWAY]: No way available interrupt\n"
+        "    Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(2);
+    info.status_mask        = 1ull<<7 /* rddislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(2);
+    info.enable_mask        = 1ull<<7 /* rddislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(2)[RDDISLMC]: Illegal Read  to Disabled LMC Error\n"
+        "    A DRAM read  arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(2);
+    info.status_mask        = 1ull<<8 /* wrdislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(2);
+    info.enable_mask        = 1ull<<8 /* wrdislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(2)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
+        "    A DRAM write arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TDTX(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(2);
+    info.status_mask        = 1ull<<60 /* vsbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(2)[VSBE]: VBF Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(2);
+    info.status_mask        = 1ull<<61 /* vdbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(2)[VDBE]: VBF Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(2);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(2)[SBE]: L2D Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(2);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(2)[DBE]: L2D Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TTGX(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(2);
+    info.status_mask        = 1ull<<61 /* noway */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(2)[NOWAY]: No way was available for allocation.\n"
+        "    L2C sets NOWAY during its processing of a\n"
+        "    transaction whenever it needed/wanted to allocate\n"
+        "    a WAY in the L2 cache, but was unable to. NOWAY==1\n"
+        "    is (generally) not an indication that L2C failed to\n"
+        "    complete transactions. Rather, it is a hint of\n"
+        "    possible performance degradation. (For example, L2C\n"
+        "    must read-modify-write DRAM for every transaction\n"
+        "    that updates some, but not all, of the bytes in a\n"
+        "    cache block, misses in the L2 cache, and cannot\n"
+        "    allocate a WAY.) There is one \"failure\" case where\n"
+        "    L2C will set NOWAY: when it cannot leave a block\n"
+        "    locked in the L2 cache as part of a LCKL2\n"
+        "    transaction.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(2);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(2)[SBE]: Single-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(2);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(2)[DBE]: Double-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_FPA_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<0 /* fed0_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* fed0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<1 /* fed0_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* fed0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<2 /* fed1_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* fed1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<3 /* fed1_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* fed1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<4 /* q0_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* q0_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<5 /* q0_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* q0_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<6 /* q0_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* q0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<7 /* q1_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* q1_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<8 /* q1_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* q1_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<9 /* q1_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* q1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<10 /* q2_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* q2_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<11 /* q2_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* q2_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<12 /* q2_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* q2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<13 /* q3_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* q3_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<14 /* q3_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* q3_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<15 /* q3_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* q3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<16 /* q4_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* q4_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<17 /* q4_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* q4_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<18 /* q4_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* q4_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<19 /* q5_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* q5_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<20 /* q5_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* q5_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<21 /* q5_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* q5_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<22 /* q6_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* q6_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<23 /* q6_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* q6_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<24 /* q6_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* q6_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<25 /* q7_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* q7_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<26 /* q7_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* q7_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<27 /* q7_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* q7_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<28 /* pool0th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<28 /* pool0th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL0TH]: Set when FPA_QUE0_AVAILABLE is equal to\n"
+        "    FPA_POOL0_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<29 /* pool1th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<29 /* pool1th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL1TH]: Set when FPA_QUE1_AVAILABLE is equal to\n"
+        "    FPA_POOL1_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<30 /* pool2th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<30 /* pool2th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL2TH]: Set when FPA_QUE2_AVAILABLE is equal to\n"
+        "    FPA_POOL2_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<31 /* pool3th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<31 /* pool3th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL3TH]: Set when FPA_QUE3_AVAILABLE is equal to\n"
+        "    FPA_POOL3_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<32 /* pool4th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<32 /* pool4th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL4TH]: Set when FPA_QUE4_AVAILABLE is equal to\n"
+        "    FPA_POOL4_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<33 /* pool5th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<33 /* pool5th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL5TH]: Set when FPA_QUE5_AVAILABLE is equal to\n"
+        "    FPA_POOL5_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<34 /* pool6th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<34 /* pool6th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL6TH]: Set when FPA_QUE6_AVAILABLE is equal to\n"
+        "    FPA_POOL6_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<35 /* pool7th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<35 /* pool7th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL7TH]: Set when FPA_QUE7_AVAILABLE is equal to\n"
+        "    FPA_POOL7_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<36 /* free0 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<36 /* free0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE0]: When a pointer for POOL0 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<37 /* free1 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<37 /* free1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE1]: When a pointer for POOL1 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<38 /* free2 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<38 /* free2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE2]: When a pointer for POOL2 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<39 /* free3 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<39 /* free3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE3]: When a pointer for POOL3 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<40 /* free4 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<40 /* free4 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE4]: When a pointer for POOL4 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<41 /* free5 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<41 /* free5 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE5]: When a pointer for POOL5 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<42 /* free6 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<42 /* free6 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE6]: When a pointer for POOL6 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<43 /* free7 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<43 /* free7 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE7]: When a pointer for POOL7 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<44 /* free8 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<44 /* free8 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE8]: When a pointer for POOL8 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<45 /* q8_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<45 /* q8_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q8_UND]: Set when a Queue8 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<46 /* q8_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<46 /* q8_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q8_COFF]: Set when a Queue8 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<47 /* q8_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<47 /* q8_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q8_PERR]: Set when a Queue8 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<48 /* pool8th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<48 /* pool8th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL8TH]: Set when FPA_QUE8_AVAILABLE is equal to\n"
+        "    FPA_POOL8_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<49 /* paddr_e */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<49 /* paddr_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[PADDR_E]: Set when a pointer address does not fall in the\n"
+        "    address range for a pool specified by\n"
+        "    FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ZIP_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ZIP_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_ZIP_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<24 /* zip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IPD_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<0 /* prc_par0 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* prc_par0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+        "    [31:0] of the PBM memory.\n"
+        "    NOT USED ON o68.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<1 /* prc_par1 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* prc_par1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+        "    [63:32] of the PBM memory.\n"
+        "    NOT USED ON o68.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<2 /* prc_par2 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* prc_par2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+        "    [95:64] of the PBM memory.\n"
+        "    NOT USED ON o68.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<3 /* prc_par3 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* prc_par3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+        "    [127:96] of the PBM memory.\n"
+        "    NOT USED ON o68.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<4 /* bp_sub */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* bp_sub */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+        "    supplied illegal value.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* dc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<6 /* cc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* cc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<7 /* c_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* c_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<8 /* d_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* d_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<9 /* bc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* bc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<12 /* sop */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    reasm-id for a packet.\n"
+        "    The first detected error associated with bits [14:12]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n"
+        "    Also see IPD_PKT_ERR.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<13 /* eop */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    reasm-id for a packet.\n"
+        "    The first detected error associated with bits [14:12]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n"
+        "    Also see IPD_PKT_ERR.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<14 /* dat */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[DAT]: Set when a data arrives before a SOP for the same\n"
+        "    reasm-id for a packet.\n"
+        "    The first detected error associated with bits [14:12]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n"
+        "    Also see IPD_PKT_ERR.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<15 /* pw0_sbe */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* pw0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PW0_SBE]: Packet memory 0 had ECC SBE.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<16 /* pw0_dbe */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* pw0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PW0_DBE]: Packet memory 0 had ECC DBE.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<17 /* pw1_sbe */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* pw1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PW1_SBE]: Packet memory 1 had ECC SBE.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<18 /* pw1_dbe */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* pw1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PW1_DBE]: Packet memory 1 had ECC DBE.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<19 /* pw2_sbe */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* pw2_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PW2_SBE]: Packet memory 2 had ECC SBE.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<20 /* pw2_dbe */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* pw2_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PW2_DBE]: Packet memory 2 had ECC DBE.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<21 /* pw3_sbe */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* pw3_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PW3_SBE]: Packet memory 3 had ECC SBE.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<22 /* pw3_dbe */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* pw3_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PW3_DBE]: Packet memory 3 had ECC DBE.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_RAD_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_RAD_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_RAD_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<29 /* rad */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_SSO_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 0x7ffull<<32 /* iop */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 0x7ffull<<32 /* iop_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[IOP]: Illegal operation errors\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<1 /* fidx_dbe */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<1 /* fidx_dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[FIDX_DBE]: Double bit error for FIDX RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<2 /* idx_sbe */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<2 /* idx_sbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[IDX_SBE]: Single bit error for IDX RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<11 /* pnd_dbe0 */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<11 /* pnd_dbe0_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[PND_DBE0]: Double bit error for even PND RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<4 /* oth_sbe1 */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<4 /* oth_sbe1_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[OTH_SBE1]: Single bit error for odd OTH RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<5 /* oth_dbe1 */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<5 /* oth_dbe1_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[OTH_DBE1]: Double bit error for odd OTH RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<6 /* oth_sbe0 */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<6 /* oth_sbe0_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[OTH_SBE0]: Single bit error for even OTH RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<7 /* oth_dbe0 */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<7 /* oth_dbe0_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[OTH_DBE0]: Double bit error for even OTH RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<8 /* pnd_sbe1 */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<8 /* pnd_sbe1_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[PND_SBE1]: Single bit error for odd PND RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<9 /* pnd_dbe1 */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<9 /* pnd_dbe1_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[PND_DBE1]: Double bit error for odd PND RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<10 /* pnd_sbe0 */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<10 /* pnd_sbe0_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[PND_SBE0]: Single bit error for even PND RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<45 /* fpe */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<45 /* fpe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[FPE]: Free page error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<46 /* awe */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<46 /* awe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[AWE]: Out-of-memory error (ADDWQ Request is dropped)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<47 /* bfp */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<47 /* bfp_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[BFP]: Bad Fill Packet error\n"
+        "    Last byte of the fill packet did not match 8'h1a\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<3 /* idx_dbe */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<3 /* idx_dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[IDX_DBE]: Double bit error for IDX RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<0 /* fidx_sbe */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<0 /* fidx_sbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[FIDX_SBE]: Single bit error for FIDX RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEXP_SLI_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<0 /* rml_to */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<0 /* rml_to */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n"
+        "    within 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<1 /* reserved_1_1 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<1 /* reserved_1_1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<2 /* bar0_to */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<2 /* bar0_to */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
+        "    read-data/commit in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<3 /* iob2big */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<3 /* iob2big */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 0x3ull<<6 /* reserved_6_7 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 0x3ull<<6 /* reserved_6_7 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<8 /* m0_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<8 /* m0_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<9 /* m0_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<9 /* m0_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n"
+        "    from MAC 0. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<10 /* m0_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<10 /* m0_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<11 /* m0_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<11 /* m0_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n"
+        "    from MAC 0. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<12 /* m1_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<12 /* m1_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<13 /* m1_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<13 /* m1_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n"
+        "    from MAC 1. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<14 /* m1_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<14 /* m1_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<15 /* m1_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<15 /* m1_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n"
+        "    from MAC 1. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<48 /* pidbof */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<48 /* pidbof */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
+        "    doorbell can be found in DPI_PINT_INFO[PIDBOF]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<49 /* psldbof */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<49 /* psldbof */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
+        "    doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<50 /* pout_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<50 /* pout_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n"
+        "    set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<52 /* pgl_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<52 /* pgl_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n"
+        "    read this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<53 /* pdi_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<53 /* pdi_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<54 /* pop_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<54 /* pop_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n"
+        "    pointer pair this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<55 /* pins_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<55 /* pins_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<56 /* sprt0_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<56 /* sprt0_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<57 /* sprt1_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<57 /* sprt1_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<60 /* ill_pad */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<60 /* ill_pad */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n"
+        "    range of the Packet-CSR, but for an unused\n"
+        "    address.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<61 /* pipe_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<61 /* pipe_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PIPE_ERR]: Set when a PIPE value outside range is received.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_KEY_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<0 /* ked0_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* ked0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<30 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<1 /* ked0_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* ked0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<30 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<2 /* ked1_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* ked1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<30 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<3 /* ked1_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* ked1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<30 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PIP_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<3 /* prtnxa */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<3 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<6 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<4 /* badtag */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<4 /* badtag */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<6 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<5 /* skprunt */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<5 /* skprunt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<6 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+        "    This interrupt can occur with received PARTIAL\n"
+        "    packets that are truncated to SKIP bytes or\n"
+        "    smaller.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<6 /* todoovr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<6 /* todoovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<6 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<7 /* feperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<7 /* feperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<6 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<8 /* beperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<8 /* beperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<6 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<12 /* punyerr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<12 /* punyerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<6 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
+        "    stripping in IPD is enable\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DFA_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 1ull<<0 /* dblovf */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 1ull<<0 /* dblina */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<40 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
+        "    When set, the 20b accumulated doorbell register\n"
+        "    had overflowed (SW wrote too many doorbell requests).\n"
+        "    If the DBLINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    NOTE: Detection of a Doorbell Register overflow\n"
+        "    is a catastrophic error which may leave the DFA\n"
+        "    HW in an unrecoverable state.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 0x7ull<<1 /* dc0perr */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 0x7ull<<1 /* dc0pena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<40 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DC0PERR]: Cluster#0 RAM[3:1] Parity Error Detected\n"
+        "    See also DFA_DTCFADR register which contains the\n"
+        "    failing addresses for the internal node cache RAMs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 0x7ull<<4 /* dc1perr */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 0x7ull<<4 /* dc1pena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<40 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DC1PERR]: Cluster#1 RAM[3:1] Parity Error Detected\n"
+        "    See also DFA_DTCFADR register which contains the\n"
+        "    failing addresses for the internal node cache RAMs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 0x7ull<<7 /* dc2perr */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 0x7ull<<7 /* dc2pena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<40 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DC2PERR]: Cluster#2 RAM[3:1] Parity Error Detected\n"
+        "    See also DFA_DTCFADR register which contains the\n"
+        "    failing addresses for the internal node cache RAMs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 1ull<<13 /* dlc0_ovferr */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 1ull<<13 /* dlc0_ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<40 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DLC0_OVFERR]: DLC0 Fifo Overflow Error Detected\n"
+        "    This condition should NEVER architecturally occur, and\n"
+        "    is here in case HW credit/debit scheme is not working.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 1ull<<14 /* dlc1_ovferr */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 1ull<<14 /* dlc1_ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<40 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DLC1_OVFERR]: DLC1 Fifo Overflow Error Detected\n"
+        "    This condition should NEVER architecturally occur, and\n"
+        "    is here in case HW credit/debit scheme is not working.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 1ull<<17 /* dfanxm */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 1ull<<17 /* dfanxmena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<40 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DFANXM]: DFA Non-existent Memory Access\n"
+        "    For o68: DTEs (and backdoor CSR DFA Memory REGION reads)\n"
+        "    have access to the following 38bit L2/DRAM address space\n"
+        "    which maps to a 37bit physical DDR3 SDRAM address space.\n"
+        "    see:\n"
+        "    DR0: 0x0 0000 0000 0000 to 0x0 0000 0FFF FFFF\n"
+        "            maps to lower 256MB of physical DDR3 SDRAM\n"
+        "    DR1: 0x0 0000 2000 0000 to 0x0 0020 0FFF FFFF\n"
+        "            maps to upper 127.75GB of DDR3 SDRAM\n"
+        "               L2/DRAM address space                     Physical DDR3 SDRAM Address space\n"
+        "                 (38bit address)                           (37bit address)\n"
+        "                  +-----------+ 0x0020.0FFF.FFFF\n"
+        "                  |\n"
+        "                 ===   DR1   ===                          +-----------+ 0x001F.FFFF.FFFF\n"
+        "     (128GB-256MB)|           |                           |\n"
+        "                  |           |                     =>    |           |  (128GB-256MB)\n"
+        "                  +-----------+ 0x0000.1FFF.FFFF          |   DR1\n"
+        "          256MB   |   HOLE    |   (DO NOT USE)            |\n"
+        "                  +-----------+ 0x0000.0FFF.FFFF          +-----------+ 0x0000.0FFF.FFFF\n"
+        "          256MB   |    DR0    |                           |   DR0     |   (256MB)\n"
+        "                  +-----------+ 0x0000.0000.0000          +-----------+ 0x0000.0000.0000\n"
+        "    In the event the DFA generates a reference to the L2/DRAM\n"
+        "    address hole (0x0000.0FFF.FFFF - 0x0000.1FFF.FFFF) or to\n"
+        "    an address above 0x0020.0FFF.FFFF, the DFANXM programmable\n"
+        "    interrupt bit will be set.\n"
+        "    SWNOTE: Both the 1) SW DFA Graph compiler and the 2) SW NCB-Direct CSR\n"
+        "    accesses to DFA Memory REGION MUST avoid making references\n"
+        "    to these non-existent memory regions.\n"
+        "    NOTE: If DFANXM is set during a DFA Graph Walk operation,\n"
+        "    then the walk will prematurely terminate with RWORD0[REA]=ERR.\n"
+        "    If DFANXM is set during a NCB-Direct CSR read access to DFA\n"
+        "    Memory REGION, then the CSR read response data is forced to\n"
+        "    128'hBADE_FEED_DEAD_BEEF_FACE_CAFE_BEAD_C0DE. (NOTE: the QW\n"
+        "    being accessed, either the upper or lower QW will be returned).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 1ull<<18 /* replerr */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 1ull<<18 /* replerrena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<40 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[REPLERR]: DFA Illegal Replication Factor Error\n"
+        "    For o68: DFA only supports 1x, 2x, and 4x port replication.\n"
+        "    Legal configurations for memory are to support 2 port or\n"
+        "    4 port configurations.\n"
+        "    The REPLERR interrupt will be set in the following illegal\n"
+        "    configuration cases:\n"
+        "        1) An 8x replication factor is detected for any memory reference.\n"
+        "        2) A 4x replication factor is detected for any memory reference\n"
+        "           when only 2 memory ports are enabled.\n"
+        "    NOTE: If REPLERR is set during a DFA Graph Walk operation,\n"
+        "    then the walk will prematurely terminate with RWORD0[REA]=ERR.\n"
+        "    If REPLERR is set during a NCB-Direct CSR read access to DFA\n"
+        "    Memory REGION, then the CSR read response data is UNPREDICTABLE.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PKO_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* parity */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* parity */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<7 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<1 /* doorbell */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<1 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<7 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<2 /* currzero */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<2 /* currzero */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<7 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<3 /* loopback */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<3 /* loopback */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<7 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[LOOPBACK]: A packet was sent to an illegal loopback port\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<0 /* nderr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<0 /* nderr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n"
+        "    DPI received a NCB transaction on the outbound\n"
+        "    bus to the DPI deviceID, but the command was not\n"
+        "    recognized.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<1 /* nfovr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<1 /* nfovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n"
+        "    DPI can store upto 16 CSR request.  The FIFO will\n"
+        "    overflow if that number is exceeded.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 0xffull<<8 /* dmadbo */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 0xffull<<8 /* dmadbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n"
+        "    DPI has a 32-bit counter for each request's queue\n"
+        "    outstanding doorbell counts. Interrupt will fire\n"
+        "    if the count overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<16 /* req_badadr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<16 /* req_badadr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n"
+        "    Interrupt will fire if DPI forms an instruction\n"
+        "    fetch to the NULL pointer.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<17 /* req_badlen */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<17 /* req_badlen */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n"
+        "    Interrupt will fire if DPI forms an instruction\n"
+        "    fetch with length of zero.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<18 /* req_ovrflw */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<18 /* req_ovrflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n"
+        "    DPI tracks outstanding instructions fetches.\n"
+        "    Interrupt will fire when FIFO overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<19 /* req_undflw */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<19 /* req_undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n"
+        "    DPI tracks outstanding instructions fetches.\n"
+        "    Interrupt will fire when FIFO underflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<20 /* req_anull */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<20 /* req_anull */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n"
+        "    Fetched instruction word was 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<21 /* req_inull */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<21 /* req_inull */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n"
+        "    Next pointer was NULL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<22 /* req_badfil */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<22 /* req_badfil */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n"
+        "    Instruction fill when none outstanding.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<24 /* sprt0_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<24 /* sprt0_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<25 /* sprt1_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<25 /* sprt1_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_PKT_ERR_RSP */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_PKT_ERR_RSP;
+    info.status_mask        = 1ull<<0 /* pkterr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n"
+        "    the I/O subsystem.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_REQ_ERR_RSP */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_REQ_ERR_RSP;
+    info.status_mask        = 0xffull<<0 /* qerr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n"
+        "    ErrorResponse from the I/O subsystem.\n"
+        "    SW must clear the bit before the the cooresponding\n"
+        "    instruction queue will continue processing\n"
+        "    instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_REQ_ERR_RST */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_REQ_ERR_RST;
+    info.status_mask        = 0xffull<<0 /* qerr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n"
+        "    instruction because the source or destination\n"
+        "    was in reset.\n"
+        "    SW must clear the bit before the the cooresponding\n"
+        "    instruction queue will continue processing\n"
+        "    instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU2_SRC_PPX_IP2_MIO(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_RST_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<0 /* rst_link0 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<0 /* rst_link0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<63 /* rst */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n"
+        "    MIO_RST_CTL0[RST_LINK]=0.  Software must assert\n"
+        "    then de-assert CIU_SOFT_PRST[SOFT_PRST]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<1 /* rst_link1 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<1 /* rst_link1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<63 /* rst */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n"
+        "    MIO_RST_CTL1[RST_LINK]=0.  Software must assert\n"
+        "    then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<8 /* perst0 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<8 /* perst0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<63 /* rst */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1\n"
+        "    and MIO_RST_CTL0[RST_CHIP]=0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<9 /* perst1 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<9 /* perst1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<63 /* rst */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1\n"
+        "    and MIO_RST_CTL1[RST_CHIP]=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NDF_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<2 /* wdog */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<2 /* wdog */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<16 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<3 /* sm_bad */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<3 /* sm_bad */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<16 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<4 /* ecc_1bit */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<4 /* ecc_1bit */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<16 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<5 /* ecc_mult */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<5 /* ecc_mult */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<16 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<6 /* ovrf */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<6 /* ovrf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<16 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n"
+        "    fatal error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_BOOT_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<0 /* adr_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<0 /* adr_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<17 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<1 /* wait_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<1 /* wait_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<17 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU2_SUM_PPX_IP2(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_INT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 0xfull<<1 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<1 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 1ull<<0 /* nxm_wr_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* intr_nxm_wr_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 0xfull<<5 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<2 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_INT(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(1);
+    info.status_mask        = 0xfull<<1 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(1);
+    info.enable_mask        = 1ull<<1 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(1)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(1);
+    info.status_mask        = 1ull<<0 /* nxm_wr_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(1);
+    info.enable_mask        = 1ull<<0 /* intr_nxm_wr_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(1)[NXM_WR_ERR]: Write to non-existent memory\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(1);
+    info.status_mask        = 0xfull<<5 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(1);
+    info.enable_mask        = 1ull<<2 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(1)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_INT(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(2);
+    info.status_mask        = 0xfull<<1 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(2);
+    info.enable_mask        = 1ull<<1 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(2)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(2);
+    info.status_mask        = 1ull<<0 /* nxm_wr_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(2);
+    info.enable_mask        = 1ull<<0 /* intr_nxm_wr_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(2)[NXM_WR_ERR]: Write to non-existent memory\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(2);
+    info.status_mask        = 0xfull<<5 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(2);
+    info.enable_mask        = 1ull<<2 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(2)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_INT(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(3);
+    info.status_mask        = 0xfull<<1 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(3);
+    info.enable_mask        = 1ull<<1 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(3)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(3);
+    info.status_mask        = 1ull<<0 /* nxm_wr_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(3);
+    info.enable_mask        = 1ull<<0 /* intr_nxm_wr_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(3)[NXM_WR_ERR]: Write to non-existent memory\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(3);
+    info.status_mask        = 0xfull<<5 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(3);
+    info.enable_mask        = 1ull<<2 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(3)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<20 /* ptp_lost */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<20 /* ptp_lost */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n"
+        "    sent due to XSCOL\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 0xfull<<20 /* ptp_lost */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 0xfull<<20 /* ptp_lost */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[PTP_LOST]: A packet with a PTP request was not able to be\n"
+        "    sent due to XSCOL\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(2);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(2);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(2)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(2);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(2);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(2)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(2);
+    info.status_mask        = 0xfull<<20 /* ptp_lost */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(2);
+    info.enable_mask        = 0xfull<<20 /* ptp_lost */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(2)[PTP_LOST]: A packet with a PTP request was not able to be\n"
+        "    sent due to XSCOL\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(3);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(3);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(3)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(3);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(3);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(3)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(3);
+    info.status_mask        = 0xfull<<20 /* ptp_lost */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(3);
+    info.enable_mask        = 0xfull<<20 /* ptp_lost */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(3)[PTP_LOST]: A packet with a PTP request was not able to be\n"
+        "    sent due to XSCOL\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(4);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(4);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(4)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(4);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(4);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(4)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(4);
+    info.status_mask        = 0xfull<<20 /* ptp_lost */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(4);
+    info.enable_mask        = 0xfull<<20 /* ptp_lost */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(4)[PTP_LOST]: A packet with a PTP request was not able to be\n"
+        "    sent due to XSCOL\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,2);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,2);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,2)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,2);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,2);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,2);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,2);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,2);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,2);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,2);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,2);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,2)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,2);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,2);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,2);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,2);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,2);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,2);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,2);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,2);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,2)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,2);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,2);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,2)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,2);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,2);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,2);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,2);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,2);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,2);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,2);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,2);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,2)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,2);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,2);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,2);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,2);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,2);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,2);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,2);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,2);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,2)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,2);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,2);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,2)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,2);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,2);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,2);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,2);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,2);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,2);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,2);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,2);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,2)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,2);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,2);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,2);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,2);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,2);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,2);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,2);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,2);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,2)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,2);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,2);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,2)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,2);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,2);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,2);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,2);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,2);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,2);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,2);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,2);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,2)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,2);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,2);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,2);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,2);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,2);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,2);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,2);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,2);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,2)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,3);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,3);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,3)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,3);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,3);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,3);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,3);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,3);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,3);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,3);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,3);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,3)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,3);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,3);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,3);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,3);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,3);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,3);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,3);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,3);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,3)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,3);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,3);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,3)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,3);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,3);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,3);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,3);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,3);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,3);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,3);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,3);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,3)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,3);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,3);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,3);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,3);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,3);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,3);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,3);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,3);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,3)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,3);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,3);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,3)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,3);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,3);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,3);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,3);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,3);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,3);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,3);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,3);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,3)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,3);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,3);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,3);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,3);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,3);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,3);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,3);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,3);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,3)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,3);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,3);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2664;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,3)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,3);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,3);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2664;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,3);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,3);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2664;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,3);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,3);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2664;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,3);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,3);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2664;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,3)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,3);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,3);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2664;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,3);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,3);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2664;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,3);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,3);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2664;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,3);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,3);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2664;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,3)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,4);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,4);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,4)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,4);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,4);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,4);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,4);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,4);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,4);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,4);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,4);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,4)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,4);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,4);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,4);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,4);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,4);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,4);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,4);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,4);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,4)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,4);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,4);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,4)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,4);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,4);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,4);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,4);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,4);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,4);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,4);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,4);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,4)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,4);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,4);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,4);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,4);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,4);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,4);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,4);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,4);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,4)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,4);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,4);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,4)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,4);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,4);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,4);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,4);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,4);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,4);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,4);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,4);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,4)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,4);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,4);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,4);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,4);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,4);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,4);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,4);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,4);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,4)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,4);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,4);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,4)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,4);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,4);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,4);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,4);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,4);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,4);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,4);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,4);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,4)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,4);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,4);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,4);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,4);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,4);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,4);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,4);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,4);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,4)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<6 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<6 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<6 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(2);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(2);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(2)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(2);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(2);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(2)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(2);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(2);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(2)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(2);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(2);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(2)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(2);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(2);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(2)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(2);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(2);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(2)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(2);
+    info.status_mask        = 1ull<<6 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(2);
+    info.enable_mask        = 1ull<<6 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(2)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(3);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(3);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(3)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(3);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(3);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(3)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(3);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(3);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(3)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(3);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(3);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(3)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(3);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(3);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(3)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(3);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(3);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(3)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(3);
+    info.status_mask        = 1ull<<6 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(3);
+    info.enable_mask        = 1ull<<6 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(3)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(4);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(4);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(4)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(4);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(4);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(4)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(4);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(4);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(4)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(4);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(4);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(4)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(4);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(4);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(4)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(4);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(4);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(4)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(4);
+    info.status_mask        = 1ull<<6 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(4);
+    info.enable_mask        = 1ull<<6 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(4)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
+    fail |= cvmx_error_add(&info);
+
+    return fail;
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn68xxp1.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn68xxp1.c
new file mode 100644
index 0000000..282c9d1
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn68xxp1.c
@@ -0,0 +1,14007 @@
+/***********************license start***************
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Automatically generated error messages for cn68xxp1.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ * <hr><h2>Error tree for CN68XXP1</h2>
+ * @dot
+ * digraph cn68xxp1
+ * {
+ *     rankdir=LR;
+ *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
+ *     edge [fontsize=7, font=helvitica];
+ *     cvmx_root [label="ROOT|<root>root"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt [label="CIU2_SRC_PPX_IP2_PKT(0)|<mii>mii|<agl>agl|<ilk>ilk"];
+ *     cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:mii:e -> cvmx_mix0_isr [label="mii"];
+ *     cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
+ *     cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
+ *     cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
+ *     cvmx_ilk_gbl_int [label="ILK_GBL_INT|<rxf_lnk0_perr>rxf_lnk0_perr|<rxf_lnk1_perr>rxf_lnk1_perr|<rxf_ctl_perr>rxf_ctl_perr|<rxf_pop_empty>rxf_pop_empty|<rxf_push_full>rxf_push_full"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_gbl_int [label="ilk"];
+ *     cvmx_ilk_tx0_int [label="ILK_TXX_INT(0)|<txf_err>txf_err|<bad_seq>bad_seq|<bad_pipe>bad_pipe|<stat_cnt_ovfl>stat_cnt_ovfl"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_tx0_int [label="ilk"];
+ *     cvmx_ilk_tx1_int [label="ILK_TXX_INT(1)|<txf_err>txf_err|<bad_seq>bad_seq|<bad_pipe>bad_pipe|<stat_cnt_ovfl>stat_cnt_ovfl"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_tx1_int [label="ilk"];
+ *     cvmx_ilk_rx0_int [label="ILK_RXX_INT(0)|<lane_align_fail>lane_align_fail|<crc24_err>crc24_err|<word_sync_done>word_sync_done|<lane_align_done>lane_align_done|<stat_cnt_ovfl>stat_cnt_ovfl|<lane_bad_word>lane_bad_word|<pkt_drop_rxf>pkt_drop_rxf|<pkt_drop_rid>pkt_drop_rid"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx0_int [label="ilk"];
+ *     cvmx_ilk_rx1_int [label="ILK_RXX_INT(1)|<lane_align_fail>lane_align_fail|<crc24_err>crc24_err|<word_sync_done>word_sync_done|<lane_align_done>lane_align_done|<stat_cnt_ovfl>stat_cnt_ovfl|<lane_bad_word>lane_bad_word|<pkt_drop_rxf>pkt_drop_rxf|<pkt_drop_rid>pkt_drop_rid"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx1_int [label="ilk"];
+ *     cvmx_ilk_rx_lne0_int [label="ILK_RX_LNEX_INT(0)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne0_int [label="ilk"];
+ *     cvmx_ilk_rx_lne1_int [label="ILK_RX_LNEX_INT(1)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne1_int [label="ilk"];
+ *     cvmx_ilk_rx_lne2_int [label="ILK_RX_LNEX_INT(2)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne2_int [label="ilk"];
+ *     cvmx_ilk_rx_lne3_int [label="ILK_RX_LNEX_INT(3)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne3_int [label="ilk"];
+ *     cvmx_ilk_rx_lne4_int [label="ILK_RX_LNEX_INT(4)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne4_int [label="ilk"];
+ *     cvmx_ilk_rx_lne5_int [label="ILK_RX_LNEX_INT(5)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne5_int [label="ilk"];
+ *     cvmx_ilk_rx_lne6_int [label="ILK_RX_LNEX_INT(6)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne6_int [label="ilk"];
+ *     cvmx_ilk_rx_lne7_int [label="ILK_RX_LNEX_INT(7)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
+ *     cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne7_int [label="ilk"];
+ *     cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
+ *     cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
+ *     cvmx_ilk_gbl_int -> cvmx_ilk_tx0_int [style=invis];
+ *     cvmx_ilk_tx0_int -> cvmx_ilk_tx1_int [style=invis];
+ *     cvmx_ilk_tx1_int -> cvmx_ilk_rx0_int [style=invis];
+ *     cvmx_ilk_rx0_int -> cvmx_ilk_rx1_int [style=invis];
+ *     cvmx_ilk_rx1_int -> cvmx_ilk_rx_lne0_int [style=invis];
+ *     cvmx_ilk_rx_lne0_int -> cvmx_ilk_rx_lne1_int [style=invis];
+ *     cvmx_ilk_rx_lne1_int -> cvmx_ilk_rx_lne2_int [style=invis];
+ *     cvmx_ilk_rx_lne2_int -> cvmx_ilk_rx_lne3_int [style=invis];
+ *     cvmx_ilk_rx_lne3_int -> cvmx_ilk_rx_lne4_int [style=invis];
+ *     cvmx_ilk_rx_lne4_int -> cvmx_ilk_rx_lne5_int [style=invis];
+ *     cvmx_ilk_rx_lne5_int -> cvmx_ilk_rx_lne6_int [style=invis];
+ *     cvmx_ilk_rx_lne6_int -> cvmx_ilk_rx_lne7_int [style=invis];
+ *     cvmx_root:root:e -> cvmx_ciu2_src_pp0_ip2_pkt [label="root"];
+ *     cvmx_ciu2_src_pp0_ip2_rml [label="CIU2_SRC_PPX_IP2_RML(0)|<l2c>l2c|<fpa>fpa|<zip>zip|<ipd>ipd|<rad>rad|<sso>sso|<sli>sli|<key>key|<pip>pip|<dfa>dfa|<pko>pko|<dpi>dpi"];
+ *     cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<bigwr>bigwr|<bigrd>bigrd|<tad1>tad1|<tad0>tad0|<tad3>tad3|<tad2>tad2"];
+ *     cvmx_l2c_tad1_int [label="L2C_TADX_INT(1)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
+ *     cvmx_l2c_int_reg:tad1:e -> cvmx_l2c_tad1_int [label="tad1"];
+ *     cvmx_l2c_err_tdt1 [label="L2C_ERR_TDTX(1)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad1:e -> cvmx_l2c_err_tdt1 [label="tad1"];
+ *     cvmx_l2c_err_ttg1 [label="L2C_ERR_TTGX(1)|<noway>noway|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad1:e -> cvmx_l2c_err_ttg1 [label="tad1"];
+ *     cvmx_l2c_tad0_int [label="L2C_TADX_INT(0)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_tad0_int [label="tad0"];
+ *     cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
+ *     cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
+ *     cvmx_l2c_tad3_int [label="L2C_TADX_INT(3)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
+ *     cvmx_l2c_int_reg:tad3:e -> cvmx_l2c_tad3_int [label="tad3"];
+ *     cvmx_l2c_err_tdt3 [label="L2C_ERR_TDTX(3)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad3:e -> cvmx_l2c_err_tdt3 [label="tad3"];
+ *     cvmx_l2c_err_ttg3 [label="L2C_ERR_TTGX(3)|<noway>noway|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad3:e -> cvmx_l2c_err_ttg3 [label="tad3"];
+ *     cvmx_l2c_tad2_int [label="L2C_TADX_INT(2)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
+ *     cvmx_l2c_int_reg:tad2:e -> cvmx_l2c_tad2_int [label="tad2"];
+ *     cvmx_l2c_err_tdt2 [label="L2C_ERR_TDTX(2)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad2:e -> cvmx_l2c_err_tdt2 [label="tad2"];
+ *     cvmx_l2c_err_ttg2 [label="L2C_ERR_TTGX(2)|<noway>noway|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad2:e -> cvmx_l2c_err_ttg2 [label="tad2"];
+ *     cvmx_l2c_tad0_int -> cvmx_l2c_err_tdt0 [style=invis];
+ *     cvmx_l2c_err_tdt0 -> cvmx_l2c_err_ttg0 [style=invis];
+ *     cvmx_l2c_tad3_int -> cvmx_l2c_err_tdt3 [style=invis];
+ *     cvmx_l2c_err_tdt3 -> cvmx_l2c_err_ttg3 [style=invis];
+ *     cvmx_l2c_tad2_int -> cvmx_l2c_err_tdt2 [style=invis];
+ *     cvmx_l2c_err_tdt2 -> cvmx_l2c_err_ttg2 [style=invis];
+ *     cvmx_ciu2_src_pp0_ip2_rml:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
+ *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr|<pool0th>pool0th|<pool1th>pool1th|<pool2th>pool2th|<pool3th>pool3th|<pool4th>pool4th|<pool5th>pool5th|<pool6th>pool6th|<pool7th>pool7th|<free0>free0|<free1>free1|<free2>free2|<free3>free3|<free4>free4|<free5>free5|<free6>free6|<free7>free7|<free8>free8|<q8_und>q8_und|<q8_coff>q8_coff|<q8_perr>q8_perr|<pool8th>pool8th|<paddr_e>paddr_e"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
+ *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:zip:e -> cvmx_zip_error [label="zip"];
+ *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr|<sop>sop|<eop>eop|<dat>dat|<pw0_sbe>pw0_sbe|<pw0_dbe>pw0_dbe|<pw1_sbe>pw1_sbe|<pw1_dbe>pw1_dbe|<pw2_sbe>pw2_sbe|<pw2_dbe>pw2_dbe|<pw3_sbe>pw3_sbe|<pw3_dbe>pw3_dbe"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
+ *     cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:rad:e -> cvmx_rad_reg_error [label="rad"];
+ *     cvmx_sso_err [label="SSO_ERR|<iop>iop|<fidx_dbe>fidx_dbe|<idx_sbe>idx_sbe|<pnd_dbe0>pnd_dbe0|<oth_sbe1>oth_sbe1|<oth_dbe1>oth_dbe1|<oth_sbe0>oth_sbe0|<oth_dbe0>oth_dbe0|<pnd_sbe1>pnd_sbe1|<pnd_dbe1>pnd_dbe1|<pnd_sbe0>pnd_sbe0|<fpe>fpe|<awe>awe|<bfp>bfp|<idx_dbe>idx_dbe|<fidx_sbe>fidx_sbe"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:sso:e -> cvmx_sso_err [label="sso"];
+ *     cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<ill_pad>ill_pad|<pipe_err>pipe_err"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:sli:e -> cvmx_sli_int_sum [label="sli"];
+ *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:key:e -> cvmx_key_int_sum [label="key"];
+ *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:pip:e -> cvmx_pip_int_reg [label="pip"];
+ *     cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr|<dc1perr>dc1perr|<dc2perr>dc2perr|<dlc0_ovferr>dlc0_ovferr|<dlc1_ovferr>dlc1_ovferr|<dfanxm>dfanxm|<replerr>replerr"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:dfa:e -> cvmx_dfa_error [label="dfa"];
+ *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero|<loopback>loopback"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:pko:e -> cvmx_pko_reg_error [label="pko"];
+ *     cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
+ *     cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
+ *     cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
+ *     cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
+ *     cvmx_ciu2_src_pp0_ip2_rml:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
+ *     cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
+ *     cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
+ *     cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
+ *     cvmx_root:root:e -> cvmx_ciu2_src_pp0_ip2_rml [label="root"];
+ *     cvmx_ciu2_src_pp0_ip2_mio [label="CIU2_SRC_PPX_IP2_MIO(0)|<rst>rst|<nand>nand|<mio>mio"];
+ *     cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<perst0>perst0|<perst1>perst1"];
+ *     cvmx_ciu2_src_pp0_ip2_mio:rst:e -> cvmx_mio_rst_int [label="rst"];
+ *     cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"];
+ *     cvmx_ciu2_src_pp0_ip2_mio:nand:e -> cvmx_ndf_int [label="nand"];
+ *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
+ *     cvmx_ciu2_src_pp0_ip2_mio:mio:e -> cvmx_mio_boot_err [label="mio"];
+ *     cvmx_root:root:e -> cvmx_ciu2_src_pp0_ip2_mio [label="root"];
+ *     cvmx_ciu2_sum_pp0_ip2 [label="CIU2_SUM_PPX_IP2(0)|<mem>mem|<pkt>pkt"];
+ *     cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
+ *     cvmx_ciu2_sum_pp0_ip2:mem:e -> cvmx_lmc0_int [label="mem"];
+ *     cvmx_lmc1_int [label="LMCX_INT(1)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
+ *     cvmx_ciu2_sum_pp0_ip2:mem:e -> cvmx_lmc1_int [label="mem"];
+ *     cvmx_lmc2_int [label="LMCX_INT(2)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
+ *     cvmx_ciu2_sum_pp0_ip2:mem:e -> cvmx_lmc2_int [label="mem"];
+ *     cvmx_lmc3_int [label="LMCX_INT(3)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
+ *     cvmx_ciu2_sum_pp0_ip2:mem:e -> cvmx_lmc3_int [label="mem"];
+ *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_rx0_int_reg [label="pkt"];
+ *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_rx1_int_reg [label="pkt"];
+ *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_rx2_int_reg [label="pkt"];
+ *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_rx3_int_reg [label="pkt"];
+ *     cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx1_rx0_int_reg [label="pkt"];
+ *     cvmx_gmx2_rx0_int_reg [label="GMXX_RXX_INT_REG(0,2)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_rx0_int_reg [label="pkt"];
+ *     cvmx_gmx2_rx1_int_reg [label="GMXX_RXX_INT_REG(1,2)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_rx1_int_reg [label="pkt"];
+ *     cvmx_gmx2_rx2_int_reg [label="GMXX_RXX_INT_REG(2,2)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_rx2_int_reg [label="pkt"];
+ *     cvmx_gmx2_rx3_int_reg [label="GMXX_RXX_INT_REG(3,2)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_rx3_int_reg [label="pkt"];
+ *     cvmx_gmx3_rx0_int_reg [label="GMXX_RXX_INT_REG(0,3)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_rx0_int_reg [label="pkt"];
+ *     cvmx_gmx3_rx1_int_reg [label="GMXX_RXX_INT_REG(1,3)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_rx1_int_reg [label="pkt"];
+ *     cvmx_gmx3_rx2_int_reg [label="GMXX_RXX_INT_REG(2,3)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_rx2_int_reg [label="pkt"];
+ *     cvmx_gmx3_rx3_int_reg [label="GMXX_RXX_INT_REG(3,3)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_rx3_int_reg [label="pkt"];
+ *     cvmx_gmx4_rx0_int_reg [label="GMXX_RXX_INT_REG(0,4)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_rx0_int_reg [label="pkt"];
+ *     cvmx_gmx4_rx1_int_reg [label="GMXX_RXX_INT_REG(1,4)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_rx1_int_reg [label="pkt"];
+ *     cvmx_gmx4_rx2_int_reg [label="GMXX_RXX_INT_REG(2,4)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_rx2_int_reg [label="pkt"];
+ *     cvmx_gmx4_rx3_int_reg [label="GMXX_RXX_INT_REG(3,4)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_rx3_int_reg [label="pkt"];
+ *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_tx_int_reg [label="pkt"];
+ *     cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx1_tx_int_reg [label="pkt"];
+ *     cvmx_gmx2_tx_int_reg [label="GMXX_TX_INT_REG(2)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_tx_int_reg [label="pkt"];
+ *     cvmx_gmx3_tx_int_reg [label="GMXX_TX_INT_REG(3)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_tx_int_reg [label="pkt"];
+ *     cvmx_gmx4_tx_int_reg [label="GMXX_TX_INT_REG(4)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_tx_int_reg [label="pkt"];
+ *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs0_int0_reg [label="pkt"];
+ *     cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs0_int1_reg [label="pkt"];
+ *     cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs0_int2_reg [label="pkt"];
+ *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs0_int3_reg [label="pkt"];
+ *     cvmx_pcs1_int0_reg [label="PCSX_INTX_REG(0,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs1_int0_reg [label="pkt"];
+ *     cvmx_pcs2_int0_reg [label="PCSX_INTX_REG(0,2)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs2_int0_reg [label="pkt"];
+ *     cvmx_pcs2_int1_reg [label="PCSX_INTX_REG(1,2)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs2_int1_reg [label="pkt"];
+ *     cvmx_pcs2_int2_reg [label="PCSX_INTX_REG(2,2)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs2_int2_reg [label="pkt"];
+ *     cvmx_pcs2_int3_reg [label="PCSX_INTX_REG(3,2)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs2_int3_reg [label="pkt"];
+ *     cvmx_pcs3_int0_reg [label="PCSX_INTX_REG(0,3)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs3_int0_reg [label="pkt"];
+ *     cvmx_pcs3_int1_reg [label="PCSX_INTX_REG(1,3)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs3_int1_reg [label="pkt"];
+ *     cvmx_pcs3_int2_reg [label="PCSX_INTX_REG(2,3)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs3_int2_reg [label="pkt"];
+ *     cvmx_pcs3_int3_reg [label="PCSX_INTX_REG(3,3)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs3_int3_reg [label="pkt"];
+ *     cvmx_pcs4_int0_reg [label="PCSX_INTX_REG(0,4)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs4_int0_reg [label="pkt"];
+ *     cvmx_pcs4_int1_reg [label="PCSX_INTX_REG(1,4)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs4_int1_reg [label="pkt"];
+ *     cvmx_pcs4_int2_reg [label="PCSX_INTX_REG(2,4)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs4_int2_reg [label="pkt"];
+ *     cvmx_pcs4_int3_reg [label="PCSX_INTX_REG(3,4)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs4_int3_reg [label="pkt"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx0_int_reg [label="pkt"];
+ *     cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx1_int_reg [label="pkt"];
+ *     cvmx_pcsx2_int_reg [label="PCSXX_INT_REG(2)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx2_int_reg [label="pkt"];
+ *     cvmx_pcsx3_int_reg [label="PCSXX_INT_REG(3)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx3_int_reg [label="pkt"];
+ *     cvmx_pcsx4_int_reg [label="PCSXX_INT_REG(4)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx4_int_reg [label="pkt"];
+ *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
+ *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
+ *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
+ *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
+ *     cvmx_gmx1_rx0_int_reg -> cvmx_gmx2_rx0_int_reg [style=invis];
+ *     cvmx_gmx2_rx0_int_reg -> cvmx_gmx2_rx1_int_reg [style=invis];
+ *     cvmx_gmx2_rx1_int_reg -> cvmx_gmx2_rx2_int_reg [style=invis];
+ *     cvmx_gmx2_rx2_int_reg -> cvmx_gmx2_rx3_int_reg [style=invis];
+ *     cvmx_gmx2_rx3_int_reg -> cvmx_gmx3_rx0_int_reg [style=invis];
+ *     cvmx_gmx3_rx0_int_reg -> cvmx_gmx3_rx1_int_reg [style=invis];
+ *     cvmx_gmx3_rx1_int_reg -> cvmx_gmx3_rx2_int_reg [style=invis];
+ *     cvmx_gmx3_rx2_int_reg -> cvmx_gmx3_rx3_int_reg [style=invis];
+ *     cvmx_gmx3_rx3_int_reg -> cvmx_gmx4_rx0_int_reg [style=invis];
+ *     cvmx_gmx4_rx0_int_reg -> cvmx_gmx4_rx1_int_reg [style=invis];
+ *     cvmx_gmx4_rx1_int_reg -> cvmx_gmx4_rx2_int_reg [style=invis];
+ *     cvmx_gmx4_rx2_int_reg -> cvmx_gmx4_rx3_int_reg [style=invis];
+ *     cvmx_gmx4_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
+ *     cvmx_gmx0_tx_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
+ *     cvmx_gmx1_tx_int_reg -> cvmx_gmx2_tx_int_reg [style=invis];
+ *     cvmx_gmx2_tx_int_reg -> cvmx_gmx3_tx_int_reg [style=invis];
+ *     cvmx_gmx3_tx_int_reg -> cvmx_gmx4_tx_int_reg [style=invis];
+ *     cvmx_gmx4_tx_int_reg -> cvmx_pcs0_int0_reg [style=invis];
+ *     cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
+ *     cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
+ *     cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
+ *     cvmx_pcs0_int3_reg -> cvmx_pcs1_int0_reg [style=invis];
+ *     cvmx_pcs1_int0_reg -> cvmx_pcs2_int0_reg [style=invis];
+ *     cvmx_pcs2_int0_reg -> cvmx_pcs2_int1_reg [style=invis];
+ *     cvmx_pcs2_int1_reg -> cvmx_pcs2_int2_reg [style=invis];
+ *     cvmx_pcs2_int2_reg -> cvmx_pcs2_int3_reg [style=invis];
+ *     cvmx_pcs2_int3_reg -> cvmx_pcs3_int0_reg [style=invis];
+ *     cvmx_pcs3_int0_reg -> cvmx_pcs3_int1_reg [style=invis];
+ *     cvmx_pcs3_int1_reg -> cvmx_pcs3_int2_reg [style=invis];
+ *     cvmx_pcs3_int2_reg -> cvmx_pcs3_int3_reg [style=invis];
+ *     cvmx_pcs3_int3_reg -> cvmx_pcs4_int0_reg [style=invis];
+ *     cvmx_pcs4_int0_reg -> cvmx_pcs4_int1_reg [style=invis];
+ *     cvmx_pcs4_int1_reg -> cvmx_pcs4_int2_reg [style=invis];
+ *     cvmx_pcs4_int2_reg -> cvmx_pcs4_int3_reg [style=invis];
+ *     cvmx_pcs4_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
+ *     cvmx_pcsx0_int_reg -> cvmx_pcsx1_int_reg [style=invis];
+ *     cvmx_pcsx1_int_reg -> cvmx_pcsx2_int_reg [style=invis];
+ *     cvmx_pcsx2_int_reg -> cvmx_pcsx3_int_reg [style=invis];
+ *     cvmx_pcsx3_int_reg -> cvmx_pcsx4_int_reg [style=invis];
+ *     cvmx_root:root:e -> cvmx_ciu2_sum_pp0_ip2 [label="root"];
+ * }
+ * @enddot
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-csr-typedefs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#endif
+
+int cvmx_error_initialize_cn68xxp1(void);
+
+int cvmx_error_initialize_cn68xxp1(void)
+{
+    cvmx_error_info_t info;
+    int fail = 0;
+
+    /* CVMX_CIU2_SRC_PPX_IP2_PKT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIXX_ISR(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<0 /* odblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<0 /* ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<40 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU2_RAW_PKT[MII]\n"
+        "       bit is set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])\n"
+        "    and the local interrupt mask bit(OVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
+        "    future ODBELL writes don't exceed the size of the\n"
+        "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
+        "    SW must reclaim O-Ring Entries by writing to the\n"
+        "    MIX_ORCNT[ORCNT]. .\n"
+        "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the O-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<1 /* idblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<1 /* ivfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<40 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU2_RAW_PKT[MII]\n"
+        "       bit is set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])\n"
+        "    and the local interrupt mask bit(IVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
+        "    future IDBELL writes don't exceed the size of the\n"
+        "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
+        "    SW must reclaim I-Ring Entries by keeping track of the\n"
+        "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
+        "    total #packets(not IRing Entries) and SW must further\n"
+        "    keep track of the # of I-Ring Entries associated with\n"
+        "    each packet as they are processed.\n"
+        "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the I-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<4 /* data_drp */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<4 /* data_drpena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<40 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
+        "    If this does occur, the DATA_DRP is set and the\n"
+        "    CIU2_RAW_PKT[MII] bit is set.\n"
+        "    If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])\n"
+        "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
+        "    interrupt is reported for this event.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<5 /* irun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<5 /* irunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<40 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
+        "    NOTE: If an IRUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<6 /* orun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<6 /* orunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<40 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
+        "    NOTE: If an ORUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_BAD_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<32 /* ovrflw */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<33 /* txpop */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<34 /* txpsh */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<35 /* ovrflw1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<36 /* txpop1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<37 /* txpsh1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 0x3ull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 0x3ull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In MII/RGMII, one bit per port\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_RXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_TX_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 0x3ull<<2 /* undflw */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 0x3ull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<32 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_GBL_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_GBL_INT;
+    info.status_mask        = 1ull<<0 /* rxf_lnk0_perr */;
+    info.enable_addr        = CVMX_ILK_GBL_INT_EN;
+    info.enable_mask        = 1ull<<0 /* rxf_lnk0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_GBL_INT[RXF_LNK0_PERR]: RXF parity error occurred on RxLink0 packet data.  Packet will\n"
+        "    be marked with error at eop\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_GBL_INT;
+    info.status_mask        = 1ull<<1 /* rxf_lnk1_perr */;
+    info.enable_addr        = CVMX_ILK_GBL_INT_EN;
+    info.enable_mask        = 1ull<<1 /* rxf_lnk1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_GBL_INT[RXF_LNK1_PERR]: RXF parity error occurred on RxLink1 packet data\n"
+        "    Packet will be marked with error at eop\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_GBL_INT;
+    info.status_mask        = 1ull<<2 /* rxf_ctl_perr */;
+    info.enable_addr        = CVMX_ILK_GBL_INT_EN;
+    info.enable_mask        = 1ull<<2 /* rxf_ctl_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_GBL_INT[RXF_CTL_PERR]: RXF parity error occurred on sideband control signals.  Data\n"
+        "    cycle will be dropped.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_GBL_INT;
+    info.status_mask        = 1ull<<3 /* rxf_pop_empty */;
+    info.enable_addr        = CVMX_ILK_GBL_INT_EN;
+    info.enable_mask        = 1ull<<3 /* rxf_pop_empty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_GBL_INT[RXF_POP_EMPTY]: RXF underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_GBL_INT;
+    info.status_mask        = 1ull<<4 /* rxf_push_full */;
+    info.enable_addr        = CVMX_ILK_GBL_INT_EN;
+    info.enable_mask        = 1ull<<4 /* rxf_push_full */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_GBL_INT[RXF_PUSH_FULL]: RXF overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_TXX_INT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_TXX_INT(0);
+    info.status_mask        = 1ull<<0 /* txf_err */;
+    info.enable_addr        = CVMX_ILK_TXX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* txf_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_TXX_INT(0)[TXF_ERR]: TX fifo parity error occurred.  At EOP time, EOP_Format will\n"
+        "    reflect the error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_TXX_INT(0);
+    info.status_mask        = 1ull<<1 /* bad_seq */;
+    info.enable_addr        = CVMX_ILK_TXX_INT_EN(0);
+    info.enable_mask        = 1ull<<1 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_TXX_INT(0)[BAD_SEQ]: Received sequence is not SOP followed by 0 or more data cycles\n"
+        "    followed by EOP.  PKO config assigned multiple engines to the\n"
+        "    same ILK Tx Link.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_TXX_INT(0);
+    info.status_mask        = 1ull<<2 /* bad_pipe */;
+    info.enable_addr        = CVMX_ILK_TXX_INT_EN(0);
+    info.enable_mask        = 1ull<<2 /* bad_pipe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_TXX_INT(0)[BAD_PIPE]: Received a PKO port-pipe out of the range specified by\n"
+        "    ILK_TXX_PIPE\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_TXX_INT(0);
+    info.status_mask        = 1ull<<3 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_TXX_INT_EN(0);
+    info.enable_mask        = 1ull<<3 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_TXX_INT(0)[STAT_CNT_OVFL]: Statistics counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_TXX_INT(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_TXX_INT(1);
+    info.status_mask        = 1ull<<0 /* txf_err */;
+    info.enable_addr        = CVMX_ILK_TXX_INT_EN(1);
+    info.enable_mask        = 1ull<<0 /* txf_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_TXX_INT(1)[TXF_ERR]: TX fifo parity error occurred.  At EOP time, EOP_Format will\n"
+        "    reflect the error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_TXX_INT(1);
+    info.status_mask        = 1ull<<1 /* bad_seq */;
+    info.enable_addr        = CVMX_ILK_TXX_INT_EN(1);
+    info.enable_mask        = 1ull<<1 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_TXX_INT(1)[BAD_SEQ]: Received sequence is not SOP followed by 0 or more data cycles\n"
+        "    followed by EOP.  PKO config assigned multiple engines to the\n"
+        "    same ILK Tx Link.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_TXX_INT(1);
+    info.status_mask        = 1ull<<2 /* bad_pipe */;
+    info.enable_addr        = CVMX_ILK_TXX_INT_EN(1);
+    info.enable_mask        = 1ull<<2 /* bad_pipe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_TXX_INT(1)[BAD_PIPE]: Received a PKO port-pipe out of the range specified by\n"
+        "    ILK_TXX_PIPE\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_TXX_INT(1);
+    info.status_mask        = 1ull<<3 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_TXX_INT_EN(1);
+    info.enable_mask        = 1ull<<3 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_TXX_INT(1)[STAT_CNT_OVFL]: Statistics counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RXX_INT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(0);
+    info.status_mask        = 1ull<<0 /* lane_align_fail */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* lane_align_fail */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(0)[LANE_ALIGN_FAIL]: Lane Alignment fails (4 tries).  Hardware will repeat lane\n"
+        "    alignment until is succeeds or until ILK_RXx_CFG1[RX_ALIGN_ENA]\n"
+        "    is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(0);
+    info.status_mask        = 1ull<<1 /* crc24_err */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<1 /* crc24_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(0)[CRC24_ERR]: Burst CRC24 error.  All open packets will be receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(0);
+    info.status_mask        = 1ull<<2 /* word_sync_done */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<2 /* word_sync_done */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(0)[WORD_SYNC_DONE]: All enabled lanes have achieved word boundary lock and\n"
+        "    scrambler synchronization.  Lane alignment may now be enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(0);
+    info.status_mask        = 1ull<<3 /* lane_align_done */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<3 /* lane_align_done */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(0)[LANE_ALIGN_DONE]: Lane alignment successful\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(0);
+    info.status_mask        = 1ull<<4 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<4 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(0)[STAT_CNT_OVFL]: Statistics counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(0);
+    info.status_mask        = 1ull<<5 /* lane_bad_word */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<5 /* lane_bad_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(0)[LANE_BAD_WORD]: A lane encountered either a bad 64B/67B codeword or an unknown\n"
+        "    control word type.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(0);
+    info.status_mask        = 1ull<<6 /* pkt_drop_rxf */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<6 /* pkt_drop_rxf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(0)[PKT_DROP_RXF]: Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(0);
+    info.status_mask        = 1ull<<7 /* pkt_drop_rid */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<7 /* pkt_drop_rid */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(0)[PKT_DROP_RID]: Entire packet dropped due to the lack of reassembly-ids or\n"
+        "    because ILK_RXX_CFG1[PKT_ENA]=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RXX_INT(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(1);
+    info.status_mask        = 1ull<<0 /* lane_align_fail */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<0 /* lane_align_fail */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(1)[LANE_ALIGN_FAIL]: Lane Alignment fails (4 tries).  Hardware will repeat lane\n"
+        "    alignment until is succeeds or until ILK_RXx_CFG1[RX_ALIGN_ENA]\n"
+        "    is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(1);
+    info.status_mask        = 1ull<<1 /* crc24_err */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<1 /* crc24_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(1)[CRC24_ERR]: Burst CRC24 error.  All open packets will be receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(1);
+    info.status_mask        = 1ull<<2 /* word_sync_done */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<2 /* word_sync_done */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(1)[WORD_SYNC_DONE]: All enabled lanes have achieved word boundary lock and\n"
+        "    scrambler synchronization.  Lane alignment may now be enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(1);
+    info.status_mask        = 1ull<<3 /* lane_align_done */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<3 /* lane_align_done */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(1)[LANE_ALIGN_DONE]: Lane alignment successful\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(1);
+    info.status_mask        = 1ull<<4 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<4 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(1)[STAT_CNT_OVFL]: Statistics counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(1);
+    info.status_mask        = 1ull<<5 /* lane_bad_word */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<5 /* lane_bad_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(1)[LANE_BAD_WORD]: A lane encountered either a bad 64B/67B codeword or an unknown\n"
+        "    control word type.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(1);
+    info.status_mask        = 1ull<<6 /* pkt_drop_rxf */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<6 /* pkt_drop_rxf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(1)[PKT_DROP_RXF]: Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RXX_INT(1);
+    info.status_mask        = 1ull<<7 /* pkt_drop_rid */;
+    info.enable_addr        = CVMX_ILK_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<7 /* pkt_drop_rid */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RXX_INT(1)[PKT_DROP_RID]: Entire packet dropped due to the lack of reassembly-ids or\n"
+        "    because ILK_RXX_CFG1[PKT_ENA]=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RX_LNEX_INT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(0);
+    info.status_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(0)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(0);
+    info.status_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(0);
+    info.enable_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(0)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries).  Hardware will\n"
+        "    automatically attempt to regain word boundary sync\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(0);
+    info.status_mask        = 1ull<<2 /* crc32_err */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(0);
+    info.enable_mask        = 1ull<<2 /* crc32_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(0)[CRC32_ERR]: Diagnostic CRC32 errors\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(0);
+    info.status_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(0);
+    info.enable_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(0)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
+        "    (SYNC,SCRAM,SKIP,DIAG)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(0);
+    info.status_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(0);
+    info.enable_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(0)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
+        "    mismatches\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(0);
+    info.status_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(0);
+    info.enable_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(0)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(0);
+    info.status_mask        = 1ull<<6 /* stat_msg */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(0);
+    info.enable_mask        = 1ull<<6 /* stat_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(0)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
+        "    (healthy) to a '0' (problem)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(0);
+    info.status_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(0);
+    info.enable_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(0)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(0);
+    info.status_mask        = 1ull<<8 /* bad_64b67b */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(0);
+    info.enable_mask        = 1ull<<8 /* bad_64b67b */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(0)[BAD_64B67B]: Bad 64B/67B codeword encountered.  Once the bad word reaches\n"
+        "    the burst control unit (as deonted by\n"
+        "    ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
+        "    packets will receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RX_LNEX_INT(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(1);
+    info.status_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(1);
+    info.enable_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(1)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(1);
+    info.status_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(1);
+    info.enable_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(1)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries).  Hardware will\n"
+        "    automatically attempt to regain word boundary sync\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(1);
+    info.status_mask        = 1ull<<2 /* crc32_err */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(1);
+    info.enable_mask        = 1ull<<2 /* crc32_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(1)[CRC32_ERR]: Diagnostic CRC32 errors\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(1);
+    info.status_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(1);
+    info.enable_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(1)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
+        "    (SYNC,SCRAM,SKIP,DIAG)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(1);
+    info.status_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(1);
+    info.enable_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(1)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
+        "    mismatches\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(1);
+    info.status_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(1);
+    info.enable_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(1)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(1);
+    info.status_mask        = 1ull<<6 /* stat_msg */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(1);
+    info.enable_mask        = 1ull<<6 /* stat_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(1)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
+        "    (healthy) to a '0' (problem)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(1);
+    info.status_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(1);
+    info.enable_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(1)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(1);
+    info.status_mask        = 1ull<<8 /* bad_64b67b */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(1);
+    info.enable_mask        = 1ull<<8 /* bad_64b67b */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(1)[BAD_64B67B]: Bad 64B/67B codeword encountered.  Once the bad word reaches\n"
+        "    the burst control unit (as deonted by\n"
+        "    ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
+        "    packets will receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RX_LNEX_INT(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(2);
+    info.status_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(2);
+    info.enable_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(2)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(2);
+    info.status_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(2);
+    info.enable_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(2)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries).  Hardware will\n"
+        "    automatically attempt to regain word boundary sync\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(2);
+    info.status_mask        = 1ull<<2 /* crc32_err */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(2);
+    info.enable_mask        = 1ull<<2 /* crc32_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(2)[CRC32_ERR]: Diagnostic CRC32 errors\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(2);
+    info.status_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(2);
+    info.enable_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(2)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
+        "    (SYNC,SCRAM,SKIP,DIAG)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(2);
+    info.status_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(2);
+    info.enable_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(2)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
+        "    mismatches\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(2);
+    info.status_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(2);
+    info.enable_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(2)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(2);
+    info.status_mask        = 1ull<<6 /* stat_msg */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(2);
+    info.enable_mask        = 1ull<<6 /* stat_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(2)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
+        "    (healthy) to a '0' (problem)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(2);
+    info.status_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(2);
+    info.enable_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(2)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(2);
+    info.status_mask        = 1ull<<8 /* bad_64b67b */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(2);
+    info.enable_mask        = 1ull<<8 /* bad_64b67b */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(2)[BAD_64B67B]: Bad 64B/67B codeword encountered.  Once the bad word reaches\n"
+        "    the burst control unit (as deonted by\n"
+        "    ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
+        "    packets will receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RX_LNEX_INT(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(3);
+    info.status_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(3);
+    info.enable_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(3)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(3);
+    info.status_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(3);
+    info.enable_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(3)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries).  Hardware will\n"
+        "    automatically attempt to regain word boundary sync\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(3);
+    info.status_mask        = 1ull<<2 /* crc32_err */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(3);
+    info.enable_mask        = 1ull<<2 /* crc32_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(3)[CRC32_ERR]: Diagnostic CRC32 errors\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(3);
+    info.status_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(3);
+    info.enable_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(3)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
+        "    (SYNC,SCRAM,SKIP,DIAG)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(3);
+    info.status_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(3);
+    info.enable_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(3)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
+        "    mismatches\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(3);
+    info.status_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(3);
+    info.enable_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(3)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(3);
+    info.status_mask        = 1ull<<6 /* stat_msg */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(3);
+    info.enable_mask        = 1ull<<6 /* stat_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(3)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
+        "    (healthy) to a '0' (problem)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(3);
+    info.status_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(3);
+    info.enable_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(3)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(3);
+    info.status_mask        = 1ull<<8 /* bad_64b67b */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(3);
+    info.enable_mask        = 1ull<<8 /* bad_64b67b */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(3)[BAD_64B67B]: Bad 64B/67B codeword encountered.  Once the bad word reaches\n"
+        "    the burst control unit (as deonted by\n"
+        "    ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
+        "    packets will receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RX_LNEX_INT(4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(4);
+    info.status_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(4);
+    info.enable_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 4;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(4)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(4);
+    info.status_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(4);
+    info.enable_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 4;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(4)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries).  Hardware will\n"
+        "    automatically attempt to regain word boundary sync\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(4);
+    info.status_mask        = 1ull<<2 /* crc32_err */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(4);
+    info.enable_mask        = 1ull<<2 /* crc32_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 4;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(4)[CRC32_ERR]: Diagnostic CRC32 errors\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(4);
+    info.status_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(4);
+    info.enable_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 4;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(4)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
+        "    (SYNC,SCRAM,SKIP,DIAG)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(4);
+    info.status_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(4);
+    info.enable_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 4;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(4)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
+        "    mismatches\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(4);
+    info.status_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(4);
+    info.enable_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 4;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(4)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(4);
+    info.status_mask        = 1ull<<6 /* stat_msg */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(4);
+    info.enable_mask        = 1ull<<6 /* stat_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 4;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(4)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
+        "    (healthy) to a '0' (problem)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(4);
+    info.status_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(4);
+    info.enable_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 4;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(4)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(4);
+    info.status_mask        = 1ull<<8 /* bad_64b67b */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(4);
+    info.enable_mask        = 1ull<<8 /* bad_64b67b */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 4;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(4)[BAD_64B67B]: Bad 64B/67B codeword encountered.  Once the bad word reaches\n"
+        "    the burst control unit (as deonted by\n"
+        "    ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
+        "    packets will receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RX_LNEX_INT(5) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(5);
+    info.status_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(5);
+    info.enable_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 5;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(5)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(5);
+    info.status_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(5);
+    info.enable_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 5;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(5)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries).  Hardware will\n"
+        "    automatically attempt to regain word boundary sync\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(5);
+    info.status_mask        = 1ull<<2 /* crc32_err */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(5);
+    info.enable_mask        = 1ull<<2 /* crc32_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 5;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(5)[CRC32_ERR]: Diagnostic CRC32 errors\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(5);
+    info.status_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(5);
+    info.enable_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 5;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(5)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
+        "    (SYNC,SCRAM,SKIP,DIAG)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(5);
+    info.status_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(5);
+    info.enable_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 5;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(5)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
+        "    mismatches\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(5);
+    info.status_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(5);
+    info.enable_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 5;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(5)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(5);
+    info.status_mask        = 1ull<<6 /* stat_msg */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(5);
+    info.enable_mask        = 1ull<<6 /* stat_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 5;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(5)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
+        "    (healthy) to a '0' (problem)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(5);
+    info.status_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(5);
+    info.enable_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 5;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(5)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(5);
+    info.status_mask        = 1ull<<8 /* bad_64b67b */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(5);
+    info.enable_mask        = 1ull<<8 /* bad_64b67b */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 5;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(5)[BAD_64B67B]: Bad 64B/67B codeword encountered.  Once the bad word reaches\n"
+        "    the burst control unit (as deonted by\n"
+        "    ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
+        "    packets will receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RX_LNEX_INT(6) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(6);
+    info.status_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(6);
+    info.enable_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 6;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(6)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(6);
+    info.status_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(6);
+    info.enable_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 6;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(6)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries).  Hardware will\n"
+        "    automatically attempt to regain word boundary sync\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(6);
+    info.status_mask        = 1ull<<2 /* crc32_err */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(6);
+    info.enable_mask        = 1ull<<2 /* crc32_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 6;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(6)[CRC32_ERR]: Diagnostic CRC32 errors\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(6);
+    info.status_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(6);
+    info.enable_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 6;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(6)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
+        "    (SYNC,SCRAM,SKIP,DIAG)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(6);
+    info.status_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(6);
+    info.enable_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 6;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(6)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
+        "    mismatches\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(6);
+    info.status_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(6);
+    info.enable_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 6;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(6)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(6);
+    info.status_mask        = 1ull<<6 /* stat_msg */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(6);
+    info.enable_mask        = 1ull<<6 /* stat_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 6;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(6)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
+        "    (healthy) to a '0' (problem)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(6);
+    info.status_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(6);
+    info.enable_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 6;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(6)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(6);
+    info.status_mask        = 1ull<<8 /* bad_64b67b */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(6);
+    info.enable_mask        = 1ull<<8 /* bad_64b67b */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 6;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(6)[BAD_64B67B]: Bad 64B/67B codeword encountered.  Once the bad word reaches\n"
+        "    the burst control unit (as deonted by\n"
+        "    ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
+        "    packets will receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ILK_RX_LNEX_INT(7) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(7);
+    info.status_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(7);
+    info.enable_mask        = 1ull<<0 /* serdes_lock_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 7;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(7)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(7);
+    info.status_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(7);
+    info.enable_mask        = 1ull<<1 /* bdry_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 7;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(7)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries).  Hardware will\n"
+        "    automatically attempt to regain word boundary sync\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(7);
+    info.status_mask        = 1ull<<2 /* crc32_err */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(7);
+    info.enable_mask        = 1ull<<2 /* crc32_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 7;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(7)[CRC32_ERR]: Diagnostic CRC32 errors\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(7);
+    info.status_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(7);
+    info.enable_mask        = 1ull<<3 /* ukwn_cntl_word */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 7;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(7)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
+        "    (SYNC,SCRAM,SKIP,DIAG)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(7);
+    info.status_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(7);
+    info.enable_mask        = 1ull<<4 /* scrm_sync_loss */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 7;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(7)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
+        "    mismatches\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(7);
+    info.status_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(7);
+    info.enable_mask        = 1ull<<5 /* dskew_fifo_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 7;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(7)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(7);
+    info.status_mask        = 1ull<<6 /* stat_msg */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(7);
+    info.enable_mask        = 1ull<<6 /* stat_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 7;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(7)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
+        "    (healthy) to a '0' (problem)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(7);
+    info.status_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(7);
+    info.enable_mask        = 1ull<<7 /* stat_cnt_ovfl */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 7;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(7)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ILK_RX_LNEX_INT(7);
+    info.status_mask        = 1ull<<8 /* bad_64b67b */;
+    info.enable_addr        = CVMX_ILK_RX_LNEX_INT_EN(7);
+    info.enable_mask        = 1ull<<8 /* bad_64b67b */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ILK;
+    info.group_index        = 7;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
+    info.parent.status_mask = 1ull<<48 /* ilk */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ILK_RX_LNEX_INT(7)[BAD_64B67B]: Bad 64B/67B codeword encountered.  Once the bad word reaches\n"
+        "    the burst control unit (as deonted by\n"
+        "    ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
+        "    packets will receive an error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU2_SRC_PPX_IP2_RML(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<0 /* holerd */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<0 /* holerd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<48 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<1 /* holewr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<1 /* holewr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<48 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<2 /* vrtwr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<2 /* vrtwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<48 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
+        "    Set when L2C_VRT_MEM blocked a store.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<3 /* vrtidrng */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<3 /* vrtidrng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<48 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
+        "    Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
+        "    store.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<4 /* vrtadrng */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<4 /* vrtadrng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<48 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
+        "    Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
+        "    store.\n"
+        "    L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<5 /* vrtpe */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<5 /* vrtpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<48 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
+        "    Whenever an L2C_VRT_MEM read finds a parity error,\n"
+        "    that L2C_VRT_MEM cannot cause stores to be blocked.\n"
+        "    Software should correct the error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<6 /* bigwr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<6 /* bigwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<48 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[BIGWR]: Write reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<7 /* bigrd */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<7 /* bigrd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<48 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[BIGRD]: Read reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<48 /* l2c */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_TADX_INT(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(1);
+    info.status_mask        = 1ull<<0 /* l2dsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(1);
+    info.enable_mask        = 1ull<<0 /* l2dsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(1)[L2DSBE]: L2D Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(1);
+    info.status_mask        = 1ull<<1 /* l2ddbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(1);
+    info.enable_mask        = 1ull<<1 /* l2ddbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(1)[L2DDBE]: L2D Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(1);
+    info.status_mask        = 1ull<<2 /* tagsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(1);
+    info.enable_mask        = 1ull<<2 /* tagsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(1)[TAGSBE]: TAG Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(1);
+    info.status_mask        = 1ull<<3 /* tagdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(1);
+    info.enable_mask        = 1ull<<3 /* tagdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(1)[TAGDBE]: TAG Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(1);
+    info.status_mask        = 1ull<<4 /* vbfsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(1);
+    info.enable_mask        = 1ull<<4 /* vbfsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(1)[VBFSBE]: VBF Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VSBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(1);
+    info.status_mask        = 1ull<<5 /* vbfdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(1);
+    info.enable_mask        = 1ull<<5 /* vbfdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(1)[VBFDBE]: VBF Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VDBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(1);
+    info.status_mask        = 1ull<<6 /* noway */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(1);
+    info.enable_mask        = 1ull<<6 /* noway */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(1)[NOWAY]: No way available interrupt\n"
+        "    Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(1);
+    info.status_mask        = 1ull<<7 /* rddislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(1);
+    info.enable_mask        = 1ull<<7 /* rddislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(1)[RDDISLMC]: Illegal Read  to Disabled LMC Error\n"
+        "    A DRAM read  arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(1);
+    info.status_mask        = 1ull<<8 /* wrdislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(1);
+    info.enable_mask        = 1ull<<8 /* wrdislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(1)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
+        "    A DRAM write arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TDTX(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(1);
+    info.status_mask        = 1ull<<60 /* vsbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(1)[VSBE]: VBF Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(1);
+    info.status_mask        = 1ull<<61 /* vdbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(1)[VDBE]: VBF Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(1);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(1)[SBE]: L2D Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(1);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(1)[DBE]: L2D Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TTGX(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(1);
+    info.status_mask        = 1ull<<61 /* noway */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(1)[NOWAY]: No way was available for allocation.\n"
+        "    L2C sets NOWAY during its processing of a\n"
+        "    transaction whenever it needed/wanted to allocate\n"
+        "    a WAY in the L2 cache, but was unable to. NOWAY==1\n"
+        "    is (generally) not an indication that L2C failed to\n"
+        "    complete transactions. Rather, it is a hint of\n"
+        "    possible performance degradation. (For example, L2C\n"
+        "    must read-modify-write DRAM for every transaction\n"
+        "    that updates some, but not all, of the bytes in a\n"
+        "    cache block, misses in the L2 cache, and cannot\n"
+        "    allocate a WAY.) There is one \"failure\" case where\n"
+        "    L2C will set NOWAY: when it cannot leave a block\n"
+        "    locked in the L2 cache as part of a LCKL2\n"
+        "    transaction.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(1);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(1)[SBE]: Single-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(1);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<17 /* tad1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(1)[DBE]: Double-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_TADX_INT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<0 /* l2dsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<0 /* l2dsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[L2DSBE]: L2D Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<1 /* l2ddbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<1 /* l2ddbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[L2DDBE]: L2D Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<2 /* tagsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<2 /* tagsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[TAGSBE]: TAG Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<3 /* tagdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<3 /* tagdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[TAGDBE]: TAG Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<4 /* vbfsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<4 /* vbfsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VSBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<5 /* vbfdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<5 /* vbfdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VDBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<6 /* noway */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<6 /* noway */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[NOWAY]: No way available interrupt\n"
+        "    Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<7 /* rddislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<7 /* rddislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[RDDISLMC]: Illegal Read  to Disabled LMC Error\n"
+        "    A DRAM read  arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<8 /* wrdislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<8 /* wrdislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
+        "    A DRAM write arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TDTX(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<60 /* vsbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<61 /* vdbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TTGX(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<61 /* noway */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
+        "    L2C sets NOWAY during its processing of a\n"
+        "    transaction whenever it needed/wanted to allocate\n"
+        "    a WAY in the L2 cache, but was unable to. NOWAY==1\n"
+        "    is (generally) not an indication that L2C failed to\n"
+        "    complete transactions. Rather, it is a hint of\n"
+        "    possible performance degradation. (For example, L2C\n"
+        "    must read-modify-write DRAM for every transaction\n"
+        "    that updates some, but not all, of the bytes in a\n"
+        "    cache block, misses in the L2 cache, and cannot\n"
+        "    allocate a WAY.) There is one \"failure\" case where\n"
+        "    L2C will set NOWAY: when it cannot leave a block\n"
+        "    locked in the L2 cache as part of a LCKL2\n"
+        "    transaction.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_TADX_INT(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(3);
+    info.status_mask        = 1ull<<0 /* l2dsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(3);
+    info.enable_mask        = 1ull<<0 /* l2dsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(3)[L2DSBE]: L2D Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(3);
+    info.status_mask        = 1ull<<1 /* l2ddbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(3);
+    info.enable_mask        = 1ull<<1 /* l2ddbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(3)[L2DDBE]: L2D Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(3);
+    info.status_mask        = 1ull<<2 /* tagsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(3);
+    info.enable_mask        = 1ull<<2 /* tagsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(3)[TAGSBE]: TAG Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(3);
+    info.status_mask        = 1ull<<3 /* tagdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(3);
+    info.enable_mask        = 1ull<<3 /* tagdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(3)[TAGDBE]: TAG Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(3);
+    info.status_mask        = 1ull<<4 /* vbfsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(3);
+    info.enable_mask        = 1ull<<4 /* vbfsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(3)[VBFSBE]: VBF Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VSBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(3);
+    info.status_mask        = 1ull<<5 /* vbfdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(3);
+    info.enable_mask        = 1ull<<5 /* vbfdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(3)[VBFDBE]: VBF Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VDBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(3);
+    info.status_mask        = 1ull<<6 /* noway */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(3);
+    info.enable_mask        = 1ull<<6 /* noway */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(3)[NOWAY]: No way available interrupt\n"
+        "    Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(3);
+    info.status_mask        = 1ull<<7 /* rddislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(3);
+    info.enable_mask        = 1ull<<7 /* rddislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(3)[RDDISLMC]: Illegal Read  to Disabled LMC Error\n"
+        "    A DRAM read  arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(3);
+    info.status_mask        = 1ull<<8 /* wrdislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(3);
+    info.enable_mask        = 1ull<<8 /* wrdislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(3)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
+        "    A DRAM write arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TDTX(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(3);
+    info.status_mask        = 1ull<<60 /* vsbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(3)[VSBE]: VBF Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(3);
+    info.status_mask        = 1ull<<61 /* vdbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(3)[VDBE]: VBF Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(3);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(3)[SBE]: L2D Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(3);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(3)[DBE]: L2D Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TTGX(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(3);
+    info.status_mask        = 1ull<<61 /* noway */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(3)[NOWAY]: No way was available for allocation.\n"
+        "    L2C sets NOWAY during its processing of a\n"
+        "    transaction whenever it needed/wanted to allocate\n"
+        "    a WAY in the L2 cache, but was unable to. NOWAY==1\n"
+        "    is (generally) not an indication that L2C failed to\n"
+        "    complete transactions. Rather, it is a hint of\n"
+        "    possible performance degradation. (For example, L2C\n"
+        "    must read-modify-write DRAM for every transaction\n"
+        "    that updates some, but not all, of the bytes in a\n"
+        "    cache block, misses in the L2 cache, and cannot\n"
+        "    allocate a WAY.) There is one \"failure\" case where\n"
+        "    L2C will set NOWAY: when it cannot leave a block\n"
+        "    locked in the L2 cache as part of a LCKL2\n"
+        "    transaction.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(3);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(3)[SBE]: Single-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(3);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<19 /* tad3 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(3)[DBE]: Double-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_TADX_INT(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(2);
+    info.status_mask        = 1ull<<0 /* l2dsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(2);
+    info.enable_mask        = 1ull<<0 /* l2dsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(2)[L2DSBE]: L2D Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(2);
+    info.status_mask        = 1ull<<1 /* l2ddbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(2);
+    info.enable_mask        = 1ull<<1 /* l2ddbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(2)[L2DDBE]: L2D Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(2);
+    info.status_mask        = 1ull<<2 /* tagsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(2);
+    info.enable_mask        = 1ull<<2 /* tagsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(2)[TAGSBE]: TAG Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(2);
+    info.status_mask        = 1ull<<3 /* tagdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(2);
+    info.enable_mask        = 1ull<<3 /* tagdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(2)[TAGDBE]: TAG Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(2);
+    info.status_mask        = 1ull<<4 /* vbfsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(2);
+    info.enable_mask        = 1ull<<4 /* vbfsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(2)[VBFSBE]: VBF Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VSBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(2);
+    info.status_mask        = 1ull<<5 /* vbfdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(2);
+    info.enable_mask        = 1ull<<5 /* vbfdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(2)[VBFDBE]: VBF Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VDBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(2);
+    info.status_mask        = 1ull<<6 /* noway */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(2);
+    info.enable_mask        = 1ull<<6 /* noway */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(2)[NOWAY]: No way available interrupt\n"
+        "    Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(2);
+    info.status_mask        = 1ull<<7 /* rddislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(2);
+    info.enable_mask        = 1ull<<7 /* rddislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(2)[RDDISLMC]: Illegal Read  to Disabled LMC Error\n"
+        "    A DRAM read  arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(2);
+    info.status_mask        = 1ull<<8 /* wrdislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(2);
+    info.enable_mask        = 1ull<<8 /* wrdislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(2)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
+        "    A DRAM write arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TDTX(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(2);
+    info.status_mask        = 1ull<<60 /* vsbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(2)[VSBE]: VBF Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(2);
+    info.status_mask        = 1ull<<61 /* vdbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(2)[VDBE]: VBF Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(2);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(2)[SBE]: L2D Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(2);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(2)[DBE]: L2D Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TTGX(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(2);
+    info.status_mask        = 1ull<<61 /* noway */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(2)[NOWAY]: No way was available for allocation.\n"
+        "    L2C sets NOWAY during its processing of a\n"
+        "    transaction whenever it needed/wanted to allocate\n"
+        "    a WAY in the L2 cache, but was unable to. NOWAY==1\n"
+        "    is (generally) not an indication that L2C failed to\n"
+        "    complete transactions. Rather, it is a hint of\n"
+        "    possible performance degradation. (For example, L2C\n"
+        "    must read-modify-write DRAM for every transaction\n"
+        "    that updates some, but not all, of the bytes in a\n"
+        "    cache block, misses in the L2 cache, and cannot\n"
+        "    allocate a WAY.) There is one \"failure\" case where\n"
+        "    L2C will set NOWAY: when it cannot leave a block\n"
+        "    locked in the L2 cache as part of a LCKL2\n"
+        "    transaction.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(2);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(2)[SBE]: Single-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(2);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<18 /* tad2 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(2)[DBE]: Double-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_FPA_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<0 /* fed0_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* fed0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<1 /* fed0_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* fed0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<2 /* fed1_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* fed1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<3 /* fed1_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* fed1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<4 /* q0_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* q0_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<5 /* q0_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* q0_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<6 /* q0_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* q0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<7 /* q1_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* q1_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<8 /* q1_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* q1_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<9 /* q1_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* q1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<10 /* q2_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* q2_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<11 /* q2_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* q2_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<12 /* q2_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* q2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<13 /* q3_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* q3_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<14 /* q3_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* q3_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<15 /* q3_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* q3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<16 /* q4_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* q4_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<17 /* q4_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* q4_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<18 /* q4_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* q4_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<19 /* q5_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* q5_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<20 /* q5_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* q5_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<21 /* q5_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* q5_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<22 /* q6_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* q6_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<23 /* q6_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* q6_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<24 /* q6_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* q6_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<25 /* q7_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* q7_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<26 /* q7_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* q7_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<27 /* q7_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* q7_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<28 /* pool0th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<28 /* pool0th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL0TH]: Set when FPA_QUE0_AVAILABLE is equal to\n"
+        "    FPA_POOL0_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<29 /* pool1th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<29 /* pool1th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL1TH]: Set when FPA_QUE1_AVAILABLE is equal to\n"
+        "    FPA_POOL1_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<30 /* pool2th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<30 /* pool2th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL2TH]: Set when FPA_QUE2_AVAILABLE is equal to\n"
+        "    FPA_POOL2_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<31 /* pool3th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<31 /* pool3th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL3TH]: Set when FPA_QUE3_AVAILABLE is equal to\n"
+        "    FPA_POOL3_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<32 /* pool4th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<32 /* pool4th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL4TH]: Set when FPA_QUE4_AVAILABLE is equal to\n"
+        "    FPA_POOL4_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<33 /* pool5th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<33 /* pool5th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL5TH]: Set when FPA_QUE5_AVAILABLE is equal to\n"
+        "    FPA_POOL5_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<34 /* pool6th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<34 /* pool6th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL6TH]: Set when FPA_QUE6_AVAILABLE is equal to\n"
+        "    FPA_POOL6_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<35 /* pool7th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<35 /* pool7th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL7TH]: Set when FPA_QUE7_AVAILABLE is equal to\n"
+        "    FPA_POOL7_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<36 /* free0 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<36 /* free0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE0]: When a pointer for POOL0 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<37 /* free1 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<37 /* free1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE1]: When a pointer for POOL1 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<38 /* free2 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<38 /* free2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE2]: When a pointer for POOL2 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<39 /* free3 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<39 /* free3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE3]: When a pointer for POOL3 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<40 /* free4 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<40 /* free4 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE4]: When a pointer for POOL4 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<41 /* free5 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<41 /* free5 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE5]: When a pointer for POOL5 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<42 /* free6 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<42 /* free6 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE6]: When a pointer for POOL6 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<43 /* free7 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<43 /* free7 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE7]: When a pointer for POOL7 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<44 /* free8 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<44 /* free8 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE8]: When a pointer for POOL8 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<45 /* q8_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<45 /* q8_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q8_UND]: Set when a Queue8 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<46 /* q8_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<46 /* q8_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q8_COFF]: Set when a Queue8 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<47 /* q8_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<47 /* q8_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q8_PERR]: Set when a Queue8 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<48 /* pool8th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<48 /* pool8th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL8TH]: Set when FPA_QUE8_AVAILABLE is equal to\n"
+        "    FPA_POOL8_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<49 /* paddr_e */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<49 /* paddr_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<4 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[PADDR_E]: Set when a pointer address does not fall in the\n"
+        "    address range for a pool specified by\n"
+        "    FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ZIP_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ZIP_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_ZIP_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<24 /* zip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IPD_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<0 /* prc_par0 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* prc_par0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+        "    [31:0] of the PBM memory.\n"
+        "    NOT USED ON o68.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<1 /* prc_par1 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* prc_par1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+        "    [63:32] of the PBM memory.\n"
+        "    NOT USED ON o68.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<2 /* prc_par2 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* prc_par2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+        "    [95:64] of the PBM memory.\n"
+        "    NOT USED ON o68.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<3 /* prc_par3 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* prc_par3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+        "    [127:96] of the PBM memory.\n"
+        "    NOT USED ON o68.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<4 /* bp_sub */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* bp_sub */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+        "    supplied illegal value.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* dc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<6 /* cc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* cc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<7 /* c_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* c_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<8 /* d_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* d_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<9 /* bc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* bc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<12 /* sop */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    reasm-id for a packet.\n"
+        "    The first detected error associated with bits [14:12]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n"
+        "    Also see IPD_PKT_ERR.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<13 /* eop */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    reasm-id for a packet.\n"
+        "    The first detected error associated with bits [14:12]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n"
+        "    Also see IPD_PKT_ERR.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<14 /* dat */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[DAT]: Set when a data arrives before a SOP for the same\n"
+        "    reasm-id for a packet.\n"
+        "    The first detected error associated with bits [14:12]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n"
+        "    Also see IPD_PKT_ERR.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<15 /* pw0_sbe */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* pw0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PW0_SBE]: Packet memory 0 had ECC SBE.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<16 /* pw0_dbe */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* pw0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PW0_DBE]: Packet memory 0 had ECC DBE.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<17 /* pw1_sbe */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* pw1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PW1_SBE]: Packet memory 1 had ECC SBE.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<18 /* pw1_dbe */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* pw1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PW1_DBE]: Packet memory 1 had ECC DBE.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<19 /* pw2_sbe */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* pw2_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PW2_SBE]: Packet memory 2 had ECC SBE.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<20 /* pw2_dbe */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* pw2_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PW2_DBE]: Packet memory 2 had ECC DBE.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<21 /* pw3_sbe */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* pw3_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PW3_SBE]: Packet memory 3 had ECC SBE.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<22 /* pw3_dbe */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* pw3_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<5 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PW3_DBE]: Packet memory 3 had ECC DBE.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_RAD_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_RAD_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_RAD_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<29 /* rad */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_SSO_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 0x7ffull<<32 /* iop */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 0x7ffull<<32 /* iop_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[IOP]: Illegal operation errors\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<1 /* fidx_dbe */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<1 /* fidx_dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[FIDX_DBE]: Double bit error for FIDX RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<2 /* idx_sbe */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<2 /* idx_sbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[IDX_SBE]: Single bit error for IDX RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<11 /* pnd_dbe0 */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<11 /* pnd_dbe0_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[PND_DBE0]: Double bit error for even PND RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<4 /* oth_sbe1 */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<4 /* oth_sbe1_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[OTH_SBE1]: Single bit error for odd OTH RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<5 /* oth_dbe1 */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<5 /* oth_dbe1_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[OTH_DBE1]: Double bit error for odd OTH RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<6 /* oth_sbe0 */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<6 /* oth_sbe0_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[OTH_SBE0]: Single bit error for even OTH RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<7 /* oth_dbe0 */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<7 /* oth_dbe0_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[OTH_DBE0]: Double bit error for even OTH RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<8 /* pnd_sbe1 */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<8 /* pnd_sbe1_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[PND_SBE1]: Single bit error for odd PND RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<9 /* pnd_dbe1 */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<9 /* pnd_dbe1_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[PND_DBE1]: Double bit error for odd PND RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<10 /* pnd_sbe0 */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<10 /* pnd_sbe0_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[PND_SBE0]: Single bit error for even PND RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<45 /* fpe */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<45 /* fpe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[FPE]: Free page error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<46 /* awe */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<46 /* awe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[AWE]: Out-of-memory error (ADDWQ Request is dropped)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<47 /* bfp */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<47 /* bfp_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[BFP]: Bad Fill Packet error\n"
+        "    Last byte of the fill packet did not match 8'h1a\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<3 /* idx_dbe */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<3 /* idx_dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[IDX_DBE]: Double bit error for IDX RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SSO_ERR;
+    info.status_mask        = 1ull<<0 /* fidx_sbe */;
+    info.enable_addr        = CVMX_SSO_ERR_ENB;
+    info.enable_mask        = 1ull<<0 /* fidx_sbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<16 /* sso */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SSO_ERR[FIDX_SBE]: Single bit error for FIDX RAM\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEXP_SLI_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<0 /* rml_to */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<0 /* rml_to */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n"
+        "    within 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<1 /* reserved_1_1 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<1 /* reserved_1_1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<2 /* bar0_to */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<2 /* bar0_to */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
+        "    read-data/commit in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<3 /* iob2big */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<3 /* iob2big */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 0x3ull<<6 /* reserved_6_7 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 0x3ull<<6 /* reserved_6_7 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<8 /* m0_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<8 /* m0_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<9 /* m0_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<9 /* m0_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n"
+        "    from MAC 0. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<10 /* m0_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<10 /* m0_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<11 /* m0_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<11 /* m0_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n"
+        "    from MAC 0. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<12 /* m1_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<12 /* m1_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<13 /* m1_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<13 /* m1_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n"
+        "    from MAC 1. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<14 /* m1_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<14 /* m1_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<15 /* m1_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<15 /* m1_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n"
+        "    from MAC 1. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<48 /* pidbof */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<48 /* pidbof */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
+        "    doorbell can be found in DPI_PINT_INFO[PIDBOF]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<49 /* psldbof */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<49 /* psldbof */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
+        "    doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<50 /* pout_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<50 /* pout_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n"
+        "    set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<52 /* pgl_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<52 /* pgl_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n"
+        "    read this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<53 /* pdi_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<53 /* pdi_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<54 /* pop_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<54 /* pop_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n"
+        "    pointer pair this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<55 /* pins_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<55 /* pins_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<56 /* sprt0_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<56 /* sprt0_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<57 /* sprt1_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<57 /* sprt1_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<60 /* ill_pad */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<60 /* ill_pad */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n"
+        "    range of the Packet-CSR, but for an unused\n"
+        "    address.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<61 /* pipe_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<61 /* pipe_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<32 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PIPE_ERR]: Set when a PIPE value outside range is received.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_KEY_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<0 /* ked0_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* ked0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<30 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<1 /* ked0_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* ked0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<30 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<2 /* ked1_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* ked1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<30 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<3 /* ked1_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* ked1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<30 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PIP_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<3 /* prtnxa */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<3 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<6 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<4 /* badtag */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<4 /* badtag */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<6 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<5 /* skprunt */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<5 /* skprunt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<6 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+        "    This interrupt can occur with received PARTIAL\n"
+        "    packets that are truncated to SKIP bytes or\n"
+        "    smaller.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<6 /* todoovr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<6 /* todoovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<6 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<7 /* feperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<7 /* feperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<6 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<8 /* beperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<8 /* beperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<6 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<12 /* punyerr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<12 /* punyerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<6 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
+        "    stripping in IPD is enable\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DFA_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 1ull<<0 /* dblovf */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 1ull<<0 /* dblina */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<40 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
+        "    When set, the 20b accumulated doorbell register\n"
+        "    had overflowed (SW wrote too many doorbell requests).\n"
+        "    If the DBLINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    NOTE: Detection of a Doorbell Register overflow\n"
+        "    is a catastrophic error which may leave the DFA\n"
+        "    HW in an unrecoverable state.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 0x7ull<<1 /* dc0perr */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 0x7ull<<1 /* dc0pena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<40 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DC0PERR]: Cluster#0 RAM[3:1] Parity Error Detected\n"
+        "    See also DFA_DTCFADR register which contains the\n"
+        "    failing addresses for the internal node cache RAMs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 0x7ull<<4 /* dc1perr */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 0x7ull<<4 /* dc1pena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<40 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DC1PERR]: Cluster#1 RAM[3:1] Parity Error Detected\n"
+        "    See also DFA_DTCFADR register which contains the\n"
+        "    failing addresses for the internal node cache RAMs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 0x7ull<<7 /* dc2perr */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 0x7ull<<7 /* dc2pena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<40 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DC2PERR]: Cluster#2 RAM[3:1] Parity Error Detected\n"
+        "    See also DFA_DTCFADR register which contains the\n"
+        "    failing addresses for the internal node cache RAMs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 1ull<<13 /* dlc0_ovferr */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 1ull<<13 /* dlc0_ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<40 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DLC0_OVFERR]: DLC0 Fifo Overflow Error Detected\n"
+        "    This condition should NEVER architecturally occur, and\n"
+        "    is here in case HW credit/debit scheme is not working.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 1ull<<14 /* dlc1_ovferr */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 1ull<<14 /* dlc1_ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<40 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DLC1_OVFERR]: DLC1 Fifo Overflow Error Detected\n"
+        "    This condition should NEVER architecturally occur, and\n"
+        "    is here in case HW credit/debit scheme is not working.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 1ull<<17 /* dfanxm */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 1ull<<17 /* dfanxmena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<40 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DFANXM]: DFA Non-existent Memory Access\n"
+        "    For o68: DTEs (and backdoor CSR DFA Memory REGION reads)\n"
+        "    have access to the following 38bit L2/DRAM address space\n"
+        "    which maps to a 37bit physical DDR3 SDRAM address space.\n"
+        "    see:\n"
+        "    DR0: 0x0 0000 0000 0000 to 0x0 0000 0FFF FFFF\n"
+        "            maps to lower 256MB of physical DDR3 SDRAM\n"
+        "    DR1: 0x0 0000 2000 0000 to 0x0 0020 0FFF FFFF\n"
+        "            maps to upper 127.75GB of DDR3 SDRAM\n"
+        "               L2/DRAM address space                     Physical DDR3 SDRAM Address space\n"
+        "                 (38bit address)                           (37bit address)\n"
+        "                  +-----------+ 0x0020.0FFF.FFFF\n"
+        "                  |\n"
+        "                 ===   DR1   ===                          +-----------+ 0x001F.FFFF.FFFF\n"
+        "     (128GB-256MB)|           |                           |\n"
+        "                  |           |                     =>    |           |  (128GB-256MB)\n"
+        "                  +-----------+ 0x0000.1FFF.FFFF          |   DR1\n"
+        "          256MB   |   HOLE    |   (DO NOT USE)            |\n"
+        "                  +-----------+ 0x0000.0FFF.FFFF          +-----------+ 0x0000.0FFF.FFFF\n"
+        "          256MB   |    DR0    |                           |   DR0     |   (256MB)\n"
+        "                  +-----------+ 0x0000.0000.0000          +-----------+ 0x0000.0000.0000\n"
+        "    In the event the DFA generates a reference to the L2/DRAM\n"
+        "    address hole (0x0000.0FFF.FFFF - 0x0000.1FFF.FFFF) or to\n"
+        "    an address above 0x0020.0FFF.FFFF, the DFANXM programmable\n"
+        "    interrupt bit will be set.\n"
+        "    SWNOTE: Both the 1) SW DFA Graph compiler and the 2) SW NCB-Direct CSR\n"
+        "    accesses to DFA Memory REGION MUST avoid making references\n"
+        "    to these non-existent memory regions.\n"
+        "    NOTE: If DFANXM is set during a DFA Graph Walk operation,\n"
+        "    then the walk will prematurely terminate with RWORD0[REA]=ERR.\n"
+        "    If DFANXM is set during a NCB-Direct CSR read access to DFA\n"
+        "    Memory REGION, then the CSR read response data is forced to\n"
+        "    128'hBADE_FEED_DEAD_BEEF_FACE_CAFE_BEAD_C0DE. (NOTE: the QW\n"
+        "    being accessed, either the upper or lower QW will be returned).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 1ull<<18 /* replerr */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 1ull<<18 /* replerrena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<40 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[REPLERR]: DFA Illegal Replication Factor Error\n"
+        "    For o68: DFA only supports 1x, 2x, and 4x port replication.\n"
+        "    Legal configurations for memory are to support 2 port or\n"
+        "    4 port configurations.\n"
+        "    The REPLERR interrupt will be set in the following illegal\n"
+        "    configuration cases:\n"
+        "        1) An 8x replication factor is detected for any memory reference.\n"
+        "        2) A 4x replication factor is detected for any memory reference\n"
+        "           when only 2 memory ports are enabled.\n"
+        "    NOTE: If REPLERR is set during a DFA Graph Walk operation,\n"
+        "    then the walk will prematurely terminate with RWORD0[REA]=ERR.\n"
+        "    If REPLERR is set during a NCB-Direct CSR read access to DFA\n"
+        "    Memory REGION, then the CSR read response data is UNPREDICTABLE.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PKO_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* parity */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* parity */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<7 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<1 /* doorbell */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<1 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<7 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<2 /* currzero */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<2 /* currzero */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<7 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<3 /* loopback */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<3 /* loopback */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<7 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[LOOPBACK]: A packet was sent to an illegal loopback port\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<0 /* nderr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<0 /* nderr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n"
+        "    DPI received a NCB transaction on the outbound\n"
+        "    bus to the DPI deviceID, but the command was not\n"
+        "    recognized.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<1 /* nfovr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<1 /* nfovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n"
+        "    DPI can store upto 16 CSR request.  The FIFO will\n"
+        "    overflow if that number is exceeded.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 0xffull<<8 /* dmadbo */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 0xffull<<8 /* dmadbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n"
+        "    DPI has a 32-bit counter for each request's queue\n"
+        "    outstanding doorbell counts. Interrupt will fire\n"
+        "    if the count overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<16 /* req_badadr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<16 /* req_badadr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n"
+        "    Interrupt will fire if DPI forms an instruction\n"
+        "    fetch to the NULL pointer.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<17 /* req_badlen */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<17 /* req_badlen */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n"
+        "    Interrupt will fire if DPI forms an instruction\n"
+        "    fetch with length of zero.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<18 /* req_ovrflw */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<18 /* req_ovrflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n"
+        "    DPI tracks outstanding instructions fetches.\n"
+        "    Interrupt will fire when FIFO overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<19 /* req_undflw */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<19 /* req_undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n"
+        "    DPI tracks outstanding instructions fetches.\n"
+        "    Interrupt will fire when FIFO underflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<20 /* req_anull */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<20 /* req_anull */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n"
+        "    Fetched instruction word was 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<21 /* req_inull */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<21 /* req_inull */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n"
+        "    Next pointer was NULL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<22 /* req_badfil */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<22 /* req_badfil */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n"
+        "    Instruction fill when none outstanding.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<24 /* sprt0_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<24 /* sprt0_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<25 /* sprt1_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<25 /* sprt1_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_PKT_ERR_RSP */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_PKT_ERR_RSP;
+    info.status_mask        = 1ull<<0 /* pkterr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n"
+        "    the I/O subsystem.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_REQ_ERR_RSP */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_REQ_ERR_RSP;
+    info.status_mask        = 0xffull<<0 /* qerr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n"
+        "    ErrorResponse from the I/O subsystem.\n"
+        "    SW must clear the bit before the the cooresponding\n"
+        "    instruction queue will continue processing\n"
+        "    instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_REQ_ERR_RST */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_REQ_ERR_RST;
+    info.status_mask        = 0xffull<<0 /* qerr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
+    info.parent.status_mask = 1ull<<33 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n"
+        "    instruction because the source or destination\n"
+        "    was in reset.\n"
+        "    SW must clear the bit before the the cooresponding\n"
+        "    instruction queue will continue processing\n"
+        "    instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU2_SRC_PPX_IP2_MIO(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_RST_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<0 /* rst_link0 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<0 /* rst_link0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<63 /* rst */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n"
+        "    MIO_RST_CTL0[RST_LINK]=0.  Software must assert\n"
+        "    then de-assert CIU_SOFT_PRST[SOFT_PRST]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<1 /* rst_link1 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<1 /* rst_link1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<63 /* rst */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n"
+        "    MIO_RST_CTL1[RST_LINK]=0.  Software must assert\n"
+        "    then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<8 /* perst0 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<8 /* perst0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<63 /* rst */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1\n"
+        "    and MIO_RST_CTL0[RST_CHIP]=0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<9 /* perst1 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<9 /* perst1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<63 /* rst */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1\n"
+        "    and MIO_RST_CTL1[RST_CHIP]=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NDF_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<2 /* wdog */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<2 /* wdog */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<16 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<3 /* sm_bad */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<3 /* sm_bad */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<16 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<4 /* ecc_1bit */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<4 /* ecc_1bit */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<16 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<5 /* ecc_mult */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<5 /* ecc_mult */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<16 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<6 /* ovrf */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<6 /* ovrf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<16 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n"
+        "    fatal error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_BOOT_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<0 /* adr_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<0 /* adr_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<17 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<1 /* wait_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<1 /* wait_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
+    info.parent.status_mask = 1ull<<17 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU2_SUM_PPX_IP2(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_INT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 0xfull<<1 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<1 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 1ull<<0 /* nxm_wr_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* intr_nxm_wr_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 0xfull<<5 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<2 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_INT(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(1);
+    info.status_mask        = 0xfull<<1 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(1);
+    info.enable_mask        = 1ull<<1 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(1)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(1);
+    info.status_mask        = 1ull<<0 /* nxm_wr_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(1);
+    info.enable_mask        = 1ull<<0 /* intr_nxm_wr_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(1)[NXM_WR_ERR]: Write to non-existent memory\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(1);
+    info.status_mask        = 0xfull<<5 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(1);
+    info.enable_mask        = 1ull<<2 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(1)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_INT(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(2);
+    info.status_mask        = 0xfull<<1 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(2);
+    info.enable_mask        = 1ull<<1 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(2)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(2);
+    info.status_mask        = 1ull<<0 /* nxm_wr_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(2);
+    info.enable_mask        = 1ull<<0 /* intr_nxm_wr_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(2)[NXM_WR_ERR]: Write to non-existent memory\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(2);
+    info.status_mask        = 0xfull<<5 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(2);
+    info.enable_mask        = 1ull<<2 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(2)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_INT(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(3);
+    info.status_mask        = 0xfull<<1 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(3);
+    info.enable_mask        = 1ull<<1 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(3)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(3);
+    info.status_mask        = 1ull<<0 /* nxm_wr_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(3);
+    info.enable_mask        = 1ull<<0 /* intr_nxm_wr_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(3)[NXM_WR_ERR]: Write to non-existent memory\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(3);
+    info.status_mask        = 0xfull<<5 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(3);
+    info.enable_mask        = 1ull<<2 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<5 /* mem */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(3)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,2);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,2);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,2)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,2);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,2);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,2)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,2);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,2);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,2)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,2);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,2);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,2)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,3);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,3);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,3)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,3);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,3);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,3)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,3);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,3);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,3)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,3);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,3);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2864;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,3)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,4);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,4);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,4)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,4);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,4);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,4)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,4);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,4);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,4)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[UNDAT]: Unexpected Data\n"
+        "    (XAUI/RXAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,4);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,4);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,4)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<20 /* ptp_lost */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<20 /* ptp_lost */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n"
+        "    sent due to XSCOL\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 0xfull<<20 /* ptp_lost */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 0xfull<<20 /* ptp_lost */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[PTP_LOST]: A packet with a PTP request was not able to be\n"
+        "    sent due to XSCOL\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(2);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(2);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(2)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(2);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(2);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(2)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(2);
+    info.status_mask        = 0xfull<<20 /* ptp_lost */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(2);
+    info.enable_mask        = 0xfull<<20 /* ptp_lost */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(2)[PTP_LOST]: A packet with a PTP request was not able to be\n"
+        "    sent due to XSCOL\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(3);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(3);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(3)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(3);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(3);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(3)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(3);
+    info.status_mask        = 0xfull<<20 /* ptp_lost */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(3);
+    info.enable_mask        = 0xfull<<20 /* ptp_lost */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(3)[PTP_LOST]: A packet with a PTP request was not able to be\n"
+        "    sent due to XSCOL\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(4);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(4);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(4)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(4);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(4);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(4)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(4);
+    info.status_mask        = 0xfull<<20 /* ptp_lost */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(4);
+    info.enable_mask        = 0xfull<<20 /* ptp_lost */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(4)[PTP_LOST]: A packet with a PTP request was not able to be\n"
+        "    sent due to XSCOL\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2064;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2080;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2096;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,2);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,2);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,2)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,2);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,2);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,2);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,2);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,2);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,2);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,2);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,2);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,2)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,2);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,2);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,2);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,2);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,2);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,2);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,2);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,2);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,2)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,2);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,2);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,2)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,2);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,2);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,2);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,2);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,2);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,2);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,2);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,2);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,2)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,2);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,2);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,2);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,2);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,2);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,2);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,2);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,2);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2576;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,2)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,2);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,2);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,2)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,2);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,2);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,2);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,2);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,2);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,2);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,2);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,2);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,2)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,2);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,2);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,2);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,2);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,2);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,2);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,2);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,2);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2592;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,2)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,2);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,2);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,2)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,2);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,2);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,2);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,2);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,2);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,2);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,2);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,2);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,2)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,2);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,2);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,2);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,2);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,2);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,2);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,2);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,2);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2608;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,2)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,3);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,3);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,3)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,3);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,3);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,3);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,3);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,3);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,3);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,3);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,3);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,3)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,3);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,3);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,3);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,3);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,3);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,3);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,3);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,3);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,3)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,3);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,3);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,3)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,3);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,3);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,3);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,3);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,3);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,3);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,3);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,3);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,3)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,3);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,3);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,3);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,3);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,3);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,3);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,3);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,3);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2832;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,3)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,3);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,3);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,3)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,3);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,3);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,3);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,3);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,3);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,3);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,3);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,3);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,3)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,3);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,3);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,3);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,3);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,3);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,3);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,3);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,3);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2848;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,3)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,3);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,3);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2664;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,3)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,3);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,3);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2664;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,3);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,3);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2664;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,3);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,3);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2664;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,3);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,3);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2664;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,3)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,3);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,3);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2664;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,3);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,3);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2664;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,3);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,3);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2664;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,3);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,3);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2664;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,3)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,4);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,4);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,4)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,4);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,4);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,4);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,4);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,4);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,4);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,4);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,4);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,4)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,4);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,4);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,4);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,4);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,4);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,4);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,4);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,4);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,4)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,4);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,4);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,4)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,4);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,4);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,4);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,4);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,4);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,4);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,4);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,4);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,4)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,4);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,4);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,4);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,4);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,4);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,4);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,4);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,4);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3088;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,4)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,4);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,4);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,4)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,4);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,4);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,4);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,4);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,4);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,4);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,4);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,4);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,4)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,4);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,4);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,4);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,4);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,4);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,4);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,4);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,4);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3104;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,4)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,4);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,4);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,4)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,4);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,4);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,4);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,4);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,4);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,4);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,4);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,4);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,4)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,4);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,4);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,4);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,4);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,4);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,4);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,4);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,4);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3120;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,4)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<6 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2048;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<6 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<6 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2368;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(2);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(2);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(2)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(2);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(2);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(2)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(2);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(2);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(2)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(2);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(2);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(2)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(2);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(2);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(2)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(2);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(2);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(2)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(2);
+    info.status_mask        = 1ull<<6 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(2);
+    info.enable_mask        = 1ull<<6 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2560;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(2)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(3);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(3);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(3)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(3);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(3);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(3)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(3);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(3);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(3)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(3);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(3);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(3)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(3);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(3);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(3)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(3);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(3);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(3)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(3);
+    info.status_mask        = 1ull<<6 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(3);
+    info.enable_mask        = 1ull<<6 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2816;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(3)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(4) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(4);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(4);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(4)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(4);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(4);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(4)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(4);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(4);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(4)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(4);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(4);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(4)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(4);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(4);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(4)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(4);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(4);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(4)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(4);
+    info.status_mask        = 1ull<<6 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(4);
+    info.enable_mask        = 1ull<<6 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3072;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
+    info.parent.status_mask = 1ull<<6 /* pkt */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(4)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
+    fail |= cvmx_error_add(&info);
+
+    return fail;
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cnf71xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cnf71xx.c
new file mode 100644
index 0000000..6af2248
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cnf71xx.c
@@ -0,0 +1,5784 @@
+/***********************license start***************
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Automatically generated error messages for cnf71xx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision: 69515 $<hr>
+ *
+ * <hr><h2>Error tree for CNF71XX</h2>
+ * @dot
+ * digraph cnf71xx
+ * {
+ *     rankdir=LR;
+ *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
+ *     edge [fontsize=7, font=helvitica];
+ *     cvmx_root [label="ROOT|<root>root"];
+ *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<gpio>gpio|<pcm>pcm"];
+ *     cvmx_pcm0_int_sum [label="PCMX_INT_SUM(0)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm0_int_sum [label="pcm"];
+ *     cvmx_pcm1_int_sum [label="PCMX_INT_SUM(1)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm1_int_sum [label="pcm"];
+ *     cvmx_pcm2_int_sum [label="PCMX_INT_SUM(2)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm2_int_sum [label="pcm"];
+ *     cvmx_pcm3_int_sum [label="PCMX_INT_SUM(3)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm3_int_sum [label="pcm"];
+ *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
+ *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
+ *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
+ *     cvmx_ciu_block_int [label="CIU_BLOCK_INT|<l2c>l2c|<pem1>pem1|<gmx0>gmx0|<mio>mio|<ipd>ipd|<tim>tim|<pow>pow|<pem0>pem0|<pko>pko|<asxpcs0>asxpcs0|<sli>sli|<key>key|<usb>usb|<pip>pip|<fpa>fpa|<lmc0>lmc0|<iob>iob|<dpi>dpi|<rad>rad"];
+ *     cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<bigwr>bigwr|<bigrd>bigrd|<tad0>tad0"];
+ *     cvmx_l2c_tad0_int [label="L2C_TADX_INT(0)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_tad0_int [label="tad0"];
+ *     cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
+ *     cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
+ *     cvmx_ciu_block_int:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
+ *     cvmx_pem1_int_sum [label="PEMX_INT_SUM(1)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
+ *     cvmx_pem1_dbg_info [label="PEMX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
+ *     cvmx_pem1_int_sum:exc:e -> cvmx_pem1_dbg_info [label="exc"];
+ *     cvmx_ciu_block_int:pem1:e -> cvmx_pem1_int_sum [label="pem1"];
+ *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
+ *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
+ *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
+ *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
+ *     cvmx_ciu_block_int:mio:e -> cvmx_mio_boot_err [label="mio"];
+ *     cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<perst0>perst0|<perst1>perst1"];
+ *     cvmx_ciu_block_int:mio:e -> cvmx_mio_rst_int [label="mio"];
+ *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
+ *     cvmx_ciu_block_int:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
+ *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
+ *     cvmx_ciu_block_int:tim:e -> cvmx_tim_reg_error [label="tim"];
+ *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
+ *     cvmx_ciu_block_int:pow:e -> cvmx_pow_ecc_err [label="pow"];
+ *     cvmx_pem0_int_sum [label="PEMX_INT_SUM(0)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
+ *     cvmx_pem0_dbg_info [label="PEMX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
+ *     cvmx_pem0_int_sum:exc:e -> cvmx_pem0_dbg_info [label="exc"];
+ *     cvmx_ciu_block_int:pem0:e -> cvmx_pem0_int_sum [label="pem0"];
+ *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
+ *     cvmx_ciu_block_int:pko:e -> cvmx_pko_reg_error [label="pko"];
+ *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
+ *     cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<m2_up_b0>m2_up_b0|<m2_up_wi>m2_up_wi|<m2_un_b0>m2_un_b0|<m2_un_wi>m2_un_wi|<m3_up_b0>m3_up_b0|<m3_up_wi>m3_up_wi|<m3_un_b0>m3_un_b0|<m3_un_wi>m3_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pin_bp>pin_bp|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<sprt2_err>sprt2_err|<sprt3_err>sprt3_err|<ill_pad>ill_pad"];
+ *     cvmx_ciu_block_int:sli:e -> cvmx_sli_int_sum [label="sli"];
+ *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
+ *     cvmx_ciu_block_int:key:e -> cvmx_key_int_sum [label="key"];
+ *     cvmx_uctl0_int_reg [label="UCTLX_INT_REG(0)|<pp_psh_f>pp_psh_f|<er_psh_f>er_psh_f|<or_psh_f>or_psh_f|<cf_psh_f>cf_psh_f|<wb_psh_f>wb_psh_f|<wb_pop_e>wb_pop_e|<oc_ovf_e>oc_ovf_e|<ec_ovf_e>ec_ovf_e"];
+ *     cvmx_ciu_block_int:usb:e -> cvmx_uctl0_int_reg [label="usb"];
+ *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
+ *     cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
+ *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr|<pool0th>pool0th|<pool1th>pool1th|<pool2th>pool2th|<pool3th>pool3th|<pool4th>pool4th|<pool5th>pool5th|<pool6th>pool6th|<pool7th>pool7th|<free0>free0|<free1>free1|<free2>free2|<free3>free3|<free4>free4|<free5>free5|<free6>free6|<free7>free7|<paddr_e>paddr_e"];
+ *     cvmx_ciu_block_int:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
+ *     cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
+ *     cvmx_ciu_block_int:lmc0:e -> cvmx_lmc0_int [label="lmc0"];
+ *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
+ *     cvmx_ciu_block_int:iob:e -> cvmx_iob_int_sum [label="iob"];
+ *     cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst|<sprt2_rst>sprt2_rst|<sprt3_rst>sprt3_rst"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
+ *     cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
+ *     cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
+ *     cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
+ *     cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
+ *     cvmx_ciu_block_int:rad:e -> cvmx_rad_reg_error [label="rad"];
+ *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
+ *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
+ *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
+ *     cvmx_mio_boot_err -> cvmx_mio_rst_int [style=invis];
+ *     cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
+ *     cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
+ *     cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
+ *     cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
+ *     cvmx_root:root:e -> cvmx_ciu_block_int [label="root"];
+ * }
+ * @enddot
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-csr-typedefs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#endif
+
+int cvmx_error_initialize_cnf71xx(void);
+
+int cvmx_error_initialize_cnf71xx(void)
+{
+    cvmx_error_info_t info;
+    int fail = 0;
+
+    /* CVMX_CIU_INTX_SUM0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INTX_SUM0(0);
+    info.status_mask        = 0xffffull<<16 /* gpio */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR CIU_INTX_SUM0(0)[GPIO]: 16 GPIO interrupts\n"
+        "    When GPIO_MULTI_CAST[EN] == 1\n"
+        "    Write 1 to clear either the per PP or common GPIO\n"
+        "    edge-triggered interrupts,depending on mode.\n"
+        "    See GPIO_MULTI_CAST for all details.\n"
+        "    When GPIO_MULTI_CAST[EN] == 0\n"
+        "    Read Only, retain the same behavior as o63.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INTX_SUM0(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[FSYNCMISSED]: FSYNC missed interrupt occurred                 |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[FSYNCEXTRA]: FSYNC extra interrupt occurred                  |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[TXEMPTY]: TX byte was empty when sampled                  |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[RXOVF]: RX byte overflowed                              |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[FSYNCMISSED]: FSYNC missed interrupt occurred                 |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[FSYNCEXTRA]: FSYNC extra interrupt occurred                  |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[TXEMPTY]: TX byte was empty when sampled                  |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[RXOVF]: RX byte overflowed                              |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[FSYNCMISSED]: FSYNC missed interrupt occurred                 |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[FSYNCEXTRA]: FSYNC extra interrupt occurred                  |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[TXEMPTY]: TX byte was empty when sampled                  |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[RXOVF]: RX byte overflowed                              |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[FSYNCMISSED]: FSYNC missed interrupt occurred                 |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[FSYNCEXTRA]: FSYNC extra interrupt occurred                  |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[TXEMPTY]: TX byte was empty when sampled                  |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[RXOVF]: RX byte overflowed                              |           NS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU_INT_SUM1 */
+    /* CVMX_CIU_BLOCK_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_BLOCK_INT;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<0 /* holerd */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<0 /* holerd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<1 /* holewr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<1 /* holewr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<2 /* vrtwr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<2 /* vrtwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
+        "    Set when L2C_VRT_MEM blocked a store.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<3 /* vrtidrng */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<3 /* vrtidrng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
+        "    Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
+        "    store.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<4 /* vrtadrng */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<4 /* vrtadrng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
+        "    Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
+        "    store.\n"
+        "    L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<5 /* vrtpe */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<5 /* vrtpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
+        "    Whenever an L2C_VRT_MEM read finds a parity error,\n"
+        "    that L2C_VRT_MEM cannot cause stores to be blocked.\n"
+        "    Software should correct the error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<6 /* bigwr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<6 /* bigwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[BIGWR]: Write reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<7 /* bigrd */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<7 /* bigrd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[BIGRD]: Read reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_TADX_INT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<0 /* l2dsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<0 /* l2dsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[L2DSBE]: L2D Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<1 /* l2ddbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<1 /* l2ddbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[L2DDBE]: L2D Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<2 /* tagsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<2 /* tagsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[TAGSBE]: TAG Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<3 /* tagdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<3 /* tagdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[TAGDBE]: TAG Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<4 /* vbfsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<4 /* vbfsbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VSBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<5 /* vbfdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<5 /* vbfdbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VDBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<6 /* noway */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<6 /* noway */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[NOWAY]: No way available interrupt\n"
+        "    Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<7 /* rddislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<7 /* rddislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[RDDISLMC]: Illegal Read  to Disabled LMC Error\n"
+        "    A DRAM read  arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<8 /* wrdislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<8 /* wrdislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
+        "    A DRAM write arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TDTX(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<60 /* vsbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<61 /* vdbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TTGX(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<61 /* noway */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
+        "    L2C sets NOWAY during its processing of a\n"
+        "    transaction whenever it needed/wanted to allocate\n"
+        "    a WAY in the L2 cache, but was unable to. NOWAY==1\n"
+        "    is (generally) not an indication that L2C failed to\n"
+        "    complete transactions. Rather, it is a hint of\n"
+        "    possible performance degradation. (For example, L2C\n"
+        "    must read-modify-write DRAM for every transaction\n"
+        "    that updates some, but not all, of the bytes in a\n"
+        "    cache block, misses in the L2 cache, and cannot\n"
+        "    allocate a WAY.) There is one \"failure\" case where\n"
+        "    L2C will set NOWAY: when it cannot leave a block\n"
+        "    locked in the L2 cache as part of a LCKL2\n"
+        "    transaction.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_INT_SUM(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<1 /* se */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<1 /* se */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[SE]: System Error, RC Mode Only.\n"
+        "    (cfg_sys_err_rc)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<4 /* up_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<4 /* up_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<5 /* up_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<5 /* up_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<6 /* up_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<6 /* up_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UP_BX]: Received P-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<7 /* un_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<7 /* un_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<8 /* un_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<8 /* un_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<9 /* un_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<9 /* un_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UN_BX]: Received N-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<11 /* rdlk */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<11 /* rdlk */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[RDLK]: Received Read Lock TLP.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<12 /* crs_er */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<12 /* crs_er */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<13 /* crs_dr */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<13 /* crs_dr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_DBG_INFO(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<0 /* spoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<0 /* spoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
+        "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<2 /* rtlplle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<2 /* rtlplle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
+        "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<3 /* recrce */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<3 /* recrce */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
+        "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<4 /* rpoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<4 /* rpoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
+        "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<5 /* rcemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<5 /* rcemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+        "    pedc_radm_correctable_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<6 /* rnfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<6 /* rnfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_nonfatal_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<7 /* rfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<7 /* rfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_fatal_err\n"
+        "    Bit set when a message with ERR_FATAL is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<8 /* rpmerc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<8 /* rpmerc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
+        "    pedc_radm_pm_pme\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<9 /* rptamrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<9 /* rptamrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+        "    (RC Mode only)\n"
+        "    pedc_radm_pm_to_ack\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<10 /* rumep */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<10 /* rumep */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+        "    pedc_radm_msg_unlock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<11 /* rvdm */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<11 /* rvdm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
+        "    pedc_radm_vendor_msg\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<12 /* acto */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<12 /* acto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
+        "    pedc_radm_cpl_timeout\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<13 /* rte */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<13 /* rte */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
+        "    xdlh_replay_timeout_err\n"
+        "    This bit is set when the REPLAY_TIMER expires in\n"
+        "    the PCIE core. The probability of this bit being\n"
+        "    set will increase with the traffic load.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<14 /* mre */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<14 /* mre */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
+        "    xdlh_replay_num_rlover_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<15 /* rdwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<15 /* rdwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+        "    rdlh_bad_dllp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<16 /* rtwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<16 /* rtwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
+        "    rdlh_bad_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<17 /* dpeoosd */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<17 /* dpeoosd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+        "    rdlh_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<18 /* fcpvwt */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<18 /* fcpvwt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+        "    rtlh_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<19 /* rpe */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<19 /* rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
+        "    (RxStatus = 3b100) or disparity error\n"
+        "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+        "    be asserted.\n"
+        "    rmlh_rcvd_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<20 /* fcuv */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<20 /* fcuv */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
+        "    int_xadm_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<21 /* rqo */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<21 /* rqo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
+        "    flow control advertisements are ignored\n"
+        "    radm_qoverflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<22 /* rauc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<22 /* rauc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
+        "    radm_unexp_cpl_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<23 /* racur */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<23 /* racur */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
+        "    radm_rcvd_cpl_ur\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<24 /* racca */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<24 /* racca */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
+        "    radm_rcvd_cpl_ca\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<25 /* caar */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<25 /* caar */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
+        "    radm_rcvd_ca_req\n"
+        "    This bit will never be set because Octeon does\n"
+        "    not generate Completer Aborts.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<26 /* rarwdns */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<26 /* rarwdns */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
+        "    radm_rcvd_ur_req\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<27 /* ramtlp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<27 /* ramtlp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
+        "    radm_mlf_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<28 /* racpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<28 /* racpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
+        "    radm_rcvd_cpl_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<29 /* rawwpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<29 /* rawwpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
+        "    radm_rcvd_wreq_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<30 /* ecrc_e */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<30 /* ecrc_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
+        "    radm_ecrc_err\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In SGMII, one bit per port\n"
+        "    In XAUI, only port0 is used\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
+        "    The common FIFO to SGMII and XAUI had an overflow\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0x3ull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0x3ull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0x3ull<<20 /* ptp_lost */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0x3ull<<20 /* ptp_lost */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n"
+        "    sent due to XSCOL\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_BOOT_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<0 /* adr_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<0 /* adr_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<1 /* wait_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<1 /* wait_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_RST_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<0 /* rst_link0 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<0 /* rst_link0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n"
+        "    MIO_RST_CTL0[RST_LINK]=0.  Software must assert\n"
+        "    then de-assert CIU_SOFT_PRST[SOFT_PRST]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<1 /* rst_link1 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<1 /* rst_link1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n"
+        "    MIO_RST_CTL1[RST_LINK]=0.  Software must assert\n"
+        "    then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<8 /* perst0 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<8 /* perst0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1\n"
+        "    and MIO_RST_CTL0[RST_CHIP]=0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<9 /* perst1 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<9 /* perst1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1\n"
+        "    and MIO_RST_CTL1[RST_CHIP]=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IPD_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<0 /* prc_par0 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* prc_par0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+        "    [31:0] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<1 /* prc_par1 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* prc_par1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+        "    [63:32] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<2 /* prc_par2 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* prc_par2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+        "    [95:64] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<3 /* prc_par3 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* prc_par3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+        "    [127:96] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<4 /* bp_sub */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* bp_sub */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+        "    supplied illegal value.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* dc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<6 /* cc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* cc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<7 /* c_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* c_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<8 /* d_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* d_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<9 /* bc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* bc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_TIM_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_TIM_REG_ERROR;
+    info.status_mask        = 0xffffull<<0 /* mask */;
+    info.enable_addr        = CVMX_TIM_REG_INT_MASK;
+    info.enable_mask        = 0xffffull<<0 /* mask */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<11 /* tim */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_POW_ECC_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<0 /* sbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<2 /* sbe_ie */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<1 /* dbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<3 /* dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<12 /* rpe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<13 /* rpe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 0x1fffull<<16 /* iop */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_iop;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_INT_SUM(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<1 /* se */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<1 /* se */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[SE]: System Error, RC Mode Only.\n"
+        "    (cfg_sys_err_rc)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<4 /* up_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<4 /* up_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<5 /* up_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<5 /* up_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<6 /* up_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<6 /* up_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UP_BX]: Received P-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<7 /* un_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<7 /* un_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<8 /* un_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<8 /* un_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<9 /* un_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<9 /* un_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UN_BX]: Received N-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<11 /* rdlk */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<11 /* rdlk */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[RDLK]: Received Read Lock TLP.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<12 /* crs_er */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<12 /* crs_er */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<13 /* crs_dr */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<13 /* crs_dr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_DBG_INFO(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<0 /* spoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<0 /* spoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
+        "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<2 /* rtlplle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<2 /* rtlplle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
+        "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<3 /* recrce */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<3 /* recrce */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
+        "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<4 /* rpoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<4 /* rpoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
+        "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<5 /* rcemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<5 /* rcemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+        "    pedc_radm_correctable_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<6 /* rnfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<6 /* rnfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_nonfatal_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<7 /* rfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<7 /* rfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_fatal_err\n"
+        "    Bit set when a message with ERR_FATAL is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<8 /* rpmerc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<8 /* rpmerc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
+        "    pedc_radm_pm_pme\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<9 /* rptamrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<9 /* rptamrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+        "    (RC Mode only)\n"
+        "    pedc_radm_pm_to_ack\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<10 /* rumep */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<10 /* rumep */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+        "    pedc_radm_msg_unlock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<11 /* rvdm */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<11 /* rvdm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
+        "    pedc_radm_vendor_msg\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<12 /* acto */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<12 /* acto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
+        "    pedc_radm_cpl_timeout\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<13 /* rte */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<13 /* rte */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
+        "    xdlh_replay_timeout_err\n"
+        "    This bit is set when the REPLAY_TIMER expires in\n"
+        "    the PCIE core. The probability of this bit being\n"
+        "    set will increase with the traffic load.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<14 /* mre */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<14 /* mre */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
+        "    xdlh_replay_num_rlover_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<15 /* rdwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<15 /* rdwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+        "    rdlh_bad_dllp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<16 /* rtwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<16 /* rtwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
+        "    rdlh_bad_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<17 /* dpeoosd */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<17 /* dpeoosd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+        "    rdlh_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<18 /* fcpvwt */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<18 /* fcpvwt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+        "    rtlh_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<19 /* rpe */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<19 /* rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
+        "    (RxStatus = 3b100) or disparity error\n"
+        "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+        "    be asserted.\n"
+        "    rmlh_rcvd_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<20 /* fcuv */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<20 /* fcuv */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
+        "    int_xadm_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<21 /* rqo */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<21 /* rqo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
+        "    flow control advertisements are ignored\n"
+        "    radm_qoverflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<22 /* rauc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<22 /* rauc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
+        "    radm_unexp_cpl_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<23 /* racur */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<23 /* racur */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
+        "    radm_rcvd_cpl_ur\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<24 /* racca */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<24 /* racca */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
+        "    radm_rcvd_cpl_ca\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<25 /* caar */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<25 /* caar */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
+        "    radm_rcvd_ca_req\n"
+        "    This bit will never be set because Octeon does\n"
+        "    not generate Completer Aborts.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<26 /* rarwdns */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<26 /* rarwdns */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
+        "    radm_rcvd_ur_req\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<27 /* ramtlp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<27 /* ramtlp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
+        "    radm_mlf_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<28 /* racpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<28 /* racpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
+        "    radm_rcvd_cpl_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<29 /* rawwpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<29 /* rawwpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
+        "    radm_rcvd_wreq_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<30 /* ecrc_e */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<30 /* ecrc_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
+        "    radm_ecrc_err\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PKO_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* parity */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* parity */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<1 /* doorbell */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<1 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<2 /* currzero */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<2 /* currzero */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEXP_SLI_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<0 /* rml_to */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<0 /* rml_to */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n"
+        "    within 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<1 /* reserved_1_1 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<1 /* reserved_1_1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<2 /* bar0_to */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<2 /* bar0_to */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
+        "    read-data/commit in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<3 /* iob2big */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<3 /* iob2big */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 0x3ull<<6 /* reserved_6_7 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 0x3ull<<6 /* reserved_6_7 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<8 /* m0_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<8 /* m0_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<9 /* m0_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<9 /* m0_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n"
+        "    from MAC 0. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<10 /* m0_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<10 /* m0_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<11 /* m0_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<11 /* m0_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n"
+        "    from MAC 0. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<12 /* m1_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<12 /* m1_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<13 /* m1_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<13 /* m1_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n"
+        "    from MAC 1. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<14 /* m1_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<14 /* m1_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<15 /* m1_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<15 /* m1_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n"
+        "    from MAC 1. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<20 /* m2_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<20 /* m2_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M2_UP_B0]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<21 /* m2_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<21 /* m2_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M2_UP_WI]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<22 /* m2_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<22 /* m2_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M2_UN_B0]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<23 /* m2_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<23 /* m2_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M2_UN_WI]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<24 /* m3_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<24 /* m3_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M3_UP_B0]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<25 /* m3_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<25 /* m3_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M3_UP_WI]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<26 /* m3_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<26 /* m3_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M3_UN_B0]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<27 /* m3_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<27 /* m3_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M3_UN_WI]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<48 /* pidbof */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<48 /* pidbof */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
+        "    doorbell can be found in DPI_PINT_INFO[PIDBOF]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<49 /* psldbof */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<49 /* psldbof */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
+        "    doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<50 /* pout_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<50 /* pout_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n"
+        "    set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<51 /* pin_bp */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<51 /* pin_bp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PIN_BP]: Packet input count has exceeded the WMARK.\n"
+        "    See SLI_PKT_IN_BP\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<52 /* pgl_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<52 /* pgl_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n"
+        "    read this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<53 /* pdi_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<53 /* pdi_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<54 /* pop_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<54 /* pop_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n"
+        "    pointer pair this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<55 /* pins_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<55 /* pins_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<56 /* sprt0_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<56 /* sprt0_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<57 /* sprt1_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<57 /* sprt1_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<58 /* sprt2_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<58 /* sprt2_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT2_ERR]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<59 /* sprt3_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<59 /* sprt3_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT3_ERR]: Reserved.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<60 /* ill_pad */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<60 /* ill_pad */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n"
+        "    range of the Packet-CSR, but for an unused\n"
+        "    address.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_KEY_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<0 /* ked0_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* ked0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<1 /* ked0_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* ked0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<2 /* ked1_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* ked1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<3 /* ked1_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* ked1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_UCTLX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pp_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<0 /* pp_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[PP_PSH_F]: PP Access FIFO  Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* er_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<1 /* er_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[ER_PSH_F]: EHCI Read Buffer FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* or_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<2 /* or_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[OR_PSH_F]: OHCI Read Buffer FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* cf_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<3 /* cf_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[CF_PSH_F]: Command FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* wb_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<4 /* wb_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[WB_PSH_F]: Write Buffer FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* wb_pop_e */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<5 /* wb_pop_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[WB_POP_E]: Write Buffer FIFO Poped When Empty\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* oc_ovf_e */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<6 /* oc_ovf_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[OC_OVF_E]: Ohci Commit OVerFlow Error\n"
+        "    When the error happenes, the whole NCB system needs\n"
+        "    to be reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<7 /* ec_ovf_e */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<7 /* ec_ovf_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[EC_OVF_E]: Ehci Commit OVerFlow Error\n"
+        "    When the error happenes, the whole NCB system needs\n"
+        "    to be reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PIP_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<3 /* prtnxa */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<3 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<4 /* badtag */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<4 /* badtag */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<5 /* skprunt */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<5 /* skprunt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+        "    This interrupt can occur with received PARTIAL\n"
+        "    packets that are truncated to SKIP bytes or\n"
+        "    smaller.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<6 /* todoovr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<6 /* todoovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<7 /* feperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<7 /* feperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<8 /* beperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<8 /* beperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<12 /* punyerr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<12 /* punyerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
+        "    stripping in IPD is enable\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_FPA_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<0 /* fed0_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* fed0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<1 /* fed0_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* fed0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<2 /* fed1_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* fed1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<3 /* fed1_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* fed1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<4 /* q0_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* q0_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<5 /* q0_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* q0_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<6 /* q0_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* q0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<7 /* q1_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* q1_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<8 /* q1_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* q1_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<9 /* q1_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* q1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<10 /* q2_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* q2_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<11 /* q2_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* q2_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<12 /* q2_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* q2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<13 /* q3_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* q3_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<14 /* q3_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* q3_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<15 /* q3_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* q3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<16 /* q4_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* q4_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<17 /* q4_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* q4_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<18 /* q4_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* q4_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<19 /* q5_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* q5_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<20 /* q5_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* q5_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<21 /* q5_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* q5_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<22 /* q6_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* q6_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<23 /* q6_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* q6_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<24 /* q6_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* q6_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<25 /* q7_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* q7_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<26 /* q7_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* q7_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<27 /* q7_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* q7_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<28 /* pool0th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<28 /* pool0th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL0TH]: Set when FPA_QUE0_AVAILABLE is equal to\n"
+        "    FPA_POOL`_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<29 /* pool1th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<29 /* pool1th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL1TH]: Set when FPA_QUE1_AVAILABLE is equal to\n"
+        "    FPA_POOL1_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<30 /* pool2th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<30 /* pool2th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL2TH]: Set when FPA_QUE2_AVAILABLE is equal to\n"
+        "    FPA_POOL2_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<31 /* pool3th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<31 /* pool3th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL3TH]: Set when FPA_QUE3_AVAILABLE is equal to\n"
+        "    FPA_POOL3_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<32 /* pool4th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<32 /* pool4th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL4TH]: Set when FPA_QUE4_AVAILABLE is equal to\n"
+        "    FPA_POOL4_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<33 /* pool5th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<33 /* pool5th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL5TH]: Set when FPA_QUE5_AVAILABLE is equal to\n"
+        "    FPA_POOL5_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<34 /* pool6th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<34 /* pool6th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL6TH]: Set when FPA_QUE6_AVAILABLE is equal to\n"
+        "    FPA_POOL6_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<35 /* pool7th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<35 /* pool7th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL7TH]: Set when FPA_QUE7_AVAILABLE is equal to\n"
+        "    FPA_POOL7_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<36 /* free0 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<36 /* free0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE0]: When a pointer for POOL0 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<37 /* free1 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<37 /* free1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE1]: When a pointer for POOL1 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<38 /* free2 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<38 /* free2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE2]: When a pointer for POOL2 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<39 /* free3 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<39 /* free3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE3]: When a pointer for POOL3 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<40 /* free4 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<40 /* free4 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE4]: When a pointer for POOL4 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<41 /* free5 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<41 /* free5 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE5]: When a pointer for POOL5 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<42 /* free6 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<42 /* free6 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE6]: When a pointer for POOL6 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<43 /* free7 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<43 /* free7 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE7]: When a pointer for POOL7 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<49 /* paddr_e */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<49 /* paddr_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[PADDR_E]: Set when a pointer address does not fall in the\n"
+        "    address range for a pool specified by\n"
+        "    FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_INT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 0xfull<<1 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<1 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "     where _cC_pP denotes cycle C and phase P\n"
+        "     Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 1ull<<0 /* nxm_wr_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* intr_nxm_wr_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 0xfull<<5 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<2 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "     where _cC_pP denotes cycle C and phase P\n"
+        "     Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IOB_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<0 /* np_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* np_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<1 /* np_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* np_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<2 /* p_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* p_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<3 /* p_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* p_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<4 /* np_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* np_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<5 /* p_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* p_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<0 /* nderr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<0 /* nderr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n"
+        "    DPI received a NCB transaction on the outbound\n"
+        "    bus to the DPI deviceID, but the command was not\n"
+        "    recognized.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<1 /* nfovr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<1 /* nfovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n"
+        "    DPI can store upto 16 CSR request.  The FIFO will\n"
+        "    overflow if that number is exceeded.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 0xffull<<8 /* dmadbo */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 0xffull<<8 /* dmadbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n"
+        "    DPI has a 32-bit counter for each request's queue\n"
+        "    outstanding doorbell counts. Interrupt will fire\n"
+        "    if the count overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<16 /* req_badadr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<16 /* req_badadr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n"
+        "    Interrupt will fire if DPI forms an instruction\n"
+        "    fetch to the NULL pointer.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<17 /* req_badlen */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<17 /* req_badlen */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n"
+        "    Interrupt will fire if DPI forms an instruction\n"
+        "    fetch with length of zero.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<18 /* req_ovrflw */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<18 /* req_ovrflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n"
+        "    DPI tracks outstanding instructions fetches.\n"
+        "    Interrupt will fire when FIFO overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<19 /* req_undflw */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<19 /* req_undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n"
+        "    DPI tracks outstanding instructions fetches.\n"
+        "    Interrupt will fire when FIFO underflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<20 /* req_anull */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<20 /* req_anull */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n"
+        "    Fetched instruction word was 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<21 /* req_inull */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<21 /* req_inull */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n"
+        "    Next pointer was NULL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<22 /* req_badfil */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<22 /* req_badfil */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n"
+        "    Instruction fill when none outstanding.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<24 /* sprt0_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<24 /* sprt0_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<25 /* sprt1_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<25 /* sprt1_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<26 /* sprt2_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<26 /* sprt2_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT2_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<27 /* sprt3_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<27 /* sprt3_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT3_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_PKT_ERR_RSP */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_PKT_ERR_RSP;
+    info.status_mask        = 1ull<<0 /* pkterr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n"
+        "    the I/O subsystem.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_REQ_ERR_RSP */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_REQ_ERR_RSP;
+    info.status_mask        = 0xffull<<0 /* qerr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n"
+        "    ErrorResponse from the I/O subsystem.\n"
+        "    SW must clear the bit before the the cooresponding\n"
+        "    instruction queue will continue processing\n"
+        "    instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_REQ_ERR_RST */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_REQ_ERR_RST;
+    info.status_mask        = 0xffull<<0 /* qerr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n"
+        "    instruction because the source or destination\n"
+        "    was in reset.\n"
+        "    SW must clear the bit before the the cooresponding\n"
+        "    instruction queue will continue processing\n"
+        "    instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_RAD_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_RAD_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_RAD_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<14 /* rad */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    return fail;
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error.c b/sys/contrib/octeon-sdk/cvmx-error.c
index 7b33b37..5f13632 100644
--- a/sys/contrib/octeon-sdk/cvmx-error.c
+++ b/sys/contrib/octeon-sdk/cvmx-error.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -51,6 +51,9 @@
 #include <asm/octeon/cvmx-error-custom.h>
 #include <asm/octeon/cvmx-pcie.h>
 #include <asm/octeon/cvmx-srio.h>
+#include <asm/octeon/cvmx-ciu2-defs.h>
+#include <asm/octeon/cvmx-dfm-defs.h>
+#include <asm/octeon/cvmx-lmcx-defs.h>
 #include <asm/octeon/cvmx-pexp-defs.h>
 #else
 #include "cvmx.h"
@@ -63,8 +66,13 @@
 
 #define MAX_TABLE_SIZE 1024   /* Max number of error status bits we can support */
 
+extern int cvmx_error_initialize_cnf71xx(void);
+extern int cvmx_error_initialize_cn68xx(void);
+extern int cvmx_error_initialize_cn68xxp1(void);
+extern int cvmx_error_initialize_cn66xx(void);
 extern int cvmx_error_initialize_cn63xx(void);
 extern int cvmx_error_initialize_cn63xxp1(void);
+extern int cvmx_error_initialize_cn61xx(void);
 extern int cvmx_error_initialize_cn58xxp1(void);
 extern int cvmx_error_initialize_cn58xx(void);
 extern int cvmx_error_initialize_cn56xxp1(void);
@@ -221,6 +229,17 @@ int __cvmx_error_display(const cvmx_error_info_t *info)
     /* This assumes that all bits in the status register are RO or R/W1C */
     __cvmx_error_write_hw(info->reg_type, info->status_addr, info->status_mask);
     cvmx_safe_printf("%s", message);
+
+    /* Clear the source to reduce the chance for spurious interrupts.  */
+                                                                                
+    /* CN68XX has an CIU-15786 errata that accessing the ACK registers
+     * can stop interrupts from propagating
+     */
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+        cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY);
+    else if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+        cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP4(cvmx_get_core_num()));
+
     return 1;
 }
 
@@ -237,7 +256,27 @@ int __cvmx_error_display(const cvmx_error_info_t *info)
 int cvmx_error_initialize(cvmx_error_flags_t flags)
 {
     __cvmx_error_flags = flags;
-    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_X))
+    if (OCTEON_IS_MODEL(OCTEON_CNF71XX))
+    {
+        if (cvmx_error_initialize_cnf71xx())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+    {
+        if (cvmx_error_initialize_cn68xx())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X))
+    {
+        if (cvmx_error_initialize_cn68xxp1())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN66XX))
+    {
+        if (cvmx_error_initialize_cn66xx())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
     {
         if (cvmx_error_initialize_cn63xx())
             return -1;
@@ -247,6 +286,11 @@ int cvmx_error_initialize(cvmx_error_flags_t flags)
         if (cvmx_error_initialize_cn63xxp1())
             return -1;
     }
+    else if (OCTEON_IS_MODEL(OCTEON_CN61XX))
+    {
+        if (cvmx_error_initialize_cn61xx())
+            return -1;
+    }
     else if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS1_X))
     {
         if (cvmx_error_initialize_cn58xxp1())
@@ -314,6 +358,11 @@ int cvmx_error_initialize(cvmx_error_flags_t flags)
     /* Enable all of the purely internal error sources by default */
     cvmx_error_enable_group(CVMX_ERROR_GROUP_INTERNAL, 0);
 
+    /* According to workaround for errata KEY-14814 in cn63xx, clearing 
+       SLI_INT_SUM[RML_TO] after enabling KEY interrupts */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+        cvmx_write_csr(CVMX_PEXP_SLI_INT_SUM, 1);
+
     /* Enable DDR error reporting based on the memory controllers */
     if (OCTEON_IS_MODEL(OCTEON_CN56XX))
     {
@@ -327,6 +376,32 @@ int cvmx_error_initialize(cvmx_error_flags_t flags)
     else
         cvmx_error_enable_group(CVMX_ERROR_GROUP_LMC, 0);
 
+    /* Enable error interrupts for other LMC only if it is
+       available. */
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+    {
+        int i;
+        for (i = 1; i < 4; i++)
+        {
+            cvmx_lmcx_dll_ctl2_t ctl2;
+            ctl2.u64 = cvmx_read_csr(CVMX_LMCX_DLL_CTL2(i));
+            if (ctl2.s.intf_en)
+                cvmx_error_enable_group(CVMX_ERROR_GROUP_LMC, i);
+        } 
+    }
+
+    /* Enable DFM error reporting based on feature availablility */
+    if (octeon_has_feature(OCTEON_FEATURE_DFM))
+    {
+        /* Only configure interrupts if DFM clock is enabled. */
+        cvmx_dfm_fnt_sclk_t dfm_fnt_sclk;
+        dfm_fnt_sclk.u64 = cvmx_read_csr(CVMX_DFM_FNT_SCLK);
+        if (!dfm_fnt_sclk.s.sclkdis)
+        {
+            cvmx_error_enable_group(CVMX_ERROR_GROUP_DFM, 0);
+        }
+    }
+
     /* Old PCI parts don't have a common PCI init, so enable error
         reporting if the bootloader told us we are a PCI host. PCIe
         is handled when cvmx_pcie_rc_initialize is called */
@@ -334,9 +409,8 @@ int cvmx_error_initialize(cvmx_error_flags_t flags)
         (cvmx_sysinfo_get()->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST))
         cvmx_error_enable_group(CVMX_ERROR_GROUP_PCI, 0);
 
-    /* FIXME: Why is this needed for CN63XX? */
-    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
-        cvmx_write_csr(CVMX_PEXP_SLI_INT_SUM, 1);
+    /* Call poll once to clear out any pending interrupts */
+    cvmx_error_poll();
 
     return 0;
 }
@@ -501,6 +575,24 @@ int cvmx_error_enable_group(cvmx_error_group_t group, int group_index)
     for (i = 0; i < __cvmx_error_table_size; i++)
     {
         const cvmx_error_info_t *h = &__cvmx_error_table[i];
+        /* SGMII and XAUI has different ipd_port, use the same group_index
+           for both the interfaces */
+        switch(group_index)
+        {
+            case 0x840:
+                group_index = 0x800;
+                break;
+            case 0xa40:
+                group_index = 0xa00;
+                break;
+            case 0xb40:
+                group_index = 0xb00;
+                break;
+            case 0xc40:
+                group_index = 0xc00;
+                break;
+        }
+            
         /* Skip entries that have a different group or group index. We
             also skip entries that don't have an enable */
         if ((h->group != group) || (h->group_index != group_index) || (!h->enable_addr))
@@ -544,6 +636,24 @@ int cvmx_error_disable_group(cvmx_error_group_t group, int group_index)
     for (i = 0; i < __cvmx_error_table_size; i++)
     {
         const cvmx_error_info_t *h = &__cvmx_error_table[i];
+
+        /* SGMII and XAUI has different ipd_port, use the same group_index
+           for both the interfaces */
+        switch(group_index)
+        {
+            case 0x840:
+                group_index = 0x800;
+                break;
+            case 0xa40:
+                group_index = 0xa00;
+                break;
+            case 0xb40:
+                group_index = 0xb00;
+                break;
+            case 0xc40:
+                group_index = 0xc00;
+                break;
+        }
         /* Skip entries that have a different group or group index. We
             also skip entries that don't have an enable */
         if ((h->group != group) || (h->group_index != group_index) || (!h->enable_addr))
@@ -641,3 +751,23 @@ int cvmx_error_disable(cvmx_error_register_t reg_type,
     }
 }
 
+
+/**
+ * Find the handler for a specific status register and mask
+ *
+ * @param status_addr
+ *                Status register address
+ *
+ * @return  Return the handler on success or null on failure.
+ */
+cvmx_error_info_t *cvmx_error_get_index(uint64_t status_addr)
+{
+    int i;
+    for (i = 0; i < __cvmx_error_table_size; i++)
+    {
+        if (__cvmx_error_table[i].status_addr == status_addr)
+            return &__cvmx_error_table[i];
+    }
+
+    return NULL;
+}
diff --git a/sys/contrib/octeon-sdk/cvmx-error.h b/sys/contrib/octeon-sdk/cvmx-error.h
index 2c1415d..f1ce492 100644
--- a/sys/contrib/octeon-sdk/cvmx-error.h
+++ b/sys/contrib/octeon-sdk/cvmx-error.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -67,6 +67,8 @@ typedef enum
     CVMX_ERROR_GROUP_SRIO,      /* All errors related to SRIO when the bus is up. Index by port number (0-1) */
     CVMX_ERROR_GROUP_USB,       /* All errors related to USB when the port is enabled. Index by port number (0-1) */
     CVMX_ERROR_GROUP_LMC,       /* All errors related to LMC when the controller is enabled. Index by controller number (0-1) */
+    CVMX_ERROR_GROUP_ILK,       /* All errors related to ILK when the controller is enabled. Index by controller number (0-1) */
+    CVMX_ERROR_GROUP_DFM,       /* All errors related to DFM when the controller is enabled. */
 } cvmx_error_group_t;
 
 /**
@@ -311,6 +313,16 @@ int __cvmx_error_decode(const cvmx_error_info_t *info);
  */
 int __cvmx_error_display(const cvmx_error_info_t *info);
 
+/**
+ * Find the handler for a specific status register and mask
+ *
+ * @param status_addr
+ *                Status register address
+ *
+ * @return  Return the handler on success or null on failure.
+ */
+cvmx_error_info_t *cvmx_error_get_index(uint64_t status_addr);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-fau.h b/sys/contrib/octeon-sdk/cvmx-fau.h
index a8d0234..81c2e04 100644
--- a/sys/contrib/octeon-sdk/cvmx-fau.h
+++ b/sys/contrib/octeon-sdk/cvmx-fau.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -43,7 +43,7 @@
  *
  * Interface to the hardware Fetch and Add Unit.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_FAU_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-flash.c b/sys/contrib/octeon-sdk/cvmx-flash.c
index bba7948..cb53027 100644
--- a/sys/contrib/octeon-sdk/cvmx-flash.c
+++ b/sys/contrib/octeon-sdk/cvmx-flash.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * This file provides bootbus flash operations
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  *
  */
diff --git a/sys/contrib/octeon-sdk/cvmx-flash.h b/sys/contrib/octeon-sdk/cvmx-flash.h
index e187fff..e67c2d7 100644
--- a/sys/contrib/octeon-sdk/cvmx-flash.h
+++ b/sys/contrib/octeon-sdk/cvmx-flash.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * This file provides bootbus flash operations
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  *
  */
diff --git a/sys/contrib/octeon-sdk/cvmx-fpa-defs.h b/sys/contrib/octeon-sdk/cvmx-fpa-defs.h
index e9d2764..62992bd 100644
--- a/sys/contrib/octeon-sdk/cvmx-fpa-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-fpa-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,16 +49,27 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_FPA_TYPEDEFS_H__
-#define __CVMX_FPA_TYPEDEFS_H__
+#ifndef __CVMX_FPA_DEFS_H__
+#define __CVMX_FPA_DEFS_H__
 
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_FPA_ADDR_RANGE_ERROR CVMX_FPA_ADDR_RANGE_ERROR_FUNC()
+static inline uint64_t CVMX_FPA_ADDR_RANGE_ERROR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_FPA_ADDR_RANGE_ERROR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180028000458ull);
+}
+#else
+#define CVMX_FPA_ADDR_RANGE_ERROR (CVMX_ADD_IO_SEG(0x0001180028000458ull))
+#endif
 #define CVMX_FPA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E8ull))
 #define CVMX_FPA_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180028000050ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_FPA_FPF0_MARKS CVMX_FPA_FPF0_MARKS_FUNC()
 static inline uint64_t CVMX_FPA_FPF0_MARKS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_FPA_FPF0_MARKS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180028000000ull);
 }
@@ -69,7 +80,7 @@ static inline uint64_t CVMX_FPA_FPF0_MARKS_FUNC(void)
 #define CVMX_FPA_FPF0_SIZE CVMX_FPA_FPF0_SIZE_FUNC()
 static inline uint64_t CVMX_FPA_FPF0_SIZE_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_FPA_FPF0_SIZE not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180028000058ull);
 }
@@ -84,13 +95,39 @@ static inline uint64_t CVMX_FPA_FPF0_SIZE_FUNC(void)
 #define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6)
 #define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7)
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_FPA_FPF8_MARKS CVMX_FPA_FPF8_MARKS_FUNC()
+static inline uint64_t CVMX_FPA_FPF8_MARKS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_FPA_FPF8_MARKS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180028000240ull);
+}
+#else
+#define CVMX_FPA_FPF8_MARKS (CVMX_ADD_IO_SEG(0x0001180028000240ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_FPA_FPF8_SIZE CVMX_FPA_FPF8_SIZE_FUNC()
+static inline uint64_t CVMX_FPA_FPF8_SIZE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_FPA_FPF8_SIZE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180028000248ull);
+}
+#else
+#define CVMX_FPA_FPF8_SIZE (CVMX_ADD_IO_SEG(0x0001180028000248ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_FPA_FPFX_MARKS(unsigned long offset)
 {
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 1) && (offset <= 7))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 1) && (offset <= 7)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 1) && (offset <= 7)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 1) && (offset <= 7)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 1) && (offset <= 7)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 1) && (offset <= 7))))))
 		cvmx_warn("CVMX_FPA_FPFX_MARKS(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1;
 }
@@ -104,7 +141,11 @@ static inline uint64_t CVMX_FPA_FPFX_SIZE(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 1) && (offset <= 7))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 1) && (offset <= 7)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 1) && (offset <= 7)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 1) && (offset <= 7)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 1) && (offset <= 7)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 1) && (offset <= 7))))))
 		cvmx_warn("CVMX_FPA_FPFX_SIZE(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1;
 }
@@ -117,7 +158,7 @@ static inline uint64_t CVMX_FPA_FPFX_SIZE(unsigned long offset)
 #define CVMX_FPA_PACKET_THRESHOLD CVMX_FPA_PACKET_THRESHOLD_FUNC()
 static inline uint64_t CVMX_FPA_PACKET_THRESHOLD_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_FPA_PACKET_THRESHOLD not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180028000460ull);
 }
@@ -125,15 +166,47 @@ static inline uint64_t CVMX_FPA_PACKET_THRESHOLD_FUNC(void)
 #define CVMX_FPA_PACKET_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000460ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_FPA_POOLX_END_ADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_FPA_POOLX_END_ADDR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_FPA_POOLX_END_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_FPA_POOLX_START_ADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_FPA_POOLX_START_ADDR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_FPA_POOLX_START_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_FPA_POOLX_THRESHOLD(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_FPA_POOLX_THRESHOLD(%lu) is invalid on this chip\n", offset);
-	return CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 7) * 8;
+	return CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8;
 }
 #else
-#define CVMX_FPA_POOLX_THRESHOLD(offset) (CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 7) * 8)
+#define CVMX_FPA_POOLX_THRESHOLD(offset) (CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8)
 #endif
 #define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0)
 #define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1)
@@ -144,6 +217,17 @@ static inline uint64_t CVMX_FPA_POOLX_THRESHOLD(unsigned long offset)
 #define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6)
 #define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7)
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_FPA_QUE8_PAGE_INDEX CVMX_FPA_QUE8_PAGE_INDEX_FUNC()
+static inline uint64_t CVMX_FPA_QUE8_PAGE_INDEX_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_FPA_QUE8_PAGE_INDEX not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180028000250ull);
+}
+#else
+#define CVMX_FPA_QUE8_PAGE_INDEX (CVMX_ADD_IO_SEG(0x0001180028000250ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_FPA_QUEX_AVAILABLE(unsigned long offset)
 {
 	if (!(
@@ -154,12 +238,16 @@ static inline uint64_t CVMX_FPA_QUEX_AVAILABLE(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_FPA_QUEX_AVAILABLE(%lu) is invalid on this chip\n", offset);
-	return CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 7) * 8;
+	return CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8;
 }
 #else
-#define CVMX_FPA_QUEX_AVAILABLE(offset) (CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 7) * 8)
+#define CVMX_FPA_QUEX_AVAILABLE(offset) (CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_FPA_QUEX_PAGE_INDEX(unsigned long offset)
@@ -172,7 +260,11 @@ static inline uint64_t CVMX_FPA_QUEX_PAGE_INDEX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_FPA_QUEX_PAGE_INDEX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8;
 }
@@ -207,7 +299,7 @@ static inline uint64_t CVMX_FPA_WART_STATUS_FUNC(void)
 #define CVMX_FPA_WQE_THRESHOLD CVMX_FPA_WQE_THRESHOLD_FUNC()
 static inline uint64_t CVMX_FPA_WQE_THRESHOLD_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_FPA_WQE_THRESHOLD not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180028000468ull);
 }
@@ -216,18 +308,49 @@ static inline uint64_t CVMX_FPA_WQE_THRESHOLD_FUNC(void)
 #endif
 
 /**
+ * cvmx_fpa_addr_range_error
+ *
+ * Space here reserved
+ *
+ *                  FPA_ADDR_RANGE_ERROR = FPA's Pool Address Range Error Information
+ *
+ * When an address is sent to a pool that does not fall in the start and end address spcified by
+ * FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR the information related to the failure is captured here.
+ * In addition FPA_INT_SUM[PADDR_E] will be set and this register will not be updated again till
+ * FPA_INT_SUM[PADDR_E] is cleared.
+ */
+union cvmx_fpa_addr_range_error {
+	uint64_t u64;
+	struct cvmx_fpa_addr_range_error_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_38_63               : 26;
+	uint64_t pool                         : 5;  /**< Pool address sent to. */
+	uint64_t addr                         : 33; /**< Failing address. */
+#else
+	uint64_t addr                         : 33;
+	uint64_t pool                         : 5;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_fpa_addr_range_error_s    cn61xx;
+	struct cvmx_fpa_addr_range_error_s    cn66xx;
+	struct cvmx_fpa_addr_range_error_s    cn68xx;
+	struct cvmx_fpa_addr_range_error_s    cn68xxp1;
+	struct cvmx_fpa_addr_range_error_s    cnf71xx;
+};
+typedef union cvmx_fpa_addr_range_error cvmx_fpa_addr_range_error_t;
+
+/**
  * cvmx_fpa_bist_status
  *
  * FPA_BIST_STATUS = BIST Status of FPA Memories
  *
  * The result of the BIST run on the FPA memories.
  */
-union cvmx_fpa_bist_status
-{
+union cvmx_fpa_bist_status {
 	uint64_t u64;
-	struct cvmx_fpa_bist_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_fpa_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t frd                          : 1;  /**< fpa_frd  memory bist status. */
 	uint64_t fpf0                         : 1;  /**< fpa_fpf0 memory bist status. */
@@ -254,8 +377,13 @@ union cvmx_fpa_bist_status
 	struct cvmx_fpa_bist_status_s         cn56xxp1;
 	struct cvmx_fpa_bist_status_s         cn58xx;
 	struct cvmx_fpa_bist_status_s         cn58xxp1;
+	struct cvmx_fpa_bist_status_s         cn61xx;
 	struct cvmx_fpa_bist_status_s         cn63xx;
 	struct cvmx_fpa_bist_status_s         cn63xxp1;
+	struct cvmx_fpa_bist_status_s         cn66xx;
+	struct cvmx_fpa_bist_status_s         cn68xx;
+	struct cvmx_fpa_bist_status_s         cn68xxp1;
+	struct cvmx_fpa_bist_status_s         cnf71xx;
 };
 typedef union cvmx_fpa_bist_status cvmx_fpa_bist_status_t;
 
@@ -266,20 +394,17 @@ typedef union cvmx_fpa_bist_status cvmx_fpa_bist_status_t;
  *
  * The FPA's interrupt enable register.
  */
-union cvmx_fpa_ctl_status
-{
+union cvmx_fpa_ctl_status {
 	uint64_t u64;
-	struct cvmx_fpa_ctl_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_fpa_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_21_63               : 43;
 	uint64_t free_en                      : 1;  /**< Enables the setting of the INT_SUM_[FREE*] bits. */
 	uint64_t ret_off                      : 1;  /**< When set NCB devices returning pointer will be
                                                          stalled. */
 	uint64_t req_off                      : 1;  /**< When set NCB devices requesting pointers will be
                                                          stalled. */
-	uint64_t reset                        : 1;  /**< When set causes a reset of the FPA with the
-                                                         exception of the RSL. This is a PASS-2 field. */
+	uint64_t reset                        : 1;  /**< When set causes a reset of the FPA with the */
 	uint64_t use_ldt                      : 1;  /**< When clear '0' the FPA will use LDT to load
                                                          pointers from the L2C. This is a PASS-2 field. */
 	uint64_t use_stt                      : 1;  /**< When clear '0' the FPA will use STT to store
@@ -307,9 +432,8 @@ union cvmx_fpa_ctl_status
 	uint64_t reserved_21_63               : 43;
 #endif
 	} s;
-	struct cvmx_fpa_ctl_status_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_fpa_ctl_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t reset                        : 1;  /**< When set causes a reset of the FPA with the
                                                          exception of the RSL. */
@@ -347,8 +471,13 @@ union cvmx_fpa_ctl_status
 	struct cvmx_fpa_ctl_status_cn30xx     cn56xxp1;
 	struct cvmx_fpa_ctl_status_cn30xx     cn58xx;
 	struct cvmx_fpa_ctl_status_cn30xx     cn58xxp1;
+	struct cvmx_fpa_ctl_status_s          cn61xx;
 	struct cvmx_fpa_ctl_status_s          cn63xx;
 	struct cvmx_fpa_ctl_status_cn30xx     cn63xxp1;
+	struct cvmx_fpa_ctl_status_s          cn66xx;
+	struct cvmx_fpa_ctl_status_s          cn68xx;
+	struct cvmx_fpa_ctl_status_s          cn68xxp1;
+	struct cvmx_fpa_ctl_status_s          cnf71xx;
 };
 typedef union cvmx_fpa_ctl_status cvmx_fpa_ctl_status_t;
 
@@ -361,12 +490,10 @@ typedef union cvmx_fpa_ctl_status cvmx_fpa_ctl_status_t;
  * for Queue 1. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend value
  * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75)
  */
-union cvmx_fpa_fpfx_marks
-{
+union cvmx_fpa_fpfx_marks {
 	uint64_t u64;
-	struct cvmx_fpa_fpfx_marks_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_fpa_fpfx_marks_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_22_63               : 42;
 	uint64_t fpf_wr                       : 11; /**< When the number of free-page-pointers in a
                                                           queue exceeds this value the FPA will write
@@ -392,8 +519,13 @@ union cvmx_fpa_fpfx_marks
 	struct cvmx_fpa_fpfx_marks_s          cn56xxp1;
 	struct cvmx_fpa_fpfx_marks_s          cn58xx;
 	struct cvmx_fpa_fpfx_marks_s          cn58xxp1;
+	struct cvmx_fpa_fpfx_marks_s          cn61xx;
 	struct cvmx_fpa_fpfx_marks_s          cn63xx;
 	struct cvmx_fpa_fpfx_marks_s          cn63xxp1;
+	struct cvmx_fpa_fpfx_marks_s          cn66xx;
+	struct cvmx_fpa_fpfx_marks_s          cn68xx;
+	struct cvmx_fpa_fpfx_marks_s          cn68xxp1;
+	struct cvmx_fpa_fpfx_marks_s          cnf71xx;
 };
 typedef union cvmx_fpa_fpfx_marks cvmx_fpa_fpfx_marks_t;
 
@@ -406,12 +538,10 @@ typedef union cvmx_fpa_fpfx_marks cvmx_fpa_fpfx_marks_t;
  * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used.
  * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048.
  */
-union cvmx_fpa_fpfx_size
-{
+union cvmx_fpa_fpfx_size {
 	uint64_t u64;
-	struct cvmx_fpa_fpfx_size_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_fpa_fpfx_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t fpf_siz                      : 11; /**< The number of entries assigned in the FPA FIFO
                                                          (used to hold page-pointers) for this Queue.
@@ -435,8 +565,13 @@ union cvmx_fpa_fpfx_size
 	struct cvmx_fpa_fpfx_size_s           cn56xxp1;
 	struct cvmx_fpa_fpfx_size_s           cn58xx;
 	struct cvmx_fpa_fpfx_size_s           cn58xxp1;
+	struct cvmx_fpa_fpfx_size_s           cn61xx;
 	struct cvmx_fpa_fpfx_size_s           cn63xx;
 	struct cvmx_fpa_fpfx_size_s           cn63xxp1;
+	struct cvmx_fpa_fpfx_size_s           cn66xx;
+	struct cvmx_fpa_fpfx_size_s           cn68xx;
+	struct cvmx_fpa_fpfx_size_s           cn68xxp1;
+	struct cvmx_fpa_fpfx_size_s           cnf71xx;
 };
 typedef union cvmx_fpa_fpfx_size cvmx_fpa_fpfx_size_t;
 
@@ -449,12 +584,10 @@ typedef union cvmx_fpa_fpfx_size cvmx_fpa_fpfx_size_t;
  * for Queue 0. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend value
  * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75)
  */
-union cvmx_fpa_fpf0_marks
-{
+union cvmx_fpa_fpf0_marks {
 	uint64_t u64;
-	struct cvmx_fpa_fpf0_marks_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_fpa_fpf0_marks_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t fpf_wr                       : 12; /**< When the number of free-page-pointers in a
                                                           queue exceeds this value the FPA will write
@@ -480,8 +613,13 @@ union cvmx_fpa_fpf0_marks
 	struct cvmx_fpa_fpf0_marks_s          cn56xxp1;
 	struct cvmx_fpa_fpf0_marks_s          cn58xx;
 	struct cvmx_fpa_fpf0_marks_s          cn58xxp1;
+	struct cvmx_fpa_fpf0_marks_s          cn61xx;
 	struct cvmx_fpa_fpf0_marks_s          cn63xx;
 	struct cvmx_fpa_fpf0_marks_s          cn63xxp1;
+	struct cvmx_fpa_fpf0_marks_s          cn66xx;
+	struct cvmx_fpa_fpf0_marks_s          cn68xx;
+	struct cvmx_fpa_fpf0_marks_s          cn68xxp1;
+	struct cvmx_fpa_fpf0_marks_s          cnf71xx;
 };
 typedef union cvmx_fpa_fpf0_marks cvmx_fpa_fpf0_marks_t;
 
@@ -494,12 +632,10 @@ typedef union cvmx_fpa_fpf0_marks cvmx_fpa_fpf0_marks_t;
  * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used.
  * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048.
  */
-union cvmx_fpa_fpf0_size
-{
+union cvmx_fpa_fpf0_size {
 	uint64_t u64;
-	struct cvmx_fpa_fpf0_size_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_fpa_fpf0_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t fpf_siz                      : 12; /**< The number of entries assigned in the FPA FIFO
                                                          (used to hold page-pointers) for this Queue.
@@ -523,25 +659,106 @@ union cvmx_fpa_fpf0_size
 	struct cvmx_fpa_fpf0_size_s           cn56xxp1;
 	struct cvmx_fpa_fpf0_size_s           cn58xx;
 	struct cvmx_fpa_fpf0_size_s           cn58xxp1;
+	struct cvmx_fpa_fpf0_size_s           cn61xx;
 	struct cvmx_fpa_fpf0_size_s           cn63xx;
 	struct cvmx_fpa_fpf0_size_s           cn63xxp1;
+	struct cvmx_fpa_fpf0_size_s           cn66xx;
+	struct cvmx_fpa_fpf0_size_s           cn68xx;
+	struct cvmx_fpa_fpf0_size_s           cn68xxp1;
+	struct cvmx_fpa_fpf0_size_s           cnf71xx;
 };
 typedef union cvmx_fpa_fpf0_size cvmx_fpa_fpf0_size_t;
 
 /**
+ * cvmx_fpa_fpf8_marks
+ *
+ * Reserved through 0x238 for additional thresholds
+ *
+ *                  FPA_FPF8_MARKS = FPA's Queue 8 Free Page FIFO Read Write Marks
+ *
+ * The high and low watermark register that determines when we write and read free pages from L2C
+ * for Queue 8. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend value
+ * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75)
+ */
+union cvmx_fpa_fpf8_marks {
+	uint64_t u64;
+	struct cvmx_fpa_fpf8_marks_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_22_63               : 42;
+	uint64_t fpf_wr                       : 11; /**< When the number of free-page-pointers in a
+                                                         queue exceeds this value the FPA will write
+                                                         32-page-pointers of that queue to DRAM.
+                                                         The MAX value for this field should be
+                                                         FPA_FPF0_SIZE[FPF_SIZ]-2. */
+	uint64_t fpf_rd                       : 11; /**< When the number of free-page-pointers in a
+                                                         queue drops below this value and there are
+                                                         free-page-pointers in DRAM, the FPA will
+                                                         read one page (32 pointers) from DRAM.
+                                                         This maximum value for this field should be
+                                                         FPA_FPF0_SIZE[FPF_SIZ]-34. The min number
+                                                         for this would be 16. */
+#else
+	uint64_t fpf_rd                       : 11;
+	uint64_t fpf_wr                       : 11;
+	uint64_t reserved_22_63               : 42;
+#endif
+	} s;
+	struct cvmx_fpa_fpf8_marks_s          cn68xx;
+	struct cvmx_fpa_fpf8_marks_s          cn68xxp1;
+};
+typedef union cvmx_fpa_fpf8_marks cvmx_fpa_fpf8_marks_t;
+
+/**
+ * cvmx_fpa_fpf8_size
+ *
+ * FPA_FPF8_SIZE = FPA's Queue 8 Free Page FIFO Size
+ *
+ * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are
+ * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used.
+ * The sum of the 9 (0-8) FPA_FPF#_SIZE registers must be limited to 2048.
+ */
+union cvmx_fpa_fpf8_size {
+	uint64_t u64;
+	struct cvmx_fpa_fpf8_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_12_63               : 52;
+	uint64_t fpf_siz                      : 12; /**< The number of entries assigned in the FPA FIFO
+                                                         (used to hold page-pointers) for this Queue.
+                                                         The value of this register must divisable by 2,
+                                                         and the FPA will ignore bit [0] of this register.
+                                                         The total of the FPF_SIZ field of the 8 (0-7)
+                                                         FPA_FPF#_SIZE registers must not exceed 2048.
+                                                         After writing this field the FPA will need 10
+                                                         core clock cycles to be ready for operation. The
+                                                         assignment of location in the FPA FIFO must
+                                                         start with Queue 0, then 1, 2, etc.
+                                                         The number of useable entries will be FPF_SIZ-2. */
+#else
+	uint64_t fpf_siz                      : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_fpa_fpf8_size_s           cn68xx;
+	struct cvmx_fpa_fpf8_size_s           cn68xxp1;
+};
+typedef union cvmx_fpa_fpf8_size cvmx_fpa_fpf8_size_t;
+
+/**
  * cvmx_fpa_int_enb
  *
  * FPA_INT_ENB = FPA's Interrupt Enable
  *
  * The FPA's interrupt enable register.
  */
-union cvmx_fpa_int_enb
-{
+union cvmx_fpa_int_enb {
 	uint64_t u64;
-	struct cvmx_fpa_int_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_44_63               : 20;
+	struct cvmx_fpa_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_50_63               : 14;
+	uint64_t paddr_e                      : 1;  /**< When set (1) and bit 49 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t reserved_44_48               : 5;
 	uint64_t free7                        : 1;  /**< When set (1) and bit 43 of the FPA_INT_SUM
                                                          register is asserted the FPA will assert an
                                                          interrupt. */
@@ -719,12 +936,13 @@ union cvmx_fpa_int_enb
 	uint64_t free5                        : 1;
 	uint64_t free6                        : 1;
 	uint64_t free7                        : 1;
-	uint64_t reserved_44_63               : 20;
+	uint64_t reserved_44_48               : 5;
+	uint64_t paddr_e                      : 1;
+	uint64_t reserved_50_63               : 14;
 #endif
 	} s;
-	struct cvmx_fpa_int_enb_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_fpa_int_enb_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t q7_perr                      : 1;  /**< When set (1) and bit 27 of the FPA_INT_SUM
                                                          register is asserted the FPA will assert an
@@ -852,8 +1070,589 @@ union cvmx_fpa_int_enb
 	struct cvmx_fpa_int_enb_cn30xx        cn56xxp1;
 	struct cvmx_fpa_int_enb_cn30xx        cn58xx;
 	struct cvmx_fpa_int_enb_cn30xx        cn58xxp1;
-	struct cvmx_fpa_int_enb_s             cn63xx;
+	struct cvmx_fpa_int_enb_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_50_63               : 14;
+	uint64_t paddr_e                      : 1;  /**< When set (1) and bit 49 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t res_44                       : 5;  /**< Reserved */
+	uint64_t free7                        : 1;  /**< When set (1) and bit 43 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free6                        : 1;  /**< When set (1) and bit 42 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free5                        : 1;  /**< When set (1) and bit 41 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free4                        : 1;  /**< When set (1) and bit 40 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free3                        : 1;  /**< When set (1) and bit 39 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free2                        : 1;  /**< When set (1) and bit 38 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free1                        : 1;  /**< When set (1) and bit 37 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free0                        : 1;  /**< When set (1) and bit 36 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool7th                      : 1;  /**< When set (1) and bit 35 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool6th                      : 1;  /**< When set (1) and bit 34 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool5th                      : 1;  /**< When set (1) and bit 33 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool4th                      : 1;  /**< When set (1) and bit 32 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool3th                      : 1;  /**< When set (1) and bit 31 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool2th                      : 1;  /**< When set (1) and bit 30 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool1th                      : 1;  /**< When set (1) and bit 29 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool0th                      : 1;  /**< When set (1) and bit 28 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q7_perr                      : 1;  /**< When set (1) and bit 27 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q7_coff                      : 1;  /**< When set (1) and bit 26 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q7_und                       : 1;  /**< When set (1) and bit 25 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q6_perr                      : 1;  /**< When set (1) and bit 24 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q6_coff                      : 1;  /**< When set (1) and bit 23 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q6_und                       : 1;  /**< When set (1) and bit 22 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q5_perr                      : 1;  /**< When set (1) and bit 21 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q5_coff                      : 1;  /**< When set (1) and bit 20 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q5_und                       : 1;  /**< When set (1) and bit 19 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q4_perr                      : 1;  /**< When set (1) and bit 18 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q4_coff                      : 1;  /**< When set (1) and bit 17 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q4_und                       : 1;  /**< When set (1) and bit 16 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q3_perr                      : 1;  /**< When set (1) and bit 15 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q3_coff                      : 1;  /**< When set (1) and bit 14 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q3_und                       : 1;  /**< When set (1) and bit 13 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q2_perr                      : 1;  /**< When set (1) and bit 12 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q2_coff                      : 1;  /**< When set (1) and bit 11 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q2_und                       : 1;  /**< When set (1) and bit 10 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q1_perr                      : 1;  /**< When set (1) and bit 9 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q1_coff                      : 1;  /**< When set (1) and bit 8 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q1_und                       : 1;  /**< When set (1) and bit 7 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q0_perr                      : 1;  /**< When set (1) and bit 6 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q0_coff                      : 1;  /**< When set (1) and bit 5 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q0_und                       : 1;  /**< When set (1) and bit 4 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed1_dbe                     : 1;  /**< When set (1) and bit 3 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed1_sbe                     : 1;  /**< When set (1) and bit 2 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed0_dbe                     : 1;  /**< When set (1) and bit 1 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed0_sbe                     : 1;  /**< When set (1) and bit 0 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+#else
+	uint64_t fed0_sbe                     : 1;
+	uint64_t fed0_dbe                     : 1;
+	uint64_t fed1_sbe                     : 1;
+	uint64_t fed1_dbe                     : 1;
+	uint64_t q0_und                       : 1;
+	uint64_t q0_coff                      : 1;
+	uint64_t q0_perr                      : 1;
+	uint64_t q1_und                       : 1;
+	uint64_t q1_coff                      : 1;
+	uint64_t q1_perr                      : 1;
+	uint64_t q2_und                       : 1;
+	uint64_t q2_coff                      : 1;
+	uint64_t q2_perr                      : 1;
+	uint64_t q3_und                       : 1;
+	uint64_t q3_coff                      : 1;
+	uint64_t q3_perr                      : 1;
+	uint64_t q4_und                       : 1;
+	uint64_t q4_coff                      : 1;
+	uint64_t q4_perr                      : 1;
+	uint64_t q5_und                       : 1;
+	uint64_t q5_coff                      : 1;
+	uint64_t q5_perr                      : 1;
+	uint64_t q6_und                       : 1;
+	uint64_t q6_coff                      : 1;
+	uint64_t q6_perr                      : 1;
+	uint64_t q7_und                       : 1;
+	uint64_t q7_coff                      : 1;
+	uint64_t q7_perr                      : 1;
+	uint64_t pool0th                      : 1;
+	uint64_t pool1th                      : 1;
+	uint64_t pool2th                      : 1;
+	uint64_t pool3th                      : 1;
+	uint64_t pool4th                      : 1;
+	uint64_t pool5th                      : 1;
+	uint64_t pool6th                      : 1;
+	uint64_t pool7th                      : 1;
+	uint64_t free0                        : 1;
+	uint64_t free1                        : 1;
+	uint64_t free2                        : 1;
+	uint64_t free3                        : 1;
+	uint64_t free4                        : 1;
+	uint64_t free5                        : 1;
+	uint64_t free6                        : 1;
+	uint64_t free7                        : 1;
+	uint64_t res_44                       : 5;
+	uint64_t paddr_e                      : 1;
+	uint64_t reserved_50_63               : 14;
+#endif
+	} cn61xx;
+	struct cvmx_fpa_int_enb_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_44_63               : 20;
+	uint64_t free7                        : 1;  /**< When set (1) and bit 43 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free6                        : 1;  /**< When set (1) and bit 42 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free5                        : 1;  /**< When set (1) and bit 41 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free4                        : 1;  /**< When set (1) and bit 40 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free3                        : 1;  /**< When set (1) and bit 39 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free2                        : 1;  /**< When set (1) and bit 38 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free1                        : 1;  /**< When set (1) and bit 37 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free0                        : 1;  /**< When set (1) and bit 36 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool7th                      : 1;  /**< When set (1) and bit 35 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool6th                      : 1;  /**< When set (1) and bit 34 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool5th                      : 1;  /**< When set (1) and bit 33 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool4th                      : 1;  /**< When set (1) and bit 32 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool3th                      : 1;  /**< When set (1) and bit 31 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool2th                      : 1;  /**< When set (1) and bit 30 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool1th                      : 1;  /**< When set (1) and bit 29 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool0th                      : 1;  /**< When set (1) and bit 28 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q7_perr                      : 1;  /**< When set (1) and bit 27 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q7_coff                      : 1;  /**< When set (1) and bit 26 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q7_und                       : 1;  /**< When set (1) and bit 25 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q6_perr                      : 1;  /**< When set (1) and bit 24 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q6_coff                      : 1;  /**< When set (1) and bit 23 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q6_und                       : 1;  /**< When set (1) and bit 22 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q5_perr                      : 1;  /**< When set (1) and bit 21 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q5_coff                      : 1;  /**< When set (1) and bit 20 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q5_und                       : 1;  /**< When set (1) and bit 19 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q4_perr                      : 1;  /**< When set (1) and bit 18 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q4_coff                      : 1;  /**< When set (1) and bit 17 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q4_und                       : 1;  /**< When set (1) and bit 16 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q3_perr                      : 1;  /**< When set (1) and bit 15 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q3_coff                      : 1;  /**< When set (1) and bit 14 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q3_und                       : 1;  /**< When set (1) and bit 13 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q2_perr                      : 1;  /**< When set (1) and bit 12 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q2_coff                      : 1;  /**< When set (1) and bit 11 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q2_und                       : 1;  /**< When set (1) and bit 10 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q1_perr                      : 1;  /**< When set (1) and bit 9 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q1_coff                      : 1;  /**< When set (1) and bit 8 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q1_und                       : 1;  /**< When set (1) and bit 7 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q0_perr                      : 1;  /**< When set (1) and bit 6 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q0_coff                      : 1;  /**< When set (1) and bit 5 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q0_und                       : 1;  /**< When set (1) and bit 4 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed1_dbe                     : 1;  /**< When set (1) and bit 3 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed1_sbe                     : 1;  /**< When set (1) and bit 2 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed0_dbe                     : 1;  /**< When set (1) and bit 1 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed0_sbe                     : 1;  /**< When set (1) and bit 0 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+#else
+	uint64_t fed0_sbe                     : 1;
+	uint64_t fed0_dbe                     : 1;
+	uint64_t fed1_sbe                     : 1;
+	uint64_t fed1_dbe                     : 1;
+	uint64_t q0_und                       : 1;
+	uint64_t q0_coff                      : 1;
+	uint64_t q0_perr                      : 1;
+	uint64_t q1_und                       : 1;
+	uint64_t q1_coff                      : 1;
+	uint64_t q1_perr                      : 1;
+	uint64_t q2_und                       : 1;
+	uint64_t q2_coff                      : 1;
+	uint64_t q2_perr                      : 1;
+	uint64_t q3_und                       : 1;
+	uint64_t q3_coff                      : 1;
+	uint64_t q3_perr                      : 1;
+	uint64_t q4_und                       : 1;
+	uint64_t q4_coff                      : 1;
+	uint64_t q4_perr                      : 1;
+	uint64_t q5_und                       : 1;
+	uint64_t q5_coff                      : 1;
+	uint64_t q5_perr                      : 1;
+	uint64_t q6_und                       : 1;
+	uint64_t q6_coff                      : 1;
+	uint64_t q6_perr                      : 1;
+	uint64_t q7_und                       : 1;
+	uint64_t q7_coff                      : 1;
+	uint64_t q7_perr                      : 1;
+	uint64_t pool0th                      : 1;
+	uint64_t pool1th                      : 1;
+	uint64_t pool2th                      : 1;
+	uint64_t pool3th                      : 1;
+	uint64_t pool4th                      : 1;
+	uint64_t pool5th                      : 1;
+	uint64_t pool6th                      : 1;
+	uint64_t pool7th                      : 1;
+	uint64_t free0                        : 1;
+	uint64_t free1                        : 1;
+	uint64_t free2                        : 1;
+	uint64_t free3                        : 1;
+	uint64_t free4                        : 1;
+	uint64_t free5                        : 1;
+	uint64_t free6                        : 1;
+	uint64_t free7                        : 1;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} cn63xx;
 	struct cvmx_fpa_int_enb_cn30xx        cn63xxp1;
+	struct cvmx_fpa_int_enb_cn61xx        cn66xx;
+	struct cvmx_fpa_int_enb_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_50_63               : 14;
+	uint64_t paddr_e                      : 1;  /**< When set (1) and bit 49 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool8th                      : 1;  /**< When set (1) and bit 48 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q8_perr                      : 1;  /**< When set (1) and bit 47 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q8_coff                      : 1;  /**< When set (1) and bit 46 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q8_und                       : 1;  /**< When set (1) and bit 45 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free8                        : 1;  /**< When set (1) and bit 44 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free7                        : 1;  /**< When set (1) and bit 43 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free6                        : 1;  /**< When set (1) and bit 42 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free5                        : 1;  /**< When set (1) and bit 41 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free4                        : 1;  /**< When set (1) and bit 40 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free3                        : 1;  /**< When set (1) and bit 39 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free2                        : 1;  /**< When set (1) and bit 38 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free1                        : 1;  /**< When set (1) and bit 37 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free0                        : 1;  /**< When set (1) and bit 36 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool7th                      : 1;  /**< When set (1) and bit 35 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool6th                      : 1;  /**< When set (1) and bit 34 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool5th                      : 1;  /**< When set (1) and bit 33 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool4th                      : 1;  /**< When set (1) and bit 32 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool3th                      : 1;  /**< When set (1) and bit 31 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool2th                      : 1;  /**< When set (1) and bit 30 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool1th                      : 1;  /**< When set (1) and bit 29 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool0th                      : 1;  /**< When set (1) and bit 28 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q7_perr                      : 1;  /**< When set (1) and bit 27 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q7_coff                      : 1;  /**< When set (1) and bit 26 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q7_und                       : 1;  /**< When set (1) and bit 25 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q6_perr                      : 1;  /**< When set (1) and bit 24 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q6_coff                      : 1;  /**< When set (1) and bit 23 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q6_und                       : 1;  /**< When set (1) and bit 22 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q5_perr                      : 1;  /**< When set (1) and bit 21 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q5_coff                      : 1;  /**< When set (1) and bit 20 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q5_und                       : 1;  /**< When set (1) and bit 19 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q4_perr                      : 1;  /**< When set (1) and bit 18 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q4_coff                      : 1;  /**< When set (1) and bit 17 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q4_und                       : 1;  /**< When set (1) and bit 16 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q3_perr                      : 1;  /**< When set (1) and bit 15 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q3_coff                      : 1;  /**< When set (1) and bit 14 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q3_und                       : 1;  /**< When set (1) and bit 13 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q2_perr                      : 1;  /**< When set (1) and bit 12 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q2_coff                      : 1;  /**< When set (1) and bit 11 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q2_und                       : 1;  /**< When set (1) and bit 10 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q1_perr                      : 1;  /**< When set (1) and bit 9 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q1_coff                      : 1;  /**< When set (1) and bit 8 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q1_und                       : 1;  /**< When set (1) and bit 7 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q0_perr                      : 1;  /**< When set (1) and bit 6 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q0_coff                      : 1;  /**< When set (1) and bit 5 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q0_und                       : 1;  /**< When set (1) and bit 4 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed1_dbe                     : 1;  /**< When set (1) and bit 3 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed1_sbe                     : 1;  /**< When set (1) and bit 2 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed0_dbe                     : 1;  /**< When set (1) and bit 1 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed0_sbe                     : 1;  /**< When set (1) and bit 0 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+#else
+	uint64_t fed0_sbe                     : 1;
+	uint64_t fed0_dbe                     : 1;
+	uint64_t fed1_sbe                     : 1;
+	uint64_t fed1_dbe                     : 1;
+	uint64_t q0_und                       : 1;
+	uint64_t q0_coff                      : 1;
+	uint64_t q0_perr                      : 1;
+	uint64_t q1_und                       : 1;
+	uint64_t q1_coff                      : 1;
+	uint64_t q1_perr                      : 1;
+	uint64_t q2_und                       : 1;
+	uint64_t q2_coff                      : 1;
+	uint64_t q2_perr                      : 1;
+	uint64_t q3_und                       : 1;
+	uint64_t q3_coff                      : 1;
+	uint64_t q3_perr                      : 1;
+	uint64_t q4_und                       : 1;
+	uint64_t q4_coff                      : 1;
+	uint64_t q4_perr                      : 1;
+	uint64_t q5_und                       : 1;
+	uint64_t q5_coff                      : 1;
+	uint64_t q5_perr                      : 1;
+	uint64_t q6_und                       : 1;
+	uint64_t q6_coff                      : 1;
+	uint64_t q6_perr                      : 1;
+	uint64_t q7_und                       : 1;
+	uint64_t q7_coff                      : 1;
+	uint64_t q7_perr                      : 1;
+	uint64_t pool0th                      : 1;
+	uint64_t pool1th                      : 1;
+	uint64_t pool2th                      : 1;
+	uint64_t pool3th                      : 1;
+	uint64_t pool4th                      : 1;
+	uint64_t pool5th                      : 1;
+	uint64_t pool6th                      : 1;
+	uint64_t pool7th                      : 1;
+	uint64_t free0                        : 1;
+	uint64_t free1                        : 1;
+	uint64_t free2                        : 1;
+	uint64_t free3                        : 1;
+	uint64_t free4                        : 1;
+	uint64_t free5                        : 1;
+	uint64_t free6                        : 1;
+	uint64_t free7                        : 1;
+	uint64_t free8                        : 1;
+	uint64_t q8_und                       : 1;
+	uint64_t q8_coff                      : 1;
+	uint64_t q8_perr                      : 1;
+	uint64_t pool8th                      : 1;
+	uint64_t paddr_e                      : 1;
+	uint64_t reserved_50_63               : 14;
+#endif
+	} cn68xx;
+	struct cvmx_fpa_int_enb_cn68xx        cn68xxp1;
+	struct cvmx_fpa_int_enb_cn61xx        cnf71xx;
 };
 typedef union cvmx_fpa_int_enb cvmx_fpa_int_enb_t;
 
@@ -864,13 +1663,25 @@ typedef union cvmx_fpa_int_enb cvmx_fpa_int_enb_t;
  *
  * Contains the different interrupt summary bits of the FPA.
  */
-union cvmx_fpa_int_sum
-{
+union cvmx_fpa_int_sum {
 	uint64_t u64;
-	struct cvmx_fpa_int_sum_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_44_63               : 20;
+	struct cvmx_fpa_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_50_63               : 14;
+	uint64_t paddr_e                      : 1;  /**< Set when a pointer address does not fall in the
+                                                         address range for a pool specified by
+                                                         FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR. */
+	uint64_t pool8th                      : 1;  /**< Set when FPA_QUE8_AVAILABLE is equal to
+                                                         FPA_POOL8_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t q8_perr                      : 1;  /**< Set when a Queue8 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q8_coff                      : 1;  /**< Set when a Queue8 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q8_und                       : 1;  /**< Set when a Queue8 page count available goes
+                                                         negative. */
+	uint64_t free8                        : 1;  /**< When a pointer for POOL8 is freed bit is set. */
 	uint64_t free7                        : 1;  /**< When a pointer for POOL7 is freed bit is set. */
 	uint64_t free6                        : 1;  /**< When a pointer for POOL6 is freed bit is set. */
 	uint64_t free5                        : 1;  /**< When a pointer for POOL5 is freed bit is set. */
@@ -1008,12 +1819,17 @@ union cvmx_fpa_int_sum
 	uint64_t free5                        : 1;
 	uint64_t free6                        : 1;
 	uint64_t free7                        : 1;
-	uint64_t reserved_44_63               : 20;
+	uint64_t free8                        : 1;
+	uint64_t q8_und                       : 1;
+	uint64_t q8_coff                      : 1;
+	uint64_t q8_perr                      : 1;
+	uint64_t pool8th                      : 1;
+	uint64_t paddr_e                      : 1;
+	uint64_t reserved_50_63               : 14;
 #endif
 	} s;
-	struct cvmx_fpa_int_sum_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_fpa_int_sum_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t q7_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
                                                          the L2C does not have the FPA owner ship bit set. */
@@ -1117,8 +1933,303 @@ union cvmx_fpa_int_sum
 	struct cvmx_fpa_int_sum_cn30xx        cn56xxp1;
 	struct cvmx_fpa_int_sum_cn30xx        cn58xx;
 	struct cvmx_fpa_int_sum_cn30xx        cn58xxp1;
-	struct cvmx_fpa_int_sum_s             cn63xx;
+	struct cvmx_fpa_int_sum_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_50_63               : 14;
+	uint64_t paddr_e                      : 1;  /**< Set when a pointer address does not fall in the
+                                                         address range for a pool specified by
+                                                         FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR. */
+	uint64_t reserved_44_48               : 5;
+	uint64_t free7                        : 1;  /**< When a pointer for POOL7 is freed bit is set. */
+	uint64_t free6                        : 1;  /**< When a pointer for POOL6 is freed bit is set. */
+	uint64_t free5                        : 1;  /**< When a pointer for POOL5 is freed bit is set. */
+	uint64_t free4                        : 1;  /**< When a pointer for POOL4 is freed bit is set. */
+	uint64_t free3                        : 1;  /**< When a pointer for POOL3 is freed bit is set. */
+	uint64_t free2                        : 1;  /**< When a pointer for POOL2 is freed bit is set. */
+	uint64_t free1                        : 1;  /**< When a pointer for POOL1 is freed bit is set. */
+	uint64_t free0                        : 1;  /**< When a pointer for POOL0 is freed bit is set. */
+	uint64_t pool7th                      : 1;  /**< Set when FPA_QUE7_AVAILABLE is equal to
+                                                         FPA_POOL7_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool6th                      : 1;  /**< Set when FPA_QUE6_AVAILABLE is equal to
+                                                         FPA_POOL6_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool5th                      : 1;  /**< Set when FPA_QUE5_AVAILABLE is equal to
+                                                         FPA_POOL5_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool4th                      : 1;  /**< Set when FPA_QUE4_AVAILABLE is equal to
+                                                         FPA_POOL4_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool3th                      : 1;  /**< Set when FPA_QUE3_AVAILABLE is equal to
+                                                         FPA_POOL3_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool2th                      : 1;  /**< Set when FPA_QUE2_AVAILABLE is equal to
+                                                         FPA_POOL2_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool1th                      : 1;  /**< Set when FPA_QUE1_AVAILABLE is equal to
+                                                         FPA_POOL1_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool0th                      : 1;  /**< Set when FPA_QUE0_AVAILABLE is equal to
+                                                         FPA_POOL`_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t q7_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q7_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q7_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q6_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q6_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q6_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q5_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q5_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q5_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q4_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q4_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q4_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q3_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q3_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q3_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q2_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q2_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q2_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q1_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q1_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than pointers
+                                                         present in the FPA. */
+	uint64_t q1_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q0_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q0_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than pointers
+                                                         present in the FPA. */
+	uint64_t q0_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t fed1_dbe                     : 1;  /**< Set when a Double Bit Error is detected in FPF1. */
+	uint64_t fed1_sbe                     : 1;  /**< Set when a Single Bit Error is detected in FPF1. */
+	uint64_t fed0_dbe                     : 1;  /**< Set when a Double Bit Error is detected in FPF0. */
+	uint64_t fed0_sbe                     : 1;  /**< Set when a Single Bit Error is detected in FPF0. */
+#else
+	uint64_t fed0_sbe                     : 1;
+	uint64_t fed0_dbe                     : 1;
+	uint64_t fed1_sbe                     : 1;
+	uint64_t fed1_dbe                     : 1;
+	uint64_t q0_und                       : 1;
+	uint64_t q0_coff                      : 1;
+	uint64_t q0_perr                      : 1;
+	uint64_t q1_und                       : 1;
+	uint64_t q1_coff                      : 1;
+	uint64_t q1_perr                      : 1;
+	uint64_t q2_und                       : 1;
+	uint64_t q2_coff                      : 1;
+	uint64_t q2_perr                      : 1;
+	uint64_t q3_und                       : 1;
+	uint64_t q3_coff                      : 1;
+	uint64_t q3_perr                      : 1;
+	uint64_t q4_und                       : 1;
+	uint64_t q4_coff                      : 1;
+	uint64_t q4_perr                      : 1;
+	uint64_t q5_und                       : 1;
+	uint64_t q5_coff                      : 1;
+	uint64_t q5_perr                      : 1;
+	uint64_t q6_und                       : 1;
+	uint64_t q6_coff                      : 1;
+	uint64_t q6_perr                      : 1;
+	uint64_t q7_und                       : 1;
+	uint64_t q7_coff                      : 1;
+	uint64_t q7_perr                      : 1;
+	uint64_t pool0th                      : 1;
+	uint64_t pool1th                      : 1;
+	uint64_t pool2th                      : 1;
+	uint64_t pool3th                      : 1;
+	uint64_t pool4th                      : 1;
+	uint64_t pool5th                      : 1;
+	uint64_t pool6th                      : 1;
+	uint64_t pool7th                      : 1;
+	uint64_t free0                        : 1;
+	uint64_t free1                        : 1;
+	uint64_t free2                        : 1;
+	uint64_t free3                        : 1;
+	uint64_t free4                        : 1;
+	uint64_t free5                        : 1;
+	uint64_t free6                        : 1;
+	uint64_t free7                        : 1;
+	uint64_t reserved_44_48               : 5;
+	uint64_t paddr_e                      : 1;
+	uint64_t reserved_50_63               : 14;
+#endif
+	} cn61xx;
+	struct cvmx_fpa_int_sum_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_44_63               : 20;
+	uint64_t free7                        : 1;  /**< When a pointer for POOL7 is freed bit is set. */
+	uint64_t free6                        : 1;  /**< When a pointer for POOL6 is freed bit is set. */
+	uint64_t free5                        : 1;  /**< When a pointer for POOL5 is freed bit is set. */
+	uint64_t free4                        : 1;  /**< When a pointer for POOL4 is freed bit is set. */
+	uint64_t free3                        : 1;  /**< When a pointer for POOL3 is freed bit is set. */
+	uint64_t free2                        : 1;  /**< When a pointer for POOL2 is freed bit is set. */
+	uint64_t free1                        : 1;  /**< When a pointer for POOL1 is freed bit is set. */
+	uint64_t free0                        : 1;  /**< When a pointer for POOL0 is freed bit is set. */
+	uint64_t pool7th                      : 1;  /**< Set when FPA_QUE7_AVAILABLE is equal to
+                                                         FPA_POOL7_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool6th                      : 1;  /**< Set when FPA_QUE6_AVAILABLE is equal to
+                                                         FPA_POOL6_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool5th                      : 1;  /**< Set when FPA_QUE5_AVAILABLE is equal to
+                                                         FPA_POOL5_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool4th                      : 1;  /**< Set when FPA_QUE4_AVAILABLE is equal to
+                                                         FPA_POOL4_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool3th                      : 1;  /**< Set when FPA_QUE3_AVAILABLE is equal to
+                                                         FPA_POOL3_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool2th                      : 1;  /**< Set when FPA_QUE2_AVAILABLE is equal to
+                                                         FPA_POOL2_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool1th                      : 1;  /**< Set when FPA_QUE1_AVAILABLE is equal to
+                                                         FPA_POOL1_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool0th                      : 1;  /**< Set when FPA_QUE0_AVAILABLE is equal to
+                                                         FPA_POOL`_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t q7_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q7_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q7_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q6_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q6_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q6_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q5_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q5_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q5_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q4_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q4_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q4_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q3_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q3_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q3_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q2_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q2_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q2_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q1_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q1_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than pointers
+                                                         present in the FPA. */
+	uint64_t q1_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q0_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q0_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than pointers
+                                                         present in the FPA. */
+	uint64_t q0_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t fed1_dbe                     : 1;  /**< Set when a Double Bit Error is detected in FPF1. */
+	uint64_t fed1_sbe                     : 1;  /**< Set when a Single Bit Error is detected in FPF1. */
+	uint64_t fed0_dbe                     : 1;  /**< Set when a Double Bit Error is detected in FPF0. */
+	uint64_t fed0_sbe                     : 1;  /**< Set when a Single Bit Error is detected in FPF0. */
+#else
+	uint64_t fed0_sbe                     : 1;
+	uint64_t fed0_dbe                     : 1;
+	uint64_t fed1_sbe                     : 1;
+	uint64_t fed1_dbe                     : 1;
+	uint64_t q0_und                       : 1;
+	uint64_t q0_coff                      : 1;
+	uint64_t q0_perr                      : 1;
+	uint64_t q1_und                       : 1;
+	uint64_t q1_coff                      : 1;
+	uint64_t q1_perr                      : 1;
+	uint64_t q2_und                       : 1;
+	uint64_t q2_coff                      : 1;
+	uint64_t q2_perr                      : 1;
+	uint64_t q3_und                       : 1;
+	uint64_t q3_coff                      : 1;
+	uint64_t q3_perr                      : 1;
+	uint64_t q4_und                       : 1;
+	uint64_t q4_coff                      : 1;
+	uint64_t q4_perr                      : 1;
+	uint64_t q5_und                       : 1;
+	uint64_t q5_coff                      : 1;
+	uint64_t q5_perr                      : 1;
+	uint64_t q6_und                       : 1;
+	uint64_t q6_coff                      : 1;
+	uint64_t q6_perr                      : 1;
+	uint64_t q7_und                       : 1;
+	uint64_t q7_coff                      : 1;
+	uint64_t q7_perr                      : 1;
+	uint64_t pool0th                      : 1;
+	uint64_t pool1th                      : 1;
+	uint64_t pool2th                      : 1;
+	uint64_t pool3th                      : 1;
+	uint64_t pool4th                      : 1;
+	uint64_t pool5th                      : 1;
+	uint64_t pool6th                      : 1;
+	uint64_t pool7th                      : 1;
+	uint64_t free0                        : 1;
+	uint64_t free1                        : 1;
+	uint64_t free2                        : 1;
+	uint64_t free3                        : 1;
+	uint64_t free4                        : 1;
+	uint64_t free5                        : 1;
+	uint64_t free6                        : 1;
+	uint64_t free7                        : 1;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} cn63xx;
 	struct cvmx_fpa_int_sum_cn30xx        cn63xxp1;
+	struct cvmx_fpa_int_sum_cn61xx        cn66xx;
+	struct cvmx_fpa_int_sum_s             cn68xx;
+	struct cvmx_fpa_int_sum_s             cn68xxp1;
+	struct cvmx_fpa_int_sum_cn61xx        cnf71xx;
 };
 typedef union cvmx_fpa_int_sum cvmx_fpa_int_sum_t;
 
@@ -1131,12 +2242,10 @@ typedef union cvmx_fpa_int_sum cvmx_fpa_int_sum_t;
  * PCIe packet instruction engine (to make it stop reading instructions) and to the Packet-Arbiter informing it to not give grants
  * to packets MAC with the exception of the PCIe MAC.
  */
-union cvmx_fpa_packet_threshold
-{
+union cvmx_fpa_packet_threshold {
 	uint64_t u64;
-	struct cvmx_fpa_packet_threshold_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_fpa_packet_threshold_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t thresh                       : 32; /**< Packet Threshold. */
 #else
@@ -1144,11 +2253,70 @@ union cvmx_fpa_packet_threshold
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_fpa_packet_threshold_s    cn61xx;
 	struct cvmx_fpa_packet_threshold_s    cn63xx;
+	struct cvmx_fpa_packet_threshold_s    cn66xx;
+	struct cvmx_fpa_packet_threshold_s    cn68xx;
+	struct cvmx_fpa_packet_threshold_s    cn68xxp1;
+	struct cvmx_fpa_packet_threshold_s    cnf71xx;
 };
 typedef union cvmx_fpa_packet_threshold cvmx_fpa_packet_threshold_t;
 
 /**
+ * cvmx_fpa_pool#_end_addr
+ *
+ * Space here reserved
+ *
+ *                  FPA_POOLX_END_ADDR = FPA's Pool-X Ending Addres
+ *
+ * Pointers sent to this pool must be equal to or less than this address.
+ */
+union cvmx_fpa_poolx_end_addr {
+	uint64_t u64;
+	struct cvmx_fpa_poolx_end_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_33_63               : 31;
+	uint64_t addr                         : 33; /**< Address. */
+#else
+	uint64_t addr                         : 33;
+	uint64_t reserved_33_63               : 31;
+#endif
+	} s;
+	struct cvmx_fpa_poolx_end_addr_s      cn61xx;
+	struct cvmx_fpa_poolx_end_addr_s      cn66xx;
+	struct cvmx_fpa_poolx_end_addr_s      cn68xx;
+	struct cvmx_fpa_poolx_end_addr_s      cn68xxp1;
+	struct cvmx_fpa_poolx_end_addr_s      cnf71xx;
+};
+typedef union cvmx_fpa_poolx_end_addr cvmx_fpa_poolx_end_addr_t;
+
+/**
+ * cvmx_fpa_pool#_start_addr
+ *
+ * FPA_POOLX_START_ADDR = FPA's Pool-X Starting Addres
+ *
+ * Pointers sent to this pool must be equal to or greater than this address.
+ */
+union cvmx_fpa_poolx_start_addr {
+	uint64_t u64;
+	struct cvmx_fpa_poolx_start_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_33_63               : 31;
+	uint64_t addr                         : 33; /**< Address. */
+#else
+	uint64_t addr                         : 33;
+	uint64_t reserved_33_63               : 31;
+#endif
+	} s;
+	struct cvmx_fpa_poolx_start_addr_s    cn61xx;
+	struct cvmx_fpa_poolx_start_addr_s    cn66xx;
+	struct cvmx_fpa_poolx_start_addr_s    cn68xx;
+	struct cvmx_fpa_poolx_start_addr_s    cn68xxp1;
+	struct cvmx_fpa_poolx_start_addr_s    cnf71xx;
+};
+typedef union cvmx_fpa_poolx_start_addr cvmx_fpa_poolx_start_addr_t;
+
+/**
  * cvmx_fpa_pool#_threshold
  *
  * FPA_POOLX_THRESHOLD = FPA's Pool 0-7 Threshold
@@ -1156,20 +2324,31 @@ typedef union cvmx_fpa_packet_threshold cvmx_fpa_packet_threshold_t;
  * When the value of FPA_QUEX_AVAILABLE is equal to FPA_POOLX_THRESHOLD[THRESH] when a pointer is allocated
  * or deallocated, set interrupt FPA_INT_SUM[POOLXTH].
  */
-union cvmx_fpa_poolx_threshold
-{
+union cvmx_fpa_poolx_threshold {
 	uint64_t u64;
-	struct cvmx_fpa_poolx_threshold_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_fpa_poolx_threshold_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t thresh                       : 32; /**< The Threshold. */
+#else
+	uint64_t thresh                       : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_fpa_poolx_threshold_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t thresh                       : 29; /**< The Threshold. */
 #else
 	uint64_t thresh                       : 29;
 	uint64_t reserved_29_63               : 35;
 #endif
-	} s;
-	struct cvmx_fpa_poolx_threshold_s     cn63xx;
+	} cn61xx;
+	struct cvmx_fpa_poolx_threshold_cn61xx cn63xx;
+	struct cvmx_fpa_poolx_threshold_cn61xx cn66xx;
+	struct cvmx_fpa_poolx_threshold_s     cn68xx;
+	struct cvmx_fpa_poolx_threshold_s     cn68xxp1;
+	struct cvmx_fpa_poolx_threshold_cn61xx cnf71xx;
 };
 typedef union cvmx_fpa_poolx_threshold cvmx_fpa_poolx_threshold_t;
 
@@ -1180,33 +2359,44 @@ typedef union cvmx_fpa_poolx_threshold cvmx_fpa_poolx_threshold_t;
  *
  * The number of page pointers that are available in the FPA and local DRAM.
  */
-union cvmx_fpa_quex_available
-{
+union cvmx_fpa_quex_available {
 	uint64_t u64;
-	struct cvmx_fpa_quex_available_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_29_63               : 35;
-	uint64_t que_siz                      : 29; /**< The number of free pages available in this Queue.
+	struct cvmx_fpa_quex_available_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t que_siz                      : 32; /**< The number of free pages available in this Queue.
                                                          In PASS-1 this field was [25:0]. */
 #else
+	uint64_t que_siz                      : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_fpa_quex_available_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_29_63               : 35;
+	uint64_t que_siz                      : 29; /**< The number of free pages available in this Queue. */
+#else
 	uint64_t que_siz                      : 29;
 	uint64_t reserved_29_63               : 35;
 #endif
-	} s;
-	struct cvmx_fpa_quex_available_s      cn30xx;
-	struct cvmx_fpa_quex_available_s      cn31xx;
-	struct cvmx_fpa_quex_available_s      cn38xx;
-	struct cvmx_fpa_quex_available_s      cn38xxp2;
-	struct cvmx_fpa_quex_available_s      cn50xx;
-	struct cvmx_fpa_quex_available_s      cn52xx;
-	struct cvmx_fpa_quex_available_s      cn52xxp1;
-	struct cvmx_fpa_quex_available_s      cn56xx;
-	struct cvmx_fpa_quex_available_s      cn56xxp1;
-	struct cvmx_fpa_quex_available_s      cn58xx;
-	struct cvmx_fpa_quex_available_s      cn58xxp1;
-	struct cvmx_fpa_quex_available_s      cn63xx;
-	struct cvmx_fpa_quex_available_s      cn63xxp1;
+	} cn30xx;
+	struct cvmx_fpa_quex_available_cn30xx cn31xx;
+	struct cvmx_fpa_quex_available_cn30xx cn38xx;
+	struct cvmx_fpa_quex_available_cn30xx cn38xxp2;
+	struct cvmx_fpa_quex_available_cn30xx cn50xx;
+	struct cvmx_fpa_quex_available_cn30xx cn52xx;
+	struct cvmx_fpa_quex_available_cn30xx cn52xxp1;
+	struct cvmx_fpa_quex_available_cn30xx cn56xx;
+	struct cvmx_fpa_quex_available_cn30xx cn56xxp1;
+	struct cvmx_fpa_quex_available_cn30xx cn58xx;
+	struct cvmx_fpa_quex_available_cn30xx cn58xxp1;
+	struct cvmx_fpa_quex_available_cn30xx cn61xx;
+	struct cvmx_fpa_quex_available_cn30xx cn63xx;
+	struct cvmx_fpa_quex_available_cn30xx cn63xxp1;
+	struct cvmx_fpa_quex_available_cn30xx cn66xx;
+	struct cvmx_fpa_quex_available_s      cn68xx;
+	struct cvmx_fpa_quex_available_s      cn68xxp1;
+	struct cvmx_fpa_quex_available_cn30xx cnf71xx;
 };
 typedef union cvmx_fpa_quex_available cvmx_fpa_quex_available_t;
 
@@ -1219,12 +2409,10 @@ typedef union cvmx_fpa_quex_available cvmx_fpa_quex_available_t;
  * This number reflects the number of pages of pointers that have been written to memory
  * for this queue.
  */
-union cvmx_fpa_quex_page_index
-{
+union cvmx_fpa_quex_page_index {
 	uint64_t u64;
-	struct cvmx_fpa_quex_page_index_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_fpa_quex_page_index_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_25_63               : 39;
 	uint64_t pg_num                       : 25; /**< Page number. */
 #else
@@ -1243,12 +2431,43 @@ union cvmx_fpa_quex_page_index
 	struct cvmx_fpa_quex_page_index_s     cn56xxp1;
 	struct cvmx_fpa_quex_page_index_s     cn58xx;
 	struct cvmx_fpa_quex_page_index_s     cn58xxp1;
+	struct cvmx_fpa_quex_page_index_s     cn61xx;
 	struct cvmx_fpa_quex_page_index_s     cn63xx;
 	struct cvmx_fpa_quex_page_index_s     cn63xxp1;
+	struct cvmx_fpa_quex_page_index_s     cn66xx;
+	struct cvmx_fpa_quex_page_index_s     cn68xx;
+	struct cvmx_fpa_quex_page_index_s     cn68xxp1;
+	struct cvmx_fpa_quex_page_index_s     cnf71xx;
 };
 typedef union cvmx_fpa_quex_page_index cvmx_fpa_quex_page_index_t;
 
 /**
+ * cvmx_fpa_que8_page_index
+ *
+ * FPA_QUE8_PAGE_INDEX = FPA's Queue7 Page Index
+ *
+ * The present index page for queue 7 of the FPA.
+ * This number reflects the number of pages of pointers that have been written to memory
+ * for this queue.
+ * Because the address space is 38-bits the number of 128 byte pages could cause this register value to wrap.
+ */
+union cvmx_fpa_que8_page_index {
+	uint64_t u64;
+	struct cvmx_fpa_que8_page_index_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_25_63               : 39;
+	uint64_t pg_num                       : 25; /**< Page number. */
+#else
+	uint64_t pg_num                       : 25;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_fpa_que8_page_index_s     cn68xx;
+	struct cvmx_fpa_que8_page_index_s     cn68xxp1;
+};
+typedef union cvmx_fpa_que8_page_index cvmx_fpa_que8_page_index_t;
+
+/**
  * cvmx_fpa_que_act
  *
  * FPA_QUE_ACT = FPA's Queue# Actual Page Index
@@ -1256,12 +2475,10 @@ typedef union cvmx_fpa_quex_page_index cvmx_fpa_quex_page_index_t;
  * When a INT_SUM[PERR#] occurs this will be latched with the value read from L2C. PASS-2 register.
  * This is latched on the first error and will not latch again unitl all errors are cleared.
  */
-union cvmx_fpa_que_act
-{
+union cvmx_fpa_que_act {
 	uint64_t u64;
-	struct cvmx_fpa_que_act_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_fpa_que_act_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t act_que                      : 3;  /**< FPA-queue-number read from memory. */
 	uint64_t act_indx                     : 26; /**< Page number read from memory. */
@@ -1282,8 +2499,13 @@ union cvmx_fpa_que_act
 	struct cvmx_fpa_que_act_s             cn56xxp1;
 	struct cvmx_fpa_que_act_s             cn58xx;
 	struct cvmx_fpa_que_act_s             cn58xxp1;
+	struct cvmx_fpa_que_act_s             cn61xx;
 	struct cvmx_fpa_que_act_s             cn63xx;
 	struct cvmx_fpa_que_act_s             cn63xxp1;
+	struct cvmx_fpa_que_act_s             cn66xx;
+	struct cvmx_fpa_que_act_s             cn68xx;
+	struct cvmx_fpa_que_act_s             cn68xxp1;
+	struct cvmx_fpa_que_act_s             cnf71xx;
 };
 typedef union cvmx_fpa_que_act cvmx_fpa_que_act_t;
 
@@ -1295,12 +2517,10 @@ typedef union cvmx_fpa_que_act cvmx_fpa_que_act_t;
  * When a INT_SUM[PERR#] occurs this will be latched with the expected value. PASS-2 register.
  * This is latched on the first error and will not latch again unitl all errors are cleared.
  */
-union cvmx_fpa_que_exp
-{
+union cvmx_fpa_que_exp {
 	uint64_t u64;
-	struct cvmx_fpa_que_exp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_fpa_que_exp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t exp_que                      : 3;  /**< Expected fpa-queue-number read from memory. */
 	uint64_t exp_indx                     : 26; /**< Expected page number read from memory. */
@@ -1321,8 +2541,13 @@ union cvmx_fpa_que_exp
 	struct cvmx_fpa_que_exp_s             cn56xxp1;
 	struct cvmx_fpa_que_exp_s             cn58xx;
 	struct cvmx_fpa_que_exp_s             cn58xxp1;
+	struct cvmx_fpa_que_exp_s             cn61xx;
 	struct cvmx_fpa_que_exp_s             cn63xx;
 	struct cvmx_fpa_que_exp_s             cn63xxp1;
+	struct cvmx_fpa_que_exp_s             cn66xx;
+	struct cvmx_fpa_que_exp_s             cn68xx;
+	struct cvmx_fpa_que_exp_s             cn68xxp1;
+	struct cvmx_fpa_que_exp_s             cnf71xx;
 };
 typedef union cvmx_fpa_que_exp cvmx_fpa_que_exp_t;
 
@@ -1333,12 +2558,10 @@ typedef union cvmx_fpa_que_exp cvmx_fpa_que_exp_t;
  *
  * Control and status for the WART block.
  */
-union cvmx_fpa_wart_ctl
-{
+union cvmx_fpa_wart_ctl {
 	uint64_t u64;
-	struct cvmx_fpa_wart_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_fpa_wart_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t ctl                          : 16; /**< Control information. */
 #else
@@ -1367,12 +2590,10 @@ typedef union cvmx_fpa_wart_ctl cvmx_fpa_wart_ctl_t;
  *
  * Control and status for the WART block.
  */
-union cvmx_fpa_wart_status
-{
+union cvmx_fpa_wart_status {
 	uint64_t u64;
-	struct cvmx_fpa_wart_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_fpa_wart_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t status                       : 32; /**< Status information. */
 #else
@@ -1403,12 +2624,10 @@ typedef union cvmx_fpa_wart_status cvmx_fpa_wart_status_t;
  * register a low pool count signal is sent to the PCIe packet instruction engine (to make it stop reading instructions) and to the
  * Packet-Arbiter informing it to not give grants to packets MAC with the exception of the PCIe MAC.
  */
-union cvmx_fpa_wqe_threshold
-{
+union cvmx_fpa_wqe_threshold {
 	uint64_t u64;
-	struct cvmx_fpa_wqe_threshold_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_fpa_wqe_threshold_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t thresh                       : 32; /**< WQE Threshold. */
 #else
@@ -1416,7 +2635,12 @@ union cvmx_fpa_wqe_threshold
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_fpa_wqe_threshold_s       cn61xx;
 	struct cvmx_fpa_wqe_threshold_s       cn63xx;
+	struct cvmx_fpa_wqe_threshold_s       cn66xx;
+	struct cvmx_fpa_wqe_threshold_s       cn68xx;
+	struct cvmx_fpa_wqe_threshold_s       cn68xxp1;
+	struct cvmx_fpa_wqe_threshold_s       cnf71xx;
 };
 typedef union cvmx_fpa_wqe_threshold cvmx_fpa_wqe_threshold_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-fpa.c b/sys/contrib/octeon-sdk/cvmx-fpa.c
index 22afc79..544c305 100644
--- a/sys/contrib/octeon-sdk/cvmx-fpa.c
+++ b/sys/contrib/octeon-sdk/cvmx-fpa.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -43,7 +43,7 @@
  *
  * Support library for the hardware Free Pool Allocator.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-fpa.h b/sys/contrib/octeon-sdk/cvmx-fpa.h
index b9671a8..45210a1 100644
--- a/sys/contrib/octeon-sdk/cvmx-fpa.h
+++ b/sys/contrib/octeon-sdk/cvmx-fpa.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -43,7 +43,7 @@
  *
  * Interface to the hardware Free Pool Allocator.
  *
- * <hr>$Revision: 50048 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
@@ -145,7 +145,12 @@ static inline void cvmx_fpa_enable(void)
     status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);
     if (status.s.enb)
     {
-        cvmx_dprintf("Warning: Enabling FPA when FPA already enabled.\n");
+	/*
+	 * CN68XXP1 should not reset the FPA (doing so may break the
+	 * SSO, so we may end up enabling it more than once.  Just
+	 * return and don't spew messages.
+	 */
+	return;
     }
 
     status.u64 = 0;
@@ -154,13 +159,13 @@ static inline void cvmx_fpa_enable(void)
 }
 
 /**
- * Reset FPA to disable. Make sure buffers from all FPA pools are freed
+ * Reset FPA to disable. Make sure buffers from all FPA pools are freed 
  * before disabling FPA.
  */
 static inline void cvmx_fpa_disable(void)
 {
     cvmx_fpa_ctl_status_t status;
-    
+
     status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);
     status.s.reset = 1;
     cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64);
@@ -204,7 +209,7 @@ static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool)
 {
    cvmx_fpa_iobdma_data_t data;
 
-   /* Hardware only uses 64 bit alligned locations, so convert from byte address
+   /* Hardware only uses 64 bit aligned locations, so convert from byte address
    ** to 64-bit index
    */
    data.s.scraddr = scr_addr >> 3;
diff --git a/sys/contrib/octeon-sdk/cvmx-gmx.h b/sys/contrib/octeon-sdk/cvmx-gmx.h
index e9ad751..a9e9a81 100644
--- a/sys/contrib/octeon-sdk/cvmx-gmx.h
+++ b/sys/contrib/octeon-sdk/cvmx-gmx.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Interface to the GMX hardware.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_GMX_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-gmxx-defs.h b/sys/contrib/octeon-sdk/cvmx-gmxx-defs.h
index e7e5cea..e409db8 100644
--- a/sys/contrib/octeon-sdk/cvmx-gmxx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-gmxx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,336 +49,702 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_GMXX_TYPEDEFS_H__
-#define __CVMX_GMXX_TYPEDEFS_H__
+#ifndef __CVMX_GMXX_DEFS_H__
+#define __CVMX_GMXX_DEFS_H__
 
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_BAD_REG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_BAD_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_BAD_REG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_BAD_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_BIST(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_BIST(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_BIST (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_BIST(block_id) (CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_GMXX_CLK_EN(unsigned long block_id)
+static inline uint64_t CVMX_GMXX_BPID_MAPX(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_CLK_EN(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + ((block_id) & 1) * 0x8000000ull;
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 15)) && ((block_id <= 4))))))
+		cvmx_warn("CVMX_GMXX_BPID_MAPX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 15) + ((block_id) & 7) * 0x200000ull) * 8;
 }
 #else
-#define CVMX_GMXX_CLK_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800080007F0ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_GMXX_BPID_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 15) + ((block_id) & 7) * 0x200000ull) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id)
+static inline uint64_t CVMX_GMXX_BPID_MSK(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_HG2_CONTROL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000550ull) + ((block_id) & 1) * 0x8000000ull;
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 4)))))
+		cvmx_warn("CVMX_GMXX_BPID_MSK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000700ull) + ((block_id) & 7) * 0x1000000ull;
 }
 #else
-#define CVMX_GMXX_HG2_CONTROL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000550ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_GMXX_BPID_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000700ull) + ((block_id) & 7) * 0x1000000ull)
 #endif
+static inline uint64_t CVMX_GMXX_CLK_EN(unsigned long block_id)
+{
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_CLK_EN (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + ((block_id) & 0) * 0x8000000ull;
+}
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id)
+static inline uint64_t CVMX_GMXX_EBP_DIS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_INF_MODE(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + ((block_id) & 1) * 0x8000000ull;
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 4)))))
+		cvmx_warn("CVMX_GMXX_EBP_DIS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000608ull) + ((block_id) & 7) * 0x1000000ull;
 }
 #else
-#define CVMX_GMXX_INF_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800080007F8ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_GMXX_EBP_DIS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000608ull) + ((block_id) & 7) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_GMXX_NXA_ADR(unsigned long block_id)
+static inline uint64_t CVMX_GMXX_EBP_MSK(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_NXA_ADR(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000510ull) + ((block_id) & 1) * 0x8000000ull;
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 4)))))
+		cvmx_warn("CVMX_GMXX_EBP_MSK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000600ull) + ((block_id) & 7) * 0x1000000ull;
 }
 #else
-#define CVMX_GMXX_NXA_ADR(block_id) (CVMX_ADD_IO_SEG(0x0001180008000510ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_GMXX_EBP_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + ((block_id) & 7) * 0x1000000ull)
 #endif
+static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id)
+{
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000550ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000550ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000550ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_HG2_CONTROL (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000550ull) + ((block_id) & 0) * 0x8000000ull;
+}
+static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id)
+{
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_INF_MODE (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + ((block_id) & 0) * 0x8000000ull;
+}
+static inline uint64_t CVMX_GMXX_NXA_ADR(unsigned long block_id)
+{
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000510ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000510ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000510ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_NXA_ADR (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000510ull) + ((block_id) & 0) * 0x8000000ull;
+}
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset, unsigned long block_id)
+static inline uint64_t CVMX_GMXX_PIPE_STATUS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset == 0)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset == 0)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset == 0)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_PRTX_CBFC_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((block_id) & 1) * 0x8000000ull;
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 4)))))
+		cvmx_warn("CVMX_GMXX_PIPE_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000760ull) + ((block_id) & 7) * 0x1000000ull;
 }
 #else
-#define CVMX_GMXX_PRTX_CBFC_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_GMXX_PIPE_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000760ull) + ((block_id) & 7) * 0x1000000ull)
 #endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset, unsigned long block_id)
+{
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if (((offset == 0)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset == 0)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset == 0)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_PRTX_CBFC_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((block_id) & 0) * 0x8000000ull;
+}
 static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_PRTX_CFG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_PRTX_CFG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_PRTX_CFG(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id)
+static inline uint64_t CVMX_GMXX_RXAUI_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_ADR_CAM0(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 4)))))
+		cvmx_warn("CVMX_GMXX_RXAUI_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000740ull) + ((block_id) & 7) * 0x1000000ull;
 }
 #else
-#define CVMX_GMXX_RXX_ADR_CAM0(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#define CVMX_GMXX_RXAUI_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000740ull) + ((block_id) & 7) * 0x1000000ull)
 #endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id)
+{
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_ADR_CAM0 (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+}
 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_ADR_CAM1(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_ADR_CAM1 (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_ADR_CAM1(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_ADR_CAM2(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_ADR_CAM2 (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_ADR_CAM2(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_ADR_CAM3(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_ADR_CAM3 (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_ADR_CAM3(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_ADR_CAM4(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_ADR_CAM4 (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_ADR_CAM4(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_ADR_CAM5(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_ADR_CAM5 (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+}
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_ALL_EN(unsigned long offset, unsigned long block_id)
+{
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000110ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000110ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000110ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_ADR_CAM_ALL_EN (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000110ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_ADR_CAM5(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_ADR_CAM_EN(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_ADR_CAM_EN (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_ADR_CAM_EN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_ADR_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_ADR_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_ADR_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_DECISION(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_DECISION(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_DECISION (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_DECISION(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_FRM_CHK(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_FRM_CHK(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_FRM_CHK (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_FRM_CHK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_FRM_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_FRM_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_FRM_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_FRM_MAX(unsigned long offset, unsigned long block_id)
 {
@@ -407,93 +773,188 @@ static inline uint64_t CVMX_GMXX_RXX_FRM_MIN(unsigned long offset, unsigned long
 #else
 #define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
 #endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_IFG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_IFG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_IFG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_IFG(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_INT_EN(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_INT_EN (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_INT_EN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_INT_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_INT_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_INT_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_JABBER(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_JABBER (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_JABBER(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_PAUSE_DROP_TIME(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_PAUSE_DROP_TIME (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_PAUSE_DROP_TIME(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_RX_INBND(unsigned long offset, unsigned long block_id)
 {
@@ -509,271 +970,547 @@ static inline uint64_t CVMX_GMXX_RXX_RX_INBND(unsigned long offset, unsigned lon
 #else
 #define CVMX_GMXX_RXX_RX_INBND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
 #endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_STATS_CTL(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_STATS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_STATS_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_STATS_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_STATS_OCTS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_STATS_OCTS_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DMAC(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DMAC (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_STATS_OCTS_DMAC(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DRP(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DRP (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_STATS_OCTS_DRP(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_STATS_PKTS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_BAD(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_BAD (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_STATS_PKTS_BAD(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_STATS_PKTS_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DMAC(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DMAC (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_STATS_PKTS_DMAC(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DRP(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DRP (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_STATS_PKTS_DRP(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RXX_UDD_SKP(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RXX_UDD_SKP(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RXX_UDD_SKP (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_RXX_UDD_SKP(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RX_BP_DROPX(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RX_BP_DROPX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 7) * 0x200000ull) * 8;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RX_BP_DROPX (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8;
 }
-#else
-#define CVMX_GMXX_RX_BP_DROPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RX_BP_OFFX(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RX_BP_OFFX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 7) * 0x200000ull) * 8;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RX_BP_OFFX (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8;
 }
-#else
-#define CVMX_GMXX_RX_BP_OFFX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RX_BP_ONX(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_RX_BP_ONX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 7) * 0x200000ull) * 8;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RX_BP_ONX (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8;
 }
-#else
-#define CVMX_GMXX_RX_BP_ONX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RX_HG2_STATUS(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_RX_HG2_STATUS(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000548ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000548ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000548ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000548ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RX_HG2_STATUS (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000548ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_RX_HG2_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000548ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RX_PASS_EN(unsigned long block_id)
 {
@@ -798,42 +1535,62 @@ static inline uint64_t CVMX_GMXX_RX_PASS_MAPX(unsigned long offset, unsigned lon
 #else
 #define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + (((offset) & 15) + ((block_id) & 1) * 0x1000000ull) * 8)
 #endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_RX_PRTS(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000410ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000410ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000410ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000410ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RX_PRTS (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000410ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_RX_PRTS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000410ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RX_PRT_INFO(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_RX_PRT_INFO(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RX_PRT_INFO (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_RX_PRT_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800080004E8ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RX_TX_STATUS(unsigned long block_id)
 {
@@ -847,141 +1604,276 @@ static inline uint64_t CVMX_GMXX_RX_TX_STATUS(unsigned long block_id)
 #else
 #define CVMX_GMXX_RX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800080007E8ull))
 #endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_RX_XAUI_BAD_COL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000538ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000538ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000538ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000538ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RX_XAUI_BAD_COL (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000538ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_RX_XAUI_BAD_COL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000538ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_RX_XAUI_CTL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000530ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000530ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000530ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000530ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_RX_XAUI_CTL (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000530ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_RX_XAUI_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000530ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_SMACX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_SMACX (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_SMACX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_SOFT_BIST(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_SOFT_BIST(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080007E8ull);
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_SOFT_BIST (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + ((block_id) & 7) * 0x1000000ull;
 }
-#else
-#define CVMX_GMXX_SOFT_BIST(block_id) (CVMX_ADD_IO_SEG(0x00011800080007E8ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_STAT_BP(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_STAT_BP(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000520ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000520ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000520ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000520ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_STAT_BP (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000520ull) + ((block_id) & 0) * 0x8000000ull;
+}
+static inline uint64_t CVMX_GMXX_TB_REG(unsigned long block_id)
+{
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TB_REG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_STAT_BP(block_id) (CVMX_ADD_IO_SEG(0x0001180008000520ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_APPEND(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_APPEND(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_APPEND (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_APPEND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_BURST(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_BURST (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_BURST(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_CBFC_XOFF(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset == 0)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset == 0)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset == 0)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_CBFC_XOFF(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if (((offset == 0)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset == 0)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset == 0)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_CBFC_XOFF (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_TXX_CBFC_XOFF(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_CBFC_XON(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset == 0)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset == 0)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset == 0)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_CBFC_XON(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if (((offset == 0)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset == 0)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset == 0)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_CBFC_XON (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_TXX_CBFC_XON(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_CLK(unsigned long offset, unsigned long block_id)
 {
@@ -997,397 +1889,811 @@ static inline uint64_t CVMX_GMXX_TXX_CLK(unsigned long offset, unsigned long blo
 #else
 #define CVMX_GMXX_TXX_CLK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
 #endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_MIN_PKT(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_MIN_PKT(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_MIN_PKT (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_MIN_PKT(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_TIME(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_TIME (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_PAUSE_PKT_TIME(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_PAUSE_TOGO(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_PAUSE_TOGO (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_PAUSE_TOGO(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_PAUSE_ZERO(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_PAUSE_ZERO (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_PAUSE_ZERO(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id)
+static inline uint64_t CVMX_GMXX_TXX_PIPE(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_SGMII_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 3)) && ((block_id <= 4))))))
+		cvmx_warn("CVMX_GMXX_TXX_PIPE(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000310ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
 }
 #else
-#define CVMX_GMXX_TXX_SGMII_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#define CVMX_GMXX_TXX_PIPE(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000310ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048)
 #endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id)
+{
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_SGMII_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+}
 static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_SLOT(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_SLOT (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_SLOT(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_SOFT_PAUSE(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_SOFT_PAUSE (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_SOFT_PAUSE(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_STAT0(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_STAT0(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_STAT0 (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_STAT0(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_STAT1(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_STAT1(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_STAT1 (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_STAT1(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_STAT2(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_STAT2(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_STAT2 (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_STAT2(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_STAT3(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_STAT3(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_STAT3 (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_STAT3(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_STAT4(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_STAT4(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_STAT4 (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_STAT4(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_STAT5(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_STAT5(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_STAT5 (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_STAT5(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_STAT6(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_STAT6(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_STAT6 (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_STAT6(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_STAT7(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_STAT7(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_STAT7 (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_STAT7(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_STAT8(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_STAT8(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_STAT8 (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_STAT8(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_STAT9(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_STAT9(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_STAT9 (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_STAT9(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_STATS_CTL(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_STATS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_STATS_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_STATS_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_GMXX_TXX_THRESH(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+			break;
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 2)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TXX_THRESH (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
 }
-#else
-#define CVMX_GMXX_TXX_THRESH(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TX_BP(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_TX_BP(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TX_BP (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_TX_BP(block_id) (CVMX_ADD_IO_SEG(0x00011800080004D0ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TX_CLK_MSKX(unsigned long offset, unsigned long block_id)
 {
@@ -1400,230 +2706,360 @@ static inline uint64_t CVMX_GMXX_TX_CLK_MSKX(unsigned long offset, unsigned long
 #else
 #define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000780ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
 #endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TX_COL_ATTEMPT(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_TX_COL_ATTEMPT(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000498ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000498ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000498ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000498ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TX_COL_ATTEMPT (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000498ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_TX_COL_ATTEMPT(block_id) (CVMX_ADD_IO_SEG(0x0001180008000498ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TX_CORRUPT(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_TX_CORRUPT(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TX_CORRUPT (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_TX_CORRUPT(block_id) (CVMX_ADD_IO_SEG(0x00011800080004D8ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TX_HG2_REG1(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_TX_HG2_REG1(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000558ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000558ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000558ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000558ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TX_HG2_REG1 (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000558ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_TX_HG2_REG1(block_id) (CVMX_ADD_IO_SEG(0x0001180008000558ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TX_HG2_REG2(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_TX_HG2_REG2(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000560ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000560ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000560ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000560ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TX_HG2_REG2 (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000560ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_TX_HG2_REG2(block_id) (CVMX_ADD_IO_SEG(0x0001180008000560ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TX_IFG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_TX_IFG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000488ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000488ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000488ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000488ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TX_IFG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000488ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_TX_IFG(block_id) (CVMX_ADD_IO_SEG(0x0001180008000488ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_TX_INT_EN(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000508ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000508ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000508ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000508ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TX_INT_EN (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000508ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_TX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x0001180008000508ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_TX_INT_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000500ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000500ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000500ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000500ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TX_INT_REG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000500ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_TX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180008000500ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TX_JAM(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_TX_JAM(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000490ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000490ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000490ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000490ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TX_JAM (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000490ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_TX_JAM(block_id) (CVMX_ADD_IO_SEG(0x0001180008000490ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TX_LFSR(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_TX_LFSR(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TX_LFSR (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_TX_LFSR(block_id) (CVMX_ADD_IO_SEG(0x00011800080004F8ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_TX_OVR_BP(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TX_OVR_BP (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_TX_OVR_BP(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C8ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_TX_PAUSE_PKT_DMAC(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TX_PAUSE_PKT_DMAC (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_TX_PAUSE_PKT_DMAC(block_id) (CVMX_ADD_IO_SEG(0x00011800080004A0ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_TX_PAUSE_PKT_TYPE(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TX_PAUSE_PKT_TYPE (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_TX_PAUSE_PKT_TYPE(block_id) (CVMX_ADD_IO_SEG(0x00011800080004A8ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_TX_PRTS(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000480ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000480ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000480ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000480ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TX_PRTS (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000480ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_TX_PRTS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000480ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TX_SPI_CTL(unsigned long block_id)
 {
@@ -1683,32 +3119,52 @@ static inline uint64_t CVMX_GMXX_TX_SPI_THRESH(unsigned long block_id)
 #else
 #define CVMX_GMXX_TX_SPI_THRESH(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull)
 #endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_TX_XAUI_CTL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000528ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000528ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000528ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000528ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_TX_XAUI_CTL (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000528ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_TX_XAUI_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000528ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_GMXX_XAUI_EXT_LOOPBACK(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180008000540ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180008000540ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180008000540ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x0001180008000540ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_GMXX_XAUI_EXT_LOOPBACK (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000540ull) + ((block_id) & 0) * 0x8000000ull;
 }
-#else
-#define CVMX_GMXX_XAUI_EXT_LOOPBACK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000540ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
 
 /**
  * cvmx_gmx#_bad_reg
@@ -1720,12 +3176,10 @@ static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id)
  * In XAUI mode, only the lsb (corresponding to port0) of INB_NXA, LOSTSTAT, OUT_OVR, are used.
  *
  */
-union cvmx_gmxx_bad_reg
-{
+union cvmx_gmxx_bad_reg {
 	uint64_t u64;
-	struct cvmx_gmxx_bad_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_bad_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t inb_nxa                      : 4;  /**< Inbound port > GMX_RX_PRTS */
 	uint64_t statovr                      : 1;  /**< TX Statistics overflow
@@ -1750,9 +3204,8 @@ union cvmx_gmxx_bad_reg
 	uint64_t reserved_31_63               : 33;
 #endif
 	} s;
-	struct cvmx_gmxx_bad_reg_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_bad_reg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t inb_nxa                      : 4;  /**< Inbound port > GMX_RX_PRTS */
 	uint64_t statovr                      : 1;  /**< TX Statistics overflow */
@@ -1777,9 +3230,8 @@ union cvmx_gmxx_bad_reg
 	struct cvmx_gmxx_bad_reg_s            cn38xx;
 	struct cvmx_gmxx_bad_reg_s            cn38xxp2;
 	struct cvmx_gmxx_bad_reg_cn30xx       cn50xx;
-	struct cvmx_gmxx_bad_reg_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_bad_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t inb_nxa                      : 4;  /**< Inbound port > GMX_RX_PRTS */
 	uint64_t statovr                      : 1;  /**< TX Statistics overflow
@@ -1807,8 +3259,13 @@ union cvmx_gmxx_bad_reg
 	struct cvmx_gmxx_bad_reg_cn52xx       cn56xxp1;
 	struct cvmx_gmxx_bad_reg_s            cn58xx;
 	struct cvmx_gmxx_bad_reg_s            cn58xxp1;
+	struct cvmx_gmxx_bad_reg_cn52xx       cn61xx;
 	struct cvmx_gmxx_bad_reg_cn52xx       cn63xx;
 	struct cvmx_gmxx_bad_reg_cn52xx       cn63xxp1;
+	struct cvmx_gmxx_bad_reg_cn52xx       cn66xx;
+	struct cvmx_gmxx_bad_reg_cn52xx       cn68xx;
+	struct cvmx_gmxx_bad_reg_cn52xx       cn68xxp1;
+	struct cvmx_gmxx_bad_reg_cn52xx       cnf71xx;
 };
 typedef union cvmx_gmxx_bad_reg cvmx_gmxx_bad_reg_t;
 
@@ -1818,12 +3275,10 @@ typedef union cvmx_gmxx_bad_reg cvmx_gmxx_bad_reg_t;
  * GMX_BIST = GMX BIST Results
  *
  */
-union cvmx_gmxx_bist
-{
+union cvmx_gmxx_bist {
 	uint64_t u64;
-	struct cvmx_gmxx_bist_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_bist_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_25_63               : 39;
 	uint64_t status                       : 25; /**< BIST Results.
                                                          HW sets a bit in BIST for for memory that fails
@@ -1857,9 +3312,8 @@ union cvmx_gmxx_bist
 	uint64_t reserved_25_63               : 39;
 #endif
 	} s;
-	struct cvmx_gmxx_bist_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_bist_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t status                       : 10; /**< BIST Results.
                                                           HW sets a bit in BIST for for memory that fails
@@ -1881,9 +3335,8 @@ union cvmx_gmxx_bist
 	struct cvmx_gmxx_bist_cn30xx          cn31xx;
 	struct cvmx_gmxx_bist_cn30xx          cn38xx;
 	struct cvmx_gmxx_bist_cn30xx          cn38xxp2;
-	struct cvmx_gmxx_bist_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_bist_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t status                       : 12; /**< BIST Results.
                                                          HW sets a bit in BIST for for memory that fails */
@@ -1892,9 +3345,8 @@ union cvmx_gmxx_bist
 	uint64_t reserved_12_63               : 52;
 #endif
 	} cn50xx;
-	struct cvmx_gmxx_bist_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_bist_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t status                       : 16; /**< BIST Results.
                                                          HW sets a bit in BIST for for memory that fails
@@ -1922,9 +3374,8 @@ union cvmx_gmxx_bist
 	struct cvmx_gmxx_bist_cn52xx          cn52xxp1;
 	struct cvmx_gmxx_bist_cn52xx          cn56xx;
 	struct cvmx_gmxx_bist_cn52xx          cn56xxp1;
-	struct cvmx_gmxx_bist_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_bist_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t status                       : 17; /**< BIST Results.
                                                          HW sets a bit in BIST for for memory that fails
@@ -1951,23 +3402,142 @@ union cvmx_gmxx_bist
 #endif
 	} cn58xx;
 	struct cvmx_gmxx_bist_cn58xx          cn58xxp1;
+	struct cvmx_gmxx_bist_s               cn61xx;
 	struct cvmx_gmxx_bist_s               cn63xx;
 	struct cvmx_gmxx_bist_s               cn63xxp1;
+	struct cvmx_gmxx_bist_s               cn66xx;
+	struct cvmx_gmxx_bist_s               cn68xx;
+	struct cvmx_gmxx_bist_s               cn68xxp1;
+	struct cvmx_gmxx_bist_s               cnf71xx;
 };
 typedef union cvmx_gmxx_bist cvmx_gmxx_bist_t;
 
 /**
+ * cvmx_gmx#_bpid_map#
+ *
+ * Notes:
+ * GMX will build BPID_VECTOR<15:0> using the 16 GMX_BPID_MAP entries and the BPID
+ * state from IPD.  In XAUI/RXAUI mode when PFC/CBFC/HiGig2 is used, the
+ * BPID_VECTOR becomes the logical backpressure.  In XAUI/RXAUI mode when
+ * PFC/CBFC/HiGig2 is not used or when in 4xSGMII mode, the BPID_VECTOR can be used
+ * with the GMX_BPID_MSK register to determine the physical backpressure.
+ *
+ * In XAUI/RXAUI mode, the entire BPID_VECTOR<15:0> is available determining physical
+ * backpressure for the single XAUI/RXAUI interface.
+ *
+ * In SGMII mode, BPID_VECTOR is broken up as follows:
+ *    SGMII interface0 uses BPID_VECTOR<3:0>
+ *    SGMII interface1 uses BPID_VECTOR<7:4>
+ *    SGMII interface2 uses BPID_VECTOR<11:8>
+ *    SGMII interface3 uses BPID_VECTOR<15:12>
+ *
+ * In all SGMII configurations, and in some XAUI/RXAUI configurations, the
+ * interface protocols only support physical backpressure. In these cases, a single
+ * BPID will commonly drive the physical backpressure for the physical
+ * interface. We provide example programmings for these simple cases.
+ *
+ * In XAUI/RXAUI mode where PFC/CBFC/HiGig2 is not used, an example programming
+ * would be as follows:
+ *
+ *    @verbatim
+ *    GMX_BPID_MAP0[VAL]    = 1;
+ *    GMX_BPID_MAP0[BPID]   = xaui_bpid;
+ *    GMX_BPID_MSK[MSK_OR]  = 1;
+ *    GMX_BPID_MSK[MSK_AND] = 0;
+ *    @endverbatim
+ *
+ * In SGMII mode, an example programming would be as follows:
+ *
+ *    @verbatim
+ *    for (i=0; i<4; i++) [
+ *       if (GMX_PRTi_CFG[EN]) [
+ *          GMX_BPID_MAP(i*4)[VAL]    = 1;
+ *          GMX_BPID_MAP(i*4)[BPID]   = sgmii_bpid(i);
+ *          GMX_BPID_MSK[MSK_OR]      = (1 << (i*4)) | GMX_BPID_MSK[MSK_OR];
+ *       ]
+ *    ]
+ *    GMX_BPID_MSK[MSK_AND] = 0;
+ *    @endverbatim
+ */
+union cvmx_gmxx_bpid_mapx {
+	uint64_t u64;
+	struct cvmx_gmxx_bpid_mapx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_17_63               : 47;
+	uint64_t status                       : 1;  /**< Current received BP from IPD */
+	uint64_t reserved_9_15                : 7;
+	uint64_t val                          : 1;  /**< Table entry is valid */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t bpid                         : 6;  /**< Backpressure ID the entry maps to */
+#else
+	uint64_t bpid                         : 6;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t val                          : 1;
+	uint64_t reserved_9_15                : 7;
+	uint64_t status                       : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_gmxx_bpid_mapx_s          cn68xx;
+	struct cvmx_gmxx_bpid_mapx_s          cn68xxp1;
+};
+typedef union cvmx_gmxx_bpid_mapx cvmx_gmxx_bpid_mapx_t;
+
+/**
+ * cvmx_gmx#_bpid_msk
+ */
+union cvmx_gmxx_bpid_msk {
+	uint64_t u64;
+	struct cvmx_gmxx_bpid_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_48_63               : 16;
+	uint64_t msk_or                       : 16; /**< Assert physical BP when the backpressure ID vector
+                                                         combined with MSK_OR indicates BP as follows.
+                                                         phys_bp_msk_or =
+                                                          (BPID_VECTOR<x:y> & MSK_OR<x:y>) != 0
+                                                         phys_bp = phys_bp_msk_or || phys_bp_msk_and
+                                                         In XAUI/RXAUI mode, x=15, y=0
+                                                         In SGMII mode, x/y are set depending on the SGMII
+                                                         interface.
+                                                         SGMII interface0, x=3,  y=0
+                                                         SGMII interface1, x=7,  y=4
+                                                         SGMII interface2, x=11, y=8
+                                                         SGMII interface3, x=15, y=12 */
+	uint64_t reserved_16_31               : 16;
+	uint64_t msk_and                      : 16; /**< Assert physical BP when the backpressure ID vector
+                                                         combined with MSK_AND indicates BP as follows.
+                                                         phys_bp_msk_and =
+                                                          (BPID_VECTOR<x:y> & MSK_AND<x:y>) == MSK_AND<x:y>
+                                                         phys_bp = phys_bp_msk_or || phys_bp_msk_and
+                                                         In XAUI/RXAUI mode, x=15, y=0
+                                                         In SGMII mode, x/y are set depending on the SGMII
+                                                         interface.
+                                                         SGMII interface0, x=3,  y=0
+                                                         SGMII interface1, x=7,  y=4
+                                                         SGMII interface2, x=11, y=8
+                                                         SGMII interface3, x=15, y=12 */
+#else
+	uint64_t msk_and                      : 16;
+	uint64_t reserved_16_31               : 16;
+	uint64_t msk_or                       : 16;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_gmxx_bpid_msk_s           cn68xx;
+	struct cvmx_gmxx_bpid_msk_s           cn68xxp1;
+};
+typedef union cvmx_gmxx_bpid_msk cvmx_gmxx_bpid_msk_t;
+
+/**
  * cvmx_gmx#_clk_en
  *
- * DO NOT DOCUMENT THIS REGISTER - IT IS NOT OFFICIAL
+ * DON'T PUT IN HRM*
  *
  */
-union cvmx_gmxx_clk_en
-{
+union cvmx_gmxx_clk_en {
 	uint64_t u64;
-	struct cvmx_gmxx_clk_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_clk_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t clk_en                       : 1;  /**< Force the clock enables on */
 #else
@@ -1979,12 +3549,62 @@ union cvmx_gmxx_clk_en
 	struct cvmx_gmxx_clk_en_s             cn52xxp1;
 	struct cvmx_gmxx_clk_en_s             cn56xx;
 	struct cvmx_gmxx_clk_en_s             cn56xxp1;
+	struct cvmx_gmxx_clk_en_s             cn61xx;
 	struct cvmx_gmxx_clk_en_s             cn63xx;
 	struct cvmx_gmxx_clk_en_s             cn63xxp1;
+	struct cvmx_gmxx_clk_en_s             cn66xx;
+	struct cvmx_gmxx_clk_en_s             cn68xx;
+	struct cvmx_gmxx_clk_en_s             cn68xxp1;
+	struct cvmx_gmxx_clk_en_s             cnf71xx;
 };
 typedef union cvmx_gmxx_clk_en cvmx_gmxx_clk_en_t;
 
 /**
+ * cvmx_gmx#_ebp_dis
+ */
+union cvmx_gmxx_ebp_dis {
+	uint64_t u64;
+	struct cvmx_gmxx_ebp_dis_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t dis                          : 16; /**< BP channel disable
+                                                         GMX has the ability to remap unused channels
+                                                         in order to get down to GMX_TX_PIPE[NUMP]
+                                                         channels. */
+#else
+	uint64_t dis                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_ebp_dis_s            cn68xx;
+	struct cvmx_gmxx_ebp_dis_s            cn68xxp1;
+};
+typedef union cvmx_gmxx_ebp_dis cvmx_gmxx_ebp_dis_t;
+
+/**
+ * cvmx_gmx#_ebp_msk
+ */
+union cvmx_gmxx_ebp_msk {
+	uint64_t u64;
+	struct cvmx_gmxx_ebp_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t msk                          : 16; /**< BP channel mask
+                                                         GMX can completely ignore the channel BP for
+                                                         channels specified by the MSK field.  Any channel
+                                                         in which MSK == 1, will never send BP information
+                                                         to PKO. */
+#else
+	uint64_t msk                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_ebp_msk_s            cn68xx;
+	struct cvmx_gmxx_ebp_msk_s            cn68xxp1;
+};
+typedef union cvmx_gmxx_ebp_msk cvmx_gmxx_ebp_msk_t;
+
+/**
  * cvmx_gmx#_hg2_control
  *
  * Notes:
@@ -2007,12 +3627,10 @@ typedef union cvmx_gmxx_clk_en cvmx_gmxx_clk_en_t;
  * and GMX*_RX0_UDD_SKP[LEN]=16.) The HW can only auto-generate backpressure via HiGig2 messages
  * (optionally, when HG2TX_EN=1) with the HiGig2 protocol.
  */
-union cvmx_gmxx_hg2_control
-{
+union cvmx_gmxx_hg2_control {
 	uint64_t u64;
-	struct cvmx_gmxx_hg2_control_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_hg2_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t hg2tx_en                     : 1;  /**< Enable Transmission of HG2 phys and logl messages
                                                          When set, also disables HW auto-generated (802.3
@@ -2038,8 +3656,13 @@ union cvmx_gmxx_hg2_control
 	struct cvmx_gmxx_hg2_control_s        cn52xx;
 	struct cvmx_gmxx_hg2_control_s        cn52xxp1;
 	struct cvmx_gmxx_hg2_control_s        cn56xx;
+	struct cvmx_gmxx_hg2_control_s        cn61xx;
 	struct cvmx_gmxx_hg2_control_s        cn63xx;
 	struct cvmx_gmxx_hg2_control_s        cn63xxp1;
+	struct cvmx_gmxx_hg2_control_s        cn66xx;
+	struct cvmx_gmxx_hg2_control_s        cn68xx;
+	struct cvmx_gmxx_hg2_control_s        cn68xxp1;
+	struct cvmx_gmxx_hg2_control_s        cnf71xx;
 };
 typedef union cvmx_gmxx_hg2_control cvmx_gmxx_hg2_control_t;
 
@@ -2049,16 +3672,41 @@ typedef union cvmx_gmxx_hg2_control cvmx_gmxx_hg2_control_t;
  * GMX_INF_MODE = Interface Mode
  *
  */
-union cvmx_gmxx_inf_mode
-{
+union cvmx_gmxx_inf_mode {
 	uint64_t u64;
-	struct cvmx_gmxx_inf_mode_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_12_63               : 52;
-	uint64_t speed                        : 4;  /**< Interface Speed */
-	uint64_t reserved_6_7                 : 2;
-	uint64_t mode                         : 2;  /**< Interface Electrical Operating Mode
+	struct cvmx_gmxx_inf_mode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t rate                         : 4;  /**< SERDES speed rate
+                                                         reset value is based on the QLM speed select
+                                                         0 = 1.25  Gbaud
+                                                         1 = 3.125 Gbaud
+                                                         (only valid for GMX0 instance)
+                                                         Software must not change RATE from its reset value */
+	uint64_t reserved_12_15               : 4;
+	uint64_t speed                        : 4;  /**< Interface Speed
+                                                         QLM speed pins  which select reference clock
+                                                         period and interface data rate.  If the QLM PLL
+                                                         inputs are correct, the speed setting correspond
+                                                         to the following data rates (in Gbaud).
+                                                         0  = 5
+                                                         1  = 2.5
+                                                         2  = 2.5
+                                                         3  = 1.25
+                                                         4  = 1.25
+                                                         5  = 6.25
+                                                         6  = 5
+                                                         7  = 2.5
+                                                         8  = 3.125
+                                                         9  = 2.5
+                                                         10 = 1.25
+                                                         11 = 5
+                                                         12 = 6.25
+                                                         13 = 3.75
+                                                         14 = 3.125
+                                                         15 = QLM disabled */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t mode                         : 3;  /**< Interface Electrical Operating Mode
                                                          - 0: SGMII (v1.8)
                                                          - 1: XAUI (IEEE 802.3-2005) */
 	uint64_t reserved_3_3                 : 1;
@@ -2078,15 +3726,16 @@ union cvmx_gmxx_inf_mode
 	uint64_t en                           : 1;
 	uint64_t p0mii                        : 1;
 	uint64_t reserved_3_3                 : 1;
-	uint64_t mode                         : 2;
-	uint64_t reserved_6_7                 : 2;
+	uint64_t mode                         : 3;
+	uint64_t reserved_7_7                 : 1;
 	uint64_t speed                        : 4;
-	uint64_t reserved_12_63               : 52;
+	uint64_t reserved_12_15               : 4;
+	uint64_t rate                         : 4;
+	uint64_t reserved_20_63               : 44;
 #endif
 	} s;
-	struct cvmx_gmxx_inf_mode_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_inf_mode_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t p0mii                        : 1;  /**< Port 0 Interface Mode
                                                          - 0: Port 0 is RGMII
@@ -2107,9 +3756,8 @@ union cvmx_gmxx_inf_mode
 	uint64_t reserved_3_63                : 61;
 #endif
 	} cn30xx;
-	struct cvmx_gmxx_inf_mode_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_inf_mode_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t en                           : 1;  /**< Interface Enable
                                                          Must be set to enable the packet interface.
@@ -2128,9 +3776,8 @@ union cvmx_gmxx_inf_mode
 	struct cvmx_gmxx_inf_mode_cn31xx      cn38xx;
 	struct cvmx_gmxx_inf_mode_cn31xx      cn38xxp2;
 	struct cvmx_gmxx_inf_mode_cn30xx      cn50xx;
-	struct cvmx_gmxx_inf_mode_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_inf_mode_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t speed                        : 2;  /**< Interface Speed
                                                          - 0: 1.250GHz
@@ -2167,11 +3814,30 @@ union cvmx_gmxx_inf_mode
 	struct cvmx_gmxx_inf_mode_cn52xx      cn56xxp1;
 	struct cvmx_gmxx_inf_mode_cn31xx      cn58xx;
 	struct cvmx_gmxx_inf_mode_cn31xx      cn58xxp1;
-	struct cvmx_gmxx_inf_mode_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_inf_mode_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
-	uint64_t speed                        : 4;  /**< Interface Speed */
+	uint64_t speed                        : 4;  /**< Interface Speed
+                                                         QLM speed pins  which select reference clock
+                                                         period and interface data rate.  If the QLM PLL
+                                                         inputs are correct, the speed setting correspond
+                                                         to the following data rates (in Gbaud).
+                                                         0  = 5
+                                                         1  = 2.5
+                                                         2  = 2.5
+                                                         3  = 1.25
+                                                         4  = 1.25
+                                                         5  = 6.25
+                                                         6  = 5
+                                                         7  = 2.5
+                                                         8  = 3.125
+                                                         9  = 2.5
+                                                         10 = 1.25
+                                                         11 = 5
+                                                         12 = 6.25
+                                                         13 = 3.75
+                                                         14 = 3.125
+                                                         15 = QLM disabled */
 	uint64_t reserved_5_7                 : 3;
 	uint64_t mode                         : 1;  /**< Interface Electrical Operating Mode
                                                          - 0: SGMII (v1.8)
@@ -2194,8 +3860,120 @@ union cvmx_gmxx_inf_mode
 	uint64_t speed                        : 4;
 	uint64_t reserved_12_63               : 52;
 #endif
-	} cn63xx;
-	struct cvmx_gmxx_inf_mode_cn63xx      cn63xxp1;
+	} cn61xx;
+	struct cvmx_gmxx_inf_mode_cn61xx      cn63xx;
+	struct cvmx_gmxx_inf_mode_cn61xx      cn63xxp1;
+	struct cvmx_gmxx_inf_mode_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t rate                         : 4;  /**< SERDES speed rate
+                                                         reset value is based on the QLM speed select
+                                                         0 = 1.25  Gbaud
+                                                         1 = 3.125 Gbaud
+                                                         (only valid for GMX0 instance)
+                                                         Software must not change RATE from its reset value */
+	uint64_t reserved_12_15               : 4;
+	uint64_t speed                        : 4;  /**< Interface Speed
+                                                         QLM speed pins  which select reference clock
+                                                         period and interface data rate.  If the QLM PLL
+                                                         inputs are correct, the speed setting correspond
+                                                         to the following data rates (in Gbaud).
+                                                         0  = 5
+                                                         1  = 2.5
+                                                         2  = 2.5
+                                                         3  = 1.25
+                                                         4  = 1.25
+                                                         5  = 6.25
+                                                         6  = 5
+                                                         7  = 2.5
+                                                         8  = 3.125
+                                                         9  = 2.5
+                                                         10 = 1.25
+                                                         11 = 5
+                                                         12 = 6.25
+                                                         13 = 3.75
+                                                         14 = 3.125
+                                                         15 = QLM disabled */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t mode                         : 1;  /**< Interface Electrical Operating Mode
+                                                         - 0: SGMII (v1.8)
+                                                         - 1: XAUI (IEEE 802.3-2005) */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t en                           : 1;  /**< Interface Enable
+                                                         Must be set to enable the packet interface.
+                                                         Should be enabled before any other requests to
+                                                         GMX including enabling port back pressure with
+                                                         IPD_CTL_STATUS[PBP_EN] */
+	uint64_t type                         : 1;  /**< Interface Protocol Type
+                                                         - 0: SGMII/1000Base-X
+                                                         - 1: XAUI */
+#else
+	uint64_t type                         : 1;
+	uint64_t en                           : 1;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t mode                         : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t speed                        : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t rate                         : 4;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn66xx;
+	struct cvmx_gmxx_inf_mode_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_12_63               : 52;
+	uint64_t speed                        : 4;  /**< Interface Speed
+                                                         QLM speed pins  which select reference clock
+                                                         period and interface data rate.  If the QLM PLL
+                                                         inputs are correct, the speed setting correspond
+                                                         to the following data rates (in Gbaud).
+                                                         0  = 5
+                                                         1  = 2.5
+                                                         2  = 2.5
+                                                         3  = 1.25
+                                                         4  = 1.25
+                                                         5  = 6.25
+                                                         6  = 5
+                                                         7  = 2.5
+                                                         8  = 3.125
+                                                         9  = 2.5
+                                                         10 = 1.25
+                                                         11 = 5
+                                                         12 = 6.25
+                                                         13 = 3.75
+                                                         14 = 3.125
+                                                         15 = QLM disabled */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t mode                         : 3;  /**< Interface Electrical Operating Mode
+                                                         - 0: Reserved
+                                                         - 1: Reserved
+                                                         - 2: SGMII (v1.8)
+                                                         - 3: XAUI (IEEE 802.3-2005)
+                                                         - 4: Reserved
+                                                         - 5: Reserved
+                                                         - 6: Reserved
+                                                         - 7: RXAUI */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t en                           : 1;  /**< Interface Enable
+                                                                   Must be set to enable the packet interface.
+                                                                   Should be enabled before any other requests to
+                                                                   GMX including enabling port back pressure with
+                                                         b         IPD_CTL_STATUS[PBP_EN] */
+	uint64_t type                         : 1;  /**< Interface Protocol Type
+                                                         - 0: SGMII/1000Base-X
+                                                         - 1: XAUI/RXAUI */
+#else
+	uint64_t type                         : 1;
+	uint64_t en                           : 1;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t mode                         : 3;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t speed                        : 4;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn68xx;
+	struct cvmx_gmxx_inf_mode_cn68xx      cn68xxp1;
+	struct cvmx_gmxx_inf_mode_cn61xx      cnf71xx;
 };
 typedef union cvmx_gmxx_inf_mode cvmx_gmxx_inf_mode_t;
 
@@ -2205,13 +3983,13 @@ typedef union cvmx_gmxx_inf_mode cvmx_gmxx_inf_mode_t;
  * GMX_NXA_ADR = NXA Port Address
  *
  */
-union cvmx_gmxx_nxa_adr
-{
+union cvmx_gmxx_nxa_adr {
 	uint64_t u64;
-	struct cvmx_gmxx_nxa_adr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_6_63                : 58;
+	struct cvmx_gmxx_nxa_adr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_23_63               : 41;
+	uint64_t pipe                         : 7;  /**< Logged pipe for NXP exceptions */
+	uint64_t reserved_6_15                : 10;
 	uint64_t prt                          : 6;  /**< Logged address for NXA exceptions
                                                          The logged address will be from the first
                                                          exception that caused the problem.  NCB has
@@ -2219,26 +3997,76 @@ union cvmx_gmxx_nxa_adr
                                                          (only PRT[3:0]) */
 #else
 	uint64_t prt                          : 6;
-	uint64_t reserved_6_63                : 58;
+	uint64_t reserved_6_15                : 10;
+	uint64_t pipe                         : 7;
+	uint64_t reserved_23_63               : 41;
 #endif
 	} s;
-	struct cvmx_gmxx_nxa_adr_s            cn30xx;
-	struct cvmx_gmxx_nxa_adr_s            cn31xx;
-	struct cvmx_gmxx_nxa_adr_s            cn38xx;
-	struct cvmx_gmxx_nxa_adr_s            cn38xxp2;
-	struct cvmx_gmxx_nxa_adr_s            cn50xx;
-	struct cvmx_gmxx_nxa_adr_s            cn52xx;
-	struct cvmx_gmxx_nxa_adr_s            cn52xxp1;
-	struct cvmx_gmxx_nxa_adr_s            cn56xx;
-	struct cvmx_gmxx_nxa_adr_s            cn56xxp1;
-	struct cvmx_gmxx_nxa_adr_s            cn58xx;
-	struct cvmx_gmxx_nxa_adr_s            cn58xxp1;
-	struct cvmx_gmxx_nxa_adr_s            cn63xx;
-	struct cvmx_gmxx_nxa_adr_s            cn63xxp1;
+	struct cvmx_gmxx_nxa_adr_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_6_63                : 58;
+	uint64_t prt                          : 6;  /**< Logged address for NXA exceptions
+                                                         The logged address will be from the first
+                                                         exception that caused the problem.  NCB has
+                                                         higher priority than PKO and will win. */
+#else
+	uint64_t prt                          : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} cn30xx;
+	struct cvmx_gmxx_nxa_adr_cn30xx       cn31xx;
+	struct cvmx_gmxx_nxa_adr_cn30xx       cn38xx;
+	struct cvmx_gmxx_nxa_adr_cn30xx       cn38xxp2;
+	struct cvmx_gmxx_nxa_adr_cn30xx       cn50xx;
+	struct cvmx_gmxx_nxa_adr_cn30xx       cn52xx;
+	struct cvmx_gmxx_nxa_adr_cn30xx       cn52xxp1;
+	struct cvmx_gmxx_nxa_adr_cn30xx       cn56xx;
+	struct cvmx_gmxx_nxa_adr_cn30xx       cn56xxp1;
+	struct cvmx_gmxx_nxa_adr_cn30xx       cn58xx;
+	struct cvmx_gmxx_nxa_adr_cn30xx       cn58xxp1;
+	struct cvmx_gmxx_nxa_adr_cn30xx       cn61xx;
+	struct cvmx_gmxx_nxa_adr_cn30xx       cn63xx;
+	struct cvmx_gmxx_nxa_adr_cn30xx       cn63xxp1;
+	struct cvmx_gmxx_nxa_adr_cn30xx       cn66xx;
+	struct cvmx_gmxx_nxa_adr_s            cn68xx;
+	struct cvmx_gmxx_nxa_adr_s            cn68xxp1;
+	struct cvmx_gmxx_nxa_adr_cn30xx       cnf71xx;
 };
 typedef union cvmx_gmxx_nxa_adr cvmx_gmxx_nxa_adr_t;
 
 /**
+ * cvmx_gmx#_pipe_status
+ *
+ * DON'T PUT IN HRM*
+ *
+ */
+union cvmx_gmxx_pipe_status {
+	uint64_t u64;
+	struct cvmx_gmxx_pipe_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t ovr                          : 4;  /**< Pipe credit return FIFO has overflowed. */
+	uint64_t reserved_12_15               : 4;
+	uint64_t bp                           : 4;  /**< Pipe credit return FIFO has filled up and asserted
+                                                         backpressure to the datapath. */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t stop                         : 4;  /**< PKO has asserted backpressure on the pipe credit
+                                                         return interface. */
+#else
+	uint64_t stop                         : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t bp                           : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t ovr                          : 4;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_gmxx_pipe_status_s        cn68xx;
+	struct cvmx_gmxx_pipe_status_s        cn68xxp1;
+};
+typedef union cvmx_gmxx_pipe_status cvmx_gmxx_pipe_status_t;
+
+/**
  * cvmx_gmx#_prt#_cbfc_ctl
  *
  * ** HG2 message CSRs end
@@ -2248,12 +4076,10 @@ typedef union cvmx_gmxx_nxa_adr cvmx_gmxx_nxa_adr_t;
  * XOFF for a specific port is XOFF<prt> = (PHYS_EN<prt> & PHYS_BP) | (LOGL_EN<prt> & LOGL_BP<prt>)
  *
  */
-union cvmx_gmxx_prtx_cbfc_ctl
-{
+union cvmx_gmxx_prtx_cbfc_ctl {
 	uint64_t u64;
-	struct cvmx_gmxx_prtx_cbfc_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_prtx_cbfc_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t phys_en                      : 16; /**< Determines which ports will have physical
                                                          backpressure pause packets.
                                                          The value pplaced in the Class Enable Vector
@@ -2294,8 +4120,13 @@ union cvmx_gmxx_prtx_cbfc_ctl
 	} s;
 	struct cvmx_gmxx_prtx_cbfc_ctl_s      cn52xx;
 	struct cvmx_gmxx_prtx_cbfc_ctl_s      cn56xx;
+	struct cvmx_gmxx_prtx_cbfc_ctl_s      cn61xx;
 	struct cvmx_gmxx_prtx_cbfc_ctl_s      cn63xx;
 	struct cvmx_gmxx_prtx_cbfc_ctl_s      cn63xxp1;
+	struct cvmx_gmxx_prtx_cbfc_ctl_s      cn66xx;
+	struct cvmx_gmxx_prtx_cbfc_ctl_s      cn68xx;
+	struct cvmx_gmxx_prtx_cbfc_ctl_s      cn68xxp1;
+	struct cvmx_gmxx_prtx_cbfc_ctl_s      cnf71xx;
 };
 typedef union cvmx_gmxx_prtx_cbfc_ctl cvmx_gmxx_prtx_cbfc_ctl_t;
 
@@ -2305,13 +4136,13 @@ typedef union cvmx_gmxx_prtx_cbfc_ctl cvmx_gmxx_prtx_cbfc_ctl_t;
  * GMX_PRT_CFG = Port description
  *
  */
-union cvmx_gmxx_prtx_cfg
-{
+union cvmx_gmxx_prtx_cfg {
 	uint64_t u64;
-	struct cvmx_gmxx_prtx_cfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_14_63               : 50;
+	struct cvmx_gmxx_prtx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_22_63               : 42;
+	uint64_t pknd                         : 6;  /**< Port Kind used for processing the packet by PKI */
+	uint64_t reserved_14_15               : 2;
 	uint64_t tx_idle                      : 1;  /**< TX Machine is idle */
 	uint64_t rx_idle                      : 1;  /**< RX Machine is idle */
 	uint64_t reserved_9_11                : 3;
@@ -2354,12 +4185,13 @@ union cvmx_gmxx_prtx_cfg
 	uint64_t reserved_9_11                : 3;
 	uint64_t rx_idle                      : 1;
 	uint64_t tx_idle                      : 1;
-	uint64_t reserved_14_63               : 50;
+	uint64_t reserved_14_15               : 2;
+	uint64_t pknd                         : 6;
+	uint64_t reserved_22_63               : 42;
 #endif
 	} s;
-	struct cvmx_gmxx_prtx_cfg_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_prtx_cfg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t slottime                     : 1;  /**< Slot Time for Half-Duplex operation
                                                          0 = 512 bitimes (10/100Mbs operation)
@@ -2392,14 +4224,66 @@ union cvmx_gmxx_prtx_cfg
 	struct cvmx_gmxx_prtx_cfg_cn30xx      cn38xx;
 	struct cvmx_gmxx_prtx_cfg_cn30xx      cn38xxp2;
 	struct cvmx_gmxx_prtx_cfg_cn30xx      cn50xx;
-	struct cvmx_gmxx_prtx_cfg_s           cn52xx;
-	struct cvmx_gmxx_prtx_cfg_s           cn52xxp1;
-	struct cvmx_gmxx_prtx_cfg_s           cn56xx;
-	struct cvmx_gmxx_prtx_cfg_s           cn56xxp1;
+	struct cvmx_gmxx_prtx_cfg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_14_63               : 50;
+	uint64_t tx_idle                      : 1;  /**< TX Machine is idle */
+	uint64_t rx_idle                      : 1;  /**< RX Machine is idle */
+	uint64_t reserved_9_11                : 3;
+	uint64_t speed_msb                    : 1;  /**< Link Speed MSB [SPEED_MSB:SPEED]
+                                                         10 = 10Mbs operation
+                                                         00 = 100Mbs operation
+                                                         01 = 1000Mbs operation
+                                                         11 = Reserved
+                                                         (SGMII/1000Base-X only) */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t slottime                     : 1;  /**< Slot Time for Half-Duplex operation
+                                                         0 = 512 bitimes (10/100Mbs operation)
+                                                         1 = 4096 bitimes (1000Mbs operation)
+                                                         (SGMII/1000Base-X only) */
+	uint64_t duplex                       : 1;  /**< Duplex
+                                                         0 = Half Duplex (collisions/extentions/bursts)
+                                                         1 = Full Duplex
+                                                         (SGMII/1000Base-X only) */
+	uint64_t speed                        : 1;  /**< Link Speed LSB [SPEED_MSB:SPEED]
+                                                         10 = 10Mbs operation
+                                                         00 = 100Mbs operation
+                                                         01 = 1000Mbs operation
+                                                         11 = Reserved
+                                                         (SGMII/1000Base-X only) */
+	uint64_t en                           : 1;  /**< Link Enable
+                                                         When EN is clear, packets will not be received
+                                                         or transmitted (including PAUSE and JAM packets).
+                                                         If EN is cleared while a packet is currently
+                                                         being received or transmitted, the packet will
+                                                         be allowed to complete before the bus is idled.
+                                                         On the RX side, subsequent packets in a burst
+                                                         will be ignored. */
+#else
+	uint64_t en                           : 1;
+	uint64_t speed                        : 1;
+	uint64_t duplex                       : 1;
+	uint64_t slottime                     : 1;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t speed_msb                    : 1;
+	uint64_t reserved_9_11                : 3;
+	uint64_t rx_idle                      : 1;
+	uint64_t tx_idle                      : 1;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} cn52xx;
+	struct cvmx_gmxx_prtx_cfg_cn52xx      cn52xxp1;
+	struct cvmx_gmxx_prtx_cfg_cn52xx      cn56xx;
+	struct cvmx_gmxx_prtx_cfg_cn52xx      cn56xxp1;
 	struct cvmx_gmxx_prtx_cfg_cn30xx      cn58xx;
 	struct cvmx_gmxx_prtx_cfg_cn30xx      cn58xxp1;
-	struct cvmx_gmxx_prtx_cfg_s           cn63xx;
-	struct cvmx_gmxx_prtx_cfg_s           cn63xxp1;
+	struct cvmx_gmxx_prtx_cfg_cn52xx      cn61xx;
+	struct cvmx_gmxx_prtx_cfg_cn52xx      cn63xx;
+	struct cvmx_gmxx_prtx_cfg_cn52xx      cn63xxp1;
+	struct cvmx_gmxx_prtx_cfg_cn52xx      cn66xx;
+	struct cvmx_gmxx_prtx_cfg_s           cn68xx;
+	struct cvmx_gmxx_prtx_cfg_s           cn68xxp1;
+	struct cvmx_gmxx_prtx_cfg_cn52xx      cnf71xx;
 };
 typedef union cvmx_gmxx_prtx_cfg cvmx_gmxx_prtx_cfg_t;
 
@@ -2409,20 +4293,22 @@ typedef union cvmx_gmxx_prtx_cfg cvmx_gmxx_prtx_cfg_t;
  * GMX_RX_ADR_CAM = Address Filtering Control
  *
  */
-union cvmx_gmxx_rxx_adr_cam0
-{
+union cvmx_gmxx_rxx_adr_cam0 {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_adr_cam0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_adr_cam0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t adr                          : 64; /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to GMX_RX_ADR_CAM will not
-                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
+
+                                                         Each entry contributes 8bits to one of 8 matchers.
                                                          The CAM matches against unicst or multicst DMAC
                                                          addresses.
-                                                         In XAUI mode, all ports will reflect the data
-                                                         written to port0. */
+
+                                                         ALL GMX_RX[0..3]_ADR_CAM[0..5] CSRs may be used
+                                                         in either SGMII or XAUI mode such that any GMX
+                                                         MAC can use any of the 32 common DMAC entries.
+
+                                                         GMX_RX[1..3]_ADR_CAM[0..5] are the only non-port0
+                                                         registers used in XAUI mode. */
 #else
 	uint64_t adr                          : 64;
 #endif
@@ -2438,8 +4324,13 @@ union cvmx_gmxx_rxx_adr_cam0
 	struct cvmx_gmxx_rxx_adr_cam0_s       cn56xxp1;
 	struct cvmx_gmxx_rxx_adr_cam0_s       cn58xx;
 	struct cvmx_gmxx_rxx_adr_cam0_s       cn58xxp1;
+	struct cvmx_gmxx_rxx_adr_cam0_s       cn61xx;
 	struct cvmx_gmxx_rxx_adr_cam0_s       cn63xx;
 	struct cvmx_gmxx_rxx_adr_cam0_s       cn63xxp1;
+	struct cvmx_gmxx_rxx_adr_cam0_s       cn66xx;
+	struct cvmx_gmxx_rxx_adr_cam0_s       cn68xx;
+	struct cvmx_gmxx_rxx_adr_cam0_s       cn68xxp1;
+	struct cvmx_gmxx_rxx_adr_cam0_s       cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_adr_cam0 cvmx_gmxx_rxx_adr_cam0_t;
 
@@ -2449,20 +4340,22 @@ typedef union cvmx_gmxx_rxx_adr_cam0 cvmx_gmxx_rxx_adr_cam0_t;
  * GMX_RX_ADR_CAM = Address Filtering Control
  *
  */
-union cvmx_gmxx_rxx_adr_cam1
-{
+union cvmx_gmxx_rxx_adr_cam1 {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_adr_cam1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_adr_cam1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t adr                          : 64; /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to GMX_RX_ADR_CAM will not
-                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
+
+                                                         Each entry contributes 8bits to one of 8 matchers.
                                                          The CAM matches against unicst or multicst DMAC
                                                          addresses.
-                                                         In XAUI mode, all ports will reflect the data
-                                                         written to port0. */
+
+                                                         ALL GMX_RX[0..3]_ADR_CAM[0..5] CSRs may be used
+                                                         in either SGMII or XAUI mode such that any GMX
+                                                         MAC can use any of the 32 common DMAC entries.
+
+                                                         GMX_RX[1..3]_ADR_CAM[0..5] are the only non-port0
+                                                         registers used in XAUI mode. */
 #else
 	uint64_t adr                          : 64;
 #endif
@@ -2478,8 +4371,13 @@ union cvmx_gmxx_rxx_adr_cam1
 	struct cvmx_gmxx_rxx_adr_cam1_s       cn56xxp1;
 	struct cvmx_gmxx_rxx_adr_cam1_s       cn58xx;
 	struct cvmx_gmxx_rxx_adr_cam1_s       cn58xxp1;
+	struct cvmx_gmxx_rxx_adr_cam1_s       cn61xx;
 	struct cvmx_gmxx_rxx_adr_cam1_s       cn63xx;
 	struct cvmx_gmxx_rxx_adr_cam1_s       cn63xxp1;
+	struct cvmx_gmxx_rxx_adr_cam1_s       cn66xx;
+	struct cvmx_gmxx_rxx_adr_cam1_s       cn68xx;
+	struct cvmx_gmxx_rxx_adr_cam1_s       cn68xxp1;
+	struct cvmx_gmxx_rxx_adr_cam1_s       cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_adr_cam1 cvmx_gmxx_rxx_adr_cam1_t;
 
@@ -2489,20 +4387,22 @@ typedef union cvmx_gmxx_rxx_adr_cam1 cvmx_gmxx_rxx_adr_cam1_t;
  * GMX_RX_ADR_CAM = Address Filtering Control
  *
  */
-union cvmx_gmxx_rxx_adr_cam2
-{
+union cvmx_gmxx_rxx_adr_cam2 {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_adr_cam2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_adr_cam2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t adr                          : 64; /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to GMX_RX_ADR_CAM will not
-                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
+
+                                                         Each entry contributes 8bits to one of 8 matchers.
                                                          The CAM matches against unicst or multicst DMAC
                                                          addresses.
-                                                         In XAUI mode, all ports will reflect the data
-                                                         written to port0. */
+
+                                                         ALL GMX_RX[0..3]_ADR_CAM[0..5] CSRs may be used
+                                                         in either SGMII or XAUI mode such that any GMX
+                                                         MAC can use any of the 32 common DMAC entries.
+
+                                                         GMX_RX[1..3]_ADR_CAM[0..5] are the only non-port0
+                                                         registers used in XAUI mode. */
 #else
 	uint64_t adr                          : 64;
 #endif
@@ -2518,8 +4418,13 @@ union cvmx_gmxx_rxx_adr_cam2
 	struct cvmx_gmxx_rxx_adr_cam2_s       cn56xxp1;
 	struct cvmx_gmxx_rxx_adr_cam2_s       cn58xx;
 	struct cvmx_gmxx_rxx_adr_cam2_s       cn58xxp1;
+	struct cvmx_gmxx_rxx_adr_cam2_s       cn61xx;
 	struct cvmx_gmxx_rxx_adr_cam2_s       cn63xx;
 	struct cvmx_gmxx_rxx_adr_cam2_s       cn63xxp1;
+	struct cvmx_gmxx_rxx_adr_cam2_s       cn66xx;
+	struct cvmx_gmxx_rxx_adr_cam2_s       cn68xx;
+	struct cvmx_gmxx_rxx_adr_cam2_s       cn68xxp1;
+	struct cvmx_gmxx_rxx_adr_cam2_s       cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_adr_cam2 cvmx_gmxx_rxx_adr_cam2_t;
 
@@ -2529,20 +4434,22 @@ typedef union cvmx_gmxx_rxx_adr_cam2 cvmx_gmxx_rxx_adr_cam2_t;
  * GMX_RX_ADR_CAM = Address Filtering Control
  *
  */
-union cvmx_gmxx_rxx_adr_cam3
-{
+union cvmx_gmxx_rxx_adr_cam3 {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_adr_cam3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_adr_cam3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t adr                          : 64; /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to GMX_RX_ADR_CAM will not
-                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
+
+                                                         Each entry contributes 8bits to one of 8 matchers.
                                                          The CAM matches against unicst or multicst DMAC
                                                          addresses.
-                                                         In XAUI mode, all ports will reflect the data
-                                                         written to port0. */
+
+                                                         ALL GMX_RX[0..3]_ADR_CAM[0..5] CSRs may be used
+                                                         in either SGMII or XAUI mode such that any GMX
+                                                         MAC can use any of the 32 common DMAC entries.
+
+                                                         GMX_RX[1..3]_ADR_CAM[0..5] are the only non-port0
+                                                         registers used in XAUI mode. */
 #else
 	uint64_t adr                          : 64;
 #endif
@@ -2558,8 +4465,13 @@ union cvmx_gmxx_rxx_adr_cam3
 	struct cvmx_gmxx_rxx_adr_cam3_s       cn56xxp1;
 	struct cvmx_gmxx_rxx_adr_cam3_s       cn58xx;
 	struct cvmx_gmxx_rxx_adr_cam3_s       cn58xxp1;
+	struct cvmx_gmxx_rxx_adr_cam3_s       cn61xx;
 	struct cvmx_gmxx_rxx_adr_cam3_s       cn63xx;
 	struct cvmx_gmxx_rxx_adr_cam3_s       cn63xxp1;
+	struct cvmx_gmxx_rxx_adr_cam3_s       cn66xx;
+	struct cvmx_gmxx_rxx_adr_cam3_s       cn68xx;
+	struct cvmx_gmxx_rxx_adr_cam3_s       cn68xxp1;
+	struct cvmx_gmxx_rxx_adr_cam3_s       cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_adr_cam3 cvmx_gmxx_rxx_adr_cam3_t;
 
@@ -2569,20 +4481,22 @@ typedef union cvmx_gmxx_rxx_adr_cam3 cvmx_gmxx_rxx_adr_cam3_t;
  * GMX_RX_ADR_CAM = Address Filtering Control
  *
  */
-union cvmx_gmxx_rxx_adr_cam4
-{
+union cvmx_gmxx_rxx_adr_cam4 {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_adr_cam4_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_adr_cam4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t adr                          : 64; /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to GMX_RX_ADR_CAM will not
-                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
+
+                                                         Each entry contributes 8bits to one of 8 matchers.
                                                          The CAM matches against unicst or multicst DMAC
                                                          addresses.
-                                                         In XAUI mode, all ports will reflect the data
-                                                         written to port0. */
+
+                                                         ALL GMX_RX[0..3]_ADR_CAM[0..5] CSRs may be used
+                                                         in either SGMII or XAUI mode such that any GMX
+                                                         MAC can use any of the 32 common DMAC entries.
+
+                                                         GMX_RX[1..3]_ADR_CAM[0..5] are the only non-port0
+                                                         registers used in XAUI mode. */
 #else
 	uint64_t adr                          : 64;
 #endif
@@ -2598,8 +4512,13 @@ union cvmx_gmxx_rxx_adr_cam4
 	struct cvmx_gmxx_rxx_adr_cam4_s       cn56xxp1;
 	struct cvmx_gmxx_rxx_adr_cam4_s       cn58xx;
 	struct cvmx_gmxx_rxx_adr_cam4_s       cn58xxp1;
+	struct cvmx_gmxx_rxx_adr_cam4_s       cn61xx;
 	struct cvmx_gmxx_rxx_adr_cam4_s       cn63xx;
 	struct cvmx_gmxx_rxx_adr_cam4_s       cn63xxp1;
+	struct cvmx_gmxx_rxx_adr_cam4_s       cn66xx;
+	struct cvmx_gmxx_rxx_adr_cam4_s       cn68xx;
+	struct cvmx_gmxx_rxx_adr_cam4_s       cn68xxp1;
+	struct cvmx_gmxx_rxx_adr_cam4_s       cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_adr_cam4 cvmx_gmxx_rxx_adr_cam4_t;
 
@@ -2609,20 +4528,22 @@ typedef union cvmx_gmxx_rxx_adr_cam4 cvmx_gmxx_rxx_adr_cam4_t;
  * GMX_RX_ADR_CAM = Address Filtering Control
  *
  */
-union cvmx_gmxx_rxx_adr_cam5
-{
+union cvmx_gmxx_rxx_adr_cam5 {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_adr_cam5_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_adr_cam5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t adr                          : 64; /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to GMX_RX_ADR_CAM will not
-                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
+
+                                                         Each entry contributes 8bits to one of 8 matchers.
                                                          The CAM matches against unicst or multicst DMAC
                                                          addresses.
-                                                         In XAUI mode, all ports will reflect the data
-                                                         written to port0. */
+
+                                                         ALL GMX_RX[0..3]_ADR_CAM[0..5] CSRs may be used
+                                                         in either SGMII or XAUI mode such that any GMX
+                                                         MAC can use any of the 32 common DMAC entries.
+
+                                                         GMX_RX[1..3]_ADR_CAM[0..5] are the only non-port0
+                                                         registers used in XAUI mode. */
 #else
 	uint64_t adr                          : 64;
 #endif
@@ -2638,25 +4559,114 @@ union cvmx_gmxx_rxx_adr_cam5
 	struct cvmx_gmxx_rxx_adr_cam5_s       cn56xxp1;
 	struct cvmx_gmxx_rxx_adr_cam5_s       cn58xx;
 	struct cvmx_gmxx_rxx_adr_cam5_s       cn58xxp1;
+	struct cvmx_gmxx_rxx_adr_cam5_s       cn61xx;
 	struct cvmx_gmxx_rxx_adr_cam5_s       cn63xx;
 	struct cvmx_gmxx_rxx_adr_cam5_s       cn63xxp1;
+	struct cvmx_gmxx_rxx_adr_cam5_s       cn66xx;
+	struct cvmx_gmxx_rxx_adr_cam5_s       cn68xx;
+	struct cvmx_gmxx_rxx_adr_cam5_s       cn68xxp1;
+	struct cvmx_gmxx_rxx_adr_cam5_s       cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_adr_cam5 cvmx_gmxx_rxx_adr_cam5_t;
 
 /**
+ * cvmx_gmx#_rx#_adr_cam_all_en
+ *
+ * GMX_RX_ADR_CAM_ALL_EN = Address Filtering Control Enable
+ *
+ */
+union cvmx_gmxx_rxx_adr_cam_all_en {
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_adr_cam_all_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t en                           : 32; /**< CAM Entry Enables
+
+                                                         GMX has 32 DMAC entries that can be accessed with
+                                                         the GMX_RX[0..3]_ADR_CAM[0..5] CSRs.
+                                                         These 32 DMAC entries can be used by any of the
+                                                         four SGMII MACs or the XAUI MAC.
+
+                                                         Each port interface has independent control of
+                                                         which of the 32 DMAC entries to include in the
+                                                         CAM lookup.
+
+                                                         GMX_RXx_ADR_CAM_ALL_EN was not present in legacy
+                                                         GMX implemenations which had only eight DMAC CAM
+                                                         entries. New applications may choose to ignore
+                                                         GMX_RXx_ADR_CAM_EN using GMX_RX_ADR_CAM_ALL_EN
+                                                         instead.
+
+                                                         EN represents the full 32 indepedent per MAC
+                                                         enables.
+
+                                                         Writes to EN will be reflected in
+                                                         GMX_RXx_ADR_CAM_EN[EN] and writes to
+                                                         GMX_RXx_ADR_CAM_EN[EN] will be reflected in EN.
+                                                         Refer to GMX_RXx_ADR_CAM_EN for the CSR mapping.
+
+                                                         In XAUI mode, only GMX_RX0_ADR_CAM_ALL_EN is used
+                                                         and GMX_RX[1,2,3]_ADR_CAM_ALL_EN should not be
+                                                         used. */
+#else
+	uint64_t en                           : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_adr_cam_all_en_s cn61xx;
+	struct cvmx_gmxx_rxx_adr_cam_all_en_s cn66xx;
+	struct cvmx_gmxx_rxx_adr_cam_all_en_s cn68xx;
+	struct cvmx_gmxx_rxx_adr_cam_all_en_s cnf71xx;
+};
+typedef union cvmx_gmxx_rxx_adr_cam_all_en cvmx_gmxx_rxx_adr_cam_all_en_t;
+
+/**
  * cvmx_gmx#_rx#_adr_cam_en
  *
  * GMX_RX_ADR_CAM_EN = Address Filtering Control Enable
  *
  */
-union cvmx_gmxx_rxx_adr_cam_en
-{
+union cvmx_gmxx_rxx_adr_cam_en {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_adr_cam_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_adr_cam_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
-	uint64_t en                           : 8;  /**< CAM Entry Enables */
+	uint64_t en                           : 8;  /**< CAM Entry Enables
+
+                                                         GMX has 32 DMAC entries that can be accessed with
+                                                         the GMX_RX[0..3]_ADR_CAM[0..5] CSRs.
+                                                         These 32 DMAC entries can be used by any of the
+                                                         four SGMII MACs or the XAUI MAC.
+
+                                                         Each port interface has independent control of
+                                                         which of the 32 DMAC entries to include in the
+                                                         CAM lookup.
+
+                                                         Legacy GMX implementations were able to CAM
+                                                         against eight DMAC entries while current
+                                                         implementations use 32 common entries.
+                                                         This register is intended for legacy applications
+                                                         that only require eight DMAC CAM entries per MAC.
+                                                         New applications may choose to ignore
+                                                         GMX_RXx_ADR_CAM_EN using GMX_RXx_ADR_CAM_ALL_EN
+                                                         instead.
+
+                                                         EN controls the enables for the eight legacy CAM
+                                                         entries as follows:
+                                                          port0, EN = GMX_RX0_ADR_CAM_ALL_EN[EN<7:0>]
+                                                          port1, EN = GMX_RX1_ADR_CAM_ALL_EN[EN<15:8>]
+                                                          port2, EN = GMX_RX2_ADR_CAM_ALL_EN[EN<23:16>]
+                                                          port3, EN = GMX_RX3_ADR_CAM_ALL_EN[EN<31:24>]
+
+                                                         The full 32 indepedent per MAC enables are in
+                                                         GMX_RX_ADR_CAM_ALL_EN.
+
+                                                         Therefore, writes to GMX_RXX_ADR_CAM_ALL_EN[EN]
+                                                         will be reflected in EN and writes to EN will be
+                                                         reflected in GMX_RXX_ADR_CAM_ALL_EN[EN].
+
+                                                         In XAUI mode, only GMX_RX0_ADR_CAM_EN is used and
+                                                         GMX_RX[1,2,3]_ADR_CAM_EN should not be used. */
 #else
 	uint64_t en                           : 8;
 	uint64_t reserved_8_63                : 56;
@@ -2673,8 +4683,13 @@ union cvmx_gmxx_rxx_adr_cam_en
 	struct cvmx_gmxx_rxx_adr_cam_en_s     cn56xxp1;
 	struct cvmx_gmxx_rxx_adr_cam_en_s     cn58xx;
 	struct cvmx_gmxx_rxx_adr_cam_en_s     cn58xxp1;
+	struct cvmx_gmxx_rxx_adr_cam_en_s     cn61xx;
 	struct cvmx_gmxx_rxx_adr_cam_en_s     cn63xx;
 	struct cvmx_gmxx_rxx_adr_cam_en_s     cn63xxp1;
+	struct cvmx_gmxx_rxx_adr_cam_en_s     cn66xx;
+	struct cvmx_gmxx_rxx_adr_cam_en_s     cn68xx;
+	struct cvmx_gmxx_rxx_adr_cam_en_s     cn68xxp1;
+	struct cvmx_gmxx_rxx_adr_cam_en_s     cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_adr_cam_en cvmx_gmxx_rxx_adr_cam_en_t;
 
@@ -2686,46 +4701,48 @@ typedef union cvmx_gmxx_rxx_adr_cam_en cvmx_gmxx_rxx_adr_cam_en_t;
  *
  * Notes:
  * * ALGORITHM
- * Here is some pseudo code that represents the address filter behavior.
- *
- *    @verbatim
- *    bool dmac_addr_filter(uint8 prt, uint48 dmac) [
- *      ASSERT(prt >= 0 && prt <= 3);
- *      if (is_bcst(dmac))                               // broadcast accept
- *        return (GMX_RX[prt]_ADR_CTL[BCST] ? ACCEPT : REJECT);
- *      if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 1)   // multicast reject
- *        return REJECT;
- *      if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 2)   // multicast accept
- *        return ACCEPT;
- *
- *      cam_hit = 0;
- *
- *      for (i=0; i<8; i++) [
- *        if (GMX_RX[prt]_ADR_CAM_EN[EN<i>] == 0)
- *          continue;
- *        uint48 unswizzled_mac_adr = 0x0;
- *        for (j=5; j>=0; j--) [
- *           unswizzled_mac_adr = (unswizzled_mac_adr << 8) | GMX_RX[prt]_ADR_CAM[j][ADR<i*8+7:i*8>];
- *        ]
- *        if (unswizzled_mac_adr == dmac) [
- *          cam_hit = 1;
- *          break;
+ *   Here is some pseudo code that represents the address filter behavior.
+ *
+ *      @verbatim
+ *      bool dmac_addr_filter(uint8 prt, uint48 dmac) [
+ *        ASSERT(prt >= 0 && prt <= 3);
+ *        if (is_bcst(dmac))                               // broadcast accept
+ *          return (GMX_RX[prt]_ADR_CTL[BCST] ? ACCEPT : REJECT);
+ *        if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 1)   // multicast reject
+ *          return REJECT;
+ *        if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 2)   // multicast accept
+ *          return ACCEPT;
+ *
+ *        cam_hit = 0;
+ *
+ *        for (i=0; i<32; i++) [
+ *          if (GMX_RX[prt]_ADR_CAM_ALL_EN[EN<i>] == 0)
+ *            continue;
+ *          uint48 unswizzled_mac_adr = 0x0;
+ *          for (j=5; j>=0; j--) [
+ *             unswizzled_mac_adr = (unswizzled_mac_adr << 8) | GMX_RX[i>>3]_ADR_CAM[j][ADR<(i&7)*8+7:(i&7)*8>];
+ *          ]
+ *          if (unswizzled_mac_adr == dmac) [
+ *            cam_hit = 1;
+ *            break;
+ *          ]
  *        ]
+ *
+ *        if (cam_hit)
+ *          return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? ACCEPT : REJECT);
+ *        else
+ *          return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? REJECT : ACCEPT);
  *      ]
+ *      @endverbatim
  *
- *      if (cam_hit)
- *        return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? ACCEPT : REJECT);
- *      else
- *        return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? REJECT : ACCEPT);
- *    ]
- *    @endverbatim
+ * * XAUI Mode
+ *
+ *   In XAUI mode, only GMX_RX0_ADR_CTL is used.  GMX_RX[1,2,3]_ADR_CTL should not be used.
  */
-union cvmx_gmxx_rxx_adr_ctl
-{
+union cvmx_gmxx_rxx_adr_ctl {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_adr_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_adr_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t cam_mode                     : 1;  /**< Allow or deny DMAC address filter
                                                          0 = reject the packet on DMAC address match
@@ -2754,8 +4771,13 @@ union cvmx_gmxx_rxx_adr_ctl
 	struct cvmx_gmxx_rxx_adr_ctl_s        cn56xxp1;
 	struct cvmx_gmxx_rxx_adr_ctl_s        cn58xx;
 	struct cvmx_gmxx_rxx_adr_ctl_s        cn58xxp1;
+	struct cvmx_gmxx_rxx_adr_ctl_s        cn61xx;
 	struct cvmx_gmxx_rxx_adr_ctl_s        cn63xx;
 	struct cvmx_gmxx_rxx_adr_ctl_s        cn63xxp1;
+	struct cvmx_gmxx_rxx_adr_ctl_s        cn66xx;
+	struct cvmx_gmxx_rxx_adr_ctl_s        cn68xx;
+	struct cvmx_gmxx_rxx_adr_ctl_s        cn68xxp1;
+	struct cvmx_gmxx_rxx_adr_ctl_s        cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_adr_ctl cvmx_gmxx_rxx_adr_ctl_t;
 
@@ -2786,12 +4808,10 @@ typedef union cvmx_gmxx_rxx_adr_ctl cvmx_gmxx_rxx_adr_ctl_t;
  *
  * where l2_size = MAX(0, total_packet_size - GMX_RX_UDD_SKP[LEN] - ((GMX_RX_FRM_CTL[PRE_CHK]==1)*8)
  */
-union cvmx_gmxx_rxx_decision
-{
+union cvmx_gmxx_rxx_decision {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_decision_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_decision_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t cnt                          : 5;  /**< The byte count to decide when to accept or filter
                                                          a packet. */
@@ -2811,8 +4831,13 @@ union cvmx_gmxx_rxx_decision
 	struct cvmx_gmxx_rxx_decision_s       cn56xxp1;
 	struct cvmx_gmxx_rxx_decision_s       cn58xx;
 	struct cvmx_gmxx_rxx_decision_s       cn58xxp1;
+	struct cvmx_gmxx_rxx_decision_s       cn61xx;
 	struct cvmx_gmxx_rxx_decision_s       cn63xx;
 	struct cvmx_gmxx_rxx_decision_s       cn63xxp1;
+	struct cvmx_gmxx_rxx_decision_s       cn66xx;
+	struct cvmx_gmxx_rxx_decision_s       cn68xx;
+	struct cvmx_gmxx_rxx_decision_s       cn68xxp1;
+	struct cvmx_gmxx_rxx_decision_s       cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_decision cvmx_gmxx_rxx_decision_t;
 
@@ -2827,12 +4852,10 @@ typedef union cvmx_gmxx_rxx_decision cvmx_gmxx_rxx_decision_t;
  *
  * In XAUI mode prt0 is used for checking.
  */
-union cvmx_gmxx_rxx_frm_chk
-{
+union cvmx_gmxx_rxx_frm_chk {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_frm_chk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_frm_chk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t niberr                       : 1;  /**< Nibble error (hi_nibble != lo_nibble) */
 	uint64_t skperr                       : 1;  /**< Skipper error */
@@ -2863,9 +4886,8 @@ union cvmx_gmxx_rxx_frm_chk
 	struct cvmx_gmxx_rxx_frm_chk_s        cn31xx;
 	struct cvmx_gmxx_rxx_frm_chk_s        cn38xx;
 	struct cvmx_gmxx_rxx_frm_chk_s        cn38xxp2;
-	struct cvmx_gmxx_rxx_frm_chk_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_frm_chk_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t niberr                       : 1;  /**< Nibble error (hi_nibble != lo_nibble) */
 	uint64_t skperr                       : 1;  /**< Skipper error */
@@ -2891,9 +4913,8 @@ union cvmx_gmxx_rxx_frm_chk
 	uint64_t reserved_10_63               : 54;
 #endif
 	} cn50xx;
-	struct cvmx_gmxx_rxx_frm_chk_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_frm_chk_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t skperr                       : 1;  /**< Skipper error */
 	uint64_t rcverr                       : 1;  /**< Frame was received with Data reception error */
@@ -2921,9 +4942,8 @@ union cvmx_gmxx_rxx_frm_chk
 	struct cvmx_gmxx_rxx_frm_chk_cn52xx   cn56xxp1;
 	struct cvmx_gmxx_rxx_frm_chk_s        cn58xx;
 	struct cvmx_gmxx_rxx_frm_chk_s        cn58xxp1;
-	struct cvmx_gmxx_rxx_frm_chk_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_frm_chk_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t skperr                       : 1;  /**< Skipper error */
 	uint64_t rcverr                       : 1;  /**< Frame was received with Data reception error */
@@ -2945,8 +4965,13 @@ union cvmx_gmxx_rxx_frm_chk
 	uint64_t skperr                       : 1;
 	uint64_t reserved_9_63                : 55;
 #endif
-	} cn63xx;
-	struct cvmx_gmxx_rxx_frm_chk_cn63xx   cn63xxp1;
+	} cn61xx;
+	struct cvmx_gmxx_rxx_frm_chk_cn61xx   cn63xx;
+	struct cvmx_gmxx_rxx_frm_chk_cn61xx   cn63xxp1;
+	struct cvmx_gmxx_rxx_frm_chk_cn61xx   cn66xx;
+	struct cvmx_gmxx_rxx_frm_chk_cn61xx   cn68xx;
+	struct cvmx_gmxx_rxx_frm_chk_cn61xx   cn68xxp1;
+	struct cvmx_gmxx_rxx_frm_chk_cn61xx   cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_frm_chk cvmx_gmxx_rxx_frm_chk_t;
 
@@ -2979,12 +5004,10 @@ typedef union cvmx_gmxx_rxx_frm_chk cvmx_gmxx_rxx_frm_chk_t;
  *   would constitute an exception which should be handled by the processing
  *   cores.  PAUSE packets should not be forwarded.
  */
-union cvmx_gmxx_rxx_frm_ctl
-{
+union cvmx_gmxx_rxx_frm_ctl {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_frm_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_frm_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t ptp_mode                     : 1;  /**< Timestamp mode
                                                          When PTP_MODE is set, a 64-bit timestamp will be
@@ -3004,7 +5027,8 @@ union cvmx_gmxx_rxx_frm_ctl
                                                           PIP_PRT_CFGx[HIGIG_EN] should be 0.
                                                           PIP_FRM_CHKx[MAXLEN] should be increased by 8.
                                                           PIP_FRM_CHKx[MINLEN] should be increased by 8.
-                                                          PIP_TAG_INCx[EN] should be adjusted. */
+                                                          PIP_TAG_INCx[EN] should be adjusted.
+                                                          PIP_PRT_CFGBx[ALT_SKP_EN] should be 0. */
 	uint64_t reserved_11_11               : 1;
 	uint64_t null_dis                     : 1;  /**< When set, do not modify the MOD bits on NULL ticks
                                                          due to PARITAL packets */
@@ -3062,9 +5086,8 @@ union cvmx_gmxx_rxx_frm_ctl
 	uint64_t reserved_13_63               : 51;
 #endif
 	} s;
-	struct cvmx_gmxx_rxx_frm_ctl_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t pad_len                      : 1;  /**< When set, disables the length check for non-min
                                                          sized pkts with padding in the client data */
@@ -3096,9 +5119,8 @@ union cvmx_gmxx_rxx_frm_ctl
 	uint64_t reserved_9_63                : 55;
 #endif
 	} cn30xx;
-	struct cvmx_gmxx_rxx_frm_ctl_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t vlan_len                     : 1;  /**< When set, disables the length check for VLAN pkts */
 	uint64_t pre_free                     : 1;  /**< Allows for less strict PREAMBLE checking.
@@ -3129,9 +5151,8 @@ union cvmx_gmxx_rxx_frm_ctl
 	} cn31xx;
 	struct cvmx_gmxx_rxx_frm_ctl_cn30xx   cn38xx;
 	struct cvmx_gmxx_rxx_frm_ctl_cn31xx   cn38xxp2;
-	struct cvmx_gmxx_rxx_frm_ctl_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t null_dis                     : 1;  /**< When set, do not modify the MOD bits on NULL ticks
                                                          due to PARITAL packets */
@@ -3173,9 +5194,8 @@ union cvmx_gmxx_rxx_frm_ctl
 	struct cvmx_gmxx_rxx_frm_ctl_cn50xx   cn52xx;
 	struct cvmx_gmxx_rxx_frm_ctl_cn50xx   cn52xxp1;
 	struct cvmx_gmxx_rxx_frm_ctl_cn50xx   cn56xx;
-	struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t pre_align                    : 1;  /**< When set, PREAMBLE parser aligns the the SFD byte
                                                          regardless of the number of previous PREAMBLE
@@ -3218,9 +5238,8 @@ union cvmx_gmxx_rxx_frm_ctl
 	uint64_t reserved_10_63               : 54;
 #endif
 	} cn56xxp1;
-	struct cvmx_gmxx_rxx_frm_ctl_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_frm_ctl_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t null_dis                     : 1;  /**< When set, do not modify the MOD bits on NULL ticks
                                                          due to PARITAL packets
@@ -3265,9 +5284,8 @@ union cvmx_gmxx_rxx_frm_ctl
 #endif
 	} cn58xx;
 	struct cvmx_gmxx_rxx_frm_ctl_cn30xx   cn58xxp1;
-	struct cvmx_gmxx_rxx_frm_ctl_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_frm_ctl_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t ptp_mode                     : 1;  /**< Timestamp mode
                                                          When PTP_MODE is set, a 64-bit timestamp will be
@@ -3287,7 +5305,8 @@ union cvmx_gmxx_rxx_frm_ctl
                                                           PIP_PRT_CFGx[HIGIG_EN] should be 0.
                                                           PIP_FRM_CHKx[MAXLEN] should be increased by 8.
                                                           PIP_FRM_CHKx[MINLEN] should be increased by 8.
-                                                          PIP_TAG_INCx[EN] should be adjusted. */
+                                                          PIP_TAG_INCx[EN] should be adjusted.
+                                                          PIP_PRT_CFGBx[ALT_SKP_EN] should be 0. */
 	uint64_t reserved_11_11               : 1;
 	uint64_t null_dis                     : 1;  /**< When set, do not modify the MOD bits on NULL ticks
                                                          due to PARITAL packets */
@@ -3340,8 +5359,13 @@ union cvmx_gmxx_rxx_frm_ctl
 	uint64_t ptp_mode                     : 1;
 	uint64_t reserved_13_63               : 51;
 #endif
-	} cn63xx;
-	struct cvmx_gmxx_rxx_frm_ctl_cn63xx   cn63xxp1;
+	} cn61xx;
+	struct cvmx_gmxx_rxx_frm_ctl_cn61xx   cn63xx;
+	struct cvmx_gmxx_rxx_frm_ctl_cn61xx   cn63xxp1;
+	struct cvmx_gmxx_rxx_frm_ctl_cn61xx   cn66xx;
+	struct cvmx_gmxx_rxx_frm_ctl_cn61xx   cn68xx;
+	struct cvmx_gmxx_rxx_frm_ctl_cn61xx   cn68xxp1;
+	struct cvmx_gmxx_rxx_frm_ctl_cn61xx   cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_frm_ctl cvmx_gmxx_rxx_frm_ctl_t;
 
@@ -3359,12 +5383,10 @@ typedef union cvmx_gmxx_rxx_frm_ctl cvmx_gmxx_rxx_frm_ctl_t;
  * are within the maximum length parameter to be rejected because they exceed
  * the GMX_RX_JABBER[CNT] limit.
  */
-union cvmx_gmxx_rxx_frm_max
-{
+union cvmx_gmxx_rxx_frm_max {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_frm_max_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_frm_max_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t len                          : 16; /**< Byte count for Max-sized frame check
                                                          GMX_RXn_FRM_CHK[MAXERR] enables the check for
@@ -3398,12 +5420,10 @@ typedef union cvmx_gmxx_rxx_frm_max cvmx_gmxx_rxx_frm_max_t;
  * In spi4 mode, all spi4 ports use prt0 for checking.
  *
  */
-union cvmx_gmxx_rxx_frm_min
-{
+union cvmx_gmxx_rxx_frm_min {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_frm_min_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_frm_min_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t len                          : 16; /**< Byte count for Min-sized frame check
                                                          GMX_RXn_FRM_CHK[MINERR] enables the check for
@@ -3432,12 +5452,10 @@ typedef union cvmx_gmxx_rxx_frm_min cvmx_gmxx_rxx_frm_min_t;
  * GMX_RX_IFG = RX Min IFG
  *
  */
-union cvmx_gmxx_rxx_ifg
-{
+union cvmx_gmxx_rxx_ifg {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_ifg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_ifg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t ifg                          : 4;  /**< Min IFG (in IFG*8 bits) between packets used to
                                                          determine IFGERR. Normally IFG is 96 bits.
@@ -3463,8 +5481,13 @@ union cvmx_gmxx_rxx_ifg
 	struct cvmx_gmxx_rxx_ifg_s            cn56xxp1;
 	struct cvmx_gmxx_rxx_ifg_s            cn58xx;
 	struct cvmx_gmxx_rxx_ifg_s            cn58xxp1;
+	struct cvmx_gmxx_rxx_ifg_s            cn61xx;
 	struct cvmx_gmxx_rxx_ifg_s            cn63xx;
 	struct cvmx_gmxx_rxx_ifg_s            cn63xxp1;
+	struct cvmx_gmxx_rxx_ifg_s            cn66xx;
+	struct cvmx_gmxx_rxx_ifg_s            cn68xx;
+	struct cvmx_gmxx_rxx_ifg_s            cn68xxp1;
+	struct cvmx_gmxx_rxx_ifg_s            cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_ifg cvmx_gmxx_rxx_ifg_t;
 
@@ -3478,12 +5501,10 @@ typedef union cvmx_gmxx_rxx_ifg cvmx_gmxx_rxx_ifg_t;
  * In XAUI mode prt0 is used for checking.
  *
  */
-union cvmx_gmxx_rxx_int_en
-{
+union cvmx_gmxx_rxx_int_en {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_int_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t hg2cc                        : 1;  /**< HiGig2 CRC8 or Control char error interrupt enable */
 	uint64_t hg2fld                       : 1;  /**< HiGig2 Bad field error interrupt enable */
@@ -3562,9 +5583,8 @@ union cvmx_gmxx_rxx_int_en
 	uint64_t reserved_29_63               : 35;
 #endif
 	} s;
-	struct cvmx_gmxx_rxx_int_en_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_int_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t phy_dupx                     : 1;  /**< Change in the RMGII inbound LinkDuplex */
 	uint64_t phy_spd                      : 1;  /**< Change in the RMGII inbound LinkSpeed */
@@ -3611,9 +5631,8 @@ union cvmx_gmxx_rxx_int_en
 	struct cvmx_gmxx_rxx_int_en_cn30xx    cn31xx;
 	struct cvmx_gmxx_rxx_int_en_cn30xx    cn38xx;
 	struct cvmx_gmxx_rxx_int_en_cn30xx    cn38xxp2;
-	struct cvmx_gmxx_rxx_int_en_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_int_en_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
 	uint64_t phy_dupx                     : 1;  /**< Change in the RMGII inbound LinkDuplex */
@@ -3659,9 +5678,8 @@ union cvmx_gmxx_rxx_int_en
 	uint64_t reserved_20_63               : 44;
 #endif
 	} cn50xx;
-	struct cvmx_gmxx_rxx_int_en_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_int_en_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t hg2cc                        : 1;  /**< HiGig2 CRC8 or Control char error interrupt enable */
 	uint64_t hg2fld                       : 1;  /**< HiGig2 Bad field error interrupt enable */
@@ -3736,9 +5754,8 @@ union cvmx_gmxx_rxx_int_en
 	} cn52xx;
 	struct cvmx_gmxx_rxx_int_en_cn52xx    cn52xxp1;
 	struct cvmx_gmxx_rxx_int_en_cn52xx    cn56xx;
-	struct cvmx_gmxx_rxx_int_en_cn56xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_int_en_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_27_63               : 37;
 	uint64_t undat                        : 1;  /**< Unexpected Data
                                                          (XAUI Mode only) */
@@ -3807,9 +5824,8 @@ union cvmx_gmxx_rxx_int_en
 	uint64_t reserved_27_63               : 37;
 #endif
 	} cn56xxp1;
-	struct cvmx_gmxx_rxx_int_en_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_int_en_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
 	uint64_t phy_dupx                     : 1;  /**< Change in the RMGII inbound LinkDuplex */
@@ -3856,9 +5872,8 @@ union cvmx_gmxx_rxx_int_en
 #endif
 	} cn58xx;
 	struct cvmx_gmxx_rxx_int_en_cn58xx    cn58xxp1;
-	struct cvmx_gmxx_rxx_int_en_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_int_en_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t hg2cc                        : 1;  /**< HiGig2 CRC8 or Control char error interrupt enable */
 	uint64_t hg2fld                       : 1;  /**< HiGig2 Bad field error interrupt enable */
@@ -3930,8 +5945,13 @@ union cvmx_gmxx_rxx_int_en
 	uint64_t hg2cc                        : 1;
 	uint64_t reserved_29_63               : 35;
 #endif
-	} cn63xx;
-	struct cvmx_gmxx_rxx_int_en_cn63xx    cn63xxp1;
+	} cn61xx;
+	struct cvmx_gmxx_rxx_int_en_cn61xx    cn63xx;
+	struct cvmx_gmxx_rxx_int_en_cn61xx    cn63xxp1;
+	struct cvmx_gmxx_rxx_int_en_cn61xx    cn66xx;
+	struct cvmx_gmxx_rxx_int_en_cn61xx    cn68xx;
+	struct cvmx_gmxx_rxx_int_en_cn61xx    cn68xxp1;
+	struct cvmx_gmxx_rxx_int_en_cn61xx    cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_int_en cvmx_gmxx_rxx_int_en_t;
 
@@ -3989,7 +6009,7 @@ typedef union cvmx_gmxx_rxx_int_en cvmx_gmxx_rxx_int_en_t;
  * (B) PCTERR - checks that the frame begins with a valid PREAMBLE sequence.
  *              Does not check the number of PREAMBLE cycles.
  *
- * (C) OVRERR - Not to be included in the HRM
+ * (C) OVRERR -
  *
  *              OVRERR is an architectural assertion check internal to GMX to
  *              make sure no assumption was violated.  In a correctly operating
@@ -4006,12 +6026,10 @@ typedef union cvmx_gmxx_rxx_int_en cvmx_gmxx_rxx_int_en_t;
  *
  * (D) In XAUI mode prt0 is used for interrupt logging.
  */
-union cvmx_gmxx_rxx_int_reg
-{
+union cvmx_gmxx_rxx_int_reg {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_int_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t hg2cc                        : 1;  /**< HiGig2 received message CRC or Control char  error
                                                          Set when either CRC8 error detected or when
@@ -4111,9 +6129,8 @@ union cvmx_gmxx_rxx_int_reg
 	uint64_t reserved_29_63               : 35;
 #endif
 	} s;
-	struct cvmx_gmxx_rxx_int_reg_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_int_reg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t phy_dupx                     : 1;  /**< Change in the RMGII inbound LinkDuplex */
 	uint64_t phy_spd                      : 1;  /**< Change in the RMGII inbound LinkSpeed */
@@ -4162,9 +6179,8 @@ union cvmx_gmxx_rxx_int_reg
 	struct cvmx_gmxx_rxx_int_reg_cn30xx   cn31xx;
 	struct cvmx_gmxx_rxx_int_reg_cn30xx   cn38xx;
 	struct cvmx_gmxx_rxx_int_reg_cn30xx   cn38xxp2;
-	struct cvmx_gmxx_rxx_int_reg_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_int_reg_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
 	uint64_t phy_dupx                     : 1;  /**< Change in the RMGII inbound LinkDuplex */
@@ -4212,9 +6228,8 @@ union cvmx_gmxx_rxx_int_reg
 	uint64_t reserved_20_63               : 44;
 #endif
 	} cn50xx;
-	struct cvmx_gmxx_rxx_int_reg_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t hg2cc                        : 1;  /**< HiGig2 received message CRC or Control char  error
                                                          Set when either CRC8 error detected or when
@@ -4307,9 +6322,8 @@ union cvmx_gmxx_rxx_int_reg
 	} cn52xx;
 	struct cvmx_gmxx_rxx_int_reg_cn52xx   cn52xxp1;
 	struct cvmx_gmxx_rxx_int_reg_cn52xx   cn56xx;
-	struct cvmx_gmxx_rxx_int_reg_cn56xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_27_63               : 37;
 	uint64_t undat                        : 1;  /**< Unexpected Data
                                                          (XAUI Mode only) */
@@ -4382,9 +6396,8 @@ union cvmx_gmxx_rxx_int_reg
 	uint64_t reserved_27_63               : 37;
 #endif
 	} cn56xxp1;
-	struct cvmx_gmxx_rxx_int_reg_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_int_reg_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
 	uint64_t phy_dupx                     : 1;  /**< Change in the RMGII inbound LinkDuplex */
@@ -4433,9 +6446,8 @@ union cvmx_gmxx_rxx_int_reg
 #endif
 	} cn58xx;
 	struct cvmx_gmxx_rxx_int_reg_cn58xx   cn58xxp1;
-	struct cvmx_gmxx_rxx_int_reg_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_int_reg_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t hg2cc                        : 1;  /**< HiGig2 received message CRC or Control char  error
                                                          Set when either CRC8 error detected or when
@@ -4528,8 +6540,13 @@ union cvmx_gmxx_rxx_int_reg
 	uint64_t hg2cc                        : 1;
 	uint64_t reserved_29_63               : 35;
 #endif
-	} cn63xx;
-	struct cvmx_gmxx_rxx_int_reg_cn63xx   cn63xxp1;
+	} cn61xx;
+	struct cvmx_gmxx_rxx_int_reg_cn61xx   cn63xx;
+	struct cvmx_gmxx_rxx_int_reg_cn61xx   cn63xxp1;
+	struct cvmx_gmxx_rxx_int_reg_cn61xx   cn66xx;
+	struct cvmx_gmxx_rxx_int_reg_cn61xx   cn68xx;
+	struct cvmx_gmxx_rxx_int_reg_cn61xx   cn68xxp1;
+	struct cvmx_gmxx_rxx_int_reg_cn61xx   cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_int_reg cvmx_gmxx_rxx_int_reg_t;
 
@@ -4551,12 +6568,10 @@ typedef union cvmx_gmxx_rxx_int_reg cvmx_gmxx_rxx_int_reg_t;
  *
  * In XAUI mode prt0 is used for checking.
  */
-union cvmx_gmxx_rxx_jabber
-{
+union cvmx_gmxx_rxx_jabber {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_jabber_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_jabber_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t cnt                          : 16; /**< Byte count for jabber check
                                                          Failing packets set the JABBER interrupt and are
@@ -4578,8 +6593,13 @@ union cvmx_gmxx_rxx_jabber
 	struct cvmx_gmxx_rxx_jabber_s         cn56xxp1;
 	struct cvmx_gmxx_rxx_jabber_s         cn58xx;
 	struct cvmx_gmxx_rxx_jabber_s         cn58xxp1;
+	struct cvmx_gmxx_rxx_jabber_s         cn61xx;
 	struct cvmx_gmxx_rxx_jabber_s         cn63xx;
 	struct cvmx_gmxx_rxx_jabber_s         cn63xxp1;
+	struct cvmx_gmxx_rxx_jabber_s         cn66xx;
+	struct cvmx_gmxx_rxx_jabber_s         cn68xx;
+	struct cvmx_gmxx_rxx_jabber_s         cn68xxp1;
+	struct cvmx_gmxx_rxx_jabber_s         cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_jabber cvmx_gmxx_rxx_jabber_t;
 
@@ -4589,12 +6609,10 @@ typedef union cvmx_gmxx_rxx_jabber cvmx_gmxx_rxx_jabber_t;
  * GMX_RX_PAUSE_DROP_TIME = The TIME field in a PAUSE Packet which was dropped due to GMX RX FIFO full condition
  *
  */
-union cvmx_gmxx_rxx_pause_drop_time
-{
+union cvmx_gmxx_rxx_pause_drop_time {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_pause_drop_time_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_pause_drop_time_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t status                       : 16; /**< Time extracted from the dropped PAUSE packet */
 #else
@@ -4609,8 +6627,13 @@ union cvmx_gmxx_rxx_pause_drop_time
 	struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1;
 	struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx;
 	struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1;
+	struct cvmx_gmxx_rxx_pause_drop_time_s cn61xx;
 	struct cvmx_gmxx_rxx_pause_drop_time_s cn63xx;
 	struct cvmx_gmxx_rxx_pause_drop_time_s cn63xxp1;
+	struct cvmx_gmxx_rxx_pause_drop_time_s cn66xx;
+	struct cvmx_gmxx_rxx_pause_drop_time_s cn68xx;
+	struct cvmx_gmxx_rxx_pause_drop_time_s cn68xxp1;
+	struct cvmx_gmxx_rxx_pause_drop_time_s cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_pause_drop_time cvmx_gmxx_rxx_pause_drop_time_t;
 
@@ -4625,12 +6648,10 @@ typedef union cvmx_gmxx_rxx_pause_drop_time cvmx_gmxx_rxx_pause_drop_time_t;
  * and supports the optional in-band status (see section 3.4.1 of the RGMII
  * specification, version 1.3 for more information).
  */
-union cvmx_gmxx_rxx_rx_inbnd
-{
+union cvmx_gmxx_rxx_rx_inbnd {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_rx_inbnd_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_rx_inbnd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t duplex                       : 1;  /**< RGMII Inbound LinkDuplex
                                                          0=half-duplex
@@ -4666,12 +6687,10 @@ typedef union cvmx_gmxx_rxx_rx_inbnd cvmx_gmxx_rxx_rx_inbnd_t;
  * GMX_RX_STATS_CTL = RX Stats Control register
  *
  */
-union cvmx_gmxx_rxx_stats_ctl
-{
+union cvmx_gmxx_rxx_stats_ctl {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_stats_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_stats_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t rd_clr                       : 1;  /**< RX Stats registers will clear on reads */
 #else
@@ -4690,8 +6709,13 @@ union cvmx_gmxx_rxx_stats_ctl
 	struct cvmx_gmxx_rxx_stats_ctl_s      cn56xxp1;
 	struct cvmx_gmxx_rxx_stats_ctl_s      cn58xx;
 	struct cvmx_gmxx_rxx_stats_ctl_s      cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_ctl_s      cn61xx;
 	struct cvmx_gmxx_rxx_stats_ctl_s      cn63xx;
 	struct cvmx_gmxx_rxx_stats_ctl_s      cn63xxp1;
+	struct cvmx_gmxx_rxx_stats_ctl_s      cn66xx;
+	struct cvmx_gmxx_rxx_stats_ctl_s      cn68xx;
+	struct cvmx_gmxx_rxx_stats_ctl_s      cn68xxp1;
+	struct cvmx_gmxx_rxx_stats_ctl_s      cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_stats_ctl cvmx_gmxx_rxx_stats_ctl_t;
 
@@ -4702,12 +6726,10 @@ typedef union cvmx_gmxx_rxx_stats_ctl cvmx_gmxx_rxx_stats_ctl_t;
  * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
  * - Counters will wrap
  */
-union cvmx_gmxx_rxx_stats_octs
-{
+union cvmx_gmxx_rxx_stats_octs {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_stats_octs_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_stats_octs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t cnt                          : 48; /**< Octet count of received good packets */
 #else
@@ -4726,8 +6748,13 @@ union cvmx_gmxx_rxx_stats_octs
 	struct cvmx_gmxx_rxx_stats_octs_s     cn56xxp1;
 	struct cvmx_gmxx_rxx_stats_octs_s     cn58xx;
 	struct cvmx_gmxx_rxx_stats_octs_s     cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_s     cn61xx;
 	struct cvmx_gmxx_rxx_stats_octs_s     cn63xx;
 	struct cvmx_gmxx_rxx_stats_octs_s     cn63xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_s     cn66xx;
+	struct cvmx_gmxx_rxx_stats_octs_s     cn68xx;
+	struct cvmx_gmxx_rxx_stats_octs_s     cn68xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_s     cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_stats_octs cvmx_gmxx_rxx_stats_octs_t;
 
@@ -4738,12 +6765,10 @@ typedef union cvmx_gmxx_rxx_stats_octs cvmx_gmxx_rxx_stats_octs_t;
  * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
  * - Counters will wrap
  */
-union cvmx_gmxx_rxx_stats_octs_ctl
-{
+union cvmx_gmxx_rxx_stats_octs_ctl {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_stats_octs_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t cnt                          : 48; /**< Octet count of received pause packets */
 #else
@@ -4762,8 +6787,13 @@ union cvmx_gmxx_rxx_stats_octs_ctl
 	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1;
 	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx;
 	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn61xx;
 	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xx;
 	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn66xx;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xx;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_stats_octs_ctl cvmx_gmxx_rxx_stats_octs_ctl_t;
 
@@ -4774,12 +6804,10 @@ typedef union cvmx_gmxx_rxx_stats_octs_ctl cvmx_gmxx_rxx_stats_octs_ctl_t;
  * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
  * - Counters will wrap
  */
-union cvmx_gmxx_rxx_stats_octs_dmac
-{
+union cvmx_gmxx_rxx_stats_octs_dmac {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_stats_octs_dmac_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t cnt                          : 48; /**< Octet count of filtered dmac packets */
 #else
@@ -4798,8 +6826,13 @@ union cvmx_gmxx_rxx_stats_octs_dmac
 	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1;
 	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx;
 	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn61xx;
 	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xx;
 	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn66xx;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xx;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_stats_octs_dmac cvmx_gmxx_rxx_stats_octs_dmac_t;
 
@@ -4810,12 +6843,10 @@ typedef union cvmx_gmxx_rxx_stats_octs_dmac cvmx_gmxx_rxx_stats_octs_dmac_t;
  * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
  * - Counters will wrap
  */
-union cvmx_gmxx_rxx_stats_octs_drp
-{
+union cvmx_gmxx_rxx_stats_octs_drp {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_stats_octs_drp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_stats_octs_drp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t cnt                          : 48; /**< Octet count of dropped packets */
 #else
@@ -4834,8 +6865,13 @@ union cvmx_gmxx_rxx_stats_octs_drp
 	struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1;
 	struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx;
 	struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s cn61xx;
 	struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xx;
 	struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s cn66xx;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xx;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_stats_octs_drp cvmx_gmxx_rxx_stats_octs_drp_t;
 
@@ -4852,12 +6888,10 @@ typedef union cvmx_gmxx_rxx_stats_octs_drp cvmx_gmxx_rxx_stats_octs_drp_t;
  * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
  * - Counters will wrap
  */
-union cvmx_gmxx_rxx_stats_pkts
-{
+union cvmx_gmxx_rxx_stats_pkts {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_stats_pkts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_stats_pkts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< Count of received good packets */
 #else
@@ -4876,8 +6910,13 @@ union cvmx_gmxx_rxx_stats_pkts
 	struct cvmx_gmxx_rxx_stats_pkts_s     cn56xxp1;
 	struct cvmx_gmxx_rxx_stats_pkts_s     cn58xx;
 	struct cvmx_gmxx_rxx_stats_pkts_s     cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_s     cn61xx;
 	struct cvmx_gmxx_rxx_stats_pkts_s     cn63xx;
 	struct cvmx_gmxx_rxx_stats_pkts_s     cn63xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_s     cn66xx;
+	struct cvmx_gmxx_rxx_stats_pkts_s     cn68xx;
+	struct cvmx_gmxx_rxx_stats_pkts_s     cn68xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_s     cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_stats_pkts cvmx_gmxx_rxx_stats_pkts_t;
 
@@ -4893,12 +6932,10 @@ typedef union cvmx_gmxx_rxx_stats_pkts cvmx_gmxx_rxx_stats_pkts_t;
  * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
  * - Counters will wrap
  */
-union cvmx_gmxx_rxx_stats_pkts_bad
-{
+union cvmx_gmxx_rxx_stats_pkts_bad {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_stats_pkts_bad_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< Count of bad packets */
 #else
@@ -4917,8 +6954,13 @@ union cvmx_gmxx_rxx_stats_pkts_bad
 	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1;
 	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx;
 	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn61xx;
 	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xx;
 	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn66xx;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xx;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_stats_pkts_bad cvmx_gmxx_rxx_stats_pkts_bad_t;
 
@@ -4939,12 +6981,10 @@ typedef union cvmx_gmxx_rxx_stats_pkts_bad cvmx_gmxx_rxx_stats_pkts_bad_t;
  * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
  * - Counters will wrap
  */
-union cvmx_gmxx_rxx_stats_pkts_ctl
-{
+union cvmx_gmxx_rxx_stats_pkts_ctl {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_stats_pkts_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< Count of received pause packets */
 #else
@@ -4963,8 +7003,13 @@ union cvmx_gmxx_rxx_stats_pkts_ctl
 	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1;
 	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx;
 	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn61xx;
 	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xx;
 	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn66xx;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xx;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_stats_pkts_ctl cvmx_gmxx_rxx_stats_pkts_ctl_t;
 
@@ -4986,12 +7031,10 @@ typedef union cvmx_gmxx_rxx_stats_pkts_ctl cvmx_gmxx_rxx_stats_pkts_ctl_t;
  * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
  * - Counters will wrap
  */
-union cvmx_gmxx_rxx_stats_pkts_dmac
-{
+union cvmx_gmxx_rxx_stats_pkts_dmac {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_stats_pkts_dmac_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< Count of filtered dmac packets */
 #else
@@ -5010,8 +7053,13 @@ union cvmx_gmxx_rxx_stats_pkts_dmac
 	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1;
 	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx;
 	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn61xx;
 	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xx;
 	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn66xx;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xx;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_stats_pkts_dmac cvmx_gmxx_rxx_stats_pkts_dmac_t;
 
@@ -5020,21 +7068,21 @@ typedef union cvmx_gmxx_rxx_stats_pkts_dmac cvmx_gmxx_rxx_stats_pkts_dmac_t;
  *
  * GMX_RX_STATS_PKTS_DRP
  *
- * Count of all packets received that were dropped due to a full receive
- * FIFO.  This counts good and bad packets received - all packets dropped by
- * the FIFO.  It does not count packets dropped by the dmac or pause packet
+ * Count of all packets received that were dropped due to a full receive FIFO.
+ * This counts both partial packets in which there was enough space in the RX
+ * FIFO to begin to buffer and the packet and total drops in which no packet was
+ * sent to PKI.  This counts good and bad packets received - all packets dropped
+ * by the FIFO.  It does not count packets dropped by the dmac or pause packet
  * filters.
  *
  * Notes:
  * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
  * - Counters will wrap
  */
-union cvmx_gmxx_rxx_stats_pkts_drp
-{
+union cvmx_gmxx_rxx_stats_pkts_drp {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_stats_pkts_drp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< Count of dropped packets */
 #else
@@ -5053,8 +7101,13 @@ union cvmx_gmxx_rxx_stats_pkts_drp
 	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1;
 	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx;
 	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn61xx;
 	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xx;
 	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn66xx;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xx;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_stats_pkts_drp cvmx_gmxx_rxx_stats_pkts_drp_t;
 
@@ -5089,12 +7142,10 @@ typedef union cvmx_gmxx_rxx_stats_pkts_drp cvmx_gmxx_rxx_stats_pkts_drp_t;
  *
  * (7) If LEN != 0, then GMX_RX_FRM_CHK[LENERR] will be disabled and GMX_RX_INT_REG[LENERR] will be zero
  */
-union cvmx_gmxx_rxx_udd_skp
-{
+union cvmx_gmxx_rxx_udd_skp {
 	uint64_t u64;
-	struct cvmx_gmxx_rxx_udd_skp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rxx_udd_skp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t fcssel                       : 1;  /**< Include the skip bytes in the FCS calculation
                                                          0 = all skip bytes are included in FCS
@@ -5127,8 +7178,13 @@ union cvmx_gmxx_rxx_udd_skp
 	struct cvmx_gmxx_rxx_udd_skp_s        cn56xxp1;
 	struct cvmx_gmxx_rxx_udd_skp_s        cn58xx;
 	struct cvmx_gmxx_rxx_udd_skp_s        cn58xxp1;
+	struct cvmx_gmxx_rxx_udd_skp_s        cn61xx;
 	struct cvmx_gmxx_rxx_udd_skp_s        cn63xx;
 	struct cvmx_gmxx_rxx_udd_skp_s        cn63xxp1;
+	struct cvmx_gmxx_rxx_udd_skp_s        cn66xx;
+	struct cvmx_gmxx_rxx_udd_skp_s        cn68xx;
+	struct cvmx_gmxx_rxx_udd_skp_s        cn68xxp1;
+	struct cvmx_gmxx_rxx_udd_skp_s        cnf71xx;
 };
 typedef union cvmx_gmxx_rxx_udd_skp cvmx_gmxx_rxx_udd_skp_t;
 
@@ -5145,12 +7201,10 @@ typedef union cvmx_gmxx_rxx_udd_skp cvmx_gmxx_rxx_udd_skp_t;
  *
  * In XAUI mode prt0 is used for checking.
  */
-union cvmx_gmxx_rx_bp_dropx
-{
+union cvmx_gmxx_rx_bp_dropx {
 	uint64_t u64;
-	struct cvmx_gmxx_rx_bp_dropx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rx_bp_dropx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t mark                         : 6;  /**< Number of 8B ticks to reserve in the RX FIFO.
                                                          When the FIFO exceeds this count, packets will
@@ -5174,8 +7228,13 @@ union cvmx_gmxx_rx_bp_dropx
 	struct cvmx_gmxx_rx_bp_dropx_s        cn56xxp1;
 	struct cvmx_gmxx_rx_bp_dropx_s        cn58xx;
 	struct cvmx_gmxx_rx_bp_dropx_s        cn58xxp1;
+	struct cvmx_gmxx_rx_bp_dropx_s        cn61xx;
 	struct cvmx_gmxx_rx_bp_dropx_s        cn63xx;
 	struct cvmx_gmxx_rx_bp_dropx_s        cn63xxp1;
+	struct cvmx_gmxx_rx_bp_dropx_s        cn66xx;
+	struct cvmx_gmxx_rx_bp_dropx_s        cn68xx;
+	struct cvmx_gmxx_rx_bp_dropx_s        cn68xxp1;
+	struct cvmx_gmxx_rx_bp_dropx_s        cnf71xx;
 };
 typedef union cvmx_gmxx_rx_bp_dropx cvmx_gmxx_rx_bp_dropx_t;
 
@@ -5189,12 +7248,10 @@ typedef union cvmx_gmxx_rx_bp_dropx cvmx_gmxx_rx_bp_dropx_t;
  * In XAUI mode, prt0 is used for checking.
  *
  */
-union cvmx_gmxx_rx_bp_offx
-{
+union cvmx_gmxx_rx_bp_offx {
 	uint64_t u64;
-	struct cvmx_gmxx_rx_bp_offx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rx_bp_offx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t mark                         : 6;  /**< Water mark (8B ticks) to deassert backpressure */
 #else
@@ -5213,8 +7270,13 @@ union cvmx_gmxx_rx_bp_offx
 	struct cvmx_gmxx_rx_bp_offx_s         cn56xxp1;
 	struct cvmx_gmxx_rx_bp_offx_s         cn58xx;
 	struct cvmx_gmxx_rx_bp_offx_s         cn58xxp1;
+	struct cvmx_gmxx_rx_bp_offx_s         cn61xx;
 	struct cvmx_gmxx_rx_bp_offx_s         cn63xx;
 	struct cvmx_gmxx_rx_bp_offx_s         cn63xxp1;
+	struct cvmx_gmxx_rx_bp_offx_s         cn66xx;
+	struct cvmx_gmxx_rx_bp_offx_s         cn68xx;
+	struct cvmx_gmxx_rx_bp_offx_s         cn68xxp1;
+	struct cvmx_gmxx_rx_bp_offx_s         cnf71xx;
 };
 typedef union cvmx_gmxx_rx_bp_offx cvmx_gmxx_rx_bp_offx_t;
 
@@ -5228,14 +7290,12 @@ typedef union cvmx_gmxx_rx_bp_offx cvmx_gmxx_rx_bp_offx_t;
  * In XAUI mode, prt0 is used for checking.
  *
  */
-union cvmx_gmxx_rx_bp_onx
-{
+union cvmx_gmxx_rx_bp_onx {
 	uint64_t u64;
-	struct cvmx_gmxx_rx_bp_onx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_9_63                : 55;
-	uint64_t mark                         : 9;  /**< Hiwater mark (8B ticks) for backpressure.
+	struct cvmx_gmxx_rx_bp_onx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_11_63               : 53;
+	uint64_t mark                         : 11; /**< Hiwater mark (8B ticks) for backpressure.
                                                          Each register is for an individual port.  In XAUI
                                                          mode, prt0 is used for the unified RX FIFO
                                                          GMX_RX_BP_ON must satisfy
@@ -5243,23 +7303,45 @@ union cvmx_gmxx_rx_bp_onx
                                                          A value of zero will immediately assert back
                                                          pressure. */
 #else
+	uint64_t mark                         : 11;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} s;
+	struct cvmx_gmxx_rx_bp_onx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_9_63                : 55;
+	uint64_t mark                         : 9;  /**< Hiwater mark (8B ticks) for backpressure.
+                                                         In RGMII mode, the backpressure is given per
+                                                         port.  In Spi4 mode, the backpressure is for the
+                                                         entire interface.  GMX_RX_BP_ON must satisfy
+                                                         BP_OFF <= BP_ON < (FIFO_SIZE - BP_DROP)
+                                                         The reset value is half the FIFO.
+                                                         Reset value RGMII mode = 0x40  (512bytes)
+                                                         Reset value Spi4 mode  = 0x100 (2048bytes)
+                                                         A value of zero will immediately assert back
+                                                         pressure. */
+#else
 	uint64_t mark                         : 9;
 	uint64_t reserved_9_63                : 55;
 #endif
-	} s;
-	struct cvmx_gmxx_rx_bp_onx_s          cn30xx;
-	struct cvmx_gmxx_rx_bp_onx_s          cn31xx;
-	struct cvmx_gmxx_rx_bp_onx_s          cn38xx;
-	struct cvmx_gmxx_rx_bp_onx_s          cn38xxp2;
-	struct cvmx_gmxx_rx_bp_onx_s          cn50xx;
-	struct cvmx_gmxx_rx_bp_onx_s          cn52xx;
-	struct cvmx_gmxx_rx_bp_onx_s          cn52xxp1;
-	struct cvmx_gmxx_rx_bp_onx_s          cn56xx;
-	struct cvmx_gmxx_rx_bp_onx_s          cn56xxp1;
-	struct cvmx_gmxx_rx_bp_onx_s          cn58xx;
-	struct cvmx_gmxx_rx_bp_onx_s          cn58xxp1;
-	struct cvmx_gmxx_rx_bp_onx_s          cn63xx;
-	struct cvmx_gmxx_rx_bp_onx_s          cn63xxp1;
+	} cn30xx;
+	struct cvmx_gmxx_rx_bp_onx_cn30xx     cn31xx;
+	struct cvmx_gmxx_rx_bp_onx_cn30xx     cn38xx;
+	struct cvmx_gmxx_rx_bp_onx_cn30xx     cn38xxp2;
+	struct cvmx_gmxx_rx_bp_onx_cn30xx     cn50xx;
+	struct cvmx_gmxx_rx_bp_onx_cn30xx     cn52xx;
+	struct cvmx_gmxx_rx_bp_onx_cn30xx     cn52xxp1;
+	struct cvmx_gmxx_rx_bp_onx_cn30xx     cn56xx;
+	struct cvmx_gmxx_rx_bp_onx_cn30xx     cn56xxp1;
+	struct cvmx_gmxx_rx_bp_onx_cn30xx     cn58xx;
+	struct cvmx_gmxx_rx_bp_onx_cn30xx     cn58xxp1;
+	struct cvmx_gmxx_rx_bp_onx_cn30xx     cn61xx;
+	struct cvmx_gmxx_rx_bp_onx_cn30xx     cn63xx;
+	struct cvmx_gmxx_rx_bp_onx_cn30xx     cn63xxp1;
+	struct cvmx_gmxx_rx_bp_onx_cn30xx     cn66xx;
+	struct cvmx_gmxx_rx_bp_onx_s          cn68xx;
+	struct cvmx_gmxx_rx_bp_onx_s          cn68xxp1;
+	struct cvmx_gmxx_rx_bp_onx_cn30xx     cnf71xx;
 };
 typedef union cvmx_gmxx_rx_bp_onx cvmx_gmxx_rx_bp_onx_t;
 
@@ -5269,12 +7351,10 @@ typedef union cvmx_gmxx_rx_bp_onx cvmx_gmxx_rx_bp_onx_t;
  * ** HG2 message CSRs
  *
  */
-union cvmx_gmxx_rx_hg2_status
-{
+union cvmx_gmxx_rx_hg2_status {
 	uint64_t u64;
-	struct cvmx_gmxx_rx_hg2_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rx_hg2_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t phtim2go                     : 16; /**< Physical time to go for removal of physical link
                                                          pause. Initial value from received HiGig2 msg pkt
@@ -5298,8 +7378,13 @@ union cvmx_gmxx_rx_hg2_status
 	struct cvmx_gmxx_rx_hg2_status_s      cn52xx;
 	struct cvmx_gmxx_rx_hg2_status_s      cn52xxp1;
 	struct cvmx_gmxx_rx_hg2_status_s      cn56xx;
+	struct cvmx_gmxx_rx_hg2_status_s      cn61xx;
 	struct cvmx_gmxx_rx_hg2_status_s      cn63xx;
 	struct cvmx_gmxx_rx_hg2_status_s      cn63xxp1;
+	struct cvmx_gmxx_rx_hg2_status_s      cn66xx;
+	struct cvmx_gmxx_rx_hg2_status_s      cn68xx;
+	struct cvmx_gmxx_rx_hg2_status_s      cn68xxp1;
+	struct cvmx_gmxx_rx_hg2_status_s      cnf71xx;
 };
 typedef union cvmx_gmxx_rx_hg2_status cvmx_gmxx_rx_hg2_status_t;
 
@@ -5319,12 +7404,10 @@ typedef union cvmx_gmxx_rx_hg2_status cvmx_gmxx_rx_hg2_status_t;
  * (2) The mapped pass through output port cannot be the destination port for
  *     any Octane core traffic.
  */
-union cvmx_gmxx_rx_pass_en
-{
+union cvmx_gmxx_rx_pass_en {
 	uint64_t u64;
-	struct cvmx_gmxx_rx_pass_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rx_pass_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t en                           : 16; /**< Which ports to configure in pass through mode */
 #else
@@ -5345,12 +7428,10 @@ typedef union cvmx_gmxx_rx_pass_en cvmx_gmxx_rx_pass_en_t;
  * GMX_RX_PASS_MAP = Packet pass through port map
  *
  */
-union cvmx_gmxx_rx_pass_mapx
-{
+union cvmx_gmxx_rx_pass_mapx {
 	uint64_t u64;
-	struct cvmx_gmxx_rx_pass_mapx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rx_pass_mapx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t dprt                         : 4;  /**< Destination port to map Spi pass through traffic */
 #else
@@ -5375,12 +7456,10 @@ typedef union cvmx_gmxx_rx_pass_mapx cvmx_gmxx_rx_pass_mapx_t;
  * In XAUI mode, only the lsb (corresponding to port0) of DROP and COMMIT are used.
  *
  */
-union cvmx_gmxx_rx_prt_info
-{
+union cvmx_gmxx_rx_prt_info {
 	uint64_t u64;
-	struct cvmx_gmxx_rx_prt_info_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rx_prt_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t drop                         : 16; /**< Per port indication that data was dropped */
 	uint64_t commit                       : 16; /**< Per port indication that SOP was accepted */
@@ -5390,9 +7469,8 @@ union cvmx_gmxx_rx_prt_info
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
-	struct cvmx_gmxx_rx_prt_info_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rx_prt_info_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t drop                         : 3;  /**< Per port indication that data was dropped */
 	uint64_t reserved_3_15                : 13;
@@ -5407,9 +7485,8 @@ union cvmx_gmxx_rx_prt_info
 	struct cvmx_gmxx_rx_prt_info_cn30xx   cn31xx;
 	struct cvmx_gmxx_rx_prt_info_s        cn38xx;
 	struct cvmx_gmxx_rx_prt_info_cn30xx   cn50xx;
-	struct cvmx_gmxx_rx_prt_info_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rx_prt_info_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t drop                         : 4;  /**< Per port indication that data was dropped */
 	uint64_t reserved_4_15                : 12;
@@ -5426,8 +7503,25 @@ union cvmx_gmxx_rx_prt_info
 	struct cvmx_gmxx_rx_prt_info_cn52xx   cn56xxp1;
 	struct cvmx_gmxx_rx_prt_info_s        cn58xx;
 	struct cvmx_gmxx_rx_prt_info_s        cn58xxp1;
+	struct cvmx_gmxx_rx_prt_info_cn52xx   cn61xx;
 	struct cvmx_gmxx_rx_prt_info_cn52xx   cn63xx;
 	struct cvmx_gmxx_rx_prt_info_cn52xx   cn63xxp1;
+	struct cvmx_gmxx_rx_prt_info_cn52xx   cn66xx;
+	struct cvmx_gmxx_rx_prt_info_cn52xx   cn68xx;
+	struct cvmx_gmxx_rx_prt_info_cn52xx   cn68xxp1;
+	struct cvmx_gmxx_rx_prt_info_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_18_63               : 46;
+	uint64_t drop                         : 2;  /**< Per port indication that data was dropped */
+	uint64_t reserved_2_15                : 14;
+	uint64_t commit                       : 2;  /**< Per port indication that SOP was accepted */
+#else
+	uint64_t commit                       : 2;
+	uint64_t reserved_2_15                : 14;
+	uint64_t drop                         : 2;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_gmxx_rx_prt_info cvmx_gmxx_rx_prt_info_t;
 
@@ -5441,12 +7535,10 @@ typedef union cvmx_gmxx_rx_prt_info cvmx_gmxx_rx_prt_info_t;
  * GMX_RX_PRTS[PRTS] must be set to '1' in XAUI mode.
  *
  */
-union cvmx_gmxx_rx_prts
-{
+union cvmx_gmxx_rx_prts {
 	uint64_t u64;
-	struct cvmx_gmxx_rx_prts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rx_prts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t prts                         : 3;  /**< In SGMII/1000Base-X mode, the RX buffer can be
                                                          carved into several logical buffers depending on
@@ -5470,8 +7562,13 @@ union cvmx_gmxx_rx_prts
 	struct cvmx_gmxx_rx_prts_s            cn56xxp1;
 	struct cvmx_gmxx_rx_prts_s            cn58xx;
 	struct cvmx_gmxx_rx_prts_s            cn58xxp1;
+	struct cvmx_gmxx_rx_prts_s            cn61xx;
 	struct cvmx_gmxx_rx_prts_s            cn63xx;
 	struct cvmx_gmxx_rx_prts_s            cn63xxp1;
+	struct cvmx_gmxx_rx_prts_s            cn66xx;
+	struct cvmx_gmxx_rx_prts_s            cn68xx;
+	struct cvmx_gmxx_rx_prts_s            cn68xxp1;
+	struct cvmx_gmxx_rx_prts_s            cnf71xx;
 };
 typedef union cvmx_gmxx_rx_prts cvmx_gmxx_rx_prts_t;
 
@@ -5481,12 +7578,10 @@ typedef union cvmx_gmxx_rx_prts cvmx_gmxx_rx_prts_t;
  * GMX_RX_TX_STATUS = GMX RX/TX Status
  *
  */
-union cvmx_gmxx_rx_tx_status
-{
+union cvmx_gmxx_rx_tx_status {
 	uint64_t u64;
-	struct cvmx_gmxx_rx_tx_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rx_tx_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t tx                           : 3;  /**< Transmit data since last read */
 	uint64_t reserved_3_3                 : 1;
@@ -5507,12 +7602,10 @@ typedef union cvmx_gmxx_rx_tx_status cvmx_gmxx_rx_tx_status_t;
 /**
  * cvmx_gmx#_rx_xaui_bad_col
  */
-union cvmx_gmxx_rx_xaui_bad_col
-{
+union cvmx_gmxx_rx_xaui_bad_col {
 	uint64_t u64;
-	struct cvmx_gmxx_rx_xaui_bad_col_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rx_xaui_bad_col_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t val                          : 1;  /**< Set when GMX_RX_INT_REG[PCTERR] is set.
                                                          (XAUI mode only) */
@@ -5538,20 +7631,23 @@ union cvmx_gmxx_rx_xaui_bad_col
 	struct cvmx_gmxx_rx_xaui_bad_col_s    cn52xxp1;
 	struct cvmx_gmxx_rx_xaui_bad_col_s    cn56xx;
 	struct cvmx_gmxx_rx_xaui_bad_col_s    cn56xxp1;
+	struct cvmx_gmxx_rx_xaui_bad_col_s    cn61xx;
 	struct cvmx_gmxx_rx_xaui_bad_col_s    cn63xx;
 	struct cvmx_gmxx_rx_xaui_bad_col_s    cn63xxp1;
+	struct cvmx_gmxx_rx_xaui_bad_col_s    cn66xx;
+	struct cvmx_gmxx_rx_xaui_bad_col_s    cn68xx;
+	struct cvmx_gmxx_rx_xaui_bad_col_s    cn68xxp1;
+	struct cvmx_gmxx_rx_xaui_bad_col_s    cnf71xx;
 };
 typedef union cvmx_gmxx_rx_xaui_bad_col cvmx_gmxx_rx_xaui_bad_col_t;
 
 /**
  * cvmx_gmx#_rx_xaui_ctl
  */
-union cvmx_gmxx_rx_xaui_ctl
-{
+union cvmx_gmxx_rx_xaui_ctl {
 	uint64_t u64;
-	struct cvmx_gmxx_rx_xaui_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_rx_xaui_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t status                       : 2;  /**< Link Status
                                                          0=Link OK
@@ -5568,23 +7664,55 @@ union cvmx_gmxx_rx_xaui_ctl
 	struct cvmx_gmxx_rx_xaui_ctl_s        cn52xxp1;
 	struct cvmx_gmxx_rx_xaui_ctl_s        cn56xx;
 	struct cvmx_gmxx_rx_xaui_ctl_s        cn56xxp1;
+	struct cvmx_gmxx_rx_xaui_ctl_s        cn61xx;
 	struct cvmx_gmxx_rx_xaui_ctl_s        cn63xx;
 	struct cvmx_gmxx_rx_xaui_ctl_s        cn63xxp1;
+	struct cvmx_gmxx_rx_xaui_ctl_s        cn66xx;
+	struct cvmx_gmxx_rx_xaui_ctl_s        cn68xx;
+	struct cvmx_gmxx_rx_xaui_ctl_s        cn68xxp1;
+	struct cvmx_gmxx_rx_xaui_ctl_s        cnf71xx;
 };
 typedef union cvmx_gmxx_rx_xaui_ctl cvmx_gmxx_rx_xaui_ctl_t;
 
 /**
+ * cvmx_gmx#_rxaui_ctl
+ */
+union cvmx_gmxx_rxaui_ctl {
+	uint64_t u64;
+	struct cvmx_gmxx_rxaui_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_1_63                : 63;
+	uint64_t disparity                    : 1;  /**< Selects which disparity calculation to use when
+                                                         combining or splitting the RXAUI lanes.
+                                                         0=Interleave lanes before PCS layer
+                                                           As described in the Dune Networks/Broadcom
+                                                           RXAUI v2.1 specification.
+                                                           (obeys 6.25GHz SERDES disparity)
+                                                         1=Interleave lanes after PCS layer
+                                                           As described in the Marvell RXAUI Interface
+                                                           specification.
+                                                           (does not obey 6.25GHz SERDES disparity)
+                                                         (RXAUI mode only) */
+#else
+	uint64_t disparity                    : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_gmxx_rxaui_ctl_s          cn68xx;
+	struct cvmx_gmxx_rxaui_ctl_s          cn68xxp1;
+};
+typedef union cvmx_gmxx_rxaui_ctl cvmx_gmxx_rxaui_ctl_t;
+
+/**
  * cvmx_gmx#_smac#
  *
  * GMX_SMAC = Packet SMAC
  *
  */
-union cvmx_gmxx_smacx
-{
+union cvmx_gmxx_smacx {
 	uint64_t u64;
-	struct cvmx_gmxx_smacx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_smacx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t smac                         : 48; /**< The SMAC field is used for generating and
                                                          accepting Control Pause packets */
@@ -5604,8 +7732,13 @@ union cvmx_gmxx_smacx
 	struct cvmx_gmxx_smacx_s              cn56xxp1;
 	struct cvmx_gmxx_smacx_s              cn58xx;
 	struct cvmx_gmxx_smacx_s              cn58xxp1;
+	struct cvmx_gmxx_smacx_s              cn61xx;
 	struct cvmx_gmxx_smacx_s              cn63xx;
 	struct cvmx_gmxx_smacx_s              cn63xxp1;
+	struct cvmx_gmxx_smacx_s              cn66xx;
+	struct cvmx_gmxx_smacx_s              cn68xx;
+	struct cvmx_gmxx_smacx_s              cn68xxp1;
+	struct cvmx_gmxx_smacx_s              cnf71xx;
 };
 typedef union cvmx_gmxx_smacx cvmx_gmxx_smacx_t;
 
@@ -5615,14 +7748,13 @@ typedef union cvmx_gmxx_smacx cvmx_gmxx_smacx_t;
  * GMX_SOFT_BIST = Software BIST Control
  *
  */
-union cvmx_gmxx_soft_bist
-{
+union cvmx_gmxx_soft_bist {
 	uint64_t u64;
-	struct cvmx_gmxx_soft_bist_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_soft_bist_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
-	uint64_t start_bist                   : 1;  /**< Run BIST on all memories in the XAUI CLK domain */
+	uint64_t start_bist                   : 1;  /**< Run BIST on all memories in the XAUI/RXAUI
+                                                         CLK domain */
 	uint64_t clear_bist                   : 1;  /**< Choose between full BIST and CLEAR bist
                                                          0=Run full BIST
                                                          1=Only run clear BIST */
@@ -5634,6 +7766,9 @@ union cvmx_gmxx_soft_bist
 	} s;
 	struct cvmx_gmxx_soft_bist_s          cn63xx;
 	struct cvmx_gmxx_soft_bist_s          cn63xxp1;
+	struct cvmx_gmxx_soft_bist_s          cn66xx;
+	struct cvmx_gmxx_soft_bist_s          cn68xx;
+	struct cvmx_gmxx_soft_bist_s          cn68xxp1;
 };
 typedef union cvmx_gmxx_soft_bist cvmx_gmxx_soft_bist_t;
 
@@ -5642,15 +7777,34 @@ typedef union cvmx_gmxx_soft_bist cvmx_gmxx_soft_bist_t;
  *
  * GMX_STAT_BP = Number of cycles that the TX/Stats block has help up operation
  *
+ *
+ * Notes:
+ * It has no relationship with the TX FIFO per se.  The TX engine sends packets
+ * from PKO and upon completion, sends a command to the TX stats block for an
+ * update based on the packet size.  The stats operation can take a few cycles -
+ * normally not enough to be visible considering the 64B min packet size that is
+ * ethernet convention.
+ *
+ * In the rare case in which SW attempted to schedule really, really, small packets
+ * or the sclk (6xxx) is running ass-slow, then the stats updates may not happen in
+ * real time and can back up the TX engine.
+ *
+ * This counter is the number of cycles in which the TX engine was stalled.  In
+ * normal operation, it should always be zeros.
  */
-union cvmx_gmxx_stat_bp
-{
+union cvmx_gmxx_stat_bp {
 	uint64_t u64;
-	struct cvmx_gmxx_stat_bp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_stat_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
-	uint64_t bp                           : 1;  /**< Current BP state */
+	uint64_t bp                           : 1;  /**< Current TX stats BP state
+                                                         When the TX stats machine cannot update the stats
+                                                         registers quickly enough, the machine has the
+                                                         ability to BP TX datapath.  This is a rare event
+                                                         and will not occur in normal operation.
+                                                         0 = no backpressure is applied
+                                                         1 = backpressure is applied to TX datapath to
+                                                             allow stat update operations to complete */
 	uint64_t cnt                          : 16; /**< Number of cycles that BP has been asserted
                                                          Saturating counter */
 #else
@@ -5670,23 +7824,50 @@ union cvmx_gmxx_stat_bp
 	struct cvmx_gmxx_stat_bp_s            cn56xxp1;
 	struct cvmx_gmxx_stat_bp_s            cn58xx;
 	struct cvmx_gmxx_stat_bp_s            cn58xxp1;
+	struct cvmx_gmxx_stat_bp_s            cn61xx;
 	struct cvmx_gmxx_stat_bp_s            cn63xx;
 	struct cvmx_gmxx_stat_bp_s            cn63xxp1;
+	struct cvmx_gmxx_stat_bp_s            cn66xx;
+	struct cvmx_gmxx_stat_bp_s            cn68xx;
+	struct cvmx_gmxx_stat_bp_s            cn68xxp1;
+	struct cvmx_gmxx_stat_bp_s            cnf71xx;
 };
 typedef union cvmx_gmxx_stat_bp cvmx_gmxx_stat_bp_t;
 
 /**
+ * cvmx_gmx#_tb_reg
+ *
+ * DON'T PUT IN HRM*
+ *
+ */
+union cvmx_gmxx_tb_reg {
+	uint64_t u64;
+	struct cvmx_gmxx_tb_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_1_63                : 63;
+	uint64_t wr_magic                     : 1;  /**< Enter stats model magic mode */
+#else
+	uint64_t wr_magic                     : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_gmxx_tb_reg_s             cn61xx;
+	struct cvmx_gmxx_tb_reg_s             cn66xx;
+	struct cvmx_gmxx_tb_reg_s             cn68xx;
+	struct cvmx_gmxx_tb_reg_s             cnf71xx;
+};
+typedef union cvmx_gmxx_tb_reg cvmx_gmxx_tb_reg_t;
+
+/**
  * cvmx_gmx#_tx#_append
  *
  * GMX_TX_APPEND = Packet TX Append Control
  *
  */
-union cvmx_gmxx_txx_append
-{
+union cvmx_gmxx_txx_append {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_append_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_append_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t force_fcs                    : 1;  /**< Append the Ethernet FCS on each pause packet
                                                          when FCS is clear.  Pause packets are normally
@@ -5716,8 +7897,13 @@ union cvmx_gmxx_txx_append
 	struct cvmx_gmxx_txx_append_s         cn56xxp1;
 	struct cvmx_gmxx_txx_append_s         cn58xx;
 	struct cvmx_gmxx_txx_append_s         cn58xxp1;
+	struct cvmx_gmxx_txx_append_s         cn61xx;
 	struct cvmx_gmxx_txx_append_s         cn63xx;
 	struct cvmx_gmxx_txx_append_s         cn63xxp1;
+	struct cvmx_gmxx_txx_append_s         cn66xx;
+	struct cvmx_gmxx_txx_append_s         cn68xx;
+	struct cvmx_gmxx_txx_append_s         cn68xxp1;
+	struct cvmx_gmxx_txx_append_s         cnf71xx;
 };
 typedef union cvmx_gmxx_txx_append cvmx_gmxx_txx_append_t;
 
@@ -5727,12 +7913,10 @@ typedef union cvmx_gmxx_txx_append cvmx_gmxx_txx_append_t;
  * GMX_TX_BURST = Packet TX Burst Counter
  *
  */
-union cvmx_gmxx_txx_burst
-{
+union cvmx_gmxx_txx_burst {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_burst_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_burst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t burst                        : 16; /**< Burst (refer to 802.3 to set correctly)
                                                          Only valid for 1000Mbs half-duplex operation
@@ -5755,20 +7939,23 @@ union cvmx_gmxx_txx_burst
 	struct cvmx_gmxx_txx_burst_s          cn56xxp1;
 	struct cvmx_gmxx_txx_burst_s          cn58xx;
 	struct cvmx_gmxx_txx_burst_s          cn58xxp1;
+	struct cvmx_gmxx_txx_burst_s          cn61xx;
 	struct cvmx_gmxx_txx_burst_s          cn63xx;
 	struct cvmx_gmxx_txx_burst_s          cn63xxp1;
+	struct cvmx_gmxx_txx_burst_s          cn66xx;
+	struct cvmx_gmxx_txx_burst_s          cn68xx;
+	struct cvmx_gmxx_txx_burst_s          cn68xxp1;
+	struct cvmx_gmxx_txx_burst_s          cnf71xx;
 };
 typedef union cvmx_gmxx_txx_burst cvmx_gmxx_txx_burst_t;
 
 /**
  * cvmx_gmx#_tx#_cbfc_xoff
  */
-union cvmx_gmxx_txx_cbfc_xoff
-{
+union cvmx_gmxx_txx_cbfc_xoff {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_cbfc_xoff_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_cbfc_xoff_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t xoff                         : 16; /**< Which ports to backpressure
                                                          Do not write in HiGig2 mode i.e. when
@@ -5781,20 +7968,23 @@ union cvmx_gmxx_txx_cbfc_xoff
 	} s;
 	struct cvmx_gmxx_txx_cbfc_xoff_s      cn52xx;
 	struct cvmx_gmxx_txx_cbfc_xoff_s      cn56xx;
+	struct cvmx_gmxx_txx_cbfc_xoff_s      cn61xx;
 	struct cvmx_gmxx_txx_cbfc_xoff_s      cn63xx;
 	struct cvmx_gmxx_txx_cbfc_xoff_s      cn63xxp1;
+	struct cvmx_gmxx_txx_cbfc_xoff_s      cn66xx;
+	struct cvmx_gmxx_txx_cbfc_xoff_s      cn68xx;
+	struct cvmx_gmxx_txx_cbfc_xoff_s      cn68xxp1;
+	struct cvmx_gmxx_txx_cbfc_xoff_s      cnf71xx;
 };
 typedef union cvmx_gmxx_txx_cbfc_xoff cvmx_gmxx_txx_cbfc_xoff_t;
 
 /**
  * cvmx_gmx#_tx#_cbfc_xon
  */
-union cvmx_gmxx_txx_cbfc_xon
-{
+union cvmx_gmxx_txx_cbfc_xon {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_cbfc_xon_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_cbfc_xon_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t xon                          : 16; /**< Which ports to stop backpressure
                                                          Do not write in HiGig2 mode i.e. when
@@ -5807,8 +7997,13 @@ union cvmx_gmxx_txx_cbfc_xon
 	} s;
 	struct cvmx_gmxx_txx_cbfc_xon_s       cn52xx;
 	struct cvmx_gmxx_txx_cbfc_xon_s       cn56xx;
+	struct cvmx_gmxx_txx_cbfc_xon_s       cn61xx;
 	struct cvmx_gmxx_txx_cbfc_xon_s       cn63xx;
 	struct cvmx_gmxx_txx_cbfc_xon_s       cn63xxp1;
+	struct cvmx_gmxx_txx_cbfc_xon_s       cn66xx;
+	struct cvmx_gmxx_txx_cbfc_xon_s       cn68xx;
+	struct cvmx_gmxx_txx_cbfc_xon_s       cn68xxp1;
+	struct cvmx_gmxx_txx_cbfc_xon_s       cnf71xx;
 };
 typedef union cvmx_gmxx_txx_cbfc_xon cvmx_gmxx_txx_cbfc_xon_t;
 
@@ -5832,12 +8027,10 @@ typedef union cvmx_gmxx_txx_cbfc_xon cvmx_gmxx_txx_cbfc_xon_t;
  *   CLK_CNT ==  5 ==>  25.0MHz TXC clock period (8ns* 5)
  *   CLK_CNT == 50 ==>   2.5MHz TXC clock period (8ns*50)
  */
-union cvmx_gmxx_txx_clk
-{
+union cvmx_gmxx_txx_clk {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_clk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_clk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t clk_cnt                      : 6;  /**< Controls the RGMII TXC frequency
                                                          When PLL is used, TXC(phase) =
@@ -5867,12 +8060,10 @@ typedef union cvmx_gmxx_txx_clk cvmx_gmxx_txx_clk_t;
  * GMX_TX_CTL = TX Control register
  *
  */
-union cvmx_gmxx_txx_ctl
-{
+union cvmx_gmxx_txx_ctl {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t xsdef_en                     : 1;  /**< Enables the excessive deferral check for stats
                                                          and interrupts
@@ -5897,8 +8088,13 @@ union cvmx_gmxx_txx_ctl
 	struct cvmx_gmxx_txx_ctl_s            cn56xxp1;
 	struct cvmx_gmxx_txx_ctl_s            cn58xx;
 	struct cvmx_gmxx_txx_ctl_s            cn58xxp1;
+	struct cvmx_gmxx_txx_ctl_s            cn61xx;
 	struct cvmx_gmxx_txx_ctl_s            cn63xx;
 	struct cvmx_gmxx_txx_ctl_s            cn63xxp1;
+	struct cvmx_gmxx_txx_ctl_s            cn66xx;
+	struct cvmx_gmxx_txx_ctl_s            cn68xx;
+	struct cvmx_gmxx_txx_ctl_s            cn68xxp1;
+	struct cvmx_gmxx_txx_ctl_s            cnf71xx;
 };
 typedef union cvmx_gmxx_txx_ctl cvmx_gmxx_txx_ctl_t;
 
@@ -5908,12 +8104,10 @@ typedef union cvmx_gmxx_txx_ctl cvmx_gmxx_txx_ctl_t;
  * GMX_TX_MIN_PKT = Packet TX Min Size Packet (PAD upto min size)
  *
  */
-union cvmx_gmxx_txx_min_pkt
-{
+union cvmx_gmxx_txx_min_pkt {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_min_pkt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_min_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t min_size                     : 8;  /**< Min frame in bytes before the FCS is applied
                                                          Padding is only appened when GMX_TX_APPEND[PAD]
@@ -5942,8 +8136,13 @@ union cvmx_gmxx_txx_min_pkt
 	struct cvmx_gmxx_txx_min_pkt_s        cn56xxp1;
 	struct cvmx_gmxx_txx_min_pkt_s        cn58xx;
 	struct cvmx_gmxx_txx_min_pkt_s        cn58xxp1;
+	struct cvmx_gmxx_txx_min_pkt_s        cn61xx;
 	struct cvmx_gmxx_txx_min_pkt_s        cn63xx;
 	struct cvmx_gmxx_txx_min_pkt_s        cn63xxp1;
+	struct cvmx_gmxx_txx_min_pkt_s        cn66xx;
+	struct cvmx_gmxx_txx_min_pkt_s        cn68xx;
+	struct cvmx_gmxx_txx_min_pkt_s        cn68xxp1;
+	struct cvmx_gmxx_txx_min_pkt_s        cnf71xx;
 };
 typedef union cvmx_gmxx_txx_min_pkt cvmx_gmxx_txx_min_pkt_t;
 
@@ -5972,12 +8171,10 @@ typedef union cvmx_gmxx_txx_min_pkt cvmx_gmxx_txx_min_pkt_t;
  * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
  * of the PAUSE packet (normally 64B).
  */
-union cvmx_gmxx_txx_pause_pkt_interval
-{
+union cvmx_gmxx_txx_pause_pkt_interval {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_pause_pkt_interval_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_pause_pkt_interval_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t interval                     : 16; /**< Arbitrate for a 802.3 pause packet, HiGig2 message,
                                                          or CBFC pause packet every (INTERVAL*512)
@@ -6001,8 +8198,13 @@ union cvmx_gmxx_txx_pause_pkt_interval
 	struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1;
 	struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx;
 	struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s cn61xx;
 	struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xx;
 	struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xxp1;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s cn66xx;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xx;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xxp1;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s cnf71xx;
 };
 typedef union cvmx_gmxx_txx_pause_pkt_interval cvmx_gmxx_txx_pause_pkt_interval_t;
 
@@ -6031,12 +8233,10 @@ typedef union cvmx_gmxx_txx_pause_pkt_interval cvmx_gmxx_txx_pause_pkt_interval_
  * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
  * of the PAUSE packet (normally 64B).
  */
-union cvmx_gmxx_txx_pause_pkt_time
-{
+union cvmx_gmxx_txx_pause_pkt_time {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_pause_pkt_time_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_pause_pkt_time_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t time                         : 16; /**< The pause_time field placed in outbnd 802.3 pause
                                                          packets, HiGig2 messages, or CBFC pause packets.
@@ -6058,8 +8258,13 @@ union cvmx_gmxx_txx_pause_pkt_time
 	struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1;
 	struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx;
 	struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1;
+	struct cvmx_gmxx_txx_pause_pkt_time_s cn61xx;
 	struct cvmx_gmxx_txx_pause_pkt_time_s cn63xx;
 	struct cvmx_gmxx_txx_pause_pkt_time_s cn63xxp1;
+	struct cvmx_gmxx_txx_pause_pkt_time_s cn66xx;
+	struct cvmx_gmxx_txx_pause_pkt_time_s cn68xx;
+	struct cvmx_gmxx_txx_pause_pkt_time_s cn68xxp1;
+	struct cvmx_gmxx_txx_pause_pkt_time_s cnf71xx;
 };
 typedef union cvmx_gmxx_txx_pause_pkt_time cvmx_gmxx_txx_pause_pkt_time_t;
 
@@ -6069,12 +8274,10 @@ typedef union cvmx_gmxx_txx_pause_pkt_time cvmx_gmxx_txx_pause_pkt_time_t;
  * GMX_TX_PAUSE_TOGO = Packet TX Amount of time remaining to backpressure
  *
  */
-union cvmx_gmxx_txx_pause_togo
-{
+union cvmx_gmxx_txx_pause_togo {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_pause_togo_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_pause_togo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t msg_time                     : 16; /**< Amount of time remaining to backpressure
                                                          From the higig2 physical message pause timer
@@ -6087,9 +8290,8 @@ union cvmx_gmxx_txx_pause_togo
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
-	struct cvmx_gmxx_txx_pause_togo_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_pause_togo_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t time                         : 16; /**< Amount of time remaining to backpressure */
 #else
@@ -6107,8 +8309,13 @@ union cvmx_gmxx_txx_pause_togo
 	struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1;
 	struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx;
 	struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1;
+	struct cvmx_gmxx_txx_pause_togo_s     cn61xx;
 	struct cvmx_gmxx_txx_pause_togo_s     cn63xx;
 	struct cvmx_gmxx_txx_pause_togo_s     cn63xxp1;
+	struct cvmx_gmxx_txx_pause_togo_s     cn66xx;
+	struct cvmx_gmxx_txx_pause_togo_s     cn68xx;
+	struct cvmx_gmxx_txx_pause_togo_s     cn68xxp1;
+	struct cvmx_gmxx_txx_pause_togo_s     cnf71xx;
 };
 typedef union cvmx_gmxx_txx_pause_togo cvmx_gmxx_txx_pause_togo_t;
 
@@ -6118,12 +8325,10 @@ typedef union cvmx_gmxx_txx_pause_togo cvmx_gmxx_txx_pause_togo_t;
  * GMX_TX_PAUSE_ZERO = Packet TX Amount of time remaining to backpressure
  *
  */
-union cvmx_gmxx_txx_pause_zero
-{
+union cvmx_gmxx_txx_pause_zero {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_pause_zero_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_pause_zero_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t send                         : 1;  /**< When backpressure condition clear, send PAUSE
                                                          packet with pause_time of zero to enable the
@@ -6144,27 +8349,93 @@ union cvmx_gmxx_txx_pause_zero
 	struct cvmx_gmxx_txx_pause_zero_s     cn56xxp1;
 	struct cvmx_gmxx_txx_pause_zero_s     cn58xx;
 	struct cvmx_gmxx_txx_pause_zero_s     cn58xxp1;
+	struct cvmx_gmxx_txx_pause_zero_s     cn61xx;
 	struct cvmx_gmxx_txx_pause_zero_s     cn63xx;
 	struct cvmx_gmxx_txx_pause_zero_s     cn63xxp1;
+	struct cvmx_gmxx_txx_pause_zero_s     cn66xx;
+	struct cvmx_gmxx_txx_pause_zero_s     cn68xx;
+	struct cvmx_gmxx_txx_pause_zero_s     cn68xxp1;
+	struct cvmx_gmxx_txx_pause_zero_s     cnf71xx;
 };
 typedef union cvmx_gmxx_txx_pause_zero cvmx_gmxx_txx_pause_zero_t;
 
 /**
+ * cvmx_gmx#_tx#_pipe
+ */
+union cvmx_gmxx_txx_pipe {
+	uint64_t u64;
+	struct cvmx_gmxx_txx_pipe_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_33_63               : 31;
+	uint64_t ign_bp                       : 1;  /**< When set, GMX will not throttle the TX machines
+                                                         if the PIPE return FIFO fills up.
+                                                         IGN_BP should be clear in normal operation. */
+	uint64_t reserved_21_31               : 11;
+	uint64_t nump                         : 5;  /**< Number of pipes this port|channel supports.
+                                                         In SGMII mode, each port binds to one pipe.
+                                                         In XAUI/RXAUI mode, the port can bind upto 16
+                                                         consecutive pipes.
+                                                         SGMII      mode, NUMP = 0 or 1.
+                                                         XAUI/RXAUI mode, NUMP = 0 or 1-16.
+                                                         0 = Disabled */
+	uint64_t reserved_7_15                : 9;
+	uint64_t base                         : 7;  /**< When NUMP is non-zero, indicates the base pipe
+                                                         number this port|channel will accept.
+                                                         This port will accept pko packets from pipes in
+                                                         the range of:
+                                                           BASE .. (BASE+(NUMP-1))
+                                                         BASE and NUMP must be constrained such that
+                                                           1) BASE+(NUMP-1) < 127
+                                                           2) Each used PKO pipe must map to exactly
+                                                              one port|channel
+                                                           3) The pipe ranges must be consistent with
+                                                              the PKO configuration. */
+#else
+	uint64_t base                         : 7;
+	uint64_t reserved_7_15                : 9;
+	uint64_t nump                         : 5;
+	uint64_t reserved_21_31               : 11;
+	uint64_t ign_bp                       : 1;
+	uint64_t reserved_33_63               : 31;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_pipe_s           cn68xx;
+	struct cvmx_gmxx_txx_pipe_s           cn68xxp1;
+};
+typedef union cvmx_gmxx_txx_pipe cvmx_gmxx_txx_pipe_t;
+
+/**
  * cvmx_gmx#_tx#_sgmii_ctl
  */
-union cvmx_gmxx_txx_sgmii_ctl
-{
+union cvmx_gmxx_txx_sgmii_ctl {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_sgmii_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_sgmii_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t align                        : 1;  /**< Align the transmission to even cycles
+
+                                                         Recommended value is:
+                                                            ALIGN = !GMX_TX_APPEND[PREAMBLE]
+
+                                                         (See the Transmit Conversion to Code groups
+                                                          section in the SGMII Interface chapter of the
+                                                          HRM for a complete discussion)
+
                                                          0 = Data can be sent on any cycle
-                                                             Possible to for the TX PCS machine to drop
-                                                             first byte of preamble
-                                                         1 = Data will only be sent on even cycles
-                                                             There will be no loss of data
+                                                             In this mode, the interface will function at
+                                                             maximum bandwidth. It is possible to for the
+                                                             TX PCS machine to drop first byte of the TX
+                                                             frame.  When GMX_TX_APPEND[PREAMBLE] is set,
+                                                             the first byte will be a preamble byte which
+                                                             can be dropped to compensate for an extended
+                                                             IPG.
+
+                                                         1 = Data will only be sent on even cycles.
+                                                             In this mode, there can be bandwidth
+                                                             implications when sending odd-byte packets as
+                                                             the IPG can extend an extra cycle.
+                                                             There will be no loss of data.
+
                                                          (SGMII/1000Base-X only) */
 #else
 	uint64_t align                        : 1;
@@ -6175,8 +8446,13 @@ union cvmx_gmxx_txx_sgmii_ctl
 	struct cvmx_gmxx_txx_sgmii_ctl_s      cn52xxp1;
 	struct cvmx_gmxx_txx_sgmii_ctl_s      cn56xx;
 	struct cvmx_gmxx_txx_sgmii_ctl_s      cn56xxp1;
+	struct cvmx_gmxx_txx_sgmii_ctl_s      cn61xx;
 	struct cvmx_gmxx_txx_sgmii_ctl_s      cn63xx;
 	struct cvmx_gmxx_txx_sgmii_ctl_s      cn63xxp1;
+	struct cvmx_gmxx_txx_sgmii_ctl_s      cn66xx;
+	struct cvmx_gmxx_txx_sgmii_ctl_s      cn68xx;
+	struct cvmx_gmxx_txx_sgmii_ctl_s      cn68xxp1;
+	struct cvmx_gmxx_txx_sgmii_ctl_s      cnf71xx;
 };
 typedef union cvmx_gmxx_txx_sgmii_ctl cvmx_gmxx_txx_sgmii_ctl_t;
 
@@ -6186,12 +8462,10 @@ typedef union cvmx_gmxx_txx_sgmii_ctl cvmx_gmxx_txx_sgmii_ctl_t;
  * GMX_TX_SLOT = Packet TX Slottime Counter
  *
  */
-union cvmx_gmxx_txx_slot
-{
+union cvmx_gmxx_txx_slot {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_slot_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_slot_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t slot                         : 10; /**< Slottime (refer to 802.3 to set correctly)
                                                          10/100Mbs: 0x40
@@ -6213,8 +8487,13 @@ union cvmx_gmxx_txx_slot
 	struct cvmx_gmxx_txx_slot_s           cn56xxp1;
 	struct cvmx_gmxx_txx_slot_s           cn58xx;
 	struct cvmx_gmxx_txx_slot_s           cn58xxp1;
+	struct cvmx_gmxx_txx_slot_s           cn61xx;
 	struct cvmx_gmxx_txx_slot_s           cn63xx;
 	struct cvmx_gmxx_txx_slot_s           cn63xxp1;
+	struct cvmx_gmxx_txx_slot_s           cn66xx;
+	struct cvmx_gmxx_txx_slot_s           cn68xx;
+	struct cvmx_gmxx_txx_slot_s           cn68xxp1;
+	struct cvmx_gmxx_txx_slot_s           cnf71xx;
 };
 typedef union cvmx_gmxx_txx_slot cvmx_gmxx_txx_slot_t;
 
@@ -6224,12 +8503,10 @@ typedef union cvmx_gmxx_txx_slot cvmx_gmxx_txx_slot_t;
  * GMX_TX_SOFT_PAUSE = Packet TX Software Pause
  *
  */
-union cvmx_gmxx_txx_soft_pause
-{
+union cvmx_gmxx_txx_soft_pause {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_soft_pause_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_soft_pause_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t time                         : 16; /**< Back off the TX bus for (TIME*512) bit-times */
 #else
@@ -6248,8 +8525,13 @@ union cvmx_gmxx_txx_soft_pause
 	struct cvmx_gmxx_txx_soft_pause_s     cn56xxp1;
 	struct cvmx_gmxx_txx_soft_pause_s     cn58xx;
 	struct cvmx_gmxx_txx_soft_pause_s     cn58xxp1;
+	struct cvmx_gmxx_txx_soft_pause_s     cn61xx;
 	struct cvmx_gmxx_txx_soft_pause_s     cn63xx;
 	struct cvmx_gmxx_txx_soft_pause_s     cn63xxp1;
+	struct cvmx_gmxx_txx_soft_pause_s     cn66xx;
+	struct cvmx_gmxx_txx_soft_pause_s     cn68xx;
+	struct cvmx_gmxx_txx_soft_pause_s     cn68xxp1;
+	struct cvmx_gmxx_txx_soft_pause_s     cnf71xx;
 };
 typedef union cvmx_gmxx_txx_soft_pause cvmx_gmxx_txx_soft_pause_t;
 
@@ -6263,12 +8545,10 @@ typedef union cvmx_gmxx_txx_soft_pause cvmx_gmxx_txx_soft_pause_t;
  * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
  * - Counters will wrap
  */
-union cvmx_gmxx_txx_stat0
-{
+union cvmx_gmxx_txx_stat0 {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_stat0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_stat0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t xsdef                        : 32; /**< Number of packets dropped (never successfully
                                                          sent) due to excessive deferal
                                                          (SGMII/1000Base-X half-duplex only) */
@@ -6292,8 +8572,13 @@ union cvmx_gmxx_txx_stat0
 	struct cvmx_gmxx_txx_stat0_s          cn56xxp1;
 	struct cvmx_gmxx_txx_stat0_s          cn58xx;
 	struct cvmx_gmxx_txx_stat0_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat0_s          cn61xx;
 	struct cvmx_gmxx_txx_stat0_s          cn63xx;
 	struct cvmx_gmxx_txx_stat0_s          cn63xxp1;
+	struct cvmx_gmxx_txx_stat0_s          cn66xx;
+	struct cvmx_gmxx_txx_stat0_s          cn68xx;
+	struct cvmx_gmxx_txx_stat0_s          cn68xxp1;
+	struct cvmx_gmxx_txx_stat0_s          cnf71xx;
 };
 typedef union cvmx_gmxx_txx_stat0 cvmx_gmxx_txx_stat0_t;
 
@@ -6307,12 +8592,10 @@ typedef union cvmx_gmxx_txx_stat0 cvmx_gmxx_txx_stat0_t;
  * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
  * - Counters will wrap
  */
-union cvmx_gmxx_txx_stat1
-{
+union cvmx_gmxx_txx_stat1 {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_stat1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_stat1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t scol                         : 32; /**< Number of packets sent with a single collision
                                                          (SGMII/1000Base-X half-duplex only) */
 	uint64_t mcol                         : 32; /**< Number of packets sent with multiple collisions
@@ -6334,8 +8617,13 @@ union cvmx_gmxx_txx_stat1
 	struct cvmx_gmxx_txx_stat1_s          cn56xxp1;
 	struct cvmx_gmxx_txx_stat1_s          cn58xx;
 	struct cvmx_gmxx_txx_stat1_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat1_s          cn61xx;
 	struct cvmx_gmxx_txx_stat1_s          cn63xx;
 	struct cvmx_gmxx_txx_stat1_s          cn63xxp1;
+	struct cvmx_gmxx_txx_stat1_s          cn66xx;
+	struct cvmx_gmxx_txx_stat1_s          cn68xx;
+	struct cvmx_gmxx_txx_stat1_s          cn68xxp1;
+	struct cvmx_gmxx_txx_stat1_s          cnf71xx;
 };
 typedef union cvmx_gmxx_txx_stat1 cvmx_gmxx_txx_stat1_t;
 
@@ -6352,12 +8640,10 @@ typedef union cvmx_gmxx_txx_stat1 cvmx_gmxx_txx_stat1_t;
  * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
  * - Counters will wrap
  */
-union cvmx_gmxx_txx_stat2
-{
+union cvmx_gmxx_txx_stat2 {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_stat2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_stat2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t octs                         : 48; /**< Number of total octets sent on the interface.
                                                          Does not count octets from frames that were
@@ -6378,8 +8664,13 @@ union cvmx_gmxx_txx_stat2
 	struct cvmx_gmxx_txx_stat2_s          cn56xxp1;
 	struct cvmx_gmxx_txx_stat2_s          cn58xx;
 	struct cvmx_gmxx_txx_stat2_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat2_s          cn61xx;
 	struct cvmx_gmxx_txx_stat2_s          cn63xx;
 	struct cvmx_gmxx_txx_stat2_s          cn63xxp1;
+	struct cvmx_gmxx_txx_stat2_s          cn66xx;
+	struct cvmx_gmxx_txx_stat2_s          cn68xx;
+	struct cvmx_gmxx_txx_stat2_s          cn68xxp1;
+	struct cvmx_gmxx_txx_stat2_s          cnf71xx;
 };
 typedef union cvmx_gmxx_txx_stat2 cvmx_gmxx_txx_stat2_t;
 
@@ -6393,12 +8684,10 @@ typedef union cvmx_gmxx_txx_stat2 cvmx_gmxx_txx_stat2_t;
  * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
  * - Counters will wrap
  */
-union cvmx_gmxx_txx_stat3
-{
+union cvmx_gmxx_txx_stat3 {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_stat3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_stat3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t pkts                         : 32; /**< Number of total frames sent on the interface.
                                                          Does not count frames that were truncated due to
@@ -6419,8 +8708,13 @@ union cvmx_gmxx_txx_stat3
 	struct cvmx_gmxx_txx_stat3_s          cn56xxp1;
 	struct cvmx_gmxx_txx_stat3_s          cn58xx;
 	struct cvmx_gmxx_txx_stat3_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat3_s          cn61xx;
 	struct cvmx_gmxx_txx_stat3_s          cn63xx;
 	struct cvmx_gmxx_txx_stat3_s          cn63xxp1;
+	struct cvmx_gmxx_txx_stat3_s          cn66xx;
+	struct cvmx_gmxx_txx_stat3_s          cn68xx;
+	struct cvmx_gmxx_txx_stat3_s          cn68xxp1;
+	struct cvmx_gmxx_txx_stat3_s          cnf71xx;
 };
 typedef union cvmx_gmxx_txx_stat3 cvmx_gmxx_txx_stat3_t;
 
@@ -6437,12 +8731,10 @@ typedef union cvmx_gmxx_txx_stat3 cvmx_gmxx_txx_stat3_t;
  * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
  * - Counters will wrap
  */
-union cvmx_gmxx_txx_stat4
-{
+union cvmx_gmxx_txx_stat4 {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_stat4_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_stat4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t hist1                        : 32; /**< Number of packets sent with an octet count of 64. */
 	uint64_t hist0                        : 32; /**< Number of packets sent with an octet count
                                                          of < 64. */
@@ -6462,8 +8754,13 @@ union cvmx_gmxx_txx_stat4
 	struct cvmx_gmxx_txx_stat4_s          cn56xxp1;
 	struct cvmx_gmxx_txx_stat4_s          cn58xx;
 	struct cvmx_gmxx_txx_stat4_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat4_s          cn61xx;
 	struct cvmx_gmxx_txx_stat4_s          cn63xx;
 	struct cvmx_gmxx_txx_stat4_s          cn63xxp1;
+	struct cvmx_gmxx_txx_stat4_s          cn66xx;
+	struct cvmx_gmxx_txx_stat4_s          cn68xx;
+	struct cvmx_gmxx_txx_stat4_s          cn68xxp1;
+	struct cvmx_gmxx_txx_stat4_s          cnf71xx;
 };
 typedef union cvmx_gmxx_txx_stat4 cvmx_gmxx_txx_stat4_t;
 
@@ -6480,12 +8777,10 @@ typedef union cvmx_gmxx_txx_stat4 cvmx_gmxx_txx_stat4_t;
  * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
  * - Counters will wrap
  */
-union cvmx_gmxx_txx_stat5
-{
+union cvmx_gmxx_txx_stat5 {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_stat5_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_stat5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t hist3                        : 32; /**< Number of packets sent with an octet count of
                                                          128 - 255. */
 	uint64_t hist2                        : 32; /**< Number of packets sent with an octet count of
@@ -6506,8 +8801,13 @@ union cvmx_gmxx_txx_stat5
 	struct cvmx_gmxx_txx_stat5_s          cn56xxp1;
 	struct cvmx_gmxx_txx_stat5_s          cn58xx;
 	struct cvmx_gmxx_txx_stat5_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat5_s          cn61xx;
 	struct cvmx_gmxx_txx_stat5_s          cn63xx;
 	struct cvmx_gmxx_txx_stat5_s          cn63xxp1;
+	struct cvmx_gmxx_txx_stat5_s          cn66xx;
+	struct cvmx_gmxx_txx_stat5_s          cn68xx;
+	struct cvmx_gmxx_txx_stat5_s          cn68xxp1;
+	struct cvmx_gmxx_txx_stat5_s          cnf71xx;
 };
 typedef union cvmx_gmxx_txx_stat5 cvmx_gmxx_txx_stat5_t;
 
@@ -6524,12 +8824,10 @@ typedef union cvmx_gmxx_txx_stat5 cvmx_gmxx_txx_stat5_t;
  * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
  * - Counters will wrap
  */
-union cvmx_gmxx_txx_stat6
-{
+union cvmx_gmxx_txx_stat6 {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_stat6_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_stat6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t hist5                        : 32; /**< Number of packets sent with an octet count of
                                                          512 - 1023. */
 	uint64_t hist4                        : 32; /**< Number of packets sent with an octet count of
@@ -6550,8 +8848,13 @@ union cvmx_gmxx_txx_stat6
 	struct cvmx_gmxx_txx_stat6_s          cn56xxp1;
 	struct cvmx_gmxx_txx_stat6_s          cn58xx;
 	struct cvmx_gmxx_txx_stat6_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat6_s          cn61xx;
 	struct cvmx_gmxx_txx_stat6_s          cn63xx;
 	struct cvmx_gmxx_txx_stat6_s          cn63xxp1;
+	struct cvmx_gmxx_txx_stat6_s          cn66xx;
+	struct cvmx_gmxx_txx_stat6_s          cn68xx;
+	struct cvmx_gmxx_txx_stat6_s          cn68xxp1;
+	struct cvmx_gmxx_txx_stat6_s          cnf71xx;
 };
 typedef union cvmx_gmxx_txx_stat6 cvmx_gmxx_txx_stat6_t;
 
@@ -6568,12 +8871,10 @@ typedef union cvmx_gmxx_txx_stat6 cvmx_gmxx_txx_stat6_t;
  * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
  * - Counters will wrap
  */
-union cvmx_gmxx_txx_stat7
-{
+union cvmx_gmxx_txx_stat7 {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_stat7_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_stat7_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t hist7                        : 32; /**< Number of packets sent with an octet count
                                                          of > 1518. */
 	uint64_t hist6                        : 32; /**< Number of packets sent with an octet count of
@@ -6594,8 +8895,13 @@ union cvmx_gmxx_txx_stat7
 	struct cvmx_gmxx_txx_stat7_s          cn56xxp1;
 	struct cvmx_gmxx_txx_stat7_s          cn58xx;
 	struct cvmx_gmxx_txx_stat7_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat7_s          cn61xx;
 	struct cvmx_gmxx_txx_stat7_s          cn63xx;
 	struct cvmx_gmxx_txx_stat7_s          cn63xxp1;
+	struct cvmx_gmxx_txx_stat7_s          cn66xx;
+	struct cvmx_gmxx_txx_stat7_s          cn68xx;
+	struct cvmx_gmxx_txx_stat7_s          cn68xxp1;
+	struct cvmx_gmxx_txx_stat7_s          cnf71xx;
 };
 typedef union cvmx_gmxx_txx_stat7 cvmx_gmxx_txx_stat7_t;
 
@@ -6614,12 +8920,10 @@ typedef union cvmx_gmxx_txx_stat7 cvmx_gmxx_txx_stat7_t;
  *   before the L2 header, then the MCST and BCST counters may not reflect
  *   reality and should be ignored by software.
  */
-union cvmx_gmxx_txx_stat8
-{
+union cvmx_gmxx_txx_stat8 {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_stat8_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_stat8_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t mcst                         : 32; /**< Number of packets sent to multicast DMAC.
                                                          Does not include BCST packets. */
 	uint64_t bcst                         : 32; /**< Number of packets sent to broadcast DMAC.
@@ -6640,8 +8944,13 @@ union cvmx_gmxx_txx_stat8
 	struct cvmx_gmxx_txx_stat8_s          cn56xxp1;
 	struct cvmx_gmxx_txx_stat8_s          cn58xx;
 	struct cvmx_gmxx_txx_stat8_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat8_s          cn61xx;
 	struct cvmx_gmxx_txx_stat8_s          cn63xx;
 	struct cvmx_gmxx_txx_stat8_s          cn63xxp1;
+	struct cvmx_gmxx_txx_stat8_s          cn66xx;
+	struct cvmx_gmxx_txx_stat8_s          cn68xx;
+	struct cvmx_gmxx_txx_stat8_s          cn68xxp1;
+	struct cvmx_gmxx_txx_stat8_s          cnf71xx;
 };
 typedef union cvmx_gmxx_txx_stat8 cvmx_gmxx_txx_stat8_t;
 
@@ -6655,16 +8964,17 @@ typedef union cvmx_gmxx_txx_stat8 cvmx_gmxx_txx_stat8_t;
  * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
  * - Counters will wrap
  */
-union cvmx_gmxx_txx_stat9
-{
+union cvmx_gmxx_txx_stat9 {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_stat9_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_stat9_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t undflw                       : 32; /**< Number of underflow packets */
 	uint64_t ctl                          : 32; /**< Number of Control packets (PAUSE flow control)
                                                          generated by GMX.  It does not include control
-                                                         packets forwarded or generated by the PP's. */
+                                                         packets forwarded or generated by the PP's.
+                                                         CTL will count the number of generated PFC frames.
+                                                         CTL will not track the number of generated HG2
+                                                         messages. */
 #else
 	uint64_t ctl                          : 32;
 	uint64_t undflw                       : 32;
@@ -6681,8 +8991,13 @@ union cvmx_gmxx_txx_stat9
 	struct cvmx_gmxx_txx_stat9_s          cn56xxp1;
 	struct cvmx_gmxx_txx_stat9_s          cn58xx;
 	struct cvmx_gmxx_txx_stat9_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat9_s          cn61xx;
 	struct cvmx_gmxx_txx_stat9_s          cn63xx;
 	struct cvmx_gmxx_txx_stat9_s          cn63xxp1;
+	struct cvmx_gmxx_txx_stat9_s          cn66xx;
+	struct cvmx_gmxx_txx_stat9_s          cn68xx;
+	struct cvmx_gmxx_txx_stat9_s          cn68xxp1;
+	struct cvmx_gmxx_txx_stat9_s          cnf71xx;
 };
 typedef union cvmx_gmxx_txx_stat9 cvmx_gmxx_txx_stat9_t;
 
@@ -6692,12 +9007,10 @@ typedef union cvmx_gmxx_txx_stat9 cvmx_gmxx_txx_stat9_t;
  * GMX_TX_STATS_CTL = TX Stats Control register
  *
  */
-union cvmx_gmxx_txx_stats_ctl
-{
+union cvmx_gmxx_txx_stats_ctl {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_stats_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_stats_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t rd_clr                       : 1;  /**< Stats registers will clear on reads */
 #else
@@ -6716,8 +9029,13 @@ union cvmx_gmxx_txx_stats_ctl
 	struct cvmx_gmxx_txx_stats_ctl_s      cn56xxp1;
 	struct cvmx_gmxx_txx_stats_ctl_s      cn58xx;
 	struct cvmx_gmxx_txx_stats_ctl_s      cn58xxp1;
+	struct cvmx_gmxx_txx_stats_ctl_s      cn61xx;
 	struct cvmx_gmxx_txx_stats_ctl_s      cn63xx;
 	struct cvmx_gmxx_txx_stats_ctl_s      cn63xxp1;
+	struct cvmx_gmxx_txx_stats_ctl_s      cn66xx;
+	struct cvmx_gmxx_txx_stats_ctl_s      cn68xx;
+	struct cvmx_gmxx_txx_stats_ctl_s      cn68xxp1;
+	struct cvmx_gmxx_txx_stats_ctl_s      cnf71xx;
 };
 typedef union cvmx_gmxx_txx_stats_ctl cvmx_gmxx_txx_stats_ctl_t;
 
@@ -6733,14 +9051,12 @@ typedef union cvmx_gmxx_txx_stats_ctl cvmx_gmxx_txx_stats_ctl_t;
  * In XAUI mode, prt0 is used for checking.  Since XAUI mode uses a single TX FIFO and is higher data rate, recommended value is 0x100.
  *
  */
-union cvmx_gmxx_txx_thresh
-{
+union cvmx_gmxx_txx_thresh {
 	uint64_t u64;
-	struct cvmx_gmxx_txx_thresh_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_9_63                : 55;
-	uint64_t cnt                          : 9;  /**< Number of 16B ticks to accumulate in the TX FIFO
+	struct cvmx_gmxx_txx_thresh_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t cnt                          : 10; /**< Number of 16B ticks to accumulate in the TX FIFO
                                                          before sending on the packet interface
                                                          This register should be large enough to prevent
                                                          underflow on the packet interface and must never
@@ -6750,13 +9066,12 @@ union cvmx_gmxx_txx_thresh
                                                           GMX_TX_PRTS==2  :  CNT MAX = 0x080
                                                           GMX_TX_PRTS==3,4:  CNT MAX = 0x040 */
 #else
-	uint64_t cnt                          : 9;
-	uint64_t reserved_9_63                : 55;
+	uint64_t cnt                          : 10;
+	uint64_t reserved_10_63               : 54;
 #endif
 	} s;
-	struct cvmx_gmxx_txx_thresh_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_txx_thresh_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t cnt                          : 7;  /**< Number of 16B ticks to accumulate in the TX FIFO
                                                          before sending on the RGMII interface
@@ -6770,17 +9085,39 @@ union cvmx_gmxx_txx_thresh
 #endif
 	} cn30xx;
 	struct cvmx_gmxx_txx_thresh_cn30xx    cn31xx;
-	struct cvmx_gmxx_txx_thresh_s         cn38xx;
-	struct cvmx_gmxx_txx_thresh_s         cn38xxp2;
+	struct cvmx_gmxx_txx_thresh_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_9_63                : 55;
+	uint64_t cnt                          : 9;  /**< Number of 16B ticks to accumulate in the TX FIFO
+                                                          before sending on the RGMII interface
+                                                          This register should be large enough to prevent
+                                                          underflow on the RGMII interface and must never
+                                                          be set to zero.  This register cannot exceed the
+                                                          the TX FIFO depth which is...
+                                                           GMX_TX_PRTS==0,1:  CNT MAX = 0x100
+                                                           GMX_TX_PRTS==2  :  CNT MAX = 0x080
+                                                           GMX_TX_PRTS==3,4:  CNT MAX = 0x040
+                                                         (PASS2 expands from 6 to 9 bits) */
+#else
+	uint64_t cnt                          : 9;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn38xx;
+	struct cvmx_gmxx_txx_thresh_cn38xx    cn38xxp2;
 	struct cvmx_gmxx_txx_thresh_cn30xx    cn50xx;
-	struct cvmx_gmxx_txx_thresh_s         cn52xx;
-	struct cvmx_gmxx_txx_thresh_s         cn52xxp1;
-	struct cvmx_gmxx_txx_thresh_s         cn56xx;
-	struct cvmx_gmxx_txx_thresh_s         cn56xxp1;
-	struct cvmx_gmxx_txx_thresh_s         cn58xx;
-	struct cvmx_gmxx_txx_thresh_s         cn58xxp1;
-	struct cvmx_gmxx_txx_thresh_s         cn63xx;
-	struct cvmx_gmxx_txx_thresh_s         cn63xxp1;
+	struct cvmx_gmxx_txx_thresh_cn38xx    cn52xx;
+	struct cvmx_gmxx_txx_thresh_cn38xx    cn52xxp1;
+	struct cvmx_gmxx_txx_thresh_cn38xx    cn56xx;
+	struct cvmx_gmxx_txx_thresh_cn38xx    cn56xxp1;
+	struct cvmx_gmxx_txx_thresh_cn38xx    cn58xx;
+	struct cvmx_gmxx_txx_thresh_cn38xx    cn58xxp1;
+	struct cvmx_gmxx_txx_thresh_cn38xx    cn61xx;
+	struct cvmx_gmxx_txx_thresh_cn38xx    cn63xx;
+	struct cvmx_gmxx_txx_thresh_cn38xx    cn63xxp1;
+	struct cvmx_gmxx_txx_thresh_cn38xx    cn66xx;
+	struct cvmx_gmxx_txx_thresh_s         cn68xx;
+	struct cvmx_gmxx_txx_thresh_s         cn68xxp1;
+	struct cvmx_gmxx_txx_thresh_cn38xx    cnf71xx;
 };
 typedef union cvmx_gmxx_txx_thresh cvmx_gmxx_txx_thresh_t;
 
@@ -6794,12 +9131,10 @@ typedef union cvmx_gmxx_txx_thresh cvmx_gmxx_txx_thresh_t;
  * In XAUI mode, only the lsb (corresponding to port0) of BP is used.
  *
  */
-union cvmx_gmxx_tx_bp
-{
+union cvmx_gmxx_tx_bp {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_bp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t bp                           : 4;  /**< Per port BackPressure status
                                                          0=Port is available
@@ -6809,9 +9144,8 @@ union cvmx_gmxx_tx_bp
 	uint64_t reserved_4_63                : 60;
 #endif
 	} s;
-	struct cvmx_gmxx_tx_bp_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_bp_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t bp                           : 3;  /**< Per port BackPressure status
                                                          0=Port is available
@@ -6831,8 +9165,23 @@ union cvmx_gmxx_tx_bp
 	struct cvmx_gmxx_tx_bp_s              cn56xxp1;
 	struct cvmx_gmxx_tx_bp_s              cn58xx;
 	struct cvmx_gmxx_tx_bp_s              cn58xxp1;
+	struct cvmx_gmxx_tx_bp_s              cn61xx;
 	struct cvmx_gmxx_tx_bp_s              cn63xx;
 	struct cvmx_gmxx_tx_bp_s              cn63xxp1;
+	struct cvmx_gmxx_tx_bp_s              cn66xx;
+	struct cvmx_gmxx_tx_bp_s              cn68xx;
+	struct cvmx_gmxx_tx_bp_s              cn68xxp1;
+	struct cvmx_gmxx_tx_bp_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_2_63                : 62;
+	uint64_t bp                           : 2;  /**< Per port BackPressure status
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+#else
+	uint64_t bp                           : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_gmxx_tx_bp cvmx_gmxx_tx_bp_t;
 
@@ -6842,12 +9191,10 @@ typedef union cvmx_gmxx_tx_bp cvmx_gmxx_tx_bp_t;
  * GMX_TX_CLK_MSK = GMX Clock Select
  *
  */
-union cvmx_gmxx_tx_clk_mskx
-{
+union cvmx_gmxx_tx_clk_mskx {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_clk_mskx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_clk_mskx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t msk                          : 1;  /**< Write this bit to a 1 when switching clks */
 #else
@@ -6866,12 +9213,10 @@ typedef union cvmx_gmxx_tx_clk_mskx cvmx_gmxx_tx_clk_mskx_t;
  * GMX_TX_COL_ATTEMPT = Packet TX collision attempts before dropping frame
  *
  */
-union cvmx_gmxx_tx_col_attempt
-{
+union cvmx_gmxx_tx_col_attempt {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_col_attempt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_col_attempt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t limit                        : 5;  /**< Collision Attempts
                                                          (SGMII/1000Base-X half-duplex only) */
@@ -6891,8 +9236,13 @@ union cvmx_gmxx_tx_col_attempt
 	struct cvmx_gmxx_tx_col_attempt_s     cn56xxp1;
 	struct cvmx_gmxx_tx_col_attempt_s     cn58xx;
 	struct cvmx_gmxx_tx_col_attempt_s     cn58xxp1;
+	struct cvmx_gmxx_tx_col_attempt_s     cn61xx;
 	struct cvmx_gmxx_tx_col_attempt_s     cn63xx;
 	struct cvmx_gmxx_tx_col_attempt_s     cn63xxp1;
+	struct cvmx_gmxx_tx_col_attempt_s     cn66xx;
+	struct cvmx_gmxx_tx_col_attempt_s     cn68xx;
+	struct cvmx_gmxx_tx_col_attempt_s     cn68xxp1;
+	struct cvmx_gmxx_tx_col_attempt_s     cnf71xx;
 };
 typedef union cvmx_gmxx_tx_col_attempt cvmx_gmxx_tx_col_attempt_t;
 
@@ -6911,12 +9261,10 @@ typedef union cvmx_gmxx_tx_col_attempt cvmx_gmxx_tx_col_attempt_t;
  * value is 0xeeeeeeee for SGMII/1000Base-X and 4 bytes of the error
  * propagation code in XAUI mode.
  */
-union cvmx_gmxx_tx_corrupt
-{
+union cvmx_gmxx_tx_corrupt {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_corrupt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_corrupt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t corrupt                      : 4;  /**< Per port error propagation
                                                          0=Never corrupt packets
@@ -6926,9 +9274,8 @@ union cvmx_gmxx_tx_corrupt
 	uint64_t reserved_4_63                : 60;
 #endif
 	} s;
-	struct cvmx_gmxx_tx_corrupt_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_corrupt_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t corrupt                      : 3;  /**< Per port error propagation
                                                          0=Never corrupt packets
@@ -6948,8 +9295,23 @@ union cvmx_gmxx_tx_corrupt
 	struct cvmx_gmxx_tx_corrupt_s         cn56xxp1;
 	struct cvmx_gmxx_tx_corrupt_s         cn58xx;
 	struct cvmx_gmxx_tx_corrupt_s         cn58xxp1;
+	struct cvmx_gmxx_tx_corrupt_s         cn61xx;
 	struct cvmx_gmxx_tx_corrupt_s         cn63xx;
 	struct cvmx_gmxx_tx_corrupt_s         cn63xxp1;
+	struct cvmx_gmxx_tx_corrupt_s         cn66xx;
+	struct cvmx_gmxx_tx_corrupt_s         cn68xx;
+	struct cvmx_gmxx_tx_corrupt_s         cn68xxp1;
+	struct cvmx_gmxx_tx_corrupt_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_2_63                : 62;
+	uint64_t corrupt                      : 2;  /**< Per port error propagation
+                                                         0=Never corrupt packets
+                                                         1=Corrupt packets with ERR */
+#else
+	uint64_t corrupt                      : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_gmxx_tx_corrupt cvmx_gmxx_tx_corrupt_t;
 
@@ -6963,12 +9325,10 @@ typedef union cvmx_gmxx_tx_corrupt cvmx_gmxx_tx_corrupt_t;
  * GMX(0)_TX_HG2_REG2, it will exhibit write 1 to clear behavior.
  * For reads, either address will return the $GMX(0)_TX_HG2_REG1 values.
  */
-union cvmx_gmxx_tx_hg2_reg1
-{
+union cvmx_gmxx_tx_hg2_reg1 {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_hg2_reg1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_hg2_reg1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t tx_xof                       : 16; /**< TX HiGig2 message for logical link pause when any
                                                          bit value changes
@@ -6983,8 +9343,13 @@ union cvmx_gmxx_tx_hg2_reg1
 	struct cvmx_gmxx_tx_hg2_reg1_s        cn52xx;
 	struct cvmx_gmxx_tx_hg2_reg1_s        cn52xxp1;
 	struct cvmx_gmxx_tx_hg2_reg1_s        cn56xx;
+	struct cvmx_gmxx_tx_hg2_reg1_s        cn61xx;
 	struct cvmx_gmxx_tx_hg2_reg1_s        cn63xx;
 	struct cvmx_gmxx_tx_hg2_reg1_s        cn63xxp1;
+	struct cvmx_gmxx_tx_hg2_reg1_s        cn66xx;
+	struct cvmx_gmxx_tx_hg2_reg1_s        cn68xx;
+	struct cvmx_gmxx_tx_hg2_reg1_s        cn68xxp1;
+	struct cvmx_gmxx_tx_hg2_reg1_s        cnf71xx;
 };
 typedef union cvmx_gmxx_tx_hg2_reg1 cvmx_gmxx_tx_hg2_reg1_t;
 
@@ -6998,12 +9363,10 @@ typedef union cvmx_gmxx_tx_hg2_reg1 cvmx_gmxx_tx_hg2_reg1_t;
  * GMX(0)_TX_HG2_REG2, it will exhibit write 1 to clear behavior.
  * For reads, either address will return the $GMX(0)_TX_HG2_REG1 values.
  */
-union cvmx_gmxx_tx_hg2_reg2
-{
+union cvmx_gmxx_tx_hg2_reg2 {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_hg2_reg2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_hg2_reg2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t tx_xon                       : 16; /**< TX HiGig2 message for logical link pause when any
                                                          bit value changes
@@ -7018,8 +9381,13 @@ union cvmx_gmxx_tx_hg2_reg2
 	struct cvmx_gmxx_tx_hg2_reg2_s        cn52xx;
 	struct cvmx_gmxx_tx_hg2_reg2_s        cn52xxp1;
 	struct cvmx_gmxx_tx_hg2_reg2_s        cn56xx;
+	struct cvmx_gmxx_tx_hg2_reg2_s        cn61xx;
 	struct cvmx_gmxx_tx_hg2_reg2_s        cn63xx;
 	struct cvmx_gmxx_tx_hg2_reg2_s        cn63xxp1;
+	struct cvmx_gmxx_tx_hg2_reg2_s        cn66xx;
+	struct cvmx_gmxx_tx_hg2_reg2_s        cn68xx;
+	struct cvmx_gmxx_tx_hg2_reg2_s        cn68xxp1;
+	struct cvmx_gmxx_tx_hg2_reg2_s        cnf71xx;
 };
 typedef union cvmx_gmxx_tx_hg2_reg2 cvmx_gmxx_tx_hg2_reg2_t;
 
@@ -7046,12 +9414,10 @@ typedef union cvmx_gmxx_tx_hg2_reg2 cvmx_gmxx_tx_hg2_reg2_t;
  * For all other systems, IFG1 and IFG2 can be any value in the range of
  * 1-15.  Allowing for a total possible IFG sum of 2-30.
  */
-union cvmx_gmxx_tx_ifg
-{
+union cvmx_gmxx_tx_ifg {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_ifg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_ifg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t ifg2                         : 4;  /**< 1/3 of the interframe gap timing (in IFG2*8 bits)
                                                          If CRS is detected during IFG2, then the
@@ -7078,8 +9444,13 @@ union cvmx_gmxx_tx_ifg
 	struct cvmx_gmxx_tx_ifg_s             cn56xxp1;
 	struct cvmx_gmxx_tx_ifg_s             cn58xx;
 	struct cvmx_gmxx_tx_ifg_s             cn58xxp1;
+	struct cvmx_gmxx_tx_ifg_s             cn61xx;
 	struct cvmx_gmxx_tx_ifg_s             cn63xx;
 	struct cvmx_gmxx_tx_ifg_s             cn63xxp1;
+	struct cvmx_gmxx_tx_ifg_s             cn66xx;
+	struct cvmx_gmxx_tx_ifg_s             cn68xx;
+	struct cvmx_gmxx_tx_ifg_s             cn68xxp1;
+	struct cvmx_gmxx_tx_ifg_s             cnf71xx;
 };
 typedef union cvmx_gmxx_tx_ifg cvmx_gmxx_tx_ifg_t;
 
@@ -7093,13 +9464,14 @@ typedef union cvmx_gmxx_tx_ifg cvmx_gmxx_tx_ifg_t;
  * In XAUI mode, only the lsb (corresponding to port0) of UNDFLW is used.
  *
  */
-union cvmx_gmxx_tx_int_en
-{
+union cvmx_gmxx_tx_int_en {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_int_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_24_63               : 40;
+	struct cvmx_gmxx_tx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_25_63               : 39;
+	uint64_t xchange                      : 1;  /**< XAUI link status changed - this denotes a change
+                                                         to GMX_RX_XAUI_CTL[STATUS]
+                                                         (XAUI mode only) */
 	uint64_t ptp_lost                     : 4;  /**< A packet with a PTP request was not able to be
                                                          sent due to XSCOL */
 	uint64_t late_col                     : 4;  /**< TX Late Collision
@@ -7110,23 +9482,23 @@ union cvmx_gmxx_tx_int_en
                                                          (SGMII/1000Base-X half-duplex only) */
 	uint64_t reserved_6_7                 : 2;
 	uint64_t undflw                       : 4;  /**< TX Underflow */
-	uint64_t ncb_nxa                      : 1;  /**< Port address out-of-range from NCB Interface */
+	uint64_t reserved_1_1                 : 1;
 	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
 #else
 	uint64_t pko_nxa                      : 1;
-	uint64_t ncb_nxa                      : 1;
+	uint64_t reserved_1_1                 : 1;
 	uint64_t undflw                       : 4;
 	uint64_t reserved_6_7                 : 2;
 	uint64_t xscol                        : 4;
 	uint64_t xsdef                        : 4;
 	uint64_t late_col                     : 4;
 	uint64_t ptp_lost                     : 4;
-	uint64_t reserved_24_63               : 40;
+	uint64_t xchange                      : 1;
+	uint64_t reserved_25_63               : 39;
 #endif
 	} s;
-	struct cvmx_gmxx_tx_int_en_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_int_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t late_col                     : 3;  /**< TX Late Collision */
 	uint64_t reserved_15_15               : 1;
@@ -7150,9 +9522,8 @@ union cvmx_gmxx_tx_int_en
 	uint64_t reserved_19_63               : 45;
 #endif
 	} cn30xx;
-	struct cvmx_gmxx_tx_int_en_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_int_en_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_15_63               : 49;
 	uint64_t xsdef                        : 3;  /**< TX Excessive deferral (RGMII/halfdup mode only) */
 	uint64_t reserved_11_11               : 1;
@@ -7172,9 +9543,8 @@ union cvmx_gmxx_tx_int_en
 	uint64_t reserved_15_63               : 49;
 #endif
 	} cn31xx;
-	struct cvmx_gmxx_tx_int_en_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_int_en_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t late_col                     : 4;  /**< TX Late Collision
                                                          (PASS3 only) */
@@ -7195,9 +9565,8 @@ union cvmx_gmxx_tx_int_en
 	uint64_t reserved_20_63               : 44;
 #endif
 	} cn38xx;
-	struct cvmx_gmxx_tx_int_en_cn38xxp2
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_int_en_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t xsdef                        : 4;  /**< TX Excessive deferral (RGMII/halfdup mode only) */
 	uint64_t xscol                        : 4;  /**< TX Excessive collisions (RGMII/halfdup mode only) */
@@ -7216,9 +9585,8 @@ union cvmx_gmxx_tx_int_en
 #endif
 	} cn38xxp2;
 	struct cvmx_gmxx_tx_int_en_cn30xx     cn50xx;
-	struct cvmx_gmxx_tx_int_en_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_int_en_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t late_col                     : 4;  /**< TX Late Collision
                                                          (SGMII/1000Base-X half-duplex only) */
@@ -7246,9 +9614,9 @@ union cvmx_gmxx_tx_int_en
 	struct cvmx_gmxx_tx_int_en_cn52xx     cn56xxp1;
 	struct cvmx_gmxx_tx_int_en_cn38xx     cn58xx;
 	struct cvmx_gmxx_tx_int_en_cn38xx     cn58xxp1;
-	struct cvmx_gmxx_tx_int_en_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_int_en_s          cn61xx;
+	struct cvmx_gmxx_tx_int_en_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t ptp_lost                     : 4;  /**< A packet with a PTP request was not able to be
                                                          sent due to XSCOL */
@@ -7275,6 +9643,78 @@ union cvmx_gmxx_tx_int_en
 #endif
 	} cn63xx;
 	struct cvmx_gmxx_tx_int_en_cn63xx     cn63xxp1;
+	struct cvmx_gmxx_tx_int_en_s          cn66xx;
+	struct cvmx_gmxx_tx_int_en_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_25_63               : 39;
+	uint64_t xchange                      : 1;  /**< XAUI/RXAUI link status changed - this denotes a
+                                                         change to GMX_RX_XAUI_CTL[STATUS]
+                                                         (XAUI/RXAUI mode only) */
+	uint64_t ptp_lost                     : 4;  /**< A packet with a PTP request was not able to be
+                                                         sent due to XSCOL */
+	uint64_t late_col                     : 4;  /**< TX Late Collision
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t xsdef                        : 4;  /**< TX Excessive deferral
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t xscol                        : 4;  /**< TX Excessive collisions
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t undflw                       : 4;  /**< TX Underflow */
+	uint64_t pko_nxp                      : 1;  /**< Port pipe out-of-range from PKO Interface */
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t pko_nxp                      : 1;
+	uint64_t undflw                       : 4;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t xscol                        : 4;
+	uint64_t xsdef                        : 4;
+	uint64_t late_col                     : 4;
+	uint64_t ptp_lost                     : 4;
+	uint64_t xchange                      : 1;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} cn68xx;
+	struct cvmx_gmxx_tx_int_en_cn68xx     cn68xxp1;
+	struct cvmx_gmxx_tx_int_en_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_25_63               : 39;
+	uint64_t xchange                      : 1;  /**< XAUI link status changed - this denotes a change
+                                                         to GMX_RX_XAUI_CTL[STATUS]
+                                                         (XAUI mode only) */
+	uint64_t reserved_22_23               : 2;
+	uint64_t ptp_lost                     : 2;  /**< A packet with a PTP request was not able to be
+                                                         sent due to XSCOL */
+	uint64_t reserved_18_19               : 2;
+	uint64_t late_col                     : 2;  /**< TX Late Collision
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t reserved_14_15               : 2;
+	uint64_t xsdef                        : 2;  /**< TX Excessive deferral
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t reserved_10_11               : 2;
+	uint64_t xscol                        : 2;  /**< TX Excessive collisions
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t undflw                       : 2;  /**< TX Underflow */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t undflw                       : 2;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t xscol                        : 2;
+	uint64_t reserved_10_11               : 2;
+	uint64_t xsdef                        : 2;
+	uint64_t reserved_14_15               : 2;
+	uint64_t late_col                     : 2;
+	uint64_t reserved_18_19               : 2;
+	uint64_t ptp_lost                     : 2;
+	uint64_t reserved_22_23               : 2;
+	uint64_t xchange                      : 1;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_gmxx_tx_int_en cvmx_gmxx_tx_int_en_t;
 
@@ -7288,13 +9728,14 @@ typedef union cvmx_gmxx_tx_int_en cvmx_gmxx_tx_int_en_t;
  * In XAUI mode, only the lsb (corresponding to port0) of UNDFLW is used.
  *
  */
-union cvmx_gmxx_tx_int_reg
-{
+union cvmx_gmxx_tx_int_reg {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_int_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_24_63               : 40;
+	struct cvmx_gmxx_tx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_25_63               : 39;
+	uint64_t xchange                      : 1;  /**< XAUI link status changed - this denotes a change
+                                                         to GMX_RX_XAUI_CTL[STATUS]
+                                                         (XAUI mode only) */
 	uint64_t ptp_lost                     : 4;  /**< A packet with a PTP request was not able to be
                                                          sent due to XSCOL */
 	uint64_t late_col                     : 4;  /**< TX Late Collision
@@ -7305,23 +9746,23 @@ union cvmx_gmxx_tx_int_reg
                                                          (SGMII/1000Base-X half-duplex only) */
 	uint64_t reserved_6_7                 : 2;
 	uint64_t undflw                       : 4;  /**< TX Underflow */
-	uint64_t ncb_nxa                      : 1;  /**< Port address out-of-range from NCB Interface */
+	uint64_t reserved_1_1                 : 1;
 	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
 #else
 	uint64_t pko_nxa                      : 1;
-	uint64_t ncb_nxa                      : 1;
+	uint64_t reserved_1_1                 : 1;
 	uint64_t undflw                       : 4;
 	uint64_t reserved_6_7                 : 2;
 	uint64_t xscol                        : 4;
 	uint64_t xsdef                        : 4;
 	uint64_t late_col                     : 4;
 	uint64_t ptp_lost                     : 4;
-	uint64_t reserved_24_63               : 40;
+	uint64_t xchange                      : 1;
+	uint64_t reserved_25_63               : 39;
 #endif
 	} s;
-	struct cvmx_gmxx_tx_int_reg_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_int_reg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t late_col                     : 3;  /**< TX Late Collision */
 	uint64_t reserved_15_15               : 1;
@@ -7345,9 +9786,8 @@ union cvmx_gmxx_tx_int_reg
 	uint64_t reserved_19_63               : 45;
 #endif
 	} cn30xx;
-	struct cvmx_gmxx_tx_int_reg_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_int_reg_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_15_63               : 49;
 	uint64_t xsdef                        : 3;  /**< TX Excessive deferral (RGMII/halfdup mode only) */
 	uint64_t reserved_11_11               : 1;
@@ -7367,9 +9807,8 @@ union cvmx_gmxx_tx_int_reg
 	uint64_t reserved_15_63               : 49;
 #endif
 	} cn31xx;
-	struct cvmx_gmxx_tx_int_reg_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_int_reg_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t late_col                     : 4;  /**< TX Late Collision
                                                          (PASS3 only) */
@@ -7390,9 +9829,8 @@ union cvmx_gmxx_tx_int_reg
 	uint64_t reserved_20_63               : 44;
 #endif
 	} cn38xx;
-	struct cvmx_gmxx_tx_int_reg_cn38xxp2
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_int_reg_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t xsdef                        : 4;  /**< TX Excessive deferral (RGMII/halfdup mode only) */
 	uint64_t xscol                        : 4;  /**< TX Excessive collisions (RGMII/halfdup mode only) */
@@ -7411,9 +9849,8 @@ union cvmx_gmxx_tx_int_reg
 #endif
 	} cn38xxp2;
 	struct cvmx_gmxx_tx_int_reg_cn30xx    cn50xx;
-	struct cvmx_gmxx_tx_int_reg_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t late_col                     : 4;  /**< TX Late Collision
                                                          (SGMII/1000Base-X half-duplex only) */
@@ -7441,9 +9878,9 @@ union cvmx_gmxx_tx_int_reg
 	struct cvmx_gmxx_tx_int_reg_cn52xx    cn56xxp1;
 	struct cvmx_gmxx_tx_int_reg_cn38xx    cn58xx;
 	struct cvmx_gmxx_tx_int_reg_cn38xx    cn58xxp1;
-	struct cvmx_gmxx_tx_int_reg_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_int_reg_s         cn61xx;
+	struct cvmx_gmxx_tx_int_reg_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t ptp_lost                     : 4;  /**< A packet with a PTP request was not able to be
                                                          sent due to XSCOL */
@@ -7470,6 +9907,78 @@ union cvmx_gmxx_tx_int_reg
 #endif
 	} cn63xx;
 	struct cvmx_gmxx_tx_int_reg_cn63xx    cn63xxp1;
+	struct cvmx_gmxx_tx_int_reg_s         cn66xx;
+	struct cvmx_gmxx_tx_int_reg_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_25_63               : 39;
+	uint64_t xchange                      : 1;  /**< XAUI/RXAUI link status changed - this denotes ae
+                                                         change to GMX_RX_XAUI_CTL[STATUS]
+                                                         (XAUI/RXAUI mode only) */
+	uint64_t ptp_lost                     : 4;  /**< A packet with a PTP request was not able to be
+                                                         sent due to XSCOL */
+	uint64_t late_col                     : 4;  /**< TX Late Collision
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t xsdef                        : 4;  /**< TX Excessive deferral
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t xscol                        : 4;  /**< TX Excessive collisions
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t undflw                       : 4;  /**< TX Underflow */
+	uint64_t pko_nxp                      : 1;  /**< Port pipe out-of-range from PKO Interface */
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t pko_nxp                      : 1;
+	uint64_t undflw                       : 4;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t xscol                        : 4;
+	uint64_t xsdef                        : 4;
+	uint64_t late_col                     : 4;
+	uint64_t ptp_lost                     : 4;
+	uint64_t xchange                      : 1;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} cn68xx;
+	struct cvmx_gmxx_tx_int_reg_cn68xx    cn68xxp1;
+	struct cvmx_gmxx_tx_int_reg_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_25_63               : 39;
+	uint64_t xchange                      : 1;  /**< XAUI link status changed - this denotes a change
+                                                         to GMX_RX_XAUI_CTL[STATUS]
+                                                         (XAUI mode only) */
+	uint64_t reserved_22_23               : 2;
+	uint64_t ptp_lost                     : 2;  /**< A packet with a PTP request was not able to be
+                                                         sent due to XSCOL */
+	uint64_t reserved_18_19               : 2;
+	uint64_t late_col                     : 2;  /**< TX Late Collision
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t reserved_14_15               : 2;
+	uint64_t xsdef                        : 2;  /**< TX Excessive deferral
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t reserved_10_11               : 2;
+	uint64_t xscol                        : 2;  /**< TX Excessive collisions
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t undflw                       : 2;  /**< TX Underflow */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t undflw                       : 2;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t xscol                        : 2;
+	uint64_t reserved_10_11               : 2;
+	uint64_t xsdef                        : 2;
+	uint64_t reserved_14_15               : 2;
+	uint64_t late_col                     : 2;
+	uint64_t reserved_18_19               : 2;
+	uint64_t ptp_lost                     : 2;
+	uint64_t reserved_22_23               : 2;
+	uint64_t xchange                      : 1;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_gmxx_tx_int_reg cvmx_gmxx_tx_int_reg_t;
 
@@ -7479,12 +9988,10 @@ typedef union cvmx_gmxx_tx_int_reg cvmx_gmxx_tx_int_reg_t;
  * GMX_TX_JAM = Packet TX Jam Pattern
  *
  */
-union cvmx_gmxx_tx_jam
-{
+union cvmx_gmxx_tx_jam {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_jam_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_jam_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t jam                          : 8;  /**< Jam pattern
                                                          (SGMII/1000Base-X half-duplex only) */
@@ -7504,8 +10011,13 @@ union cvmx_gmxx_tx_jam
 	struct cvmx_gmxx_tx_jam_s             cn56xxp1;
 	struct cvmx_gmxx_tx_jam_s             cn58xx;
 	struct cvmx_gmxx_tx_jam_s             cn58xxp1;
+	struct cvmx_gmxx_tx_jam_s             cn61xx;
 	struct cvmx_gmxx_tx_jam_s             cn63xx;
 	struct cvmx_gmxx_tx_jam_s             cn63xxp1;
+	struct cvmx_gmxx_tx_jam_s             cn66xx;
+	struct cvmx_gmxx_tx_jam_s             cn68xx;
+	struct cvmx_gmxx_tx_jam_s             cn68xxp1;
+	struct cvmx_gmxx_tx_jam_s             cnf71xx;
 };
 typedef union cvmx_gmxx_tx_jam cvmx_gmxx_tx_jam_t;
 
@@ -7515,12 +10027,10 @@ typedef union cvmx_gmxx_tx_jam cvmx_gmxx_tx_jam_t;
  * GMX_TX_LFSR = LFSR used to implement truncated binary exponential backoff
  *
  */
-union cvmx_gmxx_tx_lfsr
-{
+union cvmx_gmxx_tx_lfsr {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_lfsr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_lfsr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t lfsr                         : 16; /**< The current state of the LFSR used to feed random
                                                          numbers to compute truncated binary exponential
@@ -7542,8 +10052,13 @@ union cvmx_gmxx_tx_lfsr
 	struct cvmx_gmxx_tx_lfsr_s            cn56xxp1;
 	struct cvmx_gmxx_tx_lfsr_s            cn58xx;
 	struct cvmx_gmxx_tx_lfsr_s            cn58xxp1;
+	struct cvmx_gmxx_tx_lfsr_s            cn61xx;
 	struct cvmx_gmxx_tx_lfsr_s            cn63xx;
 	struct cvmx_gmxx_tx_lfsr_s            cn63xxp1;
+	struct cvmx_gmxx_tx_lfsr_s            cn66xx;
+	struct cvmx_gmxx_tx_lfsr_s            cn68xx;
+	struct cvmx_gmxx_tx_lfsr_s            cn68xxp1;
+	struct cvmx_gmxx_tx_lfsr_s            cnf71xx;
 };
 typedef union cvmx_gmxx_tx_lfsr cvmx_gmxx_tx_lfsr_t;
 
@@ -7563,12 +10078,10 @@ typedef union cvmx_gmxx_tx_lfsr cvmx_gmxx_tx_lfsr_t;
  * through HiGig2 messages (optionally, when GMX*_HG2_CONTROL[HG2TX_EN]=1) with the HiGig2
  * protocol.
  */
-union cvmx_gmxx_tx_ovr_bp
-{
+union cvmx_gmxx_tx_ovr_bp {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_ovr_bp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_ovr_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t tx_prt_bp                    : 16; /**< Per port BP sent to PKO
                                                          0=Port is available
@@ -7590,9 +10103,8 @@ union cvmx_gmxx_tx_ovr_bp
 	uint64_t reserved_48_63               : 16;
 #endif
 	} s;
-	struct cvmx_gmxx_tx_ovr_bp_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_ovr_bp_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t en                           : 3;  /**< Per port Enable back pressure override */
 	uint64_t reserved_7_7                 : 1;
@@ -7611,9 +10123,8 @@ union cvmx_gmxx_tx_ovr_bp
 #endif
 	} cn30xx;
 	struct cvmx_gmxx_tx_ovr_bp_cn30xx     cn31xx;
-	struct cvmx_gmxx_tx_ovr_bp_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_ovr_bp_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t en                           : 4;  /**< Per port Enable back pressure override */
 	uint64_t bp                           : 4;  /**< Per port BackPressure status to use
@@ -7635,8 +10146,39 @@ union cvmx_gmxx_tx_ovr_bp
 	struct cvmx_gmxx_tx_ovr_bp_s          cn56xxp1;
 	struct cvmx_gmxx_tx_ovr_bp_cn38xx     cn58xx;
 	struct cvmx_gmxx_tx_ovr_bp_cn38xx     cn58xxp1;
+	struct cvmx_gmxx_tx_ovr_bp_s          cn61xx;
 	struct cvmx_gmxx_tx_ovr_bp_s          cn63xx;
 	struct cvmx_gmxx_tx_ovr_bp_s          cn63xxp1;
+	struct cvmx_gmxx_tx_ovr_bp_s          cn66xx;
+	struct cvmx_gmxx_tx_ovr_bp_s          cn68xx;
+	struct cvmx_gmxx_tx_ovr_bp_s          cn68xxp1;
+	struct cvmx_gmxx_tx_ovr_bp_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_48_63               : 16;
+	uint64_t tx_prt_bp                    : 16; /**< Per port BP sent to PKO
+                                                         0=Port is available
+                                                         1=Port should be back pressured
+                                                         TX_PRT_BP should not be set until
+                                                         GMX_INF_MODE[EN] has been enabled */
+	uint64_t reserved_10_31               : 22;
+	uint64_t en                           : 2;  /**< Per port Enable back pressure override */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t bp                           : 2;  /**< Per port BackPressure status to use
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t ign_full                     : 2;  /**< Ignore the RX FIFO full when computing BP */
+#else
+	uint64_t ign_full                     : 2;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t bp                           : 2;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t en                           : 2;
+	uint64_t reserved_10_31               : 22;
+	uint64_t tx_prt_bp                    : 16;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_gmxx_tx_ovr_bp cvmx_gmxx_tx_ovr_bp_t;
 
@@ -7646,12 +10188,10 @@ typedef union cvmx_gmxx_tx_ovr_bp cvmx_gmxx_tx_ovr_bp_t;
  * GMX_TX_PAUSE_PKT_DMAC = Packet TX Pause Packet DMAC field
  *
  */
-union cvmx_gmxx_tx_pause_pkt_dmac
-{
+union cvmx_gmxx_tx_pause_pkt_dmac {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_pause_pkt_dmac_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t dmac                         : 48; /**< The DMAC field placed is outbnd pause pkts */
 #else
@@ -7670,8 +10210,13 @@ union cvmx_gmxx_tx_pause_pkt_dmac
 	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn56xxp1;
 	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn58xx;
 	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn58xxp1;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn61xx;
 	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn63xx;
 	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn63xxp1;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn66xx;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn68xx;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn68xxp1;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cnf71xx;
 };
 typedef union cvmx_gmxx_tx_pause_pkt_dmac cvmx_gmxx_tx_pause_pkt_dmac_t;
 
@@ -7681,12 +10226,10 @@ typedef union cvmx_gmxx_tx_pause_pkt_dmac cvmx_gmxx_tx_pause_pkt_dmac_t;
  * GMX_TX_PAUSE_PKT_TYPE = Packet Interface TX Pause Packet TYPE field
  *
  */
-union cvmx_gmxx_tx_pause_pkt_type
-{
+union cvmx_gmxx_tx_pause_pkt_type {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_pause_pkt_type_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_pause_pkt_type_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t type                         : 16; /**< The TYPE field placed is outbnd pause pkts */
 #else
@@ -7705,8 +10248,13 @@ union cvmx_gmxx_tx_pause_pkt_type
 	struct cvmx_gmxx_tx_pause_pkt_type_s  cn56xxp1;
 	struct cvmx_gmxx_tx_pause_pkt_type_s  cn58xx;
 	struct cvmx_gmxx_tx_pause_pkt_type_s  cn58xxp1;
+	struct cvmx_gmxx_tx_pause_pkt_type_s  cn61xx;
 	struct cvmx_gmxx_tx_pause_pkt_type_s  cn63xx;
 	struct cvmx_gmxx_tx_pause_pkt_type_s  cn63xxp1;
+	struct cvmx_gmxx_tx_pause_pkt_type_s  cn66xx;
+	struct cvmx_gmxx_tx_pause_pkt_type_s  cn68xx;
+	struct cvmx_gmxx_tx_pause_pkt_type_s  cn68xxp1;
+	struct cvmx_gmxx_tx_pause_pkt_type_s  cnf71xx;
 };
 typedef union cvmx_gmxx_tx_pause_pkt_type cvmx_gmxx_tx_pause_pkt_type_t;
 
@@ -7724,12 +10272,10 @@ typedef union cvmx_gmxx_tx_pause_pkt_type cvmx_gmxx_tx_pause_pkt_type_t;
  * highest architected port, then the programmed value should be 3 since
  * there are 3 ports in the system - 0, 1, and 2.
  */
-union cvmx_gmxx_tx_prts
-{
+union cvmx_gmxx_tx_prts {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_prts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_prts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t prts                         : 5;  /**< Number of ports allowed on the interface
                                                          (SGMII/1000Base-X only) */
@@ -7749,8 +10295,13 @@ union cvmx_gmxx_tx_prts
 	struct cvmx_gmxx_tx_prts_s            cn56xxp1;
 	struct cvmx_gmxx_tx_prts_s            cn58xx;
 	struct cvmx_gmxx_tx_prts_s            cn58xxp1;
+	struct cvmx_gmxx_tx_prts_s            cn61xx;
 	struct cvmx_gmxx_tx_prts_s            cn63xx;
 	struct cvmx_gmxx_tx_prts_s            cn63xxp1;
+	struct cvmx_gmxx_tx_prts_s            cn66xx;
+	struct cvmx_gmxx_tx_prts_s            cn68xx;
+	struct cvmx_gmxx_tx_prts_s            cn68xxp1;
+	struct cvmx_gmxx_tx_prts_s            cnf71xx;
 };
 typedef union cvmx_gmxx_tx_prts cvmx_gmxx_tx_prts_t;
 
@@ -7760,12 +10311,10 @@ typedef union cvmx_gmxx_tx_prts cvmx_gmxx_tx_prts_t;
  * GMX_TX_SPI_CTL = Spi4 TX ModesSpi4
  *
  */
-union cvmx_gmxx_tx_spi_ctl
-{
+union cvmx_gmxx_tx_spi_ctl {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_spi_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_spi_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t tpa_clr                      : 1;  /**< TPA Clear Mode
                                                          Clear credit counter when satisifed status */
@@ -7791,12 +10340,10 @@ typedef union cvmx_gmxx_tx_spi_ctl cvmx_gmxx_tx_spi_ctl_t;
  * GMX_TX_SPI_DRAIN = Drain out Spi TX FIFO
  *
  */
-union cvmx_gmxx_tx_spi_drain
-{
+union cvmx_gmxx_tx_spi_drain {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_spi_drain_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_spi_drain_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t drain                        : 16; /**< Per port drain control
                                                          0=Normal operation
@@ -7822,12 +10369,10 @@ typedef union cvmx_gmxx_tx_spi_drain cvmx_gmxx_tx_spi_drain_t;
  * GMX_TX_SPI_MAX = RGMII TX Spi4 MAX
  *
  */
-union cvmx_gmxx_tx_spi_max
-{
+union cvmx_gmxx_tx_spi_max {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_spi_max_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_spi_max_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_23_63               : 41;
 	uint64_t slice                        : 7;  /**< Number of 16B blocks to transmit in a burst before
                                                          switching to the next port. SLICE does not always
@@ -7856,9 +10401,8 @@ union cvmx_gmxx_tx_spi_max
 	uint64_t reserved_23_63               : 41;
 #endif
 	} s;
-	struct cvmx_gmxx_tx_spi_max_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_spi_max_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t max2                         : 8;  /**< MAX2 (per Spi4.2 spec) */
 	uint64_t max1                         : 8;  /**< MAX1 (per Spi4.2 spec)
@@ -7881,12 +10425,10 @@ typedef union cvmx_gmxx_tx_spi_max cvmx_gmxx_tx_spi_max_t;
  * GMX_TX_SPI_ROUND = Controls SPI4 TX Arbitration
  *
  */
-union cvmx_gmxx_tx_spi_roundx
-{
+union cvmx_gmxx_tx_spi_roundx {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_spi_roundx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_spi_roundx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t round                        : 16; /**< Which Spi ports participate in each arbitration
                                                           round.  Each bit corresponds to a spi port
@@ -7918,12 +10460,10 @@ typedef union cvmx_gmxx_tx_spi_roundx cvmx_gmxx_tx_spi_roundx_t;
  * Octeon will never violate the Spi4.2 spec and send a non-EOP burst that is
  * not a multiple of 16B.
  */
-union cvmx_gmxx_tx_spi_thresh
-{
+union cvmx_gmxx_tx_spi_thresh {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_spi_thresh_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_spi_thresh_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t thresh                       : 6;  /**< Transmit threshold in 16B blocks - cannot be zero
                                                          THRESH <= TX_FIFO size   (in non-passthrough mode)
@@ -7949,12 +10489,10 @@ typedef union cvmx_gmxx_tx_spi_thresh cvmx_gmxx_tx_spi_thresh_t;
 /**
  * cvmx_gmx#_tx_xaui_ctl
  */
-union cvmx_gmxx_tx_xaui_ctl
-{
+union cvmx_gmxx_tx_xaui_ctl {
 	uint64_t u64;
-	struct cvmx_gmxx_tx_xaui_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_tx_xaui_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t hg_pause_hgi                 : 2;  /**< HGI Field for HW generated HiGig pause packets
                                                          (XAUI mode only) */
@@ -8014,20 +10552,23 @@ union cvmx_gmxx_tx_xaui_ctl
 	struct cvmx_gmxx_tx_xaui_ctl_s        cn52xxp1;
 	struct cvmx_gmxx_tx_xaui_ctl_s        cn56xx;
 	struct cvmx_gmxx_tx_xaui_ctl_s        cn56xxp1;
+	struct cvmx_gmxx_tx_xaui_ctl_s        cn61xx;
 	struct cvmx_gmxx_tx_xaui_ctl_s        cn63xx;
 	struct cvmx_gmxx_tx_xaui_ctl_s        cn63xxp1;
+	struct cvmx_gmxx_tx_xaui_ctl_s        cn66xx;
+	struct cvmx_gmxx_tx_xaui_ctl_s        cn68xx;
+	struct cvmx_gmxx_tx_xaui_ctl_s        cn68xxp1;
+	struct cvmx_gmxx_tx_xaui_ctl_s        cnf71xx;
 };
 typedef union cvmx_gmxx_tx_xaui_ctl cvmx_gmxx_tx_xaui_ctl_t;
 
 /**
  * cvmx_gmx#_xaui_ext_loopback
  */
-union cvmx_gmxx_xaui_ext_loopback
-{
+union cvmx_gmxx_xaui_ext_loopback {
 	uint64_t u64;
-	struct cvmx_gmxx_xaui_ext_loopback_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gmxx_xaui_ext_loopback_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t en                           : 1;  /**< Loopback enable
                                                          Puts the packet interface in external loopback
@@ -8049,8 +10590,13 @@ union cvmx_gmxx_xaui_ext_loopback
 	struct cvmx_gmxx_xaui_ext_loopback_s  cn52xxp1;
 	struct cvmx_gmxx_xaui_ext_loopback_s  cn56xx;
 	struct cvmx_gmxx_xaui_ext_loopback_s  cn56xxp1;
+	struct cvmx_gmxx_xaui_ext_loopback_s  cn61xx;
 	struct cvmx_gmxx_xaui_ext_loopback_s  cn63xx;
 	struct cvmx_gmxx_xaui_ext_loopback_s  cn63xxp1;
+	struct cvmx_gmxx_xaui_ext_loopback_s  cn66xx;
+	struct cvmx_gmxx_xaui_ext_loopback_s  cn68xx;
+	struct cvmx_gmxx_xaui_ext_loopback_s  cn68xxp1;
+	struct cvmx_gmxx_xaui_ext_loopback_s  cnf71xx;
 };
 typedef union cvmx_gmxx_xaui_ext_loopback cvmx_gmxx_xaui_ext_loopback_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-gpio-defs.h b/sys/contrib/octeon-sdk/cvmx-gpio-defs.h
index d0e700f..230221e 100644
--- a/sys/contrib/octeon-sdk/cvmx-gpio-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-gpio-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_GPIO_TYPEDEFS_H__
-#define __CVMX_GPIO_TYPEDEFS_H__
+#ifndef __CVMX_GPIO_DEFS_H__
+#define __CVMX_GPIO_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GPIO_BIT_CFGX(unsigned long offset)
@@ -63,7 +63,11 @@ static inline uint64_t CVMX_GPIO_BIT_CFGX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 15)))))
 		cvmx_warn("CVMX_GPIO_BIT_CFGX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8;
 }
@@ -87,7 +91,11 @@ static inline uint64_t CVMX_GPIO_CLK_GENX(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_GPIO_CLK_GENX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8;
 }
@@ -98,7 +106,11 @@ static inline uint64_t CVMX_GPIO_CLK_GENX(unsigned long offset)
 static inline uint64_t CVMX_GPIO_CLK_QLMX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_GPIO_CLK_QLMX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8;
 }
@@ -117,7 +129,40 @@ static inline uint64_t CVMX_GPIO_DBG_ENA_FUNC(void)
 #define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
 #endif
 #define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_GPIO_MULTI_CAST CVMX_GPIO_MULTI_CAST_FUNC()
+static inline uint64_t CVMX_GPIO_MULTI_CAST_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_GPIO_MULTI_CAST not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010700000008B0ull);
+}
+#else
+#define CVMX_GPIO_MULTI_CAST (CVMX_ADD_IO_SEG(0x00010700000008B0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_GPIO_PIN_ENA CVMX_GPIO_PIN_ENA_FUNC()
+static inline uint64_t CVMX_GPIO_PIN_ENA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN66XX)))
+		cvmx_warn("CVMX_GPIO_PIN_ENA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010700000008B8ull);
+}
+#else
+#define CVMX_GPIO_PIN_ENA (CVMX_ADD_IO_SEG(0x00010700000008B8ull))
+#endif
 #define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_GPIO_TIM_CTL CVMX_GPIO_TIM_CTL_FUNC()
+static inline uint64_t CVMX_GPIO_TIM_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_GPIO_TIM_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010700000008A0ull);
+}
+#else
+#define CVMX_GPIO_TIM_CTL (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
+#endif
 #define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
 #define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
@@ -126,7 +171,10 @@ static inline uint64_t CVMX_GPIO_XBIT_CFGX(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 16) && (offset <= 23)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 16) && (offset <= 23)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 16) && (offset <= 23))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 16) && (offset <= 23)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 16) && (offset <= 19)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 16) && (offset <= 19)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 16) && (offset <= 19))))))
 		cvmx_warn("CVMX_GPIO_XBIT_CFGX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16;
 }
@@ -136,18 +184,20 @@ static inline uint64_t CVMX_GPIO_XBIT_CFGX(unsigned long offset)
 
 /**
  * cvmx_gpio_bit_cfg#
+ *
+ * Notes:
+ * Only first 16 GPIO pins can introduce interrupts, GPIO_XBIT_CFG16(17,18,19)[INT_EN] and [INT_TYPE]
+ * will not be used, read out always zero.
  */
-union cvmx_gpio_bit_cfgx
-{
+union cvmx_gpio_bit_cfgx {
 	uint64_t u64;
-	struct cvmx_gpio_bit_cfgx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_bit_cfgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t synce_sel                    : 2;  /**< Selects the QLM clock output
                                                          x0=Normal GPIO output
-                                                         01=GPIO QLM clock selected by GPIO_CLK_QLM0
-                                                         11=GPIO QLM clock selected by GPIO_CLK_QLM1 */
+                                                         01=GPIO QLM clock selected by CSR GPIO_CLK_QLM0
+                                                         11=GPIO QLM clock selected by CSR GPIO_CLK_QLM1 */
 	uint64_t clk_gen                      : 1;  /**< When TX_OE is set, GPIO pin becomes a clock */
 	uint64_t clk_sel                      : 2;  /**< Selects which of the 4 GPIO clock generators */
 	uint64_t fil_sel                      : 4;  /**< Global counter bit-select (controls sample rate) */
@@ -171,9 +221,8 @@ union cvmx_gpio_bit_cfgx
 	uint64_t reserved_17_63               : 47;
 #endif
 	} s;
-	struct cvmx_gpio_bit_cfgx_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_bit_cfgx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t fil_sel                      : 4;  /**< Global counter bit-select (controls sample rate) */
 	uint64_t fil_cnt                      : 4;  /**< Number of consecutive samples to change state */
@@ -197,9 +246,8 @@ union cvmx_gpio_bit_cfgx
 	struct cvmx_gpio_bit_cfgx_cn30xx      cn38xx;
 	struct cvmx_gpio_bit_cfgx_cn30xx      cn38xxp2;
 	struct cvmx_gpio_bit_cfgx_cn30xx      cn50xx;
-	struct cvmx_gpio_bit_cfgx_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_bit_cfgx_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_15_63               : 49;
 	uint64_t clk_gen                      : 1;  /**< When TX_OE is set, GPIO pin becomes a clock */
 	uint64_t clk_sel                      : 2;  /**< Selects which of the 4 GPIO clock generators */
@@ -228,20 +276,23 @@ union cvmx_gpio_bit_cfgx
 	struct cvmx_gpio_bit_cfgx_cn52xx      cn56xxp1;
 	struct cvmx_gpio_bit_cfgx_cn30xx      cn58xx;
 	struct cvmx_gpio_bit_cfgx_cn30xx      cn58xxp1;
+	struct cvmx_gpio_bit_cfgx_s           cn61xx;
 	struct cvmx_gpio_bit_cfgx_s           cn63xx;
 	struct cvmx_gpio_bit_cfgx_s           cn63xxp1;
+	struct cvmx_gpio_bit_cfgx_s           cn66xx;
+	struct cvmx_gpio_bit_cfgx_s           cn68xx;
+	struct cvmx_gpio_bit_cfgx_s           cn68xxp1;
+	struct cvmx_gpio_bit_cfgx_s           cnf71xx;
 };
 typedef union cvmx_gpio_bit_cfgx cvmx_gpio_bit_cfgx_t;
 
 /**
  * cvmx_gpio_boot_ena
  */
-union cvmx_gpio_boot_ena
-{
+union cvmx_gpio_boot_ena {
 	uint64_t u64;
-	struct cvmx_gpio_boot_ena_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_boot_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t boot_ena                     : 4;  /**< Drive boot bus chip enables [7:4] on gpio [11:8] */
 	uint64_t reserved_0_7                 : 8;
@@ -260,12 +311,10 @@ typedef union cvmx_gpio_boot_ena cvmx_gpio_boot_ena_t;
 /**
  * cvmx_gpio_clk_gen#
  */
-union cvmx_gpio_clk_genx
-{
+union cvmx_gpio_clk_genx {
 	uint64_t u64;
-	struct cvmx_gpio_clk_genx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_clk_genx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t n                            : 32; /**< Determines the frequency of the GPIO clk generator
                                                          NOTE: Fgpio_clk = Feclk * N / 2^32
@@ -281,8 +330,13 @@ union cvmx_gpio_clk_genx
 	struct cvmx_gpio_clk_genx_s           cn52xxp1;
 	struct cvmx_gpio_clk_genx_s           cn56xx;
 	struct cvmx_gpio_clk_genx_s           cn56xxp1;
+	struct cvmx_gpio_clk_genx_s           cn61xx;
 	struct cvmx_gpio_clk_genx_s           cn63xx;
 	struct cvmx_gpio_clk_genx_s           cn63xxp1;
+	struct cvmx_gpio_clk_genx_s           cn66xx;
+	struct cvmx_gpio_clk_genx_s           cn68xx;
+	struct cvmx_gpio_clk_genx_s           cn68xxp1;
+	struct cvmx_gpio_clk_genx_s           cnf71xx;
 };
 typedef union cvmx_gpio_clk_genx cvmx_gpio_clk_genx_t;
 
@@ -290,6 +344,7 @@ typedef union cvmx_gpio_clk_genx cvmx_gpio_clk_genx_t;
  * cvmx_gpio_clk_qlm#
  *
  * Notes:
+ * QLM0(A) and QLM1(B) can configured to source any of QLM0 or QLM2 as clock source.
  * Clock speed output for different modes ...
  *
  *                        Speed With      Speed with
@@ -301,12 +356,59 @@ typedef union cvmx_gpio_clk_genx cvmx_gpio_clk_genx_t;
  *      5.0                 250             125
  *      6.25                312.5           156.25
  */
-union cvmx_gpio_clk_qlmx
-{
+union cvmx_gpio_clk_qlmx {
 	uint64_t u64;
-	struct cvmx_gpio_clk_qlmx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_clk_qlmx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_11_63               : 53;
+	uint64_t qlm_sel                      : 3;  /**< Selects which DLM to select from
+                                                         x0 = select DLM0 as clock source
+                                                         x1 = Disabled */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t div                          : 1;  /**< Internal clock divider
+                                                         0=DIV2
+                                                         1=DIV4 */
+	uint64_t lane_sel                     : 2;  /**< Selects which RX lane clock from QLMx to use as
+                                                         the GPIO internal QLMx clock.  The GPIO block can
+                                                         support upto two unique clocks to send out any
+                                                         GPIO pin as configured by $GPIO_BIT_CFG[SYNCE_SEL]
+                                                         The clock can either be a divided by 2 or divide
+                                                         by 4 of the selected RX lane clock. */
+#else
+	uint64_t lane_sel                     : 2;
+	uint64_t div                          : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t qlm_sel                      : 3;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} s;
+	struct cvmx_gpio_clk_qlmx_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t qlm_sel                      : 2;  /**< Selects which QLM to select from
+                                                         01 = select QLM0 as clock source
+                                                         1x = select QLM2 as clock source
+                                                         0  = Disabled */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t div                          : 1;  /**< Internal clock divider
+                                                         0=DIV2
+                                                         1=DIV4 */
+	uint64_t lane_sel                     : 2;  /**< Selects which RX lane clock from QLMx to use as
+                                                         the GPIO internal QLMx clock.  The GPIO block can
+                                                         support upto two unique clocks to send out any
+                                                         GPIO pin as configured by $GPIO_BIT_CFG[SYNCE_SEL]
+                                                         The clock can either be a divided by 2 or divide
+                                                         by 4 of the selected RX lane clock. */
+#else
+	uint64_t lane_sel                     : 2;
+	uint64_t div                          : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t qlm_sel                      : 2;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn61xx;
+	struct cvmx_gpio_clk_qlmx_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t div                          : 1;  /**< Internal clock divider
                                                          0=DIV2
@@ -322,21 +424,22 @@ union cvmx_gpio_clk_qlmx
 	uint64_t div                          : 1;
 	uint64_t reserved_3_63                : 61;
 #endif
-	} s;
-	struct cvmx_gpio_clk_qlmx_s           cn63xx;
-	struct cvmx_gpio_clk_qlmx_s           cn63xxp1;
+	} cn63xx;
+	struct cvmx_gpio_clk_qlmx_cn63xx      cn63xxp1;
+	struct cvmx_gpio_clk_qlmx_cn61xx      cn66xx;
+	struct cvmx_gpio_clk_qlmx_s           cn68xx;
+	struct cvmx_gpio_clk_qlmx_s           cn68xxp1;
+	struct cvmx_gpio_clk_qlmx_cn61xx      cnf71xx;
 };
 typedef union cvmx_gpio_clk_qlmx cvmx_gpio_clk_qlmx_t;
 
 /**
  * cvmx_gpio_dbg_ena
  */
-union cvmx_gpio_dbg_ena
-{
+union cvmx_gpio_dbg_ena {
 	uint64_t u64;
-	struct cvmx_gpio_dbg_ena_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_dbg_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_21_63               : 43;
 	uint64_t dbg_ena                      : 21; /**< Enable the debug port to be driven on the gpio */
 #else
@@ -352,13 +455,15 @@ typedef union cvmx_gpio_dbg_ena cvmx_gpio_dbg_ena_t;
 
 /**
  * cvmx_gpio_int_clr
+ *
+ * Notes:
+ * Only 16 out of 20 GPIOs support interrupt.GPIO_INT_CLR only apply to GPIO0-GPIO15.
+ *
  */
-union cvmx_gpio_int_clr
-{
+union cvmx_gpio_int_clr {
 	uint64_t u64;
-	struct cvmx_gpio_int_clr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_int_clr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t type                         : 16; /**< Clear the interrupt rising edge detector */
 #else
@@ -377,20 +482,126 @@ union cvmx_gpio_int_clr
 	struct cvmx_gpio_int_clr_s            cn56xxp1;
 	struct cvmx_gpio_int_clr_s            cn58xx;
 	struct cvmx_gpio_int_clr_s            cn58xxp1;
+	struct cvmx_gpio_int_clr_s            cn61xx;
 	struct cvmx_gpio_int_clr_s            cn63xx;
 	struct cvmx_gpio_int_clr_s            cn63xxp1;
+	struct cvmx_gpio_int_clr_s            cn66xx;
+	struct cvmx_gpio_int_clr_s            cn68xx;
+	struct cvmx_gpio_int_clr_s            cn68xxp1;
+	struct cvmx_gpio_int_clr_s            cnf71xx;
 };
 typedef union cvmx_gpio_int_clr cvmx_gpio_int_clr_t;
 
 /**
+ * cvmx_gpio_multi_cast
+ *
+ * Notes:
+ * GPIO<7:4> have the option of operating in GPIO Interrupt Multicast mode.  In
+ * this mode, the PP GPIO interrupts (CIU_INT<0-7>_SUM0/CIU_INT<0-3>_SUM4[GPIO<7:4>] values are
+ * stored per cnMIPS core.
+ * For GPIO<7:4> (x=4-7):
+ *    When GPIO_MULTI_CAST[EN] = 1:
+ *        When GPIO_BIT_CFGx[INT_EN]==1 &  GPIO_BIT_CFGx[INT_TYPE]==1 (edge detection and interrupt enabled):
+ *          * Reads to CIU_INT<0-7>_SUM0/<0-3>_SUM4[GPIO<x>] will return a unique interrupt state per
+ *            cnMIPS core.
+ *          * Reads to CIU_INT32/33_SUM0/4[GPIO<x>] will return the common GPIO<x>
+ *            interrupt state.
+ *          * Write of '1' to CIU_INT<0-7>_SUM0/<0-3>_SUM4[GPIO<x>] will clear the individual
+ *            interrupt associated with the cnMIPS core.
+ *          * Write of '1' to CIU_INT32/33_SUM0/4[GPIO<x>] will clear the common GPIO<x>
+ *            interrupt state.
+ *          * Write of '1' to GPIO_INT_CLR[TYPE<x>] will clear all
+ *            CIU_INT*_SUM0/4[GPIO<x>] state across all cnMIPS cores and common GPIO<x> interrupt states.
+ *        When GPIO_BIT_CFGx[INT_EN]==0 or GPIO_BIT_CFGx[INT_TYPE]==0,
+ *          * either leveled interrupt or interrupt not enabled, write of '1' to CIU_INT*_SUM0/4[GPIO<x>]
+ *            will have no effects.
+ *     When GPIO_MULTI_CAST[EN] = 0:
+ *        * Write of '1' to CIU_INT_SUM0/4[GPIO<x>] will have no effects, as this field is RO,
+ *          backward compatible with o63.
+ *        When GPIO_BIT_CFGx[INT_EN]==1 &  GPIO_BIT_CFGx[INT_TYPE]==1 (edge detection and interrupt enabled):
+ *          * Reads to CIU_INT*_SUM0/4[GPIO<x>] will return the common GPIO<X> interrupt state.
+ *          * Write of '1' to GPIO_INT_CLR[TYPE<x>] will clear all
+ *            CIU_INT*_SUM0/4[GPIO<x>] state across all cnMIPS cores and common GPIO<x> interrupt states.
+ *        When GPIO_BIT_CFGx[INT_EN]==0 or GPIO_BIT_CFGx[INT_TYPE]==0,
+ *          * either leveled interrupt or interrupt not enabled, write of '1' to CIU_INT*_SUM0/4[GPIO<x>]
+ *            will have no effects.
+ *
+ * GPIO<15:8> and GPIO<3:0> will never be in multicast mode as those don't have per cnMIPS capabilities.
+ * For GPIO<y> (y=0-3,8-15):
+ *    When GPIO_BIT_CFGx[INT_EN]==1 &  GPIO_BIT_CFGx[INT_TYPE]==1 (edge detection and interrupt enabled):
+ *       * Reads to CIU_INT*_SUM0/4[GPIO<y>] will return the common GPIO<y> interrupt state.
+ *       * Write of '1' to GPIO_INT_CLR[TYPE<y>] will clear all CIU_INT*_SUM0/4[GPIO<y>] common GPIO<y>
+ *         interrupt states.
+ *       When GPIO_MULTI_CAST[EN] = 1:
+ *         * Write of '1' to CIU_INT*_SUM0/4[GPIO<y>] will clear the common GPIO<y> interrupt state.
+ *       When GPIO_MULTI_CAST[EN] = 0:
+ *         * Write of '1' to CIU_INT*_SUM0/4[GPIO<y>] has no effect, as this field is RO,
+ *           backward compatible to o63.
+ *    When GPIO_BIT_CFGx[INT_EN]==0 or GPIO_BIT_CFGx[INT_TYPE]==0,
+ *       * either leveled interrupt or interrupt not enabled, write of '1' to CIU_INT*_SUM0/4[GPIO<y>]
+ *         will have no effects.
+ *
+ * Whenever there is mode change, (GPIO_BIT_CFGx[INT_EN] or  GPIO_BIT_CFGx[INT_TYPE] or GPIO_MULTI_CAST[EN])
+ * software needs to write to  $GPIO_INT_CLR to clear up all pending/stale interrupts.
+ */
+union cvmx_gpio_multi_cast {
+	uint64_t u64;
+	struct cvmx_gpio_multi_cast_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_1_63                : 63;
+	uint64_t en                           : 1;  /**< Enable GPIO Interrupt Multicast mode
+                                                         When EN is set, GPIO<7:4> will function in
+                                                         multicast mode allowing these four GPIOs to
+                                                         interrupt multi-cores.
+                                                         Multicast functionality allows the GPIO to exist
+                                                         as per cnMIPS interrupts as opposed to a global
+                                                         interrupt. */
+#else
+	uint64_t en                           : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_gpio_multi_cast_s         cn61xx;
+	struct cvmx_gpio_multi_cast_s         cnf71xx;
+};
+typedef union cvmx_gpio_multi_cast cvmx_gpio_multi_cast_t;
+
+/**
+ * cvmx_gpio_pin_ena
+ *
+ * Notes:
+ * GPIO0-GPIO17 has dedicated pins.
+ * GPIO18 share pin with UART (UART0_CTS_L/GPIO_18), GPIO18 enabled when $GPIO_PIN_ENA[ENA18]=1
+ * GPIO19 share pin with UART (UART1_CTS_L/GPIO_19), GPIO18 enabled when $GPIO_PIN_ENA[ENA19]=1
+ */
+union cvmx_gpio_pin_ena {
+	uint64_t u64;
+	struct cvmx_gpio_pin_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t ena19                        : 1;  /**< If 0, UART1_CTS_L/GPIO_19 pin is UART pin
+                                                         If 1, UART1_CTS_L/GPIO_19 pin is GPIO19 pin */
+	uint64_t ena18                        : 1;  /**< If 0, UART0_CTS_L/GPIO_18 pin is UART pin
+                                                         If 1, UART0_CTS_L/GPIO_18 pin is GPIO18 pin */
+	uint64_t reserved_0_17                : 18;
+#else
+	uint64_t reserved_0_17                : 18;
+	uint64_t ena18                        : 1;
+	uint64_t ena19                        : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_gpio_pin_ena_s            cn66xx;
+};
+typedef union cvmx_gpio_pin_ena cvmx_gpio_pin_ena_t;
+
+/**
  * cvmx_gpio_rx_dat
  */
-union cvmx_gpio_rx_dat
-{
+union cvmx_gpio_rx_dat {
 	uint64_t u64;
-	struct cvmx_gpio_rx_dat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_rx_dat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t dat                          : 24; /**< GPIO Read Data */
 #else
@@ -400,9 +611,8 @@ union cvmx_gpio_rx_dat
 	} s;
 	struct cvmx_gpio_rx_dat_s             cn30xx;
 	struct cvmx_gpio_rx_dat_s             cn31xx;
-	struct cvmx_gpio_rx_dat_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_rx_dat_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t dat                          : 16; /**< GPIO Read Data */
 #else
@@ -418,20 +628,50 @@ union cvmx_gpio_rx_dat
 	struct cvmx_gpio_rx_dat_cn38xx        cn56xxp1;
 	struct cvmx_gpio_rx_dat_cn38xx        cn58xx;
 	struct cvmx_gpio_rx_dat_cn38xx        cn58xxp1;
+	struct cvmx_gpio_rx_dat_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t dat                          : 20; /**< GPIO Read Data */
+#else
+	uint64_t dat                          : 20;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn61xx;
 	struct cvmx_gpio_rx_dat_cn38xx        cn63xx;
 	struct cvmx_gpio_rx_dat_cn38xx        cn63xxp1;
+	struct cvmx_gpio_rx_dat_cn61xx        cn66xx;
+	struct cvmx_gpio_rx_dat_cn38xx        cn68xx;
+	struct cvmx_gpio_rx_dat_cn38xx        cn68xxp1;
+	struct cvmx_gpio_rx_dat_cn61xx        cnf71xx;
 };
 typedef union cvmx_gpio_rx_dat cvmx_gpio_rx_dat_t;
 
 /**
+ * cvmx_gpio_tim_ctl
+ */
+union cvmx_gpio_tim_ctl {
+	uint64_t u64;
+	struct cvmx_gpio_tim_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t sel                          : 4;  /**< Selects the GPIO pin to route to TIM */
+#else
+	uint64_t sel                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_gpio_tim_ctl_s            cn68xx;
+	struct cvmx_gpio_tim_ctl_s            cn68xxp1;
+};
+typedef union cvmx_gpio_tim_ctl cvmx_gpio_tim_ctl_t;
+
+/**
  * cvmx_gpio_tx_clr
  */
-union cvmx_gpio_tx_clr
-{
+union cvmx_gpio_tx_clr {
 	uint64_t u64;
-	struct cvmx_gpio_tx_clr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_tx_clr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t clr                          : 24; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
                                                          to '0'. When read, CLR returns the GPIO_TX_DAT
@@ -443,9 +683,8 @@ union cvmx_gpio_tx_clr
 	} s;
 	struct cvmx_gpio_tx_clr_s             cn30xx;
 	struct cvmx_gpio_tx_clr_s             cn31xx;
-	struct cvmx_gpio_tx_clr_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_tx_clr_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t clr                          : 16; /**< Bit mask to indicate which bits to drive to '0'. */
 #else
@@ -461,20 +700,33 @@ union cvmx_gpio_tx_clr
 	struct cvmx_gpio_tx_clr_cn38xx        cn56xxp1;
 	struct cvmx_gpio_tx_clr_cn38xx        cn58xx;
 	struct cvmx_gpio_tx_clr_cn38xx        cn58xxp1;
+	struct cvmx_gpio_tx_clr_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t clr                          : 20; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
+                                                         to '0'. When read, CLR returns the GPIO_TX_DAT
+                                                         storage. */
+#else
+	uint64_t clr                          : 20;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn61xx;
 	struct cvmx_gpio_tx_clr_cn38xx        cn63xx;
 	struct cvmx_gpio_tx_clr_cn38xx        cn63xxp1;
+	struct cvmx_gpio_tx_clr_cn61xx        cn66xx;
+	struct cvmx_gpio_tx_clr_cn38xx        cn68xx;
+	struct cvmx_gpio_tx_clr_cn38xx        cn68xxp1;
+	struct cvmx_gpio_tx_clr_cn61xx        cnf71xx;
 };
 typedef union cvmx_gpio_tx_clr cvmx_gpio_tx_clr_t;
 
 /**
  * cvmx_gpio_tx_set
  */
-union cvmx_gpio_tx_set
-{
+union cvmx_gpio_tx_set {
 	uint64_t u64;
-	struct cvmx_gpio_tx_set_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_tx_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t set                          : 24; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
                                                          to '1'. When read, SET returns the GPIO_TX_DAT
@@ -486,9 +738,8 @@ union cvmx_gpio_tx_set
 	} s;
 	struct cvmx_gpio_tx_set_s             cn30xx;
 	struct cvmx_gpio_tx_set_s             cn31xx;
-	struct cvmx_gpio_tx_set_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_tx_set_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t set                          : 16; /**< Bit mask to indicate which bits to drive to '1'. */
 #else
@@ -504,20 +755,67 @@ union cvmx_gpio_tx_set
 	struct cvmx_gpio_tx_set_cn38xx        cn56xxp1;
 	struct cvmx_gpio_tx_set_cn38xx        cn58xx;
 	struct cvmx_gpio_tx_set_cn38xx        cn58xxp1;
+	struct cvmx_gpio_tx_set_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t set                          : 20; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
+                                                         to '1'. When read, SET returns the GPIO_TX_DAT
+                                                         storage. */
+#else
+	uint64_t set                          : 20;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn61xx;
 	struct cvmx_gpio_tx_set_cn38xx        cn63xx;
 	struct cvmx_gpio_tx_set_cn38xx        cn63xxp1;
+	struct cvmx_gpio_tx_set_cn61xx        cn66xx;
+	struct cvmx_gpio_tx_set_cn38xx        cn68xx;
+	struct cvmx_gpio_tx_set_cn38xx        cn68xxp1;
+	struct cvmx_gpio_tx_set_cn61xx        cnf71xx;
 };
 typedef union cvmx_gpio_tx_set cvmx_gpio_tx_set_t;
 
 /**
  * cvmx_gpio_xbit_cfg#
+ *
+ * Notes:
+ * Only first 16 GPIO pins can introduce interrupts, GPIO_XBIT_CFG16(17,18,19)[INT_EN] and [INT_TYPE]
+ * will not be used, read out always zero.
  */
-union cvmx_gpio_xbit_cfgx
-{
+union cvmx_gpio_xbit_cfgx {
 	uint64_t u64;
-	struct cvmx_gpio_xbit_cfgx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_xbit_cfgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_17_63               : 47;
+	uint64_t synce_sel                    : 2;  /**< Selects the QLM clock output
+                                                         x0=Normal GPIO output
+                                                         01=GPIO QLM clock selected by CSR GPIO_CLK_QLM0
+                                                         11=GPIO QLM clock selected by CSR GPIO_CLK_QLM1 */
+	uint64_t clk_gen                      : 1;  /**< When TX_OE is set, GPIO pin becomes a clock */
+	uint64_t clk_sel                      : 2;  /**< Selects which of the 4 GPIO clock generators */
+	uint64_t fil_sel                      : 4;  /**< Global counter bit-select (controls sample rate) */
+	uint64_t fil_cnt                      : 4;  /**< Number of consecutive samples to change state */
+	uint64_t int_type                     : 1;  /**< Type of interrupt
+                                                         0 = level (default)
+                                                         1 = rising edge */
+	uint64_t int_en                       : 1;  /**< Bit mask to indicate which bits to raise interrupt */
+	uint64_t rx_xor                       : 1;  /**< Invert the GPIO pin */
+	uint64_t tx_oe                        : 1;  /**< Drive the GPIO pin as an output pin */
+#else
+	uint64_t tx_oe                        : 1;
+	uint64_t rx_xor                       : 1;
+	uint64_t int_en                       : 1;
+	uint64_t int_type                     : 1;
+	uint64_t fil_cnt                      : 4;
+	uint64_t fil_sel                      : 4;
+	uint64_t clk_sel                      : 2;
+	uint64_t clk_gen                      : 1;
+	uint64_t synce_sel                    : 2;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_gpio_xbit_cfgx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t fil_sel                      : 4;  /**< Global counter bit-select (controls sample rate) */
 	uint64_t fil_cnt                      : 4;  /**< Number of consecutive samples to change state */
@@ -532,10 +830,12 @@ union cvmx_gpio_xbit_cfgx
 	uint64_t fil_sel                      : 4;
 	uint64_t reserved_12_63               : 52;
 #endif
-	} s;
-	struct cvmx_gpio_xbit_cfgx_s          cn30xx;
-	struct cvmx_gpio_xbit_cfgx_s          cn31xx;
-	struct cvmx_gpio_xbit_cfgx_s          cn50xx;
+	} cn30xx;
+	struct cvmx_gpio_xbit_cfgx_cn30xx     cn31xx;
+	struct cvmx_gpio_xbit_cfgx_cn30xx     cn50xx;
+	struct cvmx_gpio_xbit_cfgx_s          cn61xx;
+	struct cvmx_gpio_xbit_cfgx_s          cn66xx;
+	struct cvmx_gpio_xbit_cfgx_s          cnf71xx;
 };
 typedef union cvmx_gpio_xbit_cfgx cvmx_gpio_xbit_cfgx_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-gpio.h b/sys/contrib/octeon-sdk/cvmx-gpio.h
index f728933..c10c702 100644
--- a/sys/contrib/octeon-sdk/cvmx-gpio.h
+++ b/sys/contrib/octeon-sdk/cvmx-gpio.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * General Purpose IO interface.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_GPIO_H__
@@ -64,17 +64,78 @@ extern "C" {
  * Clear the interrupt rising edge detector for the supplied
  * pins in the mask. Chips which have more than 16 GPIO pins
  * can't use them for interrupts.
- *
+ e
  * @param clear_mask Mask of pins to clear
  */
 static inline void cvmx_gpio_interrupt_clear(uint16_t clear_mask)
 {
+    if (OCTEON_IS_MODEL(OCTEON_CN61XX))
+    {
+        cvmx_gpio_multi_cast_t multi_cast;
+        cvmx_gpio_bit_cfgx_t gpio_bit;
+        int core = cvmx_get_core_num();
+        
+        multi_cast.u64 = cvmx_read_csr(CVMX_GPIO_MULTI_CAST);
+        gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(core));
+
+        /* If Multicast mode is enabled, and GPIO interrupt is enabled for
+           edge detection, then GPIO<4..7> interrupts are per core */
+        if (multi_cast.s.en && gpio_bit.s.int_en && gpio_bit.s.int_type)
+        {
+            /* Clear GPIO<4..7> per core */
+            cvmx_ciu_intx_sum0_t ciu_sum0;
+            ciu_sum0.u64 = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core * 2));
+            ciu_sum0.s.gpio = clear_mask & 0xf0;
+            cvmx_write_csr(CVMX_CIU_INTX_SUM0(core * 2), ciu_sum0.u64);
+
+            /* Clear other GPIO pins for all cores. */
+            cvmx_write_csr(CVMX_GPIO_INT_CLR, (clear_mask & ~0xf0));
+            return;
+        }
+    }
+    /* Clear GPIO pins state across all cores and common interrupt states. */ 
     cvmx_gpio_int_clr_t gpio_int_clr;
     gpio_int_clr.u64 = 0;
     gpio_int_clr.s.type = clear_mask;
     cvmx_write_csr(CVMX_GPIO_INT_CLR, gpio_int_clr.u64);
 }
 
+/**
+ * GPIO Output Pin
+ *
+ * @param bit   The GPIO to use
+ * @param mode  Drive GPIO as output pin or not.
+ *
+ */
+static inline void cvmx_gpio_cfg(int bit, int mode)
+{
+    if (bit > 15 && bit < 20)
+    {
+        /* CN61XX/CN66XX has 20 GPIO pins and only 16 are interruptable. */
+        if (OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))
+        {
+            cvmx_gpio_xbit_cfgx_t gpio_xbit;
+            gpio_xbit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(bit));
+            if (mode)
+                gpio_xbit.s.tx_oe = 1;
+            else
+                gpio_xbit.s.tx_oe = 0;
+            cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(bit), gpio_xbit.u64);
+        }
+        else
+            cvmx_dprintf("cvmx_gpio_cfg: Invalid GPIO bit(%d)\n", bit);
+    }
+    else
+    {
+        cvmx_gpio_bit_cfgx_t gpio_bit;
+        gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(bit));
+        if (mode)
+            gpio_bit.s.tx_oe = 1;
+        else
+            gpio_bit.s.tx_oe = 0;
+        cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), gpio_bit.u64);
+    }
+}
 
 /**
  * GPIO Read Data
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-board.c b/sys/contrib/octeon-sdk/cvmx-helper-board.c
index 9ce4a53..74502b6 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-board.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-board.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2011  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * Helper functions to abstract board specific data about
  * network ports from the rest of the cvmx-helper files.
  *
- * <hr>$Revision: 49627 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <linux/module.h>
@@ -72,6 +72,13 @@
 #include "cvmx-helper.h"
 #include "cvmx-helper-util.h"
 #include "cvmx-helper-board.h"
+#include "cvmx-gpio.h"
+#ifdef __U_BOOT__
+# include <libfdt.h>
+#else
+# include "libfdt/libfdt.h"
+#endif
+#include "cvmx-swap.h"
 #endif
 
 /**
@@ -84,6 +91,245 @@
  */
 CVMX_SHARED cvmx_helper_link_info_t (*cvmx_override_board_link_get)(int ipd_port) = NULL;
 
+#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL))
+
+static void cvmx_retry_i2c_write(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes, int ia_width_bytes, uint64_t data)
+{
+    int tries = 3;
+    int r;
+    do {
+        r = cvmx_twsix_write_ia(twsi_id, dev_addr, internal_addr, num_bytes, ia_width_bytes, data);
+    } while (tries-- > 0 && r < 0);
+}
+
+static int __pip_eth_node(const void *fdt_addr, int aliases, int ipd_port)
+{
+    char name_buffer[20];
+    const char*pip_path;
+    int pip, iface, eth;
+    int interface_num    = cvmx_helper_get_interface_num(ipd_port);
+    int interface_index  = cvmx_helper_get_interface_index_num(ipd_port);
+
+    pip_path = fdt_getprop(fdt_addr, aliases, "pip", NULL);
+    if (!pip_path)
+    {
+        cvmx_dprintf("ERROR: pip path not found in device tree\n");
+        return -1;
+    }
+    pip = fdt_path_offset(fdt_addr, pip_path);
+    if (pip < 0)
+    {
+        cvmx_dprintf("ERROR: pip not found in device tree\n");
+        return -1;
+    }
+#ifdef __U_BOOT__
+    sprintf(name_buffer, "interface@%d", interface_num);
+#else
+    snprintf(name_buffer, sizeof(name_buffer), "interface@%d", interface_num);
+#endif
+    iface =  fdt_subnode_offset(fdt_addr, pip, name_buffer);
+    if (iface < 0)
+    {
+        cvmx_dprintf("ERROR : pip intf %d not found in device tree \n",
+                     interface_num);
+        return -1;
+    }
+#ifdef __U_BOOT__
+    sprintf(name_buffer, "ethernet@%x", interface_index);
+#else
+    snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", interface_index);
+#endif
+    eth = fdt_subnode_offset(fdt_addr, iface, name_buffer);
+    if (eth < 0)
+    {
+        cvmx_dprintf("ERROR : pip interface@%d ethernet@%d not found in device "
+                     "tree\n", interface_num, interface_index);
+        return -1;
+    }
+    return eth;
+}
+
+static int __mix_eth_node(const void *fdt_addr, int aliases, int interface_index)
+{
+    char name_buffer[20];
+    const char*mix_path;
+    int mix;
+
+#ifdef __U_BOOT__
+    sprintf(name_buffer, "mix%d", interface_index);
+#else
+    snprintf(name_buffer, sizeof(name_buffer), "mix%d", interface_index);
+#endif
+    mix_path = fdt_getprop(fdt_addr, aliases, name_buffer, NULL);
+    if (!mix_path)
+    {
+        cvmx_dprintf("ERROR: mix%d path not found in device tree\n",interface_index);
+    }
+    mix = fdt_path_offset(fdt_addr, mix_path);
+    if (mix < 0)
+    {
+        cvmx_dprintf("ERROR: %s not found in device tree\n", mix_path);
+        return -1;
+    }
+    return mix;
+}
+
+typedef struct cvmx_phy_info
+{
+    int phy_addr;
+    int direct_connect;
+    cvmx_phy_type_t phy_type;
+}cvmx_phy_info_t;
+
+
+static int __mdiobus_addr_to_unit(uint32_t addr)
+{
+    int unit = (addr >> 7) & 3;
+    if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
+        unit >>= 1;
+    return unit;
+}
+/**
+ * Return the MII PHY address associated with the given IPD
+ * port. The phy address is obtained from the device tree.
+ *
+ * @param ipd_port Octeon IPD port to get the MII address for.
+ *
+ * @return MII PHY address and bus number or -1.
+ */
+
+static cvmx_phy_info_t __get_phy_info_from_dt(int ipd_port)
+{
+    const void *fdt_addr = CASTPTR(const void *, cvmx_sysinfo_get()->fdt_addr);
+    uint32_t *phy_handle;
+    int aliases, eth, phy, phy_parent, phandle, ret;
+    cvmx_phy_info_t phy_info;
+    int mdio_unit=-1;
+    const char *phy_comaptible_str;
+    uint32_t *phy_addr_ptr;
+
+    phy_info.phy_addr = -1;
+    phy_info.direct_connect = -1;
+    phy_info.phy_type = (cvmx_phy_type_t) -1;
+
+    if (!fdt_addr)
+    {
+        cvmx_dprintf("No device tree found.\n");
+        return phy_info;
+    }
+    aliases = fdt_path_offset(fdt_addr, "/aliases");
+    if (aliases < 0) {
+        cvmx_dprintf("Error: No /aliases node in device tree.\n");
+        return phy_info;
+    }
+    if (ipd_port < 0)
+    {
+        int interface_index = ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT;
+        eth = __mix_eth_node(fdt_addr, aliases, interface_index) ;
+    }
+    else
+    {
+        eth = __pip_eth_node(fdt_addr, aliases, ipd_port);
+    }
+    if (eth < 0 )
+    {
+        cvmx_dprintf("ERROR : cannot find interface for ipd_port=%d\n", ipd_port);
+        return phy_info;
+    }
+    /* Get handle to phy */
+    phy_handle = (uint32_t *) fdt_getprop(fdt_addr, eth, "phy-handle", NULL);
+    if (!phy_handle)
+    {
+        cvmx_dprintf("ERROR : phy handle not found in device tree ipd_port=%d"
+                     "\n", ipd_port);
+        return phy_info;
+    }
+    phandle = cvmx_be32_to_cpu(*phy_handle);
+    phy = fdt_node_offset_by_phandle(fdt_addr, phandle);
+    if (phy < 0)
+    {
+        cvmx_dprintf("ERROR : cannot find phy for ipd_port=%d ret=%d\n",
+                     ipd_port, phy);
+        return phy_info;
+    }
+    phy_comaptible_str = (const char *) fdt_getprop(fdt_addr, phy,
+                                                    "compatible", NULL);
+    if (!phy_comaptible_str)
+    {
+        cvmx_dprintf("ERROR : no compatible prop in phy\n");
+        return phy_info;
+    }
+    if (memcmp("marvell", phy_comaptible_str, strlen("marvell")) == 0)
+    {
+        phy_info.phy_type = MARVELL_GENERIC_PHY;
+    }
+    else if (memcmp("broadcom", phy_comaptible_str, strlen("broadcom")) == 0)
+    {
+        phy_info.phy_type = BROADCOM_GENERIC_PHY;
+    }
+    else
+    {
+        phy_info.phy_type = -1;
+    }
+
+    /* Check if PHY parent is the octeon MDIO bus. Some boards are connected
+       though a MUX and for them direct_connect_to_phy will be 0 */
+    phy_parent = fdt_parent_offset(fdt_addr, phy);
+    if (phy_parent < 0)
+    {
+        cvmx_dprintf("ERROR : cannot find phy parent for ipd_port=%d ret=%d\n",
+                     ipd_port, phy_parent);
+        return phy_info;
+    }
+    ret = fdt_node_check_compatible(fdt_addr, phy_parent,
+                                    "cavium,octeon-3860-mdio");
+    if (ret == 0)
+    {
+        phy_info.direct_connect = 1 ;
+        uint32_t *mdio_reg_base = (uint32_t *) fdt_getprop(fdt_addr, phy_parent,"reg",0);
+        if (mdio_reg_base == 0)
+        {
+            cvmx_dprintf("ERROR : unable to get reg property in phy mdio\n");
+            return phy_info;
+        }
+        mdio_unit = __mdiobus_addr_to_unit(mdio_reg_base[1]);
+        //cvmx_dprintf("phy parent=%s reg_base=%08x unit=%d \n",
+        //             fdt_get_name(fdt_addr,phy_parent, NULL), mdio_reg_base[1], mdio_unit);
+    }
+    else
+    {
+        phy_info.direct_connect = 0;
+        /* The PHY is not directly connected to the Octeon MDIO bus.
+           SE doesn't  have abstractions for MDIO MUX or MDIO MUX drivers and
+           hence for the non direct cases code will be needed which is
+           board specific.
+           For now the the MDIO Unit is defaulted to 1.
+        */
+        mdio_unit = 1;
+    }
+
+    phy_addr_ptr = (uint32_t *) fdt_getprop(fdt_addr, phy, "reg", NULL);
+    phy_info.phy_addr = cvmx_be32_to_cpu(*phy_addr_ptr) | mdio_unit << 8;
+    return phy_info;
+
+}
+
+/**
+ * Return the MII PHY address associated with the given IPD
+ * port. The phy address is obtained from the device tree.
+ *
+ * @param ipd_port Octeon IPD port to get the MII address for.
+ *
+ * @return MII PHY address and bus number or -1.
+ */
+
+int cvmx_helper_board_get_mii_address_from_dt(int ipd_port)
+{
+        cvmx_phy_info_t phy_info = __get_phy_info_from_dt(ipd_port);
+        return phy_info.phy_addr;
+}
+#endif
+
 /**
  * Return the MII PHY address associated with the given IPD
  * port. A result of -1 means there isn't a MII capable PHY
@@ -122,6 +368,16 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
     /*
      * For board types we can determine at runtime.
      */
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+        return -1;
+#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL))
+    if (cvmx_sysinfo_get()->fdt_addr)
+    {
+        cvmx_phy_info_t phy_info = __get_phy_info_from_dt(ipd_port);
+        //cvmx_dprintf("ipd_port=%d phy_addr=%d\n", ipd_port, phy_info.phy_addr);
+        if (phy_info.phy_addr >= 0) return phy_info.phy_addr;
+    }
+#endif
     switch (cvmx_sysinfo_get()->board_type)
     {
         case CVMX_BOARD_TYPE_SIM:
@@ -161,14 +417,6 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
                 return 9;
             else
                 return -1;
-        case CVMX_BOARD_TYPE_NAC38:
-            /* Board has 8 RGMII ports PHYs are 0-7 */
-            if ((ipd_port >= 0) && (ipd_port < 4))
-                return ipd_port;
-            else if ((ipd_port >= 16) && (ipd_port < 20))
-                return ipd_port - 16 + 4;
-            else
-                return -1;
         case CVMX_BOARD_TYPE_EBH3000:
             /* Board has dual SPI4 and no PHYs */
             return -1;
@@ -241,6 +489,37 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
                 return ipd_port + 1 + (1<<8);
             else
                 return -1;
+        case CVMX_BOARD_TYPE_EBB6800:
+            /* Board has 1 management ports */
+            if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
+                return 6;
+            if (ipd_port >= 0x800 && ipd_port < 0x900) /* QLM 0*/
+                return 0x101 + ((ipd_port >> 4) & 3); /* SMI 1*/
+            if (ipd_port >= 0xa00 && ipd_port < 0xb00) /* QLM 2*/
+                return 0x201 + ((ipd_port >> 4) & 3); /* SMI 2*/
+            if (ipd_port >= 0xb00 && ipd_port < 0xc00) /* QLM 3*/
+                return 0x301 + ((ipd_port >> 4) & 3); /* SMI 3*/
+            if (ipd_port >= 0xc00 && ipd_port < 0xd00) /* QLM 4*/
+                return 0x001 + ((ipd_port >> 4) & 3); /* SMI 0*/
+            return -1;
+        case CVMX_BOARD_TYPE_EP6300C:
+            if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
+                return 0x01;
+            if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT+1)
+                return 0x02;
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+            {
+                int interface = cvmx_helper_get_interface_num(ipd_port);
+                int mode = cvmx_helper_interface_get_mode(interface);
+                if (mode == CVMX_HELPER_INTERFACE_MODE_XAUI)
+                    return ipd_port;
+                else if ((ipd_port >= 0) && (ipd_port < 4))
+                    return ipd_port + 3;
+                else
+                    return -1;
+            }
+#endif
+            break;
         case CVMX_BOARD_TYPE_CUST_NB5:
             if (ipd_port == 2)
                 return 4;
@@ -253,7 +532,20 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
             else
                 return -1;
         case CVMX_BOARD_TYPE_NIC_XLE_10G:
+        case CVMX_BOARD_TYPE_NIC10E:
             return -1;  /* We don't use clause 45 MDIO for anything */
+        case CVMX_BOARD_TYPE_NIC4E:
+            if (ipd_port >= 0 && ipd_port <= 3)
+                return (ipd_port + 0x1f) & 0x1f;
+            else
+                return -1;
+        case CVMX_BOARD_TYPE_NIC2E:
+            if (ipd_port >= 0 && ipd_port <= 1)
+                return (ipd_port + 1);
+            else
+                return -1;
+        case CVMX_BOARD_TYPE_REDWING:
+	    return -1;  /* No PHYs connected to Octeon */
         case CVMX_BOARD_TYPE_BBGW_REF:
             return -1;  /* No PHYs are connected to Octeon, everything is through switch */
 	case CVMX_BOARD_TYPE_CUST_WSX16:
@@ -303,10 +595,329 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
 EXPORT_SYMBOL(cvmx_helper_board_get_mii_address);
 #endif
 
+/**
+ * @INTERNAL
+ * Get link state of marvell PHY
+ */
+static cvmx_helper_link_info_t __get_marvell_phy_link_state(int phy_addr)
+{
+    cvmx_helper_link_info_t  result;
+    int phy_status;
+
+    result.u64 = 0;
+    /*All the speed information can be read from register 17 in one go.*/
+    phy_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17);
+
+    /* If the resolve bit 11 isn't set, see if autoneg is turned off
+       (bit 12, reg 0). The resolve bit doesn't get set properly when
+       autoneg is off, so force it */
+    if ((phy_status & (1<<11)) == 0)
+    {
+        int auto_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0);
+        if ((auto_status & (1<<12)) == 0)
+            phy_status |= 1<<11;
+    }
+
+    /* Only return a link if the PHY has finished auto negotiation
+       and set the resolved bit (bit 11) */
+    if (phy_status & (1<<11))
+    {
+        result.s.link_up = 1;
+        result.s.full_duplex = ((phy_status>>13)&1);
+        switch ((phy_status>>14)&3)
+        {
+            case 0: /* 10 Mbps */
+                result.s.speed = 10;
+                break;
+            case 1: /* 100 Mbps */
+                result.s.speed = 100;
+                break;
+            case 2: /* 1 Gbps */
+                result.s.speed = 1000;
+                break;
+            case 3: /* Illegal */
+                result.u64 = 0;
+                break;
+        }
+    }
+    return result;
+}
+
+/**
+ * @INTERNAL
+ * Get link state of broadcom PHY
+ */
+static cvmx_helper_link_info_t __get_broadcom_phy_link_state(int phy_addr)
+{
+    cvmx_helper_link_info_t  result;
+    int phy_status;
+
+    result.u64 = 0;
+    /* Below we are going to read SMI/MDIO register 0x19 which works
+       on Broadcom parts */
+    phy_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0x19);
+    switch ((phy_status>>8) & 0x7)
+    {
+        case 0:
+            result.u64 = 0;
+            break;
+        case 1:
+            result.s.link_up = 1;
+            result.s.full_duplex = 0;
+            result.s.speed = 10;
+            break;
+        case 2:
+            result.s.link_up = 1;
+            result.s.full_duplex = 1;
+            result.s.speed = 10;
+            break;
+        case 3:
+            result.s.link_up = 1;
+            result.s.full_duplex = 0;
+            result.s.speed = 100;
+            break;
+        case 4:
+            result.s.link_up = 1;
+            result.s.full_duplex = 1;
+            result.s.speed = 100;
+            break;
+        case 5:
+            result.s.link_up = 1;
+            result.s.full_duplex = 1;
+            result.s.speed = 100;
+            break;
+        case 6:
+            result.s.link_up = 1;
+            result.s.full_duplex = 0;
+            result.s.speed = 1000;
+            break;
+        case 7:
+            result.s.link_up = 1;
+            result.s.full_duplex = 1;
+            result.s.speed = 1000;
+            break;
+    }
+    return result;
+}
+
+
+/**
+ * @INTERNAL
+ * Get link state using inband status
+ */
+static cvmx_helper_link_info_t __get_inband_link_state(int ipd_port)
+{
+    cvmx_helper_link_info_t  result;
+    cvmx_gmxx_rxx_rx_inbnd_t inband_status;
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    int index = cvmx_helper_get_interface_index_num(ipd_port);
+
+    result.u64 = 0;
+    inband_status.u64 = cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface));
+    result.s.link_up = inband_status.s.status;
+    result.s.full_duplex = inband_status.s.duplex;
+    switch (inband_status.s.speed)
+    {
+        case 0: /* 10 Mbps */
+            result.s.speed = 10;
+            break;
+        case 1: /* 100 Mbps */
+            result.s.speed = 100;
+            break;
+        case 2: /* 1 Gbps */
+            result.s.speed = 1000;
+            break;
+        case 3: /* Illegal */
+            result.u64 = 0;
+            break;
+    }
+    return result;
+}
+
+#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL))
+/**
+ * @INTERNAL
+ * Switch MDIO mux to the specified port.
+ */
+static int __switch_mdio_mux(int ipd_port)
+{
+    /* This method is board specific and doesn't use the device tree
+       information as SE doesn't implement MDIO MUX abstration */
+    switch (cvmx_sysinfo_get()->board_type)
+    {
+        case CVMX_BOARD_TYPE_EBB5600:
+        {
+            static unsigned char qlm_switch_addr = 0;
+            /* Board has 1 management port */
+            if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
+                return 0;
+            /* Board has 8 SGMII ports. 4 connected QLM1, 4 connected QLM3 */
+            if ((ipd_port >= 0) && (ipd_port < 4))
+            {
+                if (qlm_switch_addr != 0x3)
+                {
+                    qlm_switch_addr = 0x3;  /* QLM1 */
+                    cvmx_twsix_write_ia(0, 0x71, 0, 1, 1, qlm_switch_addr);
+                    cvmx_wait_usec(11000); /* Let the write complete */
+                }
+                return ipd_port+1 + (1<<8);
+            }
+            else if ((ipd_port >= 16) && (ipd_port < 20))
+            {
+                if (qlm_switch_addr != 0xC)
+                {
+                    qlm_switch_addr = 0xC;  /* QLM3 */
+                    cvmx_twsix_write_ia(0, 0x71, 0, 1, 1, qlm_switch_addr);
+                    cvmx_wait_usec(11000); /* Let the write complete */
+                }
+                return ipd_port-16+1 + (1<<8);
+            }
+            else
+                return -1;
+        }
+        case CVMX_BOARD_TYPE_EBB6600:
+        {
+            static unsigned char qlm_switch_addr = 0;
+            int old_twsi_switch_reg;
+            /* Board has 2 management ports */
+            if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) &&
+                (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
+                return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT + 4;
+            if ((ipd_port >= 0) && (ipd_port < 4)) /* QLM 2 */
+            {
+                if (qlm_switch_addr != 2)
+                {
+                    int tries;
+                    qlm_switch_addr = 2;
+                    tries = 3;
+                    do {
+                        old_twsi_switch_reg = cvmx_twsix_read8(0, 0x70, 0);
+                    } while (tries-- > 0 && old_twsi_switch_reg < 0);
+                    /* Set I2C MUX to enable port expander */
+                    cvmx_retry_i2c_write(0, 0x70, 0, 1, 0, 8);
+                    /* Set selecter to QLM 1 */
+                    cvmx_retry_i2c_write(0, 0x38, 0, 1, 0, 0xff);
+                    /* disable port expander */
+                    cvmx_retry_i2c_write(0, 0x70, 0, 1, 0, old_twsi_switch_reg);
+                }
+                return 0x101 + ipd_port;
+            }
+            else if ((ipd_port >= 16) && (ipd_port < 20)) /* QLM 1 */
+            {
+                if (qlm_switch_addr != 1)
+                {
+                    int tries;
+                    qlm_switch_addr = 1;
+                    tries = 3;
+                    do {
+                            old_twsi_switch_reg = cvmx_twsix_read8(0, 0x70, 0);
+                    } while (tries-- > 0 && old_twsi_switch_reg < 0);
+                    /* Set I2C MUX to enable port expander */
+                    cvmx_retry_i2c_write(0, 0x70, 0, 1, 0, 8);
+                    /* Set selecter to QLM 2 */
+                    cvmx_retry_i2c_write(0, 0x38, 0, 1, 0, 0xf7);
+                    /* disable port expander */
+                    cvmx_retry_i2c_write(0, 0x70, 0, 1, 0, old_twsi_switch_reg);
+                }
+                return 0x101 + (ipd_port - 16);
+            } else
+                return -1;
+        }
+        case CVMX_BOARD_TYPE_EBB6100:
+        {
+            static char gpio_configured = 0;
+
+            if (!gpio_configured)
+            {
+                cvmx_gpio_cfg(3, 1);
+                gpio_configured = 1;
+            }
+            /* Board has 2 management ports */
+            if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) &&
+                (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
+                return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT + 4;
+            if ((ipd_port >= 0) && (ipd_port < 4)) /* QLM 2 */
+            {
+                cvmx_gpio_set(1ull << 3);
+                return 0x101 + ipd_port;
+            }
+            else if ((ipd_port >= 16) && (ipd_port < 20)) /* QLM 0 */
+            {
+                cvmx_gpio_clear(1ull << 3);
+                return 0x101 + (ipd_port - 16);
+            }
+            else
+            {
+                printf("%s: Unknown ipd port 0x%x\n", __func__, ipd_port);
+                return -1;
+            }
+        }
+        default:
+        {
+            cvmx_dprintf("ERROR : unexpected mdio switch for board=%08x\n",
+                         cvmx_sysinfo_get()->board_type);
+            return -1;
+        }
+    }
+    /* should never get here */
+    return -1;
+}
+
+/**
+ * @INTERNAL
+ * This function is used ethernet ports link speed. This functions uses the
+ * device tree information to determine the phy address and type of PHY.
+ * The only supproted PHYs are Marvell and Broadcom.
+ *
+ * @param ipd_port IPD input port associated with the port we want to get link
+ *                 status for.
+ *
+ * @return The ports link status. If the link isn't fully resolved, this must
+ *         return zero.
+ */
+
+cvmx_helper_link_info_t __cvmx_helper_board_link_get_from_dt(int ipd_port)
+{
+    cvmx_helper_link_info_t  result;
+    cvmx_phy_info_t phy_info;
+
+    result.u64 = 0;
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+    {
+        /* The simulator gives you a simulated 1Gbps full duplex link */
+        result.s.link_up = 1;
+        result.s.full_duplex = 1;
+        result.s.speed = 1000;
+        return result;
+    }
+    phy_info = __get_phy_info_from_dt(ipd_port);
+    //cvmx_dprintf("ipd_port=%d phy_addr=%d dc=%d type=%d \n", ipd_port,
+    //             phy_info.phy_addr, phy_info.direct_connect, phy_info.phy_type);
+    if (phy_info.phy_addr < 0) return result;
+
+    if (phy_info.direct_connect == 0)
+        __switch_mdio_mux(ipd_port);
+    switch(phy_info.phy_type)
+    {
+        case BROADCOM_GENERIC_PHY:
+            result = __get_broadcom_phy_link_state(phy_info.phy_addr);
+            break;
+        case MARVELL_GENERIC_PHY:
+            result = __get_marvell_phy_link_state(phy_info.phy_addr);
+            break;
+        default:
+            result = __get_inband_link_state(ipd_port);
+    }
+    return result;
+
+}
+#endif
 
 /**
  * @INTERNAL
- * This function is the board specific method of determining an
+ * This function invokes  __cvmx_helper_board_link_get_from_dt when device tree
+ * info is available. When the device tree information is not available then
+ * this function is the board specific method of determining an
  * ethernet ports link speed. Most Octeon boards have Marvell PHYs
  * and are handled by the fall through case. This function must be
  * updated for boards that don't have the normal Marvell PHYs.
@@ -329,6 +940,13 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
     int phy_addr;
     int is_broadcom_phy = 0;
 
+#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL))
+    if (cvmx_sysinfo_get()->fdt_addr)
+    {
+        return __cvmx_helper_board_link_get_from_dt(ipd_port);
+    }
+#endif
+
     /* Give the user a chance to override the processing of this function */
     if (cvmx_override_board_link_get)
         return cvmx_override_board_link_get(ipd_port);
@@ -379,11 +997,16 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
             if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
                 is_broadcom_phy = 1;
             break;
+        case CVMX_BOARD_TYPE_EBB6100:
         case CVMX_BOARD_TYPE_EBB6300:   /* Only for MII mode, with PHY addresses 0/1. Default is RGMII*/
+        case CVMX_BOARD_TYPE_EBB6600:   /* Only for MII mode, with PHY addresses 0/1. Default is RGMII*/
             if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2))
                 && cvmx_helper_board_get_mii_address(ipd_port) >= 0 && cvmx_helper_board_get_mii_address(ipd_port) <= 1)
                 is_broadcom_phy = 1;
             break;
+        case CVMX_BOARD_TYPE_EP6300C:
+            is_broadcom_phy = 1;
+            break;
         case CVMX_BOARD_TYPE_CUST_NB5:
             /* Port 1 on these boards is always Gigabit */
             if (ipd_port == 1)
@@ -412,6 +1035,9 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
                 result.s.speed = 1000;
                 return result;
             }
+        case CVMX_BOARD_TYPE_NIC4E:
+        case CVMX_BOARD_TYPE_NIC2E:
+            is_broadcom_phy = 1;
             break;
 	/* Private vendor-defined boards.  */
 #if defined(OCTEON_VENDOR_LANNER)
@@ -435,128 +1061,27 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
 #endif
 
     phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
+    //cvmx_dprintf("ipd_port=%d phy_addr=%d broadcom=%d\n",
+    //             ipd_port, phy_addr, is_broadcom_phy);
     if (phy_addr != -1)
     {
         if (is_broadcom_phy)
         {
-            /* Below we are going to read SMI/MDIO register 0x19 which works
-                on Broadcom parts */
-            int phy_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0x19);
-            switch ((phy_status>>8) & 0x7)
-            {
-                case 0:
-                    result.u64 = 0;
-                    break;
-                case 1:
-                    result.s.link_up = 1;
-                    result.s.full_duplex = 0;
-                    result.s.speed = 10;
-                    break;
-                case 2:
-                    result.s.link_up = 1;
-                    result.s.full_duplex = 1;
-                    result.s.speed = 10;
-                    break;
-                case 3:
-                    result.s.link_up = 1;
-                    result.s.full_duplex = 0;
-                    result.s.speed = 100;
-                    break;
-                case 4:
-                    result.s.link_up = 1;
-                    result.s.full_duplex = 1;
-                    result.s.speed = 100;
-                    break;
-                case 5:
-                    result.s.link_up = 1;
-                    result.s.full_duplex = 1;
-                    result.s.speed = 100;
-                    break;
-                case 6:
-                    result.s.link_up = 1;
-                    result.s.full_duplex = 0;
-                    result.s.speed = 1000;
-                    break;
-                case 7:
-                    result.s.link_up = 1;
-                    result.s.full_duplex = 1;
-                    result.s.speed = 1000;
-                    break;
-            }
+            result =  __get_broadcom_phy_link_state(phy_addr);
         }
         else
         {
-            /* This code assumes we are using a Marvell Gigabit PHY. All the
-                speed information can be read from register 17 in one go. Somebody
-                using a different PHY will need to handle it above in the board
-                specific area */
-            int phy_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17);
-
-            /* If the resolve bit 11 isn't set, see if autoneg is turned off
-                (bit 12, reg 0). The resolve bit doesn't get set properly when
-                autoneg is off, so force it */
-            if ((phy_status & (1<<11)) == 0)
-            {
-                int auto_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0);
-                if ((auto_status & (1<<12)) == 0)
-                    phy_status |= 1<<11;
-            }
-
-            /* Only return a link if the PHY has finished auto negotiation
-                and set the resolved bit (bit 11) */
-            if (phy_status & (1<<11))
-            {
-#if defined(OCTEON_BOARD_CAPK_0100ND)
-                result.s.link_up = (phy_status>>10)&1;
-#else
-                result.s.link_up = 1;
-#endif
-                result.s.full_duplex = ((phy_status>>13)&1);
-                switch ((phy_status>>14)&3)
-                {
-                    case 0: /* 10 Mbps */
-                        result.s.speed = 10;
-                        break;
-                    case 1: /* 100 Mbps */
-                        result.s.speed = 100;
-                        break;
-                    case 2: /* 1 Gbps */
-                        result.s.speed = 1000;
-                        break;
-                    case 3: /* Illegal */
-                        result.u64 = 0;
-                        break;
-                }
-            }
+            /* This code assumes we are using a Marvell Gigabit PHY. */
+            result = __get_marvell_phy_link_state(phy_addr);
         }
     }
-    else if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
+    else if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN58XX)
+             || OCTEON_IS_MODEL(OCTEON_CN50XX))
     {
         /* We don't have a PHY address, so attempt to use in-band status. It is
             really important that boards not supporting in-band status never get
             here. Reading broken in-band status tends to do bad things */
-        cvmx_gmxx_rxx_rx_inbnd_t inband_status;
-        int interface = cvmx_helper_get_interface_num(ipd_port);
-        int index = cvmx_helper_get_interface_index_num(ipd_port);
-        inband_status.u64 = cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface));
-
-        result.s.link_up = inband_status.s.status;
-        result.s.full_duplex = inband_status.s.duplex;
-        switch (inband_status.s.speed)
-        {
-            case 0: /* 10 Mbps */
-                result.s.speed = 10;
-                break;
-            case 1: /* 100 Mbps */
-                result.s.speed = 100;
-                break;
-            case 2: /* 1 Gbps */
-                result.s.speed = 1000;
-                break;
-            case 3: /* Illegal */
-                result.u64 = 0;
-                break;
-        }
+        result = __get_inband_link_state(ipd_port);
     }
     else
     {
@@ -638,7 +1163,6 @@ int cvmx_helper_board_link_set_phy(int phy_addr, cvmx_helper_board_set_phy_link_
         cvmx_mdio_phy_reg_control_t reg_control;
         cvmx_mdio_phy_reg_status_t reg_status;
         cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
-        cvmx_mdio_phy_reg_extended_status_t reg_extended_status;
         cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
 
         reg_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_STATUS);
@@ -650,7 +1174,6 @@ int cvmx_helper_board_link_set_phy(int phy_addr, cvmx_helper_board_set_phy_link_
         reg_autoneg_adver.s.advert_100base_tx_half = 0;
         if (reg_status.s.capable_extended_status)
         {
-            reg_extended_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_EXTENDED_STATUS);
             reg_control_1000.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000);
             reg_control_1000.s.advert_1000base_t_full = 0;
             reg_control_1000.s.advert_1000base_t_half = 0;
@@ -762,6 +1285,9 @@ int __cvmx_helper_board_interface_probe(int interface, int supported_ports)
         case CVMX_BOARD_TYPE_EBT5810:
             return 1;  /* Two ports on each SPI: 1 hooked to MAC, 1 loopback
                        ** Loopback disabled by default. */
+        case CVMX_BOARD_TYPE_NIC2E:
+            if (interface == 0)
+                return 2;
 #if defined(OCTEON_VENDOR_LANNER)
 	case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
 	    if (interface == 1)
@@ -856,6 +1382,58 @@ int __cvmx_helper_board_hardware_enable(int interface)
  */
 cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void)
 {
+#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL))
+    const void *fdt_addr = CASTPTR(const void *, cvmx_sysinfo_get()->fdt_addr);
+    int nodeoffset;
+    const void *nodep;
+    int len;
+    uint32_t speed = 0;
+    const char *type = NULL;
+
+    if (fdt_addr)
+    {
+        nodeoffset = fdt_path_offset(fdt_addr, "/soc/uctl");
+        if (nodeoffset < 0)
+            nodeoffset = fdt_path_offset(fdt_addr, "/soc/usbn");
+
+        if (nodeoffset >= 0)
+        {
+            nodep = fdt_getprop(fdt_addr, nodeoffset, "refclk-type", &len);
+            if (nodep != NULL && len > 0)
+                type = (const char *)nodep;
+            else
+                type = "unknown";
+            nodep = fdt_getprop(fdt_addr, nodeoffset, "refclk-frequency", &len);
+            if (nodep != NULL && len == sizeof(uint32_t))
+                speed = fdt32_to_cpu(*(int *)nodep);
+            else
+                speed = 0;
+            if (!strcmp(type, "crystal"))
+            {
+                if (speed == 0 || speed == 12000000)
+                    return USB_CLOCK_TYPE_CRYSTAL_12;
+                else
+                    printf("Warning: invalid crystal speed for USB clock type in FDT\n");
+            }
+            else if (!strcmp(type, "external"))
+            {
+                switch (speed) {
+                case 12000000:
+                    return USB_CLOCK_TYPE_REF_12;
+                case 24000000:
+                    return USB_CLOCK_TYPE_REF_24;
+                case 0:
+                case 48000000:
+                    return USB_CLOCK_TYPE_REF_48;
+                default:
+                    printf("Warning: invalid USB clock speed of %u hz in FDT\n", speed);
+                }
+            }
+            else
+                printf("Warning: invalid USB reference clock type \"%s\" in FDT\n", type ? type : "NULL");
+        }
+    }
+#endif
     switch (cvmx_sysinfo_get()->board_type)
     {
         case CVMX_BOARD_TYPE_BBGW_REF:
@@ -869,8 +1447,16 @@ cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void)
 #if defined(OCTEON_BOARD_CAPK_0100ND)
 	case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
 #endif
+        case CVMX_BOARD_TYPE_NIC10E_66:
             return USB_CLOCK_TYPE_CRYSTAL_12;
+        case CVMX_BOARD_TYPE_NIC10E:
+            return USB_CLOCK_TYPE_REF_12;
+        default:
+            break;
     }
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX)	/* Most boards except NIC10e use a 12MHz crystal */
+        || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
+        return USB_CLOCK_TYPE_CRYSTAL_12;
     return USB_CLOCK_TYPE_REF_48;
 }
 
@@ -892,6 +1478,7 @@ int __cvmx_helper_board_usb_get_num_ports(int supported_ports)
     switch (cvmx_sysinfo_get()->board_type)
     {
         case CVMX_BOARD_TYPE_NIC_XLE_4G:
+        case CVMX_BOARD_TYPE_NIC2E:
             return 0;
     }
 
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-board.h b/sys/contrib/octeon-sdk/cvmx-helper-board.h
index 2e7dc31..d45688e 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-board.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-board.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * Helper functions to abstract board specific data about
  * network ports from the rest of the cvmx-helper files.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifndef __CVMX_HELPER_BOARD_H__
 #define __CVMX_HELPER_BOARD_H__
@@ -67,6 +67,11 @@ typedef enum {
 } cvmx_helper_board_usb_clock_types_t;
 
 typedef enum {
+    BROADCOM_GENERIC_PHY,
+    MARVELL_GENERIC_PHY,
+} cvmx_phy_type_t;
+
+typedef enum {
     set_phy_link_flags_autoneg                  = 0x1,
     set_phy_link_flags_flow_control_dont_touch  = 0x0 << 1,
     set_phy_link_flags_flow_control_enable      = 0x1 << 1,
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-cfg.c b/sys/contrib/octeon-sdk/cvmx-helper-cfg.c
new file mode 100644
index 0000000..af1439c
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-helper-cfg.c
@@ -0,0 +1,717 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Helper Functions for the Configuration Framework
+ *
+ * <hr>$Revision: 0 $<hr>
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-util.h>
+#include <asm/octeon/cvmx-helper-cfg.h>
+#include <asm/octeon/cvmx-helper-ilk.h>
+#include <asm/octeon/cvmx-ilk.h>
+#include <asm/octeon/cvmx-config.h>
+#else
+#include "cvmx.h"
+#include "cvmx-bootmem.h"
+#include "cvmx-helper.h"
+#include "cvmx-helper-util.h"
+#include "cvmx-helper-cfg.h"
+#include "cvmx-ilk.h"
+#include "cvmx-helper-ilk.h"
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "cvmx-config.h"
+#include "executive-config.h"
+#endif
+#endif
+
+#if defined(min)
+#else
+#define min( a, b ) ( ( a ) < ( b ) ) ? ( a ) : ( b )
+#endif
+
+/* #define CVMX_HELPER_CFG_DEBUG */
+
+/*
+ * Per physical port
+ */
+struct cvmx_cfg_port_param {
+	int8_t	ccpp_pknd;
+	int8_t	ccpp_bpid;
+	int8_t	ccpp_pko_port_base;
+	int8_t	ccpp_pko_num_ports;
+	uint8_t	ccpp_pko_nqueues;	/*
+					 * When the user explicitly
+					 * assigns queues,
+					 * cvmx_cfg_pko_nqueue_pool[
+					 *     ccpp_pko_nqueues ... 
+					 *     ccpp_pko_nqueues + 
+					 *     ccpp_pko_num_ports - 1]
+					 * are the numbers of PKO queues
+					 * assigned to the PKO ports for
+					 * this physical port.
+					 */
+};
+
+/*
+ * Per pko_port
+ */
+struct cvmx_cfg_pko_port_param {
+	int16_t	ccppp_queue_base;
+	int16_t	ccppp_num_queues;
+};
+
+/*
+ * A map from pko_port to
+ *     interface,
+ *     index, and
+ *     pko engine id
+ */
+struct cvmx_cfg_pko_port_map {
+	int16_t ccppl_interface;
+	int16_t ccppl_index;
+	int16_t ccppl_eid;
+};
+
+/*
+ * This is for looking up pko_base_port and pko_nport for ipd_port
+ */
+struct cvmx_cfg_pko_port_pair {
+	int8_t ccppp_base_port;
+	int8_t ccppp_nports;
+};
+
+static CVMX_SHARED struct cvmx_cfg_port_param cvmx_cfg_port
+    [CVMX_HELPER_CFG_MAX_IFACE][CVMX_HELPER_CFG_MAX_PORT_PER_IFACE] =
+    {[0 ... CVMX_HELPER_CFG_MAX_IFACE - 1] =
+        {[0 ... CVMX_HELPER_CFG_MAX_PORT_PER_IFACE - 1] =
+            {CVMX_HELPER_CFG_INVALID_VALUE,
+    	     CVMX_HELPER_CFG_INVALID_VALUE,
+    	     CVMX_HELPER_CFG_INVALID_VALUE,
+    	     CVMX_HELPER_CFG_INVALID_VALUE,
+    	     CVMX_HELPER_CFG_INVALID_VALUE}}};
+
+/*
+ * Indexed by the pko_port number
+ */
+static CVMX_SHARED struct cvmx_cfg_pko_port_param cvmx_cfg_pko_port
+    [CVMX_HELPER_CFG_MAX_PKO_PORT] =
+    {[0 ... CVMX_HELPER_CFG_MAX_PKO_PORT - 1] =
+        {CVMX_HELPER_CFG_INVALID_VALUE,
+	 CVMX_HELPER_CFG_INVALID_VALUE}};
+
+static CVMX_SHARED struct cvmx_cfg_pko_port_map cvmx_cfg_pko_port_map
+    [CVMX_HELPER_CFG_MAX_PKO_PORT] = 
+        {[0 ... CVMX_HELPER_CFG_MAX_PKO_PORT - 1] =
+            {CVMX_HELPER_CFG_INVALID_VALUE,
+	     CVMX_HELPER_CFG_INVALID_VALUE,
+             CVMX_HELPER_CFG_INVALID_VALUE}};
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+/*
+ * This array assists translation from ipd_port to pko_port.
+ * The ``16'' is the rounded value for the 3rd 4-bit value of
+ * ipd_port, used to differentiate ``interfaces.''
+ */
+static CVMX_SHARED struct cvmx_cfg_pko_port_pair ipd2pko_port_cache[16]
+    [CVMX_HELPER_CFG_MAX_PORT_PER_IFACE] =
+    {[0 ... 15] = 
+        {[0 ... CVMX_HELPER_CFG_MAX_PORT_PER_IFACE - 1] =
+	    {CVMX_HELPER_CFG_INVALID_VALUE,
+	     CVMX_HELPER_CFG_INVALID_VALUE}}};
+
+#ifdef CVMX_USER_DEFINED_HELPER_CONFIG_INIT
+
+static CVMX_SHARED int cvmx_cfg_default_pko_nqueues = 1;
+
+/*
+ * A pool for holding the pko_nqueues for the pko_ports assigned to a
+ * physical port.
+ */
+static CVMX_SHARED uint8_t cvmx_cfg_pko_nqueue_pool
+    [CVMX_HELPER_CFG_MAX_PKO_QUEUES] = 
+    {[0 ... CVMX_HELPER_CFG_MAX_PKO_QUEUES - 1] = 1};
+
+#endif
+#endif
+
+/*
+ * Options
+ *
+ * Each array-elem's intial value is also the option's default value.
+ */
+static CVMX_SHARED uint64_t cvmx_cfg_opts[CVMX_HELPER_CFG_OPT_MAX] =
+    {[0 ... CVMX_HELPER_CFG_OPT_MAX - 1] = 1};
+
+/*
+ * MISC
+ */
+static CVMX_SHARED int cvmx_cfg_max_pko_engines; /* # of PKO DMA engines 
+						    allocated */
+int __cvmx_helper_cfg_pknd(int interface, int index)
+{
+    return cvmx_cfg_port[interface][index].ccpp_pknd;
+}
+
+int __cvmx_helper_cfg_bpid(int interface, int index)
+{
+    return cvmx_cfg_port[interface][index].ccpp_bpid;
+}
+
+int __cvmx_helper_cfg_pko_port_base(int interface, int index)
+{
+    return cvmx_cfg_port[interface][index].ccpp_pko_port_base;
+}
+
+int __cvmx_helper_cfg_pko_port_num(int interface, int index)
+{
+    return cvmx_cfg_port[interface][index].ccpp_pko_num_ports;
+}
+
+int __cvmx_helper_cfg_pko_queue_num(int pko_port)
+{
+    return cvmx_cfg_pko_port[pko_port].ccppp_num_queues;
+}
+
+int __cvmx_helper_cfg_pko_queue_base(int pko_port)
+{
+    return cvmx_cfg_pko_port[pko_port].ccppp_queue_base;
+}
+
+int __cvmx_helper_cfg_pko_max_queue(void)
+{
+    int i;
+
+    i = CVMX_HELPER_CFG_MAX_PKO_PORT - 1;
+
+    while (i >= 0)
+    {
+        if (cvmx_cfg_pko_port[i].ccppp_queue_base !=
+	    CVMX_HELPER_CFG_INVALID_VALUE)
+	{
+	    cvmx_helper_cfg_assert(cvmx_cfg_pko_port[i].ccppp_num_queues > 0);
+	    return (cvmx_cfg_pko_port[i].ccppp_queue_base +
+	        cvmx_cfg_pko_port[i].ccppp_num_queues);
+	}
+	i --;
+    }
+
+    cvmx_helper_cfg_assert(0); /* shouldn't get here */
+    
+    return 0;
+}
+
+int __cvmx_helper_cfg_pko_max_engine(void)
+{
+    return cvmx_cfg_max_pko_engines;
+}
+
+int cvmx_helper_cfg_opt_set(cvmx_helper_cfg_option_t opt, uint64_t val)
+{
+    if (opt >= CVMX_HELPER_CFG_OPT_MAX)
+        return -1;
+    
+    cvmx_cfg_opts[opt] = val;
+
+    return 0;
+}
+
+uint64_t cvmx_helper_cfg_opt_get(cvmx_helper_cfg_option_t opt)
+{
+    if (opt >= CVMX_HELPER_CFG_OPT_MAX)
+        return (uint64_t)CVMX_HELPER_CFG_INVALID_VALUE;
+
+    return cvmx_cfg_opts[opt];
+}
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(__cvmx_helper_cfg_init);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pknd);
+EXPORT_SYMBOL(__cvmx_helper_cfg_bpid);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pko_port_base);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pko_port_num);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pko_queue_base);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pko_queue_num);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pko_max_queue);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pko_port_interface);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pko_port_index);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pko_port_eid);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pko_max_engine);
+EXPORT_SYMBOL(cvmx_helper_cfg_opt_get);
+EXPORT_SYMBOL(cvmx_helper_cfg_opt_set);
+EXPORT_SYMBOL(cvmx_helper_cfg_ipd2pko_port_base);
+EXPORT_SYMBOL(cvmx_helper_cfg_ipd2pko_port_num);
+#endif
+
+#ifdef CVMX_ENABLE_HELPER_FUNCTIONS
+
+#ifdef CVMX_HELPER_CFG_DEBUG
+void cvmx_helper_cfg_show_cfg(void)
+{
+    int i, j;
+
+    for (i = 0; i < cvmx_helper_get_number_of_interfaces(); i++)
+    {
+	cvmx_dprintf(
+	    "cvmx_helper_cfg_show_cfg: interface%d mode %10s nports%4d\n", i,
+	    cvmx_helper_interface_mode_to_string(cvmx_helper_interface_get_mode(i)),
+	    cvmx_helper_interface_enumerate(i));
+
+	for (j = 0; j < cvmx_helper_interface_enumerate(i); j++)
+	{
+	    cvmx_dprintf("\tpknd[%i][%d]%d", i, j,
+	        __cvmx_helper_cfg_pknd(i, j));
+	    cvmx_dprintf(" pko_port_base[%i][%d]%d", i, j,
+	        __cvmx_helper_cfg_pko_port_base(i, j));
+	    cvmx_dprintf(" pko_port_num[%i][%d]%d\n", i, j,
+	        __cvmx_helper_cfg_pko_port_num(i, j));
+	}
+    }
+
+    for (i = 0; i < CVMX_HELPER_CFG_MAX_PKO_PORT; i++)
+    {
+	if (__cvmx_helper_cfg_pko_queue_base(i) !=
+	    CVMX_HELPER_CFG_INVALID_VALUE)
+	{
+            cvmx_dprintf("cvmx_helper_cfg_show_cfg: pko_port%d qbase%d nqueues%d "
+	        "interface%d index%d\n", i,
+		__cvmx_helper_cfg_pko_queue_base(i),
+		__cvmx_helper_cfg_pko_queue_num(i),
+		__cvmx_helper_cfg_pko_port_interface(i),
+		__cvmx_helper_cfg_pko_port_index(i));
+        }
+    }
+}
+#endif
+
+/*
+ * initialize cvmx_cfg_pko_port_map
+ */
+static void cvmx_helper_cfg_init_pko_port_map(void)
+{
+    int i, j, k;
+    int pko_eid;
+    int pko_port_base, pko_port_max;
+    cvmx_helper_interface_mode_t mode;
+
+    /*
+     * one pko_eid is allocated to each port except for ILK, NPI, and
+     * LOOP. Each of the three has one eid.
+     */
+    pko_eid = 0;
+    for (i = 0; i < cvmx_helper_get_number_of_interfaces(); i++)
+    {
+	mode = cvmx_helper_interface_get_mode(i);
+        for (j = 0; j < cvmx_helper_interface_enumerate(i); j++)
+	{
+	    pko_port_base = cvmx_cfg_port[i][j].ccpp_pko_port_base;
+	    pko_port_max = pko_port_base +
+	        cvmx_cfg_port[i][j].ccpp_pko_num_ports;
+	    cvmx_helper_cfg_assert(pko_port_base !=
+	        CVMX_HELPER_CFG_INVALID_VALUE);
+	    cvmx_helper_cfg_assert(pko_port_max >= pko_port_base);
+	    for (k = pko_port_base; k < pko_port_max; k++)
+	    {
+	        cvmx_cfg_pko_port_map[k].ccppl_interface = i;
+	        cvmx_cfg_pko_port_map[k].ccppl_index = j;
+	        cvmx_cfg_pko_port_map[k].ccppl_eid = pko_eid;
+	    }
+
+#if 0
+	    /*
+	     * For a physical port that is not configured a PKO port,
+	     * pko_port_base here equals to pko_port_max. In this
+	     * case, the physical port does not take a DMA engine.
+	     */
+	    if (pko_port_base > pko_port_max)
+#endif
+	        if (!(mode == CVMX_HELPER_INTERFACE_MODE_NPI ||
+	            mode == CVMX_HELPER_INTERFACE_MODE_LOOP ||
+	            mode == CVMX_HELPER_INTERFACE_MODE_ILK))
+	            pko_eid ++;
+	}
+
+	if (mode == CVMX_HELPER_INTERFACE_MODE_NPI ||
+	    mode == CVMX_HELPER_INTERFACE_MODE_LOOP ||
+	    mode == CVMX_HELPER_INTERFACE_MODE_ILK)
+	        pko_eid ++;
+    }
+
+    /*
+     * Legal pko_eids [0, 0x13] should not be exhausted.
+     */
+    cvmx_helper_cfg_assert(pko_eid <= 0x14);
+
+    cvmx_cfg_max_pko_engines = pko_eid;
+}
+#endif
+
+int __cvmx_helper_cfg_pko_port_interface(int pko_port)
+{
+    return cvmx_cfg_pko_port_map[pko_port].ccppl_interface;
+}
+
+int __cvmx_helper_cfg_pko_port_index(int pko_port)
+{
+    return cvmx_cfg_pko_port_map[pko_port].ccppl_index;
+}
+
+int __cvmx_helper_cfg_pko_port_eid(int pko_port)
+{
+    return cvmx_cfg_pko_port_map[pko_port].ccppl_eid;
+}
+
+/**
+ * Perform common init tasks for all chips.
+ * @return 1 for the caller to continue init and 0 otherwise.
+ *
+ * Note: ``common'' means this function is executed regardless of
+ * 	- chip, and
+ * 	- CVMX_ENABLE_HELPER_FUNCTIONS.
+ *
+ * This function decides based on these conditions if the
+ * configuration stage of the init process should continue.
+ *
+ * This is only meant to be called by __cvmx_helper_cfg_init().
+ */
+static int __cvmx_helper_cfg_init_common(void)
+{
+    int val;
+
+#ifndef CVMX_ENABLE_HELPER_FUNCTIONS
+    val = 0;
+#else
+    val = (octeon_has_feature(OCTEON_FEATURE_PKND));
+#endif
+
+    return val;
+}
+
+#define IPD2PKO_CACHE_Y(ipd_port)	(ipd_port) >> 8
+#define IPD2PKO_CACHE_X(ipd_port)	(ipd_port) & 0xff
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+/*
+ * ipd_port to pko_port translation cache
+ */
+static int __cvmx_helper_cfg_init_ipd2pko_cache(void)
+{
+    int i, j, n;
+    int ipd_y, ipd_x, ipd_port;
+
+    for (i = 0; i < cvmx_helper_get_number_of_interfaces(); i++)
+    {
+	n = cvmx_helper_interface_enumerate(i);
+    
+        for (j = 0; j < n; j++)
+	{
+	    ipd_port = cvmx_helper_get_ipd_port(i, j);
+	    ipd_y = IPD2PKO_CACHE_Y(ipd_port);
+	    ipd_x = IPD2PKO_CACHE_X(ipd_port);
+	    ipd2pko_port_cache[ipd_y]
+	        [(ipd_port & 0x800) ? ((ipd_x >> 4) & 3) : ipd_x] = 
+		(struct cvmx_cfg_pko_port_pair)
+		{__cvmx_helper_cfg_pko_port_base(i, j),
+		 __cvmx_helper_cfg_pko_port_num(i, j)};
+	}
+    }
+
+    return 0;
+}
+
+int cvmx_helper_cfg_ipd2pko_port_base(int ipd_port)
+{
+	int ipd_y, ipd_x;
+
+        ipd_y = IPD2PKO_CACHE_Y(ipd_port);
+	ipd_x = IPD2PKO_CACHE_X(ipd_port);
+
+        return ipd2pko_port_cache[ipd_y]
+	    [(ipd_port & 0x800) ? ((ipd_x >> 4) & 3) : ipd_x].ccppp_base_port;
+}
+
+int cvmx_helper_cfg_ipd2pko_port_num(int ipd_port)
+{
+	int ipd_y, ipd_x;
+
+        ipd_y = IPD2PKO_CACHE_Y(ipd_port);
+	ipd_x = IPD2PKO_CACHE_X(ipd_port);
+
+        return ipd2pko_port_cache[ipd_y]
+	    [(ipd_port & 0x800) ? ((ipd_x >> 4) & 3) : ipd_x].ccppp_nports;
+}
+#endif
+
+#ifdef CVMX_ENABLE_HELPER_FUNCTIONS
+#ifdef CVMX_USER_DEFINED_HELPER_CONFIG_INIT
+/**
+ * Return the number of queues assigned to this pko_port by user
+ *
+ * @param pko_port
+ * @return the number of queues for this pko_port
+ *
+ * Note: Called after the pko_port map is set up.
+ */
+static int __cvmx_ucfg_nqueues(int pko_port)
+{
+    int interface, index;
+    int i, k;
+
+    interface = __cvmx_helper_cfg_pko_port_interface(pko_port);
+    index = __cvmx_helper_cfg_pko_port_index(pko_port);
+
+    /*
+     * pko_port belongs to no physical port,
+     * don't assign a queue to it.
+     */
+    if (interface == CVMX_HELPER_CFG_INVALID_VALUE ||
+        index == CVMX_HELPER_CFG_INVALID_VALUE)
+	return 0;
+
+    /*
+     * Assign the default number of queues to those pko_ports not
+     * assigned explicitly.
+     */
+    i = cvmx_cfg_port[interface][index].ccpp_pko_nqueues;
+    if (i == (uint8_t)CVMX_HELPER_CFG_INVALID_VALUE)
+        return cvmx_cfg_default_pko_nqueues;
+
+    /*
+     * The user has assigned nqueues to this pko_port,
+     * recorded in the pool.
+     */
+    k = pko_port - cvmx_cfg_port[interface][index].ccpp_pko_port_base;
+    cvmx_helper_cfg_assert(k < 
+        cvmx_cfg_port[interface][index].ccpp_pko_num_ports);
+    return cvmx_cfg_pko_nqueue_pool[i + k];
+}
+
+#else
+
+/**
+ * Return the number of queues to be assigned to this pko_port
+ *
+ * @param pko_port
+ * @return the number of queues for this pko_port
+ *
+ * Note: This function exists for backward compatibility.
+ * CVMX_PKO_QUEUES_PER_PORT_XXXX defines no of queues per HW port.
+ * pko_port is equivalent in pre-o68 SDK.
+ */
+static int cvmx_helper_cfg_dft_nqueues(int pko_port)
+{
+    cvmx_helper_interface_mode_t mode;
+    int interface;
+    int n;
+
+#ifndef CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE0
+#define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE0 1
+#endif
+
+#ifndef CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE1
+#define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE1 1
+#endif
+
+#ifndef CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE2
+#define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE2 1
+#endif
+
+#ifndef CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE3
+#define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE3 1
+#endif
+
+#ifndef CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE4
+#define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE4 1
+#endif
+
+    n = 1;
+    interface = __cvmx_helper_cfg_pko_port_interface(pko_port);
+    if (interface == 0)
+    {
+#ifdef CVMX_PKO_QUEUES_PER_PORT_INTERFACE0
+	n = CVMX_PKO_QUEUES_PER_PORT_INTERFACE0;
+#endif
+    }
+    if (interface == 1)
+    {
+#ifdef CVMX_PKO_QUEUES_PER_PORT_INTERFACE1
+	n = CVMX_PKO_QUEUES_PER_PORT_INTERFACE1;
+#endif
+    }
+
+    if (interface == 2)
+    {
+#ifdef CVMX_PKO_QUEUES_PER_PORT_INTERFACE2
+	n = CVMX_PKO_QUEUES_PER_PORT_INTERFACE2;
+#endif
+    }
+    if (interface == 3)
+    {
+#ifdef CVMX_PKO_QUEUES_PER_PORT_INTERFACE3
+	n = CVMX_PKO_QUEUES_PER_PORT_INTERFACE3;
+#endif
+    }
+    if (interface == 4)
+    {
+#ifdef CVMX_PKO_QUEUES_PER_PORT_INTERFACE4
+	n = CVMX_PKO_QUEUES_PER_PORT_INTERFACE4;
+#endif
+    }
+
+    mode = cvmx_helper_interface_get_mode(interface);
+    if (mode == CVMX_HELPER_INTERFACE_MODE_LOOP)
+    {
+#ifdef CVMX_PKO_QUEUES_PER_PORT_LOOP
+	n = CVMX_PKO_QUEUES_PER_PORT_LOOP;
+#endif
+    }
+    if (mode == CVMX_HELPER_INTERFACE_MODE_NPI)
+    {
+#ifdef CVMX_PKO_QUEUES_PER_PORT_PCI
+	n = CVMX_PKO_QUEUES_PER_PORT_PCI;
+#endif
+    }
+
+    return n;
+}
+#endif /* CVMX_USER_DEFINED_HELPER_CONFIG_INIT */
+#endif /* CVMX_ENABLE_HELPER_FUNCTIONS */
+
+int __cvmx_helper_cfg_init(void)
+{
+#ifdef CVMX_ENABLE_HELPER_FUNCTIONS
+    struct cvmx_cfg_port_param *pport;
+    int cvmx_cfg_default_pko_nports;
+    int pknd, bpid, pko_port_base;
+    int qbase;
+    int i, j, n;
+
+    cvmx_cfg_default_pko_nports = 1;
+#endif
+    
+    if (!__cvmx_helper_cfg_init_common())
+        return 0;
+
+#ifdef CVMX_ENABLE_HELPER_FUNCTIONS
+
+#ifdef CVMX_USER_DEFINED_HELPER_CONFIG_INIT
+{
+	int cvmx_ucfg_nq;
+	cvmx_ucfg_nq = 0;
+#include "cvmx-helper-cfg-init.c"
+}
+#endif
+
+    /*
+     * per-port parameters
+     */
+    pknd = 0;
+    bpid = 0;
+    pko_port_base = 0;
+    
+    for (i = 0; i < cvmx_helper_get_number_of_interfaces(); i++)
+    {
+	n = cvmx_helper_interface_enumerate(i);
+    
+        pport = cvmx_cfg_port[i];
+        for (j = 0; j < n; j++, pport++)
+	{
+	    int t;
+
+	    t = cvmx_cfg_default_pko_nports;
+	    if (pport->ccpp_pko_num_ports != CVMX_HELPER_CFG_INVALID_VALUE)
+	        t = pport->ccpp_pko_num_ports;
+
+            *pport = (struct cvmx_cfg_port_param) {
+		pknd++,
+		bpid++,
+		pko_port_base,
+		t,
+	        pport->ccpp_pko_nqueues};
+	    pko_port_base += t;
+	}
+    }
+    
+    cvmx_helper_cfg_assert(pknd <= CVMX_HELPER_CFG_MAX_PIP_PKND);
+    cvmx_helper_cfg_assert(bpid <= CVMX_HELPER_CFG_MAX_PIP_BPID);
+    cvmx_helper_cfg_assert(pko_port_base <= CVMX_HELPER_CFG_MAX_PKO_PORT);
+    
+    /*
+     * pko_port map
+     */
+    cvmx_helper_cfg_init_pko_port_map();
+
+    /*
+     * per-pko_port parameters
+     */
+    qbase = 0;
+    for (i = 0; i < pko_port_base; i++)
+    {
+#ifdef CVMX_USER_DEFINED_HELPER_CONFIG_INIT
+	n = __cvmx_ucfg_nqueues(i);
+#else
+	n = cvmx_helper_cfg_dft_nqueues(i);
+#endif
+	cvmx_cfg_pko_port[i] = (struct cvmx_cfg_pko_port_param) {qbase, n};
+	qbase += n;
+	cvmx_helper_cfg_assert(qbase <= CVMX_HELPER_CFG_MAX_PKO_QUEUES);
+    }
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+    __cvmx_helper_cfg_init_ipd2pko_cache();
+#endif
+
+#ifdef CVMX_HELPER_CFG_DEBUG
+    cvmx_helper_cfg_show_cfg();
+#endif /* CVMX_HELPER_CFG_DEBUG */
+#endif
+    return 0;
+}
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-cfg.h b/sys/contrib/octeon-sdk/cvmx-helper-cfg.h
new file mode 100644
index 0000000..622504b
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-helper-cfg.h
@@ -0,0 +1,282 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Helper Functions for the Configuration Framework
+ *
+ * OCTEON_CN68XX introduces a flexible hw interface configuration
+ * scheme. To cope with this change and the requirements of
+ * configurability for other system resources, e.g., IPD/PIP pknd and
+ * PKO ports and queues, a configuration framework for the SDK is
+ * designed. It has two goals: first to recognize and establish the
+ * default configuration and, second, to allow the user to define key
+ * parameters in a high-level language.
+ *
+ * The helper functions query the QLM setup to help achieving the
+ * first goal.
+ *
+ * The second goal is accomplished by generating
+ * cvmx_helper_cfg_init() from a high-level lanaguage.
+ *
+ * <hr>$Revision: 0 $<hr>
+ */
+
+#ifndef __CVMX_HELPER_CFG_H__
+#define __CVMX_HELPER_CFG_H__
+
+#define CVMX_HELPER_CFG_MAX_IFACE		9
+#define CVMX_HELPER_CFG_MAX_PKO_PORT		128
+#define CVMX_HELPER_CFG_MAX_PIP_BPID       	64
+#define CVMX_HELPER_CFG_MAX_PIP_PKND       	64
+#define CVMX_HELPER_CFG_MAX_PKO_QUEUES     	256
+#define CVMX_HELPER_CFG_MAX_PORT_PER_IFACE 	256
+
+#define CVMX_HELPER_CFG_INVALID_VALUE		-1	/* The default return 
+						   	 * value upon failure
+							 */
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define cvmx_helper_cfg_assert(cond)					\
+	do {								\
+	    if (!(cond))						\
+	    {								\
+	        cvmx_dprintf("cvmx_helper_cfg_assert (%s) at %s:%d\n",	\
+		    #cond, __FILE__, __LINE__);				\
+	    }								\
+	} while (0)
+
+/*
+ * Config Options
+ *
+ * These options have to be set via cvmx_helper_cfg_opt_set() before calling the
+ * routines that set up the hw. These routines process the options and set them
+ * correctly to take effect at runtime. 
+ */
+enum cvmx_helper_cfg_option {
+	CVMX_HELPER_CFG_OPT_USE_DWB, /*
+				      * Global option to control if
+				      * the SDK configures units (DMA,
+				      * SSO, and PKO) to send don't
+				      * write back (DWB) requests for
+				      * freed buffers. Set to 1/0 to
+				      * enable/disable DWB.
+				      *
+				      * For programs that fit inside
+				      * L2, sending DWB just causes
+				      * more L2 operations without
+				      * benefit.
+	                              */
+
+	CVMX_HELPER_CFG_OPT_MAX
+};
+typedef enum cvmx_helper_cfg_option cvmx_helper_cfg_option_t;
+
+/*
+ * @INTERNAL
+ * Return configured pknd for the port
+ *
+ * @param interface the interface number
+ * @param index the port's index number
+ * @return the pknd
+ */
+extern int __cvmx_helper_cfg_pknd(int interface, int index);
+
+/*
+ * @INTERNAL
+ * Return the configured bpid for the port
+ *
+ * @param interface the interface number
+ * @param index the port's index number
+ * @return the bpid
+ */
+extern int __cvmx_helper_cfg_bpid(int interface, int index);
+
+/*
+ * @INTERNAL
+ * Return the configured pko_port base for the port
+ *
+ * @param interface the interface number
+ * @param index the port's index number
+ * @return the pko_port base
+ */
+extern int __cvmx_helper_cfg_pko_port_base(int interface, int index);
+
+/*
+ * @INTERNAL
+ * Return the configured number of pko_ports for the port
+ *
+ * @param interface the interface number
+ * @param index the port's index number
+ * @return the number of pko_ports
+ */
+extern int __cvmx_helper_cfg_pko_port_num(int interface, int index);
+
+/*
+ * @INTERNAL
+ * Return the configured pko_queue base for the pko_port
+ *
+ * @param pko_port
+ * @return the pko_queue base
+ */
+extern int __cvmx_helper_cfg_pko_queue_base(int pko_port);
+
+/*
+ * @INTERNAL
+ * Return the configured number of pko_queues for the pko_port
+ *
+ * @param pko_port
+ * @return the number of pko_queues
+ */
+extern int __cvmx_helper_cfg_pko_queue_num(int pko_port);
+
+/*
+ * @INTERNAL
+ * Return the interface the pko_port is configured for
+ *
+ * @param pko_port
+ * @return the interface for the pko_port
+ */
+extern int __cvmx_helper_cfg_pko_port_interface(int pko_port);
+
+/*
+ * @INTERNAL
+ * Return the index of the port the pko_port is configured for
+ *
+ * @param pko_port
+ * @return the index of the port
+ */
+extern int __cvmx_helper_cfg_pko_port_index(int pko_port);
+
+/*
+ * @INTERNAL
+ * Return the pko_eid of the pko_port
+ *
+ * @param pko_port
+ * @return the pko_eid
+ */
+extern int __cvmx_helper_cfg_pko_port_eid(int pko_port);
+
+/*
+ * @INTERNAL
+ * Return the max# of pko queues allocated.
+ *
+ * @return the max# of pko queues
+ *
+ * Note: there might be holes in the queue space depending on user
+ * configuration. The function returns the highest queue's index in
+ * use.
+ */
+extern int __cvmx_helper_cfg_pko_max_queue(void);
+
+/*
+ * @INTERNAL
+ * Return the max# of PKO DMA engines allocated.
+ *
+ * @return the max# of DMA engines
+ *
+ * NOTE: the DMA engines are allocated contiguously and starting from
+ * 0.
+ */
+extern int __cvmx_helper_cfg_pko_max_engine(void);
+
+/*
+ * Get the value set for the config option ``opt''.
+ *
+ * @param opt is the config option.
+ * @return the value set for the option
+ */
+extern uint64_t cvmx_helper_cfg_opt_get(cvmx_helper_cfg_option_t opt);
+
+/*
+ * Set the value for a config option.
+ *
+ * @param opt is the config option.
+ * @param val is the value to set for the opt.
+ * @return 0 for success and -1 on error
+ *
+ * Note an option here is a config-time parameter and this means that
+ * it has to be set before calling the corresponding setup functions
+ * that actually sets the option in hw.
+ */
+extern int cvmx_helper_cfg_opt_set(cvmx_helper_cfg_option_t opt, uint64_t val);
+
+/*
+ * Retrieve the pko_port base given ipd_port.
+ *
+ * @param ipd_port is the IPD eport
+ * @return the corresponding PKO port base for the physical port
+ * represented by the IPD eport or CVMX_HELPER_CFG_INVALID_VALUE.
+ */
+extern int cvmx_helper_cfg_ipd2pko_port_base(int ipd_port);
+
+/*
+ * Retrieve the number of pko_ports given ipd_port.
+ *
+ * @param ipd_port is the IPD eport
+ * @return the corresponding number of PKO ports for the physical port 
+ *  represented by IPD eport or CVMX_HELPER_CFG_INVALID_VALUE.
+ */
+extern int cvmx_helper_cfg_ipd2pko_port_num(int ipd_port);
+
+/*
+ * @INTERNAL
+ * The init function
+ *
+ * @param none
+ * @return 0 for success.
+ *
+ * Note: this function is meant to be called to set the ``configured
+ * parameters,'' e.g., pknd, bpid, etc. and therefore should be before
+ * any of the corresponding cvmx_helper_cfg_xxxx() functions are
+ * called.
+ */
+
+extern int __cvmx_helper_cfg_init(void);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_HELPER_CFG_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-check-defines.h b/sys/contrib/octeon-sdk/cvmx-helper-check-defines.h
index 70a2ca0..e162388 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-check-defines.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-check-defines.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -51,7 +51,7 @@
  * function properly. It either supplies a default or fails
  * compile if a define is incorrect.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifndef __CVMX_HELPER_CHECK_DEFINES_H__
 #define __CVMX_HELPER_CHECK_DEFINES_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-errata.c b/sys/contrib/octeon-sdk/cvmx-helper-errata.c
index d226acd..cf1313b 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-errata.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-errata.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -51,7 +51,7 @@
  * chip errata. For the most part, code doesn't need to call
  * these functions directly.
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <asm/octeon/cvmx.h>
@@ -106,7 +106,6 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
     cvmx_gmxx_prtx_cfg_t gmx_cfg;
     int retry_cnt;
     int retry_loop_cnt;
-    int mtu;
     int i;
     cvmx_helper_link_info_t link_info;
 
@@ -195,7 +194,6 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
         cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT));
         cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT));
 
-        mtu = cvmx_read_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
         cvmx_write_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), 65392-14-4);
         cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), 65392-14-4);
 
@@ -304,6 +302,12 @@ int cvmx_helper_fix_ipd_packet_chain(cvmx_wqe_t *work)
 void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)
 {
     int lane;
+    /* Apply the workaround only once. */
+    cvmx_ciu_qlm_jtgd_t qlm_jtgd;
+    qlm_jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
+    if (qlm_jtgd.s.select != 0)
+        return;
+
     cvmx_helper_qlm_jtag_init();
     /* We need to load all four lanes of the QLM, a total of 1072 bits */
     for (lane=0; lane<4; lane++)
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-errata.h b/sys/contrib/octeon-sdk/cvmx-helper-errata.h
index 3d94d1a..0c51220 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-errata.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-errata.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -51,7 +51,7 @@
  * chip errata. For the most part, code doesn't need to call
  * these functions directly.
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifndef __CVMX_HELPER_ERRATA_H__
 #define __CVMX_HELPER_ERRATA_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-fpa.c b/sys/contrib/octeon-sdk/cvmx-helper-fpa.c
index 18bcdb6..205958d 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-fpa.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-fpa.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Helper functions for FPA setup.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #include "cvmx.h"
 #include "cvmx-bootmem.h"
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-fpa.h b/sys/contrib/octeon-sdk/cvmx-helper-fpa.h
index f7fd583..de22404 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-fpa.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-fpa.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Helper functions for FPA setup.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifndef __CVMX_HELPER_H_FPA__
 #define __CVMX_HELPER_H_FPA__
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-ilk.c b/sys/contrib/octeon-sdk/cvmx-helper-ilk.c
new file mode 100644
index 0000000..37e1af9
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-helper-ilk.c
@@ -0,0 +1,442 @@
+/***********************license start***************
+ * Copyright (c) 2010  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Functions for ILK initialization, configuration,
+ * and monitoring.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-cfg.h>
+#include <asm/octeon/cvmx-ilk.h>
+#include <asm/octeon/cvmx-bootmem.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-qlm.h>
+#include <asm/octeon/cvmx-ilk-defs.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "executive-config.h"
+#include "cvmx-config.h"
+#endif
+#include "cvmx.h"
+#include "cvmx-helper.h"
+#include "cvmx-helper-cfg.h"
+#include "cvmx-ilk.h"
+#include "cvmx-bootmem.h"
+#include "cvmx-pko.h"
+#include "cvmx-qlm.h"
+#endif
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+int __cvmx_helper_ilk_enumerate(int interface)
+{
+    interface -= CVMX_ILK_GBL_BASE;
+    return cvmx_ilk_chans[interface];
+}
+
+/**
+ * @INTERNAL
+ * Probe a ILK interface and determine the number of ports
+ * connected to it. The ILK interface should still be down
+ * after this call.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+int __cvmx_helper_ilk_probe(int interface)
+{
+    int i, j, res = -1;
+    static int pipe_base = 0, pknd_base = 0;
+    static cvmx_ilk_pipe_chan_t *pch = NULL, *tmp;
+    static cvmx_ilk_chan_pknd_t *chpknd = NULL, *tmp1;
+    static cvmx_ilk_cal_entry_t *calent = NULL, *tmp2;
+
+    if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
+        return 0;
+
+    interface -= CVMX_ILK_GBL_BASE;
+    if (interface >= CVMX_NUM_ILK_INTF)
+        return 0;
+
+    /* the configuration should be done only once */
+    if (cvmx_ilk_get_intf_ena (interface))
+        return cvmx_ilk_chans[interface];
+
+    /* configure lanes and enable the link */
+    res = cvmx_ilk_start_interface (interface, cvmx_ilk_lane_mask[interface]);
+    if (res < 0)
+        return 0;
+
+    /* set up the group of pipes available to ilk */
+    if (pipe_base == 0)
+        pipe_base = __cvmx_pko_get_pipe (interface + CVMX_ILK_GBL_BASE, 0);
+
+    if (pipe_base == -1)
+    {
+        pipe_base = 0;
+        return 0;
+    }
+
+    res = cvmx_ilk_set_pipe (interface, pipe_base, cvmx_ilk_chans[interface]);
+    if (res < 0)
+        return 0;
+
+    /* set up pipe to channel mapping */
+    i = pipe_base;
+    if (pch == NULL)
+    {
+        pch = (cvmx_ilk_pipe_chan_t *)
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+        kmalloc(CVMX_MAX_ILK_CHANS * sizeof(cvmx_ilk_pipe_chan_t), GFP_KERNEL);
+#else
+        cvmx_bootmem_alloc (CVMX_MAX_ILK_CHANS * sizeof(cvmx_ilk_pipe_chan_t),
+                            sizeof(cvmx_ilk_pipe_chan_t));
+#endif
+        if (pch == NULL)
+            return 0;
+    }
+
+    memset (pch, 0, CVMX_MAX_ILK_CHANS * sizeof(cvmx_ilk_pipe_chan_t));
+    tmp = pch;
+    for (j = 0; j < cvmx_ilk_chans[interface]; j++)
+    {
+        tmp->pipe = i++;
+        tmp->chan = cvmx_ilk_chan_map[interface][j];
+        tmp++;
+    }
+    res = cvmx_ilk_tx_set_channel (interface, pch, cvmx_ilk_chans[interface]);
+    if (res < 0)
+    {
+        res = 0;
+        goto err_free_pch;
+    }
+    pipe_base += cvmx_ilk_chans[interface];
+
+    /* set up channel to pkind mapping */
+    if (pknd_base == 0)
+        pknd_base = cvmx_helper_get_pknd (interface + CVMX_ILK_GBL_BASE, 0);
+
+    i = pknd_base;
+    if (chpknd == NULL)
+    {
+        chpknd = (cvmx_ilk_chan_pknd_t *)
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+        kmalloc(CVMX_MAX_ILK_PKNDS * sizeof(cvmx_ilk_chan_pknd_t), GFP_KERNEL);
+#else
+        cvmx_bootmem_alloc (CVMX_MAX_ILK_PKNDS * sizeof(cvmx_ilk_chan_pknd_t),
+                            sizeof(cvmx_ilk_chan_pknd_t));
+#endif
+        if (chpknd == NULL)
+        {
+            pipe_base -= cvmx_ilk_chans[interface];
+            res = 0;
+            goto err_free_pch;
+        }
+    }
+
+    memset (chpknd, 0, CVMX_MAX_ILK_PKNDS * sizeof(cvmx_ilk_chan_pknd_t));
+    tmp1 = chpknd;
+    for (j = 0; j < cvmx_ilk_chans[interface]; j++)
+    {
+        tmp1->chan = cvmx_ilk_chan_map[interface][j];
+        tmp1->pknd = i++;
+        tmp1++;
+    }
+    res = cvmx_ilk_rx_set_pknd (interface, chpknd, cvmx_ilk_chans[interface]);
+    if (res < 0)
+    {
+        pipe_base -= cvmx_ilk_chans[interface];
+        res = 0;
+        goto err_free_chpknd;
+    }
+    pknd_base += cvmx_ilk_chans[interface];
+
+    /* Set up tx calendar */
+    if (calent == NULL)
+    {
+        calent = (cvmx_ilk_cal_entry_t *)
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+        kmalloc(CVMX_MAX_ILK_PIPES * sizeof(cvmx_ilk_cal_entry_t), GFP_KERNEL);
+#else
+        cvmx_bootmem_alloc (CVMX_MAX_ILK_PIPES * sizeof(cvmx_ilk_cal_entry_t),
+                            sizeof(cvmx_ilk_cal_entry_t));
+#endif
+        if (calent == NULL)
+        {
+            pipe_base -= cvmx_ilk_chans[interface];
+            pknd_base -= cvmx_ilk_chans[interface];
+            res = 0;
+            goto err_free_chpknd;
+        }
+    }
+
+    memset (calent, 0, CVMX_MAX_ILK_PIPES * sizeof(cvmx_ilk_cal_entry_t));
+    tmp1 = chpknd;
+    tmp2 = calent;
+    for (j = 0; j < cvmx_ilk_chans[interface]; j++)
+    {
+        tmp2->pipe_bpid = tmp1->pknd;
+        tmp2->ent_ctrl = PIPE_BPID;
+        tmp1++;
+        tmp2++;
+    }
+    res = cvmx_ilk_cal_setup_tx (interface, cvmx_ilk_chans[interface],
+                                 calent, 1);
+    if (res < 0)
+    {
+        pipe_base -= cvmx_ilk_chans[interface];
+        pknd_base -= cvmx_ilk_chans[interface];
+        res = 0;
+        goto err_free_calent;
+    }
+
+    /* set up rx calendar. allocated memory can be reused.
+     * this is because max pkind is always less than max pipe */
+    memset (calent, 0, CVMX_MAX_ILK_PIPES * sizeof(cvmx_ilk_cal_entry_t));
+    tmp = pch;
+    tmp2 = calent;
+    for (j = 0; j < cvmx_ilk_chans[interface]; j++)
+    {
+        tmp2->pipe_bpid = tmp->pipe;
+        tmp2->ent_ctrl = PIPE_BPID;
+        tmp++;
+        tmp2++;
+    }
+    res = cvmx_ilk_cal_setup_rx (interface, cvmx_ilk_chans[interface],
+                                 calent, CVMX_ILK_RX_FIFO_WM, 1);
+    if (res < 0)
+    {
+        pipe_base -= cvmx_ilk_chans[interface];
+        pknd_base -= cvmx_ilk_chans[interface];
+        res = 0;
+        goto err_free_calent;
+    }
+    res = __cvmx_helper_ilk_enumerate(interface + CVMX_ILK_GBL_BASE);
+
+    goto out;
+
+err_free_calent:
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+    kfree (calent);
+#else
+    /* no free() for cvmx_bootmem_alloc() */
+#endif
+
+err_free_chpknd:
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+    kfree (chpknd);
+#else
+    /* no free() for cvmx_bootmem_alloc() */ 
+#endif
+
+err_free_pch:
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+    kfree (pch);
+#else
+    /* no free() for cvmx_bootmem_alloc() */ 
+#endif
+out:
+    return res;
+}
+
+/**
+ * @INTERNAL
+ * Bringup and enable ILK interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @param interface Interface to bring up
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_ilk_enable(int interface)
+{
+    interface -= CVMX_ILK_GBL_BASE;
+    return cvmx_ilk_enable(interface);
+}
+
+/**
+ * @INTERNAL
+ * Return the link state of an IPD/PKO port as returned by ILK link status.
+ *
+ * @param ipd_port IPD/PKO port to query
+ *
+ * @return Link state
+ */
+cvmx_helper_link_info_t __cvmx_helper_ilk_link_get(int ipd_port)
+{
+    cvmx_helper_link_info_t result;
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    int retry_count = 0;
+    cvmx_ilk_rxx_cfg1_t ilk_rxx_cfg1;
+    cvmx_ilk_rxx_int_t ilk_rxx_int;
+    int lanes = 0;
+
+    result.u64 = 0;
+    interface -= CVMX_ILK_GBL_BASE;
+
+retry:
+    retry_count++;
+    if (retry_count > 10)
+        goto out;
+
+    ilk_rxx_cfg1.u64 = cvmx_read_csr (CVMX_ILK_RXX_CFG1(interface));
+    ilk_rxx_int.u64 = cvmx_read_csr (CVMX_ILK_RXX_INT(interface));
+
+    /* Clear all RX status bits */
+    if (ilk_rxx_int.u64)
+        cvmx_write_csr(CVMX_ILK_RXX_INT(interface), ilk_rxx_int.u64);
+
+    if (ilk_rxx_cfg1.s.rx_bdry_lock_ena == 0)
+    {
+        /* We need to start looking for work boundary lock */
+        ilk_rxx_cfg1.s.rx_bdry_lock_ena = cvmx_ilk_get_intf_ln_msk(interface);
+        ilk_rxx_cfg1.s.rx_align_ena = 0;
+        cvmx_write_csr(CVMX_ILK_RXX_CFG1(interface), ilk_rxx_cfg1.u64);
+        //cvmx_dprintf("ILK%d: Looking for word boundary lock\n", interface);
+        goto retry;
+    }
+
+    if (ilk_rxx_cfg1.s.rx_align_ena == 0)
+    {
+        if (ilk_rxx_int.s.word_sync_done)
+        {
+            ilk_rxx_cfg1.s.rx_align_ena = 1;
+            cvmx_write_csr(CVMX_ILK_RXX_CFG1(interface), ilk_rxx_cfg1.u64);
+            //printf("ILK%d: Looking for lane alignment\n", interface);
+            goto retry;
+        }
+        goto out;
+    }
+
+    if (ilk_rxx_int.s.lane_align_fail)
+    {
+        ilk_rxx_cfg1.s.rx_bdry_lock_ena = 0;
+        ilk_rxx_cfg1.s.rx_align_ena = 0;
+        cvmx_write_csr(CVMX_ILK_RXX_CFG1(interface), ilk_rxx_cfg1.u64);
+        cvmx_dprintf("ILK%d: Lane alignment failed\n", interface);
+        goto out;
+    }
+
+    if (ilk_rxx_int.s.lane_align_done)
+    {
+        //cvmx_dprintf("ILK%d: Lane alignment complete\n", interface);
+    }
+
+    lanes = cvmx_pop(ilk_rxx_cfg1.s.rx_bdry_lock_ena);
+
+    result.s.link_up = 1;
+    result.s.full_duplex = 1;
+    result.s.speed = cvmx_qlm_get_gbaud_mhz(1+interface) * 64 / 67;
+    result.s.speed *= lanes;
+
+out:
+    /* If the link is down we will force disable the RX path. If it up, we'll
+        set it to match the TX state set by the if_enable call */
+    if (result.s.link_up)
+    {
+        cvmx_ilk_txx_cfg1_t ilk_txx_cfg1;
+        ilk_txx_cfg1.u64 = cvmx_read_csr(CVMX_ILK_TXX_CFG1(interface));
+        ilk_rxx_cfg1.s.pkt_ena = ilk_txx_cfg1.s.pkt_ena;
+        cvmx_write_csr(CVMX_ILK_RXX_CFG1(interface), ilk_rxx_cfg1.u64);
+        //cvmx_dprintf("ILK%d: link up, %d Mbps, Full duplex mode, %d lanes\n", interface, result.s.speed, lanes);  
+    }
+    else
+    {
+        ilk_rxx_cfg1.s.pkt_ena = 0;
+        cvmx_write_csr(CVMX_ILK_RXX_CFG1(interface), ilk_rxx_cfg1.u64);
+        //cvmx_dprintf("ILK link down\n");
+    }
+    return result;
+}
+
+/**
+ * @INTERNAL
+ * Set the link state of an IPD/PKO port.
+ *
+ * @param ipd_port  IPD/PKO port to configure
+ * @param link_info The new link state
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_ilk_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
+{
+    /* nothing to do */
+
+    return 0;
+}
+
+/**
+ * Display ilk interface statistics.
+ *
+ */
+void __cvmx_helper_ilk_show_stats (void)
+{
+    int i, j;
+    unsigned char *pchans, num_chans;
+    unsigned int chan_tmp[CVMX_MAX_ILK_CHANS];
+    cvmx_ilk_stats_ctrl_t ilk_stats_ctrl;
+
+    for (i = 0; i < CVMX_NUM_ILK_INTF; i++)
+    {
+        cvmx_ilk_get_chan_info (i, &pchans, &num_chans);
+
+        memset (chan_tmp, 0, CVMX_MAX_ILK_CHANS * sizeof (int));
+        for (j = 0; j < num_chans; j++)
+            chan_tmp[j] = pchans[j];
+
+        ilk_stats_ctrl.chan_list = chan_tmp;
+        ilk_stats_ctrl.num_chans = num_chans;
+        ilk_stats_ctrl.clr_on_rd = 0;
+        cvmx_ilk_show_stats (i, &ilk_stats_ctrl);
+    }
+}
+
+#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-ilk.h b/sys/contrib/octeon-sdk/cvmx-helper-ilk.h
new file mode 100644
index 0000000..b05148c
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-helper-ilk.h
@@ -0,0 +1,110 @@
+/***********************license start***************
+ * Copyright (c) 2010  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Functions for ILK initialization, configuration,
+ * and monitoring.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#ifndef __CVMX_HELPER_ILK_H__
+#define __CVMX_HELPER_ILK_H__
+
+extern int __cvmx_helper_ilk_enumerate(int interface);
+
+/**
+ * @INTERNAL
+ * Probe a ILK interface and determine the number of ports
+ * connected to it. The ILK interface should still be down after
+ * this call.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+extern int __cvmx_helper_ilk_probe(int interface);
+
+/**
+ * @INTERNAL
+ * Bringup and enable a ILK interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @param interface Interface to bring up
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int __cvmx_helper_ilk_enable(int interface);
+
+/**
+ * @INTERNAL
+ * Return the link state of an IPD/PKO port as returned by ILK link status.
+ *
+ * @param ipd_port IPD/PKO port to query
+ *
+ * @return Link state
+ */
+extern cvmx_helper_link_info_t __cvmx_helper_ilk_link_get(int ipd_port);
+
+/**
+ * @INTERNAL
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @param ipd_port  IPD/PKO port to configure
+ * @param link_info The new link state
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int __cvmx_helper_ilk_link_set(int ipd_port, cvmx_helper_link_info_t link_info);
+
+extern void __cvmx_helper_ilk_show_stats (void);
+#endif
+
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-jtag.c b/sys/contrib/octeon-sdk/cvmx-helper-jtag.c
index 57971f6..b280225 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-jtag.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-jtag.c
@@ -1,6 +1,6 @@
 
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -16,7 +16,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -27,7 +27,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -72,7 +72,11 @@ void cvmx_helper_qlm_jtag_init(void)
 {
     cvmx_ciu_qlm_jtgc_t jtgc;
     int clock_div = 0;
-    int divisor = cvmx_clock_get_rate(CVMX_CLOCK_SCLK) / (25 * 1000000);
+    int divisor;
+
+    divisor = cvmx_clock_get_rate(CVMX_CLOCK_SCLK) / (1000000 *
+        (OCTEON_IS_MODEL(OCTEON_CN68XX) ? 10 : 25));
+
     divisor = (divisor-1)>>2;
     /* Convert the divisor into a power of 2 shift */
     while (divisor)
@@ -87,10 +91,12 @@ void cvmx_helper_qlm_jtag_init(void)
     jtgc.s.mux_sel = 0;
     if (OCTEON_IS_MODEL(OCTEON_CN52XX))
         jtgc.s.bypass = 0x3;
-    else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+    else if (OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))
         jtgc.s.bypass = 0x7;
     else
         jtgc.s.bypass = 0xf;
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+        jtgc.s.bypass_ext = 1;
     cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
     cvmx_read_csr(CVMX_CIU_QLM_JTGC);
 }
@@ -118,7 +124,7 @@ uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
 
     jtgc.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGC);
     jtgc.s.mux_sel = qlm;
-    if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
+    if (!OCTEON_IS_MODEL(OCTEON_CN6XXX) && !OCTEON_IS_MODEL(OCTEON_CNF7XXX))
         jtgc.s.bypass = 1<<qlm;
     cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
     cvmx_read_csr(CVMX_CIU_QLM_JTGC);
@@ -175,7 +181,7 @@ void cvmx_helper_qlm_jtag_update(int qlm)
 
     jtgc.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGC);
     jtgc.s.mux_sel = qlm;
-    if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
+    if (!OCTEON_IS_MODEL(OCTEON_CN6XXX) && !OCTEON_IS_MODEL(OCTEON_CNF7XXX))
         jtgc.s.bypass = 1<<qlm;
 
     cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
@@ -206,7 +212,7 @@ void cvmx_helper_qlm_jtag_capture(int qlm)
 
     jtgc.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGC);
     jtgc.s.mux_sel = qlm;
-    if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
+    if (!OCTEON_IS_MODEL(OCTEON_CN6XXX) && !OCTEON_IS_MODEL(OCTEON_CNF7XXX))
         jtgc.s.bypass = 1<<qlm;
 
     cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
@@ -222,4 +228,3 @@ void cvmx_helper_qlm_jtag_capture(int qlm)
         jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
     } while (jtgd.s.capture);
 }
-
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-jtag.h b/sys/contrib/octeon-sdk/cvmx-helper-jtag.h
index dae1c38..a0c9eb0 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-jtag.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-jtag.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-loop.c b/sys/contrib/octeon-sdk/cvmx-helper-loop.c
index c12ec59..18b0d51 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-loop.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-loop.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * Functions for LOOP initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <asm/octeon/cvmx.h>
@@ -74,6 +74,12 @@
 #endif
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
 
+
+int __cvmx_helper_loop_enumerate(int interface)
+{
+	return (OCTEON_IS_MODEL(OCTEON_CN68XX) ? 8 : 4);
+}
+
 /**
  * @INTERNAL
  * Probe a LOOP interface and determine the number of ports
@@ -86,27 +92,7 @@
  */
 int __cvmx_helper_loop_probe(int interface)
 {
-    cvmx_ipd_sub_port_fcs_t ipd_sub_port_fcs;
-    int num_ports = 4;
-    int port;
-
-    /* We need to disable length checking so packet < 64 bytes and jumbo
-        frames don't get errors */
-    for (port=0; port<num_ports; port++)
-    {
-        cvmx_pip_prt_cfgx_t port_cfg;
-        int ipd_port = cvmx_helper_get_ipd_port(interface, port);
-        port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
-        port_cfg.s.maxerr_en = 0;
-        port_cfg.s.minerr_en = 0;
-        cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64);
-    }
-
-    /* Disable FCS stripping for loopback ports */
-    ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
-    ipd_sub_port_fcs.s.port_bit2 = 0;
-    cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);
-    return num_ports;
+	return __cvmx_helper_loop_enumerate(interface);
 }
 
 
@@ -122,7 +108,37 @@ int __cvmx_helper_loop_probe(int interface)
  */
 int __cvmx_helper_loop_enable(int interface)
 {
-    /* Do nothing. */
+    cvmx_pip_prt_cfgx_t port_cfg;
+    int num_ports, index;
+    unsigned long offset;
+
+    num_ports = __cvmx_helper_get_num_ipd_ports(interface);
+
+    /* 
+     * We need to disable length checking so packet < 64 bytes and jumbo
+     * frames don't get errors
+     */
+    for (index = 0; index < num_ports; index++) {
+        offset = ((octeon_has_feature(OCTEON_FEATURE_PKND)) ?
+	    cvmx_helper_get_pknd(interface, index) :
+            cvmx_helper_get_ipd_port(interface, index));
+
+        port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(offset));
+        port_cfg.s.maxerr_en = 0;
+        port_cfg.s.minerr_en = 0;
+        cvmx_write_csr(CVMX_PIP_PRT_CFGX(offset), port_cfg.u64);
+    }
+
+    /*
+     * Disable FCS stripping for loopback ports
+     */
+    if (!octeon_has_feature(OCTEON_FEATURE_PKND)) {
+        cvmx_ipd_sub_port_fcs_t ipd_sub_port_fcs;
+        ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
+        ipd_sub_port_fcs.s.port_bit2 = 0;
+        cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);
+    }
+
     return 0;
 }
 
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-loop.h b/sys/contrib/octeon-sdk/cvmx-helper-loop.h
index 30acdb6..08d1e58 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-loop.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-loop.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * Functions for LOOP initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifndef __CVMX_HELPER_LOOP_H__
 #define __CVMX_HELPER_LOOP_H__
@@ -65,6 +65,7 @@
  * @return Number of ports on the interface. Zero to disable.
  */
 extern int __cvmx_helper_loop_probe(int interface);
+extern int __cvmx_helper_loop_enumerate(int interface);
 
 /**
  * @INTERNAL
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-npi.c b/sys/contrib/octeon-sdk/cvmx-helper-npi.c
index 72629bb..6f64c3e 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-npi.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-npi.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,26 +49,30 @@
  * Functions for NPI initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <asm/octeon/cvmx.h>
 #include <asm/octeon/cvmx-config.h>
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
 #include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-pexp-defs.h>
+#include <asm/octeon/cvmx-sli-defs.h>
 #endif
 #include <asm/octeon/cvmx-pip-defs.h>
 #else
 #if !defined(__FreeBSD__) || !defined(_KERNEL)
 #include "executive-config.h"
 #include "cvmx-config.h"
-#ifdef CVMX_ENABLE_PKO_FUNCTIONS
-
 #include "cvmx.h"
+#include "cvmx-pko.h"
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
 #include "cvmx-helper.h"
 #endif
 #else
 #include "cvmx.h"
+#include "cvmx-pko.h"
 #include "cvmx-helper.h"
 #endif
 #endif
@@ -88,14 +92,8 @@
 int __cvmx_helper_npi_probe(int interface)
 {
 #if CVMX_PKO_QUEUES_PER_PORT_PCI > 0
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
-        return 4;
-    else if (OCTEON_IS_MODEL(OCTEON_CN56XX) && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
-        return 4; /* The packet engines didn't exist before pass 2 */
-    else if (OCTEON_IS_MODEL(OCTEON_CN52XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
-        return 4; /* The packet engines didn't exist before pass 2 */
-    else if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
-        return 4;
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+        return 32;
 #if 0
     /* Technically CN30XX, CN31XX, and CN50XX contain packet engines, but
         nobody ever uses them. Since this is the case, we disable them here */
@@ -104,6 +102,8 @@ int __cvmx_helper_npi_probe(int interface)
     else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
         return 1;
 #endif
+    else if (!(OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN30XX)))
+        return 4; /* The packet engines didn't exist before cn56xx pass 2 */
 #endif
     return 0;
 }
@@ -121,23 +121,56 @@ int __cvmx_helper_npi_probe(int interface)
  */
 int __cvmx_helper_npi_enable(int interface)
 {
+    int num_ports = cvmx_helper_ports_on_interface(interface);
+
     /* On CN50XX, CN52XX, and CN56XX we need to disable length checking
         so packet < 64 bytes and jumbo frames don't get errors */
     if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) && !OCTEON_IS_MODEL(OCTEON_CN58XX))
     {
-        int num_ports = cvmx_helper_ports_on_interface(interface);
         int port;
         for (port=0; port<num_ports; port++)
         {
             cvmx_pip_prt_cfgx_t port_cfg;
-            int ipd_port = cvmx_helper_get_ipd_port(interface, port);
+            int ipd_port = (OCTEON_IS_MODEL(OCTEON_CN68XX)) ?
+	        cvmx_helper_get_pknd(interface, port) :
+		cvmx_helper_get_ipd_port(interface, port);
             port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
+            port_cfg.s.lenerr_en = 0;
             port_cfg.s.maxerr_en = 0;
             port_cfg.s.minerr_en = 0;
             cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64);
+
+            if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+            {
+                /*
+                 * Set up pknd and bpid
+                 */
+		cvmx_sli_portx_pkind_t config;
+		config.u64 = cvmx_read_csr(CVMX_PEXP_SLI_PORTX_PKIND(port));
+		config.s.bpkind = cvmx_helper_get_bpid(interface, port);
+		config.s.pkind = cvmx_helper_get_pknd(interface, port);
+		cvmx_write_csr(CVMX_PEXP_SLI_PORTX_PKIND(port), config.u64);
+            }
         }
     }
 
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+    {
+	/*
+	 * Set up pko pipes.
+	 */
+	cvmx_sli_tx_pipe_t config;
+	config.u64 = cvmx_read_csr(CVMX_PEXP_SLI_TX_PIPE);
+	config.s.base = __cvmx_pko_get_pipe (interface, 0);
+#ifdef CVMX_HELPER_NPI_MAX_PIPES
+	config.s.nump = CVMX_HELPER_NPI_MAX_PIPES;
+#else
+	config.s.nump = num_ports;
+#endif
+	cvmx_write_csr(CVMX_PEXP_SLI_TX_PIPE, config.u64);
+    }
+
+
     /* Enables are controlled by the remote host, so nothing to do here */
     return 0;
 }
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-npi.h b/sys/contrib/octeon-sdk/cvmx-helper-npi.h
index 3f43ad4..5a255eb 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-npi.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-npi.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * Functions for NPI initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifndef __CVMX_HELPER_NPI_H__
 #define __CVMX_HELPER_NPI_H__
@@ -65,6 +65,10 @@
  * @return Number of ports on the interface. Zero to disable.
  */
 extern int __cvmx_helper_npi_probe(int interface);
+static inline int __cvmx_helper_npi_enumerate(int interface)
+{
+	return __cvmx_helper_npi_probe(interface);
+}
 
 /**
  * @INTERNAL
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-rgmii.c b/sys/contrib/octeon-sdk/cvmx-helper-rgmii.c
index 9cecb6a..bd66f87 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-rgmii.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-rgmii.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * Functions for RGMII/GMII/MII initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <asm/octeon/cvmx.h>
@@ -352,6 +352,7 @@ int __cvmx_helper_rgmii_link_set(int ipd_port, cvmx_helper_link_info_t link_info
     cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
                    cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) & ~(1<<index));
 
+    memset(pko_mem_queue_qos_save, 0, sizeof(pko_mem_queue_qos_save));
     /* Disable all queues so that TX should become idle */
     for (i=0; i<cvmx_pko_get_num_queues(ipd_port); i++)
     {
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-rgmii.h b/sys/contrib/octeon-sdk/cvmx-helper-rgmii.h
index 5526370..bd4094f 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-rgmii.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-rgmii.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * Functions for RGMII/GMII/MII initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifndef __CVMX_HELPER_RGMII_H__
 #define __CVMX_HELPER_RGMII_H__
@@ -63,6 +63,10 @@
  * @return Number of RGMII/GMII/MII ports (0-4).
  */
 extern int __cvmx_helper_rgmii_probe(int interface);
+static inline int __cvmx_helper_rgmii_enumerate(int interface)
+{
+	return __cvmx_helper_rgmii_probe(interface);
+}
 
 /**
  * Put an RGMII interface in loopback mode. Internal packets sent
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-sgmii.c b/sys/contrib/octeon-sdk/cvmx-helper-sgmii.c
index a3a8b16..8699548 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-sgmii.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-sgmii.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,15 +49,17 @@
  * Functions for SGMII initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <asm/octeon/cvmx.h>
 #include <asm/octeon/cvmx-config.h>
 #include <asm/octeon/cvmx-clock.h>
+#include <asm/octeon/cvmx-qlm.h>
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
 #include <asm/octeon/cvmx-helper.h>
 #include <asm/octeon/cvmx-helper-board.h>
+#include <asm/octeon/cvmx-helper-cfg.h>
 #endif
 #include <asm/octeon/cvmx-pcsx-defs.h>
 #include <asm/octeon/cvmx-gmxx-defs.h>
@@ -73,6 +75,8 @@
 #include "cvmx-mdio.h"
 #include "cvmx-helper.h"
 #include "cvmx-helper-board.h"
+#include "cvmx-helper-cfg.h"
+#include "cvmx-qlm.h"
 #endif
 #else
 #include "cvmx.h"
@@ -80,6 +84,7 @@
 #include "cvmx-mdio.h"
 #include "cvmx-helper.h"
 #include "cvmx-helper-board.h"
+#include "cvmx-qlm.h"
 #endif
 #endif
 
@@ -142,12 +147,21 @@ static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index)
     }
     else
     {
+#ifdef CVMX_HELPER_CONFIG_NO_PHY
+        /* If the interface does not have PHY, then set explicitly in PHY mode
+           so that link will be set during auto negotiation. */
+        if (!pcsx_miscx_ctl_reg.s.mac_phy) 
+        {
+            cvmx_dprintf("SGMII%d%d: Forcing PHY mode as PHY address is not set\n", interface, index);
+            pcsx_miscx_ctl_reg.s.mac_phy = 1;
+            cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), pcsx_miscx_ctl_reg.u64);
+        }
+#endif
         if (pcsx_miscx_ctl_reg.s.mac_phy)
         {
             /* PHY Mode */
             cvmx_pcsx_sgmx_an_adv_reg_t pcsx_sgmx_an_adv_reg;
             pcsx_sgmx_an_adv_reg.u64 = cvmx_read_csr(CVMX_PCSX_SGMX_AN_ADV_REG(index, interface));
-            pcsx_sgmx_an_adv_reg.s.link = 1;
             pcsx_sgmx_an_adv_reg.s.dup = 1;
             pcsx_sgmx_an_adv_reg.s.speed= 2;
             cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG(index, interface), pcsx_sgmx_an_adv_reg.u64);
@@ -160,6 +174,18 @@ static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index)
     return 0;
 }
 
+static int __cvmx_helper_need_g15618(void)
+{
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM
+        || OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)
+        || OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)
+        || OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_1)
+        || OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_X)
+        || OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X))
+	return 1;
+    else
+	return 0;
+ }
 
 /**
  * @INTERNAL
@@ -181,7 +207,9 @@ static int __cvmx_helper_sgmii_hardware_init_link(int interface, int index)
             the other PCS*_MR*_CONTROL_REG bits).
         Read PCS*_MR*_CONTROL_REG[RESET] until it changes value to zero. */
     control_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
-    if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)
+
+    /* Errata G-15618 requires disabling PCS soft reset in CN63XX pass upto 2.1. */
+    if (!__cvmx_helper_need_g15618())
     {
         control_reg.s.reset = 1;
         cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), control_reg.u64);
@@ -320,6 +348,7 @@ static int __cvmx_helper_sgmii_hardware_init_link_speed(int interface, int index
 static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports)
 {
     int index;
+    int do_link_set = 1;
 
     /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */
     if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0))
@@ -332,19 +361,53 @@ static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports)
         cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64);
     }
 
+    /* CN63XX Pass 2.0 and 2.1 errata G-15273 requires the QLM De-emphasis be
+        programmed when using a 156.25Mhz ref clock */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0) ||
+        OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_1))
+    {
+        /* Read the QLM speed pins */
+        cvmx_mio_rst_boot_t mio_rst_boot;
+        mio_rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
+
+        if (mio_rst_boot.cn63xx.qlm2_spd == 4)
+        {
+            cvmx_ciu_qlm2_t ciu_qlm;
+            ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM2);
+            ciu_qlm.s.txbypass = 1;
+            ciu_qlm.s.txdeemph = 0x0;
+            ciu_qlm.s.txmargin = 0xf;
+            cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64);
+        }
+    }
+
     __cvmx_helper_setup_gmx(interface, num_ports);
 
     for (index=0; index<num_ports; index++)
     {
         int ipd_port = cvmx_helper_get_ipd_port(interface, index);
         __cvmx_helper_sgmii_hardware_init_one_time(interface, index);
-        __cvmx_helper_sgmii_link_set(ipd_port, __cvmx_helper_sgmii_link_get(ipd_port));
-
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+        /* Linux kernel driver will call ....link_set with the proper link
+           state. In the simulator there is no link state polling and
+           hence it is set from here. */
+        if (!(cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM))
+            do_link_set = 0;
+#endif
+        if (do_link_set)
+            __cvmx_helper_sgmii_link_set(ipd_port, __cvmx_helper_sgmii_link_get(ipd_port));
     }
 
     return 0;
 }
 
+int __cvmx_helper_sgmii_enumerate(int interface)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CNF71XX))
+        return 2;
+
+    return 4;
+}
 
 /**
  * @INTERNAL
@@ -360,13 +423,24 @@ int __cvmx_helper_sgmii_probe(int interface)
 {
     cvmx_gmxx_inf_mode_t mode;
 
+    /* Check if QLM is configured correct for SGMII, verify the speed 
+       as well as mode */
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        int qlm = cvmx_qlm_interface(interface);
+
+        if (cvmx_qlm_get_status(qlm) != 1)
+            return 0;
+    }
+
     /* Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the interface
-        needs to be enabled before IPD otherwise per port backpressure
-        may not work properly */
+       needs to be enabled before IPD otherwise per port backpressure
+       may not work properly */
     mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
     mode.s.en = 1;
     cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
-    return 4;
+
+    return __cvmx_helper_sgmii_enumerate(interface);
 }
 
 
@@ -385,11 +459,63 @@ int __cvmx_helper_sgmii_enable(int interface)
     int num_ports = cvmx_helper_ports_on_interface(interface);
     int index;
 
+    /* Setup PKND and BPID */
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+    {
+        for (index = 0; index < num_ports; index++)
+        {
+            cvmx_gmxx_bpid_msk_t bpid_msk;
+            cvmx_gmxx_bpid_mapx_t bpid_map;
+            cvmx_gmxx_prtx_cfg_t gmxx_prtx_cfg;
+
+            /* Setup PKIND */
+            gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+            gmxx_prtx_cfg.s.pknd = cvmx_helper_get_pknd(interface, index);
+            cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
+
+            /* Setup BPID */
+            bpid_map.u64 = cvmx_read_csr(CVMX_GMXX_BPID_MAPX(index, interface));
+            bpid_map.s.val = 1;
+            bpid_map.s.bpid = cvmx_helper_get_bpid(interface, index);
+            cvmx_write_csr(CVMX_GMXX_BPID_MAPX(index, interface), bpid_map.u64);
+
+            bpid_msk.u64 = cvmx_read_csr(CVMX_GMXX_BPID_MSK(interface));
+            bpid_msk.s.msk_or |= (1<<index);
+            bpid_msk.s.msk_and &= ~(1<<index);
+            cvmx_write_csr(CVMX_GMXX_BPID_MSK(interface), bpid_msk.u64);
+        }
+    }
+
     __cvmx_helper_sgmii_hardware_init(interface, num_ports);
 
+    /* CN68XX adds the padding and FCS in PKO, not GMX */
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+    {
+	cvmx_gmxx_txx_append_t gmxx_txx_append_cfg;
+
+        for (index = 0; index < num_ports; index++)
+	{
+	    gmxx_txx_append_cfg.u64 = cvmx_read_csr(
+	        CVMX_GMXX_TXX_APPEND(index, interface));
+	    gmxx_txx_append_cfg.s.fcs = 0;
+	    gmxx_txx_append_cfg.s.pad = 0;
+            cvmx_write_csr(CVMX_GMXX_TXX_APPEND(index, interface), 
+	        gmxx_txx_append_cfg.u64);
+	}
+    }
+
     for (index=0; index<num_ports; index++)
     {
+        cvmx_gmxx_txx_append_t append_cfg;
+        cvmx_gmxx_txx_sgmii_ctl_t sgmii_ctl;
         cvmx_gmxx_prtx_cfg_t gmxx_prtx_cfg;
+
+        /* Clear the align bit if preamble is set to attain maximum tx rate. */
+        append_cfg.u64 = cvmx_read_csr(CVMX_GMXX_TXX_APPEND(index, interface));
+        sgmii_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TXX_SGMII_CTL(index, interface));
+        sgmii_ctl.s.align = append_cfg.s.preamble ? 0 : 1;
+        cvmx_write_csr(CVMX_GMXX_TXX_SGMII_CTL(index, interface), sgmii_ctl.u64);
+
         gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
         gmxx_prtx_cfg.s.en = 1;
         cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
@@ -416,25 +542,43 @@ cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port)
     int interface = cvmx_helper_get_interface_num(ipd_port);
     int index = cvmx_helper_get_interface_index_num(ipd_port);
     cvmx_pcsx_mrx_control_reg_t pcsx_mrx_control_reg;
-
-    result.u64 = 0;
+    int speed = 1000;
+    int qlm;
 
     if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
     {
         /* The simulator gives you a simulated 1Gbps full duplex link */
         result.s.link_up = 1;
         result.s.full_duplex = 1;
-        result.s.speed = 1000;
+        result.s.speed = speed;
         return result;
     }
 
+    if (OCTEON_IS_MODEL(OCTEON_CN66XX))
+    {
+        cvmx_gmxx_inf_mode_t inf_mode;
+        inf_mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
+        if (inf_mode.s.rate & (1<<index))
+            speed = 2500;
+        else
+            speed = 1000;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        qlm = cvmx_qlm_interface(interface);
+
+        speed = cvmx_qlm_get_gbaud_mhz(qlm) * 8 / 10;
+    }
+
+    result.u64 = 0;
+
     pcsx_mrx_control_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
     if (pcsx_mrx_control_reg.s.loopbck1)
     {
         /* Force 1Gbps full duplex link for internal loopback */
         result.s.link_up = 1;
         result.s.full_duplex = 1;
-        result.s.speed = 1000;
+        result.s.speed = speed;
         return result;
     }
 
@@ -471,13 +615,13 @@ cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port)
                 switch (pcsx_anx_results_reg.s.spd)
                 {
                     case 0:
-                        result.s.speed = 10;
+                        result.s.speed = speed / 100;
                         break;
                     case 1:
-                        result.s.speed = 100;
+                        result.s.speed = speed / 10;
                         break;
                     case 2:
-                        result.s.speed = 1000;
+                        result.s.speed = speed;
                         break;
                     default:
                         result.s.speed = 0;
@@ -518,7 +662,23 @@ int __cvmx_helper_sgmii_link_set(int ipd_port, cvmx_helper_link_info_t link_info
 {
     int interface = cvmx_helper_get_interface_num(ipd_port);
     int index = cvmx_helper_get_interface_index_num(ipd_port);
-    __cvmx_helper_sgmii_hardware_init_link(interface, index);
+
+    if (link_info.s.link_up || !__cvmx_helper_need_g15618()) {
+	__cvmx_helper_sgmii_hardware_init_link(interface, index);
+    } else {
+	cvmx_pcsx_mrx_control_reg_t control_reg;
+	cvmx_pcsx_miscx_ctl_reg_t pcsx_miscx_ctl_reg;
+
+	control_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
+	control_reg.s.an_en = 0;
+	cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), control_reg.u64);
+	cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
+	/* Use GMXENO to force the link down it will get reenabled later... */
+	pcsx_miscx_ctl_reg.s.gmxeno = 1;
+	cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), pcsx_miscx_ctl_reg.u64);
+	cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
+	return 0;
+    }
     return __cvmx_helper_sgmii_hardware_init_link_speed(interface, index, link_info);
 }
 
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-sgmii.h b/sys/contrib/octeon-sdk/cvmx-helper-sgmii.h
index 4eb9863..d5e1938 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-sgmii.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-sgmii.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * Functions for SGMII initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifndef __CVMX_HELPER_SGMII_H__
 #define __CVMX_HELPER_SGMII_H__
@@ -65,6 +65,7 @@
  * @return Number of ports on the interface. Zero to disable.
  */
 extern int __cvmx_helper_sgmii_probe(int interface);
+extern int __cvmx_helper_sgmii_enumerate(int interface);
 
 /**
  * @INTERNAL
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-spi.c b/sys/contrib/octeon-sdk/cvmx-helper-spi.c
index 54c768b..c5916a1 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-spi.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-spi.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -47,7 +47,7 @@
  * Functions for SPI initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <asm/octeon/cvmx.h>
@@ -86,6 +86,30 @@
 #define CVMX_HELPER_SPI_TIMEOUT 10
 #endif
 
+int __cvmx_helper_spi_enumerate(int interface)
+{
+#if defined(OCTEON_VENDOR_LANNER)
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CUST_LANNER_MR955)
+    {
+        cvmx_pko_reg_crc_enable_t enable;
+
+        enable.u64 = cvmx_read_csr(CVMX_PKO_REG_CRC_ENABLE);
+        enable.s.enable &= 0xffff << (16 - (interface*16));
+        cvmx_write_csr(CVMX_PKO_REG_CRC_ENABLE, enable.u64);
+
+	if (interface == 1)
+	    return 12;
+	/* XXX This is not entirely true.  */
+	return 0;
+    }
+#endif
+
+	if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) &&
+	    cvmx_spi4000_is_present(interface))
+		return 10;
+	else
+		return 16;
+}
 
 /**
  * @INTERNAL
@@ -99,41 +123,22 @@
  */
 int __cvmx_helper_spi_probe(int interface)
 {
-    int num_ports = 0;
+	int num_ports = __cvmx_helper_spi_enumerate(interface);
 
-    if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) &&
-        cvmx_spi4000_is_present(interface))
-    {
-        num_ports = 10;
-    }
-#if defined(OCTEON_VENDOR_LANNER)
-    else if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CUST_LANNER_MR955)
-    {
-        cvmx_pko_reg_crc_enable_t enable;
-	if (interface == 1) {
-	    num_ports = 12;
-	} else {
-	    /* XXX This is not entirely true.  */
-	    num_ports = 0;
+	if (num_ports == 16) {
+		cvmx_pko_reg_crc_enable_t enable;
+		/*
+		 * Unlike the SPI4000, most SPI devices don't
+		 * automatically put on the L2 CRC. For everything
+		 * except for the SPI4000 have PKO append the L2 CRC
+		 * to the packet
+		 */
+		enable.u64 = cvmx_read_csr(CVMX_PKO_REG_CRC_ENABLE);
+		enable.s.enable |= 0xffff << (interface*16);
+		cvmx_write_csr(CVMX_PKO_REG_CRC_ENABLE, enable.u64);
 	}
-        enable.u64 = cvmx_read_csr(CVMX_PKO_REG_CRC_ENABLE);
-        enable.s.enable &= 0xffff << (16 - (interface*16));
-        cvmx_write_csr(CVMX_PKO_REG_CRC_ENABLE, enable.u64);
-    }
-#endif
-    else
-    {
-        cvmx_pko_reg_crc_enable_t enable;
-        num_ports = 16;
-        /* Unlike the SPI4000, most SPI devices don't automatically
-            put on the L2 CRC. For everything except for the SPI4000
-            have PKO append the L2 CRC to the packet */
-        enable.u64 = cvmx_read_csr(CVMX_PKO_REG_CRC_ENABLE);
-        enable.s.enable |= 0xffff << (interface*16);
-        cvmx_write_csr(CVMX_PKO_REG_CRC_ENABLE, enable.u64);
-    }
-    __cvmx_helper_setup_gmx(interface, num_ports);
-    return num_ports;
+	__cvmx_helper_setup_gmx(interface, num_ports);
+	return num_ports;
 }
 
 
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-spi.h b/sys/contrib/octeon-sdk/cvmx-helper-spi.h
index d34da55..feef409 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-spi.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-spi.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * Functions for SPI initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifndef __CVMX_HELPER_SPI_H__
 #define __CVMX_HELPER_SPI_H__
@@ -65,6 +65,7 @@
  * @return Number of ports on the interface. Zero to disable.
  */
 extern int __cvmx_helper_spi_probe(int interface);
+extern int __cvmx_helper_spi_enumerate(int interface);
 
 /**
  * @INTERNAL
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-srio.c b/sys/contrib/octeon-sdk/cvmx-helper-srio.c
index bf5e297..1baf91c 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-srio.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-srio.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -56,6 +56,7 @@
 #include <asm/octeon/cvmx-config.h>
 #include <asm/octeon/cvmx-clock.h>
 #include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-qlm.h>
 #include <asm/octeon/cvmx-srio.h>
 #include <asm/octeon/cvmx-pip-defs.h>
 #include <asm/octeon/cvmx-sriox-defs.h>
@@ -71,9 +72,11 @@
 #include "cvmx-helper.h"
 #include "cvmx-srio.h"
 #endif
+#include "cvmx-qlm.h"
 #else
 #include "cvmx.h"
 #include "cvmx-helper.h"
+#include "cvmx-qlm.h"
 #include "cvmx-srio.h"
 #endif
 #endif
@@ -95,9 +98,33 @@ int __cvmx_helper_srio_probe(int interface)
     cvmx_sriox_status_reg_t srio0_status_reg;
     cvmx_sriox_status_reg_t srio1_status_reg;
 
-    if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
+    if (!octeon_has_feature(OCTEON_FEATURE_SRIO))
         return 0;
 
+    /* Read MIO_QLMX_CFG CSRs to find SRIO status. */
+    if (OCTEON_IS_MODEL(OCTEON_CN66XX))
+    {
+        int status = cvmx_qlm_get_status(0);
+        int srio_port = interface - 4;
+        switch(srio_port)
+        {
+            case 0:  /* 1x4 lane */
+                if (status == 4)
+                    return 2;
+                break;
+            case 2:  /* 2x2 lane */
+                if (status == 5)
+                    return 2;
+                break;
+            case 1: /* 4x1 long/short */
+            case 3: /* 4x1 long/short */
+                if (status == 6)
+                    return 2;
+                break;
+        }
+        return 0;
+    }
+
     srio0_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));
     srio1_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));
     if (srio0_status_reg.s.srio || srio1_status_reg.s.srio)
@@ -123,7 +150,9 @@ int __cvmx_helper_srio_enable(int interface)
     int index;
     cvmx_sriomaintx_core_enables_t sriomaintx_core_enables;
     cvmx_sriox_imsg_ctrl_t sriox_imsg_ctrl;
+    cvmx_sriox_status_reg_t srio_status_reg;
     cvmx_dpi_ctl_t dpi_ctl;
+    int srio_port = interface - 4;
 
     /* All SRIO ports have a cvmx_srio_rx_message_header_t header
         on them that must be skipped by IPD */
@@ -144,10 +173,10 @@ int __cvmx_helper_srio_enable(int interface)
         }
 
         /* Enable TX with PKO */
-        sriox_omsg_portx.u64 = cvmx_read_csr(CVMX_SRIOX_OMSG_PORTX(index, interface - 4));
-        sriox_omsg_portx.s.port = (interface - 4) * 2 + index;
+        sriox_omsg_portx.u64 = cvmx_read_csr(CVMX_SRIOX_OMSG_PORTX(index, srio_port));
+        sriox_omsg_portx.s.port = (srio_port) * 2 + index;
         sriox_omsg_portx.s.enable = 1;
-        cvmx_write_csr(CVMX_SRIOX_OMSG_PORTX(index, interface - 4), sriox_omsg_portx.u64);
+        cvmx_write_csr(CVMX_SRIOX_OMSG_PORTX(index, srio_port), sriox_omsg_portx.u64);
 
         /* Allow OMSG controller to send regardless of the state of any other
             controller. Allow messages to different IDs and MBOXes to go in
@@ -164,7 +193,7 @@ int __cvmx_helper_srio_enable(int interface)
         sriox_omsg_sp_mrx.s.mbox_fmp = 1;
         sriox_omsg_sp_mrx.s.mbox_nmp = 1;
         sriox_omsg_sp_mrx.s.all_psd = 1;
-        cvmx_write_csr(CVMX_SRIOX_OMSG_SP_MRX(index, interface-4), sriox_omsg_sp_mrx.u64);
+        cvmx_write_csr(CVMX_SRIOX_OMSG_SP_MRX(index, srio_port), sriox_omsg_sp_mrx.u64);
 
         /* Allow OMSG controller to send regardless of the state of any other
             controller. Allow messages to different IDs and MBOXes to go in
@@ -180,7 +209,7 @@ int __cvmx_helper_srio_enable(int interface)
         sriox_omsg_fmp_mrx.s.mbox_fmp = 1;
         sriox_omsg_fmp_mrx.s.mbox_nmp = 1;
         sriox_omsg_fmp_mrx.s.all_psd = 1;
-        cvmx_write_csr(CVMX_SRIOX_OMSG_FMP_MRX(index, interface-4), sriox_omsg_fmp_mrx.u64);
+        cvmx_write_csr(CVMX_SRIOX_OMSG_FMP_MRX(index, srio_port), sriox_omsg_fmp_mrx.u64);
 
         /* Once the first part of a message is accepted, always acept the rest
             of the message */
@@ -188,15 +217,15 @@ int __cvmx_helper_srio_enable(int interface)
         sriox_omsg_nmp_mrx.s.all_sp = 1;
         sriox_omsg_nmp_mrx.s.all_fmp = 1;
         sriox_omsg_nmp_mrx.s.all_nmp = 1;
-        cvmx_write_csr(CVMX_SRIOX_OMSG_NMP_MRX(index, interface-4), sriox_omsg_nmp_mrx.u64);
+        cvmx_write_csr(CVMX_SRIOX_OMSG_NMP_MRX(index, srio_port), sriox_omsg_nmp_mrx.u64);
 
     }
 
     /* Choose the receive controller based on the mailbox */
-    sriox_imsg_ctrl.u64 = cvmx_read_csr(CVMX_SRIOX_IMSG_CTRL(interface - 4));
+    sriox_imsg_ctrl.u64 = cvmx_read_csr(CVMX_SRIOX_IMSG_CTRL(srio_port));
     sriox_imsg_ctrl.s.prt_sel = 0;
     sriox_imsg_ctrl.s.mbox = 0xa;
-    cvmx_write_csr(CVMX_SRIOX_IMSG_CTRL(interface - 4), sriox_imsg_ctrl.u64);
+    cvmx_write_csr(CVMX_SRIOX_IMSG_CTRL(srio_port), sriox_imsg_ctrl.u64);
 
     /* DPI must be enabled for us to RX messages */
     dpi_ctl.u64 = cvmx_read_csr(CVMX_DPI_CTL);
@@ -204,14 +233,19 @@ int __cvmx_helper_srio_enable(int interface)
     dpi_ctl.s.en = 1;
     cvmx_write_csr(CVMX_DPI_CTL, dpi_ctl.u64);
 
+    /* Make sure register access is allowed */
+    srio_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(srio_port));
+    if (!srio_status_reg.s.access)
+        return 0;
+
     /* Enable RX */
-    if (!cvmx_srio_config_read32(interface - 4, 0, -1, 0, 0,
-        CVMX_SRIOMAINTX_CORE_ENABLES(interface-4), &sriomaintx_core_enables.u32))
+    if (!cvmx_srio_config_read32(srio_port, 0, -1, 0, 0,
+        CVMX_SRIOMAINTX_CORE_ENABLES(srio_port), &sriomaintx_core_enables.u32))
     {
         sriomaintx_core_enables.s.imsg0 = 1;
         sriomaintx_core_enables.s.imsg1 = 1;
-        cvmx_srio_config_write32(interface - 4, 0, -1, 0, 0,
-            CVMX_SRIOMAINTX_CORE_ENABLES(interface-4), sriomaintx_core_enables.u32);
+        cvmx_srio_config_write32(srio_port, 0, -1, 0, 0,
+            CVMX_SRIOMAINTX_CORE_ENABLES(srio_port), sriomaintx_core_enables.u32);
     }
 
     return 0;
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-srio.h b/sys/contrib/octeon-sdk/cvmx-helper-srio.h
index 1f9e62c..c0a498e 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-srio.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-srio.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -65,6 +65,10 @@
  * @return Number of ports on the interface. Zero to disable.
  */
 extern int __cvmx_helper_srio_probe(int interface);
+static inline int __cvmx_helper_srio_enumerate(int interface)
+{
+	return __cvmx_helper_srio_probe(interface);
+}
 
 /**
  * @INTERNAL
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-util.c b/sys/contrib/octeon-sdk/cvmx-helper-util.c
index 47250df..0ac8365 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-util.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-util.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,10 +48,11 @@
  *
  * Small helper utilities.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <linux/module.h>
+#include <linux/slab.h>					\
 
 #include <asm/octeon/cvmx.h>
 #include <asm/octeon/cvmx-config.h>
@@ -60,6 +61,10 @@
 #include <asm/octeon/cvmx-helper.h>
 #include <asm/octeon/cvmx-gmxx-defs.h>
 #include <asm/octeon/cvmx-pko-defs.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-sli-defs.h>
+#include <asm/octeon/cvmx-pexp-defs.h>
+#include <asm/octeon/cvmx-helper-cfg.h>
 #else
 #if !defined(__FreeBSD__) || !defined(_KERNEL)
 #include "executive-config.h"
@@ -70,6 +75,7 @@
 #include "cvmx-fpa.h"
 #include "cvmx-pip.h"
 #include "cvmx-pko.h"
+#include "cvmx-ilk.h"
 #include "cvmx-ipd.h"
 #include "cvmx-gmx.h"
 #include "cvmx-spi.h"
@@ -77,10 +83,25 @@
 #include "cvmx-helper.h"
 #include "cvmx-helper-util.h"
 #include "cvmx-version.h"
+#include "cvmx-helper-ilk.h"
+#include "cvmx-helper-cfg.h"
 #endif
 
 #ifdef CVMX_ENABLE_HELPER_FUNCTIONS
 
+struct cvmx_iface {
+    int				cvif_ipd_nports;
+    int				cvif_has_fcs; /* PKO fcs for this interface. */
+    enum cvmx_pko_padding	cvif_padding;
+    cvmx_helper_link_info_t	*cvif_ipd_port_link_info;
+};
+
+/*
+ * This has to be static as u-boot expects to probe an interface and
+ * gets the number of its ports.
+ */
+static CVMX_SHARED struct cvmx_iface cvmx_interfaces[CVMX_HELPER_MAX_IFACE];
+
 #ifndef CVMX_BUILD_FOR_LINUX_KERNEL
 /**
  * Get the version of the CVMX libraries.
@@ -111,11 +132,13 @@ const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mo
         case CVMX_HELPER_INTERFACE_MODE_SPI:        return "SPI";
         case CVMX_HELPER_INTERFACE_MODE_PCIE:       return "PCIE";
         case CVMX_HELPER_INTERFACE_MODE_XAUI:       return "XAUI";
+        case CVMX_HELPER_INTERFACE_MODE_RXAUI:      return "RXAUI";
         case CVMX_HELPER_INTERFACE_MODE_SGMII:      return "SGMII";
         case CVMX_HELPER_INTERFACE_MODE_PICMG:      return "PICMG";
         case CVMX_HELPER_INTERFACE_MODE_NPI:        return "NPI";
         case CVMX_HELPER_INTERFACE_MODE_LOOP:       return "LOOP";
         case CVMX_HELPER_INTERFACE_MODE_SRIO:       return "SRIO";
+        case CVMX_HELPER_INTERFACE_MODE_ILK:        return "ILK";
     }
     return "UNKNOWN";
 }
@@ -136,9 +159,9 @@ int cvmx_helper_dump_packet(cvmx_wqe_t *work)
     uint8_t *       data_address;
     uint8_t *       end_of_data;
 
-    cvmx_dprintf("Packet Length:   %u\n", work->len);
-    cvmx_dprintf("    Input Port:  %u\n", work->ipprt);
-    cvmx_dprintf("    QoS:         %u\n", work->qos);
+    cvmx_dprintf("Packet Length:   %u\n", cvmx_wqe_get_len(work));
+    cvmx_dprintf("    Input Port:  %u\n", cvmx_wqe_get_port(work));
+    cvmx_dprintf("    QoS:         %u\n", cvmx_wqe_get_qos(work));
     cvmx_dprintf("    Buffers:     %u\n", work->word2.s.bufs);
 
     if (work->word2.s.bufs == 0)
@@ -168,7 +191,7 @@ int cvmx_helper_dump_packet(cvmx_wqe_t *work)
     }
     else
         buffer_ptr = work->packet_ptr;
-    remaining_bytes = work->len;
+    remaining_bytes = cvmx_wqe_get_len(work);
 
     while (remaining_bytes)
     {
@@ -258,45 +281,107 @@ int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh)
  */
 int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
 {
-    cvmx_ipd_portx_bp_page_cnt_t page_cnt;
-    cvmx_ipd_bp_prt_red_end_t ipd_bp_prt_red_end;
-    cvmx_ipd_red_port_enable_t red_port_enable;
     int queue;
     int interface;
     int port;
 
-    /* Disable backpressure based on queued buffers. It needs SW support */
-    page_cnt.u64 = 0;
-    page_cnt.s.bp_enb = 0;
-    page_cnt.s.page_cnt = 100;
-    for (interface=0; interface<2; interface++)
+    /*
+     * Disable backpressure based on queued buffers. It needs SW support
+     */
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
     {
-        for (port=cvmx_helper_get_first_ipd_port(interface); port<cvmx_helper_get_last_ipd_port(interface); port++)
-            cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port), page_cnt.u64);
+	int bpid;
+        for (interface = 0; interface < CVMX_HELPER_MAX_GMX; interface++)
+	{
+	    int num_ports;
+
+	    num_ports = cvmx_helper_ports_on_interface(interface);
+	    for (port = 0; port < num_ports; port++) {
+		bpid = cvmx_helper_get_bpid(interface, port);
+		if (bpid == CVMX_INVALID_BPID)
+	            cvmx_dprintf(
+		        "setup_red: cvmx_helper_get_bpid(%d, %d) = %d\n",
+			interface, port, cvmx_helper_get_bpid(interface, port));
+		else
+                    cvmx_write_csr(CVMX_IPD_BPIDX_MBUF_TH(bpid), 0);
+	    }
+	}
     }
+    else
+    {
+        cvmx_ipd_portx_bp_page_cnt_t page_cnt;
 
-    for (queue=0; queue<8; queue++)
-        cvmx_helper_setup_red_queue(queue, pass_thresh, drop_thresh);
-
-    /* Shutoff the dropping based on the per port page count. SW isn't
-        decrementing it right now */
-    ipd_bp_prt_red_end.u64 = 0;
-    ipd_bp_prt_red_end.s.prt_enb = 0;
-    cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64);
+        page_cnt.u64 = 0;
+        page_cnt.s.bp_enb = 0;
+        page_cnt.s.page_cnt = 100;
+        for (interface = 0; interface < CVMX_HELPER_MAX_GMX; interface++)
+        {
+            for (port = cvmx_helper_get_first_ipd_port(interface);
+	        port < cvmx_helper_get_last_ipd_port(interface); port++)
+                cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port), page_cnt.u64);
+        }
+    }
 
-    red_port_enable.u64 = 0;
-    red_port_enable.s.prt_enb = 0xfffffffffull;
-    red_port_enable.s.avg_dly = 10000;
-    red_port_enable.s.prb_dly = 10000;
-    cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64);
+    for (queue = 0; queue < 8; queue++)
+        cvmx_helper_setup_red_queue(queue, pass_thresh, drop_thresh);
 
-    /* Shutoff the dropping of packets based on RED for SRIO ports */
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    /*
+     * Shutoff the dropping based on the per port page count. SW isn't
+     * decrementing it right now
+     */
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+        cvmx_write_csr(CVMX_IPD_ON_BP_DROP_PKTX(0), 0);
+    else
+        cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, 0);
+
+#define IPD_RED_AVG_DLY	1000
+#define IPD_RED_PRB_DLY	1000
+    /*
+     * Setting up avg_dly and prb_dly, enable bits
+     */
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
     {
-        cvmx_ipd_red_port_enable2_t red_port_enable2;
-        red_port_enable2.u64 = 0;
-        red_port_enable2.s.prt_enb = 0xf0;
-        cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE2, red_port_enable2.u64);
+	cvmx_ipd_red_delay_t red_delay;
+        cvmx_ipd_red_bpid_enablex_t red_bpid_enable;
+
+	red_delay.u64 = 0;
+	red_delay.s.avg_dly = IPD_RED_AVG_DLY;
+	red_delay.s.prb_dly = IPD_RED_PRB_DLY;
+        cvmx_write_csr(CVMX_IPD_RED_DELAY, red_delay.u64);
+
+	/*
+	 * Only enable the gmx ports
+	 */
+	red_bpid_enable.u64 = 0;
+        for (interface = 0; interface < CVMX_HELPER_MAX_GMX; interface++)
+	{
+	    int num_ports = cvmx_helper_ports_on_interface(interface);
+	    for (port = 0; port < num_ports; port++)
+		red_bpid_enable.u64 |= (((uint64_t) 1) <<
+		    cvmx_helper_get_bpid(interface, port));
+	}
+	cvmx_write_csr(CVMX_IPD_RED_BPID_ENABLEX(0), red_bpid_enable.u64);
+    }
+    else
+    {
+        cvmx_ipd_red_port_enable_t red_port_enable;
+
+        red_port_enable.u64 = 0;
+        red_port_enable.s.prt_enb = 0xfffffffffull;
+        red_port_enable.s.avg_dly = IPD_RED_AVG_DLY;
+        red_port_enable.s.prb_dly = IPD_RED_PRB_DLY;
+        cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64);
+
+        /*
+	 * Shutoff the dropping of packets based on RED for SRIO ports
+	 */
+        if (octeon_has_feature(OCTEON_FEATURE_SRIO))
+        {
+            cvmx_ipd_red_port_enable2_t red_port_enable2;
+            red_port_enable2.u64 = 0;
+            red_port_enable2.s.prt_enb = 0xf0;
+            cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE2, red_port_enable2.u64);
+        }
     }
 
     return 0;
@@ -325,13 +410,17 @@ int __cvmx_helper_setup_gmx(int interface, int num_ports)
     cvmx_gmxx_txx_thresh_t gmx_tx_thresh;
     int index;
 
-    /* Tell GMX the number of TX ports on this interface */
+    /*
+     * Tell GMX the number of TX ports on this interface
+     */
     gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface));
     gmx_tx_prts.s.prts = num_ports;
     cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64);
 
-    /* Tell GMX the number of RX ports on this interface.  This only
-    ** applies to *GMII and XAUI ports */
+    /*
+     * Tell GMX the number of RX ports on this interface.  This only applies
+     * to GMII and XAUI ports
+     */
     if (cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_RGMII
         || cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_SGMII
         || cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_GMII
@@ -348,8 +437,12 @@ int __cvmx_helper_setup_gmx(int interface, int num_ports)
         cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64);
     }
 
-    /* Skip setting CVMX_PKO_REG_GMX_PORT_MODE on 30XX, 31XX, and 50XX */
-    if (!OCTEON_IS_MODEL(OCTEON_CN30XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX) && !OCTEON_IS_MODEL(OCTEON_CN50XX))
+    /* 
+     * Skip setting CVMX_PKO_REG_GMX_PORT_MODE on 30XX, 31XX, 50XX,
+     * and 68XX.
+     */
+    if (!OCTEON_IS_MODEL(OCTEON_CN30XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX) &&
+        !OCTEON_IS_MODEL(OCTEON_CN50XX) && !OCTEON_IS_MODEL(OCTEON_CN68XX))
     {
         /* Tell PKO the number of ports on this interface */
         pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE);
@@ -382,48 +475,96 @@ int __cvmx_helper_setup_gmx(int interface, int num_ports)
         cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64);
     }
 
-    /* Set GMX to buffer as much data as possible before starting transmit.
-        This reduces the chances that we have a TX under run due to memory
-        contention. Any packet that fits entirely in the GMX FIFO can never
-        have an under run regardless of memory load */
+    /* 
+     * Set GMX to buffer as much data as possible before starting
+     * transmit. This reduces the chances that we have a TX under run
+     * due to memory contention. Any packet that fits entirely in the
+     * GMX FIFO can never have an under run regardless of memory load.
+     */
     gmx_tx_thresh.u64 = cvmx_read_csr(CVMX_GMXX_TXX_THRESH(0, interface));
-    if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
-    {
+    if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) ||
+        OCTEON_IS_MODEL(OCTEON_CN50XX))
         /* These chips have a fixed max threshold of 0x40 */
         gmx_tx_thresh.s.cnt = 0x40;
-    }
     else
     {
+        /* ccn - common cnt numberator */
+	int ccn = 0x100; 
+
         /* Choose the max value for the number of ports */
         if (num_ports <= 1)
-            gmx_tx_thresh.s.cnt = 0x100 / 1;
+            gmx_tx_thresh.s.cnt = ccn / 1;
         else if (num_ports == 2)
-            gmx_tx_thresh.s.cnt = 0x100 / 2;
+            gmx_tx_thresh.s.cnt = ccn / 2;
         else
-            gmx_tx_thresh.s.cnt = 0x100 / 4;
+            gmx_tx_thresh.s.cnt = ccn / 4;
     }
-    /* SPI and XAUI can have lots of ports but the GMX hardware only ever has
-        a max of 4 */
+
+    /*
+     * SPI and XAUI can have lots of ports but the GMX hardware only ever has
+     * a max of 4
+     */
     if (num_ports > 4)
         num_ports = 4;
-    for (index=0; index<num_ports; index++)
-        cvmx_write_csr(CVMX_GMXX_TXX_THRESH(index, interface), gmx_tx_thresh.u64);
+    for (index = 0; index < num_ports; index++)
+        cvmx_write_csr(CVMX_GMXX_TXX_THRESH(index, interface),
+	    gmx_tx_thresh.u64);
+
+    /*
+     * For o68, we need to setup the pipes
+     */
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX) && interface < CVMX_HELPER_MAX_GMX)
+    {
+	cvmx_gmxx_txx_pipe_t config;
+
+	for (index = 0; index < num_ports; index++)
+	{
+	    config.u64 = 0;
+
+	    if (__cvmx_helper_cfg_pko_port_base(interface, index) >= 0)
+	    {
+	        config.u64 = cvmx_read_csr(
+		    CVMX_GMXX_TXX_PIPE(index, interface));
+		config.s.nump = __cvmx_helper_cfg_pko_port_num(interface, index);
+		config.s.base = __cvmx_helper_cfg_pko_port_base(interface, index);
+		cvmx_write_csr(CVMX_GMXX_TXX_PIPE(index, interface),
+		    config.u64);
+	    }
+	}
+    }
 
     return 0;
 }
 
+int cvmx_helper_get_pko_port(int interface, int port)
+{
+    return cvmx_pko_get_base_pko_port(interface, port);
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_helper_get_pko_port);
+#endif
 
-/**
- * Returns the IPD/PKO port number for a port on the given
- * interface.
- *
- * @param interface Interface to use
- * @param port      Port on the interface
- *
- * @return IPD/PKO port number
- */
 int cvmx_helper_get_ipd_port(int interface, int port)
 {
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+    {
+        if (interface >= 0 && interface <= 4)
+        {
+            cvmx_helper_interface_mode_t mode = cvmx_helper_interface_get_mode(interface);
+            if (mode == CVMX_HELPER_INTERFACE_MODE_XAUI || mode == CVMX_HELPER_INTERFACE_MODE_RXAUI)
+                return 0x840 + (interface * 0x100);
+            else
+                return 0x800 + (interface * 0x100) + (port * 16);
+        }
+        else if (interface == 5 || interface == 6)
+            return 0x400 + (interface - 5) * 0x100 + port;
+        else if (interface == 7)
+            return 0x100 + port;
+        else if (interface == 8)
+            return port;
+        else
+            return -1;
+    }
     switch (interface)
     {
         case 0: return port;
@@ -432,6 +573,7 @@ int cvmx_helper_get_ipd_port(int interface, int port)
         case 3: return port + 36;
         case 4: return port + 40;
         case 5: return port + 42;
+        case 6: return port + 44;
     }
     return -1;
 }
@@ -439,8 +581,190 @@ int cvmx_helper_get_ipd_port(int interface, int port)
 EXPORT_SYMBOL(cvmx_helper_get_ipd_port);
 #endif
 
-#endif /* CVMX_ENABLE_HELPER_FUNCTIONS */
+int __cvmx_helper_get_num_ipd_ports(int interface)
+{
+    struct cvmx_iface *piface;
+
+    if (interface >= cvmx_helper_get_number_of_interfaces())
+        return -1;
+
+    piface = &cvmx_interfaces[interface];
+    return piface->cvif_ipd_nports;
+}
+
+enum cvmx_pko_padding __cvmx_helper_get_pko_padding(int interface)
+{
+    struct cvmx_iface *piface;
+
+    if (interface >= cvmx_helper_get_number_of_interfaces())
+        return CVMX_PKO_PADDING_NONE;
+
+    piface = &cvmx_interfaces[interface];
+    return piface->cvif_padding;
+}
+
+int __cvmx_helper_init_interface(int interface, int num_ipd_ports, int has_fcs, enum cvmx_pko_padding pad)
+{
+    struct cvmx_iface *piface;
+    int sz;
+
+    if (interface >= cvmx_helper_get_number_of_interfaces())
+        return -1;
+
+    piface = &cvmx_interfaces[interface];
+    piface->cvif_ipd_nports = num_ipd_ports;
+    piface->cvif_padding = pad;
+
+    piface->cvif_has_fcs = has_fcs;
+
+    /*
+     * allocate the per-ipd_port link_info structure
+     */
+    sz = piface->cvif_ipd_nports * sizeof(cvmx_helper_link_info_t);
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+    if (sz == 0)
+	    sz = sizeof(cvmx_helper_link_info_t);
+    piface->cvif_ipd_port_link_info = (cvmx_helper_link_info_t *)kmalloc(sz, GFP_KERNEL);
+    if (ZERO_OR_NULL_PTR(piface->cvif_ipd_port_link_info))
+	    panic("Cannot allocate memory in __cvmx_helper_init_interface.");
+#else
+    piface->cvif_ipd_port_link_info = (cvmx_helper_link_info_t *)cvmx_bootmem_alloc(sz, sizeof(cvmx_helper_link_info_t));
+#endif
+    if (!piface->cvif_ipd_port_link_info)
+        return -1;
+
+    /* Initialize 'em */ {
+	int i;
+	cvmx_helper_link_info_t *p;
+	p = piface->cvif_ipd_port_link_info;
+
+	for (i = 0; i < piface->cvif_ipd_nports; i++)
+	{
+	    (*p).u64 = 0;
+	    p++;
+	}
+    }
+
+    return 0;
+}
 
+/*
+ * Shut down the interfaces; free the resources.
+ * @INTERNAL
+ */
+void __cvmx_helper_shutdown_interfaces(void)
+{
+    int i;
+    int nifaces;	/* number of interfaces */
+    struct cvmx_iface *piface;
+
+    nifaces = cvmx_helper_get_number_of_interfaces();
+    for (i = 0; i < nifaces; i++)
+    {
+        piface = cvmx_interfaces + i;
+        if (piface->cvif_ipd_port_link_info)
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+            kfree(piface->cvif_ipd_port_link_info);
+#else
+            /*
+	     * For SE apps, bootmem was meant to be allocated and never
+	     * freed.
+	     */
+#endif
+        piface->cvif_ipd_port_link_info = 0;
+    }
+}
+
+int __cvmx_helper_set_link_info(int interface, int port,
+    cvmx_helper_link_info_t link_info)
+{
+    struct cvmx_iface *piface;
+
+    if (interface >= cvmx_helper_get_number_of_interfaces())
+        return -1;
+
+    piface = &cvmx_interfaces[interface];
+
+    if (piface->cvif_ipd_port_link_info)
+    {
+        piface->cvif_ipd_port_link_info[port] = link_info;
+        return 0;
+    }
+
+    return -1;
+}
+
+cvmx_helper_link_info_t __cvmx_helper_get_link_info(int interface, int port)
+{
+    struct cvmx_iface *piface;
+    cvmx_helper_link_info_t err;
+
+    err.u64 = 0;
+
+    if (interface >= cvmx_helper_get_number_of_interfaces())
+        return err;
+    piface = &cvmx_interfaces[interface];
+
+    if (piface->cvif_ipd_port_link_info)
+        return piface->cvif_ipd_port_link_info[port];
+
+    return err;
+}
+
+int __cvmx_helper_get_has_fcs(int interface)
+{
+    return cvmx_interfaces[interface].cvif_has_fcs;
+}
+
+int cvmx_helper_get_pknd(int interface, int port)
+{
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+        return __cvmx_helper_cfg_pknd(interface, port);
+
+    return CVMX_INVALID_PKND;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_helper_get_pknd);
+#endif
+
+int cvmx_helper_get_bpid(int interface, int port)
+{
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+        return __cvmx_helper_cfg_bpid(interface, port);
+
+    return CVMX_INVALID_BPID;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_helper_get_bpid);
+#endif
+
+/**
+ * Display interface statistics.
+ *
+ * @param port IPD/PKO port number
+ *
+ * @return none
+ */
+void cvmx_helper_show_stats(int port)
+{
+    cvmx_pip_port_status_t status;
+    cvmx_pko_port_status_t pko_status;
+
+    /* ILK stats */
+    if (octeon_has_feature(OCTEON_FEATURE_ILK))
+        __cvmx_helper_ilk_show_stats();
+
+    /* PIP stats */
+    cvmx_pip_get_port_status (port, 0, &status);
+    cvmx_dprintf ("port %d: the number of packets - ipd: %d\n", port, (int)status.packets);
+
+    /* PKO stats */
+    cvmx_pko_get_port_status (port, 0, &pko_status);
+    cvmx_dprintf ("port %d: the number of packets - pko: %d\n", port, (int)pko_status.packets);
+
+    /* TODO: other stats */
+}
+#endif /* CVMX_ENABLE_HELPER_FUNCTIONS */
 
 /**
  * Returns the interface number for an IPD/PKO port number.
@@ -451,21 +775,43 @@ EXPORT_SYMBOL(cvmx_helper_get_ipd_port);
  */
 int cvmx_helper_get_interface_num(int ipd_port)
 {
-    if (ipd_port < 16)
-        return 0;
-    else if (ipd_port < 32)
-        return 1;
-    else if (ipd_port < 36)
-        return 2;
-    else if (ipd_port < 40)
-        return 3;
-    else if (ipd_port < 42)
-	return 4;
-    else if (ipd_port < 44)
-	return 5;
-    else
-        cvmx_dprintf("cvmx_helper_get_interface_num: Illegal IPD port number\n");
-
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+    {
+        if (ipd_port >= 0x800 && ipd_port < 0x900)
+            return 0;
+        else if (ipd_port >= 0x900 && ipd_port < 0xa00)
+            return 1;
+        else if (ipd_port >= 0xa00 && ipd_port < 0xb00)
+            return 2;
+        else if (ipd_port >= 0xb00 && ipd_port < 0xc00)
+            return 3;
+        else if (ipd_port >= 0xc00 && ipd_port < 0xd00)
+            return 4;
+        else if (ipd_port >= 0x400 && ipd_port < 0x500)
+            return 5;
+        else if (ipd_port >= 0x500 && ipd_port < 0x600)
+            return 6;
+        else if (ipd_port >= 0x100 && ipd_port < 0x120)
+            return 7;
+        else if (ipd_port < 8)
+            return 8;
+    } else {
+	if (ipd_port < 16)
+	    return 0;
+	else if (ipd_port < 32)
+	    return 1;
+	else if (ipd_port < 36)
+	    return 2;
+	else if (ipd_port < 40)
+	    return 3;
+	else if (ipd_port < 42)
+	    return 4;
+	else if (ipd_port < 44)
+	    return 5;
+	else if (ipd_port < 46)
+	    return 6;
+    }
+    cvmx_dprintf("cvmx_helper_get_interface_num: Illegal IPD port number %d\n", ipd_port);
     return -1;
 }
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
@@ -483,12 +829,31 @@ EXPORT_SYMBOL(cvmx_helper_get_interface_num);
  */
 int cvmx_helper_get_interface_index_num(int ipd_port)
 {
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+    {
+        if (ipd_port >= 0x800 && ipd_port < 0xd00)
+        {
+            int port = ((ipd_port & 0xff) >> 6);
+            return ((port) ? (port - 1) : ((ipd_port & 0xff) >> 4));
+        }
+        else if (ipd_port >= 0x400 && ipd_port < 0x600)
+            return (ipd_port & 0xff);
+        else if (ipd_port >= 0x100 && ipd_port < 0x120)
+            return (ipd_port & 0xff);
+        else if (ipd_port < 8)
+            return ipd_port;
+        else
+            cvmx_dprintf("cvmx_helper_get_interface_index_num: Illegal IPD port number %d\n", ipd_port);
+        return -1;
+    }
     if (ipd_port < 32)
         return ipd_port & 15;
     else if (ipd_port < 40)
         return ipd_port & 3;
     else if (ipd_port < 44)
-	return ipd_port & 1;
+        return ipd_port & 1;
+    else if (ipd_port < 46)
+        return ipd_port & 1;
     else
         cvmx_dprintf("cvmx_helper_get_interface_index_num: Illegal IPD port number\n");
 
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-util.h b/sys/contrib/octeon-sdk/cvmx-helper-util.h
index fdbc84e..56a06f4 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-util.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-util.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,15 +48,27 @@
  *
  * Small helper utilities.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_HELPER_UTIL_H__
 #define __CVMX_HELPER_UTIL_H__
 
+#include "cvmx.h"
+#include "cvmx-mio-defs.h"
 
 #ifdef CVMX_ENABLE_HELPER_FUNCTIONS
 
+typedef char cvmx_pknd_t;
+typedef char cvmx_bpid_t;
+
+#define CVMX_INVALID_PKND	((cvmx_pknd_t) -1)
+#define CVMX_INVALID_BPID	((cvmx_bpid_t) -1)
+#define CVMX_MAX_PKND		((cvmx_pknd_t) 64)
+#define CVMX_MAX_BPID		((cvmx_bpid_t) 64)
+
+#define CVMX_HELPER_MAX_IFACE		9
+
 /**
  * Convert a interface mode into a human readable string
  *
@@ -125,16 +137,99 @@ extern const char *cvmx_helper_get_version(void);
 extern int __cvmx_helper_setup_gmx(int interface, int num_ports);
 
 /**
- * Returns the IPD/PKO port number for a port on the given
+ * @INTERNAL
+ * Get the number of ipd_ports on an interface.
+ *
+ * @param interface
+ *
+ * @return the number of ipd_ports on the interface and -1 for error.
+ */
+extern int __cvmx_helper_get_num_ipd_ports(int interface);
+
+/**
+ * @INTERNAL
+ * Get the number of pko_ports on an interface.
+ *
+ * @param interface
+ *
+ * @return the number of pko_ports on the interface.
+ */
+extern int __cvmx_helper_get_num_pko_ports(int interface);
+
+/*
+ * @INTERNAL
+ *
+ * @param interface
+ * @param port
+ * @param link_info
+ *
+ * @return 0 for success and -1 for failure
+ */
+extern int __cvmx_helper_set_link_info(int interface, int port,
+    cvmx_helper_link_info_t link_info);
+
+/**
+ * @INTERNAL
+ *
+ * @param interface
+ * @param port
+ *
+ * @return valid link_info on success or -1 on failure
+ */
+extern cvmx_helper_link_info_t __cvmx_helper_get_link_info(int interface,
+    int port);
+
+enum cvmx_pko_padding {
+	CVMX_PKO_PADDING_NONE = 0,
+	CVMX_PKO_PADDING_60 = 1,
+};
+
+/**
+ * @INTERNAL
+ *
+ * @param interface
+ * @param num_ipd_ports is the number of ipd_ports on the interface
+ * @param has_fcs indicates if PKO does FCS for the ports on this
+ * @param pad The padding that PKO should apply.
+ * interface.
+ *
+ * @return 0 for success and -1 for failure
+ */
+extern int __cvmx_helper_init_interface(int interface, int num_ipd_ports, int has_fcs, enum cvmx_pko_padding pad);
+
+/**
+ * @INTERNAL
+ *
+ * @param interface
+ *
+ * @return 0 if PKO does not do FCS and 1 otherwise.
+ */
+extern int __cvmx_helper_get_has_fcs(int interface);
+
+
+extern enum cvmx_pko_padding __cvmx_helper_get_pko_padding(int interface);
+
+/**
+ * Returns the IPD port number for a port on the given
  * interface.
  *
  * @param interface Interface to use
  * @param port      Port on the interface
  *
- * @return IPD/PKO port number
+ * @return IPD port number
  */
 extern int cvmx_helper_get_ipd_port(int interface, int port);
 
+/**
+ * Returns the PKO port number for a port on the given interface,
+ * This is the base pko_port for o68 and ipd_port for older models.
+ *
+ * @param interface Interface to use
+ * @param port      Port on the interface
+ *
+ * @return PKO port number and -1 on error.
+ */
+extern int cvmx_helper_get_pko_port(int interface, int port);
 
 /**
  * Returns the IPD/PKO port number for the first port on the given
@@ -217,7 +312,6 @@ static inline void cvmx_helper_free_packet_data(cvmx_wqe_t *work)
  */
 extern int cvmx_helper_get_interface_num(int ipd_port);
 
-
 /**
  * Returns the interface index number for an IPD/PKO port
  * number.
@@ -228,4 +322,33 @@ extern int cvmx_helper_get_interface_num(int ipd_port);
  */
 extern int cvmx_helper_get_interface_index_num(int ipd_port);
 
+/**
+ * Get port kind for a given port in an interface.
+ *
+ * @param interface  Interface
+ * @param port       index of the port in the interface
+ *
+ * @return port kind on sucicess  and -1 on failure
+ */
+extern int cvmx_helper_get_pknd(int interface, int port);
+
+/**
+ * Get bpid for a given port in an interface.
+ *
+ * @param interface  Interface
+ * @param port       index of the port in the interface
+ *
+ * @return port kind on sucicess  and -1 on failure
+ */
+extern int cvmx_helper_get_bpid(int interface, int port);
+
+
+/**
+ * Internal functions.
+ */
+extern int __cvmx_helper_post_init_interfaces(void);
+extern void __cvmx_helper_shutdown_interfaces(void);
+
+extern void cvmx_helper_show_stats(int port);
+
 #endif  /* __CVMX_HELPER_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-xaui.c b/sys/contrib/octeon-sdk/cvmx-helper-xaui.c
index 2616f32..345e9c2 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-xaui.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-xaui.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,16 +49,19 @@
  * Functions for XAUI initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <asm/octeon/cvmx.h>
 #include <asm/octeon/cvmx-config.h>
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
+#include <asm/octeon/cvmx-qlm.h>
 #include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-cfg.h>
 #endif
 #include <asm/octeon/cvmx-gmxx-defs.h>
 #include <asm/octeon/cvmx-pko-defs.h>
+#include <asm/octeon/cvmx-pcsx-defs.h>
 #include <asm/octeon/cvmx-pcsxx-defs.h>
 #include <asm/octeon/cvmx-ciu-defs.h>
 #else
@@ -70,15 +73,29 @@
 
 #include "cvmx.h"
 #include "cvmx-helper.h"
+#include "cvmx-helper-cfg.h"
+#include "cvmx-qlm.h"
 #endif
 #else
 #include "cvmx.h"
 #include "cvmx-helper.h"
+#include "cvmx-qlm.h"
 #endif
 #endif
 
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
 
+int __cvmx_helper_xaui_enumerate(int interface)
+{
+	union cvmx_gmxx_hg2_control gmx_hg2_control;
+
+	/* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
+	gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
+	if (gmx_hg2_control.s.hg2tx_en)
+		return 16;
+	else
+		return 1;
+}
 
 /**
  * @INTERNAL
@@ -93,7 +110,6 @@
 int __cvmx_helper_xaui_probe(int interface)
 {
     int i;
-    cvmx_gmxx_hg2_control_t gmx_hg2_control;
     cvmx_gmxx_inf_mode_t mode;
 
     /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */
@@ -107,6 +123,38 @@ int __cvmx_helper_xaui_probe(int interface)
         cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64);
     }
 
+    /* CN63XX Pass 2.0 and 2.1 errata G-15273 requires the QLM De-emphasis be
+        programmed when using a 156.25Mhz ref clock */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0) ||
+        OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_1))
+    {
+        /* Read the QLM speed pins */
+        cvmx_mio_rst_boot_t mio_rst_boot;
+        mio_rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
+
+        if (mio_rst_boot.cn63xx.qlm2_spd == 0xb)
+        {
+            cvmx_ciu_qlm2_t ciu_qlm;
+            ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM2);
+            ciu_qlm.s.txbypass = 1;
+            ciu_qlm.s.txdeemph = 0xa;
+            ciu_qlm.s.txmargin = 0x1f;
+            cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64);
+        }
+    }
+
+    /* Check if QLM is configured correct for XAUI/RXAUI, verify the 
+       speed as well as mode */
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        int qlm, status;
+
+        qlm = cvmx_qlm_interface(interface);
+        status = cvmx_qlm_get_status(qlm);
+        if (status != 2 && status != 10)
+            return 0;
+    }
+
     /* Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the interface
         needs to be enabled before IPD otherwise per port backpressure
         may not work properly */
@@ -116,49 +164,44 @@ int __cvmx_helper_xaui_probe(int interface)
 
     __cvmx_helper_setup_gmx(interface, 1);
 
-    /* Setup PKO to support 16 ports for HiGig2 virtual ports. We're pointing
-        all of the PKO packet ports for this interface to the XAUI. This allows
-        us to use HiGig2 backpressure per port */
-    for (i=0; i<16; i++)
+    if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
     {
-        cvmx_pko_mem_port_ptrs_t pko_mem_port_ptrs;
-        pko_mem_port_ptrs.u64 = 0;
-        /* We set each PKO port to have equal priority in a round robin
-            fashion */
-        pko_mem_port_ptrs.s.static_p = 0;
-        pko_mem_port_ptrs.s.qos_mask = 0xff;
-        /* All PKO ports map to the same XAUI hardware port */
-        pko_mem_port_ptrs.s.eid = interface*4;
-        pko_mem_port_ptrs.s.pid = interface*16 + i;
-        cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
+	/* Setup PKO to support 16 ports for HiGig2 virtual ports. We're pointing
+	    all of the PKO packet ports for this interface to the XAUI. This allows
+	    us to use HiGig2 backpressure per port */
+	for (i=0; i<16; i++)
+	{
+	    cvmx_pko_mem_port_ptrs_t pko_mem_port_ptrs;
+	    pko_mem_port_ptrs.u64 = 0;
+	    /* We set each PKO port to have equal priority in a round robin
+	        fashion */
+	    pko_mem_port_ptrs.s.static_p = 0;
+	    pko_mem_port_ptrs.s.qos_mask = 0xff;
+	    /* All PKO ports map to the same XAUI hardware port */
+	    pko_mem_port_ptrs.s.eid = interface*4;
+	    pko_mem_port_ptrs.s.pid = interface*16 + i;
+	    cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
+	}
     }
 
-    /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
-    gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
-    if (gmx_hg2_control.s.hg2tx_en)
-        return 16;
-    else
-        return 1;
+    return __cvmx_helper_xaui_enumerate(interface);
 }
 
-
 /**
  * @INTERNAL
- * Bringup and enable a XAUI interface. After this call packet
- * I/O should be fully functional. This is called with IPD
- * enabled but PKO disabled.
+ * Bringup XAUI interface. After this call packet I/O should be 
+ * fully functional.
  *
  * @param interface Interface to bring up
  *
  * @return Zero on success, negative on failure
  */
-int __cvmx_helper_xaui_enable(int interface)
+static int __cvmx_helper_xaui_link_init(int interface)
 {
     cvmx_gmxx_prtx_cfg_t          gmx_cfg;
     cvmx_pcsxx_control1_reg_t     xauiCtl;
     cvmx_pcsxx_misc_ctl_reg_t     xauiMiscCtl;
     cvmx_gmxx_tx_xaui_ctl_t       gmxXauiTxCtl;
-    cvmx_helper_link_info_t       link_info;
 
     /* (1) Interface has already been enabled. */
 
@@ -183,7 +226,14 @@ int __cvmx_helper_xaui_enable(int interface)
     /* (4)c Aply reset sequence */
     xauiCtl.u64 = cvmx_read_csr (CVMX_PCSXX_CONTROL1_REG(interface));
     xauiCtl.s.lo_pwr = 0;
-    xauiCtl.s.reset  = 1;
+
+    /* Errata G-15618 requires disabling PCS soft reset in some OCTEON II models. */
+    if (!OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)
+        && !OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0) 
+        && !OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_1) 
+        && !OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_X) 
+        && !OCTEON_IS_MODEL(OCTEON_CN68XX))
+        xauiCtl.s.reset  = 1;
     cvmx_write_csr (CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
 
     /* Wait for PCS to come out of reset */
@@ -197,9 +247,6 @@ int __cvmx_helper_xaui_enable(int interface)
         return -1;
 
     /* (6) Configure GMX */
-    gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
-    gmx_cfg.s.en = 0;
-    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
 
     /* Wait for GMX RX to be idle */
     if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(0, interface), cvmx_gmxx_prtx_cfg_t, rx_idle, ==, 1, 10000))
@@ -230,13 +277,63 @@ int __cvmx_helper_xaui_enable(int interface)
     xauiMiscCtl.s.gmxeno = 0;
     cvmx_write_csr (CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
 
+    /* Clear all error interrupts before enabling the interface. */
+    cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0,interface), ~0x0ull);
+    cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface), ~0x0ull);
+    cvmx_write_csr(CVMX_PCSXX_INT_REG(interface), ~0x0ull);
+
+    /* Enable GMX */
     gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
     gmx_cfg.s.en = 1;
     cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
 
-    link_info = cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port(interface, 0));
-    if (!link_info.s.link_up)
-        return -1;
+    return 0;
+}
+
+/**
+ * @INTERNAL
+ * Bringup and enable a XAUI interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @param interface Interface to bring up
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_xaui_enable(int interface)
+{
+    /* Setup PKND and BPID */
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+    {
+        cvmx_gmxx_bpid_msk_t bpid_msk;
+        cvmx_gmxx_bpid_mapx_t bpid_map;
+        cvmx_gmxx_prtx_cfg_t gmxx_prtx_cfg;
+        cvmx_gmxx_txx_append_t gmxx_txx_append_cfg;
+
+        /* Setup PKIND */
+        gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
+        gmxx_prtx_cfg.s.pknd = cvmx_helper_get_pknd(interface, 0);
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmxx_prtx_cfg.u64);
+
+        /* Setup BPID */
+        bpid_map.u64 = cvmx_read_csr(CVMX_GMXX_BPID_MAPX(0, interface));
+        bpid_map.s.val = 1;
+        bpid_map.s.bpid = cvmx_helper_get_bpid(interface, 0);
+        cvmx_write_csr(CVMX_GMXX_BPID_MAPX(0, interface), bpid_map.u64);
+
+        bpid_msk.u64 = cvmx_read_csr(CVMX_GMXX_BPID_MSK(interface));
+        bpid_msk.s.msk_or |= 1;
+        bpid_msk.s.msk_and &= ~1;
+        cvmx_write_csr(CVMX_GMXX_BPID_MSK(interface), bpid_msk.u64);
+
+        /* CN68XX adds the padding and FCS in PKO, not GMX */                   
+        gmxx_txx_append_cfg.u64 = cvmx_read_csr(CVMX_GMXX_TXX_APPEND(0, interface));
+        gmxx_txx_append_cfg.s.fcs = 0;
+        gmxx_txx_append_cfg.s.pad = 0;
+        cvmx_write_csr(CVMX_GMXX_TXX_APPEND(0, interface), gmxx_txx_append_cfg.u64);
+    }
+
+    __cvmx_helper_xaui_link_init(interface);
 
     return 0;
 }
@@ -269,9 +366,31 @@ cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port)
     if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0) &&
         (pcsxx_status1_reg.s.rcv_lnk == 1))
     {
+        cvmx_pcsxx_misc_ctl_reg_t misc_ctl;
         result.s.link_up = 1;
         result.s.full_duplex = 1;
-        result.s.speed = 10000;
+        if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+        {
+            cvmx_mio_qlmx_cfg_t qlm_cfg;
+            int lanes;
+            int qlm = (interface == 1) ? 0 : interface;
+
+            qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
+            result.s.speed = cvmx_qlm_get_gbaud_mhz(qlm) * 8 / 10;
+            lanes = (qlm_cfg.s.qlm_cfg == 7) ? 2 : 4;          
+            result.s.speed *= lanes;
+        }
+        else if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+        {
+            int qlm = cvmx_qlm_interface(interface);
+            result.s.speed = cvmx_qlm_get_gbaud_mhz(qlm) * 8 / 10;
+            result.s.speed *= 4;
+        }
+        else
+            result.s.speed = 10000;
+        misc_ctl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
+        if (misc_ctl.s.gmxeno)
+            __cvmx_helper_xaui_link_init(interface);
     }
     else
     {
@@ -313,9 +432,9 @@ int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
     /* Do nothing if both RX and TX are happy */
     if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0))
         return 0;
-
+    
     /* Bring the link up */
-    return __cvmx_helper_xaui_enable(interface);
+    return __cvmx_helper_xaui_link_init(interface);
 }
 
 
@@ -350,7 +469,7 @@ extern int __cvmx_helper_xaui_configure_loopback(int ipd_port, int enable_intern
     cvmx_write_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface), gmxx_xaui_ext_loopback.u64);
 
     /* Take the link through a reset */
-    return __cvmx_helper_xaui_enable(interface);
+    return __cvmx_helper_xaui_link_init(interface);
 }
 
 #endif /* CVMX_ENABLE_PKO_FUNCTIONS */
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-xaui.h b/sys/contrib/octeon-sdk/cvmx-helper-xaui.h
index 14c2659..8b8814c 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-xaui.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-xaui.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * Functions for XAUI initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifndef __CVMX_HELPER_XAUI_H__
 #define __CVMX_HELPER_XAUI_H__
@@ -65,6 +65,7 @@
  * @return Number of ports on the interface. Zero to disable.
  */
 extern int __cvmx_helper_xaui_probe(int interface);
+extern int __cvmx_helper_xaui_enumerate(int interface);
 
 /**
  * @INTERNAL
diff --git a/sys/contrib/octeon-sdk/cvmx-helper.c b/sys/contrib/octeon-sdk/cvmx-helper.c
index c5e9054..309d984 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Helper functions for common, but complicated tasks.
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <linux/module.h>
@@ -57,12 +57,14 @@
 #include <asm/octeon/cvmx-bootmem.h>
 #include <asm/octeon/cvmx-sriox-defs.h>
 #include <asm/octeon/cvmx-npi-defs.h>
+#include <asm/octeon/cvmx-mio-defs.h>
 #include <asm/octeon/cvmx-pexp-defs.h>
 #include <asm/octeon/cvmx-pip-defs.h>
 #include <asm/octeon/cvmx-asxx-defs.h>
 #include <asm/octeon/cvmx-gmxx-defs.h>
 #include <asm/octeon/cvmx-smix-defs.h>
 #include <asm/octeon/cvmx-dbg-defs.h>
+#include <asm/octeon/cvmx-sso-defs.h>
 
 #include <asm/octeon/cvmx-gmx.h>
 #include <asm/octeon/cvmx-fpa.h>
@@ -74,6 +76,7 @@
 #include <asm/octeon/cvmx-helper.h>
 #include <asm/octeon/cvmx-helper-board.h>
 #include <asm/octeon/cvmx-helper-errata.h>
+#include <asm/octeon/cvmx-helper-cfg.h>
 #else
 #if !defined(__FreeBSD__) || !defined(_KERNEL)
 #include "executive-config.h"
@@ -97,40 +100,35 @@
 #include "cvmx-helper.h"
 #include "cvmx-helper-board.h"
 #include "cvmx-helper-errata.h"
+#include "cvmx-helper-cfg.h"
 #endif
 
 
-
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
 
 /**
- * cvmx_override_pko_queue_priority(int ipd_port, uint64_t
+ * cvmx_override_pko_queue_priority(int pko_port, uint64_t
  * priorities[16]) is a function pointer. It is meant to allow
  * customization of the PKO queue priorities based on the port
  * number. Users should set this pointer to a function before
  * calling any cvmx-helper operations.
  */
-CVMX_SHARED void (*cvmx_override_pko_queue_priority)(int pko_port, uint64_t priorities[16]) = NULL;
+CVMX_SHARED void (*cvmx_override_pko_queue_priority)(int ipd_port,
+    uint64_t *priorities) = NULL;
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 EXPORT_SYMBOL(cvmx_override_pko_queue_priority);
 #endif
 
 /**
  * cvmx_override_ipd_port_setup(int ipd_port) is a function
- * pointer. It is meant to allow customization of the IPD port
- * setup before packet input/output comes online. It is called
- * after cvmx-helper does the default IPD configuration, but
- * before IPD is enabled. Users should set this pointer to a
+ * pointer. It is meant to allow customization of the IPD 
+ * port/port kind setup before packet input/output comes online. 
+ * It is called after cvmx-helper does the default IPD configuration,
+ * but before IPD is enabled. Users should set this pointer to a
  * function before calling any cvmx-helper operations.
  */
 CVMX_SHARED void (*cvmx_override_ipd_port_setup)(int ipd_port) = NULL;
 
-/* Port count per interface */
-static CVMX_SHARED int interface_port_count[6] = {0,};
-/* Port last configured link info index by IPD/PKO port */
-static CVMX_SHARED cvmx_helper_link_info_t port_link_info[CVMX_PIP_NUM_INPUT_PORTS];
-
-
 /**
  * Return the number of interfaces the chip has. Each interface
  * may have multiple ports. Most chips support two interfaces,
@@ -152,9 +150,16 @@ int cvmx_helper_get_number_of_interfaces(void)
 	    break;
     }
 
-    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
-	return 6;
-    else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+        return 9;
+    else if (OCTEON_IS_MODEL(OCTEON_CN66XX))
+        if (OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_0))
+            return 7;
+        else
+            return 8;
+    else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+        return 6;
+    else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN61XX))
         return 4;
     else
         return 3;
@@ -175,7 +180,10 @@ EXPORT_SYMBOL(cvmx_helper_get_number_of_interfaces);
  */
 int cvmx_helper_ports_on_interface(int interface)
 {
-    return interface_port_count[interface];
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+        return cvmx_helper_interface_enumerate(interface);
+    else
+        return __cvmx_helper_get_num_ipd_ports(interface);
 }
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 EXPORT_SYMBOL(cvmx_helper_ports_on_interface);
@@ -195,20 +203,113 @@ EXPORT_SYMBOL(cvmx_helper_ports_on_interface);
 cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
 {
     cvmx_gmxx_inf_mode_t mode;
+
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+    {
+        cvmx_mio_qlmx_cfg_t qlm_cfg;
+        switch(interface)
+        {
+            case 0:
+                qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0));
+                /* QLM is disabled when QLM SPD is 15. */
+                if (qlm_cfg.s.qlm_spd == 15)
+                    return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
+                if (qlm_cfg.s.qlm_cfg == 7)
+                    return CVMX_HELPER_INTERFACE_MODE_RXAUI;
+                else if (qlm_cfg.s.qlm_cfg == 2)
+                    return CVMX_HELPER_INTERFACE_MODE_SGMII;
+                else if (qlm_cfg.s.qlm_cfg == 3)
+                    return CVMX_HELPER_INTERFACE_MODE_XAUI;
+                else
+                    return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+                break;
+            case 1:
+                qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0));
+                /* QLM is disabled when QLM SPD is 15. */
+                if (qlm_cfg.s.qlm_spd == 15)
+                    return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
+                if (qlm_cfg.s.qlm_cfg == 7)
+                    return CVMX_HELPER_INTERFACE_MODE_RXAUI;
+                else
+                    return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+                break;
+            case 2:
+            case 3:
+            case 4:
+                qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(interface));
+                /* QLM is disabled when QLM SPD is 15. */
+                if (qlm_cfg.s.qlm_spd == 15)
+                    return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
+                if (qlm_cfg.s.qlm_cfg == 2)
+                    return CVMX_HELPER_INTERFACE_MODE_SGMII;
+                else if (qlm_cfg.s.qlm_cfg == 3)
+                    return CVMX_HELPER_INTERFACE_MODE_XAUI;
+                else
+                    return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+                break; 
+            case 5:
+            case 6:
+                qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(interface - 4));
+                /* QLM is disabled when QLM SPD is 15. */
+                if (qlm_cfg.s.qlm_spd == 15)
+                    return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
+                if (qlm_cfg.s.qlm_cfg == 1)
+		{
+                    return CVMX_HELPER_INTERFACE_MODE_ILK;
+		}
+                else
+                    return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+                break; 
+            case 7:
+                qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(3));
+                /* QLM is disabled when QLM SPD is 15. */
+                if (qlm_cfg.s.qlm_spd == 15)
+                    return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+                else if (qlm_cfg.s.qlm_cfg != 0)
+                {
+                    qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1));
+                    if (qlm_cfg.s.qlm_cfg != 0)
+                        return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+                }
+                return CVMX_HELPER_INTERFACE_MODE_NPI;
+                break; 
+            case 8:
+                return CVMX_HELPER_INTERFACE_MODE_LOOP;
+                break; 
+            default:
+                return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+                break; 
+        }
+    }
+                    
     if (interface == 2)
         return CVMX_HELPER_INTERFACE_MODE_NPI;
 
     if (interface == 3)
     {
-        if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN6XXX))
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX)
+            || OCTEON_IS_MODEL(OCTEON_CN52XX)
+            || OCTEON_IS_MODEL(OCTEON_CN6XXX)
+            || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
             return CVMX_HELPER_INTERFACE_MODE_LOOP;
         else
             return CVMX_HELPER_INTERFACE_MODE_DISABLED;
     }
 
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && (interface == 4 || interface == 5))
+    /* Only present in CN63XX & CN66XX Octeon model */
+    if ((OCTEON_IS_MODEL(OCTEON_CN63XX) && (interface == 4 || interface == 5)) 
+        || (OCTEON_IS_MODEL(OCTEON_CN66XX) && interface >= 4 && interface <= 7))
     {
         cvmx_sriox_status_reg_t sriox_status_reg;
+
+        /* cn66xx pass1.0 has only 2 SRIO interfaces. */
+        if ((interface == 5 || interface == 7) && OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_0))
+            return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
         sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(interface-4));
         if (sriox_status_reg.s.srio)
             return CVMX_HELPER_INTERFACE_MODE_SRIO;
@@ -216,6 +317,60 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
             return CVMX_HELPER_INTERFACE_MODE_DISABLED;
     }
 
+    /* Interface 5 always disabled in CN66XX */
+    if (OCTEON_IS_MODEL(OCTEON_CN66XX))
+    {
+        cvmx_mio_qlmx_cfg_t mio_qlm_cfg;
+
+        /* QLM2 is SGMII0 and QLM1 is SGMII1 */
+        if (interface == 0)
+            mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2));
+        else if (interface == 1)
+            mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1));
+        else
+            return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
+        if (mio_qlm_cfg.s.qlm_spd == 15)
+            return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
+        if (mio_qlm_cfg.s.qlm_cfg == 9)
+            return CVMX_HELPER_INTERFACE_MODE_SGMII;
+        else if (mio_qlm_cfg.s.qlm_cfg == 11)
+            return CVMX_HELPER_INTERFACE_MODE_XAUI;
+        else
+            return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN61XX))
+    {
+        cvmx_mio_qlmx_cfg_t qlm_cfg;
+
+        if (interface == 0)
+        {
+            qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2));
+            if (qlm_cfg.s.qlm_cfg == 2)
+                return CVMX_HELPER_INTERFACE_MODE_SGMII;
+            else if (qlm_cfg.s.qlm_cfg == 3)
+                return CVMX_HELPER_INTERFACE_MODE_XAUI;
+            else
+                return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+        }
+        else if (interface == 1)
+        {
+            /* If QLM 1 is PEV0/PEM1 mode, them QLM0 cannot be SGMII/XAUI */
+            qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1));
+            if (qlm_cfg.s.qlm_cfg == 1)
+                return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
+            qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0));
+            if (qlm_cfg.s.qlm_cfg == 2)
+                return CVMX_HELPER_INTERFACE_MODE_SGMII;
+            else if (qlm_cfg.s.qlm_cfg == 3)
+                return CVMX_HELPER_INTERFACE_MODE_XAUI;
+            else
+                return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+        }
+    }
+
     if (interface == 0 && cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5 && cvmx_sysinfo_get()->board_rev_major == 1)
     {
         /* Lie about interface type of CN3005 board.  This board has a switch on port 1 like
@@ -227,7 +382,13 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
     }
 
     /* Interface 1 is always disabled on CN31XX and CN30XX */
-    if ((interface == 1) && (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+    if ((interface == 1) 
+        && (OCTEON_IS_MODEL(OCTEON_CN31XX)
+            || OCTEON_IS_MODEL(OCTEON_CN30XX)
+            || OCTEON_IS_MODEL(OCTEON_CN50XX)
+            || OCTEON_IS_MODEL(OCTEON_CN52XX)
+            || OCTEON_IS_MODEL(OCTEON_CN63XX)
+            || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
         return CVMX_HELPER_INTERFACE_MODE_DISABLED;
 
     mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
@@ -243,14 +404,14 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
             default:return CVMX_HELPER_INTERFACE_MODE_DISABLED;
         }
     }
-    else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+    else if (OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
     {
-	switch(mode.cn63xx.mode)
-	{
-	    case 0: return CVMX_HELPER_INTERFACE_MODE_SGMII;
-	    case 1: return CVMX_HELPER_INTERFACE_MODE_XAUI;
-	    default: return CVMX_HELPER_INTERFACE_MODE_DISABLED;
-	}
+        switch(mode.cn63xx.mode)
+        {
+            case 0: return CVMX_HELPER_INTERFACE_MODE_SGMII;
+            case 1: return CVMX_HELPER_INTERFACE_MODE_XAUI;
+            default: return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+        }
     }
     else
     {
@@ -279,8 +440,8 @@ EXPORT_SYMBOL(cvmx_helper_interface_get_mode);
  * contents for a port. The setup performed here is controlled by
  * the defines in executive-config.h.
  *
- * @param ipd_port Port to configure. This follows the IPD numbering, not the
- *                 per interface numbering
+ * @param ipd_port Port/Port kind to configure. This follows the IPD numbering, 
+ *                 not the per interface numbering
  *
  * @return Zero on success, negative on failure
  */
@@ -289,11 +450,33 @@ static int __cvmx_helper_port_setup_ipd(int ipd_port)
     cvmx_pip_prt_cfgx_t port_config;
     cvmx_pip_prt_tagx_t tag_config;
 
-    port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
-    tag_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(ipd_port));
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+    {
+        int interface, index, pknd;
+        cvmx_pip_prt_cfgbx_t prt_cfgbx;
 
-    /* Have each port go to a different POW queue */
-    port_config.s.qos = ipd_port & 0x7;
+        interface = cvmx_helper_get_interface_num(ipd_port);
+        index = cvmx_helper_get_interface_index_num(ipd_port);
+        pknd = cvmx_helper_get_pknd(interface, index);
+
+        port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(pknd));
+        tag_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(pknd));
+
+        port_config.s.qos = pknd & 0x7;
+
+        /* Default BPID to use for packets on this port-kind */
+        prt_cfgbx.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGBX(pknd));
+        prt_cfgbx.s.bpid = pknd;
+        cvmx_write_csr(CVMX_PIP_PRT_CFGBX(pknd), prt_cfgbx.u64);
+    }
+    else
+    {
+        port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
+        tag_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(ipd_port));
+
+        /* Have each port go to a different POW queue */
+        port_config.s.qos = ipd_port & 0x7;
+    }
 
     /* Process the headers and place the IP header in the work queue */
     port_config.s.mode = CVMX_HELPER_INPUT_PORT_SKIP_MODE;
@@ -326,13 +509,102 @@ static int __cvmx_helper_port_setup_ipd(int ipd_port)
     return 0;
 }
 
+/**
+ * Enable or disable FCS stripping for all the ports on an interface.
+ *
+ * @param interface
+ * @param nports number of ports
+ * @param has_fcs 0 for disable and !0 for enable
+ */
+static int cvmx_helper_fcs_op(int interface, int nports, int has_fcs)
+{
+    uint64_t port_bit;
+    int index;
+    int pknd;
+    cvmx_pip_sub_pkind_fcsx_t pkind_fcsx;
+    cvmx_pip_prt_cfgx_t port_cfg;
+    
+    if (!octeon_has_feature(OCTEON_FEATURE_PKND))
+        return 0;
+
+    port_bit = 0;
+    for (index = 0; index < nports; index++)
+        port_bit |= ((uint64_t)1 << cvmx_helper_get_pknd(interface, index));
+    
+    pkind_fcsx.u64 = cvmx_read_csr(CVMX_PIP_SUB_PKIND_FCSX(0));
+    if (has_fcs)
+        pkind_fcsx.s.port_bit |= port_bit;
+    else
+        pkind_fcsx.s.port_bit &= ~port_bit;
+    cvmx_write_csr(CVMX_PIP_SUB_PKIND_FCSX(0), pkind_fcsx.u64);
+
+    for (pknd = 0; pknd < 64; pknd++)
+    {
+	if ((1ull << pknd) & port_bit)
+	{
+            port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(pknd));
+            port_cfg.s.crc_en = (has_fcs) ? 1 : 0;
+	    cvmx_write_csr(CVMX_PIP_PRT_CFGX(pknd), port_cfg.u64);
+	}
+    }
+
+    return 0;
+}
+
+/**
+ * Determine the actual number of hardware ports connected to an
+ * interface. It doesn't setup the ports or enable them.
+ *
+ * @param interface Interface to enumerate
+ *
+ * @return The number of ports on the interface, negative on failure
+ */
+int cvmx_helper_interface_enumerate(int interface)
+{
+	switch (cvmx_helper_interface_get_mode(interface)) {
+		/* XAUI is a single high speed port */
+        case CVMX_HELPER_INTERFACE_MODE_XAUI:
+        case CVMX_HELPER_INTERFACE_MODE_RXAUI:
+		return __cvmx_helper_xaui_enumerate(interface);
+		/* RGMII/GMII/MII are all treated about the same. Most functions
+		   refer to these ports as RGMII */
+        case CVMX_HELPER_INTERFACE_MODE_RGMII:
+        case CVMX_HELPER_INTERFACE_MODE_GMII:
+		return  __cvmx_helper_rgmii_enumerate(interface);
+		/* SPI4 can have 1-16 ports depending on the device at the other end */
+        case CVMX_HELPER_INTERFACE_MODE_SPI:
+		return __cvmx_helper_spi_enumerate(interface);
+		/* SGMII can have 1-4 ports depending on how many are hooked up */
+        case CVMX_HELPER_INTERFACE_MODE_SGMII:
+        case CVMX_HELPER_INTERFACE_MODE_PICMG:
+		return __cvmx_helper_sgmii_enumerate(interface);
+		/* PCI target Network Packet Interface */
+        case CVMX_HELPER_INTERFACE_MODE_NPI:
+		return __cvmx_helper_npi_enumerate(interface);
+		/* Special loopback only ports. These are not the same
+		 * as other ports in loopback mode */
+        case CVMX_HELPER_INTERFACE_MODE_LOOP:
+		return __cvmx_helper_loop_enumerate(interface);
+		/* SRIO has 2^N ports, where N is number of interfaces */
+        case CVMX_HELPER_INTERFACE_MODE_SRIO:
+		return __cvmx_helper_srio_enumerate(interface);
+
+        case CVMX_HELPER_INTERFACE_MODE_ILK:
+		return __cvmx_helper_ilk_enumerate(interface);
+		/* These types don't support ports to IPD/PKO */
+        case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+        case CVMX_HELPER_INTERFACE_MODE_PCIE:
+	default:
+		return 0;
+    }
+}
 
 /**
- * This function probes an interface to determine the actual
- * number of hardware ports connected to it. It doesn't setup the
- * ports or enable them. The main goal here is to set the global
- * interface_port_count[interface] correctly. Hardware setup of the
- * ports will be performed later.
+ * This function probes an interface to determine the actual number of
+ * hardware ports connected to it. It does some setup the ports but
+ * doesn't enable them. The main goal here is to set the global
+ * interface_port_count[interface] correctly. Final hardware setup of
+ * the ports will be performed later.
  *
  * @param interface Interface to probe
  *
@@ -343,48 +615,74 @@ int cvmx_helper_interface_probe(int interface)
     /* At this stage in the game we don't want packets to be moving yet.
         The following probe calls should perform hardware setup
         needed to determine port counts. Receive must still be disabled */
+    int nports;
+    int has_fcs;
+    enum cvmx_pko_padding padding = CVMX_PKO_PADDING_NONE;
+
+    nports = -1;
+    has_fcs = 0;
     switch (cvmx_helper_interface_get_mode(interface))
     {
         /* These types don't support ports to IPD/PKO */
         case CVMX_HELPER_INTERFACE_MODE_DISABLED:
         case CVMX_HELPER_INTERFACE_MODE_PCIE:
-            interface_port_count[interface] = 0;
+            nports = 0;
             break;
         /* XAUI is a single high speed port */
         case CVMX_HELPER_INTERFACE_MODE_XAUI:
-            interface_port_count[interface] = __cvmx_helper_xaui_probe(interface);
+        case CVMX_HELPER_INTERFACE_MODE_RXAUI:
+            nports = __cvmx_helper_xaui_probe(interface);
+            has_fcs = 1;
+            padding = CVMX_PKO_PADDING_60;
             break;
         /* RGMII/GMII/MII are all treated about the same. Most functions
             refer to these ports as RGMII */
         case CVMX_HELPER_INTERFACE_MODE_RGMII:
         case CVMX_HELPER_INTERFACE_MODE_GMII:
-            interface_port_count[interface] = __cvmx_helper_rgmii_probe(interface);
+            nports = __cvmx_helper_rgmii_probe(interface);
+            padding = CVMX_PKO_PADDING_60;
             break;
         /* SPI4 can have 1-16 ports depending on the device at the other end */
         case CVMX_HELPER_INTERFACE_MODE_SPI:
-            interface_port_count[interface] = __cvmx_helper_spi_probe(interface);
+            nports = __cvmx_helper_spi_probe(interface);
+            padding = CVMX_PKO_PADDING_60;
             break;
         /* SGMII can have 1-4 ports depending on how many are hooked up */
         case CVMX_HELPER_INTERFACE_MODE_SGMII:
+            padding = CVMX_PKO_PADDING_60;
         case CVMX_HELPER_INTERFACE_MODE_PICMG:
-            interface_port_count[interface] = __cvmx_helper_sgmii_probe(interface);
+            nports = __cvmx_helper_sgmii_probe(interface);
+            has_fcs = 1;
             break;
         /* PCI target Network Packet Interface */
         case CVMX_HELPER_INTERFACE_MODE_NPI:
-            interface_port_count[interface] = __cvmx_helper_npi_probe(interface);
+            nports = __cvmx_helper_npi_probe(interface);
             break;
         /* Special loopback only ports. These are not the same as other ports
             in loopback mode */
         case CVMX_HELPER_INTERFACE_MODE_LOOP:
-            interface_port_count[interface] = __cvmx_helper_loop_probe(interface);
+            nports = __cvmx_helper_loop_probe(interface);
+            break;
+        /* SRIO has 2^N ports, where N is number of interfaces */
+        case CVMX_HELPER_INTERFACE_MODE_SRIO:
+            nports = __cvmx_helper_srio_probe(interface);
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_ILK:
+            nports = __cvmx_helper_ilk_probe(interface);
+            has_fcs = 1;
+            padding = CVMX_PKO_PADDING_60;
             break;
-	/* SRIO has 2^N ports, where N is number of interfaces */
-	case CVMX_HELPER_INTERFACE_MODE_SRIO:
-	    interface_port_count[interface] = __cvmx_helper_srio_probe(interface);
-	    break;
     }
 
-    interface_port_count[interface] = __cvmx_helper_board_interface_probe(interface, interface_port_count[interface]);
+    if (nports == -1)
+        return -1;
+
+    if (!octeon_has_feature(OCTEON_FEATURE_PKND))
+        has_fcs = 0;
+
+    nports = __cvmx_helper_board_interface_probe(interface, nports);
+    __cvmx_helper_init_interface(interface, nports, has_fcs, padding);
+    cvmx_helper_fcs_op(interface, nports, has_fcs);
 
     /* Make sure all global variables propagate to other cores */
     CVMX_SYNCWS;
@@ -406,14 +704,33 @@ int cvmx_helper_interface_probe(int interface)
  */
 static int __cvmx_helper_interface_setup_ipd(int interface)
 {
+
+    cvmx_helper_interface_mode_t mode;
     int ipd_port = cvmx_helper_get_ipd_port(interface, 0);
-    int num_ports = interface_port_count[interface];
+    int num_ports = cvmx_helper_ports_on_interface(interface);
+    int delta;
+
+    if (num_ports == CVMX_HELPER_CFG_INVALID_VALUE)
+        return 0;
+
+    mode = cvmx_helper_interface_get_mode(interface);
+
+    if (mode == CVMX_HELPER_INTERFACE_MODE_LOOP)
+	__cvmx_helper_loop_enable(interface);
+
+    delta = 1;
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+    {
+        if (mode == CVMX_HELPER_INTERFACE_MODE_SGMII)
+	    delta = 16;
+    }
 
     while (num_ports--)
     {
         __cvmx_helper_port_setup_ipd(ipd_port);
-        ipd_port++;
+        ipd_port += delta;
     }
+
     return 0;
 }
 
@@ -465,12 +782,13 @@ static int __cvmx_helper_interface_setup_pko(int interface)
         priorities and replicate them in the second half.
         With per-core PKO queues (PKO lockless operation) all queues have
         the same priority. */
-    uint64_t priorities[16] = {8,7,6,5,4,3,2,1,8,7,6,5,4,3,2,1};
+    /* uint64_t priorities[16] = {8,7,6,5,4,3,2,1,8,7,6,5,4,3,2,1}; */
+    uint64_t priorities[16] = {[0 ... 15] = 8};
 
     /* Setup the IPD/PIP and PKO for the ports discovered above. Here packet
         classification, tagging and output priorities are set */
     int ipd_port = cvmx_helper_get_ipd_port(interface, 0);
-    int num_ports = interface_port_count[interface];
+    int num_ports = cvmx_helper_ports_on_interface(interface);
     while (num_ports--)
     {
         /* Give the user a chance to override the per queue priorities */
@@ -501,6 +819,21 @@ static int __cvmx_helper_global_setup_pko(void)
     fau_to.s.tout_val = 0xfff;
     fau_to.s.tout_enb = 0;
     cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_to.u64);
+
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
+	    cvmx_pko_reg_min_pkt_t min_pkt;
+
+	    min_pkt.u64 = 0;
+	    min_pkt.s.size1 = 59;
+	    min_pkt.s.size2 = 59;
+	    min_pkt.s.size3 = 59;
+	    min_pkt.s.size4 = 59;
+	    min_pkt.s.size5 = 59;
+	    min_pkt.s.size6 = 59;
+	    min_pkt.s.size7 = 59;
+	    cvmx_write_csr(CVMX_PKO_REG_MIN_PKT, min_pkt.u64);
+    }
+
     return 0;
 }
 
@@ -525,9 +858,11 @@ static int __cvmx_helper_global_setup_backpressure(void)
             case CVMX_HELPER_INTERFACE_MODE_DISABLED:
             case CVMX_HELPER_INTERFACE_MODE_PCIE:
             case CVMX_HELPER_INTERFACE_MODE_SRIO:
+            case CVMX_HELPER_INTERFACE_MODE_ILK:
             case CVMX_HELPER_INTERFACE_MODE_NPI:
             case CVMX_HELPER_INTERFACE_MODE_LOOP:
             case CVMX_HELPER_INTERFACE_MODE_XAUI:
+            case CVMX_HELPER_INTERFACE_MODE_RXAUI:
                 break;
             case CVMX_HELPER_INTERFACE_MODE_RGMII:
             case CVMX_HELPER_INTERFACE_MODE_GMII:
@@ -678,10 +1013,12 @@ static int __cvmx_helper_packet_hardware_enable(int interface)
         /* These types don't support ports to IPD/PKO */
         case CVMX_HELPER_INTERFACE_MODE_DISABLED:
         case CVMX_HELPER_INTERFACE_MODE_PCIE:
+        case CVMX_HELPER_INTERFACE_MODE_LOOP:
             /* Nothing to do */
             break;
         /* XAUI is a single high speed port */
         case CVMX_HELPER_INTERFACE_MODE_XAUI:
+        case CVMX_HELPER_INTERFACE_MODE_RXAUI:
             result = __cvmx_helper_xaui_enable(interface);
             break;
         /* RGMII/GMII/MII are all treated about the same. Most functions
@@ -703,15 +1040,13 @@ static int __cvmx_helper_packet_hardware_enable(int interface)
         case CVMX_HELPER_INTERFACE_MODE_NPI:
             result = __cvmx_helper_npi_enable(interface);
             break;
-        /* Special loopback only ports. These are not the same as other ports
-            in loopback mode */
-        case CVMX_HELPER_INTERFACE_MODE_LOOP:
-            result = __cvmx_helper_loop_enable(interface);
-            break;
-	/* SRIO has 2^N ports, where N is number of interfaces */
+        /* SRIO has 2^N ports, where N is number of interfaces */
         case CVMX_HELPER_INTERFACE_MODE_SRIO:
-	    result = __cvmx_helper_srio_enable(interface);
-	    break;
+            result = __cvmx_helper_srio_enable(interface);
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_ILK:
+            result = __cvmx_helper_ilk_enable(interface);
+            break;
     }
     result |= __cvmx_helper_board_hardware_enable(interface);
     return result;
@@ -756,6 +1091,154 @@ int cvmx_helper_ipd_and_packet_input_enable(void)
 EXPORT_SYMBOL(cvmx_helper_ipd_and_packet_input_enable);
 #endif
 
+#define __CVMX_SSO_RWQ_SIZE 256
+
+int cvmx_helper_initialize_sso(int wqe_entries)
+{
+    int cvm_oct_sso_number_rwq_bufs;
+    char *mem;
+    int i;
+    cvmx_sso_cfg_t sso_cfg;
+    cvmx_fpa_fpfx_marks_t fpa_marks;
+
+    if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
+        return 0;
+
+    /*
+     * CN68XX-P1 may reset with the wrong values, put in
+     * the correct values.
+     */
+    fpa_marks.u64 = 0;
+    fpa_marks.s.fpf_wr = 0xa4;
+    fpa_marks.s.fpf_rd = 0x40;
+    cvmx_write_csr(CVMX_FPA_FPF8_MARKS, fpa_marks.u64);
+
+    cvm_oct_sso_number_rwq_bufs = ((wqe_entries - 1) / 26) + 1 + 48 + 8;
+
+    mem = cvmx_bootmem_alloc(__CVMX_SSO_RWQ_SIZE * cvm_oct_sso_number_rwq_bufs, CVMX_CACHE_LINE_SIZE);
+    if (mem == NULL) {
+        cvmx_dprintf("Out of memory initializing sso pool\n");
+        return -1;
+    }
+    /* Make sure RWI/RWO is disabled. */
+    sso_cfg.u64 = cvmx_read_csr(CVMX_SSO_CFG);
+    sso_cfg.s.rwen = 0;
+    cvmx_write_csr(CVMX_SSO_CFG, sso_cfg.u64);
+
+    for (i = cvm_oct_sso_number_rwq_bufs - 8; i > 0; i--) {
+        cvmx_sso_rwq_psh_fptr_t fptr;
+
+        for (;;) {
+            fptr.u64 = cvmx_read_csr(CVMX_SSO_RWQ_PSH_FPTR);
+            if (!fptr.s.full)
+                break;
+            cvmx_wait(1000);
+        }
+        fptr.s.fptr = cvmx_ptr_to_phys(mem) >> 7;
+        cvmx_write_csr(CVMX_SSO_RWQ_PSH_FPTR, fptr.u64);
+        mem = mem + __CVMX_SSO_RWQ_SIZE;
+    }
+
+    for (i = 0; i < 8; i++) {
+        cvmx_sso_rwq_head_ptrx_t head_ptr;
+        cvmx_sso_rwq_tail_ptrx_t tail_ptr;
+
+        head_ptr.u64 = 0;
+        tail_ptr.u64 = 0;
+        head_ptr.s.ptr = cvmx_ptr_to_phys(mem) >> 7;
+        tail_ptr.s.ptr = head_ptr.s.ptr;
+        cvmx_write_csr(CVMX_SSO_RWQ_HEAD_PTRX(i), head_ptr.u64);
+        cvmx_write_csr(CVMX_SSO_RWQ_TAIL_PTRX(i), tail_ptr.u64);
+        mem = mem + __CVMX_SSO_RWQ_SIZE;
+    }
+
+    sso_cfg.u64 = cvmx_read_csr(CVMX_SSO_CFG);
+    sso_cfg.s.rwen = 1;
+    sso_cfg.s.dwb = cvmx_helper_cfg_opt_get(CVMX_HELPER_CFG_OPT_USE_DWB);
+    sso_cfg.s.rwq_byp_dis = 0;
+    sso_cfg.s.rwio_byp_dis = 0;
+    cvmx_write_csr(CVMX_SSO_CFG, sso_cfg.u64);
+
+    return 0;
+}
+
+int cvmx_helper_uninitialize_sso(void)
+{
+    cvmx_fpa_quex_available_t queue_available;
+    cvmx_sso_cfg_t sso_cfg;
+    cvmx_sso_rwq_pop_fptr_t pop_fptr;
+    cvmx_sso_rwq_psh_fptr_t fptr;
+    cvmx_sso_fpage_cnt_t fpage_cnt;
+    int num_to_transfer, i;
+    char *mem;
+
+    if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
+        return 0;
+
+    sso_cfg.u64 = cvmx_read_csr(CVMX_SSO_CFG);
+    sso_cfg.s.rwen = 0;
+    sso_cfg.s.rwq_byp_dis = 1;
+    cvmx_write_csr(CVMX_SSO_CFG, sso_cfg.u64);
+    cvmx_read_csr(CVMX_SSO_CFG);
+    queue_available.u64 = cvmx_read_csr(CVMX_FPA_QUEX_AVAILABLE(8));
+
+    /* Make CVMX_FPA_QUEX_AVAILABLE(8) % 16 == 0*/
+    for (num_to_transfer = (16 - queue_available.s.que_siz) % 16;
+         num_to_transfer > 0; num_to_transfer--) {
+        do {
+            pop_fptr.u64 = cvmx_read_csr(CVMX_SSO_RWQ_POP_FPTR);
+        } while (!pop_fptr.s.val);
+        for (;;) {
+            fptr.u64 = cvmx_read_csr(CVMX_SSO_RWQ_PSH_FPTR);
+            if (!fptr.s.full)
+                break;
+            cvmx_wait(1000);
+        }
+        fptr.s.fptr = pop_fptr.s.fptr;
+        cvmx_write_csr(CVMX_SSO_RWQ_PSH_FPTR, fptr.u64);
+    }
+    cvmx_read_csr(CVMX_SSO_CFG);
+
+    do {
+        queue_available.u64 = cvmx_read_csr(CVMX_FPA_QUEX_AVAILABLE(8));
+    } while (queue_available.s.que_siz % 16);
+
+    sso_cfg.s.rwen = 1;
+    sso_cfg.s.rwq_byp_dis = 0;
+    cvmx_write_csr(CVMX_SSO_CFG, sso_cfg.u64);
+
+    for (i = 0; i < 8; i++) {
+        cvmx_sso_rwq_head_ptrx_t head_ptr;
+        cvmx_sso_rwq_tail_ptrx_t tail_ptr;
+
+        head_ptr.u64 = cvmx_read_csr(CVMX_SSO_RWQ_HEAD_PTRX(i));
+        tail_ptr.u64 = cvmx_read_csr(CVMX_SSO_RWQ_TAIL_PTRX(i));
+        if (head_ptr.s.ptr != tail_ptr.s.ptr) {
+            cvmx_dprintf("head_ptr.s.ptr != tail_ptr.s.ptr, idx: %d\n", i);
+        }
+
+        mem = cvmx_phys_to_ptr(((uint64_t)head_ptr.s.ptr) << 7);
+        /* Leak the memory */
+    }
+
+    do {
+        do {
+            pop_fptr.u64 = cvmx_read_csr(CVMX_SSO_RWQ_POP_FPTR);
+            if (pop_fptr.s.val) {
+                mem = cvmx_phys_to_ptr(((uint64_t)pop_fptr.s.fptr) << 7);
+                /* Leak the memory */
+            }
+        } while (pop_fptr.s.val);
+        fpage_cnt.u64 = cvmx_read_csr(CVMX_SSO_FPAGE_CNT);
+    } while (fpage_cnt.s.fpage_cnt);
+
+    sso_cfg.s.rwen = 0;
+    sso_cfg.s.rwq_byp_dis = 0;
+    cvmx_write_csr(CVMX_SSO_CFG, sso_cfg.u64);
+
+    return 0;
+}
+
 /**
  * Initialize the PIP, IPD, and PKO hardware to support
  * simple priority based queues for the ethernet ports. Each
@@ -780,7 +1263,7 @@ int cvmx_helper_initialize_packet_io_global(void)
     /* Tell L2 to give the IOB statically higher priority compared to the
         cores. This avoids conditions where IO blocks might be starved under
         very high L2 loads */
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
     {
         cvmx_l2c_ctl_t l2c_ctl;
         l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);
@@ -798,28 +1281,31 @@ int cvmx_helper_initialize_packet_io_global(void)
 
     if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)
     {
-        /* Make sure SMI/MDIO is enabled so we can query PHYs */
-        smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(0));
-        if (!smix_en.s.en)
-        {
-            smix_en.s.en = 1;
-            cvmx_write_csr(CVMX_SMIX_EN(0), smix_en.u64);
-        }
-
-        /* Newer chips actually have two SMI/MDIO interfaces */
-        if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) &&
-            !OCTEON_IS_MODEL(OCTEON_CN58XX) &&
-            !OCTEON_IS_MODEL(OCTEON_CN50XX))
+        int smi_inf = 1;
+        int i;
+
+        /* Newer chips have more than one SMI/MDIO interface */
+        if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+            smi_inf = 4;
+        else if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) 
+                 && !OCTEON_IS_MODEL(OCTEON_CN58XX) 
+                 && !OCTEON_IS_MODEL(OCTEON_CN50XX))
+            smi_inf = 2;
+
+        for (i = 0; i < smi_inf; i++)
         {
-            smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(1));
+            /* Make sure SMI/MDIO is enabled so we can query PHYs */
+            smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(i));
             if (!smix_en.s.en)
             {
                 smix_en.s.en = 1;
-                cvmx_write_csr(CVMX_SMIX_EN(1), smix_en.u64);
+                cvmx_write_csr(CVMX_SMIX_EN(i), smix_en.u64);
             }
         }
     }
 
+    __cvmx_helper_cfg_init();
+
     for (interface=0; interface<num_interfaces; interface++)
         result |= cvmx_helper_interface_probe(interface);
 
@@ -831,7 +1317,8 @@ int cvmx_helper_initialize_packet_io_global(void)
                      interface, cvmx_helper_ports_on_interface(interface),
                      cvmx_helper_interface_mode_to_string(cvmx_helper_interface_get_mode(interface)));
         result |= __cvmx_helper_interface_setup_ipd(interface);
-        result |= __cvmx_helper_interface_setup_pko(interface);
+        if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
+            result |= __cvmx_helper_interface_setup_pko(interface);
     }
 
     result |= __cvmx_helper_global_setup_ipd();
@@ -860,6 +1347,34 @@ int cvmx_helper_initialize_packet_io_local(void)
     return cvmx_pko_initialize_local();
 }
 
+/**
+ * wait for the pko queue to drain
+ *
+ * @param queue a valid pko queue
+ * @return count is the length of the queue after calling this
+ * function
+ */
+static int cvmx_helper_wait_pko_queue_drain(int queue)
+{
+    const int timeout = 5; /* Wait up to 5 seconds for timeouts */
+    int count;
+    uint64_t start_cycle, stop_cycle;
+
+    count = cvmx_cmd_queue_length(CVMX_CMD_QUEUE_PKO(queue));
+    start_cycle = cvmx_get_cycle();
+    stop_cycle = start_cycle + cvmx_clock_get_rate(CVMX_CLOCK_CORE) * timeout;
+    while (count && (cvmx_get_cycle() < stop_cycle))
+    {
+        cvmx_wait(10000);
+        count = cvmx_cmd_queue_length(CVMX_CMD_QUEUE_PKO(queue));
+    }
+
+    return count;
+}
+
+struct cvmx_buffer_list {
+    struct cvmx_buffer_list *next;
+};
 
 /**
  * Undo the initialization performed in
@@ -880,49 +1395,58 @@ int cvmx_helper_shutdown_packet_io_global(void)
     int interface;
     int num_ports;
     int index;
-    int pool0_count;
+    struct cvmx_buffer_list *pool0_buffers;
+    struct cvmx_buffer_list *pool0_buffers_tail;
     cvmx_wqe_t *work;
 
     /* Step 1: Disable all backpressure */
-    for (interface=0; interface<2; interface++)
+    for (interface=0; interface<CVMX_HELPER_MAX_GMX; interface++)
         if (cvmx_helper_interface_get_mode(interface) != CVMX_HELPER_INTERFACE_MODE_DISABLED)
             cvmx_gmx_set_backpressure_override(interface, 0xf);
 
 step2:
     /* Step 2: Wait for the PKO queues to drain */
-    num_interfaces = cvmx_helper_get_number_of_interfaces();
-    for (interface=0; interface<num_interfaces; interface++)
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+    {
+        int queue, max_queue;
+
+	max_queue = __cvmx_helper_cfg_pko_max_queue();
+	for (queue = 0; queue < max_queue; queue++)
+	{
+	    if (cvmx_helper_wait_pko_queue_drain(queue))
+	    {
+	        result = -1;
+		goto step3;
+            }
+        }
+    }
+    else
     {
-        num_ports = cvmx_helper_ports_on_interface(interface);
-        for (index=0; index<num_ports; index++)
+        num_interfaces = cvmx_helper_get_number_of_interfaces();
+        for (interface=0; interface<num_interfaces; interface++)
         {
-            int pko_port = cvmx_helper_get_ipd_port(interface, index);
-            int queue = cvmx_pko_get_base_queue(pko_port);
-            int max_queue = queue + cvmx_pko_get_num_queues(pko_port);
-            while (queue < max_queue)
+            num_ports = cvmx_helper_ports_on_interface(interface);
+            for (index=0; index<num_ports; index++)
             {
-                int count = cvmx_cmd_queue_length(CVMX_CMD_QUEUE_PKO(queue));
-                uint64_t start_cycle = cvmx_get_cycle();
-                uint64_t stop_cycle = start_cycle +
-                    cvmx_clock_get_rate(CVMX_CLOCK_CORE) * timeout;
-                while (count && (cvmx_get_cycle() < stop_cycle))
-                {
-                    cvmx_wait(10000);
-                    count = cvmx_cmd_queue_length(CVMX_CMD_QUEUE_PKO(queue));
-                }
-                if (count)
+                int pko_port = cvmx_helper_get_ipd_port(interface, index);
+                int queue = cvmx_pko_get_base_queue(pko_port);
+                int max_queue = queue + cvmx_pko_get_num_queues(pko_port);
+                while (queue < max_queue)
                 {
-                    cvmx_dprintf("PKO port %d, queue %d, timeout waiting for idle\n",
-                        pko_port, queue);
-                    result = -1;
+	            if (cvmx_helper_wait_pko_queue_drain(queue))
+		    {
+		        result = -1;
+			goto step3;
+		    }
+                    queue++;
                 }
-                queue++;
             }
         }
     }
 
+step3:
     /* Step 3: Disable TX and RX on all ports */
-    for (interface=0; interface<2; interface++)
+    for (interface=0; interface<CVMX_HELPER_MAX_GMX; interface++)
     {
         switch (cvmx_helper_interface_get_mode(interface))
         {
@@ -932,6 +1456,7 @@ step2:
                 break;
             case CVMX_HELPER_INTERFACE_MODE_NPI:
             case CVMX_HELPER_INTERFACE_MODE_SRIO:
+            case CVMX_HELPER_INTERFACE_MODE_ILK:
                 /* We don't handle the NPI/NPEI/SRIO packet engines. The caller
                     must know these are idle */
                 break;
@@ -977,6 +1502,7 @@ step2:
                 cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0);
                 break;
             case CVMX_HELPER_INTERFACE_MODE_XAUI:
+            case CVMX_HELPER_INTERFACE_MODE_RXAUI:
             case CVMX_HELPER_INTERFACE_MODE_SGMII:
             case CVMX_HELPER_INTERFACE_MODE_PICMG:
                 num_ports = cvmx_helper_ports_on_interface(interface);
@@ -1080,9 +1606,8 @@ step2:
         }
     }
 
-    /* Step 5: Disable IPD and PKO. PIP is taken care of in the next step */
+    /* Step 5 */
     cvmx_ipd_disable();
-    cvmx_pko_disable();
 
     /* Step 6: Drain all prefetched buffers from IPD/PIP. Note that IPD/PIP
         have not been reset yet */
@@ -1092,17 +1617,19 @@ step2:
     cvmx_pko_shutdown();
 
     /* Step 8: Disable MAC address filtering */
-    for (interface=0; interface<2; interface++)
+    for (interface=0; interface<CVMX_HELPER_MAX_GMX; interface++)
     {
         switch (cvmx_helper_interface_get_mode(interface))
         {
             case CVMX_HELPER_INTERFACE_MODE_DISABLED:
             case CVMX_HELPER_INTERFACE_MODE_PCIE:
             case CVMX_HELPER_INTERFACE_MODE_SRIO:
+            case CVMX_HELPER_INTERFACE_MODE_ILK:
             case CVMX_HELPER_INTERFACE_MODE_NPI:
             case CVMX_HELPER_INTERFACE_MODE_LOOP:
                 break;
             case CVMX_HELPER_INTERFACE_MODE_XAUI:
+            case CVMX_HELPER_INTERFACE_MODE_RXAUI:
             case CVMX_HELPER_INTERFACE_MODE_GMII:
             case CVMX_HELPER_INTERFACE_MODE_RGMII:
             case CVMX_HELPER_INTERFACE_MODE_SPI:
@@ -1126,23 +1653,30 @@ step2:
         }
     }
 
-    /* Step 9: Drain all FPA buffers out of pool 0 before we reset IPD/PIP.
-        This is needed to keep IPD_QUE0_FREE_PAGE_CNT in sync. We use pool 1
-        for temporary storage */
-    pool0_count = 0;
+    /* Step 9: Drain all FPA buffers out of pool 0 before we reset
+     * IPD/PIP.  This is needed to keep IPD_QUE0_FREE_PAGE_CNT in
+     * sync. We temporarily keep the buffers in the pool0_buffers
+     * list.
+     */
+    pool0_buffers = NULL;
+    pool0_buffers_tail = NULL;
     while (1)
     {
-        void *buffer = cvmx_fpa_alloc(0);
-        if (buffer)
-        {
-            cvmx_fpa_free(buffer, 1, 0);
-            pool0_count++;
+        struct cvmx_buffer_list *buffer = cvmx_fpa_alloc(0);
+        if (buffer) {
+            buffer->next = NULL;
+
+            if (pool0_buffers == NULL)
+                pool0_buffers = buffer;
+            else
+                pool0_buffers_tail->next = buffer;
+
+            pool0_buffers_tail = buffer;
         }
         else
             break;
     }
 
-
     /* Step 10: Reset IPD and PIP */
     {
         cvmx_ipd_ctl_status_t ipd_ctl_status;
@@ -1187,11 +1721,27 @@ step2:
             pip_sft_rst.s.rst = 1;
             cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64);
         }
+
+        /* Make sure IPD has finished reset. */
+        if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+        {
+            if (CVMX_WAIT_FOR_FIELD64(CVMX_IPD_CTL_STATUS, cvmx_ipd_ctl_status_t, rst_done, ==, 0, 1000))
+            {
+                cvmx_dprintf("IPD reset timeout waiting for idle\n");
+                result = -1;
+            }
+        }
     }
 
     /* Step 11: Restore the FPA buffers into pool 0 */
-    while (pool0_count--)
-        cvmx_fpa_free(cvmx_fpa_alloc(1), 0, 0);
+    while (pool0_buffers) {
+        struct cvmx_buffer_list *n = pool0_buffers->next;
+        cvmx_fpa_free(pool0_buffers, 0, 0);
+        pool0_buffers = n;
+    }
+
+    /* Step 12: Release interface structures */
+    __cvmx_helper_shutdown_interfaces();
 
     return result;
 }
@@ -1236,7 +1786,7 @@ cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port)
     }
 
     link_info = cvmx_helper_link_get(ipd_port);
-    if (link_info.u64 ==  port_link_info[ipd_port].u64)
+    if (link_info.u64 == (__cvmx_helper_get_link_info(interface, index)).u64)
         return link_info;
 
 #if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
@@ -1252,9 +1802,7 @@ cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port)
         cvmx_error_enable_group(CVMX_ERROR_GROUP_ETHERNET, ipd_port);
 #endif
 
-    /* port_link_info should be the current value, which will be different
-        than expect if cvmx_helper_link_set() failed */
-    return port_link_info[ipd_port];
+    return link_info;
 }
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 EXPORT_SYMBOL(cvmx_helper_link_autoconf);
@@ -1290,6 +1838,7 @@ cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port)
             /* Network links are not supported */
             break;
         case CVMX_HELPER_INTERFACE_MODE_XAUI:
+        case CVMX_HELPER_INTERFACE_MODE_RXAUI:
             result = __cvmx_helper_xaui_link_get(ipd_port);
             break;
         case CVMX_HELPER_INTERFACE_MODE_GMII:
@@ -1315,6 +1864,9 @@ cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port)
         case CVMX_HELPER_INTERFACE_MODE_SRIO:
             result = __cvmx_helper_srio_link_get(ipd_port);
             break;
+        case CVMX_HELPER_INTERFACE_MODE_ILK:
+            result = __cvmx_helper_ilk_link_get(ipd_port);
+            break;
         case CVMX_HELPER_INTERFACE_MODE_NPI:
         case CVMX_HELPER_INTERFACE_MODE_LOOP:
             /* Network links are not supported */
@@ -1354,6 +1906,7 @@ int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
         case CVMX_HELPER_INTERFACE_MODE_PCIE:
             break;
         case CVMX_HELPER_INTERFACE_MODE_XAUI:
+        case CVMX_HELPER_INTERFACE_MODE_RXAUI:
             result = __cvmx_helper_xaui_link_set(ipd_port, link_info);
             break;
         /* RGMII/GMII/MII are all treated about the same. Most functions
@@ -1372,6 +1925,9 @@ int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
         case CVMX_HELPER_INTERFACE_MODE_SRIO:
             result = __cvmx_helper_srio_link_set(ipd_port, link_info);
             break;
+        case CVMX_HELPER_INTERFACE_MODE_ILK:
+            result = __cvmx_helper_ilk_link_set(ipd_port, link_info);
+            break;
         case CVMX_HELPER_INTERFACE_MODE_NPI:
         case CVMX_HELPER_INTERFACE_MODE_LOOP:
             break;
@@ -1380,7 +1936,7 @@ int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
        no matter how cvmx_helper_link_set is called. We don't change
        the value if link_set failed */
     if (result == 0)
-        port_link_info[ipd_port].u64 = link_info.u64;
+        __cvmx_helper_set_link_info(interface, index, link_info);
     return result;
 }
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
@@ -1415,11 +1971,13 @@ int cvmx_helper_configure_loopback(int ipd_port, int enable_internal, int enable
         case CVMX_HELPER_INTERFACE_MODE_DISABLED:
         case CVMX_HELPER_INTERFACE_MODE_PCIE:
         case CVMX_HELPER_INTERFACE_MODE_SRIO:
+        case CVMX_HELPER_INTERFACE_MODE_ILK:
         case CVMX_HELPER_INTERFACE_MODE_SPI:
         case CVMX_HELPER_INTERFACE_MODE_NPI:
         case CVMX_HELPER_INTERFACE_MODE_LOOP:
             break;
         case CVMX_HELPER_INTERFACE_MODE_XAUI:
+        case CVMX_HELPER_INTERFACE_MODE_RXAUI:
             result = __cvmx_helper_xaui_configure_loopback(ipd_port, enable_internal, enable_external);
             break;
         case CVMX_HELPER_INTERFACE_MODE_RGMII:
diff --git a/sys/contrib/octeon-sdk/cvmx-helper.h b/sys/contrib/octeon-sdk/cvmx-helper.h
index 82d34e1..4486989 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Helper functions for common, but complicated tasks.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_HELPER_H__
@@ -65,10 +65,60 @@
 #include "cvmx-fpa.h"
 #include "cvmx-wqe.h"
 
-#ifdef	__cplusplus
+#ifdef  __cplusplus
 extern "C" {
 #endif
 
+/* Max number of GMXX */
+#define CVMX_HELPER_MAX_GMX             (OCTEON_IS_MODEL(OCTEON_CN68XX) ? 5 : 2)
+
+#define CVMX_HELPER_CSR_INIT0           0       /* Do not change as 
+                                                   CVMX_HELPER_WRITE_CSR()
+                                                   assumes it */
+#define CVMX_HELPER_CSR_INIT_READ       -1
+
+/*
+ * CVMX_HELPER_WRITE_CSR--set a field in a CSR with a value.
+ *
+ * @param chcsr_init    intial value of the csr (CVMX_HELPER_CSR_INIT_READ
+ *                      means to use the existing csr value as the
+ *                      initial value.)
+ * @param chcsr_csr     the name of the csr
+ * @param chcsr_type    the type of the csr (see the -defs.h)
+ * @param chcsr_chip    the chip for the csr/field
+ * @param chcsr_fld     the field in the csr
+ * @param chcsr_val     the value for field
+ */
+#define CVMX_HELPER_WRITE_CSR(chcsr_init, chcsr_csr, chcsr_type,        \
+    chcsr_chip, chcsr_fld, chcsr_val)                                   \
+        do {                                                            \
+                chcsr_type csr;                                         \
+                if ((chcsr_init) == CVMX_HELPER_CSR_INIT_READ)          \
+                        csr.u64 = cvmx_read_csr(chcsr_csr);             \
+                else                                                    \
+                        csr.u64 = (chcsr_init);                         \
+                csr.chcsr_chip.chcsr_fld = (chcsr_val);                 \
+                cvmx_write_csr((chcsr_csr), csr.u64);                   \
+        } while(0)
+
+/*
+ * CVMX_HELPER_WRITE_CSR0--set a field in a CSR with the initial value of 0
+ */
+#define CVMX_HELPER_WRITE_CSR0(chcsr_csr, chcsr_type, chcsr_chip,       \
+    chcsr_fld, chcsr_val)                                               \
+        CVMX_HELPER_WRITE_CSR(CVMX_HELPER_CSR_INIT0, chcsr_csr,         \
+            chcsr_type, chcsr_chip, chcsr_fld, chcsr_val)
+
+/*
+ * CVMX_HELPER_WRITE_CSR1--set a field in a CSR with the initial value of
+ *                      the CSR's current value.
+ */
+#define CVMX_HELPER_WRITE_CSR1(chcsr_csr, chcsr_type, chcsr_chip,       \
+    chcsr_fld, chcsr_val)                                               \
+        CVMX_HELPER_WRITE_CSR(CVMX_HELPER_CSR_INIT_READ, chcsr_csr,     \
+            chcsr_type, chcsr_chip, chcsr_fld, chcsr_val)
+
+
 typedef enum
 {
     CVMX_HELPER_INTERFACE_MODE_DISABLED,
@@ -82,6 +132,8 @@ typedef enum
     CVMX_HELPER_INTERFACE_MODE_NPI,
     CVMX_HELPER_INTERFACE_MODE_LOOP,
     CVMX_HELPER_INTERFACE_MODE_SRIO,
+    CVMX_HELPER_INTERFACE_MODE_ILK,
+    CVMX_HELPER_INTERFACE_MODE_RXAUI,
 } cvmx_helper_interface_mode_t;
 
 typedef union
@@ -101,6 +153,7 @@ typedef union
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
 
 #include "cvmx-helper-errata.h"
+#include "cvmx-helper-ilk.h"
 #include "cvmx-helper-loop.h"
 #include "cvmx-helper-npi.h"
 #include "cvmx-helper-rgmii.h"
@@ -116,17 +169,17 @@ typedef union
  * number. Users should set this pointer to a function before
  * calling any cvmx-helper operations.
  */
-extern void (*cvmx_override_pko_queue_priority)(int pko_port, uint64_t priorities[16]);
+extern CVMX_SHARED void (*cvmx_override_pko_queue_priority)(int ipd_port, uint64_t *priorities);
 
 /**
  * cvmx_override_ipd_port_setup(int ipd_port) is a function
- * pointer. It is meant to allow customization of the IPD port
+ * pointer. It is meant to allow customization of the IPD port/port kind
  * setup before packet input/output comes online. It is called
  * after cvmx-helper does the default IPD configuration, but
  * before IPD is enabled. Users should set this pointer to a
  * function before calling any cvmx-helper operations.
  */
-extern void (*cvmx_override_ipd_port_setup)(int ipd_port);
+extern CVMX_SHARED void (*cvmx_override_ipd_port_setup)(int ipd_port);
 
 /**
  * This function enables the IPD and also enables the packet interfaces.
@@ -141,6 +194,26 @@ extern void (*cvmx_override_ipd_port_setup)(int ipd_port);
 extern int cvmx_helper_ipd_and_packet_input_enable(void);
 
 /**
+ * Initialize and allocate memory for the SSO.
+ *
+ * @param wqe_entries The maximum number of work queue entries to be
+ * supported.
+ *
+ * @return Zero on success, non-zero on failure.
+ */
+extern int cvmx_helper_initialize_sso(int wqe_entries);
+
+/**
+ * Undo the effect of cvmx_helper_initialize_sso().
+ *
+ * Warning: since cvmx_bootmem_alloc() memory cannot be freed, the
+ * memory allocated by cvmx_helper_initialize_sso() will be leaked.
+ *
+ * @return Zero on success, non-zero on failure.
+ */
+extern int cvmx_helper_uninitialize_sso(void);
+
+/**
  * Initialize the PIP, IPD, and PKO hardware to support
  * simple priority based queues for the ethernet ports. Each
  * port is configured with a number of priority queues based
@@ -252,11 +325,11 @@ extern int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
 
 
 /**
- * This function probes an interface to determine the actual
- * number of hardware ports connected to it. It doesn't setup the
- * ports or enable them. The main goal here is to set the global
- * interface_port_count[interface] correctly. Hardware setup of the
- * ports will be performed later.
+ * This function probes an interface to determine the actual number of
+ * hardware ports connected to it. It does some setup the ports but
+ * doesn't enable them. The main goal here is to set the global
+ * interface_port_count[interface] correctly. Final hardware setup of
+ * the ports will be performed later.
  *
  * @param interface Interface to probe
  *
@@ -265,6 +338,16 @@ extern int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
 extern int cvmx_helper_interface_probe(int interface);
 
 /**
+ * Determine the actual number of hardware ports connected to an
+ * interface. It doesn't setup the ports or enable them.
+ *
+ * @param interface Interface to enumerate
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int cvmx_helper_interface_enumerate(int interface);
+
+/**
  * Configure a port for internal and/or external loopback. Internal loopback
  * causes packets sent by the port to be received by Octeon. External loopback
  * causes packets received from the wire to sent out again.
@@ -283,7 +366,7 @@ extern int cvmx_helper_configure_loopback(int ipd_port, int enable_internal, int
 
 #endif /* CVMX_ENABLE_PKO_FUNCTIONS */
 
-#ifdef	__cplusplus
+#ifdef  __cplusplus
 }
 #endif
 
diff --git a/sys/contrib/octeon-sdk/cvmx-hfa.c b/sys/contrib/octeon-sdk/cvmx-hfa.c
new file mode 100644
index 0000000..74dd04e
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-hfa.c
@@ -0,0 +1,174 @@
+/***********************license start***************
+ * Copyright (c) 2011  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Support library for the CN63XX, CN68XX hardware HFA engine.
+ *
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-clock.h>
+#include <asm/octeon/cvmx-dfa-defs.h>
+#include <asm/octeon/cvmx-hfa.h>
+#else
+#include "executive-config.h"
+#ifdef CVMX_ENABLE_DFA_FUNCTIONS
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-fau.h"
+#include "cvmx-cmd-queue.h"
+#include "cvmx-hfa.h"
+#endif
+#endif
+
+#ifdef CVMX_ENABLE_DFA_FUNCTIONS
+
+/**
+ * Initialize the DFA block
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_hfa_initialize(void)
+{
+    cvmx_dfa_difctl_t control;
+    cvmx_cmd_queue_result_t result;
+    void *initial_base_address;
+    int cmdsize;
+
+    cmdsize = ((CVMX_FPA_DFA_POOL_SIZE - 8) / sizeof (cvmx_dfa_command_t)) *
+        sizeof (cvmx_dfa_command_t);
+    result = cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_DFA, 0,
+                                       CVMX_FPA_DFA_POOL, cmdsize + 8);
+    if (result != CVMX_CMD_QUEUE_SUCCESS)
+        return -1;
+
+    control.u64 = 0;
+    control.s.dwbcnt = CVMX_FPA_DFA_POOL_SIZE / 128;
+    control.s.pool = CVMX_FPA_DFA_POOL;
+    control.s.size = cmdsize / sizeof(cvmx_dfa_command_t);
+    CVMX_SYNCWS;
+    cvmx_write_csr(CVMX_DFA_DIFCTL, control.u64);
+    initial_base_address = cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_DFA);
+    CVMX_SYNCWS;
+    cvmx_write_csr(CVMX_DFA_DIFRDPTR, cvmx_ptr_to_phys(initial_base_address));
+    cvmx_read_csr(CVMX_DFA_DIFRDPTR); /* Read to make sure setup is complete */
+    return 0;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_hfa_initialize);
+#endif
+
+/**
+ * Shutdown the DFA block. DFA must be idle when
+ * this function is called.
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_hfa_shutdown(void)
+{
+    if (cvmx_cmd_queue_length(CVMX_CMD_QUEUE_DFA))
+    {
+        cvmx_dprintf("ERROR: cvmx_hfa_shutdown: DFA not idle.\n");
+        return -1;
+    }
+    cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_DFA);
+    return 0;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_hfa_shutdown);
+#endif
+
+/**
+ * Submit a command to the DFA block
+ *
+ * @param command DFA command to submit
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_hfa_submit(cvmx_dfa_command_t *command)
+{
+    cvmx_cmd_queue_result_t result = cvmx_cmd_queue_write(CVMX_CMD_QUEUE_DFA, 1, 4, command->u64);
+    if (result == CVMX_CMD_QUEUE_SUCCESS)
+        cvmx_write_csr(CVMX_DFA_DBELL, 1);
+    return result;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_hfa_submit);
+#endif
+
+void *hfa_bootmem_alloc (uint64_t size, uint64_t alignment)
+{
+    int64_t address;
+
+    address = cvmx_bootmem_phy_alloc(size, 0, 0, alignment, 0);
+
+    if (address > 0)
+        return cvmx_phys_to_ptr(address);
+    else
+        return NULL;
+}
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(hfa_bootmem_alloc);
+#endif
+
+int  hfa_bootmem_free (void *ptr, uint64_t size)
+{	
+	uint64_t address;
+	address = cvmx_ptr_to_phys (ptr);
+	return __cvmx_bootmem_phy_free (address, size, 0);
+}
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(hfa_bootmem_free);
+#endif
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-hfa.h b/sys/contrib/octeon-sdk/cvmx-hfa.h
new file mode 100644
index 0000000..0dd8656
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-hfa.h
@@ -0,0 +1,437 @@
+/***********************license start***************
+ * Copyright (c) 2011  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the CN63XX, CN68XX hardware HFA engine.
+ *
+ * <hr>$Revision: 49448 $<hr>
+ */
+
+#ifndef __CVMX_HFA_H__
+#define __CVMX_HFA_H__
+
+#ifndef CVMX_BUILD_FOR_LINUX_USER
+#include "cvmx-llm.h"
+#include "cvmx-wqe.h"
+#include "cvmx-fpa.h"
+#include "cvmx-bootmem.h"
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+
+#ifdef CVMX_ENABLE_DFA_FUNCTIONS
+/* DFA queue cmd buffers */
+
+#define CVMX_FPA_DFA_POOL                   (4)             /**< DFA command buffers */
+#define CVMX_FPA_DFA_POOL_SIZE              (2 * CVMX_CACHE_LINE_SIZE)
+#endif 
+
+#else
+#include "executive-config.h"
+#ifdef CVMX_ENABLE_DFA_FUNCTIONS
+#include "cvmx-config.h"
+#endif
+#endif
+#endif
+
+#define ENABLE_DEPRECATED   /* Set to enable the old 18/36 bit names */
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	CVMX_DFA_ITYPE_MEMLOAD		0x0
+#define	CVMX_DFA_ITYPE_CACHELOAD	0x1
+#define	CVMX_DFA_ITYPE_GRAPHFREE	0x3
+#define	CVMX_DFA_ITYPE_GRAPHWALK	0x4
+
+typedef union {
+   uint64_t u64;
+   struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+      uint64_t size:24;
+      uint64_t addr:40;
+#else
+      uint64_t addr:40;
+      uint64_t size:24;
+#endif
+   } s;
+} cvmx_dfa_gather_entry_t;
+
+typedef union {
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t f1:3;
+        uint64_t unused1:2;
+        uint64_t snode:27;
+        uint64_t gather_mode:1;
+        uint64_t little_endian:1;
+        uint64_t store_full:1;
+        uint64_t load_through:1;
+        uint64_t small:1;
+        uint64_t itype:3;
+        uint64_t unused0:2;
+        uint64_t mbase:22;
+#else
+        uint64_t mbase:22;
+        uint64_t unused0:2;
+        uint64_t itype:3;
+        uint64_t small:1;
+        uint64_t load_through:1;
+        uint64_t store_full:1;
+        uint64_t little_endian:1;
+        uint64_t gather_mode:1;
+        uint64_t snode:27;
+        uint64_t unused1:2;
+        uint64_t f1:3;
+#endif
+    } walk;
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t unused4:7;
+        uint64_t dbase:9;
+        uint64_t unused3:2;
+        uint64_t cbase:14;
+        uint64_t gather_mode:1;
+        uint64_t little_endian:1;
+        uint64_t store_full:1;
+        uint64_t load_through:1;
+        uint64_t unused2:1;
+        uint64_t itype:3;
+        uint64_t unused1:6;
+        uint64_t dsize:10;
+        uint64_t unused0:2;
+        uint64_t pgid:6;
+#else
+        uint64_t pgid:6;
+        uint64_t unused0:2;
+        uint64_t dsize:10;
+        uint64_t unused1:6;
+        uint64_t itype:3;
+        uint64_t unused2:1;
+        uint64_t load_through:1;
+        uint64_t store_full:1;
+        uint64_t little_endian:1;
+        uint64_t gather_mode:1;
+        uint64_t cbase:14;
+        uint64_t unused3:2;
+        uint64_t dbase:9;
+        uint64_t unused4:7;
+#endif
+    } cload;
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t unused2:32;
+        uint64_t gather_mode:1;
+        uint64_t little_endian:1;
+        uint64_t store_full:1;
+        uint64_t load_through:1;
+        uint64_t unused1:1;
+        uint64_t itype:3;
+        uint64_t unused0:2;
+        uint64_t mbase:22;
+#else
+        uint64_t mbase:22;
+        uint64_t unused0:2;
+        uint64_t itype:3;
+        uint64_t unused1:1;
+        uint64_t load_through:1;
+        uint64_t store_full:1;
+        uint64_t little_endian:1;
+        uint64_t gather_mode:1;
+        uint64_t unused2:32;
+#endif
+    } mload;
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t unused2:34;
+        uint64_t store_full:1;
+        uint64_t unused1:2;
+        uint64_t itype:3;
+        uint64_t unused0:24;
+#else
+        uint64_t unused0:24;
+        uint64_t itype:3;
+        uint64_t unused1:2;
+        uint64_t store_full:1;
+        uint64_t unused2:34;
+#endif
+    } free;
+} cvmx_dfa_word0_t;
+
+typedef union {
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t rmax:16;
+        uint64_t f2:8;
+        uint64_t rptr:40;
+#else
+        uint64_t rptr:40;
+        uint64_t f2:8;
+        uint64_t rmax:16;
+#endif
+    } walk;
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t unused1:13;
+        uint64_t rmax:3;
+        uint64_t unused0:8;
+        uint64_t rptr:40;
+#else
+        uint64_t rptr:40;
+        uint64_t unused0:8;
+        uint64_t rmax:3;
+        uint64_t unused1:13;
+#endif
+    } cload;
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t unused1:4;
+        uint64_t rmax:12;
+        uint64_t unused0:8;
+        uint64_t rptr:40;
+#else
+        uint64_t rptr:40;
+        uint64_t unused0:8;
+        uint64_t rmax:12;
+        uint64_t unused1:4;
+#endif
+    } mload;
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t unused:24;
+        uint64_t rptr:40;
+#else
+        uint64_t rptr:40;
+        uint64_t unused:24;
+#endif
+    } free;
+} cvmx_dfa_word1_t;
+
+typedef union {
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t dlen:16;
+		uint64_t srepl:2;
+        uint64_t unused:2;
+        uint64_t clmsk:4;
+        uint64_t dptr:40;
+#else
+        uint64_t dptr:40;
+        uint64_t clmsk:4;
+        uint64_t unused:2;
+		uint64_t srepl:2;
+        uint64_t dlen:16;
+#endif
+    } walk;
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t dlen:16;
+        uint64_t unused:4;
+        uint64_t clmsk:4;
+        uint64_t dptr:40;
+#else
+        uint64_t dptr:40;
+        uint64_t clmsk:4;
+        uint64_t unused:4;
+        uint64_t dlen:16;
+#endif
+    } cload;
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t dlen:16;
+        uint64_t repl:2;
+        uint64_t unused:2;
+        uint64_t clmsk:4;
+        uint64_t dptr:40;
+#else
+        uint64_t dptr:40;
+        uint64_t clmsk:4;
+        uint64_t unused:2;
+        uint64_t repl:2;
+        uint64_t dlen:16;
+#endif
+    } mload;
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t unused1:20;
+        uint64_t clmsk:4;
+        uint64_t unused0:40;
+#else
+        uint64_t unused0:40;
+        uint64_t clmsk:4;
+        uint64_t unused1:20;
+#endif
+    } free;
+} cvmx_dfa_word2_t;
+
+typedef union {
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t unused1:2;
+        uint64_t vgid:8;
+        uint64_t unused0:5;
+        uint64_t f3:9;
+        uint64_t wqptr:40;
+#else
+        uint64_t wqptr:40;
+        uint64_t f3:9;
+        uint64_t unused0:5;
+        uint64_t vgid:8;
+        uint64_t unused1:2;
+#endif
+    } walk;
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t unused1:2;
+        uint64_t vgid:8;
+        uint64_t unused0:7;
+        uint64_t f4:7;
+        uint64_t wqptr:40;
+#else
+        uint64_t wqptr:40;
+        uint64_t f4:7;
+        uint64_t unused0:7;
+        uint64_t vgid:8;
+        uint64_t unused1:2;
+#endif
+    } cload;
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t unused1:2;
+        uint64_t vgid:8;
+        uint64_t unused0:7;
+        uint64_t f4:7;
+        uint64_t wqptr:40;
+#else
+        uint64_t wqptr:40;
+        uint64_t f4:7;
+        uint64_t unused0:7;
+        uint64_t vgid:8;
+        uint64_t unused1:2;
+#endif
+    } mload;
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t unused1:2;
+        uint64_t vgid:8;
+        uint64_t unused0:14;
+        uint64_t wqptr:40;
+#else
+        uint64_t wqptr:40;
+        uint64_t unused0:14;
+        uint64_t vgid:8;
+        uint64_t unused1:2;
+#endif
+    } free;
+} cvmx_dfa_word3_t;
+
+typedef union {
+    uint64_t u64[4];
+    struct {
+        cvmx_dfa_word0_t word0;
+        cvmx_dfa_word1_t word1;
+        cvmx_dfa_word2_t word2;
+        cvmx_dfa_word3_t word3;
+    };
+} cvmx_dfa_command_t;
+
+#ifdef CVMX_ENABLE_DFA_FUNCTIONS
+/**
+ * Initialize the DFA hardware before use
+ * Returns 0 on success, -1 on failure
+ */
+int cvmx_hfa_initialize(void);
+
+
+/**
+ * Shutdown and cleanup resources used by the DFA
+ */
+int cvmx_hfa_shutdown(void);
+
+/**
+ * Submit a command to the HFA block
+ *
+ * @param command HFA command to submit
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_hfa_submit(cvmx_dfa_command_t *command);
+
+/**
+ * Allocate a block of memory from the free list that was passed
+ * to the application by the bootloader.
+ * 
+ * @param size      Size in bytes of block to allocate
+ * @param alignment Alignment required - must be power of 2
+ *
+ *  @return pointer to block of memory, NULL on error 
+ */
+
+void *hfa_bootmem_alloc (uint64_t size, uint64_t alignment);
+
+/**
+ * Frees a block to the bootmem allocator list.  
+ *
+ * @param ptr  	   address of block  (memory pointer (void*))
+ * @param size     size of block in bytes.
+ *
+ * @return 1 on success,
+ *         0 on failure
+ *
+ */
+
+int  hfa_bootmem_free (void *ptr, uint64_t size);
+
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_HFA_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-higig.h b/sys/contrib/octeon-sdk/cvmx-higig.h
index 87dd754..426ca26 100644
--- a/sys/contrib/octeon-sdk/cvmx-higig.h
+++ b/sys/contrib/octeon-sdk/cvmx-higig.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,12 +49,14 @@
  * Functions and typedefs for using Octeon in HiGig/HiGig+/HiGig2 mode over
  * XAUI.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_HIGIG_H__
 #define __CVMX_HIGIG_H__
 #include "cvmx-wqe.h"
+#include "cvmx-helper.h"
+#include "cvmx-helper-util.h"
 
 #ifdef	__cplusplus
 extern "C" {
@@ -68,20 +70,6 @@ typedef struct
         struct
         {
             uint32_t start          : 8; /**< 8-bits of Preamble indicating start of frame */
-            uint32_t dst_modid_6    : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of
-                                            DST_MODID (bits 4:0 are in Byte 7 and bit 5 is in Byte 9). ). For HGI field
-                                            value of b'01' this field should be b'1'. For all other values of HGI it is don't
-                                            care. */
-            uint32_t src_modid_6    : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of
-                                            SRC_MODID (bits 4:0 are in Byte 4 and bit 5 is in Byte 9). For HGI field
-                                            value of b'01' this field should be b'0'. For all other values of HGI it is don't
-                                            care. */
-            uint32_t hdr_ext_len    : 3; /**< This field is valid only if the HGI field is a b'10' and it indicates the extension
-                                            to the standard 12-bytes of XGS HiGig header. Each unit represents 4
-                                            bytes, giving a total of 16 additional extension bytes. Value of b'101', b'110'
-                                            and b'111' are reserved. For HGI field value of b'01' this field should be
-                                            b'01'. For all other values of HGI it is don't care. */
-            uint32_t cng_high       : 1; /**< Congestion Bit High flag */
             uint32_t hgi            : 2; /**< HiGig interface format indicator
                                             00 = Reserved
                                             01 = Pure preamble - IEEE standard framing of 10GE
@@ -89,6 +77,20 @@ typedef struct
                                                 format, the default length of the header is 12 bytes and additional
                                                 bytes are indicated by the HDR_EXT_LEN field
                                             11 = Reserved */
+            uint32_t cng_high       : 1; /**< Congestion Bit High flag */
+            uint32_t hdr_ext_len    : 3; /**< This field is valid only if the HGI field is a b'10' and it indicates the extension
+                                            to the standard 12-bytes of XGS HiGig header. Each unit represents 4
+                                            bytes, giving a total of 16 additional extension bytes. Value of b'101', b'110'
+                                            and b'111' are reserved. For HGI field value of b'01' this field should be
+                                            b'01'. For all other values of HGI it is don't care. */
+            uint32_t src_modid_6    : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of
+                                            SRC_MODID (bits 4:0 are in Byte 4 and bit 5 is in Byte 9). For HGI field
+                                            value of b'01' this field should be b'0'. For all other values of HGI it is don't
+                                            care. */
+            uint32_t dst_modid_6    : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of
+                                            DST_MODID (bits 4:0 are in Byte 7 and bit 5 is in Byte 9). ). For HGI field
+                                            value of b'01' this field should be b'1'. For all other values of HGI it is don't
+                                            care. */
             uint32_t vid_high       : 8; /**< 8-bits of the VLAN tag information */
             uint32_t vid_low        : 8; /**< 8 bits LSB of the VLAN tag information */
         } s;
@@ -98,6 +100,8 @@ typedef struct
         uint32_t u32;
         struct
         {
+            uint32_t src_modid_low  : 5; /**< Bits 4:0 of Module ID of the source module on which the packet ingress (bit
+                                            5 is in Byte 9 and bit 6 Is in Byte 1) */
             uint32_t opcode         : 3; /**< XGS HiGig op-code, indicating the type of packet
                                             000 =     Control frames used for CPU to CPU communications
                                             001 =     Unicast packet with destination resolved; The packet can be
@@ -112,10 +116,6 @@ typedef struct
                                             101 =     Reserved
                                             110 =     Reserved
                                             111 =     Reserved */
-            uint32_t src_modid_low  : 5; /**< Bits 4:0 of Module ID of the source module on which the packet ingress (bit
-                                            5 is in Byte 9 and bit 6 Is in Byte 1) */
-            uint32_t src_port_tgid  : 6; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed
-                                            on, else it represents the physical port the packet ingressed on. */
             uint32_t pfm            : 2; /**< Three Port Filtering Modes (0, 1, 2) used in handling registed/unregistered
                                             multicast (unknown L2 multicast and IPMC) packets. This field is used
                                             when OPCODE is 011 or 100 Semantics of PFM bits are as follows;
@@ -125,22 +125,24 @@ typedef struct
                                             For unregistered L2 multicast packets:
                                                 PFM= 0 or 1 � Flood to VLAN
                                                 PFM= 2 � Drop the packet */
+            uint32_t src_port_tgid  : 6; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed
+                                            on, else it represents the physical port the packet ingressed on. */
+            uint32_t dst_port       : 5; /**< Port number of destination port on which the packet needs to egress. */
             uint32_t priority       : 3; /**< This is the internal priority of the packet. This internal priority will go through
                                             COS_SEL mapping registers to map to the actual MMU queues. */
-            uint32_t dst_port       : 5; /**< Port number of destination port on which the packet needs to egress. */
-            uint32_t dst_modid_low  : 5; /**< Bits [4-: 0] of Module ID of the destination port on which the packet needs to egress. */
+            uint32_t header_type    : 2; /**< Indicates the format of the next 4 bytes of the XGS HiGig header
+                                            00 = Overlay 1 (default)
+                                            01 = Overlay 2 (Classification Tag)
+                                            10 = Reserved
+                                            11 = Reserved */
             uint32_t cng_low        : 1; /**< Semantics of CNG_HIGH and CNG_LOW are as follows: The following
                                             encodings are to make it backward compatible:
-                                            {CNG_HIGH, CNG_LOW] - COLOR
+                                            [CNG_HIGH, CNG_LOW] - COLOR
                                             [0, 0] � Packet is green
                                             [0, 1] � Packet is red
                                             [1, 1] � Packet is yellow
                                             [1, 0] � Undefined */
-            uint32_t header_type    : 2; /**< Indicates the format of the next 4 bytes of the XGS HiGig header
-                                            00 = Overlay 1 (default)
-                                            01 = Overlay 2 (Classification Tag)
-                                            10 = Reserved
-                                            11 = Reserved */
+            uint32_t dst_modid_low  : 5; /**< Bits [4-: 0] of Module ID of the destination port on which the packet needs to egress. */
         } s;
     } dw1;
     union
@@ -148,26 +150,27 @@ typedef struct
         uint32_t u32;
         struct
         {
-            uint32_t mirror         : 1; /**< Mirror: XGS3 mode: a mirror copy packet. XGS1/2 mode: Indicates that the
-                                            packet was switched and only needs to be mirrored. */
-            uint32_t mirror_done    : 1; /**< Mirroring Done: XGS1/2 mode: Indicates that the packet was mirrored and
-                                            may still need to be switched. */
-            uint32_t mirror_only    : 1; /**< Mirror Only: XGS 1/2 mode: Indicates that the packet was switched and only
-                                            needs to be mirrored. */
-            uint32_t ingress_tagged : 1; /**< Ingress Tagged: Indicates whether the packet was tagged when it originally
-                                            ingressed the system. */
-            uint32_t dst_tgid       : 3; /**< Destination Trunk Group ID: Trunk group ID of the destination port. The
-                                            DO_NOT_LEARN bit is overlaid on the second bit of this field. */
             uint32_t dst_t          : 1; /**< Destination Trunk: Indicates that the destination port is a member of a trunk
                                             group. */
-            uint32_t vc_label_16_19 : 4; /**< VC Label: Bits 19:16 of VC label: HiGig+ added field */
-            uint32_t label_present  : 1; /**< Label Present: Indicates that header contains a 20-bit VC label: HiGig+
-                                            added field. */
-            uint32_t l3             : 1; /**< L3: Indicates that the packet is L3 switched */
-            uint32_t dst_modid_5    : 1; /**< Destination Module ID: Bit 5 of Dst_ModID (bits 4:0 are in byte 7 and bit 6
-                                            is in byte 1) */
+            uint32_t dst_tgid       : 3; /**< Destination Trunk Group ID: Trunk group ID of the destination port. The
+                                            DO_NOT_LEARN bit is overlaid on the second bit of this field. */
+            uint32_t ingress_tagged : 1; /**< Ingress Tagged: Indicates whether the packet was tagged when it originally
+                                            ingressed the system. */
+            uint32_t mirror_only    : 1; /**< Mirror Only: XGS 1/2 mode: Indicates that the packet was switched and only
+                                            needs to be mirrored. */
+            uint32_t mirror_done    : 1; /**< Mirroring Done: XGS1/2 mode: Indicates that the packet was mirrored and
+                                            may still need to be switched. */
+            uint32_t mirror         : 1; /**< Mirror: XGS3 mode: a mirror copy packet. XGS1/2 mode: Indicates that the
+                                            packet was switched and only needs to be mirrored. */
+
             uint32_t src_modid_5    : 1; /**< Source Module ID: Bit 5 of Src_ModID (bits 4:0 are in byte 4 and bit 6 is in
                                             byte 1) */
+            uint32_t dst_modid_5    : 1; /**< Destination Module ID: Bit 5 of Dst_ModID (bits 4:0 are in byte 7 and bit 6
+                                            is in byte 1) */
+            uint32_t l3             : 1; /**< L3: Indicates that the packet is L3 switched */
+            uint32_t label_present  : 1; /**< Label Present: Indicates that header contains a 20-bit VC label: HiGig+
+                                            added field. */
+            uint32_t vc_label_16_19 : 4; /**< VC Label: Bits 19:16 of VC label: HiGig+ added field */
             uint32_t vc_label_0_15  : 16;/**< VC Label: Bits 15:0 of VC label: HiGig+ added field */
         } o1;
         struct
@@ -324,26 +327,33 @@ static inline int cvmx_higig_initialize(int interface, int enable_higig2)
     cvmx_gmxx_tx_ovr_bp_t gmx_tx_ovr_bp;
     cvmx_gmxx_rxx_frm_ctl_t gmx_rx_frm_ctl;
     cvmx_gmxx_tx_xaui_ctl_t gmx_tx_xaui_ctl;
-    int i;
+    int i, pknd;
     int header_size = (enable_higig2) ? 16 : 12;
 
     /* Setup PIP to handle HiGig */
-    pip_prt_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(interface*16));
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+        pknd = cvmx_helper_get_pknd(interface, 0);
+    else
+        pknd = interface*16;
+    pip_prt_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(pknd));
     pip_prt_cfg.s.dsa_en = 0;
     pip_prt_cfg.s.higig_en = 1;
     pip_prt_cfg.s.hg_qos = 1;
     pip_prt_cfg.s.skip = header_size;
-    cvmx_write_csr(CVMX_PIP_PRT_CFGX(interface*16), pip_prt_cfg.u64);
+    cvmx_write_csr(CVMX_PIP_PRT_CFGX(pknd), pip_prt_cfg.u64);
 
     /* Setup some sample QoS defaults. These can be changed later */
-    for (i=0; i<64; i++)
+    if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
     {
-        cvmx_pip_hg_pri_qos_t pip_hg_pri_qos;
-        pip_hg_pri_qos.u64 = 0;
-        pip_hg_pri_qos.s.up_qos = 1;
-        pip_hg_pri_qos.s.pri = i;
-        pip_hg_pri_qos.s.qos = i&7;
-        cvmx_write_csr(CVMX_PIP_HG_PRI_QOS, pip_hg_pri_qos.u64);
+        for (i=0; i<64; i++)
+        {
+            cvmx_pip_hg_pri_qos_t pip_hg_pri_qos;
+            pip_hg_pri_qos.u64 = 0;
+            pip_hg_pri_qos.s.up_qos = 1;
+            pip_hg_pri_qos.s.pri = i;
+            pip_hg_pri_qos.s.qos = i&7;
+            cvmx_write_csr(CVMX_PIP_HG_PRI_QOS, pip_hg_pri_qos.u64);
+        }
     }
 
     /* Setup GMX RX to treat the HiGig header as user data to ignore */
diff --git a/sys/contrib/octeon-sdk/cvmx-ilk-defs.h b/sys/contrib/octeon-sdk/cvmx-ilk-defs.h
new file mode 100644
index 0000000..2d0b496
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-ilk-defs.h
@@ -0,0 +1,3529 @@
+/***********************license start***************
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-ilk-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon ilk.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_ILK_DEFS_H__
+#define __CVMX_ILK_DEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ILK_BIST_SUM CVMX_ILK_BIST_SUM_FUNC()
+static inline uint64_t CVMX_ILK_BIST_SUM_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_ILK_BIST_SUM not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180014000038ull);
+}
+#else
+#define CVMX_ILK_BIST_SUM (CVMX_ADD_IO_SEG(0x0001180014000038ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ILK_GBL_CFG CVMX_ILK_GBL_CFG_FUNC()
+static inline uint64_t CVMX_ILK_GBL_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_ILK_GBL_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180014000000ull);
+}
+#else
+#define CVMX_ILK_GBL_CFG (CVMX_ADD_IO_SEG(0x0001180014000000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ILK_GBL_INT CVMX_ILK_GBL_INT_FUNC()
+static inline uint64_t CVMX_ILK_GBL_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_ILK_GBL_INT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180014000008ull);
+}
+#else
+#define CVMX_ILK_GBL_INT (CVMX_ADD_IO_SEG(0x0001180014000008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ILK_GBL_INT_EN CVMX_ILK_GBL_INT_EN_FUNC()
+static inline uint64_t CVMX_ILK_GBL_INT_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_ILK_GBL_INT_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180014000010ull);
+}
+#else
+#define CVMX_ILK_GBL_INT_EN (CVMX_ADD_IO_SEG(0x0001180014000010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ILK_INT_SUM CVMX_ILK_INT_SUM_FUNC()
+static inline uint64_t CVMX_ILK_INT_SUM_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_ILK_INT_SUM not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180014000030ull);
+}
+#else
+#define CVMX_ILK_INT_SUM (CVMX_ADD_IO_SEG(0x0001180014000030ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ILK_LNE_DBG CVMX_ILK_LNE_DBG_FUNC()
+static inline uint64_t CVMX_ILK_LNE_DBG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_ILK_LNE_DBG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180014030008ull);
+}
+#else
+#define CVMX_ILK_LNE_DBG (CVMX_ADD_IO_SEG(0x0001180014030008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ILK_LNE_STS_MSG CVMX_ILK_LNE_STS_MSG_FUNC()
+static inline uint64_t CVMX_ILK_LNE_STS_MSG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_ILK_LNE_STS_MSG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180014030000ull);
+}
+#else
+#define CVMX_ILK_LNE_STS_MSG (CVMX_ADD_IO_SEG(0x0001180014030000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ILK_RXF_IDX_PMAP CVMX_ILK_RXF_IDX_PMAP_FUNC()
+static inline uint64_t CVMX_ILK_RXF_IDX_PMAP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_ILK_RXF_IDX_PMAP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180014000020ull);
+}
+#else
+#define CVMX_ILK_RXF_IDX_PMAP (CVMX_ADD_IO_SEG(0x0001180014000020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ILK_RXF_MEM_PMAP CVMX_ILK_RXF_MEM_PMAP_FUNC()
+static inline uint64_t CVMX_ILK_RXF_MEM_PMAP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_ILK_RXF_MEM_PMAP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180014000028ull);
+}
+#else
+#define CVMX_ILK_RXF_MEM_PMAP (CVMX_ADD_IO_SEG(0x0001180014000028ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_CFG0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_CFG0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020000ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_CFG0(offset) (CVMX_ADD_IO_SEG(0x0001180014020000ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_CFG1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_CFG1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020008ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_CFG1(offset) (CVMX_ADD_IO_SEG(0x0001180014020008ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_FLOW_CTL0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_FLOW_CTL0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020090ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_FLOW_CTL0(offset) (CVMX_ADD_IO_SEG(0x0001180014020090ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_FLOW_CTL1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_FLOW_CTL1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020098ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_FLOW_CTL1(offset) (CVMX_ADD_IO_SEG(0x0001180014020098ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_IDX_CAL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_IDX_CAL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800140200A0ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_IDX_CAL(offset) (CVMX_ADD_IO_SEG(0x00011800140200A0ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_IDX_STAT0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_IDX_STAT0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020070ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_IDX_STAT0(offset) (CVMX_ADD_IO_SEG(0x0001180014020070ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_IDX_STAT1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_IDX_STAT1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020078ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_IDX_STAT1(offset) (CVMX_ADD_IO_SEG(0x0001180014020078ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_INT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_INT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020010ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180014020010ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_INT_EN(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_INT_EN(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020018ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x0001180014020018ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_JABBER(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_JABBER(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800140200B8ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800140200B8ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_MEM_CAL0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_MEM_CAL0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800140200A8ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_MEM_CAL0(offset) (CVMX_ADD_IO_SEG(0x00011800140200A8ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_MEM_CAL1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_MEM_CAL1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800140200B0ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_MEM_CAL1(offset) (CVMX_ADD_IO_SEG(0x00011800140200B0ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_MEM_STAT0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_MEM_STAT0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020080ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_MEM_STAT0(offset) (CVMX_ADD_IO_SEG(0x0001180014020080ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_MEM_STAT1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_MEM_STAT1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020088ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_MEM_STAT1(offset) (CVMX_ADD_IO_SEG(0x0001180014020088ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_RID(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_RID(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800140200C0ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_RID(offset) (CVMX_ADD_IO_SEG(0x00011800140200C0ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_STAT0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_STAT0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020020ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x0001180014020020ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_STAT1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_STAT1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020028ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x0001180014020028ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_STAT2(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_STAT2(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020030ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x0001180014020030ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_STAT3(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_STAT3(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020038ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x0001180014020038ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_STAT4(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_STAT4(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020040ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x0001180014020040ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_STAT5(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_STAT5(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020048ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x0001180014020048ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_STAT6(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_STAT6(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020050ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x0001180014020050ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_STAT7(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_STAT7(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020058ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x0001180014020058ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_STAT8(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_STAT8(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020060ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x0001180014020060ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RXX_STAT9(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_RXX_STAT9(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014020068ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_RXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x0001180014020068ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RX_LNEX_CFG(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ILK_RX_LNEX_CFG(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014038000ull) + ((offset) & 7) * 1024;
+}
+#else
+#define CVMX_ILK_RX_LNEX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180014038000ull) + ((offset) & 7) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RX_LNEX_INT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ILK_RX_LNEX_INT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014038008ull) + ((offset) & 7) * 1024;
+}
+#else
+#define CVMX_ILK_RX_LNEX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180014038008ull) + ((offset) & 7) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RX_LNEX_INT_EN(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ILK_RX_LNEX_INT_EN(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014038010ull) + ((offset) & 7) * 1024;
+}
+#else
+#define CVMX_ILK_RX_LNEX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x0001180014038010ull) + ((offset) & 7) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RX_LNEX_STAT0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ILK_RX_LNEX_STAT0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014038018ull) + ((offset) & 7) * 1024;
+}
+#else
+#define CVMX_ILK_RX_LNEX_STAT0(offset) (CVMX_ADD_IO_SEG(0x0001180014038018ull) + ((offset) & 7) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RX_LNEX_STAT1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ILK_RX_LNEX_STAT1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014038020ull) + ((offset) & 7) * 1024;
+}
+#else
+#define CVMX_ILK_RX_LNEX_STAT1(offset) (CVMX_ADD_IO_SEG(0x0001180014038020ull) + ((offset) & 7) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RX_LNEX_STAT2(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ILK_RX_LNEX_STAT2(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014038028ull) + ((offset) & 7) * 1024;
+}
+#else
+#define CVMX_ILK_RX_LNEX_STAT2(offset) (CVMX_ADD_IO_SEG(0x0001180014038028ull) + ((offset) & 7) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RX_LNEX_STAT3(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ILK_RX_LNEX_STAT3(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014038030ull) + ((offset) & 7) * 1024;
+}
+#else
+#define CVMX_ILK_RX_LNEX_STAT3(offset) (CVMX_ADD_IO_SEG(0x0001180014038030ull) + ((offset) & 7) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RX_LNEX_STAT4(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ILK_RX_LNEX_STAT4(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014038038ull) + ((offset) & 7) * 1024;
+}
+#else
+#define CVMX_ILK_RX_LNEX_STAT4(offset) (CVMX_ADD_IO_SEG(0x0001180014038038ull) + ((offset) & 7) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RX_LNEX_STAT5(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ILK_RX_LNEX_STAT5(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014038040ull) + ((offset) & 7) * 1024;
+}
+#else
+#define CVMX_ILK_RX_LNEX_STAT5(offset) (CVMX_ADD_IO_SEG(0x0001180014038040ull) + ((offset) & 7) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RX_LNEX_STAT6(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ILK_RX_LNEX_STAT6(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014038048ull) + ((offset) & 7) * 1024;
+}
+#else
+#define CVMX_ILK_RX_LNEX_STAT6(offset) (CVMX_ADD_IO_SEG(0x0001180014038048ull) + ((offset) & 7) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RX_LNEX_STAT7(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ILK_RX_LNEX_STAT7(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014038050ull) + ((offset) & 7) * 1024;
+}
+#else
+#define CVMX_ILK_RX_LNEX_STAT7(offset) (CVMX_ADD_IO_SEG(0x0001180014038050ull) + ((offset) & 7) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RX_LNEX_STAT8(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ILK_RX_LNEX_STAT8(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014038058ull) + ((offset) & 7) * 1024;
+}
+#else
+#define CVMX_ILK_RX_LNEX_STAT8(offset) (CVMX_ADD_IO_SEG(0x0001180014038058ull) + ((offset) & 7) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_RX_LNEX_STAT9(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_ILK_RX_LNEX_STAT9(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014038060ull) + ((offset) & 7) * 1024;
+}
+#else
+#define CVMX_ILK_RX_LNEX_STAT9(offset) (CVMX_ADD_IO_SEG(0x0001180014038060ull) + ((offset) & 7) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ILK_SER_CFG CVMX_ILK_SER_CFG_FUNC()
+static inline uint64_t CVMX_ILK_SER_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_ILK_SER_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180014000018ull);
+}
+#else
+#define CVMX_ILK_SER_CFG (CVMX_ADD_IO_SEG(0x0001180014000018ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_TXX_CFG0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_TXX_CFG0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014010000ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_TXX_CFG0(offset) (CVMX_ADD_IO_SEG(0x0001180014010000ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_TXX_CFG1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_TXX_CFG1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014010008ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_TXX_CFG1(offset) (CVMX_ADD_IO_SEG(0x0001180014010008ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_TXX_DBG(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_TXX_DBG(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014010070ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_TXX_DBG(offset) (CVMX_ADD_IO_SEG(0x0001180014010070ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_TXX_FLOW_CTL0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_TXX_FLOW_CTL0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014010048ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_TXX_FLOW_CTL0(offset) (CVMX_ADD_IO_SEG(0x0001180014010048ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_TXX_FLOW_CTL1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_TXX_FLOW_CTL1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014010050ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_TXX_FLOW_CTL1(offset) (CVMX_ADD_IO_SEG(0x0001180014010050ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_TXX_IDX_CAL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_TXX_IDX_CAL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014010058ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_TXX_IDX_CAL(offset) (CVMX_ADD_IO_SEG(0x0001180014010058ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_TXX_IDX_PMAP(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_TXX_IDX_PMAP(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014010010ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_TXX_IDX_PMAP(offset) (CVMX_ADD_IO_SEG(0x0001180014010010ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_TXX_IDX_STAT0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_TXX_IDX_STAT0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014010020ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_TXX_IDX_STAT0(offset) (CVMX_ADD_IO_SEG(0x0001180014010020ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_TXX_IDX_STAT1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_TXX_IDX_STAT1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014010028ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_TXX_IDX_STAT1(offset) (CVMX_ADD_IO_SEG(0x0001180014010028ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_TXX_INT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_TXX_INT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014010078ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_TXX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180014010078ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_TXX_INT_EN(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_TXX_INT_EN(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014010080ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_TXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x0001180014010080ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_TXX_MEM_CAL0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_TXX_MEM_CAL0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014010060ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_TXX_MEM_CAL0(offset) (CVMX_ADD_IO_SEG(0x0001180014010060ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_TXX_MEM_CAL1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_TXX_MEM_CAL1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014010068ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_TXX_MEM_CAL1(offset) (CVMX_ADD_IO_SEG(0x0001180014010068ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_TXX_MEM_PMAP(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_TXX_MEM_PMAP(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014010018ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_TXX_MEM_PMAP(offset) (CVMX_ADD_IO_SEG(0x0001180014010018ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_TXX_MEM_STAT0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_TXX_MEM_STAT0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014010030ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_TXX_MEM_STAT0(offset) (CVMX_ADD_IO_SEG(0x0001180014010030ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_TXX_MEM_STAT1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_TXX_MEM_STAT1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014010038ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_TXX_MEM_STAT1(offset) (CVMX_ADD_IO_SEG(0x0001180014010038ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_TXX_PIPE(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_TXX_PIPE(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014010088ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_TXX_PIPE(offset) (CVMX_ADD_IO_SEG(0x0001180014010088ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ILK_TXX_RMATCH(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ILK_TXX_RMATCH(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180014010040ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_ILK_TXX_RMATCH(offset) (CVMX_ADD_IO_SEG(0x0001180014010040ull) + ((offset) & 1) * 16384)
+#endif
+
+/**
+ * cvmx_ilk_bist_sum
+ */
+union cvmx_ilk_bist_sum {
+	uint64_t u64;
+	struct cvmx_ilk_bist_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_58_63               : 6;
+	uint64_t rxf_x2p1                     : 1;  /**< Bist status of rxf.x2p_fif_mem1 */
+	uint64_t rxf_x2p0                     : 1;  /**< Bist status of rxf.x2p_fif_mem0 */
+	uint64_t rxf_pmap                     : 1;  /**< Bist status of rxf.rx_map_mem */
+	uint64_t rxf_mem2                     : 1;  /**< Bist status of rxf.rx_fif_mem2 */
+	uint64_t rxf_mem1                     : 1;  /**< Bist status of rxf.rx_fif_mem1 */
+	uint64_t rxf_mem0                     : 1;  /**< Bist status of rxf.rx_fif_mem0 */
+	uint64_t reserved_36_51               : 16;
+	uint64_t rle7_dsk1                    : 1;  /**< Bist status of lne.rle7.dsk.dsk_fif_mem1 */
+	uint64_t rle7_dsk0                    : 1;  /**< Bist status of lne.rle7.dsk.dsk_fif_mem0 */
+	uint64_t rle6_dsk1                    : 1;  /**< Bist status of lne.rle6.dsk.dsk_fif_mem1 */
+	uint64_t rle6_dsk0                    : 1;  /**< Bist status of lne.rle6.dsk.dsk_fif_mem0 */
+	uint64_t rle5_dsk1                    : 1;  /**< Bist status of lne.rle5.dsk.dsk_fif_mem1 */
+	uint64_t rle5_dsk0                    : 1;  /**< Bist status of lne.rle5.dsk.dsk_fif_mem0 */
+	uint64_t rle4_dsk1                    : 1;  /**< Bist status of lne.rle4.dsk.dsk_fif_mem1 */
+	uint64_t rle4_dsk0                    : 1;  /**< Bist status of lne.rle4.dsk.dsk_fif_mem0 */
+	uint64_t rle3_dsk1                    : 1;  /**< Bist status of lne.rle3.dsk.dsk_fif_mem1 */
+	uint64_t rle3_dsk0                    : 1;  /**< Bist status of lne.rle3.dsk.dsk_fif_mem0 */
+	uint64_t rle2_dsk1                    : 1;  /**< Bist status of lne.rle2.dsk.dsk_fif_mem1 */
+	uint64_t rle2_dsk0                    : 1;  /**< Bist status of lne.rle2.dsk.dsk_fif_mem0 */
+	uint64_t rle1_dsk1                    : 1;  /**< Bist status of lne.rle1.dsk.dsk_fif_mem1 */
+	uint64_t rle1_dsk0                    : 1;  /**< Bist status of lne.rle1.dsk.dsk_fif_mem0 */
+	uint64_t rle0_dsk1                    : 1;  /**< Bist status of lne.rle0.dsk.dsk_fif_mem1 */
+	uint64_t rle0_dsk0                    : 1;  /**< Bist status of lne.rle0.dsk.dsk_fif_mem0 */
+	uint64_t reserved_19_19               : 1;
+	uint64_t rlk1_stat1                   : 1;  /**< Bist status of rlk1.csr.stat_mem1    ***NOTE: Added in pass 2.0 */
+	uint64_t rlk1_fwc                     : 1;  /**< Bist status of rlk1.fwc.cal_chan_ram */
+	uint64_t rlk1_stat                    : 1;  /**< Bist status of rlk1.csr.stat_mem */
+	uint64_t reserved_15_15               : 1;
+	uint64_t rlk0_stat1                   : 1;  /**< Bist status of rlk0.csr.stat_mem1    ***NOTE: Added in pass 2.0 */
+	uint64_t rlk0_fwc                     : 1;  /**< Bist status of rlk0.fwc.cal_chan_ram */
+	uint64_t rlk0_stat                    : 1;  /**< Bist status of rlk0.csr.stat_mem */
+	uint64_t tlk1_stat1                   : 1;  /**< Bist status of tlk1.csr.stat_mem1 */
+	uint64_t tlk1_fwc                     : 1;  /**< Bist status of tlk1.fwc.cal_chan_ram */
+	uint64_t reserved_9_9                 : 1;
+	uint64_t tlk1_txf2                    : 1;  /**< Bist status of tlk1.txf.tx_map_mem */
+	uint64_t tlk1_txf1                    : 1;  /**< Bist status of tlk1.txf.tx_fif_mem1 */
+	uint64_t tlk1_txf0                    : 1;  /**< Bist status of tlk1.txf.tx_fif_mem0 */
+	uint64_t tlk0_stat1                   : 1;  /**< Bist status of tlk0.csr.stat_mem1 */
+	uint64_t tlk0_fwc                     : 1;  /**< Bist status of tlk0.fwc.cal_chan_ram */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t tlk0_txf2                    : 1;  /**< Bist status of tlk0.txf.tx_map_mem */
+	uint64_t tlk0_txf1                    : 1;  /**< Bist status of tlk0.txf.tx_fif_mem1 */
+	uint64_t tlk0_txf0                    : 1;  /**< Bist status of tlk0.txf.tx_fif_mem0 */
+#else
+	uint64_t tlk0_txf0                    : 1;
+	uint64_t tlk0_txf1                    : 1;
+	uint64_t tlk0_txf2                    : 1;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t tlk0_fwc                     : 1;
+	uint64_t tlk0_stat1                   : 1;
+	uint64_t tlk1_txf0                    : 1;
+	uint64_t tlk1_txf1                    : 1;
+	uint64_t tlk1_txf2                    : 1;
+	uint64_t reserved_9_9                 : 1;
+	uint64_t tlk1_fwc                     : 1;
+	uint64_t tlk1_stat1                   : 1;
+	uint64_t rlk0_stat                    : 1;
+	uint64_t rlk0_fwc                     : 1;
+	uint64_t rlk0_stat1                   : 1;
+	uint64_t reserved_15_15               : 1;
+	uint64_t rlk1_stat                    : 1;
+	uint64_t rlk1_fwc                     : 1;
+	uint64_t rlk1_stat1                   : 1;
+	uint64_t reserved_19_19               : 1;
+	uint64_t rle0_dsk0                    : 1;
+	uint64_t rle0_dsk1                    : 1;
+	uint64_t rle1_dsk0                    : 1;
+	uint64_t rle1_dsk1                    : 1;
+	uint64_t rle2_dsk0                    : 1;
+	uint64_t rle2_dsk1                    : 1;
+	uint64_t rle3_dsk0                    : 1;
+	uint64_t rle3_dsk1                    : 1;
+	uint64_t rle4_dsk0                    : 1;
+	uint64_t rle4_dsk1                    : 1;
+	uint64_t rle5_dsk0                    : 1;
+	uint64_t rle5_dsk1                    : 1;
+	uint64_t rle6_dsk0                    : 1;
+	uint64_t rle6_dsk1                    : 1;
+	uint64_t rle7_dsk0                    : 1;
+	uint64_t rle7_dsk1                    : 1;
+	uint64_t reserved_36_51               : 16;
+	uint64_t rxf_mem0                     : 1;
+	uint64_t rxf_mem1                     : 1;
+	uint64_t rxf_mem2                     : 1;
+	uint64_t rxf_pmap                     : 1;
+	uint64_t rxf_x2p0                     : 1;
+	uint64_t rxf_x2p1                     : 1;
+	uint64_t reserved_58_63               : 6;
+#endif
+	} s;
+	struct cvmx_ilk_bist_sum_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_58_63               : 6;
+	uint64_t rxf_x2p1                     : 1;  /**< Bist status of rxf.x2p_fif_mem1 */
+	uint64_t rxf_x2p0                     : 1;  /**< Bist status of rxf.x2p_fif_mem0 */
+	uint64_t rxf_pmap                     : 1;  /**< Bist status of rxf.rx_map_mem */
+	uint64_t rxf_mem2                     : 1;  /**< Bist status of rxf.rx_fif_mem2 */
+	uint64_t rxf_mem1                     : 1;  /**< Bist status of rxf.rx_fif_mem1 */
+	uint64_t rxf_mem0                     : 1;  /**< Bist status of rxf.rx_fif_mem0 */
+	uint64_t reserved_36_51               : 16;
+	uint64_t rle7_dsk1                    : 1;  /**< Bist status of lne.rle7.dsk.dsk_fif_mem1 */
+	uint64_t rle7_dsk0                    : 1;  /**< Bist status of lne.rle7.dsk.dsk_fif_mem0 */
+	uint64_t rle6_dsk1                    : 1;  /**< Bist status of lne.rle6.dsk.dsk_fif_mem1 */
+	uint64_t rle6_dsk0                    : 1;  /**< Bist status of lne.rle6.dsk.dsk_fif_mem0 */
+	uint64_t rle5_dsk1                    : 1;  /**< Bist status of lne.rle5.dsk.dsk_fif_mem1 */
+	uint64_t rle5_dsk0                    : 1;  /**< Bist status of lne.rle5.dsk.dsk_fif_mem0 */
+	uint64_t rle4_dsk1                    : 1;  /**< Bist status of lne.rle4.dsk.dsk_fif_mem1 */
+	uint64_t rle4_dsk0                    : 1;  /**< Bist status of lne.rle4.dsk.dsk_fif_mem0 */
+	uint64_t rle3_dsk1                    : 1;  /**< Bist status of lne.rle3.dsk.dsk_fif_mem1 */
+	uint64_t rle3_dsk0                    : 1;  /**< Bist status of lne.rle3.dsk.dsk_fif_mem0 */
+	uint64_t rle2_dsk1                    : 1;  /**< Bist status of lne.rle2.dsk.dsk_fif_mem1 */
+	uint64_t rle2_dsk0                    : 1;  /**< Bist status of lne.rle2.dsk.dsk_fif_mem0 */
+	uint64_t rle1_dsk1                    : 1;  /**< Bist status of lne.rle1.dsk.dsk_fif_mem1 */
+	uint64_t rle1_dsk0                    : 1;  /**< Bist status of lne.rle1.dsk.dsk_fif_mem0 */
+	uint64_t rle0_dsk1                    : 1;  /**< Bist status of lne.rle0.dsk.dsk_fif_mem1 */
+	uint64_t rle0_dsk0                    : 1;  /**< Bist status of lne.rle0.dsk.dsk_fif_mem0 */
+	uint64_t reserved_19_19               : 1;
+	uint64_t rlk1_stat1                   : 1;  /**< Bist status of rlk1.csr.stat_mem1    ***NOTE: Added in pass 2.0 */
+	uint64_t rlk1_fwc                     : 1;  /**< Bist status of rlk1.fwc.cal_chan_ram */
+	uint64_t rlk1_stat                    : 1;  /**< Bist status of rlk1.csr.stat_mem0 */
+	uint64_t reserved_15_15               : 1;
+	uint64_t rlk0_stat1                   : 1;  /**< Bist status of rlk0.csr.stat_mem1    ***NOTE: Added in pass 2.0 */
+	uint64_t rlk0_fwc                     : 1;  /**< Bist status of rlk0.fwc.cal_chan_ram */
+	uint64_t rlk0_stat                    : 1;  /**< Bist status of rlk0.csr.stat_mem0 */
+	uint64_t tlk1_stat1                   : 1;  /**< Bist status of tlk1.csr.stat_mem1 */
+	uint64_t tlk1_fwc                     : 1;  /**< Bist status of tlk1.fwc.cal_chan_ram */
+	uint64_t tlk1_stat0                   : 1;  /**< Bist status of tlk1.csr.stat_mem0 */
+	uint64_t tlk1_txf2                    : 1;  /**< Bist status of tlk1.txf.tx_map_mem */
+	uint64_t tlk1_txf1                    : 1;  /**< Bist status of tlk1.txf.tx_fif_mem1 */
+	uint64_t tlk1_txf0                    : 1;  /**< Bist status of tlk1.txf.tx_fif_mem0 */
+	uint64_t tlk0_stat1                   : 1;  /**< Bist status of tlk0.csr.stat_mem1 */
+	uint64_t tlk0_fwc                     : 1;  /**< Bist status of tlk0.fwc.cal_chan_ram */
+	uint64_t tlk0_stat0                   : 1;  /**< Bist status of tlk0.csr.stat_mem0 */
+	uint64_t tlk0_txf2                    : 1;  /**< Bist status of tlk0.txf.tx_map_mem */
+	uint64_t tlk0_txf1                    : 1;  /**< Bist status of tlk0.txf.tx_fif_mem1 */
+	uint64_t tlk0_txf0                    : 1;  /**< Bist status of tlk0.txf.tx_fif_mem0 */
+#else
+	uint64_t tlk0_txf0                    : 1;
+	uint64_t tlk0_txf1                    : 1;
+	uint64_t tlk0_txf2                    : 1;
+	uint64_t tlk0_stat0                   : 1;
+	uint64_t tlk0_fwc                     : 1;
+	uint64_t tlk0_stat1                   : 1;
+	uint64_t tlk1_txf0                    : 1;
+	uint64_t tlk1_txf1                    : 1;
+	uint64_t tlk1_txf2                    : 1;
+	uint64_t tlk1_stat0                   : 1;
+	uint64_t tlk1_fwc                     : 1;
+	uint64_t tlk1_stat1                   : 1;
+	uint64_t rlk0_stat                    : 1;
+	uint64_t rlk0_fwc                     : 1;
+	uint64_t rlk0_stat1                   : 1;
+	uint64_t reserved_15_15               : 1;
+	uint64_t rlk1_stat                    : 1;
+	uint64_t rlk1_fwc                     : 1;
+	uint64_t rlk1_stat1                   : 1;
+	uint64_t reserved_19_19               : 1;
+	uint64_t rle0_dsk0                    : 1;
+	uint64_t rle0_dsk1                    : 1;
+	uint64_t rle1_dsk0                    : 1;
+	uint64_t rle1_dsk1                    : 1;
+	uint64_t rle2_dsk0                    : 1;
+	uint64_t rle2_dsk1                    : 1;
+	uint64_t rle3_dsk0                    : 1;
+	uint64_t rle3_dsk1                    : 1;
+	uint64_t rle4_dsk0                    : 1;
+	uint64_t rle4_dsk1                    : 1;
+	uint64_t rle5_dsk0                    : 1;
+	uint64_t rle5_dsk1                    : 1;
+	uint64_t rle6_dsk0                    : 1;
+	uint64_t rle6_dsk1                    : 1;
+	uint64_t rle7_dsk0                    : 1;
+	uint64_t rle7_dsk1                    : 1;
+	uint64_t reserved_36_51               : 16;
+	uint64_t rxf_mem0                     : 1;
+	uint64_t rxf_mem1                     : 1;
+	uint64_t rxf_mem2                     : 1;
+	uint64_t rxf_pmap                     : 1;
+	uint64_t rxf_x2p0                     : 1;
+	uint64_t rxf_x2p1                     : 1;
+	uint64_t reserved_58_63               : 6;
+#endif
+	} cn68xx;
+	struct cvmx_ilk_bist_sum_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_58_63               : 6;
+	uint64_t rxf_x2p1                     : 1;  /**< Bist status of rxf.x2p_fif_mem1 */
+	uint64_t rxf_x2p0                     : 1;  /**< Bist status of rxf.x2p_fif_mem0 */
+	uint64_t rxf_pmap                     : 1;  /**< Bist status of rxf.rx_map_mem */
+	uint64_t rxf_mem2                     : 1;  /**< Bist status of rxf.rx_fif_mem2 */
+	uint64_t rxf_mem1                     : 1;  /**< Bist status of rxf.rx_fif_mem1 */
+	uint64_t rxf_mem0                     : 1;  /**< Bist status of rxf.rx_fif_mem0 */
+	uint64_t reserved_36_51               : 16;
+	uint64_t rle7_dsk1                    : 1;  /**< Bist status of lne.rle7.dsk.dsk_fif_mem1 */
+	uint64_t rle7_dsk0                    : 1;  /**< Bist status of lne.rle7.dsk.dsk_fif_mem0 */
+	uint64_t rle6_dsk1                    : 1;  /**< Bist status of lne.rle6.dsk.dsk_fif_mem1 */
+	uint64_t rle6_dsk0                    : 1;  /**< Bist status of lne.rle6.dsk.dsk_fif_mem0 */
+	uint64_t rle5_dsk1                    : 1;  /**< Bist status of lne.rle5.dsk.dsk_fif_mem1 */
+	uint64_t rle5_dsk0                    : 1;  /**< Bist status of lne.rle5.dsk.dsk_fif_mem0 */
+	uint64_t rle4_dsk1                    : 1;  /**< Bist status of lne.rle4.dsk.dsk_fif_mem1 */
+	uint64_t rle4_dsk0                    : 1;  /**< Bist status of lne.rle4.dsk.dsk_fif_mem0 */
+	uint64_t rle3_dsk1                    : 1;  /**< Bist status of lne.rle3.dsk.dsk_fif_mem1 */
+	uint64_t rle3_dsk0                    : 1;  /**< Bist status of lne.rle3.dsk.dsk_fif_mem0 */
+	uint64_t rle2_dsk1                    : 1;  /**< Bist status of lne.rle2.dsk.dsk_fif_mem1 */
+	uint64_t rle2_dsk0                    : 1;  /**< Bist status of lne.rle2.dsk.dsk_fif_mem0 */
+	uint64_t rle1_dsk1                    : 1;  /**< Bist status of lne.rle1.dsk.dsk_fif_mem1 */
+	uint64_t rle1_dsk0                    : 1;  /**< Bist status of lne.rle1.dsk.dsk_fif_mem0 */
+	uint64_t rle0_dsk1                    : 1;  /**< Bist status of lne.rle0.dsk.dsk_fif_mem1 */
+	uint64_t rle0_dsk0                    : 1;  /**< Bist status of lne.rle0.dsk.dsk_fif_mem0 */
+	uint64_t reserved_18_19               : 2;
+	uint64_t rlk1_fwc                     : 1;  /**< Bist status of rlk1.fwc.cal_chan_ram */
+	uint64_t rlk1_stat                    : 1;  /**< Bist status of rlk1.csr.stat_mem */
+	uint64_t reserved_14_15               : 2;
+	uint64_t rlk0_fwc                     : 1;  /**< Bist status of rlk0.fwc.cal_chan_ram */
+	uint64_t rlk0_stat                    : 1;  /**< Bist status of rlk0.csr.stat_mem */
+	uint64_t reserved_11_11               : 1;
+	uint64_t tlk1_fwc                     : 1;  /**< Bist status of tlk1.fwc.cal_chan_ram */
+	uint64_t tlk1_stat                    : 1;  /**< Bist status of tlk1.csr.stat_mem */
+	uint64_t tlk1_txf2                    : 1;  /**< Bist status of tlk1.txf.tx_map_mem */
+	uint64_t tlk1_txf1                    : 1;  /**< Bist status of tlk1.txf.tx_fif_mem1 */
+	uint64_t tlk1_txf0                    : 1;  /**< Bist status of tlk1.txf.tx_fif_mem0 */
+	uint64_t reserved_5_5                 : 1;
+	uint64_t tlk0_fwc                     : 1;  /**< Bist status of tlk0.fwc.cal_chan_ram */
+	uint64_t tlk0_stat                    : 1;  /**< Bist status of tlk0.csr.stat_mem */
+	uint64_t tlk0_txf2                    : 1;  /**< Bist status of tlk0.txf.tx_map_mem */
+	uint64_t tlk0_txf1                    : 1;  /**< Bist status of tlk0.txf.tx_fif_mem1 */
+	uint64_t tlk0_txf0                    : 1;  /**< Bist status of tlk0.txf.tx_fif_mem0 */
+#else
+	uint64_t tlk0_txf0                    : 1;
+	uint64_t tlk0_txf1                    : 1;
+	uint64_t tlk0_txf2                    : 1;
+	uint64_t tlk0_stat                    : 1;
+	uint64_t tlk0_fwc                     : 1;
+	uint64_t reserved_5_5                 : 1;
+	uint64_t tlk1_txf0                    : 1;
+	uint64_t tlk1_txf1                    : 1;
+	uint64_t tlk1_txf2                    : 1;
+	uint64_t tlk1_stat                    : 1;
+	uint64_t tlk1_fwc                     : 1;
+	uint64_t reserved_11_11               : 1;
+	uint64_t rlk0_stat                    : 1;
+	uint64_t rlk0_fwc                     : 1;
+	uint64_t reserved_14_15               : 2;
+	uint64_t rlk1_stat                    : 1;
+	uint64_t rlk1_fwc                     : 1;
+	uint64_t reserved_18_19               : 2;
+	uint64_t rle0_dsk0                    : 1;
+	uint64_t rle0_dsk1                    : 1;
+	uint64_t rle1_dsk0                    : 1;
+	uint64_t rle1_dsk1                    : 1;
+	uint64_t rle2_dsk0                    : 1;
+	uint64_t rle2_dsk1                    : 1;
+	uint64_t rle3_dsk0                    : 1;
+	uint64_t rle3_dsk1                    : 1;
+	uint64_t rle4_dsk0                    : 1;
+	uint64_t rle4_dsk1                    : 1;
+	uint64_t rle5_dsk0                    : 1;
+	uint64_t rle5_dsk1                    : 1;
+	uint64_t rle6_dsk0                    : 1;
+	uint64_t rle6_dsk1                    : 1;
+	uint64_t rle7_dsk0                    : 1;
+	uint64_t rle7_dsk1                    : 1;
+	uint64_t reserved_36_51               : 16;
+	uint64_t rxf_mem0                     : 1;
+	uint64_t rxf_mem1                     : 1;
+	uint64_t rxf_mem2                     : 1;
+	uint64_t rxf_pmap                     : 1;
+	uint64_t rxf_x2p0                     : 1;
+	uint64_t rxf_x2p1                     : 1;
+	uint64_t reserved_58_63               : 6;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ilk_bist_sum cvmx_ilk_bist_sum_t;
+
+/**
+ * cvmx_ilk_gbl_cfg
+ */
+union cvmx_ilk_gbl_cfg {
+	uint64_t u64;
+	struct cvmx_ilk_gbl_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t rid_rstdis                   : 1;  /**< Disable automatic reassembly-id error recovery. For diagnostic
+                                                         use only.
+
+                                                         ***NOTE: Added in pass 2.0 */
+	uint64_t reset                        : 1;  /**< Reset ILK.  For diagnostic use only.
+
+                                                         ***NOTE: Added in pass 2.0 */
+	uint64_t cclk_dis                     : 1;  /**< Disable ILK conditional clocking.   For diagnostic use only. */
+	uint64_t rxf_xlink                    : 1;  /**< Causes external loopback traffic to switch links.  Enabling
+                                                         this allow simultaneous use of external and internal loopback. */
+#else
+	uint64_t rxf_xlink                    : 1;
+	uint64_t cclk_dis                     : 1;
+	uint64_t reset                        : 1;
+	uint64_t rid_rstdis                   : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ilk_gbl_cfg_s             cn68xx;
+	struct cvmx_ilk_gbl_cfg_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_2_63                : 62;
+	uint64_t cclk_dis                     : 1;  /**< Disable ILK conditional clocking.   For diagnostic use only. */
+	uint64_t rxf_xlink                    : 1;  /**< Causes external loopback traffic to switch links.  Enabling
+                                                         this allow simultaneous use of external and internal loopback. */
+#else
+	uint64_t rxf_xlink                    : 1;
+	uint64_t cclk_dis                     : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ilk_gbl_cfg cvmx_ilk_gbl_cfg_t;
+
+/**
+ * cvmx_ilk_gbl_int
+ */
+union cvmx_ilk_gbl_int {
+	uint64_t u64;
+	struct cvmx_ilk_gbl_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_5_63                : 59;
+	uint64_t rxf_push_full                : 1;  /**< RXF overflow */
+	uint64_t rxf_pop_empty                : 1;  /**< RXF underflow */
+	uint64_t rxf_ctl_perr                 : 1;  /**< RXF parity error occurred on sideband control signals.  Data
+                                                         cycle will be dropped. */
+	uint64_t rxf_lnk1_perr                : 1;  /**< RXF parity error occurred on RxLink1 packet data
+                                                         Packet will be marked with error at eop */
+	uint64_t rxf_lnk0_perr                : 1;  /**< RXF parity error occurred on RxLink0 packet data.  Packet will
+                                                         be marked with error at eop */
+#else
+	uint64_t rxf_lnk0_perr                : 1;
+	uint64_t rxf_lnk1_perr                : 1;
+	uint64_t rxf_ctl_perr                 : 1;
+	uint64_t rxf_pop_empty                : 1;
+	uint64_t rxf_push_full                : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_ilk_gbl_int_s             cn68xx;
+	struct cvmx_ilk_gbl_int_s             cn68xxp1;
+};
+typedef union cvmx_ilk_gbl_int cvmx_ilk_gbl_int_t;
+
+/**
+ * cvmx_ilk_gbl_int_en
+ */
+union cvmx_ilk_gbl_int_en {
+	uint64_t u64;
+	struct cvmx_ilk_gbl_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_5_63                : 59;
+	uint64_t rxf_push_full                : 1;  /**< RXF overflow */
+	uint64_t rxf_pop_empty                : 1;  /**< RXF underflow */
+	uint64_t rxf_ctl_perr                 : 1;  /**< RXF parity error occurred on sideband control signals.  Data
+                                                         cycle will be dropped. */
+	uint64_t rxf_lnk1_perr                : 1;  /**< RXF parity error occurred on RxLink1 packet data
+                                                         Packet will be marked with error at eop */
+	uint64_t rxf_lnk0_perr                : 1;  /**< RXF parity error occurred on RxLink0 packet data
+                                                         Packet will be marked with error at eop */
+#else
+	uint64_t rxf_lnk0_perr                : 1;
+	uint64_t rxf_lnk1_perr                : 1;
+	uint64_t rxf_ctl_perr                 : 1;
+	uint64_t rxf_pop_empty                : 1;
+	uint64_t rxf_push_full                : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_ilk_gbl_int_en_s          cn68xx;
+	struct cvmx_ilk_gbl_int_en_s          cn68xxp1;
+};
+typedef union cvmx_ilk_gbl_int_en cvmx_ilk_gbl_int_en_t;
+
+/**
+ * cvmx_ilk_int_sum
+ */
+union cvmx_ilk_int_sum {
+	uint64_t u64;
+	struct cvmx_ilk_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_13_63               : 51;
+	uint64_t rle7_int                     : 1;  /**< RxLane7 interrupt status. See ILK_RX_LNE7_INT */
+	uint64_t rle6_int                     : 1;  /**< RxLane6 interrupt status. See ILK_RX_LNE6_INT */
+	uint64_t rle5_int                     : 1;  /**< RxLane5 interrupt status. See ILK_RX_LNE5_INT */
+	uint64_t rle4_int                     : 1;  /**< RxLane4 interrupt status. See ILK_RX_LNE4_INT */
+	uint64_t rle3_int                     : 1;  /**< RxLane3 interrupt status. See ILK_RX_LNE3_INT */
+	uint64_t rle2_int                     : 1;  /**< RxLane2 interrupt status. See ILK_RX_LNE2_INT */
+	uint64_t rle1_int                     : 1;  /**< RxLane1 interrupt status. See ILK_RX_LNE1_INT */
+	uint64_t rle0_int                     : 1;  /**< RxLane0 interrupt status. See ILK_RX_LNE0_INT */
+	uint64_t rlk1_int                     : 1;  /**< RxLink1 interrupt status. See ILK_RX1_INT */
+	uint64_t rlk0_int                     : 1;  /**< RxLink0 interrupt status. See ILK_RX0_INT */
+	uint64_t tlk1_int                     : 1;  /**< TxLink1 interrupt status. See ILK_TX1_INT */
+	uint64_t tlk0_int                     : 1;  /**< TxLink0 interrupt status. See ILK_TX0_INT */
+	uint64_t gbl_int                      : 1;  /**< Global interrupt status. See ILK_GBL_INT */
+#else
+	uint64_t gbl_int                      : 1;
+	uint64_t tlk0_int                     : 1;
+	uint64_t tlk1_int                     : 1;
+	uint64_t rlk0_int                     : 1;
+	uint64_t rlk1_int                     : 1;
+	uint64_t rle0_int                     : 1;
+	uint64_t rle1_int                     : 1;
+	uint64_t rle2_int                     : 1;
+	uint64_t rle3_int                     : 1;
+	uint64_t rle4_int                     : 1;
+	uint64_t rle5_int                     : 1;
+	uint64_t rle6_int                     : 1;
+	uint64_t rle7_int                     : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_ilk_int_sum_s             cn68xx;
+	struct cvmx_ilk_int_sum_s             cn68xxp1;
+};
+typedef union cvmx_ilk_int_sum cvmx_ilk_int_sum_t;
+
+/**
+ * cvmx_ilk_lne_dbg
+ */
+union cvmx_ilk_lne_dbg {
+	uint64_t u64;
+	struct cvmx_ilk_lne_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_60_63               : 4;
+	uint64_t tx_bad_crc32                 : 1;  /**< Send 1 diagnostic word with bad CRC32 to the selected lane.
+                                                         Note: injects just once */
+	uint64_t tx_bad_6467_cnt              : 5;  /**< Send N bad 64B/67B codewords on selected lane */
+	uint64_t tx_bad_sync_cnt              : 3;  /**< Send N bad sync words on selected lane */
+	uint64_t tx_bad_scram_cnt             : 3;  /**< Send N bad scram state on selected lane */
+	uint64_t reserved_40_47               : 8;
+	uint64_t tx_bad_lane_sel              : 8;  /**< Select lane to apply error injection counts */
+	uint64_t reserved_24_31               : 8;
+	uint64_t tx_dis_dispr                 : 8;  /**< Per-lane disparity disable */
+	uint64_t reserved_8_15                : 8;
+	uint64_t tx_dis_scram                 : 8;  /**< Per-lane scrambler disable */
+#else
+	uint64_t tx_dis_scram                 : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t tx_dis_dispr                 : 8;
+	uint64_t reserved_24_31               : 8;
+	uint64_t tx_bad_lane_sel              : 8;
+	uint64_t reserved_40_47               : 8;
+	uint64_t tx_bad_scram_cnt             : 3;
+	uint64_t tx_bad_sync_cnt              : 3;
+	uint64_t tx_bad_6467_cnt              : 5;
+	uint64_t tx_bad_crc32                 : 1;
+	uint64_t reserved_60_63               : 4;
+#endif
+	} s;
+	struct cvmx_ilk_lne_dbg_s             cn68xx;
+	struct cvmx_ilk_lne_dbg_s             cn68xxp1;
+};
+typedef union cvmx_ilk_lne_dbg cvmx_ilk_lne_dbg_t;
+
+/**
+ * cvmx_ilk_lne_sts_msg
+ */
+union cvmx_ilk_lne_sts_msg {
+	uint64_t u64;
+	struct cvmx_ilk_lne_sts_msg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t rx_lnk_stat                  : 8;  /**< Link status received in the diagnostic word (per-lane) */
+	uint64_t reserved_40_47               : 8;
+	uint64_t rx_lne_stat                  : 8;  /**< Lane status received in the diagnostic word (per-lane) */
+	uint64_t reserved_24_31               : 8;
+	uint64_t tx_lnk_stat                  : 8;  /**< Link status transmitted in the diagnostic word (per-lane) */
+	uint64_t reserved_8_15                : 8;
+	uint64_t tx_lne_stat                  : 8;  /**< Lane status transmitted in the diagnostic word (per-lane) */
+#else
+	uint64_t tx_lne_stat                  : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t tx_lnk_stat                  : 8;
+	uint64_t reserved_24_31               : 8;
+	uint64_t rx_lne_stat                  : 8;
+	uint64_t reserved_40_47               : 8;
+	uint64_t rx_lnk_stat                  : 8;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_ilk_lne_sts_msg_s         cn68xx;
+	struct cvmx_ilk_lne_sts_msg_s         cn68xxp1;
+};
+typedef union cvmx_ilk_lne_sts_msg cvmx_ilk_lne_sts_msg_t;
+
+/**
+ * cvmx_ilk_rx#_cfg0
+ */
+union cvmx_ilk_rxx_cfg0 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_cfg0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t ext_lpbk_fc                  : 1;  /**< Enable Rx-Tx flowcontrol loopback (external) */
+	uint64_t ext_lpbk                     : 1;  /**< Enable Rx-Tx data loopback (external). Note that with differing
+                                                         transmit & receive clocks, skip word are  inserted/deleted */
+	uint64_t reserved_60_61               : 2;
+	uint64_t lnk_stats_wrap               : 1;  /**< Upon overflow, a statistics counter should wrap instead of
+                                                         saturating.
+
+                                                         ***NOTE: Added in pass 2.0 */
+	uint64_t bcw_push                     : 1;  /**< The 8 byte burst control word containing the SOP will be
+                                                         prepended to the corresponding packet.
+
+                                                         ***NOTE: Added in pass 2.0 */
+	uint64_t mproto_ign                   : 1;  /**< When LA_MODE=1 and MPROTO_IGN=0, the multi-protocol bit of the
+                                                         LA control word is used to determine if the burst is an LA or
+                                                         non-LA burst.   When LA_MODE=1 and MPROTO_IGN=1, all bursts
+                                                         are treated LA.   When LA_MODE=0, this field is ignored
+
+                                                         ***NOTE: Added in pass 2.0 */
+	uint64_t ptrn_mode                    : 1;  /**< Enable programmable test pattern mode */
+	uint64_t lnk_stats_rdclr              : 1;  /**< CSR read to ILK_RXx_STAT* clears the counter after returning
+                                                         its current value. */
+	uint64_t lnk_stats_ena                : 1;  /**< Enable link statistics counters */
+	uint64_t mltuse_fc_ena                : 1;  /**< Use multi-use field for calendar */
+	uint64_t cal_ena                      : 1;  /**< Enable Rx calendar.  When the calendar table is disabled, all
+                                                         port-pipes receive XON. */
+	uint64_t mfrm_len                     : 13; /**< The quantity of data sent on each lane including one sync word,
+                                                         scrambler state, diag word, zero or more skip words, and the
+                                                         data  payload.  Must be large than ILK_RXX_CFG1[SKIP_CNT]+9.
+                                                         Supported range:ILK_RXX_CFG1[SKIP_CNT]+9 < MFRM_LEN <= 4096) */
+	uint64_t brst_shrt                    : 7;  /**< Minimum interval between burst control words, as a multiple of
+                                                         8 bytes.  Supported range from 8 bytes to 512 (ie. 0 <
+                                                         BRST_SHRT <= 64)
+                                                         This field affects the ILK_RX*_STAT4[BRST_SHRT_ERR_CNT]
+                                                         counter. It does not affect correct operation of the link. */
+	uint64_t lane_rev                     : 1;  /**< Lane reversal.   When enabled, lane de-striping is performed
+                                                         from most significant lane enabled to least significant lane
+                                                         enabled.  LANE_ENA must be zero before changing LANE_REV. */
+	uint64_t brst_max                     : 5;  /**< Maximum size of a data burst, as a multiple of 64 byte blocks.
+                                                         Supported range is from 64 bytes to  1024 bytes. (ie. 0 <
+                                                         BRST_MAX <= 16)
+                                                         This field affects the ILK_RX*_STAT2[BRST_NOT_FULL_CNT] and
+                                                         ILK_RX*_STAT3[BRST_MAX_ERR_CNT] counters. It does not affect
+                                                         correct operation of the link. */
+	uint64_t reserved_25_25               : 1;
+	uint64_t cal_depth                    : 9;  /**< Number of valid entries in the calendar.   Supported range from
+                                                         1 to 288. */
+	uint64_t reserved_8_15                : 8;
+	uint64_t lane_ena                     : 8;  /**< Lane enable mask.  Link is enabled if any lane is enabled.  The
+                                                         same lane should not be enabled in multiple ILK_RXx_CFG0.  Each
+                                                         bit of LANE_ENA maps to a RX lane (RLE) and a QLM lane.  NOTE:
+                                                         LANE_REV has no effect on this mapping.
+
+                                                               LANE_ENA[0] = RLE0 = QLM1 lane 0
+                                                               LANE_ENA[1] = RLE1 = QLM1 lane 1
+                                                               LANE_ENA[2] = RLE2 = QLM1 lane 2
+                                                               LANE_ENA[3] = RLE3 = QLM1 lane 3
+                                                               LANE_ENA[4] = RLE4 = QLM2 lane 0
+                                                               LANE_ENA[5] = RLE5 = QLM2 lane 1
+                                                               LANE_ENA[6] = RLE6 = QLM2 lane 2
+                                                               LANE_ENA[7] = RLE7 = QLM2 lane 3 */
+#else
+	uint64_t lane_ena                     : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t cal_depth                    : 9;
+	uint64_t reserved_25_25               : 1;
+	uint64_t brst_max                     : 5;
+	uint64_t lane_rev                     : 1;
+	uint64_t brst_shrt                    : 7;
+	uint64_t mfrm_len                     : 13;
+	uint64_t cal_ena                      : 1;
+	uint64_t mltuse_fc_ena                : 1;
+	uint64_t lnk_stats_ena                : 1;
+	uint64_t lnk_stats_rdclr              : 1;
+	uint64_t ptrn_mode                    : 1;
+	uint64_t mproto_ign                   : 1;
+	uint64_t bcw_push                     : 1;
+	uint64_t lnk_stats_wrap               : 1;
+	uint64_t reserved_60_61               : 2;
+	uint64_t ext_lpbk                     : 1;
+	uint64_t ext_lpbk_fc                  : 1;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_cfg0_s            cn68xx;
+	struct cvmx_ilk_rxx_cfg0_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t ext_lpbk_fc                  : 1;  /**< Enable Rx-Tx flowcontrol loopback (external) */
+	uint64_t ext_lpbk                     : 1;  /**< Enable Rx-Tx data loopback (external). Note that with differing
+                                                         transmit & receive clocks, skip word are  inserted/deleted */
+	uint64_t reserved_57_61               : 5;
+	uint64_t ptrn_mode                    : 1;  /**< Enable programmable test pattern mode */
+	uint64_t lnk_stats_rdclr              : 1;  /**< CSR read to ILK_RXx_STAT* clears the counter after returning
+                                                         its current value. */
+	uint64_t lnk_stats_ena                : 1;  /**< Enable link statistics counters */
+	uint64_t mltuse_fc_ena                : 1;  /**< Use multi-use field for calendar */
+	uint64_t cal_ena                      : 1;  /**< Enable Rx calendar.  When the calendar table is disabled, all
+                                                         port-pipes receive XON. */
+	uint64_t mfrm_len                     : 13; /**< The quantity of data sent on each lane including one sync word,
+                                                         scrambler state, diag word, zero or more skip words, and the
+                                                         data  payload.  Must be large than ILK_RXX_CFG1[SKIP_CNT]+9.
+                                                         Supported range:ILK_RXX_CFG1[SKIP_CNT]+9 < MFRM_LEN <= 4096) */
+	uint64_t brst_shrt                    : 7;  /**< Minimum interval between burst control words, as a multiple of
+                                                         8 bytes.  Supported range from 8 bytes to 512 (ie. 0 <
+                                                         BRST_SHRT <= 64)
+                                                         This field affects the ILK_RX*_STAT4[BRST_SHRT_ERR_CNT]
+                                                         counter. It does not affect correct operation of the link. */
+	uint64_t lane_rev                     : 1;  /**< Lane reversal.   When enabled, lane de-striping is performed
+                                                         from most significant lane enabled to least significant lane
+                                                         enabled.  LANE_ENA must be zero before changing LANE_REV. */
+	uint64_t brst_max                     : 5;  /**< Maximum size of a data burst, as a multiple of 64 byte blocks.
+                                                         Supported range is from 64 bytes to  1024 bytes. (ie. 0 <
+                                                         BRST_MAX <= 16)
+                                                         This field affects the ILK_RX*_STAT2[BRST_NOT_FULL_CNT] and
+                                                         ILK_RX*_STAT3[BRST_MAX_ERR_CNT] counters. It does not affect
+                                                         correct operation of the link. */
+	uint64_t reserved_25_25               : 1;
+	uint64_t cal_depth                    : 9;  /**< Number of valid entries in the calendar.   Supported range from
+                                                         1 to 288. */
+	uint64_t reserved_8_15                : 8;
+	uint64_t lane_ena                     : 8;  /**< Lane enable mask.  Link is enabled if any lane is enabled.  The
+                                                         same lane should not be enabled in multiple ILK_RXx_CFG0.  Each
+                                                         bit of LANE_ENA maps to a RX lane (RLE) and a QLM lane.  NOTE:
+                                                         LANE_REV has no effect on this mapping.
+
+                                                               LANE_ENA[0] = RLE0 = QLM1 lane 0
+                                                               LANE_ENA[1] = RLE1 = QLM1 lane 1
+                                                               LANE_ENA[2] = RLE2 = QLM1 lane 2
+                                                               LANE_ENA[3] = RLE3 = QLM1 lane 3
+                                                               LANE_ENA[4] = RLE4 = QLM2 lane 0
+                                                               LANE_ENA[5] = RLE5 = QLM2 lane 1
+                                                               LANE_ENA[6] = RLE6 = QLM2 lane 2
+                                                               LANE_ENA[7] = RLE7 = QLM2 lane 3 */
+#else
+	uint64_t lane_ena                     : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t cal_depth                    : 9;
+	uint64_t reserved_25_25               : 1;
+	uint64_t brst_max                     : 5;
+	uint64_t lane_rev                     : 1;
+	uint64_t brst_shrt                    : 7;
+	uint64_t mfrm_len                     : 13;
+	uint64_t cal_ena                      : 1;
+	uint64_t mltuse_fc_ena                : 1;
+	uint64_t lnk_stats_ena                : 1;
+	uint64_t lnk_stats_rdclr              : 1;
+	uint64_t ptrn_mode                    : 1;
+	uint64_t reserved_57_61               : 5;
+	uint64_t ext_lpbk                     : 1;
+	uint64_t ext_lpbk_fc                  : 1;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_cfg0 cvmx_ilk_rxx_cfg0_t;
+
+/**
+ * cvmx_ilk_rx#_cfg1
+ */
+union cvmx_ilk_rxx_cfg1 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_cfg1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_62_63               : 2;
+	uint64_t rx_fifo_cnt                  : 12; /**< Number of 64-bit words currently consumed by this link in the
+                                                         RX fifo. */
+	uint64_t reserved_48_49               : 2;
+	uint64_t rx_fifo_hwm                  : 12; /**< Number of 64-bit words consumed by this link before switch
+                                                         transmitted link flow control status from XON to XOFF.
+
+                                                         XON  = RX_FIFO_CNT < RX_FIFO_HWM
+                                                         XOFF = RX_FIFO_CNT >= RX_FIFO_HWM. */
+	uint64_t reserved_34_35               : 2;
+	uint64_t rx_fifo_max                  : 12; /**< Maximum number of 64-bit words consumed by this link in the RX
+                                                         fifo.  The sum of all links should be equal to 2048 (16KB) */
+	uint64_t pkt_flush                    : 1;  /**< Packet receive flush.  Writing PKT_FLUSH=1 will cause all open
+                                                         packets to be error-out, just as though the link went down. */
+	uint64_t pkt_ena                      : 1;  /**< Packet receive enable.  When PKT_ENA=0, any received SOP causes
+                                                         the entire packet to be dropped. */
+	uint64_t la_mode                      : 1;  /**< 0 = Interlaken
+                                                         1 = Interlaken Look-Aside */
+	uint64_t tx_link_fc                   : 1;  /**< Link flow control status transmitted by the Tx-Link
+                                                         XON when RX_FIFO_CNT <= RX_FIFO_HWM and lane alignment is done */
+	uint64_t rx_link_fc                   : 1;  /**< Link flow control status received in burst/idle control words.
+                                                         XOFF will cause Tx-Link to stop transmitting on all channels. */
+	uint64_t rx_align_ena                 : 1;  /**< Enable the lane alignment.  This should only be done after all
+                                                         enabled lanes have achieved word boundary lock and scrambler
+                                                         synchronization.  Note: Hardware will clear this when any
+                                                         participating lane loses either word boundary lock or scrambler
+                                                         synchronization */
+	uint64_t reserved_8_15                : 8;
+	uint64_t rx_bdry_lock_ena             : 8;  /**< Enable word boundary lock.  While disabled, received data is
+                                                         tossed.  Once enabled,  received data is searched for legal
+                                                         2bit patterns.  Automatically cleared for disabled lanes. */
+#else
+	uint64_t rx_bdry_lock_ena             : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t rx_align_ena                 : 1;
+	uint64_t rx_link_fc                   : 1;
+	uint64_t tx_link_fc                   : 1;
+	uint64_t la_mode                      : 1;
+	uint64_t pkt_ena                      : 1;
+	uint64_t pkt_flush                    : 1;
+	uint64_t rx_fifo_max                  : 12;
+	uint64_t reserved_34_35               : 2;
+	uint64_t rx_fifo_hwm                  : 12;
+	uint64_t reserved_48_49               : 2;
+	uint64_t rx_fifo_cnt                  : 12;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_cfg1_s            cn68xx;
+	struct cvmx_ilk_rxx_cfg1_s            cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_cfg1 cvmx_ilk_rxx_cfg1_t;
+
+/**
+ * cvmx_ilk_rx#_flow_ctl0
+ */
+union cvmx_ilk_rxx_flow_ctl0 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_flow_ctl0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t status                       : 64; /**< Flow control status for port-pipes 63-0, where a 1 indicates
+                                                         the presence of backpressure (ie. XOFF) and 0 indicates the
+                                                         absence of backpressure (ie. XON) */
+#else
+	uint64_t status                       : 64;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_flow_ctl0_s       cn68xx;
+	struct cvmx_ilk_rxx_flow_ctl0_s       cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_flow_ctl0 cvmx_ilk_rxx_flow_ctl0_t;
+
+/**
+ * cvmx_ilk_rx#_flow_ctl1
+ */
+union cvmx_ilk_rxx_flow_ctl1 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_flow_ctl1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t status                       : 64; /**< Flow control status for port-pipes 127-64, where a 1 indicates
+                                                         the presence of backpressure (ie. XOFF) and 0 indicates the
+                                                         absence of backpressure (ie. XON) */
+#else
+	uint64_t status                       : 64;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_flow_ctl1_s       cn68xx;
+	struct cvmx_ilk_rxx_flow_ctl1_s       cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_flow_ctl1 cvmx_ilk_rxx_flow_ctl1_t;
+
+/**
+ * cvmx_ilk_rx#_idx_cal
+ */
+union cvmx_ilk_rxx_idx_cal {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_idx_cal_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_14_63               : 50;
+	uint64_t inc                          : 6;  /**< Increment to add to current index for next index. NOTE:
+                                                         Increment performed after access to   ILK_RXx_MEM_CAL1 */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t index                        : 6;  /**< Specify the group of 8 entries accessed by the next CSR
+                                                         read/write to calendar table memory.  Software must never write
+                                                         IDX >= 36 */
+#else
+	uint64_t index                        : 6;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t inc                          : 6;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_idx_cal_s         cn68xx;
+	struct cvmx_ilk_rxx_idx_cal_s         cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_idx_cal cvmx_ilk_rxx_idx_cal_t;
+
+/**
+ * cvmx_ilk_rx#_idx_stat0
+ */
+union cvmx_ilk_rxx_idx_stat0 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_idx_stat0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t clr                          : 1;  /**< CSR read to ILK_RXx_MEM_STAT0 clears the selected counter after
+                                                         returning its current value. */
+	uint64_t reserved_24_30               : 7;
+	uint64_t inc                          : 8;  /**< Increment to add to current index for next index */
+	uint64_t reserved_8_15                : 8;
+	uint64_t index                        : 8;  /**< Specify the channel accessed during the next CSR read to the
+                                                         ILK_RXx_MEM_STAT0 */
+#else
+	uint64_t index                        : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t inc                          : 8;
+	uint64_t reserved_24_30               : 7;
+	uint64_t clr                          : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_idx_stat0_s       cn68xx;
+	struct cvmx_ilk_rxx_idx_stat0_s       cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_idx_stat0 cvmx_ilk_rxx_idx_stat0_t;
+
+/**
+ * cvmx_ilk_rx#_idx_stat1
+ */
+union cvmx_ilk_rxx_idx_stat1 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_idx_stat1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t clr                          : 1;  /**< CSR read to ILK_RXx_MEM_STAT1 clears the selected counter after
+                                                         returning its current value. */
+	uint64_t reserved_24_30               : 7;
+	uint64_t inc                          : 8;  /**< Increment to add to current index for next index */
+	uint64_t reserved_8_15                : 8;
+	uint64_t index                        : 8;  /**< Specify the channel accessed during the next CSR read to the
+                                                         ILK_RXx_MEM_STAT1 */
+#else
+	uint64_t index                        : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t inc                          : 8;
+	uint64_t reserved_24_30               : 7;
+	uint64_t clr                          : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_idx_stat1_s       cn68xx;
+	struct cvmx_ilk_rxx_idx_stat1_s       cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_idx_stat1 cvmx_ilk_rxx_idx_stat1_t;
+
+/**
+ * cvmx_ilk_rx#_int
+ */
+union cvmx_ilk_rxx_int {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_9_63                : 55;
+	uint64_t pkt_drop_sop                 : 1;  /**< Entire packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX,
+                                                         lack of reassembly-ids or because ILK_RXX_CFG1[PKT_ENA]=0      | $RW
+                                                         because ILK_RXX_CFG1[PKT_ENA]=0
+
+                                                         ***NOTE: Added in pass 2.0 */
+	uint64_t pkt_drop_rid                 : 1;  /**< Entire packet dropped due to the lack of reassembly-ids or
+                                                         because ILK_RXX_CFG1[PKT_ENA]=0 */
+	uint64_t pkt_drop_rxf                 : 1;  /**< Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX */
+	uint64_t lane_bad_word                : 1;  /**< A lane encountered either a bad 64B/67B codeword or an unknown
+                                                         control word type. */
+	uint64_t stat_cnt_ovfl                : 1;  /**< Statistics counter overflow */
+	uint64_t lane_align_done              : 1;  /**< Lane alignment successful */
+	uint64_t word_sync_done               : 1;  /**< All enabled lanes have achieved word boundary lock and
+                                                         scrambler synchronization.  Lane alignment may now be enabled. */
+	uint64_t crc24_err                    : 1;  /**< Burst CRC24 error.  All open packets will be receive an error. */
+	uint64_t lane_align_fail              : 1;  /**< Lane Alignment fails (4 tries).  Hardware will repeat lane
+                                                         alignment until is succeeds or until ILK_RXx_CFG1[RX_ALIGN_ENA]
+                                                         is cleared. */
+#else
+	uint64_t lane_align_fail              : 1;
+	uint64_t crc24_err                    : 1;
+	uint64_t word_sync_done               : 1;
+	uint64_t lane_align_done              : 1;
+	uint64_t stat_cnt_ovfl                : 1;
+	uint64_t lane_bad_word                : 1;
+	uint64_t pkt_drop_rxf                 : 1;
+	uint64_t pkt_drop_rid                 : 1;
+	uint64_t pkt_drop_sop                 : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_int_s             cn68xx;
+	struct cvmx_ilk_rxx_int_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_8_63                : 56;
+	uint64_t pkt_drop_rid                 : 1;  /**< Entire packet dropped due to the lack of reassembly-ids or
+                                                         because ILK_RXX_CFG1[PKT_ENA]=0 */
+	uint64_t pkt_drop_rxf                 : 1;  /**< Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX */
+	uint64_t lane_bad_word                : 1;  /**< A lane encountered either a bad 64B/67B codeword or an unknown
+                                                         control word type. */
+	uint64_t stat_cnt_ovfl                : 1;  /**< Statistics counter overflow */
+	uint64_t lane_align_done              : 1;  /**< Lane alignment successful */
+	uint64_t word_sync_done               : 1;  /**< All enabled lanes have achieved word boundary lock and
+                                                         scrambler synchronization.  Lane alignment may now be enabled. */
+	uint64_t crc24_err                    : 1;  /**< Burst CRC24 error.  All open packets will be receive an error. */
+	uint64_t lane_align_fail              : 1;  /**< Lane Alignment fails (4 tries).  Hardware will repeat lane
+                                                         alignment until is succeeds or until ILK_RXx_CFG1[RX_ALIGN_ENA]
+                                                         is cleared. */
+#else
+	uint64_t lane_align_fail              : 1;
+	uint64_t crc24_err                    : 1;
+	uint64_t word_sync_done               : 1;
+	uint64_t lane_align_done              : 1;
+	uint64_t stat_cnt_ovfl                : 1;
+	uint64_t lane_bad_word                : 1;
+	uint64_t pkt_drop_rxf                 : 1;
+	uint64_t pkt_drop_rid                 : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_int cvmx_ilk_rxx_int_t;
+
+/**
+ * cvmx_ilk_rx#_int_en
+ */
+union cvmx_ilk_rxx_int_en {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_9_63                : 55;
+	uint64_t pkt_drop_sop                 : 1;  /**< Entire packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX,
+                                                         lack of reassembly-ids or because ILK_RXX_CFG1[PKT_ENA]=0      | $PRW
+                                                         because ILK_RXX_CFG1[PKT_ENA]=0
+
+                                                         ***NOTE: Added in pass 2.0 */
+	uint64_t pkt_drop_rid                 : 1;  /**< Entire packet dropped due to the lack of reassembly-ids or
+                                                         because ILK_RXX_CFG1[PKT_ENA]=0 */
+	uint64_t pkt_drop_rxf                 : 1;  /**< Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX */
+	uint64_t lane_bad_word                : 1;  /**< A lane encountered either a bad 64B/67B codeword or an unknown
+                                                         control word type. */
+	uint64_t stat_cnt_ovfl                : 1;  /**< Statistics counter overflow */
+	uint64_t lane_align_done              : 1;  /**< Lane alignment successful */
+	uint64_t word_sync_done               : 1;  /**< All enabled lanes have achieved word boundary lock and
+                                                         scrambler synchronization.  Lane alignment may now be enabled. */
+	uint64_t crc24_err                    : 1;  /**< Burst CRC24 error.  All open packets will be receive an error. */
+	uint64_t lane_align_fail              : 1;  /**< Lane Alignment fails (4 tries) */
+#else
+	uint64_t lane_align_fail              : 1;
+	uint64_t crc24_err                    : 1;
+	uint64_t word_sync_done               : 1;
+	uint64_t lane_align_done              : 1;
+	uint64_t stat_cnt_ovfl                : 1;
+	uint64_t lane_bad_word                : 1;
+	uint64_t pkt_drop_rxf                 : 1;
+	uint64_t pkt_drop_rid                 : 1;
+	uint64_t pkt_drop_sop                 : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_int_en_s          cn68xx;
+	struct cvmx_ilk_rxx_int_en_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_8_63                : 56;
+	uint64_t pkt_drop_rid                 : 1;  /**< Entire packet dropped due to the lack of reassembly-ids or
+                                                         because ILK_RXX_CFG1[PKT_ENA]=0 */
+	uint64_t pkt_drop_rxf                 : 1;  /**< Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX */
+	uint64_t lane_bad_word                : 1;  /**< A lane encountered either a bad 64B/67B codeword or an unknown
+                                                         control word type. */
+	uint64_t stat_cnt_ovfl                : 1;  /**< Statistics counter overflow */
+	uint64_t lane_align_done              : 1;  /**< Lane alignment successful */
+	uint64_t word_sync_done               : 1;  /**< All enabled lanes have achieved word boundary lock and
+                                                         scrambler synchronization.  Lane alignment may now be enabled. */
+	uint64_t crc24_err                    : 1;  /**< Burst CRC24 error.  All open packets will be receive an error. */
+	uint64_t lane_align_fail              : 1;  /**< Lane Alignment fails (4 tries) */
+#else
+	uint64_t lane_align_fail              : 1;
+	uint64_t crc24_err                    : 1;
+	uint64_t word_sync_done               : 1;
+	uint64_t lane_align_done              : 1;
+	uint64_t stat_cnt_ovfl                : 1;
+	uint64_t lane_bad_word                : 1;
+	uint64_t pkt_drop_rxf                 : 1;
+	uint64_t pkt_drop_rid                 : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_int_en cvmx_ilk_rxx_int_en_t;
+
+/**
+ * cvmx_ilk_rx#_jabber
+ */
+union cvmx_ilk_rxx_jabber {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_jabber_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t cnt                          : 16; /**< Byte count for jabber check.   Failing packets will be
+                                                         truncated to CNT bytes.
+
+                                                         NOTE: Hardware tracks the size of up to two concurrent packet
+                                                         per link.  If using segment mode with more than 2 channels,
+                                                         some large packets may not be flagged or truncated.
+
+                                                         NOTE: CNT must be 8-byte aligned such that CNT[2:0] == 0 */
+#else
+	uint64_t cnt                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_jabber_s          cn68xx;
+	struct cvmx_ilk_rxx_jabber_s          cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_jabber cvmx_ilk_rxx_jabber_t;
+
+/**
+ * cvmx_ilk_rx#_mem_cal0
+ *
+ * Notes:
+ * Software must program the calendar table prior to enabling the
+ * link.
+ *
+ * Software must always write ILK_RXx_MEM_CAL0 then ILK_RXx_MEM_CAL1.
+ * Software must never write them in reverse order or write one without
+ * writing the other.
+ *
+ * A given calendar table entry has no effect on PKO pipe
+ * backpressure when either:
+ *  - ENTRY_CTLx=Link (1), or
+ *  - ENTRY_CTLx=XON (3) and PORT_PIPEx is outside the range of ILK_TXx_PIPE[BASE/NUMP].
+ *
+ * Within the 8 calendar table entries of one IDX value, if more
+ * than one affects the same PKO pipe, XOFF always wins over XON,
+ * regardless of the calendar table order.
+ *
+ * Software must always read ILK_RXx_MEM_CAL0 then ILK_RXx_MEM_CAL1.  Software
+ * must never read them in reverse order or read one without reading the
+ * other.
+ */
+union cvmx_ilk_rxx_mem_cal0 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_mem_cal0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_36_63               : 28;
+	uint64_t entry_ctl3                   : 2;  /**< XON/XOFF destination for entry (IDX*8)+3
+
+                                                         - 0: PKO port-pipe  Apply backpressure received from the
+                                                                            remote tranmitter to the PKO pipe selected
+                                                                            by PORT_PIPE3.
+
+                                                         - 1: Link           Apply the backpressure received from the
+                                                                            remote transmitter to link backpressure.
+                                                                            PORT_PIPE3 is unused.
+
+                                                         - 2: XOFF           Apply XOFF to the PKO pipe selected by
+                                                                            PORT_PIPE3.
+
+                                                         - 3: XON            Apply XON to the PKO pipe selected by
+                                                                            PORT_PIPE3. The calendar table entry is
+                                                                            effectively unused if PORT_PIPE3 is out of
+                                                                            range of ILK_TXx_PIPE[BASE/NUMP]. */
+	uint64_t port_pipe3                   : 7;  /**< Select PKO port-pipe for calendar table entry (IDX*8)+3
+
+                                                         PORT_PIPE3 must reside in the range of ILK_TXx_PIPE[BASE/NUMP]
+                                                         when ENTRY_CTL3 is "XOFF" (2) or "PKO port-pipe" (0). */
+	uint64_t entry_ctl2                   : 2;  /**< XON/XOFF destination for entry (IDX*8)+2
+
+                                                         - 0: PKO port-pipe  Apply backpressure received from the
+                                                                            remote tranmitter to the PKO pipe selected
+                                                                            by PORT_PIPE2.
+
+                                                         - 1: Link           Apply the backpressure received from the
+                                                                            remote transmitter to link backpressure.
+                                                                            PORT_PIPE2 is unused.
+
+                                                         - 2: XOFF           Apply XOFF to the PKO pipe selected by
+                                                                            PORT_PIPE2.
+
+                                                         - 3: XON            Apply XON to the PKO pipe selected by
+                                                                            PORT_PIPE2. The calendar table entry is
+                                                                            effectively unused if PORT_PIPE2 is out of
+                                                                            range of ILK_TXx_PIPE[BASE/NUMP]. */
+	uint64_t port_pipe2                   : 7;  /**< Select PKO port-pipe for calendar table entry (IDX*8)+2
+
+                                                         PORT_PIPE2 must reside in the range of ILK_TXx_PIPE[BASE/NUMP]
+                                                         when ENTRY_CTL2 is "XOFF" (2) or "PKO port-pipe" (0). */
+	uint64_t entry_ctl1                   : 2;  /**< XON/XOFF destination for entry (IDX*8)+1
+
+                                                         - 0: PKO port-pipe  Apply backpressure received from the
+                                                                            remote tranmitter to the PKO pipe selected
+                                                                            by PORT_PIPE1.
+
+                                                         - 1: Link           Apply the backpressure received from the
+                                                                            remote transmitter to link backpressure.
+                                                                            PORT_PIPE1 is unused.
+
+                                                         - 2: XOFF           Apply XOFF to the PKO pipe selected by
+                                                                            PORT_PIPE1.
+
+                                                         - 3: XON            Apply XON to the PKO pipe selected by
+                                                                            PORT_PIPE1. The calendar table entry is
+                                                                            effectively unused if PORT_PIPE1 is out of
+                                                                            range of ILK_TXx_PIPE[BASE/NUMP]. */
+	uint64_t port_pipe1                   : 7;  /**< Select PKO port-pipe for calendar table entry (IDX*8)+1
+
+                                                         PORT_PIPE1 must reside in the range of ILK_TXx_PIPE[BASE/NUMP]
+                                                         when ENTRY_CTL1 is "XOFF" (2) or "PKO port-pipe" (0). */
+	uint64_t entry_ctl0                   : 2;  /**< XON/XOFF destination for entry (IDX*8)+0
+
+                                                         - 0: PKO port-pipe  Apply backpressure received from the
+                                                                            remote tranmitter to the PKO pipe selected
+                                                                            by PORT_PIPE0.
+
+                                                         - 1: Link           Apply the backpressure received from the
+                                                                            remote transmitter to link backpressure.
+                                                                            PORT_PIPE0 is unused.
+
+                                                         - 2: XOFF           Apply XOFF to the PKO pipe selected by
+                                                                            PORT_PIPE0.
+
+                                                         - 3: XON            Apply XON to the PKO pipe selected by
+                                                                            PORT_PIPE0. The calendar table entry is
+                                                                            effectively unused if PORT_PIPEx is out of
+                                                                            range of ILK_TXx_PIPE[BASE/NUMP]. */
+	uint64_t port_pipe0                   : 7;  /**< Select PKO port-pipe for calendar table entry (IDX*8)+0
+
+                                                         PORT_PIPE0 must reside in the range of ILK_TXx_PIPE[BASE/NUMP]
+                                                         when ENTRY_CTL0 is "XOFF" (2) or "PKO port-pipe" (0). */
+#else
+	uint64_t port_pipe0                   : 7;
+	uint64_t entry_ctl0                   : 2;
+	uint64_t port_pipe1                   : 7;
+	uint64_t entry_ctl1                   : 2;
+	uint64_t port_pipe2                   : 7;
+	uint64_t entry_ctl2                   : 2;
+	uint64_t port_pipe3                   : 7;
+	uint64_t entry_ctl3                   : 2;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_mem_cal0_s        cn68xx;
+	struct cvmx_ilk_rxx_mem_cal0_s        cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_mem_cal0 cvmx_ilk_rxx_mem_cal0_t;
+
+/**
+ * cvmx_ilk_rx#_mem_cal1
+ *
+ * Notes:
+ * Software must program the calendar table prior to enabling the
+ * link.
+ *
+ * Software must always write ILK_RXx_MEM_CAL0 then ILK_RXx_MEM_CAL1.
+ * Software must never write them in reverse order or write one without
+ * writing the other.
+ *
+ * A given calendar table entry has no effect on PKO pipe
+ * backpressure when either:
+ *  - ENTRY_CTLx=Link (1), or
+ *  - ENTRY_CTLx=XON (3) and PORT_PIPEx is outside the range of ILK_TXx_PIPE[BASE/NUMP].
+ *
+ * Within the 8 calendar table entries of one IDX value, if more
+ * than one affects the same PKO pipe, XOFF always wins over XON,
+ * regardless of the calendar table order.
+ *
+ * Software must always read ILK_RXx_MEM_CAL0 then ILK_Rx_MEM_CAL1.  Software
+ * must never read them in reverse order or read one without reading the
+ * other.
+ */
+union cvmx_ilk_rxx_mem_cal1 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_mem_cal1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_36_63               : 28;
+	uint64_t entry_ctl7                   : 2;  /**< XON/XOFF destination for entry (IDX*8)+7
+
+                                                         - 0: PKO port-pipe  Apply backpressure received from the
+                                                                            remote tranmitter to the PKO pipe selected
+                                                                            by PORT_PIPE7.
+
+                                                         - 1: Link           Apply the backpressure received from the
+                                                                            remote transmitter to link backpressure.
+                                                                            PORT_PIPE7 is unused.
+
+                                                         - 2: XOFF           Apply XOFF to the PKO pipe selected by
+                                                                            PORT_PIPE7.
+
+                                                         - 3: XON            Apply XON to the PKO pipe selected by
+                                                                            PORT_PIPE7. The calendar table entry is
+                                                                            effectively unused if PORT_PIPE3 is out of
+                                                                            range of ILK_TXx_PIPE[BASE/NUMP]. */
+	uint64_t port_pipe7                   : 7;  /**< Select PKO port-pipe for calendar table entry (IDX*8)+7
+
+                                                         PORT_PIPE7 must reside in the range of ILK_TXx_PIPE[BASE/NUMP]
+                                                         when ENTRY_CTL7 is "XOFF" (2) or "PKO port-pipe" (0). */
+	uint64_t entry_ctl6                   : 2;  /**< XON/XOFF destination for entry (IDX*8)+6
+
+                                                         - 0: PKO port-pipe  Apply backpressure received from the
+                                                                            remote tranmitter to the PKO pipe selected
+                                                                            by PORT_PIPE6.
+
+                                                         - 1: Link           Apply the backpressure received from the
+                                                                            remote transmitter to link backpressure.
+                                                                            PORT_PIPE6 is unused.
+
+                                                         - 2: XOFF           Apply XOFF to the PKO pipe selected by
+                                                                            PORT_PIPE6.
+
+                                                         - 3: XON            Apply XON to the PKO pipe selected by
+                                                                            PORT_PIPE6. The calendar table entry is
+                                                                            effectively unused if PORT_PIPE6 is out of
+                                                                            range of ILK_TXx_PIPE[BASE/NUMP]. */
+	uint64_t port_pipe6                   : 7;  /**< Select PKO port-pipe for calendar table entry (IDX*8)+6
+
+                                                         PORT_PIPE6 must reside in the range of ILK_TXx_PIPE[BASE/NUMP]
+                                                         when ENTRY_CTL6 is "XOFF" (2) or "PKO port-pipe" (0). */
+	uint64_t entry_ctl5                   : 2;  /**< XON/XOFF destination for entry (IDX*8)+5
+
+                                                         - 0: PKO port-pipe  Apply backpressure received from the
+                                                                            remote tranmitter to the PKO pipe selected
+                                                                            by PORT_PIPE5.
+
+                                                         - 1: Link           Apply the backpressure received from the
+                                                                            remote transmitter to link backpressure.
+                                                                            PORT_PIPE5 is unused.
+
+                                                         - 2: XOFF           Apply XOFF to the PKO pipe selected by
+                                                                            PORT_PIPE5.
+
+                                                         - 3: XON            Apply XON to the PKO pipe selected by
+                                                                            PORT_PIPE5. The calendar table entry is
+                                                                            effectively unused if PORT_PIPE5 is out of
+                                                                            range of ILK_TXx_PIPE[BASE/NUMP]. */
+	uint64_t port_pipe5                   : 7;  /**< Select PKO port-pipe for calendar table entry (IDX*8)+5
+
+                                                         PORT_PIPE5 must reside in the range of ILK_TXx_PIPE[BASE/NUMP]
+                                                         when ENTRY_CTL5 is "XOFF" (2) or "PKO port-pipe" (0). */
+	uint64_t entry_ctl4                   : 2;  /**< XON/XOFF destination for entry (IDX*8)+4
+
+                                                         - 0: PKO port-pipe  Apply backpressure received from the
+                                                                            remote tranmitter to the PKO pipe selected
+                                                                            by PORT_PIPE4.
+
+                                                         - 1: Link           Apply the backpressure received from the
+                                                                            remote transmitter to link backpressure.
+                                                                            PORT_PIPE4 is unused.
+
+                                                         - 2: XOFF           Apply XOFF to the PKO pipe selected by
+                                                                            PORT_PIPE4.
+
+                                                         - 3: XON            Apply XON to the PKO pipe selected by
+                                                                            PORT_PIPE4. The calendar table entry is
+                                                                            effectively unused if PORT_PIPE4 is out of
+                                                                            range of ILK_TXx_PIPE[BASE/NUMP]. */
+	uint64_t port_pipe4                   : 7;  /**< Select PKO port-pipe for calendar table entry (IDX*8)+4
+
+                                                         PORT_PIPE4 must reside in the range of ILK_TXx_PIPE[BASE/NUMP]
+                                                         when ENTRY_CTL4 is "XOFF" (2) or "PKO port-pipe" (0). */
+#else
+	uint64_t port_pipe4                   : 7;
+	uint64_t entry_ctl4                   : 2;
+	uint64_t port_pipe5                   : 7;
+	uint64_t entry_ctl5                   : 2;
+	uint64_t port_pipe6                   : 7;
+	uint64_t entry_ctl6                   : 2;
+	uint64_t port_pipe7                   : 7;
+	uint64_t entry_ctl7                   : 2;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_mem_cal1_s        cn68xx;
+	struct cvmx_ilk_rxx_mem_cal1_s        cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_mem_cal1 cvmx_ilk_rxx_mem_cal1_t;
+
+/**
+ * cvmx_ilk_rx#_mem_stat0
+ */
+union cvmx_ilk_rxx_mem_stat0 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_mem_stat0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_28_63               : 36;
+	uint64_t rx_pkt                       : 28; /**< Number of packets received (256M)
+                                                         Channel selected by ILK_RXx_IDX_STAT0[IDX].  Saturates.
+                                                         Interrupt on saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */
+#else
+	uint64_t rx_pkt                       : 28;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_mem_stat0_s       cn68xx;
+	struct cvmx_ilk_rxx_mem_stat0_s       cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_mem_stat0 cvmx_ilk_rxx_mem_stat0_t;
+
+/**
+ * cvmx_ilk_rx#_mem_stat1
+ */
+union cvmx_ilk_rxx_mem_stat1 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_mem_stat1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_36_63               : 28;
+	uint64_t rx_bytes                     : 36; /**< Number of bytes received (64GB)
+                                                         Channel selected by ILK_RXx_IDX_STAT1[IDX].    Saturates.
+                                                         Interrupt on saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */
+#else
+	uint64_t rx_bytes                     : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_mem_stat1_s       cn68xx;
+	struct cvmx_ilk_rxx_mem_stat1_s       cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_mem_stat1 cvmx_ilk_rxx_mem_stat1_t;
+
+/**
+ * cvmx_ilk_rx#_rid
+ */
+union cvmx_ilk_rxx_rid {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_rid_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_6_63                : 58;
+	uint64_t max_cnt                      : 6;  /**< Maximum number of reassembly-ids allowed for a given link.  If
+                                                         an SOP arrives and the link has already allocated at least
+                                                         MAX_CNT reassembly-ids, the packet will be dropped.
+
+                                                         Note: An an SOP allocates a reassembly-ids.
+                                                         Note: An an EOP frees a reassembly-ids.
+
+                                                         ***NOTE: Added in pass 2.0 */
+#else
+	uint64_t max_cnt                      : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_rid_s             cn68xx;
+};
+typedef union cvmx_ilk_rxx_rid cvmx_ilk_rxx_rid_t;
+
+/**
+ * cvmx_ilk_rx#_stat0
+ */
+union cvmx_ilk_rxx_stat0 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_stat0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_33_63               : 31;
+	uint64_t crc24_match_cnt              : 33; /**< Number of CRC24 matches received.  Saturates.  Interrupt on
+                                                         saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */
+#else
+	uint64_t crc24_match_cnt              : 33;
+	uint64_t reserved_33_63               : 31;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_stat0_s           cn68xx;
+	struct cvmx_ilk_rxx_stat0_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_27_63               : 37;
+	uint64_t crc24_match_cnt              : 27; /**< Number of CRC24 matches received.  Saturates.  Interrupt on
+                                                         saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */
+#else
+	uint64_t crc24_match_cnt              : 27;
+	uint64_t reserved_27_63               : 37;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_stat0 cvmx_ilk_rxx_stat0_t;
+
+/**
+ * cvmx_ilk_rx#_stat1
+ */
+union cvmx_ilk_rxx_stat1 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_stat1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_18_63               : 46;
+	uint64_t crc24_err_cnt                : 18; /**< Number of bursts with a detected CRC error.  Saturates.
+                                                         Interrupt on saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */
+#else
+	uint64_t crc24_err_cnt                : 18;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_stat1_s           cn68xx;
+	struct cvmx_ilk_rxx_stat1_s           cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_stat1 cvmx_ilk_rxx_stat1_t;
+
+/**
+ * cvmx_ilk_rx#_stat2
+ */
+union cvmx_ilk_rxx_stat2 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_stat2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_48_63               : 16;
+	uint64_t brst_not_full_cnt            : 16; /**< Number of bursts received which terminated without an eop and
+                                                         contained fewer than BurstMax words.  Saturates.  Interrupt on
+                                                         saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */
+	uint64_t reserved_28_31               : 4;
+	uint64_t brst_cnt                     : 28; /**< Number of bursts correctly received. (ie. good CRC24, not in
+                                                         violation of BurstMax or BurstShort) */
+#else
+	uint64_t brst_cnt                     : 28;
+	uint64_t reserved_28_31               : 4;
+	uint64_t brst_not_full_cnt            : 16;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_stat2_s           cn68xx;
+	struct cvmx_ilk_rxx_stat2_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_48_63               : 16;
+	uint64_t brst_not_full_cnt            : 16; /**< Number of bursts received which terminated without an eop and
+                                                         contained fewer than BurstMax words.  Saturates.  Interrupt on
+                                                         saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */
+	uint64_t reserved_16_31               : 16;
+	uint64_t brst_cnt                     : 16; /**< Number of bursts correctly received. (ie. good CRC24, not in
+                                                         violation of BurstMax or BurstShort) */
+#else
+	uint64_t brst_cnt                     : 16;
+	uint64_t reserved_16_31               : 16;
+	uint64_t brst_not_full_cnt            : 16;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_stat2 cvmx_ilk_rxx_stat2_t;
+
+/**
+ * cvmx_ilk_rx#_stat3
+ */
+union cvmx_ilk_rxx_stat3 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_stat3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t brst_max_err_cnt             : 16; /**< Number of bursts received longer than the BurstMax parameter */
+#else
+	uint64_t brst_max_err_cnt             : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_stat3_s           cn68xx;
+	struct cvmx_ilk_rxx_stat3_s           cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_stat3 cvmx_ilk_rxx_stat3_t;
+
+/**
+ * cvmx_ilk_rx#_stat4
+ */
+union cvmx_ilk_rxx_stat4 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_stat4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t brst_shrt_err_cnt            : 16; /**< Number of bursts received that violate the BurstShort
+                                                         parameter.  Saturates.  Interrupt on saturation if
+                                                         ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */
+#else
+	uint64_t brst_shrt_err_cnt            : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_stat4_s           cn68xx;
+	struct cvmx_ilk_rxx_stat4_s           cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_stat4 cvmx_ilk_rxx_stat4_t;
+
+/**
+ * cvmx_ilk_rx#_stat5
+ */
+union cvmx_ilk_rxx_stat5 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_stat5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_23_63               : 41;
+	uint64_t align_cnt                    : 23; /**< Number of alignment sequences received  (ie. those that do not
+                                                         violate the current alignment).  Saturates.  Interrupt on
+                                                         saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */
+#else
+	uint64_t align_cnt                    : 23;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_stat5_s           cn68xx;
+	struct cvmx_ilk_rxx_stat5_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t align_cnt                    : 16; /**< Number of alignment sequences received  (ie. those that do not
+                                                         violate the current alignment).  Saturates.  Interrupt on
+                                                         saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */
+#else
+	uint64_t align_cnt                    : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_stat5 cvmx_ilk_rxx_stat5_t;
+
+/**
+ * cvmx_ilk_rx#_stat6
+ */
+union cvmx_ilk_rxx_stat6 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_stat6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t align_err_cnt                : 16; /**< Number of alignment sequences received in error (ie. those that
+                                                         violate the current alignment).  Saturates.  Interrupt on
+                                                         saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */
+#else
+	uint64_t align_err_cnt                : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_stat6_s           cn68xx;
+	struct cvmx_ilk_rxx_stat6_s           cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_stat6 cvmx_ilk_rxx_stat6_t;
+
+/**
+ * cvmx_ilk_rx#_stat7
+ */
+union cvmx_ilk_rxx_stat7 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_stat7_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t bad_64b67b_cnt               : 16; /**< Number of bad 64B/67B codewords.  Saturates.  Interrupt on
+                                                         saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */
+#else
+	uint64_t bad_64b67b_cnt               : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_stat7_s           cn68xx;
+	struct cvmx_ilk_rxx_stat7_s           cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_stat7 cvmx_ilk_rxx_stat7_t;
+
+/**
+ * cvmx_ilk_rx#_stat8
+ */
+union cvmx_ilk_rxx_stat8 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_stat8_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t pkt_drop_rid_cnt             : 16; /**< Number of packets dropped due to the lack of reassembly-ids or
+                                                         because ILK_RXX_CFG1[PKT_ENA]=0.  Saturates.  Interrupt on
+                                                         saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */
+	uint64_t pkt_drop_rxf_cnt             : 16; /**< Number of packets dropped due to RX_FIFO_CNT >= RX_FIFO_MAX.
+                                                         Saturates.  Interrupt on saturation if
+                                                         ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */
+#else
+	uint64_t pkt_drop_rxf_cnt             : 16;
+	uint64_t pkt_drop_rid_cnt             : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_stat8_s           cn68xx;
+	struct cvmx_ilk_rxx_stat8_s           cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_stat8 cvmx_ilk_rxx_stat8_t;
+
+/**
+ * cvmx_ilk_rx#_stat9
+ */
+union cvmx_ilk_rxx_stat9 {
+	uint64_t u64;
+	struct cvmx_ilk_rxx_stat9_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} s;
+	struct cvmx_ilk_rxx_stat9_s           cn68xx;
+	struct cvmx_ilk_rxx_stat9_s           cn68xxp1;
+};
+typedef union cvmx_ilk_rxx_stat9 cvmx_ilk_rxx_stat9_t;
+
+/**
+ * cvmx_ilk_rx_lne#_cfg
+ */
+union cvmx_ilk_rx_lnex_cfg {
+	uint64_t u64;
+	struct cvmx_ilk_rx_lnex_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_9_63                : 55;
+	uint64_t rx_dis_psh_skip              : 1;  /**< When RX_DIS_PSH_SKIP=0, skip words are de-stripped.
+                                                         When RX_DIS_PSH_SKIP=1, skip words are discarded in the lane
+                                                         logic.
+
+                                                         If the lane is in internal loopback mode, RX_DIS_PSH_SKIP
+                                                         is ignored and skip words are always discarded in the lane
+                                                         logic.
+
+                                                         ***NOTE: Added in pass 2.0 */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t rx_scrm_sync                 : 1;  /**< Rx scrambler synchronization status
+
+                                                         ***NOTE: Added in pass 2.0 */
+	uint64_t rx_bdry_sync                 : 1;  /**< Rx word boundary sync status */
+	uint64_t rx_dis_ukwn                  : 1;  /**< Disable normal response to unknown words.  They are still
+                                                         logged but do not cause an error to all open channels */
+	uint64_t rx_dis_scram                 : 1;  /**< Disable lane scrambler (debug) */
+	uint64_t stat_rdclr                   : 1;  /**< CSR read to ILK_RX_LNEx_STAT* clears the selected counter after
+                                                         returning its current value. */
+	uint64_t stat_ena                     : 1;  /**< Enable RX lane statistics counters */
+#else
+	uint64_t stat_ena                     : 1;
+	uint64_t stat_rdclr                   : 1;
+	uint64_t rx_dis_scram                 : 1;
+	uint64_t rx_dis_ukwn                  : 1;
+	uint64_t rx_bdry_sync                 : 1;
+	uint64_t rx_scrm_sync                 : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t rx_dis_psh_skip              : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_ilk_rx_lnex_cfg_s         cn68xx;
+	struct cvmx_ilk_rx_lnex_cfg_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_5_63                : 59;
+	uint64_t rx_bdry_sync                 : 1;  /**< Rx word boundary sync status */
+	uint64_t rx_dis_ukwn                  : 1;  /**< Disable normal response to unknown words.  They are still
+                                                         logged but do not cause an error to all open channels */
+	uint64_t rx_dis_scram                 : 1;  /**< Disable lane scrambler (debug) */
+	uint64_t stat_rdclr                   : 1;  /**< CSR read to ILK_RX_LNEx_STAT* clears the selected counter after
+                                                         returning its current value. */
+	uint64_t stat_ena                     : 1;  /**< Enable RX lane statistics counters */
+#else
+	uint64_t stat_ena                     : 1;
+	uint64_t stat_rdclr                   : 1;
+	uint64_t rx_dis_scram                 : 1;
+	uint64_t rx_dis_ukwn                  : 1;
+	uint64_t rx_bdry_sync                 : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ilk_rx_lnex_cfg cvmx_ilk_rx_lnex_cfg_t;
+
+/**
+ * cvmx_ilk_rx_lne#_int
+ */
+union cvmx_ilk_rx_lnex_int {
+	uint64_t u64;
+	struct cvmx_ilk_rx_lnex_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_9_63                : 55;
+	uint64_t bad_64b67b                   : 1;  /**< Bad 64B/67B codeword encountered.  Once the bad word reaches
+                                                         the burst control unit (as deonted by
+                                                         ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open
+                                                         packets will receive an error. */
+	uint64_t stat_cnt_ovfl                : 1;  /**< Rx lane statistic counter overflow */
+	uint64_t stat_msg                     : 1;  /**< Status bits for the link or a lane transitioned from a '1'
+                                                         (healthy) to a '0' (problem) */
+	uint64_t dskew_fifo_ovfl              : 1;  /**< Rx deskew fifo overflow occurred. */
+	uint64_t scrm_sync_loss               : 1;  /**< 4 consecutive bad sync words or 3 consecutive scramble state
+                                                         mismatches */
+	uint64_t ukwn_cntl_word               : 1;  /**< Unknown framing control word. Block type does not match any of
+                                                         (SYNC,SCRAM,SKIP,DIAG) */
+	uint64_t crc32_err                    : 1;  /**< Diagnostic CRC32 errors */
+	uint64_t bdry_sync_loss               : 1;  /**< Rx logic loses word boundary sync (16 tries).  Hardware will
+                                                         automatically attempt to regain word boundary sync */
+	uint64_t serdes_lock_loss             : 1;  /**< Rx SERDES loses lock */
+#else
+	uint64_t serdes_lock_loss             : 1;
+	uint64_t bdry_sync_loss               : 1;
+	uint64_t crc32_err                    : 1;
+	uint64_t ukwn_cntl_word               : 1;
+	uint64_t scrm_sync_loss               : 1;
+	uint64_t dskew_fifo_ovfl              : 1;
+	uint64_t stat_msg                     : 1;
+	uint64_t stat_cnt_ovfl                : 1;
+	uint64_t bad_64b67b                   : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_ilk_rx_lnex_int_s         cn68xx;
+	struct cvmx_ilk_rx_lnex_int_s         cn68xxp1;
+};
+typedef union cvmx_ilk_rx_lnex_int cvmx_ilk_rx_lnex_int_t;
+
+/**
+ * cvmx_ilk_rx_lne#_int_en
+ */
+union cvmx_ilk_rx_lnex_int_en {
+	uint64_t u64;
+	struct cvmx_ilk_rx_lnex_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_9_63                : 55;
+	uint64_t bad_64b67b                   : 1;  /**< Bad 64B/67B codeword encountered.  Once the bad word reaches
+                                                         the burst control unit (as deonted by
+                                                         ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open
+                                                         packets will receive an error. */
+	uint64_t stat_cnt_ovfl                : 1;  /**< Rx lane statistic counter overflow */
+	uint64_t stat_msg                     : 1;  /**< Status bits for the link or a lane transitioned from a '1'
+                                                         (healthy) to a '0' (problem) */
+	uint64_t dskew_fifo_ovfl              : 1;  /**< Rx deskew fifo overflow occurred. */
+	uint64_t scrm_sync_loss               : 1;  /**< 4 consecutive bad sync words or 3 consecutive scramble state
+                                                         mismatches */
+	uint64_t ukwn_cntl_word               : 1;  /**< Unknown framing control word. Block type does not match any of
+                                                         (SYNC,SCRAM,SKIP,DIAG) */
+	uint64_t crc32_err                    : 1;  /**< Diagnostic CRC32 error */
+	uint64_t bdry_sync_loss               : 1;  /**< Rx logic loses word boundary sync (16 tries).  Hardware will
+                                                         automatically attempt to regain word boundary sync */
+	uint64_t serdes_lock_loss             : 1;  /**< Rx SERDES loses lock */
+#else
+	uint64_t serdes_lock_loss             : 1;
+	uint64_t bdry_sync_loss               : 1;
+	uint64_t crc32_err                    : 1;
+	uint64_t ukwn_cntl_word               : 1;
+	uint64_t scrm_sync_loss               : 1;
+	uint64_t dskew_fifo_ovfl              : 1;
+	uint64_t stat_msg                     : 1;
+	uint64_t stat_cnt_ovfl                : 1;
+	uint64_t bad_64b67b                   : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_ilk_rx_lnex_int_en_s      cn68xx;
+	struct cvmx_ilk_rx_lnex_int_en_s      cn68xxp1;
+};
+typedef union cvmx_ilk_rx_lnex_int_en cvmx_ilk_rx_lnex_int_en_t;
+
+/**
+ * cvmx_ilk_rx_lne#_stat0
+ */
+union cvmx_ilk_rx_lnex_stat0 {
+	uint64_t u64;
+	struct cvmx_ilk_rx_lnex_stat0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_18_63               : 46;
+	uint64_t ser_lock_loss_cnt            : 18; /**< Number of times the lane lost clock-data-recovery.
+                                                         Saturates.  Interrupt on saturation if
+                                                         ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */
+#else
+	uint64_t ser_lock_loss_cnt            : 18;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_ilk_rx_lnex_stat0_s       cn68xx;
+	struct cvmx_ilk_rx_lnex_stat0_s       cn68xxp1;
+};
+typedef union cvmx_ilk_rx_lnex_stat0 cvmx_ilk_rx_lnex_stat0_t;
+
+/**
+ * cvmx_ilk_rx_lne#_stat1
+ */
+union cvmx_ilk_rx_lnex_stat1 {
+	uint64_t u64;
+	struct cvmx_ilk_rx_lnex_stat1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_18_63               : 46;
+	uint64_t bdry_sync_loss_cnt           : 18; /**< Number of times a lane lost word boundary synchronization.
+                                                         Saturates.  Interrupt on saturation if
+                                                         ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */
+#else
+	uint64_t bdry_sync_loss_cnt           : 18;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_ilk_rx_lnex_stat1_s       cn68xx;
+	struct cvmx_ilk_rx_lnex_stat1_s       cn68xxp1;
+};
+typedef union cvmx_ilk_rx_lnex_stat1 cvmx_ilk_rx_lnex_stat1_t;
+
+/**
+ * cvmx_ilk_rx_lne#_stat2
+ */
+union cvmx_ilk_rx_lnex_stat2 {
+	uint64_t u64;
+	struct cvmx_ilk_rx_lnex_stat2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_50_63               : 14;
+	uint64_t syncw_good_cnt               : 18; /**< Number of good synchronization words.  Saturates.  Interrupt on
+                                                         saturation if ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */
+	uint64_t reserved_18_31               : 14;
+	uint64_t syncw_bad_cnt                : 18; /**< Number of bad synchronization words.  Saturates.  Interrupt on
+                                                         saturation if ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */
+#else
+	uint64_t syncw_bad_cnt                : 18;
+	uint64_t reserved_18_31               : 14;
+	uint64_t syncw_good_cnt               : 18;
+	uint64_t reserved_50_63               : 14;
+#endif
+	} s;
+	struct cvmx_ilk_rx_lnex_stat2_s       cn68xx;
+	struct cvmx_ilk_rx_lnex_stat2_s       cn68xxp1;
+};
+typedef union cvmx_ilk_rx_lnex_stat2 cvmx_ilk_rx_lnex_stat2_t;
+
+/**
+ * cvmx_ilk_rx_lne#_stat3
+ */
+union cvmx_ilk_rx_lnex_stat3 {
+	uint64_t u64;
+	struct cvmx_ilk_rx_lnex_stat3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_18_63               : 46;
+	uint64_t bad_64b67b_cnt               : 18; /**< Number of bad 64B/67B words, meaning bit 65 or 64 has been
+                                                         corrupted.  Saturates.  Interrupt on saturation if
+                                                         ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */
+#else
+	uint64_t bad_64b67b_cnt               : 18;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_ilk_rx_lnex_stat3_s       cn68xx;
+	struct cvmx_ilk_rx_lnex_stat3_s       cn68xxp1;
+};
+typedef union cvmx_ilk_rx_lnex_stat3 cvmx_ilk_rx_lnex_stat3_t;
+
+/**
+ * cvmx_ilk_rx_lne#_stat4
+ */
+union cvmx_ilk_rx_lnex_stat4 {
+	uint64_t u64;
+	struct cvmx_ilk_rx_lnex_stat4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_59_63               : 5;
+	uint64_t cntl_word_cnt                : 27; /**< Number of control words received.  Saturates.  Interrupt on
+                                                         saturation if ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */
+	uint64_t reserved_27_31               : 5;
+	uint64_t data_word_cnt                : 27; /**< Number of data words received.  Saturates.  Interrupt on
+                                                         saturation if ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */
+#else
+	uint64_t data_word_cnt                : 27;
+	uint64_t reserved_27_31               : 5;
+	uint64_t cntl_word_cnt                : 27;
+	uint64_t reserved_59_63               : 5;
+#endif
+	} s;
+	struct cvmx_ilk_rx_lnex_stat4_s       cn68xx;
+	struct cvmx_ilk_rx_lnex_stat4_s       cn68xxp1;
+};
+typedef union cvmx_ilk_rx_lnex_stat4 cvmx_ilk_rx_lnex_stat4_t;
+
+/**
+ * cvmx_ilk_rx_lne#_stat5
+ */
+union cvmx_ilk_rx_lnex_stat5 {
+	uint64_t u64;
+	struct cvmx_ilk_rx_lnex_stat5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_18_63               : 46;
+	uint64_t unkwn_word_cnt               : 18; /**< Number of unknown control words.  Saturates.  Interrupt on
+                                                         saturation if ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */
+#else
+	uint64_t unkwn_word_cnt               : 18;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_ilk_rx_lnex_stat5_s       cn68xx;
+	struct cvmx_ilk_rx_lnex_stat5_s       cn68xxp1;
+};
+typedef union cvmx_ilk_rx_lnex_stat5 cvmx_ilk_rx_lnex_stat5_t;
+
+/**
+ * cvmx_ilk_rx_lne#_stat6
+ */
+union cvmx_ilk_rx_lnex_stat6 {
+	uint64_t u64;
+	struct cvmx_ilk_rx_lnex_stat6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_18_63               : 46;
+	uint64_t scrm_sync_loss_cnt           : 18; /**< Number of times scrambler synchronization was lost (due to
+                                                         either 4 consecutive bad sync words or 3 consecutive scrambler
+                                                         state mismatches).  Saturates.  Interrupt on saturation if
+                                                         ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */
+#else
+	uint64_t scrm_sync_loss_cnt           : 18;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_ilk_rx_lnex_stat6_s       cn68xx;
+	struct cvmx_ilk_rx_lnex_stat6_s       cn68xxp1;
+};
+typedef union cvmx_ilk_rx_lnex_stat6 cvmx_ilk_rx_lnex_stat6_t;
+
+/**
+ * cvmx_ilk_rx_lne#_stat7
+ */
+union cvmx_ilk_rx_lnex_stat7 {
+	uint64_t u64;
+	struct cvmx_ilk_rx_lnex_stat7_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_18_63               : 46;
+	uint64_t scrm_match_cnt               : 18; /**< Number of scrambler state matches received.  Saturates.
+                                                         Interrupt on saturation if ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */
+#else
+	uint64_t scrm_match_cnt               : 18;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_ilk_rx_lnex_stat7_s       cn68xx;
+	struct cvmx_ilk_rx_lnex_stat7_s       cn68xxp1;
+};
+typedef union cvmx_ilk_rx_lnex_stat7 cvmx_ilk_rx_lnex_stat7_t;
+
+/**
+ * cvmx_ilk_rx_lne#_stat8
+ */
+union cvmx_ilk_rx_lnex_stat8 {
+	uint64_t u64;
+	struct cvmx_ilk_rx_lnex_stat8_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_18_63               : 46;
+	uint64_t skipw_good_cnt               : 18; /**< Number of good skip words.  Saturates.  Interrupt on saturation
+                                                         if ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */
+#else
+	uint64_t skipw_good_cnt               : 18;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_ilk_rx_lnex_stat8_s       cn68xx;
+	struct cvmx_ilk_rx_lnex_stat8_s       cn68xxp1;
+};
+typedef union cvmx_ilk_rx_lnex_stat8 cvmx_ilk_rx_lnex_stat8_t;
+
+/**
+ * cvmx_ilk_rx_lne#_stat9
+ */
+union cvmx_ilk_rx_lnex_stat9 {
+	uint64_t u64;
+	struct cvmx_ilk_rx_lnex_stat9_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_50_63               : 14;
+	uint64_t crc32_err_cnt                : 18; /**< Number of errors in the lane CRC.  Saturates.  Interrupt on
+                                                         saturation if ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */
+	uint64_t reserved_27_31               : 5;
+	uint64_t crc32_match_cnt              : 27; /**< Number of CRC32 matches received.  Saturates.  Interrupt on
+                                                         saturation if ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */
+#else
+	uint64_t crc32_match_cnt              : 27;
+	uint64_t reserved_27_31               : 5;
+	uint64_t crc32_err_cnt                : 18;
+	uint64_t reserved_50_63               : 14;
+#endif
+	} s;
+	struct cvmx_ilk_rx_lnex_stat9_s       cn68xx;
+	struct cvmx_ilk_rx_lnex_stat9_s       cn68xxp1;
+};
+typedef union cvmx_ilk_rx_lnex_stat9 cvmx_ilk_rx_lnex_stat9_t;
+
+/**
+ * cvmx_ilk_rxf_idx_pmap
+ */
+union cvmx_ilk_rxf_idx_pmap {
+	uint64_t u64;
+	struct cvmx_ilk_rxf_idx_pmap_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_25_63               : 39;
+	uint64_t inc                          : 9;  /**< Increment to add to current index for next index. */
+	uint64_t reserved_9_15                : 7;
+	uint64_t index                        : 9;  /**< Specify the link/channel accessed by the next CSR read/write to
+                                                         port map memory.   IDX[8]=link, IDX[7:0]=channel */
+#else
+	uint64_t index                        : 9;
+	uint64_t reserved_9_15                : 7;
+	uint64_t inc                          : 9;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_ilk_rxf_idx_pmap_s        cn68xx;
+	struct cvmx_ilk_rxf_idx_pmap_s        cn68xxp1;
+};
+typedef union cvmx_ilk_rxf_idx_pmap cvmx_ilk_rxf_idx_pmap_t;
+
+/**
+ * cvmx_ilk_rxf_mem_pmap
+ */
+union cvmx_ilk_rxf_mem_pmap {
+	uint64_t u64;
+	struct cvmx_ilk_rxf_mem_pmap_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_6_63                : 58;
+	uint64_t port_kind                    : 6;  /**< Specify the port-kind for the link/channel selected by
+                                                         ILK_IDX_PMAP[IDX] */
+#else
+	uint64_t port_kind                    : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_ilk_rxf_mem_pmap_s        cn68xx;
+	struct cvmx_ilk_rxf_mem_pmap_s        cn68xxp1;
+};
+typedef union cvmx_ilk_rxf_mem_pmap cvmx_ilk_rxf_mem_pmap_t;
+
+/**
+ * cvmx_ilk_ser_cfg
+ */
+union cvmx_ilk_ser_cfg {
+	uint64_t u64;
+	struct cvmx_ilk_ser_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_57_63               : 7;
+	uint64_t ser_rxpol_auto               : 1;  /**< Serdes lane receive polarity auto detection mode */
+	uint64_t reserved_48_55               : 8;
+	uint64_t ser_rxpol                    : 8;  /**< Serdes lane receive polarity
+                                                         - 0: rx without inversion
+                                                         - 1: rx with inversion */
+	uint64_t reserved_32_39               : 8;
+	uint64_t ser_txpol                    : 8;  /**< Serdes lane transmit polarity
+                                                         - 0: tx without inversion
+                                                         - 1: tx with inversion */
+	uint64_t reserved_16_23               : 8;
+	uint64_t ser_reset_n                  : 8;  /**< Serdes lane reset */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ser_pwrup                    : 2;  /**< Serdes modules (QLM) power up. */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t ser_haul                     : 2;  /**< Serdes module (QLM) haul mode */
+#else
+	uint64_t ser_haul                     : 2;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t ser_pwrup                    : 2;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ser_reset_n                  : 8;
+	uint64_t reserved_16_23               : 8;
+	uint64_t ser_txpol                    : 8;
+	uint64_t reserved_32_39               : 8;
+	uint64_t ser_rxpol                    : 8;
+	uint64_t reserved_48_55               : 8;
+	uint64_t ser_rxpol_auto               : 1;
+	uint64_t reserved_57_63               : 7;
+#endif
+	} s;
+	struct cvmx_ilk_ser_cfg_s             cn68xx;
+	struct cvmx_ilk_ser_cfg_s             cn68xxp1;
+};
+typedef union cvmx_ilk_ser_cfg cvmx_ilk_ser_cfg_t;
+
+/**
+ * cvmx_ilk_tx#_cfg0
+ */
+union cvmx_ilk_txx_cfg0 {
+	uint64_t u64;
+	struct cvmx_ilk_txx_cfg0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t ext_lpbk_fc                  : 1;  /**< Enable Rx-Tx flowcontrol loopback (external) */
+	uint64_t ext_lpbk                     : 1;  /**< Enable Rx-Tx data loopback (external). Note that with differing
+                                                         transmit & receive clocks, skip word are  inserted/deleted */
+	uint64_t int_lpbk                     : 1;  /**< Enable Tx-Rx loopback (internal) */
+	uint64_t reserved_57_60               : 4;
+	uint64_t ptrn_mode                    : 1;  /**< Enable programmable test pattern mode.  This mode allows
+                                                         software to send a packet containing a programmable pattern.
+                                                         While in this mode, the scramblers and disparity inversion will
+                                                         be disabled.  In addition, no framing layer control words will
+                                                         be transmitted (ie. no SYNC, scrambler state, skip, or
+                                                         diagnostic words will be transmitted).
+
+                                                         NOTE: Software must first write ILK_TXX_CFG0[LANE_ENA]=0 before
+                                                         enabling/disabling this mode. */
+	uint64_t reserved_55_55               : 1;
+	uint64_t lnk_stats_ena                : 1;  /**< Enable link statistics counters */
+	uint64_t mltuse_fc_ena                : 1;  /**< When set, the multi-use field of control words will contain
+                                                         flow control status.  Otherwise, the multi-use field will
+                                                         contain ILK_TXX_CFG1[TX_MLTUSE] */
+	uint64_t cal_ena                      : 1;  /**< Enable Tx calendar, else default calendar used:
+                                                              First control word:
+                                                               Entry 0  = link
+                                                               Entry 1  = backpressue id 0
+                                                               Entry 2  = backpressue id 1
+                                                               ...etc.
+                                                            Second control word:
+                                                               Entry 15 = link
+                                                               Entry 16 = backpressue id 15
+                                                               Entry 17 = backpressue id 16
+                                                               ...etc.
+                                                         This continues until the status for all 64 backpressue ids gets
+                                                         transmitted (ie. 0-68 calendar table entries).  The remaining 3
+                                                         calendar table entries (ie. 69-71) will always transmit XOFF.
+
+                                                         To disable backpressure completely, enable the calendar table
+                                                         and program each calendar table entry to transmit XON */
+	uint64_t mfrm_len                     : 13; /**< The quantity of data sent on each lane including one sync word,
+                                                         scrambler state, diag word, zero or more skip words, and the
+                                                         data  payload.  Must be large than ILK_TXX_CFG1[SKIP_CNT]+9.
+                                                         Supported range:ILK_TXX_CFG1[SKIP_CNT]+9 < MFRM_LEN <= 4096) */
+	uint64_t brst_shrt                    : 7;  /**< Minimum interval between burst control words, as a multiple of
+                                                         8 bytes.  Supported range from 8 bytes to 512 (ie. 0 <
+                                                         BRST_SHRT <= 64) */
+	uint64_t lane_rev                     : 1;  /**< Lane reversal.   When enabled, lane striping is performed from
+                                                         most significant lane enabled to least significant lane
+                                                         enabled.  LANE_ENA must be zero before changing LANE_REV. */
+	uint64_t brst_max                     : 5;  /**< Maximum size of a data burst, as a multiple of 64 byte blocks.
+                                                         Supported range is from 64 bytes to 1024 bytes. (ie. 0 <
+                                                         BRST_MAX <= 16) */
+	uint64_t reserved_25_25               : 1;
+	uint64_t cal_depth                    : 9;  /**< Number of valid entries in the calendar.  CAL_DEPTH[2:0] must
+                                                         be zero.  Supported range from 8 to 288.  If CAL_ENA is 0,
+                                                         this field has no effect and the calendar depth is 72 entries. */
+	uint64_t reserved_8_15                : 8;
+	uint64_t lane_ena                     : 8;  /**< Lane enable mask.  Link is enabled if any lane is enabled.  The
+                                                         same lane should not be enabled in multiple ILK_TXx_CFG0.  Each
+                                                         bit of LANE_ENA maps to a TX lane (TLE) and a QLM lane.  NOTE:
+                                                         LANE_REV has no effect on this mapping.
+
+                                                               LANE_ENA[0] = TLE0 = QLM1 lane 0
+                                                               LANE_ENA[1] = TLE1 = QLM1 lane 1
+                                                               LANE_ENA[2] = TLE2 = QLM1 lane 2
+                                                               LANE_ENA[3] = TLE3 = QLM1 lane 3
+                                                               LANE_ENA[4] = TLE4 = QLM2 lane 0
+                                                               LANE_ENA[5] = TLE5 = QLM2 lane 1
+                                                               LANE_ENA[6] = TLE6 = QLM2 lane 2
+                                                               LANE_ENA[7] = TLE7 = QLM2 lane 3 */
+#else
+	uint64_t lane_ena                     : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t cal_depth                    : 9;
+	uint64_t reserved_25_25               : 1;
+	uint64_t brst_max                     : 5;
+	uint64_t lane_rev                     : 1;
+	uint64_t brst_shrt                    : 7;
+	uint64_t mfrm_len                     : 13;
+	uint64_t cal_ena                      : 1;
+	uint64_t mltuse_fc_ena                : 1;
+	uint64_t lnk_stats_ena                : 1;
+	uint64_t reserved_55_55               : 1;
+	uint64_t ptrn_mode                    : 1;
+	uint64_t reserved_57_60               : 4;
+	uint64_t int_lpbk                     : 1;
+	uint64_t ext_lpbk                     : 1;
+	uint64_t ext_lpbk_fc                  : 1;
+#endif
+	} s;
+	struct cvmx_ilk_txx_cfg0_s            cn68xx;
+	struct cvmx_ilk_txx_cfg0_s            cn68xxp1;
+};
+typedef union cvmx_ilk_txx_cfg0 cvmx_ilk_txx_cfg0_t;
+
+/**
+ * cvmx_ilk_tx#_cfg1
+ */
+union cvmx_ilk_txx_cfg1 {
+	uint64_t u64;
+	struct cvmx_ilk_txx_cfg1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_33_63               : 31;
+	uint64_t pkt_busy                     : 1;  /**< Tx-Link is transmitting data. */
+	uint64_t pipe_crd_dis                 : 1;  /**< Disable pipe credits.   Should be set when PKO is configure to
+                                                         ignore pipe credits. */
+	uint64_t ptp_delay                    : 5;  /**< Timestamp commit delay.  Must not be zero. */
+	uint64_t skip_cnt                     : 4;  /**< Number of skip words to insert after the scrambler state */
+	uint64_t pkt_flush                    : 1;  /**< Packet transmit flush.  While PKT_FLUSH=1, the TxFifo will
+                                                         continuously drain; all data will be dropped.  Software should
+                                                         first write PKT_ENA=0 and wait packet transmission to stop. */
+	uint64_t pkt_ena                      : 1;  /**< Packet transmit enable.  When PKT_ENA=0, the Tx-Link will stop
+                                                         transmitting packets, as per RX_LINK_FC_PKT */
+	uint64_t la_mode                      : 1;  /**< 0 = Interlaken
+                                                         1 = Interlaken Look-Aside */
+	uint64_t tx_link_fc                   : 1;  /**< Link flow control status transmitted by the Tx-Link
+                                                         XON when RX_FIFO_CNT <= RX_FIFO_HWM and lane alignment is done */
+	uint64_t rx_link_fc                   : 1;  /**< Link flow control status received in burst/idle control words.
+                                                         When RX_LINK_FC_IGN=0, XOFF will cause Tx-Link to stop
+                                                         transmitting on all channels. */
+	uint64_t reserved_12_16               : 5;
+	uint64_t tx_link_fc_jam               : 1;  /**< All flow control transmitted in burst/idle control words will
+                                                         be XOFF whenever TX_LINK_FC is XOFF.   Enable this to allow
+                                                         link XOFF to automatically XOFF all channels. */
+	uint64_t rx_link_fc_pkt               : 1;  /**< Link flow control received in burst/idle control words causes
+                                                         Tx-Link to stop transmitting at the end of a packet instead of
+                                                         the end of a burst */
+	uint64_t rx_link_fc_ign               : 1;  /**< Ignore the link flow control status received in burst/idle
+                                                         control words */
+	uint64_t rmatch                       : 1;  /**< Enable rate matching circuitry */
+	uint64_t tx_mltuse                    : 8;  /**< Multiple Use bits used when ILKx_TX_CFG[LA_MODE=0] and
+                                                         ILKx_TX_CFG[MLTUSE_FC_ENA] is zero */
+#else
+	uint64_t tx_mltuse                    : 8;
+	uint64_t rmatch                       : 1;
+	uint64_t rx_link_fc_ign               : 1;
+	uint64_t rx_link_fc_pkt               : 1;
+	uint64_t tx_link_fc_jam               : 1;
+	uint64_t reserved_12_16               : 5;
+	uint64_t rx_link_fc                   : 1;
+	uint64_t tx_link_fc                   : 1;
+	uint64_t la_mode                      : 1;
+	uint64_t pkt_ena                      : 1;
+	uint64_t pkt_flush                    : 1;
+	uint64_t skip_cnt                     : 4;
+	uint64_t ptp_delay                    : 5;
+	uint64_t pipe_crd_dis                 : 1;
+	uint64_t pkt_busy                     : 1;
+	uint64_t reserved_33_63               : 31;
+#endif
+	} s;
+	struct cvmx_ilk_txx_cfg1_s            cn68xx;
+	struct cvmx_ilk_txx_cfg1_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t pipe_crd_dis                 : 1;  /**< Disable pipe credits.   Should be set when PKO is configure to
+                                                         ignore pipe credits. */
+	uint64_t ptp_delay                    : 5;  /**< Timestamp commit delay.  Must not be zero. */
+	uint64_t skip_cnt                     : 4;  /**< Number of skip words to insert after the scrambler state */
+	uint64_t pkt_flush                    : 1;  /**< Packet transmit flush.  While PKT_FLUSH=1, the TxFifo will
+                                                         continuously drain; all data will be dropped.  Software should
+                                                         first write PKT_ENA=0 and wait packet transmission to stop. */
+	uint64_t pkt_ena                      : 1;  /**< Packet transmit enable.  When PKT_ENA=0, the Tx-Link will stop
+                                                         transmitting packets, as per RX_LINK_FC_PKT */
+	uint64_t la_mode                      : 1;  /**< 0 = Interlaken
+                                                         1 = Interlaken Look-Aside */
+	uint64_t tx_link_fc                   : 1;  /**< Link flow control status transmitted by the Tx-Link
+                                                         XON when RX_FIFO_CNT <= RX_FIFO_HWM and lane alignment is done */
+	uint64_t rx_link_fc                   : 1;  /**< Link flow control status received in burst/idle control words.
+                                                         When RX_LINK_FC_IGN=0, XOFF will cause Tx-Link to stop
+                                                         transmitting on all channels. */
+	uint64_t reserved_12_16               : 5;
+	uint64_t tx_link_fc_jam               : 1;  /**< All flow control transmitted in burst/idle control words will
+                                                         be XOFF whenever TX_LINK_FC is XOFF.   Enable this to allow
+                                                         link XOFF to automatically XOFF all channels. */
+	uint64_t rx_link_fc_pkt               : 1;  /**< Link flow control received in burst/idle control words causes
+                                                         Tx-Link to stop transmitting at the end of a packet instead of
+                                                         the end of a burst */
+	uint64_t rx_link_fc_ign               : 1;  /**< Ignore the link flow control status received in burst/idle
+                                                         control words */
+	uint64_t rmatch                       : 1;  /**< Enable rate matching circuitry */
+	uint64_t tx_mltuse                    : 8;  /**< Multiple Use bits used when ILKx_TX_CFG[LA_MODE=0] and
+                                                         ILKx_TX_CFG[MLTUSE_FC_ENA] is zero */
+#else
+	uint64_t tx_mltuse                    : 8;
+	uint64_t rmatch                       : 1;
+	uint64_t rx_link_fc_ign               : 1;
+	uint64_t rx_link_fc_pkt               : 1;
+	uint64_t tx_link_fc_jam               : 1;
+	uint64_t reserved_12_16               : 5;
+	uint64_t rx_link_fc                   : 1;
+	uint64_t tx_link_fc                   : 1;
+	uint64_t la_mode                      : 1;
+	uint64_t pkt_ena                      : 1;
+	uint64_t pkt_flush                    : 1;
+	uint64_t skip_cnt                     : 4;
+	uint64_t ptp_delay                    : 5;
+	uint64_t pipe_crd_dis                 : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ilk_txx_cfg1 cvmx_ilk_txx_cfg1_t;
+
+/**
+ * cvmx_ilk_tx#_dbg
+ */
+union cvmx_ilk_txx_dbg {
+	uint64_t u64;
+	struct cvmx_ilk_txx_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_3_63                : 61;
+	uint64_t tx_bad_crc24                 : 1;  /**< Send a control word with bad CRC24.  Hardware will clear this
+                                                         field once the injection is performed. */
+	uint64_t tx_bad_ctlw2                 : 1;  /**< Send a control word without the control bit set */
+	uint64_t tx_bad_ctlw1                 : 1;  /**< Send a data word with the control bit set */
+#else
+	uint64_t tx_bad_ctlw1                 : 1;
+	uint64_t tx_bad_ctlw2                 : 1;
+	uint64_t tx_bad_crc24                 : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_ilk_txx_dbg_s             cn68xx;
+	struct cvmx_ilk_txx_dbg_s             cn68xxp1;
+};
+typedef union cvmx_ilk_txx_dbg cvmx_ilk_txx_dbg_t;
+
+/**
+ * cvmx_ilk_tx#_flow_ctl0
+ */
+union cvmx_ilk_txx_flow_ctl0 {
+	uint64_t u64;
+	struct cvmx_ilk_txx_flow_ctl0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t status                       : 64; /**< IPD flow control status for backpressue id 63-0, where a 0
+                                                         indicates the presence of backpressure (ie. XOFF) and 1
+                                                         indicates the absence of backpressure (ie. XON) */
+#else
+	uint64_t status                       : 64;
+#endif
+	} s;
+	struct cvmx_ilk_txx_flow_ctl0_s       cn68xx;
+	struct cvmx_ilk_txx_flow_ctl0_s       cn68xxp1;
+};
+typedef union cvmx_ilk_txx_flow_ctl0 cvmx_ilk_txx_flow_ctl0_t;
+
+/**
+ * cvmx_ilk_tx#_flow_ctl1
+ *
+ * Notes:
+ * Do not publish.
+ *
+ */
+union cvmx_ilk_txx_flow_ctl1 {
+	uint64_t u64;
+	struct cvmx_ilk_txx_flow_ctl1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} s;
+	struct cvmx_ilk_txx_flow_ctl1_s       cn68xx;
+	struct cvmx_ilk_txx_flow_ctl1_s       cn68xxp1;
+};
+typedef union cvmx_ilk_txx_flow_ctl1 cvmx_ilk_txx_flow_ctl1_t;
+
+/**
+ * cvmx_ilk_tx#_idx_cal
+ */
+union cvmx_ilk_txx_idx_cal {
+	uint64_t u64;
+	struct cvmx_ilk_txx_idx_cal_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_14_63               : 50;
+	uint64_t inc                          : 6;  /**< Increment to add to current index for next index. NOTE:
+                                                         Increment only performed after *MEM_CAL1 access (ie. not
+                                                         *MEM_CAL0) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t index                        : 6;  /**< Specify the group of 8 entries accessed by the next CSR
+                                                         read/write to calendar table memory.  Software must ensure IDX
+                                                         is <36 whenever writing to *MEM_CAL1 */
+#else
+	uint64_t index                        : 6;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t inc                          : 6;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_ilk_txx_idx_cal_s         cn68xx;
+	struct cvmx_ilk_txx_idx_cal_s         cn68xxp1;
+};
+typedef union cvmx_ilk_txx_idx_cal cvmx_ilk_txx_idx_cal_t;
+
+/**
+ * cvmx_ilk_tx#_idx_pmap
+ */
+union cvmx_ilk_txx_idx_pmap {
+	uint64_t u64;
+	struct cvmx_ilk_txx_idx_pmap_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_23_63               : 41;
+	uint64_t inc                          : 7;  /**< Increment to add to current index for next index. */
+	uint64_t reserved_7_15                : 9;
+	uint64_t index                        : 7;  /**< Specify the port-pipe accessed by the next CSR read/write to
+                                                         ILK_TXx_MEM_PMAP.   Note that IDX=n is always port-pipe n,
+                                                         regardless of ILK_TXx_PIPE[BASE] */
+#else
+	uint64_t index                        : 7;
+	uint64_t reserved_7_15                : 9;
+	uint64_t inc                          : 7;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} s;
+	struct cvmx_ilk_txx_idx_pmap_s        cn68xx;
+	struct cvmx_ilk_txx_idx_pmap_s        cn68xxp1;
+};
+typedef union cvmx_ilk_txx_idx_pmap cvmx_ilk_txx_idx_pmap_t;
+
+/**
+ * cvmx_ilk_tx#_idx_stat0
+ */
+union cvmx_ilk_txx_idx_stat0 {
+	uint64_t u64;
+	struct cvmx_ilk_txx_idx_stat0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t clr                          : 1;  /**< CSR read to ILK_TXx_MEM_STAT0 clears the selected counter after
+                                                         returning its current value. */
+	uint64_t reserved_24_30               : 7;
+	uint64_t inc                          : 8;  /**< Increment to add to current index for next index */
+	uint64_t reserved_8_15                : 8;
+	uint64_t index                        : 8;  /**< Specify the channel accessed during the next CSR read to the
+                                                         ILK_TXx_MEM_STAT0 */
+#else
+	uint64_t index                        : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t inc                          : 8;
+	uint64_t reserved_24_30               : 7;
+	uint64_t clr                          : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ilk_txx_idx_stat0_s       cn68xx;
+	struct cvmx_ilk_txx_idx_stat0_s       cn68xxp1;
+};
+typedef union cvmx_ilk_txx_idx_stat0 cvmx_ilk_txx_idx_stat0_t;
+
+/**
+ * cvmx_ilk_tx#_idx_stat1
+ */
+union cvmx_ilk_txx_idx_stat1 {
+	uint64_t u64;
+	struct cvmx_ilk_txx_idx_stat1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t clr                          : 1;  /**< CSR read to ILK_TXx_MEM_STAT1 clears the selected counter after
+                                                         returning its current value. */
+	uint64_t reserved_24_30               : 7;
+	uint64_t inc                          : 8;  /**< Increment to add to current index for next index */
+	uint64_t reserved_8_15                : 8;
+	uint64_t index                        : 8;  /**< Specify the channel accessed during the next CSR read to the
+                                                         ILK_TXx_MEM_STAT1 */
+#else
+	uint64_t index                        : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t inc                          : 8;
+	uint64_t reserved_24_30               : 7;
+	uint64_t clr                          : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ilk_txx_idx_stat1_s       cn68xx;
+	struct cvmx_ilk_txx_idx_stat1_s       cn68xxp1;
+};
+typedef union cvmx_ilk_txx_idx_stat1 cvmx_ilk_txx_idx_stat1_t;
+
+/**
+ * cvmx_ilk_tx#_int
+ */
+union cvmx_ilk_txx_int {
+	uint64_t u64;
+	struct cvmx_ilk_txx_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t stat_cnt_ovfl                : 1;  /**< Statistics counter overflow */
+	uint64_t bad_pipe                     : 1;  /**< Received a PKO port-pipe out of the range specified by
+                                                         ILK_TXX_PIPE */
+	uint64_t bad_seq                      : 1;  /**< Received sequence is not SOP followed by 0 or more data cycles
+                                                         followed by EOP.  PKO config assigned multiple engines to the
+                                                         same ILK Tx Link. */
+	uint64_t txf_err                      : 1;  /**< TX fifo parity error occurred.  At EOP time, EOP_Format will
+                                                         reflect the error. */
+#else
+	uint64_t txf_err                      : 1;
+	uint64_t bad_seq                      : 1;
+	uint64_t bad_pipe                     : 1;
+	uint64_t stat_cnt_ovfl                : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ilk_txx_int_s             cn68xx;
+	struct cvmx_ilk_txx_int_s             cn68xxp1;
+};
+typedef union cvmx_ilk_txx_int cvmx_ilk_txx_int_t;
+
+/**
+ * cvmx_ilk_tx#_int_en
+ */
+union cvmx_ilk_txx_int_en {
+	uint64_t u64;
+	struct cvmx_ilk_txx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t stat_cnt_ovfl                : 1;  /**< Statistics counter overflow */
+	uint64_t bad_pipe                     : 1;  /**< Received a PKO port-pipe out of the range specified by
+                                                         ILK_TXX_PIPE. */
+	uint64_t bad_seq                      : 1;  /**< Received sequence is not SOP followed by 0 or more data cycles
+                                                         followed by EOP.  PKO config assigned multiple engines to the
+                                                         same ILK Tx Link. */
+	uint64_t txf_err                      : 1;  /**< TX fifo parity error occurred.  At EOP time, EOP_Format will
+                                                         reflect the error. */
+#else
+	uint64_t txf_err                      : 1;
+	uint64_t bad_seq                      : 1;
+	uint64_t bad_pipe                     : 1;
+	uint64_t stat_cnt_ovfl                : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ilk_txx_int_en_s          cn68xx;
+	struct cvmx_ilk_txx_int_en_s          cn68xxp1;
+};
+typedef union cvmx_ilk_txx_int_en cvmx_ilk_txx_int_en_t;
+
+/**
+ * cvmx_ilk_tx#_mem_cal0
+ *
+ * Notes:
+ * Software must always read ILK_TXx_MEM_CAL0 then ILK_TXx_MEM_CAL1.  Software
+ * must never read them in reverse order or read one without reading the
+ * other.
+ *
+ * Software must always write ILK_TXx_MEM_CAL0 then ILK_TXx_MEM_CAL1.
+ * Software must never write them in reverse order or write one without
+ * writing the other.
+ */
+union cvmx_ilk_txx_mem_cal0 {
+	uint64_t u64;
+	struct cvmx_ilk_txx_mem_cal0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_36_63               : 28;
+	uint64_t entry_ctl3                   : 2;  /**< Select source of XON/XOFF for entry (IDX*8)+3
+                                                         - 0: IPD backpressue id
+                                                         - 1: Link
+                                                         - 2: XOFF
+                                                         - 3: XON */
+	uint64_t reserved_33_33               : 1;
+	uint64_t bpid3                        : 6;  /**< Select IPD backpressue id for calendar table entry (IDX*8)+3
+                                                         (unused if ENTRY_CTL3 != 0) */
+	uint64_t entry_ctl2                   : 2;  /**< Select source of XON/XOFF for entry (IDX*8)+2
+                                                         - 0: IPD backpressue id
+                                                         - 1: Link
+                                                         - 2: XOFF
+                                                         - 3: XON */
+	uint64_t reserved_24_24               : 1;
+	uint64_t bpid2                        : 6;  /**< Select IPD backpressue id for calendar table entry (IDX*8)+2
+                                                         (unused if ENTRY_CTL2 != 0) */
+	uint64_t entry_ctl1                   : 2;  /**< Select source of XON/XOFF for entry (IDX*8)+1
+                                                         - 0: IPD backpressue id
+                                                         - 1: Link
+                                                         - 2: XOFF
+                                                         - 3: XON */
+	uint64_t reserved_15_15               : 1;
+	uint64_t bpid1                        : 6;  /**< Select IPD backpressue id for calendar table entry (IDX*8)+1
+                                                         (unused if ENTRY_CTL1 != 0) */
+	uint64_t entry_ctl0                   : 2;  /**< Select source of XON/XOFF for entry (IDX*8)+0
+                                                         - 0: IPD backpressue id
+                                                         - 1: Link
+                                                         - 2: XOFF
+                                                         - 3: XON */
+	uint64_t reserved_6_6                 : 1;
+	uint64_t bpid0                        : 6;  /**< Select IPD backpressue id for calendar table entry (IDX*8)+0
+                                                         (unused if ENTRY_CTL0 != 0) */
+#else
+	uint64_t bpid0                        : 6;
+	uint64_t reserved_6_6                 : 1;
+	uint64_t entry_ctl0                   : 2;
+	uint64_t bpid1                        : 6;
+	uint64_t reserved_15_15               : 1;
+	uint64_t entry_ctl1                   : 2;
+	uint64_t bpid2                        : 6;
+	uint64_t reserved_24_24               : 1;
+	uint64_t entry_ctl2                   : 2;
+	uint64_t bpid3                        : 6;
+	uint64_t reserved_33_33               : 1;
+	uint64_t entry_ctl3                   : 2;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_ilk_txx_mem_cal0_s        cn68xx;
+	struct cvmx_ilk_txx_mem_cal0_s        cn68xxp1;
+};
+typedef union cvmx_ilk_txx_mem_cal0 cvmx_ilk_txx_mem_cal0_t;
+
+/**
+ * cvmx_ilk_tx#_mem_cal1
+ *
+ * Notes:
+ * Software must always read ILK_TXx_MEM_CAL0 then ILK_TXx_MEM_CAL1.  Software
+ * must never read them in reverse order or read one without reading the
+ * other.
+ *
+ * Software must always write ILK_TXx_MEM_CAL0 then ILK_TXx_MEM_CAL1.
+ * Software must never write them in reverse order or write one without
+ * writing the other.
+ */
+union cvmx_ilk_txx_mem_cal1 {
+	uint64_t u64;
+	struct cvmx_ilk_txx_mem_cal1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_36_63               : 28;
+	uint64_t entry_ctl7                   : 2;  /**< Select source of XON/XOFF for entry (IDX*8)+7
+                                                         - 0: IPD backpressue id
+                                                         - 1: Link
+                                                         - 2: XOFF
+                                                         - 3: XON */
+	uint64_t reserved_33_33               : 1;
+	uint64_t bpid7                        : 6;  /**< Select IPD backpressue id for calendar table entry (IDX*8)+7
+                                                         (unused if ENTRY_CTL7 != 0) */
+	uint64_t entry_ctl6                   : 2;  /**< Select source of XON/XOFF for entry (IDX*8)+6
+                                                         - 0: IPD backpressue id
+                                                         - 1: Link
+                                                         - 2: XOFF
+                                                         - 3: XON */
+	uint64_t reserved_24_24               : 1;
+	uint64_t bpid6                        : 6;  /**< Select IPD backpressue id for calendar table entry (IDX*8)+6
+                                                         (unused if ENTRY_CTL6 != 0) */
+	uint64_t entry_ctl5                   : 2;  /**< Select source of XON/XOFF for entry (IDX*8)+5
+                                                         - 0: IPD backpressue id
+                                                         - 1: Link
+                                                         - 2: XOFF
+                                                         - 3: XON */
+	uint64_t reserved_15_15               : 1;
+	uint64_t bpid5                        : 6;  /**< Select IPD backpressue id for calendar table entry (IDX*8)+5
+                                                         (unused if ENTRY_CTL5 != 0) */
+	uint64_t entry_ctl4                   : 2;  /**< Select source of XON/XOFF for entry (IDX*8)+4
+                                                         - 0: IPD backpressue id
+                                                         - 1: Link
+                                                         - 2: XOFF
+                                                         - 3: XON */
+	uint64_t reserved_6_6                 : 1;
+	uint64_t bpid4                        : 6;  /**< Select IPD backpressue id for calendar table entry (IDX*8)+4
+                                                         (unused if ENTRY_CTL4 != 0) */
+#else
+	uint64_t bpid4                        : 6;
+	uint64_t reserved_6_6                 : 1;
+	uint64_t entry_ctl4                   : 2;
+	uint64_t bpid5                        : 6;
+	uint64_t reserved_15_15               : 1;
+	uint64_t entry_ctl5                   : 2;
+	uint64_t bpid6                        : 6;
+	uint64_t reserved_24_24               : 1;
+	uint64_t entry_ctl6                   : 2;
+	uint64_t bpid7                        : 6;
+	uint64_t reserved_33_33               : 1;
+	uint64_t entry_ctl7                   : 2;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_ilk_txx_mem_cal1_s        cn68xx;
+	struct cvmx_ilk_txx_mem_cal1_s        cn68xxp1;
+};
+typedef union cvmx_ilk_txx_mem_cal1 cvmx_ilk_txx_mem_cal1_t;
+
+/**
+ * cvmx_ilk_tx#_mem_pmap
+ */
+union cvmx_ilk_txx_mem_pmap {
+	uint64_t u64;
+	struct cvmx_ilk_txx_mem_pmap_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_17_63               : 47;
+	uint64_t remap                        : 1;  /**< Dynamically select channel using bits[39:32] of an 8-byte
+                                                         header prepended to any packet transmitted on the port-pipe
+                                                         selected by ILK_TXx_IDX_PMAP[IDX].
+
+                                                         ***NOTE: Added in pass 2.0 */
+	uint64_t reserved_8_15                : 8;
+	uint64_t channel                      : 8;  /**< Specify the channel for the port-pipe selected by
+                                                         ILK_TXx_IDX_PMAP[IDX] */
+#else
+	uint64_t channel                      : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t remap                        : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_ilk_txx_mem_pmap_s        cn68xx;
+	struct cvmx_ilk_txx_mem_pmap_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_8_63                : 56;
+	uint64_t channel                      : 8;  /**< Specify the channel for the port-pipe selected by
+                                                         ILK_TXx_IDX_PMAP[IDX] */
+#else
+	uint64_t channel                      : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_ilk_txx_mem_pmap cvmx_ilk_txx_mem_pmap_t;
+
+/**
+ * cvmx_ilk_tx#_mem_stat0
+ */
+union cvmx_ilk_txx_mem_stat0 {
+	uint64_t u64;
+	struct cvmx_ilk_txx_mem_stat0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_28_63               : 36;
+	uint64_t tx_pkt                       : 28; /**< Number of packets transmitted per channel (256M)
+                                                         Channel selected by ILK_TXx_IDX_STAT0[IDX].  Interrupt on
+                                                         saturation if ILK_TXX_INT_EN[STAT_CNT_OVFL]=1. */
+#else
+	uint64_t tx_pkt                       : 28;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} s;
+	struct cvmx_ilk_txx_mem_stat0_s       cn68xx;
+	struct cvmx_ilk_txx_mem_stat0_s       cn68xxp1;
+};
+typedef union cvmx_ilk_txx_mem_stat0 cvmx_ilk_txx_mem_stat0_t;
+
+/**
+ * cvmx_ilk_tx#_mem_stat1
+ */
+union cvmx_ilk_txx_mem_stat1 {
+	uint64_t u64;
+	struct cvmx_ilk_txx_mem_stat1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_36_63               : 28;
+	uint64_t tx_bytes                     : 36; /**< Number of bytes transmitted per channel (64GB) Channel selected
+                                                         by ILK_TXx_IDX_STAT1[IDX].    Saturates.  Interrupt on
+                                                         saturation if ILK_TXX_INT_EN[STAT_CNT_OVFL]=1. */
+#else
+	uint64_t tx_bytes                     : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_ilk_txx_mem_stat1_s       cn68xx;
+	struct cvmx_ilk_txx_mem_stat1_s       cn68xxp1;
+};
+typedef union cvmx_ilk_txx_mem_stat1 cvmx_ilk_txx_mem_stat1_t;
+
+/**
+ * cvmx_ilk_tx#_pipe
+ */
+union cvmx_ilk_txx_pipe {
+	uint64_t u64;
+	struct cvmx_ilk_txx_pipe_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_24_63               : 40;
+	uint64_t nump                         : 8;  /**< Number of pipes assigned to this Tx Link */
+	uint64_t reserved_7_15                : 9;
+	uint64_t base                         : 7;  /**< When NUMP is non-zero, indicates the base pipe number this
+                                                         Tx link will accept.  This Tx will accept PKO packets from
+                                                         pipes in the range of:  BASE .. (BASE+(NUMP-1))
+
+                                                           BASE and NUMP must be constrained such that
+                                                           1) BASE+(NUMP-1) < 127
+                                                           2) Each used PKO pipe must map to exactly
+                                                              one port|channel
+                                                           3) The pipe ranges must be consistent with
+                                                              the PKO configuration. */
+#else
+	uint64_t base                         : 7;
+	uint64_t reserved_7_15                : 9;
+	uint64_t nump                         : 8;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_ilk_txx_pipe_s            cn68xx;
+	struct cvmx_ilk_txx_pipe_s            cn68xxp1;
+};
+typedef union cvmx_ilk_txx_pipe cvmx_ilk_txx_pipe_t;
+
+/**
+ * cvmx_ilk_tx#_rmatch
+ */
+union cvmx_ilk_txx_rmatch {
+	uint64_t u64;
+	struct cvmx_ilk_txx_rmatch_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_50_63               : 14;
+	uint64_t grnlrty                      : 2;  /**< Granularity of a token, where 1 token equal (1<<GRNLRTY) bytes. */
+	uint64_t brst_limit                   : 16; /**< Size of token bucket, also the maximum quantity of data that
+                                                         may be burst across the interface before invoking rate limiting
+                                                         logic. */
+	uint64_t time_limit                   : 16; /**< Number of cycles per time interval. (Must be >= 4) */
+	uint64_t rate_limit                   : 16; /**< Number of tokens added to the bucket when the interval timer
+                                                         expires. */
+#else
+	uint64_t rate_limit                   : 16;
+	uint64_t time_limit                   : 16;
+	uint64_t brst_limit                   : 16;
+	uint64_t grnlrty                      : 2;
+	uint64_t reserved_50_63               : 14;
+#endif
+	} s;
+	struct cvmx_ilk_txx_rmatch_s          cn68xx;
+	struct cvmx_ilk_txx_rmatch_s          cn68xxp1;
+};
+typedef union cvmx_ilk_txx_rmatch cvmx_ilk_txx_rmatch_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-ilk.c b/sys/contrib/octeon-sdk/cvmx-ilk.c
new file mode 100644
index 0000000..8042059
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-ilk.c
@@ -0,0 +1,1400 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Support library for the ILK
+ *
+ * <hr>$Revision: 49448 $<hr>
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-sysinfo.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-ilk.h>
+#include <asm/octeon/cvmx-ilk-defs.h>
+#include <asm/octeon/cvmx-helper-util.h>
+#include <asm/octeon/cvmx-helper-ilk.h>
+#else
+#include "cvmx.h"
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "cvmx-config.h"
+#endif
+#include "cvmx-sysinfo.h"
+#include "cvmx-pko.h"
+#include "cvmx-ilk.h"
+#include "cvmx-helper-util.h"
+#include "cvmx-helper-ilk.h"
+#endif
+
+#ifdef CVMX_ENABLE_HELPER_FUNCTIONS
+
+/*
+ * global configurations. to disable the 2nd ILK, set
+ * cvmx_ilk_lane_mask[CVMX_NUM_ILK_INTF] = {0xff, 0x0} and
+ * cvmx_ilk_chans[CVMX_NUM_ILK_INTF] = {8, 0}
+ */
+unsigned char cvmx_ilk_lane_mask[CVMX_NUM_ILK_INTF] = {0xf, 0xf0};
+//#define SINGLE_PORT_SIM_ILK
+#ifdef SINGLE_PORT_SIM_ILK
+unsigned char cvmx_ilk_chans[CVMX_NUM_ILK_INTF] = {1, 1};
+unsigned char cvmx_ilk_chan_map[CVMX_NUM_ILK_INTF][CVMX_MAX_ILK_CHANS] =
+{{0},
+ {0}};
+#else /* sample case */
+unsigned char cvmx_ilk_chans[CVMX_NUM_ILK_INTF] = {8, 8};
+unsigned char cvmx_ilk_chan_map[CVMX_NUM_ILK_INTF][CVMX_MAX_ILK_CHANS] =
+{{0, 1, 2, 3, 4, 5, 6, 7},
+ {0, 1, 2, 3, 4, 5, 6, 7}};
+#endif
+
+/* Default callbacks, can be overridden
+ *  using cvmx_ilk_get_callbacks/cvmx_ilk_set_callbacks
+ */
+static cvmx_ilk_callbacks_t cvmx_ilk_callbacks = {
+  .calendar_setup_rx   = cvmx_ilk_cal_setup_rx,
+};
+
+static cvmx_ilk_intf_t cvmx_ilk_intf_cfg[CVMX_NUM_ILK_INTF];
+
+/**
+ * Get current ILK initialization callbacks
+ *
+ * @param callbacks  Pointer to the callbacks structure.to fill
+ *
+ * @return Pointer to cvmx_ilk_callbacks_t structure.
+ */
+void cvmx_ilk_get_callbacks(cvmx_ilk_callbacks_t * callbacks)
+{
+    memcpy(callbacks, &cvmx_ilk_callbacks, sizeof(cvmx_ilk_callbacks));
+}
+
+/**
+ * Set new ILK initialization callbacks
+ *
+ * @param new_callbacks  Pointer to an updated callbacks structure.
+ */
+void cvmx_ilk_set_callbacks(cvmx_ilk_callbacks_t * new_callbacks)
+{
+    memcpy(&cvmx_ilk_callbacks, new_callbacks, sizeof(cvmx_ilk_callbacks));
+}
+
+/**
+ * Initialize and start the ILK interface.
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a ILK interface. cn68xx has 2 interfaces: ilk0 and
+ *                  ilk1.
+ *
+ * @param lane_mask the lane group for this interface
+ *
+ * @return Zero on success, negative of failure.
+ */
+int cvmx_ilk_start_interface (int interface, unsigned char lane_mask)
+{
+    int res = -1;
+    int other_intf, this_qlm, other_qlm;
+    unsigned char uni_mask;
+    cvmx_mio_qlmx_cfg_t mio_qlmx_cfg, other_mio_qlmx_cfg;
+    cvmx_ilk_txx_cfg0_t ilk_txx_cfg0;
+    cvmx_ilk_rxx_cfg0_t ilk_rxx_cfg0;
+    cvmx_ilk_ser_cfg_t ilk_ser_cfg;
+
+    if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+        return res;
+
+    if (interface >= CVMX_NUM_ILK_INTF)
+        return res;
+
+    if (lane_mask == 0)
+        return res;
+
+    /* check conflicts between 2 ilk interfaces. 1 lane can be assigned to 1
+     * interface only */
+    other_intf = !interface;
+    this_qlm = interface + CVMX_ILK_QLM_BASE;
+    other_qlm = other_intf + CVMX_ILK_QLM_BASE;
+    if (cvmx_ilk_intf_cfg[other_intf].lane_en_mask & lane_mask)
+    {
+        cvmx_dprintf ("ILK%d: %s: lane assignment conflict\n", interface,
+                      __FUNCTION__);
+        return res;
+    }
+
+    /* check the legality of the lane mask. interface 0 can have 8 lanes,
+     * while interface 1 can have 4 lanes at most */
+    uni_mask = lane_mask >> (interface * 4);
+    if ((uni_mask != 0x1 && uni_mask != 0x3 && uni_mask != 0xf &&
+         uni_mask != 0xff) || (interface == 1 && lane_mask > 0xf0))
+    {
+#if CVMX_ENABLE_DEBUG_PRINTS
+        cvmx_dprintf ("ILK%d: %s: incorrect lane mask: 0x%x \n", interface,
+                      __FUNCTION__, uni_mask);
+#endif
+        return res;
+    }
+
+    /* check the availability of qlms. qlm_cfg = 001 means the chip is fused
+     * to give this qlm to ilk */
+    mio_qlmx_cfg.u64 = cvmx_read_csr (CVMX_MIO_QLMX_CFG(this_qlm));
+    other_mio_qlmx_cfg.u64 = cvmx_read_csr (CVMX_MIO_QLMX_CFG(other_qlm));
+    if (mio_qlmx_cfg.s.qlm_cfg != 1 ||
+        (uni_mask == 0xff && other_mio_qlmx_cfg.s.qlm_cfg != 1))
+    {
+#if CVMX_ENABLE_DEBUG_PRINTS
+        cvmx_dprintf ("ILK%d: %s: qlm unavailable\n", interface, __FUNCTION__);
+#endif
+        return res;
+    }
+
+    /* power up the serdes */
+    ilk_ser_cfg.u64 = cvmx_read_csr (CVMX_ILK_SER_CFG);
+    if (ilk_ser_cfg.s.ser_pwrup == 0)
+    {
+        ilk_ser_cfg.s.ser_rxpol_auto = 1;
+        ilk_ser_cfg.s.ser_rxpol = 0;
+        ilk_ser_cfg.s.ser_txpol = 0;
+        ilk_ser_cfg.s.ser_reset_n = 0xff;
+        ilk_ser_cfg.s.ser_haul = 0;
+    }
+    ilk_ser_cfg.s.ser_pwrup |= ((interface ==0) && (lane_mask > 0xf)) ?
+                               0x3 : (1 << interface);
+    cvmx_write_csr (CVMX_ILK_SER_CFG, ilk_ser_cfg.u64);
+
+    /* configure the lane enable of the interface */
+    ilk_txx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_TXX_CFG0(interface));
+    ilk_rxx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_RXX_CFG0(interface));
+    ilk_txx_cfg0.s.lane_ena = ilk_rxx_cfg0.s.lane_ena = lane_mask;
+    cvmx_write_csr (CVMX_ILK_TXX_CFG0(interface), ilk_txx_cfg0.u64);
+    cvmx_write_csr (CVMX_ILK_RXX_CFG0(interface), ilk_rxx_cfg0.u64);
+
+    /* write to local cache. for lane speed, if interface 0 has 8 lanes,
+     * assume both qlms have the same speed */
+    cvmx_ilk_intf_cfg[interface].intf_en = 1;
+    cvmx_ilk_intf_cfg[interface].lane_en_mask = lane_mask;
+    res = 0;
+
+    return res;
+}
+
+/**
+ * set pipe group base and length for the interface
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a ILK interface. cn68xx has 2 interfaces: ilk0 and
+ *                  ilk1.
+ *
+ * @param pipe_base the base of the pipe group
+ * @param pipe_len  the length of the pipe group
+ * 
+ * @return Zero on success, negative of failure.
+ */
+int cvmx_ilk_set_pipe (int interface, int pipe_base, unsigned int pipe_len) 
+{
+    int res = -1;
+    cvmx_ilk_txx_pipe_t ilk_txx_pipe;
+
+    if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+        return res;
+
+    if (interface >= CVMX_NUM_ILK_INTF)
+        return res;
+
+    /* base should be between 0 and 127. base + length should be <127 */
+    if (!(pipe_base >= 0 && pipe_base <= 127) || (pipe_base + pipe_len > 127))
+    {
+#if CVMX_ENABLE_DEBUG_PRINTS
+        cvmx_dprintf ("ILK%d: %s: pipe base/length out of bounds\n", interface,
+                      __FUNCTION__);
+#endif
+        return res;
+    }
+
+    /* set them in ilk tx section */
+    ilk_txx_pipe.u64 = cvmx_read_csr (CVMX_ILK_TXX_PIPE(interface));
+    ilk_txx_pipe.s.base = pipe_base;
+    ilk_txx_pipe.s.nump = pipe_len;
+    cvmx_write_csr (CVMX_ILK_TXX_PIPE(interface), ilk_txx_pipe.u64);
+    res = 0;
+
+    return res;
+}
+
+/**
+ * set logical channels for tx
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a ILK interface. cn68xx has 2 interfaces: ilk0 and
+ *                  ilk1.
+ *
+ * @param pch     pointer to an array of pipe-channel pair
+ * @param num_chs the number of entries in the pipe-channel array
+ *
+ * @return Zero on success, negative of failure.
+ */
+int cvmx_ilk_tx_set_channel (int interface, cvmx_ilk_pipe_chan_t *pch,
+                             unsigned int num_chs)
+{
+    int res = -1;
+    cvmx_ilk_txx_idx_pmap_t ilk_txx_idx_pmap;
+    unsigned int i;
+
+    if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+        return res;
+
+    if (interface >= CVMX_NUM_ILK_INTF)
+        return res;
+
+    if (pch == NULL || num_chs > CVMX_MAX_ILK_PIPES)
+        return res;
+
+    /* write the pair to ilk tx */
+    for (i = 0; i < num_chs; i++)
+    {
+        ilk_txx_idx_pmap.u64 = 0;
+        ilk_txx_idx_pmap.s.index = pch->pipe;
+        cvmx_write_csr(CVMX_ILK_TXX_IDX_PMAP(interface), ilk_txx_idx_pmap.u64);
+        cvmx_write_csr(CVMX_ILK_TXX_MEM_PMAP(interface), pch->chan);
+        pch++;
+    }
+    res = 0;
+
+    return res;
+}
+
+/**
+ * set pkind for rx
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a ILK interface. cn68xx has 2 interfaces: ilk0 and
+ *                  ilk1.
+ *
+ * @param chpknd    pointer to an array of channel-pkind pair
+ * @param num_pknd the number of entries in the channel-pkind array
+ *
+ * @return Zero on success, negative of failure.
+ */
+int cvmx_ilk_rx_set_pknd (int interface, cvmx_ilk_chan_pknd_t *chpknd,
+                          unsigned int num_pknd)
+{
+    int res = -1;
+    cvmx_ilk_rxf_idx_pmap_t ilk_rxf_idx_pmap;
+    unsigned int i;
+
+    if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+        return res;
+
+    if (interface >= CVMX_NUM_ILK_INTF)
+        return res;
+
+    if (chpknd == NULL || num_pknd > CVMX_MAX_ILK_PKNDS)
+        return res;
+
+    /* write the pair to ilk rx. note the channels for different interfaces
+     * are given in *chpknd and interface is not used as a param */
+    for (i = 0; i < num_pknd; i++)
+    {
+        ilk_rxf_idx_pmap.u64 = 0;
+        ilk_rxf_idx_pmap.s.index = interface * 256 + chpknd->chan;
+        cvmx_write_csr (CVMX_ILK_RXF_IDX_PMAP, ilk_rxf_idx_pmap.u64);
+        cvmx_write_csr (CVMX_ILK_RXF_MEM_PMAP, chpknd->pknd);
+        chpknd++;
+    }
+    res = 0;
+
+    return res;
+}
+
+/**
+ * configure calendar for rx
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a ILK interface. cn68xx has 2 interfaces: ilk0 and
+ *                  ilk1.
+ *
+ * @param cal_depth the number of calendar entries
+ * @param pent      pointer to calendar entries
+ *
+ * @return Zero on success, negative of failure.
+ */
+static int cvmx_ilk_rx_cal_conf (int interface, int cal_depth, 
+                          cvmx_ilk_cal_entry_t *pent)
+{
+    int res = -1, num_grp, num_rest, i, j;
+    cvmx_ilk_rxx_cfg0_t ilk_rxx_cfg0;
+    cvmx_ilk_rxx_idx_cal_t ilk_rxx_idx_cal;
+    cvmx_ilk_rxx_mem_cal0_t ilk_rxx_mem_cal0;
+    cvmx_ilk_rxx_mem_cal1_t ilk_rxx_mem_cal1;
+    unsigned long int tmp;
+
+    if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+        return res;
+
+    if (interface >= CVMX_NUM_ILK_INTF)
+        return res;
+
+    if (cal_depth < CVMX_ILK_RX_MIN_CAL || cal_depth > CVMX_ILK_MAX_CAL
+        || pent == NULL)
+        return res;
+
+    /* mandatory link-level fc as workarounds for ILK-15397 and ILK-15479 */
+    /* TODO: test effectiveness */
+#if 0
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_0) && pent->ent_ctrl == PIPE_BPID)
+        for (i = 0; i < cal_depth; i++)
+            pent->ent_ctrl = LINK;
+#endif
+
+    /* set the depth */
+    ilk_rxx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_RXX_CFG0(interface));
+    ilk_rxx_cfg0.s.cal_depth = cal_depth;
+    cvmx_write_csr (CVMX_ILK_RXX_CFG0(interface), ilk_rxx_cfg0.u64); 
+
+    /* set the calendar index */
+    num_grp = cal_depth / CVMX_ILK_CAL_GRP_SZ;
+    num_rest = cal_depth % CVMX_ILK_CAL_GRP_SZ;
+    ilk_rxx_idx_cal.u64 = 0;
+    ilk_rxx_idx_cal.s.inc = 1;
+    cvmx_write_csr (CVMX_ILK_RXX_IDX_CAL(interface), ilk_rxx_idx_cal.u64); 
+
+    /* set the calendar entries. each group has both cal0 and cal1 registers */
+    for (i = 0; i < num_grp; i++)
+    {
+        ilk_rxx_mem_cal0.u64 = 0;
+        for (j = 0; j < CVMX_ILK_CAL_GRP_SZ/2; j++)
+        {
+            tmp = 0;
+            tmp = pent->pipe_bpid & ~(~tmp << CVMX_ILK_PIPE_BPID_SZ);
+            tmp <<= (CVMX_ILK_PIPE_BPID_SZ + CVMX_ILK_ENT_CTRL_SZ) * j;
+            ilk_rxx_mem_cal0.u64 |= tmp;
+
+            tmp = 0;
+            tmp = pent->ent_ctrl & ~(~tmp << CVMX_ILK_ENT_CTRL_SZ);
+            tmp <<= (CVMX_ILK_PIPE_BPID_SZ + CVMX_ILK_ENT_CTRL_SZ) * j +
+                    CVMX_ILK_PIPE_BPID_SZ;
+            ilk_rxx_mem_cal0.u64 |= tmp;
+            pent++;
+        }
+        cvmx_write_csr(CVMX_ILK_RXX_MEM_CAL0(interface), ilk_rxx_mem_cal0.u64);
+
+        ilk_rxx_mem_cal1.u64 = 0;
+        for (j = 0; j < CVMX_ILK_CAL_GRP_SZ/2; j++)
+        {
+            tmp = 0;
+            tmp = pent->pipe_bpid & ~(~tmp << CVMX_ILK_PIPE_BPID_SZ);
+            tmp <<= (CVMX_ILK_PIPE_BPID_SZ + CVMX_ILK_ENT_CTRL_SZ) * j;
+            ilk_rxx_mem_cal1.u64 |= tmp;
+
+            tmp = 0;
+            tmp = pent->ent_ctrl & ~(~tmp << CVMX_ILK_ENT_CTRL_SZ);
+            tmp <<= (CVMX_ILK_PIPE_BPID_SZ + CVMX_ILK_ENT_CTRL_SZ) * j +
+                    CVMX_ILK_PIPE_BPID_SZ;
+            ilk_rxx_mem_cal1.u64 |= tmp;
+            pent++;
+        }
+        cvmx_write_csr(CVMX_ILK_RXX_MEM_CAL1(interface), ilk_rxx_mem_cal1.u64);
+    }
+
+    /* set the calendar entries, the fraction of a group. but both cal0 and
+     * cal1 must be written */
+    ilk_rxx_mem_cal0.u64 = 0;
+    ilk_rxx_mem_cal1.u64 = 0;
+    for (i = 0; i < num_rest; i++)
+    {
+        if (i < CVMX_ILK_CAL_GRP_SZ/2)
+        {
+            tmp = 0;
+            tmp = pent->pipe_bpid & ~(~tmp << CVMX_ILK_PIPE_BPID_SZ);
+            tmp <<= (CVMX_ILK_PIPE_BPID_SZ + CVMX_ILK_ENT_CTRL_SZ) * i;
+            ilk_rxx_mem_cal0.u64 |= tmp;
+
+            tmp = 0;
+            tmp = pent->ent_ctrl & ~(~tmp << CVMX_ILK_ENT_CTRL_SZ);
+            tmp <<= (CVMX_ILK_PIPE_BPID_SZ + CVMX_ILK_ENT_CTRL_SZ) * i +
+                    CVMX_ILK_PIPE_BPID_SZ;
+            ilk_rxx_mem_cal0.u64 |= tmp;
+            pent++;
+        }
+
+        if (i >= CVMX_ILK_CAL_GRP_SZ/2)
+        {
+            tmp = 0;
+            tmp = pent->pipe_bpid & ~(~tmp << CVMX_ILK_PIPE_BPID_SZ);
+            tmp <<= (CVMX_ILK_PIPE_BPID_SZ + CVMX_ILK_ENT_CTRL_SZ) *
+                    (i - CVMX_ILK_CAL_GRP_SZ/2);
+            ilk_rxx_mem_cal1.u64 |= tmp;
+
+            tmp = 0;
+            tmp = pent->ent_ctrl & ~(~tmp << CVMX_ILK_ENT_CTRL_SZ);
+            tmp <<= (CVMX_ILK_PIPE_BPID_SZ + CVMX_ILK_ENT_CTRL_SZ) *
+                    (i - CVMX_ILK_CAL_GRP_SZ/2) + CVMX_ILK_PIPE_BPID_SZ;
+            ilk_rxx_mem_cal1.u64 |= tmp;
+            pent++;
+        }
+    }
+    cvmx_write_csr(CVMX_ILK_RXX_MEM_CAL0(interface), ilk_rxx_mem_cal0.u64);
+    cvmx_write_csr(CVMX_ILK_RXX_MEM_CAL1(interface), ilk_rxx_mem_cal1.u64);
+    cvmx_read_csr (CVMX_ILK_RXX_MEM_CAL1(interface));
+
+    return 0;
+}
+
+/**
+ * set high water mark for rx
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a ILK interface. cn68xx has 2 interfaces: ilk0 and
+ *                  ilk1.
+ *
+ * @param hi_wm     high water mark for this interface
+ *
+ * @return Zero on success, negative of failure.
+ */
+static int cvmx_ilk_rx_set_hwm (int interface, int hi_wm)
+{
+    int res = -1;
+    cvmx_ilk_rxx_cfg1_t ilk_rxx_cfg1;
+
+    if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+        return res;
+
+    if (interface >= CVMX_NUM_ILK_INTF)
+        return res;
+
+    if (hi_wm <= 0)
+        return res;
+
+    /* set the hwm */
+    ilk_rxx_cfg1.u64 = cvmx_read_csr (CVMX_ILK_RXX_CFG1(interface));
+    ilk_rxx_cfg1.s.rx_fifo_hwm = hi_wm;
+    cvmx_write_csr (CVMX_ILK_RXX_CFG1(interface), ilk_rxx_cfg1.u64); 
+    res = 0;
+
+    return res;
+}
+
+/**
+ * enable calendar for rx
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a ILK interface. cn68xx has 2 interfaces: ilk0 and
+ *                  ilk1.
+ *
+ * @param cal_ena   enable or disable calendar
+ *
+ * @return Zero on success, negative of failure.
+ */
+static int cvmx_ilk_rx_cal_ena (int interface, unsigned char cal_ena)
+{
+    int res = -1;
+    cvmx_ilk_rxx_cfg0_t ilk_rxx_cfg0;
+
+    if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+        return res;
+
+    if (interface >= CVMX_NUM_ILK_INTF)
+        return res;
+
+    /* set the enable */
+    ilk_rxx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_RXX_CFG0(interface));
+    ilk_rxx_cfg0.s.cal_ena = cal_ena;
+    cvmx_write_csr (CVMX_ILK_RXX_CFG0(interface), ilk_rxx_cfg0.u64); 
+    cvmx_read_csr (CVMX_ILK_RXX_CFG0(interface));
+    res = 0;
+
+    return res;
+}
+
+/**
+ * set up calendar for rx
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a ILK interface. cn68xx has 2 interfaces: ilk0 and
+ *                  ilk1.
+ *
+ * @param cal_depth the number of calendar entries
+ * @param pent      pointer to calendar entries
+ * @param hi_wm     high water mark for this interface
+ * @param cal_ena   enable or disable calendar
+ *
+ * @return Zero on success, negative of failure.
+ */
+int cvmx_ilk_cal_setup_rx (int interface, int cal_depth,
+                           cvmx_ilk_cal_entry_t *pent, int hi_wm,
+                           unsigned char cal_ena)
+{
+    int res = -1;
+
+    if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+        return res;
+
+    if (interface >= CVMX_NUM_ILK_INTF)
+        return res;
+
+    res = cvmx_ilk_rx_cal_conf (interface, cal_depth, pent);
+    if (res < 0)
+        return res;
+
+    res = cvmx_ilk_rx_set_hwm (interface, hi_wm);
+    if (res < 0)
+        return res;
+
+    res = cvmx_ilk_rx_cal_ena (interface, cal_ena);
+    return res;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_ilk_cal_setup_rx);
+#endif
+
+/**
+ * configure calendar for tx
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a ILK interface. cn68xx has 2 interfaces: ilk0 and
+ *                  ilk1.
+ *
+ * @param cal_depth the number of calendar entries
+ * @param pent      pointer to calendar entries
+ *
+ * @return Zero on success, negative of failure.
+ */
+static int cvmx_ilk_tx_cal_conf (int interface, int cal_depth, 
+                          cvmx_ilk_cal_entry_t *pent)
+{
+    int res = -1, num_grp, num_rest, i, j;
+    cvmx_ilk_txx_cfg0_t ilk_txx_cfg0;
+    cvmx_ilk_txx_idx_cal_t ilk_txx_idx_cal;
+    cvmx_ilk_txx_mem_cal0_t ilk_txx_mem_cal0;
+    cvmx_ilk_txx_mem_cal1_t ilk_txx_mem_cal1;
+    unsigned long int tmp;
+    cvmx_ilk_cal_entry_t *ent_tmp;
+
+    if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+        return res;
+
+    if (interface >= CVMX_NUM_ILK_INTF)
+        return res;
+
+    if (cal_depth < CVMX_ILK_TX_MIN_CAL || cal_depth > CVMX_ILK_MAX_CAL
+        || pent == NULL)
+        return res;
+
+    /* mandatory link-level fc as workarounds for ILK-15397 and ILK-15479 */
+    /* TODO: test effectiveness */
+#if 0
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_0) && pent->ent_ctrl == PIPE_BPID)
+        for (i = 0; i < cal_depth; i++)
+            pent->ent_ctrl = LINK;
+#endif
+
+    /* tx calendar depth must be a multiple of 8 */
+    num_grp = (cal_depth - 1) / CVMX_ILK_CAL_GRP_SZ + 1;
+    num_rest = cal_depth % CVMX_ILK_CAL_GRP_SZ;
+    if (num_rest != 0)
+    {
+        ent_tmp = pent + cal_depth;
+        for (i = num_rest; i < 8; i++, ent_tmp++)
+        {
+            ent_tmp->pipe_bpid = 0;
+            ent_tmp->ent_ctrl = XOFF;
+        }
+    }
+    cal_depth = num_grp * 8;
+
+    /* set the depth */
+    ilk_txx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_TXX_CFG0(interface));
+    ilk_txx_cfg0.s.cal_depth = cal_depth;
+    cvmx_write_csr (CVMX_ILK_TXX_CFG0(interface), ilk_txx_cfg0.u64); 
+
+    /* set the calendar index */
+    ilk_txx_idx_cal.u64 = 0;
+    ilk_txx_idx_cal.s.inc = 1;
+    cvmx_write_csr (CVMX_ILK_TXX_IDX_CAL(interface), ilk_txx_idx_cal.u64); 
+
+    /* set the calendar entries. each group has both cal0 and cal1 registers */
+    for (i = 0; i < num_grp; i++)
+    {
+        ilk_txx_mem_cal0.u64 = 0;
+        for (j = 0; j < CVMX_ILK_CAL_GRP_SZ/2; j++)
+        {
+            tmp = 0;
+            tmp = pent->pipe_bpid & ~(~tmp << CVMX_ILK_PIPE_BPID_SZ);
+            tmp <<= (CVMX_ILK_PIPE_BPID_SZ + CVMX_ILK_ENT_CTRL_SZ) * j;
+            ilk_txx_mem_cal0.u64 |= tmp;
+
+            tmp = 0;
+            tmp = pent->ent_ctrl & ~(~tmp << CVMX_ILK_ENT_CTRL_SZ);
+            tmp <<= (CVMX_ILK_PIPE_BPID_SZ + CVMX_ILK_ENT_CTRL_SZ) * j +
+                    CVMX_ILK_PIPE_BPID_SZ;
+            ilk_txx_mem_cal0.u64 |= tmp;
+            pent++;
+        }
+        cvmx_write_csr(CVMX_ILK_TXX_MEM_CAL0(interface), ilk_txx_mem_cal0.u64);
+
+        ilk_txx_mem_cal1.u64 = 0;
+        for (j = 0; j < CVMX_ILK_CAL_GRP_SZ/2; j++)
+        {
+            tmp = 0;
+            tmp = pent->pipe_bpid & ~(~tmp << CVMX_ILK_PIPE_BPID_SZ);
+            tmp <<= (CVMX_ILK_PIPE_BPID_SZ + CVMX_ILK_ENT_CTRL_SZ) * j;
+            ilk_txx_mem_cal1.u64 |= tmp;
+
+            tmp = 0;
+            tmp = pent->ent_ctrl & ~(~tmp << CVMX_ILK_ENT_CTRL_SZ);
+            tmp <<= (CVMX_ILK_PIPE_BPID_SZ + CVMX_ILK_ENT_CTRL_SZ) * j +
+                    CVMX_ILK_PIPE_BPID_SZ;
+            ilk_txx_mem_cal1.u64 |= tmp;
+            pent++;
+        }
+        cvmx_write_csr(CVMX_ILK_TXX_MEM_CAL1(interface), ilk_txx_mem_cal1.u64);
+    }
+    cvmx_read_csr (CVMX_ILK_TXX_MEM_CAL1(interface));
+
+    return 0;
+}
+
+#ifdef CVMX_ILK_BP_CONF_ENA
+/**
+ * configure backpressure for tx
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a ILK interface. cn68xx has 2 interfaces: ilk0 and
+ *                  ilk1.
+ *
+ * @param cal_depth the number of calendar entries
+ * @param pent      pointer to calendar entries
+ *
+ * @return Zero on success, negative of failure.
+ */
+static int cvmx_ilk_bp_conf (int interface, int cal_depth, cvmx_ilk_cal_entry_t *pent)
+{
+    int res = -1, i;
+    cvmx_ipd_ctl_status_t ipd_ctl_status;
+    cvmx_ilk_cal_entry_t *tmp;
+    unsigned char bpid;
+    cvmx_ipd_bpidx_mbuf_th_t ipd_bpidx_mbuf_th;
+
+    /* enable bp for the interface */
+    ipd_ctl_status.u64 = cvmx_read_csr (CVMX_IPD_CTL_STATUS);
+    ipd_ctl_status.s.pbp_en = 1;
+    cvmx_write_csr (CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64);
+
+    /* enable bp for each id */
+    for (i = 0, tmp = pent; i < cal_depth; i++, tmp++)
+    {
+        bpid = tmp->pipe_bpid;
+        ipd_bpidx_mbuf_th.u64 =
+            cvmx_read_csr (CVMX_IPD_BPIDX_MBUF_TH(bpid));
+        ipd_bpidx_mbuf_th.s.page_cnt = 1; /* 256 buffers */
+        ipd_bpidx_mbuf_th.s.bp_enb = 1;
+        cvmx_write_csr (CVMX_IPD_BPIDX_MBUF_TH(bpid), ipd_bpidx_mbuf_th.u64);
+    }         
+    res = 0;
+
+    return res;
+}
+#endif
+
+/**
+ * enable calendar for tx
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a ILK interface. cn68xx has 2 interfaces: ilk0 and
+ *                  ilk1.
+ *
+ * @param cal_ena   enable or disable calendar
+ *
+ * @return Zero on success, negative of failure.
+ */
+static int cvmx_ilk_tx_cal_ena (int interface, unsigned char cal_ena)
+{
+    int res = -1;
+    cvmx_ilk_txx_cfg0_t ilk_txx_cfg0;
+
+    if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+        return res;
+
+    if (interface >= CVMX_NUM_ILK_INTF)
+        return res;
+
+    /* set the enable */
+    ilk_txx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_TXX_CFG0(interface));
+    ilk_txx_cfg0.s.cal_ena = cal_ena;
+    cvmx_write_csr (CVMX_ILK_TXX_CFG0(interface), ilk_txx_cfg0.u64); 
+    cvmx_read_csr (CVMX_ILK_TXX_CFG0(interface));
+    res = 0;
+
+    return res;
+}
+
+/**
+ * set up calendar for tx
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a ILK interface. cn68xx has 2 interfaces: ilk0 and
+ *                  ilk1.
+ *
+ * @param cal_depth the number of calendar entries
+ * @param pent      pointer to calendar entries
+ * @param cal_ena   enable or disable calendar
+ *
+ * @return Zero on success, negative of failure.
+ */
+int cvmx_ilk_cal_setup_tx (int interface, int cal_depth,
+                           cvmx_ilk_cal_entry_t *pent, unsigned char cal_ena)
+{
+    int res = -1;
+
+    if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+        return res;
+
+    if (interface >= CVMX_NUM_ILK_INTF)
+        return res;
+
+    res = cvmx_ilk_tx_cal_conf (interface, cal_depth, pent);
+    if (res < 0)
+        return res;
+
+#ifdef CVMX_ILK_BP_CONF_ENA
+    res = cvmx_ilk_bp_conf (interface, cal_depth, pent);
+    if (res < 0)
+        return res;
+#endif
+
+    res = cvmx_ilk_tx_cal_ena (interface, cal_ena);
+    return res;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_ilk_cal_setup_tx);
+#endif
+
+#ifdef CVMX_ILK_STATS_ENA
+static void cvmx_ilk_reg_dump_rx (int interface)
+{
+    int i;
+    cvmx_ilk_rxx_cfg0_t ilk_rxx_cfg0;
+    cvmx_ilk_rxx_cfg1_t ilk_rxx_cfg1;
+    cvmx_ilk_rxx_int_t ilk_rxx_int;
+    cvmx_ilk_rxx_jabber_t ilk_rxx_jabber;
+    cvmx_ilk_rx_lnex_cfg_t ilk_rx_lnex_cfg;
+    cvmx_ilk_rx_lnex_int_t ilk_rx_lnex_int;
+    cvmx_ilk_gbl_cfg_t ilk_gbl_cfg;
+    cvmx_ilk_ser_cfg_t ilk_ser_cfg;
+    cvmx_ilk_rxf_idx_pmap_t ilk_rxf_idx_pmap;
+    cvmx_ilk_rxf_mem_pmap_t ilk_rxf_mem_pmap;
+    cvmx_ilk_rxx_idx_cal_t ilk_rxx_idx_cal;
+    cvmx_ilk_rxx_mem_cal0_t ilk_rxx_mem_cal0;
+    cvmx_ilk_rxx_mem_cal1_t ilk_rxx_mem_cal1;
+
+    ilk_rxx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_RXX_CFG0(interface));
+    cvmx_dprintf ("ilk rxx cfg0: 0x%16lx\n", ilk_rxx_cfg0.u64);
+    
+    ilk_rxx_cfg1.u64 = cvmx_read_csr (CVMX_ILK_RXX_CFG1(interface));
+    cvmx_dprintf ("ilk rxx cfg1: 0x%16lx\n", ilk_rxx_cfg1.u64);
+    
+    ilk_rxx_int.u64 = cvmx_read_csr (CVMX_ILK_RXX_INT(interface));
+    cvmx_dprintf ("ilk rxx int: 0x%16lx\n", ilk_rxx_int.u64);
+    cvmx_write_csr (CVMX_ILK_RXX_INT(interface), ilk_rxx_int.u64);
+
+    ilk_rxx_jabber.u64 = cvmx_read_csr (CVMX_ILK_RXX_JABBER(interface));
+    cvmx_dprintf ("ilk rxx jabber: 0x%16lx\n", ilk_rxx_jabber.u64);
+
+#define LNE_NUM_DBG 4
+    for (i = 0; i < LNE_NUM_DBG; i++)
+    {
+        ilk_rx_lnex_cfg.u64 = cvmx_read_csr (CVMX_ILK_RX_LNEX_CFG(i));
+        cvmx_dprintf ("ilk rx lnex cfg lane: %d  0x%16lx\n", i,
+                      ilk_rx_lnex_cfg.u64);
+    }
+
+    for (i = 0; i < LNE_NUM_DBG; i++)
+    {
+        ilk_rx_lnex_int.u64 = cvmx_read_csr (CVMX_ILK_RX_LNEX_INT(i));
+        cvmx_dprintf ("ilk rx lnex int lane: %d  0x%16lx\n", i,
+                      ilk_rx_lnex_int.u64);
+        cvmx_write_csr (CVMX_ILK_RX_LNEX_INT(i), ilk_rx_lnex_int.u64);
+    }
+
+    ilk_gbl_cfg.u64 = cvmx_read_csr (CVMX_ILK_GBL_CFG);
+    cvmx_dprintf ("ilk gbl cfg: 0x%16lx\n", ilk_gbl_cfg.u64);
+
+    ilk_ser_cfg.u64 = cvmx_read_csr (CVMX_ILK_SER_CFG);
+    cvmx_dprintf ("ilk ser cfg: 0x%16lx\n", ilk_ser_cfg.u64);
+
+#define CHAN_NUM_DBG 8
+    ilk_rxf_idx_pmap.u64 = 0;
+    ilk_rxf_idx_pmap.s.index = interface * 256;
+    ilk_rxf_idx_pmap.s.inc = 1;
+    cvmx_write_csr (CVMX_ILK_RXF_IDX_PMAP, ilk_rxf_idx_pmap.u64);
+    for (i = 0; i < CHAN_NUM_DBG; i++)
+    {
+        ilk_rxf_mem_pmap.u64 = cvmx_read_csr (CVMX_ILK_RXF_MEM_PMAP);
+        cvmx_dprintf ("ilk rxf mem pmap chan: %3d  0x%16lx\n", i,
+                      ilk_rxf_mem_pmap.u64);
+    }
+
+#define CAL_NUM_DBG 2
+    ilk_rxx_idx_cal.u64 = 0;
+    ilk_rxx_idx_cal.s.inc = 1;
+    cvmx_write_csr (CVMX_ILK_RXX_IDX_CAL(interface), ilk_rxx_idx_cal.u64); 
+    for (i = 0; i < CAL_NUM_DBG; i++)
+    {
+        ilk_rxx_idx_cal.u64 = cvmx_read_csr(CVMX_ILK_RXX_IDX_CAL(interface));
+        cvmx_dprintf ("ilk rxx idx cal: 0x%16lx\n", ilk_rxx_idx_cal.u64);
+
+        ilk_rxx_mem_cal0.u64 = cvmx_read_csr(CVMX_ILK_RXX_MEM_CAL0(interface));
+        cvmx_dprintf ("ilk rxx mem cal0: 0x%16lx\n", ilk_rxx_mem_cal0.u64);
+        ilk_rxx_mem_cal1.u64 = cvmx_read_csr(CVMX_ILK_RXX_MEM_CAL1(interface));
+        cvmx_dprintf ("ilk rxx mem cal1: 0x%16lx\n", ilk_rxx_mem_cal1.u64);
+    }
+}
+
+static void cvmx_ilk_reg_dump_tx (int interface)
+{
+    int i;
+    cvmx_ilk_txx_cfg0_t ilk_txx_cfg0;
+    cvmx_ilk_txx_cfg1_t ilk_txx_cfg1;
+    cvmx_ilk_txx_idx_pmap_t ilk_txx_idx_pmap;
+    cvmx_ilk_txx_mem_pmap_t ilk_txx_mem_pmap;
+    cvmx_ilk_txx_int_t ilk_txx_int;
+    cvmx_ilk_txx_pipe_t ilk_txx_pipe;
+    cvmx_ilk_txx_idx_cal_t ilk_txx_idx_cal;
+    cvmx_ilk_txx_mem_cal0_t ilk_txx_mem_cal0;
+    cvmx_ilk_txx_mem_cal1_t ilk_txx_mem_cal1;
+
+    ilk_txx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_TXX_CFG0(interface));
+    cvmx_dprintf ("ilk txx cfg0: 0x%16lx\n", ilk_txx_cfg0.u64);
+    
+    ilk_txx_cfg1.u64 = cvmx_read_csr (CVMX_ILK_TXX_CFG1(interface));
+    cvmx_dprintf ("ilk txx cfg1: 0x%16lx\n", ilk_txx_cfg1.u64);
+
+    ilk_txx_pipe.u64 = cvmx_read_csr (CVMX_ILK_TXX_PIPE(interface));
+    cvmx_dprintf ("ilk txx pipe: 0x%16lx\n", ilk_txx_pipe.u64);
+
+    ilk_txx_idx_pmap.u64 = 0;
+    ilk_txx_idx_pmap.s.index = ilk_txx_pipe.s.base;
+    ilk_txx_idx_pmap.s.inc = 1;
+    cvmx_write_csr (CVMX_ILK_TXX_IDX_PMAP(interface), ilk_txx_idx_pmap.u64);
+    for (i = 0; i < CHAN_NUM_DBG; i++)
+    {
+        ilk_txx_mem_pmap.u64 = cvmx_read_csr (CVMX_ILK_TXX_MEM_PMAP(interface));
+        cvmx_dprintf ("ilk txx mem pmap pipe: %3d  0x%16lx\n",
+                      ilk_txx_pipe.s.base + i, ilk_txx_mem_pmap.u64);
+    }
+
+    ilk_txx_int.u64 = cvmx_read_csr (CVMX_ILK_TXX_INT(interface));
+    cvmx_dprintf ("ilk txx int: 0x%16lx\n", ilk_txx_int.u64);
+
+    ilk_txx_idx_cal.u64 = 0;
+    ilk_txx_idx_cal.s.inc = 1;
+    cvmx_write_csr (CVMX_ILK_TXX_IDX_CAL(interface), ilk_txx_idx_cal.u64); 
+    for (i = 0; i < CAL_NUM_DBG; i++)
+    {
+        ilk_txx_idx_cal.u64 = cvmx_read_csr(CVMX_ILK_TXX_IDX_CAL(interface));
+        cvmx_dprintf ("ilk txx idx cal: 0x%16lx\n", ilk_txx_idx_cal.u64);
+
+        ilk_txx_mem_cal0.u64 = cvmx_read_csr(CVMX_ILK_TXX_MEM_CAL0(interface));
+        cvmx_dprintf ("ilk txx mem cal0: 0x%16lx\n", ilk_txx_mem_cal0.u64);
+        ilk_txx_mem_cal1.u64 = cvmx_read_csr(CVMX_ILK_TXX_MEM_CAL1(interface));
+        cvmx_dprintf ("ilk txx mem cal1: 0x%16lx\n", ilk_txx_mem_cal1.u64);
+    }
+}
+#endif
+
+/**
+ * show run time status
+ *
+ * @param interface The identifier of the packet interface to enable. cn68xx
+ *                  has 2 interfaces: ilk0 and ilk1.
+ *
+ * @return nothing
+ */
+#ifdef CVMX_ILK_RUNTIME_DBG
+void cvmx_ilk_runtime_status (int interface)
+{
+    cvmx_ilk_txx_cfg1_t ilk_txx_cfg1;
+    cvmx_ilk_txx_flow_ctl0_t ilk_txx_flow_ctl0; 
+    cvmx_ilk_rxx_cfg1_t ilk_rxx_cfg1;
+    cvmx_ilk_rxx_int_t ilk_rxx_int;
+    cvmx_ilk_rxx_flow_ctl0_t ilk_rxx_flow_ctl0; 
+    cvmx_ilk_rxx_flow_ctl1_t ilk_rxx_flow_ctl1; 
+    cvmx_ilk_gbl_int_t ilk_gbl_int;
+
+    cvmx_dprintf ("\nilk run-time status: interface: %d\n", interface);
+
+    ilk_txx_cfg1.u64 = cvmx_read_csr (CVMX_ILK_TXX_CFG1(interface));
+    cvmx_dprintf ("\nilk txx cfg1: 0x%16lx\n", ilk_txx_cfg1.u64);
+    if (ilk_txx_cfg1.s.rx_link_fc)
+        cvmx_dprintf ("link flow control received\n");
+    if (ilk_txx_cfg1.s.tx_link_fc)
+        cvmx_dprintf ("link flow control sent\n");
+
+    ilk_txx_flow_ctl0.u64 = cvmx_read_csr (CVMX_ILK_TXX_FLOW_CTL0(interface));
+    cvmx_dprintf ("\nilk txx flow ctl0: 0x%16lx\n", ilk_txx_flow_ctl0.u64);
+        
+    ilk_rxx_cfg1.u64 = cvmx_read_csr (CVMX_ILK_RXX_CFG1(interface));
+    cvmx_dprintf ("\nilk rxx cfg1: 0x%16lx\n", ilk_rxx_cfg1.u64);
+    cvmx_dprintf ("rx fifo count: %d\n", ilk_rxx_cfg1.s.rx_fifo_cnt);
+
+    ilk_rxx_int.u64 = cvmx_read_csr (CVMX_ILK_RXX_INT(interface));
+    cvmx_dprintf ("\nilk rxx int: 0x%16lx\n", ilk_rxx_int.u64);
+    if (ilk_rxx_int.s.pkt_drop_rxf)
+        cvmx_dprintf ("rx fifo packet drop\n");
+    if (ilk_rxx_int.u64)
+        cvmx_write_csr (CVMX_ILK_RXX_INT(interface), ilk_rxx_int.u64);
+        
+    ilk_rxx_flow_ctl0.u64 = cvmx_read_csr (CVMX_ILK_RXX_FLOW_CTL0(interface));
+    cvmx_dprintf ("\nilk rxx flow ctl0: 0x%16lx\n", ilk_rxx_flow_ctl0.u64);
+
+    ilk_rxx_flow_ctl1.u64 = cvmx_read_csr (CVMX_ILK_RXX_FLOW_CTL1(interface));
+    cvmx_dprintf ("\nilk rxx flow ctl1: 0x%16lx\n", ilk_rxx_flow_ctl1.u64);
+
+    ilk_gbl_int.u64 = cvmx_read_csr (CVMX_ILK_GBL_INT);
+    cvmx_dprintf ("\nilk gbl int: 0x%16lx\n", ilk_gbl_int.u64);
+    if (ilk_gbl_int.s.rxf_push_full)
+        cvmx_dprintf ("rx fifo overflow\n");
+    if (ilk_gbl_int.u64)
+        cvmx_write_csr (CVMX_ILK_GBL_INT, ilk_gbl_int.u64);
+}
+#endif
+
+/**
+ * enable interface
+ *
+ * @param interface The identifier of the packet interface to enable. cn68xx
+ *                  has 2 interfaces: ilk0 and ilk1.
+ *
+ * @return Zero on success, negative of failure.
+ */
+//#define CVMX_ILK_STATS_ENA 1
+int cvmx_ilk_enable (int interface)
+{
+    int res = -1;
+    int retry_count = 0;
+    cvmx_helper_link_info_t result;
+    cvmx_ilk_txx_cfg1_t ilk_txx_cfg1;
+    cvmx_ilk_rxx_cfg1_t ilk_rxx_cfg1;
+#ifdef CVMX_ILK_STATS_ENA
+    cvmx_ilk_rxx_cfg0_t ilk_rxx_cfg0;
+    cvmx_ilk_txx_cfg0_t ilk_txx_cfg0;
+#endif
+
+    if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+        return res;
+
+    if (interface >= CVMX_NUM_ILK_INTF)
+        return res;
+
+    result.u64 = 0;
+    
+#ifdef CVMX_ILK_STATS_ENA
+    cvmx_dprintf ("\n");
+    cvmx_dprintf ("<<<< ILK%d: Before enabling ilk\n", interface);
+    cvmx_ilk_reg_dump_rx (interface);
+    cvmx_ilk_reg_dump_tx (interface);
+#endif
+
+    /* RX packet will be enabled only if link is up */
+
+    /* TX side */
+    ilk_txx_cfg1.u64 = cvmx_read_csr (CVMX_ILK_TXX_CFG1(interface));
+    ilk_txx_cfg1.s.pkt_ena = 1;
+    ilk_txx_cfg1.s.rx_link_fc_ign = 1; /* cannot use link fc workaround */
+    cvmx_write_csr (CVMX_ILK_TXX_CFG1(interface), ilk_txx_cfg1.u64); 
+    cvmx_read_csr (CVMX_ILK_TXX_CFG1(interface));
+
+#ifdef CVMX_ILK_STATS_ENA
+    /* RX side stats */
+    ilk_rxx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_RXX_CFG0(interface));
+    ilk_rxx_cfg0.s.lnk_stats_ena = 1;
+    cvmx_write_csr (CVMX_ILK_RXX_CFG0(interface), ilk_rxx_cfg0.u64); 
+
+    /* TX side stats */
+    ilk_txx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_TXX_CFG0(interface));
+    ilk_txx_cfg0.s.lnk_stats_ena = 1;
+    cvmx_write_csr (CVMX_ILK_TXX_CFG0(interface), ilk_txx_cfg0.u64); 
+#endif
+
+retry:
+    retry_count++;
+    if (retry_count > 10)
+       goto out;
+
+    /* Make sure the link is up, so that packets can be sent. */
+    result = __cvmx_helper_ilk_link_get(cvmx_helper_get_ipd_port(interface + CVMX_ILK_GBL_BASE, 0));
+
+    /* Small delay before another retry. */
+    cvmx_wait_usec(100);
+
+    ilk_rxx_cfg1.u64 = cvmx_read_csr(CVMX_ILK_RXX_CFG1(interface));
+    if (ilk_rxx_cfg1.s.pkt_ena == 0)
+       goto retry; 
+
+out:
+        
+#ifdef CVMX_ILK_STATS_ENA
+    cvmx_dprintf (">>>> ILK%d: After ILK is enabled\n", interface);
+    cvmx_ilk_reg_dump_rx (interface);
+    cvmx_ilk_reg_dump_tx (interface);
+#endif
+
+    if (result.s.link_up)
+        return 0;
+
+    return -1;
+}
+
+/**
+ * Disable interface
+ *
+ * @param interface The identifier of the packet interface to disable. cn68xx
+ *                  has 2 interfaces: ilk0 and ilk1.
+ *
+ * @return Zero on success, negative of failure.
+ */
+int cvmx_ilk_disable (int interface)
+{
+    int res = -1;
+    cvmx_ilk_txx_cfg1_t ilk_txx_cfg1;
+    cvmx_ilk_rxx_cfg1_t ilk_rxx_cfg1;
+#ifdef CVMX_ILK_STATS_ENA
+    cvmx_ilk_rxx_cfg0_t ilk_rxx_cfg0;
+    cvmx_ilk_txx_cfg0_t ilk_txx_cfg0;
+#endif
+
+    if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+        return res;
+
+    if (interface >= CVMX_NUM_ILK_INTF)
+        return res;
+
+    /* TX side */
+    ilk_txx_cfg1.u64 = cvmx_read_csr (CVMX_ILK_TXX_CFG1(interface));
+    ilk_txx_cfg1.s.pkt_ena = 0;
+    cvmx_write_csr (CVMX_ILK_TXX_CFG1(interface), ilk_txx_cfg1.u64); 
+
+    /* RX side */
+    ilk_rxx_cfg1.u64 = cvmx_read_csr (CVMX_ILK_RXX_CFG1(interface));
+    ilk_rxx_cfg1.s.pkt_ena = 0;
+    cvmx_write_csr (CVMX_ILK_RXX_CFG1(interface), ilk_rxx_cfg1.u64); 
+
+#ifdef CVMX_ILK_STATS_ENA
+    /* RX side stats */
+    ilk_rxx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_RXX_CFG0(interface));
+    ilk_rxx_cfg0.s.lnk_stats_ena = 0;
+    cvmx_write_csr (CVMX_ILK_RXX_CFG0(interface), ilk_rxx_cfg0.u64); 
+
+    /* RX side stats */
+    ilk_txx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_TXX_CFG0(interface));
+    ilk_txx_cfg0.s.lnk_stats_ena = 0;
+    cvmx_write_csr (CVMX_ILK_TXX_CFG0(interface), ilk_txx_cfg0.u64); 
+#endif
+
+    return 0;
+}
+
+/**
+ * Provide interface enable status
+ *
+ * @param interface The identifier of the packet interface to disable. cn68xx
+ *                  has 2 interfaces: ilk0 and ilk1.
+ *
+ * @return Zero, not enabled; One, enabled.
+ */
+int cvmx_ilk_get_intf_ena (int interface)
+{
+    return cvmx_ilk_intf_cfg[interface].intf_en;
+}
+
+/**
+ * bit counter
+ *
+ * @param uc the byte to be counted
+ *
+ * @return number of bits set
+ */
+unsigned char cvmx_ilk_bit_count (unsigned char uc)
+{
+    unsigned char count;
+
+    for (count = 0; uc > 0; uc &= uc-1)
+        count++;
+
+    return count;
+}
+
+/**
+ * Provide interface lane mask
+ *
+ * @param interface The identifier of the packet interface to disable. cn68xx
+ *                  has 2 interfaces: ilk0 and ilk1.
+ *
+ * @return lane mask
+ */
+unsigned char cvmx_ilk_get_intf_ln_msk (int interface)
+{
+    return cvmx_ilk_intf_cfg[interface].lane_en_mask;
+}
+
+/**
+ * Provide channel info
+ *
+ * @param interface The identifier of the packet interface to disable. cn68xx
+ *                  has 2 interfaces: ilk0 and ilk1.
+ * @param chans    A pointer to a channel array
+ * @param num_chan A pointer to the number of channels
+ *
+ * @return Zero on success, negative of failure.
+ */
+int cvmx_ilk_get_chan_info (int interface, unsigned char **chans,
+                            unsigned char *num_chan)
+{
+    *chans = cvmx_ilk_chan_map[interface];
+    *num_chan = cvmx_ilk_chans[interface];
+
+    return 0;
+}
+
+/**
+ * Show channel statistics
+ *
+ * @param interface The identifier of the packet interface to disable. cn68xx
+ *                  has 2 interfaces: ilk0 and ilk1.
+ * @param pstats A pointer to cvmx_ilk_stats_ctrl_t that specifies which
+ *               logical channels to access
+ *
+ * @return nothing
+ */
+void cvmx_ilk_show_stats (int interface, cvmx_ilk_stats_ctrl_t *pstats)
+{
+    unsigned int i;
+    cvmx_ilk_rxx_idx_stat0_t ilk_rxx_idx_stat0;
+    cvmx_ilk_rxx_idx_stat1_t ilk_rxx_idx_stat1;
+    cvmx_ilk_rxx_mem_stat0_t ilk_rxx_mem_stat0;
+    cvmx_ilk_rxx_mem_stat1_t ilk_rxx_mem_stat1;
+
+    cvmx_ilk_txx_idx_stat0_t ilk_txx_idx_stat0;
+    cvmx_ilk_txx_idx_stat1_t ilk_txx_idx_stat1;
+    cvmx_ilk_txx_mem_stat0_t ilk_txx_mem_stat0;
+    cvmx_ilk_txx_mem_stat1_t ilk_txx_mem_stat1;
+
+    if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+        return;
+
+    if (interface >= CVMX_NUM_ILK_INTF)
+        return;
+
+    if (pstats == NULL)
+        return;
+
+    /* discrete channels */
+    if (pstats->chan_list != NULL)
+    {
+        for (i = 0; i < pstats->num_chans; i++)
+        {
+
+            /* get the number of rx packets */
+            ilk_rxx_idx_stat0.u64 = 0;
+            ilk_rxx_idx_stat0.s.index = *pstats->chan_list;
+            ilk_rxx_idx_stat0.s.clr = pstats->clr_on_rd;
+            cvmx_write_csr (CVMX_ILK_RXX_IDX_STAT0(interface),
+                            ilk_rxx_idx_stat0.u64);
+            ilk_rxx_mem_stat0.u64 = cvmx_read_csr
+                                    (CVMX_ILK_RXX_MEM_STAT0(interface));
+
+            /* get the number of rx bytes */
+            ilk_rxx_idx_stat1.u64 = 0;
+            ilk_rxx_idx_stat1.s.index = *pstats->chan_list;
+            ilk_rxx_idx_stat1.s.clr = pstats->clr_on_rd;
+            cvmx_write_csr (CVMX_ILK_RXX_IDX_STAT1(interface),
+                            ilk_rxx_idx_stat1.u64);
+            ilk_rxx_mem_stat1.u64 = cvmx_read_csr
+                                    (CVMX_ILK_RXX_MEM_STAT1(interface));
+
+            cvmx_dprintf ("ILK%d Channel%d Rx: %d packets %d bytes\n", interface,
+                    *pstats->chan_list, ilk_rxx_mem_stat0.s.rx_pkt,
+                    (unsigned int) ilk_rxx_mem_stat1.s.rx_bytes);
+
+            /* get the number of tx packets */
+            ilk_txx_idx_stat0.u64 = 0;
+            ilk_txx_idx_stat0.s.index = *pstats->chan_list;
+            ilk_txx_idx_stat0.s.clr = pstats->clr_on_rd;
+            cvmx_write_csr (CVMX_ILK_TXX_IDX_STAT0(interface),
+                            ilk_txx_idx_stat0.u64);
+            ilk_txx_mem_stat0.u64 = cvmx_read_csr
+                                    (CVMX_ILK_TXX_MEM_STAT0(interface));
+
+            /* get the number of tx bytes */
+            ilk_txx_idx_stat1.u64 = 0;
+            ilk_txx_idx_stat1.s.index = *pstats->chan_list;
+            ilk_txx_idx_stat1.s.clr = pstats->clr_on_rd;
+            cvmx_write_csr (CVMX_ILK_TXX_IDX_STAT1(interface),
+                            ilk_txx_idx_stat1.u64);
+            ilk_txx_mem_stat1.u64 = cvmx_read_csr
+                                    (CVMX_ILK_TXX_MEM_STAT1(interface));
+
+            cvmx_dprintf ("ILK%d Channel%d Tx: %d packets %d bytes\n", interface,
+                    *pstats->chan_list, ilk_txx_mem_stat0.s.tx_pkt,
+                    (unsigned int) ilk_txx_mem_stat1.s.tx_bytes);
+
+            pstats++;
+        }
+        return;
+    }
+
+    /* continuous channels */
+    ilk_rxx_idx_stat0.u64 = 0;
+    ilk_rxx_idx_stat0.s.index = pstats->chan_start;
+    ilk_rxx_idx_stat0.s.inc = pstats->chan_step;
+    ilk_rxx_idx_stat0.s.clr = pstats->clr_on_rd;
+    cvmx_write_csr (CVMX_ILK_RXX_IDX_STAT0(interface), ilk_rxx_idx_stat0.u64);
+
+    ilk_rxx_idx_stat1.u64 = 0;
+    ilk_rxx_idx_stat1.s.index = pstats->chan_start;
+    ilk_rxx_idx_stat1.s.inc = pstats->chan_step;
+    ilk_rxx_idx_stat1.s.clr = pstats->clr_on_rd;
+    cvmx_write_csr (CVMX_ILK_RXX_IDX_STAT1(interface), ilk_rxx_idx_stat1.u64);
+
+    ilk_txx_idx_stat0.u64 = 0;
+    ilk_txx_idx_stat0.s.index = pstats->chan_start;
+    ilk_txx_idx_stat0.s.inc = pstats->chan_step;
+    ilk_txx_idx_stat0.s.clr = pstats->clr_on_rd;
+    cvmx_write_csr (CVMX_ILK_TXX_IDX_STAT0(interface), ilk_txx_idx_stat0.u64);
+
+    ilk_txx_idx_stat1.u64 = 0;
+    ilk_txx_idx_stat1.s.index = pstats->chan_start;
+    ilk_txx_idx_stat1.s.inc = pstats->chan_step;
+    ilk_txx_idx_stat1.s.clr = pstats->clr_on_rd;
+    cvmx_write_csr (CVMX_ILK_TXX_IDX_STAT1(interface), ilk_txx_idx_stat1.u64);
+
+    for (i = pstats->chan_start; i <= pstats->chan_end; i += pstats->chan_step)
+    {
+        ilk_rxx_mem_stat0.u64 = cvmx_read_csr
+                                (CVMX_ILK_RXX_MEM_STAT0(interface));
+        ilk_rxx_mem_stat1.u64 = cvmx_read_csr
+                                (CVMX_ILK_RXX_MEM_STAT1(interface));
+        cvmx_dprintf ("ILK%d Channel%d Rx: %d packets %d bytes\n", interface, i,
+                ilk_rxx_mem_stat0.s.rx_pkt,
+                (unsigned int) ilk_rxx_mem_stat1.s.rx_bytes);
+
+        ilk_txx_mem_stat0.u64 = cvmx_read_csr
+                                (CVMX_ILK_TXX_MEM_STAT0(interface));
+        ilk_txx_mem_stat1.u64 = cvmx_read_csr
+                                (CVMX_ILK_TXX_MEM_STAT1(interface));
+        cvmx_dprintf ("ILK%d Channel%d Tx: %d packets %d bytes\n", interface, i,
+                ilk_rxx_mem_stat0.s.rx_pkt,
+                (unsigned int) ilk_rxx_mem_stat1.s.rx_bytes);
+    }
+
+    return;
+}
+
+/**
+ * enable or disable loopbacks
+ *
+ * @param interface The identifier of the packet interface to disable. cn68xx
+ *                  has 2 interfaces: ilk0 and ilk1.
+ * @param enable    Enable or disable loopback
+ * @param mode      Internal or external loopback
+ *
+ * @return Zero on success, negative of failure.
+ */
+int cvmx_ilk_lpbk (int interface, cvmx_ilk_lpbk_ena_t enable,
+                   cvmx_ilk_lpbk_mode_t mode)
+{
+    int res = -1;
+    cvmx_ilk_txx_cfg0_t ilk_txx_cfg0;
+    cvmx_ilk_rxx_cfg0_t ilk_rxx_cfg0;
+
+    if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+        return res;
+
+    if (interface >= CVMX_NUM_ILK_INTF)
+        return res;
+
+    /* internal loopback. only 1 type of loopback can be on at 1 time */
+    if (mode == CVMX_ILK_LPBK_INT)
+    {
+        if (enable == CVMX_ILK_LPBK_ENA)
+        {
+            ilk_txx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_TXX_CFG0(interface));
+            ilk_txx_cfg0.s.ext_lpbk = CVMX_ILK_LPBK_DISA;
+            ilk_txx_cfg0.s.ext_lpbk_fc = CVMX_ILK_LPBK_DISA;
+            cvmx_write_csr (CVMX_ILK_TXX_CFG0(interface), ilk_txx_cfg0.u64);
+
+            ilk_rxx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_RXX_CFG0(interface));
+            ilk_rxx_cfg0.s.ext_lpbk = CVMX_ILK_LPBK_DISA;
+            ilk_rxx_cfg0.s.ext_lpbk_fc = CVMX_ILK_LPBK_DISA;
+            cvmx_write_csr (CVMX_ILK_RXX_CFG0(interface), ilk_rxx_cfg0.u64);
+        }
+
+        ilk_txx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_TXX_CFG0(interface));
+        ilk_txx_cfg0.s.int_lpbk = enable;
+        cvmx_write_csr (CVMX_ILK_TXX_CFG0(interface), ilk_txx_cfg0.u64);
+
+        res = 0;
+        return res;
+    }
+
+    /* external loopback. only 1 type of loopback can be on at 1 time */
+    if (enable == CVMX_ILK_LPBK_ENA)
+    {
+        ilk_txx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_TXX_CFG0(interface));
+        ilk_txx_cfg0.s.int_lpbk = CVMX_ILK_LPBK_DISA;
+        cvmx_write_csr (CVMX_ILK_TXX_CFG0(interface), ilk_txx_cfg0.u64);
+    }
+
+    ilk_txx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_TXX_CFG0(interface));
+    ilk_txx_cfg0.s.ext_lpbk = enable;
+    ilk_txx_cfg0.s.ext_lpbk_fc = enable;
+    cvmx_write_csr (CVMX_ILK_TXX_CFG0(interface), ilk_txx_cfg0.u64);
+
+    ilk_rxx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_RXX_CFG0(interface));
+    ilk_rxx_cfg0.s.ext_lpbk = enable;
+    ilk_rxx_cfg0.s.ext_lpbk_fc = enable;
+    cvmx_write_csr (CVMX_ILK_RXX_CFG0(interface), ilk_rxx_cfg0.u64);
+
+    res = 0;
+    return res;
+}
+
+#endif /* CVMX_ENABLE_HELPER_FUNCTIONS */
diff --git a/sys/contrib/octeon-sdk/cvmx-ilk.h b/sys/contrib/octeon-sdk/cvmx-ilk.h
new file mode 100644
index 0000000..83e0b91
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-ilk.h
@@ -0,0 +1,183 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * This file contains defines for the ILK interface
+
+ * <hr>$Revision: 49448 $<hr>
+ *
+ *
+ */
+#ifndef __CVMX_ILK_H__
+#define __CVMX_ILK_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* CSR typedefs have been moved to cvmx-ilk-defs.h */
+
+#define CVMX_ILK_GBL_BASE  5
+#define CVMX_ILK_QLM_BASE  1
+
+typedef struct
+{
+    int intf_en      : 8;
+    int lane_en_mask : 8;
+    int lane_speed   : 16;
+    /* add more here */
+} cvmx_ilk_intf_t;
+
+#define CVMX_NUM_ILK_INTF  2
+#define CVMX_MAX_ILK_LANES 8
+extern unsigned char cvmx_ilk_lane_mask[CVMX_NUM_ILK_INTF];
+
+typedef struct
+{
+    unsigned int pipe;
+    unsigned int chan;
+} cvmx_ilk_pipe_chan_t;
+
+#define CVMX_ILK_PIPE_BASE 72
+#define CVMX_MAX_ILK_PIPES 45
+#define CVMX_MAX_ILK_CHANS 8
+extern unsigned char cvmx_ilk_chans[CVMX_NUM_ILK_INTF];
+extern unsigned char cvmx_ilk_chan_map[CVMX_NUM_ILK_INTF][CVMX_MAX_ILK_CHANS];
+
+typedef struct
+{
+    unsigned int chan;
+    unsigned int pknd;
+} cvmx_ilk_chan_pknd_t;
+
+#define CVMX_ILK_PKND_BASE 20
+#define CVMX_MAX_ILK_PKNDS 8 /* must be <45 */
+
+typedef struct
+{
+    unsigned int *chan_list; /* for discrete channels. or, must be null */
+    unsigned int num_chans;
+
+    unsigned int chan_start; /* for continuous channels */
+    unsigned int chan_end;
+    unsigned int chan_step;
+
+    unsigned int clr_on_rd;
+} cvmx_ilk_stats_ctrl_t;
+
+#define CVMX_ILK_MAX_CAL      288
+#define CVMX_ILK_TX_MIN_CAL   1
+#define CVMX_ILK_RX_MIN_CAL   1
+#define CVMX_ILK_CAL_GRP_SZ   8
+#define CVMX_ILK_PIPE_BPID_SZ 7
+#define CVMX_ILK_ENT_CTRL_SZ  2
+#define CVMX_ILK_RX_FIFO_WM   0x200
+
+typedef enum
+{
+    PIPE_BPID = 0,
+    LINK, 
+    XOFF,
+    XON
+} cvmx_ilk_cal_ent_ctrl_t;
+
+typedef struct
+{
+    unsigned char pipe_bpid;
+    cvmx_ilk_cal_ent_ctrl_t ent_ctrl;
+} cvmx_ilk_cal_entry_t;
+
+/** Callbacks structure to customize ILK initialization sequence */
+typedef struct
+{
+    /** Called to setup rx calendar */
+    int (*calendar_setup_rx) (int interface, int cal_depth,
+                              cvmx_ilk_cal_entry_t *pent, int hi_wm,
+                              unsigned char cal_ena);
+
+    /** add more here */
+} cvmx_ilk_callbacks_t;
+
+typedef enum
+{
+    CVMX_ILK_LPBK_DISA = 0,
+    CVMX_ILK_LPBK_ENA
+} cvmx_ilk_lpbk_ena_t;
+
+typedef enum
+{
+    CVMX_ILK_LPBK_INT = 0,
+    CVMX_ILK_LPBK_EXT
+} cvmx_ilk_lpbk_mode_t;
+
+extern void cvmx_ilk_get_callbacks(cvmx_ilk_callbacks_t * callbacks);
+extern void cvmx_ilk_set_callbacks(cvmx_ilk_callbacks_t * new_callbacks);
+
+extern int cvmx_ilk_start_interface (int interface, unsigned char num_lanes);
+extern int cvmx_ilk_set_pipe (int interface, int pipe_base,
+                              unsigned int pipe_len);
+extern int cvmx_ilk_tx_set_channel (int interface, cvmx_ilk_pipe_chan_t *pch,
+                                    unsigned int num_chs);
+extern int cvmx_ilk_rx_set_pknd (int interface, cvmx_ilk_chan_pknd_t *chpknd,
+                                 unsigned int num_pknd);
+extern int cvmx_ilk_calendar_setup_cb (int interface, int num_ports);
+extern int cvmx_ilk_calendar_sync_cb (int interface, int timeout);
+extern int cvmx_ilk_enable (int interface);
+extern int cvmx_ilk_disable (int interface);
+extern int cvmx_ilk_get_intf_ena (int interface);
+extern unsigned char cvmx_ilk_bit_count (unsigned char uc);
+extern unsigned char cvmx_ilk_get_intf_ln_msk (int interface);
+extern int cvmx_ilk_get_chan_info (int interface, unsigned char **chans,
+                                   unsigned char *num_chan);
+extern void cvmx_ilk_show_stats (int interface, cvmx_ilk_stats_ctrl_t *pstats);
+extern int cvmx_ilk_cal_setup_rx (int interface, int cal_depth,
+                                  cvmx_ilk_cal_entry_t *pent, int hi_wm,
+                                  unsigned char cal_ena);
+extern int cvmx_ilk_cal_setup_tx (int interface, int cal_depth,
+                                  cvmx_ilk_cal_entry_t *pent,
+                                  unsigned char cal_ena);
+extern int cvmx_ilk_lpbk (int interface, cvmx_ilk_lpbk_ena_t enable,
+                          cvmx_ilk_lpbk_mode_t mode);
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /* __CVMX_ILK_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-interrupt-handler.S b/sys/contrib/octeon-sdk/cvmx-interrupt-handler.S
index fc45622..b2b1837 100644
--- a/sys/contrib/octeon-sdk/cvmx-interrupt-handler.S
+++ b/sys/contrib/octeon-sdk/cvmx-interrupt-handler.S
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights 
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights 
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.  
@@ -26,7 +26,7 @@
  * countries. 
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -103,7 +103,7 @@ LEAF(cvmx_interrupt_stage2)
         ** error bit */
         dmfc0   k0, $27, 1
         sd      k0, 272(sp)
-        /* Store DEPC for GCC's frame unwinder. */
+        /* Store EPC for GCC's frame unwinder. */
         dmfc0   k0, $14
         sd      k0, 280(sp)
 
@@ -184,6 +184,13 @@ not_dcache_error:
 	sd	k0, ICACHE_ERROR_COUNT($0)	// Store the icache error count
 not_icache_error:
 	ld	k0, K0_STORE_LOCATION($0)	// Restore K0 since we might have been in an exception
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop					// Keep the ERET 8 instructions away
+	nop					// from a branch target.
 	eret					// Return from the Icache exception
 	.set pop
 END(cvmx_interrupt_cache_error)
diff --git a/sys/contrib/octeon-sdk/cvmx-interrupt.c b/sys/contrib/octeon-sdk/cvmx-interrupt.c
index 9280e8d..f90412a 100644
--- a/sys/contrib/octeon-sdk/cvmx-interrupt.c
+++ b/sys/contrib/octeon-sdk/cvmx-interrupt.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -37,18 +37,12 @@
  * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
-
-
-
-
-
-
 /**
  * @file
  *
  * Interface to the Mips interrupts.
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifndef __U_BOOT__
 #if __GNUC__ >= 4
@@ -65,23 +59,34 @@
 #include "cvmx-ebt3000.h"
 #include "cvmx-coremask.h"
 #include "cvmx-spinlock.h"
+#include "cvmx-atomic.h"
 #include "cvmx-app-init.h"
 #include "cvmx-error.h"
-#include "../../bootloader/u-boot/include/octeon_mem_map.h"
-
+#include "cvmx-app-hotplug.h"
+#include "cvmx-profiler.h"
+#ifndef __U_BOOT__
+# include <octeon_mem_map.h>
+#else
+# include <asm/arch/octeon_mem_map.h>
+#endif
 EXTERN_ASM void cvmx_interrupt_stage1(void);
 EXTERN_ASM void cvmx_debug_handler_stage1(void);
 EXTERN_ASM void cvmx_interrupt_cache_error(void);
 
 int cvmx_interrupt_in_isr = 0;
 
+struct __cvmx_interrupt_handler {
+    cvmx_interrupt_func_t handler;      /**< One function to call per interrupt */
+    void *data;                         /**< User data per interrupt */
+    int handler_data;                   /**< Used internally */
+};
+
 /**
  * Internal status the interrupt registration
  */
 typedef struct
 {
-    cvmx_interrupt_func_t handlers[256];  /**< One function to call per interrupt */
-    void *                data[256];      /**< User data per interrupt */
+    struct __cvmx_interrupt_handler handlers[CVMX_IRQ_MAX];
     cvmx_interrupt_exception_t exception_handler;
 } cvmx_interrupt_state_t;
 
@@ -91,12 +96,14 @@ typedef struct
 #ifndef __U_BOOT__
 static CVMX_SHARED cvmx_interrupt_state_t cvmx_interrupt_state;
 static CVMX_SHARED cvmx_spinlock_t cvmx_interrupt_default_lock;
+/* Incremented once first core processing is finished. */
+static CVMX_SHARED int32_t cvmx_interrupt_initialize_flag;
 #endif  /* __U_BOOT__ */
 
 #define ULL unsigned long long
 
-#define HI32(data64)	((uint32_t)(data64 >> 32))
-#define LO32(data64)	((uint32_t)(data64 & 0xFFFFFFFF))
+#define HI32(data64)    ((uint32_t)(data64 >> 32))
+#define LO32(data64)    ((uint32_t)(data64 & 0xFFFFFFFF))
 
 static const char reg_names[][32] = { "r0","at","v0","v1","a0","a1","a2","a3",
                                       "t0","t1","t2","t3","t4","t5","t6","t7",
@@ -197,7 +204,7 @@ static inline void print_reg64(const char *name, uint64_t reg)
  *
  * @param registers CPU register to dump
  */
-static void __cvmx_interrupt_dump_registers(uint64_t registers[32])
+static void __cvmx_interrupt_dump_registers(uint64_t *registers)
 {
     uint64_t r1, r2;
     int reg;
@@ -228,12 +235,13 @@ static void __cvmx_interrupt_dump_registers(uint64_t registers[32])
 #ifndef __U_BOOT__
 static
 #endif  /* __U_BOOT__ */
-void __cvmx_interrupt_default_exception_handler(uint64_t registers[32])
+void __cvmx_interrupt_default_exception_handler(uint64_t *registers)
 {
     uint64_t trap_print_cause;
     const char *str;
-
 #ifndef __U_BOOT__
+    int modified_zero_pc = 0;
+
     ebt3000_str_write("Trap");
     cvmx_spinlock_lock(&cvmx_interrupt_default_lock);
 #endif
@@ -248,36 +256,43 @@ void __cvmx_interrupt_default_exception_handler(uint64_t registers[32])
     cvmx_safe_printf("******************************************************************\n");
 #if __GNUC__ >= 4 && !defined(OCTEON_DISABLE_BACKTRACE)
     cvmx_safe_printf("Backtrace:\n\n");
+    if (registers[35] == 0) {
+	modified_zero_pc = 1;
+	/* If PC is zero we probably did jalr $zero, in which case $31 - 8 is the call site. */
+	registers[35] = registers[31] - 8;
+    }
     __octeon_print_backtrace_func ((__octeon_backtrace_printf_t)cvmx_safe_printf);
+    if (modified_zero_pc)
+	registers[35] = 0;
     cvmx_safe_printf("******************************************************************\n");
 #endif
 
     cvmx_spinlock_unlock(&cvmx_interrupt_default_lock);
 
     if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
-	CVMX_BREAK;
+        CVMX_BREAK;
 
     while (1)
     {
-	/* Interrupts are suppressed when we are in the exception
-	   handler (because of SR[EXL]).  Spin and poll the uart
-	   status and see if the debugger is trying to stop us. */
-	cvmx_uart_lsr_t lsrval;
-	lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(cvmx_debug_uart));
-	if (lsrval.s.dr)
-	{
-	    uint64_t tmp;
-	    /* Pulse the MCD0 signal. */
-	    asm volatile (
-	    ".set push\n"
-	    ".set noreorder\n"
-	    ".set mips64\n"
-	    "dmfc0 %0, $22\n"
-	    "ori   %0, %0, 0x10\n"
-	    "dmtc0 %0, $22\n"
-	    ".set pop\n"
-	    : "=r" (tmp));
-	}
+        /* Interrupts are suppressed when we are in the exception
+           handler (because of SR[EXL]).  Spin and poll the uart
+           status and see if the debugger is trying to stop us. */
+        cvmx_uart_lsr_t lsrval;
+        lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(cvmx_debug_uart));
+        if (lsrval.s.dr)
+        {
+            uint64_t tmp;
+            /* Pulse the MCD0 signal. */
+            asm volatile (
+            ".set push\n"
+            ".set noreorder\n"
+            ".set mips64\n"
+            "dmfc0 %0, $22\n"
+            "ori   %0, %0, 0x10\n"
+            "dmtc0 %0, $22\n"
+            ".set pop\n"
+            : "=r" (tmp));
+        }
     }
 #endif /* __U_BOOT__ */
 }
@@ -291,17 +306,69 @@ void __cvmx_interrupt_default_exception_handler(uint64_t registers[32])
  * @param registers  Register at the time of the interrupt
  * @param user_arg   Unused optional user data
  */
-static void __cvmx_interrupt_default(int irq_number, uint64_t registers[32], void *user_arg)
+static void __cvmx_interrupt_default(int irq_number, uint64_t *registers, void *user_arg)
 {
     cvmx_safe_printf("cvmx_interrupt_default: Received interrupt %d\n", irq_number);
     __cvmx_interrupt_dump_registers(registers);
 }
 
+/**
+ * Map a ciu bit to an irq number.  0xff for invalid.
+ * 0-63 for en0.
+ * 64-127 for en1.
+ */
+
+static CVMX_SHARED uint8_t cvmx_ciu_to_irq[8][64];
+#define cvmx_ciu_en0_to_irq cvmx_ciu_to_irq[0]
+#define cvmx_ciu_en1_to_irq cvmx_ciu_to_irq[1]
+#define cvmx_ciu2_wrkq_to_irq cvmx_ciu_to_irq[0]
+#define cvmx_ciu2_wdog_to_irq cvmx_ciu_to_irq[1]
+#define cvmx_ciu2_rml_to_irq cvmx_ciu_to_irq[2]
+#define cvmx_ciu2_mio_to_irq cvmx_ciu_to_irq[3]
+#define cvmx_ciu2_io_to_irq cvmx_ciu_to_irq[4]
+#define cvmx_ciu2_mem_to_irq cvmx_ciu_to_irq[5]
+#define cvmx_ciu2_eth_to_irq cvmx_ciu_to_irq[6]
+#define cvmx_ciu2_gpio_to_irq cvmx_ciu_to_irq[7]
+
+static CVMX_SHARED uint8_t cvmx_ciu2_mbox_to_irq[64];
+static CVMX_SHARED uint8_t cvmx_ciu_61xx_timer_to_irq[64];
+
+static void __cvmx_interrupt_set_mapping(int irq, unsigned int en, unsigned int bit)
+{
+    cvmx_interrupt_state.handlers[irq].handler_data = (en << 6) | bit;
+    if (en <= 7)
+        cvmx_ciu_to_irq[en][bit] = irq;
+    else if (en == 8)
+        cvmx_ciu_61xx_timer_to_irq[bit] = irq;
+    else 
+        cvmx_ciu2_mbox_to_irq[bit] = irq;
+}
+
+static uint64_t cvmx_interrupt_ciu_en0_mirror;
+static uint64_t cvmx_interrupt_ciu_en1_mirror;
+static uint64_t cvmx_interrupt_ciu_61xx_timer_mirror;
+
+/**
+ * @INTERNAL
+ * Called for all Performance Counter interrupts. Handler for 
+ * interrupt line 6
+ *
+ * @param irq_number Interrupt number that we're being called for
+ * @param registers  Registers at the time of the interrupt
+ * @param user_arg   Unused user argument*
+ */ 
+static void __cvmx_interrupt_perf(int irq_number, uint64_t *registers, void *user_arg)
+{
+    uint64_t perf_counter;
+    CVMX_MF_COP0(perf_counter, COP0_PERFVALUE0);
+    if (perf_counter & (1ull << 63))
+        cvmx_collect_sample();
+}
 
 /**
  * @INTERNAL
  * Handler for interrupt lines 2 and 3. These are directly tied
- * to the CIU. The handler queres the status of the CIU and
+ * to the CIU. The handler queries the status of the CIU and
  * calls the secondary handler for the CIU interrupt that
  * occurred.
  *
@@ -309,37 +376,194 @@ static void __cvmx_interrupt_default(int irq_number, uint64_t registers[32], voi
  * @param registers  Registers at the time of the interrupt
  * @param user_arg   Unused user argument
  */
-static void __cvmx_interrupt_ciu(int irq_number, uint64_t registers[32], void *user_arg)
+static void __cvmx_interrupt_ciu(int irq_number, uint64_t *registers, void *user_arg)
 {
-    int ciu_offset = cvmx_get_core_num() * 2 + irq_number - 2;
-    uint64_t irq_mask = cvmx_read_csr(CVMX_CIU_INTX_SUM0(ciu_offset)) & cvmx_read_csr(CVMX_CIU_INTX_EN0(ciu_offset));
-    int irq = 8;
+    int ciu_offset;
+    uint64_t irq_mask;
+    uint64_t irq;
+    int bit;
+    int core = cvmx_get_core_num();
+
+    if (irq_number == CVMX_IRQ_MIPS2) {
+        /* Handle EN0 sources */
+        ciu_offset = core * 2;
+        irq_mask = cvmx_read_csr(CVMX_CIU_INTX_SUM0(ciu_offset)) & cvmx_interrupt_ciu_en0_mirror;
+        CVMX_DCLZ(bit, irq_mask);
+        bit = 63 - bit;
+        /* If ciu_int_sum1<sum2> is set, means its a timer interrupt */
+        if (bit == 51 && (OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_2))) {
+            uint64_t irq_mask;
+            int bit;
+            irq_mask = cvmx_read_csr(CVMX_CIU_SUM2_PPX_IP2(core)) & cvmx_interrupt_ciu_61xx_timer_mirror;
+            CVMX_DCLZ(bit, irq_mask);
+            bit = 63 - bit;
+            /* Handle TIMER(4..9) interrupts */
+            if (bit <= 9 && bit >= 4) {
+                uint64_t irq = cvmx_ciu_61xx_timer_to_irq[bit];
+                if (cvmx_unlikely(irq == 0xff)) {
+                    /* No mapping */
+                    cvmx_interrupt_ciu_61xx_timer_mirror &= ~(1ull << bit);
+                    cvmx_write_csr(CVMX_CIU_EN2_PPX_IP2(core), cvmx_interrupt_ciu_61xx_timer_mirror);
+                    return;
+                }
+                struct __cvmx_interrupt_handler *h = cvmx_interrupt_state.handlers + irq;
+                h->handler(irq, registers, h->data);
+                return;
+            }
+        }
 
-    /* Handle EN0 sources */
-    while (irq_mask)
-    {
-        if (irq_mask&1)
-        {
-            cvmx_interrupt_state.handlers[irq](irq, registers, cvmx_interrupt_state.data[irq]);
+        if (bit >= 0) {
+            irq = cvmx_ciu_en0_to_irq[bit];
+            if (cvmx_unlikely(irq == 0xff)) {
+                /* No mapping. */
+                cvmx_interrupt_ciu_en0_mirror &= ~(1ull << bit);
+                cvmx_write_csr(CVMX_CIU_INTX_EN0(ciu_offset), cvmx_interrupt_ciu_en0_mirror);
+                return;
+            }
+            struct __cvmx_interrupt_handler *h = cvmx_interrupt_state.handlers + irq;
+            h->handler(irq, registers, h->data);
+            return;
+        }
+    } else {
+        /* Handle EN1 sources */
+        ciu_offset = cvmx_get_core_num() * 2 + 1;
+        irq_mask = cvmx_read_csr(CVMX_CIU_INT_SUM1) & cvmx_interrupt_ciu_en1_mirror;
+        CVMX_DCLZ(bit, irq_mask);
+        bit = 63 - bit;
+        if (bit >= 0) {
+            irq = cvmx_ciu_en1_to_irq[bit];
+            if (cvmx_unlikely(irq == 0xff)) {
+                /* No mapping. */
+                cvmx_interrupt_ciu_en1_mirror &= ~(1ull << bit);
+                cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), cvmx_interrupt_ciu_en1_mirror);
+                return;
+            }
+            struct __cvmx_interrupt_handler *h = cvmx_interrupt_state.handlers + irq;
+            h->handler(irq, registers, h->data);
             return;
         }
-        irq_mask = irq_mask >> 1;
-        irq++;
     }
+}
 
+/**
+ * @INTERNAL
+ * Handler for interrupt line 3, the DPI_DMA will have different value
+ * per core, all other fields values are identical for different cores.
+ *  These are directly tied to the CIU. The handler queries the status of
+ * the CIU and calls the secondary handler for the CIU interrupt that
+ * occurred.
+ *
+ * @param irq_number Interrupt number that fired (2 or 3)
+ * @param registers  Registers at the time of the interrupt
+ * @param user_arg   Unused user argument
+ */
+static void __cvmx_interrupt_ciu_cn61xx(int irq_number, uint64_t *registers, void *user_arg)
+{
     /* Handle EN1 sources */
-    irq_mask = cvmx_read_csr(CVMX_CIU_INT_SUM1) & cvmx_read_csr(CVMX_CIU_INTX_EN1(ciu_offset));
-    irq = 8 + 64;
-    while (irq_mask)
-    {
-        if (irq_mask&1)
-        {
-            cvmx_interrupt_state.handlers[irq](irq, registers, cvmx_interrupt_state.data[irq]);
+    int core = cvmx_get_core_num();
+    int ciu_offset;
+    uint64_t irq_mask;
+    uint64_t irq;
+    int bit;
+
+    ciu_offset = core * 2 + 1;
+    irq_mask = cvmx_read_csr(CVMX_CIU_SUM1_PPX_IP3(core)) & cvmx_interrupt_ciu_en1_mirror;
+    CVMX_DCLZ(bit, irq_mask);
+    bit = 63 - bit;
+    if (bit >= 0) {
+        irq = cvmx_ciu_en1_to_irq[bit];
+        if (cvmx_unlikely(irq == 0xff)) {
+            /* No mapping. */
+            cvmx_interrupt_ciu_en1_mirror &= ~(1ull << bit);
+            cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), cvmx_interrupt_ciu_en1_mirror);
             return;
         }
-        irq_mask = irq_mask >> 1;
-        irq++;
+        struct __cvmx_interrupt_handler *h = cvmx_interrupt_state.handlers + irq;
+        h->handler(irq, registers, h->data);
+        return;
+    }
+}
+
+/**
+ * @INTERNAL
+ * Handler for interrupt line 2 on 68XX. These are directly tied
+ * to the CIU2. The handler queries the status of the CIU and
+ * calls the secondary handler for the CIU interrupt that
+ * occurred.
+ *
+ * @param irq_number Interrupt number that fired (2 or 3)
+ * @param registers  Registers at the time of the interrupt
+ * @param user_arg   Unused user argument
+ */
+static void __cvmx_interrupt_ciu2(int irq_number, uint64_t *registers, void *user_arg)
+{
+    int sum_bit, src_bit;
+    uint64_t irq;
+    uint64_t src_reg, src_val;
+    struct __cvmx_interrupt_handler *h;
+    int core = cvmx_get_core_num();
+    uint64_t sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(core));
+
+    CVMX_DCLZ(sum_bit, sum);
+    sum_bit = 63 - sum_bit;
+
+    if (sum_bit >= 0) {
+        switch (sum_bit) {
+        case 63:
+        case 62:
+        case 61:
+        case 60:
+            irq = cvmx_ciu2_mbox_to_irq[sum_bit - 60];
+            if (cvmx_unlikely(irq == 0xff)) {
+                /* No mapping. */
+                uint64_t mask_reg = CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(core);
+                cvmx_write_csr(mask_reg, 1ull << (sum_bit - 60));
+                break;
+            }
+            h = cvmx_interrupt_state.handlers + irq;
+            h->handler(irq, registers, h->data);
+            break;
+
+        case 7:
+        case 6:
+        case 5:
+        case 4:
+        case 3:
+        case 2:
+        case 1:
+        case 0:
+            src_reg = CVMX_CIU2_SRC_PPX_IP2_WRKQ(core) + (0x1000 * sum_bit);
+            src_val = cvmx_read_csr(src_reg);
+            if (!src_val)
+                break;
+            CVMX_DCLZ(src_bit, src_val);
+            src_bit = 63 - src_bit;
+            irq = cvmx_ciu_to_irq[sum_bit][src_bit];
+            if (cvmx_unlikely(irq == 0xff)) {
+                /* No mapping. */
+                uint64_t mask_reg = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(core) + (0x1000 * sum_bit);
+                cvmx_write_csr(mask_reg, 1ull << src_bit);
+                break;
+            }
+            h = cvmx_interrupt_state.handlers + irq;
+            h->handler(irq, registers, h->data);
+            break;
+
+        default:
+            cvmx_safe_printf("Unknown CIU2 bit: %d\n", sum_bit);
+            break;
+        }
     }
+    /* Clear the source to reduce the chance for spurious interrupts.  */
+
+    /* CN68XX has an CIU-15786 errata that accessing the ACK registers
+     * can stop interrupts from propagating
+     */
+
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+        cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY);
+    else
+        cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP2(core));
 }
 
 
@@ -351,7 +575,7 @@ static void __cvmx_interrupt_ciu(int irq_number, uint64_t registers[32], void *u
  * @param registers  Registers at the time of the interrupt
  * @param user_arg   Unused user argument
  */
-static void __cvmx_interrupt_ecc(int irq_number, uint64_t registers[32], void *user_arg)
+static void __cvmx_interrupt_ecc(int irq_number, uint64_t *registers, void *user_arg)
 {
     cvmx_error_poll();
 }
@@ -364,8 +588,8 @@ static void __cvmx_interrupt_ecc(int irq_number, uint64_t registers[32], void *u
  * Registers 0-31 are standard MIPS, others specific to this routine
  * @return
  */
-EXTERN_ASM void cvmx_interrupt_do_irq(uint64_t registers[35]);
-void cvmx_interrupt_do_irq(uint64_t registers[35])
+void cvmx_interrupt_do_irq(uint64_t *registers);
+void cvmx_interrupt_do_irq(uint64_t *registers)
 {
     uint64_t        mask;
     uint64_t        cause;
@@ -390,26 +614,49 @@ void cvmx_interrupt_do_irq(uint64_t registers[35])
     /* Check for cache errors.  The cache errors go to a separate exception vector,
     ** so we will only check these if we got here from a cache error exception, and
     ** the ERL (error level) bit is set. */
+    i = cvmx_get_core_num();
     if (exc_vec == 0x100 && (status & 0x4))
     {
-        i = cvmx_get_core_num();
         CVMX_MF_CACHE_ERR(cache_err);
 
         /* Use copy of DCACHE_ERR register that early exception stub read */
-        if (registers[34] & 0x1)
+        if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
         {
-            cvmx_safe_printf("Dcache error detected: core: %d, set: %d, va 6:3: 0x%x\n", i, (int)(cache_err >> 3) & 0x3, (int)(cache_err >> 3) & 0xf);
-            uint64_t dcache_err = 0;
-            CVMX_MT_DCACHE_ERR(dcache_err);
+            if (registers[34] & 0x1)
+                cvmx_safe_printf("Dcache error detected: core: %d, way: %d, va 7:3: 0x%x\n", i, (int)(registers[34] >> 8) & 0x3f, (int)(registers[34] >> 3) & 0x1f);
+            else if (cache_err & 0x1)
+                cvmx_safe_printf("Icache error detected: core: %d, set: %d, way : %d, va 6:3 = 0x%x\n", i, (int)(cache_err >> 5) & 0x3f, (int)(cache_err >> 3) & 0x3, (int)(cache_err >> 11) & 0xf);
+            else
+                cvmx_safe_printf("Cache error exception: core %d\n", i);
         }
-        else if (cache_err & 0x1)
+        else
         {
-            cvmx_safe_printf("Icache error detected: core: %d, set: %d, way : %d\n", i, (int)(cache_err >> 5) & 0x3f, (int)(cache_err >> 7) & 0x3);
-            cache_err = 0;
-            CVMX_MT_CACHE_ERR(cache_err);
+            if (registers[34] & 0x1)
+                cvmx_safe_printf("Dcache error detected: core: %d, way: %d, va 9:7: 0x%x\n", i, (int)(registers[34] >> 10) & 0x1f, (int)(registers[34] >> 7) & 0x3);
+            else if (cache_err & 0x1)
+                cvmx_safe_printf("Icache error detected: core: %d, way : %d, va 9:3 = 0x%x\n", i, (int)(cache_err >> 10) & 0x3f, (int)(cache_err >> 3) & 0x7f);
+            else
+                cvmx_safe_printf("Cache error exception: core %d\n", i);
+        }
+        CVMX_MT_DCACHE_ERR(1);
+        CVMX_MT_CACHE_ERR(0);
+    }
+
+    /* The bus error exceptions can occur due to DID timeout or write buffer,
+       check by reading COP0_CACHEERRD */
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
+    {
+        i = cvmx_get_core_num();
+        if (registers[34] & 0x4)
+        {
+            cvmx_safe_printf("Bus error detected due to DID timeout: core: %d\n", i);
+            CVMX_MT_DCACHE_ERR(4);
+        }
+        else if (registers[34] & 0x2)
+        {
+            cvmx_safe_printf("Bus error detected due to write buffer parity: core: %d\n", i);
+            CVMX_MT_DCACHE_ERR(2);
         }
-        else
-            cvmx_safe_printf("Cache error exception: core %d\n", i);
     }
 
     if ((cause & 0x7c) != 0)
@@ -429,7 +676,8 @@ void cvmx_interrupt_do_irq(uint64_t registers[35])
     {
         if (mask & (1<<i))
         {
-            cvmx_interrupt_state.handlers[i](i, registers, cvmx_interrupt_state.data[i]);
+            struct __cvmx_interrupt_handler *h = cvmx_interrupt_state.handlers + i;
+            h->handler(i, registers, h->data);
             goto return_from_interrupt;
         }
     }
@@ -442,6 +690,399 @@ return_from_interrupt:
     asm volatile ("dmtc0 %0, $12, 0" : : "r" (status));
 }
 
+void (*cvmx_interrupt_mask_irq)(int irq_number);
+void (*cvmx_interrupt_unmask_irq)(int irq_number);
+
+#define CLEAR_OR_MASK(V,M,O) ({\
+            if (O)             \
+                (V) &= ~(M);   \
+            else               \
+                (V) |= (M);    \
+        })
+
+static void __cvmx_interrupt_ciu2_mask_unmask_irq(int irq_number, int op)
+{
+
+    if (irq_number < 0 || irq_number >= CVMX_IRQ_MAX)
+        return;
+
+    if (irq_number <=  CVMX_IRQ_MIPS7) {
+        uint32_t flags, mask;
+
+        flags = cvmx_interrupt_disable_save();
+        asm volatile ("mfc0 %0,$12,0" : "=r" (mask));
+        CLEAR_OR_MASK(mask, 1 << (8 + irq_number), op);
+        asm volatile ("mtc0 %0,$12,0" : : "r" (mask));
+        cvmx_interrupt_restore(flags);
+    } else {
+        int idx;
+        uint64_t reg;
+        int core = cvmx_get_core_num();
+
+        int bit = cvmx_interrupt_state.handlers[irq_number].handler_data;
+
+        if (bit < 0)
+            return;
+
+        idx = bit >> 6;
+        bit &= 0x3f;
+        if (idx > 7) {
+            /* MBOX */
+            if (op)
+                reg = CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(core);
+            else
+                reg = CVMX_CIU2_EN_PPX_IP2_MBOX_W1S(core);
+        } else {
+            if (op)
+                reg = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(core) + (0x1000 * idx);
+            else
+                reg = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(core) + (0x1000 * idx);
+        }
+        cvmx_write_csr(reg, 1ull << bit);
+    }
+}
+
+static void __cvmx_interrupt_ciu2_mask_irq(int irq_number)
+{
+    __cvmx_interrupt_ciu2_mask_unmask_irq(irq_number, 1);
+}
+
+static void __cvmx_interrupt_ciu2_unmask_irq(int irq_number)
+{
+    __cvmx_interrupt_ciu2_mask_unmask_irq(irq_number, 0);
+}
+
+static void __cvmx_interrupt_ciu_mask_unmask_irq(int irq_number, int op)
+{
+    uint32_t flags;
+
+    if (irq_number < 0 || irq_number >= CVMX_IRQ_MAX)
+        return;
+
+    flags = cvmx_interrupt_disable_save();
+    if (irq_number <=  CVMX_IRQ_MIPS7) {
+        uint32_t mask;
+        asm volatile ("mfc0 %0,$12,0" : "=r" (mask));
+        CLEAR_OR_MASK(mask, 1 << (8 + irq_number), op);
+        asm volatile ("mtc0 %0,$12,0" : : "r" (mask));
+    } else {
+        int ciu_bit, ciu_offset;
+        int bit = cvmx_interrupt_state.handlers[irq_number].handler_data;
+        int is_timer_intr = bit >> 6;
+        int core = cvmx_get_core_num();
+
+        if (bit < 0)
+            goto out;
+
+        ciu_bit = bit & 0x3f;
+        ciu_offset = core * 2;
+
+        if (is_timer_intr == 8)
+        {
+            CLEAR_OR_MASK(cvmx_interrupt_ciu_61xx_timer_mirror, 1ull << ciu_bit, op);
+            CLEAR_OR_MASK(cvmx_interrupt_ciu_en0_mirror, 1ull << 51, op); // SUM2 bit
+            cvmx_write_csr(CVMX_CIU_EN2_PPX_IP2(core), cvmx_interrupt_ciu_61xx_timer_mirror);
+        }
+        else if (bit & 0x40) {
+            /* EN1 */
+            ciu_offset += 1;
+            CLEAR_OR_MASK(cvmx_interrupt_ciu_en1_mirror, 1ull << ciu_bit, op);
+            cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), cvmx_interrupt_ciu_en1_mirror);
+        } else {
+            /* EN0 */
+            CLEAR_OR_MASK(cvmx_interrupt_ciu_en0_mirror, 1ull << ciu_bit, op);
+            cvmx_write_csr(CVMX_CIU_INTX_EN0(ciu_offset), cvmx_interrupt_ciu_en0_mirror);
+        }
+    }
+out:
+    cvmx_interrupt_restore(flags);
+}
+
+static void __cvmx_interrupt_ciu_mask_irq(int irq_number)
+{
+    __cvmx_interrupt_ciu_mask_unmask_irq(irq_number, 1);
+}
+
+static void __cvmx_interrupt_ciu_unmask_irq(int irq_number)
+{
+    __cvmx_interrupt_ciu_mask_unmask_irq(irq_number, 0);
+}
+
+/**
+ * Register an interrupt handler for the specified interrupt number.
+ *
+ * @param irq_number Interrupt number to register for See
+ *                   cvmx-interrupt.h for enumeration and description of sources.
+ * @param func       Function to call on interrupt.
+ * @param user_arg   User data to pass to the interrupt handler
+ */
+void cvmx_interrupt_register(int irq_number, cvmx_interrupt_func_t func, void *user_arg)
+{
+    if (irq_number >= CVMX_IRQ_MAX || irq_number < 0) {
+        cvmx_warn("cvmx_interrupt_register: Illegal irq_number %d\n", irq_number);
+        return;
+    }
+    cvmx_interrupt_state.handlers[irq_number].handler = func;
+    cvmx_interrupt_state.handlers[irq_number].data = user_arg;
+    CVMX_SYNCWS;
+}
+
+
+static void cvmx_interrupt_ciu_initialize(cvmx_sysinfo_t *sys_info_ptr)
+{
+    int i;
+    int core = cvmx_get_core_num();
+
+    /* Disable all CIU interrupts by default */
+    cvmx_interrupt_ciu_en0_mirror = 0;
+    cvmx_interrupt_ciu_en1_mirror = 0;
+    cvmx_interrupt_ciu_61xx_timer_mirror = 0;
+    cvmx_write_csr(CVMX_CIU_INTX_EN0(core * 2), cvmx_interrupt_ciu_en0_mirror);
+    cvmx_write_csr(CVMX_CIU_INTX_EN0((core * 2)+1), cvmx_interrupt_ciu_en0_mirror);
+    cvmx_write_csr(CVMX_CIU_INTX_EN1(core * 2), cvmx_interrupt_ciu_en1_mirror);
+    cvmx_write_csr(CVMX_CIU_INTX_EN1((core * 2)+1), cvmx_interrupt_ciu_en1_mirror);
+    if (OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_2))
+        cvmx_write_csr(CVMX_CIU_EN2_PPX_IP2(cvmx_get_core_num()), cvmx_interrupt_ciu_61xx_timer_mirror);
+
+    if (!cvmx_coremask_first_core(sys_info_ptr->core_mask)|| is_core_being_hot_plugged())
+        return;
+
+    /* On the first core, set up the maps */
+    for (i = 0; i < 64; i++) {
+        cvmx_ciu_en0_to_irq[i] = 0xff;
+        cvmx_ciu_en1_to_irq[i] = 0xff;
+        cvmx_ciu_61xx_timer_to_irq[i] = 0xff;
+    }
+
+    /* WORKQ */
+    for (i = 0; i < 16; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_WORKQ0 + i, 0, i);
+    /* GPIO */
+    for (i = 0; i < 16; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_GPIO0 + i, 0, i + 16);
+
+    /* MBOX */
+    for (i = 0; i < 2; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_MBOX0 + i, 0, i + 32);
+
+    /* UART */
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_UART0 + 0, 0, 34);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_UART0 + 1, 0, 35);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_UART0 + 2, 1, 16);
+
+    /* PCI */
+    for (i = 0; i < 4; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_PCI_INT0 + i, 0, i + 36);
+
+    /* MSI */
+    for (i = 0; i < 4; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_PCI_MSI0 + i, 0, i + 40);
+
+    /* TWSI */
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_TWSI0 + 0, 0, 45);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_TWSI0 + 1, 0, 59);
+
+    /* other */
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_RML, 0, 46);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_TRACE0, 0, 47);
+
+    /* GMX_DRP */
+    for (i = 0; i < 2; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_GMX_DRP0 + i, 0, i + 48);
+
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_IPD_DRP, 0, 50);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_KEY_ZERO, 0, 51);
+
+    /* TIMER0 */
+    for (i = 0; i < 4; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_TIMER0 + i, 0, i + 52);
+
+    /* TIMER4..9 */
+    for(i = 0; i < 6; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_TIMER4 + i, 8, i + 4);
+
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_USB0 + 0, 0, 56);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_USB0 + 1, 1, 17);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_PCM, 0, 57);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_MPI, 0, 58);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_POWIQ, 0, 60);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_IPDPPTHR, 0, 61);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_MII0 + 0, 0, 62);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_MII0 + 1, 1, 18);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_BOOTDMA, 0, 63);
+
+    /* WDOG */
+    for (i = 0; i < 16; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_WDOG0 + i, 1, i);
+
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_NAND, 1, 19);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_MIO, 1, 20);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_IOB, 1, 21);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_FPA, 1, 22);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_POW, 1, 23);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_L2C, 1, 24);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_IPD, 1, 25);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_PIP, 1, 26);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_PKO, 1, 27);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_ZIP, 1, 28);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_TIM, 1, 29);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_RAD, 1, 30);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_KEY, 1, 31);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_DFA, 1, 32);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_USBCTL, 1, 33);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_SLI, 1, 34);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_DPI, 1, 35);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_AGX0, 1, 36);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_AGX0 + 1, 1, 37);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_DPI_DMA, 1, 40);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_AGL, 1, 46);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_PTP, 1, 47);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_PEM0, 1, 48);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_PEM1, 1, 49);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_SRIO0, 1, 50);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_SRIO1, 1, 51);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_LMC0, 1, 52);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_DFM, 1, 56);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_SRIO2, 1, 60);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_RST, 1, 63);
+}
+
+static void cvmx_interrupt_ciu2_initialize(cvmx_sysinfo_t *sys_info_ptr)
+{
+    int i;
+
+    /* Disable all CIU2 interrupts by default */
+
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP2_WRKQ(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP3_WRKQ(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP4_WRKQ(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP2_WDOG(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP3_WDOG(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP4_WDOG(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP2_RML(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP3_RML(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP4_RML(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP2_MIO(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP3_MIO(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP4_MIO(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP2_IO(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP3_IO(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP4_IO(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP2_MEM(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP3_MEM(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP4_MEM(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP2_PKT(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP3_PKT(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP4_PKT(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP2_GPIO(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP3_GPIO(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP4_GPIO(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP2_MBOX(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP3_MBOX(cvmx_get_core_num()), 0);
+    cvmx_write_csr(CVMX_CIU2_EN_PPX_IP4_MBOX(cvmx_get_core_num()), 0);
+
+    if (!cvmx_coremask_first_core(sys_info_ptr->core_mask) || is_core_being_hot_plugged())
+        return;
+
+    /* On the first core, set up the maps */
+    for (i = 0; i < 64; i++) {
+        cvmx_ciu2_wrkq_to_irq[i] = 0xff;
+        cvmx_ciu2_wdog_to_irq[i] = 0xff;
+        cvmx_ciu2_rml_to_irq[i] = 0xff;
+        cvmx_ciu2_mio_to_irq[i] = 0xff;
+        cvmx_ciu2_io_to_irq[i] = 0xff;
+        cvmx_ciu2_mem_to_irq[i] = 0xff;
+        cvmx_ciu2_eth_to_irq[i] = 0xff;
+        cvmx_ciu2_gpio_to_irq[i] = 0xff;
+        cvmx_ciu2_mbox_to_irq[i] = 0xff;
+    }
+
+    /* WORKQ */
+    for (i = 0; i < 64; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_WORKQ0 + i, 0, i);
+
+    /* GPIO */
+    for (i = 0; i < 16; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_GPIO0 + i, 7, i);
+
+    /* MBOX */
+    for (i = 0; i < 4; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_MBOX0 + i, 60, i);
+
+    /* UART */
+    for (i = 0; i < 2; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_UART0 + i, 3, 36 + i);
+
+    /* PCI */
+    for (i = 0; i < 4; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_PCI_INT0 + i, 4, 16 + i);
+
+    /* MSI */
+    for (i = 0; i < 4; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_PCI_MSI0 + i, 4, 8 + i);
+
+    /* TWSI */
+    for (i = 0; i < 2; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_TWSI0 + i, 3, 32 + i);
+
+    /* TRACE */
+    for (i = 0; i < 4; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_TRACE0 + i, 2, 52 + i);
+
+    /* GMX_DRP */
+    for (i = 0; i < 5; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_GMX_DRP0 + i, 6, 8 + i);
+
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_IPD_DRP, 3, 2);
+
+    /* TIMER0 */
+    for (i = 0; i < 4; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_TIMER0 + i, 3, 8 + i);
+
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_USB0, 3, 44);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_IPDPPTHR, 3, 0);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_MII0, 6, 40);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_BOOTDMA, 3, 18);
+
+    /* WDOG */
+    for (i = 0; i < 32; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_WDOG0 + i, 1, i);
+
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_NAND, 3, 16);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_MIO, 3, 17);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_IOB, 2, 0);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_FPA, 2, 4);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_POW, 2, 16);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_L2C, 2, 48);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_IPD, 2, 5);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_PIP, 2, 6);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_PKO, 2, 7);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_ZIP, 2, 24);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_TIM, 2, 28);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_RAD, 2, 29);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_KEY, 2, 30);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_DFA, 2, 40);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_USBCTL, 3, 40);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_SLI, 2, 32);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_DPI, 2, 33);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_DPI_DMA, 2, 36);
+
+    /* AGX */
+    for (i = 0; i < 5; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_AGX0 + i, 6, i);
+
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_AGL, 6, 32);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_PTP, 3, 48);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_PEM0, 4, 32);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_PEM1, 4, 32);
+
+    /* LMC */
+    for (i = 0; i < 4; i++)
+        __cvmx_interrupt_set_mapping(CVMX_IRQ_LMC0 + i, 5, i);
+
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_RST, 3, 63);
+    __cvmx_interrupt_set_mapping(CVMX_IRQ_ILK, 6, 48);
+}
 
 /**
  * Initialize the interrupt routine and copy the low level
@@ -454,21 +1095,77 @@ void cvmx_interrupt_initialize(void)
     cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
     int i;
 
-    /* Disable all CIU interrupts by default */
-    cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0);
-    cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0);
-    cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0);
-    cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0);
+    if (cvmx_coremask_first_core(sys_info_ptr->core_mask) && !is_core_being_hot_plugged()) {
+#ifndef CVMX_ENABLE_CSR_ADDRESS_CHECKING
+        /* We assume this relationship between the registers. */
+        CVMX_BUILD_ASSERT(CVMX_CIU2_SRC_PPX_IP2_WRKQ(0) + 0x1000 == CVMX_CIU2_SRC_PPX_IP2_WDOG(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_SRC_PPX_IP2_WRKQ(0) + 0x2000 == CVMX_CIU2_SRC_PPX_IP2_RML(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_SRC_PPX_IP2_WRKQ(0) + 0x3000 == CVMX_CIU2_SRC_PPX_IP2_MIO(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_SRC_PPX_IP2_WRKQ(0) + 0x4000 == CVMX_CIU2_SRC_PPX_IP2_IO(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_SRC_PPX_IP2_WRKQ(0) + 0x5000 == CVMX_CIU2_SRC_PPX_IP2_MEM(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_SRC_PPX_IP2_WRKQ(0) + 0x6000 == CVMX_CIU2_SRC_PPX_IP2_PKT(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_SRC_PPX_IP2_WRKQ(0) + 0x7000 == CVMX_CIU2_SRC_PPX_IP2_GPIO(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(0) + 0x1000 == CVMX_CIU2_EN_PPX_IP2_WDOG_W1C(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(0) + 0x2000 == CVMX_CIU2_EN_PPX_IP2_RML_W1C(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(0) + 0x3000 == CVMX_CIU2_EN_PPX_IP2_MIO_W1C(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(0) + 0x4000 == CVMX_CIU2_EN_PPX_IP2_IO_W1C(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(0) + 0x5000 == CVMX_CIU2_EN_PPX_IP2_MEM_W1C(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(0) + 0x6000 == CVMX_CIU2_EN_PPX_IP2_PKT_W1C(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(0) + 0x7000 == CVMX_CIU2_EN_PPX_IP2_GPIO_W1C(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(0) + 0x1000 == CVMX_CIU2_EN_PPX_IP2_WDOG_W1S(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(0) + 0x2000 == CVMX_CIU2_EN_PPX_IP2_RML_W1S(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(0) + 0x3000 == CVMX_CIU2_EN_PPX_IP2_MIO_W1S(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(0) + 0x4000 == CVMX_CIU2_EN_PPX_IP2_IO_W1S(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(0) + 0x5000 == CVMX_CIU2_EN_PPX_IP2_MEM_W1S(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(0) + 0x6000 == CVMX_CIU2_EN_PPX_IP2_PKT_W1S(0));
+        CVMX_BUILD_ASSERT(CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(0) + 0x7000 == CVMX_CIU2_EN_PPX_IP2_GPIO_W1S(0));
+#endif /* !CVMX_ENABLE_CSR_ADDRESS_CHECKING */
+
+        for (i = 0; i < CVMX_IRQ_MAX; i++) {
+            cvmx_interrupt_state.handlers[i].handler = __cvmx_interrupt_default;
+            cvmx_interrupt_state.handlers[i].data = NULL;
+            cvmx_interrupt_state.handlers[i].handler_data = -1;
+        }
+    }
 
-    if (cvmx_coremask_first_core(sys_info_ptr->core_mask))
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
     {
-        cvmx_interrupt_state.exception_handler = __cvmx_interrupt_default_exception_handler;
+        cvmx_interrupt_mask_irq = __cvmx_interrupt_ciu2_mask_irq;
+        cvmx_interrupt_unmask_irq = __cvmx_interrupt_ciu2_unmask_irq;
+        cvmx_interrupt_ciu2_initialize(sys_info_ptr);
+        /* Add an interrupt handlers for chained CIU interrupt */
+        cvmx_interrupt_register(CVMX_IRQ_MIPS2, __cvmx_interrupt_ciu2, NULL);
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_2))
+    {
+        cvmx_interrupt_mask_irq = __cvmx_interrupt_ciu_mask_irq;
+        cvmx_interrupt_unmask_irq = __cvmx_interrupt_ciu_unmask_irq;
+        cvmx_interrupt_ciu_initialize(sys_info_ptr);
 
-        for (i=0; i<256; i++)
-        {
-            cvmx_interrupt_state.handlers[i] = __cvmx_interrupt_default;
-            cvmx_interrupt_state.data[i] = NULL;
-        }
+        /* Add an interrupt handlers for chained CIU interrupts */
+        cvmx_interrupt_register(CVMX_IRQ_MIPS2, __cvmx_interrupt_ciu, NULL);
+        cvmx_interrupt_register(CVMX_IRQ_MIPS3, __cvmx_interrupt_ciu_cn61xx, NULL);
+    }
+    else
+    {
+        cvmx_interrupt_mask_irq = __cvmx_interrupt_ciu_mask_irq;
+        cvmx_interrupt_unmask_irq = __cvmx_interrupt_ciu_unmask_irq;
+        cvmx_interrupt_ciu_initialize(sys_info_ptr);
+
+        /* Add an interrupt handlers for chained CIU interrupts */
+        cvmx_interrupt_register(CVMX_IRQ_MIPS2, __cvmx_interrupt_ciu, NULL);
+        cvmx_interrupt_register(CVMX_IRQ_MIPS3, __cvmx_interrupt_ciu, NULL);
+    }
+   
+    /* Move performance counter interrupts to IRQ 6*/
+    cvmx_update_perfcnt_irq();
+
+    /* Add an interrupt handler for Perf counter interrupts */
+    cvmx_interrupt_register(CVMX_IRQ_MIPS6, __cvmx_interrupt_perf, NULL);
+    
+    if (cvmx_coremask_first_core(sys_info_ptr->core_mask) && !is_core_being_hot_plugged())
+    {
+        cvmx_interrupt_state.exception_handler = __cvmx_interrupt_default_exception_handler;
 
         low_level_loc = CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,sys_info_ptr->exception_base_addr));
         memcpy(low_level_loc + 0x80, (void*)cvmx_interrupt_stage1, 0x80);
@@ -483,47 +1180,95 @@ void cvmx_interrupt_initialize(void)
         cvmx_write64_uint64(CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, 24), 0);
         CVMX_SYNC;
 
-        /* Add an interrupt handlers for chained CIU interrupts */
-        cvmx_interrupt_register(CVMX_IRQ_CIU0, __cvmx_interrupt_ciu, NULL);
-        cvmx_interrupt_register(CVMX_IRQ_CIU1, __cvmx_interrupt_ciu, NULL);
-
         /* Add an interrupt handler for ECC failures */
-        cvmx_interrupt_register(CVMX_IRQ_RML, __cvmx_interrupt_ecc, NULL);
-
         if (cvmx_error_initialize(0 /* || CVMX_ERROR_FLAGS_ECC_SINGLE_BIT */))
             cvmx_warn("cvmx_error_initialize() failed\n");
-        cvmx_interrupt_unmask_irq(CVMX_IRQ_RML);
+
+        /* Enable PIP/IPD, POW, PKO, FPA, NAND, KEY, RAD, L2C, LMC, GMX, AGL,
+           DFM, DFA, error handling interrupts. */ 
+        if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+        {
+            int i;
+
+            for (i = 0; i < 5; i++)
+            {
+                cvmx_interrupt_register(CVMX_IRQ_AGX0+i, __cvmx_interrupt_ecc, NULL);
+                cvmx_interrupt_unmask_irq(CVMX_IRQ_AGX0+i);
+            }
+            cvmx_interrupt_register(CVMX_IRQ_NAND, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_NAND);
+            cvmx_interrupt_register(CVMX_IRQ_MIO, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_MIO);
+            cvmx_interrupt_register(CVMX_IRQ_FPA, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_FPA);
+            cvmx_interrupt_register(CVMX_IRQ_IPD, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_IPD);
+            cvmx_interrupt_register(CVMX_IRQ_PIP, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_PIP);
+            cvmx_interrupt_register(CVMX_IRQ_POW, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_POW);
+            cvmx_interrupt_register(CVMX_IRQ_L2C, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_L2C);
+            cvmx_interrupt_register(CVMX_IRQ_PKO, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_PKO);
+            cvmx_interrupt_register(CVMX_IRQ_ZIP, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_ZIP);
+            cvmx_interrupt_register(CVMX_IRQ_RAD, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_RAD);
+            cvmx_interrupt_register(CVMX_IRQ_KEY, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_KEY);
+            /* Before enabling SLI interrupt clear any RML_TO interrupt */
+            if (cvmx_read_csr(CVMX_PEXP_SLI_INT_SUM) & 0x1)
+            {
+                cvmx_safe_printf("clearing pending SLI_INT_SUM[RML_TO] interrupt (ignore)\n");
+                cvmx_write_csr(CVMX_PEXP_SLI_INT_SUM, 1);
+            }
+            cvmx_interrupt_register(CVMX_IRQ_SLI, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_SLI);
+            cvmx_interrupt_register(CVMX_IRQ_DPI, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_DPI);
+            cvmx_interrupt_register(CVMX_IRQ_DFA, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_DFA);
+            cvmx_interrupt_register(CVMX_IRQ_AGL, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_AGL);
+            for (i = 0; i < 4; i++)
+            {
+                cvmx_interrupt_register(CVMX_IRQ_LMC0+i, __cvmx_interrupt_ecc, NULL);
+                cvmx_interrupt_unmask_irq(CVMX_IRQ_LMC0+i);
+            }
+            cvmx_interrupt_register(CVMX_IRQ_DFM, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_DFM);
+            cvmx_interrupt_register(CVMX_IRQ_RST, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_RST);
+            cvmx_interrupt_register(CVMX_IRQ_ILK, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_ILK);
+        }
+        else
+        {
+            cvmx_interrupt_register(CVMX_IRQ_RML, __cvmx_interrupt_ecc, NULL);
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_RML);
+        }
+
+        cvmx_atomic_set32(&cvmx_interrupt_initialize_flag, 1);
+    }
+
+    while (!cvmx_atomic_get32(&cvmx_interrupt_initialize_flag))
+        ; /* Wait for first core to finish above. */
+
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
+        cvmx_interrupt_unmask_irq(CVMX_IRQ_MIPS2);
+    } else {
+        cvmx_interrupt_unmask_irq(CVMX_IRQ_MIPS2);
+        cvmx_interrupt_unmask_irq(CVMX_IRQ_MIPS3);
     }
 
-    cvmx_interrupt_unmask_irq(CVMX_IRQ_CIU0);
-    cvmx_interrupt_unmask_irq(CVMX_IRQ_CIU1);
     CVMX_ICACHE_INVALIDATE;
 
     /* Enable interrupts for each core (bit0 of COP0 Status) */
-    uint32_t mask;
-    asm volatile (
-        "mfc0   %0,$12,0\n"
-        "ori    %0, %0, 1\n"
-        "mtc0   %0,$12,0\n"
-        : "=r" (mask));
+    cvmx_interrupt_restore(1);
 }
 
 
-/**
- * Register an interrupt handler for the specified interrupt number.
- *
- * @param irq_number Interrupt number to register for (0-135)  See
- *                   cvmx-interrupt.h for enumeration and description of sources.
- * @param func       Function to call on interrupt.
- * @param user_arg   User data to pass to the interrupt handler
- */
-void cvmx_interrupt_register(cvmx_irq_t irq_number, cvmx_interrupt_func_t func, void *user_arg)
-{
-    cvmx_interrupt_state.handlers[irq_number] = func;
-    cvmx_interrupt_state.data[irq_number] = user_arg;
-    CVMX_SYNCWS;
-}
-
 
 /**
  * Set the exception handler for all non interrupt sources.
diff --git a/sys/contrib/octeon-sdk/cvmx-interrupt.h b/sys/contrib/octeon-sdk/cvmx-interrupt.h
index c3275c3..c2619d7 100644
--- a/sys/contrib/octeon-sdk/cvmx-interrupt.h
+++ b/sys/contrib/octeon-sdk/cvmx-interrupt.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,12 +48,12 @@
  *
  * Interface to the Mips interrupts.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifndef __CVMX_INTERRUPT_H__
 #define __CVMX_INTERRUPT_H__
 
-#ifdef	__cplusplus
+#ifdef  __cplusplus
 extern "C" {
 #endif
 
@@ -64,140 +64,100 @@ typedef enum
 {
     /* 0 - 7 represent the 8 MIPS standard interrupt sources */
     CVMX_IRQ_SW0        = 0,
-    CVMX_IRQ_SW1        = 1,
-    CVMX_IRQ_CIU0       = 2,
-    CVMX_IRQ_CIU1       = 3,
-    CVMX_IRQ_4          = 4,
-    CVMX_IRQ_5          = 5,
-    CVMX_IRQ_6          = 6,
-    CVMX_IRQ_7          = 7,
-
-    /* 8 - 71 represent the sources in CIU_INTX_EN0 */
-    CVMX_IRQ_WORKQ0     = 8,
-    CVMX_IRQ_WORKQ1     = 9,
-    CVMX_IRQ_WORKQ2     = 10,
-    CVMX_IRQ_WORKQ3     = 11,
-    CVMX_IRQ_WORKQ4     = 12,
-    CVMX_IRQ_WORKQ5     = 13,
-    CVMX_IRQ_WORKQ6     = 14,
-    CVMX_IRQ_WORKQ7     = 15,
-    CVMX_IRQ_WORKQ8     = 16,
-    CVMX_IRQ_WORKQ9     = 17,
-    CVMX_IRQ_WORKQ10    = 18,
-    CVMX_IRQ_WORKQ11    = 19,
-    CVMX_IRQ_WORKQ12    = 20,
-    CVMX_IRQ_WORKQ13    = 21,
-    CVMX_IRQ_WORKQ14    = 22,
-    CVMX_IRQ_WORKQ15    = 23,
-    CVMX_IRQ_GPIO0      = 24,
-    CVMX_IRQ_GPIO1      = 25,
-    CVMX_IRQ_GPIO2      = 26,
-    CVMX_IRQ_GPIO3      = 27,
-    CVMX_IRQ_GPIO4      = 28,
-    CVMX_IRQ_GPIO5      = 29,
-    CVMX_IRQ_GPIO6      = 30,
-    CVMX_IRQ_GPIO7      = 31,
-    CVMX_IRQ_GPIO8      = 32,
-    CVMX_IRQ_GPIO9      = 33,
-    CVMX_IRQ_GPIO10     = 34,
-    CVMX_IRQ_GPIO11     = 35,
-    CVMX_IRQ_GPIO12     = 36,
-    CVMX_IRQ_GPIO13     = 37,
-    CVMX_IRQ_GPIO14     = 38,
-    CVMX_IRQ_GPIO15     = 39,
-    CVMX_IRQ_MBOX0      = 40,
-    CVMX_IRQ_MBOX1      = 41,
-    CVMX_IRQ_UART0      = 42,
-    CVMX_IRQ_UART1      = 43,
-    CVMX_IRQ_PCI_INT0   = 44,
-    CVMX_IRQ_PCI_INT1   = 45,
-    CVMX_IRQ_PCI_INT2   = 46,
-    CVMX_IRQ_PCI_INT3   = 47,
-    CVMX_IRQ_PCI_MSI0   = 48,
-    CVMX_IRQ_PCI_MSI1   = 49,
-    CVMX_IRQ_PCI_MSI2   = 50,
-    CVMX_IRQ_PCI_MSI3   = 51,
-    CVMX_IRQ_RESERVED44 = 52,
-    CVMX_IRQ_TWSI       = 53,
-    CVMX_IRQ_RML        = 54,
-    CVMX_IRQ_TRACE      = 55,
-    CVMX_IRQ_GMX_DRP0   = 56,
-    CVMX_IRQ_GMX_DRP1   = 57,   /* Doesn't apply on CN52XX or CN63XX */
-    CVMX_IRQ_IPD_DRP    = 58,
-    CVMX_IRQ_KEY_ZERO   = 59,   /* Doesn't apply on CN52XX or CN63XX */
-    CVMX_IRQ_TIMER0     = 60,
-    CVMX_IRQ_TIMER1     = 61,
-    CVMX_IRQ_TIMER2     = 62,
-    CVMX_IRQ_TIMER3     = 63,
-    CVMX_IRQ_USB0       = 64,   /* Doesn't apply on CN38XX or CN58XX */
-    CVMX_IRQ_PCM        = 65,   /* Doesn't apply on CN52XX or CN63XX */
-    CVMX_IRQ_MPI        = 66,   /* Doesn't apply on CN52XX or CN63XX */
-    CVMX_IRQ_TWSI2      = 67,   /* Added in CN56XX */
-    CVMX_IRQ_POWIQ      = 68,   /* Added in CN56XX */
-    CVMX_IRQ_IPDPPTHR   = 69,   /* Added in CN56XX */
-    CVMX_IRQ_MII        = 70,   /* Added in CN56XX */
-    CVMX_IRQ_BOOTDMA    = 71,   /* Added in CN56XX */
-
-    /* 72 - 135 represent the sources in CIU_INTX_EN1 */
-    CVMX_IRQ_WDOG0 = 72,
-    CVMX_IRQ_WDOG1 = 73,
-    CVMX_IRQ_WDOG2 = 74,
-    CVMX_IRQ_WDOG3 = 75,
-    CVMX_IRQ_WDOG4 = 76,
-    CVMX_IRQ_WDOG5 = 77,
-    CVMX_IRQ_WDOG6 = 78,
-    CVMX_IRQ_WDOG7 = 79,
-    CVMX_IRQ_WDOG8 = 80,
-    CVMX_IRQ_WDOG9 = 81,
-    CVMX_IRQ_WDOG10= 82,
-    CVMX_IRQ_WDOG11= 83,
-    CVMX_IRQ_WDOG12= 84,
-    CVMX_IRQ_WDOG13= 85,
-    CVMX_IRQ_WDOG14= 86,
-    CVMX_IRQ_WDOG15= 87,
-    CVMX_IRQ_UART2 = 88,           /* Added in CN52XX */
-    CVMX_IRQ_USB1  = 89,           /* Added in CN52XX */
-    CVMX_IRQ_MII1  = 90,           /* Added in CN52XX */
-    CVMX_IRQ_NAND  = 91,           /* Added in CN52XX */
-    CVMX_IRQ_MIO   = 92,           /* Added in CN63XX */
-    CVMX_IRQ_IOB   = 93,           /* Added in CN63XX */
-    CVMX_IRQ_FPA   = 94,           /* Added in CN63XX */
-    CVMX_IRQ_POW   = 95,           /* Added in CN63XX */
-    CVMX_IRQ_L2C   = 96,           /* Added in CN63XX */
-    CVMX_IRQ_IPD   = 97,           /* Added in CN63XX */
-    CVMX_IRQ_PIP   = 98,           /* Added in CN63XX */
-    CVMX_IRQ_PKO   = 99,           /* Added in CN63XX */
-    CVMX_IRQ_ZIP   = 100,          /* Added in CN63XX */
-    CVMX_IRQ_TIM   = 101,          /* Added in CN63XX */
-    CVMX_IRQ_RAD   = 102,          /* Added in CN63XX */
-    CVMX_IRQ_KEY   = 103,          /* Added in CN63XX */
-    CVMX_IRQ_DFA   = 104,          /* Added in CN63XX */
-    CVMX_IRQ_USB   = 105,          /* Added in CN63XX */
-    CVMX_IRQ_SLI   = 106,          /* Added in CN63XX */
-    CVMX_IRQ_DPI   = 107,          /* Added in CN63XX */
-    CVMX_IRQ_AGX0  = 108,          /* Added in CN63XX */
-    /* 109 - 117 are reserved */
-    CVMX_IRQ_AGL   = 118,          /* Added in CN63XX */
-    CVMX_IRQ_PTP   = 119,          /* Added in CN63XX */
-    CVMX_IRQ_PEM0  = 120,          /* Added in CN63XX */
-    CVMX_IRQ_PEM1  = 121,          /* Added in CN63XX */
-    CVMX_IRQ_SRIO0 = 122,          /* Added in CN63XX */
-    CVMX_IRQ_SRIO1 = 123,          /* Added in CN63XX */
-    CVMX_IRQ_LMC0  = 124,          /* Added in CN63XX */
-    /* Interrupts 125 - 127 are reserved */
-    CVMX_IRQ_DFM   = 128,          /* Added in CN63XX */
-    /* Interrupts 129 - 135 are reserved */
+    CVMX_IRQ_SW1,
+    CVMX_IRQ_MIPS2,
+    CVMX_IRQ_MIPS3,
+    CVMX_IRQ_MIPS4,
+    CVMX_IRQ_MIPS5,
+    CVMX_IRQ_MIPS6,
+    CVMX_IRQ_MIPS7,
+    /* 64 WORKQ interrupts. */
+    CVMX_IRQ_WORKQ0,
+    /* 16 GPIO interrupts. */
+    CVMX_IRQ_GPIO0      = CVMX_IRQ_WORKQ0 + 64,
+    /* 4  MBOX interrupts. */
+    CVMX_IRQ_MBOX0      = CVMX_IRQ_GPIO0 + 16,
+    /* 3  UART interrupts. */
+    CVMX_IRQ_UART0      = CVMX_IRQ_MBOX0 + 4,
+    CVMX_IRQ_PCI_INT0   = CVMX_IRQ_UART0 + 3,
+    CVMX_IRQ_PCI_INT1,
+    CVMX_IRQ_PCI_INT2,
+    CVMX_IRQ_PCI_INT3,
+    CVMX_IRQ_PCI_MSI0,
+    CVMX_IRQ_PCI_MSI1,
+    CVMX_IRQ_PCI_MSI2,
+    CVMX_IRQ_PCI_MSI3,
+    /* 2 TWSI interrupts */
+    CVMX_IRQ_TWSI0,
+    CVMX_IRQ_RML        = CVMX_IRQ_TWSI0 + 2,
+    /* 4 TRACE interrupts added in CN68XX */
+    CVMX_IRQ_TRACE0,
+    /* 5 GMX_DRP interrupts added in CN68XX */
+    CVMX_IRQ_GMX_DRP0 = CVMX_IRQ_TRACE0 + 4,
+    CVMX_IRQ_GMX_DRP1,   /* Doesn't apply on CN52XX or CN63XX */
+    CVMX_IRQ_IPD_DRP = CVMX_IRQ_GMX_DRP0 + 5,
+    CVMX_IRQ_KEY_ZERO,   /* Doesn't apply on CN52XX or CN63XX */
+    /* 4 TIMER interrupts. */
+    CVMX_IRQ_TIMER0,
+    /* 2 USB interrupts. */
+    CVMX_IRQ_USB0       = CVMX_IRQ_TIMER0 + 4,   /* Doesn't apply on CN38XX or CN58XX */
+    CVMX_IRQ_PCM        = CVMX_IRQ_USB0 + 2,   /* Doesn't apply on CN52XX or CN63XX */
+    CVMX_IRQ_MPI,   /* Doesn't apply on CN52XX or CN63XX */
+    CVMX_IRQ_POWIQ,   /* Added in CN56XX */
+    CVMX_IRQ_IPDPPTHR,   /* Added in CN56XX */
+    /* 2 MII interrupts. */
+    CVMX_IRQ_MII0,   /* Added in CN56XX */
+    CVMX_IRQ_BOOTDMA    = CVMX_IRQ_MII0 + 2,   /* Added in CN56XX */
+
+    /* 32 WDOG interrupts. */
+    CVMX_IRQ_WDOG0,
+    CVMX_IRQ_NAND  = CVMX_IRQ_WDOG0 + 32,           /* Added in CN52XX */
+    CVMX_IRQ_MIO,           /* Added in CN63XX */
+    CVMX_IRQ_IOB,           /* Added in CN63XX */
+    CVMX_IRQ_FPA,           /* Added in CN63XX */
+    CVMX_IRQ_POW,           /* Added in CN63XX */
+    CVMX_IRQ_L2C,           /* Added in CN63XX */
+    CVMX_IRQ_IPD,           /* Added in CN63XX */
+    CVMX_IRQ_PIP,           /* Added in CN63XX */
+    CVMX_IRQ_PKO,           /* Added in CN63XX */
+    CVMX_IRQ_ZIP,          /* Added in CN63XX */
+    CVMX_IRQ_TIM,          /* Added in CN63XX */
+    CVMX_IRQ_RAD,          /* Added in CN63XX */
+    CVMX_IRQ_KEY,          /* Added in CN63XX */
+    CVMX_IRQ_DFA,          /* Added in CN63XX */
+    CVMX_IRQ_USBCTL,          /* Added in CN63XX */
+    CVMX_IRQ_SLI,          /* Added in CN63XX */
+    CVMX_IRQ_DPI,          /* Added in CN63XX */
+    /* 5 AGX interrupts added in CN68XX. */
+    CVMX_IRQ_AGX0,          /* Added in CN63XX */
+
+    CVMX_IRQ_AGL = CVMX_IRQ_AGX0 + 5,          /* Added in CN63XX */
+    CVMX_IRQ_PTP,          /* Added in CN63XX */
+    CVMX_IRQ_PEM0,          /* Added in CN63XX */
+    CVMX_IRQ_PEM1,          /* Added in CN63XX */
+    CVMX_IRQ_SRIO0,          /* Added in CN63XX */
+    CVMX_IRQ_SRIO1,          /* Added in CN63XX */
+    CVMX_IRQ_LMC0,          /* Added in CN63XX */
+    /* 4 LMC interrupts added in CN68XX. */
+    CVMX_IRQ_DFM = CVMX_IRQ_LMC0 + 4,          /* Added in CN63XX */
+    CVMX_IRQ_RST,          /* Added in CN63XX */
+    CVMX_IRQ_ILK,         /* Added for CN68XX */
+    CVMX_IRQ_SRIO2,       /* Added in CN66XX */
+    CVMX_IRQ_DPI_DMA,     /* Added in CN61XX */
+    /* 6 addition timers added in CN61XX */
+    CVMX_IRQ_TIMER4,      /* Added in CN61XX */
+    CVMX_IRQ_MAX = CVMX_IRQ_TIMER4 + 6          /* One greater than the last valid number.*/
 } cvmx_irq_t;
 
 /**
  * Function prototype for the exception handler
  */
-typedef void (*cvmx_interrupt_exception_t)(uint64_t registers[32]);
+typedef void (*cvmx_interrupt_exception_t)(uint64_t *registers);
 
 /**
  * Function prototype for interrupt handlers
  */
-typedef void (*cvmx_interrupt_func_t)(int irq_number, uint64_t registers[32], void *user_arg);
+typedef void (*cvmx_interrupt_func_t)(int irq_number, uint64_t *registers, void *user_arg);
 
 /**
  * Register an interrupt handler for the specified interrupt number.
@@ -206,7 +166,7 @@ typedef void (*cvmx_interrupt_func_t)(int irq_number, uint64_t registers[32], vo
  * @param func       Function to call on interrupt.
  * @param user_arg   User data to pass to the interrupt handler
  */
-void cvmx_interrupt_register(cvmx_irq_t irq_number, cvmx_interrupt_func_t func, void *user_arg);
+void cvmx_interrupt_register(int irq_number, cvmx_interrupt_func_t func, void *user_arg);
 
 /**
  * Set the exception handler for all non interrupt sources.
@@ -216,74 +176,21 @@ void cvmx_interrupt_register(cvmx_irq_t irq_number, cvmx_interrupt_func_t func,
  */
 cvmx_interrupt_exception_t cvmx_interrupt_set_exception(cvmx_interrupt_exception_t handler);
 
+
 /**
  * Masks a given interrupt number.
- * EN0 sources are masked on IP2
- * EN1 sources are masked on IP3
  *
- * @param irq_number interrupt number to mask (0-135)
+ * @param irq_number interrupt number to mask
  */
-static inline void cvmx_interrupt_mask_irq(int irq_number)
-{
-    if (irq_number<8)
-    {
-        uint32_t mask;
-        asm volatile ("mfc0 %0,$12,0" : "=r" (mask));
-        mask &= ~(1<< (8 + irq_number));
-        asm volatile ("mtc0 %0,$12,0" : : "r" (mask));
-    }
-    else if (irq_number < 8 + 64)
-    {
-        int ciu_bit = (irq_number - 8) & 63;
-        int ciu_offset = cvmx_get_core_num() * 2;
-        uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(ciu_offset));
-        mask &= ~(1ull << ciu_bit);
-        cvmx_write_csr(CVMX_CIU_INTX_EN0(ciu_offset), mask);
-    }
-    else
-    {
-        int ciu_bit = (irq_number - 8) & 63;
-        int ciu_offset = cvmx_get_core_num() * 2 + 1;
-        uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(ciu_offset));
-        mask &= ~(1ull << ciu_bit);
-        cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), mask);
-    }
-}
+extern void (*cvmx_interrupt_mask_irq)(int irq_number);
 
 
 /**
  * Unmasks a given interrupt number
- * EN0 sources are unmasked on IP2
- * EN1 sources are unmasked on IP3
  *
- * @param irq_number interrupt number to unmask (0-135)
+ * @param irq_number interrupt number to unmask
  */
-static inline void cvmx_interrupt_unmask_irq(int irq_number)
-{
-    if (irq_number<8)
-    {
-        uint32_t mask;
-        asm volatile ("mfc0 %0,$12,0" : "=r" (mask));
-        mask |= (1<< (8 + irq_number));
-        asm volatile ("mtc0 %0,$12,0" : : "r" (mask));
-    }
-    else if (irq_number < 8 + 64)
-    {
-        int ciu_bit = (irq_number - 8) & 63;
-        int ciu_offset = cvmx_get_core_num() * 2;
-        uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(ciu_offset));
-        mask |= (1ull << ciu_bit);
-        cvmx_write_csr(CVMX_CIU_INTX_EN0(ciu_offset), mask);
-    }
-    else
-    {
-        int ciu_bit = (irq_number - 8) & 63;
-        int ciu_offset = cvmx_get_core_num() * 2 + 1;
-        uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(ciu_offset));
-        mask |= (1ull << ciu_bit);
-        cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), mask);
-    }
-}
+extern void (*cvmx_interrupt_unmask_irq)(int irq_number);
 
 
 /* Disable interrupts by clearing bit 0 of the COP0 status register,
@@ -318,16 +225,16 @@ static inline void cvmx_interrupt_restore(uint32_t flags)
  * Utility function to do interrupt safe printf
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-	#define cvmx_safe_printf printk
+        #define cvmx_safe_printf printk
 #elif defined(CVMX_BUILD_FOR_LINUX_USER)
-	#define cvmx_safe_printf printf
+        #define cvmx_safe_printf printf
 #else
-	extern void cvmx_safe_printf(const char* format, ... ) __attribute__ ((format(printf, 1, 2)));
+        extern void cvmx_safe_printf(const char* format, ... ) __attribute__ ((format(printf, 1, 2)));
 #endif
 
 #define PRINT_ERROR(format, ...) cvmx_safe_printf("ERROR " format, ##__VA_ARGS__)
 
-#ifdef	__cplusplus
+#ifdef  __cplusplus
 }
 #endif
 
diff --git a/sys/contrib/octeon-sdk/cvmx-iob-defs.h b/sys/contrib/octeon-sdk/cvmx-iob-defs.h
index bb669f8..f1eb34c 100644
--- a/sys/contrib/octeon-sdk/cvmx-iob-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-iob-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_IOB_TYPEDEFS_H__
-#define __CVMX_IOB_TYPEDEFS_H__
+#ifndef __CVMX_IOB_DEFS_H__
+#define __CVMX_IOB_DEFS_H__
 
 #define CVMX_IOB_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00007F8ull))
 #define CVMX_IOB_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0000050ull))
@@ -58,7 +58,7 @@
 #define CVMX_IOB_DWB_PRI_CNT CVMX_IOB_DWB_PRI_CNT_FUNC()
 static inline uint64_t CVMX_IOB_DWB_PRI_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_IOB_DWB_PRI_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800F0000028ull);
 }
@@ -70,7 +70,7 @@ static inline uint64_t CVMX_IOB_DWB_PRI_CNT_FUNC(void)
 #define CVMX_IOB_I2C_PRI_CNT CVMX_IOB_I2C_PRI_CNT_FUNC()
 static inline uint64_t CVMX_IOB_I2C_PRI_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_IOB_I2C_PRI_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800F0000010ull);
 }
@@ -87,7 +87,7 @@ static inline uint64_t CVMX_IOB_I2C_PRI_CNT_FUNC(void)
 #define CVMX_IOB_N2C_L2C_PRI_CNT CVMX_IOB_N2C_L2C_PRI_CNT_FUNC()
 static inline uint64_t CVMX_IOB_N2C_L2C_PRI_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_IOB_N2C_L2C_PRI_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800F0000020ull);
 }
@@ -98,7 +98,7 @@ static inline uint64_t CVMX_IOB_N2C_L2C_PRI_CNT_FUNC(void)
 #define CVMX_IOB_N2C_RSP_PRI_CNT CVMX_IOB_N2C_RSP_PRI_CNT_FUNC()
 static inline uint64_t CVMX_IOB_N2C_RSP_PRI_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_IOB_N2C_RSP_PRI_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800F0000008ull);
 }
@@ -109,7 +109,7 @@ static inline uint64_t CVMX_IOB_N2C_RSP_PRI_CNT_FUNC(void)
 #define CVMX_IOB_OUTB_COM_PRI_CNT CVMX_IOB_OUTB_COM_PRI_CNT_FUNC()
 static inline uint64_t CVMX_IOB_OUTB_COM_PRI_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_IOB_OUTB_COM_PRI_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800F0000040ull);
 }
@@ -124,7 +124,7 @@ static inline uint64_t CVMX_IOB_OUTB_COM_PRI_CNT_FUNC(void)
 #define CVMX_IOB_OUTB_FPA_PRI_CNT CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC()
 static inline uint64_t CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_IOB_OUTB_FPA_PRI_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800F0000048ull);
 }
@@ -135,7 +135,7 @@ static inline uint64_t CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC(void)
 #define CVMX_IOB_OUTB_REQ_PRI_CNT CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC()
 static inline uint64_t CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_IOB_OUTB_REQ_PRI_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800F0000038ull);
 }
@@ -146,25 +146,156 @@ static inline uint64_t CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC(void)
 #define CVMX_IOB_P2C_REQ_PRI_CNT CVMX_IOB_P2C_REQ_PRI_CNT_FUNC()
 static inline uint64_t CVMX_IOB_P2C_REQ_PRI_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_IOB_P2C_REQ_PRI_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800F0000018ull);
 }
 #else
 #define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull))
 #endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_PKT_ERR CVMX_IOB_PKT_ERR_FUNC()
+static inline uint64_t CVMX_IOB_PKT_ERR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_IOB_PKT_ERR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0000068ull);
+}
+#else
 #define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull))
+#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_IOB_TO_CMB_CREDITS CVMX_IOB_TO_CMB_CREDITS_FUNC()
 static inline uint64_t CVMX_IOB_TO_CMB_CREDITS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_IOB_TO_CMB_CREDITS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800F00000B0ull);
 }
 #else
 #define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull))
 #endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_TO_NCB_DID_00_CREDITS CVMX_IOB_TO_NCB_DID_00_CREDITS_FUNC()
+static inline uint64_t CVMX_IOB_TO_NCB_DID_00_CREDITS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IOB_TO_NCB_DID_00_CREDITS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0000800ull);
+}
+#else
+#define CVMX_IOB_TO_NCB_DID_00_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000800ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_TO_NCB_DID_111_CREDITS CVMX_IOB_TO_NCB_DID_111_CREDITS_FUNC()
+static inline uint64_t CVMX_IOB_TO_NCB_DID_111_CREDITS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IOB_TO_NCB_DID_111_CREDITS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0000B78ull);
+}
+#else
+#define CVMX_IOB_TO_NCB_DID_111_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B78ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_TO_NCB_DID_223_CREDITS CVMX_IOB_TO_NCB_DID_223_CREDITS_FUNC()
+static inline uint64_t CVMX_IOB_TO_NCB_DID_223_CREDITS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IOB_TO_NCB_DID_223_CREDITS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0000EF8ull);
+}
+#else
+#define CVMX_IOB_TO_NCB_DID_223_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000EF8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_TO_NCB_DID_24_CREDITS CVMX_IOB_TO_NCB_DID_24_CREDITS_FUNC()
+static inline uint64_t CVMX_IOB_TO_NCB_DID_24_CREDITS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IOB_TO_NCB_DID_24_CREDITS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F00008C0ull);
+}
+#else
+#define CVMX_IOB_TO_NCB_DID_24_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00008C0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_TO_NCB_DID_32_CREDITS CVMX_IOB_TO_NCB_DID_32_CREDITS_FUNC()
+static inline uint64_t CVMX_IOB_TO_NCB_DID_32_CREDITS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IOB_TO_NCB_DID_32_CREDITS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0000900ull);
+}
+#else
+#define CVMX_IOB_TO_NCB_DID_32_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000900ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_TO_NCB_DID_40_CREDITS CVMX_IOB_TO_NCB_DID_40_CREDITS_FUNC()
+static inline uint64_t CVMX_IOB_TO_NCB_DID_40_CREDITS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IOB_TO_NCB_DID_40_CREDITS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0000940ull);
+}
+#else
+#define CVMX_IOB_TO_NCB_DID_40_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000940ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_TO_NCB_DID_55_CREDITS CVMX_IOB_TO_NCB_DID_55_CREDITS_FUNC()
+static inline uint64_t CVMX_IOB_TO_NCB_DID_55_CREDITS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IOB_TO_NCB_DID_55_CREDITS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F00009B8ull);
+}
+#else
+#define CVMX_IOB_TO_NCB_DID_55_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00009B8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_TO_NCB_DID_64_CREDITS CVMX_IOB_TO_NCB_DID_64_CREDITS_FUNC()
+static inline uint64_t CVMX_IOB_TO_NCB_DID_64_CREDITS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IOB_TO_NCB_DID_64_CREDITS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0000A00ull);
+}
+#else
+#define CVMX_IOB_TO_NCB_DID_64_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A00ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_TO_NCB_DID_79_CREDITS CVMX_IOB_TO_NCB_DID_79_CREDITS_FUNC()
+static inline uint64_t CVMX_IOB_TO_NCB_DID_79_CREDITS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IOB_TO_NCB_DID_79_CREDITS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0000A78ull);
+}
+#else
+#define CVMX_IOB_TO_NCB_DID_79_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A78ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_TO_NCB_DID_96_CREDITS CVMX_IOB_TO_NCB_DID_96_CREDITS_FUNC()
+static inline uint64_t CVMX_IOB_TO_NCB_DID_96_CREDITS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IOB_TO_NCB_DID_96_CREDITS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0000B00ull);
+}
+#else
+#define CVMX_IOB_TO_NCB_DID_96_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B00ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_TO_NCB_DID_98_CREDITS CVMX_IOB_TO_NCB_DID_98_CREDITS_FUNC()
+static inline uint64_t CVMX_IOB_TO_NCB_DID_98_CREDITS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IOB_TO_NCB_DID_98_CREDITS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0000B10ull);
+}
+#else
+#define CVMX_IOB_TO_NCB_DID_98_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B10ull))
+#endif
 
 /**
  * cvmx_iob_bist_status
@@ -173,12 +304,74 @@ static inline uint64_t CVMX_IOB_TO_CMB_CREDITS_FUNC(void)
  *
  * The result of the BIST run on the IOB memories.
  */
-union cvmx_iob_bist_status
-{
+union cvmx_iob_bist_status {
 	uint64_t u64;
-	struct cvmx_iob_bist_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_2_63                : 62;
+	uint64_t ibd                          : 1;  /**< ibd_bist_mem0_status */
+	uint64_t icd                          : 1;  /**< icd_ncb_fifo_bist_status */
+#else
+	uint64_t icd                          : 1;
+	uint64_t ibd                          : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_iob_bist_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_18_63               : 46;
+	uint64_t icnrcb                       : 1;  /**< Reserved */
+	uint64_t icr0                         : 1;  /**< Reserved */
+	uint64_t icr1                         : 1;  /**< Reserved */
+	uint64_t icnr1                        : 1;  /**< Reserved */
+	uint64_t icnr0                        : 1;  /**< icnr_reg_mem0_bist_status */
+	uint64_t ibdr0                        : 1;  /**< ibdr_bist_req_fifo0_status */
+	uint64_t ibdr1                        : 1;  /**< ibdr_bist_req_fifo1_status */
+	uint64_t ibr0                         : 1;  /**< ibr_bist_rsp_fifo0_status */
+	uint64_t ibr1                         : 1;  /**< ibr_bist_rsp_fifo1_status */
+	uint64_t icnrt                        : 1;  /**< Reserved */
+	uint64_t ibrq0                        : 1;  /**< ibrq_bist_req_fifo0_status */
+	uint64_t ibrq1                        : 1;  /**< ibrq_bist_req_fifo1_status */
+	uint64_t icrn0                        : 1;  /**< icr_ncb_bist_mem0_status */
+	uint64_t icrn1                        : 1;  /**< icr_ncb_bist_mem1_status */
+	uint64_t icrp0                        : 1;  /**< icr_pko_bist_mem0_status */
+	uint64_t icrp1                        : 1;  /**< icr_pko_bist_mem1_status */
+	uint64_t ibd                          : 1;  /**< ibd_bist_mem0_status */
+	uint64_t icd                          : 1;  /**< icd_ncb_fifo_bist_status */
+#else
+	uint64_t icd                          : 1;
+	uint64_t ibd                          : 1;
+	uint64_t icrp1                        : 1;
+	uint64_t icrp0                        : 1;
+	uint64_t icrn1                        : 1;
+	uint64_t icrn0                        : 1;
+	uint64_t ibrq1                        : 1;
+	uint64_t ibrq0                        : 1;
+	uint64_t icnrt                        : 1;
+	uint64_t ibr1                         : 1;
+	uint64_t ibr0                         : 1;
+	uint64_t ibdr1                        : 1;
+	uint64_t ibdr0                        : 1;
+	uint64_t icnr0                        : 1;
+	uint64_t icnr1                        : 1;
+	uint64_t icr1                         : 1;
+	uint64_t icr0                         : 1;
+	uint64_t icnrcb                       : 1;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} cn30xx;
+	struct cvmx_iob_bist_status_cn30xx    cn31xx;
+	struct cvmx_iob_bist_status_cn30xx    cn38xx;
+	struct cvmx_iob_bist_status_cn30xx    cn38xxp2;
+	struct cvmx_iob_bist_status_cn30xx    cn50xx;
+	struct cvmx_iob_bist_status_cn30xx    cn52xx;
+	struct cvmx_iob_bist_status_cn30xx    cn52xxp1;
+	struct cvmx_iob_bist_status_cn30xx    cn56xx;
+	struct cvmx_iob_bist_status_cn30xx    cn56xxp1;
+	struct cvmx_iob_bist_status_cn30xx    cn58xx;
+	struct cvmx_iob_bist_status_cn30xx    cn58xxp1;
+	struct cvmx_iob_bist_status_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_23_63               : 41;
 	uint64_t xmdfif                       : 1;  /**< xmdfif_bist_status */
 	uint64_t xmcfif                       : 1;  /**< xmcfif_bist_status */
@@ -229,34 +422,34 @@ union cvmx_iob_bist_status
 	uint64_t xmdfif                       : 1;
 	uint64_t reserved_23_63               : 41;
 #endif
-	} s;
-	struct cvmx_iob_bist_status_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	} cn61xx;
+	struct cvmx_iob_bist_status_cn61xx    cn63xx;
+	struct cvmx_iob_bist_status_cn61xx    cn63xxp1;
+	struct cvmx_iob_bist_status_cn61xx    cn66xx;
+	struct cvmx_iob_bist_status_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
-	uint64_t icnrcb                       : 1;  /**< Reserved */
-	uint64_t icr0                         : 1;  /**< Reserved */
-	uint64_t icr1                         : 1;  /**< Reserved */
-	uint64_t icnr1                        : 1;  /**< Reserved */
+	uint64_t xmdfif                       : 1;  /**< xmdfif_bist_status */
+	uint64_t xmcfif                       : 1;  /**< xmcfif_bist_status */
+	uint64_t iorfif                       : 1;  /**< iorfif_bist_status */
+	uint64_t rsdfif                       : 1;  /**< rsdfif_bist_status */
+	uint64_t iocfif                       : 1;  /**< iocfif_bist_status */
+	uint64_t icnrcb                       : 1;  /**< icnr_cb_reg_fifo_bist_status */
+	uint64_t icr0                         : 1;  /**< icr_bist_req_fifo0_status */
+	uint64_t icr1                         : 1;  /**< icr_bist_req_fifo1_status */
 	uint64_t icnr0                        : 1;  /**< icnr_reg_mem0_bist_status */
-	uint64_t ibdr0                        : 1;  /**< ibdr_bist_req_fifo0_status */
-	uint64_t ibdr1                        : 1;  /**< ibdr_bist_req_fifo1_status */
 	uint64_t ibr0                         : 1;  /**< ibr_bist_rsp_fifo0_status */
 	uint64_t ibr1                         : 1;  /**< ibr_bist_rsp_fifo1_status */
-	uint64_t icnrt                        : 1;  /**< Reserved */
+	uint64_t icnrt                        : 1;  /**< icnr_tag_cb_reg_fifo_bist_status */
 	uint64_t ibrq0                        : 1;  /**< ibrq_bist_req_fifo0_status */
 	uint64_t ibrq1                        : 1;  /**< ibrq_bist_req_fifo1_status */
 	uint64_t icrn0                        : 1;  /**< icr_ncb_bist_mem0_status */
 	uint64_t icrn1                        : 1;  /**< icr_ncb_bist_mem1_status */
-	uint64_t icrp0                        : 1;  /**< icr_pko_bist_mem0_status */
-	uint64_t icrp1                        : 1;  /**< icr_pko_bist_mem1_status */
 	uint64_t ibd                          : 1;  /**< ibd_bist_mem0_status */
 	uint64_t icd                          : 1;  /**< icd_ncb_fifo_bist_status */
 #else
 	uint64_t icd                          : 1;
 	uint64_t ibd                          : 1;
-	uint64_t icrp1                        : 1;
-	uint64_t icrp0                        : 1;
 	uint64_t icrn1                        : 1;
 	uint64_t icrn0                        : 1;
 	uint64_t ibrq1                        : 1;
@@ -264,28 +457,20 @@ union cvmx_iob_bist_status
 	uint64_t icnrt                        : 1;
 	uint64_t ibr1                         : 1;
 	uint64_t ibr0                         : 1;
-	uint64_t ibdr1                        : 1;
-	uint64_t ibdr0                        : 1;
 	uint64_t icnr0                        : 1;
-	uint64_t icnr1                        : 1;
 	uint64_t icr1                         : 1;
 	uint64_t icr0                         : 1;
 	uint64_t icnrcb                       : 1;
+	uint64_t iocfif                       : 1;
+	uint64_t rsdfif                       : 1;
+	uint64_t iorfif                       : 1;
+	uint64_t xmcfif                       : 1;
+	uint64_t xmdfif                       : 1;
 	uint64_t reserved_18_63               : 46;
 #endif
-	} cn30xx;
-	struct cvmx_iob_bist_status_cn30xx    cn31xx;
-	struct cvmx_iob_bist_status_cn30xx    cn38xx;
-	struct cvmx_iob_bist_status_cn30xx    cn38xxp2;
-	struct cvmx_iob_bist_status_cn30xx    cn50xx;
-	struct cvmx_iob_bist_status_cn30xx    cn52xx;
-	struct cvmx_iob_bist_status_cn30xx    cn52xxp1;
-	struct cvmx_iob_bist_status_cn30xx    cn56xx;
-	struct cvmx_iob_bist_status_cn30xx    cn56xxp1;
-	struct cvmx_iob_bist_status_cn30xx    cn58xx;
-	struct cvmx_iob_bist_status_cn30xx    cn58xxp1;
-	struct cvmx_iob_bist_status_s         cn63xx;
-	struct cvmx_iob_bist_status_s         cn63xxp1;
+	} cn68xx;
+	struct cvmx_iob_bist_status_cn68xx    cn68xxp1;
+	struct cvmx_iob_bist_status_cn61xx    cnf71xx;
 };
 typedef union cvmx_iob_bist_status cvmx_iob_bist_status_t;
 
@@ -296,16 +481,16 @@ typedef union cvmx_iob_bist_status cvmx_iob_bist_status_t;
  *
  * Provides control for IOB functions.
  */
-union cvmx_iob_ctl_status
-{
+union cvmx_iob_ctl_status {
 	uint64_t u64;
-	struct cvmx_iob_ctl_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_10_63               : 54;
+	struct cvmx_iob_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_11_63               : 53;
+	uint64_t fif_dly                      : 1;  /**< Delay async FIFO counts to be used when clock ratio
+                                                         is greater then 3:1. Writes should be followed by an
+                                                         immediate read. */
 	uint64_t xmc_per                      : 4;  /**< IBC XMC PUSH EARLY */
-	uint64_t rr_mode                      : 1;  /**< When set to '1' will enable Round-Robin mode of next
-                                                         transaction that could arbitrate for the XMB. */
+	uint64_t reserved_5_5                 : 1;
 	uint64_t outb_mat                     : 1;  /**< Was a match on the outbound bus to the inb pattern
                                                          matchers. PASS2 FIELD. */
 	uint64_t inb_mat                      : 1;  /**< Was a match on the inbound bus to the inb pattern
@@ -321,14 +506,14 @@ union cvmx_iob_ctl_status
 	uint64_t pko_enb                      : 1;
 	uint64_t inb_mat                      : 1;
 	uint64_t outb_mat                     : 1;
-	uint64_t rr_mode                      : 1;
+	uint64_t reserved_5_5                 : 1;
 	uint64_t xmc_per                      : 4;
-	uint64_t reserved_10_63               : 54;
+	uint64_t fif_dly                      : 1;
+	uint64_t reserved_11_63               : 53;
 #endif
 	} s;
-	struct cvmx_iob_ctl_status_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_ctl_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t outb_mat                     : 1;  /**< Was a match on the outbound bus to the inb pattern
                                                          matchers. */
@@ -352,9 +537,8 @@ union cvmx_iob_ctl_status
 	struct cvmx_iob_ctl_status_cn30xx     cn38xx;
 	struct cvmx_iob_ctl_status_cn30xx     cn38xxp2;
 	struct cvmx_iob_ctl_status_cn30xx     cn50xx;
-	struct cvmx_iob_ctl_status_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_ctl_status_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t rr_mode                      : 1;  /**< When set to '1' will enable Round-Robin mode of next
                                                          transaction that could arbitrate for the XMB. */
@@ -382,8 +566,95 @@ union cvmx_iob_ctl_status
 	struct cvmx_iob_ctl_status_cn30xx     cn56xxp1;
 	struct cvmx_iob_ctl_status_cn30xx     cn58xx;
 	struct cvmx_iob_ctl_status_cn30xx     cn58xxp1;
-	struct cvmx_iob_ctl_status_s          cn63xx;
-	struct cvmx_iob_ctl_status_s          cn63xxp1;
+	struct cvmx_iob_ctl_status_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_11_63               : 53;
+	uint64_t fif_dly                      : 1;  /**< Delay async FIFO counts to be used when clock ratio
+                                                         is greater then 3:1. Writes should be followed by an
+                                                         immediate read. */
+	uint64_t xmc_per                      : 4;  /**< IBC XMC PUSH EARLY */
+	uint64_t rr_mode                      : 1;  /**< When set to '1' will enable Round-Robin mode of next
+                                                         transaction that could arbitrate for the XMB. */
+	uint64_t outb_mat                     : 1;  /**< Was a match on the outbound bus to the inb pattern
+                                                         matchers. PASS2 FIELD. */
+	uint64_t inb_mat                      : 1;  /**< Was a match on the inbound bus to the inb pattern
+                                                         matchers. PASS2 FIELD. */
+	uint64_t pko_enb                      : 1;  /**< Toggles the endian style of the FAU for the PKO.
+                                                         '0' is for big-endian and '1' is for little-endian. */
+	uint64_t dwb_enb                      : 1;  /**< Enables the DWB function of the IOB. */
+	uint64_t fau_end                      : 1;  /**< Toggles the endian style of the FAU. '0' is for
+                                                         big-endian and '1' is for little-endian. */
+#else
+	uint64_t fau_end                      : 1;
+	uint64_t dwb_enb                      : 1;
+	uint64_t pko_enb                      : 1;
+	uint64_t inb_mat                      : 1;
+	uint64_t outb_mat                     : 1;
+	uint64_t rr_mode                      : 1;
+	uint64_t xmc_per                      : 4;
+	uint64_t fif_dly                      : 1;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} cn61xx;
+	struct cvmx_iob_ctl_status_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t xmc_per                      : 4;  /**< IBC XMC PUSH EARLY */
+	uint64_t rr_mode                      : 1;  /**< When set to '1' will enable Round-Robin mode of next
+                                                         transaction that could arbitrate for the XMB. */
+	uint64_t outb_mat                     : 1;  /**< Was a match on the outbound bus to the inb pattern
+                                                         matchers. PASS2 FIELD. */
+	uint64_t inb_mat                      : 1;  /**< Was a match on the inbound bus to the inb pattern
+                                                         matchers. PASS2 FIELD. */
+	uint64_t pko_enb                      : 1;  /**< Toggles the endian style of the FAU for the PKO.
+                                                         '0' is for big-endian and '1' is for little-endian. */
+	uint64_t dwb_enb                      : 1;  /**< Enables the DWB function of the IOB. */
+	uint64_t fau_end                      : 1;  /**< Toggles the endian style of the FAU. '0' is for
+                                                         big-endian and '1' is for little-endian. */
+#else
+	uint64_t fau_end                      : 1;
+	uint64_t dwb_enb                      : 1;
+	uint64_t pko_enb                      : 1;
+	uint64_t inb_mat                      : 1;
+	uint64_t outb_mat                     : 1;
+	uint64_t rr_mode                      : 1;
+	uint64_t xmc_per                      : 4;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn63xx;
+	struct cvmx_iob_ctl_status_cn63xx     cn63xxp1;
+	struct cvmx_iob_ctl_status_cn61xx     cn66xx;
+	struct cvmx_iob_ctl_status_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_11_63               : 53;
+	uint64_t fif_dly                      : 1;  /**< Delay async FIFO counts to be used when clock ratio
+                                                         is greater then 3:1. Writes should be followed by an
+                                                         immediate read. */
+	uint64_t xmc_per                      : 4;  /**< IBC XMC PUSH EARLY */
+	uint64_t rsvr5                        : 1;  /**< Reserved */
+	uint64_t outb_mat                     : 1;  /**< Was a match on the outbound bus to the inb pattern
+                                                         matchers. */
+	uint64_t inb_mat                      : 1;  /**< Was a match on the inbound bus to the inb pattern
+                                                         matchers. */
+	uint64_t pko_enb                      : 1;  /**< Toggles the endian style of the FAU for the PKO.
+                                                         '0' is for big-endian and '1' is for little-endian. */
+	uint64_t dwb_enb                      : 1;  /**< Enables the DWB function of the IOB. */
+	uint64_t fau_end                      : 1;  /**< Toggles the endian style of the FAU. '0' is for
+                                                         big-endian and '1' is for little-endian. */
+#else
+	uint64_t fau_end                      : 1;
+	uint64_t dwb_enb                      : 1;
+	uint64_t pko_enb                      : 1;
+	uint64_t inb_mat                      : 1;
+	uint64_t outb_mat                     : 1;
+	uint64_t rsvr5                        : 1;
+	uint64_t xmc_per                      : 4;
+	uint64_t fif_dly                      : 1;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} cn68xx;
+	struct cvmx_iob_ctl_status_cn68xx     cn68xxp1;
+	struct cvmx_iob_ctl_status_cn61xx     cnf71xx;
 };
 typedef union cvmx_iob_ctl_status cvmx_iob_ctl_status_t;
 
@@ -394,12 +665,10 @@ typedef union cvmx_iob_ctl_status cvmx_iob_ctl_status_t;
  *
  * Enables and supplies the timeout count for raising the priority of Don't Write Back request to the L2C.
  */
-union cvmx_iob_dwb_pri_cnt
-{
+union cvmx_iob_dwb_pri_cnt {
 	uint64_t u64;
-	struct cvmx_iob_dwb_pri_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_dwb_pri_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t cnt_enb                      : 1;  /**< Enables the raising of CMB access priority
                                                          when CNT_VAL is reached. */
@@ -419,8 +688,11 @@ union cvmx_iob_dwb_pri_cnt
 	struct cvmx_iob_dwb_pri_cnt_s         cn56xxp1;
 	struct cvmx_iob_dwb_pri_cnt_s         cn58xx;
 	struct cvmx_iob_dwb_pri_cnt_s         cn58xxp1;
+	struct cvmx_iob_dwb_pri_cnt_s         cn61xx;
 	struct cvmx_iob_dwb_pri_cnt_s         cn63xx;
 	struct cvmx_iob_dwb_pri_cnt_s         cn63xxp1;
+	struct cvmx_iob_dwb_pri_cnt_s         cn66xx;
+	struct cvmx_iob_dwb_pri_cnt_s         cnf71xx;
 };
 typedef union cvmx_iob_dwb_pri_cnt cvmx_iob_dwb_pri_cnt_t;
 
@@ -432,12 +704,10 @@ typedef union cvmx_iob_dwb_pri_cnt cvmx_iob_dwb_pri_cnt_t;
  * How many clokc ticks the FAU unit will wait for a tag-switch before timeing out.
  * for Queue 0.
  */
-union cvmx_iob_fau_timeout
-{
+union cvmx_iob_fau_timeout {
 	uint64_t u64;
-	struct cvmx_iob_fau_timeout_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_fau_timeout_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t tout_enb                     : 1;  /**< The enable for the FAU timeout feature.
                                                          '1' will enable the timeout, '0' will disable. */
@@ -468,8 +738,13 @@ union cvmx_iob_fau_timeout
 	struct cvmx_iob_fau_timeout_s         cn56xxp1;
 	struct cvmx_iob_fau_timeout_s         cn58xx;
 	struct cvmx_iob_fau_timeout_s         cn58xxp1;
+	struct cvmx_iob_fau_timeout_s         cn61xx;
 	struct cvmx_iob_fau_timeout_s         cn63xx;
 	struct cvmx_iob_fau_timeout_s         cn63xxp1;
+	struct cvmx_iob_fau_timeout_s         cn66xx;
+	struct cvmx_iob_fau_timeout_s         cn68xx;
+	struct cvmx_iob_fau_timeout_s         cn68xxp1;
+	struct cvmx_iob_fau_timeout_s         cnf71xx;
 };
 typedef union cvmx_iob_fau_timeout cvmx_iob_fau_timeout_t;
 
@@ -480,12 +755,10 @@ typedef union cvmx_iob_fau_timeout cvmx_iob_fau_timeout_t;
  *
  * Enables and supplies the timeout count for raising the priority of IPD Store access to the CMB.
  */
-union cvmx_iob_i2c_pri_cnt
-{
+union cvmx_iob_i2c_pri_cnt {
 	uint64_t u64;
-	struct cvmx_iob_i2c_pri_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_i2c_pri_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t cnt_enb                      : 1;  /**< Enables the raising of CMB access priority
                                                          when CNT_VAL is reached. */
@@ -505,8 +778,11 @@ union cvmx_iob_i2c_pri_cnt
 	struct cvmx_iob_i2c_pri_cnt_s         cn56xxp1;
 	struct cvmx_iob_i2c_pri_cnt_s         cn58xx;
 	struct cvmx_iob_i2c_pri_cnt_s         cn58xxp1;
+	struct cvmx_iob_i2c_pri_cnt_s         cn61xx;
 	struct cvmx_iob_i2c_pri_cnt_s         cn63xx;
 	struct cvmx_iob_i2c_pri_cnt_s         cn63xxp1;
+	struct cvmx_iob_i2c_pri_cnt_s         cn66xx;
+	struct cvmx_iob_i2c_pri_cnt_s         cnf71xx;
 };
 typedef union cvmx_iob_i2c_pri_cnt cvmx_iob_i2c_pri_cnt_t;
 
@@ -517,12 +793,10 @@ typedef union cvmx_iob_i2c_pri_cnt cvmx_iob_i2c_pri_cnt_t;
  *
  * Match pattern for the inbound control to set the INB_MATCH_BIT. PASS-2 Register
  */
-union cvmx_iob_inb_control_match
-{
+union cvmx_iob_inb_control_match {
 	uint64_t u64;
-	struct cvmx_iob_inb_control_match_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_inb_control_match_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t mask                         : 8;  /**< Pattern to match on the inbound NCB. */
 	uint64_t opc                          : 4;  /**< Pattern to match on the inbound NCB. */
@@ -547,8 +821,13 @@ union cvmx_iob_inb_control_match
 	struct cvmx_iob_inb_control_match_s   cn56xxp1;
 	struct cvmx_iob_inb_control_match_s   cn58xx;
 	struct cvmx_iob_inb_control_match_s   cn58xxp1;
+	struct cvmx_iob_inb_control_match_s   cn61xx;
 	struct cvmx_iob_inb_control_match_s   cn63xx;
 	struct cvmx_iob_inb_control_match_s   cn63xxp1;
+	struct cvmx_iob_inb_control_match_s   cn66xx;
+	struct cvmx_iob_inb_control_match_s   cn68xx;
+	struct cvmx_iob_inb_control_match_s   cn68xxp1;
+	struct cvmx_iob_inb_control_match_s   cnf71xx;
 };
 typedef union cvmx_iob_inb_control_match cvmx_iob_inb_control_match_t;
 
@@ -559,12 +838,10 @@ typedef union cvmx_iob_inb_control_match cvmx_iob_inb_control_match_t;
  *
  * Enables the match of the corresponding bit in the IOB_INB_CONTROL_MATCH reister. PASS-2 Register
  */
-union cvmx_iob_inb_control_match_enb
-{
+union cvmx_iob_inb_control_match_enb {
 	uint64_t u64;
-	struct cvmx_iob_inb_control_match_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_inb_control_match_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t mask                         : 8;  /**< Pattern to match on the inbound NCB. */
 	uint64_t opc                          : 4;  /**< Pattern to match on the inbound NCB. */
@@ -589,8 +866,13 @@ union cvmx_iob_inb_control_match_enb
 	struct cvmx_iob_inb_control_match_enb_s cn56xxp1;
 	struct cvmx_iob_inb_control_match_enb_s cn58xx;
 	struct cvmx_iob_inb_control_match_enb_s cn58xxp1;
+	struct cvmx_iob_inb_control_match_enb_s cn61xx;
 	struct cvmx_iob_inb_control_match_enb_s cn63xx;
 	struct cvmx_iob_inb_control_match_enb_s cn63xxp1;
+	struct cvmx_iob_inb_control_match_enb_s cn66xx;
+	struct cvmx_iob_inb_control_match_enb_s cn68xx;
+	struct cvmx_iob_inb_control_match_enb_s cn68xxp1;
+	struct cvmx_iob_inb_control_match_enb_s cnf71xx;
 };
 typedef union cvmx_iob_inb_control_match_enb cvmx_iob_inb_control_match_enb_t;
 
@@ -601,12 +883,10 @@ typedef union cvmx_iob_inb_control_match_enb cvmx_iob_inb_control_match_enb_t;
  *
  * Match pattern for the inbound data to set the INB_MATCH_BIT. PASS-2 Register
  */
-union cvmx_iob_inb_data_match
-{
+union cvmx_iob_inb_data_match {
 	uint64_t u64;
-	struct cvmx_iob_inb_data_match_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_inb_data_match_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 64; /**< Pattern to match on the inbound NCB. */
 #else
 	uint64_t data                         : 64;
@@ -623,8 +903,13 @@ union cvmx_iob_inb_data_match
 	struct cvmx_iob_inb_data_match_s      cn56xxp1;
 	struct cvmx_iob_inb_data_match_s      cn58xx;
 	struct cvmx_iob_inb_data_match_s      cn58xxp1;
+	struct cvmx_iob_inb_data_match_s      cn61xx;
 	struct cvmx_iob_inb_data_match_s      cn63xx;
 	struct cvmx_iob_inb_data_match_s      cn63xxp1;
+	struct cvmx_iob_inb_data_match_s      cn66xx;
+	struct cvmx_iob_inb_data_match_s      cn68xx;
+	struct cvmx_iob_inb_data_match_s      cn68xxp1;
+	struct cvmx_iob_inb_data_match_s      cnf71xx;
 };
 typedef union cvmx_iob_inb_data_match cvmx_iob_inb_data_match_t;
 
@@ -635,12 +920,10 @@ typedef union cvmx_iob_inb_data_match cvmx_iob_inb_data_match_t;
  *
  * Enables the match of the corresponding bit in the IOB_INB_DATA_MATCH reister. PASS-2 Register
  */
-union cvmx_iob_inb_data_match_enb
-{
+union cvmx_iob_inb_data_match_enb {
 	uint64_t u64;
-	struct cvmx_iob_inb_data_match_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_inb_data_match_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 64; /**< Bit to enable match of. */
 #else
 	uint64_t data                         : 64;
@@ -657,8 +940,13 @@ union cvmx_iob_inb_data_match_enb
 	struct cvmx_iob_inb_data_match_enb_s  cn56xxp1;
 	struct cvmx_iob_inb_data_match_enb_s  cn58xx;
 	struct cvmx_iob_inb_data_match_enb_s  cn58xxp1;
+	struct cvmx_iob_inb_data_match_enb_s  cn61xx;
 	struct cvmx_iob_inb_data_match_enb_s  cn63xx;
 	struct cvmx_iob_inb_data_match_enb_s  cn63xxp1;
+	struct cvmx_iob_inb_data_match_enb_s  cn66xx;
+	struct cvmx_iob_inb_data_match_enb_s  cn68xx;
+	struct cvmx_iob_inb_data_match_enb_s  cn68xxp1;
+	struct cvmx_iob_inb_data_match_enb_s  cnf71xx;
 };
 typedef union cvmx_iob_inb_data_match_enb cvmx_iob_inb_data_match_enb_t;
 
@@ -669,12 +957,10 @@ typedef union cvmx_iob_inb_data_match_enb cvmx_iob_inb_data_match_enb_t;
  *
  * The IOB's interrupt enable register. This is a PASS-2 register.
  */
-union cvmx_iob_int_enb
-{
+union cvmx_iob_int_enb {
 	uint64_t u64;
-	struct cvmx_iob_int_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t p_dat                        : 1;  /**< When set (1) and bit 5 of the IOB_INT_SUM
                                                          register is asserted the IOB will assert an
@@ -704,9 +990,8 @@ union cvmx_iob_int_enb
 	uint64_t reserved_6_63                : 58;
 #endif
 	} s;
-	struct cvmx_iob_int_enb_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_int_enb_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t p_eop                        : 1;  /**< When set (1) and bit 3 of the IOB_INT_SUM
                                                          register is asserted the IOB will assert an
@@ -738,8 +1023,19 @@ union cvmx_iob_int_enb
 	struct cvmx_iob_int_enb_s             cn56xxp1;
 	struct cvmx_iob_int_enb_s             cn58xx;
 	struct cvmx_iob_int_enb_s             cn58xxp1;
+	struct cvmx_iob_int_enb_s             cn61xx;
 	struct cvmx_iob_int_enb_s             cn63xx;
 	struct cvmx_iob_int_enb_s             cn63xxp1;
+	struct cvmx_iob_int_enb_s             cn66xx;
+	struct cvmx_iob_int_enb_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} cn68xx;
+	struct cvmx_iob_int_enb_cn68xx        cn68xxp1;
+	struct cvmx_iob_int_enb_s             cnf71xx;
 };
 typedef union cvmx_iob_int_enb cvmx_iob_int_enb_t;
 
@@ -750,12 +1046,10 @@ typedef union cvmx_iob_int_enb cvmx_iob_int_enb_t;
  *
  * Contains the diffrent interrupt summary bits of the IOB. This is a PASS-2 register.
  */
-union cvmx_iob_int_sum
-{
+union cvmx_iob_int_sum {
 	uint64_t u64;
-	struct cvmx_iob_int_sum_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t p_dat                        : 1;  /**< Set when a data arrives before a SOP for the same
                                                          port for a passthrough packet.
@@ -797,9 +1091,8 @@ union cvmx_iob_int_sum
 	uint64_t reserved_6_63                : 58;
 #endif
 	} s;
-	struct cvmx_iob_int_sum_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_int_sum_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t p_eop                        : 1;  /**< Set when a EOP is followed by an EOP for the same
                                                          port for a passthrough packet.
@@ -839,8 +1132,19 @@ union cvmx_iob_int_sum
 	struct cvmx_iob_int_sum_s             cn56xxp1;
 	struct cvmx_iob_int_sum_s             cn58xx;
 	struct cvmx_iob_int_sum_s             cn58xxp1;
+	struct cvmx_iob_int_sum_s             cn61xx;
 	struct cvmx_iob_int_sum_s             cn63xx;
 	struct cvmx_iob_int_sum_s             cn63xxp1;
+	struct cvmx_iob_int_sum_s             cn66xx;
+	struct cvmx_iob_int_sum_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} cn68xx;
+	struct cvmx_iob_int_sum_cn68xx        cn68xxp1;
+	struct cvmx_iob_int_sum_s             cnf71xx;
 };
 typedef union cvmx_iob_int_sum cvmx_iob_int_sum_t;
 
@@ -851,12 +1155,10 @@ typedef union cvmx_iob_int_sum cvmx_iob_int_sum_t;
  *
  * Enables and supplies the timeout count for raising the priority of NCB Store/Load access to the CMB.
  */
-union cvmx_iob_n2c_l2c_pri_cnt
-{
+union cvmx_iob_n2c_l2c_pri_cnt {
 	uint64_t u64;
-	struct cvmx_iob_n2c_l2c_pri_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_n2c_l2c_pri_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t cnt_enb                      : 1;  /**< Enables the raising of CMB access priority
                                                          when CNT_VAL is reached. */
@@ -876,8 +1178,11 @@ union cvmx_iob_n2c_l2c_pri_cnt
 	struct cvmx_iob_n2c_l2c_pri_cnt_s     cn56xxp1;
 	struct cvmx_iob_n2c_l2c_pri_cnt_s     cn58xx;
 	struct cvmx_iob_n2c_l2c_pri_cnt_s     cn58xxp1;
+	struct cvmx_iob_n2c_l2c_pri_cnt_s     cn61xx;
 	struct cvmx_iob_n2c_l2c_pri_cnt_s     cn63xx;
 	struct cvmx_iob_n2c_l2c_pri_cnt_s     cn63xxp1;
+	struct cvmx_iob_n2c_l2c_pri_cnt_s     cn66xx;
+	struct cvmx_iob_n2c_l2c_pri_cnt_s     cnf71xx;
 };
 typedef union cvmx_iob_n2c_l2c_pri_cnt cvmx_iob_n2c_l2c_pri_cnt_t;
 
@@ -888,12 +1193,10 @@ typedef union cvmx_iob_n2c_l2c_pri_cnt cvmx_iob_n2c_l2c_pri_cnt_t;
  *
  * Enables and supplies the timeout count for raising the priority of NCB Responses access to the CMB.
  */
-union cvmx_iob_n2c_rsp_pri_cnt
-{
+union cvmx_iob_n2c_rsp_pri_cnt {
 	uint64_t u64;
-	struct cvmx_iob_n2c_rsp_pri_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_n2c_rsp_pri_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t cnt_enb                      : 1;  /**< Enables the raising of CMB access priority
                                                          when CNT_VAL is reached. */
@@ -913,8 +1216,11 @@ union cvmx_iob_n2c_rsp_pri_cnt
 	struct cvmx_iob_n2c_rsp_pri_cnt_s     cn56xxp1;
 	struct cvmx_iob_n2c_rsp_pri_cnt_s     cn58xx;
 	struct cvmx_iob_n2c_rsp_pri_cnt_s     cn58xxp1;
+	struct cvmx_iob_n2c_rsp_pri_cnt_s     cn61xx;
 	struct cvmx_iob_n2c_rsp_pri_cnt_s     cn63xx;
 	struct cvmx_iob_n2c_rsp_pri_cnt_s     cn63xxp1;
+	struct cvmx_iob_n2c_rsp_pri_cnt_s     cn66xx;
+	struct cvmx_iob_n2c_rsp_pri_cnt_s     cnf71xx;
 };
 typedef union cvmx_iob_n2c_rsp_pri_cnt cvmx_iob_n2c_rsp_pri_cnt_t;
 
@@ -925,12 +1231,10 @@ typedef union cvmx_iob_n2c_rsp_pri_cnt cvmx_iob_n2c_rsp_pri_cnt_t;
  *
  * Enables and supplies the timeout count for raising the priority of Commit request to the Outbound NCB.
  */
-union cvmx_iob_outb_com_pri_cnt
-{
+union cvmx_iob_outb_com_pri_cnt {
 	uint64_t u64;
-	struct cvmx_iob_outb_com_pri_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_outb_com_pri_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t cnt_enb                      : 1;  /**< Enables the raising of NCB access priority
                                                          when CNT_VAL is reached. */
@@ -950,8 +1254,13 @@ union cvmx_iob_outb_com_pri_cnt
 	struct cvmx_iob_outb_com_pri_cnt_s    cn56xxp1;
 	struct cvmx_iob_outb_com_pri_cnt_s    cn58xx;
 	struct cvmx_iob_outb_com_pri_cnt_s    cn58xxp1;
+	struct cvmx_iob_outb_com_pri_cnt_s    cn61xx;
 	struct cvmx_iob_outb_com_pri_cnt_s    cn63xx;
 	struct cvmx_iob_outb_com_pri_cnt_s    cn63xxp1;
+	struct cvmx_iob_outb_com_pri_cnt_s    cn66xx;
+	struct cvmx_iob_outb_com_pri_cnt_s    cn68xx;
+	struct cvmx_iob_outb_com_pri_cnt_s    cn68xxp1;
+	struct cvmx_iob_outb_com_pri_cnt_s    cnf71xx;
 };
 typedef union cvmx_iob_outb_com_pri_cnt cvmx_iob_outb_com_pri_cnt_t;
 
@@ -962,12 +1271,10 @@ typedef union cvmx_iob_outb_com_pri_cnt cvmx_iob_outb_com_pri_cnt_t;
  *
  * Match pattern for the outbound control to set the OUTB_MATCH_BIT. PASS-2 Register
  */
-union cvmx_iob_outb_control_match
-{
+union cvmx_iob_outb_control_match {
 	uint64_t u64;
-	struct cvmx_iob_outb_control_match_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_outb_control_match_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_26_63               : 38;
 	uint64_t mask                         : 8;  /**< Pattern to match on the outbound NCB. */
 	uint64_t eot                          : 1;  /**< Pattern to match on the outbound NCB. */
@@ -992,8 +1299,13 @@ union cvmx_iob_outb_control_match
 	struct cvmx_iob_outb_control_match_s  cn56xxp1;
 	struct cvmx_iob_outb_control_match_s  cn58xx;
 	struct cvmx_iob_outb_control_match_s  cn58xxp1;
+	struct cvmx_iob_outb_control_match_s  cn61xx;
 	struct cvmx_iob_outb_control_match_s  cn63xx;
 	struct cvmx_iob_outb_control_match_s  cn63xxp1;
+	struct cvmx_iob_outb_control_match_s  cn66xx;
+	struct cvmx_iob_outb_control_match_s  cn68xx;
+	struct cvmx_iob_outb_control_match_s  cn68xxp1;
+	struct cvmx_iob_outb_control_match_s  cnf71xx;
 };
 typedef union cvmx_iob_outb_control_match cvmx_iob_outb_control_match_t;
 
@@ -1004,12 +1316,10 @@ typedef union cvmx_iob_outb_control_match cvmx_iob_outb_control_match_t;
  *
  * Enables the match of the corresponding bit in the IOB_OUTB_CONTROL_MATCH reister. PASS-2 Register
  */
-union cvmx_iob_outb_control_match_enb
-{
+union cvmx_iob_outb_control_match_enb {
 	uint64_t u64;
-	struct cvmx_iob_outb_control_match_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_outb_control_match_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_26_63               : 38;
 	uint64_t mask                         : 8;  /**< Pattern to match on the outbound NCB. */
 	uint64_t eot                          : 1;  /**< Pattern to match on the outbound NCB. */
@@ -1034,8 +1344,13 @@ union cvmx_iob_outb_control_match_enb
 	struct cvmx_iob_outb_control_match_enb_s cn56xxp1;
 	struct cvmx_iob_outb_control_match_enb_s cn58xx;
 	struct cvmx_iob_outb_control_match_enb_s cn58xxp1;
+	struct cvmx_iob_outb_control_match_enb_s cn61xx;
 	struct cvmx_iob_outb_control_match_enb_s cn63xx;
 	struct cvmx_iob_outb_control_match_enb_s cn63xxp1;
+	struct cvmx_iob_outb_control_match_enb_s cn66xx;
+	struct cvmx_iob_outb_control_match_enb_s cn68xx;
+	struct cvmx_iob_outb_control_match_enb_s cn68xxp1;
+	struct cvmx_iob_outb_control_match_enb_s cnf71xx;
 };
 typedef union cvmx_iob_outb_control_match_enb cvmx_iob_outb_control_match_enb_t;
 
@@ -1046,12 +1361,10 @@ typedef union cvmx_iob_outb_control_match_enb cvmx_iob_outb_control_match_enb_t;
  *
  * Match pattern for the outbound data to set the OUTB_MATCH_BIT. PASS-2 Register
  */
-union cvmx_iob_outb_data_match
-{
+union cvmx_iob_outb_data_match {
 	uint64_t u64;
-	struct cvmx_iob_outb_data_match_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_outb_data_match_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 64; /**< Pattern to match on the outbound NCB. */
 #else
 	uint64_t data                         : 64;
@@ -1068,8 +1381,13 @@ union cvmx_iob_outb_data_match
 	struct cvmx_iob_outb_data_match_s     cn56xxp1;
 	struct cvmx_iob_outb_data_match_s     cn58xx;
 	struct cvmx_iob_outb_data_match_s     cn58xxp1;
+	struct cvmx_iob_outb_data_match_s     cn61xx;
 	struct cvmx_iob_outb_data_match_s     cn63xx;
 	struct cvmx_iob_outb_data_match_s     cn63xxp1;
+	struct cvmx_iob_outb_data_match_s     cn66xx;
+	struct cvmx_iob_outb_data_match_s     cn68xx;
+	struct cvmx_iob_outb_data_match_s     cn68xxp1;
+	struct cvmx_iob_outb_data_match_s     cnf71xx;
 };
 typedef union cvmx_iob_outb_data_match cvmx_iob_outb_data_match_t;
 
@@ -1080,12 +1398,10 @@ typedef union cvmx_iob_outb_data_match cvmx_iob_outb_data_match_t;
  *
  * Enables the match of the corresponding bit in the IOB_OUTB_DATA_MATCH reister. PASS-2 Register
  */
-union cvmx_iob_outb_data_match_enb
-{
+union cvmx_iob_outb_data_match_enb {
 	uint64_t u64;
-	struct cvmx_iob_outb_data_match_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_outb_data_match_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 64; /**< Bit to enable match of. */
 #else
 	uint64_t data                         : 64;
@@ -1102,8 +1418,13 @@ union cvmx_iob_outb_data_match_enb
 	struct cvmx_iob_outb_data_match_enb_s cn56xxp1;
 	struct cvmx_iob_outb_data_match_enb_s cn58xx;
 	struct cvmx_iob_outb_data_match_enb_s cn58xxp1;
+	struct cvmx_iob_outb_data_match_enb_s cn61xx;
 	struct cvmx_iob_outb_data_match_enb_s cn63xx;
 	struct cvmx_iob_outb_data_match_enb_s cn63xxp1;
+	struct cvmx_iob_outb_data_match_enb_s cn66xx;
+	struct cvmx_iob_outb_data_match_enb_s cn68xx;
+	struct cvmx_iob_outb_data_match_enb_s cn68xxp1;
+	struct cvmx_iob_outb_data_match_enb_s cnf71xx;
 };
 typedef union cvmx_iob_outb_data_match_enb cvmx_iob_outb_data_match_enb_t;
 
@@ -1114,12 +1435,10 @@ typedef union cvmx_iob_outb_data_match_enb cvmx_iob_outb_data_match_enb_t;
  *
  * Enables and supplies the timeout count for raising the priority of FPA Rreturn Page request to the Outbound NCB.
  */
-union cvmx_iob_outb_fpa_pri_cnt
-{
+union cvmx_iob_outb_fpa_pri_cnt {
 	uint64_t u64;
-	struct cvmx_iob_outb_fpa_pri_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_outb_fpa_pri_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t cnt_enb                      : 1;  /**< Enables the raising of NCB access priority
                                                          when CNT_VAL is reached. */
@@ -1139,8 +1458,13 @@ union cvmx_iob_outb_fpa_pri_cnt
 	struct cvmx_iob_outb_fpa_pri_cnt_s    cn56xxp1;
 	struct cvmx_iob_outb_fpa_pri_cnt_s    cn58xx;
 	struct cvmx_iob_outb_fpa_pri_cnt_s    cn58xxp1;
+	struct cvmx_iob_outb_fpa_pri_cnt_s    cn61xx;
 	struct cvmx_iob_outb_fpa_pri_cnt_s    cn63xx;
 	struct cvmx_iob_outb_fpa_pri_cnt_s    cn63xxp1;
+	struct cvmx_iob_outb_fpa_pri_cnt_s    cn66xx;
+	struct cvmx_iob_outb_fpa_pri_cnt_s    cn68xx;
+	struct cvmx_iob_outb_fpa_pri_cnt_s    cn68xxp1;
+	struct cvmx_iob_outb_fpa_pri_cnt_s    cnf71xx;
 };
 typedef union cvmx_iob_outb_fpa_pri_cnt cvmx_iob_outb_fpa_pri_cnt_t;
 
@@ -1151,12 +1475,10 @@ typedef union cvmx_iob_outb_fpa_pri_cnt cvmx_iob_outb_fpa_pri_cnt_t;
  *
  * Enables and supplies the timeout count for raising the priority of Request transfers to the Outbound NCB.
  */
-union cvmx_iob_outb_req_pri_cnt
-{
+union cvmx_iob_outb_req_pri_cnt {
 	uint64_t u64;
-	struct cvmx_iob_outb_req_pri_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_outb_req_pri_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t cnt_enb                      : 1;  /**< Enables the raising of NCB access priority
                                                          when CNT_VAL is reached. */
@@ -1176,8 +1498,13 @@ union cvmx_iob_outb_req_pri_cnt
 	struct cvmx_iob_outb_req_pri_cnt_s    cn56xxp1;
 	struct cvmx_iob_outb_req_pri_cnt_s    cn58xx;
 	struct cvmx_iob_outb_req_pri_cnt_s    cn58xxp1;
+	struct cvmx_iob_outb_req_pri_cnt_s    cn61xx;
 	struct cvmx_iob_outb_req_pri_cnt_s    cn63xx;
 	struct cvmx_iob_outb_req_pri_cnt_s    cn63xxp1;
+	struct cvmx_iob_outb_req_pri_cnt_s    cn66xx;
+	struct cvmx_iob_outb_req_pri_cnt_s    cn68xx;
+	struct cvmx_iob_outb_req_pri_cnt_s    cn68xxp1;
+	struct cvmx_iob_outb_req_pri_cnt_s    cnf71xx;
 };
 typedef union cvmx_iob_outb_req_pri_cnt cvmx_iob_outb_req_pri_cnt_t;
 
@@ -1188,12 +1515,10 @@ typedef union cvmx_iob_outb_req_pri_cnt cvmx_iob_outb_req_pri_cnt_t;
  *
  * Enables and supplies the timeout count for raising the priority of PKO Load access to the CMB.
  */
-union cvmx_iob_p2c_req_pri_cnt
-{
+union cvmx_iob_p2c_req_pri_cnt {
 	uint64_t u64;
-	struct cvmx_iob_p2c_req_pri_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_p2c_req_pri_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t cnt_enb                      : 1;  /**< Enables the raising of CMB access priority
                                                          when CNT_VAL is reached. */
@@ -1213,8 +1538,11 @@ union cvmx_iob_p2c_req_pri_cnt
 	struct cvmx_iob_p2c_req_pri_cnt_s     cn56xxp1;
 	struct cvmx_iob_p2c_req_pri_cnt_s     cn58xx;
 	struct cvmx_iob_p2c_req_pri_cnt_s     cn58xxp1;
+	struct cvmx_iob_p2c_req_pri_cnt_s     cn61xx;
 	struct cvmx_iob_p2c_req_pri_cnt_s     cn63xx;
 	struct cvmx_iob_p2c_req_pri_cnt_s     cn63xxp1;
+	struct cvmx_iob_p2c_req_pri_cnt_s     cn66xx;
+	struct cvmx_iob_p2c_req_pri_cnt_s     cnf71xx;
 };
 typedef union cvmx_iob_p2c_req_pri_cnt cvmx_iob_p2c_req_pri_cnt_t;
 
@@ -1225,12 +1553,10 @@ typedef union cvmx_iob_p2c_req_pri_cnt cvmx_iob_p2c_req_pri_cnt_t;
  *
  * Provides status about the failing packet recevie error. This is a PASS-2 register.
  */
-union cvmx_iob_pkt_err
-{
+union cvmx_iob_pkt_err {
 	uint64_t u64;
-	struct cvmx_iob_pkt_err_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_pkt_err_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t vport                        : 6;  /**< When IOB_INT_SUM[3:0] bit is set, this field
                                                          latches the failing vport associate with the
@@ -1244,9 +1570,8 @@ union cvmx_iob_pkt_err
 	uint64_t reserved_12_63               : 52;
 #endif
 	} s;
-	struct cvmx_iob_pkt_err_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_pkt_err_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t port                         : 6;  /**< When IOB_INT_SUM[3:0] bit is set, this field
                                                          latches the failing port associate with the
@@ -1266,8 +1591,11 @@ union cvmx_iob_pkt_err
 	struct cvmx_iob_pkt_err_cn30xx        cn56xxp1;
 	struct cvmx_iob_pkt_err_cn30xx        cn58xx;
 	struct cvmx_iob_pkt_err_cn30xx        cn58xxp1;
+	struct cvmx_iob_pkt_err_s             cn61xx;
 	struct cvmx_iob_pkt_err_s             cn63xx;
 	struct cvmx_iob_pkt_err_s             cn63xxp1;
+	struct cvmx_iob_pkt_err_s             cn66xx;
+	struct cvmx_iob_pkt_err_s             cnf71xx;
 };
 typedef union cvmx_iob_pkt_err cvmx_iob_pkt_err_t;
 
@@ -1278,12 +1606,23 @@ typedef union cvmx_iob_pkt_err cvmx_iob_pkt_err_t;
  *
  * Controls the number of reads and writes that may be outstanding to the L2C (via the CMB).
  */
-union cvmx_iob_to_cmb_credits
-{
+union cvmx_iob_to_cmb_credits {
 	uint64_t u64;
-	struct cvmx_iob_to_cmb_credits_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_iob_to_cmb_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_6_63                : 58;
+	uint64_t ncb_rd                       : 3;  /**< Number of NCB reads that can be out to L2C where
+                                                         0 == 8-credits. */
+	uint64_t ncb_wr                       : 3;  /**< Number of NCB/PKI writes that can be out to L2C
+                                                         where 0 == 8-credits. */
+#else
+	uint64_t ncb_wr                       : 3;
+	uint64_t ncb_rd                       : 3;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_iob_to_cmb_credits_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t pko_rd                       : 3;  /**< Number of PKO reads that can be out to L2C where
                                                          0 == 8-credits. */
@@ -1297,11 +1636,316 @@ union cvmx_iob_to_cmb_credits
 	uint64_t pko_rd                       : 3;
 	uint64_t reserved_9_63                : 55;
 #endif
-	} s;
-	struct cvmx_iob_to_cmb_credits_s      cn52xx;
-	struct cvmx_iob_to_cmb_credits_s      cn63xx;
-	struct cvmx_iob_to_cmb_credits_s      cn63xxp1;
+	} cn52xx;
+	struct cvmx_iob_to_cmb_credits_cn52xx cn61xx;
+	struct cvmx_iob_to_cmb_credits_cn52xx cn63xx;
+	struct cvmx_iob_to_cmb_credits_cn52xx cn63xxp1;
+	struct cvmx_iob_to_cmb_credits_cn52xx cn66xx;
+	struct cvmx_iob_to_cmb_credits_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_9_63                : 55;
+	uint64_t dwb                          : 3;  /**< Number of DWBs  that can be out to L2C where
+                                                         0 == 8-credits. */
+	uint64_t ncb_rd                       : 3;  /**< Number of NCB reads that can be out to L2C where
+                                                         0 == 8-credits. */
+	uint64_t ncb_wr                       : 3;  /**< Number of NCB/PKI writes that can be out to L2C
+                                                         where 0 == 8-credits. */
+#else
+	uint64_t ncb_wr                       : 3;
+	uint64_t ncb_rd                       : 3;
+	uint64_t dwb                          : 3;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn68xx;
+	struct cvmx_iob_to_cmb_credits_cn68xx cn68xxp1;
+	struct cvmx_iob_to_cmb_credits_cn52xx cnf71xx;
 };
 typedef union cvmx_iob_to_cmb_credits cvmx_iob_to_cmb_credits_t;
 
+/**
+ * cvmx_iob_to_ncb_did_00_credits
+ *
+ * IOB_TO_NCB_DID_00_CREDITS = IOB NCB DID 00 Credits
+ *
+ * Number of credits for NCB DID 00.
+ */
+union cvmx_iob_to_ncb_did_00_credits {
+	uint64_t u64;
+	struct cvmx_iob_to_ncb_did_00_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t crd                          : 7;  /**< Number of credits for DID. Writing this field will
+                                                         casuse the credits to be set to the value written.
+                                                         Reading this field will give the number of credits
+                                                         PRESENTLY available. */
+#else
+	uint64_t crd                          : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_iob_to_ncb_did_00_credits_s cn68xx;
+	struct cvmx_iob_to_ncb_did_00_credits_s cn68xxp1;
+};
+typedef union cvmx_iob_to_ncb_did_00_credits cvmx_iob_to_ncb_did_00_credits_t;
+
+/**
+ * cvmx_iob_to_ncb_did_111_credits
+ *
+ * IOB_TO_NCB_DID_111_CREDITS = IOB NCB DID 111 Credits
+ *
+ * Number of credits for NCB DID 111.
+ */
+union cvmx_iob_to_ncb_did_111_credits {
+	uint64_t u64;
+	struct cvmx_iob_to_ncb_did_111_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t crd                          : 7;  /**< Number of credits for DID. Writing this field will
+                                                         casuse the credits to be set to the value written.
+                                                         Reading this field will give the number of credits
+                                                         PRESENTLY available. */
+#else
+	uint64_t crd                          : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_iob_to_ncb_did_111_credits_s cn68xx;
+	struct cvmx_iob_to_ncb_did_111_credits_s cn68xxp1;
+};
+typedef union cvmx_iob_to_ncb_did_111_credits cvmx_iob_to_ncb_did_111_credits_t;
+
+/**
+ * cvmx_iob_to_ncb_did_223_credits
+ *
+ * IOB_TO_NCB_DID_223_CREDITS = IOB NCB DID 223 Credits
+ *
+ * Number of credits for NCB DID 223.
+ */
+union cvmx_iob_to_ncb_did_223_credits {
+	uint64_t u64;
+	struct cvmx_iob_to_ncb_did_223_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t crd                          : 7;  /**< Number of credits for DID. Writing this field will
+                                                         casuse the credits to be set to the value written.
+                                                         Reading this field will give the number of credits
+                                                         PRESENTLY available. */
+#else
+	uint64_t crd                          : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_iob_to_ncb_did_223_credits_s cn68xx;
+	struct cvmx_iob_to_ncb_did_223_credits_s cn68xxp1;
+};
+typedef union cvmx_iob_to_ncb_did_223_credits cvmx_iob_to_ncb_did_223_credits_t;
+
+/**
+ * cvmx_iob_to_ncb_did_24_credits
+ *
+ * IOB_TO_NCB_DID_24_CREDITS = IOB NCB DID 24 Credits
+ *
+ * Number of credits for NCB DID 24.
+ */
+union cvmx_iob_to_ncb_did_24_credits {
+	uint64_t u64;
+	struct cvmx_iob_to_ncb_did_24_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t crd                          : 7;  /**< Number of credits for DID. Writing this field will
+                                                         casuse the credits to be set to the value written.
+                                                         Reading this field will give the number of credits
+                                                         PRESENTLY available. */
+#else
+	uint64_t crd                          : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_iob_to_ncb_did_24_credits_s cn68xx;
+	struct cvmx_iob_to_ncb_did_24_credits_s cn68xxp1;
+};
+typedef union cvmx_iob_to_ncb_did_24_credits cvmx_iob_to_ncb_did_24_credits_t;
+
+/**
+ * cvmx_iob_to_ncb_did_32_credits
+ *
+ * IOB_TO_NCB_DID_32_CREDITS = IOB NCB DID 32 Credits
+ *
+ * Number of credits for NCB DID 32.
+ */
+union cvmx_iob_to_ncb_did_32_credits {
+	uint64_t u64;
+	struct cvmx_iob_to_ncb_did_32_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t crd                          : 7;  /**< Number of credits for DID. Writing this field will
+                                                         casuse the credits to be set to the value written.
+                                                         Reading this field will give the number of credits
+                                                         PRESENTLY available. */
+#else
+	uint64_t crd                          : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_iob_to_ncb_did_32_credits_s cn68xx;
+	struct cvmx_iob_to_ncb_did_32_credits_s cn68xxp1;
+};
+typedef union cvmx_iob_to_ncb_did_32_credits cvmx_iob_to_ncb_did_32_credits_t;
+
+/**
+ * cvmx_iob_to_ncb_did_40_credits
+ *
+ * IOB_TO_NCB_DID_40_CREDITS = IOB NCB DID 40 Credits
+ *
+ * Number of credits for NCB DID 40.
+ */
+union cvmx_iob_to_ncb_did_40_credits {
+	uint64_t u64;
+	struct cvmx_iob_to_ncb_did_40_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t crd                          : 7;  /**< Number of credits for DID. Writing this field will
+                                                         casuse the credits to be set to the value written.
+                                                         Reading this field will give the number of credits
+                                                         PRESENTLY available. */
+#else
+	uint64_t crd                          : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_iob_to_ncb_did_40_credits_s cn68xx;
+	struct cvmx_iob_to_ncb_did_40_credits_s cn68xxp1;
+};
+typedef union cvmx_iob_to_ncb_did_40_credits cvmx_iob_to_ncb_did_40_credits_t;
+
+/**
+ * cvmx_iob_to_ncb_did_55_credits
+ *
+ * IOB_TO_NCB_DID_55_CREDITS = IOB NCB DID 55 Credits
+ *
+ * Number of credits for NCB DID 55.
+ */
+union cvmx_iob_to_ncb_did_55_credits {
+	uint64_t u64;
+	struct cvmx_iob_to_ncb_did_55_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t crd                          : 7;  /**< Number of credits for DID. Writing this field will
+                                                         casuse the credits to be set to the value written.
+                                                         Reading this field will give the number of credits
+                                                         PRESENTLY available. */
+#else
+	uint64_t crd                          : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_iob_to_ncb_did_55_credits_s cn68xx;
+	struct cvmx_iob_to_ncb_did_55_credits_s cn68xxp1;
+};
+typedef union cvmx_iob_to_ncb_did_55_credits cvmx_iob_to_ncb_did_55_credits_t;
+
+/**
+ * cvmx_iob_to_ncb_did_64_credits
+ *
+ * IOB_TO_NCB_DID_64_CREDITS = IOB NCB DID 64 Credits
+ *
+ * Number of credits for NCB DID 64.
+ */
+union cvmx_iob_to_ncb_did_64_credits {
+	uint64_t u64;
+	struct cvmx_iob_to_ncb_did_64_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t crd                          : 7;  /**< Number of credits for DID. Writing this field will
+                                                         casuse the credits to be set to the value written.
+                                                         Reading this field will give the number of credits
+                                                         PRESENTLY available. */
+#else
+	uint64_t crd                          : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_iob_to_ncb_did_64_credits_s cn68xx;
+	struct cvmx_iob_to_ncb_did_64_credits_s cn68xxp1;
+};
+typedef union cvmx_iob_to_ncb_did_64_credits cvmx_iob_to_ncb_did_64_credits_t;
+
+/**
+ * cvmx_iob_to_ncb_did_79_credits
+ *
+ * IOB_TO_NCB_DID_79_CREDITS = IOB NCB DID 79 Credits
+ *
+ * Number of credits for NCB DID 79.
+ */
+union cvmx_iob_to_ncb_did_79_credits {
+	uint64_t u64;
+	struct cvmx_iob_to_ncb_did_79_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t crd                          : 7;  /**< Number of credits for DID. Writing this field will
+                                                         casuse the credits to be set to the value written.
+                                                         Reading this field will give the number of credits
+                                                         PRESENTLY available. */
+#else
+	uint64_t crd                          : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_iob_to_ncb_did_79_credits_s cn68xx;
+	struct cvmx_iob_to_ncb_did_79_credits_s cn68xxp1;
+};
+typedef union cvmx_iob_to_ncb_did_79_credits cvmx_iob_to_ncb_did_79_credits_t;
+
+/**
+ * cvmx_iob_to_ncb_did_96_credits
+ *
+ * IOB_TO_NCB_DID_96_CREDITS = IOB NCB DID 96 Credits
+ *
+ * Number of credits for NCB DID 96.
+ */
+union cvmx_iob_to_ncb_did_96_credits {
+	uint64_t u64;
+	struct cvmx_iob_to_ncb_did_96_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t crd                          : 7;  /**< Number of credits for DID. Writing this field will
+                                                         casuse the credits to be set to the value written.
+                                                         Reading this field will give the number of credits
+                                                         PRESENTLY available. */
+#else
+	uint64_t crd                          : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_iob_to_ncb_did_96_credits_s cn68xx;
+	struct cvmx_iob_to_ncb_did_96_credits_s cn68xxp1;
+};
+typedef union cvmx_iob_to_ncb_did_96_credits cvmx_iob_to_ncb_did_96_credits_t;
+
+/**
+ * cvmx_iob_to_ncb_did_98_credits
+ *
+ * IOB_TO_NCB_DID_98_CREDITS = IOB NCB DID 96 Credits
+ *
+ * Number of credits for NCB DID 98.
+ */
+union cvmx_iob_to_ncb_did_98_credits {
+	uint64_t u64;
+	struct cvmx_iob_to_ncb_did_98_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t crd                          : 7;  /**< Number of credits for DID. Writing this field will
+                                                         casuse the credits to be set to the value written.
+                                                         Reading this field will give the number of credits
+                                                         PRESENTLY available. */
+#else
+	uint64_t crd                          : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_iob_to_ncb_did_98_credits_s cn68xx;
+	struct cvmx_iob_to_ncb_did_98_credits_s cn68xxp1;
+};
+typedef union cvmx_iob_to_ncb_did_98_credits cvmx_iob_to_ncb_did_98_credits_t;
+
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-iob1-defs.h b/sys/contrib/octeon-sdk/cvmx-iob1-defs.h
new file mode 100644
index 0000000..5e39e5c
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-iob1-defs.h
@@ -0,0 +1,184 @@
+/***********************license start***************
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-iob1-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon iob1.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_IOB1_DEFS_H__
+#define __CVMX_IOB1_DEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB1_BIST_STATUS CVMX_IOB1_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_IOB1_BIST_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IOB1_BIST_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F00107F8ull);
+}
+#else
+#define CVMX_IOB1_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00107F8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB1_CTL_STATUS CVMX_IOB1_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_IOB1_CTL_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IOB1_CTL_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0010050ull);
+}
+#else
+#define CVMX_IOB1_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0010050ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB1_TO_CMB_CREDITS CVMX_IOB1_TO_CMB_CREDITS_FUNC()
+static inline uint64_t CVMX_IOB1_TO_CMB_CREDITS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IOB1_TO_CMB_CREDITS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F00100B0ull);
+}
+#else
+#define CVMX_IOB1_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00100B0ull))
+#endif
+
+/**
+ * cvmx_iob1_bist_status
+ *
+ * IOB_BIST_STATUS = BIST Status of IOB Memories
+ *
+ * The result of the BIST run on the IOB memories.
+ */
+union cvmx_iob1_bist_status {
+	uint64_t u64;
+	struct cvmx_iob1_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_9_63                : 55;
+	uint64_t xmdfif                       : 1;  /**< xmdfif_bist_status */
+	uint64_t xmcfif                       : 1;  /**< xmcfif_bist_status */
+	uint64_t iorfif                       : 1;  /**< iorfif_bist_status */
+	uint64_t rsdfif                       : 1;  /**< rsdfif_bist_status */
+	uint64_t iocfif                       : 1;  /**< iocfif_bist_status */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t icrp0                        : 1;  /**< icr_pko_bist_mem0_status */
+	uint64_t icrp1                        : 1;  /**< icr_pko_bist_mem1_status */
+#else
+	uint64_t icrp1                        : 1;
+	uint64_t icrp0                        : 1;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t iocfif                       : 1;
+	uint64_t rsdfif                       : 1;
+	uint64_t iorfif                       : 1;
+	uint64_t xmcfif                       : 1;
+	uint64_t xmdfif                       : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_iob1_bist_status_s        cn68xx;
+	struct cvmx_iob1_bist_status_s        cn68xxp1;
+};
+typedef union cvmx_iob1_bist_status cvmx_iob1_bist_status_t;
+
+/**
+ * cvmx_iob1_ctl_status
+ *
+ * IOB Control Status = IOB Control and Status Register
+ *
+ * Provides control for IOB functions.
+ */
+union cvmx_iob1_ctl_status {
+	uint64_t u64;
+	struct cvmx_iob1_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_11_63               : 53;
+	uint64_t fif_dly                      : 1;  /**< Delay async FIFO counts to be used when clock ratio
+                                                         is greater then 3:1. Writes should be followed by an
+                                                         immediate read. */
+	uint64_t xmc_per                      : 4;  /**< IBC XMC PUSH EARLY */
+	uint64_t reserved_0_5                 : 6;
+#else
+	uint64_t reserved_0_5                 : 6;
+	uint64_t xmc_per                      : 4;
+	uint64_t fif_dly                      : 1;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} s;
+	struct cvmx_iob1_ctl_status_s         cn68xx;
+	struct cvmx_iob1_ctl_status_s         cn68xxp1;
+};
+typedef union cvmx_iob1_ctl_status cvmx_iob1_ctl_status_t;
+
+/**
+ * cvmx_iob1_to_cmb_credits
+ *
+ * IOB_TO_CMB_CREDITS = IOB To CMB Credits
+ *
+ * Controls the number of reads and writes that may be outstanding to the L2C (via the CMB).
+ */
+union cvmx_iob1_to_cmb_credits {
+	uint64_t u64;
+	struct cvmx_iob1_to_cmb_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t pko_rd                       : 4;  /**< Number of PKO reads that can be out to L2C where
+                                                         0 == 16-credits. */
+	uint64_t reserved_3_5                 : 3;
+	uint64_t ncb_wr                       : 3;  /**< Number of NCB/PKI writes that can be out to L2C
+                                                         where 0 == 8-credits. */
+#else
+	uint64_t ncb_wr                       : 3;
+	uint64_t reserved_3_5                 : 3;
+	uint64_t pko_rd                       : 4;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_iob1_to_cmb_credits_s     cn68xx;
+	struct cvmx_iob1_to_cmb_credits_s     cn68xxp1;
+};
+typedef union cvmx_iob1_to_cmb_credits cvmx_iob1_to_cmb_credits_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-ipd-defs.h b/sys/contrib/octeon-sdk/cvmx-ipd-defs.h
index a0a4a3e..5e1a05a 100644
--- a/sys/contrib/octeon-sdk/cvmx-ipd-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-ipd-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,21 +49,162 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_IPD_TYPEDEFS_H__
-#define __CVMX_IPD_TYPEDEFS_H__
+#ifndef __CVMX_IPD_DEFS_H__
+#define __CVMX_IPD_DEFS_H__
 
 #define CVMX_IPD_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000000ull))
 #define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull))
 #define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull))
 #define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_IPD_BPIDX_MBUF_TH(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_IPD_BPIDX_MBUF_TH(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8;
+}
+#else
+#define CVMX_IPD_BPIDX_MBUF_TH(offset) (CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_IPD_BPID_BP_COUNTERX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_IPD_BPID_BP_COUNTERX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8;
+}
+#else
+#define CVMX_IPD_BPID_BP_COUNTERX(offset) (CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_BP_PRT_RED_END CVMX_IPD_BP_PRT_RED_END_FUNC()
+static inline uint64_t CVMX_IPD_BP_PRT_RED_END_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_IPD_BP_PRT_RED_END not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F0000000328ull);
+}
+#else
 #define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull))
+#endif
 #define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_CREDITS CVMX_IPD_CREDITS_FUNC()
+static inline uint64_t CVMX_IPD_CREDITS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IPD_CREDITS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F0000004410ull);
+}
+#else
+#define CVMX_IPD_CREDITS (CVMX_ADD_IO_SEG(0x00014F0000004410ull))
+#endif
 #define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_ECC_CTL CVMX_IPD_ECC_CTL_FUNC()
+static inline uint64_t CVMX_IPD_ECC_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IPD_ECC_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F0000004408ull);
+}
+#else
+#define CVMX_IPD_ECC_CTL (CVMX_ADD_IO_SEG(0x00014F0000004408ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_FREE_PTR_FIFO_CTL CVMX_IPD_FREE_PTR_FIFO_CTL_FUNC()
+static inline uint64_t CVMX_IPD_FREE_PTR_FIFO_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IPD_FREE_PTR_FIFO_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F0000000780ull);
+}
+#else
+#define CVMX_IPD_FREE_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000780ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_FREE_PTR_VALUE CVMX_IPD_FREE_PTR_VALUE_FUNC()
+static inline uint64_t CVMX_IPD_FREE_PTR_VALUE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IPD_FREE_PTR_VALUE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F0000000788ull);
+}
+#else
+#define CVMX_IPD_FREE_PTR_VALUE (CVMX_ADD_IO_SEG(0x00014F0000000788ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_HOLD_PTR_FIFO_CTL CVMX_IPD_HOLD_PTR_FIFO_CTL_FUNC()
+static inline uint64_t CVMX_IPD_HOLD_PTR_FIFO_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IPD_HOLD_PTR_FIFO_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F0000000790ull);
+}
+#else
+#define CVMX_IPD_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000790ull))
+#endif
 #define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull))
 #define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_NEXT_PKT_PTR CVMX_IPD_NEXT_PKT_PTR_FUNC()
+static inline uint64_t CVMX_IPD_NEXT_PKT_PTR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IPD_NEXT_PKT_PTR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F00000007A0ull);
+}
+#else
+#define CVMX_IPD_NEXT_PKT_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_NEXT_WQE_PTR CVMX_IPD_NEXT_WQE_PTR_FUNC()
+static inline uint64_t CVMX_IPD_NEXT_WQE_PTR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IPD_NEXT_WQE_PTR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F00000007A8ull);
+}
+#else
+#define CVMX_IPD_NEXT_WQE_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A8ull))
+#endif
 #define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_IPD_ON_BP_DROP_PKTX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_IPD_ON_BP_DROP_PKTX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00014F0000004100ull);
+}
+#else
+#define CVMX_IPD_ON_BP_DROP_PKTX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004100ull))
+#endif
 #define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_PKT_ERR CVMX_IPD_PKT_ERR_FUNC()
+static inline uint64_t CVMX_IPD_PKT_ERR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IPD_PKT_ERR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F00000003F0ull);
+}
+#else
+#define CVMX_IPD_PKT_ERR (CVMX_ADD_IO_SEG(0x00014F00000003F0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_PKT_PTR_VALID CVMX_IPD_PKT_PTR_VALID_FUNC()
+static inline uint64_t CVMX_IPD_PKT_PTR_VALID_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_IPD_PKT_PTR_VALID not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F0000000358ull);
+}
+#else
 #define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull))
+#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT(unsigned long offset)
 {
@@ -75,7 +216,10 @@ static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35))))))
 		cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8;
 }
@@ -88,7 +232,10 @@ static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT2(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 36) && (offset <= 39)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 36) && (offset <= 39))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 36) && (offset <= 39))))))
 		cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT2(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36;
 }
@@ -99,7 +246,10 @@ static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT2(unsigned long offset)
 static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT3(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 40) && (offset <= 47)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 40) && (offset <= 47))))))
 		cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT3(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40;
 }
@@ -112,7 +262,10 @@ static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 36) && (offset <= 39)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 36) && (offset <= 39))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 36) && (offset <= 39))))))
 		cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36;
 }
@@ -123,7 +276,10 @@ static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(unsigned long offset)
 static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 40) && (offset <= 43))))))
 		cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40;
 }
@@ -131,6 +287,19 @@ static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(unsigned long offset)
 #define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 44) && (offset <= 47)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 44) && (offset <= 47)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 44) && (offset <= 47))))))
+		cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8*44;
+}
+#else
+#define CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8*44)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS_PAIRX(unsigned long offset)
 {
 	if (!(
@@ -141,7 +310,10 @@ static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS_PAIRX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35))))))
 		cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS_PAIRX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8;
 }
@@ -149,12 +321,27 @@ static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS_PAIRX(unsigned long offset)
 #define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_PORT_PTR_FIFO_CTL CVMX_IPD_PORT_PTR_FIFO_CTL_FUNC()
+static inline uint64_t CVMX_IPD_PORT_PTR_FIFO_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IPD_PORT_PTR_FIFO_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F0000000798ull);
+}
+#else
+#define CVMX_IPD_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000798ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_IPD_PORT_QOS_INTX(unsigned long offset)
 {
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset == 0) || (offset == 4))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0) || (offset == 2) || (offset == 4))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0) || (offset == 4) || (offset == 5)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0) || (offset == 4) || (offset == 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5)))))
 		cvmx_warn("CVMX_IPD_PORT_QOS_INTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8;
 }
@@ -167,7 +354,11 @@ static inline uint64_t CVMX_IPD_PORT_QOS_INT_ENBX(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset == 0) || (offset == 4))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0) || (offset == 2) || (offset == 4))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0) || (offset == 4) || (offset == 5)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0) || (offset == 4) || (offset == 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5)))))
 		cvmx_warn("CVMX_IPD_PORT_QOS_INT_ENBX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8;
 }
@@ -180,17 +371,62 @@ static inline uint64_t CVMX_IPD_PORT_QOS_X_CNT(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31) || ((offset >= 256) && (offset <= 319)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 319)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31) || ((offset >= 256) && (offset <= 351))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 383)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31) || ((offset >= 256) && (offset <= 351)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 335)) || ((offset >= 352) && (offset <= 383)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 511))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 383))))))
 		cvmx_warn("CVMX_IPD_PORT_QOS_X_CNT(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8;
 }
 #else
 #define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8)
 #endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_IPD_PORT_SOPX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_IPD_PORT_SOPX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00014F0000004400ull);
+}
+#else
+#define CVMX_IPD_PORT_SOPX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004400ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL_FUNC()
+static inline uint64_t CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F0000000348ull);
+}
+#else
 #define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL CVMX_IPD_PRC_PORT_PTR_FIFO_CTL_FUNC()
+static inline uint64_t CVMX_IPD_PRC_PORT_PTR_FIFO_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_IPD_PRC_PORT_PTR_FIFO_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F0000000350ull);
+}
+#else
 #define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull))
+#endif
 #define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_PWP_PTR_FIFO_CTL CVMX_IPD_PWP_PTR_FIFO_CTL_FUNC()
+static inline uint64_t CVMX_IPD_PWP_PTR_FIFO_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_IPD_PWP_PTR_FIFO_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F0000000340ull);
+}
+#else
 #define CVMX_IPD_PWP_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000340ull))
+#endif
 #define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0)
 #define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1)
 #define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2)
@@ -210,7 +446,11 @@ static inline uint64_t CVMX_IPD_QOSX_RED_MARKS(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_IPD_QOSX_RED_MARKS(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8;
 }
@@ -218,12 +458,44 @@ static inline uint64_t CVMX_IPD_QOSX_RED_MARKS(unsigned long offset)
 #define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8)
 #endif
 #define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_IPD_RED_BPID_ENABLEX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_IPD_RED_BPID_ENABLEX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00014F0000004200ull);
+}
+#else
+#define CVMX_IPD_RED_BPID_ENABLEX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004200ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_RED_DELAY CVMX_IPD_RED_DELAY_FUNC()
+static inline uint64_t CVMX_IPD_RED_DELAY_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IPD_RED_DELAY not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F0000004300ull);
+}
+#else
+#define CVMX_IPD_RED_DELAY (CVMX_ADD_IO_SEG(0x00014F0000004300ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_RED_PORT_ENABLE CVMX_IPD_RED_PORT_ENABLE_FUNC()
+static inline uint64_t CVMX_IPD_RED_PORT_ENABLE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_IPD_RED_PORT_ENABLE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F00000002D8ull);
+}
+#else
 #define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull))
+#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_IPD_RED_PORT_ENABLE2 CVMX_IPD_RED_PORT_ENABLE2_FUNC()
 static inline uint64_t CVMX_IPD_RED_PORT_ENABLE2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_IPD_RED_PORT_ENABLE2 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00014F00000003A8ull);
 }
@@ -249,20 +521,45 @@ static inline uint64_t CVMX_IPD_RED_QUEX_PARAM(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_IPD_RED_QUEX_PARAM(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8;
 }
 #else
 #define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8)
 #endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_REQ_WGT CVMX_IPD_REQ_WGT_FUNC()
+static inline uint64_t CVMX_IPD_REQ_WGT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_IPD_REQ_WGT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F0000004418ull);
+}
+#else
+#define CVMX_IPD_REQ_WGT (CVMX_ADD_IO_SEG(0x00014F0000004418ull))
+#endif
 #define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_SUB_PORT_FCS CVMX_IPD_SUB_PORT_FCS_FUNC()
+static inline uint64_t CVMX_IPD_SUB_PORT_FCS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_IPD_SUB_PORT_FCS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F0000000170ull);
+}
+#else
 #define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull))
+#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_IPD_SUB_PORT_QOS_CNT CVMX_IPD_SUB_PORT_QOS_CNT_FUNC()
 static inline uint64_t CVMX_IPD_SUB_PORT_QOS_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_IPD_SUB_PORT_QOS_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00014F0000000800ull);
 }
@@ -270,7 +567,17 @@ static inline uint64_t CVMX_IPD_SUB_PORT_QOS_CNT_FUNC(void)
 #define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull))
 #endif
 #define CVMX_IPD_WQE_FPA_QUEUE (CVMX_ADD_IO_SEG(0x00014F0000000020ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_WQE_PTR_VALID CVMX_IPD_WQE_PTR_VALID_FUNC()
+static inline uint64_t CVMX_IPD_WQE_PTR_VALID_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_IPD_WQE_PTR_VALID not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F0000000360ull);
+}
+#else
 #define CVMX_IPD_WQE_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000360ull))
+#endif
 
 /**
  * cvmx_ipd_1st_mbuff_skip
@@ -279,12 +586,10 @@ static inline uint64_t CVMX_IPD_SUB_PORT_QOS_CNT_FUNC(void)
  *
  * The number of words that the IPD will skip when writing the first MBUFF.
  */
-union cvmx_ipd_1st_mbuff_skip
-{
+union cvmx_ipd_1st_mbuff_skip {
 	uint64_t u64;
-	struct cvmx_ipd_1st_mbuff_skip_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_1st_mbuff_skip_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t skip_sz                      : 6;  /**< The number of 8-byte words from the top of the
                                                          1st MBUFF that the IPD will store the next-pointer.
@@ -309,8 +614,13 @@ union cvmx_ipd_1st_mbuff_skip
 	struct cvmx_ipd_1st_mbuff_skip_s      cn56xxp1;
 	struct cvmx_ipd_1st_mbuff_skip_s      cn58xx;
 	struct cvmx_ipd_1st_mbuff_skip_s      cn58xxp1;
+	struct cvmx_ipd_1st_mbuff_skip_s      cn61xx;
 	struct cvmx_ipd_1st_mbuff_skip_s      cn63xx;
 	struct cvmx_ipd_1st_mbuff_skip_s      cn63xxp1;
+	struct cvmx_ipd_1st_mbuff_skip_s      cn66xx;
+	struct cvmx_ipd_1st_mbuff_skip_s      cn68xx;
+	struct cvmx_ipd_1st_mbuff_skip_s      cn68xxp1;
+	struct cvmx_ipd_1st_mbuff_skip_s      cnf71xx;
 };
 typedef union cvmx_ipd_1st_mbuff_skip cvmx_ipd_1st_mbuff_skip_t;
 
@@ -321,12 +631,10 @@ typedef union cvmx_ipd_1st_mbuff_skip cvmx_ipd_1st_mbuff_skip_t;
  *
  * Contains the Back Field for use in creating the Next Pointer Header for the First MBUF
  */
-union cvmx_ipd_1st_next_ptr_back
-{
+union cvmx_ipd_1st_next_ptr_back {
 	uint64_t u64;
-	struct cvmx_ipd_1st_next_ptr_back_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_1st_next_ptr_back_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t back                         : 4;  /**< Used to find head of buffer from the nxt-hdr-ptr. */
 #else
@@ -345,8 +653,13 @@ union cvmx_ipd_1st_next_ptr_back
 	struct cvmx_ipd_1st_next_ptr_back_s   cn56xxp1;
 	struct cvmx_ipd_1st_next_ptr_back_s   cn58xx;
 	struct cvmx_ipd_1st_next_ptr_back_s   cn58xxp1;
+	struct cvmx_ipd_1st_next_ptr_back_s   cn61xx;
 	struct cvmx_ipd_1st_next_ptr_back_s   cn63xx;
 	struct cvmx_ipd_1st_next_ptr_back_s   cn63xxp1;
+	struct cvmx_ipd_1st_next_ptr_back_s   cn66xx;
+	struct cvmx_ipd_1st_next_ptr_back_s   cn68xx;
+	struct cvmx_ipd_1st_next_ptr_back_s   cn68xxp1;
+	struct cvmx_ipd_1st_next_ptr_back_s   cnf71xx;
 };
 typedef union cvmx_ipd_1st_next_ptr_back cvmx_ipd_1st_next_ptr_back_t;
 
@@ -357,12 +670,10 @@ typedef union cvmx_ipd_1st_next_ptr_back cvmx_ipd_1st_next_ptr_back_t;
  *
  * Contains the Back Field for use in creating the Next Pointer Header for the First MBUF
  */
-union cvmx_ipd_2nd_next_ptr_back
-{
+union cvmx_ipd_2nd_next_ptr_back {
 	uint64_t u64;
-	struct cvmx_ipd_2nd_next_ptr_back_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_2nd_next_ptr_back_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t back                         : 4;  /**< Used to find head of buffer from the nxt-hdr-ptr. */
 #else
@@ -381,8 +692,13 @@ union cvmx_ipd_2nd_next_ptr_back
 	struct cvmx_ipd_2nd_next_ptr_back_s   cn56xxp1;
 	struct cvmx_ipd_2nd_next_ptr_back_s   cn58xx;
 	struct cvmx_ipd_2nd_next_ptr_back_s   cn58xxp1;
+	struct cvmx_ipd_2nd_next_ptr_back_s   cn61xx;
 	struct cvmx_ipd_2nd_next_ptr_back_s   cn63xx;
 	struct cvmx_ipd_2nd_next_ptr_back_s   cn63xxp1;
+	struct cvmx_ipd_2nd_next_ptr_back_s   cn66xx;
+	struct cvmx_ipd_2nd_next_ptr_back_s   cn68xx;
+	struct cvmx_ipd_2nd_next_ptr_back_s   cn68xxp1;
+	struct cvmx_ipd_2nd_next_ptr_back_s   cnf71xx;
 };
 typedef union cvmx_ipd_2nd_next_ptr_back cvmx_ipd_2nd_next_ptr_back_t;
 
@@ -393,13 +709,16 @@ typedef union cvmx_ipd_2nd_next_ptr_back cvmx_ipd_2nd_next_ptr_back_t;
  *
  * BIST Status for IPD's Memories.
  */
-union cvmx_ipd_bist_status
-{
+union cvmx_ipd_bist_status {
 	uint64_t u64;
-	struct cvmx_ipd_bist_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_18_63               : 46;
+	struct cvmx_ipd_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_23_63               : 41;
+	uint64_t iiwo1                        : 1;  /**< IPD IOB WQE Dataout MEM1 Bist Status. */
+	uint64_t iiwo0                        : 1;  /**< IPD IOB WQE Dataout MEM0 Bist Status. */
+	uint64_t iio1                         : 1;  /**< IPD IOB Dataout MEM1 Bist Status. */
+	uint64_t iio0                         : 1;  /**< IPD IOB Dataout MEM0 Bist Status. */
+	uint64_t pbm4                         : 1;  /**< PBM4Memory Bist Status. */
 	uint64_t csr_mem                      : 1;  /**< CSR Register Memory Bist Status. */
 	uint64_t csr_ncmd                     : 1;  /**< CSR NCB Commands Memory Bist Status. */
 	uint64_t pwq_wqed                     : 1;  /**< PWQ PIP WQE DONE Memory Bist Status. */
@@ -437,12 +756,16 @@ union cvmx_ipd_bist_status
 	uint64_t pwq_wqed                     : 1;
 	uint64_t csr_ncmd                     : 1;
 	uint64_t csr_mem                      : 1;
-	uint64_t reserved_18_63               : 46;
+	uint64_t pbm4                         : 1;
+	uint64_t iio0                         : 1;
+	uint64_t iio1                         : 1;
+	uint64_t iiwo0                        : 1;
+	uint64_t iiwo1                        : 1;
+	uint64_t reserved_23_63               : 41;
 #endif
 	} s;
-	struct cvmx_ipd_bist_status_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_bist_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t pwq_wqed                     : 1;  /**< PWQ PIP WQE DONE Memory Bist Status. */
 	uint64_t pwq_wp1                      : 1;  /**< PWQ WQE PAGE1 PTR Memory Bist Status. */
@@ -484,14 +807,61 @@ union cvmx_ipd_bist_status
 	struct cvmx_ipd_bist_status_cn30xx    cn38xx;
 	struct cvmx_ipd_bist_status_cn30xx    cn38xxp2;
 	struct cvmx_ipd_bist_status_cn30xx    cn50xx;
-	struct cvmx_ipd_bist_status_s         cn52xx;
-	struct cvmx_ipd_bist_status_s         cn52xxp1;
-	struct cvmx_ipd_bist_status_s         cn56xx;
-	struct cvmx_ipd_bist_status_s         cn56xxp1;
+	struct cvmx_ipd_bist_status_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_18_63               : 46;
+	uint64_t csr_mem                      : 1;  /**< CSR Register Memory Bist Status. */
+	uint64_t csr_ncmd                     : 1;  /**< CSR NCB Commands Memory Bist Status. */
+	uint64_t pwq_wqed                     : 1;  /**< PWQ PIP WQE DONE Memory Bist Status. */
+	uint64_t pwq_wp1                      : 1;  /**< PWQ WQE PAGE1 PTR Memory Bist Status. */
+	uint64_t pwq_pow                      : 1;  /**< PWQ POW MEM Memory Bist Status. */
+	uint64_t ipq_pbe1                     : 1;  /**< IPQ PBE1 Memory Bist Status. */
+	uint64_t ipq_pbe0                     : 1;  /**< IPQ PBE0 Memory Bist Status. */
+	uint64_t pbm3                         : 1;  /**< PBM3 Memory Bist Status. */
+	uint64_t pbm2                         : 1;  /**< PBM2 Memory Bist Status. */
+	uint64_t pbm1                         : 1;  /**< PBM1 Memory Bist Status. */
+	uint64_t pbm0                         : 1;  /**< PBM0 Memory Bist Status. */
+	uint64_t pbm_word                     : 1;  /**< PBM_WORD Memory Bist Status. */
+	uint64_t pwq1                         : 1;  /**< PWQ1 Memory Bist Status. */
+	uint64_t pwq0                         : 1;  /**< PWQ0 Memory Bist Status. */
+	uint64_t prc_off                      : 1;  /**< PRC_OFF Memory Bist Status. */
+	uint64_t ipd_old                      : 1;  /**< IPD_OLD Memory Bist Status. */
+	uint64_t ipd_new                      : 1;  /**< IPD_NEW Memory Bist Status. */
+	uint64_t pwp                          : 1;  /**< PWP Memory Bist Status. */
+#else
+	uint64_t pwp                          : 1;
+	uint64_t ipd_new                      : 1;
+	uint64_t ipd_old                      : 1;
+	uint64_t prc_off                      : 1;
+	uint64_t pwq0                         : 1;
+	uint64_t pwq1                         : 1;
+	uint64_t pbm_word                     : 1;
+	uint64_t pbm0                         : 1;
+	uint64_t pbm1                         : 1;
+	uint64_t pbm2                         : 1;
+	uint64_t pbm3                         : 1;
+	uint64_t ipq_pbe0                     : 1;
+	uint64_t ipq_pbe1                     : 1;
+	uint64_t pwq_pow                      : 1;
+	uint64_t pwq_wp1                      : 1;
+	uint64_t pwq_wqed                     : 1;
+	uint64_t csr_ncmd                     : 1;
+	uint64_t csr_mem                      : 1;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} cn52xx;
+	struct cvmx_ipd_bist_status_cn52xx    cn52xxp1;
+	struct cvmx_ipd_bist_status_cn52xx    cn56xx;
+	struct cvmx_ipd_bist_status_cn52xx    cn56xxp1;
 	struct cvmx_ipd_bist_status_cn30xx    cn58xx;
 	struct cvmx_ipd_bist_status_cn30xx    cn58xxp1;
-	struct cvmx_ipd_bist_status_s         cn63xx;
-	struct cvmx_ipd_bist_status_s         cn63xxp1;
+	struct cvmx_ipd_bist_status_cn52xx    cn61xx;
+	struct cvmx_ipd_bist_status_cn52xx    cn63xx;
+	struct cvmx_ipd_bist_status_cn52xx    cn63xxp1;
+	struct cvmx_ipd_bist_status_cn52xx    cn66xx;
+	struct cvmx_ipd_bist_status_s         cn68xx;
+	struct cvmx_ipd_bist_status_s         cn68xxp1;
+	struct cvmx_ipd_bist_status_cn52xx    cnf71xx;
 };
 typedef union cvmx_ipd_bist_status cvmx_ipd_bist_status_t;
 
@@ -503,14 +873,12 @@ typedef union cvmx_ipd_bist_status cvmx_ipd_bist_status_t;
  * When IPD applies backpressure to a PORT and the corresponding bit in this register is set,
  * the RED Unit will drop packets for that port.
  */
-union cvmx_ipd_bp_prt_red_end
-{
+union cvmx_ipd_bp_prt_red_end {
 	uint64_t u64;
-	struct cvmx_ipd_bp_prt_red_end_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_44_63               : 20;
-	uint64_t prt_enb                      : 44; /**< The port corresponding to the bit position in this
+	struct cvmx_ipd_bp_prt_red_end_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_48_63               : 16;
+	uint64_t prt_enb                      : 48; /**< The port corresponding to the bit position in this
                                                          field will drop all NON-RAW packets to that port
                                                          when port level backpressure is applied to that
                                                          port.  The applying of port-level backpressure for
@@ -518,13 +886,12 @@ union cvmx_ipd_bp_prt_red_end
                                                          value of IPD_PORTX_BP_PAGE_CNT[BP_ENB], nor
                                                          IPD_RED_PORT_ENABLE[PRT_ENB]. */
 #else
-	uint64_t prt_enb                      : 44;
-	uint64_t reserved_44_63               : 20;
+	uint64_t prt_enb                      : 48;
+	uint64_t reserved_48_63               : 16;
 #endif
 	} s;
-	struct cvmx_ipd_bp_prt_red_end_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_bp_prt_red_end_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t prt_enb                      : 36; /**< The port corresponding to the bit position in this
                                                          field, will allow RED to drop back when port level
@@ -541,9 +908,8 @@ union cvmx_ipd_bp_prt_red_end
 	struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx;
 	struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2;
 	struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx;
-	struct cvmx_ipd_bp_prt_red_end_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_bp_prt_red_end_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t prt_enb                      : 40; /**< The port corresponding to the bit position in this
                                                          field, will allow RED to drop back when port level
@@ -561,24 +927,96 @@ union cvmx_ipd_bp_prt_red_end
 	struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xxp1;
 	struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx;
 	struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1;
-	struct cvmx_ipd_bp_prt_red_end_s      cn63xx;
-	struct cvmx_ipd_bp_prt_red_end_s      cn63xxp1;
+	struct cvmx_ipd_bp_prt_red_end_s      cn61xx;
+	struct cvmx_ipd_bp_prt_red_end_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_44_63               : 20;
+	uint64_t prt_enb                      : 44; /**< The port corresponding to the bit position in this
+                                                         field will drop all NON-RAW packets to that port
+                                                         when port level backpressure is applied to that
+                                                         port.  The applying of port-level backpressure for
+                                                         this dropping does not take into consideration the
+                                                         value of IPD_PORTX_BP_PAGE_CNT[BP_ENB], nor
+                                                         IPD_RED_PORT_ENABLE[PRT_ENB]. */
+#else
+	uint64_t prt_enb                      : 44;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} cn63xx;
+	struct cvmx_ipd_bp_prt_red_end_cn63xx cn63xxp1;
+	struct cvmx_ipd_bp_prt_red_end_s      cn66xx;
+	struct cvmx_ipd_bp_prt_red_end_s      cnf71xx;
 };
 typedef union cvmx_ipd_bp_prt_red_end cvmx_ipd_bp_prt_red_end_t;
 
 /**
+ * cvmx_ipd_bpid#_mbuf_th
+ *
+ * 0x2000 2FFF
+ *
+ *                  IPD_BPIDX_MBUF_TH = IPD BPID  MBUFF Threshold
+ *
+ * The number of MBUFFs in use by the BPID, that when exceeded, backpressure will be applied to the BPID.
+ */
+union cvmx_ipd_bpidx_mbuf_th {
+	uint64_t u64;
+	struct cvmx_ipd_bpidx_mbuf_th_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_18_63               : 46;
+	uint64_t bp_enb                       : 1;  /**< When set '1' BP will be applied, if '0' BP will
+                                                         not be applied to bpid. */
+	uint64_t page_cnt                     : 17; /**< The number of page pointers assigned to
+                                                         the BPID, that when exceeded will cause
+                                                         back-pressure to be applied to the BPID.
+                                                         This value is in 256 page-pointer increments,
+                                                         (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */
+#else
+	uint64_t page_cnt                     : 17;
+	uint64_t bp_enb                       : 1;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_ipd_bpidx_mbuf_th_s       cn68xx;
+	struct cvmx_ipd_bpidx_mbuf_th_s       cn68xxp1;
+};
+typedef union cvmx_ipd_bpidx_mbuf_th cvmx_ipd_bpidx_mbuf_th_t;
+
+/**
+ * cvmx_ipd_bpid_bp_counter#
+ *
+ * RESERVE SPACE UPTO 0x2FFF
+ *
+ * 0x3000 0x3ffff
+ *
+ * IPD_BPID_BP_COUNTERX = MBUF BPID Counters used to generate Back Pressure Per BPID.
+ */
+union cvmx_ipd_bpid_bp_counterx {
+	uint64_t u64;
+	struct cvmx_ipd_bpid_bp_counterx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_25_63               : 39;
+	uint64_t cnt_val                      : 25; /**< Number of MBUFs being used by data on this BPID. */
+#else
+	uint64_t cnt_val                      : 25;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_ipd_bpid_bp_counterx_s    cn68xx;
+	struct cvmx_ipd_bpid_bp_counterx_s    cn68xxp1;
+};
+typedef union cvmx_ipd_bpid_bp_counterx cvmx_ipd_bpid_bp_counterx_t;
+
+/**
  * cvmx_ipd_clk_count
  *
  * IPD_CLK_COUNT = IPD Clock Count
  *
  * Counts the number of core clocks periods since the de-asserition of reset.
  */
-union cvmx_ipd_clk_count
-{
+union cvmx_ipd_clk_count {
 	uint64_t u64;
-	struct cvmx_ipd_clk_count_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_clk_count_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t clk_cnt                      : 64; /**< This counter will be zeroed when reset is applied
                                                          and will increment every rising edge of the
                                                          core-clock. */
@@ -597,24 +1035,56 @@ union cvmx_ipd_clk_count
 	struct cvmx_ipd_clk_count_s           cn56xxp1;
 	struct cvmx_ipd_clk_count_s           cn58xx;
 	struct cvmx_ipd_clk_count_s           cn58xxp1;
+	struct cvmx_ipd_clk_count_s           cn61xx;
 	struct cvmx_ipd_clk_count_s           cn63xx;
 	struct cvmx_ipd_clk_count_s           cn63xxp1;
+	struct cvmx_ipd_clk_count_s           cn66xx;
+	struct cvmx_ipd_clk_count_s           cn68xx;
+	struct cvmx_ipd_clk_count_s           cn68xxp1;
+	struct cvmx_ipd_clk_count_s           cnf71xx;
 };
 typedef union cvmx_ipd_clk_count cvmx_ipd_clk_count_t;
 
 /**
+ * cvmx_ipd_credits
+ *
+ * IPD_CREDITS = IPD Credits
+ *
+ * The credits allowed for IPD.
+ */
+union cvmx_ipd_credits {
+	uint64_t u64;
+	struct cvmx_ipd_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t iob_wrc                      : 8;  /**< The present number of credits available for
+                                                         stores to the IOB. */
+	uint64_t iob_wr                       : 8;  /**< The number of command credits the IPD has to send
+                                                         stores to the IOB. Legal values for this field
+                                                         are 1-8 (a value of 0 will be treated as a 1 and
+                                                         a value greater than 8 will be treated as an 8. */
+#else
+	uint64_t iob_wr                       : 8;
+	uint64_t iob_wrc                      : 8;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ipd_credits_s             cn68xx;
+	struct cvmx_ipd_credits_s             cn68xxp1;
+};
+typedef union cvmx_ipd_credits cvmx_ipd_credits_t;
+
+/**
  * cvmx_ipd_ctl_status
  *
  * IPD_CTL_STATUS = IPD's Control Status Register
  *
  * The number of words in a MBUFF used for packet data store.
  */
-union cvmx_ipd_ctl_status
-{
+union cvmx_ipd_ctl_status {
 	uint64_t u64;
-	struct cvmx_ipd_ctl_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t use_sop                      : 1;  /**< When '1' the SOP sent by the MAC will be used in
                                                          place of the SOP generated by the IPD. */
@@ -725,9 +1195,8 @@ union cvmx_ipd_ctl_status
 	uint64_t reserved_18_63               : 46;
 #endif
 	} s;
-	struct cvmx_ipd_ctl_status_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_ctl_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t len_m8                       : 1;  /**< Setting of this bit will subtract 8 from the
                                                          data-length field in the header written wo the
@@ -786,9 +1255,8 @@ union cvmx_ipd_ctl_status
 	} cn30xx;
 	struct cvmx_ipd_ctl_status_cn30xx     cn31xx;
 	struct cvmx_ipd_ctl_status_cn30xx     cn38xx;
-	struct cvmx_ipd_ctl_status_cn38xxp2
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_ctl_status_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t reset                        : 1;  /**< When set '1' causes a reset of the IPD, except
                                                          RSL. */
@@ -834,9 +1302,8 @@ union cvmx_ipd_ctl_status
 	uint64_t reserved_9_63                : 55;
 #endif
 	} cn38xxp2;
-	struct cvmx_ipd_ctl_status_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_ctl_status_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_15_63               : 49;
 	uint64_t no_wptr                      : 1;  /**< When set '1' the WQE pointers will not be used and
                                                          the WQE will be located at the front of the packet. */
@@ -917,9 +1384,8 @@ union cvmx_ipd_ctl_status
 	struct cvmx_ipd_ctl_status_cn50xx     cn52xxp1;
 	struct cvmx_ipd_ctl_status_cn50xx     cn56xx;
 	struct cvmx_ipd_ctl_status_cn50xx     cn56xxp1;
-	struct cvmx_ipd_ctl_status_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_ctl_status_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t ipd_full                     : 1;  /**< When clear '0' the IPD acts normaly.
                                                          When set '1' the IPD drive the IPD_BUFF_FULL line to
@@ -989,10 +1455,10 @@ union cvmx_ipd_ctl_status
 #endif
 	} cn58xx;
 	struct cvmx_ipd_ctl_status_cn58xx     cn58xxp1;
+	struct cvmx_ipd_ctl_status_s          cn61xx;
 	struct cvmx_ipd_ctl_status_s          cn63xx;
-	struct cvmx_ipd_ctl_status_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_ctl_status_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t clken                        : 1;  /**< Controls the conditional clocking within IPD
                                                          0=Allow HW to control the clocks
@@ -1095,23 +1561,200 @@ union cvmx_ipd_ctl_status
 	uint64_t reserved_16_63               : 48;
 #endif
 	} cn63xxp1;
+	struct cvmx_ipd_ctl_status_s          cn66xx;
+	struct cvmx_ipd_ctl_status_s          cn68xx;
+	struct cvmx_ipd_ctl_status_s          cn68xxp1;
+	struct cvmx_ipd_ctl_status_s          cnf71xx;
 };
 typedef union cvmx_ipd_ctl_status cvmx_ipd_ctl_status_t;
 
 /**
+ * cvmx_ipd_ecc_ctl
+ *
+ * IPD_ECC_CTL = IPD ECC Control
+ *
+ * Allows inserting ECC errors for testing.
+ */
+union cvmx_ipd_ecc_ctl {
+	uint64_t u64;
+	struct cvmx_ipd_ecc_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_8_63                : 56;
+	uint64_t pm3_syn                      : 2;  /**< Flip the syndrom to generate 1-bit/2-bits error
+                                                         for testing of Packet Memory 3.
+                                                          2'b00       : No Error Generation
+                                                          2'b10, 2'b01: Flip 1 bit
+                                                          2'b11       : Flip 2 bits */
+	uint64_t pm2_syn                      : 2;  /**< Flip the syndrom to generate 1-bit/2-bits error
+                                                         for testing of Packet Memory 2.
+                                                          2'b00       : No Error Generation
+                                                          2'b10, 2'b01: Flip 1 bit
+                                                          2'b11       : Flip 2 bits */
+	uint64_t pm1_syn                      : 2;  /**< Flip the syndrom to generate 1-bit/2-bits error
+                                                         for testing of Packet Memory 1.
+                                                          2'b00       : No Error Generation
+                                                          2'b10, 2'b01: Flip 1 bit
+                                                          2'b11       : Flip 2 bits */
+	uint64_t pm0_syn                      : 2;  /**< Flip the syndrom to generate 1-bit/2-bits error
+                                                         for testing of Packet Memory 0.
+                                                          2'b00       : No Error Generation
+                                                          2'b10, 2'b01: Flip 1 bit
+                                                          2'b11       : Flip 2 bits */
+#else
+	uint64_t pm0_syn                      : 2;
+	uint64_t pm1_syn                      : 2;
+	uint64_t pm2_syn                      : 2;
+	uint64_t pm3_syn                      : 2;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_ipd_ecc_ctl_s             cn68xx;
+	struct cvmx_ipd_ecc_ctl_s             cn68xxp1;
+};
+typedef union cvmx_ipd_ecc_ctl cvmx_ipd_ecc_ctl_t;
+
+/**
+ * cvmx_ipd_free_ptr_fifo_ctl
+ *
+ * IPD_FREE_PTR_FIFO_CTL = IPD's FREE Pointer FIFO Control
+ *
+ * Allows reading of the Page-Pointers stored in the IPD's FREE Fifo.
+ * See also the IPD_FREE_PTR_VALUE
+ */
+union cvmx_ipd_free_ptr_fifo_ctl {
+	uint64_t u64;
+	struct cvmx_ipd_free_ptr_fifo_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t max_cnts                     : 7;  /**< Maximum number of Packet-Pointers or WQE-Pointers
+                                                         that COULD be in the FIFO.
+                                                         When IPD_CTL_STATUS[NO_WPTR] is set '1' this field
+                                                         only represents the Max number of Packet-Pointers,
+                                                         WQE-Pointers are not used in this mode. */
+	uint64_t wraddr                       : 8;  /**< Present FIFO WQE Read address. */
+	uint64_t praddr                       : 8;  /**< Present FIFO Packet Read address. */
+	uint64_t cena                         : 1;  /**< Active low Chip Enable to the read the
+                                                         pwp_fifo. This bit also controls the MUX-select
+                                                         that steers [RADDR] to the pwp_fifo.
+                                                         *WARNING - Setting this field to '0' will allow
+                                                         reading of the memories thorugh the PTR field,
+                                                         but will cause unpredictable operation of the IPD
+                                                         under normal operation. */
+	uint64_t raddr                        : 8;  /**< Sets the address to read from in the pwp_fifo.
+                                                         Addresses 0 through 63 contain Packet-Pointers and
+                                                         addresses 64 through 127 contain WQE-Pointers.
+                                                         When IPD_CTL_STATUS[NO_WPTR] is set '1' addresses
+                                                         64 through 127 are not valid. */
+#else
+	uint64_t raddr                        : 8;
+	uint64_t cena                         : 1;
+	uint64_t praddr                       : 8;
+	uint64_t wraddr                       : 8;
+	uint64_t max_cnts                     : 7;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ipd_free_ptr_fifo_ctl_s   cn68xx;
+	struct cvmx_ipd_free_ptr_fifo_ctl_s   cn68xxp1;
+};
+typedef union cvmx_ipd_free_ptr_fifo_ctl cvmx_ipd_free_ptr_fifo_ctl_t;
+
+/**
+ * cvmx_ipd_free_ptr_value
+ *
+ * IPD_FREE_PTR_VALUE = IPD's FREE Pointer Value
+ *
+ * The value of the pointer selected through the IPD_FREE_PTR_FIFO_CTL
+ */
+union cvmx_ipd_free_ptr_value {
+	uint64_t u64;
+	struct cvmx_ipd_free_ptr_value_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_33_63               : 31;
+	uint64_t ptr                          : 33; /**< The output of the pwp_fifo. */
+#else
+	uint64_t ptr                          : 33;
+	uint64_t reserved_33_63               : 31;
+#endif
+	} s;
+	struct cvmx_ipd_free_ptr_value_s      cn68xx;
+	struct cvmx_ipd_free_ptr_value_s      cn68xxp1;
+};
+typedef union cvmx_ipd_free_ptr_value cvmx_ipd_free_ptr_value_t;
+
+/**
+ * cvmx_ipd_hold_ptr_fifo_ctl
+ *
+ * IPD_HOLD_PTR_FIFO_CTL = IPD's Holding Pointer FIFO Control
+ *
+ * Allows reading of the Page-Pointers stored in the IPD's Holding Fifo.
+ */
+union cvmx_ipd_hold_ptr_fifo_ctl {
+	uint64_t u64;
+	struct cvmx_ipd_hold_ptr_fifo_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_43_63               : 21;
+	uint64_t ptr                          : 33; /**< The output of the holding-fifo. */
+	uint64_t max_pkt                      : 3;  /**< Maximum number of Packet-Pointers that COULD be
+                                                         in the FIFO. */
+	uint64_t praddr                       : 3;  /**< Present Packet-Pointer read address. */
+	uint64_t cena                         : 1;  /**< Active low Chip Enable that controls the
+                                                         MUX-select that steers [RADDR] to the fifo.
+                                                         *WARNING - Setting this field to '0' will allow
+                                                         reading of the memories thorugh the PTR field,
+                                                         but will cause unpredictable operation of the IPD
+                                                         under normal operation. */
+	uint64_t raddr                        : 3;  /**< Sets the address to read from in the holding.
+                                                         fifo in the IPD. This FIFO holds Packet-Pointers
+                                                         to be used for packet data storage. */
+#else
+	uint64_t raddr                        : 3;
+	uint64_t cena                         : 1;
+	uint64_t praddr                       : 3;
+	uint64_t max_pkt                      : 3;
+	uint64_t ptr                          : 33;
+	uint64_t reserved_43_63               : 21;
+#endif
+	} s;
+	struct cvmx_ipd_hold_ptr_fifo_ctl_s   cn68xx;
+	struct cvmx_ipd_hold_ptr_fifo_ctl_s   cn68xxp1;
+};
+typedef union cvmx_ipd_hold_ptr_fifo_ctl cvmx_ipd_hold_ptr_fifo_ctl_t;
+
+/**
  * cvmx_ipd_int_enb
  *
  * IPD_INTERRUPT_ENB = IPD Interrupt Enable Register
  *
  * Used to enable the various interrupting conditions of IPD
  */
-union cvmx_ipd_int_enb
-{
+union cvmx_ipd_int_enb {
 	uint64_t u64;
-	struct cvmx_ipd_int_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_12_63               : 52;
+	struct cvmx_ipd_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_23_63               : 41;
+	uint64_t pw3_dbe                      : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t pw3_sbe                      : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t pw2_dbe                      : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t pw2_sbe                      : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t pw1_dbe                      : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t pw1_sbe                      : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t pw0_dbe                      : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t pw0_sbe                      : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t dat                          : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t eop                          : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t sop                          : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
 	uint64_t pq_sub                       : 1;  /**< Allows an interrupt to be sent when the
                                                          corresponding bit in the IPD_INT_SUM is set. */
 	uint64_t pq_add                       : 1;  /**< Allows an interrupt to be sent when the
@@ -1149,12 +1792,22 @@ union cvmx_ipd_int_enb
 	uint64_t bc_ovr                       : 1;
 	uint64_t pq_add                       : 1;
 	uint64_t pq_sub                       : 1;
-	uint64_t reserved_12_63               : 52;
+	uint64_t sop                          : 1;
+	uint64_t eop                          : 1;
+	uint64_t dat                          : 1;
+	uint64_t pw0_sbe                      : 1;
+	uint64_t pw0_dbe                      : 1;
+	uint64_t pw1_sbe                      : 1;
+	uint64_t pw1_dbe                      : 1;
+	uint64_t pw2_sbe                      : 1;
+	uint64_t pw2_dbe                      : 1;
+	uint64_t pw3_sbe                      : 1;
+	uint64_t pw3_dbe                      : 1;
+	uint64_t reserved_23_63               : 41;
 #endif
 	} s;
-	struct cvmx_ipd_int_enb_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_int_enb_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t bp_sub                       : 1;  /**< Enables interrupts when a backpressure subtract
                                                          has an illegal value. */
@@ -1176,9 +1829,8 @@ union cvmx_ipd_int_enb
 #endif
 	} cn30xx;
 	struct cvmx_ipd_int_enb_cn30xx        cn31xx;
-	struct cvmx_ipd_int_enb_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_int_enb_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t bc_ovr                       : 1;  /**< Allows an interrupt to be sent when the
                                                          corresponding bit in the IPD_INT_SUM is set.
@@ -1221,14 +1873,61 @@ union cvmx_ipd_int_enb
 	} cn38xx;
 	struct cvmx_ipd_int_enb_cn30xx        cn38xxp2;
 	struct cvmx_ipd_int_enb_cn38xx        cn50xx;
-	struct cvmx_ipd_int_enb_s             cn52xx;
-	struct cvmx_ipd_int_enb_s             cn52xxp1;
-	struct cvmx_ipd_int_enb_s             cn56xx;
-	struct cvmx_ipd_int_enb_s             cn56xxp1;
+	struct cvmx_ipd_int_enb_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_12_63               : 52;
+	uint64_t pq_sub                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t pq_add                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t bc_ovr                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t d_coll                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t c_coll                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t cc_ovr                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t dc_ovr                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t bp_sub                       : 1;  /**< Enables interrupts when a backpressure subtract
+                                                         has an illegal value. */
+	uint64_t prc_par3                     : 1;  /**< Enable parity error interrupts for bits
+                                                         [127:96] of the PBM memory. */
+	uint64_t prc_par2                     : 1;  /**< Enable parity error interrupts for bits
+                                                         [95:64] of the PBM memory. */
+	uint64_t prc_par1                     : 1;  /**< Enable parity error interrupts for bits
+                                                         [63:32] of the PBM memory. */
+	uint64_t prc_par0                     : 1;  /**< Enable parity error interrupts for bits
+                                                         [31:0] of the PBM memory. */
+#else
+	uint64_t prc_par0                     : 1;
+	uint64_t prc_par1                     : 1;
+	uint64_t prc_par2                     : 1;
+	uint64_t prc_par3                     : 1;
+	uint64_t bp_sub                       : 1;
+	uint64_t dc_ovr                       : 1;
+	uint64_t cc_ovr                       : 1;
+	uint64_t c_coll                       : 1;
+	uint64_t d_coll                       : 1;
+	uint64_t bc_ovr                       : 1;
+	uint64_t pq_add                       : 1;
+	uint64_t pq_sub                       : 1;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn52xx;
+	struct cvmx_ipd_int_enb_cn52xx        cn52xxp1;
+	struct cvmx_ipd_int_enb_cn52xx        cn56xx;
+	struct cvmx_ipd_int_enb_cn52xx        cn56xxp1;
 	struct cvmx_ipd_int_enb_cn38xx        cn58xx;
 	struct cvmx_ipd_int_enb_cn38xx        cn58xxp1;
-	struct cvmx_ipd_int_enb_s             cn63xx;
-	struct cvmx_ipd_int_enb_s             cn63xxp1;
+	struct cvmx_ipd_int_enb_cn52xx        cn61xx;
+	struct cvmx_ipd_int_enb_cn52xx        cn63xx;
+	struct cvmx_ipd_int_enb_cn52xx        cn63xxp1;
+	struct cvmx_ipd_int_enb_cn52xx        cn66xx;
+	struct cvmx_ipd_int_enb_s             cn68xx;
+	struct cvmx_ipd_int_enb_s             cn68xxp1;
+	struct cvmx_ipd_int_enb_cn52xx        cnf71xx;
 };
 typedef union cvmx_ipd_int_enb cvmx_ipd_int_enb_t;
 
@@ -1239,13 +1938,37 @@ typedef union cvmx_ipd_int_enb cvmx_ipd_int_enb_t;
  *
  * Set when an interrupt condition occurs, write '1' to clear.
  */
-union cvmx_ipd_int_sum
-{
+union cvmx_ipd_int_sum {
 	uint64_t u64;
-	struct cvmx_ipd_int_sum_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_12_63               : 52;
+	struct cvmx_ipd_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_23_63               : 41;
+	uint64_t pw3_dbe                      : 1;  /**< Packet memory 3 had ECC DBE. */
+	uint64_t pw3_sbe                      : 1;  /**< Packet memory 3 had ECC SBE. */
+	uint64_t pw2_dbe                      : 1;  /**< Packet memory 2 had ECC DBE. */
+	uint64_t pw2_sbe                      : 1;  /**< Packet memory 2 had ECC SBE. */
+	uint64_t pw1_dbe                      : 1;  /**< Packet memory 1 had ECC DBE. */
+	uint64_t pw1_sbe                      : 1;  /**< Packet memory 1 had ECC SBE. */
+	uint64_t pw0_dbe                      : 1;  /**< Packet memory 0 had ECC DBE. */
+	uint64_t pw0_sbe                      : 1;  /**< Packet memory 0 had ECC SBE. */
+	uint64_t dat                          : 1;  /**< Set when a data arrives before a SOP for the same
+                                                         reasm-id for a packet.
+                                                         The first detected error associated with bits [14:12]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared.
+                                                         Also see IPD_PKT_ERR. */
+	uint64_t eop                          : 1;  /**< Set when a EOP is followed by an EOP for the same
+                                                         reasm-id for a packet.
+                                                         The first detected error associated with bits [14:12]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared.
+                                                         Also see IPD_PKT_ERR. */
+	uint64_t sop                          : 1;  /**< Set when a SOP is followed by an SOP for the same
+                                                         reasm-id for a packet.
+                                                         The first detected error associated with bits [14:12]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared.
+                                                         Also see IPD_PKT_ERR. */
 	uint64_t pq_sub                       : 1;  /**< Set when a port-qos does an sub to the count
                                                          that causes the counter to wrap. */
 	uint64_t pq_add                       : 1;  /**< Set when a port-qos does an add to the count
@@ -1280,12 +2003,22 @@ union cvmx_ipd_int_sum
 	uint64_t bc_ovr                       : 1;
 	uint64_t pq_add                       : 1;
 	uint64_t pq_sub                       : 1;
-	uint64_t reserved_12_63               : 52;
+	uint64_t sop                          : 1;
+	uint64_t eop                          : 1;
+	uint64_t dat                          : 1;
+	uint64_t pw0_sbe                      : 1;
+	uint64_t pw0_dbe                      : 1;
+	uint64_t pw1_sbe                      : 1;
+	uint64_t pw1_dbe                      : 1;
+	uint64_t pw2_sbe                      : 1;
+	uint64_t pw2_dbe                      : 1;
+	uint64_t pw3_sbe                      : 1;
+	uint64_t pw3_dbe                      : 1;
+	uint64_t reserved_23_63               : 41;
 #endif
 	} s;
-	struct cvmx_ipd_int_sum_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_int_sum_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t bp_sub                       : 1;  /**< Set when a backpressure subtract is done with a
                                                          supplied illegal value. */
@@ -1307,9 +2040,8 @@ union cvmx_ipd_int_sum
 #endif
 	} cn30xx;
 	struct cvmx_ipd_int_sum_cn30xx        cn31xx;
-	struct cvmx_ipd_int_sum_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_int_sum_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t bc_ovr                       : 1;  /**< Set when the byte-count to send to IOB overflows.
                                                          This is a PASS-3 Field. */
@@ -1349,30 +2081,120 @@ union cvmx_ipd_int_sum
 	} cn38xx;
 	struct cvmx_ipd_int_sum_cn30xx        cn38xxp2;
 	struct cvmx_ipd_int_sum_cn38xx        cn50xx;
-	struct cvmx_ipd_int_sum_s             cn52xx;
-	struct cvmx_ipd_int_sum_s             cn52xxp1;
-	struct cvmx_ipd_int_sum_s             cn56xx;
-	struct cvmx_ipd_int_sum_s             cn56xxp1;
+	struct cvmx_ipd_int_sum_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_12_63               : 52;
+	uint64_t pq_sub                       : 1;  /**< Set when a port-qos does an sub to the count
+                                                         that causes the counter to wrap. */
+	uint64_t pq_add                       : 1;  /**< Set when a port-qos does an add to the count
+                                                         that causes the counter to wrap. */
+	uint64_t bc_ovr                       : 1;  /**< Set when the byte-count to send to IOB overflows. */
+	uint64_t d_coll                       : 1;  /**< Set when the packet/WQE data to be sent to IOB
+                                                         collides. */
+	uint64_t c_coll                       : 1;  /**< Set when the packet/WQE commands to be sent to IOB
+                                                         collides. */
+	uint64_t cc_ovr                       : 1;  /**< Set when the command credits to the IOB overflow. */
+	uint64_t dc_ovr                       : 1;  /**< Set when the data credits to the IOB overflow. */
+	uint64_t bp_sub                       : 1;  /**< Set when a backpressure subtract is done with a
+                                                         supplied illegal value. */
+	uint64_t prc_par3                     : 1;  /**< Set when a parity error is dected for bits
+                                                         [127:96] of the PBM memory. */
+	uint64_t prc_par2                     : 1;  /**< Set when a parity error is dected for bits
+                                                         [95:64] of the PBM memory. */
+	uint64_t prc_par1                     : 1;  /**< Set when a parity error is dected for bits
+                                                         [63:32] of the PBM memory. */
+	uint64_t prc_par0                     : 1;  /**< Set when a parity error is dected for bits
+                                                         [31:0] of the PBM memory. */
+#else
+	uint64_t prc_par0                     : 1;
+	uint64_t prc_par1                     : 1;
+	uint64_t prc_par2                     : 1;
+	uint64_t prc_par3                     : 1;
+	uint64_t bp_sub                       : 1;
+	uint64_t dc_ovr                       : 1;
+	uint64_t cc_ovr                       : 1;
+	uint64_t c_coll                       : 1;
+	uint64_t d_coll                       : 1;
+	uint64_t bc_ovr                       : 1;
+	uint64_t pq_add                       : 1;
+	uint64_t pq_sub                       : 1;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn52xx;
+	struct cvmx_ipd_int_sum_cn52xx        cn52xxp1;
+	struct cvmx_ipd_int_sum_cn52xx        cn56xx;
+	struct cvmx_ipd_int_sum_cn52xx        cn56xxp1;
 	struct cvmx_ipd_int_sum_cn38xx        cn58xx;
 	struct cvmx_ipd_int_sum_cn38xx        cn58xxp1;
-	struct cvmx_ipd_int_sum_s             cn63xx;
-	struct cvmx_ipd_int_sum_s             cn63xxp1;
+	struct cvmx_ipd_int_sum_cn52xx        cn61xx;
+	struct cvmx_ipd_int_sum_cn52xx        cn63xx;
+	struct cvmx_ipd_int_sum_cn52xx        cn63xxp1;
+	struct cvmx_ipd_int_sum_cn52xx        cn66xx;
+	struct cvmx_ipd_int_sum_s             cn68xx;
+	struct cvmx_ipd_int_sum_s             cn68xxp1;
+	struct cvmx_ipd_int_sum_cn52xx        cnf71xx;
 };
 typedef union cvmx_ipd_int_sum cvmx_ipd_int_sum_t;
 
 /**
+ * cvmx_ipd_next_pkt_ptr
+ *
+ * IPD_NEXT_PKT_PTR = IPD's Next Packet Pointer
+ *
+ * The value of the packet-pointer fetched and in the valid register.
+ */
+union cvmx_ipd_next_pkt_ptr {
+	uint64_t u64;
+	struct cvmx_ipd_next_pkt_ptr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_33_63               : 31;
+	uint64_t ptr                          : 33; /**< Pointer value. */
+#else
+	uint64_t ptr                          : 33;
+	uint64_t reserved_33_63               : 31;
+#endif
+	} s;
+	struct cvmx_ipd_next_pkt_ptr_s        cn68xx;
+	struct cvmx_ipd_next_pkt_ptr_s        cn68xxp1;
+};
+typedef union cvmx_ipd_next_pkt_ptr cvmx_ipd_next_pkt_ptr_t;
+
+/**
+ * cvmx_ipd_next_wqe_ptr
+ *
+ * IPD_NEXT_WQE_PTR = IPD's NEXT_WQE Pointer
+ *
+ * The value of the WQE-pointer fetched and in the valid register.
+ */
+union cvmx_ipd_next_wqe_ptr {
+	uint64_t u64;
+	struct cvmx_ipd_next_wqe_ptr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_33_63               : 31;
+	uint64_t ptr                          : 33; /**< Pointer value.
+                                                         When IPD_CTL_STATUS[NO_WPTR] is set '1' this field
+                                                         represents a Packet-Pointer NOT a WQE pointer. */
+#else
+	uint64_t ptr                          : 33;
+	uint64_t reserved_33_63               : 31;
+#endif
+	} s;
+	struct cvmx_ipd_next_wqe_ptr_s        cn68xx;
+	struct cvmx_ipd_next_wqe_ptr_s        cn68xxp1;
+};
+typedef union cvmx_ipd_next_wqe_ptr cvmx_ipd_next_wqe_ptr_t;
+
+/**
  * cvmx_ipd_not_1st_mbuff_skip
  *
  * IPD_NOT_1ST_MBUFF_SKIP = IPD Not First MBUFF Word Skip Size
  *
  * The number of words that the IPD will skip when writing any MBUFF that is not the first.
  */
-union cvmx_ipd_not_1st_mbuff_skip
-{
+union cvmx_ipd_not_1st_mbuff_skip {
 	uint64_t u64;
-	struct cvmx_ipd_not_1st_mbuff_skip_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_not_1st_mbuff_skip_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t skip_sz                      : 6;  /**< The number of 8-byte words from the top of any
                                                          MBUFF, that is not the 1st MBUFF, that the IPD
@@ -1396,24 +2218,63 @@ union cvmx_ipd_not_1st_mbuff_skip
 	struct cvmx_ipd_not_1st_mbuff_skip_s  cn56xxp1;
 	struct cvmx_ipd_not_1st_mbuff_skip_s  cn58xx;
 	struct cvmx_ipd_not_1st_mbuff_skip_s  cn58xxp1;
+	struct cvmx_ipd_not_1st_mbuff_skip_s  cn61xx;
 	struct cvmx_ipd_not_1st_mbuff_skip_s  cn63xx;
 	struct cvmx_ipd_not_1st_mbuff_skip_s  cn63xxp1;
+	struct cvmx_ipd_not_1st_mbuff_skip_s  cn66xx;
+	struct cvmx_ipd_not_1st_mbuff_skip_s  cn68xx;
+	struct cvmx_ipd_not_1st_mbuff_skip_s  cn68xxp1;
+	struct cvmx_ipd_not_1st_mbuff_skip_s  cnf71xx;
 };
 typedef union cvmx_ipd_not_1st_mbuff_skip cvmx_ipd_not_1st_mbuff_skip_t;
 
 /**
+ * cvmx_ipd_on_bp_drop_pkt#
+ *
+ * RESERVE SPACE UPTO 0x3FFF
+ *
+ *
+ * RESERVED FOR FORMER IPD_SUB_PKIND_FCS - MOVED TO PIP
+ *
+ * RESERVE 4008 - 40FF
+ *
+ *
+ *                  IPD_ON_BP_DROP_PKT = IPD On Backpressure Drop Packet
+ *
+ * When IPD applies backpressure to a BPID and the corresponding bit in this register is set,
+ * then previously received packets will be dropped when processed.
+ */
+union cvmx_ipd_on_bp_drop_pktx {
+	uint64_t u64;
+	struct cvmx_ipd_on_bp_drop_pktx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t prt_enb                      : 64; /**< The BPID corresponding to the bit position in this
+                                                         field will drop all NON-RAW packets to that BPID
+                                                         when BPID level backpressure is applied to that
+                                                         BPID.  The applying of BPID-level backpressure for
+                                                         this dropping does not take into consideration the
+                                                         value of IPD_BPIDX_MBUF_TH[BP_ENB], nor
+                                                         IPD_RED_BPID_ENABLE[PRT_ENB]. */
+#else
+	uint64_t prt_enb                      : 64;
+#endif
+	} s;
+	struct cvmx_ipd_on_bp_drop_pktx_s     cn68xx;
+	struct cvmx_ipd_on_bp_drop_pktx_s     cn68xxp1;
+};
+typedef union cvmx_ipd_on_bp_drop_pktx cvmx_ipd_on_bp_drop_pktx_t;
+
+/**
  * cvmx_ipd_packet_mbuff_size
  *
  * IPD_PACKET_MBUFF_SIZE = IPD's PACKET MUBUF Size In Words
  *
  * The number of words in a MBUFF used for packet data store.
  */
-union cvmx_ipd_packet_mbuff_size
-{
+union cvmx_ipd_packet_mbuff_size {
 	uint64_t u64;
-	struct cvmx_ipd_packet_mbuff_size_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_packet_mbuff_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t mb_size                      : 12; /**< The number of 8-byte words in a MBUF.
                                                          This must be a number in the range of 32 to
@@ -1436,24 +2297,54 @@ union cvmx_ipd_packet_mbuff_size
 	struct cvmx_ipd_packet_mbuff_size_s   cn56xxp1;
 	struct cvmx_ipd_packet_mbuff_size_s   cn58xx;
 	struct cvmx_ipd_packet_mbuff_size_s   cn58xxp1;
+	struct cvmx_ipd_packet_mbuff_size_s   cn61xx;
 	struct cvmx_ipd_packet_mbuff_size_s   cn63xx;
 	struct cvmx_ipd_packet_mbuff_size_s   cn63xxp1;
+	struct cvmx_ipd_packet_mbuff_size_s   cn66xx;
+	struct cvmx_ipd_packet_mbuff_size_s   cn68xx;
+	struct cvmx_ipd_packet_mbuff_size_s   cn68xxp1;
+	struct cvmx_ipd_packet_mbuff_size_s   cnf71xx;
 };
 typedef union cvmx_ipd_packet_mbuff_size cvmx_ipd_packet_mbuff_size_t;
 
 /**
+ * cvmx_ipd_pkt_err
+ *
+ * IPD_PKT_ERR = IPD Packet Error Register
+ *
+ * Provides status about the failing packet recevie error.
+ */
+union cvmx_ipd_pkt_err {
+	uint64_t u64;
+	struct cvmx_ipd_pkt_err_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_6_63                : 58;
+	uint64_t reasm                        : 6;  /**< When IPD_INT_SUM[14:12] bit is set, this field
+                                                         latches the failing reasm number associated with
+                                                         the IPD_INT_SUM[14:12] bit set.
+                                                         Values 0-62 can be seen here, reasm-id 63 is not
+                                                         used. */
+#else
+	uint64_t reasm                        : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_ipd_pkt_err_s             cn68xx;
+	struct cvmx_ipd_pkt_err_s             cn68xxp1;
+};
+typedef union cvmx_ipd_pkt_err cvmx_ipd_pkt_err_t;
+
+/**
  * cvmx_ipd_pkt_ptr_valid
  *
  * IPD_PKT_PTR_VALID = IPD's Packet Pointer Valid
  *
  * The value of the packet-pointer fetched and in the valid register.
  */
-union cvmx_ipd_pkt_ptr_valid
-{
+union cvmx_ipd_pkt_ptr_valid {
 	uint64_t u64;
-	struct cvmx_ipd_pkt_ptr_valid_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_pkt_ptr_valid_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t ptr                          : 29; /**< Pointer value. */
 #else
@@ -1471,8 +2362,11 @@ union cvmx_ipd_pkt_ptr_valid
 	struct cvmx_ipd_pkt_ptr_valid_s       cn56xxp1;
 	struct cvmx_ipd_pkt_ptr_valid_s       cn58xx;
 	struct cvmx_ipd_pkt_ptr_valid_s       cn58xxp1;
+	struct cvmx_ipd_pkt_ptr_valid_s       cn61xx;
 	struct cvmx_ipd_pkt_ptr_valid_s       cn63xx;
 	struct cvmx_ipd_pkt_ptr_valid_s       cn63xxp1;
+	struct cvmx_ipd_pkt_ptr_valid_s       cn66xx;
+	struct cvmx_ipd_pkt_ptr_valid_s       cnf71xx;
 };
 typedef union cvmx_ipd_pkt_ptr_valid cvmx_ipd_pkt_ptr_valid_t;
 
@@ -1485,12 +2379,10 @@ typedef union cvmx_ipd_pkt_ptr_valid cvmx_ipd_pkt_ptr_valid_t;
  * See also IPD_PORTX_BP_PAGE_CNT2
  * See also IPD_PORTX_BP_PAGE_CNT3
  */
-union cvmx_ipd_portx_bp_page_cnt
-{
+union cvmx_ipd_portx_bp_page_cnt {
 	uint64_t u64;
-	struct cvmx_ipd_portx_bp_page_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_portx_bp_page_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t bp_enb                       : 1;  /**< When set '1' BP will be applied, if '0' BP will
                                                          not be applied to port. */
@@ -1516,8 +2408,11 @@ union cvmx_ipd_portx_bp_page_cnt
 	struct cvmx_ipd_portx_bp_page_cnt_s   cn56xxp1;
 	struct cvmx_ipd_portx_bp_page_cnt_s   cn58xx;
 	struct cvmx_ipd_portx_bp_page_cnt_s   cn58xxp1;
+	struct cvmx_ipd_portx_bp_page_cnt_s   cn61xx;
 	struct cvmx_ipd_portx_bp_page_cnt_s   cn63xx;
 	struct cvmx_ipd_portx_bp_page_cnt_s   cn63xxp1;
+	struct cvmx_ipd_portx_bp_page_cnt_s   cn66xx;
+	struct cvmx_ipd_portx_bp_page_cnt_s   cnf71xx;
 };
 typedef union cvmx_ipd_portx_bp_page_cnt cvmx_ipd_portx_bp_page_cnt_t;
 
@@ -1529,13 +2424,12 @@ typedef union cvmx_ipd_portx_bp_page_cnt cvmx_ipd_portx_bp_page_cnt_t;
  * The number of pages in use by the port that when exceeded, backpressure will be applied to the port.
  * See also IPD_PORTX_BP_PAGE_CNT
  * See also IPD_PORTX_BP_PAGE_CNT3
+ * 0x368-0x380
  */
-union cvmx_ipd_portx_bp_page_cnt2
-{
+union cvmx_ipd_portx_bp_page_cnt2 {
 	uint64_t u64;
-	struct cvmx_ipd_portx_bp_page_cnt2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_portx_bp_page_cnt2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t bp_enb                       : 1;  /**< When set '1' BP will be applied, if '0' BP will
                                                          not be applied to port. */
@@ -1554,8 +2448,11 @@ union cvmx_ipd_portx_bp_page_cnt2
 	struct cvmx_ipd_portx_bp_page_cnt2_s  cn52xxp1;
 	struct cvmx_ipd_portx_bp_page_cnt2_s  cn56xx;
 	struct cvmx_ipd_portx_bp_page_cnt2_s  cn56xxp1;
+	struct cvmx_ipd_portx_bp_page_cnt2_s  cn61xx;
 	struct cvmx_ipd_portx_bp_page_cnt2_s  cn63xx;
 	struct cvmx_ipd_portx_bp_page_cnt2_s  cn63xxp1;
+	struct cvmx_ipd_portx_bp_page_cnt2_s  cn66xx;
+	struct cvmx_ipd_portx_bp_page_cnt2_s  cnf71xx;
 };
 typedef union cvmx_ipd_portx_bp_page_cnt2 cvmx_ipd_portx_bp_page_cnt2_t;
 
@@ -1567,13 +2464,12 @@ typedef union cvmx_ipd_portx_bp_page_cnt2 cvmx_ipd_portx_bp_page_cnt2_t;
  * The number of pages in use by the port that when exceeded, backpressure will be applied to the port.
  * See also IPD_PORTX_BP_PAGE_CNT
  * See also IPD_PORTX_BP_PAGE_CNT2
+ * 0x3d0-408
  */
-union cvmx_ipd_portx_bp_page_cnt3
-{
+union cvmx_ipd_portx_bp_page_cnt3 {
 	uint64_t u64;
-	struct cvmx_ipd_portx_bp_page_cnt3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_portx_bp_page_cnt3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t bp_enb                       : 1;  /**< When set '1' BP will be applied, if '0' BP will
                                                          not be applied to port. */
@@ -1588,8 +2484,11 @@ union cvmx_ipd_portx_bp_page_cnt3
 	uint64_t reserved_18_63               : 46;
 #endif
 	} s;
+	struct cvmx_ipd_portx_bp_page_cnt3_s  cn61xx;
 	struct cvmx_ipd_portx_bp_page_cnt3_s  cn63xx;
 	struct cvmx_ipd_portx_bp_page_cnt3_s  cn63xxp1;
+	struct cvmx_ipd_portx_bp_page_cnt3_s  cn66xx;
+	struct cvmx_ipd_portx_bp_page_cnt3_s  cnf71xx;
 };
 typedef union cvmx_ipd_portx_bp_page_cnt3 cvmx_ipd_portx_bp_page_cnt3_t;
 
@@ -1599,13 +2498,12 @@ typedef union cvmx_ipd_portx_bp_page_cnt3 cvmx_ipd_portx_bp_page_cnt3_t;
  * IPD_PORT_BP_COUNTERS2_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port.
  * See also IPD_PORT_BP_COUNTERS_PAIRX
  * See also IPD_PORT_BP_COUNTERS3_PAIRX
+ * 0x388-0x3a0
  */
-union cvmx_ipd_port_bp_counters2_pairx
-{
+union cvmx_ipd_port_bp_counters2_pairx {
 	uint64_t u64;
-	struct cvmx_ipd_port_bp_counters2_pairx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_port_bp_counters2_pairx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_25_63               : 39;
 	uint64_t cnt_val                      : 25; /**< Number of MBUFs being used by data on this port. */
 #else
@@ -1617,8 +2515,11 @@ union cvmx_ipd_port_bp_counters2_pairx
 	struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1;
 	struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx;
 	struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1;
+	struct cvmx_ipd_port_bp_counters2_pairx_s cn61xx;
 	struct cvmx_ipd_port_bp_counters2_pairx_s cn63xx;
 	struct cvmx_ipd_port_bp_counters2_pairx_s cn63xxp1;
+	struct cvmx_ipd_port_bp_counters2_pairx_s cn66xx;
+	struct cvmx_ipd_port_bp_counters2_pairx_s cnf71xx;
 };
 typedef union cvmx_ipd_port_bp_counters2_pairx cvmx_ipd_port_bp_counters2_pairx_t;
 
@@ -1628,13 +2529,12 @@ typedef union cvmx_ipd_port_bp_counters2_pairx cvmx_ipd_port_bp_counters2_pairx_
  * IPD_PORT_BP_COUNTERS3_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port.
  * See also IPD_PORT_BP_COUNTERS_PAIRX
  * See also IPD_PORT_BP_COUNTERS2_PAIRX
+ *  0x3b0-0x3c8
  */
-union cvmx_ipd_port_bp_counters3_pairx
-{
+union cvmx_ipd_port_bp_counters3_pairx {
 	uint64_t u64;
-	struct cvmx_ipd_port_bp_counters3_pairx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_port_bp_counters3_pairx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_25_63               : 39;
 	uint64_t cnt_val                      : 25; /**< Number of MBUFs being used by data on this port. */
 #else
@@ -1642,24 +2542,51 @@ union cvmx_ipd_port_bp_counters3_pairx
 	uint64_t reserved_25_63               : 39;
 #endif
 	} s;
+	struct cvmx_ipd_port_bp_counters3_pairx_s cn61xx;
 	struct cvmx_ipd_port_bp_counters3_pairx_s cn63xx;
 	struct cvmx_ipd_port_bp_counters3_pairx_s cn63xxp1;
+	struct cvmx_ipd_port_bp_counters3_pairx_s cn66xx;
+	struct cvmx_ipd_port_bp_counters3_pairx_s cnf71xx;
 };
 typedef union cvmx_ipd_port_bp_counters3_pairx cvmx_ipd_port_bp_counters3_pairx_t;
 
 /**
+ * cvmx_ipd_port_bp_counters4_pair#
+ *
+ * IPD_PORT_BP_COUNTERS4_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port.
+ * See also IPD_PORT_BP_COUNTERS_PAIRX
+ * See also IPD_PORT_BP_COUNTERS2_PAIRX
+ *  0x410-0x3c8
+ */
+union cvmx_ipd_port_bp_counters4_pairx {
+	uint64_t u64;
+	struct cvmx_ipd_port_bp_counters4_pairx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_25_63               : 39;
+	uint64_t cnt_val                      : 25; /**< Number of MBUFs being used by data on this port. */
+#else
+	uint64_t cnt_val                      : 25;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_ipd_port_bp_counters4_pairx_s cn61xx;
+	struct cvmx_ipd_port_bp_counters4_pairx_s cn66xx;
+	struct cvmx_ipd_port_bp_counters4_pairx_s cnf71xx;
+};
+typedef union cvmx_ipd_port_bp_counters4_pairx cvmx_ipd_port_bp_counters4_pairx_t;
+
+/**
  * cvmx_ipd_port_bp_counters_pair#
  *
  * IPD_PORT_BP_COUNTERS_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port.
  * See also IPD_PORT_BP_COUNTERS2_PAIRX
  * See also IPD_PORT_BP_COUNTERS3_PAIRX
+ * 0x1b8-0x2d0
  */
-union cvmx_ipd_port_bp_counters_pairx
-{
+union cvmx_ipd_port_bp_counters_pairx {
 	uint64_t u64;
-	struct cvmx_ipd_port_bp_counters_pairx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_port_bp_counters_pairx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_25_63               : 39;
 	uint64_t cnt_val                      : 25; /**< Number of MBUFs being used by data on this port. */
 #else
@@ -1678,12 +2605,53 @@ union cvmx_ipd_port_bp_counters_pairx
 	struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1;
 	struct cvmx_ipd_port_bp_counters_pairx_s cn58xx;
 	struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1;
+	struct cvmx_ipd_port_bp_counters_pairx_s cn61xx;
 	struct cvmx_ipd_port_bp_counters_pairx_s cn63xx;
 	struct cvmx_ipd_port_bp_counters_pairx_s cn63xxp1;
+	struct cvmx_ipd_port_bp_counters_pairx_s cn66xx;
+	struct cvmx_ipd_port_bp_counters_pairx_s cnf71xx;
 };
 typedef union cvmx_ipd_port_bp_counters_pairx cvmx_ipd_port_bp_counters_pairx_t;
 
 /**
+ * cvmx_ipd_port_ptr_fifo_ctl
+ *
+ * IPD_PORT_PTR_FIFO_CTL = IPD's Reasm-Id Pointer FIFO Control
+ *
+ * Allows reading of the Page-Pointers stored in the IPD's Reasm-Id Fifo.
+ */
+union cvmx_ipd_port_ptr_fifo_ctl {
+	uint64_t u64;
+	struct cvmx_ipd_port_ptr_fifo_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_48_63               : 16;
+	uint64_t ptr                          : 33; /**< The output of the reasm-id-ptr-fifo. */
+	uint64_t max_pkt                      : 7;  /**< Maximum number of Packet-Pointers that are in
+                                                         in the FIFO. */
+	uint64_t cena                         : 1;  /**< Active low Chip Enable to the read the
+                                                         pwp_fifo. This bit also controls the MUX-select
+                                                         that steers [RADDR] to the pwp_fifo.
+                                                         *WARNING - Setting this field to '0' will allow
+                                                         reading of the memories thorugh the PTR field,
+                                                         but will cause unpredictable operation of the IPD
+                                                         under normal operation. */
+	uint64_t raddr                        : 7;  /**< Sets the address to read from in the reasm-id
+                                                         fifo in the IPD. This FIFO holds Packet-Pointers
+                                                         to be used for packet data storage. */
+#else
+	uint64_t raddr                        : 7;
+	uint64_t cena                         : 1;
+	uint64_t max_pkt                      : 7;
+	uint64_t ptr                          : 33;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_ipd_port_ptr_fifo_ctl_s   cn68xx;
+	struct cvmx_ipd_port_ptr_fifo_ctl_s   cn68xxp1;
+};
+typedef union cvmx_ipd_port_ptr_fifo_ctl cvmx_ipd_port_ptr_fifo_ctl_t;
+
+/**
  * cvmx_ipd_port_qos_#_cnt
  *
  * IPD_PORT_QOS_X_CNT = IPD PortX QOS-0 Count
@@ -1692,12 +2660,10 @@ typedef union cvmx_ipd_port_bp_counters_pairx cvmx_ipd_port_bp_counters_pairx_t;
  * QOS 0-7 respectively followed by port 1 at (8-15), etc
  * Ports 0-3, 32-43
  */
-union cvmx_ipd_port_qos_x_cnt
-{
+union cvmx_ipd_port_qos_x_cnt {
 	uint64_t u64;
-	struct cvmx_ipd_port_qos_x_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_port_qos_x_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t wmark                        : 32; /**< When the field CNT after being modified is equal to
                                                          or crosses this value (i.e. value was greater than
                                                          then becomes less then, or value was less than and
@@ -1714,8 +2680,13 @@ union cvmx_ipd_port_qos_x_cnt
 	struct cvmx_ipd_port_qos_x_cnt_s      cn52xxp1;
 	struct cvmx_ipd_port_qos_x_cnt_s      cn56xx;
 	struct cvmx_ipd_port_qos_x_cnt_s      cn56xxp1;
+	struct cvmx_ipd_port_qos_x_cnt_s      cn61xx;
 	struct cvmx_ipd_port_qos_x_cnt_s      cn63xx;
 	struct cvmx_ipd_port_qos_x_cnt_s      cn63xxp1;
+	struct cvmx_ipd_port_qos_x_cnt_s      cn66xx;
+	struct cvmx_ipd_port_qos_x_cnt_s      cn68xx;
+	struct cvmx_ipd_port_qos_x_cnt_s      cn68xxp1;
+	struct cvmx_ipd_port_qos_x_cnt_s      cnf71xx;
 };
 typedef union cvmx_ipd_port_qos_x_cnt cvmx_ipd_port_qos_x_cnt_t;
 
@@ -1728,16 +2699,14 @@ typedef union cvmx_ipd_port_qos_x_cnt cvmx_ipd_port_qos_x_cnt_t;
  *
  * 0=P0-7; 1=P8-15; 2=P16-23; 3=P24-31; 4=P32-39; 5=P40-47; 6=P48-55; 7=P56-63
  *
- * Only ports used are: P0-3, P32-39, and P40-43. Therefore only IPD_PORT_QOS_INT0, IPD_PORT_QOS_INT4,
- * and IPD_PORT_QOS_INT5 exist and, furthermore:  <63:32> of IPD_PORT_QOS_INT0 and IPD_PORT_QOS_INT5,
+ * Only ports used are: P0-3, P32-39, and P40-47. Therefore only IPD_PORT_QOS_INT0, IPD_PORT_QOS_INT4,
+ * and IPD_PORT_QOS_INT5 exist and, furthermore:  <63:32> of IPD_PORT_QOS_INT0,
  * are reserved.
  */
-union cvmx_ipd_port_qos_intx
-{
+union cvmx_ipd_port_qos_intx {
 	uint64_t u64;
-	struct cvmx_ipd_port_qos_intx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_port_qos_intx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t intr                         : 64; /**< Interrupt bits. */
 #else
 	uint64_t intr                         : 64;
@@ -1747,8 +2716,13 @@ union cvmx_ipd_port_qos_intx
 	struct cvmx_ipd_port_qos_intx_s       cn52xxp1;
 	struct cvmx_ipd_port_qos_intx_s       cn56xx;
 	struct cvmx_ipd_port_qos_intx_s       cn56xxp1;
+	struct cvmx_ipd_port_qos_intx_s       cn61xx;
 	struct cvmx_ipd_port_qos_intx_s       cn63xx;
 	struct cvmx_ipd_port_qos_intx_s       cn63xxp1;
+	struct cvmx_ipd_port_qos_intx_s       cn66xx;
+	struct cvmx_ipd_port_qos_intx_s       cn68xx;
+	struct cvmx_ipd_port_qos_intx_s       cn68xxp1;
+	struct cvmx_ipd_port_qos_intx_s       cnf71xx;
 };
 typedef union cvmx_ipd_port_qos_intx cvmx_ipd_port_qos_intx_t;
 
@@ -1759,12 +2733,10 @@ typedef union cvmx_ipd_port_qos_intx cvmx_ipd_port_qos_intx_t;
  *
  * When the IPD_PORT_QOS_INTX[\#] is '1' and IPD_PORT_QOS_INT_ENBX[\#] is '1' a interrupt will be generated.
  */
-union cvmx_ipd_port_qos_int_enbx
-{
+union cvmx_ipd_port_qos_int_enbx {
 	uint64_t u64;
-	struct cvmx_ipd_port_qos_int_enbx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_port_qos_int_enbx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t enb                          : 64; /**< Enable bits. */
 #else
 	uint64_t enb                          : 64;
@@ -1774,24 +2746,52 @@ union cvmx_ipd_port_qos_int_enbx
 	struct cvmx_ipd_port_qos_int_enbx_s   cn52xxp1;
 	struct cvmx_ipd_port_qos_int_enbx_s   cn56xx;
 	struct cvmx_ipd_port_qos_int_enbx_s   cn56xxp1;
+	struct cvmx_ipd_port_qos_int_enbx_s   cn61xx;
 	struct cvmx_ipd_port_qos_int_enbx_s   cn63xx;
 	struct cvmx_ipd_port_qos_int_enbx_s   cn63xxp1;
+	struct cvmx_ipd_port_qos_int_enbx_s   cn66xx;
+	struct cvmx_ipd_port_qos_int_enbx_s   cn68xx;
+	struct cvmx_ipd_port_qos_int_enbx_s   cn68xxp1;
+	struct cvmx_ipd_port_qos_int_enbx_s   cnf71xx;
 };
 typedef union cvmx_ipd_port_qos_int_enbx cvmx_ipd_port_qos_int_enbx_t;
 
 /**
+ * cvmx_ipd_port_sop#
+ *
+ * IPD_PORT_SOP = IPD Reasm-Id SOP
+ *
+ * Set when a SOP is detected on a reasm-num. Where the reasm-num value set the bit vector of this register.
+ */
+union cvmx_ipd_port_sopx {
+	uint64_t u64;
+	struct cvmx_ipd_port_sopx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t sop                          : 64; /**< When set '1' a SOP was detected on a reasm-num,
+                                                         When clear '0' no SOP was yet received or an EOP
+                                                         was received on the reasm-num.
+                                                         IPD only supports 63 reasm-nums, so bit [63]
+                                                         should never be set. */
+#else
+	uint64_t sop                          : 64;
+#endif
+	} s;
+	struct cvmx_ipd_port_sopx_s           cn68xx;
+	struct cvmx_ipd_port_sopx_s           cn68xxp1;
+};
+typedef union cvmx_ipd_port_sopx cvmx_ipd_port_sopx_t;
+
+/**
  * cvmx_ipd_prc_hold_ptr_fifo_ctl
  *
  * IPD_PRC_HOLD_PTR_FIFO_CTL = IPD's PRC Holding Pointer FIFO Control
  *
  * Allows reading of the Page-Pointers stored in the IPD's PRC Holding Fifo.
  */
-union cvmx_ipd_prc_hold_ptr_fifo_ctl
-{
+union cvmx_ipd_prc_hold_ptr_fifo_ctl {
 	uint64_t u64;
-	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_39_63               : 25;
 	uint64_t max_pkt                      : 3;  /**< Maximum number of Packet-Pointers that COULD be
                                                          in the FIFO. */
@@ -1825,8 +2825,11 @@ union cvmx_ipd_prc_hold_ptr_fifo_ctl
 	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1;
 	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx;
 	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1;
+	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn61xx;
 	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xx;
 	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xxp1;
+	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn66xx;
+	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cnf71xx;
 };
 typedef union cvmx_ipd_prc_hold_ptr_fifo_ctl cvmx_ipd_prc_hold_ptr_fifo_ctl_t;
 
@@ -1837,12 +2840,10 @@ typedef union cvmx_ipd_prc_hold_ptr_fifo_ctl cvmx_ipd_prc_hold_ptr_fifo_ctl_t;
  *
  * Allows reading of the Page-Pointers stored in the IPD's PRC PORT Fifo.
  */
-union cvmx_ipd_prc_port_ptr_fifo_ctl
-{
+union cvmx_ipd_prc_port_ptr_fifo_ctl {
 	uint64_t u64;
-	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_44_63               : 20;
 	uint64_t max_pkt                      : 7;  /**< Maximum number of Packet-Pointers that are in
                                                          in the FIFO. */
@@ -1875,8 +2876,11 @@ union cvmx_ipd_prc_port_ptr_fifo_ctl
 	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1;
 	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx;
 	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1;
+	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn61xx;
 	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xx;
 	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xxp1;
+	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn66xx;
+	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cnf71xx;
 };
 typedef union cvmx_ipd_prc_port_ptr_fifo_ctl cvmx_ipd_prc_port_ptr_fifo_ctl_t;
 
@@ -1887,12 +2891,10 @@ typedef union cvmx_ipd_prc_port_ptr_fifo_ctl cvmx_ipd_prc_port_ptr_fifo_ctl_t;
  *
  * Shows the number of WQE and Packet Page Pointers stored in the IPD.
  */
-union cvmx_ipd_ptr_count
-{
+union cvmx_ipd_ptr_count {
 	uint64_t u64;
-	struct cvmx_ipd_ptr_count_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_ptr_count_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t pktv_cnt                     : 1;  /**< PKT Ptr Valid. */
 	uint64_t wqev_cnt                     : 1;  /**< WQE Ptr Valid. This value is '1' when a WQE
@@ -1932,8 +2934,13 @@ union cvmx_ipd_ptr_count
 	struct cvmx_ipd_ptr_count_s           cn56xxp1;
 	struct cvmx_ipd_ptr_count_s           cn58xx;
 	struct cvmx_ipd_ptr_count_s           cn58xxp1;
+	struct cvmx_ipd_ptr_count_s           cn61xx;
 	struct cvmx_ipd_ptr_count_s           cn63xx;
 	struct cvmx_ipd_ptr_count_s           cn63xxp1;
+	struct cvmx_ipd_ptr_count_s           cn66xx;
+	struct cvmx_ipd_ptr_count_s           cn68xx;
+	struct cvmx_ipd_ptr_count_s           cn68xxp1;
+	struct cvmx_ipd_ptr_count_s           cnf71xx;
 };
 typedef union cvmx_ipd_ptr_count cvmx_ipd_ptr_count_t;
 
@@ -1944,12 +2951,10 @@ typedef union cvmx_ipd_ptr_count cvmx_ipd_ptr_count_t;
  *
  * Allows reading of the Page-Pointers stored in the IPD's PWP Fifo.
  */
-union cvmx_ipd_pwp_ptr_fifo_ctl
-{
+union cvmx_ipd_pwp_ptr_fifo_ctl {
 	uint64_t u64;
-	struct cvmx_ipd_pwp_ptr_fifo_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_pwp_ptr_fifo_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_61_63               : 3;
 	uint64_t max_cnts                     : 7;  /**< Maximum number of Packet-Pointers or WQE-Pointers
                                                          that COULD be in the FIFO.
@@ -1991,8 +2996,11 @@ union cvmx_ipd_pwp_ptr_fifo_ctl
 	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn56xxp1;
 	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn58xx;
 	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn58xxp1;
+	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn61xx;
 	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn63xx;
 	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn63xxp1;
+	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn66xx;
+	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cnf71xx;
 };
 typedef union cvmx_ipd_pwp_ptr_fifo_ctl cvmx_ipd_pwp_ptr_fifo_ctl_t;
 
@@ -2003,12 +3011,10 @@ typedef union cvmx_ipd_pwp_ptr_fifo_ctl cvmx_ipd_pwp_ptr_fifo_ctl_t;
  *
  * Set the pass-drop marks for qos level.
  */
-union cvmx_ipd_qosx_red_marks
-{
+union cvmx_ipd_qosx_red_marks {
 	uint64_t u64;
-	struct cvmx_ipd_qosx_red_marks_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_qosx_red_marks_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t drop                         : 32; /**< Packets will be dropped when the average value of
                                                          IPD_QUE0_FREE_PAGE_CNT is equal to or less than
                                                          this value. */
@@ -2030,8 +3036,13 @@ union cvmx_ipd_qosx_red_marks
 	struct cvmx_ipd_qosx_red_marks_s      cn56xxp1;
 	struct cvmx_ipd_qosx_red_marks_s      cn58xx;
 	struct cvmx_ipd_qosx_red_marks_s      cn58xxp1;
+	struct cvmx_ipd_qosx_red_marks_s      cn61xx;
 	struct cvmx_ipd_qosx_red_marks_s      cn63xx;
 	struct cvmx_ipd_qosx_red_marks_s      cn63xxp1;
+	struct cvmx_ipd_qosx_red_marks_s      cn66xx;
+	struct cvmx_ipd_qosx_red_marks_s      cn68xx;
+	struct cvmx_ipd_qosx_red_marks_s      cn68xxp1;
+	struct cvmx_ipd_qosx_red_marks_s      cnf71xx;
 };
 typedef union cvmx_ipd_qosx_red_marks cvmx_ipd_qosx_red_marks_t;
 
@@ -2042,12 +3053,10 @@ typedef union cvmx_ipd_qosx_red_marks cvmx_ipd_qosx_red_marks_t;
  *
  * Number of Free-Page Pointer that are available for use in the FPA for Queue-0.
  */
-union cvmx_ipd_que0_free_page_cnt
-{
+union cvmx_ipd_que0_free_page_cnt {
 	uint64_t u64;
-	struct cvmx_ipd_que0_free_page_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_que0_free_page_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t q0_pcnt                      : 32; /**< Number of Queue-0 Page Pointers Available. */
 #else
@@ -2066,24 +3075,85 @@ union cvmx_ipd_que0_free_page_cnt
 	struct cvmx_ipd_que0_free_page_cnt_s  cn56xxp1;
 	struct cvmx_ipd_que0_free_page_cnt_s  cn58xx;
 	struct cvmx_ipd_que0_free_page_cnt_s  cn58xxp1;
+	struct cvmx_ipd_que0_free_page_cnt_s  cn61xx;
 	struct cvmx_ipd_que0_free_page_cnt_s  cn63xx;
 	struct cvmx_ipd_que0_free_page_cnt_s  cn63xxp1;
+	struct cvmx_ipd_que0_free_page_cnt_s  cn66xx;
+	struct cvmx_ipd_que0_free_page_cnt_s  cn68xx;
+	struct cvmx_ipd_que0_free_page_cnt_s  cn68xxp1;
+	struct cvmx_ipd_que0_free_page_cnt_s  cnf71xx;
 };
 typedef union cvmx_ipd_que0_free_page_cnt cvmx_ipd_que0_free_page_cnt_t;
 
 /**
+ * cvmx_ipd_red_bpid_enable#
+ *
+ * IPD_RED_BPID_ENABLE = IPD RED BPID Enable
+ *
+ * Set the pass-drop marks for qos level.
+ */
+union cvmx_ipd_red_bpid_enablex {
+	uint64_t u64;
+	struct cvmx_ipd_red_bpid_enablex_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t prt_enb                      : 64; /**< The bit position will enable the corresponding
+                                                         BPIDs ability to have packets dropped by RED
+                                                         probability. */
+#else
+	uint64_t prt_enb                      : 64;
+#endif
+	} s;
+	struct cvmx_ipd_red_bpid_enablex_s    cn68xx;
+	struct cvmx_ipd_red_bpid_enablex_s    cn68xxp1;
+};
+typedef union cvmx_ipd_red_bpid_enablex cvmx_ipd_red_bpid_enablex_t;
+
+/**
+ * cvmx_ipd_red_delay
+ *
+ * IPD_RED_DELAY = IPD RED BPID Enable
+ *
+ * Set the pass-drop marks for qos level.
+ */
+union cvmx_ipd_red_delay {
+	uint64_t u64;
+	struct cvmx_ipd_red_delay_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_28_63               : 36;
+	uint64_t prb_dly                      : 14; /**< Number (core clocks periods + 68) * 8 to wait
+                                                         before calculating the new packet drop
+                                                         probability for each QOS level. */
+	uint64_t avg_dly                      : 14; /**< Number (core clocks periods + 10) * 8 to wait
+                                                         before calculating the moving average for each
+                                                         QOS level.
+                                                         Larger AVG_DLY values cause the moving averages
+                                                         of ALL QOS levels to track changes in the actual
+                                                         free space more slowly. Smaller NEW_CON (and
+                                                         larger AVG_CON) values can have a similar effect,
+                                                         but only affect an individual QOS level, rather
+                                                         than all. */
+#else
+	uint64_t avg_dly                      : 14;
+	uint64_t prb_dly                      : 14;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} s;
+	struct cvmx_ipd_red_delay_s           cn68xx;
+	struct cvmx_ipd_red_delay_s           cn68xxp1;
+};
+typedef union cvmx_ipd_red_delay cvmx_ipd_red_delay_t;
+
+/**
  * cvmx_ipd_red_port_enable
  *
  * IPD_RED_PORT_ENABLE = IPD RED Port Enable
  *
  * Set the pass-drop marks for qos level.
  */
-union cvmx_ipd_red_port_enable
-{
+union cvmx_ipd_red_port_enable {
 	uint64_t u64;
-	struct cvmx_ipd_red_port_enable_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_red_port_enable_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t prb_dly                      : 14; /**< Number (core clocks periods + 68) * 8 to wait
                                                          before calculating the new packet drop
                                                          probability for each QOS level. */
@@ -2116,8 +3186,11 @@ union cvmx_ipd_red_port_enable
 	struct cvmx_ipd_red_port_enable_s     cn56xxp1;
 	struct cvmx_ipd_red_port_enable_s     cn58xx;
 	struct cvmx_ipd_red_port_enable_s     cn58xxp1;
+	struct cvmx_ipd_red_port_enable_s     cn61xx;
 	struct cvmx_ipd_red_port_enable_s     cn63xx;
 	struct cvmx_ipd_red_port_enable_s     cn63xxp1;
+	struct cvmx_ipd_red_port_enable_s     cn66xx;
+	struct cvmx_ipd_red_port_enable_s     cnf71xx;
 };
 typedef union cvmx_ipd_red_port_enable cvmx_ipd_red_port_enable_t;
 
@@ -2128,24 +3201,21 @@ typedef union cvmx_ipd_red_port_enable cvmx_ipd_red_port_enable_t;
  *
  * Set the pass-drop marks for qos level.
  */
-union cvmx_ipd_red_port_enable2
-{
+union cvmx_ipd_red_port_enable2 {
 	uint64_t u64;
-	struct cvmx_ipd_red_port_enable2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_8_63                : 56;
-	uint64_t prt_enb                      : 8;  /**< Bits 7-0 corresponds to ports 43-36. These bits
+	struct cvmx_ipd_red_port_enable2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_12_63               : 52;
+	uint64_t prt_enb                      : 12; /**< Bits 11-0 corresponds to ports 47-36. These bits
                                                          have the same meaning as the PRT_ENB field of
                                                          IPD_RED_PORT_ENABLE. */
 #else
-	uint64_t prt_enb                      : 8;
-	uint64_t reserved_8_63                : 56;
+	uint64_t prt_enb                      : 12;
+	uint64_t reserved_12_63               : 52;
 #endif
 	} s;
-	struct cvmx_ipd_red_port_enable2_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_red_port_enable2_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t prt_enb                      : 4;  /**< Bits 3-0 cooresponds to ports 39-36. These bits
                                                          have the same meaning as the PRT_ENB field of
@@ -2158,8 +3228,21 @@ union cvmx_ipd_red_port_enable2
 	struct cvmx_ipd_red_port_enable2_cn52xx cn52xxp1;
 	struct cvmx_ipd_red_port_enable2_cn52xx cn56xx;
 	struct cvmx_ipd_red_port_enable2_cn52xx cn56xxp1;
-	struct cvmx_ipd_red_port_enable2_s    cn63xx;
-	struct cvmx_ipd_red_port_enable2_s    cn63xxp1;
+	struct cvmx_ipd_red_port_enable2_s    cn61xx;
+	struct cvmx_ipd_red_port_enable2_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_8_63                : 56;
+	uint64_t prt_enb                      : 8;  /**< Bits 7-0 corresponds to ports 43-36. These bits
+                                                         have the same meaning as the PRT_ENB field of
+                                                         IPD_RED_PORT_ENABLE. */
+#else
+	uint64_t prt_enb                      : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} cn63xx;
+	struct cvmx_ipd_red_port_enable2_cn63xx cn63xxp1;
+	struct cvmx_ipd_red_port_enable2_s    cn66xx;
+	struct cvmx_ipd_red_port_enable2_s    cnf71xx;
 };
 typedef union cvmx_ipd_red_port_enable2 cvmx_ipd_red_port_enable2_t;
 
@@ -2170,12 +3253,10 @@ typedef union cvmx_ipd_red_port_enable2 cvmx_ipd_red_port_enable2_t;
  *
  * Value control the Passing and Dropping of packets by the red engine for QOS Level-0.
  */
-union cvmx_ipd_red_quex_param
-{
+union cvmx_ipd_red_quex_param {
 	uint64_t u64;
-	struct cvmx_ipd_red_quex_param_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_red_quex_param_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_49_63               : 15;
 	uint64_t use_pcnt                     : 1;  /**< When set '1' red will use the actual Packet-Page
                                                          Count in place of the Average for RED calculations. */
@@ -2229,12 +3310,52 @@ union cvmx_ipd_red_quex_param
 	struct cvmx_ipd_red_quex_param_s      cn56xxp1;
 	struct cvmx_ipd_red_quex_param_s      cn58xx;
 	struct cvmx_ipd_red_quex_param_s      cn58xxp1;
+	struct cvmx_ipd_red_quex_param_s      cn61xx;
 	struct cvmx_ipd_red_quex_param_s      cn63xx;
 	struct cvmx_ipd_red_quex_param_s      cn63xxp1;
+	struct cvmx_ipd_red_quex_param_s      cn66xx;
+	struct cvmx_ipd_red_quex_param_s      cn68xx;
+	struct cvmx_ipd_red_quex_param_s      cn68xxp1;
+	struct cvmx_ipd_red_quex_param_s      cnf71xx;
 };
 typedef union cvmx_ipd_red_quex_param cvmx_ipd_red_quex_param_t;
 
 /**
+ * cvmx_ipd_req_wgt
+ *
+ * IPD_REQ_WGT = IPD REQ weights
+ *
+ * There are 8 devices that can request to send packet traffic to the IPD. These weights are used for the Weighted Round Robin
+ * grant generated by the IPD to requestors.
+ */
+union cvmx_ipd_req_wgt {
+	uint64_t u64;
+	struct cvmx_ipd_req_wgt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t wgt7                         : 8;  /**< Weight for ILK  REQ */
+	uint64_t wgt6                         : 8;  /**< Weight for PKO  REQ */
+	uint64_t wgt5                         : 8;  /**< Weight for DPI  REQ */
+	uint64_t wgt4                         : 8;  /**< Weight for AGX4 REQ */
+	uint64_t wgt3                         : 8;  /**< Weight for AGX3 REQ */
+	uint64_t wgt2                         : 8;  /**< Weight for AGX2 REQ */
+	uint64_t wgt1                         : 8;  /**< Weight for AGX1 REQ */
+	uint64_t wgt0                         : 8;  /**< Weight for AGX0 REQ */
+#else
+	uint64_t wgt0                         : 8;
+	uint64_t wgt1                         : 8;
+	uint64_t wgt2                         : 8;
+	uint64_t wgt3                         : 8;
+	uint64_t wgt4                         : 8;
+	uint64_t wgt5                         : 8;
+	uint64_t wgt6                         : 8;
+	uint64_t wgt7                         : 8;
+#endif
+	} s;
+	struct cvmx_ipd_req_wgt_s             cn68xx;
+};
+typedef union cvmx_ipd_req_wgt cvmx_ipd_req_wgt_t;
+
+/**
  * cvmx_ipd_sub_port_bp_page_cnt
  *
  * IPD_SUB_PORT_BP_PAGE_CNT = IPD Subtract Port Backpressure Page Count
@@ -2247,12 +3368,10 @@ typedef union cvmx_ipd_red_quex_param cvmx_ipd_red_quex_param_t;
  *
  * This register can't be written from the PCI via a window write.
  */
-union cvmx_ipd_sub_port_bp_page_cnt
-{
+union cvmx_ipd_sub_port_bp_page_cnt {
 	uint64_t u64;
-	struct cvmx_ipd_sub_port_bp_page_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_sub_port_bp_page_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t port                         : 6;  /**< The port to add the PAGE_CNT field to. */
 	uint64_t page_cnt                     : 25; /**< The number of page pointers to add to
@@ -2275,8 +3394,13 @@ union cvmx_ipd_sub_port_bp_page_cnt
 	struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1;
 	struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx;
 	struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s cn61xx;
 	struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xx;
 	struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xxp1;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s cn66xx;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s cn68xx;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s cn68xxp1;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s cnf71xx;
 };
 typedef union cvmx_ipd_sub_port_bp_page_cnt cvmx_ipd_sub_port_bp_page_cnt_t;
 
@@ -2288,12 +3412,10 @@ typedef union cvmx_ipd_sub_port_bp_page_cnt cvmx_ipd_sub_port_bp_page_cnt_t;
  * When set '1' the port corresponding to the bit set will subtract 4 bytes from the end of
  * the packet.
  */
-union cvmx_ipd_sub_port_fcs
-{
+union cvmx_ipd_sub_port_fcs {
 	uint64_t u64;
-	struct cvmx_ipd_sub_port_fcs_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_sub_port_fcs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t port_bit2                    : 4;  /**< When set '1', the port corresponding to the bit
                                                          position set, will subtract the FCS for packets
@@ -2309,9 +3431,8 @@ union cvmx_ipd_sub_port_fcs
 	uint64_t reserved_40_63               : 24;
 #endif
 	} s;
-	struct cvmx_ipd_sub_port_fcs_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_sub_port_fcs_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t port_bit                     : 3;  /**< When set '1', the port corresponding to the bit
                                                          position set, will subtract the FCS for packets
@@ -2322,9 +3443,8 @@ union cvmx_ipd_sub_port_fcs
 #endif
 	} cn30xx;
 	struct cvmx_ipd_sub_port_fcs_cn30xx   cn31xx;
-	struct cvmx_ipd_sub_port_fcs_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_sub_port_fcs_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t port_bit                     : 32; /**< When set '1', the port corresponding to the bit
                                                          position set, will subtract the FCS for packets
@@ -2342,8 +3462,11 @@ union cvmx_ipd_sub_port_fcs
 	struct cvmx_ipd_sub_port_fcs_s        cn56xxp1;
 	struct cvmx_ipd_sub_port_fcs_cn38xx   cn58xx;
 	struct cvmx_ipd_sub_port_fcs_cn38xx   cn58xxp1;
+	struct cvmx_ipd_sub_port_fcs_s        cn61xx;
 	struct cvmx_ipd_sub_port_fcs_s        cn63xx;
 	struct cvmx_ipd_sub_port_fcs_s        cn63xxp1;
+	struct cvmx_ipd_sub_port_fcs_s        cn66xx;
+	struct cvmx_ipd_sub_port_fcs_s        cnf71xx;
 };
 typedef union cvmx_ipd_sub_port_fcs cvmx_ipd_sub_port_fcs_t;
 
@@ -2355,12 +3478,10 @@ typedef union cvmx_ipd_sub_port_fcs cvmx_ipd_sub_port_fcs_t;
  * Will add the value (CNT) to the indicated Port-QOS register (PORT_QOS). The value added must be
  * be the 2's complement of the value that needs to be subtracted.
  */
-union cvmx_ipd_sub_port_qos_cnt
-{
+union cvmx_ipd_sub_port_qos_cnt {
 	uint64_t u64;
-	struct cvmx_ipd_sub_port_qos_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_sub_port_qos_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_41_63               : 23;
 	uint64_t port_qos                     : 9;  /**< The port to add the CNT field to. */
 	uint64_t cnt                          : 32; /**< The value to be added to the register selected
@@ -2375,8 +3496,13 @@ union cvmx_ipd_sub_port_qos_cnt
 	struct cvmx_ipd_sub_port_qos_cnt_s    cn52xxp1;
 	struct cvmx_ipd_sub_port_qos_cnt_s    cn56xx;
 	struct cvmx_ipd_sub_port_qos_cnt_s    cn56xxp1;
+	struct cvmx_ipd_sub_port_qos_cnt_s    cn61xx;
 	struct cvmx_ipd_sub_port_qos_cnt_s    cn63xx;
 	struct cvmx_ipd_sub_port_qos_cnt_s    cn63xxp1;
+	struct cvmx_ipd_sub_port_qos_cnt_s    cn66xx;
+	struct cvmx_ipd_sub_port_qos_cnt_s    cn68xx;
+	struct cvmx_ipd_sub_port_qos_cnt_s    cn68xxp1;
+	struct cvmx_ipd_sub_port_qos_cnt_s    cnf71xx;
 };
 typedef union cvmx_ipd_sub_port_qos_cnt cvmx_ipd_sub_port_qos_cnt_t;
 
@@ -2387,12 +3513,10 @@ typedef union cvmx_ipd_sub_port_qos_cnt cvmx_ipd_sub_port_qos_cnt_t;
  *
  * Which FPA Queue (0-7) to fetch page-pointers from for WQE's
  */
-union cvmx_ipd_wqe_fpa_queue
-{
+union cvmx_ipd_wqe_fpa_queue {
 	uint64_t u64;
-	struct cvmx_ipd_wqe_fpa_queue_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_wqe_fpa_queue_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t wqe_pool                     : 3;  /**< Which FPA Queue to fetch page-pointers
                                                          from for WQE's.
@@ -2413,8 +3537,13 @@ union cvmx_ipd_wqe_fpa_queue
 	struct cvmx_ipd_wqe_fpa_queue_s       cn56xxp1;
 	struct cvmx_ipd_wqe_fpa_queue_s       cn58xx;
 	struct cvmx_ipd_wqe_fpa_queue_s       cn58xxp1;
+	struct cvmx_ipd_wqe_fpa_queue_s       cn61xx;
 	struct cvmx_ipd_wqe_fpa_queue_s       cn63xx;
 	struct cvmx_ipd_wqe_fpa_queue_s       cn63xxp1;
+	struct cvmx_ipd_wqe_fpa_queue_s       cn66xx;
+	struct cvmx_ipd_wqe_fpa_queue_s       cn68xx;
+	struct cvmx_ipd_wqe_fpa_queue_s       cn68xxp1;
+	struct cvmx_ipd_wqe_fpa_queue_s       cnf71xx;
 };
 typedef union cvmx_ipd_wqe_fpa_queue cvmx_ipd_wqe_fpa_queue_t;
 
@@ -2425,12 +3554,10 @@ typedef union cvmx_ipd_wqe_fpa_queue cvmx_ipd_wqe_fpa_queue_t;
  *
  * The value of the WQE-pointer fetched and in the valid register.
  */
-union cvmx_ipd_wqe_ptr_valid
-{
+union cvmx_ipd_wqe_ptr_valid {
 	uint64_t u64;
-	struct cvmx_ipd_wqe_ptr_valid_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ipd_wqe_ptr_valid_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t ptr                          : 29; /**< Pointer value.
                                                          When IPD_CTL_STATUS[NO_WPTR] is set '1' this field
@@ -2450,8 +3577,11 @@ union cvmx_ipd_wqe_ptr_valid
 	struct cvmx_ipd_wqe_ptr_valid_s       cn56xxp1;
 	struct cvmx_ipd_wqe_ptr_valid_s       cn58xx;
 	struct cvmx_ipd_wqe_ptr_valid_s       cn58xxp1;
+	struct cvmx_ipd_wqe_ptr_valid_s       cn61xx;
 	struct cvmx_ipd_wqe_ptr_valid_s       cn63xx;
 	struct cvmx_ipd_wqe_ptr_valid_s       cn63xxp1;
+	struct cvmx_ipd_wqe_ptr_valid_s       cn66xx;
+	struct cvmx_ipd_wqe_ptr_valid_s       cnf71xx;
 };
 typedef union cvmx_ipd_wqe_ptr_valid cvmx_ipd_wqe_ptr_valid_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-ipd.c b/sys/contrib/octeon-sdk/cvmx-ipd.c
new file mode 100644
index 0000000..64840c4
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-ipd.c
@@ -0,0 +1,318 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * IPD Support.
+ *
+ * <hr>$Revision: 58943 $<hr>
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-bootmem.h>
+#include <asm/octeon/cvmx-pip-defs.h>
+#include <asm/octeon/cvmx-dbg-defs.h>
+#include <asm/octeon/cvmx-sso-defs.h>
+
+#include <asm/octeon/cvmx-fpa.h>
+#include <asm/octeon/cvmx-wqe.h>
+#include <asm/octeon/cvmx-ipd.h>
+#include <asm/octeon/cvmx-clock.h>
+#include <asm/octeon/cvmx-helper-errata.h>
+#include <asm/octeon/cvmx-helper-cfg.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "executive-config.h"
+#endif
+#include "cvmx.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-bootmem.h"
+#include "cvmx-version.h"
+#include "cvmx-helper-check-defines.h"
+#include "cvmx-error.h"
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "cvmx-config.h"
+#endif
+
+#include "cvmx-fpa.h"
+#include "cvmx-wqe.h"
+#include "cvmx-ipd.h"
+#include "cvmx-helper-errata.h"
+#include "cvmx-helper-cfg.h"
+#endif
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+static void __cvmx_ipd_free_ptr_v1(void)
+{
+    /* Only CN38XXp{1,2} cannot read pointer out of the IPD */
+    if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
+	int no_wptr = 0;
+	cvmx_ipd_ptr_count_t ipd_ptr_count;
+	ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
+
+	/* Handle Work Queue Entry in cn56xx and cn52xx */
+	if (octeon_has_feature(OCTEON_FEATURE_NO_WPTR)) {
+	    cvmx_ipd_ctl_status_t ipd_ctl_status;
+	    ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+	    if (ipd_ctl_status.s.no_wptr)
+		no_wptr = 1;
+	}
+
+	/* Free the prefetched WQE */
+	if (ipd_ptr_count.s.wqev_cnt) {
+	    cvmx_ipd_wqe_ptr_valid_t ipd_wqe_ptr_valid;
+	    ipd_wqe_ptr_valid.u64 = cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID);
+	    if (no_wptr)
+	        cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_wqe_ptr_valid.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+	    else
+	        cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_wqe_ptr_valid.s.ptr<<7), CVMX_FPA_WQE_POOL, 0);
+	}
+
+	/* Free all WQE in the fifo */
+	if (ipd_ptr_count.s.wqe_pcnt) {
+	    int i;
+	    cvmx_ipd_pwp_ptr_fifo_ctl_t ipd_pwp_ptr_fifo_ctl;
+	    ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
+	    for (i = 0; i < ipd_ptr_count.s.wqe_pcnt; i++) {
+		ipd_pwp_ptr_fifo_ctl.s.cena = 0;
+		ipd_pwp_ptr_fifo_ctl.s.raddr = ipd_pwp_ptr_fifo_ctl.s.max_cnts + (ipd_pwp_ptr_fifo_ctl.s.wraddr+i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
+		cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
+		ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
+		if (no_wptr)
+		    cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_pwp_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+		else
+		    cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_pwp_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_WQE_POOL, 0);
+	    }
+	    ipd_pwp_ptr_fifo_ctl.s.cena = 1;
+	    cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
+	}
+
+	/* Free the prefetched packet */
+	if (ipd_ptr_count.s.pktv_cnt) {
+	    cvmx_ipd_pkt_ptr_valid_t ipd_pkt_ptr_valid;
+	    ipd_pkt_ptr_valid.u64 = cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID);
+	    cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_pkt_ptr_valid.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+	}
+
+	/* Free the per port prefetched packets */
+	if (1) {
+	    int i;
+	    cvmx_ipd_prc_port_ptr_fifo_ctl_t ipd_prc_port_ptr_fifo_ctl;
+	    ipd_prc_port_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
+
+	    for (i = 0; i < ipd_prc_port_ptr_fifo_ctl.s.max_pkt; i++) {
+		ipd_prc_port_ptr_fifo_ctl.s.cena = 0;
+		ipd_prc_port_ptr_fifo_ctl.s.raddr = i % ipd_prc_port_ptr_fifo_ctl.s.max_pkt;
+		cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, ipd_prc_port_ptr_fifo_ctl.u64);
+		ipd_prc_port_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
+		cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_prc_port_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+	    }
+	    ipd_prc_port_ptr_fifo_ctl.s.cena = 1;
+	    cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, ipd_prc_port_ptr_fifo_ctl.u64);
+	}
+
+	/* Free all packets in the holding fifo */
+	if (ipd_ptr_count.s.pfif_cnt) {
+	    int i;
+	    cvmx_ipd_prc_hold_ptr_fifo_ctl_t ipd_prc_hold_ptr_fifo_ctl;
+
+	    ipd_prc_hold_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
+
+	    for (i = 0; i < ipd_ptr_count.s.pfif_cnt; i++) {
+		ipd_prc_hold_ptr_fifo_ctl.s.cena = 0;
+		ipd_prc_hold_ptr_fifo_ctl.s.raddr = (ipd_prc_hold_ptr_fifo_ctl.s.praddr + i) % ipd_prc_hold_ptr_fifo_ctl.s.max_pkt;
+		cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, ipd_prc_hold_ptr_fifo_ctl.u64);
+		ipd_prc_hold_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
+		cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_prc_hold_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+	    }
+	    ipd_prc_hold_ptr_fifo_ctl.s.cena = 1;
+	    cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, ipd_prc_hold_ptr_fifo_ctl.u64);
+	}
+
+	/* Free all packets in the fifo */
+	if (ipd_ptr_count.s.pkt_pcnt) {
+	    int i;
+	    cvmx_ipd_pwp_ptr_fifo_ctl_t ipd_pwp_ptr_fifo_ctl;
+	    ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
+
+	    for (i = 0; i < ipd_ptr_count.s.pkt_pcnt; i++) {
+		ipd_pwp_ptr_fifo_ctl.s.cena = 0;
+		ipd_pwp_ptr_fifo_ctl.s.raddr = (ipd_pwp_ptr_fifo_ctl.s.praddr+i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
+		cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
+		ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
+		cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_pwp_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+	    }
+	    ipd_pwp_ptr_fifo_ctl.s.cena = 1;
+	    cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
+	}
+    }
+}
+
+static void __cvmx_ipd_free_ptr_v2(void)
+{
+    int no_wptr = 0;
+    int i;
+    cvmx_ipd_port_ptr_fifo_ctl_t ipd_port_ptr_fifo_ctl;
+    cvmx_ipd_ptr_count_t ipd_ptr_count;
+    ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
+
+    /* Handle Work Queue Entry in cn68xx */
+    if (octeon_has_feature(OCTEON_FEATURE_NO_WPTR)) {
+        cvmx_ipd_ctl_status_t ipd_ctl_status;
+        ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+        if (ipd_ctl_status.s.no_wptr)
+            no_wptr = 1;
+    }
+
+    /* Free the prefetched WQE */
+    if (ipd_ptr_count.s.wqev_cnt) {
+        cvmx_ipd_next_wqe_ptr_t ipd_next_wqe_ptr;
+        ipd_next_wqe_ptr.u64 = cvmx_read_csr(CVMX_IPD_NEXT_WQE_PTR);
+        if (no_wptr)
+            cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_next_wqe_ptr.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+        else
+            cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_next_wqe_ptr.s.ptr<<7), CVMX_FPA_WQE_POOL, 0);
+    }
+
+
+    /* Free all WQE in the fifo */
+    if (ipd_ptr_count.s.wqe_pcnt) {
+        cvmx_ipd_free_ptr_fifo_ctl_t ipd_free_ptr_fifo_ctl;
+        cvmx_ipd_free_ptr_value_t ipd_free_ptr_value;
+        ipd_free_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_FREE_PTR_FIFO_CTL);
+        for (i = 0; i < ipd_ptr_count.s.wqe_pcnt; i++) {
+            ipd_free_ptr_fifo_ctl.s.cena = 0;
+            ipd_free_ptr_fifo_ctl.s.raddr = ipd_free_ptr_fifo_ctl.s.max_cnts + (ipd_free_ptr_fifo_ctl.s.wraddr+i) % ipd_free_ptr_fifo_ctl.s.max_cnts;
+            cvmx_write_csr(CVMX_IPD_FREE_PTR_FIFO_CTL, ipd_free_ptr_fifo_ctl.u64);
+            ipd_free_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_FREE_PTR_FIFO_CTL);
+            ipd_free_ptr_value.u64 = cvmx_read_csr(CVMX_IPD_FREE_PTR_VALUE);
+            if (no_wptr)
+                cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_free_ptr_value.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+            else
+                cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_free_ptr_value.s.ptr<<7), CVMX_FPA_WQE_POOL, 0);
+        }
+        ipd_free_ptr_fifo_ctl.s.cena = 1;
+        cvmx_write_csr(CVMX_IPD_FREE_PTR_FIFO_CTL, ipd_free_ptr_fifo_ctl.u64);
+    }
+
+    /* Free the prefetched packet */
+    if (ipd_ptr_count.s.pktv_cnt) {
+        cvmx_ipd_next_pkt_ptr_t ipd_next_pkt_ptr;
+        ipd_next_pkt_ptr.u64 = cvmx_read_csr(CVMX_IPD_NEXT_PKT_PTR);
+        cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_next_pkt_ptr.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+    }
+
+    /* Free the per port prefetched packets */
+    ipd_port_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PORT_PTR_FIFO_CTL);
+
+    for (i = 0; i < ipd_port_ptr_fifo_ctl.s.max_pkt; i++) {
+        ipd_port_ptr_fifo_ctl.s.cena = 0;
+        ipd_port_ptr_fifo_ctl.s.raddr = i % ipd_port_ptr_fifo_ctl.s.max_pkt;
+        cvmx_write_csr(CVMX_IPD_PORT_PTR_FIFO_CTL, ipd_port_ptr_fifo_ctl.u64);
+        ipd_port_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PORT_PTR_FIFO_CTL);
+        cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_port_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+    }
+    ipd_port_ptr_fifo_ctl.s.cena = 1;
+    cvmx_write_csr(CVMX_IPD_PORT_PTR_FIFO_CTL, ipd_port_ptr_fifo_ctl.u64);
+
+    /* Free all packets in the holding fifo */
+    if (ipd_ptr_count.s.pfif_cnt) {
+        cvmx_ipd_hold_ptr_fifo_ctl_t ipd_hold_ptr_fifo_ctl;
+
+        ipd_hold_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_HOLD_PTR_FIFO_CTL);
+
+        for (i = 0; i < ipd_ptr_count.s.pfif_cnt; i++) {
+            ipd_hold_ptr_fifo_ctl.s.cena = 0;
+            ipd_hold_ptr_fifo_ctl.s.raddr = (ipd_hold_ptr_fifo_ctl.s.praddr + i) % ipd_hold_ptr_fifo_ctl.s.max_pkt;
+            cvmx_write_csr(CVMX_IPD_HOLD_PTR_FIFO_CTL, ipd_hold_ptr_fifo_ctl.u64);
+            ipd_hold_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_HOLD_PTR_FIFO_CTL);
+            cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_hold_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+        }
+        ipd_hold_ptr_fifo_ctl.s.cena = 1;
+        cvmx_write_csr(CVMX_IPD_HOLD_PTR_FIFO_CTL, ipd_hold_ptr_fifo_ctl.u64);
+    }
+
+    /* Free all packets in the fifo */
+    if (ipd_ptr_count.s.pkt_pcnt) {
+        cvmx_ipd_free_ptr_fifo_ctl_t ipd_free_ptr_fifo_ctl;
+        cvmx_ipd_free_ptr_value_t ipd_free_ptr_value;
+        ipd_free_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_FREE_PTR_FIFO_CTL);
+
+        for (i = 0; i < ipd_ptr_count.s.pkt_pcnt; i++) {
+            ipd_free_ptr_fifo_ctl.s.cena = 0;
+            ipd_free_ptr_fifo_ctl.s.raddr = (ipd_free_ptr_fifo_ctl.s.praddr+i) % ipd_free_ptr_fifo_ctl.s.max_cnts;
+            cvmx_write_csr(CVMX_IPD_FREE_PTR_FIFO_CTL, ipd_free_ptr_fifo_ctl.u64);
+            ipd_free_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_FREE_PTR_FIFO_CTL);
+            ipd_free_ptr_value.u64 = cvmx_read_csr(CVMX_IPD_FREE_PTR_VALUE);
+            cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_free_ptr_value.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+        }
+        ipd_free_ptr_fifo_ctl.s.cena = 1;
+        cvmx_write_csr(CVMX_IPD_FREE_PTR_FIFO_CTL, ipd_free_ptr_fifo_ctl.u64);
+    }
+}
+
+/**
+ * @INTERNAL
+ * This function is called by cvmx_helper_shutdown() to extract
+ * all FPA buffers out of the IPD and PIP. After this function
+ * completes, all FPA buffers that were prefetched by IPD and PIP
+ * wil be in the apropriate FPA pool. This functions does not reset
+ * PIP or IPD as FPA pool zero must be empty before the reset can
+ * be performed. WARNING: It is very important that IPD and PIP be
+ * reset soon after a call to this function.
+ */
+void __cvmx_ipd_free_ptr(void)
+{
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+        __cvmx_ipd_free_ptr_v2();
+    else
+        __cvmx_ipd_free_ptr_v1();
+}
+
+#endif
+
diff --git a/sys/contrib/octeon-sdk/cvmx-ipd.h b/sys/contrib/octeon-sdk/cvmx-ipd.h
index c6c7bf9..3765a35 100644
--- a/sys/contrib/octeon-sdk/cvmx-ipd.h
+++ b/sys/contrib/octeon-sdk/cvmx-ipd.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Interface to the hardware Input Packet Data unit.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 
@@ -159,17 +159,26 @@ static inline void cvmx_ipd_config(uint64_t mbuff_size,
 static inline void cvmx_ipd_enable(void)
 {
     cvmx_ipd_ctl_status_t ipd_reg;
+
     ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+
+    /*
+     * busy-waiting for rst_done in o68
+     */
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+        while(ipd_reg.s.rst_done != 0)
+            ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+
     if (ipd_reg.s.ipd_en)
-    {
         cvmx_dprintf("Warning: Enabling IPD when IPD already enabled.\n");
-    }
+
     ipd_reg.s.ipd_en = 1;
-    #if  CVMX_ENABLE_LEN_M8_FIX
-    if(!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
+
+#if  CVMX_ENABLE_LEN_M8_FIX
+    if(!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
         ipd_reg.s.len_m8 = 1;
-    }
-    #endif
+#endif
+
     cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
 }
 
@@ -185,123 +194,7 @@ static inline void cvmx_ipd_disable(void)
     cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
 }
 
-#ifdef CVMX_ENABLE_PKO_FUNCTIONS
-/**
- * @INTERNAL
- * This function is called by cvmx_helper_shutdown() to extract
- * all FPA buffers out of the IPD and PIP. After this function
- * completes, all FPA buffers that were prefetched by IPD and PIP
- * wil be in the apropriate FPA pool. This functions does not reset
- * PIP or IPD as FPA pool zero must be empty before the reset can
- * be performed. WARNING: It is very important that IPD and PIP be
- * reset soon after a call to this function.
- */
-static inline void __cvmx_ipd_free_ptr(void)
-{
-    /* Only CN38XXp{1,2} cannot read pointer out of the IPD */
-    if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
-	int no_wptr = 0;
-	cvmx_ipd_ptr_count_t ipd_ptr_count;
-	ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
-
-	/* Handle Work Queue Entry in cn56xx and cn52xx */
-	if (octeon_has_feature(OCTEON_FEATURE_NO_WPTR)) {
-	    cvmx_ipd_ctl_status_t ipd_ctl_status;
-	    ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
-	    if (ipd_ctl_status.s.no_wptr)
-		no_wptr = 1;
-	}
-
-	/* Free the prefetched WQE */
-	if (ipd_ptr_count.s.wqev_cnt) {
-	    cvmx_ipd_wqe_ptr_valid_t ipd_wqe_ptr_valid;
-	    ipd_wqe_ptr_valid.u64 = cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID);
-	    if (no_wptr)
-	        cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_wqe_ptr_valid.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
-	    else
-	        cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_wqe_ptr_valid.s.ptr<<7), CVMX_FPA_WQE_POOL, 0);
-	}
-
-	/* Free all WQE in the fifo */
-	if (ipd_ptr_count.s.wqe_pcnt) {
-	    int i;
-	    cvmx_ipd_pwp_ptr_fifo_ctl_t ipd_pwp_ptr_fifo_ctl;
-	    ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
-	    for (i = 0; i < ipd_ptr_count.s.wqe_pcnt; i++) {
-		ipd_pwp_ptr_fifo_ctl.s.cena = 0;
-		ipd_pwp_ptr_fifo_ctl.s.raddr = ipd_pwp_ptr_fifo_ctl.s.max_cnts + (ipd_pwp_ptr_fifo_ctl.s.wraddr+i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
-		cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
-		ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
-		if (no_wptr)
-		    cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_pwp_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
-		else
-		    cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_pwp_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_WQE_POOL, 0);
-	    }
-	    ipd_pwp_ptr_fifo_ctl.s.cena = 1;
-	    cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
-	}
-
-	/* Free the prefetched packet */
-	if (ipd_ptr_count.s.pktv_cnt) {
-	    cvmx_ipd_pkt_ptr_valid_t ipd_pkt_ptr_valid;
-	    ipd_pkt_ptr_valid.u64 = cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID);
-	    cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_pkt_ptr_valid.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
-	}
-
-	/* Free the per port prefetched packets */
-	if (1) {
-	    int i;
-	    cvmx_ipd_prc_port_ptr_fifo_ctl_t ipd_prc_port_ptr_fifo_ctl;
-	    ipd_prc_port_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
-
-	    for (i = 0; i < ipd_prc_port_ptr_fifo_ctl.s.max_pkt; i++) {
-		ipd_prc_port_ptr_fifo_ctl.s.cena = 0;
-		ipd_prc_port_ptr_fifo_ctl.s.raddr = i % ipd_prc_port_ptr_fifo_ctl.s.max_pkt;
-		cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, ipd_prc_port_ptr_fifo_ctl.u64);
-		ipd_prc_port_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
-		cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_prc_port_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
-	    }
-	    ipd_prc_port_ptr_fifo_ctl.s.cena = 1;
-	    cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, ipd_prc_port_ptr_fifo_ctl.u64);
-	}
-
-	/* Free all packets in the holding fifo */
-	if (ipd_ptr_count.s.pfif_cnt) {
-	    int i;
-	    cvmx_ipd_prc_hold_ptr_fifo_ctl_t ipd_prc_hold_ptr_fifo_ctl;
-
-	    ipd_prc_hold_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
-
-	    for (i = 0; i < ipd_ptr_count.s.pfif_cnt; i++) {
-		ipd_prc_hold_ptr_fifo_ctl.s.cena = 0;
-		ipd_prc_hold_ptr_fifo_ctl.s.raddr = (ipd_prc_hold_ptr_fifo_ctl.s.praddr + i) % ipd_prc_hold_ptr_fifo_ctl.s.max_pkt;
-		cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, ipd_prc_hold_ptr_fifo_ctl.u64);
-		ipd_prc_hold_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
-		cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_prc_hold_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
-	    }
-	    ipd_prc_hold_ptr_fifo_ctl.s.cena = 1;
-	    cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, ipd_prc_hold_ptr_fifo_ctl.u64);
-	}
-
-	/* Free all packets in the fifo */
-	if (ipd_ptr_count.s.pkt_pcnt) {
-	    int i;
-	    cvmx_ipd_pwp_ptr_fifo_ctl_t ipd_pwp_ptr_fifo_ctl;
-	    ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
-
-	    for (i = 0; i < ipd_ptr_count.s.pkt_pcnt; i++) {
-		ipd_pwp_ptr_fifo_ctl.s.cena = 0;
-		ipd_pwp_ptr_fifo_ctl.s.raddr = (ipd_pwp_ptr_fifo_ctl.s.praddr+i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
-		cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
-		ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
-		cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_pwp_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
-	    }
-	    ipd_pwp_ptr_fifo_ctl.s.cena = 1;
-	    cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
-	}
-    }
-}
-#endif
+extern void __cvmx_ipd_free_ptr(void);
 
 #ifdef	__cplusplus
 }
diff --git a/sys/contrib/octeon-sdk/cvmx-ixf18201.c b/sys/contrib/octeon-sdk/cvmx-ixf18201.c
index 8f423d8..718b906 100644
--- a/sys/contrib/octeon-sdk/cvmx-ixf18201.c
+++ b/sys/contrib/octeon-sdk/cvmx-ixf18201.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-ixf18201.h b/sys/contrib/octeon-sdk/cvmx-ixf18201.h
index d387f5e..6a39c0bf 100644
--- a/sys/contrib/octeon-sdk/cvmx-ixf18201.h
+++ b/sys/contrib/octeon-sdk/cvmx-ixf18201.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-key-defs.h b/sys/contrib/octeon-sdk/cvmx-key-defs.h
index cf22a0c..10b56fb 100644
--- a/sys/contrib/octeon-sdk/cvmx-key-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-key-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,14 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_KEY_TYPEDEFS_H__
-#define __CVMX_KEY_TYPEDEFS_H__
+#ifndef __CVMX_KEY_DEFS_H__
+#define __CVMX_KEY_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_KEY_BIST_REG CVMX_KEY_BIST_REG_FUNC()
 static inline uint64_t CVMX_KEY_BIST_REG_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_KEY_BIST_REG not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180020000018ull);
 }
@@ -67,7 +67,7 @@ static inline uint64_t CVMX_KEY_BIST_REG_FUNC(void)
 #define CVMX_KEY_CTL_STATUS CVMX_KEY_CTL_STATUS_FUNC()
 static inline uint64_t CVMX_KEY_CTL_STATUS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_KEY_CTL_STATUS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180020000010ull);
 }
@@ -78,7 +78,7 @@ static inline uint64_t CVMX_KEY_CTL_STATUS_FUNC(void)
 #define CVMX_KEY_INT_ENB CVMX_KEY_INT_ENB_FUNC()
 static inline uint64_t CVMX_KEY_INT_ENB_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_KEY_INT_ENB not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180020000008ull);
 }
@@ -89,7 +89,7 @@ static inline uint64_t CVMX_KEY_INT_ENB_FUNC(void)
 #define CVMX_KEY_INT_SUM CVMX_KEY_INT_SUM_FUNC()
 static inline uint64_t CVMX_KEY_INT_SUM_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_KEY_INT_SUM not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180020000000ull);
 }
@@ -104,12 +104,10 @@ static inline uint64_t CVMX_KEY_INT_SUM_FUNC(void)
  *
  * The KEY's BIST status for memories.
  */
-union cvmx_key_bist_reg
-{
+union cvmx_key_bist_reg {
 	uint64_t u64;
-	struct cvmx_key_bist_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_key_bist_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t rrc                          : 1;  /**< RRC bist status. */
 	uint64_t mem1                         : 1;  /**< MEM - 1 bist status. */
@@ -127,8 +125,13 @@ union cvmx_key_bist_reg
 	struct cvmx_key_bist_reg_s            cn56xxp1;
 	struct cvmx_key_bist_reg_s            cn58xx;
 	struct cvmx_key_bist_reg_s            cn58xxp1;
+	struct cvmx_key_bist_reg_s            cn61xx;
 	struct cvmx_key_bist_reg_s            cn63xx;
 	struct cvmx_key_bist_reg_s            cn63xxp1;
+	struct cvmx_key_bist_reg_s            cn66xx;
+	struct cvmx_key_bist_reg_s            cn68xx;
+	struct cvmx_key_bist_reg_s            cn68xxp1;
+	struct cvmx_key_bist_reg_s            cnf71xx;
 };
 typedef union cvmx_key_bist_reg cvmx_key_bist_reg_t;
 
@@ -139,12 +142,10 @@ typedef union cvmx_key_bist_reg cvmx_key_bist_reg_t;
  *
  * The KEY's interrupt enable register.
  */
-union cvmx_key_ctl_status
-{
+union cvmx_key_ctl_status {
 	uint64_t u64;
-	struct cvmx_key_ctl_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_key_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t mem1_err                     : 7;  /**< Causes a flip of the ECC bit associated 38:32
                                                          respective to bit 13:7 of this field, for FPF
@@ -164,8 +165,13 @@ union cvmx_key_ctl_status
 	struct cvmx_key_ctl_status_s          cn56xxp1;
 	struct cvmx_key_ctl_status_s          cn58xx;
 	struct cvmx_key_ctl_status_s          cn58xxp1;
+	struct cvmx_key_ctl_status_s          cn61xx;
 	struct cvmx_key_ctl_status_s          cn63xx;
 	struct cvmx_key_ctl_status_s          cn63xxp1;
+	struct cvmx_key_ctl_status_s          cn66xx;
+	struct cvmx_key_ctl_status_s          cn68xx;
+	struct cvmx_key_ctl_status_s          cn68xxp1;
+	struct cvmx_key_ctl_status_s          cnf71xx;
 };
 typedef union cvmx_key_ctl_status cvmx_key_ctl_status_t;
 
@@ -176,12 +182,10 @@ typedef union cvmx_key_ctl_status cvmx_key_ctl_status_t;
  *
  * The KEY's interrupt enable register.
  */
-union cvmx_key_int_enb
-{
+union cvmx_key_int_enb {
 	uint64_t u64;
-	struct cvmx_key_int_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_key_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t ked1_dbe                     : 1;  /**< When set (1) and bit 3 of the KEY_INT_SUM
                                                          register is asserted the KEY will assert an
@@ -209,8 +213,13 @@ union cvmx_key_int_enb
 	struct cvmx_key_int_enb_s             cn56xxp1;
 	struct cvmx_key_int_enb_s             cn58xx;
 	struct cvmx_key_int_enb_s             cn58xxp1;
+	struct cvmx_key_int_enb_s             cn61xx;
 	struct cvmx_key_int_enb_s             cn63xx;
 	struct cvmx_key_int_enb_s             cn63xxp1;
+	struct cvmx_key_int_enb_s             cn66xx;
+	struct cvmx_key_int_enb_s             cn68xx;
+	struct cvmx_key_int_enb_s             cn68xxp1;
+	struct cvmx_key_int_enb_s             cnf71xx;
 };
 typedef union cvmx_key_int_enb cvmx_key_int_enb_t;
 
@@ -221,12 +230,10 @@ typedef union cvmx_key_int_enb cvmx_key_int_enb_t;
  *
  * Contains the diffrent interrupt summary bits of the KEY.
  */
-union cvmx_key_int_sum
-{
+union cvmx_key_int_sum {
 	uint64_t u64;
-	struct cvmx_key_int_sum_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_key_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t ked1_dbe                     : 1;
 	uint64_t ked1_sbe                     : 1;
@@ -246,8 +253,13 @@ union cvmx_key_int_sum
 	struct cvmx_key_int_sum_s             cn56xxp1;
 	struct cvmx_key_int_sum_s             cn58xx;
 	struct cvmx_key_int_sum_s             cn58xxp1;
+	struct cvmx_key_int_sum_s             cn61xx;
 	struct cvmx_key_int_sum_s             cn63xx;
 	struct cvmx_key_int_sum_s             cn63xxp1;
+	struct cvmx_key_int_sum_s             cn66xx;
+	struct cvmx_key_int_sum_s             cn68xx;
+	struct cvmx_key_int_sum_s             cn68xxp1;
+	struct cvmx_key_int_sum_s             cnf71xx;
 };
 typedef union cvmx_key_int_sum cvmx_key_int_sum_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-key.h b/sys/contrib/octeon-sdk/cvmx-key.h
index c4754d8..7e5c67d 100644
--- a/sys/contrib/octeon-sdk/cvmx-key.h
+++ b/sys/contrib/octeon-sdk/cvmx-key.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -50,7 +50,7 @@
  * 8k on chip that is inaccessible from off chip. It can
  * also be cleared using an external hardware pin.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-l2c-defs.h b/sys/contrib/octeon-sdk/cvmx-l2c-defs.h
index f0dd6d4..0c93ad3 100644
--- a/sys/contrib/octeon-sdk/cvmx-l2c-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-l2c-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,14 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_L2C_TYPEDEFS_H__
-#define __CVMX_L2C_TYPEDEFS_H__
+#ifndef __CVMX_L2C_DEFS_H__
+#define __CVMX_L2C_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_L2C_BIG_CTL CVMX_L2C_BIG_CTL_FUNC()
 static inline uint64_t CVMX_L2C_BIG_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_L2C_BIG_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180080800030ull);
 }
@@ -67,7 +67,7 @@ static inline uint64_t CVMX_L2C_BIG_CTL_FUNC(void)
 #define CVMX_L2C_BST CVMX_L2C_BST_FUNC()
 static inline uint64_t CVMX_L2C_BST_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_L2C_BST not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800808007F8ull);
 }
@@ -111,34 +111,46 @@ static inline uint64_t CVMX_L2C_BST2_FUNC(void)
 static inline uint64_t CVMX_L2C_BST_MEMX(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_L2C_BST_MEMX(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080C007F8ull);
+	return CVMX_ADD_IO_SEG(0x0001180080C007F8ull) + ((block_id) & 3) * 0x40000ull;
 }
 #else
-#define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull))
+#define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull) + ((block_id) & 3) * 0x40000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_L2C_BST_TDTX(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_L2C_BST_TDTX(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080A007F0ull);
+	return CVMX_ADD_IO_SEG(0x0001180080A007F0ull) + ((block_id) & 3) * 0x40000ull;
 }
 #else
-#define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull))
+#define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull) + ((block_id) & 3) * 0x40000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_L2C_BST_TTGX(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_L2C_BST_TTGX(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080A007F8ull);
+	return CVMX_ADD_IO_SEG(0x0001180080A007F8ull) + ((block_id) & 3) * 0x40000ull;
 }
 #else
-#define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull))
+#define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull) + ((block_id) & 3) * 0x40000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_L2C_CFG CVMX_L2C_CFG_FUNC()
@@ -155,7 +167,11 @@ static inline uint64_t CVMX_L2C_CFG_FUNC(void)
 static inline uint64_t CVMX_L2C_COP0_MAPX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1535) || ((offset >= 16128) && (offset <= 16383))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1023) || ((offset >= 16128) && (offset <= 16383)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1535) || ((offset >= 16128) && (offset <= 16383)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 2559) || ((offset >= 16128) && (offset <= 16383)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8191) || ((offset >= 16128) && (offset <= 16383)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1023) || ((offset >= 16128) && (offset <= 16383))))))
 		cvmx_warn("CVMX_L2C_COP0_MAPX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180080940000ull) + ((offset) & 16383) * 8;
 }
@@ -166,7 +182,7 @@ static inline uint64_t CVMX_L2C_COP0_MAPX(unsigned long offset)
 #define CVMX_L2C_CTL CVMX_L2C_CTL_FUNC()
 static inline uint64_t CVMX_L2C_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_L2C_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180080800000ull);
 }
@@ -199,51 +215,67 @@ static inline uint64_t CVMX_L2C_DUT_FUNC(void)
 static inline uint64_t CVMX_L2C_DUT_MAPX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1535)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1023))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1535))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 2559))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8191))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1023)))))
 		cvmx_warn("CVMX_L2C_DUT_MAPX(%lu) is invalid on this chip\n", offset);
-	return CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 2047) * 8;
+	return CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 8191) * 8;
 }
 #else
-#define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 2047) * 8)
+#define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 8191) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_L2C_ERR_TDTX(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_L2C_ERR_TDTX(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080A007E0ull);
+	return CVMX_ADD_IO_SEG(0x0001180080A007E0ull) + ((block_id) & 3) * 0x40000ull;
 }
 #else
-#define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull))
+#define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull) + ((block_id) & 3) * 0x40000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_L2C_ERR_TTGX(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_L2C_ERR_TTGX(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080A007E8ull);
+	return CVMX_ADD_IO_SEG(0x0001180080A007E8ull) + ((block_id) & 3) * 0x40000ull;
 }
 #else
-#define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull))
+#define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull) + ((block_id) & 3) * 0x40000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_L2C_ERR_VBFX(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_L2C_ERR_VBFX(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080C007F0ull);
+	return CVMX_ADD_IO_SEG(0x0001180080C007F0ull) + ((block_id) & 3) * 0x40000ull;
 }
 #else
-#define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull))
+#define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull) + ((block_id) & 3) * 0x40000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_L2C_ERR_XMC CVMX_L2C_ERR_XMC_FUNC()
 static inline uint64_t CVMX_L2C_ERR_XMC_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_L2C_ERR_XMC not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800808007D8ull);
 }
@@ -287,7 +319,7 @@ static inline uint64_t CVMX_L2C_INT_EN_FUNC(void)
 #define CVMX_L2C_INT_ENA CVMX_L2C_INT_ENA_FUNC()
 static inline uint64_t CVMX_L2C_INT_ENA_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_L2C_INT_ENA not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180080800020ull);
 }
@@ -298,7 +330,7 @@ static inline uint64_t CVMX_L2C_INT_ENA_FUNC(void)
 #define CVMX_L2C_INT_REG CVMX_L2C_INT_REG_FUNC()
 static inline uint64_t CVMX_L2C_INT_REG_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_L2C_INT_REG not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180080800018ull);
 }
@@ -320,7 +352,11 @@ static inline uint64_t CVMX_L2C_INT_STAT_FUNC(void)
 static inline uint64_t CVMX_L2C_IOCX_PFC(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_L2C_IOCX_PFC(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x0001180080800420ull);
 }
@@ -331,7 +367,11 @@ static inline uint64_t CVMX_L2C_IOCX_PFC(unsigned long block_id)
 static inline uint64_t CVMX_L2C_IORX_PFC(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_L2C_IORX_PFC(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x0001180080800428ull);
 }
@@ -492,32 +532,40 @@ static inline uint64_t CVMX_L2C_PPGRP_FUNC(void)
 #define CVMX_L2C_PPGRP (CVMX_ADD_IO_SEG(0x00011800800000C0ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_L2C_QOS_IOBX(unsigned long block_id)
+static inline uint64_t CVMX_L2C_QOS_IOBX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_L2C_QOS_IOBX(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080880200ull);
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0)))))
+		cvmx_warn("CVMX_L2C_QOS_IOBX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180080880200ull) + ((offset) & 1) * 8;
 }
 #else
-#define CVMX_L2C_QOS_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080880200ull))
+#define CVMX_L2C_QOS_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080880200ull) + ((offset) & 1) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_L2C_QOS_PPX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_L2C_QOS_PPX(%lu) is invalid on this chip\n", offset);
-	return CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 7) * 8;
+	return CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 31) * 8;
 }
 #else
-#define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 7) * 8)
+#define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 31) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_L2C_QOS_WGT CVMX_L2C_QOS_WGT_FUNC()
 static inline uint64_t CVMX_L2C_QOS_WGT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_L2C_QOS_WGT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180080800008ull);
 }
@@ -525,26 +573,34 @@ static inline uint64_t CVMX_L2C_QOS_WGT_FUNC(void)
 #define CVMX_L2C_QOS_WGT (CVMX_ADD_IO_SEG(0x0001180080800008ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_L2C_RSCX_PFC(unsigned long block_id)
+static inline uint64_t CVMX_L2C_RSCX_PFC(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_L2C_RSCX_PFC(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080800410ull);
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0)))))
+		cvmx_warn("CVMX_L2C_RSCX_PFC(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180080800410ull) + ((offset) & 3) * 64;
 }
 #else
-#define CVMX_L2C_RSCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800410ull))
+#define CVMX_L2C_RSCX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800410ull) + ((offset) & 3) * 64)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_L2C_RSDX_PFC(unsigned long block_id)
+static inline uint64_t CVMX_L2C_RSDX_PFC(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_L2C_RSDX_PFC(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080800418ull);
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0)))))
+		cvmx_warn("CVMX_L2C_RSDX_PFC(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180080800418ull) + ((offset) & 3) * 64;
 }
 #else
-#define CVMX_L2C_RSDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800418ull))
+#define CVMX_L2C_RSDX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800418ull) + ((offset) & 3) * 64)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_L2C_SPAR0 CVMX_L2C_SPAR0_FUNC()
@@ -605,117 +661,157 @@ static inline uint64_t CVMX_L2C_SPAR4_FUNC(void)
 static inline uint64_t CVMX_L2C_TADX_ECC0(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_L2C_TADX_ECC0(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080A00018ull);
+	return CVMX_ADD_IO_SEG(0x0001180080A00018ull) + ((block_id) & 3) * 0x40000ull;
 }
 #else
-#define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull))
+#define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull) + ((block_id) & 3) * 0x40000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_L2C_TADX_ECC1(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_L2C_TADX_ECC1(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080A00020ull);
+	return CVMX_ADD_IO_SEG(0x0001180080A00020ull) + ((block_id) & 3) * 0x40000ull;
 }
 #else
-#define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull))
+#define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull) + ((block_id) & 3) * 0x40000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_L2C_TADX_IEN(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_L2C_TADX_IEN(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080A00000ull);
+	return CVMX_ADD_IO_SEG(0x0001180080A00000ull) + ((block_id) & 3) * 0x40000ull;
 }
 #else
-#define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull))
+#define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull) + ((block_id) & 3) * 0x40000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_L2C_TADX_INT(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_L2C_TADX_INT(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080A00028ull);
+	return CVMX_ADD_IO_SEG(0x0001180080A00028ull) + ((block_id) & 3) * 0x40000ull;
 }
 #else
-#define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull))
+#define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull) + ((block_id) & 3) * 0x40000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_L2C_TADX_PFC0(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_L2C_TADX_PFC0(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080A00400ull);
+	return CVMX_ADD_IO_SEG(0x0001180080A00400ull) + ((block_id) & 3) * 0x40000ull;
 }
 #else
-#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull))
+#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + ((block_id) & 3) * 0x40000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_L2C_TADX_PFC1(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_L2C_TADX_PFC1(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080A00408ull);
+	return CVMX_ADD_IO_SEG(0x0001180080A00408ull) + ((block_id) & 3) * 0x40000ull;
 }
 #else
-#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull))
+#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull) + ((block_id) & 3) * 0x40000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_L2C_TADX_PFC2(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_L2C_TADX_PFC2(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080A00410ull);
+	return CVMX_ADD_IO_SEG(0x0001180080A00410ull) + ((block_id) & 3) * 0x40000ull;
 }
 #else
-#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull))
+#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull) + ((block_id) & 3) * 0x40000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_L2C_TADX_PFC3(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_L2C_TADX_PFC3(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080A00418ull);
+	return CVMX_ADD_IO_SEG(0x0001180080A00418ull) + ((block_id) & 3) * 0x40000ull;
 }
 #else
-#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull))
+#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull) + ((block_id) & 3) * 0x40000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_L2C_TADX_PRF(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_L2C_TADX_PRF(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080A00008ull);
+	return CVMX_ADD_IO_SEG(0x0001180080A00008ull) + ((block_id) & 3) * 0x40000ull;
 }
 #else
-#define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull))
+#define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull) + ((block_id) & 3) * 0x40000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_L2C_TADX_TAG(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_L2C_TADX_TAG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080A00010ull);
+	return CVMX_ADD_IO_SEG(0x0001180080A00010ull) + ((block_id) & 3) * 0x40000ull;
 }
 #else
-#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull))
+#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull) + ((block_id) & 3) * 0x40000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_L2C_VER_ID CVMX_L2C_VER_ID_FUNC()
 static inline uint64_t CVMX_L2C_VER_ID_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_L2C_VER_ID not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800808007E0ull);
 }
@@ -726,7 +822,7 @@ static inline uint64_t CVMX_L2C_VER_ID_FUNC(void)
 #define CVMX_L2C_VER_IOB CVMX_L2C_VER_IOB_FUNC()
 static inline uint64_t CVMX_L2C_VER_IOB_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_L2C_VER_IOB not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800808007F0ull);
 }
@@ -737,7 +833,7 @@ static inline uint64_t CVMX_L2C_VER_IOB_FUNC(void)
 #define CVMX_L2C_VER_MSC CVMX_L2C_VER_MSC_FUNC()
 static inline uint64_t CVMX_L2C_VER_MSC_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_L2C_VER_MSC not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800808007D0ull);
 }
@@ -748,7 +844,7 @@ static inline uint64_t CVMX_L2C_VER_MSC_FUNC(void)
 #define CVMX_L2C_VER_PP CVMX_L2C_VER_PP_FUNC()
 static inline uint64_t CVMX_L2C_VER_PP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_L2C_VER_PP not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800808007E8ull);
 }
@@ -756,32 +852,40 @@ static inline uint64_t CVMX_L2C_VER_PP_FUNC(void)
 #define CVMX_L2C_VER_PP (CVMX_ADD_IO_SEG(0x00011800808007E8ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_L2C_VIRTID_IOBX(unsigned long block_id)
+static inline uint64_t CVMX_L2C_VIRTID_IOBX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_L2C_VIRTID_IOBX(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800808C0200ull);
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0)))))
+		cvmx_warn("CVMX_L2C_VIRTID_IOBX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800808C0200ull) + ((offset) & 1) * 8;
 }
 #else
-#define CVMX_L2C_VIRTID_IOBX(block_id) (CVMX_ADD_IO_SEG(0x00011800808C0200ull))
+#define CVMX_L2C_VIRTID_IOBX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0200ull) + ((offset) & 1) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_L2C_VIRTID_PPX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_L2C_VIRTID_PPX(%lu) is invalid on this chip\n", offset);
-	return CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 7) * 8;
+	return CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 31) * 8;
 }
 #else
-#define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 7) * 8)
+#define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 31) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_L2C_VRT_CTL CVMX_L2C_VRT_CTL_FUNC()
 static inline uint64_t CVMX_L2C_VRT_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_L2C_VRT_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180080800010ull);
 }
@@ -792,7 +896,11 @@ static inline uint64_t CVMX_L2C_VRT_CTL_FUNC(void)
 static inline uint64_t CVMX_L2C_VRT_MEMX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1023)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1023))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1023))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1023))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1023))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1023)))))
 		cvmx_warn("CVMX_L2C_VRT_MEMX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180080900000ull) + ((offset) & 1023) * 8;
 }
@@ -800,43 +908,55 @@ static inline uint64_t CVMX_L2C_VRT_MEMX(unsigned long offset)
 #define CVMX_L2C_VRT_MEMX(offset) (CVMX_ADD_IO_SEG(0x0001180080900000ull) + ((offset) & 1023) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_L2C_WPAR_IOBX(unsigned long block_id)
+static inline uint64_t CVMX_L2C_WPAR_IOBX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_L2C_WPAR_IOBX(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080840200ull);
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0)))))
+		cvmx_warn("CVMX_L2C_WPAR_IOBX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180080840200ull) + ((offset) & 1) * 8;
 }
 #else
-#define CVMX_L2C_WPAR_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080840200ull))
+#define CVMX_L2C_WPAR_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080840200ull) + ((offset) & 1) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_L2C_WPAR_PPX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_L2C_WPAR_PPX(%lu) is invalid on this chip\n", offset);
-	return CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 7) * 8;
+	return CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 31) * 8;
 }
 #else
-#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 7) * 8)
+#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 31) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_L2C_XMCX_PFC(unsigned long block_id)
+static inline uint64_t CVMX_L2C_XMCX_PFC(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_L2C_XMCX_PFC(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080800400ull);
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0)))))
+		cvmx_warn("CVMX_L2C_XMCX_PFC(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180080800400ull) + ((offset) & 3) * 64;
 }
 #else
-#define CVMX_L2C_XMCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800400ull))
+#define CVMX_L2C_XMCX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800400ull) + ((offset) & 3) * 64)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_L2C_XMC_CMD CVMX_L2C_XMC_CMD_FUNC()
 static inline uint64_t CVMX_L2C_XMC_CMD_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_L2C_XMC_CMD not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180080800028ull);
 }
@@ -844,15 +964,19 @@ static inline uint64_t CVMX_L2C_XMC_CMD_FUNC(void)
 #define CVMX_L2C_XMC_CMD (CVMX_ADD_IO_SEG(0x0001180080800028ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_L2C_XMDX_PFC(unsigned long block_id)
+static inline uint64_t CVMX_L2C_XMDX_PFC(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_L2C_XMDX_PFC(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180080800408ull);
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0)))))
+		cvmx_warn("CVMX_L2C_XMDX_PFC(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180080800408ull) + ((offset) & 3) * 64;
 }
 #else
-#define CVMX_L2C_XMDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800408ull))
+#define CVMX_L2C_XMDX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800408ull) + ((offset) & 3) * 64)
 #endif
 
 /**
@@ -868,12 +992,10 @@ static inline uint64_t CVMX_L2C_XMDX_PFC(unsigned long block_id)
  * (2) When HOLEWR/BIGWR blocks a store L2C_VER_ID, L2C_VER_PP, L2C_VER_IOB, and L2C_VER_MSC will be
  *     loaded just like a store which is blocked by VRTWR.  Additionally, L2C_ERR_XMC will be loaded.
  */
-union cvmx_l2c_big_ctl
-{
+union cvmx_l2c_big_ctl {
 	uint64_t u64;
-	struct cvmx_l2c_big_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_big_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t maxdram                      : 4;  /**< Amount of configured DRAM
                                                              0 = reserved
@@ -901,7 +1023,12 @@ union cvmx_l2c_big_ctl
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
+	struct cvmx_l2c_big_ctl_s             cn61xx;
 	struct cvmx_l2c_big_ctl_s             cn63xx;
+	struct cvmx_l2c_big_ctl_s             cn66xx;
+	struct cvmx_l2c_big_ctl_s             cn68xx;
+	struct cvmx_l2c_big_ctl_s             cn68xxp1;
+	struct cvmx_l2c_big_ctl_s             cnf71xx;
 };
 typedef union cvmx_l2c_big_ctl cvmx_l2c_big_ctl_t;
 
@@ -911,12 +1038,62 @@ typedef union cvmx_l2c_big_ctl cvmx_l2c_big_ctl_t;
  * L2C_BST = L2C BIST Status
  *
  */
-union cvmx_l2c_bst
-{
+union cvmx_l2c_bst {
 	uint64_t u64;
-	struct cvmx_l2c_bst_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t dutfl                        : 32; /**< BIST failure status for PP0-3 DUT */
+	uint64_t rbffl                        : 4;  /**< BIST failure status for RBF0-3 */
+	uint64_t xbffl                        : 4;  /**< BIST failure status for XBF0-3 */
+	uint64_t tdpfl                        : 4;  /**< BIST failure status for TDP0-3 */
+	uint64_t ioccmdfl                     : 4;  /**< BIST failure status for IOCCMD */
+	uint64_t iocdatfl                     : 4;  /**< BIST failure status for IOCDAT */
+	uint64_t dutresfl                     : 4;  /**< BIST failure status for DUTRES */
+	uint64_t vrtfl                        : 4;  /**< BIST failure status for VRT0 */
+	uint64_t tdffl                        : 4;  /**< BIST failure status for TDF0 */
+#else
+	uint64_t tdffl                        : 4;
+	uint64_t vrtfl                        : 4;
+	uint64_t dutresfl                     : 4;
+	uint64_t iocdatfl                     : 4;
+	uint64_t ioccmdfl                     : 4;
+	uint64_t tdpfl                        : 4;
+	uint64_t xbffl                        : 4;
+	uint64_t rbffl                        : 4;
+	uint64_t dutfl                        : 32;
+#endif
+	} s;
+	struct cvmx_l2c_bst_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_36_63               : 28;
+	uint64_t dutfl                        : 4;  /**< BIST failure status for PP0-3 DUT */
+	uint64_t reserved_17_31               : 15;
+	uint64_t ioccmdfl                     : 1;  /**< BIST failure status for IOCCMD */
+	uint64_t reserved_13_15               : 3;
+	uint64_t iocdatfl                     : 1;  /**< BIST failure status for IOCDAT */
+	uint64_t reserved_9_11                : 3;
+	uint64_t dutresfl                     : 1;  /**< BIST failure status for DUTRES */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t vrtfl                        : 1;  /**< BIST failure status for VRT0 */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t tdffl                        : 1;  /**< BIST failure status for TDF0 */
+#else
+	uint64_t tdffl                        : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t vrtfl                        : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t dutresfl                     : 1;
+	uint64_t reserved_9_11                : 3;
+	uint64_t iocdatfl                     : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t ioccmdfl                     : 1;
+	uint64_t reserved_17_31               : 15;
+	uint64_t dutfl                        : 4;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn61xx;
+	struct cvmx_l2c_bst_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_38_63               : 26;
 	uint64_t dutfl                        : 6;  /**< BIST failure status for PP0-5 DUT */
 	uint64_t reserved_17_31               : 15;
@@ -943,9 +1120,40 @@ union cvmx_l2c_bst
 	uint64_t dutfl                        : 6;
 	uint64_t reserved_38_63               : 26;
 #endif
-	} s;
-	struct cvmx_l2c_bst_s                 cn63xx;
-	struct cvmx_l2c_bst_s                 cn63xxp1;
+	} cn63xx;
+	struct cvmx_l2c_bst_cn63xx            cn63xxp1;
+	struct cvmx_l2c_bst_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_42_63               : 22;
+	uint64_t dutfl                        : 10; /**< BIST failure status for PP0-9 DUT */
+	uint64_t reserved_17_31               : 15;
+	uint64_t ioccmdfl                     : 1;  /**< BIST failure status for IOCCMD */
+	uint64_t reserved_13_15               : 3;
+	uint64_t iocdatfl                     : 1;  /**< BIST failure status for IOCDAT */
+	uint64_t reserved_9_11                : 3;
+	uint64_t dutresfl                     : 1;  /**< BIST failure status for DUTRES */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t vrtfl                        : 1;  /**< BIST failure status for VRT0 */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t tdffl                        : 1;  /**< BIST failure status for TDF0 */
+#else
+	uint64_t tdffl                        : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t vrtfl                        : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t dutresfl                     : 1;
+	uint64_t reserved_9_11                : 3;
+	uint64_t iocdatfl                     : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t ioccmdfl                     : 1;
+	uint64_t reserved_17_31               : 15;
+	uint64_t dutfl                        : 10;
+	uint64_t reserved_42_63               : 22;
+#endif
+	} cn66xx;
+	struct cvmx_l2c_bst_s                 cn68xx;
+	struct cvmx_l2c_bst_s                 cn68xxp1;
+	struct cvmx_l2c_bst_cn61xx            cnf71xx;
 };
 typedef union cvmx_l2c_bst cvmx_l2c_bst_t;
 
@@ -955,12 +1163,10 @@ typedef union cvmx_l2c_bst cvmx_l2c_bst_t;
  * L2C_BST0 = L2C BIST 0 CTL/STAT
  *
  */
-union cvmx_l2c_bst0
-{
+union cvmx_l2c_bst0 {
 	uint64_t u64;
-	struct cvmx_l2c_bst0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t dtbnk                        : 1;  /**< DuTag Bank#
                                                          When DT=1(BAD), this field provides additional information
@@ -992,9 +1198,8 @@ union cvmx_l2c_bst0
 	uint64_t reserved_24_63               : 40;
 #endif
 	} s;
-	struct cvmx_l2c_bst0_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst0_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_23_63               : 41;
 	uint64_t wlb_msk                      : 4;  /**< Bist Results for WLB-MSK RAM [DP0-3]
                                                          - 0: GOOD (or bist in progress/never run)
@@ -1021,9 +1226,8 @@ union cvmx_l2c_bst0
 	uint64_t reserved_23_63               : 41;
 #endif
 	} cn30xx;
-	struct cvmx_l2c_bst0_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst0_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_23_63               : 41;
 	uint64_t wlb_msk                      : 4;  /**< Bist Results for WLB-MSK RAM [DP0-3]
                                                          - 0: GOOD (or bist in progress/never run)
@@ -1053,9 +1257,8 @@ union cvmx_l2c_bst0
 	uint64_t reserved_23_63               : 41;
 #endif
 	} cn31xx;
-	struct cvmx_l2c_bst0_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst0_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t dtcnt                        : 13; /**< DuTag BiST Counter (used to help isolate the failure)
                                                          [12]:    i (0=FORWARD/1=REVERSE pass)
@@ -1080,9 +1283,8 @@ union cvmx_l2c_bst0
 #endif
 	} cn38xx;
 	struct cvmx_l2c_bst0_cn38xx           cn38xxp2;
-	struct cvmx_l2c_bst0_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst0_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t dtbnk                        : 1;  /**< DuTag Bank#
                                                          When DT=1(BAD), this field provides additional information
@@ -1131,12 +1333,10 @@ typedef union cvmx_l2c_bst0 cvmx_l2c_bst0_t;
  * L2C_BST1 = L2C BIST 1 CTL/STAT
  *
  */
-union cvmx_l2c_bst1
-{
+union cvmx_l2c_bst1 {
 	uint64_t u64;
-	struct cvmx_l2c_bst1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t l2t                          : 9;  /**< Bist Results for L2T (USE+8SET RAMs)
                                                          - 0: GOOD (or bist in progress/never run)
@@ -1146,9 +1346,8 @@ union cvmx_l2c_bst1
 	uint64_t reserved_9_63                : 55;
 #endif
 	} s;
-	struct cvmx_l2c_bst1_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst1_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t vwdf                         : 4;  /**< Bist Results for VWDF RAMs
                                                          - 0: GOOD (or bist in progress/never run)
@@ -1173,9 +1372,8 @@ union cvmx_l2c_bst1
 #endif
 	} cn30xx;
 	struct cvmx_l2c_bst1_cn30xx           cn31xx;
-	struct cvmx_l2c_bst1_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst1_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t vwdf                         : 4;  /**< Bist Results for VWDF RAMs
                                                          - 0: GOOD (or bist in progress/never run)
@@ -1199,9 +1397,8 @@ union cvmx_l2c_bst1
 	} cn38xx;
 	struct cvmx_l2c_bst1_cn38xx           cn38xxp2;
 	struct cvmx_l2c_bst1_cn38xx           cn50xx;
-	struct cvmx_l2c_bst1_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst1_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t plc2                         : 1;  /**< Bist Results for PLC2 RAM
                                                          - 0: GOOD (or bist in progress/never run)
@@ -1238,9 +1435,8 @@ union cvmx_l2c_bst1
 #endif
 	} cn52xx;
 	struct cvmx_l2c_bst1_cn52xx           cn52xxp1;
-	struct cvmx_l2c_bst1_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst1_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t plc2                         : 1;  /**< Bist Results for LRF RAMs (ILC)
                                                          - 0: GOOD (or bist in progress/never run)
@@ -1294,12 +1490,10 @@ typedef union cvmx_l2c_bst1 cvmx_l2c_bst1_t;
  * L2C_BST2 = L2C BIST 2 CTL/STAT
  *
  */
-union cvmx_l2c_bst2
-{
+union cvmx_l2c_bst2 {
 	uint64_t u64;
-	struct cvmx_l2c_bst2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t mrb                          : 4;  /**< Bist Results for MRB RAMs
                                                          - 0: GOOD (or bist in progress/never run)
@@ -1325,9 +1519,8 @@ union cvmx_l2c_bst2
 	uint64_t reserved_16_63               : 48;
 #endif
 	} s;
-	struct cvmx_l2c_bst2_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst2_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t mrb                          : 4;  /**< Bist Results for MRB RAMs
                                                          - 0: GOOD (or bist in progress/never run)
@@ -1358,9 +1551,8 @@ union cvmx_l2c_bst2
 #endif
 	} cn30xx;
 	struct cvmx_l2c_bst2_cn30xx           cn31xx;
-	struct cvmx_l2c_bst2_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst2_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t mrb                          : 4;  /**< Bist Results for MRB RAMs
                                                          - 0: GOOD (or bist in progress/never run)
@@ -1396,9 +1588,8 @@ union cvmx_l2c_bst2
 	struct cvmx_l2c_bst2_cn30xx           cn50xx;
 	struct cvmx_l2c_bst2_cn30xx           cn52xx;
 	struct cvmx_l2c_bst2_cn30xx           cn52xxp1;
-	struct cvmx_l2c_bst2_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst2_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t mrb                          : 4;  /**< Bist Results for MRB RAMs
                                                          - 0: GOOD (or bist in progress/never run)
@@ -1448,12 +1639,10 @@ typedef union cvmx_l2c_bst2 cvmx_l2c_bst2_t;
  * (2) CLEAR_BIST must not be changed after writing START_BIST to 1 until the BIST operation completes
  *     (indicated by START_BIST returning to 0) or operation is undefined.
  */
-union cvmx_l2c_bst_memx
-{
+union cvmx_l2c_bst_memx {
 	uint64_t u64;
-	struct cvmx_l2c_bst_memx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst_memx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t start_bist                   : 1;  /**< When written to 1, starts BIST.  Will read 1 until
                                                          BIST is complete (see Note). */
 	uint64_t clear_bist                   : 1;  /**< When BIST is triggered, run clear BIST (see Note) */
@@ -1468,8 +1657,13 @@ union cvmx_l2c_bst_memx
 	uint64_t start_bist                   : 1;
 #endif
 	} s;
+	struct cvmx_l2c_bst_memx_s            cn61xx;
 	struct cvmx_l2c_bst_memx_s            cn63xx;
 	struct cvmx_l2c_bst_memx_s            cn63xxp1;
+	struct cvmx_l2c_bst_memx_s            cn66xx;
+	struct cvmx_l2c_bst_memx_s            cn68xx;
+	struct cvmx_l2c_bst_memx_s            cn68xxp1;
+	struct cvmx_l2c_bst_memx_s            cnf71xx;
 };
 typedef union cvmx_l2c_bst_memx cvmx_l2c_bst_memx_t;
 
@@ -1479,16 +1673,14 @@ typedef union cvmx_l2c_bst_memx cvmx_l2c_bst_memx_t;
  * L2C_BST_TDT = L2C TAD DaTa BIST Status
  *
  */
-union cvmx_l2c_bst_tdtx
-{
+union cvmx_l2c_bst_tdtx {
 	uint64_t u64;
-	struct cvmx_l2c_bst_tdtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst_tdtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t fbfrspfl                     : 8;  /**< BIST failure status for quad 0-7 FBF RSP read port */
 	uint64_t sbffl                        : 8;  /**< BIST failure status for quad 0-7 SBF */
-	uint64_t fbffl                        : 8;  /**< BIST failure status for quad 0-7 FBF */
+	uint64_t fbffl                        : 8;  /**< BIST failure status for quad 0-7 FBF WRP read port */
 	uint64_t l2dfl                        : 8;  /**< BIST failure status for quad 0-7 L2D */
 #else
 	uint64_t l2dfl                        : 8;
@@ -1498,10 +1690,10 @@ union cvmx_l2c_bst_tdtx
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_l2c_bst_tdtx_s            cn61xx;
 	struct cvmx_l2c_bst_tdtx_s            cn63xx;
-	struct cvmx_l2c_bst_tdtx_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst_tdtx_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t sbffl                        : 8;  /**< BIST failure status for quad 0-7 SBF */
 	uint64_t fbffl                        : 8;  /**< BIST failure status for quad 0-7 FBF */
@@ -1513,6 +1705,10 @@ union cvmx_l2c_bst_tdtx
 	uint64_t reserved_24_63               : 40;
 #endif
 	} cn63xxp1;
+	struct cvmx_l2c_bst_tdtx_s            cn66xx;
+	struct cvmx_l2c_bst_tdtx_s            cn68xx;
+	struct cvmx_l2c_bst_tdtx_s            cn68xxp1;
+	struct cvmx_l2c_bst_tdtx_s            cnf71xx;
 };
 typedef union cvmx_l2c_bst_tdtx cvmx_l2c_bst_tdtx_t;
 
@@ -1522,12 +1718,10 @@ typedef union cvmx_l2c_bst_tdtx cvmx_l2c_bst_tdtx_t;
  * L2C_BST_TTG = L2C TAD TaG BIST Status
  *
  */
-union cvmx_l2c_bst_ttgx
-{
+union cvmx_l2c_bst_ttgx {
 	uint64_t u64;
-	struct cvmx_l2c_bst_ttgx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_bst_ttgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t lrufl                        : 1;  /**< BIST failure status for tag LRU */
 	uint64_t tagfl                        : 16; /**< BIST failure status for tag ways 0-15 */
@@ -1537,8 +1731,13 @@ union cvmx_l2c_bst_ttgx
 	uint64_t reserved_17_63               : 47;
 #endif
 	} s;
+	struct cvmx_l2c_bst_ttgx_s            cn61xx;
 	struct cvmx_l2c_bst_ttgx_s            cn63xx;
 	struct cvmx_l2c_bst_ttgx_s            cn63xxp1;
+	struct cvmx_l2c_bst_ttgx_s            cn66xx;
+	struct cvmx_l2c_bst_ttgx_s            cn68xx;
+	struct cvmx_l2c_bst_ttgx_s            cn68xxp1;
+	struct cvmx_l2c_bst_ttgx_s            cnf71xx;
 };
 typedef union cvmx_l2c_bst_ttgx cvmx_l2c_bst_ttgx_t;
 
@@ -1551,12 +1750,10 @@ typedef union cvmx_l2c_bst_ttgx cvmx_l2c_bst_ttgx_t;
  *
  * Description:
  */
-union cvmx_l2c_cfg
-{
+union cvmx_l2c_cfg {
 	uint64_t u64;
-	struct cvmx_l2c_cfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t bstrun                       : 1;  /**< L2 Data Store Bist Running
                                                          Indicates when the L2C HW Bist sequence(short or long) is
@@ -1696,9 +1893,8 @@ union cvmx_l2c_cfg
 	uint64_t reserved_20_63               : 44;
 #endif
 	} s;
-	struct cvmx_l2c_cfg_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_cfg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t fpexp                        : 4;  /**< [CYA] Forward Progress Counter Exponent
                                                          NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
@@ -1784,9 +1980,8 @@ union cvmx_l2c_cfg
 	struct cvmx_l2c_cfg_cn30xx            cn31xx;
 	struct cvmx_l2c_cfg_cn30xx            cn38xx;
 	struct cvmx_l2c_cfg_cn30xx            cn38xxp2;
-	struct cvmx_l2c_cfg_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_cfg_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t bstrun                       : 1;  /**< L2 Data Store Bist Running
                                                          Indicates when the L2C HW Bist sequence(short or long) is
@@ -1889,9 +2084,8 @@ union cvmx_l2c_cfg
 	struct cvmx_l2c_cfg_cn50xx            cn52xxp1;
 	struct cvmx_l2c_cfg_s                 cn56xx;
 	struct cvmx_l2c_cfg_s                 cn56xxp1;
-	struct cvmx_l2c_cfg_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_cfg_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t bstrun                       : 1;  /**< L2 Data Store Bist Running
                                                          Indicates when the L2C HW Bist sequence(short or long) is
@@ -1999,9 +2193,8 @@ union cvmx_l2c_cfg
 	uint64_t reserved_20_63               : 44;
 #endif
 	} cn58xx;
-	struct cvmx_l2c_cfg_cn58xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_cfg_cn58xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_15_63               : 49;
 	uint64_t dfill_dis                    : 1;  /**< L2C Dual Fill Disable
                                                          When set, the L2C dual-fill performance feature is
@@ -2101,7 +2294,7 @@ typedef union cvmx_l2c_cfg cvmx_l2c_cfg_t;
  *
  * Description: PP COP0 register mapped region.
  *
- * NOTE: for 63xx, if the PPID is outside the range of 0-5,63 the write will be ignored and reads
+ * NOTE: for 63xx, if the PPID is outside the range of 0-3,63 the write will be ignored and reads
  * will return 0x2bad2bad2bad2bad
  *
  * Notes:
@@ -2118,7 +2311,7 @@ typedef union cvmx_l2c_cfg cvmx_l2c_cfg_t;
  * (2) if a COP0 register cannot be accessed by this mechanism the write be silently ignored and the
  *     read data will be 0xBADDEED.
  *
- * (3) for 63xx, if the PPID is outside the range of 0-5,63 or if the PP in question is in reset a
+ * (3) for 61xx, if the PPID is outside the range of 0-3,63 or if the PP in question is in reset a
  *     write will be ignored and reads will timeout the RSL bus.
  *
  * (4) Referring to note (1) above, the following rd/sel values are supported:
@@ -2149,6 +2342,7 @@ typedef union cvmx_l2c_cfg cvmx_l2c_cfg_t;
  *       18      0       RO          COP0 WatchLo0                                 RW
  *       19      0       RO          COP0 WatchHi0                                 RW
  *       22      0       RO          COP0 MultiCoreDebug                           RW
+ *       22      1                   COP0 VoltageMonitor                           RW
  *       23      0       RO          COP0 Debug                                    RW
  *       23      6       RO          COP0 Debug2                                   RO
  *       24      0       RO          COP0 DEPC                                     RW
@@ -2196,20 +2390,23 @@ typedef union cvmx_l2c_cfg cvmx_l2c_cfg_t;
  *          1 waiting_for_pfill_4a // when waiting_for_ifill_4a is set, indicates whether instruction cache fill is due to a prefetch
  *          0 waiting_for_ifill_4a // set when there is an outstanding instruction cache fill
  */
-union cvmx_l2c_cop0_mapx
-{
+union cvmx_l2c_cop0_mapx {
 	uint64_t u64;
-	struct cvmx_l2c_cop0_mapx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_cop0_mapx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 64; /**< Data to write to/read from designated PP's COP0
                                                          register. */
 #else
 	uint64_t data                         : 64;
 #endif
 	} s;
+	struct cvmx_l2c_cop0_mapx_s           cn61xx;
 	struct cvmx_l2c_cop0_mapx_s           cn63xx;
 	struct cvmx_l2c_cop0_mapx_s           cn63xxp1;
+	struct cvmx_l2c_cop0_mapx_s           cn66xx;
+	struct cvmx_l2c_cop0_mapx_s           cn68xx;
+	struct cvmx_l2c_cop0_mapx_s           cn68xxp1;
+	struct cvmx_l2c_cop0_mapx_s           cnf71xx;
 };
 typedef union cvmx_l2c_cop0_mapx cvmx_l2c_cop0_mapx_t;
 
@@ -2236,12 +2433,150 @@ typedef union cvmx_l2c_cop0_mapx cvmx_l2c_cop0_mapx_t;
  *     without the error must change the block to dirty.  Then, a subsequent WBL2/WBIL2/victim will
  *     trigger the VBFSBE/VBFDBE error.
  */
-union cvmx_l2c_ctl
-{
+union cvmx_l2c_ctl {
 	uint64_t u64;
-	struct cvmx_l2c_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_30_63               : 34;
+	uint64_t sepcmt                       : 1;  /**< Sends all invals before the corresponding commit. */
+	uint64_t rdf_fast                     : 1;  /**< When 0, delay read data fifo from DCLK to RCLK by one
+                                                         cycle.  Needed when DCLK:RCLK ratio > 3:1.  Should be
+                                                         set before DDR traffic begins and only changed when
+                                                         memory traffic is idle. */
+	uint64_t disstgl2i                    : 1;  /**< Disable STGL2I's from changing the tags */
+	uint64_t l2dfsbe                      : 1;  /**< Force single bit ECC error on PL2 allocates (2) */
+	uint64_t l2dfdbe                      : 1;  /**< Force double bit ECC error on PL2 allocates (2) */
+	uint64_t discclk                      : 1;  /**< Disable conditional clocking in L2C PNR blocks */
+	uint64_t maxvab                       : 4;  /**< Maximum VABs in use at once
+                                                         (0 means 16, 1-15 as expected) */
+	uint64_t maxlfb                       : 4;  /**< Maximum LFBs in use at once
+                                                         (0 means 16, 1-15 as expected) */
+	uint64_t rsp_arb_mode                 : 1;  /**< Arbitration mode for RSC/RSD bus
+                                                         == 0, round-robin
+                                                         == 1, static priority
+                                                             1. IOR data
+                                                             2. STIN/FILLs
+                                                             3. STDN/SCDN/SCFL */
+	uint64_t xmc_arb_mode                 : 1;  /**< Arbitration mode for XMC QOS queues
+                                                         == 0, fully determined through QOS
+                                                         == 1, QOS0 highest priority, QOS1-3 use normal mode */
+	uint64_t ef_ena                       : 1;  /**< LMC early fill enable */
+	uint64_t ef_cnt                       : 7;  /**< LMC early fill count
+                                                         Specifies the number of cycles after the first LMC
+                                                         fill cycle to wait before requesting a fill on the
+                                                         RSC/RSD bus.
+                                                           // 7 dclks (we've received 1st out of 8
+                                                           // by the time we start counting)
+                                                           ef_cnt = ((LMCn_CONFIG[MODE32b] ? 14 : 7) *
+                                                                     dclk0_period) / rclk_period;
+                                                           // + 1 rclk if the dclk and rclk edges don't
+                                                           // stay in the same position
+                                                           if ((dclk0_gen.period % rclk_gen.period) != 0)
+                                                              ef_cnt = ef_cnt + 1;
+                                                           // + 2 rclk synchronization uncertainty
+                                                           ef_cnt = ef_cnt + 2;
+                                                           // - 3 rclks to recognize first write
+                                                           ef_cnt = ef_cnt - 3;
+                                                           // + 3 rclks to perform first write
+                                                           ef_cnt = ef_cnt + 3;
+                                                           // - 9 rclks minimum latency from counter expire
+                                                           // to final fbf read
+                                                           ef_cnt = ef_cnt - 9; */
+	uint64_t vab_thresh                   : 4;  /**< VAB Threshold
+                                                         When the number of valid VABs exceeds this number the
+                                                         L2C increases the priority of all writes in the LMC. */
+	uint64_t disecc                       : 1;  /**< Tag and Data ECC Disable */
+	uint64_t disidxalias                  : 1;  /**< Index Alias Disable */
+#else
+	uint64_t disidxalias                  : 1;
+	uint64_t disecc                       : 1;
+	uint64_t vab_thresh                   : 4;
+	uint64_t ef_cnt                       : 7;
+	uint64_t ef_ena                       : 1;
+	uint64_t xmc_arb_mode                 : 1;
+	uint64_t rsp_arb_mode                 : 1;
+	uint64_t maxlfb                       : 4;
+	uint64_t maxvab                       : 4;
+	uint64_t discclk                      : 1;
+	uint64_t l2dfdbe                      : 1;
+	uint64_t l2dfsbe                      : 1;
+	uint64_t disstgl2i                    : 1;
+	uint64_t rdf_fast                     : 1;
+	uint64_t sepcmt                       : 1;
+	uint64_t reserved_30_63               : 34;
+#endif
+	} s;
+	struct cvmx_l2c_ctl_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_29_63               : 35;
+	uint64_t rdf_fast                     : 1;  /**< When 0, delay read data fifo from DCLK to RCLK by one
+                                                         cycle.  Needed when DCLK:RCLK ratio > 3:1.  Should be
+                                                         set before DDR traffic begins and only changed when
+                                                         memory traffic is idle. */
+	uint64_t disstgl2i                    : 1;  /**< Disable STGL2I's from changing the tags */
+	uint64_t l2dfsbe                      : 1;  /**< Force single bit ECC error on PL2 allocates (2) */
+	uint64_t l2dfdbe                      : 1;  /**< Force double bit ECC error on PL2 allocates (2) */
+	uint64_t discclk                      : 1;  /**< Disable conditional clocking in L2C PNR blocks */
+	uint64_t maxvab                       : 4;  /**< Maximum VABs in use at once
+                                                         (0 means 16, 1-15 as expected) */
+	uint64_t maxlfb                       : 4;  /**< Maximum LFBs in use at once
+                                                         (0 means 16, 1-15 as expected) */
+	uint64_t rsp_arb_mode                 : 1;  /**< Arbitration mode for RSC/RSD bus
+                                                         == 0, round-robin
+                                                         == 1, static priority
+                                                             1. IOR data
+                                                             2. STIN/FILLs
+                                                             3. STDN/SCDN/SCFL */
+	uint64_t xmc_arb_mode                 : 1;  /**< Arbitration mode for XMC QOS queues
+                                                         == 0, fully determined through QOS
+                                                         == 1, QOS0 highest priority, QOS1-3 use normal mode */
+	uint64_t ef_ena                       : 1;  /**< LMC early fill enable */
+	uint64_t ef_cnt                       : 7;  /**< LMC early fill count
+                                                         Specifies the number of cycles after the first LMC
+                                                         fill cycle to wait before requesting a fill on the
+                                                         RSC/RSD bus.
+                                                           // 7 dclks (we've received 1st out of 8
+                                                           // by the time we start counting)
+                                                           ef_cnt = ((LMCn_CONFIG[MODE32b] ? 14 : 7) *
+                                                                     dclk0_period) / rclk_period;
+                                                           // + 1 rclk if the dclk and rclk edges don't
+                                                           // stay in the same position
+                                                           if ((dclk0_gen.period % rclk_gen.period) != 0)
+                                                              ef_cnt = ef_cnt + 1;
+                                                           // + 2 rclk synchronization uncertainty
+                                                           ef_cnt = ef_cnt + 2;
+                                                           // - 3 rclks to recognize first write
+                                                           ef_cnt = ef_cnt - 3;
+                                                           // + 3 rclks to perform first write
+                                                           ef_cnt = ef_cnt + 3;
+                                                           // - 9 rclks minimum latency from counter expire
+                                                           // to final fbf read
+                                                           ef_cnt = ef_cnt - 9; */
+	uint64_t vab_thresh                   : 4;  /**< VAB Threshold
+                                                         When the number of valid VABs exceeds this number the
+                                                         L2C increases the priority of all writes in the LMC. */
+	uint64_t disecc                       : 1;  /**< Tag and Data ECC Disable */
+	uint64_t disidxalias                  : 1;  /**< Index Alias Disable */
+#else
+	uint64_t disidxalias                  : 1;
+	uint64_t disecc                       : 1;
+	uint64_t vab_thresh                   : 4;
+	uint64_t ef_cnt                       : 7;
+	uint64_t ef_ena                       : 1;
+	uint64_t xmc_arb_mode                 : 1;
+	uint64_t rsp_arb_mode                 : 1;
+	uint64_t maxlfb                       : 4;
+	uint64_t maxvab                       : 4;
+	uint64_t discclk                      : 1;
+	uint64_t l2dfdbe                      : 1;
+	uint64_t l2dfsbe                      : 1;
+	uint64_t disstgl2i                    : 1;
+	uint64_t rdf_fast                     : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn61xx;
+	struct cvmx_l2c_ctl_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t disstgl2i                    : 1;  /**< Disable STGL2I's from changing the tags */
 	uint64_t l2dfsbe                      : 1;  /**< Force single bit ECC error on PL2 allocates (2) */
@@ -2302,11 +2637,9 @@ union cvmx_l2c_ctl
 	uint64_t disstgl2i                    : 1;
 	uint64_t reserved_28_63               : 36;
 #endif
-	} s;
-	struct cvmx_l2c_ctl_s                 cn63xx;
-	struct cvmx_l2c_ctl_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	} cn63xx;
+	struct cvmx_l2c_ctl_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_25_63               : 39;
 	uint64_t discclk                      : 1;  /**< Disable conditional clocking in L2C PNR blocks */
 	uint64_t maxvab                       : 4;  /**< Maximum VABs in use at once
@@ -2362,6 +2695,10 @@ union cvmx_l2c_ctl
 	uint64_t reserved_25_63               : 39;
 #endif
 	} cn63xxp1;
+	struct cvmx_l2c_ctl_cn61xx            cn66xx;
+	struct cvmx_l2c_ctl_s                 cn68xx;
+	struct cvmx_l2c_ctl_cn63xx            cn68xxp1;
+	struct cvmx_l2c_ctl_cn61xx            cnf71xx;
 };
 typedef union cvmx_l2c_ctl cvmx_l2c_ctl_t;
 
@@ -2380,12 +2717,10 @@ typedef union cvmx_l2c_ctl cvmx_l2c_ctl_t;
  * (4) L2 Cache Lock Down feature MUST BE disabled (L2C_LCKBASE[LCK_ENA]=0) if ANY of the L2C debug
  *     features (L2T, L2D, FINV) are enabled.
  */
-union cvmx_l2c_dbg
-{
+union cvmx_l2c_dbg {
 	uint64_t u64;
-	struct cvmx_l2c_dbg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_15_63               : 49;
 	uint64_t lfb_enum                     : 4;  /**< Specifies the LFB Entry# which is to be captured. */
 	uint64_t lfb_dmp                      : 1;  /**< LFB Dump Enable: When written(=1), the contents of
@@ -2479,9 +2814,8 @@ union cvmx_l2c_dbg
 	uint64_t reserved_15_63               : 49;
 #endif
 	} s;
-	struct cvmx_l2c_dbg_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_dbg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t lfb_enum                     : 2;  /**< Specifies the LFB Entry# which is to be captured. */
 	uint64_t lfb_dmp                      : 1;  /**< LFB Dump Enable: When written(=1), the contents of
@@ -2576,9 +2910,8 @@ union cvmx_l2c_dbg
 	uint64_t reserved_13_63               : 51;
 #endif
 	} cn30xx;
-	struct cvmx_l2c_dbg_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_dbg_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t lfb_enum                     : 3;  /**< Specifies the LFB Entry# which is to be captured. */
 	uint64_t lfb_dmp                      : 1;  /**< LFB Dump Enable: When written(=1), the contents of
@@ -2676,9 +3009,8 @@ union cvmx_l2c_dbg
 	} cn31xx;
 	struct cvmx_l2c_dbg_s                 cn38xx;
 	struct cvmx_l2c_dbg_s                 cn38xxp2;
-	struct cvmx_l2c_dbg_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_dbg_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t lfb_enum                     : 3;  /**< Specifies the LFB Entry# which is to be captured. */
 	uint64_t lfb_dmp                      : 1;  /**< LFB Dump Enable: When written(=1), the contents of
@@ -2772,9 +3104,8 @@ union cvmx_l2c_dbg
 	uint64_t reserved_14_63               : 50;
 #endif
 	} cn50xx;
-	struct cvmx_l2c_dbg_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_dbg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t lfb_enum                     : 3;  /**< Specifies the LFB Entry# which is to be captured. */
 	uint64_t lfb_dmp                      : 1;  /**< LFB Dump Enable: When written(=1), the contents of
@@ -2891,12 +3222,10 @@ typedef union cvmx_l2c_dbg cvmx_l2c_dbg_t;
  *     dirty data to memory to maintain coherency. (A side effect of FINV is that an LDD L2 fill is
  *     launched which fills data into the L2 DS).
  */
-union cvmx_l2c_dut
-{
+union cvmx_l2c_dut {
 	uint64_t u64;
-	struct cvmx_l2c_dut_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_dut_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t dtena                        : 1;  /**< DuTag Diagnostic read enable.
                                                          When L2C_DUT[DTENA]=1, all LDD(L1 load-miss)
@@ -2964,8 +3293,8 @@ typedef union cvmx_l2c_dut cvmx_l2c_dut_t;
  *
  * This base address should be combined with PP virtual ID, L1 way and L1 set to produce the final
  * address as follows:
- *     addr<63:14>      L2C_DUT_MAP<63:14>
- *     addr<13:11>      PP VID
+ *     addr<63:13>      L2C_DUT_MAP<63:13>
+ *     addr<12:11>      PP VID
  *     addr<10:6>       L1 way
  *     addr<5:3>        L1 set
  *     addr<2:0>        UNUSED
@@ -2974,12 +3303,10 @@ typedef union cvmx_l2c_dut cvmx_l2c_dut_t;
  * (1) The tag is 37:10 from the 38-bit OCTEON physical address after hole removal. (The hole is between DR0
  * and DR1. Remove the hole by subtracting 256MB from 38-bit OCTEON L2/DRAM physical addresses >= 512 MB.)
  */
-union cvmx_l2c_dut_mapx
-{
+union cvmx_l2c_dut_mapx {
 	uint64_t u64;
-	struct cvmx_l2c_dut_mapx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_dut_mapx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_38_63               : 26;
 	uint64_t tag                          : 28; /**< The tag value (see Note 1) */
 	uint64_t reserved_1_9                 : 9;
@@ -2991,8 +3318,13 @@ union cvmx_l2c_dut_mapx
 	uint64_t reserved_38_63               : 26;
 #endif
 	} s;
+	struct cvmx_l2c_dut_mapx_s            cn61xx;
 	struct cvmx_l2c_dut_mapx_s            cn63xx;
 	struct cvmx_l2c_dut_mapx_s            cn63xxp1;
+	struct cvmx_l2c_dut_mapx_s            cn66xx;
+	struct cvmx_l2c_dut_mapx_s            cn68xx;
+	struct cvmx_l2c_dut_mapx_s            cn68xxp1;
+	struct cvmx_l2c_dut_mapx_s            cnf71xx;
 };
 typedef union cvmx_l2c_dut_mapx cvmx_l2c_dut_mapx_t;
 
@@ -3019,12 +3351,64 @@ typedef union cvmx_l2c_dut_mapx cvmx_l2c_dut_mapx_t;
  *
  * (4) The syndrome is recorded for DBE errors, though the utility of the value is not clear.
  */
-union cvmx_l2c_err_tdtx
-{
+union cvmx_l2c_err_tdtx {
 	uint64_t u64;
-	struct cvmx_l2c_err_tdtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_err_tdtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t dbe                          : 1;  /**< L2D Double-Bit error has occurred */
+	uint64_t sbe                          : 1;  /**< L2D Single-Bit error has occurred */
+	uint64_t vdbe                         : 1;  /**< VBF Double-Bit error has occurred */
+	uint64_t vsbe                         : 1;  /**< VBF Single-Bit error has occurred */
+	uint64_t syn                          : 10; /**< L2D syndrome (valid only for SBE/DBE, not VSBE/VDBE) */
+	uint64_t reserved_22_49               : 28;
+	uint64_t wayidx                       : 18; /**< Way, index, OW of the L2 block containing the error */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t type                         : 2;  /**< The type of error the WAYIDX,SYN were latched for.
+                                                         0 - VSBE
+                                                         1 - VDBE
+                                                         2 - SBE
+                                                         3 - DBE */
+#else
+	uint64_t type                         : 2;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t wayidx                       : 18;
+	uint64_t reserved_22_49               : 28;
+	uint64_t syn                          : 10;
+	uint64_t vsbe                         : 1;
+	uint64_t vdbe                         : 1;
+	uint64_t sbe                          : 1;
+	uint64_t dbe                          : 1;
+#endif
+	} s;
+	struct cvmx_l2c_err_tdtx_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t dbe                          : 1;  /**< L2D Double-Bit error has occurred */
+	uint64_t sbe                          : 1;  /**< L2D Single-Bit error has occurred */
+	uint64_t vdbe                         : 1;  /**< VBF Double-Bit error has occurred */
+	uint64_t vsbe                         : 1;  /**< VBF Single-Bit error has occurred */
+	uint64_t syn                          : 10; /**< L2D syndrome (valid only for SBE/DBE, not VSBE/VDBE) */
+	uint64_t reserved_20_49               : 30;
+	uint64_t wayidx                       : 16; /**< Way, index, OW of the L2 block containing the error */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t type                         : 2;  /**< The type of error the WAYIDX,SYN were latched for.
+                                                         0 - VSBE
+                                                         1 - VDBE
+                                                         2 - SBE
+                                                         3 - DBE */
+#else
+	uint64_t type                         : 2;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t wayidx                       : 16;
+	uint64_t reserved_20_49               : 30;
+	uint64_t syn                          : 10;
+	uint64_t vsbe                         : 1;
+	uint64_t vdbe                         : 1;
+	uint64_t sbe                          : 1;
+	uint64_t dbe                          : 1;
+#endif
+	} cn61xx;
+	struct cvmx_l2c_err_tdtx_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t dbe                          : 1;  /**< L2D Double-Bit error has occurred */
 	uint64_t sbe                          : 1;  /**< L2D Single-Bit error has occurred */
 	uint64_t vdbe                         : 1;  /**< VBF Double-Bit error has occurred */
@@ -3049,9 +3433,12 @@ union cvmx_l2c_err_tdtx
 	uint64_t sbe                          : 1;
 	uint64_t dbe                          : 1;
 #endif
-	} s;
-	struct cvmx_l2c_err_tdtx_s            cn63xx;
-	struct cvmx_l2c_err_tdtx_s            cn63xxp1;
+	} cn63xx;
+	struct cvmx_l2c_err_tdtx_cn63xx       cn63xxp1;
+	struct cvmx_l2c_err_tdtx_cn63xx       cn66xx;
+	struct cvmx_l2c_err_tdtx_s            cn68xx;
+	struct cvmx_l2c_err_tdtx_s            cn68xxp1;
+	struct cvmx_l2c_err_tdtx_cn61xx       cnf71xx;
 };
 typedef union cvmx_l2c_err_tdtx cvmx_l2c_err_tdtx_t;
 
@@ -3077,12 +3464,90 @@ typedef union cvmx_l2c_err_tdtx cvmx_l2c_err_tdtx_t;
  *     priority, SBE error occuring.  If the SBE arrives prior to the DBE clear the WAYIDX/SYN fields
  *     will still be locked, but the new SBE error status bit will still be set.
  */
-union cvmx_l2c_err_ttgx
-{
+union cvmx_l2c_err_ttgx {
 	uint64_t u64;
-	struct cvmx_l2c_err_ttgx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_err_ttgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t dbe                          : 1;  /**< Double-Bit ECC error */
+	uint64_t sbe                          : 1;  /**< Single-Bit ECC error */
+	uint64_t noway                        : 1;  /**< No way was available for allocation.
+                                                         L2C sets NOWAY during its processing of a
+                                                         transaction whenever it needed/wanted to allocate
+                                                         a WAY in the L2 cache, but was unable to. NOWAY==1
+                                                         is (generally) not an indication that L2C failed to
+                                                         complete transactions. Rather, it is a hint of
+                                                         possible performance degradation. (For example, L2C
+                                                         must read-modify-write DRAM for every transaction
+                                                         that updates some, but not all, of the bytes in a
+                                                         cache block, misses in the L2 cache, and cannot
+                                                         allocate a WAY.) There is one "failure" case where
+                                                         L2C will set NOWAY: when it cannot leave a block
+                                                         locked in the L2 cache as part of a LCKL2
+                                                         transaction. */
+	uint64_t reserved_56_60               : 5;
+	uint64_t syn                          : 6;  /**< Syndrome for the single-bit error */
+	uint64_t reserved_22_49               : 28;
+	uint64_t wayidx                       : 15; /**< Way and index of the L2 block containing the error */
+	uint64_t reserved_2_6                 : 5;
+	uint64_t type                         : 2;  /**< The type of error the WAYIDX,SYN were latched for.
+                                                         0 - not valid
+                                                         1 - NOWAY
+                                                         2 - SBE
+                                                         3 - DBE */
+#else
+	uint64_t type                         : 2;
+	uint64_t reserved_2_6                 : 5;
+	uint64_t wayidx                       : 15;
+	uint64_t reserved_22_49               : 28;
+	uint64_t syn                          : 6;
+	uint64_t reserved_56_60               : 5;
+	uint64_t noway                        : 1;
+	uint64_t sbe                          : 1;
+	uint64_t dbe                          : 1;
+#endif
+	} s;
+	struct cvmx_l2c_err_ttgx_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t dbe                          : 1;  /**< Double-Bit ECC error */
+	uint64_t sbe                          : 1;  /**< Single-Bit ECC error */
+	uint64_t noway                        : 1;  /**< No way was available for allocation.
+                                                         L2C sets NOWAY during its processing of a
+                                                         transaction whenever it needed/wanted to allocate
+                                                         a WAY in the L2 cache, but was unable to. NOWAY==1
+                                                         is (generally) not an indication that L2C failed to
+                                                         complete transactions. Rather, it is a hint of
+                                                         possible performance degradation. (For example, L2C
+                                                         must read-modify-write DRAM for every transaction
+                                                         that updates some, but not all, of the bytes in a
+                                                         cache block, misses in the L2 cache, and cannot
+                                                         allocate a WAY.) There is one "failure" case where
+                                                         L2C will set NOWAY: when it cannot leave a block
+                                                         locked in the L2 cache as part of a LCKL2
+                                                         transaction. */
+	uint64_t reserved_56_60               : 5;
+	uint64_t syn                          : 6;  /**< Syndrome for the single-bit error */
+	uint64_t reserved_20_49               : 30;
+	uint64_t wayidx                       : 13; /**< Way and index of the L2 block containing the error */
+	uint64_t reserved_2_6                 : 5;
+	uint64_t type                         : 2;  /**< The type of error the WAYIDX,SYN were latched for.
+                                                         0 - not valid
+                                                         1 - NOWAY
+                                                         2 - SBE
+                                                         3 - DBE */
+#else
+	uint64_t type                         : 2;
+	uint64_t reserved_2_6                 : 5;
+	uint64_t wayidx                       : 13;
+	uint64_t reserved_20_49               : 30;
+	uint64_t syn                          : 6;
+	uint64_t reserved_56_60               : 5;
+	uint64_t noway                        : 1;
+	uint64_t sbe                          : 1;
+	uint64_t dbe                          : 1;
+#endif
+	} cn61xx;
+	struct cvmx_l2c_err_ttgx_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t dbe                          : 1;  /**< Double-Bit ECC error */
 	uint64_t sbe                          : 1;  /**< Single-Bit ECC error */
 	uint64_t noway                        : 1;  /**< No way was available for allocation.
@@ -3120,9 +3585,12 @@ union cvmx_l2c_err_ttgx
 	uint64_t sbe                          : 1;
 	uint64_t dbe                          : 1;
 #endif
-	} s;
-	struct cvmx_l2c_err_ttgx_s            cn63xx;
-	struct cvmx_l2c_err_ttgx_s            cn63xxp1;
+	} cn63xx;
+	struct cvmx_l2c_err_ttgx_cn63xx       cn63xxp1;
+	struct cvmx_l2c_err_ttgx_cn63xx       cn66xx;
+	struct cvmx_l2c_err_ttgx_s            cn68xx;
+	struct cvmx_l2c_err_ttgx_s            cn68xxp1;
+	struct cvmx_l2c_err_ttgx_cn61xx       cnf71xx;
 };
 typedef union cvmx_l2c_err_ttgx cvmx_l2c_err_ttgx_t;
 
@@ -3149,12 +3617,10 @@ typedef union cvmx_l2c_err_ttgx cvmx_l2c_err_ttgx_t;
  *     VSBE error occuring.  If the VSBE arrives prior to the VDBE clear the SYN field will still be
  *     locked, but the new VSBE error status bit will still be set.
  */
-union cvmx_l2c_err_vbfx
-{
+union cvmx_l2c_err_vbfx {
 	uint64_t u64;
-	struct cvmx_l2c_err_vbfx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_err_vbfx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_62_63               : 2;
 	uint64_t vdbe                         : 1;  /**< VBF Double-Bit error has occurred */
 	uint64_t vsbe                         : 1;  /**< VBF Single-Bit error has occurred */
@@ -3172,8 +3638,13 @@ union cvmx_l2c_err_vbfx
 	uint64_t reserved_62_63               : 2;
 #endif
 	} s;
+	struct cvmx_l2c_err_vbfx_s            cn61xx;
 	struct cvmx_l2c_err_vbfx_s            cn63xx;
 	struct cvmx_l2c_err_vbfx_s            cn63xxp1;
+	struct cvmx_l2c_err_vbfx_s            cn66xx;
+	struct cvmx_l2c_err_vbfx_s            cn68xx;
+	struct cvmx_l2c_err_vbfx_s            cn68xxp1;
+	struct cvmx_l2c_err_vbfx_s            cnf71xx;
 };
 typedef union cvmx_l2c_err_vbfx cvmx_l2c_err_vbfx_t;
 
@@ -3196,12 +3667,25 @@ typedef union cvmx_l2c_err_vbfx cvmx_l2c_err_vbfx_t;
  *
  * (4) For 63xx pass 2.0 and all 68xx ADDR<15:0> will ALWAYS be zero.
  */
-union cvmx_l2c_err_xmc
-{
+union cvmx_l2c_err_xmc {
 	uint64_t u64;
-	struct cvmx_l2c_err_xmc_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_err_xmc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t cmd                          : 6;  /**< XMC command or request causing error */
+	uint64_t reserved_54_57               : 4;
+	uint64_t sid                          : 6;  /**< XMC sid of request causing error */
+	uint64_t reserved_38_47               : 10;
+	uint64_t addr                         : 38; /**< XMC address causing the error (see Notes 2 and 3) */
+#else
+	uint64_t addr                         : 38;
+	uint64_t reserved_38_47               : 10;
+	uint64_t sid                          : 6;
+	uint64_t reserved_54_57               : 4;
+	uint64_t cmd                          : 6;
+#endif
+	} s;
+	struct cvmx_l2c_err_xmc_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t cmd                          : 6;  /**< XMC command or request causing error */
 	uint64_t reserved_52_57               : 6;
 	uint64_t sid                          : 4;  /**< XMC sid of request causing error */
@@ -3214,9 +3698,27 @@ union cvmx_l2c_err_xmc
 	uint64_t reserved_52_57               : 6;
 	uint64_t cmd                          : 6;
 #endif
-	} s;
-	struct cvmx_l2c_err_xmc_s             cn63xx;
-	struct cvmx_l2c_err_xmc_s             cn63xxp1;
+	} cn61xx;
+	struct cvmx_l2c_err_xmc_cn61xx        cn63xx;
+	struct cvmx_l2c_err_xmc_cn61xx        cn63xxp1;
+	struct cvmx_l2c_err_xmc_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t cmd                          : 6;  /**< XMC command or request causing error */
+	uint64_t reserved_53_57               : 5;
+	uint64_t sid                          : 5;  /**< XMC sid of request causing error */
+	uint64_t reserved_38_47               : 10;
+	uint64_t addr                         : 38; /**< XMC address causing the error (see Notes 2 and 3) */
+#else
+	uint64_t addr                         : 38;
+	uint64_t reserved_38_47               : 10;
+	uint64_t sid                          : 5;
+	uint64_t reserved_53_57               : 5;
+	uint64_t cmd                          : 6;
+#endif
+	} cn66xx;
+	struct cvmx_l2c_err_xmc_s             cn68xx;
+	struct cvmx_l2c_err_xmc_s             cn68xxp1;
+	struct cvmx_l2c_err_xmc_cn61xx        cnf71xx;
 };
 typedef union cvmx_l2c_err_xmc cvmx_l2c_err_xmc_t;
 
@@ -3231,12 +3733,10 @@ typedef union cvmx_l2c_err_xmc cvmx_l2c_err_xmc_t;
  * - Starvation of a group 'could' occur, unless SW takes the precaution to ensure that each GROUP
  * participates in at least 1(of 32) rounds (ie: At least 1 bit(of 32) should be clear).
  */
-union cvmx_l2c_grpwrr0
-{
+union cvmx_l2c_grpwrr0 {
 	uint64_t u64;
-	struct cvmx_l2c_grpwrr0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_grpwrr0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t plc1rmsk                     : 32; /**< PLC1 Group#1 Weighted Round Mask
                                                          Each bit represents 1 of 32 rounds
                                                          for Group \#1's participation. When a 'round' bit is
@@ -3272,12 +3772,10 @@ typedef union cvmx_l2c_grpwrr0 cvmx_l2c_grpwrr0_t;
  * - Starvation of a group 'could' occur, unless SW takes the precaution to ensure that each GROUP
  * participates in at least 1(of 32) rounds (ie: At least 1 bit(of 32) should be clear).
  */
-union cvmx_l2c_grpwrr1
-{
+union cvmx_l2c_grpwrr1 {
 	uint64_t u64;
-	struct cvmx_l2c_grpwrr1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_grpwrr1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t ilcrmsk                      : 32; /**< ILC (IOB) Weighted Round Mask
                                                          Each bit represents 1 of 32 rounds
                                                          for IOB participation. When a 'round' bit is
@@ -3309,12 +3807,10 @@ typedef union cvmx_l2c_grpwrr1 cvmx_l2c_grpwrr1_t;
  *
  * Description:
  */
-union cvmx_l2c_int_en
-{
+union cvmx_l2c_int_en {
 	uint64_t u64;
-	struct cvmx_l2c_int_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t lck2ena                      : 1;  /**< L2 Tag Lock Error2 Interrupt Enable bit
                                                          NOTE: This is the 'same' bit as L2T_ERR[LCK_INTENA2] */
@@ -3364,12 +3860,10 @@ typedef union cvmx_l2c_int_en cvmx_l2c_int_en_t;
  * L2C_INT_ENA = L2C Interrupt Enable
  *
  */
-union cvmx_l2c_int_ena
-{
+union cvmx_l2c_int_ena {
 	uint64_t u64;
-	struct cvmx_l2c_int_ena_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_int_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t bigrd                        : 1;  /**< Read reference past MAXDRAM enable */
 	uint64_t bigwr                        : 1;  /**< Write reference past MAXDRAM enable */
@@ -3391,10 +3885,10 @@ union cvmx_l2c_int_ena
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
+	struct cvmx_l2c_int_ena_s             cn61xx;
 	struct cvmx_l2c_int_ena_s             cn63xx;
-	struct cvmx_l2c_int_ena_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_int_ena_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t vrtpe                        : 1;  /**< Virtualization memory parity error */
 	uint64_t vrtadrng                     : 1;  /**< Address outside of virtualization range enable */
@@ -3412,6 +3906,10 @@ union cvmx_l2c_int_ena
 	uint64_t reserved_6_63                : 58;
 #endif
 	} cn63xxp1;
+	struct cvmx_l2c_int_ena_s             cn66xx;
+	struct cvmx_l2c_int_ena_s             cn68xx;
+	struct cvmx_l2c_int_ena_s             cn68xxp1;
+	struct cvmx_l2c_int_ena_s             cnf71xx;
 };
 typedef union cvmx_l2c_int_ena cvmx_l2c_int_ena_t;
 
@@ -3421,15 +3919,59 @@ typedef union cvmx_l2c_int_ena cvmx_l2c_int_ena_t;
  * L2C_INT_REG = L2C Interrupt Register
  *
  */
-union cvmx_l2c_int_reg
-{
+union cvmx_l2c_int_reg {
 	uint64_t u64;
-	struct cvmx_l2c_int_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t tad3                         : 1;  /**< When set, the enabled interrupt is in
+                                                         the L2C_TAD3_INT CSR */
+	uint64_t tad2                         : 1;  /**< When set, the enabled interrupt is in
+                                                         the L2C_TAD2_INT CSR */
+	uint64_t tad1                         : 1;  /**< When set, the enabled interrupt is in
+                                                         the L2C_TAD1_INT CSR */
+	uint64_t tad0                         : 1;  /**< When set, the enabled interrupt is in
+                                                         the L2C_TAD0_INT CSR */
+	uint64_t reserved_8_15                : 8;
+	uint64_t bigrd                        : 1;  /**< Read reference past L2C_BIG_CTL[MAXDRAM] occurred */
+	uint64_t bigwr                        : 1;  /**< Write reference past L2C_BIG_CTL[MAXDRAM] occurred */
+	uint64_t vrtpe                        : 1;  /**< L2C_VRT_MEM read found a parity error
+                                                         Whenever an L2C_VRT_MEM read finds a parity error,
+                                                         that L2C_VRT_MEM cannot cause stores to be blocked.
+                                                         Software should correct the error. */
+	uint64_t vrtadrng                     : 1;  /**< Address outside of virtualization range
+                                                         Set when a L2C_VRT_CTL[MEMSZ] violation blocked a
+                                                         store.
+                                                         L2C_VRT_CTL[OOBERR] must be set for L2C to set this. */
+	uint64_t vrtidrng                     : 1;  /**< Virtualization ID out of range
+                                                         Set when a L2C_VRT_CTL[NUMID] violation blocked a
+                                                         store. */
+	uint64_t vrtwr                        : 1;  /**< Virtualization ID prevented a write
+                                                         Set when L2C_VRT_MEM blocked a store. */
+	uint64_t holewr                       : 1;  /**< Write reference to 256MB hole occurred */
+	uint64_t holerd                       : 1;  /**< Read reference to 256MB hole occurred */
+#else
+	uint64_t holerd                       : 1;
+	uint64_t holewr                       : 1;
+	uint64_t vrtwr                        : 1;
+	uint64_t vrtidrng                     : 1;
+	uint64_t vrtadrng                     : 1;
+	uint64_t vrtpe                        : 1;
+	uint64_t bigwr                        : 1;
+	uint64_t bigrd                        : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t tad0                         : 1;
+	uint64_t tad1                         : 1;
+	uint64_t tad2                         : 1;
+	uint64_t tad3                         : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_l2c_int_reg_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
-	uint64_t tad0                         : 1;  /**< When set, the enabled interrupt is in either
-                                                         the L2C_ERR_TDT0 or L2C_ERR_TTG0 CSR */
+	uint64_t tad0                         : 1;  /**< When set, the enabled interrupt is in
+                                                         the L2C_TAD0_INT CSR */
 	uint64_t reserved_8_15                : 8;
 	uint64_t bigrd                        : 1;  /**< Read reference past L2C_BIG_CTL[MAXDRAM] occurred */
 	uint64_t bigwr                        : 1;  /**< Write reference past L2C_BIG_CTL[MAXDRAM] occurred */
@@ -3461,11 +4003,10 @@ union cvmx_l2c_int_reg
 	uint64_t tad0                         : 1;
 	uint64_t reserved_17_63               : 47;
 #endif
-	} s;
-	struct cvmx_l2c_int_reg_s             cn63xx;
-	struct cvmx_l2c_int_reg_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	} cn61xx;
+	struct cvmx_l2c_int_reg_cn61xx        cn63xx;
+	struct cvmx_l2c_int_reg_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t tad0                         : 1;  /**< When set, the enabled interrupt is in either
                                                          the L2C_ERR_TDT0 or L2C_ERR_TTG0 CSR */
@@ -3497,6 +4038,10 @@ union cvmx_l2c_int_reg
 	uint64_t reserved_17_63               : 47;
 #endif
 	} cn63xxp1;
+	struct cvmx_l2c_int_reg_cn61xx        cn66xx;
+	struct cvmx_l2c_int_reg_s             cn68xx;
+	struct cvmx_l2c_int_reg_s             cn68xxp1;
+	struct cvmx_l2c_int_reg_cn61xx        cnf71xx;
 };
 typedef union cvmx_l2c_int_reg cvmx_l2c_int_reg_t;
 
@@ -3507,12 +4052,10 @@ typedef union cvmx_l2c_int_reg cvmx_l2c_int_reg_t;
  *
  * Description:
  */
-union cvmx_l2c_int_stat
-{
+union cvmx_l2c_int_stat {
 	uint64_t u64;
-	struct cvmx_l2c_int_stat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_int_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t lck2                         : 1;  /**< HW detected a case where a Rd/Wr Miss from PP#n
                                                          could not find an available/unlocked set (for
@@ -3585,19 +4128,22 @@ typedef union cvmx_l2c_int_stat cvmx_l2c_int_stat_t;
  * L2C_IOC_PFC = L2C IOC Performance Counter(s)
  *
  */
-union cvmx_l2c_iocx_pfc
-{
+union cvmx_l2c_iocx_pfc {
 	uint64_t u64;
-	struct cvmx_l2c_iocx_pfc_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_iocx_pfc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t count                        : 64; /**< Current counter value */
 #else
 	uint64_t count                        : 64;
 #endif
 	} s;
+	struct cvmx_l2c_iocx_pfc_s            cn61xx;
 	struct cvmx_l2c_iocx_pfc_s            cn63xx;
 	struct cvmx_l2c_iocx_pfc_s            cn63xxp1;
+	struct cvmx_l2c_iocx_pfc_s            cn66xx;
+	struct cvmx_l2c_iocx_pfc_s            cn68xx;
+	struct cvmx_l2c_iocx_pfc_s            cn68xxp1;
+	struct cvmx_l2c_iocx_pfc_s            cnf71xx;
 };
 typedef union cvmx_l2c_iocx_pfc cvmx_l2c_iocx_pfc_t;
 
@@ -3607,19 +4153,22 @@ typedef union cvmx_l2c_iocx_pfc cvmx_l2c_iocx_pfc_t;
  * L2C_IOR_PFC = L2C IOR Performance Counter(s)
  *
  */
-union cvmx_l2c_iorx_pfc
-{
+union cvmx_l2c_iorx_pfc {
 	uint64_t u64;
-	struct cvmx_l2c_iorx_pfc_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_iorx_pfc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t count                        : 64; /**< Current counter value */
 #else
 	uint64_t count                        : 64;
 #endif
 	} s;
+	struct cvmx_l2c_iorx_pfc_s            cn61xx;
 	struct cvmx_l2c_iorx_pfc_s            cn63xx;
 	struct cvmx_l2c_iorx_pfc_s            cn63xxp1;
+	struct cvmx_l2c_iorx_pfc_s            cn66xx;
+	struct cvmx_l2c_iorx_pfc_s            cn68xx;
+	struct cvmx_l2c_iorx_pfc_s            cn68xxp1;
+	struct cvmx_l2c_iorx_pfc_s            cnf71xx;
 };
 typedef union cvmx_l2c_iorx_pfc cvmx_l2c_iorx_pfc_t;
 
@@ -3640,12 +4189,10 @@ typedef union cvmx_l2c_iorx_pfc cvmx_l2c_iorx_pfc_t;
  * (3) To 'unlock' a locked cache line, SW can use the FLUSH-INVAL CSR mechanism (see L2C_DBG[FINV]).
  * (4) LCK_ENA MUST only be activated when debug modes are disabled (L2C_DBG[L2T], L2C_DBG[L2D], L2C_DBG[FINV]).
  */
-union cvmx_l2c_lckbase
-{
+union cvmx_l2c_lckbase {
 	uint64_t u64;
-	struct cvmx_l2c_lckbase_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_lckbase_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t lck_base                     : 27; /**< Base Memory block address[33:7]. Specifies the
                                                          starting address of the lockdown region. */
@@ -3717,12 +4264,10 @@ typedef union cvmx_l2c_lckbase cvmx_l2c_lckbase_t;
  * (1) The generation of the end lockdown block address will 'wrap'.
  * (2) The minimum granularity for lockdown is 1 cache line (= 128B block)
  */
-union cvmx_l2c_lckoff
-{
+union cvmx_l2c_lckoff {
 	uint64_t u64;
-	struct cvmx_l2c_lckoff_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_lckoff_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t lck_offset                   : 10; /**< LockDown block Offset. Used in determining
                                                          the ending block address of the lockdown
@@ -3755,12 +4300,10 @@ typedef union cvmx_l2c_lckoff cvmx_l2c_lckoff_t;
  *
  * Description: L2C LFB Contents (Status Bits)
  */
-union cvmx_l2c_lfb0
-{
+union cvmx_l2c_lfb0 {
 	uint64_t u64;
-	struct cvmx_l2c_lfb0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_lfb0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t stcpnd                       : 1;  /**< LFB STC Pending Status */
 	uint64_t stpnd                        : 1;  /**< LFB ST* Pending Status */
@@ -3792,9 +4335,8 @@ union cvmx_l2c_lfb0
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
-	struct cvmx_l2c_lfb0_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_lfb0_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t stcpnd                       : 1;  /**< LFB STC Pending Status */
 	uint64_t stpnd                        : 1;  /**< LFB ST* Pending Status */
@@ -3832,9 +4374,8 @@ union cvmx_l2c_lfb0
 	uint64_t reserved_32_63               : 32;
 #endif
 	} cn30xx;
-	struct cvmx_l2c_lfb0_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_lfb0_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t stcpnd                       : 1;  /**< LFB STC Pending Status */
 	uint64_t stpnd                        : 1;  /**< LFB ST* Pending Status */
@@ -3874,9 +4415,8 @@ union cvmx_l2c_lfb0
 	} cn31xx;
 	struct cvmx_l2c_lfb0_s                cn38xx;
 	struct cvmx_l2c_lfb0_s                cn38xxp2;
-	struct cvmx_l2c_lfb0_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_lfb0_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t stcpnd                       : 1;  /**< LFB STC Pending Status */
 	uint64_t stpnd                        : 1;  /**< LFB ST* Pending Status */
@@ -3928,12 +4468,10 @@ typedef union cvmx_l2c_lfb0 cvmx_l2c_lfb0_t;
  *
  * Description: L2C LFB Contents (Wait Bits)
  */
-union cvmx_l2c_lfb1
-{
+union cvmx_l2c_lfb1 {
 	uint64_t u64;
-	struct cvmx_l2c_lfb1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_lfb1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t dsgoing                      : 1;  /**< LFB DS Going (in flight) */
 	uint64_t bid                          : 2;  /**< LFB DS Bid# */
@@ -3998,20 +4536,17 @@ typedef union cvmx_l2c_lfb1 cvmx_l2c_lfb1_t;
  *
  * Description: L2C LFB Contents Tag/Index
  */
-union cvmx_l2c_lfb2
-{
+union cvmx_l2c_lfb2 {
 	uint64_t u64;
-	struct cvmx_l2c_lfb2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_lfb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_0_63                : 64;
 #else
 	uint64_t reserved_0_63                : 64;
 #endif
 	} s;
-	struct cvmx_l2c_lfb2_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_lfb2_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_27_63               : 37;
 	uint64_t lfb_tag                      : 19; /**< LFB TAG[33:15] */
 	uint64_t lfb_idx                      : 8;  /**< LFB IDX[14:7] */
@@ -4021,9 +4556,8 @@ union cvmx_l2c_lfb2
 	uint64_t reserved_27_63               : 37;
 #endif
 	} cn30xx;
-	struct cvmx_l2c_lfb2_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_lfb2_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_27_63               : 37;
 	uint64_t lfb_tag                      : 17; /**< LFB TAG[33:16] */
 	uint64_t lfb_idx                      : 10; /**< LFB IDX[15:7] */
@@ -4035,9 +4569,8 @@ union cvmx_l2c_lfb2
 	} cn31xx;
 	struct cvmx_l2c_lfb2_cn31xx           cn38xx;
 	struct cvmx_l2c_lfb2_cn31xx           cn38xxp2;
-	struct cvmx_l2c_lfb2_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_lfb2_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_27_63               : 37;
 	uint64_t lfb_tag                      : 20; /**< LFB TAG[33:14] */
 	uint64_t lfb_idx                      : 7;  /**< LFB IDX[13:7] */
@@ -4047,9 +4580,8 @@ union cvmx_l2c_lfb2
 	uint64_t reserved_27_63               : 37;
 #endif
 	} cn50xx;
-	struct cvmx_l2c_lfb2_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_lfb2_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_27_63               : 37;
 	uint64_t lfb_tag                      : 18; /**< LFB TAG[33:16] */
 	uint64_t lfb_idx                      : 9;  /**< LFB IDX[15:7] */
@@ -4060,9 +4592,8 @@ union cvmx_l2c_lfb2
 #endif
 	} cn52xx;
 	struct cvmx_l2c_lfb2_cn52xx           cn52xxp1;
-	struct cvmx_l2c_lfb2_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_lfb2_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_27_63               : 37;
 	uint64_t lfb_tag                      : 16; /**< LFB TAG[33:18] */
 	uint64_t lfb_idx                      : 11; /**< LFB IDX[17:7] */
@@ -4085,12 +4616,10 @@ typedef union cvmx_l2c_lfb2 cvmx_l2c_lfb2_t;
  *
  * Description: LFB High Water Mark Register
  */
-union cvmx_l2c_lfb3
-{
+union cvmx_l2c_lfb3 {
 	uint64_t u64;
-	struct cvmx_l2c_lfb3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_lfb3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t stpartdis                    : 1;  /**< STP/C Performance Enhancement Disable
                                                          When clear, all STP/C(store partials) will take 2 cycles
@@ -4110,9 +4639,8 @@ union cvmx_l2c_lfb3
 	uint64_t reserved_5_63                : 59;
 #endif
 	} s;
-	struct cvmx_l2c_lfb3_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_lfb3_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t stpartdis                    : 1;  /**< STP/C Performance Enhancement Disable
                                                          When clear, all STP/C(store partials) will take 2 cycles
@@ -4134,9 +4662,8 @@ union cvmx_l2c_lfb3
 	uint64_t reserved_5_63                : 59;
 #endif
 	} cn30xx;
-	struct cvmx_l2c_lfb3_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_lfb3_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t stpartdis                    : 1;  /**< STP/C Performance Enhancement Disable
                                                          When clear, all STP/C(store partials) will take 2 cycles
@@ -4177,12 +4704,10 @@ typedef union cvmx_l2c_lfb3 cvmx_l2c_lfb3_t;
  *
  * Description: Defines DMA "Out of Bounds" global enables.
  */
-union cvmx_l2c_oob
-{
+union cvmx_l2c_oob {
 	uint64_t u64;
-	struct cvmx_l2c_oob_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_oob_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t dwbena                       : 1;  /**< DMA Out of Bounds Range Checker for DMA DWB
                                                          commands (Don't WriteBack).
@@ -4219,12 +4744,10 @@ typedef union cvmx_l2c_oob cvmx_l2c_oob_t;
  * Description: Defines DMA "Out of Bounds" region \#1. If a DMA initiated write transaction generates an address
  * within the specified region, the write is 'ignored' and an interrupt is generated to alert software.
  */
-union cvmx_l2c_oob1
-{
+union cvmx_l2c_oob1 {
 	uint64_t u64;
-	struct cvmx_l2c_oob1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_oob1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t fadr                         : 27; /**< DMA initated Memory Range Checker Failing Address
                                                          When L2C_INT_STAT[OOB1]=1, this field indicates the
                                                          DMA cacheline address.
@@ -4273,12 +4796,10 @@ typedef union cvmx_l2c_oob1 cvmx_l2c_oob1_t;
  * Description: Defines DMA "Out of Bounds" region \#2. If a DMA initiated write transaction generates an address
  * within the specified region, the write is 'ignored' and an interrupt is generated to alert software.
  */
-union cvmx_l2c_oob2
-{
+union cvmx_l2c_oob2 {
 	uint64_t u64;
-	struct cvmx_l2c_oob2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_oob2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t fadr                         : 27; /**< DMA initated Memory Range Checker Failing Address
                                                          When L2C_INT_STAT[OOB2]=1, this field indicates the
                                                          DMA cacheline address.
@@ -4327,12 +4848,10 @@ typedef union cvmx_l2c_oob2 cvmx_l2c_oob2_t;
  * Description: Defines DMA "Out of Bounds" region \#3. If a DMA initiated write transaction generates an address
  * within the specified region, the write is 'ignored' and an interrupt is generated to alert software.
  */
-union cvmx_l2c_oob3
-{
+union cvmx_l2c_oob3 {
 	uint64_t u64;
-	struct cvmx_l2c_oob3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_oob3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t fadr                         : 27; /**< DMA initated Memory Range Checker Failing Address
                                                          When L2C_INT_STAT[OOB3]=1, this field indicates the
                                                          DMA cacheline address.
@@ -4380,12 +4899,10 @@ typedef union cvmx_l2c_oob3 cvmx_l2c_oob3_t;
  *
  * Description:
  */
-union cvmx_l2c_pfcx
-{
+union cvmx_l2c_pfcx {
 	uint64_t u64;
-	struct cvmx_l2c_pfcx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_pfcx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t pfcnt0                       : 36; /**< Performance Counter \#0 */
 #else
@@ -4474,12 +4991,10 @@ typedef union cvmx_l2c_pfcx cvmx_l2c_pfcx_t;
  *            52       | DT RD-ALLOC (LDD/PSL1 Commands)
  *            53       | DT WR-INVAL (ST* Commands)
  */
-union cvmx_l2c_pfctl
-{
+union cvmx_l2c_pfctl {
 	uint64_t u64;
-	struct cvmx_l2c_pfctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_pfctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t cnt3rdclr                    : 1;  /**< Performance Counter 3 Read Clear
                                                          When set, all CSR reads of the L2C_PFC3
@@ -4586,12 +5101,10 @@ typedef union cvmx_l2c_pfctl cvmx_l2c_pfctl_t;
  *
  * Description: Defines the PP(Packet Processor) PLC Group \# (0,1,2)
  */
-union cvmx_l2c_ppgrp
-{
+union cvmx_l2c_ppgrp {
 	uint64_t u64;
-	struct cvmx_l2c_ppgrp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_ppgrp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t pp11grp                      : 2;  /**< PP11 PLC Group# (0,1,2) */
 	uint64_t pp10grp                      : 2;  /**< PP10 PLC Group# (0,1,2) */
@@ -4621,9 +5134,8 @@ union cvmx_l2c_ppgrp
 	uint64_t reserved_24_63               : 40;
 #endif
 	} s;
-	struct cvmx_l2c_ppgrp_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_ppgrp_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t pp3grp                       : 2;  /**< PP3 PLC Group# (0,1,2) */
 	uint64_t pp2grp                       : 2;  /**< PP2 PLC Group# (0,1,2) */
@@ -4650,12 +5162,23 @@ typedef union cvmx_l2c_ppgrp cvmx_l2c_ppgrp_t;
  *
  * Description:
  */
-union cvmx_l2c_qos_iobx
-{
+union cvmx_l2c_qos_iobx {
 	uint64_t u64;
-	struct cvmx_l2c_qos_iobx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_qos_iobx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t dwblvl                       : 3;  /**< QOS level for DWB commands. */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t lvl                          : 3;  /**< QOS level for non-DWB commands. */
+#else
+	uint64_t lvl                          : 3;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t dwblvl                       : 3;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_l2c_qos_iobx_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t dwblvl                       : 2;  /**< QOS level for DWB commands. */
 	uint64_t reserved_2_3                 : 2;
@@ -4666,9 +5189,13 @@ union cvmx_l2c_qos_iobx
 	uint64_t dwblvl                       : 2;
 	uint64_t reserved_6_63                : 58;
 #endif
-	} s;
-	struct cvmx_l2c_qos_iobx_s            cn63xx;
-	struct cvmx_l2c_qos_iobx_s            cn63xxp1;
+	} cn61xx;
+	struct cvmx_l2c_qos_iobx_cn61xx       cn63xx;
+	struct cvmx_l2c_qos_iobx_cn61xx       cn63xxp1;
+	struct cvmx_l2c_qos_iobx_cn61xx       cn66xx;
+	struct cvmx_l2c_qos_iobx_s            cn68xx;
+	struct cvmx_l2c_qos_iobx_s            cn68xxp1;
+	struct cvmx_l2c_qos_iobx_cn61xx       cnf71xx;
 };
 typedef union cvmx_l2c_qos_iobx cvmx_l2c_qos_iobx_t;
 
@@ -4679,21 +5206,32 @@ typedef union cvmx_l2c_qos_iobx cvmx_l2c_qos_iobx_t;
  *
  * Description:
  */
-union cvmx_l2c_qos_ppx
-{
+union cvmx_l2c_qos_ppx {
 	uint64_t u64;
-	struct cvmx_l2c_qos_ppx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_qos_ppx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_3_63                : 61;
+	uint64_t lvl                          : 3;  /**< QOS level to use for this PP. */
+#else
+	uint64_t lvl                          : 3;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_l2c_qos_ppx_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t lvl                          : 2;  /**< QOS level to use for this PP. */
 #else
 	uint64_t lvl                          : 2;
 	uint64_t reserved_2_63                : 62;
 #endif
-	} s;
-	struct cvmx_l2c_qos_ppx_s             cn63xx;
-	struct cvmx_l2c_qos_ppx_s             cn63xxp1;
+	} cn61xx;
+	struct cvmx_l2c_qos_ppx_cn61xx        cn63xx;
+	struct cvmx_l2c_qos_ppx_cn61xx        cn63xxp1;
+	struct cvmx_l2c_qos_ppx_cn61xx        cn66xx;
+	struct cvmx_l2c_qos_ppx_s             cn68xx;
+	struct cvmx_l2c_qos_ppx_s             cn68xxp1;
+	struct cvmx_l2c_qos_ppx_cn61xx        cnf71xx;
 };
 typedef union cvmx_l2c_qos_ppx cvmx_l2c_qos_ppx_t;
 
@@ -4703,12 +5241,31 @@ typedef union cvmx_l2c_qos_ppx cvmx_l2c_qos_ppx_t;
  * L2C_QOS_WGT = L2C QOS weights
  *
  */
-union cvmx_l2c_qos_wgt
-{
+union cvmx_l2c_qos_wgt {
 	uint64_t u64;
-	struct cvmx_l2c_qos_wgt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_qos_wgt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t wgt7                         : 8;  /**< Weight for QOS level 7 */
+	uint64_t wgt6                         : 8;  /**< Weight for QOS level 6 */
+	uint64_t wgt5                         : 8;  /**< Weight for QOS level 5 */
+	uint64_t wgt4                         : 8;  /**< Weight for QOS level 4 */
+	uint64_t wgt3                         : 8;  /**< Weight for QOS level 3 */
+	uint64_t wgt2                         : 8;  /**< Weight for QOS level 2 */
+	uint64_t wgt1                         : 8;  /**< Weight for QOS level 1 */
+	uint64_t wgt0                         : 8;  /**< Weight for QOS level 0 */
+#else
+	uint64_t wgt0                         : 8;
+	uint64_t wgt1                         : 8;
+	uint64_t wgt2                         : 8;
+	uint64_t wgt3                         : 8;
+	uint64_t wgt4                         : 8;
+	uint64_t wgt5                         : 8;
+	uint64_t wgt6                         : 8;
+	uint64_t wgt7                         : 8;
+#endif
+	} s;
+	struct cvmx_l2c_qos_wgt_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t wgt3                         : 8;  /**< Weight for QOS level 3 */
 	uint64_t wgt2                         : 8;  /**< Weight for QOS level 2 */
@@ -4721,9 +5278,13 @@ union cvmx_l2c_qos_wgt
 	uint64_t wgt3                         : 8;
 	uint64_t reserved_32_63               : 32;
 #endif
-	} s;
-	struct cvmx_l2c_qos_wgt_s             cn63xx;
-	struct cvmx_l2c_qos_wgt_s             cn63xxp1;
+	} cn61xx;
+	struct cvmx_l2c_qos_wgt_cn61xx        cn63xx;
+	struct cvmx_l2c_qos_wgt_cn61xx        cn63xxp1;
+	struct cvmx_l2c_qos_wgt_cn61xx        cn66xx;
+	struct cvmx_l2c_qos_wgt_s             cn68xx;
+	struct cvmx_l2c_qos_wgt_s             cn68xxp1;
+	struct cvmx_l2c_qos_wgt_cn61xx        cnf71xx;
 };
 typedef union cvmx_l2c_qos_wgt cvmx_l2c_qos_wgt_t;
 
@@ -4733,19 +5294,22 @@ typedef union cvmx_l2c_qos_wgt cvmx_l2c_qos_wgt_t;
  * L2C_RSC_PFC = L2C RSC Performance Counter(s)
  *
  */
-union cvmx_l2c_rscx_pfc
-{
+union cvmx_l2c_rscx_pfc {
 	uint64_t u64;
-	struct cvmx_l2c_rscx_pfc_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_rscx_pfc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t count                        : 64; /**< Current counter value */
 #else
 	uint64_t count                        : 64;
 #endif
 	} s;
+	struct cvmx_l2c_rscx_pfc_s            cn61xx;
 	struct cvmx_l2c_rscx_pfc_s            cn63xx;
 	struct cvmx_l2c_rscx_pfc_s            cn63xxp1;
+	struct cvmx_l2c_rscx_pfc_s            cn66xx;
+	struct cvmx_l2c_rscx_pfc_s            cn68xx;
+	struct cvmx_l2c_rscx_pfc_s            cn68xxp1;
+	struct cvmx_l2c_rscx_pfc_s            cnf71xx;
 };
 typedef union cvmx_l2c_rscx_pfc cvmx_l2c_rscx_pfc_t;
 
@@ -4755,19 +5319,22 @@ typedef union cvmx_l2c_rscx_pfc cvmx_l2c_rscx_pfc_t;
  * L2C_RSD_PFC = L2C RSD Performance Counter(s)
  *
  */
-union cvmx_l2c_rsdx_pfc
-{
+union cvmx_l2c_rsdx_pfc {
 	uint64_t u64;
-	struct cvmx_l2c_rsdx_pfc_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_rsdx_pfc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t count                        : 64; /**< Current counter value */
 #else
 	uint64_t count                        : 64;
 #endif
 	} s;
+	struct cvmx_l2c_rsdx_pfc_s            cn61xx;
 	struct cvmx_l2c_rsdx_pfc_s            cn63xx;
 	struct cvmx_l2c_rsdx_pfc_s            cn63xxp1;
+	struct cvmx_l2c_rsdx_pfc_s            cn66xx;
+	struct cvmx_l2c_rsdx_pfc_s            cn68xx;
+	struct cvmx_l2c_rsdx_pfc_s            cn68xxp1;
+	struct cvmx_l2c_rsdx_pfc_s            cnf71xx;
 };
 typedef union cvmx_l2c_rsdx_pfc cvmx_l2c_rsdx_pfc_t;
 
@@ -4785,12 +5352,10 @@ typedef union cvmx_l2c_rsdx_pfc cvmx_l2c_rsdx_pfc_t;
  * - NOTES: When L2C FUSE[136] is blown(CRIP_256K), then SETS#7-4 are SET in all UMSK'x' registers
  *          When L2C FUSE[137] is blown(CRIP_128K), then SETS#7-2 are SET in all UMSK'x' registers
  */
-union cvmx_l2c_spar0
-{
+union cvmx_l2c_spar0 {
 	uint64_t u64;
-	struct cvmx_l2c_spar0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_spar0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t umsk3                        : 8;  /**< PP[3] L2 'DO NOT USE' set partition mask */
 	uint64_t umsk2                        : 8;  /**< PP[2] L2 'DO NOT USE' set partition mask */
@@ -4804,9 +5369,8 @@ union cvmx_l2c_spar0
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
-	struct cvmx_l2c_spar0_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_spar0_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t umsk0                        : 4;  /**< PP[0] L2 'DO NOT USE' set partition mask */
 #else
@@ -4814,9 +5378,8 @@ union cvmx_l2c_spar0
 	uint64_t reserved_4_63                : 60;
 #endif
 	} cn30xx;
-	struct cvmx_l2c_spar0_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_spar0_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t umsk1                        : 4;  /**< PP[1] L2 'DO NOT USE' set partition mask */
 	uint64_t reserved_4_7                 : 4;
@@ -4830,9 +5393,8 @@ union cvmx_l2c_spar0
 	} cn31xx;
 	struct cvmx_l2c_spar0_s               cn38xx;
 	struct cvmx_l2c_spar0_s               cn38xxp2;
-	struct cvmx_l2c_spar0_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_spar0_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t umsk1                        : 8;  /**< PP[1] L2 'DO NOT USE' set partition mask */
 	uint64_t umsk0                        : 8;  /**< PP[0] L2 'DO NOT USE' set partition mask */
@@ -4865,12 +5427,10 @@ typedef union cvmx_l2c_spar0 cvmx_l2c_spar0_t;
  * - NOTES: When L2C FUSE[136] is blown(CRIP_1024K), then SETS#7-4 are SET in all UMSK'x' registers
  *          When L2C FUSE[137] is blown(CRIP_512K), then SETS#7-2 are SET in all UMSK'x' registers
  */
-union cvmx_l2c_spar1
-{
+union cvmx_l2c_spar1 {
 	uint64_t u64;
-	struct cvmx_l2c_spar1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_spar1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t umsk7                        : 8;  /**< PP[7] L2 'DO NOT USE' set partition mask */
 	uint64_t umsk6                        : 8;  /**< PP[6] L2 'DO NOT USE' set partition mask */
@@ -4907,12 +5467,10 @@ typedef union cvmx_l2c_spar1 cvmx_l2c_spar1_t;
  * - NOTES: When L2C FUSE[136] is blown(CRIP_1024K), then SETS#7-4 are SET in all UMSK'x' registers
  *          When L2C FUSE[137] is blown(CRIP_512K), then SETS#7-2 are SET in all UMSK'x' registers
  */
-union cvmx_l2c_spar2
-{
+union cvmx_l2c_spar2 {
 	uint64_t u64;
-	struct cvmx_l2c_spar2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_spar2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t umsk11                       : 8;  /**< PP[11] L2 'DO NOT USE' set partition mask */
 	uint64_t umsk10                       : 8;  /**< PP[10] L2 'DO NOT USE' set partition mask */
@@ -4949,12 +5507,10 @@ typedef union cvmx_l2c_spar2 cvmx_l2c_spar2_t;
  * - NOTES: When L2C FUSE[136] is blown(CRIP_1024K), then SETS#7-4 are SET in all UMSK'x' registers
  *          When L2C FUSE[137] is blown(CRIP_512K), then SETS#7-2 are SET in all UMSK'x' registers
  */
-union cvmx_l2c_spar3
-{
+union cvmx_l2c_spar3 {
 	uint64_t u64;
-	struct cvmx_l2c_spar3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_spar3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t umsk15                       : 8;  /**< PP[15] L2 'DO NOT USE' set partition mask */
 	uint64_t umsk14                       : 8;  /**< PP[14] L2 'DO NOT USE' set partition mask */
@@ -4989,12 +5545,10 @@ typedef union cvmx_l2c_spar3 cvmx_l2c_spar3_t;
  * - NOTES: When L2C FUSE[136] is blown(CRIP_256K), then SETS#7-4 are SET in all UMSK'x' registers
  *          When L2C FUSE[137] is blown(CRIP_128K), then SETS#7-2 are SET in all UMSK'x' registers
  */
-union cvmx_l2c_spar4
-{
+union cvmx_l2c_spar4 {
 	uint64_t u64;
-	struct cvmx_l2c_spar4_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_spar4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t umskiob                      : 8;  /**< IOB L2 'DO NOT USE' set partition mask */
 #else
@@ -5002,9 +5556,8 @@ union cvmx_l2c_spar4
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
-	struct cvmx_l2c_spar4_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_spar4_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t umskiob                      : 4;  /**< IOB L2 'DO NOT USE' set partition mask */
 #else
@@ -5032,12 +5585,10 @@ typedef union cvmx_l2c_spar4 cvmx_l2c_spar4_t;
  *
  * Description: holds the syndromes for a L2D read generated from L2C_XMC_CMD
  */
-union cvmx_l2c_tadx_ecc0
-{
+union cvmx_l2c_tadx_ecc0 {
 	uint64_t u64;
-	struct cvmx_l2c_tadx_ecc0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_tadx_ecc0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_58_63               : 6;
 	uint64_t ow3ecc                       : 10; /**< ECC for OW3 of cache block */
 	uint64_t reserved_42_47               : 6;
@@ -5057,8 +5608,13 @@ union cvmx_l2c_tadx_ecc0
 	uint64_t reserved_58_63               : 6;
 #endif
 	} s;
+	struct cvmx_l2c_tadx_ecc0_s           cn61xx;
 	struct cvmx_l2c_tadx_ecc0_s           cn63xx;
 	struct cvmx_l2c_tadx_ecc0_s           cn63xxp1;
+	struct cvmx_l2c_tadx_ecc0_s           cn66xx;
+	struct cvmx_l2c_tadx_ecc0_s           cn68xx;
+	struct cvmx_l2c_tadx_ecc0_s           cn68xxp1;
+	struct cvmx_l2c_tadx_ecc0_s           cnf71xx;
 };
 typedef union cvmx_l2c_tadx_ecc0 cvmx_l2c_tadx_ecc0_t;
 
@@ -5069,12 +5625,10 @@ typedef union cvmx_l2c_tadx_ecc0 cvmx_l2c_tadx_ecc0_t;
  *
  * Description: holds the syndromes for a L2D read generated from L2C_XMC_CMD
  */
-union cvmx_l2c_tadx_ecc1
-{
+union cvmx_l2c_tadx_ecc1 {
 	uint64_t u64;
-	struct cvmx_l2c_tadx_ecc1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_tadx_ecc1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_58_63               : 6;
 	uint64_t ow7ecc                       : 10; /**< ECC for OW7 of cache block */
 	uint64_t reserved_42_47               : 6;
@@ -5094,8 +5648,13 @@ union cvmx_l2c_tadx_ecc1
 	uint64_t reserved_58_63               : 6;
 #endif
 	} s;
+	struct cvmx_l2c_tadx_ecc1_s           cn61xx;
 	struct cvmx_l2c_tadx_ecc1_s           cn63xx;
 	struct cvmx_l2c_tadx_ecc1_s           cn63xxp1;
+	struct cvmx_l2c_tadx_ecc1_s           cn66xx;
+	struct cvmx_l2c_tadx_ecc1_s           cn68xx;
+	struct cvmx_l2c_tadx_ecc1_s           cn68xxp1;
+	struct cvmx_l2c_tadx_ecc1_s           cnf71xx;
 };
 typedef union cvmx_l2c_tadx_ecc1 cvmx_l2c_tadx_ecc1_t;
 
@@ -5105,12 +5664,10 @@ typedef union cvmx_l2c_tadx_ecc1 cvmx_l2c_tadx_ecc1_t;
  * L2C_TAD_IEN = L2C TAD Interrupt Enable
  *
  */
-union cvmx_l2c_tadx_ien
-{
+union cvmx_l2c_tadx_ien {
 	uint64_t u64;
-	struct cvmx_l2c_tadx_ien_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_tadx_ien_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t wrdislmc                     : 1;  /**< Illegal Write to Disabled LMC Error enable
                                                          Enables L2C_TADX_INT[WRDISLMC] to
@@ -5119,26 +5676,26 @@ union cvmx_l2c_tadx_ien
                                                          Enables L2C_TADX_INT[RDDISLMC] to
                                                          assert L2C_INT_REG[TADX] (and cause an interrupt) */
 	uint64_t noway                        : 1;  /**< No way available interrupt enable
-                                                         Enables L2C_ERR_TTGX[NOWAY] to assert
-                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+                                                         Enables L2C_ERR_TTGX[NOWAY]/L2C_TADX_INT[NOWAY] to
+                                                         assert L2C_INT_REG[TADX] (and cause an interrupt) */
 	uint64_t vbfdbe                       : 1;  /**< VBF Double-Bit Error enable
-                                                         Enables L2C_ERR_TDTX[VSBE] to assert
-                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+                                                         Enables L2C_ERR_TDTX[VDBE]/L2C_TADX_INT[VBFSBE] to
+                                                         assert L2C_INT_REG[TADX] (and cause an interrupt) */
 	uint64_t vbfsbe                       : 1;  /**< VBF Single-Bit Error enable
-                                                         Enables L2C_ERR_TDTX[VSBE] to assert
-                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+                                                         Enables L2C_ERR_TDTX[VSBE]/L2C_TADX_INT[VBFSBE] to
+                                                         assert L2C_INT_REG[TADX] (and cause an interrupt) */
 	uint64_t tagdbe                       : 1;  /**< TAG Double-Bit Error enable
-                                                         Enables L2C_ERR_TTGX[DBE] to assert
-                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+                                                         Enables L2C_ERR_TTGX[DBE]/L2C_TADX_INT[TAGDBE] to
+                                                         assert L2C_INT_REG[TADX] (and cause an interrupt) */
 	uint64_t tagsbe                       : 1;  /**< TAG Single-Bit Error enable
-                                                         Enables L2C_ERR_TTGX[SBE] to assert
-                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+                                                         Enables L2C_ERR_TTGX[SBE]/L2C_TADX_INT[TAGSBE] to
+                                                         assert L2C_INT_REG[TADX] (and cause an interrupt) */
 	uint64_t l2ddbe                       : 1;  /**< L2D Double-Bit Error enable
-                                                         Enables L2C_ERR_TDTX[DBE] to assert
-                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+                                                         Enables L2C_ERR_TDTX[DBE]/L2C_TADX_INT[L2DDBE] to
+                                                         assert L2C_INT_REG[TADX] (and cause an interrupt) */
 	uint64_t l2dsbe                       : 1;  /**< L2D Single-Bit Error enable
-                                                         Enables L2C_ERR_TDTX[SBE] to assert
-                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+                                                         Enables L2C_ERR_TDTX[SBE]/L2C_TADX_INT[L2DSBE] to
+                                                         assert L2C_INT_REG[TADX] (and cause an interrupt) */
 #else
 	uint64_t l2dsbe                       : 1;
 	uint64_t l2ddbe                       : 1;
@@ -5152,10 +5709,10 @@ union cvmx_l2c_tadx_ien
 	uint64_t reserved_9_63                : 55;
 #endif
 	} s;
+	struct cvmx_l2c_tadx_ien_s            cn61xx;
 	struct cvmx_l2c_tadx_ien_s            cn63xx;
-	struct cvmx_l2c_tadx_ien_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_tadx_ien_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t noway                        : 1;  /**< No way available interrupt enable
                                                          Enables L2C_ERR_TTGX[NOWAY] to assert
@@ -5189,6 +5746,10 @@ union cvmx_l2c_tadx_ien
 	uint64_t reserved_7_63                : 57;
 #endif
 	} cn63xxp1;
+	struct cvmx_l2c_tadx_ien_s            cn66xx;
+	struct cvmx_l2c_tadx_ien_s            cn68xx;
+	struct cvmx_l2c_tadx_ien_s            cn68xxp1;
+	struct cvmx_l2c_tadx_ien_s            cnf71xx;
 };
 typedef union cvmx_l2c_tadx_ien cvmx_l2c_tadx_ien_t;
 
@@ -5202,12 +5763,10 @@ typedef union cvmx_l2c_tadx_ien cvmx_l2c_tadx_ien_t;
  * L2C_TAD_IEN is the interrupt enable register corresponding to this register.
  *
  */
-union cvmx_l2c_tadx_int
-{
+union cvmx_l2c_tadx_int {
 	uint64_t u64;
-	struct cvmx_l2c_tadx_int_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_tadx_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t wrdislmc                     : 1;  /**< Illegal Write to Disabled LMC Error
                                                          A DRAM write arrived before the LMC(s) were enabled */
@@ -5247,7 +5806,12 @@ union cvmx_l2c_tadx_int
 	uint64_t reserved_9_63                : 55;
 #endif
 	} s;
+	struct cvmx_l2c_tadx_int_s            cn61xx;
 	struct cvmx_l2c_tadx_int_s            cn63xx;
+	struct cvmx_l2c_tadx_int_s            cn66xx;
+	struct cvmx_l2c_tadx_int_s            cn68xx;
+	struct cvmx_l2c_tadx_int_s            cn68xxp1;
+	struct cvmx_l2c_tadx_int_s            cnf71xx;
 };
 typedef union cvmx_l2c_tadx_int cvmx_l2c_tadx_int_t;
 
@@ -5257,19 +5821,22 @@ typedef union cvmx_l2c_tadx_int cvmx_l2c_tadx_int_t;
  * L2C_TAD_PFC0 = L2C TAD Performance Counter 0
  *
  */
-union cvmx_l2c_tadx_pfc0
-{
+union cvmx_l2c_tadx_pfc0 {
 	uint64_t u64;
-	struct cvmx_l2c_tadx_pfc0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_tadx_pfc0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t count                        : 64; /**< Current counter value */
 #else
 	uint64_t count                        : 64;
 #endif
 	} s;
+	struct cvmx_l2c_tadx_pfc0_s           cn61xx;
 	struct cvmx_l2c_tadx_pfc0_s           cn63xx;
 	struct cvmx_l2c_tadx_pfc0_s           cn63xxp1;
+	struct cvmx_l2c_tadx_pfc0_s           cn66xx;
+	struct cvmx_l2c_tadx_pfc0_s           cn68xx;
+	struct cvmx_l2c_tadx_pfc0_s           cn68xxp1;
+	struct cvmx_l2c_tadx_pfc0_s           cnf71xx;
 };
 typedef union cvmx_l2c_tadx_pfc0 cvmx_l2c_tadx_pfc0_t;
 
@@ -5279,19 +5846,22 @@ typedef union cvmx_l2c_tadx_pfc0 cvmx_l2c_tadx_pfc0_t;
  * L2C_TAD_PFC1 = L2C TAD Performance Counter 1
  *
  */
-union cvmx_l2c_tadx_pfc1
-{
+union cvmx_l2c_tadx_pfc1 {
 	uint64_t u64;
-	struct cvmx_l2c_tadx_pfc1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_tadx_pfc1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t count                        : 64; /**< Current counter value */
 #else
 	uint64_t count                        : 64;
 #endif
 	} s;
+	struct cvmx_l2c_tadx_pfc1_s           cn61xx;
 	struct cvmx_l2c_tadx_pfc1_s           cn63xx;
 	struct cvmx_l2c_tadx_pfc1_s           cn63xxp1;
+	struct cvmx_l2c_tadx_pfc1_s           cn66xx;
+	struct cvmx_l2c_tadx_pfc1_s           cn68xx;
+	struct cvmx_l2c_tadx_pfc1_s           cn68xxp1;
+	struct cvmx_l2c_tadx_pfc1_s           cnf71xx;
 };
 typedef union cvmx_l2c_tadx_pfc1 cvmx_l2c_tadx_pfc1_t;
 
@@ -5301,19 +5871,22 @@ typedef union cvmx_l2c_tadx_pfc1 cvmx_l2c_tadx_pfc1_t;
  * L2C_TAD_PFC2 = L2C TAD Performance Counter 2
  *
  */
-union cvmx_l2c_tadx_pfc2
-{
+union cvmx_l2c_tadx_pfc2 {
 	uint64_t u64;
-	struct cvmx_l2c_tadx_pfc2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_tadx_pfc2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t count                        : 64; /**< Current counter value */
 #else
 	uint64_t count                        : 64;
 #endif
 	} s;
+	struct cvmx_l2c_tadx_pfc2_s           cn61xx;
 	struct cvmx_l2c_tadx_pfc2_s           cn63xx;
 	struct cvmx_l2c_tadx_pfc2_s           cn63xxp1;
+	struct cvmx_l2c_tadx_pfc2_s           cn66xx;
+	struct cvmx_l2c_tadx_pfc2_s           cn68xx;
+	struct cvmx_l2c_tadx_pfc2_s           cn68xxp1;
+	struct cvmx_l2c_tadx_pfc2_s           cnf71xx;
 };
 typedef union cvmx_l2c_tadx_pfc2 cvmx_l2c_tadx_pfc2_t;
 
@@ -5323,19 +5896,22 @@ typedef union cvmx_l2c_tadx_pfc2 cvmx_l2c_tadx_pfc2_t;
  * L2C_TAD_PFC3 = L2C TAD Performance Counter 3
  *
  */
-union cvmx_l2c_tadx_pfc3
-{
+union cvmx_l2c_tadx_pfc3 {
 	uint64_t u64;
-	struct cvmx_l2c_tadx_pfc3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_tadx_pfc3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t count                        : 64; /**< Current counter value */
 #else
 	uint64_t count                        : 64;
 #endif
 	} s;
+	struct cvmx_l2c_tadx_pfc3_s           cn61xx;
 	struct cvmx_l2c_tadx_pfc3_s           cn63xx;
 	struct cvmx_l2c_tadx_pfc3_s           cn63xxp1;
+	struct cvmx_l2c_tadx_pfc3_s           cn66xx;
+	struct cvmx_l2c_tadx_pfc3_s           cn68xx;
+	struct cvmx_l2c_tadx_pfc3_s           cn68xxp1;
+	struct cvmx_l2c_tadx_pfc3_s           cnf71xx;
 };
 typedef union cvmx_l2c_tadx_pfc3 cvmx_l2c_tadx_pfc3_t;
 
@@ -5376,12 +5952,10 @@ typedef union cvmx_l2c_tadx_pfc3 cvmx_l2c_tadx_pfc3_t;
  *         0xB2 -- Quad 3 \# banks inuse (0-4/cycle)
  *         0xB3 -- Quad 3 wdat flops inuse (0-4/cycle)
  */
-union cvmx_l2c_tadx_prf
-{
+union cvmx_l2c_tadx_prf {
 	uint64_t u64;
-	struct cvmx_l2c_tadx_prf_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_tadx_prf_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt3sel                      : 8;  /**< Selects event to count for L2C_TAD_PFC3 */
 	uint64_t cnt2sel                      : 8;  /**< Selects event to count for L2C_TAD_PFC2 */
@@ -5395,8 +5969,13 @@ union cvmx_l2c_tadx_prf
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_l2c_tadx_prf_s            cn61xx;
 	struct cvmx_l2c_tadx_prf_s            cn63xx;
 	struct cvmx_l2c_tadx_prf_s            cn63xxp1;
+	struct cvmx_l2c_tadx_prf_s            cn66xx;
+	struct cvmx_l2c_tadx_prf_s            cn68xx;
+	struct cvmx_l2c_tadx_prf_s            cn68xxp1;
+	struct cvmx_l2c_tadx_prf_s            cnf71xx;
 };
 typedef union cvmx_l2c_tadx_prf cvmx_l2c_tadx_prf_t;
 
@@ -5415,12 +5994,10 @@ typedef union cvmx_l2c_tadx_prf cvmx_l2c_tadx_prf_t;
  *
  * (3) The tag is the corresponding bits from the L2C+LMC internal L2/DRAM byte address.
  */
-union cvmx_l2c_tadx_tag
-{
+union cvmx_l2c_tadx_tag {
 	uint64_t u64;
-	struct cvmx_l2c_tadx_tag_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_tadx_tag_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_46_63               : 18;
 	uint64_t ecc                          : 6;  /**< The tag ECC */
 	uint64_t reserved_36_39               : 4;
@@ -5442,8 +6019,13 @@ union cvmx_l2c_tadx_tag
 	uint64_t reserved_46_63               : 18;
 #endif
 	} s;
+	struct cvmx_l2c_tadx_tag_s            cn61xx;
 	struct cvmx_l2c_tadx_tag_s            cn63xx;
 	struct cvmx_l2c_tadx_tag_s            cn63xxp1;
+	struct cvmx_l2c_tadx_tag_s            cn66xx;
+	struct cvmx_l2c_tadx_tag_s            cn68xx;
+	struct cvmx_l2c_tadx_tag_s            cn68xxp1;
+	struct cvmx_l2c_tadx_tag_s            cnf71xx;
 };
 typedef union cvmx_l2c_tadx_tag cvmx_l2c_tadx_tag_t;
 
@@ -5454,19 +6036,23 @@ typedef union cvmx_l2c_tadx_tag cvmx_l2c_tadx_tag_t;
  *
  * Description: records virtualization IDs associated with HOLEWR/BIGWR/VRTWR/VRTIDRNG/VRTADRNG interrupts.
  */
-union cvmx_l2c_ver_id
-{
+union cvmx_l2c_ver_id {
 	uint64_t u64;
-	struct cvmx_l2c_ver_id_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t mask                         : 64; /**< Mask of virtualization IDs which had an error */
+	struct cvmx_l2c_ver_id_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mask                         : 64; /**< Mask of virtualization IDs which had a
+                                                         HOLEWR/BIGWR/VRTWR error */
 #else
 	uint64_t mask                         : 64;
 #endif
 	} s;
+	struct cvmx_l2c_ver_id_s              cn61xx;
 	struct cvmx_l2c_ver_id_s              cn63xx;
 	struct cvmx_l2c_ver_id_s              cn63xxp1;
+	struct cvmx_l2c_ver_id_s              cn66xx;
+	struct cvmx_l2c_ver_id_s              cn68xx;
+	struct cvmx_l2c_ver_id_s              cn68xxp1;
+	struct cvmx_l2c_ver_id_s              cnf71xx;
 };
 typedef union cvmx_l2c_ver_id cvmx_l2c_ver_id_t;
 
@@ -5477,21 +6063,32 @@ typedef union cvmx_l2c_ver_id cvmx_l2c_ver_id_t;
  *
  * Description: records IOBs associated with HOLEWR/BIGWR/VRTWR/VRTIDRNG/VRTADRNG interrupts.
  */
-union cvmx_l2c_ver_iob
-{
+union cvmx_l2c_ver_iob {
 	uint64_t u64;
-	struct cvmx_l2c_ver_iob_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_ver_iob_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_2_63                : 62;
+	uint64_t mask                         : 2;  /**< Mask of IOBs which had a HOLEWR/BIGWR/VRTWR error */
+#else
+	uint64_t mask                         : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_l2c_ver_iob_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
-	uint64_t mask                         : 1;  /**< Mask of IOBs which had a virtualization error */
+	uint64_t mask                         : 1;  /**< Mask of IOBs which had a HOLEWR/BIGWR/VRTWR error */
 #else
 	uint64_t mask                         : 1;
 	uint64_t reserved_1_63                : 63;
 #endif
-	} s;
-	struct cvmx_l2c_ver_iob_s             cn63xx;
-	struct cvmx_l2c_ver_iob_s             cn63xxp1;
+	} cn61xx;
+	struct cvmx_l2c_ver_iob_cn61xx        cn63xx;
+	struct cvmx_l2c_ver_iob_cn61xx        cn63xxp1;
+	struct cvmx_l2c_ver_iob_cn61xx        cn66xx;
+	struct cvmx_l2c_ver_iob_s             cn68xx;
+	struct cvmx_l2c_ver_iob_s             cn68xxp1;
+	struct cvmx_l2c_ver_iob_cn61xx        cnf71xx;
 };
 typedef union cvmx_l2c_ver_iob cvmx_l2c_ver_iob_t;
 
@@ -5502,12 +6099,10 @@ typedef union cvmx_l2c_ver_iob cvmx_l2c_ver_iob_t;
  *
  * Description: records type of command associated with HOLEWR/BIGWR/VRTWR/VRTIDRNG/VRTADRNG interrupts
  */
-union cvmx_l2c_ver_msc
-{
+union cvmx_l2c_ver_msc {
 	uint64_t u64;
-	struct cvmx_l2c_ver_msc_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_ver_msc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t invl2                        : 1;  /**< If set, a INVL2 caused HOLEWR/BIGWR/VRT* to set */
 	uint64_t dwb                          : 1;  /**< If set, a DWB caused HOLEWR/BIGWR/VRT* to set */
@@ -5517,7 +6112,12 @@ union cvmx_l2c_ver_msc
 	uint64_t reserved_2_63                : 62;
 #endif
 	} s;
+	struct cvmx_l2c_ver_msc_s             cn61xx;
 	struct cvmx_l2c_ver_msc_s             cn63xx;
+	struct cvmx_l2c_ver_msc_s             cn66xx;
+	struct cvmx_l2c_ver_msc_s             cn68xx;
+	struct cvmx_l2c_ver_msc_s             cn68xxp1;
+	struct cvmx_l2c_ver_msc_s             cnf71xx;
 };
 typedef union cvmx_l2c_ver_msc cvmx_l2c_ver_msc_t;
 
@@ -5528,21 +6128,48 @@ typedef union cvmx_l2c_ver_msc cvmx_l2c_ver_msc_t;
  *
  * Description: records PPs associated with HOLEWR/BIGWR/VRTWR/VRTIDRNG/VRTADRNG interrupts.
  */
-union cvmx_l2c_ver_pp
-{
+union cvmx_l2c_ver_pp {
 	uint64_t u64;
-	struct cvmx_l2c_ver_pp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_ver_pp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t mask                         : 32; /**< Mask of PPs which had a HOLEWR/BIGWR/VRTWR error */
+#else
+	uint64_t mask                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_l2c_ver_pp_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t mask                         : 4;  /**< Mask of PPs which had a HOLEWR/BIGWR/VRTWR error */
+#else
+	uint64_t mask                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn61xx;
+	struct cvmx_l2c_ver_pp_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
-	uint64_t mask                         : 6;  /**< Mask of PPs which had a virtualization error */
+	uint64_t mask                         : 6;  /**< Mask of PPs which had a HOLEWR/BIGWR/VRTWR error */
 #else
 	uint64_t mask                         : 6;
 	uint64_t reserved_6_63                : 58;
 #endif
-	} s;
-	struct cvmx_l2c_ver_pp_s              cn63xx;
-	struct cvmx_l2c_ver_pp_s              cn63xxp1;
+	} cn63xx;
+	struct cvmx_l2c_ver_pp_cn63xx         cn63xxp1;
+	struct cvmx_l2c_ver_pp_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t mask                         : 10; /**< Mask of PPs which had a HOLEWR/BIGWR/VRTWR error */
+#else
+	uint64_t mask                         : 10;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn66xx;
+	struct cvmx_l2c_ver_pp_s              cn68xx;
+	struct cvmx_l2c_ver_pp_s              cn68xxp1;
+	struct cvmx_l2c_ver_pp_cn61xx         cnf71xx;
 };
 typedef union cvmx_l2c_ver_pp cvmx_l2c_ver_pp_t;
 
@@ -5553,12 +6180,10 @@ typedef union cvmx_l2c_ver_pp cvmx_l2c_ver_pp_t;
  *
  * Description:
  */
-union cvmx_l2c_virtid_iobx
-{
+union cvmx_l2c_virtid_iobx {
 	uint64_t u64;
-	struct cvmx_l2c_virtid_iobx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_virtid_iobx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t dwbid                        : 6;  /**< Virtualization ID to use for DWB commands */
 	uint64_t reserved_6_7                 : 2;
@@ -5570,8 +6195,13 @@ union cvmx_l2c_virtid_iobx
 	uint64_t reserved_14_63               : 50;
 #endif
 	} s;
+	struct cvmx_l2c_virtid_iobx_s         cn61xx;
 	struct cvmx_l2c_virtid_iobx_s         cn63xx;
 	struct cvmx_l2c_virtid_iobx_s         cn63xxp1;
+	struct cvmx_l2c_virtid_iobx_s         cn66xx;
+	struct cvmx_l2c_virtid_iobx_s         cn68xx;
+	struct cvmx_l2c_virtid_iobx_s         cn68xxp1;
+	struct cvmx_l2c_virtid_iobx_s         cnf71xx;
 };
 typedef union cvmx_l2c_virtid_iobx cvmx_l2c_virtid_iobx_t;
 
@@ -5582,12 +6212,10 @@ typedef union cvmx_l2c_virtid_iobx cvmx_l2c_virtid_iobx_t;
  *
  * Description:
  */
-union cvmx_l2c_virtid_ppx
-{
+union cvmx_l2c_virtid_ppx {
 	uint64_t u64;
-	struct cvmx_l2c_virtid_ppx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_virtid_ppx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t id                           : 6;  /**< Virtualization ID to use for this PP. */
 #else
@@ -5595,8 +6223,13 @@ union cvmx_l2c_virtid_ppx
 	uint64_t reserved_6_63                : 58;
 #endif
 	} s;
+	struct cvmx_l2c_virtid_ppx_s          cn61xx;
 	struct cvmx_l2c_virtid_ppx_s          cn63xx;
 	struct cvmx_l2c_virtid_ppx_s          cn63xxp1;
+	struct cvmx_l2c_virtid_ppx_s          cn66xx;
+	struct cvmx_l2c_virtid_ppx_s          cn68xx;
+	struct cvmx_l2c_virtid_ppx_s          cn68xxp1;
+	struct cvmx_l2c_virtid_ppx_s          cnf71xx;
 };
 typedef union cvmx_l2c_virtid_ppx cvmx_l2c_virtid_ppx_t;
 
@@ -5606,12 +6239,10 @@ typedef union cvmx_l2c_virtid_ppx cvmx_l2c_virtid_ppx_t;
  * L2C_VRT_CTL = L2C Virtualization control register
  *
  */
-union cvmx_l2c_vrt_ctl
-{
+union cvmx_l2c_vrt_ctl {
 	uint64_t u64;
-	struct cvmx_l2c_vrt_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_vrt_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t ooberr                       : 1;  /**< Whether out of bounds writes are an error
                                                          Determines virtualization hardware behavior for
@@ -5652,8 +6283,13 @@ union cvmx_l2c_vrt_ctl
 	uint64_t reserved_9_63                : 55;
 #endif
 	} s;
+	struct cvmx_l2c_vrt_ctl_s             cn61xx;
 	struct cvmx_l2c_vrt_ctl_s             cn63xx;
 	struct cvmx_l2c_vrt_ctl_s             cn63xxp1;
+	struct cvmx_l2c_vrt_ctl_s             cn66xx;
+	struct cvmx_l2c_vrt_ctl_s             cn68xx;
+	struct cvmx_l2c_vrt_ctl_s             cn68xxp1;
+	struct cvmx_l2c_vrt_ctl_s             cnf71xx;
 };
 typedef union cvmx_l2c_vrt_ctl cvmx_l2c_vrt_ctl_t;
 
@@ -5704,12 +6340,10 @@ typedef union cvmx_l2c_vrt_ctl cvmx_l2c_vrt_ctl_t;
  *   For L2/DRAM physical address 0x51000000 with virtID=5:
  *      L2C_VRT_MEM648[DATA<4>] determines when the store is allowed (648 is decimal, not hex)
  */
-union cvmx_l2c_vrt_memx
-{
+union cvmx_l2c_vrt_memx {
 	uint64_t u64;
-	struct cvmx_l2c_vrt_memx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_vrt_memx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t parity                       : 4;  /**< Parity to write into (or read from) the
                                                          virtualization memory.
@@ -5722,8 +6356,13 @@ union cvmx_l2c_vrt_memx
 	uint64_t reserved_36_63               : 28;
 #endif
 	} s;
+	struct cvmx_l2c_vrt_memx_s            cn61xx;
 	struct cvmx_l2c_vrt_memx_s            cn63xx;
 	struct cvmx_l2c_vrt_memx_s            cn63xxp1;
+	struct cvmx_l2c_vrt_memx_s            cn66xx;
+	struct cvmx_l2c_vrt_memx_s            cn68xx;
+	struct cvmx_l2c_vrt_memx_s            cn68xxp1;
+	struct cvmx_l2c_vrt_memx_s            cnf71xx;
 };
 typedef union cvmx_l2c_vrt_memx cvmx_l2c_vrt_memx_t;
 
@@ -5737,12 +6376,10 @@ typedef union cvmx_l2c_vrt_memx cvmx_l2c_vrt_memx_t;
  * (1) The read value of MASK will include bits set because of the L2C cripple fuses.
  *
  */
-union cvmx_l2c_wpar_iobx
-{
+union cvmx_l2c_wpar_iobx {
 	uint64_t u64;
-	struct cvmx_l2c_wpar_iobx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_wpar_iobx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t mask                         : 16; /**< Way partitioning mask. (1 means do not use) */
 #else
@@ -5750,8 +6387,13 @@ union cvmx_l2c_wpar_iobx
 	uint64_t reserved_16_63               : 48;
 #endif
 	} s;
+	struct cvmx_l2c_wpar_iobx_s           cn61xx;
 	struct cvmx_l2c_wpar_iobx_s           cn63xx;
 	struct cvmx_l2c_wpar_iobx_s           cn63xxp1;
+	struct cvmx_l2c_wpar_iobx_s           cn66xx;
+	struct cvmx_l2c_wpar_iobx_s           cn68xx;
+	struct cvmx_l2c_wpar_iobx_s           cn68xxp1;
+	struct cvmx_l2c_wpar_iobx_s           cnf71xx;
 };
 typedef union cvmx_l2c_wpar_iobx cvmx_l2c_wpar_iobx_t;
 
@@ -5765,12 +6407,10 @@ typedef union cvmx_l2c_wpar_iobx cvmx_l2c_wpar_iobx_t;
  * (1) The read value of MASK will include bits set because of the L2C cripple fuses.
  *
  */
-union cvmx_l2c_wpar_ppx
-{
+union cvmx_l2c_wpar_ppx {
 	uint64_t u64;
-	struct cvmx_l2c_wpar_ppx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_wpar_ppx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t mask                         : 16; /**< Way partitioning mask. (1 means do not use) */
 #else
@@ -5778,8 +6418,13 @@ union cvmx_l2c_wpar_ppx
 	uint64_t reserved_16_63               : 48;
 #endif
 	} s;
+	struct cvmx_l2c_wpar_ppx_s            cn61xx;
 	struct cvmx_l2c_wpar_ppx_s            cn63xx;
 	struct cvmx_l2c_wpar_ppx_s            cn63xxp1;
+	struct cvmx_l2c_wpar_ppx_s            cn66xx;
+	struct cvmx_l2c_wpar_ppx_s            cn68xx;
+	struct cvmx_l2c_wpar_ppx_s            cn68xxp1;
+	struct cvmx_l2c_wpar_ppx_s            cnf71xx;
 };
 typedef union cvmx_l2c_wpar_ppx cvmx_l2c_wpar_ppx_t;
 
@@ -5789,19 +6434,22 @@ typedef union cvmx_l2c_wpar_ppx cvmx_l2c_wpar_ppx_t;
  * L2C_XMC_PFC = L2C XMC Performance Counter(s)
  *
  */
-union cvmx_l2c_xmcx_pfc
-{
+union cvmx_l2c_xmcx_pfc {
 	uint64_t u64;
-	struct cvmx_l2c_xmcx_pfc_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_xmcx_pfc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t count                        : 64; /**< Current counter value */
 #else
 	uint64_t count                        : 64;
 #endif
 	} s;
+	struct cvmx_l2c_xmcx_pfc_s            cn61xx;
 	struct cvmx_l2c_xmcx_pfc_s            cn63xx;
 	struct cvmx_l2c_xmcx_pfc_s            cn63xxp1;
+	struct cvmx_l2c_xmcx_pfc_s            cn66xx;
+	struct cvmx_l2c_xmcx_pfc_s            cn68xx;
+	struct cvmx_l2c_xmcx_pfc_s            cn68xxp1;
+	struct cvmx_l2c_xmcx_pfc_s            cnf71xx;
 };
 typedef union cvmx_l2c_xmcx_pfc cvmx_l2c_xmcx_pfc_t;
 
@@ -5838,12 +6486,10 @@ typedef union cvmx_l2c_xmcx_pfc cvmx_l2c_xmcx_pfc_t;
  *     index aliasing (if enabled) on the written address and uses that for the command. This hole
  *     removed/index aliased 38-bit address is what is returned on a read of the L2C_XMC_CMD register.
  */
-union cvmx_l2c_xmc_cmd
-{
+union cvmx_l2c_xmc_cmd {
 	uint64_t u64;
-	struct cvmx_l2c_xmc_cmd_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_xmc_cmd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t inuse                        : 1;  /**< Set to 1 by HW upon receiving a write, cleared when
                                                          command has issued (not necessarily completed, but
                                                          ordered relative to other traffic) and HW can accept
@@ -5859,8 +6505,13 @@ union cvmx_l2c_xmc_cmd
 	uint64_t inuse                        : 1;
 #endif
 	} s;
+	struct cvmx_l2c_xmc_cmd_s             cn61xx;
 	struct cvmx_l2c_xmc_cmd_s             cn63xx;
 	struct cvmx_l2c_xmc_cmd_s             cn63xxp1;
+	struct cvmx_l2c_xmc_cmd_s             cn66xx;
+	struct cvmx_l2c_xmc_cmd_s             cn68xx;
+	struct cvmx_l2c_xmc_cmd_s             cn68xxp1;
+	struct cvmx_l2c_xmc_cmd_s             cnf71xx;
 };
 typedef union cvmx_l2c_xmc_cmd cvmx_l2c_xmc_cmd_t;
 
@@ -5870,19 +6521,22 @@ typedef union cvmx_l2c_xmc_cmd cvmx_l2c_xmc_cmd_t;
  * L2C_XMD_PFC = L2C XMD Performance Counter(s)
  *
  */
-union cvmx_l2c_xmdx_pfc
-{
+union cvmx_l2c_xmdx_pfc {
 	uint64_t u64;
-	struct cvmx_l2c_xmdx_pfc_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2c_xmdx_pfc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t count                        : 64; /**< Current counter value */
 #else
 	uint64_t count                        : 64;
 #endif
 	} s;
+	struct cvmx_l2c_xmdx_pfc_s            cn61xx;
 	struct cvmx_l2c_xmdx_pfc_s            cn63xx;
 	struct cvmx_l2c_xmdx_pfc_s            cn63xxp1;
+	struct cvmx_l2c_xmdx_pfc_s            cn66xx;
+	struct cvmx_l2c_xmdx_pfc_s            cn68xx;
+	struct cvmx_l2c_xmdx_pfc_s            cn68xxp1;
+	struct cvmx_l2c_xmdx_pfc_s            cnf71xx;
 };
 typedef union cvmx_l2c_xmdx_pfc cvmx_l2c_xmdx_pfc_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-l2c.c b/sys/contrib/octeon-sdk/cvmx-l2c.c
index fab7141..8a39f9e 100644
--- a/sys/contrib/octeon-sdk/cvmx-l2c.c
+++ b/sys/contrib/octeon-sdk/cvmx-l2c.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -37,21 +37,16 @@
  * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
-
-
-
-
-
-
 /**
  * @file
  *
  * Implementation of the Level 2 Cache (L2C) control,
  * measurement, and debugging facilities.
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70215 $<hr>
  *
  */
+
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <asm/octeon/cvmx.h>
 #include <asm/octeon/cvmx-l2c.h>
@@ -67,110 +62,110 @@
 #endif
 
 #ifndef CVMX_BUILD_FOR_LINUX_HOST
-/* This spinlock is used internally to ensure that only one core is performing
-** certain L2 operations at a time.
-**
-** NOTE: This only protects calls from within a single application - if multiple applications
-** or operating systems are running, then it is up to the user program to coordinate between them.
-*/
+/*
+ * This spinlock is used internally to ensure that only one core is
+ * performing certain L2 operations at a time.
+ *
+ * NOTE: This only protects calls from within a single application -
+ * if multiple applications or operating systems are running, then it
+ * is up to the user program to coordinate between them.
+ */
 CVMX_SHARED cvmx_spinlock_t cvmx_l2c_spinlock;
 #endif
 
-CVMX_SHARED cvmx_spinlock_t cvmx_l2c_vrt_spinlock;
-
 int cvmx_l2c_get_core_way_partition(uint32_t core)
 {
-    uint32_t    field;
+    uint32_t field;
 
     /* Validate the core number */
     if (core >= cvmx_octeon_num_cores())
         return -1;
 
-    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
         return (cvmx_read_csr(CVMX_L2C_WPAR_PPX(core)) & 0xffff);
 
-    /* Use the lower two bits of the coreNumber to determine the bit offset
-     * of the UMSK[] field in the L2C_SPAR register.
+    /*
+     * Use the lower two bits of the coreNumber to determine the
+     * bit offset of the UMSK[] field in the L2C_SPAR register.
      */
     field = (core & 0x3) * 8;
 
-    /* Return the UMSK[] field from the appropriate L2C_SPAR register based
-     * on the coreNumber.
+    /*
+     * Return the UMSK[] field from the appropriate L2C_SPAR
+     * register based on the coreNumber.
      */
 
-    switch (core & 0xC)
-    {
-        case 0x0:
-            return((cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >> field);
-        case 0x4:
-            return((cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >> field);
-        case 0x8:
-            return((cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >> field);
-        case 0xC:
-            return((cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >> field);
+    switch (core & 0xC) {
+    case 0x0:
+        return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >> field;
+    case 0x4:
+        return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >> field;
+    case 0x8:
+        return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >> field;
+    case 0xC:
+        return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >> field;
     }
-    return(0);
+    return 0;
 }
 
 int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask)
 {
-    uint32_t    field;
-    uint32_t    valid_mask;
+    uint32_t field;
+    uint32_t valid_mask;
 
     valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1;
 
     mask &= valid_mask;
 
     /* A UMSK setting which blocks all L2C Ways is an error on some chips */
-    if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX))
+    if (mask == valid_mask && (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
         return -1;
 
     /* Validate the core number */
     if (core >= cvmx_octeon_num_cores())
         return -1;
 
-    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
-    {
-       cvmx_write_csr(CVMX_L2C_WPAR_PPX(core), mask);
-       return 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) {
+        cvmx_write_csr(CVMX_L2C_WPAR_PPX(core), mask);
+        return 0;
     }
 
-    /* Use the lower two bits of core to determine the bit offset of the
+    /*
+     * Use the lower two bits of core to determine the bit offset of the
      * UMSK[] field in the L2C_SPAR register.
      */
     field = (core & 0x3) * 8;
 
-    /* Assign the new mask setting to the UMSK[] field in the appropriate
+    /*
+     * Assign the new mask setting to the UMSK[] field in the appropriate
      * L2C_SPAR register based on the core_num.
      *
      */
-    switch (core & 0xC)
-    {
-        case 0x0:
-            cvmx_write_csr(CVMX_L2C_SPAR0,
-                           (cvmx_read_csr(CVMX_L2C_SPAR0) & ~(0xFF << field)) |
-                           mask << field);
-            break;
-        case 0x4:
-            cvmx_write_csr(CVMX_L2C_SPAR1,
-                           (cvmx_read_csr(CVMX_L2C_SPAR1) & ~(0xFF << field)) |
-                           mask << field);
-            break;
-        case 0x8:
-            cvmx_write_csr(CVMX_L2C_SPAR2,
-                           (cvmx_read_csr(CVMX_L2C_SPAR2) & ~(0xFF << field)) |
-                           mask << field);
-            break;
-        case 0xC:
-            cvmx_write_csr(CVMX_L2C_SPAR3,
-                           (cvmx_read_csr(CVMX_L2C_SPAR3) & ~(0xFF << field)) |
-                           mask << field);
-            break;
+    switch (core & 0xC) {
+    case 0x0:
+        cvmx_write_csr(CVMX_L2C_SPAR0,
+                   (cvmx_read_csr(CVMX_L2C_SPAR0) & ~(0xFF << field)) |
+                   mask << field);
+        break;
+    case 0x4:
+        cvmx_write_csr(CVMX_L2C_SPAR1,
+                   (cvmx_read_csr(CVMX_L2C_SPAR1) & ~(0xFF << field)) |
+                   mask << field);
+        break;
+    case 0x8:
+        cvmx_write_csr(CVMX_L2C_SPAR2,
+                   (cvmx_read_csr(CVMX_L2C_SPAR2) & ~(0xFF << field)) |
+                   mask << field);
+        break;
+    case 0xC:
+        cvmx_write_csr(CVMX_L2C_SPAR3,
+                   (cvmx_read_csr(CVMX_L2C_SPAR3) & ~(0xFF << field)) |
+                   mask << field);
+        break;
     }
     return 0;
 }
 
-
 int cvmx_l2c_set_hw_way_partition(uint32_t mask)
 {
     uint32_t valid_mask;
@@ -179,64 +174,84 @@ int cvmx_l2c_set_hw_way_partition(uint32_t mask)
     mask &= valid_mask;
 
     /* A UMSK setting which blocks all L2C Ways is an error on some chips */
-    if (mask == valid_mask  && !OCTEON_IS_MODEL(OCTEON_CN63XX))
+    if (mask == valid_mask  && (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
         return -1;
 
-    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
         cvmx_write_csr(CVMX_L2C_WPAR_IOBX(0), mask);
     else
-        cvmx_write_csr(CVMX_L2C_SPAR4, (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask);
+        cvmx_write_csr(CVMX_L2C_SPAR4,
+                   (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask);
     return 0;
 }
 
 int cvmx_l2c_get_hw_way_partition(void)
 {
-    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
-        return(cvmx_read_csr(CVMX_L2C_WPAR_IOBX(0)) & 0xffff);
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
+        return cvmx_read_csr(CVMX_L2C_WPAR_IOBX(0)) & 0xffff;
     else
-        return(cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF));
+        return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF);
 }
 
-void cvmx_l2c_config_perf(uint32_t counter, cvmx_l2c_event_t event,
-                          uint32_t clear_on_read)
+int cvmx_l2c_set_hw_way_partition2(uint32_t mask)
 {
+    uint32_t valid_mask;
 
-    if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
-    {
-        cvmx_l2c_pfctl_t pfctl;
+        if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
+            return -1;
+
+    valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1;
+    mask &= valid_mask;
+        cvmx_write_csr(CVMX_L2C_WPAR_IOBX(1), mask);
+        return 0;
+}
+
+int cvmx_l2c_get_hw_way_partition2(void)
+{
+        if (!OCTEON_IS_MODEL(OCTEON_CN68XX)) {
+            cvmx_warn("only one IOB on this chip");
+            return -1;
+        }
+        return cvmx_read_csr(CVMX_L2C_WPAR_IOBX(1)) & 0xffff;
+}
+
+
+
+void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event,
+              uint32_t clear_on_read)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
+        union cvmx_l2c_pfctl pfctl;
 
         pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL);
 
-        switch (counter)
-        {
-            case 0:
-                pfctl.s.cnt0sel = event;
-                pfctl.s.cnt0ena = 1;
-                pfctl.s.cnt0rdclr = clear_on_read;
-                break;
-            case 1:
-                pfctl.s.cnt1sel = event;
-                pfctl.s.cnt1ena = 1;
-                pfctl.s.cnt1rdclr = clear_on_read;
-                break;
-            case 2:
-                pfctl.s.cnt2sel = event;
-                pfctl.s.cnt2ena = 1;
-                pfctl.s.cnt2rdclr = clear_on_read;
-                break;
-            case 3:
-            default:
-                pfctl.s.cnt3sel = event;
-                pfctl.s.cnt3ena = 1;
-                pfctl.s.cnt3rdclr = clear_on_read;
-                break;
+        switch (counter) {
+        case 0:
+            pfctl.s.cnt0sel = event;
+            pfctl.s.cnt0ena = 1;
+            pfctl.s.cnt0rdclr = clear_on_read;
+            break;
+        case 1:
+            pfctl.s.cnt1sel = event;
+            pfctl.s.cnt1ena = 1;
+            pfctl.s.cnt1rdclr = clear_on_read;
+            break;
+        case 2:
+            pfctl.s.cnt2sel = event;
+            pfctl.s.cnt2ena = 1;
+            pfctl.s.cnt2rdclr = clear_on_read;
+            break;
+        case 3:
+        default:
+            pfctl.s.cnt3sel = event;
+            pfctl.s.cnt3ena = 1;
+            pfctl.s.cnt3rdclr = clear_on_read;
+            break;
         }
 
         cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64);
-    }
-    else
-    {
-        cvmx_l2c_tadx_prf_t l2c_tadx_prf;
+    } else {
+        union cvmx_l2c_tadx_prf l2c_tadx_prf;
         int tad;
 
         cvmx_warn("L2C performance counter events are different for this chip, mapping 'event' to cvmx_l2c_tad_event_t\n");
@@ -245,76 +260,71 @@ void cvmx_l2c_config_perf(uint32_t counter, cvmx_l2c_event_t event,
 
         l2c_tadx_prf.u64 = cvmx_read_csr(CVMX_L2C_TADX_PRF(0));
 
-        switch (counter)
-        {
-            case 0:
-                l2c_tadx_prf.s.cnt0sel = event;
-                break;
-            case 1:
-                l2c_tadx_prf.s.cnt1sel = event;
-                break;
-            case 2:
-                l2c_tadx_prf.s.cnt2sel = event;
-                break;
-            default:
-            case 3:
-                l2c_tadx_prf.s.cnt3sel = event;
-                break;
+        switch (counter) {
+        case 0:
+            l2c_tadx_prf.s.cnt0sel = event;
+            break;
+        case 1:
+            l2c_tadx_prf.s.cnt1sel = event;
+            break;
+        case 2:
+            l2c_tadx_prf.s.cnt2sel = event;
+            break;
+        default:
+        case 3:
+            l2c_tadx_prf.s.cnt3sel = event;
+            break;
         }
-        for (tad=0; tad<CVMX_L2C_TADS; tad++)
-            cvmx_write_csr(CVMX_L2C_TADX_PRF(tad), l2c_tadx_prf.u64);
+        for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+            cvmx_write_csr(CVMX_L2C_TADX_PRF(tad),
+                       l2c_tadx_prf.u64);
     }
 }
 
 uint64_t cvmx_l2c_read_perf(uint32_t counter)
 {
-    switch (counter)
-    {
-        case 0:
-            if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
-                return(cvmx_read_csr(CVMX_L2C_PFC0));
-            else
-            {
-                uint64_t counter = 0;
-                int tad;
-                for (tad=0; tad<CVMX_L2C_TADS; tad++)
-                    counter += cvmx_read_csr(CVMX_L2C_TADX_PFC0(tad));
-                return counter;
-            }
-        case 1:
-            if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
-                return(cvmx_read_csr(CVMX_L2C_PFC1));
-            else
-            {
-                uint64_t counter = 0;
-                int tad;
-                for (tad=0; tad<CVMX_L2C_TADS; tad++)
-                    counter += cvmx_read_csr(CVMX_L2C_TADX_PFC1(tad));
-                return counter;
-            }
-        case 2:
-            if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
-                return(cvmx_read_csr(CVMX_L2C_PFC2));
-            else
-            {
-                uint64_t counter = 0;
-                int tad;
-                for (tad=0; tad<CVMX_L2C_TADS; tad++)
-                    counter += cvmx_read_csr(CVMX_L2C_TADX_PFC2(tad));
-                return counter;
-            }
-        case 3:
-        default:
-            if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
-                return(cvmx_read_csr(CVMX_L2C_PFC3));
-            else
-            {
-                uint64_t counter = 0;
-                int tad;
-                for (tad=0; tad<CVMX_L2C_TADS; tad++)
-                    counter += cvmx_read_csr(CVMX_L2C_TADX_PFC3(tad));
-                return counter;
-            }
+    switch (counter) {
+    case 0:
+        if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+            return cvmx_read_csr(CVMX_L2C_PFC0);
+        else {
+            uint64_t counter = 0;
+            int tad;
+            for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+                counter += cvmx_read_csr(CVMX_L2C_TADX_PFC0(tad));
+            return counter;
+        }
+    case 1:
+        if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+            return cvmx_read_csr(CVMX_L2C_PFC1);
+        else {
+            uint64_t counter = 0;
+            int tad;
+            for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+                counter += cvmx_read_csr(CVMX_L2C_TADX_PFC1(tad));
+            return counter;
+        }
+    case 2:
+        if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+            return cvmx_read_csr(CVMX_L2C_PFC2);
+        else {
+            uint64_t counter = 0;
+            int tad;
+            for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+                counter += cvmx_read_csr(CVMX_L2C_TADX_PFC2(tad));
+            return counter;
+        }
+    case 3:
+    default:
+        if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+            return cvmx_read_csr(CVMX_L2C_PFC3);
+        else {
+            uint64_t counter = 0;
+            int tad;
+            for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+                counter += cvmx_read_csr(CVMX_L2C_TADX_PFC3(tad));
+            return counter;
+        }
     }
 }
 
@@ -330,14 +340,19 @@ static void fault_in(uint64_t addr, int len)
 {
     volatile char *ptr;
     volatile char dummy;
-    /* Adjust addr and length so we get all cache lines even for
-    ** small ranges spanning two cache lines */
+    /*
+     * Adjust addr and length so we get all cache lines even for
+     * small ranges spanning two cache lines.
+     */
     len += addr & CVMX_CACHE_LINE_MASK;
     addr &= ~CVMX_CACHE_LINE_MASK;
     ptr = (volatile char *)cvmx_phys_to_ptr(addr);
-    CVMX_DCACHE_INVALIDATE;  /* Invalidate L1 cache to make sure all loads result in data being in L2 */
-    while (len > 0)
-    {
+    /*
+     * Invalidate L1 cache to make sure all loads result in data
+     * being in L2.
+     */
+    CVMX_DCACHE_INVALIDATE;
+    while (len > 0) {
         dummy += *ptr;
         len -= CVMX_CACHE_LINE_SIZE;
         ptr += CVMX_CACHE_LINE_SIZE;
@@ -346,50 +361,60 @@ static void fault_in(uint64_t addr, int len)
 
 int cvmx_l2c_lock_line(uint64_t addr)
 {
-    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
-    {
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) {
         int shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT;
         uint64_t assoc = cvmx_l2c_get_num_assoc();
-        uint64_t tag = addr >> shift;
-        uint64_t index = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, cvmx_l2c_address_to_index(addr) << CVMX_L2C_IDX_ADDR_SHIFT);
+        uint32_t tag = cvmx_l2c_v2_address_to_tag(addr);
+        uint64_t indext =  cvmx_l2c_address_to_index(addr) << CVMX_L2C_IDX_ADDR_SHIFT;
+        uint64_t index = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, indext);
         uint64_t way;
-        cvmx_l2c_tadx_tag_t l2c_tadx_tag;
+        uint32_t tad;
+        union cvmx_l2c_tadx_tag l2c_tadx_tag;
 
-        CVMX_CACHE_LCKL2(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, addr), 0);
+        if (tag == 0xFFFFFFFF) {
+            cvmx_dprintf("ERROR: cvmx_l2c_lock_line: addr 0x%llx in LMC hole."
+                         "\n", (unsigned long long) addr); 
+            return -1;
+        }
+        
+        tad = cvmx_l2c_address_to_tad(addr);
 
+        /* cvmx_dprintf("shift=%d index=%lx tag=%x\n",shift, index, tag); */
+        CVMX_CACHE_LCKL2(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, addr), 0);
+        CVMX_SYNCW;
         /* Make sure we were able to lock the line */
-        for (way = 0; way < assoc; way++)
-        {
-            CVMX_CACHE_LTGL2I(index | (way << shift), 0);
-            CVMX_SYNC;   // make sure CVMX_L2C_TADX_TAG is updated
-            l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
+        for (way = 0; way < assoc; way++) {
+            uint64_t caddr = index | (way << shift);
+            CVMX_CACHE_LTGL2I(caddr, 0);
+            /* make sure CVMX_L2C_TADX_TAG is updated */
+            CVMX_SYNC;
+            l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(tad));
             if (l2c_tadx_tag.s.valid && l2c_tadx_tag.s.tag == tag)
                 break;
+            /* cvmx_printf("caddr=%lx tad=%d tagu64=%lx valid=%x tag=%x \n", caddr,
+               tad, l2c_tadx_tag.u64, l2c_tadx_tag.s.valid, l2c_tadx_tag.s.tag); */
         }
 
         /* Check if a valid line is found */
-        if (way >= assoc)
-        {
-            //cvmx_dprintf("ERROR: cvmx_l2c_lock_line: line not found for locking at 0x%llx address\n", (unsigned long long)addr);
+        if (way >= assoc) {
+            /* cvmx_dprintf("ERROR: cvmx_l2c_lock_line: line not found for locking at"
+                         " 0x%llx address\n", (unsigned long long)addr); */
             return -1;
         }
 
         /* Check if lock bit is not set */
-        if (!l2c_tadx_tag.s.lock)
-        {
-            //cvmx_dprintf("ERROR: cvmx_l2c_lock_line: Not able to lock at 0x%llx address\n", (unsigned long long)addr);
+        if (!l2c_tadx_tag.s.lock) {
+             /* cvmx_dprintf("ERROR: cvmx_l2c_lock_line: Not able to lock at "
+               "0x%llx address\n", (unsigned long long)addr); */
             return -1;
         }
-
-        return way;
-    }
-    else
-    {
+        return 0;
+    } else {
         int retval = 0;
-        cvmx_l2c_dbg_t l2cdbg;
-        cvmx_l2c_lckbase_t lckbase;
-        cvmx_l2c_lckoff_t lckoff;
-        cvmx_l2t_err_t l2t_err;
+        union cvmx_l2c_dbg l2cdbg;
+        union cvmx_l2c_lckbase lckbase;
+        union cvmx_l2c_lckoff lckoff;
+        union cvmx_l2t_err l2t_err;
 
         cvmx_spinlock_lock(&cvmx_l2c_spinlock);
 
@@ -415,26 +440,25 @@ int cvmx_l2c_lock_line(uint64_t addr)
         cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64);
         cvmx_read_csr(CVMX_L2C_LCKOFF);
 
-        if (((cvmx_l2c_cfg_t)(cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias)
-        {
-            int alias_shift = CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
-            uint64_t addr_tmp = addr ^ (addr & ((1 << alias_shift) - 1)) >> CVMX_L2_SET_BITS;
+        if (((union cvmx_l2c_cfg)(cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) {
+            int alias_shift = CVMX_L2C_IDX_ADDR_SHIFT + 2 * cvmx_l2c_get_set_bits() - 1;
+            uint64_t addr_tmp = addr ^ (addr & ((1 << alias_shift) - 1)) >> cvmx_l2c_get_set_bits();
             lckbase.s.lck_base = addr_tmp >> 7;
-        }
-        else
-        {
+        } else {
             lckbase.s.lck_base = addr >> 7;
         }
 
         lckbase.s.lck_ena = 1;
         cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
-        cvmx_read_csr(CVMX_L2C_LCKBASE);    // Make sure it gets there
+        /* Make sure it gets there */
+        cvmx_read_csr(CVMX_L2C_LCKBASE);
 
         fault_in(addr, CVMX_CACHE_LINE_SIZE);
 
         lckbase.s.lck_ena = 0;
         cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
-        cvmx_read_csr(CVMX_L2C_LCKBASE);    // Make sure it gets there
+        /* Make sure it gets there */
+        cvmx_read_csr(CVMX_L2C_LCKBASE);
 
         /* Stop being debug core */
         cvmx_write_csr(CVMX_L2C_DBG, 0);
@@ -445,11 +469,10 @@ int cvmx_l2c_lock_line(uint64_t addr)
             retval = 1;  /* We were unable to lock the line */
 
         cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
-        return(retval);
+        return retval;
     }
 }
 
-
 int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len)
 {
     int retval = 0;
@@ -459,17 +482,15 @@ int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len)
     start &= ~CVMX_CACHE_LINE_MASK;
     len = (len + CVMX_CACHE_LINE_MASK) & ~CVMX_CACHE_LINE_MASK;
 
-    while (len)
-    {
-        retval += cvmx_l2c_lock_line(start);
+    while (len) {
+        if (cvmx_l2c_lock_line(start) != 0)
+            retval--;
         start += CVMX_CACHE_LINE_SIZE;
         len -= CVMX_CACHE_LINE_SIZE;
     }
-
-    return(retval);
+    return retval;
 }
 
-
 void cvmx_l2c_flush(void)
 {
     uint64_t assoc, set;
@@ -478,74 +499,64 @@ void cvmx_l2c_flush(void)
     n_set = cvmx_l2c_get_num_sets();
     n_assoc = cvmx_l2c_get_num_assoc();
 
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
-    {
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) {
         uint64_t address;
         /* These may look like constants, but they aren't... */
         int assoc_shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT;
         int set_shift = CVMX_L2C_IDX_ADDR_SHIFT;
-        for (set=0; set < n_set; set++)
-        {
-            for(assoc=0; assoc < n_assoc; assoc++)
-            {
+        for (set = 0; set < n_set; set++) {
+            for (assoc = 0; assoc < n_assoc; assoc++) {
                 address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                       (assoc << assoc_shift) |
-                                       (set << set_shift));
+                               (assoc << assoc_shift) |    (set << set_shift));
                 CVMX_CACHE_WBIL2I(address, 0);
             }
         }
-    }
-    else
-    {
-        for (set=0; set < n_set; set++)
-            for(assoc=0; assoc < n_assoc; assoc++)
+    } else {
+        for (set = 0; set < n_set; set++)
+            for (assoc = 0; assoc < n_assoc; assoc++)
                 cvmx_l2c_flush_line(assoc, set);
     }
 }
 
-
 int cvmx_l2c_unlock_line(uint64_t address)
 {
+    uint32_t tad = cvmx_l2c_address_to_tad(address);
 
-    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
-    {
-        int assoc;         cvmx_l2c_tag_t tag;
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) {
+        int assoc;
+        union cvmx_l2c_tag tag;
         uint32_t tag_addr;
         uint32_t index = cvmx_l2c_address_to_index(address);
 
         tag_addr = ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
 
-        /* For 63XX, we can flush a line by using the physical address directly,
-        ** so finding the cache line used by the address is only required to provide
-        ** the proper return value for the function.
-        */
-        for(assoc = 0; assoc < CVMX_L2_ASSOC; assoc++)
-        {
-            tag = cvmx_l2c_get_tag(assoc, index);
+        /*
+         * For OcteonII, we can flush a line by using the physical
+         * address directly, so finding the cache line used by
+         * the address is only required to provide the proper
+         * return value for the function.
+         */
+        for (assoc = 0; assoc < cvmx_l2c_get_num_assoc(); assoc++) {
+            tag = cvmx_l2c_get_tag_v2(assoc, index, tad);
 
-            if (tag.s.V && (tag.s.addr == tag_addr))
-            {
+            if (tag.s.V && (tag.s.addr == tag_addr)) {
                 CVMX_CACHE_WBIL2(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, address), 0);
                 return tag.s.L;
             }
         }
-    }
-    else
-    {
+    } else {
         int assoc;
-        cvmx_l2c_tag_t tag;
+        union cvmx_l2c_tag tag;
         uint32_t tag_addr;
 
         uint32_t index = cvmx_l2c_address_to_index(address);
 
         /* Compute portion of address that is stored in tag */
         tag_addr = ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
-        for(assoc = 0; assoc < CVMX_L2_ASSOC; assoc++)
-        {
-            tag = cvmx_l2c_get_tag(assoc, index);
+        for (assoc = 0; assoc < cvmx_l2c_get_num_assoc(); assoc++) {
+            tag = cvmx_l2c_get_tag_v2(assoc, index, tad);
 
-            if (tag.s.V && (tag.s.addr == tag_addr))
-            {
+            if (tag.s.V && (tag.s.addr == tag_addr)) {
                 cvmx_l2c_flush_line(assoc, index);
                 return tag.s.L;
             }
@@ -561,8 +572,7 @@ int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len)
     len += start & CVMX_CACHE_LINE_MASK;
     start &= ~CVMX_CACHE_LINE_MASK;
     len = (len + CVMX_CACHE_LINE_MASK) & ~CVMX_CACHE_LINE_MASK;
-    while (len > 0)
-    {
+    while (len > 0) {
         num_unlocked += cvmx_l2c_unlock_line(start);
         start += CVMX_CACHE_LINE_SIZE;
         len -= CVMX_CACHE_LINE_SIZE;
@@ -571,62 +581,98 @@ int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len)
     return num_unlocked;
 }
 
-
-/* Internal l2c tag types.  These are converted to a generic structure
-** that can be used on all chips */
-typedef union
-{
+/*
+ * Internal l2c tag types.  These are converted to a generic structure
+ * that can be used on all chips.
+ */
+union __cvmx_l2c_tag {
     uint64_t u64;
-#if __BYTE_ORDER == __BIG_ENDIAN
-    struct cvmx_l2c_tag_cn50xx
-    {
-	uint64_t reserved		: 40;
-	uint64_t V			: 1;	// Line valid
-	uint64_t D			: 1;	// Line dirty
-	uint64_t L			: 1;	// Line locked
-	uint64_t U			: 1;	// Use, LRU eviction
-	uint64_t addr			: 20;	// Phys mem addr (33..14)
+#ifdef __BIG_ENDIAN_BITFIELD
+    struct cvmx_l2c_tag_cn50xx {
+        uint64_t reserved:40;
+        uint64_t V:1;        /* Line valid */
+        uint64_t D:1;        /* Line dirty */
+        uint64_t L:1;        /* Line locked */
+        uint64_t U:1;        /* Use, LRU eviction */
+        uint64_t addr:20;    /* Phys mem addr (33..14) */
     } cn50xx;
-    struct cvmx_l2c_tag_cn30xx
-    {
-	uint64_t reserved		: 41;
-	uint64_t V			: 1;	// Line valid
-	uint64_t D			: 1;	// Line dirty
-	uint64_t L			: 1;	// Line locked
-	uint64_t U			: 1;	// Use, LRU eviction
-	uint64_t addr			: 19;	// Phys mem addr (33..15)
+    struct cvmx_l2c_tag_cn30xx {
+        uint64_t reserved:41;
+        uint64_t V:1;        /* Line valid */
+        uint64_t D:1;        /* Line dirty */
+        uint64_t L:1;        /* Line locked */
+        uint64_t U:1;        /* Use, LRU eviction */
+        uint64_t addr:19;    /* Phys mem addr (33..15) */
     } cn30xx;
-    struct cvmx_l2c_tag_cn31xx
-    {
-	uint64_t reserved		: 42;
-	uint64_t V			: 1;	// Line valid
-	uint64_t D			: 1;	// Line dirty
-	uint64_t L			: 1;	// Line locked
-	uint64_t U			: 1;	// Use, LRU eviction
-	uint64_t addr			: 18;	// Phys mem addr (33..16)
+    struct cvmx_l2c_tag_cn31xx {
+        uint64_t reserved:42;
+        uint64_t V:1;        /* Line valid */
+        uint64_t D:1;        /* Line dirty */
+        uint64_t L:1;        /* Line locked */
+        uint64_t U:1;        /* Use, LRU eviction */
+        uint64_t addr:18;    /* Phys mem addr (33..16) */
     } cn31xx;
-    struct cvmx_l2c_tag_cn38xx
-    {
-	uint64_t reserved		: 43;
-	uint64_t V			: 1;	// Line valid
-	uint64_t D			: 1;	// Line dirty
-	uint64_t L			: 1;	// Line locked
-	uint64_t U			: 1;	// Use, LRU eviction
-	uint64_t addr			: 17;	// Phys mem addr (33..17)
+    struct cvmx_l2c_tag_cn38xx {
+        uint64_t reserved:43;
+        uint64_t V:1;        /* Line valid */
+        uint64_t D:1;        /* Line dirty */
+        uint64_t L:1;        /* Line locked */
+        uint64_t U:1;        /* Use, LRU eviction */
+        uint64_t addr:17;    /* Phys mem addr (33..17) */
     } cn38xx;
-    struct cvmx_l2c_tag_cn58xx
-    {
-	uint64_t reserved		: 44;
-	uint64_t V			: 1;	// Line valid
-	uint64_t D			: 1;	// Line dirty
-	uint64_t L			: 1;	// Line locked
-	uint64_t U			: 1;	// Use, LRU eviction
-	uint64_t addr			: 16;	// Phys mem addr (33..18)
+    struct cvmx_l2c_tag_cn58xx {
+        uint64_t reserved:44;
+        uint64_t V:1;        /* Line valid */
+        uint64_t D:1;        /* Line dirty */
+        uint64_t L:1;        /* Line locked */
+        uint64_t U:1;        /* Use, LRU eviction */
+        uint64_t addr:16;    /* Phys mem addr (33..18) */
+    } cn58xx;
+#else
+    struct cvmx_l2c_tag_cn50xx {
+        uint64_t addr:20;    /* Phys mem addr (33..14) */
+        uint64_t U:1;        /* Use, LRU eviction */
+        uint64_t L:1;        /* Line locked */
+        uint64_t D:1;        /* Line dirty */
+        uint64_t V:1;        /* Line valid */
+        uint64_t reserved:40;
+    } cn50xx;
+    struct cvmx_l2c_tag_cn30xx {
+        uint64_t addr:19;    /* Phys mem addr (33..15) */
+        uint64_t U:1;        /* Use, LRU eviction */
+        uint64_t L:1;        /* Line locked */
+        uint64_t D:1;        /* Line dirty */
+        uint64_t V:1;        /* Line valid */
+        uint64_t reserved:41;
+    } cn30xx;
+    struct cvmx_l2c_tag_cn31xx {
+        uint64_t addr:18;    /* Phys mem addr (33..16) */
+        uint64_t U:1;        /* Use, LRU eviction */
+        uint64_t L:1;        /* Line locked */
+        uint64_t D:1;        /* Line dirty */
+        uint64_t V:1;        /* Line valid */
+        uint64_t reserved:42;
+    } cn31xx;
+    struct cvmx_l2c_tag_cn38xx {
+        uint64_t addr:17;    /* Phys mem addr (33..17) */
+        uint64_t U:1;        /* Use, LRU eviction */
+        uint64_t L:1;        /* Line locked */
+        uint64_t D:1;        /* Line dirty */
+        uint64_t V:1;        /* Line valid */
+        uint64_t reserved:43;
+    } cn38xx;
+    struct cvmx_l2c_tag_cn58xx {
+        uint64_t addr:16;    /* Phys mem addr (33..18) */
+        uint64_t U:1;        /* Use, LRU eviction */
+        uint64_t L:1;        /* Line locked */
+        uint64_t D:1;        /* Line dirty */
+        uint64_t V:1;        /* Line valid */
+        uint64_t reserved:44;
     } cn58xx;
-    struct cvmx_l2c_tag_cn58xx   cn56xx; /* 2048 sets */
-    struct cvmx_l2c_tag_cn31xx   cn52xx; /* 512 sets */
 #endif
-} __cvmx_l2c_tag_t;
+    struct cvmx_l2c_tag_cn58xx cn56xx;    /* 2048 sets */
+    struct cvmx_l2c_tag_cn31xx cn52xx;    /* 512 sets */
+};
 
 
 /**
@@ -638,186 +684,305 @@ typedef union
  * @param assoc  Association (way) of the tag to dump
  * @param index  Index of the cacheline
  *
- * @return The Octeon model specific tag structure.  This is translated by a wrapper
- *         function to a generic form that is easier for applications to use.
+ * @return The Octeon model specific tag structure.  This is
+ *         translated by a wrapper function to a generic form that is
+ *         easier for applications to use.
  */
-static __cvmx_l2c_tag_t __read_l2_tag(uint64_t assoc, uint64_t index)
+static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
 {
 
     uint64_t debug_tag_addr = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, (index << 7) + 96);
     uint64_t core = cvmx_get_core_num();
-    __cvmx_l2c_tag_t tag_val;
+    union __cvmx_l2c_tag tag_val;
     uint64_t dbg_addr = CVMX_L2C_DBG;
     unsigned long flags;
 
-    cvmx_l2c_dbg_t debug_val;
+    union cvmx_l2c_dbg debug_val;
     debug_val.u64 = 0;
-    /* For low core count parts, the core number is always small enough
-    ** to stay in the correct field and not set any reserved bits */
+    /*
+     * For low core count parts, the core number is always small
+     * enough to stay in the correct field and not set any
+     * reserved bits.
+     */
     debug_val.s.ppnum = core;
     debug_val.s.l2t = 1;
     debug_val.s.set = assoc;
 
-    CVMX_SYNC;  /* Make sure core is quiet (no prefetches, etc.) before entering debug mode */
-    CVMX_DCACHE_INVALIDATE;  /* Flush L1 to make sure debug load misses L1 */
-
     cvmx_local_irq_save(flags);
+    /*
+     * Make sure core is quiet (no prefetches, etc.) before
+     * entering debug mode.
+     */
+    CVMX_SYNC;
+    /* Flush L1 to make sure debug load misses L1 */
+    CVMX_DCACHE_INVALIDATE;
+
+    /*
+     * The following must be done in assembly as when in debug
+     * mode all data loads from L2 return special debug data, not
+     * normal memory contents.  Also, interrupts must be disabled,
+     * since if an interrupt occurs while in debug mode the ISR
+     * will get debug data from all its memory * reads instead of
+     * the contents of memory.
+     */
 
-    /* The following must be done in assembly as when in debug mode all data loads from
-    ** L2 return special debug data, not normal memory contents.  Also, interrupts must be disabled,
-    ** since if an interrupt occurs while in debug mode the ISR will get debug data from all its memory
-    ** reads instead of the contents of memory */
-
-        asm volatile (
-    "        .set push              \n"
-    "        .set mips64              \n"
-    "        .set noreorder           \n"
-    "        sd    %[dbg_val], 0(%[dbg_addr])  \n"   /* Enter debug mode, wait for store */
-    "        ld    $0, 0(%[dbg_addr]) \n"
-    "        ld    %[tag_val], 0(%[tag_addr]) \n"   /* Read L2C tag data */
-    "        sd    $0, 0(%[dbg_addr])  \n"          /* Exit debug mode, wait for store */
-    "        ld    $0, 0(%[dbg_addr]) \n"
-    "        cache 9, 0($0) \n"             /* Invalidate dcache to discard debug data */
-    "        .set pop             \n"
-    :[tag_val] "=r" (tag_val):  [dbg_addr] "r" (dbg_addr), [dbg_val] "r" (debug_val), [tag_addr] "r" (debug_tag_addr) : "memory");
+    asm volatile (
+        ".set push\n\t"
+        ".set mips64\n\t"
+        ".set noreorder\n\t"
+        "sd    %[dbg_val], 0(%[dbg_addr])\n\t"   /* Enter debug mode, wait for store */
+        "ld    $0, 0(%[dbg_addr])\n\t"
+        "ld    %[tag_val], 0(%[tag_addr])\n\t"   /* Read L2C tag data */
+        "sd    $0, 0(%[dbg_addr])\n\t"          /* Exit debug mode, wait for store */
+        "ld    $0, 0(%[dbg_addr])\n\t"
+        "cache 9, 0($0)\n\t"             /* Invalidate dcache to discard debug data */
+        ".set pop"
+        : [tag_val] "=r" (tag_val)
+        : [dbg_addr] "r" (dbg_addr), [dbg_val] "r" (debug_val), [tag_addr] "r" (debug_tag_addr)
+        : "memory");
 
     cvmx_local_irq_restore(flags);
 
-    return(tag_val);
-
+    return tag_val;
 }
 
 
-cvmx_l2c_tag_t cvmx_l2c_get_tag(uint32_t association, uint32_t index)
+union cvmx_l2c_tag cvmx_l2c_get_tag_v2(uint32_t association, uint32_t index, uint32_t tad)
 {
-    cvmx_l2c_tag_t tag;
+    union cvmx_l2c_tag tag;
     tag.u64 = 0;
 
-    if ((int)association >= cvmx_l2c_get_num_assoc())
-    {
+    if ((int)association >= cvmx_l2c_get_num_assoc()) {
         cvmx_dprintf("ERROR: cvmx_l2c_get_tag association out of range\n");
-        return(tag);
+        return tag;
     }
-    if ((int)index >= cvmx_l2c_get_num_sets())
-    {
-        cvmx_dprintf("ERROR: cvmx_l2c_get_tag index out of range (arg: %d, max: %d)\n", (int)index, cvmx_l2c_get_num_sets());
-        return(tag);
+    if ((int)index >= cvmx_l2c_get_num_sets()) {
+        cvmx_dprintf("ERROR: cvmx_l2c_get_tag index out of range (arg: %d, max: %d)\n",
+                 (int)index, cvmx_l2c_get_num_sets());
+        return tag;
     }
-    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
-    {
-        cvmx_l2c_tadx_tag_t l2c_tadx_tag;
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) {
+        union cvmx_l2c_tadx_tag l2c_tadx_tag;
         uint64_t address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                        (association << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) |
-                                        (index << CVMX_L2C_IDX_ADDR_SHIFT));
-        /* Use L2 cache Index load tag cache instruction, as hardware loads
-           the virtual tag for the L2 cache block with the contents of
-           L2C_TAD0_TAG register. */
+                        (association << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) |
+                        (index << CVMX_L2C_IDX_ADDR_SHIFT));
+        /*
+         * Use L2 cache Index load tag cache instruction, as
+         * hardware loads the virtual tag for the L2 cache
+         * block with the contents of L2C_TAD0_TAG
+         * register.
+         */
+        if (tad > CVMX_L2C_TADS) {
+            cvmx_dprintf("ERROR: cvmx_l2c_get_tag_v2: TAD#%d out of range\n", (unsigned int)tad);
+            return tag;
+        }
         CVMX_CACHE_LTGL2I(address, 0);
-        CVMX_SYNC;   // make sure CVMX_L2C_TADX_TAG is updated
-        l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
+        CVMX_SYNC;   /* make sure CVMX_L2C_TADX_TAG is updated */
+        l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(tad));
 
         tag.s.V     = l2c_tadx_tag.s.valid;
         tag.s.D     = l2c_tadx_tag.s.dirty;
         tag.s.L     = l2c_tadx_tag.s.lock;
         tag.s.U     = l2c_tadx_tag.s.use;
         tag.s.addr  = l2c_tadx_tag.s.tag;
-    }
-    else
-    {
-        __cvmx_l2c_tag_t tmp_tag;
+    } else {
+        union __cvmx_l2c_tag tmp_tag;
         /* __read_l2_tag is intended for internal use only */
         tmp_tag = __read_l2_tag(association, index);
 
-        /* Convert all tag structure types to generic version, as it can represent all models */
-        if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))
-        {
+        /*
+         * Convert all tag structure types to generic version,
+         * as it can represent all models.
+         */
+        if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
             tag.s.V    = tmp_tag.cn58xx.V;
             tag.s.D    = tmp_tag.cn58xx.D;
             tag.s.L    = tmp_tag.cn58xx.L;
             tag.s.U    = tmp_tag.cn58xx.U;
             tag.s.addr = tmp_tag.cn58xx.addr;
-        }
-        else if (OCTEON_IS_MODEL(OCTEON_CN38XX))
-        {
+        } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
             tag.s.V    = tmp_tag.cn38xx.V;
             tag.s.D    = tmp_tag.cn38xx.D;
             tag.s.L    = tmp_tag.cn38xx.L;
             tag.s.U    = tmp_tag.cn38xx.U;
             tag.s.addr = tmp_tag.cn38xx.addr;
-        }
-        else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
-        {
+        } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
             tag.s.V    = tmp_tag.cn31xx.V;
             tag.s.D    = tmp_tag.cn31xx.D;
             tag.s.L    = tmp_tag.cn31xx.L;
             tag.s.U    = tmp_tag.cn31xx.U;
             tag.s.addr = tmp_tag.cn31xx.addr;
-        }
-        else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
-        {
+        } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
             tag.s.V    = tmp_tag.cn30xx.V;
             tag.s.D    = tmp_tag.cn30xx.D;
             tag.s.L    = tmp_tag.cn30xx.L;
             tag.s.U    = tmp_tag.cn30xx.U;
             tag.s.addr = tmp_tag.cn30xx.addr;
-        }
-        else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
-        {
+        } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
             tag.s.V    = tmp_tag.cn50xx.V;
             tag.s.D    = tmp_tag.cn50xx.D;
             tag.s.L    = tmp_tag.cn50xx.L;
             tag.s.U    = tmp_tag.cn50xx.U;
             tag.s.addr = tmp_tag.cn50xx.addr;
-        }
-        else
-        {
-            cvmx_dprintf("Unsupported OCTEON Model in %s\n", __FUNCTION__);
+        } else {
+            cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
         }
     }
-
     return tag;
 }
 
+union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index)
+{
+    union cvmx_l2c_tag tag;
+    tag.u64 = 0;
+
+    if ((int)association >= cvmx_l2c_get_num_assoc()) {
+        cvmx_dprintf("ERROR: cvmx_l2c_get_tag association out of range\n");
+        return tag;
+    }
+    if ((int)index >= cvmx_l2c_get_num_sets()) {
+        cvmx_dprintf("ERROR: cvmx_l2c_get_tag index out of range (arg: %d, max: %d)\n",
+                 (int)index, cvmx_l2c_get_num_sets());
+        return tag;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) {
+        union cvmx_l2c_tadx_tag l2c_tadx_tag;
+        uint64_t address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                        (association << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) |
+                        (index << CVMX_L2C_IDX_ADDR_SHIFT));
+        if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
+            cvmx_dprintf("ERROR: Cannot use %s on OCTEON CN68XX, use cvmx_l2c_get_tag_v2 instead!\n",
+                     __func__);
+            return tag;
+        }
+        /*
+         * Use L2 cache Index load tag cache instruction, as
+         * hardware loads the virtual tag for the L2 cache
+         * block with the contents of L2C_TAD0_TAG
+         * register.
+         */
+        CVMX_CACHE_LTGL2I(address, 0);
+        CVMX_SYNC;   /* make sure CVMX_L2C_TADX_TAG is updated */
+        l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
+
+        tag.s.V     = l2c_tadx_tag.s.valid;
+        tag.s.D     = l2c_tadx_tag.s.dirty;
+        tag.s.L     = l2c_tadx_tag.s.lock;
+        tag.s.U     = l2c_tadx_tag.s.use;
+        tag.s.addr  = l2c_tadx_tag.s.tag;
+    } else {
+        union __cvmx_l2c_tag tmp_tag;
+        /* __read_l2_tag is intended for internal use only */
+        tmp_tag = __read_l2_tag(association, index);
+
+        /*
+         * Convert all tag structure types to generic version,
+         * as it can represent all models.
+         */
+        if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
+            tag.s.V    = tmp_tag.cn58xx.V;
+            tag.s.D    = tmp_tag.cn58xx.D;
+            tag.s.L    = tmp_tag.cn58xx.L;
+            tag.s.U    = tmp_tag.cn58xx.U;
+            tag.s.addr = tmp_tag.cn58xx.addr;
+        } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
+            tag.s.V    = tmp_tag.cn38xx.V;
+            tag.s.D    = tmp_tag.cn38xx.D;
+            tag.s.L    = tmp_tag.cn38xx.L;
+            tag.s.U    = tmp_tag.cn38xx.U;
+            tag.s.addr = tmp_tag.cn38xx.addr;
+        } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
+            tag.s.V    = tmp_tag.cn31xx.V;
+            tag.s.D    = tmp_tag.cn31xx.D;
+            tag.s.L    = tmp_tag.cn31xx.L;
+            tag.s.U    = tmp_tag.cn31xx.U;
+            tag.s.addr = tmp_tag.cn31xx.addr;
+        } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
+            tag.s.V    = tmp_tag.cn30xx.V;
+            tag.s.D    = tmp_tag.cn30xx.D;
+            tag.s.L    = tmp_tag.cn30xx.L;
+            tag.s.U    = tmp_tag.cn30xx.U;
+            tag.s.addr = tmp_tag.cn30xx.addr;
+        } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
+            tag.s.V    = tmp_tag.cn50xx.V;
+            tag.s.D    = tmp_tag.cn50xx.D;
+            tag.s.L    = tmp_tag.cn50xx.L;
+            tag.s.U    = tmp_tag.cn50xx.U;
+            tag.s.addr = tmp_tag.cn50xx.addr;
+        } else {
+            cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
+        }
+    }
+    return tag;
+}
 #endif
 
-uint32_t cvmx_l2c_address_to_index (uint64_t addr)
+int cvmx_l2c_address_to_tad(uint64_t addr)
+{
+    uint32_t tad;
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
+        cvmx_l2c_ctl_t l2c_ctl;
+        l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);
+        if (!l2c_ctl.s.disidxalias) {
+            tad = ((addr >> 7) ^ (addr >> 12) ^ (addr >> 18)) & 3;
+        } else {
+            tad = (addr >> 7) & 3;
+        }
+    } else {
+        tad = 0;
+    }
+    return tad;
+}
+
+uint32_t cvmx_l2c_v2_address_to_tag(uint64_t addr)
+{
+#define DR0_END   ( (256 * 1024 * 1024) -1)
+#define DR1_START (512 * 1024 * 1024)
+#define L2_HOLE   (256 * 1024 * 1024)
+
+    if ( (addr > DR0_END) && (addr < DR1_START) ) return (uint32_t) (-1);
+    if (addr > DR1_START) addr = addr - L2_HOLE ;
+    addr = addr & 0x7FFFFFFFFULL;
+    return (uint32_t )(addr >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT);
+}
+
+uint32_t cvmx_l2c_address_to_index(uint64_t addr)
 {
     uint64_t idx = addr >> CVMX_L2C_IDX_ADDR_SHIFT;
     int indxalias = 0;
 
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
-    {
-        cvmx_l2c_ctl_t l2c_ctl;
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) {
+        union cvmx_l2c_ctl l2c_ctl;
         l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);
         indxalias = !l2c_ctl.s.disidxalias;
-    }
-    else
-    {
-        cvmx_l2c_cfg_t l2c_cfg;
+    } else {
+        union cvmx_l2c_cfg l2c_cfg;
         l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
         indxalias = l2c_cfg.s.idxalias;
     }
 
-    if (indxalias)
-    {
-        if (OCTEON_IS_MODEL(OCTEON_CN63XX))
-        {
+    if (indxalias) {
+        if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
+            uint32_t a_14_12 = (idx / (CVMX_L2C_MEMBANK_SELECT_SIZE/(1<<CVMX_L2C_IDX_ADDR_SHIFT))) & 0x7;
+            idx ^= (idx / cvmx_l2c_get_num_sets()) & 0x3ff;
+            idx ^= a_14_12 & 0x3;
+            idx ^= a_14_12 << 2; 
+        } else if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) {
             uint32_t a_14_12 = (idx / (CVMX_L2C_MEMBANK_SELECT_SIZE/(1<<CVMX_L2C_IDX_ADDR_SHIFT))) & 0x7;
             idx ^= idx / cvmx_l2c_get_num_sets();
             idx ^= a_14_12;
-        }
-        else
-        {
+        } else {
             idx ^= ((addr & CVMX_L2C_ALIAS_MASK) >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT);
         }
     }
     idx &= CVMX_L2C_IDX_MASK;
-    return(idx);
+    return idx;
 }
 
 int cvmx_l2c_get_cache_size_bytes(void)
 {
-    return (cvmx_l2c_get_num_sets() * cvmx_l2c_get_num_assoc() * CVMX_CACHE_LINE_SIZE);
+    return cvmx_l2c_get_num_sets() * cvmx_l2c_get_num_assoc() *
+        CVMX_CACHE_LINE_SIZE;
 }
 
 /**
@@ -827,30 +992,27 @@ int cvmx_l2c_get_cache_size_bytes(void)
 int cvmx_l2c_get_set_bits(void)
 {
     int l2_set_bits;
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX) ||
-        OCTEON_IS_MODEL(OCTEON_CN58XX))
-        l2_set_bits =  11; /* 2048 sets */
-    else if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
-        l2_set_bits =  10; /* 1024 sets */
-    else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
-        l2_set_bits =  9; /* 512 sets */
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
+        l2_set_bits = 11;    /* 2048 sets */
+    else if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))
+        l2_set_bits = 10;    /* 1024 sets */
+    else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
+        l2_set_bits = 9;    /* 512 sets */
     else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
-        l2_set_bits =  8; /* 256 sets */
+        l2_set_bits = 8;    /* 256 sets */
     else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
-        l2_set_bits =  7; /* 128 sets */
-    else
-    {
-        cvmx_dprintf("Unsupported OCTEON Model in %s\n", __FUNCTION__);
-        l2_set_bits =  11; /* 2048 sets */
+        l2_set_bits = 7;    /* 128 sets */
+    else {
+        cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
+        l2_set_bits = 11;    /* 2048 sets */
     }
-    return(l2_set_bits);
-
+    return l2_set_bits;
 }
 
 /* Return the number of sets in the L2 Cache */
 int cvmx_l2c_get_num_sets(void)
 {
-    return (1 << cvmx_l2c_get_set_bits());
+    return 1 << cvmx_l2c_get_set_bits();
 }
 
 /* Return the number of associations in the L2 Cache */
@@ -862,58 +1024,57 @@ int cvmx_l2c_get_num_assoc(void)
         OCTEON_IS_MODEL(OCTEON_CN58XX) ||
         OCTEON_IS_MODEL(OCTEON_CN50XX) ||
         OCTEON_IS_MODEL(OCTEON_CN38XX))
-        l2_assoc =  8;
-    else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
-        l2_assoc =  16;
+        l2_assoc = 8;
+    else if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
+        l2_assoc = 16;
     else if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
-             OCTEON_IS_MODEL(OCTEON_CN30XX))
-        l2_assoc =  4;
-    else
-    {
-        cvmx_dprintf("Unsupported OCTEON Model in %s\n", __FUNCTION__);
-        l2_assoc =  8;
+         OCTEON_IS_MODEL(OCTEON_CN30XX))
+        l2_assoc = 4;
+    else {
+        cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
+        l2_assoc = 8;
     }
 
     /* Check to see if part of the cache is disabled */
-    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
-    {
-        cvmx_mio_fus_dat3_t mio_fus_dat3;
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) {
+        union cvmx_mio_fus_dat3 mio_fus_dat3;
 
         mio_fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
-        /* cvmx_mio_fus_dat3.s.l2c_crip fuses map as follows
-           <2> will be not used for 63xx
-           <1> disables 1/2 ways
-           <0> disables 1/4 ways
-           They are cumulative, so for 63xx:
-           <1> <0>
-           0 0 16-way 2MB cache
-           0 1 12-way 1.5MB cache
-           1 0 8-way 1MB cache
-           1 1 4-way 512KB cache */
-
-        if (mio_fus_dat3.s.l2c_crip == 3)
+        /*
+         * cvmx_mio_fus_dat3.s.l2c_crip fuses map as follows
+         * <2> will be not used for 63xx
+         * <1> disables 1/2 ways
+         * <0> disables 1/4 ways
+         * They are cumulative, so for 63xx:
+         * <1> <0>
+         * 0 0 16-way 2MB cache
+         * 0 1 12-way 1.5MB cache
+         * 1 0 8-way 1MB cache
+         * 1 1 4-way 512KB cache
+         */
+
+        if (mio_fus_dat3.cn63xx.l2c_crip == 3)
             l2_assoc = 4;
-        else if (mio_fus_dat3.s.l2c_crip == 2)
+        else if (mio_fus_dat3.cn63xx.l2c_crip == 2)
             l2_assoc = 8;
-        else if (mio_fus_dat3.s.l2c_crip == 1)
+        else if (mio_fus_dat3.cn63xx.l2c_crip == 1)
             l2_assoc = 12;
-    }
-    else
-    {
-        cvmx_l2d_fus3_t val;
+    } else {
+        union cvmx_l2d_fus3 val;
         val.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
-        /* Using shifts here, as bit position names are different for
-           each model but they all mean the same. */
+        /*
+         * Using shifts here, as bit position names are
+         * different for each model but they all mean the
+         * same.
+         */
         if ((val.u64 >> 35) & 0x1)
             l2_assoc = l2_assoc >> 2;
         else if ((val.u64 >> 34) & 0x1)
             l2_assoc = l2_assoc >> 1;
     }
-
-    return(l2_assoc);
+    return l2_assoc;
 }
 
-
 #ifndef CVMX_BUILD_FOR_LINUX_HOST
 /**
  * Flush a line from the L2 cache
@@ -926,34 +1087,30 @@ int cvmx_l2c_get_num_assoc(void)
 void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index)
 {
     /* Check the range of the index. */
-    if (index > (uint32_t)cvmx_l2c_get_num_sets())
-    {
+    if (index > (uint32_t)cvmx_l2c_get_num_sets()) {
         cvmx_dprintf("ERROR: cvmx_l2c_flush_line index out of range.\n");
         return;
     }
 
     /* Check the range of association. */
-    if (assoc > (uint32_t)cvmx_l2c_get_num_assoc())
-    {
+    if (assoc > (uint32_t)cvmx_l2c_get_num_assoc()) {
         cvmx_dprintf("ERROR: cvmx_l2c_flush_line association out of range.\n");
         return;
     }
 
-    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
-    {
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) {
         uint64_t address;
         /* Create the address based on index and association.
-           Bits<20:17> select the way of the cache block involved in
-                       the operation
-           Bits<16:7> of the effect address select the index */
+         * Bits<20:17> select the way of the cache block involved in
+         *             the operation
+         * Bits<16:7> of the effect address select the index
+         */
         address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                               (assoc << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) |
-                               (index << CVMX_L2C_IDX_ADDR_SHIFT));
+                (assoc << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) |
+                (index << CVMX_L2C_IDX_ADDR_SHIFT));
         CVMX_CACHE_WBIL2I(address, 0);
-    }
-    else
-    {
-        cvmx_l2c_dbg_t l2cdbg;
+    } else {
+        union cvmx_l2c_dbg l2cdbg;
 
         l2cdbg.u64 = 0;
         if (!OCTEON_IS_MODEL(OCTEON_CN30XX))
@@ -962,13 +1119,17 @@ void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index)
 
         l2cdbg.s.set = assoc;
         cvmx_spinlock_lock(&cvmx_l2c_spinlock);
-        /* Enter debug mode, and make sure all other writes complete before we
-        ** enter debug mode */
+        /*
+         * Enter debug mode, and make sure all other writes
+         * complete before we enter debug mode
+         */
         CVMX_SYNC;
         cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
         cvmx_read_csr(CVMX_L2C_DBG);
 
-        CVMX_PREPARE_FOR_STORE (CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, index*CVMX_CACHE_LINE_SIZE), 0);
+        CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                            index * CVMX_CACHE_LINE_SIZE),
+                       0);
         /* Exit debug mode */
         CVMX_SYNC;
         cvmx_write_csr(CVMX_L2C_DBG, 0);
@@ -978,15 +1139,64 @@ void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index)
 }
 #endif
 
-#ifndef CVMX_BUILD_FOR_LINUX_HOST
+/**
+ * Initialize the BIG address in L2C+DRAM to generate proper error
+ * on reading/writing to an non-existant memory location. 
+ *
+ * @param mem_size  Amount of DRAM configured in MB.
+ * @param mode      Allow/Disallow reporting errors L2C_INT_SUM[BIGRD,BIGWR].
+ */
+void cvmx_l2c_set_big_size(uint64_t mem_size, int mode)
+{
+    if ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
+         && !OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+    {
+        cvmx_l2c_big_ctl_t big_ctl;
+        int bits = 0, zero_bits = 0;
+        uint64_t mem;
+
+        if (mem_size > (CVMX_L2C_MAX_MEMSZ_ALLOWED * 1024))
+        {
+            cvmx_dprintf("WARNING: Invalid memory size(%lld) requested, should be <= %lld\n",
+                (unsigned long long)mem_size, (unsigned long long)CVMX_L2C_MAX_MEMSZ_ALLOWED * 1024);
+            mem_size = CVMX_L2C_MAX_MEMSZ_ALLOWED * 1024;
+        }
 
+        mem = mem_size;
+        while (mem)
+        {
+            if ((mem & 1) == 0)
+                zero_bits++;
+            bits++;
+            mem >>= 1;
+        }
+
+        if ((bits - zero_bits) != 1 || (bits - 9) <= 0)
+        {
+            cvmx_dprintf("ERROR: Invalid DRAM size (%lld) requested, refer to L2C_BIG_CTL[maxdram] for valid options.\n", (unsigned long long)mem_size);
+            return;
+        }
+
+        big_ctl.u64 = 0;
+        big_ctl.s.maxdram = bits - 9;
+        big_ctl.s.disable = mode;
+        cvmx_write_csr(CVMX_L2C_BIG_CTL, big_ctl.u64);
+    }
+}
+
+#if !defined(CVMX_BUILD_FOR_LINUX_HOST) && !defined(CVMX_BUILD_FOR_LINUX_KERNEL)
 /* L2C Virtualization APIs. These APIs are based on Octeon II documentation. */
 
+/*
+ * These could be used by the Linux kernel, but currently are not, so
+ * disable them to save space.
+ */
+
 /**
  * @INTERNAL
  * Helper function to decode VALUE to number of allowed virtualization IDS.
  * Returns L2C_VRT_CTL[NUMID].
- * 
+ *
  * @param nvid     Number of virtual Ids.
  * @return         On success decode to NUMID, or to -1 on failure.
  */
@@ -995,59 +1205,57 @@ static inline int __cvmx_l2c_vrt_decode_numid(int nvid)
     int bits = -1;
     int zero_bits = -1;
 
-    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
-    {
-        if (nvid < 1 || nvid > CVMX_L2C_VRT_MAX_VIRTID_ALLOWED)
-        {
-            cvmx_dprintf("WARNING: Invalid number of virtual ids(%d) requested, should be <= 64\n", nvid);
-            return bits;
-        }
+    if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
+        return -1;
 
-        while (nvid)
-        {
-           if ((nvid & 1) == 0)
-              zero_bits++;
+    if (nvid < 1 || nvid > CVMX_L2C_VRT_MAX_VIRTID_ALLOWED) {
+        cvmx_dprintf("WARNING: Invalid number of virtual ids(%d) requested, should be <= 64\n",
+                 nvid);
+        return bits;
+    }
 
-            bits++;
-            nvid >>= 1;
-        }
+    while (nvid) {
+        if ((nvid & 1) == 0)
+            zero_bits++;
 
-        if (bits == 1 || (zero_bits && ((bits - zero_bits) == 1)))
-            return zero_bits;
+        bits++;
+        nvid >>= 1;
     }
+
+    if (bits == 1 || (zero_bits && ((bits - zero_bits) == 1)))
+        return zero_bits;
     return -1;
 }
 
 /**
- * Set maxium number of Virtual IDs allowed in a machine. 
+ * Set maxium number of Virtual IDs allowed in a machine.
  *
  * @param nvid   Number of virtial ids allowed in a machine.
  * @return       Return 0 on success or -1 on failure.
  */
 int cvmx_l2c_vrt_set_max_virtids(int nvid)
 {
-    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
-    {
-        cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
+    cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
 
-        l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
+    if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
+        return -1;
 
-        if (l2c_vrt_ctl.s.enable)
-        {
-            cvmx_dprintf("WARNING: Changing number of Virtual Machine IDs is not allowed after Virtualization is enabled\n");
-            return -1;
-        }
+    l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
 
-        if (nvid < 1 || nvid > CVMX_L2C_VRT_MAX_VIRTID_ALLOWED)
-        {
-            cvmx_dprintf("WARNING: cvmx_l2c_vrt_set_max_virtids: Invalid number of Virtual Machine IDs(%d) requested, max allowed %d\n", nvid, CVMX_L2C_VRT_MAX_VIRTID_ALLOWED);
-            return -1;
-        }
+    if (l2c_vrt_ctl.s.enable) {
+        cvmx_dprintf("WARNING: Changing number of Virtual Machine IDs is not allowed after Virtualization is enabled\n");
+        return -1;
+    }
 
-        /* Calculate the numid based on nvid */
-        l2c_vrt_ctl.s.numid = __cvmx_l2c_vrt_decode_numid(nvid);
-        cvmx_write_csr(CVMX_L2C_VRT_CTL, l2c_vrt_ctl.u64);
+    if (nvid < 1 || nvid > CVMX_L2C_VRT_MAX_VIRTID_ALLOWED) {
+        cvmx_dprintf("WARNING: cvmx_l2c_vrt_set_max_virtids: Invalid number of Virtual Machine IDs(%d) requested, max allowed %d\n",
+                 nvid, CVMX_L2C_VRT_MAX_VIRTID_ALLOWED);
+        return -1;
     }
+
+    /* Calculate the numid based on nvid */
+    l2c_vrt_ctl.s.numid = __cvmx_l2c_vrt_decode_numid(nvid);
+    cvmx_write_csr(CVMX_L2C_VRT_CTL, l2c_vrt_ctl.u64);
     return 0;
 }
 
@@ -1058,18 +1266,18 @@ int cvmx_l2c_vrt_set_max_virtids(int nvid)
  */
 int cvmx_l2c_vrt_get_max_virtids(void)
 {
-    int virtids = -1;
+    int virtids;
+    cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
 
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
-    {
-        cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
-        l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
-        virtids = 1 << (l2c_vrt_ctl.s.numid + 1);
-        if (virtids > CVMX_L2C_VRT_MAX_VIRTID_ALLOWED)
-        {
-            cvmx_dprintf("WARNING: cvmx_l2c_vrt_get_max_virtids: Invalid number of Virtual IDs initialized (%d)\n", virtids);
-            return -1;
-        }
+    if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
+        return -1;
+
+    l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
+    virtids = 1 << (l2c_vrt_ctl.s.numid + 1);
+    if (virtids > CVMX_L2C_VRT_MAX_VIRTID_ALLOWED) {
+        cvmx_dprintf("WARNING: cvmx_l2c_vrt_get_max_virtids: Invalid number of Virtual IDs initialized (%d)\n",
+                 virtids);
+        return -1;
     }
     return virtids;
 }
@@ -1078,7 +1286,7 @@ int cvmx_l2c_vrt_get_max_virtids(void)
  * @INTERNAL
  * Helper function to decode VALUE to memory space coverage of L2C_VRT_MEM.
  * Returns L2C_VRT_CTL[MEMSZ].
- * 
+ *
  * @param memsz    Memory in GB.
  * @return         On success, decode to MEMSZ, or on failure return -1.
  */
@@ -1087,26 +1295,25 @@ static inline int __cvmx_l2c_vrt_decode_memsize(int memsz)
     int bits = 0;
     int zero_bits = 0;
 
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
-    {
-        if (memsz == 0 || memsz > CVMX_L2C_VRT_MAX_MEMSZ_ALLOWED)
-        {
-            cvmx_dprintf("WARNING: Invalid virtual memory size(%d) requested, should be <= %d\n", memsz, CVMX_L2C_VRT_MAX_MEMSZ_ALLOWED);
-            return -1;
-        }
+    if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
+        return -1;
 
-        while (memsz)
-        {
-           if ((memsz & 1) == 0)
-              zero_bits++;
+    if (memsz == 0 || memsz > CVMX_L2C_MAX_MEMSZ_ALLOWED) {
+        cvmx_dprintf("WARNING: Invalid virtual memory size(%d) requested, should be <= %d\n",
+                 memsz, CVMX_L2C_MAX_MEMSZ_ALLOWED);
+        return -1;
+    }
 
-            bits++;
-            memsz >>= 1;
-        }
+    while (memsz) {
+        if ((memsz & 1) == 0)
+            zero_bits++;
 
-        if (bits == 1 || (bits - zero_bits) == 1)
-            return zero_bits;
+        bits++;
+        memsz >>= 1;
     }
+
+    if (bits == 1 || (bits - zero_bits) == 1)
+        return zero_bits;
     return -1;
 }
 
@@ -1118,35 +1325,35 @@ static inline int __cvmx_l2c_vrt_decode_memsize(int memsz)
  */
 int cvmx_l2c_vrt_set_max_memsz(int memsz)
 {
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
-    {
-        cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
-        int decode = 0;
+    cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
+    int decode = 0;
 
-        l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
+    if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
+        return -1;
 
-        if (l2c_vrt_ctl.s.enable)
-        {
-            cvmx_dprintf("WARNING: cvmx_l2c_vrt_set_memsz: Changing the size of the memory after Virtualization is enabled is not allowed.\n");
-            return -1;
-        }
 
-        if (memsz >= (int)(cvmx_sysinfo_get()->system_dram_size / 1000000))
-        {
-            cvmx_dprintf("WARNING: cvmx_l2c_vrt_set_memsz: Invalid memory size (%d GB), greater than available on the chip\n", memsz);
-            return -1;
-        }
-        
-        decode = __cvmx_l2c_vrt_decode_memsize(memsz);
-        if (decode == -1)
-        {
-            cvmx_dprintf("WARNING: cvmx_l2c_vrt_set_memsz: Invalid memory size (%d GB), refer to L2C_VRT_CTL[MEMSZ] for more information\n", memsz);
-            return -1;
-        }
+    l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
 
-        l2c_vrt_ctl.s.memsz = decode;
-        cvmx_write_csr(CVMX_L2C_VRT_CTL, l2c_vrt_ctl.u64);
+    if (l2c_vrt_ctl.s.enable) {
+        cvmx_dprintf("WARNING: cvmx_l2c_vrt_set_memsz: Changing the size of the memory after Virtualization is enabled is not allowed.\n");
+        return -1;
     }
+
+    if (memsz >= (int)(cvmx_sysinfo_get()->system_dram_size / 1000000)) {
+        cvmx_dprintf("WARNING: cvmx_l2c_vrt_set_memsz: Invalid memory size (%d GB), greater than available on the chip\n",
+                 memsz);
+        return -1;
+    }
+
+    decode = __cvmx_l2c_vrt_decode_memsize(memsz);
+    if (decode == -1) {
+        cvmx_dprintf("WARNING: cvmx_l2c_vrt_set_memsz: Invalid memory size (%d GB), refer to L2C_VRT_CTL[MEMSZ] for more information\n",
+                 memsz);
+        return -1;
+    }
+
+    l2c_vrt_ctl.s.memsz = decode;
+    cvmx_write_csr(CVMX_L2C_VRT_CTL, l2c_vrt_ctl.u64);
     return 0;
 }
 
@@ -1160,76 +1367,75 @@ int cvmx_l2c_vrt_set_max_memsz(int memsz)
 int cvmx_l2c_vrt_assign_virtid(int virtid, uint32_t coremask)
 {
     uint32_t core = 0;
+    int found = 0;
+    int max_virtid;
 
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
-    {
-        int found = 0;
-        int max_virtid = cvmx_l2c_vrt_get_max_virtids();
-        
-        if (virtid > max_virtid)
-        {
-            cvmx_dprintf("WARNING: cvmx_l2c_vrt_assign_virt_id: Max %d number of virtids are allowed, passed %d.\n", max_virtid, virtid);
-            return -1;
-        }
+    if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
+        return -1;
 
-        while (core < cvmx_octeon_num_cores())
-        {
-            if ((coremask >> core) & 1)
-            {
-                cvmx_l2c_virtid_ppx_t l2c_virtid_ppx;
-                cvmx_l2c_virtid_iobx_t l2c_virtid_iobx;
-                l2c_virtid_ppx.u64 = cvmx_read_csr(CVMX_L2C_VIRTID_PPX(core));
-
-                /* Check if the core already has a virtid assigned. */
-                if (l2c_virtid_ppx.s.id)
-                {
-                    cvmx_dprintf("WARNING: cvmx_l2c_vrt_assign_virt_id: Changing virtid of core #%d to %d from %d.\n", 
-                        (unsigned int)core, virtid, l2c_virtid_ppx.s.id);
-
-                    /* Flush L2 cache to avoid write errors */
-                    cvmx_l2c_flush();
-                }
-                cvmx_write_csr(CVMX_L2C_VIRTID_PPX(core), virtid & 0x3f);
-
-                /* Set the IOB to normal mode. */
-                l2c_virtid_iobx.u64 = cvmx_read_csr(CVMX_L2C_VIRTID_IOBX(core));
-                l2c_virtid_iobx.s.id = 1;
-                l2c_virtid_iobx.s.dwbid = 0;
-                cvmx_write_csr(CVMX_L2C_VIRTID_IOBX(core), l2c_virtid_iobx.u64); 
-                found = 1;
-            }
-            core++;
-        } 
+    max_virtid = cvmx_l2c_vrt_get_max_virtids();
 
-        /* Invalid coremask passed. */
-        if (!found)
-        {
-           cvmx_dprintf("WARNING: cvmx_l2c_vrt_assign_virt_id: Invalid coremask(0x%x) passed\n", (unsigned int)coremask);
-           return -1;
+    if (virtid > max_virtid) {
+        cvmx_dprintf("WARNING: cvmx_l2c_vrt_assign_virt_id: Max %d number of virtids are allowed, passed %d.\n",
+                 max_virtid, virtid);
+        return -1;
+    }
+
+    while (core < cvmx_octeon_num_cores()) {
+        if ((coremask >> core) & 1) {
+            cvmx_l2c_virtid_ppx_t l2c_virtid_ppx;
+            cvmx_l2c_virtid_iobx_t l2c_virtid_iobx;
+            l2c_virtid_ppx.u64 = cvmx_read_csr(CVMX_L2C_VIRTID_PPX(core));
+
+            /* Check if the core already has a virtid assigned. */
+            if (l2c_virtid_ppx.s.id) {
+                cvmx_dprintf("WARNING: cvmx_l2c_vrt_assign_virt_id: Changing virtid of core #%d to %d from %d.\n",
+                         (unsigned int)core, virtid,
+                         l2c_virtid_ppx.s.id);
+
+                /* Flush L2 cache to avoid write errors */
+                cvmx_l2c_flush();
+            }
+            cvmx_write_csr(CVMX_L2C_VIRTID_PPX(core), virtid & 0x3f);
+
+            /* Set the IOB to normal mode. */
+            l2c_virtid_iobx.u64 = cvmx_read_csr(CVMX_L2C_VIRTID_IOBX(core));
+            l2c_virtid_iobx.s.id = 1;
+            l2c_virtid_iobx.s.dwbid = 0;
+            cvmx_write_csr(CVMX_L2C_VIRTID_IOBX(core),
+                       l2c_virtid_iobx.u64);
+            found = 1;
         }
+        core++;
+    }
+
+    /* Invalid coremask passed. */
+    if (!found) {
+        cvmx_dprintf("WARNING: cvmx_l2c_vrt_assign_virt_id: Invalid coremask(0x%x) passed\n",
+                 (unsigned int)coremask);
+        return -1;
     }
     return 0;
 }
 
 /**
  * Remove a virt id assigned to a set of cores. Update the virtid mask and
- * virtid stored for each core. 
+ * virtid stored for each core.
  *
  * @param virtid  Remove the specified Virtualization machine ID.
  */
 void cvmx_l2c_vrt_remove_virtid(int virtid)
 {
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
-    {
-        uint32_t core;
-        cvmx_l2c_virtid_ppx_t l2c_virtid_ppx;
+    uint32_t core;
+    cvmx_l2c_virtid_ppx_t l2c_virtid_ppx;
 
-        for (core = 0; core < cvmx_octeon_num_cores(); core++)
-        {
-            l2c_virtid_ppx.u64 = cvmx_read_csr(CVMX_L2C_VIRTID_PPX(core));
-            if (virtid == l2c_virtid_ppx.s.id)
-                cvmx_write_csr(CVMX_L2C_VIRTID_PPX(core), 0);
-        }
+    if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
+        return;
+
+    for (core = 0; core < cvmx_octeon_num_cores(); core++) {
+        l2c_virtid_ppx.u64 = cvmx_read_csr(CVMX_L2C_VIRTID_PPX(core));
+        if (virtid == l2c_virtid_ppx.s.id)
+            cvmx_write_csr(CVMX_L2C_VIRTID_PPX(core), 0);
     }
 }
 
@@ -1240,8 +1446,7 @@ static uint64_t __cvmx_l2c_vrt_get_granularity(void)
 {
     uint64_t gran = 0;
 
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
-    {
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) {
         int nvid;
         uint64_t szd;
         cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
@@ -1254,6 +1459,8 @@ static uint64_t __cvmx_l2c_vrt_get_granularity(void)
     return gran;
 }
 
+CVMX_SHARED cvmx_spinlock_t cvmx_l2c_vrt_spinlock;
+
 /**
  * Block a memory region to be updated for a given virtual id.
  *
@@ -1266,119 +1473,123 @@ static uint64_t __cvmx_l2c_vrt_get_granularity(void)
  */
 int cvmx_l2c_vrt_memprotect(uint64_t start_addr, int size, int virtid, int mode)
 {
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
-    {
-        /* Check the alignment of start address, should be aligned to the
-           granularity. */
-        uint64_t gran = __cvmx_l2c_vrt_get_granularity();
-        uint64_t end_addr = start_addr + size;
-        int byte_offset, virtid_offset;
-        cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
-        cvmx_l2c_vrt_memx_t l2c_vrt_mem;
+    uint64_t gran;
+    uint64_t end_addr;
+    int byte_offset, virtid_offset;
+    cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
+    cvmx_l2c_vrt_memx_t l2c_vrt_mem;
+    cvmx_l2c_virtid_ppx_t l2c_virtid_ppx;
+    int found;
+    uint32_t core;
+
+    if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
+        return -1;
+    /*
+     * Check the alignment of start address, should be aligned to the
+     * granularity.
+     */
+    gran = __cvmx_l2c_vrt_get_granularity();
+    end_addr = start_addr + size;
+    l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
 
-        l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
+    /* No need to protect if virtualization is not enabled */
+    if (!l2c_vrt_ctl.s.enable) {
+        cvmx_dprintf("WARNING: cvmx_l2c_vrt_memprotect: Virtualization is not enabled.\n");
+        return -1;
+    }
 
-        /* No need to protect if virtualization is not enabled */
-        if (!l2c_vrt_ctl.s.enable)
-        {
-            cvmx_dprintf("WARNING: cvmx_l2c_vrt_memprotect: Virtualization is not enabled.\n");
-            return -1;
-        }
+    if (virtid > cvmx_l2c_vrt_get_max_virtids()) {
+        cvmx_dprintf("WARNING: cvmx_l2c_vrt_memprotect: Virtualization id is greater than max allowed\n");
+        return -1;
+    }
 
-        if (virtid > cvmx_l2c_vrt_get_max_virtids())
-        {
-            cvmx_dprintf("WARNING: cvmx_l2c_vrt_memprotect: Virtualization id is greater than max allowed\n");
-            return -1;
+    /* No need to protect if virtid is not assigned to a core */
+    found = 0;
+    for (core = 0; core < cvmx_octeon_num_cores(); core++) {
+        l2c_virtid_ppx.u64 = cvmx_read_csr(CVMX_L2C_VIRTID_PPX(core));
+        if (l2c_virtid_ppx.s.id == virtid) {
+            found = 1;
+            break;
         }
+    }
+    if (found == 0) {
+        cvmx_dprintf("WARNING: cvmx_l2c_vrt_memprotect: Virtualization id (%d) is not assigned to any core.\n",
+                 virtid);
+        return -1;
+    }
 
-        /* No need to protect if virtid is not assigned to a core */
-        {
-            cvmx_l2c_virtid_ppx_t l2c_virtid_ppx;
-            int found = 0;
-            uint32_t core;
-
-            for (core = 0; core < cvmx_octeon_num_cores(); core++)
-            {
-                l2c_virtid_ppx.u64 = cvmx_read_csr(CVMX_L2C_VIRTID_PPX(core));
-                if (l2c_virtid_ppx.s.id == virtid)
-                {
-                    found = 1;
-                    break;
-                }
-            }
-            if (found == 0)
-            {
-                cvmx_dprintf("WARNING: cvmx_l2c_vrt_memprotect: Virtualization id (%d) is not assigned to any core.\n", virtid);
-                return -1;
-            }
-        }
+    /*
+     * Make sure previous stores are through before protecting the
+     * memory.
+     */
+    CVMX_SYNCW;
 
-        /* Make sure previous stores are through before protecting the memory. */
-        CVMX_SYNCW;
+    /*
+     * If the L2/DRAM physical address is >= 512 MB, subtract 256
+     * MB to get the address to use. This is because L2C removes
+     * the 256MB "hole" between DR0 and DR1.
+     */
+    if (start_addr >= (512 * 1024 * 1024))
+        start_addr -= 256 * 1024 * 1024;
 
-        /* If the L2/DRAM physical address is >= 512 MB, subtract 256 MB
-           to get the address to use. This is because L2C removes the 256MB 
-           "hole" between DR0 and DR1. */
-        if (start_addr >= (512 * 1024 * 1024))
-            start_addr -= 256 * 1024 * 1024;
+    if (start_addr != ((start_addr + (gran - 1)) & ~(gran - 1))) {
+        cvmx_dprintf("WARNING: cvmx_l2c_vrt_memprotect: Start address is not aligned\n");
+        return -1;
+    }
 
-        if (start_addr != ((start_addr + (gran - 1)) & ~(gran - 1)))
-        {
-            cvmx_dprintf("WARNING: cvmx_l2c_vrt_memprotect: Start address is not aligned\n");
-            return -1;
-        } 
+    /*
+     * Check the size of the memory to protect, should be aligned
+     * to the granularity.
+     */
+    if (end_addr != ((end_addr + (gran - 1)) & ~(gran - 1))) {
+        end_addr = (start_addr + (gran - 1)) & ~(gran - 1);
+        size = start_addr - end_addr;
+    }
 
-        /* Check the size of the memory to protect, should be aligned to the
-           granularity. */
-        if (end_addr != ((end_addr + (gran - 1)) & ~(gran - 1)))
-        {
-            end_addr = (start_addr + (gran - 1)) & ~(gran - 1);
-            size = start_addr - end_addr;
+    byte_offset = l2c_vrt_ctl.s.memsz + l2c_vrt_ctl.s.numid + 16;
+    virtid_offset = 14 - l2c_vrt_ctl.s.numid;
+
+    cvmx_spinlock_lock(&cvmx_l2c_vrt_spinlock);
+
+    /* Enable memory protection for each virtid for the specified range. */
+    while (start_addr < end_addr) {
+        /*
+         * When L2C virtualization is enabled and a bit is set
+         * in L2C_VRT_MEM(0..1023), then L2C prevents the
+         * selected virtual machine from storing to the
+         * selected L2C/DRAM region.
+         */
+        int offset, position, i;
+        int l2c_vrt_mem_bit_index = start_addr >> byte_offset;
+        l2c_vrt_mem_bit_index |= (virtid << virtid_offset);
+
+        offset = l2c_vrt_mem_bit_index >> 5;
+        position = l2c_vrt_mem_bit_index & 0x1f;
+
+        l2c_vrt_mem.u64 = cvmx_read_csr(CVMX_L2C_VRT_MEMX(offset));
+        /* Allow/Disallow write access to memory. */
+        if (mode == 0)
+            l2c_vrt_mem.s.data &= ~(1 << position);
+        else
+            l2c_vrt_mem.s.data |= 1 << position;
+        l2c_vrt_mem.s.parity = 0;
+        /* PARITY<i> is the even parity of DATA<i*8+7:i*8>, which means
+         * that each bit<i> in PARITY[0..3], is the XOR of all the bits
+         * in the corresponding byte in DATA.
+         */
+        for (i = 0; i <= 4; i++) {
+            uint64_t mask = 0xffull << (i*8);
+            if ((cvmx_pop(l2c_vrt_mem.s.data & mask) & 0x1))
+                l2c_vrt_mem.s.parity |= (1ull << i);
         }
+        cvmx_write_csr(CVMX_L2C_VRT_MEMX(offset), l2c_vrt_mem.u64);
+        start_addr += gran;
+    }
 
-        byte_offset = l2c_vrt_ctl.s.memsz + l2c_vrt_ctl.s.numid + 16;
-        virtid_offset = 14 - l2c_vrt_ctl.s.numid;
-        
-        cvmx_spinlock_lock(&cvmx_l2c_vrt_spinlock);
-
-        /* Enable memory protection for each virtid for the specified range. */
-        while (start_addr < end_addr)
-        {
-            /* When L2C virtualization is enabled and a bit is set in 
-               L2C_VRT_MEM(0..1023), then L2C prevents the selected virtual 
-               machine from storing to the selected L2C/DRAM region. */ 
-            int offset, position, i;
-            int l2c_vrt_mem_bit_index = start_addr >> byte_offset;
-            l2c_vrt_mem_bit_index |= (virtid << virtid_offset);
-
-            offset = l2c_vrt_mem_bit_index >> 5;
-            position = l2c_vrt_mem_bit_index & 0x1f;
-
-            l2c_vrt_mem.u64 = cvmx_read_csr(CVMX_L2C_VRT_MEMX(offset));
-            /* Allow/Disallow write access to memory. */
-            if (mode == 0)
-                l2c_vrt_mem.s.data &= ~(1 << position);
-            else
-                l2c_vrt_mem.s.data |= 1 << position;
-            l2c_vrt_mem.s.parity = 0;
-            /* PARITY<i> is the even parity of DATA<i*8+7:i*8>, which means
-               that each bit<i> in PARITY[0..3], is the XOR of all the bits
-               in the corresponding byte in DATA. */
-            for (i = 0; i <= 4; i++)
-            {
-               uint64_t mask = 0xffull << (i*8);
-               if ((cvmx_pop(l2c_vrt_mem.s.data & mask) & 0x1))
-                   l2c_vrt_mem.s.parity |= (1ull << i);
-            }
-            cvmx_write_csr(CVMX_L2C_VRT_MEMX(offset), l2c_vrt_mem.u64);
-            start_addr += gran;
-        }
+    cvmx_spinlock_unlock(&cvmx_l2c_vrt_spinlock);
 
-        cvmx_spinlock_unlock(&cvmx_l2c_vrt_spinlock);
-    }
     return 0;
 }
-#endif
 
 /**
  * Enable virtualization.
@@ -1387,16 +1598,16 @@ int cvmx_l2c_vrt_memprotect(uint64_t start_addr, int size, int virtid, int mode)
  */
 void cvmx_l2c_vrt_enable(int mode)
 {
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
-    {
-        cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
+    cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
 
-        /* Enable global virtualization */
-        l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
-        l2c_vrt_ctl.s.ooberr = mode;
-        l2c_vrt_ctl.s.enable = 1;
-        cvmx_write_csr(CVMX_L2C_VRT_CTL, l2c_vrt_ctl.u64);
-    }
+    if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
+        return;
+
+    /* Enable global virtualization */
+    l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
+    l2c_vrt_ctl.s.ooberr = mode;
+    l2c_vrt_ctl.s.enable = 1;
+    cvmx_write_csr(CVMX_L2C_VRT_CTL, l2c_vrt_ctl.u64);
 }
 
 /**
@@ -1404,13 +1615,14 @@ void cvmx_l2c_vrt_enable(int mode)
  */
 void cvmx_l2c_vrt_disable(void)
 {
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
-    {
-        cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
+    cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
 
-        /* Disable global virtualization */
-        l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
-        l2c_vrt_ctl.s.enable = 0;
-        cvmx_write_csr(CVMX_L2C_VRT_CTL, l2c_vrt_ctl.u64);
-    }
+    if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
+        return;
+
+    /* Disable global virtualization */
+    l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
+    l2c_vrt_ctl.s.enable = 0;
+    cvmx_write_csr(CVMX_L2C_VRT_CTL, l2c_vrt_ctl.u64);
 }
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-l2c.h b/sys/contrib/octeon-sdk/cvmx-l2c.h
index 775f26f..ef689d8 100644
--- a/sys/contrib/octeon-sdk/cvmx-l2c.h
+++ b/sys/contrib/octeon-sdk/cvmx-l2c.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2011  Cavium, Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -37,30 +37,19 @@
  * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
-
-
-
-
-
-
 /**
  * @file
  *
  * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
  * facilities.
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
 #ifndef __CVMX_L2C_H__
 #define __CVMX_L2C_H__
 
-#define CVMX_L2_ASSOC     cvmx_l2c_get_num_assoc()   /* Deprecated macro, use function */
-#define CVMX_L2_SET_BITS  cvmx_l2c_get_set_bits()    /* Deprecated macro, use function */
-#define CVMX_L2_SETS      cvmx_l2c_get_num_sets()    /* Deprecated macro, use function */
-
-
 #define CVMX_L2C_IDX_ADDR_SHIFT 7  /* based on 128 byte cache line size */
 #define CVMX_L2C_IDX_MASK       (cvmx_l2c_get_num_sets() - 1)
 
@@ -70,123 +59,139 @@
 #define CVMX_L2C_MEMBANK_SELECT_SIZE  4096
 
 /* Defines for Virtualizations, valid only from Octeon II onwards. */
-#define CVMX_L2C_VRT_MAX_VIRTID_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 64 : 0)
-#define CVMX_L2C_VRT_MAX_MEMSZ_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 32 : 0)
+#define CVMX_L2C_VRT_MAX_VIRTID_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) ? 64 : 0)
+#define CVMX_L2C_MAX_MEMSZ_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) ? 32 : 0)
 
   /*------------*/
   /*  TYPEDEFS  */
   /*------------*/
 
-typedef union
-{
-    uint64_t u64;
-#if __BYTE_ORDER == __BIG_ENDIAN
-    struct
-    {
-	uint64_t reserved		: 28;
-	uint64_t V			: 1;	// Line valid
-	uint64_t D			: 1;	// Line dirty
-	uint64_t L			: 1;	// Line locked
-	uint64_t U			: 1;	// Use, LRU eviction
-	uint64_t addr			: 32;	// Phys mem (not all bits valid)
-    } s;
+union cvmx_l2c_tag {
+	uint64_t u64;
+#ifdef __BIG_ENDIAN_BITFIELD
+	struct {
+		uint64_t reserved:28;
+		uint64_t V:1;		/* Line valid */
+		uint64_t D:1;		/* Line dirty */
+		uint64_t L:1;		/* Line locked */
+		uint64_t U:1;		/* Use, LRU eviction */
+		uint64_t addr:32;	/* Phys mem (not all bits valid) */
+	} s;
+#else
+	struct {
+		uint64_t addr:32;	/* Phys mem (not all bits valid) */
+		uint64_t U:1;		/* Use, LRU eviction */
+		uint64_t L:1;		/* Line locked */
+		uint64_t D:1;		/* Line dirty */
+		uint64_t V:1;		/* Line valid */
+		uint64_t reserved:28;
+	} s;
+
 #endif
-} cvmx_l2c_tag_t;
+};
+typedef union cvmx_l2c_tag cvmx_l2c_tag_t;
+
+/* Maximium number of TADs */
+#define CVMX_L2C_MAX_TADS     4
+/* Maximium number of L2C performance counters */
+#define CVMX_L2C_MAX_PCNT     4
 
 /* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
-#define CVMX_L2C_TADS  1
+#define CVMX_L2C_TADS  ((OCTEON_IS_MODEL(OCTEON_CN68XX)) ? 4 : 1)
+/* Number of L2C IOBs connected to LMC. */ 
+#define CVMX_L2C_IOBS  ((OCTEON_IS_MODEL(OCTEON_CN68XX)) ? 2 : 1)
 
   /* L2C Performance Counter events. */
-typedef enum
-{
-    CVMX_L2C_EVENT_CYCLES           =  0,    /**< Cycles */
-    CVMX_L2C_EVENT_INSTRUCTION_MISS =  1,    /**< L2 Instruction Miss */
-    CVMX_L2C_EVENT_INSTRUCTION_HIT  =  2,    /**< L2 Instruction Hit */
-    CVMX_L2C_EVENT_DATA_MISS        =  3,    /**< L2 Data Miss */
-    CVMX_L2C_EVENT_DATA_HIT         =  4,    /**< L2 Data Hit */
-    CVMX_L2C_EVENT_MISS             =  5,    /**< L2 Miss (I/D) */
-    CVMX_L2C_EVENT_HIT              =  6,    /**< L2 Hit (I/D) */
-    CVMX_L2C_EVENT_VICTIM_HIT       =  7,    /**< L2 Victim Buffer Hit (Retry Probe) */
-    CVMX_L2C_EVENT_INDEX_CONFLICT   =  8,    /**< LFB-NQ Index Conflict */
-    CVMX_L2C_EVENT_TAG_PROBE        =  9,    /**< L2 Tag Probe (issued - could be VB-Retried) */
-    CVMX_L2C_EVENT_TAG_UPDATE       = 10,    /**< L2 Tag Update (completed). Note: Some CMD types do not update */
-    CVMX_L2C_EVENT_TAG_COMPLETE     = 11,    /**< L2 Tag Probe Completed (beyond VB-RTY window) */
-    CVMX_L2C_EVENT_TAG_DIRTY        = 12,    /**< L2 Tag Dirty Victim */
-    CVMX_L2C_EVENT_DATA_STORE_NOP   = 13,    /**< L2 Data Store NOP */
-    CVMX_L2C_EVENT_DATA_STORE_READ  = 14,    /**< L2 Data Store READ */
-    CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,    /**< L2 Data Store WRITE */
-    CVMX_L2C_EVENT_FILL_DATA_VALID  = 16,    /**< Memory Fill Data valid */
-    CVMX_L2C_EVENT_WRITE_REQUEST    = 17,    /**< Memory Write Request */
-    CVMX_L2C_EVENT_READ_REQUEST     = 18,    /**< Memory Read Request */
-    CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,    /**< Memory Write Data valid */
-    CVMX_L2C_EVENT_XMC_NOP          = 20,    /**< XMC NOP */
-    CVMX_L2C_EVENT_XMC_LDT          = 21,    /**< XMC LDT */
-    CVMX_L2C_EVENT_XMC_LDI          = 22,    /**< XMC LDI */
-    CVMX_L2C_EVENT_XMC_LDD          = 23,    /**< XMC LDD */
-    CVMX_L2C_EVENT_XMC_STF          = 24,    /**< XMC STF */
-    CVMX_L2C_EVENT_XMC_STT          = 25,    /**< XMC STT */
-    CVMX_L2C_EVENT_XMC_STP          = 26,    /**< XMC STP */
-    CVMX_L2C_EVENT_XMC_STC          = 27,    /**< XMC STC */
-    CVMX_L2C_EVENT_XMC_DWB          = 28,    /**< XMC DWB */
-    CVMX_L2C_EVENT_XMC_PL2          = 29,    /**< XMC PL2 */
-    CVMX_L2C_EVENT_XMC_PSL1         = 30,    /**< XMC PSL1 */
-    CVMX_L2C_EVENT_XMC_IOBLD        = 31,    /**< XMC IOBLD */
-    CVMX_L2C_EVENT_XMC_IOBST        = 32,    /**< XMC IOBST */
-    CVMX_L2C_EVENT_XMC_IOBDMA       = 33,    /**< XMC IOBDMA */
-    CVMX_L2C_EVENT_XMC_IOBRSP       = 34,    /**< XMC IOBRSP */
-    CVMX_L2C_EVENT_XMC_BUS_VALID    = 35,    /**< XMC Bus valid (all) */
-    CVMX_L2C_EVENT_XMC_MEM_DATA     = 36,    /**< XMC Bus valid (DST=L2C) Memory */
-    CVMX_L2C_EVENT_XMC_REFL_DATA    = 37,    /**< XMC Bus valid (DST=IOB) REFL Data */
-    CVMX_L2C_EVENT_XMC_IOBRSP_DATA  = 38,    /**< XMC Bus valid (DST=PP) IOBRSP Data */
-    CVMX_L2C_EVENT_RSC_NOP          = 39,    /**< RSC NOP */
-    CVMX_L2C_EVENT_RSC_STDN         = 40,    /**< RSC STDN */
-    CVMX_L2C_EVENT_RSC_FILL         = 41,    /**< RSC FILL */
-    CVMX_L2C_EVENT_RSC_REFL         = 42,    /**< RSC REFL */
-    CVMX_L2C_EVENT_RSC_STIN         = 43,    /**< RSC STIN */
-    CVMX_L2C_EVENT_RSC_SCIN         = 44,    /**< RSC SCIN */
-    CVMX_L2C_EVENT_RSC_SCFL         = 45,    /**< RSC SCFL */
-    CVMX_L2C_EVENT_RSC_SCDN         = 46,    /**< RSC SCDN */
-    CVMX_L2C_EVENT_RSC_DATA_VALID   = 47,    /**< RSC Data Valid */
-    CVMX_L2C_EVENT_RSC_VALID_FILL   = 48,    /**< RSC Data Valid (FILL) */
-    CVMX_L2C_EVENT_RSC_VALID_STRSP  = 49,    /**< RSC Data Valid (STRSP) */
-    CVMX_L2C_EVENT_RSC_VALID_REFL   = 50,    /**< RSC Data Valid (REFL) */
-    CVMX_L2C_EVENT_LRF_REQ          = 51,    /**< LRF-REQ (LFB-NQ) */
-    CVMX_L2C_EVENT_DT_RD_ALLOC      = 52,    /**< DT RD-ALLOC */
-    CVMX_L2C_EVENT_DT_WR_INVAL      = 53,    /**< DT WR-INVAL */
-    CVMX_L2C_EVENT_MAX
-} cvmx_l2c_event_t;
+enum cvmx_l2c_event {
+	CVMX_L2C_EVENT_CYCLES           =  0,    /**< Cycles */
+	CVMX_L2C_EVENT_INSTRUCTION_MISS =  1,    /**< L2 Instruction Miss */
+	CVMX_L2C_EVENT_INSTRUCTION_HIT  =  2,    /**< L2 Instruction Hit */
+	CVMX_L2C_EVENT_DATA_MISS        =  3,    /**< L2 Data Miss */
+	CVMX_L2C_EVENT_DATA_HIT         =  4,    /**< L2 Data Hit */
+	CVMX_L2C_EVENT_MISS             =  5,    /**< L2 Miss (I/D) */
+	CVMX_L2C_EVENT_HIT              =  6,    /**< L2 Hit (I/D) */
+	CVMX_L2C_EVENT_VICTIM_HIT       =  7,    /**< L2 Victim Buffer Hit (Retry Probe) */
+	CVMX_L2C_EVENT_INDEX_CONFLICT   =  8,    /**< LFB-NQ Index Conflict */
+	CVMX_L2C_EVENT_TAG_PROBE        =  9,    /**< L2 Tag Probe (issued - could be VB-Retried) */
+	CVMX_L2C_EVENT_TAG_UPDATE       = 10,    /**< L2 Tag Update (completed). Note: Some CMD types do not update */
+	CVMX_L2C_EVENT_TAG_COMPLETE     = 11,    /**< L2 Tag Probe Completed (beyond VB-RTY window) */
+	CVMX_L2C_EVENT_TAG_DIRTY        = 12,    /**< L2 Tag Dirty Victim */
+	CVMX_L2C_EVENT_DATA_STORE_NOP   = 13,    /**< L2 Data Store NOP */
+	CVMX_L2C_EVENT_DATA_STORE_READ  = 14,    /**< L2 Data Store READ */
+	CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,    /**< L2 Data Store WRITE */
+	CVMX_L2C_EVENT_FILL_DATA_VALID  = 16,    /**< Memory Fill Data valid */
+	CVMX_L2C_EVENT_WRITE_REQUEST    = 17,    /**< Memory Write Request */
+	CVMX_L2C_EVENT_READ_REQUEST     = 18,    /**< Memory Read Request */
+	CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,    /**< Memory Write Data valid */
+	CVMX_L2C_EVENT_XMC_NOP          = 20,    /**< XMC NOP */
+	CVMX_L2C_EVENT_XMC_LDT          = 21,    /**< XMC LDT */
+	CVMX_L2C_EVENT_XMC_LDI          = 22,    /**< XMC LDI */
+	CVMX_L2C_EVENT_XMC_LDD          = 23,    /**< XMC LDD */
+	CVMX_L2C_EVENT_XMC_STF          = 24,    /**< XMC STF */
+	CVMX_L2C_EVENT_XMC_STT          = 25,    /**< XMC STT */
+	CVMX_L2C_EVENT_XMC_STP          = 26,    /**< XMC STP */
+	CVMX_L2C_EVENT_XMC_STC          = 27,    /**< XMC STC */
+	CVMX_L2C_EVENT_XMC_DWB          = 28,    /**< XMC DWB */
+	CVMX_L2C_EVENT_XMC_PL2          = 29,    /**< XMC PL2 */
+	CVMX_L2C_EVENT_XMC_PSL1         = 30,    /**< XMC PSL1 */
+	CVMX_L2C_EVENT_XMC_IOBLD        = 31,    /**< XMC IOBLD */
+	CVMX_L2C_EVENT_XMC_IOBST        = 32,    /**< XMC IOBST */
+	CVMX_L2C_EVENT_XMC_IOBDMA       = 33,    /**< XMC IOBDMA */
+	CVMX_L2C_EVENT_XMC_IOBRSP       = 34,    /**< XMC IOBRSP */
+	CVMX_L2C_EVENT_XMC_BUS_VALID    = 35,    /**< XMC Bus valid (all) */
+	CVMX_L2C_EVENT_XMC_MEM_DATA     = 36,    /**< XMC Bus valid (DST=L2C) Memory */
+	CVMX_L2C_EVENT_XMC_REFL_DATA    = 37,    /**< XMC Bus valid (DST=IOB) REFL Data */
+	CVMX_L2C_EVENT_XMC_IOBRSP_DATA  = 38,    /**< XMC Bus valid (DST=PP) IOBRSP Data */
+	CVMX_L2C_EVENT_RSC_NOP          = 39,    /**< RSC NOP */
+	CVMX_L2C_EVENT_RSC_STDN         = 40,    /**< RSC STDN */
+	CVMX_L2C_EVENT_RSC_FILL         = 41,    /**< RSC FILL */
+	CVMX_L2C_EVENT_RSC_REFL         = 42,    /**< RSC REFL */
+	CVMX_L2C_EVENT_RSC_STIN         = 43,    /**< RSC STIN */
+	CVMX_L2C_EVENT_RSC_SCIN         = 44,    /**< RSC SCIN */
+	CVMX_L2C_EVENT_RSC_SCFL         = 45,    /**< RSC SCFL */
+	CVMX_L2C_EVENT_RSC_SCDN         = 46,    /**< RSC SCDN */
+	CVMX_L2C_EVENT_RSC_DATA_VALID   = 47,    /**< RSC Data Valid */
+	CVMX_L2C_EVENT_RSC_VALID_FILL   = 48,    /**< RSC Data Valid (FILL) */
+	CVMX_L2C_EVENT_RSC_VALID_STRSP  = 49,    /**< RSC Data Valid (STRSP) */
+	CVMX_L2C_EVENT_RSC_VALID_REFL   = 50,    /**< RSC Data Valid (REFL) */
+	CVMX_L2C_EVENT_LRF_REQ          = 51,    /**< LRF-REQ (LFB-NQ) */
+	CVMX_L2C_EVENT_DT_RD_ALLOC      = 52,    /**< DT RD-ALLOC */
+	CVMX_L2C_EVENT_DT_WR_INVAL      = 53,    /**< DT WR-INVAL */
+	CVMX_L2C_EVENT_MAX
+};
+typedef enum cvmx_l2c_event cvmx_l2c_event_t;
 
 /* L2C Performance Counter events for Octeon2. */
-typedef enum
-{
-     CVMX_L2C_TAD_EVENT_NONE          = 0,     /* None */
-     CVMX_L2C_TAD_EVENT_TAG_HIT       = 1,     /* L2 Tag Hit */
-     CVMX_L2C_TAD_EVENT_TAG_MISS      = 2,     /* L2 Tag Miss */
-     CVMX_L2C_TAD_EVENT_TAG_NOALLOC   = 3,     /* L2 Tag NoAlloc (forced no-allocate) */
-     CVMX_L2C_TAD_EVENT_TAG_VICTIM    = 4,     /* L2 Tag Victim */
-     CVMX_L2C_TAD_EVENT_SC_FAIL       = 5,     /* SC Fail */
-     CVMX_L2C_TAD_EVENT_SC_PASS       = 6,     /* SC Pass */
-     CVMX_L2C_TAD_EVENT_LFB_VALID     = 7,     /* LFB Occupancy (each cycle adds \# of LFBs valid) */
-     CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB  = 8,     /* LFB Wait LFB (each cycle adds \# LFBs waiting for other LFBs) */
-     CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB  = 9,     /* LFB Wait VAB (each cycle adds \# LFBs waiting for VAB) */
-     CVMX_L2C_TAD_EVENT_QUAD0_INDEX   = 128,   /* Quad 0 index bus inuse */
-     CVMX_L2C_TAD_EVENT_QUAD0_READ    = 129,   /* Quad 0 read data bus inuse */
-     CVMX_L2C_TAD_EVENT_QUAD0_BANK    = 130,   /* Quad 0 \# banks inuse (0-4/cycle) */
-     CVMX_L2C_TAD_EVENT_QUAD0_WDAT    = 131,   /* Quad 0 wdat flops inuse (0-4/cycle) */
-     CVMX_L2C_TAD_EVENT_QUAD1_INDEX   = 144,   /* Quad 1 index bus inuse */
-     CVMX_L2C_TAD_EVENT_QUAD1_READ    = 145,   /* Quad 1 read data bus inuse */
-     CVMX_L2C_TAD_EVENT_QUAD1_BANK    = 146,   /* Quad 1 \# banks inuse (0-4/cycle) */
-     CVMX_L2C_TAD_EVENT_QUAD1_WDAT    = 147,   /* Quad 1 wdat flops inuse (0-4/cycle) */
-     CVMX_L2C_TAD_EVENT_QUAD2_INDEX   = 160,   /* Quad 2 index bus inuse */
-     CVMX_L2C_TAD_EVENT_QUAD2_READ    = 161,   /* Quad 2 read data bus inuse */
-     CVMX_L2C_TAD_EVENT_QUAD2_BANK    = 162,   /* Quad 2 \# banks inuse (0-4/cycle) */
-     CVMX_L2C_TAD_EVENT_QUAD2_WDAT    = 163,   /* Quad 2 wdat flops inuse (0-4/cycle) */
-     CVMX_L2C_TAD_EVENT_QUAD3_INDEX   = 176,   /* Quad 3 index bus inuse */
-     CVMX_L2C_TAD_EVENT_QUAD3_READ    = 177,   /* Quad 3 read data bus inuse */
-     CVMX_L2C_TAD_EVENT_QUAD3_BANK    = 178,   /* Quad 3 \# banks inuse (0-4/cycle) */
-     CVMX_L2C_TAD_EVENT_QUAD3_WDAT    = 179,   /* Quad 3 wdat flops inuse (0-4/cycle) */
-     CVMX_L2C_TAD_EVENT_MAX
-} cvmx_l2c_tad_event_t;
+enum cvmx_l2c_tad_event {
+	CVMX_L2C_TAD_EVENT_NONE          = 0,     /* None */
+	CVMX_L2C_TAD_EVENT_TAG_HIT       = 1,     /* L2 Tag Hit */
+	CVMX_L2C_TAD_EVENT_TAG_MISS      = 2,     /* L2 Tag Miss */
+	CVMX_L2C_TAD_EVENT_TAG_NOALLOC   = 3,     /* L2 Tag NoAlloc (forced no-allocate) */
+	CVMX_L2C_TAD_EVENT_TAG_VICTIM    = 4,     /* L2 Tag Victim */
+	CVMX_L2C_TAD_EVENT_SC_FAIL       = 5,     /* SC Fail */
+	CVMX_L2C_TAD_EVENT_SC_PASS       = 6,     /* SC Pass */
+	CVMX_L2C_TAD_EVENT_LFB_VALID     = 7,     /* LFB Occupancy (each cycle adds \# of LFBs valid) */
+	CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB  = 8,     /* LFB Wait LFB (each cycle adds \# LFBs waiting for other LFBs) */
+	CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB  = 9,     /* LFB Wait VAB (each cycle adds \# LFBs waiting for VAB) */
+	CVMX_L2C_TAD_EVENT_QUAD0_INDEX   = 128,   /* Quad 0 index bus inuse */
+	CVMX_L2C_TAD_EVENT_QUAD0_READ    = 129,   /* Quad 0 read data bus inuse */
+	CVMX_L2C_TAD_EVENT_QUAD0_BANK    = 130,   /* Quad 0 \# banks inuse (0-4/cycle) */
+	CVMX_L2C_TAD_EVENT_QUAD0_WDAT    = 131,   /* Quad 0 wdat flops inuse (0-4/cycle) */
+	CVMX_L2C_TAD_EVENT_QUAD1_INDEX   = 144,   /* Quad 1 index bus inuse */
+	CVMX_L2C_TAD_EVENT_QUAD1_READ    = 145,   /* Quad 1 read data bus inuse */
+	CVMX_L2C_TAD_EVENT_QUAD1_BANK    = 146,   /* Quad 1 \# banks inuse (0-4/cycle) */
+	CVMX_L2C_TAD_EVENT_QUAD1_WDAT    = 147,   /* Quad 1 wdat flops inuse (0-4/cycle) */
+	CVMX_L2C_TAD_EVENT_QUAD2_INDEX   = 160,   /* Quad 2 index bus inuse */
+	CVMX_L2C_TAD_EVENT_QUAD2_READ    = 161,   /* Quad 2 read data bus inuse */
+	CVMX_L2C_TAD_EVENT_QUAD2_BANK    = 162,   /* Quad 2 \# banks inuse (0-4/cycle) */
+	CVMX_L2C_TAD_EVENT_QUAD2_WDAT    = 163,   /* Quad 2 wdat flops inuse (0-4/cycle) */
+	CVMX_L2C_TAD_EVENT_QUAD3_INDEX   = 176,   /* Quad 3 index bus inuse */
+	CVMX_L2C_TAD_EVENT_QUAD3_READ    = 177,   /* Quad 3 read data bus inuse */
+	CVMX_L2C_TAD_EVENT_QUAD3_BANK    = 178,   /* Quad 3 \# banks inuse (0-4/cycle) */
+	CVMX_L2C_TAD_EVENT_QUAD3_WDAT    = 179,   /* Quad 3 wdat flops inuse (0-4/cycle) */
+	CVMX_L2C_TAD_EVENT_MAX
+};
+typedef enum cvmx_l2c_tad_event cvmx_l2c_tad_event_t;
 
 /**
  * Configure one of the four L2 Cache performance counters to capture event
@@ -225,14 +230,18 @@ int cvmx_l2c_get_core_way_partition(uint32_t core);
 /**
  * Partitions the L2 cache for a core
  *
- * @param core   The core that the partitioning applies to.
- * @param mask The partitioning of the ways expressed as a binary mask. A 0 bit allows the core
- *             to evict cache lines from a way, while a 1 bit blocks the core from evicting any lines
- *             from that way. There must be at least one allowed way (0 bit) in the mask.
+ * @param core The core that the partitioning applies to.
+ * @param mask The partitioning of the ways expressed as a binary
+ *             mask. A 0 bit allows the core to evict cache lines from
+ *             a way, while a 1 bit blocks the core from evicting any
+ *             lines from that way. There must be at least one allowed
+ *             way (0 bit) in the mask.
  *
- * @note  If any ways are blocked for all cores and the HW blocks, then those ways will never have
- *        any cache lines evicted from them.  All cores and the hardware blocks are free to read from
- *        all ways regardless of the partitioning.
+
+ * @note If any ways are blocked for all cores and the HW blocks, then
+ *       those ways will never have any cache lines evicted from them.
+ *       All cores and the hardware blocks are free to read from all
+ *       ways regardless of the partitioning.
  */
 int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
 
@@ -248,18 +257,48 @@ int cvmx_l2c_get_hw_way_partition(void);
 /**
  * Partitions the L2 cache for the hardware blocks.
  *
- * @param mask The partitioning of the ways expressed as a binary mask. A 0 bit allows the core
- *             to evict cache lines from a way, while a 1 bit blocks the core from evicting any lines
- *             from that way. There must be at least one allowed way (0 bit) in the mask.
+ * @param mask The partitioning of the ways expressed as a binary
+ *             mask. A 0 bit allows the core to evict cache lines from
+ *             a way, while a 1 bit blocks the core from evicting any
+ *             lines from that way. There must be at least one allowed
+ *             way (0 bit) in the mask.
  *
- * @note  If any ways are blocked for all cores and the HW blocks, then those ways will never have
- *        any cache lines evicted from them.  All cores and the hardware blocks are free to read from
- *        all ways regardless of the partitioning.
+
+ * @note If any ways are blocked for all cores and the HW blocks, then
+ *       those ways will never have any cache lines evicted from them.
+ *       All cores and the hardware blocks are free to read from all
+ *       ways regardless of the partitioning.
  */
 int cvmx_l2c_set_hw_way_partition(uint32_t mask);
 
 
 /**
+ * Return the L2 Cache way partitioning for the second set of hw blocks.
+ *
+ * @return    The mask specifying the reserved way. 0 bits in mask indicates
+ *              the cache 'ways' that a core can evict from.
+ *            -1 on error
+ */
+int cvmx_l2c_get_hw_way_partition2(void);
+
+/**
+ * Partitions the L2 cache for the second set of  blocks.
+ *
+ * @param mask The partitioning of the ways expressed as a binary
+ *             mask. A 0 bit allows the core to evict cache lines from
+ *             a way, while a 1 bit blocks the core from evicting any
+ *             lines from that way. There must be at least one allowed
+ *             way (0 bit) in the mask.
+ *
+
+ * @note If any ways are blocked for all cores and the HW blocks, then
+ *       those ways will never have any cache lines evicted from them.
+ *       All cores and the hardware blocks are free to read from all
+ *       ways regardless of the partitioning.
+ */
+int cvmx_l2c_set_hw_way_partition2(uint32_t mask);
+
+/**
  * Locks a line in the L2 cache at the specified physical address
  *
  * @param addr   physical address of line to lock
@@ -313,8 +352,6 @@ int cvmx_l2c_unlock_line(uint64_t address);
 int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
 
 
-
-
 /**
  * Read the L2 controller tag for a given location in L2
  *
@@ -323,16 +360,35 @@ int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
  * @param index  Which way to read from.
  *
  * @return l2c tag structure for line requested.
+ * 
+ * NOTE: This function is deprecated and cannot be used on devices with 
+ *       multiple L2C interfaces such as the OCTEON CN68XX.
+ *       Please use cvmx_l2c_get_tag_v2 instead.
  */
-cvmx_l2c_tag_t cvmx_l2c_get_tag(uint32_t association, uint32_t index);
+cvmx_l2c_tag_t cvmx_l2c_get_tag(uint32_t association, uint32_t index)
+        __attribute__ ((deprecated));
 
-/* Wrapper providing a deprecated old function name */
-static inline cvmx_l2c_tag_t cvmx_get_l2c_tag(uint32_t association, uint32_t index) __attribute__((deprecated));
-static inline cvmx_l2c_tag_t cvmx_get_l2c_tag(uint32_t association, uint32_t index)
-{
-    return cvmx_l2c_get_tag(association, index);
-}
+/**
+ * Read the L2 controller tag for a given location in L2
+ *
+ * @param association
+ *               Which association to read line from
+ * @param index  Which way to read from.
+ * 
+ * @param tad    Which TAD to read from, set to 0 except on OCTEON CN68XX.
+ *
+ * @return l2c tag structure for line requested.
+ */
+cvmx_l2c_tag_t cvmx_l2c_get_tag_v2(uint32_t association, uint32_t index, uint32_t tad);
 
+/**
+ * Find the TAD for the specified address
+ *
+ * @param addr   physical address to get TAD for
+ * 
+ * @return TAD number for address.
+ */
+int cvmx_l2c_address_to_tad(uint64_t addr);
 
 /**
  * Returns the cache index for a given physical address
@@ -343,6 +399,14 @@ static inline cvmx_l2c_tag_t cvmx_get_l2c_tag(uint32_t association, uint32_t ind
  */
 uint32_t cvmx_l2c_address_to_index (uint64_t addr);
 
+/**
+ * Returns the L2 tag that will be used for the given physical address
+ *
+ * @param addr   physical address
+ * @return L2 cache tag. Addreses in the LMC hole are not valid.
+ * Returns 0xFFFFFFFF if the address specified is in the LMC hole.
+ */
+uint32_t cvmx_l2c_v2_address_to_tag(uint64_t addr);
 
 /**
  * Flushes (and unlocks) the entire L2 cache.
@@ -351,8 +415,6 @@ uint32_t cvmx_l2c_address_to_index (uint64_t addr);
  */
 void cvmx_l2c_flush(void);
 
-
-
 /**
  *
  * @return Returns the size of the L2 cache in bytes,
@@ -389,6 +451,17 @@ int cvmx_l2c_get_num_assoc(void);
  */
 void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index);
 
+/**
+ * Initialize the BIG address in L2C+DRAM to generate proper error
+ * on reading/writing to an non-existant memory location. 
+ *
+ * @param mem_size  Amount of DRAM configured in MB.
+ * @param mode      Allow/Disallow reporting errors L2C_INT_SUM[BIGRD,BIGWR].
+ */
+void cvmx_l2c_set_big_size(uint64_t mem_size, int mode);
+
+#if !defined(CVMX_BUILD_FOR_LINUX_HOST) && !defined(CVMX_BUILD_FOR_LINUX_KERNEL)
+
 /*
  * Set maxium number of Virtual IDS allowed in a machine.
  *
@@ -451,4 +524,6 @@ void cvmx_l2c_vrt_enable(int mode);
  */
 void cvmx_l2c_vrt_disable(void);
 
+#endif /* CVMX_BUILD_FOR_LINUX_HOST */
+
 #endif /* __CVMX_L2C_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-l2d-defs.h b/sys/contrib/octeon-sdk/cvmx-l2d-defs.h
index 402edd0..37a377e 100644
--- a/sys/contrib/octeon-sdk/cvmx-l2d-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-l2d-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_L2D_TYPEDEFS_H__
-#define __CVMX_L2D_TYPEDEFS_H__
+#ifndef __CVMX_L2D_DEFS_H__
+#define __CVMX_L2D_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_L2D_BST0 CVMX_L2D_BST0_FUNC()
@@ -191,12 +191,10 @@ static inline uint64_t CVMX_L2D_FUS3_FUNC(void)
  * L2D_BST0 = L2C Data Store QUAD0 BIST Status Register
  *
  */
-union cvmx_l2d_bst0
-{
+union cvmx_l2d_bst0 {
 	uint64_t u64;
-	struct cvmx_l2d_bst0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_bst0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_35_63               : 29;
 	uint64_t ftl                          : 1;  /**< L2C Data Store Fatal Defect(across all QUADs)
                                                          2 or more columns were detected bad across all
@@ -244,12 +242,10 @@ typedef union cvmx_l2d_bst0 cvmx_l2d_bst0_t;
  * L2D_BST1 = L2C Data Store QUAD1 BIST Status Register
  *
  */
-union cvmx_l2d_bst1
-{
+union cvmx_l2d_bst1 {
 	uint64_t u64;
-	struct cvmx_l2d_bst1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_bst1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t q1stat                       : 34; /**< Bist Results for QUAD1
                                                          Failure \#1 Status
@@ -291,12 +287,10 @@ typedef union cvmx_l2d_bst1 cvmx_l2d_bst1_t;
  * L2D_BST2 = L2C Data Store QUAD2 BIST Status Register
  *
  */
-union cvmx_l2d_bst2
-{
+union cvmx_l2d_bst2 {
 	uint64_t u64;
-	struct cvmx_l2d_bst2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_bst2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t q2stat                       : 34; /**< Bist Results for QUAD2
                                                          Failure \#1 Status
@@ -338,12 +332,10 @@ typedef union cvmx_l2d_bst2 cvmx_l2d_bst2_t;
  * L2D_BST3 = L2C Data Store QUAD3 BIST Status Register
  *
  */
-union cvmx_l2d_bst3
-{
+union cvmx_l2d_bst3 {
 	uint64_t u64;
-	struct cvmx_l2d_bst3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_bst3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t q3stat                       : 34; /**< Bist Results for QUAD3
                                                          Failure \#1 Status
@@ -386,12 +378,10 @@ typedef union cvmx_l2d_bst3 cvmx_l2d_bst3_t;
  *
  * Description: L2 Data ECC SEC/DED Errors and Interrupt Enable
  */
-union cvmx_l2d_err
-{
+union cvmx_l2d_err {
 	uint64_t u64;
-	struct cvmx_l2d_err_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_err_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t bmhclsel                     : 1;  /**< L2 Bit Map Half CacheLine ECC Selector
 
@@ -450,12 +440,10 @@ typedef union cvmx_l2d_err cvmx_l2d_err_t;
  * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data store index.
  * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
  */
-union cvmx_l2d_fadr
-{
+union cvmx_l2d_fadr {
 	uint64_t u64;
-	struct cvmx_l2d_fadr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fadr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t fadru                        : 1;  /**< Failing L2 Data Store Upper Index bit(MSB) */
 	uint64_t fowmsk                       : 4;  /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
@@ -475,9 +463,8 @@ union cvmx_l2d_fadr
 	uint64_t reserved_19_63               : 45;
 #endif
 	} s;
-	struct cvmx_l2d_fadr_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fadr_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t fowmsk                       : 4;  /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
                                                          error) */
@@ -494,9 +481,8 @@ union cvmx_l2d_fadr
 	uint64_t reserved_18_63               : 46;
 #endif
 	} cn30xx;
-	struct cvmx_l2d_fadr_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fadr_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t fowmsk                       : 4;  /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
                                                          error) */
@@ -514,9 +500,8 @@ union cvmx_l2d_fadr
 	uint64_t reserved_18_63               : 46;
 #endif
 	} cn31xx;
-	struct cvmx_l2d_fadr_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fadr_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t fowmsk                       : 4;  /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
                                                          error) */
@@ -530,9 +515,8 @@ union cvmx_l2d_fadr
 #endif
 	} cn38xx;
 	struct cvmx_l2d_fadr_cn38xx           cn38xxp2;
-	struct cvmx_l2d_fadr_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fadr_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t fowmsk                       : 4;  /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
                                                          error) */
@@ -550,9 +534,8 @@ union cvmx_l2d_fadr
 	uint64_t reserved_18_63               : 46;
 #endif
 	} cn50xx;
-	struct cvmx_l2d_fadr_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fadr_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t fowmsk                       : 4;  /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
                                                          error) */
@@ -589,12 +572,10 @@ typedef union cvmx_l2d_fadr cvmx_l2d_fadr_t;
  * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome.
  * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
  */
-union cvmx_l2d_fsyn0
-{
+union cvmx_l2d_fsyn0 {
 	uint64_t u64;
-	struct cvmx_l2d_fsyn0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fsyn0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t fsyn_ow1                     : 10; /**< Failing L2 Data Store SYNDROME OW[1,5]
                                                          When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR]
@@ -649,12 +630,10 @@ typedef union cvmx_l2d_fsyn0 cvmx_l2d_fsyn0_t;
  * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome.
  * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
  */
-union cvmx_l2d_fsyn1
-{
+union cvmx_l2d_fsyn1 {
 	uint64_t u64;
-	struct cvmx_l2d_fsyn1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fsyn1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t fsyn_ow3                     : 10; /**< Failing L2 Data Store SYNDROME OW[3,7] */
 	uint64_t fsyn_ow2                     : 10; /**< Failing L2 Data Store SYNDROME OW[2,5] */
@@ -684,12 +663,10 @@ typedef union cvmx_l2d_fsyn1 cvmx_l2d_fsyn1_t;
  * L2D_FUS0 = L2C Data Store QUAD0 Fuse Register
  *
  */
-union cvmx_l2d_fus0
-{
+union cvmx_l2d_fus0 {
 	uint64_t u64;
-	struct cvmx_l2d_fus0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fus0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t q0fus                        : 34; /**< Fuse Register for QUAD0
                                                          This is purely for debug and not needed in the general
@@ -731,12 +708,10 @@ typedef union cvmx_l2d_fus0 cvmx_l2d_fus0_t;
  * L2D_FUS1 = L2C Data Store QUAD1 Fuse Register
  *
  */
-union cvmx_l2d_fus1
-{
+union cvmx_l2d_fus1 {
 	uint64_t u64;
-	struct cvmx_l2d_fus1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fus1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t q1fus                        : 34; /**< Fuse Register for QUAD1
                                                          This is purely for debug and not needed in the general
@@ -778,12 +753,10 @@ typedef union cvmx_l2d_fus1 cvmx_l2d_fus1_t;
  * L2D_FUS2 = L2C Data Store QUAD2 Fuse Register
  *
  */
-union cvmx_l2d_fus2
-{
+union cvmx_l2d_fus2 {
 	uint64_t u64;
-	struct cvmx_l2d_fus2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fus2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t q2fus                        : 34; /**< Fuse Register for QUAD2
                                                          This is purely for debug and not needed in the general
@@ -825,12 +798,10 @@ typedef union cvmx_l2d_fus2 cvmx_l2d_fus2_t;
  * L2D_FUS3 = L2C Data Store QUAD3 Fuse Register
  *
  */
-union cvmx_l2d_fus3
-{
+union cvmx_l2d_fus3 {
 	uint64_t u64;
-	struct cvmx_l2d_fus3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fus3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t ema_ctl                      : 3;  /**< L2 Data Store EMA Control
                                                          These bits are used to 'observe' the EMA[1:0] inputs
@@ -864,9 +835,8 @@ union cvmx_l2d_fus3
 	uint64_t reserved_40_63               : 24;
 #endif
 	} s;
-	struct cvmx_l2d_fus3_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fus3_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_35_63               : 29;
 	uint64_t crip_64k                     : 1;  /**< This is purely for debug and not needed in the general
                                                          manufacturing flow.
@@ -896,9 +866,8 @@ union cvmx_l2d_fus3
 	uint64_t reserved_35_63               : 29;
 #endif
 	} cn30xx;
-	struct cvmx_l2d_fus3_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fus3_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_35_63               : 29;
 	uint64_t crip_128k                    : 1;  /**< This is purely for debug and not needed in the general
                                                          manufacturing flow.
@@ -928,9 +897,8 @@ union cvmx_l2d_fus3
 	uint64_t reserved_35_63               : 29;
 #endif
 	} cn31xx;
-	struct cvmx_l2d_fus3_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fus3_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t crip_256k                    : 1;  /**< This is purely for debug and not needed in the general
                                                          manufacturing flow.
@@ -967,9 +935,8 @@ union cvmx_l2d_fus3
 #endif
 	} cn38xx;
 	struct cvmx_l2d_fus3_cn38xx           cn38xxp2;
-	struct cvmx_l2d_fus3_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fus3_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t ema_ctl                      : 3;  /**< L2 Data Store EMA Control
                                                          These bits are used to 'observe' the EMA[2:0] inputs
@@ -1015,9 +982,8 @@ union cvmx_l2d_fus3
 	uint64_t reserved_40_63               : 24;
 #endif
 	} cn50xx;
-	struct cvmx_l2d_fus3_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fus3_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t ema_ctl                      : 3;  /**< L2 Data Store EMA Control
                                                          These bits are used to 'observe' the EMA[2:0] inputs
@@ -1064,9 +1030,8 @@ union cvmx_l2d_fus3
 #endif
 	} cn52xx;
 	struct cvmx_l2d_fus3_cn52xx           cn52xxp1;
-	struct cvmx_l2d_fus3_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fus3_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t ema_ctl                      : 3;  /**< L2 Data Store EMA Control
                                                          These bits are used to 'observe' the EMA[2:0] inputs
@@ -1115,9 +1080,8 @@ union cvmx_l2d_fus3
 #endif
 	} cn56xx;
 	struct cvmx_l2d_fus3_cn56xx           cn56xxp1;
-	struct cvmx_l2d_fus3_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2d_fus3_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_39_63               : 25;
 	uint64_t ema_ctl                      : 2;  /**< L2 Data Store EMA Control
                                                          These bits are used to 'observe' the EMA[1:0] inputs
diff --git a/sys/contrib/octeon-sdk/cvmx-l2t-defs.h b/sys/contrib/octeon-sdk/cvmx-l2t-defs.h
index d56b811..b16becf 100644
--- a/sys/contrib/octeon-sdk/cvmx-l2t-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-l2t-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_L2T_TYPEDEFS_H__
-#define __CVMX_L2T_TYPEDEFS_H__
+#ifndef __CVMX_L2T_DEFS_H__
+#define __CVMX_L2T_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_L2T_ERR CVMX_L2T_ERR_FUNC()
@@ -71,12 +71,10 @@ static inline uint64_t CVMX_L2T_ERR_FUNC(void)
  *
  * Description: L2 Tag ECC SEC/DED Errors and Interrupt Enable
  */
-union cvmx_l2t_err
-{
+union cvmx_l2t_err {
 	uint64_t u64;
-	struct cvmx_l2t_err_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2t_err_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t fadru                        : 1;  /**< Failing L2 Tag Upper Address Bit (Index[10])
                                                          When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
@@ -171,9 +169,8 @@ union cvmx_l2t_err
 	uint64_t reserved_29_63               : 35;
 #endif
 	} s;
-	struct cvmx_l2t_err_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2t_err_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t lck_intena2                  : 1;  /**< L2 Tag Lock Error2 Interrupt Enable bit */
 	uint64_t lckerr2                      : 1;  /**< HW detected a case where a Rd/Wr Miss from PP#n
@@ -268,9 +265,8 @@ union cvmx_l2t_err
 	uint64_t reserved_28_63               : 36;
 #endif
 	} cn30xx;
-	struct cvmx_l2t_err_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2t_err_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t lck_intena2                  : 1;  /**< L2 Tag Lock Error2 Interrupt Enable bit */
 	uint64_t lckerr2                      : 1;  /**< HW detected a case where a Rd/Wr Miss from PP#n
@@ -364,9 +360,8 @@ union cvmx_l2t_err
 	uint64_t reserved_28_63               : 36;
 #endif
 	} cn31xx;
-	struct cvmx_l2t_err_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2t_err_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t lck_intena2                  : 1;  /**< L2 Tag Lock Error2 Interrupt Enable bit */
 	uint64_t lckerr2                      : 1;  /**< HW detected a case where a Rd/Wr Miss from PP#n
@@ -457,9 +452,8 @@ union cvmx_l2t_err
 #endif
 	} cn38xx;
 	struct cvmx_l2t_err_cn38xx            cn38xxp2;
-	struct cvmx_l2t_err_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2t_err_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t lck_intena2                  : 1;  /**< L2 Tag Lock Error2 Interrupt Enable bit */
 	uint64_t lckerr2                      : 1;  /**< HW detected a case where a Rd/Wr Miss from PP#n
@@ -551,9 +545,8 @@ union cvmx_l2t_err
 	uint64_t reserved_28_63               : 36;
 #endif
 	} cn50xx;
-	struct cvmx_l2t_err_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_l2t_err_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t lck_intena2                  : 1;  /**< L2 Tag Lock Error2 Interrupt Enable bit */
 	uint64_t lckerr2                      : 1;  /**< HW detected a case where a Rd/Wr Miss from PP#n
diff --git a/sys/contrib/octeon-sdk/cvmx-led-defs.h b/sys/contrib/octeon-sdk/cvmx-led-defs.h
index b32c670..63b3b7c 100644
--- a/sys/contrib/octeon-sdk/cvmx-led-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-led-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_LED_TYPEDEFS_H__
-#define __CVMX_LED_TYPEDEFS_H__
+#ifndef __CVMX_LED_DEFS_H__
+#define __CVMX_LED_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_LED_BLINK CVMX_LED_BLINK_FUNC()
@@ -212,12 +212,10 @@ static inline uint64_t CVMX_LED_UDD_DAT_SETX(unsigned long offset)
  * LED_BLINK = LED Blink Rate (in led_clks)
  *
  */
-union cvmx_led_blink
-{
+union cvmx_led_blink {
 	uint64_t u64;
-	struct cvmx_led_blink_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_led_blink_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t rate                         : 8;  /**< LED Blink rate in led_latch clks
                                                          RATE must be > 0 */
@@ -248,12 +246,10 @@ typedef union cvmx_led_blink cvmx_led_blink_t;
  * or 256ns which is 3.9MHz.  The default value of 4, yields an led_clk
  * period of 64*4*2ns*2 = 1024ns or ~1MHz (977KHz).
  */
-union cvmx_led_clk_phase
-{
+union cvmx_led_clk_phase {
 	uint64_t u64;
-	struct cvmx_led_clk_phase_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_led_clk_phase_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t phase                        : 7;  /**< Number of 64 eclks in order to create the led_clk */
 #else
@@ -276,12 +272,10 @@ typedef union cvmx_led_clk_phase cvmx_led_clk_phase_t;
  * LED_CYLON = LED CYLON Effect (should remain undocumented)
  *
  */
-union cvmx_led_cylon
-{
+union cvmx_led_cylon {
 	uint64_t u64;
-	struct cvmx_led_cylon_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_led_cylon_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t rate                         : 16; /**< LED Cylon Effect when RATE!=0
                                                          Changes at RATE*LATCH period */
@@ -305,12 +299,10 @@ typedef union cvmx_led_cylon cvmx_led_cylon_t;
  * LED_DBG = LED Debug Port information
  *
  */
-union cvmx_led_dbg
-{
+union cvmx_led_dbg {
 	uint64_t u64;
-	struct cvmx_led_dbg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_led_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t dbg_en                       : 1;  /**< Add Debug Port Data to the LED shift chain
                                                          Debug Data is shifted out LSB to MSB */
@@ -363,12 +355,10 @@ typedef union cvmx_led_dbg cvmx_led_dbg_t;
  * The UDD trailer data is identical to the header data, but uses LED_UDD_CNT1
  * and LED_UDD_DAT1.
  */
-union cvmx_led_en
-{
+union cvmx_led_en {
 	uint64_t u64;
-	struct cvmx_led_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_led_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t en                           : 1;  /**< Enable the LED interface shift-chain */
 #else
@@ -391,12 +381,10 @@ typedef union cvmx_led_en cvmx_led_en_t;
  * LED_POLARITY = LED Polarity
  *
  */
-union cvmx_led_polarity
-{
+union cvmx_led_polarity {
 	uint64_t u64;
-	struct cvmx_led_polarity_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_led_polarity_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t polarity                     : 1;  /**< LED active polarity
                                                          0 = active HIGH LED
@@ -426,12 +414,10 @@ typedef union cvmx_led_polarity cvmx_led_polarity_t;
  * the PRT vector enables information of the 8 RGMII ports connected to
  * Octane.  It does not reflect the actual programmed PHY addresses.
  */
-union cvmx_led_prt
-{
+union cvmx_led_prt {
 	uint64_t u64;
-	struct cvmx_led_prt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_led_prt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t prt_en                       : 8;  /**< Which ports are enabled to display status
                                                          PRT_EN<3:0> coresponds to RGMII ports 3-0 on int0
@@ -464,12 +450,10 @@ typedef union cvmx_led_prt cvmx_led_prt_t;
  *
  * For short transfers, LEDs will remain on for at least one blink cycle
  */
-union cvmx_led_prt_fmt
-{
+union cvmx_led_prt_fmt {
 	uint64_t u64;
-	struct cvmx_led_prt_fmt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_led_prt_fmt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t format                       : 4;  /**< Port Status Information for each enabled port in
                                                          LED_PRT.  The formats are below
@@ -503,12 +487,10 @@ typedef union cvmx_led_prt_fmt cvmx_led_prt_fmt_t;
  * LED_PRT_STATUS = LED Port Status information
  *
  */
-union cvmx_led_prt_statusx
-{
+union cvmx_led_prt_statusx {
 	uint64_t u64;
-	struct cvmx_led_prt_statusx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_led_prt_statusx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t status                       : 6;  /**< Bits that software can set to be added to the
                                                          LED shift chain - depending on LED_PRT_FMT
@@ -537,12 +519,10 @@ typedef union cvmx_led_prt_statusx cvmx_led_prt_statusx_t;
  * LED_UDD_CNT = LED UDD Counts
  *
  */
-union cvmx_led_udd_cntx
-{
+union cvmx_led_udd_cntx {
 	uint64_t u64;
-	struct cvmx_led_udd_cntx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_led_udd_cntx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t cnt                          : 6;  /**< Number of bits of user-defined data to include in
                                                          the LED shift chain.  Legal values: 0-32. */
@@ -571,12 +551,10 @@ typedef union cvmx_led_udd_cntx cvmx_led_udd_cntx_t;
  * then the bits comes out LED_UDD_DAT[0], LED_UDD_DAT[1], LED_UDD_DAT[2],
  * LED_UDD_DAT[3].
  */
-union cvmx_led_udd_datx
-{
+union cvmx_led_udd_datx {
 	uint64_t u64;
-	struct cvmx_led_udd_datx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_led_udd_datx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t dat                          : 32; /**< Header or trailer UDD data to be displayed on
                                                          the LED shift chain.  Number of bits to include
@@ -601,12 +579,10 @@ typedef union cvmx_led_udd_datx cvmx_led_udd_datx_t;
  * LED_UDD_DAT_CLR = User defined data (header or trailer)
  *
  */
-union cvmx_led_udd_dat_clrx
-{
+union cvmx_led_udd_dat_clrx {
 	uint64_t u64;
-	struct cvmx_led_udd_dat_clrx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_led_udd_dat_clrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t clr                          : 32; /**< Bitwise clear for the Header or trailer UDD data to
                                                          be displayed on the LED shift chain. */
@@ -630,12 +606,10 @@ typedef union cvmx_led_udd_dat_clrx cvmx_led_udd_dat_clrx_t;
  * LED_UDD_DAT_SET = User defined data (header or trailer)
  *
  */
-union cvmx_led_udd_dat_setx
-{
+union cvmx_led_udd_dat_setx {
 	uint64_t u64;
-	struct cvmx_led_udd_dat_setx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_led_udd_dat_setx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t set                          : 32; /**< Bitwise set for the Header or trailer UDD data to
                                                          be displayed on the LED shift chain. */
diff --git a/sys/contrib/octeon-sdk/cvmx-llm.c b/sys/contrib/octeon-sdk/cvmx-llm.c
index 3d19670..01a202c 100644
--- a/sys/contrib/octeon-sdk/cvmx-llm.c
+++ b/sys/contrib/octeon-sdk/cvmx-llm.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Configuration functions for low latency memory.
  *
- * <hr>$Revision: 52372 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #include "cvmx-config.h"
 #include "cvmx.h"
@@ -154,31 +154,6 @@ int cvmx_llm_get_default_descriptor(llm_descriptor_t *llm_desc_ptr)
         llm_desc_ptr->rld0_mbytes = 128;
         llm_desc_ptr->rld1_mbytes = 128;
     }
-    else if (sys_ptr->board_type == CVMX_BOARD_TYPE_NAC38)
-    {
-        if (sys_ptr->board_rev_major == 1 && sys_ptr->board_rev_minor == 0)
-        {
-            strcpy(llm_desc_ptr->addr_rld0_fb_str, "22 21 20 00 08 07 06 05 04 13 02 01 03 09 18 17 16 15 14 10 12 11 19");
-            strcpy(llm_desc_ptr->addr_rld0_bb_str, "22 21 20 00 08 07 06 05 04 13 02 01 03 09 18 17 16 15 14 10 12 11 19");
-            strcpy(llm_desc_ptr->addr_rld1_fb_str, "22 21 20 00 08 07 06 05 04 13 02 01 03 09 18 17 16 15 14 10 12 11 19");
-            strcpy(llm_desc_ptr->addr_rld1_bb_str, "22 21 20 00 08 07 06 05 04 13 02 01 03 09 18 17 16 15 14 10 12 11 19");
-            llm_desc_ptr->rld0_bunks = 2;
-            llm_desc_ptr->rld1_bunks = 2;
-            llm_desc_ptr->rld0_mbytes = 128;
-            llm_desc_ptr->rld1_mbytes = 128;
-        }
-        else
-        {   /* Asus new recommendation  */
-            strcpy(llm_desc_ptr->addr_rld0_fb_str, "22 21 09 11 04 06 05 08 15 20 16 18 12 13 00 01 07 02 19 17 10 14 03");
-            strcpy(llm_desc_ptr->addr_rld0_bb_str, "22 21 11 09 00 01 07 02 19 17 10 14 03 13 04 06 05 08 15 20 16 18 12");
-            strcpy(llm_desc_ptr->addr_rld1_fb_str, "22 21 08 13 14 00 04 12 16 11 19 10 07 02 01 05 03 06 17 18 20 09 15");
-            strcpy(llm_desc_ptr->addr_rld1_bb_str, "22 21 13 08 01 05 03 06 17 18 20 09 15 02 14 00 04 12 16 11 19 10 07");
-            llm_desc_ptr->rld0_bunks = 2;
-            llm_desc_ptr->rld1_bunks = 2;
-            llm_desc_ptr->rld0_mbytes = 128;
-            llm_desc_ptr->rld1_mbytes = 128;
-        }
-    }
     else if (sys_ptr->board_type == CVMX_BOARD_TYPE_THUNDER)
     {
 
diff --git a/sys/contrib/octeon-sdk/cvmx-llm.h b/sys/contrib/octeon-sdk/cvmx-llm.h
index 1abec09..098c3e0 100644
--- a/sys/contrib/octeon-sdk/cvmx-llm.h
+++ b/sys/contrib/octeon-sdk/cvmx-llm.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * interface to the low latency DRAM
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-lmcx-defs.h b/sys/contrib/octeon-sdk/cvmx-lmcx-defs.h
index dbc45eb..8b3d879 100644
--- a/sys/contrib/octeon-sdk/cvmx-lmcx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-lmcx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_LMCX_TYPEDEFS_H__
-#define __CVMX_LMCX_TYPEDEFS_H__
+#ifndef __CVMX_LMCX_DEFS_H__
+#define __CVMX_LMCX_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_BIST_CTL(unsigned long block_id)
@@ -82,67 +82,91 @@ static inline uint64_t CVMX_LMCX_BIST_RESULT(unsigned long block_id)
 static inline uint64_t CVMX_LMCX_CHAR_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_CHAR_CTL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000220ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000220ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_CHAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000220ull))
+#define CVMX_LMCX_CHAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000220ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_CHAR_MASK0(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_CHAR_MASK0(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000228ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000228ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_CHAR_MASK0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000228ull))
+#define CVMX_LMCX_CHAR_MASK0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000228ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_CHAR_MASK1(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_CHAR_MASK1(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000230ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000230ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_CHAR_MASK1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000230ull))
+#define CVMX_LMCX_CHAR_MASK1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000230ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_CHAR_MASK2(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_CHAR_MASK2(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000238ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000238ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_CHAR_MASK2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000238ull))
+#define CVMX_LMCX_CHAR_MASK2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000238ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_CHAR_MASK3(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_CHAR_MASK3(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000240ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000240ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_CHAR_MASK3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000240ull))
+#define CVMX_LMCX_CHAR_MASK3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000240ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_CHAR_MASK4(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_CHAR_MASK4(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000318ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000318ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_CHAR_MASK4(block_id) (CVMX_ADD_IO_SEG(0x0001180088000318ull))
+#define CVMX_LMCX_CHAR_MASK4(block_id) (CVMX_ADD_IO_SEG(0x0001180088000318ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_COMP_CTL(unsigned long block_id)
@@ -165,34 +189,46 @@ static inline uint64_t CVMX_LMCX_COMP_CTL(unsigned long block_id)
 static inline uint64_t CVMX_LMCX_COMP_CTL2(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_COMP_CTL2(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800880001B8ull);
+	return CVMX_ADD_IO_SEG(0x00011800880001B8ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_COMP_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B8ull))
+#define CVMX_LMCX_COMP_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B8ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_CONFIG(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_CONFIG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000188ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000188ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_CONFIG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000188ull))
+#define CVMX_LMCX_CONFIG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000188ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_CONTROL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_CONTROL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000190ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000190ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_CONTROL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000190ull))
+#define CVMX_LMCX_CONTROL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000190ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_CTL(unsigned long block_id)
@@ -230,12 +266,16 @@ static inline uint64_t CVMX_LMCX_CTL1(unsigned long block_id)
 static inline uint64_t CVMX_LMCX_DCLK_CNT(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_DCLK_CNT(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800880001E0ull);
+	return CVMX_ADD_IO_SEG(0x00011800880001E0ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_DCLK_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E0ull))
+#define CVMX_LMCX_DCLK_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E0ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_DCLK_CNT_HI(unsigned long block_id)
@@ -303,12 +343,16 @@ static inline uint64_t CVMX_LMCX_DDR2_CTL(unsigned long block_id)
 static inline uint64_t CVMX_LMCX_DDR_PLL_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_DDR_PLL_CTL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000258ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000258ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_DDR_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000258ull))
+#define CVMX_LMCX_DDR_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000258ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_DELAY_CFG(unsigned long block_id)
@@ -330,23 +374,31 @@ static inline uint64_t CVMX_LMCX_DELAY_CFG(unsigned long block_id)
 static inline uint64_t CVMX_LMCX_DIMMX_PARAMS(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id == 0))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset <= 1)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 1)) && ((block_id <= 3)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset <= 1)) && ((block_id == 0))))))
 		cvmx_warn("CVMX_LMCX_DIMMX_PARAMS(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000270ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8;
+	return CVMX_ADD_IO_SEG(0x0001180088000270ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8;
 }
 #else
-#define CVMX_LMCX_DIMMX_PARAMS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000270ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
+#define CVMX_LMCX_DIMMX_PARAMS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000270ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_DIMM_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_DIMM_CTL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000310ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000310ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_DIMM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000310ull))
+#define CVMX_LMCX_DIMM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000310ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_DLL_CTL(unsigned long block_id)
@@ -364,85 +416,127 @@ static inline uint64_t CVMX_LMCX_DLL_CTL(unsigned long block_id)
 static inline uint64_t CVMX_LMCX_DLL_CTL2(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_DLL_CTL2(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800880001C8ull);
+	return CVMX_ADD_IO_SEG(0x00011800880001C8ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_DLL_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001C8ull))
+#define CVMX_LMCX_DLL_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001C8ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_DLL_CTL3(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_DLL_CTL3(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000218ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000218ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_DLL_CTL3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000218ull))
+#define CVMX_LMCX_DLL_CTL3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000218ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_DUAL_MEMCFG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_LMCX_DUAL_MEMCFG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000098ull) + ((block_id) & 1) * 0x60000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180088000098ull) + ((block_id) & 0) * 0x60000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180088000098ull) + ((block_id) & 1) * 0x60000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 3))
+				return CVMX_ADD_IO_SEG(0x0001180088000098ull) + ((block_id) & 3) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_LMCX_DUAL_MEMCFG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000098ull) + ((block_id) & 0) * 0x60000000ull;
 }
-#else
-#define CVMX_LMCX_DUAL_MEMCFG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000098ull) + ((block_id) & 1) * 0x60000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_ECC_SYND(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_LMCX_ECC_SYND(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000038ull) + ((block_id) & 1) * 0x60000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180088000038ull) + ((block_id) & 0) * 0x60000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180088000038ull) + ((block_id) & 1) * 0x60000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 3))
+				return CVMX_ADD_IO_SEG(0x0001180088000038ull) + ((block_id) & 3) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_LMCX_ECC_SYND (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000038ull) + ((block_id) & 0) * 0x60000000ull;
 }
-#else
-#define CVMX_LMCX_ECC_SYND(block_id) (CVMX_ADD_IO_SEG(0x0001180088000038ull) + ((block_id) & 1) * 0x60000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_FADR(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_LMCX_FADR(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000020ull) + ((block_id) & 1) * 0x60000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x0001180088000020ull) + ((block_id) & 0) * 0x60000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180088000020ull) + ((block_id) & 1) * 0x60000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 3))
+				return CVMX_ADD_IO_SEG(0x0001180088000020ull) + ((block_id) & 3) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_LMCX_FADR (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000020ull) + ((block_id) & 0) * 0x60000000ull;
 }
-#else
-#define CVMX_LMCX_FADR(block_id) (CVMX_ADD_IO_SEG(0x0001180088000020ull) + ((block_id) & 1) * 0x60000000ull)
-#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_IFB_CNT(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_IFB_CNT(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800880001D0ull);
+	return CVMX_ADD_IO_SEG(0x00011800880001D0ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_IFB_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D0ull))
+#define CVMX_LMCX_IFB_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D0ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_IFB_CNT_HI(unsigned long block_id)
@@ -482,23 +576,31 @@ static inline uint64_t CVMX_LMCX_IFB_CNT_LO(unsigned long block_id)
 static inline uint64_t CVMX_LMCX_INT(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_INT(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800880001F0ull);
+	return CVMX_ADD_IO_SEG(0x00011800880001F0ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F0ull))
+#define CVMX_LMCX_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F0ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_INT_EN(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_INT_EN(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800880001E8ull);
+	return CVMX_ADD_IO_SEG(0x00011800880001E8ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E8ull))
+#define CVMX_LMCX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E8ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_MEM_CFG0(unsigned long block_id)
@@ -538,48 +640,70 @@ static inline uint64_t CVMX_LMCX_MEM_CFG1(unsigned long block_id)
 static inline uint64_t CVMX_LMCX_MODEREG_PARAMS0(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_MODEREG_PARAMS0(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800880001A8ull);
+	return CVMX_ADD_IO_SEG(0x00011800880001A8ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_MODEREG_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A8ull))
+#define CVMX_LMCX_MODEREG_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A8ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_MODEREG_PARAMS1(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_MODEREG_PARAMS1(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000260ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000260ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_MODEREG_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000260ull))
+#define CVMX_LMCX_MODEREG_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000260ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_NXM(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_LMCX_NXM(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + ((block_id) & 1) * 0x60000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + ((block_id) & 0) * 0x60000000ull;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + ((block_id) & 1) * 0x60000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 3))
+				return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + ((block_id) & 3) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_LMCX_NXM (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + ((block_id) & 0) * 0x60000000ull;
 }
-#else
-#define CVMX_LMCX_NXM(block_id) (CVMX_ADD_IO_SEG(0x00011800880000C8ull) + ((block_id) & 1) * 0x60000000ull)
-#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_OPS_CNT(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_OPS_CNT(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800880001D8ull);
+	return CVMX_ADD_IO_SEG(0x00011800880001D8ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_OPS_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D8ull))
+#define CVMX_LMCX_OPS_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D8ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_OPS_CNT_HI(unsigned long block_id)
@@ -619,12 +743,16 @@ static inline uint64_t CVMX_LMCX_OPS_CNT_LO(unsigned long block_id)
 static inline uint64_t CVMX_LMCX_PHY_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_PHY_CTL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000210ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000210ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_PHY_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000210ull))
+#define CVMX_LMCX_PHY_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000210ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_PLL_BWCTL(unsigned long block_id)
@@ -707,45 +835,61 @@ static inline uint64_t CVMX_LMCX_READ_LEVEL_RANKX(unsigned long offset, unsigned
 static inline uint64_t CVMX_LMCX_RESET_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_RESET_CTL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000180ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000180ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_RESET_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000180ull))
+#define CVMX_LMCX_RESET_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000180ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_RLEVEL_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_RLEVEL_CTL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800880002A0ull);
+	return CVMX_ADD_IO_SEG(0x00011800880002A0ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_RLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A0ull))
+#define CVMX_LMCX_RLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A0ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_RLEVEL_DBG(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_RLEVEL_DBG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800880002A8ull);
+	return CVMX_ADD_IO_SEG(0x00011800880002A8ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_RLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A8ull))
+#define CVMX_LMCX_RLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A8ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_RLEVEL_RANKX(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 3)) && ((block_id <= 3)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset <= 3)) && ((block_id == 0))))))
 		cvmx_warn("CVMX_LMCX_RLEVEL_RANKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000280ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8;
+	return CVMX_ADD_IO_SEG(0x0001180088000280ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8;
 }
 #else
-#define CVMX_LMCX_RLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000280ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8)
+#define CVMX_LMCX_RLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000280ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_RODT_COMP_CTL(unsigned long block_id)
@@ -782,122 +926,205 @@ static inline uint64_t CVMX_LMCX_RODT_CTL(unsigned long block_id)
 static inline uint64_t CVMX_LMCX_RODT_MASK(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_RODT_MASK(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000268ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000268ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_RODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x0001180088000268ull))
+#define CVMX_LMCX_RODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x0001180088000268ull) + ((block_id) & 3) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_SCRAMBLED_FADR(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_SCRAMBLED_FADR(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000330ull);
+}
+#else
+#define CVMX_LMCX_SCRAMBLED_FADR(block_id) (CVMX_ADD_IO_SEG(0x0001180088000330ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_SCRAMBLE_CFG0(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_SCRAMBLE_CFG0(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000320ull);
+}
+#else
+#define CVMX_LMCX_SCRAMBLE_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000320ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_SCRAMBLE_CFG1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_SCRAMBLE_CFG1(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000328ull);
+}
+#else
+#define CVMX_LMCX_SCRAMBLE_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000328ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_SLOT_CTL0(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_SLOT_CTL0(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800880001F8ull);
+	return CVMX_ADD_IO_SEG(0x00011800880001F8ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_SLOT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F8ull))
+#define CVMX_LMCX_SLOT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F8ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_SLOT_CTL1(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_SLOT_CTL1(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000200ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000200ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_SLOT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000200ull))
+#define CVMX_LMCX_SLOT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000200ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_SLOT_CTL2(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_SLOT_CTL2(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000208ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000208ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_SLOT_CTL2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000208ull))
+#define CVMX_LMCX_SLOT_CTL2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000208ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_TIMING_PARAMS0(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_TIMING_PARAMS0(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000198ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000198ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_TIMING_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000198ull))
+#define CVMX_LMCX_TIMING_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000198ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_TIMING_PARAMS1(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_TIMING_PARAMS1(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800880001A0ull);
+	return CVMX_ADD_IO_SEG(0x00011800880001A0ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_TIMING_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A0ull))
+#define CVMX_LMCX_TIMING_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A0ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_TRO_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_TRO_CTL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000248ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000248ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_TRO_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000248ull))
+#define CVMX_LMCX_TRO_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000248ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_TRO_STAT(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_TRO_STAT(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000250ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000250ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_TRO_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180088000250ull))
+#define CVMX_LMCX_TRO_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180088000250ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_WLEVEL_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_WLEVEL_CTL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000300ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000300ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_WLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000300ull))
+#define CVMX_LMCX_WLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000300ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_WLEVEL_DBG(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_WLEVEL_DBG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x0001180088000308ull);
+	return CVMX_ADD_IO_SEG(0x0001180088000308ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_WLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000308ull))
+#define CVMX_LMCX_WLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000308ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_WLEVEL_RANKX(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 3)) && ((block_id <= 3)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset <= 3)) && ((block_id == 0))))))
 		cvmx_warn("CVMX_LMCX_WLEVEL_RANKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800880002B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8;
+	return CVMX_ADD_IO_SEG(0x00011800880002B0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8;
 }
 #else
-#define CVMX_LMCX_WLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800880002B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8)
+#define CVMX_LMCX_WLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800880002B0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_LMCX_WODT_CTL0(unsigned long block_id)
@@ -934,12 +1161,16 @@ static inline uint64_t CVMX_LMCX_WODT_CTL1(unsigned long block_id)
 static inline uint64_t CVMX_LMCX_WODT_MASK(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_LMCX_WODT_MASK(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800880001B0ull);
+	return CVMX_ADD_IO_SEG(0x00011800880001B0ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_LMCX_WODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B0ull))
+#define CVMX_LMCX_WODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B0ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 
 /**
@@ -949,12 +1180,10 @@ static inline uint64_t CVMX_LMCX_WODT_MASK(unsigned long block_id)
  * This controls BiST only for the memories that operate on DCLK.  The normal, chip-wide BiST flow
  * controls BiST for the memories that operate on ECLK.
  */
-union cvmx_lmcx_bist_ctl
-{
+union cvmx_lmcx_bist_ctl {
 	uint64_t u64;
-	struct cvmx_lmcx_bist_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_bist_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t start                        : 1;  /**< A 0->1 transition causes BiST to run. */
 #else
@@ -977,12 +1206,10 @@ typedef union cvmx_lmcx_bist_ctl cvmx_lmcx_bist_ctl_t;
  * Access to the internal BiST results
  * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
  */
-union cvmx_lmcx_bist_result
-{
+union cvmx_lmcx_bist_result {
 	uint64_t u64;
-	struct cvmx_lmcx_bist_result_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_bist_result_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t csrd2e                       : 1;  /**< BiST result of CSRD2E memory (0=pass, !0=fail) */
 	uint64_t csre2d                       : 1;  /**< BiST result of CSRE2D memory (0=pass, !0=fail) */
@@ -1002,9 +1229,8 @@ union cvmx_lmcx_bist_result
 	uint64_t reserved_11_63               : 53;
 #endif
 	} s;
-	struct cvmx_lmcx_bist_result_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_bist_result_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t mwf                          : 1;  /**< BiST result of MWF memories (0=pass, !0=fail) */
 	uint64_t mwd                          : 3;  /**< BiST result of MWD memories (0=pass, !0=fail) */
@@ -1033,12 +1259,32 @@ typedef union cvmx_lmcx_bist_result cvmx_lmcx_bist_result_t;
  * LMC_CHAR_CTL = LMC Characterization Control
  * This register is an assortment of various control fields needed to charecterize the DDR3 interface
  */
-union cvmx_lmcx_char_ctl
-{
+union cvmx_lmcx_char_ctl {
 	uint64_t u64;
-	struct cvmx_lmcx_char_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_char_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_44_63               : 20;
+	uint64_t dr                           : 1;  /**< Pattern at Data Rate (not Clock Rate) */
+	uint64_t skew_on                      : 1;  /**< Skew adjacent bits */
+	uint64_t en                           : 1;  /**< Enable characterization */
+	uint64_t sel                          : 1;  /**< Pattern select
+                                                         0 = PRBS
+                                                         1 = Programmable pattern */
+	uint64_t prog                         : 8;  /**< Programmable pattern */
+	uint64_t prbs                         : 32; /**< PRBS Polynomial */
+#else
+	uint64_t prbs                         : 32;
+	uint64_t prog                         : 8;
+	uint64_t sel                          : 1;
+	uint64_t en                           : 1;
+	uint64_t skew_on                      : 1;
+	uint64_t dr                           : 1;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_lmcx_char_ctl_s           cn61xx;
+	struct cvmx_lmcx_char_ctl_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_42_63               : 22;
 	uint64_t en                           : 1;  /**< Enable characterization */
 	uint64_t sel                          : 1;  /**< Pattern select
@@ -1053,9 +1299,12 @@ union cvmx_lmcx_char_ctl
 	uint64_t en                           : 1;
 	uint64_t reserved_42_63               : 22;
 #endif
-	} s;
-	struct cvmx_lmcx_char_ctl_s           cn63xx;
-	struct cvmx_lmcx_char_ctl_s           cn63xxp1;
+	} cn63xx;
+	struct cvmx_lmcx_char_ctl_cn63xx      cn63xxp1;
+	struct cvmx_lmcx_char_ctl_s           cn66xx;
+	struct cvmx_lmcx_char_ctl_s           cn68xx;
+	struct cvmx_lmcx_char_ctl_cn63xx      cn68xxp1;
+	struct cvmx_lmcx_char_ctl_s           cnf71xx;
 };
 typedef union cvmx_lmcx_char_ctl cvmx_lmcx_char_ctl_t;
 
@@ -1065,19 +1314,22 @@ typedef union cvmx_lmcx_char_ctl cvmx_lmcx_char_ctl_t;
  * LMC_CHAR_MASK0 = LMC Characterization Mask0
  * This register is an assortment of various control fields needed to charecterize the DDR3 interface
  */
-union cvmx_lmcx_char_mask0
-{
+union cvmx_lmcx_char_mask0 {
 	uint64_t u64;
-	struct cvmx_lmcx_char_mask0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_char_mask0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t mask                         : 64; /**< Mask for DQ0[63:0] */
 #else
 	uint64_t mask                         : 64;
 #endif
 	} s;
+	struct cvmx_lmcx_char_mask0_s         cn61xx;
 	struct cvmx_lmcx_char_mask0_s         cn63xx;
 	struct cvmx_lmcx_char_mask0_s         cn63xxp1;
+	struct cvmx_lmcx_char_mask0_s         cn66xx;
+	struct cvmx_lmcx_char_mask0_s         cn68xx;
+	struct cvmx_lmcx_char_mask0_s         cn68xxp1;
+	struct cvmx_lmcx_char_mask0_s         cnf71xx;
 };
 typedef union cvmx_lmcx_char_mask0 cvmx_lmcx_char_mask0_t;
 
@@ -1087,12 +1339,10 @@ typedef union cvmx_lmcx_char_mask0 cvmx_lmcx_char_mask0_t;
  * LMC_CHAR_MASK1 = LMC Characterization Mask1
  * This register is an assortment of various control fields needed to charecterize the DDR3 interface
  */
-union cvmx_lmcx_char_mask1
-{
+union cvmx_lmcx_char_mask1 {
 	uint64_t u64;
-	struct cvmx_lmcx_char_mask1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_char_mask1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t mask                         : 8;  /**< Mask for DQ0[71:64] */
 #else
@@ -1100,8 +1350,13 @@ union cvmx_lmcx_char_mask1
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
+	struct cvmx_lmcx_char_mask1_s         cn61xx;
 	struct cvmx_lmcx_char_mask1_s         cn63xx;
 	struct cvmx_lmcx_char_mask1_s         cn63xxp1;
+	struct cvmx_lmcx_char_mask1_s         cn66xx;
+	struct cvmx_lmcx_char_mask1_s         cn68xx;
+	struct cvmx_lmcx_char_mask1_s         cn68xxp1;
+	struct cvmx_lmcx_char_mask1_s         cnf71xx;
 };
 typedef union cvmx_lmcx_char_mask1 cvmx_lmcx_char_mask1_t;
 
@@ -1111,19 +1366,22 @@ typedef union cvmx_lmcx_char_mask1 cvmx_lmcx_char_mask1_t;
  * LMC_CHAR_MASK2 = LMC Characterization Mask2
  * This register is an assortment of various control fields needed to charecterize the DDR3 interface
  */
-union cvmx_lmcx_char_mask2
-{
+union cvmx_lmcx_char_mask2 {
 	uint64_t u64;
-	struct cvmx_lmcx_char_mask2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_char_mask2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t mask                         : 64; /**< Mask for DQ1[63:0] */
 #else
 	uint64_t mask                         : 64;
 #endif
 	} s;
+	struct cvmx_lmcx_char_mask2_s         cn61xx;
 	struct cvmx_lmcx_char_mask2_s         cn63xx;
 	struct cvmx_lmcx_char_mask2_s         cn63xxp1;
+	struct cvmx_lmcx_char_mask2_s         cn66xx;
+	struct cvmx_lmcx_char_mask2_s         cn68xx;
+	struct cvmx_lmcx_char_mask2_s         cn68xxp1;
+	struct cvmx_lmcx_char_mask2_s         cnf71xx;
 };
 typedef union cvmx_lmcx_char_mask2 cvmx_lmcx_char_mask2_t;
 
@@ -1133,12 +1391,10 @@ typedef union cvmx_lmcx_char_mask2 cvmx_lmcx_char_mask2_t;
  * LMC_CHAR_MASK3 = LMC Characterization Mask3
  * This register is an assortment of various control fields needed to charecterize the DDR3 interface
  */
-union cvmx_lmcx_char_mask3
-{
+union cvmx_lmcx_char_mask3 {
 	uint64_t u64;
-	struct cvmx_lmcx_char_mask3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_char_mask3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t mask                         : 8;  /**< Mask for DQ1[71:64] */
 #else
@@ -1146,8 +1402,13 @@ union cvmx_lmcx_char_mask3
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
+	struct cvmx_lmcx_char_mask3_s         cn61xx;
 	struct cvmx_lmcx_char_mask3_s         cn63xx;
 	struct cvmx_lmcx_char_mask3_s         cn63xxp1;
+	struct cvmx_lmcx_char_mask3_s         cn66xx;
+	struct cvmx_lmcx_char_mask3_s         cn68xx;
+	struct cvmx_lmcx_char_mask3_s         cn68xxp1;
+	struct cvmx_lmcx_char_mask3_s         cnf71xx;
 };
 typedef union cvmx_lmcx_char_mask3 cvmx_lmcx_char_mask3_t;
 
@@ -1157,12 +1418,10 @@ typedef union cvmx_lmcx_char_mask3 cvmx_lmcx_char_mask3_t;
  * LMC_CHAR_MASK4 = LMC Characterization Mask4
  * This register is an assortment of various control fields needed to charecterize the DDR3 interface
  */
-union cvmx_lmcx_char_mask4
-{
+union cvmx_lmcx_char_mask4 {
 	uint64_t u64;
-	struct cvmx_lmcx_char_mask4_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_char_mask4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_33_63               : 31;
 	uint64_t reset_n_mask                 : 1;  /**< Mask for RESET_L */
 	uint64_t a_mask                       : 16; /**< Mask for A[15:0] */
@@ -1190,8 +1449,13 @@ union cvmx_lmcx_char_mask4
 	uint64_t reserved_33_63               : 31;
 #endif
 	} s;
+	struct cvmx_lmcx_char_mask4_s         cn61xx;
 	struct cvmx_lmcx_char_mask4_s         cn63xx;
 	struct cvmx_lmcx_char_mask4_s         cn63xxp1;
+	struct cvmx_lmcx_char_mask4_s         cn66xx;
+	struct cvmx_lmcx_char_mask4_s         cn68xx;
+	struct cvmx_lmcx_char_mask4_s         cn68xxp1;
+	struct cvmx_lmcx_char_mask4_s         cnf71xx;
 };
 typedef union cvmx_lmcx_char_mask4 cvmx_lmcx_char_mask4_t;
 
@@ -1201,12 +1465,10 @@ typedef union cvmx_lmcx_char_mask4 cvmx_lmcx_char_mask4_t;
  * LMC_COMP_CTL = LMC Compensation control
  *
  */
-union cvmx_lmcx_comp_ctl
-{
+union cvmx_lmcx_comp_ctl {
 	uint64_t u64;
-	struct cvmx_lmcx_comp_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_comp_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t nctl_csr                     : 4;  /**< Compensation control bits */
 	uint64_t nctl_clk                     : 4;  /**< Compensation control bits */
@@ -1226,9 +1488,8 @@ union cvmx_lmcx_comp_ctl
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
-	struct cvmx_lmcx_comp_ctl_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_comp_ctl_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t nctl_csr                     : 4;  /**< Compensation control bits */
 	uint64_t nctl_clk                     : 4;  /**< Compensation control bits */
@@ -1253,9 +1514,8 @@ union cvmx_lmcx_comp_ctl
 	struct cvmx_lmcx_comp_ctl_cn30xx      cn31xx;
 	struct cvmx_lmcx_comp_ctl_cn30xx      cn38xx;
 	struct cvmx_lmcx_comp_ctl_cn30xx      cn38xxp2;
-	struct cvmx_lmcx_comp_ctl_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_comp_ctl_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t nctl_csr                     : 4;  /**< Compensation control bits */
 	uint64_t reserved_20_27               : 8;
@@ -1278,9 +1538,8 @@ union cvmx_lmcx_comp_ctl
 	struct cvmx_lmcx_comp_ctl_cn50xx      cn56xx;
 	struct cvmx_lmcx_comp_ctl_cn50xx      cn56xxp1;
 	struct cvmx_lmcx_comp_ctl_cn50xx      cn58xx;
-	struct cvmx_lmcx_comp_ctl_cn58xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_comp_ctl_cn58xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t nctl_csr                     : 4;  /**< Compensation control bits */
 	uint64_t reserved_20_27               : 8;
@@ -1307,12 +1566,10 @@ typedef union cvmx_lmcx_comp_ctl cvmx_lmcx_comp_ctl_t;
  * LMC_COMP_CTL2 = LMC Compensation control
  *
  */
-union cvmx_lmcx_comp_ctl2
-{
+union cvmx_lmcx_comp_ctl2 {
 	uint64_t u64;
-	struct cvmx_lmcx_comp_ctl2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_comp_ctl2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t ddr__ptune                   : 4;  /**< DDR PCTL from compensation circuit
                                                          The encoded value provides debug information for the
@@ -1336,7 +1593,7 @@ union cvmx_lmcx_comp_ctl2
                                                          0100 = 60 ohm
                                                          0101 = 120 ohm
                                                          0110-1111 = Reserved */
-	uint64_t cmd_ctl                      : 4;  /**< Drive strength control for CMD/A/RESET_L/CKE* drivers
+	uint64_t cmd_ctl                      : 4;  /**< Drive strength control for CMD/A/RESET_L drivers
                                                          0001 = 24 ohm
                                                          0010 = 26.67 ohm
                                                          0011 = 30 ohm
@@ -1345,7 +1602,7 @@ union cvmx_lmcx_comp_ctl2
                                                          0110 = 48 ohm
                                                          0111 = 60 ohm
                                                          0000,1000-1111 = Reserved */
-	uint64_t ck_ctl                       : 4;  /**< Drive strength control for CK/CS*_L/ODT drivers
+	uint64_t ck_ctl                       : 4;  /**< Drive strength control for CK/CS*_L/ODT/CKE* drivers
                                                          0001 = 24 ohm
                                                          0010 = 26.67 ohm
                                                          0011 = 30 ohm
@@ -1377,8 +1634,13 @@ union cvmx_lmcx_comp_ctl2
 	uint64_t reserved_34_63               : 30;
 #endif
 	} s;
+	struct cvmx_lmcx_comp_ctl2_s          cn61xx;
 	struct cvmx_lmcx_comp_ctl2_s          cn63xx;
 	struct cvmx_lmcx_comp_ctl2_s          cn63xxp1;
+	struct cvmx_lmcx_comp_ctl2_s          cn66xx;
+	struct cvmx_lmcx_comp_ctl2_s          cn68xx;
+	struct cvmx_lmcx_comp_ctl2_s          cn68xxp1;
+	struct cvmx_lmcx_comp_ctl2_s          cnf71xx;
 };
 typedef union cvmx_lmcx_comp_ctl2 cvmx_lmcx_comp_ctl2_t;
 
@@ -1390,7 +1652,7 @@ typedef union cvmx_lmcx_comp_ctl2 cvmx_lmcx_comp_ctl2_t;
  * This register controls certain parameters of  Memory Configuration
  *
  * Notes:
- * a. Priority order for hardware writes to LMC*_CONFIG/LMC*_FADR/LMC*_ECC_SYND: DED error >= NXM error > SEC error
+ * a. Priority order for hardware writes to LMC*_CONFIG/LMC*_FADR/LMC*_SCRAMBLED_FADR/LMC*_ECC_SYND: DED error >= NXM error > SEC error
  * b. The self refresh entry sequence(s) power the DLL up/down (depending on LMC*_MODEREG_PARAMS0[DLL])
  * when LMC*_CONFIG[SREF_WITH_DLL] is set
  * c. Prior to the self-refresh exit sequence, LMC*_MODEREG_PARAMS0 and LMC*_MODEREG_PARAMS1 should be re-programmed (if needed) to the
@@ -1421,12 +1683,271 @@ typedef union cvmx_lmcx_comp_ctl2 cvmx_lmcx_comp_ctl2_t;
  *       ]
  *    ]
  */
-union cvmx_lmcx_config
-{
+union cvmx_lmcx_config {
 	uint64_t u64;
-	struct cvmx_lmcx_config_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_config_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_61_63               : 3;
+	uint64_t mode32b                      : 1;  /**< 32b Datapath Mode                                          NS
+                                                         Set to 1 if we use only 32 DQ pins
+                                                         0 for 64b DQ mode. */
+	uint64_t scrz                         : 1;  /**< Hide LMC*_SCRAMBLE_CFG0 and LMC*_SCRAMBLE_CFG1 when set */
+	uint64_t early_unload_d1_r1           : 1;  /**< When set, unload the PHY silo one cycle early for Rank 3
+                                                         reads
+                                                         The recommended EARLY_UNLOAD_D1_R1 value can be calculated
+                                                         after the final LMC*_RLEVEL_RANK3[BYTE*] values are
+                                                         selected (as part of read-leveling initialization).
+                                                         Then, determine the largest read-leveling setting
+                                                         for rank 3 (i.e. calculate maxset=MAX(LMC*_RLEVEL_RANK3[BYTEi])
+                                                         across all i), then set EARLY_UNLOAD_D1_R1
+                                                         when the low two bits of this largest setting is not
+                                                         3 (i.e. EARLY_UNLOAD_D1_R1 = (maxset<1:0>!=3)). */
+	uint64_t early_unload_d1_r0           : 1;  /**< When set, unload the PHY silo one cycle early for Rank 2
+                                                         reads
+                                                         The recommended EARLY_UNLOAD_D1_RO value can be calculated
+                                                         after the final LMC*_RLEVEL_RANK2[BYTE*] values are
+                                                         selected (as part of read-leveling initialization).
+                                                         Then, determine the largest read-leveling setting
+                                                         for rank 2 (i.e. calculate maxset=MAX(LMC*_RLEVEL_RANK2[BYTEi])
+                                                         across all i), then set EARLY_UNLOAD_D1_RO
+                                                         when the low two bits of this largest setting is not
+                                                         3 (i.e. EARLY_UNLOAD_D1_RO = (maxset<1:0>!=3)). */
+	uint64_t early_unload_d0_r1           : 1;  /**< When set, unload the PHY silo one cycle early for Rank 1
+                                                         reads
+                                                         The recommended EARLY_UNLOAD_D0_R1 value can be calculated
+                                                         after the final LMC*_RLEVEL_RANK1[BYTE*] values are
+                                                         selected (as part of read-leveling initialization).
+                                                         Then, determine the largest read-leveling setting
+                                                         for rank 1 (i.e. calculate maxset=MAX(LMC*_RLEVEL_RANK1[BYTEi])
+                                                         across all i), then set EARLY_UNLOAD_D0_R1
+                                                         when the low two bits of this largest setting is not
+                                                         3 (i.e. EARLY_UNLOAD_D0_R1 = (maxset<1:0>!=3)). */
+	uint64_t early_unload_d0_r0           : 1;  /**< When set, unload the PHY silo one cycle early for Rank 0
+                                                         reads.
+                                                         The recommended EARLY_UNLOAD_D0_R0 value can be calculated
+                                                         after the final LMC*_RLEVEL_RANK0[BYTE*] values are
+                                                         selected (as part of read-leveling initialization).
+                                                         Then, determine the largest read-leveling setting
+                                                         for rank 0 (i.e. calculate maxset=MAX(LMC*_RLEVEL_RANK0[BYTEi])
+                                                         across all i), then set EARLY_UNLOAD_D0_R0
+                                                         when the low two bits of this largest setting is not
+                                                         3 (i.e. EARLY_UNLOAD_D0_R0 = (maxset<1:0>!=3)). */
+	uint64_t init_status                  : 4;  /**< Indicates status of initialization
+                                                         INIT_STATUS[n] = 1 implies rank n has been initialized
+                                                         SW must set necessary INIT_STATUS bits with the
+                                                         same LMC*_CONFIG write that initiates
+                                                         power-up/init and self-refresh exit sequences
+                                                         (if the required INIT_STATUS bits are not already
+                                                         set before LMC initiates the sequence).
+                                                         INIT_STATUS determines the chip-selects that assert
+                                                         during refresh, ZQCS, and precharge power-down and
+                                                         self-refresh entry/exit SEQUENCE's. */
+	uint64_t mirrmask                     : 4;  /**< Mask determining which ranks are address-mirrored.
+                                                         MIRRMASK<n> = 1 means Rank n addresses are mirrored
+                                                         for 0 <= n <= 3
+                                                         A mirrored read/write has these differences:
+                                                          - DDR_BA<1> is swapped with DDR_BA<0>
+                                                          - DDR_A<8> is swapped with DDR_A<7>
+                                                          - DDR_A<6> is swapped with DDR_A<5>
+                                                          - DDR_A<4> is swapped with DDR_A<3>
+                                                         When RANK_ENA=0, MIRRMASK<1> and MIRRMASK<3> MBZ */
+	uint64_t rankmask                     : 4;  /**< Mask to select rank to be leveled/initialized.
+                                                         To write-level/read-level/initialize rank i, set RANKMASK<i>
+                                                                         RANK_ENA=1               RANK_ENA=0
+                                                           RANKMASK<0> = DIMM0_CS0                DIMM0_CS0
+                                                           RANKMASK<1> = DIMM0_CS1                  MBZ
+                                                           RANKMASK<2> = DIMM1_CS0                DIMM1_CS0
+                                                           RANKMASK<3> = DIMM1_CS1                  MBZ
+                                                         For read/write leveling, each rank has to be leveled separately,
+                                                         so RANKMASK should only have one bit set.
+                                                         RANKMASK is not used during self-refresh entry/exit and
+                                                         precharge power-down entry/exit instruction sequences.
+                                                         When RANK_ENA=0, RANKMASK<1> and RANKMASK<3> MBZ */
+	uint64_t rank_ena                     : 1;  /**< RANK ena (for use with dual-rank DIMMs)
+                                                         For dual-rank DIMMs, the rank_ena bit will enable
+                                                         the drive of the CS*_L[1:0] and ODT_<1:0> pins differently based on the
+                                                         (pbank_lsb-1) address bit.
+                                                         Write 0 for SINGLE ranked DIMM's. */
+	uint64_t sref_with_dll                : 1;  /**< Self-refresh entry/exit write MR1 and MR2
+                                                         When set, self-refresh entry and exit instruction sequences
+                                                         write MR1 and MR2 (in all ranks). (The writes occur before
+                                                         self-refresh entry, and after self-refresh exit.)
+                                                         When clear, self-refresh entry and exit instruction sequences
+                                                         do not write any registers in the DDR3 parts. */
+	uint64_t early_dqx                    : 1;  /**< Send DQx signals one CK cycle earlier for the case when
+                                                         the shortest DQx lines have a larger delay than the CK line */
+	uint64_t sequence                     : 3;  /**< Selects the sequence that LMC runs after a 0->1
+                                                         transition on LMC*_CONFIG[INIT_START].
+                                                         SEQUENCE=0=power-up/init:
+                                                           - RANKMASK selects participating ranks (should be all ranks with attached DRAM)
+                                                           - INIT_STATUS must equal RANKMASK
+                                                           - DDR_DIMM*_CKE signals activated (if they weren't already active)
+                                                           - RDIMM register control words 0-15 will be written to RANKMASK-selected
+                                                               RDIMM's when LMC(0)_CONTROL[RDIMM_ENA]=1 and corresponding
+                                                               LMC*_DIMM_CTL[DIMM*_WMASK] bits are set. (Refer to LMC*_DIMM*_PARAMS and
+                                                               LMC*_DIMM_CTL descriptions below for more details.)
+                                                           - MR0, MR1, MR2, and MR3 will be written to selected ranks
+                                                         SEQUENCE=1=read-leveling:
+                                                           - RANKMASK selects the rank to be read-leveled
+                                                           - MR3 written to selected rank
+                                                         SEQUENCE=2=self-refresh entry:
+                                                           - INIT_STATUS selects participating ranks (should be all ranks with attached DRAM)
+                                                           - MR1 and MR2 will be written to selected ranks if SREF_WITH_DLL=1
+                                                           - DDR_DIMM*_CKE signals de-activated
+                                                         SEQUENCE=3=self-refresh exit:
+                                                           - INIT_STATUS must be set to indicate participating ranks (should be all ranks with attached DRAM)
+                                                           - DDR_DIMM*_CKE signals activated
+                                                           - MR0, MR1, MR2, and MR3 will be written to participating ranks if SREF_WITH_DLL=1
+                                                         SEQUENCE=4=precharge power-down entry:
+                                                           - INIT_STATUS selects participating ranks (should be all ranks with attached DRAM)
+                                                           - DDR_DIMM*_CKE signals de-activated
+                                                         SEQUENCE=5=precharge power-down exit:
+                                                           - INIT_STATUS selects participating ranks (should be all ranks with attached DRAM)
+                                                           - DDR_DIMM*_CKE signals activated
+                                                         SEQUENCE=6=write-leveling:
+                                                           - RANKMASK selects the rank to be write-leveled
+                                                           - INIT_STATUS must indicate all ranks with attached DRAM
+                                                           - MR1 and MR2 written to INIT_STATUS-selected ranks
+                                                         SEQUENCE=7=illegal
+                                                         Precharge power-down entry and exit SEQUENCE's may also
+                                                         be automatically generated by the HW when IDLEPOWER!=0.
+                                                         Self-refresh entry SEQUENCE's may also be automatically
+                                                         generated by hardware upon a chip warm or soft reset
+                                                         sequence when LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT] are set.
+                                                         LMC writes the LMC*_MODEREG_PARAMS0 and LMC*_MODEREG_PARAMS1 CSR field values
+                                                         to the Mode registers in the DRAM parts (i.e. MR0, MR1, MR2, and MR3) as part of some of these sequences.
+                                                         Refer to the LMC*_MODEREG_PARAMS0 and LMC*_MODEREG_PARAMS1 descriptions for more details.
+                                                         If there are two consecutive power-up/init's without
+                                                         a DRESET assertion between them, LMC asserts DDR_DIMM*_CKE as part of
+                                                         the first power-up/init, and continues to assert DDR_DIMM*_CKE
+                                                         through the remainder of the first and the second power-up/init.
+                                                         If DDR_DIMM*_CKE deactivation and reactivation is needed for
+                                                         a second power-up/init, a DRESET assertion is required
+                                                         between the first and the second. */
+	uint64_t ref_zqcs_int                 : 19; /**< Refresh & ZQCS interval represented in \#of 512 CK cycle
+                                                         increments. A Refresh sequence is triggered when bits
+                                                         [24:18] are equal to 0, and a ZQCS sequence is triggered
+                                                         when [36:18] are equal to 0.
+                                                         Program [24:18] to RND-DN(tREFI/clkPeriod/512)
+                                                         Program [36:25] to RND-DN(ZQCS_Interval/clkPeriod/(512*64)). Note
+                                                         that this value should always be greater than 32, to account for
+                                                         resistor calibration delays.
+                                                         000_00000000_00000000: RESERVED
+                                                         Max Refresh interval = 127 * 512           = 65024 CKs
+                                                         Max ZQCS interval    = (8*256*256-1) * 512 = 268434944 CKs ~ 335ms for a 800 MHz CK
+                                                         LMC*_CONFIG[INIT_STATUS] determines which ranks receive
+                                                         the REF / ZQCS. LMC does not send any refreshes / ZQCS's
+                                                         when LMC*_CONFIG[INIT_STATUS]=0. */
+	uint64_t reset                        : 1;  /**< Reset oneshot pulse for refresh counter,
+                                                         and LMC*_OPS_CNT, LMC*_IFB_CNT, and LMC*_DCLK_CNT
+                                                         CSR's. SW should write this to a one, then re-write
+                                                         it to a zero to cause the reset. */
+	uint64_t ecc_adr                      : 1;  /**< Include memory reference address in the ECC calculation
+                                                         0=disabled, 1=enabled */
+	uint64_t forcewrite                   : 4;  /**< Force the oldest outstanding write to complete after
+                                                         having waited for 2^FORCEWRITE CK cycles.  0=disabled. */
+	uint64_t idlepower                    : 3;  /**< Enter precharge power-down mode after the memory
+                                                         controller has been idle for 2^(2+IDLEPOWER) CK cycles.
+                                                         0=disabled.
+                                                         This field should only be programmed after initialization.
+                                                         LMC*_MODEREG_PARAMS0[PPD] determines whether the DRAM DLL
+                                                         is disabled during the precharge power-down. */
+	uint64_t pbank_lsb                    : 4;  /**< DIMM address bit select
+                                                         Reverting to the explanation for ROW_LSB,
+                                                         PBank_LSB would be Row_LSB bit + \#rowbits + \#rankbits
+                                                         In the 512MB DIMM Example, assuming no rank bits:
+                                                         pbank_lsb=mem_addr[15+13] for 64b mode
+                                                                  =mem_addr[14+13] for 32b mode
+                                                         Decoding for pbank_lsb
+                                                              - 0000:DIMM = mem_adr[28]    / rank = mem_adr[27] (if RANK_ENA)
+                                                              - 0001:DIMM = mem_adr[29]    / rank = mem_adr[28]      "
+                                                              - 0010:DIMM = mem_adr[30]    / rank = mem_adr[29]      "
+                                                              - 0011:DIMM = mem_adr[31]    / rank = mem_adr[30]      "
+                                                              - 0100:DIMM = mem_adr[32]    / rank = mem_adr[31]      "
+                                                              - 0101:DIMM = mem_adr[33]    / rank = mem_adr[32]      "
+                                                              - 0110:DIMM = mem_adr[34]    / rank = mem_adr[33]      "
+                                                              - 0111:DIMM = 0              / rank = mem_adr[34]      "
+                                                              - 1000-1111: RESERVED
+                                                         For example, for a DIMM made of Samsung's k4b1g0846c-f7 1Gb (16M x 8 bit x 8 bank)
+                                                         DDR3 parts, the column address width = 10, so with
+                                                         10b of col, 3b of bus, 3b of bank, row_lsb = 16. So, row = mem_adr[29:16]
+                                                         With rank_ena = 0, pbank_lsb = 2
+                                                         With rank_ena = 1, pbank_lsb = 3 */
+	uint64_t row_lsb                      : 3;  /**< Row Address bit select
+                                                         Encoding used to determine which memory address
+                                                         bit position represents the low order DDR ROW address.
+                                                         The processor's memory address[34:7] needs to be
+                                                         translated to DRAM addresses (bnk,row,col,rank and DIMM)
+                                                         and that is a function of the following:
+                                                         1. Datapath Width (64 or 32)
+                                                         2. \# Banks (8)
+                                                         3. \# Column Bits of the memory part - spec'd indirectly
+                                                         by this register.
+                                                         4. \# Row Bits of the memory part - spec'd indirectly
+                                                         5. \# Ranks in a DIMM - spec'd by RANK_ENA
+                                                         6. \# DIMM's in the system by the register below (PBANK_LSB).
+                                                         Col Address starts from mem_addr[2] for 32b (4Bytes)
+                                                         dq width or from mem_addr[3] for 64b (8Bytes) dq width
+                                                         \# col + \# bank = 12. Hence row_lsb is mem_adr[15] for
+                                                         64bmode or mem_adr[14] for 32b mode. Hence row_lsb
+                                                         parameter should be set to 001 (64b) or 000 (32b).
+                                                         Decoding for row_lsb
+                                                              - 000: row_lsb = mem_adr[14]
+                                                              - 001: row_lsb = mem_adr[15]
+                                                              - 010: row_lsb = mem_adr[16]
+                                                              - 011: row_lsb = mem_adr[17]
+                                                              - 100: row_lsb = mem_adr[18]
+                                                              - 101: row_lsb = mem_adr[19]
+                                                              - 110: row_lsb = mem_adr[20]
+                                                              - 111: RESERVED
+                                                         For example, for a DIMM made of Samsung's k4b1g0846c-f7 1Gb (16M x 8 bit x 8 bank)
+                                                         DDR3 parts, the column address width = 10, so with
+                                                         10b of col, 3b of bus, 3b of bank, row_lsb = 16. So, row = mem_adr[29:16] */
+	uint64_t ecc_ena                      : 1;  /**< ECC Enable: When set will enable the 8b ECC
+                                                         check/correct logic. Should be 1 when used with DIMMs
+                                                         with ECC. 0, otherwise.
+                                                         When this mode is turned on, DQ[71:64]
+                                                         on writes, will contain the ECC code generated for
+                                                         the 64 bits of data which will
+                                                         written in the memory and then later on reads, used
+                                                         to check for Single bit error (which will be auto-
+                                                         corrected) and Double Bit error (which will be
+                                                         reported). When not turned on, DQ[71:64]
+                                                         are driven to 0.  Please refer to SEC_ERR, DED_ERR,
+                                                         LMC*_FADR, LMC*_SCRAMBLED_FADR and LMC*_ECC_SYND registers
+                                                         for diagnostics information when there is an error. */
+	uint64_t init_start                   : 1;  /**< A 0->1 transition starts the DDR memory sequence that is
+                                                         selected by LMC*_CONFIG[SEQUENCE].  This register is a
+                                                         oneshot and clears itself each time it is set. */
+#else
+	uint64_t init_start                   : 1;
+	uint64_t ecc_ena                      : 1;
+	uint64_t row_lsb                      : 3;
+	uint64_t pbank_lsb                    : 4;
+	uint64_t idlepower                    : 3;
+	uint64_t forcewrite                   : 4;
+	uint64_t ecc_adr                      : 1;
+	uint64_t reset                        : 1;
+	uint64_t ref_zqcs_int                 : 19;
+	uint64_t sequence                     : 3;
+	uint64_t early_dqx                    : 1;
+	uint64_t sref_with_dll                : 1;
+	uint64_t rank_ena                     : 1;
+	uint64_t rankmask                     : 4;
+	uint64_t mirrmask                     : 4;
+	uint64_t init_status                  : 4;
+	uint64_t early_unload_d0_r0           : 1;
+	uint64_t early_unload_d0_r1           : 1;
+	uint64_t early_unload_d1_r0           : 1;
+	uint64_t early_unload_d1_r1           : 1;
+	uint64_t scrz                         : 1;
+	uint64_t mode32b                      : 1;
+	uint64_t reserved_61_63               : 3;
+#endif
+	} s;
+	struct cvmx_lmcx_config_s             cn61xx;
+	struct cvmx_lmcx_config_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_59_63               : 5;
 	uint64_t early_unload_d1_r1           : 1;  /**< When set, unload the PHY silo one cycle early for Rank 3
                                                          reads
@@ -1670,11 +2191,9 @@ union cvmx_lmcx_config
 	uint64_t early_unload_d1_r1           : 1;
 	uint64_t reserved_59_63               : 5;
 #endif
-	} s;
-	struct cvmx_lmcx_config_s             cn63xx;
-	struct cvmx_lmcx_config_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	} cn63xx;
+	struct cvmx_lmcx_config_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_55_63               : 9;
 	uint64_t init_status                  : 4;  /**< Indicates status of initialization
                                                          INIT_STATUS[n] = 1 implies rank n has been initialized
@@ -1875,6 +2394,257 @@ union cvmx_lmcx_config
 	uint64_t reserved_55_63               : 9;
 #endif
 	} cn63xxp1;
+	struct cvmx_lmcx_config_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_60_63               : 4;
+	uint64_t scrz                         : 1;  /**< Hide LMC*_SCRAMBLE_CFG0 and LMC*_SCRAMBLE_CFG1 when set */
+	uint64_t early_unload_d1_r1           : 1;  /**< When set, unload the PHY silo one cycle early for Rank 3
+                                                         reads
+                                                         The recommended EARLY_UNLOAD_D1_R1 value can be calculated
+                                                         after the final LMC*_RLEVEL_RANK3[BYTE*] values are
+                                                         selected (as part of read-leveling initialization).
+                                                         Then, determine the largest read-leveling setting
+                                                         for rank 3 (i.e. calculate maxset=MAX(LMC*_RLEVEL_RANK3[BYTEi])
+                                                         across all i), then set EARLY_UNLOAD_D1_R1
+                                                         when the low two bits of this largest setting is not
+                                                         3 (i.e. EARLY_UNLOAD_D1_R1 = (maxset<1:0>!=3)). */
+	uint64_t early_unload_d1_r0           : 1;  /**< When set, unload the PHY silo one cycle early for Rank 2
+                                                         reads
+                                                         The recommended EARLY_UNLOAD_D1_RO value can be calculated
+                                                         after the final LMC*_RLEVEL_RANK2[BYTE*] values are
+                                                         selected (as part of read-leveling initialization).
+                                                         Then, determine the largest read-leveling setting
+                                                         for rank 2 (i.e. calculate maxset=MAX(LMC*_RLEVEL_RANK2[BYTEi])
+                                                         across all i), then set EARLY_UNLOAD_D1_RO
+                                                         when the low two bits of this largest setting is not
+                                                         3 (i.e. EARLY_UNLOAD_D1_RO = (maxset<1:0>!=3)). */
+	uint64_t early_unload_d0_r1           : 1;  /**< When set, unload the PHY silo one cycle early for Rank 1
+                                                         reads
+                                                         The recommended EARLY_UNLOAD_D0_R1 value can be calculated
+                                                         after the final LMC*_RLEVEL_RANK1[BYTE*] values are
+                                                         selected (as part of read-leveling initialization).
+                                                         Then, determine the largest read-leveling setting
+                                                         for rank 1 (i.e. calculate maxset=MAX(LMC*_RLEVEL_RANK1[BYTEi])
+                                                         across all i), then set EARLY_UNLOAD_D0_R1
+                                                         when the low two bits of this largest setting is not
+                                                         3 (i.e. EARLY_UNLOAD_D0_R1 = (maxset<1:0>!=3)). */
+	uint64_t early_unload_d0_r0           : 1;  /**< When set, unload the PHY silo one cycle early for Rank 0
+                                                         reads.
+                                                         The recommended EARLY_UNLOAD_D0_R0 value can be calculated
+                                                         after the final LMC*_RLEVEL_RANK0[BYTE*] values are
+                                                         selected (as part of read-leveling initialization).
+                                                         Then, determine the largest read-leveling setting
+                                                         for rank 0 (i.e. calculate maxset=MAX(LMC*_RLEVEL_RANK0[BYTEi])
+                                                         across all i), then set EARLY_UNLOAD_D0_R0
+                                                         when the low two bits of this largest setting is not
+                                                         3 (i.e. EARLY_UNLOAD_D0_R0 = (maxset<1:0>!=3)). */
+	uint64_t init_status                  : 4;  /**< Indicates status of initialization
+                                                         INIT_STATUS[n] = 1 implies rank n has been initialized
+                                                         SW must set necessary INIT_STATUS bits with the
+                                                         same LMC*_CONFIG write that initiates
+                                                         power-up/init and self-refresh exit sequences
+                                                         (if the required INIT_STATUS bits are not already
+                                                         set before LMC initiates the sequence).
+                                                         INIT_STATUS determines the chip-selects that assert
+                                                         during refresh, ZQCS, and precharge power-down and
+                                                         self-refresh entry/exit SEQUENCE's. */
+	uint64_t mirrmask                     : 4;  /**< Mask determining which ranks are address-mirrored.
+                                                         MIRRMASK<n> = 1 means Rank n addresses are mirrored
+                                                         for 0 <= n <= 3
+                                                         A mirrored read/write has these differences:
+                                                          - DDR_BA<1> is swapped with DDR_BA<0>
+                                                          - DDR_A<8> is swapped with DDR_A<7>
+                                                          - DDR_A<6> is swapped with DDR_A<5>
+                                                          - DDR_A<4> is swapped with DDR_A<3>
+                                                         When RANK_ENA=0, MIRRMASK<1> and MIRRMASK<3> MBZ */
+	uint64_t rankmask                     : 4;  /**< Mask to select rank to be leveled/initialized.
+                                                         To write-level/read-level/initialize rank i, set RANKMASK<i>
+                                                                         RANK_ENA=1               RANK_ENA=0
+                                                           RANKMASK<0> = DIMM0_CS0                DIMM0_CS0
+                                                           RANKMASK<1> = DIMM0_CS1                  MBZ
+                                                           RANKMASK<2> = DIMM1_CS0                DIMM1_CS0
+                                                           RANKMASK<3> = DIMM1_CS1                  MBZ
+                                                         For read/write leveling, each rank has to be leveled separately,
+                                                         so RANKMASK should only have one bit set.
+                                                         RANKMASK is not used during self-refresh entry/exit and
+                                                         precharge power-down entry/exit instruction sequences.
+                                                         When RANK_ENA=0, RANKMASK<1> and RANKMASK<3> MBZ */
+	uint64_t rank_ena                     : 1;  /**< RANK ena (for use with dual-rank DIMMs)
+                                                         For dual-rank DIMMs, the rank_ena bit will enable
+                                                         the drive of the CS*_L[1:0] and ODT_<1:0> pins differently based on the
+                                                         (pbank_lsb-1) address bit.
+                                                         Write 0 for SINGLE ranked DIMM's. */
+	uint64_t sref_with_dll                : 1;  /**< Self-refresh entry/exit write MR1 and MR2
+                                                         When set, self-refresh entry and exit instruction sequences
+                                                         write MR1 and MR2 (in all ranks). (The writes occur before
+                                                         self-refresh entry, and after self-refresh exit.)
+                                                         When clear, self-refresh entry and exit instruction sequences
+                                                         do not write any registers in the DDR3 parts. */
+	uint64_t early_dqx                    : 1;  /**< Send DQx signals one CK cycle earlier for the case when
+                                                         the shortest DQx lines have a larger delay than the CK line */
+	uint64_t sequence                     : 3;  /**< Selects the sequence that LMC runs after a 0->1
+                                                         transition on LMC*_CONFIG[INIT_START].
+                                                         SEQUENCE=0=power-up/init:
+                                                           - RANKMASK selects participating ranks (should be all ranks with attached DRAM)
+                                                           - INIT_STATUS must equal RANKMASK
+                                                           - DDR_CKE* signals activated (if they weren't already active)
+                                                           - RDIMM register control words 0-15 will be written to RANKMASK-selected
+                                                               RDIMM's when LMC(0)_CONTROL[RDIMM_ENA]=1 and corresponding
+                                                               LMC*_DIMM_CTL[DIMM*_WMASK] bits are set. (Refer to LMC*_DIMM*_PARAMS and
+                                                               LMC*_DIMM_CTL descriptions below for more details.)
+                                                           - MR0, MR1, MR2, and MR3 will be written to selected ranks
+                                                         SEQUENCE=1=read-leveling:
+                                                           - RANKMASK selects the rank to be read-leveled
+                                                           - MR3 written to selected rank
+                                                         SEQUENCE=2=self-refresh entry:
+                                                           - INIT_STATUS selects participating ranks (should be all ranks with attached DRAM)
+                                                           - MR1 and MR2 will be written to selected ranks if SREF_WITH_DLL=1
+                                                           - DDR_CKE* signals de-activated
+                                                         SEQUENCE=3=self-refresh exit:
+                                                           - INIT_STATUS must be set to indicate participating ranks (should be all ranks with attached DRAM)
+                                                           - DDR_CKE* signals activated
+                                                           - MR0, MR1, MR2, and MR3 will be written to participating ranks if SREF_WITH_DLL=1
+                                                         SEQUENCE=4=precharge power-down entry:
+                                                           - INIT_STATUS selects participating ranks (should be all ranks with attached DRAM)
+                                                           - DDR_CKE* signals de-activated
+                                                         SEQUENCE=5=precharge power-down exit:
+                                                           - INIT_STATUS selects participating ranks (should be all ranks with attached DRAM)
+                                                           - DDR_CKE* signals activated
+                                                         SEQUENCE=6=write-leveling:
+                                                           - RANKMASK selects the rank to be write-leveled
+                                                           - INIT_STATUS must indicate all ranks with attached DRAM
+                                                           - MR1 and MR2 written to INIT_STATUS-selected ranks
+                                                         SEQUENCE=7=illegal
+                                                         Precharge power-down entry and exit SEQUENCE's may also
+                                                         be automatically generated by the HW when IDLEPOWER!=0.
+                                                         Self-refresh entry SEQUENCE's may also be automatically
+                                                         generated by hardware upon a chip warm or soft reset
+                                                         sequence when LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT] are set.
+                                                         LMC writes the LMC*_MODEREG_PARAMS0 and LMC*_MODEREG_PARAMS1 CSR field values
+                                                         to the Mode registers in the DRAM parts (i.e. MR0, MR1, MR2, and MR3) as part of some of these sequences.
+                                                         Refer to the LMC*_MODEREG_PARAMS0 and LMC*_MODEREG_PARAMS1 descriptions for more details.
+                                                         If there are two consecutive power-up/init's without
+                                                         a DRESET assertion between them, LMC asserts DDR_CKE* as part of
+                                                         the first power-up/init, and continues to assert DDR_CKE*
+                                                         through the remainder of the first and the second power-up/init.
+                                                         If DDR_CKE* deactivation and reactivation is needed for
+                                                         a second power-up/init, a DRESET assertion is required
+                                                         between the first and the second. */
+	uint64_t ref_zqcs_int                 : 19; /**< Refresh & ZQCS interval represented in \#of 512 CK cycle
+                                                         increments. A Refresh sequence is triggered when bits
+                                                         [24:18] are equal to 0, and a ZQCS sequence is triggered
+                                                         when [36:18] are equal to 0.
+                                                         Program [24:18] to RND-DN(tREFI/clkPeriod/512)
+                                                         Program [36:25] to RND-DN(ZQCS_Interval/clkPeriod/(512*64)). Note
+                                                         that this value should always be greater than 32, to account for
+                                                         resistor calibration delays.
+                                                         000_00000000_00000000: RESERVED
+                                                         Max Refresh interval = 127 * 512           = 65024 CKs
+                                                         Max ZQCS interval    = (8*256*256-1) * 512 = 268434944 CKs ~ 335ms for a 800 MHz CK
+                                                         LMC*_CONFIG[INIT_STATUS] determines which ranks receive
+                                                         the REF / ZQCS. LMC does not send any refreshes / ZQCS's
+                                                         when LMC*_CONFIG[INIT_STATUS]=0. */
+	uint64_t reset                        : 1;  /**< Reset oneshot pulse for refresh counter,
+                                                         and LMC*_OPS_CNT, LMC*_IFB_CNT, and LMC*_DCLK_CNT
+                                                         CSR's. SW should write this to a one, then re-write
+                                                         it to a zero to cause the reset. */
+	uint64_t ecc_adr                      : 1;  /**< Include memory reference address in the ECC calculation
+                                                         0=disabled, 1=enabled */
+	uint64_t forcewrite                   : 4;  /**< Force the oldest outstanding write to complete after
+                                                         having waited for 2^FORCEWRITE CK cycles.  0=disabled. */
+	uint64_t idlepower                    : 3;  /**< Enter precharge power-down mode after the memory
+                                                         controller has been idle for 2^(2+IDLEPOWER) CK cycles.
+                                                         0=disabled.
+                                                         This field should only be programmed after initialization.
+                                                         LMC*_MODEREG_PARAMS0[PPD] determines whether the DRAM DLL
+                                                         is disabled during the precharge power-down. */
+	uint64_t pbank_lsb                    : 4;  /**< DIMM address bit select
+                                                         Reverting to the explanation for ROW_LSB,
+                                                         PBank_LSB would be Row_LSB bit + \#rowbits + \#rankbits
+                                                         Decoding for pbank_lsb
+                                                              - 0000:DIMM = mem_adr[28]    / rank = mem_adr[27] (if RANK_ENA)
+                                                              - 0001:DIMM = mem_adr[29]    / rank = mem_adr[28]      "
+                                                              - 0010:DIMM = mem_adr[30]    / rank = mem_adr[29]      "
+                                                              - 0011:DIMM = mem_adr[31]    / rank = mem_adr[30]      "
+                                                              - 0100:DIMM = mem_adr[32]    / rank = mem_adr[31]      "
+                                                              - 0101:DIMM = mem_adr[33]    / rank = mem_adr[32]      "
+                                                              - 0110:DIMM = mem_adr[34]    / rank = mem_adr[33]      "
+                                                              - 0111:DIMM = 0              / rank = mem_adr[34]      "
+                                                              - 1000-1111: RESERVED
+                                                         For example, for a DIMM made of Samsung's k4b1g0846c-f7 1Gb (16M x 8 bit x 8 bank)
+                                                         DDR3 parts, the column address width = 10, so with
+                                                         10b of col, 3b of bus, 3b of bank, row_lsb = 16. So, row = mem_adr[29:16]
+                                                         With rank_ena = 0, pbank_lsb = 2
+                                                         With rank_ena = 1, pbank_lsb = 3 */
+	uint64_t row_lsb                      : 3;  /**< Row Address bit select
+                                                         Encoding used to determine which memory address
+                                                         bit position represents the low order DDR ROW address.
+                                                         The processor's memory address[34:7] needs to be
+                                                         translated to DRAM addresses (bnk,row,col,rank and DIMM)
+                                                         and that is a function of the following:
+                                                         1. Datapath Width (64)
+                                                         2. \# Banks (8)
+                                                         3. \# Column Bits of the memory part - spec'd indirectly
+                                                         by this register.
+                                                         4. \# Row Bits of the memory part - spec'd indirectly
+                                                         5. \# Ranks in a DIMM - spec'd by RANK_ENA
+                                                         6. \# DIMM's in the system by the register below (PBANK_LSB).
+                                                         Decoding for row_lsb
+                                                              - 000: row_lsb = mem_adr[14]
+                                                              - 001: row_lsb = mem_adr[15]
+                                                              - 010: row_lsb = mem_adr[16]
+                                                              - 011: row_lsb = mem_adr[17]
+                                                              - 100: row_lsb = mem_adr[18]
+                                                              - 101: row_lsb = mem_adr[19]
+                                                              - 110: row_lsb = mem_adr[20]
+                                                              - 111: RESERVED
+                                                         For example, for a DIMM made of Samsung's k4b1g0846c-f7 1Gb (16M x 8 bit x 8 bank)
+                                                         DDR3 parts, the column address width = 10, so with
+                                                         10b of col, 3b of bus, 3b of bank, row_lsb = 16. So, row = mem_adr[29:16] */
+	uint64_t ecc_ena                      : 1;  /**< ECC Enable: When set will enable the 8b ECC
+                                                         check/correct logic. Should be 1 when used with DIMMs
+                                                         with ECC. 0, otherwise.
+                                                         When this mode is turned on, DQ[71:64]
+                                                         on writes, will contain the ECC code generated for
+                                                         the 64 bits of data which will
+                                                         written in the memory and then later on reads, used
+                                                         to check for Single bit error (which will be auto-
+                                                         corrected) and Double Bit error (which will be
+                                                         reported). When not turned on, DQ[71:64]
+                                                         are driven to 0.  Please refer to SEC_ERR, DED_ERR,
+                                                         LMC*_FADR, LMC*_SCRAMBLED_FADR and LMC*_ECC_SYND registers
+                                                         for diagnostics information when there is an error. */
+	uint64_t init_start                   : 1;  /**< A 0->1 transition starts the DDR memory sequence that is
+                                                         selected by LMC*_CONFIG[SEQUENCE].  This register is a
+                                                         oneshot and clears itself each time it is set. */
+#else
+	uint64_t init_start                   : 1;
+	uint64_t ecc_ena                      : 1;
+	uint64_t row_lsb                      : 3;
+	uint64_t pbank_lsb                    : 4;
+	uint64_t idlepower                    : 3;
+	uint64_t forcewrite                   : 4;
+	uint64_t ecc_adr                      : 1;
+	uint64_t reset                        : 1;
+	uint64_t ref_zqcs_int                 : 19;
+	uint64_t sequence                     : 3;
+	uint64_t early_dqx                    : 1;
+	uint64_t sref_with_dll                : 1;
+	uint64_t rank_ena                     : 1;
+	uint64_t rankmask                     : 4;
+	uint64_t mirrmask                     : 4;
+	uint64_t init_status                  : 4;
+	uint64_t early_unload_d0_r0           : 1;
+	uint64_t early_unload_d0_r1           : 1;
+	uint64_t early_unload_d1_r0           : 1;
+	uint64_t early_unload_d1_r1           : 1;
+	uint64_t scrz                         : 1;
+	uint64_t reserved_60_63               : 4;
+#endif
+	} cn66xx;
+	struct cvmx_lmcx_config_cn63xx        cn68xx;
+	struct cvmx_lmcx_config_cn63xx        cn68xxp1;
+	struct cvmx_lmcx_config_s             cnf71xx;
 };
 typedef union cvmx_lmcx_config cvmx_lmcx_config_t;
 
@@ -1884,12 +2654,122 @@ typedef union cvmx_lmcx_config cvmx_lmcx_config_t;
  * LMC_CONTROL = LMC Control
  * This register is an assortment of various control fields needed by the memory controller
  */
-union cvmx_lmcx_control
-{
+union cvmx_lmcx_control {
 	uint64_t u64;
-	struct cvmx_lmcx_control_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t scramble_ena                 : 1;  /**< When set, will enable the scramble/descramble logic */
+	uint64_t thrcnt                       : 12; /**< Fine Count */
+	uint64_t persub                       : 8;  /**< Offset for DFA rate-matching */
+	uint64_t thrmax                       : 4;  /**< Fine Rate Matching Max Bucket Size
+                                                         0 = Reserved
+                                                         In conjunction with the Coarse Rate Matching Logic, the Fine Rate
+                                                         Matching Logic gives SW the ability to prioritize DFA Rds over
+                                                         L2C Writes. Higher PERSUB values result in a lower DFA Rd
+                                                         bandwidth. */
+	uint64_t crm_cnt                      : 5;  /**< Coarse Count */
+	uint64_t crm_thr                      : 5;  /**< Coarse Rate Matching Threshold */
+	uint64_t crm_max                      : 5;  /**< Coarse Rate Matching Max Bucket Size
+                                                         0 = Reserved
+                                                         The Coarse Rate Matching Logic is used to control the bandwidth
+                                                         allocated to DFA Rds. CRM_MAX is subdivided into two regions
+                                                         with DFA Rds being preferred over LMC Rd/Wrs when
+                                                         CRM_CNT < CRM_THR. CRM_CNT increments by 1 when a DFA Rd is
+                                                         slotted and by 2 when a LMC Rd/Wr is slotted, and rolls over
+                                                         when CRM_MAX is reached. */
+	uint64_t rodt_bprch                   : 1;  /**< When set, the turn-off time for the ODT pin during a
+                                                         RD cmd is delayed an additional CK cycle. */
+	uint64_t wodt_bprch                   : 1;  /**< When set, the turn-off time for the ODT pin during a
+                                                         WR cmd is delayed an additional CK cycle. */
+	uint64_t bprch                        : 2;  /**< Back Porch Enable: When set, the turn-on time for
+                                                         the default DDR_DQ/DQS drivers is delayed an additional BPRCH
+                                                         CK cycles.
+                                                         00 = 0 CKs
+                                                         01 = 1 CKs
+                                                         10 = 2 CKs
+                                                         11 = 3 CKs */
+	uint64_t ext_zqcs_dis                 : 1;  /**< Disable (external) auto-zqcs calibration
+                                                         When clear, LMC runs external ZQ calibration
+                                                         every LMC*_CONFIG[REF_ZQCS_INT] CK cycles. */
+	uint64_t int_zqcs_dis                 : 1;  /**< Disable (internal) auto-zqcs calibration
+                                                         When clear, LMC runs internal ZQ calibration
+                                                         every LMC*_CONFIG[REF_ZQCS_INT] CK cycles. */
+	uint64_t auto_dclkdis                 : 1;  /**< When 1, LMC will automatically shut off its internal
+                                                         clock to conserve power when there is no traffic. Note
+                                                         that this has no effect on the DDR3 PHY and pads clocks. */
+	uint64_t xor_bank                     : 1;  /**< If (XOR_BANK == 1), then
+                                                          bank[2:0]=address[9:7] ^ address[14:12]
+                                                         else
+                                                          bank[2:0]=address[9:7] */
+	uint64_t max_write_batch              : 4;  /**< Maximum number of consecutive writes to service before
+                                                         forcing reads to interrupt. */
+	uint64_t nxm_write_en                 : 1;  /**< NXM Write mode
+                                                         When clear, LMC discards writes to addresses that don't
+                                                         exist in the DRAM (as defined by LMC*_NXM configuration).
+                                                         When set, LMC completes writes to addresses that don't
+                                                         exist in the DRAM at an aliased address. */
+	uint64_t elev_prio_dis                : 1;  /**< Disable elevate priority logic.
+                                                         When set, writes are sent in
+                                                         regardless of priority information from L2C. */
+	uint64_t inorder_wr                   : 1;  /**< Send writes in order(regardless of priority) */
+	uint64_t inorder_rd                   : 1;  /**< Send reads in order (regardless of priority) */
+	uint64_t throttle_wr                  : 1;  /**< When set, use at most one IFB for writes */
+	uint64_t throttle_rd                  : 1;  /**< When set, use at most one IFB for reads */
+	uint64_t fprch2                       : 2;  /**< Front Porch Enable: When set, the turn-off
+                                                         time for the default DDR_DQ/DQS drivers is FPRCH2 CKs earlier.
+                                                         00 = 0 CKs
+                                                         01 = 1 CKs
+                                                         10 = 2 CKs
+                                                         11 = RESERVED */
+	uint64_t pocas                        : 1;  /**< Enable the Posted CAS feature of DDR3.
+                                                         This bit must be set whenever LMC*_MODEREG_PARAMS0[AL]!=0,
+                                                         and clear otherwise. */
+	uint64_t ddr2t                        : 1;  /**< Turn on the DDR 2T mode. 2 CK cycle window for CMD and
+                                                         address. This mode helps relieve setup time pressure
+                                                         on the Address and command bus which nominally have
+                                                         a very large fanout. Please refer to Micron's tech
+                                                         note tn_47_01 titled "DDR2-533 Memory Design Guide
+                                                         for Two Dimm Unbuffered Systems" for physical details. */
+	uint64_t bwcnt                        : 1;  /**< Bus utilization counter Clear.
+                                                         Clears the LMC*_OPS_CNT, LMC*_IFB_CNT, and
+                                                         LMC*_DCLK_CNT registers. SW should first write this
+                                                         field to a one, then write this field to a zero to
+                                                         clear the CSR's. */
+	uint64_t rdimm_ena                    : 1;  /**< Registered DIMM Enable - When set allows the use
+                                                         of JEDEC Registered DIMMs which require address and
+                                                         control bits to be registered in the controller. */
+#else
+	uint64_t rdimm_ena                    : 1;
+	uint64_t bwcnt                        : 1;
+	uint64_t ddr2t                        : 1;
+	uint64_t pocas                        : 1;
+	uint64_t fprch2                       : 2;
+	uint64_t throttle_rd                  : 1;
+	uint64_t throttle_wr                  : 1;
+	uint64_t inorder_rd                   : 1;
+	uint64_t inorder_wr                   : 1;
+	uint64_t elev_prio_dis                : 1;
+	uint64_t nxm_write_en                 : 1;
+	uint64_t max_write_batch              : 4;
+	uint64_t xor_bank                     : 1;
+	uint64_t auto_dclkdis                 : 1;
+	uint64_t int_zqcs_dis                 : 1;
+	uint64_t ext_zqcs_dis                 : 1;
+	uint64_t bprch                        : 2;
+	uint64_t wodt_bprch                   : 1;
+	uint64_t rodt_bprch                   : 1;
+	uint64_t crm_max                      : 5;
+	uint64_t crm_thr                      : 5;
+	uint64_t crm_cnt                      : 5;
+	uint64_t thrmax                       : 4;
+	uint64_t persub                       : 8;
+	uint64_t thrcnt                       : 12;
+	uint64_t scramble_ena                 : 1;
+#endif
+	} s;
+	struct cvmx_lmcx_control_s            cn61xx;
+	struct cvmx_lmcx_control_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t rodt_bprch                   : 1;  /**< When set, the turn-off time for the ODT pin during a
                                                          RD cmd is delayed an additional CK cycle. */
@@ -1974,9 +2854,210 @@ union cvmx_lmcx_control
 	uint64_t rodt_bprch                   : 1;
 	uint64_t reserved_24_63               : 40;
 #endif
-	} s;
-	struct cvmx_lmcx_control_s            cn63xx;
-	struct cvmx_lmcx_control_s            cn63xxp1;
+	} cn63xx;
+	struct cvmx_lmcx_control_cn63xx       cn63xxp1;
+	struct cvmx_lmcx_control_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t scramble_ena                 : 1;  /**< When set, will enable the scramble/descramble logic */
+	uint64_t reserved_24_62               : 39;
+	uint64_t rodt_bprch                   : 1;  /**< When set, the turn-off time for the ODT pin during a
+                                                         RD cmd is delayed an additional CK cycle. */
+	uint64_t wodt_bprch                   : 1;  /**< When set, the turn-off time for the ODT pin during a
+                                                         WR cmd is delayed an additional CK cycle. */
+	uint64_t bprch                        : 2;  /**< Back Porch Enable: When set, the turn-on time for
+                                                         the default DDR_DQ/DQS drivers is delayed an additional BPRCH
+                                                         CK cycles.
+                                                         00 = 0 CKs
+                                                         01 = 1 CKs
+                                                         10 = 2 CKs
+                                                         11 = 3 CKs */
+	uint64_t ext_zqcs_dis                 : 1;  /**< Disable (external) auto-zqcs calibration
+                                                         When clear, LMC runs external ZQ calibration
+                                                         every LMC*_CONFIG[REF_ZQCS_INT] CK cycles. */
+	uint64_t int_zqcs_dis                 : 1;  /**< Disable (internal) auto-zqcs calibration
+                                                         When clear, LMC runs internal ZQ calibration
+                                                         every LMC*_CONFIG[REF_ZQCS_INT] CK cycles. */
+	uint64_t auto_dclkdis                 : 1;  /**< When 1, LMC will automatically shut off its internal
+                                                         clock to conserve power when there is no traffic. Note
+                                                         that this has no effect on the DDR3 PHY and pads clocks. */
+	uint64_t xor_bank                     : 1;  /**< If (XOR_BANK == 1), then
+                                                          bank[2:0]=address[9:7] ^ address[14:12]
+                                                         else
+                                                          bank[2:0]=address[9:7] */
+	uint64_t max_write_batch              : 4;  /**< Maximum number of consecutive writes to service before
+                                                         forcing reads to interrupt. */
+	uint64_t nxm_write_en                 : 1;  /**< NXM Write mode
+                                                         When clear, LMC discards writes to addresses that don't
+                                                         exist in the DRAM (as defined by LMC*_NXM configuration).
+                                                         When set, LMC completes writes to addresses that don't
+                                                         exist in the DRAM at an aliased address. */
+	uint64_t elev_prio_dis                : 1;  /**< Disable elevate priority logic.
+                                                         When set, writes are sent in
+                                                         regardless of priority information from L2C. */
+	uint64_t inorder_wr                   : 1;  /**< Send writes in order(regardless of priority) */
+	uint64_t inorder_rd                   : 1;  /**< Send reads in order (regardless of priority) */
+	uint64_t throttle_wr                  : 1;  /**< When set, use at most one IFB for writes */
+	uint64_t throttle_rd                  : 1;  /**< When set, use at most one IFB for reads */
+	uint64_t fprch2                       : 2;  /**< Front Porch Enable: When set, the turn-off
+                                                         time for the default DDR_DQ/DQS drivers is FPRCH2 CKs earlier.
+                                                         00 = 0 CKs
+                                                         01 = 1 CKs
+                                                         10 = 2 CKs
+                                                         11 = RESERVED */
+	uint64_t pocas                        : 1;  /**< Enable the Posted CAS feature of DDR3.
+                                                         This bit must be set whenever LMC*_MODEREG_PARAMS0[AL]!=0,
+                                                         and clear otherwise. */
+	uint64_t ddr2t                        : 1;  /**< Turn on the DDR 2T mode. 2 CK cycle window for CMD and
+                                                         address. This mode helps relieve setup time pressure
+                                                         on the Address and command bus which nominally have
+                                                         a very large fanout. Please refer to Micron's tech
+                                                         note tn_47_01 titled "DDR2-533 Memory Design Guide
+                                                         for Two Dimm Unbuffered Systems" for physical details. */
+	uint64_t bwcnt                        : 1;  /**< Bus utilization counter Clear.
+                                                         Clears the LMC*_OPS_CNT, LMC*_IFB_CNT, and
+                                                         LMC*_DCLK_CNT registers. SW should first write this
+                                                         field to a one, then write this field to a zero to
+                                                         clear the CSR's. */
+	uint64_t rdimm_ena                    : 1;  /**< Registered DIMM Enable - When set allows the use
+                                                         of JEDEC Registered DIMMs which require address and
+                                                         control bits to be registered in the controller. */
+#else
+	uint64_t rdimm_ena                    : 1;
+	uint64_t bwcnt                        : 1;
+	uint64_t ddr2t                        : 1;
+	uint64_t pocas                        : 1;
+	uint64_t fprch2                       : 2;
+	uint64_t throttle_rd                  : 1;
+	uint64_t throttle_wr                  : 1;
+	uint64_t inorder_rd                   : 1;
+	uint64_t inorder_wr                   : 1;
+	uint64_t elev_prio_dis                : 1;
+	uint64_t nxm_write_en                 : 1;
+	uint64_t max_write_batch              : 4;
+	uint64_t xor_bank                     : 1;
+	uint64_t auto_dclkdis                 : 1;
+	uint64_t int_zqcs_dis                 : 1;
+	uint64_t ext_zqcs_dis                 : 1;
+	uint64_t bprch                        : 2;
+	uint64_t wodt_bprch                   : 1;
+	uint64_t rodt_bprch                   : 1;
+	uint64_t reserved_24_62               : 39;
+	uint64_t scramble_ena                 : 1;
+#endif
+	} cn66xx;
+	struct cvmx_lmcx_control_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_63_63               : 1;
+	uint64_t thrcnt                       : 12; /**< Fine Count */
+	uint64_t persub                       : 8;  /**< Offset for DFA rate-matching */
+	uint64_t thrmax                       : 4;  /**< Fine Rate Matching Max Bucket Size
+                                                         0 = Reserved
+                                                         In conjunction with the Coarse Rate Matching Logic, the Fine Rate
+                                                         Matching Logic gives SW the ability to prioritize DFA Rds over
+                                                         L2C Writes. Higher PERSUB values result in a lower DFA Rd
+                                                         bandwidth. */
+	uint64_t crm_cnt                      : 5;  /**< Coarse Count */
+	uint64_t crm_thr                      : 5;  /**< Coarse Rate Matching Threshold */
+	uint64_t crm_max                      : 5;  /**< Coarse Rate Matching Max Bucket Size
+                                                         0 = Reserved
+                                                         The Coarse Rate Matching Logic is used to control the bandwidth
+                                                         allocated to DFA Rds. CRM_MAX is subdivided into two regions
+                                                         with DFA Rds being preferred over LMC Rd/Wrs when
+                                                         CRM_CNT < CRM_THR. CRM_CNT increments by 1 when a DFA Rd is
+                                                         slotted and by 2 when a LMC Rd/Wr is slotted, and rolls over
+                                                         when CRM_MAX is reached. */
+	uint64_t rodt_bprch                   : 1;  /**< When set, the turn-off time for the ODT pin during a
+                                                         RD cmd is delayed an additional CK cycle. */
+	uint64_t wodt_bprch                   : 1;  /**< When set, the turn-off time for the ODT pin during a
+                                                         WR cmd is delayed an additional CK cycle. */
+	uint64_t bprch                        : 2;  /**< Back Porch Enable: When set, the turn-on time for
+                                                         the default DDR_DQ/DQS drivers is delayed an additional BPRCH
+                                                         CK cycles.
+                                                         00 = 0 CKs
+                                                         01 = 1 CKs
+                                                         10 = 2 CKs
+                                                         11 = 3 CKs */
+	uint64_t ext_zqcs_dis                 : 1;  /**< Disable (external) auto-zqcs calibration
+                                                         When clear, LMC runs external ZQ calibration
+                                                         every LMC*_CONFIG[REF_ZQCS_INT] CK cycles. */
+	uint64_t int_zqcs_dis                 : 1;  /**< Disable (internal) auto-zqcs calibration
+                                                         When clear, LMC runs internal ZQ calibration
+                                                         every LMC*_CONFIG[REF_ZQCS_INT] CK cycles. */
+	uint64_t auto_dclkdis                 : 1;  /**< When 1, LMC will automatically shut off its internal
+                                                         clock to conserve power when there is no traffic. Note
+                                                         that this has no effect on the DDR3 PHY and pads clocks. */
+	uint64_t xor_bank                     : 1;  /**< If (XOR_BANK == 1), then
+                                                          bank[2:0]=address[9:7] ^ address[14:12]
+                                                         else
+                                                          bank[2:0]=address[9:7] */
+	uint64_t max_write_batch              : 4;  /**< Maximum number of consecutive writes to service before
+                                                         forcing reads to interrupt. */
+	uint64_t nxm_write_en                 : 1;  /**< NXM Write mode
+                                                         When clear, LMC discards writes to addresses that don't
+                                                         exist in the DRAM (as defined by LMC*_NXM configuration).
+                                                         When set, LMC completes writes to addresses that don't
+                                                         exist in the DRAM at an aliased address. */
+	uint64_t elev_prio_dis                : 1;  /**< Disable elevate priority logic.
+                                                         When set, writes are sent in
+                                                         regardless of priority information from L2C. */
+	uint64_t inorder_wr                   : 1;  /**< Send writes in order(regardless of priority) */
+	uint64_t inorder_rd                   : 1;  /**< Send reads in order (regardless of priority) */
+	uint64_t throttle_wr                  : 1;  /**< When set, use at most one IFB for writes */
+	uint64_t throttle_rd                  : 1;  /**< When set, use at most one IFB for reads */
+	uint64_t fprch2                       : 2;  /**< Front Porch Enable: When set, the turn-off
+                                                         time for the default DDR_DQ/DQS drivers is FPRCH2 CKs earlier.
+                                                         00 = 0 CKs
+                                                         01 = 1 CKs
+                                                         10 = 2 CKs
+                                                         11 = RESERVED */
+	uint64_t pocas                        : 1;  /**< Enable the Posted CAS feature of DDR3.
+                                                         This bit must be set whenever LMC*_MODEREG_PARAMS0[AL]!=0,
+                                                         and clear otherwise. */
+	uint64_t ddr2t                        : 1;  /**< Turn on the DDR 2T mode. 2 CK cycle window for CMD and
+                                                         address. This mode helps relieve setup time pressure
+                                                         on the Address and command bus which nominally have
+                                                         a very large fanout. Please refer to Micron's tech
+                                                         note tn_47_01 titled "DDR2-533 Memory Design Guide
+                                                         for Two Dimm Unbuffered Systems" for physical details. */
+	uint64_t bwcnt                        : 1;  /**< Bus utilization counter Clear.
+                                                         Clears the LMC*_OPS_CNT, LMC*_IFB_CNT, and
+                                                         LMC*_DCLK_CNT registers. SW should first write this
+                                                         field to a one, then write this field to a zero to
+                                                         clear the CSR's. */
+	uint64_t rdimm_ena                    : 1;  /**< Registered DIMM Enable - When set allows the use
+                                                         of JEDEC Registered DIMMs which require address and
+                                                         control bits to be registered in the controller. */
+#else
+	uint64_t rdimm_ena                    : 1;
+	uint64_t bwcnt                        : 1;
+	uint64_t ddr2t                        : 1;
+	uint64_t pocas                        : 1;
+	uint64_t fprch2                       : 2;
+	uint64_t throttle_rd                  : 1;
+	uint64_t throttle_wr                  : 1;
+	uint64_t inorder_rd                   : 1;
+	uint64_t inorder_wr                   : 1;
+	uint64_t elev_prio_dis                : 1;
+	uint64_t nxm_write_en                 : 1;
+	uint64_t max_write_batch              : 4;
+	uint64_t xor_bank                     : 1;
+	uint64_t auto_dclkdis                 : 1;
+	uint64_t int_zqcs_dis                 : 1;
+	uint64_t ext_zqcs_dis                 : 1;
+	uint64_t bprch                        : 2;
+	uint64_t wodt_bprch                   : 1;
+	uint64_t rodt_bprch                   : 1;
+	uint64_t crm_max                      : 5;
+	uint64_t crm_thr                      : 5;
+	uint64_t crm_cnt                      : 5;
+	uint64_t thrmax                       : 4;
+	uint64_t persub                       : 8;
+	uint64_t thrcnt                       : 12;
+	uint64_t reserved_63_63               : 1;
+#endif
+	} cn68xx;
+	struct cvmx_lmcx_control_cn68xx       cn68xxp1;
+	struct cvmx_lmcx_control_cn66xx       cnf71xx;
 };
 typedef union cvmx_lmcx_control cvmx_lmcx_control_t;
 
@@ -1986,12 +3067,10 @@ typedef union cvmx_lmcx_control cvmx_lmcx_control_t;
  * LMC_CTL = LMC Control
  * This register is an assortment of various control fields needed by the memory controller
  */
-union cvmx_lmcx_ctl
-{
+union cvmx_lmcx_ctl {
 	uint64_t u64;
-	struct cvmx_lmcx_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t ddr__nctl                    : 4;  /**< DDR nctl from compensation circuit
                                                          The encoded value on this will adjust the drive strength
@@ -2096,9 +3175,8 @@ union cvmx_lmcx_ctl
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
-	struct cvmx_lmcx_ctl_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ctl_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t ddr__nctl                    : 4;  /**< DDR nctl from compensation circuit
                                                          The encoded value on this will adjust the drive strength
@@ -2212,9 +3290,8 @@ union cvmx_lmcx_ctl
 #endif
 	} cn30xx;
 	struct cvmx_lmcx_ctl_cn30xx           cn31xx;
-	struct cvmx_lmcx_ctl_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ctl_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t ddr__nctl                    : 4;  /**< DDR nctl from compensation circuit
                                                          The encoded value on this will adjust the drive strength
@@ -2344,9 +3421,8 @@ union cvmx_lmcx_ctl
 #endif
 	} cn38xx;
 	struct cvmx_lmcx_ctl_cn38xx           cn38xxp2;
-	struct cvmx_lmcx_ctl_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ctl_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t ddr__nctl                    : 4;  /**< DDR nctl from compensation circuit
                                                          The encoded value on this will adjust the drive strength
@@ -2456,9 +3532,8 @@ union cvmx_lmcx_ctl
 	uint64_t reserved_32_63               : 32;
 #endif
 	} cn50xx;
-	struct cvmx_lmcx_ctl_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ctl_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t ddr__nctl                    : 4;  /**< DDR nctl from compensation circuit
                                                          The encoded value on this will adjust the drive strength
@@ -2571,9 +3646,8 @@ union cvmx_lmcx_ctl
 	struct cvmx_lmcx_ctl_cn52xx           cn52xxp1;
 	struct cvmx_lmcx_ctl_cn52xx           cn56xx;
 	struct cvmx_lmcx_ctl_cn52xx           cn56xxp1;
-	struct cvmx_lmcx_ctl_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ctl_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t ddr__nctl                    : 4;  /**< DDR nctl from compensation circuit
                                                          The encoded value on this will adjust the drive strength
@@ -2691,12 +3765,10 @@ typedef union cvmx_lmcx_ctl cvmx_lmcx_ctl_t;
  * LMC_CTL1 = LMC Control1
  * This register is an assortment of various control fields needed by the memory controller
  */
-union cvmx_lmcx_ctl1
-{
+union cvmx_lmcx_ctl1 {
 	uint64_t u64;
-	struct cvmx_lmcx_ctl1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ctl1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_21_63               : 43;
 	uint64_t ecc_adr                      : 1;  /**< Include memory reference address in the ECC calculation
                                                          0=disabled, 1=enabled */
@@ -2737,9 +3809,8 @@ union cvmx_lmcx_ctl1
 	uint64_t reserved_21_63               : 43;
 #endif
 	} s;
-	struct cvmx_lmcx_ctl1_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ctl1_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t data_layout                  : 2;  /**< Logical data layout per DQ byte lane:
                                                          In 32b mode, this setting has no effect and the data
@@ -2756,9 +3827,8 @@ union cvmx_lmcx_ctl1
 	uint64_t reserved_2_63                : 62;
 #endif
 	} cn30xx;
-	struct cvmx_lmcx_ctl1_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ctl1_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t sil_mode                     : 1;  /**< Read Silo mode.  0=envelope, 1=self-timed. */
 	uint64_t dcc_enable                   : 1;  /**< Duty Cycle Corrector Enable.
@@ -2784,9 +3854,8 @@ union cvmx_lmcx_ctl1
 	uint64_t reserved_10_63               : 54;
 #endif
 	} cn50xx;
-	struct cvmx_lmcx_ctl1_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ctl1_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_21_63               : 43;
 	uint64_t ecc_adr                      : 1;  /**< Include memory reference address in the ECC calculation
                                                          0=disabled, 1=enabled */
@@ -2819,9 +3888,8 @@ union cvmx_lmcx_ctl1
 	struct cvmx_lmcx_ctl1_cn52xx          cn52xxp1;
 	struct cvmx_lmcx_ctl1_cn52xx          cn56xx;
 	struct cvmx_lmcx_ctl1_cn52xx          cn56xxp1;
-	struct cvmx_lmcx_ctl1_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ctl1_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t sil_mode                     : 1;  /**< Read Silo mode.  0=envelope, 1=self-timed. */
 	uint64_t dcc_enable                   : 1;  /**< Duty Cycle Corrector Enable.
@@ -2846,20 +3914,23 @@ typedef union cvmx_lmcx_ctl1 cvmx_lmcx_ctl1_t;
  * LMC_DCLK_CNT  = Performance Counters
  *
  */
-union cvmx_lmcx_dclk_cnt
-{
+union cvmx_lmcx_dclk_cnt {
 	uint64_t u64;
-	struct cvmx_lmcx_dclk_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_dclk_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t dclkcnt                      : 64; /**< Performance Counter
                                                          64-bit counter that increments every CK cycle */
 #else
 	uint64_t dclkcnt                      : 64;
 #endif
 	} s;
+	struct cvmx_lmcx_dclk_cnt_s           cn61xx;
 	struct cvmx_lmcx_dclk_cnt_s           cn63xx;
 	struct cvmx_lmcx_dclk_cnt_s           cn63xxp1;
+	struct cvmx_lmcx_dclk_cnt_s           cn66xx;
+	struct cvmx_lmcx_dclk_cnt_s           cn68xx;
+	struct cvmx_lmcx_dclk_cnt_s           cn68xxp1;
+	struct cvmx_lmcx_dclk_cnt_s           cnf71xx;
 };
 typedef union cvmx_lmcx_dclk_cnt cvmx_lmcx_dclk_cnt_t;
 
@@ -2869,12 +3940,10 @@ typedef union cvmx_lmcx_dclk_cnt cvmx_lmcx_dclk_cnt_t;
  * LMC_DCLK_CNT_HI  = Performance Counters
  *
  */
-union cvmx_lmcx_dclk_cnt_hi
-{
+union cvmx_lmcx_dclk_cnt_hi {
 	uint64_t u64;
-	struct cvmx_lmcx_dclk_cnt_hi_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_dclk_cnt_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t dclkcnt_hi                   : 32; /**< Performance Counter that counts dclks
                                                          Upper 32-bits of a 64-bit counter. */
@@ -2903,12 +3972,10 @@ typedef union cvmx_lmcx_dclk_cnt_hi cvmx_lmcx_dclk_cnt_hi_t;
  * LMC_DCLK_CNT_LO  = Performance Counters
  *
  */
-union cvmx_lmcx_dclk_cnt_lo
-{
+union cvmx_lmcx_dclk_cnt_lo {
 	uint64_t u64;
-	struct cvmx_lmcx_dclk_cnt_lo_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_dclk_cnt_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t dclkcnt_lo                   : 32; /**< Performance Counter that counts dclks
                                                          Lower 32-bits of a 64-bit counter. */
@@ -2941,12 +4008,10 @@ typedef union cvmx_lmcx_dclk_cnt_lo cvmx_lmcx_dclk_cnt_lo_t;
  * This CSR is only relevant for LMC1. LMC0_DCLK_CTL is not used.
  *
  */
-union cvmx_lmcx_dclk_ctl
-{
+union cvmx_lmcx_dclk_ctl {
 	uint64_t u64;
-	struct cvmx_lmcx_dclk_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_dclk_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t off90_ena                    : 1;  /**< 0=use global DCLK (i.e. the PLL) directly for LMC1
                                                          1=use the 90 degree DCLK DLL to offset LMC1 DCLK */
@@ -2978,12 +4043,10 @@ typedef union cvmx_lmcx_dclk_ctl cvmx_lmcx_dclk_ctl_t;
  * LMC_DDR2_CTL = LMC DDR2 & DLL Control Register
  *
  */
-union cvmx_lmcx_ddr2_ctl
-{
+union cvmx_lmcx_ddr2_ctl {
 	uint64_t u64;
-	struct cvmx_lmcx_ddr2_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ddr2_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t bank8                        : 1;  /**< For 8 bank DDR2 parts
                                                          1 - DDR2 parts have 8 internal banks (BA is 3 bits
@@ -3097,9 +4160,8 @@ union cvmx_lmcx_ddr2_ctl
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
-	struct cvmx_lmcx_ddr2_ctl_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ddr2_ctl_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t bank8                        : 1;  /**< For 8 bank DDR2 parts
                                                          1 - DDR2 parts have 8 internal banks (BA is 3 bits
@@ -3238,12 +4300,10 @@ typedef union cvmx_lmcx_ddr2_ctl cvmx_lmcx_ddr2_ctl_t;
  *     If test mode is going to be activated, wait an additional 8191 ref clocks (8191*16 rclk cycles) to allow PLL
  *     clock alignment
  */
-union cvmx_lmcx_ddr_pll_ctl
-{
+union cvmx_lmcx_ddr_pll_ctl {
 	uint64_t u64;
-	struct cvmx_lmcx_ddr_pll_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ddr_pll_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_27_63               : 37;
 	uint64_t jtg_test_mode                : 1;  /**< JTAG Test Mode
                                                          Clock alignment between DCLK & REFCLK as well as FCLK &
@@ -3302,8 +4362,13 @@ union cvmx_lmcx_ddr_pll_ctl
 	uint64_t reserved_27_63               : 37;
 #endif
 	} s;
+	struct cvmx_lmcx_ddr_pll_ctl_s        cn61xx;
 	struct cvmx_lmcx_ddr_pll_ctl_s        cn63xx;
 	struct cvmx_lmcx_ddr_pll_ctl_s        cn63xxp1;
+	struct cvmx_lmcx_ddr_pll_ctl_s        cn66xx;
+	struct cvmx_lmcx_ddr_pll_ctl_s        cn68xx;
+	struct cvmx_lmcx_ddr_pll_ctl_s        cn68xxp1;
+	struct cvmx_lmcx_ddr_pll_ctl_s        cnf71xx;
 };
 typedef union cvmx_lmcx_ddr_pll_ctl cvmx_lmcx_ddr_pll_ctl_t;
 
@@ -3334,12 +4399,10 @@ typedef union cvmx_lmcx_ddr_pll_ctl cvmx_lmcx_ddr_pll_ctl_t;
  * This scheme should eliminate the board need of adding routing delay to clock signals to make high
  * frequencies work.
  */
-union cvmx_lmcx_delay_cfg
-{
+union cvmx_lmcx_delay_cfg {
 	uint64_t u64;
-	struct cvmx_lmcx_delay_cfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_delay_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_15_63               : 49;
 	uint64_t dq                           : 5;  /**< Setting for DQ  delay line */
 	uint64_t cmd                          : 5;  /**< Setting for CMD delay line */
@@ -3352,9 +4415,8 @@ union cvmx_lmcx_delay_cfg
 #endif
 	} s;
 	struct cvmx_lmcx_delay_cfg_s          cn30xx;
-	struct cvmx_lmcx_delay_cfg_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_delay_cfg_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t dq                           : 4;  /**< Setting for DQ  delay line */
 	uint64_t reserved_9_9                 : 1;
@@ -3392,12 +4454,10 @@ typedef union cvmx_lmcx_delay_cfg cvmx_lmcx_delay_cfg_t;
  * these fields into the control words in the JEDEC standard SSTE32882 registering clock driver on an
  * RDIMM when corresponding LMC*_DIMM_CTL[DIMM*_WMASK] bits are set.
  */
-union cvmx_lmcx_dimmx_params
-{
+union cvmx_lmcx_dimmx_params {
 	uint64_t u64;
-	struct cvmx_lmcx_dimmx_params_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_dimmx_params_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rc15                         : 4;  /**< RC15, Reserved */
 	uint64_t rc14                         : 4;  /**< RC14, Reserved */
 	uint64_t rc13                         : 4;  /**< RC13, Reserved */
@@ -3433,8 +4493,13 @@ union cvmx_lmcx_dimmx_params
 	uint64_t rc15                         : 4;
 #endif
 	} s;
+	struct cvmx_lmcx_dimmx_params_s       cn61xx;
 	struct cvmx_lmcx_dimmx_params_s       cn63xx;
 	struct cvmx_lmcx_dimmx_params_s       cn63xxp1;
+	struct cvmx_lmcx_dimmx_params_s       cn66xx;
+	struct cvmx_lmcx_dimmx_params_s       cn68xx;
+	struct cvmx_lmcx_dimmx_params_s       cn68xxp1;
+	struct cvmx_lmcx_dimmx_params_s       cnf71xx;
 };
 typedef union cvmx_lmcx_dimmx_params cvmx_lmcx_dimmx_params_t;
 
@@ -3449,14 +4514,18 @@ typedef union cvmx_lmcx_dimmx_params cvmx_lmcx_dimmx_params_t;
  * controls LMC's writes to the control words in the JEDEC standard SSTE32882 registering clock driver
  * on an RDIMM.
  */
-union cvmx_lmcx_dimm_ctl
-{
+union cvmx_lmcx_dimm_ctl {
 	uint64_t u64;
-	struct cvmx_lmcx_dimm_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_dimm_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_46_63               : 18;
-	uint64_t parity                       : 1;  /**< Parity */
+	uint64_t parity                       : 1;  /**< Parity
+                                                         The PAR_IN input of a registered DIMM should be
+                                                         tied off. LMC adjusts the value of the DDR_WE_L (DWE#)
+                                                         pin during DDR3 register part control word writes to
+                                                         ensure the parity is observed correctly by the receiving
+                                                         SSTE32882 register part.
+                                                         When PAR_IN is grounded, PARITY should be cleared to 0. */
 	uint64_t tcws                         : 13; /**< LMC waits for this time period before and after a RDIMM
                                                          Control Word Access during a power-up/init SEQUENCE.
                                                          TCWS is in multiples of 8 CK cycles.
@@ -3482,8 +4551,13 @@ union cvmx_lmcx_dimm_ctl
 	uint64_t reserved_46_63               : 18;
 #endif
 	} s;
+	struct cvmx_lmcx_dimm_ctl_s           cn61xx;
 	struct cvmx_lmcx_dimm_ctl_s           cn63xx;
 	struct cvmx_lmcx_dimm_ctl_s           cn63xxp1;
+	struct cvmx_lmcx_dimm_ctl_s           cn66xx;
+	struct cvmx_lmcx_dimm_ctl_s           cn68xx;
+	struct cvmx_lmcx_dimm_ctl_s           cn68xxp1;
+	struct cvmx_lmcx_dimm_ctl_s           cnf71xx;
 };
 typedef union cvmx_lmcx_dimm_ctl cvmx_lmcx_dimm_ctl_t;
 
@@ -3493,12 +4567,10 @@ typedef union cvmx_lmcx_dimm_ctl cvmx_lmcx_dimm_ctl_t;
  * LMC_DLL_CTL = LMC DLL control and DCLK reset
  *
  */
-union cvmx_lmcx_dll_ctl
-{
+union cvmx_lmcx_dll_ctl {
 	uint64_t u64;
-	struct cvmx_lmcx_dll_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_dll_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t dreset                       : 1;  /**< Dclk domain reset.  The reset signal that is used by the
                                                          Dclk domain is (DRESET || ECLK_RESET). */
@@ -3552,12 +4624,43 @@ typedef union cvmx_lmcx_dll_ctl cvmx_lmcx_dll_ctl_t;
  * 8. Write 0 to LMC*_DLL_CTL2[DRESET].  LMC*_DLL_CTL2[DRESET] must not change after this point without restarting the LMC and/or
  *    DRESET initialization sequence.
  */
-union cvmx_lmcx_dll_ctl2
-{
+union cvmx_lmcx_dll_ctl2 {
 	uint64_t u64;
-	struct cvmx_lmcx_dll_ctl2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_dll_ctl2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t intf_en                      : 1;  /**< Interface Enable */
+	uint64_t dll_bringup                  : 1;  /**< DLL Bringup */
+	uint64_t dreset                       : 1;  /**< Dclk domain reset.  The reset signal that is used by the
+                                                         Dclk domain is (DRESET || ECLK_RESET). */
+	uint64_t quad_dll_ena                 : 1;  /**< DLL Enable */
+	uint64_t byp_sel                      : 4;  /**< Bypass select
+                                                         0000 : no byte
+                                                         0001 : byte 0
+                                                         - ...
+                                                         1001 : byte 8
+                                                         1010 : all bytes
+                                                         1011-1111 : Reserved */
+	uint64_t byp_setting                  : 8;  /**< Bypass setting
+                                                         DDR3-1600: 00100010
+                                                         DDR3-1333: 00110010
+                                                         DDR3-1066: 01001011
+                                                         DDR3-800 : 01110101
+                                                         DDR3-667 : 10010110
+                                                         DDR3-600 : 10101100 */
+#else
+	uint64_t byp_setting                  : 8;
+	uint64_t byp_sel                      : 4;
+	uint64_t quad_dll_ena                 : 1;
+	uint64_t dreset                       : 1;
+	uint64_t dll_bringup                  : 1;
+	uint64_t intf_en                      : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_lmcx_dll_ctl2_s           cn61xx;
+	struct cvmx_lmcx_dll_ctl2_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_15_63               : 49;
 	uint64_t dll_bringup                  : 1;  /**< DLL Bringup */
 	uint64_t dreset                       : 1;  /**< Dclk domain reset.  The reset signal that is used by the
@@ -3585,9 +4688,12 @@ union cvmx_lmcx_dll_ctl2
 	uint64_t dll_bringup                  : 1;
 	uint64_t reserved_15_63               : 49;
 #endif
-	} s;
-	struct cvmx_lmcx_dll_ctl2_s           cn63xx;
-	struct cvmx_lmcx_dll_ctl2_s           cn63xxp1;
+	} cn63xx;
+	struct cvmx_lmcx_dll_ctl2_cn63xx      cn63xxp1;
+	struct cvmx_lmcx_dll_ctl2_cn63xx      cn66xx;
+	struct cvmx_lmcx_dll_ctl2_s           cn68xx;
+	struct cvmx_lmcx_dll_ctl2_s           cn68xxp1;
+	struct cvmx_lmcx_dll_ctl2_s           cnf71xx;
 };
 typedef union cvmx_lmcx_dll_ctl2 cvmx_lmcx_dll_ctl2_t;
 
@@ -3597,12 +4703,81 @@ typedef union cvmx_lmcx_dll_ctl2 cvmx_lmcx_dll_ctl2_t;
  * LMC_DLL_CTL3 = LMC DLL control and DCLK reset
  *
  */
-union cvmx_lmcx_dll_ctl3
-{
+union cvmx_lmcx_dll_ctl3 {
 	uint64_t u64;
-	struct cvmx_lmcx_dll_ctl3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_dll_ctl3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_41_63               : 23;
+	uint64_t dclk90_fwd                   : 1;  /**< Forward setting
+                                                         0 : disable
+                                                         1 : forward (generates a 1 cycle pulse to forward setting)
+                                                         This register is oneshot and clears itself each time
+                                                         it is set */
+	uint64_t ddr_90_dly_byp               : 1;  /**< Bypass DDR90_DLY in Clock Tree */
+	uint64_t dclk90_recal_dis             : 1;  /**< Disable periodic recalibration of DDR90 Delay Line in */
+	uint64_t dclk90_byp_sel               : 1;  /**< Bypass Setting Select for DDR90 Delay Line */
+	uint64_t dclk90_byp_setting           : 8;  /**< Bypass Setting for DDR90 Delay Line */
+	uint64_t dll_fast                     : 1;  /**< DLL lock
+                                                         0 = DLL locked */
+	uint64_t dll90_setting                : 8;  /**< Encoded DLL settings. Works in conjuction with
+                                                         DLL90_BYTE_SEL */
+	uint64_t fine_tune_mode               : 1;  /**< DLL Fine Tune Mode
+                                                         0 = disabled
+                                                         1 = enable.
+                                                         When enabled, calibrate internal PHY DLL every
+                                                         LMC*_CONFIG[REF_ZQCS_INT] CK cycles. */
+	uint64_t dll_mode                     : 1;  /**< DLL Mode */
+	uint64_t dll90_byte_sel               : 4;  /**< Observe DLL settings for selected byte
+                                                         0001 : byte 0
+                                                         - ...
+                                                         1001 : byte 8
+                                                         0000,1010-1111 : Reserved */
+	uint64_t offset_ena                   : 1;  /**< Offset enable
+                                                         0 = disable
+                                                         1 = enable */
+	uint64_t load_offset                  : 1;  /**< Load offset
+                                                         0 : disable
+                                                         1 : load (generates a 1 cycle pulse to the PHY)
+                                                         This register is oneshot and clears itself each time
+                                                         it is set */
+	uint64_t mode_sel                     : 2;  /**< Mode select
+                                                         00 : reset
+                                                         01 : write
+                                                         10 : read
+                                                         11 : write & read */
+	uint64_t byte_sel                     : 4;  /**< Byte select
+                                                         0000 : no byte
+                                                         0001 : byte 0
+                                                         - ...
+                                                         1001 : byte 8
+                                                         1010 : all bytes
+                                                         1011-1111 : Reserved */
+	uint64_t offset                       : 6;  /**< Write/read offset setting
+                                                         [4:0] : offset
+                                                         [5]   : 0 = increment, 1 = decrement
+                                                         Not a 2's complement value */
+#else
+	uint64_t offset                       : 6;
+	uint64_t byte_sel                     : 4;
+	uint64_t mode_sel                     : 2;
+	uint64_t load_offset                  : 1;
+	uint64_t offset_ena                   : 1;
+	uint64_t dll90_byte_sel               : 4;
+	uint64_t dll_mode                     : 1;
+	uint64_t fine_tune_mode               : 1;
+	uint64_t dll90_setting                : 8;
+	uint64_t dll_fast                     : 1;
+	uint64_t dclk90_byp_setting           : 8;
+	uint64_t dclk90_byp_sel               : 1;
+	uint64_t dclk90_recal_dis             : 1;
+	uint64_t ddr_90_dly_byp               : 1;
+	uint64_t dclk90_fwd                   : 1;
+	uint64_t reserved_41_63               : 23;
+#endif
+	} s;
+	struct cvmx_lmcx_dll_ctl3_s           cn61xx;
+	struct cvmx_lmcx_dll_ctl3_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t dll_fast                     : 1;  /**< DLL lock
                                                          0 = DLL locked */
@@ -3656,9 +4831,12 @@ union cvmx_lmcx_dll_ctl3
 	uint64_t dll_fast                     : 1;
 	uint64_t reserved_29_63               : 35;
 #endif
-	} s;
-	struct cvmx_lmcx_dll_ctl3_s           cn63xx;
-	struct cvmx_lmcx_dll_ctl3_s           cn63xxp1;
+	} cn63xx;
+	struct cvmx_lmcx_dll_ctl3_cn63xx      cn63xxp1;
+	struct cvmx_lmcx_dll_ctl3_cn63xx      cn66xx;
+	struct cvmx_lmcx_dll_ctl3_s           cn68xx;
+	struct cvmx_lmcx_dll_ctl3_s           cn68xxp1;
+	struct cvmx_lmcx_dll_ctl3_s           cnf71xx;
 };
 typedef union cvmx_lmcx_dll_ctl3 cvmx_lmcx_dll_ctl3_t;
 
@@ -3689,12 +4867,10 @@ typedef union cvmx_lmcx_dll_ctl3 cvmx_lmcx_dll_ctl3_t;
  *  Programming restrictions for CS_MASK:
  *    when LMC*_CONFIG[RANK_ENA] == 0, CS_MASK[2n + 1] = CS_MASK[2n]
  */
-union cvmx_lmcx_dual_memcfg
-{
+union cvmx_lmcx_dual_memcfg {
 	uint64_t u64;
-	struct cvmx_lmcx_dual_memcfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_dual_memcfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t bank8                        : 1;  /**< See LMC_DDR2_CTL[BANK8] */
 	uint64_t row_lsb                      : 3;  /**< See LMC*_CONFIG[ROW_LSB] */
@@ -3706,7 +4882,7 @@ union cvmx_lmcx_dual_memcfg
                                                          corresponding CS_MASK bit set, then the "config1"
                                                          parameters are used, otherwise the "config0" parameters
                                                          are used.  See additional notes below.
-                                                         [7:4] */
+                                                         [7:4] *UNUSED IN 6xxx* */
 #else
 	uint64_t cs_mask                      : 8;
 	uint64_t reserved_8_15                : 8;
@@ -3722,9 +4898,8 @@ union cvmx_lmcx_dual_memcfg
 	struct cvmx_lmcx_dual_memcfg_s        cn56xxp1;
 	struct cvmx_lmcx_dual_memcfg_s        cn58xx;
 	struct cvmx_lmcx_dual_memcfg_s        cn58xxp1;
-	struct cvmx_lmcx_dual_memcfg_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_dual_memcfg_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t row_lsb                      : 3;  /**< See LMC*_CONFIG[ROW_LSB] */
 	uint64_t reserved_8_15                : 8;
@@ -3735,15 +4910,20 @@ union cvmx_lmcx_dual_memcfg
                                                          corresponding CS_MASK bit set, then the "config1"
                                                          parameters are used, otherwise the "config0" parameters
                                                          are used.  See additional notes below.
-                                                         [7:4] */
+                                                         [7:4] *UNUSED IN 6xxx* */
 #else
 	uint64_t cs_mask                      : 8;
 	uint64_t reserved_8_15                : 8;
 	uint64_t row_lsb                      : 3;
 	uint64_t reserved_19_63               : 45;
 #endif
-	} cn63xx;
-	struct cvmx_lmcx_dual_memcfg_cn63xx   cn63xxp1;
+	} cn61xx;
+	struct cvmx_lmcx_dual_memcfg_cn61xx   cn63xx;
+	struct cvmx_lmcx_dual_memcfg_cn61xx   cn63xxp1;
+	struct cvmx_lmcx_dual_memcfg_cn61xx   cn66xx;
+	struct cvmx_lmcx_dual_memcfg_cn61xx   cn68xx;
+	struct cvmx_lmcx_dual_memcfg_cn61xx   cn68xxp1;
+	struct cvmx_lmcx_dual_memcfg_cn61xx   cnf71xx;
 };
 typedef union cvmx_lmcx_dual_memcfg cvmx_lmcx_dual_memcfg_t;
 
@@ -3753,24 +4933,30 @@ typedef union cvmx_lmcx_dual_memcfg cvmx_lmcx_dual_memcfg_t;
  * LMC_ECC_SYND = MRD ECC Syndromes
  *
  */
-union cvmx_lmcx_ecc_synd
-{
+union cvmx_lmcx_ecc_synd {
 	uint64_t u64;
-	struct cvmx_lmcx_ecc_synd_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ecc_synd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t mrdsyn3                      : 8;  /**< MRD ECC Syndrome Quad3
                                                          MRDSYN3 corresponds to DQ[63:0]_c1_p1
+                                                         In 32b mode, ecc is calculated on 4 cycle worth of data
+                                                         MRDSYN3 corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]
                                                            where _cC_pP denotes cycle C and phase P */
 	uint64_t mrdsyn2                      : 8;  /**< MRD ECC Syndrome Quad2
                                                          MRDSYN2 corresponds to DQ[63:0]_c1_p0
+                                                         In 32b mode, ecc is calculated on 4 cycle worth of data
+                                                         MRDSYN2 corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]
                                                            where _cC_pP denotes cycle C and phase P */
 	uint64_t mrdsyn1                      : 8;  /**< MRD ECC Syndrome Quad1
                                                          MRDSYN1 corresponds to DQ[63:0]_c0_p1
+                                                         In 32b mode, ecc is calculated on 4 cycle worth of data
+                                                         MRDSYN1 corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]
                                                            where _cC_pP denotes cycle C and phase P */
 	uint64_t mrdsyn0                      : 8;  /**< MRD ECC Syndrome Quad0
                                                          MRDSYN0 corresponds to DQ[63:0]_c0_p0
+                                                         In 32b mode, ecc is calculated on 4 cycle worth of data
+                                                         MRDSYN0 corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]
                                                            where _cC_pP denotes cycle C and phase P */
 #else
 	uint64_t mrdsyn0                      : 8;
@@ -3791,8 +4977,13 @@ union cvmx_lmcx_ecc_synd
 	struct cvmx_lmcx_ecc_synd_s           cn56xxp1;
 	struct cvmx_lmcx_ecc_synd_s           cn58xx;
 	struct cvmx_lmcx_ecc_synd_s           cn58xxp1;
+	struct cvmx_lmcx_ecc_synd_s           cn61xx;
 	struct cvmx_lmcx_ecc_synd_s           cn63xx;
 	struct cvmx_lmcx_ecc_synd_s           cn63xxp1;
+	struct cvmx_lmcx_ecc_synd_s           cn66xx;
+	struct cvmx_lmcx_ecc_synd_s           cn68xx;
+	struct cvmx_lmcx_ecc_synd_s           cn68xxp1;
+	struct cvmx_lmcx_ecc_synd_s           cnf71xx;
 };
 typedef union cvmx_lmcx_ecc_synd cvmx_lmcx_ecc_synd_t;
 
@@ -3807,21 +4998,28 @@ typedef union cvmx_lmcx_ecc_synd cvmx_lmcx_ecc_synd_t;
  * next failing address.
  *
  * If FDIMM is 2 that means the error is in the higher bits DIMM.
+ *
+ * Notes:
+ * LMC*_FADR captures the failing pre-scrambled address location (split into dimm, bunk, bank, etc). If
+ * scrambling is off, then LMC*_FADR will also capture the failing physical location in the DRAM parts.
+ *
+ * LMC*_SCRAMBLED_FADR captures the actual failing address location in the physical DRAM parts, i.e.,
+ * a. if scrambling is on, LMC*_SCRAMBLE_FADR contains the failing physical location in the DRAM parts (split
+ *    into dimm, bunk, bank, etc)
+ * b. if scrambling is off, the pre-scramble and post-scramble addresses are the same, and so the contents of
+ *    LMC*_SCRAMBLED_FADR match the contents of LMC*_FADR
  */
-union cvmx_lmcx_fadr
-{
+union cvmx_lmcx_fadr {
 	uint64_t u64;
-	struct cvmx_lmcx_fadr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_fadr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_0_63                : 64;
 #else
 	uint64_t reserved_0_63                : 64;
 #endif
 	} s;
-	struct cvmx_lmcx_fadr_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_fadr_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t fdimm                        : 2;  /**< Failing DIMM# */
 	uint64_t fbunk                        : 1;  /**< Failing Rank */
@@ -3850,9 +5048,8 @@ union cvmx_lmcx_fadr
 	struct cvmx_lmcx_fadr_cn30xx          cn56xxp1;
 	struct cvmx_lmcx_fadr_cn30xx          cn58xx;
 	struct cvmx_lmcx_fadr_cn30xx          cn58xxp1;
-	struct cvmx_lmcx_fadr_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_fadr_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t fdimm                        : 2;  /**< Failing DIMM# */
 	uint64_t fbunk                        : 1;  /**< Failing Rank */
@@ -3871,8 +5068,13 @@ union cvmx_lmcx_fadr
 	uint64_t fdimm                        : 2;
 	uint64_t reserved_36_63               : 28;
 #endif
-	} cn63xx;
-	struct cvmx_lmcx_fadr_cn63xx          cn63xxp1;
+	} cn61xx;
+	struct cvmx_lmcx_fadr_cn61xx          cn63xx;
+	struct cvmx_lmcx_fadr_cn61xx          cn63xxp1;
+	struct cvmx_lmcx_fadr_cn61xx          cn66xx;
+	struct cvmx_lmcx_fadr_cn61xx          cn68xx;
+	struct cvmx_lmcx_fadr_cn61xx          cn68xxp1;
+	struct cvmx_lmcx_fadr_cn61xx          cnf71xx;
 };
 typedef union cvmx_lmcx_fadr cvmx_lmcx_fadr_t;
 
@@ -3882,12 +5084,10 @@ typedef union cvmx_lmcx_fadr cvmx_lmcx_fadr_t;
  * LMC_IFB_CNT  = Performance Counters
  *
  */
-union cvmx_lmcx_ifb_cnt
-{
+union cvmx_lmcx_ifb_cnt {
 	uint64_t u64;
-	struct cvmx_lmcx_ifb_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ifb_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t ifbcnt                       : 64; /**< Performance Counter
                                                          64-bit counter that increments every
                                                          CK cycle there is something in the in-flight buffer. */
@@ -3895,8 +5095,13 @@ union cvmx_lmcx_ifb_cnt
 	uint64_t ifbcnt                       : 64;
 #endif
 	} s;
+	struct cvmx_lmcx_ifb_cnt_s            cn61xx;
 	struct cvmx_lmcx_ifb_cnt_s            cn63xx;
 	struct cvmx_lmcx_ifb_cnt_s            cn63xxp1;
+	struct cvmx_lmcx_ifb_cnt_s            cn66xx;
+	struct cvmx_lmcx_ifb_cnt_s            cn68xx;
+	struct cvmx_lmcx_ifb_cnt_s            cn68xxp1;
+	struct cvmx_lmcx_ifb_cnt_s            cnf71xx;
 };
 typedef union cvmx_lmcx_ifb_cnt cvmx_lmcx_ifb_cnt_t;
 
@@ -3906,12 +5111,10 @@ typedef union cvmx_lmcx_ifb_cnt cvmx_lmcx_ifb_cnt_t;
  * LMC_IFB_CNT_HI  = Performance Counters
  *
  */
-union cvmx_lmcx_ifb_cnt_hi
-{
+union cvmx_lmcx_ifb_cnt_hi {
 	uint64_t u64;
-	struct cvmx_lmcx_ifb_cnt_hi_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ifb_cnt_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t ifbcnt_hi                    : 32; /**< Performance Counter to measure Bus Utilization
                                                          Upper 32-bits of 64-bit counter that increments every
@@ -3941,12 +5144,10 @@ typedef union cvmx_lmcx_ifb_cnt_hi cvmx_lmcx_ifb_cnt_hi_t;
  * LMC_IFB_CNT_LO  = Performance Counters
  *
  */
-union cvmx_lmcx_ifb_cnt_lo
-{
+union cvmx_lmcx_ifb_cnt_lo {
 	uint64_t u64;
-	struct cvmx_lmcx_ifb_cnt_lo_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ifb_cnt_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t ifbcnt_lo                    : 32; /**< Performance Counter
                                                          Low 32-bits of 64-bit counter that increments every
@@ -3976,27 +5177,35 @@ typedef union cvmx_lmcx_ifb_cnt_lo cvmx_lmcx_ifb_cnt_lo_t;
  * LMC_INT = LMC Interrupt Register
  *
  */
-union cvmx_lmcx_int
-{
+union cvmx_lmcx_int {
 	uint64_t u64;
-	struct cvmx_lmcx_int_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t ded_err                      : 4;  /**< Double Error detected (DED) of Rd Data
                                                          [0] corresponds to DQ[63:0]_c0_p0
                                                          [1] corresponds to DQ[63:0]_c0_p1
                                                          [2] corresponds to DQ[63:0]_c1_p0
                                                          [3] corresponds to DQ[63:0]_c1_p1
-                                                         where _cC_pP denotes cycle C and phase P
-                                                         Write of 1 will clear the corresponding error bit */
+                                                         In 32b mode, ecc is calculated on 4 cycle worth of data
+                                                         [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]
+                                                         [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]
+                                                         [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]
+                                                         [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]
+                                                          where _cC_pP denotes cycle C and phase P
+                                                          Write of 1 will clear the corresponding error bit */
 	uint64_t sec_err                      : 4;  /**< Single Error (corrected) of Rd Data
                                                          [0] corresponds to DQ[63:0]_c0_p0
                                                          [1] corresponds to DQ[63:0]_c0_p1
                                                          [2] corresponds to DQ[63:0]_c1_p0
                                                          [3] corresponds to DQ[63:0]_c1_p1
-                                                         where _cC_pP denotes cycle C and phase P
-                                                         Write of 1 will clear the corresponding error bit */
+                                                         In 32b mode, ecc is calculated on 4 cycle worth of data
+                                                         [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]
+                                                         [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]
+                                                         [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]
+                                                         [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]
+                                                          where _cC_pP denotes cycle C and phase P
+                                                          Write of 1 will clear the corresponding error bit */
 	uint64_t nxm_wr_err                   : 1;  /**< Write to non-existent memory
                                                          Write of 1 will clear the corresponding error bit */
 #else
@@ -4006,8 +5215,13 @@ union cvmx_lmcx_int
 	uint64_t reserved_9_63                : 55;
 #endif
 	} s;
+	struct cvmx_lmcx_int_s                cn61xx;
 	struct cvmx_lmcx_int_s                cn63xx;
 	struct cvmx_lmcx_int_s                cn63xxp1;
+	struct cvmx_lmcx_int_s                cn66xx;
+	struct cvmx_lmcx_int_s                cn68xx;
+	struct cvmx_lmcx_int_s                cn68xxp1;
+	struct cvmx_lmcx_int_s                cnf71xx;
 };
 typedef union cvmx_lmcx_int cvmx_lmcx_int_t;
 
@@ -4017,12 +5231,10 @@ typedef union cvmx_lmcx_int cvmx_lmcx_int_t;
  * LMC_INT_EN = LMC Interrupt Enable Register
  *
  */
-union cvmx_lmcx_int_en
-{
+union cvmx_lmcx_int_en {
 	uint64_t u64;
-	struct cvmx_lmcx_int_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t intr_ded_ena                 : 1;  /**< ECC Double Error Detect(DED) Interrupt Enable bit
                                                          When set, the memory controller raises a processor
@@ -4042,8 +5254,13 @@ union cvmx_lmcx_int_en
 	uint64_t reserved_3_63                : 61;
 #endif
 	} s;
+	struct cvmx_lmcx_int_en_s             cn61xx;
 	struct cvmx_lmcx_int_en_s             cn63xx;
 	struct cvmx_lmcx_int_en_s             cn63xxp1;
+	struct cvmx_lmcx_int_en_s             cn66xx;
+	struct cvmx_lmcx_int_en_s             cn68xx;
+	struct cvmx_lmcx_int_en_s             cn68xxp1;
+	struct cvmx_lmcx_int_en_s             cnf71xx;
 };
 typedef union cvmx_lmcx_int_en cvmx_lmcx_int_en_t;
 
@@ -4056,12 +5273,10 @@ typedef union cvmx_lmcx_int_en cvmx_lmcx_int_en_t;
  *
  * This register controls certain parameters of  Memory Configuration
  */
-union cvmx_lmcx_mem_cfg0
-{
+union cvmx_lmcx_mem_cfg0 {
 	uint64_t u64;
-	struct cvmx_lmcx_mem_cfg0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_mem_cfg0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t reset                        : 1;  /**< Reset oneshot pulse for refresh counter,
                                                          and LMC_OPS_CNT_*, LMC_IFB_CNT_*, and LMC_DCLK_CNT_*
@@ -4221,12 +5436,10 @@ typedef union cvmx_lmcx_mem_cfg0 cvmx_lmcx_mem_cfg0_t;
  * The details of each of these timing parameters can be found in the JEDEC spec or the vendor
  * spec of the memory parts.
  */
-union cvmx_lmcx_mem_cfg1
-{
+union cvmx_lmcx_mem_cfg1 {
 	uint64_t u64;
-	struct cvmx_lmcx_mem_cfg1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_mem_cfg1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t comp_bypass                  : 1;  /**< Compensation bypass. */
 	uint64_t trrd                         : 3;  /**< tRRD cycles: ACT-ACT timing parameter for different
@@ -4329,9 +5542,8 @@ union cvmx_lmcx_mem_cfg1
 	} s;
 	struct cvmx_lmcx_mem_cfg1_s           cn30xx;
 	struct cvmx_lmcx_mem_cfg1_s           cn31xx;
-	struct cvmx_lmcx_mem_cfg1_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_mem_cfg1_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t trrd                         : 3;  /**< tRRD cycles: ACT-ACT timing parameter for different
                                                          banks. (Represented in tCYC cycles == 1dclks)
@@ -4451,12 +5663,10 @@ typedef union cvmx_lmcx_mem_cfg1 cvmx_lmcx_mem_cfg1_t;
  * These parameters are written into the DDR3 MR0, MR1, MR2 and MR3 registers.
  *
  */
-union cvmx_lmcx_modereg_params0
-{
+union cvmx_lmcx_modereg_params0 {
 	uint64_t u64;
-	struct cvmx_lmcx_modereg_params0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_modereg_params0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_25_63               : 39;
 	uint64_t ppd                          : 1;  /**< DLL Control for precharge powerdown
                                                          0 = Slow exit (DLL off)
@@ -4470,14 +5680,14 @@ union cvmx_lmcx_modereg_params0
 	uint64_t wrp                          : 3;  /**< Write recovery for auto precharge
                                                          Should be programmed to be equal to or greater than
                                                          RNDUP[tWR(ns)/tCYC(ns)]
-                                                         000 = Reserved
+                                                         000 = 5
                                                          001 = 5
                                                          010 = 6
                                                          011 = 7
                                                          100 = 8
                                                          101 = 10
                                                          110 = 12
-                                                         111 = Reserved
+                                                         111 = 14
                                                          LMC writes this value to MR0[WR] in the selected DDR3 parts
                                                          during power-up/init and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
                                                          self-refresh exit instruction sequences.
@@ -4514,7 +5724,12 @@ union cvmx_lmcx_modereg_params0
                                                          1010 = 9
                                                          1100 = 10
                                                          1110 = 11
-                                                         0000, ???1 = Reserved
+                                                         0001 = 12
+                                                         0011 = 13
+                                                         0101 = 14
+                                                         0111 = 15
+                                                         1001 = 16
+                                                         0000, 1011, 1101, 1111 = Reserved
                                                          LMC writes this value to MR0[CAS Latency / CL] in the selected DDR3 parts
                                                          during power-up/init and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
                                                          self-refresh exit instruction sequences.
@@ -4604,7 +5819,10 @@ union cvmx_lmcx_modereg_params0
                                                          - 001: 6
                                                          - 010: 7
                                                          - 011: 8
-                                                         1xx: Reserved
+                                                         - 100: 9
+                                                         - 101: 10
+                                                         - 110: 11
+                                                         - 111: 12
                                                          LMC writes this value to MR2[CWL] in the selected DDR3 parts
                                                          during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
                                                          self-refresh entry and exit instruction sequences.
@@ -4631,8 +5849,13 @@ union cvmx_lmcx_modereg_params0
 	uint64_t reserved_25_63               : 39;
 #endif
 	} s;
+	struct cvmx_lmcx_modereg_params0_s    cn61xx;
 	struct cvmx_lmcx_modereg_params0_s    cn63xx;
 	struct cvmx_lmcx_modereg_params0_s    cn63xxp1;
+	struct cvmx_lmcx_modereg_params0_s    cn66xx;
+	struct cvmx_lmcx_modereg_params0_s    cn68xx;
+	struct cvmx_lmcx_modereg_params0_s    cn68xxp1;
+	struct cvmx_lmcx_modereg_params0_s    cnf71xx;
 };
 typedef union cvmx_lmcx_modereg_params0 cvmx_lmcx_modereg_params0_t;
 
@@ -4643,12 +5866,10 @@ typedef union cvmx_lmcx_modereg_params0 cvmx_lmcx_modereg_params0_t;
  * These parameters are written into the DDR3 MR0, MR1, MR2 and MR3 registers.
  *
  */
-union cvmx_lmcx_modereg_params1
-{
+union cvmx_lmcx_modereg_params1 {
 	uint64_t u64;
-	struct cvmx_lmcx_modereg_params1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_modereg_params1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t rtt_nom_11                   : 3;  /**< RTT_NOM Rank 3
                                                          LMC writes this value to MR1[Rtt_Nom] in the rank 3 (i.e. DIMM1_CS1) DDR3 parts
@@ -4834,8 +6055,13 @@ union cvmx_lmcx_modereg_params1
 	uint64_t reserved_48_63               : 16;
 #endif
 	} s;
+	struct cvmx_lmcx_modereg_params1_s    cn61xx;
 	struct cvmx_lmcx_modereg_params1_s    cn63xx;
 	struct cvmx_lmcx_modereg_params1_s    cn63xxp1;
+	struct cvmx_lmcx_modereg_params1_s    cn66xx;
+	struct cvmx_lmcx_modereg_params1_s    cn68xx;
+	struct cvmx_lmcx_modereg_params1_s    cn68xxp1;
+	struct cvmx_lmcx_modereg_params1_s    cnf71xx;
 };
 typedef union cvmx_lmcx_modereg_params1 cvmx_lmcx_modereg_params1_t;
 
@@ -4866,17 +6092,19 @@ typedef union cvmx_lmcx_modereg_params1 cvmx_lmcx_modereg_params1_t;
  * Note also that addresses greater the max defined space (pbank_msb) are also treated
  * as NXM accesses
  */
-union cvmx_lmcx_nxm
-{
+union cvmx_lmcx_nxm {
 	uint64_t u64;
-	struct cvmx_lmcx_nxm_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_nxm_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
-	uint64_t mem_msb_d3_r1                : 4;  /**< Max Row MSB for DIMM3, RANK1/DIMM3 in Single Ranked */
-	uint64_t mem_msb_d3_r0                : 4;  /**< Max Row MSB for DIMM3, RANK0 */
-	uint64_t mem_msb_d2_r1                : 4;  /**< Max Row MSB for DIMM2, RANK1/DIMM2 in Single Ranked */
-	uint64_t mem_msb_d2_r0                : 4;  /**< Max Row MSB for DIMM2, RANK0 */
+	uint64_t mem_msb_d3_r1                : 4;  /**< Max Row MSB for DIMM3, RANK1/DIMM3 in Single Ranked
+                                                         *UNUSED IN 6xxx* */
+	uint64_t mem_msb_d3_r0                : 4;  /**< Max Row MSB for DIMM3, RANK0
+                                                         *UNUSED IN 6xxx* */
+	uint64_t mem_msb_d2_r1                : 4;  /**< Max Row MSB for DIMM2, RANK1/DIMM2 in Single Ranked
+                                                         *UNUSED IN 6xxx* */
+	uint64_t mem_msb_d2_r0                : 4;  /**< Max Row MSB for DIMM2, RANK0
+                                                         *UNUSED IN 6xxx* */
 	uint64_t mem_msb_d1_r1                : 4;  /**< Max Row MSB for DIMM1, RANK1/DIMM1 in Single Ranked */
 	uint64_t mem_msb_d1_r0                : 4;  /**< Max Row MSB for DIMM1, RANK0 */
 	uint64_t mem_msb_d0_r1                : 4;  /**< Max Row MSB for DIMM0, RANK1/DIMM0 in Single Ranked */
@@ -4891,7 +6119,7 @@ union cvmx_lmcx_nxm
                                                          NXM read reference to use the lowest, legal chip select(s)
                                                          and return 0's. LMC normally discards NXM writes, but will
                                                          also alias them when LMC*_CONTROL[NXM_WRITE_EN]=1.
-                                                         CS_MASK<7:4> MBZ in 63xx */
+                                                         CS_MASK<7:4> MBZ in 6xxx */
 #else
 	uint64_t cs_mask                      : 8;
 	uint64_t mem_msb_d0_r0                : 4;
@@ -4905,9 +6133,8 @@ union cvmx_lmcx_nxm
 	uint64_t reserved_40_63               : 24;
 #endif
 	} s;
-	struct cvmx_lmcx_nxm_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_nxm_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t cs_mask                      : 8;  /**< Chip select mask.
                                                          This mask corresponds to the 8 chip selects for a memory
@@ -4925,8 +6152,13 @@ union cvmx_lmcx_nxm
 	} cn52xx;
 	struct cvmx_lmcx_nxm_cn52xx           cn56xx;
 	struct cvmx_lmcx_nxm_cn52xx           cn58xx;
+	struct cvmx_lmcx_nxm_s                cn61xx;
 	struct cvmx_lmcx_nxm_s                cn63xx;
 	struct cvmx_lmcx_nxm_s                cn63xxp1;
+	struct cvmx_lmcx_nxm_s                cn66xx;
+	struct cvmx_lmcx_nxm_s                cn68xx;
+	struct cvmx_lmcx_nxm_s                cn68xxp1;
+	struct cvmx_lmcx_nxm_s                cnf71xx;
 };
 typedef union cvmx_lmcx_nxm cvmx_lmcx_nxm_t;
 
@@ -4936,12 +6168,10 @@ typedef union cvmx_lmcx_nxm cvmx_lmcx_nxm_t;
  * LMC_OPS_CNT  = Performance Counters
  *
  */
-union cvmx_lmcx_ops_cnt
-{
+union cvmx_lmcx_ops_cnt {
 	uint64_t u64;
-	struct cvmx_lmcx_ops_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ops_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t opscnt                       : 64; /**< Performance Counter
                                                          64-bit counter that increments when the DDR3 data bus
                                                          is being used
@@ -4950,8 +6180,13 @@ union cvmx_lmcx_ops_cnt
 	uint64_t opscnt                       : 64;
 #endif
 	} s;
+	struct cvmx_lmcx_ops_cnt_s            cn61xx;
 	struct cvmx_lmcx_ops_cnt_s            cn63xx;
 	struct cvmx_lmcx_ops_cnt_s            cn63xxp1;
+	struct cvmx_lmcx_ops_cnt_s            cn66xx;
+	struct cvmx_lmcx_ops_cnt_s            cn68xx;
+	struct cvmx_lmcx_ops_cnt_s            cn68xxp1;
+	struct cvmx_lmcx_ops_cnt_s            cnf71xx;
 };
 typedef union cvmx_lmcx_ops_cnt cvmx_lmcx_ops_cnt_t;
 
@@ -4961,12 +6196,10 @@ typedef union cvmx_lmcx_ops_cnt cvmx_lmcx_ops_cnt_t;
  * LMC_OPS_CNT_HI  = Performance Counters
  *
  */
-union cvmx_lmcx_ops_cnt_hi
-{
+union cvmx_lmcx_ops_cnt_hi {
 	uint64_t u64;
-	struct cvmx_lmcx_ops_cnt_hi_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ops_cnt_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t opscnt_hi                    : 32; /**< Performance Counter to measure Bus Utilization
                                                          Upper 32-bits of 64-bit counter
@@ -4996,12 +6229,10 @@ typedef union cvmx_lmcx_ops_cnt_hi cvmx_lmcx_ops_cnt_hi_t;
  * LMC_OPS_CNT_LO  = Performance Counters
  *
  */
-union cvmx_lmcx_ops_cnt_lo
-{
+union cvmx_lmcx_ops_cnt_lo {
 	uint64_t u64;
-	struct cvmx_lmcx_ops_cnt_lo_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_ops_cnt_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t opscnt_lo                    : 32; /**< Performance Counter
                                                          Low 32-bits of 64-bit counter
@@ -5031,12 +6262,10 @@ typedef union cvmx_lmcx_ops_cnt_lo cvmx_lmcx_ops_cnt_lo_t;
  * LMC_PHY_CTL = LMC PHY Control
  *
  */
-union cvmx_lmcx_phy_ctl
-{
+union cvmx_lmcx_phy_ctl {
 	uint64_t u64;
-	struct cvmx_lmcx_phy_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_phy_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_15_63               : 49;
 	uint64_t rx_always_on                 : 1;  /**< Disable dynamic DDR3 IO Rx power gating */
 	uint64_t lv_mode                      : 1;  /**< Low Voltage Mode (1.35V) */
@@ -5068,10 +6297,10 @@ union cvmx_lmcx_phy_ctl
 	uint64_t reserved_15_63               : 49;
 #endif
 	} s;
+	struct cvmx_lmcx_phy_ctl_s            cn61xx;
 	struct cvmx_lmcx_phy_ctl_s            cn63xx;
-	struct cvmx_lmcx_phy_ctl_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_phy_ctl_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t lv_mode                      : 1;  /**< Low Voltage Mode (1.35V) */
 	uint64_t ck_tune1                     : 1;  /**< Clock Tune */
@@ -5101,6 +6330,10 @@ union cvmx_lmcx_phy_ctl
 	uint64_t reserved_14_63               : 50;
 #endif
 	} cn63xxp1;
+	struct cvmx_lmcx_phy_ctl_s            cn66xx;
+	struct cvmx_lmcx_phy_ctl_s            cn68xx;
+	struct cvmx_lmcx_phy_ctl_s            cn68xxp1;
+	struct cvmx_lmcx_phy_ctl_s            cnf71xx;
 };
 typedef union cvmx_lmcx_phy_ctl cvmx_lmcx_phy_ctl_t;
 
@@ -5110,12 +6343,10 @@ typedef union cvmx_lmcx_phy_ctl cvmx_lmcx_phy_ctl_t;
  * LMC_PLL_BWCTL  = DDR PLL Bandwidth Control Register
  *
  */
-union cvmx_lmcx_pll_bwctl
-{
+union cvmx_lmcx_pll_bwctl {
 	uint64_t u64;
-	struct cvmx_lmcx_pll_bwctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_pll_bwctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t bwupd                        : 1;  /**< Load this Bandwidth Register value into the PLL */
 	uint64_t bwctl                        : 4;  /**< Bandwidth Control Register for DDR PLL */
@@ -5154,12 +6385,10 @@ typedef union cvmx_lmcx_pll_bwctl cvmx_lmcx_pll_bwctl_t;
  *
  * must reside between 1.2 and 2.5 GHz. A faster PLL frequency is desirable if there is a choice.
  */
-union cvmx_lmcx_pll_ctl
-{
+union cvmx_lmcx_pll_ctl {
 	uint64_t u64;
-	struct cvmx_lmcx_pll_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_pll_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_30_63               : 34;
 	uint64_t bypass                       : 1;  /**< PLL Bypass */
 	uint64_t fasten_n                     : 1;  /**< Should be set, especially when CLKF > ~80 */
@@ -5196,9 +6425,8 @@ union cvmx_lmcx_pll_ctl
 	uint64_t reserved_30_63               : 34;
 #endif
 	} s;
-	struct cvmx_lmcx_pll_ctl_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_pll_ctl_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t fasten_n                     : 1;  /**< Should be set, especially when CLKF > ~80 */
 	uint64_t div_reset                    : 1;  /**< Analog pll divider reset
@@ -5236,9 +6464,8 @@ union cvmx_lmcx_pll_ctl
 	struct cvmx_lmcx_pll_ctl_s            cn52xx;
 	struct cvmx_lmcx_pll_ctl_s            cn52xxp1;
 	struct cvmx_lmcx_pll_ctl_cn50xx       cn56xx;
-	struct cvmx_lmcx_pll_ctl_cn56xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_pll_ctl_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t div_reset                    : 1;  /**< Analog pll divider reset
                                                          De-assert at least 500*(CLKR+1) reference clock
@@ -5282,12 +6509,10 @@ typedef union cvmx_lmcx_pll_ctl cvmx_lmcx_pll_ctl_t;
  * LMC_PLL_STATUS = LMC pll status
  *
  */
-union cvmx_lmcx_pll_status
-{
+union cvmx_lmcx_pll_status {
 	uint64_t u64;
-	struct cvmx_lmcx_pll_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_pll_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t ddr__nctl                    : 5;  /**< DDR nctl from compensation circuit */
 	uint64_t ddr__pctl                    : 5;  /**< DDR pctl from compensation circuit */
@@ -5309,9 +6534,8 @@ union cvmx_lmcx_pll_status
 	struct cvmx_lmcx_pll_status_s         cn56xx;
 	struct cvmx_lmcx_pll_status_s         cn56xxp1;
 	struct cvmx_lmcx_pll_status_s         cn58xx;
-	struct cvmx_lmcx_pll_status_cn58xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_pll_status_cn58xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t rfslip                       : 1;  /**< Reference clock slip */
 	uint64_t fbslip                       : 1;  /**< Feedback clock slip */
@@ -5334,12 +6558,10 @@ typedef union cvmx_lmcx_pll_status cvmx_lmcx_pll_status_t;
  * the last 8 words is the inverse of the write value of the first 8 words.
  * See LMC*_READ_LEVEL_RANK*.
  */
-union cvmx_lmcx_read_level_ctl
-{
+union cvmx_lmcx_read_level_ctl {
 	uint64_t u64;
-	struct cvmx_lmcx_read_level_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_read_level_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_44_63               : 20;
 	uint64_t rankmask                     : 4;  /**< Selects ranks to be leveled
                                                          to read-level rank i, set RANKMASK<i> */
@@ -5378,12 +6600,10 @@ typedef union cvmx_lmcx_read_level_ctl cvmx_lmcx_read_level_ctl_t;
  * if you run read-leveling separately for each rank, probing LMC*_READ_LEVEL_DBG between each
  * read-leveling.
  */
-union cvmx_lmcx_read_level_dbg
-{
+union cvmx_lmcx_read_level_dbg {
 	uint64_t u64;
-	struct cvmx_lmcx_read_level_dbg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_read_level_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t bitmask                      : 16; /**< Bitmask generated during deskew settings sweep
                                                          BITMASK[n]=0 means deskew setting n failed
@@ -5416,12 +6636,10 @@ typedef union cvmx_lmcx_read_level_dbg cvmx_lmcx_read_level_dbg_t;
  * SW initiates a HW read-leveling sequence by programming LMC*_READ_LEVEL_CTL and writing INIT_START=1 with SEQUENCE=1.
  * See LMC*_READ_LEVEL_CTL.
  */
-union cvmx_lmcx_read_level_rankx
-{
+union cvmx_lmcx_read_level_rankx {
 	uint64_t u64;
-	struct cvmx_lmcx_read_level_rankx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_read_level_rankx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_38_63               : 26;
 	uint64_t status                       : 2;  /**< Indicates status of the read-levelling and where
                                                          the BYTE* programmings in <35:0> came from:
@@ -5469,9 +6687,9 @@ typedef union cvmx_lmcx_read_level_rankx cvmx_lmcx_read_level_rankx_t;
  * DDR3RST - DDR3 DRAM parts have a new RESET#
  *   pin that wasn't present in DDR2 parts. The
  *   DDR3RST CSR field controls the assertion of
- *   the new 63xx pin that attaches to RESET#.
- *   When DDR3RST is set, 63xx asserts RESET#.
- *   When DDR3RST is clear, 63xx de-asserts
+ *   the new 6xxx pin that attaches to RESET#.
+ *   When DDR3RST is set, 6xxx asserts RESET#.
+ *   When DDR3RST is clear, 6xxx de-asserts
  *   RESET#.
  *
  *   DDR3RST is set on a cold reset. Warm and
@@ -5524,12 +6742,10 @@ typedef union cvmx_lmcx_read_level_rankx cvmx_lmcx_read_level_rankx_t;
  *
  *   Can also be written by software (to any value).
  */
-union cvmx_lmcx_reset_ctl
-{
+union cvmx_lmcx_reset_ctl {
 	uint64_t u64;
-	struct cvmx_lmcx_reset_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_reset_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t ddr3psv                      : 1;  /**< Memory Reset
                                                          1 = DDR contents preserved */
@@ -5548,20 +6764,23 @@ union cvmx_lmcx_reset_ctl
 	uint64_t reserved_4_63                : 60;
 #endif
 	} s;
+	struct cvmx_lmcx_reset_ctl_s          cn61xx;
 	struct cvmx_lmcx_reset_ctl_s          cn63xx;
 	struct cvmx_lmcx_reset_ctl_s          cn63xxp1;
+	struct cvmx_lmcx_reset_ctl_s          cn66xx;
+	struct cvmx_lmcx_reset_ctl_s          cn68xx;
+	struct cvmx_lmcx_reset_ctl_s          cn68xxp1;
+	struct cvmx_lmcx_reset_ctl_s          cnf71xx;
 };
 typedef union cvmx_lmcx_reset_ctl cvmx_lmcx_reset_ctl_t;
 
 /**
  * cvmx_lmc#_rlevel_ctl
  */
-union cvmx_lmcx_rlevel_ctl
-{
+union cvmx_lmcx_rlevel_ctl {
 	uint64_t u64;
-	struct cvmx_lmcx_rlevel_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_rlevel_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_22_63               : 42;
 	uint64_t delay_unload_3               : 1;  /**< When set, unload the PHY silo one cycle later
                                                          during read-leveling if LMC*_RLEVEL_RANKi[BYTE*<1:0>] = 3
@@ -5605,10 +6824,10 @@ union cvmx_lmcx_rlevel_ctl
 	uint64_t reserved_22_63               : 42;
 #endif
 	} s;
+	struct cvmx_lmcx_rlevel_ctl_s         cn61xx;
 	struct cvmx_lmcx_rlevel_ctl_s         cn63xx;
-	struct cvmx_lmcx_rlevel_ctl_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_rlevel_ctl_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t offset_en                    : 1;  /**< When set, LMC attempts to select the read-leveling
                                                          setting that is LMC*RLEVEL_CTL[OFFSET] settings earlier than the
@@ -5629,6 +6848,10 @@ union cvmx_lmcx_rlevel_ctl
 	uint64_t reserved_9_63                : 55;
 #endif
 	} cn63xxp1;
+	struct cvmx_lmcx_rlevel_ctl_s         cn66xx;
+	struct cvmx_lmcx_rlevel_ctl_s         cn68xx;
+	struct cvmx_lmcx_rlevel_ctl_s         cn68xxp1;
+	struct cvmx_lmcx_rlevel_ctl_s         cnf71xx;
 };
 typedef union cvmx_lmcx_rlevel_ctl cvmx_lmcx_rlevel_ctl_t;
 
@@ -5645,12 +6868,10 @@ typedef union cvmx_lmcx_rlevel_ctl cvmx_lmcx_rlevel_ctl_t;
  * if you run read-leveling separately for each rank, probing LMC*_RLEVEL_DBG between each
  * read-leveling.
  */
-union cvmx_lmcx_rlevel_dbg
-{
+union cvmx_lmcx_rlevel_dbg {
 	uint64_t u64;
-	struct cvmx_lmcx_rlevel_dbg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_rlevel_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bitmask                      : 64; /**< Bitmask generated during deskew settings sweep
                                                          BITMASK[n]=0 means deskew setting n failed
                                                          BITMASK[n]=1 means deskew setting n passed
@@ -5659,8 +6880,13 @@ union cvmx_lmcx_rlevel_dbg
 	uint64_t bitmask                      : 64;
 #endif
 	} s;
+	struct cvmx_lmcx_rlevel_dbg_s         cn61xx;
 	struct cvmx_lmcx_rlevel_dbg_s         cn63xx;
 	struct cvmx_lmcx_rlevel_dbg_s         cn63xxp1;
+	struct cvmx_lmcx_rlevel_dbg_s         cn66xx;
+	struct cvmx_lmcx_rlevel_dbg_s         cn68xx;
+	struct cvmx_lmcx_rlevel_dbg_s         cn68xxp1;
+	struct cvmx_lmcx_rlevel_dbg_s         cnf71xx;
 };
 typedef union cvmx_lmcx_rlevel_dbg cvmx_lmcx_rlevel_dbg_t;
 
@@ -5687,12 +6913,10 @@ typedef union cvmx_lmcx_rlevel_dbg cvmx_lmcx_rlevel_dbg_t;
  *     LMC*_RLEVEL_RANKi = LMC*_RLEVEL_RANKj,
  * where j is some rank with attached DRAM whose LMC*_RLEVEL_RANKj is already fully initialized.
  */
-union cvmx_lmcx_rlevel_rankx
-{
+union cvmx_lmcx_rlevel_rankx {
 	uint64_t u64;
-	struct cvmx_lmcx_rlevel_rankx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_rlevel_rankx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_56_63               : 8;
 	uint64_t status                       : 2;  /**< Indicates status of the read-levelling and where
                                                          the BYTE* programmings in <35:0> came from:
@@ -5730,8 +6954,13 @@ union cvmx_lmcx_rlevel_rankx
 	uint64_t reserved_56_63               : 8;
 #endif
 	} s;
+	struct cvmx_lmcx_rlevel_rankx_s       cn61xx;
 	struct cvmx_lmcx_rlevel_rankx_s       cn63xx;
 	struct cvmx_lmcx_rlevel_rankx_s       cn63xxp1;
+	struct cvmx_lmcx_rlevel_rankx_s       cn66xx;
+	struct cvmx_lmcx_rlevel_rankx_s       cn68xx;
+	struct cvmx_lmcx_rlevel_rankx_s       cn68xxp1;
+	struct cvmx_lmcx_rlevel_rankx_s       cnf71xx;
 };
 typedef union cvmx_lmcx_rlevel_rankx cvmx_lmcx_rlevel_rankx_t;
 
@@ -5741,12 +6970,10 @@ typedef union cvmx_lmcx_rlevel_rankx cvmx_lmcx_rlevel_rankx_t;
  * LMC_RODT_COMP_CTL = LMC Compensation control
  *
  */
-union cvmx_lmcx_rodt_comp_ctl
-{
+union cvmx_lmcx_rodt_comp_ctl {
 	uint64_t u64;
-	struct cvmx_lmcx_rodt_comp_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_rodt_comp_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t enable                       : 1;  /**< 0=not enabled, 1=enable */
 	uint64_t reserved_12_15               : 4;
@@ -5793,12 +7020,10 @@ typedef union cvmx_lmcx_rodt_comp_ctl cvmx_lmcx_rodt_comp_ctl_t;
  *  position 1: [DIMM2_RANK1_HI, DIMM0_RANK1_LO]
  *  position 0: [DIMM2_RANK0_HI, DIMM0_RANK0_LO]
  */
-union cvmx_lmcx_rodt_ctl
-{
+union cvmx_lmcx_rodt_ctl {
 	uint64_t u64;
-	struct cvmx_lmcx_rodt_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_rodt_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t rodt_hi3                     : 4;  /**< Read ODT mask for position 3, data[127:64] */
 	uint64_t rodt_hi2                     : 4;  /**< Read ODT mask for position 2, data[127:64] */
@@ -5877,44 +7102,42 @@ typedef union cvmx_lmcx_rodt_ctl cvmx_lmcx_rodt_ctl_t;
  * Note that it may be necessary to force LMC to space back-to-back cache block reads
  * to different ranks apart by at least 10+LMC*_CONTROL[RODT_BPRCH] CK's to prevent DDR3 ODTH8 violations.
  */
-union cvmx_lmcx_rodt_mask
-{
+union cvmx_lmcx_rodt_mask {
 	uint64_t u64;
-	struct cvmx_lmcx_rodt_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_rodt_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rodt_d3_r1                   : 8;  /**< Read ODT mask DIMM3, RANK1/DIMM3 in SingleRanked
-                                                         *UNUSED IN 63xx, and MBZ* */
+                                                         *UNUSED IN 6xxx, and MBZ* */
 	uint64_t rodt_d3_r0                   : 8;  /**< Read ODT mask DIMM3, RANK0
-                                                         *UNUSED IN 63xx, and MBZ* */
+                                                         *UNUSED IN 6xxx, and MBZ* */
 	uint64_t rodt_d2_r1                   : 8;  /**< Read ODT mask DIMM2, RANK1/DIMM2 in SingleRanked
-                                                         *UNUSED IN 63xx, and MBZ* */
+                                                         *UNUSED IN 6xxx, and MBZ* */
 	uint64_t rodt_d2_r0                   : 8;  /**< Read ODT mask DIMM2, RANK0
-                                                         *UNUSED IN 63xx, and MBZ* */
+                                                         *UNUSED IN 6xxx, and MBZ* */
 	uint64_t rodt_d1_r1                   : 8;  /**< Read ODT mask DIMM1, RANK1/DIMM1 in SingleRanked
                                                          if (RANK_ENA) then
                                                              RODT_D1_R1[3] must be 0
                                                          else
                                                              RODT_D1_R1[3:0] is not used and MBZ
-                                                         *Upper 4 bits UNUSED IN 63xx, and MBZ* */
+                                                         *Upper 4 bits UNUSED IN 6xxx, and MBZ* */
 	uint64_t rodt_d1_r0                   : 8;  /**< Read ODT mask DIMM1, RANK0
                                                          if (RANK_ENA) then
                                                              RODT_D1_RO[2] must be 0
                                                          else
                                                              RODT_D1_RO[3:2,1] must be 0
-                                                         *Upper 4 bits UNUSED IN 63xx, and MBZ* */
+                                                         *Upper 4 bits UNUSED IN 6xxx, and MBZ* */
 	uint64_t rodt_d0_r1                   : 8;  /**< Read ODT mask DIMM0, RANK1/DIMM0 in SingleRanked
                                                          if (RANK_ENA) then
                                                              RODT_D0_R1[1] must be 0
                                                          else
                                                              RODT_D0_R1[3:0] is not used and MBZ
-                                                         *Upper 4 bits UNUSED IN 63xx, and MBZ* */
+                                                         *Upper 4 bits UNUSED IN 6xxx, and MBZ* */
 	uint64_t rodt_d0_r0                   : 8;  /**< Read ODT mask DIMM0, RANK0
                                                          if (RANK_ENA) then
                                                              RODT_D0_RO[0] must be 0
                                                          else
                                                              RODT_D0_RO[1:0,3] must be 0
-                                                         *Upper 4 bits UNUSED IN 63xx, and MBZ* */
+                                                         *Upper 4 bits UNUSED IN 6xxx, and MBZ* */
 #else
 	uint64_t rodt_d0_r0                   : 8;
 	uint64_t rodt_d0_r1                   : 8;
@@ -5926,12 +7149,114 @@ union cvmx_lmcx_rodt_mask
 	uint64_t rodt_d3_r1                   : 8;
 #endif
 	} s;
+	struct cvmx_lmcx_rodt_mask_s          cn61xx;
 	struct cvmx_lmcx_rodt_mask_s          cn63xx;
 	struct cvmx_lmcx_rodt_mask_s          cn63xxp1;
+	struct cvmx_lmcx_rodt_mask_s          cn66xx;
+	struct cvmx_lmcx_rodt_mask_s          cn68xx;
+	struct cvmx_lmcx_rodt_mask_s          cn68xxp1;
+	struct cvmx_lmcx_rodt_mask_s          cnf71xx;
 };
 typedef union cvmx_lmcx_rodt_mask cvmx_lmcx_rodt_mask_t;
 
 /**
+ * cvmx_lmc#_scramble_cfg0
+ *
+ * LMC_SCRAMBLE_CFG0 = LMC Scramble Config0
+ *
+ */
+union cvmx_lmcx_scramble_cfg0 {
+	uint64_t u64;
+	struct cvmx_lmcx_scramble_cfg0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t key                          : 64; /**< Scramble Key for Data */
+#else
+	uint64_t key                          : 64;
+#endif
+	} s;
+	struct cvmx_lmcx_scramble_cfg0_s      cn61xx;
+	struct cvmx_lmcx_scramble_cfg0_s      cn66xx;
+	struct cvmx_lmcx_scramble_cfg0_s      cnf71xx;
+};
+typedef union cvmx_lmcx_scramble_cfg0 cvmx_lmcx_scramble_cfg0_t;
+
+/**
+ * cvmx_lmc#_scramble_cfg1
+ *
+ * LMC_SCRAMBLE_CFG1 = LMC Scramble Config1
+ *
+ *
+ * Notes:
+ * Address scrambling usually maps addresses into the same rank. Exceptions are when LMC_NXM[CS_MASK] requires
+ * aliasing that uses the lowest, legal chip select(s).
+ */
+union cvmx_lmcx_scramble_cfg1 {
+	uint64_t u64;
+	struct cvmx_lmcx_scramble_cfg1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t key                          : 64; /**< Scramble Key for Addresses */
+#else
+	uint64_t key                          : 64;
+#endif
+	} s;
+	struct cvmx_lmcx_scramble_cfg1_s      cn61xx;
+	struct cvmx_lmcx_scramble_cfg1_s      cn66xx;
+	struct cvmx_lmcx_scramble_cfg1_s      cnf71xx;
+};
+typedef union cvmx_lmcx_scramble_cfg1 cvmx_lmcx_scramble_cfg1_t;
+
+/**
+ * cvmx_lmc#_scrambled_fadr
+ *
+ * LMC_SCRAMBLED_FADR = LMC Scrambled Failing Address Register (SEC/DED/NXM)
+ *
+ * This register only captures the first transaction with ecc/nxm errors. A DED/NXM error can
+ * over-write this register with its failing addresses if the first error was a SEC. If you write
+ * LMC*_CONFIG->SEC_ERR/DED_ERR/NXM_ERR then it will clear the error bits and capture the
+ * next failing address.
+ *
+ * If FDIMM is 2 that means the error is in the higher bits DIMM.
+ *
+ * Notes:
+ * LMC*_FADR captures the failing pre-scrambled address location (split into dimm, bunk, bank, etc). If
+ * scrambling is off, then LMC*_FADR will also capture the failing physical location in the DRAM parts.
+ *
+ * LMC*_SCRAMBLED_FADR captures the actual failing address location in the physical DRAM parts, i.e.,
+ * a. if scrambling is on, LMC*_SCRAMBLE_FADR contains the failing physical location in the DRAM parts (split
+ *    into dimm, bunk, bank, etc)
+ * b. if scrambling is off, the pre-scramble and post-scramble addresses are the same, and so the contents of
+ *    LMC*_SCRAMBLED_FADR match the contents of LMC*_FADR
+ */
+union cvmx_lmcx_scrambled_fadr {
+	uint64_t u64;
+	struct cvmx_lmcx_scrambled_fadr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_36_63               : 28;
+	uint64_t fdimm                        : 2;  /**< Failing DIMM# */
+	uint64_t fbunk                        : 1;  /**< Failing Rank */
+	uint64_t fbank                        : 3;  /**< Failing Bank[2:0] */
+	uint64_t frow                         : 16; /**< Failing Row Address[15:0] */
+	uint64_t fcol                         : 14; /**< Failing Column Address[13:0]
+                                                         Technically, represents the address of the 128b data
+                                                         that had an ecc error, i.e., fcol[0] is always 0. Can
+                                                         be used in conjuction with LMC*_CONFIG[DED_ERR] to
+                                                         isolate the 64b chunk of data in error */
+#else
+	uint64_t fcol                         : 14;
+	uint64_t frow                         : 16;
+	uint64_t fbank                        : 3;
+	uint64_t fbunk                        : 1;
+	uint64_t fdimm                        : 2;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_lmcx_scrambled_fadr_s     cn61xx;
+	struct cvmx_lmcx_scrambled_fadr_s     cn66xx;
+	struct cvmx_lmcx_scrambled_fadr_s     cnf71xx;
+};
+typedef union cvmx_lmcx_scrambled_fadr cvmx_lmcx_scrambled_fadr_t;
+
+/**
  * cvmx_lmc#_slot_ctl0
  *
  * LMC_SLOT_CTL0 = LMC Slot Control0
@@ -5970,21 +7295,23 @@ typedef union cvmx_lmcx_rodt_mask cvmx_lmcx_rodt_mask_t;
  *
  * R2W_INIT has 1 CK cycle built in for OCTEON-internal ODT settling/channel turnaround time.
  */
-union cvmx_lmcx_slot_ctl0
-{
+union cvmx_lmcx_slot_ctl0 {
 	uint64_t u64;
-	struct cvmx_lmcx_slot_ctl0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_slot_ctl0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t w2w_init                     : 6;  /**< Write-to-write spacing control
-                                                         for back to back accesses to the same rank and DIMM */
+                                                         for back to back write followed by write cache block
+                                                         accesses to the same rank and DIMM */
 	uint64_t w2r_init                     : 6;  /**< Write-to-read spacing control
-                                                         for back to back accesses to the same rank and DIMM */
+                                                         for back to back write followed by read cache block
+                                                         accesses to the same rank and DIMM */
 	uint64_t r2w_init                     : 6;  /**< Read-to-write spacing control
-                                                         for back to back accesses to the same rank and DIMM */
+                                                         for back to back read followed by write cache block
+                                                         accesses to the same rank and DIMM */
 	uint64_t r2r_init                     : 6;  /**< Read-to-read spacing control
-                                                         for back to back accesses to the same rank and DIMM */
+                                                         for back to back read followed by read cache block
+                                                         accesses to the same rank and DIMM */
 #else
 	uint64_t r2r_init                     : 6;
 	uint64_t r2w_init                     : 6;
@@ -5993,8 +7320,13 @@ union cvmx_lmcx_slot_ctl0
 	uint64_t reserved_24_63               : 40;
 #endif
 	} s;
+	struct cvmx_lmcx_slot_ctl0_s          cn61xx;
 	struct cvmx_lmcx_slot_ctl0_s          cn63xx;
 	struct cvmx_lmcx_slot_ctl0_s          cn63xxp1;
+	struct cvmx_lmcx_slot_ctl0_s          cn66xx;
+	struct cvmx_lmcx_slot_ctl0_s          cn68xx;
+	struct cvmx_lmcx_slot_ctl0_s          cn68xxp1;
+	struct cvmx_lmcx_slot_ctl0_s          cnf71xx;
 };
 typedef union cvmx_lmcx_slot_ctl0 cvmx_lmcx_slot_ctl0_t;
 
@@ -6023,7 +7355,7 @@ typedef union cvmx_lmcx_slot_ctl0 cvmx_lmcx_slot_ctl0_t;
  *
  * The hardware-calculated minimums are:
  *
- * min R2R_XRANK_INIT = 2 - LMC*_CONFIG[DDR2T] + MaxRdSkew - MinRdSkew
+ * min R2R_XRANK_INIT = 2 - LMC*_CONFIG[DDR2T] + MaxRdSkew - MinRdSkew + LMC*_CONTROL[RODT_BPRCH]
  * min R2W_XRANK_INIT = 5 - LMC*_CONFIG[DDR2T] + (RL + MaxRdSkew) - (WL + MinWrSkew) + LMC*_CONTROL[BPRCH]
  * min W2R_XRANK_INIT = 3 - LMC*_CONFIG[DDR2T] + MaxWrSkew + LMC*_CONTROL[FPRCH2]
  * min W2W_XRANK_INIT = 4 - LMC*_CONFIG[DDR2T] + MaxWrSkew - MinWrSkew
@@ -6041,21 +7373,23 @@ typedef union cvmx_lmcx_slot_ctl0 cvmx_lmcx_slot_ctl0_t;
  *
  * W2R_XRANK_INIT has 1 extra CK cycle built in for channel turnaround time.
  */
-union cvmx_lmcx_slot_ctl1
-{
+union cvmx_lmcx_slot_ctl1 {
 	uint64_t u64;
-	struct cvmx_lmcx_slot_ctl1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_slot_ctl1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t w2w_xrank_init               : 6;  /**< Write-to-write spacing control
-                                                         for back to back accesses across ranks of the same DIMM */
+                                                         for back to back write followed by write cache block
+                                                         accesses across ranks of the same DIMM */
 	uint64_t w2r_xrank_init               : 6;  /**< Write-to-read spacing control
-                                                         for back to back accesses across ranks of the same DIMM */
+                                                         for back to back write followed by read cache block
+                                                         accesses across ranks of the same DIMM */
 	uint64_t r2w_xrank_init               : 6;  /**< Read-to-write spacing control
-                                                         for back to back accesses across ranks of the same DIMM */
+                                                         for back to back read followed by write cache block
+                                                         accesses across ranks of the same DIMM */
 	uint64_t r2r_xrank_init               : 6;  /**< Read-to-read spacing control
-                                                         for back to back accesses across ranks of the same DIMM */
+                                                         for back to back read followed by read cache block
+                                                         accesses across ranks of the same DIMM */
 #else
 	uint64_t r2r_xrank_init               : 6;
 	uint64_t r2w_xrank_init               : 6;
@@ -6064,8 +7398,13 @@ union cvmx_lmcx_slot_ctl1
 	uint64_t reserved_24_63               : 40;
 #endif
 	} s;
+	struct cvmx_lmcx_slot_ctl1_s          cn61xx;
 	struct cvmx_lmcx_slot_ctl1_s          cn63xx;
 	struct cvmx_lmcx_slot_ctl1_s          cn63xxp1;
+	struct cvmx_lmcx_slot_ctl1_s          cn66xx;
+	struct cvmx_lmcx_slot_ctl1_s          cn68xx;
+	struct cvmx_lmcx_slot_ctl1_s          cn68xxp1;
+	struct cvmx_lmcx_slot_ctl1_s          cnf71xx;
 };
 typedef union cvmx_lmcx_slot_ctl1 cvmx_lmcx_slot_ctl1_t;
 
@@ -6094,7 +7433,7 @@ typedef union cvmx_lmcx_slot_ctl1 cvmx_lmcx_slot_ctl1_t;
  *
  * The hardware-calculated minimums are:
  *
- * min R2R_XDIMM_INIT = 3 - LMC*_CONFIG[DDR2T] + MaxRdSkew - MinRdSkew
+ * min R2R_XDIMM_INIT = 3 - LMC*_CONFIG[DDR2T] + MaxRdSkew - MinRdSkew + LMC*_CONTROL[RODT_BPRCH]
  * min R2W_XDIMM_INIT = 6 - LMC*_CONFIG[DDR2T] + (RL + MaxRdSkew) - (WL + MinWrSkew) + LMC*_CONTROL[BPRCH]
  * min W2R_XDIMM_INIT = 3 - LMC*_CONFIG[DDR2T] + MaxWrSkew + LMC*_CONTROL[FPRCH2]
  * min W2W_XDIMM_INIT = 5 - LMC*_CONFIG[DDR2T] + MaxWrSkew - MinWrSkew
@@ -6112,21 +7451,23 @@ typedef union cvmx_lmcx_slot_ctl1 cvmx_lmcx_slot_ctl1_t;
  *
  * R2R_XDIMM_INIT, W2R_XRANK_INIT, W2W_XDIMM_INIT have 1 extra CK cycle built in for channel turnaround time.
  */
-union cvmx_lmcx_slot_ctl2
-{
+union cvmx_lmcx_slot_ctl2 {
 	uint64_t u64;
-	struct cvmx_lmcx_slot_ctl2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_slot_ctl2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t w2w_xdimm_init               : 6;  /**< Write-to-write spacing control
-                                                         for back to back accesses across DIMMs */
+                                                         for back to back write followed by write cache block
+                                                         accesses across DIMMs */
 	uint64_t w2r_xdimm_init               : 6;  /**< Write-to-read spacing control
-                                                         for back to back accesses across DIMMs */
+                                                         for back to back write followed by read cache block
+                                                         accesses across DIMMs */
 	uint64_t r2w_xdimm_init               : 6;  /**< Read-to-write spacing control
-                                                         for back to back accesses across DIMMs */
+                                                         for back to back read followed by write cache block
+                                                         accesses across DIMMs */
 	uint64_t r2r_xdimm_init               : 6;  /**< Read-to-read spacing control
-                                                         for back to back accesses across DIMMs */
+                                                         for back to back read followed by read cache block
+                                                         accesses across DIMMs */
 #else
 	uint64_t r2r_xdimm_init               : 6;
 	uint64_t r2w_xdimm_init               : 6;
@@ -6135,20 +7476,23 @@ union cvmx_lmcx_slot_ctl2
 	uint64_t reserved_24_63               : 40;
 #endif
 	} s;
+	struct cvmx_lmcx_slot_ctl2_s          cn61xx;
 	struct cvmx_lmcx_slot_ctl2_s          cn63xx;
 	struct cvmx_lmcx_slot_ctl2_s          cn63xxp1;
+	struct cvmx_lmcx_slot_ctl2_s          cn66xx;
+	struct cvmx_lmcx_slot_ctl2_s          cn68xx;
+	struct cvmx_lmcx_slot_ctl2_s          cn68xxp1;
+	struct cvmx_lmcx_slot_ctl2_s          cnf71xx;
 };
 typedef union cvmx_lmcx_slot_ctl2 cvmx_lmcx_slot_ctl2_t;
 
 /**
  * cvmx_lmc#_timing_params0
  */
-union cvmx_lmcx_timing_params0
-{
+union cvmx_lmcx_timing_params0 {
 	uint64_t u64;
-	struct cvmx_lmcx_timing_params0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_timing_params0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_47_63               : 17;
 	uint64_t trp_ext                      : 1;  /**< Indicates tRP constraints.
                                                          Set [TRP_EXT[0:0], TRP[3:0]] (CSR field) = RNDUP[tRP(ns)/tCYC(ns)]
@@ -6163,7 +7507,7 @@ union cvmx_lmcx_timing_params0
                                                          is the DDR clock frequency (not data rate).
                                                          TYP=max(5nCK, 10ns) */
 	uint64_t trp                          : 4;  /**< Indicates tRP constraints.
-                                                         Set TRP (CSR field) = RNDUP[tRP(ns)/tCYC(ns)]
+                                                         Set [TRP_EXT[0:0], TRP[3:0]] (CSR field) = RNDUP[tRP(ns)/tCYC(ns)]
                                                          + (RNDUP[tRTP(ns)/tCYC(ns)])-4)-1,
                                                          where tRP, tRTP are from the DDR3 spec, and tCYC(ns)
                                                          is the DDR clock frequency (not data rate).
@@ -6222,9 +7566,8 @@ union cvmx_lmcx_timing_params0
 	uint64_t reserved_47_63               : 17;
 #endif
 	} s;
-	struct cvmx_lmcx_timing_params0_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_timing_params0_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_47_63               : 17;
 	uint64_t trp_ext                      : 1;  /**< Indicates tRP constraints.
                                                          Set [TRP_EXT[0:0], TRP[3:0]] (CSR field) = RNDUP[tRP(ns)/tCYC(ns)]
@@ -6297,10 +7640,10 @@ union cvmx_lmcx_timing_params0
 	uint64_t trp_ext                      : 1;
 	uint64_t reserved_47_63               : 17;
 #endif
-	} cn63xx;
-	struct cvmx_lmcx_timing_params0_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	} cn61xx;
+	struct cvmx_lmcx_timing_params0_cn61xx cn63xx;
+	struct cvmx_lmcx_timing_params0_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_46_63               : 18;
 	uint64_t tcksre                       : 4;  /**< Indicates tCKSRE constraints.
                                                          Set TCKSRE (CSR field) = RNDUP[tCKSRE(ns)/tCYC(ns)]-1,
@@ -6366,18 +7709,20 @@ union cvmx_lmcx_timing_params0
 	uint64_t reserved_46_63               : 18;
 #endif
 	} cn63xxp1;
+	struct cvmx_lmcx_timing_params0_cn61xx cn66xx;
+	struct cvmx_lmcx_timing_params0_cn61xx cn68xx;
+	struct cvmx_lmcx_timing_params0_cn61xx cn68xxp1;
+	struct cvmx_lmcx_timing_params0_cn61xx cnf71xx;
 };
 typedef union cvmx_lmcx_timing_params0 cvmx_lmcx_timing_params0_t;
 
 /**
  * cvmx_lmc#_timing_params1
  */
-union cvmx_lmcx_timing_params1
-{
+union cvmx_lmcx_timing_params1 {
 	uint64_t u64;
-	struct cvmx_lmcx_timing_params1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_timing_params1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_47_63               : 17;
 	uint64_t tras_ext                     : 1;  /**< Indicates tRAS constraints.
                                                          Set [TRAS_EXT[0:0], TRAS[4:0]] (CSR field) = RNDUP[tRAS(ns)/tCYC(ns)]-1,
@@ -6456,20 +7801,20 @@ union cvmx_lmcx_timing_params1
                                                              - 0001: 2 (2 is the smallest value allowed)
                                                              - 0002: 2
                                                              - ...
-                                                             - 1001: 9
-                                                             - 1010-1111: RESERVED
+                                                             - 1110: 14
+                                                             - 1111: RESERVED
                                                          In 2T mode, make this register TRCD-1, not going
                                                          below 2. */
 	uint64_t tras                         : 5;  /**< Indicates tRAS constraints.
-                                                         Set TRAS (CSR field) = RNDUP[tRAS(ns)/tCYC(ns)]-1,
+                                                         Set [TRAS_EXT[0:0], TRAS[4:0]] (CSR field) = RNDUP[tRAS(ns)/tCYC(ns)]-1,
                                                          where tRAS is from the DDR3 spec, and tCYC(ns)
                                                          is the DDR clock frequency (not data rate).
                                                          TYP=35ns-9*tREFI
-                                                             - 00000: RESERVED
-                                                             - 00001: 2 tCYC
-                                                             - 00010: 3 tCYC
+                                                             - 000000: RESERVED
+                                                             - 000001: 2 tCYC
+                                                             - 000010: 3 tCYC
                                                              - ...
-                                                             - 11111: 32 tCYC */
+                                                             - 111111: 64 tCYC */
 	uint64_t tmprr                        : 4;  /**< Indicates tMPRR constraints.
                                                          Set TMPRR (CSR field) = RNDUP[tMPRR(ns)/tCYC(ns)]-1,
                                                          where tMPRR is from the DDR3 spec, and tCYC(ns)
@@ -6491,10 +7836,10 @@ union cvmx_lmcx_timing_params1
 	uint64_t reserved_47_63               : 17;
 #endif
 	} s;
+	struct cvmx_lmcx_timing_params1_s     cn61xx;
 	struct cvmx_lmcx_timing_params1_s     cn63xx;
-	struct cvmx_lmcx_timing_params1_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_timing_params1_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_46_63               : 18;
 	uint64_t txpdll                       : 5;  /**< Indicates tXPDLL constraints.
                                                          Set TXPDLL (CSR field) = RNDUP[tXPDLL(ns)/tCYC(ns)]-1,
@@ -6597,6 +7942,10 @@ union cvmx_lmcx_timing_params1
 	uint64_t reserved_46_63               : 18;
 #endif
 	} cn63xxp1;
+	struct cvmx_lmcx_timing_params1_s     cn66xx;
+	struct cvmx_lmcx_timing_params1_s     cn68xx;
+	struct cvmx_lmcx_timing_params1_s     cn68xxp1;
+	struct cvmx_lmcx_timing_params1_s     cnf71xx;
 };
 typedef union cvmx_lmcx_timing_params1 cvmx_lmcx_timing_params1_t;
 
@@ -6610,12 +7959,10 @@ typedef union cvmx_lmcx_timing_params1 cvmx_lmcx_timing_params1_t;
  * To bring up the temperature ring oscillator, write TRESET to 0, and follow by initializing RCLK_CNT to desired
  * value
  */
-union cvmx_lmcx_tro_ctl
-{
+union cvmx_lmcx_tro_ctl {
 	uint64_t u64;
-	struct cvmx_lmcx_tro_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_tro_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_33_63               : 31;
 	uint64_t rclk_cnt                     : 32; /**< rclk counter */
 	uint64_t treset                       : 1;  /**< Reset ring oscillator */
@@ -6625,8 +7972,13 @@ union cvmx_lmcx_tro_ctl
 	uint64_t reserved_33_63               : 31;
 #endif
 	} s;
+	struct cvmx_lmcx_tro_ctl_s            cn61xx;
 	struct cvmx_lmcx_tro_ctl_s            cn63xx;
 	struct cvmx_lmcx_tro_ctl_s            cn63xxp1;
+	struct cvmx_lmcx_tro_ctl_s            cn66xx;
+	struct cvmx_lmcx_tro_ctl_s            cn68xx;
+	struct cvmx_lmcx_tro_ctl_s            cn68xxp1;
+	struct cvmx_lmcx_tro_ctl_s            cnf71xx;
 };
 typedef union cvmx_lmcx_tro_ctl cvmx_lmcx_tro_ctl_t;
 
@@ -6636,12 +7988,10 @@ typedef union cvmx_lmcx_tro_ctl cvmx_lmcx_tro_ctl_t;
  * LMC_TRO_STAT = LMC Temperature Ring Osc Status
  * This register is an assortment of various control fields needed to control the temperature ring oscillator
  */
-union cvmx_lmcx_tro_stat
-{
+union cvmx_lmcx_tro_stat {
 	uint64_t u64;
-	struct cvmx_lmcx_tro_stat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_tro_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t ring_cnt                     : 32; /**< ring counter */
 #else
@@ -6649,20 +7999,23 @@ union cvmx_lmcx_tro_stat
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_lmcx_tro_stat_s           cn61xx;
 	struct cvmx_lmcx_tro_stat_s           cn63xx;
 	struct cvmx_lmcx_tro_stat_s           cn63xxp1;
+	struct cvmx_lmcx_tro_stat_s           cn66xx;
+	struct cvmx_lmcx_tro_stat_s           cn68xx;
+	struct cvmx_lmcx_tro_stat_s           cn68xxp1;
+	struct cvmx_lmcx_tro_stat_s           cnf71xx;
 };
 typedef union cvmx_lmcx_tro_stat cvmx_lmcx_tro_stat_t;
 
 /**
  * cvmx_lmc#_wlevel_ctl
  */
-union cvmx_lmcx_wlevel_ctl
-{
+union cvmx_lmcx_wlevel_ctl {
 	uint64_t u64;
-	struct cvmx_lmcx_wlevel_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_wlevel_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_22_63               : 42;
 	uint64_t rtt_nom                      : 3;  /**< RTT_NOM
                                                          LMC writes a decoded value to MR1[Rtt_Nom] of the rank during
@@ -6695,10 +8048,10 @@ union cvmx_lmcx_wlevel_ctl
 	uint64_t reserved_22_63               : 42;
 #endif
 	} s;
+	struct cvmx_lmcx_wlevel_ctl_s         cn61xx;
 	struct cvmx_lmcx_wlevel_ctl_s         cn63xx;
-	struct cvmx_lmcx_wlevel_ctl_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_wlevel_ctl_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t sset                         : 1;  /**< Run write-leveling on the current setting only. */
 	uint64_t lanemask                     : 9;  /**< One-hot mask to select byte lane to be leveled by
@@ -6711,6 +8064,10 @@ union cvmx_lmcx_wlevel_ctl
 	uint64_t reserved_10_63               : 54;
 #endif
 	} cn63xxp1;
+	struct cvmx_lmcx_wlevel_ctl_s         cn66xx;
+	struct cvmx_lmcx_wlevel_ctl_s         cn68xx;
+	struct cvmx_lmcx_wlevel_ctl_s         cn68xxp1;
+	struct cvmx_lmcx_wlevel_ctl_s         cnf71xx;
 };
 typedef union cvmx_lmcx_wlevel_ctl cvmx_lmcx_wlevel_ctl_t;
 
@@ -6726,12 +8083,10 @@ typedef union cvmx_lmcx_wlevel_ctl cvmx_lmcx_wlevel_ctl_t;
  * if you run write-leveling separately for each rank, probing LMC*_WLEVEL_DBG between each
  * write-leveling.
  */
-union cvmx_lmcx_wlevel_dbg
-{
+union cvmx_lmcx_wlevel_dbg {
 	uint64_t u64;
-	struct cvmx_lmcx_wlevel_dbg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_wlevel_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t bitmask                      : 8;  /**< Bitmask generated during deskew settings sweep
                                                          if LMCX_WLEVEL_CTL[SSET]=0
@@ -6750,8 +8105,13 @@ union cvmx_lmcx_wlevel_dbg
 	uint64_t reserved_12_63               : 52;
 #endif
 	} s;
+	struct cvmx_lmcx_wlevel_dbg_s         cn61xx;
 	struct cvmx_lmcx_wlevel_dbg_s         cn63xx;
 	struct cvmx_lmcx_wlevel_dbg_s         cn63xxp1;
+	struct cvmx_lmcx_wlevel_dbg_s         cn66xx;
+	struct cvmx_lmcx_wlevel_dbg_s         cn68xx;
+	struct cvmx_lmcx_wlevel_dbg_s         cn68xxp1;
+	struct cvmx_lmcx_wlevel_dbg_s         cnf71xx;
 };
 typedef union cvmx_lmcx_wlevel_dbg cvmx_lmcx_wlevel_dbg_t;
 
@@ -6783,12 +8143,10 @@ typedef union cvmx_lmcx_wlevel_dbg cvmx_lmcx_wlevel_dbg_t;
  *     LMC*_WLEVEL_RANKi = LMC*_WLEVEL_RANKj,
  * where j is some rank with attached DRAM whose LMC*_WLEVEL_RANKj is already fully initialized.
  */
-union cvmx_lmcx_wlevel_rankx
-{
+union cvmx_lmcx_wlevel_rankx {
 	uint64_t u64;
-	struct cvmx_lmcx_wlevel_rankx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_wlevel_rankx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_47_63               : 17;
 	uint64_t status                       : 2;  /**< Indicates status of the write-leveling and where
                                                          the BYTE* programmings in <44:0> came from:
@@ -6836,8 +8194,13 @@ union cvmx_lmcx_wlevel_rankx
 	uint64_t reserved_47_63               : 17;
 #endif
 	} s;
+	struct cvmx_lmcx_wlevel_rankx_s       cn61xx;
 	struct cvmx_lmcx_wlevel_rankx_s       cn63xx;
 	struct cvmx_lmcx_wlevel_rankx_s       cn63xxp1;
+	struct cvmx_lmcx_wlevel_rankx_s       cn66xx;
+	struct cvmx_lmcx_wlevel_rankx_s       cn68xx;
+	struct cvmx_lmcx_wlevel_rankx_s       cn68xxp1;
+	struct cvmx_lmcx_wlevel_rankx_s       cnf71xx;
 };
 typedef union cvmx_lmcx_wlevel_rankx cvmx_lmcx_wlevel_rankx_t;
 
@@ -6851,20 +8214,17 @@ typedef union cvmx_lmcx_wlevel_rankx cvmx_lmcx_wlevel_rankx_t;
  * Together, the LMC_WODT_CTL1 and LMC_WODT_CTL0 CSRs control the write ODT mask.  See LMC_WODT_CTL1.
  *
  */
-union cvmx_lmcx_wodt_ctl0
-{
+union cvmx_lmcx_wodt_ctl0 {
 	uint64_t u64;
-	struct cvmx_lmcx_wodt_ctl0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_wodt_ctl0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_0_63                : 64;
 #else
 	uint64_t reserved_0_63                : 64;
 #endif
 	} s;
-	struct cvmx_lmcx_wodt_ctl0_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_wodt_ctl0_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t wodt_d1_r1                   : 8;  /**< Write ODT mask DIMM1, RANK1 */
 	uint64_t wodt_d1_r0                   : 8;  /**< Write ODT mask DIMM1, RANK0 */
@@ -6879,9 +8239,8 @@ union cvmx_lmcx_wodt_ctl0
 #endif
 	} cn30xx;
 	struct cvmx_lmcx_wodt_ctl0_cn30xx     cn31xx;
-	struct cvmx_lmcx_wodt_ctl0_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_wodt_ctl0_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t wodt_hi3                     : 4;  /**< Write ODT mask for position 3, data[127:64] */
 	uint64_t wodt_hi2                     : 4;  /**< Write ODT mask for position 2, data[127:64] */
@@ -6946,12 +8305,10 @@ typedef union cvmx_lmcx_wodt_ctl0 cvmx_lmcx_wodt_ctl0_t;
  * Mask[1] -> DIMM0, RANK1    DIMM0
  * Mask[0] -> DIMM0, RANK0
  */
-union cvmx_lmcx_wodt_ctl1
-{
+union cvmx_lmcx_wodt_ctl1 {
 	uint64_t u64;
-	struct cvmx_lmcx_wodt_ctl1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_wodt_ctl1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t wodt_d3_r1                   : 8;  /**< Write ODT mask DIMM3, RANK1/DIMM3 in SingleRanked */
 	uint64_t wodt_d3_r0                   : 8;  /**< Write ODT mask DIMM3, RANK0 */
@@ -7016,32 +8373,30 @@ typedef union cvmx_lmcx_wodt_ctl1 cvmx_lmcx_wodt_ctl1_t;
  * Note that it may be necessary to force LMC to space back-to-back cache block writes
  * to different ranks apart by at least 10+LMC*_CONTROL[WODT_BPRCH] CK's to prevent DDR3 ODTH8 violations.
  */
-union cvmx_lmcx_wodt_mask
-{
+union cvmx_lmcx_wodt_mask {
 	uint64_t u64;
-	struct cvmx_lmcx_wodt_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_lmcx_wodt_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t wodt_d3_r1                   : 8;  /**< Write ODT mask DIMM3, RANK1/DIMM3 in SingleRanked
-                                                         *UNUSED IN 63xx, and MBZ* */
+                                                         *UNUSED IN 6xxx, and MBZ* */
 	uint64_t wodt_d3_r0                   : 8;  /**< Write ODT mask DIMM3, RANK0
-                                                         *UNUSED IN 63xx, and MBZ* */
+                                                         *UNUSED IN 6xxx, and MBZ* */
 	uint64_t wodt_d2_r1                   : 8;  /**< Write ODT mask DIMM2, RANK1/DIMM2 in SingleRanked
-                                                         *UNUSED IN 63xx, and MBZ* */
+                                                         *UNUSED IN 6xxx, and MBZ* */
 	uint64_t wodt_d2_r0                   : 8;  /**< Write ODT mask DIMM2, RANK0
-                                                         *UNUSED IN 63xx, and MBZ* */
+                                                         *UNUSED IN 6xxx, and MBZ* */
 	uint64_t wodt_d1_r1                   : 8;  /**< Write ODT mask DIMM1, RANK1/DIMM1 in SingleRanked
                                                          if (!RANK_ENA) then WODT_D1_R1[3:0] MBZ
-                                                         *Upper 4 bits UNUSED IN 63xx, and MBZ* */
+                                                         *Upper 4 bits UNUSED IN 6xxx, and MBZ* */
 	uint64_t wodt_d1_r0                   : 8;  /**< Write ODT mask DIMM1, RANK0
                                                          if (!RANK_ENA) then WODT_D1_R0[3,1] MBZ
-                                                         *Upper 4 bits UNUSED IN 63xx, and MBZ* */
+                                                         *Upper 4 bits UNUSED IN 6xxx, and MBZ* */
 	uint64_t wodt_d0_r1                   : 8;  /**< Write ODT mask DIMM0, RANK1/DIMM0 in SingleRanked
                                                          if (!RANK_ENA) then WODT_D0_R1[3:0] MBZ
-                                                         *Upper 4 bits UNUSED IN 63xx, and MBZ* */
+                                                         *Upper 4 bits UNUSED IN 6xxx, and MBZ* */
 	uint64_t wodt_d0_r0                   : 8;  /**< Write ODT mask DIMM0, RANK0
                                                          if (!RANK_ENA) then WODT_D0_R0[3,1] MBZ
-                                                         *Upper 4 bits UNUSED IN 63xx, and MBZ* */
+                                                         *Upper 4 bits UNUSED IN 6xxx, and MBZ* */
 #else
 	uint64_t wodt_d0_r0                   : 8;
 	uint64_t wodt_d0_r1                   : 8;
@@ -7053,8 +8408,13 @@ union cvmx_lmcx_wodt_mask
 	uint64_t wodt_d3_r1                   : 8;
 #endif
 	} s;
+	struct cvmx_lmcx_wodt_mask_s          cn61xx;
 	struct cvmx_lmcx_wodt_mask_s          cn63xx;
 	struct cvmx_lmcx_wodt_mask_s          cn63xxp1;
+	struct cvmx_lmcx_wodt_mask_s          cn66xx;
+	struct cvmx_lmcx_wodt_mask_s          cn68xx;
+	struct cvmx_lmcx_wodt_mask_s          cn68xxp1;
+	struct cvmx_lmcx_wodt_mask_s          cnf71xx;
 };
 typedef union cvmx_lmcx_wodt_mask cvmx_lmcx_wodt_mask_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-log-arc.S b/sys/contrib/octeon-sdk/cvmx-log-arc.S
index f57456a..bfb068e 100644
--- a/sys/contrib/octeon-sdk/cvmx-log-arc.S
+++ b/sys/contrib/octeon-sdk/cvmx-log-arc.S
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights 
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights 
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.  
@@ -26,7 +26,7 @@
  * countries. 
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-log.c b/sys/contrib/octeon-sdk/cvmx-log.c
index ea03d99..2944a2a 100644
--- a/sys/contrib/octeon-sdk/cvmx-log.c
+++ b/sys/contrib/octeon-sdk/cvmx-log.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -50,7 +50,7 @@
  * log data to a differnet buffer to avoid synchronization overhead. Function
  * call logging can be turned on with the GCC option "-pg".
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #include "cvmx.h"
 #include "cvmx-core.h"
diff --git a/sys/contrib/octeon-sdk/cvmx-log.h b/sys/contrib/octeon-sdk/cvmx-log.h
index 87fb61c..b8894e8 100644
--- a/sys/contrib/octeon-sdk/cvmx-log.h
+++ b/sys/contrib/octeon-sdk/cvmx-log.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -52,9 +52,15 @@
  * log data to a differnet buffer to avoid synchronization overhead. Function
  * call logging can be turned on with the GCC option "-pg".
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx-core.h>
+#else
+#include "cvmx-core.h"
+#endif
+
 #ifdef	__cplusplus
 extern "C" {
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-malloc.h b/sys/contrib/octeon-sdk/cvmx-malloc.h
index 5a872bd..2cad2bb 100644
--- a/sys/contrib/octeon-sdk/cvmx-malloc.h
+++ b/sys/contrib/octeon-sdk/cvmx-malloc.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -50,7 +50,7 @@
  * modified version of ptmalloc2 (used in glibc), and a zone allocator for allocating fixed
  * size memory blocks.
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_MALLOC_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-malloc/README-malloc b/sys/contrib/octeon-sdk/cvmx-malloc/README-malloc
new file mode 100644
index 0000000..922a713
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-malloc/README-malloc
@@ -0,0 +1,12 @@
+Readme for Octeon shared memory malloc
+
+This malloc is based on ptmalloc2, which is the malloc
+implementation of glibc.  Source code and more information
+on this can be found at http://www.malloc.de/en/index.html.
+Please see the individual files for licensing terms.
+
+The main change to the code modifies the way the malloc
+gets memory from the system.  Under Linux/Unix, malloc
+uses the brk or memmap sytem calls to request more memory.
+In this implementation, memory regions must be explicitly
+given to malloc by the application.
diff --git a/sys/contrib/octeon-sdk/cvmx-malloc/arena.c b/sys/contrib/octeon-sdk/cvmx-malloc/arena.c
new file mode 100644
index 0000000..8e0ce1f
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-malloc/arena.c
@@ -0,0 +1,293 @@
+/*
+Copyright (c) 2001 Wolfram Gloger
+Copyright (c) 2006 Cavium networks
+
+Permission to use, copy, modify, distribute, and sell this software
+and its documentation for any purpose is hereby granted without fee,
+provided that (i) the above copyright notices and this permission
+notice appear in all copies of the software and related documentation,
+and (ii) the name of Wolfram Gloger may not be used in any advertising
+or publicity relating to the software.
+
+THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND,
+EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY
+WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
+
+IN NO EVENT SHALL WOLFRAM GLOGER BE LIABLE FOR ANY SPECIAL,
+INCIDENTAL, INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY
+DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+WHETHER OR NOT ADVISED OF THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY
+OF LIABILITY, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+/* $Id: arena.c 30481 2007-12-05 21:46:59Z rfranz $ */
+
+/* Compile-time constants.  */
+
+#define HEAP_MIN_SIZE (4096)   /* Must leave room for struct malloc_state, arena ptrs, etc., totals about 2400 bytes */
+
+#ifndef THREAD_STATS
+#define THREAD_STATS 0
+#endif
+
+/* If THREAD_STATS is non-zero, some statistics on mutex locking are
+   computed.  */
+
+/***************************************************************************/
+
+// made static to avoid conflicts with newlib
+static mstate         _int_new_arena __MALLOC_P ((size_t __ini_size));
+
+/***************************************************************************/
+
+#define top(ar_ptr) ((ar_ptr)->top)
+
+/* A heap is a single contiguous memory region holding (coalesceable)
+   malloc_chunks.    Not used unless compiling with
+   USE_ARENAS. */
+
+typedef struct _heap_info {
+  mstate ar_ptr; /* Arena for this heap. */
+  struct _heap_info *prev; /* Previous heap. */
+  size_t size;   /* Current size in bytes. */
+  size_t pad;    /* Make sure the following data is properly aligned. */
+} heap_info;
+
+/* Thread specific data */
+
+static tsd_key_t arena_key;  // one per PP (thread)
+static CVMX_SHARED mutex_t list_lock;  // shared...
+
+#if THREAD_STATS
+static int stat_n_heaps;
+#define THREAD_STAT(x) x
+#else
+#define THREAD_STAT(x) do ; while(0)
+#endif
+
+/* Mapped memory in non-main arenas (reliable only for NO_THREADS). */
+static unsigned long arena_mem;
+
+/* Already initialized? */
+int CVMX_SHARED cvmx__malloc_initialized = -1;
+
+/**************************************************************************/
+
+#if USE_ARENAS
+
+/* find the heap and corresponding arena for a given ptr */
+
+#define arena_for_chunk(ptr) ((ptr)->arena_ptr)
+#define set_arena_for_chunk(ptr, arena) (ptr)->arena_ptr = (arena)
+
+
+#endif /* USE_ARENAS */
+
+/**************************************************************************/
+
+#ifndef NO_THREADS
+
+/* atfork support.  */
+
+static __malloc_ptr_t (*save_malloc_hook) __MALLOC_P ((size_t __size,
+						       __const __malloc_ptr_t));
+static void           (*save_free_hook) __MALLOC_P ((__malloc_ptr_t __ptr,
+						     __const __malloc_ptr_t));
+static Void_t*        save_arena;
+
+/* Magic value for the thread-specific arena pointer when
+   malloc_atfork() is in use.  */
+
+#define ATFORK_ARENA_PTR ((Void_t*)-1)
+
+/* The following hooks are used while the `atfork' handling mechanism
+   is active. */
+
+static Void_t*
+malloc_atfork(size_t sz, const Void_t *caller)
+{
+return(NULL);
+}
+
+static void
+free_atfork(Void_t* mem, const Void_t *caller)
+{
+  Void_t *vptr = NULL;
+  mstate ar_ptr;
+  mchunkptr p;                          /* chunk corresponding to mem */
+
+  if (mem == 0)                              /* free(0) has no effect */
+    return;
+
+  p = mem2chunk(mem);         /* do not bother to replicate free_check here */
+
+#if HAVE_MMAP
+  if (chunk_is_mmapped(p))                       /* release mmapped memory. */
+  {
+    munmap_chunk(p);
+    return;
+  }
+#endif
+
+  ar_ptr = arena_for_chunk(p);
+  tsd_getspecific(arena_key, vptr);
+  if(vptr != ATFORK_ARENA_PTR)
+    (void)mutex_lock(&ar_ptr->mutex);
+  _int_free(ar_ptr, mem);
+  if(vptr != ATFORK_ARENA_PTR)
+    (void)mutex_unlock(&ar_ptr->mutex);
+}
+
+
+
+#ifdef __linux__
+#error   __linux__defined!
+#endif
+
+#endif /* !defined NO_THREADS */
+
+
+
+/* Initialization routine. */
+#ifdef _LIBC
+#error  _LIBC is defined, and should not be
+#endif /* _LIBC */
+
+static CVMX_SHARED cvmx_spinlock_t malloc_init_spin_lock;
+
+
+
+
+/* Managing heaps and arenas (for concurrent threads) */
+
+#if USE_ARENAS
+
+#if MALLOC_DEBUG > 1
+
+/* Print the complete contents of a single heap to stderr. */
+
+static void
+#if __STD_C
+dump_heap(heap_info *heap)
+#else
+dump_heap(heap) heap_info *heap;
+#endif
+{
+  char *ptr;
+  mchunkptr p;
+
+  fprintf(stderr, "Heap %p, size %10lx:\n", heap, (long)heap->size);
+  ptr = (heap->ar_ptr != (mstate)(heap+1)) ?
+    (char*)(heap + 1) : (char*)(heap + 1) + sizeof(struct malloc_state);
+  p = (mchunkptr)(((unsigned long)ptr + MALLOC_ALIGN_MASK) &
+                  ~MALLOC_ALIGN_MASK);
+  for(;;) {
+    fprintf(stderr, "chunk %p size %10lx", p, (long)p->size);
+    if(p == top(heap->ar_ptr)) {
+      fprintf(stderr, " (top)\n");
+      break;
+    } else if(p->size == (0|PREV_INUSE)) {
+      fprintf(stderr, " (fence)\n");
+      break;
+    }
+    fprintf(stderr, "\n");
+    p = next_chunk(p);
+  }
+}
+
+#endif /* MALLOC_DEBUG > 1 */
+/* Delete a heap. */
+
+
+static mstate cvmx_new_arena(void *addr, size_t size)
+{
+  mstate a;
+  heap_info *h;
+  char *ptr;
+  unsigned long misalign;
+  int page_mask = malloc_getpagesize - 1;
+
+  debug_printf("cvmx_new_arena called, addr: %p, size %ld\n", addr, size);
+  debug_printf("heapinfo size: %ld, mstate size: %d\n", sizeof(heap_info), sizeof(struct malloc_state));
+
+  if (!addr || (size < HEAP_MIN_SIZE))
+  {
+      return(NULL);
+  }
+  /* We must zero out the arena as the malloc code assumes this. */
+  memset(addr, 0, size);
+
+  h = (heap_info *)addr;
+  h->size = size;
+
+  a = h->ar_ptr = (mstate)(h+1);
+  malloc_init_state(a);
+  /*a->next = NULL;*/
+  a->system_mem = a->max_system_mem = h->size;
+  arena_mem += h->size;
+  a->next = a;
+
+  /* Set up the top chunk, with proper alignment. */
+  ptr = (char *)(a + 1);
+  misalign = (unsigned long)chunk2mem(ptr) & MALLOC_ALIGN_MASK;
+  if (misalign > 0)
+    ptr += MALLOC_ALIGNMENT - misalign;
+  top(a) = (mchunkptr)ptr;
+  set_head(top(a), (((char*)h + h->size) - ptr) | PREV_INUSE);
+
+  return a;
+}
+
+
+int cvmx_add_arena(cvmx_arena_list_t *arena_list, void *ptr, size_t size)
+{
+  mstate a;
+
+  /* Enforce required alignement, and adjust size */
+  int misaligned = ((size_t)ptr) & (MALLOC_ALIGNMENT - 1);
+  if (misaligned)
+  {
+      ptr = (char*)ptr + MALLOC_ALIGNMENT - misaligned;
+      size -= MALLOC_ALIGNMENT - misaligned;
+  }
+
+  debug_printf("Adding arena at addr: %p, size %d\n", ptr, size);
+
+  a = cvmx_new_arena(ptr, size);  /* checks ptr and size */
+  if (!a)
+  {
+      return(-1);
+  }
+
+  debug_printf("cmvx_add_arena - arena_list: %p, *arena_list: %p\n", arena_list, *arena_list);
+  debug_printf("cmvx_add_arena - list: %p, new: %p\n", *arena_list, a);
+  mutex_init(&a->mutex);
+  mutex_lock(&a->mutex);
+
+
+  if (*arena_list)
+  {
+      mstate ar_ptr = *arena_list;
+      (void)mutex_lock(&ar_ptr->mutex);
+      a->next = ar_ptr->next;  // lock held on a and ar_ptr
+      ar_ptr->next = a;
+      (void)mutex_unlock(&ar_ptr->mutex);
+  }
+  else
+  {
+      *arena_list = a;
+//      a->next = a;
+  }
+
+  debug_printf("cvmx_add_arena - list: %p, list->next: %p\n", *arena_list, ((mstate)*arena_list)->next);
+
+  // unlock, since it is not going to be used immediately
+  (void)mutex_unlock(&a->mutex);
+
+  return(0);
+}
+
+
+
+#endif /* USE_ARENAS */
diff --git a/sys/contrib/octeon-sdk/cvmx-malloc/malloc.c b/sys/contrib/octeon-sdk/cvmx-malloc/malloc.c
new file mode 100644
index 0000000..222ad5d
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-malloc/malloc.c
@@ -0,0 +1,4106 @@
+/*
+Copyright (c) 2001 Wolfram Gloger
+Copyright (c) 2006 Cavium networks
+
+Permission to use, copy, modify, distribute, and sell this software
+and its documentation for any purpose is hereby granted without fee,
+provided that (i) the above copyright notices and this permission
+notice appear in all copies of the software and related documentation,
+and (ii) the name of Wolfram Gloger may not be used in any advertising
+or publicity relating to the software.
+
+THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND,
+EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY
+WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
+
+IN NO EVENT SHALL WOLFRAM GLOGER BE LIABLE FOR ANY SPECIAL,
+INCIDENTAL, INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY
+DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+WHETHER OR NOT ADVISED OF THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY
+OF LIABILITY, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+/*
+  This is a version (aka ptmalloc2) of malloc/free/realloc written by
+  Doug Lea and adapted to multiple threads/arenas by Wolfram Gloger.
+
+* Version ptmalloc2-20011215
+  $Id: malloc.c 30481 2007-12-05 21:46:59Z rfranz $
+  based on:
+  VERSION 2.7.1pre1 Sat May 12 07:41:21 2001  Doug Lea  (dl at gee)
+
+   Note: There may be an updated version of this malloc obtainable at
+           http://www.malloc.de/malloc/ptmalloc2.tar.gz
+         Check before installing!
+
+* Quickstart
+
+  In order to compile this implementation, a Makefile is provided with
+  the ptmalloc2 distribution, which has pre-defined targets for some
+  popular systems (e.g. "make posix" for Posix threads).  All that is
+  typically required with regard to compiler flags is the selection of
+  the thread package via defining one out of USE_PTHREADS, USE_THR or
+  USE_SPROC.  Check the thread-m.h file for what effects this has.
+  Many/most systems will additionally require USE_TSD_DATA_HACK to be
+  defined, so this is the default for "make posix".
+
+* Why use this malloc?
+
+  This is not the fastest, most space-conserving, most portable, or
+  most tunable malloc ever written. However it is among the fastest
+  while also being among the most space-conserving, portable and tunable.
+  Consistent balance across these factors results in a good general-purpose
+  allocator for malloc-intensive programs.
+
+  The main properties of the algorithms are:
+  * For large (>= 512 bytes) requests, it is a pure best-fit allocator,
+    with ties normally decided via FIFO (i.e. least recently used).
+  * For small (<= 64 bytes by default) requests, it is a caching
+    allocator, that maintains pools of quickly recycled chunks.
+  * In between, and for combinations of large and small requests, it does
+    the best it can trying to meet both goals at once.
+  * For very large requests (>= 128KB by default), it relies on system
+    memory mapping facilities, if supported.
+
+  For a longer but slightly out of date high-level description, see
+     http://gee.cs.oswego.edu/dl/html/malloc.html
+
+  You may already by default be using a C library containing a malloc
+  that is  based on some version of this malloc (for example in
+  linux). You might still want to use the one in this file in order to
+  customize settings or to avoid overheads associated with library
+  versions.
+
+* Contents, described in more detail in "description of public routines" below.
+
+  Standard (ANSI/SVID/...)  functions:
+    malloc(size_t n);
+    calloc(size_t n_elements, size_t element_size);
+    free(Void_t* p);
+    realloc(Void_t* p, size_t n);
+    memalign(size_t alignment, size_t n);
+    valloc(size_t n);
+    mallinfo()
+    mallopt(int parameter_number, int parameter_value)
+
+  Additional functions:
+    independent_calloc(size_t n_elements, size_t size, Void_t* chunks[]);
+    independent_comalloc(size_t n_elements, size_t sizes[], Void_t* chunks[]);
+    pvalloc(size_t n);
+    cfree(Void_t* p);
+    malloc_trim(size_t pad);
+    malloc_usable_size(Void_t* p);
+    malloc_stats();
+
+* Vital statistics:
+
+  Supported pointer representation:       4 or 8 bytes
+  Supported size_t  representation:       4 or 8 bytes
+       Note that size_t is allowed to be 4 bytes even if pointers are 8.
+       You can adjust this by defining INTERNAL_SIZE_T
+
+  Alignment:                              2 * sizeof(size_t) (default)
+       (i.e., 8 byte alignment with 4byte size_t). This suffices for
+       nearly all current machines and C compilers. However, you can
+       define MALLOC_ALIGNMENT to be wider than this if necessary.
+
+  Minimum overhead per allocated chunk:   4 or 8 bytes
+       Each malloced chunk has a hidden word of overhead holding size
+       and status information.
+
+  Minimum allocated size: 4-byte ptrs:  16 bytes    (including 4 overhead)
+                          8-byte ptrs:  24/32 bytes (including, 4/8 overhead)
+
+       When a chunk is freed, 12 (for 4byte ptrs) or 20 (for 8 byte
+       ptrs but 4 byte size) or 24 (for 8/8) additional bytes are
+       needed; 4 (8) for a trailing size field and 8 (16) bytes for
+       free list pointers. Thus, the minimum allocatable size is
+       16/24/32 bytes.
+
+       Even a request for zero bytes (i.e., malloc(0)) returns a
+       pointer to something of the minimum allocatable size.
+
+       The maximum overhead wastage (i.e., number of extra bytes
+       allocated than were requested in malloc) is less than or equal
+       to the minimum size, except for requests >= mmap_threshold that
+       are serviced via mmap(), where the worst case wastage is 2 *
+       sizeof(size_t) bytes plus the remainder from a system page (the
+       minimal mmap unit); typically 4096 or 8192 bytes.
+
+  Maximum allocated size:  4-byte size_t: 2^32 minus about two pages
+                           8-byte size_t: 2^64 minus about two pages
+
+       It is assumed that (possibly signed) size_t values suffice to
+       represent chunk sizes. `Possibly signed' is due to the fact
+       that `size_t' may be defined on a system as either a signed or
+       an unsigned type. The ISO C standard says that it must be
+       unsigned, but a few systems are known not to adhere to this.
+       Additionally, even when size_t is unsigned, sbrk (which is by
+       default used to obtain memory from system) accepts signed
+       arguments, and may not be able to handle size_t-wide arguments
+       with negative sign bit.  Generally, values that would
+       appear as negative after accounting for overhead and alignment
+       are supported only via mmap(), which does not have this
+       limitation.
+
+       Requests for sizes outside the allowed range will perform an optional
+       failure action and then return null. (Requests may also
+       also fail because a system is out of memory.)
+
+  Thread-safety: thread-safe unless NO_THREADS is defined
+
+  Compliance: I believe it is compliant with the 1997 Single Unix Specification
+       (See http://www.opennc.org). Also SVID/XPG, ANSI C, and probably
+       others as well.
+
+* Synopsis of compile-time options:
+
+    People have reported using previous versions of this malloc on all
+    versions of Unix, sometimes by tweaking some of the defines
+    below. It has been tested most extensively on Solaris and
+    Linux. It is also reported to work on WIN32 platforms.
+    People also report using it in stand-alone embedded systems.
+
+    The implementation is in straight, hand-tuned ANSI C.  It is not
+    at all modular. (Sorry!)  It uses a lot of macros.  To be at all
+    usable, this code should be compiled using an optimizing compiler
+    (for example gcc -O3) that can simplify expressions and control
+    paths. (FAQ: some macros import variables as arguments rather than
+    declare locals because people reported that some debuggers
+    otherwise get confused.)
+
+    OPTION                     DEFAULT VALUE
+
+    Compilation Environment options:
+
+    __STD_C                    derived from C compiler defines
+    WIN32                      NOT defined
+    HAVE_MEMCPY                defined
+    USE_MEMCPY                 1 if HAVE_MEMCPY is defined
+    HAVE_MMAP                  defined as 1
+    MMAP_CLEARS                1
+    HAVE_MREMAP                0 unless linux defined
+    USE_ARENAS                 the same as HAVE_MMAP
+    malloc_getpagesize         derived from system #includes, or 4096 if not
+    HAVE_USR_INCLUDE_MALLOC_H  NOT defined
+    LACKS_UNISTD_H             NOT defined unless WIN32
+    LACKS_SYS_PARAM_H          NOT defined unless WIN32
+    LACKS_SYS_MMAN_H           NOT defined unless WIN32
+
+    Changing default word sizes:
+
+    INTERNAL_SIZE_T            size_t
+    MALLOC_ALIGNMENT           2 * sizeof(INTERNAL_SIZE_T)
+
+    Configuration and functionality options:
+
+    USE_DL_PREFIX              NOT defined
+    USE_PUBLIC_MALLOC_WRAPPERS NOT defined
+    USE_MALLOC_LOCK            NOT defined
+    MALLOC_DEBUG               NOT defined
+    REALLOC_ZERO_BYTES_FREES   1
+    MALLOC_FAILURE_ACTION      errno = ENOMEM, if __STD_C defined, else no-op
+    TRIM_FASTBINS              0
+    FIRST_SORTED_BIN_SIZE      512
+
+    Options for customizing MORECORE:
+
+    MORECORE                   sbrk
+    MORECORE_FAILURE           -1
+    MORECORE_CONTIGUOUS        1
+    MORECORE_CANNOT_TRIM       NOT defined
+    MORECORE_CLEARS            1
+    MMAP_AS_MORECORE_SIZE      (1024 * 1024)
+
+    Tuning options that are also dynamically changeable via mallopt:
+
+    DEFAULT_MXFAST             64
+    DEFAULT_TRIM_THRESHOLD     128 * 1024
+    DEFAULT_TOP_PAD            0
+    DEFAULT_MMAP_THRESHOLD     128 * 1024
+    DEFAULT_MMAP_MAX           65536
+
+    There are several other #defined constants and macros that you
+    probably don't want to touch unless you are extending or adapting malloc.  */
+
+/*
+  __STD_C should be nonzero if using ANSI-standard C compiler, a C++
+  compiler, or a C compiler sufficiently close to ANSI to get away
+  with it.
+*/
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-spinlock.h"
+#include "cvmx-malloc.h"
+
+
+#ifndef __STD_C
+#if defined(__STDC__) || defined(__cplusplus)
+#define __STD_C     1
+#else
+#define __STD_C     0
+#endif
+#endif /*__STD_C*/
+
+
+/*
+  Void_t* is the pointer type that malloc should say it returns
+*/
+
+#ifndef Void_t
+#if 1
+#define Void_t      void
+#else
+#define Void_t      char
+#endif
+#endif /*Void_t*/
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* define LACKS_UNISTD_H if your system does not have a <unistd.h>. */
+
+/* #define  LACKS_UNISTD_H */
+
+#ifndef LACKS_UNISTD_H
+#include <unistd.h>
+#endif
+
+/* define LACKS_SYS_PARAM_H if your system does not have a <sys/param.h>. */
+
+/* #define  LACKS_SYS_PARAM_H */
+
+
+#include <stdio.h>    /* needed for malloc_stats */
+#include <errno.h>    /* needed for optional MALLOC_FAILURE_ACTION */
+
+
+/*
+  Debugging:
+
+  Because freed chunks may be overwritten with bookkeeping fields, this
+  malloc will often die when freed memory is overwritten by user
+  programs.  This can be very effective (albeit in an annoying way)
+  in helping track down dangling pointers.
+
+  If you compile with -DMALLOC_DEBUG, a number of assertion checks are
+  enabled that will catch more memory errors. You probably won't be
+  able to make much sense of the actual assertion errors, but they
+  should help you locate incorrectly overwritten memory.  The checking
+  is fairly extensive, and will slow down execution
+  noticeably. Calling malloc_stats or mallinfo with MALLOC_DEBUG set
+  will attempt to check every non-mmapped allocated and free chunk in
+  the course of computing the summmaries. (By nature, mmapped regions
+  cannot be checked very much automatically.)
+
+  Setting MALLOC_DEBUG may also be helpful if you are trying to modify
+  this code. The assertions in the check routines spell out in more
+  detail the assumptions and invariants underlying the algorithms.
+
+  Setting MALLOC_DEBUG does NOT provide an automated mechanism for
+  checking that all accesses to malloced memory stay within their
+  bounds. However, there are several add-ons and adaptations of this
+  or other mallocs available that do this.
+*/
+
+#define MALLOC_DEBUG 1
+#if MALLOC_DEBUG
+#include <assert.h>
+#else
+#define assert(x) ((void)0)
+#endif
+
+
+/*
+  INTERNAL_SIZE_T is the word-size used for internal bookkeeping
+  of chunk sizes.
+
+  The default version is the same as size_t.
+
+  While not strictly necessary, it is best to define this as an
+  unsigned type, even if size_t is a signed type. This may avoid some
+  artificial size limitations on some systems.
+
+  On a 64-bit machine, you may be able to reduce malloc overhead by
+  defining INTERNAL_SIZE_T to be a 32 bit `unsigned int' at the
+  expense of not being able to handle more than 2^32 of malloced
+  space. If this limitation is acceptable, you are encouraged to set
+  this unless you are on a platform requiring 16byte alignments. In
+  this case the alignment requirements turn out to negate any
+  potential advantages of decreasing size_t word size.
+
+  Implementors: Beware of the possible combinations of:
+     - INTERNAL_SIZE_T might be signed or unsigned, might be 32 or 64 bits,
+       and might be the same width as int or as long
+     - size_t might have different width and signedness as INTERNAL_SIZE_T
+     - int and long might be 32 or 64 bits, and might be the same width
+  To deal with this, most comparisons and difference computations
+  among INTERNAL_SIZE_Ts should cast them to unsigned long, being
+  aware of the fact that casting an unsigned int to a wider long does
+  not sign-extend. (This also makes checking for negative numbers
+  awkward.) Some of these casts result in harmless compiler warnings
+  on some systems.
+*/
+
+#ifndef INTERNAL_SIZE_T
+#define INTERNAL_SIZE_T size_t
+#endif
+
+/* The corresponding word size */
+#define SIZE_SZ                (sizeof(INTERNAL_SIZE_T))
+
+
+/*
+  MALLOC_ALIGNMENT is the minimum alignment for malloc'ed chunks.
+  It must be a power of two at least 2 * SIZE_SZ, even on machines
+  for which smaller alignments would suffice. It may be defined as
+  larger than this though. Note however that code and data structures
+  are optimized for the case of 8-byte alignment.
+*/
+
+
+#ifndef MALLOC_ALIGNMENT
+#define MALLOC_ALIGNMENT       (2 * SIZE_SZ)
+#endif
+
+/* The corresponding bit mask value */
+#define MALLOC_ALIGN_MASK      (MALLOC_ALIGNMENT - 1)
+
+
+
+/*
+  REALLOC_ZERO_BYTES_FREES should be set if a call to
+  realloc with zero bytes should be the same as a call to free.
+  This is required by the C standard. Otherwise, since this malloc
+  returns a unique pointer for malloc(0), so does realloc(p, 0).
+*/
+
+#ifndef REALLOC_ZERO_BYTES_FREES
+#define REALLOC_ZERO_BYTES_FREES 1
+#endif
+
+/*
+  TRIM_FASTBINS controls whether free() of a very small chunk can
+  immediately lead to trimming. Setting to true (1) can reduce memory
+  footprint, but will almost always slow down programs that use a lot
+  of small chunks.
+
+  Define this only if you are willing to give up some speed to more
+  aggressively reduce system-level memory footprint when releasing
+  memory in programs that use many small chunks.  You can get
+  essentially the same effect by setting MXFAST to 0, but this can
+  lead to even greater slowdowns in programs using many small chunks.
+  TRIM_FASTBINS is an in-between compile-time option, that disables
+  only those chunks bordering topmost memory from being placed in
+  fastbins.
+*/
+
+#ifndef TRIM_FASTBINS
+#define TRIM_FASTBINS  0
+#endif
+
+
+/*
+  USE_DL_PREFIX will prefix all public routines with the string 'dl'.
+  This is necessary when you only want to use this malloc in one part
+  of a program, using your regular system malloc elsewhere.
+*/
+
+#define USE_DL_PREFIX
+
+
+/*
+   Two-phase name translation.
+   All of the actual routines are given mangled names.
+   When wrappers are used, they become the public callable versions.
+   When DL_PREFIX is used, the callable names are prefixed.
+*/
+
+#ifdef USE_DL_PREFIX
+#define public_cALLOc    cvmx_calloc
+#define public_fREe      cvmx_free
+#define public_cFREe     dlcfree
+#define public_mALLOc    cvmx_malloc
+#define public_mEMALIGn  cvmx_memalign
+#define public_rEALLOc   cvmx_realloc
+#define public_vALLOc    dlvalloc
+#define public_pVALLOc   dlpvalloc
+#define public_mALLINFo  dlmallinfo
+#define public_mALLOPt   dlmallopt
+#define public_mTRIm     dlmalloc_trim
+#define public_mSTATs    dlmalloc_stats
+#define public_mUSABLe   dlmalloc_usable_size
+#define public_iCALLOc   dlindependent_calloc
+#define public_iCOMALLOc dlindependent_comalloc
+#define public_gET_STATe dlget_state
+#define public_sET_STATe dlset_state
+#else /* USE_DL_PREFIX */
+#ifdef _LIBC
+#error _LIBC defined and should not be
+/* Special defines for the GNU C library.  */
+#define public_cALLOc    __libc_calloc
+#define public_fREe      __libc_free
+#define public_cFREe     __libc_cfree
+#define public_mALLOc    __libc_malloc
+#define public_mEMALIGn  __libc_memalign
+#define public_rEALLOc   __libc_realloc
+#define public_vALLOc    __libc_valloc
+#define public_pVALLOc   __libc_pvalloc
+#define public_mALLINFo  __libc_mallinfo
+#define public_mALLOPt   __libc_mallopt
+#define public_mTRIm     __malloc_trim
+#define public_mSTATs    __malloc_stats
+#define public_mUSABLe   __malloc_usable_size
+#define public_iCALLOc   __libc_independent_calloc
+#define public_iCOMALLOc __libc_independent_comalloc
+#define public_gET_STATe __malloc_get_state
+#define public_sET_STATe __malloc_set_state
+#define malloc_getpagesize __getpagesize()
+#define open             __open
+#define mmap             __mmap
+#define munmap           __munmap
+#define mremap           __mremap
+#define mprotect         __mprotect
+#define MORECORE         (*__morecore)
+#define MORECORE_FAILURE 0
+
+Void_t * __default_morecore (ptrdiff_t);
+Void_t *(*__morecore)(ptrdiff_t) = __default_morecore;
+
+#else /* !_LIBC */
+#define public_cALLOc    calloc
+#define public_fREe      free
+#define public_cFREe     cfree
+#define public_mALLOc    malloc
+#define public_mEMALIGn  memalign
+#define public_rEALLOc   realloc
+#define public_vALLOc    valloc
+#define public_pVALLOc   pvalloc
+#define public_mALLINFo  mallinfo
+#define public_mALLOPt   mallopt
+#define public_mTRIm     malloc_trim
+#define public_mSTATs    malloc_stats
+#define public_mUSABLe   malloc_usable_size
+#define public_iCALLOc   independent_calloc
+#define public_iCOMALLOc independent_comalloc
+#define public_gET_STATe malloc_get_state
+#define public_sET_STATe malloc_set_state
+#endif /* _LIBC */
+#endif /* USE_DL_PREFIX */
+
+
+/*
+  HAVE_MEMCPY should be defined if you are not otherwise using
+  ANSI STD C, but still have memcpy and memset in your C library
+  and want to use them in calloc and realloc. Otherwise simple
+  macro versions are defined below.
+
+  USE_MEMCPY should be defined as 1 if you actually want to
+  have memset and memcpy called. People report that the macro
+  versions are faster than libc versions on some systems.
+
+  Even if USE_MEMCPY is set to 1, loops to copy/clear small chunks
+  (of <= 36 bytes) are manually unrolled in realloc and calloc.
+*/
+
+#define HAVE_MEMCPY
+
+#ifndef USE_MEMCPY
+#ifdef HAVE_MEMCPY
+#define USE_MEMCPY 1
+#else
+#define USE_MEMCPY 0
+#endif
+#endif
+
+
+#if (__STD_C || defined(HAVE_MEMCPY))
+
+#ifdef WIN32
+/* On Win32 memset and memcpy are already declared in windows.h */
+#else
+#if __STD_C
+void* memset(void*, int, size_t);
+void* memcpy(void*, const void*, size_t);
+#else
+Void_t* memset();
+Void_t* memcpy();
+#endif
+#endif
+#endif
+
+/*
+  MALLOC_FAILURE_ACTION is the action to take before "return 0" when
+  malloc fails to be able to return memory, either because memory is
+  exhausted or because of illegal arguments.
+
+  By default, sets errno if running on STD_C platform, else does nothing.
+*/
+
+#ifndef MALLOC_FAILURE_ACTION
+#if __STD_C
+#define MALLOC_FAILURE_ACTION \
+   errno = ENOMEM;
+
+#else
+#define MALLOC_FAILURE_ACTION
+#endif
+#endif
+
+/*
+  MORECORE-related declarations. By default, rely on sbrk
+*/
+
+
+#ifdef LACKS_UNISTD_H
+#if !defined(__FreeBSD__) && !defined(__OpenBSD__) && !defined(__NetBSD__)
+#if __STD_C
+extern Void_t*     sbrk(ptrdiff_t);
+#else
+extern Void_t*     sbrk();
+#endif
+#endif
+#endif
+
+/*
+  MORECORE is the name of the routine to call to obtain more memory
+  from the system.  See below for general guidance on writing
+  alternative MORECORE functions, as well as a version for WIN32 and a
+  sample version for pre-OSX macos.
+*/
+#undef MORECORE  // not supported
+#ifndef MORECORE
+#define MORECORE notsupported
+#endif
+
+/*
+  MORECORE_FAILURE is the value returned upon failure of MORECORE
+  as well as mmap. Since it cannot be an otherwise valid memory address,
+  and must reflect values of standard sys calls, you probably ought not
+  try to redefine it.
+*/
+
+#ifndef MORECORE_FAILURE
+#define MORECORE_FAILURE (-1)
+#endif
+
+/*
+  If MORECORE_CONTIGUOUS is true, take advantage of fact that
+  consecutive calls to MORECORE with positive arguments always return
+  contiguous increasing addresses.  This is true of unix sbrk.  Even
+  if not defined, when regions happen to be contiguous, malloc will
+  permit allocations spanning regions obtained from different
+  calls. But defining this when applicable enables some stronger
+  consistency checks and space efficiencies.
+*/
+
+#ifndef MORECORE_CONTIGUOUS
+#define MORECORE_CONTIGUOUS 0
+#endif
+
+/*
+  Define MORECORE_CANNOT_TRIM if your version of MORECORE
+  cannot release space back to the system when given negative
+  arguments. This is generally necessary only if you are using
+  a hand-crafted MORECORE function that cannot handle negative arguments.
+*/
+
+#define MORECORE_CANNOT_TRIM 1
+
+/*  MORECORE_CLEARS           (default 1)
+     The degree to which the routine mapped to MORECORE zeroes out
+     memory: never (0), only for newly allocated space (1) or always
+     (2).  The distinction between (1) and (2) is necessary because on
+     some systems, if the application first decrements and then
+     increments the break value, the contents of the reallocated space
+     are unspecified.
+*/
+
+#ifndef MORECORE_CLEARS
+#define MORECORE_CLEARS 0
+#endif
+
+
+/*
+  Define HAVE_MMAP as true to optionally make malloc() use mmap() to
+  allocate very large blocks.  These will be returned to the
+  operating system immediately after a free(). Also, if mmap
+  is available, it is used as a backup strategy in cases where
+  MORECORE fails to provide space from system.
+
+  This malloc is best tuned to work with mmap for large requests.
+  If you do not have mmap, operations involving very large chunks (1MB
+  or so) may be slower than you'd like.
+*/
+
+#undef HAVE_MMAP
+#ifndef HAVE_MMAP
+#define HAVE_MMAP 0
+
+/*
+   Standard unix mmap using /dev/zero clears memory so calloc doesn't
+   need to.
+*/
+
+#ifndef MMAP_CLEARS
+#define MMAP_CLEARS 0
+#endif
+
+#else /* no mmap */
+#ifndef MMAP_CLEARS
+#define MMAP_CLEARS 0
+#endif
+#endif
+
+
+/*
+   MMAP_AS_MORECORE_SIZE is the minimum mmap size argument to use if
+   sbrk fails, and mmap is used as a backup (which is done only if
+   HAVE_MMAP).  The value must be a multiple of page size.  This
+   backup strategy generally applies only when systems have "holes" in
+   address space, so sbrk cannot perform contiguous expansion, but
+   there is still space available on system.  On systems for which
+   this is known to be useful (i.e. most linux kernels), this occurs
+   only when programs allocate huge amounts of memory.  Between this,
+   and the fact that mmap regions tend to be limited, the size should
+   be large, to avoid too many mmap calls and thus avoid running out
+   of kernel resources.
+*/
+
+#ifndef MMAP_AS_MORECORE_SIZE
+#define MMAP_AS_MORECORE_SIZE (1024 * 1024)
+#endif
+
+/*
+  Define HAVE_MREMAP to make realloc() use mremap() to re-allocate
+  large blocks.  This is currently only possible on Linux with
+  kernel versions newer than 1.3.77.
+*/
+#undef linux
+#ifndef HAVE_MREMAP
+#ifdef linux
+#define HAVE_MREMAP 1
+#else
+#define HAVE_MREMAP 0
+#endif
+
+#endif /* HAVE_MMAP */
+
+/* Define USE_ARENAS to enable support for multiple `arenas'.  These
+   are allocated using mmap(), are necessary for threads and
+   occasionally useful to overcome address space limitations affecting
+   sbrk(). */
+
+#ifndef USE_ARENAS
+#define USE_ARENAS 1  // we 'manually' mmap the arenas.....
+#endif
+
+
+/*
+  The system page size. To the extent possible, this malloc manages
+  memory from the system in page-size units.  Note that this value is
+  cached during initialization into a field of malloc_state. So even
+  if malloc_getpagesize is a function, it is only called once.
+
+  The following mechanics for getpagesize were adapted from bsd/gnu
+  getpagesize.h. If none of the system-probes here apply, a value of
+  4096 is used, which should be OK: If they don't apply, then using
+  the actual value probably doesn't impact performance.
+*/
+
+
+#define malloc_getpagesize (4096)
+#ifndef malloc_getpagesize
+
+#ifndef LACKS_UNISTD_H
+#  include <unistd.h>
+#endif
+
+#  ifdef _SC_PAGESIZE         /* some SVR4 systems omit an underscore */
+#    ifndef _SC_PAGE_SIZE
+#      define _SC_PAGE_SIZE _SC_PAGESIZE
+#    endif
+#  endif
+
+#  ifdef _SC_PAGE_SIZE
+#    define malloc_getpagesize sysconf(_SC_PAGE_SIZE)
+#  else
+#    if defined(BSD) || defined(DGUX) || defined(HAVE_GETPAGESIZE)
+       extern size_t getpagesize();
+#      define malloc_getpagesize getpagesize()
+#    else
+#      ifdef WIN32 /* use supplied emulation of getpagesize */
+#        define malloc_getpagesize getpagesize()
+#      else
+#        ifndef LACKS_SYS_PARAM_H
+#          include <sys/param.h>
+#        endif
+#        ifdef EXEC_PAGESIZE
+#          define malloc_getpagesize EXEC_PAGESIZE
+#        else
+#          ifdef NBPG
+#            ifndef CLSIZE
+#              define malloc_getpagesize NBPG
+#            else
+#              define malloc_getpagesize (NBPG * CLSIZE)
+#            endif
+#          else
+#            ifdef NBPC
+#              define malloc_getpagesize NBPC
+#            else
+#              ifdef PAGESIZE
+#                define malloc_getpagesize PAGESIZE
+#              else /* just guess */
+#                define malloc_getpagesize (4096)
+#              endif
+#            endif
+#          endif
+#        endif
+#      endif
+#    endif
+#  endif
+#endif
+
+/*
+  This version of malloc supports the standard SVID/XPG mallinfo
+  routine that returns a struct containing usage properties and
+  statistics. It should work on any SVID/XPG compliant system that has
+  a /usr/include/malloc.h defining struct mallinfo. (If you'd like to
+  install such a thing yourself, cut out the preliminary declarations
+  as described above and below and save them in a malloc.h file. But
+  there's no compelling reason to bother to do this.)
+
+  The main declaration needed is the mallinfo struct that is returned
+  (by-copy) by mallinfo().  The SVID/XPG malloinfo struct contains a
+  bunch of fields that are not even meaningful in this version of
+  malloc.  These fields are are instead filled by mallinfo() with
+  other numbers that might be of interest.
+
+  HAVE_USR_INCLUDE_MALLOC_H should be set if you have a
+  /usr/include/malloc.h file that includes a declaration of struct
+  mallinfo.  If so, it is included; else an SVID2/XPG2 compliant
+  version is declared below.  These must be precisely the same for
+  mallinfo() to work.  The original SVID version of this struct,
+  defined on most systems with mallinfo, declares all fields as
+  ints. But some others define as unsigned long. If your system
+  defines the fields using a type of different width than listed here,
+  you must #include your system version and #define
+  HAVE_USR_INCLUDE_MALLOC_H.
+*/
+
+/* #define HAVE_USR_INCLUDE_MALLOC_H */
+
+#ifdef HAVE_USR_INCLUDE_MALLOC_H
+#include "/usr/include/malloc.h"
+#endif
+
+
+/* ---------- description of public routines ------------ */
+
+/*
+  malloc(size_t n)
+  Returns a pointer to a newly allocated chunk of at least n bytes, or null
+  if no space is available. Additionally, on failure, errno is
+  set to ENOMEM on ANSI C systems.
+
+  If n is zero, malloc returns a minumum-sized chunk. (The minimum
+  size is 16 bytes on most 32bit systems, and 24 or 32 bytes on 64bit
+  systems.)  On most systems, size_t is an unsigned type, so calls
+  with negative arguments are interpreted as requests for huge amounts
+  of space, which will often fail. The maximum supported value of n
+  differs across systems, but is in all cases less than the maximum
+  representable value of a size_t.
+*/
+#if __STD_C
+Void_t*  public_mALLOc(cvmx_arena_list_t arena_list, size_t);
+#else
+Void_t*  public_mALLOc();
+#endif
+
+/*
+  free(Void_t* p)
+  Releases the chunk of memory pointed to by p, that had been previously
+  allocated using malloc or a related routine such as realloc.
+  It has no effect if p is null. It can have arbitrary (i.e., bad!)
+  effects if p has already been freed.
+
+  Unless disabled (using mallopt), freeing very large spaces will
+  when possible, automatically trigger operations that give
+  back unused memory to the system, thus reducing program footprint.
+*/
+#if __STD_C
+void     public_fREe(Void_t*);
+#else
+void     public_fREe();
+#endif
+
+/*
+  calloc(size_t n_elements, size_t element_size);
+  Returns a pointer to n_elements * element_size bytes, with all locations
+  set to zero.
+*/
+#if __STD_C
+Void_t*  public_cALLOc(cvmx_arena_list_t arena_list, size_t, size_t);
+#else
+Void_t*  public_cALLOc();
+#endif
+
+/*
+  realloc(Void_t* p, size_t n)
+  Returns a pointer to a chunk of size n that contains the same data
+  as does chunk p up to the minimum of (n, p's size) bytes, or null
+  if no space is available.
+
+  The returned pointer may or may not be the same as p. The algorithm
+  prefers extending p when possible, otherwise it employs the
+  equivalent of a malloc-copy-free sequence.
+
+  If p is null, realloc is equivalent to malloc.
+
+  If space is not available, realloc returns null, errno is set (if on
+  ANSI) and p is NOT freed.
+
+  if n is for fewer bytes than already held by p, the newly unused
+  space is lopped off and freed if possible.  Unless the #define
+  REALLOC_ZERO_BYTES_FREES is set, realloc with a size argument of
+  zero (re)allocates a minimum-sized chunk.
+
+  Large chunks that were internally obtained via mmap will always
+  be reallocated using malloc-copy-free sequences unless
+  the system supports MREMAP (currently only linux).
+
+  The old unix realloc convention of allowing the last-free'd chunk
+  to be used as an argument to realloc is not supported.
+*/
+#if __STD_C
+Void_t*  public_rEALLOc(cvmx_arena_list_t arena_list, Void_t*, size_t);
+#else
+Void_t*  public_rEALLOc();
+#endif
+
+/*
+  memalign(size_t alignment, size_t n);
+  Returns a pointer to a newly allocated chunk of n bytes, aligned
+  in accord with the alignment argument.
+
+  The alignment argument should be a power of two. If the argument is
+  not a power of two, the nearest greater power is used.
+  8-byte alignment is guaranteed by normal malloc calls, so don't
+  bother calling memalign with an argument of 8 or less.
+
+  Overreliance on memalign is a sure way to fragment space.
+*/
+#if __STD_C
+Void_t*  public_mEMALIGn(cvmx_arena_list_t arena_list, size_t, size_t);
+#else
+Void_t*  public_mEMALIGn();
+#endif
+
+/*
+  valloc(size_t n);
+  Equivalent to memalign(pagesize, n), where pagesize is the page
+  size of the system. If the pagesize is unknown, 4096 is used.
+*/
+#if __STD_C
+Void_t*  public_vALLOc(size_t);
+#else
+Void_t*  public_vALLOc();
+#endif
+
+
+
+/*
+  mallopt(int parameter_number, int parameter_value)
+  Sets tunable parameters The format is to provide a
+  (parameter-number, parameter-value) pair.  mallopt then sets the
+  corresponding parameter to the argument value if it can (i.e., so
+  long as the value is meaningful), and returns 1 if successful else
+  0.  SVID/XPG/ANSI defines four standard param numbers for mallopt,
+  normally defined in malloc.h.  Only one of these (M_MXFAST) is used
+  in this malloc. The others (M_NLBLKS, M_GRAIN, M_KEEP) don't apply,
+  so setting them has no effect. But this malloc also supports four
+  other options in mallopt. See below for details.  Briefly, supported
+  parameters are as follows (listed defaults are for "typical"
+  configurations).
+
+  Symbol            param #   default    allowed param values
+  M_MXFAST          1         64         0-80  (0 disables fastbins)
+  M_TRIM_THRESHOLD -1         128*1024   any   (-1U disables trimming)
+  M_TOP_PAD        -2         0          any
+  M_MMAP_THRESHOLD -3         128*1024   any   (or 0 if no MMAP support)
+  M_MMAP_MAX       -4         65536      any   (0 disables use of mmap)
+*/
+#if __STD_C
+int      public_mALLOPt(int, int);
+#else
+int      public_mALLOPt();
+#endif
+
+
+/*
+  mallinfo()
+  Returns (by copy) a struct containing various summary statistics:
+
+  arena:     current total non-mmapped bytes allocated from system
+  ordblks:   the number of free chunks
+  smblks:    the number of fastbin blocks (i.e., small chunks that
+               have been freed but not use resused or consolidated)
+  hblks:     current number of mmapped regions
+  hblkhd:    total bytes held in mmapped regions
+  usmblks:   the maximum total allocated space. This will be greater
+                than current total if trimming has occurred.
+  fsmblks:   total bytes held in fastbin blocks
+  uordblks:  current total allocated space (normal or mmapped)
+  fordblks:  total free space
+  keepcost:  the maximum number of bytes that could ideally be released
+               back to system via malloc_trim. ("ideally" means that
+               it ignores page restrictions etc.)
+
+  Because these fields are ints, but internal bookkeeping may
+  be kept as longs, the reported values may wrap around zero and
+  thus be inaccurate.
+*/
+#if __STD_C
+struct mallinfo public_mALLINFo(void);
+#else
+struct mallinfo public_mALLINFo();
+#endif
+
+/*
+  independent_calloc(size_t n_elements, size_t element_size, Void_t* chunks[]);
+
+  independent_calloc is similar to calloc, but instead of returning a
+  single cleared space, it returns an array of pointers to n_elements
+  independent elements that can hold contents of size elem_size, each
+  of which starts out cleared, and can be independently freed,
+  realloc'ed etc. The elements are guaranteed to be adjacently
+  allocated (this is not guaranteed to occur with multiple callocs or
+  mallocs), which may also improve cache locality in some
+  applications.
+
+  The "chunks" argument is optional (i.e., may be null, which is
+  probably the most typical usage). If it is null, the returned array
+  is itself dynamically allocated and should also be freed when it is
+  no longer needed. Otherwise, the chunks array must be of at least
+  n_elements in length. It is filled in with the pointers to the
+  chunks.
+
+  In either case, independent_calloc returns this pointer array, or
+  null if the allocation failed.  If n_elements is zero and "chunks"
+  is null, it returns a chunk representing an array with zero elements
+  (which should be freed if not wanted).
+
+  Each element must be individually freed when it is no longer
+  needed. If you'd like to instead be able to free all at once, you
+  should instead use regular calloc and assign pointers into this
+  space to represent elements.  (In this case though, you cannot
+  independently free elements.)
+
+  independent_calloc simplifies and speeds up implementations of many
+  kinds of pools.  It may also be useful when constructing large data
+  structures that initially have a fixed number of fixed-sized nodes,
+  but the number is not known at compile time, and some of the nodes
+  may later need to be freed. For example:
+
+  struct Node { int item; struct Node* next; };
+
+  struct Node* build_list() {
+    struct Node** pool;
+    int n = read_number_of_nodes_needed();
+    if (n <= 0) return 0;
+    pool = (struct Node**)(independent_calloc(n, sizeof(struct Node), 0);
+    if (pool == 0) die();
+    // organize into a linked list...
+    struct Node* first = pool[0];
+    for (i = 0; i < n-1; ++i)
+      pool[i]->next = pool[i+1];
+    free(pool);     // Can now free the array (or not, if it is needed later)
+    return first;
+  }
+*/
+#if __STD_C
+Void_t** public_iCALLOc(size_t, size_t, Void_t**);
+#else
+Void_t** public_iCALLOc();
+#endif
+
+/*
+  independent_comalloc(size_t n_elements, size_t sizes[], Void_t* chunks[]);
+
+  independent_comalloc allocates, all at once, a set of n_elements
+  chunks with sizes indicated in the "sizes" array.    It returns
+  an array of pointers to these elements, each of which can be
+  independently freed, realloc'ed etc. The elements are guaranteed to
+  be adjacently allocated (this is not guaranteed to occur with
+  multiple callocs or mallocs), which may also improve cache locality
+  in some applications.
+
+  The "chunks" argument is optional (i.e., may be null). If it is null
+  the returned array is itself dynamically allocated and should also
+  be freed when it is no longer needed. Otherwise, the chunks array
+  must be of at least n_elements in length. It is filled in with the
+  pointers to the chunks.
+
+  In either case, independent_comalloc returns this pointer array, or
+  null if the allocation failed.  If n_elements is zero and chunks is
+  null, it returns a chunk representing an array with zero elements
+  (which should be freed if not wanted).
+
+  Each element must be individually freed when it is no longer
+  needed. If you'd like to instead be able to free all at once, you
+  should instead use a single regular malloc, and assign pointers at
+  particular offsets in the aggregate space. (In this case though, you
+  cannot independently free elements.)
+
+  independent_comallac differs from independent_calloc in that each
+  element may have a different size, and also that it does not
+  automatically clear elements.
+
+  independent_comalloc can be used to speed up allocation in cases
+  where several structs or objects must always be allocated at the
+  same time.  For example:
+
+  struct Head { ... }
+  struct Foot { ... }
+
+  void send_message(char* msg) {
+    int msglen = strlen(msg);
+    size_t sizes[3] = { sizeof(struct Head), msglen, sizeof(struct Foot) };
+    void* chunks[3];
+    if (independent_comalloc(3, sizes, chunks) == 0)
+      die();
+    struct Head* head = (struct Head*)(chunks[0]);
+    char*        body = (char*)(chunks[1]);
+    struct Foot* foot = (struct Foot*)(chunks[2]);
+    // ...
+  }
+
+  In general though, independent_comalloc is worth using only for
+  larger values of n_elements. For small values, you probably won't
+  detect enough difference from series of malloc calls to bother.
+
+  Overuse of independent_comalloc can increase overall memory usage,
+  since it cannot reuse existing noncontiguous small chunks that
+  might be available for some of the elements.
+*/
+#if __STD_C
+Void_t** public_iCOMALLOc(size_t, size_t*, Void_t**);
+#else
+Void_t** public_iCOMALLOc();
+#endif
+
+
+/*
+  pvalloc(size_t n);
+  Equivalent to valloc(minimum-page-that-holds(n)), that is,
+  round up n to nearest pagesize.
+ */
+#if __STD_C
+Void_t*  public_pVALLOc(size_t);
+#else
+Void_t*  public_pVALLOc();
+#endif
+
+/*
+  cfree(Void_t* p);
+  Equivalent to free(p).
+
+  cfree is needed/defined on some systems that pair it with calloc,
+  for odd historical reasons (such as: cfree is used in example
+  code in the first edition of K&R).
+*/
+#if __STD_C
+void     public_cFREe(Void_t*);
+#else
+void     public_cFREe();
+#endif
+
+/*
+  malloc_trim(size_t pad);
+
+  If possible, gives memory back to the system (via negative
+  arguments to sbrk) if there is unused memory at the `high' end of
+  the malloc pool. You can call this after freeing large blocks of
+  memory to potentially reduce the system-level memory requirements
+  of a program. However, it cannot guarantee to reduce memory. Under
+  some allocation patterns, some large free blocks of memory will be
+  locked between two used chunks, so they cannot be given back to
+  the system.
+
+  The `pad' argument to malloc_trim represents the amount of free
+  trailing space to leave untrimmed. If this argument is zero,
+  only the minimum amount of memory to maintain internal data
+  structures will be left (one page or less). Non-zero arguments
+  can be supplied to maintain enough trailing space to service
+  future expected allocations without having to re-obtain memory
+  from the system.
+
+  Malloc_trim returns 1 if it actually released any memory, else 0.
+  On systems that do not support "negative sbrks", it will always
+  rreturn 0.
+*/
+#if __STD_C
+int      public_mTRIm(size_t);
+#else
+int      public_mTRIm();
+#endif
+
+/*
+  malloc_usable_size(Void_t* p);
+
+  Returns the number of bytes you can actually use in
+  an allocated chunk, which may be more than you requested (although
+  often not) due to alignment and minimum size constraints.
+  You can use this many bytes without worrying about
+  overwriting other allocated objects. This is not a particularly great
+  programming practice. malloc_usable_size can be more useful in
+  debugging and assertions, for example:
+
+  p = malloc(n);
+  assert(malloc_usable_size(p) >= 256);
+
+*/
+#if __STD_C
+size_t   public_mUSABLe(Void_t*);
+#else
+size_t   public_mUSABLe();
+#endif
+
+/*
+  malloc_stats();
+  Prints on stderr the amount of space obtained from the system (both
+  via sbrk and mmap), the maximum amount (which may be more than
+  current if malloc_trim and/or munmap got called), and the current
+  number of bytes allocated via malloc (or realloc, etc) but not yet
+  freed. Note that this is the number of bytes allocated, not the
+  number requested. It will be larger than the number requested
+  because of alignment and bookkeeping overhead. Because it includes
+  alignment wastage as being in use, this figure may be greater than
+  zero even when no user-level chunks are allocated.
+
+  The reported current and maximum system memory can be inaccurate if
+  a program makes other calls to system memory allocation functions
+  (normally sbrk) outside of malloc.
+
+  malloc_stats prints only the most commonly interesting statistics.
+  More information can be obtained by calling mallinfo.
+
+*/
+#if __STD_C
+void     public_mSTATs(void);
+#else
+void     public_mSTATs();
+#endif
+
+/*
+  malloc_get_state(void);
+
+  Returns the state of all malloc variables in an opaque data
+  structure.
+*/
+#if __STD_C
+Void_t*  public_gET_STATe(void);
+#else
+Void_t*  public_gET_STATe();
+#endif
+
+/*
+  malloc_set_state(Void_t* state);
+
+  Restore the state of all malloc variables from data obtained with
+  malloc_get_state().
+*/
+#if __STD_C
+int      public_sET_STATe(Void_t*);
+#else
+int      public_sET_STATe();
+#endif
+
+#ifdef _LIBC
+/*
+  posix_memalign(void **memptr, size_t alignment, size_t size);
+
+  POSIX wrapper like memalign(), checking for validity of size.
+*/
+int      __posix_memalign(void **, size_t, size_t);
+#endif
+
+/* mallopt tuning options */
+
+/*
+  M_MXFAST is the maximum request size used for "fastbins", special bins
+  that hold returned chunks without consolidating their spaces. This
+  enables future requests for chunks of the same size to be handled
+  very quickly, but can increase fragmentation, and thus increase the
+  overall memory footprint of a program.
+
+  This malloc manages fastbins very conservatively yet still
+  efficiently, so fragmentation is rarely a problem for values less
+  than or equal to the default.  The maximum supported value of MXFAST
+  is 80. You wouldn't want it any higher than this anyway.  Fastbins
+  are designed especially for use with many small structs, objects or
+  strings -- the default handles structs/objects/arrays with sizes up
+  to 8 4byte fields, or small strings representing words, tokens,
+  etc. Using fastbins for larger objects normally worsens
+  fragmentation without improving speed.
+
+  M_MXFAST is set in REQUEST size units. It is internally used in
+  chunksize units, which adds padding and alignment.  You can reduce
+  M_MXFAST to 0 to disable all use of fastbins.  This causes the malloc
+  algorithm to be a closer approximation of fifo-best-fit in all cases,
+  not just for larger requests, but will generally cause it to be
+  slower.
+*/
+
+
+/* M_MXFAST is a standard SVID/XPG tuning option, usually listed in malloc.h */
+#ifndef M_MXFAST
+#define M_MXFAST            1
+#endif
+
+#ifndef DEFAULT_MXFAST
+#define DEFAULT_MXFAST     64
+#endif
+
+
+/*
+  M_TRIM_THRESHOLD is the maximum amount of unused top-most memory
+  to keep before releasing via malloc_trim in free().
+
+  Automatic trimming is mainly useful in long-lived programs.
+  Because trimming via sbrk can be slow on some systems, and can
+  sometimes be wasteful (in cases where programs immediately
+  afterward allocate more large chunks) the value should be high
+  enough so that your overall system performance would improve by
+  releasing this much memory.
+
+  The trim threshold and the mmap control parameters (see below)
+  can be traded off with one another. Trimming and mmapping are
+  two different ways of releasing unused memory back to the
+  system. Between these two, it is often possible to keep
+  system-level demands of a long-lived program down to a bare
+  minimum. For example, in one test suite of sessions measuring
+  the XF86 X server on Linux, using a trim threshold of 128K and a
+  mmap threshold of 192K led to near-minimal long term resource
+  consumption.
+
+  If you are using this malloc in a long-lived program, it should
+  pay to experiment with these values.  As a rough guide, you
+  might set to a value close to the average size of a process
+  (program) running on your system.  Releasing this much memory
+  would allow such a process to run in memory.  Generally, it's
+  worth it to tune for trimming rather tham memory mapping when a
+  program undergoes phases where several large chunks are
+  allocated and released in ways that can reuse each other's
+  storage, perhaps mixed with phases where there are no such
+  chunks at all.  And in well-behaved long-lived programs,
+  controlling release of large blocks via trimming versus mapping
+  is usually faster.
+
+  However, in most programs, these parameters serve mainly as
+  protection against the system-level effects of carrying around
+  massive amounts of unneeded memory. Since frequent calls to
+  sbrk, mmap, and munmap otherwise degrade performance, the default
+  parameters are set to relatively high values that serve only as
+  safeguards.
+
+  The trim value It must be greater than page size to have any useful
+  effect.  To disable trimming completely, you can set to
+  (unsigned long)(-1)
+
+  Trim settings interact with fastbin (MXFAST) settings: Unless
+  TRIM_FASTBINS is defined, automatic trimming never takes place upon
+  freeing a chunk with size less than or equal to MXFAST. Trimming is
+  instead delayed until subsequent freeing of larger chunks. However,
+  you can still force an attempted trim by calling malloc_trim.
+
+  Also, trimming is not generally possible in cases where
+  the main arena is obtained via mmap.
+
+  Note that the trick some people use of mallocing a huge space and
+  then freeing it at program startup, in an attempt to reserve system
+  memory, doesn't have the intended effect under automatic trimming,
+  since that memory will immediately be returned to the system.
+*/
+
+#define M_TRIM_THRESHOLD       -1
+
+#ifndef DEFAULT_TRIM_THRESHOLD
+#define DEFAULT_TRIM_THRESHOLD (128 * 1024)
+#endif
+
+/*
+  M_TOP_PAD is the amount of extra `padding' space to allocate or
+  retain whenever sbrk is called. It is used in two ways internally:
+
+  * When sbrk is called to extend the top of the arena to satisfy
+  a new malloc request, this much padding is added to the sbrk
+  request.
+
+  * When malloc_trim is called automatically from free(),
+  it is used as the `pad' argument.
+
+  In both cases, the actual amount of padding is rounded
+  so that the end of the arena is always a system page boundary.
+
+  The main reason for using padding is to avoid calling sbrk so
+  often. Having even a small pad greatly reduces the likelihood
+  that nearly every malloc request during program start-up (or
+  after trimming) will invoke sbrk, which needlessly wastes
+  time.
+
+  Automatic rounding-up to page-size units is normally sufficient
+  to avoid measurable overhead, so the default is 0.  However, in
+  systems where sbrk is relatively slow, it can pay to increase
+  this value, at the expense of carrying around more memory than
+  the program needs.
+*/
+
+#define M_TOP_PAD              -2
+
+#ifndef DEFAULT_TOP_PAD
+#define DEFAULT_TOP_PAD        (0)
+#endif
+
+/*
+  M_MMAP_THRESHOLD is the request size threshold for using mmap()
+  to service a request. Requests of at least this size that cannot
+  be allocated using already-existing space will be serviced via mmap.
+  (If enough normal freed space already exists it is used instead.)
+
+  Using mmap segregates relatively large chunks of memory so that
+  they can be individually obtained and released from the host
+  system. A request serviced through mmap is never reused by any
+  other request (at least not directly; the system may just so
+  happen to remap successive requests to the same locations).
+
+  Segregating space in this way has the benefits that:
+
+   1. Mmapped space can ALWAYS be individually released back
+      to the system, which helps keep the system level memory
+      demands of a long-lived program low.
+   2. Mapped memory can never become `locked' between
+      other chunks, as can happen with normally allocated chunks, which
+      means that even trimming via malloc_trim would not release them.
+   3. On some systems with "holes" in address spaces, mmap can obtain
+      memory that sbrk cannot.
+
+  However, it has the disadvantages that:
+
+   1. The space cannot be reclaimed, consolidated, and then
+      used to service later requests, as happens with normal chunks.
+   2. It can lead to more wastage because of mmap page alignment
+      requirements
+   3. It causes malloc performance to be more dependent on host
+      system memory management support routines which may vary in
+      implementation quality and may impose arbitrary
+      limitations. Generally, servicing a request via normal
+      malloc steps is faster than going through a system's mmap.
+
+  The advantages of mmap nearly always outweigh disadvantages for
+  "large" chunks, but the value of "large" varies across systems.  The
+  default is an empirically derived value that works well in most
+  systems.
+*/
+
+#define M_MMAP_THRESHOLD      -3
+
+#ifndef DEFAULT_MMAP_THRESHOLD
+#define DEFAULT_MMAP_THRESHOLD (128 * 1024)
+#endif
+
+/*
+  M_MMAP_MAX is the maximum number of requests to simultaneously
+  service using mmap. This parameter exists because
+  some systems have a limited number of internal tables for
+  use by mmap, and using more than a few of them may degrade
+  performance.
+
+  The default is set to a value that serves only as a safeguard.
+  Setting to 0 disables use of mmap for servicing large requests.  If
+  HAVE_MMAP is not set, the default value is 0, and attempts to set it
+  to non-zero values in mallopt will fail.
+*/
+
+#define M_MMAP_MAX             -4
+
+#ifndef DEFAULT_MMAP_MAX
+#if HAVE_MMAP
+#define DEFAULT_MMAP_MAX       (65536)
+#else
+#define DEFAULT_MMAP_MAX       (0)
+#endif
+#endif
+
+#ifdef __cplusplus
+};  /* end of extern "C" */
+#endif
+
+#include <cvmx-spinlock.h>
+#include "malloc.h"
+#include "thread-m.h"
+
+#ifdef DEBUG_PRINTS
+#define debug_printf    printf
+#else
+#define debug_printf(format, args...)  
+#endif
+
+#ifndef BOUNDED_N
+#define BOUNDED_N(ptr, sz) (ptr)
+#endif
+#ifndef RETURN_ADDRESS
+#define RETURN_ADDRESS(X_) (NULL)
+#endif
+
+/* On some platforms we can compile internal, not exported functions better.
+   Let the environment provide a macro and define it to be empty if it
+   is not available.  */
+#ifndef internal_function
+# define internal_function
+#endif
+
+/* Forward declarations.  */
+struct malloc_chunk;
+typedef struct malloc_chunk* mchunkptr;
+
+/* Internal routines.  */
+
+#if __STD_C
+
+static Void_t*         _int_malloc(mstate, size_t);
+static void            _int_free(mstate, Void_t*);
+static Void_t*         _int_realloc(mstate, Void_t*, size_t);
+static Void_t*         _int_memalign(mstate, size_t, size_t);
+static Void_t*         _int_valloc(mstate, size_t);
+static Void_t*  _int_pvalloc(mstate, size_t);
+static Void_t*  cALLOc(cvmx_arena_list_t arena_list, size_t, size_t);
+static Void_t** _int_icalloc(mstate, size_t, size_t, Void_t**);
+static Void_t** _int_icomalloc(mstate, size_t, size_t*, Void_t**);
+static int      mTRIm(size_t);
+static size_t   mUSABLe(Void_t*);
+static void     mSTATs(void);
+static int      mALLOPt(int, int);
+static struct mallinfo mALLINFo(mstate);
+
+static Void_t* internal_function mem2mem_check(Void_t *p, size_t sz);
+static int internal_function top_check(void);
+static void internal_function munmap_chunk(mchunkptr p);
+#if HAVE_MREMAP
+static mchunkptr internal_function mremap_chunk(mchunkptr p, size_t new_size);
+#endif
+
+static Void_t*   malloc_check(size_t sz, const Void_t *caller);
+static void      free_check(Void_t* mem, const Void_t *caller);
+static Void_t*   realloc_check(Void_t* oldmem, size_t bytes,
+			       const Void_t *caller);
+static Void_t*   memalign_check(size_t alignment, size_t bytes,
+				const Void_t *caller);
+#ifndef NO_THREADS
+static Void_t*   malloc_starter(size_t sz, const Void_t *caller);
+static void      free_starter(Void_t* mem, const Void_t *caller);
+static Void_t*   malloc_atfork(size_t sz, const Void_t *caller);
+static void      free_atfork(Void_t* mem, const Void_t *caller);
+#endif
+
+#else
+
+Void_t*         _int_malloc();
+void            _int_free();
+Void_t*         _int_realloc();
+Void_t*         _int_memalign();
+Void_t*         _int_valloc();
+Void_t*         _int_pvalloc();
+/*static Void_t*  cALLOc();*/
+static Void_t** _int_icalloc();
+static Void_t** _int_icomalloc();
+static int      mTRIm();
+static size_t   mUSABLe();
+static void     mSTATs();
+static int      mALLOPt();
+static struct mallinfo mALLINFo();
+
+#endif
+
+
+
+
+/* ------------- Optional versions of memcopy ---------------- */
+
+
+#if USE_MEMCPY
+
+/*
+  Note: memcpy is ONLY invoked with non-overlapping regions,
+  so the (usually slower) memmove is not needed.
+*/
+
+#define MALLOC_COPY(dest, src, nbytes)  memcpy(dest, src, nbytes)
+#define MALLOC_ZERO(dest, nbytes)       memset(dest, 0,   nbytes)
+
+#else /* !USE_MEMCPY */
+
+/* Use Duff's device for good zeroing/copying performance. */
+
+#define MALLOC_ZERO(charp, nbytes)                                            \
+do {                                                                          \
+  INTERNAL_SIZE_T* mzp = (INTERNAL_SIZE_T*)(charp);                           \
+  unsigned long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T);                     \
+  long mcn;                                                                   \
+  if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; }             \
+  switch (mctmp) {                                                            \
+    case 0: for(;;) { *mzp++ = 0;                                             \
+    case 7:           *mzp++ = 0;                                             \
+    case 6:           *mzp++ = 0;                                             \
+    case 5:           *mzp++ = 0;                                             \
+    case 4:           *mzp++ = 0;                                             \
+    case 3:           *mzp++ = 0;                                             \
+    case 2:           *mzp++ = 0;                                             \
+    case 1:           *mzp++ = 0; if(mcn <= 0) break; mcn--; }                \
+  }                                                                           \
+} while(0)
+
+#define MALLOC_COPY(dest,src,nbytes)                                          \
+do {                                                                          \
+  INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) src;                            \
+  INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) dest;                           \
+  unsigned long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T);                     \
+  long mcn;                                                                   \
+  if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; }             \
+  switch (mctmp) {                                                            \
+    case 0: for(;;) { *mcdst++ = *mcsrc++;                                    \
+    case 7:           *mcdst++ = *mcsrc++;                                    \
+    case 6:           *mcdst++ = *mcsrc++;                                    \
+    case 5:           *mcdst++ = *mcsrc++;                                    \
+    case 4:           *mcdst++ = *mcsrc++;                                    \
+    case 3:           *mcdst++ = *mcsrc++;                                    \
+    case 2:           *mcdst++ = *mcsrc++;                                    \
+    case 1:           *mcdst++ = *mcsrc++; if(mcn <= 0) break; mcn--; }       \
+  }                                                                           \
+} while(0)
+
+#endif
+
+/* ------------------ MMAP support ------------------  */
+
+
+#if HAVE_MMAP
+
+#include <fcntl.h>
+#ifndef LACKS_SYS_MMAN_H
+#include <sys/mman.h>
+#endif
+
+#if !defined(MAP_ANONYMOUS) && defined(MAP_ANON)
+# define MAP_ANONYMOUS MAP_ANON
+#endif
+#if !defined(MAP_FAILED)
+# define MAP_FAILED ((char*)-1)
+#endif
+
+#ifndef MAP_NORESERVE
+# ifdef MAP_AUTORESRV
+#  define MAP_NORESERVE MAP_AUTORESRV
+# else
+#  define MAP_NORESERVE 0
+# endif
+#endif
+
+/*
+   Nearly all versions of mmap support MAP_ANONYMOUS,
+   so the following is unlikely to be needed, but is
+   supplied just in case.
+*/
+
+#ifndef MAP_ANONYMOUS
+
+static int dev_zero_fd = -1; /* Cached file descriptor for /dev/zero. */
+
+#define MMAP(addr, size, prot, flags) ((dev_zero_fd < 0) ? \
+ (dev_zero_fd = open("/dev/zero", O_RDWR), \
+  mmap((addr), (size), (prot), (flags), dev_zero_fd, 0)) : \
+   mmap((addr), (size), (prot), (flags), dev_zero_fd, 0))
+
+#else
+
+#define MMAP(addr, size, prot, flags) \
+ (mmap((addr), (size), (prot), (flags)|MAP_ANONYMOUS, -1, 0))
+
+#endif
+
+
+#endif /* HAVE_MMAP */
+
+
+/*
+  -----------------------  Chunk representations -----------------------
+*/
+
+
+/*
+  This struct declaration is misleading (but accurate and necessary).
+  It declares a "view" into memory allowing access to necessary
+  fields at known offsets from a given base. See explanation below.
+*/
+struct malloc_chunk {
+
+  INTERNAL_SIZE_T      prev_size;  /* Size of previous chunk (if free).  */
+  INTERNAL_SIZE_T      size;       /* Size in bytes, including overhead. */
+  mstate               arena_ptr;  /* ptr to arena chunk belongs to */
+
+  struct malloc_chunk* fd;         /* double links -- used only if free. */
+  struct malloc_chunk* bk;
+};
+
+
+/*
+   malloc_chunk details:
+
+    (The following includes lightly edited explanations by Colin Plumb.)
+
+    Chunks of memory are maintained using a `boundary tag' method as
+    described in e.g., Knuth or Standish.  (See the paper by Paul
+    Wilson ftp://ftp.cs.utexas.edu/pub/garbage/allocsrv.ps for a
+    survey of such techniques.)  Sizes of free chunks are stored both
+    in the front of each chunk and at the end.  This makes
+    consolidating fragmented chunks into bigger chunks very fast.  The
+    size fields also hold bits representing whether chunks are free or
+    in use.
+
+    An allocated chunk looks like this:
+
+
+    chunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+            |             Size of previous chunk, if allocated            | |
+            +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+            |             Size of chunk, in bytes                         |P|
+      mem-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+            |             User data starts here...                          .
+            .                                                               .
+            .             (malloc_usable_space() bytes)                     .
+            .                                                               |
+nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+            |             Size of chunk                                     |
+            +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+
+
+    Where "chunk" is the front of the chunk for the purpose of most of
+    the malloc code, but "mem" is the pointer that is returned to the
+    user.  "Nextchunk" is the beginning of the next contiguous chunk.
+
+    Chunks always begin on even word boundries, so the mem portion
+    (which is returned to the user) is also on an even word boundary, and
+    thus at least double-word aligned.
+
+    Free chunks are stored in circular doubly-linked lists, and look like this:
+
+    chunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+            |             Size of previous chunk                            |
+            +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+    `head:' |             Size of chunk, in bytes                         |P|
+      mem-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+            |             Forward pointer to next chunk in list             |
+            +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+            |             Back pointer to previous chunk in list            |
+            +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+            |             Unused space (may be 0 bytes long)                .
+            .                                                               .
+            .                                                               |
+nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+    `foot:' |             Size of chunk, in bytes                           |
+            +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+
+    The P (PREV_INUSE) bit, stored in the unused low-order bit of the
+    chunk size (which is always a multiple of two words), is an in-use
+    bit for the *previous* chunk.  If that bit is *clear*, then the
+    word before the current chunk size contains the previous chunk
+    size, and can be used to find the front of the previous chunk.
+    The very first chunk allocated always has this bit set,
+    preventing access to non-existent (or non-owned) memory. If
+    prev_inuse is set for any given chunk, then you CANNOT determine
+    the size of the previous chunk, and might even get a memory
+    addressing fault when trying to do so.
+
+    Note that the `foot' of the current chunk is actually represented
+    as the prev_size of the NEXT chunk. This makes it easier to
+    deal with alignments etc but can be very confusing when trying
+    to extend or adapt this code.
+
+    The two exceptions to all this are
+
+     1. The special chunk `top' doesn't bother using the
+        trailing size field since there is no next contiguous chunk
+        that would have to index off it. After initialization, `top'
+        is forced to always exist.  If it would become less than
+        MINSIZE bytes long, it is replenished.
+
+     2. Chunks allocated via mmap, which have the second-lowest-order
+        bit (IS_MMAPPED) set in their size fields.  Because they are
+        allocated one-by-one, each must contain its own trailing size field.
+
+*/
+
+/*
+  ---------- Size and alignment checks and conversions ----------
+*/
+
+/* conversion from malloc headers to user pointers, and back */
+/* Added size for pointer to make room for arena_ptr */
+#define chunk2mem(p)   ((Void_t*)((char*)(p) + 2*SIZE_SZ + sizeof(void *)))
+#define mem2chunk(mem) ((mchunkptr)((char*)(mem) - 2*SIZE_SZ - sizeof(void *)))
+
+/* The smallest possible chunk */
+#define MIN_CHUNK_SIZE        (sizeof(struct malloc_chunk))
+
+/* The smallest size we can malloc is an aligned minimal chunk */
+
+#define MINSIZE  \
+  (unsigned long)(((MIN_CHUNK_SIZE+MALLOC_ALIGN_MASK) & ~MALLOC_ALIGN_MASK))
+
+/* Check if m has acceptable alignment */
+
+#define aligned_OK(m)  (((unsigned long)((m)) & (MALLOC_ALIGN_MASK)) == 0)
+
+
+/*
+   Check if a request is so large that it would wrap around zero when
+   padded and aligned. To simplify some other code, the bound is made
+   low enough so that adding MINSIZE will also not wrap around zero.
+*/
+
+#define REQUEST_OUT_OF_RANGE(req)                                 \
+  ((unsigned long)(req) >=                                        \
+   (unsigned long)(INTERNAL_SIZE_T)(-2 * MINSIZE))
+
+/* pad request bytes into a usable size -- internal version */
+
+
+/* prev_size field of next chunk is overwritten with data
+** when in use.  NOTE - last SIZE_SZ of arena must be left
+** unused for last chunk to use
+*/
+/* Added sizeof(void *) to make room for arena_ptr */
+#define request2size(req)                                         \
+  (((req) + sizeof(void *) + SIZE_SZ + MALLOC_ALIGN_MASK < MINSIZE)  ?             \
+   MINSIZE :                                                      \
+   ((req) + sizeof(void *) + SIZE_SZ + MALLOC_ALIGN_MASK) & ~MALLOC_ALIGN_MASK)
+
+/*  Same, except also perform argument check */
+
+#define checked_request2size(req, sz)                             \
+  if (REQUEST_OUT_OF_RANGE(req)) {                                \
+    MALLOC_FAILURE_ACTION;                                        \
+    return 0;                                                     \
+  }                                                               \
+  (sz) = request2size(req);
+
+/*
+  --------------- Physical chunk operations ---------------
+*/
+
+
+/* size field is or'ed with PREV_INUSE when previous adjacent chunk in use */
+#define PREV_INUSE 0x1
+
+/* extract inuse bit of previous chunk */
+#define prev_inuse(p)       ((p)->size & PREV_INUSE)
+
+
+/* size field is or'ed with IS_MMAPPED if the chunk was obtained with mmap() */
+#define IS_MMAPPED 0x2
+
+/* check for mmap()'ed chunk */
+#define chunk_is_mmapped(p) ((p)->size & IS_MMAPPED)
+
+
+
+/*
+  Bits to mask off when extracting size
+
+  Note: IS_MMAPPED is intentionally not masked off from size field in
+  macros for which mmapped chunks should never be seen. This should
+  cause helpful core dumps to occur if it is tried by accident by
+  people extending or adapting this malloc.
+*/
+#define SIZE_BITS (PREV_INUSE|IS_MMAPPED)
+
+/* Get size, ignoring use bits */
+#define chunksize(p)         ((p)->size & ~(SIZE_BITS))
+
+
+/* Ptr to next physical malloc_chunk. */
+#define next_chunk(p) ((mchunkptr)( ((char*)(p)) + ((p)->size & ~SIZE_BITS) ))
+
+/* Ptr to previous physical malloc_chunk */
+#define prev_chunk(p) ((mchunkptr)( ((char*)(p)) - ((p)->prev_size) ))
+
+/* Treat space at ptr + offset as a chunk */
+#define chunk_at_offset(p, s)  ((mchunkptr)(((char*)(p)) + (s)))
+
+/* extract p's inuse bit */
+#define inuse(p)\
+((((mchunkptr)(((char*)(p))+((p)->size & ~SIZE_BITS)))->size) & PREV_INUSE)
+
+/* set/clear chunk as being inuse without otherwise disturbing */
+#define set_inuse(p)\
+((mchunkptr)(((char*)(p)) + ((p)->size & ~SIZE_BITS)))->size |= PREV_INUSE
+
+#define clear_inuse(p)\
+((mchunkptr)(((char*)(p)) + ((p)->size & ~SIZE_BITS)))->size &= ~(PREV_INUSE)
+
+
+/* check/set/clear inuse bits in known places */
+#define inuse_bit_at_offset(p, s)\
+ (((mchunkptr)(((char*)(p)) + (s)))->size & PREV_INUSE)
+
+#define set_inuse_bit_at_offset(p, s)\
+ (((mchunkptr)(((char*)(p)) + (s)))->size |= PREV_INUSE)
+
+#define clear_inuse_bit_at_offset(p, s)\
+ (((mchunkptr)(((char*)(p)) + (s)))->size &= ~(PREV_INUSE))
+
+
+/* Set size at head, without disturbing its use bit */
+#define set_head_size(p, s)  ((p)->size = (((p)->size & SIZE_BITS) | (s)))
+
+/* Set size/use field */
+#define set_head(p, s)       ((p)->size = (s))
+
+/* Set size at footer (only when chunk is not in use) */
+#define set_foot(p, s)       (((mchunkptr)((char*)(p) + (s)))->prev_size = (s))
+
+
+/*
+  -------------------- Internal data structures --------------------
+
+   All internal state is held in an instance of malloc_state defined
+   below. There are no other static variables, except in two optional
+   cases:
+   * If USE_MALLOC_LOCK is defined, the mALLOC_MUTEx declared above.
+   * If HAVE_MMAP is true, but mmap doesn't support
+     MAP_ANONYMOUS, a dummy file descriptor for mmap.
+
+   Beware of lots of tricks that minimize the total bookkeeping space
+   requirements. The result is a little over 1K bytes (for 4byte
+   pointers and size_t.)
+*/
+
+/*
+  Bins
+
+    An array of bin headers for free chunks. Each bin is doubly
+    linked.  The bins are approximately proportionally (log) spaced.
+    There are a lot of these bins (128). This may look excessive, but
+    works very well in practice.  Most bins hold sizes that are
+    unusual as malloc request sizes, but are more usual for fragments
+    and consolidated sets of chunks, which is what these bins hold, so
+    they can be found quickly.  All procedures maintain the invariant
+    that no consolidated chunk physically borders another one, so each
+    chunk in a list is known to be preceeded and followed by either
+    inuse chunks or the ends of memory.
+
+    Chunks in bins are kept in size order, with ties going to the
+    approximately least recently used chunk. Ordering isn't needed
+    for the small bins, which all contain the same-sized chunks, but
+    facilitates best-fit allocation for larger chunks. These lists
+    are just sequential. Keeping them in order almost never requires
+    enough traversal to warrant using fancier ordered data
+    structures.
+
+    Chunks of the same size are linked with the most
+    recently freed at the front, and allocations are taken from the
+    back.  This results in LRU (FIFO) allocation order, which tends
+    to give each chunk an equal opportunity to be consolidated with
+    adjacent freed chunks, resulting in larger free chunks and less
+    fragmentation.
+
+    To simplify use in double-linked lists, each bin header acts
+    as a malloc_chunk. This avoids special-casing for headers.
+    But to conserve space and improve locality, we allocate
+    only the fd/bk pointers of bins, and then use repositioning tricks
+    to treat these as the fields of a malloc_chunk*.
+*/
+
+typedef struct malloc_chunk* mbinptr;
+
+/* addressing -- note that bin_at(0) does not exist */
+#define bin_at(m, i) ((mbinptr)((char*)&((m)->bins[(i)<<1]) - (SIZE_SZ<<1)))
+
+/* analog of ++bin */
+#define next_bin(b)  ((mbinptr)((char*)(b) + (sizeof(mchunkptr)<<1)))
+
+/* Reminders about list directionality within bins */
+#define first(b)     ((b)->fd)
+#define last(b)      ((b)->bk)
+
+/* Take a chunk off a bin list */
+#define unlink(P, BK, FD) {                                            \
+  FD = P->fd;                                                          \
+  BK = P->bk;                                                          \
+  FD->bk = BK;                                                         \
+  BK->fd = FD;                                                         \
+}
+
+/*
+  Indexing
+
+    Bins for sizes < 512 bytes contain chunks of all the same size, spaced
+    8 bytes apart. Larger bins are approximately logarithmically spaced:
+
+    64 bins of size       8
+    32 bins of size      64
+    16 bins of size     512
+     8 bins of size    4096
+     4 bins of size   32768
+     2 bins of size  262144
+     1 bin  of size what's left
+
+    There is actually a little bit of slop in the numbers in bin_index
+    for the sake of speed. This makes no difference elsewhere.
+
+    The bins top out around 1MB because we expect to service large
+    requests via mmap.
+*/
+
+#define NBINS             128
+#define NSMALLBINS         64
+#define SMALLBIN_WIDTH      8
+#define MIN_LARGE_SIZE    512
+
+#define in_smallbin_range(sz)  \
+  ((unsigned long)(sz) < (unsigned long)MIN_LARGE_SIZE)
+
+#define smallbin_index(sz)     (((unsigned)(sz)) >> 3)
+
+#define largebin_index(sz)                                                   \
+(((((unsigned long)(sz)) >>  6) <= 32)?  56 + (((unsigned long)(sz)) >>  6): \
+ ((((unsigned long)(sz)) >>  9) <= 20)?  91 + (((unsigned long)(sz)) >>  9): \
+ ((((unsigned long)(sz)) >> 12) <= 10)? 110 + (((unsigned long)(sz)) >> 12): \
+ ((((unsigned long)(sz)) >> 15) <=  4)? 119 + (((unsigned long)(sz)) >> 15): \
+ ((((unsigned long)(sz)) >> 18) <=  2)? 124 + (((unsigned long)(sz)) >> 18): \
+                                        126)
+
+#define bin_index(sz) \
+ ((in_smallbin_range(sz)) ? smallbin_index(sz) : largebin_index(sz))
+
+/*
+  FIRST_SORTED_BIN_SIZE is the chunk size corresponding to the
+  first bin that is maintained in sorted order. This must
+  be the smallest size corresponding to a given bin.
+
+  Normally, this should be MIN_LARGE_SIZE. But you can weaken
+  best fit guarantees to sometimes speed up malloc by increasing value.
+  Doing this means that malloc may choose a chunk that is 
+  non-best-fitting by up to the width of the bin.
+
+  Some useful cutoff values:
+      512 - all bins sorted
+     2560 - leaves bins <=     64 bytes wide unsorted  
+    12288 - leaves bins <=    512 bytes wide unsorted
+    65536 - leaves bins <=   4096 bytes wide unsorted
+   262144 - leaves bins <=  32768 bytes wide unsorted
+       -1 - no bins sorted (not recommended!)
+*/
+
+#define FIRST_SORTED_BIN_SIZE MIN_LARGE_SIZE 
+/* #define FIRST_SORTED_BIN_SIZE 65536 */
+
+/*
+  Unsorted chunks
+
+    All remainders from chunk splits, as well as all returned chunks,
+    are first placed in the "unsorted" bin. They are then placed
+    in regular bins after malloc gives them ONE chance to be used before
+    binning. So, basically, the unsorted_chunks list acts as a queue,
+    with chunks being placed on it in free (and malloc_consolidate),
+    and taken off (to be either used or placed in bins) in malloc.
+
+    The NON_MAIN_ARENA flag is never set for unsorted chunks, so it
+    does not have to be taken into account in size comparisons.
+*/
+
+/* The otherwise unindexable 1-bin is used to hold unsorted chunks. */
+#define unsorted_chunks(M)          (bin_at(M, 1))
+
+/*
+  Top
+
+    The top-most available chunk (i.e., the one bordering the end of
+    available memory) is treated specially. It is never included in
+    any bin, is used only if no other chunk is available, and is
+    released back to the system if it is very large (see
+    M_TRIM_THRESHOLD).  Because top initially
+    points to its own bin with initial zero size, thus forcing
+    extension on the first malloc request, we avoid having any special
+    code in malloc to check whether it even exists yet. But we still
+    need to do so when getting memory from system, so we make
+    initial_top treat the bin as a legal but unusable chunk during the
+    interval between initialization and the first call to
+    sYSMALLOc. (This is somewhat delicate, since it relies on
+    the 2 preceding words to be zero during this interval as well.)
+*/
+
+/* Conveniently, the unsorted bin can be used as dummy top on first call */
+#define initial_top(M)              (unsorted_chunks(M))
+
+/*
+  Binmap
+
+    To help compensate for the large number of bins, a one-level index
+    structure is used for bin-by-bin searching.  `binmap' is a
+    bitvector recording whether bins are definitely empty so they can
+    be skipped over during during traversals.  The bits are NOT always
+    cleared as soon as bins are empty, but instead only
+    when they are noticed to be empty during traversal in malloc.
+*/
+
+/* Conservatively use 32 bits per map word, even if on 64bit system */
+#define BINMAPSHIFT      5
+#define BITSPERMAP       (1U << BINMAPSHIFT)
+#define BINMAPSIZE       (NBINS / BITSPERMAP)
+
+#define idx2block(i)     ((i) >> BINMAPSHIFT)
+#define idx2bit(i)       ((1U << ((i) & ((1U << BINMAPSHIFT)-1))))
+
+#define mark_bin(m,i)    ((m)->binmap[idx2block(i)] |=  idx2bit(i))
+#define unmark_bin(m,i)  ((m)->binmap[idx2block(i)] &= ~(idx2bit(i)))
+#define get_binmap(m,i)  ((m)->binmap[idx2block(i)] &   idx2bit(i))
+
+/*
+  Fastbins
+
+    An array of lists holding recently freed small chunks.  Fastbins
+    are not doubly linked.  It is faster to single-link them, and
+    since chunks are never removed from the middles of these lists,
+    double linking is not necessary. Also, unlike regular bins, they
+    are not even processed in FIFO order (they use faster LIFO) since
+    ordering doesn't much matter in the transient contexts in which
+    fastbins are normally used.
+
+    Chunks in fastbins keep their inuse bit set, so they cannot
+    be consolidated with other free chunks. malloc_consolidate
+    releases all chunks in fastbins and consolidates them with
+    other free chunks.
+*/
+
+typedef struct malloc_chunk* mfastbinptr;
+
+/* offset 2 to use otherwise unindexable first 2 bins */
+#define fastbin_index(sz)        ((int)((((unsigned int)(sz)) >> 3) - 2))
+
+/* The maximum fastbin request size we support */
+#define MAX_FAST_SIZE     80
+
+#define NFASTBINS  (fastbin_index(request2size(MAX_FAST_SIZE))+1)
+
+/*
+  FASTBIN_CONSOLIDATION_THRESHOLD is the size of a chunk in free()
+  that triggers automatic consolidation of possibly-surrounding
+  fastbin chunks. This is a heuristic, so the exact value should not
+  matter too much. It is defined at half the default trim threshold as a
+  compromise heuristic to only attempt consolidation if it is likely
+  to lead to trimming. However, it is not dynamically tunable, since
+  consolidation reduces fragmentation surrounding large chunks even
+  if trimming is not used.
+*/
+
+#define FASTBIN_CONSOLIDATION_THRESHOLD  (65536UL)
+
+/*
+  Since the lowest 2 bits in max_fast don't matter in size comparisons,
+  they are used as flags.
+*/
+
+/*
+  FASTCHUNKS_BIT held in max_fast indicates that there are probably
+  some fastbin chunks. It is set true on entering a chunk into any
+  fastbin, and cleared only in malloc_consolidate.
+
+  The truth value is inverted so that have_fastchunks will be true
+  upon startup (since statics are zero-filled), simplifying
+  initialization checks.
+*/
+
+#define FASTCHUNKS_BIT        (1U)
+
+#define have_fastchunks(M)     (((M)->max_fast &  FASTCHUNKS_BIT) == 0)
+#define clear_fastchunks(M)    ((M)->max_fast |=  FASTCHUNKS_BIT)
+#define set_fastchunks(M)      ((M)->max_fast &= ~FASTCHUNKS_BIT)
+
+/*
+  NONCONTIGUOUS_BIT indicates that MORECORE does not return contiguous
+  regions.  Otherwise, contiguity is exploited in merging together,
+  when possible, results from consecutive MORECORE calls.
+
+  The initial value comes from MORECORE_CONTIGUOUS, but is
+  changed dynamically if mmap is ever used as an sbrk substitute.
+*/
+
+#define NONCONTIGUOUS_BIT     (2U)
+
+#define contiguous(M)          (((M)->max_fast &  NONCONTIGUOUS_BIT) == 0)
+#define noncontiguous(M)       (((M)->max_fast &  NONCONTIGUOUS_BIT) != 0)
+#define set_noncontiguous(M)   ((M)->max_fast |=  NONCONTIGUOUS_BIT)
+#define set_contiguous(M)      ((M)->max_fast &= ~NONCONTIGUOUS_BIT)
+
+/*
+   Set value of max_fast.
+   Use impossibly small value if 0.
+   Precondition: there are no existing fastbin chunks.
+   Setting the value clears fastchunk bit but preserves noncontiguous bit.
+*/
+
+#define set_max_fast(M, s) \
+  (M)->max_fast = (((s) == 0)? SMALLBIN_WIDTH: request2size(s)) | \
+  FASTCHUNKS_BIT | \
+  ((M)->max_fast &  NONCONTIGUOUS_BIT)
+
+
+/*
+   ----------- Internal state representation and initialization -----------
+*/
+
+struct malloc_state {
+  /* Serialize access.  */
+  mutex_t mutex;
+
+  /* Statistics for locking.  Only used if THREAD_STATS is defined.  */
+  long stat_lock_direct, stat_lock_loop, stat_lock_wait;
+  long pad0_[1]; /* try to give the mutex its own cacheline */
+
+  /* The maximum chunk size to be eligible for fastbin */
+  INTERNAL_SIZE_T  max_fast;   /* low 2 bits used as flags */
+
+  /* Fastbins */
+  mfastbinptr      fastbins[NFASTBINS];
+
+  /* Base of the topmost chunk -- not otherwise kept in a bin */
+  mchunkptr        top;
+
+  /* The remainder from the most recent split of a small request */
+  mchunkptr        last_remainder;
+
+  /* Normal bins packed as described above */
+  mchunkptr        bins[NBINS * 2];
+
+  /* Bitmap of bins */
+  unsigned int     binmap[BINMAPSIZE];
+
+  /* Linked list */
+  struct malloc_state *next;
+
+  /* Memory allocated from the system in this arena.  */
+  INTERNAL_SIZE_T system_mem;
+  INTERNAL_SIZE_T max_system_mem;
+};
+
+struct malloc_par {
+  /* Tunable parameters */
+  unsigned long    trim_threshold;
+  INTERNAL_SIZE_T  top_pad;
+  INTERNAL_SIZE_T  mmap_threshold;
+
+  /* Memory map support */
+  int              n_mmaps;
+  int              n_mmaps_max;
+  int              max_n_mmaps;
+
+  /* Cache malloc_getpagesize */
+  unsigned int     pagesize;
+
+  /* Statistics */
+  INTERNAL_SIZE_T  mmapped_mem;
+  /*INTERNAL_SIZE_T  sbrked_mem;*/
+  /*INTERNAL_SIZE_T  max_sbrked_mem;*/
+  INTERNAL_SIZE_T  max_mmapped_mem;
+  INTERNAL_SIZE_T  max_total_mem; /* only kept for NO_THREADS */
+
+  /* First address handed out by MORECORE/sbrk.  */
+  char*            sbrk_base;
+};
+
+/* There are several instances of this struct ("arenas") in this
+   malloc.  If you are adapting this malloc in a way that does NOT use
+   a static or mmapped malloc_state, you MUST explicitly zero-fill it
+   before using. This malloc relies on the property that malloc_state
+   is initialized to all zeroes (as is true of C statics).  */
+
+
+
+/*
+  Initialize a malloc_state struct.
+
+  This is called only from within malloc_consolidate, which needs
+  be called in the same contexts anyway.  It is never called directly
+  outside of malloc_consolidate because some optimizing compilers try
+  to inline it at all call points, which turns out not to be an
+  optimization at all. (Inlining it in malloc_consolidate is fine though.)
+*/
+
+#if __STD_C
+static void malloc_init_state(mstate av)
+#else
+static void malloc_init_state(av) mstate av;
+#endif
+{
+  int     i;
+  mbinptr bin;
+
+  /* Establish circular links for normal bins */
+  for (i = 1; i < NBINS; ++i) {
+    bin = bin_at(av,i);
+    bin->fd = bin->bk = bin;
+  }
+
+  set_noncontiguous(av);
+
+  set_max_fast(av, DEFAULT_MXFAST);
+
+  av->top            = initial_top(av);
+}
+
+/*
+   Other internal utilities operating on mstates
+*/
+
+#if __STD_C
+static Void_t*  sYSMALLOc(INTERNAL_SIZE_T, mstate);
+static void     malloc_consolidate(mstate);
+//static Void_t** iALLOc(mstate, size_t, size_t*, int, Void_t**);
+#else
+static Void_t*  sYSMALLOc();
+static void     malloc_consolidate();
+static Void_t** iALLOc();
+#endif
+
+/* ------------------- Support for multiple arenas -------------------- */
+#include "arena.c"
+
+/*
+  Debugging support
+
+  These routines make a number of assertions about the states
+  of data structures that should be true at all times. If any
+  are not true, it's very likely that a user program has somehow
+  trashed memory. (It's also possible that there is a coding error
+  in malloc. In which case, please report it!)
+*/
+
+#if ! MALLOC_DEBUG
+
+#define check_chunk(A,P)
+#define check_free_chunk(A,P)
+#define check_inuse_chunk(A,P)
+#define check_remalloced_chunk(A,P,N)
+#define check_malloced_chunk(A,P,N)
+#define check_malloc_state(A)
+
+#else
+
+#define check_chunk(A,P)              do_check_chunk(A,P)
+#define check_free_chunk(A,P)         do_check_free_chunk(A,P)
+#define check_inuse_chunk(A,P)        do_check_inuse_chunk(A,P)
+#define check_remalloced_chunk(A,P,N) do_check_remalloced_chunk(A,P,N)
+#define check_malloced_chunk(A,P,N)   do_check_malloced_chunk(A,P,N)
+#define check_malloc_state(A)         do_check_malloc_state(A)
+
+/*
+  Properties of all chunks
+*/
+
+#if __STD_C
+static void do_check_chunk(mstate av, mchunkptr p)
+#else
+static void do_check_chunk(av, p) mstate av; mchunkptr p;
+#endif
+{
+  unsigned long sz = chunksize(p);
+  /* min and max possible addresses assuming contiguous allocation */
+  char* max_address = (char*)(av->top) + chunksize(av->top);
+  char* min_address = max_address - av->system_mem;
+
+  if (!chunk_is_mmapped(p)) {
+
+    /* Has legal address ... */
+    if (p != av->top) {
+      if (contiguous(av)) {
+        assert(((char*)p) >= min_address);
+        assert(((char*)p + sz) <= ((char*)(av->top)));
+      }
+    }
+    else {
+      /* top size is always at least MINSIZE */
+      assert((unsigned long)(sz) >= MINSIZE);
+      /* top predecessor always marked inuse */
+      assert(prev_inuse(p));
+    }
+
+  }
+  else {
+#if HAVE_MMAP
+    /* address is outside main heap  */
+    if (contiguous(av) && av->top != initial_top(av)) {
+      assert(((char*)p) < min_address || ((char*)p) > max_address);
+    }
+    /* chunk is page-aligned */
+    assert(((p->prev_size + sz) & (mp_.pagesize-1)) == 0);
+    /* mem is aligned */
+    assert(aligned_OK(chunk2mem(p)));
+#else
+    /* force an appropriate assert violation if debug set */
+    assert(!chunk_is_mmapped(p));
+#endif
+  }
+}
+
+/*
+  Properties of free chunks
+*/
+
+#if __STD_C
+static void do_check_free_chunk(mstate av, mchunkptr p)
+#else
+static void do_check_free_chunk(av, p) mstate av; mchunkptr p;
+#endif
+{
+  INTERNAL_SIZE_T sz = p->size & ~(PREV_INUSE);
+  mchunkptr next = chunk_at_offset(p, sz);
+
+  do_check_chunk(av, p);
+
+  /* Chunk must claim to be free ... */
+  assert(!inuse(p));
+  assert (!chunk_is_mmapped(p));
+
+  /* Unless a special marker, must have OK fields */
+  if ((unsigned long)(sz) >= MINSIZE)
+  {
+    assert((sz & MALLOC_ALIGN_MASK) == 0);
+    assert(aligned_OK(chunk2mem(p)));
+    /* ... matching footer field */
+    assert(next->prev_size == sz);
+    /* ... and is fully consolidated */
+    assert(prev_inuse(p));
+    assert (next == av->top || inuse(next));
+
+    /* ... and has minimally sane links */
+    assert(p->fd->bk == p);
+    assert(p->bk->fd == p);
+  }
+  else /* markers are always of size SIZE_SZ */
+    assert(sz == SIZE_SZ);
+}
+
+/*
+  Properties of inuse chunks
+*/
+
+#if __STD_C
+static void do_check_inuse_chunk(mstate av, mchunkptr p)
+#else
+static void do_check_inuse_chunk(av, p) mstate av; mchunkptr p;
+#endif
+{
+  mchunkptr next;
+
+  do_check_chunk(av, p);
+
+  assert(av == arena_for_chunk(p));
+  if (chunk_is_mmapped(p))
+    return; /* mmapped chunks have no next/prev */
+
+  /* Check whether it claims to be in use ... */
+  assert(inuse(p));
+
+  next = next_chunk(p);
+
+  /* ... and is surrounded by OK chunks.
+    Since more things can be checked with free chunks than inuse ones,
+    if an inuse chunk borders them and debug is on, it's worth doing them.
+  */
+  if (!prev_inuse(p))  {
+    /* Note that we cannot even look at prev unless it is not inuse */
+    mchunkptr prv = prev_chunk(p);
+    assert(next_chunk(prv) == p);
+    do_check_free_chunk(av, prv);
+  }
+
+  if (next == av->top) {
+    assert(prev_inuse(next));
+    assert(chunksize(next) >= MINSIZE);
+  }
+  else if (!inuse(next))
+    do_check_free_chunk(av, next);
+}
+
+/*
+  Properties of chunks recycled from fastbins
+*/
+
+#if __STD_C
+static void do_check_remalloced_chunk(mstate av, mchunkptr p, INTERNAL_SIZE_T s)
+#else
+static void do_check_remalloced_chunk(av, p, s)
+mstate av; mchunkptr p; INTERNAL_SIZE_T s;
+#endif
+{
+  INTERNAL_SIZE_T sz = p->size & ~(PREV_INUSE);
+
+  if (!chunk_is_mmapped(p)) {
+    assert(av == arena_for_chunk(p));
+  }
+
+  do_check_inuse_chunk(av, p);
+
+  /* Legal size ... */
+  assert((sz & MALLOC_ALIGN_MASK) == 0);
+  assert((unsigned long)(sz) >= MINSIZE);
+  /* ... and alignment */
+  assert(aligned_OK(chunk2mem(p)));
+  /* chunk is less than MINSIZE more than request */
+  assert((long)(sz) - (long)(s) >= 0);
+  assert((long)(sz) - (long)(s + MINSIZE) < 0);
+}
+
+/*
+  Properties of nonrecycled chunks at the point they are malloced
+*/
+
+#if __STD_C
+static void do_check_malloced_chunk(mstate av, mchunkptr p, INTERNAL_SIZE_T s)
+#else
+static void do_check_malloced_chunk(av, p, s)
+mstate av; mchunkptr p; INTERNAL_SIZE_T s;
+#endif
+{
+  /* same as recycled case ... */
+  do_check_remalloced_chunk(av, p, s);
+
+  /*
+    ... plus,  must obey implementation invariant that prev_inuse is
+    always true of any allocated chunk; i.e., that each allocated
+    chunk borders either a previously allocated and still in-use
+    chunk, or the base of its memory arena. This is ensured
+    by making all allocations from the the `lowest' part of any found
+    chunk.  This does not necessarily hold however for chunks
+    recycled via fastbins.
+  */
+
+  assert(prev_inuse(p));
+}
+
+
+/*
+  Properties of malloc_state.
+
+  This may be useful for debugging malloc, as well as detecting user
+  programmer errors that somehow write into malloc_state.
+
+  If you are extending or experimenting with this malloc, you can
+  probably figure out how to hack this routine to print out or
+  display chunk addresses, sizes, bins, and other instrumentation.
+*/
+
+static void do_check_malloc_state(mstate av)
+{
+  int i;
+  mchunkptr p;
+  mchunkptr q;
+  mbinptr b;
+  unsigned int binbit;
+  int empty;
+  unsigned int idx;
+  INTERNAL_SIZE_T size;
+  unsigned long total = 0;
+  int max_fast_bin;
+
+  /* internal size_t must be no wider than pointer type */
+  assert(sizeof(INTERNAL_SIZE_T) <= sizeof(char*));
+
+  /* alignment is a power of 2 */
+  assert((MALLOC_ALIGNMENT & (MALLOC_ALIGNMENT-1)) == 0);
+
+  /* cannot run remaining checks until fully initialized */
+  if (av->top == 0 || av->top == initial_top(av))
+    return;
+
+
+  /* properties of fastbins */
+
+  /* max_fast is in allowed range */
+  assert((av->max_fast & ~1) <= request2size(MAX_FAST_SIZE));
+
+  max_fast_bin = fastbin_index(av->max_fast);
+
+  for (i = 0; i < NFASTBINS; ++i) {
+    p = av->fastbins[i];
+
+    /* all bins past max_fast are empty */
+    if (i > max_fast_bin)
+      assert(p == 0);
+
+    while (p != 0) {
+      /* each chunk claims to be inuse */
+      do_check_inuse_chunk(av, p);
+      total += chunksize(p);
+      /* chunk belongs in this bin */
+      assert(fastbin_index(chunksize(p)) == i);
+      p = p->fd;
+    }
+  }
+
+  if (total != 0)
+    assert(have_fastchunks(av));
+  else if (!have_fastchunks(av))
+    assert(total == 0);
+
+  /* check normal bins */
+  for (i = 1; i < NBINS; ++i) {
+    b = bin_at(av,i);
+
+    /* binmap is accurate (except for bin 1 == unsorted_chunks) */
+    if (i >= 2) {
+      binbit = get_binmap(av,i);
+      empty = last(b) == b;
+      if (!binbit)
+        assert(empty);
+      else if (!empty)
+        assert(binbit);
+    }
+
+    for (p = last(b); p != b; p = p->bk) {
+      /* each chunk claims to be free */
+      do_check_free_chunk(av, p);
+      size = chunksize(p);
+      total += size;
+      if (i >= 2) {
+        /* chunk belongs in bin */
+        idx = bin_index(size);
+        assert(idx == (unsigned int)i);
+        /* lists are sorted */
+        if ((unsigned long) size >= (unsigned long)(FIRST_SORTED_BIN_SIZE)) {
+	  assert(p->bk == b ||
+		 (unsigned long)chunksize(p->bk) >=
+		 (unsigned long)chunksize(p));
+	}
+      }
+      /* chunk is followed by a legal chain of inuse chunks */
+      for (q = next_chunk(p);
+           (q != av->top && inuse(q) &&
+             (unsigned long)(chunksize(q)) >= MINSIZE);
+           q = next_chunk(q))
+        do_check_inuse_chunk(av, q);
+    }
+  }
+
+  /* top chunk is OK */
+  check_chunk(av, av->top);
+
+  /* sanity checks for statistics */
+
+
+  assert((unsigned long)(av->system_mem) <=
+         (unsigned long)(av->max_system_mem));
+
+
+}
+#endif
+
+
+
+/* ----------- Routines dealing with system allocation -------------- */
+
+/* No system allocation routines supported */
+
+
+/*------------------------ Public wrappers. --------------------------------*/
+
+
+
+#undef DEBUG_MALLOC
+Void_t*
+public_mALLOc(cvmx_arena_list_t arena_list, size_t bytes)
+{
+  mstate ar_ptr, orig_ar_ptr;
+  Void_t *victim = NULL;
+  static mstate debug_prev_ar;  // debug only!
+#ifdef DEBUG_MALLOC
+  int arena_cnt=0;
+#endif
+  
+  ar_ptr = arena_list;
+
+  if (!ar_ptr)
+  {
+     return(NULL);
+  }
+
+  if (debug_prev_ar != ar_ptr)
+  {
+      debug_printf("New arena: %p\n", ar_ptr);
+#ifdef CVMX_SPINLOCK_DEBUG
+      cvmx_dprintf("lock wait count for arena: %p is %ld\n", ar_ptr, ar_ptr->mutex.wait_cnt);
+#endif
+      debug_prev_ar = ar_ptr;
+  }
+  orig_ar_ptr = ar_ptr;
+
+  // try to get an arena without contention
+  do
+  {
+#ifdef DEBUG_MALLOC
+  arena_cnt++;
+#endif
+      if (!mutex_trylock(&ar_ptr->mutex))
+      {
+          // we locked it
+          victim = _int_malloc(ar_ptr, bytes);
+          (void)mutex_unlock(&ar_ptr->mutex);
+          if(victim)
+          {
+              break;
+          }
+      }
+      ar_ptr = ar_ptr->next;
+  } while (ar_ptr != orig_ar_ptr);
+
+  // we couldn't get the memory without contention, so try all
+  // arenas.  SLOW!
+  if (!victim)
+  {
+      ar_ptr = orig_ar_ptr;
+      do
+      {
+#ifdef DEBUG_MALLOC
+  arena_cnt++;
+#endif
+          mutex_lock(&ar_ptr->mutex);
+          victim = _int_malloc(ar_ptr, bytes);
+          (void)mutex_unlock(&ar_ptr->mutex);
+          if(victim)
+          {
+              break;
+          }
+          ar_ptr = ar_ptr->next;
+      } while (ar_ptr != orig_ar_ptr);
+  }
+
+
+  assert(!victim || chunk_is_mmapped(mem2chunk(victim)) ||
+	 ar_ptr == arena_for_chunk(mem2chunk(victim)));
+
+#ifdef DEBUG_MALLOC
+  if (!victim)
+  {
+     cvmx_dprintf("Malloc failed: size: %ld, arena_cnt: %d\n", bytes, arena_cnt);
+  }
+#endif
+
+  debug_printf("cvmx_malloc(%ld) = %p\n", bytes, victim);
+
+  // remember which arena we last used.....
+  tsd_setspecific(arena_key, (Void_t *)ar_ptr);
+  return victim;
+}
+
+
+
+void
+public_fREe(Void_t* mem)
+{
+  mstate ar_ptr;
+  mchunkptr p;                          /* chunk corresponding to mem */
+
+  debug_printf("cvmx_free(%p)\n", mem);
+
+
+  if (mem == 0)                              /* free(0) has no effect */
+    return;
+
+  p = mem2chunk(mem);
+
+
+  ar_ptr = arena_for_chunk(p);
+  assert(ar_ptr);
+#if THREAD_STATS
+  if(!mutex_trylock(&ar_ptr->mutex))
+    ++(ar_ptr->stat_lock_direct);
+  else {
+    (void)mutex_lock(&ar_ptr->mutex);
+    ++(ar_ptr->stat_lock_wait);
+  }
+#else
+  (void)mutex_lock(&ar_ptr->mutex);
+#endif
+  _int_free(ar_ptr, mem);
+  (void)mutex_unlock(&ar_ptr->mutex);
+}
+
+Void_t*
+public_rEALLOc(cvmx_arena_list_t arena_list, Void_t* oldmem, size_t bytes)
+{
+  mstate ar_ptr;
+  INTERNAL_SIZE_T    nb;      /* padded request size */
+
+  mchunkptr oldp;             /* chunk corresponding to oldmem */
+  INTERNAL_SIZE_T    oldsize; /* its size */
+
+  Void_t* newp;             /* chunk to return */
+
+
+#if REALLOC_ZERO_BYTES_FREES
+  if (bytes == 0 && oldmem != NULL) { public_fREe(oldmem); return 0; }
+#endif
+
+  /* realloc of null is supposed to be same as malloc */
+  if (oldmem == 0) return public_mALLOc(arena_list, bytes);
+
+  oldp    = mem2chunk(oldmem);
+  oldsize = chunksize(oldp);
+
+  checked_request2size(bytes, nb);
+
+
+  ar_ptr = arena_for_chunk(oldp);
+  (void)mutex_lock(&ar_ptr->mutex);
+
+
+  newp = _int_realloc(ar_ptr, oldmem, bytes);
+
+  (void)mutex_unlock(&ar_ptr->mutex);
+  assert(!newp || chunk_is_mmapped(mem2chunk(newp)) ||
+	 ar_ptr == arena_for_chunk(mem2chunk(newp)));
+  return newp;
+}
+
+#undef DEBUG_MEMALIGN
+Void_t*
+public_mEMALIGn(cvmx_arena_list_t arena_list, size_t alignment, size_t bytes)
+{
+  mstate ar_ptr, orig_ar_ptr;
+  Void_t *p = NULL;
+#ifdef DEBUG_MEMALIGN
+  int arena_cnt=0;
+#endif
+
+
+  /* If need less alignment than we give anyway, just relay to malloc */
+  if (alignment <= MALLOC_ALIGNMENT) return public_mALLOc(arena_list, bytes);
+
+  /* Otherwise, ensure that it is at least a minimum chunk size */
+  if (alignment <  MINSIZE) alignment = MINSIZE;
+
+
+  ar_ptr = arena_list;
+
+  if (!ar_ptr)
+  {
+     return(NULL);
+  }
+
+  orig_ar_ptr = ar_ptr;
+
+
+  // try to get an arena without contention
+  do
+  {
+
+#ifdef DEBUG_MEMALIGN
+   arena_cnt++;
+#endif
+      if (!mutex_trylock(&ar_ptr->mutex))
+      {
+          // we locked it
+          p = _int_memalign(ar_ptr, alignment, bytes);
+          (void)mutex_unlock(&ar_ptr->mutex);
+          if(p)
+          {
+              break;
+          }
+      }
+      ar_ptr = ar_ptr->next;
+  } while (ar_ptr != orig_ar_ptr);
+
+
+  // we couldn't get the memory without contention, so try all
+  // arenas.  SLOW!
+  if (!p)
+  {
+#ifdef DEBUG_MEMALIGN
+   arena_cnt++;
+#endif
+      ar_ptr = orig_ar_ptr;
+      do
+      {
+          mutex_lock(&ar_ptr->mutex);
+          p = _int_memalign(ar_ptr, alignment, bytes);
+          (void)mutex_unlock(&ar_ptr->mutex);
+          if(p)
+          {
+              break;
+          }
+          ar_ptr = ar_ptr->next;
+      } while (ar_ptr != orig_ar_ptr);
+  }
+
+
+  if (p)
+  {
+     assert(ar_ptr == arena_for_chunk(mem2chunk(p)));
+  }
+  else
+  {
+#ifdef DEBUG_MEMALIGN
+     cvmx_dprintf("Memalign failed: align: 0x%x, size: %ld, arena_cnt: %ld\n", alignment, bytes, arena_cnt);
+#endif
+  }
+
+  assert(!p || ar_ptr == arena_for_chunk(mem2chunk(p)));
+  return p;
+}
+
+
+
+Void_t*
+public_cALLOc(cvmx_arena_list_t arena_list, size_t n, size_t elem_size)
+{
+  mstate av;
+  mchunkptr oldtop, p;
+  INTERNAL_SIZE_T sz, csz, oldtopsize;
+  Void_t* mem;
+  unsigned long clearsize;
+  unsigned long nclears;
+  INTERNAL_SIZE_T* d;
+
+
+  /* FIXME: check for overflow on multiplication.  */
+  sz = n * elem_size;
+
+  mem = public_mALLOc(arena_list, sz);
+  if (mem)
+  {
+     memset(mem, 0, sz);
+  }
+
+  return mem;
+}
+
+
+#ifndef _LIBC
+
+void
+public_cFREe(Void_t* m)
+{
+  public_fREe(m);
+}
+
+#endif /* _LIBC */
+
+/*
+  ------------------------------ malloc ------------------------------
+*/
+
+static Void_t*
+_int_malloc(mstate av, size_t bytes)
+{
+  INTERNAL_SIZE_T nb;               /* normalized request size */
+  unsigned int    idx;              /* associated bin index */
+  mbinptr         bin;              /* associated bin */
+  mfastbinptr*    fb;               /* associated fastbin */
+
+  mchunkptr       victim;           /* inspected/selected chunk */
+  INTERNAL_SIZE_T size;             /* its size */
+  int             victim_index;     /* its bin index */
+
+  mchunkptr       remainder;        /* remainder from a split */
+  unsigned long   remainder_size;   /* its size */
+
+  unsigned int    block;            /* bit map traverser */
+  unsigned int    bit;              /* bit map traverser */
+  unsigned int    map;              /* current word of binmap */
+
+  mchunkptr       fwd;              /* misc temp for linking */
+  mchunkptr       bck;              /* misc temp for linking */
+
+  /*
+    Convert request size to internal form by adding SIZE_SZ bytes
+    overhead plus possibly more to obtain necessary alignment and/or
+    to obtain a size of at least MINSIZE, the smallest allocatable
+    size. Also, checked_request2size traps (returning 0) request sizes
+    that are so large that they wrap around zero when padded and
+    aligned.
+  */
+
+
+  checked_request2size(bytes, nb);
+
+  /*
+    If the size qualifies as a fastbin, first check corresponding bin.
+    This code is safe to execute even if av is not yet initialized, so we
+    can try it without checking, which saves some time on this fast path.
+  */
+
+  if ((unsigned long)(nb) <= (unsigned long)(av->max_fast)) {
+    fb = &(av->fastbins[(fastbin_index(nb))]);
+    if ( (victim = *fb) != 0) {
+      *fb = victim->fd;
+      check_remalloced_chunk(av, victim, nb);
+      set_arena_for_chunk(victim, av);
+      return chunk2mem(victim);
+    }
+  }
+
+  /*
+    If a small request, check regular bin.  Since these "smallbins"
+    hold one size each, no searching within bins is necessary.
+    (For a large request, we need to wait until unsorted chunks are
+    processed to find best fit. But for small ones, fits are exact
+    anyway, so we can check now, which is faster.)
+  */
+
+  if (in_smallbin_range(nb)) {
+    idx = smallbin_index(nb);
+    bin = bin_at(av,idx);
+
+    if ( (victim = last(bin)) != bin) {
+      if (victim == 0) /* initialization check */
+        malloc_consolidate(av);
+      else {
+        bck = victim->bk;
+        set_inuse_bit_at_offset(victim, nb);
+        bin->bk = bck;
+        bck->fd = bin;
+
+        set_arena_for_chunk(victim, av);
+        check_malloced_chunk(av, victim, nb);
+        return chunk2mem(victim);
+      }
+    }
+  }
+
+  /*
+     If this is a large request, consolidate fastbins before continuing.
+     While it might look excessive to kill all fastbins before
+     even seeing if there is space available, this avoids
+     fragmentation problems normally associated with fastbins.
+     Also, in practice, programs tend to have runs of either small or
+     large requests, but less often mixtures, so consolidation is not
+     invoked all that often in most programs. And the programs that
+     it is called frequently in otherwise tend to fragment.
+  */
+
+  else {
+    idx = largebin_index(nb);
+    if (have_fastchunks(av))
+      malloc_consolidate(av);
+  }
+
+  /*
+    Process recently freed or remaindered chunks, taking one only if
+    it is exact fit, or, if this a small request, the chunk is remainder from
+    the most recent non-exact fit.  Place other traversed chunks in
+    bins.  Note that this step is the only place in any routine where
+    chunks are placed in bins.
+
+    The outer loop here is needed because we might not realize until
+    near the end of malloc that we should have consolidated, so must
+    do so and retry. This happens at most once, and only when we would
+    otherwise need to expand memory to service a "small" request.
+  */
+
+  for(;;) {
+
+    while ( (victim = unsorted_chunks(av)->bk) != unsorted_chunks(av)) {
+      bck = victim->bk;
+      size = chunksize(victim);
+
+      /*
+         If a small request, try to use last remainder if it is the
+         only chunk in unsorted bin.  This helps promote locality for
+         runs of consecutive small requests. This is the only
+         exception to best-fit, and applies only when there is
+         no exact fit for a small chunk.
+      */
+
+      if (in_smallbin_range(nb) &&
+          bck == unsorted_chunks(av) &&
+          victim == av->last_remainder &&
+          (unsigned long)(size) > (unsigned long)(nb + MINSIZE)) {
+
+        /* split and reattach remainder */
+        remainder_size = size - nb;
+        remainder = chunk_at_offset(victim, nb);
+        unsorted_chunks(av)->bk = unsorted_chunks(av)->fd = remainder;
+        av->last_remainder = remainder;
+        remainder->bk = remainder->fd = unsorted_chunks(av);
+
+        set_head(victim, nb | PREV_INUSE);
+        set_head(remainder, remainder_size | PREV_INUSE);
+        set_foot(remainder, remainder_size);
+
+        set_arena_for_chunk(victim, av);
+        check_malloced_chunk(av, victim, nb);
+        return chunk2mem(victim);
+      }
+
+      /* remove from unsorted list */
+      unsorted_chunks(av)->bk = bck;
+      bck->fd = unsorted_chunks(av);
+
+      /* Take now instead of binning if exact fit */
+
+      if (size == nb) {
+        set_inuse_bit_at_offset(victim, size);
+        set_arena_for_chunk(victim, av);
+        check_malloced_chunk(av, victim, nb);
+        return chunk2mem(victim);
+      }
+
+      /* place chunk in bin */
+
+      if (in_smallbin_range(size)) {
+        victim_index = smallbin_index(size);
+        bck = bin_at(av, victim_index);
+        fwd = bck->fd;
+      }
+      else {
+        victim_index = largebin_index(size);
+        bck = bin_at(av, victim_index);
+        fwd = bck->fd;
+
+        if (fwd != bck) {
+          /* if smaller than smallest, place first */
+          if ((unsigned long)(size) < (unsigned long)(bck->bk->size)) {
+            fwd = bck;
+            bck = bck->bk;
+          }
+          else if ((unsigned long)(size) >= 
+                   (unsigned long)(FIRST_SORTED_BIN_SIZE)) {
+
+            /* maintain large bins in sorted order */
+            size |= PREV_INUSE; /* Or with inuse bit to speed comparisons */
+            while ((unsigned long)(size) < (unsigned long)(fwd->size)) {
+              fwd = fwd->fd;
+	    }
+            bck = fwd->bk;
+          }
+        }
+      }
+
+      mark_bin(av, victim_index);
+      victim->bk = bck;
+      victim->fd = fwd;
+      fwd->bk = victim;
+      bck->fd = victim;
+    }
+
+    /*
+      If a large request, scan through the chunks of current bin in
+      sorted order to find smallest that fits.  This is the only step
+      where an unbounded number of chunks might be scanned without doing
+      anything useful with them. However the lists tend to be short.
+    */
+
+    if (!in_smallbin_range(nb)) {
+      bin = bin_at(av, idx);
+
+      for (victim = last(bin); victim != bin; victim = victim->bk) {
+	size = chunksize(victim);
+
+	if ((unsigned long)(size) >= (unsigned long)(nb)) {
+	  remainder_size = size - nb;
+	  unlink(victim, bck, fwd);
+
+	  /* Exhaust */
+	  if (remainder_size < MINSIZE)  {
+	    set_inuse_bit_at_offset(victim, size);
+        set_arena_for_chunk(victim, av);
+	    check_malloced_chunk(av, victim, nb);
+	    return chunk2mem(victim);
+	  }
+	  /* Split */
+	  else {
+	    remainder = chunk_at_offset(victim, nb);
+	    unsorted_chunks(av)->bk = unsorted_chunks(av)->fd = remainder;
+	    remainder->bk = remainder->fd = unsorted_chunks(av);
+	    set_head(victim, nb | PREV_INUSE);
+	    set_head(remainder, remainder_size | PREV_INUSE);
+	    set_foot(remainder, remainder_size);
+        set_arena_for_chunk(victim, av);
+	    check_malloced_chunk(av, victim, nb);
+	    return chunk2mem(victim);
+	  }
+	}
+      }
+    }
+
+    /*
+      Search for a chunk by scanning bins, starting with next largest
+      bin. This search is strictly by best-fit; i.e., the smallest
+      (with ties going to approximately the least recently used) chunk
+      that fits is selected.
+
+      The bitmap avoids needing to check that most blocks are nonempty.
+      The particular case of skipping all bins during warm-up phases
+      when no chunks have been returned yet is faster than it might look.
+    */
+
+    ++idx;
+    bin = bin_at(av,idx);
+    block = idx2block(idx);
+    map = av->binmap[block];
+    bit = idx2bit(idx);
+
+    for (;;) {
+
+      /* Skip rest of block if there are no more set bits in this block.  */
+      if (bit > map || bit == 0) {
+        do {
+          if (++block >= BINMAPSIZE)  /* out of bins */
+            goto use_top;
+        } while ( (map = av->binmap[block]) == 0);
+
+        bin = bin_at(av, (block << BINMAPSHIFT));
+        bit = 1;
+      }
+
+      /* Advance to bin with set bit. There must be one. */
+      while ((bit & map) == 0) {
+        bin = next_bin(bin);
+        bit <<= 1;
+        assert(bit != 0);
+      }
+
+      /* Inspect the bin. It is likely to be non-empty */
+      victim = last(bin);
+
+      /*  If a false alarm (empty bin), clear the bit. */
+      if (victim == bin) {
+        av->binmap[block] = map &= ~bit; /* Write through */
+        bin = next_bin(bin);
+        bit <<= 1;
+      }
+
+      else {
+        size = chunksize(victim);
+
+        /*  We know the first chunk in this bin is big enough to use. */
+        assert((unsigned long)(size) >= (unsigned long)(nb));
+
+        remainder_size = size - nb;
+
+        /* unlink */
+        bck = victim->bk;
+        bin->bk = bck;
+        bck->fd = bin;
+
+        /* Exhaust */
+        if (remainder_size < MINSIZE) {
+          set_inuse_bit_at_offset(victim, size);
+          set_arena_for_chunk(victim, av);
+          check_malloced_chunk(av, victim, nb);
+          return chunk2mem(victim);
+        }
+
+        /* Split */
+        else {
+          remainder = chunk_at_offset(victim, nb);
+
+          unsorted_chunks(av)->bk = unsorted_chunks(av)->fd = remainder;
+          remainder->bk = remainder->fd = unsorted_chunks(av);
+          /* advertise as last remainder */
+          if (in_smallbin_range(nb))
+            av->last_remainder = remainder;
+
+          set_head(victim, nb | PREV_INUSE);
+          set_head(remainder, remainder_size | PREV_INUSE);
+          set_foot(remainder, remainder_size);
+          set_arena_for_chunk(victim, av);
+          check_malloced_chunk(av, victim, nb);
+          return chunk2mem(victim);
+        }
+      }
+    }
+
+  use_top:
+    /*
+      If large enough, split off the chunk bordering the end of memory
+      (held in av->top). Note that this is in accord with the best-fit
+      search rule.  In effect, av->top is treated as larger (and thus
+      less well fitting) than any other available chunk since it can
+      be extended to be as large as necessary (up to system
+      limitations).
+
+      We require that av->top always exists (i.e., has size >=
+      MINSIZE) after initialization, so if it would otherwise be
+      exhuasted by current request, it is replenished. (The main
+      reason for ensuring it exists is that we may need MINSIZE space
+      to put in fenceposts in sysmalloc.)
+    */
+
+    victim = av->top;
+    size = chunksize(victim);
+
+    if ((unsigned long)(size) >= (unsigned long)(nb + MINSIZE)) {
+      remainder_size = size - nb;
+      remainder = chunk_at_offset(victim, nb);
+      av->top = remainder;
+      set_head(victim, nb | PREV_INUSE);
+      set_head(remainder, remainder_size | PREV_INUSE);
+
+      set_arena_for_chunk(victim, av);
+      check_malloced_chunk(av, victim, nb);
+      return chunk2mem(victim);
+    }
+
+    /*
+      If there is space available in fastbins, consolidate and retry,
+      to possibly avoid expanding memory. This can occur only if nb is
+      in smallbin range so we didn't consolidate upon entry.
+    */
+
+    else if (have_fastchunks(av)) {
+      assert(in_smallbin_range(nb));
+      malloc_consolidate(av);
+      idx = smallbin_index(nb); /* restore original bin index */
+    }
+
+    /*
+       Otherwise, relay to handle system-dependent cases
+    */
+    else
+      return(NULL); // sysmalloc not supported
+  }
+}
+
+/*
+  ------------------------------ free ------------------------------
+*/
+
+static void
+_int_free(mstate av, Void_t* mem)
+{
+  mchunkptr       p;           /* chunk corresponding to mem */
+  INTERNAL_SIZE_T size;        /* its size */
+  mfastbinptr*    fb;          /* associated fastbin */
+  mchunkptr       nextchunk;   /* next contiguous chunk */
+  INTERNAL_SIZE_T nextsize;    /* its size */
+  int             nextinuse;   /* true if nextchunk is used */
+  INTERNAL_SIZE_T prevsize;    /* size of previous contiguous chunk */
+  mchunkptr       bck;         /* misc temp for linking */
+  mchunkptr       fwd;         /* misc temp for linking */
+
+
+  /* free(0) has no effect */
+  if (mem != 0) {
+    p = mem2chunk(mem);
+    size = chunksize(p);
+
+    check_inuse_chunk(av, p);
+
+    /*
+      If eligible, place chunk on a fastbin so it can be found
+      and used quickly in malloc.
+    */
+
+    if ((unsigned long)(size) <= (unsigned long)(av->max_fast)
+
+#if TRIM_FASTBINS
+        /*
+           If TRIM_FASTBINS set, don't place chunks
+           bordering top into fastbins
+        */
+        && (chunk_at_offset(p, size) != av->top)
+#endif
+        ) {
+
+      set_fastchunks(av);
+      fb = &(av->fastbins[fastbin_index(size)]);
+      p->fd = *fb;
+      *fb = p;
+    }
+
+    /*
+       Consolidate other non-mmapped chunks as they arrive.
+    */
+
+    else if (!chunk_is_mmapped(p)) {
+      nextchunk = chunk_at_offset(p, size);
+      nextsize = chunksize(nextchunk);
+      assert(nextsize > 0);
+
+      /* consolidate backward */
+      if (!prev_inuse(p)) {
+        prevsize = p->prev_size;
+        size += prevsize;
+        p = chunk_at_offset(p, -((long) prevsize));
+        unlink(p, bck, fwd);
+      }
+
+      if (nextchunk != av->top) {
+        /* get and clear inuse bit */
+        nextinuse = inuse_bit_at_offset(nextchunk, nextsize);
+
+        /* consolidate forward */
+        if (!nextinuse) {
+          unlink(nextchunk, bck, fwd);
+          size += nextsize;
+        } else
+	  clear_inuse_bit_at_offset(nextchunk, 0);
+
+        /*
+          Place the chunk in unsorted chunk list. Chunks are
+          not placed into regular bins until after they have
+          been given one chance to be used in malloc.
+        */
+
+        bck = unsorted_chunks(av);
+        fwd = bck->fd;
+        p->bk = bck;
+        p->fd = fwd;
+        bck->fd = p;
+        fwd->bk = p;
+
+        set_head(p, size | PREV_INUSE);
+        set_foot(p, size);
+
+        check_free_chunk(av, p);
+      }
+
+      /*
+         If the chunk borders the current high end of memory,
+         consolidate into top
+      */
+
+      else {
+        size += nextsize;
+        set_head(p, size | PREV_INUSE);
+        av->top = p;
+        check_chunk(av, p);
+      }
+
+      /*
+        If freeing a large space, consolidate possibly-surrounding
+        chunks. Then, if the total unused topmost memory exceeds trim
+        threshold, ask malloc_trim to reduce top.
+
+        Unless max_fast is 0, we don't know if there are fastbins
+        bordering top, so we cannot tell for sure whether threshold
+        has been reached unless fastbins are consolidated.  But we
+        don't want to consolidate on each free.  As a compromise,
+        consolidation is performed if FASTBIN_CONSOLIDATION_THRESHOLD
+        is reached.
+      */
+
+      if ((unsigned long)(size) >= FASTBIN_CONSOLIDATION_THRESHOLD) {
+        if (have_fastchunks(av))
+          malloc_consolidate(av);
+      }
+    }
+  }
+}
+
+/*
+  ------------------------- malloc_consolidate -------------------------
+
+  malloc_consolidate is a specialized version of free() that tears
+  down chunks held in fastbins.  Free itself cannot be used for this
+  purpose since, among other things, it might place chunks back onto
+  fastbins.  So, instead, we need to use a minor variant of the same
+  code.
+
+  Also, because this routine needs to be called the first time through
+  malloc anyway, it turns out to be the perfect place to trigger
+  initialization code.
+*/
+
+#if __STD_C
+static void malloc_consolidate(mstate av)
+#else
+static void malloc_consolidate(av) mstate av;
+#endif
+{
+  mfastbinptr*    fb;                 /* current fastbin being consolidated */
+  mfastbinptr*    maxfb;              /* last fastbin (for loop control) */
+  mchunkptr       p;                  /* current chunk being consolidated */
+  mchunkptr       nextp;              /* next chunk to consolidate */
+  mchunkptr       unsorted_bin;       /* bin header */
+  mchunkptr       first_unsorted;     /* chunk to link to */
+
+  /* These have same use as in free() */
+  mchunkptr       nextchunk;
+  INTERNAL_SIZE_T size;
+  INTERNAL_SIZE_T nextsize;
+  INTERNAL_SIZE_T prevsize;
+  int             nextinuse;
+  mchunkptr       bck;
+  mchunkptr       fwd;
+
+  /*
+    If max_fast is 0, we know that av hasn't
+    yet been initialized, in which case do so below
+  */
+
+  if (av->max_fast != 0) {
+    clear_fastchunks(av);
+
+    unsorted_bin = unsorted_chunks(av);
+
+    /*
+      Remove each chunk from fast bin and consolidate it, placing it
+      then in unsorted bin. Among other reasons for doing this,
+      placing in unsorted bin avoids needing to calculate actual bins
+      until malloc is sure that chunks aren't immediately going to be
+      reused anyway.
+    */
+
+    maxfb = &(av->fastbins[fastbin_index(av->max_fast)]);
+    fb = &(av->fastbins[0]);
+    do {
+      if ( (p = *fb) != 0) {
+        *fb = 0;
+
+        do {
+          check_inuse_chunk(av, p);
+          nextp = p->fd;
+
+          /* Slightly streamlined version of consolidation code in free() */
+          size = p->size & ~(PREV_INUSE);
+          nextchunk = chunk_at_offset(p, size);
+          nextsize = chunksize(nextchunk);
+
+          if (!prev_inuse(p)) {
+            prevsize = p->prev_size;
+            size += prevsize;
+            p = chunk_at_offset(p, -((long) prevsize));
+            unlink(p, bck, fwd);
+          }
+
+          if (nextchunk != av->top) {
+            nextinuse = inuse_bit_at_offset(nextchunk, nextsize);
+
+            if (!nextinuse) {
+              size += nextsize;
+              unlink(nextchunk, bck, fwd);
+            } else
+	      clear_inuse_bit_at_offset(nextchunk, 0);
+
+            first_unsorted = unsorted_bin->fd;
+            unsorted_bin->fd = p;
+            first_unsorted->bk = p;
+
+            set_head(p, size | PREV_INUSE);
+            p->bk = unsorted_bin;
+            p->fd = first_unsorted;
+            set_foot(p, size);
+          }
+
+          else {
+            size += nextsize;
+            set_head(p, size | PREV_INUSE);
+            av->top = p;
+          }
+
+        } while ( (p = nextp) != 0);
+
+      }
+    } while (fb++ != maxfb);
+  }
+  else {
+    malloc_init_state(av);
+    check_malloc_state(av);
+  }
+}
+
+/*
+  ------------------------------ realloc ------------------------------
+*/
+
+static Void_t*
+_int_realloc(mstate av, Void_t* oldmem, size_t bytes)
+{
+  INTERNAL_SIZE_T  nb;              /* padded request size */
+
+  mchunkptr        oldp;            /* chunk corresponding to oldmem */
+  INTERNAL_SIZE_T  oldsize;         /* its size */
+
+  mchunkptr        newp;            /* chunk to return */
+  INTERNAL_SIZE_T  newsize;         /* its size */
+  Void_t*          newmem;          /* corresponding user mem */
+
+  mchunkptr        next;            /* next contiguous chunk after oldp */
+
+  mchunkptr        remainder;       /* extra space at end of newp */
+  unsigned long    remainder_size;  /* its size */
+
+  mchunkptr        bck;             /* misc temp for linking */
+  mchunkptr        fwd;             /* misc temp for linking */
+
+  unsigned long    copysize;        /* bytes to copy */
+  unsigned int     ncopies;         /* INTERNAL_SIZE_T words to copy */
+  INTERNAL_SIZE_T* s;               /* copy source */
+  INTERNAL_SIZE_T* d;               /* copy destination */
+
+
+#if REALLOC_ZERO_BYTES_FREES
+  if (bytes == 0) {
+    _int_free(av, oldmem);
+    return 0;
+  }
+#endif
+
+  /* realloc of null is supposed to be same as malloc */
+  if (oldmem == 0) return _int_malloc(av, bytes);
+
+  checked_request2size(bytes, nb);
+
+  oldp    = mem2chunk(oldmem);
+  oldsize = chunksize(oldp);
+
+  check_inuse_chunk(av, oldp);
+
+  // force to act like not mmapped
+  if (1) {
+
+    if ((unsigned long)(oldsize) >= (unsigned long)(nb)) {
+      /* already big enough; split below */
+      newp = oldp;
+      newsize = oldsize;
+    }
+
+    else {
+      next = chunk_at_offset(oldp, oldsize);
+
+      /* Try to expand forward into top */
+      if (next == av->top &&
+          (unsigned long)(newsize = oldsize + chunksize(next)) >=
+          (unsigned long)(nb + MINSIZE)) {
+        set_head_size(oldp, nb );
+        av->top = chunk_at_offset(oldp, nb);
+        set_head(av->top, (newsize - nb) | PREV_INUSE);
+    	check_inuse_chunk(av, oldp);
+        set_arena_for_chunk(oldp, av);
+        return chunk2mem(oldp);
+      }
+
+      /* Try to expand forward into next chunk;  split off remainder below */
+      else if (next != av->top &&
+               !inuse(next) &&
+               (unsigned long)(newsize = oldsize + chunksize(next)) >=
+               (unsigned long)(nb)) {
+        newp = oldp;
+        unlink(next, bck, fwd);
+      }
+
+      /* allocate, copy, free */
+      else {
+        newmem = _int_malloc(av, nb - MALLOC_ALIGN_MASK);
+        if (newmem == 0)
+          return 0; /* propagate failure */
+
+        newp = mem2chunk(newmem);
+        newsize = chunksize(newp);
+
+        /*
+          Avoid copy if newp is next chunk after oldp.
+        */
+        if (newp == next) {
+          newsize += oldsize;
+          newp = oldp;
+        }
+        else {
+          /*
+            Unroll copy of <= 36 bytes (72 if 8byte sizes)
+            We know that contents have an odd number of
+            INTERNAL_SIZE_T-sized words; minimally 3.
+          */
+
+          copysize = oldsize - SIZE_SZ;
+          s = (INTERNAL_SIZE_T*)(oldmem);
+          d = (INTERNAL_SIZE_T*)(newmem);
+          ncopies = copysize / sizeof(INTERNAL_SIZE_T);
+          assert(ncopies >= 3);
+
+          if (ncopies > 9)
+            MALLOC_COPY(d, s, copysize);
+
+          else {
+            *(d+0) = *(s+0);
+            *(d+1) = *(s+1);
+            *(d+2) = *(s+2);
+            if (ncopies > 4) {
+              *(d+3) = *(s+3);
+              *(d+4) = *(s+4);
+              if (ncopies > 6) {
+                *(d+5) = *(s+5);
+                *(d+6) = *(s+6);
+                if (ncopies > 8) {
+                  *(d+7) = *(s+7);
+                  *(d+8) = *(s+8);
+                }
+              }
+            }
+          }
+
+          _int_free(av, oldmem);
+          set_arena_for_chunk(newp, av);
+          check_inuse_chunk(av, newp);
+          return chunk2mem(newp);
+        }
+      }
+    }
+
+    /* If possible, free extra space in old or extended chunk */
+
+    assert((unsigned long)(newsize) >= (unsigned long)(nb));
+
+    remainder_size = newsize - nb;
+
+    if (remainder_size < MINSIZE) { /* not enough extra to split off */
+      set_head_size(newp, newsize);
+      set_inuse_bit_at_offset(newp, newsize);
+    }
+    else { /* split remainder */
+      remainder = chunk_at_offset(newp, nb);
+      set_head_size(newp, nb );
+      set_head(remainder, remainder_size | PREV_INUSE );
+      /* Mark remainder as inuse so free() won't complain */
+      set_inuse_bit_at_offset(remainder, remainder_size);
+      set_arena_for_chunk(remainder, av);
+      _int_free(av, chunk2mem(remainder));
+    }
+
+    set_arena_for_chunk(newp, av);
+    check_inuse_chunk(av, newp);
+    return chunk2mem(newp);
+  }
+
+  /*
+    Handle mmap cases
+  */
+
+  else {
+    /* If !HAVE_MMAP, but chunk_is_mmapped, user must have overwritten mem */
+    check_malloc_state(av);
+    MALLOC_FAILURE_ACTION;
+    return 0;
+  }
+}
+
+/*
+  ------------------------------ memalign ------------------------------
+*/
+
+static Void_t*
+_int_memalign(mstate av, size_t alignment, size_t bytes)
+{
+  INTERNAL_SIZE_T nb;             /* padded  request size */
+  char*           m;              /* memory returned by malloc call */
+  mchunkptr       p;              /* corresponding chunk */
+  char*           brk;            /* alignment point within p */
+  mchunkptr       newp;           /* chunk to return */
+  INTERNAL_SIZE_T newsize;        /* its size */
+  INTERNAL_SIZE_T leadsize;       /* leading space before alignment point */
+  mchunkptr       remainder;      /* spare room at end to split off */
+  unsigned long   remainder_size; /* its size */
+  INTERNAL_SIZE_T size;
+
+  /* If need less alignment than we give anyway, just relay to malloc */
+
+  if (alignment <= MALLOC_ALIGNMENT) return _int_malloc(av, bytes);
+
+  /* Otherwise, ensure that it is at least a minimum chunk size */
+
+  if (alignment <  MINSIZE) alignment = MINSIZE;
+
+  /* Make sure alignment is power of 2 (in case MINSIZE is not).  */
+  if ((alignment & (alignment - 1)) != 0) {
+    size_t a = MALLOC_ALIGNMENT * 2;
+    while ((unsigned long)a < (unsigned long)alignment) a <<= 1;
+    alignment = a;
+  }
+
+  checked_request2size(bytes, nb);
+
+  /*
+    Strategy: find a spot within that chunk that meets the alignment
+    request, and then possibly free the leading and trailing space.
+  */
+
+
+  /* Call malloc with worst case padding to hit alignment. */
+
+  m  = (char*)(_int_malloc(av, nb + alignment + MINSIZE));
+
+  if (m == 0) return 0; /* propagate failure */
+
+  p = mem2chunk(m);
+
+  if ((((unsigned long)(m)) % alignment) != 0) { /* misaligned */
+
+    /*
+      Find an aligned spot inside chunk.  Since we need to give back
+      leading space in a chunk of at least MINSIZE, if the first
+      calculation places us at a spot with less than MINSIZE leader,
+      we can move to the next aligned spot -- we've allocated enough
+      total room so that this is always possible.
+    */
+
+    brk = (char*)mem2chunk(((unsigned long)(m + alignment - 1)) &
+                           -((signed long) alignment));
+    if ((unsigned long)(brk - (char*)(p)) < MINSIZE)
+      brk += alignment;
+
+    newp = (mchunkptr)brk;
+    leadsize = brk - (char*)(p);
+    newsize = chunksize(p) - leadsize;
+
+    /* For mmapped chunks, just adjust offset */
+    if (chunk_is_mmapped(p)) {
+      newp->prev_size = p->prev_size + leadsize;
+      set_head(newp, newsize|IS_MMAPPED);
+      set_arena_for_chunk(newp, av);
+      return chunk2mem(newp);
+    }
+
+    /* Otherwise, give back leader, use the rest */
+    set_head(newp, newsize | PREV_INUSE );
+    set_inuse_bit_at_offset(newp, newsize);
+    set_head_size(p, leadsize);
+    set_arena_for_chunk(p, av);
+    _int_free(av, chunk2mem(p));
+    p = newp;
+
+    assert (newsize >= nb &&
+            (((unsigned long)(chunk2mem(p))) % alignment) == 0);
+  }
+
+  /* Also give back spare room at the end */
+  if (!chunk_is_mmapped(p)) {
+    size = chunksize(p);
+    if ((unsigned long)(size) > (unsigned long)(nb + MINSIZE)) {
+      remainder_size = size - nb;
+      remainder = chunk_at_offset(p, nb);
+      set_head(remainder, remainder_size | PREV_INUSE );
+      set_head_size(p, nb);
+      set_arena_for_chunk(remainder, av);
+      _int_free(av, chunk2mem(remainder));
+    }
+  }
+
+  set_arena_for_chunk(p, av);
+  check_inuse_chunk(av, p);
+  return chunk2mem(p);
+}
+
+#if 1
+/*
+  ------------------------------ calloc ------------------------------
+*/
+
+#if __STD_C
+Void_t* cALLOc(cvmx_arena_list_t arena_list, size_t n_elements, size_t elem_size)
+#else
+Void_t* cALLOc(n_elements, elem_size) size_t n_elements; size_t elem_size;
+#endif
+{
+  mchunkptr p;
+  unsigned long clearsize;
+  unsigned long nclears;
+  INTERNAL_SIZE_T* d;
+
+  Void_t* mem = public_mALLOc(arena_list, n_elements * elem_size);
+
+  if (mem != 0) {
+    p = mem2chunk(mem);
+
+    {
+      /*
+        Unroll clear of <= 36 bytes (72 if 8byte sizes)
+        We know that contents have an odd number of
+        INTERNAL_SIZE_T-sized words; minimally 3.
+      */
+
+      d = (INTERNAL_SIZE_T*)mem;
+      clearsize = chunksize(p) - SIZE_SZ;
+      nclears = clearsize / sizeof(INTERNAL_SIZE_T);
+      assert(nclears >= 3);
+
+      if (nclears > 9)
+        MALLOC_ZERO(d, clearsize);
+
+      else {
+        *(d+0) = 0;
+        *(d+1) = 0;
+        *(d+2) = 0;
+        if (nclears > 4) {
+          *(d+3) = 0;
+          *(d+4) = 0;
+          if (nclears > 6) {
+            *(d+5) = 0;
+            *(d+6) = 0;
+            if (nclears > 8) {
+              *(d+7) = 0;
+              *(d+8) = 0;
+            }
+          }
+        }
+      }
+    }
+  }
+  return mem;
+}
+#endif
+
+
+/*
+  ------------------------- malloc_usable_size -------------------------
+*/
+
+#if __STD_C
+size_t mUSABLe(Void_t* mem)
+#else
+size_t mUSABLe(mem) Void_t* mem;
+#endif
+{
+  mchunkptr p;
+  if (mem != 0) {
+    p = mem2chunk(mem);
+    if (chunk_is_mmapped(p))
+      return chunksize(p) - 3*SIZE_SZ; /* updated size for adding arena_ptr */
+    else if (inuse(p))
+      return chunksize(p) - 2*SIZE_SZ; /* updated size for adding arena_ptr */
+  }
+  return 0;
+}
+
+/*
+  ------------------------------ mallinfo ------------------------------
+*/
+
+struct mallinfo mALLINFo(mstate av)
+{
+  struct mallinfo mi;
+  int i;
+  mbinptr b;
+  mchunkptr p;
+  INTERNAL_SIZE_T avail;
+  INTERNAL_SIZE_T fastavail;
+  int nblocks;
+  int nfastblocks;
+
+  /* Ensure initialization */
+  if (av->top == 0)  malloc_consolidate(av);
+
+  check_malloc_state(av);
+
+  /* Account for top */
+  avail = chunksize(av->top);
+  nblocks = 1;  /* top always exists */
+
+  /* traverse fastbins */
+  nfastblocks = 0;
+  fastavail = 0;
+
+  for (i = 0; i < NFASTBINS; ++i) {
+    for (p = av->fastbins[i]; p != 0; p = p->fd) {
+      ++nfastblocks;
+      fastavail += chunksize(p);
+    }
+  }
+
+  avail += fastavail;
+
+  /* traverse regular bins */
+  for (i = 1; i < NBINS; ++i) {
+    b = bin_at(av, i);
+    for (p = last(b); p != b; p = p->bk) {
+      ++nblocks;
+      avail += chunksize(p);
+    }
+  }
+
+  mi.smblks = nfastblocks;
+  mi.ordblks = nblocks;
+  mi.fordblks = avail;
+  mi.uordblks = av->system_mem - avail;
+  mi.arena = av->system_mem;
+  mi.fsmblks = fastavail;
+  mi.keepcost = chunksize(av->top);
+  return mi;
+}
+
+/*
+  ------------------------------ malloc_stats ------------------------------
+*/
+
+void mSTATs()
+{
+}
+
+
+/*
+  ------------------------------ mallopt ------------------------------
+*/
+
+#if 0
+#if __STD_C
+int mALLOPt(int param_number, int value)
+#else
+int mALLOPt(param_number, value) int param_number; int value;
+#endif
+{
+}
+#endif
+
+
+/*
+  -------------------- Alternative MORECORE functions --------------------
+*/
+
+
+/*
+  General Requirements for MORECORE.
+
+  The MORECORE function must have the following properties:
+
+  If MORECORE_CONTIGUOUS is false:
+
+    * MORECORE must allocate in multiples of pagesize. It will
+      only be called with arguments that are multiples of pagesize.
+
+    * MORECORE(0) must return an address that is at least
+      MALLOC_ALIGNMENT aligned. (Page-aligning always suffices.)
+
+  else (i.e. If MORECORE_CONTIGUOUS is true):
+
+    * Consecutive calls to MORECORE with positive arguments
+      return increasing addresses, indicating that space has been
+      contiguously extended.
+
+    * MORECORE need not allocate in multiples of pagesize.
+      Calls to MORECORE need not have args of multiples of pagesize.
+
+    * MORECORE need not page-align.
+
+  In either case:
+
+    * MORECORE may allocate more memory than requested. (Or even less,
+      but this will generally result in a malloc failure.)
+
+    * MORECORE must not allocate memory when given argument zero, but
+      instead return one past the end address of memory from previous
+      nonzero call. This malloc does NOT call MORECORE(0)
+      until at least one call with positive arguments is made, so
+      the initial value returned is not important.
+
+    * Even though consecutive calls to MORECORE need not return contiguous
+      addresses, it must be OK for malloc'ed chunks to span multiple
+      regions in those cases where they do happen to be contiguous.
+
+    * MORECORE need not handle negative arguments -- it may instead
+      just return MORECORE_FAILURE when given negative arguments.
+      Negative arguments are always multiples of pagesize. MORECORE
+      must not misinterpret negative args as large positive unsigned
+      args. You can suppress all such calls from even occurring by defining
+      MORECORE_CANNOT_TRIM,
+
+  There is some variation across systems about the type of the
+  argument to sbrk/MORECORE. If size_t is unsigned, then it cannot
+  actually be size_t, because sbrk supports negative args, so it is
+  normally the signed type of the same width as size_t (sometimes
+  declared as "intptr_t", and sometimes "ptrdiff_t").  It doesn't much
+  matter though. Internally, we use "long" as arguments, which should
+  work across all reasonable possibilities.
+
+  Additionally, if MORECORE ever returns failure for a positive
+  request, and HAVE_MMAP is true, then mmap is used as a noncontiguous
+  system allocator. This is a useful backup strategy for systems with
+  holes in address spaces -- in this case sbrk cannot contiguously
+  expand the heap, but mmap may be able to map noncontiguous space.
+
+  If you'd like mmap to ALWAYS be used, you can define MORECORE to be
+  a function that always returns MORECORE_FAILURE.
+
+  If you are using this malloc with something other than sbrk (or its
+  emulation) to supply memory regions, you probably want to set
+  MORECORE_CONTIGUOUS as false.  As an example, here is a custom
+  allocator kindly contributed for pre-OSX macOS.  It uses virtually
+  but not necessarily physically contiguous non-paged memory (locked
+  in, present and won't get swapped out).  You can use it by
+  uncommenting this section, adding some #includes, and setting up the
+  appropriate defines above:
+
+      #define MORECORE osMoreCore
+      #define MORECORE_CONTIGUOUS 0
+
+  There is also a shutdown routine that should somehow be called for
+  cleanup upon program exit.
+
+  #define MAX_POOL_ENTRIES 100
+  #define MINIMUM_MORECORE_SIZE  (64 * 1024)
+  static int next_os_pool;
+  void *our_os_pools[MAX_POOL_ENTRIES];
+
+  void *osMoreCore(int size)
+  {
+    void *ptr = 0;
+    static void *sbrk_top = 0;
+
+    if (size > 0)
+    {
+      if (size < MINIMUM_MORECORE_SIZE)
+         size = MINIMUM_MORECORE_SIZE;
+      if (CurrentExecutionLevel() == kTaskLevel)
+         ptr = PoolAllocateResident(size + RM_PAGE_SIZE, 0);
+      if (ptr == 0)
+      {
+        return (void *) MORECORE_FAILURE;
+      }
+      // save ptrs so they can be freed during cleanup
+      our_os_pools[next_os_pool] = ptr;
+      next_os_pool++;
+      ptr = (void *) ((((unsigned long) ptr) + RM_PAGE_MASK) & ~RM_PAGE_MASK);
+      sbrk_top = (char *) ptr + size;
+      return ptr;
+    }
+    else if (size < 0)
+    {
+      // we don't currently support shrink behavior
+      return (void *) MORECORE_FAILURE;
+    }
+    else
+    {
+      return sbrk_top;
+    }
+  }
+
+  // cleanup any allocated memory pools
+  // called as last thing before shutting down driver
+
+  void osCleanupMem(void)
+  {
+    void **ptr;
+
+    for (ptr = our_os_pools; ptr < &our_os_pools[MAX_POOL_ENTRIES]; ptr++)
+      if (*ptr)
+      {
+         PoolDeallocate(*ptr);
+         *ptr = 0;
+      }
+  }
+
+*/
+
+
+
+/* ------------------------------------------------------------
+History:
+
+[see ftp://g.oswego.edu/pub/misc/malloc.c for the history of dlmalloc]
+
+*/
diff --git a/sys/contrib/octeon-sdk/cvmx-malloc/malloc.h b/sys/contrib/octeon-sdk/cvmx-malloc/malloc.h
new file mode 100644
index 0000000..6d6f634
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-malloc/malloc.h
@@ -0,0 +1,213 @@
+/*
+Copyright (c) 2001 Wolfram Gloger
+Copyright (c) 2006 Cavium networks
+
+Permission to use, copy, modify, distribute, and sell this software
+and its documentation for any purpose is hereby granted without fee,
+provided that (i) the above copyright notices and this permission
+notice appear in all copies of the software and related documentation,
+and (ii) the name of Wolfram Gloger may not be used in any advertising
+or publicity relating to the software.
+
+THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND,
+EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY
+WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
+
+IN NO EVENT SHALL WOLFRAM GLOGER BE LIABLE FOR ANY SPECIAL,
+INCIDENTAL, INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY
+DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+WHETHER OR NOT ADVISED OF THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY
+OF LIABILITY, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+#ifndef _MALLOC_H
+#define _MALLOC_H 1
+
+#undef _LIBC
+#ifdef _LIBC
+#include <features.h>
+#endif
+
+/*
+  $Id: malloc.h 30481 2007-12-05 21:46:59Z rfranz $
+  `ptmalloc2', a malloc implementation for multiple threads without
+  lock contention, by Wolfram Gloger <wg@malloc.de>.
+
+  VERSION 2.7.0
+
+  This work is mainly derived from malloc-2.7.0 by Doug Lea
+  <dl@cs.oswego.edu>, which is available from:
+
+                 ftp://gee.cs.oswego.edu/pub/misc/malloc.c
+
+  This trimmed-down header file only provides function prototypes and
+  the exported data structures.  For more detailed function
+  descriptions and compile-time options, see the source file
+  `malloc.c'.
+*/
+
+#if 0
+# include <stddef.h>
+# define __malloc_ptr_t  void *
+# undef  size_t
+# define size_t          unsigned long
+# undef  ptrdiff_t
+# define ptrdiff_t       long
+#else
+# undef  Void_t
+# define Void_t       void
+# define __malloc_ptr_t  char *
+#endif
+
+#ifdef _LIBC
+/* Used by GNU libc internals. */
+# define __malloc_size_t size_t
+# define __malloc_ptrdiff_t ptrdiff_t
+#elif !defined __attribute_malloc__
+# define __attribute_malloc__
+#endif
+
+#ifdef __GNUC__
+
+/* GCC can always grok prototypes.  For C++ programs we add throw()
+   to help it optimize the function calls.  But this works only with
+   gcc 2.8.x and egcs.  */
+# if defined __cplusplus && (__GNUC__ >= 3 || __GNUC_MINOR__ >= 8)
+#  define __THROW	throw ()
+# else
+#  define __THROW
+# endif
+# define __MALLOC_P(args)	args __THROW
+/* This macro will be used for functions which might take C++ callback
+   functions.  */
+# define __MALLOC_PMT(args)	args
+
+#else	/* Not GCC.  */
+
+# define __THROW
+
+# if (defined __STDC__ && __STDC__) || defined __cplusplus
+
+#  define __MALLOC_P(args)	args
+#  define __MALLOC_PMT(args)	args
+
+# else	/* Not ANSI C or C++.  */
+
+#  define __MALLOC_P(args)	()	/* No prototypes.  */
+#  define __MALLOC_PMT(args)	()
+
+# endif	/* ANSI C or C++.  */
+
+#endif	/* GCC.  */
+
+#ifndef NULL
+# ifdef __cplusplus
+#  define NULL	0
+# else
+#  define NULL	((__malloc_ptr_t) 0)
+# endif
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Nonzero if the malloc is already initialized.  */
+#ifdef _LIBC
+/* In the GNU libc we rename the global variable
+   `__malloc_initialized' to `__libc_malloc_initialized'.  */
+# define __malloc_initialized __libc_malloc_initialized
+#endif
+extern int cvmx__malloc_initialized;
+
+
+/* SVID2/XPG mallinfo structure */
+
+struct mallinfo {
+  int arena;    /* non-mmapped space allocated from system */
+  int ordblks;  /* number of free chunks */
+  int smblks;   /* number of fastbin blocks */
+  int hblks;    /* number of mmapped regions */
+  int hblkhd;   /* space in mmapped regions */
+  int usmblks;  /* maximum total allocated space */
+  int fsmblks;  /* space available in freed fastbin blocks */
+  int uordblks; /* total allocated space */
+  int fordblks; /* total free space */
+  int keepcost; /* top-most, releasable (via malloc_trim) space */
+};
+
+/* Returns a copy of the updated current mallinfo. */
+extern struct mallinfo mallinfo __MALLOC_P ((void));
+
+/* SVID2/XPG mallopt options */
+#ifndef M_MXFAST
+# define M_MXFAST  1	/* maximum request size for "fastbins" */
+#endif
+#ifndef M_NLBLKS
+# define M_NLBLKS  2	/* UNUSED in this malloc */
+#endif
+#ifndef M_GRAIN
+# define M_GRAIN   3	/* UNUSED in this malloc */
+#endif
+#ifndef M_KEEP
+# define M_KEEP    4	/* UNUSED in this malloc */
+#endif
+
+/* mallopt options that actually do something */
+#define M_TRIM_THRESHOLD    -1
+#define M_TOP_PAD           -2
+#define M_MMAP_THRESHOLD    -3
+#define M_MMAP_MAX          -4
+#define M_CHECK_ACTION      -5
+
+/* General SVID/XPG interface to tunable parameters. */
+extern int mallopt __MALLOC_P ((int __param, int __val));
+
+/* Release all but __pad bytes of freed top-most memory back to the
+   system. Return 1 if successful, else 0. */
+extern int malloc_trim __MALLOC_P ((size_t __pad));
+
+/* Report the number of usable allocated bytes associated with allocated
+   chunk __ptr. */
+extern size_t malloc_usable_size __MALLOC_P ((__malloc_ptr_t __ptr));
+
+/* Prints brief summary statistics on stderr. */
+extern void malloc_stats __MALLOC_P ((void));
+
+/* Record the state of all malloc variables in an opaque data structure. */
+extern __malloc_ptr_t malloc_get_state __MALLOC_P ((void));
+
+/* Restore the state of all malloc variables from data obtained with
+   malloc_get_state(). */
+extern int malloc_set_state __MALLOC_P ((__malloc_ptr_t __ptr));
+
+/* Called once when malloc is initialized; redefining this variable in
+   the application provides the preferred way to set up the hook
+   pointers. */
+extern void (*cmvx__malloc_initialize_hook) __MALLOC_PMT ((void));
+/* Hooks for debugging and user-defined versions. */
+extern void (*cvmx__free_hook) __MALLOC_PMT ((__malloc_ptr_t __ptr,
+					__const __malloc_ptr_t));
+extern __malloc_ptr_t (*cvmx__malloc_hook) __MALLOC_PMT ((size_t __size,
+						    __const __malloc_ptr_t));
+extern __malloc_ptr_t (*cvmx__realloc_hook) __MALLOC_PMT ((__malloc_ptr_t __ptr,
+						     size_t __size,
+						     __const __malloc_ptr_t));
+extern __malloc_ptr_t (*cvmx__memalign_hook) __MALLOC_PMT ((size_t __alignment,
+						      size_t __size,
+						      __const __malloc_ptr_t));
+extern void (*__after_morecore_hook) __MALLOC_PMT ((void));
+
+/* Activate a standard set of debugging hooks. */
+extern void cvmx__malloc_check_init __MALLOC_P ((void));
+
+/* Internal routines, operating on "arenas".  */
+struct malloc_state;
+typedef struct malloc_state *mstate;
+#ifdef __cplusplus
+}; /* end of extern "C" */
+#endif
+
+
+#endif /* malloc.h */
diff --git a/sys/contrib/octeon-sdk/cvmx-malloc/thread-m.h b/sys/contrib/octeon-sdk/cvmx-malloc/thread-m.h
new file mode 100644
index 0000000..de9ba6c
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-malloc/thread-m.h
@@ -0,0 +1,73 @@
+/*
+Copyright (c) 2001 Wolfram Gloger
+Copyright (c) 2006 Cavium networks
+
+Permission to use, copy, modify, distribute, and sell this software
+and its documentation for any purpose is hereby granted without fee,
+provided that (i) the above copyright notices and this permission
+notice appear in all copies of the software and related documentation,
+and (ii) the name of Wolfram Gloger may not be used in any advertising
+or publicity relating to the software.
+
+THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND,
+EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY
+WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
+
+IN NO EVENT SHALL WOLFRAM GLOGER BE LIABLE FOR ANY SPECIAL,
+INCIDENTAL, INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY
+DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+WHETHER OR NOT ADVISED OF THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY
+OF LIABILITY, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+/* $Id: thread-m.h 30481 2007-12-05 21:46:59Z rfranz $
+   One out of _LIBC, USE_PTHREADS, USE_THR or USE_SPROC should be
+   defined, otherwise the token NO_THREADS and dummy implementations
+   of the macros will be defined.  */
+
+#ifndef _THREAD_M_H
+#define _THREAD_M_H
+
+#undef thread_atfork_static
+
+
+#undef NO_THREADS /* No threads, provide dummy macros */
+
+typedef int thread_id;
+
+/* The mutex functions used to do absolutely nothing, i.e. lock,
+   trylock and unlock would always just return 0.  However, even
+   without any concurrently active threads, a mutex can be used
+   legitimately as an `in use' flag.  To make the code that is
+   protected by a mutex async-signal safe, these macros would have to
+   be based on atomic test-and-set operations, for example. */
+#ifdef __OCTEON__
+typedef cvmx_spinlock_t mutex_t;
+#define MUTEX_INITIALIZER          CMVX_SPINLOCK_UNLOCKED_VAL
+#define mutex_init(m)              cvmx_spinlock_init(m)
+#define mutex_lock(m)              cvmx_spinlock_lock(m)
+#define mutex_trylock(m)           (cvmx_spinlock_trylock(m))
+#define mutex_unlock(m)            cvmx_spinlock_unlock(m)
+#else
+
+typedef int mutex_t;
+
+#define MUTEX_INITIALIZER          0
+#define mutex_init(m)              (*(m) = 0)
+#define mutex_lock(m)              ((*(m) = 1), 0)
+#define mutex_trylock(m)           (*(m) ? 1 : ((*(m) = 1), 0))
+#define mutex_unlock(m)            (*(m) = 0)
+#endif
+
+
+
+typedef void *tsd_key_t;
+#define tsd_key_create(key, destr) do {} while(0)
+#define tsd_setspecific(key, data) ((key) = (data))
+#define tsd_getspecific(key, vptr) (vptr = (key))
+
+#define thread_atfork(prepare, parent, child) do {} while(0)
+
+
+#endif /* !defined(_THREAD_M_H) */
diff --git a/sys/contrib/octeon-sdk/cvmx-mdio.h b/sys/contrib/octeon-sdk/cvmx-mdio.h
index 859f03e..28decbf 100644
--- a/sys/contrib/octeon-sdk/cvmx-mdio.h
+++ b/sys/contrib/octeon-sdk/cvmx-mdio.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * Interface to the SMI/MDIO hardware, including support for both IEEE 802.3
  * clause 22 and clause 45 operations.
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_MIO_H__
@@ -308,7 +308,7 @@ typedef union
 #define MDIO_CLAUSE_45_READ_INC 2
 #define MDIO_CLAUSE_45_READ     3
 
-/* MMD identifiers, mostly for accessing devices withing XENPAK modules. */
+/* MMD identifiers, mostly for accessing devices within XENPAK modules. */
 #define CVMX_MMD_DEVICE_PMA_PMD      1
 #define CVMX_MMD_DEVICE_WIS          2
 #define CVMX_MMD_DEVICE_PCS          3
@@ -382,7 +382,7 @@ static inline int cvmx_mdio_read(int bus_id, int phy_id, int location)
 	struct mii_bus *bus;
 	int rv;
 
-	BUG_ON(bus_id > 1 || bus_id < 0);
+	BUG_ON(bus_id > 3 || bus_id < 0);
 
 	bus = octeon_mdiobuses[bus_id];
 	if (bus == NULL)
@@ -434,7 +434,7 @@ static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val)
 	struct mii_bus *bus;
 	int rv;
 
-	BUG_ON(bus_id > 1 || bus_id < 0);
+	BUG_ON(bus_id > 3 || bus_id < 0);
 
 	bus = octeon_mdiobuses[bus_id];
 	if (bus == NULL)
diff --git a/sys/contrib/octeon-sdk/cvmx-mgmt-port.c b/sys/contrib/octeon-sdk/cvmx-mgmt-port.c
index 8bb064b..a5586bf 100644
--- a/sys/contrib/octeon-sdk/cvmx-mgmt-port.c
+++ b/sys/contrib/octeon-sdk/cvmx-mgmt-port.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Support functions for managing the MII management port
  *
- * <hr>$Revision: 49628 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #include "cvmx.h"
 #include "cvmx-bootmem.h"
@@ -114,9 +114,9 @@ CVMX_SHARED cvmx_mgmt_port_state_t *cvmx_mgmt_port_state_ptr = NULL;
  */
 static int __cvmx_mgmt_port_num_ports(void)
 {
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
         return 1;
-    else if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
+    else if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN6XXX))
         return 2;
     else
         return 0;
@@ -140,7 +140,7 @@ cvmx_mgmt_port_result_t cvmx_mgmt_port_initialize(int port)
     if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
         return CVMX_MGMT_PORT_INVALID_PARAM;
 
-    cvmx_mgmt_port_state_ptr = cvmx_bootmem_alloc_named(CVMX_MGMT_PORT_NUM_PORTS * sizeof(cvmx_mgmt_port_state_t), 128, alloc_name);
+    cvmx_mgmt_port_state_ptr = cvmx_bootmem_alloc_named_flags(CVMX_MGMT_PORT_NUM_PORTS * sizeof(cvmx_mgmt_port_state_t), 128, alloc_name, CVMX_BOOTMEM_FLAG_END_ALLOC);
     if (cvmx_mgmt_port_state_ptr)
     {
         memset(cvmx_mgmt_port_state_ptr, 0, CVMX_MGMT_PORT_NUM_PORTS * sizeof(cvmx_mgmt_port_state_t));
@@ -363,6 +363,7 @@ cvmx_mgmt_port_result_t cvmx_mgmt_port_initialize(int port)
 
             /* Enable the componsation controller */
             agl_prtx_ctl.s.comp = 1;
+            agl_prtx_ctl.s.drv_byp = 0;
             cvmx_write_csr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64);
             cvmx_read_csr(CVMX_AGL_PRTX_CTL(port));  /* Force write out before wait */
             cvmx_wait(1024 * clock_scale); // for componsation state to lock.
diff --git a/sys/contrib/octeon-sdk/cvmx-mgmt-port.h b/sys/contrib/octeon-sdk/cvmx-mgmt-port.h
index bd09ded..202c1dd 100644
--- a/sys/contrib/octeon-sdk/cvmx-mgmt-port.h
+++ b/sys/contrib/octeon-sdk/cvmx-mgmt-port.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Support functions for managing the MII management port
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_MGMT_PORT_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-mio-defs.h b/sys/contrib/octeon-sdk/cvmx-mio-defs.h
index bd006f6..9314eea 100644
--- a/sys/contrib/octeon-sdk/cvmx-mio-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-mio-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,15 +49,15 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_MIO_TYPEDEFS_H__
-#define __CVMX_MIO_TYPEDEFS_H__
+#ifndef __CVMX_MIO_DEFS_H__
+#define __CVMX_MIO_DEFS_H__
 
 #define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_MIO_BOOT_COMP CVMX_MIO_BOOT_COMP_FUNC()
 static inline uint64_t CVMX_MIO_BOOT_COMP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_BOOT_COMP not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800000000B8ull);
 }
@@ -70,7 +70,11 @@ static inline uint64_t CVMX_MIO_BOOT_DMA_CFGX(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_BOOT_DMA_CFGX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8;
 }
@@ -83,7 +87,11 @@ static inline uint64_t CVMX_MIO_BOOT_DMA_INTX(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_BOOT_DMA_INTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8;
 }
@@ -96,7 +104,11 @@ static inline uint64_t CVMX_MIO_BOOT_DMA_INT_ENX(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_BOOT_DMA_INT_ENX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8;
 }
@@ -109,7 +121,11 @@ static inline uint64_t CVMX_MIO_BOOT_DMA_TIMX(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_BOOT_DMA_TIMX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8;
 }
@@ -130,7 +146,11 @@ static inline uint64_t CVMX_MIO_BOOT_LOC_CFGX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_BOOT_LOC_CFGX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8;
 }
@@ -142,7 +162,7 @@ static inline uint64_t CVMX_MIO_BOOT_LOC_CFGX(unsigned long offset)
 #define CVMX_MIO_BOOT_PIN_DEFS CVMX_MIO_BOOT_PIN_DEFS_FUNC()
 static inline uint64_t CVMX_MIO_BOOT_PIN_DEFS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_BOOT_PIN_DEFS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800000000C0ull);
 }
@@ -160,7 +180,11 @@ static inline uint64_t CVMX_MIO_BOOT_REG_CFGX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_MIO_BOOT_REG_CFGX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8;
 }
@@ -178,7 +202,11 @@ static inline uint64_t CVMX_MIO_BOOT_REG_TIMX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_MIO_BOOT_REG_TIMX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8;
 }
@@ -187,6 +215,183 @@ static inline uint64_t CVMX_MIO_BOOT_REG_TIMX(unsigned long offset)
 #endif
 #define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_EMM_BUF_DAT CVMX_MIO_EMM_BUF_DAT_FUNC()
+static inline uint64_t CVMX_MIO_EMM_BUF_DAT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_EMM_BUF_DAT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800000020E8ull);
+}
+#else
+#define CVMX_MIO_EMM_BUF_DAT (CVMX_ADD_IO_SEG(0x00011800000020E8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_EMM_BUF_IDX CVMX_MIO_EMM_BUF_IDX_FUNC()
+static inline uint64_t CVMX_MIO_EMM_BUF_IDX_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_EMM_BUF_IDX not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800000020E0ull);
+}
+#else
+#define CVMX_MIO_EMM_BUF_IDX (CVMX_ADD_IO_SEG(0x00011800000020E0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_EMM_CFG CVMX_MIO_EMM_CFG_FUNC()
+static inline uint64_t CVMX_MIO_EMM_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_EMM_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000002000ull);
+}
+#else
+#define CVMX_MIO_EMM_CFG (CVMX_ADD_IO_SEG(0x0001180000002000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_EMM_CMD CVMX_MIO_EMM_CMD_FUNC()
+static inline uint64_t CVMX_MIO_EMM_CMD_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_EMM_CMD not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000002058ull);
+}
+#else
+#define CVMX_MIO_EMM_CMD (CVMX_ADD_IO_SEG(0x0001180000002058ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_EMM_DMA CVMX_MIO_EMM_DMA_FUNC()
+static inline uint64_t CVMX_MIO_EMM_DMA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_EMM_DMA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000002050ull);
+}
+#else
+#define CVMX_MIO_EMM_DMA (CVMX_ADD_IO_SEG(0x0001180000002050ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_EMM_INT CVMX_MIO_EMM_INT_FUNC()
+static inline uint64_t CVMX_MIO_EMM_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_EMM_INT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000002078ull);
+}
+#else
+#define CVMX_MIO_EMM_INT (CVMX_ADD_IO_SEG(0x0001180000002078ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_EMM_INT_EN CVMX_MIO_EMM_INT_EN_FUNC()
+static inline uint64_t CVMX_MIO_EMM_INT_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_EMM_INT_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000002080ull);
+}
+#else
+#define CVMX_MIO_EMM_INT_EN (CVMX_ADD_IO_SEG(0x0001180000002080ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_EMM_MODEX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_MIO_EMM_MODEX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_MIO_EMM_MODEX(offset) (CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_EMM_RCA CVMX_MIO_EMM_RCA_FUNC()
+static inline uint64_t CVMX_MIO_EMM_RCA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_EMM_RCA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800000020A0ull);
+}
+#else
+#define CVMX_MIO_EMM_RCA (CVMX_ADD_IO_SEG(0x00011800000020A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_EMM_RSP_HI CVMX_MIO_EMM_RSP_HI_FUNC()
+static inline uint64_t CVMX_MIO_EMM_RSP_HI_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_EMM_RSP_HI not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000002070ull);
+}
+#else
+#define CVMX_MIO_EMM_RSP_HI (CVMX_ADD_IO_SEG(0x0001180000002070ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_EMM_RSP_LO CVMX_MIO_EMM_RSP_LO_FUNC()
+static inline uint64_t CVMX_MIO_EMM_RSP_LO_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_EMM_RSP_LO not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000002068ull);
+}
+#else
+#define CVMX_MIO_EMM_RSP_LO (CVMX_ADD_IO_SEG(0x0001180000002068ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_EMM_RSP_STS CVMX_MIO_EMM_RSP_STS_FUNC()
+static inline uint64_t CVMX_MIO_EMM_RSP_STS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_EMM_RSP_STS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000002060ull);
+}
+#else
+#define CVMX_MIO_EMM_RSP_STS (CVMX_ADD_IO_SEG(0x0001180000002060ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_EMM_SAMPLE CVMX_MIO_EMM_SAMPLE_FUNC()
+static inline uint64_t CVMX_MIO_EMM_SAMPLE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_EMM_SAMPLE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000002090ull);
+}
+#else
+#define CVMX_MIO_EMM_SAMPLE (CVMX_ADD_IO_SEG(0x0001180000002090ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_EMM_STS_MASK CVMX_MIO_EMM_STS_MASK_FUNC()
+static inline uint64_t CVMX_MIO_EMM_STS_MASK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_EMM_STS_MASK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000002098ull);
+}
+#else
+#define CVMX_MIO_EMM_STS_MASK (CVMX_ADD_IO_SEG(0x0001180000002098ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_EMM_SWITCH CVMX_MIO_EMM_SWITCH_FUNC()
+static inline uint64_t CVMX_MIO_EMM_SWITCH_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_EMM_SWITCH not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000002048ull);
+}
+#else
+#define CVMX_MIO_EMM_SWITCH (CVMX_ADD_IO_SEG(0x0001180000002048ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_EMM_WDOG CVMX_MIO_EMM_WDOG_FUNC()
+static inline uint64_t CVMX_MIO_EMM_WDOG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_EMM_WDOG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000002088ull);
+}
+#else
+#define CVMX_MIO_EMM_WDOG (CVMX_ADD_IO_SEG(0x0001180000002088ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_MIO_FUS_BNK_DATX(unsigned long offset)
 {
 	if (!(
@@ -194,7 +399,11 @@ static inline uint64_t CVMX_MIO_FUS_BNK_DATX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_FUS_BNK_DATX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8;
 }
@@ -209,7 +418,7 @@ static inline uint64_t CVMX_MIO_FUS_BNK_DATX(unsigned long offset)
 #define CVMX_MIO_FUS_EMA CVMX_MIO_FUS_EMA_FUNC()
 static inline uint64_t CVMX_MIO_FUS_EMA_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_FUS_EMA not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180000001550ull);
 }
@@ -220,7 +429,7 @@ static inline uint64_t CVMX_MIO_FUS_EMA_FUNC(void)
 #define CVMX_MIO_FUS_PDF CVMX_MIO_FUS_PDF_FUNC()
 static inline uint64_t CVMX_MIO_FUS_PDF_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_FUS_PDF not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180000001420ull);
 }
@@ -231,7 +440,7 @@ static inline uint64_t CVMX_MIO_FUS_PDF_FUNC(void)
 #define CVMX_MIO_FUS_PLL CVMX_MIO_FUS_PLL_FUNC()
 static inline uint64_t CVMX_MIO_FUS_PLL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_FUS_PLL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180000001580ull);
 }
@@ -243,7 +452,7 @@ static inline uint64_t CVMX_MIO_FUS_PLL_FUNC(void)
 #define CVMX_MIO_FUS_PROG_TIMES CVMX_MIO_FUS_PROG_TIMES_FUNC()
 static inline uint64_t CVMX_MIO_FUS_PROG_TIMES_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_FUS_PROG_TIMES not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180000001518ull);
 }
@@ -255,7 +464,7 @@ static inline uint64_t CVMX_MIO_FUS_PROG_TIMES_FUNC(void)
 #define CVMX_MIO_FUS_READ_TIMES CVMX_MIO_FUS_READ_TIMES_FUNC()
 static inline uint64_t CVMX_MIO_FUS_READ_TIMES_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_FUS_READ_TIMES not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180000001570ull);
 }
@@ -266,7 +475,7 @@ static inline uint64_t CVMX_MIO_FUS_READ_TIMES_FUNC(void)
 #define CVMX_MIO_FUS_REPAIR_RES0 CVMX_MIO_FUS_REPAIR_RES0_FUNC()
 static inline uint64_t CVMX_MIO_FUS_REPAIR_RES0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_FUS_REPAIR_RES0 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180000001558ull);
 }
@@ -277,7 +486,7 @@ static inline uint64_t CVMX_MIO_FUS_REPAIR_RES0_FUNC(void)
 #define CVMX_MIO_FUS_REPAIR_RES1 CVMX_MIO_FUS_REPAIR_RES1_FUNC()
 static inline uint64_t CVMX_MIO_FUS_REPAIR_RES1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_FUS_REPAIR_RES1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180000001560ull);
 }
@@ -288,7 +497,7 @@ static inline uint64_t CVMX_MIO_FUS_REPAIR_RES1_FUNC(void)
 #define CVMX_MIO_FUS_REPAIR_RES2 CVMX_MIO_FUS_REPAIR_RES2_FUNC()
 static inline uint64_t CVMX_MIO_FUS_REPAIR_RES2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_FUS_REPAIR_RES2 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180000001568ull);
 }
@@ -298,6 +507,17 @@ static inline uint64_t CVMX_MIO_FUS_REPAIR_RES2_FUNC(void)
 #define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
 #define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_FUS_TGG CVMX_MIO_FUS_TGG_FUNC()
+static inline uint64_t CVMX_MIO_FUS_TGG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_FUS_TGG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001428ull);
+}
+#else
+#define CVMX_MIO_FUS_TGG (CVMX_ADD_IO_SEG(0x0001180000001428ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_MIO_FUS_UNLOCK CVMX_MIO_FUS_UNLOCK_FUNC()
 static inline uint64_t CVMX_MIO_FUS_UNLOCK_FUNC(void)
 {
@@ -313,7 +533,7 @@ static inline uint64_t CVMX_MIO_FUS_UNLOCK_FUNC(void)
 #define CVMX_MIO_GPIO_COMP CVMX_MIO_GPIO_COMP_FUNC()
 static inline uint64_t CVMX_MIO_GPIO_COMP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_GPIO_COMP not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800000000C8ull);
 }
@@ -324,7 +544,7 @@ static inline uint64_t CVMX_MIO_GPIO_COMP_FUNC(void)
 #define CVMX_MIO_NDF_DMA_CFG CVMX_MIO_NDF_DMA_CFG_FUNC()
 static inline uint64_t CVMX_MIO_NDF_DMA_CFG_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_NDF_DMA_CFG not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180000000168ull);
 }
@@ -335,7 +555,7 @@ static inline uint64_t CVMX_MIO_NDF_DMA_CFG_FUNC(void)
 #define CVMX_MIO_NDF_DMA_INT CVMX_MIO_NDF_DMA_INT_FUNC()
 static inline uint64_t CVMX_MIO_NDF_DMA_INT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_NDF_DMA_INT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180000000170ull);
 }
@@ -346,7 +566,7 @@ static inline uint64_t CVMX_MIO_NDF_DMA_INT_FUNC(void)
 #define CVMX_MIO_NDF_DMA_INT_EN CVMX_MIO_NDF_DMA_INT_EN_FUNC()
 static inline uint64_t CVMX_MIO_NDF_DMA_INT_EN_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_NDF_DMA_INT_EN not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180000000178ull);
 }
@@ -376,10 +596,54 @@ static inline uint64_t CVMX_MIO_PLL_SETTING_FUNC(void)
 #define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_PTP_CKOUT_HI_INCR CVMX_MIO_PTP_CKOUT_HI_INCR_FUNC()
+static inline uint64_t CVMX_MIO_PTP_CKOUT_HI_INCR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_PTP_CKOUT_HI_INCR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000F40ull);
+}
+#else
+#define CVMX_MIO_PTP_CKOUT_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F40ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_PTP_CKOUT_LO_INCR CVMX_MIO_PTP_CKOUT_LO_INCR_FUNC()
+static inline uint64_t CVMX_MIO_PTP_CKOUT_LO_INCR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_PTP_CKOUT_LO_INCR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000F48ull);
+}
+#else
+#define CVMX_MIO_PTP_CKOUT_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F48ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_PTP_CKOUT_THRESH_HI CVMX_MIO_PTP_CKOUT_THRESH_HI_FUNC()
+static inline uint64_t CVMX_MIO_PTP_CKOUT_THRESH_HI_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_PTP_CKOUT_THRESH_HI not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000F38ull);
+}
+#else
+#define CVMX_MIO_PTP_CKOUT_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F38ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_PTP_CKOUT_THRESH_LO CVMX_MIO_PTP_CKOUT_THRESH_LO_FUNC()
+static inline uint64_t CVMX_MIO_PTP_CKOUT_THRESH_LO_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_PTP_CKOUT_THRESH_LO not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000F30ull);
+}
+#else
+#define CVMX_MIO_PTP_CKOUT_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F30ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_MIO_PTP_CLOCK_CFG CVMX_MIO_PTP_CLOCK_CFG_FUNC()
 static inline uint64_t CVMX_MIO_PTP_CLOCK_CFG_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_PTP_CLOCK_CFG not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070000000F00ull);
 }
@@ -390,7 +654,7 @@ static inline uint64_t CVMX_MIO_PTP_CLOCK_CFG_FUNC(void)
 #define CVMX_MIO_PTP_CLOCK_COMP CVMX_MIO_PTP_CLOCK_COMP_FUNC()
 static inline uint64_t CVMX_MIO_PTP_CLOCK_COMP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_PTP_CLOCK_COMP not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070000000F18ull);
 }
@@ -401,7 +665,7 @@ static inline uint64_t CVMX_MIO_PTP_CLOCK_COMP_FUNC(void)
 #define CVMX_MIO_PTP_CLOCK_HI CVMX_MIO_PTP_CLOCK_HI_FUNC()
 static inline uint64_t CVMX_MIO_PTP_CLOCK_HI_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_PTP_CLOCK_HI not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070000000F10ull);
 }
@@ -412,7 +676,7 @@ static inline uint64_t CVMX_MIO_PTP_CLOCK_HI_FUNC(void)
 #define CVMX_MIO_PTP_CLOCK_LO CVMX_MIO_PTP_CLOCK_LO_FUNC()
 static inline uint64_t CVMX_MIO_PTP_CLOCK_LO_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_PTP_CLOCK_LO not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070000000F08ull);
 }
@@ -423,7 +687,7 @@ static inline uint64_t CVMX_MIO_PTP_CLOCK_LO_FUNC(void)
 #define CVMX_MIO_PTP_EVT_CNT CVMX_MIO_PTP_EVT_CNT_FUNC()
 static inline uint64_t CVMX_MIO_PTP_EVT_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_PTP_EVT_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070000000F28ull);
 }
@@ -431,10 +695,65 @@ static inline uint64_t CVMX_MIO_PTP_EVT_CNT_FUNC(void)
 #define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_PTP_PHY_1PPS_IN CVMX_MIO_PTP_PHY_1PPS_IN_FUNC()
+static inline uint64_t CVMX_MIO_PTP_PHY_1PPS_IN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_PTP_PHY_1PPS_IN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000F70ull);
+}
+#else
+#define CVMX_MIO_PTP_PHY_1PPS_IN (CVMX_ADD_IO_SEG(0x0001070000000F70ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_PTP_PPS_HI_INCR CVMX_MIO_PTP_PPS_HI_INCR_FUNC()
+static inline uint64_t CVMX_MIO_PTP_PPS_HI_INCR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_PTP_PPS_HI_INCR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000F60ull);
+}
+#else
+#define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_PTP_PPS_LO_INCR CVMX_MIO_PTP_PPS_LO_INCR_FUNC()
+static inline uint64_t CVMX_MIO_PTP_PPS_LO_INCR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_PTP_PPS_LO_INCR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000F68ull);
+}
+#else
+#define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_PTP_PPS_THRESH_HI CVMX_MIO_PTP_PPS_THRESH_HI_FUNC()
+static inline uint64_t CVMX_MIO_PTP_PPS_THRESH_HI_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_PTP_PPS_THRESH_HI not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000F58ull);
+}
+#else
+#define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_PTP_PPS_THRESH_LO CVMX_MIO_PTP_PPS_THRESH_LO_FUNC()
+static inline uint64_t CVMX_MIO_PTP_PPS_THRESH_LO_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_PTP_PPS_THRESH_LO not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000F50ull);
+}
+#else
+#define CVMX_MIO_PTP_PPS_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F50ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_MIO_PTP_TIMESTAMP CVMX_MIO_PTP_TIMESTAMP_FUNC()
 static inline uint64_t CVMX_MIO_PTP_TIMESTAMP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_PTP_TIMESTAMP not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070000000F20ull);
 }
@@ -442,10 +761,24 @@ static inline uint64_t CVMX_MIO_PTP_TIMESTAMP_FUNC(void)
 #define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_QLMX_CFG(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 2))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 2))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 4))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_QLMX_CFG(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_MIO_RST_BOOT CVMX_MIO_RST_BOOT_FUNC()
 static inline uint64_t CVMX_MIO_RST_BOOT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_RST_BOOT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180000001600ull);
 }
@@ -456,7 +789,7 @@ static inline uint64_t CVMX_MIO_RST_BOOT_FUNC(void)
 #define CVMX_MIO_RST_CFG CVMX_MIO_RST_CFG_FUNC()
 static inline uint64_t CVMX_MIO_RST_CFG_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_RST_CFG not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180000001610ull);
 }
@@ -464,10 +797,39 @@ static inline uint64_t CVMX_MIO_RST_CFG_FUNC(void)
 #define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_RST_CKILL CVMX_MIO_RST_CKILL_FUNC()
+static inline uint64_t CVMX_MIO_RST_CKILL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_MIO_RST_CKILL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001638ull);
+}
+#else
+#define CVMX_MIO_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180000001638ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_RST_CNTLX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_RST_CNTLX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_MIO_RST_CNTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_MIO_RST_CTLX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_RST_CTLX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8;
 }
@@ -478,7 +840,7 @@ static inline uint64_t CVMX_MIO_RST_CTLX(unsigned long offset)
 #define CVMX_MIO_RST_DELAY CVMX_MIO_RST_DELAY_FUNC()
 static inline uint64_t CVMX_MIO_RST_DELAY_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_RST_DELAY not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180000001608ull);
 }
@@ -489,7 +851,7 @@ static inline uint64_t CVMX_MIO_RST_DELAY_FUNC(void)
 #define CVMX_MIO_RST_INT CVMX_MIO_RST_INT_FUNC()
 static inline uint64_t CVMX_MIO_RST_INT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_RST_INT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180000001628ull);
 }
@@ -500,7 +862,7 @@ static inline uint64_t CVMX_MIO_RST_INT_FUNC(void)
 #define CVMX_MIO_RST_INT_EN CVMX_MIO_RST_INT_EN_FUNC()
 static inline uint64_t CVMX_MIO_RST_INT_EN_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MIO_RST_INT_EN not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180000001630ull);
 }
@@ -518,7 +880,11 @@ static inline uint64_t CVMX_MIO_TWSX_INT(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_TWSX_INT(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512;
 }
@@ -536,7 +902,11 @@ static inline uint64_t CVMX_MIO_TWSX_SW_TWSI(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_TWSX_SW_TWSI(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512;
 }
@@ -554,7 +924,11 @@ static inline uint64_t CVMX_MIO_TWSX_SW_TWSI_EXT(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_TWSX_SW_TWSI_EXT(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512;
 }
@@ -572,7 +946,11 @@ static inline uint64_t CVMX_MIO_TWSX_TWSI_SW(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_TWSX_TWSI_SW(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512;
 }
@@ -865,7 +1243,11 @@ static inline uint64_t CVMX_MIO_UARTX_DLH(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_DLH(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024;
 }
@@ -883,7 +1265,11 @@ static inline uint64_t CVMX_MIO_UARTX_DLL(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_DLL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024;
 }
@@ -901,7 +1287,11 @@ static inline uint64_t CVMX_MIO_UARTX_FAR(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_FAR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024;
 }
@@ -919,7 +1309,11 @@ static inline uint64_t CVMX_MIO_UARTX_FCR(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_FCR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024;
 }
@@ -937,7 +1331,11 @@ static inline uint64_t CVMX_MIO_UARTX_HTX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_HTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024;
 }
@@ -955,7 +1353,11 @@ static inline uint64_t CVMX_MIO_UARTX_IER(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_IER(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024;
 }
@@ -973,7 +1375,11 @@ static inline uint64_t CVMX_MIO_UARTX_IIR(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_IIR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024;
 }
@@ -991,7 +1397,11 @@ static inline uint64_t CVMX_MIO_UARTX_LCR(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_LCR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024;
 }
@@ -1009,7 +1419,11 @@ static inline uint64_t CVMX_MIO_UARTX_LSR(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_LSR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024;
 }
@@ -1027,7 +1441,11 @@ static inline uint64_t CVMX_MIO_UARTX_MCR(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_MCR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024;
 }
@@ -1045,7 +1463,11 @@ static inline uint64_t CVMX_MIO_UARTX_MSR(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_MSR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024;
 }
@@ -1063,7 +1485,11 @@ static inline uint64_t CVMX_MIO_UARTX_RBR(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_RBR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024;
 }
@@ -1081,7 +1507,11 @@ static inline uint64_t CVMX_MIO_UARTX_RFL(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_RFL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024;
 }
@@ -1099,7 +1529,11 @@ static inline uint64_t CVMX_MIO_UARTX_RFW(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_RFW(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024;
 }
@@ -1117,7 +1551,11 @@ static inline uint64_t CVMX_MIO_UARTX_SBCR(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_SBCR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024;
 }
@@ -1135,7 +1573,11 @@ static inline uint64_t CVMX_MIO_UARTX_SCR(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_SCR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024;
 }
@@ -1153,7 +1595,11 @@ static inline uint64_t CVMX_MIO_UARTX_SFE(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_SFE(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024;
 }
@@ -1171,7 +1617,11 @@ static inline uint64_t CVMX_MIO_UARTX_SRR(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_SRR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024;
 }
@@ -1189,7 +1639,11 @@ static inline uint64_t CVMX_MIO_UARTX_SRT(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_SRT(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024;
 }
@@ -1207,7 +1661,11 @@ static inline uint64_t CVMX_MIO_UARTX_SRTS(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_SRTS(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024;
 }
@@ -1225,7 +1683,11 @@ static inline uint64_t CVMX_MIO_UARTX_STT(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_STT(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024;
 }
@@ -1243,7 +1705,11 @@ static inline uint64_t CVMX_MIO_UARTX_TFL(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_TFL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024;
 }
@@ -1261,7 +1727,11 @@ static inline uint64_t CVMX_MIO_UARTX_TFR(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_TFR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024;
 }
@@ -1279,7 +1749,11 @@ static inline uint64_t CVMX_MIO_UARTX_THR(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_THR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024;
 }
@@ -1297,7 +1771,11 @@ static inline uint64_t CVMX_MIO_UARTX_USR(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_MIO_UARTX_USR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024;
 }
@@ -1312,20 +1790,17 @@ static inline uint64_t CVMX_MIO_UARTX_USR(unsigned long offset)
  *
  * Contains the BIST status for the MIO boot memories.  '0' = pass, '1' = fail.
  */
-union cvmx_mio_boot_bist_stat
-{
+union cvmx_mio_boot_bist_stat {
 	uint64_t u64;
-	struct cvmx_mio_boot_bist_stat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_bist_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_0_63                : 64;
 #else
 	uint64_t reserved_0_63                : 64;
 #endif
 	} s;
-	struct cvmx_mio_boot_bist_stat_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_bist_stat_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t ncbo_1                       : 1;  /**< NCB output FIFO 1 BIST status */
 	uint64_t ncbo_0                       : 1;  /**< NCB output FIFO 0 BIST status */
@@ -1340,9 +1815,8 @@ union cvmx_mio_boot_bist_stat
 #endif
 	} cn30xx;
 	struct cvmx_mio_boot_bist_stat_cn30xx cn31xx;
-	struct cvmx_mio_boot_bist_stat_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_bist_stat_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t ncbo_0                       : 1;  /**< NCB output FIFO BIST status */
 	uint64_t loc                          : 1;  /**< Local memory BIST status */
@@ -1355,15 +1829,14 @@ union cvmx_mio_boot_bist_stat
 #endif
 	} cn38xx;
 	struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2;
-	struct cvmx_mio_boot_bist_stat_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_bist_stat_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t pcm_1                        : 1;  /**< PCM memory 1 BIST status */
 	uint64_t pcm_0                        : 1;  /**< PCM memory 0 BIST status */
 	uint64_t ncbo_1                       : 1;  /**< NCB output FIFO 1 BIST status */
 	uint64_t ncbo_0                       : 1;  /**< NCB output FIFO 0 BIST status */
-	uint64_t loc                          : 1;  /**< Local memory BIST status */
+	uint64_t loc                          : 1;  /**< Local memory region BIST status */
 	uint64_t ncbi                         : 1;  /**< NCB input FIFO BIST status */
 #else
 	uint64_t ncbi                         : 1;
@@ -1375,9 +1848,8 @@ union cvmx_mio_boot_bist_stat
 	uint64_t reserved_6_63                : 58;
 #endif
 	} cn50xx;
-	struct cvmx_mio_boot_bist_stat_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_bist_stat_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t ndf                          : 2;  /**< NAND flash BIST status */
 	uint64_t ncbo_0                       : 1;  /**< NCB output FIFO BIST status */
@@ -1393,13 +1865,12 @@ union cvmx_mio_boot_bist_stat
 	uint64_t reserved_6_63                : 58;
 #endif
 	} cn52xx;
-	struct cvmx_mio_boot_bist_stat_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_bist_stat_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t ncbo_0                       : 1;  /**< NCB output FIFO BIST status */
 	uint64_t dma                          : 1;  /**< DMA memory BIST status */
-	uint64_t loc                          : 1;  /**< Local memory BIST status */
+	uint64_t loc                          : 1;  /**< Local memory region BIST status */
 	uint64_t ncbi                         : 1;  /**< NCB input FIFO BIST status */
 #else
 	uint64_t ncbi                         : 1;
@@ -1413,9 +1884,17 @@ union cvmx_mio_boot_bist_stat
 	struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
 	struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
 	struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
-	struct cvmx_mio_boot_bist_stat_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_bist_stat_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_12_63               : 52;
+	uint64_t stat                         : 12; /**< BIST status */
+#else
+	uint64_t stat                         : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn61xx;
+	struct cvmx_mio_boot_bist_stat_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t stat                         : 9;  /**< BIST status */
 #else
@@ -1424,6 +1903,18 @@ union cvmx_mio_boot_bist_stat
 #endif
 	} cn63xx;
 	struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1;
+	struct cvmx_mio_boot_bist_stat_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t stat                         : 10; /**< BIST status */
+#else
+	uint64_t stat                         : 10;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn66xx;
+	struct cvmx_mio_boot_bist_stat_cn66xx cn68xx;
+	struct cvmx_mio_boot_bist_stat_cn66xx cn68xxp1;
+	struct cvmx_mio_boot_bist_stat_cn61xx cnf71xx;
 };
 typedef union cvmx_mio_boot_bist_stat cvmx_mio_boot_bist_stat_t;
 
@@ -1439,20 +1930,17 @@ typedef union cvmx_mio_boot_bist_stat cvmx_mio_boot_bist_stat_t;
  * pullup on boot_ad[10],    PCTL=15, NCTL=12 (65 ohm termination)
  * pullups on boot_ad[10:9], PCTL=15, NCTL=12 (65 ohm termination)
  */
-union cvmx_mio_boot_comp
-{
+union cvmx_mio_boot_comp {
 	uint64_t u64;
-	struct cvmx_mio_boot_comp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_comp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_0_63                : 64;
 #else
 	uint64_t reserved_0_63                : 64;
 #endif
 	} s;
-	struct cvmx_mio_boot_comp_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_comp_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t pctl                         : 5;  /**< Boot bus PCTL */
 	uint64_t nctl                         : 5;  /**< Boot bus NCTL */
@@ -1466,9 +1954,8 @@ union cvmx_mio_boot_comp
 	struct cvmx_mio_boot_comp_cn50xx      cn52xxp1;
 	struct cvmx_mio_boot_comp_cn50xx      cn56xx;
 	struct cvmx_mio_boot_comp_cn50xx      cn56xxp1;
-	struct cvmx_mio_boot_comp_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_comp_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t pctl                         : 6;  /**< Boot bus PCTL */
 	uint64_t nctl                         : 6;  /**< Boot bus NCTL */
@@ -1477,8 +1964,13 @@ union cvmx_mio_boot_comp
 	uint64_t pctl                         : 6;
 	uint64_t reserved_12_63               : 52;
 #endif
-	} cn63xx;
-	struct cvmx_mio_boot_comp_cn63xx      cn63xxp1;
+	} cn61xx;
+	struct cvmx_mio_boot_comp_cn61xx      cn63xx;
+	struct cvmx_mio_boot_comp_cn61xx      cn63xxp1;
+	struct cvmx_mio_boot_comp_cn61xx      cn66xx;
+	struct cvmx_mio_boot_comp_cn61xx      cn68xx;
+	struct cvmx_mio_boot_comp_cn61xx      cn68xxp1;
+	struct cvmx_mio_boot_comp_cn61xx      cnf71xx;
 };
 typedef union cvmx_mio_boot_comp cvmx_mio_boot_comp_t;
 
@@ -1499,12 +1991,10 @@ typedef union cvmx_mio_boot_comp cvmx_mio_boot_comp_t;
  *
  * Note: ADR must be aligned to the bus width (i.e. 16 bit aligned if WIDTH=0, 32 bit aligned if WIDTH=1).
  */
-union cvmx_mio_boot_dma_cfgx
-{
+union cvmx_mio_boot_dma_cfgx {
 	uint64_t u64;
-	struct cvmx_mio_boot_dma_cfgx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_dma_cfgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t en                           : 1;  /**< DMA Engine X enable */
 	uint64_t rw                           : 1;  /**< DMA Engine X R/W bit (0 = read, 1 = write) */
 	uint64_t clr                          : 1;  /**< DMA Engine X clear EN on device terminated burst */
@@ -1532,8 +2022,13 @@ union cvmx_mio_boot_dma_cfgx
 	struct cvmx_mio_boot_dma_cfgx_s       cn52xxp1;
 	struct cvmx_mio_boot_dma_cfgx_s       cn56xx;
 	struct cvmx_mio_boot_dma_cfgx_s       cn56xxp1;
+	struct cvmx_mio_boot_dma_cfgx_s       cn61xx;
 	struct cvmx_mio_boot_dma_cfgx_s       cn63xx;
 	struct cvmx_mio_boot_dma_cfgx_s       cn63xxp1;
+	struct cvmx_mio_boot_dma_cfgx_s       cn66xx;
+	struct cvmx_mio_boot_dma_cfgx_s       cn68xx;
+	struct cvmx_mio_boot_dma_cfgx_s       cn68xxp1;
+	struct cvmx_mio_boot_dma_cfgx_s       cnf71xx;
 };
 typedef union cvmx_mio_boot_dma_cfgx cvmx_mio_boot_dma_cfgx_t;
 
@@ -1543,12 +2038,10 @@ typedef union cvmx_mio_boot_dma_cfgx cvmx_mio_boot_dma_cfgx_t;
  * MIO_BOOT_DMA_INT = MIO Boot DMA Interrupt Register (1 per engine * 2 engines)
  *
  */
-union cvmx_mio_boot_dma_intx
-{
+union cvmx_mio_boot_dma_intx {
 	uint64_t u64;
-	struct cvmx_mio_boot_dma_intx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_dma_intx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t dmarq                        : 1;  /**< DMA Engine X DMARQ asserted interrupt */
 	uint64_t done                         : 1;  /**< DMA Engine X request completion interrupt */
@@ -1562,8 +2055,13 @@ union cvmx_mio_boot_dma_intx
 	struct cvmx_mio_boot_dma_intx_s       cn52xxp1;
 	struct cvmx_mio_boot_dma_intx_s       cn56xx;
 	struct cvmx_mio_boot_dma_intx_s       cn56xxp1;
+	struct cvmx_mio_boot_dma_intx_s       cn61xx;
 	struct cvmx_mio_boot_dma_intx_s       cn63xx;
 	struct cvmx_mio_boot_dma_intx_s       cn63xxp1;
+	struct cvmx_mio_boot_dma_intx_s       cn66xx;
+	struct cvmx_mio_boot_dma_intx_s       cn68xx;
+	struct cvmx_mio_boot_dma_intx_s       cn68xxp1;
+	struct cvmx_mio_boot_dma_intx_s       cnf71xx;
 };
 typedef union cvmx_mio_boot_dma_intx cvmx_mio_boot_dma_intx_t;
 
@@ -1573,12 +2071,10 @@ typedef union cvmx_mio_boot_dma_intx cvmx_mio_boot_dma_intx_t;
  * MIO_BOOT_DMA_INT_EN = MIO Boot DMA Interrupt Enable Register (1 per engine * 2 engines)
  *
  */
-union cvmx_mio_boot_dma_int_enx
-{
+union cvmx_mio_boot_dma_int_enx {
 	uint64_t u64;
-	struct cvmx_mio_boot_dma_int_enx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_dma_int_enx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t dmarq                        : 1;  /**< DMA Engine X DMARQ asserted interrupt enable */
 	uint64_t done                         : 1;  /**< DMA Engine X request completion interrupt enable */
@@ -1592,8 +2088,13 @@ union cvmx_mio_boot_dma_int_enx
 	struct cvmx_mio_boot_dma_int_enx_s    cn52xxp1;
 	struct cvmx_mio_boot_dma_int_enx_s    cn56xx;
 	struct cvmx_mio_boot_dma_int_enx_s    cn56xxp1;
+	struct cvmx_mio_boot_dma_int_enx_s    cn61xx;
 	struct cvmx_mio_boot_dma_int_enx_s    cn63xx;
 	struct cvmx_mio_boot_dma_int_enx_s    cn63xxp1;
+	struct cvmx_mio_boot_dma_int_enx_s    cn66xx;
+	struct cvmx_mio_boot_dma_int_enx_s    cn68xx;
+	struct cvmx_mio_boot_dma_int_enx_s    cn68xxp1;
+	struct cvmx_mio_boot_dma_int_enx_s    cnf71xx;
 };
 typedef union cvmx_mio_boot_dma_int_enx cvmx_mio_boot_dma_int_enx_t;
 
@@ -1624,12 +2125,10 @@ typedef union cvmx_mio_boot_dma_int_enx cvmx_mio_boot_dma_int_enx_t;
  *
  * If DDR is set, then WE_N must be less than WE_A.
  */
-union cvmx_mio_boot_dma_timx
-{
+union cvmx_mio_boot_dma_timx {
 	uint64_t u64;
-	struct cvmx_mio_boot_dma_timx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_dma_timx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t dmack_pi                     : 1;  /**< DMA Engine X DMA ack polarity inversion */
 	uint64_t dmarq_pi                     : 1;  /**< DMA Engine X DMA request polarity inversion */
 	uint64_t tim_mult                     : 2;  /**< DMA Engine X timing multiplier */
@@ -1667,8 +2166,13 @@ union cvmx_mio_boot_dma_timx
 	struct cvmx_mio_boot_dma_timx_s       cn52xxp1;
 	struct cvmx_mio_boot_dma_timx_s       cn56xx;
 	struct cvmx_mio_boot_dma_timx_s       cn56xxp1;
+	struct cvmx_mio_boot_dma_timx_s       cn61xx;
 	struct cvmx_mio_boot_dma_timx_s       cn63xx;
 	struct cvmx_mio_boot_dma_timx_s       cn63xxp1;
+	struct cvmx_mio_boot_dma_timx_s       cn66xx;
+	struct cvmx_mio_boot_dma_timx_s       cn68xx;
+	struct cvmx_mio_boot_dma_timx_s       cn68xxp1;
+	struct cvmx_mio_boot_dma_timx_s       cnf71xx;
 };
 typedef union cvmx_mio_boot_dma_timx cvmx_mio_boot_dma_timx_t;
 
@@ -1678,15 +2182,13 @@ typedef union cvmx_mio_boot_dma_timx cvmx_mio_boot_dma_timx_t;
  * MIO_BOOT_ERR = MIO Boot Error Register
  *
  * Contains the address decode error and wait mode error bits.  Address decode error is set when a
- * boot bus access does not hit in any of the 8 remote regions or 2 local regions.  Wait mode error is
+ * boot bus access does not hit in any of the 8 remote regions or 2 local memory regions.  Wait mode error is
  * set when wait mode is enabled and the external wait signal is not de-asserted after 32k eclk cycles.
  */
-union cvmx_mio_boot_err
-{
+union cvmx_mio_boot_err {
 	uint64_t u64;
-	struct cvmx_mio_boot_err_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_err_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t wait_err                     : 1;  /**< Wait mode error */
 	uint64_t adr_err                      : 1;  /**< Address decode error */
@@ -1707,8 +2209,13 @@ union cvmx_mio_boot_err
 	struct cvmx_mio_boot_err_s            cn56xxp1;
 	struct cvmx_mio_boot_err_s            cn58xx;
 	struct cvmx_mio_boot_err_s            cn58xxp1;
+	struct cvmx_mio_boot_err_s            cn61xx;
 	struct cvmx_mio_boot_err_s            cn63xx;
 	struct cvmx_mio_boot_err_s            cn63xxp1;
+	struct cvmx_mio_boot_err_s            cn66xx;
+	struct cvmx_mio_boot_err_s            cn68xx;
+	struct cvmx_mio_boot_err_s            cn68xxp1;
+	struct cvmx_mio_boot_err_s            cnf71xx;
 };
 typedef union cvmx_mio_boot_err cvmx_mio_boot_err_t;
 
@@ -1719,12 +2226,10 @@ typedef union cvmx_mio_boot_err cvmx_mio_boot_err_t;
  *
  * Contains the interrupt enable bits for address decode error and wait mode error.
  */
-union cvmx_mio_boot_int
-{
+union cvmx_mio_boot_int {
 	uint64_t u64;
-	struct cvmx_mio_boot_int_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t wait_int                     : 1;  /**< Wait mode error interrupt enable */
 	uint64_t adr_int                      : 1;  /**< Address decode error interrupt enable */
@@ -1745,30 +2250,33 @@ union cvmx_mio_boot_int
 	struct cvmx_mio_boot_int_s            cn56xxp1;
 	struct cvmx_mio_boot_int_s            cn58xx;
 	struct cvmx_mio_boot_int_s            cn58xxp1;
+	struct cvmx_mio_boot_int_s            cn61xx;
 	struct cvmx_mio_boot_int_s            cn63xx;
 	struct cvmx_mio_boot_int_s            cn63xxp1;
+	struct cvmx_mio_boot_int_s            cn66xx;
+	struct cvmx_mio_boot_int_s            cn68xx;
+	struct cvmx_mio_boot_int_s            cn68xxp1;
+	struct cvmx_mio_boot_int_s            cnf71xx;
 };
 typedef union cvmx_mio_boot_int cvmx_mio_boot_int_t;
 
 /**
  * cvmx_mio_boot_loc_adr
  *
- * MIO_BOOT_LOC_ADR = MIO Boot Local Memory Address Register
+ * MIO_BOOT_LOC_ADR = MIO Boot Local Memory Region Address Register
  *
- * Specifies the address for reading or writing the local memory.  This address will post-increment
- * following an access to the MIO Boot Local Memory Data Register (MIO_BOOT_LOC_DAT).
+ * Specifies the address for reading or writing the local memory region.  This address will post-increment
+ * following an access to the MIO Boot Local Memory Region Data Register (MIO_BOOT_LOC_DAT).
  *
  * Local memory region 0 exists from addresses 0x00 - 0x78.
  * Local memory region 1 exists from addresses 0x80 - 0xf8.
  */
-union cvmx_mio_boot_loc_adr
-{
+union cvmx_mio_boot_loc_adr {
 	uint64_t u64;
-	struct cvmx_mio_boot_loc_adr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_loc_adr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
-	uint64_t adr                          : 5;  /**< Local memory address */
+	uint64_t adr                          : 5;  /**< Local memory region address */
 	uint64_t reserved_0_2                 : 3;
 #else
 	uint64_t reserved_0_2                 : 3;
@@ -1787,31 +2295,34 @@ union cvmx_mio_boot_loc_adr
 	struct cvmx_mio_boot_loc_adr_s        cn56xxp1;
 	struct cvmx_mio_boot_loc_adr_s        cn58xx;
 	struct cvmx_mio_boot_loc_adr_s        cn58xxp1;
+	struct cvmx_mio_boot_loc_adr_s        cn61xx;
 	struct cvmx_mio_boot_loc_adr_s        cn63xx;
 	struct cvmx_mio_boot_loc_adr_s        cn63xxp1;
+	struct cvmx_mio_boot_loc_adr_s        cn66xx;
+	struct cvmx_mio_boot_loc_adr_s        cn68xx;
+	struct cvmx_mio_boot_loc_adr_s        cn68xxp1;
+	struct cvmx_mio_boot_loc_adr_s        cnf71xx;
 };
 typedef union cvmx_mio_boot_loc_adr cvmx_mio_boot_loc_adr_t;
 
 /**
  * cvmx_mio_boot_loc_cfg#
  *
- * MIO_BOOT_LOC_CFG = MIO Boot Local Region Config Register (1 per region * 2 regions)
+ * MIO_BOOT_LOC_CFG = MIO Boot Local Memory Region Config Register (1 per region * 2 regions)
  *
- * Contains local region enable and local region base address parameters.  Each local region is 128
+ * Contains local memory region enable and local memory region base address parameters.  Each local memory region is 128
  * bytes organized as 16 entries x 8 bytes.
  *
  * Base address specifies address bits [31:7] of the region.
  */
-union cvmx_mio_boot_loc_cfgx
-{
+union cvmx_mio_boot_loc_cfgx {
 	uint64_t u64;
-	struct cvmx_mio_boot_loc_cfgx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_loc_cfgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
-	uint64_t en                           : 1;  /**< Local region X enable */
+	uint64_t en                           : 1;  /**< Local memory region X enable */
 	uint64_t reserved_28_30               : 3;
-	uint64_t base                         : 25; /**< Local region X base address */
+	uint64_t base                         : 25; /**< Local memory region X base address */
 	uint64_t reserved_0_2                 : 3;
 #else
 	uint64_t reserved_0_2                 : 3;
@@ -1832,26 +2343,29 @@ union cvmx_mio_boot_loc_cfgx
 	struct cvmx_mio_boot_loc_cfgx_s       cn56xxp1;
 	struct cvmx_mio_boot_loc_cfgx_s       cn58xx;
 	struct cvmx_mio_boot_loc_cfgx_s       cn58xxp1;
+	struct cvmx_mio_boot_loc_cfgx_s       cn61xx;
 	struct cvmx_mio_boot_loc_cfgx_s       cn63xx;
 	struct cvmx_mio_boot_loc_cfgx_s       cn63xxp1;
+	struct cvmx_mio_boot_loc_cfgx_s       cn66xx;
+	struct cvmx_mio_boot_loc_cfgx_s       cn68xx;
+	struct cvmx_mio_boot_loc_cfgx_s       cn68xxp1;
+	struct cvmx_mio_boot_loc_cfgx_s       cnf71xx;
 };
 typedef union cvmx_mio_boot_loc_cfgx cvmx_mio_boot_loc_cfgx_t;
 
 /**
  * cvmx_mio_boot_loc_dat
  *
- * MIO_BOOT_LOC_DAT = MIO Boot Local Memory Data Register
+ * MIO_BOOT_LOC_DAT = MIO Boot Local Memory Region Data Register
  *
- * This is a pseudo-register that will read/write the local memory at the address specified by the MIO
- * Boot Local Address Register (MIO_BOOT_LOC_ADR) when accessed.
+ * This is a pseudo-register that will read/write the local memory region at the address specified by the MIO
+ * Boot Local Memory Region Address Register (MIO_BOOT_LOC_ADR) when accessed.
  */
-union cvmx_mio_boot_loc_dat
-{
+union cvmx_mio_boot_loc_dat {
 	uint64_t u64;
-	struct cvmx_mio_boot_loc_dat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t data                         : 64; /**< Local memory data */
+	struct cvmx_mio_boot_loc_dat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t data                         : 64; /**< Local memory region data */
 #else
 	uint64_t data                         : 64;
 #endif
@@ -1867,8 +2381,13 @@ union cvmx_mio_boot_loc_dat
 	struct cvmx_mio_boot_loc_dat_s        cn56xxp1;
 	struct cvmx_mio_boot_loc_dat_s        cn58xx;
 	struct cvmx_mio_boot_loc_dat_s        cn58xxp1;
+	struct cvmx_mio_boot_loc_dat_s        cn61xx;
 	struct cvmx_mio_boot_loc_dat_s        cn63xx;
 	struct cvmx_mio_boot_loc_dat_s        cn63xxp1;
+	struct cvmx_mio_boot_loc_dat_s        cn66xx;
+	struct cvmx_mio_boot_loc_dat_s        cn68xx;
+	struct cvmx_mio_boot_loc_dat_s        cn68xxp1;
+	struct cvmx_mio_boot_loc_dat_s        cnf71xx;
 };
 typedef union cvmx_mio_boot_loc_dat cvmx_mio_boot_loc_dat_t;
 
@@ -1878,13 +2397,12 @@ typedef union cvmx_mio_boot_loc_dat cvmx_mio_boot_loc_dat_t;
  * MIO_BOOT_PIN_DEFS = MIO Boot Pin Defaults Register
  *
  */
-union cvmx_mio_boot_pin_defs
-{
+union cvmx_mio_boot_pin_defs {
 	uint64_t u64;
-	struct cvmx_mio_boot_pin_defs_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_16_63               : 48;
+	struct cvmx_mio_boot_pin_defs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t user1                        : 16; /**< BOOT_AD [31:16] latched during power up */
 	uint64_t ale                          : 1;  /**< Region 0 default ALE mode */
 	uint64_t width                        : 1;  /**< Region 0 default bus width */
 	uint64_t dmack_p2                     : 1;  /**< boot_dmack[2] default polarity */
@@ -1892,9 +2410,9 @@ union cvmx_mio_boot_pin_defs
 	uint64_t dmack_p0                     : 1;  /**< boot_dmack[0] default polarity */
 	uint64_t term                         : 2;  /**< Selects default driver termination */
 	uint64_t nand                         : 1;  /**< Region 0 is NAND flash */
-	uint64_t reserved_0_7                 : 8;
+	uint64_t user0                        : 8;  /**< BOOT_AD [7:0] latched during power up */
 #else
-	uint64_t reserved_0_7                 : 8;
+	uint64_t user0                        : 8;
 	uint64_t nand                         : 1;
 	uint64_t term                         : 2;
 	uint64_t dmack_p0                     : 1;
@@ -1902,12 +2420,12 @@ union cvmx_mio_boot_pin_defs
 	uint64_t dmack_p2                     : 1;
 	uint64_t width                        : 1;
 	uint64_t ale                          : 1;
-	uint64_t reserved_16_63               : 48;
+	uint64_t user1                        : 16;
+	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
-	struct cvmx_mio_boot_pin_defs_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_pin_defs_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t ale                          : 1;  /**< Region 0 default ALE mode */
 	uint64_t width                        : 1;  /**< Region 0 default bus width */
@@ -1929,9 +2447,8 @@ union cvmx_mio_boot_pin_defs
 	uint64_t reserved_16_63               : 48;
 #endif
 	} cn52xx;
-	struct cvmx_mio_boot_pin_defs_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_pin_defs_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t ale                          : 1;  /**< Region 0 default ALE mode */
 	uint64_t width                        : 1;  /**< Region 0 default bus width */
@@ -1951,20 +2468,47 @@ union cvmx_mio_boot_pin_defs
 	uint64_t reserved_16_63               : 48;
 #endif
 	} cn56xx;
+	struct cvmx_mio_boot_pin_defs_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t user1                        : 16; /**< BOOT_AD [31:16] latched during power up */
+	uint64_t ale                          : 1;  /**< Region 0 default ALE mode */
+	uint64_t width                        : 1;  /**< Region 0 default bus width */
+	uint64_t reserved_13_13               : 1;
+	uint64_t dmack_p1                     : 1;  /**< boot_dmack[1] default polarity */
+	uint64_t dmack_p0                     : 1;  /**< boot_dmack[0] default polarity */
+	uint64_t term                         : 2;  /**< Selects default driver termination */
+	uint64_t nand                         : 1;  /**< Region 0 is NAND flash */
+	uint64_t user0                        : 8;  /**< BOOT_AD [7:0] latched during power up */
+#else
+	uint64_t user0                        : 8;
+	uint64_t nand                         : 1;
+	uint64_t term                         : 2;
+	uint64_t dmack_p0                     : 1;
+	uint64_t dmack_p1                     : 1;
+	uint64_t reserved_13_13               : 1;
+	uint64_t width                        : 1;
+	uint64_t ale                          : 1;
+	uint64_t user1                        : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn61xx;
 	struct cvmx_mio_boot_pin_defs_cn52xx  cn63xx;
 	struct cvmx_mio_boot_pin_defs_cn52xx  cn63xxp1;
+	struct cvmx_mio_boot_pin_defs_cn52xx  cn66xx;
+	struct cvmx_mio_boot_pin_defs_cn52xx  cn68xx;
+	struct cvmx_mio_boot_pin_defs_cn52xx  cn68xxp1;
+	struct cvmx_mio_boot_pin_defs_cn61xx  cnf71xx;
 };
 typedef union cvmx_mio_boot_pin_defs cvmx_mio_boot_pin_defs_t;
 
 /**
  * cvmx_mio_boot_reg_cfg#
  */
-union cvmx_mio_boot_reg_cfgx
-{
+union cvmx_mio_boot_reg_cfgx {
 	uint64_t u64;
-	struct cvmx_mio_boot_reg_cfgx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_reg_cfgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_44_63               : 20;
 	uint64_t dmack                        : 2;  /**< Region X DMACK */
 	uint64_t tim_mult                     : 2;  /**< Region X timing multiplier */
@@ -1994,9 +2538,8 @@ union cvmx_mio_boot_reg_cfgx
 	uint64_t reserved_44_63               : 20;
 #endif
 	} s;
-	struct cvmx_mio_boot_reg_cfgx_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_reg_cfgx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_37_63               : 27;
 	uint64_t sam                          : 1;  /**< Region X SAM mode */
 	uint64_t we_ext                       : 2;  /**< Region X write enable count extension */
@@ -2021,9 +2564,8 @@ union cvmx_mio_boot_reg_cfgx
 #endif
 	} cn30xx;
 	struct cvmx_mio_boot_reg_cfgx_cn30xx  cn31xx;
-	struct cvmx_mio_boot_reg_cfgx_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_reg_cfgx_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t en                           : 1;  /**< Region X enable */
 	uint64_t orbit                        : 1;  /**< Region X or bit */
@@ -2040,9 +2582,8 @@ union cvmx_mio_boot_reg_cfgx
 #endif
 	} cn38xx;
 	struct cvmx_mio_boot_reg_cfgx_cn38xx  cn38xxp2;
-	struct cvmx_mio_boot_reg_cfgx_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_reg_cfgx_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_42_63               : 22;
 	uint64_t tim_mult                     : 2;  /**< Region X timing multiplier */
 	uint64_t rd_dly                       : 3;  /**< Region X read sample delay */
@@ -2076,20 +2617,23 @@ union cvmx_mio_boot_reg_cfgx
 	struct cvmx_mio_boot_reg_cfgx_s       cn56xxp1;
 	struct cvmx_mio_boot_reg_cfgx_cn30xx  cn58xx;
 	struct cvmx_mio_boot_reg_cfgx_cn30xx  cn58xxp1;
+	struct cvmx_mio_boot_reg_cfgx_s       cn61xx;
 	struct cvmx_mio_boot_reg_cfgx_s       cn63xx;
 	struct cvmx_mio_boot_reg_cfgx_s       cn63xxp1;
+	struct cvmx_mio_boot_reg_cfgx_s       cn66xx;
+	struct cvmx_mio_boot_reg_cfgx_s       cn68xx;
+	struct cvmx_mio_boot_reg_cfgx_s       cn68xxp1;
+	struct cvmx_mio_boot_reg_cfgx_s       cnf71xx;
 };
 typedef union cvmx_mio_boot_reg_cfgx cvmx_mio_boot_reg_cfgx_t;
 
 /**
  * cvmx_mio_boot_reg_tim#
  */
-union cvmx_mio_boot_reg_timx
-{
+union cvmx_mio_boot_reg_timx {
 	uint64_t u64;
-	struct cvmx_mio_boot_reg_timx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_reg_timx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t pagem                        : 1;  /**< Region X page mode */
 	uint64_t waitm                        : 1;  /**< Region X wait mode */
 	uint64_t pages                        : 2;  /**< Region X page size */
@@ -2121,9 +2665,8 @@ union cvmx_mio_boot_reg_timx
 	} s;
 	struct cvmx_mio_boot_reg_timx_s       cn30xx;
 	struct cvmx_mio_boot_reg_timx_s       cn31xx;
-	struct cvmx_mio_boot_reg_timx_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_reg_timx_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t pagem                        : 1;  /**< Region X page mode */
 	uint64_t waitm                        : 1;  /**< Region X wait mode */
 	uint64_t pages                        : 2;  /**< Region X page size (NOT IN PASS 1) */
@@ -2161,8 +2704,13 @@ union cvmx_mio_boot_reg_timx
 	struct cvmx_mio_boot_reg_timx_s       cn56xxp1;
 	struct cvmx_mio_boot_reg_timx_s       cn58xx;
 	struct cvmx_mio_boot_reg_timx_s       cn58xxp1;
+	struct cvmx_mio_boot_reg_timx_s       cn61xx;
 	struct cvmx_mio_boot_reg_timx_s       cn63xx;
 	struct cvmx_mio_boot_reg_timx_s       cn63xxp1;
+	struct cvmx_mio_boot_reg_timx_s       cn66xx;
+	struct cvmx_mio_boot_reg_timx_s       cn68xx;
+	struct cvmx_mio_boot_reg_timx_s       cn68xxp1;
+	struct cvmx_mio_boot_reg_timx_s       cnf71xx;
 };
 typedef union cvmx_mio_boot_reg_timx cvmx_mio_boot_reg_timx_t;
 
@@ -2180,12 +2728,10 @@ typedef union cvmx_mio_boot_reg_timx cvmx_mio_boot_reg_timx_t;
  *           accesses have completed.  If set to zero, only perform a DMA access when non-DMA
  *           accesses are not pending.
  */
-union cvmx_mio_boot_thr
-{
+union cvmx_mio_boot_thr {
 	uint64_t u64;
-	struct cvmx_mio_boot_thr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_thr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_22_63               : 42;
 	uint64_t dma_thr                      : 6;  /**< DMA threshold */
 	uint64_t reserved_14_15               : 2;
@@ -2201,9 +2747,8 @@ union cvmx_mio_boot_thr
 	uint64_t reserved_22_63               : 42;
 #endif
 	} s;
-	struct cvmx_mio_boot_thr_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_boot_thr_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t fif_cnt                      : 6;  /**< Current NCB FIFO count */
 	uint64_t reserved_6_7                 : 2;
@@ -2225,24 +2770,670 @@ union cvmx_mio_boot_thr
 	struct cvmx_mio_boot_thr_s            cn56xxp1;
 	struct cvmx_mio_boot_thr_cn30xx       cn58xx;
 	struct cvmx_mio_boot_thr_cn30xx       cn58xxp1;
+	struct cvmx_mio_boot_thr_s            cn61xx;
 	struct cvmx_mio_boot_thr_s            cn63xx;
 	struct cvmx_mio_boot_thr_s            cn63xxp1;
+	struct cvmx_mio_boot_thr_s            cn66xx;
+	struct cvmx_mio_boot_thr_s            cn68xx;
+	struct cvmx_mio_boot_thr_s            cn68xxp1;
+	struct cvmx_mio_boot_thr_s            cnf71xx;
 };
 typedef union cvmx_mio_boot_thr cvmx_mio_boot_thr_t;
 
 /**
+ * cvmx_mio_emm_buf_dat
+ *
+ * MIO_EMM_BUF_DAT = MIO EMMC Data buffer access Register
+ *
+ */
+union cvmx_mio_emm_buf_dat {
+	uint64_t u64;
+	struct cvmx_mio_emm_buf_dat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t dat                          : 64; /**< Direct access to the 1KB data buffer memory.    Address
+                                                         specified by MIO_EMM_BUF_IDX */
+#else
+	uint64_t dat                          : 64;
+#endif
+	} s;
+	struct cvmx_mio_emm_buf_dat_s         cn61xx;
+	struct cvmx_mio_emm_buf_dat_s         cnf71xx;
+};
+typedef union cvmx_mio_emm_buf_dat cvmx_mio_emm_buf_dat_t;
+
+/**
+ * cvmx_mio_emm_buf_idx
+ *
+ * MIO_EMM_BUF_IDX = MIO EMMC Data buffer address Register
+ *
+ */
+union cvmx_mio_emm_buf_idx {
+	uint64_t u64;
+	struct cvmx_mio_emm_buf_idx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_17_63               : 47;
+	uint64_t inc                          : 1;  /**< Automatically advance BUF_SEL/OFFSET after each access to
+                                                         MIO_EMM_BUF_DAT.   Wraps after last offset of last data buffer. */
+	uint64_t reserved_7_15                : 9;
+	uint64_t buf_num                      : 1;  /**< Specify the data buffer for the next access to MIO_EMM_BUF_DAT */
+	uint64_t offset                       : 6;  /**< Specify the 8B data buffer offset for the next access to
+                                                         MIO_EMM_BUF_DAT */
+#else
+	uint64_t offset                       : 6;
+	uint64_t buf_num                      : 1;
+	uint64_t reserved_7_15                : 9;
+	uint64_t inc                          : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_mio_emm_buf_idx_s         cn61xx;
+	struct cvmx_mio_emm_buf_idx_s         cnf71xx;
+};
+typedef union cvmx_mio_emm_buf_idx cvmx_mio_emm_buf_idx_t;
+
+/**
+ * cvmx_mio_emm_cfg
+ *
+ * MIO_EMM_CFG = MIO EMMC Configuration Register
+ *
+ */
+union cvmx_mio_emm_cfg {
+	uint64_t u64;
+	struct cvmx_mio_emm_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_17_63               : 47;
+	uint64_t boot_fail                    : 1;  /**< SW should set BOOT_FAIL when an unrecoverable error occurs
+                                                         while attempt to boot from eMMC or NOR Flash.   When set, the
+                                                         following pattern will be output:
+                                                           BOOT_AD[7:0] pulled up to 1
+                                                           BOOT_CE_N[7:0] driven to 1
+                                                           BOOT_ALE driven to 0
+                                                           BOOT_OE_L driven to 1
+                                                           BOOT_WE_L driven to 1 */
+	uint64_t reserved_4_15                : 12;
+	uint64_t bus_ena                      : 4;  /**< eMMC bus enable mask.
+
+                                                         Setting bit0 of BUS_ENA causes BOOT_CE[1] to become dedicated
+                                                         eMMC bus 0 command (ie. disabling any NOR use)
+
+                                                         Setting bit1 of BUS_ENA causes BOOT_CE[2] to become dedicated
+                                                         eMMC bus 1 command (ie. disabling any NOR use).
+
+                                                         Setting bit2 of BUS_ENA causes BOOT_CE[3] to become dedicated
+                                                         eMMC bus 2 command (ie. disabling any NOR use).
+
+                                                         Setting bit3 of BUS_ENA causes BOOT_CE[4] to become dedicated
+                                                         eMMC bus 3 command (ie. disabling any NOR use).
+
+                                                         Setting any bit of BUS_ENA causes BOOT_CE[5] to become the eMMC
+                                                         clock for both bus0 and bus1. */
+#else
+	uint64_t bus_ena                      : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t boot_fail                    : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_mio_emm_cfg_s             cn61xx;
+	struct cvmx_mio_emm_cfg_s             cnf71xx;
+};
+typedef union cvmx_mio_emm_cfg cvmx_mio_emm_cfg_t;
+
+/**
+ * cvmx_mio_emm_cmd
+ *
+ * MIO_EMM_CMD = MIO EMMC Command Register
+ *
+ */
+union cvmx_mio_emm_cmd {
+	uint64_t u64;
+	struct cvmx_mio_emm_cmd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_62_63               : 2;
+	uint64_t bus_id                       : 2;  /**< Specify the eMMC bus */
+	uint64_t cmd_val                      : 1;  /**< Request valid.  SW writes this bit to a 1.   HW clears it when
+                                                         the operation completes. */
+	uint64_t reserved_56_58               : 3;
+	uint64_t dbuf                         : 1;  /**< Specify the data buffer to be used for a block transfer. */
+	uint64_t offset                       : 6;  /**< Debug only.  Specify the number of 8 byte transfers in the
+                                                         used in the command.  Value is 64-OFFSET.  The block transfer
+                                                         will still start at the first btye in the 512B data buffer.
+                                                         SW must ensure CMD16 has updated the card block length. */
+	uint64_t reserved_43_48               : 6;
+	uint64_t ctype_xor                    : 2;  /**< Reserved. Must be zero */
+	uint64_t rtype_xor                    : 3;  /**< Reserved. Must be zero */
+	uint64_t cmd_idx                      : 6;  /**< eMMC command */
+	uint64_t arg                          : 32; /**< eMMC command argument */
+#else
+	uint64_t arg                          : 32;
+	uint64_t cmd_idx                      : 6;
+	uint64_t rtype_xor                    : 3;
+	uint64_t ctype_xor                    : 2;
+	uint64_t reserved_43_48               : 6;
+	uint64_t offset                       : 6;
+	uint64_t dbuf                         : 1;
+	uint64_t reserved_56_58               : 3;
+	uint64_t cmd_val                      : 1;
+	uint64_t bus_id                       : 2;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} s;
+	struct cvmx_mio_emm_cmd_s             cn61xx;
+	struct cvmx_mio_emm_cmd_s             cnf71xx;
+};
+typedef union cvmx_mio_emm_cmd cvmx_mio_emm_cmd_t;
+
+/**
+ * cvmx_mio_emm_dma
+ *
+ * MIO_EMM_DMA = MIO EMMC DMA config Register
+ *
+ */
+union cvmx_mio_emm_dma {
+	uint64_t u64;
+	struct cvmx_mio_emm_dma_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_62_63               : 2;
+	uint64_t bus_id                       : 2;  /**< Specify the eMMC bus */
+	uint64_t dma_val                      : 1;  /**< SW writes this bit to a 1 to indicate that HW should perform
+                                                         the DMA transfer.   HW clears when DMA operation completes or
+                                                         is terminated. */
+	uint64_t sector                       : 1;  /**< Specify CARD_ADDR and eMMC are using sector (512B) addressing. */
+	uint64_t dat_null                     : 1;  /**< Do not perform any eMMC commands.   A DMA read will return all
+                                                         0s.  A DMA write tosses the data.  In the case of a failure,
+                                                         this can be used to unwind the DMA engine. */
+	uint64_t thres                        : 6;  /**< Number of 8B blocks of data that must exist in the DBUF before
+                                                         the starting the 512B block transfer.  0 indicates to wait for
+                                                         the entire block. */
+	uint64_t rel_wr                       : 1;  /**< Set the reliable write parameter when performing CMD23
+                                                         (SET_BLOCK_COUNT) for a multiple block */
+	uint64_t rw                           : 1;  /**< R/W bit (0 = read, 1 = write) */
+	uint64_t multi                        : 1;  /**< Perform operation using a multiple block command instead of a
+                                                         series of single block commands. */
+	uint64_t block_cnt                    : 16; /**< Number of blocks to read/write.  Hardware decrements the block
+                                                         count after each successful block transfer. */
+	uint64_t card_addr                    : 32; /**< Data address for media =<2GB is a 32bit byte address and data
+                                                         address for media > 2GB is a 32bit sector (512B) address.
+                                                         Hardware advances the card address after each successful block
+                                                         transfer by 512 for byte addressing and by 1 for sector
+                                                         addressing. */
+#else
+	uint64_t card_addr                    : 32;
+	uint64_t block_cnt                    : 16;
+	uint64_t multi                        : 1;
+	uint64_t rw                           : 1;
+	uint64_t rel_wr                       : 1;
+	uint64_t thres                        : 6;
+	uint64_t dat_null                     : 1;
+	uint64_t sector                       : 1;
+	uint64_t dma_val                      : 1;
+	uint64_t bus_id                       : 2;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} s;
+	struct cvmx_mio_emm_dma_s             cn61xx;
+	struct cvmx_mio_emm_dma_s             cnf71xx;
+};
+typedef union cvmx_mio_emm_dma cvmx_mio_emm_dma_t;
+
+/**
+ * cvmx_mio_emm_int
+ *
+ * MIO_EMM_INT = MIO EMMC Interrupt Register
+ *
+ */
+union cvmx_mio_emm_int {
+	uint64_t u64;
+	struct cvmx_mio_emm_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t switch_err                   : 1;  /**< Switch operation encountered an error. */
+	uint64_t switch_done                  : 1;  /**< Switch operation completed successfully */
+	uint64_t dma_err                      : 1;  /**< DMA transfer encountered an error.   See MIO_EMM_RSP. */
+	uint64_t cmd_err                      : 1;  /**< Operation specified by MIO_EMM_CMD encountered an error.  See
+                                                         MIO_EMM_RSP. */
+	uint64_t dma_done                     : 1;  /**< DMA transfer completed successfully */
+	uint64_t cmd_done                     : 1;  /**< Operation specified by MIO_EMM_CMD completed successfully */
+	uint64_t buf_done                     : 1;  /**< The next 512B block transfer of a multi-block transfer has
+                                                         completed. */
+#else
+	uint64_t buf_done                     : 1;
+	uint64_t cmd_done                     : 1;
+	uint64_t dma_done                     : 1;
+	uint64_t cmd_err                      : 1;
+	uint64_t dma_err                      : 1;
+	uint64_t switch_done                  : 1;
+	uint64_t switch_err                   : 1;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_mio_emm_int_s             cn61xx;
+	struct cvmx_mio_emm_int_s             cnf71xx;
+};
+typedef union cvmx_mio_emm_int cvmx_mio_emm_int_t;
+
+/**
+ * cvmx_mio_emm_int_en
+ *
+ * MIO_EMM_INT_EN = MIO EMMC Interrupt enable Register
+ *
+ */
+union cvmx_mio_emm_int_en {
+	uint64_t u64;
+	struct cvmx_mio_emm_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t switch_err                   : 1;  /**< Switch operation encountered an error. */
+	uint64_t switch_done                  : 1;  /**< Switch operation completed. */
+	uint64_t dma_err                      : 1;  /**< DMA transfer encountered an error.   See MIO_EMM_RSP. */
+	uint64_t cmd_err                      : 1;  /**< Operation specified by MIO_EMM_CMD encountered an error.  See
+                                                         MIO_EMM_RSP. */
+	uint64_t dma_done                     : 1;  /**< DMA transfer completed */
+	uint64_t cmd_done                     : 1;  /**< Operation specified by MIO_EMM_CMD completed */
+	uint64_t buf_done                     : 1;  /**< The next 512B block transfer of a multi-block transfer has
+                                                         completed. */
+#else
+	uint64_t buf_done                     : 1;
+	uint64_t cmd_done                     : 1;
+	uint64_t dma_done                     : 1;
+	uint64_t cmd_err                      : 1;
+	uint64_t dma_err                      : 1;
+	uint64_t switch_done                  : 1;
+	uint64_t switch_err                   : 1;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_mio_emm_int_en_s          cn61xx;
+	struct cvmx_mio_emm_int_en_s          cnf71xx;
+};
+typedef union cvmx_mio_emm_int_en cvmx_mio_emm_int_en_t;
+
+/**
+ * cvmx_mio_emm_mode#
+ *
+ * MIO_EMM_MODE = MIO EMMC Operating mode Register
+ *
+ */
+union cvmx_mio_emm_modex {
+	uint64_t u64;
+	struct cvmx_mio_emm_modex_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_49_63               : 15;
+	uint64_t hs_timing                    : 1;  /**< Current high speed timing mode.   Required when CLK frequency
+                                                         higher than 20MHz. */
+	uint64_t reserved_43_47               : 5;
+	uint64_t bus_width                    : 3;  /**< Current card bus mode.  Out of reset, the card is in 1 bit data
+                                                         bus mode.   Select bus width.
+
+                                                         0 - 1 bit data bus (power on)
+                                                         1 - 4 bit data bus
+                                                         2 - 8 bit data bus
+                                                         5 - 4 bit data bus (dual data rate)
+                                                         6 - 8 bit data bus (dual data rate) */
+	uint64_t reserved_36_39               : 4;
+	uint64_t power_class                  : 4;  /**< Out of reset, the card power class is 0, which is the minimum
+                                                         current consumption class for the card.  EXT_CSD bytes
+                                                         [203:200] and [239:238] contain the power class for different
+                                                         BUS_WITDH and CLK frequencies.  Software should write this
+                                                         field with the  4-bit field from the EXT_CSD bytes
+                                                         corresponding to the selected operating mode. */
+	uint64_t clk_hi                       : 16; /**< Current number of sclk cycles to hold the eMMC CLK pin high */
+	uint64_t clk_lo                       : 16; /**< Current number of sclk cycles to hold the eMMC CLK pin low. */
+#else
+	uint64_t clk_lo                       : 16;
+	uint64_t clk_hi                       : 16;
+	uint64_t power_class                  : 4;
+	uint64_t reserved_36_39               : 4;
+	uint64_t bus_width                    : 3;
+	uint64_t reserved_43_47               : 5;
+	uint64_t hs_timing                    : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} s;
+	struct cvmx_mio_emm_modex_s           cn61xx;
+	struct cvmx_mio_emm_modex_s           cnf71xx;
+};
+typedef union cvmx_mio_emm_modex cvmx_mio_emm_modex_t;
+
+/**
+ * cvmx_mio_emm_rca
+ */
+union cvmx_mio_emm_rca {
+	uint64_t u64;
+	struct cvmx_mio_emm_rca_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t card_rca                     : 16; /**< Whenever SW performs CMD7, HW will update CARD_RCA with the
+                                                         relative card address from the MIO_EMM_CMD[ARG] unless the
+                                                         operations encounters an error. */
+#else
+	uint64_t card_rca                     : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_mio_emm_rca_s             cn61xx;
+	struct cvmx_mio_emm_rca_s             cnf71xx;
+};
+typedef union cvmx_mio_emm_rca cvmx_mio_emm_rca_t;
+
+/**
+ * cvmx_mio_emm_rsp_hi
+ *
+ * MIO_EMM_RSP_HI = MIO EMMC Response data high Register
+ *
+ */
+union cvmx_mio_emm_rsp_hi {
+	uint64_t u64;
+	struct cvmx_mio_emm_rsp_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t dat                          : 64; /**< Command response (as per JEDEC eMMC spec)
+
+                                                         RSP_TYPE=1 - DAT[63:0] - 0x0
+                                                         RSP_TYPE=2 - DAT[63:0] - CID[127:64] or CSD[127:64]
+                                                         RSP_TYPE=3 - DAT[63:0] - 0x0
+                                                         RSP_TYPE=4 - DAT[63:0] - 0x0
+                                                         RSP_TYPE=5 - DAT[63:0] - 0x0 */
+#else
+	uint64_t dat                          : 64;
+#endif
+	} s;
+	struct cvmx_mio_emm_rsp_hi_s          cn61xx;
+	struct cvmx_mio_emm_rsp_hi_s          cnf71xx;
+};
+typedef union cvmx_mio_emm_rsp_hi cvmx_mio_emm_rsp_hi_t;
+
+/**
+ * cvmx_mio_emm_rsp_lo
+ *
+ * MIO_EMM_RSP_LO = MIO EMMC Response data low Register
+ *
+ */
+union cvmx_mio_emm_rsp_lo {
+	uint64_t u64;
+	struct cvmx_mio_emm_rsp_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t dat                          : 64; /**< Command response (as per JEDEC eMMC spec)
+
+                                                         RSP_TYPE = 1
+                                                                 DAT[63:46] - 0x0
+                                                                 DAT[45:40] - Command index
+                                                                 DAT[39: 8] - Card status
+                                                                 DAT[ 7: 1] - CRC7
+                                                                 DAT[    0] - End bit
+
+                                                         RSP_TYPE = 2
+                                                                 DAT[63: 1] - CID[63:1] or CSD[63:1] including CRC
+                                                                 DAT[    0] - End bit
+
+                                                         RSP_TYPE = 3
+                                                                 DAT[63:46] - 0x0
+                                                                 DAT[45:40] - Check bits (0x3f)
+                                                                 DAT[39: 8] - OCR register
+                                                                 DAT[ 7: 1] - Check bits (0x7f)
+                                                                 DAT[    0] - End bit
+
+                                                         RSP_TYPE = 4
+                                                                 DAT[63:46] - 0x0
+                                                                 DAT[45:40] - CMD39 ('10111')
+                                                                 DAT[39:24] - RCA[31:16]
+                                                                 DAT[   23] - Status
+                                                                 DAT[22:16] - Register address
+                                                                 DAT[15: 8] - Register contents
+                                                                 DAT[ 7: 1] - CRC7
+                                                                 DAT[    0] - End bit
+
+                                                         RSP_TYPE = 5
+                                                                 DAT[63:46] - 0x0
+                                                                 DAT[45:40] - CMD40 ('10100')
+                                                                 DAT[39:24] - RCA[31:16]
+                                                                 DAT[   23] - Status
+                                                                 DAT[22:16] - Register address
+                                                                 DAT[15: 8] - Not defined.  May be used for IRQ data
+                                                                 DAT[ 7: 1] - CRC7
+                                                                 DAT[    0] - End bit */
+#else
+	uint64_t dat                          : 64;
+#endif
+	} s;
+	struct cvmx_mio_emm_rsp_lo_s          cn61xx;
+	struct cvmx_mio_emm_rsp_lo_s          cnf71xx;
+};
+typedef union cvmx_mio_emm_rsp_lo cvmx_mio_emm_rsp_lo_t;
+
+/**
+ * cvmx_mio_emm_rsp_sts
+ *
+ * MIO_EMM_RSP_STS = MIO EMMC Response status Register
+ *
+ */
+union cvmx_mio_emm_rsp_sts {
+	uint64_t u64;
+	struct cvmx_mio_emm_rsp_sts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_62_63               : 2;
+	uint64_t bus_id                       : 2;  /**< eMMC bus id to which the response status corresponds. */
+	uint64_t cmd_val                      : 1;  /**< Read-only copy of MIO_EMM_CMD[CMD_VAL].  CMD_VAL=1 indicates a
+                                                         direct operation is in progress. */
+	uint64_t switch_val                   : 1;  /**< Read-only copy of MIO_EMM_SWITCH[SWITCH_EXE].   SWITCH_VAL=1
+                                                         indicates a switch operation is in progress. */
+	uint64_t dma_val                      : 1;  /**< Read-only copy of MIO_EMM_DMA[DMA_VAL].   DMA_VAL=1 indicates a
+                                                         DMA operation is in progress. */
+	uint64_t dma_pend                     : 1;  /**< The DMA engine has a pending transfer resulting from an error.
+                                                         SW can resume the transfer by writing MIO_EMM_DMA[DMA_VAL]=1.
+                                                         SW can terminate the transfer by writing MIO_EMM_DMA[DMA_VAL]=1
+                                                         and MIO_EMM_DMA[NULL]=1.   HW will clear DMA_PEND and perform
+                                                         the DMA operation */
+	uint64_t reserved_29_55               : 27;
+	uint64_t dbuf_err                     : 1;  /**< For CMD_TYPE=1, indicates a DMA read data arrived from card
+                                                         without a free DBUF.
+
+                                                         For CMD_TYPE=2, indicates a DBUF underflow occurred during a
+                                                         DMA write.    See MIO_EMM_DMA[THRES]. */
+	uint64_t reserved_24_27               : 4;
+	uint64_t dbuf                         : 1;  /**< DBUF corresponding to the most recently attempted block
+                                                         transfer. */
+	uint64_t blk_timeout                  : 1;  /**< Timeout waiting for read data or 3bit CRC token */
+	uint64_t blk_crc_err                  : 1;  /**< For CMD_TYPE=1, indicates a card read data CRC mismatch.
+                                                         MIO_EMM_RSP_STS[DBUF] indicates the failing data buffer.
+
+                                                         For CMD_TYPE=2, indicates card returned 3-bit CRC status token
+                                                         indicating the card encountered a write data CRC check
+                                                         mismatch.  MIO_EMM_RSP_STS[DBUF] indicates the failing data
+                                                         buffer. */
+	uint64_t rsp_busybit                  : 1;  /**< Debug only.  eMMC protocol utilizes DAT0 as a busy signal
+                                                         during block writes and R1b responses. */
+	uint64_t stp_timeout                  : 1;  /**< Stop transmission response timeout. */
+	uint64_t stp_crc_err                  : 1;  /**< Stop transmission response had a CRC error */
+	uint64_t stp_bad_sts                  : 1;  /**< Stop transmission response had bad status. */
+	uint64_t stp_val                      : 1;  /**< Stop transmission response valid. */
+	uint64_t rsp_timeout                  : 1;  /**< Response timeout */
+	uint64_t rsp_crc_err                  : 1;  /**< Response CRC error */
+	uint64_t rsp_bad_sts                  : 1;  /**< Response bad status */
+	uint64_t rsp_val                      : 1;  /**< Response id.   See MIO_EMM_RSP_HI/LO */
+	uint64_t rsp_type                     : 3;  /**< Indicates the response type. See MIO_EMM_RSP_HI/LO */
+	uint64_t cmd_type                     : 2;  /**< eMMC command type (0=no data, 1=read, 2=write) */
+	uint64_t cmd_idx                      : 6;  /**< eMMC command index most recently attempted */
+	uint64_t cmd_done                     : 1;  /**< eMMC command completed.   Once the command has complete, the
+                                                         status is final and can be examined by SW. */
+#else
+	uint64_t cmd_done                     : 1;
+	uint64_t cmd_idx                      : 6;
+	uint64_t cmd_type                     : 2;
+	uint64_t rsp_type                     : 3;
+	uint64_t rsp_val                      : 1;
+	uint64_t rsp_bad_sts                  : 1;
+	uint64_t rsp_crc_err                  : 1;
+	uint64_t rsp_timeout                  : 1;
+	uint64_t stp_val                      : 1;
+	uint64_t stp_bad_sts                  : 1;
+	uint64_t stp_crc_err                  : 1;
+	uint64_t stp_timeout                  : 1;
+	uint64_t rsp_busybit                  : 1;
+	uint64_t blk_crc_err                  : 1;
+	uint64_t blk_timeout                  : 1;
+	uint64_t dbuf                         : 1;
+	uint64_t reserved_24_27               : 4;
+	uint64_t dbuf_err                     : 1;
+	uint64_t reserved_29_55               : 27;
+	uint64_t dma_pend                     : 1;
+	uint64_t dma_val                      : 1;
+	uint64_t switch_val                   : 1;
+	uint64_t cmd_val                      : 1;
+	uint64_t bus_id                       : 2;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} s;
+	struct cvmx_mio_emm_rsp_sts_s         cn61xx;
+	struct cvmx_mio_emm_rsp_sts_s         cnf71xx;
+};
+typedef union cvmx_mio_emm_rsp_sts cvmx_mio_emm_rsp_sts_t;
+
+/**
+ * cvmx_mio_emm_sample
+ */
+union cvmx_mio_emm_sample {
+	uint64_t u64;
+	struct cvmx_mio_emm_sample_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_26_63               : 38;
+	uint64_t cmd_cnt                      : 10; /**< Number of SCLK cycles before the eMMC clock edge to sample the
+                                                         command pin. */
+	uint64_t reserved_10_15               : 6;
+	uint64_t dat_cnt                      : 10; /**< Number of SCLK cycles before the eMMC clock rising edge to
+                                                         sample the data pin. */
+#else
+	uint64_t dat_cnt                      : 10;
+	uint64_t reserved_10_15               : 6;
+	uint64_t cmd_cnt                      : 10;
+	uint64_t reserved_26_63               : 38;
+#endif
+	} s;
+	struct cvmx_mio_emm_sample_s          cn61xx;
+	struct cvmx_mio_emm_sample_s          cnf71xx;
+};
+typedef union cvmx_mio_emm_sample cvmx_mio_emm_sample_t;
+
+/**
+ * cvmx_mio_emm_sts_mask
+ */
+union cvmx_mio_emm_sts_mask {
+	uint64_t u64;
+	struct cvmx_mio_emm_sts_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t sts_msk                      : 32; /**< Any bit set in STS_MSK causes the corresponding bit in the card
+                                                         status to be considered when computing response bad status. */
+#else
+	uint64_t sts_msk                      : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_mio_emm_sts_mask_s        cn61xx;
+	struct cvmx_mio_emm_sts_mask_s        cnf71xx;
+};
+typedef union cvmx_mio_emm_sts_mask cvmx_mio_emm_sts_mask_t;
+
+/**
+ * cvmx_mio_emm_switch
+ *
+ * MIO_EMM_SWITCH = MIO EMMC Operating mode switch Register
+ *
+ */
+union cvmx_mio_emm_switch {
+	uint64_t u64;
+	struct cvmx_mio_emm_switch_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_62_63               : 2;
+	uint64_t bus_id                       : 2;  /**< Specify the eMMC bus */
+	uint64_t switch_exe                   : 1;  /**< When SWITCH_EXE is 0, the operating modes will be update
+                                                         directly without performing any SWITCH operations.   This
+                                                         allows SW to perform the SWITCH operations manually, then
+                                                         update the HW.
+
+                                                         SW writes this bit to a 1 to indicate that HW should perform
+                                                         the necessary SWITCH operations.   First, the POWER_CLASS
+                                                         switch will be performed.   If it fails, SWITCH_ERR0 will be
+                                                         and the remaining SWITCH operations will not be performed.   If
+                                                         is succeeds, the POWER_CLASS field will be updated and the
+                                                         HS_TIMING switch will be performed.   If it fails, SWITCH_ERR1
+                                                         will be set and the remaining SWITCH operations will not be
+                                                         performed.   If is succeeds, the HS_TIMING field will be
+                                                         updated and the BUS_WITDH switch operation will be performed.
+                                                         If it fails, SWITCH_ERR2 will be set.  If it succeeds, the
+                                                         BUS_WITDH will be updated.
+
+                                                         Changes to CLK_HI and CLK_LO are discarded if any switch error
+                                                         occurs. */
+	uint64_t switch_err0                  : 1;  /**< Error encounter while performing POWER_CLASS switch .   See
+                                                         MIO_EMM_RSP_STS */
+	uint64_t switch_err1                  : 1;  /**< Error encounter while performing HS_TIMING switch .   See
+                                                         MIO_EMM_RSP_STS */
+	uint64_t switch_err2                  : 1;  /**< Error encounter while performing BUS_WIDTH switch .   See
+                                                         MIO_EMM_RSP_STS */
+	uint64_t reserved_49_55               : 7;
+	uint64_t hs_timing                    : 1;  /**< Requested update to HS_TIMING */
+	uint64_t reserved_43_47               : 5;
+	uint64_t bus_width                    : 3;  /**< Requested update to BUS_WIDTH */
+	uint64_t reserved_36_39               : 4;
+	uint64_t power_class                  : 4;  /**< Requested update to POWER_CLASS */
+	uint64_t clk_hi                       : 16; /**< Requested update to CLK_HI */
+	uint64_t clk_lo                       : 16; /**< Requested update to CLK_LO */
+#else
+	uint64_t clk_lo                       : 16;
+	uint64_t clk_hi                       : 16;
+	uint64_t power_class                  : 4;
+	uint64_t reserved_36_39               : 4;
+	uint64_t bus_width                    : 3;
+	uint64_t reserved_43_47               : 5;
+	uint64_t hs_timing                    : 1;
+	uint64_t reserved_49_55               : 7;
+	uint64_t switch_err2                  : 1;
+	uint64_t switch_err1                  : 1;
+	uint64_t switch_err0                  : 1;
+	uint64_t switch_exe                   : 1;
+	uint64_t bus_id                       : 2;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} s;
+	struct cvmx_mio_emm_switch_s          cn61xx;
+	struct cvmx_mio_emm_switch_s          cnf71xx;
+};
+typedef union cvmx_mio_emm_switch cvmx_mio_emm_switch_t;
+
+/**
+ * cvmx_mio_emm_wdog
+ *
+ * MIO_EMM_WDOG = MIO EMMC Watchdog Register
+ *
+ */
+union cvmx_mio_emm_wdog {
+	uint64_t u64;
+	struct cvmx_mio_emm_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_26_63               : 38;
+	uint64_t clk_cnt                      : 26; /**< Number of CLK_CNT cycles to wait for the card to return a
+                                                         response, read data, or the 3-bit CRC status token. */
+#else
+	uint64_t clk_cnt                      : 26;
+	uint64_t reserved_26_63               : 38;
+#endif
+	} s;
+	struct cvmx_mio_emm_wdog_s            cn61xx;
+	struct cvmx_mio_emm_wdog_s            cnf71xx;
+};
+typedef union cvmx_mio_emm_wdog cvmx_mio_emm_wdog_t;
+
+/**
  * cvmx_mio_fus_bnk_dat#
  *
  * Notes:
  * The intial state of MIO_FUS_BNK_DAT* is as if bank6 was just read i.e. DAT* = fus[895:768]
  *
  */
-union cvmx_mio_fus_bnk_datx
-{
+union cvmx_mio_fus_bnk_datx {
 	uint64_t u64;
-	struct cvmx_mio_fus_bnk_datx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_bnk_datx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t dat                          : 64; /**< Efuse bank store
                                                          For reads, the DAT gets the fus bank last read
                                                          For write, the DAT determines which fuses to blow */
@@ -2257,20 +3448,23 @@ union cvmx_mio_fus_bnk_datx
 	struct cvmx_mio_fus_bnk_datx_s        cn56xxp1;
 	struct cvmx_mio_fus_bnk_datx_s        cn58xx;
 	struct cvmx_mio_fus_bnk_datx_s        cn58xxp1;
+	struct cvmx_mio_fus_bnk_datx_s        cn61xx;
 	struct cvmx_mio_fus_bnk_datx_s        cn63xx;
 	struct cvmx_mio_fus_bnk_datx_s        cn63xxp1;
+	struct cvmx_mio_fus_bnk_datx_s        cn66xx;
+	struct cvmx_mio_fus_bnk_datx_s        cn68xx;
+	struct cvmx_mio_fus_bnk_datx_s        cn68xxp1;
+	struct cvmx_mio_fus_bnk_datx_s        cnf71xx;
 };
 typedef union cvmx_mio_fus_bnk_datx cvmx_mio_fus_bnk_datx_t;
 
 /**
  * cvmx_mio_fus_dat0
  */
-union cvmx_mio_fus_dat0
-{
+union cvmx_mio_fus_dat0 {
 	uint64_t u64;
-	struct cvmx_mio_fus_dat0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_dat0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t man_info                     : 32; /**< Fuse information - manufacturing info [31:0] */
 #else
@@ -2289,20 +3483,23 @@ union cvmx_mio_fus_dat0
 	struct cvmx_mio_fus_dat0_s            cn56xxp1;
 	struct cvmx_mio_fus_dat0_s            cn58xx;
 	struct cvmx_mio_fus_dat0_s            cn58xxp1;
+	struct cvmx_mio_fus_dat0_s            cn61xx;
 	struct cvmx_mio_fus_dat0_s            cn63xx;
 	struct cvmx_mio_fus_dat0_s            cn63xxp1;
+	struct cvmx_mio_fus_dat0_s            cn66xx;
+	struct cvmx_mio_fus_dat0_s            cn68xx;
+	struct cvmx_mio_fus_dat0_s            cn68xxp1;
+	struct cvmx_mio_fus_dat0_s            cnf71xx;
 };
 typedef union cvmx_mio_fus_dat0 cvmx_mio_fus_dat0_t;
 
 /**
  * cvmx_mio_fus_dat1
  */
-union cvmx_mio_fus_dat1
-{
+union cvmx_mio_fus_dat1 {
 	uint64_t u64;
-	struct cvmx_mio_fus_dat1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_dat1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t man_info                     : 32; /**< Fuse information - manufacturing info [63:32] */
 #else
@@ -2321,8 +3518,13 @@ union cvmx_mio_fus_dat1
 	struct cvmx_mio_fus_dat1_s            cn56xxp1;
 	struct cvmx_mio_fus_dat1_s            cn58xx;
 	struct cvmx_mio_fus_dat1_s            cn58xxp1;
+	struct cvmx_mio_fus_dat1_s            cn61xx;
 	struct cvmx_mio_fus_dat1_s            cn63xx;
 	struct cvmx_mio_fus_dat1_s            cn63xxp1;
+	struct cvmx_mio_fus_dat1_s            cn66xx;
+	struct cvmx_mio_fus_dat1_s            cn68xx;
+	struct cvmx_mio_fus_dat1_s            cn68xxp1;
+	struct cvmx_mio_fus_dat1_s            cnf71xx;
 };
 typedef union cvmx_mio_fus_dat1 cvmx_mio_fus_dat1_t;
 
@@ -2341,21 +3543,29 @@ typedef union cvmx_mio_fus_dat1 cvmx_mio_fus_dat1_t;
  * Modification to the efuses will not change what the JTAG controller reports
  * for CHIP_ID.
  */
-union cvmx_mio_fus_dat2
-{
+union cvmx_mio_fus_dat2 {
 	uint64_t u64;
-	struct cvmx_mio_fus_dat2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_35_63               : 29;
-	uint64_t dorm_crypto                  : 1;  /**< Fuse information - Dormant Encryption enable */
-	uint64_t fus318                       : 1;  /**< Fuse information - a copy of fuse318 */
+	struct cvmx_mio_fus_dat2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_48_63               : 16;
+	uint64_t fus118                       : 1;  /**< Ignore Authentik disable */
+	uint64_t rom_info                     : 10; /**< Fuse information - ROM info */
+	uint64_t power_limit                  : 2;  /**< Fuse information - Power limit */
+	uint64_t dorm_crypto                  : 1;  /**< Fuse information - See NOCRYPTO */
+	uint64_t fus318                       : 1;  /**< Reserved */
 	uint64_t raid_en                      : 1;  /**< Fuse information - RAID enabled */
 	uint64_t reserved_30_31               : 2;
 	uint64_t nokasu                       : 1;  /**< Fuse information - Disable Kasumi */
 	uint64_t nodfa_cp2                    : 1;  /**< Fuse information - DFA Disable (CP2) */
 	uint64_t nomul                        : 1;  /**< Fuse information - VMUL disable */
-	uint64_t nocrypto                     : 1;  /**< Fuse information - AES/DES/HASH disable */
+	uint64_t nocrypto                     : 1;  /**< Fuse information - DORM_CRYPTO and NOCRYPTO
+                                                         together to select 1 of 4 mutually-exclusive
+                                                         modes:
+
+                                                         DORM_CRYPT=0,NOCRYPTO=0 AES/DES/HASH enabled
+                                                         DORM_CRYPT=0,NOCRYPTO=1 AES/DES/HASH disable
+                                                         DORM_CRYPT=1,NOCRYPTO=0 Dormant Encryption enable
+                                                         DORM_CRYPT=1,NOCRYPTO=1 Authenik mode */
 	uint64_t rst_sht                      : 1;  /**< Fuse information - When set, use short reset count */
 	uint64_t bist_dis                     : 1;  /**< Fuse information - BIST Disable */
 	uint64_t chip_id                      : 8;  /**< Fuse information - CHIP_ID */
@@ -2373,12 +3583,14 @@ union cvmx_mio_fus_dat2
 	uint64_t raid_en                      : 1;
 	uint64_t fus318                       : 1;
 	uint64_t dorm_crypto                  : 1;
-	uint64_t reserved_35_63               : 29;
+	uint64_t power_limit                  : 2;
+	uint64_t rom_info                     : 10;
+	uint64_t fus118                       : 1;
+	uint64_t reserved_48_63               : 16;
 #endif
 	} s;
-	struct cvmx_mio_fus_dat2_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_dat2_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t nodfa_cp2                    : 1;  /**< Fuse information - DFA Disable (CP2) */
 	uint64_t nomul                        : 1;  /**< Fuse information - VMUL disable */
@@ -2405,9 +3617,8 @@ union cvmx_mio_fus_dat2
 	uint64_t reserved_29_63               : 35;
 #endif
 	} cn30xx;
-	struct cvmx_mio_fus_dat2_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_dat2_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t nodfa_cp2                    : 1;  /**< Fuse information - DFA Disable (CP2) */
 	uint64_t nomul                        : 1;  /**< Fuse information - VMUL disable */
@@ -2434,9 +3645,8 @@ union cvmx_mio_fus_dat2
 	uint64_t reserved_29_63               : 35;
 #endif
 	} cn31xx;
-	struct cvmx_mio_fus_dat2_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_dat2_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t nodfa_cp2                    : 1;  /**< Fuse information - DFA Disable (CP2)
                                                          (PASS2 Only) */
@@ -2460,9 +3670,8 @@ union cvmx_mio_fus_dat2
 #endif
 	} cn38xx;
 	struct cvmx_mio_fus_dat2_cn38xx       cn38xxp2;
-	struct cvmx_mio_fus_dat2_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_dat2_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t fus318                       : 1;  /**< Fuse information - a copy of fuse318 */
 	uint64_t raid_en                      : 1;  /**< Fuse information - RAID enabled
@@ -2494,9 +3703,8 @@ union cvmx_mio_fus_dat2
 	uint64_t reserved_34_63               : 30;
 #endif
 	} cn50xx;
-	struct cvmx_mio_fus_dat2_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_dat2_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t fus318                       : 1;  /**< Fuse information - a copy of fuse318 */
 	uint64_t raid_en                      : 1;  /**< Fuse information - RAID enabled */
@@ -2527,9 +3735,8 @@ union cvmx_mio_fus_dat2
 #endif
 	} cn52xx;
 	struct cvmx_mio_fus_dat2_cn52xx       cn52xxp1;
-	struct cvmx_mio_fus_dat2_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_dat2_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t fus318                       : 1;  /**< Fuse information - a copy of fuse318 */
 	uint64_t raid_en                      : 1;  /**< Fuse information - RAID enabled */
@@ -2560,9 +3767,8 @@ union cvmx_mio_fus_dat2
 #endif
 	} cn56xx;
 	struct cvmx_mio_fus_dat2_cn56xx       cn56xxp1;
-	struct cvmx_mio_fus_dat2_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_dat2_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_30_63               : 34;
 	uint64_t nokasu                       : 1;  /**< Fuse information - Disable Kasumi */
 	uint64_t nodfa_cp2                    : 1;  /**< Fuse information - DFA Disable (CP2) */
@@ -2585,12 +3791,53 @@ union cvmx_mio_fus_dat2
 #endif
 	} cn58xx;
 	struct cvmx_mio_fus_dat2_cn58xx       cn58xxp1;
-	struct cvmx_mio_fus_dat2_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_dat2_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_48_63               : 16;
+	uint64_t fus118                       : 1;  /**< Ignore Authentik disable */
+	uint64_t rom_info                     : 10; /**< Fuse information - ROM info */
+	uint64_t power_limit                  : 2;  /**< Fuse information - Power limit */
+	uint64_t dorm_crypto                  : 1;  /**< Fuse information - See NOCRYPTO */
+	uint64_t fus318                       : 1;  /**< Reserved */
+	uint64_t raid_en                      : 1;  /**< Fuse information - RAID enabled */
+	uint64_t reserved_29_31               : 3;
+	uint64_t nodfa_cp2                    : 1;  /**< Fuse information - DFA Disable (CP2) */
+	uint64_t nomul                        : 1;  /**< Fuse information - VMUL disable */
+	uint64_t nocrypto                     : 1;  /**< Fuse information - DORM_CRYPTO and NOCRYPTO
+                                                         together to select 1 of 4 mutually-exclusive
+                                                         modes:
+
+                                                         DORM_CRYPT=0,NOCRYPTO=0 AES/DES/HASH enabled
+                                                         DORM_CRYPT=0,NOCRYPTO=1 AES/DES/HASH disable
+                                                         DORM_CRYPT=1,NOCRYPTO=0 Dormant Encryption enable
+                                                         DORM_CRYPT=1,NOCRYPTO=1 Authenik mode */
+	uint64_t reserved_24_25               : 2;
+	uint64_t chip_id                      : 8;  /**< Fuse information - CHIP_ID */
+	uint64_t reserved_4_15                : 12;
+	uint64_t pp_dis                       : 4;  /**< Fuse information - PP_DISABLES */
+#else
+	uint64_t pp_dis                       : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t chip_id                      : 8;
+	uint64_t reserved_24_25               : 2;
+	uint64_t nocrypto                     : 1;
+	uint64_t nomul                        : 1;
+	uint64_t nodfa_cp2                    : 1;
+	uint64_t reserved_29_31               : 3;
+	uint64_t raid_en                      : 1;
+	uint64_t fus318                       : 1;
+	uint64_t dorm_crypto                  : 1;
+	uint64_t power_limit                  : 2;
+	uint64_t rom_info                     : 10;
+	uint64_t fus118                       : 1;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} cn61xx;
+	struct cvmx_mio_fus_dat2_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_35_63               : 29;
 	uint64_t dorm_crypto                  : 1;  /**< Fuse information - Dormant Encryption enable */
-	uint64_t fus318                       : 1;  /**< Fuse information - a copy of fuse318 */
+	uint64_t fus318                       : 1;  /**< Reserved */
 	uint64_t raid_en                      : 1;  /**< Fuse information - RAID enabled */
 	uint64_t reserved_29_31               : 3;
 	uint64_t nodfa_cp2                    : 1;  /**< Fuse information - DFA Disable (CP2) */
@@ -2616,18 +3863,89 @@ union cvmx_mio_fus_dat2
 #endif
 	} cn63xx;
 	struct cvmx_mio_fus_dat2_cn63xx       cn63xxp1;
+	struct cvmx_mio_fus_dat2_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_48_63               : 16;
+	uint64_t fus118                       : 1;  /**< Ignore Authentik disable */
+	uint64_t rom_info                     : 10; /**< Fuse information - ROM info */
+	uint64_t power_limit                  : 2;  /**< Fuse information - Power limit */
+	uint64_t dorm_crypto                  : 1;  /**< Fuse information - See NOCRYPTO */
+	uint64_t fus318                       : 1;  /**< Reserved */
+	uint64_t raid_en                      : 1;  /**< Fuse information - RAID enabled */
+	uint64_t reserved_29_31               : 3;
+	uint64_t nodfa_cp2                    : 1;  /**< Fuse information - DFA Disable (CP2) */
+	uint64_t nomul                        : 1;  /**< Fuse information - VMUL disable */
+	uint64_t nocrypto                     : 1;  /**< Fuse information - DORM_CRYPTO and NOCRYPTO
+                                                         together to select 1 of 4 mutually-exclusive
+                                                         modes:
+
+                                                         DORM_CRYPT=0,NOCRYPTO=0 AES/DES/HASH enabled
+                                                         DORM_CRYPT=0,NOCRYPTO=1 AES/DES/HASH disable
+                                                         DORM_CRYPT=1,NOCRYPTO=0 Dormant Encryption enable
+                                                         DORM_CRYPT=1,NOCRYPTO=1 Authenik mode */
+	uint64_t reserved_24_25               : 2;
+	uint64_t chip_id                      : 8;  /**< Fuse information - CHIP_ID */
+	uint64_t reserved_10_15               : 6;
+	uint64_t pp_dis                       : 10; /**< Fuse information - PP_DISABLES */
+#else
+	uint64_t pp_dis                       : 10;
+	uint64_t reserved_10_15               : 6;
+	uint64_t chip_id                      : 8;
+	uint64_t reserved_24_25               : 2;
+	uint64_t nocrypto                     : 1;
+	uint64_t nomul                        : 1;
+	uint64_t nodfa_cp2                    : 1;
+	uint64_t reserved_29_31               : 3;
+	uint64_t raid_en                      : 1;
+	uint64_t fus318                       : 1;
+	uint64_t dorm_crypto                  : 1;
+	uint64_t power_limit                  : 2;
+	uint64_t rom_info                     : 10;
+	uint64_t fus118                       : 1;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} cn66xx;
+	struct cvmx_mio_fus_dat2_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_37_63               : 27;
+	uint64_t power_limit                  : 2;  /**< Fuse information - Power limit */
+	uint64_t dorm_crypto                  : 1;  /**< Fuse information - Dormant Encryption enable */
+	uint64_t fus318                       : 1;  /**< Reserved */
+	uint64_t raid_en                      : 1;  /**< Fuse information - RAID enabled */
+	uint64_t reserved_29_31               : 3;
+	uint64_t nodfa_cp2                    : 1;  /**< Fuse information - DFA Disable (CP2) */
+	uint64_t nomul                        : 1;  /**< Fuse information - VMUL disable */
+	uint64_t nocrypto                     : 1;  /**< Fuse information - AES/DES/HASH disable */
+	uint64_t reserved_24_25               : 2;
+	uint64_t chip_id                      : 8;  /**< Fuse information - CHIP_ID */
+	uint64_t reserved_0_15                : 16;
+#else
+	uint64_t reserved_0_15                : 16;
+	uint64_t chip_id                      : 8;
+	uint64_t reserved_24_25               : 2;
+	uint64_t nocrypto                     : 1;
+	uint64_t nomul                        : 1;
+	uint64_t nodfa_cp2                    : 1;
+	uint64_t reserved_29_31               : 3;
+	uint64_t raid_en                      : 1;
+	uint64_t fus318                       : 1;
+	uint64_t dorm_crypto                  : 1;
+	uint64_t power_limit                  : 2;
+	uint64_t reserved_37_63               : 27;
+#endif
+	} cn68xx;
+	struct cvmx_mio_fus_dat2_cn68xx       cn68xxp1;
+	struct cvmx_mio_fus_dat2_cn61xx       cnf71xx;
 };
 typedef union cvmx_mio_fus_dat2 cvmx_mio_fus_dat2_t;
 
 /**
  * cvmx_mio_fus_dat3
  */
-union cvmx_mio_fus_dat3
-{
+union cvmx_mio_fus_dat3 {
 	uint64_t u64;
-	struct cvmx_mio_fus_dat3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_dat3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_58_63               : 6;
 	uint64_t pll_ctl                      : 10; /**< Fuse information - PLL control */
 	uint64_t dfa_info_dte                 : 3;  /**< Fuse information - DFA information (DTE) */
@@ -2668,9 +3986,8 @@ union cvmx_mio_fus_dat3
 	uint64_t reserved_58_63               : 6;
 #endif
 	} s;
-	struct cvmx_mio_fus_dat3_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_dat3_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t pll_div4                     : 1;  /**< Fuse information - PLL DIV4 mode
                                                          (laser fuse only) */
@@ -2696,9 +4013,8 @@ union cvmx_mio_fus_dat3
 	uint64_t reserved_32_63               : 32;
 #endif
 	} cn30xx;
-	struct cvmx_mio_fus_dat3_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_dat3_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t pll_div4                     : 1;  /**< Fuse information - PLL DIV4 mode
                                                          (laser fuse only) */
@@ -2725,9 +4041,8 @@ union cvmx_mio_fus_dat3
 	uint64_t reserved_32_63               : 32;
 #endif
 	} cn31xx;
-	struct cvmx_mio_fus_dat3_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_dat3_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t zip_crip                     : 2;  /**< Fuse information - Zip Cripple
                                                          (PASS3 Only) */
@@ -2756,9 +4071,8 @@ union cvmx_mio_fus_dat3
 	uint64_t reserved_31_63               : 33;
 #endif
 	} cn38xx;
-	struct cvmx_mio_fus_dat3_cn38xxp2
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_dat3_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t bar2_en                      : 1;  /**< Fuse information - BAR2 Enable (when blown '1')
                                                          (PASS2 Only) */
@@ -2791,9 +4105,8 @@ union cvmx_mio_fus_dat3
 	struct cvmx_mio_fus_dat3_cn38xx       cn56xxp1;
 	struct cvmx_mio_fus_dat3_cn38xx       cn58xx;
 	struct cvmx_mio_fus_dat3_cn38xx       cn58xxp1;
-	struct cvmx_mio_fus_dat3_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_dat3_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_58_63               : 6;
 	uint64_t pll_ctl                      : 10; /**< Fuse information - PLL control */
 	uint64_t dfa_info_dte                 : 3;  /**< Fuse information - DFA information (DTE) */
@@ -2832,20 +4145,26 @@ union cvmx_mio_fus_dat3
 	uint64_t pll_ctl                      : 10;
 	uint64_t reserved_58_63               : 6;
 #endif
-	} cn63xx;
-	struct cvmx_mio_fus_dat3_cn63xx       cn63xxp1;
+	} cn61xx;
+	struct cvmx_mio_fus_dat3_cn61xx       cn63xx;
+	struct cvmx_mio_fus_dat3_cn61xx       cn63xxp1;
+	struct cvmx_mio_fus_dat3_cn61xx       cn66xx;
+	struct cvmx_mio_fus_dat3_cn61xx       cn68xx;
+	struct cvmx_mio_fus_dat3_cn61xx       cn68xxp1;
+	struct cvmx_mio_fus_dat3_cn61xx       cnf71xx;
 };
 typedef union cvmx_mio_fus_dat3 cvmx_mio_fus_dat3_t;
 
 /**
  * cvmx_mio_fus_ema
+ *
+ * DON'T PUT IN HRM*
+ *
  */
-union cvmx_mio_fus_ema
-{
+union cvmx_mio_fus_ema {
 	uint64_t u64;
-	struct cvmx_mio_fus_ema_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_ema_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t eff_ema                      : 3;  /**< Reserved */
 	uint64_t reserved_3_3                 : 1;
@@ -2862,9 +4181,8 @@ union cvmx_mio_fus_ema
 	struct cvmx_mio_fus_ema_s             cn52xxp1;
 	struct cvmx_mio_fus_ema_s             cn56xx;
 	struct cvmx_mio_fus_ema_s             cn56xxp1;
-	struct cvmx_mio_fus_ema_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_ema_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t ema                          : 2;  /**< EMA Settings */
 #else
@@ -2873,20 +4191,23 @@ union cvmx_mio_fus_ema
 #endif
 	} cn58xx;
 	struct cvmx_mio_fus_ema_cn58xx        cn58xxp1;
+	struct cvmx_mio_fus_ema_s             cn61xx;
 	struct cvmx_mio_fus_ema_s             cn63xx;
 	struct cvmx_mio_fus_ema_s             cn63xxp1;
+	struct cvmx_mio_fus_ema_s             cn66xx;
+	struct cvmx_mio_fus_ema_s             cn68xx;
+	struct cvmx_mio_fus_ema_s             cn68xxp1;
+	struct cvmx_mio_fus_ema_s             cnf71xx;
 };
 typedef union cvmx_mio_fus_ema cvmx_mio_fus_ema_t;
 
 /**
  * cvmx_mio_fus_pdf
  */
-union cvmx_mio_fus_pdf
-{
+union cvmx_mio_fus_pdf {
 	uint64_t u64;
-	struct cvmx_mio_fus_pdf_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_pdf_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t pdf                          : 64; /**< Fuse information - Product Definition Field */
 #else
 	uint64_t pdf                          : 64;
@@ -2898,8 +4219,13 @@ union cvmx_mio_fus_pdf
 	struct cvmx_mio_fus_pdf_s             cn56xx;
 	struct cvmx_mio_fus_pdf_s             cn56xxp1;
 	struct cvmx_mio_fus_pdf_s             cn58xx;
+	struct cvmx_mio_fus_pdf_s             cn61xx;
 	struct cvmx_mio_fus_pdf_s             cn63xx;
 	struct cvmx_mio_fus_pdf_s             cn63xxp1;
+	struct cvmx_mio_fus_pdf_s             cn66xx;
+	struct cvmx_mio_fus_pdf_s             cn68xx;
+	struct cvmx_mio_fus_pdf_s             cn68xxp1;
+	struct cvmx_mio_fus_pdf_s             cnf71xx;
 };
 typedef union cvmx_mio_fus_pdf cvmx_mio_fus_pdf_t;
 
@@ -2915,19 +4241,22 @@ typedef union cvmx_mio_fus_pdf cvmx_mio_fus_pdf_t;
  * the pnr clkout select.  The pnr clkout postscaler should remain under reset for at least 10
  * ref clocks after the pnr clkout select changes.
  */
-union cvmx_mio_fus_pll
-{
+union cvmx_mio_fus_pll {
 	uint64_t u64;
-	struct cvmx_mio_fus_pll_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_8_63                : 56;
+	struct cvmx_mio_fus_pll_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_48_63               : 16;
+	uint64_t rclk_align_r                 : 8;  /**< RCLK right alignment settings */
+	uint64_t rclk_align_l                 : 8;  /**< RCLK left alignment settings */
+	uint64_t reserved_8_31                : 24;
 	uint64_t c_cout_rst                   : 1;  /**< Core clkout postscaler reset */
 	uint64_t c_cout_sel                   : 2;  /**< Core clkout select
-                                                         (0=RCLK,1=PS output,2=PLL output, 3=GND)         |   $PR */
+                                                         0=RCLK,1=PS output,2=PLL output,3=undivided RCLK |   $PR
+                                                         (***Pass 1.x: 3=GND) */
 	uint64_t pnr_cout_rst                 : 1;  /**< PNR  clkout postscaler reset */
 	uint64_t pnr_cout_sel                 : 2;  /**< PNR  clkout select
-                                                         (0=SCLK,1=PS output,2=PLL output, 3=GND)         |   $PR */
+                                                         0=SCLK,1=PS output,2=PLL output,3=undivided RCLK |   $PR
+                                                         (***Pass 1.x: 3=GND) */
 	uint64_t rfslip                       : 1;  /**< Reserved */
 	uint64_t fbslip                       : 1;  /**< Reserved */
 #else
@@ -2937,12 +4266,14 @@ union cvmx_mio_fus_pll
 	uint64_t pnr_cout_rst                 : 1;
 	uint64_t c_cout_sel                   : 2;
 	uint64_t c_cout_rst                   : 1;
-	uint64_t reserved_8_63                : 56;
+	uint64_t reserved_8_31                : 24;
+	uint64_t rclk_align_l                 : 8;
+	uint64_t rclk_align_r                 : 8;
+	uint64_t reserved_48_63               : 16;
 #endif
 	} s;
-	struct cvmx_mio_fus_pll_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_pll_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t rfslip                       : 1;  /**< PLL reference clock slip */
 	uint64_t fbslip                       : 1;  /**< PLL feedback clock slip */
@@ -2958,8 +4289,35 @@ union cvmx_mio_fus_pll
 	struct cvmx_mio_fus_pll_cn50xx        cn56xxp1;
 	struct cvmx_mio_fus_pll_cn50xx        cn58xx;
 	struct cvmx_mio_fus_pll_cn50xx        cn58xxp1;
-	struct cvmx_mio_fus_pll_s             cn63xx;
-	struct cvmx_mio_fus_pll_s             cn63xxp1;
+	struct cvmx_mio_fus_pll_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_8_63                : 56;
+	uint64_t c_cout_rst                   : 1;  /**< Core clkout postscaler reset */
+	uint64_t c_cout_sel                   : 2;  /**< Core clkout select
+                                                         0=RCLK,1=PS output,2=PLL output,3=undivided RCLK |   $PR
+                                                         (***Pass 1.x: 3=GND) */
+	uint64_t pnr_cout_rst                 : 1;  /**< PNR  clkout postscaler reset */
+	uint64_t pnr_cout_sel                 : 2;  /**< PNR  clkout select
+                                                         0=SCLK,1=PS output,2=PLL output,3=undivided RCLK |   $PR
+                                                         (***Pass 1.x: 3=GND) */
+	uint64_t rfslip                       : 1;  /**< Reserved */
+	uint64_t fbslip                       : 1;  /**< Reserved */
+#else
+	uint64_t fbslip                       : 1;
+	uint64_t rfslip                       : 1;
+	uint64_t pnr_cout_sel                 : 2;
+	uint64_t pnr_cout_rst                 : 1;
+	uint64_t c_cout_sel                   : 2;
+	uint64_t c_cout_rst                   : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} cn61xx;
+	struct cvmx_mio_fus_pll_cn61xx        cn63xx;
+	struct cvmx_mio_fus_pll_cn61xx        cn63xxp1;
+	struct cvmx_mio_fus_pll_cn61xx        cn66xx;
+	struct cvmx_mio_fus_pll_s             cn68xx;
+	struct cvmx_mio_fus_pll_s             cn68xxp1;
+	struct cvmx_mio_fus_pll_cn61xx        cnf71xx;
 };
 typedef union cvmx_mio_fus_pll cvmx_mio_fus_pll_t;
 
@@ -2982,12 +4340,10 @@ typedef union cvmx_mio_fus_pll cvmx_mio_fus_pll_t;
  * chip will behave as though the fuses were actually blown.  A cold reset restores
  * the actual fuse valuse.
  */
-union cvmx_mio_fus_prog
-{
+union cvmx_mio_fus_prog {
 	uint64_t u64;
-	struct cvmx_mio_fus_prog_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_prog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t soft                         : 1;  /**< When set with PROG, causes only the local storeage
                                                          to change.  Will not really blow any fuses.  HW
@@ -3001,9 +4357,8 @@ union cvmx_mio_fus_prog
 	uint64_t reserved_2_63                : 62;
 #endif
 	} s;
-	struct cvmx_mio_fus_prog_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_prog_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t prog                         : 1;  /**< Blow the fuse
                                                          SW will set PROG, hold it for 10us, then clear it */
@@ -3022,8 +4377,13 @@ union cvmx_mio_fus_prog
 	struct cvmx_mio_fus_prog_cn30xx       cn56xxp1;
 	struct cvmx_mio_fus_prog_cn30xx       cn58xx;
 	struct cvmx_mio_fus_prog_cn30xx       cn58xxp1;
+	struct cvmx_mio_fus_prog_s            cn61xx;
 	struct cvmx_mio_fus_prog_s            cn63xx;
 	struct cvmx_mio_fus_prog_s            cn63xxp1;
+	struct cvmx_mio_fus_prog_s            cn66xx;
+	struct cvmx_mio_fus_prog_s            cn68xx;
+	struct cvmx_mio_fus_prog_s            cn68xxp1;
+	struct cvmx_mio_fus_prog_s            cnf71xx;
 };
 typedef union cvmx_mio_fus_prog cvmx_mio_fus_prog_t;
 
@@ -3043,12 +4403,10 @@ typedef union cvmx_mio_fus_prog cvmx_mio_fus_prog_t;
  *
  * The reset values are for IFB fuses for ref_clk of 100MHZ
  */
-union cvmx_mio_fus_prog_times
-{
+union cvmx_mio_fus_prog_times {
 	uint64_t u64;
-	struct cvmx_mio_fus_prog_times_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_prog_times_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_35_63               : 29;
 	uint64_t vgate_pin                    : 1;  /**< efuse vgate pin (L6G) */
 	uint64_t fsrc_pin                     : 1;  /**< efuse fsource pin (L6G) */
@@ -3069,9 +4427,8 @@ union cvmx_mio_fus_prog_times
 	uint64_t reserved_35_63               : 29;
 #endif
 	} s;
-	struct cvmx_mio_fus_prog_times_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_prog_times_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_33_63               : 31;
 	uint64_t prog_pin                     : 1;  /**< efuse program pin */
 	uint64_t out                          : 8;  /**< efuse timing param (ref_clks to delay 10ns) */
@@ -3093,9 +4450,8 @@ union cvmx_mio_fus_prog_times
 	struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1;
 	struct cvmx_mio_fus_prog_times_cn50xx cn58xx;
 	struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1;
-	struct cvmx_mio_fus_prog_times_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_prog_times_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_35_63               : 29;
 	uint64_t vgate_pin                    : 1;  /**< efuse vgate pin (L6G) */
 	uint64_t fsrc_pin                     : 1;  /**< efuse fsource pin (L6G) */
@@ -3135,8 +4491,13 @@ union cvmx_mio_fus_prog_times
 	uint64_t vgate_pin                    : 1;
 	uint64_t reserved_35_63               : 29;
 #endif
-	} cn63xx;
-	struct cvmx_mio_fus_prog_times_cn63xx cn63xxp1;
+	} cn61xx;
+	struct cvmx_mio_fus_prog_times_cn61xx cn63xx;
+	struct cvmx_mio_fus_prog_times_cn61xx cn63xxp1;
+	struct cvmx_mio_fus_prog_times_cn61xx cn66xx;
+	struct cvmx_mio_fus_prog_times_cn61xx cn68xx;
+	struct cvmx_mio_fus_prog_times_cn61xx cn68xxp1;
+	struct cvmx_mio_fus_prog_times_cn61xx cnf71xx;
 };
 typedef union cvmx_mio_fus_prog_times cvmx_mio_fus_prog_times_t;
 
@@ -3151,12 +4512,10 @@ typedef union cvmx_mio_fus_prog_times cvmx_mio_fus_prog_times_t;
  * MIO_FUS_BNK_DATX which contains all 128 fuses in the bank associated in
  * ADDR.
  */
-union cvmx_mio_fus_rcmd
-{
+union cvmx_mio_fus_rcmd {
 	uint64_t u64;
-	struct cvmx_mio_fus_rcmd_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_rcmd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t dat                          : 8;  /**< 8bits of fuse data */
 	uint64_t reserved_13_15               : 3;
@@ -3177,9 +4536,8 @@ union cvmx_mio_fus_rcmd
 	uint64_t reserved_24_63               : 40;
 #endif
 	} s;
-	struct cvmx_mio_fus_rcmd_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_rcmd_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t dat                          : 8;  /**< 8bits of fuse data */
 	uint64_t reserved_13_15               : 3;
@@ -3212,8 +4570,13 @@ union cvmx_mio_fus_rcmd
 	struct cvmx_mio_fus_rcmd_s            cn56xxp1;
 	struct cvmx_mio_fus_rcmd_cn30xx       cn58xx;
 	struct cvmx_mio_fus_rcmd_cn30xx       cn58xxp1;
+	struct cvmx_mio_fus_rcmd_s            cn61xx;
 	struct cvmx_mio_fus_rcmd_s            cn63xx;
 	struct cvmx_mio_fus_rcmd_s            cn63xxp1;
+	struct cvmx_mio_fus_rcmd_s            cn66xx;
+	struct cvmx_mio_fus_rcmd_s            cn68xx;
+	struct cvmx_mio_fus_rcmd_s            cn68xxp1;
+	struct cvmx_mio_fus_rcmd_s            cnf71xx;
 };
 typedef union cvmx_mio_fus_rcmd cvmx_mio_fus_rcmd_t;
 
@@ -3225,7 +4588,6 @@ typedef union cvmx_mio_fus_rcmd cvmx_mio_fus_rcmd_t;
  * L6G fuses are 1792 to 2047
  *
  * The reset values are for IFB fuses for refclk up to 100MHZ when core PLL is enagaged
- * The reset values are for IFB fuses for refclk up to 500MHZ when core PLL is not enagaged
  *
  * If any of the formulas above result in a value less than zero, the corresponding
  * timing parameter should be set to zero.
@@ -3236,12 +4598,10 @@ typedef union cvmx_mio_fus_rcmd cvmx_mio_fus_rcmd_t;
  *
  * This register should not be written while MIO_FUS_RCMD[PEND]=1.
  */
-union cvmx_mio_fus_read_times
-{
+union cvmx_mio_fus_read_times {
 	uint64_t u64;
-	struct cvmx_mio_fus_read_times_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_read_times_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_26_63               : 38;
 	uint64_t sch                          : 4;  /**< Hold CS for (SCH+1) refclks after FSET desserts
 
@@ -3286,20 +4646,23 @@ union cvmx_mio_fus_read_times
 	uint64_t reserved_26_63               : 38;
 #endif
 	} s;
+	struct cvmx_mio_fus_read_times_s      cn61xx;
 	struct cvmx_mio_fus_read_times_s      cn63xx;
 	struct cvmx_mio_fus_read_times_s      cn63xxp1;
+	struct cvmx_mio_fus_read_times_s      cn66xx;
+	struct cvmx_mio_fus_read_times_s      cn68xx;
+	struct cvmx_mio_fus_read_times_s      cn68xxp1;
+	struct cvmx_mio_fus_read_times_s      cnf71xx;
 };
 typedef union cvmx_mio_fus_read_times cvmx_mio_fus_read_times_t;
 
 /**
  * cvmx_mio_fus_repair_res0
  */
-union cvmx_mio_fus_repair_res0
-{
+union cvmx_mio_fus_repair_res0 {
 	uint64_t u64;
-	struct cvmx_mio_fus_repair_res0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_repair_res0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_55_63               : 9;
 	uint64_t too_many                     : 1;  /**< Too many defects */
 	uint64_t repair2                      : 18; /**< BISR Results */
@@ -3313,20 +4676,23 @@ union cvmx_mio_fus_repair_res0
 	uint64_t reserved_55_63               : 9;
 #endif
 	} s;
+	struct cvmx_mio_fus_repair_res0_s     cn61xx;
 	struct cvmx_mio_fus_repair_res0_s     cn63xx;
 	struct cvmx_mio_fus_repair_res0_s     cn63xxp1;
+	struct cvmx_mio_fus_repair_res0_s     cn66xx;
+	struct cvmx_mio_fus_repair_res0_s     cn68xx;
+	struct cvmx_mio_fus_repair_res0_s     cn68xxp1;
+	struct cvmx_mio_fus_repair_res0_s     cnf71xx;
 };
 typedef union cvmx_mio_fus_repair_res0 cvmx_mio_fus_repair_res0_t;
 
 /**
  * cvmx_mio_fus_repair_res1
  */
-union cvmx_mio_fus_repair_res1
-{
+union cvmx_mio_fus_repair_res1 {
 	uint64_t u64;
-	struct cvmx_mio_fus_repair_res1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_repair_res1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_54_63               : 10;
 	uint64_t repair5                      : 18; /**< BISR Results */
 	uint64_t repair4                      : 18; /**< BISR Results */
@@ -3338,20 +4704,23 @@ union cvmx_mio_fus_repair_res1
 	uint64_t reserved_54_63               : 10;
 #endif
 	} s;
+	struct cvmx_mio_fus_repair_res1_s     cn61xx;
 	struct cvmx_mio_fus_repair_res1_s     cn63xx;
 	struct cvmx_mio_fus_repair_res1_s     cn63xxp1;
+	struct cvmx_mio_fus_repair_res1_s     cn66xx;
+	struct cvmx_mio_fus_repair_res1_s     cn68xx;
+	struct cvmx_mio_fus_repair_res1_s     cn68xxp1;
+	struct cvmx_mio_fus_repair_res1_s     cnf71xx;
 };
 typedef union cvmx_mio_fus_repair_res1 cvmx_mio_fus_repair_res1_t;
 
 /**
  * cvmx_mio_fus_repair_res2
  */
-union cvmx_mio_fus_repair_res2
-{
+union cvmx_mio_fus_repair_res2 {
 	uint64_t u64;
-	struct cvmx_mio_fus_repair_res2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_repair_res2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t repair6                      : 18; /**< BISR Results */
 #else
@@ -3359,24 +4728,26 @@ union cvmx_mio_fus_repair_res2
 	uint64_t reserved_18_63               : 46;
 #endif
 	} s;
+	struct cvmx_mio_fus_repair_res2_s     cn61xx;
 	struct cvmx_mio_fus_repair_res2_s     cn63xx;
 	struct cvmx_mio_fus_repair_res2_s     cn63xxp1;
+	struct cvmx_mio_fus_repair_res2_s     cn66xx;
+	struct cvmx_mio_fus_repair_res2_s     cn68xx;
+	struct cvmx_mio_fus_repair_res2_s     cn68xxp1;
+	struct cvmx_mio_fus_repair_res2_s     cnf71xx;
 };
 typedef union cvmx_mio_fus_repair_res2 cvmx_mio_fus_repair_res2_t;
 
 /**
  * cvmx_mio_fus_spr_repair_res
  *
- * Notes:
- * Pass3 Only
+ * DON'T PUT IN HRM*
  *
  */
-union cvmx_mio_fus_spr_repair_res
-{
+union cvmx_mio_fus_spr_repair_res {
 	uint64_t u64;
-	struct cvmx_mio_fus_spr_repair_res_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_spr_repair_res_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_42_63               : 22;
 	uint64_t repair2                      : 14; /**< Reserved (see  MIO_FUS_REPAIR_RES*) */
 	uint64_t repair1                      : 14; /**< Reserved (see  MIO_FUS_REPAIR_RES*) */
@@ -3398,24 +4769,26 @@ union cvmx_mio_fus_spr_repair_res
 	struct cvmx_mio_fus_spr_repair_res_s  cn56xxp1;
 	struct cvmx_mio_fus_spr_repair_res_s  cn58xx;
 	struct cvmx_mio_fus_spr_repair_res_s  cn58xxp1;
+	struct cvmx_mio_fus_spr_repair_res_s  cn61xx;
 	struct cvmx_mio_fus_spr_repair_res_s  cn63xx;
 	struct cvmx_mio_fus_spr_repair_res_s  cn63xxp1;
+	struct cvmx_mio_fus_spr_repair_res_s  cn66xx;
+	struct cvmx_mio_fus_spr_repair_res_s  cn68xx;
+	struct cvmx_mio_fus_spr_repair_res_s  cn68xxp1;
+	struct cvmx_mio_fus_spr_repair_res_s  cnf71xx;
 };
 typedef union cvmx_mio_fus_spr_repair_res cvmx_mio_fus_spr_repair_res_t;
 
 /**
  * cvmx_mio_fus_spr_repair_sum
  *
- * Notes:
- * Pass3 Only
+ * DON'T PUT IN HRM*
  *
  */
-union cvmx_mio_fus_spr_repair_sum
-{
+union cvmx_mio_fus_spr_repair_sum {
 	uint64_t u64;
-	struct cvmx_mio_fus_spr_repair_sum_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_spr_repair_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t too_many                     : 1;  /**< Reserved (see  MIO_FUS_REPAIR_RES*) */
 #else
@@ -3433,20 +4806,70 @@ union cvmx_mio_fus_spr_repair_sum
 	struct cvmx_mio_fus_spr_repair_sum_s  cn56xxp1;
 	struct cvmx_mio_fus_spr_repair_sum_s  cn58xx;
 	struct cvmx_mio_fus_spr_repair_sum_s  cn58xxp1;
+	struct cvmx_mio_fus_spr_repair_sum_s  cn61xx;
 	struct cvmx_mio_fus_spr_repair_sum_s  cn63xx;
 	struct cvmx_mio_fus_spr_repair_sum_s  cn63xxp1;
+	struct cvmx_mio_fus_spr_repair_sum_s  cn66xx;
+	struct cvmx_mio_fus_spr_repair_sum_s  cn68xx;
+	struct cvmx_mio_fus_spr_repair_sum_s  cn68xxp1;
+	struct cvmx_mio_fus_spr_repair_sum_s  cnf71xx;
 };
 typedef union cvmx_mio_fus_spr_repair_sum cvmx_mio_fus_spr_repair_sum_t;
 
 /**
+ * cvmx_mio_fus_tgg
+ *
+ * Notes:
+ * The TGG fuses are fuses[831:768].  The valid bit (TGG[63]) is fuse[831].
+ *
+ */
+union cvmx_mio_fus_tgg {
+	uint64_t u64;
+	struct cvmx_mio_fus_tgg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t val                          : 1;  /**< Out of reset, VAL will return the TGG[63] fuse.
+                                                         Software may write this CSR bit to zero (to hide
+                                                         the value of the TGG fuses).  Software cannot write
+                                                         the valid bit to a one, so it is not possible to
+                                                         read  the value of the TGG fuses after the valid
+                                                         bit is clear.
+
+                                                         It is never possible to read the value of the TGG
+                                                         fuses directly (ie. the only way to read the value
+                                                         of the TGG fuses is via the MIO_FUS_TGG CSR.)
+
+                                                         Whenever the fuse corresponding to the valid bit
+                                                         (ie. TGG[63]) is blown, it is not possible to blow
+                                                         the other 63 TGG fuses.  (ie. only when the TGG[63]
+                                                         fuse is not blown, the other 63 TGG fuses can be
+                                                         blown.  The TGG[63] fuse is the one and only fuse
+                                                         lockdown bit for the other 63 fuses TGG fuses.  No
+                                                         other fuse lockdown bits can prevent blowing the 63
+                                                         fuses. */
+	uint64_t dat                          : 63; /**< Whenever VAL is clear, DAT will always read as
+                                                         zero, regardless of the value of the TGG[62:0]
+                                                         fuses.
+
+                                                         Whenever VAL is set, DAT will match the value of
+                                                         other 63 TGG fuses (ie. TGG[62:0]) */
+#else
+	uint64_t dat                          : 63;
+	uint64_t val                          : 1;
+#endif
+	} s;
+	struct cvmx_mio_fus_tgg_s             cn61xx;
+	struct cvmx_mio_fus_tgg_s             cn66xx;
+	struct cvmx_mio_fus_tgg_s             cnf71xx;
+};
+typedef union cvmx_mio_fus_tgg cvmx_mio_fus_tgg_t;
+
+/**
  * cvmx_mio_fus_unlock
  */
-union cvmx_mio_fus_unlock
-{
+union cvmx_mio_fus_unlock {
 	uint64_t u64;
-	struct cvmx_mio_fus_unlock_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_unlock_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t key                          : 24; /**< When set to the typical value, allows SW to
                                                          program the efuses */
@@ -3463,12 +4886,10 @@ typedef union cvmx_mio_fus_unlock cvmx_mio_fus_unlock_t;
 /**
  * cvmx_mio_fus_wadr
  */
-union cvmx_mio_fus_wadr
-{
+union cvmx_mio_fus_wadr {
 	uint64_t u64;
-	struct cvmx_mio_fus_wadr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_wadr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t addr                         : 10; /**< Which of the banks of 128 fuses to blow */
 #else
@@ -3480,9 +4901,8 @@ union cvmx_mio_fus_wadr
 	struct cvmx_mio_fus_wadr_s            cn31xx;
 	struct cvmx_mio_fus_wadr_s            cn38xx;
 	struct cvmx_mio_fus_wadr_s            cn38xxp2;
-	struct cvmx_mio_fus_wadr_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_wadr_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t addr                         : 2;  /**< Which of the four banks of 256 fuses to blow */
 #else
@@ -3490,9 +4910,8 @@ union cvmx_mio_fus_wadr
 	uint64_t reserved_2_63                : 62;
 #endif
 	} cn50xx;
-	struct cvmx_mio_fus_wadr_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_wadr_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t addr                         : 3;  /**< Which of the four banks of 256 fuses to blow */
 #else
@@ -3505,17 +4924,21 @@ union cvmx_mio_fus_wadr
 	struct cvmx_mio_fus_wadr_cn52xx       cn56xxp1;
 	struct cvmx_mio_fus_wadr_cn50xx       cn58xx;
 	struct cvmx_mio_fus_wadr_cn50xx       cn58xxp1;
-	struct cvmx_mio_fus_wadr_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_fus_wadr_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t addr                         : 4;  /**< Which of the banks of 128 fuses to blow */
 #else
 	uint64_t addr                         : 4;
 	uint64_t reserved_4_63                : 60;
 #endif
-	} cn63xx;
-	struct cvmx_mio_fus_wadr_cn63xx       cn63xxp1;
+	} cn61xx;
+	struct cvmx_mio_fus_wadr_cn61xx       cn63xx;
+	struct cvmx_mio_fus_wadr_cn61xx       cn63xxp1;
+	struct cvmx_mio_fus_wadr_cn61xx       cn66xx;
+	struct cvmx_mio_fus_wadr_cn61xx       cn68xx;
+	struct cvmx_mio_fus_wadr_cn61xx       cn68xxp1;
+	struct cvmx_mio_fus_wadr_cn61xx       cnf71xx;
 };
 typedef union cvmx_mio_fus_wadr cvmx_mio_fus_wadr_t;
 
@@ -3525,12 +4948,10 @@ typedef union cvmx_mio_fus_wadr cvmx_mio_fus_wadr_t;
  * MIO_GPIO_COMP = MIO GPIO Compensation Register
  *
  */
-union cvmx_mio_gpio_comp
-{
+union cvmx_mio_gpio_comp {
 	uint64_t u64;
-	struct cvmx_mio_gpio_comp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_gpio_comp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t pctl                         : 6;  /**< GPIO bus PCTL */
 	uint64_t nctl                         : 6;  /**< GPIO bus NCTL */
@@ -3540,8 +4961,13 @@ union cvmx_mio_gpio_comp
 	uint64_t reserved_12_63               : 52;
 #endif
 	} s;
+	struct cvmx_mio_gpio_comp_s           cn61xx;
 	struct cvmx_mio_gpio_comp_s           cn63xx;
 	struct cvmx_mio_gpio_comp_s           cn63xxp1;
+	struct cvmx_mio_gpio_comp_s           cn66xx;
+	struct cvmx_mio_gpio_comp_s           cn68xx;
+	struct cvmx_mio_gpio_comp_s           cn68xxp1;
+	struct cvmx_mio_gpio_comp_s           cnf71xx;
 };
 typedef union cvmx_mio_gpio_comp cvmx_mio_gpio_comp_t;
 
@@ -3554,12 +4980,10 @@ typedef union cvmx_mio_gpio_comp cvmx_mio_gpio_comp_t;
  *
  * ADR must be 64 bit aligned.
  */
-union cvmx_mio_ndf_dma_cfg
-{
+union cvmx_mio_ndf_dma_cfg {
 	uint64_t u64;
-	struct cvmx_mio_ndf_dma_cfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_ndf_dma_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t en                           : 1;  /**< DMA Engine enable */
 	uint64_t rw                           : 1;  /**< DMA Engine R/W bit (0 = read, 1 = write) */
 	uint64_t clr                          : 1;  /**< DMA Engine clear EN on device terminated burst */
@@ -3584,8 +5008,13 @@ union cvmx_mio_ndf_dma_cfg
 #endif
 	} s;
 	struct cvmx_mio_ndf_dma_cfg_s         cn52xx;
+	struct cvmx_mio_ndf_dma_cfg_s         cn61xx;
 	struct cvmx_mio_ndf_dma_cfg_s         cn63xx;
 	struct cvmx_mio_ndf_dma_cfg_s         cn63xxp1;
+	struct cvmx_mio_ndf_dma_cfg_s         cn66xx;
+	struct cvmx_mio_ndf_dma_cfg_s         cn68xx;
+	struct cvmx_mio_ndf_dma_cfg_s         cn68xxp1;
+	struct cvmx_mio_ndf_dma_cfg_s         cnf71xx;
 };
 typedef union cvmx_mio_ndf_dma_cfg cvmx_mio_ndf_dma_cfg_t;
 
@@ -3595,12 +5024,10 @@ typedef union cvmx_mio_ndf_dma_cfg cvmx_mio_ndf_dma_cfg_t;
  * MIO_NDF_DMA_INT = MIO NAND Flash DMA Interrupt Register
  *
  */
-union cvmx_mio_ndf_dma_int
-{
+union cvmx_mio_ndf_dma_int {
 	uint64_t u64;
-	struct cvmx_mio_ndf_dma_int_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_ndf_dma_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t done                         : 1;  /**< DMA Engine request completion interrupt */
 #else
@@ -3609,8 +5036,13 @@ union cvmx_mio_ndf_dma_int
 #endif
 	} s;
 	struct cvmx_mio_ndf_dma_int_s         cn52xx;
+	struct cvmx_mio_ndf_dma_int_s         cn61xx;
 	struct cvmx_mio_ndf_dma_int_s         cn63xx;
 	struct cvmx_mio_ndf_dma_int_s         cn63xxp1;
+	struct cvmx_mio_ndf_dma_int_s         cn66xx;
+	struct cvmx_mio_ndf_dma_int_s         cn68xx;
+	struct cvmx_mio_ndf_dma_int_s         cn68xxp1;
+	struct cvmx_mio_ndf_dma_int_s         cnf71xx;
 };
 typedef union cvmx_mio_ndf_dma_int cvmx_mio_ndf_dma_int_t;
 
@@ -3620,12 +5052,10 @@ typedef union cvmx_mio_ndf_dma_int cvmx_mio_ndf_dma_int_t;
  * MIO_NDF_DMA_INT_EN = MIO NAND Flash DMA Interrupt Enable Register
  *
  */
-union cvmx_mio_ndf_dma_int_en
-{
+union cvmx_mio_ndf_dma_int_en {
 	uint64_t u64;
-	struct cvmx_mio_ndf_dma_int_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_ndf_dma_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t done                         : 1;  /**< DMA Engine request completion interrupt enable */
 #else
@@ -3634,20 +5064,23 @@ union cvmx_mio_ndf_dma_int_en
 #endif
 	} s;
 	struct cvmx_mio_ndf_dma_int_en_s      cn52xx;
+	struct cvmx_mio_ndf_dma_int_en_s      cn61xx;
 	struct cvmx_mio_ndf_dma_int_en_s      cn63xx;
 	struct cvmx_mio_ndf_dma_int_en_s      cn63xxp1;
+	struct cvmx_mio_ndf_dma_int_en_s      cn66xx;
+	struct cvmx_mio_ndf_dma_int_en_s      cn68xx;
+	struct cvmx_mio_ndf_dma_int_en_s      cn68xxp1;
+	struct cvmx_mio_ndf_dma_int_en_s      cnf71xx;
 };
 typedef union cvmx_mio_ndf_dma_int_en cvmx_mio_ndf_dma_int_en_t;
 
 /**
  * cvmx_mio_pll_ctl
  */
-union cvmx_mio_pll_ctl
-{
+union cvmx_mio_pll_ctl {
 	uint64_t u64;
-	struct cvmx_mio_pll_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_pll_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t bw_ctl                       : 5;  /**< Core PLL bandwidth control */
 #else
@@ -3663,12 +5096,10 @@ typedef union cvmx_mio_pll_ctl cvmx_mio_pll_ctl_t;
 /**
  * cvmx_mio_pll_setting
  */
-union cvmx_mio_pll_setting
-{
+union cvmx_mio_pll_setting {
 	uint64_t u64;
-	struct cvmx_mio_pll_setting_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_pll_setting_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t setting                      : 17; /**< Core PLL setting */
 #else
@@ -3682,17 +5113,213 @@ union cvmx_mio_pll_setting
 typedef union cvmx_mio_pll_setting cvmx_mio_pll_setting_t;
 
 /**
+ * cvmx_mio_ptp_ckout_hi_incr
+ *
+ * MIO_PTP_CKOUT_HI_INCR = PTP Clock Out Hi Increment
+ *
+ */
+union cvmx_mio_ptp_ckout_hi_incr {
+	uint64_t u64;
+	struct cvmx_mio_ptp_ckout_hi_incr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t nanosec                      : 32; /**< Nanoseconds */
+	uint64_t frnanosec                    : 32; /**< Fractions of Nanoseconds */
+#else
+	uint64_t frnanosec                    : 32;
+	uint64_t nanosec                      : 32;
+#endif
+	} s;
+	struct cvmx_mio_ptp_ckout_hi_incr_s   cn61xx;
+	struct cvmx_mio_ptp_ckout_hi_incr_s   cn66xx;
+	struct cvmx_mio_ptp_ckout_hi_incr_s   cn68xx;
+	struct cvmx_mio_ptp_ckout_hi_incr_s   cnf71xx;
+};
+typedef union cvmx_mio_ptp_ckout_hi_incr cvmx_mio_ptp_ckout_hi_incr_t;
+
+/**
+ * cvmx_mio_ptp_ckout_lo_incr
+ *
+ * MIO_PTP_CKOUT_LO_INCR = PTP Clock Out Lo Increment
+ *
+ */
+union cvmx_mio_ptp_ckout_lo_incr {
+	uint64_t u64;
+	struct cvmx_mio_ptp_ckout_lo_incr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t nanosec                      : 32; /**< Nanoseconds */
+	uint64_t frnanosec                    : 32; /**< Fractions of Nanoseconds */
+#else
+	uint64_t frnanosec                    : 32;
+	uint64_t nanosec                      : 32;
+#endif
+	} s;
+	struct cvmx_mio_ptp_ckout_lo_incr_s   cn61xx;
+	struct cvmx_mio_ptp_ckout_lo_incr_s   cn66xx;
+	struct cvmx_mio_ptp_ckout_lo_incr_s   cn68xx;
+	struct cvmx_mio_ptp_ckout_lo_incr_s   cnf71xx;
+};
+typedef union cvmx_mio_ptp_ckout_lo_incr cvmx_mio_ptp_ckout_lo_incr_t;
+
+/**
+ * cvmx_mio_ptp_ckout_thresh_hi
+ *
+ * MIO_PTP_CKOUT_THRESH_HI = Hi bytes of PTP Clock Out
+ *
+ * Writes to MIO_PTP_CKOUT_THRESH_HI also clear MIO_PTP_CKOUT_THRESH_LO. To update all 96 bits, write MIO_PTP_CKOUT_THRESH_HI followed
+ * by MIO_PTP_CKOUT_THRESH_LO
+ */
+union cvmx_mio_ptp_ckout_thresh_hi {
+	uint64_t u64;
+	struct cvmx_mio_ptp_ckout_thresh_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t nanosec                      : 64; /**< Nanoseconds */
+#else
+	uint64_t nanosec                      : 64;
+#endif
+	} s;
+	struct cvmx_mio_ptp_ckout_thresh_hi_s cn61xx;
+	struct cvmx_mio_ptp_ckout_thresh_hi_s cn66xx;
+	struct cvmx_mio_ptp_ckout_thresh_hi_s cn68xx;
+	struct cvmx_mio_ptp_ckout_thresh_hi_s cnf71xx;
+};
+typedef union cvmx_mio_ptp_ckout_thresh_hi cvmx_mio_ptp_ckout_thresh_hi_t;
+
+/**
+ * cvmx_mio_ptp_ckout_thresh_lo
+ *
+ * MIO_PTP_CKOUT_THRESH_LO = Lo bytes of PTP Clock Out
+ *
+ */
+union cvmx_mio_ptp_ckout_thresh_lo {
+	uint64_t u64;
+	struct cvmx_mio_ptp_ckout_thresh_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t frnanosec                    : 32; /**< Fractions of Nanoseconds */
+#else
+	uint64_t frnanosec                    : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_mio_ptp_ckout_thresh_lo_s cn61xx;
+	struct cvmx_mio_ptp_ckout_thresh_lo_s cn66xx;
+	struct cvmx_mio_ptp_ckout_thresh_lo_s cn68xx;
+	struct cvmx_mio_ptp_ckout_thresh_lo_s cnf71xx;
+};
+typedef union cvmx_mio_ptp_ckout_thresh_lo cvmx_mio_ptp_ckout_thresh_lo_t;
+
+/**
  * cvmx_mio_ptp_clock_cfg
  *
  * MIO_PTP_CLOCK_CFG = Configuration
  *
  */
-union cvmx_mio_ptp_clock_cfg
-{
+union cvmx_mio_ptp_clock_cfg {
 	uint64_t u64;
-	struct cvmx_mio_ptp_clock_cfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_ptp_clock_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_42_63               : 22;
+	uint64_t pps                          : 1;  /**< PTP PPS Output
+                                                         reflects ptp__pps after PPS_INV inverter */
+	uint64_t ckout                        : 1;  /**< PTP Clock Output
+                                                         reflects ptp__ckout after CKOUT_INV inverter */
+	uint64_t ext_clk_edge                 : 2;  /**< External Clock input edge
+                                                         00 = rising edge
+                                                         01 = falling edge
+                                                         10 = both rising & falling edge
+                                                         11 = reserved */
+	uint64_t ckout_out4                   : 1;  /**< Destination for PTP Clock Out output
+                                                         See CKOUT_OUT */
+	uint64_t pps_out                      : 5;  /**< Destination for PTP PPS output to GPIO
+                                                         0-19 : GPIO[PPS_OUT[4:0]]
+                                                         - 20:30: Reserved
+                                                         31   : Disabled
+                                                         This should be different from CKOUT_OUT */
+	uint64_t pps_inv                      : 1;  /**< Invert PTP PPS
+                                                         0 = don't invert
+                                                         1 = invert */
+	uint64_t pps_en                       : 1;  /**< Enable PTP PPS */
+	uint64_t ckout_out                    : 4;  /**< Destination for PTP Clock Out output to GPIO
+                                                         0-19 : GPIO[[CKOUT_OUT4,CKOUT_OUT[3:0]]]
+                                                         - 20:30: Reserved
+                                                         31   : Disabled
+                                                         This should be different from PPS_OUT */
+	uint64_t ckout_inv                    : 1;  /**< Invert PTP Clock Out
+                                                         0 = don't invert
+                                                         1 = invert */
+	uint64_t ckout_en                     : 1;  /**< Enable PTP Clock Out */
+	uint64_t evcnt_in                     : 6;  /**< Source for event counter input
+                                                         0x00-0x0f : GPIO[EVCNT_IN[3:0]]
+                                                         0x20      : GPIO[16]
+                                                         0x21      : GPIO[17]
+                                                         0x22      : GPIO[18]
+                                                         0x23      : GPIO[19]
+                                                         0x10      : QLM0_REF_CLK
+                                                         0x11      : QLM1_REF_CLK
+                                                         0x18      : RF_MCLK (PHY pin)
+                                                         0x12-0x17 : Reserved
+                                                         0x19-0x1f : Reserved
+                                                         0x24-0x3f : Reserved */
+	uint64_t evcnt_edge                   : 1;  /**< Event counter input edge
+                                                         0 = falling edge
+                                                         1 = rising edge */
+	uint64_t evcnt_en                     : 1;  /**< Enable event counter */
+	uint64_t tstmp_in                     : 6;  /**< Source for timestamp input
+                                                         0x00-0x0f : GPIO[TSTMP_IN[3:0]]
+                                                         0x20      : GPIO[16]
+                                                         0x21      : GPIO[17]
+                                                         0x22      : GPIO[18]
+                                                         0x23      : GPIO[19]
+                                                         0x10      : QLM0_REF_CLK
+                                                         0x11      : QLM1_REF_CLK
+                                                         0x18      : RF_MCLK (PHY pin)
+                                                         0x12-0x17 : Reserved
+                                                         0x19-0x1f : Reserved
+                                                         0x24-0x3f : Reserved */
+	uint64_t tstmp_edge                   : 1;  /**< External timestamp input edge
+                                                         0 = falling edge
+                                                         1 = rising edge */
+	uint64_t tstmp_en                     : 1;  /**< Enable external timestamp */
+	uint64_t ext_clk_in                   : 6;  /**< Source for external clock
+                                                         0x00-0x0f : GPIO[EXT_CLK_IN[3:0]]
+                                                         0x20      : GPIO[16]
+                                                         0x21      : GPIO[17]
+                                                         0x22      : GPIO[18]
+                                                         0x23      : GPIO[19]
+                                                         0x10      : QLM0_REF_CLK
+                                                         0x11      : QLM1_REF_CLK
+                                                         0x18      : RF_MCLK (PHY pin)
+                                                         0x12-0x17 : Reserved
+                                                         0x19-0x1f : Reserved
+                                                         0x24-0x3f : Reserved */
+	uint64_t ext_clk_en                   : 1;  /**< Use external clock */
+	uint64_t ptp_en                       : 1;  /**< Enable PTP Module */
+#else
+	uint64_t ptp_en                       : 1;
+	uint64_t ext_clk_en                   : 1;
+	uint64_t ext_clk_in                   : 6;
+	uint64_t tstmp_en                     : 1;
+	uint64_t tstmp_edge                   : 1;
+	uint64_t tstmp_in                     : 6;
+	uint64_t evcnt_en                     : 1;
+	uint64_t evcnt_edge                   : 1;
+	uint64_t evcnt_in                     : 6;
+	uint64_t ckout_en                     : 1;
+	uint64_t ckout_inv                    : 1;
+	uint64_t ckout_out                    : 4;
+	uint64_t pps_en                       : 1;
+	uint64_t pps_inv                      : 1;
+	uint64_t pps_out                      : 5;
+	uint64_t ckout_out4                   : 1;
+	uint64_t ext_clk_edge                 : 2;
+	uint64_t ckout                        : 1;
+	uint64_t pps                          : 1;
+	uint64_t reserved_42_63               : 22;
+#endif
+	} s;
+	struct cvmx_mio_ptp_clock_cfg_s       cn61xx;
+	struct cvmx_mio_ptp_clock_cfg_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t evcnt_in                     : 6;  /**< Source for event counter input
                                                          0x00-0x0f : GPIO[EVCNT_IN[3:0]]
@@ -3734,9 +5361,100 @@ union cvmx_mio_ptp_clock_cfg
 	uint64_t evcnt_in                     : 6;
 	uint64_t reserved_24_63               : 40;
 #endif
-	} s;
-	struct cvmx_mio_ptp_clock_cfg_s       cn63xx;
-	struct cvmx_mio_ptp_clock_cfg_s       cn63xxp1;
+	} cn63xx;
+	struct cvmx_mio_ptp_clock_cfg_cn63xx  cn63xxp1;
+	struct cvmx_mio_ptp_clock_cfg_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_40_63               : 24;
+	uint64_t ext_clk_edge                 : 2;  /**< External Clock input edge
+                                                         00 = rising edge
+                                                         01 = falling edge
+                                                         10 = both rising & falling edge
+                                                         11 = reserved */
+	uint64_t ckout_out4                   : 1;  /**< Destination for PTP Clock Out output
+                                                         0-19 : GPIO[[CKOUT_OUT4,CKOUT_OUT[3:0]]]
+                                                         This should be different from PPS_OUT */
+	uint64_t pps_out                      : 5;  /**< Destination for PTP PPS output
+                                                         0-19 : GPIO[PPS_OUT[4:0]]
+                                                         This should be different from CKOUT_OUT */
+	uint64_t pps_inv                      : 1;  /**< Invert PTP PPS
+                                                         0 = don't invert
+                                                         1 = invert */
+	uint64_t pps_en                       : 1;  /**< Enable PTP PPS */
+	uint64_t ckout_out                    : 4;  /**< Destination for PTP Clock Out output
+                                                         0-19 : GPIO[[CKOUT_OUT4,CKOUT_OUT[3:0]]]
+                                                         This should be different from PPS_OUT */
+	uint64_t ckout_inv                    : 1;  /**< Invert PTP Clock Out
+                                                         0 = don't invert
+                                                         1 = invert */
+	uint64_t ckout_en                     : 1;  /**< Enable PTP Clock Out */
+	uint64_t evcnt_in                     : 6;  /**< Source for event counter input
+                                                         0x00-0x0f : GPIO[EVCNT_IN[3:0]]
+                                                         0x20      : GPIO[16]
+                                                         0x21      : GPIO[17]
+                                                         0x22      : GPIO[18]
+                                                         0x23      : GPIO[19]
+                                                         0x10      : QLM0_REF_CLK
+                                                         0x11      : QLM1_REF_CLK
+                                                         0x12      : QLM2_REF_CLK
+                                                         0x13-0x1f : Reserved
+                                                         0x24-0x3f : Reserved */
+	uint64_t evcnt_edge                   : 1;  /**< Event counter input edge
+                                                         0 = falling edge
+                                                         1 = rising edge */
+	uint64_t evcnt_en                     : 1;  /**< Enable event counter */
+	uint64_t tstmp_in                     : 6;  /**< Source for timestamp input
+                                                         0x00-0x0f : GPIO[TSTMP_IN[3:0]]
+                                                         0x20      : GPIO[16]
+                                                         0x21      : GPIO[17]
+                                                         0x22      : GPIO[18]
+                                                         0x23      : GPIO[19]
+                                                         0x10      : QLM0_REF_CLK
+                                                         0x11      : QLM1_REF_CLK
+                                                         0x12      : QLM2_REF_CLK
+                                                         0x13-0x1f : Reserved
+                                                         0x24-0x3f : Reserved */
+	uint64_t tstmp_edge                   : 1;  /**< External timestamp input edge
+                                                         0 = falling edge
+                                                         1 = rising edge */
+	uint64_t tstmp_en                     : 1;  /**< Enable external timestamp */
+	uint64_t ext_clk_in                   : 6;  /**< Source for external clock
+                                                         0x00-0x0f : GPIO[EXT_CLK_IN[3:0]]
+                                                         0x20      : GPIO[16]
+                                                         0x21      : GPIO[17]
+                                                         0x22      : GPIO[18]
+                                                         0x23      : GPIO[19]
+                                                         0x10      : QLM0_REF_CLK
+                                                         0x11      : QLM1_REF_CLK
+                                                         0x12      : QLM2_REF_CLK
+                                                         0x13-0x1f : Reserved
+                                                         0x24-0x3f : Reserved */
+	uint64_t ext_clk_en                   : 1;  /**< Use external clock */
+	uint64_t ptp_en                       : 1;  /**< Enable PTP Module */
+#else
+	uint64_t ptp_en                       : 1;
+	uint64_t ext_clk_en                   : 1;
+	uint64_t ext_clk_in                   : 6;
+	uint64_t tstmp_en                     : 1;
+	uint64_t tstmp_edge                   : 1;
+	uint64_t tstmp_in                     : 6;
+	uint64_t evcnt_en                     : 1;
+	uint64_t evcnt_edge                   : 1;
+	uint64_t evcnt_in                     : 6;
+	uint64_t ckout_en                     : 1;
+	uint64_t ckout_inv                    : 1;
+	uint64_t ckout_out                    : 4;
+	uint64_t pps_en                       : 1;
+	uint64_t pps_inv                      : 1;
+	uint64_t pps_out                      : 5;
+	uint64_t ckout_out4                   : 1;
+	uint64_t ext_clk_edge                 : 2;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} cn66xx;
+	struct cvmx_mio_ptp_clock_cfg_s       cn68xx;
+	struct cvmx_mio_ptp_clock_cfg_cn63xx  cn68xxp1;
+	struct cvmx_mio_ptp_clock_cfg_s       cnf71xx;
 };
 typedef union cvmx_mio_ptp_clock_cfg cvmx_mio_ptp_clock_cfg_t;
 
@@ -3746,12 +5464,10 @@ typedef union cvmx_mio_ptp_clock_cfg cvmx_mio_ptp_clock_cfg_t;
  * MIO_PTP_CLOCK_COMP = Compensator
  *
  */
-union cvmx_mio_ptp_clock_comp
-{
+union cvmx_mio_ptp_clock_comp {
 	uint64_t u64;
-	struct cvmx_mio_ptp_clock_comp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_ptp_clock_comp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t nanosec                      : 32; /**< Nanoseconds */
 	uint64_t frnanosec                    : 32; /**< Fractions of Nanoseconds */
 #else
@@ -3759,8 +5475,13 @@ union cvmx_mio_ptp_clock_comp
 	uint64_t nanosec                      : 32;
 #endif
 	} s;
+	struct cvmx_mio_ptp_clock_comp_s      cn61xx;
 	struct cvmx_mio_ptp_clock_comp_s      cn63xx;
 	struct cvmx_mio_ptp_clock_comp_s      cn63xxp1;
+	struct cvmx_mio_ptp_clock_comp_s      cn66xx;
+	struct cvmx_mio_ptp_clock_comp_s      cn68xx;
+	struct cvmx_mio_ptp_clock_comp_s      cn68xxp1;
+	struct cvmx_mio_ptp_clock_comp_s      cnf71xx;
 };
 typedef union cvmx_mio_ptp_clock_comp cvmx_mio_ptp_clock_comp_t;
 
@@ -3772,19 +5493,22 @@ typedef union cvmx_mio_ptp_clock_comp cvmx_mio_ptp_clock_comp_t;
  * Writes to MIO_PTP_CLOCK_HI also clear MIO_PTP_CLOCK_LO. To update all 96 bits, write MIO_PTP_CLOCK_HI followed
  * by MIO_PTP_CLOCK_LO
  */
-union cvmx_mio_ptp_clock_hi
-{
+union cvmx_mio_ptp_clock_hi {
 	uint64_t u64;
-	struct cvmx_mio_ptp_clock_hi_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_ptp_clock_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t nanosec                      : 64; /**< Nanoseconds */
 #else
 	uint64_t nanosec                      : 64;
 #endif
 	} s;
+	struct cvmx_mio_ptp_clock_hi_s        cn61xx;
 	struct cvmx_mio_ptp_clock_hi_s        cn63xx;
 	struct cvmx_mio_ptp_clock_hi_s        cn63xxp1;
+	struct cvmx_mio_ptp_clock_hi_s        cn66xx;
+	struct cvmx_mio_ptp_clock_hi_s        cn68xx;
+	struct cvmx_mio_ptp_clock_hi_s        cn68xxp1;
+	struct cvmx_mio_ptp_clock_hi_s        cnf71xx;
 };
 typedef union cvmx_mio_ptp_clock_hi cvmx_mio_ptp_clock_hi_t;
 
@@ -3794,12 +5518,10 @@ typedef union cvmx_mio_ptp_clock_hi cvmx_mio_ptp_clock_hi_t;
  * MIO_PTP_CLOCK_LO = Lo bytes of CLOCK
  *
  */
-union cvmx_mio_ptp_clock_lo
-{
+union cvmx_mio_ptp_clock_lo {
 	uint64_t u64;
-	struct cvmx_mio_ptp_clock_lo_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_ptp_clock_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t frnanosec                    : 32; /**< Fractions of Nanoseconds */
 #else
@@ -3807,8 +5529,13 @@ union cvmx_mio_ptp_clock_lo
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_mio_ptp_clock_lo_s        cn61xx;
 	struct cvmx_mio_ptp_clock_lo_s        cn63xx;
 	struct cvmx_mio_ptp_clock_lo_s        cn63xxp1;
+	struct cvmx_mio_ptp_clock_lo_s        cn66xx;
+	struct cvmx_mio_ptp_clock_lo_s        cn68xx;
+	struct cvmx_mio_ptp_clock_lo_s        cn68xxp1;
+	struct cvmx_mio_ptp_clock_lo_s        cnf71xx;
 };
 typedef union cvmx_mio_ptp_clock_lo cvmx_mio_ptp_clock_lo_t;
 
@@ -3821,53 +5548,554 @@ typedef union cvmx_mio_ptp_clock_lo cvmx_mio_ptp_clock_lo_t;
  * 1 for every MIO_PTP_CLOCK_CFG[EVCNT_EDGE] edge of MIO_PTP_CLOCK_CFG[EVCNT_IN]. When register equals
  * 0, an interrupt gets gerated
  */
-union cvmx_mio_ptp_evt_cnt
-{
+union cvmx_mio_ptp_evt_cnt {
 	uint64_t u64;
-	struct cvmx_mio_ptp_evt_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_ptp_evt_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t cntr                         : 64; /**< Nanoseconds */
 #else
 	uint64_t cntr                         : 64;
 #endif
 	} s;
+	struct cvmx_mio_ptp_evt_cnt_s         cn61xx;
 	struct cvmx_mio_ptp_evt_cnt_s         cn63xx;
 	struct cvmx_mio_ptp_evt_cnt_s         cn63xxp1;
+	struct cvmx_mio_ptp_evt_cnt_s         cn66xx;
+	struct cvmx_mio_ptp_evt_cnt_s         cn68xx;
+	struct cvmx_mio_ptp_evt_cnt_s         cn68xxp1;
+	struct cvmx_mio_ptp_evt_cnt_s         cnf71xx;
 };
 typedef union cvmx_mio_ptp_evt_cnt cvmx_mio_ptp_evt_cnt_t;
 
 /**
+ * cvmx_mio_ptp_phy_1pps_in
+ *
+ * MIO_PTP_PHY_1PPS_IN = PHY 1PPS input mux selection
+ *
+ */
+union cvmx_mio_ptp_phy_1pps_in {
+	uint64_t u64;
+	struct cvmx_mio_ptp_phy_1pps_in_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_5_63                : 59;
+	uint64_t sel                          : 5;  /**< Source for PHY 1pps input signal
+                                                         0-19 : GPIO[SEL[4:0]], for AGPS_1PPS
+                                                         24   : PPS_OUT (Enabled by PPS_EN and PPS_INV,
+                                                                reflects ptp_pps after PPS_INV inverter)
+                                                         - 20-23: Reserved
+                                                         - 25-30: Reserved
+                                                         31   : Disabled */
+#else
+	uint64_t sel                          : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_mio_ptp_phy_1pps_in_s     cnf71xx;
+};
+typedef union cvmx_mio_ptp_phy_1pps_in cvmx_mio_ptp_phy_1pps_in_t;
+
+/**
+ * cvmx_mio_ptp_pps_hi_incr
+ *
+ * MIO_PTP_PPS_HI_INCR = PTP PPS Hi Increment
+ *
+ */
+union cvmx_mio_ptp_pps_hi_incr {
+	uint64_t u64;
+	struct cvmx_mio_ptp_pps_hi_incr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t nanosec                      : 32; /**< Nanoseconds */
+	uint64_t frnanosec                    : 32; /**< Fractions of Nanoseconds */
+#else
+	uint64_t frnanosec                    : 32;
+	uint64_t nanosec                      : 32;
+#endif
+	} s;
+	struct cvmx_mio_ptp_pps_hi_incr_s     cn61xx;
+	struct cvmx_mio_ptp_pps_hi_incr_s     cn66xx;
+	struct cvmx_mio_ptp_pps_hi_incr_s     cn68xx;
+	struct cvmx_mio_ptp_pps_hi_incr_s     cnf71xx;
+};
+typedef union cvmx_mio_ptp_pps_hi_incr cvmx_mio_ptp_pps_hi_incr_t;
+
+/**
+ * cvmx_mio_ptp_pps_lo_incr
+ *
+ * MIO_PTP_PPS_LO_INCR = PTP PPS Lo Increment
+ *
+ */
+union cvmx_mio_ptp_pps_lo_incr {
+	uint64_t u64;
+	struct cvmx_mio_ptp_pps_lo_incr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t nanosec                      : 32; /**< Nanoseconds */
+	uint64_t frnanosec                    : 32; /**< Fractions of Nanoseconds */
+#else
+	uint64_t frnanosec                    : 32;
+	uint64_t nanosec                      : 32;
+#endif
+	} s;
+	struct cvmx_mio_ptp_pps_lo_incr_s     cn61xx;
+	struct cvmx_mio_ptp_pps_lo_incr_s     cn66xx;
+	struct cvmx_mio_ptp_pps_lo_incr_s     cn68xx;
+	struct cvmx_mio_ptp_pps_lo_incr_s     cnf71xx;
+};
+typedef union cvmx_mio_ptp_pps_lo_incr cvmx_mio_ptp_pps_lo_incr_t;
+
+/**
+ * cvmx_mio_ptp_pps_thresh_hi
+ *
+ * MIO_PTP_PPS_THRESH_HI = Hi bytes of PTP PPS
+ *
+ * Writes to MIO_PTP_PPS_THRESH_HI also clear MIO_PTP_PPS_THRESH_LO. To update all 96 bits, write MIO_PTP_PPS_THRESH_HI followed
+ * by MIO_PTP_PPS_THRESH_LO
+ */
+union cvmx_mio_ptp_pps_thresh_hi {
+	uint64_t u64;
+	struct cvmx_mio_ptp_pps_thresh_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t nanosec                      : 64; /**< Nanoseconds */
+#else
+	uint64_t nanosec                      : 64;
+#endif
+	} s;
+	struct cvmx_mio_ptp_pps_thresh_hi_s   cn61xx;
+	struct cvmx_mio_ptp_pps_thresh_hi_s   cn66xx;
+	struct cvmx_mio_ptp_pps_thresh_hi_s   cn68xx;
+	struct cvmx_mio_ptp_pps_thresh_hi_s   cnf71xx;
+};
+typedef union cvmx_mio_ptp_pps_thresh_hi cvmx_mio_ptp_pps_thresh_hi_t;
+
+/**
+ * cvmx_mio_ptp_pps_thresh_lo
+ *
+ * MIO_PTP_PPS_THRESH_LO = Lo bytes of PTP PPS
+ *
+ */
+union cvmx_mio_ptp_pps_thresh_lo {
+	uint64_t u64;
+	struct cvmx_mio_ptp_pps_thresh_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t frnanosec                    : 32; /**< Fractions of Nanoseconds */
+#else
+	uint64_t frnanosec                    : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_mio_ptp_pps_thresh_lo_s   cn61xx;
+	struct cvmx_mio_ptp_pps_thresh_lo_s   cn66xx;
+	struct cvmx_mio_ptp_pps_thresh_lo_s   cn68xx;
+	struct cvmx_mio_ptp_pps_thresh_lo_s   cnf71xx;
+};
+typedef union cvmx_mio_ptp_pps_thresh_lo cvmx_mio_ptp_pps_thresh_lo_t;
+
+/**
  * cvmx_mio_ptp_timestamp
  *
  * MIO_PTP_TIMESTAMP = Timestamp latched on MIO_PTP_CLOCK_CFG[TSTMP_EDGE] edge of MIO_PTP_CLOCK_CFG[TSTMP_IN]
  *
  */
-union cvmx_mio_ptp_timestamp
-{
+union cvmx_mio_ptp_timestamp {
 	uint64_t u64;
-	struct cvmx_mio_ptp_timestamp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_ptp_timestamp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t nanosec                      : 64; /**< Nanoseconds */
 #else
 	uint64_t nanosec                      : 64;
 #endif
 	} s;
+	struct cvmx_mio_ptp_timestamp_s       cn61xx;
 	struct cvmx_mio_ptp_timestamp_s       cn63xx;
 	struct cvmx_mio_ptp_timestamp_s       cn63xxp1;
+	struct cvmx_mio_ptp_timestamp_s       cn66xx;
+	struct cvmx_mio_ptp_timestamp_s       cn68xx;
+	struct cvmx_mio_ptp_timestamp_s       cn68xxp1;
+	struct cvmx_mio_ptp_timestamp_s       cnf71xx;
 };
 typedef union cvmx_mio_ptp_timestamp cvmx_mio_ptp_timestamp_t;
 
 /**
+ * cvmx_mio_qlm#_cfg
+ *
+ * Notes:
+ * Certain QLM_SPD is valid only for certain QLM_CFG configuration, refer to HRM for valid
+ * combinations.  These csrs are reset only on COLD_RESET.  The Reset values for QLM_SPD and QLM_CFG
+ * are as follows:               MIO_QLM0_CFG  SPD=F, CFG=2 SGMII (AGX0)
+ *                               MIO_QLM1_CFG  SPD=0, CFG=1 PCIE 2x1 (PEM0/PEM1)
+ */
+union cvmx_mio_qlmx_cfg {
+	uint64_t u64;
+	struct cvmx_mio_qlmx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t prtmode                      : 1;  /**< Port Mode, value of MIO_RST_CNTLX.PRTMODE[0]
+                                                         0 = port is EP mode
+                                                         1 = port is RC mode */
+	uint64_t reserved_12_13               : 2;
+	uint64_t qlm_spd                      : 4;  /**< QLM0 speed for SGMii
+                                                            0   = 5     Gbaud   100.00 MHz Ref
+                                                            1   = 2.5   Gbaud   100.00 MHz Ref
+                                                            2   = 2.5   Gbaud   100.00 MHz Ref
+                                                            3   = 1.25  Gbaud   100.00 MHz Ref
+                                                            4   = 1.25  Gbaud   156.25 MHz Ref
+                                                            5   = 6.25  Gbaud   125.00 MHz Ref
+                                                            6   = 5     Gbaud   125.00 MHz Ref
+                                                            7   = 2.5   Gbaud   156.25 MHz Ref
+                                                            8   = 3.125 Gbaud   125.00 MHz Ref
+                                                            9   = 2.5   Gbaud   125.00 MHz Ref
+                                                            10  = 1.25  Gbaud   125.00 MHz Ref
+                                                            11  = 5     Gbaud   156.25 MHz Ref
+                                                            12  = 6.25  Gbaud   156.25 MHz Ref
+                                                            13  = 3.75  Gbaud   156.25 MHz Ref
+                                                            14  = 3.125 Gbaud   156.25 MHz Ref
+                                                            15  = QLM Disabled
+
+                                                         QLM1 speed PEM0   PEM1
+                                                            0   =  2.5/5  2.5/5 Gbaud  100.00 MHz Ref
+                                                            1   =  2.5    2.5/5 Gbaud  100.00 MHz Ref
+                                                            2   =  2.5/5  2.5   Gbaud  100.00 MHz Ref
+                                                            3   =  2.5    2.5   Gbaud  100.00 MHz Ref
+                                                            4   =  2.5/5  2.5/5 Gbaud  125.00 MHz Ref
+                                                            6   =  2.5/5  2.5   Gbaud  125.00 MHz Ref
+                                                            7   =  2.5    2.5   Gbaud  125.00 MHz Ref
+                                                            9   =  2.5    2.5/5 Gbaud  125.00 MHz Ref
+                                                            15  =  QLM Disabled
+                                                            5,8,10-14 are reserved */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t qlm_cfg                      : 4;  /**< QLM configuration mode
+                                                         For Interface 0:
+                                                            00 Reserved
+                                                            01 Reserved
+                                                            10 SGMII (AGX0)
+                                                            11 Reserved
+                                                         For Interface 1:
+                                                            00 PCIE 1x2 (PEM1)
+                                                            01 PCIE 2x1 (PEM0/PEM1)
+                                                            1x Reserved */
+#else
+	uint64_t qlm_cfg                      : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t qlm_spd                      : 4;
+	uint64_t reserved_12_13               : 2;
+	uint64_t prtmode                      : 1;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_mio_qlmx_cfg_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t prtmode                      : 1;  /**< Port Mode, value of MIO_RST_CNTLX.PRTMODE[0]
+                                                            0 = port is EP mode
+                                                            1 = port is RC mode
+                                                         For QLM2, HOST_MODE is always '0' because PCIe
+                                                         is not supported. */
+	uint64_t reserved_12_13               : 2;
+	uint64_t qlm_spd                      : 4;  /**< QLM speed for SGMii/XAUI
+                                                            0   = 5     Gbaud   100.00 MHz Ref
+                                                            1   = 2.5   Gbaud   100.00 MHz Ref
+                                                            2   = 2.5   Gbaud   100.00 MHz Ref
+                                                            3   = 1.25  Gbaud   100.00 MHz Ref
+                                                            4   = 1.25  Gbaud   156.25 MHz Ref
+                                                            5   = 6.25  Gbaud   125.00 MHz Ref
+                                                            6   = 5     Gbaud   125.00 MHz Ref
+                                                            7   = 2.5   Gbaud   156.25 MHz Ref
+                                                            8   = 3.125 Gbaud   125.00 MHz Ref
+                                                            9   = 2.5   Gbaud   125.00 MHz Ref
+                                                            10  = 1.25  Gbaud   125.00 MHz Ref
+                                                            11  = 5     Gbaud   156.25 MHz Ref
+                                                            12  = 6.25  Gbaud   156.25 MHz Ref
+                                                            13  = 3.75  Gbaud   156.25 MHz Ref
+                                                            14  = 3.125 Gbaud   156.25 MHz Ref
+                                                            15  = QLM Disabled
+
+                                                         QLM speed PEM0   PEM1
+                                                            0   =  2.5/5  2.5/5 Gbaud  100.00 MHz Ref
+                                                            1   =  2.5    2.5/5 Gbaud  100.00 MHz Ref
+                                                            2   =  2.5/5  2.5   Gbaud  100.00 MHz Ref
+                                                            3   =  2.5    2.5   Gbaud  100.00 MHz Ref
+                                                            4   =  2.5/5  2.5/5 Gbaud  125.00 MHz Ref
+                                                            6   =  2.5/5  2.5   Gbaud  125.00 MHz Ref
+                                                            7   =  2.5    2.5   Gbaud  125.00 MHz Ref
+                                                            9   =  2.5    2.5/5 Gbaud  125.00 MHz Ref
+                                                            15  =  QLM Disabled
+                                                            5,8,10-14 are reserved */
+	uint64_t reserved_2_7                 : 6;
+	uint64_t qlm_cfg                      : 2;  /**< QLM configuration mode
+                                                         For Interface 0:
+                                                            00 PCIE 1x4 (PEM0)
+                                                            01 Reserved
+                                                            10 SGMII (AGX1)
+                                                            11 XAUI (AGX1)
+                                                         For Interface 1:
+                                                            00 PCIE 1x2 (PEM1)
+                                                            01 PCIE 2x1 (PEM0/PEM1)
+                                                            10 Reserved
+                                                            11 Reserved
+                                                         For Interface 2:
+                                                            00 Reserved
+                                                            01 Reserved
+                                                            10 SGMII (AGX0)
+                                                            11 XAUI (AGX0) */
+#else
+	uint64_t qlm_cfg                      : 2;
+	uint64_t reserved_2_7                 : 6;
+	uint64_t qlm_spd                      : 4;
+	uint64_t reserved_12_13               : 2;
+	uint64_t prtmode                      : 1;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} cn61xx;
+	struct cvmx_mio_qlmx_cfg_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_12_63               : 52;
+	uint64_t qlm_spd                      : 4;  /**< QLM speed
+                                                         0   = 5     Gbaud
+                                                         1   = 2.5   Gbaud
+                                                         2   = 2.5   Gbaud
+                                                         3   = 1.25  Gbaud
+                                                         4   = 1.25  Gbaud
+                                                         5   = 6.25  Gbaud
+                                                         6   = 5     Gbaud
+                                                         7   = 2.5   Gbaud
+                                                         8   = 3.125 Gbaud
+                                                         9   = 2.5   Gbaud
+                                                         10  = 1.25  Gbaud
+                                                         11  = 5     Gbaud
+                                                         12  = 6.25  Gbaud
+                                                         13  = 3.75  Gbaud
+                                                         14  = 3.125 Gbaud
+                                                         15  = QLM Disabled */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t qlm_cfg                      : 4;  /**< QLM configuration mode
+                                                            0000 PCIE gen2
+                                                            0001 SRIO 1x4 short
+                                                            0010 PCIE gen1 only
+                                                            0011 SRIO 1x4 long
+                                                            0100 SRIO 2x2 short
+                                                            0101 SRIO 4x1 short
+                                                            0110 SRIO 2x2 long
+                                                            0111 SRIO 4x1 long
+                                                            1000 PCIE gen2 (alias)
+                                                            1001 SGMII
+                                                            1010 PCIE gen1 only (alias)
+                                                            1011 XAUI
+                                                            1100 RESERVED
+                                                            1101 RESERVED
+                                                            1110 RESERVED
+                                                            1111 RESERVED
+                                                         NOTE: Internal encodings differ from QLM_MODE
+                                                               pins encodings */
+#else
+	uint64_t qlm_cfg                      : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t qlm_spd                      : 4;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn66xx;
+	struct cvmx_mio_qlmx_cfg_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_12_63               : 52;
+	uint64_t qlm_spd                      : 4;  /**< QLM speed
+                                                         0   = 5     Gbaud   100.00 MHz Ref
+                                                         1   = 2.5   Gbaud   100.00 MHz Ref
+                                                         2   = 2.5   Gbaud   100.00 MHz Ref
+                                                         3   = 1.25  Gbaud   100.00 MHz Ref
+                                                         4   = 1.25  Gbaud   156.25 MHz Ref
+                                                         5   = 6.25  Gbaud   125.00 MHz Ref
+                                                         6   = 5     Gbaud   125.00 MHz Ref
+                                                         7   = 2.5   Gbaud   156.25 MHz Ref
+                                                         8   = 3.125 Gbaud   125.00 MHz Ref
+                                                         9   = 2.5   Gbaud   125.00 MHz Ref
+                                                         10  = 1.25  Gbaud   125.00 MHz Ref
+                                                         11  = 5     Gbaud   156.25 MHz Ref
+                                                         12  = 6.25  Gbaud   156.25 MHz Ref
+                                                         13  = 3.75  Gbaud   156.25 MHz Ref
+                                                         14  = 3.125 Gbaud   156.25 MHz Ref
+                                                         15  = QLM Disabled */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t qlm_cfg                      : 3;  /**< QLM configuration mode
+                                                            000 = PCIE
+                                                            001 = ILK
+                                                            010 = SGMII
+                                                            011 = XAUI
+                                                            100 = RESERVED
+                                                            101 = RESERVED
+                                                            110 = RESERVED
+                                                            111 = RXAUI
+                                                         NOTE: Internal encodings differ from QLM_MODE
+                                                               pins encodings */
+#else
+	uint64_t qlm_cfg                      : 3;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t qlm_spd                      : 4;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn68xx;
+	struct cvmx_mio_qlmx_cfg_cn68xx       cn68xxp1;
+	struct cvmx_mio_qlmx_cfg_cn61xx       cnf71xx;
+};
+typedef union cvmx_mio_qlmx_cfg cvmx_mio_qlmx_cfg_t;
+
+/**
  * cvmx_mio_rst_boot
+ *
+ * Notes:
+ * JTCSRDIS, EJTAGDIS, ROMEN reset to 1 in authentik mode; in all other modes they reset to 0.
+ *
  */
-union cvmx_mio_rst_boot
-{
+union cvmx_mio_rst_boot {
 	uint64_t u64;
-	struct cvmx_mio_rst_boot_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_rst_boot_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t chipkill                     : 1;  /**< A 0->1 transition of CHIPKILL starts the CHIPKILL
+                                                         timer.  When CHIPKILL=1 and the timer expires,
+                                                         internal chip reset is asserted forever until the
+                                                         next chip reset.  The CHIPKILL timer can be
+                                                         stopped only by a chip (cold, warm, soft) reset.
+                                                         The length of the CHIPKILL timer is specified by
+                                                         MIO_RST_CKILL[TIMER]. */
+	uint64_t jtcsrdis                     : 1;  /**< If JTCSRDIS=1, internal CSR access via JTAG TAP
+                                                         controller is disabled */
+	uint64_t ejtagdis                     : 1;  /**< If EJTAGDIS=1, external EJTAG access is disabled */
+	uint64_t romen                        : 1;  /**< If ROMEN=1, Authentik/eMMC boot ROM is visible
+                                                         in the boot bus address space. */
+	uint64_t ckill_ppdis                  : 1;  /**< If CK_PPDIS=1, PPs other than 0 are disabled
+                                                         during a CHIPKILL.  Writes have no effect when
+                                                         MIO_RST_BOOT[CHIPKILL]=1. */
+	uint64_t jt_tstmode                   : 1;  /**< JTAG test mode */
+	uint64_t reserved_50_57               : 8;
+	uint64_t lboot_ext                    : 2;  /**< Reserved */
+	uint64_t reserved_44_47               : 4;
+	uint64_t qlm4_spd                     : 4;  /**< QLM4_SPD pins sampled at DCOK assertion */
+	uint64_t qlm3_spd                     : 4;  /**< QLM3_SPD pins sampled at DCOK assertion */
+	uint64_t c_mul                        : 6;  /**< Core clock multiplier:
+                                                           C_MUL = (core clk speed) / (ref clock speed)
+                                                         "ref clock speed" should always be 50MHz.
+                                                         If PLL_QLM_REF_CLK_EN=0, "ref clock" comes
+                                                              from PLL_REF_CLK pin.
+                                                         If PLL_QLM_REF_CLK_EN=1, "ref clock" is
+                                                              1/2 speed of QLMC_REF_CLK_* pins. */
+	uint64_t pnr_mul                      : 6;  /**< Coprocessor clock multiplier:
+                                                           PNR_MUL = (coprocessor clk speed) /
+                                                                           (ref clock speed)
+                                                         See C_MUL comments about ref clock. */
+	uint64_t qlm2_spd                     : 4;  /**< QLM2_SPD, report MIO_QLM2_CFG[SPD] */
+	uint64_t qlm1_spd                     : 4;  /**< QLM1_SPD, report MIO_QLM1_CFG[SPD] */
+	uint64_t qlm0_spd                     : 4;  /**< QLM0_SPD, report MIO_QLM0_CFG[SPD] */
+	uint64_t lboot                        : 10; /**< Last boot cause mask, resets only with dcok.
+
+                                                         bit9 - Soft reset due to watchdog
+                                                         bit8 - Soft reset due to CIU_SOFT_RST write
+                                                         bit7 - Warm reset due to cntl0 link-down or
+                                                                hot-reset
+                                                         bit6 - Warm reset due to cntl1 link-down or
+                                                                hot-reset
+                                                         bit5 - Cntl1 reset due to PERST1_L pin
+                                                         bit4 - Cntl0 reset due to PERST0_L pin
+                                                         bit3 - Warm reset due to PERST1_L pin
+                                                         bit2 - Warm reset due to PERST0_L pin
+                                                         bit1 - Warm reset due to CHIP_RESET_L pin
+                                                         bit0 - Cold reset due to DCOK pin */
+	uint64_t rboot                        : 1;  /**< Determines whether core 0 remains in reset after
+                                                         after chip cold/warm/soft reset. */
+	uint64_t rboot_pin                    : 1;  /**< Read-only access to REMOTE_BOOT pin */
+#else
+	uint64_t rboot_pin                    : 1;
+	uint64_t rboot                        : 1;
+	uint64_t lboot                        : 10;
+	uint64_t qlm0_spd                     : 4;
+	uint64_t qlm1_spd                     : 4;
+	uint64_t qlm2_spd                     : 4;
+	uint64_t pnr_mul                      : 6;
+	uint64_t c_mul                        : 6;
+	uint64_t qlm3_spd                     : 4;
+	uint64_t qlm4_spd                     : 4;
+	uint64_t reserved_44_47               : 4;
+	uint64_t lboot_ext                    : 2;
+	uint64_t reserved_50_57               : 8;
+	uint64_t jt_tstmode                   : 1;
+	uint64_t ckill_ppdis                  : 1;
+	uint64_t romen                        : 1;
+	uint64_t ejtagdis                     : 1;
+	uint64_t jtcsrdis                     : 1;
+	uint64_t chipkill                     : 1;
+#endif
+	} s;
+	struct cvmx_mio_rst_boot_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t chipkill                     : 1;  /**< A 0->1 transition of CHIPKILL starts the CHIPKILL
+                                                         timer.  When CHIPKILL=1 and the timer expires,
+                                                         internal chip reset is asserted forever until the
+                                                         next chip reset.  The CHIPKILL timer can be
+                                                         stopped only by a chip (cold, warm, soft) reset.
+                                                         The length of the CHIPKILL timer is specified by
+                                                         MIO_RST_CKILL[TIMER]. */
+	uint64_t jtcsrdis                     : 1;  /**< If JTCSRDIS=1, internal CSR access via JTAG TAP
+                                                         controller is disabled */
+	uint64_t ejtagdis                     : 1;  /**< If EJTAGDIS=1, external EJTAG access is disabled */
+	uint64_t romen                        : 1;  /**< If ROMEN=1, Authentik/eMMC boot ROM is visible
+                                                         in the boot bus address space. */
+	uint64_t ckill_ppdis                  : 1;  /**< If CK_PPDIS=1, PPs other than 0 are disabled
+                                                         during a CHIPKILL.  Writes have no effect when
+                                                         MIO_RST_BOOT[CHIPKILL]=1. */
+	uint64_t jt_tstmode                   : 1;  /**< JTAG test mode */
+	uint64_t reserved_50_57               : 8;
+	uint64_t lboot_ext                    : 2;  /**< Reserved */
+	uint64_t reserved_36_47               : 12;
+	uint64_t c_mul                        : 6;  /**< Core clock multiplier:
+                                                           C_MUL = (core clk speed) / (ref clock speed)
+                                                         "ref clock speed" should always be 50MHz.
+                                                         If PLL_QLM_REF_CLK_EN=0, "ref clock" comes
+                                                              from PLL_REF_CLK pin.
+                                                         If PLL_QLM_REF_CLK_EN=1, "ref clock" is
+                                                              1/2 speed of QLMC_REF_CLK_* pins. */
+	uint64_t pnr_mul                      : 6;  /**< Coprocessor clock multiplier:
+                                                           PNR_MUL = (coprocessor clk speed) /
+                                                                           (ref clock speed)
+                                                         See C_MUL comments about ref clock. */
+	uint64_t qlm2_spd                     : 4;  /**< QLM2_SPD, report MIO_QLM2_CFG[SPD] */
+	uint64_t qlm1_spd                     : 4;  /**< QLM1_SPD, report MIO_QLM1_CFG[SPD] */
+	uint64_t qlm0_spd                     : 4;  /**< QLM0_SPD, report MIO_QLM0_CFG[SPD] */
+	uint64_t lboot                        : 10; /**< Last boot cause mask, resets only with dcok.
+
+                                                         bit9 - Soft reset due to watchdog
+                                                         bit8 - Soft reset due to CIU_SOFT_RST write
+                                                         bit7 - Warm reset due to cntl0 link-down or
+                                                                hot-reset
+                                                         bit6 - Warm reset due to cntl1 link-down or
+                                                                hot-reset
+                                                         bit5 - Cntl1 reset due to PERST1_L pin
+                                                         bit4 - Cntl0 reset due to PERST0_L pin
+                                                         bit3 - Warm reset due to PERST1_L pin
+                                                         bit2 - Warm reset due to PERST0_L pin
+                                                         bit1 - Warm reset due to CHIP_RESET_L pin
+                                                         bit0 - Cold reset due to DCOK pin */
+	uint64_t rboot                        : 1;  /**< Determines whether core 0 remains in reset after
+                                                         after chip cold/warm/soft reset. */
+	uint64_t rboot_pin                    : 1;  /**< Read-only access to REMOTE_BOOT pin */
+#else
+	uint64_t rboot_pin                    : 1;
+	uint64_t rboot                        : 1;
+	uint64_t lboot                        : 10;
+	uint64_t qlm0_spd                     : 4;
+	uint64_t qlm1_spd                     : 4;
+	uint64_t qlm2_spd                     : 4;
+	uint64_t pnr_mul                      : 6;
+	uint64_t c_mul                        : 6;
+	uint64_t reserved_36_47               : 12;
+	uint64_t lboot_ext                    : 2;
+	uint64_t reserved_50_57               : 8;
+	uint64_t jt_tstmode                   : 1;
+	uint64_t ckill_ppdis                  : 1;
+	uint64_t romen                        : 1;
+	uint64_t ejtagdis                     : 1;
+	uint64_t jtcsrdis                     : 1;
+	uint64_t chipkill                     : 1;
+#endif
+	} cn61xx;
+	struct cvmx_mio_rst_boot_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t c_mul                        : 6;  /**< Core clock multiplier:
                                                            C_MUL = (core clk speed) / (ref clock speed)
@@ -3911,9 +6139,183 @@ union cvmx_mio_rst_boot
 	uint64_t c_mul                        : 6;
 	uint64_t reserved_36_63               : 28;
 #endif
-	} s;
-	struct cvmx_mio_rst_boot_s            cn63xx;
-	struct cvmx_mio_rst_boot_s            cn63xxp1;
+	} cn63xx;
+	struct cvmx_mio_rst_boot_cn63xx       cn63xxp1;
+	struct cvmx_mio_rst_boot_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t chipkill                     : 1;  /**< A 0->1 transition of CHIPKILL starts the CHIPKILL
+                                                         timer.  When CHIPKILL=1 and the timer expires,
+                                                         internal chip reset is asserted forever until the
+                                                         next chip reset.  The CHIPKILL timer can be
+                                                         stopped only by a chip (cold, warm, soft) reset.
+                                                         The length of the CHIPKILL timer is specified by
+                                                         MIO_RST_CKILL[TIMER]. */
+	uint64_t jtcsrdis                     : 1;  /**< If JTCSRDIS=1, internal CSR access via JTAG TAP
+                                                         controller is disabled */
+	uint64_t ejtagdis                     : 1;  /**< If EJTAGDIS=1, external EJTAG access is disabled */
+	uint64_t romen                        : 1;  /**< If ROMEN=1, Authentik ROM is visible in the boot
+                                                         bus address space. */
+	uint64_t ckill_ppdis                  : 1;  /**< If CK_PPDIS=1, PPs other than 0 are disabled
+                                                         during a CHIPKILL.  Writes have no effect when
+                                                         MIO_RST_BOOT[CHIPKILL]=1. */
+	uint64_t reserved_50_58               : 9;
+	uint64_t lboot_ext                    : 2;  /**< Extended Last boot cause mask, resets only with
+                                                         dock.
+
+                                                           bit1 - Warm reset due to cntl3 link-down or
+                                                                  hot-reset
+                                                           bit0 - Warm reset due to cntl2 link-down or
+                                                                  hot-reset */
+	uint64_t reserved_36_47               : 12;
+	uint64_t c_mul                        : 6;  /**< Core clock multiplier:
+                                                           C_MUL = (core clk speed) / (ref clock speed)
+                                                         "ref clock speed" should always be 50MHz.
+                                                         If PLL_QLM_REF_CLK_EN=0, "ref clock" comes
+                                                              from PLL_REF_CLK pin.
+                                                         If PLL_QLM_REF_CLK_EN=1, "ref clock" is
+                                                              1/2 speed of QLMC_REF_CLK_* pins. */
+	uint64_t pnr_mul                      : 6;  /**< Coprocessor clock multiplier:
+                                                           PNR_MUL = (coprocessor clk speed) /
+                                                                           (ref clock speed)
+                                                         See C_MUL comments about ref clock. */
+	uint64_t qlm2_spd                     : 4;  /**< QLM2_SPD pins sampled at DCOK assertion */
+	uint64_t qlm1_spd                     : 4;  /**< QLM1_SPD pins sampled at DCOK assertion */
+	uint64_t qlm0_spd                     : 4;  /**< QLM0_SPD pins sampled at DCOK assertion */
+	uint64_t lboot                        : 10; /**< Last boot cause mask, resets only with dock.
+
+                                                         bit9 - Soft reset due to watchdog
+                                                         bit8 - Soft reset due to CIU_SOFT_RST write
+                                                         bit7 - Warm reset due to cntl0 link-down or
+                                                                hot-reset
+                                                         bit6 - Warm reset due to cntl1 link-down or
+                                                                hot-reset
+                                                         bit5 - Cntl1 reset due to PERST1_L pin
+                                                         bit4 - Cntl0 reset due to PERST0_L pin
+                                                         bit3 - Warm reset due to PERST1_L pin
+                                                         bit2 - Warm reset due to PERST0_L pin
+                                                         bit1 - Warm reset due to CHIP_RESET_L pin
+                                                         bit0 - Cold reset due to DCOK pin */
+	uint64_t rboot                        : 1;  /**< Determines whether core 0 remains in reset after
+                                                         after chip cold/warm/soft reset. */
+	uint64_t rboot_pin                    : 1;  /**< Read-only access to REMOTE_BOOT pin */
+#else
+	uint64_t rboot_pin                    : 1;
+	uint64_t rboot                        : 1;
+	uint64_t lboot                        : 10;
+	uint64_t qlm0_spd                     : 4;
+	uint64_t qlm1_spd                     : 4;
+	uint64_t qlm2_spd                     : 4;
+	uint64_t pnr_mul                      : 6;
+	uint64_t c_mul                        : 6;
+	uint64_t reserved_36_47               : 12;
+	uint64_t lboot_ext                    : 2;
+	uint64_t reserved_50_58               : 9;
+	uint64_t ckill_ppdis                  : 1;
+	uint64_t romen                        : 1;
+	uint64_t ejtagdis                     : 1;
+	uint64_t jtcsrdis                     : 1;
+	uint64_t chipkill                     : 1;
+#endif
+	} cn66xx;
+	struct cvmx_mio_rst_boot_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_59_63               : 5;
+	uint64_t jt_tstmode                   : 1;  /**< JTAG test mode */
+	uint64_t reserved_44_57               : 14;
+	uint64_t qlm4_spd                     : 4;  /**< QLM4_SPD pins sampled at DCOK assertion */
+	uint64_t qlm3_spd                     : 4;  /**< QLM3_SPD pins sampled at DCOK assertion */
+	uint64_t c_mul                        : 6;  /**< Core clock multiplier:
+                                                           C_MUL = (core clk speed) / (ref clock speed)
+                                                         "ref clock" is PLL_REF_CLK pin, which should
+                                                         always be 50 MHz. */
+	uint64_t pnr_mul                      : 6;  /**< Coprocessor clock multiplier:
+                                                           PNR_MUL = (coprocessor clk speed)
+                                                                         (ref clock speed)
+                                                         See C_MUL comments about ref clock. */
+	uint64_t qlm2_spd                     : 4;  /**< QLM2_SPD pins sampled at DCOK assertion */
+	uint64_t qlm1_spd                     : 4;  /**< QLM1_SPD pins sampled at DCOK assertion */
+	uint64_t qlm0_spd                     : 4;  /**< QLM0_SPD pins sampled at DCOK assertion */
+	uint64_t lboot                        : 10; /**< Last boot cause mask, resets only with dock.
+
+                                                         bit9 - Soft reset due to watchdog
+                                                         bit8 - Soft reset due to CIU_SOFT_RST write
+                                                         bit7 - Warm reset due to cntl0 link-down or
+                                                                hot-reset
+                                                         bit6 - Warm reset due to cntl1 link-down or
+                                                                hot-reset
+                                                         bit5 - Cntl1 reset due to PERST1_L pin
+                                                         bit4 - Cntl0 reset due to PERST0_L pin
+                                                         bit3 - Warm reset due to PERST1_L pin
+                                                         bit2 - Warm reset due to PERST0_L pin
+                                                         bit1 - Warm reset due to CHIP_RESET_L pin
+                                                         bit0 - Cold reset due to DCOK pin */
+	uint64_t rboot                        : 1;  /**< Determines whether core 0 remains in reset after
+                                                         after chip cold/warm/soft reset. */
+	uint64_t rboot_pin                    : 1;  /**< Read-only access to REMOTE_BOOT pin */
+#else
+	uint64_t rboot_pin                    : 1;
+	uint64_t rboot                        : 1;
+	uint64_t lboot                        : 10;
+	uint64_t qlm0_spd                     : 4;
+	uint64_t qlm1_spd                     : 4;
+	uint64_t qlm2_spd                     : 4;
+	uint64_t pnr_mul                      : 6;
+	uint64_t c_mul                        : 6;
+	uint64_t qlm3_spd                     : 4;
+	uint64_t qlm4_spd                     : 4;
+	uint64_t reserved_44_57               : 14;
+	uint64_t jt_tstmode                   : 1;
+	uint64_t reserved_59_63               : 5;
+#endif
+	} cn68xx;
+	struct cvmx_mio_rst_boot_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_44_63               : 20;
+	uint64_t qlm4_spd                     : 4;  /**< QLM4_SPD pins sampled at DCOK assertion */
+	uint64_t qlm3_spd                     : 4;  /**< QLM3_SPD pins sampled at DCOK assertion */
+	uint64_t c_mul                        : 6;  /**< Core clock multiplier:
+                                                           C_MUL = (core clk speed) / (ref clock speed)
+                                                         "ref clock" is PLL_REF_CLK pin, which should
+                                                         always be 50 MHz. */
+	uint64_t pnr_mul                      : 6;  /**< Coprocessor clock multiplier:
+                                                           PNR_MUL = (coprocessor clk speed)
+                                                                         (ref clock speed)
+                                                         See C_MUL comments about ref clock. */
+	uint64_t qlm2_spd                     : 4;  /**< QLM2_SPD pins sampled at DCOK assertion */
+	uint64_t qlm1_spd                     : 4;  /**< QLM1_SPD pins sampled at DCOK assertion */
+	uint64_t qlm0_spd                     : 4;  /**< QLM0_SPD pins sampled at DCOK assertion */
+	uint64_t lboot                        : 10; /**< Last boot cause mask, resets only with dock.
+
+                                                         bit9 - Soft reset due to watchdog
+                                                         bit8 - Soft reset due to CIU_SOFT_RST write
+                                                         bit7 - Warm reset due to cntl0 link-down or
+                                                                hot-reset
+                                                         bit6 - Warm reset due to cntl1 link-down or
+                                                                hot-reset
+                                                         bit5 - Cntl1 reset due to PERST1_L pin
+                                                         bit4 - Cntl0 reset due to PERST0_L pin
+                                                         bit3 - Warm reset due to PERST1_L pin
+                                                         bit2 - Warm reset due to PERST0_L pin
+                                                         bit1 - Warm reset due to CHIP_RESET_L pin
+                                                         bit0 - Cold reset due to DCOK pin */
+	uint64_t rboot                        : 1;  /**< Determines whether core 0 remains in reset after
+                                                         after chip cold/warm/soft reset. */
+	uint64_t rboot_pin                    : 1;  /**< Read-only access to REMOTE_BOOT pin */
+#else
+	uint64_t rboot_pin                    : 1;
+	uint64_t rboot                        : 1;
+	uint64_t lboot                        : 10;
+	uint64_t qlm0_spd                     : 4;
+	uint64_t qlm1_spd                     : 4;
+	uint64_t qlm2_spd                     : 4;
+	uint64_t pnr_mul                      : 6;
+	uint64_t c_mul                        : 6;
+	uint64_t qlm3_spd                     : 4;
+	uint64_t qlm4_spd                     : 4;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} cn68xxp1;
+	struct cvmx_mio_rst_boot_cn61xx       cnf71xx;
 };
 typedef union cvmx_mio_rst_boot cvmx_mio_rst_boot_t;
 
@@ -3924,12 +6326,29 @@ typedef union cvmx_mio_rst_boot cvmx_mio_rst_boot_t;
  * Cold reset will always performs a full bist.
  *
  */
-union cvmx_mio_rst_cfg
-{
+union cvmx_mio_rst_cfg {
 	uint64_t u64;
-	struct cvmx_mio_rst_cfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_rst_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_3_63                : 61;
+	uint64_t cntl_clr_bist                : 1;  /**< Peform clear bist during cntl only reset,
+                                                         instead of a full bist. A warm/soft reset will
+                                                         not change this field. */
+	uint64_t warm_clr_bist                : 1;  /**< Peform clear bist during warm reset, instead
+                                                         of a full bist. A warm/soft reset will not
+                                                         change this field. */
+	uint64_t soft_clr_bist                : 1;  /**< Peform clear bist during soft reset, instead
+                                                         of a full bist. A warm/soft reset will not
+                                                         change this field. */
+#else
+	uint64_t soft_clr_bist                : 1;
+	uint64_t warm_clr_bist                : 1;
+	uint64_t cntl_clr_bist                : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_mio_rst_cfg_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bist_delay                   : 58; /**< Reserved */
 	uint64_t reserved_3_5                 : 3;
 	uint64_t cntl_clr_bist                : 1;  /**< Peform clear bist during cntl only reset,
@@ -3948,11 +6367,10 @@ union cvmx_mio_rst_cfg
 	uint64_t reserved_3_5                 : 3;
 	uint64_t bist_delay                   : 58;
 #endif
-	} s;
-	struct cvmx_mio_rst_cfg_s             cn63xx;
-	struct cvmx_mio_rst_cfg_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	} cn61xx;
+	struct cvmx_mio_rst_cfg_cn61xx        cn63xx;
+	struct cvmx_mio_rst_cfg_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bist_delay                   : 58; /**< Reserved */
 	uint64_t reserved_2_5                 : 4;
 	uint64_t warm_clr_bist                : 1;  /**< Peform clear bist during warm reset, instead
@@ -3968,29 +6386,453 @@ union cvmx_mio_rst_cfg
 	uint64_t bist_delay                   : 58;
 #endif
 	} cn63xxp1;
+	struct cvmx_mio_rst_cfg_cn61xx        cn66xx;
+	struct cvmx_mio_rst_cfg_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bist_delay                   : 56; /**< Reserved */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t cntl_clr_bist                : 1;  /**< Peform clear bist during cntl only reset,
+                                                         instead of a full bist. A warm/soft reset will
+                                                         not change this field. */
+	uint64_t warm_clr_bist                : 1;  /**< Peform clear bist during warm reset, instead
+                                                         of a full bist. A warm/soft reset will not
+                                                         change this field. */
+	uint64_t soft_clr_bist                : 1;  /**< Peform clear bist during soft reset, instead
+                                                         of a full bist. A warm/soft reset will not
+                                                         change this field. */
+#else
+	uint64_t soft_clr_bist                : 1;
+	uint64_t warm_clr_bist                : 1;
+	uint64_t cntl_clr_bist                : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t bist_delay                   : 56;
+#endif
+	} cn68xx;
+	struct cvmx_mio_rst_cfg_cn68xx        cn68xxp1;
+	struct cvmx_mio_rst_cfg_cn61xx        cnf71xx;
 };
 typedef union cvmx_mio_rst_cfg cvmx_mio_rst_cfg_t;
 
 /**
- * cvmx_mio_rst_ctl#
+ * cvmx_mio_rst_ckill
+ *
+ * MIO_RST_CKILL = MIO Chipkill Timer Register
+ *
  */
-union cvmx_mio_rst_ctlx
-{
+union cvmx_mio_rst_ckill {
+	uint64_t u64;
+	struct cvmx_mio_rst_ckill_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_47_63               : 17;
+	uint64_t timer                        : 47; /**< CHIPKILL timer measured in SCLKs.  Reads return
+                                                         the current CHIPKILL timer.   Writes have no
+                                                         effect when MIO_RST_BOOT[CHIPKILL]=1. */
+#else
+	uint64_t timer                        : 47;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} s;
+	struct cvmx_mio_rst_ckill_s           cn61xx;
+	struct cvmx_mio_rst_ckill_s           cn66xx;
+	struct cvmx_mio_rst_ckill_s           cnf71xx;
+};
+typedef union cvmx_mio_rst_ckill cvmx_mio_rst_ckill_t;
+
+/**
+ * cvmx_mio_rst_cntl#
+ *
+ * Notes:
+ * GEN1_Only mode is enabled for PEM0 when QLM1_SPD[0] is set or when sclk < 550Mhz.
+ * GEN1_Only mode is enabled for PEM1 when QLM1_SPD[1] is set or when sclk < 550Mhz.
+ */
+union cvmx_mio_rst_cntlx {
 	uint64_t u64;
-	struct cvmx_mio_rst_ctlx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_rst_cntlx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_13_63               : 51;
+	uint64_t in_rev_ln                    : 1;  /**< RO access to corresponding pin PCIE*_REV_LANES
+                                                         which is used for initial value for REV_LANES
+                                                         For INT0/CNTL0: pin PCIE0_REV_LANES
+                                                         For INT1/CNTL1: always zero as no PCIE1 pin */
+	uint64_t rev_lanes                    : 1;  /**< Reverse the lanes for INT*.
+                                                         A warm/soft reset will not change this field.
+                                                         On cold reset, this field is initialized to
+                                                         IN_REVLANE value.
+                                                         When QLM1_CFG=1, INT0(PEM0) REV_LANES internal
+                                                         setting will be always forced to '0', INT1(PEM1)
+                                                         will be forced to '1' regardless CSR value. */
+	uint64_t gen1_only                    : 1;  /**< Disable PCIE GEN2 Capability.  This bit is
+                                                         always unpredictable whenever the controller
+                                                         is not attached to any SerDes lanes, and is
+                                                         otherwise always set when SCLK is slower than
+                                                         550Mhz.
+                                                         The MIO_RST_CNTL*[GEN1_ONLY] value is based on
+                                                         the MIO_QLM1_CFG[QLM_SPD] value. */
+	uint64_t prst_link                    : 1;  /**< Controls whether corresponding controller
+                                                         link-down or hot-reset causes the assertion of
+                                                         CIU_SOFT_PRST*[SOFT_PRST]
+
+                                                         A warm/soft reset will not change this field.
+                                                         On cold reset, this field is initialized to 0 */
+	uint64_t rst_done                     : 1;  /**< Read-only access to controller reset status
+
+                                                         RESET_DONE is always zero (i.e. the controller
+                                                         is held in reset) when:
+                                                           - CIU_SOFT_PRST*[SOFT_PRST]=1, or
+                                                           - RST_RCV==1 and PERST*_L pin is asserted */
+	uint64_t rst_link                     : 1;  /**< Controls whether corresponding controller
+                                                         link-down or hot-reset causes a warm chip reset
+                                                         On cold reset, this field is initialized as
+                                                         follows:
+                                                            0 = when corresponding HOST_MODE=1
+                                                            1 = when corresponding HOST_MODE=0
+
+                                                         Note that a link-down or hot-reset event can
+                                                         never cause a warm chip reset when the
+                                                         controller is in reset (i.e. can never cause a
+                                                         warm reset when RST_DONE==0). */
+	uint64_t host_mode                    : 1;  /**< RO access to corresponding strap PCIE*_HOST_MODE
+                                                         For CNTL1/INT1, HOST_MODE is always '1' because
+                                                         there is no PCIE1_HOST_MODE pin. */
+	uint64_t prtmode                      : 2;  /**< Port mode
+                                                            0 = port is EP mode
+                                                            1 = port is RC mode
+                                                            2,3 = Reserved
+                                                         A warm/soft reset will not change this field.
+                                                         On cold reset, this field is initialized as
+                                                         HOST_MODE (corresponding strap PCIE*_HOST_MODE) */
+	uint64_t rst_drv                      : 1;  /**< Controls whether corresponding PERST*_L chip pin
+                                                         is driven by the OCTEON.  A warm/soft reset
+                                                         will not change this field.  On cold reset,
+                                                         this field is initialized as follows:
+                                                          0 = when corresponding HOST_MODE=0
+                                                          1 = when corresponding HOST_MODE=1
+
+                                                         When set, OCTEON drives the corresponding
+                                                         PERST*_L pin. Otherwise, OCTEON does not drive
+                                                         the corresponding PERST*_L pin. */
+	uint64_t rst_rcv                      : 1;  /**< Controls whether corresponding PERST*_L chip pin
+                                                         is recieved by OCTEON.  A warm/soft reset
+                                                         will not change this field.  On cold reset,
+                                                         this field is initialized as follows:
+                                                          0 = when corresponding HOST_MODE=1
+                                                          1 = when corresponding HOST_MODE=0
+
+                                                         When RST_RCV==1, the PERST*_L value is
+                                                         received and may be used to reset the
+                                                         controller and (optionally, based on RST_CHIP)
+                                                         warm reset the chip.
+
+                                                         When RST_RCV==1 (and RST_CHIP=0),
+                                                         MIO_RST_INT[PERST*] gets set when the PERST*_L
+                                                         pin asserts. (This interrupt can alert SW
+                                                         whenever the external reset pin initiates a
+                                                         controller reset sequence.)
+
+                                                         RST_VAL gives the PERST*_L pin value when
+                                                         RST_RCV==1.
+
+                                                         When RST_RCV==0, the PERST*_L pin value is
+                                                         ignored. */
+	uint64_t rst_chip                     : 1;  /**< Controls whether corresponding PERST*_L chip
+                                                         pin causes a chip warm reset like CHIP_RESET_L.
+                                                         A warm/soft reset will not change this field.
+                                                         On cold reset, this field is initialized to 0.
+
+                                                         RST_CHIP is not used when RST_RCV==0.
+
+                                                         When RST_RCV==0, RST_CHIP is ignored.
+
+                                                         When RST_RCV==1, RST_CHIP==1, and PERST*_L
+                                                         asserts, a chip warm reset will be generated. */
+	uint64_t rst_val                      : 1;  /**< Read-only access to corresponding PERST*_L pin
+                                                         Unpredictable when RST_RCV==0. Reads as 1 when
+                                                         RST_RCV==1 and the PERST*_L pin is asserted.
+                                                         Reads as 0 when RST_RCV==1 and the PERST*_L
+                                                         pin is not asserted. */
+#else
+	uint64_t rst_val                      : 1;
+	uint64_t rst_chip                     : 1;
+	uint64_t rst_rcv                      : 1;
+	uint64_t rst_drv                      : 1;
+	uint64_t prtmode                      : 2;
+	uint64_t host_mode                    : 1;
+	uint64_t rst_link                     : 1;
+	uint64_t rst_done                     : 1;
+	uint64_t prst_link                    : 1;
+	uint64_t gen1_only                    : 1;
+	uint64_t rev_lanes                    : 1;
+	uint64_t in_rev_ln                    : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_mio_rst_cntlx_s           cn61xx;
+	struct cvmx_mio_rst_cntlx_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t prst_link                    : 1;  /**< Controls whether corresponding controller
                                                          link-down or hot-reset causes the assertion of
                                                          CIU_SOFT_PRST*[SOFT_PRST]
 
                                                          A warm/soft reset will not change this field.
-                                                         On cold reset, this field is initialized to 0
+                                                         On cold reset, this field is initialized to 0 */
+	uint64_t rst_done                     : 1;  /**< Read-only access to controller reset status
+
+                                                         RESET_DONE is always zero (i.e. the controller
+                                                         is held in reset) when:
+                                                           - CIU_SOFT_PRST*[SOFT_PRST]=1, or
+                                                           - RST_RCV==1 and PERST*_L pin is asserted */
+	uint64_t rst_link                     : 1;  /**< Controls whether corresponding controller
+                                                         link-down or hot-reset causes a warm chip reset
+                                                         On cold reset, this field is initialized as
+                                                         follows:
+                                                            0 = when corresponding strap QLM*_HOST_MODE=1
+                                                            1 = when corresponding strap QLM*_HOST_MODE=0
+
+                                                         For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field
+                                                         is initialized to 1 on cold reset.
+
+                                                         Note that a link-down or hot-reset event can
+                                                         never cause a warm chip reset when the
+                                                         controller is in reset (i.e. can never cause a
+                                                         warm reset when RST_DONE==0). */
+	uint64_t host_mode                    : 1;  /**< RO access to corresponding strap QLM*_HOST_MODE
+
+                                                         For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field
+                                                         is reserved/RAZ.
+
+                                                         QLM0_HOST_MODE corresponds to PCIe0/sRIO0
+                                                         QLM1_HOST_MODE corresponds to PCIe1/sRIO1 */
+	uint64_t prtmode                      : 2;  /**< Port mode
+                                                            0 = port is EP mode
+                                                            1 = port is RC mode
+                                                            2,3 = Reserved
+                                                         A warm/soft reset will not change this field.
+                                                         On cold reset, this field is initialized as
                                                          follows:
+                                                            0 = when corresponding strap QLM*_HOST_MODE=0
+                                                            1 = when corresponding strap QLM*_HOST_MODE=1
+
+                                                         For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field
+                                                         is initialized to 0 on cold reset. */
+	uint64_t rst_drv                      : 1;  /**< Controls whether corresponding PERST*_L chip pin
+                                                           is driven by the OCTEON.  A warm/soft reset
+                                                           will not change this field.  On cold reset,
+                                                           this field is initialized as follows:
+                                                            0 = when corresponding strap QLM*_HOST_MODE=0
+                                                            1 = when corresponding strap QLM*_HOST_MODE=1
+
+                                                           When set, OCTEON drives the corresponding
+                                                           PERST*_L pin. Otherwise, OCTEON does not drive
+                                                           the corresponding PERST*_L pin.
+
+                                                         For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field
+                                                         is reserved/RAZ. */
+	uint64_t rst_rcv                      : 1;  /**< Controls whether corresponding PERST*_L chip pin
+                                                           is recieved by OCTEON.  A warm/soft reset
+                                                           will not change this field.  On cold reset,
+                                                           this field is initialized as follows:
                                                             0 = when corresponding strap QLM*_HOST_MODE=1
                                                             1 = when corresponding strap QLM*_HOST_MODE=0
 
+                                                           When RST_RCV==1, the PERST*_L value is
+                                                           received and may be used to reset the
+                                                           controller and (optionally, based on RST_CHIP)
+                                                           warm reset the chip.
+
+                                                           When RST_RCV==1 (and RST_CHIP=0),
+                                                           MIO_RST_INT[PERST*] gets set when the PERST*_L
+                                                           pin asserts. (This interrupt can alert SW
+                                                           whenever the external reset pin initiates a
+                                                           controller reset sequence.)
+
+                                                           RST_VAL gives the PERST*_L pin value when
+                                                           RST_RCV==1.
+
+                                                           When RST_RCV==0, the PERST*_L pin value is
+                                                           ignored.
+
+                                                         For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field
+                                                         is reserved/RAZ. */
+	uint64_t rst_chip                     : 1;  /**< Controls whether corresponding PERST*_L chip
+                                                           pin causes a chip warm reset like CHIP_RESET_L.
+                                                           A warm/soft reset will not change this field.
+                                                           On cold reset, this field is initialized to 0.
+
+                                                           RST_CHIP is not used when RST_RCV==0.
+
+                                                           When RST_RCV==0, RST_CHIP is ignored.
+
+                                                           When RST_RCV==1, RST_CHIP==1, and PERST*_L
+                                                           asserts, a chip warm reset will be generated.
+
+                                                         For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field
+                                                         is reserved/RAZ. */
+	uint64_t rst_val                      : 1;  /**< Read-only access to corresponding PERST*_L pin
+                                                           Unpredictable when RST_RCV==0. Reads as 1 when
+                                                           RST_RCV==1 and the PERST*_L pin is asserted.
+                                                           Reads as 0 when RST_RCV==1 and the PERST*_L
+                                                           pin is not asserted.
+
+                                                         For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field
+                                                         is reserved/RAZ. */
+#else
+	uint64_t rst_val                      : 1;
+	uint64_t rst_chip                     : 1;
+	uint64_t rst_rcv                      : 1;
+	uint64_t rst_drv                      : 1;
+	uint64_t prtmode                      : 2;
+	uint64_t host_mode                    : 1;
+	uint64_t rst_link                     : 1;
+	uint64_t rst_done                     : 1;
+	uint64_t prst_link                    : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn66xx;
+	struct cvmx_mio_rst_cntlx_cn66xx      cn68xx;
+	struct cvmx_mio_rst_cntlx_s           cnf71xx;
+};
+typedef union cvmx_mio_rst_cntlx cvmx_mio_rst_cntlx_t;
+
+/**
+ * cvmx_mio_rst_ctl#
+ *
+ * Notes:
+ * GEN1_Only mode is enabled for PEM0 when QLM1_SPD[0] is set or when sclk < 550Mhz.
+ * GEN1_Only mode is enabled for PEM1 when QLM1_SPD[1] is set or when sclk < 550Mhz.
+ */
+union cvmx_mio_rst_ctlx {
+	uint64_t u64;
+	struct cvmx_mio_rst_ctlx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_13_63               : 51;
+	uint64_t in_rev_ln                    : 1;  /**< RO access to corresponding pin PCIE*_REV_LANES
+                                                         which is used for initial value for REV_LANES
+                                                         For INT0/CNTL0: pin PCIE0_REV_LANES
+                                                         For INT1/CNTL1: always zero as no PCIE1 pin */
+	uint64_t rev_lanes                    : 1;  /**< Reverse the lanes for INT*.
+                                                         A warm/soft reset will not change this field.
+                                                         On cold reset, this field is initialized to
+                                                         IN_REVLANE value.
+                                                         When QLM1_CFG=1, INT0(PEM0) REV_LANES internal
+                                                         setting will be always forced to '0', INT1(PEM1)
+                                                         will be forced to '1' regardless CSR value. */
+	uint64_t gen1_only                    : 1;  /**< Disable PCIE GEN2 Capability.  This bit is
+                                                         always unpredictable whenever the controller
+                                                         is not attached to any SerDes lanes, and is
+                                                         otherwise always set when SCLK is slower than
+                                                         550Mhz.
+                                                         The MIO_RST_CNTL*[GEN1_ONLY] value is based on
+                                                         the MIO_QLM1_CFG[QLM_SPD] value. */
+	uint64_t prst_link                    : 1;  /**< Controls whether corresponding controller
+                                                         link-down or hot-reset causes the assertion of
+                                                         CIU_SOFT_PRST*[SOFT_PRST]
+
+                                                         A warm/soft reset will not change this field.
+                                                         On cold reset, this field is initialized to 0 */
+	uint64_t rst_done                     : 1;  /**< Read-only access to controller reset status
+
+                                                         RESET_DONE is always zero (i.e. the controller
+                                                         is held in reset) when:
+                                                           - CIU_SOFT_PRST*[SOFT_PRST]=1, or
+                                                           - RST_RCV==1 and PERST*_L pin is asserted */
+	uint64_t rst_link                     : 1;  /**< Controls whether corresponding controller
+                                                         link-down or hot-reset causes a warm chip reset
+                                                         On cold reset, this field is initialized as
+                                                         follows:
+                                                            0 = when corresponding HOST_MODE=1
+                                                            1 = when corresponding HOST_MODE=0
+
+                                                         Note that a link-down or hot-reset event can
+                                                         never cause a warm chip reset when the
+                                                         controller is in reset (i.e. can never cause a
+                                                         warm reset when RST_DONE==0). */
+	uint64_t host_mode                    : 1;  /**< RO access to corresponding strap PCIE*_HOST_MODE
+                                                         For CNTL1/INT1, HOST_MODE is always '1' because
+                                                         there is no PCIE1_HOST_MODE pin. */
+	uint64_t prtmode                      : 2;  /**< Port mode
+                                                            0 = port is EP mode
+                                                            1 = port is RC mode
+                                                            2,3 = Reserved
+                                                         A warm/soft reset will not change this field.
+                                                         On cold reset, this field is initialized as
+                                                         HOST_MODE (corresponding strap PCIE*_HOST_MODE) */
+	uint64_t rst_drv                      : 1;  /**< Controls whether corresponding PERST*_L chip pin
+                                                         is driven by the OCTEON.  A warm/soft reset
+                                                         will not change this field.  On cold reset,
+                                                         this field is initialized as follows:
+                                                          0 = when corresponding HOST_MODE=0
+                                                          1 = when corresponding HOST_MODE=1
+
+                                                         When set, OCTEON drives the corresponding
+                                                         PERST*_L pin. Otherwise, OCTEON does not drive
+                                                         the corresponding PERST*_L pin. */
+	uint64_t rst_rcv                      : 1;  /**< Controls whether corresponding PERST*_L chip pin
+                                                         is recieved by OCTEON.  A warm/soft reset
+                                                         will not change this field.  On cold reset,
+                                                         this field is initialized as follows:
+                                                          0 = when corresponding HOST_MODE=1
+                                                          1 = when corresponding HOST_MODE=0
+
+                                                         When RST_RCV==1, the PERST*_L value is
+                                                         received and may be used to reset the
+                                                         controller and (optionally, based on RST_CHIP)
+                                                         warm reset the chip.
+
+                                                         When RST_RCV==1 (and RST_CHIP=0),
+                                                         MIO_RST_INT[PERST*] gets set when the PERST*_L
+                                                         pin asserts. (This interrupt can alert SW
+                                                         whenever the external reset pin initiates a
+                                                         controller reset sequence.)
+
+                                                         RST_VAL gives the PERST*_L pin value when
+                                                         RST_RCV==1.
+
+                                                         When RST_RCV==0, the PERST*_L pin value is
+                                                         ignored. */
+	uint64_t rst_chip                     : 1;  /**< Controls whether corresponding PERST*_L chip
+                                                         pin causes a chip warm reset like CHIP_RESET_L.
+                                                         A warm/soft reset will not change this field.
+                                                         On cold reset, this field is initialized to 0.
+
+                                                         RST_CHIP is not used when RST_RCV==0.
+
+                                                         When RST_RCV==0, RST_CHIP is ignored.
+
+                                                         When RST_RCV==1, RST_CHIP==1, and PERST*_L
+                                                         asserts, a chip warm reset will be generated. */
+	uint64_t rst_val                      : 1;  /**< Read-only access to corresponding PERST*_L pin
+                                                         Unpredictable when RST_RCV==0. Reads as 1 when
+                                                         RST_RCV==1 and the PERST*_L pin is asserted.
+                                                         Reads as 0 when RST_RCV==1 and the PERST*_L
+                                                         pin is not asserted. */
+#else
+	uint64_t rst_val                      : 1;
+	uint64_t rst_chip                     : 1;
+	uint64_t rst_rcv                      : 1;
+	uint64_t rst_drv                      : 1;
+	uint64_t prtmode                      : 2;
+	uint64_t host_mode                    : 1;
+	uint64_t rst_link                     : 1;
+	uint64_t rst_done                     : 1;
+	uint64_t prst_link                    : 1;
+	uint64_t gen1_only                    : 1;
+	uint64_t rev_lanes                    : 1;
+	uint64_t in_rev_ln                    : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_mio_rst_ctlx_s            cn61xx;
+	struct cvmx_mio_rst_ctlx_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t prst_link                    : 1;  /**< Controls whether corresponding controller
+                                                         link-down or hot-reset causes the assertion of
+                                                         CIU_SOFT_PRST*[SOFT_PRST]
+
+                                                         A warm/soft reset will not change this field.
+                                                         On cold reset, this field is initialized to 0
+
                                                          ***NOTE: Added in pass 2.0 */
 	uint64_t rst_done                     : 1;  /**< Read-only access to controller reset status
 
@@ -4080,11 +6922,9 @@ union cvmx_mio_rst_ctlx
 	uint64_t prst_link                    : 1;
 	uint64_t reserved_10_63               : 54;
 #endif
-	} s;
-	struct cvmx_mio_rst_ctlx_s            cn63xx;
-	struct cvmx_mio_rst_ctlx_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	} cn63xx;
+	struct cvmx_mio_rst_ctlx_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t rst_done                     : 1;  /**< Read-only access to controller reset status
 
@@ -4174,37 +7014,44 @@ union cvmx_mio_rst_ctlx
 	uint64_t reserved_9_63                : 55;
 #endif
 	} cn63xxp1;
+	struct cvmx_mio_rst_ctlx_cn63xx       cn66xx;
+	struct cvmx_mio_rst_ctlx_cn63xx       cn68xx;
+	struct cvmx_mio_rst_ctlx_cn63xx       cn68xxp1;
+	struct cvmx_mio_rst_ctlx_s            cnf71xx;
 };
 typedef union cvmx_mio_rst_ctlx cvmx_mio_rst_ctlx_t;
 
 /**
  * cvmx_mio_rst_delay
  */
-union cvmx_mio_rst_delay
-{
+union cvmx_mio_rst_delay {
 	uint64_t u64;
-	struct cvmx_mio_rst_delay_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_rst_delay_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
-	uint64_t soft_rst_dly                 : 16; /**< A soft reset immediately causes an early soft
+	uint64_t warm_rst_dly                 : 16; /**< A warm reset immediately causes an early warm
                                                          reset notification.  However, the assertion of
-                                                         soft reset will be delayed this many sclks.
+                                                         warm reset will be delayed this many sclks.
                                                          A warm/soft reset will not change this field.
                                                          NOTE: This must be at least 500 dclks */
-	uint64_t warm_rst_dly                 : 16; /**< A warm reset immediately causes an early warm
+	uint64_t soft_rst_dly                 : 16; /**< A soft reset immediately causes an early soft
                                                          reset notification.  However, the assertion of
-                                                         warm reset will be delayed this many sclks.
+                                                         soft reset will be delayed this many sclks.
                                                          A warm/soft reset will not change this field.
                                                          NOTE: This must be at least 500 dclks */
 #else
-	uint64_t warm_rst_dly                 : 16;
 	uint64_t soft_rst_dly                 : 16;
+	uint64_t warm_rst_dly                 : 16;
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_mio_rst_delay_s           cn61xx;
 	struct cvmx_mio_rst_delay_s           cn63xx;
 	struct cvmx_mio_rst_delay_s           cn63xxp1;
+	struct cvmx_mio_rst_delay_s           cn66xx;
+	struct cvmx_mio_rst_delay_s           cn68xx;
+	struct cvmx_mio_rst_delay_s           cn68xxp1;
+	struct cvmx_mio_rst_delay_s           cnf71xx;
 };
 typedef union cvmx_mio_rst_delay cvmx_mio_rst_delay_t;
 
@@ -4214,12 +7061,41 @@ typedef union cvmx_mio_rst_delay cvmx_mio_rst_delay_t;
  * MIO_RST_INT = MIO Reset Interrupt Register
  *
  */
-union cvmx_mio_rst_int
-{
+union cvmx_mio_rst_int {
 	uint64_t u64;
-	struct cvmx_mio_rst_int_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_rst_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t perst1                       : 1;  /**< PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1
+                                                         and MIO_RST_CTL1[RST_CHIP]=0 */
+	uint64_t perst0                       : 1;  /**< PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1
+                                                         and MIO_RST_CTL0[RST_CHIP]=0 */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t rst_link3                    : 1;  /**< A controller3 link-down/hot-reset occurred while
+                                                         MIO_RST_CNTL3[RST_LINK]=0.  Software must assert
+                                                         then de-assert CIU_SOFT_PRST3[SOFT_PRST] */
+	uint64_t rst_link2                    : 1;  /**< A controller2 link-down/hot-reset occurred while
+                                                         MIO_RST_CNTL2[RST_LINK]=0.  Software must assert
+                                                         then de-assert CIU_SOFT_PRST2[SOFT_PRST] */
+	uint64_t rst_link1                    : 1;  /**< A controller1 link-down/hot-reset occurred while
+                                                         MIO_RST_CTL1[RST_LINK]=0.  Software must assert
+                                                         then de-assert CIU_SOFT_PRST1[SOFT_PRST] */
+	uint64_t rst_link0                    : 1;  /**< A controller0 link-down/hot-reset occurred while
+                                                         MIO_RST_CTL0[RST_LINK]=0.  Software must assert
+                                                         then de-assert CIU_SOFT_PRST[SOFT_PRST] */
+#else
+	uint64_t rst_link0                    : 1;
+	uint64_t rst_link1                    : 1;
+	uint64_t rst_link2                    : 1;
+	uint64_t rst_link3                    : 1;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t perst0                       : 1;
+	uint64_t perst1                       : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_mio_rst_int_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t perst1                       : 1;  /**< PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1
                                                          and MIO_RST_CTL1[RST_CHIP]=0 */
@@ -4240,9 +7116,13 @@ union cvmx_mio_rst_int
 	uint64_t perst1                       : 1;
 	uint64_t reserved_10_63               : 54;
 #endif
-	} s;
-	struct cvmx_mio_rst_int_s             cn63xx;
-	struct cvmx_mio_rst_int_s             cn63xxp1;
+	} cn61xx;
+	struct cvmx_mio_rst_int_cn61xx        cn63xx;
+	struct cvmx_mio_rst_int_cn61xx        cn63xxp1;
+	struct cvmx_mio_rst_int_s             cn66xx;
+	struct cvmx_mio_rst_int_cn61xx        cn68xx;
+	struct cvmx_mio_rst_int_cn61xx        cn68xxp1;
+	struct cvmx_mio_rst_int_cn61xx        cnf71xx;
 };
 typedef union cvmx_mio_rst_int cvmx_mio_rst_int_t;
 
@@ -4252,12 +7132,31 @@ typedef union cvmx_mio_rst_int cvmx_mio_rst_int_t;
  * MIO_RST_INT_EN = MIO Reset Interrupt Enable Register
  *
  */
-union cvmx_mio_rst_int_en
-{
+union cvmx_mio_rst_int_en {
 	uint64_t u64;
-	struct cvmx_mio_rst_int_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_rst_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t perst1                       : 1;  /**< Controller1 PERST reset interrupt enable */
+	uint64_t perst0                       : 1;  /**< Controller0 PERST reset interrupt enable */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t rst_link3                    : 1;  /**< Controller3 link-down/hot reset interrupt enable */
+	uint64_t rst_link2                    : 1;  /**< Controller2 link-down/hot reset interrupt enable */
+	uint64_t rst_link1                    : 1;  /**< Controller1 link-down/hot reset interrupt enable */
+	uint64_t rst_link0                    : 1;  /**< Controller0 link-down/hot reset interrupt enable */
+#else
+	uint64_t rst_link0                    : 1;
+	uint64_t rst_link1                    : 1;
+	uint64_t rst_link2                    : 1;
+	uint64_t rst_link3                    : 1;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t perst0                       : 1;
+	uint64_t perst1                       : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_mio_rst_int_en_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t perst1                       : 1;  /**< Controller1 PERST reset interrupt enable */
 	uint64_t perst0                       : 1;  /**< Controller0 PERST reset interrupt enable */
@@ -4272,9 +7171,13 @@ union cvmx_mio_rst_int_en
 	uint64_t perst1                       : 1;
 	uint64_t reserved_10_63               : 54;
 #endif
-	} s;
-	struct cvmx_mio_rst_int_en_s          cn63xx;
-	struct cvmx_mio_rst_int_en_s          cn63xxp1;
+	} cn61xx;
+	struct cvmx_mio_rst_int_en_cn61xx     cn63xx;
+	struct cvmx_mio_rst_int_en_cn61xx     cn63xxp1;
+	struct cvmx_mio_rst_int_en_s          cn66xx;
+	struct cvmx_mio_rst_int_en_cn61xx     cn68xx;
+	struct cvmx_mio_rst_int_en_cn61xx     cn68xxp1;
+	struct cvmx_mio_rst_int_en_cn61xx     cnf71xx;
 };
 typedef union cvmx_mio_rst_int_en cvmx_mio_rst_int_en_t;
 
@@ -4298,12 +7201,10 @@ typedef union cvmx_mio_rst_int_en cvmx_mio_rst_int_en_t;
  * override the current state of the TWSI bus (SCL_OVR and SDA_OVR).  Setting an override bit high will
  * result in the open drain driver being activated, thus driving the corresponding signal low.
  */
-union cvmx_mio_twsx_int
-{
+union cvmx_mio_twsx_int {
 	uint64_t u64;
-	struct cvmx_mio_twsx_int_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_twsx_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t scl                          : 1;  /**< SCL */
 	uint64_t sda                          : 1;  /**< SDA */
@@ -4336,9 +7237,8 @@ union cvmx_mio_twsx_int
 	struct cvmx_mio_twsx_int_s            cn30xx;
 	struct cvmx_mio_twsx_int_s            cn31xx;
 	struct cvmx_mio_twsx_int_s            cn38xx;
-	struct cvmx_mio_twsx_int_cn38xxp2
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_twsx_int_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t core_en                      : 1;  /**< TWSI core interrupt enable */
 	uint64_t ts_en                        : 1;  /**< MIO_TWS_TWSI_SW register update interrupt enable */
@@ -4365,8 +7265,13 @@ union cvmx_mio_twsx_int
 	struct cvmx_mio_twsx_int_s            cn56xxp1;
 	struct cvmx_mio_twsx_int_s            cn58xx;
 	struct cvmx_mio_twsx_int_s            cn58xxp1;
+	struct cvmx_mio_twsx_int_s            cn61xx;
 	struct cvmx_mio_twsx_int_s            cn63xx;
 	struct cvmx_mio_twsx_int_s            cn63xxp1;
+	struct cvmx_mio_twsx_int_s            cn66xx;
+	struct cvmx_mio_twsx_int_s            cn68xx;
+	struct cvmx_mio_twsx_int_s            cn68xxp1;
+	struct cvmx_mio_twsx_int_s            cnf71xx;
 };
 typedef union cvmx_mio_twsx_int cvmx_mio_twsx_int_t;
 
@@ -4385,12 +7290,10 @@ typedef union cvmx_mio_twsx_int cvmx_mio_twsx_int_t;
  *
  * The TWSI device considers this register valid when V==1 and SLONLY==1.
  */
-union cvmx_mio_twsx_sw_twsi
-{
+union cvmx_mio_twsx_sw_twsi {
 	uint64_t u64;
-	struct cvmx_mio_twsx_sw_twsi_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_twsx_sw_twsi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t v                            : 1;  /**< Valid bit
                                                          - Set on a write (should always be written with
                                                            a 1)
@@ -4498,8 +7401,13 @@ union cvmx_mio_twsx_sw_twsi
 	struct cvmx_mio_twsx_sw_twsi_s        cn56xxp1;
 	struct cvmx_mio_twsx_sw_twsi_s        cn58xx;
 	struct cvmx_mio_twsx_sw_twsi_s        cn58xxp1;
+	struct cvmx_mio_twsx_sw_twsi_s        cn61xx;
 	struct cvmx_mio_twsx_sw_twsi_s        cn63xx;
 	struct cvmx_mio_twsx_sw_twsi_s        cn63xxp1;
+	struct cvmx_mio_twsx_sw_twsi_s        cn66xx;
+	struct cvmx_mio_twsx_sw_twsi_s        cn68xx;
+	struct cvmx_mio_twsx_sw_twsi_s        cn68xxp1;
+	struct cvmx_mio_twsx_sw_twsi_s        cnf71xx;
 };
 typedef union cvmx_mio_twsx_sw_twsi cvmx_mio_twsx_sw_twsi_t;
 
@@ -4514,12 +7422,10 @@ typedef union cvmx_mio_twsx_sw_twsi cvmx_mio_twsx_sw_twsi_t;
  * MIO_TWS_SW_TWSI is set.  D extends the data field of MIO_TWS_SW_TWSI for a total of 8 bytes (SOVR
  * must be set to perform operations greater than 4 bytes).
  */
-union cvmx_mio_twsx_sw_twsi_ext
-{
+union cvmx_mio_twsx_sw_twsi_ext {
 	uint64_t u64;
-	struct cvmx_mio_twsx_sw_twsi_ext_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_twsx_sw_twsi_ext_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t ia                           : 8;  /**< Extended Internal Address */
 	uint64_t d                            : 32; /**< Extended Data Field */
@@ -4540,8 +7446,13 @@ union cvmx_mio_twsx_sw_twsi_ext
 	struct cvmx_mio_twsx_sw_twsi_ext_s    cn56xxp1;
 	struct cvmx_mio_twsx_sw_twsi_ext_s    cn58xx;
 	struct cvmx_mio_twsx_sw_twsi_ext_s    cn58xxp1;
+	struct cvmx_mio_twsx_sw_twsi_ext_s    cn61xx;
 	struct cvmx_mio_twsx_sw_twsi_ext_s    cn63xx;
 	struct cvmx_mio_twsx_sw_twsi_ext_s    cn63xxp1;
+	struct cvmx_mio_twsx_sw_twsi_ext_s    cn66xx;
+	struct cvmx_mio_twsx_sw_twsi_ext_s    cn68xx;
+	struct cvmx_mio_twsx_sw_twsi_ext_s    cn68xxp1;
+	struct cvmx_mio_twsx_sw_twsi_ext_s    cnf71xx;
 };
 typedef union cvmx_mio_twsx_sw_twsi_ext cvmx_mio_twsx_sw_twsi_ext_t;
 
@@ -4558,12 +7469,10 @@ typedef union cvmx_mio_twsx_sw_twsi_ext cvmx_mio_twsx_sw_twsi_ext_t;
  *
  * The TWSI device considers this register valid when V==1.
  */
-union cvmx_mio_twsx_twsi_sw
-{
+union cvmx_mio_twsx_twsi_sw {
 	uint64_t u64;
-	struct cvmx_mio_twsx_twsi_sw_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_twsx_twsi_sw_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t v                            : 2;  /**< Valid Bits
                                                          - Not directly writable
                                                          - Set to 1 on any write by the TWSI device
@@ -4587,8 +7496,13 @@ union cvmx_mio_twsx_twsi_sw
 	struct cvmx_mio_twsx_twsi_sw_s        cn56xxp1;
 	struct cvmx_mio_twsx_twsi_sw_s        cn58xx;
 	struct cvmx_mio_twsx_twsi_sw_s        cn58xxp1;
+	struct cvmx_mio_twsx_twsi_sw_s        cn61xx;
 	struct cvmx_mio_twsx_twsi_sw_s        cn63xx;
 	struct cvmx_mio_twsx_twsi_sw_s        cn63xxp1;
+	struct cvmx_mio_twsx_twsi_sw_s        cn66xx;
+	struct cvmx_mio_twsx_twsi_sw_s        cn68xx;
+	struct cvmx_mio_twsx_twsi_sw_s        cn68xxp1;
+	struct cvmx_mio_twsx_twsi_sw_s        cnf71xx;
 };
 typedef union cvmx_mio_twsx_twsi_sw cvmx_mio_twsx_twsi_sw_t;
 
@@ -4613,12 +7527,10 @@ typedef union cvmx_mio_twsx_twsi_sw cvmx_mio_twsx_twsi_sw_t;
  * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
  * IER and DLH registers are the same.
  */
-union cvmx_mio_uartx_dlh
-{
+union cvmx_mio_uartx_dlh {
 	uint64_t u64;
-	struct cvmx_mio_uartx_dlh_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_dlh_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t dlh                          : 8;  /**< Divisor Latch High Register */
 #else
@@ -4637,8 +7549,13 @@ union cvmx_mio_uartx_dlh
 	struct cvmx_mio_uartx_dlh_s           cn56xxp1;
 	struct cvmx_mio_uartx_dlh_s           cn58xx;
 	struct cvmx_mio_uartx_dlh_s           cn58xxp1;
+	struct cvmx_mio_uartx_dlh_s           cn61xx;
 	struct cvmx_mio_uartx_dlh_s           cn63xx;
 	struct cvmx_mio_uartx_dlh_s           cn63xxp1;
+	struct cvmx_mio_uartx_dlh_s           cn66xx;
+	struct cvmx_mio_uartx_dlh_s           cn68xx;
+	struct cvmx_mio_uartx_dlh_s           cn68xxp1;
+	struct cvmx_mio_uartx_dlh_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_dlh cvmx_mio_uartx_dlh_t;
 typedef cvmx_mio_uartx_dlh_t cvmx_uart_dlh_t;
@@ -4664,12 +7581,10 @@ typedef cvmx_mio_uartx_dlh_t cvmx_uart_dlh_t;
  * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
  * RBR, THR, and DLL registers are the same.
  */
-union cvmx_mio_uartx_dll
-{
+union cvmx_mio_uartx_dll {
 	uint64_t u64;
-	struct cvmx_mio_uartx_dll_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_dll_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t dll                          : 8;  /**< Divisor Latch Low Register */
 #else
@@ -4688,8 +7603,13 @@ union cvmx_mio_uartx_dll
 	struct cvmx_mio_uartx_dll_s           cn56xxp1;
 	struct cvmx_mio_uartx_dll_s           cn58xx;
 	struct cvmx_mio_uartx_dll_s           cn58xxp1;
+	struct cvmx_mio_uartx_dll_s           cn61xx;
 	struct cvmx_mio_uartx_dll_s           cn63xx;
 	struct cvmx_mio_uartx_dll_s           cn63xxp1;
+	struct cvmx_mio_uartx_dll_s           cn66xx;
+	struct cvmx_mio_uartx_dll_s           cn68xx;
+	struct cvmx_mio_uartx_dll_s           cn68xxp1;
+	struct cvmx_mio_uartx_dll_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_dll cvmx_mio_uartx_dll_t;
 typedef cvmx_mio_uartx_dll_t cvmx_uart_dll_t;
@@ -4705,12 +7625,10 @@ typedef cvmx_mio_uartx_dll_t cvmx_uart_dll_t;
  * by software. Note, that when the FIFO access mode is enabled/disabled, the control portion of the
  * receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty.
  */
-union cvmx_mio_uartx_far
-{
+union cvmx_mio_uartx_far {
 	uint64_t u64;
-	struct cvmx_mio_uartx_far_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_far_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t far                          : 1;  /**< FIFO Access Register */
 #else
@@ -4729,8 +7647,13 @@ union cvmx_mio_uartx_far
 	struct cvmx_mio_uartx_far_s           cn56xxp1;
 	struct cvmx_mio_uartx_far_s           cn58xx;
 	struct cvmx_mio_uartx_far_s           cn58xxp1;
+	struct cvmx_mio_uartx_far_s           cn61xx;
 	struct cvmx_mio_uartx_far_s           cn63xx;
 	struct cvmx_mio_uartx_far_s           cn63xxp1;
+	struct cvmx_mio_uartx_far_s           cn66xx;
+	struct cvmx_mio_uartx_far_s           cn68xx;
+	struct cvmx_mio_uartx_far_s           cn68xxp1;
+	struct cvmx_mio_uartx_far_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_far cvmx_mio_uartx_far_t;
 typedef cvmx_mio_uartx_far_t cvmx_uart_far_t;
@@ -4779,12 +7702,10 @@ typedef cvmx_mio_uartx_far_t cvmx_uart_far_t;
  * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
  * IIR and FCR registers are the same.
  */
-union cvmx_mio_uartx_fcr
-{
+union cvmx_mio_uartx_fcr {
 	uint64_t u64;
-	struct cvmx_mio_uartx_fcr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_fcr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t rxtrig                       : 2;  /**< RX Trigger */
 	uint64_t txtrig                       : 2;  /**< TX Trigger */
@@ -4813,8 +7734,13 @@ union cvmx_mio_uartx_fcr
 	struct cvmx_mio_uartx_fcr_s           cn56xxp1;
 	struct cvmx_mio_uartx_fcr_s           cn58xx;
 	struct cvmx_mio_uartx_fcr_s           cn58xxp1;
+	struct cvmx_mio_uartx_fcr_s           cn61xx;
 	struct cvmx_mio_uartx_fcr_s           cn63xx;
 	struct cvmx_mio_uartx_fcr_s           cn63xxp1;
+	struct cvmx_mio_uartx_fcr_s           cn66xx;
+	struct cvmx_mio_uartx_fcr_s           cn68xx;
+	struct cvmx_mio_uartx_fcr_s           cn68xxp1;
+	struct cvmx_mio_uartx_fcr_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_fcr cvmx_mio_uartx_fcr_t;
 typedef cvmx_mio_uartx_fcr_t cvmx_uart_fcr_t;
@@ -4828,12 +7754,10 @@ typedef cvmx_mio_uartx_fcr_t cvmx_uart_fcr_t;
  * filled by software when FIFOs are enabled. If FIFOs are not enabled, setting the HTX register will
  * have no effect.
  */
-union cvmx_mio_uartx_htx
-{
+union cvmx_mio_uartx_htx {
 	uint64_t u64;
-	struct cvmx_mio_uartx_htx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_htx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t htx                          : 1;  /**< Halt TX */
 #else
@@ -4852,8 +7776,13 @@ union cvmx_mio_uartx_htx
 	struct cvmx_mio_uartx_htx_s           cn56xxp1;
 	struct cvmx_mio_uartx_htx_s           cn58xx;
 	struct cvmx_mio_uartx_htx_s           cn58xxp1;
+	struct cvmx_mio_uartx_htx_s           cn61xx;
 	struct cvmx_mio_uartx_htx_s           cn63xx;
 	struct cvmx_mio_uartx_htx_s           cn63xxp1;
+	struct cvmx_mio_uartx_htx_s           cn66xx;
+	struct cvmx_mio_uartx_htx_s           cn68xx;
+	struct cvmx_mio_uartx_htx_s           cn68xxp1;
+	struct cvmx_mio_uartx_htx_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_htx cvmx_mio_uartx_htx_t;
 typedef cvmx_mio_uartx_htx_t cvmx_uart_htx_t;
@@ -4876,12 +7805,10 @@ typedef cvmx_mio_uartx_htx_t cvmx_uart_htx_t;
  * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
  * IER and DLH registers are the same.
  */
-union cvmx_mio_uartx_ier
-{
+union cvmx_mio_uartx_ier {
 	uint64_t u64;
-	struct cvmx_mio_uartx_ier_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_ier_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t ptime                        : 1;  /**< Programmable THRE Interrupt mode enable */
 	uint64_t reserved_4_6                 : 3;
@@ -4910,8 +7837,13 @@ union cvmx_mio_uartx_ier
 	struct cvmx_mio_uartx_ier_s           cn56xxp1;
 	struct cvmx_mio_uartx_ier_s           cn58xx;
 	struct cvmx_mio_uartx_ier_s           cn58xxp1;
+	struct cvmx_mio_uartx_ier_s           cn61xx;
 	struct cvmx_mio_uartx_ier_s           cn63xx;
 	struct cvmx_mio_uartx_ier_s           cn63xxp1;
+	struct cvmx_mio_uartx_ier_s           cn66xx;
+	struct cvmx_mio_uartx_ier_s           cn68xx;
+	struct cvmx_mio_uartx_ier_s           cn68xxp1;
+	struct cvmx_mio_uartx_ier_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_ier cvmx_mio_uartx_ier_t;
 typedef cvmx_mio_uartx_ier_t cvmx_uart_ier_t;
@@ -4965,12 +7897,10 @@ typedef cvmx_mio_uartx_ier_t cvmx_uart_ier_t;
  * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
  * IIR and FCR registers are the same.
  */
-union cvmx_mio_uartx_iir
-{
+union cvmx_mio_uartx_iir {
 	uint64_t u64;
-	struct cvmx_mio_uartx_iir_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_iir_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t fen                          : 2;  /**< FIFO-enabled bits */
 	uint64_t reserved_4_5                 : 2;
@@ -4993,8 +7923,13 @@ union cvmx_mio_uartx_iir
 	struct cvmx_mio_uartx_iir_s           cn56xxp1;
 	struct cvmx_mio_uartx_iir_s           cn58xx;
 	struct cvmx_mio_uartx_iir_s           cn58xxp1;
+	struct cvmx_mio_uartx_iir_s           cn61xx;
 	struct cvmx_mio_uartx_iir_s           cn63xx;
 	struct cvmx_mio_uartx_iir_s           cn63xxp1;
+	struct cvmx_mio_uartx_iir_s           cn66xx;
+	struct cvmx_mio_uartx_iir_s           cn68xx;
+	struct cvmx_mio_uartx_iir_s           cn68xxp1;
+	struct cvmx_mio_uartx_iir_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_iir cvmx_mio_uartx_iir_t;
 typedef cvmx_mio_uartx_iir_t cvmx_uart_iir_t;
@@ -5041,12 +7976,10 @@ typedef cvmx_mio_uartx_iir_t cvmx_uart_iir_t;
  * Status Register (USR) is clear). The LCR is always readable. In PASS3, the LCR is always writable
  * because the BUSY bit is always clear.
  */
-union cvmx_mio_uartx_lcr
-{
+union cvmx_mio_uartx_lcr {
 	uint64_t u64;
-	struct cvmx_mio_uartx_lcr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_lcr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t dlab                         : 1;  /**< Divisor Latch Address bit */
 	uint64_t brk                          : 1;  /**< Break Control bit */
@@ -5077,8 +8010,13 @@ union cvmx_mio_uartx_lcr
 	struct cvmx_mio_uartx_lcr_s           cn56xxp1;
 	struct cvmx_mio_uartx_lcr_s           cn58xx;
 	struct cvmx_mio_uartx_lcr_s           cn58xxp1;
+	struct cvmx_mio_uartx_lcr_s           cn61xx;
 	struct cvmx_mio_uartx_lcr_s           cn63xx;
 	struct cvmx_mio_uartx_lcr_s           cn63xxp1;
+	struct cvmx_mio_uartx_lcr_s           cn66xx;
+	struct cvmx_mio_uartx_lcr_s           cn68xx;
+	struct cvmx_mio_uartx_lcr_s           cn68xxp1;
+	struct cvmx_mio_uartx_lcr_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_lcr cvmx_mio_uartx_lcr_t;
 typedef cvmx_mio_uartx_lcr_t cvmx_uart_lcr_t;
@@ -5145,12 +8083,10 @@ typedef cvmx_mio_uartx_lcr_t cvmx_uart_lcr_t;
  * bit is cleared when the LSR is read and the character with the error is at the top of the receiver
  * FIFO and there are no subsequent errors in the FIFO.
  */
-union cvmx_mio_uartx_lsr
-{
+union cvmx_mio_uartx_lsr {
 	uint64_t u64;
-	struct cvmx_mio_uartx_lsr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_lsr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t ferr                         : 1;  /**< Error in Receiver FIFO bit */
 	uint64_t temt                         : 1;  /**< Transmitter Empty bit */
@@ -5183,8 +8119,13 @@ union cvmx_mio_uartx_lsr
 	struct cvmx_mio_uartx_lsr_s           cn56xxp1;
 	struct cvmx_mio_uartx_lsr_s           cn58xx;
 	struct cvmx_mio_uartx_lsr_s           cn58xxp1;
+	struct cvmx_mio_uartx_lsr_s           cn61xx;
 	struct cvmx_mio_uartx_lsr_s           cn63xx;
 	struct cvmx_mio_uartx_lsr_s           cn63xxp1;
+	struct cvmx_mio_uartx_lsr_s           cn66xx;
+	struct cvmx_mio_uartx_lsr_s           cn68xx;
+	struct cvmx_mio_uartx_lsr_s           cn68xxp1;
+	struct cvmx_mio_uartx_lsr_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_lsr cvmx_mio_uartx_lsr_t;
 typedef cvmx_mio_uartx_lsr_t cvmx_uart_lsr_t;
@@ -5259,12 +8200,10 @@ typedef cvmx_mio_uartx_lsr_t cvmx_uart_lsr_t;
  * disabled through FCR[0]. When Auto CTS is disabled or inactive, the transmitter is unaffected by
  * cts_n.
  */
-union cvmx_mio_uartx_mcr
-{
+union cvmx_mio_uartx_mcr {
 	uint64_t u64;
-	struct cvmx_mio_uartx_mcr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_mcr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t afce                         : 1;  /**< Auto Flow Control Enable bit */
 	uint64_t loop                         : 1;  /**< Loopback bit */
@@ -5293,8 +8232,13 @@ union cvmx_mio_uartx_mcr
 	struct cvmx_mio_uartx_mcr_s           cn56xxp1;
 	struct cvmx_mio_uartx_mcr_s           cn58xx;
 	struct cvmx_mio_uartx_mcr_s           cn58xxp1;
+	struct cvmx_mio_uartx_mcr_s           cn61xx;
 	struct cvmx_mio_uartx_mcr_s           cn63xx;
 	struct cvmx_mio_uartx_mcr_s           cn63xxp1;
+	struct cvmx_mio_uartx_mcr_s           cn66xx;
+	struct cvmx_mio_uartx_mcr_s           cn68xx;
+	struct cvmx_mio_uartx_mcr_s           cn68xxp1;
+	struct cvmx_mio_uartx_mcr_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_mcr cvmx_mio_uartx_mcr_t;
 typedef cvmx_mio_uartx_mcr_t cvmx_uart_mcr_t;
@@ -5329,12 +8273,10 @@ typedef cvmx_mio_uartx_mcr_t cvmx_uart_mcr_t;
  * inputs are internally tied to power and not present on the pins of chip. Thus the UART1 DSR, RI, and
  * DCD bits will be '0' when not in Loopback mode.
  */
-union cvmx_mio_uartx_msr
-{
+union cvmx_mio_uartx_msr {
 	uint64_t u64;
-	struct cvmx_mio_uartx_msr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_msr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t dcd                          : 1;  /**< Data Carrier Detect input bit */
 	uint64_t ri                           : 1;  /**< Ring Indicator input bit */
@@ -5367,8 +8309,13 @@ union cvmx_mio_uartx_msr
 	struct cvmx_mio_uartx_msr_s           cn56xxp1;
 	struct cvmx_mio_uartx_msr_s           cn58xx;
 	struct cvmx_mio_uartx_msr_s           cn58xxp1;
+	struct cvmx_mio_uartx_msr_s           cn61xx;
 	struct cvmx_mio_uartx_msr_s           cn63xx;
 	struct cvmx_mio_uartx_msr_s           cn63xxp1;
+	struct cvmx_mio_uartx_msr_s           cn66xx;
+	struct cvmx_mio_uartx_msr_s           cn68xx;
+	struct cvmx_mio_uartx_msr_s           cn68xxp1;
+	struct cvmx_mio_uartx_msr_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_msr cvmx_mio_uartx_msr_t;
 typedef cvmx_mio_uartx_msr_t cvmx_uart_msr_t;
@@ -5392,12 +8339,10 @@ typedef cvmx_mio_uartx_msr_t cvmx_uart_msr_t;
  * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
  * RBR, THR, and DLL registers are the same.
  */
-union cvmx_mio_uartx_rbr
-{
+union cvmx_mio_uartx_rbr {
 	uint64_t u64;
-	struct cvmx_mio_uartx_rbr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_rbr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t rbr                          : 8;  /**< Receive Buffer Register */
 #else
@@ -5416,8 +8361,13 @@ union cvmx_mio_uartx_rbr
 	struct cvmx_mio_uartx_rbr_s           cn56xxp1;
 	struct cvmx_mio_uartx_rbr_s           cn58xx;
 	struct cvmx_mio_uartx_rbr_s           cn58xxp1;
+	struct cvmx_mio_uartx_rbr_s           cn61xx;
 	struct cvmx_mio_uartx_rbr_s           cn63xx;
 	struct cvmx_mio_uartx_rbr_s           cn63xxp1;
+	struct cvmx_mio_uartx_rbr_s           cn66xx;
+	struct cvmx_mio_uartx_rbr_s           cn68xx;
+	struct cvmx_mio_uartx_rbr_s           cn68xxp1;
+	struct cvmx_mio_uartx_rbr_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_rbr cvmx_mio_uartx_rbr_t;
 typedef cvmx_mio_uartx_rbr_t cvmx_uart_rbr_t;
@@ -5429,12 +8379,10 @@ typedef cvmx_mio_uartx_rbr_t cvmx_uart_rbr_t;
  *
  * The Receive FIFO Level Register (RFL) indicates the number of data entries in the receive FIFO.
  */
-union cvmx_mio_uartx_rfl
-{
+union cvmx_mio_uartx_rfl {
 	uint64_t u64;
-	struct cvmx_mio_uartx_rfl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_rfl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t rfl                          : 7;  /**< Receive FIFO Level Register */
 #else
@@ -5453,8 +8401,13 @@ union cvmx_mio_uartx_rfl
 	struct cvmx_mio_uartx_rfl_s           cn56xxp1;
 	struct cvmx_mio_uartx_rfl_s           cn58xx;
 	struct cvmx_mio_uartx_rfl_s           cn58xxp1;
+	struct cvmx_mio_uartx_rfl_s           cn61xx;
 	struct cvmx_mio_uartx_rfl_s           cn63xx;
 	struct cvmx_mio_uartx_rfl_s           cn63xxp1;
+	struct cvmx_mio_uartx_rfl_s           cn66xx;
+	struct cvmx_mio_uartx_rfl_s           cn68xx;
+	struct cvmx_mio_uartx_rfl_s           cn68xxp1;
+	struct cvmx_mio_uartx_rfl_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_rfl cvmx_mio_uartx_rfl_t;
 typedef cvmx_mio_uartx_rfl_t cvmx_uart_rfl_t;
@@ -5469,12 +8422,10 @@ typedef cvmx_mio_uartx_rfl_t cvmx_uart_rfl_t;
  * consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are
  * not enabled, this register is used to write data to the RBR.
  */
-union cvmx_mio_uartx_rfw
-{
+union cvmx_mio_uartx_rfw {
 	uint64_t u64;
-	struct cvmx_mio_uartx_rfw_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_rfw_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t rffe                         : 1;  /**< Receive FIFO Framing Error */
 	uint64_t rfpe                         : 1;  /**< Receive FIFO Parity Error */
@@ -5497,8 +8448,13 @@ union cvmx_mio_uartx_rfw
 	struct cvmx_mio_uartx_rfw_s           cn56xxp1;
 	struct cvmx_mio_uartx_rfw_s           cn58xx;
 	struct cvmx_mio_uartx_rfw_s           cn58xxp1;
+	struct cvmx_mio_uartx_rfw_s           cn61xx;
 	struct cvmx_mio_uartx_rfw_s           cn63xx;
 	struct cvmx_mio_uartx_rfw_s           cn63xxp1;
+	struct cvmx_mio_uartx_rfw_s           cn66xx;
+	struct cvmx_mio_uartx_rfw_s           cn68xx;
+	struct cvmx_mio_uartx_rfw_s           cn68xxp1;
+	struct cvmx_mio_uartx_rfw_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_rfw cvmx_mio_uartx_rfw_t;
 typedef cvmx_mio_uartx_rfw_t cvmx_uart_rfw_t;
@@ -5511,12 +8467,10 @@ typedef cvmx_mio_uartx_rfw_t cvmx_uart_rfw_t;
  * The Shadow Break Control Register (SBCR) is a shadow register for the BREAK bit (LCR bit 6) that can
  * be used to remove the burden of having to perform a read-modify-write on the LCR.
  */
-union cvmx_mio_uartx_sbcr
-{
+union cvmx_mio_uartx_sbcr {
 	uint64_t u64;
-	struct cvmx_mio_uartx_sbcr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_sbcr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t sbcr                         : 1;  /**< Shadow Break Control */
 #else
@@ -5535,8 +8489,13 @@ union cvmx_mio_uartx_sbcr
 	struct cvmx_mio_uartx_sbcr_s          cn56xxp1;
 	struct cvmx_mio_uartx_sbcr_s          cn58xx;
 	struct cvmx_mio_uartx_sbcr_s          cn58xxp1;
+	struct cvmx_mio_uartx_sbcr_s          cn61xx;
 	struct cvmx_mio_uartx_sbcr_s          cn63xx;
 	struct cvmx_mio_uartx_sbcr_s          cn63xxp1;
+	struct cvmx_mio_uartx_sbcr_s          cn66xx;
+	struct cvmx_mio_uartx_sbcr_s          cn68xx;
+	struct cvmx_mio_uartx_sbcr_s          cn68xxp1;
+	struct cvmx_mio_uartx_sbcr_s          cnf71xx;
 };
 typedef union cvmx_mio_uartx_sbcr cvmx_mio_uartx_sbcr_t;
 typedef cvmx_mio_uartx_sbcr_t cvmx_uart_sbcr_t;
@@ -5549,12 +8508,10 @@ typedef cvmx_mio_uartx_sbcr_t cvmx_uart_sbcr_t;
  * The Scratchpad Register (SCR) is an 8-bit read/write register for programmers to use as a temporary
  * storage space.
  */
-union cvmx_mio_uartx_scr
-{
+union cvmx_mio_uartx_scr {
 	uint64_t u64;
-	struct cvmx_mio_uartx_scr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_scr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t scr                          : 8;  /**< Scratchpad Register */
 #else
@@ -5573,8 +8530,13 @@ union cvmx_mio_uartx_scr
 	struct cvmx_mio_uartx_scr_s           cn56xxp1;
 	struct cvmx_mio_uartx_scr_s           cn58xx;
 	struct cvmx_mio_uartx_scr_s           cn58xxp1;
+	struct cvmx_mio_uartx_scr_s           cn61xx;
 	struct cvmx_mio_uartx_scr_s           cn63xx;
 	struct cvmx_mio_uartx_scr_s           cn63xxp1;
+	struct cvmx_mio_uartx_scr_s           cn66xx;
+	struct cvmx_mio_uartx_scr_s           cn68xx;
+	struct cvmx_mio_uartx_scr_s           cn68xxp1;
+	struct cvmx_mio_uartx_scr_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_scr cvmx_mio_uartx_scr_t;
 typedef cvmx_mio_uartx_scr_t cvmx_uart_scr_t;
@@ -5588,12 +8550,10 @@ typedef cvmx_mio_uartx_scr_t cvmx_uart_scr_t;
  * can be used to remove the burden of having to store the previously written value to the FCR in memory
  * and having to mask this value so that only the FIFO enable bit gets updated.
  */
-union cvmx_mio_uartx_sfe
-{
+union cvmx_mio_uartx_sfe {
 	uint64_t u64;
-	struct cvmx_mio_uartx_sfe_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_sfe_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t sfe                          : 1;  /**< Shadow FIFO Enable */
 #else
@@ -5612,8 +8572,13 @@ union cvmx_mio_uartx_sfe
 	struct cvmx_mio_uartx_sfe_s           cn56xxp1;
 	struct cvmx_mio_uartx_sfe_s           cn58xx;
 	struct cvmx_mio_uartx_sfe_s           cn58xxp1;
+	struct cvmx_mio_uartx_sfe_s           cn61xx;
 	struct cvmx_mio_uartx_sfe_s           cn63xx;
 	struct cvmx_mio_uartx_sfe_s           cn63xxp1;
+	struct cvmx_mio_uartx_sfe_s           cn66xx;
+	struct cvmx_mio_uartx_sfe_s           cn68xx;
+	struct cvmx_mio_uartx_sfe_s           cn68xxp1;
+	struct cvmx_mio_uartx_sfe_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_sfe cvmx_mio_uartx_sfe_t;
 typedef cvmx_mio_uartx_sfe_t cvmx_uart_sfe_t;
@@ -5636,12 +8601,10 @@ typedef cvmx_mio_uartx_sfe_t cvmx_uart_sfe_t;
  * the burden on software having to store previously written FCR values (which are pretty static) just
  * to reset the transmit FIFO.
  */
-union cvmx_mio_uartx_srr
-{
+union cvmx_mio_uartx_srr {
 	uint64_t u64;
-	struct cvmx_mio_uartx_srr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_srr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t stfr                         : 1;  /**< Shadow TX FIFO Reset */
 	uint64_t srfr                         : 1;  /**< Shadow RX FIFO Reset */
@@ -5664,8 +8627,13 @@ union cvmx_mio_uartx_srr
 	struct cvmx_mio_uartx_srr_s           cn56xxp1;
 	struct cvmx_mio_uartx_srr_s           cn58xx;
 	struct cvmx_mio_uartx_srr_s           cn58xxp1;
+	struct cvmx_mio_uartx_srr_s           cn61xx;
 	struct cvmx_mio_uartx_srr_s           cn63xx;
 	struct cvmx_mio_uartx_srr_s           cn63xxp1;
+	struct cvmx_mio_uartx_srr_s           cn66xx;
+	struct cvmx_mio_uartx_srr_s           cn68xx;
+	struct cvmx_mio_uartx_srr_s           cn68xxp1;
+	struct cvmx_mio_uartx_srr_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_srr cvmx_mio_uartx_srr_t;
 typedef cvmx_mio_uartx_srr_t cvmx_uart_srr_t;
@@ -5679,12 +8647,10 @@ typedef cvmx_mio_uartx_srr_t cvmx_uart_srr_t;
  * can be used to remove the burden of having to store the previously written value to the FCR in memory
  * and having to mask this value so that only the RX Trigger bits get updated.
  */
-union cvmx_mio_uartx_srt
-{
+union cvmx_mio_uartx_srt {
 	uint64_t u64;
-	struct cvmx_mio_uartx_srt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_srt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t srt                          : 2;  /**< Shadow RX Trigger */
 #else
@@ -5703,8 +8669,13 @@ union cvmx_mio_uartx_srt
 	struct cvmx_mio_uartx_srt_s           cn56xxp1;
 	struct cvmx_mio_uartx_srt_s           cn58xx;
 	struct cvmx_mio_uartx_srt_s           cn58xxp1;
+	struct cvmx_mio_uartx_srt_s           cn61xx;
 	struct cvmx_mio_uartx_srt_s           cn63xx;
 	struct cvmx_mio_uartx_srt_s           cn63xxp1;
+	struct cvmx_mio_uartx_srt_s           cn66xx;
+	struct cvmx_mio_uartx_srt_s           cn68xx;
+	struct cvmx_mio_uartx_srt_s           cn68xxp1;
+	struct cvmx_mio_uartx_srt_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_srt cvmx_mio_uartx_srt_t;
 typedef cvmx_mio_uartx_srt_t cvmx_uart_srt_t;
@@ -5717,12 +8688,10 @@ typedef cvmx_mio_uartx_srt_t cvmx_uart_srt_t;
  * The Shadow Request To Send Register (SRTS) is a shadow register for the RTS bit (MCR bit 1) that can
  * be used to remove the burden of having to perform a read-modify-write on the MCR.
  */
-union cvmx_mio_uartx_srts
-{
+union cvmx_mio_uartx_srts {
 	uint64_t u64;
-	struct cvmx_mio_uartx_srts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_srts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t srts                         : 1;  /**< Shadow Request To Send */
 #else
@@ -5741,8 +8710,13 @@ union cvmx_mio_uartx_srts
 	struct cvmx_mio_uartx_srts_s          cn56xxp1;
 	struct cvmx_mio_uartx_srts_s          cn58xx;
 	struct cvmx_mio_uartx_srts_s          cn58xxp1;
+	struct cvmx_mio_uartx_srts_s          cn61xx;
 	struct cvmx_mio_uartx_srts_s          cn63xx;
 	struct cvmx_mio_uartx_srts_s          cn63xxp1;
+	struct cvmx_mio_uartx_srts_s          cn66xx;
+	struct cvmx_mio_uartx_srts_s          cn68xx;
+	struct cvmx_mio_uartx_srts_s          cn68xxp1;
+	struct cvmx_mio_uartx_srts_s          cnf71xx;
 };
 typedef union cvmx_mio_uartx_srts cvmx_mio_uartx_srts_t;
 typedef cvmx_mio_uartx_srts_t cvmx_uart_srts_t;
@@ -5756,12 +8730,10 @@ typedef cvmx_mio_uartx_srts_t cvmx_uart_srts_t;
  * can be used to remove the burden of having to store the previously written value to the FCR in memory
  * and having to mask this value so that only the TX Trigger bits get updated.
  */
-union cvmx_mio_uartx_stt
-{
+union cvmx_mio_uartx_stt {
 	uint64_t u64;
-	struct cvmx_mio_uartx_stt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_stt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t stt                          : 2;  /**< Shadow TX Trigger */
 #else
@@ -5780,8 +8752,13 @@ union cvmx_mio_uartx_stt
 	struct cvmx_mio_uartx_stt_s           cn56xxp1;
 	struct cvmx_mio_uartx_stt_s           cn58xx;
 	struct cvmx_mio_uartx_stt_s           cn58xxp1;
+	struct cvmx_mio_uartx_stt_s           cn61xx;
 	struct cvmx_mio_uartx_stt_s           cn63xx;
 	struct cvmx_mio_uartx_stt_s           cn63xxp1;
+	struct cvmx_mio_uartx_stt_s           cn66xx;
+	struct cvmx_mio_uartx_stt_s           cn68xx;
+	struct cvmx_mio_uartx_stt_s           cn68xxp1;
+	struct cvmx_mio_uartx_stt_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_stt cvmx_mio_uartx_stt_t;
 typedef cvmx_mio_uartx_stt_t cvmx_uart_stt_t;
@@ -5793,12 +8770,10 @@ typedef cvmx_mio_uartx_stt_t cvmx_uart_stt_t;
  *
  * The Transmit FIFO Level Register (TFL) indicates the number of data entries in the transmit FIFO.
  */
-union cvmx_mio_uartx_tfl
-{
+union cvmx_mio_uartx_tfl {
 	uint64_t u64;
-	struct cvmx_mio_uartx_tfl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_tfl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t tfl                          : 7;  /**< Transmit FIFO Level Register */
 #else
@@ -5817,8 +8792,13 @@ union cvmx_mio_uartx_tfl
 	struct cvmx_mio_uartx_tfl_s           cn56xxp1;
 	struct cvmx_mio_uartx_tfl_s           cn58xx;
 	struct cvmx_mio_uartx_tfl_s           cn58xxp1;
+	struct cvmx_mio_uartx_tfl_s           cn61xx;
 	struct cvmx_mio_uartx_tfl_s           cn63xx;
 	struct cvmx_mio_uartx_tfl_s           cn63xxp1;
+	struct cvmx_mio_uartx_tfl_s           cn66xx;
+	struct cvmx_mio_uartx_tfl_s           cn68xx;
+	struct cvmx_mio_uartx_tfl_s           cn68xxp1;
+	struct cvmx_mio_uartx_tfl_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_tfl cvmx_mio_uartx_tfl_t;
 typedef cvmx_mio_uartx_tfl_t cvmx_uart_tfl_t;
@@ -5833,12 +8813,10 @@ typedef cvmx_mio_uartx_tfl_t cvmx_uart_tfl_t;
  * Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the
  * top of the FIFO. When FIFOs are not enabled, reading this register gives the data in the THR.
  */
-union cvmx_mio_uartx_tfr
-{
+union cvmx_mio_uartx_tfr {
 	uint64_t u64;
-	struct cvmx_mio_uartx_tfr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_tfr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t tfr                          : 8;  /**< Transmit FIFO Read Register */
 #else
@@ -5857,8 +8835,13 @@ union cvmx_mio_uartx_tfr
 	struct cvmx_mio_uartx_tfr_s           cn56xxp1;
 	struct cvmx_mio_uartx_tfr_s           cn58xx;
 	struct cvmx_mio_uartx_tfr_s           cn58xxp1;
+	struct cvmx_mio_uartx_tfr_s           cn61xx;
 	struct cvmx_mio_uartx_tfr_s           cn63xx;
 	struct cvmx_mio_uartx_tfr_s           cn63xxp1;
+	struct cvmx_mio_uartx_tfr_s           cn66xx;
+	struct cvmx_mio_uartx_tfr_s           cn68xx;
+	struct cvmx_mio_uartx_tfr_s           cn68xxp1;
+	struct cvmx_mio_uartx_tfr_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_tfr cvmx_mio_uartx_tfr_t;
 typedef cvmx_mio_uartx_tfr_t cvmx_uart_tfr_t;
@@ -5885,12 +8868,10 @@ typedef cvmx_mio_uartx_tfr_t cvmx_uart_tfr_t;
  * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
  * RBR, THR, and DLL registers are the same.
  */
-union cvmx_mio_uartx_thr
-{
+union cvmx_mio_uartx_thr {
 	uint64_t u64;
-	struct cvmx_mio_uartx_thr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_thr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t thr                          : 8;  /**< Transmit Holding Register */
 #else
@@ -5909,8 +8890,13 @@ union cvmx_mio_uartx_thr
 	struct cvmx_mio_uartx_thr_s           cn56xxp1;
 	struct cvmx_mio_uartx_thr_s           cn58xx;
 	struct cvmx_mio_uartx_thr_s           cn58xxp1;
+	struct cvmx_mio_uartx_thr_s           cn61xx;
 	struct cvmx_mio_uartx_thr_s           cn63xx;
 	struct cvmx_mio_uartx_thr_s           cn63xxp1;
+	struct cvmx_mio_uartx_thr_s           cn66xx;
+	struct cvmx_mio_uartx_thr_s           cn68xx;
+	struct cvmx_mio_uartx_thr_s           cn68xxp1;
+	struct cvmx_mio_uartx_thr_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_thr cvmx_mio_uartx_thr_t;
 typedef cvmx_mio_uartx_thr_t cvmx_uart_thr_t;
@@ -5930,12 +8916,10 @@ typedef cvmx_mio_uartx_thr_t cvmx_uart_thr_t;
  * USR bits 1-4 indicate the following FIFO status: TX FIFO Not Full (TFNF), TX FIFO Empty (TFE), RX
  * FIFO Not Empty (RFNE), and RX FIFO Full (RFF).
  */
-union cvmx_mio_uartx_usr
-{
+union cvmx_mio_uartx_usr {
 	uint64_t u64;
-	struct cvmx_mio_uartx_usr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uartx_usr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t rff                          : 1;  /**< RX FIFO Full */
 	uint64_t rfne                         : 1;  /**< RX FIFO Not Empty */
@@ -5962,8 +8946,13 @@ union cvmx_mio_uartx_usr
 	struct cvmx_mio_uartx_usr_s           cn56xxp1;
 	struct cvmx_mio_uartx_usr_s           cn58xx;
 	struct cvmx_mio_uartx_usr_s           cn58xxp1;
+	struct cvmx_mio_uartx_usr_s           cn61xx;
 	struct cvmx_mio_uartx_usr_s           cn63xx;
 	struct cvmx_mio_uartx_usr_s           cn63xxp1;
+	struct cvmx_mio_uartx_usr_s           cn66xx;
+	struct cvmx_mio_uartx_usr_s           cn68xx;
+	struct cvmx_mio_uartx_usr_s           cn68xxp1;
+	struct cvmx_mio_uartx_usr_s           cnf71xx;
 };
 typedef union cvmx_mio_uartx_usr cvmx_mio_uartx_usr_t;
 typedef cvmx_mio_uartx_usr_t cvmx_uart_usr_t;
@@ -5971,12 +8960,10 @@ typedef cvmx_mio_uartx_usr_t cvmx_uart_usr_t;
 /**
  * cvmx_mio_uart2_dlh
  */
-union cvmx_mio_uart2_dlh
-{
+union cvmx_mio_uart2_dlh {
 	uint64_t u64;
-	struct cvmx_mio_uart2_dlh_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_dlh_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t dlh                          : 8;  /**< Divisor Latch High Register */
 #else
@@ -5992,12 +8979,10 @@ typedef union cvmx_mio_uart2_dlh cvmx_mio_uart2_dlh_t;
 /**
  * cvmx_mio_uart2_dll
  */
-union cvmx_mio_uart2_dll
-{
+union cvmx_mio_uart2_dll {
 	uint64_t u64;
-	struct cvmx_mio_uart2_dll_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_dll_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t dll                          : 8;  /**< Divisor Latch Low Register */
 #else
@@ -6013,12 +8998,10 @@ typedef union cvmx_mio_uart2_dll cvmx_mio_uart2_dll_t;
 /**
  * cvmx_mio_uart2_far
  */
-union cvmx_mio_uart2_far
-{
+union cvmx_mio_uart2_far {
 	uint64_t u64;
-	struct cvmx_mio_uart2_far_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_far_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t far                          : 1;  /**< FIFO Access Register */
 #else
@@ -6034,12 +9017,10 @@ typedef union cvmx_mio_uart2_far cvmx_mio_uart2_far_t;
 /**
  * cvmx_mio_uart2_fcr
  */
-union cvmx_mio_uart2_fcr
-{
+union cvmx_mio_uart2_fcr {
 	uint64_t u64;
-	struct cvmx_mio_uart2_fcr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_fcr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t rxtrig                       : 2;  /**< RX Trigger */
 	uint64_t txtrig                       : 2;  /**< TX Trigger */
@@ -6065,12 +9046,10 @@ typedef union cvmx_mio_uart2_fcr cvmx_mio_uart2_fcr_t;
 /**
  * cvmx_mio_uart2_htx
  */
-union cvmx_mio_uart2_htx
-{
+union cvmx_mio_uart2_htx {
 	uint64_t u64;
-	struct cvmx_mio_uart2_htx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_htx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t htx                          : 1;  /**< Halt TX */
 #else
@@ -6086,12 +9065,10 @@ typedef union cvmx_mio_uart2_htx cvmx_mio_uart2_htx_t;
 /**
  * cvmx_mio_uart2_ier
  */
-union cvmx_mio_uart2_ier
-{
+union cvmx_mio_uart2_ier {
 	uint64_t u64;
-	struct cvmx_mio_uart2_ier_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_ier_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t ptime                        : 1;  /**< Programmable THRE Interrupt mode enable */
 	uint64_t reserved_4_6                 : 3;
@@ -6117,12 +9094,10 @@ typedef union cvmx_mio_uart2_ier cvmx_mio_uart2_ier_t;
 /**
  * cvmx_mio_uart2_iir
  */
-union cvmx_mio_uart2_iir
-{
+union cvmx_mio_uart2_iir {
 	uint64_t u64;
-	struct cvmx_mio_uart2_iir_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_iir_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t fen                          : 2;  /**< FIFO-enabled bits */
 	uint64_t reserved_4_5                 : 2;
@@ -6142,12 +9117,10 @@ typedef union cvmx_mio_uart2_iir cvmx_mio_uart2_iir_t;
 /**
  * cvmx_mio_uart2_lcr
  */
-union cvmx_mio_uart2_lcr
-{
+union cvmx_mio_uart2_lcr {
 	uint64_t u64;
-	struct cvmx_mio_uart2_lcr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_lcr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t dlab                         : 1;  /**< Divisor Latch Address bit */
 	uint64_t brk                          : 1;  /**< Break Control bit */
@@ -6175,12 +9148,10 @@ typedef union cvmx_mio_uart2_lcr cvmx_mio_uart2_lcr_t;
 /**
  * cvmx_mio_uart2_lsr
  */
-union cvmx_mio_uart2_lsr
-{
+union cvmx_mio_uart2_lsr {
 	uint64_t u64;
-	struct cvmx_mio_uart2_lsr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_lsr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t ferr                         : 1;  /**< Error in Receiver FIFO bit */
 	uint64_t temt                         : 1;  /**< Transmitter Empty bit */
@@ -6210,12 +9181,10 @@ typedef union cvmx_mio_uart2_lsr cvmx_mio_uart2_lsr_t;
 /**
  * cvmx_mio_uart2_mcr
  */
-union cvmx_mio_uart2_mcr
-{
+union cvmx_mio_uart2_mcr {
 	uint64_t u64;
-	struct cvmx_mio_uart2_mcr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_mcr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t afce                         : 1;  /**< Auto Flow Control Enable bit */
 	uint64_t loop                         : 1;  /**< Loopback bit */
@@ -6241,12 +9210,10 @@ typedef union cvmx_mio_uart2_mcr cvmx_mio_uart2_mcr_t;
 /**
  * cvmx_mio_uart2_msr
  */
-union cvmx_mio_uart2_msr
-{
+union cvmx_mio_uart2_msr {
 	uint64_t u64;
-	struct cvmx_mio_uart2_msr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_msr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t dcd                          : 1;  /**< Data Carrier Detect input bit */
 	uint64_t ri                           : 1;  /**< Ring Indicator input bit */
@@ -6276,12 +9243,10 @@ typedef union cvmx_mio_uart2_msr cvmx_mio_uart2_msr_t;
 /**
  * cvmx_mio_uart2_rbr
  */
-union cvmx_mio_uart2_rbr
-{
+union cvmx_mio_uart2_rbr {
 	uint64_t u64;
-	struct cvmx_mio_uart2_rbr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_rbr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t rbr                          : 8;  /**< Receive Buffer Register */
 #else
@@ -6297,12 +9262,10 @@ typedef union cvmx_mio_uart2_rbr cvmx_mio_uart2_rbr_t;
 /**
  * cvmx_mio_uart2_rfl
  */
-union cvmx_mio_uart2_rfl
-{
+union cvmx_mio_uart2_rfl {
 	uint64_t u64;
-	struct cvmx_mio_uart2_rfl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_rfl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t rfl                          : 7;  /**< Receive FIFO Level Register */
 #else
@@ -6318,12 +9281,10 @@ typedef union cvmx_mio_uart2_rfl cvmx_mio_uart2_rfl_t;
 /**
  * cvmx_mio_uart2_rfw
  */
-union cvmx_mio_uart2_rfw
-{
+union cvmx_mio_uart2_rfw {
 	uint64_t u64;
-	struct cvmx_mio_uart2_rfw_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_rfw_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t rffe                         : 1;  /**< Receive FIFO Framing Error */
 	uint64_t rfpe                         : 1;  /**< Receive FIFO Parity Error */
@@ -6343,12 +9304,10 @@ typedef union cvmx_mio_uart2_rfw cvmx_mio_uart2_rfw_t;
 /**
  * cvmx_mio_uart2_sbcr
  */
-union cvmx_mio_uart2_sbcr
-{
+union cvmx_mio_uart2_sbcr {
 	uint64_t u64;
-	struct cvmx_mio_uart2_sbcr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_sbcr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t sbcr                         : 1;  /**< Shadow Break Control */
 #else
@@ -6364,12 +9323,10 @@ typedef union cvmx_mio_uart2_sbcr cvmx_mio_uart2_sbcr_t;
 /**
  * cvmx_mio_uart2_scr
  */
-union cvmx_mio_uart2_scr
-{
+union cvmx_mio_uart2_scr {
 	uint64_t u64;
-	struct cvmx_mio_uart2_scr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_scr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t scr                          : 8;  /**< Scratchpad Register */
 #else
@@ -6385,12 +9342,10 @@ typedef union cvmx_mio_uart2_scr cvmx_mio_uart2_scr_t;
 /**
  * cvmx_mio_uart2_sfe
  */
-union cvmx_mio_uart2_sfe
-{
+union cvmx_mio_uart2_sfe {
 	uint64_t u64;
-	struct cvmx_mio_uart2_sfe_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_sfe_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t sfe                          : 1;  /**< Shadow FIFO Enable */
 #else
@@ -6406,12 +9361,10 @@ typedef union cvmx_mio_uart2_sfe cvmx_mio_uart2_sfe_t;
 /**
  * cvmx_mio_uart2_srr
  */
-union cvmx_mio_uart2_srr
-{
+union cvmx_mio_uart2_srr {
 	uint64_t u64;
-	struct cvmx_mio_uart2_srr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_srr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t stfr                         : 1;  /**< Shadow TX FIFO Reset */
 	uint64_t srfr                         : 1;  /**< Shadow RX FIFO Reset */
@@ -6431,12 +9384,10 @@ typedef union cvmx_mio_uart2_srr cvmx_mio_uart2_srr_t;
 /**
  * cvmx_mio_uart2_srt
  */
-union cvmx_mio_uart2_srt
-{
+union cvmx_mio_uart2_srt {
 	uint64_t u64;
-	struct cvmx_mio_uart2_srt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_srt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t srt                          : 2;  /**< Shadow RX Trigger */
 #else
@@ -6452,12 +9403,10 @@ typedef union cvmx_mio_uart2_srt cvmx_mio_uart2_srt_t;
 /**
  * cvmx_mio_uart2_srts
  */
-union cvmx_mio_uart2_srts
-{
+union cvmx_mio_uart2_srts {
 	uint64_t u64;
-	struct cvmx_mio_uart2_srts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_srts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t srts                         : 1;  /**< Shadow Request To Send */
 #else
@@ -6473,12 +9422,10 @@ typedef union cvmx_mio_uart2_srts cvmx_mio_uart2_srts_t;
 /**
  * cvmx_mio_uart2_stt
  */
-union cvmx_mio_uart2_stt
-{
+union cvmx_mio_uart2_stt {
 	uint64_t u64;
-	struct cvmx_mio_uart2_stt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_stt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t stt                          : 2;  /**< Shadow TX Trigger */
 #else
@@ -6494,12 +9441,10 @@ typedef union cvmx_mio_uart2_stt cvmx_mio_uart2_stt_t;
 /**
  * cvmx_mio_uart2_tfl
  */
-union cvmx_mio_uart2_tfl
-{
+union cvmx_mio_uart2_tfl {
 	uint64_t u64;
-	struct cvmx_mio_uart2_tfl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_tfl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t tfl                          : 7;  /**< Transmit FIFO Level Register */
 #else
@@ -6515,12 +9460,10 @@ typedef union cvmx_mio_uart2_tfl cvmx_mio_uart2_tfl_t;
 /**
  * cvmx_mio_uart2_tfr
  */
-union cvmx_mio_uart2_tfr
-{
+union cvmx_mio_uart2_tfr {
 	uint64_t u64;
-	struct cvmx_mio_uart2_tfr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_tfr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t tfr                          : 8;  /**< Transmit FIFO Read Register */
 #else
@@ -6536,12 +9479,10 @@ typedef union cvmx_mio_uart2_tfr cvmx_mio_uart2_tfr_t;
 /**
  * cvmx_mio_uart2_thr
  */
-union cvmx_mio_uart2_thr
-{
+union cvmx_mio_uart2_thr {
 	uint64_t u64;
-	struct cvmx_mio_uart2_thr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_thr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t thr                          : 8;  /**< Transmit Holding Register */
 #else
@@ -6557,12 +9498,10 @@ typedef union cvmx_mio_uart2_thr cvmx_mio_uart2_thr_t;
 /**
  * cvmx_mio_uart2_usr
  */
-union cvmx_mio_uart2_usr
-{
+union cvmx_mio_uart2_usr {
 	uint64_t u64;
-	struct cvmx_mio_uart2_usr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mio_uart2_usr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t rff                          : 1;  /**< RX FIFO Full */
 	uint64_t rfne                         : 1;  /**< RX FIFO Not Empty */
diff --git a/sys/contrib/octeon-sdk/cvmx-mixx-defs.h b/sys/contrib/octeon-sdk/cvmx-mixx-defs.h
index c5d0274..6c65e4f 100644
--- a/sys/contrib/octeon-sdk/cvmx-mixx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-mixx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_MIXX_TYPEDEFS_H__
-#define __CVMX_MIXX_TYPEDEFS_H__
+#ifndef __CVMX_MIXX_DEFS_H__
+#define __CVMX_MIXX_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_MIXX_BIST(unsigned long offset)
@@ -58,7 +58,10 @@ static inline uint64_t CVMX_MIXX_BIST(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_MIXX_BIST(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048;
 }
@@ -71,7 +74,10 @@ static inline uint64_t CVMX_MIXX_CTL(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_MIXX_CTL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048;
 }
@@ -84,7 +90,10 @@ static inline uint64_t CVMX_MIXX_INTENA(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_MIXX_INTENA(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048;
 }
@@ -97,7 +106,10 @@ static inline uint64_t CVMX_MIXX_IRCNT(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_MIXX_IRCNT(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048;
 }
@@ -110,7 +122,10 @@ static inline uint64_t CVMX_MIXX_IRHWM(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_MIXX_IRHWM(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048;
 }
@@ -123,7 +138,10 @@ static inline uint64_t CVMX_MIXX_IRING1(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_MIXX_IRING1(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048;
 }
@@ -136,7 +154,10 @@ static inline uint64_t CVMX_MIXX_IRING2(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_MIXX_IRING2(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048;
 }
@@ -149,7 +170,10 @@ static inline uint64_t CVMX_MIXX_ISR(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_MIXX_ISR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048;
 }
@@ -162,7 +186,10 @@ static inline uint64_t CVMX_MIXX_ORCNT(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_MIXX_ORCNT(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048;
 }
@@ -175,7 +202,10 @@ static inline uint64_t CVMX_MIXX_ORHWM(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_MIXX_ORHWM(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048;
 }
@@ -188,7 +218,10 @@ static inline uint64_t CVMX_MIXX_ORING1(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_MIXX_ORING1(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048;
 }
@@ -201,7 +234,10 @@ static inline uint64_t CVMX_MIXX_ORING2(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_MIXX_ORING2(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048;
 }
@@ -214,7 +250,10 @@ static inline uint64_t CVMX_MIXX_REMCNT(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_MIXX_REMCNT(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048;
 }
@@ -225,7 +264,10 @@ static inline uint64_t CVMX_MIXX_REMCNT(unsigned long offset)
 static inline uint64_t CVMX_MIXX_TSCTL(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_MIXX_TSCTL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048;
 }
@@ -236,7 +278,10 @@ static inline uint64_t CVMX_MIXX_TSCTL(unsigned long offset)
 static inline uint64_t CVMX_MIXX_TSTAMP(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_MIXX_TSTAMP(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048;
 }
@@ -252,12 +297,10 @@ static inline uint64_t CVMX_MIXX_TSTAMP(unsigned long offset)
  * Description:
  *  NOTE: To read the MIX_BIST register, a device would issue an IOBLD64 directed at the MIO.
  */
-union cvmx_mixx_bist
-{
+union cvmx_mixx_bist {
 	uint64_t u64;
-	struct cvmx_mixx_bist_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_bist_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t opfdat                       : 1;  /**< Bist Results for AGO OPF Buffer RAM
                                                          - 0: GOOD (or bist in progress/never run)
@@ -287,9 +330,8 @@ union cvmx_mixx_bist
 	uint64_t reserved_6_63                : 58;
 #endif
 	} s;
-	struct cvmx_mixx_bist_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_bist_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t mrqdat                       : 1;  /**< Bist Results for NBR CSR RdReq RAM
                                                          - 0: GOOD (or bist in progress/never run)
@@ -314,8 +356,12 @@ union cvmx_mixx_bist
 	struct cvmx_mixx_bist_cn52xx          cn52xxp1;
 	struct cvmx_mixx_bist_cn52xx          cn56xx;
 	struct cvmx_mixx_bist_cn52xx          cn56xxp1;
+	struct cvmx_mixx_bist_s               cn61xx;
 	struct cvmx_mixx_bist_s               cn63xx;
 	struct cvmx_mixx_bist_s               cn63xxp1;
+	struct cvmx_mixx_bist_s               cn66xx;
+	struct cvmx_mixx_bist_s               cn68xx;
+	struct cvmx_mixx_bist_s               cn68xxp1;
 };
 typedef union cvmx_mixx_bist cvmx_mixx_bist_t;
 
@@ -328,12 +374,10 @@ typedef union cvmx_mixx_bist cvmx_mixx_bist_t;
  *  NOTE: To write to the MIX_CTL register, a device would issue an IOBST directed at the MIO.
  *        To read the MIX_CTL register, a device would issue an IOBLD64 directed at the MIO.
  */
-union cvmx_mixx_ctl
-{
+union cvmx_mixx_ctl {
 	uint64_t u64;
-	struct cvmx_mixx_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t ts_thresh                    : 4;  /**< TimeStamp Interrupt Threshold
                                                          When the \#of pending Timestamp interrupts (MIX_TSCTL[TSCNT]
@@ -373,7 +417,11 @@ union cvmx_mixx_ctl
                                                           However, the values of the CSR fields will be effected by
                                                           soft reset (except MIX_CTL[RESET] itself).
                                                           NOTE: After power-on, the MII-AGL/MIX are held in reset
-                                                          until the MIX_CTL[RESET] is written to zero.
+                                                          until the MIX_CTL[RESET] is written to zero. SW MUST also
+                                                          perform a MIX_CTL CSR read after this write to ensure the
+                                                          soft reset de-assertion has had sufficient time to propagate
+                                                          to all MIO-MIX internal logic before any subsequent MIX CSR
+                                                          accesses are issued.
                                                           The intended "soft reset" sequence is: (please also
                                                           refer to HRM Section 12.6.2 on MIX/AGL Block Reset).
                                                              1) Write MIX_CTL[EN]=0
@@ -422,9 +470,8 @@ union cvmx_mixx_ctl
 	uint64_t reserved_12_63               : 52;
 #endif
 	} s;
-	struct cvmx_mixx_ctl_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_ctl_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t crc_strip                    : 1;  /**< HW CRC Strip Enable
                                                          When enabled, the last 4 bytes(CRC) of the ingress packet
@@ -456,7 +503,11 @@ union cvmx_mixx_ctl
                                                           However, the values of the CSR fields will be effected by
                                                           soft reset (except MIX_CTL[RESET] itself).
                                                           NOTE: After power-on, the MII-AGL/MIX are held in reset
-                                                          until the MIX_CTL[RESET] is written to zero.
+                                                          until the MIX_CTL[RESET] is written to zero. SW MUST also
+                                                          perform a MIX_CTL CSR read after this write to ensure the
+                                                          soft reset de-assertion has had sufficient time to propagate
+                                                          to all MIO-MIX internal logic before any subsequent MIX CSR
+                                                          accesses are issued.
                                                           The intended "soft reset" sequence is: (please also
                                                           refer to HRM Section 12.6.2 on MIX/AGL Block Reset).
                                                              1) Write MIX_CTL[EN]=0
@@ -507,8 +558,12 @@ union cvmx_mixx_ctl
 	struct cvmx_mixx_ctl_cn52xx           cn52xxp1;
 	struct cvmx_mixx_ctl_cn52xx           cn56xx;
 	struct cvmx_mixx_ctl_cn52xx           cn56xxp1;
+	struct cvmx_mixx_ctl_s                cn61xx;
 	struct cvmx_mixx_ctl_s                cn63xx;
 	struct cvmx_mixx_ctl_s                cn63xxp1;
+	struct cvmx_mixx_ctl_s                cn66xx;
+	struct cvmx_mixx_ctl_s                cn68xx;
+	struct cvmx_mixx_ctl_s                cn68xxp1;
 };
 typedef union cvmx_mixx_ctl cvmx_mixx_ctl_t;
 
@@ -521,50 +576,48 @@ typedef union cvmx_mixx_ctl cvmx_mixx_ctl_t;
  *  NOTE: To write to the MIX_INTENA register, a device would issue an IOBST directed at the MIO.
  *        To read the MIX_INTENA register, a device would issue an IOBLD64 directed at the MIO.
  */
-union cvmx_mixx_intena
-{
+union cvmx_mixx_intena {
 	uint64_t u64;
-	struct cvmx_mixx_intena_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_intena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t tsena                        : 1;  /**< TimeStamp Interrupt Enable
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
                                                          and this local interrupt mask bit is set, than an
                                                          interrupt is reported for an Outbound Ring with Timestamp
                                                          event (see: MIX_ISR[TS]). */
 	uint64_t orunena                      : 1;  /**< ORCNT UnderFlow Detected Enable
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
                                                          and this local interrupt mask bit is set, than an
                                                          interrupt is reported for an ORCNT underflow condition
                                                          MIX_ISR[ORUN]. */
 	uint64_t irunena                      : 1;  /**< IRCNT UnderFlow Interrupt Enable
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
                                                          and this local interrupt mask bit is set, than an
                                                          interrupt is reported for an IRCNT underflow condition
                                                          MIX_ISR[IRUN]. */
 	uint64_t data_drpena                  : 1;  /**< Data was dropped due to RX FIFO full Interrupt
                                                          enable. If both the global interrupt mask bits
-                                                         (CIU_INTx_EN*[MII]) and the local interrupt mask
+                                                         (CIU2_EN_xx_yy_PKT[MII]) and the local interrupt mask
                                                          bit(DATA_DRPENA) is set, than an interrupt is
                                                          reported for this event. */
 	uint64_t ithena                       : 1;  /**< Inbound Ring Threshold Exceeded Interrupt Enable
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
                                                          and this local interrupt mask bit is set, than an
                                                          interrupt is reported for an Inbound Ring Threshold
                                                          Exceeded event(IRTHRESH). */
 	uint64_t othena                       : 1;  /**< Outbound Ring Threshold Exceeded Interrupt Enable
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
                                                          and this local interrupt mask bit is set, than an
                                                          interrupt is reported for an Outbound Ring Threshold
                                                          Exceeded event(ORTHRESH). */
 	uint64_t ivfena                       : 1;  /**< Inbound DoorBell(IDBELL) Overflow Detected
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
                                                          and this local interrupt mask bit is set, than an
                                                          interrupt is reported for an Inbound Doorbell Overflow
                                                          event(IDBOVF). */
 	uint64_t ovfena                       : 1;  /**< Outbound DoorBell(ODBELL) Overflow Interrupt Enable
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
                                                          and this local interrupt mask bit is set, than an
                                                          interrupt is reported for an Outbound Doorbell Overflow
                                                          event(ODBOVF). */
@@ -580,9 +633,8 @@ union cvmx_mixx_intena
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
-	struct cvmx_mixx_intena_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_intena_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t orunena                      : 1;  /**< ORCNT UnderFlow Detected
                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
@@ -633,8 +685,12 @@ union cvmx_mixx_intena
 	struct cvmx_mixx_intena_cn52xx        cn52xxp1;
 	struct cvmx_mixx_intena_cn52xx        cn56xx;
 	struct cvmx_mixx_intena_cn52xx        cn56xxp1;
+	struct cvmx_mixx_intena_s             cn61xx;
 	struct cvmx_mixx_intena_s             cn63xx;
 	struct cvmx_mixx_intena_s             cn63xxp1;
+	struct cvmx_mixx_intena_s             cn66xx;
+	struct cvmx_mixx_intena_s             cn68xx;
+	struct cvmx_mixx_intena_s             cn68xxp1;
 };
 typedef union cvmx_mixx_intena cvmx_mixx_intena_t;
 
@@ -647,12 +703,10 @@ typedef union cvmx_mixx_intena cvmx_mixx_intena_t;
  *  NOTE: To write to the MIX_IRCNT register, a device would issue an IOBST directed at the MIO.
  *        To read the MIX_IRCNT register, a device would issue an IOBLD64 directed at the MIO.
  */
-union cvmx_mixx_ircnt
-{
+union cvmx_mixx_ircnt {
 	uint64_t u64;
-	struct cvmx_mixx_ircnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_ircnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t ircnt                        : 20; /**< Pending \# of I-Ring Packets.
                                                          Whenever HW writes a completion code of Done, Trunc,
@@ -679,8 +733,12 @@ union cvmx_mixx_ircnt
 	struct cvmx_mixx_ircnt_s              cn52xxp1;
 	struct cvmx_mixx_ircnt_s              cn56xx;
 	struct cvmx_mixx_ircnt_s              cn56xxp1;
+	struct cvmx_mixx_ircnt_s              cn61xx;
 	struct cvmx_mixx_ircnt_s              cn63xx;
 	struct cvmx_mixx_ircnt_s              cn63xxp1;
+	struct cvmx_mixx_ircnt_s              cn66xx;
+	struct cvmx_mixx_ircnt_s              cn68xx;
+	struct cvmx_mixx_ircnt_s              cn68xxp1;
 };
 typedef union cvmx_mixx_ircnt cvmx_mixx_ircnt_t;
 
@@ -693,12 +751,10 @@ typedef union cvmx_mixx_ircnt cvmx_mixx_ircnt_t;
  *  NOTE: To write to the MIX_IHWM register, a device would issue an IOBST directed at the MIO.
  *        To read the MIX_IHWM register, a device would issue an IOBLD64 directed at the MIO.
  */
-union cvmx_mixx_irhwm
-{
+union cvmx_mixx_irhwm {
 	uint64_t u64;
-	struct cvmx_mixx_irhwm_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_irhwm_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t ibplwm                       : 20; /**< I-Ring BackPressure Low Water Mark Threshold.
                                                          When the \#of available I-Ring Entries (IDBELL)
@@ -712,7 +768,7 @@ union cvmx_mixx_irhwm
                                                          Used to determine when the \# of Inbound packets
                                                          in system memory(MIX_IRCNT[IRCNT]) exceeds this IRHWM
                                                          threshold.
-                                                         NOTE: The power-on value of the CIU_INTx_EN*[MII]
+                                                         NOTE: The power-on value of the CIU2_EN_xx_yy_PKT[MII]
                                                          interrupt enable bits is zero and must be enabled
                                                          to allow interrupts to be reported. */
 #else
@@ -725,8 +781,12 @@ union cvmx_mixx_irhwm
 	struct cvmx_mixx_irhwm_s              cn52xxp1;
 	struct cvmx_mixx_irhwm_s              cn56xx;
 	struct cvmx_mixx_irhwm_s              cn56xxp1;
+	struct cvmx_mixx_irhwm_s              cn61xx;
 	struct cvmx_mixx_irhwm_s              cn63xx;
 	struct cvmx_mixx_irhwm_s              cn63xxp1;
+	struct cvmx_mixx_irhwm_s              cn66xx;
+	struct cvmx_mixx_irhwm_s              cn68xx;
+	struct cvmx_mixx_irhwm_s              cn68xxp1;
 };
 typedef union cvmx_mixx_irhwm cvmx_mixx_irhwm_t;
 
@@ -739,12 +799,10 @@ typedef union cvmx_mixx_irhwm cvmx_mixx_irhwm_t;
  *  NOTE: To write to the MIX_IRING1 register, a device would issue an IOBST directed at the MIO.
  *        To read the MIX_IRING1 register, a device would issue an IOBLD64 directed at the MIO.
  */
-union cvmx_mixx_iring1
-{
+union cvmx_mixx_iring1 {
 	uint64_t u64;
-	struct cvmx_mixx_iring1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_iring1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_60_63               : 4;
 	uint64_t isize                        : 20; /**< Represents the Inbound Ring Buffer's Size(in 8B
                                                          words). The ring can be as large as 1M entries.
@@ -762,9 +820,8 @@ union cvmx_mixx_iring1
 	uint64_t reserved_60_63               : 4;
 #endif
 	} s;
-	struct cvmx_mixx_iring1_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_iring1_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_60_63               : 4;
 	uint64_t isize                        : 20; /**< Represents the Inbound Ring Buffer's Size(in 8B
                                                          words). The ring can be as large as 1M entries.
@@ -787,8 +844,12 @@ union cvmx_mixx_iring1
 	struct cvmx_mixx_iring1_cn52xx        cn52xxp1;
 	struct cvmx_mixx_iring1_cn52xx        cn56xx;
 	struct cvmx_mixx_iring1_cn52xx        cn56xxp1;
+	struct cvmx_mixx_iring1_s             cn61xx;
 	struct cvmx_mixx_iring1_s             cn63xx;
 	struct cvmx_mixx_iring1_s             cn63xxp1;
+	struct cvmx_mixx_iring1_s             cn66xx;
+	struct cvmx_mixx_iring1_s             cn68xx;
+	struct cvmx_mixx_iring1_s             cn68xxp1;
 };
 typedef union cvmx_mixx_iring1 cvmx_mixx_iring1_t;
 
@@ -801,12 +862,10 @@ typedef union cvmx_mixx_iring1 cvmx_mixx_iring1_t;
  *  NOTE: To write to the MIX_IRING2 register, a device would issue an IOBST directed at the MIO.
  *        To read the MIX_IRING2 register, a device would issue an IOBLD64 directed at the MIO.
  */
-union cvmx_mixx_iring2
-{
+union cvmx_mixx_iring2 {
 	uint64_t u64;
-	struct cvmx_mixx_iring2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_iring2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_52_63               : 12;
 	uint64_t itlptr                       : 20; /**< The Inbound Ring Tail Pointer selects the I-Ring
                                                          Entry that the HW will process next. After the HW
@@ -838,8 +897,12 @@ union cvmx_mixx_iring2
 	struct cvmx_mixx_iring2_s             cn52xxp1;
 	struct cvmx_mixx_iring2_s             cn56xx;
 	struct cvmx_mixx_iring2_s             cn56xxp1;
+	struct cvmx_mixx_iring2_s             cn61xx;
 	struct cvmx_mixx_iring2_s             cn63xx;
 	struct cvmx_mixx_iring2_s             cn63xxp1;
+	struct cvmx_mixx_iring2_s             cn66xx;
+	struct cvmx_mixx_iring2_s             cn68xx;
+	struct cvmx_mixx_iring2_s             cn68xxp1;
 };
 typedef union cvmx_mixx_iring2 cvmx_mixx_iring2_t;
 
@@ -852,18 +915,16 @@ typedef union cvmx_mixx_iring2 cvmx_mixx_iring2_t;
  *  NOTE: To write to the MIX_ISR register, a device would issue an IOBST directed at the MIO.
  *        To read the MIX_ISR register, a device would issue an IOBLD64 directed at the MIO.
  */
-union cvmx_mixx_isr
-{
+union cvmx_mixx_isr {
 	uint64_t u64;
-	struct cvmx_mixx_isr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_isr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t ts                           : 1;  /**< TimeStamp Interrupt
                                                          When the \#of pending Timestamp Interrupts (MIX_TSCTL[TSCNT])
                                                          is greater than the TimeStamp Interrupt Threshold
                                                          (MIX_CTL[TS_THRESH]) value this interrupt bit is set.
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
                                                          and this local interrupt mask bit is set, than an
                                                          interrupt is reported for an Outbound Ring with Timestamp
                                                          event (see: MIX_INTENA[TSENA]). */
@@ -887,26 +948,26 @@ union cvmx_mixx_isr
                                                          software reset sequence (see: MIX_CTL[RESET] */
 	uint64_t data_drp                     : 1;  /**< Data was dropped due to RX FIFO full
                                                          If this does occur, the DATA_DRP is set and the
-                                                         CIU_INTx_SUM0,4[MII] bits are set.
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         CIU2_RAW_PKT[MII] bit is set.
+                                                         If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
                                                          and the local interrupt mask bit(DATA_DRPENA) is set, than an
                                                          interrupt is reported for this event. */
 	uint64_t irthresh                     : 1;  /**< Inbound Ring Packet Threshold Exceeded
                                                          When the pending \#inbound packets in system
                                                          memory(IRCNT) has exceeded a programmable threshold
                                                          (IRHWM), then this bit is set. If this does occur,
-                                                         the IRTHRESH is set and the CIU_INTx_SUM0,4[MII] bits
-                                                         are set if ((MIX_ISR & MIX_INTENA) != 0)).
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         the IRTHRESH is set and the CIU2_RAW_PKT[MII] bit
+                                                         is set if ((MIX_ISR & MIX_INTENA) != 0)).
+                                                         If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
                                                          and the local interrupt mask bit(ITHENA) is set, than an
                                                          interrupt is reported for this event. */
 	uint64_t orthresh                     : 1;  /**< Outbound Ring Packet Threshold Exceeded
                                                          When the pending \#outbound packets in system
                                                          memory(ORCNT) has exceeded a programmable threshold
                                                          (ORHWM), then this bit is set. If this does occur,
-                                                         the ORTHRESH is set and the CIU_INTx_SUM0,4[MII] bits
-                                                         are set if ((MIX_ISR & MIX_INTENA) != 0)).
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         the ORTHRESH is set and the CIU2_RAW_PKT[MII] bit
+                                                         is set if ((MIX_ISR & MIX_INTENA) != 0)).
+                                                         If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
                                                          and the local interrupt mask bit(OTHENA) is set, than an
                                                          interrupt is reported for this event. */
 	uint64_t idblovf                      : 1;  /**< Inbound DoorBell(IDBELL) Overflow Detected
@@ -915,9 +976,9 @@ union cvmx_mixx_isr
                                                          I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then
                                                          the following occurs:
                                                          1) The  MIX_IRING2[IDBELL] write is IGNORED
-                                                         2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]
-                                                            bits are set if ((MIX_ISR & MIX_INTENA) != 0)).
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         2) The ODBLOVF is set and the CIU2_RAW_PKT[MII]
+                                                            bit is set if ((MIX_ISR & MIX_INTENA) != 0)).
+                                                         If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
                                                          and the local interrupt mask bit(IVFENA) is set, than an
                                                          interrupt is reported for this event.
                                                          SW should keep track of the \#I-Ring Entries in use
@@ -940,9 +1001,9 @@ union cvmx_mixx_isr
                                                          O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then
                                                          the following occurs:
                                                          1) The  MIX_ORING2[ODBELL] write is IGNORED
-                                                         2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]
-                                                            bits are set if ((MIX_ISR & MIX_INTENA) != 0)).
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         2) The ODBLOVF is set and the CIU2_RAW_PKT[MII]
+                                                            bit is set if ((MIX_ISR & MIX_INTENA) != 0)).
+                                                         If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
                                                          and the local interrupt mask bit(OVFENA) is set, than an
                                                          interrupt is reported for this event.
                                                          SW should keep track of the \#I-Ring Entries in use
@@ -967,9 +1028,8 @@ union cvmx_mixx_isr
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
-	struct cvmx_mixx_isr_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_isr_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t orun                         : 1;  /**< ORCNT UnderFlow Detected
                                                          If SW writes a larger value than what is currently
@@ -1073,8 +1133,12 @@ union cvmx_mixx_isr
 	struct cvmx_mixx_isr_cn52xx           cn52xxp1;
 	struct cvmx_mixx_isr_cn52xx           cn56xx;
 	struct cvmx_mixx_isr_cn52xx           cn56xxp1;
+	struct cvmx_mixx_isr_s                cn61xx;
 	struct cvmx_mixx_isr_s                cn63xx;
 	struct cvmx_mixx_isr_s                cn63xxp1;
+	struct cvmx_mixx_isr_s                cn66xx;
+	struct cvmx_mixx_isr_s                cn68xx;
+	struct cvmx_mixx_isr_s                cn68xxp1;
 };
 typedef union cvmx_mixx_isr cvmx_mixx_isr_t;
 
@@ -1087,12 +1151,10 @@ typedef union cvmx_mixx_isr cvmx_mixx_isr_t;
  *  NOTE: To write to the MIX_ORCNT register, a device would issue an IOBST directed at the MIO.
  *        To read the MIX_ORCNT register, a device would issue an IOBLD64 directed at the MIO.
  */
-union cvmx_mixx_orcnt
-{
+union cvmx_mixx_orcnt {
 	uint64_t u64;
-	struct cvmx_mixx_orcnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_orcnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t orcnt                        : 20; /**< Pending \# of O-Ring Packets.
                                                          Whenever HW removes a packet from the O-Ring, it
@@ -1116,8 +1178,12 @@ union cvmx_mixx_orcnt
 	struct cvmx_mixx_orcnt_s              cn52xxp1;
 	struct cvmx_mixx_orcnt_s              cn56xx;
 	struct cvmx_mixx_orcnt_s              cn56xxp1;
+	struct cvmx_mixx_orcnt_s              cn61xx;
 	struct cvmx_mixx_orcnt_s              cn63xx;
 	struct cvmx_mixx_orcnt_s              cn63xxp1;
+	struct cvmx_mixx_orcnt_s              cn66xx;
+	struct cvmx_mixx_orcnt_s              cn68xx;
+	struct cvmx_mixx_orcnt_s              cn68xxp1;
 };
 typedef union cvmx_mixx_orcnt cvmx_mixx_orcnt_t;
 
@@ -1130,18 +1196,16 @@ typedef union cvmx_mixx_orcnt cvmx_mixx_orcnt_t;
  *  NOTE: To write to the MIX_ORHWM register, a device would issue an IOBST directed at the MIO.
  *        To read the MIX_ORHWM register, a device would issue an IOBLD64 directed at the MIO.
  */
-union cvmx_mixx_orhwm
-{
+union cvmx_mixx_orhwm {
 	uint64_t u64;
-	struct cvmx_mixx_orhwm_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_orhwm_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t orhwm                        : 20; /**< O-Ring Entry High Water Mark Threshold.
                                                          Used to determine when the \# of Outbound packets
                                                          in system memory that can be reclaimed
                                                          (MIX_ORCNT[ORCNT]) exceeds this ORHWM threshold.
-                                                         NOTE: The power-on value of the CIU_INTx_EN*[MII]
+                                                         NOTE: The power-on value of the CIU2_EN_xx_yy_PKT[MII]
                                                          interrupt enable bits is zero and must be enabled
                                                          to allow interrupts to be reported. */
 #else
@@ -1153,8 +1217,12 @@ union cvmx_mixx_orhwm
 	struct cvmx_mixx_orhwm_s              cn52xxp1;
 	struct cvmx_mixx_orhwm_s              cn56xx;
 	struct cvmx_mixx_orhwm_s              cn56xxp1;
+	struct cvmx_mixx_orhwm_s              cn61xx;
 	struct cvmx_mixx_orhwm_s              cn63xx;
 	struct cvmx_mixx_orhwm_s              cn63xxp1;
+	struct cvmx_mixx_orhwm_s              cn66xx;
+	struct cvmx_mixx_orhwm_s              cn68xx;
+	struct cvmx_mixx_orhwm_s              cn68xxp1;
 };
 typedef union cvmx_mixx_orhwm cvmx_mixx_orhwm_t;
 
@@ -1167,12 +1235,10 @@ typedef union cvmx_mixx_orhwm cvmx_mixx_orhwm_t;
  *  NOTE: To write to the MIX_ORING1 register, a device would issue an IOBST directed at the MIO.
  *        To read the MIX_ORING1 register, a device would issue an IOBLD64 directed at the MIO.
  */
-union cvmx_mixx_oring1
-{
+union cvmx_mixx_oring1 {
 	uint64_t u64;
-	struct cvmx_mixx_oring1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_oring1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_60_63               : 4;
 	uint64_t osize                        : 20; /**< Represents the Outbound Ring Buffer's Size(in 8B
                                                          words). The ring can be as large as 1M entries.
@@ -1190,9 +1256,8 @@ union cvmx_mixx_oring1
 	uint64_t reserved_60_63               : 4;
 #endif
 	} s;
-	struct cvmx_mixx_oring1_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_oring1_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_60_63               : 4;
 	uint64_t osize                        : 20; /**< Represents the Outbound Ring Buffer's Size(in 8B
                                                          words). The ring can be as large as 1M entries.
@@ -1215,8 +1280,12 @@ union cvmx_mixx_oring1
 	struct cvmx_mixx_oring1_cn52xx        cn52xxp1;
 	struct cvmx_mixx_oring1_cn52xx        cn56xx;
 	struct cvmx_mixx_oring1_cn52xx        cn56xxp1;
+	struct cvmx_mixx_oring1_s             cn61xx;
 	struct cvmx_mixx_oring1_s             cn63xx;
 	struct cvmx_mixx_oring1_s             cn63xxp1;
+	struct cvmx_mixx_oring1_s             cn66xx;
+	struct cvmx_mixx_oring1_s             cn68xx;
+	struct cvmx_mixx_oring1_s             cn68xxp1;
 };
 typedef union cvmx_mixx_oring1 cvmx_mixx_oring1_t;
 
@@ -1229,12 +1298,10 @@ typedef union cvmx_mixx_oring1 cvmx_mixx_oring1_t;
  *  NOTE: To write to the MIX_ORING2 register, a device would issue an IOBST directed at the MIO.
  *        To read the MIX_ORING2 register, a device would issue an IOBLD64 directed at the MIO.
  */
-union cvmx_mixx_oring2
-{
+union cvmx_mixx_oring2 {
 	uint64_t u64;
-	struct cvmx_mixx_oring2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_oring2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_52_63               : 12;
 	uint64_t otlptr                       : 20; /**< The Outbound Ring Tail Pointer selects the O-Ring
                                                          Entry that the HW will process next. After the HW
@@ -1268,8 +1335,12 @@ union cvmx_mixx_oring2
 	struct cvmx_mixx_oring2_s             cn52xxp1;
 	struct cvmx_mixx_oring2_s             cn56xx;
 	struct cvmx_mixx_oring2_s             cn56xxp1;
+	struct cvmx_mixx_oring2_s             cn61xx;
 	struct cvmx_mixx_oring2_s             cn63xx;
 	struct cvmx_mixx_oring2_s             cn63xxp1;
+	struct cvmx_mixx_oring2_s             cn66xx;
+	struct cvmx_mixx_oring2_s             cn68xx;
+	struct cvmx_mixx_oring2_s             cn68xxp1;
 };
 typedef union cvmx_mixx_oring2 cvmx_mixx_oring2_t;
 
@@ -1281,12 +1352,10 @@ typedef union cvmx_mixx_oring2 cvmx_mixx_oring2_t;
  * Description:
  *  NOTE: To read the MIX_REMCNT register, a device would issue an IOBLD64 directed at the MIO.
  */
-union cvmx_mixx_remcnt
-{
+union cvmx_mixx_remcnt {
 	uint64_t u64;
-	struct cvmx_mixx_remcnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_remcnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_52_63               : 12;
 	uint64_t iremcnt                      : 20; /**< Remaining I-Ring Buffer Count
                                                          Reflects the \# of unused/remaining I-Ring Entries
@@ -1326,8 +1395,12 @@ union cvmx_mixx_remcnt
 	struct cvmx_mixx_remcnt_s             cn52xxp1;
 	struct cvmx_mixx_remcnt_s             cn56xx;
 	struct cvmx_mixx_remcnt_s             cn56xxp1;
+	struct cvmx_mixx_remcnt_s             cn61xx;
 	struct cvmx_mixx_remcnt_s             cn63xx;
 	struct cvmx_mixx_remcnt_s             cn63xxp1;
+	struct cvmx_mixx_remcnt_s             cn66xx;
+	struct cvmx_mixx_remcnt_s             cn68xx;
+	struct cvmx_mixx_remcnt_s             cn68xxp1;
 };
 typedef union cvmx_mixx_remcnt cvmx_mixx_remcnt_t;
 
@@ -1354,12 +1427,10 @@ typedef union cvmx_mixx_remcnt cvmx_mixx_remcnt_t;
  *
  * SWNOTE: A MIX_TSCTL write when MIX_TSCTL[TSCNT]=0 (ie: TimeStamp Fifo empty), then the write is ignored.
  */
-union cvmx_mixx_tsctl
-{
+union cvmx_mixx_tsctl {
 	uint64_t u64;
-	struct cvmx_mixx_tsctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_tsctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_21_63               : 43;
 	uint64_t tsavl                        : 5;  /**< # of MIX TimeStamp Entries Available for use
                                                          For o63: TSAVL MAX=4 (implementation
@@ -1382,8 +1453,12 @@ union cvmx_mixx_tsctl
 	uint64_t reserved_21_63               : 43;
 #endif
 	} s;
+	struct cvmx_mixx_tsctl_s              cn61xx;
 	struct cvmx_mixx_tsctl_s              cn63xx;
 	struct cvmx_mixx_tsctl_s              cn63xxp1;
+	struct cvmx_mixx_tsctl_s              cn66xx;
+	struct cvmx_mixx_tsctl_s              cn68xx;
+	struct cvmx_mixx_tsctl_s              cn68xxp1;
 };
 typedef union cvmx_mixx_tsctl cvmx_mixx_tsctl_t;
 
@@ -1395,12 +1470,10 @@ typedef union cvmx_mixx_tsctl cvmx_mixx_tsctl_t;
  * Description:
  *  NOTE: To read the MIX_TSTAMP register, a device would issue an IOBLD64 directed at the MIO.
  */
-union cvmx_mixx_tstamp
-{
+union cvmx_mixx_tstamp {
 	uint64_t u64;
-	struct cvmx_mixx_tstamp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mixx_tstamp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t tstamp                       : 64; /**< MIX TimeStamp Value
                                                           When SW sets up an ORING Entry with [47]=1(TSTAMP),
                                                           The packet is tagged with a specal SOP w/TSTAMP flag
@@ -1439,8 +1512,12 @@ union cvmx_mixx_tstamp
 	uint64_t tstamp                       : 64;
 #endif
 	} s;
+	struct cvmx_mixx_tstamp_s             cn61xx;
 	struct cvmx_mixx_tstamp_s             cn63xx;
 	struct cvmx_mixx_tstamp_s             cn63xxp1;
+	struct cvmx_mixx_tstamp_s             cn66xx;
+	struct cvmx_mixx_tstamp_s             cn68xx;
+	struct cvmx_mixx_tstamp_s             cn68xxp1;
 };
 typedef union cvmx_mixx_tstamp cvmx_mixx_tstamp_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-mpi-defs.h b/sys/contrib/octeon-sdk/cvmx-mpi-defs.h
index 058d845..d5b4eb9 100644
--- a/sys/contrib/octeon-sdk/cvmx-mpi-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-mpi-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,14 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_MPI_TYPEDEFS_H__
-#define __CVMX_MPI_TYPEDEFS_H__
+#ifndef __CVMX_MPI_DEFS_H__
+#define __CVMX_MPI_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_MPI_CFG CVMX_MPI_CFG_FUNC()
 static inline uint64_t CVMX_MPI_CFG_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MPI_CFG not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070000001000ull);
 }
@@ -69,7 +69,10 @@ static inline uint64_t CVMX_MPI_DATX(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 8))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 8))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 8)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 8))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 8))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 8))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 8)))))
 		cvmx_warn("CVMX_MPI_DATX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8;
 }
@@ -80,7 +83,7 @@ static inline uint64_t CVMX_MPI_DATX(unsigned long offset)
 #define CVMX_MPI_STS CVMX_MPI_STS_FUNC()
 static inline uint64_t CVMX_MPI_STS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MPI_STS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070000001008ull);
 }
@@ -91,7 +94,7 @@ static inline uint64_t CVMX_MPI_STS_FUNC(void)
 #define CVMX_MPI_TX CVMX_MPI_TX_FUNC()
 static inline uint64_t CVMX_MPI_TX_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_MPI_TX not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070000001010ull);
 }
@@ -101,13 +104,95 @@ static inline uint64_t CVMX_MPI_TX_FUNC(void)
 
 /**
  * cvmx_mpi_cfg
+ *
+ * SPI_MPI interface
+ *
+ *
+ * Notes:
+ * Some of the SPI/MPI pins are muxed with UART pins.
+ * SPI_CLK         : spi clock, dedicated pin
+ * SPI_DI          : spi input, shared with UART0_DCD_N/SPI_DI, enabled when MPI_CFG[ENABLE]=1
+ * SPI_DO          : spi output, mux to UART0_DTR_N/SPI_DO, enabled when MPI_CFG[ENABLE]=1
+ * SPI_CS0_L       : chips select 0, mux to BOOT_CE_N<6>/SPI_CS0_L pin, enabled when MPI_CFG[CSENA0]=1 and MPI_CFG[ENABLE]=1
+ * SPI_CS1_L       : chips select 1, mux to BOOT_CE_N<7>/SPI_CS1_L pin, enabled when MPI_CFG[CSENA1]=1 and MPI_CFG[ENABLE]=1
  */
-union cvmx_mpi_cfg
-{
+union cvmx_mpi_cfg {
 	uint64_t u64;
-	struct cvmx_mpi_cfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mpi_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_29_63               : 35;
+	uint64_t clkdiv                       : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV)                    |          NS
+                                                         CLKDIV = Fsclk / (2 * Fspi_clk) */
+	uint64_t csena3                       : 1;  /**< If 0, UART1_RTS_L/SPI_CS3_L pin is UART pin        |          NS
+                                                         1, UART1_RTS_L/SPI_CS3_L pin is SPI pin
+                                                            SPI_CS3_L drives UART1_RTS_L/SPI_CS3_L */
+	uint64_t csena2                       : 1;  /**< If 0, UART0_RTS_L/SPI_CS2_L pin is UART pin        |          NS
+                                                         1, UART0_RTS_L/SPI_CS2_L pin is SPI pin
+                                                            SPI_CS2_L drives  UART0_RTS_L/SPI_CS2_L */
+	uint64_t csena1                       : 1;  /**< If 0, BOOT_CE_N<7>/SPI_CS1_L pin is BOOT pin       |          NS
+                                                         1, BOOT_CE_N<7>/SPI_CS1_L pin is SPI pin
+                                                            SPI_CS1_L drives BOOT_CE_N<7>/SPI_CS1_L */
+	uint64_t csena0                       : 1;  /**< If 0, BOOT_CE_N<6>/SPI_CS0_L pin is BOOT pin       |          NS
+                                                         1, BOOT_CE_N<6>/SPI_CS0_L pin is SPI pin
+                                                            SPI_CS0_L drives BOOT_CE_N<6>/SPI_CS0_L */
+	uint64_t cslate                       : 1;  /**< If 0, SPI_CS asserts 1/2 SCLK before transaction   |          NS
+                                                            1, SPI_CS assert coincident with transaction
+                                                         NOTE: This control apply for 2 CSs */
+	uint64_t tritx                        : 1;  /**< If 0, SPI_DO pin is driven when slave is not       |          NS
+                                                               expected to be driving
+                                                            1, SPI_DO pin is tristated when not transmitting
+                                                         NOTE: only used when WIREOR==1 */
+	uint64_t idleclks                     : 2;  /**< Guarantee IDLECLKS idle sclk cycles between        |          NS
+                                                         commands. */
+	uint64_t cshi                         : 1;  /**< If 0, CS is low asserted                           |          NS
+                                                         1, CS is high asserted */
+	uint64_t csena                        : 1;  /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
+                                                         1, CS is driven per MPI_TX intruction */
+	uint64_t int_ena                      : 1;  /**< If 0, polling is required                          |          NS
+                                                         1, MPI engine interrupts X end of transaction */
+	uint64_t lsbfirst                     : 1;  /**< If 0, shift MSB first                              |          NS
+                                                         1, shift LSB first */
+	uint64_t wireor                       : 1;  /**< If 0, SPI_DO and SPI_DI are separate wires (SPI)   |          NS
+                                                               SPI_DO pin is always driven
+                                                            1, SPI_DO/DI is all from SPI_DO pin (MPI)
+                                                               SPI_DO pin is tristated when not transmitting
+                                                         NOTE: if WIREOR==1, SPI_DI pin is not used by the
+                                                               MPI engine */
+	uint64_t clk_cont                     : 1;  /**< If 0, clock idles to value given by IDLELO after   |          NS
+                                                            completion of MPI transaction
+                                                         1, clock never idles, requires CS deassertion
+                                                            assertion between commands */
+	uint64_t idlelo                       : 1;  /**< If 0, SPI_CLK idles high, 1st transition is hi->lo |          NS
+                                                         1, SPI_CLK idles low, 1st transition is lo->hi */
+	uint64_t enable                       : 1;  /**< If 0, UART0_DTR_L/SPI_DO, UART0_DCD_L/SPI_DI       |          NS
+                                                            BOOT_CE_N<7:6>/SPI_CSx_L
+                                                            pins are UART/BOOT pins
+                                                         1, UART0_DTR_L/SPI_DO and UART0_DCD_L/SPI_DI
+                                                            pins are SPI/MPI pins.
+                                                            BOOT_CE_N<6>/SPI_CS0_L is SPI pin if CSENA0=1
+                                                            BOOT_CE_N<7>/SPI_CS1_L is SPI pin if CSENA1=1 */
+#else
+	uint64_t enable                       : 1;
+	uint64_t idlelo                       : 1;
+	uint64_t clk_cont                     : 1;
+	uint64_t wireor                       : 1;
+	uint64_t lsbfirst                     : 1;
+	uint64_t int_ena                      : 1;
+	uint64_t csena                        : 1;
+	uint64_t cshi                         : 1;
+	uint64_t idleclks                     : 2;
+	uint64_t tritx                        : 1;
+	uint64_t cslate                       : 1;
+	uint64_t csena0                       : 1;
+	uint64_t csena1                       : 1;
+	uint64_t csena2                       : 1;
+	uint64_t csena3                       : 1;
+	uint64_t clkdiv                       : 13;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} s;
+	struct cvmx_mpi_cfg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t clkdiv                       : 13; /**< Fsclk = Feclk / (2 * CLKDIV)
                                                          CLKDIV = Feclk / (2 * Fsclk) */
@@ -159,11 +244,9 @@ union cvmx_mpi_cfg
 	uint64_t clkdiv                       : 13;
 	uint64_t reserved_29_63               : 35;
 #endif
-	} s;
-	struct cvmx_mpi_cfg_s                 cn30xx;
-	struct cvmx_mpi_cfg_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	} cn30xx;
+	struct cvmx_mpi_cfg_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t clkdiv                       : 13; /**< Fsclk = Feclk / (2 * CLKDIV)
                                                          CLKDIV = Feclk / (2 * Fsclk) */
@@ -212,21 +295,152 @@ union cvmx_mpi_cfg
 	uint64_t reserved_29_63               : 35;
 #endif
 	} cn31xx;
-	struct cvmx_mpi_cfg_s                 cn50xx;
+	struct cvmx_mpi_cfg_cn30xx            cn50xx;
+	struct cvmx_mpi_cfg_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_29_63               : 35;
+	uint64_t clkdiv                       : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV)                    |          NS
+                                                         CLKDIV = Fsclk / (2 * Fspi_clk) */
+	uint64_t reserved_14_15               : 2;
+	uint64_t csena1                       : 1;  /**< If 0, BOOT_CE_N<7>/SPI_CS1_L pin is BOOT pin       |          NS
+                                                         1, BOOT_CE_N<7>/SPI_CS1_L pin is SPI pin
+                                                            SPI_CS1_L drives BOOT_CE_N<7>/SPI_CS1_L */
+	uint64_t csena0                       : 1;  /**< If 0, BOOT_CE_N<6>/SPI_CS0_L pin is BOOT pin       |          NS
+                                                         1, BOOT_CE_N<6>/SPI_CS0_L pin is SPI pin
+                                                            SPI_CS0_L drives BOOT_CE_N<6>/SPI_CS0_L */
+	uint64_t cslate                       : 1;  /**< If 0, SPI_CS asserts 1/2 SCLK before transaction   |          NS
+                                                            1, SPI_CS assert coincident with transaction
+                                                         NOTE: This control apply for 2 CSs */
+	uint64_t tritx                        : 1;  /**< If 0, SPI_DO pin is driven when slave is not       |          NS
+                                                               expected to be driving
+                                                            1, SPI_DO pin is tristated when not transmitting
+                                                         NOTE: only used when WIREOR==1 */
+	uint64_t idleclks                     : 2;  /**< Guarantee IDLECLKS idle sclk cycles between        |          NS
+                                                         commands. */
+	uint64_t cshi                         : 1;  /**< If 0, CS is low asserted                           |          NS
+                                                         1, CS is high asserted */
+	uint64_t reserved_6_6                 : 1;
+	uint64_t int_ena                      : 1;  /**< If 0, polling is required                          |          NS
+                                                         1, MPI engine interrupts X end of transaction */
+	uint64_t lsbfirst                     : 1;  /**< If 0, shift MSB first                              |          NS
+                                                         1, shift LSB first */
+	uint64_t wireor                       : 1;  /**< If 0, SPI_DO and SPI_DI are separate wires (SPI)   |          NS
+                                                               SPI_DO pin is always driven
+                                                            1, SPI_DO/DI is all from SPI_DO pin (MPI)
+                                                               SPI_DO pin is tristated when not transmitting
+                                                         NOTE: if WIREOR==1, SPI_DI pin is not used by the
+                                                               MPI engine */
+	uint64_t clk_cont                     : 1;  /**< If 0, clock idles to value given by IDLELO after   |          NS
+                                                            completion of MPI transaction
+                                                         1, clock never idles, requires CS deassertion
+                                                            assertion between commands */
+	uint64_t idlelo                       : 1;  /**< If 0, SPI_CLK idles high, 1st transition is hi->lo |          NS
+                                                         1, SPI_CLK idles low, 1st transition is lo->hi */
+	uint64_t enable                       : 1;  /**< If 0, UART0_DTR_L/SPI_DO, UART0_DCD_L/SPI_DI       |          NS
+                                                            BOOT_CE_N<7:6>/SPI_CSx_L
+                                                            pins are UART/BOOT pins
+                                                         1, UART0_DTR_L/SPI_DO and UART0_DCD_L/SPI_DI
+                                                            pins are SPI/MPI pins.
+                                                            BOOT_CE_N<6>/SPI_CS0_L is SPI pin if CSENA0=1
+                                                            BOOT_CE_N<7>/SPI_CS1_L is SPI pin if CSENA1=1 */
+#else
+	uint64_t enable                       : 1;
+	uint64_t idlelo                       : 1;
+	uint64_t clk_cont                     : 1;
+	uint64_t wireor                       : 1;
+	uint64_t lsbfirst                     : 1;
+	uint64_t int_ena                      : 1;
+	uint64_t reserved_6_6                 : 1;
+	uint64_t cshi                         : 1;
+	uint64_t idleclks                     : 2;
+	uint64_t tritx                        : 1;
+	uint64_t cslate                       : 1;
+	uint64_t csena0                       : 1;
+	uint64_t csena1                       : 1;
+	uint64_t reserved_14_15               : 2;
+	uint64_t clkdiv                       : 13;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn61xx;
+	struct cvmx_mpi_cfg_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_29_63               : 35;
+	uint64_t clkdiv                       : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV)                    |          NS
+                                                         CLKDIV = Fsclk / (2 * Fspi_clk) */
+	uint64_t csena3                       : 1;  /**< If 0, UART1_RTS_L/SPI_CS3_L pin is UART pin        |          NS
+                                                         1, UART1_RTS_L/SPI_CS3_L pin is SPI pin
+                                                            SPI_CS3_L drives UART1_RTS_L/SPI_CS3_L */
+	uint64_t csena2                       : 1;  /**< If 0, UART0_RTS_L/SPI_CS2_L pin is UART pin        |          NS
+                                                         1, UART0_RTS_L/SPI_CS2_L pin is SPI pin
+                                                            SPI_CS2_L drives  UART0_RTS_L/SPI_CS2_L */
+	uint64_t reserved_12_13               : 2;
+	uint64_t cslate                       : 1;  /**< If 0, SPI_CS asserts 1/2 SCLK before transaction   |          NS
+                                                            1, SPI_CS assert coincident with transaction
+                                                         NOTE: This control apply for 4 CSs */
+	uint64_t tritx                        : 1;  /**< If 0, SPI_DO pin is driven when slave is not       |          NS
+                                                               expected to be driving
+                                                            1, SPI_DO pin is tristated when not transmitting
+                                                         NOTE: only used when WIREOR==1 */
+	uint64_t idleclks                     : 2;  /**< Guarantee IDLECLKS idle sclk cycles between        |          NS
+                                                         commands. */
+	uint64_t cshi                         : 1;  /**< If 0, CS is low asserted                           |          NS
+                                                         1, CS is high asserted */
+	uint64_t reserved_6_6                 : 1;
+	uint64_t int_ena                      : 1;  /**< If 0, polling is required                          |          NS
+                                                         1, MPI engine interrupts X end of transaction */
+	uint64_t lsbfirst                     : 1;  /**< If 0, shift MSB first                              |          NS
+                                                         1, shift LSB first */
+	uint64_t wireor                       : 1;  /**< If 0, SPI_DO and SPI_DI are separate wires (SPI)   |          NS
+                                                               SPI_DO pin is always driven
+                                                            1, SPI_DO/DI is all from SPI_DO pin (MPI)
+                                                               SPI_DO pin is tristated when not transmitting
+                                                         NOTE: if WIREOR==1, SPI_DI pin is not used by the
+                                                               MPI engine */
+	uint64_t clk_cont                     : 1;  /**< If 0, clock idles to value given by IDLELO after   |          NS
+                                                            completion of MPI transaction
+                                                         1, clock never idles, requires CS deassertion
+                                                            assertion between commands */
+	uint64_t idlelo                       : 1;  /**< If 0, SPI_CLK idles high, 1st transition is hi->lo |          NS
+                                                         1, SPI_CLK idles low, 1st transition is lo->hi */
+	uint64_t enable                       : 1;  /**< If 0, UART0_DTR_L/SPI_DO, UART0_DCD_L/SPI_DI       |          NS
+                                                            UART0_RTS_L/SPI_CS2_L, UART1_RTS_L/SPI_CS3_L
+                                                            pins are UART pins
+                                                         1, UART0_DTR_L/SPI_DO and UART0_DCD_L/SPI_DI
+                                                            pins are SPI/MPI pins.
+                                                            UART0_RTS_L/SPI_CS2_L is SPI pin if CSENA2=1
+                                                            UART1_RTS_L/SPI_CS3_L is SPI pin if CSENA3=1 */
+#else
+	uint64_t enable                       : 1;
+	uint64_t idlelo                       : 1;
+	uint64_t clk_cont                     : 1;
+	uint64_t wireor                       : 1;
+	uint64_t lsbfirst                     : 1;
+	uint64_t int_ena                      : 1;
+	uint64_t reserved_6_6                 : 1;
+	uint64_t cshi                         : 1;
+	uint64_t idleclks                     : 2;
+	uint64_t tritx                        : 1;
+	uint64_t cslate                       : 1;
+	uint64_t reserved_12_13               : 2;
+	uint64_t csena2                       : 1;
+	uint64_t csena3                       : 1;
+	uint64_t clkdiv                       : 13;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn66xx;
+	struct cvmx_mpi_cfg_cn61xx            cnf71xx;
 };
 typedef union cvmx_mpi_cfg cvmx_mpi_cfg_t;
 
 /**
  * cvmx_mpi_dat#
  */
-union cvmx_mpi_datx
-{
+union cvmx_mpi_datx {
 	uint64_t u64;
-	struct cvmx_mpi_datx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mpi_datx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
-	uint64_t data                         : 8;  /**< Data to transmit/received */
+	uint64_t data                         : 8;  /**< Data to transmit/received                          |           NS */
 #else
 	uint64_t data                         : 8;
 	uint64_t reserved_8_63                : 56;
@@ -235,22 +449,23 @@ union cvmx_mpi_datx
 	struct cvmx_mpi_datx_s                cn30xx;
 	struct cvmx_mpi_datx_s                cn31xx;
 	struct cvmx_mpi_datx_s                cn50xx;
+	struct cvmx_mpi_datx_s                cn61xx;
+	struct cvmx_mpi_datx_s                cn66xx;
+	struct cvmx_mpi_datx_s                cnf71xx;
 };
 typedef union cvmx_mpi_datx cvmx_mpi_datx_t;
 
 /**
  * cvmx_mpi_sts
  */
-union cvmx_mpi_sts
-{
+union cvmx_mpi_sts {
 	uint64_t u64;
-	struct cvmx_mpi_sts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mpi_sts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
-	uint64_t rxnum                        : 5;  /**< Number of bytes written for transaction */
+	uint64_t rxnum                        : 5;  /**< Number of bytes written for transaction            |          NS */
 	uint64_t reserved_1_7                 : 7;
-	uint64_t busy                         : 1;  /**< If 0, no MPI transaction in progress
+	uint64_t busy                         : 1;  /**< If 0, no MPI transaction in progress               |          NS
                                                          1, MPI engine is processing a transaction */
 #else
 	uint64_t busy                         : 1;
@@ -262,18 +477,41 @@ union cvmx_mpi_sts
 	struct cvmx_mpi_sts_s                 cn30xx;
 	struct cvmx_mpi_sts_s                 cn31xx;
 	struct cvmx_mpi_sts_s                 cn50xx;
+	struct cvmx_mpi_sts_s                 cn61xx;
+	struct cvmx_mpi_sts_s                 cn66xx;
+	struct cvmx_mpi_sts_s                 cnf71xx;
 };
 typedef union cvmx_mpi_sts cvmx_mpi_sts_t;
 
 /**
  * cvmx_mpi_tx
  */
-union cvmx_mpi_tx
-{
+union cvmx_mpi_tx {
 	uint64_t u64;
-	struct cvmx_mpi_tx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_mpi_tx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_22_63               : 42;
+	uint64_t csid                         : 2;  /**< Which CS to assert for this transaction            |          NS */
+	uint64_t reserved_17_19               : 3;
+	uint64_t leavecs                      : 1;  /**< If 0, deassert CS after transaction is done        |          NS
+                                                         1, leave CS asserted after transactrion is done */
+	uint64_t reserved_13_15               : 3;
+	uint64_t txnum                        : 5;  /**< Number of bytes to transmit                        |          NS */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t totnum                       : 5;  /**< Number of bytes to shift (transmit + receive)      |          NS */
+#else
+	uint64_t totnum                       : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t txnum                        : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t leavecs                      : 1;
+	uint64_t reserved_17_19               : 3;
+	uint64_t csid                         : 2;
+	uint64_t reserved_22_63               : 42;
+#endif
+	} s;
+	struct cvmx_mpi_tx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t leavecs                      : 1;  /**< If 0, deassert CS after transaction is done
                                                          1, leave CS asserted after transactrion is done */
@@ -289,10 +527,33 @@ union cvmx_mpi_tx
 	uint64_t leavecs                      : 1;
 	uint64_t reserved_17_63               : 47;
 #endif
-	} s;
-	struct cvmx_mpi_tx_s                  cn30xx;
-	struct cvmx_mpi_tx_s                  cn31xx;
-	struct cvmx_mpi_tx_s                  cn50xx;
+	} cn30xx;
+	struct cvmx_mpi_tx_cn30xx             cn31xx;
+	struct cvmx_mpi_tx_cn30xx             cn50xx;
+	struct cvmx_mpi_tx_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_21_63               : 43;
+	uint64_t csid                         : 1;  /**< Which CS to assert for this transaction            |          NS */
+	uint64_t reserved_17_19               : 3;
+	uint64_t leavecs                      : 1;  /**< If 0, deassert CS after transaction is done        |          NS
+                                                         1, leave CS asserted after transactrion is done */
+	uint64_t reserved_13_15               : 3;
+	uint64_t txnum                        : 5;  /**< Number of bytes to transmit                        |          NS */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t totnum                       : 5;  /**< Number of bytes to shift (transmit + receive)      |          NS */
+#else
+	uint64_t totnum                       : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t txnum                        : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t leavecs                      : 1;
+	uint64_t reserved_17_19               : 3;
+	uint64_t csid                         : 1;
+	uint64_t reserved_21_63               : 43;
+#endif
+	} cn61xx;
+	struct cvmx_mpi_tx_s                  cn66xx;
+	struct cvmx_mpi_tx_cn61xx             cnf71xx;
 };
 typedef union cvmx_mpi_tx cvmx_mpi_tx_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-nand.c b/sys/contrib/octeon-sdk/cvmx-nand.c
index 0d5a948..dc5f7e7 100644
--- a/sys/contrib/octeon-sdk/cvmx-nand.c
+++ b/sys/contrib/octeon-sdk/cvmx-nand.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -63,6 +63,11 @@
 #include "cvmx-swap.h"
 #include "cvmx-bootmem.h"
 #endif
+#if defined(__U_BOOT__) && defined(CONFIG_HW_WATCHDOG)
+# include <watchdog.h>
+#else
+# define WATCHDOG_RESET()
+#endif
 
 #define NAND_COMMAND_READ_ID            0x90
 #define NAND_COMMAND_READ_PARAM_PAGE    0xec
@@ -74,17 +79,21 @@
 #define NAND_COMMAND_ERASE_FIN          0xd0
 #define NAND_COMMAND_PROGRAM            0x80
 #define NAND_COMMAND_PROGRAM_FIN        0x10
-#define NAND_TIMEOUT_USECS              1000000
+#define NAND_TIMEOUT_USECS_READ         100000
+#define NAND_TIMEOUT_USECS_WRITE        1000000
+#define NAND_TIMEOUT_USECS_BLOCK_ERASE  1000000
 
-#define CVMX_NAND_ROUNDUP(_Dividend, _Divisor) (((_Dividend)+(_Divisor-1))/(_Divisor))
+#define CVMX_NAND_ROUNDUP(_Dividend, _Divisor) (((_Dividend)+((_Divisor)-1))/(_Divisor))
 #undef min
 #define min(X, Y)                               \
-        ({ typeof (X) __x = (X), __y = (Y);     \
+        ({ typeof (X) __x = (X);                \
+           typeof (Y) __y = (Y);                \
                 (__x < __y) ? __x : __y; })
 
 #undef max
 #define max(X, Y)                               \
-        ({ typeof (X) __x = (X), __y = (Y);     \
+        ({ typeof (X) __x = (X);                \
+           typeof (Y) __y = (Y);                \
                 (__x > __y) ? __x : __y; })
 
 
@@ -109,6 +118,7 @@ static const onfi_speed_mode_desc_t onfi_speed_modes[] =
     {15,10, 30, 5,10},  /* Mode 3 */
     {12,10, 25, 5,10},  /* Mode 4, requires EDO timings */
     {10, 7, 20, 5,10},  /* Mode 5, requries EDO timings */
+    {10,10, 25, 5,12},	/* Mode 6, requires EDO timings */
 };
 
 
@@ -142,12 +152,12 @@ typedef struct
  * Array indexed by bootbus chip select with information
  * about NAND devices.
  */
-#if defined(CVMX_BUILD_FOR_UBOOT) && CONFIG_OCTEON_NAND_STAGE2
+#if defined(__U_BOOT__)
 /* For u-boot nand boot we need to play some tricks to be able
 ** to use this early in boot.  We put them in a special section that is merged
 ** with the text segment.  (Using the text segment directly results in an assembler warning.)
 */
-#define USE_DATA_IN_TEXT
+/*#define USE_DATA_IN_TEXT*/
 #endif
 
 #ifdef USE_DATA_IN_TEXT
@@ -351,7 +361,7 @@ void __set_onfi_timing_mode(int *tim_par, int clocks_us, int mode)
     int margin;
     int pulse_adjust;
 
-    if (mode > 5)
+    if (mode > 6)
     {
         cvmx_dprintf("%s: invalid ONFI timing mode: %d\n", __FUNCTION__, mode);
         return;
@@ -463,6 +473,9 @@ cvmx_nand_status_t cvmx_nand_initialize(cvmx_nand_initialize_flags_t flags, int
     union cvmx_ndf_misc ndf_misc;
     uint8_t nand_id_buffer[16];
 
+    if (!octeon_has_feature(OCTEON_FEATURE_NAND))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_DEVICE);
+
     cvmx_nand_flags = flags;
     CVMX_NAND_LOG_CALLED();
     CVMX_NAND_LOG_PARAM("0x%x", flags);
@@ -472,7 +485,15 @@ cvmx_nand_status_t cvmx_nand_initialize(cvmx_nand_initialize_flags_t flags, int
 #ifndef USE_DATA_IN_TEXT
     /* cvmx_nand_buffer is statically allocated in the TEXT_IN_DATA case */
     if (!cvmx_nand_buffer)
-        cvmx_nand_buffer = cvmx_bootmem_alloc(CVMX_NAND_MAX_PAGE_AND_OOB_SIZE, 128);
+    {
+        cvmx_nand_buffer = cvmx_bootmem_alloc_named_flags(CVMX_NAND_MAX_PAGE_AND_OOB_SIZE, 128, "__nand_buffer", CVMX_BOOTMEM_FLAG_END_ALLOC);
+    }
+    if (!cvmx_nand_buffer) {
+        const cvmx_bootmem_named_block_desc_t *block_desc = cvmx_bootmem_find_named_block("__nand_buffer");
+        if (block_desc)
+            cvmx_nand_buffer = cvmx_phys_to_ptr(block_desc->base_addr);
+    }
+
     if (!cvmx_nand_buffer)
         CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
 #endif
@@ -698,7 +719,8 @@ cvmx_nand_status_t cvmx_nand_initialize(cvmx_nand_initialize_flags_t flags, int
                 /* We have a Samsung part, so decode part info from ID bytes */
                 uint64_t nand_size_bits = (64*1024*1024ULL) << ((nand_id_buffer[4] & 0x70) >> 4); /* Plane size */
                 cvmx_nand_state[chip].page_size = 1024 << (nand_id_buffer[3] & 0x3);  /* NAND page size in bytes */
-                cvmx_nand_state[chip].oob_size = 128;     /* NAND OOB (spare) size in bytes (per page) */
+		/* NAND OOB (spare) size in bytes (per page) */
+		cvmx_nand_state[chip].oob_size = (cvmx_nand_state[chip].page_size / 512) * ((nand_id_buffer[3] & 4) ? 16 : 8);
                 cvmx_nand_state[chip].pages_per_block = (0x10000 << ((nand_id_buffer[3] & 0x30) >> 4))/cvmx_nand_state[chip].page_size;
 
                 nand_size_bits *= 1 << ((nand_id_buffer[4] & 0xc) >> 2);
@@ -708,7 +730,15 @@ cvmx_nand_status_t cvmx_nand_initialize(cvmx_nand_initialize_flags_t flags, int
                     cvmx_nand_state[chip].oob_size *= 2;
 
                 cvmx_nand_state[chip].blocks = nand_size_bits/(8ULL*cvmx_nand_state[chip].page_size*cvmx_nand_state[chip].pages_per_block);
-                cvmx_nand_state[chip].onfi_timing = 2;
+                switch (nand_id_buffer[1]) {
+                case 0xD3:      /* K9F8G08U0M */
+                case 0xDC:      /* K9F4G08U0B */
+                    cvmx_nand_state[chip].onfi_timing = 6;
+                    break;
+                default:
+                    cvmx_nand_state[chip].onfi_timing = 2;
+                    break;
+                }
 
                 if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
                 {
@@ -962,7 +992,7 @@ static inline int __cvmx_nand_get_address_cycles(int chip)
  * @INTERNAL
  * Build the set of command common to most transactions
  * @param chip      NAND chip to program
- * @param cmd_data  NAND comamnd for CLE cycle 1
+ * @param cmd_data  NAND command for CLE cycle 1
  * @param num_address_cycles
  *                  Number of address cycles to put on the bus
  * @param nand_address
@@ -1189,7 +1219,7 @@ static void __cvmx_nand_hex_dump(uint64_t buffer_address, int buffer_length)
  * @param nand_address
  *               NAND address to use for address cycles
  * @param nand_command2
- *               NAND comamnd cycle 2 if not zero
+ *               NAND command cycle 2 if not zero
  * @param buffer_address
  *               Physical address to DMA into
  * @param buffer_length
@@ -1261,11 +1291,13 @@ static inline int __cvmx_nand_low_level_read(int chip, int nand_command1, int ad
 
     if (__cvmx_nand_build_post_cmd())
         CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
-
+    WATCHDOG_RESET();
     /* Wait for the DMA to complete */
-    if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_NDF_DMA_CFG, cvmx_mio_ndf_dma_cfg_t, en, ==, 0, NAND_TIMEOUT_USECS))
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_NDF_DMA_CFG, cvmx_mio_ndf_dma_cfg_t, en, ==, 0, NAND_TIMEOUT_USECS_READ))
+    {
+        WATCHDOG_RESET();
         CVMX_NAND_RETURN(CVMX_NAND_TIMEOUT);
-
+    }
     /* Return the number of bytes transfered */
     ndf_dma_cfg.u64 = cvmx_read_csr(CVMX_MIO_NDF_DMA_CFG);
     bytes = ndf_dma_cfg.s.adr - buffer_address;
@@ -1403,9 +1435,12 @@ cvmx_nand_status_t cvmx_nand_page_write(int chip, uint64_t nand_address, uint64_
         CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
 
     /* Wait for the DMA to complete */
-    if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_NDF_DMA_CFG, cvmx_mio_ndf_dma_cfg_t, en, ==, 0, NAND_TIMEOUT_USECS))
+    WATCHDOG_RESET();
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_NDF_DMA_CFG, cvmx_mio_ndf_dma_cfg_t, en, ==, 0, NAND_TIMEOUT_USECS_WRITE))
+    {
+        WATCHDOG_RESET();
         CVMX_NAND_RETURN(CVMX_NAND_TIMEOUT);
-
+    }
     CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
 }
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
@@ -1448,8 +1483,12 @@ cvmx_nand_status_t cvmx_nand_block_erase(int chip, uint64_t nand_address)
         CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
 
     /* Wait for the command queue to be idle, which means the wait is done */
-    if (CVMX_WAIT_FOR_FIELD64(CVMX_NDF_ST_REG, cvmx_ndf_st_reg_t, exe_idle, ==, 1, NAND_TIMEOUT_USECS))
+    WATCHDOG_RESET();
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_NDF_ST_REG, cvmx_ndf_st_reg_t, exe_idle, ==, 1, NAND_TIMEOUT_USECS_BLOCK_ERASE))
+    {
+        WATCHDOG_RESET();
         CVMX_NAND_RETURN(CVMX_NAND_TIMEOUT);
+    }
 
     CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
 }
diff --git a/sys/contrib/octeon-sdk/cvmx-nand.h b/sys/contrib/octeon-sdk/cvmx-nand.h
index 580dbb3..3cd95f4 100644
--- a/sys/contrib/octeon-sdk/cvmx-nand.h
+++ b/sys/contrib/octeon-sdk/cvmx-nand.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -137,6 +137,7 @@ typedef enum
     CVMX_NAND_INVALID_PARAM = -3,
     CVMX_NAND_TIMEOUT = -4,
     CVMX_NAND_ERROR = -5,
+    CVMX_NAND_NO_DEVICE = -6,
 } cvmx_nand_status_t;
 
 /**
diff --git a/sys/contrib/octeon-sdk/cvmx-ndf-defs.h b/sys/contrib/octeon-sdk/cvmx-ndf-defs.h
index e004236..17964f3 100644
--- a/sys/contrib/octeon-sdk/cvmx-ndf-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-ndf-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,14 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_NDF_TYPEDEFS_H__
-#define __CVMX_NDF_TYPEDEFS_H__
+#ifndef __CVMX_NDF_DEFS_H__
+#define __CVMX_NDF_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_NDF_BT_PG_INFO CVMX_NDF_BT_PG_INFO_FUNC()
 static inline uint64_t CVMX_NDF_BT_PG_INFO_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_NDF_BT_PG_INFO not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070001000018ull);
 }
@@ -67,7 +67,7 @@ static inline uint64_t CVMX_NDF_BT_PG_INFO_FUNC(void)
 #define CVMX_NDF_CMD CVMX_NDF_CMD_FUNC()
 static inline uint64_t CVMX_NDF_CMD_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_NDF_CMD not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070001000000ull);
 }
@@ -78,7 +78,7 @@ static inline uint64_t CVMX_NDF_CMD_FUNC(void)
 #define CVMX_NDF_DRBELL CVMX_NDF_DRBELL_FUNC()
 static inline uint64_t CVMX_NDF_DRBELL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_NDF_DRBELL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070001000030ull);
 }
@@ -89,7 +89,7 @@ static inline uint64_t CVMX_NDF_DRBELL_FUNC(void)
 #define CVMX_NDF_ECC_CNT CVMX_NDF_ECC_CNT_FUNC()
 static inline uint64_t CVMX_NDF_ECC_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_NDF_ECC_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070001000010ull);
 }
@@ -100,7 +100,7 @@ static inline uint64_t CVMX_NDF_ECC_CNT_FUNC(void)
 #define CVMX_NDF_INT CVMX_NDF_INT_FUNC()
 static inline uint64_t CVMX_NDF_INT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_NDF_INT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070001000020ull);
 }
@@ -111,7 +111,7 @@ static inline uint64_t CVMX_NDF_INT_FUNC(void)
 #define CVMX_NDF_INT_EN CVMX_NDF_INT_EN_FUNC()
 static inline uint64_t CVMX_NDF_INT_EN_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_NDF_INT_EN not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070001000028ull);
 }
@@ -122,7 +122,7 @@ static inline uint64_t CVMX_NDF_INT_EN_FUNC(void)
 #define CVMX_NDF_MISC CVMX_NDF_MISC_FUNC()
 static inline uint64_t CVMX_NDF_MISC_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_NDF_MISC not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070001000008ull);
 }
@@ -133,7 +133,7 @@ static inline uint64_t CVMX_NDF_MISC_FUNC(void)
 #define CVMX_NDF_ST_REG CVMX_NDF_ST_REG_FUNC()
 static inline uint64_t CVMX_NDF_ST_REG_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_NDF_ST_REG not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001070001000038ull);
 }
@@ -158,12 +158,10 @@ static inline uint64_t CVMX_NDF_ST_REG_FUNC(void)
  *
  * Like all NDF_... registers, 64-bit operations must be used to access this register
  */
-union cvmx_ndf_bt_pg_info
-{
+union cvmx_ndf_bt_pg_info {
 	uint64_t u64;
-	struct cvmx_ndf_bt_pg_info_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ndf_bt_pg_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t t_mult                       : 4;  /**< Boot time TIM_MULT[3:0] field of SET__TM_PAR[63:0]
                                                          command */
@@ -179,6 +177,9 @@ union cvmx_ndf_bt_pg_info
 	struct cvmx_ndf_bt_pg_info_s          cn52xx;
 	struct cvmx_ndf_bt_pg_info_s          cn63xx;
 	struct cvmx_ndf_bt_pg_info_s          cn63xxp1;
+	struct cvmx_ndf_bt_pg_info_s          cn66xx;
+	struct cvmx_ndf_bt_pg_info_s          cn68xx;
+	struct cvmx_ndf_bt_pg_info_s          cn68xxp1;
 };
 typedef union cvmx_ndf_bt_pg_info cvmx_ndf_bt_pg_info_t;
 
@@ -193,12 +194,10 @@ typedef union cvmx_ndf_bt_pg_info cvmx_ndf_bt_pg_info_t;
  *
  * Like all NDF_... registers, 64-bit operations must be used to access this register
  */
-union cvmx_ndf_cmd
-{
+union cvmx_ndf_cmd {
 	uint64_t u64;
-	struct cvmx_ndf_cmd_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ndf_cmd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t nf_cmd                       : 64; /**< 8 Command Bytes */
 #else
 	uint64_t nf_cmd                       : 64;
@@ -207,6 +206,9 @@ union cvmx_ndf_cmd
 	struct cvmx_ndf_cmd_s                 cn52xx;
 	struct cvmx_ndf_cmd_s                 cn63xx;
 	struct cvmx_ndf_cmd_s                 cn63xxp1;
+	struct cvmx_ndf_cmd_s                 cn66xx;
+	struct cvmx_ndf_cmd_s                 cn68xx;
+	struct cvmx_ndf_cmd_s                 cn68xxp1;
 };
 typedef union cvmx_ndf_cmd cvmx_ndf_cmd_t;
 
@@ -232,12 +234,10 @@ typedef union cvmx_ndf_cmd cvmx_ndf_cmd_t;
  *
  * Like all NDF_... registers, 64-bit operations must be used to access this register
  */
-union cvmx_ndf_drbell
-{
+union cvmx_ndf_drbell {
 	uint64_t u64;
-	struct cvmx_ndf_drbell_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ndf_drbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t cnt                          : 8;  /**< Doorbell count register, 2's complement 8 bit value */
 #else
@@ -248,6 +248,9 @@ union cvmx_ndf_drbell
 	struct cvmx_ndf_drbell_s              cn52xx;
 	struct cvmx_ndf_drbell_s              cn63xx;
 	struct cvmx_ndf_drbell_s              cn63xxp1;
+	struct cvmx_ndf_drbell_s              cn66xx;
+	struct cvmx_ndf_drbell_s              cn68xx;
+	struct cvmx_ndf_drbell_s              cn68xxp1;
 };
 typedef union cvmx_ndf_drbell cvmx_ndf_drbell_t;
 
@@ -261,12 +264,10 @@ typedef union cvmx_ndf_drbell cvmx_ndf_drbell_t;
  *
  * Like all NDF_... registers, 64-bit operations must be used to access this register
  */
-union cvmx_ndf_ecc_cnt
-{
+union cvmx_ndf_ecc_cnt {
 	uint64_t u64;
-	struct cvmx_ndf_ecc_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ndf_ecc_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t xor_ecc                      : 24; /**< result of XOR of ecc read bytes and ecc genarated
                                                          bytes. The value pertains to the last 1 bit ecc err */
@@ -281,6 +282,9 @@ union cvmx_ndf_ecc_cnt
 	struct cvmx_ndf_ecc_cnt_s             cn52xx;
 	struct cvmx_ndf_ecc_cnt_s             cn63xx;
 	struct cvmx_ndf_ecc_cnt_s             cn63xxp1;
+	struct cvmx_ndf_ecc_cnt_s             cn66xx;
+	struct cvmx_ndf_ecc_cnt_s             cn68xx;
+	struct cvmx_ndf_ecc_cnt_s             cn68xxp1;
 };
 typedef union cvmx_ndf_ecc_cnt cvmx_ndf_ecc_cnt_t;
 
@@ -295,12 +299,10 @@ typedef union cvmx_ndf_ecc_cnt cvmx_ndf_ecc_cnt_t;
  *
  * Like all NDF_... registers, 64-bit operations must be used to access this register
  */
-union cvmx_ndf_int
-{
+union cvmx_ndf_int {
 	uint64_t u64;
-	struct cvmx_ndf_int_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ndf_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t ovrf                         : 1;  /**< NDF_CMD write when fifo is full. Generally a
                                                          fatal error. */
@@ -324,6 +326,9 @@ union cvmx_ndf_int
 	struct cvmx_ndf_int_s                 cn52xx;
 	struct cvmx_ndf_int_s                 cn63xx;
 	struct cvmx_ndf_int_s                 cn63xxp1;
+	struct cvmx_ndf_int_s                 cn66xx;
+	struct cvmx_ndf_int_s                 cn68xx;
+	struct cvmx_ndf_int_s                 cn68xxp1;
 };
 typedef union cvmx_ndf_int cvmx_ndf_int_t;
 
@@ -334,12 +339,10 @@ typedef union cvmx_ndf_int cvmx_ndf_int_t;
  * Like all NDF_... registers, 64-bit operations must be used to access this register
  *
  */
-union cvmx_ndf_int_en
-{
+union cvmx_ndf_int_en {
 	uint64_t u64;
-	struct cvmx_ndf_int_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ndf_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t ovrf                         : 1;  /**< Wrote to a full command fifo */
 	uint64_t ecc_mult                     : 1;  /**< Multi bit ECC error detected during boot */
@@ -362,6 +365,9 @@ union cvmx_ndf_int_en
 	struct cvmx_ndf_int_en_s              cn52xx;
 	struct cvmx_ndf_int_en_s              cn63xx;
 	struct cvmx_ndf_int_en_s              cn63xxp1;
+	struct cvmx_ndf_int_en_s              cn66xx;
+	struct cvmx_ndf_int_en_s              cn68xx;
+	struct cvmx_ndf_int_en_s              cn68xxp1;
 };
 typedef union cvmx_ndf_int_en cvmx_ndf_int_en_t;
 
@@ -409,12 +415,10 @@ typedef union cvmx_ndf_int_en cvmx_ndf_int_en_t;
  *
  * Like all NDF_... registers, 64-bit operations must be used to access this register
  */
-union cvmx_ndf_misc
-{
+union cvmx_ndf_misc {
 	uint64_t u64;
-	struct cvmx_ndf_misc_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ndf_misc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t mb_dis                       : 1;  /**< Disable multibit error hangs and allow boot loads
                                                          or boot dma's proceed as if no multi bit errors
@@ -451,9 +455,8 @@ union cvmx_ndf_misc
 	uint64_t reserved_28_63               : 36;
 #endif
 	} s;
-	struct cvmx_ndf_misc_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ndf_misc_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_27_63               : 37;
 	uint64_t nbr_hwm                      : 3;  /**< Hi Water mark for NBR fifo or load/stores */
 	uint64_t wait_cnt                     : 6;  /**< WAIT input filter count */
@@ -488,6 +491,9 @@ union cvmx_ndf_misc
 	} cn52xx;
 	struct cvmx_ndf_misc_s                cn63xx;
 	struct cvmx_ndf_misc_s                cn63xxp1;
+	struct cvmx_ndf_misc_s                cn66xx;
+	struct cvmx_ndf_misc_s                cn68xx;
+	struct cvmx_ndf_misc_s                cn68xxp1;
 };
 typedef union cvmx_ndf_misc cvmx_ndf_misc_t;
 
@@ -498,12 +504,10 @@ typedef union cvmx_ndf_misc cvmx_ndf_misc_t;
  * This CSR aggregates all state machines used in nand flash controller for debug.
  * Like all NDF_... registers, 64-bit operations must be used to access this register
  */
-union cvmx_ndf_st_reg
-{
+union cvmx_ndf_st_reg {
 	uint64_t u64;
-	struct cvmx_ndf_st_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_ndf_st_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t exe_idle                     : 1;  /**< Command Execution status 1=IDLE, 0=Busy
                                                          1 means execution of command sequence is complete
@@ -528,6 +532,9 @@ union cvmx_ndf_st_reg
 	struct cvmx_ndf_st_reg_s              cn52xx;
 	struct cvmx_ndf_st_reg_s              cn63xx;
 	struct cvmx_ndf_st_reg_s              cn63xxp1;
+	struct cvmx_ndf_st_reg_s              cn66xx;
+	struct cvmx_ndf_st_reg_s              cn68xx;
+	struct cvmx_ndf_st_reg_s              cn68xxp1;
 };
 typedef union cvmx_ndf_st_reg cvmx_ndf_st_reg_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-npei-defs.h b/sys/contrib/octeon-sdk/cvmx-npei-defs.h
index 72155f8..0714258 100644
--- a/sys/contrib/octeon-sdk/cvmx-npei-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-npei-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_NPEI_TYPEDEFS_H__
-#define __CVMX_NPEI_TYPEDEFS_H__
+#ifndef __CVMX_NPEI_DEFS_H__
+#define __CVMX_NPEI_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_NPEI_BAR1_INDEXX(unsigned long offset)
@@ -421,10 +421,10 @@ static inline uint64_t CVMX_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 12) && (offset <= 27)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 12) && (offset <= 27))))))
 		cvmx_warn("CVMX_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
-	return 0x0000000000000340ull + ((offset) & 31) * 16 - 16*12;
+	return 0x0000000000000280ull + ((offset) & 31) * 16 - 16*12;
 }
 #else
-#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12)
+#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16*12)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_NPEI_MSI_ENB0 CVMX_NPEI_MSI_ENB0_FUNC()
@@ -1253,12 +1253,10 @@ static inline uint64_t CVMX_NPEI_WIN_WR_MASK_FUNC(void)
  * NPEI_BAR1_INDEX0 through NPEI_BAR1_INDEX15 is used for transactions orginating with PCIE-PORT0 and NPEI_BAR1_INDEX16
  * through NPEI_BAR1_INDEX31 is used for transactions originating with PCIE-PORT1.
  */
-union cvmx_npei_bar1_indexx
-{
+union cvmx_npei_bar1_indexx {
 	uint32_t u32;
-	struct cvmx_npei_bar1_indexx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_bar1_indexx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_18_31               : 14;
 	uint32_t addr_idx                     : 14; /**< Address bits [35:22] sent to L2C */
 	uint32_t ca                           : 1;  /**< Set '1' when access is not to be cached in L2. */
@@ -1286,12 +1284,10 @@ typedef union cvmx_npei_bar1_indexx cvmx_npei_bar1_indexx_t;
  *
  * Results from BIST runs of NPEI's memories.
  */
-union cvmx_npei_bist_status
-{
+union cvmx_npei_bist_status {
 	uint64_t u64;
-	struct cvmx_npei_bist_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t pkt_rdf                      : 1;  /**< BIST Status for PKT Read FIFO */
 	uint64_t reserved_60_62               : 3;
 	uint64_t pcr_gim                      : 1;  /**< BIST Status for PKT Gather Instr MEM */
@@ -1393,9 +1389,8 @@ union cvmx_npei_bist_status
 	uint64_t pkt_rdf                      : 1;
 #endif
 	} s;
-	struct cvmx_npei_bist_status_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_bist_status_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t pkt_rdf                      : 1;  /**< BIST Status for PKT Read FIFO */
 	uint64_t reserved_60_62               : 3;
 	uint64_t pcr_gim                      : 1;  /**< BIST Status for PKT Gather Instr MEM */
@@ -1515,9 +1510,8 @@ union cvmx_npei_bist_status
 	uint64_t pkt_rdf                      : 1;
 #endif
 	} cn52xx;
-	struct cvmx_npei_bist_status_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_bist_status_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_46_63               : 18;
 	uint64_t d0_mem0                      : 1;  /**< BIST Status for DMA0 Memory */
 	uint64_t d1_mem1                      : 1;  /**< BIST Status for DMA1 Memory */
@@ -1616,9 +1610,8 @@ union cvmx_npei_bist_status
 #endif
 	} cn52xxp1;
 	struct cvmx_npei_bist_status_cn52xx   cn56xx;
-	struct cvmx_npei_bist_status_cn56xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_bist_status_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_58_63               : 6;
 	uint64_t pcsr_int                     : 1;  /**< BIST Status for PKT pout_int_bstatus */
 	uint64_t pcsr_im                      : 1;  /**< BIST Status for PKT pcsr_instr_mem_bstatus */
@@ -1750,12 +1743,10 @@ typedef union cvmx_npei_bist_status cvmx_npei_bist_status_t;
  *
  * Results from BIST runs of NPEI's memories.
  */
-union cvmx_npei_bist_status2
-{
+union cvmx_npei_bist_status2 {
 	uint64_t u64;
-	struct cvmx_npei_bist_status2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_bist_status2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t prd_tag                      : 1;  /**< BIST Status for DMA PCIE RD Tag MEM */
 	uint64_t prd_st0                      : 1;  /**< BIST Status for DMA PCIE RD state MEM 0 */
@@ -1801,12 +1792,10 @@ typedef union cvmx_npei_bist_status2 cvmx_npei_bist_status2_t;
  *
  * Contains control for access for Port0
  */
-union cvmx_npei_ctl_port0
-{
+union cvmx_npei_ctl_port0 {
 	uint64_t u64;
-	struct cvmx_npei_ctl_port0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_ctl_port0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_21_63               : 43;
 	uint64_t waitl_com                    : 1;  /**< When set '1' casues the NPI to wait for a commit
                                                          from the L2C before sending additional completions
@@ -1876,12 +1865,10 @@ typedef union cvmx_npei_ctl_port0 cvmx_npei_ctl_port0_t;
  *
  * Contains control for access for Port1
  */
-union cvmx_npei_ctl_port1
-{
+union cvmx_npei_ctl_port1 {
 	uint64_t u64;
-	struct cvmx_npei_ctl_port1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_ctl_port1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_21_63               : 43;
 	uint64_t waitl_com                    : 1;  /**< When set '1' casues the NPI to wait for a commit
                                                          from the L2C before sending additional completions
@@ -1952,12 +1939,10 @@ typedef union cvmx_npei_ctl_port1 cvmx_npei_ctl_port1_t;
  * To ensure that a write has completed the user must read the register before making an access(i.e. PCIe memory space)
  * that requires the value of this register to be updated.
  */
-union cvmx_npei_ctl_status
-{
+union cvmx_npei_ctl_status {
 	uint64_t u64;
-	struct cvmx_npei_ctl_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_44_63               : 20;
 	uint64_t p1_ntags                     : 6;  /**< Number of tags avaiable for PCIe Port1.
                                                          In RC mode 1 tag is needed for each outbound TLP
@@ -2011,9 +1996,8 @@ union cvmx_npei_ctl_status
 #endif
 	} s;
 	struct cvmx_npei_ctl_status_s         cn52xx;
-	struct cvmx_npei_ctl_status_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_ctl_status_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_44_63               : 20;
 	uint64_t p1_ntags                     : 6;  /**< Number of tags avaiable for PCIe Port1.
                                                          In RC mode 1 tag is needed for each outbound TLP
@@ -2062,9 +2046,8 @@ union cvmx_npei_ctl_status
 #endif
 	} cn52xxp1;
 	struct cvmx_npei_ctl_status_s         cn56xx;
-	struct cvmx_npei_ctl_status_cn56xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_ctl_status_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_15_63               : 49;
 	uint64_t lnk_rst                      : 1;  /**< Set when PCIe Core 0 request a link reset due to
                                                          link down state. This bit is only reset on raw
@@ -2098,12 +2081,10 @@ typedef union cvmx_npei_ctl_status cvmx_npei_ctl_status_t;
  * To ensure that a write has completed the user must read the register before
  * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
  */
-union cvmx_npei_ctl_status2
-{
+union cvmx_npei_ctl_status2 {
 	uint64_t u64;
-	struct cvmx_npei_ctl_status2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_ctl_status2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t mps                          : 1;  /**< Max Payload Size
                                                                   0  = 128B
@@ -2210,12 +2191,10 @@ typedef union cvmx_npei_ctl_status2 cvmx_npei_ctl_status2_t;
  *
  * The EXEC data out fifo-count and the data unload counter.
  */
-union cvmx_npei_data_out_cnt
-{
+union cvmx_npei_data_out_cnt {
 	uint64_t u64;
-	struct cvmx_npei_data_out_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_data_out_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_44_63               : 20;
 	uint64_t p1_ucnt                      : 16; /**< PCIE-Port1 Fifo Unload Count. This counter is
                                                          incremented by '1' every time a word is removed
@@ -2253,12 +2232,10 @@ typedef union cvmx_npei_data_out_cnt cvmx_npei_data_out_cnt_t;
  *
  * Value returned on the debug-data lines from the RSLs
  */
-union cvmx_npei_dbg_data
-{
+union cvmx_npei_dbg_data {
 	uint64_t u64;
-	struct cvmx_npei_dbg_data_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dbg_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t qlm0_rev_lanes               : 1;  /**< Lane reversal for PCIe port 0 */
 	uint64_t reserved_25_26               : 2;
@@ -2282,9 +2259,8 @@ union cvmx_npei_dbg_data
 	uint64_t reserved_28_63               : 36;
 #endif
 	} s;
-	struct cvmx_npei_dbg_data_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dbg_data_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t qlm0_link_width              : 1;  /**< Link width of PCIe port 0
                                                          0 = PCIe port 0 is 2 lanes,
@@ -2319,9 +2295,8 @@ union cvmx_npei_dbg_data
 #endif
 	} cn52xx;
 	struct cvmx_npei_dbg_data_cn52xx      cn52xxp1;
-	struct cvmx_npei_dbg_data_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dbg_data_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t qlm2_rev_lanes               : 1;  /**< Lane reversal for PCIe port 1 */
 	uint64_t qlm0_rev_lanes               : 1;  /**< Lane reversal for PCIe port 0 */
@@ -2362,12 +2337,10 @@ typedef union cvmx_npei_dbg_data cvmx_npei_dbg_data_t;
  *
  * Contains the debug select value last written to the RSLs.
  */
-union cvmx_npei_dbg_select
-{
+union cvmx_npei_dbg_select {
 	uint64_t u64;
-	struct cvmx_npei_dbg_select_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dbg_select_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t dbg_sel                      : 16; /**< When this register is written its value is sent to
                                                          all RSLs. */
@@ -2390,12 +2363,10 @@ typedef union cvmx_npei_dbg_select cvmx_npei_dbg_select_t;
  *
  * Values for determing the number of instructions for DMA[0..4] in the NPEI.
  */
-union cvmx_npei_dmax_counts
-{
+union cvmx_npei_dmax_counts {
 	uint64_t u64;
-	struct cvmx_npei_dmax_counts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dmax_counts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_39_63               : 25;
 	uint64_t fcnt                         : 7;  /**< Number of words in the Instruction FIFO. */
 	uint64_t dbell                        : 32; /**< Number of available words of Instructions to read. */
@@ -2419,12 +2390,10 @@ typedef union cvmx_npei_dmax_counts cvmx_npei_dmax_counts_t;
  *
  * The door bell register for DMA[0..4] queue.
  */
-union cvmx_npei_dmax_dbell
-{
+union cvmx_npei_dmax_dbell {
 	uint32_t u32;
-	struct cvmx_npei_dmax_dbell_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dmax_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_16_31               : 16;
 	uint32_t dbell                        : 16; /**< The value written to this register is added to the
                                                          number of 8byte words to be read and processes for
@@ -2448,12 +2417,10 @@ typedef union cvmx_npei_dmax_dbell cvmx_npei_dmax_dbell_t;
  *
  * The address to start reading Instructions from for DMA[0..4].
  */
-union cvmx_npei_dmax_ibuff_saddr
-{
+union cvmx_npei_dmax_ibuff_saddr {
 	uint64_t u64;
-	struct cvmx_npei_dmax_ibuff_saddr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dmax_ibuff_saddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_37_63               : 27;
 	uint64_t idle                         : 1;  /**< DMA Engine IDLE state */
 	uint64_t saddr                        : 29; /**< The 128 byte aligned starting address to read the
@@ -2468,9 +2435,8 @@ union cvmx_npei_dmax_ibuff_saddr
 #endif
 	} s;
 	struct cvmx_npei_dmax_ibuff_saddr_s   cn52xx;
-	struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t saddr                        : 29; /**< The 128 byte aligned starting address to read the
                                                          first instruction. SADDR is address bit 35:7 of the
@@ -2494,12 +2460,10 @@ typedef union cvmx_npei_dmax_ibuff_saddr cvmx_npei_dmax_ibuff_saddr_t;
  *
  * Place NPEI will read the next Ichunk data from. This is valid when state is 0
  */
-union cvmx_npei_dmax_naddr
-{
+union cvmx_npei_dmax_naddr {
 	uint64_t u64;
-	struct cvmx_npei_dmax_naddr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dmax_naddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t addr                         : 36; /**< The next L2C address to read DMA# instructions
                                                          from. */
@@ -2522,12 +2486,10 @@ typedef union cvmx_npei_dmax_naddr cvmx_npei_dmax_naddr_t;
  *
  * Thresholds for DMA count and timer interrupts for DMA0.
  */
-union cvmx_npei_dma0_int_level
-{
+union cvmx_npei_dma0_int_level {
 	uint64_t u64;
-	struct cvmx_npei_dma0_int_level_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dma0_int_level_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t time                         : 32; /**< Whenever the DMA_CNT0 timer exceeds
                                                          this value, NPEI_INT_SUM[DTIME0] is set.
                                                          The DMA_CNT0 timer increments every core clock
@@ -2554,12 +2516,10 @@ typedef union cvmx_npei_dma0_int_level cvmx_npei_dma0_int_level_t;
  *
  * Thresholds for DMA count and timer interrupts for DMA1.
  */
-union cvmx_npei_dma1_int_level
-{
+union cvmx_npei_dma1_int_level {
 	uint64_t u64;
-	struct cvmx_npei_dma1_int_level_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dma1_int_level_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t time                         : 32; /**< Whenever the DMA_CNT1 timer exceeds
                                                          this value, NPEI_INT_SUM[DTIME1] is set.
                                                          The DMA_CNT1 timer increments every core clock
@@ -2586,12 +2546,10 @@ typedef union cvmx_npei_dma1_int_level cvmx_npei_dma1_int_level_t;
  *
  * The DMA Count values for DMA0 and DMA1.
  */
-union cvmx_npei_dma_cnts
-{
+union cvmx_npei_dma_cnts {
 	uint64_t u64;
-	struct cvmx_npei_dma_cnts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dma_cnts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t dma1                         : 32; /**< The DMA counter 1.
                                                          Writing this field will cause the written value to
                                                          be subtracted from DMA1. SW should use a 4-byte
@@ -2631,12 +2589,10 @@ typedef union cvmx_npei_dma_cnts cvmx_npei_dma_cnts_t;
  *
  * Controls operation of the DMA IN/OUT.
  */
-union cvmx_npei_dma_control
-{
+union cvmx_npei_dma_control {
 	uint64_t u64;
-	struct cvmx_npei_dma_control_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dma_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t p_32b_m                      : 1;  /**< DMA PCIE 32-bit word read disable bit
                                                          When 0, enable the feature */
@@ -2704,9 +2660,8 @@ union cvmx_npei_dma_control
 #endif
 	} s;
 	struct cvmx_npei_dma_control_s        cn52xx;
-	struct cvmx_npei_dma_control_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dma_control_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_38_63               : 26;
 	uint64_t dma3_enb                     : 1;  /**< DMA# enable. Enables the operation of the DMA
                                                          engine. After being enabled a DMA engine should not
@@ -2767,9 +2722,8 @@ union cvmx_npei_dma_control
 #endif
 	} cn52xxp1;
 	struct cvmx_npei_dma_control_s        cn56xx;
-	struct cvmx_npei_dma_control_cn56xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dma_control_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_39_63               : 25;
 	uint64_t dma4_enb                     : 1;  /**< DMA# enable. Enables the operation of the DMA
                                                          engine. After being enabled a DMA engine should not
@@ -2843,12 +2797,10 @@ typedef union cvmx_npei_dma_control cvmx_npei_dma_control_t;
  *
  * Outstanding PCIE read request number for DMAs and Packet, maximum number is 16
  */
-union cvmx_npei_dma_pcie_req_num
-{
+union cvmx_npei_dma_pcie_req_num {
 	uint64_t u64;
-	struct cvmx_npei_dma_pcie_req_num_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dma_pcie_req_num_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t dma_arb                      : 1;  /**< DMA_PKT Read Request Arbitration
                                                          - 1: DMA0-4 and PKT are round robin. i.e.
                                                              DMA0-DMA1-DMA2-DMA3-DMA4-PKT...
@@ -2930,12 +2882,10 @@ typedef union cvmx_npei_dma_pcie_req_num cvmx_npei_dma_pcie_req_num_t;
  *
  * Results from DMA state register 1
  */
-union cvmx_npei_dma_state1
-{
+union cvmx_npei_dma_state1 {
 	uint64_t u64;
-	struct cvmx_npei_dma_state1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dma_state1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t d4_dwe                       : 8;  /**< DMA4 PICe Write State */
 	uint64_t d3_dwe                       : 8;  /**< DMA3 PICe Write State */
@@ -2962,12 +2912,10 @@ typedef union cvmx_npei_dma_state1 cvmx_npei_dma_state1_t;
  *
  * DMA engine Debug information.
  */
-union cvmx_npei_dma_state1_p1
-{
+union cvmx_npei_dma_state1_p1 {
 	uint64_t u64;
-	struct cvmx_npei_dma_state1_p1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dma_state1_p1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_60_63               : 4;
 	uint64_t d0_difst                     : 7;  /**< DMA engine 0 dif instruction read state */
 	uint64_t d1_difst                     : 7;  /**< DMA engine 1 dif instruction read state */
@@ -2993,9 +2941,8 @@ union cvmx_npei_dma_state1_p1
 	uint64_t reserved_60_63               : 4;
 #endif
 	} s;
-	struct cvmx_npei_dma_state1_p1_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dma_state1_p1_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_60_63               : 4;
 	uint64_t d0_difst                     : 7;  /**< DMA engine 0 dif instruction read state */
 	uint64_t d1_difst                     : 7;  /**< DMA engine 1 dif instruction read state */
@@ -3032,12 +2979,10 @@ typedef union cvmx_npei_dma_state1_p1 cvmx_npei_dma_state1_p1_t;
  *
  * Results from DMA state register 2
  */
-union cvmx_npei_dma_state2
-{
+union cvmx_npei_dma_state2 {
 	uint64_t u64;
-	struct cvmx_npei_dma_state2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dma_state2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t ndwe                         : 4;  /**< DMA L2C Write State */
 	uint64_t reserved_21_23               : 3;
@@ -3064,12 +3009,10 @@ typedef union cvmx_npei_dma_state2 cvmx_npei_dma_state2_t;
  *
  * DMA engine Debug information.
  */
-union cvmx_npei_dma_state2_p1
-{
+union cvmx_npei_dma_state2_p1 {
 	uint64_t u64;
-	struct cvmx_npei_dma_state2_p1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dma_state2_p1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_45_63               : 19;
 	uint64_t d0_dffst                     : 9;  /**< DMA engine 0 dif instruction fetch state */
 	uint64_t d1_dffst                     : 9;  /**< DMA engine 1 dif instruction fetch state */
@@ -3085,9 +3028,8 @@ union cvmx_npei_dma_state2_p1
 	uint64_t reserved_45_63               : 19;
 #endif
 	} s;
-	struct cvmx_npei_dma_state2_p1_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dma_state2_p1_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_45_63               : 19;
 	uint64_t d0_dffst                     : 9;  /**< DMA engine 0 dif instruction fetch state */
 	uint64_t d1_dffst                     : 9;  /**< DMA engine 1 dif instruction fetch state */
@@ -3114,12 +3056,10 @@ typedef union cvmx_npei_dma_state2_p1 cvmx_npei_dma_state2_p1_t;
  *
  * DMA engine Debug information.
  */
-union cvmx_npei_dma_state3_p1
-{
+union cvmx_npei_dma_state3_p1 {
 	uint64_t u64;
-	struct cvmx_npei_dma_state3_p1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dma_state3_p1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_60_63               : 4;
 	uint64_t d0_drest                     : 15; /**< DMA engine 0 dre state */
 	uint64_t d1_drest                     : 15; /**< DMA engine 1 dre state */
@@ -3145,12 +3085,10 @@ typedef union cvmx_npei_dma_state3_p1 cvmx_npei_dma_state3_p1_t;
  *
  * DMA engine Debug information.
  */
-union cvmx_npei_dma_state4_p1
-{
+union cvmx_npei_dma_state4_p1 {
 	uint64_t u64;
-	struct cvmx_npei_dma_state4_p1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dma_state4_p1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_52_63               : 12;
 	uint64_t d0_dwest                     : 13; /**< DMA engine 0 dwe state */
 	uint64_t d1_dwest                     : 13; /**< DMA engine 1 dwe state */
@@ -3176,12 +3114,10 @@ typedef union cvmx_npei_dma_state4_p1 cvmx_npei_dma_state4_p1_t;
  *
  * DMA engine Debug information.
  */
-union cvmx_npei_dma_state5_p1
-{
+union cvmx_npei_dma_state5_p1 {
 	uint64_t u64;
-	struct cvmx_npei_dma_state5_p1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_dma_state5_p1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t d4_drest                     : 15; /**< DMA engine 4 dre state */
 	uint64_t d4_dwest                     : 13; /**< DMA engine 4 dwe state */
@@ -3202,12 +3138,10 @@ typedef union cvmx_npei_dma_state5_p1 cvmx_npei_dma_state5_p1_t;
  *
  * Used to allow the generation of interrupts (MSI/INTA) to the PCIe CoresUsed to enable the various interrupting conditions of NPEI
  */
-union cvmx_npei_int_a_enb
-{
+union cvmx_npei_int_a_enb {
 	uint64_t u64;
-	struct cvmx_npei_int_a_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_int_a_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t pout_err                     : 1;  /**< Enables NPEI_INT_A_SUM[9] to generate an
                                                          interrupt to the PCIE core for MSI/inta. */
@@ -3244,9 +3178,8 @@ union cvmx_npei_int_a_enb
 #endif
 	} s;
 	struct cvmx_npei_int_a_enb_s          cn52xx;
-	struct cvmx_npei_int_a_enb_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_int_a_enb_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t dma1_cpl                     : 1;  /**< Enables NPEI_INT_A_SUM[1] to generate an
                                                          interrupt to the PCIE core for MSI/inta. */
@@ -3269,12 +3202,10 @@ typedef union cvmx_npei_int_a_enb cvmx_npei_int_a_enb_t;
  *
  * Used to enable the various interrupting conditions of NPEI
  */
-union cvmx_npei_int_a_enb2
-{
+union cvmx_npei_int_a_enb2 {
 	uint64_t u64;
-	struct cvmx_npei_int_a_enb2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_int_a_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t pout_err                     : 1;  /**< Enables NPEI_INT_A_SUM[9] to generate an
                                                          interrupt on the RSL. */
@@ -3311,9 +3242,8 @@ union cvmx_npei_int_a_enb2
 #endif
 	} s;
 	struct cvmx_npei_int_a_enb2_s         cn52xx;
-	struct cvmx_npei_int_a_enb2_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_int_a_enb2_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t dma1_cpl                     : 1;  /**< Enables NPEI_INT_A_SUM[1] to generate an
                                                          interrupt to the PCIE core for MSI/inta. */
@@ -3337,12 +3267,10 @@ typedef union cvmx_npei_int_a_enb2 cvmx_npei_int_a_enb2_t;
  * Set when an interrupt condition occurs, write '1' to clear. When an interrupt bitin this register is set and
  * the cooresponding bit in the NPEI_INT_A_ENB register is set, then NPEI_INT_SUM[61] will be set.
  */
-union cvmx_npei_int_a_sum
-{
+union cvmx_npei_int_a_sum {
 	uint64_t u64;
-	struct cvmx_npei_int_a_sum_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_int_a_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t pout_err                     : 1;  /**< Set when PKO sends packet data with the error bit
                                                          set. */
@@ -3377,9 +3305,8 @@ union cvmx_npei_int_a_sum
 #endif
 	} s;
 	struct cvmx_npei_int_a_sum_s          cn52xx;
-	struct cvmx_npei_int_a_sum_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_int_a_sum_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t dma1_cpl                     : 1;  /**< Set each time any PCIe DMA engine recieves a UR/CA
                                                          response from PCIe Port 1 */
@@ -3402,12 +3329,10 @@ typedef union cvmx_npei_int_a_sum cvmx_npei_int_a_sum_t;
  *
  * Used to allow the generation of interrupts (MSI/INTA) to the PCIe CoresUsed to enable the various interrupting conditions of NPI
  */
-union cvmx_npei_int_enb
-{
+union cvmx_npei_int_enb {
 	uint64_t u64;
-	struct cvmx_npei_int_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t mio_inta                     : 1;  /**< Enables NPEI_INT_SUM[63] to generate an
                                                          interrupt to the PCIE core for MSI/inta. */
 	uint64_t reserved_62_62               : 1;
@@ -3603,9 +3528,8 @@ union cvmx_npei_int_enb
 #endif
 	} s;
 	struct cvmx_npei_int_enb_s            cn52xx;
-	struct cvmx_npei_int_enb_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_int_enb_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t mio_inta                     : 1;  /**< Enables NPEI_INT_SUM[63] to generate an
                                                          interrupt to the PCIE core for MSI/inta. */
 	uint64_t reserved_62_62               : 1;
@@ -3800,9 +3724,8 @@ union cvmx_npei_int_enb
 #endif
 	} cn52xxp1;
 	struct cvmx_npei_int_enb_s            cn56xx;
-	struct cvmx_npei_int_enb_cn56xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_int_enb_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t mio_inta                     : 1;  /**< Enables NPEI_INT_SUM[63] to generate an
                                                          interrupt to the PCIE core for MSI/inta. */
 	uint64_t reserved_61_62               : 2;
@@ -4000,12 +3923,10 @@ typedef union cvmx_npei_int_enb cvmx_npei_int_enb_t;
  *
  * Used to enable the various interrupting conditions of NPI
  */
-union cvmx_npei_int_enb2
-{
+union cvmx_npei_int_enb2 {
 	uint64_t u64;
-	struct cvmx_npei_int_enb2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_int_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_62_63               : 2;
 	uint64_t int_a                        : 1;  /**< Enables NPEI_INT_SUM2[61] to generate an
                                                          interrupt on the RSL. */
@@ -4198,9 +4119,8 @@ union cvmx_npei_int_enb2
 #endif
 	} s;
 	struct cvmx_npei_int_enb2_s           cn52xx;
-	struct cvmx_npei_int_enb2_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_int_enb2_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_62_63               : 2;
 	uint64_t int_a                        : 1;  /**< Enables NPEI_INT_SUM2[61] to generate an
                                                          interrupt on the RSL. */
@@ -4392,9 +4312,8 @@ union cvmx_npei_int_enb2
 #endif
 	} cn52xxp1;
 	struct cvmx_npei_int_enb2_s           cn56xx;
-	struct cvmx_npei_int_enb2_cn56xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_int_enb2_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_61_63               : 3;
 	uint64_t c1_ldwn                      : 1;  /**< Enables NPEI_INT_SUM[60] to generate an
                                                          interrupt on the RSL. */
@@ -4589,12 +4508,10 @@ typedef union cvmx_npei_int_enb2 cvmx_npei_int_enb2_t;
  *
  * Contains information about some of the interrupt condition that can occur in the NPEI_INTERRUPT_SUM register.
  */
-union cvmx_npei_int_info
-{
+union cvmx_npei_int_info {
 	uint64_t u64;
-	struct cvmx_npei_int_info_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_int_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t pidbof                       : 6;  /**< Field set when the NPEI_INTERRUPT_SUM[PIDBOF] bit
                                                          is set. This field when set will not change again
@@ -4633,12 +4550,10 @@ typedef union cvmx_npei_int_info cvmx_npei_int_info_t;
  * <31>    P0_PTOUT R/W1C    0x0         0         Port-0 output had a read timeout on a DATA/INFO         $R     NS
  *                                                 pair.
  */
-union cvmx_npei_int_sum
-{
+union cvmx_npei_int_sum {
 	uint64_t u64;
-	struct cvmx_npei_int_sum_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t mio_inta                     : 1;  /**< Interrupt from MIO. */
 	uint64_t reserved_62_62               : 1;
 	uint64_t int_a                        : 1;  /**< Set when a bit in the NPEI_INT_A_SUM register and
@@ -4839,9 +4754,8 @@ union cvmx_npei_int_sum
 #endif
 	} s;
 	struct cvmx_npei_int_sum_s            cn52xx;
-	struct cvmx_npei_int_sum_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_int_sum_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t mio_inta                     : 1;  /**< Interrupt from MIO. */
 	uint64_t reserved_62_62               : 1;
 	uint64_t int_a                        : 1;  /**< Set when a bit in the NPEI_INT_A_SUM register and
@@ -5031,9 +4945,8 @@ union cvmx_npei_int_sum
 #endif
 	} cn52xxp1;
 	struct cvmx_npei_int_sum_s            cn56xx;
-	struct cvmx_npei_int_sum_cn56xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_int_sum_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t mio_inta                     : 1;  /**< Interrupt from MIO. */
 	uint64_t reserved_61_62               : 2;
 	uint64_t c1_ldwn                      : 1;  /**< Reset request due to link1 down status. */
@@ -5229,12 +5142,10 @@ typedef union cvmx_npei_int_sum cvmx_npei_int_sum_t;
  *
  * This is a read only copy of the NPEI_INTERRUPT_SUM register with bit variances.
  */
-union cvmx_npei_int_sum2
-{
+union cvmx_npei_int_sum2 {
 	uint64_t u64;
-	struct cvmx_npei_int_sum2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_int_sum2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t mio_inta                     : 1;  /**< Equal to the cooresponding bit if the
                                                          NPEI_INT_SUM register. */
 	uint64_t reserved_62_62               : 1;
@@ -5432,12 +5343,10 @@ typedef union cvmx_npei_int_sum2 cvmx_npei_int_sum2_t;
  *
  * The data from the last initiated window read.
  */
-union cvmx_npei_last_win_rdata0
-{
+union cvmx_npei_last_win_rdata0 {
 	uint64_t u64;
-	struct cvmx_npei_last_win_rdata0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_last_win_rdata0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 64; /**< Last window read data. */
 #else
 	uint64_t data                         : 64;
@@ -5457,12 +5366,10 @@ typedef union cvmx_npei_last_win_rdata0 cvmx_npei_last_win_rdata0_t;
  *
  * The data from the last initiated window read.
  */
-union cvmx_npei_last_win_rdata1
-{
+union cvmx_npei_last_win_rdata1 {
 	uint64_t u64;
-	struct cvmx_npei_last_win_rdata1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_last_win_rdata1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 64; /**< Last window read data. */
 #else
 	uint64_t data                         : 64;
@@ -5482,12 +5389,10 @@ typedef union cvmx_npei_last_win_rdata1 cvmx_npei_last_win_rdata1_t;
  *
  * Contains control for access to the PCIe address space.
  */
-union cvmx_npei_mem_access_ctl
-{
+union cvmx_npei_mem_access_ctl {
 	uint64_t u64;
-	struct cvmx_npei_mem_access_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_mem_access_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t max_word                     : 4;  /**< The maximum number of words to merge into a single
                                                          write operation from the PPs to the PCIe. Legal
@@ -5517,12 +5422,10 @@ typedef union cvmx_npei_mem_access_ctl cvmx_npei_mem_access_ctl_t;
  *
  * Contains address index and control bits for access to memory from Core PPs.
  */
-union cvmx_npei_mem_access_subidx
-{
+union cvmx_npei_mem_access_subidx {
 	uint64_t u64;
-	struct cvmx_npei_mem_access_subidx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_mem_access_subidx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_42_63               : 22;
 	uint64_t zero                         : 1;  /**< Causes all byte reads to be zero length reads.
                                                          Returns to the EXEC a zero for all read data. */
@@ -5563,12 +5466,10 @@ typedef union cvmx_npei_mem_access_subidx cvmx_npei_mem_access_subidx_t;
  *
  * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV0.
  */
-union cvmx_npei_msi_enb0
-{
+union cvmx_npei_msi_enb0 {
 	uint64_t u64;
-	struct cvmx_npei_msi_enb0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_msi_enb0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t enb                          : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV0. */
 #else
 	uint64_t enb                          : 64;
@@ -5588,12 +5489,10 @@ typedef union cvmx_npei_msi_enb0 cvmx_npei_msi_enb0_t;
  *
  * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV1.
  */
-union cvmx_npei_msi_enb1
-{
+union cvmx_npei_msi_enb1 {
 	uint64_t u64;
-	struct cvmx_npei_msi_enb1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_msi_enb1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t enb                          : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV1. */
 #else
 	uint64_t enb                          : 64;
@@ -5613,12 +5512,10 @@ typedef union cvmx_npei_msi_enb1 cvmx_npei_msi_enb1_t;
  *
  * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV2.
  */
-union cvmx_npei_msi_enb2
-{
+union cvmx_npei_msi_enb2 {
 	uint64_t u64;
-	struct cvmx_npei_msi_enb2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_msi_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t enb                          : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV2. */
 #else
 	uint64_t enb                          : 64;
@@ -5638,12 +5535,10 @@ typedef union cvmx_npei_msi_enb2 cvmx_npei_msi_enb2_t;
  *
  * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV3.
  */
-union cvmx_npei_msi_enb3
-{
+union cvmx_npei_msi_enb3 {
 	uint64_t u64;
-	struct cvmx_npei_msi_enb3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_msi_enb3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t enb                          : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV3. */
 #else
 	uint64_t enb                          : 64;
@@ -5663,12 +5558,10 @@ typedef union cvmx_npei_msi_enb3 cvmx_npei_msi_enb3_t;
  *
  * Contains bits [63:0] of the 256 bits oof MSI interrupts.
  */
-union cvmx_npei_msi_rcv0
-{
+union cvmx_npei_msi_rcv0 {
 	uint64_t u64;
-	struct cvmx_npei_msi_rcv0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_msi_rcv0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t intr                         : 64; /**< Bits 63-0 of the 256 bits of MSI interrupt. */
 #else
 	uint64_t intr                         : 64;
@@ -5688,12 +5581,10 @@ typedef union cvmx_npei_msi_rcv0 cvmx_npei_msi_rcv0_t;
  *
  * Contains bits [127:64] of the 256 bits oof MSI interrupts.
  */
-union cvmx_npei_msi_rcv1
-{
+union cvmx_npei_msi_rcv1 {
 	uint64_t u64;
-	struct cvmx_npei_msi_rcv1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_msi_rcv1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t intr                         : 64; /**< Bits 127-64 of the 256 bits of MSI interrupt. */
 #else
 	uint64_t intr                         : 64;
@@ -5713,12 +5604,10 @@ typedef union cvmx_npei_msi_rcv1 cvmx_npei_msi_rcv1_t;
  *
  * Contains bits [191:128] of the 256 bits oof MSI interrupts.
  */
-union cvmx_npei_msi_rcv2
-{
+union cvmx_npei_msi_rcv2 {
 	uint64_t u64;
-	struct cvmx_npei_msi_rcv2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_msi_rcv2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t intr                         : 64; /**< Bits 191-128 of the 256 bits of MSI interrupt. */
 #else
 	uint64_t intr                         : 64;
@@ -5738,12 +5627,10 @@ typedef union cvmx_npei_msi_rcv2 cvmx_npei_msi_rcv2_t;
  *
  * Contains bits [255:192] of the 256 bits oof MSI interrupts.
  */
-union cvmx_npei_msi_rcv3
-{
+union cvmx_npei_msi_rcv3 {
 	uint64_t u64;
-	struct cvmx_npei_msi_rcv3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_msi_rcv3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t intr                         : 64; /**< Bits 255-192 of the 256 bits of MSI interrupt. */
 #else
 	uint64_t intr                         : 64;
@@ -5763,12 +5650,10 @@ typedef union cvmx_npei_msi_rcv3 cvmx_npei_msi_rcv3_t;
  *
  * Used to read the mapping function of the NPEI_PCIE_MSI_RCV to NPEI_MSI_RCV registers.
  */
-union cvmx_npei_msi_rd_map
-{
+union cvmx_npei_msi_rd_map {
 	uint64_t u64;
-	struct cvmx_npei_msi_rd_map_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_msi_rd_map_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t rd_int                       : 8;  /**< The value of the map at the location PREVIOUSLY
                                                          written to the MSI_INT field of this register. */
@@ -5794,12 +5679,10 @@ typedef union cvmx_npei_msi_rd_map cvmx_npei_msi_rd_map_t;
  *
  * Used to clear bits in NPEI_MSI_ENB0. This is a PASS2 register.
  */
-union cvmx_npei_msi_w1c_enb0
-{
+union cvmx_npei_msi_w1c_enb0 {
 	uint64_t u64;
-	struct cvmx_npei_msi_w1c_enb0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_msi_w1c_enb0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
                                                          cooresponding bit in NPEI_MSI_ENB0.
                                                          A read to this address will return 0. */
@@ -5819,12 +5702,10 @@ typedef union cvmx_npei_msi_w1c_enb0 cvmx_npei_msi_w1c_enb0_t;
  *
  * Used to clear bits in NPEI_MSI_ENB1. This is a PASS2 register.
  */
-union cvmx_npei_msi_w1c_enb1
-{
+union cvmx_npei_msi_w1c_enb1 {
 	uint64_t u64;
-	struct cvmx_npei_msi_w1c_enb1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_msi_w1c_enb1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
                                                          cooresponding bit in NPEI_MSI_ENB1.
                                                          A read to this address will return 0. */
@@ -5844,12 +5725,10 @@ typedef union cvmx_npei_msi_w1c_enb1 cvmx_npei_msi_w1c_enb1_t;
  *
  * Used to clear bits in NPEI_MSI_ENB2. This is a PASS2 register.
  */
-union cvmx_npei_msi_w1c_enb2
-{
+union cvmx_npei_msi_w1c_enb2 {
 	uint64_t u64;
-	struct cvmx_npei_msi_w1c_enb2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_msi_w1c_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
                                                          cooresponding bit in NPEI_MSI_ENB2.
                                                          A read to this address will return 0. */
@@ -5869,12 +5748,10 @@ typedef union cvmx_npei_msi_w1c_enb2 cvmx_npei_msi_w1c_enb2_t;
  *
  * Used to clear bits in NPEI_MSI_ENB3. This is a PASS2 register.
  */
-union cvmx_npei_msi_w1c_enb3
-{
+union cvmx_npei_msi_w1c_enb3 {
 	uint64_t u64;
-	struct cvmx_npei_msi_w1c_enb3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_msi_w1c_enb3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
                                                          cooresponding bit in NPEI_MSI_ENB3.
                                                          A read to this address will return 0. */
@@ -5894,12 +5771,10 @@ typedef union cvmx_npei_msi_w1c_enb3 cvmx_npei_msi_w1c_enb3_t;
  *
  * Used to set bits in NPEI_MSI_ENB0. This is a PASS2 register.
  */
-union cvmx_npei_msi_w1s_enb0
-{
+union cvmx_npei_msi_w1s_enb0 {
 	uint64_t u64;
-	struct cvmx_npei_msi_w1s_enb0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_msi_w1s_enb0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
                                                          cooresponding bit in NPEI_MSI_ENB0.
                                                          A read to this address will return 0. */
@@ -5919,12 +5794,10 @@ typedef union cvmx_npei_msi_w1s_enb0 cvmx_npei_msi_w1s_enb0_t;
  *
  * Used to set bits in NPEI_MSI_ENB1. This is a PASS2 register.
  */
-union cvmx_npei_msi_w1s_enb1
-{
+union cvmx_npei_msi_w1s_enb1 {
 	uint64_t u64;
-	struct cvmx_npei_msi_w1s_enb1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_msi_w1s_enb1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
                                                          cooresponding bit in NPEI_MSI_ENB1.
                                                          A read to this address will return 0. */
@@ -5944,12 +5817,10 @@ typedef union cvmx_npei_msi_w1s_enb1 cvmx_npei_msi_w1s_enb1_t;
  *
  * Used to set bits in NPEI_MSI_ENB2. This is a PASS2 register.
  */
-union cvmx_npei_msi_w1s_enb2
-{
+union cvmx_npei_msi_w1s_enb2 {
 	uint64_t u64;
-	struct cvmx_npei_msi_w1s_enb2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_msi_w1s_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
                                                          cooresponding bit in NPEI_MSI_ENB2.
                                                          A read to this address will return 0. */
@@ -5969,12 +5840,10 @@ typedef union cvmx_npei_msi_w1s_enb2 cvmx_npei_msi_w1s_enb2_t;
  *
  * Used to set bits in NPEI_MSI_ENB3. This is a PASS2 register.
  */
-union cvmx_npei_msi_w1s_enb3
-{
+union cvmx_npei_msi_w1s_enb3 {
 	uint64_t u64;
-	struct cvmx_npei_msi_w1s_enb3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_msi_w1s_enb3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
                                                          cooresponding bit in NPEI_MSI_ENB3.
                                                          A read to this address will return 0. */
@@ -5994,12 +5863,10 @@ typedef union cvmx_npei_msi_w1s_enb3 cvmx_npei_msi_w1s_enb3_t;
  *
  * Used to write the mapping function of the NPEI_PCIE_MSI_RCV to NPEI_MSI_RCV registers.
  */
-union cvmx_npei_msi_wr_map
-{
+union cvmx_npei_msi_wr_map {
 	uint64_t u64;
-	struct cvmx_npei_msi_wr_map_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_msi_wr_map_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t ciu_int                      : 8;  /**< Selects which bit in the NPEI_MSI_RCV# (0-255)
                                                          will be set when the value specified in the
@@ -6029,12 +5896,10 @@ typedef union cvmx_npei_msi_wr_map cvmx_npei_msi_wr_map_t;
  * flow from NPEI to PCIE Ports starts. A write to this register will cause the credit counts in the NPEI for the two
  * PCIE ports to be reset to the value in this register.
  */
-union cvmx_npei_pcie_credit_cnt
-{
+union cvmx_npei_pcie_credit_cnt {
 	uint64_t u64;
-	struct cvmx_npei_pcie_credit_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pcie_credit_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t p1_ccnt                      : 8;  /**< Port1 C-TLP FIFO Credits.
                                                          Legal values are 0x25 to 0x80. */
@@ -6070,12 +5935,10 @@ typedef union cvmx_npei_pcie_credit_cnt cvmx_npei_pcie_credit_cnt_t;
  *
  * Register where MSI writes are directed from the PCIe.
  */
-union cvmx_npei_pcie_msi_rcv
-{
+union cvmx_npei_pcie_msi_rcv {
 	uint64_t u64;
-	struct cvmx_npei_pcie_msi_rcv_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pcie_msi_rcv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
                                                          one of the NPEI_MSI_RCV# registers being set.
@@ -6101,12 +5964,10 @@ typedef union cvmx_npei_pcie_msi_rcv cvmx_npei_pcie_msi_rcv_t;
  *
  * Register where MSI writes are directed from the PCIe.
  */
-union cvmx_npei_pcie_msi_rcv_b1
-{
+union cvmx_npei_pcie_msi_rcv_b1 {
 	uint64_t u64;
-	struct cvmx_npei_pcie_msi_rcv_b1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pcie_msi_rcv_b1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
                                                          one of the NPEI_MSI_RCV# registers being set.
@@ -6134,12 +5995,10 @@ typedef union cvmx_npei_pcie_msi_rcv_b1 cvmx_npei_pcie_msi_rcv_b1_t;
  *
  * Register where MSI writes are directed from the PCIe.
  */
-union cvmx_npei_pcie_msi_rcv_b2
-{
+union cvmx_npei_pcie_msi_rcv_b2 {
 	uint64_t u64;
-	struct cvmx_npei_pcie_msi_rcv_b2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pcie_msi_rcv_b2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
                                                          one of the NPEI_MSI_RCV# registers being set.
@@ -6167,12 +6026,10 @@ typedef union cvmx_npei_pcie_msi_rcv_b2 cvmx_npei_pcie_msi_rcv_b2_t;
  *
  * Register where MSI writes are directed from the PCIe.
  */
-union cvmx_npei_pcie_msi_rcv_b3
-{
+union cvmx_npei_pcie_msi_rcv_b3 {
 	uint64_t u64;
-	struct cvmx_npei_pcie_msi_rcv_b3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pcie_msi_rcv_b3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
                                                          one of the NPEI_MSI_RCV# registers being set.
@@ -6200,12 +6057,10 @@ typedef union cvmx_npei_pcie_msi_rcv_b3 cvmx_npei_pcie_msi_rcv_b3_t;
  *
  * The counters for output rings.
  */
-union cvmx_npei_pktx_cnts
-{
+union cvmx_npei_pktx_cnts {
 	uint64_t u64;
-	struct cvmx_npei_pktx_cnts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pktx_cnts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_54_63               : 10;
 	uint64_t timer                        : 22; /**< Timer incremented every 1024 core clocks
                                                          when NPEI_PKTS#_CNTS[CNT] is non zero. Field
@@ -6241,12 +6096,10 @@ typedef union cvmx_npei_pktx_cnts cvmx_npei_pktx_cnts_t;
  *
  * The counters and thresholds for input packets to apply backpressure to processing of the packets.
  */
-union cvmx_npei_pktx_in_bp
-{
+union cvmx_npei_pktx_in_bp {
 	uint64_t u64;
-	struct cvmx_npei_pktx_in_bp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pktx_in_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t wmark                        : 32; /**< When CNT is greater than this threshold no more
                                                          packets will be processed for this ring.
                                                          When writing this field of the NPEI_PKT#_IN_BP
@@ -6277,12 +6130,10 @@ typedef union cvmx_npei_pktx_in_bp cvmx_npei_pktx_in_bp_t;
  *
  * Start of Instruction for input packets.
  */
-union cvmx_npei_pktx_instr_baddr
-{
+union cvmx_npei_pktx_instr_baddr {
 	uint64_t u64;
-	struct cvmx_npei_pktx_instr_baddr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pktx_instr_baddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t addr                         : 61; /**< Base address for Instructions. */
 	uint64_t reserved_0_2                 : 3;
 #else
@@ -6302,12 +6153,10 @@ typedef union cvmx_npei_pktx_instr_baddr cvmx_npei_pktx_instr_baddr_t;
  *
  * The doorbell and base address offset for next read.
  */
-union cvmx_npei_pktx_instr_baoff_dbell
-{
+union cvmx_npei_pktx_instr_baoff_dbell {
 	uint64_t u64;
-	struct cvmx_npei_pktx_instr_baoff_dbell_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pktx_instr_baoff_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t aoff                         : 32; /**< The offset from the NPEI_PKT[0..31]_INSTR_BADDR
                                                          where the next instruction will be read. */
 	uint64_t dbell                        : 32; /**< Instruction doorbell count. Writes to this field
@@ -6331,12 +6180,10 @@ typedef union cvmx_npei_pktx_instr_baoff_dbell cvmx_npei_pktx_instr_baoff_dbell_
  *
  * Fifo field and ring size for Instructions.
  */
-union cvmx_npei_pktx_instr_fifo_rsize
-{
+union cvmx_npei_pktx_instr_fifo_rsize {
 	uint64_t u64;
-	struct cvmx_npei_pktx_instr_fifo_rsize_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pktx_instr_fifo_rsize_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t max                          : 9;  /**< Max Fifo Size. */
 	uint64_t rrp                          : 9;  /**< Fifo read pointer. */
 	uint64_t wrp                          : 9;  /**< Fifo write pointer. */
@@ -6362,12 +6209,10 @@ typedef union cvmx_npei_pktx_instr_fifo_rsize cvmx_npei_pktx_instr_fifo_rsize_t;
  *
  * VAlues used to build input packet header.
  */
-union cvmx_npei_pktx_instr_header
-{
+union cvmx_npei_pktx_instr_header {
 	uint64_t u64;
-	struct cvmx_npei_pktx_instr_header_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pktx_instr_header_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_44_63               : 20;
 	uint64_t pbp                          : 1;  /**< Enable Packet-by-packet mode. */
 	uint64_t reserved_38_42               : 5;
@@ -6414,12 +6259,10 @@ typedef union cvmx_npei_pktx_instr_header cvmx_npei_pktx_instr_header_t;
  *
  * Start of Scatter List for output packet pointers - MUST be 16 byte alligned
  */
-union cvmx_npei_pktx_slist_baddr
-{
+union cvmx_npei_pktx_slist_baddr {
 	uint64_t u64;
-	struct cvmx_npei_pktx_slist_baddr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pktx_slist_baddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t addr                         : 60; /**< Base address for scatter list pointers. */
 	uint64_t reserved_0_3                 : 4;
 #else
@@ -6439,12 +6282,10 @@ typedef union cvmx_npei_pktx_slist_baddr cvmx_npei_pktx_slist_baddr_t;
  *
  * The doorbell and base address offset for next read.
  */
-union cvmx_npei_pktx_slist_baoff_dbell
-{
+union cvmx_npei_pktx_slist_baoff_dbell {
 	uint64_t u64;
-	struct cvmx_npei_pktx_slist_baoff_dbell_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pktx_slist_baoff_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t aoff                         : 32; /**< The offset from the NPEI_PKT[0..31]_SLIST_BADDR
                                                          where the next SList pointer will be read.
                                                          A write of 0xFFFFFFFF to the DBELL field will
@@ -6472,12 +6313,10 @@ typedef union cvmx_npei_pktx_slist_baoff_dbell cvmx_npei_pktx_slist_baoff_dbell_
  *
  * The number of scatter pointer pairs in the scatter list.
  */
-union cvmx_npei_pktx_slist_fifo_rsize
-{
+union cvmx_npei_pktx_slist_fifo_rsize {
 	uint64_t u64;
-	struct cvmx_npei_pktx_slist_fifo_rsize_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pktx_slist_fifo_rsize_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t rsize                        : 32; /**< The number of scatter pointer pairs contained in
                                                          the scatter list ring. */
@@ -6498,12 +6337,10 @@ typedef union cvmx_npei_pktx_slist_fifo_rsize cvmx_npei_pktx_slist_fifo_rsize_t;
  *
  * The packets rings that are interrupting because of Packet Counters.
  */
-union cvmx_npei_pkt_cnt_int
-{
+union cvmx_npei_pkt_cnt_int {
 	uint64_t u64;
-	struct cvmx_npei_pkt_cnt_int_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_cnt_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t port                         : 32; /**< Bit vector cooresponding to ring number is set when
                                                          NPEI_PKT#_CNTS[CNT] is greater
@@ -6525,12 +6362,10 @@ typedef union cvmx_npei_pkt_cnt_int cvmx_npei_pkt_cnt_int_t;
  *
  * Enable for the packets rings that are interrupting because of Packet Counters.
  */
-union cvmx_npei_pkt_cnt_int_enb
-{
+union cvmx_npei_pkt_cnt_int_enb {
 	uint64_t u64;
-	struct cvmx_npei_pkt_cnt_int_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_cnt_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t port                         : 32; /**< Bit vector cooresponding to ring number when set
                                                          allows NPEI_PKT_CNT_INT to generate an interrupt. */
@@ -6551,12 +6386,10 @@ typedef union cvmx_npei_pkt_cnt_int_enb cvmx_npei_pkt_cnt_int_enb_t;
  *
  * The Endian Swap for writing Data Out.
  */
-union cvmx_npei_pkt_data_out_es
-{
+union cvmx_npei_pkt_data_out_es {
 	uint64_t u64;
-	struct cvmx_npei_pkt_data_out_es_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_data_out_es_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t es                           : 64; /**< The endian swap mode for Packet rings 0 through 31.
                                                          Two bits are used per ring (i.e. ring 0 [1:0],
                                                          ring 1 [3:2], ....). */
@@ -6576,12 +6409,10 @@ typedef union cvmx_npei_pkt_data_out_es cvmx_npei_pkt_data_out_es_t;
  *
  * The NS field for the TLP when writing packet data.
  */
-union cvmx_npei_pkt_data_out_ns
-{
+union cvmx_npei_pkt_data_out_ns {
 	uint64_t u64;
-	struct cvmx_npei_pkt_data_out_ns_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_data_out_ns_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t nsr                          : 32; /**< When asserted '1' the vector bit cooresponding
                                                          to the Packet-ring will enable NS in TLP header. */
@@ -6602,12 +6433,10 @@ typedef union cvmx_npei_pkt_data_out_ns cvmx_npei_pkt_data_out_ns_t;
  *
  * The ROR field for the TLP when writing Packet Data.
  */
-union cvmx_npei_pkt_data_out_ror
-{
+union cvmx_npei_pkt_data_out_ror {
 	uint64_t u64;
-	struct cvmx_npei_pkt_data_out_ror_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_data_out_ror_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t ror                          : 32; /**< When asserted '1' the vector bit cooresponding
                                                          to the Packet-ring will enable ROR in TLP header. */
@@ -6628,12 +6457,10 @@ typedef union cvmx_npei_pkt_data_out_ror cvmx_npei_pkt_data_out_ror_t;
  *
  * Used to detemine address and attributes for packet data writes.
  */
-union cvmx_npei_pkt_dpaddr
-{
+union cvmx_npei_pkt_dpaddr {
 	uint64_t u64;
-	struct cvmx_npei_pkt_dpaddr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_dpaddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t dptr                         : 32; /**< When asserted '1' the vector bit cooresponding
                                                          to the Packet-ring will use:
@@ -6661,12 +6488,10 @@ typedef union cvmx_npei_pkt_dpaddr cvmx_npei_pkt_dpaddr_t;
  *
  * Which input rings have backpressure applied.
  */
-union cvmx_npei_pkt_in_bp
-{
+union cvmx_npei_pkt_in_bp {
 	uint64_t u64;
-	struct cvmx_npei_pkt_in_bp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_in_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t bp                           : 32; /**< A packet input  ring that has its count greater
                                                          than its WMARK will have backpressure applied.
@@ -6691,12 +6516,10 @@ typedef union cvmx_npei_pkt_in_bp cvmx_npei_pkt_in_bp_t;
  *
  * Counters for instructions completed on Input rings.
  */
-union cvmx_npei_pkt_in_donex_cnts
-{
+union cvmx_npei_pkt_in_donex_cnts {
 	uint64_t u64;
-	struct cvmx_npei_pkt_in_donex_cnts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_in_donex_cnts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< This field is incrmented by '1' when an instruction
                                                          is completed. This field is incremented as the
@@ -6718,12 +6541,10 @@ typedef union cvmx_npei_pkt_in_donex_cnts cvmx_npei_pkt_in_donex_cnts_t;
  *
  * Keeps track of the number of instructions read into the FIFO and Packets sent to IPD.
  */
-union cvmx_npei_pkt_in_instr_counts
-{
+union cvmx_npei_pkt_in_instr_counts {
 	uint64_t u64;
-	struct cvmx_npei_pkt_in_instr_counts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_in_instr_counts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t wr_cnt                       : 32; /**< Shows the number of packets sent to the IPD. */
 	uint64_t rd_cnt                       : 32; /**< Shows the value of instructions that have had reads
                                                          issued for them.
@@ -6745,12 +6566,10 @@ typedef union cvmx_npei_pkt_in_instr_counts cvmx_npei_pkt_in_instr_counts_t;
  *
  * Assigns Packet Input rings to PCIe ports.
  */
-union cvmx_npei_pkt_in_pcie_port
-{
+union cvmx_npei_pkt_in_pcie_port {
 	uint64_t u64;
-	struct cvmx_npei_pkt_in_pcie_port_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_in_pcie_port_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t pp                           : 64; /**< The PCIe port that the Packet ring number is
                                                          assigned. Two bits are used per ring (i.e. ring 0
                                                          [1:0], ring 1 [3:2], ....). A value of '0 means
@@ -6772,12 +6591,10 @@ typedef union cvmx_npei_pkt_in_pcie_port cvmx_npei_pkt_in_pcie_port_t;
  *
  * Control for reads for gather list and instructions.
  */
-union cvmx_npei_pkt_input_control
-{
+union cvmx_npei_pkt_input_control {
 	uint64_t u64;
-	struct cvmx_npei_pkt_input_control_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_input_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_23_63               : 41;
 	uint64_t pkt_rr                       : 1;  /**< When set '1' the input packet selection will be
                                                          made with a Round Robin arbitration. When '0'
@@ -6827,12 +6644,10 @@ typedef union cvmx_npei_pkt_input_control cvmx_npei_pkt_input_control_t;
  *
  * Enables the instruction fetch for a Packet-ring.
  */
-union cvmx_npei_pkt_instr_enb
-{
+union cvmx_npei_pkt_instr_enb {
 	uint64_t u64;
-	struct cvmx_npei_pkt_instr_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_instr_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t enb                          : 32; /**< When asserted '1' the vector bit cooresponding
                                                          to the Packet-ring is enabled. */
@@ -6853,12 +6668,10 @@ typedef union cvmx_npei_pkt_instr_enb cvmx_npei_pkt_instr_enb_t;
  *
  * The number of instruction allowed to be read at one time.
  */
-union cvmx_npei_pkt_instr_rd_size
-{
+union cvmx_npei_pkt_instr_rd_size {
 	uint64_t u64;
-	struct cvmx_npei_pkt_instr_rd_size_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_instr_rd_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rdsize                       : 64; /**< Number of instructions to be read in one PCIe read
                                                          request for the 4 PKOport - 8 rings. Every two bits
                                                          (i.e. 1:0, 3:2, 5:4..) are assign to the port/ring
@@ -6886,12 +6699,10 @@ typedef union cvmx_npei_pkt_instr_rd_size cvmx_npei_pkt_instr_rd_size_t;
  *
  * Determines if instructions are 64 or 32 byte in size for a Packet-ring.
  */
-union cvmx_npei_pkt_instr_size
-{
+union cvmx_npei_pkt_instr_size {
 	uint64_t u64;
-	struct cvmx_npei_pkt_instr_size_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_instr_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t is_64b                       : 32; /**< When asserted '1' the vector bit cooresponding
                                                          to the Packet-ring is a 64-byte instruction. */
@@ -6915,12 +6726,10 @@ typedef union cvmx_npei_pkt_instr_size cvmx_npei_pkt_instr_size_t;
  *
  * Output packet interrupt levels.
  */
-union cvmx_npei_pkt_int_levels
-{
+union cvmx_npei_pkt_int_levels {
 	uint64_t u64;
-	struct cvmx_npei_pkt_int_levels_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_int_levels_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_54_63               : 10;
 	uint64_t time                         : 22; /**< When NPEI_PKT#_CNTS[TIMER] is greater than this
                                                          value an interrupt is generated. */
@@ -6944,12 +6753,10 @@ typedef union cvmx_npei_pkt_int_levels cvmx_npei_pkt_int_levels_t;
  *
  * Controls using the Info-Pointer to store length and data.
  */
-union cvmx_npei_pkt_iptr
-{
+union cvmx_npei_pkt_iptr {
 	uint64_t u64;
-	struct cvmx_npei_pkt_iptr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_iptr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t iptr                         : 32; /**< When asserted '1' the vector bit cooresponding
                                                          to the Packet-ring will use the Info-Pointer to
@@ -6971,12 +6778,10 @@ typedef union cvmx_npei_pkt_iptr cvmx_npei_pkt_iptr_t;
  *
  * Control the updating of the NPEI_PKT#_CNT register.
  */
-union cvmx_npei_pkt_out_bmode
-{
+union cvmx_npei_pkt_out_bmode {
 	uint64_t u64;
-	struct cvmx_npei_pkt_out_bmode_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_out_bmode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t bmode                        : 32; /**< When asserted '1' the vector bit cooresponding
                                                          to the Packet-ring will have its NPEI_PKT#_CNT
@@ -7000,12 +6805,10 @@ typedef union cvmx_npei_pkt_out_bmode cvmx_npei_pkt_out_bmode_t;
  *
  * Enables the output packet engines.
  */
-union cvmx_npei_pkt_out_enb
-{
+union cvmx_npei_pkt_out_enb {
 	uint64_t u64;
-	struct cvmx_npei_pkt_out_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_out_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t enb                          : 32; /**< When asserted '1' the vector bit cooresponding
                                                          to the Packet-ring is enabled.
@@ -7029,12 +6832,10 @@ typedef union cvmx_npei_pkt_out_enb cvmx_npei_pkt_out_enb_t;
  *
  * Value that when the NPEI_PKT#_SLIST_BAOFF_DBELL[DBELL] value is less then that backpressure for the rings will be applied.
  */
-union cvmx_npei_pkt_output_wmark
-{
+union cvmx_npei_pkt_output_wmark {
 	uint64_t u64;
-	struct cvmx_npei_pkt_output_wmark_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_output_wmark_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t wmark                        : 32; /**< Value when DBELL count drops below backpressure
                                                          for the ring will be applied to the PKO. */
@@ -7055,12 +6856,10 @@ typedef union cvmx_npei_pkt_output_wmark cvmx_npei_pkt_output_wmark_t;
  *
  * Assigns Packet Ports to PCIe ports.
  */
-union cvmx_npei_pkt_pcie_port
-{
+union cvmx_npei_pkt_pcie_port {
 	uint64_t u64;
-	struct cvmx_npei_pkt_pcie_port_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_pcie_port_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t pp                           : 64; /**< The PCIe port that the Packet ring number is
                                                          assigned. Two bits are used per ring (i.e. ring 0
                                                          [1:0], ring 1 [3:2], ....). A value of '0 means
@@ -7082,12 +6881,10 @@ typedef union cvmx_npei_pkt_pcie_port cvmx_npei_pkt_pcie_port_t;
  *
  * Vector bits related to ring-port for ones that are reset.
  */
-union cvmx_npei_pkt_port_in_rst
-{
+union cvmx_npei_pkt_port_in_rst {
 	uint64_t u64;
-	struct cvmx_npei_pkt_port_in_rst_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_port_in_rst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t in_rst                       : 32; /**< When asserted '1' the vector bit cooresponding
                                                          to the inbound Packet-ring is in reset. */
 	uint64_t out_rst                      : 32; /**< When asserted '1' the vector bit cooresponding
@@ -7109,12 +6906,10 @@ typedef union cvmx_npei_pkt_port_in_rst cvmx_npei_pkt_port_in_rst_t;
  *
  * The Endian Swap for Scatter List Read.
  */
-union cvmx_npei_pkt_slist_es
-{
+union cvmx_npei_pkt_slist_es {
 	uint64_t u64;
-	struct cvmx_npei_pkt_slist_es_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_slist_es_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t es                           : 64; /**< The endian swap mode for Packet rings 0 through 31.
                                                          Two bits are used per ring (i.e. ring 0 [1:0],
                                                          ring 1 [3:2], ....). */
@@ -7134,12 +6929,10 @@ typedef union cvmx_npei_pkt_slist_es cvmx_npei_pkt_slist_es_t;
  *
  * The Size of the information and data fields pointed to by Scatter List pointers.
  */
-union cvmx_npei_pkt_slist_id_size
-{
+union cvmx_npei_pkt_slist_id_size {
 	uint64_t u64;
-	struct cvmx_npei_pkt_slist_id_size_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_slist_id_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_23_63               : 41;
 	uint64_t isize                        : 7;  /**< Information size. Legal sizes are 0 to 120. */
 	uint64_t bsize                        : 16; /**< Data size. */
@@ -7161,12 +6954,10 @@ typedef union cvmx_npei_pkt_slist_id_size cvmx_npei_pkt_slist_id_size_t;
  *
  * The NS field for the TLP when fetching Scatter List.
  */
-union cvmx_npei_pkt_slist_ns
-{
+union cvmx_npei_pkt_slist_ns {
 	uint64_t u64;
-	struct cvmx_npei_pkt_slist_ns_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_slist_ns_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t nsr                          : 32; /**< When asserted '1' the vector bit cooresponding
                                                          to the Packet-ring will enable NS in TLP header. */
@@ -7187,12 +6978,10 @@ typedef union cvmx_npei_pkt_slist_ns cvmx_npei_pkt_slist_ns_t;
  *
  * The ROR field for the TLP when fetching Scatter List.
  */
-union cvmx_npei_pkt_slist_ror
-{
+union cvmx_npei_pkt_slist_ror {
 	uint64_t u64;
-	struct cvmx_npei_pkt_slist_ror_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_slist_ror_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t ror                          : 32; /**< When asserted '1' the vector bit cooresponding
                                                          to the Packet-ring will enable ROR in TLP header. */
@@ -7213,12 +7002,10 @@ typedef union cvmx_npei_pkt_slist_ror cvmx_npei_pkt_slist_ror_t;
  *
  * The packets rings that are interrupting because of Packet Timers.
  */
-union cvmx_npei_pkt_time_int
-{
+union cvmx_npei_pkt_time_int {
 	uint64_t u64;
-	struct cvmx_npei_pkt_time_int_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_time_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t port                         : 32; /**< Bit vector cooresponding to ring number is set when
                                                          NPEI_PKT#_CNTS[TIMER] is greater than
@@ -7240,12 +7027,10 @@ typedef union cvmx_npei_pkt_time_int cvmx_npei_pkt_time_int_t;
  *
  * The packets rings that are interrupting because of Packet Timers.
  */
-union cvmx_npei_pkt_time_int_enb
-{
+union cvmx_npei_pkt_time_int_enb {
 	uint64_t u64;
-	struct cvmx_npei_pkt_time_int_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_pkt_time_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t port                         : 32; /**< Bit vector cooresponding to ring number when set
                                                          allows NPEI_PKT_TIME_INT to generate an interrupt. */
@@ -7268,12 +7053,10 @@ typedef union cvmx_npei_pkt_time_int_enb cvmx_npei_pkt_time_int_enb_t;
  * that presently has an interrupt pending. The Field Description below supplies the name of the
  * register that software should read to find out why that intterupt bit is set.
  */
-union cvmx_npei_rsl_int_blocks
-{
+union cvmx_npei_rsl_int_blocks {
 	uint64_t u64;
-	struct cvmx_npei_rsl_int_blocks_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_rsl_int_blocks_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t iob                          : 1;  /**< IOB_INT_SUM */
 	uint64_t lmc1                         : 1;  /**< LMC1_MEM_CFG0 */
@@ -7349,12 +7132,10 @@ typedef union cvmx_npei_rsl_int_blocks cvmx_npei_rsl_int_blocks_t;
  *
  * A general purpose 64 bit register for SW use.
  */
-union cvmx_npei_scratch_1
-{
+union cvmx_npei_scratch_1 {
 	uint64_t u64;
-	struct cvmx_npei_scratch_1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_scratch_1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 64; /**< The value in this register is totaly SW dependent. */
 #else
 	uint64_t data                         : 64;
@@ -7374,12 +7155,10 @@ typedef union cvmx_npei_scratch_1 cvmx_npei_scratch_1_t;
  *
  * State machines in NPEI. For debug.
  */
-union cvmx_npei_state1
-{
+union cvmx_npei_state1 {
 	uint64_t u64;
-	struct cvmx_npei_state1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_state1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t cpl1                         : 12; /**< CPL1 State */
 	uint64_t cpl0                         : 12; /**< CPL0 State */
 	uint64_t arb                          : 1;  /**< ARB State */
@@ -7405,12 +7184,10 @@ typedef union cvmx_npei_state1 cvmx_npei_state1_t;
  *
  * State machines in NPEI. For debug.
  */
-union cvmx_npei_state2
-{
+union cvmx_npei_state2 {
 	uint64_t u64;
-	struct cvmx_npei_state2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_state2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t npei                         : 1;  /**< NPEI State */
 	uint64_t rac                          : 1;  /**< RAC State */
@@ -7442,12 +7219,10 @@ typedef union cvmx_npei_state2 cvmx_npei_state2_t;
  *
  * State machines in NPEI. For debug.
  */
-union cvmx_npei_state3
-{
+union cvmx_npei_state3 {
 	uint64_t u64;
-	struct cvmx_npei_state3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_state3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_56_63               : 8;
 	uint64_t psm1                         : 15; /**< PSM1 State */
 	uint64_t psm0                         : 15; /**< PSM0 State */
@@ -7475,12 +7250,10 @@ typedef union cvmx_npei_state3 cvmx_npei_state3_t;
  *
  * The address to be read when the NPEI_WIN_RD_DATA register is read.
  */
-union cvmx_npei_win_rd_addr
-{
+union cvmx_npei_win_rd_addr {
 	uint64_t u64;
-	struct cvmx_npei_win_rd_addr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_win_rd_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_51_63               : 13;
 	uint64_t ld_cmd                       : 2;  /**< The load command sent wit hthe read.
                                                          0x0 == Load 8-bytes, 0x1 == Load 4-bytes,
@@ -7518,12 +7291,10 @@ typedef union cvmx_npei_win_rd_addr cvmx_npei_win_rd_addr_t;
  * Reading this register causes a window read operation to take place. Address read is taht contained in the NPEI_WIN_RD_ADDR
  * register.
  */
-union cvmx_npei_win_rd_data
-{
+union cvmx_npei_win_rd_data {
 	uint64_t u64;
-	struct cvmx_npei_win_rd_data_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_win_rd_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rd_data                      : 64; /**< The read data. */
 #else
 	uint64_t rd_data                      : 64;
@@ -7548,12 +7319,10 @@ typedef union cvmx_npei_win_rd_data cvmx_npei_win_rd_data_t;
  * Even though address bit [2] can be set, it should always be kept to '0'.
  *
  */
-union cvmx_npei_win_wr_addr
-{
+union cvmx_npei_win_wr_addr {
 	uint64_t u64;
-	struct cvmx_npei_win_wr_addr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_win_wr_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_49_63               : 15;
 	uint64_t iobit                        : 1;  /**< A 1 or 0 can be written here but this will always
                                                          read as '0'. */
@@ -7589,12 +7358,10 @@ typedef union cvmx_npei_win_wr_addr cvmx_npei_win_wr_addr_t;
  * Contains the data to write to the address located in the NPEI_WIN_WR_ADDR Register.
  * Writing the least-significant-byte of this register will cause a write operation to take place.
  */
-union cvmx_npei_win_wr_data
-{
+union cvmx_npei_win_wr_data {
 	uint64_t u64;
-	struct cvmx_npei_win_wr_data_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_win_wr_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t wr_data                      : 64; /**< The data to be written. Whenever the LSB of this
                                                          register is written, the Window Write will take
                                                          place. */
@@ -7616,12 +7383,10 @@ typedef union cvmx_npei_win_wr_data cvmx_npei_win_wr_data_t;
  *
  * Contains the mask for the data in the NPEI_WIN_WR_DATA Register.
  */
-union cvmx_npei_win_wr_mask
-{
+union cvmx_npei_win_wr_mask {
 	uint64_t u64;
-	struct cvmx_npei_win_wr_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_win_wr_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t wr_mask                      : 8;  /**< The data to be written. When a bit is '0'
                                                          the corresponding byte will be written. */
@@ -7649,12 +7414,10 @@ typedef union cvmx_npei_win_wr_mask cvmx_npei_win_wr_mask_t;
  * The value of this register should be set to a minimum of 0x200000 to ensure that a timeout to an RML register
  * occurs on the RML 0xFFFF timer before the timeout for a BAR0 access from the PCIE#.
  */
-union cvmx_npei_window_ctl
-{
+union cvmx_npei_window_ctl {
 	uint64_t u64;
-	struct cvmx_npei_window_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npei_window_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t time                         : 32; /**< Time to wait in core clocks to wait for a
                                                          BAR0 access to completeon the NCB
diff --git a/sys/contrib/octeon-sdk/cvmx-npi-defs.h b/sys/contrib/octeon-sdk/cvmx-npi-defs.h
index f8e18e9..4049973 100644
--- a/sys/contrib/octeon-sdk/cvmx-npi-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-npi-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_NPI_TYPEDEFS_H__
-#define __CVMX_NPI_TYPEDEFS_H__
+#ifndef __CVMX_NPI_DEFS_H__
+#define __CVMX_NPI_DEFS_H__
 
 #define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
 #define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
@@ -1024,12 +1024,10 @@ static inline uint64_t CVMX_NPI_WIN_READ_TO_FUNC(void)
  *
  * The address to start reading Instructions from for Input-0.
  */
-union cvmx_npi_base_addr_inputx
-{
+union cvmx_npi_base_addr_inputx {
 	uint64_t u64;
-	struct cvmx_npi_base_addr_inputx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_base_addr_inputx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t baddr                        : 61; /**< The address to read Instruction from for output 0.
                                                          This address is 8-byte aligned, for this reason
                                                          address bits [2:0] will always be zero. */
@@ -1056,12 +1054,10 @@ typedef union cvmx_npi_base_addr_inputx cvmx_npi_base_addr_inputx_t;
  *
  * The address to start reading Instructions from for Output-0.
  */
-union cvmx_npi_base_addr_outputx
-{
+union cvmx_npi_base_addr_outputx {
 	uint64_t u64;
-	struct cvmx_npi_base_addr_outputx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_base_addr_outputx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t baddr                        : 61; /**< The address to read Instruction from for output 0.
                                                          This address is 8-byte aligned, for this reason
                                                          address bits [2:0] will always be zero. */
@@ -1088,12 +1084,10 @@ typedef union cvmx_npi_base_addr_outputx cvmx_npi_base_addr_outputx_t;
  *
  * Results from BIST runs of NPI's memories.
  */
-union cvmx_npi_bist_status
-{
+union cvmx_npi_bist_status {
 	uint64_t u64;
-	struct cvmx_npi_bist_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t csr_bs                       : 1;  /**< BIST Status for the csr_fifo */
 	uint64_t dif_bs                       : 1;  /**< BIST Status for the dif_fifo */
@@ -1139,9 +1133,8 @@ union cvmx_npi_bist_status
 	uint64_t reserved_20_63               : 44;
 #endif
 	} s;
-	struct cvmx_npi_bist_status_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_bist_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t csr_bs                       : 1;  /**< BIST Status for the csr_fifo */
 	uint64_t dif_bs                       : 1;  /**< BIST Status for the dif_fifo */
@@ -1186,9 +1179,8 @@ union cvmx_npi_bist_status
 	struct cvmx_npi_bist_status_s         cn31xx;
 	struct cvmx_npi_bist_status_s         cn38xx;
 	struct cvmx_npi_bist_status_s         cn38xxp2;
-	struct cvmx_npi_bist_status_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_bist_status_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t csr_bs                       : 1;  /**< BIST Status for the csr_fifo */
 	uint64_t dif_bs                       : 1;  /**< BIST Status for the dif_fifo */
@@ -1244,12 +1236,10 @@ typedef union cvmx_npi_bist_status cvmx_npi_bist_status_t;
  *
  * The size in bytes of the Data Bufffer and Information Buffer for output 0.
  */
-union cvmx_npi_buff_size_outputx
-{
+union cvmx_npi_buff_size_outputx {
 	uint64_t u64;
-	struct cvmx_npi_buff_size_outputx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_buff_size_outputx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_23_63               : 41;
 	uint64_t isize                        : 7;  /**< The number of bytes to move to the Info-Pointer
                                                          from the front of the packet.
@@ -1279,12 +1269,10 @@ typedef union cvmx_npi_buff_size_outputx cvmx_npi_buff_size_outputx_t;
  *
  * PCI Compensation Control
  */
-union cvmx_npi_comp_ctl
-{
+union cvmx_npi_comp_ctl {
 	uint64_t u64;
-	struct cvmx_npi_comp_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_comp_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t pctl                         : 5;  /**< Bypass value for PCTL */
 	uint64_t nctl                         : 5;  /**< Bypass value for NCTL */
@@ -1310,12 +1298,10 @@ typedef union cvmx_npi_comp_ctl cvmx_npi_comp_ctl_t;
  * To ensure that a write has completed the user must read the register before
  * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
  */
-union cvmx_npi_ctl_status
-{
+union cvmx_npi_ctl_status {
 	uint64_t u64;
-	struct cvmx_npi_ctl_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_63_63               : 1;
 	uint64_t chip_rev                     : 8;  /**< The revision of the N3. */
 	uint64_t dis_pniw                     : 1;  /**< When asserted '1' access from the PNI Window
@@ -1395,9 +1381,8 @@ union cvmx_npi_ctl_status
 	uint64_t reserved_63_63               : 1;
 #endif
 	} s;
-	struct cvmx_npi_ctl_status_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_ctl_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_63_63               : 1;
 	uint64_t chip_rev                     : 8;  /**< The revision of the N3. */
 	uint64_t dis_pniw                     : 1;  /**< When asserted '1' access from the PNI Window
@@ -1447,9 +1432,8 @@ union cvmx_npi_ctl_status
 	uint64_t reserved_63_63               : 1;
 #endif
 	} cn30xx;
-	struct cvmx_npi_ctl_status_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_ctl_status_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_63_63               : 1;
 	uint64_t chip_rev                     : 8;  /**< The revision of the N3.
                                                          0 => pass1.x, 1 => 2.0 */
@@ -1527,12 +1511,10 @@ typedef union cvmx_npi_ctl_status cvmx_npi_ctl_status_t;
  *
  * Contains the debug select value in last written to the RSLs.
  */
-union cvmx_npi_dbg_select
-{
+union cvmx_npi_dbg_select {
 	uint64_t u64;
-	struct cvmx_npi_dbg_select_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_dbg_select_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t dbg_sel                      : 16; /**< When this register is written its value is sent to
                                                          all RSLs. */
@@ -1558,12 +1540,10 @@ typedef union cvmx_npi_dbg_select cvmx_npi_dbg_select_t;
  *
  * Controls operation of the DMA IN/OUT of the NPI.
  */
-union cvmx_npi_dma_control
-{
+union cvmx_npi_dma_control {
 	uint64_t u64;
-	struct cvmx_npi_dma_control_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_dma_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t b0_lend                      : 1;  /**< When set '1' and the NPI is in the mode to write
                                                          0 to L2C memory when a DMA is done, the address
@@ -1639,12 +1619,10 @@ typedef union cvmx_npi_dma_control cvmx_npi_dma_control_t;
  *
  * Values for determing the number of instructions for High Priority DMA in the NPI.
  */
-union cvmx_npi_dma_highp_counts
-{
+union cvmx_npi_dma_highp_counts {
 	uint64_t u64;
-	struct cvmx_npi_dma_highp_counts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_dma_highp_counts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_39_63               : 25;
 	uint64_t fcnt                         : 7;  /**< Number of words in the Instruction FIFO. */
 	uint64_t dbell                        : 32; /**< Number of available words of Instructions to read. */
@@ -1671,12 +1649,10 @@ typedef union cvmx_npi_dma_highp_counts cvmx_npi_dma_highp_counts_t;
  *
  * Place NPI will read the next Ichunk data from. This is valid when state is 0
  */
-union cvmx_npi_dma_highp_naddr
-{
+union cvmx_npi_dma_highp_naddr {
 	uint64_t u64;
-	struct cvmx_npi_dma_highp_naddr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_dma_highp_naddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t state                        : 4;  /**< The DMA instruction engine state vector.
                                                          Typical value is 0 (IDLE). */
@@ -1705,12 +1681,10 @@ typedef union cvmx_npi_dma_highp_naddr cvmx_npi_dma_highp_naddr_t;
  *
  * Values for determing the number of instructions for Low Priority DMA in the NPI.
  */
-union cvmx_npi_dma_lowp_counts
-{
+union cvmx_npi_dma_lowp_counts {
 	uint64_t u64;
-	struct cvmx_npi_dma_lowp_counts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_dma_lowp_counts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_39_63               : 25;
 	uint64_t fcnt                         : 7;  /**< Number of words in the Instruction FIFO. */
 	uint64_t dbell                        : 32; /**< Number of available words of Instructions to read. */
@@ -1737,12 +1711,10 @@ typedef union cvmx_npi_dma_lowp_counts cvmx_npi_dma_lowp_counts_t;
  *
  * Place NPI will read the next Ichunk data from. This is valid when state is 0
  */
-union cvmx_npi_dma_lowp_naddr
-{
+union cvmx_npi_dma_lowp_naddr {
 	uint64_t u64;
-	struct cvmx_npi_dma_lowp_naddr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_dma_lowp_naddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t state                        : 4;  /**< The DMA instruction engine state vector.
                                                          Typical value is 0 (IDLE). */
@@ -1771,12 +1743,10 @@ typedef union cvmx_npi_dma_lowp_naddr cvmx_npi_dma_lowp_naddr_t;
  *
  * The door bell register for the high priority DMA queue.
  */
-union cvmx_npi_highp_dbell
-{
+union cvmx_npi_highp_dbell {
 	uint64_t u64;
-	struct cvmx_npi_highp_dbell_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_highp_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t dbell                        : 16; /**< The value written to this register is added to the
                                                          number of 8byte words to be read and processes for
@@ -1803,12 +1773,10 @@ typedef union cvmx_npi_highp_dbell cvmx_npi_highp_dbell_t;
  *
  * The address to start reading Instructions from for HIGHP.
  */
-union cvmx_npi_highp_ibuff_saddr
-{
+union cvmx_npi_highp_ibuff_saddr {
 	uint64_t u64;
-	struct cvmx_npi_highp_ibuff_saddr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_highp_ibuff_saddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t saddr                        : 36; /**< The starting address to read the first instruction. */
 #else
@@ -1833,12 +1801,10 @@ typedef union cvmx_npi_highp_ibuff_saddr cvmx_npi_highp_ibuff_saddr_t;
  *
  * Control for reads for gather list and instructions.
  */
-union cvmx_npi_input_control
-{
+union cvmx_npi_input_control {
 	uint64_t u64;
-	struct cvmx_npi_input_control_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_input_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_23_63               : 41;
 	uint64_t pkt_rr                       : 1;  /**< When set '1' the input packet selection will be
                                                          made with a Round Robin arbitration. When '0'
@@ -1877,9 +1843,8 @@ union cvmx_npi_input_control
 	uint64_t reserved_23_63               : 41;
 #endif
 	} s;
-	struct cvmx_npi_input_control_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_input_control_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_22_63               : 42;
 	uint64_t pbp_dhi                      : 13; /**< Field when in [PBP] is set to be used in
                                                          calculating a DPTR. */
@@ -1928,12 +1893,10 @@ typedef union cvmx_npi_input_control cvmx_npi_input_control_t;
  *
  * Used to enable the various interrupting conditions of NPI
  */
-union cvmx_npi_int_enb
-{
+union cvmx_npi_int_enb {
 	uint64_t u64;
-	struct cvmx_npi_int_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_62_63               : 2;
 	uint64_t q1_a_f                       : 1;  /**< Enables NPI_INT_SUM[Q1_A_F] to generate an
                                                          interrupt. */
@@ -2125,9 +2088,8 @@ union cvmx_npi_int_enb
 	uint64_t reserved_62_63               : 2;
 #endif
 	} s;
-	struct cvmx_npi_int_enb_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_int_enb_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_62_63               : 2;
 	uint64_t q1_a_f                       : 1;  /**< Enables NPI_INT_SUM[Q1_A_F] to generate an
                                                          interrupt. */
@@ -2256,9 +2218,8 @@ union cvmx_npi_int_enb
 	uint64_t reserved_62_63               : 2;
 #endif
 	} cn30xx;
-	struct cvmx_npi_int_enb_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_int_enb_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_62_63               : 2;
 	uint64_t q1_a_f                       : 1;  /**< Enables NPI_INT_SUM[Q1_A_F] to generate an
                                                          interrupt. */
@@ -2415,9 +2376,8 @@ union cvmx_npi_int_enb
 #endif
 	} cn31xx;
 	struct cvmx_npi_int_enb_s             cn38xx;
-	struct cvmx_npi_int_enb_cn38xxp2
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_int_enb_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_42_63               : 22;
 	uint64_t iobdma                       : 1;  /**< Enables NPI_INT_SUM[IOBDMA] to generate an
                                                          interrupt. */
@@ -2562,12 +2522,10 @@ typedef union cvmx_npi_int_enb cvmx_npi_int_enb_t;
  *
  * Set when an interrupt condition occurs, write '1' to clear.
  */
-union cvmx_npi_int_sum
-{
+union cvmx_npi_int_sum {
 	uint64_t u64;
-	struct cvmx_npi_int_sum_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_62_63               : 2;
 	uint64_t q1_a_f                       : 1;  /**< Attempted to add when Queue-1 FIFO is full.
                                                          PASS3 Field. */
@@ -2759,9 +2717,8 @@ union cvmx_npi_int_sum
 	uint64_t reserved_62_63               : 2;
 #endif
 	} s;
-	struct cvmx_npi_int_sum_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_int_sum_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_62_63               : 2;
 	uint64_t q1_a_f                       : 1;  /**< Attempted to add when Queue-1 FIFO is full. */
 	uint64_t q1_s_e                       : 1;  /**< Attempted to subtract when Queue-1 FIFO is empty. */
@@ -2870,9 +2827,8 @@ union cvmx_npi_int_sum
 	uint64_t reserved_62_63               : 2;
 #endif
 	} cn30xx;
-	struct cvmx_npi_int_sum_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_int_sum_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_62_63               : 2;
 	uint64_t q1_a_f                       : 1;  /**< Attempted to add when Queue-1 FIFO is full. */
 	uint64_t q1_s_e                       : 1;  /**< Attempted to subtract when Queue-1 FIFO is empty. */
@@ -3009,9 +2965,8 @@ union cvmx_npi_int_sum
 #endif
 	} cn31xx;
 	struct cvmx_npi_int_sum_s             cn38xx;
-	struct cvmx_npi_int_sum_cn38xxp2
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_int_sum_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_42_63               : 22;
 	uint64_t iobdma                       : 1;  /**< Requested IOBDMA read size exceeded 128 words. */
 	uint64_t p_dperr                      : 1;  /**< If a parity error occured on data written to L2C
@@ -3156,12 +3111,10 @@ typedef union cvmx_npi_int_sum cvmx_npi_int_sum_t;
  *
  * The door bell register for the low priority DMA queue.
  */
-union cvmx_npi_lowp_dbell
-{
+union cvmx_npi_lowp_dbell {
 	uint64_t u64;
-	struct cvmx_npi_lowp_dbell_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_lowp_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t dbell                        : 16; /**< The value written to this register is added to the
                                                          number of 8byte words to be read and processes for
@@ -3188,12 +3141,10 @@ typedef union cvmx_npi_lowp_dbell cvmx_npi_lowp_dbell_t;
  *
  * The address to start reading Instructions from for LOWP.
  */
-union cvmx_npi_lowp_ibuff_saddr
-{
+union cvmx_npi_lowp_ibuff_saddr {
 	uint64_t u64;
-	struct cvmx_npi_lowp_ibuff_saddr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_lowp_ibuff_saddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t saddr                        : 36; /**< The starting address to read the first instruction. */
 #else
@@ -3221,12 +3172,10 @@ typedef union cvmx_npi_lowp_ibuff_saddr cvmx_npi_lowp_ibuff_saddr_t;
  * To ensure that a write has completed the user must read the register before
  * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
  */
-union cvmx_npi_mem_access_subidx
-{
+union cvmx_npi_mem_access_subidx {
 	uint64_t u64;
-	struct cvmx_npi_mem_access_subidx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_mem_access_subidx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_38_63               : 26;
 	uint64_t shortl                       : 1;  /**< Generate CMD-6 on PCI(x) when '1'.
                                                          Loads from the cores to the corresponding subid
@@ -3261,9 +3210,8 @@ union cvmx_npi_mem_access_subidx
 #endif
 	} s;
 	struct cvmx_npi_mem_access_subidx_s   cn30xx;
-	struct cvmx_npi_mem_access_subidx_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_mem_access_subidx_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t esr                          : 2;  /**< Endian-Swap on read. */
 	uint64_t esw                          : 2;  /**< Endian-Swap on write. */
@@ -3298,12 +3246,10 @@ typedef union cvmx_npi_mem_access_subidx cvmx_npi_mem_access_subidx_t;
  *
  * A bit is set in this register relative to the vector received during a MSI. And cleared by a W1 to the register.
  */
-union cvmx_npi_msi_rcv
-{
+union cvmx_npi_msi_rcv {
 	uint64_t u64;
-	struct cvmx_npi_msi_rcv_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_msi_rcv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t int_vec                      : 64; /**< Refer to PCI_MSI_RCV */
 #else
 	uint64_t int_vec                      : 64;
@@ -3326,12 +3272,10 @@ typedef union cvmx_npi_msi_rcv cvmx_npi_msi_rcv_t;
  *
  * The size of the Buffer/Info Pointer Pair ring for Output-0.
  */
-union cvmx_npi_num_desc_outputx
-{
+union cvmx_npi_num_desc_outputx {
 	uint64_t u64;
-	struct cvmx_npi_num_desc_outputx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_num_desc_outputx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t size                         : 32; /**< The size of the Buffer/Info Pointer Pair ring. */
 #else
@@ -3356,12 +3300,10 @@ typedef union cvmx_npi_num_desc_outputx cvmx_npi_num_desc_outputx_t;
  *
  * The address to start reading Instructions from for Output-3.
  */
-union cvmx_npi_output_control
-{
+union cvmx_npi_output_control {
 	uint64_t u64;
-	struct cvmx_npi_output_control_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_output_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_49_63               : 15;
 	uint64_t pkt_rr                       : 1;  /**< When set '1' the output packet selection will be
                                                          made with a Round Robin arbitration. When '0'
@@ -3487,9 +3429,8 @@ union cvmx_npi_output_control
 	uint64_t reserved_49_63               : 15;
 #endif
 	} s;
-	struct cvmx_npi_output_control_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_output_control_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_45_63               : 19;
 	uint64_t p0_bmode                     : 1;  /**< When set '1' PCI_PKTS_SENT0 register will be
                                                          updated with the number of bytes in the packet
@@ -3531,9 +3472,8 @@ union cvmx_npi_output_control
 	uint64_t reserved_45_63               : 19;
 #endif
 	} cn30xx;
-	struct cvmx_npi_output_control_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_output_control_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_46_63               : 18;
 	uint64_t p1_bmode                     : 1;  /**< When set '1' PCI_PKTS_SENT1 register will be
                                                          updated with the number of bytes in the packet
@@ -3604,9 +3544,8 @@ union cvmx_npi_output_control
 #endif
 	} cn31xx;
 	struct cvmx_npi_output_control_s      cn38xx;
-	struct cvmx_npi_output_control_cn38xxp2
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_output_control_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t p3_bmode                     : 1;  /**< When set '1' PCI_PKTS_SENT3 register will be
                                                          updated with the number of bytes in the packet
@@ -3726,9 +3665,8 @@ union cvmx_npi_output_control
 	uint64_t reserved_48_63               : 16;
 #endif
 	} cn38xxp2;
-	struct cvmx_npi_output_control_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_output_control_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_49_63               : 15;
 	uint64_t pkt_rr                       : 1;  /**< When set '1' the output packet selection will be
                                                          made with a Round Robin arbitration. When '0'
@@ -3818,12 +3756,10 @@ typedef union cvmx_npi_output_control cvmx_npi_output_control_t;
  *
  * Contains the next address to read for Port's-0 Data/Buffer Pair.
  */
-union cvmx_npi_px_dbpair_addr
-{
+union cvmx_npi_px_dbpair_addr {
 	uint64_t u64;
-	struct cvmx_npi_px_dbpair_addr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_px_dbpair_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_63_63               : 1;
 	uint64_t state                        : 2;  /**< POS state machine vector. Used to tell when NADDR
                                                          is valid (when STATE == 0). */
@@ -3852,12 +3788,10 @@ typedef union cvmx_npi_px_dbpair_addr cvmx_npi_px_dbpair_addr_t;
  *
  * Contains the next address to read for Port's-0 Instructions.
  */
-union cvmx_npi_px_instr_addr
-{
+union cvmx_npi_px_instr_addr {
 	uint64_t u64;
-	struct cvmx_npi_px_instr_addr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_px_instr_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t state                        : 3;  /**< Gather engine state vector. Used to tell when
                                                          NADDR is valid (when STATE == 0). */
 	uint64_t naddr                        : 61; /**< Bits [63:3] of the next Instruction to read.
@@ -3884,12 +3818,10 @@ typedef union cvmx_npi_px_instr_addr cvmx_npi_px_instr_addr_t;
  *
  * Used to determine the number of instruction in the NPI and to be fetched for Input-Packets.
  */
-union cvmx_npi_px_instr_cnts
-{
+union cvmx_npi_px_instr_cnts {
 	uint64_t u64;
-	struct cvmx_npi_px_instr_cnts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_px_instr_cnts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_38_63               : 26;
 	uint64_t fcnt                         : 6;  /**< Number entries in the Instruction FIFO. */
 	uint64_t avail                        : 32; /**< Doorbell count to be read. */
@@ -3916,12 +3848,10 @@ typedef union cvmx_npi_px_instr_cnts cvmx_npi_px_instr_cnts_t;
  *
  * Used to determine the number of instruction in the NPI and to be fetched for Output-Packets.
  */
-union cvmx_npi_px_pair_cnts
-{
+union cvmx_npi_px_pair_cnts {
 	uint64_t u64;
-	struct cvmx_npi_px_pair_cnts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_px_pair_cnts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_37_63               : 27;
 	uint64_t fcnt                         : 5;  /**< 16 - number entries in the D/I Pair FIFO. */
 	uint64_t avail                        : 32; /**< Doorbell count to be read. */
@@ -3948,12 +3878,10 @@ typedef union cvmx_npi_px_pair_cnts cvmx_npi_px_pair_cnts_t;
  *
  * Control the number of words the NPI will attempt to read / write to/from the PCI.
  */
-union cvmx_npi_pci_burst_size
-{
+union cvmx_npi_pci_burst_size {
 	uint64_t u64;
-	struct cvmx_npi_pci_burst_size_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_pci_burst_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t wr_brst                      : 7;  /**< The number of 8B words to write to PCI in any one
                                                          write operation. A zero is equal to 128. This
@@ -3991,12 +3919,10 @@ typedef union cvmx_npi_pci_burst_size cvmx_npi_pci_burst_size_t;
  * only be written when PRST# is asserted.  NPI_PCI_INT_ARB_CFG[EN] should
  * only be set when Octane is a host.
  */
-union cvmx_npi_pci_int_arb_cfg
-{
+union cvmx_npi_pci_int_arb_cfg {
 	uint64_t u64;
-	struct cvmx_npi_pci_int_arb_cfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_pci_int_arb_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t hostmode                     : 1;  /**< PCI Host Mode Pin (sampled for use by software).
                                                          This bit reflects the sampled PCI_HOSTMODE pin.
@@ -4066,9 +3992,8 @@ union cvmx_npi_pci_int_arb_cfg
 	uint64_t reserved_13_63               : 51;
 #endif
 	} s;
-	struct cvmx_npi_pci_int_arb_cfg_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_pci_int_arb_cfg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t en                           : 1;  /**< Internal arbiter enable. */
 	uint64_t park_mod                     : 1;  /**< Bus park mode. 0=park on last, 1=park on device. */
@@ -4101,12 +4026,10 @@ typedef union cvmx_npi_pci_int_arb_cfg cvmx_npi_pci_int_arb_cfg_t;
  * Also any previously issued reads/writes to PCI memory space, still stored in the outbound
  * FIFO will use the value of this register after it has been updated.
  */
-union cvmx_npi_pci_read_cmd
-{
+union cvmx_npi_pci_read_cmd {
 	uint64_t u64;
-	struct cvmx_npi_pci_read_cmd_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_pci_read_cmd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t cmd_size                     : 11; /**< Number bytes to be read is equal to or exceeds this
                                                          size will cause the PCI in PCI mode to use a
@@ -4135,12 +4058,10 @@ typedef union cvmx_npi_pci_read_cmd cvmx_npi_pci_read_cmd_t;
  *
  * Contains bits [62:42] of the Instruction Header for port 32.
  */
-union cvmx_npi_port32_instr_hdr
-{
+union cvmx_npi_port32_instr_hdr {
 	uint64_t u64;
-	struct cvmx_npi_port32_instr_hdr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_port32_instr_hdr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_44_63               : 20;
 	uint64_t pbp                          : 1;  /**< Enable Packet-by-packet mode. */
 	uint64_t rsv_f                        : 5;  /**< Reserved */
@@ -4193,12 +4114,10 @@ typedef union cvmx_npi_port32_instr_hdr cvmx_npi_port32_instr_hdr_t;
  *
  * Contains bits [62:42] of the Instruction Header for port 33.
  */
-union cvmx_npi_port33_instr_hdr
-{
+union cvmx_npi_port33_instr_hdr {
 	uint64_t u64;
-	struct cvmx_npi_port33_instr_hdr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_port33_instr_hdr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_44_63               : 20;
 	uint64_t pbp                          : 1;  /**< Enable Packet-by-packet mode. */
 	uint64_t rsv_f                        : 5;  /**< Reserved */
@@ -4250,12 +4169,10 @@ typedef union cvmx_npi_port33_instr_hdr cvmx_npi_port33_instr_hdr_t;
  *
  * Contains bits [62:42] of the Instruction Header for port 34. Added for PASS-2.
  */
-union cvmx_npi_port34_instr_hdr
-{
+union cvmx_npi_port34_instr_hdr {
 	uint64_t u64;
-	struct cvmx_npi_port34_instr_hdr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_port34_instr_hdr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_44_63               : 20;
 	uint64_t pbp                          : 1;  /**< Enable Packet-by-packet mode. */
 	uint64_t rsv_f                        : 5;  /**< Reserved */
@@ -4305,12 +4222,10 @@ typedef union cvmx_npi_port34_instr_hdr cvmx_npi_port34_instr_hdr_t;
  *
  * Contains bits [62:42] of the Instruction Header for port 35. Added for PASS-2.
  */
-union cvmx_npi_port35_instr_hdr
-{
+union cvmx_npi_port35_instr_hdr {
 	uint64_t u64;
-	struct cvmx_npi_port35_instr_hdr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_port35_instr_hdr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_44_63               : 20;
 	uint64_t pbp                          : 1;  /**< Enable Packet-by-packet mode. */
 	uint64_t rsv_f                        : 5;  /**< Reserved */
@@ -4360,12 +4275,10 @@ typedef union cvmx_npi_port35_instr_hdr cvmx_npi_port35_instr_hdr_t;
  *
  * Enables Port Level Backpressure
  */
-union cvmx_npi_port_bp_control
-{
+union cvmx_npi_port_bp_control {
 	uint64_t u64;
-	struct cvmx_npi_port_bp_control_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_port_bp_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t bp_on                        : 4;  /**< Port 35-32 port level backpressure applied. */
 	uint64_t enb                          : 4;  /**< Enables port level backpressure from the IPD. */
@@ -4394,12 +4307,10 @@ typedef union cvmx_npi_port_bp_control cvmx_npi_port_bp_control_t;
  * that presently has an interrupt pending. The Field Description below supplies the name of the
  * register that software should read to find out why that intterupt bit is set.
  */
-union cvmx_npi_rsl_int_blocks
-{
+union cvmx_npi_rsl_int_blocks {
 	uint64_t u64;
-	struct cvmx_npi_rsl_int_blocks_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_rsl_int_blocks_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t rint_31                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
 	uint64_t iob                          : 1;  /**< IOB_INT_SUM */
@@ -4465,9 +4376,8 @@ union cvmx_npi_rsl_int_blocks
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
-	struct cvmx_npi_rsl_int_blocks_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_rsl_int_blocks_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t rint_31                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
 	uint64_t iob                          : 1;  /**< IOB_INT_SUM */
@@ -4538,9 +4448,8 @@ union cvmx_npi_rsl_int_blocks
 #endif
 	} cn30xx;
 	struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
-	struct cvmx_npi_rsl_int_blocks_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_rsl_int_blocks_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t rint_31                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
 	uint64_t iob                          : 1;  /**< IOB_INT_SUM */
@@ -4611,9 +4520,8 @@ union cvmx_npi_rsl_int_blocks
 #endif
 	} cn38xx;
 	struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
-	struct cvmx_npi_rsl_int_blocks_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_rsl_int_blocks_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t iob                          : 1;  /**< IOB_INT_SUM */
 	uint64_t lmc1                         : 1;  /**< Always reads as zero */
@@ -4687,12 +4595,10 @@ typedef union cvmx_npi_rsl_int_blocks cvmx_npi_rsl_int_blocks_t;
  *
  * The size (in instructions) of Instruction Queue-0.
  */
-union cvmx_npi_size_inputx
-{
+union cvmx_npi_size_inputx {
 	uint64_t u64;
-	struct cvmx_npi_size_inputx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_size_inputx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t size                         : 32; /**< The size of the Instruction Queue used by Octane.
                                                          The value [SIZE] is in Instructions.
@@ -4719,12 +4625,10 @@ typedef union cvmx_npi_size_inputx cvmx_npi_size_inputx_t;
  *
  * Number of core clocks to wait before timing out on a WINDOW-READ to the NCB.
  */
-union cvmx_npi_win_read_to
-{
+union cvmx_npi_win_read_to {
 	uint64_t u64;
-	struct cvmx_npi_win_read_to_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_npi_win_read_to_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t time                         : 32; /**< Time to wait in core clocks. A value of 0 will
                                                          cause no timeouts. */
diff --git a/sys/contrib/octeon-sdk/cvmx-npi.h b/sys/contrib/octeon-sdk/cvmx-npi.h
index 5c90717..09621c0 100644
--- a/sys/contrib/octeon-sdk/cvmx-npi.h
+++ b/sys/contrib/octeon-sdk/cvmx-npi.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * PCI / PCIe packet engine related structures.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_NPI_H__
@@ -66,7 +66,7 @@ typedef union
     uint64_t u64;
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t            r :     1;      /**< Packet is RAW */
         uint64_t            g :     1;      /**< Gather list is used */
         uint64_t            dlengsz : 14;   /**< Data length / Gather list size */
@@ -98,7 +98,7 @@ typedef union
     uint64_t dptr0;
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    es      : 2;    /**< Endian swap mode */
         uint64_t    ns      : 1;    /**< No snoop */
         uint64_t    ro      : 1;    /**< Relaxed ordering */
@@ -112,7 +112,7 @@ typedef union
     } dptr1;
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    pm      : 2;    /**< Parse mode */
         uint64_t    sl      : 7;    /**< Skip length */
         uint64_t    addr    : 55;   /**< PCI/PCIe address */
@@ -124,7 +124,7 @@ typedef union
     } dptr2;
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    es      : 2;    /**< Endian swap mode */
         uint64_t    ns      : 1;    /**< No snoop */
         uint64_t    ro      : 1;    /**< Relaxed ordering */
diff --git a/sys/contrib/octeon-sdk/cvmx-packet.h b/sys/contrib/octeon-sdk/cvmx-packet.h
index 8dbf554..94dd036 100644
--- a/sys/contrib/octeon-sdk/cvmx-packet.h
+++ b/sys/contrib/octeon-sdk/cvmx-packet.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -43,7 +43,7 @@
  *
  * Packet buffer defines.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-pci-defs.h b/sys/contrib/octeon-sdk/cvmx-pci-defs.h
index df38d8d..28be954 100644
--- a/sys/contrib/octeon-sdk/cvmx-pci-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-pci-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_PCI_TYPEDEFS_H__
-#define __CVMX_PCI_TYPEDEFS_H__
+#ifndef __CVMX_PCI_DEFS_H__
+#define __CVMX_PCI_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCI_BAR1_INDEXX(unsigned long offset)
@@ -776,12 +776,10 @@ static inline uint64_t CVMX_PCI_WIN_WR_MASK_FUNC(void)
  * Contains address index and control bits for access to memory ranges of Bar-1,
  * when PCI supplied address-bits [26:22] == X.
  */
-union cvmx_pci_bar1_indexx
-{
+union cvmx_pci_bar1_indexx {
 	uint32_t u32;
-	struct cvmx_pci_bar1_indexx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_bar1_indexx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_18_31               : 14;
 	uint32_t addr_idx                     : 14; /**< Address bits [35:22] sent to L2C */
 	uint32_t ca                           : 1;  /**< Set '1' when access is not to be cached in L2. */
@@ -812,12 +810,10 @@ typedef union cvmx_pci_bar1_indexx cvmx_pci_bar1_indexx_t;
  *
  * Contains the bist results for the PNI memories.
  */
-union cvmx_pci_bist_reg
-{
+union cvmx_pci_bist_reg {
 	uint64_t u64;
-	struct cvmx_pci_bist_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_bist_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t rsp_bs                       : 1;  /**< Bist Status For b12_rsp_fifo_bist
                                                          The value of this register is available 100,000
@@ -900,12 +896,10 @@ typedef union cvmx_pci_bist_reg cvmx_pci_bist_reg_t;
  *
  * This register contains the first 32-bits of the PCI config space registers
  */
-union cvmx_pci_cfg00
-{
+union cvmx_pci_cfg00 {
 	uint32_t u32;
-	struct cvmx_pci_cfg00_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg00_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t devid                        : 16; /**< This is the device ID for OCTEON (90nm shhrink) */
 	uint32_t vendid                       : 16; /**< This is the Cavium's vendor ID */
 #else
@@ -929,12 +923,10 @@ typedef union cvmx_pci_cfg00 cvmx_pci_cfg00_t;
  * PCI_CFG01 = Second 32-bits of PCI config space (Command/Status Register)
  *
  */
-union cvmx_pci_cfg01
-{
+union cvmx_pci_cfg01 {
 	uint32_t u32;
-	struct cvmx_pci_cfg01_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg01_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dpe                          : 1;  /**< Detected Parity Error */
 	uint32_t sse                          : 1;  /**< Signaled System Error */
 	uint32_t rma                          : 1;  /**< Received Master Abort */
@@ -1016,12 +1008,10 @@ typedef union cvmx_pci_cfg01 cvmx_pci_cfg01_t;
  * PCI_CFG02 = Third 32-bits of PCI config space (Class Code / Revision ID)
  *
  */
-union cvmx_pci_cfg02
-{
+union cvmx_pci_cfg02 {
 	uint32_t u32;
-	struct cvmx_pci_cfg02_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg02_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t cc                           : 24; /**< Class Code (Processor/MIPS)
                                                          (was 0x100000 in pass 1 and pass 2) */
 	uint32_t rid                          : 8;  /**< Revision ID
@@ -1047,12 +1037,10 @@ typedef union cvmx_pci_cfg02 cvmx_pci_cfg02_t;
  * PCI_CFG03 = Fourth 32-bits of PCI config space (BIST, HEADER Type, Latency timer, line size)
  *
  */
-union cvmx_pci_cfg03
-{
+union cvmx_pci_cfg03 {
 	uint32_t u32;
-	struct cvmx_pci_cfg03_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg03_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t bcap                         : 1;  /**< BIST Capable */
 	uint32_t brb                          : 1;  /**< BIST Request/busy bit
                                                          Note: OCTEON does not support PCI BIST, therefore
@@ -1096,12 +1084,10 @@ typedef union cvmx_pci_cfg03 cvmx_pci_cfg03_t;
  *       [11:4]:  RAZ (to imply 4KB space)
  *       [31:12]: RW (User may define base address)
  */
-union cvmx_pci_cfg04
-{
+union cvmx_pci_cfg04 {
 	uint32_t u32;
-	struct cvmx_pci_cfg04_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg04_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t lbase                        : 20; /**< Base Address[31:12]
                                                          Base Address[30:12] read as zero if
                                                          PCI_CTL_STATUS_2[BB0] is set (in pass 3+) */
@@ -1133,12 +1119,10 @@ typedef union cvmx_pci_cfg04 cvmx_pci_cfg04_t;
  * PCI_CFG05 = Sixth 32-bits of PCI config space (Base Address Register 0 - High)
  *
  */
-union cvmx_pci_cfg05
-{
+union cvmx_pci_cfg05 {
 	uint32_t u32;
-	struct cvmx_pci_cfg05_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg05_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t hbase                        : 32; /**< Base Address[63:32] */
 #else
 	uint32_t hbase                        : 32;
@@ -1166,12 +1150,10 @@ typedef union cvmx_pci_cfg05 cvmx_pci_cfg05_t;
  *       [26:4]:  RAZ (to imply 128MB space)
  *       [31:27]: RW (User may define base address)
  */
-union cvmx_pci_cfg06
-{
+union cvmx_pci_cfg06 {
 	uint32_t u32;
-	struct cvmx_pci_cfg06_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg06_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t lbase                        : 5;  /**< Base Address[31:27]
                                                          In pass 3+:
                                                            Base Address[29:27] read as zero if
@@ -1207,12 +1189,10 @@ typedef union cvmx_pci_cfg06 cvmx_pci_cfg06_t;
  * PCI_CFG07 = Eighth 32-bits of PCI config space (Base Address Register 1 - High)
  *
  */
-union cvmx_pci_cfg07
-{
+union cvmx_pci_cfg07 {
 	uint32_t u32;
-	struct cvmx_pci_cfg07_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg07_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t hbase                        : 32; /**< Base Address[63:32] */
 #else
 	uint32_t hbase                        : 32;
@@ -1239,12 +1219,10 @@ typedef union cvmx_pci_cfg07 cvmx_pci_cfg07_t;
  *       [3]:     1 (Prefetchable)
  *       [31:4]:  RAZ
  */
-union cvmx_pci_cfg08
-{
+union cvmx_pci_cfg08 {
 	uint32_t u32;
-	struct cvmx_pci_cfg08_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg08_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t lbasez                       : 28; /**< Base Address[31:4] (Read as Zero) */
 	uint32_t pf                           : 1;  /**< Prefetchable Space */
 	uint32_t typ                          : 2;  /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */
@@ -1272,12 +1250,10 @@ typedef union cvmx_pci_cfg08 cvmx_pci_cfg08_t;
  * PCI_CFG09 = Tenth 32-bits of PCI config space (Base Address Register 2 - High)
  *
  */
-union cvmx_pci_cfg09
-{
+union cvmx_pci_cfg09 {
 	uint32_t u32;
-	struct cvmx_pci_cfg09_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg09_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t hbase                        : 25; /**< Base Address[63:39] */
 	uint32_t hbasez                       : 7;  /**< Base Address[38:31]  (Read as Zero) */
 #else
@@ -1301,12 +1277,10 @@ typedef union cvmx_pci_cfg09 cvmx_pci_cfg09_t;
  * PCI_CFG10 = Eleventh 32-bits of PCI config space (Card Bus CIS Pointer)
  *
  */
-union cvmx_pci_cfg10
-{
+union cvmx_pci_cfg10 {
 	uint32_t u32;
-	struct cvmx_pci_cfg10_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg10_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t cisp                         : 32; /**< CardBus CIS Pointer (UNUSED) */
 #else
 	uint32_t cisp                         : 32;
@@ -1328,12 +1302,10 @@ typedef union cvmx_pci_cfg10 cvmx_pci_cfg10_t;
  * PCI_CFG11 = Twelfth 32-bits of PCI config space (SubSystem ID/Subsystem Vendor ID Register)
  *
  */
-union cvmx_pci_cfg11
-{
+union cvmx_pci_cfg11 {
 	uint32_t u32;
-	struct cvmx_pci_cfg11_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg11_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ssid                         : 16; /**< SubSystem ID */
 	uint32_t ssvid                        : 16; /**< Subsystem Vendor ID */
 #else
@@ -1357,12 +1329,10 @@ typedef union cvmx_pci_cfg11 cvmx_pci_cfg11_t;
  * PCI_CFG12 = Thirteenth 32-bits of PCI config space (Expansion ROM Base Address Register)
  *
  */
-union cvmx_pci_cfg12
-{
+union cvmx_pci_cfg12 {
 	uint32_t u32;
-	struct cvmx_pci_cfg12_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg12_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t erbar                        : 16; /**< Expansion ROM Base Address[31:16] 64KB in size */
 	uint32_t erbarz                       : 5;  /**< Expansion ROM Base Base Address (Read as Zero) */
 	uint32_t reserved_1_10                : 10;
@@ -1390,12 +1360,10 @@ typedef union cvmx_pci_cfg12 cvmx_pci_cfg12_t;
  * PCI_CFG13 = Fourteenth 32-bits of PCI config space (Capabilities Pointer Register)
  *
  */
-union cvmx_pci_cfg13
-{
+union cvmx_pci_cfg13 {
 	uint32_t u32;
-	struct cvmx_pci_cfg13_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg13_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_8_31                : 24;
 	uint32_t cp                           : 8;  /**< Capabilities Pointer */
 #else
@@ -1419,12 +1387,10 @@ typedef union cvmx_pci_cfg13 cvmx_pci_cfg13_t;
  * PCI_CFG15 = Sixteenth 32-bits of PCI config space (INT/ARB/LATENCY Register)
  *
  */
-union cvmx_pci_cfg15
-{
+union cvmx_pci_cfg15 {
 	uint32_t u32;
-	struct cvmx_pci_cfg15_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg15_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ml                           : 8;  /**< Maximum Latency */
 	uint32_t mg                           : 8;  /**< Minimum Grant */
 	uint32_t inta                         : 8;  /**< Interrupt Pin (INTA#) */
@@ -1452,12 +1418,10 @@ typedef union cvmx_pci_cfg15 cvmx_pci_cfg15_t;
  * PCI_CFG16 = Seventeenth 32-bits of PCI config space (Target Implementation Register)
  *
  */
-union cvmx_pci_cfg16
-{
+union cvmx_pci_cfg16 {
 	uint32_t u32;
-	struct cvmx_pci_cfg16_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg16_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t trdnpr                       : 1;  /**< Target Read Delayed Transaction for I/O and
                                                          non-prefetchable regions discarded. */
 	uint32_t trdard                       : 1;  /**< Target Read Delayed Transaction for all regions
@@ -1547,12 +1511,10 @@ typedef union cvmx_pci_cfg16 cvmx_pci_cfg16_t;
  * PCI_CFG17 = Eighteenth 32-bits of PCI config space (Target Split Completion Message
  * Enable Register)
  */
-union cvmx_pci_cfg17
-{
+union cvmx_pci_cfg17 {
 	uint32_t u32;
-	struct cvmx_pci_cfg17_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg17_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t tscme                        : 32; /**< Target Split Completion Message Enable
                                                           [31:30]: 00
                                                           [29]: Split Completion Error Indication
@@ -1582,12 +1544,10 @@ typedef union cvmx_pci_cfg17 cvmx_pci_cfg17_t;
  * PCI_CFG18 = Nineteenth 32-bits of PCI config space (Target Delayed/Split Request
  * Pending Sequences)
  */
-union cvmx_pci_cfg18
-{
+union cvmx_pci_cfg18 {
 	uint32_t u32;
-	struct cvmx_pci_cfg18_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg18_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t tdsrps                       : 32; /**< Target Delayed/Split Request Pending Sequences
                                                          The application uses this address to remove a
                                                          pending split sequence from the target queue by
@@ -1618,12 +1578,10 @@ typedef union cvmx_pci_cfg18 cvmx_pci_cfg18_t;
  * PCI_CFG19 = Twentieth 32-bits of PCI config space (Master/Target Implementation Register)
  *
  */
-union cvmx_pci_cfg19
-{
+union cvmx_pci_cfg19 {
 	uint32_t u32;
-	struct cvmx_pci_cfg19_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg19_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t mrbcm                        : 1;  /**< Master Request (Memory Read) Byte Count/Byte
                                                          Enable select.
                                                            0 = Byte Enables valid. In PCI mode, a burst
@@ -1761,12 +1719,10 @@ typedef union cvmx_pci_cfg19 cvmx_pci_cfg19_t;
  * PCI_CFG20 = Twenty-first 32-bits of PCI config space (Master Deferred/Split Sequence Pending)
  *
  */
-union cvmx_pci_cfg20
-{
+union cvmx_pci_cfg20 {
 	uint32_t u32;
-	struct cvmx_pci_cfg20_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg20_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t mdsp                         : 32; /**< Master Deferred/Split sequence Pending
                                                          For OCTEON, this register is intended for debug use
                                                          only and MUST NEVER be written with anything other
@@ -1791,12 +1747,10 @@ typedef union cvmx_pci_cfg20 cvmx_pci_cfg20_t;
  * PCI_CFG21 = Twenty-second 32-bits of PCI config space (Master Split Completion Message Register)
  *
  */
-union cvmx_pci_cfg21
-{
+union cvmx_pci_cfg21 {
 	uint32_t u32;
-	struct cvmx_pci_cfg21_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg21_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t scmre                        : 32; /**< Master Split Completion message received with
                                                          error message.
                                                          For OCTEON, this register is intended for debug use
@@ -1822,12 +1776,10 @@ typedef union cvmx_pci_cfg21 cvmx_pci_cfg21_t;
  * PCI_CFG22 = Twenty-third 32-bits of PCI config space (Master Arbiter Control Register)
  *
  */
-union cvmx_pci_cfg22
-{
+union cvmx_pci_cfg22 {
 	uint32_t u32;
-	struct cvmx_pci_cfg22_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg22_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t mac                          : 7;  /**< Master Arbiter Control
                                                          [31:26]: Used only in Fixed Priority mode
                                                                   (when [25]=1)
@@ -1890,12 +1842,10 @@ typedef union cvmx_pci_cfg22 cvmx_pci_cfg22_t;
  * PCI_CFG56 = Fifty-seventh 32-bits of PCI config space (PCIX Capabilities Register)
  *
  */
-union cvmx_pci_cfg56
-{
+union cvmx_pci_cfg56 {
 	uint32_t u32;
-	struct cvmx_pci_cfg56_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg56_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_23_31               : 9;
 	uint32_t most                         : 3;  /**< Maximum outstanding Split transactions
                                                            Encoded Value    \#Max outstanding splits
@@ -1943,12 +1893,10 @@ typedef union cvmx_pci_cfg56 cvmx_pci_cfg56_t;
  * PCI_CFG57 = Fifty-eigth 32-bits of PCI config space (PCIX Status Register)
  *
  */
-union cvmx_pci_cfg57
-{
+union cvmx_pci_cfg57 {
 	uint32_t u32;
-	struct cvmx_pci_cfg57_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg57_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_30_31               : 2;
 	uint32_t scemr                        : 1;  /**< Split Completion Error Message Received */
 	uint32_t mcrsd                        : 3;  /**< Maximum Cumulative Read Size designed */
@@ -1999,12 +1947,10 @@ typedef union cvmx_pci_cfg57 cvmx_pci_cfg57_t;
  * PCI_CFG58 = Fifty-ninth 32-bits of PCI config space (Power Management Capabilities Register)
  *
  */
-union cvmx_pci_cfg58
-{
+union cvmx_pci_cfg58 {
 	uint32_t u32;
-	struct cvmx_pci_cfg58_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg58_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t pmes                         : 5;  /**< PME Support (D0 to D3cold) */
 	uint32_t d2s                          : 1;  /**< D2_Support */
 	uint32_t d1s                          : 1;  /**< D1_Support */
@@ -2049,12 +1995,10 @@ typedef union cvmx_pci_cfg58 cvmx_pci_cfg58_t;
  * PCI_CFG59 = Sixtieth 32-bits of PCI config space (Power Management Data/PMCSR Register(s))
  *
  */
-union cvmx_pci_cfg59
-{
+union cvmx_pci_cfg59 {
 	uint32_t u32;
-	struct cvmx_pci_cfg59_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg59_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t pmdia                        : 8;  /**< Power Management data input from application
                                                          (PME_DATA) */
 	uint32_t bpccen                       : 1;  /**< BPCC_En (bus power/clock control) enable */
@@ -2104,12 +2048,10 @@ typedef union cvmx_pci_cfg59 cvmx_pci_cfg59_t;
  * PCI_CFG60 = Sixty-first 32-bits of PCI config space (MSI Capabilities Register)
  *
  */
-union cvmx_pci_cfg60
-{
+union cvmx_pci_cfg60 {
 	uint32_t u32;
-	struct cvmx_pci_cfg60_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg60_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_24_31               : 8;
 	uint32_t m64                          : 1;  /**< 32/64 b message */
 	uint32_t mme                          : 3;  /**< Multiple Message Enable(1,2,4,8,16,32) */
@@ -2143,12 +2085,10 @@ typedef union cvmx_pci_cfg60 cvmx_pci_cfg60_t;
  * PCI_CFG61 = Sixty-second 32-bits of PCI config space (MSI Lower Address Register)
  *
  */
-union cvmx_pci_cfg61
-{
+union cvmx_pci_cfg61 {
 	uint32_t u32;
-	struct cvmx_pci_cfg61_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg61_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t msi31t2                      : 30; /**< App Specific    MSI Address [31:2] */
 	uint32_t reserved_0_1                 : 2;
 #else
@@ -2172,12 +2112,10 @@ typedef union cvmx_pci_cfg61 cvmx_pci_cfg61_t;
  * PCI_CFG62 = Sixty-third 32-bits of PCI config space (MSI Upper Address Register)
  *
  */
-union cvmx_pci_cfg62
-{
+union cvmx_pci_cfg62 {
 	uint32_t u32;
-	struct cvmx_pci_cfg62_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg62_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t msi                          : 32; /**< MSI Address [63:32] */
 #else
 	uint32_t msi                          : 32;
@@ -2199,12 +2137,10 @@ typedef union cvmx_pci_cfg62 cvmx_pci_cfg62_t;
  * PCI_CFG63 = Sixty-fourth 32-bits of PCI config space (MSI Message Data Register)
  *
  */
-union cvmx_pci_cfg63
-{
+union cvmx_pci_cfg63 {
 	uint32_t u32;
-	struct cvmx_pci_cfg63_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cfg63_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_16_31               : 16;
 	uint32_t msimd                        : 16; /**< MSI Message Data */
 #else
@@ -2229,12 +2165,10 @@ typedef union cvmx_pci_cfg63 cvmx_pci_cfg63_t;
  *
  * This register is provided to software as a means to determine PCI Bus Type/Speed.
  */
-union cvmx_pci_cnt_reg
-{
+union cvmx_pci_cnt_reg {
 	uint64_t u64;
-	struct cvmx_pci_cnt_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_cnt_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_38_63               : 26;
 	uint64_t hm_pcix                      : 1;  /**< PCI Host Mode Sampled Bus Type (0:PCI/1:PCIX)
                                                          This field represents what OCTEON(in Host mode)
@@ -2348,12 +2282,10 @@ typedef union cvmx_pci_cnt_reg cvmx_pci_cnt_reg_t;
  *
  * Control status register accessable from both PCI and NCB.
  */
-union cvmx_pci_ctl_status_2
-{
+union cvmx_pci_ctl_status_2 {
 	uint32_t u32;
-	struct cvmx_pci_ctl_status_2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_ctl_status_2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_29_31               : 3;
 	uint32_t bb1_hole                     : 3;  /**< Big BAR 1 Hole
                                                          NOT IN PASS 1 NOR PASS 2
@@ -2598,9 +2530,8 @@ union cvmx_pci_ctl_status_2
 #endif
 	} s;
 	struct cvmx_pci_ctl_status_2_s        cn30xx;
-	struct cvmx_pci_ctl_status_2_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_ctl_status_2_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_20_31               : 12;
 	uint32_t erst_n                       : 1;  /**< Reset active Low. */
 	uint32_t bar2pres                     : 1;  /**< From fuse block. When fuse(MIO_FUS_DAT3[BAR2_EN])
@@ -2727,12 +2658,10 @@ typedef union cvmx_pci_ctl_status_2 cvmx_pci_ctl_status_2_t;
  * The value to write to the doorbell 0 register. The value in this register is acted upon when the
  * least-significant-byte of this register is written.
  */
-union cvmx_pci_dbellx
-{
+union cvmx_pci_dbellx {
 	uint32_t u32;
-	struct cvmx_pci_dbellx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_dbellx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_16_31               : 16;
 	uint32_t inc_val                      : 16; /**< Software writes this register with the
                                                          number of new Instructions to be processed
@@ -2761,12 +2690,10 @@ typedef union cvmx_pci_dbellx cvmx_pci_dbellx_t;
  * Keeps track of the number of DMAs or bytes sent by DMAs. The value in this register is acted upon when the
  * least-significant-byte of this register is written.
  */
-union cvmx_pci_dma_cntx
-{
+union cvmx_pci_dma_cntx {
 	uint32_t u32;
-	struct cvmx_pci_dma_cntx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_dma_cntx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dma_cnt                      : 32; /**< Update with the number of DMAs completed or the
                                                          number of bytes sent for DMA's associated with
                                                          this counter. When this register is written the
@@ -2793,12 +2720,10 @@ typedef union cvmx_pci_dma_cntx cvmx_pci_dma_cntx_t;
  *
  * Interrupt when the value in PCI_DMA_CNT0 is equal to or greater than the register value.
  */
-union cvmx_pci_dma_int_levx
-{
+union cvmx_pci_dma_int_levx {
 	uint32_t u32;
-	struct cvmx_pci_dma_int_levx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_dma_int_levx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t pkt_cnt                      : 32; /**< When PCI_DMA_CNT0 exceeds the value in this
                                                          DCNT0 will be set in PCI_INT_SUM and PCI_INT_SUM2. */
 #else
@@ -2822,12 +2747,10 @@ typedef union cvmx_pci_dma_int_levx cvmx_pci_dma_int_levx_t;
  *
  * Time to wait from DMA being sent before issuing an interrupt.
  */
-union cvmx_pci_dma_timex
-{
+union cvmx_pci_dma_timex {
 	uint32_t u32;
-	struct cvmx_pci_dma_timex_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_dma_timex_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dma_time                     : 32; /**< Number of PCI clock cycle to wait before
                                                          setting DTIME0 in PCI_INT_SUM and PCI_INT_SUM2.
                                                          After PCI_DMA_CNT0 becomes non-zero.
@@ -2854,12 +2777,10 @@ typedef union cvmx_pci_dma_timex cvmx_pci_dma_timex_t;
  *
  * The number of instructions to be fetched by the Instruction-0 Engine.
  */
-union cvmx_pci_instr_countx
-{
+union cvmx_pci_instr_countx {
 	uint32_t u32;
-	struct cvmx_pci_instr_countx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_instr_countx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t icnt                         : 32; /**< Number of Instructions to be fetched by the
                                                          Instruction Engine.
                                                          A write of any non zero value to this register
@@ -2885,12 +2806,10 @@ typedef union cvmx_pci_instr_countx cvmx_pci_instr_countx_t;
  *
  * Enables interrupt bits in the PCI_INT_SUM register.
  */
-union cvmx_pci_int_enb
-{
+union cvmx_pci_int_enb {
 	uint64_t u64;
-	struct cvmx_pci_int_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t ill_rd                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */
 	uint64_t ill_wr                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */
@@ -2964,9 +2883,8 @@ union cvmx_pci_int_enb
 	uint64_t reserved_34_63               : 30;
 #endif
 	} s;
-	struct cvmx_pci_int_enb_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_int_enb_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t ill_rd                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */
 	uint64_t ill_wr                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */
@@ -3032,9 +2950,8 @@ union cvmx_pci_int_enb
 	uint64_t reserved_34_63               : 30;
 #endif
 	} cn30xx;
-	struct cvmx_pci_int_enb_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_int_enb_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t ill_rd                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */
 	uint64_t ill_wr                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */
@@ -3119,12 +3036,10 @@ typedef union cvmx_pci_int_enb cvmx_pci_int_enb_t;
  *
  * Enables interrupt bits in the PCI_INT_SUM2 register.
  */
-union cvmx_pci_int_enb2
-{
+union cvmx_pci_int_enb2 {
 	uint64_t u64;
-	struct cvmx_pci_int_enb2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_int_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t ill_rd                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */
 	uint64_t ill_wr                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */
@@ -3198,9 +3113,8 @@ union cvmx_pci_int_enb2
 	uint64_t reserved_34_63               : 30;
 #endif
 	} s;
-	struct cvmx_pci_int_enb2_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_int_enb2_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t ill_rd                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */
 	uint64_t ill_wr                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */
@@ -3266,9 +3180,8 @@ union cvmx_pci_int_enb2
 	uint64_t reserved_34_63               : 30;
 #endif
 	} cn30xx;
-	struct cvmx_pci_int_enb2_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_int_enb2_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t ill_rd                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */
 	uint64_t ill_wr                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */
@@ -3353,12 +3266,10 @@ typedef union cvmx_pci_int_enb2 cvmx_pci_int_enb2_t;
  *
  * The PCI Interrupt Summary Register.
  */
-union cvmx_pci_int_sum
-{
+union cvmx_pci_int_sum {
 	uint64_t u64;
-	struct cvmx_pci_int_sum_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t ill_rd                       : 1;  /**< A read to a disabled area of bar1 or bar2,
                                                          when the mem area is disabled. */
@@ -3497,9 +3408,8 @@ union cvmx_pci_int_sum
 	uint64_t reserved_34_63               : 30;
 #endif
 	} s;
-	struct cvmx_pci_int_sum_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_int_sum_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t ill_rd                       : 1;  /**< A read to a disabled area of bar1 or bar2,
                                                          when the mem area is disabled. */
@@ -3609,9 +3519,8 @@ union cvmx_pci_int_sum
 	uint64_t reserved_34_63               : 30;
 #endif
 	} cn30xx;
-	struct cvmx_pci_int_sum_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_int_sum_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t ill_rd                       : 1;  /**< A read to a disabled area of bar1 or bar2,
                                                          when the mem area is disabled. */
@@ -3747,12 +3656,10 @@ typedef union cvmx_pci_int_sum cvmx_pci_int_sum_t;
  *
  * The PCI Interrupt Summary2 Register copy used for RSL interrupts.
  */
-union cvmx_pci_int_sum2
-{
+union cvmx_pci_int_sum2 {
 	uint64_t u64;
-	struct cvmx_pci_int_sum2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_int_sum2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t ill_rd                       : 1;  /**< A read to a disabled area of bar1 or bar2,
                                                          when the mem area is disabled. */
@@ -3874,9 +3781,8 @@ union cvmx_pci_int_sum2
 	uint64_t reserved_34_63               : 30;
 #endif
 	} s;
-	struct cvmx_pci_int_sum2_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_int_sum2_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t ill_rd                       : 1;  /**< A read to a disabled area of bar1 or bar2,
                                                          when the mem area is disabled. */
@@ -3969,9 +3875,8 @@ union cvmx_pci_int_sum2
 	uint64_t reserved_34_63               : 30;
 #endif
 	} cn30xx;
-	struct cvmx_pci_int_sum2_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_int_sum2_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_34_63               : 30;
 	uint64_t ill_rd                       : 1;  /**< A read to a disabled area of bar1 or bar2,
                                                          when the mem area is disabled. */
@@ -4091,12 +3996,10 @@ typedef union cvmx_pci_int_sum2 cvmx_pci_int_sum2_t;
  * A bit is set in this register relative to the vector received during a MSI. The value in this
  * register is acted upon when the least-significant-byte of this register is written.
  */
-union cvmx_pci_msi_rcv
-{
+union cvmx_pci_msi_rcv {
 	uint32_t u32;
-	struct cvmx_pci_msi_rcv_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_msi_rcv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_6_31                : 26;
 	uint32_t intr                         : 6;  /**< When an MSI is received on the PCI the bit selected
                                                          by data [5:0] will be set in this register. To
@@ -4128,12 +4031,10 @@ typedef union cvmx_pci_msi_rcv cvmx_pci_msi_rcv_t;
  * buffer/info pointer pairs to OCTEON Output-0. The value in this register is acted upon when the
  * least-significant-byte of this register is written.
  */
-union cvmx_pci_pkt_creditsx
-{
+union cvmx_pci_pkt_creditsx {
 	uint32_t u32;
-	struct cvmx_pci_pkt_creditsx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_pkt_creditsx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t pkt_cnt                      : 16; /**< The value written to this field will be
                                                          subtracted from PCI_PKTS_SENT0[PKT_CNT]. */
 	uint32_t ptr_cnt                      : 16; /**< This field value is added to the
@@ -4160,12 +4061,10 @@ typedef union cvmx_pci_pkt_creditsx cvmx_pci_pkt_creditsx_t;
  *
  * Number of packets sent to the host memory from PCI Output 0
  */
-union cvmx_pci_pkts_sentx
-{
+union cvmx_pci_pkts_sentx {
 	uint32_t u32;
-	struct cvmx_pci_pkts_sentx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_pkts_sentx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t pkt_cnt                      : 32; /**< Each time a packet is written to the memory via
                                                          PCI from PCI Output 0,  this counter is
                                                          incremented by 1 or the byte count of the packet
@@ -4191,12 +4090,10 @@ typedef union cvmx_pci_pkts_sentx cvmx_pci_pkts_sentx_t;
  *
  * Interrupt when number of packets sent is equal to or greater than the register value.
  */
-union cvmx_pci_pkts_sent_int_levx
-{
+union cvmx_pci_pkts_sent_int_levx {
 	uint32_t u32;
-	struct cvmx_pci_pkts_sent_int_levx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_pkts_sent_int_levx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t pkt_cnt                      : 32; /**< When corresponding port's PCI_PKTS_SENT0 value
                                                          exceeds the value in this register, PCNT0 of the
                                                          PCI_INT_SUM and PCI_INT_SUM2 will be set. */
@@ -4221,12 +4118,10 @@ typedef union cvmx_pci_pkts_sent_int_levx cvmx_pci_pkts_sent_int_levx_t;
  *
  * Time to wait from packet being sent to host from Output-0 before issuing an interrupt.
  */
-union cvmx_pci_pkts_sent_timex
-{
+union cvmx_pci_pkts_sent_timex {
 	uint32_t u32;
-	struct cvmx_pci_pkts_sent_timex_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_pkts_sent_timex_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t pkt_time                     : 32; /**< Number of PCI clock cycle to wait before
                                                          issuing an interrupt to the host when a
                                                          packet from this port has been sent to the
@@ -4253,12 +4148,10 @@ typedef union cvmx_pci_pkts_sent_timex cvmx_pci_pkts_sent_timex_t;
  *
  * Contains control inforamtion related to a received PCI Command 6.
  */
-union cvmx_pci_read_cmd_6
-{
+union cvmx_pci_read_cmd_6 {
 	uint32_t u32;
-	struct cvmx_pci_read_cmd_6_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_read_cmd_6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_9_31                : 23;
 	uint32_t min_data                     : 6;  /**< The number of words to have buffered in the PNI
                                                          before informing the PCIX-Core that we have
@@ -4296,12 +4189,10 @@ typedef union cvmx_pci_read_cmd_6 cvmx_pci_read_cmd_6_t;
  *
  * Contains control inforamtion related to a received PCI Command C.
  */
-union cvmx_pci_read_cmd_c
-{
+union cvmx_pci_read_cmd_c {
 	uint32_t u32;
-	struct cvmx_pci_read_cmd_c_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_read_cmd_c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_9_31                : 23;
 	uint32_t min_data                     : 6;  /**< The number of words to have buffered in the PNI
                                                          before informing the PCIX-Core that we have
@@ -4339,12 +4230,10 @@ typedef union cvmx_pci_read_cmd_c cvmx_pci_read_cmd_c_t;
  *
  * Contains control inforamtion related to a received PCI Command 6.
  */
-union cvmx_pci_read_cmd_e
-{
+union cvmx_pci_read_cmd_e {
 	uint32_t u32;
-	struct cvmx_pci_read_cmd_e_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_read_cmd_e_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_9_31                : 23;
 	uint32_t min_data                     : 6;  /**< The number of words to have buffered in the PNI
                                                          before informaing the PCIX-Core that we have
@@ -4382,12 +4271,10 @@ typedef union cvmx_pci_read_cmd_e cvmx_pci_read_cmd_e_t;
  *
  * The address to start reading Instructions from for Input-3.
  */
-union cvmx_pci_read_timeout
-{
+union cvmx_pci_read_timeout {
 	uint64_t u64;
-	struct cvmx_pci_read_timeout_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_read_timeout_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t enb                          : 1;  /**< Enable the use of the Timeout function. */
 	uint64_t cnt                          : 31; /**< The number of eclk cycles to wait after issuing
@@ -4418,12 +4305,10 @@ typedef union cvmx_pci_read_timeout cvmx_pci_read_timeout_t;
  * This register contains the Master Split Completion Message(SCM) generated when a master split
  * transaction is aborted.
  */
-union cvmx_pci_scm_reg
-{
+union cvmx_pci_scm_reg {
 	uint64_t u64;
-	struct cvmx_pci_scm_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_scm_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t scm                          : 32; /**< Contains the Split Completion Message (SCM)
                                                          driven when a master-split transaction is aborted.
@@ -4459,12 +4344,10 @@ typedef union cvmx_pci_scm_reg cvmx_pci_scm_reg_t;
  * This register contains the Attribute field Master Split Completion Message(SCM) generated when a master split
  * transaction is aborted.
  */
-union cvmx_pci_tsr_reg
-{
+union cvmx_pci_tsr_reg {
 	uint64_t u64;
-	struct cvmx_pci_tsr_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_tsr_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t tsr                          : 36; /**< Contains the Target Split Attribute field when a
                                                          target-split transaction is aborted.
@@ -4504,12 +4387,10 @@ typedef union cvmx_pci_tsr_reg cvmx_pci_tsr_reg_t;
  * UNLESS, a read operation is already taking place. A read is consider to end when the PCI_WIN_RD_DATA
  * register is read.
  */
-union cvmx_pci_win_rd_addr
-{
+union cvmx_pci_win_rd_addr {
 	uint64_t u64;
-	struct cvmx_pci_win_rd_addr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_win_rd_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_49_63               : 15;
 	uint64_t iobit                        : 1;  /**< A 1 or 0 can be written here but this will always
                                                          read as '0'. */
@@ -4520,9 +4401,8 @@ union cvmx_pci_win_rd_addr
 	uint64_t reserved_49_63               : 15;
 #endif
 	} s;
-	struct cvmx_pci_win_rd_addr_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_win_rd_addr_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_49_63               : 15;
 	uint64_t iobit                        : 1;  /**< A 1 or 0 can be written here but this will always
                                                          read as '0'. */
@@ -4545,9 +4425,8 @@ union cvmx_pci_win_rd_addr
 #endif
 	} cn30xx;
 	struct cvmx_pci_win_rd_addr_cn30xx    cn31xx;
-	struct cvmx_pci_win_rd_addr_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_win_rd_addr_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_49_63               : 15;
 	uint64_t iobit                        : 1;  /**< A 1 or 0 can be written here but this will always
                                                          read as '0'. */
@@ -4584,12 +4463,10 @@ typedef union cvmx_pci_win_rd_addr cvmx_pci_win_rd_addr_t;
  * Contains the result from the read operation that took place when the LSB of the PCI_WIN_RD_ADDR
  * register was written.
  */
-union cvmx_pci_win_rd_data
-{
+union cvmx_pci_win_rd_data {
 	uint64_t u64;
-	struct cvmx_pci_win_rd_data_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_win_rd_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rd_data                      : 64; /**< The read data. */
 #else
 	uint64_t rd_data                      : 64;
@@ -4613,12 +4490,10 @@ typedef union cvmx_pci_win_rd_data cvmx_pci_win_rd_data_t;
  * Contains the address to be writen to when a write operation is started by writing the
  * PCI_WIN_WR_DATA register (see below).
  */
-union cvmx_pci_win_wr_addr
-{
+union cvmx_pci_win_wr_addr {
 	uint64_t u64;
-	struct cvmx_pci_win_wr_addr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_win_wr_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_49_63               : 15;
 	uint64_t iobit                        : 1;  /**< A 1 or 0 can be written here but this will always
                                                          read as '0'. */
@@ -4657,12 +4532,10 @@ typedef union cvmx_pci_win_wr_addr cvmx_pci_win_wr_addr_t;
  * Contains the data to write to the address located in the PCI_WIN_WR_ADDR Register.
  * Writing the least-significant-byte of this register will cause a write operation to take place.
  */
-union cvmx_pci_win_wr_data
-{
+union cvmx_pci_win_wr_data {
 	uint64_t u64;
-	struct cvmx_pci_win_wr_data_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_win_wr_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t wr_data                      : 64; /**< The data to be written. Whenever the LSB of this
                                                          register is written, the Window Write will take
                                                          place. */
@@ -4687,12 +4560,10 @@ typedef union cvmx_pci_win_wr_data cvmx_pci_win_wr_data_t;
  *
  * Contains the mask for the data in the PCI_WIN_WR_DATA Register.
  */
-union cvmx_pci_win_wr_mask
-{
+union cvmx_pci_win_wr_mask {
 	uint64_t u64;
-	struct cvmx_pci_win_wr_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pci_win_wr_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t wr_mask                      : 8;  /**< The data to be written. When a bit is set '1'
                                                          the corresponding byte will not be written. */
diff --git a/sys/contrib/octeon-sdk/cvmx-pci.h b/sys/contrib/octeon-sdk/cvmx-pci.h
index a1d9b37..88a2cfc 100644
--- a/sys/contrib/octeon-sdk/cvmx-pci.h
+++ b/sys/contrib/octeon-sdk/cvmx-pci.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * PCI related structures.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_PCI_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-pcie.c b/sys/contrib/octeon-sdk/cvmx-pcie.c
index bfa6091..60562cb 100644
--- a/sys/contrib/octeon-sdk/cvmx-pcie.c
+++ b/sys/contrib/octeon-sdk/cvmx-pcie.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2011  Cavium, Inc. <support@cavium.com>.  All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -37,18 +37,12 @@
  * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
-
-
-
-
-
-
 /**
  * @file
  *
  * Interface to PCIe as a host(RC) or target(EP)
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <asm/octeon/cvmx.h>
@@ -56,6 +50,7 @@
 #include <asm/octeon/cvmx-clock.h>
 #include <asm/octeon/cvmx-ciu-defs.h>
 #include <asm/octeon/cvmx-dpi-defs.h>
+#include <asm/octeon/cvmx-mio-defs.h>
 #include <asm/octeon/cvmx-npi-defs.h>
 #include <asm/octeon/cvmx-npei-defs.h>
 #include <asm/octeon/cvmx-pci-defs.h>
@@ -66,6 +61,7 @@
 #include <asm/octeon/cvmx-pescx-defs.h>
 #include <asm/octeon/cvmx-sli-defs.h>
 #include <asm/octeon/cvmx-sriox-defs.h>
+#include <asm/octeon/cvmx-helper-jtag.h>
 
 #ifdef CONFIG_CAVIUM_DECODE_RSL
 #include <asm/octeon/cvmx-error.h>
@@ -73,6 +69,7 @@
 #include <asm/octeon/cvmx-helper.h>
 #include <asm/octeon/cvmx-helper-board.h>
 #include <asm/octeon/cvmx-helper-errata.h>
+#include <asm/octeon/cvmx-qlm.h>
 #include <asm/octeon/cvmx-pcie.h>
 #include <asm/octeon/cvmx-sysinfo.h>
 #include <asm/octeon/cvmx-swap.h>
@@ -86,6 +83,7 @@
 #include "cvmx-wqe.h"
 #include "cvmx-error.h"
 #include "cvmx-helper-errata.h"
+#include "cvmx-qlm.h"
 #endif
 
 #define MRRS_CN5XXX 0 /* 128 byte Max Read Request Size */
@@ -221,6 +219,8 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
         prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port));
         prt_cfg.s.mps = MPS_CN6XXX;
         prt_cfg.s.mrrs = MRRS_CN6XXX;
+        /* Max outstanding load request. */
+        prt_cfg.s.molr = 32;
         cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);
 
         sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));
@@ -456,6 +456,13 @@ static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port)
     return 0;
 }
 
+static inline void __cvmx_increment_ba(cvmx_sli_mem_access_subidx_t *pmas)
+{   
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+        pmas->cn68xx.ba++;
+    else
+        pmas->cn63xx.ba++;
+}
 
 /**
  * Initialize a PCIe gen 1 port for use in host(RC) mode. It doesn't enumerate
@@ -822,7 +829,6 @@ retry:
     return 0;
 }
 
-
 /**
  * @INTERNAL
  * Initialize a host mode PCIe gen 2 link. This function takes a PCIe
@@ -853,7 +859,7 @@ static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port)
             return -1;
         cvmx_wait(10000);
         pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
-    } while (pciercx_cfg032.s.dlla == 0);
+    } while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1));
 
     /* Update the Replay Time Limit. Empirically, some PCIe devices take a
         little longer to respond than expected under load. As a workaround for
@@ -904,21 +910,75 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
     cvmx_sli_ctl_portx_t sli_ctl_portx;
     cvmx_sli_mem_access_ctl_t sli_mem_access_ctl;
     cvmx_sli_mem_access_subidx_t mem_access_subid;
-    cvmx_mio_rst_ctlx_t mio_rst_ctlx;
-    cvmx_sriox_status_reg_t sriox_status_reg;
     cvmx_pemx_bar1_indexx_t bar1_index;
+    int ep_mode;
 
-    /* Make sure this interface isn't SRIO */
-    sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(pcie_port));
-    if (sriox_status_reg.s.srio)
+    /* Make sure this interface is PCIe */
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
     {
-        cvmx_dprintf("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
-        return -1;
+        /* Requires reading the MIO_QLMX_CFG register to figure
+           out the port type. */
+        int qlm = pcie_port;
+        int status;
+        if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+            qlm = 3 - (pcie_port * 2);
+        else if (OCTEON_IS_MODEL(OCTEON_CN61XX))
+        {
+            cvmx_mio_qlmx_cfg_t qlm_cfg;
+            qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1));
+            if (qlm_cfg.s.qlm_cfg == 1)
+                qlm = 1;
+        }
+        /* PCIe is allowed only in QLM1, 1 PCIe port in x2 or 
+           2 PCIe ports in x1 */
+        else if (OCTEON_IS_MODEL(OCTEON_CNF71XX))
+            qlm = 1;
+        status = cvmx_qlm_get_status(qlm);
+        if (status == 4 || status == 5)
+        {
+            cvmx_dprintf("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
+            return -1;
+        }
+        if (status == 1)
+        {
+            cvmx_dprintf("PCIe: Port %d is SGMII, skipping.\n", pcie_port);
+            return -1;
+        }
+        if (status == 2)
+        {
+            cvmx_dprintf("PCIe: Port %d is XAUI, skipping.\n", pcie_port);
+            return -1;
+        }
+        if (status == -1)
+        {
+            cvmx_dprintf("PCIe: Port %d is unknown, skipping.\n", pcie_port);
+            return -1;
+        }
     }
 
+#if 0
+    /* This code is so that the PCIe analyzer is able to see 63XX traffic */
+    cvmx_dprintf("PCIE : init for pcie analyzer.\n");
+    cvmx_helper_qlm_jtag_init();
+    cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
+    cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
+    cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
+    cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
+    cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
+    cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
+    cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
+    cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
+    cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
+    cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
+    cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
+    cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
+    cvmx_helper_qlm_jtag_update(pcie_port);
+#endif
+
     /* Make sure we aren't trying to setup a target mode interface in host mode */
     mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port));
-    if (!mio_rst_ctl.s.host_mode)
+    ep_mode = (OCTEON_IS_MODEL(OCTEON_CN61XX || OCTEON_IS_MODEL(OCTEON_CNF71XX)) ? (mio_rst_ctl.s.prtmode != 1) : (!mio_rst_ctl.s.host_mode));
+    if (ep_mode)
     {
         cvmx_dprintf("PCIe: Port %d in endpoint mode.\n", pcie_port);
         return -1;
@@ -946,7 +1006,6 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
             cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64);
         }
     }
-
     /* Bring the PCIe out of reset */
     if (pcie_port)
         ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
@@ -985,8 +1044,7 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
     /* Check and make sure PCIe came out of reset. If it doesn't the board
         probably hasn't wired the clocks up and the interface should be
         skipped */
-    mio_rst_ctlx.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port));
-    if (!mio_rst_ctlx.s.rst_done)
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_RST_CTLX(pcie_port), cvmx_mio_rst_ctlx_t, rst_done, ==, 1, 10000))
     {
         cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
         return -1;
@@ -997,6 +1055,9 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
     if (pemx_bist_status.u64)
         cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status.u64));
     pemx_bist_status2.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS2(pcie_port));
+    /* Errata PCIE-14766 may cause the lower 6 bits to be randomly set on CN63XXp1 */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+        pemx_bist_status2.u64 &= ~0x3full;
     if (pemx_bist_status2.u64)
         cvmx_dprintf("PCIe: BIST2 FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status2.u64));
 
@@ -1016,7 +1077,7 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
         cvmx_pciercx_cfg031_t pciercx_cfg031;
         pciercx_cfg031.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG031(pcie_port));
         pciercx_cfg031.s.mls = 1;
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG031(pcie_port), pciercx_cfg515.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG031(pcie_port), pciercx_cfg031.u32);
         if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port))
         {
             cvmx_dprintf("PCIe: Link timeout on port %d, probably the slot is empty\n", pcie_port);
@@ -1038,22 +1099,30 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
     mem_access_subid.s.esw = 1;     /* Endian-swap for Writes. */
     mem_access_subid.s.wtype = 0;   /* "No snoop" and "Relaxed ordering" are not set */
     mem_access_subid.s.rtype = 0;   /* "No snoop" and "Relaxed ordering" are not set */
-    mem_access_subid.s.ba = 0;      /* PCIe Adddress Bits <63:34>. */
+    /* PCIe Adddress Bits <63:34>. */
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+        mem_access_subid.cn68xx.ba = 0;
+    else
+        mem_access_subid.cn63xx.ba = 0;
 
     /* Setup mem access 12-15 for port 0, 16-19 for port 1, supplying 36 bits of address space */
     for (i=12 + pcie_port*4; i<16 + pcie_port*4; i++)
     {
         cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
-        mem_access_subid.s.ba += 1; /* Set each SUBID to extend the addressable range */
+        /* Set each SUBID to extend the addressable range */
+	__cvmx_increment_ba(&mem_access_subid);
     }
 
-    /* Disable the peer to peer forwarding register. This must be setup
-        by the OS after it enumerates the bus and assigns addresses to the
-        PCIe busses */
-    for (i=0; i<4; i++)
+    if (!OCTEON_IS_MODEL(OCTEON_CN61XX))
     {
-        cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1);
-        cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1);
+        /* Disable the peer to peer forwarding register. This must be setup
+            by the OS after it enumerates the bus and assigns addresses to the
+            PCIe busses */
+        for (i=0; i<4; i++)
+        {
+            cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1);
+            cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1);
+        }
     }
 
     /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
@@ -1409,8 +1478,10 @@ int cvmx_pcie_ep_initialize(int pcie_port)
     else
     {
         cvmx_mio_rst_ctlx_t mio_rst_ctl;
+        int ep_mode;
         mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port));
-        if (mio_rst_ctl.s.host_mode)
+        ep_mode = (OCTEON_IS_MODEL(OCTEON_CN61XX) ? (mio_rst_ctl.s.prtmode != 0) : mio_rst_ctl.s.host_mode);
+        if (ep_mode)
             return -1;
     }
 
@@ -1485,6 +1556,8 @@ int cvmx_pcie_ep_initialize(int pcie_port)
         prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port));
         prt_cfg.s.mps = MPS_CN6XXX;
         prt_cfg.s.mrrs = MRRS_CN6XXX;
+        /* Max outstanding load request. */
+        prt_cfg.s.molr = 32;
         cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);
 
         sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));
@@ -1518,7 +1591,11 @@ int cvmx_pcie_ep_initialize(int pcie_port)
         mem_access_subid.s.esw = 0;     /* Endian-swap for Writes. */
         mem_access_subid.s.wtype = 0;   /* "No snoop" and "Relaxed ordering" are not set */
         mem_access_subid.s.rtype = 0;   /* "No snoop" and "Relaxed ordering" are not set */
-        mem_access_subid.s.ba = 0;      /* PCIe Adddress Bits <63:34>. */
+        /* PCIe Adddress Bits <63:34>. */
+        if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+            mem_access_subid.cn68xx.ba = 0;
+        else
+            mem_access_subid.cn63xx.ba = 0;
         cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(12 + pcie_port*4), mem_access_subid.u64);
     }
     return 0;
diff --git a/sys/contrib/octeon-sdk/cvmx-pcie.h b/sys/contrib/octeon-sdk/cvmx-pcie.h
index 962150f..3b23d67 100644
--- a/sys/contrib/octeon-sdk/cvmx-pcie.h
+++ b/sys/contrib/octeon-sdk/cvmx-pcie.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Interface to PCIe as a host(RC) or target(EP)
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_PCIE_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-pcieepx-defs.h b/sys/contrib/octeon-sdk/cvmx-pcieepx-defs.h
index 6af85a1..4562d6d 100644
--- a/sys/contrib/octeon-sdk/cvmx-pcieepx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-pcieepx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_PCIEEPX_TYPEDEFS_H__
-#define __CVMX_PCIEEPX_TYPEDEFS_H__
+#ifndef __CVMX_PCIEEPX_DEFS_H__
+#define __CVMX_PCIEEPX_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCIEEPX_CFG000(unsigned long block_id)
@@ -58,7 +58,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG000(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG000(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000000ull;
 }
@@ -71,7 +75,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG001(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG001(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000004ull;
 }
@@ -84,7 +92,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG002(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG002(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000008ull;
 }
@@ -97,7 +109,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG003(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG003(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000000Cull;
 }
@@ -110,7 +126,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG004(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG004(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000010ull;
 }
@@ -123,7 +143,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG004_MASK(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG004_MASK(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000080000010ull;
 }
@@ -136,7 +160,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG005(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG005(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000014ull;
 }
@@ -149,7 +177,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG005_MASK(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG005_MASK(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000080000014ull;
 }
@@ -162,7 +194,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG006(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG006(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000018ull;
 }
@@ -175,7 +211,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG006_MASK(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG006_MASK(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000080000018ull;
 }
@@ -188,7 +228,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG007(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG007(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000001Cull;
 }
@@ -201,7 +245,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG007_MASK(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG007_MASK(%lu) is invalid on this chip\n", block_id);
 	return 0x000000008000001Cull;
 }
@@ -214,7 +262,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG008(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG008(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000020ull;
 }
@@ -227,7 +279,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG008_MASK(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG008_MASK(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000080000020ull;
 }
@@ -240,7 +296,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG009(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG009(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000024ull;
 }
@@ -253,7 +313,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG009_MASK(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG009_MASK(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000080000024ull;
 }
@@ -266,7 +330,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG010(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG010(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000028ull;
 }
@@ -279,7 +347,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG011(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG011(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000002Cull;
 }
@@ -292,7 +364,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG012(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG012(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000030ull;
 }
@@ -305,7 +381,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG012_MASK(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG012_MASK(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000080000030ull;
 }
@@ -318,7 +398,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG013(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG013(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000034ull;
 }
@@ -331,7 +415,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG015(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG015(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000003Cull;
 }
@@ -344,7 +432,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG016(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG016(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000040ull;
 }
@@ -357,7 +449,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG017(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG017(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000044ull;
 }
@@ -370,7 +466,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG020(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG020(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000050ull;
 }
@@ -383,7 +483,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG021(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG021(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000054ull;
 }
@@ -396,7 +500,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG022(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG022(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000058ull;
 }
@@ -409,7 +517,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG023(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG023(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000005Cull;
 }
@@ -422,7 +534,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG028(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG028(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000070ull;
 }
@@ -435,7 +551,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG029(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG029(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000074ull;
 }
@@ -448,7 +568,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG030(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG030(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000078ull;
 }
@@ -461,7 +585,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG031(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG031(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000007Cull;
 }
@@ -474,7 +602,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG032(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG032(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000080ull;
 }
@@ -513,7 +645,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG037(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG037(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000094ull;
 }
@@ -526,7 +662,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG038(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG038(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000098ull;
 }
@@ -539,7 +679,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG039(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG039(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000009Cull;
 }
@@ -552,7 +696,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG040(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG040(%lu) is invalid on this chip\n", block_id);
 	return 0x00000000000000A0ull;
 }
@@ -591,7 +739,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG064(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG064(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000100ull;
 }
@@ -604,7 +756,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG065(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG065(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000104ull;
 }
@@ -617,7 +773,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG066(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG066(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000108ull;
 }
@@ -630,7 +790,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG067(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG067(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000010Cull;
 }
@@ -643,7 +807,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG068(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG068(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000110ull;
 }
@@ -656,7 +824,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG069(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG069(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000114ull;
 }
@@ -669,7 +841,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG070(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG070(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000118ull;
 }
@@ -682,7 +858,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG071(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG071(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000011Cull;
 }
@@ -695,7 +875,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG072(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG072(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000120ull;
 }
@@ -708,7 +892,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG073(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG073(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000124ull;
 }
@@ -721,7 +909,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG074(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG074(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000128ull;
 }
@@ -734,7 +926,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG448(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG448(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000700ull;
 }
@@ -747,7 +943,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG449(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG449(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000704ull;
 }
@@ -760,7 +960,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG450(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG450(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000708ull;
 }
@@ -773,7 +977,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG451(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG451(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000070Cull;
 }
@@ -786,7 +994,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG452(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG452(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000710ull;
 }
@@ -799,7 +1011,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG453(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG453(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000714ull;
 }
@@ -812,7 +1028,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG454(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG454(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000718ull;
 }
@@ -825,7 +1045,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG455(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG455(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000071Cull;
 }
@@ -838,7 +1062,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG456(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG456(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000720ull;
 }
@@ -851,7 +1079,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG458(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG458(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000728ull;
 }
@@ -864,7 +1096,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG459(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG459(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000072Cull;
 }
@@ -877,7 +1113,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG460(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG460(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000730ull;
 }
@@ -890,7 +1130,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG461(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG461(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000734ull;
 }
@@ -903,7 +1147,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG462(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG462(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000738ull;
 }
@@ -916,7 +1164,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG463(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG463(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000073Cull;
 }
@@ -929,7 +1181,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG464(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG464(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000740ull;
 }
@@ -942,7 +1198,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG465(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG465(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000744ull;
 }
@@ -955,7 +1215,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG466(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG466(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000748ull;
 }
@@ -968,7 +1232,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG467(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG467(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000074Cull;
 }
@@ -981,7 +1249,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG468(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG468(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000750ull;
 }
@@ -994,7 +1266,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG490(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG490(%lu) is invalid on this chip\n", block_id);
 	return 0x00000000000007A8ull;
 }
@@ -1007,7 +1283,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG491(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG491(%lu) is invalid on this chip\n", block_id);
 	return 0x00000000000007ACull;
 }
@@ -1020,7 +1300,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG492(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG492(%lu) is invalid on this chip\n", block_id);
 	return 0x00000000000007B0ull;
 }
@@ -1031,7 +1315,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG492(unsigned long block_id)
 static inline uint64_t CVMX_PCIEEPX_CFG515(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG515(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000080Cull;
 }
@@ -1044,7 +1332,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG516(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG516(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000810ull;
 }
@@ -1057,7 +1349,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG517(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIEEPX_CFG517(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000814ull;
 }
@@ -1071,12 +1367,10 @@ static inline uint64_t CVMX_PCIEEPX_CFG517(unsigned long block_id)
  * PCIE_CFG000 = First 32-bits of PCIE type 0 config space (Device ID and Vendor ID Register)
  *
  */
-union cvmx_pcieepx_cfg000
-{
+union cvmx_pcieepx_cfg000 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg000_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg000_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t devid                        : 16; /**< Device ID, writable through PEM(0..1)_CFG_WR
                                                           However, the application must not change this field.
                                                          For EEPROM loads also see VENDID of this register. */
@@ -1096,8 +1390,13 @@ union cvmx_pcieepx_cfg000
 	struct cvmx_pcieepx_cfg000_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg000_s          cn56xx;
 	struct cvmx_pcieepx_cfg000_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg000_s          cn61xx;
 	struct cvmx_pcieepx_cfg000_s          cn63xx;
 	struct cvmx_pcieepx_cfg000_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg000_s          cn66xx;
+	struct cvmx_pcieepx_cfg000_s          cn68xx;
+	struct cvmx_pcieepx_cfg000_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg000_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg000 cvmx_pcieepx_cfg000_t;
 
@@ -1107,12 +1406,10 @@ typedef union cvmx_pcieepx_cfg000 cvmx_pcieepx_cfg000_t;
  * PCIE_CFG001 = Second 32-bits of PCIE type 0 config space (Command/Status Register)
  *
  */
-union cvmx_pcieepx_cfg001
-{
+union cvmx_pcieepx_cfg001 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg001_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg001_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dpe                          : 1;  /**< Detected Parity Error */
 	uint32_t sse                          : 1;  /**< Signaled System Error */
 	uint32_t rma                          : 1;  /**< Received Master Abort */
@@ -1178,8 +1475,13 @@ union cvmx_pcieepx_cfg001
 	struct cvmx_pcieepx_cfg001_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg001_s          cn56xx;
 	struct cvmx_pcieepx_cfg001_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg001_s          cn61xx;
 	struct cvmx_pcieepx_cfg001_s          cn63xx;
 	struct cvmx_pcieepx_cfg001_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg001_s          cn66xx;
+	struct cvmx_pcieepx_cfg001_s          cn68xx;
+	struct cvmx_pcieepx_cfg001_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg001_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg001 cvmx_pcieepx_cfg001_t;
 
@@ -1189,12 +1491,10 @@ typedef union cvmx_pcieepx_cfg001 cvmx_pcieepx_cfg001_t;
  * PCIE_CFG002 = Third 32-bits of PCIE type 0 config space (Revision ID/Class Code Register)
  *
  */
-union cvmx_pcieepx_cfg002
-{
+union cvmx_pcieepx_cfg002 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg002_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg002_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t bcc                          : 8;  /**< Base Class Code, writable through PEM(0..1)_CFG_WR
                                                          However, the application must not change this field. */
 	uint32_t sc                           : 8;  /**< Subclass Code, writable through PEM(0..1)_CFG_WR
@@ -1214,8 +1514,13 @@ union cvmx_pcieepx_cfg002
 	struct cvmx_pcieepx_cfg002_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg002_s          cn56xx;
 	struct cvmx_pcieepx_cfg002_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg002_s          cn61xx;
 	struct cvmx_pcieepx_cfg002_s          cn63xx;
 	struct cvmx_pcieepx_cfg002_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg002_s          cn66xx;
+	struct cvmx_pcieepx_cfg002_s          cn68xx;
+	struct cvmx_pcieepx_cfg002_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg002_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg002 cvmx_pcieepx_cfg002_t;
 
@@ -1225,12 +1530,10 @@ typedef union cvmx_pcieepx_cfg002 cvmx_pcieepx_cfg002_t;
  * PCIE_CFG003 = Fourth 32-bits of PCIE type 0 config space (Cache Line Size/Master Latency Timer/Header Type Register/BIST Register)
  *
  */
-union cvmx_pcieepx_cfg003
-{
+union cvmx_pcieepx_cfg003 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg003_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg003_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t bist                         : 8;  /**< The BIST register functions are not supported.
                                                          All 8 bits of the BIST register are hardwired to 0. */
 	uint32_t mfd                          : 1;  /**< Multi Function Device
@@ -1259,8 +1562,13 @@ union cvmx_pcieepx_cfg003
 	struct cvmx_pcieepx_cfg003_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg003_s          cn56xx;
 	struct cvmx_pcieepx_cfg003_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg003_s          cn61xx;
 	struct cvmx_pcieepx_cfg003_s          cn63xx;
 	struct cvmx_pcieepx_cfg003_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg003_s          cn66xx;
+	struct cvmx_pcieepx_cfg003_s          cn68xx;
+	struct cvmx_pcieepx_cfg003_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg003_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg003 cvmx_pcieepx_cfg003_t;
 
@@ -1270,12 +1578,10 @@ typedef union cvmx_pcieepx_cfg003 cvmx_pcieepx_cfg003_t;
  * PCIE_CFG004 = Fifth 32-bits of PCIE type 0 config space (Base Address Register 0 - Low)
  *
  */
-union cvmx_pcieepx_cfg004
-{
+union cvmx_pcieepx_cfg004 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg004_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg004_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t lbab                         : 18; /**< Lower bits of the BAR 0 base address */
 	uint32_t reserved_4_13                : 10;
 	uint32_t pf                           : 1;  /**< Prefetchable
@@ -1303,8 +1609,13 @@ union cvmx_pcieepx_cfg004
 	struct cvmx_pcieepx_cfg004_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg004_s          cn56xx;
 	struct cvmx_pcieepx_cfg004_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg004_s          cn61xx;
 	struct cvmx_pcieepx_cfg004_s          cn63xx;
 	struct cvmx_pcieepx_cfg004_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg004_s          cn66xx;
+	struct cvmx_pcieepx_cfg004_s          cn68xx;
+	struct cvmx_pcieepx_cfg004_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg004_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg004 cvmx_pcieepx_cfg004_t;
 
@@ -1315,12 +1626,10 @@ typedef union cvmx_pcieepx_cfg004 cvmx_pcieepx_cfg004_t;
  * The BAR 0 Mask register is invisible to host software and not readable from the application.
  * The BAR 0 Mask register is only writable through PEM(0..1)_CFG_WR.
  */
-union cvmx_pcieepx_cfg004_mask
-{
+union cvmx_pcieepx_cfg004_mask {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg004_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg004_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t lmask                        : 31; /**< Bar Mask Low */
 	uint32_t enb                          : 1;  /**< Bar Enable
                                                          o 0: BAR 0 is disabled
@@ -1338,8 +1647,13 @@ union cvmx_pcieepx_cfg004_mask
 	struct cvmx_pcieepx_cfg004_mask_s     cn52xxp1;
 	struct cvmx_pcieepx_cfg004_mask_s     cn56xx;
 	struct cvmx_pcieepx_cfg004_mask_s     cn56xxp1;
+	struct cvmx_pcieepx_cfg004_mask_s     cn61xx;
 	struct cvmx_pcieepx_cfg004_mask_s     cn63xx;
 	struct cvmx_pcieepx_cfg004_mask_s     cn63xxp1;
+	struct cvmx_pcieepx_cfg004_mask_s     cn66xx;
+	struct cvmx_pcieepx_cfg004_mask_s     cn68xx;
+	struct cvmx_pcieepx_cfg004_mask_s     cn68xxp1;
+	struct cvmx_pcieepx_cfg004_mask_s     cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg004_mask cvmx_pcieepx_cfg004_mask_t;
 
@@ -1349,12 +1663,10 @@ typedef union cvmx_pcieepx_cfg004_mask cvmx_pcieepx_cfg004_mask_t;
  * PCIE_CFG005 = Sixth 32-bits of PCIE type 0 config space (Base Address Register 0 - High)
  *
  */
-union cvmx_pcieepx_cfg005
-{
+union cvmx_pcieepx_cfg005 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg005_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg005_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ubab                         : 32; /**< Contains the upper 32 bits of the BAR 0 base address. */
 #else
 	uint32_t ubab                         : 32;
@@ -1364,8 +1676,13 @@ union cvmx_pcieepx_cfg005
 	struct cvmx_pcieepx_cfg005_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg005_s          cn56xx;
 	struct cvmx_pcieepx_cfg005_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg005_s          cn61xx;
 	struct cvmx_pcieepx_cfg005_s          cn63xx;
 	struct cvmx_pcieepx_cfg005_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg005_s          cn66xx;
+	struct cvmx_pcieepx_cfg005_s          cn68xx;
+	struct cvmx_pcieepx_cfg005_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg005_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg005 cvmx_pcieepx_cfg005_t;
 
@@ -1376,12 +1693,10 @@ typedef union cvmx_pcieepx_cfg005 cvmx_pcieepx_cfg005_t;
  * The BAR 0 Mask register is invisible to host software and not readable from the application.
  * The BAR 0 Mask register is only writable through PEM(0..1)_CFG_WR.
  */
-union cvmx_pcieepx_cfg005_mask
-{
+union cvmx_pcieepx_cfg005_mask {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg005_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg005_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t umask                        : 32; /**< Bar Mask High */
 #else
 	uint32_t umask                        : 32;
@@ -1391,8 +1706,13 @@ union cvmx_pcieepx_cfg005_mask
 	struct cvmx_pcieepx_cfg005_mask_s     cn52xxp1;
 	struct cvmx_pcieepx_cfg005_mask_s     cn56xx;
 	struct cvmx_pcieepx_cfg005_mask_s     cn56xxp1;
+	struct cvmx_pcieepx_cfg005_mask_s     cn61xx;
 	struct cvmx_pcieepx_cfg005_mask_s     cn63xx;
 	struct cvmx_pcieepx_cfg005_mask_s     cn63xxp1;
+	struct cvmx_pcieepx_cfg005_mask_s     cn66xx;
+	struct cvmx_pcieepx_cfg005_mask_s     cn68xx;
+	struct cvmx_pcieepx_cfg005_mask_s     cn68xxp1;
+	struct cvmx_pcieepx_cfg005_mask_s     cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg005_mask cvmx_pcieepx_cfg005_mask_t;
 
@@ -1402,12 +1722,10 @@ typedef union cvmx_pcieepx_cfg005_mask cvmx_pcieepx_cfg005_mask_t;
  * PCIE_CFG006 = Seventh 32-bits of PCIE type 0 config space (Base Address Register 1 - Low)
  *
  */
-union cvmx_pcieepx_cfg006
-{
+union cvmx_pcieepx_cfg006 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg006_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg006_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t lbab                         : 6;  /**< Lower bits of the BAR 1 base address */
 	uint32_t reserved_4_25                : 22;
 	uint32_t pf                           : 1;  /**< Prefetchable
@@ -1435,8 +1753,13 @@ union cvmx_pcieepx_cfg006
 	struct cvmx_pcieepx_cfg006_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg006_s          cn56xx;
 	struct cvmx_pcieepx_cfg006_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg006_s          cn61xx;
 	struct cvmx_pcieepx_cfg006_s          cn63xx;
 	struct cvmx_pcieepx_cfg006_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg006_s          cn66xx;
+	struct cvmx_pcieepx_cfg006_s          cn68xx;
+	struct cvmx_pcieepx_cfg006_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg006_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg006 cvmx_pcieepx_cfg006_t;
 
@@ -1447,12 +1770,10 @@ typedef union cvmx_pcieepx_cfg006 cvmx_pcieepx_cfg006_t;
  * The BAR 1 Mask register is invisible to host software and not readable from the application.
  * The BAR 1 Mask register is only writable through PEM(0..1)_CFG_WR.
  */
-union cvmx_pcieepx_cfg006_mask
-{
+union cvmx_pcieepx_cfg006_mask {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg006_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg006_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t lmask                        : 31; /**< Bar Mask Low */
 	uint32_t enb                          : 1;  /**< Bar Enable
                                                          o 0: BAR 1 is disabled
@@ -1470,8 +1791,13 @@ union cvmx_pcieepx_cfg006_mask
 	struct cvmx_pcieepx_cfg006_mask_s     cn52xxp1;
 	struct cvmx_pcieepx_cfg006_mask_s     cn56xx;
 	struct cvmx_pcieepx_cfg006_mask_s     cn56xxp1;
+	struct cvmx_pcieepx_cfg006_mask_s     cn61xx;
 	struct cvmx_pcieepx_cfg006_mask_s     cn63xx;
 	struct cvmx_pcieepx_cfg006_mask_s     cn63xxp1;
+	struct cvmx_pcieepx_cfg006_mask_s     cn66xx;
+	struct cvmx_pcieepx_cfg006_mask_s     cn68xx;
+	struct cvmx_pcieepx_cfg006_mask_s     cn68xxp1;
+	struct cvmx_pcieepx_cfg006_mask_s     cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg006_mask cvmx_pcieepx_cfg006_mask_t;
 
@@ -1481,12 +1807,10 @@ typedef union cvmx_pcieepx_cfg006_mask cvmx_pcieepx_cfg006_mask_t;
  * PCIE_CFG007 = Eighth 32-bits of PCIE type 0 config space (Base Address Register 1 - High)
  *
  */
-union cvmx_pcieepx_cfg007
-{
+union cvmx_pcieepx_cfg007 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg007_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg007_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ubab                         : 32; /**< Contains the upper 32 bits of the BAR 1 base address. */
 #else
 	uint32_t ubab                         : 32;
@@ -1496,8 +1820,13 @@ union cvmx_pcieepx_cfg007
 	struct cvmx_pcieepx_cfg007_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg007_s          cn56xx;
 	struct cvmx_pcieepx_cfg007_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg007_s          cn61xx;
 	struct cvmx_pcieepx_cfg007_s          cn63xx;
 	struct cvmx_pcieepx_cfg007_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg007_s          cn66xx;
+	struct cvmx_pcieepx_cfg007_s          cn68xx;
+	struct cvmx_pcieepx_cfg007_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg007_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg007 cvmx_pcieepx_cfg007_t;
 
@@ -1508,12 +1837,10 @@ typedef union cvmx_pcieepx_cfg007 cvmx_pcieepx_cfg007_t;
  * The BAR 1 Mask register is invisible to host software and not readable from the application.
  * The BAR 1 Mask register is only writable through PEM(0..1)_CFG_WR.
  */
-union cvmx_pcieepx_cfg007_mask
-{
+union cvmx_pcieepx_cfg007_mask {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg007_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg007_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t umask                        : 32; /**< Bar Mask High */
 #else
 	uint32_t umask                        : 32;
@@ -1523,8 +1850,13 @@ union cvmx_pcieepx_cfg007_mask
 	struct cvmx_pcieepx_cfg007_mask_s     cn52xxp1;
 	struct cvmx_pcieepx_cfg007_mask_s     cn56xx;
 	struct cvmx_pcieepx_cfg007_mask_s     cn56xxp1;
+	struct cvmx_pcieepx_cfg007_mask_s     cn61xx;
 	struct cvmx_pcieepx_cfg007_mask_s     cn63xx;
 	struct cvmx_pcieepx_cfg007_mask_s     cn63xxp1;
+	struct cvmx_pcieepx_cfg007_mask_s     cn66xx;
+	struct cvmx_pcieepx_cfg007_mask_s     cn68xx;
+	struct cvmx_pcieepx_cfg007_mask_s     cn68xxp1;
+	struct cvmx_pcieepx_cfg007_mask_s     cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg007_mask cvmx_pcieepx_cfg007_mask_t;
 
@@ -1534,12 +1866,10 @@ typedef union cvmx_pcieepx_cfg007_mask cvmx_pcieepx_cfg007_mask_t;
  * PCIE_CFG008 = Ninth 32-bits of PCIE type 0 config space (Base Address Register 2 - Low)
  *
  */
-union cvmx_pcieepx_cfg008
-{
+union cvmx_pcieepx_cfg008 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg008_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg008_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_4_31                : 28;
 	uint32_t pf                           : 1;  /**< Prefetchable
                                                          This field is writable through PEM(0..1)_CFG_WR.
@@ -1565,8 +1895,13 @@ union cvmx_pcieepx_cfg008
 	struct cvmx_pcieepx_cfg008_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg008_s          cn56xx;
 	struct cvmx_pcieepx_cfg008_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg008_s          cn61xx;
 	struct cvmx_pcieepx_cfg008_s          cn63xx;
 	struct cvmx_pcieepx_cfg008_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg008_s          cn66xx;
+	struct cvmx_pcieepx_cfg008_s          cn68xx;
+	struct cvmx_pcieepx_cfg008_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg008_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg008 cvmx_pcieepx_cfg008_t;
 
@@ -1577,12 +1912,10 @@ typedef union cvmx_pcieepx_cfg008 cvmx_pcieepx_cfg008_t;
  * The BAR 2 Mask register is invisible to host software and not readable from the application.
  * The BAR 2 Mask register is only writable through PEM(0..1)_CFG_WR.
  */
-union cvmx_pcieepx_cfg008_mask
-{
+union cvmx_pcieepx_cfg008_mask {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg008_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg008_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t lmask                        : 31; /**< Bar Mask Low */
 	uint32_t enb                          : 1;  /**< Bar Enable
                                                          o 0: BAR 2 is disabled
@@ -1600,8 +1933,13 @@ union cvmx_pcieepx_cfg008_mask
 	struct cvmx_pcieepx_cfg008_mask_s     cn52xxp1;
 	struct cvmx_pcieepx_cfg008_mask_s     cn56xx;
 	struct cvmx_pcieepx_cfg008_mask_s     cn56xxp1;
+	struct cvmx_pcieepx_cfg008_mask_s     cn61xx;
 	struct cvmx_pcieepx_cfg008_mask_s     cn63xx;
 	struct cvmx_pcieepx_cfg008_mask_s     cn63xxp1;
+	struct cvmx_pcieepx_cfg008_mask_s     cn66xx;
+	struct cvmx_pcieepx_cfg008_mask_s     cn68xx;
+	struct cvmx_pcieepx_cfg008_mask_s     cn68xxp1;
+	struct cvmx_pcieepx_cfg008_mask_s     cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg008_mask cvmx_pcieepx_cfg008_mask_t;
 
@@ -1611,20 +1949,17 @@ typedef union cvmx_pcieepx_cfg008_mask cvmx_pcieepx_cfg008_mask_t;
  * PCIE_CFG009 = Tenth 32-bits of PCIE type 0 config space (Base Address Register 2 - High)
  *
  */
-union cvmx_pcieepx_cfg009
-{
+union cvmx_pcieepx_cfg009 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg009_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg009_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_0_31                : 32;
 #else
 	uint32_t reserved_0_31                : 32;
 #endif
 	} s;
-	struct cvmx_pcieepx_cfg009_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg009_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ubab                         : 25; /**< Contains the upper 32 bits of the BAR 2 base address. */
 	uint32_t reserved_0_6                 : 7;
 #else
@@ -1635,17 +1970,21 @@ union cvmx_pcieepx_cfg009
 	struct cvmx_pcieepx_cfg009_cn52xx     cn52xxp1;
 	struct cvmx_pcieepx_cfg009_cn52xx     cn56xx;
 	struct cvmx_pcieepx_cfg009_cn52xx     cn56xxp1;
-	struct cvmx_pcieepx_cfg009_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg009_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ubab                         : 23; /**< Contains the upper 32 bits of the BAR 2 base address. */
 	uint32_t reserved_0_8                 : 9;
 #else
 	uint32_t reserved_0_8                 : 9;
 	uint32_t ubab                         : 23;
 #endif
-	} cn63xx;
-	struct cvmx_pcieepx_cfg009_cn63xx     cn63xxp1;
+	} cn61xx;
+	struct cvmx_pcieepx_cfg009_cn61xx     cn63xx;
+	struct cvmx_pcieepx_cfg009_cn61xx     cn63xxp1;
+	struct cvmx_pcieepx_cfg009_cn61xx     cn66xx;
+	struct cvmx_pcieepx_cfg009_cn61xx     cn68xx;
+	struct cvmx_pcieepx_cfg009_cn61xx     cn68xxp1;
+	struct cvmx_pcieepx_cfg009_cn61xx     cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg009 cvmx_pcieepx_cfg009_t;
 
@@ -1656,12 +1995,10 @@ typedef union cvmx_pcieepx_cfg009 cvmx_pcieepx_cfg009_t;
  * The BAR 2 Mask register is invisible to host software and not readable from the application.
  * The BAR 2 Mask register is only writable through PEM(0..1)_CFG_WR.
  */
-union cvmx_pcieepx_cfg009_mask
-{
+union cvmx_pcieepx_cfg009_mask {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg009_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg009_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t umask                        : 32; /**< Bar Mask High */
 #else
 	uint32_t umask                        : 32;
@@ -1671,8 +2008,13 @@ union cvmx_pcieepx_cfg009_mask
 	struct cvmx_pcieepx_cfg009_mask_s     cn52xxp1;
 	struct cvmx_pcieepx_cfg009_mask_s     cn56xx;
 	struct cvmx_pcieepx_cfg009_mask_s     cn56xxp1;
+	struct cvmx_pcieepx_cfg009_mask_s     cn61xx;
 	struct cvmx_pcieepx_cfg009_mask_s     cn63xx;
 	struct cvmx_pcieepx_cfg009_mask_s     cn63xxp1;
+	struct cvmx_pcieepx_cfg009_mask_s     cn66xx;
+	struct cvmx_pcieepx_cfg009_mask_s     cn68xx;
+	struct cvmx_pcieepx_cfg009_mask_s     cn68xxp1;
+	struct cvmx_pcieepx_cfg009_mask_s     cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg009_mask cvmx_pcieepx_cfg009_mask_t;
 
@@ -1682,12 +2024,10 @@ typedef union cvmx_pcieepx_cfg009_mask cvmx_pcieepx_cfg009_mask_t;
  * PCIE_CFG010 = Eleventh 32-bits of PCIE type 0 config space (CardBus CIS Pointer Register)
  *
  */
-union cvmx_pcieepx_cfg010
-{
+union cvmx_pcieepx_cfg010 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg010_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg010_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t cisp                         : 32; /**< CardBus CIS Pointer
                                                          Optional, writable through PEM(0..1)_CFG_WR. */
 #else
@@ -1698,8 +2038,13 @@ union cvmx_pcieepx_cfg010
 	struct cvmx_pcieepx_cfg010_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg010_s          cn56xx;
 	struct cvmx_pcieepx_cfg010_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg010_s          cn61xx;
 	struct cvmx_pcieepx_cfg010_s          cn63xx;
 	struct cvmx_pcieepx_cfg010_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg010_s          cn66xx;
+	struct cvmx_pcieepx_cfg010_s          cn68xx;
+	struct cvmx_pcieepx_cfg010_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg010_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg010 cvmx_pcieepx_cfg010_t;
 
@@ -1709,12 +2054,10 @@ typedef union cvmx_pcieepx_cfg010 cvmx_pcieepx_cfg010_t;
  * PCIE_CFG011 = Twelfth 32-bits of PCIE type 0 config space (Subsystem ID and Subsystem Vendor ID Register)
  *
  */
-union cvmx_pcieepx_cfg011
-{
+union cvmx_pcieepx_cfg011 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg011_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg011_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ssid                         : 16; /**< Subsystem ID
                                                          Assigned by PCI-SIG, writable through PEM(0..1)_CFG_WR.                                                                                                           However, the application must not change this field. */
 	uint32_t ssvid                        : 16; /**< Subsystem Vendor ID
@@ -1729,8 +2072,13 @@ union cvmx_pcieepx_cfg011
 	struct cvmx_pcieepx_cfg011_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg011_s          cn56xx;
 	struct cvmx_pcieepx_cfg011_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg011_s          cn61xx;
 	struct cvmx_pcieepx_cfg011_s          cn63xx;
 	struct cvmx_pcieepx_cfg011_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg011_s          cn66xx;
+	struct cvmx_pcieepx_cfg011_s          cn68xx;
+	struct cvmx_pcieepx_cfg011_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg011_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg011 cvmx_pcieepx_cfg011_t;
 
@@ -1740,12 +2088,10 @@ typedef union cvmx_pcieepx_cfg011 cvmx_pcieepx_cfg011_t;
  * PCIE_CFG012 = Thirteenth 32-bits of PCIE type 0 config space (Expansion ROM Base Address Register)
  *
  */
-union cvmx_pcieepx_cfg012
-{
+union cvmx_pcieepx_cfg012 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg012_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg012_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t eraddr                       : 16; /**< Expansion ROM Address */
 	uint32_t reserved_1_15                : 15;
 	uint32_t er_en                        : 1;  /**< Expansion ROM Enable */
@@ -1759,8 +2105,13 @@ union cvmx_pcieepx_cfg012
 	struct cvmx_pcieepx_cfg012_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg012_s          cn56xx;
 	struct cvmx_pcieepx_cfg012_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg012_s          cn61xx;
 	struct cvmx_pcieepx_cfg012_s          cn63xx;
 	struct cvmx_pcieepx_cfg012_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg012_s          cn66xx;
+	struct cvmx_pcieepx_cfg012_s          cn68xx;
+	struct cvmx_pcieepx_cfg012_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg012_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg012 cvmx_pcieepx_cfg012_t;
 
@@ -1771,12 +2122,10 @@ typedef union cvmx_pcieepx_cfg012 cvmx_pcieepx_cfg012_t;
  * The ROM Mask register is invisible to host software and not readable from the application.
  * The ROM Mask register is only writable through PEM(0..1)_CFG_WR.
  */
-union cvmx_pcieepx_cfg012_mask
-{
+union cvmx_pcieepx_cfg012_mask {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg012_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg012_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t mask                         : 31; /**< Bar Mask Low                                                                 NS */
 	uint32_t enb                          : 1;  /**< Bar Enable                                                                   NS
                                                          o 0: BAR ROM is disabled
@@ -1794,8 +2143,13 @@ union cvmx_pcieepx_cfg012_mask
 	struct cvmx_pcieepx_cfg012_mask_s     cn52xxp1;
 	struct cvmx_pcieepx_cfg012_mask_s     cn56xx;
 	struct cvmx_pcieepx_cfg012_mask_s     cn56xxp1;
+	struct cvmx_pcieepx_cfg012_mask_s     cn61xx;
 	struct cvmx_pcieepx_cfg012_mask_s     cn63xx;
 	struct cvmx_pcieepx_cfg012_mask_s     cn63xxp1;
+	struct cvmx_pcieepx_cfg012_mask_s     cn66xx;
+	struct cvmx_pcieepx_cfg012_mask_s     cn68xx;
+	struct cvmx_pcieepx_cfg012_mask_s     cn68xxp1;
+	struct cvmx_pcieepx_cfg012_mask_s     cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg012_mask cvmx_pcieepx_cfg012_mask_t;
 
@@ -1805,12 +2159,10 @@ typedef union cvmx_pcieepx_cfg012_mask cvmx_pcieepx_cfg012_mask_t;
  * PCIE_CFG013 = Fourteenth 32-bits of PCIE type 0 config space (Capability Pointer Register)
  *
  */
-union cvmx_pcieepx_cfg013
-{
+union cvmx_pcieepx_cfg013 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg013_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg013_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_8_31                : 24;
 	uint32_t cp                           : 8;  /**< First Capability Pointer.
                                                          Points to Power Management Capability structure by
@@ -1825,8 +2177,13 @@ union cvmx_pcieepx_cfg013
 	struct cvmx_pcieepx_cfg013_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg013_s          cn56xx;
 	struct cvmx_pcieepx_cfg013_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg013_s          cn61xx;
 	struct cvmx_pcieepx_cfg013_s          cn63xx;
 	struct cvmx_pcieepx_cfg013_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg013_s          cn66xx;
+	struct cvmx_pcieepx_cfg013_s          cn68xx;
+	struct cvmx_pcieepx_cfg013_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg013_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg013 cvmx_pcieepx_cfg013_t;
 
@@ -1836,12 +2193,10 @@ typedef union cvmx_pcieepx_cfg013 cvmx_pcieepx_cfg013_t;
  * PCIE_CFG015 = Sixteenth 32-bits of PCIE type 0 config space (Interrupt Line Register/Interrupt Pin/Bridge Control Register)
  *
  */
-union cvmx_pcieepx_cfg015
-{
+union cvmx_pcieepx_cfg015 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg015_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg015_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ml                           : 8;  /**< Maximum Latency     (Hardwired to 0) */
 	uint32_t mg                           : 8;  /**< Minimum Grant       (Hardwired to 0) */
 	uint32_t inta                         : 8;  /**< Interrupt Pin
@@ -1862,8 +2217,13 @@ union cvmx_pcieepx_cfg015
 	struct cvmx_pcieepx_cfg015_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg015_s          cn56xx;
 	struct cvmx_pcieepx_cfg015_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg015_s          cn61xx;
 	struct cvmx_pcieepx_cfg015_s          cn63xx;
 	struct cvmx_pcieepx_cfg015_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg015_s          cn66xx;
+	struct cvmx_pcieepx_cfg015_s          cn68xx;
+	struct cvmx_pcieepx_cfg015_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg015_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg015 cvmx_pcieepx_cfg015_t;
 
@@ -1875,12 +2235,10 @@ typedef union cvmx_pcieepx_cfg015 cvmx_pcieepx_cfg015_t;
  * Power Management Next Item Pointer/
  * Power Management Capabilities Register)
  */
-union cvmx_pcieepx_cfg016
-{
+union cvmx_pcieepx_cfg016 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg016_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg016_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t pmes                         : 5;  /**< PME_Support
                                                          o Bit 11: If set, PME Messages can be generated from D0
                                                          o Bit 12: If set, PME Messages can be generated from D1
@@ -1923,8 +2281,13 @@ union cvmx_pcieepx_cfg016
 	struct cvmx_pcieepx_cfg016_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg016_s          cn56xx;
 	struct cvmx_pcieepx_cfg016_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg016_s          cn61xx;
 	struct cvmx_pcieepx_cfg016_s          cn63xx;
 	struct cvmx_pcieepx_cfg016_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg016_s          cn66xx;
+	struct cvmx_pcieepx_cfg016_s          cn68xx;
+	struct cvmx_pcieepx_cfg016_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg016_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg016 cvmx_pcieepx_cfg016_t;
 
@@ -1934,12 +2297,10 @@ typedef union cvmx_pcieepx_cfg016 cvmx_pcieepx_cfg016_t;
  * PCIE_CFG017 = Eighteenth 32-bits of PCIE type 0 config space (Power Management Control and Status Register)
  *
  */
-union cvmx_pcieepx_cfg017
-{
+union cvmx_pcieepx_cfg017 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg017_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg017_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t pmdia                        : 8;  /**< Data register for additional information (not supported) */
 	uint32_t bpccee                       : 1;  /**< Bus Power/Clock Control Enable, hardwired to 0 */
 	uint32_t bd3h                         : 1;  /**< B2/B3 Support, hardwired to 0 */
@@ -1982,8 +2343,13 @@ union cvmx_pcieepx_cfg017
 	struct cvmx_pcieepx_cfg017_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg017_s          cn56xx;
 	struct cvmx_pcieepx_cfg017_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg017_s          cn61xx;
 	struct cvmx_pcieepx_cfg017_s          cn63xx;
 	struct cvmx_pcieepx_cfg017_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg017_s          cn66xx;
+	struct cvmx_pcieepx_cfg017_s          cn68xx;
+	struct cvmx_pcieepx_cfg017_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg017_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg017 cvmx_pcieepx_cfg017_t;
 
@@ -1995,13 +2361,12 @@ typedef union cvmx_pcieepx_cfg017 cvmx_pcieepx_cfg017_t;
  *  MSI Next Item Pointer/
  *  MSI Control Register)
  */
-union cvmx_pcieepx_cfg020
-{
+union cvmx_pcieepx_cfg020 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg020_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint32_t reserved_24_31               : 8;
+	struct cvmx_pcieepx_cfg020_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t pvm                          : 1;  /**< Per-vector masking capable */
 	uint32_t m64                          : 1;  /**< 64-bit Address Capable, writable through PEM(0..1)_CFG_WR
                                                          However, the application must not change this field. */
 	uint32_t mme                          : 3;  /**< Multiple Message Enabled
@@ -2024,15 +2389,48 @@ union cvmx_pcieepx_cfg020
 	uint32_t mmc                          : 3;
 	uint32_t mme                          : 3;
 	uint32_t m64                          : 1;
-	uint32_t reserved_24_31               : 8;
+	uint32_t pvm                          : 1;
+	uint32_t reserved_25_31               : 7;
 #endif
 	} s;
-	struct cvmx_pcieepx_cfg020_s          cn52xx;
-	struct cvmx_pcieepx_cfg020_s          cn52xxp1;
-	struct cvmx_pcieepx_cfg020_s          cn56xx;
-	struct cvmx_pcieepx_cfg020_s          cn56xxp1;
-	struct cvmx_pcieepx_cfg020_s          cn63xx;
-	struct cvmx_pcieepx_cfg020_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg020_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t m64                          : 1;  /**< 64-bit Address Capable, writable through PESC(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t mme                          : 3;  /**< Multiple Message Enabled
+                                                         Indicates that multiple Message mode is enabled by system
+                                                         software. The number of Messages enabled must be less than
+                                                         or equal to the Multiple Message Capable value. */
+	uint32_t mmc                          : 3;  /**< Multiple Message Capable, writable through PESC(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t msien                        : 1;  /**< MSI Enabled
+                                                         When set, INTx must be disabled. */
+	uint32_t ncp                          : 8;  /**< Next Capability Pointer
+                                                         Points to PCI Express Capabilities by default,
+                                                         writable through PESC(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t msicid                       : 8;  /**< MSI Capability ID */
+#else
+	uint32_t msicid                       : 8;
+	uint32_t ncp                          : 8;
+	uint32_t msien                        : 1;
+	uint32_t mmc                          : 3;
+	uint32_t mme                          : 3;
+	uint32_t m64                          : 1;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} cn52xx;
+	struct cvmx_pcieepx_cfg020_cn52xx     cn52xxp1;
+	struct cvmx_pcieepx_cfg020_cn52xx     cn56xx;
+	struct cvmx_pcieepx_cfg020_cn52xx     cn56xxp1;
+	struct cvmx_pcieepx_cfg020_s          cn61xx;
+	struct cvmx_pcieepx_cfg020_cn52xx     cn63xx;
+	struct cvmx_pcieepx_cfg020_cn52xx     cn63xxp1;
+	struct cvmx_pcieepx_cfg020_s          cn66xx;
+	struct cvmx_pcieepx_cfg020_s          cn68xx;
+	struct cvmx_pcieepx_cfg020_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg020_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg020 cvmx_pcieepx_cfg020_t;
 
@@ -2042,12 +2440,10 @@ typedef union cvmx_pcieepx_cfg020 cvmx_pcieepx_cfg020_t;
  * PCIE_CFG021 = Twenty-second 32-bits of PCIE type 0 config space (MSI Lower 32 Bits Address Register)
  *
  */
-union cvmx_pcieepx_cfg021
-{
+union cvmx_pcieepx_cfg021 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg021_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg021_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t lmsi                         : 30; /**< Lower 32-bit Address */
 	uint32_t reserved_0_1                 : 2;
 #else
@@ -2059,8 +2455,13 @@ union cvmx_pcieepx_cfg021
 	struct cvmx_pcieepx_cfg021_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg021_s          cn56xx;
 	struct cvmx_pcieepx_cfg021_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg021_s          cn61xx;
 	struct cvmx_pcieepx_cfg021_s          cn63xx;
 	struct cvmx_pcieepx_cfg021_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg021_s          cn66xx;
+	struct cvmx_pcieepx_cfg021_s          cn68xx;
+	struct cvmx_pcieepx_cfg021_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg021_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg021 cvmx_pcieepx_cfg021_t;
 
@@ -2070,12 +2471,10 @@ typedef union cvmx_pcieepx_cfg021 cvmx_pcieepx_cfg021_t;
  * PCIE_CFG022 = Twenty-third 32-bits of PCIE type 0 config space (MSI Upper 32 bits Address Register)
  *
  */
-union cvmx_pcieepx_cfg022
-{
+union cvmx_pcieepx_cfg022 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg022_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg022_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t umsi                         : 32; /**< Upper 32-bit Address */
 #else
 	uint32_t umsi                         : 32;
@@ -2085,8 +2484,13 @@ union cvmx_pcieepx_cfg022
 	struct cvmx_pcieepx_cfg022_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg022_s          cn56xx;
 	struct cvmx_pcieepx_cfg022_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg022_s          cn61xx;
 	struct cvmx_pcieepx_cfg022_s          cn63xx;
 	struct cvmx_pcieepx_cfg022_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg022_s          cn66xx;
+	struct cvmx_pcieepx_cfg022_s          cn68xx;
+	struct cvmx_pcieepx_cfg022_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg022_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg022 cvmx_pcieepx_cfg022_t;
 
@@ -2096,12 +2500,10 @@ typedef union cvmx_pcieepx_cfg022 cvmx_pcieepx_cfg022_t;
  * PCIE_CFG023 = Twenty-fourth 32-bits of PCIE type 0 config space (MSI Data Register)
  *
  */
-union cvmx_pcieepx_cfg023
-{
+union cvmx_pcieepx_cfg023 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg023_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg023_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_16_31               : 16;
 	uint32_t msimd                        : 16; /**< MSI Data
                                                          Pattern assigned by system software, bits [4:0] are Or-ed with
@@ -2115,8 +2517,13 @@ union cvmx_pcieepx_cfg023
 	struct cvmx_pcieepx_cfg023_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg023_s          cn56xx;
 	struct cvmx_pcieepx_cfg023_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg023_s          cn61xx;
 	struct cvmx_pcieepx_cfg023_s          cn63xx;
 	struct cvmx_pcieepx_cfg023_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg023_s          cn66xx;
+	struct cvmx_pcieepx_cfg023_s          cn68xx;
+	struct cvmx_pcieepx_cfg023_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg023_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg023 cvmx_pcieepx_cfg023_t;
 
@@ -2127,12 +2534,10 @@ typedef union cvmx_pcieepx_cfg023 cvmx_pcieepx_cfg023_t;
  * (PCI Express Capabilities List Register/
  *  PCI Express Capabilities Register)
  */
-union cvmx_pcieepx_cfg028
-{
+union cvmx_pcieepx_cfg028 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg028_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg028_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_30_31               : 2;
 	uint32_t imn                          : 5;  /**< Interrupt Message Number
                                                          Updated by hardware, writable through PEM(0..1)_CFG_WR.
@@ -2145,7 +2550,7 @@ union cvmx_pcieepx_cfg028
 	uint32_t dpt                          : 4;  /**< Device Port Type */
 	uint32_t pciecv                       : 4;  /**< PCI Express Capability Version */
 	uint32_t ncp                          : 8;  /**< Next Capability Pointer
-                                                         Writable through PEM(0..1)_CFG_WR.
+                                                         writable through PEM(0..1)_CFG_WR.
                                                          However, the application must not change this field. */
 	uint32_t pcieid                       : 8;  /**< PCIE Capability ID */
 #else
@@ -2162,8 +2567,13 @@ union cvmx_pcieepx_cfg028
 	struct cvmx_pcieepx_cfg028_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg028_s          cn56xx;
 	struct cvmx_pcieepx_cfg028_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg028_s          cn61xx;
 	struct cvmx_pcieepx_cfg028_s          cn63xx;
 	struct cvmx_pcieepx_cfg028_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg028_s          cn66xx;
+	struct cvmx_pcieepx_cfg028_s          cn68xx;
+	struct cvmx_pcieepx_cfg028_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg028_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg028 cvmx_pcieepx_cfg028_t;
 
@@ -2173,12 +2583,10 @@ typedef union cvmx_pcieepx_cfg028 cvmx_pcieepx_cfg028_t;
  * PCIE_CFG029 = Thirtieth 32-bits of PCIE type 0 config space (Device Capabilities Register)
  *
  */
-union cvmx_pcieepx_cfg029
-{
+union cvmx_pcieepx_cfg029 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg029_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg029_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_28_31               : 4;
 	uint32_t cspls                        : 2;  /**< Captured Slot Power Limit Scale
                                                          From Message from RC, upstream port only. */
@@ -2221,8 +2629,97 @@ union cvmx_pcieepx_cfg029
 	struct cvmx_pcieepx_cfg029_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg029_s          cn56xx;
 	struct cvmx_pcieepx_cfg029_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg029_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_29_31               : 3;
+	uint32_t flr_cap                      : 1;  /**< Function Level Reset Capable
+                                                         not supported */
+	uint32_t cspls                        : 2;  /**< Captured Slot Power Limit Scale
+                                                         From Message from RC, upstream port only. */
+	uint32_t csplv                        : 8;  /**< Captured Slot Power Limit Value
+                                                         From Message from RC, upstream port only. */
+	uint32_t reserved_16_17               : 2;
+	uint32_t rber                         : 1;  /**< Role-Based Error Reporting, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t reserved_12_14               : 3;
+	uint32_t el1al                        : 3;  /**< Endpoint L1 Acceptable Latency, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t el0al                        : 3;  /**< Endpoint L0s Acceptable Latency, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t etfs                         : 1;  /**< Extended Tag Field Supported
+                                                         This bit is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application
+                                                         must not write a 1 to this bit. */
+	uint32_t pfs                          : 2;  /**< Phantom Function Supported
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, Phantom
+                                                         Function is not supported. Therefore, the application must not
+                                                         write any value other than 0x0 to this field. */
+	uint32_t mpss                         : 3;  /**< Max_Payload_Size Supported, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+#else
+	uint32_t mpss                         : 3;
+	uint32_t pfs                          : 2;
+	uint32_t etfs                         : 1;
+	uint32_t el0al                        : 3;
+	uint32_t el1al                        : 3;
+	uint32_t reserved_12_14               : 3;
+	uint32_t rber                         : 1;
+	uint32_t reserved_16_17               : 2;
+	uint32_t csplv                        : 8;
+	uint32_t cspls                        : 2;
+	uint32_t flr_cap                      : 1;
+	uint32_t reserved_29_31               : 3;
+#endif
+	} cn61xx;
 	struct cvmx_pcieepx_cfg029_s          cn63xx;
 	struct cvmx_pcieepx_cfg029_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg029_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_29_31               : 3;
+	uint32_t flr                          : 1;  /**< Function Level Reset Capability
+                                                         When set, core support of SR-IOV */
+	uint32_t cspls                        : 2;  /**< Captured Slot Power Limit Scale
+                                                         From Message from RC, upstream port only. */
+	uint32_t csplv                        : 8;  /**< Captured Slot Power Limit Value
+                                                         From Message from RC, upstream port only. */
+	uint32_t reserved_16_17               : 2;
+	uint32_t rber                         : 1;  /**< Role-Based Error Reporting, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t reserved_12_14               : 3;
+	uint32_t el1al                        : 3;  /**< Endpoint L1 Acceptable Latency, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t el0al                        : 3;  /**< Endpoint L0s Acceptable Latency, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t etfs                         : 1;  /**< Extended Tag Field Supported
+                                                         This bit is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application
+                                                         must not write a 1 to this bit. */
+	uint32_t pfs                          : 2;  /**< Phantom Function Supported
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, Phantom
+                                                         Function is not supported. Therefore, the application must not
+                                                         write any value other than 0x0 to this field. */
+	uint32_t mpss                         : 3;  /**< Max_Payload_Size Supported, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+#else
+	uint32_t mpss                         : 3;
+	uint32_t pfs                          : 2;
+	uint32_t etfs                         : 1;
+	uint32_t el0al                        : 3;
+	uint32_t el1al                        : 3;
+	uint32_t reserved_12_14               : 3;
+	uint32_t rber                         : 1;
+	uint32_t reserved_16_17               : 2;
+	uint32_t csplv                        : 8;
+	uint32_t cspls                        : 2;
+	uint32_t flr                          : 1;
+	uint32_t reserved_29_31               : 3;
+#endif
+	} cn66xx;
+	struct cvmx_pcieepx_cfg029_cn66xx     cn68xx;
+	struct cvmx_pcieepx_cfg029_cn66xx     cn68xxp1;
+	struct cvmx_pcieepx_cfg029_cn61xx     cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg029 cvmx_pcieepx_cfg029_t;
 
@@ -2232,12 +2729,10 @@ typedef union cvmx_pcieepx_cfg029 cvmx_pcieepx_cfg029_t;
  * PCIE_CFG030 = Thirty-first 32-bits of PCIE type 0 config space
  * (Device Control Register/Device Status Register)
  */
-union cvmx_pcieepx_cfg030
-{
+union cvmx_pcieepx_cfg030 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg030_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg030_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_22_31               : 10;
 	uint32_t tp                           : 1;  /**< Transaction Pending
                                                          Set to 1 when Non-Posted Requests are not yet completed
@@ -2273,7 +2768,8 @@ union cvmx_pcieepx_cfg030
                                                          set to Nonfatal and meets the Advisory Nonfatal criteria,
                                                          which most ECRC errors
                                                          should be. */
-	uint32_t reserved_15_15               : 1;
+	uint32_t i_flr                        : 1;  /**< Initiate Function Level Reset
+                                                         (Not Supported) */
 	uint32_t mrrs                         : 3;  /**< Max Read Request Size
                                                           0 = 128B
                                                           1 = 256B
@@ -2300,6 +2796,97 @@ union cvmx_pcieepx_cfg030
                                                           Larger sizes not supported by OCTEON.
                                                          Note: DPI_SLI_PRT#_CFG[MPS] must be set to the same
                                                                value for proper functionality. */
+	uint32_t ro_en                        : 1;  /**< Enable Relaxed Ordering
+                                                         This bit is not used. */
+	uint32_t ur_en                        : 1;  /**< Unsupported Request Reporting Enable */
+	uint32_t fe_en                        : 1;  /**< Fatal Error Reporting Enable */
+	uint32_t nfe_en                       : 1;  /**< Non-Fatal Error Reporting Enable */
+	uint32_t ce_en                        : 1;  /**< Correctable Error Reporting Enable */
+#else
+	uint32_t ce_en                        : 1;
+	uint32_t nfe_en                       : 1;
+	uint32_t fe_en                        : 1;
+	uint32_t ur_en                        : 1;
+	uint32_t ro_en                        : 1;
+	uint32_t mps                          : 3;
+	uint32_t etf_en                       : 1;
+	uint32_t pf_en                        : 1;
+	uint32_t ap_en                        : 1;
+	uint32_t ns_en                        : 1;
+	uint32_t mrrs                         : 3;
+	uint32_t i_flr                        : 1;
+	uint32_t ce_d                         : 1;
+	uint32_t nfe_d                        : 1;
+	uint32_t fe_d                         : 1;
+	uint32_t ur_d                         : 1;
+	uint32_t ap_d                         : 1;
+	uint32_t tp                           : 1;
+	uint32_t reserved_22_31               : 10;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg030_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_22_31               : 10;
+	uint32_t tp                           : 1;  /**< Transaction Pending
+                                                         Set to 1 when Non-Posted Requests are not yet completed
+                                                         and clear when they are completed. */
+	uint32_t ap_d                         : 1;  /**< Aux Power Detected
+                                                         Set to 1 if Aux power detected. */
+	uint32_t ur_d                         : 1;  /**< Unsupported Request Detected
+                                                          Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         UR_D occurs when we receive something we don't support.
+                                                         Unsupported requests are Nonfatal errors, so UR_D should
+                                                         cause NFE_D.  Receiving a  vendor defined message should
+                                                         cause an unsupported request. */
+	uint32_t fe_d                         : 1;  /**< Fatal Error Detected
+                                                          Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         FE_D is set if receive any of the errors in PCIE_CFG066 that
+                                                         has a severity set to Fatal.  Malformed TLP's generally fit
+                                                         into this category. */
+	uint32_t nfe_d                        : 1;  /**< Non-Fatal Error detected
+                                                          Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         NFE_D is set if we receive any of the errors in PCIE_CFG066
+                                                         that has a severity set to Nonfatal and does NOT meet Advisory
+                                                         Nonfatal criteria (PCIe 1.1 spec, Section 6.2.3.2.4), which
+                                                         most poisoned TLP's should be. */
+	uint32_t ce_d                         : 1;  /**< Correctable Error Detected
+                                                          Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         CE_D is set if we receive any of the errors in PCIE_CFG068
+                                                         for example a Replay Timer Timeout.  Also, it can be set if
+                                                         we get any of the errors in PCIE_CFG066 that has a severity
+                                                         set to Nonfatal and meets the Advisory Nonfatal criteria
+                                                         (PCIe 1.1 spec, Section 6.2.3.2.4), which most ECRC errors
+                                                         should be. */
+	uint32_t reserved_15_15               : 1;
+	uint32_t mrrs                         : 3;  /**< Max Read Request Size
+                                                          0 = 128B
+                                                          1 = 256B
+                                                          2 = 512B
+                                                          3 = 1024B
+                                                          4 = 2048B
+                                                          5 = 4096B
+                                                         Note: NPEI_CTL_STATUS2[MRRS] also must be set properly.
+                                                         NPEI_CTL_STATUS2[MRRS] must not exceed the
+                                                         desired max read request size. */
+	uint32_t ns_en                        : 1;  /**< Enable No Snoop */
+	uint32_t ap_en                        : 1;  /**< AUX Power PM Enable */
+	uint32_t pf_en                        : 1;  /**< Phantom Function Enable
+                                                         This bit should never be set - OCTEON requests never use
+                                                         phantom functions. */
+	uint32_t etf_en                       : 1;  /**< Extended Tag Field Enable
+                                                         This bit should never be set - OCTEON requests never use
+                                                         extended tags. */
+	uint32_t mps                          : 3;  /**< Max Payload Size
+                                                          Legal values:
+                                                           0  = 128B
+                                                           1  = 256B
+                                                          Larger sizes not supported by OCTEON.
+                                                         Note: NPEI_CTL_STATUS2[MPS] must be set to the same
+                                                               value for proper functionality. */
 	uint32_t ro_en                        : 1;  /**< Enable Relaxed Ordering */
 	uint32_t ur_en                        : 1;  /**< Unsupported Request Reporting Enable */
 	uint32_t fe_en                        : 1;  /**< Fatal Error Reporting Enable */
@@ -2326,13 +2913,17 @@ union cvmx_pcieepx_cfg030
 	uint32_t tp                           : 1;
 	uint32_t reserved_22_31               : 10;
 #endif
-	} s;
-	struct cvmx_pcieepx_cfg030_s          cn52xx;
-	struct cvmx_pcieepx_cfg030_s          cn52xxp1;
-	struct cvmx_pcieepx_cfg030_s          cn56xx;
-	struct cvmx_pcieepx_cfg030_s          cn56xxp1;
-	struct cvmx_pcieepx_cfg030_s          cn63xx;
-	struct cvmx_pcieepx_cfg030_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pcieepx_cfg030_cn52xx     cn52xxp1;
+	struct cvmx_pcieepx_cfg030_cn52xx     cn56xx;
+	struct cvmx_pcieepx_cfg030_cn52xx     cn56xxp1;
+	struct cvmx_pcieepx_cfg030_s          cn61xx;
+	struct cvmx_pcieepx_cfg030_cn52xx     cn63xx;
+	struct cvmx_pcieepx_cfg030_cn52xx     cn63xxp1;
+	struct cvmx_pcieepx_cfg030_s          cn66xx;
+	struct cvmx_pcieepx_cfg030_s          cn68xx;
+	struct cvmx_pcieepx_cfg030_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg030_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg030 cvmx_pcieepx_cfg030_t;
 
@@ -2342,16 +2933,17 @@ typedef union cvmx_pcieepx_cfg030 cvmx_pcieepx_cfg030_t;
  * PCIE_CFG031 = Thirty-second 32-bits of PCIE type 0 config space
  * (Link Capabilities Register)
  */
-union cvmx_pcieepx_cfg031
-{
+union cvmx_pcieepx_cfg031 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg031_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint32_t pnum                         : 8;  /**< Port Number, writable through PEM(0..1)_CFG_WR
-                                                         However, the application must not change this field. */
-	uint32_t reserved_22_23               : 2;
-	uint32_t lbnc                         : 1;  /**< Link Bandwith Notification Capability */
+	struct cvmx_pcieepx_cfg031_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t pnum                         : 8;  /**< Port Number
+                                                         writable through PEM(0..1)_CFG_WR, however the application
+                                                         must not change this field. */
+	uint32_t reserved_23_23               : 1;
+	uint32_t aspm                         : 1;  /**< ASPM Optionality Compliance */
+	uint32_t lbnc                         : 1;  /**< Link Bandwidth Notification Capability
+                                                         Set 0 for Endpoint devices. */
 	uint32_t dllarc                       : 1;  /**< Data Link Layer Active Reporting Capable */
 	uint32_t sderc                        : 1;  /**< Surprise Down Error Reporting Capable
                                                          Not supported, hardwired to 0x0. */
@@ -2373,11 +2965,14 @@ union cvmx_pcieepx_cfg031
                                                          However, the application must not change this field. */
 	uint32_t mlw                          : 6;  /**< Maximum Link Width
                                                          The default value is the value you specify during hardware
-                                                         configuration (x1, x4, x8, or x16), writable through PEM(0..1)_CFG_WR. */
+                                                         configuration (x1), writable through PEM(0..1)_CFG_WR
+                                                         however wider cofigurations are not supported. */
 	uint32_t mls                          : 4;  /**< Maximum Link Speed
-                                                         The following values are accepted:
-                                                         0001b: 2.5 GHz supported
-                                                         0010b: 5.0 GHz and 2.5 GHz supported
+                                                         The reset value of this field is controlled by a value sent from
+                                                         the lsb of the MIO_QLM#_SPD register.
+                                                         qlm#_spd[1]   RST_VALUE   NOTE
+                                                         1             0001b       2.5 GHz supported
+                                                         0             0010b       5.0 GHz and 2.5 GHz supported
                                                          This field is writable through PEM(0..1)_CFG_WR.
                                                          However, the application must not change this field. */
 #else
@@ -2390,16 +2985,71 @@ union cvmx_pcieepx_cfg031
 	uint32_t sderc                        : 1;
 	uint32_t dllarc                       : 1;
 	uint32_t lbnc                         : 1;
-	uint32_t reserved_22_23               : 2;
+	uint32_t aspm                         : 1;
+	uint32_t reserved_23_23               : 1;
 	uint32_t pnum                         : 8;
 #endif
 	} s;
-	struct cvmx_pcieepx_cfg031_s          cn52xx;
-	struct cvmx_pcieepx_cfg031_s          cn52xxp1;
-	struct cvmx_pcieepx_cfg031_s          cn56xx;
-	struct cvmx_pcieepx_cfg031_s          cn56xxp1;
-	struct cvmx_pcieepx_cfg031_s          cn63xx;
-	struct cvmx_pcieepx_cfg031_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg031_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t pnum                         : 8;  /**< Port Number, writable through PESC(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t reserved_22_23               : 2;
+	uint32_t lbnc                         : 1;  /**< Link Bandwith Notification Capability */
+	uint32_t dllarc                       : 1;  /**< Data Link Layer Active Reporting Capable */
+	uint32_t sderc                        : 1;  /**< Surprise Down Error Reporting Capable
+                                                         Not supported, hardwired to 0x0. */
+	uint32_t cpm                          : 1;  /**< Clock Power Management
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through PESC(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t l1el                         : 3;  /**< L1 Exit Latency
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through PESC(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t l0el                         : 3;  /**< L0s Exit Latency
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through PESC(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t aslpms                       : 2;  /**< Active State Link PM Support
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through PESC(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t mlw                          : 6;  /**< Maximum Link Width
+                                                         The default value is the value you specify during hardware
+                                                         configuration (x1, x2, x4, x8, or x16), writable through PESC(0..1)_CFG_WR.
+                                                         This value will be set to 0x4 or 0x2 depending on the max
+                                                         number of lanes (QLM_CFG == 0 set to 0x2 else 0x4). */
+	uint32_t mls                          : 4;  /**< Maximum Link Speed
+                                                         Default value is 0x1 for 2.5 Gbps Link.
+                                                         This field is writable through PESC(0..1)_CFG_WR.
+                                                         However, 0x1 is the
+                                                         only supported value. Therefore, the application must not write
+                                                         any value other than 0x1 to this field. */
+#else
+	uint32_t mls                          : 4;
+	uint32_t mlw                          : 6;
+	uint32_t aslpms                       : 2;
+	uint32_t l0el                         : 3;
+	uint32_t l1el                         : 3;
+	uint32_t cpm                          : 1;
+	uint32_t sderc                        : 1;
+	uint32_t dllarc                       : 1;
+	uint32_t lbnc                         : 1;
+	uint32_t reserved_22_23               : 2;
+	uint32_t pnum                         : 8;
+#endif
+	} cn52xx;
+	struct cvmx_pcieepx_cfg031_cn52xx     cn52xxp1;
+	struct cvmx_pcieepx_cfg031_cn52xx     cn56xx;
+	struct cvmx_pcieepx_cfg031_cn52xx     cn56xxp1;
+	struct cvmx_pcieepx_cfg031_s          cn61xx;
+	struct cvmx_pcieepx_cfg031_cn52xx     cn63xx;
+	struct cvmx_pcieepx_cfg031_cn52xx     cn63xxp1;
+	struct cvmx_pcieepx_cfg031_s          cn66xx;
+	struct cvmx_pcieepx_cfg031_s          cn68xx;
+	struct cvmx_pcieepx_cfg031_cn52xx     cn68xxp1;
+	struct cvmx_pcieepx_cfg031_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg031 cvmx_pcieepx_cfg031_t;
 
@@ -2409,13 +3059,12 @@ typedef union cvmx_pcieepx_cfg031 cvmx_pcieepx_cfg031_t;
  * PCIE_CFG032 = Thirty-third 32-bits of PCIE type 0 config space
  * (Link Control Register/Link Status Register)
  */
-union cvmx_pcieepx_cfg032
-{
+union cvmx_pcieepx_cfg032 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg032_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint32_t reserved_30_31               : 2;
+	struct cvmx_pcieepx_cfg032_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t lab                          : 1;  /**< Link Autonomous Bandwidth Status */
+	uint32_t lbm                          : 1;  /**< Link Bandwidth Management Status */
 	uint32_t dlla                         : 1;  /**< Data Link Layer Active
                                                          Not applicable for an upstream Port or Endpoint device,
                                                          hardwired to 0. */
@@ -2429,6 +3078,72 @@ union cvmx_pcieepx_cfg032
                                                          hardwired to 0. */
 	uint32_t reserved_26_26               : 1;
 	uint32_t nlw                          : 6;  /**< Negotiated Link Width
+                                                         Set automatically by hardware after Link initialization.
+                                                         Value is undefined when link is not up. */
+	uint32_t ls                           : 4;  /**< Link Speed
+                                                         1 == The negotiated Link speed: 2.5 Gbps
+                                                         2 == The negotiated Link speed: 5.0 Gbps
+                                                         4 == The negotiated Link speed: 8.0 Gbps (Not Supported) */
+	uint32_t reserved_12_15               : 4;
+	uint32_t lab_int_enb                  : 1;  /**< Link Autonomous Bandwidth Interrupt Enable
+                                                         This bit is not applicable and is reserved for endpoints */
+	uint32_t lbm_int_enb                  : 1;  /**< Link Bandwidth Management Interrupt Enable
+                                                         This bit is not applicable and is reserved for endpoints */
+	uint32_t hawd                         : 1;  /**< Hardware Autonomous Width Disable
+                                                         (Not Supported) */
+	uint32_t ecpm                         : 1;  /**< Enable Clock Power Management
+                                                         Hardwired to 0 if Clock Power Management is disabled in
+                                                         the Link Capabilities register. */
+	uint32_t es                           : 1;  /**< Extended Synch */
+	uint32_t ccc                          : 1;  /**< Common Clock Configuration */
+	uint32_t rl                           : 1;  /**< Retrain Link
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+	uint32_t ld                           : 1;  /**< Link Disable
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+	uint32_t rcb                          : 1;  /**< Read Completion Boundary (RCB) */
+	uint32_t reserved_2_2                 : 1;
+	uint32_t aslpc                        : 2;  /**< Active State Link PM Control */
+#else
+	uint32_t aslpc                        : 2;
+	uint32_t reserved_2_2                 : 1;
+	uint32_t rcb                          : 1;
+	uint32_t ld                           : 1;
+	uint32_t rl                           : 1;
+	uint32_t ccc                          : 1;
+	uint32_t es                           : 1;
+	uint32_t ecpm                         : 1;
+	uint32_t hawd                         : 1;
+	uint32_t lbm_int_enb                  : 1;
+	uint32_t lab_int_enb                  : 1;
+	uint32_t reserved_12_15               : 4;
+	uint32_t ls                           : 4;
+	uint32_t nlw                          : 6;
+	uint32_t reserved_26_26               : 1;
+	uint32_t lt                           : 1;
+	uint32_t scc                          : 1;
+	uint32_t dlla                         : 1;
+	uint32_t lbm                          : 1;
+	uint32_t lab                          : 1;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg032_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_30_31               : 2;
+	uint32_t dlla                         : 1;  /**< Data Link Layer Active
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+	uint32_t scc                          : 1;  /**< Slot Clock Configuration
+                                                         Indicates that the component uses the same physical reference
+                                                         clock that the platform provides on the connector.
+                                                         Writable through PESC(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t lt                           : 1;  /**< Link Training
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+	uint32_t reserved_26_26               : 1;
+	uint32_t nlw                          : 6;  /**< Negotiated Link Width
                                                          Set automatically by hardware after Link initialization. */
 	uint32_t ls                           : 4;  /**< Link Speed
                                                          The negotiated Link speed: 2.5 Gbps */
@@ -2468,13 +3183,80 @@ union cvmx_pcieepx_cfg032
 	uint32_t dlla                         : 1;
 	uint32_t reserved_30_31               : 2;
 #endif
-	} s;
-	struct cvmx_pcieepx_cfg032_s          cn52xx;
-	struct cvmx_pcieepx_cfg032_s          cn52xxp1;
-	struct cvmx_pcieepx_cfg032_s          cn56xx;
-	struct cvmx_pcieepx_cfg032_s          cn56xxp1;
-	struct cvmx_pcieepx_cfg032_s          cn63xx;
-	struct cvmx_pcieepx_cfg032_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pcieepx_cfg032_cn52xx     cn52xxp1;
+	struct cvmx_pcieepx_cfg032_cn52xx     cn56xx;
+	struct cvmx_pcieepx_cfg032_cn52xx     cn56xxp1;
+	struct cvmx_pcieepx_cfg032_s          cn61xx;
+	struct cvmx_pcieepx_cfg032_cn52xx     cn63xx;
+	struct cvmx_pcieepx_cfg032_cn52xx     cn63xxp1;
+	struct cvmx_pcieepx_cfg032_s          cn66xx;
+	struct cvmx_pcieepx_cfg032_s          cn68xx;
+	struct cvmx_pcieepx_cfg032_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_30_31               : 2;
+	uint32_t dlla                         : 1;  /**< Data Link Layer Active
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+	uint32_t scc                          : 1;  /**< Slot Clock Configuration
+                                                         Indicates that the component uses the same physical reference
+                                                         clock that the platform provides on the connector.
+                                                         Writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t lt                           : 1;  /**< Link Training
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+	uint32_t reserved_26_26               : 1;
+	uint32_t nlw                          : 6;  /**< Negotiated Link Width
+                                                         Set automatically by hardware after Link initialization. */
+	uint32_t ls                           : 4;  /**< Link Speed
+                                                         1 == The negotiated Link speed: 2.5 Gbps
+                                                         2 == The negotiated Link speed: 5.0 Gbps
+                                                         4 == The negotiated Link speed: 8.0 Gbps (Not Supported) */
+	uint32_t reserved_12_15               : 4;
+	uint32_t lab_int_enb                  : 1;  /**< Link Autonomous Bandwidth Interrupt Enable
+                                                         This bit is not applicable and is reserved for endpoints */
+	uint32_t lbm_int_enb                  : 1;  /**< Link Bandwidth Management Interrupt Enable
+                                                         This bit is not applicable and is reserved for endpoints */
+	uint32_t hawd                         : 1;  /**< Hardware Autonomous Width Disable
+                                                         (Not Supported) */
+	uint32_t ecpm                         : 1;  /**< Enable Clock Power Management
+                                                         Hardwired to 0 if Clock Power Management is disabled in
+                                                         the Link Capabilities register. */
+	uint32_t es                           : 1;  /**< Extended Synch */
+	uint32_t ccc                          : 1;  /**< Common Clock Configuration */
+	uint32_t rl                           : 1;  /**< Retrain Link
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+	uint32_t ld                           : 1;  /**< Link Disable
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+	uint32_t rcb                          : 1;  /**< Read Completion Boundary (RCB) */
+	uint32_t reserved_2_2                 : 1;
+	uint32_t aslpc                        : 2;  /**< Active State Link PM Control */
+#else
+	uint32_t aslpc                        : 2;
+	uint32_t reserved_2_2                 : 1;
+	uint32_t rcb                          : 1;
+	uint32_t ld                           : 1;
+	uint32_t rl                           : 1;
+	uint32_t ccc                          : 1;
+	uint32_t es                           : 1;
+	uint32_t ecpm                         : 1;
+	uint32_t hawd                         : 1;
+	uint32_t lbm_int_enb                  : 1;
+	uint32_t lab_int_enb                  : 1;
+	uint32_t reserved_12_15               : 4;
+	uint32_t ls                           : 4;
+	uint32_t nlw                          : 6;
+	uint32_t reserved_26_26               : 1;
+	uint32_t lt                           : 1;
+	uint32_t scc                          : 1;
+	uint32_t dlla                         : 1;
+	uint32_t reserved_30_31               : 2;
+#endif
+	} cn68xxp1;
+	struct cvmx_pcieepx_cfg032_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg032 cvmx_pcieepx_cfg032_t;
 
@@ -2484,12 +3266,10 @@ typedef union cvmx_pcieepx_cfg032 cvmx_pcieepx_cfg032_t;
  * PCIE_CFG033 = Thirty-fourth 32-bits of PCIE type 0 config space
  * (Slot Capabilities Register)
  */
-union cvmx_pcieepx_cfg033
-{
+union cvmx_pcieepx_cfg033 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg033_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg033_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ps_num                       : 13; /**< Physical Slot Number, writable through PEM(0..1)_CFG_WR
                                                          However, the application must not change this field. */
 	uint32_t nccs                         : 1;  /**< No Command Complete Support, writable through PEM(0..1)_CFG_WR
@@ -2544,12 +3324,10 @@ typedef union cvmx_pcieepx_cfg033 cvmx_pcieepx_cfg033_t;
  * PCIE_CFG034 = Thirty-fifth 32-bits of PCIE type 0 config space
  * (Slot Control Register/Slot Status Register)
  */
-union cvmx_pcieepx_cfg034
-{
+union cvmx_pcieepx_cfg034 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg034_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg034_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_25_31               : 7;
 	uint32_t dlls_c                       : 1;  /**< Data Link Layer State Changed
                                                          Not applicable for an upstream Port or Endpoint device,
@@ -2616,12 +3394,47 @@ typedef union cvmx_pcieepx_cfg034 cvmx_pcieepx_cfg034_t;
  * PCIE_CFG037 = Thirty-eighth 32-bits of PCIE type 0 config space
  * (Device Capabilities 2 Register)
  */
-union cvmx_pcieepx_cfg037
-{
+union cvmx_pcieepx_cfg037 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg037_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg037_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t obffs                        : 2;  /**< Optimized Buffer Flush Fill (OBFF) Supported
+                                                         (Not Supported) */
+	uint32_t reserved_12_17               : 6;
+	uint32_t ltrs                         : 1;  /**< Latency Tolerance Reporting (LTR) Mechanism Supported
+                                                         (Not Supported) */
+	uint32_t noroprpr                     : 1;  /**< No RO-enabled PR-PR Passing
+                                                         (This bit applies to RCs) */
+	uint32_t atom128s                     : 1;  /**< 128-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom64s                      : 1;  /**< 64-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom32s                      : 1;  /**< 32-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom_ops                     : 1;  /**< AtomicOp Routing Supported
+                                                         (Not Applicable for EP) */
+	uint32_t ari                          : 1;  /**< Alternate Routing ID Forwarding Supported
+                                                         (Not Supported) */
+	uint32_t ctds                         : 1;  /**< Completion Timeout Disable Supported */
+	uint32_t ctrs                         : 4;  /**< Completion Timeout Ranges Supported */
+#else
+	uint32_t ctrs                         : 4;
+	uint32_t ctds                         : 1;
+	uint32_t ari                          : 1;
+	uint32_t atom_ops                     : 1;
+	uint32_t atom32s                      : 1;
+	uint32_t atom64s                      : 1;
+	uint32_t atom128s                     : 1;
+	uint32_t noroprpr                     : 1;
+	uint32_t ltrs                         : 1;
+	uint32_t reserved_12_17               : 6;
+	uint32_t obffs                        : 2;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg037_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_5_31                : 27;
 	uint32_t ctds                         : 1;  /**< Completion Timeout Disable Supported */
 	uint32_t ctrs                         : 4;  /**< Completion Timeout Ranges Supported
@@ -2633,13 +3446,89 @@ union cvmx_pcieepx_cfg037
 	uint32_t ctds                         : 1;
 	uint32_t reserved_5_31                : 27;
 #endif
-	} s;
-	struct cvmx_pcieepx_cfg037_s          cn52xx;
-	struct cvmx_pcieepx_cfg037_s          cn52xxp1;
-	struct cvmx_pcieepx_cfg037_s          cn56xx;
-	struct cvmx_pcieepx_cfg037_s          cn56xxp1;
-	struct cvmx_pcieepx_cfg037_s          cn63xx;
-	struct cvmx_pcieepx_cfg037_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pcieepx_cfg037_cn52xx     cn52xxp1;
+	struct cvmx_pcieepx_cfg037_cn52xx     cn56xx;
+	struct cvmx_pcieepx_cfg037_cn52xx     cn56xxp1;
+	struct cvmx_pcieepx_cfg037_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_14_31               : 18;
+	uint32_t tph                          : 2;  /**< TPH Completer Supported
+                                                         (Not Supported) */
+	uint32_t reserved_11_11               : 1;
+	uint32_t noroprpr                     : 1;  /**< No RO-enabled PR-PR Passing
+                                                         (This bit applies to RCs) */
+	uint32_t atom128s                     : 1;  /**< 128-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom64s                      : 1;  /**< 64-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom32s                      : 1;  /**< 32-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom_ops                     : 1;  /**< AtomicOp Routing Supported
+                                                         (Not Applicable for EP) */
+	uint32_t ari                          : 1;  /**< Alternate Routing ID Forwarding Supported
+                                                         (Not Supported) */
+	uint32_t ctds                         : 1;  /**< Completion Timeout Disable Supported */
+	uint32_t ctrs                         : 4;  /**< Completion Timeout Ranges Supported */
+#else
+	uint32_t ctrs                         : 4;
+	uint32_t ctds                         : 1;
+	uint32_t ari                          : 1;
+	uint32_t atom_ops                     : 1;
+	uint32_t atom32s                      : 1;
+	uint32_t atom64s                      : 1;
+	uint32_t atom128s                     : 1;
+	uint32_t noroprpr                     : 1;
+	uint32_t reserved_11_11               : 1;
+	uint32_t tph                          : 2;
+	uint32_t reserved_14_31               : 18;
+#endif
+	} cn61xx;
+	struct cvmx_pcieepx_cfg037_cn52xx     cn63xx;
+	struct cvmx_pcieepx_cfg037_cn52xx     cn63xxp1;
+	struct cvmx_pcieepx_cfg037_cn61xx     cn66xx;
+	struct cvmx_pcieepx_cfg037_cn61xx     cn68xx;
+	struct cvmx_pcieepx_cfg037_cn61xx     cn68xxp1;
+	struct cvmx_pcieepx_cfg037_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t obffs                        : 2;  /**< Optimized Buffer Flush Fill (OBFF) Supported
+                                                         (Not Supported) */
+	uint32_t reserved_14_17               : 4;
+	uint32_t tphs                         : 2;  /**< TPH Completer Supported
+                                                         (Not Supported) */
+	uint32_t ltrs                         : 1;  /**< Latency Tolerance Reporting (LTR) Mechanism Supported
+                                                         (Not Supported) */
+	uint32_t noroprpr                     : 1;  /**< No RO-enabled PR-PR Passing
+                                                         (This bit applies to RCs) */
+	uint32_t atom128s                     : 1;  /**< 128-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom64s                      : 1;  /**< 64-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom32s                      : 1;  /**< 32-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom_ops                     : 1;  /**< AtomicOp Routing Supported
+                                                         (Not Applicable for EP) */
+	uint32_t ari                          : 1;  /**< Alternate Routing ID Forwarding Supported
+                                                         (Not Supported) */
+	uint32_t ctds                         : 1;  /**< Completion Timeout Disable Supported */
+	uint32_t ctrs                         : 4;  /**< Completion Timeout Ranges Supported */
+#else
+	uint32_t ctrs                         : 4;
+	uint32_t ctds                         : 1;
+	uint32_t ari                          : 1;
+	uint32_t atom_ops                     : 1;
+	uint32_t atom32s                      : 1;
+	uint32_t atom64s                      : 1;
+	uint32_t atom128s                     : 1;
+	uint32_t noroprpr                     : 1;
+	uint32_t ltrs                         : 1;
+	uint32_t tphs                         : 2;
+	uint32_t reserved_14_17               : 4;
+	uint32_t obffs                        : 2;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg037 cvmx_pcieepx_cfg037_t;
 
@@ -2649,12 +3538,46 @@ typedef union cvmx_pcieepx_cfg037 cvmx_pcieepx_cfg037_t;
  * PCIE_CFG038 = Thirty-ninth 32-bits of PCIE type 0 config space
  * (Device Control 2 Register/Device Status 2 Register)
  */
-union cvmx_pcieepx_cfg038
-{
+union cvmx_pcieepx_cfg038 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg038_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg038_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_15_31               : 17;
+	uint32_t obffe                        : 2;  /**< Optimized Buffer Flush Fill (OBFF) Enable
+                                                         (Not Supported) */
+	uint32_t reserved_11_12               : 2;
+	uint32_t ltre                         : 1;  /**< Latency Tolerance Reporting (LTR) Mechanism Enable
+                                                         (Not Supported) */
+	uint32_t id0_cp                       : 1;  /**< ID Based Ordering Completion Enable
+                                                         (Not Supported) */
+	uint32_t id0_rq                       : 1;  /**< ID Based Ordering Request Enable
+                                                         (Not Supported) */
+	uint32_t atom_op_eb                   : 1;  /**< AtomicOp Egress Blocking
+                                                         (Not Supported)m */
+	uint32_t atom_op                      : 1;  /**< AtomicOp Requester Enable
+                                                         (Not Supported) */
+	uint32_t ari                          : 1;  /**< Alternate Routing ID Forwarding Supported
+                                                         (Not Supported) */
+	uint32_t ctd                          : 1;  /**< Completion Timeout Disable */
+	uint32_t ctv                          : 4;  /**< Completion Timeout Value
+                                                         Completion Timeout Programming is not supported
+                                                         Completion timeout is the range of 16 ms to 55 ms. */
+#else
+	uint32_t ctv                          : 4;
+	uint32_t ctd                          : 1;
+	uint32_t ari                          : 1;
+	uint32_t atom_op                      : 1;
+	uint32_t atom_op_eb                   : 1;
+	uint32_t id0_rq                       : 1;
+	uint32_t id0_cp                       : 1;
+	uint32_t ltre                         : 1;
+	uint32_t reserved_11_12               : 2;
+	uint32_t obffe                        : 2;
+	uint32_t reserved_15_31               : 17;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg038_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_5_31                : 27;
 	uint32_t ctd                          : 1;  /**< Completion Timeout Disable */
 	uint32_t ctv                          : 4;  /**< Completion Timeout Value
@@ -2665,13 +3588,44 @@ union cvmx_pcieepx_cfg038
 	uint32_t ctd                          : 1;
 	uint32_t reserved_5_31                : 27;
 #endif
-	} s;
-	struct cvmx_pcieepx_cfg038_s          cn52xx;
-	struct cvmx_pcieepx_cfg038_s          cn52xxp1;
-	struct cvmx_pcieepx_cfg038_s          cn56xx;
-	struct cvmx_pcieepx_cfg038_s          cn56xxp1;
-	struct cvmx_pcieepx_cfg038_s          cn63xx;
-	struct cvmx_pcieepx_cfg038_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pcieepx_cfg038_cn52xx     cn52xxp1;
+	struct cvmx_pcieepx_cfg038_cn52xx     cn56xx;
+	struct cvmx_pcieepx_cfg038_cn52xx     cn56xxp1;
+	struct cvmx_pcieepx_cfg038_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_10_31               : 22;
+	uint32_t id0_cp                       : 1;  /**< ID Based Ordering Completion Enable
+                                                         (Not Supported) */
+	uint32_t id0_rq                       : 1;  /**< ID Based Ordering Request Enable
+                                                         (Not Supported) */
+	uint32_t atom_op_eb                   : 1;  /**< AtomicOp Egress Blocking
+                                                         (Not Supported)m */
+	uint32_t atom_op                      : 1;  /**< AtomicOp Requester Enable
+                                                         (Not Supported) */
+	uint32_t ari                          : 1;  /**< Alternate Routing ID Forwarding Supported
+                                                         (Not Supported) */
+	uint32_t ctd                          : 1;  /**< Completion Timeout Disable */
+	uint32_t ctv                          : 4;  /**< Completion Timeout Value
+                                                         Completion Timeout Programming is not supported
+                                                         Completion timeout is the range of 16 ms to 55 ms. */
+#else
+	uint32_t ctv                          : 4;
+	uint32_t ctd                          : 1;
+	uint32_t ari                          : 1;
+	uint32_t atom_op                      : 1;
+	uint32_t atom_op_eb                   : 1;
+	uint32_t id0_rq                       : 1;
+	uint32_t id0_cp                       : 1;
+	uint32_t reserved_10_31               : 22;
+#endif
+	} cn61xx;
+	struct cvmx_pcieepx_cfg038_cn52xx     cn63xx;
+	struct cvmx_pcieepx_cfg038_cn52xx     cn63xxp1;
+	struct cvmx_pcieepx_cfg038_cn61xx     cn66xx;
+	struct cvmx_pcieepx_cfg038_cn61xx     cn68xx;
+	struct cvmx_pcieepx_cfg038_cn61xx     cn68xxp1;
+	struct cvmx_pcieepx_cfg038_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg038 cvmx_pcieepx_cfg038_t;
 
@@ -2681,23 +3635,52 @@ typedef union cvmx_pcieepx_cfg038 cvmx_pcieepx_cfg038_t;
  * PCIE_CFG039 = Fourtieth 32-bits of PCIE type 0 config space
  * (Link Capabilities 2 Register)
  */
-union cvmx_pcieepx_cfg039
-{
+union cvmx_pcieepx_cfg039 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg039_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg039_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_9_31                : 23;
+	uint32_t cls                          : 1;  /**< Crosslink Supported */
+	uint32_t slsv                         : 7;  /**< Supported Link Speeds Vector
+                                                         Indicates the supported Link speeds of the associated Port.
+                                                         For each bit, a value of 1b indicates that the cooresponding
+                                                         Link speed is supported; otherwise, the Link speed is not
+                                                         supported.
+                                                         Bit definitions are:
+                                                         Bit 1 2.5 GT/s
+                                                         Bit 2 5.0 GT/s
+                                                         Bit 3 8.0 GT/s (Not Supported)
+                                                         Bits 7:4 reserved
+                                                         The reset value of this field is controlled by a value sent from
+                                                         the lsb of the MIO_QLM#_SPD register
+                                                         qlm#_spd[0]   RST_VALUE   NOTE
+                                                         1             0001b       2.5 GHz supported
+                                                         0             0011b       5.0 GHz and 2.5 GHz supported */
+	uint32_t reserved_0_0                 : 1;
+#else
+	uint32_t reserved_0_0                 : 1;
+	uint32_t slsv                         : 7;
+	uint32_t cls                          : 1;
+	uint32_t reserved_9_31                : 23;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg039_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_0_31                : 32;
 #else
 	uint32_t reserved_0_31                : 32;
 #endif
-	} s;
-	struct cvmx_pcieepx_cfg039_s          cn52xx;
-	struct cvmx_pcieepx_cfg039_s          cn52xxp1;
-	struct cvmx_pcieepx_cfg039_s          cn56xx;
-	struct cvmx_pcieepx_cfg039_s          cn56xxp1;
+	} cn52xx;
+	struct cvmx_pcieepx_cfg039_cn52xx     cn52xxp1;
+	struct cvmx_pcieepx_cfg039_cn52xx     cn56xx;
+	struct cvmx_pcieepx_cfg039_cn52xx     cn56xxp1;
+	struct cvmx_pcieepx_cfg039_s          cn61xx;
 	struct cvmx_pcieepx_cfg039_s          cn63xx;
-	struct cvmx_pcieepx_cfg039_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg039_cn52xx     cn63xxp1;
+	struct cvmx_pcieepx_cfg039_s          cn66xx;
+	struct cvmx_pcieepx_cfg039_s          cn68xx;
+	struct cvmx_pcieepx_cfg039_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg039_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg039 cvmx_pcieepx_cfg039_t;
 
@@ -2707,12 +3690,10 @@ typedef union cvmx_pcieepx_cfg039 cvmx_pcieepx_cfg039_t;
  * PCIE_CFG040 = Fourty-first 32-bits of PCIE type 0 config space
  * (Link Control 2 Register/Link Status 2 Register)
  */
-union cvmx_pcieepx_cfg040
-{
+union cvmx_pcieepx_cfg040 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg040_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg040_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_17_31               : 15;
 	uint32_t cdl                          : 1;  /**< Current De-emphasis Level
                                                          When the Link is operating at 5 GT/s speed, this bit
@@ -2742,7 +3723,7 @@ union cvmx_pcieepx_cfg040
                                                          Compliance state. */
 	uint32_t tm                           : 3;  /**< Transmit Margin
                                                          This field controls the value of the non-de-emphasized
-                                                         voltage level at the Transmitter pins:
+                                                         voltage level at the Transmitter signals:
                                                           - 000: 800-1200 mV for full swing 400-600 mV for half-swing
                                                           - 001-010: values must be monotonic with a non-zero slope
                                                           - 011: 200-400 mV for full-swing and 100-200 mV for halfswing
@@ -2774,6 +3755,7 @@ union cvmx_pcieepx_cfg040
                                                          the upstream component in its training sequences:
                                                            - 0001: 2.5Gb/s Target Link Speed
                                                            - 0010: 5Gb/s Target Link Speed
+                                                           - 0100: 8Gb/s Target Link Speed (Not Supported)
                                                          All other encodings are reserved.
                                                          If a value is written to this field that does not correspond to
                                                          a speed included in the Supported Link Speeds field, the
@@ -2782,8 +3764,11 @@ union cvmx_pcieepx_cfg040
                                                          used to set the target compliance mode speed when
                                                          software is using the Enter Compliance bit to force a link
                                                          into compliance mode.
-                                                         Out of reset this will have a value of 1 or 2 which is
-                                                         selected by qlmCfgx[1]. */
+                                                         The reset value of this field is controlled by a value sent from
+                                                         the lsb of the MIO_QLM#_SPD register.
+                                                         qlm#_spd[0]   RST_VALUE   NOTE
+                                                         1             0001b       2.5 GHz supported
+                                                         0             0010b       5.0 GHz and 2.5 GHz supported */
 #else
 	uint32_t tls                          : 4;
 	uint32_t ec                           : 1;
@@ -2798,9 +3783,8 @@ union cvmx_pcieepx_cfg040
 	uint32_t reserved_17_31               : 15;
 #endif
 	} s;
-	struct cvmx_pcieepx_cfg040_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg040_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_0_31                : 32;
 #else
 	uint32_t reserved_0_31                : 32;
@@ -2809,8 +3793,13 @@ union cvmx_pcieepx_cfg040
 	struct cvmx_pcieepx_cfg040_cn52xx     cn52xxp1;
 	struct cvmx_pcieepx_cfg040_cn52xx     cn56xx;
 	struct cvmx_pcieepx_cfg040_cn52xx     cn56xxp1;
+	struct cvmx_pcieepx_cfg040_s          cn61xx;
 	struct cvmx_pcieepx_cfg040_s          cn63xx;
 	struct cvmx_pcieepx_cfg040_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg040_s          cn66xx;
+	struct cvmx_pcieepx_cfg040_s          cn68xx;
+	struct cvmx_pcieepx_cfg040_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg040_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg040 cvmx_pcieepx_cfg040_t;
 
@@ -2820,12 +3809,10 @@ typedef union cvmx_pcieepx_cfg040 cvmx_pcieepx_cfg040_t;
  * PCIE_CFG041 = Fourty-second 32-bits of PCIE type 0 config space
  * (Slot Capabilities 2 Register)
  */
-union cvmx_pcieepx_cfg041
-{
+union cvmx_pcieepx_cfg041 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg041_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg041_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_0_31                : 32;
 #else
 	uint32_t reserved_0_31                : 32;
@@ -2846,12 +3833,10 @@ typedef union cvmx_pcieepx_cfg041 cvmx_pcieepx_cfg041_t;
  * PCIE_CFG042 = Fourty-third 32-bits of PCIE type 0 config space
  * (Slot Control 2 Register/Slot Status 2 Register)
  */
-union cvmx_pcieepx_cfg042
-{
+union cvmx_pcieepx_cfg042 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg042_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg042_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_0_31                : 32;
 #else
 	uint32_t reserved_0_31                : 32;
@@ -2870,14 +3855,12 @@ typedef union cvmx_pcieepx_cfg042 cvmx_pcieepx_cfg042_t;
  * cvmx_pcieep#_cfg064
  *
  * PCIE_CFG064 = Sixty-fifth 32-bits of PCIE type 0 config space
- * (PCI Express Enhanced Capability Header)
+ * (PCI Express Extended Capability Header)
  */
-union cvmx_pcieepx_cfg064
-{
+union cvmx_pcieepx_cfg064 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg064_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg064_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t nco                          : 12; /**< Next Capability Offset */
 	uint32_t cv                           : 4;  /**< Capability Version */
 	uint32_t pcieec                       : 16; /**< PCIE Express Extended Capability */
@@ -2891,8 +3874,13 @@ union cvmx_pcieepx_cfg064
 	struct cvmx_pcieepx_cfg064_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg064_s          cn56xx;
 	struct cvmx_pcieepx_cfg064_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg064_s          cn61xx;
 	struct cvmx_pcieepx_cfg064_s          cn63xx;
 	struct cvmx_pcieepx_cfg064_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg064_s          cn66xx;
+	struct cvmx_pcieepx_cfg064_s          cn68xx;
+	struct cvmx_pcieepx_cfg064_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg064_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg064 cvmx_pcieepx_cfg064_t;
 
@@ -2902,12 +3890,51 @@ typedef union cvmx_pcieepx_cfg064 cvmx_pcieepx_cfg064_t;
  * PCIE_CFG065 = Sixty-sixth 32-bits of PCIE type 0 config space
  * (Uncorrectable Error Status Register)
  */
-union cvmx_pcieepx_cfg065
-{
+union cvmx_pcieepx_cfg065 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg065_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg065_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t uatombs                      : 1;  /**< Unsupported AtomicOp Egress Blocked Status */
+	uint32_t reserved_23_23               : 1;
+	uint32_t ucies                        : 1;  /**< Uncorrectable Internal Error Status */
+	uint32_t reserved_21_21               : 1;
+	uint32_t ures                         : 1;  /**< Unsupported Request Error Status */
+	uint32_t ecrces                       : 1;  /**< ECRC Error Status */
+	uint32_t mtlps                        : 1;  /**< Malformed TLP Status */
+	uint32_t ros                          : 1;  /**< Receiver Overflow Status */
+	uint32_t ucs                          : 1;  /**< Unexpected Completion Status */
+	uint32_t cas                          : 1;  /**< Completer Abort Status */
+	uint32_t cts                          : 1;  /**< Completion Timeout Status */
+	uint32_t fcpes                        : 1;  /**< Flow Control Protocol Error Status */
+	uint32_t ptlps                        : 1;  /**< Poisoned TLP Status */
+	uint32_t reserved_6_11                : 6;
+	uint32_t sdes                         : 1;  /**< Surprise Down Error Status (not supported) */
+	uint32_t dlpes                        : 1;  /**< Data Link Protocol Error Status */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpes                        : 1;
+	uint32_t sdes                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t ptlps                        : 1;
+	uint32_t fcpes                        : 1;
+	uint32_t cts                          : 1;
+	uint32_t cas                          : 1;
+	uint32_t ucs                          : 1;
+	uint32_t ros                          : 1;
+	uint32_t mtlps                        : 1;
+	uint32_t ecrces                       : 1;
+	uint32_t ures                         : 1;
+	uint32_t reserved_21_21               : 1;
+	uint32_t ucies                        : 1;
+	uint32_t reserved_23_23               : 1;
+	uint32_t uatombs                      : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg065_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_21_31               : 11;
 	uint32_t ures                         : 1;  /**< Unsupported Request Error Status */
 	uint32_t ecrces                       : 1;  /**< ECRC Error Status */
@@ -2938,13 +3965,91 @@ union cvmx_pcieepx_cfg065
 	uint32_t ures                         : 1;
 	uint32_t reserved_21_31               : 11;
 #endif
-	} s;
-	struct cvmx_pcieepx_cfg065_s          cn52xx;
-	struct cvmx_pcieepx_cfg065_s          cn52xxp1;
-	struct cvmx_pcieepx_cfg065_s          cn56xx;
-	struct cvmx_pcieepx_cfg065_s          cn56xxp1;
-	struct cvmx_pcieepx_cfg065_s          cn63xx;
-	struct cvmx_pcieepx_cfg065_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pcieepx_cfg065_cn52xx     cn52xxp1;
+	struct cvmx_pcieepx_cfg065_cn52xx     cn56xx;
+	struct cvmx_pcieepx_cfg065_cn52xx     cn56xxp1;
+	struct cvmx_pcieepx_cfg065_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t uatombs                      : 1;  /**< Unsupported AtomicOp Egress Blocked Status */
+	uint32_t reserved_21_23               : 3;
+	uint32_t ures                         : 1;  /**< Unsupported Request Error Status */
+	uint32_t ecrces                       : 1;  /**< ECRC Error Status */
+	uint32_t mtlps                        : 1;  /**< Malformed TLP Status */
+	uint32_t ros                          : 1;  /**< Receiver Overflow Status */
+	uint32_t ucs                          : 1;  /**< Unexpected Completion Status */
+	uint32_t cas                          : 1;  /**< Completer Abort Status */
+	uint32_t cts                          : 1;  /**< Completion Timeout Status */
+	uint32_t fcpes                        : 1;  /**< Flow Control Protocol Error Status */
+	uint32_t ptlps                        : 1;  /**< Poisoned TLP Status */
+	uint32_t reserved_6_11                : 6;
+	uint32_t sdes                         : 1;  /**< Surprise Down Error Status (not supported) */
+	uint32_t dlpes                        : 1;  /**< Data Link Protocol Error Status */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpes                        : 1;
+	uint32_t sdes                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t ptlps                        : 1;
+	uint32_t fcpes                        : 1;
+	uint32_t cts                          : 1;
+	uint32_t cas                          : 1;
+	uint32_t ucs                          : 1;
+	uint32_t ros                          : 1;
+	uint32_t mtlps                        : 1;
+	uint32_t ecrces                       : 1;
+	uint32_t ures                         : 1;
+	uint32_t reserved_21_23               : 3;
+	uint32_t uatombs                      : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} cn61xx;
+	struct cvmx_pcieepx_cfg065_cn52xx     cn63xx;
+	struct cvmx_pcieepx_cfg065_cn52xx     cn63xxp1;
+	struct cvmx_pcieepx_cfg065_cn61xx     cn66xx;
+	struct cvmx_pcieepx_cfg065_cn61xx     cn68xx;
+	struct cvmx_pcieepx_cfg065_cn52xx     cn68xxp1;
+	struct cvmx_pcieepx_cfg065_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t uatombs                      : 1;  /**< Unsupported AtomicOp Egress Blocked Status */
+	uint32_t reserved_23_23               : 1;
+	uint32_t ucies                        : 1;  /**< Uncorrectable Internal Error Status */
+	uint32_t reserved_21_21               : 1;
+	uint32_t ures                         : 1;  /**< Unsupported Request Error Status */
+	uint32_t ecrces                       : 1;  /**< ECRC Error Status */
+	uint32_t mtlps                        : 1;  /**< Malformed TLP Status */
+	uint32_t ros                          : 1;  /**< Receiver Overflow Status */
+	uint32_t ucs                          : 1;  /**< Unexpected Completion Status */
+	uint32_t cas                          : 1;  /**< Completer Abort Status */
+	uint32_t cts                          : 1;  /**< Completion Timeout Status */
+	uint32_t fcpes                        : 1;  /**< Flow Control Protocol Error Status */
+	uint32_t ptlps                        : 1;  /**< Poisoned TLP Status */
+	uint32_t reserved_5_11                : 7;
+	uint32_t dlpes                        : 1;  /**< Data Link Protocol Error Status */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpes                        : 1;
+	uint32_t reserved_5_11                : 7;
+	uint32_t ptlps                        : 1;
+	uint32_t fcpes                        : 1;
+	uint32_t cts                          : 1;
+	uint32_t cas                          : 1;
+	uint32_t ucs                          : 1;
+	uint32_t ros                          : 1;
+	uint32_t mtlps                        : 1;
+	uint32_t ecrces                       : 1;
+	uint32_t ures                         : 1;
+	uint32_t reserved_21_21               : 1;
+	uint32_t ucies                        : 1;
+	uint32_t reserved_23_23               : 1;
+	uint32_t uatombs                      : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg065 cvmx_pcieepx_cfg065_t;
 
@@ -2954,12 +4059,51 @@ typedef union cvmx_pcieepx_cfg065 cvmx_pcieepx_cfg065_t;
  * PCIE_CFG066 = Sixty-seventh 32-bits of PCIE type 0 config space
  * (Uncorrectable Error Mask Register)
  */
-union cvmx_pcieepx_cfg066
-{
+union cvmx_pcieepx_cfg066 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg066_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg066_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t uatombm                      : 1;  /**< Unsupported AtomicOp Egress Blocked Mask */
+	uint32_t reserved_23_23               : 1;
+	uint32_t uciem                        : 1;  /**< Uncorrectable Internal Error Mask */
+	uint32_t reserved_21_21               : 1;
+	uint32_t urem                         : 1;  /**< Unsupported Request Error Mask */
+	uint32_t ecrcem                       : 1;  /**< ECRC Error Mask */
+	uint32_t mtlpm                        : 1;  /**< Malformed TLP Mask */
+	uint32_t rom                          : 1;  /**< Receiver Overflow Mask */
+	uint32_t ucm                          : 1;  /**< Unexpected Completion Mask */
+	uint32_t cam                          : 1;  /**< Completer Abort Mask */
+	uint32_t ctm                          : 1;  /**< Completion Timeout Mask */
+	uint32_t fcpem                        : 1;  /**< Flow Control Protocol Error Mask */
+	uint32_t ptlpm                        : 1;  /**< Poisoned TLP Mask */
+	uint32_t reserved_6_11                : 6;
+	uint32_t sdem                         : 1;  /**< Surprise Down Error Mask (not supported) */
+	uint32_t dlpem                        : 1;  /**< Data Link Protocol Error Mask */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpem                        : 1;
+	uint32_t sdem                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t ptlpm                        : 1;
+	uint32_t fcpem                        : 1;
+	uint32_t ctm                          : 1;
+	uint32_t cam                          : 1;
+	uint32_t ucm                          : 1;
+	uint32_t rom                          : 1;
+	uint32_t mtlpm                        : 1;
+	uint32_t ecrcem                       : 1;
+	uint32_t urem                         : 1;
+	uint32_t reserved_21_21               : 1;
+	uint32_t uciem                        : 1;
+	uint32_t reserved_23_23               : 1;
+	uint32_t uatombm                      : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg066_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_21_31               : 11;
 	uint32_t urem                         : 1;  /**< Unsupported Request Error Mask */
 	uint32_t ecrcem                       : 1;  /**< ECRC Error Mask */
@@ -2990,13 +4134,91 @@ union cvmx_pcieepx_cfg066
 	uint32_t urem                         : 1;
 	uint32_t reserved_21_31               : 11;
 #endif
-	} s;
-	struct cvmx_pcieepx_cfg066_s          cn52xx;
-	struct cvmx_pcieepx_cfg066_s          cn52xxp1;
-	struct cvmx_pcieepx_cfg066_s          cn56xx;
-	struct cvmx_pcieepx_cfg066_s          cn56xxp1;
-	struct cvmx_pcieepx_cfg066_s          cn63xx;
-	struct cvmx_pcieepx_cfg066_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pcieepx_cfg066_cn52xx     cn52xxp1;
+	struct cvmx_pcieepx_cfg066_cn52xx     cn56xx;
+	struct cvmx_pcieepx_cfg066_cn52xx     cn56xxp1;
+	struct cvmx_pcieepx_cfg066_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t uatombm                      : 1;  /**< Unsupported AtomicOp Egress Blocked Mask */
+	uint32_t reserved_21_23               : 3;
+	uint32_t urem                         : 1;  /**< Unsupported Request Error Mask */
+	uint32_t ecrcem                       : 1;  /**< ECRC Error Mask */
+	uint32_t mtlpm                        : 1;  /**< Malformed TLP Mask */
+	uint32_t rom                          : 1;  /**< Receiver Overflow Mask */
+	uint32_t ucm                          : 1;  /**< Unexpected Completion Mask */
+	uint32_t cam                          : 1;  /**< Completer Abort Mask */
+	uint32_t ctm                          : 1;  /**< Completion Timeout Mask */
+	uint32_t fcpem                        : 1;  /**< Flow Control Protocol Error Mask */
+	uint32_t ptlpm                        : 1;  /**< Poisoned TLP Mask */
+	uint32_t reserved_6_11                : 6;
+	uint32_t sdem                         : 1;  /**< Surprise Down Error Mask (not supported) */
+	uint32_t dlpem                        : 1;  /**< Data Link Protocol Error Mask */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpem                        : 1;
+	uint32_t sdem                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t ptlpm                        : 1;
+	uint32_t fcpem                        : 1;
+	uint32_t ctm                          : 1;
+	uint32_t cam                          : 1;
+	uint32_t ucm                          : 1;
+	uint32_t rom                          : 1;
+	uint32_t mtlpm                        : 1;
+	uint32_t ecrcem                       : 1;
+	uint32_t urem                         : 1;
+	uint32_t reserved_21_23               : 3;
+	uint32_t uatombm                      : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} cn61xx;
+	struct cvmx_pcieepx_cfg066_cn52xx     cn63xx;
+	struct cvmx_pcieepx_cfg066_cn52xx     cn63xxp1;
+	struct cvmx_pcieepx_cfg066_cn61xx     cn66xx;
+	struct cvmx_pcieepx_cfg066_cn61xx     cn68xx;
+	struct cvmx_pcieepx_cfg066_cn52xx     cn68xxp1;
+	struct cvmx_pcieepx_cfg066_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t uatombm                      : 1;  /**< Unsupported AtomicOp Egress Blocked Mask */
+	uint32_t reserved_23_23               : 1;
+	uint32_t uciem                        : 1;  /**< Uncorrectable Internal Error Mask */
+	uint32_t reserved_21_21               : 1;
+	uint32_t urem                         : 1;  /**< Unsupported Request Error Mask */
+	uint32_t ecrcem                       : 1;  /**< ECRC Error Mask */
+	uint32_t mtlpm                        : 1;  /**< Malformed TLP Mask */
+	uint32_t rom                          : 1;  /**< Receiver Overflow Mask */
+	uint32_t ucm                          : 1;  /**< Unexpected Completion Mask */
+	uint32_t cam                          : 1;  /**< Completer Abort Mask */
+	uint32_t ctm                          : 1;  /**< Completion Timeout Mask */
+	uint32_t fcpem                        : 1;  /**< Flow Control Protocol Error Mask */
+	uint32_t ptlpm                        : 1;  /**< Poisoned TLP Mask */
+	uint32_t reserved_5_11                : 7;
+	uint32_t dlpem                        : 1;  /**< Data Link Protocol Error Mask */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpem                        : 1;
+	uint32_t reserved_5_11                : 7;
+	uint32_t ptlpm                        : 1;
+	uint32_t fcpem                        : 1;
+	uint32_t ctm                          : 1;
+	uint32_t cam                          : 1;
+	uint32_t ucm                          : 1;
+	uint32_t rom                          : 1;
+	uint32_t mtlpm                        : 1;
+	uint32_t ecrcem                       : 1;
+	uint32_t urem                         : 1;
+	uint32_t reserved_21_21               : 1;
+	uint32_t uciem                        : 1;
+	uint32_t reserved_23_23               : 1;
+	uint32_t uatombm                      : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg066 cvmx_pcieepx_cfg066_t;
 
@@ -3006,12 +4228,51 @@ typedef union cvmx_pcieepx_cfg066 cvmx_pcieepx_cfg066_t;
  * PCIE_CFG067 = Sixty-eighth 32-bits of PCIE type 0 config space
  * (Uncorrectable Error Severity Register)
  */
-union cvmx_pcieepx_cfg067
-{
+union cvmx_pcieepx_cfg067 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg067_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg067_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t uatombs                      : 1;  /**< Unsupported AtomicOp Egress Blocked Severity */
+	uint32_t reserved_23_23               : 1;
+	uint32_t ucies                        : 1;  /**< Uncorrectable Internal Error Severity */
+	uint32_t reserved_21_21               : 1;
+	uint32_t ures                         : 1;  /**< Unsupported Request Error Severity */
+	uint32_t ecrces                       : 1;  /**< ECRC Error Severity */
+	uint32_t mtlps                        : 1;  /**< Malformed TLP Severity */
+	uint32_t ros                          : 1;  /**< Receiver Overflow Severity */
+	uint32_t ucs                          : 1;  /**< Unexpected Completion Severity */
+	uint32_t cas                          : 1;  /**< Completer Abort Severity */
+	uint32_t cts                          : 1;  /**< Completion Timeout Severity */
+	uint32_t fcpes                        : 1;  /**< Flow Control Protocol Error Severity */
+	uint32_t ptlps                        : 1;  /**< Poisoned TLP Severity */
+	uint32_t reserved_6_11                : 6;
+	uint32_t sdes                         : 1;  /**< Surprise Down Error Severity (not supported) */
+	uint32_t dlpes                        : 1;  /**< Data Link Protocol Error Severity */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpes                        : 1;
+	uint32_t sdes                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t ptlps                        : 1;
+	uint32_t fcpes                        : 1;
+	uint32_t cts                          : 1;
+	uint32_t cas                          : 1;
+	uint32_t ucs                          : 1;
+	uint32_t ros                          : 1;
+	uint32_t mtlps                        : 1;
+	uint32_t ecrces                       : 1;
+	uint32_t ures                         : 1;
+	uint32_t reserved_21_21               : 1;
+	uint32_t ucies                        : 1;
+	uint32_t reserved_23_23               : 1;
+	uint32_t uatombs                      : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg067_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_21_31               : 11;
 	uint32_t ures                         : 1;  /**< Unsupported Request Error Severity */
 	uint32_t ecrces                       : 1;  /**< ECRC Error Severity */
@@ -3042,13 +4303,91 @@ union cvmx_pcieepx_cfg067
 	uint32_t ures                         : 1;
 	uint32_t reserved_21_31               : 11;
 #endif
-	} s;
-	struct cvmx_pcieepx_cfg067_s          cn52xx;
-	struct cvmx_pcieepx_cfg067_s          cn52xxp1;
-	struct cvmx_pcieepx_cfg067_s          cn56xx;
-	struct cvmx_pcieepx_cfg067_s          cn56xxp1;
-	struct cvmx_pcieepx_cfg067_s          cn63xx;
-	struct cvmx_pcieepx_cfg067_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pcieepx_cfg067_cn52xx     cn52xxp1;
+	struct cvmx_pcieepx_cfg067_cn52xx     cn56xx;
+	struct cvmx_pcieepx_cfg067_cn52xx     cn56xxp1;
+	struct cvmx_pcieepx_cfg067_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t uatombs                      : 1;  /**< Unsupported AtomicOp Egress Blocked Severity */
+	uint32_t reserved_21_23               : 3;
+	uint32_t ures                         : 1;  /**< Unsupported Request Error Severity */
+	uint32_t ecrces                       : 1;  /**< ECRC Error Severity */
+	uint32_t mtlps                        : 1;  /**< Malformed TLP Severity */
+	uint32_t ros                          : 1;  /**< Receiver Overflow Severity */
+	uint32_t ucs                          : 1;  /**< Unexpected Completion Severity */
+	uint32_t cas                          : 1;  /**< Completer Abort Severity */
+	uint32_t cts                          : 1;  /**< Completion Timeout Severity */
+	uint32_t fcpes                        : 1;  /**< Flow Control Protocol Error Severity */
+	uint32_t ptlps                        : 1;  /**< Poisoned TLP Severity */
+	uint32_t reserved_6_11                : 6;
+	uint32_t sdes                         : 1;  /**< Surprise Down Error Severity (not supported) */
+	uint32_t dlpes                        : 1;  /**< Data Link Protocol Error Severity */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpes                        : 1;
+	uint32_t sdes                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t ptlps                        : 1;
+	uint32_t fcpes                        : 1;
+	uint32_t cts                          : 1;
+	uint32_t cas                          : 1;
+	uint32_t ucs                          : 1;
+	uint32_t ros                          : 1;
+	uint32_t mtlps                        : 1;
+	uint32_t ecrces                       : 1;
+	uint32_t ures                         : 1;
+	uint32_t reserved_21_23               : 3;
+	uint32_t uatombs                      : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} cn61xx;
+	struct cvmx_pcieepx_cfg067_cn52xx     cn63xx;
+	struct cvmx_pcieepx_cfg067_cn52xx     cn63xxp1;
+	struct cvmx_pcieepx_cfg067_cn61xx     cn66xx;
+	struct cvmx_pcieepx_cfg067_cn61xx     cn68xx;
+	struct cvmx_pcieepx_cfg067_cn52xx     cn68xxp1;
+	struct cvmx_pcieepx_cfg067_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t uatombs                      : 1;  /**< Unsupported AtomicOp Egress Blocked Severity */
+	uint32_t reserved_23_23               : 1;
+	uint32_t ucies                        : 1;  /**< Uncorrectable Internal Error Severity */
+	uint32_t reserved_21_21               : 1;
+	uint32_t ures                         : 1;  /**< Unsupported Request Error Severity */
+	uint32_t ecrces                       : 1;  /**< ECRC Error Severity */
+	uint32_t mtlps                        : 1;  /**< Malformed TLP Severity */
+	uint32_t ros                          : 1;  /**< Receiver Overflow Severity */
+	uint32_t ucs                          : 1;  /**< Unexpected Completion Severity */
+	uint32_t cas                          : 1;  /**< Completer Abort Severity */
+	uint32_t cts                          : 1;  /**< Completion Timeout Severity */
+	uint32_t fcpes                        : 1;  /**< Flow Control Protocol Error Severity */
+	uint32_t ptlps                        : 1;  /**< Poisoned TLP Severity */
+	uint32_t reserved_5_11                : 7;
+	uint32_t dlpes                        : 1;  /**< Data Link Protocol Error Severity */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpes                        : 1;
+	uint32_t reserved_5_11                : 7;
+	uint32_t ptlps                        : 1;
+	uint32_t fcpes                        : 1;
+	uint32_t cts                          : 1;
+	uint32_t cas                          : 1;
+	uint32_t ucs                          : 1;
+	uint32_t ros                          : 1;
+	uint32_t mtlps                        : 1;
+	uint32_t ecrces                       : 1;
+	uint32_t ures                         : 1;
+	uint32_t reserved_21_21               : 1;
+	uint32_t ucies                        : 1;
+	uint32_t reserved_23_23               : 1;
+	uint32_t uatombs                      : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg067 cvmx_pcieepx_cfg067_t;
 
@@ -3058,12 +4397,35 @@ typedef union cvmx_pcieepx_cfg067 cvmx_pcieepx_cfg067_t;
  * PCIE_CFG068 = Sixty-ninth 32-bits of PCIE type 0 config space
  * (Correctable Error Status Register)
  */
-union cvmx_pcieepx_cfg068
-{
+union cvmx_pcieepx_cfg068 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg068_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg068_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_15_31               : 17;
+	uint32_t cies                         : 1;  /**< Corrected Internal Error Status */
+	uint32_t anfes                        : 1;  /**< Advisory Non-Fatal Error Status */
+	uint32_t rtts                         : 1;  /**< Reply Timer Timeout Status */
+	uint32_t reserved_9_11                : 3;
+	uint32_t rnrs                         : 1;  /**< REPLAY_NUM Rollover Status */
+	uint32_t bdllps                       : 1;  /**< Bad DLLP Status */
+	uint32_t btlps                        : 1;  /**< Bad TLP Status */
+	uint32_t reserved_1_5                 : 5;
+	uint32_t res                          : 1;  /**< Receiver Error Status */
+#else
+	uint32_t res                          : 1;
+	uint32_t reserved_1_5                 : 5;
+	uint32_t btlps                        : 1;
+	uint32_t bdllps                       : 1;
+	uint32_t rnrs                         : 1;
+	uint32_t reserved_9_11                : 3;
+	uint32_t rtts                         : 1;
+	uint32_t anfes                        : 1;
+	uint32_t cies                         : 1;
+	uint32_t reserved_15_31               : 17;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg068_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_14_31               : 18;
 	uint32_t anfes                        : 1;  /**< Advisory Non-Fatal Error Status */
 	uint32_t rtts                         : 1;  /**< Reply Timer Timeout Status */
@@ -3084,13 +4446,17 @@ union cvmx_pcieepx_cfg068
 	uint32_t anfes                        : 1;
 	uint32_t reserved_14_31               : 18;
 #endif
-	} s;
-	struct cvmx_pcieepx_cfg068_s          cn52xx;
-	struct cvmx_pcieepx_cfg068_s          cn52xxp1;
-	struct cvmx_pcieepx_cfg068_s          cn56xx;
-	struct cvmx_pcieepx_cfg068_s          cn56xxp1;
-	struct cvmx_pcieepx_cfg068_s          cn63xx;
-	struct cvmx_pcieepx_cfg068_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pcieepx_cfg068_cn52xx     cn52xxp1;
+	struct cvmx_pcieepx_cfg068_cn52xx     cn56xx;
+	struct cvmx_pcieepx_cfg068_cn52xx     cn56xxp1;
+	struct cvmx_pcieepx_cfg068_cn52xx     cn61xx;
+	struct cvmx_pcieepx_cfg068_cn52xx     cn63xx;
+	struct cvmx_pcieepx_cfg068_cn52xx     cn63xxp1;
+	struct cvmx_pcieepx_cfg068_cn52xx     cn66xx;
+	struct cvmx_pcieepx_cfg068_cn52xx     cn68xx;
+	struct cvmx_pcieepx_cfg068_cn52xx     cn68xxp1;
+	struct cvmx_pcieepx_cfg068_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg068 cvmx_pcieepx_cfg068_t;
 
@@ -3100,12 +4466,35 @@ typedef union cvmx_pcieepx_cfg068 cvmx_pcieepx_cfg068_t;
  * PCIE_CFG069 = Seventieth 32-bits of PCIE type 0 config space
  * (Correctable Error Mask Register)
  */
-union cvmx_pcieepx_cfg069
-{
+union cvmx_pcieepx_cfg069 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg069_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg069_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_15_31               : 17;
+	uint32_t ciem                         : 1;  /**< Corrected Internal Error Mask */
+	uint32_t anfem                        : 1;  /**< Advisory Non-Fatal Error Mask */
+	uint32_t rttm                         : 1;  /**< Reply Timer Timeout Mask */
+	uint32_t reserved_9_11                : 3;
+	uint32_t rnrm                         : 1;  /**< REPLAY_NUM Rollover Mask */
+	uint32_t bdllpm                       : 1;  /**< Bad DLLP Mask */
+	uint32_t btlpm                        : 1;  /**< Bad TLP Mask */
+	uint32_t reserved_1_5                 : 5;
+	uint32_t rem                          : 1;  /**< Receiver Error Mask */
+#else
+	uint32_t rem                          : 1;
+	uint32_t reserved_1_5                 : 5;
+	uint32_t btlpm                        : 1;
+	uint32_t bdllpm                       : 1;
+	uint32_t rnrm                         : 1;
+	uint32_t reserved_9_11                : 3;
+	uint32_t rttm                         : 1;
+	uint32_t anfem                        : 1;
+	uint32_t ciem                         : 1;
+	uint32_t reserved_15_31               : 17;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg069_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_14_31               : 18;
 	uint32_t anfem                        : 1;  /**< Advisory Non-Fatal Error Mask */
 	uint32_t rttm                         : 1;  /**< Reply Timer Timeout Mask */
@@ -3126,13 +4515,17 @@ union cvmx_pcieepx_cfg069
 	uint32_t anfem                        : 1;
 	uint32_t reserved_14_31               : 18;
 #endif
-	} s;
-	struct cvmx_pcieepx_cfg069_s          cn52xx;
-	struct cvmx_pcieepx_cfg069_s          cn52xxp1;
-	struct cvmx_pcieepx_cfg069_s          cn56xx;
-	struct cvmx_pcieepx_cfg069_s          cn56xxp1;
-	struct cvmx_pcieepx_cfg069_s          cn63xx;
-	struct cvmx_pcieepx_cfg069_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pcieepx_cfg069_cn52xx     cn52xxp1;
+	struct cvmx_pcieepx_cfg069_cn52xx     cn56xx;
+	struct cvmx_pcieepx_cfg069_cn52xx     cn56xxp1;
+	struct cvmx_pcieepx_cfg069_cn52xx     cn61xx;
+	struct cvmx_pcieepx_cfg069_cn52xx     cn63xx;
+	struct cvmx_pcieepx_cfg069_cn52xx     cn63xxp1;
+	struct cvmx_pcieepx_cfg069_cn52xx     cn66xx;
+	struct cvmx_pcieepx_cfg069_cn52xx     cn68xx;
+	struct cvmx_pcieepx_cfg069_cn52xx     cn68xxp1;
+	struct cvmx_pcieepx_cfg069_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg069 cvmx_pcieepx_cfg069_t;
 
@@ -3142,12 +4535,10 @@ typedef union cvmx_pcieepx_cfg069 cvmx_pcieepx_cfg069_t;
  * PCIE_CFG070 = Seventy-first 32-bits of PCIE type 0 config space
  * (Advanced Error Capabilities and Control Register)
  */
-union cvmx_pcieepx_cfg070
-{
+union cvmx_pcieepx_cfg070 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg070_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg070_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_9_31                : 23;
 	uint32_t ce                           : 1;  /**< ECRC Check Enable */
 	uint32_t cc                           : 1;  /**< ECRC Check Capable */
@@ -3167,8 +4558,13 @@ union cvmx_pcieepx_cfg070
 	struct cvmx_pcieepx_cfg070_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg070_s          cn56xx;
 	struct cvmx_pcieepx_cfg070_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg070_s          cn61xx;
 	struct cvmx_pcieepx_cfg070_s          cn63xx;
 	struct cvmx_pcieepx_cfg070_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg070_s          cn66xx;
+	struct cvmx_pcieepx_cfg070_s          cn68xx;
+	struct cvmx_pcieepx_cfg070_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg070_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg070 cvmx_pcieepx_cfg070_t;
 
@@ -3178,12 +4574,10 @@ typedef union cvmx_pcieepx_cfg070 cvmx_pcieepx_cfg070_t;
  * PCIE_CFG071 = Seventy-second 32-bits of PCIE type 0 config space
  * (Header Log Register 1)
  */
-union cvmx_pcieepx_cfg071
-{
+union cvmx_pcieepx_cfg071 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg071_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg071_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dword1                       : 32; /**< Header Log Register (first DWORD) */
 #else
 	uint32_t dword1                       : 32;
@@ -3193,8 +4587,13 @@ union cvmx_pcieepx_cfg071
 	struct cvmx_pcieepx_cfg071_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg071_s          cn56xx;
 	struct cvmx_pcieepx_cfg071_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg071_s          cn61xx;
 	struct cvmx_pcieepx_cfg071_s          cn63xx;
 	struct cvmx_pcieepx_cfg071_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg071_s          cn66xx;
+	struct cvmx_pcieepx_cfg071_s          cn68xx;
+	struct cvmx_pcieepx_cfg071_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg071_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg071 cvmx_pcieepx_cfg071_t;
 
@@ -3204,12 +4603,10 @@ typedef union cvmx_pcieepx_cfg071 cvmx_pcieepx_cfg071_t;
  * PCIE_CFG072 = Seventy-third 32-bits of PCIE type 0 config space
  * (Header Log Register 2)
  */
-union cvmx_pcieepx_cfg072
-{
+union cvmx_pcieepx_cfg072 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg072_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg072_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dword2                       : 32; /**< Header Log Register (second DWORD) */
 #else
 	uint32_t dword2                       : 32;
@@ -3219,8 +4616,13 @@ union cvmx_pcieepx_cfg072
 	struct cvmx_pcieepx_cfg072_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg072_s          cn56xx;
 	struct cvmx_pcieepx_cfg072_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg072_s          cn61xx;
 	struct cvmx_pcieepx_cfg072_s          cn63xx;
 	struct cvmx_pcieepx_cfg072_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg072_s          cn66xx;
+	struct cvmx_pcieepx_cfg072_s          cn68xx;
+	struct cvmx_pcieepx_cfg072_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg072_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg072 cvmx_pcieepx_cfg072_t;
 
@@ -3230,12 +4632,10 @@ typedef union cvmx_pcieepx_cfg072 cvmx_pcieepx_cfg072_t;
  * PCIE_CFG073 = Seventy-fourth 32-bits of PCIE type 0 config space
  * (Header Log Register 3)
  */
-union cvmx_pcieepx_cfg073
-{
+union cvmx_pcieepx_cfg073 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg073_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg073_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dword3                       : 32; /**< Header Log Register (third DWORD) */
 #else
 	uint32_t dword3                       : 32;
@@ -3245,8 +4645,13 @@ union cvmx_pcieepx_cfg073
 	struct cvmx_pcieepx_cfg073_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg073_s          cn56xx;
 	struct cvmx_pcieepx_cfg073_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg073_s          cn61xx;
 	struct cvmx_pcieepx_cfg073_s          cn63xx;
 	struct cvmx_pcieepx_cfg073_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg073_s          cn66xx;
+	struct cvmx_pcieepx_cfg073_s          cn68xx;
+	struct cvmx_pcieepx_cfg073_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg073_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg073 cvmx_pcieepx_cfg073_t;
 
@@ -3256,12 +4661,10 @@ typedef union cvmx_pcieepx_cfg073 cvmx_pcieepx_cfg073_t;
  * PCIE_CFG074 = Seventy-fifth 32-bits of PCIE type 0 config space
  * (Header Log Register 4)
  */
-union cvmx_pcieepx_cfg074
-{
+union cvmx_pcieepx_cfg074 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg074_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg074_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dword4                       : 32; /**< Header Log Register (fourth DWORD) */
 #else
 	uint32_t dword4                       : 32;
@@ -3271,8 +4674,13 @@ union cvmx_pcieepx_cfg074
 	struct cvmx_pcieepx_cfg074_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg074_s          cn56xx;
 	struct cvmx_pcieepx_cfg074_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg074_s          cn61xx;
 	struct cvmx_pcieepx_cfg074_s          cn63xx;
 	struct cvmx_pcieepx_cfg074_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg074_s          cn66xx;
+	struct cvmx_pcieepx_cfg074_s          cn68xx;
+	struct cvmx_pcieepx_cfg074_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg074_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg074 cvmx_pcieepx_cfg074_t;
 
@@ -3282,22 +4690,26 @@ typedef union cvmx_pcieepx_cfg074 cvmx_pcieepx_cfg074_t;
  * PCIE_CFG448 = Four hundred forty-ninth 32-bits of PCIE type 0 config space
  * (Ack Latency Timer and Replay Timer Register)
  */
-union cvmx_pcieepx_cfg448
-{
+union cvmx_pcieepx_cfg448 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg448_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg448_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t rtl                          : 16; /**< Replay Time Limit
                                                          The replay timer expires when it reaches this limit. The PCI
                                                          Express bus initiates a replay upon reception of a Nak or when
                                                          the replay timer expires.
-                                                         The default is then updated based on the Negotiated Link Width
-                                                         and Max_Payload_Size. */
+                                                         This value will be set correctly by the hardware out of reset
+                                                         or when the negotiated Link-Width or Payload-Size changes. If
+                                                         the user changes this value through a CSR write or by an
+                                                         EEPROM load then they should refer to the PCIe Specification
+                                                         for the correct value. */
 	uint32_t rtltl                        : 16; /**< Round Trip Latency Time Limit
                                                          The Ack/Nak latency timer expires when it reaches this limit.
-                                                         The default is then updated based on the Negotiated Link Width
-                                                         and Max_Payload_Size. */
+                                                         This value will be set correctly by the hardware out of reset
+                                                         or when the negotiated Link-Width or Payload-Size changes. If
+                                                         the user changes this value through a CSR write or by an
+                                                         EEPROM load then they should refer to the PCIe Specification
+                                                         for the correct value. */
 #else
 	uint32_t rtltl                        : 16;
 	uint32_t rtl                          : 16;
@@ -3307,8 +4719,13 @@ union cvmx_pcieepx_cfg448
 	struct cvmx_pcieepx_cfg448_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg448_s          cn56xx;
 	struct cvmx_pcieepx_cfg448_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg448_s          cn61xx;
 	struct cvmx_pcieepx_cfg448_s          cn63xx;
 	struct cvmx_pcieepx_cfg448_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg448_s          cn66xx;
+	struct cvmx_pcieepx_cfg448_s          cn68xx;
+	struct cvmx_pcieepx_cfg448_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg448_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg448 cvmx_pcieepx_cfg448_t;
 
@@ -3318,12 +4735,10 @@ typedef union cvmx_pcieepx_cfg448 cvmx_pcieepx_cfg448_t;
  * PCIE_CFG449 = Four hundred fiftieth 32-bits of PCIE type 0 config space
  * (Other Message Register)
  */
-union cvmx_pcieepx_cfg449
-{
+union cvmx_pcieepx_cfg449 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg449_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg449_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t omr                          : 32; /**< Other Message Register
                                                          This register can be used for either of the following purposes:
                                                          o To send a specific PCI Express Message, the application
@@ -3344,8 +4759,13 @@ union cvmx_pcieepx_cfg449
 	struct cvmx_pcieepx_cfg449_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg449_s          cn56xx;
 	struct cvmx_pcieepx_cfg449_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg449_s          cn61xx;
 	struct cvmx_pcieepx_cfg449_s          cn63xx;
 	struct cvmx_pcieepx_cfg449_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg449_s          cn66xx;
+	struct cvmx_pcieepx_cfg449_s          cn68xx;
+	struct cvmx_pcieepx_cfg449_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg449_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg449 cvmx_pcieepx_cfg449_t;
 
@@ -3355,12 +4775,10 @@ typedef union cvmx_pcieepx_cfg449 cvmx_pcieepx_cfg449_t;
  * PCIE_CFG450 = Four hundred fifty-first 32-bits of PCIE type 0 config space
  * (Port Force Link Register)
  */
-union cvmx_pcieepx_cfg450
-{
+union cvmx_pcieepx_cfg450 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg450_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg450_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t lpec                         : 8;  /**< Low Power Entrance Count
                                                          The Power Management state will wait for this many clock cycles
                                                          for the associated completion of a CfgWr to PCIE_CFG017 register
@@ -3427,8 +4845,13 @@ union cvmx_pcieepx_cfg450
 	struct cvmx_pcieepx_cfg450_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg450_s          cn56xx;
 	struct cvmx_pcieepx_cfg450_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg450_s          cn61xx;
 	struct cvmx_pcieepx_cfg450_s          cn63xx;
 	struct cvmx_pcieepx_cfg450_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg450_s          cn66xx;
+	struct cvmx_pcieepx_cfg450_s          cn68xx;
+	struct cvmx_pcieepx_cfg450_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg450_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg450 cvmx_pcieepx_cfg450_t;
 
@@ -3438,12 +4861,63 @@ typedef union cvmx_pcieepx_cfg450 cvmx_pcieepx_cfg450_t;
  * PCIE_CFG451 = Four hundred fifty-second 32-bits of PCIE type 0 config space
  * (Ack Frequency Register)
  */
-union cvmx_pcieepx_cfg451
-{
+union cvmx_pcieepx_cfg451 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg451_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg451_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_31_31               : 1;
+	uint32_t easpml1                      : 1;  /**< Enter ASPM L1 without receive in L0s
+                                                         Allow core to enter ASPM L1 even when link partner did
+                                                         not go to L0s (receive is not in L0s).
+                                                         When not set, core goes to ASPM L1 only after idle period
+                                                         during which both receive and transmit are in L0s. */
+	uint32_t l1el                         : 3;  /**< L1 Entrance Latency
+                                                         Values correspond to:
+                                                         o 000: 1 ms
+                                                         o 001: 2 ms
+                                                         o 010: 4 ms
+                                                         o 011: 8 ms
+                                                         o 100: 16 ms
+                                                         o 101: 32 ms
+                                                         o 110 or 111: 64 ms */
+	uint32_t l0el                         : 3;  /**< L0s Entrance Latency
+                                                         Values correspond to:
+                                                         o 000: 1 ms
+                                                         o 001: 2 ms
+                                                         o 010: 3 ms
+                                                         o 011: 4 ms
+                                                         o 100: 5 ms
+                                                         o 101: 6 ms
+                                                         o 110 or 111: 7 ms */
+	uint32_t n_fts_cc                     : 8;  /**< N_FTS when common clock is used.
+                                                         The number of Fast Training Sequence ordered sets to be
+                                                         transmitted when transitioning from L0s to L0. The maximum
+                                                         number of FTS ordered-sets that a component can request is 255.
+                                                          Note: A value of zero is not supported; a value of
+                                                                zero can cause the LTSSM to go into the recovery state
+                                                                when exiting from L0s. */
+	uint32_t n_fts                        : 8;  /**< N_FTS
+                                                         The number of Fast Training Sequence ordered sets to be
+                                                         transmitted when transitioning from L0s to L0. The maximum
+                                                         number of FTS ordered-sets that a component can request is 255.
+                                                         Note: A value of zero is not supported; a value of
+                                                               zero can cause the LTSSM to go into the recovery state
+                                                               when exiting from L0s. */
+	uint32_t ack_freq                     : 8;  /**< Ack Frequency
+                                                         The number of pending Ack's specified here (up to 255) before
+                                                         sending an Ack. */
+#else
+	uint32_t ack_freq                     : 8;
+	uint32_t n_fts                        : 8;
+	uint32_t n_fts_cc                     : 8;
+	uint32_t l0el                         : 3;
+	uint32_t l1el                         : 3;
+	uint32_t easpml1                      : 1;
+	uint32_t reserved_31_31               : 1;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg451_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_30_31               : 2;
 	uint32_t l1el                         : 3;  /**< L1 Entrance Latency
                                                          Values correspond to:
@@ -3488,13 +4962,17 @@ union cvmx_pcieepx_cfg451
 	uint32_t l1el                         : 3;
 	uint32_t reserved_30_31               : 2;
 #endif
-	} s;
-	struct cvmx_pcieepx_cfg451_s          cn52xx;
-	struct cvmx_pcieepx_cfg451_s          cn52xxp1;
-	struct cvmx_pcieepx_cfg451_s          cn56xx;
-	struct cvmx_pcieepx_cfg451_s          cn56xxp1;
-	struct cvmx_pcieepx_cfg451_s          cn63xx;
-	struct cvmx_pcieepx_cfg451_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pcieepx_cfg451_cn52xx     cn52xxp1;
+	struct cvmx_pcieepx_cfg451_cn52xx     cn56xx;
+	struct cvmx_pcieepx_cfg451_cn52xx     cn56xxp1;
+	struct cvmx_pcieepx_cfg451_s          cn61xx;
+	struct cvmx_pcieepx_cfg451_cn52xx     cn63xx;
+	struct cvmx_pcieepx_cfg451_cn52xx     cn63xxp1;
+	struct cvmx_pcieepx_cfg451_s          cn66xx;
+	struct cvmx_pcieepx_cfg451_s          cn68xx;
+	struct cvmx_pcieepx_cfg451_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg451_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg451 cvmx_pcieepx_cfg451_t;
 
@@ -3504,12 +4982,10 @@ typedef union cvmx_pcieepx_cfg451 cvmx_pcieepx_cfg451_t;
  * PCIE_CFG452 = Four hundred fifty-third 32-bits of PCIE type 0 config space
  * (Port Link Control Register)
  */
-union cvmx_pcieepx_cfg452
-{
+union cvmx_pcieepx_cfg452 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg452_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg452_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_26_31               : 6;
 	uint32_t eccrc                        : 1;  /**< Enable Corrupted CRC
                                                          Causes corrupt LCRC for TLPs when set,
@@ -3518,6 +4994,68 @@ union cvmx_pcieepx_cfg452
 	uint32_t reserved_22_24               : 3;
 	uint32_t lme                          : 6;  /**< Link Mode Enable
                                                          o 000001: x1
+                                                         o 000011: x2  (not supported)
+                                                         o 000111: x4  (not supported)
+                                                         o 001111: x8  (not supported)
+                                                         o 011111: x16 (not supported)
+                                                         o 111111: x32 (not supported)
+                                                         This field indicates the MAXIMUM number of lanes supported
+                                                         by the PCIe port.
+                                                         See also MLW.
+                                                         (Note: The value of this field does NOT indicate the number
+                                                          of lanes in use by the PCIe. LME sets the max number of lanes
+                                                          in the PCIe core that COULD be used. As per the PCIe specs,
+                                                          the PCIe core can negotiate a smaller link width) */
+	uint32_t reserved_8_15                : 8;
+	uint32_t flm                          : 1;  /**< Fast Link Mode
+                                                         Sets all internal timers to fast mode for simulation purposes.
+                                                         If during an eeprom load, the first word loaded is 0xffffffff,
+                                                         then the EEPROM load will be terminated and this bit will be set. */
+	uint32_t reserved_6_6                 : 1;
+	uint32_t dllle                        : 1;  /**< DLL Link Enable
+                                                         Enables Link initialization. If DLL Link Enable = 0, the PCI
+                                                         Express bus does not transmit InitFC DLLPs and does not
+                                                         establish a Link. */
+	uint32_t reserved_4_4                 : 1;
+	uint32_t ra                           : 1;  /**< Reset Assert
+                                                         Triggers a recovery and forces the LTSSM to the Hot Reset
+                                                         state (downstream port only). */
+	uint32_t le                           : 1;  /**< Loopback Enable
+                                                         Initiate loopback mode as a master. On a 0->1 transition,
+                                                         the PCIe core sends TS ordered sets with the loopback bit set
+                                                         to cause the link partner to enter into loopback mode as a
+                                                         slave. Normal transmission is not possible when LE=1. To exit
+                                                         loopback mode, take the link through a reset sequence. */
+	uint32_t sd                           : 1;  /**< Scramble Disable
+                                                         Turns off data scrambling. */
+	uint32_t omr                          : 1;  /**< Other Message Request
+                                                         When software writes a `1' to this bit, the PCI Express bus
+                                                         transmits the Message contained in the Other Message register. */
+#else
+	uint32_t omr                          : 1;
+	uint32_t sd                           : 1;
+	uint32_t le                           : 1;
+	uint32_t ra                           : 1;
+	uint32_t reserved_4_4                 : 1;
+	uint32_t dllle                        : 1;
+	uint32_t reserved_6_6                 : 1;
+	uint32_t flm                          : 1;
+	uint32_t reserved_8_15                : 8;
+	uint32_t lme                          : 6;
+	uint32_t reserved_22_24               : 3;
+	uint32_t eccrc                        : 1;
+	uint32_t reserved_26_31               : 6;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg452_s          cn52xx;
+	struct cvmx_pcieepx_cfg452_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg452_s          cn56xx;
+	struct cvmx_pcieepx_cfg452_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg452_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_22_31               : 10;
+	uint32_t lme                          : 6;  /**< Link Mode Enable
+                                                         o 000001: x1
                                                          o 000011: x2
                                                          o 000111: x4
                                                          o 001111: x8  (not supported)
@@ -3571,17 +5109,15 @@ union cvmx_pcieepx_cfg452
 	uint32_t flm                          : 1;
 	uint32_t reserved_8_15                : 8;
 	uint32_t lme                          : 6;
-	uint32_t reserved_22_24               : 3;
-	uint32_t eccrc                        : 1;
-	uint32_t reserved_26_31               : 6;
+	uint32_t reserved_22_31               : 10;
 #endif
-	} s;
-	struct cvmx_pcieepx_cfg452_s          cn52xx;
-	struct cvmx_pcieepx_cfg452_s          cn52xxp1;
-	struct cvmx_pcieepx_cfg452_s          cn56xx;
-	struct cvmx_pcieepx_cfg452_s          cn56xxp1;
+	} cn61xx;
 	struct cvmx_pcieepx_cfg452_s          cn63xx;
 	struct cvmx_pcieepx_cfg452_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg452_cn61xx     cn66xx;
+	struct cvmx_pcieepx_cfg452_cn61xx     cn68xx;
+	struct cvmx_pcieepx_cfg452_cn61xx     cn68xxp1;
+	struct cvmx_pcieepx_cfg452_cn61xx     cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg452 cvmx_pcieepx_cfg452_t;
 
@@ -3591,12 +5127,10 @@ typedef union cvmx_pcieepx_cfg452 cvmx_pcieepx_cfg452_t;
  * PCIE_CFG453 = Four hundred fifty-fourth 32-bits of PCIE type 0 config space
  * (Lane Skew Register)
  */
-union cvmx_pcieepx_cfg453
-{
+union cvmx_pcieepx_cfg453 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg453_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg453_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dlld                         : 1;  /**< Disable Lane-to-Lane Deskew
                                                          Disables the internal Lane-to-Lane deskew logic. */
 	uint32_t reserved_26_30               : 5;
@@ -3622,8 +5156,13 @@ union cvmx_pcieepx_cfg453
 	struct cvmx_pcieepx_cfg453_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg453_s          cn56xx;
 	struct cvmx_pcieepx_cfg453_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg453_s          cn61xx;
 	struct cvmx_pcieepx_cfg453_s          cn63xx;
 	struct cvmx_pcieepx_cfg453_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg453_s          cn66xx;
+	struct cvmx_pcieepx_cfg453_s          cn68xx;
+	struct cvmx_pcieepx_cfg453_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg453_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg453 cvmx_pcieepx_cfg453_t;
 
@@ -3633,12 +5172,37 @@ typedef union cvmx_pcieepx_cfg453 cvmx_pcieepx_cfg453_t;
  * PCIE_CFG454 = Four hundred fifty-fifth 32-bits of PCIE type 0 config space
  * (Symbol Number Register)
  */
-union cvmx_pcieepx_cfg454
-{
+union cvmx_pcieepx_cfg454 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg454_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg454_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t cx_nfunc                     : 3;  /**< Number of Functions (minus 1)
+                                                         Configuration Requests targeted at function numbers above this
+                                                         value will be returned with unsupported request */
+	uint32_t tmfcwt                       : 5;  /**< Timer Modifier for Flow Control Watchdog Timer
+                                                         Increases the timer value for the Flow Control watchdog timer,
+                                                         in increments of 16 clock cycles. */
+	uint32_t tmanlt                       : 5;  /**< Timer Modifier for Ack/Nak Latency Timer
+                                                         Increases the timer value for the Ack/Nak latency timer, in
+                                                         increments of 64 clock cycles. */
+	uint32_t tmrt                         : 5;  /**< Timer Modifier for Replay Timer
+                                                         Increases the timer value for the replay timer, in increments
+                                                         of 64 clock cycles. */
+	uint32_t reserved_11_13               : 3;
+	uint32_t nskps                        : 3;  /**< Number of SKP Symbols */
+	uint32_t reserved_0_7                 : 8;
+#else
+	uint32_t reserved_0_7                 : 8;
+	uint32_t nskps                        : 3;
+	uint32_t reserved_11_13               : 3;
+	uint32_t tmrt                         : 5;
+	uint32_t tmanlt                       : 5;
+	uint32_t tmfcwt                       : 5;
+	uint32_t cx_nfunc                     : 3;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg454_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_29_31               : 3;
 	uint32_t tmfcwt                       : 5;  /**< Timer Modifier for Flow Control Watchdog Timer
                                                          Increases the timer value for the Flow Control watchdog timer,
@@ -3665,13 +5229,41 @@ union cvmx_pcieepx_cfg454
 	uint32_t tmfcwt                       : 5;
 	uint32_t reserved_29_31               : 3;
 #endif
-	} s;
-	struct cvmx_pcieepx_cfg454_s          cn52xx;
-	struct cvmx_pcieepx_cfg454_s          cn52xxp1;
-	struct cvmx_pcieepx_cfg454_s          cn56xx;
-	struct cvmx_pcieepx_cfg454_s          cn56xxp1;
-	struct cvmx_pcieepx_cfg454_s          cn63xx;
-	struct cvmx_pcieepx_cfg454_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pcieepx_cfg454_cn52xx     cn52xxp1;
+	struct cvmx_pcieepx_cfg454_cn52xx     cn56xx;
+	struct cvmx_pcieepx_cfg454_cn52xx     cn56xxp1;
+	struct cvmx_pcieepx_cfg454_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t cx_nfunc                     : 3;  /**< Number of Functions (minus 1)
+                                                         Configuration Requests targeted at function numbers above this
+                                                         value will be returned with unsupported request */
+	uint32_t tmfcwt                       : 5;  /**< Timer Modifier for Flow Control Watchdog Timer
+                                                         Increases the timer value for the Flow Control watchdog timer,
+                                                         in increments of 16 clock cycles. */
+	uint32_t tmanlt                       : 5;  /**< Timer Modifier for Ack/Nak Latency Timer
+                                                         Increases the timer value for the Ack/Nak latency timer, in
+                                                         increments of 64 clock cycles. */
+	uint32_t tmrt                         : 5;  /**< Timer Modifier for Replay Timer
+                                                         Increases the timer value for the replay timer, in increments
+                                                         of 64 clock cycles. */
+	uint32_t reserved_8_13                : 6;
+	uint32_t mfuncn                       : 8;  /**< Max Number of Functions Supported */
+#else
+	uint32_t mfuncn                       : 8;
+	uint32_t reserved_8_13                : 6;
+	uint32_t tmrt                         : 5;
+	uint32_t tmanlt                       : 5;
+	uint32_t tmfcwt                       : 5;
+	uint32_t cx_nfunc                     : 3;
+#endif
+	} cn61xx;
+	struct cvmx_pcieepx_cfg454_cn52xx     cn63xx;
+	struct cvmx_pcieepx_cfg454_cn52xx     cn63xxp1;
+	struct cvmx_pcieepx_cfg454_cn61xx     cn66xx;
+	struct cvmx_pcieepx_cfg454_cn61xx     cn68xx;
+	struct cvmx_pcieepx_cfg454_cn52xx     cn68xxp1;
+	struct cvmx_pcieepx_cfg454_cn61xx     cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg454 cvmx_pcieepx_cfg454_t;
 
@@ -3681,12 +5273,10 @@ typedef union cvmx_pcieepx_cfg454 cvmx_pcieepx_cfg454_t;
  * PCIE_CFG455 = Four hundred fifty-sixth 32-bits of PCIE type 0 config space
  * (Symbol Timer Register/Filter Mask Register 1)
  */
-union cvmx_pcieepx_cfg455
-{
+union cvmx_pcieepx_cfg455 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg455_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg455_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t m_cfg0_filt                  : 1;  /**< Mask filtering of received Configuration Requests (RC mode only) */
 	uint32_t m_io_filt                    : 1;  /**< Mask filtering of received I/O Requests (RC mode only) */
 	uint32_t msg_ctrl                     : 1;  /**< Message Control
@@ -3733,8 +5323,13 @@ union cvmx_pcieepx_cfg455
 	struct cvmx_pcieepx_cfg455_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg455_s          cn56xx;
 	struct cvmx_pcieepx_cfg455_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg455_s          cn61xx;
 	struct cvmx_pcieepx_cfg455_s          cn63xx;
 	struct cvmx_pcieepx_cfg455_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg455_s          cn66xx;
+	struct cvmx_pcieepx_cfg455_s          cn68xx;
+	struct cvmx_pcieepx_cfg455_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg455_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg455 cvmx_pcieepx_cfg455_t;
 
@@ -3744,12 +5339,25 @@ typedef union cvmx_pcieepx_cfg455 cvmx_pcieepx_cfg455_t;
  * PCIE_CFG456 = Four hundred fifty-seventh 32-bits of PCIE type 0 config space
  * (Filter Mask Register 2)
  */
-union cvmx_pcieepx_cfg456
-{
+union cvmx_pcieepx_cfg456 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg456_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg456_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_4_31                : 28;
+	uint32_t m_handle_flush               : 1;  /**< Mask Core Filter to handle flush request */
+	uint32_t m_dabort_4ucpl               : 1;  /**< Mask DLLP abort for unexpected CPL */
+	uint32_t m_vend1_drp                  : 1;  /**< Mask Vendor MSG Type 1 dropped silently */
+	uint32_t m_vend0_drp                  : 1;  /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */
+#else
+	uint32_t m_vend0_drp                  : 1;
+	uint32_t m_vend1_drp                  : 1;
+	uint32_t m_dabort_4ucpl               : 1;
+	uint32_t m_handle_flush               : 1;
+	uint32_t reserved_4_31                : 28;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg456_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_2_31                : 30;
 	uint32_t m_vend1_drp                  : 1;  /**< Mask Vendor MSG Type 1 dropped silently */
 	uint32_t m_vend0_drp                  : 1;  /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */
@@ -3758,13 +5366,17 @@ union cvmx_pcieepx_cfg456
 	uint32_t m_vend1_drp                  : 1;
 	uint32_t reserved_2_31                : 30;
 #endif
-	} s;
-	struct cvmx_pcieepx_cfg456_s          cn52xx;
-	struct cvmx_pcieepx_cfg456_s          cn52xxp1;
-	struct cvmx_pcieepx_cfg456_s          cn56xx;
-	struct cvmx_pcieepx_cfg456_s          cn56xxp1;
-	struct cvmx_pcieepx_cfg456_s          cn63xx;
-	struct cvmx_pcieepx_cfg456_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pcieepx_cfg456_cn52xx     cn52xxp1;
+	struct cvmx_pcieepx_cfg456_cn52xx     cn56xx;
+	struct cvmx_pcieepx_cfg456_cn52xx     cn56xxp1;
+	struct cvmx_pcieepx_cfg456_s          cn61xx;
+	struct cvmx_pcieepx_cfg456_cn52xx     cn63xx;
+	struct cvmx_pcieepx_cfg456_cn52xx     cn63xxp1;
+	struct cvmx_pcieepx_cfg456_s          cn66xx;
+	struct cvmx_pcieepx_cfg456_s          cn68xx;
+	struct cvmx_pcieepx_cfg456_cn52xx     cn68xxp1;
+	struct cvmx_pcieepx_cfg456_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg456 cvmx_pcieepx_cfg456_t;
 
@@ -3774,12 +5386,10 @@ typedef union cvmx_pcieepx_cfg456 cvmx_pcieepx_cfg456_t;
  * PCIE_CFG458 = Four hundred fifty-ninth 32-bits of PCIE type 0 config space
  * (Debug Register 0)
  */
-union cvmx_pcieepx_cfg458
-{
+union cvmx_pcieepx_cfg458 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg458_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg458_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dbg_info_l32                 : 32; /**< Debug Info Lower 32 Bits */
 #else
 	uint32_t dbg_info_l32                 : 32;
@@ -3789,8 +5399,13 @@ union cvmx_pcieepx_cfg458
 	struct cvmx_pcieepx_cfg458_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg458_s          cn56xx;
 	struct cvmx_pcieepx_cfg458_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg458_s          cn61xx;
 	struct cvmx_pcieepx_cfg458_s          cn63xx;
 	struct cvmx_pcieepx_cfg458_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg458_s          cn66xx;
+	struct cvmx_pcieepx_cfg458_s          cn68xx;
+	struct cvmx_pcieepx_cfg458_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg458_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg458 cvmx_pcieepx_cfg458_t;
 
@@ -3800,12 +5415,10 @@ typedef union cvmx_pcieepx_cfg458 cvmx_pcieepx_cfg458_t;
  * PCIE_CFG459 = Four hundred sixtieth 32-bits of PCIE type 0 config space
  * (Debug Register 1)
  */
-union cvmx_pcieepx_cfg459
-{
+union cvmx_pcieepx_cfg459 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg459_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg459_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dbg_info_u32                 : 32; /**< Debug Info Upper 32 Bits */
 #else
 	uint32_t dbg_info_u32                 : 32;
@@ -3815,8 +5428,13 @@ union cvmx_pcieepx_cfg459
 	struct cvmx_pcieepx_cfg459_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg459_s          cn56xx;
 	struct cvmx_pcieepx_cfg459_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg459_s          cn61xx;
 	struct cvmx_pcieepx_cfg459_s          cn63xx;
 	struct cvmx_pcieepx_cfg459_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg459_s          cn66xx;
+	struct cvmx_pcieepx_cfg459_s          cn68xx;
+	struct cvmx_pcieepx_cfg459_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg459_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg459 cvmx_pcieepx_cfg459_t;
 
@@ -3826,12 +5444,10 @@ typedef union cvmx_pcieepx_cfg459 cvmx_pcieepx_cfg459_t;
  * PCIE_CFG460 = Four hundred sixty-first 32-bits of PCIE type 0 config space
  * (Transmit Posted FC Credit Status)
  */
-union cvmx_pcieepx_cfg460
-{
+union cvmx_pcieepx_cfg460 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg460_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg460_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_20_31               : 12;
 	uint32_t tphfcc                       : 8;  /**< Transmit Posted Header FC Credits
                                                          The Posted Header credits advertised by the receiver at the
@@ -3849,8 +5465,13 @@ union cvmx_pcieepx_cfg460
 	struct cvmx_pcieepx_cfg460_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg460_s          cn56xx;
 	struct cvmx_pcieepx_cfg460_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg460_s          cn61xx;
 	struct cvmx_pcieepx_cfg460_s          cn63xx;
 	struct cvmx_pcieepx_cfg460_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg460_s          cn66xx;
+	struct cvmx_pcieepx_cfg460_s          cn68xx;
+	struct cvmx_pcieepx_cfg460_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg460_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg460 cvmx_pcieepx_cfg460_t;
 
@@ -3860,12 +5481,10 @@ typedef union cvmx_pcieepx_cfg460 cvmx_pcieepx_cfg460_t;
  * PCIE_CFG461 = Four hundred sixty-second 32-bits of PCIE type 0 config space
  * (Transmit Non-Posted FC Credit Status)
  */
-union cvmx_pcieepx_cfg461
-{
+union cvmx_pcieepx_cfg461 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg461_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg461_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_20_31               : 12;
 	uint32_t tchfcc                       : 8;  /**< Transmit Non-Posted Header FC Credits
                                                          The Non-Posted Header credits advertised by the receiver at the
@@ -3883,8 +5502,13 @@ union cvmx_pcieepx_cfg461
 	struct cvmx_pcieepx_cfg461_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg461_s          cn56xx;
 	struct cvmx_pcieepx_cfg461_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg461_s          cn61xx;
 	struct cvmx_pcieepx_cfg461_s          cn63xx;
 	struct cvmx_pcieepx_cfg461_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg461_s          cn66xx;
+	struct cvmx_pcieepx_cfg461_s          cn68xx;
+	struct cvmx_pcieepx_cfg461_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg461_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg461 cvmx_pcieepx_cfg461_t;
 
@@ -3894,12 +5518,10 @@ typedef union cvmx_pcieepx_cfg461 cvmx_pcieepx_cfg461_t;
  * PCIE_CFG462 = Four hundred sixty-third 32-bits of PCIE type 0 config space
  * (Transmit Completion FC Credit Status )
  */
-union cvmx_pcieepx_cfg462
-{
+union cvmx_pcieepx_cfg462 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg462_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg462_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_20_31               : 12;
 	uint32_t tchfcc                       : 8;  /**< Transmit Completion Header FC Credits
                                                          The Completion Header credits advertised by the receiver at the
@@ -3917,8 +5539,13 @@ union cvmx_pcieepx_cfg462
 	struct cvmx_pcieepx_cfg462_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg462_s          cn56xx;
 	struct cvmx_pcieepx_cfg462_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg462_s          cn61xx;
 	struct cvmx_pcieepx_cfg462_s          cn63xx;
 	struct cvmx_pcieepx_cfg462_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg462_s          cn66xx;
+	struct cvmx_pcieepx_cfg462_s          cn68xx;
+	struct cvmx_pcieepx_cfg462_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg462_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg462 cvmx_pcieepx_cfg462_t;
 
@@ -3928,12 +5555,10 @@ typedef union cvmx_pcieepx_cfg462 cvmx_pcieepx_cfg462_t;
  * PCIE_CFG463 = Four hundred sixty-fourth 32-bits of PCIE type 0 config space
  * (Queue Status)
  */
-union cvmx_pcieepx_cfg463
-{
+union cvmx_pcieepx_cfg463 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg463_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg463_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_3_31                : 29;
 	uint32_t rqne                         : 1;  /**< Received Queue Not Empty
                                                          Indicates there is data in one or more of the receive buffers. */
@@ -3955,8 +5580,13 @@ union cvmx_pcieepx_cfg463
 	struct cvmx_pcieepx_cfg463_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg463_s          cn56xx;
 	struct cvmx_pcieepx_cfg463_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg463_s          cn61xx;
 	struct cvmx_pcieepx_cfg463_s          cn63xx;
 	struct cvmx_pcieepx_cfg463_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg463_s          cn66xx;
+	struct cvmx_pcieepx_cfg463_s          cn68xx;
+	struct cvmx_pcieepx_cfg463_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg463_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg463 cvmx_pcieepx_cfg463_t;
 
@@ -3966,12 +5596,10 @@ typedef union cvmx_pcieepx_cfg463 cvmx_pcieepx_cfg463_t;
  * PCIE_CFG464 = Four hundred sixty-fifth 32-bits of PCIE type 0 config space
  * (VC Transmit Arbitration Register 1)
  */
-union cvmx_pcieepx_cfg464
-{
+union cvmx_pcieepx_cfg464 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg464_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg464_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t wrr_vc3                      : 8;  /**< WRR Weight for VC3 */
 	uint32_t wrr_vc2                      : 8;  /**< WRR Weight for VC2 */
 	uint32_t wrr_vc1                      : 8;  /**< WRR Weight for VC1 */
@@ -3987,8 +5615,13 @@ union cvmx_pcieepx_cfg464
 	struct cvmx_pcieepx_cfg464_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg464_s          cn56xx;
 	struct cvmx_pcieepx_cfg464_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg464_s          cn61xx;
 	struct cvmx_pcieepx_cfg464_s          cn63xx;
 	struct cvmx_pcieepx_cfg464_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg464_s          cn66xx;
+	struct cvmx_pcieepx_cfg464_s          cn68xx;
+	struct cvmx_pcieepx_cfg464_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg464_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg464 cvmx_pcieepx_cfg464_t;
 
@@ -3998,12 +5631,10 @@ typedef union cvmx_pcieepx_cfg464 cvmx_pcieepx_cfg464_t;
  * PCIE_CFG465 = Four hundred sixty-sixth 32-bits of PCIE type 0 config space
  * (VC Transmit Arbitration Register 2)
  */
-union cvmx_pcieepx_cfg465
-{
+union cvmx_pcieepx_cfg465 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg465_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg465_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t wrr_vc7                      : 8;  /**< WRR Weight for VC7 */
 	uint32_t wrr_vc6                      : 8;  /**< WRR Weight for VC6 */
 	uint32_t wrr_vc5                      : 8;  /**< WRR Weight for VC5 */
@@ -4019,8 +5650,13 @@ union cvmx_pcieepx_cfg465
 	struct cvmx_pcieepx_cfg465_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg465_s          cn56xx;
 	struct cvmx_pcieepx_cfg465_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg465_s          cn61xx;
 	struct cvmx_pcieepx_cfg465_s          cn63xx;
 	struct cvmx_pcieepx_cfg465_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg465_s          cn66xx;
+	struct cvmx_pcieepx_cfg465_s          cn68xx;
+	struct cvmx_pcieepx_cfg465_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg465_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg465 cvmx_pcieepx_cfg465_t;
 
@@ -4030,12 +5666,10 @@ typedef union cvmx_pcieepx_cfg465 cvmx_pcieepx_cfg465_t;
  * PCIE_CFG466 = Four hundred sixty-seventh 32-bits of PCIE type 0 config space
  * (VC0 Posted Receive Queue Control)
  */
-union cvmx_pcieepx_cfg466
-{
+union cvmx_pcieepx_cfg466 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg466_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg466_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t rx_queue_order               : 1;  /**< VC Ordering for Receive Queues
                                                          Determines the VC ordering rule for the receive queues, used
                                                          only in the segmented-buffer configuration,
@@ -4087,8 +5721,13 @@ union cvmx_pcieepx_cfg466
 	struct cvmx_pcieepx_cfg466_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg466_s          cn56xx;
 	struct cvmx_pcieepx_cfg466_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg466_s          cn61xx;
 	struct cvmx_pcieepx_cfg466_s          cn63xx;
 	struct cvmx_pcieepx_cfg466_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg466_s          cn66xx;
+	struct cvmx_pcieepx_cfg466_s          cn68xx;
+	struct cvmx_pcieepx_cfg466_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg466_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg466 cvmx_pcieepx_cfg466_t;
 
@@ -4098,12 +5737,10 @@ typedef union cvmx_pcieepx_cfg466 cvmx_pcieepx_cfg466_t;
  * PCIE_CFG467 = Four hundred sixty-eighth 32-bits of PCIE type 0 config space
  * (VC0 Non-Posted Receive Queue Control)
  */
-union cvmx_pcieepx_cfg467
-{
+union cvmx_pcieepx_cfg467 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg467_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg467_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_24_31               : 8;
 	uint32_t queue_mode                   : 3;  /**< VC0 Non-Posted TLP Queue Mode
                                                          The operating mode of the Non-Posted receive queue for VC0,
@@ -4137,8 +5774,13 @@ union cvmx_pcieepx_cfg467
 	struct cvmx_pcieepx_cfg467_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg467_s          cn56xx;
 	struct cvmx_pcieepx_cfg467_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg467_s          cn61xx;
 	struct cvmx_pcieepx_cfg467_s          cn63xx;
 	struct cvmx_pcieepx_cfg467_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg467_s          cn66xx;
+	struct cvmx_pcieepx_cfg467_s          cn68xx;
+	struct cvmx_pcieepx_cfg467_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg467_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg467 cvmx_pcieepx_cfg467_t;
 
@@ -4148,12 +5790,10 @@ typedef union cvmx_pcieepx_cfg467 cvmx_pcieepx_cfg467_t;
  * PCIE_CFG468 = Four hundred sixty-ninth 32-bits of PCIE type 0 config space
  * (VC0 Completion Receive Queue Control)
  */
-union cvmx_pcieepx_cfg468
-{
+union cvmx_pcieepx_cfg468 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg468_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg468_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_24_31               : 8;
 	uint32_t queue_mode                   : 3;  /**< VC0 Completion TLP Queue Mode
                                                          The operating mode of the Completion receive queue for VC0,
@@ -4187,8 +5827,13 @@ union cvmx_pcieepx_cfg468
 	struct cvmx_pcieepx_cfg468_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg468_s          cn56xx;
 	struct cvmx_pcieepx_cfg468_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg468_s          cn61xx;
 	struct cvmx_pcieepx_cfg468_s          cn63xx;
 	struct cvmx_pcieepx_cfg468_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg468_s          cn66xx;
+	struct cvmx_pcieepx_cfg468_s          cn68xx;
+	struct cvmx_pcieepx_cfg468_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg468_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg468 cvmx_pcieepx_cfg468_t;
 
@@ -4198,12 +5843,10 @@ typedef union cvmx_pcieepx_cfg468 cvmx_pcieepx_cfg468_t;
  * PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 0 config space
  * (VC0 Posted Buffer Depth)
  */
-union cvmx_pcieepx_cfg490
-{
+union cvmx_pcieepx_cfg490 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg490_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg490_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_26_31               : 6;
 	uint32_t header_depth                 : 10; /**< VC0 Posted Header Queue Depth
                                                          Sets the number of entries in the Posted header queue for VC0
@@ -4227,8 +5870,13 @@ union cvmx_pcieepx_cfg490
 	struct cvmx_pcieepx_cfg490_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg490_s          cn56xx;
 	struct cvmx_pcieepx_cfg490_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg490_s          cn61xx;
 	struct cvmx_pcieepx_cfg490_s          cn63xx;
 	struct cvmx_pcieepx_cfg490_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg490_s          cn66xx;
+	struct cvmx_pcieepx_cfg490_s          cn68xx;
+	struct cvmx_pcieepx_cfg490_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg490_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg490 cvmx_pcieepx_cfg490_t;
 
@@ -4238,12 +5886,10 @@ typedef union cvmx_pcieepx_cfg490 cvmx_pcieepx_cfg490_t;
  * PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 0 config space
  * (VC0 Non-Posted Buffer Depth)
  */
-union cvmx_pcieepx_cfg491
-{
+union cvmx_pcieepx_cfg491 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg491_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg491_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_26_31               : 6;
 	uint32_t header_depth                 : 10; /**< VC0 Non-Posted Header Queue Depth
                                                          Sets the number of entries in the Non-Posted header queue for
@@ -4267,8 +5913,13 @@ union cvmx_pcieepx_cfg491
 	struct cvmx_pcieepx_cfg491_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg491_s          cn56xx;
 	struct cvmx_pcieepx_cfg491_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg491_s          cn61xx;
 	struct cvmx_pcieepx_cfg491_s          cn63xx;
 	struct cvmx_pcieepx_cfg491_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg491_s          cn66xx;
+	struct cvmx_pcieepx_cfg491_s          cn68xx;
+	struct cvmx_pcieepx_cfg491_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg491_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg491 cvmx_pcieepx_cfg491_t;
 
@@ -4278,12 +5929,10 @@ typedef union cvmx_pcieepx_cfg491 cvmx_pcieepx_cfg491_t;
  * PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 0 config space
  * (VC0 Completion Buffer Depth)
  */
-union cvmx_pcieepx_cfg492
-{
+union cvmx_pcieepx_cfg492 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg492_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg492_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_26_31               : 6;
 	uint32_t header_depth                 : 10; /**< VC0 Completion Header Queue Depth
                                                          Sets the number of entries in the Completion header queue for
@@ -4307,8 +5956,13 @@ union cvmx_pcieepx_cfg492
 	struct cvmx_pcieepx_cfg492_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg492_s          cn56xx;
 	struct cvmx_pcieepx_cfg492_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg492_s          cn61xx;
 	struct cvmx_pcieepx_cfg492_s          cn63xx;
 	struct cvmx_pcieepx_cfg492_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg492_s          cn66xx;
+	struct cvmx_pcieepx_cfg492_s          cn68xx;
+	struct cvmx_pcieepx_cfg492_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg492_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg492 cvmx_pcieepx_cfg492_t;
 
@@ -4318,12 +5972,10 @@ typedef union cvmx_pcieepx_cfg492 cvmx_pcieepx_cfg492_t;
  * PCIE_CFG515 = Five hundred sixteenth 32-bits of PCIE type 0 config space
  * (Port Logic Register (Gen2))
  */
-union cvmx_pcieepx_cfg515
-{
+union cvmx_pcieepx_cfg515 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg515_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg515_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_21_31               : 11;
 	uint32_t s_d_e                        : 1;  /**< SEL_DE_EMPHASIS
                                                          Used to set the de-emphasis level for upstream ports. */
@@ -4334,8 +5986,8 @@ union cvmx_pcieepx_cfg515
                                                          Indicates the voltage level the PHY should drive. When set to
                                                          1, indicates Full Swing. When set to 0, indicates Low Swing */
 	uint32_t dsc                          : 1;  /**< Directed Speed Change
-                                                         Indicates to the LTSSM whether or not to initiate a speed
-                                                         change. */
+                                                         o a write of '1' will initiate a speed change
+                                                         o always reads a zero */
 	uint32_t le                           : 9;  /**< Lane Enable
                                                          Indicates the number of lanes to check for exit from electrical
                                                          idle in Polling.Active and Polling.Compliance. 1 = x1, 2 = x2,
@@ -4361,8 +6013,13 @@ union cvmx_pcieepx_cfg515
 	uint32_t reserved_21_31               : 11;
 #endif
 	} s;
+	struct cvmx_pcieepx_cfg515_s          cn61xx;
 	struct cvmx_pcieepx_cfg515_s          cn63xx;
 	struct cvmx_pcieepx_cfg515_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg515_s          cn66xx;
+	struct cvmx_pcieepx_cfg515_s          cn68xx;
+	struct cvmx_pcieepx_cfg515_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg515_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg515 cvmx_pcieepx_cfg515_t;
 
@@ -4372,12 +6029,10 @@ typedef union cvmx_pcieepx_cfg515 cvmx_pcieepx_cfg515_t;
  * PCIE_CFG516 = Five hundred seventeenth 32-bits of PCIE type 0 config space
  * (PHY Status Register)
  */
-union cvmx_pcieepx_cfg516
-{
+union cvmx_pcieepx_cfg516 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg516_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg516_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t phy_stat                     : 32; /**< PHY Status */
 #else
 	uint32_t phy_stat                     : 32;
@@ -4387,8 +6042,13 @@ union cvmx_pcieepx_cfg516
 	struct cvmx_pcieepx_cfg516_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg516_s          cn56xx;
 	struct cvmx_pcieepx_cfg516_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg516_s          cn61xx;
 	struct cvmx_pcieepx_cfg516_s          cn63xx;
 	struct cvmx_pcieepx_cfg516_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg516_s          cn66xx;
+	struct cvmx_pcieepx_cfg516_s          cn68xx;
+	struct cvmx_pcieepx_cfg516_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg516_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg516 cvmx_pcieepx_cfg516_t;
 
@@ -4398,12 +6058,10 @@ typedef union cvmx_pcieepx_cfg516 cvmx_pcieepx_cfg516_t;
  * PCIE_CFG517 = Five hundred eighteenth 32-bits of PCIE type 0 config space
  * (PHY Control Register)
  */
-union cvmx_pcieepx_cfg517
-{
+union cvmx_pcieepx_cfg517 {
 	uint32_t u32;
-	struct cvmx_pcieepx_cfg517_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcieepx_cfg517_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t phy_ctrl                     : 32; /**< PHY Control */
 #else
 	uint32_t phy_ctrl                     : 32;
@@ -4413,8 +6071,13 @@ union cvmx_pcieepx_cfg517
 	struct cvmx_pcieepx_cfg517_s          cn52xxp1;
 	struct cvmx_pcieepx_cfg517_s          cn56xx;
 	struct cvmx_pcieepx_cfg517_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg517_s          cn61xx;
 	struct cvmx_pcieepx_cfg517_s          cn63xx;
 	struct cvmx_pcieepx_cfg517_s          cn63xxp1;
+	struct cvmx_pcieepx_cfg517_s          cn66xx;
+	struct cvmx_pcieepx_cfg517_s          cn68xx;
+	struct cvmx_pcieepx_cfg517_s          cn68xxp1;
+	struct cvmx_pcieepx_cfg517_s          cnf71xx;
 };
 typedef union cvmx_pcieepx_cfg517 cvmx_pcieepx_cfg517_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-pciercx-defs.h b/sys/contrib/octeon-sdk/cvmx-pciercx-defs.h
index 3094bac..66d3137 100644
--- a/sys/contrib/octeon-sdk/cvmx-pciercx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-pciercx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_PCIERCX_TYPEDEFS_H__
-#define __CVMX_PCIERCX_TYPEDEFS_H__
+#ifndef __CVMX_PCIERCX_DEFS_H__
+#define __CVMX_PCIERCX_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCIERCX_CFG000(unsigned long block_id)
@@ -58,7 +58,11 @@ static inline uint64_t CVMX_PCIERCX_CFG000(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG000(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000000ull;
 }
@@ -71,7 +75,11 @@ static inline uint64_t CVMX_PCIERCX_CFG001(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG001(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000004ull;
 }
@@ -84,7 +92,11 @@ static inline uint64_t CVMX_PCIERCX_CFG002(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG002(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000008ull;
 }
@@ -97,7 +109,11 @@ static inline uint64_t CVMX_PCIERCX_CFG003(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG003(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000000Cull;
 }
@@ -110,7 +126,11 @@ static inline uint64_t CVMX_PCIERCX_CFG004(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG004(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000010ull;
 }
@@ -123,7 +143,11 @@ static inline uint64_t CVMX_PCIERCX_CFG005(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG005(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000014ull;
 }
@@ -136,7 +160,11 @@ static inline uint64_t CVMX_PCIERCX_CFG006(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG006(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000018ull;
 }
@@ -149,7 +177,11 @@ static inline uint64_t CVMX_PCIERCX_CFG007(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG007(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000001Cull;
 }
@@ -162,7 +194,11 @@ static inline uint64_t CVMX_PCIERCX_CFG008(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG008(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000020ull;
 }
@@ -175,7 +211,11 @@ static inline uint64_t CVMX_PCIERCX_CFG009(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG009(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000024ull;
 }
@@ -188,7 +228,11 @@ static inline uint64_t CVMX_PCIERCX_CFG010(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG010(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000028ull;
 }
@@ -201,7 +245,11 @@ static inline uint64_t CVMX_PCIERCX_CFG011(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG011(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000002Cull;
 }
@@ -214,7 +262,11 @@ static inline uint64_t CVMX_PCIERCX_CFG012(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG012(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000030ull;
 }
@@ -227,7 +279,11 @@ static inline uint64_t CVMX_PCIERCX_CFG013(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG013(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000034ull;
 }
@@ -240,7 +296,11 @@ static inline uint64_t CVMX_PCIERCX_CFG014(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG014(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000038ull;
 }
@@ -253,7 +313,11 @@ static inline uint64_t CVMX_PCIERCX_CFG015(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG015(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000003Cull;
 }
@@ -266,7 +330,11 @@ static inline uint64_t CVMX_PCIERCX_CFG016(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG016(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000040ull;
 }
@@ -279,7 +347,11 @@ static inline uint64_t CVMX_PCIERCX_CFG017(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG017(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000044ull;
 }
@@ -292,7 +364,11 @@ static inline uint64_t CVMX_PCIERCX_CFG020(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG020(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000050ull;
 }
@@ -305,7 +381,11 @@ static inline uint64_t CVMX_PCIERCX_CFG021(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG021(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000054ull;
 }
@@ -318,7 +398,11 @@ static inline uint64_t CVMX_PCIERCX_CFG022(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG022(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000058ull;
 }
@@ -331,7 +415,11 @@ static inline uint64_t CVMX_PCIERCX_CFG023(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG023(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000005Cull;
 }
@@ -344,7 +432,11 @@ static inline uint64_t CVMX_PCIERCX_CFG028(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG028(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000070ull;
 }
@@ -357,7 +449,11 @@ static inline uint64_t CVMX_PCIERCX_CFG029(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG029(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000074ull;
 }
@@ -370,7 +466,11 @@ static inline uint64_t CVMX_PCIERCX_CFG030(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG030(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000078ull;
 }
@@ -383,7 +483,11 @@ static inline uint64_t CVMX_PCIERCX_CFG031(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG031(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000007Cull;
 }
@@ -396,7 +500,11 @@ static inline uint64_t CVMX_PCIERCX_CFG032(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG032(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000080ull;
 }
@@ -409,7 +517,11 @@ static inline uint64_t CVMX_PCIERCX_CFG033(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG033(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000084ull;
 }
@@ -422,7 +534,11 @@ static inline uint64_t CVMX_PCIERCX_CFG034(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG034(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000088ull;
 }
@@ -435,7 +551,11 @@ static inline uint64_t CVMX_PCIERCX_CFG035(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG035(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000008Cull;
 }
@@ -448,7 +568,11 @@ static inline uint64_t CVMX_PCIERCX_CFG036(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG036(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000090ull;
 }
@@ -461,7 +585,11 @@ static inline uint64_t CVMX_PCIERCX_CFG037(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG037(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000094ull;
 }
@@ -474,7 +602,11 @@ static inline uint64_t CVMX_PCIERCX_CFG038(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG038(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000098ull;
 }
@@ -487,7 +619,11 @@ static inline uint64_t CVMX_PCIERCX_CFG039(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG039(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000009Cull;
 }
@@ -500,7 +636,11 @@ static inline uint64_t CVMX_PCIERCX_CFG040(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG040(%lu) is invalid on this chip\n", block_id);
 	return 0x00000000000000A0ull;
 }
@@ -513,7 +653,11 @@ static inline uint64_t CVMX_PCIERCX_CFG041(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG041(%lu) is invalid on this chip\n", block_id);
 	return 0x00000000000000A4ull;
 }
@@ -526,7 +670,11 @@ static inline uint64_t CVMX_PCIERCX_CFG042(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG042(%lu) is invalid on this chip\n", block_id);
 	return 0x00000000000000A8ull;
 }
@@ -539,7 +687,11 @@ static inline uint64_t CVMX_PCIERCX_CFG064(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG064(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000100ull;
 }
@@ -552,7 +704,11 @@ static inline uint64_t CVMX_PCIERCX_CFG065(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG065(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000104ull;
 }
@@ -565,7 +721,11 @@ static inline uint64_t CVMX_PCIERCX_CFG066(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG066(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000108ull;
 }
@@ -578,7 +738,11 @@ static inline uint64_t CVMX_PCIERCX_CFG067(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG067(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000010Cull;
 }
@@ -591,7 +755,11 @@ static inline uint64_t CVMX_PCIERCX_CFG068(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG068(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000110ull;
 }
@@ -604,7 +772,11 @@ static inline uint64_t CVMX_PCIERCX_CFG069(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG069(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000114ull;
 }
@@ -617,7 +789,11 @@ static inline uint64_t CVMX_PCIERCX_CFG070(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG070(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000118ull;
 }
@@ -630,7 +806,11 @@ static inline uint64_t CVMX_PCIERCX_CFG071(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG071(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000011Cull;
 }
@@ -643,7 +823,11 @@ static inline uint64_t CVMX_PCIERCX_CFG072(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG072(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000120ull;
 }
@@ -656,7 +840,11 @@ static inline uint64_t CVMX_PCIERCX_CFG073(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG073(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000124ull;
 }
@@ -669,7 +857,11 @@ static inline uint64_t CVMX_PCIERCX_CFG074(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG074(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000128ull;
 }
@@ -682,7 +874,11 @@ static inline uint64_t CVMX_PCIERCX_CFG075(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG075(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000012Cull;
 }
@@ -695,7 +891,11 @@ static inline uint64_t CVMX_PCIERCX_CFG076(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG076(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000130ull;
 }
@@ -708,7 +908,11 @@ static inline uint64_t CVMX_PCIERCX_CFG077(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG077(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000134ull;
 }
@@ -721,7 +925,11 @@ static inline uint64_t CVMX_PCIERCX_CFG448(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG448(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000700ull;
 }
@@ -734,7 +942,11 @@ static inline uint64_t CVMX_PCIERCX_CFG449(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG449(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000704ull;
 }
@@ -747,7 +959,11 @@ static inline uint64_t CVMX_PCIERCX_CFG450(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG450(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000708ull;
 }
@@ -760,7 +976,11 @@ static inline uint64_t CVMX_PCIERCX_CFG451(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG451(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000070Cull;
 }
@@ -773,7 +993,11 @@ static inline uint64_t CVMX_PCIERCX_CFG452(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG452(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000710ull;
 }
@@ -786,7 +1010,11 @@ static inline uint64_t CVMX_PCIERCX_CFG453(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG453(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000714ull;
 }
@@ -799,7 +1027,11 @@ static inline uint64_t CVMX_PCIERCX_CFG454(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG454(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000718ull;
 }
@@ -812,7 +1044,11 @@ static inline uint64_t CVMX_PCIERCX_CFG455(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG455(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000071Cull;
 }
@@ -825,7 +1061,11 @@ static inline uint64_t CVMX_PCIERCX_CFG456(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG456(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000720ull;
 }
@@ -838,7 +1078,11 @@ static inline uint64_t CVMX_PCIERCX_CFG458(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG458(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000728ull;
 }
@@ -851,7 +1095,11 @@ static inline uint64_t CVMX_PCIERCX_CFG459(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG459(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000072Cull;
 }
@@ -864,7 +1112,11 @@ static inline uint64_t CVMX_PCIERCX_CFG460(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG460(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000730ull;
 }
@@ -877,7 +1129,11 @@ static inline uint64_t CVMX_PCIERCX_CFG461(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG461(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000734ull;
 }
@@ -890,7 +1146,11 @@ static inline uint64_t CVMX_PCIERCX_CFG462(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG462(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000738ull;
 }
@@ -903,7 +1163,11 @@ static inline uint64_t CVMX_PCIERCX_CFG463(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG463(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000073Cull;
 }
@@ -916,7 +1180,11 @@ static inline uint64_t CVMX_PCIERCX_CFG464(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG464(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000740ull;
 }
@@ -929,7 +1197,11 @@ static inline uint64_t CVMX_PCIERCX_CFG465(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG465(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000744ull;
 }
@@ -942,7 +1214,11 @@ static inline uint64_t CVMX_PCIERCX_CFG466(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG466(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000748ull;
 }
@@ -955,7 +1231,11 @@ static inline uint64_t CVMX_PCIERCX_CFG467(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG467(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000074Cull;
 }
@@ -968,7 +1248,11 @@ static inline uint64_t CVMX_PCIERCX_CFG468(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG468(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000750ull;
 }
@@ -981,7 +1265,11 @@ static inline uint64_t CVMX_PCIERCX_CFG490(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG490(%lu) is invalid on this chip\n", block_id);
 	return 0x00000000000007A8ull;
 }
@@ -994,7 +1282,11 @@ static inline uint64_t CVMX_PCIERCX_CFG491(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG491(%lu) is invalid on this chip\n", block_id);
 	return 0x00000000000007ACull;
 }
@@ -1007,7 +1299,11 @@ static inline uint64_t CVMX_PCIERCX_CFG492(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG492(%lu) is invalid on this chip\n", block_id);
 	return 0x00000000000007B0ull;
 }
@@ -1018,7 +1314,11 @@ static inline uint64_t CVMX_PCIERCX_CFG492(unsigned long block_id)
 static inline uint64_t CVMX_PCIERCX_CFG515(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG515(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000080Cull;
 }
@@ -1031,7 +1331,11 @@ static inline uint64_t CVMX_PCIERCX_CFG516(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG516(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000810ull;
 }
@@ -1044,7 +1348,11 @@ static inline uint64_t CVMX_PCIERCX_CFG517(unsigned long block_id)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PCIERCX_CFG517(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000814ull;
 }
@@ -1058,12 +1366,10 @@ static inline uint64_t CVMX_PCIERCX_CFG517(unsigned long block_id)
  * PCIE_CFG000 = First 32-bits of PCIE type 1 config space (Device ID and Vendor ID Register)
  *
  */
-union cvmx_pciercx_cfg000
-{
+union cvmx_pciercx_cfg000 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg000_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg000_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t devid                        : 16; /**< Device ID, writable through PEM(0..1)_CFG_WR
                                                          However, the application must not change this field. */
 	uint32_t vendid                       : 16; /**< Vendor ID, writable through PEM(0..1)_CFG_WR
@@ -1077,8 +1383,13 @@ union cvmx_pciercx_cfg000
 	struct cvmx_pciercx_cfg000_s          cn52xxp1;
 	struct cvmx_pciercx_cfg000_s          cn56xx;
 	struct cvmx_pciercx_cfg000_s          cn56xxp1;
+	struct cvmx_pciercx_cfg000_s          cn61xx;
 	struct cvmx_pciercx_cfg000_s          cn63xx;
 	struct cvmx_pciercx_cfg000_s          cn63xxp1;
+	struct cvmx_pciercx_cfg000_s          cn66xx;
+	struct cvmx_pciercx_cfg000_s          cn68xx;
+	struct cvmx_pciercx_cfg000_s          cn68xxp1;
+	struct cvmx_pciercx_cfg000_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg000 cvmx_pciercx_cfg000_t;
 
@@ -1088,12 +1399,10 @@ typedef union cvmx_pciercx_cfg000 cvmx_pciercx_cfg000_t;
  * PCIE_CFG001 = Second 32-bits of PCIE type 1 config space (Command/Status Register)
  *
  */
-union cvmx_pciercx_cfg001
-{
+union cvmx_pciercx_cfg001 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg001_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg001_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dpe                          : 1;  /**< Detected Parity Error */
 	uint32_t sse                          : 1;  /**< Signaled System Error */
 	uint32_t rma                          : 1;  /**< Received Master Abort */
@@ -1159,8 +1468,13 @@ union cvmx_pciercx_cfg001
 	struct cvmx_pciercx_cfg001_s          cn52xxp1;
 	struct cvmx_pciercx_cfg001_s          cn56xx;
 	struct cvmx_pciercx_cfg001_s          cn56xxp1;
+	struct cvmx_pciercx_cfg001_s          cn61xx;
 	struct cvmx_pciercx_cfg001_s          cn63xx;
 	struct cvmx_pciercx_cfg001_s          cn63xxp1;
+	struct cvmx_pciercx_cfg001_s          cn66xx;
+	struct cvmx_pciercx_cfg001_s          cn68xx;
+	struct cvmx_pciercx_cfg001_s          cn68xxp1;
+	struct cvmx_pciercx_cfg001_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg001 cvmx_pciercx_cfg001_t;
 
@@ -1170,12 +1484,10 @@ typedef union cvmx_pciercx_cfg001 cvmx_pciercx_cfg001_t;
  * PCIE_CFG002 = Third 32-bits of PCIE type 1 config space (Revision ID/Class Code Register)
  *
  */
-union cvmx_pciercx_cfg002
-{
+union cvmx_pciercx_cfg002 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg002_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg002_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t bcc                          : 8;  /**< Base Class Code, writable through PEM(0..1)_CFG_WR
                                                          However, the application must not change this field. */
 	uint32_t sc                           : 8;  /**< Subclass Code, writable through PEM(0..1)_CFG_WR
@@ -1195,8 +1507,13 @@ union cvmx_pciercx_cfg002
 	struct cvmx_pciercx_cfg002_s          cn52xxp1;
 	struct cvmx_pciercx_cfg002_s          cn56xx;
 	struct cvmx_pciercx_cfg002_s          cn56xxp1;
+	struct cvmx_pciercx_cfg002_s          cn61xx;
 	struct cvmx_pciercx_cfg002_s          cn63xx;
 	struct cvmx_pciercx_cfg002_s          cn63xxp1;
+	struct cvmx_pciercx_cfg002_s          cn66xx;
+	struct cvmx_pciercx_cfg002_s          cn68xx;
+	struct cvmx_pciercx_cfg002_s          cn68xxp1;
+	struct cvmx_pciercx_cfg002_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg002 cvmx_pciercx_cfg002_t;
 
@@ -1206,12 +1523,10 @@ typedef union cvmx_pciercx_cfg002 cvmx_pciercx_cfg002_t;
  * PCIE_CFG003 = Fourth 32-bits of PCIE type 1 config space (Cache Line Size/Master Latency Timer/Header Type Register/BIST Register)
  *
  */
-union cvmx_pciercx_cfg003
-{
+union cvmx_pciercx_cfg003 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg003_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg003_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t bist                         : 8;  /**< The BIST register functions are not supported.
                                                          All 8 bits of the BIST register are hardwired to 0. */
 	uint32_t mfd                          : 1;  /**< Multi Function Device
@@ -1238,8 +1553,13 @@ union cvmx_pciercx_cfg003
 	struct cvmx_pciercx_cfg003_s          cn52xxp1;
 	struct cvmx_pciercx_cfg003_s          cn56xx;
 	struct cvmx_pciercx_cfg003_s          cn56xxp1;
+	struct cvmx_pciercx_cfg003_s          cn61xx;
 	struct cvmx_pciercx_cfg003_s          cn63xx;
 	struct cvmx_pciercx_cfg003_s          cn63xxp1;
+	struct cvmx_pciercx_cfg003_s          cn66xx;
+	struct cvmx_pciercx_cfg003_s          cn68xx;
+	struct cvmx_pciercx_cfg003_s          cn68xxp1;
+	struct cvmx_pciercx_cfg003_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg003 cvmx_pciercx_cfg003_t;
 
@@ -1249,12 +1569,10 @@ typedef union cvmx_pciercx_cfg003 cvmx_pciercx_cfg003_t;
  * PCIE_CFG004 = Fifth 32-bits of PCIE type 1 config space (Base Address Register 0 - Low)
  *
  */
-union cvmx_pciercx_cfg004
-{
+union cvmx_pciercx_cfg004 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg004_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg004_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_0_31                : 32;
 #else
 	uint32_t reserved_0_31                : 32;
@@ -1264,8 +1582,13 @@ union cvmx_pciercx_cfg004
 	struct cvmx_pciercx_cfg004_s          cn52xxp1;
 	struct cvmx_pciercx_cfg004_s          cn56xx;
 	struct cvmx_pciercx_cfg004_s          cn56xxp1;
+	struct cvmx_pciercx_cfg004_s          cn61xx;
 	struct cvmx_pciercx_cfg004_s          cn63xx;
 	struct cvmx_pciercx_cfg004_s          cn63xxp1;
+	struct cvmx_pciercx_cfg004_s          cn66xx;
+	struct cvmx_pciercx_cfg004_s          cn68xx;
+	struct cvmx_pciercx_cfg004_s          cn68xxp1;
+	struct cvmx_pciercx_cfg004_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg004 cvmx_pciercx_cfg004_t;
 
@@ -1275,12 +1598,10 @@ typedef union cvmx_pciercx_cfg004 cvmx_pciercx_cfg004_t;
  * PCIE_CFG005 = Sixth 32-bits of PCIE type 1 config space (Base Address Register 0 - High)
  *
  */
-union cvmx_pciercx_cfg005
-{
+union cvmx_pciercx_cfg005 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg005_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg005_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_0_31                : 32;
 #else
 	uint32_t reserved_0_31                : 32;
@@ -1290,8 +1611,13 @@ union cvmx_pciercx_cfg005
 	struct cvmx_pciercx_cfg005_s          cn52xxp1;
 	struct cvmx_pciercx_cfg005_s          cn56xx;
 	struct cvmx_pciercx_cfg005_s          cn56xxp1;
+	struct cvmx_pciercx_cfg005_s          cn61xx;
 	struct cvmx_pciercx_cfg005_s          cn63xx;
 	struct cvmx_pciercx_cfg005_s          cn63xxp1;
+	struct cvmx_pciercx_cfg005_s          cn66xx;
+	struct cvmx_pciercx_cfg005_s          cn68xx;
+	struct cvmx_pciercx_cfg005_s          cn68xxp1;
+	struct cvmx_pciercx_cfg005_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg005 cvmx_pciercx_cfg005_t;
 
@@ -1301,12 +1627,10 @@ typedef union cvmx_pciercx_cfg005 cvmx_pciercx_cfg005_t;
  * PCIE_CFG006 = Seventh 32-bits of PCIE type 1 config space (Bus Number Registers)
  *
  */
-union cvmx_pciercx_cfg006
-{
+union cvmx_pciercx_cfg006 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg006_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg006_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t slt                          : 8;  /**< Secondary Latency Timer
                                                          Not applicable to PCI Express, hardwired to 0x00. */
 	uint32_t subbnum                      : 8;  /**< Subordinate Bus Number */
@@ -1323,8 +1647,13 @@ union cvmx_pciercx_cfg006
 	struct cvmx_pciercx_cfg006_s          cn52xxp1;
 	struct cvmx_pciercx_cfg006_s          cn56xx;
 	struct cvmx_pciercx_cfg006_s          cn56xxp1;
+	struct cvmx_pciercx_cfg006_s          cn61xx;
 	struct cvmx_pciercx_cfg006_s          cn63xx;
 	struct cvmx_pciercx_cfg006_s          cn63xxp1;
+	struct cvmx_pciercx_cfg006_s          cn66xx;
+	struct cvmx_pciercx_cfg006_s          cn68xx;
+	struct cvmx_pciercx_cfg006_s          cn68xxp1;
+	struct cvmx_pciercx_cfg006_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg006 cvmx_pciercx_cfg006_t;
 
@@ -1334,12 +1663,10 @@ typedef union cvmx_pciercx_cfg006 cvmx_pciercx_cfg006_t;
  * PCIE_CFG007 = Eighth 32-bits of PCIE type 1 config space (IO Base and IO Limit/Secondary Status Register)
  *
  */
-union cvmx_pciercx_cfg007
-{
+union cvmx_pciercx_cfg007 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg007_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg007_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dpe                          : 1;  /**< Detected Parity Error */
 	uint32_t sse                          : 1;  /**< Signaled System Error */
 	uint32_t rma                          : 1;  /**< Received Master Abort */
@@ -1391,8 +1718,13 @@ union cvmx_pciercx_cfg007
 	struct cvmx_pciercx_cfg007_s          cn52xxp1;
 	struct cvmx_pciercx_cfg007_s          cn56xx;
 	struct cvmx_pciercx_cfg007_s          cn56xxp1;
+	struct cvmx_pciercx_cfg007_s          cn61xx;
 	struct cvmx_pciercx_cfg007_s          cn63xx;
 	struct cvmx_pciercx_cfg007_s          cn63xxp1;
+	struct cvmx_pciercx_cfg007_s          cn66xx;
+	struct cvmx_pciercx_cfg007_s          cn68xx;
+	struct cvmx_pciercx_cfg007_s          cn68xxp1;
+	struct cvmx_pciercx_cfg007_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg007 cvmx_pciercx_cfg007_t;
 
@@ -1402,12 +1734,10 @@ typedef union cvmx_pciercx_cfg007 cvmx_pciercx_cfg007_t;
  * PCIE_CFG008 = Ninth 32-bits of PCIE type 1 config space (Memory Base and Memory Limit Register)
  *
  */
-union cvmx_pciercx_cfg008
-{
+union cvmx_pciercx_cfg008 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg008_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg008_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ml_addr                      : 12; /**< Memory Limit Address */
 	uint32_t reserved_16_19               : 4;
 	uint32_t mb_addr                      : 12; /**< Memory Base Address */
@@ -1423,8 +1753,13 @@ union cvmx_pciercx_cfg008
 	struct cvmx_pciercx_cfg008_s          cn52xxp1;
 	struct cvmx_pciercx_cfg008_s          cn56xx;
 	struct cvmx_pciercx_cfg008_s          cn56xxp1;
+	struct cvmx_pciercx_cfg008_s          cn61xx;
 	struct cvmx_pciercx_cfg008_s          cn63xx;
 	struct cvmx_pciercx_cfg008_s          cn63xxp1;
+	struct cvmx_pciercx_cfg008_s          cn66xx;
+	struct cvmx_pciercx_cfg008_s          cn68xx;
+	struct cvmx_pciercx_cfg008_s          cn68xxp1;
+	struct cvmx_pciercx_cfg008_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg008 cvmx_pciercx_cfg008_t;
 
@@ -1434,12 +1769,10 @@ typedef union cvmx_pciercx_cfg008 cvmx_pciercx_cfg008_t;
  * PCIE_CFG009 = Tenth 32-bits of PCIE type 1 config space (Prefetchable Memory Base and Limit Register)
  *
  */
-union cvmx_pciercx_cfg009
-{
+union cvmx_pciercx_cfg009 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg009_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg009_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t lmem_limit                   : 12; /**< Upper 12 bits of 32-bit Prefetchable Memory End Address */
 	uint32_t reserved_17_19               : 3;
 	uint32_t mem64b                       : 1;  /**< 64-Bit Memory Addressing
@@ -1468,8 +1801,13 @@ union cvmx_pciercx_cfg009
 	struct cvmx_pciercx_cfg009_s          cn52xxp1;
 	struct cvmx_pciercx_cfg009_s          cn56xx;
 	struct cvmx_pciercx_cfg009_s          cn56xxp1;
+	struct cvmx_pciercx_cfg009_s          cn61xx;
 	struct cvmx_pciercx_cfg009_s          cn63xx;
 	struct cvmx_pciercx_cfg009_s          cn63xxp1;
+	struct cvmx_pciercx_cfg009_s          cn66xx;
+	struct cvmx_pciercx_cfg009_s          cn68xx;
+	struct cvmx_pciercx_cfg009_s          cn68xxp1;
+	struct cvmx_pciercx_cfg009_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg009 cvmx_pciercx_cfg009_t;
 
@@ -1479,12 +1817,10 @@ typedef union cvmx_pciercx_cfg009 cvmx_pciercx_cfg009_t;
  * PCIE_CFG010 = Eleventh 32-bits of PCIE type 1 config space (Prefetchable Base Upper 32 Bits Register)
  *
  */
-union cvmx_pciercx_cfg010
-{
+union cvmx_pciercx_cfg010 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg010_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg010_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t umem_base                    : 32; /**< Upper 32 Bits of Base Address of Prefetchable Memory Space
                                                          Used only when 64-bit prefetchable memory addressing is
                                                          enabled. */
@@ -1496,8 +1832,13 @@ union cvmx_pciercx_cfg010
 	struct cvmx_pciercx_cfg010_s          cn52xxp1;
 	struct cvmx_pciercx_cfg010_s          cn56xx;
 	struct cvmx_pciercx_cfg010_s          cn56xxp1;
+	struct cvmx_pciercx_cfg010_s          cn61xx;
 	struct cvmx_pciercx_cfg010_s          cn63xx;
 	struct cvmx_pciercx_cfg010_s          cn63xxp1;
+	struct cvmx_pciercx_cfg010_s          cn66xx;
+	struct cvmx_pciercx_cfg010_s          cn68xx;
+	struct cvmx_pciercx_cfg010_s          cn68xxp1;
+	struct cvmx_pciercx_cfg010_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg010 cvmx_pciercx_cfg010_t;
 
@@ -1507,12 +1848,10 @@ typedef union cvmx_pciercx_cfg010 cvmx_pciercx_cfg010_t;
  * PCIE_CFG011 = Twelfth 32-bits of PCIE type 1 config space (Prefetchable Limit Upper 32 Bits Register)
  *
  */
-union cvmx_pciercx_cfg011
-{
+union cvmx_pciercx_cfg011 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg011_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg011_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t umem_limit                   : 32; /**< Upper 32 Bits of Limit Address of Prefetchable Memory Space
                                                          Used only when 64-bit prefetchable memory addressing is
                                                          enabled. */
@@ -1524,8 +1863,13 @@ union cvmx_pciercx_cfg011
 	struct cvmx_pciercx_cfg011_s          cn52xxp1;
 	struct cvmx_pciercx_cfg011_s          cn56xx;
 	struct cvmx_pciercx_cfg011_s          cn56xxp1;
+	struct cvmx_pciercx_cfg011_s          cn61xx;
 	struct cvmx_pciercx_cfg011_s          cn63xx;
 	struct cvmx_pciercx_cfg011_s          cn63xxp1;
+	struct cvmx_pciercx_cfg011_s          cn66xx;
+	struct cvmx_pciercx_cfg011_s          cn68xx;
+	struct cvmx_pciercx_cfg011_s          cn68xxp1;
+	struct cvmx_pciercx_cfg011_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg011 cvmx_pciercx_cfg011_t;
 
@@ -1535,12 +1879,10 @@ typedef union cvmx_pciercx_cfg011 cvmx_pciercx_cfg011_t;
  * PCIE_CFG012 = Thirteenth 32-bits of PCIE type 1 config space (IO Base and Limit Upper 16 Bits Register)
  *
  */
-union cvmx_pciercx_cfg012
-{
+union cvmx_pciercx_cfg012 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg012_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg012_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t uio_limit                    : 16; /**< Upper 16 Bits of I/O Limit (if 32-bit I/O decoding is supported
                                                          for devices on the secondary side) */
 	uint32_t uio_base                     : 16; /**< Upper 16 Bits of I/O Base (if 32-bit I/O decoding is supported
@@ -1554,8 +1896,13 @@ union cvmx_pciercx_cfg012
 	struct cvmx_pciercx_cfg012_s          cn52xxp1;
 	struct cvmx_pciercx_cfg012_s          cn56xx;
 	struct cvmx_pciercx_cfg012_s          cn56xxp1;
+	struct cvmx_pciercx_cfg012_s          cn61xx;
 	struct cvmx_pciercx_cfg012_s          cn63xx;
 	struct cvmx_pciercx_cfg012_s          cn63xxp1;
+	struct cvmx_pciercx_cfg012_s          cn66xx;
+	struct cvmx_pciercx_cfg012_s          cn68xx;
+	struct cvmx_pciercx_cfg012_s          cn68xxp1;
+	struct cvmx_pciercx_cfg012_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg012 cvmx_pciercx_cfg012_t;
 
@@ -1565,12 +1912,10 @@ typedef union cvmx_pciercx_cfg012 cvmx_pciercx_cfg012_t;
  * PCIE_CFG013 = Fourteenth 32-bits of PCIE type 1 config space (Capability Pointer Register)
  *
  */
-union cvmx_pciercx_cfg013
-{
+union cvmx_pciercx_cfg013 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg013_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg013_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_8_31                : 24;
 	uint32_t cp                           : 8;  /**< First Capability Pointer.
                                                          Points to Power Management Capability structure by
@@ -1585,8 +1930,13 @@ union cvmx_pciercx_cfg013
 	struct cvmx_pciercx_cfg013_s          cn52xxp1;
 	struct cvmx_pciercx_cfg013_s          cn56xx;
 	struct cvmx_pciercx_cfg013_s          cn56xxp1;
+	struct cvmx_pciercx_cfg013_s          cn61xx;
 	struct cvmx_pciercx_cfg013_s          cn63xx;
 	struct cvmx_pciercx_cfg013_s          cn63xxp1;
+	struct cvmx_pciercx_cfg013_s          cn66xx;
+	struct cvmx_pciercx_cfg013_s          cn68xx;
+	struct cvmx_pciercx_cfg013_s          cn68xxp1;
+	struct cvmx_pciercx_cfg013_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg013 cvmx_pciercx_cfg013_t;
 
@@ -1596,12 +1946,10 @@ typedef union cvmx_pciercx_cfg013 cvmx_pciercx_cfg013_t;
  * PCIE_CFG014 = Fifteenth 32-bits of PCIE type 1 config space (Expansion ROM Base Address Register)
  *
  */
-union cvmx_pciercx_cfg014
-{
+union cvmx_pciercx_cfg014 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg014_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg014_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_0_31                : 32;
 #else
 	uint32_t reserved_0_31                : 32;
@@ -1611,8 +1959,13 @@ union cvmx_pciercx_cfg014
 	struct cvmx_pciercx_cfg014_s          cn52xxp1;
 	struct cvmx_pciercx_cfg014_s          cn56xx;
 	struct cvmx_pciercx_cfg014_s          cn56xxp1;
+	struct cvmx_pciercx_cfg014_s          cn61xx;
 	struct cvmx_pciercx_cfg014_s          cn63xx;
 	struct cvmx_pciercx_cfg014_s          cn63xxp1;
+	struct cvmx_pciercx_cfg014_s          cn66xx;
+	struct cvmx_pciercx_cfg014_s          cn68xx;
+	struct cvmx_pciercx_cfg014_s          cn68xxp1;
+	struct cvmx_pciercx_cfg014_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg014 cvmx_pciercx_cfg014_t;
 
@@ -1622,12 +1975,10 @@ typedef union cvmx_pciercx_cfg014 cvmx_pciercx_cfg014_t;
  * PCIE_CFG015 = Sixteenth 32-bits of PCIE type 1 config space (Interrupt Line Register/Interrupt Pin/Bridge Control Register)
  *
  */
-union cvmx_pciercx_cfg015
-{
+union cvmx_pciercx_cfg015 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg015_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg015_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_28_31               : 4;
 	uint32_t dtsees                       : 1;  /**< Discard Timer SERR Enable Status
                                                          Not applicable to PCI Express, hardwired to 0. */
@@ -1682,8 +2033,13 @@ union cvmx_pciercx_cfg015
 	struct cvmx_pciercx_cfg015_s          cn52xxp1;
 	struct cvmx_pciercx_cfg015_s          cn56xx;
 	struct cvmx_pciercx_cfg015_s          cn56xxp1;
+	struct cvmx_pciercx_cfg015_s          cn61xx;
 	struct cvmx_pciercx_cfg015_s          cn63xx;
 	struct cvmx_pciercx_cfg015_s          cn63xxp1;
+	struct cvmx_pciercx_cfg015_s          cn66xx;
+	struct cvmx_pciercx_cfg015_s          cn68xx;
+	struct cvmx_pciercx_cfg015_s          cn68xxp1;
+	struct cvmx_pciercx_cfg015_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg015 cvmx_pciercx_cfg015_t;
 
@@ -1695,12 +2051,10 @@ typedef union cvmx_pciercx_cfg015 cvmx_pciercx_cfg015_t;
  * Power Management Next Item Pointer/
  * Power Management Capabilities Register)
  */
-union cvmx_pciercx_cfg016
-{
+union cvmx_pciercx_cfg016 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg016_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg016_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t pmes                         : 5;  /**< PME_Support
                                                          A value of 0 for any bit indicates that the
                                                          device (or function) is not capable of generating PME Messages
@@ -1745,8 +2099,13 @@ union cvmx_pciercx_cfg016
 	struct cvmx_pciercx_cfg016_s          cn52xxp1;
 	struct cvmx_pciercx_cfg016_s          cn56xx;
 	struct cvmx_pciercx_cfg016_s          cn56xxp1;
+	struct cvmx_pciercx_cfg016_s          cn61xx;
 	struct cvmx_pciercx_cfg016_s          cn63xx;
 	struct cvmx_pciercx_cfg016_s          cn63xxp1;
+	struct cvmx_pciercx_cfg016_s          cn66xx;
+	struct cvmx_pciercx_cfg016_s          cn68xx;
+	struct cvmx_pciercx_cfg016_s          cn68xxp1;
+	struct cvmx_pciercx_cfg016_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg016 cvmx_pciercx_cfg016_t;
 
@@ -1756,12 +2115,10 @@ typedef union cvmx_pciercx_cfg016 cvmx_pciercx_cfg016_t;
  * PCIE_CFG017 = Eighteenth 32-bits of PCIE type 1 config space (Power Management Control and Status Register)
  *
  */
-union cvmx_pciercx_cfg017
-{
+union cvmx_pciercx_cfg017 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg017_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg017_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t pmdia                        : 8;  /**< Data register for additional information (not supported) */
 	uint32_t bpccee                       : 1;  /**< Bus Power/Clock Control Enable, hardwired to 0 */
 	uint32_t bd3h                         : 1;  /**< B2/B3 Support, hardwired to 0 */
@@ -1804,8 +2161,13 @@ union cvmx_pciercx_cfg017
 	struct cvmx_pciercx_cfg017_s          cn52xxp1;
 	struct cvmx_pciercx_cfg017_s          cn56xx;
 	struct cvmx_pciercx_cfg017_s          cn56xxp1;
+	struct cvmx_pciercx_cfg017_s          cn61xx;
 	struct cvmx_pciercx_cfg017_s          cn63xx;
 	struct cvmx_pciercx_cfg017_s          cn63xxp1;
+	struct cvmx_pciercx_cfg017_s          cn66xx;
+	struct cvmx_pciercx_cfg017_s          cn68xx;
+	struct cvmx_pciercx_cfg017_s          cn68xxp1;
+	struct cvmx_pciercx_cfg017_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg017 cvmx_pciercx_cfg017_t;
 
@@ -1817,13 +2179,12 @@ typedef union cvmx_pciercx_cfg017 cvmx_pciercx_cfg017_t;
  *  MSI Next Item Pointer/
  *  MSI Control Register)
  */
-union cvmx_pciercx_cfg020
-{
+union cvmx_pciercx_cfg020 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg020_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint32_t reserved_24_31               : 8;
+	struct cvmx_pciercx_cfg020_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t pvm                          : 1;  /**< Per-vector masking capable */
 	uint32_t m64                          : 1;  /**< 64-bit Address Capable, writable through PEM(0..1)_CFG_WR
                                                          However, the application must not change this field. */
 	uint32_t mme                          : 3;  /**< Multiple Message Enabled
@@ -1849,15 +2210,51 @@ union cvmx_pciercx_cfg020
 	uint32_t mmc                          : 3;
 	uint32_t mme                          : 3;
 	uint32_t m64                          : 1;
-	uint32_t reserved_24_31               : 8;
+	uint32_t pvm                          : 1;
+	uint32_t reserved_25_31               : 7;
 #endif
 	} s;
-	struct cvmx_pciercx_cfg020_s          cn52xx;
-	struct cvmx_pciercx_cfg020_s          cn52xxp1;
-	struct cvmx_pciercx_cfg020_s          cn56xx;
-	struct cvmx_pciercx_cfg020_s          cn56xxp1;
-	struct cvmx_pciercx_cfg020_s          cn63xx;
-	struct cvmx_pciercx_cfg020_s          cn63xxp1;
+	struct cvmx_pciercx_cfg020_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_24_31               : 8;
+	uint32_t m64                          : 1;  /**< 64-bit Address Capable, writable through PESC(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t mme                          : 3;  /**< Multiple Message Enabled
+                                                         Indicates that multiple Message mode is enabled by system
+                                                         software. The number of Messages enabled must be less than
+                                                         or equal to the Multiple Message Capable value. */
+	uint32_t mmc                          : 3;  /**< Multiple Message Capable, writable through PESC(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t msien                        : 1;  /**< MSI Enabled
+                                                         When set, INTx must be disabled.
+                                                         This bit must never be set, as internal-MSI is not supported in
+                                                         RC mode. (Note that this has no effect on external MSI, which
+                                                         will be commonly used in RC mode.) */
+	uint32_t ncp                          : 8;  /**< Next Capability Pointer
+                                                         Points to PCI Express Capabilities by default,
+                                                         writable through PESC(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t msicid                       : 8;  /**< MSI Capability ID */
+#else
+	uint32_t msicid                       : 8;
+	uint32_t ncp                          : 8;
+	uint32_t msien                        : 1;
+	uint32_t mmc                          : 3;
+	uint32_t mme                          : 3;
+	uint32_t m64                          : 1;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} cn52xx;
+	struct cvmx_pciercx_cfg020_cn52xx     cn52xxp1;
+	struct cvmx_pciercx_cfg020_cn52xx     cn56xx;
+	struct cvmx_pciercx_cfg020_cn52xx     cn56xxp1;
+	struct cvmx_pciercx_cfg020_s          cn61xx;
+	struct cvmx_pciercx_cfg020_cn52xx     cn63xx;
+	struct cvmx_pciercx_cfg020_cn52xx     cn63xxp1;
+	struct cvmx_pciercx_cfg020_cn52xx     cn66xx;
+	struct cvmx_pciercx_cfg020_cn52xx     cn68xx;
+	struct cvmx_pciercx_cfg020_cn52xx     cn68xxp1;
+	struct cvmx_pciercx_cfg020_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg020 cvmx_pciercx_cfg020_t;
 
@@ -1867,12 +2264,10 @@ typedef union cvmx_pciercx_cfg020 cvmx_pciercx_cfg020_t;
  * PCIE_CFG021 = Twenty-second 32-bits of PCIE type 1 config space (MSI Lower 32 Bits Address Register)
  *
  */
-union cvmx_pciercx_cfg021
-{
+union cvmx_pciercx_cfg021 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg021_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg021_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t lmsi                         : 30; /**< Lower 32-bit Address */
 	uint32_t reserved_0_1                 : 2;
 #else
@@ -1884,8 +2279,13 @@ union cvmx_pciercx_cfg021
 	struct cvmx_pciercx_cfg021_s          cn52xxp1;
 	struct cvmx_pciercx_cfg021_s          cn56xx;
 	struct cvmx_pciercx_cfg021_s          cn56xxp1;
+	struct cvmx_pciercx_cfg021_s          cn61xx;
 	struct cvmx_pciercx_cfg021_s          cn63xx;
 	struct cvmx_pciercx_cfg021_s          cn63xxp1;
+	struct cvmx_pciercx_cfg021_s          cn66xx;
+	struct cvmx_pciercx_cfg021_s          cn68xx;
+	struct cvmx_pciercx_cfg021_s          cn68xxp1;
+	struct cvmx_pciercx_cfg021_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg021 cvmx_pciercx_cfg021_t;
 
@@ -1895,12 +2295,10 @@ typedef union cvmx_pciercx_cfg021 cvmx_pciercx_cfg021_t;
  * PCIE_CFG022 = Twenty-third 32-bits of PCIE type 1 config space (MSI Upper 32 bits Address Register)
  *
  */
-union cvmx_pciercx_cfg022
-{
+union cvmx_pciercx_cfg022 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg022_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg022_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t umsi                         : 32; /**< Upper 32-bit Address */
 #else
 	uint32_t umsi                         : 32;
@@ -1910,8 +2308,13 @@ union cvmx_pciercx_cfg022
 	struct cvmx_pciercx_cfg022_s          cn52xxp1;
 	struct cvmx_pciercx_cfg022_s          cn56xx;
 	struct cvmx_pciercx_cfg022_s          cn56xxp1;
+	struct cvmx_pciercx_cfg022_s          cn61xx;
 	struct cvmx_pciercx_cfg022_s          cn63xx;
 	struct cvmx_pciercx_cfg022_s          cn63xxp1;
+	struct cvmx_pciercx_cfg022_s          cn66xx;
+	struct cvmx_pciercx_cfg022_s          cn68xx;
+	struct cvmx_pciercx_cfg022_s          cn68xxp1;
+	struct cvmx_pciercx_cfg022_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg022 cvmx_pciercx_cfg022_t;
 
@@ -1921,12 +2324,10 @@ typedef union cvmx_pciercx_cfg022 cvmx_pciercx_cfg022_t;
  * PCIE_CFG023 = Twenty-fourth 32-bits of PCIE type 1 config space (MSI Data Register)
  *
  */
-union cvmx_pciercx_cfg023
-{
+union cvmx_pciercx_cfg023 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg023_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg023_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_16_31               : 16;
 	uint32_t msimd                        : 16; /**< MSI Data
                                                          Pattern assigned by system software, bits [4:0] are Or-ed with
@@ -1940,8 +2341,13 @@ union cvmx_pciercx_cfg023
 	struct cvmx_pciercx_cfg023_s          cn52xxp1;
 	struct cvmx_pciercx_cfg023_s          cn56xx;
 	struct cvmx_pciercx_cfg023_s          cn56xxp1;
+	struct cvmx_pciercx_cfg023_s          cn61xx;
 	struct cvmx_pciercx_cfg023_s          cn63xx;
 	struct cvmx_pciercx_cfg023_s          cn63xxp1;
+	struct cvmx_pciercx_cfg023_s          cn66xx;
+	struct cvmx_pciercx_cfg023_s          cn68xx;
+	struct cvmx_pciercx_cfg023_s          cn68xxp1;
+	struct cvmx_pciercx_cfg023_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg023 cvmx_pciercx_cfg023_t;
 
@@ -1952,12 +2358,10 @@ typedef union cvmx_pciercx_cfg023 cvmx_pciercx_cfg023_t;
  * (PCI Express Capabilities List Register/
  *  PCI Express Capabilities Register)
  */
-union cvmx_pciercx_cfg028
-{
+union cvmx_pciercx_cfg028 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg028_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg028_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_30_31               : 2;
 	uint32_t imn                          : 5;  /**< Interrupt Message Number
                                                          Updated by hardware, writable through PEM(0..1)_CFG_WR.
@@ -1987,8 +2391,13 @@ union cvmx_pciercx_cfg028
 	struct cvmx_pciercx_cfg028_s          cn52xxp1;
 	struct cvmx_pciercx_cfg028_s          cn56xx;
 	struct cvmx_pciercx_cfg028_s          cn56xxp1;
+	struct cvmx_pciercx_cfg028_s          cn61xx;
 	struct cvmx_pciercx_cfg028_s          cn63xx;
 	struct cvmx_pciercx_cfg028_s          cn63xxp1;
+	struct cvmx_pciercx_cfg028_s          cn66xx;
+	struct cvmx_pciercx_cfg028_s          cn68xx;
+	struct cvmx_pciercx_cfg028_s          cn68xxp1;
+	struct cvmx_pciercx_cfg028_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg028 cvmx_pciercx_cfg028_t;
 
@@ -1998,12 +2407,10 @@ typedef union cvmx_pciercx_cfg028 cvmx_pciercx_cfg028_t;
  * PCIE_CFG029 = Thirtieth 32-bits of PCIE type 1 config space (Device Capabilities Register)
  *
  */
-union cvmx_pciercx_cfg029
-{
+union cvmx_pciercx_cfg029 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg029_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg029_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_28_31               : 4;
 	uint32_t cspls                        : 2;  /**< Captured Slot Power Limit Scale
                                                          Not applicable for RC port, upstream port only. */
@@ -2046,8 +2453,13 @@ union cvmx_pciercx_cfg029
 	struct cvmx_pciercx_cfg029_s          cn52xxp1;
 	struct cvmx_pciercx_cfg029_s          cn56xx;
 	struct cvmx_pciercx_cfg029_s          cn56xxp1;
+	struct cvmx_pciercx_cfg029_s          cn61xx;
 	struct cvmx_pciercx_cfg029_s          cn63xx;
 	struct cvmx_pciercx_cfg029_s          cn63xxp1;
+	struct cvmx_pciercx_cfg029_s          cn66xx;
+	struct cvmx_pciercx_cfg029_s          cn68xx;
+	struct cvmx_pciercx_cfg029_s          cn68xxp1;
+	struct cvmx_pciercx_cfg029_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg029 cvmx_pciercx_cfg029_t;
 
@@ -2057,16 +2469,13 @@ typedef union cvmx_pciercx_cfg029 cvmx_pciercx_cfg029_t;
  * PCIE_CFG030 = Thirty-first 32-bits of PCIE type 1 config space
  * (Device Control Register/Device Status Register)
  */
-union cvmx_pciercx_cfg030
-{
+union cvmx_pciercx_cfg030 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg030_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg030_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_22_31               : 10;
 	uint32_t tp                           : 1;  /**< Transaction Pending
-                                                         Set to 1 when Non-Posted Requests are not yet completed
-                                                         and clear when they are completed. */
+                                                         Hard-wired to 0. */
 	uint32_t ap_d                         : 1;  /**< Aux Power Detected
                                                          Set to 1 if Aux power detected. */
 	uint32_t ur_d                         : 1;  /**< Unsupported Request Detected
@@ -2126,7 +2535,8 @@ union cvmx_pciercx_cfg030
                                                                for Peer-to-Peer to function properly.
                                                          Note: DPI_SLI_PRT#_CFG[MPS] must also be set to the same
                                                                value for proper functionality. */
-	uint32_t ro_en                        : 1;  /**< Enable Relaxed Ordering */
+	uint32_t ro_en                        : 1;  /**< Enable Relaxed Ordering
+                                                         This bit is not used. */
 	uint32_t ur_en                        : 1;  /**< Unsupported Request Reporting Enable */
 	uint32_t fe_en                        : 1;  /**< Fatal Error Reporting Enable */
 	uint32_t nfe_en                       : 1;  /**< Non-Fatal Error Reporting Enable */
@@ -2157,8 +2567,13 @@ union cvmx_pciercx_cfg030
 	struct cvmx_pciercx_cfg030_s          cn52xxp1;
 	struct cvmx_pciercx_cfg030_s          cn56xx;
 	struct cvmx_pciercx_cfg030_s          cn56xxp1;
+	struct cvmx_pciercx_cfg030_s          cn61xx;
 	struct cvmx_pciercx_cfg030_s          cn63xx;
 	struct cvmx_pciercx_cfg030_s          cn63xxp1;
+	struct cvmx_pciercx_cfg030_s          cn66xx;
+	struct cvmx_pciercx_cfg030_s          cn68xx;
+	struct cvmx_pciercx_cfg030_s          cn68xxp1;
+	struct cvmx_pciercx_cfg030_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg030 cvmx_pciercx_cfg030_t;
 
@@ -2168,16 +2583,18 @@ typedef union cvmx_pciercx_cfg030 cvmx_pciercx_cfg030_t;
  * PCIE_CFG031 = Thirty-second 32-bits of PCIE type 1 config space
  * (Link Capabilities Register)
  */
-union cvmx_pciercx_cfg031
-{
+union cvmx_pciercx_cfg031 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg031_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint32_t pnum                         : 8;  /**< Port Number, writable through PEM(0..1)_CFG_WR
+	struct cvmx_pciercx_cfg031_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t pnum                         : 8;  /**< Port Number
+                                                         writable through PEM(0..1)_CFG_WR, however the application
+                                                         must not change this field. */
+	uint32_t reserved_23_23               : 1;
+	uint32_t aspm                         : 1;  /**< ASPM Optionality Compliance */
+	uint32_t lbnc                         : 1;  /**< Link Bandwidth Notification Capability
+                                                         Set to 1 for Root Complex devices. writable through PEM(0..1)_CFG_WR.
                                                          However, the application must not change this field. */
-	uint32_t reserved_22_23               : 2;
-	uint32_t lbnc                         : 1;  /**< Link Bandwith Notification Capability */
 	uint32_t dllarc                       : 1;  /**< Data Link Layer Active Reporting Capable
                                                          Set to 1 for Root Complex devices and 0 for Endpoint devices. */
 	uint32_t sderc                        : 1;  /**< Surprise Down Error Reporting Capable
@@ -2200,11 +2617,13 @@ union cvmx_pciercx_cfg031
                                                          However, the application must not change this field. */
 	uint32_t mlw                          : 6;  /**< Maximum Link Width
                                                          The default value is the value you specify during hardware
-                                                         configuration (x1, x4, x8, or x16), writable through PEM(0..1)_CFG_WR. */
+                                                         configuration (x1 or x2) writable through PEM(0..1)_CFG_WR. */
 	uint32_t mls                          : 4;  /**< Maximum Link Speed
-                                                         The following values are accepted:
-                                                         0001b: 2.5 GHz supported
-                                                         0010b: 5.0 GHz and 2.5 GHz supported
+                                                         The reset value of this field is controlled by a value sent from
+                                                         the lsb of the MIO_QLM#_SPD register.
+                                                         qlm#_spd[0]   RST_VALUE   NOTE
+                                                         1             0001b       2.5 GHz supported
+                                                         0             0010b       5.0 GHz and 2.5 GHz supported
                                                          This field is writable through PEM(0..1)_CFG_WR.
                                                          However, the application must not change this field. */
 #else
@@ -2217,16 +2636,72 @@ union cvmx_pciercx_cfg031
 	uint32_t sderc                        : 1;
 	uint32_t dllarc                       : 1;
 	uint32_t lbnc                         : 1;
-	uint32_t reserved_22_23               : 2;
+	uint32_t aspm                         : 1;
+	uint32_t reserved_23_23               : 1;
 	uint32_t pnum                         : 8;
 #endif
 	} s;
-	struct cvmx_pciercx_cfg031_s          cn52xx;
-	struct cvmx_pciercx_cfg031_s          cn52xxp1;
-	struct cvmx_pciercx_cfg031_s          cn56xx;
-	struct cvmx_pciercx_cfg031_s          cn56xxp1;
-	struct cvmx_pciercx_cfg031_s          cn63xx;
-	struct cvmx_pciercx_cfg031_s          cn63xxp1;
+	struct cvmx_pciercx_cfg031_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t pnum                         : 8;  /**< Port Number, writable through PESC(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t reserved_22_23               : 2;
+	uint32_t lbnc                         : 1;  /**< Link Bandwith Notification Capability */
+	uint32_t dllarc                       : 1;  /**< Data Link Layer Active Reporting Capable
+                                                         Set to 1 for Root Complex devices and 0 for Endpoint devices. */
+	uint32_t sderc                        : 1;  /**< Surprise Down Error Reporting Capable
+                                                         Not supported, hardwired to 0x0. */
+	uint32_t cpm                          : 1;  /**< Clock Power Management
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through PESC(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t l1el                         : 3;  /**< L1 Exit Latency
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through PESC(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t l0el                         : 3;  /**< L0s Exit Latency
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through PESC(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t aslpms                       : 2;  /**< Active State Link PM Support
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through PESC(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t mlw                          : 6;  /**< Maximum Link Width
+                                                         The default value is the value you specify during hardware
+                                                         configuration (x1, x4, x8, or x16), writable through PESC(0..1)_CFG_WR.
+                                                         The SW needs to set this to 0x4 or 0x2 depending on the max
+                                                         number of lanes (QLM_CFG == 1 set to 0x4 else 0x2). */
+	uint32_t mls                          : 4;  /**< Maximum Link Speed
+                                                         Default value is 0x1 for 2.5 Gbps Link.
+                                                         This field is writable through PESC(0..1)_CFG_WR.
+                                                         However, 0x1 is the
+                                                         only supported value. Therefore, the application must not write
+                                                         any value other than 0x1 to this field. */
+#else
+	uint32_t mls                          : 4;
+	uint32_t mlw                          : 6;
+	uint32_t aslpms                       : 2;
+	uint32_t l0el                         : 3;
+	uint32_t l1el                         : 3;
+	uint32_t cpm                          : 1;
+	uint32_t sderc                        : 1;
+	uint32_t dllarc                       : 1;
+	uint32_t lbnc                         : 1;
+	uint32_t reserved_22_23               : 2;
+	uint32_t pnum                         : 8;
+#endif
+	} cn52xx;
+	struct cvmx_pciercx_cfg031_cn52xx     cn52xxp1;
+	struct cvmx_pciercx_cfg031_cn52xx     cn56xx;
+	struct cvmx_pciercx_cfg031_cn52xx     cn56xxp1;
+	struct cvmx_pciercx_cfg031_s          cn61xx;
+	struct cvmx_pciercx_cfg031_cn52xx     cn63xx;
+	struct cvmx_pciercx_cfg031_cn52xx     cn63xxp1;
+	struct cvmx_pciercx_cfg031_s          cn66xx;
+	struct cvmx_pciercx_cfg031_s          cn68xx;
+	struct cvmx_pciercx_cfg031_cn52xx     cn68xxp1;
+	struct cvmx_pciercx_cfg031_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg031 cvmx_pciercx_cfg031_t;
 
@@ -2236,14 +2711,26 @@ typedef union cvmx_pciercx_cfg031 cvmx_pciercx_cfg031_t;
  * PCIE_CFG032 = Thirty-third 32-bits of PCIE type 1 config space
  * (Link Control Register/Link Status Register)
  */
-union cvmx_pciercx_cfg032
-{
+union cvmx_pciercx_cfg032 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg032_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint32_t lab                          : 1;  /**< Link Autonomous Bandwidth Status */
-	uint32_t lbm                          : 1;  /**< Link Bandwidth Management Status */
+	struct cvmx_pciercx_cfg032_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t lab                          : 1;  /**< Link Autonomous Bandwidth Status
+                                                         this bit is set to indicate that hardware has autonomously
+                                                         changed Link speed or width, without the Port transitioning
+                                                         through DL_Down status, for reasons other than to attempt
+                                                         to correct unreliable Link operation. */
+	uint32_t lbm                          : 1;  /**< Link Bandwidth Management Status
+                                                         This bit is set to indicate either of the following has
+                                                         occurred without the Port transitioning through DL_DOWN status
+                                                         o A link retraining has completed following a write of 1b to
+                                                           the Retrain Link bit
+                                                         o Hardware has changed the Link speed or width to attempt to
+                                                           correct unreliable Link operation, either through a LTSSM
+                                                           timeout of higher level process.  This bit must be set if
+                                                           the Physical Layer reports a speed or width change was
+                                                           inititiated by the Downstream component tha was not
+                                                           indicated as an autonomous change */
 	uint32_t dlla                         : 1;  /**< Data Link Layer Active */
 	uint32_t scc                          : 1;  /**< Slot Clock Configuration
                                                          Indicates that the component uses the same physical reference
@@ -2254,16 +2741,19 @@ union cvmx_pciercx_cfg032
 	uint32_t lt                           : 1;  /**< Link Training */
 	uint32_t reserved_26_26               : 1;
 	uint32_t nlw                          : 6;  /**< Negotiated Link Width
-                                                         Set automatically by hardware after Link initialization. */
+                                                         Set automatically by hardware after Link initialization.
+                                                         Value is undefined when link is not up. */
 	uint32_t ls                           : 4;  /**< Link Speed
-                                                         The negotiated Link speed: 2.5 Gbps */
+                                                         0001 == The negotiated Link speed: 2.5 Gbps
+                                                         0010 == The negotiated Link speed: 5.0 Gbps
+                                                         0100 == The negotiated Link speed: 8.0 Gbps (Not Supported) */
 	uint32_t reserved_12_15               : 4;
 	uint32_t lab_int_enb                  : 1;  /**< Link Autonomous Bandwidth Interrupt Enable
-                                                         This interrupt is for Gen2 and is not supported. This bit should
-                                                         always be written to zero. */
+                                                         When set, enables the generation of an interrupt to indicate
+                                                         that the Link Autonomous Bandwidth Status bit has been set. */
 	uint32_t lbm_int_enb                  : 1;  /**< Link Bandwidth Management Interrupt Enable
-                                                         This interrupt is for Gen2 and is not supported. This bit should
-                                                         always be written to zero. */
+                                                         When set, enables the generation of an interrupt to indicate
+                                                         that the Link Bandwidth Management Status bit has been set. */
 	uint32_t hawd                         : 1;  /**< Hardware Autonomous Width Disable
                                                          (Not Supported) */
 	uint32_t ecpm                         : 1;  /**< Enable Clock Power Management
@@ -2305,8 +2795,13 @@ union cvmx_pciercx_cfg032
 	struct cvmx_pciercx_cfg032_s          cn52xxp1;
 	struct cvmx_pciercx_cfg032_s          cn56xx;
 	struct cvmx_pciercx_cfg032_s          cn56xxp1;
+	struct cvmx_pciercx_cfg032_s          cn61xx;
 	struct cvmx_pciercx_cfg032_s          cn63xx;
 	struct cvmx_pciercx_cfg032_s          cn63xxp1;
+	struct cvmx_pciercx_cfg032_s          cn66xx;
+	struct cvmx_pciercx_cfg032_s          cn68xx;
+	struct cvmx_pciercx_cfg032_s          cn68xxp1;
+	struct cvmx_pciercx_cfg032_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg032 cvmx_pciercx_cfg032_t;
 
@@ -2316,12 +2811,10 @@ typedef union cvmx_pciercx_cfg032 cvmx_pciercx_cfg032_t;
  * PCIE_CFG033 = Thirty-fourth 32-bits of PCIE type 1 config space
  * (Slot Capabilities Register)
  */
-union cvmx_pciercx_cfg033
-{
+union cvmx_pciercx_cfg033 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg033_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg033_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ps_num                       : 13; /**< Physical Slot Number, writable through PEM(0..1)_CFG_WR
                                                          However, the application must not change this field. */
 	uint32_t nccs                         : 1;  /**< No Command Complete Support, writable through PEM(0..1)_CFG_WR
@@ -2363,8 +2856,13 @@ union cvmx_pciercx_cfg033
 	struct cvmx_pciercx_cfg033_s          cn52xxp1;
 	struct cvmx_pciercx_cfg033_s          cn56xx;
 	struct cvmx_pciercx_cfg033_s          cn56xxp1;
+	struct cvmx_pciercx_cfg033_s          cn61xx;
 	struct cvmx_pciercx_cfg033_s          cn63xx;
 	struct cvmx_pciercx_cfg033_s          cn63xxp1;
+	struct cvmx_pciercx_cfg033_s          cn66xx;
+	struct cvmx_pciercx_cfg033_s          cn68xx;
+	struct cvmx_pciercx_cfg033_s          cn68xxp1;
+	struct cvmx_pciercx_cfg033_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg033 cvmx_pciercx_cfg033_t;
 
@@ -2374,12 +2872,10 @@ typedef union cvmx_pciercx_cfg033 cvmx_pciercx_cfg033_t;
  * PCIE_CFG034 = Thirty-fifth 32-bits of PCIE type 1 config space
  * (Slot Control Register/Slot Status Register)
  */
-union cvmx_pciercx_cfg034
-{
+union cvmx_pciercx_cfg034 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg034_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg034_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_25_31               : 7;
 	uint32_t dlls_c                       : 1;  /**< Data Link Layer State Changed */
 	uint32_t emis                         : 1;  /**< Electromechanical Interlock Status */
@@ -2431,8 +2927,13 @@ union cvmx_pciercx_cfg034
 	struct cvmx_pciercx_cfg034_s          cn52xxp1;
 	struct cvmx_pciercx_cfg034_s          cn56xx;
 	struct cvmx_pciercx_cfg034_s          cn56xxp1;
+	struct cvmx_pciercx_cfg034_s          cn61xx;
 	struct cvmx_pciercx_cfg034_s          cn63xx;
 	struct cvmx_pciercx_cfg034_s          cn63xxp1;
+	struct cvmx_pciercx_cfg034_s          cn66xx;
+	struct cvmx_pciercx_cfg034_s          cn68xx;
+	struct cvmx_pciercx_cfg034_s          cn68xxp1;
+	struct cvmx_pciercx_cfg034_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg034 cvmx_pciercx_cfg034_t;
 
@@ -2442,12 +2943,10 @@ typedef union cvmx_pciercx_cfg034 cvmx_pciercx_cfg034_t;
  * PCIE_CFG035 = Thirty-sixth 32-bits of PCIE type 1 config space
  * (Root Control Register/Root Capabilities Register)
  */
-union cvmx_pciercx_cfg035
-{
+union cvmx_pciercx_cfg035 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg035_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg035_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_17_31               : 15;
 	uint32_t crssv                        : 1;  /**< CRS Software Visibility
                                                          Not supported, hardwired to 0x0. */
@@ -2473,8 +2972,13 @@ union cvmx_pciercx_cfg035
 	struct cvmx_pciercx_cfg035_s          cn52xxp1;
 	struct cvmx_pciercx_cfg035_s          cn56xx;
 	struct cvmx_pciercx_cfg035_s          cn56xxp1;
+	struct cvmx_pciercx_cfg035_s          cn61xx;
 	struct cvmx_pciercx_cfg035_s          cn63xx;
 	struct cvmx_pciercx_cfg035_s          cn63xxp1;
+	struct cvmx_pciercx_cfg035_s          cn66xx;
+	struct cvmx_pciercx_cfg035_s          cn68xx;
+	struct cvmx_pciercx_cfg035_s          cn68xxp1;
+	struct cvmx_pciercx_cfg035_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg035 cvmx_pciercx_cfg035_t;
 
@@ -2484,12 +2988,10 @@ typedef union cvmx_pciercx_cfg035 cvmx_pciercx_cfg035_t;
  * PCIE_CFG036 = Thirty-seventh 32-bits of PCIE type 1 config space
  * (Root Status Register)
  */
-union cvmx_pciercx_cfg036
-{
+union cvmx_pciercx_cfg036 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg036_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg036_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_18_31               : 14;
 	uint32_t pme_pend                     : 1;  /**< PME Pending */
 	uint32_t pme_stat                     : 1;  /**< PME Status */
@@ -2505,8 +3007,13 @@ union cvmx_pciercx_cfg036
 	struct cvmx_pciercx_cfg036_s          cn52xxp1;
 	struct cvmx_pciercx_cfg036_s          cn56xx;
 	struct cvmx_pciercx_cfg036_s          cn56xxp1;
+	struct cvmx_pciercx_cfg036_s          cn61xx;
 	struct cvmx_pciercx_cfg036_s          cn63xx;
 	struct cvmx_pciercx_cfg036_s          cn63xxp1;
+	struct cvmx_pciercx_cfg036_s          cn66xx;
+	struct cvmx_pciercx_cfg036_s          cn68xx;
+	struct cvmx_pciercx_cfg036_s          cn68xxp1;
+	struct cvmx_pciercx_cfg036_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg036 cvmx_pciercx_cfg036_t;
 
@@ -2516,12 +3023,47 @@ typedef union cvmx_pciercx_cfg036 cvmx_pciercx_cfg036_t;
  * PCIE_CFG037 = Thirty-eighth 32-bits of PCIE type 1 config space
  * (Device Capabilities 2 Register)
  */
-union cvmx_pciercx_cfg037
-{
+union cvmx_pciercx_cfg037 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg037_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg037_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t obffs                        : 2;  /**< Optimized Buffer Flush Fill (OBFF) Supported
+                                                         (Not Supported) */
+	uint32_t reserved_12_17               : 6;
+	uint32_t ltrs                         : 1;  /**< Latency Tolerance Reporting (LTR) Mechanism Supported
+                                                         (Not Supported) */
+	uint32_t noroprpr                     : 1;  /**< No RO-enabled PR-PR Passing
+                                                         When set, the routing element never carries out the passing
+                                                         permitted in the Relaxed Ordering Model. */
+	uint32_t atom128s                     : 1;  /**< 128-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom64s                      : 1;  /**< 64-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom32s                      : 1;  /**< 32-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom_ops                     : 1;  /**< AtomicOp Routing Supported
+                                                         (Not Supported) */
+	uint32_t reserved_5_5                 : 1;
+	uint32_t ctds                         : 1;  /**< Completion Timeout Disable Supported */
+	uint32_t ctrs                         : 4;  /**< Completion Timeout Ranges Supported */
+#else
+	uint32_t ctrs                         : 4;
+	uint32_t ctds                         : 1;
+	uint32_t reserved_5_5                 : 1;
+	uint32_t atom_ops                     : 1;
+	uint32_t atom32s                      : 1;
+	uint32_t atom64s                      : 1;
+	uint32_t atom128s                     : 1;
+	uint32_t noroprpr                     : 1;
+	uint32_t ltrs                         : 1;
+	uint32_t reserved_12_17               : 6;
+	uint32_t obffs                        : 2;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg037_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_5_31                : 27;
 	uint32_t ctds                         : 1;  /**< Completion Timeout Disable Supported */
 	uint32_t ctrs                         : 4;  /**< Completion Timeout Ranges Supported
@@ -2533,13 +3075,125 @@ union cvmx_pciercx_cfg037
 	uint32_t ctds                         : 1;
 	uint32_t reserved_5_31                : 27;
 #endif
-	} s;
-	struct cvmx_pciercx_cfg037_s          cn52xx;
-	struct cvmx_pciercx_cfg037_s          cn52xxp1;
-	struct cvmx_pciercx_cfg037_s          cn56xx;
-	struct cvmx_pciercx_cfg037_s          cn56xxp1;
-	struct cvmx_pciercx_cfg037_s          cn63xx;
-	struct cvmx_pciercx_cfg037_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pciercx_cfg037_cn52xx     cn52xxp1;
+	struct cvmx_pciercx_cfg037_cn52xx     cn56xx;
+	struct cvmx_pciercx_cfg037_cn52xx     cn56xxp1;
+	struct cvmx_pciercx_cfg037_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_14_31               : 18;
+	uint32_t tph                          : 2;  /**< TPH Completer Supported
+                                                         (Not Supported) */
+	uint32_t reserved_11_11               : 1;
+	uint32_t noroprpr                     : 1;  /**< No RO-enabled PR-PR Passing
+                                                         When set, the routing element never carries out the passing
+                                                         permitted in the Relaxed Ordering Model. */
+	uint32_t atom128s                     : 1;  /**< 128-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom64s                      : 1;  /**< 64-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom32s                      : 1;  /**< 32-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom_ops                     : 1;  /**< AtomicOp Routing Supported
+                                                         (Not Supported) */
+	uint32_t ari_fw                       : 1;  /**< ARI Forwarding Supported
+                                                         (Not Supported) */
+	uint32_t ctds                         : 1;  /**< Completion Timeout Disable Supported */
+	uint32_t ctrs                         : 4;  /**< Completion Timeout Ranges Supported */
+#else
+	uint32_t ctrs                         : 4;
+	uint32_t ctds                         : 1;
+	uint32_t ari_fw                       : 1;
+	uint32_t atom_ops                     : 1;
+	uint32_t atom32s                      : 1;
+	uint32_t atom64s                      : 1;
+	uint32_t atom128s                     : 1;
+	uint32_t noroprpr                     : 1;
+	uint32_t reserved_11_11               : 1;
+	uint32_t tph                          : 2;
+	uint32_t reserved_14_31               : 18;
+#endif
+	} cn61xx;
+	struct cvmx_pciercx_cfg037_cn52xx     cn63xx;
+	struct cvmx_pciercx_cfg037_cn52xx     cn63xxp1;
+	struct cvmx_pciercx_cfg037_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_14_31               : 18;
+	uint32_t tph                          : 2;  /**< TPH Completer Supported
+                                                         (Not Supported) */
+	uint32_t reserved_11_11               : 1;
+	uint32_t noroprpr                     : 1;  /**< No RO-enabled PR-PR Passing
+                                                         When set, the routing element never carries out the passing
+                                                         permitted in the Relaxed Ordering Model. */
+	uint32_t atom128s                     : 1;  /**< 128-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom64s                      : 1;  /**< 64-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom32s                      : 1;  /**< 32-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom_ops                     : 1;  /**< AtomicOp Routing Supported
+                                                         (Not Supported) */
+	uint32_t ari                          : 1;  /**< Alternate Routing ID Forwarding Supported
+                                                         (Not Supported) */
+	uint32_t ctds                         : 1;  /**< Completion Timeout Disable Supported */
+	uint32_t ctrs                         : 4;  /**< Completion Timeout Ranges Supported */
+#else
+	uint32_t ctrs                         : 4;
+	uint32_t ctds                         : 1;
+	uint32_t ari                          : 1;
+	uint32_t atom_ops                     : 1;
+	uint32_t atom32s                      : 1;
+	uint32_t atom64s                      : 1;
+	uint32_t atom128s                     : 1;
+	uint32_t noroprpr                     : 1;
+	uint32_t reserved_11_11               : 1;
+	uint32_t tph                          : 2;
+	uint32_t reserved_14_31               : 18;
+#endif
+	} cn66xx;
+	struct cvmx_pciercx_cfg037_cn66xx     cn68xx;
+	struct cvmx_pciercx_cfg037_cn66xx     cn68xxp1;
+	struct cvmx_pciercx_cfg037_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t obffs                        : 2;  /**< Optimized Buffer Flush Fill (OBFF) Supported
+                                                         (Not Supported) */
+	uint32_t reserved_14_17               : 4;
+	uint32_t tphs                         : 2;  /**< TPH Completer Supported
+                                                         (Not Supported) */
+	uint32_t ltrs                         : 1;  /**< Latency Tolerance Reporting (LTR) Mechanism Supported
+                                                         (Not Supported) */
+	uint32_t noroprpr                     : 1;  /**< No RO-enabled PR-PR Passing
+                                                         When set, the routing element never carries out the passing
+                                                         permitted in the Relaxed Ordering Model. */
+	uint32_t atom128s                     : 1;  /**< 128-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom64s                      : 1;  /**< 64-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom32s                      : 1;  /**< 32-bit AtomicOp Supported
+                                                         (Not Supported) */
+	uint32_t atom_ops                     : 1;  /**< AtomicOp Routing Supported
+                                                         (Not Supported) */
+	uint32_t ari_fw                       : 1;  /**< ARI Forwarding Supported
+                                                         (Not Supported) */
+	uint32_t ctds                         : 1;  /**< Completion Timeout Disable Supported */
+	uint32_t ctrs                         : 4;  /**< Completion Timeout Ranges Supported */
+#else
+	uint32_t ctrs                         : 4;
+	uint32_t ctds                         : 1;
+	uint32_t ari_fw                       : 1;
+	uint32_t atom_ops                     : 1;
+	uint32_t atom32s                      : 1;
+	uint32_t atom64s                      : 1;
+	uint32_t atom128s                     : 1;
+	uint32_t noroprpr                     : 1;
+	uint32_t ltrs                         : 1;
+	uint32_t tphs                         : 2;
+	uint32_t reserved_14_17               : 4;
+	uint32_t obffs                        : 2;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} cnf71xx;
 };
 typedef union cvmx_pciercx_cfg037 cvmx_pciercx_cfg037_t;
 
@@ -2549,12 +3203,54 @@ typedef union cvmx_pciercx_cfg037 cvmx_pciercx_cfg037_t;
  * PCIE_CFG038 = Thirty-ninth 32-bits of PCIE type 1 config space
  * (Device Control 2 Register)
  */
-union cvmx_pciercx_cfg038
-{
+union cvmx_pciercx_cfg038 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg038_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg038_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_15_31               : 17;
+	uint32_t obffe                        : 2;  /**< Optimized Buffer Flush Fill (OBFF) Enable
+                                                         (Not Supported) */
+	uint32_t reserved_11_12               : 2;
+	uint32_t ltre                         : 1;  /**< Latency Tolerance Reporting (LTR) Mechanism Enable
+                                                         (Not Supported) */
+	uint32_t id0_cp                       : 1;  /**< ID Based Ordering Completion Enable
+                                                         (Not Supported) */
+	uint32_t id0_rq                       : 1;  /**< ID Based Ordering Request Enable
+                                                         (Not Supported) */
+	uint32_t atom_op_eb                   : 1;  /**< AtomicOp Egress Blocking
+                                                         (Not Supported)m */
+	uint32_t atom_op                      : 1;  /**< AtomicOp Requester Enable
+                                                         (Not Supported) */
+	uint32_t ari                          : 1;  /**< Alternate Routing ID Forwarding Supported
+                                                         (Not Supported) */
+	uint32_t ctd                          : 1;  /**< Completion Timeout Disable */
+	uint32_t ctv                          : 4;  /**< Completion Timeout Value
+                                                         o 0000b Default range: 16 ms to 55 ms
+                                                         o 0001b 50 us to 100 us
+                                                         o 0010b 1 ms to 10 ms
+                                                         o 0101b 16 ms to 55 ms
+                                                         o 0110b 65 ms to 210 ms
+                                                         o 1001b 260 ms to 900 ms
+                                                         o 1010b 1 s to 3.5 s
+                                                         o 1101b 4 s to 13 s
+                                                         o 1110b 17 s to 64 s
+                                                         Values not defined are reserved */
+#else
+	uint32_t ctv                          : 4;
+	uint32_t ctd                          : 1;
+	uint32_t ari                          : 1;
+	uint32_t atom_op                      : 1;
+	uint32_t atom_op_eb                   : 1;
+	uint32_t id0_rq                       : 1;
+	uint32_t id0_cp                       : 1;
+	uint32_t ltre                         : 1;
+	uint32_t reserved_11_12               : 2;
+	uint32_t obffe                        : 2;
+	uint32_t reserved_15_31               : 17;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg038_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_5_31                : 27;
 	uint32_t ctd                          : 1;  /**< Completion Timeout Disable */
 	uint32_t ctv                          : 4;  /**< Completion Timeout Value
@@ -2565,13 +3261,52 @@ union cvmx_pciercx_cfg038
 	uint32_t ctd                          : 1;
 	uint32_t reserved_5_31                : 27;
 #endif
-	} s;
-	struct cvmx_pciercx_cfg038_s          cn52xx;
-	struct cvmx_pciercx_cfg038_s          cn52xxp1;
-	struct cvmx_pciercx_cfg038_s          cn56xx;
-	struct cvmx_pciercx_cfg038_s          cn56xxp1;
-	struct cvmx_pciercx_cfg038_s          cn63xx;
-	struct cvmx_pciercx_cfg038_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pciercx_cfg038_cn52xx     cn52xxp1;
+	struct cvmx_pciercx_cfg038_cn52xx     cn56xx;
+	struct cvmx_pciercx_cfg038_cn52xx     cn56xxp1;
+	struct cvmx_pciercx_cfg038_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_10_31               : 22;
+	uint32_t id0_cp                       : 1;  /**< ID Based Ordering Completion Enable
+                                                         (Not Supported) */
+	uint32_t id0_rq                       : 1;  /**< ID Based Ordering Request Enable
+                                                         (Not Supported) */
+	uint32_t atom_op_eb                   : 1;  /**< AtomicOp Egress Blocking
+                                                         (Not Supported)m */
+	uint32_t atom_op                      : 1;  /**< AtomicOp Requester Enable
+                                                         (Not Supported) */
+	uint32_t ari                          : 1;  /**< Alternate Routing ID Forwarding Supported
+                                                         (Not Supported) */
+	uint32_t ctd                          : 1;  /**< Completion Timeout Disable */
+	uint32_t ctv                          : 4;  /**< Completion Timeout Value
+                                                         o 0000b Default range: 16 ms to 55 ms
+                                                         o 0001b 50 us to 100 us
+                                                         o 0010b 1 ms to 10 ms
+                                                         o 0101b 16 ms to 55 ms
+                                                         o 0110b 65 ms to 210 ms
+                                                         o 1001b 260 ms to 900 ms
+                                                         o 1010b 1 s to 3.5 s
+                                                         o 1101b 4 s to 13 s
+                                                         o 1110b 17 s to 64 s
+                                                         Values not defined are reserved */
+#else
+	uint32_t ctv                          : 4;
+	uint32_t ctd                          : 1;
+	uint32_t ari                          : 1;
+	uint32_t atom_op                      : 1;
+	uint32_t atom_op_eb                   : 1;
+	uint32_t id0_rq                       : 1;
+	uint32_t id0_cp                       : 1;
+	uint32_t reserved_10_31               : 22;
+#endif
+	} cn61xx;
+	struct cvmx_pciercx_cfg038_cn52xx     cn63xx;
+	struct cvmx_pciercx_cfg038_cn52xx     cn63xxp1;
+	struct cvmx_pciercx_cfg038_cn61xx     cn66xx;
+	struct cvmx_pciercx_cfg038_cn61xx     cn68xx;
+	struct cvmx_pciercx_cfg038_cn61xx     cn68xxp1;
+	struct cvmx_pciercx_cfg038_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg038 cvmx_pciercx_cfg038_t;
 
@@ -2581,23 +3316,52 @@ typedef union cvmx_pciercx_cfg038 cvmx_pciercx_cfg038_t;
  * PCIE_CFG039 = Fourtieth 32-bits of PCIE type 1 config space
  * (Link Capabilities 2 Register)
  */
-union cvmx_pciercx_cfg039
-{
+union cvmx_pciercx_cfg039 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg039_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg039_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_9_31                : 23;
+	uint32_t cls                          : 1;  /**< Crosslink Supported */
+	uint32_t slsv                         : 7;  /**< Supported Link Speeds Vector
+                                                         Indicates the supported Link speeds of the associated Port.
+                                                         For each bit, a value of 1b indicates that the cooresponding
+                                                         Link speed is supported; otherwise, the Link speed is not
+                                                         supported.
+                                                         Bit definitions are:
+                                                         Bit 1 2.5 GT/s
+                                                         Bit 2 5.0 GT/s
+                                                         Bit 3 8.0 GT/s (Not Supported)
+                                                         Bits 7:4 reserved
+                                                         The reset value of this field is controlled by a value sent from
+                                                         the lsb of the MIO_QLM#_SPD register
+                                                         qlm#_spd[0]   RST_VALUE   NOTE
+                                                         1             0001b       2.5 GHz supported
+                                                         0             0011b       5.0 GHz and 2.5 GHz supported */
+	uint32_t reserved_0_0                 : 1;
+#else
+	uint32_t reserved_0_0                 : 1;
+	uint32_t slsv                         : 7;
+	uint32_t cls                          : 1;
+	uint32_t reserved_9_31                : 23;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg039_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_0_31                : 32;
 #else
 	uint32_t reserved_0_31                : 32;
 #endif
-	} s;
-	struct cvmx_pciercx_cfg039_s          cn52xx;
-	struct cvmx_pciercx_cfg039_s          cn52xxp1;
-	struct cvmx_pciercx_cfg039_s          cn56xx;
-	struct cvmx_pciercx_cfg039_s          cn56xxp1;
+	} cn52xx;
+	struct cvmx_pciercx_cfg039_cn52xx     cn52xxp1;
+	struct cvmx_pciercx_cfg039_cn52xx     cn56xx;
+	struct cvmx_pciercx_cfg039_cn52xx     cn56xxp1;
+	struct cvmx_pciercx_cfg039_s          cn61xx;
 	struct cvmx_pciercx_cfg039_s          cn63xx;
-	struct cvmx_pciercx_cfg039_s          cn63xxp1;
+	struct cvmx_pciercx_cfg039_cn52xx     cn63xxp1;
+	struct cvmx_pciercx_cfg039_s          cn66xx;
+	struct cvmx_pciercx_cfg039_s          cn68xx;
+	struct cvmx_pciercx_cfg039_s          cn68xxp1;
+	struct cvmx_pciercx_cfg039_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg039 cvmx_pciercx_cfg039_t;
 
@@ -2607,12 +3371,10 @@ typedef union cvmx_pciercx_cfg039 cvmx_pciercx_cfg039_t;
  * PCIE_CFG040 = Fourty-first 32-bits of PCIE type 1 config space
  * (Link Control 2 Register/Link Status 2 Register)
  */
-union cvmx_pciercx_cfg040
-{
+union cvmx_pciercx_cfg040 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg040_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg040_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_17_31               : 15;
 	uint32_t cdl                          : 1;  /**< Current De-emphasis Level
                                                          When the Link is operating at 5 GT/s speed, this bit
@@ -2642,7 +3404,7 @@ union cvmx_pciercx_cfg040
                                                          Compliance state. */
 	uint32_t tm                           : 3;  /**< Transmit Margin
                                                          This field controls the value of the non-de-emphasized
-                                                         voltage level at the Transmitter pins:
+                                                         voltage level at the Transmitter signals:
                                                           - 000: 800-1200 mV for full swing 400-600 mV for half-swing
                                                           - 001-010: values must be monotonic with a non-zero slope
                                                           - 011: 200-400 mV for full-swing and 100-200 mV for halfswing
@@ -2678,6 +3440,7 @@ union cvmx_pciercx_cfg040
                                                          the upstream component in its training sequences:
                                                            - 0001: 2.5Gb/s Target Link Speed
                                                            - 0010: 5Gb/s Target Link Speed
+                                                           - 0100: 8Gb/s Target Link Speed (Not Supported)
                                                          All other encodings are reserved.
                                                          If a value is written to this field that does not correspond to
                                                          a speed included in the Supported Link Speeds field, the
@@ -2686,8 +3449,11 @@ union cvmx_pciercx_cfg040
                                                          used to set the target compliance mode speed when
                                                          software is using the Enter Compliance bit to force a link
                                                          into compliance mode.
-                                                         Out of reset this will have a value of 1 or 2 which is
-                                                         selected by qlmCfgx[1]. */
+                                                         The reset value of this field is controlled by a value sent from
+                                                         the lsb of the MIO_QLM#_SPD register.
+                                                         qlm#_spd[0]   RST_VALUE   NOTE
+                                                         1             0001b       2.5 GHz supported
+                                                         0             0010b       5.0 GHz and 2.5 GHz supported */
 #else
 	uint32_t tls                          : 4;
 	uint32_t ec                           : 1;
@@ -2702,9 +3468,8 @@ union cvmx_pciercx_cfg040
 	uint32_t reserved_17_31               : 15;
 #endif
 	} s;
-	struct cvmx_pciercx_cfg040_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg040_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_0_31                : 32;
 #else
 	uint32_t reserved_0_31                : 32;
@@ -2713,8 +3478,13 @@ union cvmx_pciercx_cfg040
 	struct cvmx_pciercx_cfg040_cn52xx     cn52xxp1;
 	struct cvmx_pciercx_cfg040_cn52xx     cn56xx;
 	struct cvmx_pciercx_cfg040_cn52xx     cn56xxp1;
+	struct cvmx_pciercx_cfg040_s          cn61xx;
 	struct cvmx_pciercx_cfg040_s          cn63xx;
 	struct cvmx_pciercx_cfg040_s          cn63xxp1;
+	struct cvmx_pciercx_cfg040_s          cn66xx;
+	struct cvmx_pciercx_cfg040_s          cn68xx;
+	struct cvmx_pciercx_cfg040_s          cn68xxp1;
+	struct cvmx_pciercx_cfg040_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg040 cvmx_pciercx_cfg040_t;
 
@@ -2724,12 +3494,10 @@ typedef union cvmx_pciercx_cfg040 cvmx_pciercx_cfg040_t;
  * PCIE_CFG041 = Fourty-second 32-bits of PCIE type 1 config space
  * (Slot Capabilities 2 Register)
  */
-union cvmx_pciercx_cfg041
-{
+union cvmx_pciercx_cfg041 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg041_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg041_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_0_31                : 32;
 #else
 	uint32_t reserved_0_31                : 32;
@@ -2739,8 +3507,13 @@ union cvmx_pciercx_cfg041
 	struct cvmx_pciercx_cfg041_s          cn52xxp1;
 	struct cvmx_pciercx_cfg041_s          cn56xx;
 	struct cvmx_pciercx_cfg041_s          cn56xxp1;
+	struct cvmx_pciercx_cfg041_s          cn61xx;
 	struct cvmx_pciercx_cfg041_s          cn63xx;
 	struct cvmx_pciercx_cfg041_s          cn63xxp1;
+	struct cvmx_pciercx_cfg041_s          cn66xx;
+	struct cvmx_pciercx_cfg041_s          cn68xx;
+	struct cvmx_pciercx_cfg041_s          cn68xxp1;
+	struct cvmx_pciercx_cfg041_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg041 cvmx_pciercx_cfg041_t;
 
@@ -2750,12 +3523,10 @@ typedef union cvmx_pciercx_cfg041 cvmx_pciercx_cfg041_t;
  * PCIE_CFG042 = Fourty-third 32-bits of PCIE type 1 config space
  * (Slot Control 2 Register/Slot Status 2 Register)
  */
-union cvmx_pciercx_cfg042
-{
+union cvmx_pciercx_cfg042 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg042_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg042_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_0_31                : 32;
 #else
 	uint32_t reserved_0_31                : 32;
@@ -2765,8 +3536,13 @@ union cvmx_pciercx_cfg042
 	struct cvmx_pciercx_cfg042_s          cn52xxp1;
 	struct cvmx_pciercx_cfg042_s          cn56xx;
 	struct cvmx_pciercx_cfg042_s          cn56xxp1;
+	struct cvmx_pciercx_cfg042_s          cn61xx;
 	struct cvmx_pciercx_cfg042_s          cn63xx;
 	struct cvmx_pciercx_cfg042_s          cn63xxp1;
+	struct cvmx_pciercx_cfg042_s          cn66xx;
+	struct cvmx_pciercx_cfg042_s          cn68xx;
+	struct cvmx_pciercx_cfg042_s          cn68xxp1;
+	struct cvmx_pciercx_cfg042_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg042 cvmx_pciercx_cfg042_t;
 
@@ -2774,14 +3550,12 @@ typedef union cvmx_pciercx_cfg042 cvmx_pciercx_cfg042_t;
  * cvmx_pcierc#_cfg064
  *
  * PCIE_CFG064 = Sixty-fifth 32-bits of PCIE type 1 config space
- * (PCI Express Enhanced Capability Header)
+ * (PCI Express Extended Capability Header)
  */
-union cvmx_pciercx_cfg064
-{
+union cvmx_pciercx_cfg064 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg064_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg064_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t nco                          : 12; /**< Next Capability Offset */
 	uint32_t cv                           : 4;  /**< Capability Version */
 	uint32_t pcieec                       : 16; /**< PCIE Express Extended Capability */
@@ -2795,8 +3569,13 @@ union cvmx_pciercx_cfg064
 	struct cvmx_pciercx_cfg064_s          cn52xxp1;
 	struct cvmx_pciercx_cfg064_s          cn56xx;
 	struct cvmx_pciercx_cfg064_s          cn56xxp1;
+	struct cvmx_pciercx_cfg064_s          cn61xx;
 	struct cvmx_pciercx_cfg064_s          cn63xx;
 	struct cvmx_pciercx_cfg064_s          cn63xxp1;
+	struct cvmx_pciercx_cfg064_s          cn66xx;
+	struct cvmx_pciercx_cfg064_s          cn68xx;
+	struct cvmx_pciercx_cfg064_s          cn68xxp1;
+	struct cvmx_pciercx_cfg064_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg064 cvmx_pciercx_cfg064_t;
 
@@ -2806,12 +3585,51 @@ typedef union cvmx_pciercx_cfg064 cvmx_pciercx_cfg064_t;
  * PCIE_CFG065 = Sixty-sixth 32-bits of PCIE type 1 config space
  * (Uncorrectable Error Status Register)
  */
-union cvmx_pciercx_cfg065
-{
+union cvmx_pciercx_cfg065 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg065_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg065_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t uatombs                      : 1;  /**< Unsupported AtomicOp Egress Blocked Status */
+	uint32_t reserved_23_23               : 1;
+	uint32_t ucies                        : 1;  /**< Uncorrectable Internal Error Status */
+	uint32_t reserved_21_21               : 1;
+	uint32_t ures                         : 1;  /**< Unsupported Request Error Status */
+	uint32_t ecrces                       : 1;  /**< ECRC Error Status */
+	uint32_t mtlps                        : 1;  /**< Malformed TLP Status */
+	uint32_t ros                          : 1;  /**< Receiver Overflow Status */
+	uint32_t ucs                          : 1;  /**< Unexpected Completion Status */
+	uint32_t cas                          : 1;  /**< Completer Abort Status */
+	uint32_t cts                          : 1;  /**< Completion Timeout Status */
+	uint32_t fcpes                        : 1;  /**< Flow Control Protocol Error Status */
+	uint32_t ptlps                        : 1;  /**< Poisoned TLP Status */
+	uint32_t reserved_6_11                : 6;
+	uint32_t sdes                         : 1;  /**< Surprise Down Error Status (not supported) */
+	uint32_t dlpes                        : 1;  /**< Data Link Protocol Error Status */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpes                        : 1;
+	uint32_t sdes                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t ptlps                        : 1;
+	uint32_t fcpes                        : 1;
+	uint32_t cts                          : 1;
+	uint32_t cas                          : 1;
+	uint32_t ucs                          : 1;
+	uint32_t ros                          : 1;
+	uint32_t mtlps                        : 1;
+	uint32_t ecrces                       : 1;
+	uint32_t ures                         : 1;
+	uint32_t reserved_21_21               : 1;
+	uint32_t ucies                        : 1;
+	uint32_t reserved_23_23               : 1;
+	uint32_t uatombs                      : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg065_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_21_31               : 11;
 	uint32_t ures                         : 1;  /**< Unsupported Request Error Status */
 	uint32_t ecrces                       : 1;  /**< ECRC Error Status */
@@ -2842,13 +3660,53 @@ union cvmx_pciercx_cfg065
 	uint32_t ures                         : 1;
 	uint32_t reserved_21_31               : 11;
 #endif
-	} s;
-	struct cvmx_pciercx_cfg065_s          cn52xx;
-	struct cvmx_pciercx_cfg065_s          cn52xxp1;
-	struct cvmx_pciercx_cfg065_s          cn56xx;
-	struct cvmx_pciercx_cfg065_s          cn56xxp1;
-	struct cvmx_pciercx_cfg065_s          cn63xx;
-	struct cvmx_pciercx_cfg065_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pciercx_cfg065_cn52xx     cn52xxp1;
+	struct cvmx_pciercx_cfg065_cn52xx     cn56xx;
+	struct cvmx_pciercx_cfg065_cn52xx     cn56xxp1;
+	struct cvmx_pciercx_cfg065_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t uatombs                      : 1;  /**< Unsupported AtomicOp Egress Blocked Status */
+	uint32_t reserved_21_23               : 3;
+	uint32_t ures                         : 1;  /**< Unsupported Request Error Status */
+	uint32_t ecrces                       : 1;  /**< ECRC Error Status */
+	uint32_t mtlps                        : 1;  /**< Malformed TLP Status */
+	uint32_t ros                          : 1;  /**< Receiver Overflow Status */
+	uint32_t ucs                          : 1;  /**< Unexpected Completion Status */
+	uint32_t cas                          : 1;  /**< Completer Abort Status */
+	uint32_t cts                          : 1;  /**< Completion Timeout Status */
+	uint32_t fcpes                        : 1;  /**< Flow Control Protocol Error Status */
+	uint32_t ptlps                        : 1;  /**< Poisoned TLP Status */
+	uint32_t reserved_6_11                : 6;
+	uint32_t sdes                         : 1;  /**< Surprise Down Error Status (not supported) */
+	uint32_t dlpes                        : 1;  /**< Data Link Protocol Error Status */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpes                        : 1;
+	uint32_t sdes                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t ptlps                        : 1;
+	uint32_t fcpes                        : 1;
+	uint32_t cts                          : 1;
+	uint32_t cas                          : 1;
+	uint32_t ucs                          : 1;
+	uint32_t ros                          : 1;
+	uint32_t mtlps                        : 1;
+	uint32_t ecrces                       : 1;
+	uint32_t ures                         : 1;
+	uint32_t reserved_21_23               : 3;
+	uint32_t uatombs                      : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} cn61xx;
+	struct cvmx_pciercx_cfg065_cn52xx     cn63xx;
+	struct cvmx_pciercx_cfg065_cn52xx     cn63xxp1;
+	struct cvmx_pciercx_cfg065_cn61xx     cn66xx;
+	struct cvmx_pciercx_cfg065_cn61xx     cn68xx;
+	struct cvmx_pciercx_cfg065_cn52xx     cn68xxp1;
+	struct cvmx_pciercx_cfg065_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg065 cvmx_pciercx_cfg065_t;
 
@@ -2858,12 +3716,51 @@ typedef union cvmx_pciercx_cfg065 cvmx_pciercx_cfg065_t;
  * PCIE_CFG066 = Sixty-seventh 32-bits of PCIE type 1 config space
  * (Uncorrectable Error Mask Register)
  */
-union cvmx_pciercx_cfg066
-{
+union cvmx_pciercx_cfg066 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg066_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg066_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t uatombm                      : 1;  /**< Unsupported AtomicOp Egress Blocked Mask */
+	uint32_t reserved_23_23               : 1;
+	uint32_t uciem                        : 1;  /**< Uncorrectable Internal Error Mask */
+	uint32_t reserved_21_21               : 1;
+	uint32_t urem                         : 1;  /**< Unsupported Request Error Mask */
+	uint32_t ecrcem                       : 1;  /**< ECRC Error Mask */
+	uint32_t mtlpm                        : 1;  /**< Malformed TLP Mask */
+	uint32_t rom                          : 1;  /**< Receiver Overflow Mask */
+	uint32_t ucm                          : 1;  /**< Unexpected Completion Mask */
+	uint32_t cam                          : 1;  /**< Completer Abort Mask */
+	uint32_t ctm                          : 1;  /**< Completion Timeout Mask */
+	uint32_t fcpem                        : 1;  /**< Flow Control Protocol Error Mask */
+	uint32_t ptlpm                        : 1;  /**< Poisoned TLP Mask */
+	uint32_t reserved_6_11                : 6;
+	uint32_t sdem                         : 1;  /**< Surprise Down Error Mask (not supported) */
+	uint32_t dlpem                        : 1;  /**< Data Link Protocol Error Mask */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpem                        : 1;
+	uint32_t sdem                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t ptlpm                        : 1;
+	uint32_t fcpem                        : 1;
+	uint32_t ctm                          : 1;
+	uint32_t cam                          : 1;
+	uint32_t ucm                          : 1;
+	uint32_t rom                          : 1;
+	uint32_t mtlpm                        : 1;
+	uint32_t ecrcem                       : 1;
+	uint32_t urem                         : 1;
+	uint32_t reserved_21_21               : 1;
+	uint32_t uciem                        : 1;
+	uint32_t reserved_23_23               : 1;
+	uint32_t uatombm                      : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg066_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_21_31               : 11;
 	uint32_t urem                         : 1;  /**< Unsupported Request Error Mask */
 	uint32_t ecrcem                       : 1;  /**< ECRC Error Mask */
@@ -2894,13 +3791,53 @@ union cvmx_pciercx_cfg066
 	uint32_t urem                         : 1;
 	uint32_t reserved_21_31               : 11;
 #endif
-	} s;
-	struct cvmx_pciercx_cfg066_s          cn52xx;
-	struct cvmx_pciercx_cfg066_s          cn52xxp1;
-	struct cvmx_pciercx_cfg066_s          cn56xx;
-	struct cvmx_pciercx_cfg066_s          cn56xxp1;
-	struct cvmx_pciercx_cfg066_s          cn63xx;
-	struct cvmx_pciercx_cfg066_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pciercx_cfg066_cn52xx     cn52xxp1;
+	struct cvmx_pciercx_cfg066_cn52xx     cn56xx;
+	struct cvmx_pciercx_cfg066_cn52xx     cn56xxp1;
+	struct cvmx_pciercx_cfg066_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t uatombm                      : 1;  /**< Unsupported AtomicOp Egress Blocked Mask */
+	uint32_t reserved_21_23               : 3;
+	uint32_t urem                         : 1;  /**< Unsupported Request Error Mask */
+	uint32_t ecrcem                       : 1;  /**< ECRC Error Mask */
+	uint32_t mtlpm                        : 1;  /**< Malformed TLP Mask */
+	uint32_t rom                          : 1;  /**< Receiver Overflow Mask */
+	uint32_t ucm                          : 1;  /**< Unexpected Completion Mask */
+	uint32_t cam                          : 1;  /**< Completer Abort Mask */
+	uint32_t ctm                          : 1;  /**< Completion Timeout Mask */
+	uint32_t fcpem                        : 1;  /**< Flow Control Protocol Error Mask */
+	uint32_t ptlpm                        : 1;  /**< Poisoned TLP Mask */
+	uint32_t reserved_6_11                : 6;
+	uint32_t sdem                         : 1;  /**< Surprise Down Error Mask (not supported) */
+	uint32_t dlpem                        : 1;  /**< Data Link Protocol Error Mask */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpem                        : 1;
+	uint32_t sdem                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t ptlpm                        : 1;
+	uint32_t fcpem                        : 1;
+	uint32_t ctm                          : 1;
+	uint32_t cam                          : 1;
+	uint32_t ucm                          : 1;
+	uint32_t rom                          : 1;
+	uint32_t mtlpm                        : 1;
+	uint32_t ecrcem                       : 1;
+	uint32_t urem                         : 1;
+	uint32_t reserved_21_23               : 3;
+	uint32_t uatombm                      : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} cn61xx;
+	struct cvmx_pciercx_cfg066_cn52xx     cn63xx;
+	struct cvmx_pciercx_cfg066_cn52xx     cn63xxp1;
+	struct cvmx_pciercx_cfg066_cn61xx     cn66xx;
+	struct cvmx_pciercx_cfg066_cn61xx     cn68xx;
+	struct cvmx_pciercx_cfg066_cn52xx     cn68xxp1;
+	struct cvmx_pciercx_cfg066_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg066 cvmx_pciercx_cfg066_t;
 
@@ -2910,12 +3847,51 @@ typedef union cvmx_pciercx_cfg066 cvmx_pciercx_cfg066_t;
  * PCIE_CFG067 = Sixty-eighth 32-bits of PCIE type 1 config space
  * (Uncorrectable Error Severity Register)
  */
-union cvmx_pciercx_cfg067
-{
+union cvmx_pciercx_cfg067 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg067_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg067_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t uatombs                      : 1;  /**< Unsupported AtomicOp Egress Blocked Severity */
+	uint32_t reserved_23_23               : 1;
+	uint32_t ucies                        : 1;  /**< Uncorrectable Internal Error Severity */
+	uint32_t reserved_21_21               : 1;
+	uint32_t ures                         : 1;  /**< Unsupported Request Error Severity */
+	uint32_t ecrces                       : 1;  /**< ECRC Error Severity */
+	uint32_t mtlps                        : 1;  /**< Malformed TLP Severity */
+	uint32_t ros                          : 1;  /**< Receiver Overflow Severity */
+	uint32_t ucs                          : 1;  /**< Unexpected Completion Severity */
+	uint32_t cas                          : 1;  /**< Completer Abort Severity */
+	uint32_t cts                          : 1;  /**< Completion Timeout Severity */
+	uint32_t fcpes                        : 1;  /**< Flow Control Protocol Error Severity */
+	uint32_t ptlps                        : 1;  /**< Poisoned TLP Severity */
+	uint32_t reserved_6_11                : 6;
+	uint32_t sdes                         : 1;  /**< Surprise Down Error Severity (not supported) */
+	uint32_t dlpes                        : 1;  /**< Data Link Protocol Error Severity */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpes                        : 1;
+	uint32_t sdes                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t ptlps                        : 1;
+	uint32_t fcpes                        : 1;
+	uint32_t cts                          : 1;
+	uint32_t cas                          : 1;
+	uint32_t ucs                          : 1;
+	uint32_t ros                          : 1;
+	uint32_t mtlps                        : 1;
+	uint32_t ecrces                       : 1;
+	uint32_t ures                         : 1;
+	uint32_t reserved_21_21               : 1;
+	uint32_t ucies                        : 1;
+	uint32_t reserved_23_23               : 1;
+	uint32_t uatombs                      : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg067_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_21_31               : 11;
 	uint32_t ures                         : 1;  /**< Unsupported Request Error Severity */
 	uint32_t ecrces                       : 1;  /**< ECRC Error Severity */
@@ -2946,13 +3922,53 @@ union cvmx_pciercx_cfg067
 	uint32_t ures                         : 1;
 	uint32_t reserved_21_31               : 11;
 #endif
-	} s;
-	struct cvmx_pciercx_cfg067_s          cn52xx;
-	struct cvmx_pciercx_cfg067_s          cn52xxp1;
-	struct cvmx_pciercx_cfg067_s          cn56xx;
-	struct cvmx_pciercx_cfg067_s          cn56xxp1;
-	struct cvmx_pciercx_cfg067_s          cn63xx;
-	struct cvmx_pciercx_cfg067_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pciercx_cfg067_cn52xx     cn52xxp1;
+	struct cvmx_pciercx_cfg067_cn52xx     cn56xx;
+	struct cvmx_pciercx_cfg067_cn52xx     cn56xxp1;
+	struct cvmx_pciercx_cfg067_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_25_31               : 7;
+	uint32_t uatombs                      : 1;  /**< Unsupported AtomicOp Egress Blocked Severity */
+	uint32_t reserved_21_23               : 3;
+	uint32_t ures                         : 1;  /**< Unsupported Request Error Severity */
+	uint32_t ecrces                       : 1;  /**< ECRC Error Severity */
+	uint32_t mtlps                        : 1;  /**< Malformed TLP Severity */
+	uint32_t ros                          : 1;  /**< Receiver Overflow Severity */
+	uint32_t ucs                          : 1;  /**< Unexpected Completion Severity */
+	uint32_t cas                          : 1;  /**< Completer Abort Severity */
+	uint32_t cts                          : 1;  /**< Completion Timeout Severity */
+	uint32_t fcpes                        : 1;  /**< Flow Control Protocol Error Severity */
+	uint32_t ptlps                        : 1;  /**< Poisoned TLP Severity */
+	uint32_t reserved_6_11                : 6;
+	uint32_t sdes                         : 1;  /**< Surprise Down Error Severity (not supported) */
+	uint32_t dlpes                        : 1;  /**< Data Link Protocol Error Severity */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpes                        : 1;
+	uint32_t sdes                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t ptlps                        : 1;
+	uint32_t fcpes                        : 1;
+	uint32_t cts                          : 1;
+	uint32_t cas                          : 1;
+	uint32_t ucs                          : 1;
+	uint32_t ros                          : 1;
+	uint32_t mtlps                        : 1;
+	uint32_t ecrces                       : 1;
+	uint32_t ures                         : 1;
+	uint32_t reserved_21_23               : 3;
+	uint32_t uatombs                      : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} cn61xx;
+	struct cvmx_pciercx_cfg067_cn52xx     cn63xx;
+	struct cvmx_pciercx_cfg067_cn52xx     cn63xxp1;
+	struct cvmx_pciercx_cfg067_cn61xx     cn66xx;
+	struct cvmx_pciercx_cfg067_cn61xx     cn68xx;
+	struct cvmx_pciercx_cfg067_cn52xx     cn68xxp1;
+	struct cvmx_pciercx_cfg067_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg067 cvmx_pciercx_cfg067_t;
 
@@ -2962,12 +3978,35 @@ typedef union cvmx_pciercx_cfg067 cvmx_pciercx_cfg067_t;
  * PCIE_CFG068 = Sixty-ninth 32-bits of PCIE type 1 config space
  * (Correctable Error Status Register)
  */
-union cvmx_pciercx_cfg068
-{
+union cvmx_pciercx_cfg068 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg068_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg068_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_15_31               : 17;
+	uint32_t cies                         : 1;  /**< Corrected Internal Error Status */
+	uint32_t anfes                        : 1;  /**< Advisory Non-Fatal Error Status */
+	uint32_t rtts                         : 1;  /**< Replay Timer Timeout Status */
+	uint32_t reserved_9_11                : 3;
+	uint32_t rnrs                         : 1;  /**< REPLAY_NUM Rollover Status */
+	uint32_t bdllps                       : 1;  /**< Bad DLLP Status */
+	uint32_t btlps                        : 1;  /**< Bad TLP Status */
+	uint32_t reserved_1_5                 : 5;
+	uint32_t res                          : 1;  /**< Receiver Error Status */
+#else
+	uint32_t res                          : 1;
+	uint32_t reserved_1_5                 : 5;
+	uint32_t btlps                        : 1;
+	uint32_t bdllps                       : 1;
+	uint32_t rnrs                         : 1;
+	uint32_t reserved_9_11                : 3;
+	uint32_t rtts                         : 1;
+	uint32_t anfes                        : 1;
+	uint32_t cies                         : 1;
+	uint32_t reserved_15_31               : 17;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg068_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_14_31               : 18;
 	uint32_t anfes                        : 1;  /**< Advisory Non-Fatal Error Status */
 	uint32_t rtts                         : 1;  /**< Replay Timer Timeout Status */
@@ -2988,13 +4027,17 @@ union cvmx_pciercx_cfg068
 	uint32_t anfes                        : 1;
 	uint32_t reserved_14_31               : 18;
 #endif
-	} s;
-	struct cvmx_pciercx_cfg068_s          cn52xx;
-	struct cvmx_pciercx_cfg068_s          cn52xxp1;
-	struct cvmx_pciercx_cfg068_s          cn56xx;
-	struct cvmx_pciercx_cfg068_s          cn56xxp1;
-	struct cvmx_pciercx_cfg068_s          cn63xx;
-	struct cvmx_pciercx_cfg068_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pciercx_cfg068_cn52xx     cn52xxp1;
+	struct cvmx_pciercx_cfg068_cn52xx     cn56xx;
+	struct cvmx_pciercx_cfg068_cn52xx     cn56xxp1;
+	struct cvmx_pciercx_cfg068_cn52xx     cn61xx;
+	struct cvmx_pciercx_cfg068_cn52xx     cn63xx;
+	struct cvmx_pciercx_cfg068_cn52xx     cn63xxp1;
+	struct cvmx_pciercx_cfg068_cn52xx     cn66xx;
+	struct cvmx_pciercx_cfg068_cn52xx     cn68xx;
+	struct cvmx_pciercx_cfg068_cn52xx     cn68xxp1;
+	struct cvmx_pciercx_cfg068_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg068 cvmx_pciercx_cfg068_t;
 
@@ -3004,12 +4047,35 @@ typedef union cvmx_pciercx_cfg068 cvmx_pciercx_cfg068_t;
  * PCIE_CFG069 = Seventieth 32-bits of PCIE type 1 config space
  * (Correctable Error Mask Register)
  */
-union cvmx_pciercx_cfg069
-{
+union cvmx_pciercx_cfg069 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg069_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg069_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_15_31               : 17;
+	uint32_t ciem                         : 1;  /**< Corrected Internal Error Mask */
+	uint32_t anfem                        : 1;  /**< Advisory Non-Fatal Error Mask */
+	uint32_t rttm                         : 1;  /**< Replay Timer Timeout Mask */
+	uint32_t reserved_9_11                : 3;
+	uint32_t rnrm                         : 1;  /**< REPLAY_NUM Rollover Mask */
+	uint32_t bdllpm                       : 1;  /**< Bad DLLP Mask */
+	uint32_t btlpm                        : 1;  /**< Bad TLP Mask */
+	uint32_t reserved_1_5                 : 5;
+	uint32_t rem                          : 1;  /**< Receiver Error Mask */
+#else
+	uint32_t rem                          : 1;
+	uint32_t reserved_1_5                 : 5;
+	uint32_t btlpm                        : 1;
+	uint32_t bdllpm                       : 1;
+	uint32_t rnrm                         : 1;
+	uint32_t reserved_9_11                : 3;
+	uint32_t rttm                         : 1;
+	uint32_t anfem                        : 1;
+	uint32_t ciem                         : 1;
+	uint32_t reserved_15_31               : 17;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg069_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_14_31               : 18;
 	uint32_t anfem                        : 1;  /**< Advisory Non-Fatal Error Mask */
 	uint32_t rttm                         : 1;  /**< Replay Timer Timeout Mask */
@@ -3030,13 +4096,17 @@ union cvmx_pciercx_cfg069
 	uint32_t anfem                        : 1;
 	uint32_t reserved_14_31               : 18;
 #endif
-	} s;
-	struct cvmx_pciercx_cfg069_s          cn52xx;
-	struct cvmx_pciercx_cfg069_s          cn52xxp1;
-	struct cvmx_pciercx_cfg069_s          cn56xx;
-	struct cvmx_pciercx_cfg069_s          cn56xxp1;
-	struct cvmx_pciercx_cfg069_s          cn63xx;
-	struct cvmx_pciercx_cfg069_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pciercx_cfg069_cn52xx     cn52xxp1;
+	struct cvmx_pciercx_cfg069_cn52xx     cn56xx;
+	struct cvmx_pciercx_cfg069_cn52xx     cn56xxp1;
+	struct cvmx_pciercx_cfg069_cn52xx     cn61xx;
+	struct cvmx_pciercx_cfg069_cn52xx     cn63xx;
+	struct cvmx_pciercx_cfg069_cn52xx     cn63xxp1;
+	struct cvmx_pciercx_cfg069_cn52xx     cn66xx;
+	struct cvmx_pciercx_cfg069_cn52xx     cn68xx;
+	struct cvmx_pciercx_cfg069_cn52xx     cn68xxp1;
+	struct cvmx_pciercx_cfg069_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg069 cvmx_pciercx_cfg069_t;
 
@@ -3046,12 +4116,10 @@ typedef union cvmx_pciercx_cfg069 cvmx_pciercx_cfg069_t;
  * PCIE_CFG070 = Seventy-first 32-bits of PCIE type 1 config space
  * (Advanced Capabilities and Control Register)
  */
-union cvmx_pciercx_cfg070
-{
+union cvmx_pciercx_cfg070 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg070_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg070_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_9_31                : 23;
 	uint32_t ce                           : 1;  /**< ECRC Check Enable */
 	uint32_t cc                           : 1;  /**< ECRC Check Capable */
@@ -3071,8 +4139,13 @@ union cvmx_pciercx_cfg070
 	struct cvmx_pciercx_cfg070_s          cn52xxp1;
 	struct cvmx_pciercx_cfg070_s          cn56xx;
 	struct cvmx_pciercx_cfg070_s          cn56xxp1;
+	struct cvmx_pciercx_cfg070_s          cn61xx;
 	struct cvmx_pciercx_cfg070_s          cn63xx;
 	struct cvmx_pciercx_cfg070_s          cn63xxp1;
+	struct cvmx_pciercx_cfg070_s          cn66xx;
+	struct cvmx_pciercx_cfg070_s          cn68xx;
+	struct cvmx_pciercx_cfg070_s          cn68xxp1;
+	struct cvmx_pciercx_cfg070_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg070 cvmx_pciercx_cfg070_t;
 
@@ -3084,12 +4157,10 @@ typedef union cvmx_pciercx_cfg070 cvmx_pciercx_cfg070_t;
  *
  * The Header Log registers collect the header for the TLP corresponding to a detected error.
  */
-union cvmx_pciercx_cfg071
-{
+union cvmx_pciercx_cfg071 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg071_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg071_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dword1                       : 32; /**< Header Log Register (first DWORD) */
 #else
 	uint32_t dword1                       : 32;
@@ -3099,8 +4170,13 @@ union cvmx_pciercx_cfg071
 	struct cvmx_pciercx_cfg071_s          cn52xxp1;
 	struct cvmx_pciercx_cfg071_s          cn56xx;
 	struct cvmx_pciercx_cfg071_s          cn56xxp1;
+	struct cvmx_pciercx_cfg071_s          cn61xx;
 	struct cvmx_pciercx_cfg071_s          cn63xx;
 	struct cvmx_pciercx_cfg071_s          cn63xxp1;
+	struct cvmx_pciercx_cfg071_s          cn66xx;
+	struct cvmx_pciercx_cfg071_s          cn68xx;
+	struct cvmx_pciercx_cfg071_s          cn68xxp1;
+	struct cvmx_pciercx_cfg071_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg071 cvmx_pciercx_cfg071_t;
 
@@ -3112,12 +4188,10 @@ typedef union cvmx_pciercx_cfg071 cvmx_pciercx_cfg071_t;
  *
  * The Header Log registers collect the header for the TLP corresponding to a detected error.
  */
-union cvmx_pciercx_cfg072
-{
+union cvmx_pciercx_cfg072 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg072_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg072_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dword2                       : 32; /**< Header Log Register (second DWORD) */
 #else
 	uint32_t dword2                       : 32;
@@ -3127,8 +4201,13 @@ union cvmx_pciercx_cfg072
 	struct cvmx_pciercx_cfg072_s          cn52xxp1;
 	struct cvmx_pciercx_cfg072_s          cn56xx;
 	struct cvmx_pciercx_cfg072_s          cn56xxp1;
+	struct cvmx_pciercx_cfg072_s          cn61xx;
 	struct cvmx_pciercx_cfg072_s          cn63xx;
 	struct cvmx_pciercx_cfg072_s          cn63xxp1;
+	struct cvmx_pciercx_cfg072_s          cn66xx;
+	struct cvmx_pciercx_cfg072_s          cn68xx;
+	struct cvmx_pciercx_cfg072_s          cn68xxp1;
+	struct cvmx_pciercx_cfg072_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg072 cvmx_pciercx_cfg072_t;
 
@@ -3140,12 +4219,10 @@ typedef union cvmx_pciercx_cfg072 cvmx_pciercx_cfg072_t;
  *
  * The Header Log registers collect the header for the TLP corresponding to a detected error.
  */
-union cvmx_pciercx_cfg073
-{
+union cvmx_pciercx_cfg073 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg073_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg073_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dword3                       : 32; /**< Header Log Register (third DWORD) */
 #else
 	uint32_t dword3                       : 32;
@@ -3155,8 +4232,13 @@ union cvmx_pciercx_cfg073
 	struct cvmx_pciercx_cfg073_s          cn52xxp1;
 	struct cvmx_pciercx_cfg073_s          cn56xx;
 	struct cvmx_pciercx_cfg073_s          cn56xxp1;
+	struct cvmx_pciercx_cfg073_s          cn61xx;
 	struct cvmx_pciercx_cfg073_s          cn63xx;
 	struct cvmx_pciercx_cfg073_s          cn63xxp1;
+	struct cvmx_pciercx_cfg073_s          cn66xx;
+	struct cvmx_pciercx_cfg073_s          cn68xx;
+	struct cvmx_pciercx_cfg073_s          cn68xxp1;
+	struct cvmx_pciercx_cfg073_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg073 cvmx_pciercx_cfg073_t;
 
@@ -3168,12 +4250,10 @@ typedef union cvmx_pciercx_cfg073 cvmx_pciercx_cfg073_t;
  *
  * The Header Log registers collect the header for the TLP corresponding to a detected error.
  */
-union cvmx_pciercx_cfg074
-{
+union cvmx_pciercx_cfg074 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg074_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg074_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dword4                       : 32; /**< Header Log Register (fourth DWORD) */
 #else
 	uint32_t dword4                       : 32;
@@ -3183,8 +4263,13 @@ union cvmx_pciercx_cfg074
 	struct cvmx_pciercx_cfg074_s          cn52xxp1;
 	struct cvmx_pciercx_cfg074_s          cn56xx;
 	struct cvmx_pciercx_cfg074_s          cn56xxp1;
+	struct cvmx_pciercx_cfg074_s          cn61xx;
 	struct cvmx_pciercx_cfg074_s          cn63xx;
 	struct cvmx_pciercx_cfg074_s          cn63xxp1;
+	struct cvmx_pciercx_cfg074_s          cn66xx;
+	struct cvmx_pciercx_cfg074_s          cn68xx;
+	struct cvmx_pciercx_cfg074_s          cn68xxp1;
+	struct cvmx_pciercx_cfg074_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg074 cvmx_pciercx_cfg074_t;
 
@@ -3194,12 +4279,10 @@ typedef union cvmx_pciercx_cfg074 cvmx_pciercx_cfg074_t;
  * PCIE_CFG075 = Seventy-sixth 32-bits of PCIE type 1 config space
  * (Root Error Command Register)
  */
-union cvmx_pciercx_cfg075
-{
+union cvmx_pciercx_cfg075 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg075_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg075_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_3_31                : 29;
 	uint32_t fere                         : 1;  /**< Fatal Error Reporting Enable */
 	uint32_t nfere                        : 1;  /**< Non-Fatal Error Reporting Enable */
@@ -3215,8 +4298,13 @@ union cvmx_pciercx_cfg075
 	struct cvmx_pciercx_cfg075_s          cn52xxp1;
 	struct cvmx_pciercx_cfg075_s          cn56xx;
 	struct cvmx_pciercx_cfg075_s          cn56xxp1;
+	struct cvmx_pciercx_cfg075_s          cn61xx;
 	struct cvmx_pciercx_cfg075_s          cn63xx;
 	struct cvmx_pciercx_cfg075_s          cn63xxp1;
+	struct cvmx_pciercx_cfg075_s          cn66xx;
+	struct cvmx_pciercx_cfg075_s          cn68xx;
+	struct cvmx_pciercx_cfg075_s          cn68xxp1;
+	struct cvmx_pciercx_cfg075_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg075 cvmx_pciercx_cfg075_t;
 
@@ -3226,12 +4314,10 @@ typedef union cvmx_pciercx_cfg075 cvmx_pciercx_cfg075_t;
  * PCIE_CFG076 = Seventy-seventh 32-bits of PCIE type 1 config space
  * (Root Error Status Register)
  */
-union cvmx_pciercx_cfg076
-{
+union cvmx_pciercx_cfg076 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg076_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg076_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t aeimn                        : 5;  /**< Advanced Error Interrupt Message Number,
                                                          writable through PEM(0..1)_CFG_WR */
 	uint32_t reserved_7_26                : 20;
@@ -3258,8 +4344,13 @@ union cvmx_pciercx_cfg076
 	struct cvmx_pciercx_cfg076_s          cn52xxp1;
 	struct cvmx_pciercx_cfg076_s          cn56xx;
 	struct cvmx_pciercx_cfg076_s          cn56xxp1;
+	struct cvmx_pciercx_cfg076_s          cn61xx;
 	struct cvmx_pciercx_cfg076_s          cn63xx;
 	struct cvmx_pciercx_cfg076_s          cn63xxp1;
+	struct cvmx_pciercx_cfg076_s          cn66xx;
+	struct cvmx_pciercx_cfg076_s          cn68xx;
+	struct cvmx_pciercx_cfg076_s          cn68xxp1;
+	struct cvmx_pciercx_cfg076_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg076 cvmx_pciercx_cfg076_t;
 
@@ -3269,12 +4360,10 @@ typedef union cvmx_pciercx_cfg076 cvmx_pciercx_cfg076_t;
  * PCIE_CFG077 = Seventy-eighth 32-bits of PCIE type 1 config space
  * (Error Source Identification Register)
  */
-union cvmx_pciercx_cfg077
-{
+union cvmx_pciercx_cfg077 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg077_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg077_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t efnfsi                       : 16; /**< ERR_FATAL/NONFATAL Source Identification */
 	uint32_t ecsi                         : 16; /**< ERR_COR Source Identification */
 #else
@@ -3286,8 +4375,13 @@ union cvmx_pciercx_cfg077
 	struct cvmx_pciercx_cfg077_s          cn52xxp1;
 	struct cvmx_pciercx_cfg077_s          cn56xx;
 	struct cvmx_pciercx_cfg077_s          cn56xxp1;
+	struct cvmx_pciercx_cfg077_s          cn61xx;
 	struct cvmx_pciercx_cfg077_s          cn63xx;
 	struct cvmx_pciercx_cfg077_s          cn63xxp1;
+	struct cvmx_pciercx_cfg077_s          cn66xx;
+	struct cvmx_pciercx_cfg077_s          cn68xx;
+	struct cvmx_pciercx_cfg077_s          cn68xxp1;
+	struct cvmx_pciercx_cfg077_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg077 cvmx_pciercx_cfg077_t;
 
@@ -3297,22 +4391,26 @@ typedef union cvmx_pciercx_cfg077 cvmx_pciercx_cfg077_t;
  * PCIE_CFG448 = Four hundred forty-ninth 32-bits of PCIE type 1 config space
  * (Ack Latency Timer and Replay Timer Register)
  */
-union cvmx_pciercx_cfg448
-{
+union cvmx_pciercx_cfg448 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg448_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg448_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t rtl                          : 16; /**< Replay Time Limit
                                                          The replay timer expires when it reaches this limit. The PCI
                                                          Express bus initiates a replay upon reception of a Nak or when
                                                          the replay timer expires.
-                                                         The default is then updated based on the Negotiated Link Width
-                                                         and Max_Payload_Size. */
+                                                         This value will be set correctly by the hardware out of reset
+                                                         or when the negotiated Link-Width or Payload-Size changes. If
+                                                         the user changes this value through a CSR write or by an
+                                                         EEPROM load then they should refer to the PCIe Specification
+                                                         for the correct value. */
 	uint32_t rtltl                        : 16; /**< Round Trip Latency Time Limit
                                                          The Ack/Nak latency timer expires when it reaches this limit.
-                                                         The default is then updated based on the Negotiated Link Width
-                                                         and Max_Payload_Size. */
+                                                         This value will be set correctly by the hardware out of reset
+                                                         or when the negotiated Link-Width or Payload-Size changes. If
+                                                         the user changes this value through a CSR write or by an
+                                                         EEPROM load then they should refer to the PCIe Specification
+                                                         for the correct value. */
 #else
 	uint32_t rtltl                        : 16;
 	uint32_t rtl                          : 16;
@@ -3322,8 +4420,13 @@ union cvmx_pciercx_cfg448
 	struct cvmx_pciercx_cfg448_s          cn52xxp1;
 	struct cvmx_pciercx_cfg448_s          cn56xx;
 	struct cvmx_pciercx_cfg448_s          cn56xxp1;
+	struct cvmx_pciercx_cfg448_s          cn61xx;
 	struct cvmx_pciercx_cfg448_s          cn63xx;
 	struct cvmx_pciercx_cfg448_s          cn63xxp1;
+	struct cvmx_pciercx_cfg448_s          cn66xx;
+	struct cvmx_pciercx_cfg448_s          cn68xx;
+	struct cvmx_pciercx_cfg448_s          cn68xxp1;
+	struct cvmx_pciercx_cfg448_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg448 cvmx_pciercx_cfg448_t;
 
@@ -3333,12 +4436,10 @@ typedef union cvmx_pciercx_cfg448 cvmx_pciercx_cfg448_t;
  * PCIE_CFG449 = Four hundred fiftieth 32-bits of PCIE type 1 config space
  * (Other Message Register)
  */
-union cvmx_pciercx_cfg449
-{
+union cvmx_pciercx_cfg449 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg449_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg449_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t omr                          : 32; /**< Other Message Register
                                                          This register can be used for either of the following purposes:
                                                          o To send a specific PCI Express Message, the application
@@ -3359,8 +4460,13 @@ union cvmx_pciercx_cfg449
 	struct cvmx_pciercx_cfg449_s          cn52xxp1;
 	struct cvmx_pciercx_cfg449_s          cn56xx;
 	struct cvmx_pciercx_cfg449_s          cn56xxp1;
+	struct cvmx_pciercx_cfg449_s          cn61xx;
 	struct cvmx_pciercx_cfg449_s          cn63xx;
 	struct cvmx_pciercx_cfg449_s          cn63xxp1;
+	struct cvmx_pciercx_cfg449_s          cn66xx;
+	struct cvmx_pciercx_cfg449_s          cn68xx;
+	struct cvmx_pciercx_cfg449_s          cn68xxp1;
+	struct cvmx_pciercx_cfg449_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg449 cvmx_pciercx_cfg449_t;
 
@@ -3370,12 +4476,10 @@ typedef union cvmx_pciercx_cfg449 cvmx_pciercx_cfg449_t;
  * PCIE_CFG450 = Four hundred fifty-first 32-bits of PCIE type 1 config space
  * (Port Force Link Register)
  */
-union cvmx_pciercx_cfg450
-{
+union cvmx_pciercx_cfg450 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg450_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg450_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t lpec                         : 8;  /**< Low Power Entrance Count
                                                          The Power Management state will wait for this many clock cycles
                                                          for the associated completion of a CfgWr to PCIE_CFG017 register
@@ -3441,8 +4545,13 @@ union cvmx_pciercx_cfg450
 	struct cvmx_pciercx_cfg450_s          cn52xxp1;
 	struct cvmx_pciercx_cfg450_s          cn56xx;
 	struct cvmx_pciercx_cfg450_s          cn56xxp1;
+	struct cvmx_pciercx_cfg450_s          cn61xx;
 	struct cvmx_pciercx_cfg450_s          cn63xx;
 	struct cvmx_pciercx_cfg450_s          cn63xxp1;
+	struct cvmx_pciercx_cfg450_s          cn66xx;
+	struct cvmx_pciercx_cfg450_s          cn68xx;
+	struct cvmx_pciercx_cfg450_s          cn68xxp1;
+	struct cvmx_pciercx_cfg450_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg450 cvmx_pciercx_cfg450_t;
 
@@ -3452,12 +4561,63 @@ typedef union cvmx_pciercx_cfg450 cvmx_pciercx_cfg450_t;
  * PCIE_CFG451 = Four hundred fifty-second 32-bits of PCIE type 1 config space
  * (Ack Frequency Register)
  */
-union cvmx_pciercx_cfg451
-{
+union cvmx_pciercx_cfg451 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg451_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg451_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_31_31               : 1;
+	uint32_t easpml1                      : 1;  /**< Enter ASPM L1 without receive in L0s
+                                                         Allow core to enter ASPM L1 even when link partner did
+                                                         not go to L0s (receive is not in L0s).
+                                                         When not set, core goes to ASPM L1 only after idle period
+                                                         during which both receive and transmit are in L0s. */
+	uint32_t l1el                         : 3;  /**< L1 Entrance Latency
+                                                         Values correspond to:
+                                                         o 000: 1 ms
+                                                         o 001: 2 ms
+                                                         o 010: 4 ms
+                                                         o 011: 8 ms
+                                                         o 100: 16 ms
+                                                         o 101: 32 ms
+                                                         o 110 or 111: 64 ms */
+	uint32_t l0el                         : 3;  /**< L0s Entrance Latency
+                                                         Values correspond to:
+                                                         o 000: 1 ms
+                                                         o 001: 2 ms
+                                                         o 010: 3 ms
+                                                         o 011: 4 ms
+                                                         o 100: 5 ms
+                                                         o 101: 6 ms
+                                                         o 110 or 111: 7 ms */
+	uint32_t n_fts_cc                     : 8;  /**< N_FTS when common clock is used.
+                                                         The number of Fast Training Sequence ordered sets to be
+                                                         transmitted when transitioning from L0s to L0. The maximum
+                                                         number of FTS ordered-sets that a component can request is 255.
+                                                          Note: The core does not support a value of zero; a value of
+                                                                zero can cause the LTSSM to go into the recovery state
+                                                                when exiting from L0s. */
+	uint32_t n_fts                        : 8;  /**< N_FTS
+                                                         The number of Fast Training Sequence ordered sets to be
+                                                         transmitted when transitioning from L0s to L0. The maximum
+                                                         number of FTS ordered-sets that a component can request is 255.
+                                                         Note: The core does not support a value of zero; a value of
+                                                               zero can cause the LTSSM to go into the recovery state
+                                                               when exiting from L0s. */
+	uint32_t ack_freq                     : 8;  /**< Ack Frequency
+                                                         The number of pending Ack's specified here (up to 255) before
+                                                         sending an Ack. */
+#else
+	uint32_t ack_freq                     : 8;
+	uint32_t n_fts                        : 8;
+	uint32_t n_fts_cc                     : 8;
+	uint32_t l0el                         : 3;
+	uint32_t l1el                         : 3;
+	uint32_t easpml1                      : 1;
+	uint32_t reserved_31_31               : 1;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg451_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_30_31               : 2;
 	uint32_t l1el                         : 3;  /**< L1 Entrance Latency
                                                          Values correspond to:
@@ -3502,13 +4662,17 @@ union cvmx_pciercx_cfg451
 	uint32_t l1el                         : 3;
 	uint32_t reserved_30_31               : 2;
 #endif
-	} s;
-	struct cvmx_pciercx_cfg451_s          cn52xx;
-	struct cvmx_pciercx_cfg451_s          cn52xxp1;
-	struct cvmx_pciercx_cfg451_s          cn56xx;
-	struct cvmx_pciercx_cfg451_s          cn56xxp1;
-	struct cvmx_pciercx_cfg451_s          cn63xx;
-	struct cvmx_pciercx_cfg451_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pciercx_cfg451_cn52xx     cn52xxp1;
+	struct cvmx_pciercx_cfg451_cn52xx     cn56xx;
+	struct cvmx_pciercx_cfg451_cn52xx     cn56xxp1;
+	struct cvmx_pciercx_cfg451_s          cn61xx;
+	struct cvmx_pciercx_cfg451_cn52xx     cn63xx;
+	struct cvmx_pciercx_cfg451_cn52xx     cn63xxp1;
+	struct cvmx_pciercx_cfg451_s          cn66xx;
+	struct cvmx_pciercx_cfg451_s          cn68xx;
+	struct cvmx_pciercx_cfg451_s          cn68xxp1;
+	struct cvmx_pciercx_cfg451_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg451 cvmx_pciercx_cfg451_t;
 
@@ -3518,12 +4682,10 @@ typedef union cvmx_pciercx_cfg451 cvmx_pciercx_cfg451_t;
  * PCIE_CFG452 = Four hundred fifty-third 32-bits of PCIE type 1 config space
  * (Port Link Control Register)
  */
-union cvmx_pciercx_cfg452
-{
+union cvmx_pciercx_cfg452 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg452_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg452_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_26_31               : 6;
 	uint32_t eccrc                        : 1;  /**< Enable Corrupted CRC
                                                          Causes corrupt LCRC for TLPs when set,
@@ -3533,21 +4695,20 @@ union cvmx_pciercx_cfg452
 	uint32_t lme                          : 6;  /**< Link Mode Enable
                                                          o 000001: x1
                                                          o 000011: x2
-                                                         o 000111: x4
+                                                         o 000111: x4  (not supported)
                                                          o 001111: x8  (not supported)
                                                          o 011111: x16 (not supported)
                                                          o 111111: x32 (not supported)
                                                          This field indicates the MAXIMUM number of lanes supported
-                                                         by the PCIe port. The value can be set less than 0x7
+                                                         by the PCIe port. The value can be set less than 0x3
                                                          to limit the number of lanes the PCIe will attempt to use.
                                                          The programming of this field needs to be done by SW BEFORE
                                                          enabling the link. See also MLW.
                                                          (Note: The value of this field does NOT indicate the number
                                                           of lanes in use by the PCIe. LME sets the max number of lanes
                                                           in the PCIe core that COULD be used. As per the PCIe specs,
-                                                          the PCIe core can negotiate a smaller link width, so all
-                                                          of x4, x2, and x1 are supported when LME=0x7,
-                                                          for example.) */
+                                                          the PCIe core can negotiate a smaller link width, so
+                                                          x1 is also supported when LME=0x3, for example.) */
 	uint32_t reserved_8_15                : 8;
 	uint32_t flm                          : 1;  /**< Fast Link Mode
                                                          Sets all internal timers to fast mode for simulation purposes. */
@@ -3591,8 +4752,70 @@ union cvmx_pciercx_cfg452
 	struct cvmx_pciercx_cfg452_s          cn52xxp1;
 	struct cvmx_pciercx_cfg452_s          cn56xx;
 	struct cvmx_pciercx_cfg452_s          cn56xxp1;
+	struct cvmx_pciercx_cfg452_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_22_31               : 10;
+	uint32_t lme                          : 6;  /**< Link Mode Enable
+                                                         o 000001: x1
+                                                         o 000011: x2
+                                                         o 000111: x4
+                                                         o 001111: x8  (not supported)
+                                                         o 011111: x16 (not supported)
+                                                         o 111111: x32 (not supported)
+                                                         This field indicates the MAXIMUM number of lanes supported
+                                                         by the PCIe port. The value can be set less than 0x7
+                                                         to limit the number of lanes the PCIe will attempt to use.
+                                                         The programming of this field needs to be done by SW BEFORE
+                                                         enabling the link. See also MLW.
+                                                         (Note: The value of this field does NOT indicate the number
+                                                          of lanes in use by the PCIe. LME sets the max number of lanes
+                                                          in the PCIe core that COULD be used. As per the PCIe specs,
+                                                          the PCIe core can negotiate a smaller link width, so all
+                                                          of x4, x2, and x1 are supported when LME=0x7,
+                                                          for example.) */
+	uint32_t reserved_8_15                : 8;
+	uint32_t flm                          : 1;  /**< Fast Link Mode
+                                                         Sets all internal timers to fast mode for simulation purposes. */
+	uint32_t reserved_6_6                 : 1;
+	uint32_t dllle                        : 1;  /**< DLL Link Enable
+                                                         Enables Link initialization. If DLL Link Enable = 0, the PCI
+                                                         Express bus does not transmit InitFC DLLPs and does not
+                                                         establish a Link. */
+	uint32_t reserved_4_4                 : 1;
+	uint32_t ra                           : 1;  /**< Reset Assert
+                                                         Triggers a recovery and forces the LTSSM to the Hot Reset
+                                                         state (downstream port only). */
+	uint32_t le                           : 1;  /**< Loopback Enable
+                                                         Initiate loopback mode as a master. On a 0->1 transition,
+                                                         the PCIe core sends TS ordered sets with the loopback bit set
+                                                         to cause the link partner to enter into loopback mode as a
+                                                         slave. Normal transmission is not possible when LE=1. To exit
+                                                         loopback mode, take the link through a reset sequence. */
+	uint32_t sd                           : 1;  /**< Scramble Disable
+                                                         Turns off data scrambling. */
+	uint32_t omr                          : 1;  /**< Other Message Request
+                                                         When software writes a `1' to this bit, the PCI Express bus
+                                                         transmits the Message contained in the Other Message register. */
+#else
+	uint32_t omr                          : 1;
+	uint32_t sd                           : 1;
+	uint32_t le                           : 1;
+	uint32_t ra                           : 1;
+	uint32_t reserved_4_4                 : 1;
+	uint32_t dllle                        : 1;
+	uint32_t reserved_6_6                 : 1;
+	uint32_t flm                          : 1;
+	uint32_t reserved_8_15                : 8;
+	uint32_t lme                          : 6;
+	uint32_t reserved_22_31               : 10;
+#endif
+	} cn61xx;
 	struct cvmx_pciercx_cfg452_s          cn63xx;
 	struct cvmx_pciercx_cfg452_s          cn63xxp1;
+	struct cvmx_pciercx_cfg452_cn61xx     cn66xx;
+	struct cvmx_pciercx_cfg452_cn61xx     cn68xx;
+	struct cvmx_pciercx_cfg452_cn61xx     cn68xxp1;
+	struct cvmx_pciercx_cfg452_cn61xx     cnf71xx;
 };
 typedef union cvmx_pciercx_cfg452 cvmx_pciercx_cfg452_t;
 
@@ -3602,12 +4825,10 @@ typedef union cvmx_pciercx_cfg452 cvmx_pciercx_cfg452_t;
  * PCIE_CFG453 = Four hundred fifty-fourth 32-bits of PCIE type 1 config space
  * (Lane Skew Register)
  */
-union cvmx_pciercx_cfg453
-{
+union cvmx_pciercx_cfg453 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg453_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg453_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dlld                         : 1;  /**< Disable Lane-to-Lane Deskew
                                                          Disables the internal Lane-to-Lane deskew logic. */
 	uint32_t reserved_26_30               : 5;
@@ -3633,8 +4854,13 @@ union cvmx_pciercx_cfg453
 	struct cvmx_pciercx_cfg453_s          cn52xxp1;
 	struct cvmx_pciercx_cfg453_s          cn56xx;
 	struct cvmx_pciercx_cfg453_s          cn56xxp1;
+	struct cvmx_pciercx_cfg453_s          cn61xx;
 	struct cvmx_pciercx_cfg453_s          cn63xx;
 	struct cvmx_pciercx_cfg453_s          cn63xxp1;
+	struct cvmx_pciercx_cfg453_s          cn66xx;
+	struct cvmx_pciercx_cfg453_s          cn68xx;
+	struct cvmx_pciercx_cfg453_s          cn68xxp1;
+	struct cvmx_pciercx_cfg453_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg453 cvmx_pciercx_cfg453_t;
 
@@ -3644,12 +4870,37 @@ typedef union cvmx_pciercx_cfg453 cvmx_pciercx_cfg453_t;
  * PCIE_CFG454 = Four hundred fifty-fifth 32-bits of PCIE type 1 config space
  * (Symbol Number Register)
  */
-union cvmx_pciercx_cfg454
-{
+union cvmx_pciercx_cfg454 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg454_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg454_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t cx_nfunc                     : 3;  /**< Number of Functions (minus 1)
+                                                         Configuration Requests targeted at function numbers above this
+                                                         value will be returned with unsupported request */
+	uint32_t tmfcwt                       : 5;  /**< Timer Modifier for Flow Control Watchdog Timer
+                                                         Increases the timer value for the Flow Control watchdog timer,
+                                                         in increments of 16 clock cycles. */
+	uint32_t tmanlt                       : 5;  /**< Timer Modifier for Ack/Nak Latency Timer
+                                                         Increases the timer value for the Ack/Nak latency timer, in
+                                                         increments of 64 clock cycles. */
+	uint32_t tmrt                         : 5;  /**< Timer Modifier for Replay Timer
+                                                         Increases the timer value for the replay timer, in increments
+                                                         of 64 clock cycles. */
+	uint32_t reserved_11_13               : 3;
+	uint32_t nskps                        : 3;  /**< Number of SKP Symbols */
+	uint32_t reserved_0_7                 : 8;
+#else
+	uint32_t reserved_0_7                 : 8;
+	uint32_t nskps                        : 3;
+	uint32_t reserved_11_13               : 3;
+	uint32_t tmrt                         : 5;
+	uint32_t tmanlt                       : 5;
+	uint32_t tmfcwt                       : 5;
+	uint32_t cx_nfunc                     : 3;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg454_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_29_31               : 3;
 	uint32_t tmfcwt                       : 5;  /**< Timer Modifier for Flow Control Watchdog Timer
                                                          Increases the timer value for the Flow Control watchdog timer,
@@ -3676,13 +4927,41 @@ union cvmx_pciercx_cfg454
 	uint32_t tmfcwt                       : 5;
 	uint32_t reserved_29_31               : 3;
 #endif
-	} s;
-	struct cvmx_pciercx_cfg454_s          cn52xx;
-	struct cvmx_pciercx_cfg454_s          cn52xxp1;
-	struct cvmx_pciercx_cfg454_s          cn56xx;
-	struct cvmx_pciercx_cfg454_s          cn56xxp1;
-	struct cvmx_pciercx_cfg454_s          cn63xx;
-	struct cvmx_pciercx_cfg454_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pciercx_cfg454_cn52xx     cn52xxp1;
+	struct cvmx_pciercx_cfg454_cn52xx     cn56xx;
+	struct cvmx_pciercx_cfg454_cn52xx     cn56xxp1;
+	struct cvmx_pciercx_cfg454_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t cx_nfunc                     : 3;  /**< Number of Functions (minus 1)
+                                                         Configuration Requests targeted at function numbers above this
+                                                         value will be returned with unsupported request */
+	uint32_t tmfcwt                       : 5;  /**< Timer Modifier for Flow Control Watchdog Timer
+                                                         Increases the timer value for the Flow Control watchdog timer,
+                                                         in increments of 16 clock cycles. */
+	uint32_t tmanlt                       : 5;  /**< Timer Modifier for Ack/Nak Latency Timer
+                                                         Increases the timer value for the Ack/Nak latency timer, in
+                                                         increments of 64 clock cycles. */
+	uint32_t tmrt                         : 5;  /**< Timer Modifier for Replay Timer
+                                                         Increases the timer value for the replay timer, in increments
+                                                         of 64 clock cycles. */
+	uint32_t reserved_8_13                : 6;
+	uint32_t mfuncn                       : 8;  /**< Max Number of Functions Supported */
+#else
+	uint32_t mfuncn                       : 8;
+	uint32_t reserved_8_13                : 6;
+	uint32_t tmrt                         : 5;
+	uint32_t tmanlt                       : 5;
+	uint32_t tmfcwt                       : 5;
+	uint32_t cx_nfunc                     : 3;
+#endif
+	} cn61xx;
+	struct cvmx_pciercx_cfg454_cn52xx     cn63xx;
+	struct cvmx_pciercx_cfg454_cn52xx     cn63xxp1;
+	struct cvmx_pciercx_cfg454_cn61xx     cn66xx;
+	struct cvmx_pciercx_cfg454_cn61xx     cn68xx;
+	struct cvmx_pciercx_cfg454_cn52xx     cn68xxp1;
+	struct cvmx_pciercx_cfg454_cn61xx     cnf71xx;
 };
 typedef union cvmx_pciercx_cfg454 cvmx_pciercx_cfg454_t;
 
@@ -3692,12 +4971,10 @@ typedef union cvmx_pciercx_cfg454 cvmx_pciercx_cfg454_t;
  * PCIE_CFG455 = Four hundred fifty-sixth 32-bits of PCIE type 1 config space
  * (Symbol Timer Register/Filter Mask Register 1)
  */
-union cvmx_pciercx_cfg455
-{
+union cvmx_pciercx_cfg455 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg455_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg455_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t m_cfg0_filt                  : 1;  /**< Mask filtering of received Configuration Requests (RC mode only) */
 	uint32_t m_io_filt                    : 1;  /**< Mask filtering of received I/O Requests (RC mode only) */
 	uint32_t msg_ctrl                     : 1;  /**< Message Control
@@ -3744,8 +5021,13 @@ union cvmx_pciercx_cfg455
 	struct cvmx_pciercx_cfg455_s          cn52xxp1;
 	struct cvmx_pciercx_cfg455_s          cn56xx;
 	struct cvmx_pciercx_cfg455_s          cn56xxp1;
+	struct cvmx_pciercx_cfg455_s          cn61xx;
 	struct cvmx_pciercx_cfg455_s          cn63xx;
 	struct cvmx_pciercx_cfg455_s          cn63xxp1;
+	struct cvmx_pciercx_cfg455_s          cn66xx;
+	struct cvmx_pciercx_cfg455_s          cn68xx;
+	struct cvmx_pciercx_cfg455_s          cn68xxp1;
+	struct cvmx_pciercx_cfg455_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg455 cvmx_pciercx_cfg455_t;
 
@@ -3755,12 +5037,25 @@ typedef union cvmx_pciercx_cfg455 cvmx_pciercx_cfg455_t;
  * PCIE_CFG456 = Four hundred fifty-seventh 32-bits of PCIE type 1 config space
  * (Filter Mask Register 2)
  */
-union cvmx_pciercx_cfg456
-{
+union cvmx_pciercx_cfg456 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg456_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg456_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_4_31                : 28;
+	uint32_t m_handle_flush               : 1;  /**< Mask Core Filter to handle flush request */
+	uint32_t m_dabort_4ucpl               : 1;  /**< Mask DLLP abort for unexpected CPL */
+	uint32_t m_vend1_drp                  : 1;  /**< Mask Vendor MSG Type 1 dropped silently */
+	uint32_t m_vend0_drp                  : 1;  /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */
+#else
+	uint32_t m_vend0_drp                  : 1;
+	uint32_t m_vend1_drp                  : 1;
+	uint32_t m_dabort_4ucpl               : 1;
+	uint32_t m_handle_flush               : 1;
+	uint32_t reserved_4_31                : 28;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg456_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_2_31                : 30;
 	uint32_t m_vend1_drp                  : 1;  /**< Mask Vendor MSG Type 1 dropped silently */
 	uint32_t m_vend0_drp                  : 1;  /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */
@@ -3769,13 +5064,17 @@ union cvmx_pciercx_cfg456
 	uint32_t m_vend1_drp                  : 1;
 	uint32_t reserved_2_31                : 30;
 #endif
-	} s;
-	struct cvmx_pciercx_cfg456_s          cn52xx;
-	struct cvmx_pciercx_cfg456_s          cn52xxp1;
-	struct cvmx_pciercx_cfg456_s          cn56xx;
-	struct cvmx_pciercx_cfg456_s          cn56xxp1;
-	struct cvmx_pciercx_cfg456_s          cn63xx;
-	struct cvmx_pciercx_cfg456_s          cn63xxp1;
+	} cn52xx;
+	struct cvmx_pciercx_cfg456_cn52xx     cn52xxp1;
+	struct cvmx_pciercx_cfg456_cn52xx     cn56xx;
+	struct cvmx_pciercx_cfg456_cn52xx     cn56xxp1;
+	struct cvmx_pciercx_cfg456_s          cn61xx;
+	struct cvmx_pciercx_cfg456_cn52xx     cn63xx;
+	struct cvmx_pciercx_cfg456_cn52xx     cn63xxp1;
+	struct cvmx_pciercx_cfg456_s          cn66xx;
+	struct cvmx_pciercx_cfg456_s          cn68xx;
+	struct cvmx_pciercx_cfg456_cn52xx     cn68xxp1;
+	struct cvmx_pciercx_cfg456_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg456 cvmx_pciercx_cfg456_t;
 
@@ -3785,12 +5084,10 @@ typedef union cvmx_pciercx_cfg456 cvmx_pciercx_cfg456_t;
  * PCIE_CFG458 = Four hundred fifty-ninth 32-bits of PCIE type 1 config space
  * (Debug Register 0)
  */
-union cvmx_pciercx_cfg458
-{
+union cvmx_pciercx_cfg458 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg458_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg458_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dbg_info_l32                 : 32; /**< The value on cxpl_debug_info[31:0]. */
 #else
 	uint32_t dbg_info_l32                 : 32;
@@ -3800,8 +5097,13 @@ union cvmx_pciercx_cfg458
 	struct cvmx_pciercx_cfg458_s          cn52xxp1;
 	struct cvmx_pciercx_cfg458_s          cn56xx;
 	struct cvmx_pciercx_cfg458_s          cn56xxp1;
+	struct cvmx_pciercx_cfg458_s          cn61xx;
 	struct cvmx_pciercx_cfg458_s          cn63xx;
 	struct cvmx_pciercx_cfg458_s          cn63xxp1;
+	struct cvmx_pciercx_cfg458_s          cn66xx;
+	struct cvmx_pciercx_cfg458_s          cn68xx;
+	struct cvmx_pciercx_cfg458_s          cn68xxp1;
+	struct cvmx_pciercx_cfg458_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg458 cvmx_pciercx_cfg458_t;
 
@@ -3811,12 +5113,10 @@ typedef union cvmx_pciercx_cfg458 cvmx_pciercx_cfg458_t;
  * PCIE_CFG459 = Four hundred sixtieth 32-bits of PCIE type 1 config space
  * (Debug Register 1)
  */
-union cvmx_pciercx_cfg459
-{
+union cvmx_pciercx_cfg459 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg459_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg459_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dbg_info_u32                 : 32; /**< The value on cxpl_debug_info[63:32]. */
 #else
 	uint32_t dbg_info_u32                 : 32;
@@ -3826,8 +5126,13 @@ union cvmx_pciercx_cfg459
 	struct cvmx_pciercx_cfg459_s          cn52xxp1;
 	struct cvmx_pciercx_cfg459_s          cn56xx;
 	struct cvmx_pciercx_cfg459_s          cn56xxp1;
+	struct cvmx_pciercx_cfg459_s          cn61xx;
 	struct cvmx_pciercx_cfg459_s          cn63xx;
 	struct cvmx_pciercx_cfg459_s          cn63xxp1;
+	struct cvmx_pciercx_cfg459_s          cn66xx;
+	struct cvmx_pciercx_cfg459_s          cn68xx;
+	struct cvmx_pciercx_cfg459_s          cn68xxp1;
+	struct cvmx_pciercx_cfg459_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg459 cvmx_pciercx_cfg459_t;
 
@@ -3837,12 +5142,10 @@ typedef union cvmx_pciercx_cfg459 cvmx_pciercx_cfg459_t;
  * PCIE_CFG460 = Four hundred sixty-first 32-bits of PCIE type 1 config space
  * (Transmit Posted FC Credit Status)
  */
-union cvmx_pciercx_cfg460
-{
+union cvmx_pciercx_cfg460 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg460_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg460_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_20_31               : 12;
 	uint32_t tphfcc                       : 8;  /**< Transmit Posted Header FC Credits
                                                          The Posted Header credits advertised by the receiver at the
@@ -3860,8 +5163,13 @@ union cvmx_pciercx_cfg460
 	struct cvmx_pciercx_cfg460_s          cn52xxp1;
 	struct cvmx_pciercx_cfg460_s          cn56xx;
 	struct cvmx_pciercx_cfg460_s          cn56xxp1;
+	struct cvmx_pciercx_cfg460_s          cn61xx;
 	struct cvmx_pciercx_cfg460_s          cn63xx;
 	struct cvmx_pciercx_cfg460_s          cn63xxp1;
+	struct cvmx_pciercx_cfg460_s          cn66xx;
+	struct cvmx_pciercx_cfg460_s          cn68xx;
+	struct cvmx_pciercx_cfg460_s          cn68xxp1;
+	struct cvmx_pciercx_cfg460_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg460 cvmx_pciercx_cfg460_t;
 
@@ -3871,12 +5179,10 @@ typedef union cvmx_pciercx_cfg460 cvmx_pciercx_cfg460_t;
  * PCIE_CFG461 = Four hundred sixty-second 32-bits of PCIE type 1 config space
  * (Transmit Non-Posted FC Credit Status)
  */
-union cvmx_pciercx_cfg461
-{
+union cvmx_pciercx_cfg461 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg461_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg461_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_20_31               : 12;
 	uint32_t tchfcc                       : 8;  /**< Transmit Non-Posted Header FC Credits
                                                          The Non-Posted Header credits advertised by the receiver at the
@@ -3894,8 +5200,13 @@ union cvmx_pciercx_cfg461
 	struct cvmx_pciercx_cfg461_s          cn52xxp1;
 	struct cvmx_pciercx_cfg461_s          cn56xx;
 	struct cvmx_pciercx_cfg461_s          cn56xxp1;
+	struct cvmx_pciercx_cfg461_s          cn61xx;
 	struct cvmx_pciercx_cfg461_s          cn63xx;
 	struct cvmx_pciercx_cfg461_s          cn63xxp1;
+	struct cvmx_pciercx_cfg461_s          cn66xx;
+	struct cvmx_pciercx_cfg461_s          cn68xx;
+	struct cvmx_pciercx_cfg461_s          cn68xxp1;
+	struct cvmx_pciercx_cfg461_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg461 cvmx_pciercx_cfg461_t;
 
@@ -3905,12 +5216,10 @@ typedef union cvmx_pciercx_cfg461 cvmx_pciercx_cfg461_t;
  * PCIE_CFG462 = Four hundred sixty-third 32-bits of PCIE type 1 config space
  * (Transmit Completion FC Credit Status )
  */
-union cvmx_pciercx_cfg462
-{
+union cvmx_pciercx_cfg462 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg462_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg462_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_20_31               : 12;
 	uint32_t tchfcc                       : 8;  /**< Transmit Completion Header FC Credits
                                                          The Completion Header credits advertised by the receiver at the
@@ -3928,8 +5237,13 @@ union cvmx_pciercx_cfg462
 	struct cvmx_pciercx_cfg462_s          cn52xxp1;
 	struct cvmx_pciercx_cfg462_s          cn56xx;
 	struct cvmx_pciercx_cfg462_s          cn56xxp1;
+	struct cvmx_pciercx_cfg462_s          cn61xx;
 	struct cvmx_pciercx_cfg462_s          cn63xx;
 	struct cvmx_pciercx_cfg462_s          cn63xxp1;
+	struct cvmx_pciercx_cfg462_s          cn66xx;
+	struct cvmx_pciercx_cfg462_s          cn68xx;
+	struct cvmx_pciercx_cfg462_s          cn68xxp1;
+	struct cvmx_pciercx_cfg462_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg462 cvmx_pciercx_cfg462_t;
 
@@ -3939,12 +5253,10 @@ typedef union cvmx_pciercx_cfg462 cvmx_pciercx_cfg462_t;
  * PCIE_CFG463 = Four hundred sixty-fourth 32-bits of PCIE type 1 config space
  * (Queue Status)
  */
-union cvmx_pciercx_cfg463
-{
+union cvmx_pciercx_cfg463 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg463_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg463_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_3_31                : 29;
 	uint32_t rqne                         : 1;  /**< Received Queue Not Empty
                                                          Indicates there is data in one or more of the receive buffers. */
@@ -3966,8 +5278,13 @@ union cvmx_pciercx_cfg463
 	struct cvmx_pciercx_cfg463_s          cn52xxp1;
 	struct cvmx_pciercx_cfg463_s          cn56xx;
 	struct cvmx_pciercx_cfg463_s          cn56xxp1;
+	struct cvmx_pciercx_cfg463_s          cn61xx;
 	struct cvmx_pciercx_cfg463_s          cn63xx;
 	struct cvmx_pciercx_cfg463_s          cn63xxp1;
+	struct cvmx_pciercx_cfg463_s          cn66xx;
+	struct cvmx_pciercx_cfg463_s          cn68xx;
+	struct cvmx_pciercx_cfg463_s          cn68xxp1;
+	struct cvmx_pciercx_cfg463_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg463 cvmx_pciercx_cfg463_t;
 
@@ -3977,12 +5294,10 @@ typedef union cvmx_pciercx_cfg463 cvmx_pciercx_cfg463_t;
  * PCIE_CFG464 = Four hundred sixty-fifth 32-bits of PCIE type 1 config space
  * (VC Transmit Arbitration Register 1)
  */
-union cvmx_pciercx_cfg464
-{
+union cvmx_pciercx_cfg464 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg464_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg464_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t wrr_vc3                      : 8;  /**< WRR Weight for VC3 */
 	uint32_t wrr_vc2                      : 8;  /**< WRR Weight for VC2 */
 	uint32_t wrr_vc1                      : 8;  /**< WRR Weight for VC1 */
@@ -3998,8 +5313,13 @@ union cvmx_pciercx_cfg464
 	struct cvmx_pciercx_cfg464_s          cn52xxp1;
 	struct cvmx_pciercx_cfg464_s          cn56xx;
 	struct cvmx_pciercx_cfg464_s          cn56xxp1;
+	struct cvmx_pciercx_cfg464_s          cn61xx;
 	struct cvmx_pciercx_cfg464_s          cn63xx;
 	struct cvmx_pciercx_cfg464_s          cn63xxp1;
+	struct cvmx_pciercx_cfg464_s          cn66xx;
+	struct cvmx_pciercx_cfg464_s          cn68xx;
+	struct cvmx_pciercx_cfg464_s          cn68xxp1;
+	struct cvmx_pciercx_cfg464_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg464 cvmx_pciercx_cfg464_t;
 
@@ -4009,12 +5329,10 @@ typedef union cvmx_pciercx_cfg464 cvmx_pciercx_cfg464_t;
  * PCIE_CFG465 = Four hundred sixty-sixth 32-bits of config space
  * (VC Transmit Arbitration Register 2)
  */
-union cvmx_pciercx_cfg465
-{
+union cvmx_pciercx_cfg465 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg465_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg465_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t wrr_vc7                      : 8;  /**< WRR Weight for VC7 */
 	uint32_t wrr_vc6                      : 8;  /**< WRR Weight for VC6 */
 	uint32_t wrr_vc5                      : 8;  /**< WRR Weight for VC5 */
@@ -4030,8 +5348,13 @@ union cvmx_pciercx_cfg465
 	struct cvmx_pciercx_cfg465_s          cn52xxp1;
 	struct cvmx_pciercx_cfg465_s          cn56xx;
 	struct cvmx_pciercx_cfg465_s          cn56xxp1;
+	struct cvmx_pciercx_cfg465_s          cn61xx;
 	struct cvmx_pciercx_cfg465_s          cn63xx;
 	struct cvmx_pciercx_cfg465_s          cn63xxp1;
+	struct cvmx_pciercx_cfg465_s          cn66xx;
+	struct cvmx_pciercx_cfg465_s          cn68xx;
+	struct cvmx_pciercx_cfg465_s          cn68xxp1;
+	struct cvmx_pciercx_cfg465_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg465 cvmx_pciercx_cfg465_t;
 
@@ -4041,12 +5364,10 @@ typedef union cvmx_pciercx_cfg465 cvmx_pciercx_cfg465_t;
  * PCIE_CFG466 = Four hundred sixty-seventh 32-bits of PCIE type 1 config space
  * (VC0 Posted Receive Queue Control)
  */
-union cvmx_pciercx_cfg466
-{
+union cvmx_pciercx_cfg466 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg466_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg466_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t rx_queue_order               : 1;  /**< VC Ordering for Receive Queues
                                                          Determines the VC ordering rule for the receive queues, used
                                                          only in the segmented-buffer configuration,
@@ -4098,8 +5419,13 @@ union cvmx_pciercx_cfg466
 	struct cvmx_pciercx_cfg466_s          cn52xxp1;
 	struct cvmx_pciercx_cfg466_s          cn56xx;
 	struct cvmx_pciercx_cfg466_s          cn56xxp1;
+	struct cvmx_pciercx_cfg466_s          cn61xx;
 	struct cvmx_pciercx_cfg466_s          cn63xx;
 	struct cvmx_pciercx_cfg466_s          cn63xxp1;
+	struct cvmx_pciercx_cfg466_s          cn66xx;
+	struct cvmx_pciercx_cfg466_s          cn68xx;
+	struct cvmx_pciercx_cfg466_s          cn68xxp1;
+	struct cvmx_pciercx_cfg466_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg466 cvmx_pciercx_cfg466_t;
 
@@ -4109,12 +5435,10 @@ typedef union cvmx_pciercx_cfg466 cvmx_pciercx_cfg466_t;
  * PCIE_CFG467 = Four hundred sixty-eighth 32-bits of PCIE type 1 config space
  * (VC0 Non-Posted Receive Queue Control)
  */
-union cvmx_pciercx_cfg467
-{
+union cvmx_pciercx_cfg467 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg467_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg467_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_24_31               : 8;
 	uint32_t queue_mode                   : 3;  /**< VC0 Non-Posted TLP Queue Mode
                                                          The operating mode of the Non-Posted receive queue for VC0,
@@ -4148,8 +5472,13 @@ union cvmx_pciercx_cfg467
 	struct cvmx_pciercx_cfg467_s          cn52xxp1;
 	struct cvmx_pciercx_cfg467_s          cn56xx;
 	struct cvmx_pciercx_cfg467_s          cn56xxp1;
+	struct cvmx_pciercx_cfg467_s          cn61xx;
 	struct cvmx_pciercx_cfg467_s          cn63xx;
 	struct cvmx_pciercx_cfg467_s          cn63xxp1;
+	struct cvmx_pciercx_cfg467_s          cn66xx;
+	struct cvmx_pciercx_cfg467_s          cn68xx;
+	struct cvmx_pciercx_cfg467_s          cn68xxp1;
+	struct cvmx_pciercx_cfg467_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg467 cvmx_pciercx_cfg467_t;
 
@@ -4159,12 +5488,10 @@ typedef union cvmx_pciercx_cfg467 cvmx_pciercx_cfg467_t;
  * PCIE_CFG468 = Four hundred sixty-ninth 32-bits of PCIE type 1 config space
  * (VC0 Completion Receive Queue Control)
  */
-union cvmx_pciercx_cfg468
-{
+union cvmx_pciercx_cfg468 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg468_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg468_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_24_31               : 8;
 	uint32_t queue_mode                   : 3;  /**< VC0 Completion TLP Queue Mode
                                                          The operating mode of the Completion receive queue for VC0,
@@ -4198,8 +5525,13 @@ union cvmx_pciercx_cfg468
 	struct cvmx_pciercx_cfg468_s          cn52xxp1;
 	struct cvmx_pciercx_cfg468_s          cn56xx;
 	struct cvmx_pciercx_cfg468_s          cn56xxp1;
+	struct cvmx_pciercx_cfg468_s          cn61xx;
 	struct cvmx_pciercx_cfg468_s          cn63xx;
 	struct cvmx_pciercx_cfg468_s          cn63xxp1;
+	struct cvmx_pciercx_cfg468_s          cn66xx;
+	struct cvmx_pciercx_cfg468_s          cn68xx;
+	struct cvmx_pciercx_cfg468_s          cn68xxp1;
+	struct cvmx_pciercx_cfg468_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg468 cvmx_pciercx_cfg468_t;
 
@@ -4209,12 +5541,10 @@ typedef union cvmx_pciercx_cfg468 cvmx_pciercx_cfg468_t;
  * PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 1 config space
  * (VC0 Posted Buffer Depth)
  */
-union cvmx_pciercx_cfg490
-{
+union cvmx_pciercx_cfg490 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg490_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg490_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_26_31               : 6;
 	uint32_t header_depth                 : 10; /**< VC0 Posted Header Queue Depth
                                                          Sets the number of entries in the Posted header queue for VC0
@@ -4238,8 +5568,13 @@ union cvmx_pciercx_cfg490
 	struct cvmx_pciercx_cfg490_s          cn52xxp1;
 	struct cvmx_pciercx_cfg490_s          cn56xx;
 	struct cvmx_pciercx_cfg490_s          cn56xxp1;
+	struct cvmx_pciercx_cfg490_s          cn61xx;
 	struct cvmx_pciercx_cfg490_s          cn63xx;
 	struct cvmx_pciercx_cfg490_s          cn63xxp1;
+	struct cvmx_pciercx_cfg490_s          cn66xx;
+	struct cvmx_pciercx_cfg490_s          cn68xx;
+	struct cvmx_pciercx_cfg490_s          cn68xxp1;
+	struct cvmx_pciercx_cfg490_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg490 cvmx_pciercx_cfg490_t;
 
@@ -4249,12 +5584,10 @@ typedef union cvmx_pciercx_cfg490 cvmx_pciercx_cfg490_t;
  * PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 1 config space
  * (VC0 Non-Posted Buffer Depth)
  */
-union cvmx_pciercx_cfg491
-{
+union cvmx_pciercx_cfg491 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg491_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg491_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_26_31               : 6;
 	uint32_t header_depth                 : 10; /**< VC0 Non-Posted Header Queue Depth
                                                          Sets the number of entries in the Non-Posted header queue for
@@ -4278,8 +5611,13 @@ union cvmx_pciercx_cfg491
 	struct cvmx_pciercx_cfg491_s          cn52xxp1;
 	struct cvmx_pciercx_cfg491_s          cn56xx;
 	struct cvmx_pciercx_cfg491_s          cn56xxp1;
+	struct cvmx_pciercx_cfg491_s          cn61xx;
 	struct cvmx_pciercx_cfg491_s          cn63xx;
 	struct cvmx_pciercx_cfg491_s          cn63xxp1;
+	struct cvmx_pciercx_cfg491_s          cn66xx;
+	struct cvmx_pciercx_cfg491_s          cn68xx;
+	struct cvmx_pciercx_cfg491_s          cn68xxp1;
+	struct cvmx_pciercx_cfg491_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg491 cvmx_pciercx_cfg491_t;
 
@@ -4289,12 +5627,10 @@ typedef union cvmx_pciercx_cfg491 cvmx_pciercx_cfg491_t;
  * PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 1 config space
  * (VC0 Completion Buffer Depth)
  */
-union cvmx_pciercx_cfg492
-{
+union cvmx_pciercx_cfg492 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg492_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg492_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_26_31               : 6;
 	uint32_t header_depth                 : 10; /**< VC0 Completion Header Queue Depth
                                                          Sets the number of entries in the Completion header queue for
@@ -4318,8 +5654,13 @@ union cvmx_pciercx_cfg492
 	struct cvmx_pciercx_cfg492_s          cn52xxp1;
 	struct cvmx_pciercx_cfg492_s          cn56xx;
 	struct cvmx_pciercx_cfg492_s          cn56xxp1;
+	struct cvmx_pciercx_cfg492_s          cn61xx;
 	struct cvmx_pciercx_cfg492_s          cn63xx;
 	struct cvmx_pciercx_cfg492_s          cn63xxp1;
+	struct cvmx_pciercx_cfg492_s          cn66xx;
+	struct cvmx_pciercx_cfg492_s          cn68xx;
+	struct cvmx_pciercx_cfg492_s          cn68xxp1;
+	struct cvmx_pciercx_cfg492_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg492 cvmx_pciercx_cfg492_t;
 
@@ -4329,12 +5670,10 @@ typedef union cvmx_pciercx_cfg492 cvmx_pciercx_cfg492_t;
  * PCIE_CFG515 = Five hundred sixteenth 32-bits of PCIE type 1 config space
  * (Port Logic Register (Gen2))
  */
-union cvmx_pciercx_cfg515
-{
+union cvmx_pciercx_cfg515 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg515_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg515_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_21_31               : 11;
 	uint32_t s_d_e                        : 1;  /**< SEL_DE_EMPHASIS
                                                          Used to set the de-emphasis level for upstream ports. */
@@ -4345,8 +5684,8 @@ union cvmx_pciercx_cfg515
                                                          Indicates the voltage level the PHY should drive. When set to
                                                          1, indicates Full Swing. When set to 0, indicates Low Swing */
 	uint32_t dsc                          : 1;  /**< Directed Speed Change
-                                                         Indicates to the LTSSM whether or not to initiate a speed
-                                                         change. */
+                                                         o a write of '1' will initiate a speed change
+                                                         o always reads a zero */
 	uint32_t le                           : 9;  /**< Lane Enable
                                                          Indicates the number of lanes to check for exit from electrical
                                                          idle in Polling.Active and Polling.Compliance. 1 = x1, 2 = x2,
@@ -4372,8 +5711,13 @@ union cvmx_pciercx_cfg515
 	uint32_t reserved_21_31               : 11;
 #endif
 	} s;
+	struct cvmx_pciercx_cfg515_s          cn61xx;
 	struct cvmx_pciercx_cfg515_s          cn63xx;
 	struct cvmx_pciercx_cfg515_s          cn63xxp1;
+	struct cvmx_pciercx_cfg515_s          cn66xx;
+	struct cvmx_pciercx_cfg515_s          cn68xx;
+	struct cvmx_pciercx_cfg515_s          cn68xxp1;
+	struct cvmx_pciercx_cfg515_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg515 cvmx_pciercx_cfg515_t;
 
@@ -4383,12 +5727,10 @@ typedef union cvmx_pciercx_cfg515 cvmx_pciercx_cfg515_t;
  * PCIE_CFG516 = Five hundred seventeenth 32-bits of PCIE type 1 config space
  * (PHY Status Register)
  */
-union cvmx_pciercx_cfg516
-{
+union cvmx_pciercx_cfg516 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg516_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg516_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t phy_stat                     : 32; /**< PHY Status */
 #else
 	uint32_t phy_stat                     : 32;
@@ -4398,8 +5740,13 @@ union cvmx_pciercx_cfg516
 	struct cvmx_pciercx_cfg516_s          cn52xxp1;
 	struct cvmx_pciercx_cfg516_s          cn56xx;
 	struct cvmx_pciercx_cfg516_s          cn56xxp1;
+	struct cvmx_pciercx_cfg516_s          cn61xx;
 	struct cvmx_pciercx_cfg516_s          cn63xx;
 	struct cvmx_pciercx_cfg516_s          cn63xxp1;
+	struct cvmx_pciercx_cfg516_s          cn66xx;
+	struct cvmx_pciercx_cfg516_s          cn68xx;
+	struct cvmx_pciercx_cfg516_s          cn68xxp1;
+	struct cvmx_pciercx_cfg516_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg516 cvmx_pciercx_cfg516_t;
 
@@ -4409,12 +5756,10 @@ typedef union cvmx_pciercx_cfg516 cvmx_pciercx_cfg516_t;
  * PCIE_CFG517 = Five hundred eighteenth 32-bits of PCIE type 1 config space
  * (PHY Control Register)
  */
-union cvmx_pciercx_cfg517
-{
+union cvmx_pciercx_cfg517 {
 	uint32_t u32;
-	struct cvmx_pciercx_cfg517_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pciercx_cfg517_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t phy_ctrl                     : 32; /**< PHY Control */
 #else
 	uint32_t phy_ctrl                     : 32;
@@ -4424,8 +5769,13 @@ union cvmx_pciercx_cfg517
 	struct cvmx_pciercx_cfg517_s          cn52xxp1;
 	struct cvmx_pciercx_cfg517_s          cn56xx;
 	struct cvmx_pciercx_cfg517_s          cn56xxp1;
+	struct cvmx_pciercx_cfg517_s          cn61xx;
 	struct cvmx_pciercx_cfg517_s          cn63xx;
 	struct cvmx_pciercx_cfg517_s          cn63xxp1;
+	struct cvmx_pciercx_cfg517_s          cn66xx;
+	struct cvmx_pciercx_cfg517_s          cn68xx;
+	struct cvmx_pciercx_cfg517_s          cn68xxp1;
+	struct cvmx_pciercx_cfg517_s          cnf71xx;
 };
 typedef union cvmx_pciercx_cfg517 cvmx_pciercx_cfg517_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-pcm-defs.h b/sys/contrib/octeon-sdk/cvmx-pcm-defs.h
index 808f1b2..b688223 100644
--- a/sys/contrib/octeon-sdk/cvmx-pcm-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-pcm-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_PCM_TYPEDEFS_H__
-#define __CVMX_PCM_TYPEDEFS_H__
+#ifndef __CVMX_PCM_DEFS_H__
+#define __CVMX_PCM_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCM_CLKX_CFG(unsigned long offset)
@@ -58,7 +58,9 @@ static inline uint64_t CVMX_PCM_CLKX_CFG(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_PCM_CLKX_CFG(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000010000ull) + ((offset) & 1) * 16384;
 }
@@ -71,7 +73,9 @@ static inline uint64_t CVMX_PCM_CLKX_DBG(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_PCM_CLKX_DBG(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000010038ull) + ((offset) & 1) * 16384;
 }
@@ -84,7 +88,9 @@ static inline uint64_t CVMX_PCM_CLKX_GEN(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_PCM_CLKX_GEN(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000010008ull) + ((offset) & 1) * 16384;
 }
@@ -95,13 +101,11 @@ static inline uint64_t CVMX_PCM_CLKX_GEN(unsigned long offset)
 /**
  * cvmx_pcm_clk#_cfg
  */
-union cvmx_pcm_clkx_cfg
-{
+union cvmx_pcm_clkx_cfg {
 	uint64_t u64;
-	struct cvmx_pcm_clkx_cfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t fsyncgood                    : 1;  /**< FSYNC status
+	struct cvmx_pcm_clkx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t fsyncgood                    : 1;  /**< FSYNC status                                      |         NS
                                                          If 1, the last frame had a correctly positioned
                                                                fsync pulse
                                                          If 0, none/extra fsync pulse seen on most recent
@@ -110,23 +114,23 @@ union cvmx_pcm_clkx_cfg
                                                          and FSYNCMISSING interrupts are intended for
                                                          detecting loss of sync during normal operation. */
 	uint64_t reserved_48_62               : 15;
-	uint64_t fsyncsamp                    : 16; /**< Number of ECLKs from internal BCLK edge to
+	uint64_t fsyncsamp                    : 16; /**< Number of ECLKs from internal BCLK edge to        |          NS
                                                          sample FSYNC
                                                          NOTE: used to sync to the start of a frame and to
                                                          check for FSYNC errors. */
 	uint64_t reserved_26_31               : 6;
-	uint64_t fsynclen                     : 5;  /**< Number of 1/2 BCLKs FSYNC is asserted for
+	uint64_t fsynclen                     : 5;  /**< Number of 1/2 BCLKs FSYNC is asserted for         |          NS
                                                          NOTE: only used when GEN==1 */
-	uint64_t fsyncloc                     : 5;  /**< FSYNC location, in 1/2 BCLKS before timeslot 0,
+	uint64_t fsyncloc                     : 5;  /**< FSYNC location, in 1/2 BCLKS before timeslot 0,   |          NS
                                                          bit 0.
                                                          NOTE: also used to detect framing errors and
                                                          therefore must have a correct value even if GEN==0 */
-	uint64_t numslots                     : 10; /**< Number of 8-bit slots in a frame
+	uint64_t numslots                     : 10; /**< Number of 8-bit slots in a frame                  |          NS
                                                          NOTE: this, along with EXTRABIT and Fbclk
                                                          determines FSYNC frequency when GEN == 1
                                                          NOTE: also used to detect framing errors and
                                                          therefore must have a correct value even if GEN==0 */
-	uint64_t extrabit                     : 1;  /**< If 0, no frame bit
+	uint64_t extrabit                     : 1;  /**< If 0, no frame bit                                |          NS
                                                          If 1, add one extra bit time for frame bit
                                                          NOTE: if GEN == 1, then FSYNC will be delayed one
                                                          extra bit time.
@@ -136,20 +140,20 @@ union cvmx_pcm_clkx_cfg
                                                          first byte of the frame in the transmit memory
                                                          region.  LSB vs MSB is determined from the setting
                                                          of PCMn_TDM_CFG[LSBFIRST]. */
-	uint64_t bitlen                       : 2;  /**< Number of BCLKs in a bit time.
+	uint64_t bitlen                       : 2;  /**< Number of BCLKs in a bit time.                    |          NS
                                                          0 : 1 BCLK
                                                          1 : 2 BCLKs
                                                          2 : 4 BCLKs
                                                          3 : operation undefined */
-	uint64_t bclkpol                      : 1;  /**< If 0, BCLK rise edge is start of bit time
+	uint64_t bclkpol                      : 1;  /**< If 0, BCLK rise edge is start of bit time         |          NS
                                                          If 1, BCLK fall edge is start of bit time
                                                          NOTE: also used to detect framing errors and
                                                          therefore must have a correct value even if GEN==0 */
-	uint64_t fsyncpol                     : 1;  /**< If 0, FSYNC idles low, asserts high
+	uint64_t fsyncpol                     : 1;  /**< If 0, FSYNC idles low, asserts high               |          NS
                                                          If 1, FSYNC idles high, asserts low
                                                          NOTE: also used to detect framing errors and
                                                          therefore must have a correct value even if GEN==0 */
-	uint64_t ena                          : 1;  /**< If 0, Clock receiving logic is doing nothing
+	uint64_t ena                          : 1;  /**< If 0, Clock receiving logic is doing nothing      |          NS
                                                          1, Clock receiving logic is looking for sync */
 #else
 	uint64_t ena                          : 1;
@@ -169,19 +173,19 @@ union cvmx_pcm_clkx_cfg
 	struct cvmx_pcm_clkx_cfg_s            cn30xx;
 	struct cvmx_pcm_clkx_cfg_s            cn31xx;
 	struct cvmx_pcm_clkx_cfg_s            cn50xx;
+	struct cvmx_pcm_clkx_cfg_s            cn61xx;
+	struct cvmx_pcm_clkx_cfg_s            cnf71xx;
 };
 typedef union cvmx_pcm_clkx_cfg cvmx_pcm_clkx_cfg_t;
 
 /**
  * cvmx_pcm_clk#_dbg
  */
-union cvmx_pcm_clkx_dbg
-{
+union cvmx_pcm_clkx_dbg {
 	uint64_t u64;
-	struct cvmx_pcm_clkx_dbg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t debuginfo                    : 64; /**< Miscellaneous debug information */
+	struct cvmx_pcm_clkx_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t debuginfo                    : 64; /**< Miscellaneous debug information                   |           NS */
 #else
 	uint64_t debuginfo                    : 64;
 #endif
@@ -189,28 +193,28 @@ union cvmx_pcm_clkx_dbg
 	struct cvmx_pcm_clkx_dbg_s            cn30xx;
 	struct cvmx_pcm_clkx_dbg_s            cn31xx;
 	struct cvmx_pcm_clkx_dbg_s            cn50xx;
+	struct cvmx_pcm_clkx_dbg_s            cn61xx;
+	struct cvmx_pcm_clkx_dbg_s            cnf71xx;
 };
 typedef union cvmx_pcm_clkx_dbg cvmx_pcm_clkx_dbg_t;
 
 /**
  * cvmx_pcm_clk#_gen
  */
-union cvmx_pcm_clkx_gen
-{
+union cvmx_pcm_clkx_gen {
 	uint64_t u64;
-	struct cvmx_pcm_clkx_gen_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t deltasamp                    : 16; /**< Signed number of ECLKs to move sampled BCLK edge
+	struct cvmx_pcm_clkx_gen_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t deltasamp                    : 16; /**< Signed number of ECLKs to move sampled BCLK edge   |          NS
                                                          NOTE: the complete number of ECLKs to move is:
                                                                    NUMSAMP + 2 + 1 + DELTASAMP
                                                                NUMSAMP to compensate for sampling delay
                                                                + 2 to compensate for dual-rank synchronizer
                                                                + 1 for uncertainity
                                                                + DELTASAMP to CMA/debugging */
-	uint64_t numsamp                      : 16; /**< Number of ECLK samples to detect BCLK change when
+	uint64_t numsamp                      : 16; /**< Number of ECLK samples to detect BCLK change when  |          NS
                                                          receiving clock. */
-	uint64_t n                            : 32; /**< Determines BCLK frequency when generating clock
+	uint64_t n                            : 32; /**< Determines BCLK frequency when generating clock    |          NS
                                                          NOTE: Fbclk = Feclk * N / 2^32
                                                                N = (Fbclk / Feclk) * 2^32
                                                          NOTE: writing N == 0 stops the clock generator, and
@@ -224,6 +228,8 @@ union cvmx_pcm_clkx_gen
 	struct cvmx_pcm_clkx_gen_s            cn30xx;
 	struct cvmx_pcm_clkx_gen_s            cn31xx;
 	struct cvmx_pcm_clkx_gen_s            cn50xx;
+	struct cvmx_pcm_clkx_gen_s            cn61xx;
+	struct cvmx_pcm_clkx_gen_s            cnf71xx;
 };
 typedef union cvmx_pcm_clkx_gen cvmx_pcm_clkx_gen_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-pcmx-defs.h b/sys/contrib/octeon-sdk/cvmx-pcmx-defs.h
index 6e2495b..8d42db8 100644
--- a/sys/contrib/octeon-sdk/cvmx-pcmx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-pcmx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_PCMX_TYPEDEFS_H__
-#define __CVMX_PCMX_TYPEDEFS_H__
+#ifndef __CVMX_PCMX_DEFS_H__
+#define __CVMX_PCMX_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCMX_DMA_CFG(unsigned long offset)
@@ -58,7 +58,9 @@ static inline uint64_t CVMX_PCMX_DMA_CFG(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_DMA_CFG(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000010018ull) + ((offset) & 3) * 16384;
 }
@@ -71,7 +73,9 @@ static inline uint64_t CVMX_PCMX_INT_ENA(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_INT_ENA(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000010020ull) + ((offset) & 3) * 16384;
 }
@@ -84,7 +88,9 @@ static inline uint64_t CVMX_PCMX_INT_SUM(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_INT_SUM(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000010028ull) + ((offset) & 3) * 16384;
 }
@@ -97,7 +103,9 @@ static inline uint64_t CVMX_PCMX_RXADDR(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_RXADDR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000010068ull) + ((offset) & 3) * 16384;
 }
@@ -110,7 +118,9 @@ static inline uint64_t CVMX_PCMX_RXCNT(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_RXCNT(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000010060ull) + ((offset) & 3) * 16384;
 }
@@ -123,7 +133,9 @@ static inline uint64_t CVMX_PCMX_RXMSK0(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_RXMSK0(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00010700000100C0ull) + ((offset) & 3) * 16384;
 }
@@ -136,7 +148,9 @@ static inline uint64_t CVMX_PCMX_RXMSK1(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_RXMSK1(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00010700000100C8ull) + ((offset) & 3) * 16384;
 }
@@ -149,7 +163,9 @@ static inline uint64_t CVMX_PCMX_RXMSK2(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_RXMSK2(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00010700000100D0ull) + ((offset) & 3) * 16384;
 }
@@ -162,7 +178,9 @@ static inline uint64_t CVMX_PCMX_RXMSK3(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_RXMSK3(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00010700000100D8ull) + ((offset) & 3) * 16384;
 }
@@ -175,7 +193,9 @@ static inline uint64_t CVMX_PCMX_RXMSK4(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_RXMSK4(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00010700000100E0ull) + ((offset) & 3) * 16384;
 }
@@ -188,7 +208,9 @@ static inline uint64_t CVMX_PCMX_RXMSK5(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_RXMSK5(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00010700000100E8ull) + ((offset) & 3) * 16384;
 }
@@ -201,7 +223,9 @@ static inline uint64_t CVMX_PCMX_RXMSK6(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_RXMSK6(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00010700000100F0ull) + ((offset) & 3) * 16384;
 }
@@ -214,7 +238,9 @@ static inline uint64_t CVMX_PCMX_RXMSK7(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_RXMSK7(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00010700000100F8ull) + ((offset) & 3) * 16384;
 }
@@ -227,7 +253,9 @@ static inline uint64_t CVMX_PCMX_RXSTART(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_RXSTART(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000010058ull) + ((offset) & 3) * 16384;
 }
@@ -240,7 +268,9 @@ static inline uint64_t CVMX_PCMX_TDM_CFG(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_TDM_CFG(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000010010ull) + ((offset) & 3) * 16384;
 }
@@ -253,7 +283,9 @@ static inline uint64_t CVMX_PCMX_TDM_DBG(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_TDM_DBG(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000010030ull) + ((offset) & 3) * 16384;
 }
@@ -266,7 +298,9 @@ static inline uint64_t CVMX_PCMX_TXADDR(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_TXADDR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000010050ull) + ((offset) & 3) * 16384;
 }
@@ -279,7 +313,9 @@ static inline uint64_t CVMX_PCMX_TXCNT(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_TXCNT(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000010048ull) + ((offset) & 3) * 16384;
 }
@@ -292,7 +328,9 @@ static inline uint64_t CVMX_PCMX_TXMSK0(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_TXMSK0(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000010080ull) + ((offset) & 3) * 16384;
 }
@@ -305,7 +343,9 @@ static inline uint64_t CVMX_PCMX_TXMSK1(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_TXMSK1(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000010088ull) + ((offset) & 3) * 16384;
 }
@@ -318,7 +358,9 @@ static inline uint64_t CVMX_PCMX_TXMSK2(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_TXMSK2(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000010090ull) + ((offset) & 3) * 16384;
 }
@@ -331,7 +373,9 @@ static inline uint64_t CVMX_PCMX_TXMSK3(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_TXMSK3(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000010098ull) + ((offset) & 3) * 16384;
 }
@@ -344,7 +388,9 @@ static inline uint64_t CVMX_PCMX_TXMSK4(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_TXMSK4(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00010700000100A0ull) + ((offset) & 3) * 16384;
 }
@@ -357,7 +403,9 @@ static inline uint64_t CVMX_PCMX_TXMSK5(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_TXMSK5(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00010700000100A8ull) + ((offset) & 3) * 16384;
 }
@@ -370,7 +418,9 @@ static inline uint64_t CVMX_PCMX_TXMSK6(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_TXMSK6(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00010700000100B0ull) + ((offset) & 3) * 16384;
 }
@@ -383,7 +433,9 @@ static inline uint64_t CVMX_PCMX_TXMSK7(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_TXMSK7(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00010700000100B8ull) + ((offset) & 3) * 16384;
 }
@@ -396,7 +448,9 @@ static inline uint64_t CVMX_PCMX_TXSTART(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PCMX_TXSTART(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000010040ull) + ((offset) & 3) * 16384;
 }
@@ -407,32 +461,30 @@ static inline uint64_t CVMX_PCMX_TXSTART(unsigned long offset)
 /**
  * cvmx_pcm#_dma_cfg
  */
-union cvmx_pcmx_dma_cfg
-{
+union cvmx_pcmx_dma_cfg {
 	uint64_t u64;
-	struct cvmx_pcmx_dma_cfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t rdpend                       : 1;  /**< If 0, no L2C read responses pending
+	struct cvmx_pcmx_dma_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rdpend                       : 1;  /**< If 0, no L2C read responses pending               |          NS
                                                             1, L2C read responses are outstanding
                                                          NOTE: When restarting after stopping a running TDM
                                                          engine, software must wait for RDPEND to read 0
                                                          before writing PCMn_TDM_CFG[ENABLE] to a 1 */
 	uint64_t reserved_54_62               : 9;
-	uint64_t rxslots                      : 10; /**< Number of 8-bit slots to receive per frame
+	uint64_t rxslots                      : 10; /**< Number of 8-bit slots to receive per frame        |          NS
                                                          (number of slots in a receive superframe) */
 	uint64_t reserved_42_43               : 2;
-	uint64_t txslots                      : 10; /**< Number of 8-bit slots to transmit per frame
+	uint64_t txslots                      : 10; /**< Number of 8-bit slots to transmit per frame       |          NS
                                                          (number of slots in a transmit superframe) */
 	uint64_t reserved_30_31               : 2;
-	uint64_t rxst                         : 10; /**< Number of frame writes for interrupt */
+	uint64_t rxst                         : 10; /**< Number of frame writes for interrupt              |          NS */
 	uint64_t reserved_19_19               : 1;
-	uint64_t useldt                       : 1;  /**< If 0, use LDI command to read from L2C
+	uint64_t useldt                       : 1;  /**< If 0, use LDI command to read from L2C            |          NS
                                                          1, use LDT command to read from L2C */
-	uint64_t txrd                         : 10; /**< Number of frame reads for interrupt */
-	uint64_t fetchsiz                     : 4;  /**< FETCHSIZ+1 timeslots are read when threshold is
+	uint64_t txrd                         : 10; /**< Number of frame reads for interrupt               |          NS */
+	uint64_t fetchsiz                     : 4;  /**< FETCHSIZ+1 timeslots are read when threshold is   |          NS
                                                          reached. */
-	uint64_t thresh                       : 4;  /**< If number of bytes remaining in the DMA fifo is <=
+	uint64_t thresh                       : 4;  /**< If number of bytes remaining in the DMA fifo is <=|          NS
                                                          THRESH, initiate a fetch of timeslot data from the
                                                          transmit memory region.
                                                          NOTE: there are only 16B of buffer for each engine
@@ -458,31 +510,31 @@ union cvmx_pcmx_dma_cfg
 	struct cvmx_pcmx_dma_cfg_s            cn30xx;
 	struct cvmx_pcmx_dma_cfg_s            cn31xx;
 	struct cvmx_pcmx_dma_cfg_s            cn50xx;
+	struct cvmx_pcmx_dma_cfg_s            cn61xx;
+	struct cvmx_pcmx_dma_cfg_s            cnf71xx;
 };
 typedef union cvmx_pcmx_dma_cfg cvmx_pcmx_dma_cfg_t;
 
 /**
  * cvmx_pcm#_int_ena
  */
-union cvmx_pcmx_int_ena
-{
+union cvmx_pcmx_int_ena {
 	uint64_t u64;
-	struct cvmx_pcmx_int_ena_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcmx_int_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
-	uint64_t rxovf                        : 1;  /**< Enable interrupt if RX byte overflows */
-	uint64_t txempty                      : 1;  /**< Enable interrupt on TX byte empty */
-	uint64_t txrd                         : 1;  /**< Enable DMA engine frame read interrupts */
-	uint64_t txwrap                       : 1;  /**< Enable TX region wrap interrupts */
-	uint64_t rxst                         : 1;  /**< Enable DMA engine frame store interrupts */
-	uint64_t rxwrap                       : 1;  /**< Enable RX region wrap interrupts */
-	uint64_t fsyncextra                   : 1;  /**< Enable FSYNC extra interrupts
+	uint64_t rxovf                        : 1;  /**< Enable interrupt if RX byte overflows           |          NS */
+	uint64_t txempty                      : 1;  /**< Enable interrupt on TX byte empty               |          NS */
+	uint64_t txrd                         : 1;  /**< Enable DMA engine frame read interrupts         |          NS */
+	uint64_t txwrap                       : 1;  /**< Enable TX region wrap interrupts                |          NS */
+	uint64_t rxst                         : 1;  /**< Enable DMA engine frame store interrupts        |          NS */
+	uint64_t rxwrap                       : 1;  /**< Enable RX region wrap interrupts                |          NS */
+	uint64_t fsyncextra                   : 1;  /**< Enable FSYNC extra interrupts                   |          NS
                                                          NOTE: FSYNCEXTRA errors are defined as an FSYNC
                                                          found in the "wrong" spot of a frame given the
                                                          programming of PCMn_CLK_CFG[NUMSLOTS] and
                                                          PCMn_CLK_CFG[EXTRABIT]. */
-	uint64_t fsyncmissed                  : 1;  /**< Enable FSYNC missed interrupts
+	uint64_t fsyncmissed                  : 1;  /**< Enable FSYNC missed interrupts                  |          NS
                                                          NOTE: FSYNCMISSED errors are defined as an FSYNC
                                                          missing from the correct spot in a frame given
                                                          the programming of PCMn_CLK_CFG[NUMSLOTS] and
@@ -502,27 +554,27 @@ union cvmx_pcmx_int_ena
 	struct cvmx_pcmx_int_ena_s            cn30xx;
 	struct cvmx_pcmx_int_ena_s            cn31xx;
 	struct cvmx_pcmx_int_ena_s            cn50xx;
+	struct cvmx_pcmx_int_ena_s            cn61xx;
+	struct cvmx_pcmx_int_ena_s            cnf71xx;
 };
 typedef union cvmx_pcmx_int_ena cvmx_pcmx_int_ena_t;
 
 /**
  * cvmx_pcm#_int_sum
  */
-union cvmx_pcmx_int_sum
-{
+union cvmx_pcmx_int_sum {
 	uint64_t u64;
-	struct cvmx_pcmx_int_sum_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcmx_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
-	uint64_t rxovf                        : 1;  /**< RX byte overflowed */
-	uint64_t txempty                      : 1;  /**< TX byte was empty when sampled */
-	uint64_t txrd                         : 1;  /**< DMA engine frame read interrupt occurred */
-	uint64_t txwrap                       : 1;  /**< TX region wrap interrupt occurred */
-	uint64_t rxst                         : 1;  /**< DMA engine frame store interrupt occurred */
-	uint64_t rxwrap                       : 1;  /**< RX region wrap interrupt occurred */
-	uint64_t fsyncextra                   : 1;  /**< FSYNC extra interrupt occurred */
-	uint64_t fsyncmissed                  : 1;  /**< FSYNC missed interrupt occurred */
+	uint64_t rxovf                        : 1;  /**< RX byte overflowed                              |           NS */
+	uint64_t txempty                      : 1;  /**< TX byte was empty when sampled                  |           NS */
+	uint64_t txrd                         : 1;  /**< DMA engine frame read interrupt occurred        |           NS */
+	uint64_t txwrap                       : 1;  /**< TX region wrap interrupt occurred               |           NS */
+	uint64_t rxst                         : 1;  /**< DMA engine frame store interrupt occurred       |           NS */
+	uint64_t rxwrap                       : 1;  /**< RX region wrap interrupt occurred               |           NS */
+	uint64_t fsyncextra                   : 1;  /**< FSYNC extra interrupt occurred                  |           NS */
+	uint64_t fsyncmissed                  : 1;  /**< FSYNC missed interrupt occurred                 |           NS */
 #else
 	uint64_t fsyncmissed                  : 1;
 	uint64_t fsyncextra                   : 1;
@@ -538,20 +590,20 @@ union cvmx_pcmx_int_sum
 	struct cvmx_pcmx_int_sum_s            cn30xx;
 	struct cvmx_pcmx_int_sum_s            cn31xx;
 	struct cvmx_pcmx_int_sum_s            cn50xx;
+	struct cvmx_pcmx_int_sum_s            cn61xx;
+	struct cvmx_pcmx_int_sum_s            cnf71xx;
 };
 typedef union cvmx_pcmx_int_sum cvmx_pcmx_int_sum_t;
 
 /**
  * cvmx_pcm#_rxaddr
  */
-union cvmx_pcmx_rxaddr
-{
+union cvmx_pcmx_rxaddr {
 	uint64_t u64;
-	struct cvmx_pcmx_rxaddr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcmx_rxaddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 36; /**< Address of the next write to the receive memory
+	uint64_t addr                         : 36; /**< Address of the next write to the receive memory    |           NS
                                                          region */
 #else
 	uint64_t addr                         : 36;
@@ -561,20 +613,20 @@ union cvmx_pcmx_rxaddr
 	struct cvmx_pcmx_rxaddr_s             cn30xx;
 	struct cvmx_pcmx_rxaddr_s             cn31xx;
 	struct cvmx_pcmx_rxaddr_s             cn50xx;
+	struct cvmx_pcmx_rxaddr_s             cn61xx;
+	struct cvmx_pcmx_rxaddr_s             cnf71xx;
 };
 typedef union cvmx_pcmx_rxaddr cvmx_pcmx_rxaddr_t;
 
 /**
  * cvmx_pcm#_rxcnt
  */
-union cvmx_pcmx_rxcnt
-{
+union cvmx_pcmx_rxcnt {
 	uint64_t u64;
-	struct cvmx_pcmx_rxcnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcmx_rxcnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
-	uint64_t cnt                          : 16; /**< Number of superframes in receive memory region */
+	uint64_t cnt                          : 16; /**< Number of superframes in receive memory region     |          NS */
 #else
 	uint64_t cnt                          : 16;
 	uint64_t reserved_16_63               : 48;
@@ -583,19 +635,19 @@ union cvmx_pcmx_rxcnt
 	struct cvmx_pcmx_rxcnt_s              cn30xx;
 	struct cvmx_pcmx_rxcnt_s              cn31xx;
 	struct cvmx_pcmx_rxcnt_s              cn50xx;
+	struct cvmx_pcmx_rxcnt_s              cn61xx;
+	struct cvmx_pcmx_rxcnt_s              cnf71xx;
 };
 typedef union cvmx_pcmx_rxcnt cvmx_pcmx_rxcnt_t;
 
 /**
  * cvmx_pcm#_rxmsk0
  */
-union cvmx_pcmx_rxmsk0
-{
+union cvmx_pcmx_rxmsk0 {
 	uint64_t u64;
-	struct cvmx_pcmx_rxmsk0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t mask                         : 64; /**< Receive mask bits for slots 63 to 0
+	struct cvmx_pcmx_rxmsk0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mask                         : 64; /**< Receive mask bits for slots 63 to 0                |          NS
                                                          (1 means transmit, 0 means don't transmit) */
 #else
 	uint64_t mask                         : 64;
@@ -604,19 +656,19 @@ union cvmx_pcmx_rxmsk0
 	struct cvmx_pcmx_rxmsk0_s             cn30xx;
 	struct cvmx_pcmx_rxmsk0_s             cn31xx;
 	struct cvmx_pcmx_rxmsk0_s             cn50xx;
+	struct cvmx_pcmx_rxmsk0_s             cn61xx;
+	struct cvmx_pcmx_rxmsk0_s             cnf71xx;
 };
 typedef union cvmx_pcmx_rxmsk0 cvmx_pcmx_rxmsk0_t;
 
 /**
  * cvmx_pcm#_rxmsk1
  */
-union cvmx_pcmx_rxmsk1
-{
+union cvmx_pcmx_rxmsk1 {
 	uint64_t u64;
-	struct cvmx_pcmx_rxmsk1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t mask                         : 64; /**< Receive mask bits for slots 127 to 64
+	struct cvmx_pcmx_rxmsk1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mask                         : 64; /**< Receive mask bits for slots 127 to 64              |          NS
                                                          (1 means transmit, 0 means don't transmit) */
 #else
 	uint64_t mask                         : 64;
@@ -625,19 +677,19 @@ union cvmx_pcmx_rxmsk1
 	struct cvmx_pcmx_rxmsk1_s             cn30xx;
 	struct cvmx_pcmx_rxmsk1_s             cn31xx;
 	struct cvmx_pcmx_rxmsk1_s             cn50xx;
+	struct cvmx_pcmx_rxmsk1_s             cn61xx;
+	struct cvmx_pcmx_rxmsk1_s             cnf71xx;
 };
 typedef union cvmx_pcmx_rxmsk1 cvmx_pcmx_rxmsk1_t;
 
 /**
  * cvmx_pcm#_rxmsk2
  */
-union cvmx_pcmx_rxmsk2
-{
+union cvmx_pcmx_rxmsk2 {
 	uint64_t u64;
-	struct cvmx_pcmx_rxmsk2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t mask                         : 64; /**< Receive mask bits for slots 191 to 128
+	struct cvmx_pcmx_rxmsk2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mask                         : 64; /**< Receive mask bits for slots 191 to 128             |          NS
                                                          (1 means transmit, 0 means don't transmit) */
 #else
 	uint64_t mask                         : 64;
@@ -646,19 +698,19 @@ union cvmx_pcmx_rxmsk2
 	struct cvmx_pcmx_rxmsk2_s             cn30xx;
 	struct cvmx_pcmx_rxmsk2_s             cn31xx;
 	struct cvmx_pcmx_rxmsk2_s             cn50xx;
+	struct cvmx_pcmx_rxmsk2_s             cn61xx;
+	struct cvmx_pcmx_rxmsk2_s             cnf71xx;
 };
 typedef union cvmx_pcmx_rxmsk2 cvmx_pcmx_rxmsk2_t;
 
 /**
  * cvmx_pcm#_rxmsk3
  */
-union cvmx_pcmx_rxmsk3
-{
+union cvmx_pcmx_rxmsk3 {
 	uint64_t u64;
-	struct cvmx_pcmx_rxmsk3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t mask                         : 64; /**< Receive mask bits for slots 255 to 192
+	struct cvmx_pcmx_rxmsk3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mask                         : 64; /**< Receive mask bits for slots 255 to 192             |          NS
                                                          (1 means transmit, 0 means don't transmit) */
 #else
 	uint64_t mask                         : 64;
@@ -667,19 +719,19 @@ union cvmx_pcmx_rxmsk3
 	struct cvmx_pcmx_rxmsk3_s             cn30xx;
 	struct cvmx_pcmx_rxmsk3_s             cn31xx;
 	struct cvmx_pcmx_rxmsk3_s             cn50xx;
+	struct cvmx_pcmx_rxmsk3_s             cn61xx;
+	struct cvmx_pcmx_rxmsk3_s             cnf71xx;
 };
 typedef union cvmx_pcmx_rxmsk3 cvmx_pcmx_rxmsk3_t;
 
 /**
  * cvmx_pcm#_rxmsk4
  */
-union cvmx_pcmx_rxmsk4
-{
+union cvmx_pcmx_rxmsk4 {
 	uint64_t u64;
-	struct cvmx_pcmx_rxmsk4_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t mask                         : 64; /**< Receive mask bits for slots 319 to 256
+	struct cvmx_pcmx_rxmsk4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mask                         : 64; /**< Receive mask bits for slots 319 to 256             |          NS
                                                          (1 means transmit, 0 means don't transmit) */
 #else
 	uint64_t mask                         : 64;
@@ -688,19 +740,19 @@ union cvmx_pcmx_rxmsk4
 	struct cvmx_pcmx_rxmsk4_s             cn30xx;
 	struct cvmx_pcmx_rxmsk4_s             cn31xx;
 	struct cvmx_pcmx_rxmsk4_s             cn50xx;
+	struct cvmx_pcmx_rxmsk4_s             cn61xx;
+	struct cvmx_pcmx_rxmsk4_s             cnf71xx;
 };
 typedef union cvmx_pcmx_rxmsk4 cvmx_pcmx_rxmsk4_t;
 
 /**
  * cvmx_pcm#_rxmsk5
  */
-union cvmx_pcmx_rxmsk5
-{
+union cvmx_pcmx_rxmsk5 {
 	uint64_t u64;
-	struct cvmx_pcmx_rxmsk5_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t mask                         : 64; /**< Receive mask bits for slots 383 to 320
+	struct cvmx_pcmx_rxmsk5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mask                         : 64; /**< Receive mask bits for slots 383 to 320             |          NS
                                                          (1 means transmit, 0 means don't transmit) */
 #else
 	uint64_t mask                         : 64;
@@ -709,19 +761,19 @@ union cvmx_pcmx_rxmsk5
 	struct cvmx_pcmx_rxmsk5_s             cn30xx;
 	struct cvmx_pcmx_rxmsk5_s             cn31xx;
 	struct cvmx_pcmx_rxmsk5_s             cn50xx;
+	struct cvmx_pcmx_rxmsk5_s             cn61xx;
+	struct cvmx_pcmx_rxmsk5_s             cnf71xx;
 };
 typedef union cvmx_pcmx_rxmsk5 cvmx_pcmx_rxmsk5_t;
 
 /**
  * cvmx_pcm#_rxmsk6
  */
-union cvmx_pcmx_rxmsk6
-{
+union cvmx_pcmx_rxmsk6 {
 	uint64_t u64;
-	struct cvmx_pcmx_rxmsk6_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t mask                         : 64; /**< Receive mask bits for slots 447 to 384
+	struct cvmx_pcmx_rxmsk6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mask                         : 64; /**< Receive mask bits for slots 447 to 384             |          NS
                                                          (1 means transmit, 0 means don't transmit) */
 #else
 	uint64_t mask                         : 64;
@@ -730,19 +782,19 @@ union cvmx_pcmx_rxmsk6
 	struct cvmx_pcmx_rxmsk6_s             cn30xx;
 	struct cvmx_pcmx_rxmsk6_s             cn31xx;
 	struct cvmx_pcmx_rxmsk6_s             cn50xx;
+	struct cvmx_pcmx_rxmsk6_s             cn61xx;
+	struct cvmx_pcmx_rxmsk6_s             cnf71xx;
 };
 typedef union cvmx_pcmx_rxmsk6 cvmx_pcmx_rxmsk6_t;
 
 /**
  * cvmx_pcm#_rxmsk7
  */
-union cvmx_pcmx_rxmsk7
-{
+union cvmx_pcmx_rxmsk7 {
 	uint64_t u64;
-	struct cvmx_pcmx_rxmsk7_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t mask                         : 64; /**< Receive mask bits for slots 511 to 448
+	struct cvmx_pcmx_rxmsk7_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mask                         : 64; /**< Receive mask bits for slots 511 to 448             |          NS
                                                          (1 means transmit, 0 means don't transmit) */
 #else
 	uint64_t mask                         : 64;
@@ -751,20 +803,20 @@ union cvmx_pcmx_rxmsk7
 	struct cvmx_pcmx_rxmsk7_s             cn30xx;
 	struct cvmx_pcmx_rxmsk7_s             cn31xx;
 	struct cvmx_pcmx_rxmsk7_s             cn50xx;
+	struct cvmx_pcmx_rxmsk7_s             cn61xx;
+	struct cvmx_pcmx_rxmsk7_s             cnf71xx;
 };
 typedef union cvmx_pcmx_rxmsk7 cvmx_pcmx_rxmsk7_t;
 
 /**
  * cvmx_pcm#_rxstart
  */
-union cvmx_pcmx_rxstart
-{
+union cvmx_pcmx_rxstart {
 	uint64_t u64;
-	struct cvmx_pcmx_rxstart_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcmx_rxstart_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 33; /**< Starting address for the receive memory region */
+	uint64_t addr                         : 33; /**< Starting address for the receive memory region     |          NS */
 	uint64_t reserved_0_2                 : 3;
 #else
 	uint64_t reserved_0_2                 : 3;
@@ -775,29 +827,29 @@ union cvmx_pcmx_rxstart
 	struct cvmx_pcmx_rxstart_s            cn30xx;
 	struct cvmx_pcmx_rxstart_s            cn31xx;
 	struct cvmx_pcmx_rxstart_s            cn50xx;
+	struct cvmx_pcmx_rxstart_s            cn61xx;
+	struct cvmx_pcmx_rxstart_s            cnf71xx;
 };
 typedef union cvmx_pcmx_rxstart cvmx_pcmx_rxstart_t;
 
 /**
  * cvmx_pcm#_tdm_cfg
  */
-union cvmx_pcmx_tdm_cfg
-{
+union cvmx_pcmx_tdm_cfg {
 	uint64_t u64;
-	struct cvmx_pcmx_tdm_cfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t drvtim                       : 16; /**< Number of ECLKs from start of bit time to stop
+	struct cvmx_pcmx_tdm_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t drvtim                       : 16; /**< Number of ECLKs from start of bit time to stop    |          NS
                                                          driving last bit of timeslot (if not driving next
                                                          timeslot) */
-	uint64_t samppt                       : 16; /**< Number of ECLKs from start of bit time to sample
+	uint64_t samppt                       : 16; /**< Number of ECLKs from start of bit time to sample  |          NS
                                                          data bit. */
 	uint64_t reserved_3_31                : 29;
-	uint64_t lsbfirst                     : 1;  /**< If 0, shift/receive MSB first
+	uint64_t lsbfirst                     : 1;  /**< If 0, shift/receive MSB first                     |          NS
                                                          1, shift/receive LSB first */
-	uint64_t useclk1                      : 1;  /**< If 0, this PCM is based on BCLK/FSYNC0
+	uint64_t useclk1                      : 1;  /**< If 0, this PCM is based on BCLK/FSYNC0            |          NS
                                                          1, this PCM is based on BCLK/FSYNC1 */
-	uint64_t enable                       : 1;  /**< If 1, PCM is enabled, otherwise pins are GPIOs
+	uint64_t enable                       : 1;  /**< If 1, PCM is enabled, otherwise pins are GPIOs    |          NS
                                                          NOTE: when TDM is disabled by detection of an
                                                          FSYNC error all transmission and reception is
                                                          halted.  In addition, PCMn_TX/RXADDR are updated
@@ -815,19 +867,19 @@ union cvmx_pcmx_tdm_cfg
 	struct cvmx_pcmx_tdm_cfg_s            cn30xx;
 	struct cvmx_pcmx_tdm_cfg_s            cn31xx;
 	struct cvmx_pcmx_tdm_cfg_s            cn50xx;
+	struct cvmx_pcmx_tdm_cfg_s            cn61xx;
+	struct cvmx_pcmx_tdm_cfg_s            cnf71xx;
 };
 typedef union cvmx_pcmx_tdm_cfg cvmx_pcmx_tdm_cfg_t;
 
 /**
  * cvmx_pcm#_tdm_dbg
  */
-union cvmx_pcmx_tdm_dbg
-{
+union cvmx_pcmx_tdm_dbg {
 	uint64_t u64;
-	struct cvmx_pcmx_tdm_dbg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t debuginfo                    : 64; /**< Miscellaneous debug information */
+	struct cvmx_pcmx_tdm_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t debuginfo                    : 64; /**< Miscellaneous debug information                   |           NS */
 #else
 	uint64_t debuginfo                    : 64;
 #endif
@@ -835,22 +887,22 @@ union cvmx_pcmx_tdm_dbg
 	struct cvmx_pcmx_tdm_dbg_s            cn30xx;
 	struct cvmx_pcmx_tdm_dbg_s            cn31xx;
 	struct cvmx_pcmx_tdm_dbg_s            cn50xx;
+	struct cvmx_pcmx_tdm_dbg_s            cn61xx;
+	struct cvmx_pcmx_tdm_dbg_s            cnf71xx;
 };
 typedef union cvmx_pcmx_tdm_dbg cvmx_pcmx_tdm_dbg_t;
 
 /**
  * cvmx_pcm#_txaddr
  */
-union cvmx_pcmx_txaddr
-{
+union cvmx_pcmx_txaddr {
 	uint64_t u64;
-	struct cvmx_pcmx_txaddr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcmx_txaddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 33; /**< Address of the next read from the transmit memory
+	uint64_t addr                         : 33; /**< Address of the next read from the transmit memory  |           NS
                                                          region */
-	uint64_t fram                         : 3;  /**< Frame offset
+	uint64_t fram                         : 3;  /**< Frame offset                                       |           NS
                                                          NOTE: this is used to extract the correct byte from
                                                          each 64b word read from the transmit memory region */
 #else
@@ -862,20 +914,20 @@ union cvmx_pcmx_txaddr
 	struct cvmx_pcmx_txaddr_s             cn30xx;
 	struct cvmx_pcmx_txaddr_s             cn31xx;
 	struct cvmx_pcmx_txaddr_s             cn50xx;
+	struct cvmx_pcmx_txaddr_s             cn61xx;
+	struct cvmx_pcmx_txaddr_s             cnf71xx;
 };
 typedef union cvmx_pcmx_txaddr cvmx_pcmx_txaddr_t;
 
 /**
  * cvmx_pcm#_txcnt
  */
-union cvmx_pcmx_txcnt
-{
+union cvmx_pcmx_txcnt {
 	uint64_t u64;
-	struct cvmx_pcmx_txcnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcmx_txcnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
-	uint64_t cnt                          : 16; /**< Number of superframes in transmit memory region */
+	uint64_t cnt                          : 16; /**< Number of superframes in transmit memory region    |          NS */
 #else
 	uint64_t cnt                          : 16;
 	uint64_t reserved_16_63               : 48;
@@ -884,19 +936,19 @@ union cvmx_pcmx_txcnt
 	struct cvmx_pcmx_txcnt_s              cn30xx;
 	struct cvmx_pcmx_txcnt_s              cn31xx;
 	struct cvmx_pcmx_txcnt_s              cn50xx;
+	struct cvmx_pcmx_txcnt_s              cn61xx;
+	struct cvmx_pcmx_txcnt_s              cnf71xx;
 };
 typedef union cvmx_pcmx_txcnt cvmx_pcmx_txcnt_t;
 
 /**
  * cvmx_pcm#_txmsk0
  */
-union cvmx_pcmx_txmsk0
-{
+union cvmx_pcmx_txmsk0 {
 	uint64_t u64;
-	struct cvmx_pcmx_txmsk0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t mask                         : 64; /**< Transmit mask bits for slots 63 to 0
+	struct cvmx_pcmx_txmsk0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mask                         : 64; /**< Transmit mask bits for slots 63 to 0               |          NS
                                                          (1 means transmit, 0 means don't transmit) */
 #else
 	uint64_t mask                         : 64;
@@ -905,19 +957,19 @@ union cvmx_pcmx_txmsk0
 	struct cvmx_pcmx_txmsk0_s             cn30xx;
 	struct cvmx_pcmx_txmsk0_s             cn31xx;
 	struct cvmx_pcmx_txmsk0_s             cn50xx;
+	struct cvmx_pcmx_txmsk0_s             cn61xx;
+	struct cvmx_pcmx_txmsk0_s             cnf71xx;
 };
 typedef union cvmx_pcmx_txmsk0 cvmx_pcmx_txmsk0_t;
 
 /**
  * cvmx_pcm#_txmsk1
  */
-union cvmx_pcmx_txmsk1
-{
+union cvmx_pcmx_txmsk1 {
 	uint64_t u64;
-	struct cvmx_pcmx_txmsk1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t mask                         : 64; /**< Transmit mask bits for slots 127 to 64
+	struct cvmx_pcmx_txmsk1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mask                         : 64; /**< Transmit mask bits for slots 127 to 64             |          NS
                                                          (1 means transmit, 0 means don't transmit) */
 #else
 	uint64_t mask                         : 64;
@@ -926,19 +978,19 @@ union cvmx_pcmx_txmsk1
 	struct cvmx_pcmx_txmsk1_s             cn30xx;
 	struct cvmx_pcmx_txmsk1_s             cn31xx;
 	struct cvmx_pcmx_txmsk1_s             cn50xx;
+	struct cvmx_pcmx_txmsk1_s             cn61xx;
+	struct cvmx_pcmx_txmsk1_s             cnf71xx;
 };
 typedef union cvmx_pcmx_txmsk1 cvmx_pcmx_txmsk1_t;
 
 /**
  * cvmx_pcm#_txmsk2
  */
-union cvmx_pcmx_txmsk2
-{
+union cvmx_pcmx_txmsk2 {
 	uint64_t u64;
-	struct cvmx_pcmx_txmsk2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t mask                         : 64; /**< Transmit mask bits for slots 191 to 128
+	struct cvmx_pcmx_txmsk2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mask                         : 64; /**< Transmit mask bits for slots 191 to 128            |          NS
                                                          (1 means transmit, 0 means don't transmit) */
 #else
 	uint64_t mask                         : 64;
@@ -947,19 +999,19 @@ union cvmx_pcmx_txmsk2
 	struct cvmx_pcmx_txmsk2_s             cn30xx;
 	struct cvmx_pcmx_txmsk2_s             cn31xx;
 	struct cvmx_pcmx_txmsk2_s             cn50xx;
+	struct cvmx_pcmx_txmsk2_s             cn61xx;
+	struct cvmx_pcmx_txmsk2_s             cnf71xx;
 };
 typedef union cvmx_pcmx_txmsk2 cvmx_pcmx_txmsk2_t;
 
 /**
  * cvmx_pcm#_txmsk3
  */
-union cvmx_pcmx_txmsk3
-{
+union cvmx_pcmx_txmsk3 {
 	uint64_t u64;
-	struct cvmx_pcmx_txmsk3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t mask                         : 64; /**< Transmit mask bits for slots 255 to 192
+	struct cvmx_pcmx_txmsk3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mask                         : 64; /**< Transmit mask bits for slots 255 to 192            |          NS
                                                          (1 means transmit, 0 means don't transmit) */
 #else
 	uint64_t mask                         : 64;
@@ -968,19 +1020,19 @@ union cvmx_pcmx_txmsk3
 	struct cvmx_pcmx_txmsk3_s             cn30xx;
 	struct cvmx_pcmx_txmsk3_s             cn31xx;
 	struct cvmx_pcmx_txmsk3_s             cn50xx;
+	struct cvmx_pcmx_txmsk3_s             cn61xx;
+	struct cvmx_pcmx_txmsk3_s             cnf71xx;
 };
 typedef union cvmx_pcmx_txmsk3 cvmx_pcmx_txmsk3_t;
 
 /**
  * cvmx_pcm#_txmsk4
  */
-union cvmx_pcmx_txmsk4
-{
+union cvmx_pcmx_txmsk4 {
 	uint64_t u64;
-	struct cvmx_pcmx_txmsk4_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t mask                         : 64; /**< Transmit mask bits for slots 319 to 256
+	struct cvmx_pcmx_txmsk4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mask                         : 64; /**< Transmit mask bits for slots 319 to 256            |          NS
                                                          (1 means transmit, 0 means don't transmit) */
 #else
 	uint64_t mask                         : 64;
@@ -989,19 +1041,19 @@ union cvmx_pcmx_txmsk4
 	struct cvmx_pcmx_txmsk4_s             cn30xx;
 	struct cvmx_pcmx_txmsk4_s             cn31xx;
 	struct cvmx_pcmx_txmsk4_s             cn50xx;
+	struct cvmx_pcmx_txmsk4_s             cn61xx;
+	struct cvmx_pcmx_txmsk4_s             cnf71xx;
 };
 typedef union cvmx_pcmx_txmsk4 cvmx_pcmx_txmsk4_t;
 
 /**
  * cvmx_pcm#_txmsk5
  */
-union cvmx_pcmx_txmsk5
-{
+union cvmx_pcmx_txmsk5 {
 	uint64_t u64;
-	struct cvmx_pcmx_txmsk5_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t mask                         : 64; /**< Transmit mask bits for slots 383 to 320
+	struct cvmx_pcmx_txmsk5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mask                         : 64; /**< Transmit mask bits for slots 383 to 320            |          NS
                                                          (1 means transmit, 0 means don't transmit) */
 #else
 	uint64_t mask                         : 64;
@@ -1010,19 +1062,19 @@ union cvmx_pcmx_txmsk5
 	struct cvmx_pcmx_txmsk5_s             cn30xx;
 	struct cvmx_pcmx_txmsk5_s             cn31xx;
 	struct cvmx_pcmx_txmsk5_s             cn50xx;
+	struct cvmx_pcmx_txmsk5_s             cn61xx;
+	struct cvmx_pcmx_txmsk5_s             cnf71xx;
 };
 typedef union cvmx_pcmx_txmsk5 cvmx_pcmx_txmsk5_t;
 
 /**
  * cvmx_pcm#_txmsk6
  */
-union cvmx_pcmx_txmsk6
-{
+union cvmx_pcmx_txmsk6 {
 	uint64_t u64;
-	struct cvmx_pcmx_txmsk6_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t mask                         : 64; /**< Transmit mask bits for slots 447 to 384
+	struct cvmx_pcmx_txmsk6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mask                         : 64; /**< Transmit mask bits for slots 447 to 384            |          NS
                                                          (1 means transmit, 0 means don't transmit) */
 #else
 	uint64_t mask                         : 64;
@@ -1031,19 +1083,19 @@ union cvmx_pcmx_txmsk6
 	struct cvmx_pcmx_txmsk6_s             cn30xx;
 	struct cvmx_pcmx_txmsk6_s             cn31xx;
 	struct cvmx_pcmx_txmsk6_s             cn50xx;
+	struct cvmx_pcmx_txmsk6_s             cn61xx;
+	struct cvmx_pcmx_txmsk6_s             cnf71xx;
 };
 typedef union cvmx_pcmx_txmsk6 cvmx_pcmx_txmsk6_t;
 
 /**
  * cvmx_pcm#_txmsk7
  */
-union cvmx_pcmx_txmsk7
-{
+union cvmx_pcmx_txmsk7 {
 	uint64_t u64;
-	struct cvmx_pcmx_txmsk7_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t mask                         : 64; /**< Transmit mask bits for slots 511 to 448
+	struct cvmx_pcmx_txmsk7_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mask                         : 64; /**< Transmit mask bits for slots 511 to 448            |          NS
                                                          (1 means transmit, 0 means don't transmit) */
 #else
 	uint64_t mask                         : 64;
@@ -1052,20 +1104,20 @@ union cvmx_pcmx_txmsk7
 	struct cvmx_pcmx_txmsk7_s             cn30xx;
 	struct cvmx_pcmx_txmsk7_s             cn31xx;
 	struct cvmx_pcmx_txmsk7_s             cn50xx;
+	struct cvmx_pcmx_txmsk7_s             cn61xx;
+	struct cvmx_pcmx_txmsk7_s             cnf71xx;
 };
 typedef union cvmx_pcmx_txmsk7 cvmx_pcmx_txmsk7_t;
 
 /**
  * cvmx_pcm#_txstart
  */
-union cvmx_pcmx_txstart
-{
+union cvmx_pcmx_txstart {
 	uint64_t u64;
-	struct cvmx_pcmx_txstart_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcmx_txstart_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 33; /**< Starting address for the transmit memory region */
+	uint64_t addr                         : 33; /**< Starting address for the transmit memory region    |          NS */
 	uint64_t reserved_0_2                 : 3;
 #else
 	uint64_t reserved_0_2                 : 3;
@@ -1076,6 +1128,8 @@ union cvmx_pcmx_txstart
 	struct cvmx_pcmx_txstart_s            cn30xx;
 	struct cvmx_pcmx_txstart_s            cn31xx;
 	struct cvmx_pcmx_txstart_s            cn50xx;
+	struct cvmx_pcmx_txstart_s            cn61xx;
+	struct cvmx_pcmx_txstart_s            cnf71xx;
 };
 typedef union cvmx_pcmx_txstart cvmx_pcmx_txstart_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-pcsx-defs.h b/sys/contrib/octeon-sdk/cvmx-pcsx-defs.h
index 53bd30c..64ebe00 100644
--- a/sys/contrib/octeon-sdk/cvmx-pcsx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-pcsx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,230 +49,451 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_PCSX_TYPEDEFS_H__
-#define __CVMX_PCSX_TYPEDEFS_H__
+#ifndef __CVMX_PCSX_DEFS_H__
+#define __CVMX_PCSX_DEFS_H__
 
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_PCSX_ANX_ADV_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
+			break;
+	}
+	cvmx_warn("CVMX_PCSX_ANX_ADV_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
 }
-#else
-#define CVMX_PCSX_ANX_ADV_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_PCSX_ANX_EXT_ST_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
+			break;
+	}
+	cvmx_warn("CVMX_PCSX_ANX_EXT_ST_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
 }
-#else
-#define CVMX_PCSX_ANX_EXT_ST_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_PCSX_ANX_LP_ABIL_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
+			break;
+	}
+	cvmx_warn("CVMX_PCSX_ANX_LP_ABIL_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
 }
-#else
-#define CVMX_PCSX_ANX_LP_ABIL_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_PCSX_ANX_RESULTS_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
+			break;
+	}
+	cvmx_warn("CVMX_PCSX_ANX_RESULTS_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
 }
-#else
-#define CVMX_PCSX_ANX_RESULTS_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_PCSX_INTX_EN_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
+			break;
+	}
+	cvmx_warn("CVMX_PCSX_INTX_EN_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
 }
-#else
-#define CVMX_PCSX_INTX_EN_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_PCSX_INTX_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
+			break;
+	}
+	cvmx_warn("CVMX_PCSX_INTX_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
 }
-#else
-#define CVMX_PCSX_INTX_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_PCSX_LINKX_TIMER_COUNT_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
+			break;
+	}
+	cvmx_warn("CVMX_PCSX_LINKX_TIMER_COUNT_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
 }
-#else
-#define CVMX_PCSX_LINKX_TIMER_COUNT_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_PCSX_LOG_ANLX_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
+			break;
+	}
+	cvmx_warn("CVMX_PCSX_LOG_ANLX_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
 }
-#else
-#define CVMX_PCSX_LOG_ANLX_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_PCSX_MISCX_CTL_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
+			break;
+	}
+	cvmx_warn("CVMX_PCSX_MISCX_CTL_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
 }
-#else
-#define CVMX_PCSX_MISCX_CTL_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_PCSX_MRX_CONTROL_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
+			break;
+	}
+	cvmx_warn("CVMX_PCSX_MRX_CONTROL_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
 }
-#else
-#define CVMX_PCSX_MRX_CONTROL_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_PCSX_MRX_STATUS_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
+			break;
+	}
+	cvmx_warn("CVMX_PCSX_MRX_STATUS_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
 }
-#else
-#define CVMX_PCSX_MRX_STATUS_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_PCSX_RXX_STATES_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
+			break;
+	}
+	cvmx_warn("CVMX_PCSX_RXX_STATES_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
 }
-#else
-#define CVMX_PCSX_RXX_STATES_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_PCSX_RXX_SYNC_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
+			break;
+	}
+	cvmx_warn("CVMX_PCSX_RXX_SYNC_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
 }
-#else
-#define CVMX_PCSX_RXX_SYNC_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_PCSX_SGMX_AN_ADV_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
+			break;
+	}
+	cvmx_warn("CVMX_PCSX_SGMX_AN_ADV_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
 }
-#else
-#define CVMX_PCSX_SGMX_AN_ADV_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_PCSX_SGMX_LP_ADV_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
+			break;
+	}
+	cvmx_warn("CVMX_PCSX_SGMX_LP_ADV_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
 }
-#else
-#define CVMX_PCSX_SGMX_LP_ADV_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_PCSX_TXX_STATES_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
+			break;
+	}
+	cvmx_warn("CVMX_PCSX_TXX_STATES_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
 }
-#else
-#define CVMX_PCSX_TXX_STATES_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
-		cvmx_warn("CVMX_PCSX_TX_RXX_POLARITY_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 1)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id == 0)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 1)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if (((offset <= 3)) && ((block_id <= 4)))
+				return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
+			break;
+	}
+	cvmx_warn("CVMX_PCSX_TX_RXX_POLARITY_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
 }
-#else
-#define CVMX_PCSX_TX_RXX_POLARITY_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
-#endif
 
 /**
  * cvmx_pcs#_an#_adv_reg
@@ -287,12 +508,10 @@ static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsig
  *
  * PCS_AN_ADV_REG = AN Advertisement Register4
  */
-union cvmx_pcsx_anx_adv_reg
-{
+union cvmx_pcsx_anx_adv_reg {
 	uint64_t u64;
-	struct cvmx_pcsx_anx_adv_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_anx_adv_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t np                           : 1;  /**< Always 0, no next page capability supported */
 	uint64_t reserved_14_14               : 1;
@@ -329,8 +548,13 @@ union cvmx_pcsx_anx_adv_reg
 	struct cvmx_pcsx_anx_adv_reg_s        cn52xxp1;
 	struct cvmx_pcsx_anx_adv_reg_s        cn56xx;
 	struct cvmx_pcsx_anx_adv_reg_s        cn56xxp1;
+	struct cvmx_pcsx_anx_adv_reg_s        cn61xx;
 	struct cvmx_pcsx_anx_adv_reg_s        cn63xx;
 	struct cvmx_pcsx_anx_adv_reg_s        cn63xxp1;
+	struct cvmx_pcsx_anx_adv_reg_s        cn66xx;
+	struct cvmx_pcsx_anx_adv_reg_s        cn68xx;
+	struct cvmx_pcsx_anx_adv_reg_s        cn68xxp1;
+	struct cvmx_pcsx_anx_adv_reg_s        cnf71xx;
 };
 typedef union cvmx_pcsx_anx_adv_reg cvmx_pcsx_anx_adv_reg_t;
 
@@ -345,12 +569,10 @@ typedef union cvmx_pcsx_anx_adv_reg cvmx_pcsx_anx_adv_reg_t;
  * PCS_AN_EXT_ST_REG = AN Extended Status Register15
  * as per IEEE802.3 Clause 22
  */
-union cvmx_pcsx_anx_ext_st_reg
-{
+union cvmx_pcsx_anx_ext_st_reg {
 	uint64_t u64;
-	struct cvmx_pcsx_anx_ext_st_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_anx_ext_st_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t thou_xfd                     : 1;  /**< 1 means PHY is 1000BASE-X Full Dup capable */
 	uint64_t thou_xhd                     : 1;  /**< 1 means PHY is 1000BASE-X Half Dup capable */
@@ -370,8 +592,13 @@ union cvmx_pcsx_anx_ext_st_reg
 	struct cvmx_pcsx_anx_ext_st_reg_s     cn52xxp1;
 	struct cvmx_pcsx_anx_ext_st_reg_s     cn56xx;
 	struct cvmx_pcsx_anx_ext_st_reg_s     cn56xxp1;
+	struct cvmx_pcsx_anx_ext_st_reg_s     cn61xx;
 	struct cvmx_pcsx_anx_ext_st_reg_s     cn63xx;
 	struct cvmx_pcsx_anx_ext_st_reg_s     cn63xxp1;
+	struct cvmx_pcsx_anx_ext_st_reg_s     cn66xx;
+	struct cvmx_pcsx_anx_ext_st_reg_s     cn68xx;
+	struct cvmx_pcsx_anx_ext_st_reg_s     cn68xxp1;
+	struct cvmx_pcsx_anx_ext_st_reg_s     cnf71xx;
 };
 typedef union cvmx_pcsx_anx_ext_st_reg cvmx_pcsx_anx_ext_st_reg_t;
 
@@ -381,12 +608,10 @@ typedef union cvmx_pcsx_anx_ext_st_reg cvmx_pcsx_anx_ext_st_reg_t;
  * PCS_AN_LP_ABIL_REG = AN link Partner Ability Register5
  * as per IEEE802.3 Clause 37
  */
-union cvmx_pcsx_anx_lp_abil_reg
-{
+union cvmx_pcsx_anx_lp_abil_reg {
 	uint64_t u64;
-	struct cvmx_pcsx_anx_lp_abil_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_anx_lp_abil_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t np                           : 1;  /**< 1=lp next page capable, 0=lp not next page capable */
 	uint64_t ack                          : 1;  /**< 1=Acknowledgement received */
@@ -420,8 +645,13 @@ union cvmx_pcsx_anx_lp_abil_reg
 	struct cvmx_pcsx_anx_lp_abil_reg_s    cn52xxp1;
 	struct cvmx_pcsx_anx_lp_abil_reg_s    cn56xx;
 	struct cvmx_pcsx_anx_lp_abil_reg_s    cn56xxp1;
+	struct cvmx_pcsx_anx_lp_abil_reg_s    cn61xx;
 	struct cvmx_pcsx_anx_lp_abil_reg_s    cn63xx;
 	struct cvmx_pcsx_anx_lp_abil_reg_s    cn63xxp1;
+	struct cvmx_pcsx_anx_lp_abil_reg_s    cn66xx;
+	struct cvmx_pcsx_anx_lp_abil_reg_s    cn68xx;
+	struct cvmx_pcsx_anx_lp_abil_reg_s    cn68xxp1;
+	struct cvmx_pcsx_anx_lp_abil_reg_s    cnf71xx;
 };
 typedef union cvmx_pcsx_anx_lp_abil_reg cvmx_pcsx_anx_lp_abil_reg_t;
 
@@ -431,12 +661,10 @@ typedef union cvmx_pcsx_anx_lp_abil_reg cvmx_pcsx_anx_lp_abil_reg_t;
  * PCS_AN_RESULTS_REG = AN Results Register
  *
  */
-union cvmx_pcsx_anx_results_reg
-{
+union cvmx_pcsx_anx_results_reg {
 	uint64_t u64;
-	struct cvmx_pcsx_anx_results_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_anx_results_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t pause                        : 2;  /**< [<6>, <5>] PAUSE Selection (Don't care for SGMII)
                                                          0    0  Disable Pause, TX and RX
@@ -464,8 +692,13 @@ union cvmx_pcsx_anx_results_reg
 	struct cvmx_pcsx_anx_results_reg_s    cn52xxp1;
 	struct cvmx_pcsx_anx_results_reg_s    cn56xx;
 	struct cvmx_pcsx_anx_results_reg_s    cn56xxp1;
+	struct cvmx_pcsx_anx_results_reg_s    cn61xx;
 	struct cvmx_pcsx_anx_results_reg_s    cn63xx;
 	struct cvmx_pcsx_anx_results_reg_s    cn63xxp1;
+	struct cvmx_pcsx_anx_results_reg_s    cn66xx;
+	struct cvmx_pcsx_anx_results_reg_s    cn68xx;
+	struct cvmx_pcsx_anx_results_reg_s    cn68xxp1;
+	struct cvmx_pcsx_anx_results_reg_s    cnf71xx;
 };
 typedef union cvmx_pcsx_anx_results_reg cvmx_pcsx_anx_results_reg_t;
 
@@ -481,12 +714,10 @@ typedef union cvmx_pcsx_anx_results_reg cvmx_pcsx_anx_results_reg_t;
  *
  * PCS Interrupt Enable Register
  */
-union cvmx_pcsx_intx_en_reg
-{
+union cvmx_pcsx_intx_en_reg {
 	uint64_t u64;
-	struct cvmx_pcsx_intx_en_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_intx_en_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t dbg_sync_en                  : 1;  /**< Code Group sync failure debug help */
 	uint64_t dup                          : 1;  /**< Enable duplex mode changed interrupt */
@@ -518,9 +749,8 @@ union cvmx_pcsx_intx_en_reg
 	uint64_t reserved_13_63               : 51;
 #endif
 	} s;
-	struct cvmx_pcsx_intx_en_reg_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_intx_en_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t dup                          : 1;  /**< Enable duplex mode changed interrupt */
 	uint64_t sync_bad_en                  : 1;  /**< Enable rx sync st machine in bad state interrupt */
@@ -553,8 +783,13 @@ union cvmx_pcsx_intx_en_reg
 	struct cvmx_pcsx_intx_en_reg_cn52xx   cn52xxp1;
 	struct cvmx_pcsx_intx_en_reg_cn52xx   cn56xx;
 	struct cvmx_pcsx_intx_en_reg_cn52xx   cn56xxp1;
+	struct cvmx_pcsx_intx_en_reg_s        cn61xx;
 	struct cvmx_pcsx_intx_en_reg_s        cn63xx;
 	struct cvmx_pcsx_intx_en_reg_s        cn63xxp1;
+	struct cvmx_pcsx_intx_en_reg_s        cn66xx;
+	struct cvmx_pcsx_intx_en_reg_s        cn68xx;
+	struct cvmx_pcsx_intx_en_reg_s        cn68xxp1;
+	struct cvmx_pcsx_intx_en_reg_s        cnf71xx;
 };
 typedef union cvmx_pcsx_intx_en_reg cvmx_pcsx_intx_en_reg_t;
 
@@ -573,12 +808,10 @@ typedef union cvmx_pcsx_intx_en_reg cvmx_pcsx_intx_en_reg_t;
  *
  * PCS Interrupt Register
  */
-union cvmx_pcsx_intx_reg
-{
+union cvmx_pcsx_intx_reg {
 	uint64_t u64;
-	struct cvmx_pcsx_intx_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_intx_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t dbg_sync                     : 1;  /**< Code Group sync failure debug help */
 	uint64_t dup                          : 1;  /**< Set whenever Duplex mode changes on the link */
@@ -622,9 +855,8 @@ union cvmx_pcsx_intx_reg
 	uint64_t reserved_13_63               : 51;
 #endif
 	} s;
-	struct cvmx_pcsx_intx_reg_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_intx_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t dup                          : 1;  /**< Set whenever Duplex mode changes on the link */
 	uint64_t sync_bad                     : 1;  /**< Set by HW whenever rx sync st machine reaches a bad
@@ -669,8 +901,13 @@ union cvmx_pcsx_intx_reg
 	struct cvmx_pcsx_intx_reg_cn52xx      cn52xxp1;
 	struct cvmx_pcsx_intx_reg_cn52xx      cn56xx;
 	struct cvmx_pcsx_intx_reg_cn52xx      cn56xxp1;
+	struct cvmx_pcsx_intx_reg_s           cn61xx;
 	struct cvmx_pcsx_intx_reg_s           cn63xx;
 	struct cvmx_pcsx_intx_reg_s           cn63xxp1;
+	struct cvmx_pcsx_intx_reg_s           cn66xx;
+	struct cvmx_pcsx_intx_reg_s           cn68xx;
+	struct cvmx_pcsx_intx_reg_s           cn68xxp1;
+	struct cvmx_pcsx_intx_reg_s           cnf71xx;
 };
 typedef union cvmx_pcsx_intx_reg cvmx_pcsx_intx_reg_t;
 
@@ -680,12 +917,10 @@ typedef union cvmx_pcsx_intx_reg cvmx_pcsx_intx_reg_t;
  * PCS_LINK_TIMER_COUNT_REG = 1.6ms nominal link timer register
  *
  */
-union cvmx_pcsx_linkx_timer_count_reg
-{
+union cvmx_pcsx_linkx_timer_count_reg {
 	uint64_t u64;
-	struct cvmx_pcsx_linkx_timer_count_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_linkx_timer_count_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t count                        : 16; /**< (core clock period times 1024) times "COUNT" should
                                                          be 1.6ms(SGMII)/10ms(otherwise) which is the link
@@ -700,8 +935,13 @@ union cvmx_pcsx_linkx_timer_count_reg
 	struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1;
 	struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx;
 	struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1;
+	struct cvmx_pcsx_linkx_timer_count_reg_s cn61xx;
 	struct cvmx_pcsx_linkx_timer_count_reg_s cn63xx;
 	struct cvmx_pcsx_linkx_timer_count_reg_s cn63xxp1;
+	struct cvmx_pcsx_linkx_timer_count_reg_s cn66xx;
+	struct cvmx_pcsx_linkx_timer_count_reg_s cn68xx;
+	struct cvmx_pcsx_linkx_timer_count_reg_s cn68xxp1;
+	struct cvmx_pcsx_linkx_timer_count_reg_s cnf71xx;
 };
 typedef union cvmx_pcsx_linkx_timer_count_reg cvmx_pcsx_linkx_timer_count_reg_t;
 
@@ -711,12 +951,10 @@ typedef union cvmx_pcsx_linkx_timer_count_reg cvmx_pcsx_linkx_timer_count_reg_t;
  * PCS Logic Analyzer Register
  *
  */
-union cvmx_pcsx_log_anlx_reg
-{
+union cvmx_pcsx_log_anlx_reg {
 	uint64_t u64;
-	struct cvmx_pcsx_log_anlx_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_log_anlx_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t lafifovfl                    : 1;  /**< 1=logic analyser fif overflowed during packetization
                                                          Write 1 to clear this bit */
@@ -737,8 +975,13 @@ union cvmx_pcsx_log_anlx_reg
 	struct cvmx_pcsx_log_anlx_reg_s       cn52xxp1;
 	struct cvmx_pcsx_log_anlx_reg_s       cn56xx;
 	struct cvmx_pcsx_log_anlx_reg_s       cn56xxp1;
+	struct cvmx_pcsx_log_anlx_reg_s       cn61xx;
 	struct cvmx_pcsx_log_anlx_reg_s       cn63xx;
 	struct cvmx_pcsx_log_anlx_reg_s       cn63xxp1;
+	struct cvmx_pcsx_log_anlx_reg_s       cn66xx;
+	struct cvmx_pcsx_log_anlx_reg_s       cn68xx;
+	struct cvmx_pcsx_log_anlx_reg_s       cn68xxp1;
+	struct cvmx_pcsx_log_anlx_reg_s       cnf71xx;
 };
 typedef union cvmx_pcsx_log_anlx_reg cvmx_pcsx_log_anlx_reg_t;
 
@@ -748,12 +991,10 @@ typedef union cvmx_pcsx_log_anlx_reg cvmx_pcsx_log_anlx_reg_t;
  * SGMII Misc Control Register
  *
  */
-union cvmx_pcsx_miscx_ctl_reg
-{
+union cvmx_pcsx_miscx_ctl_reg {
 	uint64_t u64;
-	struct cvmx_pcsx_miscx_ctl_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_miscx_ctl_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t sgmii                        : 1;  /**< 1=SGMII or 1000Base-X mode selected,
                                                          0=XAUI or PCIE mode selected
@@ -798,8 +1039,13 @@ union cvmx_pcsx_miscx_ctl_reg
 	struct cvmx_pcsx_miscx_ctl_reg_s      cn52xxp1;
 	struct cvmx_pcsx_miscx_ctl_reg_s      cn56xx;
 	struct cvmx_pcsx_miscx_ctl_reg_s      cn56xxp1;
+	struct cvmx_pcsx_miscx_ctl_reg_s      cn61xx;
 	struct cvmx_pcsx_miscx_ctl_reg_s      cn63xx;
 	struct cvmx_pcsx_miscx_ctl_reg_s      cn63xxp1;
+	struct cvmx_pcsx_miscx_ctl_reg_s      cn66xx;
+	struct cvmx_pcsx_miscx_ctl_reg_s      cn68xx;
+	struct cvmx_pcsx_miscx_ctl_reg_s      cn68xxp1;
+	struct cvmx_pcsx_miscx_ctl_reg_s      cnf71xx;
 };
 typedef union cvmx_pcsx_miscx_ctl_reg cvmx_pcsx_miscx_ctl_reg_t;
 
@@ -809,12 +1055,10 @@ typedef union cvmx_pcsx_miscx_ctl_reg cvmx_pcsx_miscx_ctl_reg_t;
  * PCS_MR_CONTROL_REG = Control Register0
  *
  */
-union cvmx_pcsx_mrx_control_reg
-{
+union cvmx_pcsx_mrx_control_reg {
 	uint64_t u64;
-	struct cvmx_pcsx_mrx_control_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_mrx_control_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t reset                        : 1;  /**< 1=SW Reset, the bit will return to 0 after pcs has
                                                          been reset. Takes 32 eclk cycles to reset pcs */
@@ -869,8 +1113,13 @@ union cvmx_pcsx_mrx_control_reg
 	struct cvmx_pcsx_mrx_control_reg_s    cn52xxp1;
 	struct cvmx_pcsx_mrx_control_reg_s    cn56xx;
 	struct cvmx_pcsx_mrx_control_reg_s    cn56xxp1;
+	struct cvmx_pcsx_mrx_control_reg_s    cn61xx;
 	struct cvmx_pcsx_mrx_control_reg_s    cn63xx;
 	struct cvmx_pcsx_mrx_control_reg_s    cn63xxp1;
+	struct cvmx_pcsx_mrx_control_reg_s    cn66xx;
+	struct cvmx_pcsx_mrx_control_reg_s    cn68xx;
+	struct cvmx_pcsx_mrx_control_reg_s    cn68xxp1;
+	struct cvmx_pcsx_mrx_control_reg_s    cnf71xx;
 };
 typedef union cvmx_pcsx_mrx_control_reg cvmx_pcsx_mrx_control_reg_t;
 
@@ -885,12 +1134,10 @@ typedef union cvmx_pcsx_mrx_control_reg cvmx_pcsx_mrx_control_reg_t;
  *
  *  PCS_MR_STATUS_REG = Status Register1
  */
-union cvmx_pcsx_mrx_status_reg
-{
+union cvmx_pcsx_mrx_status_reg {
 	uint64_t u64;
-	struct cvmx_pcsx_mrx_status_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_mrx_status_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t hun_t4                       : 1;  /**< 1 means 100Base-T4 capable */
 	uint64_t hun_xfd                      : 1;  /**< 1 means 100Base-X Full Duplex */
@@ -942,8 +1189,13 @@ union cvmx_pcsx_mrx_status_reg
 	struct cvmx_pcsx_mrx_status_reg_s     cn52xxp1;
 	struct cvmx_pcsx_mrx_status_reg_s     cn56xx;
 	struct cvmx_pcsx_mrx_status_reg_s     cn56xxp1;
+	struct cvmx_pcsx_mrx_status_reg_s     cn61xx;
 	struct cvmx_pcsx_mrx_status_reg_s     cn63xx;
 	struct cvmx_pcsx_mrx_status_reg_s     cn63xxp1;
+	struct cvmx_pcsx_mrx_status_reg_s     cn66xx;
+	struct cvmx_pcsx_mrx_status_reg_s     cn68xx;
+	struct cvmx_pcsx_mrx_status_reg_s     cn68xxp1;
+	struct cvmx_pcsx_mrx_status_reg_s     cnf71xx;
 };
 typedef union cvmx_pcsx_mrx_status_reg cvmx_pcsx_mrx_status_reg_t;
 
@@ -953,12 +1205,10 @@ typedef union cvmx_pcsx_mrx_status_reg cvmx_pcsx_mrx_status_reg_t;
  * PCS_RX_STATES_REG = RX State Machines states register
  *
  */
-union cvmx_pcsx_rxx_states_reg
-{
+union cvmx_pcsx_rxx_states_reg {
 	uint64_t u64;
-	struct cvmx_pcsx_rxx_states_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_rxx_states_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t rx_bad                       : 1;  /**< Receive state machine in an illegal state */
 	uint64_t rx_st                        : 5;  /**< Receive state machine state */
@@ -980,8 +1230,13 @@ union cvmx_pcsx_rxx_states_reg
 	struct cvmx_pcsx_rxx_states_reg_s     cn52xxp1;
 	struct cvmx_pcsx_rxx_states_reg_s     cn56xx;
 	struct cvmx_pcsx_rxx_states_reg_s     cn56xxp1;
+	struct cvmx_pcsx_rxx_states_reg_s     cn61xx;
 	struct cvmx_pcsx_rxx_states_reg_s     cn63xx;
 	struct cvmx_pcsx_rxx_states_reg_s     cn63xxp1;
+	struct cvmx_pcsx_rxx_states_reg_s     cn66xx;
+	struct cvmx_pcsx_rxx_states_reg_s     cn68xx;
+	struct cvmx_pcsx_rxx_states_reg_s     cn68xxp1;
+	struct cvmx_pcsx_rxx_states_reg_s     cnf71xx;
 };
 typedef union cvmx_pcsx_rxx_states_reg cvmx_pcsx_rxx_states_reg_t;
 
@@ -994,12 +1249,10 @@ typedef union cvmx_pcsx_rxx_states_reg cvmx_pcsx_rxx_states_reg_t;
  *
  *  PCS_RX_SYNC_REG = Code Group synchronization reg
  */
-union cvmx_pcsx_rxx_sync_reg
-{
+union cvmx_pcsx_rxx_sync_reg {
 	uint64_t u64;
-	struct cvmx_pcsx_rxx_sync_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_rxx_sync_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t sync                         : 1;  /**< 1 means code group synchronization achieved */
 	uint64_t bit_lock                     : 1;  /**< 1 means bit lock achieved */
@@ -1013,8 +1266,13 @@ union cvmx_pcsx_rxx_sync_reg
 	struct cvmx_pcsx_rxx_sync_reg_s       cn52xxp1;
 	struct cvmx_pcsx_rxx_sync_reg_s       cn56xx;
 	struct cvmx_pcsx_rxx_sync_reg_s       cn56xxp1;
+	struct cvmx_pcsx_rxx_sync_reg_s       cn61xx;
 	struct cvmx_pcsx_rxx_sync_reg_s       cn63xx;
 	struct cvmx_pcsx_rxx_sync_reg_s       cn63xxp1;
+	struct cvmx_pcsx_rxx_sync_reg_s       cn66xx;
+	struct cvmx_pcsx_rxx_sync_reg_s       cn68xx;
+	struct cvmx_pcsx_rxx_sync_reg_s       cn68xxp1;
+	struct cvmx_pcsx_rxx_sync_reg_s       cnf71xx;
 };
 typedef union cvmx_pcsx_rxx_sync_reg cvmx_pcsx_rxx_sync_reg_t;
 
@@ -1024,12 +1282,10 @@ typedef union cvmx_pcsx_rxx_sync_reg cvmx_pcsx_rxx_sync_reg_t;
  * SGMII AN Advertisement Register (sent out as tx_config_reg)
  *
  */
-union cvmx_pcsx_sgmx_an_adv_reg
-{
+union cvmx_pcsx_sgmx_an_adv_reg {
 	uint64_t u64;
-	struct cvmx_pcsx_sgmx_an_adv_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_sgmx_an_adv_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t link                         : 1;  /**< Link status 1 Link Up, 0 Link Down */
 	uint64_t ack                          : 1;  /**< Auto negotiation ack */
@@ -1057,8 +1313,13 @@ union cvmx_pcsx_sgmx_an_adv_reg
 	struct cvmx_pcsx_sgmx_an_adv_reg_s    cn52xxp1;
 	struct cvmx_pcsx_sgmx_an_adv_reg_s    cn56xx;
 	struct cvmx_pcsx_sgmx_an_adv_reg_s    cn56xxp1;
+	struct cvmx_pcsx_sgmx_an_adv_reg_s    cn61xx;
 	struct cvmx_pcsx_sgmx_an_adv_reg_s    cn63xx;
 	struct cvmx_pcsx_sgmx_an_adv_reg_s    cn63xxp1;
+	struct cvmx_pcsx_sgmx_an_adv_reg_s    cn66xx;
+	struct cvmx_pcsx_sgmx_an_adv_reg_s    cn68xx;
+	struct cvmx_pcsx_sgmx_an_adv_reg_s    cn68xxp1;
+	struct cvmx_pcsx_sgmx_an_adv_reg_s    cnf71xx;
 };
 typedef union cvmx_pcsx_sgmx_an_adv_reg cvmx_pcsx_sgmx_an_adv_reg_t;
 
@@ -1071,12 +1332,10 @@ typedef union cvmx_pcsx_sgmx_an_adv_reg cvmx_pcsx_sgmx_an_adv_reg_t;
  *
  * SGMII LP Advertisement Register (received as rx_config_reg)
  */
-union cvmx_pcsx_sgmx_lp_adv_reg
-{
+union cvmx_pcsx_sgmx_lp_adv_reg {
 	uint64_t u64;
-	struct cvmx_pcsx_sgmx_lp_adv_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_sgmx_lp_adv_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t link                         : 1;  /**< Link status 1 Link Up, 0 Link Down */
 	uint64_t reserved_13_14               : 2;
@@ -1102,8 +1361,13 @@ union cvmx_pcsx_sgmx_lp_adv_reg
 	struct cvmx_pcsx_sgmx_lp_adv_reg_s    cn52xxp1;
 	struct cvmx_pcsx_sgmx_lp_adv_reg_s    cn56xx;
 	struct cvmx_pcsx_sgmx_lp_adv_reg_s    cn56xxp1;
+	struct cvmx_pcsx_sgmx_lp_adv_reg_s    cn61xx;
 	struct cvmx_pcsx_sgmx_lp_adv_reg_s    cn63xx;
 	struct cvmx_pcsx_sgmx_lp_adv_reg_s    cn63xxp1;
+	struct cvmx_pcsx_sgmx_lp_adv_reg_s    cn66xx;
+	struct cvmx_pcsx_sgmx_lp_adv_reg_s    cn68xx;
+	struct cvmx_pcsx_sgmx_lp_adv_reg_s    cn68xxp1;
+	struct cvmx_pcsx_sgmx_lp_adv_reg_s    cnf71xx;
 };
 typedef union cvmx_pcsx_sgmx_lp_adv_reg cvmx_pcsx_sgmx_lp_adv_reg_t;
 
@@ -1113,12 +1377,10 @@ typedef union cvmx_pcsx_sgmx_lp_adv_reg cvmx_pcsx_sgmx_lp_adv_reg_t;
  * PCS_TX_STATES_REG = TX State Machines states register
  *
  */
-union cvmx_pcsx_txx_states_reg
-{
+union cvmx_pcsx_txx_states_reg {
 	uint64_t u64;
-	struct cvmx_pcsx_txx_states_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_txx_states_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t xmit                         : 2;  /**< 0=undefined, 1=config, 2=idle, 3=data */
 	uint64_t tx_bad                       : 1;  /**< Xmit state machine in a bad state */
@@ -1134,8 +1396,13 @@ union cvmx_pcsx_txx_states_reg
 	struct cvmx_pcsx_txx_states_reg_s     cn52xxp1;
 	struct cvmx_pcsx_txx_states_reg_s     cn56xx;
 	struct cvmx_pcsx_txx_states_reg_s     cn56xxp1;
+	struct cvmx_pcsx_txx_states_reg_s     cn61xx;
 	struct cvmx_pcsx_txx_states_reg_s     cn63xx;
 	struct cvmx_pcsx_txx_states_reg_s     cn63xxp1;
+	struct cvmx_pcsx_txx_states_reg_s     cn66xx;
+	struct cvmx_pcsx_txx_states_reg_s     cn68xx;
+	struct cvmx_pcsx_txx_states_reg_s     cn68xxp1;
+	struct cvmx_pcsx_txx_states_reg_s     cnf71xx;
 };
 typedef union cvmx_pcsx_txx_states_reg cvmx_pcsx_txx_states_reg_t;
 
@@ -1145,12 +1412,10 @@ typedef union cvmx_pcsx_txx_states_reg cvmx_pcsx_txx_states_reg_t;
  * PCS_POLARITY_REG = TX_RX polarity reg
  *
  */
-union cvmx_pcsx_tx_rxx_polarity_reg
-{
+union cvmx_pcsx_tx_rxx_polarity_reg {
 	uint64_t u64;
-	struct cvmx_pcsx_tx_rxx_polarity_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsx_tx_rxx_polarity_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t rxovrd                       : 1;  /**< When 0, <2> determines polarity
                                                          when 1, <1> determines polarity */
@@ -1172,8 +1437,13 @@ union cvmx_pcsx_tx_rxx_polarity_reg
 	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1;
 	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx;
 	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1;
+	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn61xx;
 	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xx;
 	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xxp1;
+	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn66xx;
+	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xx;
+	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xxp1;
+	struct cvmx_pcsx_tx_rxx_polarity_reg_s cnf71xx;
 };
 typedef union cvmx_pcsx_tx_rxx_polarity_reg cvmx_pcsx_tx_rxx_polarity_reg_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-pcsxx-defs.h b/sys/contrib/octeon-sdk/cvmx-pcsxx-defs.h
index 8483d6a..b47b605 100644
--- a/sys/contrib/octeon-sdk/cvmx-pcsxx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-pcsxx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,204 +49,339 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_PCSXX_TYPEDEFS_H__
-#define __CVMX_PCSXX_TYPEDEFS_H__
+#ifndef __CVMX_PCSXX_DEFS_H__
+#define __CVMX_PCSXX_DEFS_H__
 
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_PCSXX_10GBX_STATUS_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_PCSXX_10GBX_STATUS_REG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 7) * 0x1000000ull;
 }
-#else
-#define CVMX_PCSXX_10GBX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_PCSXX_BIST_STATUS_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_PCSXX_BIST_STATUS_REG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 7) * 0x1000000ull;
 }
-#else
-#define CVMX_PCSXX_BIST_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_PCSXX_BIT_LOCK_STATUS_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_PCSXX_BIT_LOCK_STATUS_REG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 7) * 0x1000000ull;
 }
-#else
-#define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_PCSXX_CONTROL1_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_PCSXX_CONTROL1_REG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 7) * 0x1000000ull;
 }
-#else
-#define CVMX_PCSXX_CONTROL1_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_PCSXX_CONTROL2_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_PCSXX_CONTROL2_REG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 7) * 0x1000000ull;
 }
-#else
-#define CVMX_PCSXX_CONTROL2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_PCSXX_INT_EN_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_PCSXX_INT_EN_REG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 7) * 0x1000000ull;
 }
-#else
-#define CVMX_PCSXX_INT_EN_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_PCSXX_INT_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_PCSXX_INT_REG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 7) * 0x1000000ull;
 }
-#else
-#define CVMX_PCSXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_PCSXX_LOG_ANL_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_PCSXX_LOG_ANL_REG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 7) * 0x1000000ull;
 }
-#else
-#define CVMX_PCSXX_LOG_ANL_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_PCSXX_MISC_CTL_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_PCSXX_MISC_CTL_REG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 7) * 0x1000000ull;
 }
-#else
-#define CVMX_PCSXX_MISC_CTL_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_PCSXX_RX_SYNC_STATES_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_PCSXX_RX_SYNC_STATES_REG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 7) * 0x1000000ull;
 }
-#else
-#define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_PCSXX_SPD_ABIL_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_PCSXX_SPD_ABIL_REG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 7) * 0x1000000ull;
 }
-#else
-#define CVMX_PCSXX_SPD_ABIL_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_PCSXX_STATUS1_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_PCSXX_STATUS1_REG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 7) * 0x1000000ull;
 }
-#else
-#define CVMX_PCSXX_STATUS1_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_PCSXX_STATUS2_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_PCSXX_STATUS2_REG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 7) * 0x1000000ull;
 }
-#else
-#define CVMX_PCSXX_STATUS2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_PCSXX_TX_RX_POLARITY_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_PCSXX_TX_RX_POLARITY_REG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 7) * 0x1000000ull;
 }
-#else
-#define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
-		cvmx_warn("CVMX_PCSXX_TX_RX_STATES_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 1) * 0x8000000ull;
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 1))
+				return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 1) * 0x8000000ull;
+			break;
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((block_id == 0))
+				return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 0) * 0x8000000ull;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((block_id <= 4))
+				return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 7) * 0x1000000ull;
+			break;
+	}
+	cvmx_warn("CVMX_PCSXX_TX_RX_STATES_REG (block_id = %lu) not supported on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 7) * 0x1000000ull;
 }
-#else
-#define CVMX_PCSXX_TX_RX_STATES_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
 
 /**
  * cvmx_pcsx#_10gbx_status_reg
@@ -254,12 +389,10 @@ static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
  * PCSX_10GBX_STATUS_REG = 10gbx_status_reg
  *
  */
-union cvmx_pcsxx_10gbx_status_reg
-{
+union cvmx_pcsxx_10gbx_status_reg {
 	uint64_t u64;
-	struct cvmx_pcsxx_10gbx_status_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_10gbx_status_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t alignd                       : 1;  /**< 1=Lane alignment achieved, 0=Lanes not aligned */
 	uint64_t pattst                       : 1;  /**< Always at 0, no pattern testing capability */
@@ -283,8 +416,12 @@ union cvmx_pcsxx_10gbx_status_reg
 	struct cvmx_pcsxx_10gbx_status_reg_s  cn52xxp1;
 	struct cvmx_pcsxx_10gbx_status_reg_s  cn56xx;
 	struct cvmx_pcsxx_10gbx_status_reg_s  cn56xxp1;
+	struct cvmx_pcsxx_10gbx_status_reg_s  cn61xx;
 	struct cvmx_pcsxx_10gbx_status_reg_s  cn63xx;
 	struct cvmx_pcsxx_10gbx_status_reg_s  cn63xxp1;
+	struct cvmx_pcsxx_10gbx_status_reg_s  cn66xx;
+	struct cvmx_pcsxx_10gbx_status_reg_s  cn68xx;
+	struct cvmx_pcsxx_10gbx_status_reg_s  cn68xxp1;
 };
 typedef union cvmx_pcsxx_10gbx_status_reg cvmx_pcsxx_10gbx_status_reg_t;
 
@@ -299,12 +436,10 @@ typedef union cvmx_pcsxx_10gbx_status_reg cvmx_pcsxx_10gbx_status_reg_t;
  *
  *  PCSX Bist Status Register
  */
-union cvmx_pcsxx_bist_status_reg
-{
+union cvmx_pcsxx_bist_status_reg {
 	uint64_t u64;
-	struct cvmx_pcsxx_bist_status_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_bist_status_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t bist_status                  : 1;  /**< 1=bist failure, 0=bisted memory ok or bist in progress
                                                          pcsx.tx_sm.drf8x36m1_async_bist */
@@ -317,8 +452,12 @@ union cvmx_pcsxx_bist_status_reg
 	struct cvmx_pcsxx_bist_status_reg_s   cn52xxp1;
 	struct cvmx_pcsxx_bist_status_reg_s   cn56xx;
 	struct cvmx_pcsxx_bist_status_reg_s   cn56xxp1;
+	struct cvmx_pcsxx_bist_status_reg_s   cn61xx;
 	struct cvmx_pcsxx_bist_status_reg_s   cn63xx;
 	struct cvmx_pcsxx_bist_status_reg_s   cn63xxp1;
+	struct cvmx_pcsxx_bist_status_reg_s   cn66xx;
+	struct cvmx_pcsxx_bist_status_reg_s   cn68xx;
+	struct cvmx_pcsxx_bist_status_reg_s   cn68xxp1;
 };
 typedef union cvmx_pcsxx_bist_status_reg cvmx_pcsxx_bist_status_reg_t;
 
@@ -330,12 +469,10 @@ typedef union cvmx_pcsxx_bist_status_reg cvmx_pcsxx_bist_status_reg_t;
  *
  * PCSX Bit Lock Status Register
  */
-union cvmx_pcsxx_bit_lock_status_reg
-{
+union cvmx_pcsxx_bit_lock_status_reg {
 	uint64_t u64;
-	struct cvmx_pcsxx_bit_lock_status_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_bit_lock_status_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t bitlck3                      : 1;  /**< Receive Lane 3 bit lock status */
 	uint64_t bitlck2                      : 1;  /**< Receive Lane 2 bit lock status */
@@ -353,8 +490,12 @@ union cvmx_pcsxx_bit_lock_status_reg
 	struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1;
 	struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx;
 	struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1;
+	struct cvmx_pcsxx_bit_lock_status_reg_s cn61xx;
 	struct cvmx_pcsxx_bit_lock_status_reg_s cn63xx;
 	struct cvmx_pcsxx_bit_lock_status_reg_s cn63xxp1;
+	struct cvmx_pcsxx_bit_lock_status_reg_s cn66xx;
+	struct cvmx_pcsxx_bit_lock_status_reg_s cn68xx;
+	struct cvmx_pcsxx_bit_lock_status_reg_s cn68xxp1;
 };
 typedef union cvmx_pcsxx_bit_lock_status_reg cvmx_pcsxx_bit_lock_status_reg_t;
 
@@ -372,12 +513,10 @@ typedef union cvmx_pcsxx_bit_lock_status_reg cvmx_pcsxx_bit_lock_status_reg_t;
  *
  *  PCSX_CONTROL1_REG = Control Register1
  */
-union cvmx_pcsxx_control1_reg
-{
+union cvmx_pcsxx_control1_reg {
 	uint64_t u64;
-	struct cvmx_pcsxx_control1_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_control1_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t reset                        : 1;  /**< 1=SW PCSX Reset, the bit will return to 0 after pcs
                                                          has been reset. Takes 32 eclk cycles to reset pcs
@@ -412,8 +551,12 @@ union cvmx_pcsxx_control1_reg
 	struct cvmx_pcsxx_control1_reg_s      cn52xxp1;
 	struct cvmx_pcsxx_control1_reg_s      cn56xx;
 	struct cvmx_pcsxx_control1_reg_s      cn56xxp1;
+	struct cvmx_pcsxx_control1_reg_s      cn61xx;
 	struct cvmx_pcsxx_control1_reg_s      cn63xx;
 	struct cvmx_pcsxx_control1_reg_s      cn63xxp1;
+	struct cvmx_pcsxx_control1_reg_s      cn66xx;
+	struct cvmx_pcsxx_control1_reg_s      cn68xx;
+	struct cvmx_pcsxx_control1_reg_s      cn68xxp1;
 };
 typedef union cvmx_pcsxx_control1_reg cvmx_pcsxx_control1_reg_t;
 
@@ -423,12 +566,10 @@ typedef union cvmx_pcsxx_control1_reg cvmx_pcsxx_control1_reg_t;
  * PCSX_CONTROL2_REG = Control Register2
  *
  */
-union cvmx_pcsxx_control2_reg
-{
+union cvmx_pcsxx_control2_reg {
 	uint64_t u64;
-	struct cvmx_pcsxx_control2_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_control2_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t type                         : 2;  /**< Always 2'b01, 10GBASE-X only supported */
 #else
@@ -440,8 +581,12 @@ union cvmx_pcsxx_control2_reg
 	struct cvmx_pcsxx_control2_reg_s      cn52xxp1;
 	struct cvmx_pcsxx_control2_reg_s      cn56xx;
 	struct cvmx_pcsxx_control2_reg_s      cn56xxp1;
+	struct cvmx_pcsxx_control2_reg_s      cn61xx;
 	struct cvmx_pcsxx_control2_reg_s      cn63xx;
 	struct cvmx_pcsxx_control2_reg_s      cn63xxp1;
+	struct cvmx_pcsxx_control2_reg_s      cn66xx;
+	struct cvmx_pcsxx_control2_reg_s      cn68xx;
+	struct cvmx_pcsxx_control2_reg_s      cn68xxp1;
 };
 typedef union cvmx_pcsxx_control2_reg cvmx_pcsxx_control2_reg_t;
 
@@ -456,12 +601,10 @@ typedef union cvmx_pcsxx_control2_reg cvmx_pcsxx_control2_reg_t;
  *
  * PCSX Interrupt Enable Register
  */
-union cvmx_pcsxx_int_en_reg
-{
+union cvmx_pcsxx_int_en_reg {
 	uint64_t u64;
-	struct cvmx_pcsxx_int_en_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_int_en_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t dbg_sync_en                  : 1;  /**< Code Group sync failure debug help */
 	uint64_t algnlos_en                   : 1;  /**< Enable ALGNLOS interrupt */
@@ -481,9 +624,8 @@ union cvmx_pcsxx_int_en_reg
 	uint64_t reserved_7_63                : 57;
 #endif
 	} s;
-	struct cvmx_pcsxx_int_en_reg_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_int_en_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t algnlos_en                   : 1;  /**< Enable ALGNLOS interrupt */
 	uint64_t synlos_en                    : 1;  /**< Enable SYNLOS interrupt */
@@ -504,8 +646,12 @@ union cvmx_pcsxx_int_en_reg
 	struct cvmx_pcsxx_int_en_reg_cn52xx   cn52xxp1;
 	struct cvmx_pcsxx_int_en_reg_cn52xx   cn56xx;
 	struct cvmx_pcsxx_int_en_reg_cn52xx   cn56xxp1;
+	struct cvmx_pcsxx_int_en_reg_s        cn61xx;
 	struct cvmx_pcsxx_int_en_reg_s        cn63xx;
 	struct cvmx_pcsxx_int_en_reg_s        cn63xxp1;
+	struct cvmx_pcsxx_int_en_reg_s        cn66xx;
+	struct cvmx_pcsxx_int_en_reg_s        cn68xx;
+	struct cvmx_pcsxx_int_en_reg_s        cn68xxp1;
 };
 typedef union cvmx_pcsxx_int_en_reg cvmx_pcsxx_int_en_reg_t;
 
@@ -515,12 +661,10 @@ typedef union cvmx_pcsxx_int_en_reg cvmx_pcsxx_int_en_reg_t;
  * PCSX Interrupt Register
  *
  */
-union cvmx_pcsxx_int_reg
-{
+union cvmx_pcsxx_int_reg {
 	uint64_t u64;
-	struct cvmx_pcsxx_int_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t dbg_sync                     : 1;  /**< Code Group sync failure debug help, see Note below */
 	uint64_t algnlos                      : 1;  /**< Set when XAUI lanes lose alignment */
@@ -541,9 +685,8 @@ union cvmx_pcsxx_int_reg
 	uint64_t reserved_7_63                : 57;
 #endif
 	} s;
-	struct cvmx_pcsxx_int_reg_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t algnlos                      : 1;  /**< Set when XAUI lanes lose alignment */
 	uint64_t synlos                       : 1;  /**< Set when Code group sync lost on 1 or more  lanes */
@@ -565,8 +708,12 @@ union cvmx_pcsxx_int_reg
 	struct cvmx_pcsxx_int_reg_cn52xx      cn52xxp1;
 	struct cvmx_pcsxx_int_reg_cn52xx      cn56xx;
 	struct cvmx_pcsxx_int_reg_cn52xx      cn56xxp1;
+	struct cvmx_pcsxx_int_reg_s           cn61xx;
 	struct cvmx_pcsxx_int_reg_s           cn63xx;
 	struct cvmx_pcsxx_int_reg_s           cn63xxp1;
+	struct cvmx_pcsxx_int_reg_s           cn66xx;
+	struct cvmx_pcsxx_int_reg_s           cn68xx;
+	struct cvmx_pcsxx_int_reg_s           cn68xxp1;
 };
 typedef union cvmx_pcsxx_int_reg cvmx_pcsxx_int_reg_t;
 
@@ -576,12 +723,10 @@ typedef union cvmx_pcsxx_int_reg cvmx_pcsxx_int_reg_t;
  * PCSX Logic Analyzer Register
  *
  */
-union cvmx_pcsxx_log_anl_reg
-{
+union cvmx_pcsxx_log_anl_reg {
 	uint64_t u64;
-	struct cvmx_pcsxx_log_anl_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_log_anl_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t enc_mode                     : 1;  /**< 1=send xaui encoded data, 0=send xaui raw data to GMX
                                                          See .../rtl/pcs/readme_logic_analyzer.txt for details */
@@ -613,8 +758,12 @@ union cvmx_pcsxx_log_anl_reg
 	struct cvmx_pcsxx_log_anl_reg_s       cn52xxp1;
 	struct cvmx_pcsxx_log_anl_reg_s       cn56xx;
 	struct cvmx_pcsxx_log_anl_reg_s       cn56xxp1;
+	struct cvmx_pcsxx_log_anl_reg_s       cn61xx;
 	struct cvmx_pcsxx_log_anl_reg_s       cn63xx;
 	struct cvmx_pcsxx_log_anl_reg_s       cn63xxp1;
+	struct cvmx_pcsxx_log_anl_reg_s       cn66xx;
+	struct cvmx_pcsxx_log_anl_reg_s       cn68xx;
+	struct cvmx_pcsxx_log_anl_reg_s       cn68xxp1;
 };
 typedef union cvmx_pcsxx_log_anl_reg cvmx_pcsxx_log_anl_reg_t;
 
@@ -631,12 +780,10 @@ typedef union cvmx_pcsxx_log_anl_reg cvmx_pcsxx_log_anl_reg_t;
  *
  * PCSX Misc Control Register
  */
-union cvmx_pcsxx_misc_ctl_reg
-{
+union cvmx_pcsxx_misc_ctl_reg {
 	uint64_t u64;
-	struct cvmx_pcsxx_misc_ctl_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_misc_ctl_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t tx_swap                      : 1;  /**< 0=do not swap xaui lanes going out to qlm's
                                                          1=swap lanes 3 <-> 0   and   2 <-> 1 */
@@ -658,8 +805,12 @@ union cvmx_pcsxx_misc_ctl_reg
 	struct cvmx_pcsxx_misc_ctl_reg_s      cn52xxp1;
 	struct cvmx_pcsxx_misc_ctl_reg_s      cn56xx;
 	struct cvmx_pcsxx_misc_ctl_reg_s      cn56xxp1;
+	struct cvmx_pcsxx_misc_ctl_reg_s      cn61xx;
 	struct cvmx_pcsxx_misc_ctl_reg_s      cn63xx;
 	struct cvmx_pcsxx_misc_ctl_reg_s      cn63xxp1;
+	struct cvmx_pcsxx_misc_ctl_reg_s      cn66xx;
+	struct cvmx_pcsxx_misc_ctl_reg_s      cn68xx;
+	struct cvmx_pcsxx_misc_ctl_reg_s      cn68xxp1;
 };
 typedef union cvmx_pcsxx_misc_ctl_reg cvmx_pcsxx_misc_ctl_reg_t;
 
@@ -669,12 +820,10 @@ typedef union cvmx_pcsxx_misc_ctl_reg cvmx_pcsxx_misc_ctl_reg_t;
  * PCSX_RX_SYNC_STATES_REG = Receive Sync States Register
  *
  */
-union cvmx_pcsxx_rx_sync_states_reg
-{
+union cvmx_pcsxx_rx_sync_states_reg {
 	uint64_t u64;
-	struct cvmx_pcsxx_rx_sync_states_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_rx_sync_states_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t sync3st                      : 4;  /**< Receive lane 3 code grp sync state machine state */
 	uint64_t sync2st                      : 4;  /**< Receive lane 2 code grp sync state machine state */
@@ -692,8 +841,12 @@ union cvmx_pcsxx_rx_sync_states_reg
 	struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1;
 	struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx;
 	struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1;
+	struct cvmx_pcsxx_rx_sync_states_reg_s cn61xx;
 	struct cvmx_pcsxx_rx_sync_states_reg_s cn63xx;
 	struct cvmx_pcsxx_rx_sync_states_reg_s cn63xxp1;
+	struct cvmx_pcsxx_rx_sync_states_reg_s cn66xx;
+	struct cvmx_pcsxx_rx_sync_states_reg_s cn68xx;
+	struct cvmx_pcsxx_rx_sync_states_reg_s cn68xxp1;
 };
 typedef union cvmx_pcsxx_rx_sync_states_reg cvmx_pcsxx_rx_sync_states_reg_t;
 
@@ -703,12 +856,10 @@ typedef union cvmx_pcsxx_rx_sync_states_reg cvmx_pcsxx_rx_sync_states_reg_t;
  * PCSX_SPD_ABIL_REG = Speed ability register
  *
  */
-union cvmx_pcsxx_spd_abil_reg
-{
+union cvmx_pcsxx_spd_abil_reg {
 	uint64_t u64;
-	struct cvmx_pcsxx_spd_abil_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_spd_abil_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t tenpasst                     : 1;  /**< Always 0, no 10PASS-TS/2BASE-TL capability support */
 	uint64_t tengb                        : 1;  /**< Always 1, 10Gb/s supported */
@@ -722,8 +873,12 @@ union cvmx_pcsxx_spd_abil_reg
 	struct cvmx_pcsxx_spd_abil_reg_s      cn52xxp1;
 	struct cvmx_pcsxx_spd_abil_reg_s      cn56xx;
 	struct cvmx_pcsxx_spd_abil_reg_s      cn56xxp1;
+	struct cvmx_pcsxx_spd_abil_reg_s      cn61xx;
 	struct cvmx_pcsxx_spd_abil_reg_s      cn63xx;
 	struct cvmx_pcsxx_spd_abil_reg_s      cn63xxp1;
+	struct cvmx_pcsxx_spd_abil_reg_s      cn66xx;
+	struct cvmx_pcsxx_spd_abil_reg_s      cn68xx;
+	struct cvmx_pcsxx_spd_abil_reg_s      cn68xxp1;
 };
 typedef union cvmx_pcsxx_spd_abil_reg cvmx_pcsxx_spd_abil_reg_t;
 
@@ -733,12 +888,10 @@ typedef union cvmx_pcsxx_spd_abil_reg cvmx_pcsxx_spd_abil_reg_t;
  * PCSX_STATUS1_REG = Status Register1
  *
  */
-union cvmx_pcsxx_status1_reg
-{
+union cvmx_pcsxx_status1_reg {
 	uint64_t u64;
-	struct cvmx_pcsxx_status1_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_status1_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t flt                          : 1;  /**< 1=Fault condition detected, 0=No fault condition
                                                          This bit is a logical OR of Status2 reg bits 11,10 */
@@ -761,8 +914,12 @@ union cvmx_pcsxx_status1_reg
 	struct cvmx_pcsxx_status1_reg_s       cn52xxp1;
 	struct cvmx_pcsxx_status1_reg_s       cn56xx;
 	struct cvmx_pcsxx_status1_reg_s       cn56xxp1;
+	struct cvmx_pcsxx_status1_reg_s       cn61xx;
 	struct cvmx_pcsxx_status1_reg_s       cn63xx;
 	struct cvmx_pcsxx_status1_reg_s       cn63xxp1;
+	struct cvmx_pcsxx_status1_reg_s       cn66xx;
+	struct cvmx_pcsxx_status1_reg_s       cn68xx;
+	struct cvmx_pcsxx_status1_reg_s       cn68xxp1;
 };
 typedef union cvmx_pcsxx_status1_reg cvmx_pcsxx_status1_reg_t;
 
@@ -772,12 +929,10 @@ typedef union cvmx_pcsxx_status1_reg cvmx_pcsxx_status1_reg_t;
  * PCSX_STATUS2_REG = Status Register2
  *
  */
-union cvmx_pcsxx_status2_reg
-{
+union cvmx_pcsxx_status2_reg {
 	uint64_t u64;
-	struct cvmx_pcsxx_status2_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_status2_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t dev                          : 2;  /**< Always at 2'b10, means a Device present at the addr */
 	uint64_t reserved_12_13               : 2;
@@ -805,8 +960,12 @@ union cvmx_pcsxx_status2_reg
 	struct cvmx_pcsxx_status2_reg_s       cn52xxp1;
 	struct cvmx_pcsxx_status2_reg_s       cn56xx;
 	struct cvmx_pcsxx_status2_reg_s       cn56xxp1;
+	struct cvmx_pcsxx_status2_reg_s       cn61xx;
 	struct cvmx_pcsxx_status2_reg_s       cn63xx;
 	struct cvmx_pcsxx_status2_reg_s       cn63xxp1;
+	struct cvmx_pcsxx_status2_reg_s       cn66xx;
+	struct cvmx_pcsxx_status2_reg_s       cn68xx;
+	struct cvmx_pcsxx_status2_reg_s       cn68xxp1;
 };
 typedef union cvmx_pcsxx_status2_reg cvmx_pcsxx_status2_reg_t;
 
@@ -816,12 +975,10 @@ typedef union cvmx_pcsxx_status2_reg cvmx_pcsxx_status2_reg_t;
  * PCSX_POLARITY_REG = TX_RX polarity reg
  *
  */
-union cvmx_pcsxx_tx_rx_polarity_reg
-{
+union cvmx_pcsxx_tx_rx_polarity_reg {
 	uint64_t u64;
-	struct cvmx_pcsxx_tx_rx_polarity_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_tx_rx_polarity_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t xor_rxplrt                   : 4;  /**< Per lane RX polarity control */
 	uint64_t xor_txplrt                   : 4;  /**< Per lane TX polarity control */
@@ -836,9 +993,8 @@ union cvmx_pcsxx_tx_rx_polarity_reg
 #endif
 	} s;
 	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx;
-	struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t rxplrt                       : 1;  /**< 1 is inverted polarity, 0 is normal polarity */
 	uint64_t txplrt                       : 1;  /**< 1 is inverted polarity, 0 is normal polarity */
@@ -850,8 +1006,12 @@ union cvmx_pcsxx_tx_rx_polarity_reg
 	} cn52xxp1;
 	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx;
 	struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1;
+	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn61xx;
 	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xx;
 	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xxp1;
+	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn66xx;
+	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xx;
+	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xxp1;
 };
 typedef union cvmx_pcsxx_tx_rx_polarity_reg cvmx_pcsxx_tx_rx_polarity_reg_t;
 
@@ -861,12 +1021,10 @@ typedef union cvmx_pcsxx_tx_rx_polarity_reg cvmx_pcsxx_tx_rx_polarity_reg_t;
  * PCSX_TX_RX_STATES_REG = Transmit Receive States Register
  *
  */
-union cvmx_pcsxx_tx_rx_states_reg
-{
+union cvmx_pcsxx_tx_rx_states_reg {
 	uint64_t u64;
-	struct cvmx_pcsxx_tx_rx_states_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_tx_rx_states_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t term_err                     : 1;  /**< 1=Check end function detected error in packet
                                                          terminate ||T|| column or the one after it */
@@ -892,9 +1050,8 @@ union cvmx_pcsxx_tx_rx_states_reg
 #endif
 	} s;
 	struct cvmx_pcsxx_tx_rx_states_reg_s  cn52xx;
-	struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t syn3bad                      : 1;  /**< 1=lane 3 code grp sync state machine in bad state */
 	uint64_t syn2bad                      : 1;  /**< 1=lane 2 code grp sync state machine in bad state */
@@ -918,8 +1075,12 @@ union cvmx_pcsxx_tx_rx_states_reg
 	} cn52xxp1;
 	struct cvmx_pcsxx_tx_rx_states_reg_s  cn56xx;
 	struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1;
+	struct cvmx_pcsxx_tx_rx_states_reg_s  cn61xx;
 	struct cvmx_pcsxx_tx_rx_states_reg_s  cn63xx;
 	struct cvmx_pcsxx_tx_rx_states_reg_s  cn63xxp1;
+	struct cvmx_pcsxx_tx_rx_states_reg_s  cn66xx;
+	struct cvmx_pcsxx_tx_rx_states_reg_s  cn68xx;
+	struct cvmx_pcsxx_tx_rx_states_reg_s  cn68xxp1;
 };
 typedef union cvmx_pcsxx_tx_rx_states_reg cvmx_pcsxx_tx_rx_states_reg_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-pemx-defs.h b/sys/contrib/octeon-sdk/cvmx-pemx-defs.h
index bb0269a..fb5c4e6 100644
--- a/sys/contrib/octeon-sdk/cvmx-pemx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-pemx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,18 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_PEMX_TYPEDEFS_H__
-#define __CVMX_PEMX_TYPEDEFS_H__
+#ifndef __CVMX_PEMX_DEFS_H__
+#define __CVMX_PEMX_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PEMX_BAR1_INDEXX(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset <= 15)) && ((block_id <= 1))))))
 		cvmx_warn("CVMX_PEMX_BAR1_INDEXX(%lu,%lu) is invalid on this chip\n", offset, block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8;
 }
@@ -64,10 +68,28 @@ static inline uint64_t CVMX_PEMX_BAR1_INDEXX(unsigned long offset, unsigned long
 #define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_BAR2_MASK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_BAR2_MASK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PEMX_BAR_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PEMX_BAR_CTL(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull;
 }
@@ -78,7 +100,11 @@ static inline uint64_t CVMX_PEMX_BAR_CTL(unsigned long block_id)
 static inline uint64_t CVMX_PEMX_BIST_STATUS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PEMX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull;
 }
@@ -89,7 +115,11 @@ static inline uint64_t CVMX_PEMX_BIST_STATUS(unsigned long block_id)
 static inline uint64_t CVMX_PEMX_BIST_STATUS2(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PEMX_BIST_STATUS2(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull;
 }
@@ -100,7 +130,11 @@ static inline uint64_t CVMX_PEMX_BIST_STATUS2(unsigned long block_id)
 static inline uint64_t CVMX_PEMX_CFG_RD(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PEMX_CFG_RD(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull;
 }
@@ -111,7 +145,11 @@ static inline uint64_t CVMX_PEMX_CFG_RD(unsigned long block_id)
 static inline uint64_t CVMX_PEMX_CFG_WR(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PEMX_CFG_WR(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull;
 }
@@ -122,7 +160,11 @@ static inline uint64_t CVMX_PEMX_CFG_WR(unsigned long block_id)
 static inline uint64_t CVMX_PEMX_CPL_LUT_VALID(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PEMX_CPL_LUT_VALID(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull;
 }
@@ -133,7 +175,11 @@ static inline uint64_t CVMX_PEMX_CPL_LUT_VALID(unsigned long block_id)
 static inline uint64_t CVMX_PEMX_CTL_STATUS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PEMX_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull;
 }
@@ -144,7 +190,11 @@ static inline uint64_t CVMX_PEMX_CTL_STATUS(unsigned long block_id)
 static inline uint64_t CVMX_PEMX_DBG_INFO(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PEMX_DBG_INFO(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull;
 }
@@ -155,7 +205,11 @@ static inline uint64_t CVMX_PEMX_DBG_INFO(unsigned long block_id)
 static inline uint64_t CVMX_PEMX_DBG_INFO_EN(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PEMX_DBG_INFO_EN(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull;
 }
@@ -166,7 +220,11 @@ static inline uint64_t CVMX_PEMX_DBG_INFO_EN(unsigned long block_id)
 static inline uint64_t CVMX_PEMX_DIAG_STATUS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PEMX_DIAG_STATUS(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull;
 }
@@ -174,10 +232,28 @@ static inline uint64_t CVMX_PEMX_DIAG_STATUS(unsigned long block_id)
 #define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_INB_READ_CREDITS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_INB_READ_CREDITS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PEMX_INT_ENB(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PEMX_INT_ENB(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull;
 }
@@ -188,7 +264,11 @@ static inline uint64_t CVMX_PEMX_INT_ENB(unsigned long block_id)
 static inline uint64_t CVMX_PEMX_INT_ENB_INT(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PEMX_INT_ENB_INT(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull;
 }
@@ -199,7 +279,11 @@ static inline uint64_t CVMX_PEMX_INT_ENB_INT(unsigned long block_id)
 static inline uint64_t CVMX_PEMX_INT_SUM(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PEMX_INT_SUM(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull;
 }
@@ -210,7 +294,11 @@ static inline uint64_t CVMX_PEMX_INT_SUM(unsigned long block_id)
 static inline uint64_t CVMX_PEMX_P2N_BAR0_START(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PEMX_P2N_BAR0_START(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull;
 }
@@ -221,7 +309,11 @@ static inline uint64_t CVMX_PEMX_P2N_BAR0_START(unsigned long block_id)
 static inline uint64_t CVMX_PEMX_P2N_BAR1_START(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PEMX_P2N_BAR1_START(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull;
 }
@@ -232,7 +324,11 @@ static inline uint64_t CVMX_PEMX_P2N_BAR1_START(unsigned long block_id)
 static inline uint64_t CVMX_PEMX_P2N_BAR2_START(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PEMX_P2N_BAR2_START(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull;
 }
@@ -243,7 +339,9 @@ static inline uint64_t CVMX_PEMX_P2N_BAR2_START(unsigned long block_id)
 static inline uint64_t CVMX_PEMX_P2P_BARX_END(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 3)) && ((block_id <= 1))))))
 		cvmx_warn("CVMX_PEMX_P2P_BARX_END(%lu,%lu) is invalid on this chip\n", offset, block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16;
 }
@@ -254,7 +352,9 @@ static inline uint64_t CVMX_PEMX_P2P_BARX_END(unsigned long offset, unsigned lon
 static inline uint64_t CVMX_PEMX_P2P_BARX_START(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 3)) && ((block_id <= 1))))))
 		cvmx_warn("CVMX_PEMX_P2P_BARX_START(%lu,%lu) is invalid on this chip\n", offset, block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16;
 }
@@ -265,7 +365,11 @@ static inline uint64_t CVMX_PEMX_P2P_BARX_START(unsigned long offset, unsigned l
 static inline uint64_t CVMX_PEMX_TLP_CREDITS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
 		cvmx_warn("CVMX_PEMX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull;
 }
@@ -280,12 +384,10 @@ static inline uint64_t CVMX_PEMX_TLP_CREDITS(unsigned long block_id)
  *
  * Contains address index and control bits for access to memory ranges of BAR-1. Index is build from supplied address [25:22].
  */
-union cvmx_pemx_bar1_indexx
-{
+union cvmx_pemx_bar1_indexx {
 	uint64_t u64;
-	struct cvmx_pemx_bar1_indexx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_bar1_indexx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t addr_idx                     : 16; /**< Address bits [37:22] sent to L2C */
 	uint64_t ca                           : 1;  /**< Set '1' when access is not to be cached in L2. */
@@ -299,24 +401,56 @@ union cvmx_pemx_bar1_indexx
 	uint64_t reserved_20_63               : 44;
 #endif
 	} s;
+	struct cvmx_pemx_bar1_indexx_s        cn61xx;
 	struct cvmx_pemx_bar1_indexx_s        cn63xx;
 	struct cvmx_pemx_bar1_indexx_s        cn63xxp1;
+	struct cvmx_pemx_bar1_indexx_s        cn66xx;
+	struct cvmx_pemx_bar1_indexx_s        cn68xx;
+	struct cvmx_pemx_bar1_indexx_s        cn68xxp1;
+	struct cvmx_pemx_bar1_indexx_s        cnf71xx;
 };
 typedef union cvmx_pemx_bar1_indexx cvmx_pemx_bar1_indexx_t;
 
 /**
+ * cvmx_pem#_bar2_mask
+ *
+ * PEM_BAR2_MASK = PEM BAR2 MASK
+ *
+ * The mask pattern that is ANDED with the address from PCIe core for BAR2 hits.
+ */
+union cvmx_pemx_bar2_mask {
+	uint64_t u64;
+	struct cvmx_pemx_bar2_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_38_63               : 26;
+	uint64_t mask                         : 35; /**< The value to be ANDED with the address sent to
+                                                         the Octeon memory. */
+	uint64_t reserved_0_2                 : 3;
+#else
+	uint64_t reserved_0_2                 : 3;
+	uint64_t mask                         : 35;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_pemx_bar2_mask_s          cn61xx;
+	struct cvmx_pemx_bar2_mask_s          cn66xx;
+	struct cvmx_pemx_bar2_mask_s          cn68xx;
+	struct cvmx_pemx_bar2_mask_s          cn68xxp1;
+	struct cvmx_pemx_bar2_mask_s          cnf71xx;
+};
+typedef union cvmx_pemx_bar2_mask cvmx_pemx_bar2_mask_t;
+
+/**
  * cvmx_pem#_bar_ctl
  *
- * PEM_BAR_CTUS = PEM BAR Control
+ * PEM_BAR_CTL = PEM BAR Control
  *
  * Contains control for BAR accesses.
  */
-union cvmx_pemx_bar_ctl
-{
+union cvmx_pemx_bar_ctl {
 	uint64_t u64;
-	struct cvmx_pemx_bar_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_bar_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t bar1_siz                     : 3;  /**< Pcie-Port0, Bar1 Size. 1 == 64MB, 2 == 128MB,
                                                          3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB,
@@ -336,8 +470,13 @@ union cvmx_pemx_bar_ctl
 	uint64_t reserved_7_63                : 57;
 #endif
 	} s;
+	struct cvmx_pemx_bar_ctl_s            cn61xx;
 	struct cvmx_pemx_bar_ctl_s            cn63xx;
 	struct cvmx_pemx_bar_ctl_s            cn63xxp1;
+	struct cvmx_pemx_bar_ctl_s            cn66xx;
+	struct cvmx_pemx_bar_ctl_s            cn68xx;
+	struct cvmx_pemx_bar_ctl_s            cn68xxp1;
+	struct cvmx_pemx_bar_ctl_s            cnf71xx;
 };
 typedef union cvmx_pemx_bar_ctl cvmx_pemx_bar_ctl_t;
 
@@ -348,12 +487,10 @@ typedef union cvmx_pemx_bar_ctl cvmx_pemx_bar_ctl_t;
  *
  * Contains the diffrent interrupt summary bits of the PEM.
  */
-union cvmx_pemx_bist_status
-{
+union cvmx_pemx_bist_status {
 	uint64_t u64;
-	struct cvmx_pemx_bist_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t retry                        : 1;  /**< Retry Buffer. */
 	uint64_t rqdata0                      : 1;  /**< Rx Queue Data Memory0. */
@@ -375,8 +512,13 @@ union cvmx_pemx_bist_status
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
+	struct cvmx_pemx_bist_status_s        cn61xx;
 	struct cvmx_pemx_bist_status_s        cn63xx;
 	struct cvmx_pemx_bist_status_s        cn63xxp1;
+	struct cvmx_pemx_bist_status_s        cn66xx;
+	struct cvmx_pemx_bist_status_s        cn68xx;
+	struct cvmx_pemx_bist_status_s        cn68xxp1;
+	struct cvmx_pemx_bist_status_s        cnf71xx;
 };
 typedef union cvmx_pemx_bist_status cvmx_pemx_bist_status_t;
 
@@ -387,12 +529,10 @@ typedef union cvmx_pemx_bist_status cvmx_pemx_bist_status_t;
  *
  * Results from BIST runs of PEM's memories.
  */
-union cvmx_pemx_bist_status2
-{
+union cvmx_pemx_bist_status2 {
 	uint64_t u64;
-	struct cvmx_pemx_bist_status2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_bist_status2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t e2p_cpl                      : 1;  /**< BIST Status for the e2p_cpl_fifo */
 	uint64_t e2p_n                        : 1;  /**< BIST Status for the e2p_n_fifo */
@@ -418,8 +558,13 @@ union cvmx_pemx_bist_status2
 	uint64_t reserved_10_63               : 54;
 #endif
 	} s;
+	struct cvmx_pemx_bist_status2_s       cn61xx;
 	struct cvmx_pemx_bist_status2_s       cn63xx;
 	struct cvmx_pemx_bist_status2_s       cn63xxp1;
+	struct cvmx_pemx_bist_status2_s       cn66xx;
+	struct cvmx_pemx_bist_status2_s       cn68xx;
+	struct cvmx_pemx_bist_status2_s       cn68xxp1;
+	struct cvmx_pemx_bist_status2_s       cnf71xx;
 };
 typedef union cvmx_pemx_bist_status2 cvmx_pemx_bist_status2_t;
 
@@ -430,12 +575,10 @@ typedef union cvmx_pemx_bist_status2 cvmx_pemx_bist_status2_t;
  *
  * Allows read access to the configuration in the PCIe Core.
  */
-union cvmx_pemx_cfg_rd
-{
+union cvmx_pemx_cfg_rd {
 	uint64_t u64;
-	struct cvmx_pemx_cfg_rd_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_cfg_rd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 32; /**< Data. */
 	uint64_t addr                         : 32; /**< Address to read. A write to this register
                                                          starts a read operation. */
@@ -444,8 +587,13 @@ union cvmx_pemx_cfg_rd
 	uint64_t data                         : 32;
 #endif
 	} s;
+	struct cvmx_pemx_cfg_rd_s             cn61xx;
 	struct cvmx_pemx_cfg_rd_s             cn63xx;
 	struct cvmx_pemx_cfg_rd_s             cn63xxp1;
+	struct cvmx_pemx_cfg_rd_s             cn66xx;
+	struct cvmx_pemx_cfg_rd_s             cn68xx;
+	struct cvmx_pemx_cfg_rd_s             cn68xxp1;
+	struct cvmx_pemx_cfg_rd_s             cnf71xx;
 };
 typedef union cvmx_pemx_cfg_rd cvmx_pemx_cfg_rd_t;
 
@@ -456,12 +604,10 @@ typedef union cvmx_pemx_cfg_rd cvmx_pemx_cfg_rd_t;
  *
  * Allows write access to the configuration in the PCIe Core.
  */
-union cvmx_pemx_cfg_wr
-{
+union cvmx_pemx_cfg_wr {
 	uint64_t u64;
-	struct cvmx_pemx_cfg_wr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_cfg_wr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 32; /**< Data to write. A write to this register starts
                                                          a write operation. */
 	uint64_t addr                         : 32; /**< Address to write. A write to this register starts
@@ -471,8 +617,13 @@ union cvmx_pemx_cfg_wr
 	uint64_t data                         : 32;
 #endif
 	} s;
+	struct cvmx_pemx_cfg_wr_s             cn61xx;
 	struct cvmx_pemx_cfg_wr_s             cn63xx;
 	struct cvmx_pemx_cfg_wr_s             cn63xxp1;
+	struct cvmx_pemx_cfg_wr_s             cn66xx;
+	struct cvmx_pemx_cfg_wr_s             cn68xx;
+	struct cvmx_pemx_cfg_wr_s             cn68xxp1;
+	struct cvmx_pemx_cfg_wr_s             cnf71xx;
 };
 typedef union cvmx_pemx_cfg_wr cvmx_pemx_cfg_wr_t;
 
@@ -483,12 +634,10 @@ typedef union cvmx_pemx_cfg_wr cvmx_pemx_cfg_wr_t;
  *
  * Bit set for outstanding tag read.
  */
-union cvmx_pemx_cpl_lut_valid
-{
+union cvmx_pemx_cpl_lut_valid {
 	uint64_t u64;
-	struct cvmx_pemx_cpl_lut_valid_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_cpl_lut_valid_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t tag                          : 32; /**< Bit vector set cooresponds to an outstanding tag
                                                          expecting a completion. */
@@ -497,24 +646,33 @@ union cvmx_pemx_cpl_lut_valid
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_pemx_cpl_lut_valid_s      cn61xx;
 	struct cvmx_pemx_cpl_lut_valid_s      cn63xx;
 	struct cvmx_pemx_cpl_lut_valid_s      cn63xxp1;
+	struct cvmx_pemx_cpl_lut_valid_s      cn66xx;
+	struct cvmx_pemx_cpl_lut_valid_s      cn68xx;
+	struct cvmx_pemx_cpl_lut_valid_s      cn68xxp1;
+	struct cvmx_pemx_cpl_lut_valid_s      cnf71xx;
 };
 typedef union cvmx_pemx_cpl_lut_valid cvmx_pemx_cpl_lut_valid_t;
 
 /**
  * cvmx_pem#_ctl_status
  *
- * PEM_CTL_STATUS = PEM Control Status
+ * NOTE: Logic Analyzer is enabled with LA_EN for the specified PCS lane only. PKT_SZ is effective only when LA_EN=1
+ * For normal operation(sgmii or 1000Base-X), this bit must be 0.
+ * See pcsx.csr for xaui logic analyzer mode.
+ * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt
+ *
+ *
+ *                   PEM_CTL_STATUS = PEM Control Status
  *
- * General control and status of the PEM.
+ *  General control and status of the PEM.
  */
-union cvmx_pemx_ctl_status
-{
+union cvmx_pemx_ctl_status {
 	uint64_t u64;
-	struct cvmx_pemx_ctl_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t auto_sd                      : 1;  /**< Link Hardware Autonomous Speed Disable. */
 	uint64_t dnum                         : 5;  /**< Primary bus device number. */
@@ -569,8 +727,13 @@ union cvmx_pemx_ctl_status
 	uint64_t reserved_48_63               : 16;
 #endif
 	} s;
+	struct cvmx_pemx_ctl_status_s         cn61xx;
 	struct cvmx_pemx_ctl_status_s         cn63xx;
 	struct cvmx_pemx_ctl_status_s         cn63xxp1;
+	struct cvmx_pemx_ctl_status_s         cn66xx;
+	struct cvmx_pemx_ctl_status_s         cn68xx;
+	struct cvmx_pemx_ctl_status_s         cn68xxp1;
+	struct cvmx_pemx_ctl_status_s         cnf71xx;
 };
 typedef union cvmx_pemx_ctl_status cvmx_pemx_ctl_status_t;
 
@@ -581,12 +744,10 @@ typedef union cvmx_pemx_ctl_status cvmx_pemx_ctl_status_t;
  *
  * General debug info.
  */
-union cvmx_pemx_dbg_info
-{
+union cvmx_pemx_dbg_info {
 	uint64_t u64;
-	struct cvmx_pemx_dbg_info_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_dbg_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t ecrc_e                       : 1;  /**< Received a ECRC error.
                                                          radm_ecrc_err */
@@ -698,8 +859,13 @@ union cvmx_pemx_dbg_info
 	uint64_t reserved_31_63               : 33;
 #endif
 	} s;
+	struct cvmx_pemx_dbg_info_s           cn61xx;
 	struct cvmx_pemx_dbg_info_s           cn63xx;
 	struct cvmx_pemx_dbg_info_s           cn63xxp1;
+	struct cvmx_pemx_dbg_info_s           cn66xx;
+	struct cvmx_pemx_dbg_info_s           cn68xx;
+	struct cvmx_pemx_dbg_info_s           cn68xxp1;
+	struct cvmx_pemx_dbg_info_s           cnf71xx;
 };
 typedef union cvmx_pemx_dbg_info cvmx_pemx_dbg_info_t;
 
@@ -710,12 +876,10 @@ typedef union cvmx_pemx_dbg_info cvmx_pemx_dbg_info_t;
  *
  * Allows PEM_DBG_INFO to generate interrupts when cooresponding enable bit is set.
  */
-union cvmx_pemx_dbg_info_en
-{
+union cvmx_pemx_dbg_info_en {
 	uint64_t u64;
-	struct cvmx_pemx_dbg_info_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_dbg_info_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t ecrc_e                       : 1;  /**< Allows PEM_DBG_INFO[30] to generate an interrupt. */
 	uint64_t rawwpp                       : 1;  /**< Allows PEM_DBG_INFO[29] to generate an interrupt. */
@@ -783,8 +947,13 @@ union cvmx_pemx_dbg_info_en
 	uint64_t reserved_31_63               : 33;
 #endif
 	} s;
+	struct cvmx_pemx_dbg_info_en_s        cn61xx;
 	struct cvmx_pemx_dbg_info_en_s        cn63xx;
 	struct cvmx_pemx_dbg_info_en_s        cn63xxp1;
+	struct cvmx_pemx_dbg_info_en_s        cn66xx;
+	struct cvmx_pemx_dbg_info_en_s        cn68xx;
+	struct cvmx_pemx_dbg_info_en_s        cn68xxp1;
+	struct cvmx_pemx_dbg_info_en_s        cnf71xx;
 };
 typedef union cvmx_pemx_dbg_info_en cvmx_pemx_dbg_info_en_t;
 
@@ -795,12 +964,10 @@ typedef union cvmx_pemx_dbg_info_en cvmx_pemx_dbg_info_en_t;
  *
  * Selection control for the cores diagnostic bus.
  */
-union cvmx_pemx_diag_status
-{
+union cvmx_pemx_diag_status {
 	uint64_t u64;
-	struct cvmx_pemx_diag_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_diag_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t pm_dst                       : 1;  /**< Current power management DSTATE. */
 	uint64_t pm_stat                      : 1;  /**< Power Management Status. */
@@ -814,24 +981,54 @@ union cvmx_pemx_diag_status
 	uint64_t reserved_4_63                : 60;
 #endif
 	} s;
+	struct cvmx_pemx_diag_status_s        cn61xx;
 	struct cvmx_pemx_diag_status_s        cn63xx;
 	struct cvmx_pemx_diag_status_s        cn63xxp1;
+	struct cvmx_pemx_diag_status_s        cn66xx;
+	struct cvmx_pemx_diag_status_s        cn68xx;
+	struct cvmx_pemx_diag_status_s        cn68xxp1;
+	struct cvmx_pemx_diag_status_s        cnf71xx;
 };
 typedef union cvmx_pemx_diag_status cvmx_pemx_diag_status_t;
 
 /**
+ * cvmx_pem#_inb_read_credits
+ *
+ * PEM_INB_READ_CREDITS
+ *
+ * The number of in flight reads from PCIe core to SLI
+ */
+union cvmx_pemx_inb_read_credits {
+	uint64_t u64;
+	struct cvmx_pemx_inb_read_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_6_63                : 58;
+	uint64_t num                          : 6;  /**< The number of reads that may be in flight from
+                                                         the PCIe core to the SLI. Min number is 2 max
+                                                         number is 32. */
+#else
+	uint64_t num                          : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_pemx_inb_read_credits_s   cn61xx;
+	struct cvmx_pemx_inb_read_credits_s   cn66xx;
+	struct cvmx_pemx_inb_read_credits_s   cn68xx;
+	struct cvmx_pemx_inb_read_credits_s   cnf71xx;
+};
+typedef union cvmx_pemx_inb_read_credits cvmx_pemx_inb_read_credits_t;
+
+/**
  * cvmx_pem#_int_enb
  *
  * PEM(0..1)_INT_ENB = PEM Interrupt Enable
  *
  * Enables interrupt conditions for the PEM to generate an RSL interrupt.
  */
-union cvmx_pemx_int_enb
-{
+union cvmx_pemx_int_enb {
 	uint64_t u64;
-	struct cvmx_pemx_int_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t crs_dr                       : 1;  /**< Enables PEM_INT_SUM[13] to generate an
                                                          interrupt to the MIO. */
@@ -879,8 +1076,13 @@ union cvmx_pemx_int_enb
 	uint64_t reserved_14_63               : 50;
 #endif
 	} s;
+	struct cvmx_pemx_int_enb_s            cn61xx;
 	struct cvmx_pemx_int_enb_s            cn63xx;
 	struct cvmx_pemx_int_enb_s            cn63xxp1;
+	struct cvmx_pemx_int_enb_s            cn66xx;
+	struct cvmx_pemx_int_enb_s            cn68xx;
+	struct cvmx_pemx_int_enb_s            cn68xxp1;
+	struct cvmx_pemx_int_enb_s            cnf71xx;
 };
 typedef union cvmx_pemx_int_enb cvmx_pemx_int_enb_t;
 
@@ -891,12 +1093,10 @@ typedef union cvmx_pemx_int_enb cvmx_pemx_int_enb_t;
  *
  * Enables interrupt conditions for the PEM to generate an RSL interrupt.
  */
-union cvmx_pemx_int_enb_int
-{
+union cvmx_pemx_int_enb_int {
 	uint64_t u64;
-	struct cvmx_pemx_int_enb_int_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_int_enb_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t crs_dr                       : 1;  /**< Enables PEM_INT_SUM[13] to generate an
                                                          interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
@@ -944,8 +1144,13 @@ union cvmx_pemx_int_enb_int
 	uint64_t reserved_14_63               : 50;
 #endif
 	} s;
+	struct cvmx_pemx_int_enb_int_s        cn61xx;
 	struct cvmx_pemx_int_enb_int_s        cn63xx;
 	struct cvmx_pemx_int_enb_int_s        cn63xxp1;
+	struct cvmx_pemx_int_enb_int_s        cn66xx;
+	struct cvmx_pemx_int_enb_int_s        cn68xx;
+	struct cvmx_pemx_int_enb_int_s        cn68xxp1;
+	struct cvmx_pemx_int_enb_int_s        cnf71xx;
 };
 typedef union cvmx_pemx_int_enb_int cvmx_pemx_int_enb_int_t;
 
@@ -958,12 +1163,10 @@ typedef union cvmx_pemx_int_enb_int cvmx_pemx_int_enb_int_t;
  *
  * Interrupt conditions for the PEM.
  */
-union cvmx_pemx_int_sum
-{
+union cvmx_pemx_int_sum {
 	uint64_t u64;
-	struct cvmx_pemx_int_sum_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t crs_dr                       : 1;  /**< Had a CRS Timeout when Retries were disabled. */
 	uint64_t crs_er                       : 1;  /**< Had a CRS Timeout when Retries were enabled. */
@@ -1005,8 +1208,13 @@ union cvmx_pemx_int_sum
 	uint64_t reserved_14_63               : 50;
 #endif
 	} s;
+	struct cvmx_pemx_int_sum_s            cn61xx;
 	struct cvmx_pemx_int_sum_s            cn63xx;
 	struct cvmx_pemx_int_sum_s            cn63xxp1;
+	struct cvmx_pemx_int_sum_s            cn66xx;
+	struct cvmx_pemx_int_sum_s            cn68xx;
+	struct cvmx_pemx_int_sum_s            cn68xxp1;
+	struct cvmx_pemx_int_sum_s            cnf71xx;
 };
 typedef union cvmx_pemx_int_sum cvmx_pemx_int_sum_t;
 
@@ -1017,12 +1225,10 @@ typedef union cvmx_pemx_int_sum cvmx_pemx_int_sum_t;
  *
  * The starting address for addresses to forwarded to the SLI in RC Mode.
  */
-union cvmx_pemx_p2n_bar0_start
-{
+union cvmx_pemx_p2n_bar0_start {
 	uint64_t u64;
-	struct cvmx_pemx_p2n_bar0_start_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_p2n_bar0_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t addr                         : 50; /**< The starting address of the 16KB address space that
                                                          is the BAR0 address space. */
 	uint64_t reserved_0_13                : 14;
@@ -1031,8 +1237,13 @@ union cvmx_pemx_p2n_bar0_start
 	uint64_t addr                         : 50;
 #endif
 	} s;
+	struct cvmx_pemx_p2n_bar0_start_s     cn61xx;
 	struct cvmx_pemx_p2n_bar0_start_s     cn63xx;
 	struct cvmx_pemx_p2n_bar0_start_s     cn63xxp1;
+	struct cvmx_pemx_p2n_bar0_start_s     cn66xx;
+	struct cvmx_pemx_p2n_bar0_start_s     cn68xx;
+	struct cvmx_pemx_p2n_bar0_start_s     cn68xxp1;
+	struct cvmx_pemx_p2n_bar0_start_s     cnf71xx;
 };
 typedef union cvmx_pemx_p2n_bar0_start cvmx_pemx_p2n_bar0_start_t;
 
@@ -1043,12 +1254,10 @@ typedef union cvmx_pemx_p2n_bar0_start cvmx_pemx_p2n_bar0_start_t;
  *
  * The starting address for addresses to forwarded to the SLI in RC Mode.
  */
-union cvmx_pemx_p2n_bar1_start
-{
+union cvmx_pemx_p2n_bar1_start {
 	uint64_t u64;
-	struct cvmx_pemx_p2n_bar1_start_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_p2n_bar1_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t addr                         : 38; /**< The starting address of the 64KB address space
                                                          that is the BAR1 address space. */
 	uint64_t reserved_0_25                : 26;
@@ -1057,8 +1266,13 @@ union cvmx_pemx_p2n_bar1_start
 	uint64_t addr                         : 38;
 #endif
 	} s;
+	struct cvmx_pemx_p2n_bar1_start_s     cn61xx;
 	struct cvmx_pemx_p2n_bar1_start_s     cn63xx;
 	struct cvmx_pemx_p2n_bar1_start_s     cn63xxp1;
+	struct cvmx_pemx_p2n_bar1_start_s     cn66xx;
+	struct cvmx_pemx_p2n_bar1_start_s     cn68xx;
+	struct cvmx_pemx_p2n_bar1_start_s     cn68xxp1;
+	struct cvmx_pemx_p2n_bar1_start_s     cnf71xx;
 };
 typedef union cvmx_pemx_p2n_bar1_start cvmx_pemx_p2n_bar1_start_t;
 
@@ -1069,12 +1283,10 @@ typedef union cvmx_pemx_p2n_bar1_start cvmx_pemx_p2n_bar1_start_t;
  *
  * The starting address for addresses to forwarded to the SLI in RC Mode.
  */
-union cvmx_pemx_p2n_bar2_start
-{
+union cvmx_pemx_p2n_bar2_start {
 	uint64_t u64;
-	struct cvmx_pemx_p2n_bar2_start_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_p2n_bar2_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t addr                         : 23; /**< The starting address of the 2^41 address space
                                                          that is the BAR2 address space. */
 	uint64_t reserved_0_40                : 41;
@@ -1083,8 +1295,13 @@ union cvmx_pemx_p2n_bar2_start
 	uint64_t addr                         : 23;
 #endif
 	} s;
+	struct cvmx_pemx_p2n_bar2_start_s     cn61xx;
 	struct cvmx_pemx_p2n_bar2_start_s     cn63xx;
 	struct cvmx_pemx_p2n_bar2_start_s     cn63xxp1;
+	struct cvmx_pemx_p2n_bar2_start_s     cn66xx;
+	struct cvmx_pemx_p2n_bar2_start_s     cn68xx;
+	struct cvmx_pemx_p2n_bar2_start_s     cn68xxp1;
+	struct cvmx_pemx_p2n_bar2_start_s     cnf71xx;
 };
 typedef union cvmx_pemx_p2n_bar2_start cvmx_pemx_p2n_bar2_start_t;
 
@@ -1095,12 +1312,10 @@ typedef union cvmx_pemx_p2n_bar2_start cvmx_pemx_p2n_bar2_start_t;
  *
  * The ending address for addresses to forwarded to the PCIe peer port.
  */
-union cvmx_pemx_p2p_barx_end
-{
+union cvmx_pemx_p2p_barx_end {
 	uint64_t u64;
-	struct cvmx_pemx_p2p_barx_end_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_p2p_barx_end_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t addr                         : 52; /**< The ending address of the address window created
                                                          this field and the PEM_P2P_BAR0_START[63:12]
                                                          field. The full 64-bits of address are created by:
@@ -1113,6 +1328,9 @@ union cvmx_pemx_p2p_barx_end
 	} s;
 	struct cvmx_pemx_p2p_barx_end_s       cn63xx;
 	struct cvmx_pemx_p2p_barx_end_s       cn63xxp1;
+	struct cvmx_pemx_p2p_barx_end_s       cn66xx;
+	struct cvmx_pemx_p2p_barx_end_s       cn68xx;
+	struct cvmx_pemx_p2p_barx_end_s       cn68xxp1;
 };
 typedef union cvmx_pemx_p2p_barx_end cvmx_pemx_p2p_barx_end_t;
 
@@ -1123,12 +1341,10 @@ typedef union cvmx_pemx_p2p_barx_end cvmx_pemx_p2p_barx_end_t;
  *
  * The starting address and enable for addresses to forwarded to the PCIe peer port.
  */
-union cvmx_pemx_p2p_barx_start
-{
+union cvmx_pemx_p2p_barx_start {
 	uint64_t u64;
-	struct cvmx_pemx_p2p_barx_start_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_p2p_barx_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t addr                         : 52; /**< The starting address of the address window created
                                                          by this field and the PEM_P2P_BAR0_END[63:12]
                                                          field. The full 64-bits of address are created by:
@@ -1141,6 +1357,9 @@ union cvmx_pemx_p2p_barx_start
 	} s;
 	struct cvmx_pemx_p2p_barx_start_s     cn63xx;
 	struct cvmx_pemx_p2p_barx_start_s     cn63xxp1;
+	struct cvmx_pemx_p2p_barx_start_s     cn66xx;
+	struct cvmx_pemx_p2p_barx_start_s     cn68xx;
+	struct cvmx_pemx_p2p_barx_start_s     cn68xxp1;
 };
 typedef union cvmx_pemx_p2p_barx_start cvmx_pemx_p2p_barx_start_t;
 
@@ -1152,15 +1371,15 @@ typedef union cvmx_pemx_p2p_barx_start cvmx_pemx_p2p_barx_start_t;
  * Specifies the number of credits the PEM for use in moving TLPs. When this register is written the credit values are
  * reset to the register value. A write to this register should take place BEFORE traffic flow starts.
  */
-union cvmx_pemx_tlp_credits
-{
+union cvmx_pemx_tlp_credits {
 	uint64_t u64;
-	struct cvmx_pemx_tlp_credits_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pemx_tlp_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_56_63               : 8;
 	uint64_t peai_ppf                     : 8;  /**< TLP credits for Completion TLPs in the Peer.
-                                                         Legal values are 0x24 to 0x80. */
+                                                         The value in this register should not be changed.
+                                                         Values other than 0x80 can lead to unpredictable
+                                                         behavior */
 	uint64_t pem_cpl                      : 8;  /**< TLP credits for Completion TLPs in the Peer.
                                                          Legal values are 0x24 to 0x80. */
 	uint64_t pem_np                       : 8;  /**< TLP credits for Non-Posted TLPs in the Peer.
@@ -1184,8 +1403,35 @@ union cvmx_pemx_tlp_credits
 	uint64_t reserved_56_63               : 8;
 #endif
 	} s;
+	struct cvmx_pemx_tlp_credits_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t peai_ppf                     : 8;  /**< TLP credits for Completion TLPs in the Peer.
+                                                         The value in this register should not be changed.
+                                                         Values other than 0x80 can lead to unpredictable
+                                                         behavior */
+	uint64_t reserved_24_47               : 24;
+	uint64_t sli_cpl                      : 8;  /**< TLP credits for Completion TLPs in the SLI.
+                                                         Legal values are 0x24 to 0x80. */
+	uint64_t sli_np                       : 8;  /**< TLP credits for Non-Posted TLPs in the SLI.
+                                                         Legal values are 0x4 to 0x10. */
+	uint64_t sli_p                        : 8;  /**< TLP credits for Posted TLPs in the SLI.
+                                                         Legal values are 0x24 to 0x80. */
+#else
+	uint64_t sli_p                        : 8;
+	uint64_t sli_np                       : 8;
+	uint64_t sli_cpl                      : 8;
+	uint64_t reserved_24_47               : 24;
+	uint64_t peai_ppf                     : 8;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn61xx;
 	struct cvmx_pemx_tlp_credits_s        cn63xx;
 	struct cvmx_pemx_tlp_credits_s        cn63xxp1;
+	struct cvmx_pemx_tlp_credits_s        cn66xx;
+	struct cvmx_pemx_tlp_credits_s        cn68xx;
+	struct cvmx_pemx_tlp_credits_s        cn68xxp1;
+	struct cvmx_pemx_tlp_credits_cn61xx   cnf71xx;
 };
 typedef union cvmx_pemx_tlp_credits cvmx_pemx_tlp_credits_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-pescx-defs.h b/sys/contrib/octeon-sdk/cvmx-pescx-defs.h
index 0f9b4e3..354e0d4 100644
--- a/sys/contrib/octeon-sdk/cvmx-pescx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-pescx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_PESCX_TYPEDEFS_H__
-#define __CVMX_PESCX_TYPEDEFS_H__
+#ifndef __CVMX_PESCX_DEFS_H__
+#define __CVMX_PESCX_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PESCX_BIST_STATUS(unsigned long block_id)
@@ -252,12 +252,10 @@ static inline uint64_t CVMX_PESCX_TLP_CREDITS(unsigned long block_id)
  *
  * Contains the diffrent interrupt summary bits of the PESC.
  */
-union cvmx_pescx_bist_status
-{
+union cvmx_pescx_bist_status {
 	uint64_t u64;
-	struct cvmx_pescx_bist_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t rqdata5                      : 1;  /**< Rx Queue Data Memory5. */
 	uint64_t ctlp_or                      : 1;  /**< C-TLP Order Fifo. */
@@ -290,9 +288,8 @@ union cvmx_pescx_bist_status
 #endif
 	} s;
 	struct cvmx_pescx_bist_status_s       cn52xx;
-	struct cvmx_pescx_bist_status_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_bist_status_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t ctlp_or                      : 1;  /**< C-TLP Order Fifo. */
 	uint64_t ntlp_or                      : 1;  /**< N-TLP Order Fifo. */
@@ -334,12 +331,10 @@ typedef union cvmx_pescx_bist_status cvmx_pescx_bist_status_t;
  *
  * Results from BIST runs of PESC's memories.
  */
-union cvmx_pescx_bist_status2
-{
+union cvmx_pescx_bist_status2 {
 	uint64_t u64;
-	struct cvmx_pescx_bist_status2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_bist_status2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t cto_p2e                      : 1;  /**< BIST Status for the cto_p2e_fifo */
 	uint64_t e2p_cpl                      : 1;  /**< BIST Status for the e2p_cpl_fifo */
@@ -387,12 +382,10 @@ typedef union cvmx_pescx_bist_status2 cvmx_pescx_bist_status2_t;
  *
  * Allows read access to the configuration in the PCIe Core.
  */
-union cvmx_pescx_cfg_rd
-{
+union cvmx_pescx_cfg_rd {
 	uint64_t u64;
-	struct cvmx_pescx_cfg_rd_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_cfg_rd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 32; /**< Data. */
 	uint64_t addr                         : 32; /**< Address to read. A write to this register
                                                          starts a read operation. */
@@ -415,12 +408,10 @@ typedef union cvmx_pescx_cfg_rd cvmx_pescx_cfg_rd_t;
  *
  * Allows write access to the configuration in the PCIe Core.
  */
-union cvmx_pescx_cfg_wr
-{
+union cvmx_pescx_cfg_wr {
 	uint64_t u64;
-	struct cvmx_pescx_cfg_wr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_cfg_wr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 32; /**< Data to write. A write to this register starts
                                                          a write operation. */
 	uint64_t addr                         : 32; /**< Address to write. A write to this register starts
@@ -444,12 +435,10 @@ typedef union cvmx_pescx_cfg_wr cvmx_pescx_cfg_wr_t;
  *
  * Bit set for outstanding tag read.
  */
-union cvmx_pescx_cpl_lut_valid
-{
+union cvmx_pescx_cpl_lut_valid {
 	uint64_t u64;
-	struct cvmx_pescx_cpl_lut_valid_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_cpl_lut_valid_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t tag                          : 32; /**< Bit vector set cooresponds to an outstanding tag
                                                          expecting a completion. */
@@ -472,12 +461,10 @@ typedef union cvmx_pescx_cpl_lut_valid cvmx_pescx_cpl_lut_valid_t;
  *
  * General control and status of the PESC.
  */
-union cvmx_pescx_ctl_status
-{
+union cvmx_pescx_ctl_status {
 	uint64_t u64;
-	struct cvmx_pescx_ctl_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t dnum                         : 5;  /**< Primary bus device number. */
 	uint64_t pbus                         : 8;  /**< Primary bus number. */
@@ -525,9 +512,8 @@ union cvmx_pescx_ctl_status
 	} s;
 	struct cvmx_pescx_ctl_status_s        cn52xx;
 	struct cvmx_pescx_ctl_status_s        cn52xxp1;
-	struct cvmx_pescx_ctl_status_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_ctl_status_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t dnum                         : 5;  /**< Primary bus device number. */
 	uint64_t pbus                         : 8;  /**< Primary bus number. */
@@ -584,12 +570,10 @@ typedef union cvmx_pescx_ctl_status cvmx_pescx_ctl_status_t;
  *
  * Results from BIST runs of PESC's memories.
  */
-union cvmx_pescx_ctl_status2
-{
+union cvmx_pescx_ctl_status2 {
 	uint64_t u64;
-	struct cvmx_pescx_ctl_status2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_ctl_status2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t pclk_run                     : 1;  /**< When the pce_clk is running this bit will be '1'.
                                                          Writing a '1' to this location will cause the
@@ -603,9 +587,8 @@ union cvmx_pescx_ctl_status2
 #endif
 	} s;
 	struct cvmx_pescx_ctl_status2_s       cn52xx;
-	struct cvmx_pescx_ctl_status2_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_ctl_status2_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t pcierst                      : 1;  /**< Set to '1' when PCIe is in reset. */
 #else
@@ -625,12 +608,10 @@ typedef union cvmx_pescx_ctl_status2 cvmx_pescx_ctl_status2_t;
  *
  * General debug info.
  */
-union cvmx_pescx_dbg_info
-{
+union cvmx_pescx_dbg_info {
 	uint64_t u64;
-	struct cvmx_pescx_dbg_info_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_dbg_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t ecrc_e                       : 1;  /**< Received a ECRC error.
                                                          radm_ecrc_err */
@@ -756,12 +737,10 @@ typedef union cvmx_pescx_dbg_info cvmx_pescx_dbg_info_t;
  *
  * Allows PESC_DBG_INFO to generate interrupts when cooresponding enable bit is set.
  */
-union cvmx_pescx_dbg_info_en
-{
+union cvmx_pescx_dbg_info_en {
 	uint64_t u64;
-	struct cvmx_pescx_dbg_info_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_dbg_info_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t ecrc_e                       : 1;  /**< Allows PESC_DBG_INFO[30] to generate an interrupt. */
 	uint64_t rawwpp                       : 1;  /**< Allows PESC_DBG_INFO[29] to generate an interrupt. */
@@ -843,12 +822,10 @@ typedef union cvmx_pescx_dbg_info_en cvmx_pescx_dbg_info_en_t;
  *
  * Selection control for the cores diagnostic bus.
  */
-union cvmx_pescx_diag_status
-{
+union cvmx_pescx_diag_status {
 	uint64_t u64;
-	struct cvmx_pescx_diag_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_diag_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t pm_dst                       : 1;  /**< Current power management DSTATE. */
 	uint64_t pm_stat                      : 1;  /**< Power Management Status. */
@@ -876,12 +853,10 @@ typedef union cvmx_pescx_diag_status cvmx_pescx_diag_status_t;
  *
  * The starting address for addresses to forwarded to the NPEI in RC Mode.
  */
-union cvmx_pescx_p2n_bar0_start
-{
+union cvmx_pescx_p2n_bar0_start {
 	uint64_t u64;
-	struct cvmx_pescx_p2n_bar0_start_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_p2n_bar0_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t addr                         : 50; /**< The starting address of the 16KB address space that
                                                          is the BAR0 address space. */
 	uint64_t reserved_0_13                : 14;
@@ -904,12 +879,10 @@ typedef union cvmx_pescx_p2n_bar0_start cvmx_pescx_p2n_bar0_start_t;
  *
  * The starting address for addresses to forwarded to the NPEI in RC Mode.
  */
-union cvmx_pescx_p2n_bar1_start
-{
+union cvmx_pescx_p2n_bar1_start {
 	uint64_t u64;
-	struct cvmx_pescx_p2n_bar1_start_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_p2n_bar1_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t addr                         : 38; /**< The starting address of the 64KB address space
                                                          that is the BAR1 address space. */
 	uint64_t reserved_0_25                : 26;
@@ -932,12 +905,10 @@ typedef union cvmx_pescx_p2n_bar1_start cvmx_pescx_p2n_bar1_start_t;
  *
  * The starting address for addresses to forwarded to the NPEI in RC Mode.
  */
-union cvmx_pescx_p2n_bar2_start
-{
+union cvmx_pescx_p2n_bar2_start {
 	uint64_t u64;
-	struct cvmx_pescx_p2n_bar2_start_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_p2n_bar2_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t addr                         : 25; /**< The starting address of the 2^39 address space
                                                          that is the BAR2 address space. */
 	uint64_t reserved_0_38                : 39;
@@ -960,12 +931,10 @@ typedef union cvmx_pescx_p2n_bar2_start cvmx_pescx_p2n_bar2_start_t;
  *
  * The ending address for addresses to forwarded to the PCIe peer port.
  */
-union cvmx_pescx_p2p_barx_end
-{
+union cvmx_pescx_p2p_barx_end {
 	uint64_t u64;
-	struct cvmx_pescx_p2p_barx_end_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_p2p_barx_end_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t addr                         : 52; /**< The ending address of the address window created
                                                          this field and the PESC_P2P_BAR0_START[63:12]
                                                          field. The full 64-bits of address are created by:
@@ -990,12 +959,10 @@ typedef union cvmx_pescx_p2p_barx_end cvmx_pescx_p2p_barx_end_t;
  *
  * The starting address and enable for addresses to forwarded to the PCIe peer port.
  */
-union cvmx_pescx_p2p_barx_start
-{
+union cvmx_pescx_p2p_barx_start {
 	uint64_t u64;
-	struct cvmx_pescx_p2p_barx_start_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_p2p_barx_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t addr                         : 52; /**< The starting address of the address window created
                                                          this field and the PESC_P2P_BAR0_END[63:12] field.
                                                          The full 64-bits of address are created by:
@@ -1021,20 +988,17 @@ typedef union cvmx_pescx_p2p_barx_start cvmx_pescx_p2p_barx_start_t;
  * Specifies the number of credits the PESC for use in moving TLPs. When this register is written the credit values are
  * reset to the register value. A write to this register should take place BEFORE traffic flow starts.
  */
-union cvmx_pescx_tlp_credits
-{
+union cvmx_pescx_tlp_credits {
 	uint64_t u64;
-	struct cvmx_pescx_tlp_credits_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_tlp_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_0_63                : 64;
 #else
 	uint64_t reserved_0_63                : 64;
 #endif
 	} s;
-	struct cvmx_pescx_tlp_credits_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_tlp_credits_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_56_63               : 8;
 	uint64_t peai_ppf                     : 8;  /**< TLP credits for Completion TLPs in the Peer.
                                                          Legal values are 0x24 to 0x80. */
@@ -1061,9 +1025,8 @@ union cvmx_pescx_tlp_credits
 	uint64_t reserved_56_63               : 8;
 #endif
 	} cn52xx;
-	struct cvmx_pescx_tlp_credits_cn52xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pescx_tlp_credits_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_38_63               : 26;
 	uint64_t peai_ppf                     : 8;  /**< TLP credits in core clk pre-buffer that holds TLPs
                                                          being sent from PCIe Core to NPEI or PEER. */
diff --git a/sys/contrib/octeon-sdk/cvmx-pexp-defs.h b/sys/contrib/octeon-sdk/cvmx-pexp-defs.h
index 75d3153..6559725 100644
--- a/sys/contrib/octeon-sdk/cvmx-pexp-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-pexp-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -1152,7 +1152,7 @@ static inline uint64_t CVMX_PEXP_NPEI_WINDOW_CTL_FUNC(void)
 #define CVMX_PEXP_SLI_BIST_STATUS CVMX_PEXP_SLI_BIST_STATUS_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_BIST_STATUS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_BIST_STATUS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000010580ull);
 }
@@ -1163,18 +1163,22 @@ static inline uint64_t CVMX_PEXP_SLI_BIST_STATUS_FUNC(void)
 static inline uint64_t CVMX_PEXP_SLI_CTL_PORTX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_PEXP_SLI_CTL_PORTX(%lu) is invalid on this chip\n", offset);
-	return CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16;
+	return CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16;
 }
 #else
-#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_PEXP_SLI_CTL_STATUS CVMX_PEXP_SLI_CTL_STATUS_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_CTL_STATUS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_CTL_STATUS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000010570ull);
 }
@@ -1185,7 +1189,7 @@ static inline uint64_t CVMX_PEXP_SLI_CTL_STATUS_FUNC(void)
 #define CVMX_PEXP_SLI_DATA_OUT_CNT CVMX_PEXP_SLI_DATA_OUT_CNT_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_DATA_OUT_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_DATA_OUT_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F00000105F0ull);
 }
@@ -1196,7 +1200,7 @@ static inline uint64_t CVMX_PEXP_SLI_DATA_OUT_CNT_FUNC(void)
 #define CVMX_PEXP_SLI_DBG_DATA CVMX_PEXP_SLI_DBG_DATA_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_DBG_DATA_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_DBG_DATA not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000010310ull);
 }
@@ -1207,7 +1211,7 @@ static inline uint64_t CVMX_PEXP_SLI_DBG_DATA_FUNC(void)
 #define CVMX_PEXP_SLI_DBG_SELECT CVMX_PEXP_SLI_DBG_SELECT_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_DBG_SELECT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_DBG_SELECT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000010300ull);
 }
@@ -1218,7 +1222,11 @@ static inline uint64_t CVMX_PEXP_SLI_DBG_SELECT_FUNC(void)
 static inline uint64_t CVMX_PEXP_SLI_DMAX_CNT(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_PEXP_SLI_DMAX_CNT(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16;
 }
@@ -1229,7 +1237,11 @@ static inline uint64_t CVMX_PEXP_SLI_DMAX_CNT(unsigned long offset)
 static inline uint64_t CVMX_PEXP_SLI_DMAX_INT_LEVEL(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_PEXP_SLI_DMAX_INT_LEVEL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16;
 }
@@ -1240,7 +1252,11 @@ static inline uint64_t CVMX_PEXP_SLI_DMAX_INT_LEVEL(unsigned long offset)
 static inline uint64_t CVMX_PEXP_SLI_DMAX_TIM(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_PEXP_SLI_DMAX_TIM(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16;
 }
@@ -1251,7 +1267,7 @@ static inline uint64_t CVMX_PEXP_SLI_DMAX_TIM(unsigned long offset)
 #define CVMX_PEXP_SLI_INT_ENB_CIU CVMX_PEXP_SLI_INT_ENB_CIU_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_INT_ENB_CIU_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_INT_ENB_CIU not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013CD0ull);
 }
@@ -1262,7 +1278,11 @@ static inline uint64_t CVMX_PEXP_SLI_INT_ENB_CIU_FUNC(void)
 static inline uint64_t CVMX_PEXP_SLI_INT_ENB_PORTX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_PEXP_SLI_INT_ENB_PORTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16;
 }
@@ -1273,7 +1293,7 @@ static inline uint64_t CVMX_PEXP_SLI_INT_ENB_PORTX(unsigned long offset)
 #define CVMX_PEXP_SLI_INT_SUM CVMX_PEXP_SLI_INT_SUM_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_INT_SUM_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_INT_SUM not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000010330ull);
 }
@@ -1284,7 +1304,7 @@ static inline uint64_t CVMX_PEXP_SLI_INT_SUM_FUNC(void)
 #define CVMX_PEXP_SLI_LAST_WIN_RDATA0 CVMX_PEXP_SLI_LAST_WIN_RDATA0_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA0 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000010600ull);
 }
@@ -1295,7 +1315,7 @@ static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA0_FUNC(void)
 #define CVMX_PEXP_SLI_LAST_WIN_RDATA1 CVMX_PEXP_SLI_LAST_WIN_RDATA1_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000010610ull);
 }
@@ -1303,10 +1323,32 @@ static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA1_FUNC(void)
 #define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA2 CVMX_PEXP_SLI_LAST_WIN_RDATA2_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000106C0ull);
+}
+#else
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA2 (CVMX_ADD_IO_SEG(0x00011F00000106C0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA3 CVMX_PEXP_SLI_LAST_WIN_RDATA3_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000106D0ull);
+}
+#else
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA3 (CVMX_ADD_IO_SEG(0x00011F00000106D0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_PEXP_SLI_MAC_CREDIT_CNT CVMX_PEXP_SLI_MAC_CREDIT_CNT_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MAC_CREDIT_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MAC_CREDIT_CNT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013D70ull);
 }
@@ -1314,10 +1356,21 @@ static inline uint64_t CVMX_PEXP_SLI_MAC_CREDIT_CNT_FUNC(void)
 #define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 CVMX_PEXP_SLI_MAC_CREDIT_CNT2_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MAC_CREDIT_CNT2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MAC_CREDIT_CNT2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013E10ull);
+}
+#else
+#define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 (CVMX_ADD_IO_SEG(0x00011F0000013E10ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_PEXP_SLI_MEM_ACCESS_CTL CVMX_PEXP_SLI_MEM_ACCESS_CTL_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MEM_ACCESS_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MEM_ACCESS_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F00000102F0ull);
 }
@@ -1328,7 +1381,11 @@ static inline uint64_t CVMX_PEXP_SLI_MEM_ACCESS_CTL_FUNC(void)
 static inline uint64_t CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 12) && (offset <= 27))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 12) && (offset <= 27)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 12) && (offset <= 27)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 12) && (offset <= 27)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 12) && (offset <= 27)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 12) && (offset <= 27))))))
 		cvmx_warn("CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12;
 }
@@ -1339,7 +1396,7 @@ static inline uint64_t CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)
 #define CVMX_PEXP_SLI_MSI_ENB0 CVMX_PEXP_SLI_MSI_ENB0_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MSI_ENB0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MSI_ENB0 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013C50ull);
 }
@@ -1350,7 +1407,7 @@ static inline uint64_t CVMX_PEXP_SLI_MSI_ENB0_FUNC(void)
 #define CVMX_PEXP_SLI_MSI_ENB1 CVMX_PEXP_SLI_MSI_ENB1_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MSI_ENB1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MSI_ENB1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013C60ull);
 }
@@ -1361,7 +1418,7 @@ static inline uint64_t CVMX_PEXP_SLI_MSI_ENB1_FUNC(void)
 #define CVMX_PEXP_SLI_MSI_ENB2 CVMX_PEXP_SLI_MSI_ENB2_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MSI_ENB2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MSI_ENB2 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013C70ull);
 }
@@ -1372,7 +1429,7 @@ static inline uint64_t CVMX_PEXP_SLI_MSI_ENB2_FUNC(void)
 #define CVMX_PEXP_SLI_MSI_ENB3 CVMX_PEXP_SLI_MSI_ENB3_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MSI_ENB3_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MSI_ENB3 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013C80ull);
 }
@@ -1383,7 +1440,7 @@ static inline uint64_t CVMX_PEXP_SLI_MSI_ENB3_FUNC(void)
 #define CVMX_PEXP_SLI_MSI_RCV0 CVMX_PEXP_SLI_MSI_RCV0_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MSI_RCV0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MSI_RCV0 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013C10ull);
 }
@@ -1394,7 +1451,7 @@ static inline uint64_t CVMX_PEXP_SLI_MSI_RCV0_FUNC(void)
 #define CVMX_PEXP_SLI_MSI_RCV1 CVMX_PEXP_SLI_MSI_RCV1_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MSI_RCV1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MSI_RCV1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013C20ull);
 }
@@ -1405,7 +1462,7 @@ static inline uint64_t CVMX_PEXP_SLI_MSI_RCV1_FUNC(void)
 #define CVMX_PEXP_SLI_MSI_RCV2 CVMX_PEXP_SLI_MSI_RCV2_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MSI_RCV2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MSI_RCV2 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013C30ull);
 }
@@ -1416,7 +1473,7 @@ static inline uint64_t CVMX_PEXP_SLI_MSI_RCV2_FUNC(void)
 #define CVMX_PEXP_SLI_MSI_RCV3 CVMX_PEXP_SLI_MSI_RCV3_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MSI_RCV3_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MSI_RCV3 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013C40ull);
 }
@@ -1427,7 +1484,7 @@ static inline uint64_t CVMX_PEXP_SLI_MSI_RCV3_FUNC(void)
 #define CVMX_PEXP_SLI_MSI_RD_MAP CVMX_PEXP_SLI_MSI_RD_MAP_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MSI_RD_MAP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MSI_RD_MAP not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013CA0ull);
 }
@@ -1438,7 +1495,7 @@ static inline uint64_t CVMX_PEXP_SLI_MSI_RD_MAP_FUNC(void)
 #define CVMX_PEXP_SLI_MSI_W1C_ENB0 CVMX_PEXP_SLI_MSI_W1C_ENB0_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB0 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013CF0ull);
 }
@@ -1449,7 +1506,7 @@ static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB0_FUNC(void)
 #define CVMX_PEXP_SLI_MSI_W1C_ENB1 CVMX_PEXP_SLI_MSI_W1C_ENB1_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013D00ull);
 }
@@ -1460,7 +1517,7 @@ static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB1_FUNC(void)
 #define CVMX_PEXP_SLI_MSI_W1C_ENB2 CVMX_PEXP_SLI_MSI_W1C_ENB2_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB2 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013D10ull);
 }
@@ -1471,7 +1528,7 @@ static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB2_FUNC(void)
 #define CVMX_PEXP_SLI_MSI_W1C_ENB3 CVMX_PEXP_SLI_MSI_W1C_ENB3_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB3_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB3 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013D20ull);
 }
@@ -1482,7 +1539,7 @@ static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB3_FUNC(void)
 #define CVMX_PEXP_SLI_MSI_W1S_ENB0 CVMX_PEXP_SLI_MSI_W1S_ENB0_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB0 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013D30ull);
 }
@@ -1493,7 +1550,7 @@ static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB0_FUNC(void)
 #define CVMX_PEXP_SLI_MSI_W1S_ENB1 CVMX_PEXP_SLI_MSI_W1S_ENB1_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013D40ull);
 }
@@ -1504,7 +1561,7 @@ static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB1_FUNC(void)
 #define CVMX_PEXP_SLI_MSI_W1S_ENB2 CVMX_PEXP_SLI_MSI_W1S_ENB2_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB2 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013D50ull);
 }
@@ -1515,7 +1572,7 @@ static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB2_FUNC(void)
 #define CVMX_PEXP_SLI_MSI_W1S_ENB3 CVMX_PEXP_SLI_MSI_W1S_ENB3_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB3_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB3 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013D60ull);
 }
@@ -1526,7 +1583,7 @@ static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB3_FUNC(void)
 #define CVMX_PEXP_SLI_MSI_WR_MAP CVMX_PEXP_SLI_MSI_WR_MAP_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_MSI_WR_MAP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_MSI_WR_MAP not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013C90ull);
 }
@@ -1537,7 +1594,7 @@ static inline uint64_t CVMX_PEXP_SLI_MSI_WR_MAP_FUNC(void)
 #define CVMX_PEXP_SLI_PCIE_MSI_RCV CVMX_PEXP_SLI_PCIE_MSI_RCV_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000013CB0ull);
 }
@@ -1548,7 +1605,7 @@ static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_FUNC(void)
 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 CVMX_PEXP_SLI_PCIE_MSI_RCV_B1_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000010650ull);
 }
@@ -1559,7 +1616,7 @@ static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B1_FUNC(void)
 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 CVMX_PEXP_SLI_PCIE_MSI_RCV_B2_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000010660ull);
 }
@@ -1570,7 +1627,7 @@ static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B2_FUNC(void)
 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 CVMX_PEXP_SLI_PCIE_MSI_RCV_B3_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B3_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000010670ull);
 }
@@ -1581,7 +1638,11 @@ static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B3_FUNC(void)
 static inline uint64_t CVMX_PEXP_SLI_PKTX_CNTS(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_PEXP_SLI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16;
 }
@@ -1592,7 +1653,11 @@ static inline uint64_t CVMX_PEXP_SLI_PKTX_CNTS(unsigned long offset)
 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_BADDR(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16;
 }
@@ -1603,7 +1668,11 @@ static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_BADDR(unsigned long offset)
 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16;
 }
@@ -1614,7 +1683,11 @@ static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset
 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16;
 }
@@ -1625,7 +1698,11 @@ static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_HEADER(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16;
 }
@@ -1636,7 +1713,10 @@ static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_HEADER(unsigned long offset)
 static inline uint64_t CVMX_PEXP_SLI_PKTX_IN_BP(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_PEXP_SLI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16;
 }
@@ -1647,7 +1727,11 @@ static inline uint64_t CVMX_PEXP_SLI_PKTX_IN_BP(unsigned long offset)
 static inline uint64_t CVMX_PEXP_SLI_PKTX_OUT_SIZE(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_PEXP_SLI_PKTX_OUT_SIZE(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16;
 }
@@ -1658,7 +1742,11 @@ static inline uint64_t CVMX_PEXP_SLI_PKTX_OUT_SIZE(unsigned long offset)
 static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_BADDR(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16;
 }
@@ -1669,7 +1757,11 @@ static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_BADDR(unsigned long offset)
 static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16;
 }
@@ -1680,7 +1772,11 @@ static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset
 static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16;
 }
@@ -1691,7 +1787,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
 #define CVMX_PEXP_SLI_PKT_CNT_INT CVMX_PEXP_SLI_PKT_CNT_INT_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_CNT_INT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_CNT_INT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011130ull);
 }
@@ -1702,7 +1798,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_CNT_INT_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_CNT_INT_ENB CVMX_PEXP_SLI_PKT_CNT_INT_ENB_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_CNT_INT_ENB_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_CNT_INT_ENB not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011150ull);
 }
@@ -1713,7 +1809,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_CNT_INT_ENB_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_CTL CVMX_PEXP_SLI_PKT_CTL_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011220ull);
 }
@@ -1724,7 +1820,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_CTL_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_DATA_OUT_ES CVMX_PEXP_SLI_PKT_DATA_OUT_ES_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_ES_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_ES not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F00000110B0ull);
 }
@@ -1735,7 +1831,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_ES_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_DATA_OUT_NS CVMX_PEXP_SLI_PKT_DATA_OUT_NS_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_NS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_NS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F00000110A0ull);
 }
@@ -1746,7 +1842,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_NS_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR CVMX_PEXP_SLI_PKT_DATA_OUT_ROR_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_ROR_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_ROR not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011090ull);
 }
@@ -1757,7 +1853,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_ROR_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_DPADDR CVMX_PEXP_SLI_PKT_DPADDR_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_DPADDR_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_DPADDR not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011080ull);
 }
@@ -1768,7 +1864,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_DPADDR_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_INPUT_CONTROL CVMX_PEXP_SLI_PKT_INPUT_CONTROL_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_INPUT_CONTROL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_INPUT_CONTROL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011170ull);
 }
@@ -1779,7 +1875,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_INPUT_CONTROL_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_INSTR_ENB CVMX_PEXP_SLI_PKT_INSTR_ENB_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_ENB_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_ENB not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011000ull);
 }
@@ -1790,7 +1886,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_ENB_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F00000111A0ull);
 }
@@ -1801,7 +1897,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_INSTR_SIZE CVMX_PEXP_SLI_PKT_INSTR_SIZE_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_SIZE_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_SIZE not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011020ull);
 }
@@ -1812,7 +1908,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_SIZE_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_INT_LEVELS CVMX_PEXP_SLI_PKT_INT_LEVELS_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_INT_LEVELS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_INT_LEVELS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011120ull);
 }
@@ -1823,7 +1919,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_INT_LEVELS_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_IN_BP CVMX_PEXP_SLI_PKT_IN_BP_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_IN_BP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_IN_BP not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011210ull);
 }
@@ -1834,7 +1930,11 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_IN_BP_FUNC(void)
 static inline uint64_t CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16;
 }
@@ -1845,7 +1945,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)
 #define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011200ull);
 }
@@ -1856,7 +1956,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT CVMX_PEXP_SLI_PKT_IN_PCIE_PORT_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_IN_PCIE_PORT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_IN_PCIE_PORT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F00000111B0ull);
 }
@@ -1867,7 +1967,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_IN_PCIE_PORT_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_IPTR CVMX_PEXP_SLI_PKT_IPTR_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_IPTR_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_IPTR not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011070ull);
 }
@@ -1878,7 +1978,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_IPTR_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK CVMX_PEXP_SLI_PKT_OUTPUT_WMARK_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_OUTPUT_WMARK_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_OUTPUT_WMARK not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011180ull);
 }
@@ -1889,7 +1989,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_OUTPUT_WMARK_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_OUT_BMODE CVMX_PEXP_SLI_PKT_OUT_BMODE_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_OUT_BMODE_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_OUT_BMODE not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F00000110D0ull);
 }
@@ -1897,10 +1997,21 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_OUT_BMODE_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_OUT_BP_EN CVMX_PEXP_SLI_PKT_OUT_BP_EN_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_OUT_BP_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_OUT_BP_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011240ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_OUT_BP_EN (CVMX_ADD_IO_SEG(0x00011F0000011240ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_PEXP_SLI_PKT_OUT_ENB CVMX_PEXP_SLI_PKT_OUT_ENB_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_OUT_ENB_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_OUT_ENB not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011010ull);
 }
@@ -1911,7 +2022,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_OUT_ENB_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_PCIE_PORT CVMX_PEXP_SLI_PKT_PCIE_PORT_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_PCIE_PORT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_PCIE_PORT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F00000110E0ull);
 }
@@ -1922,7 +2033,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_PCIE_PORT_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_PORT_IN_RST CVMX_PEXP_SLI_PKT_PORT_IN_RST_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_PORT_IN_RST_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_PORT_IN_RST not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F00000111F0ull);
 }
@@ -1933,7 +2044,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_PORT_IN_RST_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_SLIST_ES CVMX_PEXP_SLI_PKT_SLIST_ES_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_ES_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_ES not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011050ull);
 }
@@ -1944,7 +2055,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_ES_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_SLIST_NS CVMX_PEXP_SLI_PKT_SLIST_NS_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_NS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_NS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011040ull);
 }
@@ -1955,7 +2066,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_NS_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_SLIST_ROR CVMX_PEXP_SLI_PKT_SLIST_ROR_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_ROR_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_ROR not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011030ull);
 }
@@ -1966,7 +2077,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_ROR_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_TIME_INT CVMX_PEXP_SLI_PKT_TIME_INT_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_TIME_INT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_TIME_INT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011140ull);
 }
@@ -1977,7 +2088,7 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_TIME_INT_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_TIME_INT_ENB CVMX_PEXP_SLI_PKT_TIME_INT_ENB_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_PKT_TIME_INT_ENB_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_PKT_TIME_INT_ENB not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000011160ull);
 }
@@ -1985,21 +2096,36 @@ static inline uint64_t CVMX_PEXP_SLI_PKT_TIME_INT_ENB_FUNC(void)
 #define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_PORTX_PKIND(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_SLI_PORTX_PKIND(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_SLI_PORTX_PKIND(offset) (CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PEXP_SLI_S2M_PORTX_CTL(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_PEXP_SLI_S2M_PORTX_CTL(%lu) is invalid on this chip\n", offset);
-	return CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16;
+	return CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16;
 }
 #else
-#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_PEXP_SLI_SCRATCH_1 CVMX_PEXP_SLI_SCRATCH_1_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_SCRATCH_1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_SCRATCH_1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F00000103C0ull);
 }
@@ -2010,7 +2136,7 @@ static inline uint64_t CVMX_PEXP_SLI_SCRATCH_1_FUNC(void)
 #define CVMX_PEXP_SLI_SCRATCH_2 CVMX_PEXP_SLI_SCRATCH_2_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_SCRATCH_2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_SCRATCH_2 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F00000103D0ull);
 }
@@ -2021,7 +2147,7 @@ static inline uint64_t CVMX_PEXP_SLI_SCRATCH_2_FUNC(void)
 #define CVMX_PEXP_SLI_STATE1 CVMX_PEXP_SLI_STATE1_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_STATE1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_STATE1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000010620ull);
 }
@@ -2032,7 +2158,7 @@ static inline uint64_t CVMX_PEXP_SLI_STATE1_FUNC(void)
 #define CVMX_PEXP_SLI_STATE2 CVMX_PEXP_SLI_STATE2_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_STATE2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_STATE2 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000010630ull);
 }
@@ -2043,7 +2169,7 @@ static inline uint64_t CVMX_PEXP_SLI_STATE2_FUNC(void)
 #define CVMX_PEXP_SLI_STATE3 CVMX_PEXP_SLI_STATE3_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_STATE3_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_STATE3 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F0000010640ull);
 }
@@ -2051,10 +2177,21 @@ static inline uint64_t CVMX_PEXP_SLI_STATE3_FUNC(void)
 #define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_TX_PIPE CVMX_PEXP_SLI_TX_PIPE_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_TX_PIPE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_PEXP_SLI_TX_PIPE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011230ull);
+}
+#else
+#define CVMX_PEXP_SLI_TX_PIPE (CVMX_ADD_IO_SEG(0x00011F0000011230ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_PEXP_SLI_WINDOW_CTL CVMX_PEXP_SLI_WINDOW_CTL_FUNC()
 static inline uint64_t CVMX_PEXP_SLI_WINDOW_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PEXP_SLI_WINDOW_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011F00000102E0ull);
 }
diff --git a/sys/contrib/octeon-sdk/cvmx-pip-defs.h b/sys/contrib/octeon-sdk/cvmx-pip-defs.h
index c11038f..c98c73e 100644
--- a/sys/contrib/octeon-sdk/cvmx-pip-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-pip-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,28 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_PIP_TYPEDEFS_H__
-#define __CVMX_PIP_TYPEDEFS_H__
+#ifndef __CVMX_PIP_DEFS_H__
+#define __CVMX_PIP_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_ALT_SKIP_CFGX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PIP_ALT_SKIP_CFGX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_PIP_ALT_SKIP_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_PIP_BCK_PRS CVMX_PIP_BCK_PRS_FUNC()
 static inline uint64_t CVMX_PIP_BCK_PRS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PIP_BCK_PRS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800A0000038ull);
 }
@@ -65,10 +79,49 @@ static inline uint64_t CVMX_PIP_BCK_PRS_FUNC(void)
 #endif
 #define CVMX_PIP_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800A0000000ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_BSEL_EXT_CFGX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PIP_BSEL_EXT_CFGX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16;
+}
+#else
+#define CVMX_PIP_BSEL_EXT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_BSEL_EXT_POSX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PIP_BSEL_EXT_POSX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16;
+}
+#else
+#define CVMX_PIP_BSEL_EXT_POSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_BSEL_TBL_ENTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 511))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 511))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 511)))))
+		cvmx_warn("CVMX_PIP_BSEL_TBL_ENTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0003000ull) + ((offset) & 511) * 8;
+}
+#else
+#define CVMX_PIP_BSEL_TBL_ENTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0003000ull) + ((offset) & 511) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_PIP_CLKEN CVMX_PIP_CLKEN_FUNC()
 static inline uint64_t CVMX_PIP_CLKEN_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PIP_CLKEN not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800A0000040ull);
 }
@@ -110,7 +163,11 @@ static inline uint64_t CVMX_PIP_DEC_IPSECX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_PIP_DEC_IPSECX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8;
 }
@@ -121,7 +178,7 @@ static inline uint64_t CVMX_PIP_DEC_IPSECX(unsigned long offset)
 #define CVMX_PIP_DSA_SRC_GRP CVMX_PIP_DSA_SRC_GRP_FUNC()
 static inline uint64_t CVMX_PIP_DSA_SRC_GRP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PIP_DSA_SRC_GRP not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800A0000190ull);
 }
@@ -132,7 +189,7 @@ static inline uint64_t CVMX_PIP_DSA_SRC_GRP_FUNC(void)
 #define CVMX_PIP_DSA_VID_GRP CVMX_PIP_DSA_VID_GRP_FUNC()
 static inline uint64_t CVMX_PIP_DSA_VID_GRP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PIP_DSA_VID_GRP not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800A0000198ull);
 }
@@ -146,7 +203,11 @@ static inline uint64_t CVMX_PIP_FRM_LEN_CHKX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_PIP_FRM_LEN_CHKX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8;
 }
@@ -159,7 +220,7 @@ static inline uint64_t CVMX_PIP_FRM_LEN_CHKX(unsigned long offset)
 #define CVMX_PIP_HG_PRI_QOS CVMX_PIP_HG_PRI_QOS_FUNC()
 static inline uint64_t CVMX_PIP_HG_PRI_QOS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PIP_HG_PRI_QOS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800A00001A0ull);
 }
@@ -170,6 +231,31 @@ static inline uint64_t CVMX_PIP_HG_PRI_QOS_FUNC(void)
 #define CVMX_PIP_INT_REG (CVMX_ADD_IO_SEG(0x00011800A0000008ull))
 #define CVMX_PIP_IP_OFFSET (CVMX_ADD_IO_SEG(0x00011800A0000060ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_PRI_TBLX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 255)))))
+		cvmx_warn("CVMX_PIP_PRI_TBLX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0004000ull) + ((offset) & 255) * 8;
+}
+#else
+#define CVMX_PIP_PRI_TBLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0004000ull) + ((offset) & 255) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_PRT_CFGBX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)) || ((offset >= 44) && (offset <= 47)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+		cvmx_warn("CVMX_PIP_PRT_CFGBX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8;
+}
+#else
+#define CVMX_PIP_PRT_CFGBX(offset) (CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PIP_PRT_CFGX(unsigned long offset)
 {
 	if (!(
@@ -180,7 +266,11 @@ static inline uint64_t CVMX_PIP_PRT_CFGX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
 		cvmx_warn("CVMX_PIP_PRT_CFGX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8;
 }
@@ -198,7 +288,11 @@ static inline uint64_t CVMX_PIP_PRT_TAGX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
 		cvmx_warn("CVMX_PIP_PRT_TAGX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8;
 }
@@ -216,7 +310,10 @@ static inline uint64_t CVMX_PIP_QOS_DIFFX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 63)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 63)))))
 		cvmx_warn("CVMX_PIP_QOS_DIFFX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8;
 }
@@ -234,7 +331,10 @@ static inline uint64_t CVMX_PIP_QOS_VLANX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_PIP_QOS_VLANX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8;
 }
@@ -252,7 +352,11 @@ static inline uint64_t CVMX_PIP_QOS_WATCHX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_PIP_QOS_WATCHX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8;
 }
@@ -272,7 +376,10 @@ static inline uint64_t CVMX_PIP_STAT0_PRTX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
 		cvmx_warn("CVMX_PIP_STAT0_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80;
 }
@@ -280,6 +387,71 @@ static inline uint64_t CVMX_PIP_STAT0_PRTX(unsigned long offset)
 #define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT0_X(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_PIP_STAT0_X(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128;
+}
+#else
+#define CVMX_PIP_STAT0_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT10_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+		cvmx_warn("CVMX_PIP_STAT10_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16;
+}
+#else
+#define CVMX_PIP_STAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT10_X(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_PIP_STAT10_X(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0040050ull) + ((offset) & 63) * 128;
+}
+#else
+#define CVMX_PIP_STAT10_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040050ull) + ((offset) & 63) * 128)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT11_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+		cvmx_warn("CVMX_PIP_STAT11_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0001488ull) + ((offset) & 63) * 16;
+}
+#else
+#define CVMX_PIP_STAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001488ull) + ((offset) & 63) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT11_X(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_PIP_STAT11_X(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0040058ull) + ((offset) & 63) * 128;
+}
+#else
+#define CVMX_PIP_STAT11_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040058ull) + ((offset) & 63) * 128)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PIP_STAT1_PRTX(unsigned long offset)
 {
 	if (!(
@@ -290,7 +462,10 @@ static inline uint64_t CVMX_PIP_STAT1_PRTX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
 		cvmx_warn("CVMX_PIP_STAT1_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80;
 }
@@ -298,6 +473,17 @@ static inline uint64_t CVMX_PIP_STAT1_PRTX(unsigned long offset)
 #define CVMX_PIP_STAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT1_X(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_PIP_STAT1_X(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0040008ull) + ((offset) & 63) * 128;
+}
+#else
+#define CVMX_PIP_STAT1_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040008ull) + ((offset) & 63) * 128)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PIP_STAT2_PRTX(unsigned long offset)
 {
 	if (!(
@@ -308,7 +494,10 @@ static inline uint64_t CVMX_PIP_STAT2_PRTX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
 		cvmx_warn("CVMX_PIP_STAT2_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80;
 }
@@ -316,6 +505,17 @@ static inline uint64_t CVMX_PIP_STAT2_PRTX(unsigned long offset)
 #define CVMX_PIP_STAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT2_X(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_PIP_STAT2_X(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0040010ull) + ((offset) & 63) * 128;
+}
+#else
+#define CVMX_PIP_STAT2_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040010ull) + ((offset) & 63) * 128)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PIP_STAT3_PRTX(unsigned long offset)
 {
 	if (!(
@@ -326,7 +526,10 @@ static inline uint64_t CVMX_PIP_STAT3_PRTX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
 		cvmx_warn("CVMX_PIP_STAT3_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80;
 }
@@ -334,6 +537,17 @@ static inline uint64_t CVMX_PIP_STAT3_PRTX(unsigned long offset)
 #define CVMX_PIP_STAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT3_X(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_PIP_STAT3_X(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0040018ull) + ((offset) & 63) * 128;
+}
+#else
+#define CVMX_PIP_STAT3_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040018ull) + ((offset) & 63) * 128)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PIP_STAT4_PRTX(unsigned long offset)
 {
 	if (!(
@@ -344,7 +558,10 @@ static inline uint64_t CVMX_PIP_STAT4_PRTX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
 		cvmx_warn("CVMX_PIP_STAT4_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80;
 }
@@ -352,6 +569,17 @@ static inline uint64_t CVMX_PIP_STAT4_PRTX(unsigned long offset)
 #define CVMX_PIP_STAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT4_X(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_PIP_STAT4_X(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0040020ull) + ((offset) & 63) * 128;
+}
+#else
+#define CVMX_PIP_STAT4_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040020ull) + ((offset) & 63) * 128)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PIP_STAT5_PRTX(unsigned long offset)
 {
 	if (!(
@@ -362,7 +590,10 @@ static inline uint64_t CVMX_PIP_STAT5_PRTX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
 		cvmx_warn("CVMX_PIP_STAT5_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80;
 }
@@ -370,6 +601,17 @@ static inline uint64_t CVMX_PIP_STAT5_PRTX(unsigned long offset)
 #define CVMX_PIP_STAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT5_X(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_PIP_STAT5_X(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0040028ull) + ((offset) & 63) * 128;
+}
+#else
+#define CVMX_PIP_STAT5_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040028ull) + ((offset) & 63) * 128)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PIP_STAT6_PRTX(unsigned long offset)
 {
 	if (!(
@@ -380,7 +622,10 @@ static inline uint64_t CVMX_PIP_STAT6_PRTX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
 		cvmx_warn("CVMX_PIP_STAT6_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80;
 }
@@ -388,6 +633,17 @@ static inline uint64_t CVMX_PIP_STAT6_PRTX(unsigned long offset)
 #define CVMX_PIP_STAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT6_X(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_PIP_STAT6_X(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0040030ull) + ((offset) & 63) * 128;
+}
+#else
+#define CVMX_PIP_STAT6_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040030ull) + ((offset) & 63) * 128)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PIP_STAT7_PRTX(unsigned long offset)
 {
 	if (!(
@@ -398,7 +654,10 @@ static inline uint64_t CVMX_PIP_STAT7_PRTX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
 		cvmx_warn("CVMX_PIP_STAT7_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80;
 }
@@ -406,6 +665,17 @@ static inline uint64_t CVMX_PIP_STAT7_PRTX(unsigned long offset)
 #define CVMX_PIP_STAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT7_X(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_PIP_STAT7_X(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0040038ull) + ((offset) & 63) * 128;
+}
+#else
+#define CVMX_PIP_STAT7_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040038ull) + ((offset) & 63) * 128)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PIP_STAT8_PRTX(unsigned long offset)
 {
 	if (!(
@@ -416,7 +686,10 @@ static inline uint64_t CVMX_PIP_STAT8_PRTX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
 		cvmx_warn("CVMX_PIP_STAT8_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80;
 }
@@ -424,6 +697,17 @@ static inline uint64_t CVMX_PIP_STAT8_PRTX(unsigned long offset)
 #define CVMX_PIP_STAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT8_X(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_PIP_STAT8_X(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0040040ull) + ((offset) & 63) * 128;
+}
+#else
+#define CVMX_PIP_STAT8_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040040ull) + ((offset) & 63) * 128)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PIP_STAT9_PRTX(unsigned long offset)
 {
 	if (!(
@@ -434,13 +718,27 @@ static inline uint64_t CVMX_PIP_STAT9_PRTX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
 		cvmx_warn("CVMX_PIP_STAT9_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80;
 }
 #else
 #define CVMX_PIP_STAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80)
 #endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT9_X(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_PIP_STAT9_X(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0040048ull) + ((offset) & 63) * 128;
+}
+#else
+#define CVMX_PIP_STAT9_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040048ull) + ((offset) & 63) * 128)
+#endif
 #define CVMX_PIP_STAT_CTL (CVMX_ADD_IO_SEG(0x00011800A0000018ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PIP_STAT_INB_ERRSX(unsigned long offset)
@@ -453,7 +751,10 @@ static inline uint64_t CVMX_PIP_STAT_INB_ERRSX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
 		cvmx_warn("CVMX_PIP_STAT_INB_ERRSX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32;
 }
@@ -461,6 +762,17 @@ static inline uint64_t CVMX_PIP_STAT_INB_ERRSX(unsigned long offset)
 #define CVMX_PIP_STAT_INB_ERRSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT_INB_ERRS_PKNDX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_PIP_STAT_INB_ERRS_PKNDX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0020010ull) + ((offset) & 63) * 32;
+}
+#else
+#define CVMX_PIP_STAT_INB_ERRS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020010ull) + ((offset) & 63) * 32)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PIP_STAT_INB_OCTSX(unsigned long offset)
 {
 	if (!(
@@ -471,7 +783,10 @@ static inline uint64_t CVMX_PIP_STAT_INB_OCTSX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
 		cvmx_warn("CVMX_PIP_STAT_INB_OCTSX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32;
 }
@@ -479,6 +794,17 @@ static inline uint64_t CVMX_PIP_STAT_INB_OCTSX(unsigned long offset)
 #define CVMX_PIP_STAT_INB_OCTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT_INB_OCTS_PKNDX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_PIP_STAT_INB_OCTS_PKNDX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0020008ull) + ((offset) & 63) * 32;
+}
+#else
+#define CVMX_PIP_STAT_INB_OCTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020008ull) + ((offset) & 63) * 32)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PIP_STAT_INB_PKTSX(unsigned long offset)
 {
 	if (!(
@@ -489,7 +815,10 @@ static inline uint64_t CVMX_PIP_STAT_INB_PKTSX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
 		cvmx_warn("CVMX_PIP_STAT_INB_PKTSX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32;
 }
@@ -497,6 +826,28 @@ static inline uint64_t CVMX_PIP_STAT_INB_PKTSX(unsigned long offset)
 #define CVMX_PIP_STAT_INB_PKTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT_INB_PKTS_PKNDX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_PIP_STAT_INB_PKTS_PKNDX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0020000ull) + ((offset) & 63) * 32;
+}
+#else
+#define CVMX_PIP_STAT_INB_PKTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020000ull) + ((offset) & 63) * 32)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_SUB_PKIND_FCSX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_PIP_SUB_PKIND_FCSX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A0080000ull);
+}
+#else
+#define CVMX_PIP_SUB_PKIND_FCSX(block_id) (CVMX_ADD_IO_SEG(0x00011800A0080000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PIP_TAG_INCX(unsigned long offset)
 {
 	if (!(
@@ -507,7 +858,11 @@ static inline uint64_t CVMX_PIP_TAG_INCX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 63)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 63)))))
 		cvmx_warn("CVMX_PIP_TAG_INCX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8;
 }
@@ -518,10 +873,25 @@ static inline uint64_t CVMX_PIP_TAG_INCX(unsigned long offset)
 #define CVMX_PIP_TAG_SECRET (CVMX_ADD_IO_SEG(0x00011800A0000068ull))
 #define CVMX_PIP_TODO_ENTRY (CVMX_ADD_IO_SEG(0x00011800A0000078ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_VLAN_ETYPESX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_PIP_VLAN_ETYPESX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A00001C0ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_PIP_VLAN_ETYPESX(offset) (CVMX_ADD_IO_SEG(0x00011800A00001C0ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PIP_XSTAT0_PRTX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
 		cvmx_warn("CVMX_PIP_XSTAT0_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40;
 }
@@ -529,10 +899,35 @@ static inline uint64_t CVMX_PIP_XSTAT0_PRTX(unsigned long offset)
 #define CVMX_PIP_XSTAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_XSTAT10_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
+		cvmx_warn("CVMX_PIP_XSTAT10_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0001700ull) + ((offset) & 63) * 16 - 16*40;
+}
+#else
+#define CVMX_PIP_XSTAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001700ull) + ((offset) & 63) * 16 - 16*40)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_XSTAT11_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
+		cvmx_warn("CVMX_PIP_XSTAT11_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0001708ull) + ((offset) & 63) * 16 - 16*40;
+}
+#else
+#define CVMX_PIP_XSTAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001708ull) + ((offset) & 63) * 16 - 16*40)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_PIP_XSTAT1_PRTX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
 		cvmx_warn("CVMX_PIP_XSTAT1_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40;
 }
@@ -543,7 +938,8 @@ static inline uint64_t CVMX_PIP_XSTAT1_PRTX(unsigned long offset)
 static inline uint64_t CVMX_PIP_XSTAT2_PRTX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
 		cvmx_warn("CVMX_PIP_XSTAT2_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40;
 }
@@ -554,7 +950,8 @@ static inline uint64_t CVMX_PIP_XSTAT2_PRTX(unsigned long offset)
 static inline uint64_t CVMX_PIP_XSTAT3_PRTX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
 		cvmx_warn("CVMX_PIP_XSTAT3_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40;
 }
@@ -565,7 +962,8 @@ static inline uint64_t CVMX_PIP_XSTAT3_PRTX(unsigned long offset)
 static inline uint64_t CVMX_PIP_XSTAT4_PRTX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
 		cvmx_warn("CVMX_PIP_XSTAT4_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40;
 }
@@ -576,7 +974,8 @@ static inline uint64_t CVMX_PIP_XSTAT4_PRTX(unsigned long offset)
 static inline uint64_t CVMX_PIP_XSTAT5_PRTX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
 		cvmx_warn("CVMX_PIP_XSTAT5_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40;
 }
@@ -587,7 +986,8 @@ static inline uint64_t CVMX_PIP_XSTAT5_PRTX(unsigned long offset)
 static inline uint64_t CVMX_PIP_XSTAT6_PRTX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
 		cvmx_warn("CVMX_PIP_XSTAT6_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40;
 }
@@ -598,7 +998,8 @@ static inline uint64_t CVMX_PIP_XSTAT6_PRTX(unsigned long offset)
 static inline uint64_t CVMX_PIP_XSTAT7_PRTX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
 		cvmx_warn("CVMX_PIP_XSTAT7_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40;
 }
@@ -609,7 +1010,8 @@ static inline uint64_t CVMX_PIP_XSTAT7_PRTX(unsigned long offset)
 static inline uint64_t CVMX_PIP_XSTAT8_PRTX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
 		cvmx_warn("CVMX_PIP_XSTAT8_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40;
 }
@@ -620,7 +1022,8 @@ static inline uint64_t CVMX_PIP_XSTAT8_PRTX(unsigned long offset)
 static inline uint64_t CVMX_PIP_XSTAT9_PRTX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
 		cvmx_warn("CVMX_PIP_XSTAT9_PRTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40;
 }
@@ -629,18 +1032,76 @@ static inline uint64_t CVMX_PIP_XSTAT9_PRTX(unsigned long offset)
 #endif
 
 /**
+ * cvmx_pip_alt_skip_cfg#
+ *
+ * Notes:
+ * The actual SKIP I determined by HW is based on the packet contents.  BIT0 and
+ * BIT1 make up a two value value that the selects the skip value as follows.
+ *
+ *    lookup_value = LEN ? ( packet_in_bits[BIT1], packet_in_bits[BIT0] ) : ( 0, packet_in_bits[BIT0] );
+ *    SKIP I       = lookup_value == 3 ? SKIP3 :
+ *                   lookup_value == 2 ? SKIP2 :
+ *                   lookup_value == 1 ? SKIP1 :
+ *                   PIP_PRT_CFG<pknd>[SKIP];
+ */
+union cvmx_pip_alt_skip_cfgx {
+	uint64_t u64;
+	struct cvmx_pip_alt_skip_cfgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_57_63               : 7;
+	uint64_t len                          : 1;  /**< Indicates the length of the selection field
+                                                         0 = 0,    BIT0
+                                                         1 = BIT1, BIT0 */
+	uint64_t reserved_46_55               : 10;
+	uint64_t bit1                         : 6;  /**< Indicates the bit location in the first word of
+                                                         the packet to use to select the skip amount.
+                                                         BIT1 must be present in the packet. */
+	uint64_t reserved_38_39               : 2;
+	uint64_t bit0                         : 6;  /**< Indicates the bit location in the first word of
+                                                         the packet to use to select the skip amount.
+                                                         BIT0 must be present in the packet. */
+	uint64_t reserved_23_31               : 9;
+	uint64_t skip3                        : 7;  /**< Indicates number of bytes to skip from start of
+                                                         packet 0-64 */
+	uint64_t reserved_15_15               : 1;
+	uint64_t skip2                        : 7;  /**< Indicates number of bytes to skip from start of
+                                                         packet 0-64 */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t skip1                        : 7;  /**< Indicates number of bytes to skip from start of
+                                                         packet 0-64 */
+#else
+	uint64_t skip1                        : 7;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t skip2                        : 7;
+	uint64_t reserved_15_15               : 1;
+	uint64_t skip3                        : 7;
+	uint64_t reserved_23_31               : 9;
+	uint64_t bit0                         : 6;
+	uint64_t reserved_38_39               : 2;
+	uint64_t bit1                         : 6;
+	uint64_t reserved_46_55               : 10;
+	uint64_t len                          : 1;
+	uint64_t reserved_57_63               : 7;
+#endif
+	} s;
+	struct cvmx_pip_alt_skip_cfgx_s       cn61xx;
+	struct cvmx_pip_alt_skip_cfgx_s       cn66xx;
+	struct cvmx_pip_alt_skip_cfgx_s       cn68xx;
+	struct cvmx_pip_alt_skip_cfgx_s       cnf71xx;
+};
+typedef union cvmx_pip_alt_skip_cfgx cvmx_pip_alt_skip_cfgx_t;
+
+/**
  * cvmx_pip_bck_prs
  *
  * PIP_BCK_PRS = PIP's Back Pressure Register
  *
  * When to assert backpressure based on the todo list filling up
  */
-union cvmx_pip_bck_prs
-{
+union cvmx_pip_bck_prs {
 	uint64_t u64;
-	struct cvmx_pip_bck_prs_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_bck_prs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bckprs                       : 1;  /**< PIP is currently asserting backpressure to IOB
                                                          Backpressure from PIP will assert when the
                                                          entries to the todo list exceed HIWATER.
@@ -667,8 +1128,13 @@ union cvmx_pip_bck_prs
 	struct cvmx_pip_bck_prs_s             cn56xxp1;
 	struct cvmx_pip_bck_prs_s             cn58xx;
 	struct cvmx_pip_bck_prs_s             cn58xxp1;
+	struct cvmx_pip_bck_prs_s             cn61xx;
 	struct cvmx_pip_bck_prs_s             cn63xx;
 	struct cvmx_pip_bck_prs_s             cn63xxp1;
+	struct cvmx_pip_bck_prs_s             cn66xx;
+	struct cvmx_pip_bck_prs_s             cn68xx;
+	struct cvmx_pip_bck_prs_s             cn68xxp1;
+	struct cvmx_pip_bck_prs_s             cnf71xx;
 };
 typedef union cvmx_pip_bck_prs cvmx_pip_bck_prs_t;
 
@@ -678,12 +1144,21 @@ typedef union cvmx_pip_bck_prs cvmx_pip_bck_prs_t;
  * PIP_BIST_STATUS = PIP's BIST Results
  *
  */
-union cvmx_pip_bist_status
-{
+union cvmx_pip_bist_status {
 	uint64_t u64;
-	struct cvmx_pip_bist_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_22_63               : 42;
+	uint64_t bist                         : 22; /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         BIST. */
+#else
+	uint64_t bist                         : 22;
+	uint64_t reserved_22_63               : 42;
+#endif
+	} s;
+	struct cvmx_pip_bist_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t bist                         : 18; /**< BIST Results.
                                                          HW sets a bit in BIST for for memory that fails
@@ -692,14 +1167,12 @@ union cvmx_pip_bist_status
 	uint64_t bist                         : 18;
 	uint64_t reserved_18_63               : 46;
 #endif
-	} s;
-	struct cvmx_pip_bist_status_s         cn30xx;
-	struct cvmx_pip_bist_status_s         cn31xx;
-	struct cvmx_pip_bist_status_s         cn38xx;
-	struct cvmx_pip_bist_status_s         cn38xxp2;
-	struct cvmx_pip_bist_status_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	} cn30xx;
+	struct cvmx_pip_bist_status_cn30xx    cn31xx;
+	struct cvmx_pip_bist_status_cn30xx    cn38xx;
+	struct cvmx_pip_bist_status_cn30xx    cn38xxp2;
+	struct cvmx_pip_bist_status_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t bist                         : 17; /**< BIST Results.
                                                          HW sets a bit in BIST for for memory that fails
@@ -709,26 +1182,226 @@ union cvmx_pip_bist_status
 	uint64_t reserved_17_63               : 47;
 #endif
 	} cn50xx;
-	struct cvmx_pip_bist_status_s         cn52xx;
-	struct cvmx_pip_bist_status_s         cn52xxp1;
-	struct cvmx_pip_bist_status_s         cn56xx;
-	struct cvmx_pip_bist_status_s         cn56xxp1;
-	struct cvmx_pip_bist_status_s         cn58xx;
-	struct cvmx_pip_bist_status_s         cn58xxp1;
-	struct cvmx_pip_bist_status_s         cn63xx;
-	struct cvmx_pip_bist_status_s         cn63xxp1;
+	struct cvmx_pip_bist_status_cn30xx    cn52xx;
+	struct cvmx_pip_bist_status_cn30xx    cn52xxp1;
+	struct cvmx_pip_bist_status_cn30xx    cn56xx;
+	struct cvmx_pip_bist_status_cn30xx    cn56xxp1;
+	struct cvmx_pip_bist_status_cn30xx    cn58xx;
+	struct cvmx_pip_bist_status_cn30xx    cn58xxp1;
+	struct cvmx_pip_bist_status_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t bist                         : 20; /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         BIST. */
+#else
+	uint64_t bist                         : 20;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn61xx;
+	struct cvmx_pip_bist_status_cn30xx    cn63xx;
+	struct cvmx_pip_bist_status_cn30xx    cn63xxp1;
+	struct cvmx_pip_bist_status_cn61xx    cn66xx;
+	struct cvmx_pip_bist_status_s         cn68xx;
+	struct cvmx_pip_bist_status_cn61xx    cn68xxp1;
+	struct cvmx_pip_bist_status_cn61xx    cnf71xx;
 };
 typedef union cvmx_pip_bist_status cvmx_pip_bist_status_t;
 
 /**
+ * cvmx_pip_bsel_ext_cfg#
+ *
+ * PIP_BSEL_EXT_CFGX = Bit Select Extractor config register containing the
+ * tag, offset, and skip values to be used when using the corresponding extractor.
+ */
+union cvmx_pip_bsel_ext_cfgx {
+	uint64_t u64;
+	struct cvmx_pip_bsel_ext_cfgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t upper_tag                    : 16; /**< Extra Tag bits to be added to tag field from table
+                                                         Only included when PIP_PRT_TAG[INC_PRT]=0
+                                                         WORD2[TAG<31:16>] */
+	uint64_t tag                          : 8;  /**< Extra Tag bits to be added to tag field from table
+                                                         WORD2[TAG<15:8>] */
+	uint64_t reserved_25_31               : 7;
+	uint64_t offset                       : 9;  /**< Indicates offset to add to extractor mem adr
+                                                         to get final address to the lookup table */
+	uint64_t reserved_7_15                : 9;
+	uint64_t skip                         : 7;  /**< Indicates number of bytes to skip from start of
+                                                         packet 0-64 */
+#else
+	uint64_t skip                         : 7;
+	uint64_t reserved_7_15                : 9;
+	uint64_t offset                       : 9;
+	uint64_t reserved_25_31               : 7;
+	uint64_t tag                          : 8;
+	uint64_t upper_tag                    : 16;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_pip_bsel_ext_cfgx_s       cn61xx;
+	struct cvmx_pip_bsel_ext_cfgx_s       cn68xx;
+	struct cvmx_pip_bsel_ext_cfgx_s       cnf71xx;
+};
+typedef union cvmx_pip_bsel_ext_cfgx cvmx_pip_bsel_ext_cfgx_t;
+
+/**
+ * cvmx_pip_bsel_ext_pos#
+ *
+ * PIP_BSEL_EXT_POSX = Bit Select Extractor config register containing the 8
+ * bit positions and valids to be used when using the corresponding extractor.
+ *
+ * Notes:
+ * Examples on bit positioning:
+ *   the most-significant-bit of the 3rd byte         ... PIP_BSEL_EXT_CFG*[SKIP]=1 POSn=15 (decimal) or
+ *                                                        PIP_BSEL_EXT_CFG*[SKIP]=0 POSn=23 (decimal)
+ *   the least-significant-bit of the 5th byte        ... PIP_BSEL_EXT_CFG*[SKIP]=4 POSn=0
+ *   the second-least-significant bit of the 1st byte ... PIP_BSEL_EXT_CFG*[SKIP]=0 POSn=1
+ *
+ * POSn_VAL and POSn correspond to <n> in the resultant index into
+ * PIP_BSEL_TBL_ENT. When only x bits (0 < x < 7) are to be extracted,
+ * POS[7:x] should normally be clear.
+ */
+union cvmx_pip_bsel_ext_posx {
+	uint64_t u64;
+	struct cvmx_pip_bsel_ext_posx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t pos7_val                     : 1;  /**< Valid bit for bit position 7 */
+	uint64_t pos7                         : 7;  /**< Bit position for the 8th bit  from 128 bit segment
+                                                         of pkt that is defined by the SKIP field of
+                                                         PIP_BSEL_EXT_CFG register. */
+	uint64_t pos6_val                     : 1;  /**< Valid bit for bit position 6 */
+	uint64_t pos6                         : 7;  /**< Bit position for the 7th bit  from 128 bit segment
+                                                         of pkt that is defined by the SKIP field of
+                                                         PIP_BSEL_EXT_CFG register. */
+	uint64_t pos5_val                     : 1;  /**< Valid bit for bit position 5 */
+	uint64_t pos5                         : 7;  /**< Bit position for the 6th bit  from 128 bit segment
+                                                         of pkt that is defined by the SKIP field of
+                                                         PIP_BSEL_EXT_CFG register. */
+	uint64_t pos4_val                     : 1;  /**< Valid bit for bit position 4 */
+	uint64_t pos4                         : 7;  /**< Bit position for the 5th bit  from 128 bit segment
+                                                         of pkt that is defined by the SKIP field of
+                                                         PIP_BSEL_EXT_CFG register. */
+	uint64_t pos3_val                     : 1;  /**< Valid bit for bit position 3 */
+	uint64_t pos3                         : 7;  /**< Bit position for the 4th bit  from 128 bit segment
+                                                         of pkt that is defined by the SKIP field of
+                                                         PIP_BSEL_EXT_CFG register. */
+	uint64_t pos2_val                     : 1;  /**< Valid bit for bit position 2 */
+	uint64_t pos2                         : 7;  /**< Bit position for the 3rd bit  from 128 bit segment
+                                                         of pkt that is defined by the SKIP field of
+                                                         PIP_BSEL_EXT_CFG register. */
+	uint64_t pos1_val                     : 1;  /**< Valid bit for bit position 1 */
+	uint64_t pos1                         : 7;  /**< Bit position for the 2nd bit  from 128 bit segment
+                                                         of pkt that is defined by the SKIP field of
+                                                         PIP_BSEL_EXT_CFG register. */
+	uint64_t pos0_val                     : 1;  /**< Valid bit for bit position 0 */
+	uint64_t pos0                         : 7;  /**< Bit position for the 1st bit  from 128 bit segment
+                                                         of pkt that is defined by the SKIP field of
+                                                         PIP_BSEL_EXT_CFG register. */
+#else
+	uint64_t pos0                         : 7;
+	uint64_t pos0_val                     : 1;
+	uint64_t pos1                         : 7;
+	uint64_t pos1_val                     : 1;
+	uint64_t pos2                         : 7;
+	uint64_t pos2_val                     : 1;
+	uint64_t pos3                         : 7;
+	uint64_t pos3_val                     : 1;
+	uint64_t pos4                         : 7;
+	uint64_t pos4_val                     : 1;
+	uint64_t pos5                         : 7;
+	uint64_t pos5_val                     : 1;
+	uint64_t pos6                         : 7;
+	uint64_t pos6_val                     : 1;
+	uint64_t pos7                         : 7;
+	uint64_t pos7_val                     : 1;
+#endif
+	} s;
+	struct cvmx_pip_bsel_ext_posx_s       cn61xx;
+	struct cvmx_pip_bsel_ext_posx_s       cn68xx;
+	struct cvmx_pip_bsel_ext_posx_s       cnf71xx;
+};
+typedef union cvmx_pip_bsel_ext_posx cvmx_pip_bsel_ext_posx_t;
+
+/**
+ * cvmx_pip_bsel_tbl_ent#
+ *
+ * PIP_BSEL_TBL_ENTX = Entry for the extractor table
+ *
+ */
+union cvmx_pip_bsel_tbl_entx {
+	uint64_t u64;
+	struct cvmx_pip_bsel_tbl_entx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t tag_en                       : 1;  /**< Enables the use of the TAG field */
+	uint64_t grp_en                       : 1;  /**< Enables the use of the GRP field */
+	uint64_t tt_en                        : 1;  /**< Enables the use of the TT field */
+	uint64_t qos_en                       : 1;  /**< Enables the use of the QOS field */
+	uint64_t reserved_40_59               : 20;
+	uint64_t tag                          : 8;  /**< TAG bits to be used if TAG_EN is set */
+	uint64_t reserved_22_31               : 10;
+	uint64_t grp                          : 6;  /**< GRP field to be used if GRP_EN is set */
+	uint64_t reserved_10_15               : 6;
+	uint64_t tt                           : 2;  /**< TT field to be used if TT_EN is set */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t qos                          : 3;  /**< QOS field to be used if QOS_EN is set */
+#else
+	uint64_t qos                          : 3;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t tt                           : 2;
+	uint64_t reserved_10_15               : 6;
+	uint64_t grp                          : 6;
+	uint64_t reserved_22_31               : 10;
+	uint64_t tag                          : 8;
+	uint64_t reserved_40_59               : 20;
+	uint64_t qos_en                       : 1;
+	uint64_t tt_en                        : 1;
+	uint64_t grp_en                       : 1;
+	uint64_t tag_en                       : 1;
+#endif
+	} s;
+	struct cvmx_pip_bsel_tbl_entx_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t tag_en                       : 1;  /**< Enables the use of the TAG field */
+	uint64_t grp_en                       : 1;  /**< Enables the use of the GRP field */
+	uint64_t tt_en                        : 1;  /**< Enables the use of the TT field */
+	uint64_t qos_en                       : 1;  /**< Enables the use of the QOS field */
+	uint64_t reserved_40_59               : 20;
+	uint64_t tag                          : 8;  /**< TAG bits to be used if TAG_EN is set */
+	uint64_t reserved_20_31               : 12;
+	uint64_t grp                          : 4;  /**< GRP field to be used if GRP_EN is set */
+	uint64_t reserved_10_15               : 6;
+	uint64_t tt                           : 2;  /**< TT field to be used if TT_EN is set */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t qos                          : 3;  /**< QOS field to be used if QOS_EN is set */
+#else
+	uint64_t qos                          : 3;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t tt                           : 2;
+	uint64_t reserved_10_15               : 6;
+	uint64_t grp                          : 4;
+	uint64_t reserved_20_31               : 12;
+	uint64_t tag                          : 8;
+	uint64_t reserved_40_59               : 20;
+	uint64_t qos_en                       : 1;
+	uint64_t tt_en                        : 1;
+	uint64_t grp_en                       : 1;
+	uint64_t tag_en                       : 1;
+#endif
+	} cn61xx;
+	struct cvmx_pip_bsel_tbl_entx_s       cn68xx;
+	struct cvmx_pip_bsel_tbl_entx_cn61xx  cnf71xx;
+};
+typedef union cvmx_pip_bsel_tbl_entx cvmx_pip_bsel_tbl_entx_t;
+
+/**
  * cvmx_pip_clken
  */
-union cvmx_pip_clken
-{
+union cvmx_pip_clken {
 	uint64_t u64;
-	struct cvmx_pip_clken_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_clken_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t clken                        : 1;  /**< Controls the conditional clocking within PIP
                                                          0=Allow HW to control the clocks
@@ -738,8 +1411,13 @@ union cvmx_pip_clken
 	uint64_t reserved_1_63                : 63;
 #endif
 	} s;
+	struct cvmx_pip_clken_s               cn61xx;
 	struct cvmx_pip_clken_s               cn63xx;
 	struct cvmx_pip_clken_s               cn63xxp1;
+	struct cvmx_pip_clken_s               cn66xx;
+	struct cvmx_pip_clken_s               cn68xx;
+	struct cvmx_pip_clken_s               cn68xxp1;
+	struct cvmx_pip_clken_s               cnf71xx;
 };
 typedef union cvmx_pip_clken cvmx_pip_clken_t;
 
@@ -750,12 +1428,10 @@ typedef union cvmx_pip_clken cvmx_pip_clken_t;
  *
  * Controls datapath reflection when calculating CRC
  */
-union cvmx_pip_crc_ctlx
-{
+union cvmx_pip_crc_ctlx {
 	uint64_t u64;
-	struct cvmx_pip_crc_ctlx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_crc_ctlx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t invres                       : 1;  /**< Invert the result */
 	uint64_t reflect                      : 1;  /**< Reflect the bits in each byte.
@@ -811,12 +1487,10 @@ typedef union cvmx_pip_crc_ctlx cvmx_pip_crc_ctlx_t;
  *    return current_val;
  *  ]
  */
-union cvmx_pip_crc_ivx
-{
+union cvmx_pip_crc_ivx {
 	uint64_t u64;
-	struct cvmx_pip_crc_ivx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_crc_ivx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t iv                           : 32; /**< IV used by the CRC algorithm.  Default is FCS32. */
 #else
@@ -838,12 +1512,10 @@ typedef union cvmx_pip_crc_ivx cvmx_pip_crc_ivx_t;
  *
  * PIP sets the dec_ipsec based on TCP or UDP destination port.
  */
-union cvmx_pip_dec_ipsecx
-{
+union cvmx_pip_dec_ipsecx {
 	uint64_t u64;
-	struct cvmx_pip_dec_ipsecx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_dec_ipsecx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t tcp                          : 1;  /**< This DPRT should be used for TCP packets */
 	uint64_t udp                          : 1;  /**< This DPRT should be used for UDP packets */
@@ -866,20 +1538,23 @@ union cvmx_pip_dec_ipsecx
 	struct cvmx_pip_dec_ipsecx_s          cn56xxp1;
 	struct cvmx_pip_dec_ipsecx_s          cn58xx;
 	struct cvmx_pip_dec_ipsecx_s          cn58xxp1;
+	struct cvmx_pip_dec_ipsecx_s          cn61xx;
 	struct cvmx_pip_dec_ipsecx_s          cn63xx;
 	struct cvmx_pip_dec_ipsecx_s          cn63xxp1;
+	struct cvmx_pip_dec_ipsecx_s          cn66xx;
+	struct cvmx_pip_dec_ipsecx_s          cn68xx;
+	struct cvmx_pip_dec_ipsecx_s          cn68xxp1;
+	struct cvmx_pip_dec_ipsecx_s          cnf71xx;
 };
 typedef union cvmx_pip_dec_ipsecx cvmx_pip_dec_ipsecx_t;
 
 /**
  * cvmx_pip_dsa_src_grp
  */
-union cvmx_pip_dsa_src_grp
-{
+union cvmx_pip_dsa_src_grp {
 	uint64_t u64;
-	struct cvmx_pip_dsa_src_grp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_dsa_src_grp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t map15                        : 4;  /**< DSA Group Algorithm */
 	uint64_t map14                        : 4;  /**< DSA Group Algorithm */
 	uint64_t map13                        : 4;  /**< DSA Group Algorithm */
@@ -919,20 +1594,23 @@ union cvmx_pip_dsa_src_grp
 	struct cvmx_pip_dsa_src_grp_s         cn52xx;
 	struct cvmx_pip_dsa_src_grp_s         cn52xxp1;
 	struct cvmx_pip_dsa_src_grp_s         cn56xx;
+	struct cvmx_pip_dsa_src_grp_s         cn61xx;
 	struct cvmx_pip_dsa_src_grp_s         cn63xx;
 	struct cvmx_pip_dsa_src_grp_s         cn63xxp1;
+	struct cvmx_pip_dsa_src_grp_s         cn66xx;
+	struct cvmx_pip_dsa_src_grp_s         cn68xx;
+	struct cvmx_pip_dsa_src_grp_s         cn68xxp1;
+	struct cvmx_pip_dsa_src_grp_s         cnf71xx;
 };
 typedef union cvmx_pip_dsa_src_grp cvmx_pip_dsa_src_grp_t;
 
 /**
  * cvmx_pip_dsa_vid_grp
  */
-union cvmx_pip_dsa_vid_grp
-{
+union cvmx_pip_dsa_vid_grp {
 	uint64_t u64;
-	struct cvmx_pip_dsa_vid_grp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_dsa_vid_grp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t map15                        : 4;  /**< DSA Group Algorithm */
 	uint64_t map14                        : 4;  /**< DSA Group Algorithm */
 	uint64_t map13                        : 4;  /**< DSA Group Algorithm */
@@ -972,8 +1650,13 @@ union cvmx_pip_dsa_vid_grp
 	struct cvmx_pip_dsa_vid_grp_s         cn52xx;
 	struct cvmx_pip_dsa_vid_grp_s         cn52xxp1;
 	struct cvmx_pip_dsa_vid_grp_s         cn56xx;
+	struct cvmx_pip_dsa_vid_grp_s         cn61xx;
 	struct cvmx_pip_dsa_vid_grp_s         cn63xx;
 	struct cvmx_pip_dsa_vid_grp_s         cn63xxp1;
+	struct cvmx_pip_dsa_vid_grp_s         cn66xx;
+	struct cvmx_pip_dsa_vid_grp_s         cn68xx;
+	struct cvmx_pip_dsa_vid_grp_s         cn68xxp1;
+	struct cvmx_pip_dsa_vid_grp_s         cnf71xx;
 };
 typedef union cvmx_pip_dsa_vid_grp cvmx_pip_dsa_vid_grp_t;
 
@@ -984,12 +1667,10 @@ typedef union cvmx_pip_dsa_vid_grp cvmx_pip_dsa_vid_grp_t;
  * PIP_FRM_LEN_CHK0 is used for packets on packet interface0, PCI, PCI RAW, and PKO loopback ports.
  * PIP_FRM_LEN_CHK1 is unused.
  */
-union cvmx_pip_frm_len_chkx
-{
+union cvmx_pip_frm_len_chkx {
 	uint64_t u64;
-	struct cvmx_pip_frm_len_chkx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_frm_len_chkx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t maxlen                       : 16; /**< Byte count for Max-sized frame check
                                                          PIP_PRT_CFGn[MAXERR_EN] enables the check for
@@ -1027,8 +1708,13 @@ union cvmx_pip_frm_len_chkx
 	struct cvmx_pip_frm_len_chkx_s        cn52xxp1;
 	struct cvmx_pip_frm_len_chkx_s        cn56xx;
 	struct cvmx_pip_frm_len_chkx_s        cn56xxp1;
+	struct cvmx_pip_frm_len_chkx_s        cn61xx;
 	struct cvmx_pip_frm_len_chkx_s        cn63xx;
 	struct cvmx_pip_frm_len_chkx_s        cn63xxp1;
+	struct cvmx_pip_frm_len_chkx_s        cn66xx;
+	struct cvmx_pip_frm_len_chkx_s        cn68xx;
+	struct cvmx_pip_frm_len_chkx_s        cn68xxp1;
+	struct cvmx_pip_frm_len_chkx_s        cnf71xx;
 };
 typedef union cvmx_pip_frm_len_chkx cvmx_pip_frm_len_chkx_t;
 
@@ -1046,12 +1732,10 @@ typedef union cvmx_pip_frm_len_chkx cvmx_pip_frm_len_chkx_t;
  * bit allows the user to treat IPv6 as IPv4, meaning that the all 0's
  * pattern will cause a UDP checksum pass.
  */
-union cvmx_pip_gbl_cfg
-{
+union cvmx_pip_gbl_cfg {
 	uint64_t u64;
-	struct cvmx_pip_gbl_cfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_gbl_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t tag_syn                      : 1;  /**< Do not include src_crc for TCP/SYN&!ACK packets
                                                          0 = include src_crc
@@ -1093,8 +1777,13 @@ union cvmx_pip_gbl_cfg
 	struct cvmx_pip_gbl_cfg_s             cn56xxp1;
 	struct cvmx_pip_gbl_cfg_s             cn58xx;
 	struct cvmx_pip_gbl_cfg_s             cn58xxp1;
+	struct cvmx_pip_gbl_cfg_s             cn61xx;
 	struct cvmx_pip_gbl_cfg_s             cn63xx;
 	struct cvmx_pip_gbl_cfg_s             cn63xxp1;
+	struct cvmx_pip_gbl_cfg_s             cn66xx;
+	struct cvmx_pip_gbl_cfg_s             cn68xx;
+	struct cvmx_pip_gbl_cfg_s             cn68xxp1;
+	struct cvmx_pip_gbl_cfg_s             cnf71xx;
 };
 typedef union cvmx_pip_gbl_cfg cvmx_pip_gbl_cfg_t;
 
@@ -1176,13 +1865,14 @@ typedef union cvmx_pip_gbl_cfg cvmx_pip_gbl_cfg_t;
  *         6'bxxx11x: (RST+SYN+*)
  *         6'bxxxx11: (SYN+FIN+*)
  */
-union cvmx_pip_gbl_ctl
-{
+union cvmx_pip_gbl_ctl {
 	uint64_t u64;
-	struct cvmx_pip_gbl_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_28_63               : 36;
+	struct cvmx_pip_gbl_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_29_63               : 35;
+	uint64_t egrp_dis                     : 1;  /**< PKT_INST_HDR extended group field disable
+                                                         When set, HW will ignore the EGRP field of the
+                                                         PKT_INST_HDR - bits 47:46. */
 	uint64_t ihmsk_dis                    : 1;  /**< Instruction Header Mask Disable
                                                          0=Allow NTAG,NTT,NGRP,NQOS bits in the
                                                            instruction header to control which fields from
@@ -1200,10 +1890,10 @@ union cvmx_pip_gbl_ctl
 	uint64_t dsa_grp_sid                  : 1;  /**< DSA Group Algorithm
                                                          Use the DSA VLAN id to compute GRP */
 	uint64_t reserved_21_23               : 3;
-	uint64_t ring_en                      : 1;  /**< Enable PCIe ring information in WQE */
+	uint64_t ring_en                      : 1;  /**< Enable DPI ring information in WQE */
 	uint64_t reserved_17_19               : 3;
 	uint64_t ignrs                        : 1;  /**< Ignore the PKT_INST_HDR[RS] bit when set
-                                                         Does not apply to PCI ports (32-35)
+                                                         Does not apply to DPI ports (32-35)
                                                          When using 2-byte instruction header words,
                                                          either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */
 	uint64_t vs_wqe                       : 1;  /**< Which DSA/VLAN CFI/ID to use when VLAN Stacking
@@ -1247,12 +1937,12 @@ union cvmx_pip_gbl_ctl
 	uint64_t dsa_grp_scmd                 : 1;
 	uint64_t dsa_grp_tvid                 : 1;
 	uint64_t ihmsk_dis                    : 1;
-	uint64_t reserved_28_63               : 36;
+	uint64_t egrp_dis                     : 1;
+	uint64_t reserved_29_63               : 35;
 #endif
 	} s;
-	struct cvmx_pip_gbl_ctl_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_gbl_ctl_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t ignrs                        : 1;  /**< Ignore the PKT_INST_HDR[RS] bit when set
                                                          Only applies to the packet interface prts (0-31)
@@ -1299,9 +1989,8 @@ union cvmx_pip_gbl_ctl
 	struct cvmx_pip_gbl_ctl_cn30xx        cn38xx;
 	struct cvmx_pip_gbl_ctl_cn30xx        cn38xxp2;
 	struct cvmx_pip_gbl_ctl_cn30xx        cn50xx;
-	struct cvmx_pip_gbl_ctl_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_gbl_ctl_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_27_63               : 37;
 	uint64_t dsa_grp_tvid                 : 1;  /**< DSA Group Algorithm
                                                          Use the DSA source id to compute GRP */
@@ -1362,9 +2051,8 @@ union cvmx_pip_gbl_ctl
 	} cn52xx;
 	struct cvmx_pip_gbl_ctl_cn52xx        cn52xxp1;
 	struct cvmx_pip_gbl_ctl_cn52xx        cn56xx;
-	struct cvmx_pip_gbl_ctl_cn56xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_gbl_ctl_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_21_63               : 43;
 	uint64_t ring_en                      : 1;  /**< Enable PCIe ring information in WQE */
 	uint64_t reserved_17_19               : 3;
@@ -1413,8 +2101,214 @@ union cvmx_pip_gbl_ctl
 	} cn56xxp1;
 	struct cvmx_pip_gbl_ctl_cn30xx        cn58xx;
 	struct cvmx_pip_gbl_ctl_cn30xx        cn58xxp1;
-	struct cvmx_pip_gbl_ctl_s             cn63xx;
-	struct cvmx_pip_gbl_ctl_s             cn63xxp1;
+	struct cvmx_pip_gbl_ctl_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_28_63               : 36;
+	uint64_t ihmsk_dis                    : 1;  /**< Instruction Header Mask Disable
+                                                         0=Allow NTAG,NTT,NGRP,NQOS bits in the
+                                                           instruction header to control which fields from
+                                                           the instruction header are used for WQE WORD2.
+                                                         1=Ignore the NTAG,NTT,NGRP,NQOS bits in the
+                                                           instruction header and act as if these fields
+                                                           were zero.  Thus always use the TAG,TT,GRP,QOS
+                                                           (depending on the instruction header length)
+                                                           from the instruction header for the WQE WORD2. */
+	uint64_t dsa_grp_tvid                 : 1;  /**< DSA Group Algorithm
+                                                         Use the DSA source id to compute GRP */
+	uint64_t dsa_grp_scmd                 : 1;  /**< DSA Group Algorithm
+                                                         Use the DSA source id to compute GRP when the
+                                                         DSA tag command to TO_CPU */
+	uint64_t dsa_grp_sid                  : 1;  /**< DSA Group Algorithm
+                                                         Use the DSA VLAN id to compute GRP */
+	uint64_t reserved_21_23               : 3;
+	uint64_t ring_en                      : 1;  /**< Enable DPI ring information in WQE */
+	uint64_t reserved_17_19               : 3;
+	uint64_t ignrs                        : 1;  /**< Ignore the PKT_INST_HDR[RS] bit when set
+                                                         Does not apply to DPI ports (32-35)
+                                                         When using 2-byte instruction header words,
+                                                         either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */
+	uint64_t vs_wqe                       : 1;  /**< Which DSA/VLAN CFI/ID to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN */
+	uint64_t vs_qos                       : 1;  /**< Which DSA/VLAN priority to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN */
+	uint64_t l2_mal                       : 1;  /**< Enable L2 malformed packet check */
+	uint64_t tcp_flag                     : 1;  /**< Enable TCP flags checks */
+	uint64_t l4_len                       : 1;  /**< Enable TCP/UDP length check */
+	uint64_t l4_chk                       : 1;  /**< Enable TCP/UDP checksum check */
+	uint64_t l4_prt                       : 1;  /**< Enable TCP/UDP illegal port check */
+	uint64_t l4_mal                       : 1;  /**< Enable TCP/UDP malformed packet check */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ip6_eext                     : 2;  /**< Enable IPv6 early extension headers */
+	uint64_t ip4_opts                     : 1;  /**< Enable IPv4 options check */
+	uint64_t ip_hop                       : 1;  /**< Enable TTL (IPv4) / hop (IPv6) check */
+	uint64_t ip_mal                       : 1;  /**< Enable malformed check */
+	uint64_t ip_chk                       : 1;  /**< Enable IPv4 header checksum check */
+#else
+	uint64_t ip_chk                       : 1;
+	uint64_t ip_mal                       : 1;
+	uint64_t ip_hop                       : 1;
+	uint64_t ip4_opts                     : 1;
+	uint64_t ip6_eext                     : 2;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t l4_mal                       : 1;
+	uint64_t l4_prt                       : 1;
+	uint64_t l4_chk                       : 1;
+	uint64_t l4_len                       : 1;
+	uint64_t tcp_flag                     : 1;
+	uint64_t l2_mal                       : 1;
+	uint64_t vs_qos                       : 1;
+	uint64_t vs_wqe                       : 1;
+	uint64_t ignrs                        : 1;
+	uint64_t reserved_17_19               : 3;
+	uint64_t ring_en                      : 1;
+	uint64_t reserved_21_23               : 3;
+	uint64_t dsa_grp_sid                  : 1;
+	uint64_t dsa_grp_scmd                 : 1;
+	uint64_t dsa_grp_tvid                 : 1;
+	uint64_t ihmsk_dis                    : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn61xx;
+	struct cvmx_pip_gbl_ctl_cn61xx        cn63xx;
+	struct cvmx_pip_gbl_ctl_cn61xx        cn63xxp1;
+	struct cvmx_pip_gbl_ctl_cn61xx        cn66xx;
+	struct cvmx_pip_gbl_ctl_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_29_63               : 35;
+	uint64_t egrp_dis                     : 1;  /**< PKT_INST_HDR extended group field disable
+                                                         When set, HW will ignore the EGRP field of the
+                                                         PKT_INST_HDR - bits 47:46. */
+	uint64_t ihmsk_dis                    : 1;  /**< Instruction Header Mask Disable
+                                                         0=Allow NTAG,NTT,NGRP,NQOS bits in the
+                                                           instruction header to control which fields from
+                                                           the instruction header are used for WQE WORD2.
+                                                         1=Ignore the NTAG,NTT,NGRP,NQOS bits in the
+                                                           instruction header and act as if these fields
+                                                           were zero.  Thus always use the TAG,TT,GRP,QOS
+                                                           (depending on the instruction header length)
+                                                           from the instruction header for the WQE WORD2. */
+	uint64_t dsa_grp_tvid                 : 1;  /**< DSA Group Algorithm
+                                                         Use the DSA source id to compute GRP */
+	uint64_t dsa_grp_scmd                 : 1;  /**< DSA Group Algorithm
+                                                         Use the DSA source id to compute GRP when the
+                                                         DSA tag command to TO_CPU */
+	uint64_t dsa_grp_sid                  : 1;  /**< DSA Group Algorithm
+                                                         Use the DSA VLAN id to compute GRP */
+	uint64_t reserved_17_23               : 7;
+	uint64_t ignrs                        : 1;  /**< Ignore the PKT_INST_HDR[RS] bit when set
+                                                         When using 2-byte instruction header words,
+                                                         either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */
+	uint64_t vs_wqe                       : 1;  /**< Which DSA/VLAN CFI/ID to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN */
+	uint64_t vs_qos                       : 1;  /**< Which DSA/VLAN priority to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN */
+	uint64_t l2_mal                       : 1;  /**< Enable L2 malformed packet check */
+	uint64_t tcp_flag                     : 1;  /**< Enable TCP flags checks */
+	uint64_t l4_len                       : 1;  /**< Enable TCP/UDP length check */
+	uint64_t l4_chk                       : 1;  /**< Enable TCP/UDP checksum check */
+	uint64_t l4_prt                       : 1;  /**< Enable TCP/UDP illegal port check */
+	uint64_t l4_mal                       : 1;  /**< Enable TCP/UDP malformed packet check */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ip6_eext                     : 2;  /**< Enable IPv6 early extension headers */
+	uint64_t ip4_opts                     : 1;  /**< Enable IPv4 options check */
+	uint64_t ip_hop                       : 1;  /**< Enable TTL (IPv4) / hop (IPv6) check */
+	uint64_t ip_mal                       : 1;  /**< Enable malformed check */
+	uint64_t ip_chk                       : 1;  /**< Enable IPv4 header checksum check */
+#else
+	uint64_t ip_chk                       : 1;
+	uint64_t ip_mal                       : 1;
+	uint64_t ip_hop                       : 1;
+	uint64_t ip4_opts                     : 1;
+	uint64_t ip6_eext                     : 2;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t l4_mal                       : 1;
+	uint64_t l4_prt                       : 1;
+	uint64_t l4_chk                       : 1;
+	uint64_t l4_len                       : 1;
+	uint64_t tcp_flag                     : 1;
+	uint64_t l2_mal                       : 1;
+	uint64_t vs_qos                       : 1;
+	uint64_t vs_wqe                       : 1;
+	uint64_t ignrs                        : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t dsa_grp_sid                  : 1;
+	uint64_t dsa_grp_scmd                 : 1;
+	uint64_t dsa_grp_tvid                 : 1;
+	uint64_t ihmsk_dis                    : 1;
+	uint64_t egrp_dis                     : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn68xx;
+	struct cvmx_pip_gbl_ctl_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_28_63               : 36;
+	uint64_t ihmsk_dis                    : 1;  /**< Instruction Header Mask Disable
+                                                         0=Allow NTAG,NTT,NGRP,NQOS bits in the
+                                                           instruction header to control which fields from
+                                                           the instruction header are used for WQE WORD2.
+                                                         1=Ignore the NTAG,NTT,NGRP,NQOS bits in the
+                                                           instruction header and act as if these fields
+                                                           were zero.  Thus always use the TAG,TT,GRP,QOS
+                                                           (depending on the instruction header length)
+                                                           from the instruction header for the WQE WORD2. */
+	uint64_t dsa_grp_tvid                 : 1;  /**< DSA Group Algorithm
+                                                         Use the DSA source id to compute GRP */
+	uint64_t dsa_grp_scmd                 : 1;  /**< DSA Group Algorithm
+                                                         Use the DSA source id to compute GRP when the
+                                                         DSA tag command to TO_CPU */
+	uint64_t dsa_grp_sid                  : 1;  /**< DSA Group Algorithm
+                                                         Use the DSA VLAN id to compute GRP */
+	uint64_t reserved_17_23               : 7;
+	uint64_t ignrs                        : 1;  /**< Ignore the PKT_INST_HDR[RS] bit when set
+                                                         When using 2-byte instruction header words,
+                                                         either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */
+	uint64_t vs_wqe                       : 1;  /**< Which DSA/VLAN CFI/ID to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN */
+	uint64_t vs_qos                       : 1;  /**< Which DSA/VLAN priority to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN */
+	uint64_t l2_mal                       : 1;  /**< Enable L2 malformed packet check */
+	uint64_t tcp_flag                     : 1;  /**< Enable TCP flags checks */
+	uint64_t l4_len                       : 1;  /**< Enable TCP/UDP length check */
+	uint64_t l4_chk                       : 1;  /**< Enable TCP/UDP checksum check */
+	uint64_t l4_prt                       : 1;  /**< Enable TCP/UDP illegal port check */
+	uint64_t l4_mal                       : 1;  /**< Enable TCP/UDP malformed packet check */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ip6_eext                     : 2;  /**< Enable IPv6 early extension headers */
+	uint64_t ip4_opts                     : 1;  /**< Enable IPv4 options check */
+	uint64_t ip_hop                       : 1;  /**< Enable TTL (IPv4) / hop (IPv6) check */
+	uint64_t ip_mal                       : 1;  /**< Enable malformed check */
+	uint64_t ip_chk                       : 1;  /**< Enable IPv4 header checksum check */
+#else
+	uint64_t ip_chk                       : 1;
+	uint64_t ip_mal                       : 1;
+	uint64_t ip_hop                       : 1;
+	uint64_t ip4_opts                     : 1;
+	uint64_t ip6_eext                     : 2;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t l4_mal                       : 1;
+	uint64_t l4_prt                       : 1;
+	uint64_t l4_chk                       : 1;
+	uint64_t l4_len                       : 1;
+	uint64_t tcp_flag                     : 1;
+	uint64_t l2_mal                       : 1;
+	uint64_t vs_qos                       : 1;
+	uint64_t vs_wqe                       : 1;
+	uint64_t ignrs                        : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t dsa_grp_sid                  : 1;
+	uint64_t dsa_grp_scmd                 : 1;
+	uint64_t dsa_grp_tvid                 : 1;
+	uint64_t ihmsk_dis                    : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn68xxp1;
+	struct cvmx_pip_gbl_ctl_cn61xx        cnf71xx;
 };
 typedef union cvmx_pip_gbl_ctl cvmx_pip_gbl_ctl_t;
 
@@ -1428,12 +2322,10 @@ typedef union cvmx_pip_gbl_ctl cvmx_pip_gbl_ctl_t;
  * PRI=table address, QOS=dont_carepriority level, UP_QOS=0 and then read
  * PIP_HG_PRI_QOS.  The table data will be in PIP_HG_PRI_QOS[QOS].
  */
-union cvmx_pip_hg_pri_qos
-{
+union cvmx_pip_hg_pri_qos {
 	uint64_t u64;
-	struct cvmx_pip_hg_pri_qos_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_hg_pri_qos_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t up_qos                       : 1;  /**< When written to '1', updates the entry in the
                                                          HG_QOS_TABLE as specified by PRI to a value of
@@ -1457,8 +2349,11 @@ union cvmx_pip_hg_pri_qos
 	struct cvmx_pip_hg_pri_qos_s          cn52xx;
 	struct cvmx_pip_hg_pri_qos_s          cn52xxp1;
 	struct cvmx_pip_hg_pri_qos_s          cn56xx;
+	struct cvmx_pip_hg_pri_qos_s          cn61xx;
 	struct cvmx_pip_hg_pri_qos_s          cn63xx;
 	struct cvmx_pip_hg_pri_qos_s          cn63xxp1;
+	struct cvmx_pip_hg_pri_qos_s          cn66xx;
+	struct cvmx_pip_hg_pri_qos_s          cnf71xx;
 };
 typedef union cvmx_pip_hg_pri_qos cvmx_pip_hg_pri_qos_t;
 
@@ -1470,12 +2365,10 @@ typedef union cvmx_pip_hg_pri_qos cvmx_pip_hg_pri_qos_t;
  * Determines if hardward should raise an interrupt to software
  * when an exception event occurs.
  */
-union cvmx_pip_int_en
-{
+union cvmx_pip_int_en {
 	uint64_t u64;
-	struct cvmx_pip_int_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t punyerr                      : 1;  /**< Frame was received with length <=4B when CRC
                                                          stripping in IPD is enable */
@@ -1508,9 +2401,8 @@ union cvmx_pip_int_en
 	uint64_t reserved_13_63               : 51;
 #endif
 	} s;
-	struct cvmx_pip_int_en_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_int_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t beperr                       : 1;  /**< Parity Error in back end memory */
 	uint64_t feperr                       : 1;  /**< Parity Error in front end memory */
@@ -1540,9 +2432,8 @@ union cvmx_pip_int_en
 	struct cvmx_pip_int_en_cn30xx         cn31xx;
 	struct cvmx_pip_int_en_cn30xx         cn38xx;
 	struct cvmx_pip_int_en_cn30xx         cn38xxp2;
-	struct cvmx_pip_int_en_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_int_en_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
 	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
@@ -1572,9 +2463,8 @@ union cvmx_pip_int_en
 	uint64_t reserved_12_63               : 52;
 #endif
 	} cn50xx;
-	struct cvmx_pip_int_en_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_int_en_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t punyerr                      : 1;  /**< Frame was received with length <=4B when CRC
                                                          stripping in IPD is enable */
@@ -1609,9 +2499,8 @@ union cvmx_pip_int_en
 	} cn52xx;
 	struct cvmx_pip_int_en_cn52xx         cn52xxp1;
 	struct cvmx_pip_int_en_s              cn56xx;
-	struct cvmx_pip_int_en_cn56xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_int_en_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
 	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
@@ -1642,9 +2531,8 @@ union cvmx_pip_int_en
 	uint64_t reserved_12_63               : 52;
 #endif
 	} cn56xxp1;
-	struct cvmx_pip_int_en_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_int_en_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t punyerr                      : 1;  /**< Frame was received with length <=4B when CRC
                                                          stripping in IPD is enable */
@@ -1674,8 +2562,13 @@ union cvmx_pip_int_en
 #endif
 	} cn58xx;
 	struct cvmx_pip_int_en_cn30xx         cn58xxp1;
+	struct cvmx_pip_int_en_s              cn61xx;
 	struct cvmx_pip_int_en_s              cn63xx;
 	struct cvmx_pip_int_en_s              cn63xxp1;
+	struct cvmx_pip_int_en_s              cn66xx;
+	struct cvmx_pip_int_en_s              cn68xx;
+	struct cvmx_pip_int_en_s              cn68xxp1;
+	struct cvmx_pip_int_en_s              cnf71xx;
 };
 typedef union cvmx_pip_int_en cvmx_pip_int_en_t;
 
@@ -1735,12 +2628,10 @@ typedef union cvmx_pip_int_en cvmx_pip_int_en_t;
  *   PIP can drop packets based on QOS results received from IPD.  If the QOS
  *   algorithm decides to drop a packet, PIP will assert an interrupt.
  */
-union cvmx_pip_int_reg
-{
+union cvmx_pip_int_reg {
 	uint64_t u64;
-	struct cvmx_pip_int_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t punyerr                      : 1;  /**< Frame was received with length <=4B when CRC
                                                          stripping in IPD is enable */
@@ -1776,9 +2667,8 @@ union cvmx_pip_int_reg
 	uint64_t reserved_13_63               : 51;
 #endif
 	} s;
-	struct cvmx_pip_int_reg_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_int_reg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t beperr                       : 1;  /**< Parity Error in back end memory */
 	uint64_t feperr                       : 1;  /**< Parity Error in front end memory */
@@ -1811,9 +2701,8 @@ union cvmx_pip_int_reg
 	struct cvmx_pip_int_reg_cn30xx        cn31xx;
 	struct cvmx_pip_int_reg_cn30xx        cn38xx;
 	struct cvmx_pip_int_reg_cn30xx        cn38xxp2;
-	struct cvmx_pip_int_reg_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_int_reg_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
 	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
@@ -1846,9 +2735,8 @@ union cvmx_pip_int_reg
 	uint64_t reserved_12_63               : 52;
 #endif
 	} cn50xx;
-	struct cvmx_pip_int_reg_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t punyerr                      : 1;  /**< Frame was received with length <=4B when CRC
                                                          stripping in IPD is enable */
@@ -1886,9 +2774,8 @@ union cvmx_pip_int_reg
 	} cn52xx;
 	struct cvmx_pip_int_reg_cn52xx        cn52xxp1;
 	struct cvmx_pip_int_reg_s             cn56xx;
-	struct cvmx_pip_int_reg_cn56xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_int_reg_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
 	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
@@ -1922,9 +2809,8 @@ union cvmx_pip_int_reg
 	uint64_t reserved_12_63               : 52;
 #endif
 	} cn56xxp1;
-	struct cvmx_pip_int_reg_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_int_reg_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t punyerr                      : 1;  /**< Frame was received with length <=4B when CRC
                                                          stripping in IPD is enable */
@@ -1957,8 +2843,13 @@ union cvmx_pip_int_reg
 #endif
 	} cn58xx;
 	struct cvmx_pip_int_reg_cn30xx        cn58xxp1;
+	struct cvmx_pip_int_reg_s             cn61xx;
 	struct cvmx_pip_int_reg_s             cn63xx;
 	struct cvmx_pip_int_reg_s             cn63xxp1;
+	struct cvmx_pip_int_reg_s             cn66xx;
+	struct cvmx_pip_int_reg_s             cn68xx;
+	struct cvmx_pip_int_reg_s             cn68xxp1;
+	struct cvmx_pip_int_reg_s             cnf71xx;
 };
 typedef union cvmx_pip_int_reg cvmx_pip_int_reg_t;
 
@@ -1998,12 +2889,10 @@ typedef union cvmx_pip_int_reg cvmx_pip_int_reg_t;
  *  . PIP_PRT_TAG[TCP6_TAG] == 0
  *  . PIP_GBL_CFG[TAG_SYN]  == 0
  */
-union cvmx_pip_ip_offset
-{
+union cvmx_pip_ip_offset {
 	uint64_t u64;
-	struct cvmx_pip_ip_offset_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_ip_offset_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t offset                       : 3;  /**< Number of 8B ticks to include in workQ entry
                                                           prior to IP data
@@ -2031,24 +2920,90 @@ union cvmx_pip_ip_offset
 	struct cvmx_pip_ip_offset_s           cn56xxp1;
 	struct cvmx_pip_ip_offset_s           cn58xx;
 	struct cvmx_pip_ip_offset_s           cn58xxp1;
+	struct cvmx_pip_ip_offset_s           cn61xx;
 	struct cvmx_pip_ip_offset_s           cn63xx;
 	struct cvmx_pip_ip_offset_s           cn63xxp1;
+	struct cvmx_pip_ip_offset_s           cn66xx;
+	struct cvmx_pip_ip_offset_s           cn68xx;
+	struct cvmx_pip_ip_offset_s           cn68xxp1;
+	struct cvmx_pip_ip_offset_s           cnf71xx;
 };
 typedef union cvmx_pip_ip_offset cvmx_pip_ip_offset_t;
 
 /**
+ * cvmx_pip_pri_tbl#
+ *
+ * Notes:
+ * The priority level from HiGig header is as follows
+ *
+ * HiGig/HiGig+ PRI = [1'b0, CNG[1:0], COS[2:0]]
+ * HiGig2       PRI = [DP[1:0], TC[3:0]]
+ *
+ * DSA          PRI = WORD0[15:13]
+ *
+ * VLAN         PRI = VLAN[15:13]
+ *
+ * DIFFSERV         = IP.TOS/CLASS<7:2>
+ */
+union cvmx_pip_pri_tblx {
+	uint64_t u64;
+	struct cvmx_pip_pri_tblx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t diff2_padd                   : 8;  /**< Diffserv port-add */
+	uint64_t hg2_padd                     : 8;  /**< HG_PRI port-add */
+	uint64_t vlan2_padd                   : 8;  /**< VLAN port-add */
+	uint64_t reserved_38_39               : 2;
+	uint64_t diff2_bpid                   : 6;  /**< Diffserv backpressure ID */
+	uint64_t reserved_30_31               : 2;
+	uint64_t hg2_bpid                     : 6;  /**< HG_PRI backpressure ID */
+	uint64_t reserved_22_23               : 2;
+	uint64_t vlan2_bpid                   : 6;  /**< VLAN backpressure ID */
+	uint64_t reserved_11_15               : 5;
+	uint64_t diff2_qos                    : 3;  /**< Diffserv QOS level */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t hg2_qos                      : 3;  /**< HG_PRI QOS level */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t vlan2_qos                    : 3;  /**< VLAN QOS level */
+#else
+	uint64_t vlan2_qos                    : 3;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t hg2_qos                      : 3;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t diff2_qos                    : 3;
+	uint64_t reserved_11_15               : 5;
+	uint64_t vlan2_bpid                   : 6;
+	uint64_t reserved_22_23               : 2;
+	uint64_t hg2_bpid                     : 6;
+	uint64_t reserved_30_31               : 2;
+	uint64_t diff2_bpid                   : 6;
+	uint64_t reserved_38_39               : 2;
+	uint64_t vlan2_padd                   : 8;
+	uint64_t hg2_padd                     : 8;
+	uint64_t diff2_padd                   : 8;
+#endif
+	} s;
+	struct cvmx_pip_pri_tblx_s            cn68xx;
+	struct cvmx_pip_pri_tblx_s            cn68xxp1;
+};
+typedef union cvmx_pip_pri_tblx cvmx_pip_pri_tblx_t;
+
+/**
  * cvmx_pip_prt_cfg#
  *
  * PIP_PRT_CFGX = Per port config information
  *
  */
-union cvmx_pip_prt_cfgx
-{
+union cvmx_pip_prt_cfgx {
 	uint64_t u64;
-	struct cvmx_pip_prt_cfgx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_53_63               : 11;
+	struct cvmx_pip_prt_cfgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_55_63               : 9;
+	uint64_t ih_pri                       : 1;  /**< Use the PRI/QOS field in the instruction header
+                                                         as the PRIORITY in BPID calculations. */
+	uint64_t len_chk_sel                  : 1;  /**< Selects which PIP_FRM_LEN_CHK register is used
+                                                         for this port-kind for MINERR and MAXERR checks.
+                                                         LEN_CHK_SEL=0, use PIP_FRM_LEN_CHK0
+                                                         LEN_CHK_SEL=1, use PIP_FRM_LEN_CHK1 */
 	uint64_t pad_len                      : 1;  /**< When set, disables the length check for pkts with
                                                          padding in the client data */
 	uint64_t vlan_len                     : 1;  /**< When set, disables the length check for DSA/VLAN
@@ -2056,13 +3011,19 @@ union cvmx_pip_prt_cfgx
 	uint64_t lenerr_en                    : 1;  /**< L2 length error check enable
                                                          Frame was received with length error
                                                           Typically, this check will not be enabled for
-                                                          incoming packets on the PCIe ports. */
+                                                          incoming packets on the DPI and sRIO ports
+                                                          because the CRC bytes may not normally be
+                                                          present. */
 	uint64_t maxerr_en                    : 1;  /**< Max frame error check enable
-                                                         Frame was received with length > max_length */
+                                                         Frame was received with length > max_length
+                                                         max_length is defined by PIP_FRM_LEN_CHK[MAXLEN] */
 	uint64_t minerr_en                    : 1;  /**< Min frame error check enable
                                                          Frame was received with length < min_length
                                                           Typically, this check will not be enabled for
-                                                          incoming packets on the PCIe ports. */
+                                                          incoming packets on the DPI and sRIO ports
+                                                          because the CRC bytes may not normally be
+                                                          present.
+                                                          min_length is defined by PIP_FRM_LEN_CHK[MINLEN] */
 	uint64_t grp_wat_47                   : 4;  /**< GRP Watcher enable
                                                          (Watchers 4-7) */
 	uint64_t qos_wat_47                   : 4;  /**< QOS Watcher enable
@@ -2081,7 +3042,10 @@ union cvmx_pip_prt_cfgx
                                                          instruction header words, either DYN_RS or
                                                          PIP_GBL_CTL[IGNRS] should be set. */
 	uint64_t inst_hdr                     : 1;  /**< 8-byte INST_HDR is present on all packets
-                                                         (not for PCI prts, 32-35)
+                                                         Internally set for RAWFULL/RAWSCHED packets
+                                                         on the DPI ports (32-35).
+                                                         Internally cleared for all other packets on the
+                                                         DPI ports (32-35).
                                                          Must be zero in DSA mode */
 	uint64_t grp_wat                      : 4;  /**< GRP Watcher enable */
 	uint64_t hg_qos                       : 1;  /**< When set, uses the HiGig priority bits as a
@@ -2104,23 +3068,28 @@ union cvmx_pip_prt_cfgx
 	uint64_t reserved_13_15               : 3;
 	uint64_t crc_en                       : 1;  /**< CRC Checking enabled */
 	uint64_t higig_en                     : 1;  /**< Enable HiGig parsing
-                                                         Should not be set for PCIe ports (ports 32-35)
+                                                         Should not be set for DPI ports (ports 32-35)
+                                                         Should not be set for sRIO ports (ports 40-47)
                                                          Should not be set for ports in which PTP_MODE=1
                                                          When HIGIG_EN=1:
                                                           DSA_EN field below must be zero
+                                                          PIP_PRT_CFGB[ALT_SKP_EN] must be zero.
                                                           SKIP field below is both Skip I size and the
                                                             size of the HiGig* header (12 or 16 bytes) */
 	uint64_t dsa_en                       : 1;  /**< Enable DSA tag parsing
+                                                         Should not be set for sRIO (ports 40-47)
+                                                         Should not be set for ports in which PTP_MODE=1
                                                          When DSA_EN=1:
                                                           HIGIG_EN field above must be zero
                                                           SKIP field below is size of DSA tag (4, 8, or
                                                             12 bytes) rather than the size of Skip I
                                                           total SKIP (Skip I + header + Skip II
                                                             must be zero
-                                                          INST_HDR field above must be zero (non-PCIe
+                                                          INST_HDR field above must be zero (non-DPI
                                                             ports)
-                                                          For PCIe ports, NPEI_PKT*_INSTR_HDR[USE_IHDR]
-                                                            and PCIE_INST_HDR[R] should be clear
+                                                          PIP_PRT_CFGB[ALT_SKP_EN] must be zero.
+                                                          For DPI ports, SLI_PKT*_INSTR_HEADER[USE_IHDR]
+                                                            and DPI_INST_HDR[R] should be clear
                                                           MODE field below must be "skip to L2" */
 	cvmx_pip_port_parse_mode_t mode       : 2;  /**< Parse Mode
                                                          0 = no packet inspection (Uninterpreted)
@@ -2129,10 +3098,13 @@ union cvmx_pip_prt_cfgx
                                                          3 = (illegal)
                                                          Must be 2 ("skip to L2") when in DSA mode. */
 	uint64_t reserved_7_7                 : 1;
-	uint64_t skip                         : 7;  /**< Optional Skip I amount for packets.  Does not
-                                                         apply to packets on PCI ports when a PKT_INST_HDR
-                                                         is present.  See section 7.2.7 - Legal Skip
-                                                         Values for further details.
+	uint64_t skip                         : 7;  /**< Optional Skip I amount for packets.
+                                                         HW forces the SKIP to zero for packets on DPI
+                                                         ports (32-35) when a PKT_INST_HDR is present.
+                                                         See PIP_PRT_CFGB[ALT_SKP*] and PIP_ALT_SKIP_CFG.
+                                                         See HRM sections "Parse Mode and Skip Length
+                                                         Selection" and "Legal Skip Values"
+                                                         for further details.
                                                          In DSA mode, indicates the DSA header length, not
                                                            Skip I size. (Must be 4,8,or 12)
                                                          In HIGIG mode, indicates both the Skip I size and
@@ -2168,12 +3140,13 @@ union cvmx_pip_prt_cfgx
 	uint64_t lenerr_en                    : 1;
 	uint64_t vlan_len                     : 1;
 	uint64_t pad_len                      : 1;
-	uint64_t reserved_53_63               : 11;
+	uint64_t len_chk_sel                  : 1;
+	uint64_t ih_pri                       : 1;
+	uint64_t reserved_55_63               : 9;
 #endif
 	} s;
-	struct cvmx_pip_prt_cfgx_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_prt_cfgx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_37_63               : 27;
 	uint64_t rawdrp                       : 1;  /**< Allow the IPD to RED drop a packet.
                                                          Normally, IPD will never drop a packet that PIP
@@ -2227,9 +3200,8 @@ union cvmx_pip_prt_cfgx
 #endif
 	} cn30xx;
 	struct cvmx_pip_prt_cfgx_cn30xx       cn31xx;
-	struct cvmx_pip_prt_cfgx_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_prt_cfgx_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_37_63               : 27;
 	uint64_t rawdrp                       : 1;  /**< Allow the IPD to RED drop a packet.
                                                          Normally, IPD will never drop a packet that PIP
@@ -2287,9 +3259,8 @@ union cvmx_pip_prt_cfgx
 #endif
 	} cn38xx;
 	struct cvmx_pip_prt_cfgx_cn38xx       cn38xxp2;
-	struct cvmx_pip_prt_cfgx_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_prt_cfgx_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_53_63               : 11;
 	uint64_t pad_len                      : 1;  /**< When set, disables the length check for pkts with
                                                          padding in the client data */
@@ -2376,13 +3347,128 @@ union cvmx_pip_prt_cfgx
 	uint64_t reserved_53_63               : 11;
 #endif
 	} cn50xx;
-	struct cvmx_pip_prt_cfgx_s            cn52xx;
-	struct cvmx_pip_prt_cfgx_s            cn52xxp1;
-	struct cvmx_pip_prt_cfgx_s            cn56xx;
+	struct cvmx_pip_prt_cfgx_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_53_63               : 11;
+	uint64_t pad_len                      : 1;  /**< When set, disables the length check for pkts with
+                                                         padding in the client data */
+	uint64_t vlan_len                     : 1;  /**< When set, disables the length check for DSA/VLAN
+                                                         pkts */
+	uint64_t lenerr_en                    : 1;  /**< L2 length error check enable
+                                                         Frame was received with length error
+                                                          Typically, this check will not be enabled for
+                                                          incoming packets on the PCIe ports. */
+	uint64_t maxerr_en                    : 1;  /**< Max frame error check enable
+                                                         Frame was received with length > max_length */
+	uint64_t minerr_en                    : 1;  /**< Min frame error check enable
+                                                         Frame was received with length < min_length
+                                                          Typically, this check will not be enabled for
+                                                          incoming packets on the PCIe ports. */
+	uint64_t grp_wat_47                   : 4;  /**< GRP Watcher enable
+                                                         (Watchers 4-7) */
+	uint64_t qos_wat_47                   : 4;  /**< QOS Watcher enable
+                                                         (Watchers 4-7) */
+	uint64_t reserved_37_39               : 3;
+	uint64_t rawdrp                       : 1;  /**< Allow the IPD to RED drop a packet.
+                                                         Normally, IPD will never drop a packet that PIP
+                                                         indicates is RAW.
+                                                         0=never drop RAW packets based on RED algorithm
+                                                         1=allow RAW packet drops based on RED algorithm */
+	uint64_t tag_inc                      : 2;  /**< Which of the 4 PIP_TAG_INC to use when
+                                                         calculating mask tag hash */
+	uint64_t dyn_rs                       : 1;  /**< Dynamically calculate RS based on pkt size and
+                                                         configuration.  If DYN_RS is set then
+                                                         PKT_INST_HDR[RS] is not used.  When using 2-byte
+                                                         instruction header words, either DYN_RS or
+                                                         PIP_GBL_CTL[IGNRS] should be set. */
+	uint64_t inst_hdr                     : 1;  /**< 8-byte INST_HDR is present on all packets
+                                                         (not for PCI ports, 32-35)
+                                                         Must be zero in DSA mode */
+	uint64_t grp_wat                      : 4;  /**< GRP Watcher enable */
+	uint64_t hg_qos                       : 1;  /**< When set, uses the HiGig priority bits as a
+                                                         lookup into the HG_QOS_TABLE (PIP_HG_PRI_QOS)
+                                                         to determine the QOS value
+                                                         HG_QOS must not be set when HIGIG_EN=0 */
+	uint64_t qos                          : 3;  /**< Default QOS level of the port */
+	uint64_t qos_wat                      : 4;  /**< QOS Watcher enable
+                                                         (Watchers 0-3) */
+	uint64_t qos_vsel                     : 1;  /**< Which QOS in PIP_QOS_VLAN to use
+                                                         0 = PIP_QOS_VLAN[QOS]
+                                                         1 = PIP_QOS_VLAN[QOS1] */
+	uint64_t qos_vod                      : 1;  /**< QOS VLAN over Diffserv
+                                                         if DSA/VLAN exists, it is used
+                                                         else if IP exists, Diffserv is used
+                                                         else the per port default is used
+                                                         Watchers are still highest priority */
+	uint64_t qos_diff                     : 1;  /**< QOS Diffserv */
+	uint64_t qos_vlan                     : 1;  /**< QOS VLAN */
+	uint64_t reserved_13_15               : 3;
+	uint64_t crc_en                       : 1;  /**< CRC Checking enabled
+                                                         (Disabled in 52xx) */
+	uint64_t higig_en                     : 1;  /**< Enable HiGig parsing
+                                                         When HIGIG_EN=1:
+                                                          DSA_EN field below must be zero
+                                                          SKIP field below is both Skip I size and the
+                                                            size of the HiGig* header (12 or 16 bytes) */
+	uint64_t dsa_en                       : 1;  /**< Enable DSA tag parsing
+                                                         When DSA_EN=1:
+                                                          HIGIG_EN field above must be zero
+                                                          SKIP field below is size of DSA tag (4, 8, or
+                                                            12 bytes) rather than the size of Skip I
+                                                          total SKIP (Skip I + header + Skip II
+                                                            must be zero
+                                                          INST_HDR field above must be zero
+                                                          MODE field below must be "skip to L2" */
+	cvmx_pip_port_parse_mode_t mode       : 2;  /**< Parse Mode
+                                                         0 = no packet inspection (Uninterpreted)
+                                                         1 = L2 parsing / skip to L2
+                                                         2 = IP parsing / skip to L3
+                                                         3 = (illegal)
+                                                         Must be 2 ("skip to L2") when in DSA mode. */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t skip                         : 7;  /**< Optional Skip I amount for packets.
+                                                         See section 7.2.7 - Legal Skip
+                                                         Values for further details.
+                                                         In DSA mode, indicates the DSA header length, not
+                                                           Skip I size. (Must be 4,8,or 12)
+                                                         In HIGIG mode, indicates both the Skip I size and
+                                                           the HiGig header size (Must be 12 or 16). */
+#else
+	uint64_t skip                         : 7;
+	uint64_t reserved_7_7                 : 1;
+	cvmx_pip_port_parse_mode_t mode       : 2;
+	uint64_t dsa_en                       : 1;
+	uint64_t higig_en                     : 1;
+	uint64_t crc_en                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t qos_vlan                     : 1;
+	uint64_t qos_diff                     : 1;
+	uint64_t qos_vod                      : 1;
+	uint64_t qos_vsel                     : 1;
+	uint64_t qos_wat                      : 4;
+	uint64_t qos                          : 3;
+	uint64_t hg_qos                       : 1;
+	uint64_t grp_wat                      : 4;
+	uint64_t inst_hdr                     : 1;
+	uint64_t dyn_rs                       : 1;
+	uint64_t tag_inc                      : 2;
+	uint64_t rawdrp                       : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t qos_wat_47                   : 4;
+	uint64_t grp_wat_47                   : 4;
+	uint64_t minerr_en                    : 1;
+	uint64_t maxerr_en                    : 1;
+	uint64_t lenerr_en                    : 1;
+	uint64_t vlan_len                     : 1;
+	uint64_t pad_len                      : 1;
+	uint64_t reserved_53_63               : 11;
+#endif
+	} cn52xx;
+	struct cvmx_pip_prt_cfgx_cn52xx       cn52xxp1;
+	struct cvmx_pip_prt_cfgx_cn52xx       cn56xx;
 	struct cvmx_pip_prt_cfgx_cn50xx       cn56xxp1;
-	struct cvmx_pip_prt_cfgx_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_prt_cfgx_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_37_63               : 27;
 	uint64_t rawdrp                       : 1;  /**< Allow the IPD to RED drop a packet.
                                                          Normally, IPD will never drop a packet that PIP
@@ -2446,24 +3532,329 @@ union cvmx_pip_prt_cfgx
 #endif
 	} cn58xx;
 	struct cvmx_pip_prt_cfgx_cn58xx       cn58xxp1;
-	struct cvmx_pip_prt_cfgx_s            cn63xx;
-	struct cvmx_pip_prt_cfgx_s            cn63xxp1;
+	struct cvmx_pip_prt_cfgx_cn52xx       cn61xx;
+	struct cvmx_pip_prt_cfgx_cn52xx       cn63xx;
+	struct cvmx_pip_prt_cfgx_cn52xx       cn63xxp1;
+	struct cvmx_pip_prt_cfgx_cn52xx       cn66xx;
+	struct cvmx_pip_prt_cfgx_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_55_63               : 9;
+	uint64_t ih_pri                       : 1;  /**< Use the PRI/QOS field in the instruction header
+                                                         as the PRIORITY in BPID calculations. */
+	uint64_t len_chk_sel                  : 1;  /**< Selects which PIP_FRM_LEN_CHK register is used
+                                                         for this port-kind for MINERR and MAXERR checks.
+                                                         LEN_CHK_SEL=0, use PIP_FRM_LEN_CHK0
+                                                         LEN_CHK_SEL=1, use PIP_FRM_LEN_CHK1 */
+	uint64_t pad_len                      : 1;  /**< When set, disables the length check for pkts with
+                                                         padding in the client data */
+	uint64_t vlan_len                     : 1;  /**< When set, disables the length check for DSA/VLAN
+                                                         pkts */
+	uint64_t lenerr_en                    : 1;  /**< L2 length error check enable
+                                                         Frame was received with length error
+                                                          Typically, this check will not be enabled for
+                                                          incoming packets on the DPI rings
+                                                          because the CRC bytes may not normally be
+                                                          present. */
+	uint64_t maxerr_en                    : 1;  /**< Max frame error check enable
+                                                         Frame was received with length > max_length
+                                                         max_length is defined by PIP_FRM_LEN_CHK[MAXLEN] */
+	uint64_t minerr_en                    : 1;  /**< Min frame error check enable
+                                                         Frame was received with length < min_length
+                                                          Typically, this check will not be enabled for
+                                                          incoming packets on the DPI rings
+                                                          because the CRC bytes may not normally be
+                                                          present.
+                                                          min_length is defined by PIP_FRM_LEN_CHK[MINLEN] */
+	uint64_t grp_wat_47                   : 4;  /**< GRP Watcher enable
+                                                         (Watchers 4-7) */
+	uint64_t qos_wat_47                   : 4;  /**< QOS Watcher enable
+                                                         (Watchers 4-7) */
+	uint64_t reserved_37_39               : 3;
+	uint64_t rawdrp                       : 1;  /**< Allow the IPD to RED drop a packet.
+                                                         Normally, IPD will never drop a packet in which
+                                                         PKT_INST_HDR[R] is set.
+                                                         0=never drop RAW packets based on RED algorithm
+                                                         1=allow RAW packet drops based on RED algorithm */
+	uint64_t tag_inc                      : 2;  /**< Which of the 4 PIP_TAG_INC to use when
+                                                         calculating mask tag hash */
+	uint64_t dyn_rs                       : 1;  /**< Dynamically calculate RS based on pkt size and
+                                                         configuration.  If DYN_RS is set then
+                                                         PKT_INST_HDR[RS] is not used.  When using 2-byte
+                                                         instruction header words, either DYN_RS or
+                                                         PIP_GBL_CTL[IGNRS] should be set. */
+	uint64_t inst_hdr                     : 1;  /**< 8-byte INST_HDR is present on all packets
+                                                         Normally INST_HDR should be set for packets that
+                                                         include a PKT_INST_HDR prepended by DPI hardware.
+                                                         (If SLI_PORTx_PKIND[RPK_ENB]=0, for packets that
+                                                         include a PKT_INST_HDR prepended by DPI,
+                                                         PIP internally sets INST_HDR before using it.)
+                                                         Must be zero in DSA mode */
+	uint64_t grp_wat                      : 4;  /**< GRP Watcher enable */
+	uint64_t hg_qos                       : 1;  /**< When set, uses the HiGig priority bits as a
+                                                         lookup into the HG_QOS_TABLE (PIP_HG_PRI_QOS)
+                                                         to determine the QOS value
+                                                         HG_QOS must not be set when HIGIG_EN=0 */
+	uint64_t qos                          : 3;  /**< Default QOS level of the port */
+	uint64_t qos_wat                      : 4;  /**< QOS Watcher enable
+                                                         (Watchers 0-3) */
+	uint64_t reserved_19_19               : 1;
+	uint64_t qos_vod                      : 1;  /**< QOS VLAN over Diffserv
+                                                         if DSA/VLAN exists, it is used
+                                                         else if IP exists, Diffserv is used
+                                                         else the per port default is used
+                                                         Watchers are still highest priority */
+	uint64_t qos_diff                     : 1;  /**< QOS Diffserv */
+	uint64_t qos_vlan                     : 1;  /**< QOS VLAN */
+	uint64_t reserved_13_15               : 3;
+	uint64_t crc_en                       : 1;  /**< CRC Checking enabled */
+	uint64_t higig_en                     : 1;  /**< Enable HiGig parsing
+                                                         Normally HIGIG_EN should be clear for packets that
+                                                         include a PKT_INST_HDR prepended by DPI hardware.
+                                                         (If SLI_PORTx_PKIND[RPK_ENB]=0, for packets that
+                                                         include a PKT_INST_HDR prepended by DPI,
+                                                         PIP internally clears HIGIG_EN before using it.)
+                                                         Should not be set for ports in which PTP_MODE=1
+                                                         When HIGIG_EN=1:
+                                                          DSA_EN field below must be zero
+                                                          PIP_PRT_CFGB[ALT_SKP_EN] must be zero.
+                                                          SKIP field below is both Skip I size and the
+                                                            size of the HiGig* header (12 or 16 bytes) */
+	uint64_t dsa_en                       : 1;  /**< Enable DSA tag parsing
+                                                         Should not be set for ports in which PTP_MODE=1
+                                                         When DSA_EN=1:
+                                                          HIGIG_EN field above must be zero
+                                                          SKIP field below is size of DSA tag (4, 8, or
+                                                            12 bytes) rather than the size of Skip I
+                                                          total SKIP (Skip I + header + Skip II
+                                                            must be zero
+                                                          INST_HDR field above must be zero
+                                                          PIP_PRT_CFGB[ALT_SKP_EN] must be zero.
+                                                          For DPI rings, DPI hardware must not prepend
+                                                          a PKT_INST_HDR when DSA_EN=1.
+                                                          MODE field below must be "skip to L2" */
+	cvmx_pip_port_parse_mode_t mode       : 2;  /**< Parse Mode
+                                                         0 = no packet inspection (Uninterpreted)
+                                                         1 = L2 parsing / skip to L2
+                                                         2 = IP parsing / skip to L3
+                                                         3 = (illegal)
+                                                         Must be 2 ("skip to L2") when in DSA mode. */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t skip                         : 7;  /**< Optional Skip I amount for packets.
+                                                         Should normally be zero for  packets on
+                                                         DPI rings when a PKT_INST_HDR is prepended by DPI
+                                                         hardware.
+                                                         See PIP_PRT_CFGB[ALT_SKP*] and PIP_ALT_SKIP_CFG.
+                                                         See HRM sections "Parse Mode and Skip Length
+                                                         Selection" and "Legal Skip Values"
+                                                         for further details.
+                                                         In DSA mode, indicates the DSA header length, not
+                                                           Skip I size. (Must be 4,8,or 12)
+                                                         In HIGIG mode, indicates both the Skip I size and
+                                                           the HiGig header size (Must be 12 or 16).
+                                                         If PTP_MODE, the 8B timestamp is prepended to the
+                                                          packet.  SKIP should be increased by 8 to
+                                                          compensate for the additional timestamp field. */
+#else
+	uint64_t skip                         : 7;
+	uint64_t reserved_7_7                 : 1;
+	cvmx_pip_port_parse_mode_t mode       : 2;
+	uint64_t dsa_en                       : 1;
+	uint64_t higig_en                     : 1;
+	uint64_t crc_en                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t qos_vlan                     : 1;
+	uint64_t qos_diff                     : 1;
+	uint64_t qos_vod                      : 1;
+	uint64_t reserved_19_19               : 1;
+	uint64_t qos_wat                      : 4;
+	uint64_t qos                          : 3;
+	uint64_t hg_qos                       : 1;
+	uint64_t grp_wat                      : 4;
+	uint64_t inst_hdr                     : 1;
+	uint64_t dyn_rs                       : 1;
+	uint64_t tag_inc                      : 2;
+	uint64_t rawdrp                       : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t qos_wat_47                   : 4;
+	uint64_t grp_wat_47                   : 4;
+	uint64_t minerr_en                    : 1;
+	uint64_t maxerr_en                    : 1;
+	uint64_t lenerr_en                    : 1;
+	uint64_t vlan_len                     : 1;
+	uint64_t pad_len                      : 1;
+	uint64_t len_chk_sel                  : 1;
+	uint64_t ih_pri                       : 1;
+	uint64_t reserved_55_63               : 9;
+#endif
+	} cn68xx;
+	struct cvmx_pip_prt_cfgx_cn68xx       cn68xxp1;
+	struct cvmx_pip_prt_cfgx_cn52xx       cnf71xx;
 };
 typedef union cvmx_pip_prt_cfgx cvmx_pip_prt_cfgx_t;
 
 /**
+ * cvmx_pip_prt_cfgb#
+ *
+ * Notes:
+ * PIP_PRT_CFGB* does not exist prior to pass 1.2.
+ *
+ */
+union cvmx_pip_prt_cfgbx {
+	uint64_t u64;
+	struct cvmx_pip_prt_cfgbx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_39_63               : 25;
+	uint64_t alt_skp_sel                  : 2;  /**< Alternate skip selector
+                                                         When enabled (ALT_SKP_EN), selects which of the
+                                                         four PIP_ALT_SKIP_CFGx to use with the packets
+                                                         arriving on the port-kind. */
+	uint64_t alt_skp_en                   : 1;  /**< Enable the alternate skip selector
+                                                         When enabled, the HW is able to recompute the
+                                                         SKIP I value based on the packet contents.
+                                                         Up to two of the initial 64 bits of the header
+                                                         are used along with four PIP_ALT_SKIP_CFGx to
+                                                         determine the updated SKIP I value.
+                                                         The bits of the packet used should be present in
+                                                         all packets.
+                                                         PIP_PRT_CFG[DSA_EN,HIGIG_EN] must be disabled
+                                                         when ALT_SKP_EN is set.
+                                                         ALT_SKP_EN must not be set for DPI ports (32-35)
+                                                         when a PKT_INST_HDR is present.
+                                                         ALT_SKP_EN should not be enabled for ports which
+                                                         have GMX_RX_FRM_CTL[PTP_MODE] set as the timestamp
+                                                         will be prepended onto the initial 64 bits of the
+                                                         packet. */
+	uint64_t reserved_35_35               : 1;
+	uint64_t bsel_num                     : 2;  /**< Which of the 4 bit select extractors to use
+                                                         (Alias to PIP_PRT_CFG) */
+	uint64_t bsel_en                      : 1;  /**< Enable to turn on/off use of bit select extractor
+                                                         (Alias to PIP_PRT_CFG) */
+	uint64_t reserved_24_31               : 8;
+	uint64_t base                         : 8;  /**< Base priority address into the table */
+	uint64_t reserved_6_15                : 10;
+	uint64_t bpid                         : 6;  /**< Default BPID to use for packets on this port-kind. */
+#else
+	uint64_t bpid                         : 6;
+	uint64_t reserved_6_15                : 10;
+	uint64_t base                         : 8;
+	uint64_t reserved_24_31               : 8;
+	uint64_t bsel_en                      : 1;
+	uint64_t bsel_num                     : 2;
+	uint64_t reserved_35_35               : 1;
+	uint64_t alt_skp_en                   : 1;
+	uint64_t alt_skp_sel                  : 2;
+	uint64_t reserved_39_63               : 25;
+#endif
+	} s;
+	struct cvmx_pip_prt_cfgbx_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_39_63               : 25;
+	uint64_t alt_skp_sel                  : 2;  /**< Alternate skip selector
+                                                         When enabled (ALT_SKP_EN), selects which of the
+                                                         four PIP_ALT_SKIP_CFGx to use with the packets
+                                                         arriving on the port-kind. */
+	uint64_t alt_skp_en                   : 1;  /**< Enable the alternate skip selector
+                                                         When enabled, the HW is able to recompute the
+                                                         SKIP I value based on the packet contents.
+                                                         Up to two of the initial 64 bits of the header
+                                                         are used along with four PIP_ALT_SKIP_CFGx to
+                                                         determine the updated SKIP I value.
+                                                         The bits of the packet used should be present in
+                                                         all packets.
+                                                         PIP_PRT_CFG[DSA_EN,HIGIG_EN] must be disabled
+                                                         when ALT_SKP_EN is set.
+                                                         ALT_SKP_EN must not be set for DPI ports (32-35)
+                                                         when a PKT_INST_HDR is present.
+                                                         ALT_SKP_EN should not be enabled for ports which
+                                                         have GMX_RX_FRM_CTL[PTP_MODE] set as the timestamp
+                                                         will be prepended onto the initial 64 bits of the
+                                                         packet. */
+	uint64_t reserved_35_35               : 1;
+	uint64_t bsel_num                     : 2;  /**< Which of the 4 bit select extractors to use
+                                                         (Alias to PIP_PRT_CFG) */
+	uint64_t bsel_en                      : 1;  /**< Enable to turn on/off use of bit select extractor
+                                                         (Alias to PIP_PRT_CFG) */
+	uint64_t reserved_0_31                : 32;
+#else
+	uint64_t reserved_0_31                : 32;
+	uint64_t bsel_en                      : 1;
+	uint64_t bsel_num                     : 2;
+	uint64_t reserved_35_35               : 1;
+	uint64_t alt_skp_en                   : 1;
+	uint64_t alt_skp_sel                  : 2;
+	uint64_t reserved_39_63               : 25;
+#endif
+	} cn61xx;
+	struct cvmx_pip_prt_cfgbx_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_39_63               : 25;
+	uint64_t alt_skp_sel                  : 2;  /**< Alternate skip selector
+                                                         When enabled (ALT_SKP_EN), selects which of the
+                                                         four PIP_ALT_SKIP_CFGx to use with the packets
+                                                         arriving on the port-kind. */
+	uint64_t alt_skp_en                   : 1;  /**< Enable the alternate skip selector
+                                                         When enabled, the HW is able to recompute the
+                                                         SKIP I value based on the packet contents.
+                                                         Up to two of the initial 64 bits of the header
+                                                         are used along with four PIP_ALT_SKIP_CFGx to
+                                                         determine the updated SKIP I value.
+                                                         The bits of the packet used should be present in
+                                                         all packets.
+                                                         PIP_PRT_CFG[DSA_EN,HIGIG_EN] must be disabled
+                                                         when ALT_SKP_EN is set.
+                                                         ALT_SKP_EN must not be set for DPI ports (32-35)
+                                                         when a PKT_INST_HDR is present. */
+	uint64_t reserved_0_35                : 36;
+#else
+	uint64_t reserved_0_35                : 36;
+	uint64_t alt_skp_en                   : 1;
+	uint64_t alt_skp_sel                  : 2;
+	uint64_t reserved_39_63               : 25;
+#endif
+	} cn66xx;
+	struct cvmx_pip_prt_cfgbx_s           cn68xx;
+	struct cvmx_pip_prt_cfgbx_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_24_63               : 40;
+	uint64_t base                         : 8;  /**< Base priority address into the table */
+	uint64_t reserved_6_15                : 10;
+	uint64_t bpid                         : 6;  /**< Default BPID to use for packets on this port-kind. */
+#else
+	uint64_t bpid                         : 6;
+	uint64_t reserved_6_15                : 10;
+	uint64_t base                         : 8;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} cn68xxp1;
+	struct cvmx_pip_prt_cfgbx_cn61xx      cnf71xx;
+};
+typedef union cvmx_pip_prt_cfgbx cvmx_pip_prt_cfgbx_t;
+
+/**
  * cvmx_pip_prt_tag#
  *
  * PIP_PRT_TAGX = Per port config information
  *
  */
-union cvmx_pip_prt_tagx
-{
+union cvmx_pip_prt_tagx {
 	uint64_t u64;
-	struct cvmx_pip_prt_tagx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_40_63               : 24;
+	struct cvmx_pip_prt_tagx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t portadd_en                   : 1;  /**< Enables PIP to optionally increment the incoming
+                                                         port from the MACs based on port-kind
+                                                         configuration and packet contents. */
+	uint64_t inc_hwchk                    : 1;  /**< Include the HW_checksum into WORD0 of the WQE
+                                                         instead of the L4PTR.  This mode will be
+                                                         deprecated in future products. */
+	uint64_t reserved_50_51               : 2;
+	uint64_t grptagbase_msb               : 2;  /**< Most significant 2 bits of the GRPTAGBASE value. */
+	uint64_t reserved_46_47               : 2;
+	uint64_t grptagmask_msb               : 2;  /**< Most significant 2 bits of the GRPTAGMASK value.
+                                                         group when GRPTAG is set. */
+	uint64_t reserved_42_43               : 2;
+	uint64_t grp_msb                      : 2;  /**< Most significant 2 bits of the 6-bit value
+                                                         indicating the group to schedule to. */
 	uint64_t grptagbase                   : 4;  /**< Offset to use when computing group from tag bits
                                                          when GRPTAG is set. */
 	uint64_t grptagmask                   : 4;  /**< Which bits of the tag to exclude when computing
@@ -2555,12 +3946,19 @@ union cvmx_pip_prt_tagx
 	uint64_t grptag                       : 1;
 	uint64_t grptagmask                   : 4;
 	uint64_t grptagbase                   : 4;
-	uint64_t reserved_40_63               : 24;
+	uint64_t grp_msb                      : 2;
+	uint64_t reserved_42_43               : 2;
+	uint64_t grptagmask_msb               : 2;
+	uint64_t reserved_46_47               : 2;
+	uint64_t grptagbase_msb               : 2;
+	uint64_t reserved_50_51               : 2;
+	uint64_t inc_hwchk                    : 1;
+	uint64_t portadd_en                   : 1;
+	uint64_t reserved_54_63               : 10;
 #endif
 	} s;
-	struct cvmx_pip_prt_tagx_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_prt_tagx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t grptagbase                   : 4;  /**< Offset to use when computing group from tag bits
                                                          when GRPTAG is set. */
@@ -2658,15 +4056,116 @@ union cvmx_pip_prt_tagx
 	struct cvmx_pip_prt_tagx_cn30xx       cn31xx;
 	struct cvmx_pip_prt_tagx_cn30xx       cn38xx;
 	struct cvmx_pip_prt_tagx_cn30xx       cn38xxp2;
-	struct cvmx_pip_prt_tagx_s            cn50xx;
-	struct cvmx_pip_prt_tagx_s            cn52xx;
-	struct cvmx_pip_prt_tagx_s            cn52xxp1;
-	struct cvmx_pip_prt_tagx_s            cn56xx;
-	struct cvmx_pip_prt_tagx_s            cn56xxp1;
+	struct cvmx_pip_prt_tagx_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_40_63               : 24;
+	uint64_t grptagbase                   : 4;  /**< Offset to use when computing group from tag bits
+                                                         when GRPTAG is set. */
+	uint64_t grptagmask                   : 4;  /**< Which bits of the tag to exclude when computing
+                                                         group when GRPTAG is set. */
+	uint64_t grptag                       : 1;  /**< When set, use the lower bit of the tag to compute
+                                                         the group in the work queue entry
+                                                         GRP = WQE[TAG[3:0]] & ~GRPTAGMASK + GRPTAGBASE */
+	uint64_t grptag_mskip                 : 1;  /**< When set, GRPTAG will be used regardless if the
+                                                         packet IS_IP. */
+	uint64_t tag_mode                     : 2;  /**< Which tag algorithm to use
+                                                         0 = always use tuple tag algorithm
+                                                         1 = always use mask tag algorithm
+                                                         2 = if packet is IP, use tuple else use mask
+                                                         3 = tuple XOR mask */
+	uint64_t inc_vs                       : 2;  /**< determines the VLAN ID (VID) to be included in
+                                                         tuple tag when VLAN stacking is detected
+                                                         0 = do not include VID in tuple tag generation
+                                                         1 = include VID (VLAN0) in hash
+                                                         2 = include VID (VLAN1) in hash
+                                                         3 = include VID ([VLAN0,VLAN1]) in hash */
+	uint64_t inc_vlan                     : 1;  /**< when set, the VLAN ID is included in tuple tag
+                                                         when VLAN stacking is not detected
+                                                         0 = do not include VID in tuple tag generation
+                                                         1 = include VID in hash */
+	uint64_t inc_prt_flag                 : 1;  /**< sets whether the port is included in tuple tag */
+	uint64_t ip6_dprt_flag                : 1;  /**< sets whether the TCP/UDP dst port is
+                                                         included in tuple tag for IPv6 packets */
+	uint64_t ip4_dprt_flag                : 1;  /**< sets whether the TCP/UDP dst port is
+                                                         included in tuple tag for IPv4 */
+	uint64_t ip6_sprt_flag                : 1;  /**< sets whether the TCP/UDP src port is
+                                                         included in tuple tag for IPv6 packets */
+	uint64_t ip4_sprt_flag                : 1;  /**< sets whether the TCP/UDP src port is
+                                                         included in tuple tag for IPv4 */
+	uint64_t ip6_nxth_flag                : 1;  /**< sets whether ipv6 includes next header in tuple
+                                                         tag hash */
+	uint64_t ip4_pctl_flag                : 1;  /**< sets whether ipv4 includes protocol in tuple
+                                                         tag hash */
+	uint64_t ip6_dst_flag                 : 1;  /**< sets whether ipv6 includes dst address in tuple
+                                                         tag hash */
+	uint64_t ip4_dst_flag                 : 1;  /**< sets whether ipv4 includes dst address in tuple
+                                                         tag hash */
+	uint64_t ip6_src_flag                 : 1;  /**< sets whether ipv6 includes src address in tuple
+                                                         tag hash */
+	uint64_t ip4_src_flag                 : 1;  /**< sets whether ipv4 includes src address in tuple
+                                                         tag hash */
+	cvmx_pow_tag_type_t tcp6_tag_type     : 2;  /**< sets the tag_type of a TCP packet (IPv6)
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+	cvmx_pow_tag_type_t tcp4_tag_type     : 2;  /**< sets the tag_type of a TCP packet (IPv4)
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+	cvmx_pow_tag_type_t ip6_tag_type      : 2;  /**< sets whether IPv6 packet tag type
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+	cvmx_pow_tag_type_t ip4_tag_type      : 2;  /**< sets whether IPv4 packet tag type
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+	cvmx_pow_tag_type_t non_tag_type      : 2;  /**< sets whether non-IP packet tag type
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+	uint64_t grp                          : 4;  /**< 4-bit value indicating the group to schedule to */
+#else
+	uint64_t grp                          : 4;
+	cvmx_pow_tag_type_t non_tag_type      : 2;
+	cvmx_pow_tag_type_t ip4_tag_type      : 2;
+	cvmx_pow_tag_type_t ip6_tag_type      : 2;
+	cvmx_pow_tag_type_t tcp4_tag_type     : 2;
+	cvmx_pow_tag_type_t tcp6_tag_type     : 2;
+	uint64_t ip4_src_flag                 : 1;
+	uint64_t ip6_src_flag                 : 1;
+	uint64_t ip4_dst_flag                 : 1;
+	uint64_t ip6_dst_flag                 : 1;
+	uint64_t ip4_pctl_flag                : 1;
+	uint64_t ip6_nxth_flag                : 1;
+	uint64_t ip4_sprt_flag                : 1;
+	uint64_t ip6_sprt_flag                : 1;
+	uint64_t ip4_dprt_flag                : 1;
+	uint64_t ip6_dprt_flag                : 1;
+	uint64_t inc_prt_flag                 : 1;
+	uint64_t inc_vlan                     : 1;
+	uint64_t inc_vs                       : 2;
+	uint64_t tag_mode                     : 2;
+	uint64_t grptag_mskip                 : 1;
+	uint64_t grptag                       : 1;
+	uint64_t grptagmask                   : 4;
+	uint64_t grptagbase                   : 4;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} cn50xx;
+	struct cvmx_pip_prt_tagx_cn50xx       cn52xx;
+	struct cvmx_pip_prt_tagx_cn50xx       cn52xxp1;
+	struct cvmx_pip_prt_tagx_cn50xx       cn56xx;
+	struct cvmx_pip_prt_tagx_cn50xx       cn56xxp1;
 	struct cvmx_pip_prt_tagx_cn30xx       cn58xx;
 	struct cvmx_pip_prt_tagx_cn30xx       cn58xxp1;
-	struct cvmx_pip_prt_tagx_s            cn63xx;
-	struct cvmx_pip_prt_tagx_s            cn63xxp1;
+	struct cvmx_pip_prt_tagx_cn50xx       cn61xx;
+	struct cvmx_pip_prt_tagx_cn50xx       cn63xx;
+	struct cvmx_pip_prt_tagx_cn50xx       cn63xxp1;
+	struct cvmx_pip_prt_tagx_cn50xx       cn66xx;
+	struct cvmx_pip_prt_tagx_s            cn68xx;
+	struct cvmx_pip_prt_tagx_s            cn68xxp1;
+	struct cvmx_pip_prt_tagx_cn50xx       cnf71xx;
 };
 typedef union cvmx_pip_prt_tagx cvmx_pip_prt_tagx_t;
 
@@ -2676,12 +4175,10 @@ typedef union cvmx_pip_prt_tagx cvmx_pip_prt_tagx_t;
  * PIP_QOS_DIFFX = QOS Diffserv Tables
  *
  */
-union cvmx_pip_qos_diffx
-{
+union cvmx_pip_qos_diffx {
 	uint64_t u64;
-	struct cvmx_pip_qos_diffx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_qos_diffx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t qos                          : 3;  /**< Diffserv QOS level */
 #else
@@ -2700,8 +4197,11 @@ union cvmx_pip_qos_diffx
 	struct cvmx_pip_qos_diffx_s           cn56xxp1;
 	struct cvmx_pip_qos_diffx_s           cn58xx;
 	struct cvmx_pip_qos_diffx_s           cn58xxp1;
+	struct cvmx_pip_qos_diffx_s           cn61xx;
 	struct cvmx_pip_qos_diffx_s           cn63xx;
 	struct cvmx_pip_qos_diffx_s           cn63xxp1;
+	struct cvmx_pip_qos_diffx_s           cn66xx;
+	struct cvmx_pip_qos_diffx_s           cnf71xx;
 };
 typedef union cvmx_pip_qos_diffx cvmx_pip_qos_diffx_t;
 
@@ -2714,12 +4214,10 @@ typedef union cvmx_pip_qos_diffx cvmx_pip_qos_diffx_t;
  * can be set based on the DSA/VLAN user priority.  These eight register
  * comprise the QOS values for all DSA/VLAN user priority values.
  */
-union cvmx_pip_qos_vlanx
-{
+union cvmx_pip_qos_vlanx {
 	uint64_t u64;
-	struct cvmx_pip_qos_vlanx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_qos_vlanx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t qos1                         : 3;  /**< DSA/VLAN QOS level
                                                          Selected when PIP_PRT_CFGx[QOS_VSEL] = 1 */
@@ -2733,9 +4231,8 @@ union cvmx_pip_qos_vlanx
 	uint64_t reserved_7_63                : 57;
 #endif
 	} s;
-	struct cvmx_pip_qos_vlanx_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_qos_vlanx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t qos                          : 3;  /**< VLAN QOS level */
 #else
@@ -2753,8 +4250,11 @@ union cvmx_pip_qos_vlanx
 	struct cvmx_pip_qos_vlanx_cn30xx      cn56xxp1;
 	struct cvmx_pip_qos_vlanx_cn30xx      cn58xx;
 	struct cvmx_pip_qos_vlanx_cn30xx      cn58xxp1;
+	struct cvmx_pip_qos_vlanx_s           cn61xx;
 	struct cvmx_pip_qos_vlanx_s           cn63xx;
 	struct cvmx_pip_qos_vlanx_s           cn63xxp1;
+	struct cvmx_pip_qos_vlanx_s           cn66xx;
+	struct cvmx_pip_qos_vlanx_s           cnf71xx;
 };
 typedef union cvmx_pip_qos_vlanx cvmx_pip_qos_vlanx_t;
 
@@ -2768,16 +4268,14 @@ typedef union cvmx_pip_qos_vlanx cvmx_pip_qos_vlanx_t;
  * TCP/UDP destination port, or Ethertype to override the
  * default QOS value.
  */
-union cvmx_pip_qos_watchx
-{
+union cvmx_pip_qos_watchx {
 	uint64_t u64;
-	struct cvmx_pip_qos_watchx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_qos_watchx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t mask                         : 16; /**< Mask off a range of values */
-	uint64_t reserved_28_31               : 4;
-	uint64_t grp                          : 4;  /**< The GRP number of the watcher */
+	uint64_t reserved_30_31               : 2;
+	uint64_t grp                          : 6;  /**< The GRP number of the watcher */
 	uint64_t reserved_23_23               : 1;
 	uint64_t qos                          : 3;  /**< The QOS level of the watcher */
 	uint64_t reserved_19_19               : 1;
@@ -2796,15 +4294,14 @@ union cvmx_pip_qos_watchx
 	uint64_t reserved_19_19               : 1;
 	uint64_t qos                          : 3;
 	uint64_t reserved_23_23               : 1;
-	uint64_t grp                          : 4;
-	uint64_t reserved_28_31               : 4;
+	uint64_t grp                          : 6;
+	uint64_t reserved_30_31               : 2;
 	uint64_t mask                         : 16;
 	uint64_t reserved_48_63               : 16;
 #endif
 	} s;
-	struct cvmx_pip_qos_watchx_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_qos_watchx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t mask                         : 16; /**< Mask off a range of values */
 	uint64_t reserved_28_31               : 4;
@@ -2834,15 +4331,49 @@ union cvmx_pip_qos_watchx
 	struct cvmx_pip_qos_watchx_cn30xx     cn31xx;
 	struct cvmx_pip_qos_watchx_cn30xx     cn38xx;
 	struct cvmx_pip_qos_watchx_cn30xx     cn38xxp2;
-	struct cvmx_pip_qos_watchx_s          cn50xx;
-	struct cvmx_pip_qos_watchx_s          cn52xx;
-	struct cvmx_pip_qos_watchx_s          cn52xxp1;
-	struct cvmx_pip_qos_watchx_s          cn56xx;
-	struct cvmx_pip_qos_watchx_s          cn56xxp1;
+	struct cvmx_pip_qos_watchx_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_48_63               : 16;
+	uint64_t mask                         : 16; /**< Mask off a range of values */
+	uint64_t reserved_28_31               : 4;
+	uint64_t grp                          : 4;  /**< The GRP number of the watcher */
+	uint64_t reserved_23_23               : 1;
+	uint64_t qos                          : 3;  /**< The QOS level of the watcher */
+	uint64_t reserved_19_19               : 1;
+	cvmx_pip_qos_watch_types match_type   : 3;  /**< The field for the watcher match against
+                                                         0   = disable across all ports
+                                                         1   = protocol (ipv4)
+                                                             = next_header (ipv6)
+                                                         2   = TCP destination port
+                                                         3   = UDP destination port
+                                                         4   = Ether type
+                                                         5-7 = Reserved */
+	uint64_t match_value                  : 16; /**< The value to watch for */
+#else
+	uint64_t match_value                  : 16;
+	cvmx_pip_qos_watch_types match_type   : 3;
+	uint64_t reserved_19_19               : 1;
+	uint64_t qos                          : 3;
+	uint64_t reserved_23_23               : 1;
+	uint64_t grp                          : 4;
+	uint64_t reserved_28_31               : 4;
+	uint64_t mask                         : 16;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} cn50xx;
+	struct cvmx_pip_qos_watchx_cn50xx     cn52xx;
+	struct cvmx_pip_qos_watchx_cn50xx     cn52xxp1;
+	struct cvmx_pip_qos_watchx_cn50xx     cn56xx;
+	struct cvmx_pip_qos_watchx_cn50xx     cn56xxp1;
 	struct cvmx_pip_qos_watchx_cn30xx     cn58xx;
 	struct cvmx_pip_qos_watchx_cn30xx     cn58xxp1;
-	struct cvmx_pip_qos_watchx_s          cn63xx;
-	struct cvmx_pip_qos_watchx_s          cn63xxp1;
+	struct cvmx_pip_qos_watchx_cn50xx     cn61xx;
+	struct cvmx_pip_qos_watchx_cn50xx     cn63xx;
+	struct cvmx_pip_qos_watchx_cn50xx     cn63xxp1;
+	struct cvmx_pip_qos_watchx_cn50xx     cn66xx;
+	struct cvmx_pip_qos_watchx_s          cn68xx;
+	struct cvmx_pip_qos_watchx_s          cn68xxp1;
+	struct cvmx_pip_qos_watchx_cn50xx     cnf71xx;
 };
 typedef union cvmx_pip_qos_watchx cvmx_pip_qos_watchx_t;
 
@@ -2853,12 +4384,10 @@ typedef union cvmx_pip_qos_watchx cvmx_pip_qos_watchx_t;
  *
  * The RAW Word2 to be inserted into the workQ entry of RAWFULL packets.
  */
-union cvmx_pip_raw_word
-{
+union cvmx_pip_raw_word {
 	uint64_t u64;
-	struct cvmx_pip_raw_word_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_raw_word_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_56_63               : 8;
 	uint64_t word                         : 56; /**< Word2 of the workQ entry
                                                          The 8-bit bufs field is still set by HW (IPD) */
@@ -2878,8 +4407,13 @@ union cvmx_pip_raw_word
 	struct cvmx_pip_raw_word_s            cn56xxp1;
 	struct cvmx_pip_raw_word_s            cn58xx;
 	struct cvmx_pip_raw_word_s            cn58xxp1;
+	struct cvmx_pip_raw_word_s            cn61xx;
 	struct cvmx_pip_raw_word_s            cn63xx;
 	struct cvmx_pip_raw_word_s            cn63xxp1;
+	struct cvmx_pip_raw_word_s            cn66xx;
+	struct cvmx_pip_raw_word_s            cn68xx;
+	struct cvmx_pip_raw_word_s            cn68xxp1;
+	struct cvmx_pip_raw_word_s            cnf71xx;
 };
 typedef union cvmx_pip_raw_word cvmx_pip_raw_word_t;
 
@@ -2921,12 +4455,10 @@ typedef union cvmx_pip_raw_word cvmx_pip_raw_word_t;
  * . PIP_STAT_INB_ERRS*
  * . PIP_TAG_INC*
  */
-union cvmx_pip_sft_rst
-{
+union cvmx_pip_sft_rst {
 	uint64_t u64;
-	struct cvmx_pip_sft_rst_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_sft_rst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t rst                          : 1;  /**< Soft Reset */
 #else
@@ -2944,12 +4476,64 @@ union cvmx_pip_sft_rst
 	struct cvmx_pip_sft_rst_s             cn56xxp1;
 	struct cvmx_pip_sft_rst_s             cn58xx;
 	struct cvmx_pip_sft_rst_s             cn58xxp1;
+	struct cvmx_pip_sft_rst_s             cn61xx;
 	struct cvmx_pip_sft_rst_s             cn63xx;
 	struct cvmx_pip_sft_rst_s             cn63xxp1;
+	struct cvmx_pip_sft_rst_s             cn66xx;
+	struct cvmx_pip_sft_rst_s             cn68xx;
+	struct cvmx_pip_sft_rst_s             cn68xxp1;
+	struct cvmx_pip_sft_rst_s             cnf71xx;
 };
 typedef union cvmx_pip_sft_rst cvmx_pip_sft_rst_t;
 
 /**
+ * cvmx_pip_stat0_#
+ *
+ * PIP Statistics Counters
+ *
+ * Note: special stat counter behavior
+ *
+ * 1) Read and write operations must arbitrate for the statistics resources
+ *     along with the packet engines which are incrementing the counters.
+ *     In order to not drop packet information, the packet HW is always a
+ *     higher priority and the CSR requests will only be satisified when
+ *     there are idle cycles.  This can potentially cause long delays if the
+ *     system becomes full.
+ *
+ * 2) stat counters can be cleared in two ways.  If PIP_STAT_CTL[RDCLR] is
+ *     set, then all read accesses will clear the register.  In addition,
+ *     any write to a stats register will also reset the register to zero.
+ *     Please note that the clearing operations must obey rule \#1 above.
+ *
+ * 3) all counters are wrapping - software must ensure they are read periodically
+ *
+ * 4) The counters accumulate statistics for packets that are sent to PKI.  If
+ *    PTP_MODE is enabled, the 8B timestamp is prepended to the packet.  This
+ *    additional 8B of data is captured in the octet counts.
+ *
+ * 5) X represents either the packet's port-kind or backpressure ID as
+ *    determined by PIP_STAT_CTL[MODE]
+ * PIP_STAT0_X = PIP_STAT_DRP_PKTS / PIP_STAT_DRP_OCTS
+ */
+union cvmx_pip_stat0_x {
+	uint64_t u64;
+	struct cvmx_pip_stat0_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t drp_pkts                     : 32; /**< Inbound packets marked to be dropped by the IPD
+                                                         QOS widget per port */
+	uint64_t drp_octs                     : 32; /**< Inbound octets marked to be dropped by the IPD
+                                                         QOS widget per port */
+#else
+	uint64_t drp_octs                     : 32;
+	uint64_t drp_pkts                     : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat0_x_s             cn68xx;
+	struct cvmx_pip_stat0_x_s             cn68xxp1;
+};
+typedef union cvmx_pip_stat0_x cvmx_pip_stat0_x_t;
+
+/**
  * cvmx_pip_stat0_prt#
  *
  * PIP Statistics Counters
@@ -2975,12 +4559,10 @@ typedef union cvmx_pip_sft_rst cvmx_pip_sft_rst_t;
  *    additional 8B of data is captured in the octet counts.
  * PIP_STAT0_PRT = PIP_STAT_DRP_PKTS / PIP_STAT_DRP_OCTS
  */
-union cvmx_pip_stat0_prtx
-{
+union cvmx_pip_stat0_prtx {
 	uint64_t u64;
-	struct cvmx_pip_stat0_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_stat0_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t drp_pkts                     : 32; /**< Inbound packets marked to be dropped by the IPD
                                                          QOS widget per port */
 	uint64_t drp_octs                     : 32; /**< Inbound octets marked to be dropped by the IPD
@@ -3001,23 +4583,208 @@ union cvmx_pip_stat0_prtx
 	struct cvmx_pip_stat0_prtx_s          cn56xxp1;
 	struct cvmx_pip_stat0_prtx_s          cn58xx;
 	struct cvmx_pip_stat0_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat0_prtx_s          cn61xx;
 	struct cvmx_pip_stat0_prtx_s          cn63xx;
 	struct cvmx_pip_stat0_prtx_s          cn63xxp1;
+	struct cvmx_pip_stat0_prtx_s          cn66xx;
+	struct cvmx_pip_stat0_prtx_s          cnf71xx;
 };
 typedef union cvmx_pip_stat0_prtx cvmx_pip_stat0_prtx_t;
 
 /**
+ * cvmx_pip_stat10_#
+ *
+ * PIP_STAT10_X = PIP_STAT_L2_MCAST / PIP_STAT_L2_BCAST
+ *
+ */
+union cvmx_pip_stat10_x {
+	uint64_t u64;
+	struct cvmx_pip_stat10_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bcast                        : 32; /**< Number of packets with L2 Broadcast DMAC
+                                                         that were dropped due to RED.
+                                                         The HW will consider a packet to be an L2
+                                                         broadcast packet when the 48-bit DMAC is all 1's.
+                                                         Only applies when the parse mode for the packet
+                                                         is SKIP-TO-L2. */
+	uint64_t mcast                        : 32; /**< Number of packets with L2 Mulitcast DMAC
+                                                         that were dropped due to RED.
+                                                         The HW will consider a packet to be an L2
+                                                         multicast packet when the least-significant bit
+                                                         of the first byte of the DMAC is set and the
+                                                         packet is not an L2 broadcast packet.
+                                                         Only applies when the parse mode for the packet
+                                                         is SKIP-TO-L2. */
+#else
+	uint64_t mcast                        : 32;
+	uint64_t bcast                        : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat10_x_s            cn68xx;
+	struct cvmx_pip_stat10_x_s            cn68xxp1;
+};
+typedef union cvmx_pip_stat10_x cvmx_pip_stat10_x_t;
+
+/**
+ * cvmx_pip_stat10_prt#
+ *
+ * PIP_STAT10_PRTX = PIP_STAT_L2_MCAST / PIP_STAT_L2_BCAST
+ *
+ */
+union cvmx_pip_stat10_prtx {
+	uint64_t u64;
+	struct cvmx_pip_stat10_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bcast                        : 32; /**< Number of packets with L2 Broadcast DMAC
+                                                         that were dropped due to RED.
+                                                         The HW will consider a packet to be an L2
+                                                         broadcast packet when the 48-bit DMAC is all 1's.
+                                                         Only applies when the parse mode for the packet
+                                                         is SKIP-TO-L2. */
+	uint64_t mcast                        : 32; /**< Number of packets with L2 Mulitcast DMAC
+                                                         that were dropped due to RED.
+                                                         The HW will consider a packet to be an L2
+                                                         multicast packet when the least-significant bit
+                                                         of the first byte of the DMAC is set and the
+                                                         packet is not an L2 broadcast packet.
+                                                         Only applies when the parse mode for the packet
+                                                         is SKIP-TO-L2. */
+#else
+	uint64_t mcast                        : 32;
+	uint64_t bcast                        : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat10_prtx_s         cn52xx;
+	struct cvmx_pip_stat10_prtx_s         cn52xxp1;
+	struct cvmx_pip_stat10_prtx_s         cn56xx;
+	struct cvmx_pip_stat10_prtx_s         cn56xxp1;
+	struct cvmx_pip_stat10_prtx_s         cn61xx;
+	struct cvmx_pip_stat10_prtx_s         cn63xx;
+	struct cvmx_pip_stat10_prtx_s         cn63xxp1;
+	struct cvmx_pip_stat10_prtx_s         cn66xx;
+	struct cvmx_pip_stat10_prtx_s         cnf71xx;
+};
+typedef union cvmx_pip_stat10_prtx cvmx_pip_stat10_prtx_t;
+
+/**
+ * cvmx_pip_stat11_#
+ *
+ * PIP_STAT11_X = PIP_STAT_L3_MCAST / PIP_STAT_L3_BCAST
+ *
+ */
+union cvmx_pip_stat11_x {
+	uint64_t u64;
+	struct cvmx_pip_stat11_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bcast                        : 32; /**< Number of packets with L3 Broadcast Dest Address
+                                                         that were dropped due to RED.
+                                                         The HW considers an IPv4 packet to be broadcast
+                                                         when all bits are set in the MSB of the
+                                                         destination address. IPv6 does not have the
+                                                         concept of a broadcast packets.
+                                                         Only applies when the parse mode for the packet
+                                                         is SKIP-TO-L2 and the packet is IP or the parse
+                                                         mode for the packet is SKIP-TO-IP. */
+	uint64_t mcast                        : 32; /**< Number of packets with L3 Multicast Dest Address
+                                                         that were dropped due to RED.
+                                                         The HW considers an IPv4 packet to be multicast
+                                                         when the most-significant nibble of the 32-bit
+                                                         destination address is 0xE (i.e. it is a class D
+                                                         address). The HW considers an IPv6 packet to be
+                                                         multicast when the most-significant byte of the
+                                                         128-bit destination address is all 1's.
+                                                         Only applies when the parse mode for the packet
+                                                         is SKIP-TO-L2 and the packet is IP or the parse
+                                                         mode for the packet is SKIP-TO-IP. */
+#else
+	uint64_t mcast                        : 32;
+	uint64_t bcast                        : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat11_x_s            cn68xx;
+	struct cvmx_pip_stat11_x_s            cn68xxp1;
+};
+typedef union cvmx_pip_stat11_x cvmx_pip_stat11_x_t;
+
+/**
+ * cvmx_pip_stat11_prt#
+ *
+ * PIP_STAT11_PRTX = PIP_STAT_L3_MCAST / PIP_STAT_L3_BCAST
+ *
+ */
+union cvmx_pip_stat11_prtx {
+	uint64_t u64;
+	struct cvmx_pip_stat11_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bcast                        : 32; /**< Number of packets with L3 Broadcast Dest Address
+                                                         that were dropped due to RED.
+                                                         The HW considers an IPv4 packet to be broadcast
+                                                         when all bits are set in the MSB of the
+                                                         destination address. IPv6 does not have the
+                                                         concept of a broadcast packets.
+                                                         Only applies when the parse mode for the packet
+                                                         is SKIP-TO-L2 and the packet is IP or the parse
+                                                         mode for the packet is SKIP-TO-IP. */
+	uint64_t mcast                        : 32; /**< Number of packets with L3 Multicast Dest Address
+                                                         that were dropped due to RED.
+                                                         The HW considers an IPv4 packet to be multicast
+                                                         when the most-significant nibble of the 32-bit
+                                                         destination address is 0xE (i.e. it is a class D
+                                                         address). The HW considers an IPv6 packet to be
+                                                         multicast when the most-significant byte of the
+                                                         128-bit destination address is all 1's.
+                                                         Only applies when the parse mode for the packet
+                                                         is SKIP-TO-L2 and the packet is IP or the parse
+                                                         mode for the packet is SKIP-TO-IP. */
+#else
+	uint64_t mcast                        : 32;
+	uint64_t bcast                        : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat11_prtx_s         cn52xx;
+	struct cvmx_pip_stat11_prtx_s         cn52xxp1;
+	struct cvmx_pip_stat11_prtx_s         cn56xx;
+	struct cvmx_pip_stat11_prtx_s         cn56xxp1;
+	struct cvmx_pip_stat11_prtx_s         cn61xx;
+	struct cvmx_pip_stat11_prtx_s         cn63xx;
+	struct cvmx_pip_stat11_prtx_s         cn63xxp1;
+	struct cvmx_pip_stat11_prtx_s         cn66xx;
+	struct cvmx_pip_stat11_prtx_s         cnf71xx;
+};
+typedef union cvmx_pip_stat11_prtx cvmx_pip_stat11_prtx_t;
+
+/**
+ * cvmx_pip_stat1_#
+ *
+ * PIP_STAT1_X = PIP_STAT_OCTS
+ *
+ */
+union cvmx_pip_stat1_x {
+	uint64_t u64;
+	struct cvmx_pip_stat1_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_48_63               : 16;
+	uint64_t octs                         : 48; /**< Number of octets received by PIP (good and bad) */
+#else
+	uint64_t octs                         : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_pip_stat1_x_s             cn68xx;
+	struct cvmx_pip_stat1_x_s             cn68xxp1;
+};
+typedef union cvmx_pip_stat1_x cvmx_pip_stat1_x_t;
+
+/**
  * cvmx_pip_stat1_prt#
  *
  * PIP_STAT1_PRTX = PIP_STAT_OCTS
  *
  */
-union cvmx_pip_stat1_prtx
-{
+union cvmx_pip_stat1_prtx {
 	uint64_t u64;
-	struct cvmx_pip_stat1_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_stat1_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t octs                         : 48; /**< Number of octets received by PIP (good and bad) */
 #else
@@ -3036,23 +4803,47 @@ union cvmx_pip_stat1_prtx
 	struct cvmx_pip_stat1_prtx_s          cn56xxp1;
 	struct cvmx_pip_stat1_prtx_s          cn58xx;
 	struct cvmx_pip_stat1_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat1_prtx_s          cn61xx;
 	struct cvmx_pip_stat1_prtx_s          cn63xx;
 	struct cvmx_pip_stat1_prtx_s          cn63xxp1;
+	struct cvmx_pip_stat1_prtx_s          cn66xx;
+	struct cvmx_pip_stat1_prtx_s          cnf71xx;
 };
 typedef union cvmx_pip_stat1_prtx cvmx_pip_stat1_prtx_t;
 
 /**
+ * cvmx_pip_stat2_#
+ *
+ * PIP_STAT2_X = PIP_STAT_PKTS     / PIP_STAT_RAW
+ *
+ */
+union cvmx_pip_stat2_x {
+	uint64_t u64;
+	struct cvmx_pip_stat2_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t pkts                         : 32; /**< Number of packets processed by PIP */
+	uint64_t raw                          : 32; /**< RAWFULL + RAWSCH Packets without an L1/L2 error
+                                                         received by PIP per port */
+#else
+	uint64_t raw                          : 32;
+	uint64_t pkts                         : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat2_x_s             cn68xx;
+	struct cvmx_pip_stat2_x_s             cn68xxp1;
+};
+typedef union cvmx_pip_stat2_x cvmx_pip_stat2_x_t;
+
+/**
  * cvmx_pip_stat2_prt#
  *
  * PIP_STAT2_PRTX = PIP_STAT_PKTS     / PIP_STAT_RAW
  *
  */
-union cvmx_pip_stat2_prtx
-{
+union cvmx_pip_stat2_prtx {
 	uint64_t u64;
-	struct cvmx_pip_stat2_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_stat2_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t pkts                         : 32; /**< Number of packets processed by PIP */
 	uint64_t raw                          : 32; /**< RAWFULL + RAWSCH Packets without an L1/L2 error
                                                          received by PIP per port */
@@ -3072,23 +4863,52 @@ union cvmx_pip_stat2_prtx
 	struct cvmx_pip_stat2_prtx_s          cn56xxp1;
 	struct cvmx_pip_stat2_prtx_s          cn58xx;
 	struct cvmx_pip_stat2_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat2_prtx_s          cn61xx;
 	struct cvmx_pip_stat2_prtx_s          cn63xx;
 	struct cvmx_pip_stat2_prtx_s          cn63xxp1;
+	struct cvmx_pip_stat2_prtx_s          cn66xx;
+	struct cvmx_pip_stat2_prtx_s          cnf71xx;
 };
 typedef union cvmx_pip_stat2_prtx cvmx_pip_stat2_prtx_t;
 
 /**
+ * cvmx_pip_stat3_#
+ *
+ * PIP_STAT3_X = PIP_STAT_BCST     / PIP_STAT_MCST
+ *
+ */
+union cvmx_pip_stat3_x {
+	uint64_t u64;
+	struct cvmx_pip_stat3_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bcst                         : 32; /**< Number of indentified L2 broadcast packets
+                                                         Does not include multicast packets
+                                                         Only includes packets whose parse mode is
+                                                         SKIP_TO_L2. */
+	uint64_t mcst                         : 32; /**< Number of indentified L2 multicast packets
+                                                         Does not include broadcast packets
+                                                         Only includes packets whose parse mode is
+                                                         SKIP_TO_L2. */
+#else
+	uint64_t mcst                         : 32;
+	uint64_t bcst                         : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat3_x_s             cn68xx;
+	struct cvmx_pip_stat3_x_s             cn68xxp1;
+};
+typedef union cvmx_pip_stat3_x cvmx_pip_stat3_x_t;
+
+/**
  * cvmx_pip_stat3_prt#
  *
  * PIP_STAT3_PRTX = PIP_STAT_BCST     / PIP_STAT_MCST
  *
  */
-union cvmx_pip_stat3_prtx
-{
+union cvmx_pip_stat3_prtx {
 	uint64_t u64;
-	struct cvmx_pip_stat3_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_stat3_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bcst                         : 32; /**< Number of indentified L2 broadcast packets
                                                          Does not include multicast packets
                                                          Only includes packets whose parse mode is
@@ -3113,23 +4933,46 @@ union cvmx_pip_stat3_prtx
 	struct cvmx_pip_stat3_prtx_s          cn56xxp1;
 	struct cvmx_pip_stat3_prtx_s          cn58xx;
 	struct cvmx_pip_stat3_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat3_prtx_s          cn61xx;
 	struct cvmx_pip_stat3_prtx_s          cn63xx;
 	struct cvmx_pip_stat3_prtx_s          cn63xxp1;
+	struct cvmx_pip_stat3_prtx_s          cn66xx;
+	struct cvmx_pip_stat3_prtx_s          cnf71xx;
 };
 typedef union cvmx_pip_stat3_prtx cvmx_pip_stat3_prtx_t;
 
 /**
+ * cvmx_pip_stat4_#
+ *
+ * PIP_STAT4_X = PIP_STAT_HIST1    / PIP_STAT_HIST0
+ *
+ */
+union cvmx_pip_stat4_x {
+	uint64_t u64;
+	struct cvmx_pip_stat4_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t h65to127                     : 32; /**< Number of 65-127B packets */
+	uint64_t h64                          : 32; /**< Number of 1-64B packets */
+#else
+	uint64_t h64                          : 32;
+	uint64_t h65to127                     : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat4_x_s             cn68xx;
+	struct cvmx_pip_stat4_x_s             cn68xxp1;
+};
+typedef union cvmx_pip_stat4_x cvmx_pip_stat4_x_t;
+
+/**
  * cvmx_pip_stat4_prt#
  *
  * PIP_STAT4_PRTX = PIP_STAT_HIST1    / PIP_STAT_HIST0
  *
  */
-union cvmx_pip_stat4_prtx
-{
+union cvmx_pip_stat4_prtx {
 	uint64_t u64;
-	struct cvmx_pip_stat4_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_stat4_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t h65to127                     : 32; /**< Number of 65-127B packets */
 	uint64_t h64                          : 32; /**< Number of 1-64B packets */
 #else
@@ -3148,23 +4991,46 @@ union cvmx_pip_stat4_prtx
 	struct cvmx_pip_stat4_prtx_s          cn56xxp1;
 	struct cvmx_pip_stat4_prtx_s          cn58xx;
 	struct cvmx_pip_stat4_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat4_prtx_s          cn61xx;
 	struct cvmx_pip_stat4_prtx_s          cn63xx;
 	struct cvmx_pip_stat4_prtx_s          cn63xxp1;
+	struct cvmx_pip_stat4_prtx_s          cn66xx;
+	struct cvmx_pip_stat4_prtx_s          cnf71xx;
 };
 typedef union cvmx_pip_stat4_prtx cvmx_pip_stat4_prtx_t;
 
 /**
+ * cvmx_pip_stat5_#
+ *
+ * PIP_STAT5_X = PIP_STAT_HIST3    / PIP_STAT_HIST2
+ *
+ */
+union cvmx_pip_stat5_x {
+	uint64_t u64;
+	struct cvmx_pip_stat5_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t h256to511                    : 32; /**< Number of 256-511B packets */
+	uint64_t h128to255                    : 32; /**< Number of 128-255B packets */
+#else
+	uint64_t h128to255                    : 32;
+	uint64_t h256to511                    : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat5_x_s             cn68xx;
+	struct cvmx_pip_stat5_x_s             cn68xxp1;
+};
+typedef union cvmx_pip_stat5_x cvmx_pip_stat5_x_t;
+
+/**
  * cvmx_pip_stat5_prt#
  *
  * PIP_STAT5_PRTX = PIP_STAT_HIST3    / PIP_STAT_HIST2
  *
  */
-union cvmx_pip_stat5_prtx
-{
+union cvmx_pip_stat5_prtx {
 	uint64_t u64;
-	struct cvmx_pip_stat5_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_stat5_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t h256to511                    : 32; /**< Number of 256-511B packets */
 	uint64_t h128to255                    : 32; /**< Number of 128-255B packets */
 #else
@@ -3183,23 +5049,46 @@ union cvmx_pip_stat5_prtx
 	struct cvmx_pip_stat5_prtx_s          cn56xxp1;
 	struct cvmx_pip_stat5_prtx_s          cn58xx;
 	struct cvmx_pip_stat5_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat5_prtx_s          cn61xx;
 	struct cvmx_pip_stat5_prtx_s          cn63xx;
 	struct cvmx_pip_stat5_prtx_s          cn63xxp1;
+	struct cvmx_pip_stat5_prtx_s          cn66xx;
+	struct cvmx_pip_stat5_prtx_s          cnf71xx;
 };
 typedef union cvmx_pip_stat5_prtx cvmx_pip_stat5_prtx_t;
 
 /**
+ * cvmx_pip_stat6_#
+ *
+ * PIP_STAT6_X = PIP_STAT_HIST5    / PIP_STAT_HIST4
+ *
+ */
+union cvmx_pip_stat6_x {
+	uint64_t u64;
+	struct cvmx_pip_stat6_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t h1024to1518                  : 32; /**< Number of 1024-1518B packets */
+	uint64_t h512to1023                   : 32; /**< Number of 512-1023B packets */
+#else
+	uint64_t h512to1023                   : 32;
+	uint64_t h1024to1518                  : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat6_x_s             cn68xx;
+	struct cvmx_pip_stat6_x_s             cn68xxp1;
+};
+typedef union cvmx_pip_stat6_x cvmx_pip_stat6_x_t;
+
+/**
  * cvmx_pip_stat6_prt#
  *
  * PIP_STAT6_PRTX = PIP_STAT_HIST5    / PIP_STAT_HIST4
  *
  */
-union cvmx_pip_stat6_prtx
-{
+union cvmx_pip_stat6_prtx {
 	uint64_t u64;
-	struct cvmx_pip_stat6_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_stat6_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t h1024to1518                  : 32; /**< Number of 1024-1518B packets */
 	uint64_t h512to1023                   : 32; /**< Number of 512-1023B packets */
 #else
@@ -3218,27 +5107,50 @@ union cvmx_pip_stat6_prtx
 	struct cvmx_pip_stat6_prtx_s          cn56xxp1;
 	struct cvmx_pip_stat6_prtx_s          cn58xx;
 	struct cvmx_pip_stat6_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat6_prtx_s          cn61xx;
 	struct cvmx_pip_stat6_prtx_s          cn63xx;
 	struct cvmx_pip_stat6_prtx_s          cn63xxp1;
+	struct cvmx_pip_stat6_prtx_s          cn66xx;
+	struct cvmx_pip_stat6_prtx_s          cnf71xx;
 };
 typedef union cvmx_pip_stat6_prtx cvmx_pip_stat6_prtx_t;
 
 /**
+ * cvmx_pip_stat7_#
+ *
+ * PIP_STAT7_X = PIP_STAT_FCS      / PIP_STAT_HIST6
+ *
+ */
+union cvmx_pip_stat7_x {
+	uint64_t u64;
+	struct cvmx_pip_stat7_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t fcs                          : 32; /**< Number of packets with FCS or Align opcode errors */
+	uint64_t h1519                        : 32; /**< Number of 1519-max packets */
+#else
+	uint64_t h1519                        : 32;
+	uint64_t fcs                          : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat7_x_s             cn68xx;
+	struct cvmx_pip_stat7_x_s             cn68xxp1;
+};
+typedef union cvmx_pip_stat7_x cvmx_pip_stat7_x_t;
+
+/**
  * cvmx_pip_stat7_prt#
  *
  * PIP_STAT7_PRTX = PIP_STAT_FCS      / PIP_STAT_HIST6
  *
  *
  * Notes:
- * Note: FCS is not checked on the PCI ports 32..35.
- *
+ * DPI does not check FCS, therefore FCS will never increment on DPI ports 32-35
+ * sRIO does not check FCS, therefore FCS will never increment on sRIO ports 40-47
  */
-union cvmx_pip_stat7_prtx
-{
+union cvmx_pip_stat7_prtx {
 	uint64_t u64;
-	struct cvmx_pip_stat7_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_stat7_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t fcs                          : 32; /**< Number of packets with FCS or Align opcode errors */
 	uint64_t h1519                        : 32; /**< Number of 1519-max packets */
 #else
@@ -3257,27 +5169,50 @@ union cvmx_pip_stat7_prtx
 	struct cvmx_pip_stat7_prtx_s          cn56xxp1;
 	struct cvmx_pip_stat7_prtx_s          cn58xx;
 	struct cvmx_pip_stat7_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat7_prtx_s          cn61xx;
 	struct cvmx_pip_stat7_prtx_s          cn63xx;
 	struct cvmx_pip_stat7_prtx_s          cn63xxp1;
+	struct cvmx_pip_stat7_prtx_s          cn66xx;
+	struct cvmx_pip_stat7_prtx_s          cnf71xx;
 };
 typedef union cvmx_pip_stat7_prtx cvmx_pip_stat7_prtx_t;
 
 /**
+ * cvmx_pip_stat8_#
+ *
+ * PIP_STAT8_X = PIP_STAT_FRAG     / PIP_STAT_UNDER
+ *
+ */
+union cvmx_pip_stat8_x {
+	uint64_t u64;
+	struct cvmx_pip_stat8_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t frag                         : 32; /**< Number of packets with length < min and FCS error */
+	uint64_t undersz                      : 32; /**< Number of packets with length < min */
+#else
+	uint64_t undersz                      : 32;
+	uint64_t frag                         : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat8_x_s             cn68xx;
+	struct cvmx_pip_stat8_x_s             cn68xxp1;
+};
+typedef union cvmx_pip_stat8_x cvmx_pip_stat8_x_t;
+
+/**
  * cvmx_pip_stat8_prt#
  *
  * PIP_STAT8_PRTX = PIP_STAT_FRAG     / PIP_STAT_UNDER
  *
  *
  * Notes:
- * Note: FCS is not checked on the PCI ports 32..35.
- *
+ * DPI does not check FCS, therefore FRAG will never increment on DPI ports 32-35
+ * sRIO does not check FCS, therefore FRAG will never increment on sRIO ports 40-47
  */
-union cvmx_pip_stat8_prtx
-{
+union cvmx_pip_stat8_prtx {
 	uint64_t u64;
-	struct cvmx_pip_stat8_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_stat8_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t frag                         : 32; /**< Number of packets with length < min and FCS error */
 	uint64_t undersz                      : 32; /**< Number of packets with length < min */
 #else
@@ -3296,27 +5231,51 @@ union cvmx_pip_stat8_prtx
 	struct cvmx_pip_stat8_prtx_s          cn56xxp1;
 	struct cvmx_pip_stat8_prtx_s          cn58xx;
 	struct cvmx_pip_stat8_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat8_prtx_s          cn61xx;
 	struct cvmx_pip_stat8_prtx_s          cn63xx;
 	struct cvmx_pip_stat8_prtx_s          cn63xxp1;
+	struct cvmx_pip_stat8_prtx_s          cn66xx;
+	struct cvmx_pip_stat8_prtx_s          cnf71xx;
 };
 typedef union cvmx_pip_stat8_prtx cvmx_pip_stat8_prtx_t;
 
 /**
+ * cvmx_pip_stat9_#
+ *
+ * PIP_STAT9_X = PIP_STAT_JABBER   / PIP_STAT_OVER
+ *
+ */
+union cvmx_pip_stat9_x {
+	uint64_t u64;
+	struct cvmx_pip_stat9_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t jabber                       : 32; /**< Number of packets with length > max and FCS error */
+	uint64_t oversz                       : 32; /**< Number of packets with length > max */
+#else
+	uint64_t oversz                       : 32;
+	uint64_t jabber                       : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat9_x_s             cn68xx;
+	struct cvmx_pip_stat9_x_s             cn68xxp1;
+};
+typedef union cvmx_pip_stat9_x cvmx_pip_stat9_x_t;
+
+/**
  * cvmx_pip_stat9_prt#
  *
  * PIP_STAT9_PRTX = PIP_STAT_JABBER   / PIP_STAT_OVER
  *
  *
  * Notes:
- * Note: FCS is not checked on the PCI ports 32..35.
- *
+ * DPI does not check FCS, therefore JABBER will never increment on DPI ports 32-35
+ * sRIO does not check FCS, therefore JABBER will never increment on sRIO ports 40-47 due to FCS errors
+ * sRIO does use the JABBER opcode to communicate sRIO error, therefore JABBER can increment under the sRIO error conditions
  */
-union cvmx_pip_stat9_prtx
-{
+union cvmx_pip_stat9_prtx {
 	uint64_t u64;
-	struct cvmx_pip_stat9_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_stat9_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t jabber                       : 32; /**< Number of packets with length > max and FCS error */
 	uint64_t oversz                       : 32; /**< Number of packets with length > max */
 #else
@@ -3335,8 +5294,11 @@ union cvmx_pip_stat9_prtx
 	struct cvmx_pip_stat9_prtx_s          cn56xxp1;
 	struct cvmx_pip_stat9_prtx_s          cn58xx;
 	struct cvmx_pip_stat9_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat9_prtx_s          cn61xx;
 	struct cvmx_pip_stat9_prtx_s          cn63xx;
 	struct cvmx_pip_stat9_prtx_s          cn63xxp1;
+	struct cvmx_pip_stat9_prtx_s          cn66xx;
+	struct cvmx_pip_stat9_prtx_s          cnf71xx;
 };
 typedef union cvmx_pip_stat9_prtx cvmx_pip_stat9_prtx_t;
 
@@ -3347,12 +5309,29 @@ typedef union cvmx_pip_stat9_prtx cvmx_pip_stat9_prtx_t;
  *
  * Controls how the PIP statistics counters are handled.
  */
-union cvmx_pip_stat_ctl
-{
+union cvmx_pip_stat_ctl {
 	uint64_t u64;
-	struct cvmx_pip_stat_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_stat_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_9_63                : 55;
+	uint64_t mode                         : 1;  /**< The PIP_STAT*_X registers can be indexed either by
+                                                         port-kind or backpressure ID.
+                                                         Does not apply to the PIP_STAT_INB* registers.
+                                                         0 = X represents the packet's port-kind
+                                                         1 = X represents the packet's backpressure ID */
+	uint64_t reserved_1_7                 : 7;
+	uint64_t rdclr                        : 1;  /**< Stat registers are read and clear
+                                                         0 = stat registers hold value when read
+                                                         1 = stat registers are cleared when read */
+#else
+	uint64_t rdclr                        : 1;
+	uint64_t reserved_1_7                 : 7;
+	uint64_t mode                         : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_pip_stat_ctl_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t rdclr                        : 1;  /**< Stat registers are read and clear
                                                          0 = stat registers hold value when read
@@ -3361,20 +5340,24 @@ union cvmx_pip_stat_ctl
 	uint64_t rdclr                        : 1;
 	uint64_t reserved_1_63                : 63;
 #endif
-	} s;
-	struct cvmx_pip_stat_ctl_s            cn30xx;
-	struct cvmx_pip_stat_ctl_s            cn31xx;
-	struct cvmx_pip_stat_ctl_s            cn38xx;
-	struct cvmx_pip_stat_ctl_s            cn38xxp2;
-	struct cvmx_pip_stat_ctl_s            cn50xx;
-	struct cvmx_pip_stat_ctl_s            cn52xx;
-	struct cvmx_pip_stat_ctl_s            cn52xxp1;
-	struct cvmx_pip_stat_ctl_s            cn56xx;
-	struct cvmx_pip_stat_ctl_s            cn56xxp1;
-	struct cvmx_pip_stat_ctl_s            cn58xx;
-	struct cvmx_pip_stat_ctl_s            cn58xxp1;
-	struct cvmx_pip_stat_ctl_s            cn63xx;
-	struct cvmx_pip_stat_ctl_s            cn63xxp1;
+	} cn30xx;
+	struct cvmx_pip_stat_ctl_cn30xx       cn31xx;
+	struct cvmx_pip_stat_ctl_cn30xx       cn38xx;
+	struct cvmx_pip_stat_ctl_cn30xx       cn38xxp2;
+	struct cvmx_pip_stat_ctl_cn30xx       cn50xx;
+	struct cvmx_pip_stat_ctl_cn30xx       cn52xx;
+	struct cvmx_pip_stat_ctl_cn30xx       cn52xxp1;
+	struct cvmx_pip_stat_ctl_cn30xx       cn56xx;
+	struct cvmx_pip_stat_ctl_cn30xx       cn56xxp1;
+	struct cvmx_pip_stat_ctl_cn30xx       cn58xx;
+	struct cvmx_pip_stat_ctl_cn30xx       cn58xxp1;
+	struct cvmx_pip_stat_ctl_cn30xx       cn61xx;
+	struct cvmx_pip_stat_ctl_cn30xx       cn63xx;
+	struct cvmx_pip_stat_ctl_cn30xx       cn63xxp1;
+	struct cvmx_pip_stat_ctl_cn30xx       cn66xx;
+	struct cvmx_pip_stat_ctl_s            cn68xx;
+	struct cvmx_pip_stat_ctl_s            cn68xxp1;
+	struct cvmx_pip_stat_ctl_cn30xx       cnf71xx;
 };
 typedef union cvmx_pip_stat_ctl cvmx_pip_stat_ctl_t;
 
@@ -3389,12 +5372,10 @@ typedef union cvmx_pip_stat_ctl cvmx_pip_stat_ctl_t;
  * These counts are intended for system debug, but could convey useful
  * information in production systems.
  */
-union cvmx_pip_stat_inb_errsx
-{
+union cvmx_pip_stat_inb_errsx {
 	uint64_t u64;
-	struct cvmx_pip_stat_inb_errsx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_stat_inb_errsx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t errs                         : 16; /**< Number of packets with errors
                                                          received by PIP */
@@ -3414,12 +5395,43 @@ union cvmx_pip_stat_inb_errsx
 	struct cvmx_pip_stat_inb_errsx_s      cn56xxp1;
 	struct cvmx_pip_stat_inb_errsx_s      cn58xx;
 	struct cvmx_pip_stat_inb_errsx_s      cn58xxp1;
+	struct cvmx_pip_stat_inb_errsx_s      cn61xx;
 	struct cvmx_pip_stat_inb_errsx_s      cn63xx;
 	struct cvmx_pip_stat_inb_errsx_s      cn63xxp1;
+	struct cvmx_pip_stat_inb_errsx_s      cn66xx;
+	struct cvmx_pip_stat_inb_errsx_s      cnf71xx;
 };
 typedef union cvmx_pip_stat_inb_errsx cvmx_pip_stat_inb_errsx_t;
 
 /**
+ * cvmx_pip_stat_inb_errs_pknd#
+ *
+ * PIP_STAT_INB_ERRS_PKNDX = Inbound error packets received by PIP per pkind
+ *
+ * Inbound stats collect all data sent to PIP from all packet interfaces.
+ * Its the raw counts of everything that comes into the block.  The counts
+ * will reflect all error packets and packets dropped by the PKI RED engine.
+ * These counts are intended for system debug, but could convey useful
+ * information in production systems.
+ */
+union cvmx_pip_stat_inb_errs_pkndx {
+	uint64_t u64;
+	struct cvmx_pip_stat_inb_errs_pkndx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t errs                         : 16; /**< Number of packets with errors
+                                                         received by PIP */
+#else
+	uint64_t errs                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pip_stat_inb_errs_pkndx_s cn68xx;
+	struct cvmx_pip_stat_inb_errs_pkndx_s cn68xxp1;
+};
+typedef union cvmx_pip_stat_inb_errs_pkndx cvmx_pip_stat_inb_errs_pkndx_t;
+
+/**
  * cvmx_pip_stat_inb_octs#
  *
  * PIP_STAT_INB_OCTSX = Inbound octets received by PIP per port
@@ -3431,12 +5443,10 @@ typedef union cvmx_pip_stat_inb_errsx cvmx_pip_stat_inb_errsx_t;
  * information in production systems. The OCTS will include the bytes from
  * timestamp fields in PTP_MODE.
  */
-union cvmx_pip_stat_inb_octsx
-{
+union cvmx_pip_stat_inb_octsx {
 	uint64_t u64;
-	struct cvmx_pip_stat_inb_octsx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_stat_inb_octsx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t octs                         : 48; /**< Total number of octets from all packets received
                                                          by PIP */
@@ -3456,12 +5466,44 @@ union cvmx_pip_stat_inb_octsx
 	struct cvmx_pip_stat_inb_octsx_s      cn56xxp1;
 	struct cvmx_pip_stat_inb_octsx_s      cn58xx;
 	struct cvmx_pip_stat_inb_octsx_s      cn58xxp1;
+	struct cvmx_pip_stat_inb_octsx_s      cn61xx;
 	struct cvmx_pip_stat_inb_octsx_s      cn63xx;
 	struct cvmx_pip_stat_inb_octsx_s      cn63xxp1;
+	struct cvmx_pip_stat_inb_octsx_s      cn66xx;
+	struct cvmx_pip_stat_inb_octsx_s      cnf71xx;
 };
 typedef union cvmx_pip_stat_inb_octsx cvmx_pip_stat_inb_octsx_t;
 
 /**
+ * cvmx_pip_stat_inb_octs_pknd#
+ *
+ * PIP_STAT_INB_OCTS_PKNDX = Inbound octets received by PIP per pkind
+ *
+ * Inbound stats collect all data sent to PIP from all packet interfaces.
+ * Its the raw counts of everything that comes into the block.  The counts
+ * will reflect all error packets and packets dropped by the PKI RED engine.
+ * These counts are intended for system debug, but could convey useful
+ * information in production systems. The OCTS will include the bytes from
+ * timestamp fields in PTP_MODE.
+ */
+union cvmx_pip_stat_inb_octs_pkndx {
+	uint64_t u64;
+	struct cvmx_pip_stat_inb_octs_pkndx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_48_63               : 16;
+	uint64_t octs                         : 48; /**< Total number of octets from all packets received
+                                                         by PIP */
+#else
+	uint64_t octs                         : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_pip_stat_inb_octs_pkndx_s cn68xx;
+	struct cvmx_pip_stat_inb_octs_pkndx_s cn68xxp1;
+};
+typedef union cvmx_pip_stat_inb_octs_pkndx cvmx_pip_stat_inb_octs_pkndx_t;
+
+/**
  * cvmx_pip_stat_inb_pkts#
  *
  * PIP_STAT_INB_PKTSX = Inbound packets received by PIP per port
@@ -3472,12 +5514,10 @@ typedef union cvmx_pip_stat_inb_octsx cvmx_pip_stat_inb_octsx_t;
  * These counts are intended for system debug, but could convey useful
  * information in production systems.
  */
-union cvmx_pip_stat_inb_pktsx
-{
+union cvmx_pip_stat_inb_pktsx {
 	uint64_t u64;
-	struct cvmx_pip_stat_inb_pktsx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_stat_inb_pktsx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t pkts                         : 32; /**< Number of packets without errors
                                                          received by PIP */
@@ -3497,24 +5537,72 @@ union cvmx_pip_stat_inb_pktsx
 	struct cvmx_pip_stat_inb_pktsx_s      cn56xxp1;
 	struct cvmx_pip_stat_inb_pktsx_s      cn58xx;
 	struct cvmx_pip_stat_inb_pktsx_s      cn58xxp1;
+	struct cvmx_pip_stat_inb_pktsx_s      cn61xx;
 	struct cvmx_pip_stat_inb_pktsx_s      cn63xx;
 	struct cvmx_pip_stat_inb_pktsx_s      cn63xxp1;
+	struct cvmx_pip_stat_inb_pktsx_s      cn66xx;
+	struct cvmx_pip_stat_inb_pktsx_s      cnf71xx;
 };
 typedef union cvmx_pip_stat_inb_pktsx cvmx_pip_stat_inb_pktsx_t;
 
 /**
+ * cvmx_pip_stat_inb_pkts_pknd#
+ *
+ * PIP_STAT_INB_PKTS_PKNDX = Inbound packets received by PIP per pkind
+ *
+ * Inbound stats collect all data sent to PIP from all packet interfaces.
+ * Its the raw counts of everything that comes into the block.  The counts
+ * will reflect all error packets and packets dropped by the PKI RED engine.
+ * These counts are intended for system debug, but could convey useful
+ * information in production systems.
+ */
+union cvmx_pip_stat_inb_pkts_pkndx {
+	uint64_t u64;
+	struct cvmx_pip_stat_inb_pkts_pkndx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t pkts                         : 32; /**< Number of packets without errors
+                                                         received by PIP */
+#else
+	uint64_t pkts                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat_inb_pkts_pkndx_s cn68xx;
+	struct cvmx_pip_stat_inb_pkts_pkndx_s cn68xxp1;
+};
+typedef union cvmx_pip_stat_inb_pkts_pkndx cvmx_pip_stat_inb_pkts_pkndx_t;
+
+/**
+ * cvmx_pip_sub_pkind_fcs#
+ */
+union cvmx_pip_sub_pkind_fcsx {
+	uint64_t u64;
+	struct cvmx_pip_sub_pkind_fcsx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t port_bit                     : 64; /**< When set '1', the pkind corresponding to the bit
+                                                         position set, will subtract the FCS for packets
+                                                         on that pkind. */
+#else
+	uint64_t port_bit                     : 64;
+#endif
+	} s;
+	struct cvmx_pip_sub_pkind_fcsx_s      cn68xx;
+	struct cvmx_pip_sub_pkind_fcsx_s      cn68xxp1;
+};
+typedef union cvmx_pip_sub_pkind_fcsx cvmx_pip_sub_pkind_fcsx_t;
+
+/**
  * cvmx_pip_tag_inc#
  *
  * PIP_TAG_INC = Which bytes to include in the new tag hash algorithm
  *
  * # $PIP_TAG_INCX = 0x300+X X=(0..63) RegType=(RSL) RtlReg=(pip_tag_inc_csr_direct_TestbuilderTask)
  */
-union cvmx_pip_tag_incx
-{
+union cvmx_pip_tag_incx {
 	uint64_t u64;
-	struct cvmx_pip_tag_incx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_tag_incx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t en                           : 8;  /**< Which bytes to include in mask tag algorithm
                                                          Broken into 4, 16-entry masks to cover 128B
@@ -3544,8 +5632,13 @@ union cvmx_pip_tag_incx
 	struct cvmx_pip_tag_incx_s            cn56xxp1;
 	struct cvmx_pip_tag_incx_s            cn58xx;
 	struct cvmx_pip_tag_incx_s            cn58xxp1;
+	struct cvmx_pip_tag_incx_s            cn61xx;
 	struct cvmx_pip_tag_incx_s            cn63xx;
 	struct cvmx_pip_tag_incx_s            cn63xxp1;
+	struct cvmx_pip_tag_incx_s            cn66xx;
+	struct cvmx_pip_tag_incx_s            cn68xx;
+	struct cvmx_pip_tag_incx_s            cn68xxp1;
+	struct cvmx_pip_tag_incx_s            cnf71xx;
 };
 typedef union cvmx_pip_tag_incx cvmx_pip_tag_incx_t;
 
@@ -3555,12 +5648,10 @@ typedef union cvmx_pip_tag_incx cvmx_pip_tag_incx_t;
  * PIP_TAG_MASK = Mask bit in the tag generation
  *
  */
-union cvmx_pip_tag_mask
-{
+union cvmx_pip_tag_mask {
 	uint64_t u64;
-	struct cvmx_pip_tag_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_tag_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t mask                         : 16; /**< When set, MASK clears individual bits of lower 16
                                                          bits of the computed tag.  Does not effect RAW
@@ -3581,8 +5672,13 @@ union cvmx_pip_tag_mask
 	struct cvmx_pip_tag_mask_s            cn56xxp1;
 	struct cvmx_pip_tag_mask_s            cn58xx;
 	struct cvmx_pip_tag_mask_s            cn58xxp1;
+	struct cvmx_pip_tag_mask_s            cn61xx;
 	struct cvmx_pip_tag_mask_s            cn63xx;
 	struct cvmx_pip_tag_mask_s            cn63xxp1;
+	struct cvmx_pip_tag_mask_s            cn66xx;
+	struct cvmx_pip_tag_mask_s            cn68xx;
+	struct cvmx_pip_tag_mask_s            cn68xxp1;
+	struct cvmx_pip_tag_mask_s            cnf71xx;
 };
 typedef union cvmx_pip_tag_mask cvmx_pip_tag_mask_t;
 
@@ -3593,12 +5689,10 @@ typedef union cvmx_pip_tag_mask cvmx_pip_tag_mask_t;
  *
  * The source and destination IV's provide a mechanism for each Octeon to be unique.
  */
-union cvmx_pip_tag_secret
-{
+union cvmx_pip_tag_secret {
 	uint64_t u64;
-	struct cvmx_pip_tag_secret_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_tag_secret_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t dst                          : 16; /**< Secret for the destination tuple tag CRC calc */
 	uint64_t src                          : 16; /**< Secret for the source tuple tag CRC calc */
@@ -3619,8 +5713,13 @@ union cvmx_pip_tag_secret
 	struct cvmx_pip_tag_secret_s          cn56xxp1;
 	struct cvmx_pip_tag_secret_s          cn58xx;
 	struct cvmx_pip_tag_secret_s          cn58xxp1;
+	struct cvmx_pip_tag_secret_s          cn61xx;
 	struct cvmx_pip_tag_secret_s          cn63xx;
 	struct cvmx_pip_tag_secret_s          cn63xxp1;
+	struct cvmx_pip_tag_secret_s          cn66xx;
+	struct cvmx_pip_tag_secret_s          cn68xx;
+	struct cvmx_pip_tag_secret_s          cn68xxp1;
+	struct cvmx_pip_tag_secret_s          cnf71xx;
 };
 typedef union cvmx_pip_tag_secret cvmx_pip_tag_secret_t;
 
@@ -3631,12 +5730,10 @@ typedef union cvmx_pip_tag_secret cvmx_pip_tag_secret_t;
  *
  * Summary of the current packet that has completed and waiting to be processed
  */
-union cvmx_pip_todo_entry
-{
+union cvmx_pip_todo_entry {
 	uint64_t u64;
-	struct cvmx_pip_todo_entry_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_todo_entry_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t val                          : 1;  /**< Entry is valid */
 	uint64_t reserved_62_62               : 1;
 	uint64_t entry                        : 62; /**< Todo list entry summary */
@@ -3657,23 +5754,56 @@ union cvmx_pip_todo_entry
 	struct cvmx_pip_todo_entry_s          cn56xxp1;
 	struct cvmx_pip_todo_entry_s          cn58xx;
 	struct cvmx_pip_todo_entry_s          cn58xxp1;
+	struct cvmx_pip_todo_entry_s          cn61xx;
 	struct cvmx_pip_todo_entry_s          cn63xx;
 	struct cvmx_pip_todo_entry_s          cn63xxp1;
+	struct cvmx_pip_todo_entry_s          cn66xx;
+	struct cvmx_pip_todo_entry_s          cn68xx;
+	struct cvmx_pip_todo_entry_s          cn68xxp1;
+	struct cvmx_pip_todo_entry_s          cnf71xx;
 };
 typedef union cvmx_pip_todo_entry cvmx_pip_todo_entry_t;
 
 /**
+ * cvmx_pip_vlan_etypes#
+ */
+union cvmx_pip_vlan_etypesx {
+	uint64_t u64;
+	struct cvmx_pip_vlan_etypesx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t type3                        : 16; /**< VLAN Ethertype */
+	uint64_t type2                        : 16; /**< VLAN Ethertype */
+	uint64_t type1                        : 16; /**< VLAN Ethertype */
+	uint64_t type0                        : 16; /**< VLAN Ethertype
+                                                         Specifies ethertypes that will be parsed as
+                                                         containing VLAN information. Each TYPE is
+                                                         orthagonal; if all eight are not required, set
+                                                         multiple TYPEs to the same value (as in the
+                                                         0x8100 default value). */
+#else
+	uint64_t type0                        : 16;
+	uint64_t type1                        : 16;
+	uint64_t type2                        : 16;
+	uint64_t type3                        : 16;
+#endif
+	} s;
+	struct cvmx_pip_vlan_etypesx_s        cn61xx;
+	struct cvmx_pip_vlan_etypesx_s        cn66xx;
+	struct cvmx_pip_vlan_etypesx_s        cn68xx;
+	struct cvmx_pip_vlan_etypesx_s        cnf71xx;
+};
+typedef union cvmx_pip_vlan_etypesx cvmx_pip_vlan_etypesx_t;
+
+/**
  * cvmx_pip_xstat0_prt#
  *
  * PIP_XSTAT0_PRT = PIP_XSTAT_DRP_PKTS / PIP_XSTAT_DRP_OCTS
  *
  */
-union cvmx_pip_xstat0_prtx
-{
+union cvmx_pip_xstat0_prtx {
 	uint64_t u64;
-	struct cvmx_pip_xstat0_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_xstat0_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t drp_pkts                     : 32; /**< Inbound packets marked to be dropped by the IPD
                                                          QOS widget per port */
 	uint64_t drp_octs                     : 32; /**< Inbound octets marked to be dropped by the IPD
@@ -3685,21 +5815,96 @@ union cvmx_pip_xstat0_prtx
 	} s;
 	struct cvmx_pip_xstat0_prtx_s         cn63xx;
 	struct cvmx_pip_xstat0_prtx_s         cn63xxp1;
+	struct cvmx_pip_xstat0_prtx_s         cn66xx;
 };
 typedef union cvmx_pip_xstat0_prtx cvmx_pip_xstat0_prtx_t;
 
 /**
+ * cvmx_pip_xstat10_prt#
+ *
+ * PIP_XSTAT10_PRTX = PIP_XSTAT_L2_MCAST / PIP_XSTAT_L2_BCAST
+ *
+ */
+union cvmx_pip_xstat10_prtx {
+	uint64_t u64;
+	struct cvmx_pip_xstat10_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bcast                        : 32; /**< Number of packets with L2 Broadcast DMAC
+                                                         that were dropped due to RED.
+                                                         The HW will consider a packet to be an L2
+                                                         broadcast packet when the 48-bit DMAC is all 1's.
+                                                         Only applies when the parse mode for the packet
+                                                         is SKIP-TO-L2. */
+	uint64_t mcast                        : 32; /**< Number of packets with L2 Mulitcast DMAC
+                                                         that were dropped due to RED.
+                                                         The HW will consider a packet to be an L2
+                                                         multicast packet when the least-significant bit
+                                                         of the first byte of the DMAC is set and the
+                                                         packet is not an L2 broadcast packet.
+                                                         Only applies when the parse mode for the packet
+                                                         is SKIP-TO-L2. */
+#else
+	uint64_t mcast                        : 32;
+	uint64_t bcast                        : 32;
+#endif
+	} s;
+	struct cvmx_pip_xstat10_prtx_s        cn63xx;
+	struct cvmx_pip_xstat10_prtx_s        cn63xxp1;
+	struct cvmx_pip_xstat10_prtx_s        cn66xx;
+};
+typedef union cvmx_pip_xstat10_prtx cvmx_pip_xstat10_prtx_t;
+
+/**
+ * cvmx_pip_xstat11_prt#
+ *
+ * PIP_XSTAT11_PRTX = PIP_XSTAT_L3_MCAST / PIP_XSTAT_L3_BCAST
+ *
+ */
+union cvmx_pip_xstat11_prtx {
+	uint64_t u64;
+	struct cvmx_pip_xstat11_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t bcast                        : 32; /**< Number of packets with L3 Broadcast Dest Address
+                                                         that were dropped due to RED.
+                                                         The HW considers an IPv4 packet to be broadcast
+                                                         when all bits are set in the MSB of the
+                                                         destination address. IPv6 does not have the
+                                                         concept of a broadcast packets.
+                                                         Only applies when the parse mode for the packet
+                                                         is SKIP-TO-L2 and the packet is IP or the parse
+                                                         mode for the packet is SKIP-TO-IP. */
+	uint64_t mcast                        : 32; /**< Number of packets with L3 Multicast Dest Address
+                                                         that were dropped due to RED.
+                                                         The HW considers an IPv4 packet to be multicast
+                                                         when the most-significant nibble of the 32-bit
+                                                         destination address is 0xE (i.e. it is a class D
+                                                         address). The HW considers an IPv6 packet to be
+                                                         multicast when the most-significant byte of the
+                                                         128-bit destination address is all 1's.
+                                                         Only applies when the parse mode for the packet
+                                                         is SKIP-TO-L2 and the packet is IP or the parse
+                                                         mode for the packet is SKIP-TO-IP. */
+#else
+	uint64_t mcast                        : 32;
+	uint64_t bcast                        : 32;
+#endif
+	} s;
+	struct cvmx_pip_xstat11_prtx_s        cn63xx;
+	struct cvmx_pip_xstat11_prtx_s        cn63xxp1;
+	struct cvmx_pip_xstat11_prtx_s        cn66xx;
+};
+typedef union cvmx_pip_xstat11_prtx cvmx_pip_xstat11_prtx_t;
+
+/**
  * cvmx_pip_xstat1_prt#
  *
  * PIP_XSTAT1_PRTX = PIP_XSTAT_OCTS
  *
  */
-union cvmx_pip_xstat1_prtx
-{
+union cvmx_pip_xstat1_prtx {
 	uint64_t u64;
-	struct cvmx_pip_xstat1_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_xstat1_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t octs                         : 48; /**< Number of octets received by PIP (good and bad) */
 #else
@@ -3709,6 +5914,7 @@ union cvmx_pip_xstat1_prtx
 	} s;
 	struct cvmx_pip_xstat1_prtx_s         cn63xx;
 	struct cvmx_pip_xstat1_prtx_s         cn63xxp1;
+	struct cvmx_pip_xstat1_prtx_s         cn66xx;
 };
 typedef union cvmx_pip_xstat1_prtx cvmx_pip_xstat1_prtx_t;
 
@@ -3718,12 +5924,10 @@ typedef union cvmx_pip_xstat1_prtx cvmx_pip_xstat1_prtx_t;
  * PIP_XSTAT2_PRTX = PIP_XSTAT_PKTS     / PIP_XSTAT_RAW
  *
  */
-union cvmx_pip_xstat2_prtx
-{
+union cvmx_pip_xstat2_prtx {
 	uint64_t u64;
-	struct cvmx_pip_xstat2_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_xstat2_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t pkts                         : 32; /**< Number of packets processed by PIP */
 	uint64_t raw                          : 32; /**< RAWFULL + RAWSCH Packets without an L1/L2 error
                                                          received by PIP per port */
@@ -3734,6 +5938,7 @@ union cvmx_pip_xstat2_prtx
 	} s;
 	struct cvmx_pip_xstat2_prtx_s         cn63xx;
 	struct cvmx_pip_xstat2_prtx_s         cn63xxp1;
+	struct cvmx_pip_xstat2_prtx_s         cn66xx;
 };
 typedef union cvmx_pip_xstat2_prtx cvmx_pip_xstat2_prtx_t;
 
@@ -3743,12 +5948,10 @@ typedef union cvmx_pip_xstat2_prtx cvmx_pip_xstat2_prtx_t;
  * PIP_XSTAT3_PRTX = PIP_XSTAT_BCST     / PIP_XSTAT_MCST
  *
  */
-union cvmx_pip_xstat3_prtx
-{
+union cvmx_pip_xstat3_prtx {
 	uint64_t u64;
-	struct cvmx_pip_xstat3_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_xstat3_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bcst                         : 32; /**< Number of indentified L2 broadcast packets
                                                          Does not include multicast packets
                                                          Only includes packets whose parse mode is
@@ -3764,6 +5967,7 @@ union cvmx_pip_xstat3_prtx
 	} s;
 	struct cvmx_pip_xstat3_prtx_s         cn63xx;
 	struct cvmx_pip_xstat3_prtx_s         cn63xxp1;
+	struct cvmx_pip_xstat3_prtx_s         cn66xx;
 };
 typedef union cvmx_pip_xstat3_prtx cvmx_pip_xstat3_prtx_t;
 
@@ -3773,12 +5977,10 @@ typedef union cvmx_pip_xstat3_prtx cvmx_pip_xstat3_prtx_t;
  * PIP_XSTAT4_PRTX = PIP_XSTAT_HIST1    / PIP_XSTAT_HIST0
  *
  */
-union cvmx_pip_xstat4_prtx
-{
+union cvmx_pip_xstat4_prtx {
 	uint64_t u64;
-	struct cvmx_pip_xstat4_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_xstat4_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t h65to127                     : 32; /**< Number of 65-127B packets */
 	uint64_t h64                          : 32; /**< Number of 1-64B packets */
 #else
@@ -3788,6 +5990,7 @@ union cvmx_pip_xstat4_prtx
 	} s;
 	struct cvmx_pip_xstat4_prtx_s         cn63xx;
 	struct cvmx_pip_xstat4_prtx_s         cn63xxp1;
+	struct cvmx_pip_xstat4_prtx_s         cn66xx;
 };
 typedef union cvmx_pip_xstat4_prtx cvmx_pip_xstat4_prtx_t;
 
@@ -3797,12 +6000,10 @@ typedef union cvmx_pip_xstat4_prtx cvmx_pip_xstat4_prtx_t;
  * PIP_XSTAT5_PRTX = PIP_XSTAT_HIST3    / PIP_XSTAT_HIST2
  *
  */
-union cvmx_pip_xstat5_prtx
-{
+union cvmx_pip_xstat5_prtx {
 	uint64_t u64;
-	struct cvmx_pip_xstat5_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_xstat5_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t h256to511                    : 32; /**< Number of 256-511B packets */
 	uint64_t h128to255                    : 32; /**< Number of 128-255B packets */
 #else
@@ -3812,6 +6013,7 @@ union cvmx_pip_xstat5_prtx
 	} s;
 	struct cvmx_pip_xstat5_prtx_s         cn63xx;
 	struct cvmx_pip_xstat5_prtx_s         cn63xxp1;
+	struct cvmx_pip_xstat5_prtx_s         cn66xx;
 };
 typedef union cvmx_pip_xstat5_prtx cvmx_pip_xstat5_prtx_t;
 
@@ -3821,12 +6023,10 @@ typedef union cvmx_pip_xstat5_prtx cvmx_pip_xstat5_prtx_t;
  * PIP_XSTAT6_PRTX = PIP_XSTAT_HIST5    / PIP_XSTAT_HIST4
  *
  */
-union cvmx_pip_xstat6_prtx
-{
+union cvmx_pip_xstat6_prtx {
 	uint64_t u64;
-	struct cvmx_pip_xstat6_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_xstat6_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t h1024to1518                  : 32; /**< Number of 1024-1518B packets */
 	uint64_t h512to1023                   : 32; /**< Number of 512-1023B packets */
 #else
@@ -3836,6 +6036,7 @@ union cvmx_pip_xstat6_prtx
 	} s;
 	struct cvmx_pip_xstat6_prtx_s         cn63xx;
 	struct cvmx_pip_xstat6_prtx_s         cn63xxp1;
+	struct cvmx_pip_xstat6_prtx_s         cn66xx;
 };
 typedef union cvmx_pip_xstat6_prtx cvmx_pip_xstat6_prtx_t;
 
@@ -3846,15 +6047,13 @@ typedef union cvmx_pip_xstat6_prtx cvmx_pip_xstat6_prtx_t;
  *
  *
  * Notes:
- * Note: FCS is not checked on the PCI ports 32..35.
- *
+ * DPI does not check FCS, therefore FCS will never increment on DPI ports 32-35
+ * sRIO does not check FCS, therefore FCS will never increment on sRIO ports 40-47
  */
-union cvmx_pip_xstat7_prtx
-{
+union cvmx_pip_xstat7_prtx {
 	uint64_t u64;
-	struct cvmx_pip_xstat7_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_xstat7_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t fcs                          : 32; /**< Number of packets with FCS or Align opcode errors */
 	uint64_t h1519                        : 32; /**< Number of 1519-max packets */
 #else
@@ -3864,6 +6063,7 @@ union cvmx_pip_xstat7_prtx
 	} s;
 	struct cvmx_pip_xstat7_prtx_s         cn63xx;
 	struct cvmx_pip_xstat7_prtx_s         cn63xxp1;
+	struct cvmx_pip_xstat7_prtx_s         cn66xx;
 };
 typedef union cvmx_pip_xstat7_prtx cvmx_pip_xstat7_prtx_t;
 
@@ -3874,15 +6074,13 @@ typedef union cvmx_pip_xstat7_prtx cvmx_pip_xstat7_prtx_t;
  *
  *
  * Notes:
- * Note: FCS is not checked on the PCI ports 32..35.
- *
+ * DPI does not check FCS, therefore FRAG will never increment on DPI ports 32-35
+ * sRIO does not check FCS, therefore FRAG will never increment on sRIO ports 40-47
  */
-union cvmx_pip_xstat8_prtx
-{
+union cvmx_pip_xstat8_prtx {
 	uint64_t u64;
-	struct cvmx_pip_xstat8_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_xstat8_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t frag                         : 32; /**< Number of packets with length < min and FCS error */
 	uint64_t undersz                      : 32; /**< Number of packets with length < min */
 #else
@@ -3892,6 +6090,7 @@ union cvmx_pip_xstat8_prtx
 	} s;
 	struct cvmx_pip_xstat8_prtx_s         cn63xx;
 	struct cvmx_pip_xstat8_prtx_s         cn63xxp1;
+	struct cvmx_pip_xstat8_prtx_s         cn66xx;
 };
 typedef union cvmx_pip_xstat8_prtx cvmx_pip_xstat8_prtx_t;
 
@@ -3902,15 +6101,14 @@ typedef union cvmx_pip_xstat8_prtx cvmx_pip_xstat8_prtx_t;
  *
  *
  * Notes:
- * Note: FCS is not checked on the PCI ports 32..35.
- *
+ * DPI does not check FCS, therefore JABBER will never increment on DPI ports 32-35
+ * sRIO does not check FCS, therefore JABBER will never increment on sRIO ports 40-47 due to FCS errors
+ * sRIO does use the JABBER opcode to communicate sRIO error, therefore JABBER can increment under the sRIO error conditions
  */
-union cvmx_pip_xstat9_prtx
-{
+union cvmx_pip_xstat9_prtx {
 	uint64_t u64;
-	struct cvmx_pip_xstat9_prtx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pip_xstat9_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t jabber                       : 32; /**< Number of packets with length > max and FCS error */
 	uint64_t oversz                       : 32; /**< Number of packets with length > max */
 #else
@@ -3920,6 +6118,7 @@ union cvmx_pip_xstat9_prtx
 	} s;
 	struct cvmx_pip_xstat9_prtx_s         cn63xx;
 	struct cvmx_pip_xstat9_prtx_s         cn63xxp1;
+	struct cvmx_pip_xstat9_prtx_s         cn66xx;
 };
 typedef union cvmx_pip_xstat9_prtx cvmx_pip_xstat9_prtx_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-pip.h b/sys/contrib/octeon-sdk/cvmx-pip.h
index c6745c3..769eb21 100644
--- a/sys/contrib/octeon-sdk/cvmx-pip.h
+++ b/sys/contrib/octeon-sdk/cvmx-pip.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -43,7 +43,7 @@
  *
  * Interface to the hardware Packet Input Processing unit.
  *
- * <hr>$Revision: 49504 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 
@@ -60,12 +60,15 @@
 #endif
 #endif
 
+#include "cvmx-helper.h"
+#include "cvmx-helper-util.h"
+
 
 #ifdef	__cplusplus
 extern "C" {
 #endif
 
-#define CVMX_PIP_NUM_INPUT_PORTS                44
+#define CVMX_PIP_NUM_INPUT_PORTS                46
 
 /*
  * Encodes the different error and exception codes
@@ -199,6 +202,40 @@ typedef struct
     uint32_t    inb_packets;            /**< Number of packets without GMX/SPX/PCI errors received by PIP */
     uint64_t    inb_octets;             /**< Total number of octets from all packets received by PIP, including CRC */
     uint16_t    inb_errors;             /**< Number of packets with GMX/SPX/PCI errors received by PIP */
+    uint32_t    mcast_l2_red_packets;   /**< Number of packets with L2 Multicast DMAC
+                                             that were dropped due to RED.
+                                             The HW will consider a packet to be an L2
+                                             multicast packet when the least-significant bit
+                                             of the first byte of the DMAC is set and the
+                                             packet is not an L2 broadcast packet.
+                                             Only applies when the parse mode for the packets
+                                             is SKIP-TO-L2 */ 
+    uint32_t    bcast_l2_red_packets;   /**< Number of packets with L2 Broadcast DMAC
+                                             that were dropped due to RED.
+                                             The HW will consider a packet to be an L2
+                                             broadcast packet when the 48-bit DMAC is all 1's.
+                                             Only applies when the parse mode for the packets
+                                             is SKIP-TO-L2 */ 
+    uint32_t    mcast_l3_red_packets;   /**< Number of packets with L3 Multicast Dest Address
+                                             that were dropped due to RED.
+                                             The HW considers an IPv4 packet to be multicast
+                                             when the most-significant nibble of the 32-bit
+                                             destination address is 0xE (i.e it is a class D
+                                             address). The HW considers an IPv6 packet to be 
+                                             multicast when the most-significant byte of the
+                                             128-bit destination address is all 1's.
+                                             Only applies when the parse mode for the packets
+                                             is SKIP-TO-L2 and the packet is IP or the parse
+                                             mode for the packet is SKIP-TO-IP */ 
+    uint32_t    bcast_l3_red_packets;   /**< Number of packets with L3 Broadcast Dest Address
+                                             that were dropped due to RED.
+                                             The HW considers an IPv4 packet to be broadcast
+                                             when all bits are set in the MSB of the
+                                             destination address. IPv6 does not have the 
+                                             concept of a broadcast packets.
+                                             Only applies when the parse mode for the packet
+                                             is SKIP-TO-L2 and the packet is IP or the parse
+                                             mode for the packet is SKIP-TO-IP */ 
 } cvmx_pip_port_status_t;
 
 
@@ -217,7 +254,9 @@ typedef union
         cvmx_pip_port_parse_mode_t  parse_mode  : 2;    /**< PIP parse mode for this packet */
         uint64_t                    reserved1   : 1;    /**< Must be zero */
         uint64_t                    skip_len    : 7;    /**< Skip amount, including this header, to the beginning of the packet */
-        uint64_t                    reserved2   : 2;    /**< Must be zero */
+        uint64_t                    grpext      : 2;    /**< These bits get concatenated with the
+                                                             PKT_INST_HDR[GRP] bits, creating a 6-bit
+                                                             GRP field. Added in pass2. */
         uint64_t                    nqos        : 1;    /**< Must be 0 when PKT_INST_HDR[R] = 0.
                                                              When set to 1, NQOS prevents PIP from directly using
                                                              PKT_INST_HDR[QOS] for the QOS value in WQE.
@@ -256,39 +295,20 @@ static inline void cvmx_pip_config_port(uint64_t port_num,
                                         cvmx_pip_prt_cfgx_t port_cfg,
                                         cvmx_pip_prt_tagx_t port_tag_cfg)
 {
-    cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64);
-    cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64);
-}
 
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+    {
+        int interface, index, pknd;
 
-/**
- * @deprecated      This function is a thin wrapper around the Pass1 version
- *                  of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for
- *                  setting the group that is incompatible with this function,
- *                  the preferred upgrade path is to use the CSR directly.
- *
- * Configure the global QoS packet watchers. Each watcher is
- * capable of matching a field in a packet to determine the
- * QoS queue for scheduling.
- *
- * @param watcher    Watcher number to configure (0 - 3).
- * @param match_type Watcher match type
- * @param match_value
- *                   Value the watcher will match against
- * @param qos        QoS queue for packets matching this watcher
- */
-static inline void cvmx_pip_config_watcher(uint64_t watcher,
-                                           cvmx_pip_qos_watch_types match_type,
-                                           uint64_t match_value, uint64_t qos)
-{
-    cvmx_pip_qos_watchx_t watcher_config;
+        interface = cvmx_helper_get_interface_num(port_num);
+        index = cvmx_helper_get_interface_index_num(port_num);
+	pknd = cvmx_helper_get_pknd(interface, index);
 
-    watcher_config.u64 = 0;
-    watcher_config.s.match_type = match_type;
-    watcher_config.s.match_value = match_value;
-    watcher_config.s.qos = qos;
+	port_num = pknd; /* overload port_num with pknd */
+    }
 
-    cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64);
+    cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64);
+    cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64);
 }
 
 
@@ -301,10 +321,17 @@ static inline void cvmx_pip_config_watcher(uint64_t watcher,
  */
 static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority, uint64_t qos)
 {
-    cvmx_pip_qos_vlanx_t pip_qos_vlanx;
-    pip_qos_vlanx.u64 = 0;
-    pip_qos_vlanx.s.qos = qos;
-    cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64);
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+    {
+        /* FIXME for 68xx. */
+    }
+    else
+    {
+        cvmx_pip_qos_vlanx_t pip_qos_vlanx;
+        pip_qos_vlanx.u64 = 0;
+        pip_qos_vlanx.s.qos = qos;
+        cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64);
+    }
 }
 
 
@@ -316,17 +343,24 @@ static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority, uint64_t qos
  */
 static inline void cvmx_pip_config_diffserv_qos(uint64_t diffserv, uint64_t qos)
 {
-    cvmx_pip_qos_diffx_t pip_qos_diffx;
-    pip_qos_diffx.u64 = 0;
-    pip_qos_diffx.s.qos = qos;
-    cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64);
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+    {
+        /* FIXME for 68xx. */
+    }
+    else
+    {
+        cvmx_pip_qos_diffx_t pip_qos_diffx;
+        pip_qos_diffx.u64 = 0;
+        pip_qos_diffx.s.qos = qos;
+        cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64);
+    }
 }
 
 
 /**
  * Get the status counters for a port.
  *
- * @param port_num Port number to get statistics for.
+ * @param port_num Port number (ipd_port) to get statistics for.
  * @param clear    Set to 1 to clear the counters after they are read
  * @param status   Where to put the results.
  */
@@ -343,43 +377,93 @@ static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear, c
     cvmx_pip_stat7_prtx_t stat7;
     cvmx_pip_stat8_prtx_t stat8;
     cvmx_pip_stat9_prtx_t stat9;
+    cvmx_pip_stat10_x_t stat10;
+    cvmx_pip_stat11_x_t stat11;
     cvmx_pip_stat_inb_pktsx_t pip_stat_inb_pktsx;
     cvmx_pip_stat_inb_octsx_t pip_stat_inb_octsx;
     cvmx_pip_stat_inb_errsx_t pip_stat_inb_errsx;
+    int interface = cvmx_helper_get_interface_num(port_num);
+    int index = cvmx_helper_get_interface_index_num(port_num);
 
     pip_stat_ctl.u64 = 0;
     pip_stat_ctl.s.rdclr = clear;
     cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64);
 
-    if (port_num >= 40)
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+    {
+        int pknd = cvmx_helper_get_pknd(interface, index);
+        /*
+         * PIP_STAT_CTL[MODE] 0 means pkind.
+         */
+        stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_X(pknd));
+        stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_X(pknd));
+        stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_X(pknd));
+        stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_X(pknd));
+        stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_X(pknd));
+        stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_X(pknd));
+        stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_X(pknd));
+        stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_X(pknd));
+        stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_X(pknd));
+        stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_X(pknd));
+        stat10.u64 = cvmx_read_csr(CVMX_PIP_STAT10_X(pknd));
+        stat11.u64 = cvmx_read_csr(CVMX_PIP_STAT11_X(pknd));
+    }
+    else 
     {
-        stat0.u64 = cvmx_read_csr(CVMX_PIP_XSTAT0_PRTX(port_num));
-        stat1.u64 = cvmx_read_csr(CVMX_PIP_XSTAT1_PRTX(port_num));
-        stat2.u64 = cvmx_read_csr(CVMX_PIP_XSTAT2_PRTX(port_num));
-        stat3.u64 = cvmx_read_csr(CVMX_PIP_XSTAT3_PRTX(port_num));
-        stat4.u64 = cvmx_read_csr(CVMX_PIP_XSTAT4_PRTX(port_num));
-        stat5.u64 = cvmx_read_csr(CVMX_PIP_XSTAT5_PRTX(port_num));
-        stat6.u64 = cvmx_read_csr(CVMX_PIP_XSTAT6_PRTX(port_num));
-        stat7.u64 = cvmx_read_csr(CVMX_PIP_XSTAT7_PRTX(port_num));
-        stat8.u64 = cvmx_read_csr(CVMX_PIP_XSTAT8_PRTX(port_num));
-        stat9.u64 = cvmx_read_csr(CVMX_PIP_XSTAT9_PRTX(port_num));
+        if (port_num >= 40)
+        {
+            stat0.u64 = cvmx_read_csr(CVMX_PIP_XSTAT0_PRTX(port_num));
+            stat1.u64 = cvmx_read_csr(CVMX_PIP_XSTAT1_PRTX(port_num));
+            stat2.u64 = cvmx_read_csr(CVMX_PIP_XSTAT2_PRTX(port_num));
+            stat3.u64 = cvmx_read_csr(CVMX_PIP_XSTAT3_PRTX(port_num));
+            stat4.u64 = cvmx_read_csr(CVMX_PIP_XSTAT4_PRTX(port_num));
+            stat5.u64 = cvmx_read_csr(CVMX_PIP_XSTAT5_PRTX(port_num));
+            stat6.u64 = cvmx_read_csr(CVMX_PIP_XSTAT6_PRTX(port_num));
+            stat7.u64 = cvmx_read_csr(CVMX_PIP_XSTAT7_PRTX(port_num));
+            stat8.u64 = cvmx_read_csr(CVMX_PIP_XSTAT8_PRTX(port_num));
+            stat9.u64 = cvmx_read_csr(CVMX_PIP_XSTAT9_PRTX(port_num));
+            if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+            {
+                stat10.u64 = cvmx_read_csr(CVMX_PIP_XSTAT10_PRTX(port_num));
+                stat11.u64 = cvmx_read_csr(CVMX_PIP_XSTAT11_PRTX(port_num));
+            }
+        }
+        else
+        {
+            stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num));
+            stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num));
+            stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num));
+            stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num));
+            stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num));
+            stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num));
+            stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num));
+            stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num));
+            stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num));
+            stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num));
+            if (OCTEON_IS_MODEL(OCTEON_CN52XX)
+                || OCTEON_IS_MODEL(OCTEON_CN56XX)
+                || OCTEON_IS_MODEL(OCTEON_CN6XXX)
+                || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
+            {
+                stat10.u64 = cvmx_read_csr(CVMX_PIP_STAT10_PRTX(port_num));
+                stat11.u64 = cvmx_read_csr(CVMX_PIP_STAT11_PRTX(port_num));
+            }
+        }
+    }
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+    {
+        int pknd = cvmx_helper_get_pknd(interface, index);
+
+        pip_stat_inb_pktsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_PKTS_PKNDX(pknd));
+        pip_stat_inb_octsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_OCTS_PKNDX(pknd));
+        pip_stat_inb_errsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_ERRS_PKNDX(pknd));
     }
     else
     {
-        stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num));
-        stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num));
-        stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num));
-        stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num));
-        stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num));
-        stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num));
-        stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num));
-        stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num));
-        stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num));
-        stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num));
+        pip_stat_inb_pktsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num));
+        pip_stat_inb_octsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num));
+        pip_stat_inb_errsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num));
     }
-    pip_stat_inb_pktsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num));
-    pip_stat_inb_octsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num));
-    pip_stat_inb_errsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num));
 
     status->dropped_octets          = stat0.s.drp_octs;
     status->dropped_packets         = stat0.s.drp_pkts;
@@ -400,10 +484,19 @@ static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear, c
     status->runt_crc_packets        = stat8.s.frag;
     status->oversize_packets        = stat9.s.oversz;
     status->oversize_crc_packets    = stat9.s.jabber;
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX)
+        || OCTEON_IS_MODEL(OCTEON_CN56XX)
+        || OCTEON_IS_MODEL(OCTEON_CN6XXX)
+        || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
+    {
+        status->mcast_l2_red_packets        = stat10.s.mcast;
+        status->bcast_l2_red_packets        = stat10.s.bcast;
+        status->mcast_l3_red_packets        = stat11.s.mcast;
+        status->bcast_l3_red_packets        = stat11.s.bcast;
+    }
     status->inb_packets             = pip_stat_inb_pktsx.s.pkts;
     status->inb_octets              = pip_stat_inb_octsx.s.octs;
     status->inb_errors              = pip_stat_inb_errsx.s.errs;
-
 }
 
 
@@ -483,6 +576,229 @@ static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset, u
     }
 }
 
+/**
+ * Initialize Bit Select Extractor config. Their are 8 bit positions and valids
+ * to be used when using the corresponding extractor.
+ * 
+ * @param bit     Bit Select Extractor to use
+ * @param pos     Which position to update
+ * @param val     The value to update the position with
+ */
+static inline void cvmx_pip_set_bsel_pos(int bit, int pos, int val)
+{
+    cvmx_pip_bsel_ext_posx_t bsel_pos;
+
+    /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
+    if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
+        return;
+
+    if (bit < 0 || bit > 3)
+    {
+        cvmx_dprintf("ERROR: cvmx_pip_set_bsel_pos: Invalid Bit-Select Extractor (%d) passed\n", bit);
+        return;
+    }
+
+    bsel_pos.u64 = cvmx_read_csr(CVMX_PIP_BSEL_EXT_POSX(bit));
+    switch(pos)
+    {
+        case 0:
+            bsel_pos.s.pos0_val = 1;
+            bsel_pos.s.pos0 = val & 0x7f;
+            break;
+        case 1:
+            bsel_pos.s.pos1_val = 1;
+            bsel_pos.s.pos1 = val & 0x7f;
+            break;
+        case 2:
+            bsel_pos.s.pos2_val = 1;
+            bsel_pos.s.pos2 = val & 0x7f;
+            break;
+        case 3:
+            bsel_pos.s.pos3_val = 1;
+            bsel_pos.s.pos3 = val & 0x7f;
+            break;
+        case 4:
+            bsel_pos.s.pos4_val = 1;
+            bsel_pos.s.pos4 = val & 0x7f;
+            break;
+        case 5:
+            bsel_pos.s.pos5_val = 1;
+            bsel_pos.s.pos5 = val & 0x7f;
+            break;
+        case 6:
+            bsel_pos.s.pos6_val = 1;
+            bsel_pos.s.pos6 = val & 0x7f;
+            break;
+        case 7:
+            bsel_pos.s.pos7_val = 1;
+            bsel_pos.s.pos7 = val & 0x7f;
+            break;
+        default:
+            cvmx_dprintf("Warning: cvmx_pip_set_bsel_pos: Invalid pos(%d)\n", pos);
+            break;
+    }
+    cvmx_write_csr(CVMX_PIP_BSEL_EXT_POSX(bit), bsel_pos.u64);
+}
+
+/**
+ * Initialize offset and skip values to use by bit select extractor.
+
+ * @param bit     Bit Select Extractor to use
+ * @param offset  Offset to add to extractor mem addr to get final address
+                  to lookup table.
+ * @param skip    Number of bytes to skip from start of packet 0-64
+ */
+static inline void cvmx_pip_bsel_config(int bit, int offset, int skip)
+{
+    cvmx_pip_bsel_ext_cfgx_t bsel_cfg;
+
+    /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
+    if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
+        return;
+
+    bsel_cfg.u64 = cvmx_read_csr(CVMX_PIP_BSEL_EXT_CFGX(bit));
+    bsel_cfg.s.offset = offset;
+    bsel_cfg.s.skip = skip;
+    cvmx_write_csr(CVMX_PIP_BSEL_EXT_CFGX(bit), bsel_cfg.u64);
+}
+
+
+/**
+ * Get the entry for the Bit Select Extractor Table. 
+ * @param work   pointer to work queue entry
+ * @return       Index of the Bit Select Extractor Table
+ */
+static inline int cvmx_pip_get_bsel_table_index(cvmx_wqe_t *work)
+{
+    int bit = cvmx_wqe_get_port(work) & 0x3;
+    /* Get the Bit select table index. */
+    int index;
+    int y;
+    cvmx_pip_bsel_ext_cfgx_t bsel_cfg;
+    cvmx_pip_bsel_ext_posx_t bsel_pos;
+
+    /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
+    if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
+        return -1;
+
+    bsel_cfg.u64 = cvmx_read_csr(CVMX_PIP_BSEL_EXT_CFGX(bit));
+    bsel_pos.u64 = cvmx_read_csr(CVMX_PIP_BSEL_EXT_POSX(bit));
+
+    for (y = 0; y < 8; y++)
+    {
+        char *ptr = (char *)cvmx_phys_to_ptr(work->packet_ptr.s.addr);
+        int bit_loc = 0;
+        int bit;
+
+        ptr += bsel_cfg.s.skip;
+        switch(y)
+        {
+            case 0:
+                ptr += (bsel_pos.s.pos0 >> 3);
+                bit_loc = 7 - (bsel_pos.s.pos0 & 0x3);
+                break;
+            case 1:
+                ptr += (bsel_pos.s.pos1 >> 3);
+                bit_loc = 7 - (bsel_pos.s.pos1 & 0x3);
+                break;
+            case 2:
+                ptr += (bsel_pos.s.pos2 >> 3);
+                bit_loc = 7 - (bsel_pos.s.pos2 & 0x3);
+                break;
+            case 3:
+                ptr += (bsel_pos.s.pos3 >> 3);
+                bit_loc = 7 - (bsel_pos.s.pos3 & 0x3);
+                break;
+            case 4:
+                ptr += (bsel_pos.s.pos4 >> 3);
+                bit_loc = 7 - (bsel_pos.s.pos4 & 0x3);
+                break;
+            case 5:
+                ptr += (bsel_pos.s.pos5 >> 3);
+                bit_loc = 7 - (bsel_pos.s.pos5 & 0x3);
+                break;
+            case 6:
+                ptr += (bsel_pos.s.pos6 >> 3);
+                bit_loc = 7 - (bsel_pos.s.pos6 & 0x3);
+                break;
+            case 7:
+                ptr += (bsel_pos.s.pos7 >> 3);
+                bit_loc = 7 - (bsel_pos.s.pos7 & 0x3);
+                break;
+        }
+        bit = (*ptr >> bit_loc) & 1;
+        index |= bit << y;
+    }
+    index += bsel_cfg.s.offset;
+    index &= 0x1ff;
+    return index;
+}
+
+static inline int cvmx_pip_get_bsel_qos(cvmx_wqe_t *work)
+{
+    int index = cvmx_pip_get_bsel_table_index(work);
+    cvmx_pip_bsel_tbl_entx_t bsel_tbl;
+
+    /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
+    if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
+        return -1;
+
+    bsel_tbl.u64 = cvmx_read_csr(CVMX_PIP_BSEL_TBL_ENTX(index));
+
+    return bsel_tbl.s.qos;
+}
+                                                                                
+static inline int cvmx_pip_get_bsel_grp(cvmx_wqe_t *work)
+{
+    int index = cvmx_pip_get_bsel_table_index(work);
+    cvmx_pip_bsel_tbl_entx_t bsel_tbl;
+
+    /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
+    if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
+        return -1;
+
+    bsel_tbl.u64 = cvmx_read_csr(CVMX_PIP_BSEL_TBL_ENTX(index));
+
+    return bsel_tbl.s.grp;
+}
+                                                                                
+static inline int cvmx_pip_get_bsel_tt(cvmx_wqe_t *work)
+{
+    int index = cvmx_pip_get_bsel_table_index(work);
+    cvmx_pip_bsel_tbl_entx_t bsel_tbl;
+
+    /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
+    if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
+        return -1;
+
+    bsel_tbl.u64 = cvmx_read_csr(CVMX_PIP_BSEL_TBL_ENTX(index));
+
+    return bsel_tbl.s.tt;
+}
+                                                                                
+static inline int cvmx_pip_get_bsel_tag(cvmx_wqe_t *work)
+{
+    int index = cvmx_pip_get_bsel_table_index(work);
+    int port = cvmx_wqe_get_port(work);
+    int bit = port & 0x3;
+    int upper_tag = 0;
+    cvmx_pip_bsel_tbl_entx_t bsel_tbl;
+    cvmx_pip_bsel_ext_cfgx_t bsel_cfg;
+    cvmx_pip_prt_tagx_t prt_tag;
+
+    /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
+    if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
+        return -1;
+
+    bsel_tbl.u64 = cvmx_read_csr(CVMX_PIP_BSEL_TBL_ENTX(index));
+    bsel_cfg.u64 = cvmx_read_csr(CVMX_PIP_BSEL_EXT_CFGX(bit));
+
+    prt_tag.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(port));
+    if (prt_tag.s.inc_prt_flag == 0) 
+        upper_tag = bsel_cfg.s.upper_tag;
+    return (bsel_tbl.s.tag | ((bsel_cfg.s.tag << 8) & 0xff00) | ((upper_tag << 16) & 0xffff0000));
+}
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-pko-defs.h b/sys/contrib/octeon-sdk/cvmx-pko-defs.h
index 8c626a6..24ddea8 100644
--- a/sys/contrib/octeon-sdk/cvmx-pko-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-pko-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_PKO_TYPEDEFS_H__
-#define __CVMX_PKO_TYPEDEFS_H__
+#ifndef __CVMX_PKO_DEFS_H__
+#define __CVMX_PKO_DEFS_H__
 
 #define CVMX_PKO_MEM_COUNT0 (CVMX_ADD_IO_SEG(0x0001180050001080ull))
 #define CVMX_PKO_MEM_COUNT1 (CVMX_ADD_IO_SEG(0x0001180050001088ull))
@@ -64,7 +64,7 @@
 #define CVMX_PKO_MEM_DEBUG14 CVMX_PKO_MEM_DEBUG14_FUNC()
 static inline uint64_t CVMX_PKO_MEM_DEBUG14_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PKO_MEM_DEBUG14 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180050001170ull);
 }
@@ -80,10 +80,54 @@ static inline uint64_t CVMX_PKO_MEM_DEBUG14_FUNC(void)
 #define CVMX_PKO_MEM_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180050001140ull))
 #define CVMX_PKO_MEM_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180050001148ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_MEM_IPORT_PTRS CVMX_PKO_MEM_IPORT_PTRS_FUNC()
+static inline uint64_t CVMX_PKO_MEM_IPORT_PTRS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_PKO_MEM_IPORT_PTRS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050001030ull);
+}
+#else
+#define CVMX_PKO_MEM_IPORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001030ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_MEM_IPORT_QOS CVMX_PKO_MEM_IPORT_QOS_FUNC()
+static inline uint64_t CVMX_PKO_MEM_IPORT_QOS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_PKO_MEM_IPORT_QOS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050001038ull);
+}
+#else
+#define CVMX_PKO_MEM_IPORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001038ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_MEM_IQUEUE_PTRS CVMX_PKO_MEM_IQUEUE_PTRS_FUNC()
+static inline uint64_t CVMX_PKO_MEM_IQUEUE_PTRS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_PKO_MEM_IQUEUE_PTRS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050001040ull);
+}
+#else
+#define CVMX_PKO_MEM_IQUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001040ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_MEM_IQUEUE_QOS CVMX_PKO_MEM_IQUEUE_QOS_FUNC()
+static inline uint64_t CVMX_PKO_MEM_IQUEUE_QOS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_PKO_MEM_IQUEUE_QOS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050001048ull);
+}
+#else
+#define CVMX_PKO_MEM_IQUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001048ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_PKO_MEM_PORT_PTRS CVMX_PKO_MEM_PORT_PTRS_FUNC()
 static inline uint64_t CVMX_PKO_MEM_PORT_PTRS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PKO_MEM_PORT_PTRS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180050001010ull);
 }
@@ -94,7 +138,7 @@ static inline uint64_t CVMX_PKO_MEM_PORT_PTRS_FUNC(void)
 #define CVMX_PKO_MEM_PORT_QOS CVMX_PKO_MEM_PORT_QOS_FUNC()
 static inline uint64_t CVMX_PKO_MEM_PORT_QOS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PKO_MEM_PORT_QOS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180050001018ull);
 }
@@ -105,7 +149,7 @@ static inline uint64_t CVMX_PKO_MEM_PORT_QOS_FUNC(void)
 #define CVMX_PKO_MEM_PORT_RATE0 CVMX_PKO_MEM_PORT_RATE0_FUNC()
 static inline uint64_t CVMX_PKO_MEM_PORT_RATE0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PKO_MEM_PORT_RATE0 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180050001020ull);
 }
@@ -116,15 +160,57 @@ static inline uint64_t CVMX_PKO_MEM_PORT_RATE0_FUNC(void)
 #define CVMX_PKO_MEM_PORT_RATE1 CVMX_PKO_MEM_PORT_RATE1_FUNC()
 static inline uint64_t CVMX_PKO_MEM_PORT_RATE1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PKO_MEM_PORT_RATE1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180050001028ull);
 }
 #else
 #define CVMX_PKO_MEM_PORT_RATE1 (CVMX_ADD_IO_SEG(0x0001180050001028ull))
 #endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_MEM_QUEUE_PTRS CVMX_PKO_MEM_QUEUE_PTRS_FUNC()
+static inline uint64_t CVMX_PKO_MEM_QUEUE_PTRS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_PKO_MEM_QUEUE_PTRS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050001000ull);
+}
+#else
 #define CVMX_PKO_MEM_QUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_MEM_QUEUE_QOS CVMX_PKO_MEM_QUEUE_QOS_FUNC()
+static inline uint64_t CVMX_PKO_MEM_QUEUE_QOS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_PKO_MEM_QUEUE_QOS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050001008ull);
+}
+#else
 #define CVMX_PKO_MEM_QUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_MEM_THROTTLE_INT CVMX_PKO_MEM_THROTTLE_INT_FUNC()
+static inline uint64_t CVMX_PKO_MEM_THROTTLE_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_PKO_MEM_THROTTLE_INT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050001058ull);
+}
+#else
+#define CVMX_PKO_MEM_THROTTLE_INT (CVMX_ADD_IO_SEG(0x0001180050001058ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_MEM_THROTTLE_PIPE CVMX_PKO_MEM_THROTTLE_PIPE_FUNC()
+static inline uint64_t CVMX_PKO_MEM_THROTTLE_PIPE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_PKO_MEM_THROTTLE_PIPE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050001050ull);
+}
+#else
+#define CVMX_PKO_MEM_THROTTLE_PIPE (CVMX_ADD_IO_SEG(0x0001180050001050ull))
+#endif
 #define CVMX_PKO_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180050000080ull))
 #define CVMX_PKO_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180050000010ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
@@ -167,7 +253,7 @@ static inline uint64_t CVMX_PKO_REG_CRC_IVX(unsigned long offset)
 #define CVMX_PKO_REG_DEBUG1 CVMX_PKO_REG_DEBUG1_FUNC()
 static inline uint64_t CVMX_PKO_REG_DEBUG1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PKO_REG_DEBUG1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800500000A0ull);
 }
@@ -178,7 +264,7 @@ static inline uint64_t CVMX_PKO_REG_DEBUG1_FUNC(void)
 #define CVMX_PKO_REG_DEBUG2 CVMX_PKO_REG_DEBUG2_FUNC()
 static inline uint64_t CVMX_PKO_REG_DEBUG2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PKO_REG_DEBUG2 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800500000A8ull);
 }
@@ -189,7 +275,7 @@ static inline uint64_t CVMX_PKO_REG_DEBUG2_FUNC(void)
 #define CVMX_PKO_REG_DEBUG3 CVMX_PKO_REG_DEBUG3_FUNC()
 static inline uint64_t CVMX_PKO_REG_DEBUG3_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PKO_REG_DEBUG3 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800500000B0ull);
 }
@@ -197,10 +283,21 @@ static inline uint64_t CVMX_PKO_REG_DEBUG3_FUNC(void)
 #define CVMX_PKO_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x00011800500000B0ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_REG_DEBUG4 CVMX_PKO_REG_DEBUG4_FUNC()
+static inline uint64_t CVMX_PKO_REG_DEBUG4_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_PKO_REG_DEBUG4 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800500000B8ull);
+}
+#else
+#define CVMX_PKO_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x00011800500000B8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_PKO_REG_ENGINE_INFLIGHT CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC()
 static inline uint64_t CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PKO_REG_ENGINE_INFLIGHT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180050000050ull);
 }
@@ -208,10 +305,32 @@ static inline uint64_t CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC(void)
 #define CVMX_PKO_REG_ENGINE_INFLIGHT (CVMX_ADD_IO_SEG(0x0001180050000050ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_REG_ENGINE_INFLIGHT1 CVMX_PKO_REG_ENGINE_INFLIGHT1_FUNC()
+static inline uint64_t CVMX_PKO_REG_ENGINE_INFLIGHT1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_PKO_REG_ENGINE_INFLIGHT1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050000318ull);
+}
+#else
+#define CVMX_PKO_REG_ENGINE_INFLIGHT1 (CVMX_ADD_IO_SEG(0x0001180050000318ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PKO_REG_ENGINE_STORAGEX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_PKO_REG_ENGINE_STORAGEX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180050000300ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_PKO_REG_ENGINE_STORAGEX(offset) (CVMX_ADD_IO_SEG(0x0001180050000300ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_PKO_REG_ENGINE_THRESH CVMX_PKO_REG_ENGINE_THRESH_FUNC()
 static inline uint64_t CVMX_PKO_REG_ENGINE_THRESH_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PKO_REG_ENGINE_THRESH not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180050000058ull);
 }
@@ -220,14 +339,79 @@ static inline uint64_t CVMX_PKO_REG_ENGINE_THRESH_FUNC(void)
 #endif
 #define CVMX_PKO_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180050000088ull))
 #define CVMX_PKO_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180050000000ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_REG_GMX_PORT_MODE CVMX_PKO_REG_GMX_PORT_MODE_FUNC()
+static inline uint64_t CVMX_PKO_REG_GMX_PORT_MODE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_PKO_REG_GMX_PORT_MODE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050000018ull);
+}
+#else
 #define CVMX_PKO_REG_GMX_PORT_MODE (CVMX_ADD_IO_SEG(0x0001180050000018ull))
+#endif
 #define CVMX_PKO_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180050000090ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_REG_LOOPBACK_BPID CVMX_PKO_REG_LOOPBACK_BPID_FUNC()
+static inline uint64_t CVMX_PKO_REG_LOOPBACK_BPID_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_PKO_REG_LOOPBACK_BPID not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050000118ull);
+}
+#else
+#define CVMX_PKO_REG_LOOPBACK_BPID (CVMX_ADD_IO_SEG(0x0001180050000118ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_REG_LOOPBACK_PKIND CVMX_PKO_REG_LOOPBACK_PKIND_FUNC()
+static inline uint64_t CVMX_PKO_REG_LOOPBACK_PKIND_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_PKO_REG_LOOPBACK_PKIND not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050000068ull);
+}
+#else
+#define CVMX_PKO_REG_LOOPBACK_PKIND (CVMX_ADD_IO_SEG(0x0001180050000068ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_REG_MIN_PKT CVMX_PKO_REG_MIN_PKT_FUNC()
+static inline uint64_t CVMX_PKO_REG_MIN_PKT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_PKO_REG_MIN_PKT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050000070ull);
+}
+#else
+#define CVMX_PKO_REG_MIN_PKT (CVMX_ADD_IO_SEG(0x0001180050000070ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_REG_PREEMPT CVMX_PKO_REG_PREEMPT_FUNC()
+static inline uint64_t CVMX_PKO_REG_PREEMPT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_PKO_REG_PREEMPT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050000110ull);
+}
+#else
+#define CVMX_PKO_REG_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000110ull))
+#endif
 #define CVMX_PKO_REG_QUEUE_MODE (CVMX_ADD_IO_SEG(0x0001180050000048ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_REG_QUEUE_PREEMPT CVMX_PKO_REG_QUEUE_PREEMPT_FUNC()
+static inline uint64_t CVMX_PKO_REG_QUEUE_PREEMPT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_PKO_REG_QUEUE_PREEMPT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050000108ull);
+}
+#else
+#define CVMX_PKO_REG_QUEUE_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000108ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_PKO_REG_QUEUE_PTRS1 CVMX_PKO_REG_QUEUE_PTRS1_FUNC()
 static inline uint64_t CVMX_PKO_REG_QUEUE_PTRS1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PKO_REG_QUEUE_PTRS1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180050000100ull);
 }
@@ -236,10 +420,21 @@ static inline uint64_t CVMX_PKO_REG_QUEUE_PTRS1_FUNC(void)
 #endif
 #define CVMX_PKO_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180050000008ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_REG_THROTTLE CVMX_PKO_REG_THROTTLE_FUNC()
+static inline uint64_t CVMX_PKO_REG_THROTTLE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_PKO_REG_THROTTLE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050000078ull);
+}
+#else
+#define CVMX_PKO_REG_THROTTLE (CVMX_ADD_IO_SEG(0x0001180050000078ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_PKO_REG_TIMESTAMP CVMX_PKO_REG_TIMESTAMP_FUNC()
 static inline uint64_t CVMX_PKO_REG_TIMESTAMP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_PKO_REG_TIMESTAMP not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180050000060ull);
 }
@@ -257,12 +452,10 @@ static inline uint64_t CVMX_PKO_REG_TIMESTAMP_FUNC(void)
  * CSR read operations to this address can be performed.  A read of any entry that has not been
  * previously written is illegal and will result in unpredictable CSR read data.
  */
-union cvmx_pko_mem_count0
-{
+union cvmx_pko_mem_count0 {
 	uint64_t u64;
-	struct cvmx_pko_mem_count0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_count0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t count                        : 32; /**< Total number of packets seen by PKO */
 #else
@@ -281,8 +474,13 @@ union cvmx_pko_mem_count0
 	struct cvmx_pko_mem_count0_s          cn56xxp1;
 	struct cvmx_pko_mem_count0_s          cn58xx;
 	struct cvmx_pko_mem_count0_s          cn58xxp1;
+	struct cvmx_pko_mem_count0_s          cn61xx;
 	struct cvmx_pko_mem_count0_s          cn63xx;
 	struct cvmx_pko_mem_count0_s          cn63xxp1;
+	struct cvmx_pko_mem_count0_s          cn66xx;
+	struct cvmx_pko_mem_count0_s          cn68xx;
+	struct cvmx_pko_mem_count0_s          cn68xxp1;
+	struct cvmx_pko_mem_count0_s          cnf71xx;
 };
 typedef union cvmx_pko_mem_count0 cvmx_pko_mem_count0_t;
 
@@ -296,12 +494,10 @@ typedef union cvmx_pko_mem_count0 cvmx_pko_mem_count0_t;
  * CSR read operations to this address can be performed.  A read of any entry that has not been
  * previously written is illegal and will result in unpredictable CSR read data.
  */
-union cvmx_pko_mem_count1
-{
+union cvmx_pko_mem_count1 {
 	uint64_t u64;
-	struct cvmx_pko_mem_count1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_count1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t count                        : 48; /**< Total number of bytes seen by PKO */
 #else
@@ -320,8 +516,13 @@ union cvmx_pko_mem_count1
 	struct cvmx_pko_mem_count1_s          cn56xxp1;
 	struct cvmx_pko_mem_count1_s          cn58xx;
 	struct cvmx_pko_mem_count1_s          cn58xxp1;
+	struct cvmx_pko_mem_count1_s          cn61xx;
 	struct cvmx_pko_mem_count1_s          cn63xx;
 	struct cvmx_pko_mem_count1_s          cn63xxp1;
+	struct cvmx_pko_mem_count1_s          cn66xx;
+	struct cvmx_pko_mem_count1_s          cn68xx;
+	struct cvmx_pko_mem_count1_s          cn68xxp1;
+	struct cvmx_pko_mem_count1_s          cnf71xx;
 };
 typedef union cvmx_pko_mem_count1 cvmx_pko_mem_count1_t;
 
@@ -333,12 +534,10 @@ typedef union cvmx_pko_mem_count1 cvmx_pko_mem_count1_t;
  * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_pko_mem_debug0
-{
+union cvmx_pko_mem_debug0 {
 	uint64_t u64;
-	struct cvmx_pko_mem_debug0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t fau                          : 28; /**< Fetch and add command words */
 	uint64_t cmd                          : 14; /**< Command word */
 	uint64_t segs                         : 6;  /**< Number of segments/gather size */
@@ -361,8 +560,13 @@ union cvmx_pko_mem_debug0
 	struct cvmx_pko_mem_debug0_s          cn56xxp1;
 	struct cvmx_pko_mem_debug0_s          cn58xx;
 	struct cvmx_pko_mem_debug0_s          cn58xxp1;
+	struct cvmx_pko_mem_debug0_s          cn61xx;
 	struct cvmx_pko_mem_debug0_s          cn63xx;
 	struct cvmx_pko_mem_debug0_s          cn63xxp1;
+	struct cvmx_pko_mem_debug0_s          cn66xx;
+	struct cvmx_pko_mem_debug0_s          cn68xx;
+	struct cvmx_pko_mem_debug0_s          cn68xxp1;
+	struct cvmx_pko_mem_debug0_s          cnf71xx;
 };
 typedef union cvmx_pko_mem_debug0 cvmx_pko_mem_debug0_t;
 
@@ -374,12 +578,10 @@ typedef union cvmx_pko_mem_debug0 cvmx_pko_mem_debug0_t;
  * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_pko_mem_debug1
-{
+union cvmx_pko_mem_debug1 {
 	uint64_t u64;
-	struct cvmx_pko_mem_debug1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t i                            : 1;  /**< "I"  value used for free operation */
 	uint64_t back                         : 4;  /**< Back value used for free operation */
 	uint64_t pool                         : 3;  /**< Pool value used for free operation */
@@ -404,8 +606,13 @@ union cvmx_pko_mem_debug1
 	struct cvmx_pko_mem_debug1_s          cn56xxp1;
 	struct cvmx_pko_mem_debug1_s          cn58xx;
 	struct cvmx_pko_mem_debug1_s          cn58xxp1;
+	struct cvmx_pko_mem_debug1_s          cn61xx;
 	struct cvmx_pko_mem_debug1_s          cn63xx;
 	struct cvmx_pko_mem_debug1_s          cn63xxp1;
+	struct cvmx_pko_mem_debug1_s          cn66xx;
+	struct cvmx_pko_mem_debug1_s          cn68xx;
+	struct cvmx_pko_mem_debug1_s          cn68xxp1;
+	struct cvmx_pko_mem_debug1_s          cnf71xx;
 };
 typedef union cvmx_pko_mem_debug1 cvmx_pko_mem_debug1_t;
 
@@ -417,20 +624,17 @@ typedef union cvmx_pko_mem_debug1 cvmx_pko_mem_debug1_t;
  * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_pko_mem_debug10
-{
+union cvmx_pko_mem_debug10 {
 	uint64_t u64;
-	struct cvmx_pko_mem_debug10_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug10_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_0_63                : 64;
 #else
 	uint64_t reserved_0_63                : 64;
 #endif
 	} s;
-	struct cvmx_pko_mem_debug10_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug10_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t fau                          : 28; /**< Fetch and add command words */
 	uint64_t cmd                          : 14; /**< Command word */
 	uint64_t segs                         : 6;  /**< Number of segments/gather size */
@@ -445,9 +649,8 @@ union cvmx_pko_mem_debug10
 	struct cvmx_pko_mem_debug10_cn30xx    cn31xx;
 	struct cvmx_pko_mem_debug10_cn30xx    cn38xx;
 	struct cvmx_pko_mem_debug10_cn30xx    cn38xxp2;
-	struct cvmx_pko_mem_debug10_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug10_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_49_63               : 15;
 	uint64_t ptrs1                        : 17; /**< Internal state */
 	uint64_t reserved_17_31               : 15;
@@ -465,8 +668,13 @@ union cvmx_pko_mem_debug10
 	struct cvmx_pko_mem_debug10_cn50xx    cn56xxp1;
 	struct cvmx_pko_mem_debug10_cn50xx    cn58xx;
 	struct cvmx_pko_mem_debug10_cn50xx    cn58xxp1;
+	struct cvmx_pko_mem_debug10_cn50xx    cn61xx;
 	struct cvmx_pko_mem_debug10_cn50xx    cn63xx;
 	struct cvmx_pko_mem_debug10_cn50xx    cn63xxp1;
+	struct cvmx_pko_mem_debug10_cn50xx    cn66xx;
+	struct cvmx_pko_mem_debug10_cn50xx    cn68xx;
+	struct cvmx_pko_mem_debug10_cn50xx    cn68xxp1;
+	struct cvmx_pko_mem_debug10_cn50xx    cnf71xx;
 };
 typedef union cvmx_pko_mem_debug10 cvmx_pko_mem_debug10_t;
 
@@ -478,12 +686,10 @@ typedef union cvmx_pko_mem_debug10 cvmx_pko_mem_debug10_t;
  * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_pko_mem_debug11
-{
+union cvmx_pko_mem_debug11 {
 	uint64_t u64;
-	struct cvmx_pko_mem_debug11_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug11_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t i                            : 1;  /**< "I"  value used for free operation */
 	uint64_t back                         : 4;  /**< Back value used for free operation */
 	uint64_t pool                         : 3;  /**< Pool value used for free operation */
@@ -497,9 +703,8 @@ union cvmx_pko_mem_debug11
 	uint64_t i                            : 1;
 #endif
 	} s;
-	struct cvmx_pko_mem_debug11_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug11_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t i                            : 1;  /**< "I"  value used for free operation */
 	uint64_t back                         : 4;  /**< Back value used for free operation */
 	uint64_t pool                         : 3;  /**< Pool value used for free operation */
@@ -516,9 +721,8 @@ union cvmx_pko_mem_debug11
 	struct cvmx_pko_mem_debug11_cn30xx    cn31xx;
 	struct cvmx_pko_mem_debug11_cn30xx    cn38xx;
 	struct cvmx_pko_mem_debug11_cn30xx    cn38xxp2;
-	struct cvmx_pko_mem_debug11_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug11_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_23_63               : 41;
 	uint64_t maj                          : 1;  /**< Internal state */
 	uint64_t uid                          : 3;  /**< Internal state */
@@ -544,8 +748,13 @@ union cvmx_pko_mem_debug11
 	struct cvmx_pko_mem_debug11_cn50xx    cn56xxp1;
 	struct cvmx_pko_mem_debug11_cn50xx    cn58xx;
 	struct cvmx_pko_mem_debug11_cn50xx    cn58xxp1;
+	struct cvmx_pko_mem_debug11_cn50xx    cn61xx;
 	struct cvmx_pko_mem_debug11_cn50xx    cn63xx;
 	struct cvmx_pko_mem_debug11_cn50xx    cn63xxp1;
+	struct cvmx_pko_mem_debug11_cn50xx    cn66xx;
+	struct cvmx_pko_mem_debug11_cn50xx    cn68xx;
+	struct cvmx_pko_mem_debug11_cn50xx    cn68xxp1;
+	struct cvmx_pko_mem_debug11_cn50xx    cnf71xx;
 };
 typedef union cvmx_pko_mem_debug11 cvmx_pko_mem_debug11_t;
 
@@ -557,20 +766,17 @@ typedef union cvmx_pko_mem_debug11 cvmx_pko_mem_debug11_t;
  * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_pko_mem_debug12
-{
+union cvmx_pko_mem_debug12 {
 	uint64_t u64;
-	struct cvmx_pko_mem_debug12_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug12_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_0_63                : 64;
 #else
 	uint64_t reserved_0_63                : 64;
 #endif
 	} s;
-	struct cvmx_pko_mem_debug12_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug12_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 64; /**< WorkQ data or Store0 pointer */
 #else
 	uint64_t data                         : 64;
@@ -579,9 +785,8 @@ union cvmx_pko_mem_debug12
 	struct cvmx_pko_mem_debug12_cn30xx    cn31xx;
 	struct cvmx_pko_mem_debug12_cn30xx    cn38xx;
 	struct cvmx_pko_mem_debug12_cn30xx    cn38xxp2;
-	struct cvmx_pko_mem_debug12_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug12_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t fau                          : 28; /**< Fetch and add command words */
 	uint64_t cmd                          : 14; /**< Command word */
 	uint64_t segs                         : 6;  /**< Number of segments/gather size */
@@ -599,8 +804,19 @@ union cvmx_pko_mem_debug12
 	struct cvmx_pko_mem_debug12_cn50xx    cn56xxp1;
 	struct cvmx_pko_mem_debug12_cn50xx    cn58xx;
 	struct cvmx_pko_mem_debug12_cn50xx    cn58xxp1;
+	struct cvmx_pko_mem_debug12_cn50xx    cn61xx;
 	struct cvmx_pko_mem_debug12_cn50xx    cn63xx;
 	struct cvmx_pko_mem_debug12_cn50xx    cn63xxp1;
+	struct cvmx_pko_mem_debug12_cn50xx    cn66xx;
+	struct cvmx_pko_mem_debug12_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t state                        : 64; /**< Internal state */
+#else
+	uint64_t state                        : 64;
+#endif
+	} cn68xx;
+	struct cvmx_pko_mem_debug12_cn68xx    cn68xxp1;
+	struct cvmx_pko_mem_debug12_cn50xx    cnf71xx;
 };
 typedef union cvmx_pko_mem_debug12 cvmx_pko_mem_debug12_t;
 
@@ -612,26 +828,17 @@ typedef union cvmx_pko_mem_debug12 cvmx_pko_mem_debug12_t;
  * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_pko_mem_debug13
-{
+union cvmx_pko_mem_debug13 {
 	uint64_t u64;
-	struct cvmx_pko_mem_debug13_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t i                            : 1;  /**< "I"  value used for free operation */
-	uint64_t back                         : 4;  /**< Back value used for free operation */
-	uint64_t pool                         : 3;  /**< Pool value used for free operation */
-	uint64_t reserved_0_55                : 56;
+	struct cvmx_pko_mem_debug13_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_0_63                : 64;
 #else
-	uint64_t reserved_0_55                : 56;
-	uint64_t pool                         : 3;
-	uint64_t back                         : 4;
-	uint64_t i                            : 1;
+	uint64_t reserved_0_63                : 64;
 #endif
 	} s;
-	struct cvmx_pko_mem_debug13_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug13_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_51_63               : 13;
 	uint64_t widx                         : 17; /**< PDB widx */
 	uint64_t ridx2                        : 17; /**< PDB ridx2 */
@@ -646,9 +853,8 @@ union cvmx_pko_mem_debug13
 	struct cvmx_pko_mem_debug13_cn30xx    cn31xx;
 	struct cvmx_pko_mem_debug13_cn30xx    cn38xx;
 	struct cvmx_pko_mem_debug13_cn30xx    cn38xxp2;
-	struct cvmx_pko_mem_debug13_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug13_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t i                            : 1;  /**< "I"  value used for free operation */
 	uint64_t back                         : 4;  /**< Back value used for free operation */
 	uint64_t pool                         : 3;  /**< Pool value used for free operation */
@@ -668,8 +874,19 @@ union cvmx_pko_mem_debug13
 	struct cvmx_pko_mem_debug13_cn50xx    cn56xxp1;
 	struct cvmx_pko_mem_debug13_cn50xx    cn58xx;
 	struct cvmx_pko_mem_debug13_cn50xx    cn58xxp1;
+	struct cvmx_pko_mem_debug13_cn50xx    cn61xx;
 	struct cvmx_pko_mem_debug13_cn50xx    cn63xx;
 	struct cvmx_pko_mem_debug13_cn50xx    cn63xxp1;
+	struct cvmx_pko_mem_debug13_cn50xx    cn66xx;
+	struct cvmx_pko_mem_debug13_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t state                        : 64; /**< Internal state */
+#else
+	uint64_t state                        : 64;
+#endif
+	} cn68xx;
+	struct cvmx_pko_mem_debug13_cn68xx    cn68xxp1;
+	struct cvmx_pko_mem_debug13_cn50xx    cnf71xx;
 };
 typedef union cvmx_pko_mem_debug13 cvmx_pko_mem_debug13_t;
 
@@ -681,20 +898,17 @@ typedef union cvmx_pko_mem_debug13 cvmx_pko_mem_debug13_t;
  * This CSR is a memory of 132 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_pko_mem_debug14
-{
+union cvmx_pko_mem_debug14 {
 	uint64_t u64;
-	struct cvmx_pko_mem_debug14_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug14_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_0_63                : 64;
 #else
 	uint64_t reserved_0_63                : 64;
 #endif
 	} s;
-	struct cvmx_pko_mem_debug14_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug14_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t ridx                         : 17; /**< PDB ridx */
 #else
@@ -705,9 +919,8 @@ union cvmx_pko_mem_debug14
 	struct cvmx_pko_mem_debug14_cn30xx    cn31xx;
 	struct cvmx_pko_mem_debug14_cn30xx    cn38xx;
 	struct cvmx_pko_mem_debug14_cn30xx    cn38xxp2;
-	struct cvmx_pko_mem_debug14_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug14_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 64; /**< Command words */
 #else
 	uint64_t data                         : 64;
@@ -716,8 +929,11 @@ union cvmx_pko_mem_debug14
 	struct cvmx_pko_mem_debug14_cn52xx    cn52xxp1;
 	struct cvmx_pko_mem_debug14_cn52xx    cn56xx;
 	struct cvmx_pko_mem_debug14_cn52xx    cn56xxp1;
+	struct cvmx_pko_mem_debug14_cn52xx    cn61xx;
 	struct cvmx_pko_mem_debug14_cn52xx    cn63xx;
 	struct cvmx_pko_mem_debug14_cn52xx    cn63xxp1;
+	struct cvmx_pko_mem_debug14_cn52xx    cn66xx;
+	struct cvmx_pko_mem_debug14_cn52xx    cnf71xx;
 };
 typedef union cvmx_pko_mem_debug14 cvmx_pko_mem_debug14_t;
 
@@ -729,12 +945,10 @@ typedef union cvmx_pko_mem_debug14 cvmx_pko_mem_debug14_t;
  * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_pko_mem_debug2
-{
+union cvmx_pko_mem_debug2 {
 	uint64_t u64;
-	struct cvmx_pko_mem_debug2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t i                            : 1;  /**< "I"  value used for free operation */
 	uint64_t back                         : 4;  /**< Back value used for free operation */
 	uint64_t pool                         : 3;  /**< Pool value used for free operation */
@@ -759,8 +973,13 @@ union cvmx_pko_mem_debug2
 	struct cvmx_pko_mem_debug2_s          cn56xxp1;
 	struct cvmx_pko_mem_debug2_s          cn58xx;
 	struct cvmx_pko_mem_debug2_s          cn58xxp1;
+	struct cvmx_pko_mem_debug2_s          cn61xx;
 	struct cvmx_pko_mem_debug2_s          cn63xx;
 	struct cvmx_pko_mem_debug2_s          cn63xxp1;
+	struct cvmx_pko_mem_debug2_s          cn66xx;
+	struct cvmx_pko_mem_debug2_s          cn68xx;
+	struct cvmx_pko_mem_debug2_s          cn68xxp1;
+	struct cvmx_pko_mem_debug2_s          cnf71xx;
 };
 typedef union cvmx_pko_mem_debug2 cvmx_pko_mem_debug2_t;
 
@@ -772,20 +991,17 @@ typedef union cvmx_pko_mem_debug2 cvmx_pko_mem_debug2_t;
  * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_pko_mem_debug3
-{
+union cvmx_pko_mem_debug3 {
 	uint64_t u64;
-	struct cvmx_pko_mem_debug3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_0_63                : 64;
 #else
 	uint64_t reserved_0_63                : 64;
 #endif
 	} s;
-	struct cvmx_pko_mem_debug3_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug3_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t i                            : 1;  /**< "I"  value used for free operation */
 	uint64_t back                         : 4;  /**< Back value used for free operation */
 	uint64_t pool                         : 3;  /**< Pool value used for free operation */
@@ -802,9 +1018,8 @@ union cvmx_pko_mem_debug3
 	struct cvmx_pko_mem_debug3_cn30xx     cn31xx;
 	struct cvmx_pko_mem_debug3_cn30xx     cn38xx;
 	struct cvmx_pko_mem_debug3_cn30xx     cn38xxp2;
-	struct cvmx_pko_mem_debug3_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug3_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 64; /**< WorkQ data or Store0 pointer */
 #else
 	uint64_t data                         : 64;
@@ -816,8 +1031,13 @@ union cvmx_pko_mem_debug3
 	struct cvmx_pko_mem_debug3_cn50xx     cn56xxp1;
 	struct cvmx_pko_mem_debug3_cn50xx     cn58xx;
 	struct cvmx_pko_mem_debug3_cn50xx     cn58xxp1;
+	struct cvmx_pko_mem_debug3_cn50xx     cn61xx;
 	struct cvmx_pko_mem_debug3_cn50xx     cn63xx;
 	struct cvmx_pko_mem_debug3_cn50xx     cn63xxp1;
+	struct cvmx_pko_mem_debug3_cn50xx     cn66xx;
+	struct cvmx_pko_mem_debug3_cn50xx     cn68xx;
+	struct cvmx_pko_mem_debug3_cn50xx     cn68xxp1;
+	struct cvmx_pko_mem_debug3_cn50xx     cnf71xx;
 };
 typedef union cvmx_pko_mem_debug3 cvmx_pko_mem_debug3_t;
 
@@ -829,20 +1049,17 @@ typedef union cvmx_pko_mem_debug3 cvmx_pko_mem_debug3_t;
  * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_pko_mem_debug4
-{
+union cvmx_pko_mem_debug4 {
 	uint64_t u64;
-	struct cvmx_pko_mem_debug4_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_0_63                : 64;
 #else
 	uint64_t reserved_0_63                : 64;
 #endif
 	} s;
-	struct cvmx_pko_mem_debug4_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug4_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 64; /**< WorkQ data or Store0 pointer */
 #else
 	uint64_t data                         : 64;
@@ -851,9 +1068,8 @@ union cvmx_pko_mem_debug4
 	struct cvmx_pko_mem_debug4_cn30xx     cn31xx;
 	struct cvmx_pko_mem_debug4_cn30xx     cn38xx;
 	struct cvmx_pko_mem_debug4_cn30xx     cn38xxp2;
-	struct cvmx_pko_mem_debug4_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug4_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t cmnd_segs                    : 3;  /**< Internal state */
 	uint64_t cmnd_siz                     : 16; /**< Internal state */
 	uint64_t cmnd_off                     : 6;  /**< Internal state */
@@ -893,9 +1109,8 @@ union cvmx_pko_mem_debug4
 	uint64_t cmnd_segs                    : 3;
 #endif
 	} cn50xx;
-	struct cvmx_pko_mem_debug4_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug4_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t curr_siz                     : 8;  /**< Internal state */
 	uint64_t curr_off                     : 16; /**< Internal state */
 	uint64_t cmnd_segs                    : 6;  /**< Internal state */
@@ -930,8 +1145,13 @@ union cvmx_pko_mem_debug4
 	struct cvmx_pko_mem_debug4_cn52xx     cn56xxp1;
 	struct cvmx_pko_mem_debug4_cn50xx     cn58xx;
 	struct cvmx_pko_mem_debug4_cn50xx     cn58xxp1;
+	struct cvmx_pko_mem_debug4_cn52xx     cn61xx;
 	struct cvmx_pko_mem_debug4_cn52xx     cn63xx;
 	struct cvmx_pko_mem_debug4_cn52xx     cn63xxp1;
+	struct cvmx_pko_mem_debug4_cn52xx     cn66xx;
+	struct cvmx_pko_mem_debug4_cn52xx     cn68xx;
+	struct cvmx_pko_mem_debug4_cn52xx     cn68xxp1;
+	struct cvmx_pko_mem_debug4_cn52xx     cnf71xx;
 };
 typedef union cvmx_pko_mem_debug4 cvmx_pko_mem_debug4_t;
 
@@ -943,20 +1163,17 @@ typedef union cvmx_pko_mem_debug4 cvmx_pko_mem_debug4_t;
  * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_pko_mem_debug5
-{
+union cvmx_pko_mem_debug5 {
 	uint64_t u64;
-	struct cvmx_pko_mem_debug5_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_0_63                : 64;
 #else
 	uint64_t reserved_0_63                : 64;
 #endif
 	} s;
-	struct cvmx_pko_mem_debug5_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug5_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t dwri_mod                     : 1;  /**< Dwrite mod */
 	uint64_t dwri_sop                     : 1;  /**< Dwrite sop needed */
 	uint64_t dwri_len                     : 1;  /**< Dwrite len */
@@ -1001,9 +1218,8 @@ union cvmx_pko_mem_debug5
 	struct cvmx_pko_mem_debug5_cn30xx     cn31xx;
 	struct cvmx_pko_mem_debug5_cn30xx     cn38xx;
 	struct cvmx_pko_mem_debug5_cn30xx     cn38xxp2;
-	struct cvmx_pko_mem_debug5_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug5_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t curr_ptr                     : 29; /**< Internal state */
 	uint64_t curr_siz                     : 16; /**< Internal state */
 	uint64_t curr_off                     : 16; /**< Internal state */
@@ -1015,9 +1231,8 @@ union cvmx_pko_mem_debug5
 	uint64_t curr_ptr                     : 29;
 #endif
 	} cn50xx;
-	struct cvmx_pko_mem_debug5_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug5_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_54_63               : 10;
 	uint64_t nxt_inflt                    : 6;  /**< Internal state */
 	uint64_t curr_ptr                     : 40; /**< Internal state */
@@ -1034,9 +1249,8 @@ union cvmx_pko_mem_debug5
 	struct cvmx_pko_mem_debug5_cn52xx     cn56xxp1;
 	struct cvmx_pko_mem_debug5_cn50xx     cn58xx;
 	struct cvmx_pko_mem_debug5_cn50xx     cn58xxp1;
-	struct cvmx_pko_mem_debug5_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug5_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_56_63               : 8;
 	uint64_t ptp                          : 1;  /**< Internal state */
 	uint64_t major_3                      : 1;  /**< Internal state */
@@ -1051,8 +1265,31 @@ union cvmx_pko_mem_debug5
 	uint64_t ptp                          : 1;
 	uint64_t reserved_56_63               : 8;
 #endif
-	} cn63xx;
-	struct cvmx_pko_mem_debug5_cn63xx     cn63xxp1;
+	} cn61xx;
+	struct cvmx_pko_mem_debug5_cn61xx     cn63xx;
+	struct cvmx_pko_mem_debug5_cn61xx     cn63xxp1;
+	struct cvmx_pko_mem_debug5_cn61xx     cn66xx;
+	struct cvmx_pko_mem_debug5_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_57_63               : 7;
+	uint64_t uid_2                        : 1;  /**< Internal state */
+	uint64_t ptp                          : 1;  /**< Internal state */
+	uint64_t major_3                      : 1;  /**< Internal state */
+	uint64_t nxt_inflt                    : 6;  /**< Internal state */
+	uint64_t curr_ptr                     : 40; /**< Internal state */
+	uint64_t curr_siz                     : 8;  /**< Internal state */
+#else
+	uint64_t curr_siz                     : 8;
+	uint64_t curr_ptr                     : 40;
+	uint64_t nxt_inflt                    : 6;
+	uint64_t major_3                      : 1;
+	uint64_t ptp                          : 1;
+	uint64_t uid_2                        : 1;
+	uint64_t reserved_57_63               : 7;
+#endif
+	} cn68xx;
+	struct cvmx_pko_mem_debug5_cn68xx     cn68xxp1;
+	struct cvmx_pko_mem_debug5_cn61xx     cnf71xx;
 };
 typedef union cvmx_pko_mem_debug5 cvmx_pko_mem_debug5_t;
 
@@ -1064,12 +1301,10 @@ typedef union cvmx_pko_mem_debug5 cvmx_pko_mem_debug5_t;
  * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_pko_mem_debug6
-{
+union cvmx_pko_mem_debug6 {
 	uint64_t u64;
-	struct cvmx_pko_mem_debug6_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_37_63               : 27;
 	uint64_t qid_offres                   : 4;  /**< Internal state */
 	uint64_t qid_offths                   : 4;  /**< Internal state */
@@ -1097,9 +1332,8 @@ union cvmx_pko_mem_debug6
 	uint64_t reserved_37_63               : 27;
 #endif
 	} s;
-	struct cvmx_pko_mem_debug6_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug6_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t qid_offm                     : 3;  /**< Qid offset max */
 	uint64_t static_p                     : 1;  /**< Static port when set */
@@ -1120,9 +1354,8 @@ union cvmx_pko_mem_debug6
 	struct cvmx_pko_mem_debug6_cn30xx     cn31xx;
 	struct cvmx_pko_mem_debug6_cn30xx     cn38xx;
 	struct cvmx_pko_mem_debug6_cn30xx     cn38xxp2;
-	struct cvmx_pko_mem_debug6_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug6_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t curr_ptr                     : 11; /**< Internal state */
 #else
@@ -1130,9 +1363,8 @@ union cvmx_pko_mem_debug6
 	uint64_t reserved_11_63               : 53;
 #endif
 	} cn50xx;
-	struct cvmx_pko_mem_debug6_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug6_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_37_63               : 27;
 	uint64_t qid_offres                   : 4;  /**< Internal state */
 	uint64_t qid_offths                   : 4;  /**< Internal state */
@@ -1167,8 +1399,13 @@ union cvmx_pko_mem_debug6
 	struct cvmx_pko_mem_debug6_cn52xx     cn56xxp1;
 	struct cvmx_pko_mem_debug6_cn50xx     cn58xx;
 	struct cvmx_pko_mem_debug6_cn50xx     cn58xxp1;
+	struct cvmx_pko_mem_debug6_cn52xx     cn61xx;
 	struct cvmx_pko_mem_debug6_cn52xx     cn63xx;
 	struct cvmx_pko_mem_debug6_cn52xx     cn63xxp1;
+	struct cvmx_pko_mem_debug6_cn52xx     cn66xx;
+	struct cvmx_pko_mem_debug6_cn52xx     cn68xx;
+	struct cvmx_pko_mem_debug6_cn52xx     cn68xxp1;
+	struct cvmx_pko_mem_debug6_cn52xx     cnf71xx;
 };
 typedef union cvmx_pko_mem_debug6 cvmx_pko_mem_debug6_t;
 
@@ -1180,24 +1417,17 @@ typedef union cvmx_pko_mem_debug6 cvmx_pko_mem_debug6_t;
  * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_pko_mem_debug7
-{
+union cvmx_pko_mem_debug7 {
 	uint64_t u64;
-	struct cvmx_pko_mem_debug7_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t qos                          : 5;  /**< QOS mask to enable the queue when set */
-	uint64_t tail                         : 1;  /**< This queue is the last (tail) in the queue array */
-	uint64_t reserved_0_57                : 58;
+	struct cvmx_pko_mem_debug7_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_0_63                : 64;
 #else
-	uint64_t reserved_0_57                : 58;
-	uint64_t tail                         : 1;
-	uint64_t qos                          : 5;
+	uint64_t reserved_0_63                : 64;
 #endif
 	} s;
-	struct cvmx_pko_mem_debug7_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug7_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_58_63               : 6;
 	uint64_t dwb                          : 9;  /**< Calculated DWB count used for free operation */
 	uint64_t start                        : 33; /**< Calculated start address used for free operation */
@@ -1212,9 +1442,8 @@ union cvmx_pko_mem_debug7
 	struct cvmx_pko_mem_debug7_cn30xx     cn31xx;
 	struct cvmx_pko_mem_debug7_cn30xx     cn38xx;
 	struct cvmx_pko_mem_debug7_cn30xx     cn38xxp2;
-	struct cvmx_pko_mem_debug7_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug7_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t qos                          : 5;  /**< QOS mask to enable the queue when set */
 	uint64_t tail                         : 1;  /**< This queue is the last (tail) in the queue array */
 	uint64_t buf_siz                      : 13; /**< Command buffer remaining size in words */
@@ -1236,8 +1465,29 @@ union cvmx_pko_mem_debug7
 	struct cvmx_pko_mem_debug7_cn50xx     cn56xxp1;
 	struct cvmx_pko_mem_debug7_cn50xx     cn58xx;
 	struct cvmx_pko_mem_debug7_cn50xx     cn58xxp1;
+	struct cvmx_pko_mem_debug7_cn50xx     cn61xx;
 	struct cvmx_pko_mem_debug7_cn50xx     cn63xx;
 	struct cvmx_pko_mem_debug7_cn50xx     cn63xxp1;
+	struct cvmx_pko_mem_debug7_cn50xx     cn66xx;
+	struct cvmx_pko_mem_debug7_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t qos                          : 3;  /**< QOS mask to enable the queue when set */
+	uint64_t tail                         : 1;  /**< This queue is the last (tail) in the queue array */
+	uint64_t buf_siz                      : 13; /**< Command buffer remaining size in words */
+	uint64_t buf_ptr                      : 33; /**< Command word pointer */
+	uint64_t qcb_widx                     : 7;  /**< Buffer write index for QCB */
+	uint64_t qcb_ridx                     : 7;  /**< Buffer read  index for QCB */
+#else
+	uint64_t qcb_ridx                     : 7;
+	uint64_t qcb_widx                     : 7;
+	uint64_t buf_ptr                      : 33;
+	uint64_t buf_siz                      : 13;
+	uint64_t tail                         : 1;
+	uint64_t qos                          : 3;
+#endif
+	} cn68xx;
+	struct cvmx_pko_mem_debug7_cn68xx     cn68xxp1;
+	struct cvmx_pko_mem_debug7_cn50xx     cnf71xx;
 };
 typedef union cvmx_pko_mem_debug7 cvmx_pko_mem_debug7_t;
 
@@ -1249,12 +1499,10 @@ typedef union cvmx_pko_mem_debug7 cvmx_pko_mem_debug7_t;
  * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_pko_mem_debug8
-{
+union cvmx_pko_mem_debug8 {
 	uint64_t u64;
-	struct cvmx_pko_mem_debug8_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug8_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_59_63               : 5;
 	uint64_t tail                         : 1;  /**< This queue is the last (tail) in the queue array */
 	uint64_t buf_siz                      : 13; /**< Command buffer remaining size in words */
@@ -1266,9 +1514,8 @@ union cvmx_pko_mem_debug8
 	uint64_t reserved_59_63               : 5;
 #endif
 	} s;
-	struct cvmx_pko_mem_debug8_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug8_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t qos                          : 5;  /**< QOS mask to enable the queue when set */
 	uint64_t tail                         : 1;  /**< This queue is the last (tail) in the queue array */
 	uint64_t buf_siz                      : 13; /**< Command buffer remaining size in words */
@@ -1287,9 +1534,8 @@ union cvmx_pko_mem_debug8
 	struct cvmx_pko_mem_debug8_cn30xx     cn31xx;
 	struct cvmx_pko_mem_debug8_cn30xx     cn38xx;
 	struct cvmx_pko_mem_debug8_cn30xx     cn38xxp2;
-	struct cvmx_pko_mem_debug8_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug8_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t doorbell                     : 20; /**< Doorbell count */
 	uint64_t reserved_6_7                 : 2;
@@ -1307,9 +1553,8 @@ union cvmx_pko_mem_debug8
 	uint64_t reserved_28_63               : 36;
 #endif
 	} cn50xx;
-	struct cvmx_pko_mem_debug8_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug8_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t preempter                    : 1;  /**< Preempter */
 	uint64_t doorbell                     : 20; /**< Doorbell count */
@@ -1336,8 +1581,63 @@ union cvmx_pko_mem_debug8
 	struct cvmx_pko_mem_debug8_cn52xx     cn56xxp1;
 	struct cvmx_pko_mem_debug8_cn50xx     cn58xx;
 	struct cvmx_pko_mem_debug8_cn50xx     cn58xxp1;
+	struct cvmx_pko_mem_debug8_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_42_63               : 22;
+	uint64_t qid_qqos                     : 8;  /**< QOS_MASK */
+	uint64_t reserved_33_33               : 1;
+	uint64_t qid_idx                      : 4;  /**< IDX */
+	uint64_t preempter                    : 1;  /**< Preempter */
+	uint64_t doorbell                     : 20; /**< Doorbell count */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t preemptee                    : 1;  /**< Preemptee */
+	uint64_t static_p                     : 1;  /**< Static priority */
+	uint64_t s_tail                       : 1;  /**< Static tail */
+	uint64_t static_q                     : 1;  /**< Static priority */
+	uint64_t qos                          : 3;  /**< QOS mask to enable the queue when set */
+#else
+	uint64_t qos                          : 3;
+	uint64_t static_q                     : 1;
+	uint64_t s_tail                       : 1;
+	uint64_t static_p                     : 1;
+	uint64_t preemptee                    : 1;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t doorbell                     : 20;
+	uint64_t preempter                    : 1;
+	uint64_t qid_idx                      : 4;
+	uint64_t reserved_33_33               : 1;
+	uint64_t qid_qqos                     : 8;
+	uint64_t reserved_42_63               : 22;
+#endif
+	} cn61xx;
 	struct cvmx_pko_mem_debug8_cn52xx     cn63xx;
 	struct cvmx_pko_mem_debug8_cn52xx     cn63xxp1;
+	struct cvmx_pko_mem_debug8_cn61xx     cn66xx;
+	struct cvmx_pko_mem_debug8_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_37_63               : 27;
+	uint64_t preempter                    : 1;  /**< Preempter */
+	uint64_t doorbell                     : 20; /**< Doorbell count */
+	uint64_t reserved_9_15                : 7;
+	uint64_t preemptee                    : 1;  /**< Preemptee */
+	uint64_t static_p                     : 1;  /**< Static priority */
+	uint64_t s_tail                       : 1;  /**< Static tail */
+	uint64_t static_q                     : 1;  /**< Static priority */
+	uint64_t qos                          : 5;  /**< QOS mask to enable the queue when set */
+#else
+	uint64_t qos                          : 5;
+	uint64_t static_q                     : 1;
+	uint64_t s_tail                       : 1;
+	uint64_t static_p                     : 1;
+	uint64_t preemptee                    : 1;
+	uint64_t reserved_9_15                : 7;
+	uint64_t doorbell                     : 20;
+	uint64_t preempter                    : 1;
+	uint64_t reserved_37_63               : 27;
+#endif
+	} cn68xx;
+	struct cvmx_pko_mem_debug8_cn68xx     cn68xxp1;
+	struct cvmx_pko_mem_debug8_cn61xx     cnf71xx;
 };
 typedef union cvmx_pko_mem_debug8 cvmx_pko_mem_debug8_t;
 
@@ -1349,12 +1649,10 @@ typedef union cvmx_pko_mem_debug8 cvmx_pko_mem_debug8_t;
  * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_pko_mem_debug9
-{
+union cvmx_pko_mem_debug9 {
 	uint64_t u64;
-	struct cvmx_pko_mem_debug9_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug9_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_49_63               : 15;
 	uint64_t ptrs0                        : 17; /**< Internal state */
 	uint64_t reserved_0_31                : 32;
@@ -1364,9 +1662,8 @@ union cvmx_pko_mem_debug9
 	uint64_t reserved_49_63               : 15;
 #endif
 	} s;
-	struct cvmx_pko_mem_debug9_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug9_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t doorbell                     : 20; /**< Doorbell count */
 	uint64_t reserved_5_7                 : 3;
@@ -1383,9 +1680,8 @@ union cvmx_pko_mem_debug9
 #endif
 	} cn30xx;
 	struct cvmx_pko_mem_debug9_cn30xx     cn31xx;
-	struct cvmx_pko_mem_debug9_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug9_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t doorbell                     : 20; /**< Doorbell count */
 	uint64_t reserved_6_7                 : 2;
@@ -1404,9 +1700,8 @@ union cvmx_pko_mem_debug9
 #endif
 	} cn38xx;
 	struct cvmx_pko_mem_debug9_cn38xx     cn38xxp2;
-	struct cvmx_pko_mem_debug9_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_debug9_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_49_63               : 15;
 	uint64_t ptrs0                        : 17; /**< Internal state */
 	uint64_t reserved_17_31               : 15;
@@ -1424,12 +1719,224 @@ union cvmx_pko_mem_debug9
 	struct cvmx_pko_mem_debug9_cn50xx     cn56xxp1;
 	struct cvmx_pko_mem_debug9_cn50xx     cn58xx;
 	struct cvmx_pko_mem_debug9_cn50xx     cn58xxp1;
+	struct cvmx_pko_mem_debug9_cn50xx     cn61xx;
 	struct cvmx_pko_mem_debug9_cn50xx     cn63xx;
 	struct cvmx_pko_mem_debug9_cn50xx     cn63xxp1;
+	struct cvmx_pko_mem_debug9_cn50xx     cn66xx;
+	struct cvmx_pko_mem_debug9_cn50xx     cn68xx;
+	struct cvmx_pko_mem_debug9_cn50xx     cn68xxp1;
+	struct cvmx_pko_mem_debug9_cn50xx     cnf71xx;
 };
 typedef union cvmx_pko_mem_debug9 cvmx_pko_mem_debug9_t;
 
 /**
+ * cvmx_pko_mem_iport_ptrs
+ *
+ * Notes:
+ * This CSR is a memory of 128 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  The index to this CSR is an IPORT.  A read of any
+ * entry that has not been previously written is illegal and will result in unpredictable CSR read data.
+ */
+union cvmx_pko_mem_iport_ptrs {
+	uint64_t u64;
+	struct cvmx_pko_mem_iport_ptrs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_63_63               : 1;
+	uint64_t crc                          : 1;  /**< Set if this IPID uses CRC */
+	uint64_t static_p                     : 1;  /**< Set if this IPID has static priority */
+	uint64_t qos_mask                     : 8;  /**< Mask to control priority across 8 QOS rounds */
+	uint64_t min_pkt                      : 3;  /**< Min packet size specified by PKO_REG_MIN_PKT[MIN_PKT] */
+	uint64_t reserved_31_49               : 19;
+	uint64_t pipe                         : 7;  /**< The PKO pipe or loopback port
+                                                         When INT != PIP/IPD:
+                                                          PIPE is the PKO pipe to which this port is mapped
+                                                          All used PKO-internal ports that map to the same
+                                                          PIPE must also map to the same INT and EID in
+                                                          this case.
+                                                         When INT == PIP/IPD:
+                                                          PIPE must be in the range
+                                                                  0..PKO_REG_LOOPBACK[NUM_PORTS]-1
+                                                          in this case and selects one of the loopback
+                                                          ports. */
+	uint64_t reserved_21_23               : 3;
+	uint64_t intr                         : 5;  /**< The interface to which this port is mapped
+                                                         All used PKO-internal ports that map to the same EID
+                                                         must also map to the same INT. All used PKO-internal
+                                                         ports that map to the same INT must also map to the
+                                                         same EID.
+                                                         Encoding:
+                                                           0 = GMX0 XAUI/DXAUI/RXAUI0 or SGMII0
+                                                           1 = GMX0 SGMII1
+                                                           2 = GMX0 SGMII2
+                                                           3 = GMX0 SGMII3
+                                                           4 = GMX1 RXAUI
+                                                           8 = GMX2 XAUI/DXAUI or SGMII0
+                                                           9 = GMX2 SGMII1
+                                                          10 = GMX2 SGMII2
+                                                          11 = GMX2 SGMII3
+                                                          12 = GMX3 XAUI/DXAUI or SGMII0
+                                                          13 = GMX3 SGMII1
+                                                          14 = GMX3 SGMII2
+                                                          15 = GMX3 SGMII3
+                                                          16 = GMX4 XAUI/DXAUI or SGMII0
+                                                          17 = GMX4 SGMII1
+                                                          18 = GMX4 SGMII2
+                                                          19 = GMX4 SGMII3
+                                                          28 = ILK interface 0
+                                                          29 = ILK interface 1
+                                                          30 = DPI
+                                                          31 = PIP/IPD
+                                                          others = reserved */
+	uint64_t reserved_13_15               : 3;
+	uint64_t eid                          : 5;  /**< Engine ID to which this port is mapped
+                                                         EID==31 can be used with unused PKO-internal ports.
+                                                         Otherwise, 0-19 are legal EID values. */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t ipid                         : 7;  /**< PKO-internal Port ID to be accessed */
+#else
+	uint64_t ipid                         : 7;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t eid                          : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t intr                         : 5;
+	uint64_t reserved_21_23               : 3;
+	uint64_t pipe                         : 7;
+	uint64_t reserved_31_49               : 19;
+	uint64_t min_pkt                      : 3;
+	uint64_t qos_mask                     : 8;
+	uint64_t static_p                     : 1;
+	uint64_t crc                          : 1;
+	uint64_t reserved_63_63               : 1;
+#endif
+	} s;
+	struct cvmx_pko_mem_iport_ptrs_s      cn68xx;
+	struct cvmx_pko_mem_iport_ptrs_s      cn68xxp1;
+};
+typedef union cvmx_pko_mem_iport_ptrs cvmx_pko_mem_iport_ptrs_t;
+
+/**
+ * cvmx_pko_mem_iport_qos
+ *
+ * Notes:
+ * Sets the QOS mask, per port.  These QOS_MASK bits are logically and physically the same QOS_MASK
+ * bits in PKO_MEM_IPORT_PTRS.  This CSR address allows the QOS_MASK bits to be written during PKO
+ * operation without affecting any other port state.  The engine to which port PID is mapped is engine
+ * EID.  Note that the port to engine mapping must be the same as was previously programmed via the
+ * PKO_MEM_IPORT_PTRS CSR.
+ * This CSR is a memory of 128 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  The index to this CSR is an IPORT.  A read of
+ * any entry that has not been previously written is illegal and will result in unpredictable CSR read data.
+ */
+union cvmx_pko_mem_iport_qos {
+	uint64_t u64;
+	struct cvmx_pko_mem_iport_qos_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_61_63               : 3;
+	uint64_t qos_mask                     : 8;  /**< Mask to control priority across 8 QOS rounds */
+	uint64_t reserved_13_52               : 40;
+	uint64_t eid                          : 5;  /**< Engine ID to which this port is mapped */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t ipid                         : 7;  /**< PKO-internal Port ID */
+#else
+	uint64_t ipid                         : 7;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t eid                          : 5;
+	uint64_t reserved_13_52               : 40;
+	uint64_t qos_mask                     : 8;
+	uint64_t reserved_61_63               : 3;
+#endif
+	} s;
+	struct cvmx_pko_mem_iport_qos_s       cn68xx;
+	struct cvmx_pko_mem_iport_qos_s       cn68xxp1;
+};
+typedef union cvmx_pko_mem_iport_qos cvmx_pko_mem_iport_qos_t;
+
+/**
+ * cvmx_pko_mem_iqueue_ptrs
+ *
+ * Notes:
+ * Sets the queue to port mapping and the initial command buffer pointer, per queue.  Unused queues must
+ * set BUF_PTR=0.  Each queue may map to at most one port.  No more than 32 queues may map to a port.
+ * The set of queues that is mapped to a port must be a contiguous array of queues.  The port to which
+ * queue QID is mapped is port IPID.  The index of queue QID in port IPID's queue list is IDX.  The last
+ * queue in port IPID's queue array must have its TAIL bit set.
+ * STATIC_Q marks queue QID as having static priority.  STATIC_P marks the port IPID to which QID is
+ * mapped as having at least one queue with static priority.  If any QID that maps to IPID has static
+ * priority, then all QID that map to IPID must have STATIC_P set.  Queues marked as static priority
+ * must be contiguous and begin at IDX 0.  The last queue that is marked as having static priority
+ * must have its S_TAIL bit set.
+ * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  The index to this CSR is an IQUEUE.  A read of any
+ * entry that has not been previously written is illegal and will result in unpredictable CSR read data.
+ */
+union cvmx_pko_mem_iqueue_ptrs {
+	uint64_t u64;
+	struct cvmx_pko_mem_iqueue_ptrs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t s_tail                       : 1;  /**< Set if this QID is the tail of the static queues */
+	uint64_t static_p                     : 1;  /**< Set if any QID in this IPID has static priority */
+	uint64_t static_q                     : 1;  /**< Set if this QID has static priority */
+	uint64_t qos_mask                     : 8;  /**< Mask to control priority across 8 QOS rounds */
+	uint64_t buf_ptr                      : 31; /**< Command buffer pointer[37:7] */
+	uint64_t tail                         : 1;  /**< Set if this QID is the tail of the queue array */
+	uint64_t index                        : 5;  /**< Index (distance from head) in the queue array */
+	uint64_t reserved_15_15               : 1;
+	uint64_t ipid                         : 7;  /**< PKO-Internal Port ID to which this queue is mapped */
+	uint64_t qid                          : 8;  /**< Queue ID */
+#else
+	uint64_t qid                          : 8;
+	uint64_t ipid                         : 7;
+	uint64_t reserved_15_15               : 1;
+	uint64_t index                        : 5;
+	uint64_t tail                         : 1;
+	uint64_t buf_ptr                      : 31;
+	uint64_t qos_mask                     : 8;
+	uint64_t static_q                     : 1;
+	uint64_t static_p                     : 1;
+	uint64_t s_tail                       : 1;
+#endif
+	} s;
+	struct cvmx_pko_mem_iqueue_ptrs_s     cn68xx;
+	struct cvmx_pko_mem_iqueue_ptrs_s     cn68xxp1;
+};
+typedef union cvmx_pko_mem_iqueue_ptrs cvmx_pko_mem_iqueue_ptrs_t;
+
+/**
+ * cvmx_pko_mem_iqueue_qos
+ *
+ * Notes:
+ * Sets the QOS mask, per queue.  These QOS_MASK bits are logically and physically the same QOS_MASK
+ * bits in PKO_MEM_IQUEUE_PTRS.  This CSR address allows the QOS_MASK bits to be written during PKO
+ * operation without affecting any other queue state.  The port to which queue QID is mapped is port
+ * IPID.  Note that the queue to port mapping must be the same as was previously programmed via the
+ * PKO_MEM_IQUEUE_PTRS CSR.
+ * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  The index to this CSR is an IQUEUE.  A read of any
+ * entry that has not been previously written is illegal and will result in unpredictable CSR read data.
+ */
+union cvmx_pko_mem_iqueue_qos {
+	uint64_t u64;
+	struct cvmx_pko_mem_iqueue_qos_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_61_63               : 3;
+	uint64_t qos_mask                     : 8;  /**< Mask to control priority across 8 QOS rounds */
+	uint64_t reserved_15_52               : 38;
+	uint64_t ipid                         : 7;  /**< PKO-Internal Port ID to which this queue is mapped */
+	uint64_t qid                          : 8;  /**< Queue ID */
+#else
+	uint64_t qid                          : 8;
+	uint64_t ipid                         : 7;
+	uint64_t reserved_15_52               : 38;
+	uint64_t qos_mask                     : 8;
+	uint64_t reserved_61_63               : 3;
+#endif
+	} s;
+	struct cvmx_pko_mem_iqueue_qos_s      cn68xx;
+	struct cvmx_pko_mem_iqueue_qos_s      cn68xxp1;
+};
+typedef union cvmx_pko_mem_iqueue_qos cvmx_pko_mem_iqueue_qos_t;
+
+/**
  * cvmx_pko_mem_port_ptrs
  *
  * Notes:
@@ -1439,6 +1946,8 @@ typedef union cvmx_pko_mem_debug9 cvmx_pko_mem_debug9_t;
  * EID==15 can be used for unused PKO-internal ports.
  * BP_PORT==63 means that the PKO-internal port is not backpressured.
  * BP_PORTs are assumed to belong to an interface as follows:
+ *   46 <= BP_PORT < 48 -> srio       interface 3
+ *   44 <= BP_PORT < 46 -> srio       interface 2
  *   42 <= BP_PORT < 44 -> srio       interface 1
  *   40 <= BP_PORT < 42 -> srio       interface 0
  *   36 <= BP_PORT < 40 -> loopback   interface
@@ -1446,7 +1955,7 @@ typedef union cvmx_pko_mem_debug9 cvmx_pko_mem_debug9_t;
  *   0  <= BP_PORT < 16 -> SGMII/Xaui interface 0
  *
  * Note that the SRIO interfaces do not actually provide backpressure.  Thus, ports that use
- * 40 <= BP_PORT < 44 for backpressure will never be backpressured.
+ * 40 <= BP_PORT < 48 for backpressure will never be backpressured.
  *
  * The reset configuration is the following:
  *   PID EID(ext port) BP_PORT QOS_MASK STATIC_P
@@ -1468,22 +1977,22 @@ typedef union cvmx_pko_mem_debug9 cvmx_pko_mem_debug9_t;
  *    14   2( 2)            14     0xff        0
  *    15   3( 3)            15     0xff        0
  *   -------------------------------------------
- *    16   0( 0)             0     0xff        0
- *    17   1( 1)             1     0xff        0
- *    18   2( 2)             2     0xff        0
- *    19   3( 3)             3     0xff        0
- *    20   0( 0)             4     0xff        0
- *    21   1( 1)             5     0xff        0
- *    22   2( 2)             6     0xff        0
- *    23   3( 3)             7     0xff        0
- *    24   0( 0)             8     0xff        0
- *    25   1( 1)             9     0xff        0
- *    26   2( 2)            10     0xff        0
- *    27   3( 3)            11     0xff        0
- *    28   0( 0)            12     0xff        0
- *    29   1( 1)            13     0xff        0
- *    30   2( 2)            14     0xff        0
- *    31   3( 3)            15     0xff        0
+ *    16   4(16)            16     0xff        0
+ *    17   5(17)            17     0xff        0
+ *    18   6(18)            18     0xff        0
+ *    19   7(19)            19     0xff        0
+ *    20   4(16)            20     0xff        0
+ *    21   5(17)            21     0xff        0
+ *    22   6(18)            22     0xff        0
+ *    23   7(19)            23     0xff        0
+ *    24   4(16)            24     0xff        0
+ *    25   5(17)            25     0xff        0
+ *    26   6(18)            26     0xff        0
+ *    27   7(19)            27     0xff        0
+ *    28   4(16)            28     0xff        0
+ *    29   5(17)            29     0xff        0
+ *    30   6(18)            30     0xff        0
+ *    31   7(19)            31     0xff        0
  *   -------------------------------------------
  *    32   8(32)            32     0xff        0
  *    33   8(33)            33     0xff        0
@@ -1494,31 +2003,23 @@ typedef union cvmx_pko_mem_debug9 cvmx_pko_mem_debug9_t;
  *    37   9(37)            37     0xff        0
  *    38   9(38)            38     0xff        0
  *    39   9(39)            39     0xff        0
- *   -------------------------------------------
- *    40  10(40)            40     0xff        0
- *    41  10(41)            41     0xff        0
- *   -------------------------------------------
- *    42  11(42)            42     0xff        0
- *    43  11(43)            43     0xff        0
  *
- * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * This CSR is a memory of 48 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.  A read of any entry that has not been
  * previously written is illegal and will result in unpredictable CSR read data.
  */
-union cvmx_pko_mem_port_ptrs
-{
+union cvmx_pko_mem_port_ptrs {
 	uint64_t u64;
-	struct cvmx_pko_mem_port_ptrs_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_port_ptrs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_62_63               : 2;
 	uint64_t static_p                     : 1;  /**< Set if this PID has static priority */
 	uint64_t qos_mask                     : 8;  /**< Mask to control priority across 8 QOS rounds */
 	uint64_t reserved_16_52               : 37;
 	uint64_t bp_port                      : 6;  /**< PID listens to BP_PORT for per-packet backpressure
-                                                         Legal BP_PORTs: 0-15, 32-43, 63 (63 means no BP) */
+                                                         Legal BP_PORTs: 0-15, 32-47, 63 (63 means no BP) */
 	uint64_t eid                          : 4;  /**< Engine ID to which this port is mapped
-                                                         Legal EIDs: 0-3, 8-11, 15 (15 only if port not used) */
+                                                         Legal EIDs: 0-3, 8-13, 15 (15 only if port not used) */
 	uint64_t pid                          : 6;  /**< Port ID[5:0] */
 #else
 	uint64_t pid                          : 6;
@@ -1534,8 +2035,11 @@ union cvmx_pko_mem_port_ptrs
 	struct cvmx_pko_mem_port_ptrs_s       cn52xxp1;
 	struct cvmx_pko_mem_port_ptrs_s       cn56xx;
 	struct cvmx_pko_mem_port_ptrs_s       cn56xxp1;
+	struct cvmx_pko_mem_port_ptrs_s       cn61xx;
 	struct cvmx_pko_mem_port_ptrs_s       cn63xx;
 	struct cvmx_pko_mem_port_ptrs_s       cn63xxp1;
+	struct cvmx_pko_mem_port_ptrs_s       cn66xx;
+	struct cvmx_pko_mem_port_ptrs_s       cnf71xx;
 };
 typedef union cvmx_pko_mem_port_ptrs cvmx_pko_mem_port_ptrs_t;
 
@@ -1552,12 +2056,10 @@ typedef union cvmx_pko_mem_port_ptrs cvmx_pko_mem_port_ptrs_t;
  * CSR read operations to this address can be performed.  A read of any entry that has not been
  * previously written is illegal and will result in unpredictable CSR read data.
  */
-union cvmx_pko_mem_port_qos
-{
+union cvmx_pko_mem_port_qos {
 	uint64_t u64;
-	struct cvmx_pko_mem_port_qos_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_port_qos_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_61_63               : 3;
 	uint64_t qos_mask                     : 8;  /**< Mask to control priority across 8 QOS rounds */
 	uint64_t reserved_10_52               : 43;
@@ -1576,8 +2078,11 @@ union cvmx_pko_mem_port_qos
 	struct cvmx_pko_mem_port_qos_s        cn52xxp1;
 	struct cvmx_pko_mem_port_qos_s        cn56xx;
 	struct cvmx_pko_mem_port_qos_s        cn56xxp1;
+	struct cvmx_pko_mem_port_qos_s        cn61xx;
 	struct cvmx_pko_mem_port_qos_s        cn63xx;
 	struct cvmx_pko_mem_port_qos_s        cn63xxp1;
+	struct cvmx_pko_mem_port_qos_s        cn66xx;
+	struct cvmx_pko_mem_port_qos_s        cnf71xx;
 };
 typedef union cvmx_pko_mem_port_qos cvmx_pko_mem_port_qos_t;
 
@@ -1589,12 +2094,25 @@ typedef union cvmx_pko_mem_port_qos cvmx_pko_mem_port_qos_t;
  * CSR read operations to this address can be performed.  A read of any entry that has not been
  * previously written is illegal and will result in unpredictable CSR read data.
  */
-union cvmx_pko_mem_port_rate0
-{
+union cvmx_pko_mem_port_rate0 {
 	uint64_t u64;
-	struct cvmx_pko_mem_port_rate0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_port_rate0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_51_63               : 13;
+	uint64_t rate_word                    : 19; /**< Rate limiting adder per 8 byte */
+	uint64_t rate_pkt                     : 24; /**< Rate limiting adder per packet */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t pid                          : 7;  /**< Port ID[5:0] */
+#else
+	uint64_t pid                          : 7;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t rate_pkt                     : 24;
+	uint64_t rate_word                    : 19;
+	uint64_t reserved_51_63               : 13;
+#endif
+	} s;
+	struct cvmx_pko_mem_port_rate0_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_51_63               : 13;
 	uint64_t rate_word                    : 19; /**< Rate limiting adder per 8 byte */
 	uint64_t rate_pkt                     : 24; /**< Rate limiting adder per packet */
@@ -1607,13 +2125,17 @@ union cvmx_pko_mem_port_rate0
 	uint64_t rate_word                    : 19;
 	uint64_t reserved_51_63               : 13;
 #endif
-	} s;
-	struct cvmx_pko_mem_port_rate0_s      cn52xx;
-	struct cvmx_pko_mem_port_rate0_s      cn52xxp1;
-	struct cvmx_pko_mem_port_rate0_s      cn56xx;
-	struct cvmx_pko_mem_port_rate0_s      cn56xxp1;
-	struct cvmx_pko_mem_port_rate0_s      cn63xx;
-	struct cvmx_pko_mem_port_rate0_s      cn63xxp1;
+	} cn52xx;
+	struct cvmx_pko_mem_port_rate0_cn52xx cn52xxp1;
+	struct cvmx_pko_mem_port_rate0_cn52xx cn56xx;
+	struct cvmx_pko_mem_port_rate0_cn52xx cn56xxp1;
+	struct cvmx_pko_mem_port_rate0_cn52xx cn61xx;
+	struct cvmx_pko_mem_port_rate0_cn52xx cn63xx;
+	struct cvmx_pko_mem_port_rate0_cn52xx cn63xxp1;
+	struct cvmx_pko_mem_port_rate0_cn52xx cn66xx;
+	struct cvmx_pko_mem_port_rate0_s      cn68xx;
+	struct cvmx_pko_mem_port_rate0_s      cn68xxp1;
+	struct cvmx_pko_mem_port_rate0_cn52xx cnf71xx;
 };
 typedef union cvmx_pko_mem_port_rate0 cvmx_pko_mem_port_rate0_t;
 
@@ -1627,12 +2149,23 @@ typedef union cvmx_pko_mem_port_rate0 cvmx_pko_mem_port_rate0_t;
  * CSR read operations to this address can be performed.  A read of any entry that has not been
  * previously written is illegal and will result in unpredictable CSR read data.
  */
-union cvmx_pko_mem_port_rate1
-{
+union cvmx_pko_mem_port_rate1 {
 	uint64_t u64;
-	struct cvmx_pko_mem_port_rate1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_port_rate1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t rate_lim                     : 24; /**< Rate limiting accumulator limit */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t pid                          : 7;  /**< Port ID[5:0] */
+#else
+	uint64_t pid                          : 7;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t rate_lim                     : 24;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pko_mem_port_rate1_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t rate_lim                     : 24; /**< Rate limiting accumulator limit */
 	uint64_t reserved_6_7                 : 2;
@@ -1643,13 +2176,17 @@ union cvmx_pko_mem_port_rate1
 	uint64_t rate_lim                     : 24;
 	uint64_t reserved_32_63               : 32;
 #endif
-	} s;
-	struct cvmx_pko_mem_port_rate1_s      cn52xx;
-	struct cvmx_pko_mem_port_rate1_s      cn52xxp1;
-	struct cvmx_pko_mem_port_rate1_s      cn56xx;
-	struct cvmx_pko_mem_port_rate1_s      cn56xxp1;
-	struct cvmx_pko_mem_port_rate1_s      cn63xx;
-	struct cvmx_pko_mem_port_rate1_s      cn63xxp1;
+	} cn52xx;
+	struct cvmx_pko_mem_port_rate1_cn52xx cn52xxp1;
+	struct cvmx_pko_mem_port_rate1_cn52xx cn56xx;
+	struct cvmx_pko_mem_port_rate1_cn52xx cn56xxp1;
+	struct cvmx_pko_mem_port_rate1_cn52xx cn61xx;
+	struct cvmx_pko_mem_port_rate1_cn52xx cn63xx;
+	struct cvmx_pko_mem_port_rate1_cn52xx cn63xxp1;
+	struct cvmx_pko_mem_port_rate1_cn52xx cn66xx;
+	struct cvmx_pko_mem_port_rate1_s      cn68xx;
+	struct cvmx_pko_mem_port_rate1_s      cn68xxp1;
+	struct cvmx_pko_mem_port_rate1_cn52xx cnf71xx;
 };
 typedef union cvmx_pko_mem_port_rate1 cvmx_pko_mem_port_rate1_t;
 
@@ -1671,12 +2208,10 @@ typedef union cvmx_pko_mem_port_rate1 cvmx_pko_mem_port_rate1_t;
  * CSR read operations to this address can be performed.  A read of any entry that has not been
  * previously written is illegal and will result in unpredictable CSR read data.
  */
-union cvmx_pko_mem_queue_ptrs
-{
+union cvmx_pko_mem_queue_ptrs {
 	uint64_t u64;
-	struct cvmx_pko_mem_queue_ptrs_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_queue_ptrs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t s_tail                       : 1;  /**< Set if this QID is the tail of the static queues */
 	uint64_t static_p                     : 1;  /**< Set if any QID in this PID has static priority */
 	uint64_t static_q                     : 1;  /**< Set if this QID has static priority */
@@ -1709,8 +2244,11 @@ union cvmx_pko_mem_queue_ptrs
 	struct cvmx_pko_mem_queue_ptrs_s      cn56xxp1;
 	struct cvmx_pko_mem_queue_ptrs_s      cn58xx;
 	struct cvmx_pko_mem_queue_ptrs_s      cn58xxp1;
+	struct cvmx_pko_mem_queue_ptrs_s      cn61xx;
 	struct cvmx_pko_mem_queue_ptrs_s      cn63xx;
 	struct cvmx_pko_mem_queue_ptrs_s      cn63xxp1;
+	struct cvmx_pko_mem_queue_ptrs_s      cn66xx;
+	struct cvmx_pko_mem_queue_ptrs_s      cnf71xx;
 };
 typedef union cvmx_pko_mem_queue_ptrs cvmx_pko_mem_queue_ptrs_t;
 
@@ -1727,12 +2265,10 @@ typedef union cvmx_pko_mem_queue_ptrs cvmx_pko_mem_queue_ptrs_t;
  * CSR read operations to this address can be performed.  A read of any entry that has not been
  * previously written is illegal and will result in unpredictable CSR read data.
  */
-union cvmx_pko_mem_queue_qos
-{
+union cvmx_pko_mem_queue_qos {
 	uint64_t u64;
-	struct cvmx_pko_mem_queue_qos_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_mem_queue_qos_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_61_63               : 3;
 	uint64_t qos_mask                     : 8;  /**< Mask to control priority across 8 QOS rounds */
 	uint64_t reserved_13_52               : 40;
@@ -1757,32 +2293,137 @@ union cvmx_pko_mem_queue_qos
 	struct cvmx_pko_mem_queue_qos_s       cn56xxp1;
 	struct cvmx_pko_mem_queue_qos_s       cn58xx;
 	struct cvmx_pko_mem_queue_qos_s       cn58xxp1;
+	struct cvmx_pko_mem_queue_qos_s       cn61xx;
 	struct cvmx_pko_mem_queue_qos_s       cn63xx;
 	struct cvmx_pko_mem_queue_qos_s       cn63xxp1;
+	struct cvmx_pko_mem_queue_qos_s       cn66xx;
+	struct cvmx_pko_mem_queue_qos_s       cnf71xx;
 };
 typedef union cvmx_pko_mem_queue_qos cvmx_pko_mem_queue_qos_t;
 
 /**
+ * cvmx_pko_mem_throttle_int
+ *
+ * Notes:
+ * Writing PACKET and WORD with 0 resets both counts for INT to 0 rather than add 0.
+ * Otherwise, writes to this CSR add to the existing WORD/PACKET counts for the interface INT.
+ *
+ * PKO tracks the number of (8-byte) WORD's and PACKET's in-flight (sum total in both PKO
+ * and the interface MAC) on the interface. (When PKO first selects a packet from a PKO queue, it
+ * increments the counts appropriately. When the interface MAC has (largely) completed sending
+ * the words/packet, PKO decrements the count appropriately.) When PKO_REG_FLAGS[ENA_THROTTLE]
+ * is set and the most-significant bit of the WORD or packet count for a interface is set,
+ * PKO will not transfer any packets over the interface. Software can limit the amount of
+ * packet data and/or the number of packets that OCTEON can send out the chip after receiving backpressure
+ * from the interface/pipe via these per-pipe throttle counts when PKO_REG_FLAGS[ENA_THROTTLE]=1.
+ * For example, to limit the number of packets outstanding in the interface to N, preset PACKET for
+ * the pipe to the value 0x20-N (0x20 is the smallest PACKET value with the most-significant bit set).
+ *
+ * This CSR is a memory of 32 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  The index to this CSR is an INTERFACE.  A read of any
+ * entry that has not been previously written is illegal and will result in unpredictable CSR read data.
+ */
+union cvmx_pko_mem_throttle_int {
+	uint64_t u64;
+	struct cvmx_pko_mem_throttle_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_47_63               : 17;
+	uint64_t word                         : 15; /**< On a write, the amount to add to the interface
+                                                         throttle word count selected by INT. On a read,
+                                                         returns the current value of the interface throttle
+                                                         word count selected by PKO_REG_READ_IDX[IDX]. */
+	uint64_t reserved_14_31               : 18;
+	uint64_t packet                       : 6;  /**< On a write, the amount to add to the interface
+                                                         throttle packet count selected by INT. On a read,
+                                                         returns the current value of the interface throttle
+                                                         packet count selected by PKO_REG_READ_IDX[IDX]. */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t intr                         : 5;  /**< Selected interface for writes. Undefined on a read.
+                                                         See PKO_MEM_IPORT_PTRS[INT] for encoding. */
+#else
+	uint64_t intr                         : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t packet                       : 6;
+	uint64_t reserved_14_31               : 18;
+	uint64_t word                         : 15;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} s;
+	struct cvmx_pko_mem_throttle_int_s    cn68xx;
+	struct cvmx_pko_mem_throttle_int_s    cn68xxp1;
+};
+typedef union cvmx_pko_mem_throttle_int cvmx_pko_mem_throttle_int_t;
+
+/**
+ * cvmx_pko_mem_throttle_pipe
+ *
+ * Notes:
+ * Writing PACKET and WORD with 0 resets both counts for PIPE to 0 rather than add 0.
+ * Otherwise, writes to this CSR add to the existing WORD/PACKET counts for the PKO pipe PIPE.
+ *
+ * PKO tracks the number of (8-byte) WORD's and PACKET's in-flight (sum total in both PKO
+ * and the interface MAC) on the pipe. (When PKO first selects a packet from a PKO queue, it
+ * increments the counts appropriately. When the interface MAC has (largely) completed sending
+ * the words/packet, PKO decrements the count appropriately.) When PKO_REG_FLAGS[ENA_THROTTLE]
+ * is set and the most-significant bit of the WORD or packet count for a PKO pipe is set,
+ * PKO will not transfer any packets over the PKO pipe. Software can limit the amount of
+ * packet data and/or the number of packets that OCTEON can send out the chip after receiving backpressure
+ * from the interface/pipe via these per-pipe throttle counts when PKO_REG_FLAGS[ENA_THROTTLE]=1.
+ * For example, to limit the number of packets outstanding in the pipe to N, preset PACKET for
+ * the pipe to the value 0x20-N (0x20 is the smallest PACKET value with the most-significant bit set).
+ *
+ * This CSR is a memory of 128 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  The index to this CSR is a PIPE.  A read of any
+ * entry that has not been previously written is illegal and will result in unpredictable CSR read data.
+ */
+union cvmx_pko_mem_throttle_pipe {
+	uint64_t u64;
+	struct cvmx_pko_mem_throttle_pipe_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_47_63               : 17;
+	uint64_t word                         : 15; /**< On a write, the amount to add to the pipe throttle
+                                                         word count selected by PIPE. On a read, returns
+                                                         the current value of the pipe throttle word count
+                                                         selected by PKO_REG_READ_IDX[IDX]. */
+	uint64_t reserved_14_31               : 18;
+	uint64_t packet                       : 6;  /**< On a write, the amount to add to the pipe throttle
+                                                         packet count selected by PIPE. On a read, returns
+                                                         the current value of the pipe throttle packet count
+                                                         selected by PKO_REG_READ_IDX[IDX]. */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t pipe                         : 7;  /**< Selected PKO pipe for writes. Undefined on a read. */
+#else
+	uint64_t pipe                         : 7;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t packet                       : 6;
+	uint64_t reserved_14_31               : 18;
+	uint64_t word                         : 15;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} s;
+	struct cvmx_pko_mem_throttle_pipe_s   cn68xx;
+	struct cvmx_pko_mem_throttle_pipe_s   cn68xxp1;
+};
+typedef union cvmx_pko_mem_throttle_pipe cvmx_pko_mem_throttle_pipe_t;
+
+/**
  * cvmx_pko_reg_bist_result
  *
  * Notes:
  * Access to the internal BiST results
  * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
  */
-union cvmx_pko_reg_bist_result
-{
+union cvmx_pko_reg_bist_result {
 	uint64_t u64;
-	struct cvmx_pko_reg_bist_result_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_bist_result_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_0_63                : 64;
 #else
 	uint64_t reserved_0_63                : 64;
 #endif
 	} s;
-	struct cvmx_pko_reg_bist_result_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_bist_result_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_27_63               : 37;
 	uint64_t psb2                         : 5;  /**< BiST result of the PSB   memories (0=pass, !0=fail) */
 	uint64_t count                        : 1;  /**< BiST result of the COUNT memories (0=pass, !0=fail) */
@@ -1815,9 +2456,8 @@ union cvmx_pko_reg_bist_result
 	struct cvmx_pko_reg_bist_result_cn30xx cn31xx;
 	struct cvmx_pko_reg_bist_result_cn30xx cn38xx;
 	struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2;
-	struct cvmx_pko_reg_bist_result_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_bist_result_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_33_63               : 31;
 	uint64_t csr                          : 1;  /**< BiST result of CSR      memories (0=pass, !0=fail) */
 	uint64_t iob                          : 1;  /**< BiST result of IOB      memories (0=pass, !0=fail) */
@@ -1851,9 +2491,8 @@ union cvmx_pko_reg_bist_result
 	uint64_t reserved_33_63               : 31;
 #endif
 	} cn50xx;
-	struct cvmx_pko_reg_bist_result_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_bist_result_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_35_63               : 29;
 	uint64_t csr                          : 1;  /**< BiST result of CSR      memories (0=pass, !0=fail) */
 	uint64_t iob                          : 1;  /**< BiST result of IOB      memories (0=pass, !0=fail) */
@@ -1894,8 +2533,99 @@ union cvmx_pko_reg_bist_result
 	struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1;
 	struct cvmx_pko_reg_bist_result_cn50xx cn58xx;
 	struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1;
+	struct cvmx_pko_reg_bist_result_cn52xx cn61xx;
 	struct cvmx_pko_reg_bist_result_cn52xx cn63xx;
 	struct cvmx_pko_reg_bist_result_cn52xx cn63xxp1;
+	struct cvmx_pko_reg_bist_result_cn52xx cn66xx;
+	struct cvmx_pko_reg_bist_result_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_36_63               : 28;
+	uint64_t crc                          : 1;  /**< BiST result of CRC      memories (0=pass, !0=fail) */
+	uint64_t csr                          : 1;  /**< BiST result of CSR      memories (0=pass, !0=fail) */
+	uint64_t iob                          : 1;  /**< BiST result of IOB      memories (0=pass, !0=fail) */
+	uint64_t out_dat                      : 1;  /**< BiST result of OUT_DAT  memories (0=pass, !0=fail) */
+	uint64_t reserved_31_31               : 1;
+	uint64_t out_ctl                      : 2;  /**< BiST result of OUT_CTL  memories (0=pass, !0=fail) */
+	uint64_t out_sta                      : 1;  /**< BiST result of OUT_STA  memories (0=pass, !0=fail) */
+	uint64_t out_wif                      : 1;  /**< BiST result of OUT_WIF  memories (0=pass, !0=fail) */
+	uint64_t prt_chk                      : 3;  /**< BiST result of PRT_CHK  memories (0=pass, !0=fail) */
+	uint64_t prt_nxt                      : 1;  /**< BiST result of PRT_NXT  memories (0=pass, !0=fail) */
+	uint64_t prt_psb7                     : 1;  /**< BiST result of PRT_PSB  memories (0=pass, !0=fail) */
+	uint64_t reserved_21_21               : 1;
+	uint64_t prt_psb                      : 6;  /**< BiST result of PRT_PSB  memories (0=pass, !0=fail) */
+	uint64_t ncb_inb                      : 2;  /**< BiST result of NCB_INB  memories (0=pass, !0=fail) */
+	uint64_t prt_qcb                      : 2;  /**< BiST result of PRT_QCB  memories (0=pass, !0=fail) */
+	uint64_t prt_qsb                      : 3;  /**< BiST result of PRT_QSB  memories (0=pass, !0=fail) */
+	uint64_t prt_ctl                      : 2;  /**< BiST result of PRT_CTL  memories (0=pass, !0=fail) */
+	uint64_t dat_dat                      : 2;  /**< BiST result of DAT_DAT  memories (0=pass, !0=fail) */
+	uint64_t dat_ptr                      : 4;  /**< BiST result of DAT_PTR  memories (0=pass, !0=fail) */
+#else
+	uint64_t dat_ptr                      : 4;
+	uint64_t dat_dat                      : 2;
+	uint64_t prt_ctl                      : 2;
+	uint64_t prt_qsb                      : 3;
+	uint64_t prt_qcb                      : 2;
+	uint64_t ncb_inb                      : 2;
+	uint64_t prt_psb                      : 6;
+	uint64_t reserved_21_21               : 1;
+	uint64_t prt_psb7                     : 1;
+	uint64_t prt_nxt                      : 1;
+	uint64_t prt_chk                      : 3;
+	uint64_t out_wif                      : 1;
+	uint64_t out_sta                      : 1;
+	uint64_t out_ctl                      : 2;
+	uint64_t reserved_31_31               : 1;
+	uint64_t out_dat                      : 1;
+	uint64_t iob                          : 1;
+	uint64_t csr                          : 1;
+	uint64_t crc                          : 1;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn68xx;
+	struct cvmx_pko_reg_bist_result_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_35_63               : 29;
+	uint64_t csr                          : 1;  /**< BiST result of CSR      memories (0=pass, !0=fail) */
+	uint64_t iob                          : 1;  /**< BiST result of IOB      memories (0=pass, !0=fail) */
+	uint64_t out_dat                      : 1;  /**< BiST result of OUT_DAT  memories (0=pass, !0=fail) */
+	uint64_t reserved_31_31               : 1;
+	uint64_t out_ctl                      : 2;  /**< BiST result of OUT_CTL  memories (0=pass, !0=fail) */
+	uint64_t out_sta                      : 1;  /**< BiST result of OUT_STA  memories (0=pass, !0=fail) */
+	uint64_t out_wif                      : 1;  /**< BiST result of OUT_WIF  memories (0=pass, !0=fail) */
+	uint64_t prt_chk                      : 3;  /**< BiST result of PRT_CHK  memories (0=pass, !0=fail) */
+	uint64_t prt_nxt                      : 1;  /**< BiST result of PRT_NXT  memories (0=pass, !0=fail) */
+	uint64_t prt_psb7                     : 1;  /**< BiST result of PRT_PSB  memories (0=pass, !0=fail) */
+	uint64_t reserved_21_21               : 1;
+	uint64_t prt_psb                      : 6;  /**< BiST result of PRT_PSB  memories (0=pass, !0=fail) */
+	uint64_t ncb_inb                      : 2;  /**< BiST result of NCB_INB  memories (0=pass, !0=fail) */
+	uint64_t prt_qcb                      : 2;  /**< BiST result of PRT_QCB  memories (0=pass, !0=fail) */
+	uint64_t prt_qsb                      : 3;  /**< BiST result of PRT_QSB  memories (0=pass, !0=fail) */
+	uint64_t prt_ctl                      : 2;  /**< BiST result of PRT_CTL  memories (0=pass, !0=fail) */
+	uint64_t dat_dat                      : 2;  /**< BiST result of DAT_DAT  memories (0=pass, !0=fail) */
+	uint64_t dat_ptr                      : 4;  /**< BiST result of DAT_PTR  memories (0=pass, !0=fail) */
+#else
+	uint64_t dat_ptr                      : 4;
+	uint64_t dat_dat                      : 2;
+	uint64_t prt_ctl                      : 2;
+	uint64_t prt_qsb                      : 3;
+	uint64_t prt_qcb                      : 2;
+	uint64_t ncb_inb                      : 2;
+	uint64_t prt_psb                      : 6;
+	uint64_t reserved_21_21               : 1;
+	uint64_t prt_psb7                     : 1;
+	uint64_t prt_nxt                      : 1;
+	uint64_t prt_chk                      : 3;
+	uint64_t out_wif                      : 1;
+	uint64_t out_sta                      : 1;
+	uint64_t out_ctl                      : 2;
+	uint64_t reserved_31_31               : 1;
+	uint64_t out_dat                      : 1;
+	uint64_t iob                          : 1;
+	uint64_t csr                          : 1;
+	uint64_t reserved_35_63               : 29;
+#endif
+	} cn68xxp1;
+	struct cvmx_pko_reg_bist_result_cn52xx cnf71xx;
 };
 typedef union cvmx_pko_reg_bist_result cvmx_pko_reg_bist_result_t;
 
@@ -1907,12 +2637,10 @@ typedef union cvmx_pko_reg_bist_result cvmx_pko_reg_bist_result_t;
  * The size of the command buffer segments is measured in uint64s.  The pool specifies (1 of 8 free
  * lists to be used when freeing command buffer segments.
  */
-union cvmx_pko_reg_cmd_buf
-{
+union cvmx_pko_reg_cmd_buf {
 	uint64_t u64;
-	struct cvmx_pko_reg_cmd_buf_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_cmd_buf_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_23_63               : 41;
 	uint64_t pool                         : 3;  /**< Free list used to free command buffer segments */
 	uint64_t reserved_13_19               : 7;
@@ -1935,8 +2663,13 @@ union cvmx_pko_reg_cmd_buf
 	struct cvmx_pko_reg_cmd_buf_s         cn56xxp1;
 	struct cvmx_pko_reg_cmd_buf_s         cn58xx;
 	struct cvmx_pko_reg_cmd_buf_s         cn58xxp1;
+	struct cvmx_pko_reg_cmd_buf_s         cn61xx;
 	struct cvmx_pko_reg_cmd_buf_s         cn63xx;
 	struct cvmx_pko_reg_cmd_buf_s         cn63xxp1;
+	struct cvmx_pko_reg_cmd_buf_s         cn66xx;
+	struct cvmx_pko_reg_cmd_buf_s         cn68xx;
+	struct cvmx_pko_reg_cmd_buf_s         cn68xxp1;
+	struct cvmx_pko_reg_cmd_buf_s         cnf71xx;
 };
 typedef union cvmx_pko_reg_cmd_buf cvmx_pko_reg_cmd_buf_t;
 
@@ -1947,12 +2680,10 @@ typedef union cvmx_pko_reg_cmd_buf cvmx_pko_reg_cmd_buf_t;
  * Controls datapath reflection when calculating CRC
  *
  */
-union cvmx_pko_reg_crc_ctlx
-{
+union cvmx_pko_reg_crc_ctlx {
 	uint64_t u64;
-	struct cvmx_pko_reg_crc_ctlx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_crc_ctlx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t invres                       : 1;  /**< Invert the result */
 	uint64_t refin                        : 1;  /**< Reflect the bits in each byte.
@@ -1979,12 +2710,10 @@ typedef union cvmx_pko_reg_crc_ctlx cvmx_pko_reg_crc_ctlx_t;
  * Enables CRC for the GMX ports.
  *
  */
-union cvmx_pko_reg_crc_enable
-{
+union cvmx_pko_reg_crc_enable {
 	uint64_t u64;
-	struct cvmx_pko_reg_crc_enable_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_crc_enable_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t enable                       : 32; /**< Mask for ports 31-0 to enable CRC
                                                          Mask bit==0 means CRC not enabled
@@ -2037,12 +2766,10 @@ typedef union cvmx_pko_reg_crc_enable cvmx_pko_reg_crc_enable_t;
  *   ]
  *   @endverbatim
  */
-union cvmx_pko_reg_crc_ivx
-{
+union cvmx_pko_reg_crc_ivx {
 	uint64_t u64;
-	struct cvmx_pko_reg_crc_ivx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_crc_ivx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t iv                           : 32; /**< IV used by the CRC algorithm.  Default is FCS32. */
 #else
@@ -2064,20 +2791,17 @@ typedef union cvmx_pko_reg_crc_ivx cvmx_pko_reg_crc_ivx_t;
  * Note that this CSR is present only in chip revisions beginning with pass2.
  *
  */
-union cvmx_pko_reg_debug0
-{
+union cvmx_pko_reg_debug0 {
 	uint64_t u64;
-	struct cvmx_pko_reg_debug0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_debug0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t asserts                      : 64; /**< Various assertion checks */
 #else
 	uint64_t asserts                      : 64;
 #endif
 	} s;
-	struct cvmx_pko_reg_debug0_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_debug0_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t asserts                      : 17; /**< Various assertion checks */
 #else
@@ -2095,20 +2819,23 @@ union cvmx_pko_reg_debug0
 	struct cvmx_pko_reg_debug0_s          cn56xxp1;
 	struct cvmx_pko_reg_debug0_s          cn58xx;
 	struct cvmx_pko_reg_debug0_s          cn58xxp1;
+	struct cvmx_pko_reg_debug0_s          cn61xx;
 	struct cvmx_pko_reg_debug0_s          cn63xx;
 	struct cvmx_pko_reg_debug0_s          cn63xxp1;
+	struct cvmx_pko_reg_debug0_s          cn66xx;
+	struct cvmx_pko_reg_debug0_s          cn68xx;
+	struct cvmx_pko_reg_debug0_s          cn68xxp1;
+	struct cvmx_pko_reg_debug0_s          cnf71xx;
 };
 typedef union cvmx_pko_reg_debug0 cvmx_pko_reg_debug0_t;
 
 /**
  * cvmx_pko_reg_debug1
  */
-union cvmx_pko_reg_debug1
-{
+union cvmx_pko_reg_debug1 {
 	uint64_t u64;
-	struct cvmx_pko_reg_debug1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_debug1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t asserts                      : 64; /**< Various assertion checks */
 #else
 	uint64_t asserts                      : 64;
@@ -2121,20 +2848,23 @@ union cvmx_pko_reg_debug1
 	struct cvmx_pko_reg_debug1_s          cn56xxp1;
 	struct cvmx_pko_reg_debug1_s          cn58xx;
 	struct cvmx_pko_reg_debug1_s          cn58xxp1;
+	struct cvmx_pko_reg_debug1_s          cn61xx;
 	struct cvmx_pko_reg_debug1_s          cn63xx;
 	struct cvmx_pko_reg_debug1_s          cn63xxp1;
+	struct cvmx_pko_reg_debug1_s          cn66xx;
+	struct cvmx_pko_reg_debug1_s          cn68xx;
+	struct cvmx_pko_reg_debug1_s          cn68xxp1;
+	struct cvmx_pko_reg_debug1_s          cnf71xx;
 };
 typedef union cvmx_pko_reg_debug1 cvmx_pko_reg_debug1_t;
 
 /**
  * cvmx_pko_reg_debug2
  */
-union cvmx_pko_reg_debug2
-{
+union cvmx_pko_reg_debug2 {
 	uint64_t u64;
-	struct cvmx_pko_reg_debug2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_debug2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t asserts                      : 64; /**< Various assertion checks */
 #else
 	uint64_t asserts                      : 64;
@@ -2147,20 +2877,23 @@ union cvmx_pko_reg_debug2
 	struct cvmx_pko_reg_debug2_s          cn56xxp1;
 	struct cvmx_pko_reg_debug2_s          cn58xx;
 	struct cvmx_pko_reg_debug2_s          cn58xxp1;
+	struct cvmx_pko_reg_debug2_s          cn61xx;
 	struct cvmx_pko_reg_debug2_s          cn63xx;
 	struct cvmx_pko_reg_debug2_s          cn63xxp1;
+	struct cvmx_pko_reg_debug2_s          cn66xx;
+	struct cvmx_pko_reg_debug2_s          cn68xx;
+	struct cvmx_pko_reg_debug2_s          cn68xxp1;
+	struct cvmx_pko_reg_debug2_s          cnf71xx;
 };
 typedef union cvmx_pko_reg_debug2 cvmx_pko_reg_debug2_t;
 
 /**
  * cvmx_pko_reg_debug3
  */
-union cvmx_pko_reg_debug3
-{
+union cvmx_pko_reg_debug3 {
 	uint64_t u64;
-	struct cvmx_pko_reg_debug3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_debug3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t asserts                      : 64; /**< Various assertion checks */
 #else
 	uint64_t asserts                      : 64;
@@ -2173,34 +2906,56 @@ union cvmx_pko_reg_debug3
 	struct cvmx_pko_reg_debug3_s          cn56xxp1;
 	struct cvmx_pko_reg_debug3_s          cn58xx;
 	struct cvmx_pko_reg_debug3_s          cn58xxp1;
+	struct cvmx_pko_reg_debug3_s          cn61xx;
 	struct cvmx_pko_reg_debug3_s          cn63xx;
 	struct cvmx_pko_reg_debug3_s          cn63xxp1;
+	struct cvmx_pko_reg_debug3_s          cn66xx;
+	struct cvmx_pko_reg_debug3_s          cn68xx;
+	struct cvmx_pko_reg_debug3_s          cn68xxp1;
+	struct cvmx_pko_reg_debug3_s          cnf71xx;
 };
 typedef union cvmx_pko_reg_debug3 cvmx_pko_reg_debug3_t;
 
 /**
+ * cvmx_pko_reg_debug4
+ */
+union cvmx_pko_reg_debug4 {
+	uint64_t u64;
+	struct cvmx_pko_reg_debug4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t asserts                      : 64; /**< Various assertion checks */
+#else
+	uint64_t asserts                      : 64;
+#endif
+	} s;
+	struct cvmx_pko_reg_debug4_s          cn68xx;
+	struct cvmx_pko_reg_debug4_s          cn68xxp1;
+};
+typedef union cvmx_pko_reg_debug4 cvmx_pko_reg_debug4_t;
+
+/**
  * cvmx_pko_reg_engine_inflight
  *
  * Notes:
  * Sets the maximum number of inflight packets, per engine.  Values greater than 4 are illegal.
  * Setting an engine's value to 0 effectively stops the engine.
- * Note that engines 4-7 do not exist
  */
-union cvmx_pko_reg_engine_inflight
-{
+union cvmx_pko_reg_engine_inflight {
 	uint64_t u64;
-	struct cvmx_pko_reg_engine_inflight_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_48_63               : 16;
+	struct cvmx_pko_reg_engine_inflight_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t engine15                     : 4;  /**< Maximum number of inflight packets for engine15 */
+	uint64_t engine14                     : 4;  /**< Maximum number of inflight packets for engine14 */
+	uint64_t engine13                     : 4;  /**< Maximum number of inflight packets for engine13 */
+	uint64_t engine12                     : 4;  /**< Maximum number of inflight packets for engine12 */
 	uint64_t engine11                     : 4;  /**< Maximum number of inflight packets for engine11 */
 	uint64_t engine10                     : 4;  /**< Maximum number of inflight packets for engine10 */
 	uint64_t engine9                      : 4;  /**< Maximum number of inflight packets for engine9 */
 	uint64_t engine8                      : 4;  /**< Maximum number of inflight packets for engine8 */
-	uint64_t engine7                      : 4;  /**< MBZ */
-	uint64_t engine6                      : 4;  /**< MBZ */
-	uint64_t engine5                      : 4;  /**< MBZ */
-	uint64_t engine4                      : 4;  /**< MBZ */
+	uint64_t engine7                      : 4;  /**< Maximum number of inflight packets for engine7 */
+	uint64_t engine6                      : 4;  /**< Maximum number of inflight packets for engine6 */
+	uint64_t engine5                      : 4;  /**< Maximum number of inflight packets for engine5 */
+	uint64_t engine4                      : 4;  /**< Maximum number of inflight packets for engine4 */
 	uint64_t engine3                      : 4;  /**< Maximum number of inflight packets for engine3 */
 	uint64_t engine2                      : 4;  /**< Maximum number of inflight packets for engine2 */
 	uint64_t engine1                      : 4;  /**< Maximum number of inflight packets for engine1 */
@@ -2218,12 +2973,14 @@ union cvmx_pko_reg_engine_inflight
 	uint64_t engine9                      : 4;
 	uint64_t engine10                     : 4;
 	uint64_t engine11                     : 4;
-	uint64_t reserved_48_63               : 16;
+	uint64_t engine12                     : 4;
+	uint64_t engine13                     : 4;
+	uint64_t engine14                     : 4;
+	uint64_t engine15                     : 4;
 #endif
 	} s;
-	struct cvmx_pko_reg_engine_inflight_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_engine_inflight_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t engine9                      : 4;  /**< Maximum number of inflight packets for engine9 */
 	uint64_t engine8                      : 4;  /**< Maximum number of inflight packets for engine8 */
@@ -2252,12 +3009,201 @@ union cvmx_pko_reg_engine_inflight
 	struct cvmx_pko_reg_engine_inflight_cn52xx cn52xxp1;
 	struct cvmx_pko_reg_engine_inflight_cn52xx cn56xx;
 	struct cvmx_pko_reg_engine_inflight_cn52xx cn56xxp1;
-	struct cvmx_pko_reg_engine_inflight_s cn63xx;
-	struct cvmx_pko_reg_engine_inflight_s cn63xxp1;
+	struct cvmx_pko_reg_engine_inflight_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_56_63               : 8;
+	uint64_t engine13                     : 4;  /**< Maximum number of inflight packets for engine13 */
+	uint64_t engine12                     : 4;  /**< Maximum number of inflight packets for engine12 */
+	uint64_t engine11                     : 4;  /**< Maximum number of inflight packets for engine11 */
+	uint64_t engine10                     : 4;  /**< Maximum number of inflight packets for engine10 */
+	uint64_t engine9                      : 4;  /**< Maximum number of inflight packets for engine9 */
+	uint64_t engine8                      : 4;  /**< Maximum number of inflight packets for engine8 */
+	uint64_t engine7                      : 4;  /**< Maximum number of inflight packets for engine7 */
+	uint64_t engine6                      : 4;  /**< Maximum number of inflight packets for engine6 */
+	uint64_t engine5                      : 4;  /**< Maximum number of inflight packets for engine5 */
+	uint64_t engine4                      : 4;  /**< Maximum number of inflight packets for engine4 */
+	uint64_t engine3                      : 4;  /**< Maximum number of inflight packets for engine3 */
+	uint64_t engine2                      : 4;  /**< Maximum number of inflight packets for engine2 */
+	uint64_t engine1                      : 4;  /**< Maximum number of inflight packets for engine1 */
+	uint64_t engine0                      : 4;  /**< Maximum number of inflight packets for engine0 */
+#else
+	uint64_t engine0                      : 4;
+	uint64_t engine1                      : 4;
+	uint64_t engine2                      : 4;
+	uint64_t engine3                      : 4;
+	uint64_t engine4                      : 4;
+	uint64_t engine5                      : 4;
+	uint64_t engine6                      : 4;
+	uint64_t engine7                      : 4;
+	uint64_t engine8                      : 4;
+	uint64_t engine9                      : 4;
+	uint64_t engine10                     : 4;
+	uint64_t engine11                     : 4;
+	uint64_t engine12                     : 4;
+	uint64_t engine13                     : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn61xx;
+	struct cvmx_pko_reg_engine_inflight_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_48_63               : 16;
+	uint64_t engine11                     : 4;  /**< Maximum number of inflight packets for engine11 */
+	uint64_t engine10                     : 4;  /**< Maximum number of inflight packets for engine10 */
+	uint64_t engine9                      : 4;  /**< Maximum number of inflight packets for engine9 */
+	uint64_t engine8                      : 4;  /**< Maximum number of inflight packets for engine8 */
+	uint64_t engine7                      : 4;  /**< MBZ */
+	uint64_t engine6                      : 4;  /**< MBZ */
+	uint64_t engine5                      : 4;  /**< MBZ */
+	uint64_t engine4                      : 4;  /**< MBZ */
+	uint64_t engine3                      : 4;  /**< Maximum number of inflight packets for engine3 */
+	uint64_t engine2                      : 4;  /**< Maximum number of inflight packets for engine2 */
+	uint64_t engine1                      : 4;  /**< Maximum number of inflight packets for engine1 */
+	uint64_t engine0                      : 4;  /**< Maximum number of inflight packets for engine0 */
+#else
+	uint64_t engine0                      : 4;
+	uint64_t engine1                      : 4;
+	uint64_t engine2                      : 4;
+	uint64_t engine3                      : 4;
+	uint64_t engine4                      : 4;
+	uint64_t engine5                      : 4;
+	uint64_t engine6                      : 4;
+	uint64_t engine7                      : 4;
+	uint64_t engine8                      : 4;
+	uint64_t engine9                      : 4;
+	uint64_t engine10                     : 4;
+	uint64_t engine11                     : 4;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} cn63xx;
+	struct cvmx_pko_reg_engine_inflight_cn63xx cn63xxp1;
+	struct cvmx_pko_reg_engine_inflight_cn61xx cn66xx;
+	struct cvmx_pko_reg_engine_inflight_s cn68xx;
+	struct cvmx_pko_reg_engine_inflight_s cn68xxp1;
+	struct cvmx_pko_reg_engine_inflight_cn61xx cnf71xx;
 };
 typedef union cvmx_pko_reg_engine_inflight cvmx_pko_reg_engine_inflight_t;
 
 /**
+ * cvmx_pko_reg_engine_inflight1
+ *
+ * Notes:
+ * Sets the maximum number of inflight packets, per engine.  Values greater than 8 are illegal.
+ * Setting an engine's value to 0 effectively stops the engine.
+ */
+union cvmx_pko_reg_engine_inflight1 {
+	uint64_t u64;
+	struct cvmx_pko_reg_engine_inflight1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t engine19                     : 4;  /**< Maximum number of inflight packets for engine19 */
+	uint64_t engine18                     : 4;  /**< Maximum number of inflight packets for engine18 */
+	uint64_t engine17                     : 4;  /**< Maximum number of inflight packets for engine17 */
+	uint64_t engine16                     : 4;  /**< Maximum number of inflight packets for engine16 */
+#else
+	uint64_t engine16                     : 4;
+	uint64_t engine17                     : 4;
+	uint64_t engine18                     : 4;
+	uint64_t engine19                     : 4;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pko_reg_engine_inflight1_s cn68xx;
+	struct cvmx_pko_reg_engine_inflight1_s cn68xxp1;
+};
+typedef union cvmx_pko_reg_engine_inflight1 cvmx_pko_reg_engine_inflight1_t;
+
+/**
+ * cvmx_pko_reg_engine_storage#
+ *
+ * Notes:
+ * The PKO has 40KB of local storage, consisting of 20, 2KB chunks.  Up to 15 contiguous chunks may be mapped per engine.
+ * The total of all mapped storage must not exceed 40KB.
+ */
+union cvmx_pko_reg_engine_storagex {
+	uint64_t u64;
+	struct cvmx_pko_reg_engine_storagex_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t engine15                     : 4;  /**< Number of contiguous 2KB chunks allocated to
+                                                         engine (X * 16) + 15.
+                                                         ENGINE15 does not exist and is reserved in
+                                                         PKO_REG_ENGINE_STORAGE1. */
+	uint64_t engine14                     : 4;  /**< Number of contiguous 2KB chunks allocated to
+                                                         engine (X * 16) + 14.
+                                                         ENGINE14 does not exist and is reserved in
+                                                         PKO_REG_ENGINE_STORAGE1. */
+	uint64_t engine13                     : 4;  /**< Number of contiguous 2KB chunks allocated to
+                                                         engine (X * 16) + 13.
+                                                         ENGINE13 does not exist and is reserved in
+                                                         PKO_REG_ENGINE_STORAGE1. */
+	uint64_t engine12                     : 4;  /**< Number of contiguous 2KB chunks allocated to
+                                                         engine (X * 16) + 12.
+                                                         ENGINE12 does not exist and is reserved in
+                                                         PKO_REG_ENGINE_STORAGE1. */
+	uint64_t engine11                     : 4;  /**< Number of contiguous 2KB chunks allocated to
+                                                         engine (X * 16) + 11.
+                                                         ENGINE11 does not exist and is reserved in
+                                                         PKO_REG_ENGINE_STORAGE1. */
+	uint64_t engine10                     : 4;  /**< Number of contiguous 2KB chunks allocated to
+                                                         engine (X * 16) + 10.
+                                                         ENGINE10 does not exist and is reserved in
+                                                         PKO_REG_ENGINE_STORAGE1. */
+	uint64_t engine9                      : 4;  /**< Number of contiguous 2KB chunks allocated to
+                                                         engine (X * 16) + 9.
+                                                         ENGINE9 does not exist and is reserved in
+                                                         PKO_REG_ENGINE_STORAGE1. */
+	uint64_t engine8                      : 4;  /**< Number of contiguous 2KB chunks allocated to
+                                                         engine (X * 16) + 8.
+                                                         ENGINE8 does not exist and is reserved in
+                                                         PKO_REG_ENGINE_STORAGE1. */
+	uint64_t engine7                      : 4;  /**< Number of contiguous 2KB chunks allocated to
+                                                         engine (X * 16) + 7.
+                                                         ENGINE7 does not exist and is reserved in
+                                                         PKO_REG_ENGINE_STORAGE1. */
+	uint64_t engine6                      : 4;  /**< Number of contiguous 2KB chunks allocated to
+                                                         engine (X * 16) + 6.
+                                                         ENGINE6 does not exist and is reserved in
+                                                         PKO_REG_ENGINE_STORAGE1. */
+	uint64_t engine5                      : 4;  /**< Number of contiguous 2KB chunks allocated to
+                                                         engine (X * 16) + 5.
+                                                         ENGINE5 does not exist and is reserved in
+                                                         PKO_REG_ENGINE_STORAGE1. */
+	uint64_t engine4                      : 4;  /**< Number of contiguous 2KB chunks allocated to
+                                                         engine (X * 16) + 4.
+                                                         ENGINE4 does not exist and is reserved in
+                                                         PKO_REG_ENGINE_STORAGE1. */
+	uint64_t engine3                      : 4;  /**< Number of contiguous 2KB chunks allocated to
+                                                         engine (X * 16) + 3. */
+	uint64_t engine2                      : 4;  /**< Number of contiguous 2KB chunks allocated to
+                                                         engine (X * 16) + 2. */
+	uint64_t engine1                      : 4;  /**< Number of contiguous 2KB chunks allocated to
+                                                         engine (X * 16) + 1. */
+	uint64_t engine0                      : 4;  /**< Number of contiguous 2KB chunks allocated to
+                                                         engine (X * 16) + 0. */
+#else
+	uint64_t engine0                      : 4;
+	uint64_t engine1                      : 4;
+	uint64_t engine2                      : 4;
+	uint64_t engine3                      : 4;
+	uint64_t engine4                      : 4;
+	uint64_t engine5                      : 4;
+	uint64_t engine6                      : 4;
+	uint64_t engine7                      : 4;
+	uint64_t engine8                      : 4;
+	uint64_t engine9                      : 4;
+	uint64_t engine10                     : 4;
+	uint64_t engine11                     : 4;
+	uint64_t engine12                     : 4;
+	uint64_t engine13                     : 4;
+	uint64_t engine14                     : 4;
+	uint64_t engine15                     : 4;
+#endif
+	} s;
+	struct cvmx_pko_reg_engine_storagex_s cn68xx;
+	struct cvmx_pko_reg_engine_storagex_s cn68xxp1;
+};
+typedef union cvmx_pko_reg_engine_storagex cvmx_pko_reg_engine_storagex_t;
+
+/**
  * cvmx_pko_reg_engine_thresh
  *
  * Notes:
@@ -2268,26 +3214,21 @@ typedef union cvmx_pko_reg_engine_inflight cvmx_pko_reg_engine_inflight_t;
  * packet does not fit entirely in the PKO's internal buffer, none of the packet data will be sent until
  * at least BUFFER_SIZE-256 bytes of the packet have been written into the PKO's internal buffer
  * (note that BUFFER_SIZE is a function of PKO_REG_GMX_PORT_MODE above)
- * Note that engines 4-7 do not exist, so MASK<7:4> MBZ
  */
-union cvmx_pko_reg_engine_thresh
-{
+union cvmx_pko_reg_engine_thresh {
 	uint64_t u64;
-	struct cvmx_pko_reg_engine_thresh_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_12_63               : 52;
-	uint64_t mask                         : 12; /**< Mask[n]=0 disables packet send threshold for engine n
-                                                         Mask[n]=1 enables  packet send threshold for engine n  $PR       NS
-                                                         Mask[n] MBZ for n = 4-7, as engines 4-7 dont exist */
+	struct cvmx_pko_reg_engine_thresh_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t mask                         : 20; /**< Mask[n]=0 disables packet send threshold for engine n
+                                                         Mask[n]=1 enables  packet send threshold for engine n  $PR       NS */
 #else
-	uint64_t mask                         : 12;
-	uint64_t reserved_12_63               : 52;
+	uint64_t mask                         : 20;
+	uint64_t reserved_20_63               : 44;
 #endif
 	} s;
-	struct cvmx_pko_reg_engine_thresh_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_engine_thresh_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t mask                         : 10; /**< Mask[n]=0 disables packet send threshold for eng n
                                                          Mask[n]=1 enables  packet send threshold for eng n     $PR       NS
@@ -2300,8 +3241,32 @@ union cvmx_pko_reg_engine_thresh
 	struct cvmx_pko_reg_engine_thresh_cn52xx cn52xxp1;
 	struct cvmx_pko_reg_engine_thresh_cn52xx cn56xx;
 	struct cvmx_pko_reg_engine_thresh_cn52xx cn56xxp1;
-	struct cvmx_pko_reg_engine_thresh_s   cn63xx;
-	struct cvmx_pko_reg_engine_thresh_s   cn63xxp1;
+	struct cvmx_pko_reg_engine_thresh_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_14_63               : 50;
+	uint64_t mask                         : 14; /**< Mask[n]=0 disables packet send threshold for engine n
+                                                         Mask[n]=1 enables  packet send threshold for engine n  $PR       NS */
+#else
+	uint64_t mask                         : 14;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} cn61xx;
+	struct cvmx_pko_reg_engine_thresh_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_12_63               : 52;
+	uint64_t mask                         : 12; /**< Mask[n]=0 disables packet send threshold for engine n
+                                                         Mask[n]=1 enables  packet send threshold for engine n  $PR       NS
+                                                         Mask[n] MBZ for n = 4-7, as engines 4-7 dont exist */
+#else
+	uint64_t mask                         : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn63xx;
+	struct cvmx_pko_reg_engine_thresh_cn63xx cn63xxp1;
+	struct cvmx_pko_reg_engine_thresh_cn61xx cn66xx;
+	struct cvmx_pko_reg_engine_thresh_s   cn68xx;
+	struct cvmx_pko_reg_engine_thresh_s   cn68xxp1;
+	struct cvmx_pko_reg_engine_thresh_cn61xx cnf71xx;
 };
 typedef union cvmx_pko_reg_engine_thresh cvmx_pko_reg_engine_thresh_t;
 
@@ -2312,13 +3277,12 @@ typedef union cvmx_pko_reg_engine_thresh cvmx_pko_reg_engine_thresh_t;
  * Note that this CSR is present only in chip revisions beginning with pass2.
  *
  */
-union cvmx_pko_reg_error
-{
+union cvmx_pko_reg_error {
 	uint64_t u64;
-	struct cvmx_pko_reg_error_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_3_63                : 61;
+	struct cvmx_pko_reg_error_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t loopback                     : 1;  /**< A packet was sent to an illegal loopback port */
 	uint64_t currzero                     : 1;  /**< A packet data pointer has size=0 */
 	uint64_t doorbell                     : 1;  /**< A doorbell count has overflowed */
 	uint64_t parity                       : 1;  /**< Read parity error at port data buffer */
@@ -2326,12 +3290,12 @@ union cvmx_pko_reg_error
 	uint64_t parity                       : 1;
 	uint64_t doorbell                     : 1;
 	uint64_t currzero                     : 1;
-	uint64_t reserved_3_63                : 61;
+	uint64_t loopback                     : 1;
+	uint64_t reserved_4_63                : 60;
 #endif
 	} s;
-	struct cvmx_pko_reg_error_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_error_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t doorbell                     : 1;  /**< A doorbell count has overflowed */
 	uint64_t parity                       : 1;  /**< Read parity error at port data buffer */
@@ -2344,15 +3308,32 @@ union cvmx_pko_reg_error
 	struct cvmx_pko_reg_error_cn30xx      cn31xx;
 	struct cvmx_pko_reg_error_cn30xx      cn38xx;
 	struct cvmx_pko_reg_error_cn30xx      cn38xxp2;
-	struct cvmx_pko_reg_error_s           cn50xx;
-	struct cvmx_pko_reg_error_s           cn52xx;
-	struct cvmx_pko_reg_error_s           cn52xxp1;
-	struct cvmx_pko_reg_error_s           cn56xx;
-	struct cvmx_pko_reg_error_s           cn56xxp1;
-	struct cvmx_pko_reg_error_s           cn58xx;
-	struct cvmx_pko_reg_error_s           cn58xxp1;
-	struct cvmx_pko_reg_error_s           cn63xx;
-	struct cvmx_pko_reg_error_s           cn63xxp1;
+	struct cvmx_pko_reg_error_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_3_63                : 61;
+	uint64_t currzero                     : 1;  /**< A packet data pointer has size=0 */
+	uint64_t doorbell                     : 1;  /**< A doorbell count has overflowed */
+	uint64_t parity                       : 1;  /**< Read parity error at port data buffer */
+#else
+	uint64_t parity                       : 1;
+	uint64_t doorbell                     : 1;
+	uint64_t currzero                     : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} cn50xx;
+	struct cvmx_pko_reg_error_cn50xx      cn52xx;
+	struct cvmx_pko_reg_error_cn50xx      cn52xxp1;
+	struct cvmx_pko_reg_error_cn50xx      cn56xx;
+	struct cvmx_pko_reg_error_cn50xx      cn56xxp1;
+	struct cvmx_pko_reg_error_cn50xx      cn58xx;
+	struct cvmx_pko_reg_error_cn50xx      cn58xxp1;
+	struct cvmx_pko_reg_error_cn50xx      cn61xx;
+	struct cvmx_pko_reg_error_cn50xx      cn63xx;
+	struct cvmx_pko_reg_error_cn50xx      cn63xxp1;
+	struct cvmx_pko_reg_error_cn50xx      cn66xx;
+	struct cvmx_pko_reg_error_s           cn68xx;
+	struct cvmx_pko_reg_error_s           cn68xxp1;
+	struct cvmx_pko_reg_error_cn50xx      cnf71xx;
 };
 typedef union cvmx_pko_reg_error cvmx_pko_reg_error_t;
 
@@ -2365,12 +3346,41 @@ typedef union cvmx_pko_reg_error cvmx_pko_reg_error_t;
  * bits[2:0] of the STORE0 byte write address.  When set, RESET causes a 4-cycle reset pulse to the
  * entire box.
  */
-union cvmx_pko_reg_flags
-{
+union cvmx_pko_reg_flags {
 	uint64_t u64;
-	struct cvmx_pko_reg_flags_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_flags_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_9_63                : 55;
+	uint64_t dis_perf3                    : 1;  /**< Set to disable inactive queue QOS skipping */
+	uint64_t dis_perf2                    : 1;  /**< Set to disable inactive queue skipping */
+	uint64_t dis_perf1                    : 1;  /**< Set to disable command word prefetching */
+	uint64_t dis_perf0                    : 1;  /**< Set to disable read performance optimizations */
+	uint64_t ena_throttle                 : 1;  /**< Set to enable the PKO picker throttle logic
+                                                         When ENA_THROTTLE=1 and the most-significant
+                                                         bit of any of the pipe or interface, word or
+                                                         packet throttle count is set, then PKO will
+                                                         not output any packets to the interface/pipe.
+                                                         See PKO_MEM_THROTTLE_PIPE and
+                                                         PKO_MEM_THROTTLE_INT. */
+	uint64_t reset                        : 1;  /**< Reset oneshot pulse */
+	uint64_t store_be                     : 1;  /**< Force STORE0 byte write address to big endian */
+	uint64_t ena_dwb                      : 1;  /**< Set to enable DontWriteBacks */
+	uint64_t ena_pko                      : 1;  /**< Set to enable the PKO picker */
+#else
+	uint64_t ena_pko                      : 1;
+	uint64_t ena_dwb                      : 1;
+	uint64_t store_be                     : 1;
+	uint64_t reset                        : 1;
+	uint64_t ena_throttle                 : 1;
+	uint64_t dis_perf0                    : 1;
+	uint64_t dis_perf1                    : 1;
+	uint64_t dis_perf2                    : 1;
+	uint64_t dis_perf3                    : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_pko_reg_flags_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t reset                        : 1;  /**< Reset oneshot pulse */
 	uint64_t store_be                     : 1;  /**< Force STORE0 byte write address to big endian */
@@ -2383,20 +3393,70 @@ union cvmx_pko_reg_flags
 	uint64_t reset                        : 1;
 	uint64_t reserved_4_63                : 60;
 #endif
-	} s;
-	struct cvmx_pko_reg_flags_s           cn30xx;
-	struct cvmx_pko_reg_flags_s           cn31xx;
-	struct cvmx_pko_reg_flags_s           cn38xx;
-	struct cvmx_pko_reg_flags_s           cn38xxp2;
-	struct cvmx_pko_reg_flags_s           cn50xx;
-	struct cvmx_pko_reg_flags_s           cn52xx;
-	struct cvmx_pko_reg_flags_s           cn52xxp1;
-	struct cvmx_pko_reg_flags_s           cn56xx;
-	struct cvmx_pko_reg_flags_s           cn56xxp1;
-	struct cvmx_pko_reg_flags_s           cn58xx;
-	struct cvmx_pko_reg_flags_s           cn58xxp1;
-	struct cvmx_pko_reg_flags_s           cn63xx;
-	struct cvmx_pko_reg_flags_s           cn63xxp1;
+	} cn30xx;
+	struct cvmx_pko_reg_flags_cn30xx      cn31xx;
+	struct cvmx_pko_reg_flags_cn30xx      cn38xx;
+	struct cvmx_pko_reg_flags_cn30xx      cn38xxp2;
+	struct cvmx_pko_reg_flags_cn30xx      cn50xx;
+	struct cvmx_pko_reg_flags_cn30xx      cn52xx;
+	struct cvmx_pko_reg_flags_cn30xx      cn52xxp1;
+	struct cvmx_pko_reg_flags_cn30xx      cn56xx;
+	struct cvmx_pko_reg_flags_cn30xx      cn56xxp1;
+	struct cvmx_pko_reg_flags_cn30xx      cn58xx;
+	struct cvmx_pko_reg_flags_cn30xx      cn58xxp1;
+	struct cvmx_pko_reg_flags_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_9_63                : 55;
+	uint64_t dis_perf3                    : 1;  /**< Set to disable inactive queue QOS skipping */
+	uint64_t dis_perf2                    : 1;  /**< Set to disable inactive queue skipping */
+	uint64_t reserved_4_6                 : 3;
+	uint64_t reset                        : 1;  /**< Reset oneshot pulse */
+	uint64_t store_be                     : 1;  /**< Force STORE0 byte write address to big endian */
+	uint64_t ena_dwb                      : 1;  /**< Set to enable DontWriteBacks */
+	uint64_t ena_pko                      : 1;  /**< Set to enable the PKO picker */
+#else
+	uint64_t ena_pko                      : 1;
+	uint64_t ena_dwb                      : 1;
+	uint64_t store_be                     : 1;
+	uint64_t reset                        : 1;
+	uint64_t reserved_4_6                 : 3;
+	uint64_t dis_perf2                    : 1;
+	uint64_t dis_perf3                    : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn61xx;
+	struct cvmx_pko_reg_flags_cn30xx      cn63xx;
+	struct cvmx_pko_reg_flags_cn30xx      cn63xxp1;
+	struct cvmx_pko_reg_flags_cn61xx      cn66xx;
+	struct cvmx_pko_reg_flags_s           cn68xx;
+	struct cvmx_pko_reg_flags_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t dis_perf1                    : 1;  /**< Set to disable command word prefetching */
+	uint64_t dis_perf0                    : 1;  /**< Set to disable read performance optimizations */
+	uint64_t ena_throttle                 : 1;  /**< Set to enable the PKO picker throttle logic
+                                                         When ENA_THROTTLE=1 and the most-significant
+                                                         bit of any of the pipe or interface, word or
+                                                         packet throttle count is set, then PKO will
+                                                         not output any packets to the interface/pipe.
+                                                         See PKO_MEM_THROTTLE_PIPE and
+                                                         PKO_MEM_THROTTLE_INT. */
+	uint64_t reset                        : 1;  /**< Reset oneshot pulse */
+	uint64_t store_be                     : 1;  /**< Force STORE0 byte write address to big endian */
+	uint64_t ena_dwb                      : 1;  /**< Set to enable DontWriteBacks */
+	uint64_t ena_pko                      : 1;  /**< Set to enable the PKO picker */
+#else
+	uint64_t ena_pko                      : 1;
+	uint64_t ena_dwb                      : 1;
+	uint64_t store_be                     : 1;
+	uint64_t reset                        : 1;
+	uint64_t ena_throttle                 : 1;
+	uint64_t dis_perf0                    : 1;
+	uint64_t dis_perf1                    : 1;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} cn68xxp1;
+	struct cvmx_pko_reg_flags_cn61xx      cnf71xx;
 };
 typedef union cvmx_pko_reg_flags cvmx_pko_reg_flags_t;
 
@@ -2404,30 +3464,31 @@ typedef union cvmx_pko_reg_flags cvmx_pko_reg_flags_t;
  * cvmx_pko_reg_gmx_port_mode
  *
  * Notes:
- * The system has a total of 4 + 0 + 4 + 4 + 4 ports and 4 + 0 + 1 + 1 + 1 + 1 engines (GM0 + GM1 + PCI + LOOP + SRIO0 + SRIO1).
- * This CSR sets the number of GMX0 ports and amount of local storage per engine.
+ * The system has a total of 4 + 4 + 4 + 4 + 4 ports and 4 + 4 + 1 + 1 + 1 + 1 engines (GM0 + GM1 + PCI + LOOP + SRIO0 + SRIO1 + SRIO2 + SRIO3).
+ * This CSR sets the number of GMX0/GMX1 ports and amount of local storage per engine.
  * It has no effect on the number of ports or amount of local storage per engine for PCI, LOOP,
- * SRIO0, or SRIO1.  When all GMX ports are used (MODE0=2), each GMX engine has 2.5kB of local
+ * SRIO0, SRIO1, SRIO2, or SRIO3.  When all GMX ports are used (MODE0=2), each GMX engine has 2.5kB of local
  * storage.  Increasing the value of MODEn by 1 decreases the number of GMX ports by a power of 2 and
- * increases the local storage per PKO GMX engine by a power of 2.
- * Modes 0 and 1 are illegal and, if selected, are treated as mode 2.
- *
- * MODE[n] GM[0] PCI   LOOP  GM[0]                      PCI            LOOP            SRIO0           SRIO1
- *         ports ports ports storage/engine             storage/engine storage/engine  storage/engine  storage/engine
- * 0       4     4     4       2.5kB                    2.5kB          2.5kB           2.5kB           2.5kB
- * 1       4     4     4       2.5kB                    2.5kB          2.5kB           2.5kB           2.5kB
- * 2       4     4     4       2.5kB                    2.5kB          2.5kB           2.5kB           2.5kB
- * 3       2     4     4       5.0kB                    2.5kB          2.5kB           2.5kB           2.5kB
- * 4       1     4     4      10.0kB                    2.5kB          2.5kB           2.5kB           2.5kB
+ * increases the local storage per PKO GMX engine by a power of 2.  If one of the modes is 5, then only
+ * one of interfaces GM0 or GM1 is present and the storage per engine of the existing interface is
+ * doubled.  Modes 0 and 1 are illegal and, if selected, are treated as mode 2.
+ *
+ * MODE[n] GM[n] PCI   LOOP  GM[n]                      PCI            LOOP           SRIO[n]
+ *         ports ports ports storage/engine             storage/engine storage/engine storage/engine
+ * 0       4     4     4     ( 2.5kB << (MODE[1-n]==5)) 2.5kB          2.5kB          2.5kB
+ * 1       4     4     4     ( 2.5kB << (MODE[1-n]==5)) 2.5kB          2.5kB          2.5kB
+ * 2       4     4     4     ( 2.5kB << (MODE[1-n]==5)) 2.5kB          2.5kB          2.5kB
+ * 3       2     4     4     ( 5.0kB << (MODE[1-n]==5)) 2.5kB          2.5kB          2.5kB
+ * 4       1     4     4     (10.0kB << (MODE[1-n]==5)) 2.5kB          2.5kB          2.5kB
+ * 5       0     4     4     (   0kB                  ) 2.5kB          2.5kB          2.5kB
+ * where 0 <= n <= 1
  */
-union cvmx_pko_reg_gmx_port_mode
-{
+union cvmx_pko_reg_gmx_port_mode {
 	uint64_t u64;
-	struct cvmx_pko_reg_gmx_port_mode_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_gmx_port_mode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
-	uint64_t mode1                        : 3;  /**< MBZ */
+	uint64_t mode1                        : 3;  /**< # of GM1 ports = 16 >> MODE0, 0 <= MODE0 <= 4 */
 	uint64_t mode0                        : 3;  /**< # of GM0 ports = 16 >> MODE0, 0 <= MODE0 <= 4 */
 #else
 	uint64_t mode0                        : 3;
@@ -2446,8 +3507,11 @@ union cvmx_pko_reg_gmx_port_mode
 	struct cvmx_pko_reg_gmx_port_mode_s   cn56xxp1;
 	struct cvmx_pko_reg_gmx_port_mode_s   cn58xx;
 	struct cvmx_pko_reg_gmx_port_mode_s   cn58xxp1;
+	struct cvmx_pko_reg_gmx_port_mode_s   cn61xx;
 	struct cvmx_pko_reg_gmx_port_mode_s   cn63xx;
 	struct cvmx_pko_reg_gmx_port_mode_s   cn63xxp1;
+	struct cvmx_pko_reg_gmx_port_mode_s   cn66xx;
+	struct cvmx_pko_reg_gmx_port_mode_s   cnf71xx;
 };
 typedef union cvmx_pko_reg_gmx_port_mode cvmx_pko_reg_gmx_port_mode_t;
 
@@ -2458,13 +3522,12 @@ typedef union cvmx_pko_reg_gmx_port_mode cvmx_pko_reg_gmx_port_mode_t;
  * When a mask bit is set, the corresponding interrupt is enabled.
  *
  */
-union cvmx_pko_reg_int_mask
-{
+union cvmx_pko_reg_int_mask {
 	uint64_t u64;
-	struct cvmx_pko_reg_int_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_3_63                : 61;
+	struct cvmx_pko_reg_int_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t loopback                     : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[3] above */
 	uint64_t currzero                     : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[2] above */
 	uint64_t doorbell                     : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[1] above */
 	uint64_t parity                       : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[0] above */
@@ -2472,12 +3535,12 @@ union cvmx_pko_reg_int_mask
 	uint64_t parity                       : 1;
 	uint64_t doorbell                     : 1;
 	uint64_t currzero                     : 1;
-	uint64_t reserved_3_63                : 61;
+	uint64_t loopback                     : 1;
+	uint64_t reserved_4_63                : 60;
 #endif
 	} s;
-	struct cvmx_pko_reg_int_mask_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_int_mask_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t doorbell                     : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[1] above */
 	uint64_t parity                       : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[0] above */
@@ -2490,19 +3553,208 @@ union cvmx_pko_reg_int_mask
 	struct cvmx_pko_reg_int_mask_cn30xx   cn31xx;
 	struct cvmx_pko_reg_int_mask_cn30xx   cn38xx;
 	struct cvmx_pko_reg_int_mask_cn30xx   cn38xxp2;
-	struct cvmx_pko_reg_int_mask_s        cn50xx;
-	struct cvmx_pko_reg_int_mask_s        cn52xx;
-	struct cvmx_pko_reg_int_mask_s        cn52xxp1;
-	struct cvmx_pko_reg_int_mask_s        cn56xx;
-	struct cvmx_pko_reg_int_mask_s        cn56xxp1;
-	struct cvmx_pko_reg_int_mask_s        cn58xx;
-	struct cvmx_pko_reg_int_mask_s        cn58xxp1;
-	struct cvmx_pko_reg_int_mask_s        cn63xx;
-	struct cvmx_pko_reg_int_mask_s        cn63xxp1;
+	struct cvmx_pko_reg_int_mask_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_3_63                : 61;
+	uint64_t currzero                     : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[2] above */
+	uint64_t doorbell                     : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[1] above */
+	uint64_t parity                       : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[0] above */
+#else
+	uint64_t parity                       : 1;
+	uint64_t doorbell                     : 1;
+	uint64_t currzero                     : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} cn50xx;
+	struct cvmx_pko_reg_int_mask_cn50xx   cn52xx;
+	struct cvmx_pko_reg_int_mask_cn50xx   cn52xxp1;
+	struct cvmx_pko_reg_int_mask_cn50xx   cn56xx;
+	struct cvmx_pko_reg_int_mask_cn50xx   cn56xxp1;
+	struct cvmx_pko_reg_int_mask_cn50xx   cn58xx;
+	struct cvmx_pko_reg_int_mask_cn50xx   cn58xxp1;
+	struct cvmx_pko_reg_int_mask_cn50xx   cn61xx;
+	struct cvmx_pko_reg_int_mask_cn50xx   cn63xx;
+	struct cvmx_pko_reg_int_mask_cn50xx   cn63xxp1;
+	struct cvmx_pko_reg_int_mask_cn50xx   cn66xx;
+	struct cvmx_pko_reg_int_mask_s        cn68xx;
+	struct cvmx_pko_reg_int_mask_s        cn68xxp1;
+	struct cvmx_pko_reg_int_mask_cn50xx   cnf71xx;
 };
 typedef union cvmx_pko_reg_int_mask cvmx_pko_reg_int_mask_t;
 
 /**
+ * cvmx_pko_reg_loopback_bpid
+ *
+ * Notes:
+ * None.
+ *
+ */
+union cvmx_pko_reg_loopback_bpid {
+	uint64_t u64;
+	struct cvmx_pko_reg_loopback_bpid_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_59_63               : 5;
+	uint64_t bpid7                        : 6;  /**< Loopback port 7 backpressure-ID */
+	uint64_t reserved_52_52               : 1;
+	uint64_t bpid6                        : 6;  /**< Loopback port 6 backpressure-ID */
+	uint64_t reserved_45_45               : 1;
+	uint64_t bpid5                        : 6;  /**< Loopback port 5 backpressure-ID */
+	uint64_t reserved_38_38               : 1;
+	uint64_t bpid4                        : 6;  /**< Loopback port 4 backpressure-ID */
+	uint64_t reserved_31_31               : 1;
+	uint64_t bpid3                        : 6;  /**< Loopback port 3 backpressure-ID */
+	uint64_t reserved_24_24               : 1;
+	uint64_t bpid2                        : 6;  /**< Loopback port 2 backpressure-ID */
+	uint64_t reserved_17_17               : 1;
+	uint64_t bpid1                        : 6;  /**< Loopback port 1 backpressure-ID */
+	uint64_t reserved_10_10               : 1;
+	uint64_t bpid0                        : 6;  /**< Loopback port 0 backpressure-ID */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t bpid0                        : 6;
+	uint64_t reserved_10_10               : 1;
+	uint64_t bpid1                        : 6;
+	uint64_t reserved_17_17               : 1;
+	uint64_t bpid2                        : 6;
+	uint64_t reserved_24_24               : 1;
+	uint64_t bpid3                        : 6;
+	uint64_t reserved_31_31               : 1;
+	uint64_t bpid4                        : 6;
+	uint64_t reserved_38_38               : 1;
+	uint64_t bpid5                        : 6;
+	uint64_t reserved_45_45               : 1;
+	uint64_t bpid6                        : 6;
+	uint64_t reserved_52_52               : 1;
+	uint64_t bpid7                        : 6;
+	uint64_t reserved_59_63               : 5;
+#endif
+	} s;
+	struct cvmx_pko_reg_loopback_bpid_s   cn68xx;
+	struct cvmx_pko_reg_loopback_bpid_s   cn68xxp1;
+};
+typedef union cvmx_pko_reg_loopback_bpid cvmx_pko_reg_loopback_bpid_t;
+
+/**
+ * cvmx_pko_reg_loopback_pkind
+ *
+ * Notes:
+ * None.
+ *
+ */
+union cvmx_pko_reg_loopback_pkind {
+	uint64_t u64;
+	struct cvmx_pko_reg_loopback_pkind_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_59_63               : 5;
+	uint64_t pkind7                       : 6;  /**< Loopback port 7 port-kind */
+	uint64_t reserved_52_52               : 1;
+	uint64_t pkind6                       : 6;  /**< Loopback port 6 port-kind */
+	uint64_t reserved_45_45               : 1;
+	uint64_t pkind5                       : 6;  /**< Loopback port 5 port-kind */
+	uint64_t reserved_38_38               : 1;
+	uint64_t pkind4                       : 6;  /**< Loopback port 4 port-kind */
+	uint64_t reserved_31_31               : 1;
+	uint64_t pkind3                       : 6;  /**< Loopback port 3 port-kind */
+	uint64_t reserved_24_24               : 1;
+	uint64_t pkind2                       : 6;  /**< Loopback port 2 port-kind */
+	uint64_t reserved_17_17               : 1;
+	uint64_t pkind1                       : 6;  /**< Loopback port 1 port-kind */
+	uint64_t reserved_10_10               : 1;
+	uint64_t pkind0                       : 6;  /**< Loopback port 0 port-kind */
+	uint64_t num_ports                    : 4;  /**< Number of loopback ports, 0 <= NUM_PORTS <= 8 */
+#else
+	uint64_t num_ports                    : 4;
+	uint64_t pkind0                       : 6;
+	uint64_t reserved_10_10               : 1;
+	uint64_t pkind1                       : 6;
+	uint64_t reserved_17_17               : 1;
+	uint64_t pkind2                       : 6;
+	uint64_t reserved_24_24               : 1;
+	uint64_t pkind3                       : 6;
+	uint64_t reserved_31_31               : 1;
+	uint64_t pkind4                       : 6;
+	uint64_t reserved_38_38               : 1;
+	uint64_t pkind5                       : 6;
+	uint64_t reserved_45_45               : 1;
+	uint64_t pkind6                       : 6;
+	uint64_t reserved_52_52               : 1;
+	uint64_t pkind7                       : 6;
+	uint64_t reserved_59_63               : 5;
+#endif
+	} s;
+	struct cvmx_pko_reg_loopback_pkind_s  cn68xx;
+	struct cvmx_pko_reg_loopback_pkind_s  cn68xxp1;
+};
+typedef union cvmx_pko_reg_loopback_pkind cvmx_pko_reg_loopback_pkind_t;
+
+/**
+ * cvmx_pko_reg_min_pkt
+ *
+ * Notes:
+ * This CSR is used with PKO_MEM_IPORT_PTRS[MIN_PKT] to select the minimum packet size.  Packets whose
+ * size in bytes < (SIZEn+1) are zero-padded to (SIZEn+1) bytes.  Note that this does not include CRC bytes.
+ * SIZE0=0 is read-only and is used when no padding is desired.
+ */
+union cvmx_pko_reg_min_pkt {
+	uint64_t u64;
+	struct cvmx_pko_reg_min_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t size7                        : 8;  /**< Minimum packet size-1 in bytes                                NS */
+	uint64_t size6                        : 8;  /**< Minimum packet size-1 in bytes                                NS */
+	uint64_t size5                        : 8;  /**< Minimum packet size-1 in bytes                                NS */
+	uint64_t size4                        : 8;  /**< Minimum packet size-1 in bytes                                NS */
+	uint64_t size3                        : 8;  /**< Minimum packet size-1 in bytes                                NS */
+	uint64_t size2                        : 8;  /**< Minimum packet size-1 in bytes                                NS */
+	uint64_t size1                        : 8;  /**< Minimum packet size-1 in bytes                                NS */
+	uint64_t size0                        : 8;  /**< Minimum packet size-1 in bytes                                NS */
+#else
+	uint64_t size0                        : 8;
+	uint64_t size1                        : 8;
+	uint64_t size2                        : 8;
+	uint64_t size3                        : 8;
+	uint64_t size4                        : 8;
+	uint64_t size5                        : 8;
+	uint64_t size6                        : 8;
+	uint64_t size7                        : 8;
+#endif
+	} s;
+	struct cvmx_pko_reg_min_pkt_s         cn68xx;
+	struct cvmx_pko_reg_min_pkt_s         cn68xxp1;
+};
+typedef union cvmx_pko_reg_min_pkt cvmx_pko_reg_min_pkt_t;
+
+/**
+ * cvmx_pko_reg_preempt
+ */
+union cvmx_pko_reg_preempt {
+	uint64_t u64;
+	struct cvmx_pko_reg_preempt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t min_size                     : 16; /**< Threshhold for packet preemption, measured in bytes.
+                                                         Only packets which have at least MIN_SIZE bytes
+                                                         remaining to be read can be preempted. */
+#else
+	uint64_t min_size                     : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pko_reg_preempt_s         cn52xx;
+	struct cvmx_pko_reg_preempt_s         cn52xxp1;
+	struct cvmx_pko_reg_preempt_s         cn56xx;
+	struct cvmx_pko_reg_preempt_s         cn56xxp1;
+	struct cvmx_pko_reg_preempt_s         cn61xx;
+	struct cvmx_pko_reg_preempt_s         cn63xx;
+	struct cvmx_pko_reg_preempt_s         cn63xxp1;
+	struct cvmx_pko_reg_preempt_s         cn66xx;
+	struct cvmx_pko_reg_preempt_s         cn68xx;
+	struct cvmx_pko_reg_preempt_s         cn68xxp1;
+	struct cvmx_pko_reg_preempt_s         cnf71xx;
+};
+typedef union cvmx_pko_reg_preempt cvmx_pko_reg_preempt_t;
+
+/**
  * cvmx_pko_reg_queue_mode
  *
  * Notes:
@@ -2515,12 +3767,10 @@ typedef union cvmx_pko_reg_int_mask cvmx_pko_reg_int_mask_t;
  * 1     128    128B (16 words)
  * 2      64    256B (32 words)
  */
-union cvmx_pko_reg_queue_mode
-{
+union cvmx_pko_reg_queue_mode {
 	uint64_t u64;
-	struct cvmx_pko_reg_queue_mode_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_queue_mode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t mode                         : 2;  /**< # of queues = 256 >> MODE, 0 <= MODE <=2 */
 #else
@@ -2539,12 +3789,63 @@ union cvmx_pko_reg_queue_mode
 	struct cvmx_pko_reg_queue_mode_s      cn56xxp1;
 	struct cvmx_pko_reg_queue_mode_s      cn58xx;
 	struct cvmx_pko_reg_queue_mode_s      cn58xxp1;
+	struct cvmx_pko_reg_queue_mode_s      cn61xx;
 	struct cvmx_pko_reg_queue_mode_s      cn63xx;
 	struct cvmx_pko_reg_queue_mode_s      cn63xxp1;
+	struct cvmx_pko_reg_queue_mode_s      cn66xx;
+	struct cvmx_pko_reg_queue_mode_s      cn68xx;
+	struct cvmx_pko_reg_queue_mode_s      cn68xxp1;
+	struct cvmx_pko_reg_queue_mode_s      cnf71xx;
 };
 typedef union cvmx_pko_reg_queue_mode cvmx_pko_reg_queue_mode_t;
 
 /**
+ * cvmx_pko_reg_queue_preempt
+ *
+ * Notes:
+ * Per QID, setting both PREEMPTER=1 and PREEMPTEE=1 is illegal and sets only PREEMPTER=1.
+ * This CSR is used with PKO_MEM_QUEUE_PTRS and PKO_REG_QUEUE_PTRS1.  When programming queues, the
+ * programming sequence must first write PKO_REG_QUEUE_PREEMPT, then PKO_REG_QUEUE_PTRS1 and then
+ * PKO_MEM_QUEUE_PTRS for each queue.  Preemption is supported only on queues that are ultimately
+ * mapped to engines 0-7.  It is illegal to set preemptee or preempter for a queue that is ultimately
+ * mapped to engines 8-11.
+ *
+ * Also, PKO_REG_ENGINE_INFLIGHT must be at least 2 for any engine on which preemption is enabled.
+ *
+ * See the descriptions of PKO_MEM_QUEUE_PTRS for further explanation of queue programming.
+ */
+union cvmx_pko_reg_queue_preempt {
+	uint64_t u64;
+	struct cvmx_pko_reg_queue_preempt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_2_63                : 62;
+	uint64_t preemptee                    : 1;  /**< Allow this QID to be preempted.
+                                                         0=cannot be preempted, 1=can be preempted */
+	uint64_t preempter                    : 1;  /**< Preempts the servicing of packet on PID to
+                                                         allow this QID immediate servicing.  0=do not cause
+                                                         preemption, 1=cause preemption.  Per PID, at most
+                                                         1 QID can have this bit set. */
+#else
+	uint64_t preempter                    : 1;
+	uint64_t preemptee                    : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_pko_reg_queue_preempt_s   cn52xx;
+	struct cvmx_pko_reg_queue_preempt_s   cn52xxp1;
+	struct cvmx_pko_reg_queue_preempt_s   cn56xx;
+	struct cvmx_pko_reg_queue_preempt_s   cn56xxp1;
+	struct cvmx_pko_reg_queue_preempt_s   cn61xx;
+	struct cvmx_pko_reg_queue_preempt_s   cn63xx;
+	struct cvmx_pko_reg_queue_preempt_s   cn63xxp1;
+	struct cvmx_pko_reg_queue_preempt_s   cn66xx;
+	struct cvmx_pko_reg_queue_preempt_s   cn68xx;
+	struct cvmx_pko_reg_queue_preempt_s   cn68xxp1;
+	struct cvmx_pko_reg_queue_preempt_s   cnf71xx;
+};
+typedef union cvmx_pko_reg_queue_preempt cvmx_pko_reg_queue_preempt_t;
+
+/**
  * cvmx_pko_reg_queue_ptrs1
  *
  * Notes:
@@ -2555,12 +3856,10 @@ typedef union cvmx_pko_reg_queue_mode cvmx_pko_reg_queue_mode_t;
  * See the descriptions of PKO_MEM_QUEUE_PTRS and PKO_MEM_QUEUE_QOS for further explanation of queue
  * programming.
  */
-union cvmx_pko_reg_queue_ptrs1
-{
+union cvmx_pko_reg_queue_ptrs1 {
 	uint64_t u64;
-	struct cvmx_pko_reg_queue_ptrs1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_queue_ptrs1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t idx3                         : 1;  /**< [3] of Index (distance from head) in the queue array */
 	uint64_t qid7                         : 1;  /**< [7] of Queue ID */
@@ -2577,8 +3876,11 @@ union cvmx_pko_reg_queue_ptrs1
 	struct cvmx_pko_reg_queue_ptrs1_s     cn56xxp1;
 	struct cvmx_pko_reg_queue_ptrs1_s     cn58xx;
 	struct cvmx_pko_reg_queue_ptrs1_s     cn58xxp1;
+	struct cvmx_pko_reg_queue_ptrs1_s     cn61xx;
 	struct cvmx_pko_reg_queue_ptrs1_s     cn63xx;
 	struct cvmx_pko_reg_queue_ptrs1_s     cn63xxp1;
+	struct cvmx_pko_reg_queue_ptrs1_s     cn66xx;
+	struct cvmx_pko_reg_queue_ptrs1_s     cnf71xx;
 };
 typedef union cvmx_pko_reg_queue_ptrs1 cvmx_pko_reg_queue_ptrs1_t;
 
@@ -2592,12 +3894,10 @@ typedef union cvmx_pko_reg_queue_ptrs1 cvmx_pko_reg_queue_ptrs1_t;
  * The intended use is to initially write this CSR such that IDX=0 and INC=1.  Then, the entire
  * contents of a CSR memory can be read with consecutive CSR read commands.
  */
-union cvmx_pko_reg_read_idx
-{
+union cvmx_pko_reg_read_idx {
 	uint64_t u64;
-	struct cvmx_pko_reg_read_idx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_read_idx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t inc                          : 8;  /**< Increment to add to current index for next index */
 	uint64_t index                        : 8;  /**< Index to use for next memory CSR read */
@@ -2618,24 +3918,54 @@ union cvmx_pko_reg_read_idx
 	struct cvmx_pko_reg_read_idx_s        cn56xxp1;
 	struct cvmx_pko_reg_read_idx_s        cn58xx;
 	struct cvmx_pko_reg_read_idx_s        cn58xxp1;
+	struct cvmx_pko_reg_read_idx_s        cn61xx;
 	struct cvmx_pko_reg_read_idx_s        cn63xx;
 	struct cvmx_pko_reg_read_idx_s        cn63xxp1;
+	struct cvmx_pko_reg_read_idx_s        cn66xx;
+	struct cvmx_pko_reg_read_idx_s        cn68xx;
+	struct cvmx_pko_reg_read_idx_s        cn68xxp1;
+	struct cvmx_pko_reg_read_idx_s        cnf71xx;
 };
 typedef union cvmx_pko_reg_read_idx cvmx_pko_reg_read_idx_t;
 
 /**
+ * cvmx_pko_reg_throttle
+ *
+ * Notes:
+ * This CSR is used with PKO_MEM_THROTTLE_PIPE and PKO_MEM_THROTTLE_INT.  INT_MASK corresponds to the
+ * interfaces listed in the description for PKO_MEM_IPORT_PTRS[INT].  Set INT_MASK[N] to enable the
+ * updating of PKO_MEM_THROTTLE_PIPE and PKO_MEM_THROTTLE_INT counts for packets destined for
+ * interface N.  INT_MASK has no effect on the updates caused by CSR writes to PKO_MEM_THROTTLE_PIPE
+ * and PKO_MEM_THROTTLE_INT.  Note that this does not disable the throttle logic, just the updating of
+ * the interface counts.
+ */
+union cvmx_pko_reg_throttle {
+	uint64_t u64;
+	struct cvmx_pko_reg_throttle_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t int_mask                     : 32; /**< Mask to enable THROTTLE count updates per interface           NS */
+#else
+	uint64_t int_mask                     : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pko_reg_throttle_s        cn68xx;
+	struct cvmx_pko_reg_throttle_s        cn68xxp1;
+};
+typedef union cvmx_pko_reg_throttle cvmx_pko_reg_throttle_t;
+
+/**
  * cvmx_pko_reg_timestamp
  *
  * Notes:
  * None.
  *
  */
-union cvmx_pko_reg_timestamp
-{
+union cvmx_pko_reg_timestamp {
 	uint64_t u64;
-	struct cvmx_pko_reg_timestamp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pko_reg_timestamp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t wqe_word                     : 4;  /**< Specifies the 8-byte word in the WQE to which a PTP
                                                          timestamp is written.  Values 0 and 1 are illegal. */
@@ -2644,8 +3974,13 @@ union cvmx_pko_reg_timestamp
 	uint64_t reserved_4_63                : 60;
 #endif
 	} s;
+	struct cvmx_pko_reg_timestamp_s       cn61xx;
 	struct cvmx_pko_reg_timestamp_s       cn63xx;
 	struct cvmx_pko_reg_timestamp_s       cn63xxp1;
+	struct cvmx_pko_reg_timestamp_s       cn66xx;
+	struct cvmx_pko_reg_timestamp_s       cn68xx;
+	struct cvmx_pko_reg_timestamp_s       cn68xxp1;
+	struct cvmx_pko_reg_timestamp_s       cnf71xx;
 };
 typedef union cvmx_pko_reg_timestamp cvmx_pko_reg_timestamp_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-pko.c b/sys/contrib/octeon-sdk/cvmx-pko.c
index 74f250b..5ba4972 100644
--- a/sys/contrib/octeon-sdk/cvmx-pko.c
+++ b/sys/contrib/octeon-sdk/cvmx-pko.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -37,24 +37,19 @@
  * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
-
-
-
-
-
-
 /**
  * @file
  *
  * Support library for the hardware Packet Output unit.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <asm/octeon/cvmx.h>
 #include <asm/octeon/cvmx-config.h>
 #include <asm/octeon/cvmx-pko.h>
 #include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-cfg.h>
 #include <asm/octeon/cvmx-clock.h>
 #else
 #if !defined(__FreeBSD__) || !defined(_KERNEL)
@@ -67,14 +62,504 @@
 #endif
 #include "cvmx-pko.h"
 #include "cvmx-helper.h"
+#include "cvmx-helper-cfg.h"
 #endif
 
+/* #define PKO_DEBUG */
+
+#define CVMX_PKO_NQ_PER_PORT_MAX	32
+
 /**
  * Internal state of packet output
  */
-
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
 
+/*
+ * PKO port iterator
+ */
+#define CVMX_PKO_FOR_EACH_PORT_BEGIN	do { 					\
+	int XIT_pko_port;							\
+	for (XIT_pko_port = 0; XIT_pko_port < CVMX_HELPER_CFG_MAX_PKO_PORT;	\
+	    XIT_pko_port++)							\
+	{									\
+		if (__cvmx_helper_cfg_pko_queue_base(XIT_pko_port) !=		\
+	            CVMX_HELPER_CFG_INVALID_VALUE)
+
+#define CVMX_PKO_FOR_EACH_PORT_END	} /* for */			\
+					} while (0)
+
+/*
+ * @INTERNAL
+ *
+ * Get INT for a port
+ *
+ * @param interface 
+ * @param index 
+ * @return the INT value on success and -1 on error
+ */
+static int __cvmx_pko_int(int interface, int index)
+{
+    cvmx_helper_cfg_assert(interface < CVMX_HELPER_CFG_MAX_IFACE);
+    cvmx_helper_cfg_assert(index >= 0);
+
+    switch (interface)
+    {
+    case 0:
+        cvmx_helper_cfg_assert(index < 4);
+        return index;
+	break;
+    case 1:
+        cvmx_helper_cfg_assert(index == 0);
+        return 4;
+	break;
+    case 2:
+        cvmx_helper_cfg_assert(index < 4);
+        return index + 8;
+	break;
+    case 3:
+        cvmx_helper_cfg_assert(index < 4);
+        return index + 0xC;
+	break;
+    case 4:
+        cvmx_helper_cfg_assert(index < 4);
+        return index + 0x10;
+	break;
+    case 5:
+        cvmx_helper_cfg_assert(index < 256);
+        return 0x1C;
+	break;
+    case 6:
+        cvmx_helper_cfg_assert(index < 256);
+        return 0x1D;
+	break;
+    case 7:
+        cvmx_helper_cfg_assert(index < 32);
+        return 0x1E;
+	break;
+    case 8:
+        cvmx_helper_cfg_assert(index < 8);
+        return 0x1F;
+	break;
+    }
+
+    return -1;
+}
+
+int cvmx_pko_get_base_pko_port(int interface, int index)
+{
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+        return __cvmx_helper_cfg_pko_port_base(interface, index);
+    else
+        return cvmx_helper_get_ipd_port(interface, index);
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_pko_get_base_pko_port);
+#endif
+
+int cvmx_pko_get_num_pko_ports(int interface, int index)
+{
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+        return __cvmx_helper_cfg_pko_port_num(interface, index);
+    else
+        return 1;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_pko_get_num_pko_ports);
+#endif
+
+int cvmx_pko_get_base_queue(int port)
+{
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+    {
+        return __cvmx_helper_cfg_pko_queue_base(
+	    cvmx_helper_cfg_ipd2pko_port_base(port));
+    }
+    else
+        return cvmx_pko_get_base_queue_per_core(port, 0);
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_pko_get_base_queue);
+#endif
+
+/**
+ * For a given PKO port number, return the base output queue
+ * for the port.
+ *
+ * @param pko_port   PKO port number
+ * @return           Base output queue
+ */
+int cvmx_pko_get_base_queue_pkoid(int pko_port)
+{
+    return __cvmx_helper_cfg_pko_queue_base(pko_port);
+}
+
+/**
+ * For a given PKO port number, return the number of output queues
+ * for the port.
+ *
+ * @param pko_port	PKO port number
+ * @return		the number of output queues
+ */
+int cvmx_pko_get_num_queues_pkoid(int pko_port)
+{
+    return __cvmx_helper_cfg_pko_queue_num(pko_port);
+}
+
+int cvmx_pko_get_num_queues(int port)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+    {
+        return __cvmx_helper_cfg_pko_queue_num(
+	    cvmx_helper_cfg_ipd2pko_port_base(port));
+    }
+    else
+    {
+        if (port < 16)
+            return CVMX_PKO_QUEUES_PER_PORT_INTERFACE0;
+        else if (port < 32)
+            return CVMX_PKO_QUEUES_PER_PORT_INTERFACE1;
+        else if (port < 36)
+            return CVMX_PKO_QUEUES_PER_PORT_PCI;
+        else if (port < 40)
+            return CVMX_PKO_QUEUES_PER_PORT_LOOP;
+        else if (port < 42)
+            return CVMX_PKO_QUEUES_PER_PORT_SRIO0;
+        else if (port < 44)
+            return CVMX_PKO_QUEUES_PER_PORT_SRIO1;
+        else if (port < 46)
+            return CVMX_PKO_QUEUES_PER_PORT_SRIO2;
+    }
+    return 0;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_pko_get_num_queues);
+#endif
+
+#ifdef PKO_DEBUG
+/**
+ * Show queues for the internal ports
+ */
+void cvmx_pko_show_queue_map(void)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+    {
+	CVMX_PKO_FOR_EACH_PORT_BEGIN {
+	    cvmx_dprintf("pko_port %d (interface%d index%d) has %d queues (queue base = %d)\n",
+	        XIT_pko_port,
+		__cvmx_helper_cfg_pko_port_interface(XIT_pko_port),
+		__cvmx_helper_cfg_pko_port_index(XIT_pko_port),
+		__cvmx_helper_cfg_pko_queue_num(XIT_pko_port),
+	        __cvmx_helper_cfg_pko_queue_base(XIT_pko_port));
+	} CVMX_PKO_FOR_EACH_PORT_END;
+    }
+    else
+    {
+        int core, port;
+        int pko_output_ports;
+
+        pko_output_ports = 36;
+        cvmx_dprintf("port");
+        for(port = 0; port < pko_output_ports; port++)
+            cvmx_dprintf("%3d ", port);
+        cvmx_dprintf("\n");
+
+        for(core = 0; core < CVMX_MAX_CORES; core++)
+        {
+            cvmx_dprintf("\n%2d: ", core);
+            for(port = 0; port < pko_output_ports; port++)
+                cvmx_dprintf("%3d ",
+		    cvmx_pko_get_base_queue_per_core(port, core));
+        }
+        cvmx_dprintf("\n");
+
+    }
+}
+#endif /* PKO_DEBUG */
+
+/*
+ * Configure queues for an internal port.
+ * @INTERNAL
+ * @param pko_port PKO internal port number
+ * Note: o68 only
+ */
+static void __cvmx_pko_iport_config(int pko_port)
+{
+    int queue, base_queue, num_queues;
+    int static_priority_base;
+    int static_priority_end;
+    cvmx_pko_mem_iqueue_ptrs_t config;
+    uint64_t  *buf_ptr = NULL;
+    uint64_t priorities[CVMX_PKO_NQ_PER_PORT_MAX] = {
+        [0 ... CVMX_PKO_NQ_PER_PORT_MAX - 1] = 8 };
+
+    static_priority_base = -1;
+    static_priority_end = -1;
+    base_queue = __cvmx_helper_cfg_pko_queue_base(pko_port);
+    num_queues = __cvmx_helper_cfg_pko_queue_num(pko_port);
+
+    /* 
+     * Give the user a chance to override the per queue priorities.
+     */
+    if (cvmx_override_pko_queue_priority)
+        cvmx_override_pko_queue_priority(pko_port, &priorities[0]);
+
+    /*
+     * static queue priority validation
+     */
+    for (queue = 0; queue < num_queues; queue++)
+    {
+        if (static_priority_base == -1 &&
+	    priorities[queue] == CVMX_PKO_QUEUE_STATIC_PRIORITY)
+	    static_priority_base = queue;
+
+        if (static_priority_base != -1 &&
+	    static_priority_end == -1 &&
+	    priorities[queue] != CVMX_PKO_QUEUE_STATIC_PRIORITY &&
+	    queue)
+	        static_priority_end = queue - 1;
+        else if (static_priority_base != -1 &&
+	    static_priority_end == -1 &&
+	    queue == num_queues - 1)
+                static_priority_end = queue;  /* all queues are static priority */
+
+        /* 
+	 * Check to make sure all static priority queues are contiguous.
+	 * Also catches some cases of static priorites not starting from
+	 * queue 0.
+	 */
+        if (static_priority_end != -1 &&
+	    (int)queue > static_priority_end &&
+	    priorities[queue] == CVMX_PKO_QUEUE_STATIC_PRIORITY)
+        {
+            cvmx_dprintf("ERROR: __cvmx_pko_iport_config: Static priority "
+	        "queues aren't contiguous or don't start at base queue. "
+		"q: %d, eq: %d\n", (int)queue, static_priority_end);
+        }
+        if (static_priority_base > 0)
+        {
+            cvmx_dprintf("ERROR: __cvmx_pko_iport_config: Static priority "
+	        "queues don't start at base queue. sq: %d\n",
+		static_priority_base);
+        }
+    }
+
+    /*
+     * main loop to set the fields of CVMX_PKO_MEM_IQUEUE_PTRS for
+     * each queue
+     */
+    for (queue = 0; queue < num_queues; queue++)
+    {
+        config.u64 = 0;
+	config.s.index = queue;
+	config.s.qid = base_queue + queue;
+	config.s.ipid = pko_port;
+	config.s.tail = (queue == (num_queues - 1));
+        config.s.s_tail = (queue == static_priority_end);
+        config.s.static_p = (static_priority_base >= 0);
+        config.s.static_q = (queue <= static_priority_end);
+
+        /* 
+         * Convert the priority into an enable bit field.
+	 * Try to space the bits out evenly so the packet
+	 * don't get grouped up.
+         */
+        switch ((int)priorities[queue])
+        {
+            case 0: config.s.qos_mask = 0x00; break;
+            case 1: config.s.qos_mask = 0x01; break;
+            case 2: config.s.qos_mask = 0x11; break;
+            case 3: config.s.qos_mask = 0x49; break;
+            case 4: config.s.qos_mask = 0x55; break;
+            case 5: config.s.qos_mask = 0x57; break;
+            case 6: config.s.qos_mask = 0x77; break;
+            case 7: config.s.qos_mask = 0x7f; break;
+            case 8: config.s.qos_mask = 0xff; break;
+            case CVMX_PKO_QUEUE_STATIC_PRIORITY:
+                config.s.qos_mask = 0xff;
+                break;
+            default:
+                cvmx_dprintf("ERROR: __cvmx_pko_iport_config: "
+		    "Invalid priority %llu\n",
+		    (unsigned long long)priorities[queue]);
+                config.s.qos_mask = 0xff;
+                break;
+        }
+
+	/*
+	 * The command queues
+	 */
+        {
+            cvmx_cmd_queue_result_t cmd_res;
+
+	    cmd_res = cvmx_cmd_queue_initialize(
+	        CVMX_CMD_QUEUE_PKO(base_queue + queue),
+                CVMX_PKO_MAX_QUEUE_DEPTH,
+                CVMX_FPA_OUTPUT_BUFFER_POOL,
+                (CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE -
+		    CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST * 8));
+
+            if (cmd_res != CVMX_CMD_QUEUE_SUCCESS)
+            {
+	        switch (cmd_res)
+		{
+		    case CVMX_CMD_QUEUE_NO_MEMORY:
+                        cvmx_dprintf("ERROR: __cvmx_pko_iport_config: Unable to allocate output buffer.");
+                        break;
+		    case CVMX_CMD_QUEUE_ALREADY_SETUP:
+                        cvmx_dprintf("ERROR: __cvmx_pko_iport_config: Port already setup");
+                        break;
+		    case CVMX_CMD_QUEUE_INVALID_PARAM:
+		    default:
+                        cvmx_dprintf("ERROR: __cvmx_pko_iport_config: Command queue initialization failed.");
+                        break;
+		}
+		cvmx_dprintf(" pko_port%d base_queue%d num_queues%d queue%d.\n",
+		    pko_port, base_queue, num_queues, queue);
+            }
+
+            buf_ptr = (uint64_t*)cvmx_cmd_queue_buffer(
+	        CVMX_CMD_QUEUE_PKO(base_queue + queue));
+            config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr) >> 7;
+        }
+
+        CVMX_SYNCWS;
+        cvmx_write_csr(CVMX_PKO_MEM_IQUEUE_PTRS, config.u64);
+    }
+}
+
+/*
+ * Allocate queues for the PKO internal ports.
+ * @INTERNAL
+ * 
+ */
+static void __cvmx_pko_queue_alloc_o68(void)
+{
+    CVMX_PKO_FOR_EACH_PORT_BEGIN {
+	__cvmx_pko_iport_config(XIT_pko_port);
+    } CVMX_PKO_FOR_EACH_PORT_END;
+}
+
+/*
+ * Allocate memory for PKO engines.
+ *
+ * @param engine is the PKO engine ID.
+ * @return # of 2KB-chunks allocated to this PKO engine.
+ */
+static int __cvmx_pko_memory_per_engine_o68(int engine)
+{
+    /* CN68XX has 40KB to devide between the engines in 2KB chunks */
+    int max_engine;
+    int size_per_engine;
+    int size;
+
+    max_engine = __cvmx_helper_cfg_pko_max_engine();
+    size_per_engine = 40 / 2 / max_engine;
+
+    if (engine >= max_engine)
+    {
+        /* Unused engines get no space */
+        size = 0;
+    }
+    else if (engine == max_engine - 1)
+    {
+        /* The last engine gets all the space lost by rounding. This means
+            the ILK gets the most space */
+        size = 40 / 2 - engine * size_per_engine;
+    }
+    else
+    {
+        /* All other engines get the same space */
+        size = size_per_engine;
+    }
+
+    return size;
+}
+
+/*
+ * Setup one-to-one mapping between PKO iport and eport.
+ * @INTERNAL
+ */
+static void __cvmx_pko_port_map_o68(void)
+{
+    int i;
+    int interface, index;
+    cvmx_helper_interface_mode_t mode;
+    cvmx_pko_mem_iport_ptrs_t config;
+
+    /*
+     * Initialize every iport with the invalid eid.
+     */
+#define CVMX_O68_PKO_INVALID_EID	31
+    config.u64 = 0;
+    config.s.eid = CVMX_O68_PKO_INVALID_EID;
+    for (i = 0; i < CVMX_HELPER_CFG_MAX_PKO_PORT; i++)
+    {
+        config.s.ipid = i;
+        cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64);
+    }
+
+    /*
+     * Set up PKO_MEM_IPORT_PTRS
+     */
+    CVMX_PKO_FOR_EACH_PORT_BEGIN {
+	interface = __cvmx_helper_cfg_pko_port_interface(XIT_pko_port);
+	index = __cvmx_helper_cfg_pko_port_index(XIT_pko_port);
+	mode = cvmx_helper_interface_get_mode(interface);
+
+	if (mode == CVMX_HELPER_INTERFACE_MODE_DISABLED)
+	    continue;
+
+        config.s.ipid = XIT_pko_port;
+        config.s.qos_mask = 0xff;
+        config.s.crc = __cvmx_helper_get_has_fcs(interface);
+	config.s.min_pkt = __cvmx_helper_get_pko_padding(interface);
+        config.s.intr = __cvmx_pko_int(interface, index);
+	config.s.eid = __cvmx_helper_cfg_pko_port_eid(XIT_pko_port);
+        config.s.pipe = (mode == CVMX_HELPER_INTERFACE_MODE_LOOP) ? index :
+	    XIT_pko_port;
+        cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64);
+    } CVMX_PKO_FOR_EACH_PORT_END;
+}
+
+int __cvmx_pko_get_pipe(int interface, int index)
+{
+    /*
+     * the loopback ports do not have pipes
+     */
+    if (cvmx_helper_interface_get_mode(interface) ==
+        CVMX_HELPER_INTERFACE_MODE_LOOP)
+        return -1;
+    /*
+     * We use pko_port as the pipe. See __cvmx_pko_port_map_o68().
+     */
+    return cvmx_helper_get_pko_port(interface, index);
+}
+
+/*
+ * chip-specific setup
+ * @INTERNAL
+ */
+static void __cvmx_pko_chip_init(void)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+    {
+        __cvmx_pko_port_map_o68();
+        __cvmx_pko_queue_alloc_o68();
+    }
+    else
+    {
+        int i;
+        uint64_t priority = 8;
+
+        /*
+         * Initialize queues
+         */
+        for (i = 0; i < CVMX_PKO_MAX_OUTPUT_QUEUES; i++)
+            cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1,
+	        &priority);
+    }
+}
+
 /**
  * Call before any other calls to initialize the packet
  * output system.  This does chip global config, and should only be
@@ -83,41 +568,95 @@
 
 void cvmx_pko_initialize_global(void)
 {
-    int i;
-    uint64_t priority = 8;
     cvmx_pko_reg_cmd_buf_t config;
+    int i;
 
-    /* Set the size of the PKO command buffers to an odd number of 64bit
-        words. This allows the normal two word send to stay aligned and never
-        span a comamnd word buffer. */
+    /*
+     * Set the size of the PKO command buffers to an odd number of 64bit
+     * words. This allows the normal two word send to stay aligned and never
+     * span a command word buffer.
+     */
     config.u64 = 0;
     config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
     config.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE / 8 - 1;
-
     cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64);
 
-    for (i=0; i<CVMX_PKO_MAX_OUTPUT_QUEUES; i++)
-        cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1, &priority);
+    /*
+     * chip-specific setup.
+     */
+    __cvmx_pko_chip_init();
 
-    /* If we aren't using all of the queues optimize PKO's internal memory */
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
+    /*
+     * If we aren't using all of the queues optimize PKO's internal memory.
+     */
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) ||
+        OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) ||
+	OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
     {
-        int num_interfaces = cvmx_helper_get_number_of_interfaces();
-        int last_port = cvmx_helper_get_last_ipd_port(num_interfaces-1);
-        int max_queues = cvmx_pko_get_base_queue(last_port) + cvmx_pko_get_num_queues(last_port);
+        int num_interfaces;
+        int last_port;
+        int max_queues;
+
+        if (octeon_has_feature(OCTEON_FEATURE_PKND))
+	    max_queues = __cvmx_helper_cfg_pko_max_queue();
+	else
+	{
+	    num_interfaces = cvmx_helper_get_number_of_interfaces();
+	    last_port = cvmx_helper_get_last_ipd_port(num_interfaces-1);
+            max_queues = cvmx_pko_get_base_queue(last_port) + 
+	        cvmx_pko_get_num_queues(last_port);
+        }
+
         if (OCTEON_IS_MODEL(OCTEON_CN38XX))
         {
             if (max_queues <= 32)
                 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2);
             else if (max_queues <= 64)
                 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1);
+            else
+                cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 0);
         }
         else
         {
-            if (max_queues <= 64)
+            if (OCTEON_IS_MODEL(OCTEON_CN68XX) && max_queues <= 32)
+                cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 3);
+            else if (max_queues <= 64)
                 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2);
             else if (max_queues <= 128)
                 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1);
+            else
+                cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 0);
+            if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+	    {
+                for (i = 0; i < 2; i++)
+                {
+                    cvmx_pko_reg_engine_storagex_t engine_storage;
+
+#define PKO_ASSIGN_ENGINE_STORAGE(index)                        \
+        engine_storage.s.engine##index =                        \
+            __cvmx_pko_memory_per_engine_o68(16 * i + (index))
+
+                    engine_storage.u64 = 0;
+                    PKO_ASSIGN_ENGINE_STORAGE(0);
+                    PKO_ASSIGN_ENGINE_STORAGE(1);
+                    PKO_ASSIGN_ENGINE_STORAGE(2);
+                    PKO_ASSIGN_ENGINE_STORAGE(3);
+                    PKO_ASSIGN_ENGINE_STORAGE(4);
+                    PKO_ASSIGN_ENGINE_STORAGE(5);
+                    PKO_ASSIGN_ENGINE_STORAGE(6);
+                    PKO_ASSIGN_ENGINE_STORAGE(7);
+                    PKO_ASSIGN_ENGINE_STORAGE(8);
+                    PKO_ASSIGN_ENGINE_STORAGE(9);
+                    PKO_ASSIGN_ENGINE_STORAGE(10);
+                    PKO_ASSIGN_ENGINE_STORAGE(11);
+                    PKO_ASSIGN_ENGINE_STORAGE(12);
+                    PKO_ASSIGN_ENGINE_STORAGE(13);
+                    PKO_ASSIGN_ENGINE_STORAGE(14);
+                    PKO_ASSIGN_ENGINE_STORAGE(15);
+                    cvmx_write_csr(CVMX_PKO_REG_ENGINE_STORAGEX(i),
+                                   engine_storage.u64);
+		}
+            }
         }
     }
 }
@@ -149,13 +688,15 @@ void cvmx_pko_enable(void)
     if (flags.s.ena_pko)
         cvmx_dprintf("Warning: Enabling PKO when PKO already enabled.\n");
 
-    flags.s.ena_dwb = 1;
+    flags.s.ena_dwb = cvmx_helper_cfg_opt_get(CVMX_HELPER_CFG_OPT_USE_DWB);
     flags.s.ena_pko = 1;
-    flags.s.store_be =1;  /* always enable big endian for 3-word command. Does nothing for 2-word */
+    flags.s.store_be =1;  /*
+    			   * always enable big endian for 3-word command.
+			   * Does nothing for 2-word.
+    			   */
     cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64);
 }
 
-
 /**
  * Disables the packet output. Does not affect any configuration.
  */
@@ -167,7 +708,6 @@ void cvmx_pko_disable(void)
     cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
 }
 
-
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
 /**
  * @INTERNAL
@@ -181,40 +721,53 @@ static void __cvmx_pko_reset(void)
     cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
 }
 
-
 /**
  * Shutdown and free resources required by packet output.
  */
 void cvmx_pko_shutdown(void)
 {
-    cvmx_pko_mem_queue_ptrs_t config;
     int queue;
 
     cvmx_pko_disable();
 
-    for (queue=0; queue<CVMX_PKO_MAX_OUTPUT_QUEUES; queue++)
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
     {
-        config.u64          = 0;
-        config.s.tail       = 1;
-        config.s.index      = 0;
-        config.s.port       = CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID;
-        config.s.queue      = queue & 0x7f;
-        config.s.qos_mask   = 0;
-        config.s.buf_ptr    = 0;
-        if (!OCTEON_IS_MODEL(OCTEON_CN3XXX))
+	cvmx_pko_mem_iqueue_ptrs_t config;
+	config.u64 = 0;
+        for (queue = 0; queue < CVMX_PKO_MAX_OUTPUT_QUEUES; queue++)
+	{
+	    config.s.qid = queue;
+            cvmx_write_csr(CVMX_PKO_MEM_IQUEUE_PTRS, config.u64);
+            cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_PKO(queue));
+	}
+    }
+    else
+    {
+        cvmx_pko_mem_queue_ptrs_t config;
+        for (queue=0; queue<CVMX_PKO_MAX_OUTPUT_QUEUES; queue++)
         {
-            cvmx_pko_reg_queue_ptrs1_t config1;
-            config1.u64 = 0;
-            config1.s.qid7 = queue >> 7;
-            cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);
+            config.u64          = 0;
+            config.s.tail       = 1;
+            config.s.index      = 0;
+            config.s.port       = CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID;
+            config.s.queue      = queue & 0x7f;
+            config.s.qos_mask   = 0;
+            config.s.buf_ptr    = 0;
+            if (!OCTEON_IS_MODEL(OCTEON_CN3XXX))
+            {
+                cvmx_pko_reg_queue_ptrs1_t config1;
+                config1.u64 = 0;
+                config1.s.qid7 = queue >> 7;
+                cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);
+            }
+            cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);
+            cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_PKO(queue));
         }
-        cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);
-        cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_PKO(queue));
     }
+
     __cvmx_pko_reset();
 }
 
-
 /**
  * Configure a output port and the associated queues for use.
  *
@@ -232,7 +785,8 @@ void cvmx_pko_shutdown(void)
  *                   queues have higher priority than higher numbered queues.
  *                   There must be num_queues elements in the array.
  */
-cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, uint64_t num_queues, const uint64_t priority[])
+cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue,
+    uint64_t num_queues, const uint64_t priority[])
 {
     cvmx_pko_status_t          result_code;
     uint64_t                   queue;
@@ -241,57 +795,77 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, uint6
     int static_priority_base = -1;
     int static_priority_end = -1;
 
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+        return CVMX_PKO_SUCCESS;
 
-    if ((port >= CVMX_PKO_NUM_OUTPUT_PORTS) && (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID))
+    if ((port >= CVMX_PKO_NUM_OUTPUT_PORTS) &&
+        (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID))
     {
-        cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid port %llu\n", (unsigned long long)port);
+        cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid port %llu\n",
+	    (unsigned long long)port);
         return CVMX_PKO_INVALID_PORT;
     }
 
     if (base_queue + num_queues > CVMX_PKO_MAX_OUTPUT_QUEUES)
     {
-        cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid queue range %llu\n", (unsigned long long)(base_queue + num_queues));
+        cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid queue range %llu\n",
+	    (unsigned long long)(base_queue + num_queues));
         return CVMX_PKO_INVALID_QUEUE;
     }
 
     if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)
     {
-        /* Validate the static queue priority setup and set static_priority_base and static_priority_end
-        ** accordingly. */
+        /* 
+	 * Validate the static queue priority setup and set
+	 * static_priority_base and static_priority_end accordingly.
+	 */
         for (queue = 0; queue < num_queues; queue++)
         {
             /* Find first queue of static priority */
-            if (static_priority_base == -1 && priority[queue] == CVMX_PKO_QUEUE_STATIC_PRIORITY)
+            if (static_priority_base == -1 && priority[queue] ==
+	        CVMX_PKO_QUEUE_STATIC_PRIORITY)
                 static_priority_base = queue;
             /* Find last queue of static priority */
-            if (static_priority_base != -1 && static_priority_end == -1 && priority[queue] != CVMX_PKO_QUEUE_STATIC_PRIORITY && queue)
+            if (static_priority_base != -1 && static_priority_end == -1 && 
+	        priority[queue] != CVMX_PKO_QUEUE_STATIC_PRIORITY && queue)
                 static_priority_end = queue - 1;
-            else if (static_priority_base != -1 && static_priority_end == -1 && queue == num_queues - 1)
-                static_priority_end = queue;  /* all queues are static priority */
-            /* Check to make sure all static priority queues are contiguous.  Also catches some cases of
-            ** static priorites not starting at queue 0. */
-            if (static_priority_end != -1 && (int)queue > static_priority_end && priority[queue] == CVMX_PKO_QUEUE_STATIC_PRIORITY)
+            else if (static_priority_base != -1 && static_priority_end == -1 &&
+	        queue == num_queues - 1)
+                static_priority_end = queue; /* all queues're static priority */
+
+            /* 
+	     * Check to make sure all static priority queues are contiguous.
+	     * Also catches some cases of static priorites not starting at
+	     * queue 0.
+	     */
+            if (static_priority_end != -1 && (int)queue > static_priority_end &&
+	        priority[queue] == CVMX_PKO_QUEUE_STATIC_PRIORITY)
             {
-                cvmx_dprintf("ERROR: cvmx_pko_config_port: Static priority queues aren't contiguous or don't start at base queue. q: %d, eq: %d\n", (int)queue, static_priority_end);
+                cvmx_dprintf("ERROR: cvmx_pko_config_port: Static priority "
+		    "queues aren't contiguous or don't start at base queue. "
+		    "q: %d, eq: %d\n", (int)queue, static_priority_end);
                 return CVMX_PKO_INVALID_PRIORITY;
             }
         }
         if (static_priority_base > 0)
         {
-            cvmx_dprintf("ERROR: cvmx_pko_config_port: Static priority queues don't start at base queue. sq: %d\n", static_priority_base);
+            cvmx_dprintf("ERROR: cvmx_pko_config_port: Static priority queues "
+	        "don't start at base queue. sq: %d\n", static_priority_base);
             return CVMX_PKO_INVALID_PRIORITY;
         }
-#if 0
-        cvmx_dprintf("Port %d: Static priority queue base: %d, end: %d\n", port, static_priority_base, static_priority_end);
-#endif
     }
-    /* At this point, static_priority_base and static_priority_end are either both -1,
-    ** or are valid start/end queue numbers */
+
+    /*
+     * At this point, static_priority_base and static_priority_end are either
+     * both -1, or are valid start/end queue numbers
+     */
 
     result_code = CVMX_PKO_SUCCESS;
 
 #ifdef PKO_DEBUG
-    cvmx_dprintf("num queues: %d (%lld,%lld)\n", num_queues, CVMX_PKO_QUEUES_PER_PORT_INTERFACE0, CVMX_PKO_QUEUES_PER_PORT_INTERFACE1);
+    cvmx_dprintf("num queues: %d (%lld,%lld)\n", (int)num_queues,
+        (unsigned long long)CVMX_PKO_QUEUES_PER_PORT_INTERFACE0,
+	(unsigned long long)CVMX_PKO_QUEUES_PER_PORT_INTERFACE1);
 #endif
 
     for (queue = 0; queue < num_queues; queue++)
@@ -311,8 +885,10 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, uint6
         config.s.static_p   = static_priority_base >= 0;
         config.s.static_q   = (int)queue <= static_priority_end;
         config.s.s_tail     = (int)queue == static_priority_end;
-        /* Convert the priority into an enable bit field. Try to space the bits
-            out evenly so the packet don't get grouped up */
+        /*
+	 * Convert the priority into an enable bit field. Try to space the bits
+	 * out evenly so the packet don't get grouped up
+	 */
         switch ((int)priority[queue])
         {
             case 0: config.s.qos_mask = 0x00; break;
@@ -328,7 +904,8 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, uint6
                 config.s.qos_mask = 0xff;
                 break;
             default:
-                cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid priority %llu\n", (unsigned long long)priority[queue]);
+                cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid priority %llu\n",
+		    (unsigned long long)priority[queue]);
                 config.s.qos_mask = 0xff;
                 result_code = CVMX_PKO_INVALID_PRIORITY;
                 break;
@@ -336,28 +913,34 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, uint6
 
         if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)
         {
-            cvmx_cmd_queue_result_t cmd_res = cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_PKO(base_queue + queue),
-                                                                        CVMX_PKO_MAX_QUEUE_DEPTH,
-                                                                        CVMX_FPA_OUTPUT_BUFFER_POOL,
-                                                                        CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE - CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST*8);
+            cvmx_cmd_queue_result_t cmd_res = cvmx_cmd_queue_initialize(
+	        CVMX_CMD_QUEUE_PKO(base_queue + queue),
+                CVMX_PKO_MAX_QUEUE_DEPTH,
+                CVMX_FPA_OUTPUT_BUFFER_POOL,
+                CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE -
+		    CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST*8);
             if (cmd_res != CVMX_CMD_QUEUE_SUCCESS)
             {
 	        switch (cmd_res)
 		{
 		    case CVMX_CMD_QUEUE_NO_MEMORY:
-                        cvmx_dprintf("ERROR: cvmx_pko_config_port: Unable to allocate output buffer.\n");
+                        cvmx_dprintf("ERROR: cvmx_pko_config_port: "
+			    "Unable to allocate output buffer.\n");
                         return(CVMX_PKO_NO_MEMORY);
 		    case CVMX_CMD_QUEUE_ALREADY_SETUP:
-                        cvmx_dprintf("ERROR: cvmx_pko_config_port: Port already setup.\n");
+                        cvmx_dprintf("ERROR: cvmx_pko_config_port: "
+			    "Port already setup.\n");
                         return(CVMX_PKO_PORT_ALREADY_SETUP);
 		    case CVMX_CMD_QUEUE_INVALID_PARAM:
 		    default:
-                        cvmx_dprintf("ERROR: cvmx_pko_config_port: Command queue initialization failed.\n");
+                        cvmx_dprintf("ERROR: cvmx_pko_config_port: "
+			    "Command queue initialization failed.\n");
                         return(CVMX_PKO_CMD_QUEUE_INIT_ERROR);
 		}
             }
 
-            buf_ptr = (uint64_t*)cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_PKO(base_queue + queue));
+            buf_ptr = (uint64_t*)cvmx_cmd_queue_buffer(
+	        CVMX_CMD_QUEUE_PKO(base_queue + queue));
             config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr);
         }
         else
@@ -375,33 +958,6 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, uint6
     return result_code;
 }
 
-#ifdef PKO_DEBUG
-/**
- * Show map of ports -> queues for different cores.
- */
-void cvmx_pko_show_queue_map()
-{
-    int core, port;
-    int pko_output_ports = 36;
-
-    cvmx_dprintf("port");
-    for(port=0; port<pko_output_ports; port++)
-        cvmx_dprintf("%3d ", port);
-    cvmx_dprintf("\n");
-
-    for(core=0; core<CVMX_MAX_CORES; core++)
-    {
-        cvmx_dprintf("\n%2d: ", core);
-        for(port=0; port<pko_output_ports; port++)
-        {
-            cvmx_dprintf("%3d ", cvmx_pko_get_base_queue_per_core(port, core));
-        }
-    }
-    cvmx_dprintf("\n");
-}
-#endif
-
-
 /**
  * Rate limit a PKO port to a max packets/sec. This function is only
  * supported on CN51XX and higher, excluding CN58XX.
@@ -420,20 +976,21 @@ int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst)
 
     pko_mem_port_rate0.u64 = 0;
     pko_mem_port_rate0.s.pid = port;
-    pko_mem_port_rate0.s.rate_pkt = cvmx_clock_get_rate(CVMX_CLOCK_SCLK) / packets_s / 16;
+    pko_mem_port_rate0.s.rate_pkt =
+        cvmx_clock_get_rate(CVMX_CLOCK_SCLK) / packets_s / 16;
     /* No cost per word since we are limited by packets/sec, not bits/sec */
     pko_mem_port_rate0.s.rate_word = 0;
 
     pko_mem_port_rate1.u64 = 0;
     pko_mem_port_rate1.s.pid = port;
-    pko_mem_port_rate1.s.rate_lim = ((uint64_t)pko_mem_port_rate0.s.rate_pkt * burst) >> 8;
+    pko_mem_port_rate1.s.rate_lim = 
+        ((uint64_t)pko_mem_port_rate0.s.rate_pkt * burst) >> 8;
 
     cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);
     cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);
     return 0;
 }
 
-
 /**
  * Rate limit a PKO port to a max bits/sec. This function is only
  * supported on CN51XX and higher, excluding CN58XX.
@@ -471,4 +1028,3 @@ int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst)
 }
 
 #endif /* CVMX_ENABLE_PKO_FUNCTIONS */
-
diff --git a/sys/contrib/octeon-sdk/cvmx-pko.h b/sys/contrib/octeon-sdk/cvmx-pko.h
index f7825b4..97cf76b 100644
--- a/sys/contrib/octeon-sdk/cvmx-pko.h
+++ b/sys/contrib/octeon-sdk/cvmx-pko.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -67,7 +67,7 @@
  * - PKO 3 word commands are now supported. Use
  *   cvmx_pko_send_packet_finish3().
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 
@@ -77,6 +77,12 @@
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include "cvmx-config.h"
 #include "cvmx-pko-defs.h"
+#include <asm/octeon/cvmx-fau.h>
+#include <asm/octeon/cvmx-fpa.h>
+#include <asm/octeon/cvmx-pow.h>
+#include <asm/octeon/cvmx-cmd-queue.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-cfg.h>
 #else
 # ifndef CVMX_DONT_INCLUDE_CONFIG
 #  include "executive-config.h"
@@ -84,13 +90,14 @@
 #   include "cvmx-config.h"
 #  endif
 # endif
-#endif
-
-
 #include "cvmx-fau.h"
 #include "cvmx-fpa.h"
 #include "cvmx-pow.h"
 #include "cvmx-cmd-queue.h"
+#include "cvmx-helper.h"
+#include "cvmx-helper-util.h"
+#include "cvmx-helper-cfg.h"
+#endif
 
 /* Adjust the command buffer size by 1 word so that in the case of using only
 ** two word PKO commands no command words stradle buffers.  The useful values
@@ -102,8 +109,18 @@ extern "C" {
 #endif
 
 #define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256
-#define CVMX_PKO_MAX_OUTPUT_QUEUES      ((OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 256 : 128)
-#define CVMX_PKO_NUM_OUTPUT_PORTS       ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 44 : 40)
+#define CVMX_PKO_MAX_OUTPUT_QUEUES      ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \
+					  OCTEON_IS_MODEL(OCTEON_CN3010) || \
+					  OCTEON_IS_MODEL(OCTEON_CN3005) || \
+					  OCTEON_IS_MODEL(OCTEON_CN50XX)) ? \
+					  32 :				    \
+					 (OCTEON_IS_MODEL(OCTEON_CN58XX) || \
+					  OCTEON_IS_MODEL(OCTEON_CN56XX) || \
+					  OCTEON_IS_MODEL(OCTEON_CN52XX) || \
+					  OCTEON_IS_MODEL(OCTEON_CN6XXX) || \
+					  OCTEON_IS_MODEL(OCTEON_CNF7XXX)) ? \
+					  256 : 128)
+#define CVMX_PKO_NUM_OUTPUT_PORTS       ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 44 : (OCTEON_IS_MODEL(OCTEON_CN66XX) ? 46 : 40))
 #define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63 /* use this for queues that are not used */
 #define CVMX_PKO_QUEUE_STATIC_PRIORITY  9
 #define CVMX_PKO_ILLEGAL_QUEUE  0xFFFF
@@ -127,7 +144,7 @@ typedef enum
 {
     CVMX_PKO_LOCK_NONE = 0,         /**< PKO doesn't do any locking. It is the responsibility
                                         of the application to make sure that no other core is
-                                        accessing the same queue at the smae time */
+                                        accessing the same queue at the same time */
     CVMX_PKO_LOCK_ATOMIC_TAG = 1,   /**< PKO performs an atomic tagswitch to insure exclusive
                                         access to the output queue. This will maintain
                                         packet ordering on output */
@@ -139,9 +156,9 @@ typedef enum
 
 typedef struct
 {
-    uint32_t    packets;
-    uint64_t    octets;
-  uint64_t doorbell;
+    uint32_t packets;
+    uint64_t octets;
+    uint64_t doorbell;
 } cvmx_pko_port_status_t;
 
 /**
@@ -157,8 +174,8 @@ typedef union
         uint64_t            is_io       : 1;    /**< Must be one */
         uint64_t            did         : 8;    /**< The ID of the device on the non-coherent bus */
         uint64_t            reserved2   : 4;    /**< Must be zero */
-        uint64_t            reserved3   :18;    /**< Must be zero */
-        uint64_t            port        : 6;    /**< The hardware likes to have the output port in addition to the output queue */
+        uint64_t            reserved3   :15;    /**< Must be zero */
+        uint64_t            port        : 9;    /**< The hardware must have the output port in addition to the output queue */
         uint64_t            queue       : 9;    /**< The output queue to send the packet to (0-127 are legal) */
         uint64_t            reserved4   : 3;    /**< Must be zero */
    } s;
@@ -233,7 +250,6 @@ extern void cvmx_pko_disable(void);
 
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
 extern void cvmx_pko_shutdown(void);
-#endif
 
 /**
  * Configure a output port and the associated queues for use.
@@ -255,23 +271,34 @@ extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue
  * to its pending list.  This command includes the required
  * CVMX_SYNCWS before the doorbell ring.
  *
- * @param port   Port the packet is for
+ * WARNING: This function may have to look up the proper PKO port in
+ * the IPD port to PKO port map, and is thus slower than calling
+ * cvmx_pko_doorbell_pkoid() directly if the PKO port identifier is
+ * known.
+ *
+ * @param ipd_port   The IPD port corresponding the to pko port the packet is for
  * @param queue  Queue the packet is for
  * @param len    Length of the command in 64 bit words
  */
-static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue, uint64_t len)
+static inline void cvmx_pko_doorbell(uint64_t ipd_port, uint64_t queue, uint64_t len)
 {
    cvmx_pko_doorbell_address_t ptr;
+   uint64_t pko_port;
+
+   pko_port = ipd_port;
+   if (octeon_has_feature(OCTEON_FEATURE_PKND))
+	pko_port = cvmx_helper_cfg_ipd2pko_port_base(ipd_port);
 
    ptr.u64          = 0;
    ptr.s.mem_space  = CVMX_IO_SEG;
    ptr.s.did        = CVMX_OCT_DID_PKT_SEND;
    ptr.s.is_io      = 1;
-   ptr.s.port       = port;
+   ptr.s.port       = pko_port;
    ptr.s.queue      = queue;
    CVMX_SYNCWS;  /* Need to make sure output queue data is in DRAM before doorbell write */
    cvmx_write_io(ptr.u64, len);
 }
+#endif
 
 
 /**
@@ -287,7 +314,7 @@ static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue, uint64_t len
  * - CVMX_PKO_LOCK_NONE
  *      - PKO doesn't do any locking. It is the responsibility
  *          of the application to make sure that no other core
- *          is accessing the same queue at the smae time.
+ *          is accessing the same queue at the same time.
  * - CVMX_PKO_LOCK_ATOMIC_TAG
  *      - PKO performs an atomic tagswitch to insure exclusive
  *          access to the output queue. This will maintain
@@ -301,7 +328,8 @@ static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue, uint64_t len
  * NOTE: If atomic locking is used, the POW entry CANNOT be
  * descheduled, as it does not contain a valid WQE pointer.
  *
- * @param port   Port to send it on
+ * @param port   Port to send it on, this can be either IPD port or PKO
+ * 		 port.
  * @param queue  Queue to use
  * @param use_locking
  *               CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or CVMX_PKO_LOCK_CMD_QUEUE
@@ -321,13 +349,19 @@ static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue, c
     }
 }
 
+#define cvmx_pko_send_packet_prepare_pkoid	cvmx_pko_send_packet_prepare
 
 /**
  * Complete packet output. cvmx_pko_send_packet_prepare() must be called exactly once before this,
  * and the same parameters must be passed to both cvmx_pko_send_packet_prepare() and
  * cvmx_pko_send_packet_finish().
  *
- * @param port   Port to send it on
+ * WARNING: This function may have to look up the proper PKO port in
+ * the IPD port to PKO port map, and is thus slower than calling
+ * cvmx_pko_send_packet_finish_pkoid() directly if the PKO port
+ * identifier is known.
+ *
+ * @param ipd_port   The IPD port corresponding the to pko port the packet is for
  * @param queue  Queue to use
  * @param pko_command
  *               PKO HW command word
@@ -337,7 +371,7 @@ static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue, c
  *
  * @return returns CVMX_PKO_SUCCESS on success, or error code on failure of output
  */
-static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(uint64_t port, uint64_t queue,
+static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(uint64_t ipd_port, uint64_t queue,
                                         cvmx_pko_command_word0_t pko_command,
                                         cvmx_buf_ptr_t packet, cvmx_pko_lock_t use_locking)
 {
@@ -350,7 +384,7 @@ static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(uint64_t port, uint6
                                    packet.u64);
     if (cvmx_likely(result == CVMX_CMD_QUEUE_SUCCESS))
     {
-        cvmx_pko_doorbell(port, queue, 2);
+        cvmx_pko_doorbell(ipd_port, queue, 2);
         return CVMX_PKO_SUCCESS;
     }
     else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) || (result == CVMX_CMD_QUEUE_FULL))
@@ -369,7 +403,12 @@ static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(uint64_t port, uint6
  * and the same parameters must be passed to both cvmx_pko_send_packet_prepare() and
  * cvmx_pko_send_packet_finish().
  *
- * @param port   Port to send it on
+ * WARNING: This function may have to look up the proper PKO port in
+ * the IPD port to PKO port map, and is thus slower than calling
+ * cvmx_pko_send_packet_finish3_pkoid() directly if the PKO port
+ * identifier is known.
+ *
+ * @param ipd_port   The IPD port corresponding the to pko port the packet is for
  * @param queue  Queue to use
  * @param pko_command
  *               PKO HW command word
@@ -380,7 +419,7 @@ static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(uint64_t port, uint6
  *
  * @return returns CVMX_PKO_SUCCESS on success, or error code on failure of output
  */
-static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3(uint64_t port, uint64_t queue,
+static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3(uint64_t ipd_port, uint64_t queue,
                                         cvmx_pko_command_word0_t pko_command,
                                         cvmx_buf_ptr_t packet, uint64_t addr, cvmx_pko_lock_t use_locking)
 {
@@ -394,7 +433,7 @@ static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3(uint64_t port, uint
                                    addr);
     if (cvmx_likely(result == CVMX_CMD_QUEUE_SUCCESS))
     {
-        cvmx_pko_doorbell(port, queue, 3);
+        cvmx_pko_doorbell(ipd_port, queue, 3);
         return CVMX_PKO_SUCCESS;
     }
     else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) || (result == CVMX_CMD_QUEUE_FULL))
@@ -408,6 +447,22 @@ static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3(uint64_t port, uint
 }
 
 /**
+ * Get the first pko_port for the (interface, index)
+ *
+ * @param interface
+ * @param index
+ */
+extern int cvmx_pko_get_base_pko_port(int interface, int index);
+
+/**
+ * Get the number of pko_ports for the (interface, index)
+ *
+ * @param interface
+ * @param index
+ */
+extern int cvmx_pko_get_num_pko_ports(int interface, int index);
+
+/**
  * Return the pko output queue associated with a port and a specific core.
  * In normal mode (PKO lockless operation is disabled), the value returned
  * is the base queue.
@@ -415,10 +470,19 @@ static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3(uint64_t port, uint
  * @param port   Port number
  * @param core   Core to get queue for
  *
- * @return Core-specific output queue
+ * @return Core-specific output queue and -1 on error.
+ *
+ * Note: This function is invalid for o68.
  */
 static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
 {
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+    {
+	cvmx_dprintf("cvmx_pko_get_base_queue_per_core() not"
+	    "supported starting from o68!\n");
+        return -1;
+    }
+
 #ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
     #define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 16
 #endif
@@ -435,6 +499,11 @@ static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
         port with two ports gives us four queues, one for each mailbox */
     #define CVMX_PKO_QUEUES_PER_PORT_SRIO1 2
 #endif
+#ifndef CVMX_PKO_QUEUES_PER_PORT_SRIO2
+    /* We use two queues per port for SRIO2. Having two queues per
+        port with two ports gives us four queues, one for each mailbox */
+    #define CVMX_PKO_QUEUES_PER_PORT_SRIO2 2
+#endif
     if (port < CVMX_PKO_MAX_PORTS_INTERFACE0)
         return port * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + core;
     else if (port >=16 && port < 16 + CVMX_PKO_MAX_PORTS_INTERFACE1)
@@ -462,6 +531,13 @@ static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
                4 * CVMX_PKO_QUEUES_PER_PORT_LOOP +
 	       2 * CVMX_PKO_QUEUES_PER_PORT_SRIO0 +
 	       (port-42) * CVMX_PKO_QUEUES_PER_PORT_SRIO1;
+    else if ((port >= 44) && (port < 46))
+        return CVMX_PKO_MAX_PORTS_INTERFACE0 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
+               CVMX_PKO_MAX_PORTS_INTERFACE1 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
+               4 * CVMX_PKO_QUEUES_PER_PORT_PCI +
+               4 * CVMX_PKO_QUEUES_PER_PORT_LOOP +
+	       4 * CVMX_PKO_QUEUES_PER_PORT_SRIO0 +
+	       (port-44) * CVMX_PKO_QUEUES_PER_PORT_SRIO2;
     else
         /* Given the limit on the number of ports we can map to
          * CVMX_MAX_OUTPUT_QUEUES_STATIC queues (currently 256,
@@ -474,75 +550,98 @@ static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
  * For a given port number, return the base pko output queue
  * for the port.
  *
- * @param port   Port number
+ * @param port   IPD port number
  * @return Base output queue
  */
-static inline int cvmx_pko_get_base_queue(int port)
-{
-    return cvmx_pko_get_base_queue_per_core(port, 0);
-}
+extern int cvmx_pko_get_base_queue(int port);
 
 /**
  * For a given port number, return the number of pko output queues.
  *
- * @param port   Port number
+ * @param port   IPD port number
  * @return Number of output queues
  */
-static inline int cvmx_pko_get_num_queues(int port)
-{
-    if (port < 16)
-        return CVMX_PKO_QUEUES_PER_PORT_INTERFACE0;
-    else if (port<32)
-        return CVMX_PKO_QUEUES_PER_PORT_INTERFACE1;
-    else if (port<36)
-        return CVMX_PKO_QUEUES_PER_PORT_PCI;
-    else if (port<40)
-        return CVMX_PKO_QUEUES_PER_PORT_LOOP;
-    else if (port<42)
-        return CVMX_PKO_QUEUES_PER_PORT_SRIO0;
-    else if (port<44)
-        return CVMX_PKO_QUEUES_PER_PORT_SRIO1;
-    else
-        return 0;
-}
+extern int cvmx_pko_get_num_queues(int port);
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
 
 /**
  * Get the status counters for a port.
  *
- * @param port_num Port number to get statistics for.
+ * @param ipd_port Port number (ipd_port) to get statistics for.
  * @param clear    Set to 1 to clear the counters after they are read
  * @param status   Where to put the results.
+ *
+ * Note:
+ *     - Only the doorbell for the base queue of the ipd_port is
+ *       collected.
+ *     - Retrieving the stats involves writing the index through
+ *       CVMX_PKO_REG_READ_IDX and reading the stat CSRs, in that
+ *       order. It is not MP-safe and caller should guarantee
+ *       atomicity.
  */
-static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear, cvmx_pko_port_status_t *status)
+static inline void cvmx_pko_get_port_status(uint64_t ipd_port, uint64_t clear,
+    cvmx_pko_port_status_t *status)
 {
     cvmx_pko_reg_read_idx_t pko_reg_read_idx;
     cvmx_pko_mem_count0_t pko_mem_count0;
     cvmx_pko_mem_count1_t pko_mem_count1;
+    int pko_port, port_base, port_limit;
+
+    if (octeon_has_feature(OCTEON_FEATURE_PKND)) {
+        int interface = cvmx_helper_get_interface_num(ipd_port);
+        int index = cvmx_helper_get_interface_index_num(ipd_port);
+        port_base = cvmx_helper_get_pko_port(interface, index);
+        if (port_base == -1)
+            cvmx_dprintf("Warning: Invalid port_base\n");
+	port_limit = port_base + cvmx_pko_get_num_pko_ports(interface, index);
+    } else {
+        port_base = ipd_port;
+	port_limit = port_base + 1;
+    }
 
+    /*
+     * status->packets and status->octets
+     */
+    status->packets = 0;
+    status->octets = 0;
     pko_reg_read_idx.u64 = 0;
-    pko_reg_read_idx.s.index = port_num;
-    cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
 
-    pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0);
-    status->packets = pko_mem_count0.s.count;
-    if (clear)
+    for (pko_port = port_base; pko_port < port_limit; pko_port++)
     {
-        pko_mem_count0.s.count = port_num;
-        cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64);
-    }
 
-    pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1);
-    status->octets = pko_mem_count1.s.count;
-    if (clear)
-    {
-        pko_mem_count1.s.count = port_num;
-        cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64);
+	/*
+	 * In theory, one doesn't need to write the index csr every
+	 * time as he can set pko_reg_read_idx.s.inc to increment
+	 * the index automatically. Need to find out exactly how XXX.
+	 */
+        pko_reg_read_idx.s.index = pko_port;
+        cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
+
+        pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0);
+        status->packets += pko_mem_count0.s.count;
+        if (clear)
+        {
+            pko_mem_count0.s.count = pko_port;
+            cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64);
+        }
+
+        pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1);
+        status->octets += pko_mem_count1.s.count;
+        if (clear)
+        {
+            pko_mem_count1.s.count = pko_port;
+            cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64);
+        }
     }
 
+    /*
+     * status->doorbell
+     */
     if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
     {
         cvmx_pko_mem_debug9_t debug9;
-        pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
+        pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(ipd_port);
         cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
         debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9);
         status->doorbell = debug9.cn38xx.doorbell;
@@ -550,13 +649,18 @@ static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear, c
     else
     {
         cvmx_pko_mem_debug8_t debug8;
-        pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
+        pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(ipd_port);
         cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
         debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
-        status->doorbell = debug8.cn58xx.doorbell;
+        if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+            status->doorbell = debug8.cn68xx.doorbell;
+        else
+            status->doorbell = debug8.cn58xx.doorbell;
     }
 }
 
+#endif /* CVMX_ENABLE_PKO_FUNCTION */
+
 
 /**
  * Rate limit a PKO port to a max packets/sec. This function is only
@@ -584,6 +688,147 @@ extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst);
  */
 extern int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst);
 
+/**
+ * @INTERNAL
+ * 
+ * Retrieve the PKO pipe number for a port
+ *
+ * @param interface
+ * @param index
+ *
+ * @return negative on error.
+ *
+ * This applies only to the non-loopback interfaces.
+ *
+ */
+extern int __cvmx_pko_get_pipe(int interface, int index);
+
+/**
+ * For a given PKO port number, return the base output queue
+ * for the port.
+ *
+ * @param pko_port   PKO port number
+ * @return           Base output queue
+ */
+extern int cvmx_pko_get_base_queue_pkoid(int pko_port);
+
+/**
+ * For a given PKO port number, return the number of output queues
+ * for the port.
+ *
+ * @param pko_port	PKO port number
+ * @return		the number of output queues
+ */
+extern int cvmx_pko_get_num_queues_pkoid(int pko_port);
+
+/**
+ * Ring the packet output doorbell. This tells the packet
+ * output hardware that "len" command words have been added
+ * to its pending list.  This command includes the required
+ * CVMX_SYNCWS before the doorbell ring.
+ *
+ * @param pko_port   Port the packet is for
+ * @param queue  Queue the packet is for
+ * @param len    Length of the command in 64 bit words
+ */
+static inline void cvmx_pko_doorbell_pkoid(uint64_t pko_port, uint64_t queue, uint64_t len)
+{
+   cvmx_pko_doorbell_address_t ptr;
+
+   ptr.u64          = 0;
+   ptr.s.mem_space  = CVMX_IO_SEG;
+   ptr.s.did        = CVMX_OCT_DID_PKT_SEND;
+   ptr.s.is_io      = 1;
+   ptr.s.port       = pko_port;
+   ptr.s.queue      = queue;
+   CVMX_SYNCWS;  /* Need to make sure output queue data is in DRAM before doorbell write */
+   cvmx_write_io(ptr.u64, len);
+}
+
+/**
+ * Complete packet output. cvmx_pko_send_packet_prepare() must be called exactly once before this,
+ * and the same parameters must be passed to both cvmx_pko_send_packet_prepare() and
+ * cvmx_pko_send_packet_finish_pkoid().
+ *
+ * @param pko_port   Port to send it on
+ * @param queue  Queue to use
+ * @param pko_command
+ *               PKO HW command word
+ * @param packet Packet to send
+ * @param use_locking
+ *               CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or CVMX_PKO_LOCK_CMD_QUEUE
+ *
+ * @return returns CVMX_PKO_SUCCESS on success, or error code on failure of output
+ */
+static inline cvmx_pko_status_t cvmx_pko_send_packet_finish_pkoid(int pko_port, uint64_t queue,
+                                        cvmx_pko_command_word0_t pko_command,
+                                        cvmx_buf_ptr_t packet, cvmx_pko_lock_t use_locking)
+{
+    cvmx_cmd_queue_result_t result;
+    if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
+        cvmx_pow_tag_sw_wait();
+    result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue),
+                                   (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
+                                   pko_command.u64,
+                                   packet.u64);
+    if (cvmx_likely(result == CVMX_CMD_QUEUE_SUCCESS))
+    {
+        cvmx_pko_doorbell_pkoid(pko_port, queue, 2);
+        return CVMX_PKO_SUCCESS;
+    }
+    else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) || (result == CVMX_CMD_QUEUE_FULL))
+    {
+        return CVMX_PKO_NO_MEMORY;
+    }
+    else
+    {
+        return CVMX_PKO_INVALID_QUEUE;
+    }
+}
+
+/**
+ * Complete packet output. cvmx_pko_send_packet_prepare() must be called exactly once before this,
+ * and the same parameters must be passed to both cvmx_pko_send_packet_prepare() and
+ * cvmx_pko_send_packet_finish_pkoid().
+ *
+ * @param pko_port   The PKO port the packet is for
+ * @param queue  Queue to use
+ * @param pko_command
+ *               PKO HW command word
+ * @param packet Packet to send
+ * @param addr   Plysical address of a work queue entry or physical address to zero on complete.
+ * @param use_locking
+ *               CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or CVMX_PKO_LOCK_CMD_QUEUE
+ *
+ * @return returns CVMX_PKO_SUCCESS on success, or error code on failure of output
+ */
+static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3_pkoid(uint64_t pko_port, uint64_t queue,
+                                        cvmx_pko_command_word0_t pko_command,
+                                        cvmx_buf_ptr_t packet, uint64_t addr, cvmx_pko_lock_t use_locking)
+{
+    cvmx_cmd_queue_result_t result;
+    if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
+        cvmx_pow_tag_sw_wait();
+    result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue),
+                                   (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
+                                   pko_command.u64,
+                                   packet.u64,
+                                   addr);
+    if (cvmx_likely(result == CVMX_CMD_QUEUE_SUCCESS))
+    {
+        cvmx_pko_doorbell_pkoid(pko_port, queue, 3);
+        return CVMX_PKO_SUCCESS;
+    }
+    else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) || (result == CVMX_CMD_QUEUE_FULL))
+    {
+        return CVMX_PKO_NO_MEMORY;
+    }
+    else
+    {
+        return CVMX_PKO_INVALID_QUEUE;
+    }
+}
+
 #endif /* CVMX_ENABLE_PKO_FUNCTIONS */
 
 #ifdef	__cplusplus
diff --git a/sys/contrib/octeon-sdk/cvmx-platform.h b/sys/contrib/octeon-sdk/cvmx-platform.h
index d8b797b..a718632 100644
--- a/sys/contrib/octeon-sdk/cvmx-platform.h
+++ b/sys/contrib/octeon-sdk/cvmx-platform.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * This file is resposible for including all system dependent
  * headers for the cvmx-* files.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
 */
 
 #ifndef __CVMX_PLATFORM_H__
@@ -219,6 +219,7 @@ static inline void cvmx_linux_enable_xkphys_access(int32_t warn_count)
 
 #elif defined(CVMX_BUILD_FOR_TOOLCHAIN)
 
+    #ifndef __ASSEMBLY__
     #include <stddef.h>
     #include <stdint.h>
     #include <stdio.h>
@@ -226,6 +227,8 @@ static inline void cvmx_linux_enable_xkphys_access(int32_t warn_count)
     #include <stdarg.h>
     #include <string.h>
     #include <assert.h>
+    #endif
+    #include "rename-cvmx.h"
 
 #elif defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
 
diff --git a/sys/contrib/octeon-sdk/cvmx-pow-defs.h b/sys/contrib/octeon-sdk/cvmx-pow-defs.h
index 53065c9..6f614b1 100644
--- a/sys/contrib/octeon-sdk/cvmx-pow-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-pow-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,13 +49,53 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_POW_TYPEDEFS_H__
-#define __CVMX_POW_TYPEDEFS_H__
+#ifndef __CVMX_POW_DEFS_H__
+#define __CVMX_POW_DEFS_H__
 
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_POW_BIST_STAT CVMX_POW_BIST_STAT_FUNC()
+static inline uint64_t CVMX_POW_BIST_STAT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_POW_BIST_STAT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00016700000003F8ull);
+}
+#else
 #define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_POW_DS_PC CVMX_POW_DS_PC_FUNC()
+static inline uint64_t CVMX_POW_DS_PC_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_POW_DS_PC not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000000398ull);
+}
+#else
 #define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_POW_ECC_ERR CVMX_POW_ECC_ERR_FUNC()
+static inline uint64_t CVMX_POW_ECC_ERR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_POW_ECC_ERR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000000218ull);
+}
+#else
 #define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_POW_INT_CTL CVMX_POW_INT_CTL_FUNC()
+static inline uint64_t CVMX_POW_INT_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_POW_INT_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000000220ull);
+}
+#else
 #define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull))
+#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_POW_IQ_CNTX(unsigned long offset)
 {
@@ -67,19 +107,32 @@ static inline uint64_t CVMX_POW_IQ_CNTX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_POW_IQ_CNTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8;
 }
 #else
 #define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8)
 #endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_POW_IQ_COM_CNT CVMX_POW_IQ_COM_CNT_FUNC()
+static inline uint64_t CVMX_POW_IQ_COM_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_POW_IQ_COM_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000000388ull);
+}
+#else
 #define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull))
+#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_POW_IQ_INT CVMX_POW_IQ_INT_FUNC()
 static inline uint64_t CVMX_POW_IQ_INT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_POW_IQ_INT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001670000000238ull);
 }
@@ -90,7 +143,7 @@ static inline uint64_t CVMX_POW_IQ_INT_FUNC(void)
 #define CVMX_POW_IQ_INT_EN CVMX_POW_IQ_INT_EN_FUNC()
 static inline uint64_t CVMX_POW_IQ_INT_EN_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_POW_IQ_INT_EN not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001670000000240ull);
 }
@@ -103,20 +156,43 @@ static inline uint64_t CVMX_POW_IQ_THRX(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_POW_IQ_THRX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8;
 }
 #else
 #define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8)
 #endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_POW_NOS_CNT CVMX_POW_NOS_CNT_FUNC()
+static inline uint64_t CVMX_POW_NOS_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_POW_NOS_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000000228ull);
+}
+#else
 #define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_POW_NW_TIM CVMX_POW_NW_TIM_FUNC()
+static inline uint64_t CVMX_POW_NW_TIM_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_POW_NW_TIM not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000000210ull);
+}
+#else
 #define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull))
+#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_POW_PF_RST_MSK CVMX_POW_PF_RST_MSK_FUNC()
 static inline uint64_t CVMX_POW_PF_RST_MSK_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_POW_PF_RST_MSK not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001670000000230ull);
 }
@@ -134,7 +210,10 @@ static inline uint64_t CVMX_POW_PP_GRP_MSKX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_POW_PP_GRP_MSKX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8;
 }
@@ -152,7 +231,10 @@ static inline uint64_t CVMX_POW_QOS_RNDX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_POW_QOS_RNDX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8;
 }
@@ -170,15 +252,38 @@ static inline uint64_t CVMX_POW_QOS_THRX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_POW_QOS_THRX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8;
 }
 #else
 #define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8)
 #endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_POW_TS_PC CVMX_POW_TS_PC_FUNC()
+static inline uint64_t CVMX_POW_TS_PC_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_POW_TS_PC not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000000390ull);
+}
+#else
 #define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_POW_WA_COM_PC CVMX_POW_WA_COM_PC_FUNC()
+static inline uint64_t CVMX_POW_WA_COM_PC_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_POW_WA_COM_PC not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000000380ull);
+}
+#else
 #define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull))
+#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_POW_WA_PCX(unsigned long offset)
 {
@@ -190,14 +295,27 @@ static inline uint64_t CVMX_POW_WA_PCX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 		cvmx_warn("CVMX_POW_WA_PCX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8;
 }
 #else
 #define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8)
 #endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_POW_WQ_INT CVMX_POW_WQ_INT_FUNC()
+static inline uint64_t CVMX_POW_WQ_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_POW_WQ_INT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000000200ull);
+}
+#else
 #define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull))
+#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_POW_WQ_INT_CNTX(unsigned long offset)
 {
@@ -209,14 +327,27 @@ static inline uint64_t CVMX_POW_WQ_INT_CNTX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 15)))))
 		cvmx_warn("CVMX_POW_WQ_INT_CNTX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8;
 }
 #else
 #define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8)
 #endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_POW_WQ_INT_PC CVMX_POW_WQ_INT_PC_FUNC()
+static inline uint64_t CVMX_POW_WQ_INT_PC_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_POW_WQ_INT_PC not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000000208ull);
+}
+#else
 #define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull))
+#endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_POW_WQ_INT_THRX(unsigned long offset)
 {
@@ -228,7 +359,10 @@ static inline uint64_t CVMX_POW_WQ_INT_THRX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 15)))))
 		cvmx_warn("CVMX_POW_WQ_INT_THRX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8;
 }
@@ -246,7 +380,10 @@ static inline uint64_t CVMX_POW_WS_PCX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 15)))))
 		cvmx_warn("CVMX_POW_WS_PCX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8;
 }
@@ -264,12 +401,10 @@ static inline uint64_t CVMX_POW_WS_PCX(unsigned long offset)
  * Also contains the BIST status for the PP's.  Each bit in the PP field is the OR of all BIST
  * results for the corresponding physical PP ('0' = pass, '1' = fail).
  */
-union cvmx_pow_bist_stat
-{
+union cvmx_pow_bist_stat {
 	uint64_t u64;
-	struct cvmx_pow_bist_stat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_bist_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t pp                           : 16; /**< Physical PP BIST status */
 	uint64_t reserved_0_15                : 16;
@@ -279,9 +414,8 @@ union cvmx_pow_bist_stat
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
-	struct cvmx_pow_bist_stat_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_bist_stat_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t pp                           : 1;  /**< Physical PP BIST status */
 	uint64_t reserved_9_15                : 7;
@@ -309,9 +443,8 @@ union cvmx_pow_bist_stat
 	uint64_t reserved_17_63               : 47;
 #endif
 	} cn30xx;
-	struct cvmx_pow_bist_stat_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_bist_stat_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t pp                           : 2;  /**< Physical PP BIST status */
 	uint64_t reserved_9_15                : 7;
@@ -339,9 +472,8 @@ union cvmx_pow_bist_stat
 	uint64_t reserved_18_63               : 46;
 #endif
 	} cn31xx;
-	struct cvmx_pow_bist_stat_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_bist_stat_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t pp                           : 16; /**< Physical PP BIST status */
 	uint64_t reserved_10_15               : 6;
@@ -373,9 +505,8 @@ union cvmx_pow_bist_stat
 	} cn38xx;
 	struct cvmx_pow_bist_stat_cn38xx      cn38xxp2;
 	struct cvmx_pow_bist_stat_cn31xx      cn50xx;
-	struct cvmx_pow_bist_stat_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_bist_stat_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t pp                           : 4;  /**< Physical PP BIST status */
 	uint64_t reserved_9_15                : 7;
@@ -404,9 +535,8 @@ union cvmx_pow_bist_stat
 #endif
 	} cn52xx;
 	struct cvmx_pow_bist_stat_cn52xx      cn52xxp1;
-	struct cvmx_pow_bist_stat_cn56xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_bist_stat_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t pp                           : 12; /**< Physical PP BIST status */
 	uint64_t reserved_10_15               : 6;
@@ -439,9 +569,33 @@ union cvmx_pow_bist_stat
 	struct cvmx_pow_bist_stat_cn56xx      cn56xxp1;
 	struct cvmx_pow_bist_stat_cn38xx      cn58xx;
 	struct cvmx_pow_bist_stat_cn38xx      cn58xxp1;
-	struct cvmx_pow_bist_stat_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_bist_stat_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t pp                           : 4;  /**< Physical PP BIST status */
+	uint64_t reserved_12_15               : 4;
+	uint64_t cam                          : 1;  /**< POW CAM BIST status */
+	uint64_t nbr                          : 3;  /**< NCB receiver memory BIST status */
+	uint64_t nbt                          : 4;  /**< NCB transmitter memory BIST status */
+	uint64_t index                        : 1;  /**< Index memory BIST status */
+	uint64_t fidx                         : 1;  /**< Forward index memory BIST status */
+	uint64_t pend                         : 1;  /**< Pending switch memory BIST status */
+	uint64_t adr                          : 1;  /**< Address memory BIST status */
+#else
+	uint64_t adr                          : 1;
+	uint64_t pend                         : 1;
+	uint64_t fidx                         : 1;
+	uint64_t index                        : 1;
+	uint64_t nbt                          : 4;
+	uint64_t nbr                          : 3;
+	uint64_t cam                          : 1;
+	uint64_t reserved_12_15               : 4;
+	uint64_t pp                           : 4;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn61xx;
+	struct cvmx_pow_bist_stat_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_22_63               : 42;
 	uint64_t pp                           : 6;  /**< Physical PP BIST status */
 	uint64_t reserved_12_15               : 4;
@@ -466,6 +620,32 @@ union cvmx_pow_bist_stat
 #endif
 	} cn63xx;
 	struct cvmx_pow_bist_stat_cn63xx      cn63xxp1;
+	struct cvmx_pow_bist_stat_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_26_63               : 38;
+	uint64_t pp                           : 10; /**< Physical PP BIST status */
+	uint64_t reserved_12_15               : 4;
+	uint64_t cam                          : 1;  /**< POW CAM BIST status */
+	uint64_t nbr                          : 3;  /**< NCB receiver memory BIST status */
+	uint64_t nbt                          : 4;  /**< NCB transmitter memory BIST status */
+	uint64_t index                        : 1;  /**< Index memory BIST status */
+	uint64_t fidx                         : 1;  /**< Forward index memory BIST status */
+	uint64_t pend                         : 1;  /**< Pending switch memory BIST status */
+	uint64_t adr                          : 1;  /**< Address memory BIST status */
+#else
+	uint64_t adr                          : 1;
+	uint64_t pend                         : 1;
+	uint64_t fidx                         : 1;
+	uint64_t index                        : 1;
+	uint64_t nbt                          : 4;
+	uint64_t nbr                          : 3;
+	uint64_t cam                          : 1;
+	uint64_t reserved_12_15               : 4;
+	uint64_t pp                           : 10;
+	uint64_t reserved_26_63               : 38;
+#endif
+	} cn66xx;
+	struct cvmx_pow_bist_stat_cn61xx      cnf71xx;
 };
 typedef union cvmx_pow_bist_stat cvmx_pow_bist_stat_t;
 
@@ -476,12 +656,10 @@ typedef union cvmx_pow_bist_stat cvmx_pow_bist_stat_t;
  *
  * Counts the number of de-schedule requests.  Write to clear.
  */
-union cvmx_pow_ds_pc
-{
+union cvmx_pow_ds_pc {
 	uint64_t u64;
-	struct cvmx_pow_ds_pc_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_ds_pc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t ds_pc                        : 32; /**< De-schedule performance counter */
 #else
@@ -500,8 +678,11 @@ union cvmx_pow_ds_pc
 	struct cvmx_pow_ds_pc_s               cn56xxp1;
 	struct cvmx_pow_ds_pc_s               cn58xx;
 	struct cvmx_pow_ds_pc_s               cn58xxp1;
+	struct cvmx_pow_ds_pc_s               cn61xx;
 	struct cvmx_pow_ds_pc_s               cn63xx;
 	struct cvmx_pow_ds_pc_s               cn63xxp1;
+	struct cvmx_pow_ds_pc_s               cn66xx;
+	struct cvmx_pow_ds_pc_s               cnf71xx;
 };
 typedef union cvmx_pow_ds_pc cvmx_pow_ds_pc_t;
 
@@ -536,12 +717,10 @@ typedef union cvmx_pow_ds_pc cvmx_pow_ds_pc_t;
  * <11> Received DBG load from PP with DBG load pending
  * <12> Received CSR load from PP with CSR load pending
  */
-union cvmx_pow_ecc_err
-{
+union cvmx_pow_ecc_err {
 	uint64_t u64;
-	struct cvmx_pow_ecc_err_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_ecc_err_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_45_63               : 19;
 	uint64_t iop_ie                       : 13; /**< Illegal operation interrupt enables */
 	uint64_t reserved_29_31               : 3;
@@ -572,9 +751,8 @@ union cvmx_pow_ecc_err
 #endif
 	} s;
 	struct cvmx_pow_ecc_err_s             cn30xx;
-	struct cvmx_pow_ecc_err_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_ecc_err_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t rpe_ie                       : 1;  /**< Remote pointer error interrupt enable */
 	uint64_t rpe                          : 1;  /**< Remote pointer error */
@@ -605,8 +783,11 @@ union cvmx_pow_ecc_err
 	struct cvmx_pow_ecc_err_s             cn56xxp1;
 	struct cvmx_pow_ecc_err_s             cn58xx;
 	struct cvmx_pow_ecc_err_s             cn58xxp1;
+	struct cvmx_pow_ecc_err_s             cn61xx;
 	struct cvmx_pow_ecc_err_s             cn63xx;
 	struct cvmx_pow_ecc_err_s             cn63xxp1;
+	struct cvmx_pow_ecc_err_s             cn66xx;
+	struct cvmx_pow_ecc_err_s             cnf71xx;
 };
 typedef union cvmx_pow_ecc_err cvmx_pow_ecc_err_t;
 
@@ -622,12 +803,10 @@ typedef union cvmx_pow_ecc_err cvmx_pow_ecc_err_t;
  * NBR_THR = Assert ncb__busy when the number of remaining coherent bus NBR credits equals is less
  * than or equal to this value.
  */
-union cvmx_pow_int_ctl
-{
+union cvmx_pow_int_ctl {
 	uint64_t u64;
-	struct cvmx_pow_int_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_int_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t pfr_dis                      : 1;  /**< High-perf pre-fetch reset mode disable */
 	uint64_t nbr_thr                      : 5;  /**< NBR busy threshold */
@@ -648,8 +827,11 @@ union cvmx_pow_int_ctl
 	struct cvmx_pow_int_ctl_s             cn56xxp1;
 	struct cvmx_pow_int_ctl_s             cn58xx;
 	struct cvmx_pow_int_ctl_s             cn58xxp1;
+	struct cvmx_pow_int_ctl_s             cn61xx;
 	struct cvmx_pow_int_ctl_s             cn63xx;
 	struct cvmx_pow_int_ctl_s             cn63xxp1;
+	struct cvmx_pow_int_ctl_s             cn66xx;
+	struct cvmx_pow_int_ctl_s             cnf71xx;
 };
 typedef union cvmx_pow_int_ctl cvmx_pow_int_ctl_t;
 
@@ -660,12 +842,10 @@ typedef union cvmx_pow_int_ctl cvmx_pow_int_ctl_t;
  *
  * Contains a read-only count of the number of work queue entries for each QOS level.
  */
-union cvmx_pow_iq_cntx
-{
+union cvmx_pow_iq_cntx {
 	uint64_t u64;
-	struct cvmx_pow_iq_cntx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_iq_cntx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t iq_cnt                       : 32; /**< Input queue count for QOS level X */
 #else
@@ -684,8 +864,11 @@ union cvmx_pow_iq_cntx
 	struct cvmx_pow_iq_cntx_s             cn56xxp1;
 	struct cvmx_pow_iq_cntx_s             cn58xx;
 	struct cvmx_pow_iq_cntx_s             cn58xxp1;
+	struct cvmx_pow_iq_cntx_s             cn61xx;
 	struct cvmx_pow_iq_cntx_s             cn63xx;
 	struct cvmx_pow_iq_cntx_s             cn63xxp1;
+	struct cvmx_pow_iq_cntx_s             cn66xx;
+	struct cvmx_pow_iq_cntx_s             cnf71xx;
 };
 typedef union cvmx_pow_iq_cntx cvmx_pow_iq_cntx_t;
 
@@ -696,12 +879,10 @@ typedef union cvmx_pow_iq_cntx cvmx_pow_iq_cntx_t;
  *
  * Contains a read-only count of the total number of work queue entries in all QOS levels.
  */
-union cvmx_pow_iq_com_cnt
-{
+union cvmx_pow_iq_com_cnt {
 	uint64_t u64;
-	struct cvmx_pow_iq_com_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_iq_com_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t iq_cnt                       : 32; /**< Input queue combined count */
 #else
@@ -720,8 +901,11 @@ union cvmx_pow_iq_com_cnt
 	struct cvmx_pow_iq_com_cnt_s          cn56xxp1;
 	struct cvmx_pow_iq_com_cnt_s          cn58xx;
 	struct cvmx_pow_iq_com_cnt_s          cn58xxp1;
+	struct cvmx_pow_iq_com_cnt_s          cn61xx;
 	struct cvmx_pow_iq_com_cnt_s          cn63xx;
 	struct cvmx_pow_iq_com_cnt_s          cn63xxp1;
+	struct cvmx_pow_iq_com_cnt_s          cn66xx;
+	struct cvmx_pow_iq_com_cnt_s          cnf71xx;
 };
 typedef union cvmx_pow_iq_com_cnt cvmx_pow_iq_com_cnt_t;
 
@@ -733,12 +917,10 @@ typedef union cvmx_pow_iq_com_cnt cvmx_pow_iq_com_cnt_t;
  * Contains the bits (1 per QOS level) that can trigger the input queue interrupt.  An IQ_INT bit
  * will be set if POW_IQ_CNT#QOS# changes and the resulting value is equal to POW_IQ_THR#QOS#.
  */
-union cvmx_pow_iq_int
-{
+union cvmx_pow_iq_int {
 	uint64_t u64;
-	struct cvmx_pow_iq_int_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_iq_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t iq_int                       : 8;  /**< Input queue interrupt bits */
 #else
@@ -750,8 +932,11 @@ union cvmx_pow_iq_int
 	struct cvmx_pow_iq_int_s              cn52xxp1;
 	struct cvmx_pow_iq_int_s              cn56xx;
 	struct cvmx_pow_iq_int_s              cn56xxp1;
+	struct cvmx_pow_iq_int_s              cn61xx;
 	struct cvmx_pow_iq_int_s              cn63xx;
 	struct cvmx_pow_iq_int_s              cn63xxp1;
+	struct cvmx_pow_iq_int_s              cn66xx;
+	struct cvmx_pow_iq_int_s              cnf71xx;
 };
 typedef union cvmx_pow_iq_int cvmx_pow_iq_int_t;
 
@@ -762,12 +947,10 @@ typedef union cvmx_pow_iq_int cvmx_pow_iq_int_t;
  *
  * Contains the bits (1 per QOS level) that enable the input queue interrupt.
  */
-union cvmx_pow_iq_int_en
-{
+union cvmx_pow_iq_int_en {
 	uint64_t u64;
-	struct cvmx_pow_iq_int_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_iq_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t int_en                       : 8;  /**< Input queue interrupt enable bits */
 #else
@@ -779,8 +962,11 @@ union cvmx_pow_iq_int_en
 	struct cvmx_pow_iq_int_en_s           cn52xxp1;
 	struct cvmx_pow_iq_int_en_s           cn56xx;
 	struct cvmx_pow_iq_int_en_s           cn56xxp1;
+	struct cvmx_pow_iq_int_en_s           cn61xx;
 	struct cvmx_pow_iq_int_en_s           cn63xx;
 	struct cvmx_pow_iq_int_en_s           cn63xxp1;
+	struct cvmx_pow_iq_int_en_s           cn66xx;
+	struct cvmx_pow_iq_int_en_s           cnf71xx;
 };
 typedef union cvmx_pow_iq_int_en cvmx_pow_iq_int_en_t;
 
@@ -791,12 +977,10 @@ typedef union cvmx_pow_iq_int_en cvmx_pow_iq_int_en_t;
  *
  * Threshold value for triggering input queue interrupts.
  */
-union cvmx_pow_iq_thrx
-{
+union cvmx_pow_iq_thrx {
 	uint64_t u64;
-	struct cvmx_pow_iq_thrx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_iq_thrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t iq_thr                       : 32; /**< Input queue threshold for QOS level X */
 #else
@@ -808,8 +992,11 @@ union cvmx_pow_iq_thrx
 	struct cvmx_pow_iq_thrx_s             cn52xxp1;
 	struct cvmx_pow_iq_thrx_s             cn56xx;
 	struct cvmx_pow_iq_thrx_s             cn56xxp1;
+	struct cvmx_pow_iq_thrx_s             cn61xx;
 	struct cvmx_pow_iq_thrx_s             cn63xx;
 	struct cvmx_pow_iq_thrx_s             cn63xxp1;
+	struct cvmx_pow_iq_thrx_s             cn66xx;
+	struct cvmx_pow_iq_thrx_s             cnf71xx;
 };
 typedef union cvmx_pow_iq_thrx cvmx_pow_iq_thrx_t;
 
@@ -820,12 +1007,10 @@ typedef union cvmx_pow_iq_thrx cvmx_pow_iq_thrx_t;
  *
  * Contains the number of work queue entries on the no-schedule list.
  */
-union cvmx_pow_nos_cnt
-{
+union cvmx_pow_nos_cnt {
 	uint64_t u64;
-	struct cvmx_pow_nos_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_nos_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t nos_cnt                      : 12; /**< # of work queue entries on the no-schedule list */
 #else
@@ -833,9 +1018,8 @@ union cvmx_pow_nos_cnt
 	uint64_t reserved_12_63               : 52;
 #endif
 	} s;
-	struct cvmx_pow_nos_cnt_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_nos_cnt_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t nos_cnt                      : 7;  /**< # of work queue entries on the no-schedule list */
 #else
@@ -843,9 +1027,8 @@ union cvmx_pow_nos_cnt
 	uint64_t reserved_7_63                : 57;
 #endif
 	} cn30xx;
-	struct cvmx_pow_nos_cnt_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_nos_cnt_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t nos_cnt                      : 9;  /**< # of work queue entries on the no-schedule list */
 #else
@@ -856,9 +1039,8 @@ union cvmx_pow_nos_cnt
 	struct cvmx_pow_nos_cnt_s             cn38xx;
 	struct cvmx_pow_nos_cnt_s             cn38xxp2;
 	struct cvmx_pow_nos_cnt_cn31xx        cn50xx;
-	struct cvmx_pow_nos_cnt_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_nos_cnt_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t nos_cnt                      : 10; /**< # of work queue entries on the no-schedule list */
 #else
@@ -871,9 +1053,9 @@ union cvmx_pow_nos_cnt
 	struct cvmx_pow_nos_cnt_s             cn56xxp1;
 	struct cvmx_pow_nos_cnt_s             cn58xx;
 	struct cvmx_pow_nos_cnt_s             cn58xxp1;
-	struct cvmx_pow_nos_cnt_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_nos_cnt_cn52xx        cn61xx;
+	struct cvmx_pow_nos_cnt_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t nos_cnt                      : 11; /**< # of work queue entries on the no-schedule list */
 #else
@@ -882,6 +1064,8 @@ union cvmx_pow_nos_cnt
 #endif
 	} cn63xx;
 	struct cvmx_pow_nos_cnt_cn63xx        cn63xxp1;
+	struct cvmx_pow_nos_cnt_cn63xx        cn66xx;
+	struct cvmx_pow_nos_cnt_cn52xx        cnf71xx;
 };
 typedef union cvmx_pow_nos_cnt cvmx_pow_nos_cnt_t;
 
@@ -918,12 +1102,10 @@ typedef union cvmx_pow_nos_cnt cvmx_pow_nos_cnt_t;
  * de-schedules occuring, it's possible for the new work timer to expire (resulting in NO_WORK
  * responses) before the pre-fetch engine is able to get very deep into the work queues.
  */
-union cvmx_pow_nw_tim
-{
+union cvmx_pow_nw_tim {
 	uint64_t u64;
-	struct cvmx_pow_nw_tim_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_nw_tim_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t nw_tim                       : 10; /**< New work timer period */
 #else
@@ -942,8 +1124,11 @@ union cvmx_pow_nw_tim
 	struct cvmx_pow_nw_tim_s              cn56xxp1;
 	struct cvmx_pow_nw_tim_s              cn58xx;
 	struct cvmx_pow_nw_tim_s              cn58xxp1;
+	struct cvmx_pow_nw_tim_s              cn61xx;
 	struct cvmx_pow_nw_tim_s              cn63xx;
 	struct cvmx_pow_nw_tim_s              cn63xxp1;
+	struct cvmx_pow_nw_tim_s              cn66xx;
+	struct cvmx_pow_nw_tim_s              cnf71xx;
 };
 typedef union cvmx_pow_nw_tim cvmx_pow_nw_tim_t;
 
@@ -956,12 +1141,10 @@ typedef union cvmx_pow_nw_tim cvmx_pow_nw_tim_t;
  * work arrives or when the work is reloaded from an external buffer) for an enabled QOS level
  * (1 bit per QOS level).
  */
-union cvmx_pow_pf_rst_msk
-{
+union cvmx_pow_pf_rst_msk {
 	uint64_t u64;
-	struct cvmx_pow_pf_rst_msk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_pf_rst_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t rst_msk                      : 8;  /**< Prefetch engine reset mask */
 #else
@@ -976,8 +1159,11 @@ union cvmx_pow_pf_rst_msk
 	struct cvmx_pow_pf_rst_msk_s          cn56xxp1;
 	struct cvmx_pow_pf_rst_msk_s          cn58xx;
 	struct cvmx_pow_pf_rst_msk_s          cn58xxp1;
+	struct cvmx_pow_pf_rst_msk_s          cn61xx;
 	struct cvmx_pow_pf_rst_msk_s          cn63xx;
 	struct cvmx_pow_pf_rst_msk_s          cn63xxp1;
+	struct cvmx_pow_pf_rst_msk_s          cn66xx;
+	struct cvmx_pow_pf_rst_msk_s          cnf71xx;
 };
 typedef union cvmx_pow_pf_rst_msk cvmx_pow_pf_rst_msk_t;
 
@@ -996,12 +1182,10 @@ typedef union cvmx_pow_pf_rst_msk cvmx_pow_pf_rst_msk_t;
  * Priority values 0x8 through 0xe are reserved and should not be used.  For a given PP, priorities
  * should begin at 0x0 and remain contiguous throughout the range.
  */
-union cvmx_pow_pp_grp_mskx
-{
+union cvmx_pow_pp_grp_mskx {
 	uint64_t u64;
-	struct cvmx_pow_pp_grp_mskx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_pp_grp_mskx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t qos7_pri                     : 4;  /**< PPX priority for QOS level 7 */
 	uint64_t qos6_pri                     : 4;  /**< PPX priority for QOS level 6 */
@@ -1025,9 +1209,8 @@ union cvmx_pow_pp_grp_mskx
 	uint64_t reserved_48_63               : 16;
 #endif
 	} s;
-	struct cvmx_pow_pp_grp_mskx_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_pp_grp_mskx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t grp_msk                      : 16; /**< PPX group mask */
 #else
@@ -1045,8 +1228,11 @@ union cvmx_pow_pp_grp_mskx
 	struct cvmx_pow_pp_grp_mskx_s         cn56xxp1;
 	struct cvmx_pow_pp_grp_mskx_s         cn58xx;
 	struct cvmx_pow_pp_grp_mskx_s         cn58xxp1;
+	struct cvmx_pow_pp_grp_mskx_s         cn61xx;
 	struct cvmx_pow_pp_grp_mskx_s         cn63xx;
 	struct cvmx_pow_pp_grp_mskx_s         cn63xxp1;
+	struct cvmx_pow_pp_grp_mskx_s         cn66xx;
+	struct cvmx_pow_pp_grp_mskx_s         cnf71xx;
 };
 typedef union cvmx_pow_pp_grp_mskx cvmx_pow_pp_grp_mskx_t;
 
@@ -1063,12 +1249,10 @@ typedef union cvmx_pow_pp_grp_mskx cvmx_pow_pp_grp_mskx_t;
  * bit in the round mask.  Note: setting a QOS level to all zeroes in all issue round registers will
  * prevent work from being issued from that QOS level.
  */
-union cvmx_pow_qos_rndx
-{
+union cvmx_pow_qos_rndx {
 	uint64_t u64;
-	struct cvmx_pow_qos_rndx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_qos_rndx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t rnd_p3                       : 8;  /**< Round mask for round Xx4+3 */
 	uint64_t rnd_p2                       : 8;  /**< Round mask for round Xx4+2 */
@@ -1093,8 +1277,11 @@ union cvmx_pow_qos_rndx
 	struct cvmx_pow_qos_rndx_s            cn56xxp1;
 	struct cvmx_pow_qos_rndx_s            cn58xx;
 	struct cvmx_pow_qos_rndx_s            cn58xxp1;
+	struct cvmx_pow_qos_rndx_s            cn61xx;
 	struct cvmx_pow_qos_rndx_s            cn63xx;
 	struct cvmx_pow_qos_rndx_s            cn63xxp1;
+	struct cvmx_pow_qos_rndx_s            cn66xx;
+	struct cvmx_pow_qos_rndx_s            cnf71xx;
 };
 typedef union cvmx_pow_qos_rndx cvmx_pow_qos_rndx_t;
 
@@ -1111,12 +1298,10 @@ typedef union cvmx_pow_qos_rndx cvmx_pow_qos_rndx_t;
  * allocated to this QOS level (BUF_CNT), and the total number of buffers on the de-schedule list
  * (DES_CNT) (which is not the same as the total number of de-scheduled buffers).
  */
-union cvmx_pow_qos_thrx
-{
+union cvmx_pow_qos_thrx {
 	uint64_t u64;
-	struct cvmx_pow_qos_thrx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_qos_thrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_60_63               : 4;
 	uint64_t des_cnt                      : 12; /**< # of buffers on de-schedule list */
 	uint64_t buf_cnt                      : 12; /**< # of internal buffers allocated to QOS level X */
@@ -1136,9 +1321,8 @@ union cvmx_pow_qos_thrx
 	uint64_t reserved_60_63               : 4;
 #endif
 	} s;
-	struct cvmx_pow_qos_thrx_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_qos_thrx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_55_63               : 9;
 	uint64_t des_cnt                      : 7;  /**< # of buffers on de-schedule list */
 	uint64_t reserved_43_47               : 5;
@@ -1162,9 +1346,8 @@ union cvmx_pow_qos_thrx
 	uint64_t reserved_55_63               : 9;
 #endif
 	} cn30xx;
-	struct cvmx_pow_qos_thrx_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_qos_thrx_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_57_63               : 7;
 	uint64_t des_cnt                      : 9;  /**< # of buffers on de-schedule list */
 	uint64_t reserved_45_47               : 3;
@@ -1191,9 +1374,8 @@ union cvmx_pow_qos_thrx
 	struct cvmx_pow_qos_thrx_s            cn38xx;
 	struct cvmx_pow_qos_thrx_s            cn38xxp2;
 	struct cvmx_pow_qos_thrx_cn31xx       cn50xx;
-	struct cvmx_pow_qos_thrx_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_qos_thrx_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_58_63               : 6;
 	uint64_t des_cnt                      : 10; /**< # of buffers on de-schedule list */
 	uint64_t reserved_46_47               : 2;
@@ -1222,9 +1404,9 @@ union cvmx_pow_qos_thrx
 	struct cvmx_pow_qos_thrx_s            cn56xxp1;
 	struct cvmx_pow_qos_thrx_s            cn58xx;
 	struct cvmx_pow_qos_thrx_s            cn58xxp1;
-	struct cvmx_pow_qos_thrx_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_qos_thrx_cn52xx       cn61xx;
+	struct cvmx_pow_qos_thrx_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_59_63               : 5;
 	uint64_t des_cnt                      : 11; /**< # of buffers on de-schedule list */
 	uint64_t reserved_47_47               : 1;
@@ -1249,6 +1431,8 @@ union cvmx_pow_qos_thrx
 #endif
 	} cn63xx;
 	struct cvmx_pow_qos_thrx_cn63xx       cn63xxp1;
+	struct cvmx_pow_qos_thrx_cn63xx       cn66xx;
+	struct cvmx_pow_qos_thrx_cn52xx       cnf71xx;
 };
 typedef union cvmx_pow_qos_thrx cvmx_pow_qos_thrx_t;
 
@@ -1259,12 +1443,10 @@ typedef union cvmx_pow_qos_thrx cvmx_pow_qos_thrx_t;
  *
  * Counts the number of tag switch requests.  Write to clear.
  */
-union cvmx_pow_ts_pc
-{
+union cvmx_pow_ts_pc {
 	uint64_t u64;
-	struct cvmx_pow_ts_pc_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_ts_pc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t ts_pc                        : 32; /**< Tag switch performance counter */
 #else
@@ -1283,8 +1465,11 @@ union cvmx_pow_ts_pc
 	struct cvmx_pow_ts_pc_s               cn56xxp1;
 	struct cvmx_pow_ts_pc_s               cn58xx;
 	struct cvmx_pow_ts_pc_s               cn58xxp1;
+	struct cvmx_pow_ts_pc_s               cn61xx;
 	struct cvmx_pow_ts_pc_s               cn63xx;
 	struct cvmx_pow_ts_pc_s               cn63xxp1;
+	struct cvmx_pow_ts_pc_s               cn66xx;
+	struct cvmx_pow_ts_pc_s               cnf71xx;
 };
 typedef union cvmx_pow_ts_pc cvmx_pow_ts_pc_t;
 
@@ -1295,12 +1480,10 @@ typedef union cvmx_pow_ts_pc cvmx_pow_ts_pc_t;
  *
  * Counts the number of add new work requests for all QOS levels.  Write to clear.
  */
-union cvmx_pow_wa_com_pc
-{
+union cvmx_pow_wa_com_pc {
 	uint64_t u64;
-	struct cvmx_pow_wa_com_pc_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_wa_com_pc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t wa_pc                        : 32; /**< Work add combined performance counter */
 #else
@@ -1319,8 +1502,11 @@ union cvmx_pow_wa_com_pc
 	struct cvmx_pow_wa_com_pc_s           cn56xxp1;
 	struct cvmx_pow_wa_com_pc_s           cn58xx;
 	struct cvmx_pow_wa_com_pc_s           cn58xxp1;
+	struct cvmx_pow_wa_com_pc_s           cn61xx;
 	struct cvmx_pow_wa_com_pc_s           cn63xx;
 	struct cvmx_pow_wa_com_pc_s           cn63xxp1;
+	struct cvmx_pow_wa_com_pc_s           cn66xx;
+	struct cvmx_pow_wa_com_pc_s           cnf71xx;
 };
 typedef union cvmx_pow_wa_com_pc cvmx_pow_wa_com_pc_t;
 
@@ -1331,12 +1517,10 @@ typedef union cvmx_pow_wa_com_pc cvmx_pow_wa_com_pc_t;
  *
  * Counts the number of add new work requests for each QOS level.  Write to clear.
  */
-union cvmx_pow_wa_pcx
-{
+union cvmx_pow_wa_pcx {
 	uint64_t u64;
-	struct cvmx_pow_wa_pcx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_wa_pcx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t wa_pc                        : 32; /**< Work add performance counter for QOS level X */
 #else
@@ -1355,8 +1539,11 @@ union cvmx_pow_wa_pcx
 	struct cvmx_pow_wa_pcx_s              cn56xxp1;
 	struct cvmx_pow_wa_pcx_s              cn58xx;
 	struct cvmx_pow_wa_pcx_s              cn58xxp1;
+	struct cvmx_pow_wa_pcx_s              cn61xx;
 	struct cvmx_pow_wa_pcx_s              cn63xx;
 	struct cvmx_pow_wa_pcx_s              cn63xxp1;
+	struct cvmx_pow_wa_pcx_s              cn66xx;
+	struct cvmx_pow_wa_pcx_s              cnf71xx;
 };
 typedef union cvmx_pow_wa_pcx cvmx_pow_wa_pcx_t;
 
@@ -1369,12 +1556,10 @@ typedef union cvmx_pow_wa_pcx cvmx_pow_wa_pcx_t;
  * interrupts.  Also contains the input queue interrupt temporary disable bits (1 per group).  For
  * more information regarding this register, see the interrupt section.
  */
-union cvmx_pow_wq_int
-{
+union cvmx_pow_wq_int {
 	uint64_t u64;
-	struct cvmx_pow_wq_int_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_wq_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t iq_dis                       : 16; /**< Input queue interrupt temporary disable mask
                                                          Corresponding WQ_INT<*> bit cannot be set due to
@@ -1416,8 +1601,11 @@ union cvmx_pow_wq_int
 	struct cvmx_pow_wq_int_s              cn56xxp1;
 	struct cvmx_pow_wq_int_s              cn58xx;
 	struct cvmx_pow_wq_int_s              cn58xxp1;
+	struct cvmx_pow_wq_int_s              cn61xx;
 	struct cvmx_pow_wq_int_s              cn63xx;
 	struct cvmx_pow_wq_int_s              cn63xxp1;
+	struct cvmx_pow_wq_int_s              cn66xx;
+	struct cvmx_pow_wq_int_s              cnf71xx;
 };
 typedef union cvmx_pow_wq_int cvmx_pow_wq_int_t;
 
@@ -1429,12 +1617,10 @@ typedef union cvmx_pow_wq_int cvmx_pow_wq_int_t;
  * Contains a read-only copy of the counts used to trigger work queue interrupts.  For more
  * information regarding this register, see the interrupt section.
  */
-union cvmx_pow_wq_int_cntx
-{
+union cvmx_pow_wq_int_cntx {
 	uint64_t u64;
-	struct cvmx_pow_wq_int_cntx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_wq_int_cntx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t tc_cnt                       : 4;  /**< Time counter current value for group X
                                                          HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
@@ -1459,9 +1645,8 @@ union cvmx_pow_wq_int_cntx
 	uint64_t reserved_28_63               : 36;
 #endif
 	} s;
-	struct cvmx_pow_wq_int_cntx_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_wq_int_cntx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t tc_cnt                       : 4;  /**< Time counter current value for group X
                                                          HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
@@ -1490,9 +1675,8 @@ union cvmx_pow_wq_int_cntx
 	uint64_t reserved_28_63               : 36;
 #endif
 	} cn30xx;
-	struct cvmx_pow_wq_int_cntx_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_wq_int_cntx_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t tc_cnt                       : 4;  /**< Time counter current value for group X
                                                          HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
@@ -1524,9 +1708,8 @@ union cvmx_pow_wq_int_cntx
 	struct cvmx_pow_wq_int_cntx_s         cn38xx;
 	struct cvmx_pow_wq_int_cntx_s         cn38xxp2;
 	struct cvmx_pow_wq_int_cntx_cn31xx    cn50xx;
-	struct cvmx_pow_wq_int_cntx_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_wq_int_cntx_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t tc_cnt                       : 4;  /**< Time counter current value for group X
                                                          HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
@@ -1560,9 +1743,9 @@ union cvmx_pow_wq_int_cntx
 	struct cvmx_pow_wq_int_cntx_s         cn56xxp1;
 	struct cvmx_pow_wq_int_cntx_s         cn58xx;
 	struct cvmx_pow_wq_int_cntx_s         cn58xxp1;
-	struct cvmx_pow_wq_int_cntx_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_wq_int_cntx_cn52xx    cn61xx;
+	struct cvmx_pow_wq_int_cntx_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t tc_cnt                       : 4;  /**< Time counter current value for group X
                                                          HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
@@ -1592,6 +1775,8 @@ union cvmx_pow_wq_int_cntx
 #endif
 	} cn63xx;
 	struct cvmx_pow_wq_int_cntx_cn63xx    cn63xxp1;
+	struct cvmx_pow_wq_int_cntx_cn63xx    cn66xx;
+	struct cvmx_pow_wq_int_cntx_cn52xx    cnf71xx;
 };
 typedef union cvmx_pow_wq_int_cntx cvmx_pow_wq_int_cntx_t;
 
@@ -1604,12 +1789,10 @@ typedef union cvmx_pow_wq_int_cntx cvmx_pow_wq_int_cntx_t;
  * copy of the periodic counter.  For more information regarding this register, see the interrupt
  * section.
  */
-union cvmx_pow_wq_int_pc
-{
+union cvmx_pow_wq_int_pc {
 	uint64_t u64;
-	struct cvmx_pow_wq_int_pc_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_wq_int_pc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_60_63               : 4;
 	uint64_t pc                           : 28; /**< Work queue interrupt periodic counter */
 	uint64_t reserved_28_31               : 4;
@@ -1634,8 +1817,11 @@ union cvmx_pow_wq_int_pc
 	struct cvmx_pow_wq_int_pc_s           cn56xxp1;
 	struct cvmx_pow_wq_int_pc_s           cn58xx;
 	struct cvmx_pow_wq_int_pc_s           cn58xxp1;
+	struct cvmx_pow_wq_int_pc_s           cn61xx;
 	struct cvmx_pow_wq_int_pc_s           cn63xx;
 	struct cvmx_pow_wq_int_pc_s           cn63xxp1;
+	struct cvmx_pow_wq_int_pc_s           cn66xx;
+	struct cvmx_pow_wq_int_pc_s           cnf71xx;
 };
 typedef union cvmx_pow_wq_int_pc cvmx_pow_wq_int_pc_t;
 
@@ -1647,18 +1833,16 @@ typedef union cvmx_pow_wq_int_pc cvmx_pow_wq_int_pc_t;
  * Contains the thresholds for enabling and setting work queue interrupts.  For more information
  * regarding this register, see the interrupt section.
  *
- * Note: Up to 8 of the POW's internal storage buffers can be allocated for hardware use and are
+ * Note: Up to 4 of the POW's internal storage buffers can be allocated for hardware use and are
  * therefore not available for incoming work queue entries.  Additionally, any PP that is not in the
- * NULL_NULL state consumes a buffer.  Thus in a 6 PP system, it is not advisable to set either
- * IQ_THR or DS_THR to greater than 1024 - 8 - 6 = 1010.  Doing so may prevent the interrupt from
+ * NULL_NULL state consumes a buffer.  Thus in a 4 PP system, it is not advisable to set either
+ * IQ_THR or DS_THR to greater than 512 - 4 - 4 = 504.  Doing so may prevent the interrupt from
  * ever triggering.
  */
-union cvmx_pow_wq_int_thrx
-{
+union cvmx_pow_wq_int_thrx {
 	uint64_t u64;
-	struct cvmx_pow_wq_int_thrx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_wq_int_thrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t tc_en                        : 1;  /**< Time counter interrupt enable for group X
                                                          TC_EN must be zero when TC_THR==0 */
@@ -1680,9 +1864,8 @@ union cvmx_pow_wq_int_thrx
 	uint64_t reserved_29_63               : 35;
 #endif
 	} s;
-	struct cvmx_pow_wq_int_thrx_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_wq_int_thrx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t tc_en                        : 1;  /**< Time counter interrupt enable for group X
                                                          TC_EN must be zero when TC_THR==0 */
@@ -1704,9 +1887,8 @@ union cvmx_pow_wq_int_thrx
 	uint64_t reserved_29_63               : 35;
 #endif
 	} cn30xx;
-	struct cvmx_pow_wq_int_thrx_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_wq_int_thrx_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t tc_en                        : 1;  /**< Time counter interrupt enable for group X
                                                          TC_EN must be zero when TC_THR==0 */
@@ -1731,9 +1913,8 @@ union cvmx_pow_wq_int_thrx
 	struct cvmx_pow_wq_int_thrx_s         cn38xx;
 	struct cvmx_pow_wq_int_thrx_s         cn38xxp2;
 	struct cvmx_pow_wq_int_thrx_cn31xx    cn50xx;
-	struct cvmx_pow_wq_int_thrx_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_wq_int_thrx_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t tc_en                        : 1;  /**< Time counter interrupt enable for group X
                                                          TC_EN must be zero when TC_THR==0 */
@@ -1760,9 +1941,9 @@ union cvmx_pow_wq_int_thrx
 	struct cvmx_pow_wq_int_thrx_s         cn56xxp1;
 	struct cvmx_pow_wq_int_thrx_s         cn58xx;
 	struct cvmx_pow_wq_int_thrx_s         cn58xxp1;
-	struct cvmx_pow_wq_int_thrx_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_wq_int_thrx_cn52xx    cn61xx;
+	struct cvmx_pow_wq_int_thrx_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t tc_en                        : 1;  /**< Time counter interrupt enable for group X
                                                          TC_EN must be zero when TC_THR==0 */
@@ -1785,6 +1966,8 @@ union cvmx_pow_wq_int_thrx
 #endif
 	} cn63xx;
 	struct cvmx_pow_wq_int_thrx_cn63xx    cn63xxp1;
+	struct cvmx_pow_wq_int_thrx_cn63xx    cn66xx;
+	struct cvmx_pow_wq_int_thrx_cn52xx    cnf71xx;
 };
 typedef union cvmx_pow_wq_int_thrx cvmx_pow_wq_int_thrx_t;
 
@@ -1795,12 +1978,10 @@ typedef union cvmx_pow_wq_int_thrx cvmx_pow_wq_int_thrx_t;
  *
  * Counts the number of work schedules for each group.  Write to clear.
  */
-union cvmx_pow_ws_pcx
-{
+union cvmx_pow_ws_pcx {
 	uint64_t u64;
-	struct cvmx_pow_ws_pcx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_pow_ws_pcx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t ws_pc                        : 32; /**< Work schedule performance counter for group X */
 #else
@@ -1819,8 +2000,11 @@ union cvmx_pow_ws_pcx
 	struct cvmx_pow_ws_pcx_s              cn56xxp1;
 	struct cvmx_pow_ws_pcx_s              cn58xx;
 	struct cvmx_pow_ws_pcx_s              cn58xxp1;
+	struct cvmx_pow_ws_pcx_s              cn61xx;
 	struct cvmx_pow_ws_pcx_s              cn63xx;
 	struct cvmx_pow_ws_pcx_s              cn63xxp1;
+	struct cvmx_pow_ws_pcx_s              cn66xx;
+	struct cvmx_pow_ws_pcx_s              cnf71xx;
 };
 typedef union cvmx_pow_ws_pcx cvmx_pow_ws_pcx_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-pow.c b/sys/contrib/octeon-sdk/cvmx-pow.c
index f34a9c1..c2e4707 100644
--- a/sys/contrib/octeon-sdk/cvmx-pow.c
+++ b/sys/contrib/octeon-sdk/cvmx-pow.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -62,9 +62,9 @@
  */
 typedef struct
 {
-    cvmx_pow_tag_load_resp_t sstatus[16][8];
-    cvmx_pow_tag_load_resp_t smemload[2048][3];
-    cvmx_pow_tag_load_resp_t sindexload[16][4];
+    cvmx_pow_tag_load_resp_t sstatus[CVMX_MAX_CORES][8];
+    cvmx_pow_tag_load_resp_t smemload[2048][8];
+    cvmx_pow_tag_load_resp_t sindexload[64][8];
 } __cvmx_pow_dump_t;
 
 typedef enum
@@ -73,8 +73,8 @@ typedef enum
     CVMX_POW_LIST_FREE=1,
     CVMX_POW_LIST_INPUT=2,
     CVMX_POW_LIST_CORE=CVMX_POW_LIST_INPUT+8,
-    CVMX_POW_LIST_DESCHED=CVMX_POW_LIST_CORE+16,
-    CVMX_POW_LIST_NOSCHED=CVMX_POW_LIST_DESCHED+16,
+    CVMX_POW_LIST_DESCHED=CVMX_POW_LIST_CORE+32,
+    CVMX_POW_LIST_NOSCHED=CVMX_POW_LIST_DESCHED+64,
 } __cvmx_pow_list_types_t;
 
 static const char *__cvmx_pow_list_names[] = {
@@ -86,14 +86,27 @@ static const char *__cvmx_pow_list_names[] = {
     "Core 4", "Core 5", "Core 6", "Core 7",
     "Core 8", "Core 9", "Core 10", "Core 11",
     "Core 12", "Core 13", "Core 14", "Core 15",
+    "Core 16", "Core 17", "Core 18", "Core 19",
+    "Core 20", "Core 21", "Core 22", "Core 23",
+    "Core 24", "Core 25", "Core 26", "Core 27",
+    "Core 28", "Core 29", "Core 30", "Core 31",
     "Desched 0", "Desched 1", "Desched 2", "Desched 3",
     "Desched 4", "Desched 5", "Desched 6", "Desched 7",
     "Desched 8", "Desched 9", "Desched 10", "Desched 11",
     "Desched 12", "Desched 13", "Desched 14", "Desched 15",
-    "Nosched 0", "Nosched 1", "Nosched 2", "Nosched 3",
-    "Nosched 4", "Nosched 5", "Nosched 6", "Nosched 7",
-    "Nosched 8", "Nosched 9", "Nosched 10", "Nosched 11",
-    "Nosched 12", "Nosched 13", "Nosched 14", "Nosched 15"
+    "Desched 16", "Desched 17", "Desched 18", "Desched 19",
+    "Desched 20", "Desched 21", "Desched 22", "Desched 23",
+    "Desched 24", "Desched 25", "Desched 26", "Desched 27",
+    "Desched 28", "Desched 29", "Desched 30", "Desched 31",
+    "Desched 32", "Desched 33", "Desched 34", "Desched 35",
+    "Desched 36", "Desched 37", "Desched 38", "Desched 39",
+    "Desched 40", "Desched 41", "Desched 42", "Desched 43",
+    "Desched 44", "Desched 45", "Desched 46", "Desched 47",
+    "Desched 48", "Desched 49", "Desched 50", "Desched 51",
+    "Desched 52", "Desched 53", "Desched 54", "Desched 55",
+    "Desched 56", "Desched 57", "Desched 58", "Desched 59",
+    "Desched 60", "Desched 61", "Desched 62", "Desched 63",
+    "Nosched 0" 
 };
 
 
@@ -108,28 +121,18 @@ int cvmx_pow_get_num_entries(void)
         return 64;
     else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
         return 256;
-    else if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    else if (OCTEON_IS_MODEL(OCTEON_CN52XX)
+             || OCTEON_IS_MODEL(OCTEON_CN61XX)
+             || OCTEON_IS_MODEL(OCTEON_CNF71XX))
         return 512;
-    else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+    else if (OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))
 	return 1024;
     else
         return 2048;
 }
 
 
-/**
- * Store the current POW internal state into the supplied
- * buffer. It is recommended that you pass a buffer of at least
- * 128KB. The format of the capture may change based on SDK
- * version and Octeon chip.
- *
- * @param buffer Buffer to store capture into
- * @param buffer_size
- *               The size of the supplied buffer
- *
- * @return Zero on sucess, negative on failure
- */
-int cvmx_pow_capture(void *buffer, int buffer_size)
+static int __cvmx_pow_capture_v1(void *buffer, int buffer_size)
 {
     __cvmx_pow_dump_t *dump = (__cvmx_pow_dump_t*)buffer;
     int num_cores;
@@ -209,6 +212,91 @@ int cvmx_pow_capture(void *buffer, int buffer_size)
     return 0;
 }
 
+static int __cvmx_pow_capture_v2(void *buffer, int buffer_size)
+{
+    __cvmx_pow_dump_t *dump = (__cvmx_pow_dump_t*)buffer;
+    int num_cores;
+    int num_pow_entries = cvmx_pow_get_num_entries();
+    int core;
+    int index;
+    int bits;
+
+    if (buffer_size < (int)sizeof(__cvmx_pow_dump_t))
+    {
+        cvmx_dprintf("cvmx_pow_capture: Buffer too small\n");
+        return -1;
+    }
+
+    num_cores = cvmx_octeon_num_cores();
+
+    /* Read all core related state */
+    for (core=0; core<num_cores; core++)
+    {
+        cvmx_pow_load_addr_t load_addr;
+        load_addr.u64 = 0;
+        load_addr.sstatus_cn68xx.mem_region = CVMX_IO_SEG;
+        load_addr.sstatus_cn68xx.is_io = 1;
+        load_addr.sstatus_cn68xx.did = CVMX_OCT_DID_TAG_TAG5;
+        load_addr.sstatus_cn68xx.coreid = core;
+        for (bits=1; bits<6; bits++)
+        {
+            load_addr.sstatus_cn68xx.opcode = bits;
+            dump->sstatus[core][bits].u64 = cvmx_read_csr(load_addr.u64);
+        }
+    }
+    /* Read all internal POW entries */
+    for (index=0; index<num_pow_entries; index++)
+    {
+        cvmx_pow_load_addr_t load_addr;
+        load_addr.u64 = 0;
+        load_addr.smemload_cn68xx.mem_region = CVMX_IO_SEG;
+        load_addr.smemload_cn68xx.is_io = 1;
+        load_addr.smemload_cn68xx.did = CVMX_OCT_DID_TAG_TAG2;
+        load_addr.smemload_cn68xx.index = index;
+        for (bits=1; bits<5; bits++)
+        {
+            load_addr.smemload_cn68xx.opcode = bits;
+            dump->smemload[index][bits].u64 = cvmx_read_csr(load_addr.u64);
+        }
+    }
+
+    /* Read all group and queue pointers */
+    for (index=0; index<64; index++)
+    {
+        cvmx_pow_load_addr_t load_addr;
+        load_addr.u64 = 0;
+        load_addr.sindexload_cn68xx.mem_region = CVMX_IO_SEG;
+        load_addr.sindexload_cn68xx.is_io = 1;
+        load_addr.sindexload_cn68xx.did = CVMX_OCT_DID_TAG_TAG3;
+        load_addr.sindexload_cn68xx.qos_grp = index;
+        for (bits=1; bits<7; bits++)
+        {
+            load_addr.sindexload_cn68xx.opcode = bits;
+            dump->sindexload[index][bits].u64 = cvmx_read_csr(load_addr.u64);
+        }
+    }
+    return 0;
+}
+
+/**
+ * Store the current POW internal state into the supplied
+ * buffer. It is recommended that you pass a buffer of at least
+ * 128KB. The format of the capture may change based on SDK
+ * version and Octeon chip.
+ *
+ * @param buffer Buffer to store capture into
+ * @param buffer_size
+ *               The size of the supplied buffer
+ *
+ * @return Zero on sucess, negative on failure
+ */
+int cvmx_pow_capture(void *buffer, int buffer_size)
+{
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+        return __cvmx_pow_capture_v2(buffer, buffer_size);
+    else
+        return __cvmx_pow_capture_v1(buffer, buffer_size);
+}
 
 /**
  * Function to display a POW internal queue to the user
@@ -290,7 +378,16 @@ static void __cvmx_pow_display_list_and_walk(__cvmx_pow_list_types_t entry_type,
             {
                 if (__cvmx_pow_entry_mark_list(head, entry_type, entry_list))
                     break;
-                head = dump->smemload[head][0].s_smemload0.next_index;
+                if (octeon_has_feature(OCTEON_FEATURE_PKND))
+                {
+                    if (entry_type >= CVMX_POW_LIST_INPUT && entry_type < CVMX_POW_LIST_CORE)
+                 
+                        head = dump->smemload[head][4].s_smemload3_cn68xx.next_index;
+                    else
+                        head = dump->smemload[head][4].s_smemload3_cn68xx.fwd_index;
+                }
+                else
+                    head = dump->smemload[head][0].s_smemload0.next_index;
             }
             __cvmx_pow_entry_mark_list(tail, entry_type, entry_list);
         }
@@ -298,14 +395,7 @@ static void __cvmx_pow_display_list_and_walk(__cvmx_pow_list_types_t entry_type,
 }
 
 
-/**
- * Dump a POW capture to the console in a human readable format.
- *
- * @param buffer POW capture from cvmx_pow_capture()
- * @param buffer_size
- *               Size of the buffer
- */
-void cvmx_pow_display(void *buffer, int buffer_size)
+void __cvmx_pow_display_v1(void *buffer, int buffer_size)
 {
     __cvmx_pow_dump_t *dump = (__cvmx_pow_dump_t*)buffer;
     int num_pow_entries = cvmx_pow_get_num_entries();
@@ -323,8 +413,6 @@ void cvmx_pow_display(void *buffer, int buffer_size)
     memset(entry_list, 0, sizeof(entry_list));
     num_cores = cvmx_octeon_num_cores();
 
-    printf("POW Display Start\n");
-
     /* Print the free list info */
     __cvmx_pow_display_list_and_walk(CVMX_POW_LIST_FREE, dump, entry_list,
                                      dump->sindexload[0][0].sindexload0.free_val,
@@ -466,7 +554,6 @@ void cvmx_pow_display(void *buffer, int buffer_size)
             printf(" next=%d", dump->smemload[index][0].s_smemload0.next_index);
         if (entry_list[index] >= CVMX_POW_LIST_DESCHED)
         {
-            printf(" prev=%d", dump->smemload[index][1].s_smemload2.fwd_index);
             printf(" nosched=%d", dump->smemload[index][1].s_smemload2.nosched);
             if (dump->smemload[index][1].s_smemload2.pend_switch)
             {
@@ -477,7 +564,225 @@ void cvmx_pow_display(void *buffer, int buffer_size)
         }
         printf("\n");
     }
+}
 
+void __cvmx_pow_display_v2(void *buffer, int buffer_size)
+{
+    __cvmx_pow_dump_t *dump = (__cvmx_pow_dump_t*)buffer;
+    int num_pow_entries = cvmx_pow_get_num_entries();
+    int num_cores;
+    int core;
+    int index;
+    uint8_t entry_list[2048];
+
+    if (buffer_size < (int)sizeof(__cvmx_pow_dump_t))
+    {
+        cvmx_dprintf("cvmx_pow_dump: Buffer too small, pow_dump_t = 0x%x, buffer_size = 0x%x\n", (int)sizeof(__cvmx_pow_dump_t), buffer_size);
+        return;
+    }
+
+    memset(entry_list, 0, sizeof(entry_list));
+    num_cores = cvmx_octeon_num_cores();
+
+    /* Print the free list info */
+    {
+        int valid[3], has_one[3], head[3], tail[3], qnum_head, qnum_tail;
+        int idx;
+
+        valid[0] = dump->sindexload[0][4].sindexload1_cn68xx.queue_val;
+        valid[1] = dump->sindexload[0][5].sindexload1_cn68xx.queue_val;
+        valid[2] = dump->sindexload[0][6].sindexload1_cn68xx.queue_val;
+        has_one[0] = dump->sindexload[0][4].sindexload1_cn68xx.queue_one;
+        has_one[1] = dump->sindexload[0][5].sindexload1_cn68xx.queue_one;
+        has_one[2] = dump->sindexload[0][6].sindexload1_cn68xx.queue_one;
+        head[0] = dump->sindexload[0][4].sindexload1_cn68xx.queue_head;
+        head[1] = dump->sindexload[0][5].sindexload1_cn68xx.queue_head;
+        head[2] = dump->sindexload[0][6].sindexload1_cn68xx.queue_head;
+        tail[0] = dump->sindexload[0][4].sindexload1_cn68xx.queue_tail;
+        tail[1] = dump->sindexload[0][5].sindexload1_cn68xx.queue_tail;
+        tail[2] = dump->sindexload[0][6].sindexload1_cn68xx.queue_tail;
+        qnum_head = dump->sindexload[0][4].sindexload1_cn68xx.qnum_head;
+        qnum_tail = dump->sindexload[0][4].sindexload1_cn68xx.qnum_tail;
+
+        printf("Free List: qnum_head=%d, qnum_tail=%d\n", qnum_head, qnum_tail);
+        printf("Free0: valid=%d, one=%d, head=%llu, tail=%llu\n", valid[0], has_one[0], CAST64(head[0]), CAST64(tail[0]));
+        printf("Free1: valid=%d, one=%d, head=%llu, tail=%llu\n", valid[1], has_one[1], CAST64(head[1]), CAST64(tail[1]));
+        printf("Free2: valid=%d, one=%d, head=%llu, tail=%llu\n", valid[2], has_one[2], CAST64(head[2]), CAST64(tail[2]));
+        
+        idx=qnum_head;
+        while (valid[0] || valid[1] || valid[2])
+        {
+            int qidx = idx % 3;
+
+            if (head[qidx] == tail[qidx])
+                valid[qidx] = 0;
+
+            if (__cvmx_pow_entry_mark_list(head[qidx], CVMX_POW_LIST_FREE, entry_list))   
+                break;
+            head[qidx] = dump->smemload[head[qidx]][4].s_smemload3_cn68xx.fwd_index;
+            //printf("qidx = %d, idx = %d, head[qidx] = %d\n", qidx, idx, head[qidx]);
+            idx++;
+        }
+    }
+            
+    /* Print the core state */
+    for (core = 0; core < num_cores; core++)
+    {
+        int pendtag = 1;
+        int pendwqp = 2;
+        int tag = 3;
+        int wqp = 4;
+        int links = 5;
+
+        printf("Core %d State: tag=%s,0x%08x", core, 
+               OCT_TAG_TYPE_STRING(dump->sstatus[core][tag].s_sstatus2_cn68xx.tag_type),
+               dump->sstatus[core][tag].s_sstatus2_cn68xx.tag);
+        if (dump->sstatus[core][tag].s_sstatus2_cn68xx.tag_type != CVMX_POW_TAG_TYPE_NULL_NULL)
+        {
+            __cvmx_pow_entry_mark_list(dump->sstatus[core][tag].s_sstatus2_cn68xx.index, CVMX_POW_LIST_CORE + core, entry_list);
+            printf(" grp=%d",                   dump->sstatus[core][tag].s_sstatus2_cn68xx.grp);
+            printf(" wqp=0x%016llx",            CAST64(dump->sstatus[core][wqp].s_sstatus3_cn68xx.wqp));
+            printf(" index=%d",                 dump->sstatus[core][tag].s_sstatus2_cn68xx.index);
+            if (dump->sstatus[core][links].s_sstatus4_cn68xx.head)
+                printf(" head");
+            else
+                printf(" prev=%d", dump->sstatus[core][links].s_sstatus4_cn68xx.revlink_index);
+            if (dump->sstatus[core][links].s_sstatus4_cn68xx.tail)
+                printf(" tail");
+            else
+                printf(" next=%d", dump->sstatus[core][links].s_sstatus4_cn68xx.link_index);
+        }
+        if (dump->sstatus[core][pendtag].s_sstatus0_cn68xx.pend_switch)
+        {
+            printf(" pend_switch=%d",           dump->sstatus[core][pendtag].s_sstatus0_cn68xx.pend_switch);
+        }
+                                                                                
+        if (dump->sstatus[core][pendtag].s_sstatus0_cn68xx.pend_desched)
+        {
+            printf(" pend_desched=%d",          dump->sstatus[core][pendtag].s_sstatus0_cn68xx.pend_desched);
+            printf(" pend_nosched=%d",          dump->sstatus[core][pendtag].s_sstatus0_cn68xx.pend_nosched);
+        }
+        if (dump->sstatus[core][pendtag].s_sstatus0_cn68xx.pend_get_work)
+        {
+            if (dump->sstatus[core][pendtag].s_sstatus0_cn68xx.pend_get_work_wait)
+                printf(" (Waiting for work)");
+            else
+                printf(" (Getting work)");
+        }
+        if (dump->sstatus[core][pendtag].s_sstatus0_cn68xx.pend_alloc_we)
+            printf(" pend_alloc_we=%d",          dump->sstatus[core][pendtag].s_sstatus0_cn68xx.pend_alloc_we);
+        if (dump->sstatus[core][pendtag].s_sstatus0_cn68xx.pend_nosched_clr)
+        {
+            printf(" pend_nosched_clr=%d",      dump->sstatus[core][pendtag].s_sstatus0_cn68xx.pend_nosched_clr);
+            printf(" pend_index=%d",            dump->sstatus[core][pendtag].s_sstatus0_cn68xx.pend_index);
+        }
+        if (dump->sstatus[core][pendtag].s_sstatus0_cn68xx.pend_switch)
+        {
+            printf(" pending tag=%s,0x%08x",
+                   OCT_TAG_TYPE_STRING(dump->sstatus[core][pendtag].s_sstatus0_cn68xx.pend_type),
+                   dump->sstatus[core][pendtag].s_sstatus0_cn68xx.pend_tag);
+        }
+        if (dump->sstatus[core][pendwqp].s_sstatus1_cn68xx.pend_nosched_clr)
+            printf(" pend_wqp=0x%016llx\n",     CAST64(dump->sstatus[core][pendwqp].s_sstatus1_cn68xx.pend_wqp));
+        printf("\n");
+    }
+
+    /* Print out the state of the nosched list and the 16 deschedule lists. */
+    __cvmx_pow_display_list_and_walk(CVMX_POW_LIST_NOSCHED, dump, entry_list,
+                            dump->sindexload[0][3].sindexload0_cn68xx.queue_val,
+                            dump->sindexload[0][3].sindexload0_cn68xx.queue_one,
+                            dump->sindexload[0][3].sindexload0_cn68xx.queue_head,
+                            dump->sindexload[0][3].sindexload0_cn68xx.queue_tail);
+    for (index=0; index<64; index++)
+    {
+        __cvmx_pow_display_list_and_walk(CVMX_POW_LIST_DESCHED + index, dump, entry_list,
+                                dump->sindexload[index][2].sindexload0_cn68xx.queue_val,
+                                dump->sindexload[index][2].sindexload0_cn68xx.queue_one,
+                                dump->sindexload[index][2].sindexload0_cn68xx.queue_head,
+                                dump->sindexload[index][2].sindexload0_cn68xx.queue_tail);
+    }
+
+    /* Print out the state of the 8 internal input queues */
+    for (index=0; index<8; index++)
+    {
+        __cvmx_pow_display_list_and_walk(CVMX_POW_LIST_INPUT + index, dump, entry_list,
+                                dump->sindexload[index][1].sindexload0_cn68xx.queue_val,
+                                dump->sindexload[index][1].sindexload0_cn68xx.queue_one,
+                                dump->sindexload[index][1].sindexload0_cn68xx.queue_head,
+                                dump->sindexload[index][1].sindexload0_cn68xx.queue_tail);
+    }
+
+    /* Print out the state of the 16 memory queues */
+    for (index=0; index<8; index++)
+    {
+        const char *name;
+        if (dump->sindexload[index][1].sindexload0_cn68xx.queue_head)
+            name = "Queue %da Memory (is head)";
+        else
+            name = "Queue %da Memory";
+        __cvmx_pow_display_list(name, index,
+                                dump->sindexload[index][1].sindexload0_cn68xx.queue_val,
+                                dump->sindexload[index][1].sindexload0_cn68xx.queue_one,
+                                dump->sindexload[index][1].sindexload0_cn68xx.queue_head,
+                                dump->sindexload[index][1].sindexload0_cn68xx.queue_tail);
+        if (dump->sindexload[index+8][1].sindexload0_cn68xx.queue_head)
+            name = "Queue %db Memory (is head)";
+        else
+            name = "Queue %db Memory";
+        __cvmx_pow_display_list(name, index,
+                                dump->sindexload[index+8][1].sindexload0_cn68xx.queue_val,
+                                dump->sindexload[index+8][1].sindexload0_cn68xx.queue_one,
+                                dump->sindexload[index+8][1].sindexload0_cn68xx.queue_head,
+                                dump->sindexload[index+8][1].sindexload0_cn68xx.queue_tail);
+    }
+
+    /* Print out each of the internal POW entries. Each entry has a tag, group,
+       wqe, and possibly a next pointer. The next pointer is only valid if this
+       entry isn't make as a tail */
+    for (index=0; index<num_pow_entries; index++)
+    {
+        printf("Entry %d(%-10s): tag=%s,0x%08x grp=%d wqp=0x%016llx", index,
+               __cvmx_pow_list_names[entry_list[index]],
+               OCT_TAG_TYPE_STRING(dump->smemload[index][1].s_smemload0_cn68xx.tag_type),
+               dump->smemload[index][1].s_smemload0_cn68xx.tag,
+               dump->smemload[index][2].s_smemload1_cn68xx.grp,
+               CAST64(dump->smemload[index][2].s_smemload1_cn68xx.wqp));
+        if (dump->smemload[index][1].s_smemload0_cn68xx.tail)
+            printf(" tail");
+        else
+            printf(" next=%d", dump->smemload[index][4].s_smemload3_cn68xx.fwd_index);
+        if (entry_list[index] >= CVMX_POW_LIST_DESCHED)
+        {
+            printf(" prev=%d", dump->smemload[index][4].s_smemload3_cn68xx.fwd_index);
+            printf(" nosched=%d", dump->smemload[index][1].s_smemload1_cn68xx.nosched);
+            if (dump->smemload[index][3].s_smemload2_cn68xx.pend_switch)
+            {
+                printf(" pending tag=%s,0x%08x",
+                       OCT_TAG_TYPE_STRING(dump->smemload[index][3].s_smemload2_cn68xx.pend_type),
+                       dump->smemload[index][3].s_smemload2_cn68xx.pend_tag);
+            }
+        }
+        printf("\n");
+    }
+}
+
+/**
+ * Dump a POW capture to the console in a human readable format.
+ *
+ * @param buffer POW capture from cvmx_pow_capture()
+ * @param buffer_size
+ *               Size of the buffer
+ */
+void cvmx_pow_display(void *buffer, int buffer_size)
+{
+    printf("POW Display Start\n");
+
+    if (octeon_has_feature(OCTEON_FEATURE_PKND))
+        __cvmx_pow_display_v2(buffer, buffer_size);
+    else
+        __cvmx_pow_display_v1(buffer, buffer_size);
+        
     printf("POW Display End\n");
+    return;
 }
 
diff --git a/sys/contrib/octeon-sdk/cvmx-pow.h b/sys/contrib/octeon-sdk/cvmx-pow.h
index a398a41..a5771c6 100644
--- a/sys/contrib/octeon-sdk/cvmx-pow.h
+++ b/sys/contrib/octeon-sdk/cvmx-pow.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2011  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -61,7 +61,7 @@
  * - WQE pointer not matching the one attached to the core by
  *   the POW.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_POW_H__
@@ -70,11 +70,13 @@
 #include "cvmx-scratch.h"
 #include "cvmx-wqe.h"
 
-#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx-sso-defs.h>
+#else
 #include "cvmx-warn.h"
 #endif
 
-#ifdef	__cplusplus
+#ifdef  __cplusplus
 extern "C" {
 #endif
 
@@ -145,7 +147,7 @@ typedef union
     uint64_t u64;
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t              no_sched  : 1; /**< don't reschedule this entry. no_sched is used for CVMX_POW_TAG_OP_SWTAG_DESCH and CVMX_POW_TAG_OP_DESCH */
         uint64_t                unused  : 2;
         uint64_t                 index  :13; /**< contains index of entry for a CVMX_POW_TAG_OP_*_NSCHED */
@@ -166,9 +168,82 @@ typedef union
         uint64_t                unused  : 2;
         uint64_t              no_sched  : 1;
 #endif
-    } s;
+    } s_cn38xx;
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t              no_sched  : 1; /**< don't reschedule this entry. no_sched is used for CVMX_POW_TAG_OP_SWTAG_DESCH and CVMX_POW_TAG_OP_DESCH */
+        cvmx_pow_tag_op_t          op   : 4; /**< the operation to perform */
+        uint64_t               unused1  : 4;
+        uint64_t                 index  :11; /**< contains index of entry for a CVMX_POW_TAG_OP_*_NSCHED */
+        uint64_t               unused2  : 1;
+        uint64_t                   grp  : 6; /**< the group that the work queue entry will be scheduled to grp is used for CVMX_POW_TAG_OP_ADDWQ, CVMX_POW_TAG_OP_SWTAG_FULL, CVMX_POW_TAG_OP_SWTAG_DESCH, and CVMX_POW_TAG_OP_UPDATE_WQP_GRP */
+        uint64_t               unused3  : 3;
+        cvmx_pow_tag_type_t        type : 2; /**< the type of the tag. type is used for everything except CVMX_POW_TAG_OP_DESCH, CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and CVMX_POW_TAG_OP_*_NSCHED */
+        uint64_t                   tag  :32; /**< the actual tag. tag is used for everything except CVMX_POW_TAG_OP_DESCH, CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and CVMX_POW_TAG_OP_*_NSCHED */
+#else
+        uint64_t                   tag  :32;
+        cvmx_pow_tag_type_t        type : 2;
+        uint64_t               unused3  : 3;
+        uint64_t                   grp  : 6;
+        uint64_t               unused2  : 1;
+        uint64_t                 index  :11;
+        uint64_t               unused1  : 4;
+        cvmx_pow_tag_op_t          op   : 4;
+        uint64_t              no_sched  : 1;
+#endif
+    } s_cn68xx_clr;
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t              no_sched  : 1; /**< don't reschedule this entry. no_sched is used for CVMX_POW_TAG_OP_SWTAG_DESCH and CVMX_POW_TAG_OP_DESCH */
+        cvmx_pow_tag_op_t          op   : 4; /**< the operation to perform */
+        uint64_t               unused1  : 12;
+        uint64_t                    qos : 3; /**< contains index of entry for a CVMX_POW_TAG_OP_*_NSCHED */
+        uint64_t               unused2  : 1;
+        uint64_t                   grp  : 6; /**< the group that the work queue entry will be scheduled to grp is used for CVMX_POW_TAG_OP_ADDWQ, CVMX_POW_TAG_OP_SWTAG_FULL, CVMX_POW_TAG_OP_SWTAG_DESCH, and CVMX_POW_TAG_OP_UPDATE_WQP_GRP */
+        uint64_t               unused3  : 3;
+        cvmx_pow_tag_type_t        type : 2; /**< the type of the tag. type is used for everything except CVMX_POW_TAG_OP_DESCH, CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and CVMX_POW_TAG_OP_*_NSCHED */
+        uint64_t                   tag  :32; /**< the actual tag. tag is used for everything except CVMX_POW_TAG_OP_DESCH, CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and CVMX_POW_TAG_OP_*_NSCHED */
+#else
+        uint64_t                   tag  :32;
+        cvmx_pow_tag_type_t        type : 2;
+        uint64_t               unused3  : 3;
+        uint64_t                   grp  : 6;
+        uint64_t               unused2  : 1;
+        uint64_t                   qos  : 3;
+        uint64_t               unused1  : 12;
+        cvmx_pow_tag_op_t          op   : 4;
+        uint64_t              no_sched  : 1;
+#endif
+    } s_cn68xx_add;
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t              no_sched  : 1; /**< don't reschedule this entry. no_sched is used for CVMX_POW_TAG_OP_SWTAG_DESCH and CVMX_POW_TAG_OP_DESCH */
+        cvmx_pow_tag_op_t          op   : 4; /**< the operation to perform */
+        uint64_t               unused1  : 16;
+        uint64_t                   grp  : 6; /**< the group that the work queue entry will be scheduled to grp is used for CVMX_POW_TAG_OP_ADDWQ, CVMX_POW_TAG_OP_SWTAG_FULL, CVMX_POW_TAG_OP_SWTAG_DESCH, and CVMX_POW_TAG_OP_UPDATE_WQP_GRP */
+        uint64_t               unused3  : 3;
+        cvmx_pow_tag_type_t        type : 2; /**< the type of the tag. type is used for everything except CVMX_POW_TAG_OP_DESCH, CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and CVMX_POW_TAG_OP_*_NSCHED */
+        uint64_t                   tag  :32; /**< the actual tag. tag is used for everything except CVMX_POW_TAG_OP_DESCH, CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and CVMX_POW_TAG_OP_*_NSCHED */
+#else
+        uint64_t                   tag  :32;
+        cvmx_pow_tag_type_t        type : 2;
+        uint64_t               unused3  : 3;
+        uint64_t                   grp  : 6;
+        uint64_t               unused1  : 16;
+        cvmx_pow_tag_op_t          op   : 4;
+        uint64_t              no_sched  : 1;
+#endif
+    } s_cn68xx_other;
+
 } cvmx_pow_tag_req_t;
 
+typedef struct {
+    uint32_t tag;
+    uint16_t index;
+    uint8_t  grp;
+    uint8_t tag_type;
+}cvmx_pow_tag_info_t;
+
 /**
  * This structure describes the address to load stuff from POW
  */
@@ -181,7 +256,7 @@ typedef union
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    mem_region      : 2;    /**< Mips64 address region. Should be CVMX_IO_SEG */
         uint64_t    reserved_49_61  : 13;   /**< Must be zero */
         uint64_t    is_io           : 1;    /**< Must be one */
@@ -205,7 +280,7 @@ typedef union
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    mem_region      : 2;    /**< Mips64 address region. Should be CVMX_IO_SEG */
         uint64_t    reserved_49_61  : 13;   /**< Must be zero */
         uint64_t    is_io           : 1;    /**< Must be one */
@@ -231,11 +306,39 @@ typedef union
     } sstatus;
 
     /**
+     * Address for loads to get 68XX SS0 internal status
+     */
+    struct
+    {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t    mem_region      : 2;    /**< Mips64 address region. Should be CVMX_IO_SEG */
+        uint64_t    reserved_49_61  : 13;   /**< Must be zero */
+        uint64_t    is_io           : 1;    /**< Must be one */
+        uint64_t    did             : 8;    /**< the ID of POW -- did<2:0> == 1 in this case */
+        uint64_t    reserved_14_39  : 26;   /**< Must be zero */
+        uint64_t    coreid          : 5;    /**< The core id to get status for */
+        uint64_t    reserved_6_8    : 3;
+        uint64_t    opcode          : 3;    /**< Status operation */
+        uint64_t    reserved_0_2    : 3;    /**< Must be zero */
+#else
+        uint64_t    reserved_0_2    : 3;
+        uint64_t    opcode          : 3;
+        uint64_t    reserved_6_8    : 3;
+        uint64_t    coreid          : 5;
+        uint64_t    reserved_14_39  : 26;
+        uint64_t    did             : 8;
+        uint64_t    is_io           : 1;
+        uint64_t    reserved_49_61  : 13;
+        uint64_t    mem_region      : 2;
+#endif
+    } sstatus_cn68xx;
+
+    /**
      * Address for memory loads to get POW internal state
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    mem_region      : 2;    /**< Mips64 address region. Should be CVMX_IO_SEG */
         uint64_t    reserved_49_61  : 13;   /**< Must be zero */
         uint64_t    is_io           : 1;    /**< Must be one */
@@ -261,11 +364,39 @@ typedef union
     } smemload;
 
     /**
+     * Address for memory loads to get SSO internal state
+     */
+    struct
+    {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t    mem_region      : 2;    /**< Mips64 address region. Should be CVMX_IO_SEG */
+        uint64_t    reserved_49_61  : 13;   /**< Must be zero */
+        uint64_t    is_io           : 1;    /**< Must be one */
+        uint64_t    did             : 8;    /**< the ID of SSO - did<2:0> == 2 in this case */
+        uint64_t    reserved_20_39  : 20;   /**< Must be zero */
+        uint64_t    index           : 11;   /**< SSO memory index */
+        uint64_t    reserved_6_8    : 3;    /**< Must be zero */
+        uint64_t    opcode          : 3;    /**< Read TAG/WQ pointer/pending tag/next potr */
+        uint64_t    reserved_0_2    : 3;    /**< Must be zero */
+#else
+        uint64_t    reserved_0_2    : 3;
+        uint64_t    opcode          : 3;
+        uint64_t    reserved_3_5    : 3;
+        uint64_t    index           : 11;
+        uint64_t    reserved_20_39  : 20;
+        uint64_t    did             : 8;
+        uint64_t    is_io           : 1;
+        uint64_t    reserved_49_61  : 13;
+        uint64_t    mem_region      : 2;
+#endif
+    } smemload_cn68xx;
+
+    /**
      * Address for index/pointer loads
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    mem_region      : 2;    /**< Mips64 address region. Should be CVMX_IO_SEG */
         uint64_t    reserved_49_61  : 13;   /**< Must be zero */
         uint64_t    is_io           : 1;    /**< Must be one */
@@ -305,6 +436,36 @@ typedef union
     } sindexload;
 
     /**
+     * Address for a Index/Pointer loads to get SSO internal state
+     */
+    struct
+    {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t    mem_region      : 2;    /**< Mips64 address region. Should be CVMX_IO_SEG */
+        uint64_t    reserved_49_61  : 13;   /**< Must be zero */
+        uint64_t    is_io           : 1;    /**< Must be one */
+        uint64_t    did             : 8;    /**< the ID of SSO - did<2:0> == 2 in this case */
+        uint64_t    reserved_15_39  : 25;   /**< Must be zero */
+        uint64_t    qos_grp         : 6;    /**< When opcode = IPL_IQ, this field specifies IQ (or QOS).
+                                                 When opcode = IPL_DESCHED, this field specifies the group.
+                                                 This field is reserved for all other opcodes. */
+        uint64_t    reserved_6_8    : 3;    /**< Must be zero */
+        uint64_t    opcode          : 3;    /**< Read TAG/WQ pointer/pending tag/next potr */
+        uint64_t    reserved_0_2    : 3;    /**< Must be zero */
+#else
+        uint64_t    reserved_0_2    : 3;
+        uint64_t    opcode          : 3;
+        uint64_t    reserved_3_5    : 3;
+        uint64_t    qos_grp         : 6;
+        uint64_t    reserved_15_39  : 25;
+        uint64_t    did             : 8;
+        uint64_t    is_io           : 1;
+        uint64_t    reserved_49_61  : 13;
+        uint64_t    mem_region      : 2;
+#endif
+    } sindexload_cn68xx;
+
+    /**
      * address for NULL_RD request (did<2:0> == 4)
      * when this is read, HW attempts to change the state to NULL if it is NULL_NULL
      * (the hardware cannot switch from NULL_NULL to NULL if a POW entry is not available -
@@ -313,7 +474,7 @@ typedef union
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    mem_region      : 2;    /**< Mips64 address region. Should be CVMX_IO_SEG */
         uint64_t    reserved_49_61  : 13;   /**< Must be zero */
         uint64_t    is_io           : 1;    /**< Must be one */
@@ -341,7 +502,7 @@ typedef union
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    no_work          : 1;   /**< Set when no new work queue entry was returned.
                                                 If there was de-scheduled work, the HW will definitely
                                                 return it. When this bit is set, it could mean
@@ -365,7 +526,7 @@ typedef union
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved_62_63  : 2;
         uint64_t    pend_switch     : 1;    /**< Set when there is a pending non-NULL SWTAG or
                                                 SWTAG_FULL, and the POW entry has not left the list for the original tag. */
@@ -406,11 +567,47 @@ typedef union
     } s_sstatus0;
 
     /**
+     * Result for a SSO Status Load (when opcode is SL_PENDTAG)
+     */
+    struct
+    {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t    pend_switch     : 1;    /**< Set when there is a pending non-UNSCHEDULED SWTAG or
+                                                SWTAG_FULL, and the SSO entry has not left the list for the original tag. */
+        uint64_t    pend_get_work   : 1;    /**< Set when there is a pending GET_WORK */
+        uint64_t    pend_get_work_wait: 1;  /**< when pend_get_work is set, this biit indicates that the 
+                                                 wait bit was set. */
+        uint64_t    pend_nosched    : 1;    /**< Set when nosched is desired and pend_desched is set. */
+        uint64_t    pend_nosched_clr: 1;    /**< Set when there is a pending CLR_NSCHED. */
+        uint64_t    pend_desched    : 1;    /**< Set when there is a pending DESCHED or SWTAG_DESCHED. */
+        uint64_t    pend_alloc_we   : 1;    /**< Set when there is a pending ALLOC_WE. */
+        uint64_t    reserved_48_56  : 9;
+        uint64_t    pend_index      : 11;   /**< This is the index when pend_nosched_clr is set. */
+        uint64_t    reserved_34_36  : 3;
+        uint64_t    pend_type       : 2;    /**< This is the tag type when pend_switch is set. */
+        uint64_t    pend_tag        : 32;   /**< This is the tag when pend_switch is set. */
+#else
+        uint64_t    pend_tag        : 32;
+        uint64_t    pend_type       : 2;
+        uint64_t    reserved_34_36  : 3;
+        uint64_t    pend_index      : 11;
+        uint64_t    reserved_48_56  : 9;
+        uint64_t    pend_alloc_we   : 1;
+        uint64_t    pend_desched    : 1;
+        uint64_t    pend_nosched_clr: 1;
+        uint64_t    pend_nosched    : 1;
+        uint64_t    pend_get_work_wait: 1;
+        uint64_t    pend_get_work   : 1;
+        uint64_t    pend_switch     : 1;
+#endif
+    } s_sstatus0_cn68xx;
+
+    /**
      * Result for a POW Status Load (when get_cur==0 and get_wqp==1)
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved_62_63  : 2;
         uint64_t    pend_switch     : 1;    /**< Set when there is a pending non-NULL SWTAG or
                                                 SWTAG_FULL, and the POW entry has not left the list for the original tag. */
@@ -447,11 +644,45 @@ typedef union
     } s_sstatus1;
 
     /**
+     * Result for a SSO Status Load (when opcode is SL_PENDWQP)
+     */
+    struct
+    {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t    pend_switch     : 1;    /**< Set when there is a pending non-UNSCHEDULED SWTAG or
+                                                SWTAG_FULL, and the SSO entry has not left the list for the original tag. */
+        uint64_t    pend_get_work   : 1;    /**< Set when there is a pending GET_WORK */
+        uint64_t    pend_get_work_wait: 1;  /**< when pend_get_work is set, this biit indicates that the 
+                                                 wait bit was set. */
+        uint64_t    pend_nosched    : 1;    /**< Set when nosched is desired and pend_desched is set. */
+        uint64_t    pend_nosched_clr: 1;    /**< Set when there is a pending CLR_NSCHED. */
+        uint64_t    pend_desched    : 1;    /**< Set when there is a pending DESCHED or SWTAG_DESCHED. */
+        uint64_t    pend_alloc_we   : 1;    /**< Set when there is a pending ALLOC_WE. */
+        uint64_t    reserved_51_56  : 6;
+        uint64_t    pend_index      : 11;   /**< This is the index when pend_nosched_clr is set. */
+        uint64_t    reserved_38_39  : 2;
+        uint64_t    pend_wqp        : 38;   /**< This is the wqp when pend_nosched_clr is set. */
+#else
+        uint64_t    pend_wqp        : 38;
+        uint64_t    reserved_38_39  : 2;
+        uint64_t    pend_index      : 11;
+        uint64_t    reserved_51_56  : 6;
+        uint64_t    pend_alloc_we   : 1;
+        uint64_t    pend_desched    : 1;
+        uint64_t    pend_nosched_clr: 1;
+        uint64_t    pend_nosched    : 1;
+        uint64_t    pend_get_work_wait: 1;
+        uint64_t    pend_get_work   : 1;
+        uint64_t    pend_switch     : 1;
+#endif
+    } s_sstatus1_cn68xx;
+
+    /**
      * Result for a POW Status Load (when get_cur==1, get_wqp==0, and get_rev==0)
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved_62_63  : 2;
         uint64_t    link_index      : 11;    /**< Points to the next POW entry in the tag list when tail == 0 (and
                                                 tag_type is not NULL or NULL_NULL). */
@@ -478,11 +709,44 @@ typedef union
     } s_sstatus2;
 
     /**
+     * Result for a SSO Status Load (when opcode is SL_TAG)
+     */
+    struct
+    {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t    reserved_57_63  : 7;
+        uint64_t    index           : 11;   /**< The SSO entry attached to the core. */
+        uint64_t    reserved_45     : 1;
+        uint64_t    grp             : 6;    /**< The group attached to the core (updated when new tag list entered on
+                                                 SWTAG_FULL). */
+        uint64_t    head            : 1;    /**< Set when this SSO entry is at the head of its tag list (also set when in the
+                                                 UNSCHEDULED or EMPTY state). */
+        uint64_t    tail            : 1;    /**< Set when this SSO entry is at the tail of its tag list (also set when in the
+                                                 UNSCHEDULED or EMPTY state). */
+        uint64_t    reserved_34_36  : 3;
+        uint64_t    tag_type        : 2;    /**< The tag type attached to the core (updated when new tag list entered
+                                                 on SWTAG, SWTAG_FULL, or SWTAG_DESCHED). */
+        uint64_t    tag             : 32;   /**< The tag attached to the core (updated when new tag list entered on SWTAG,
+                                                 SWTAG_FULL, or SWTAG_DESCHED). */
+#else
+        uint64_t    tag             : 32;
+        uint64_t    tag_type        : 2;
+        uint64_t    reserved_34_36  : 3;
+        uint64_t    tail            : 1;
+        uint64_t    head            : 1;
+        uint64_t    grp             : 6;
+        uint64_t    reserved_45     : 1;
+        uint64_t    index           : 11;
+        uint64_t    reserved_57_63  : 7;
+#endif
+    } s_sstatus2_cn68xx;
+
+    /**
      * Result for a POW Status Load (when get_cur==1, get_wqp==0, and get_rev==1)
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved_62_63  : 2;
         uint64_t    revlink_index   : 11;   /**< Points to the prior POW entry in the tag list when head == 0
                                                 (and tag_type is not NULL or NULL_NULL). This field is unpredictable
@@ -510,11 +774,34 @@ typedef union
     } s_sstatus3;
 
     /**
+     * Result for a SSO Status Load (when opcode is SL_WQP)
+     */
+    struct
+    {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t    reserved_58_63  : 6;
+        uint64_t    index           : 11;   /**< The SSO entry attached to the core. */
+        uint64_t    reserved_46     : 1;
+        uint64_t    grp             : 6;    /**< The group attached to the core (updated when new tag list entered on
+                                                 SWTAG_FULL). */
+        uint64_t    reserved_38_39  : 2;
+        uint64_t    wqp             : 38;   /**< The wqp attached to the core (updated when new tag list entered on SWTAG_FULL). */
+#else
+        uint64_t    wqp             : 38;
+        uint64_t    reserved_38_39  : 2;
+        uint64_t    grp             : 6;
+        uint64_t    reserved_46     : 1;
+        uint64_t    index           : 11;
+        uint64_t    reserved_58_63  : 6;
+#endif
+    } s_sstatus3_cn68xx;
+
+    /**
      * Result for a POW Status Load (when get_cur==1, get_wqp==1, and get_rev==0)
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved_62_63  : 2;
         uint64_t    link_index      : 11;    /**< Points to the next POW entry in the tag list when tail == 0 (and
                                                 tag_type is not NULL or NULL_NULL). */
@@ -531,11 +818,44 @@ typedef union
     } s_sstatus4;
 
     /**
+     * Result for a SSO Status Load (when opcode is SL_LINKS)
+     */
+    struct
+    {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t    reserved_46_63  : 18;
+        uint64_t    index           : 11;   /**< The SSO entry attached to the core. */
+        uint64_t    reserved_34     : 1;
+        uint64_t    grp             : 6;    /**< The group attached to the core (updated when new tag list entered on
+                                                 SWTAG_FULL). */
+        uint64_t    head            : 1;    /**< Set when this SSO entry is at the head of its tag list (also set when in the
+                                                 UNSCHEDULED or EMPTY state). */
+        uint64_t    tail            : 1;    /**< Set when this SSO entry is at the tail of its tag list (also set when in the
+                                                 UNSCHEDULED or EMPTY state). */
+        uint64_t    reserved_24_25  : 2;
+        uint64_t    revlink_index   : 11;   /**< Points to the prior SSO entry in the tag list when head==0 (and tag_type is not UNSCHEDULED or EMPTY). */
+        uint64_t    reserved_11_12  : 2;
+        uint64_t    link_index      : 11;   /**< Points to the next SSO entry in the tag list when tail==0 (and tag_type is not UNSCHEDULDED or EMPTY). */
+#else
+        uint64_t    link_index      : 11;
+        uint64_t    reserved_11_12  : 2;
+        uint64_t    revlink_index   : 11;
+        uint64_t    reserved_24_25  : 2;
+        uint64_t    tail            : 1;
+        uint64_t    head            : 1;
+        uint64_t    grp             : 6;
+        uint64_t    reserved_34     : 1;
+        uint64_t    index           : 11;
+        uint64_t    reserved_46_63  : 18;
+#endif
+    } s_sstatus4_cn68xx;
+
+    /**
      * Result for a POW Status Load (when get_cur==1, get_wqp==1, and get_rev==1)
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved_62_63  : 2;
         uint64_t    revlink_index   : 11;   /**< Points to the prior POW entry in the tag list when head == 0
                                                 (and tag_type is not NULL or NULL_NULL). This field is unpredictable
@@ -557,7 +877,7 @@ typedef union
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved_51_63  : 13;
         uint64_t    next_index      : 11;    /**< The next entry in the input, free, descheduled_head list
                                                 (unpredictable if entry is the tail of the list). */
@@ -579,11 +899,32 @@ typedef union
     } s_smemload0;
 
     /**
+     * Result For SSO Memory Load (opcode is ML_TAG)
+     */
+    struct
+    {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t    reserved_38_63  : 26;
+        uint64_t    tail            : 1;    /**< Set when this SSO entry is at the tail of its tag list (also set when in the
+                                                NULL or NULL_NULL state). */
+        uint64_t    reserved_34_36  : 3;
+        uint64_t    tag_type        : 2;    /**< The tag type of the SSO entry. */
+        uint64_t    tag             : 32;   /**< The tag of the SSO entry. */
+#else
+        uint64_t    tag             : 32;
+        uint64_t    tag_type        : 2;
+        uint64_t    reserved_34_36  : 3;
+        uint64_t    tail            : 1;
+        uint64_t    reserved_38_63  : 26;
+#endif
+    } s_smemload0_cn68xx;
+
+    /**
      * Result For POW Memory Load (get_des == 0 and get_wqp == 1)
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved_51_63  : 13;
         uint64_t    next_index      : 11;    /**< The next entry in the input, free, descheduled_head list
                                                 (unpredictable if entry is the tail of the list). */
@@ -598,11 +939,33 @@ typedef union
     } s_smemload1;
 
     /**
+     * Result For SSO Memory Load (opcode is ML_WQPGRP)
+     */
+    struct
+    {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t    reserved_48_63  : 16;
+        uint64_t    nosched         : 1;    /**< The nosched bit for the SSO entry. */
+        uint64_t    reserved_46     : 1;
+        uint64_t    grp             : 6;    /**< The group of the SSO entry. */
+        uint64_t    reserved_38_39  : 2;
+        uint64_t    wqp             : 38;   /**< The WQP held in the SSO entry. */
+#else
+        uint64_t    wqp             : 38;
+        uint64_t    reserved_38_39  : 2;
+        uint64_t    grp             : 6;
+        uint64_t    reserved_46     : 1;
+        uint64_t    nosched         : 1;
+        uint64_t    reserved_51_63  : 16;
+#endif
+    } s_smemload1_cn68xx;
+
+    /**
      * Result For POW Memory Load (get_des == 1)
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved_51_63  : 13;
         uint64_t    fwd_index       : 11;   /**< The next entry in the tag list connected to the descheduled head. */
         uint64_t    grp             : 4;    /**< The group of the POW entry. */
@@ -622,11 +985,51 @@ typedef union
     } s_smemload2;
 
     /**
+     * Result For SSO Memory Load (opcode is ML_PENTAG)
+     */
+    struct
+    {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t    reserved_38_63  : 26;
+        uint64_t    pend_switch     : 1;    /**< Set when there is a pending non-UNSCHEDULED SWTAG or
+                                                 SWTAG_FULL, and the SSO entry has not left the list for the original tag. */
+        uint64_t    reserved_34_36  : 3;
+        uint64_t    pend_type       : 2;    /**< The next tag type for the new tag list when pend_switch is set. */
+        uint64_t    pend_tag        : 32;   /**< The next tag for the new tag list when pend_switch is set. */
+#else
+        uint64_t    pend_tag        : 32;
+        uint64_t    pend_type       : 2;
+        uint64_t    reserved_34_36  : 3;
+        uint64_t    pend_switch     : 1;
+        uint64_t    reserved_38_63  : 26;
+#endif
+    } s_smemload2_cn68xx;
+
+    /**
+     * Result For SSO Memory Load (opcode is ML_LINKS)
+     */
+    struct
+    {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t    reserved_24_63  : 40;
+        uint64_t    fwd_index       : 11;   /**< The next entry in the tag list connected to the descheduled head. */
+        uint64_t    reserved_11_12  : 2;
+        uint64_t    next_index      : 11;   /**< The next entry in the input, free, descheduled_head list
+                                                 (unpredicatble if entry is the tail of the list). */
+#else
+        uint64_t    next_index      : 11;
+        uint64_t    reserved_11_12  : 2;
+        uint64_t    fwd_index       : 11;
+        uint64_t    reserved_24_63  : 40;
+#endif
+    } s_smemload3_cn68xx;
+
+    /**
      * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 0)
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved_52_63  : 12;
         uint64_t    free_val        : 1;    /**< - set when there is one or more POW entries on the free list. */
         uint64_t    free_one        : 1;    /**< - set when there is exactly one POW entry on the free list. */
@@ -658,11 +1061,35 @@ typedef union
     } sindexload0;
 
     /**
+     * Result for SSO Index/Pointer Load(opcode == IPL_IQ/IPL_DESCHED/IPL_NOSCHED)
+     */
+    struct
+    {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t    reserved_28_63  : 36;
+        uint64_t    queue_val       : 1;    /**< - If set, one or more valid entries are in the queue. */
+        uint64_t    queue_one       : 1;    /**< - If set, exactly one valid entry is in the queue. */
+        uint64_t    reserved_24_25  : 2;
+        uint64_t    queue_head      : 11;   /**< - Index of entry at the head of the queue. */
+        uint64_t    reserved_11_12  : 2;
+        uint64_t    queue_tail      : 11;   /**< - Index of entry at the tail of the queue. */
+#else
+        uint64_t    queue_tail      : 11;
+        uint64_t    reserved_11_12  : 2;
+        uint64_t    queue_head      : 11;
+        uint64_t    reserved_24_25  : 2;
+        uint64_t    queue_one       : 1;
+        uint64_t    queue_val       : 1;
+        uint64_t    reserved_28_63  : 36;
+#endif
+    } sindexload0_cn68xx;
+
+    /**
      * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 1)
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved_52_63  : 12;
         uint64_t    nosched_val     : 1;    /**< - set when there is one or more POW entries on the nosched list. */
         uint64_t    nosched_one     : 1;    /**< - set when there is exactly one POW entry on the nosched list. */
@@ -694,11 +1121,41 @@ typedef union
     } sindexload1;
 
     /**
+     * Result for SSO Index/Pointer Load(opcode == IPL_FREE0/IPL_FREE1/IPL_FREE2)
+     */
+    struct
+    {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t    reserved_60_63  : 4;
+        uint64_t    qnum_head       : 2;    /**< - Subqueue with current head */
+        uint64_t    qnum_tail       : 2;    /**< - Subqueue with current tail */
+        uint64_t    reserved_28_55  : 28;
+        uint64_t    queue_val       : 1;    /**< - If set, one or more valid entries are in the queue. */
+        uint64_t    queue_one       : 1;    /**< - If set, exactly one valid entry is in the queue. */
+        uint64_t    reserved_24_25  : 2;
+        uint64_t    queue_head      : 11;   /**< - Index of entry at the head of the queue. */
+        uint64_t    reserved_11_12  : 2;
+        uint64_t    queue_tail      : 11;   /**< - Index of entry at the tail of the queue. */
+#else
+        uint64_t    queue_tail      : 11;
+        uint64_t    reserved_11_12  : 2;
+        uint64_t    queue_head      : 11;
+        uint64_t    reserved_24_25  : 2;
+        uint64_t    queue_one       : 1;
+        uint64_t    queue_val       : 1;
+        uint64_t    reserved_28_55  : 28;
+        uint64_t    qnum_tail       : 2;
+        uint64_t    qnum_head       : 2;
+        uint64_t    reserved_60_63  : 4;
+#endif
+    } sindexload1_cn68xx;
+
+    /**
      * Result For POW Index/Pointer Load (get_rmt == 1/get_des_get_tail == 0)
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved_39_63  : 25;
         uint64_t    rmt_is_head     : 1;    /**< Set when this DRAM list is the current head (i.e. is the next to
                                                 be reloaded when the POW hardware reloads a POW entry from DRAM). The
@@ -724,7 +1181,7 @@ typedef union
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved_39_63  : 25;
         uint64_t    rmt_is_head     : 1;    /**< - set when this DRAM list is the current head (i.e. is the next to
                                                 be reloaded when the POW hardware reloads a POW entry from DRAM). The
@@ -750,7 +1207,7 @@ typedef union
      */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    unused  : 62;
         uint64_t    state    : 2;  /**< of type cvmx_pow_tag_type_t. state is one of the following:
                                         - CVMX_POW_TAG_TYPE_ORDERED
@@ -765,6 +1222,33 @@ typedef union
 
 } cvmx_pow_tag_load_resp_t;
 
+typedef union {
+    uint64_t u64;
+    struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t    reserved_57_63  : 7;
+        uint64_t    index           : 11;
+        uint64_t    reserved_45     : 1;
+        uint64_t    grp             : 6;
+        uint64_t    head            : 1;
+        uint64_t    tail            : 1;
+        uint64_t    reserved_34_36  : 3;
+        uint64_t    tag_type        : 2;
+        uint64_t    tag             : 32;
+#else
+        uint64_t    tag             : 32;
+        uint64_t    tag_type        : 2;
+        uint64_t    reserved_34_36  : 3;
+        uint64_t    tail            : 1;
+        uint64_t    head            : 1;
+        uint64_t    grp             : 6;
+        uint64_t    reserved_45     : 1;
+        uint64_t    index           : 11;
+        uint64_t    reserved_57_63  : 7;
+#endif
+    } s;
+} cvmx_pow_sl_tag_resp_t;
+
 /**
  * This structure describes the address used for stores to the POW.
  *  The store address is meaningful on stores to the POW.  The hardware assumes that an aligned
@@ -795,7 +1279,7 @@ typedef union
 
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    mem_reg         : 2;    /**< Memory region.  Should be CVMX_IO_SEG in most cases */
         uint64_t    reserved_49_61  : 13;   /**< Must be zero */
         uint64_t    is_io           : 1;    /**< Must be one */
@@ -822,7 +1306,7 @@ typedef union
 
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    scraddr : 8;    /**< the (64-bit word) location in scratchpad to write to (if len != 0) */
         uint64_t    len     : 8;    /**< the number of words in the response (0 => no response) */
         uint64_t    did     : 8;    /**< the ID of the device on the non-coherent bus */
@@ -853,28 +1337,41 @@ typedef union
  *
  * @return Current tag
  */
-static inline cvmx_pow_tag_req_t cvmx_pow_get_current_tag(void)
+static inline cvmx_pow_tag_info_t cvmx_pow_get_current_tag(void)
 {
     cvmx_pow_load_addr_t load_addr;
-    cvmx_pow_tag_load_resp_t load_resp;
-    cvmx_pow_tag_req_t result;
-
-    load_addr.u64 = 0;
-    load_addr.sstatus.mem_region = CVMX_IO_SEG;
-    load_addr.sstatus.is_io = 1;
-    load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
-    load_addr.sstatus.coreid = cvmx_get_core_num();
-    load_addr.sstatus.get_cur = 1;
-    load_resp.u64 = cvmx_read_csr(load_addr.u64);
-    result.u64 = 0;
-    result.s.grp = load_resp.s_sstatus2.grp;
-    result.s.index = load_resp.s_sstatus2.index;
-    result.s.type = (cvmx_pow_tag_type_t)load_resp.s_sstatus2.tag_type;
-    result.s.tag = load_resp.s_sstatus2.tag;
+    cvmx_pow_tag_info_t result;
+
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE)) {
+        cvmx_pow_sl_tag_resp_t load_resp;
+        load_addr.u64 = 0;
+        load_addr.sstatus_cn68xx.mem_region = CVMX_IO_SEG;
+        load_addr.sstatus_cn68xx.is_io = 1;
+        load_addr.sstatus_cn68xx.did = CVMX_OCT_DID_TAG_TAG5;
+        load_addr.sstatus_cn68xx.coreid = cvmx_get_core_num();
+        load_addr.sstatus_cn68xx.opcode = 3;
+        load_resp.u64 = cvmx_read_csr(load_addr.u64);
+        result.grp = load_resp.s.grp;
+        result.index = load_resp.s.index;
+        result.tag_type = load_resp.s.tag_type;
+        result.tag = load_resp.s.tag;
+    } else {
+        cvmx_pow_tag_load_resp_t load_resp;
+        load_addr.u64 = 0;
+        load_addr.sstatus.mem_region = CVMX_IO_SEG;
+        load_addr.sstatus.is_io = 1;
+        load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
+        load_addr.sstatus.coreid = cvmx_get_core_num();
+        load_addr.sstatus.get_cur = 1;
+        load_resp.u64 = cvmx_read_csr(load_addr.u64);
+        result.grp = load_resp.s_sstatus2.grp;
+        result.index = load_resp.s_sstatus2.index;
+        result.tag_type = load_resp.s_sstatus2.tag_type;
+        result.tag = load_resp.s_sstatus2.tag;
+    }
     return result;
 }
 
-
 /**
  * Get the POW WQE for this core. This returns the work queue
  * entry currently associated with this core.
@@ -886,15 +1383,29 @@ static inline cvmx_wqe_t *cvmx_pow_get_current_wqp(void)
     cvmx_pow_load_addr_t load_addr;
     cvmx_pow_tag_load_resp_t load_resp;
 
-    load_addr.u64 = 0;
-    load_addr.sstatus.mem_region = CVMX_IO_SEG;
-    load_addr.sstatus.is_io = 1;
-    load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
-    load_addr.sstatus.coreid = cvmx_get_core_num();
-    load_addr.sstatus.get_cur = 1;
-    load_addr.sstatus.get_wqp = 1;
-    load_resp.u64 = cvmx_read_csr(load_addr.u64);
-    return (cvmx_wqe_t*)cvmx_phys_to_ptr(load_resp.s_sstatus4.wqp);
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE)) {
+        load_addr.u64 = 0;
+        load_addr.sstatus_cn68xx.mem_region = CVMX_IO_SEG;
+        load_addr.sstatus_cn68xx.is_io = 1;
+        load_addr.sstatus_cn68xx.did = CVMX_OCT_DID_TAG_TAG5;
+        load_addr.sstatus_cn68xx.coreid = cvmx_get_core_num();
+        load_addr.sstatus_cn68xx.opcode = 3;
+        load_resp.u64 = cvmx_read_csr(load_addr.u64);
+        if (load_resp.s_sstatus3_cn68xx.wqp)
+            return (cvmx_wqe_t*)cvmx_phys_to_ptr(load_resp.s_sstatus3_cn68xx.wqp);
+        else
+            return (cvmx_wqe_t*)0;
+    } else {
+        load_addr.u64 = 0;
+        load_addr.sstatus.mem_region = CVMX_IO_SEG;
+        load_addr.sstatus.is_io = 1;
+        load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
+        load_addr.sstatus.coreid = cvmx_get_core_num();
+        load_addr.sstatus.get_cur = 1;
+        load_addr.sstatus.get_wqp = 1;
+        load_resp.u64 = cvmx_read_csr(load_addr.u64);
+        return (cvmx_wqe_t*)cvmx_phys_to_ptr(load_resp.s_sstatus4.wqp);
+    }
 }
 
 
@@ -1040,6 +1551,7 @@ static inline void cvmx_pow_work_request_async_nocheck(int scr_addr, cvmx_pow_wa
         __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
 
     /* scr_addr must be 8 byte aligned */
+    data.u64 = 0;
     data.s.scraddr = scr_addr >> 3;
     data.s.len = 1;
     data.s.did = CVMX_OCT_DID_TAG_SWTAG;
@@ -1134,12 +1646,12 @@ static inline void cvmx_pow_tag_sw_nocheck(uint32_t tag, cvmx_pow_tag_type_t tag
 
     if (CVMX_ENABLE_POW_CHECKS)
     {
-        cvmx_pow_tag_req_t current_tag;
+        cvmx_pow_tag_info_t current_tag;
         __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
         current_tag = cvmx_pow_get_current_tag();
-        cvmx_warn_if(current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL, "%s called with NULL_NULL tag\n", __FUNCTION__);
-        cvmx_warn_if(current_tag.s.type == CVMX_POW_TAG_TYPE_NULL, "%s called with NULL tag\n", __FUNCTION__);
-        cvmx_warn_if((current_tag.s.type == tag_type) && (current_tag.s.tag == tag), "%s called to perform a tag switch to the same tag\n", __FUNCTION__);
+        cvmx_warn_if(current_tag.tag_type == CVMX_POW_TAG_TYPE_NULL_NULL, "%s called with NULL_NULL tag\n", __FUNCTION__);
+        cvmx_warn_if(current_tag.tag_type == CVMX_POW_TAG_TYPE_NULL, "%s called with NULL tag\n", __FUNCTION__);
+        cvmx_warn_if((current_tag.tag_type == tag_type) && (current_tag.tag == tag), "%s called to perform a tag switch to the same tag\n", __FUNCTION__);
         cvmx_warn_if(tag_type == CVMX_POW_TAG_TYPE_NULL, "%s called to perform a tag switch to NULL. Use cvmx_pow_tag_sw_null() instead\n", __FUNCTION__);
     }
 
@@ -1149,11 +1661,16 @@ static inline void cvmx_pow_tag_sw_nocheck(uint32_t tag, cvmx_pow_tag_type_t tag
     ** value if that is important.
     */
 
-
     tag_req.u64 = 0;
-    tag_req.s.op = CVMX_POW_TAG_OP_SWTAG;
-    tag_req.s.tag = tag;
-    tag_req.s.type = tag_type;
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE)) {
+        tag_req.s_cn68xx_other.op = CVMX_POW_TAG_OP_SWTAG;
+        tag_req.s_cn68xx_other.tag = tag;
+        tag_req.s_cn68xx_other.type = tag_type;
+    } else {
+        tag_req.s_cn38xx.op = CVMX_POW_TAG_OP_SWTAG;
+        tag_req.s_cn38xx.tag = tag;
+        tag_req.s_cn38xx.type = tag_type;
+    }
 
     ptr.u64 = 0;
     ptr.sio.mem_region = CVMX_IO_SEG;
@@ -1230,13 +1747,13 @@ static inline void cvmx_pow_tag_sw_full_nocheck(cvmx_wqe_t *wqp, uint32_t tag, c
 
     if (CVMX_ENABLE_POW_CHECKS)
     {
-        cvmx_pow_tag_req_t current_tag;
+        cvmx_pow_tag_info_t current_tag;
         __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
         current_tag = cvmx_pow_get_current_tag();
-        cvmx_warn_if(current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL, "%s called with NULL_NULL tag\n", __FUNCTION__);
-        cvmx_warn_if((current_tag.s.type == tag_type) && (current_tag.s.tag == tag), "%s called to perform a tag switch to the same tag\n", __FUNCTION__);
+        cvmx_warn_if(current_tag.tag_type == CVMX_POW_TAG_TYPE_NULL_NULL, "%s called with NULL_NULL tag\n", __FUNCTION__);
+        cvmx_warn_if((current_tag.tag_type == tag_type) && (current_tag.tag == tag), "%s called to perform a tag switch to the same tag\n", __FUNCTION__);
         cvmx_warn_if(tag_type == CVMX_POW_TAG_TYPE_NULL, "%s called to perform a tag switch to NULL. Use cvmx_pow_tag_sw_null() instead\n", __FUNCTION__);
-        if (wqp != cvmx_phys_to_ptr(0x80))
+        if ((wqp != cvmx_phys_to_ptr(0x80)) && cvmx_pow_get_current_wqp())
             cvmx_warn_if(wqp != cvmx_pow_get_current_wqp(), "%s passed WQE(%p) doesn't match the address in the POW(%p)\n", __FUNCTION__, wqp, cvmx_pow_get_current_wqp());
     }
 
@@ -1247,10 +1764,17 @@ static inline void cvmx_pow_tag_sw_full_nocheck(cvmx_wqe_t *wqp, uint32_t tag, c
     */
 
     tag_req.u64 = 0;
-    tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_FULL;
-    tag_req.s.tag = tag;
-    tag_req.s.type = tag_type;
-    tag_req.s.grp = group;
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE)) {
+        tag_req.s_cn68xx_other.op = CVMX_POW_TAG_OP_SWTAG_FULL;
+        tag_req.s_cn68xx_other.tag = tag;
+        tag_req.s_cn68xx_other.type = tag_type;
+        tag_req.s_cn68xx_other.grp = group;
+    } else {
+        tag_req.s_cn38xx.op = CVMX_POW_TAG_OP_SWTAG_FULL;
+        tag_req.s_cn38xx.tag = tag;
+        tag_req.s_cn38xx.type = tag_type;
+        tag_req.s_cn38xx.grp = group;
+    }
 
     ptr.u64 = 0;
     ptr.sio.mem_region = CVMX_IO_SEG;
@@ -1299,8 +1823,8 @@ static inline void cvmx_pow_tag_sw_full(cvmx_wqe_t *wqp, uint32_t tag, cvmx_pow_
 /**
  * Switch to a NULL tag, which ends any ordering or
  * synchronization provided by the POW for the current
- * work queue entry.  This operation completes immediatly,
- * so completetion should not be waited for.
+ * work queue entry.  This operation completes immediately,
+ * so completion should not be waited for.
  * This function does NOT wait for previous tag switches to complete,
  * so the caller must ensure that any previous tag switches have completed.
  */
@@ -1311,16 +1835,21 @@ static inline void cvmx_pow_tag_sw_null_nocheck(void)
 
     if (CVMX_ENABLE_POW_CHECKS)
     {
-        cvmx_pow_tag_req_t current_tag;
+        cvmx_pow_tag_info_t current_tag;
         __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
         current_tag = cvmx_pow_get_current_tag();
-        cvmx_warn_if(current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL, "%s called with NULL_NULL tag\n", __FUNCTION__);
-        cvmx_warn_if(current_tag.s.type == CVMX_POW_TAG_TYPE_NULL, "%s called when we already have a NULL tag\n", __FUNCTION__);
+        cvmx_warn_if(current_tag.tag_type == CVMX_POW_TAG_TYPE_NULL_NULL, "%s called with NULL_NULL tag\n", __FUNCTION__);
+        cvmx_warn_if(current_tag.tag_type == CVMX_POW_TAG_TYPE_NULL, "%s called when we already have a NULL tag\n", __FUNCTION__);
     }
 
     tag_req.u64 = 0;
-    tag_req.s.op = CVMX_POW_TAG_OP_SWTAG;
-    tag_req.s.type = CVMX_POW_TAG_TYPE_NULL;
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE)) {
+        tag_req.s_cn68xx_other.op = CVMX_POW_TAG_OP_SWTAG;
+        tag_req.s_cn68xx_other.type = CVMX_POW_TAG_TYPE_NULL;
+    } else {
+        tag_req.s_cn38xx.op = CVMX_POW_TAG_OP_SWTAG;
+        tag_req.s_cn38xx.type = CVMX_POW_TAG_TYPE_NULL;
+    }
 
 
     ptr.u64 = 0;
@@ -1338,7 +1867,7 @@ static inline void cvmx_pow_tag_sw_null_nocheck(void)
  * Switch to a NULL tag, which ends any ordering or
  * synchronization provided by the POW for the current
  * work queue entry.  This operation completes immediatly,
- * so completetion should not be waited for.
+ * so completion should not be waited for.
  * This function waits for any pending tag switches to complete
  * before requesting the switch to NULL.
  */
@@ -1374,18 +1903,36 @@ static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag, cvmx_pow_
     cvmx_addr_t ptr;
     cvmx_pow_tag_req_t tag_req;
 
-    wqp->qos = qos;
-    wqp->tag = tag;
-    wqp->tag_type = tag_type;
-    wqp->grp = grp;
-
     tag_req.u64 = 0;
-    tag_req.s.op = CVMX_POW_TAG_OP_ADDWQ;
-    tag_req.s.type = tag_type;
-    tag_req.s.tag = tag;
-    tag_req.s.qos = qos;
-    tag_req.s.grp = grp;
 
+    wqp->word1.s.tag = tag;
+    wqp->word1.s.tag_type = tag_type;
+
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE)) {
+        /* Reset all reserved bits */
+        wqp->word1.cn68xx.zero_0 = 0;
+        wqp->word1.cn68xx.zero_1 = 0;
+        wqp->word1.cn68xx.zero_2 = 0;
+        wqp->word1.cn68xx.qos = qos;
+        wqp->word1.cn68xx.grp = grp;
+
+        tag_req.s_cn68xx_add.op = CVMX_POW_TAG_OP_ADDWQ;
+        tag_req.s_cn68xx_add.type = tag_type;
+        tag_req.s_cn68xx_add.tag = tag;
+        tag_req.s_cn68xx_add.qos = qos;
+        tag_req.s_cn68xx_add.grp = grp;
+    } else {
+        /* Reset all reserved bits */
+        wqp->word1.cn38xx.zero_2 = 0;
+        wqp->word1.cn38xx.qos = qos;
+        wqp->word1.cn38xx.grp = grp;
+
+        tag_req.s_cn38xx.op = CVMX_POW_TAG_OP_ADDWQ;
+        tag_req.s_cn38xx.type = tag_type;
+        tag_req.s_cn38xx.tag = tag;
+        tag_req.s_cn38xx.qos = qos;
+        tag_req.s_cn38xx.grp = grp;
+    }
 
     ptr.u64 = 0;
     ptr.sio.mem_region = CVMX_IO_SEG;
@@ -1414,11 +1961,20 @@ static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag, cvmx_pow_
  */
 static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask)
 {
-    cvmx_pow_pp_grp_mskx_t grp_msk;
 
-    grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num));
-    grp_msk.s.grp_msk = mask;
-    cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64);
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+    {
+        cvmx_sso_ppx_grp_msk_t grp_msk;
+        grp_msk.s.grp_msk = mask;
+        cvmx_write_csr(CVMX_SSO_PPX_GRP_MSK(core_num), grp_msk.u64);
+    }
+    else
+    {
+        cvmx_pow_pp_grp_mskx_t grp_msk;
+        grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num));
+        grp_msk.s.grp_msk = mask;
+        cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64);
+    }
 }
 
 /**
@@ -1436,8 +1992,42 @@ static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask)
  */
 static inline void cvmx_pow_set_priority(uint64_t core_num, const uint8_t priority[])
 {
+    if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
+        return;
+
+    /* Detect gaps between priorities and flag error */
+    {
+        int i;
+        uint32_t prio_mask = 0;
+
+        for(i=0; i<8; i++)
+            if (priority[i] != 0xF)
+                prio_mask |= 1<<priority[i];
+
+        if ( prio_mask ^ ((1<<cvmx_pop(prio_mask)) - 1))
+        {
+            cvmx_dprintf("ERROR: POW static priorities should be contiguous (0x%llx)\n", (unsigned long long)prio_mask);
+            return;
+        }
+    }
+
     /* POW priorities are supported on CN5xxx and later */
-    if (!OCTEON_IS_MODEL(OCTEON_CN3XXX))
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+    {
+        cvmx_sso_ppx_qos_pri_t qos_pri;
+
+        qos_pri.u64 = cvmx_read_csr(CVMX_SSO_PPX_QOS_PRI(core_num));
+        qos_pri.s.qos0_pri = priority[0]; 
+        qos_pri.s.qos1_pri = priority[1]; 
+        qos_pri.s.qos2_pri = priority[2]; 
+        qos_pri.s.qos3_pri = priority[3]; 
+        qos_pri.s.qos4_pri = priority[4]; 
+        qos_pri.s.qos5_pri = priority[5]; 
+        qos_pri.s.qos6_pri = priority[6]; 
+        qos_pri.s.qos7_pri = priority[7]; 
+        cvmx_write_csr(CVMX_SSO_PPX_QOS_PRI(core_num), qos_pri.u64);
+    }
+    else
     {
         cvmx_pow_pp_grp_mskx_t grp_msk;
 
@@ -1451,29 +2041,13 @@ static inline void cvmx_pow_set_priority(uint64_t core_num, const uint8_t priori
         grp_msk.s.qos6_pri = priority[6];
         grp_msk.s.qos7_pri = priority[7];
 
-        /* Detect gaps between priorities and flag error */
-        {
-            int i;
-            uint32_t prio_mask = 0;
-
-            for(i=0; i<8; i++)
-               if (priority[i] != 0xF)
-		   prio_mask |= 1<<priority[i];
-
-            if ( prio_mask ^ ((1<<cvmx_pop(prio_mask)) - 1))
-            {
-                cvmx_dprintf("ERROR: POW static priorities should be contiguous (0x%llx)\n", (unsigned long long)prio_mask);
-                return;
-            }
-        }
-
         cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64);
     }
 }
 
 /**
  * Performs a tag switch and then an immediate deschedule. This completes
- * immediatly, so completion must not be waited for.  This function does NOT
+ * immediately, so completion must not be waited for.  This function does NOT
  * update the wqe in DRAM to match arguments.
  *
  * This function does NOT wait for any prior tag switches to complete, so the
@@ -1519,20 +2093,28 @@ static inline void cvmx_pow_tag_sw_desched_nocheck(uint32_t tag, cvmx_pow_tag_ty
 
     if (CVMX_ENABLE_POW_CHECKS)
     {
-        cvmx_pow_tag_req_t current_tag;
+        cvmx_pow_tag_info_t current_tag;
         __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
         current_tag = cvmx_pow_get_current_tag();
-        cvmx_warn_if(current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL, "%s called with NULL_NULL tag\n", __FUNCTION__);
-        cvmx_warn_if(current_tag.s.type == CVMX_POW_TAG_TYPE_NULL, "%s called with NULL tag. Deschedule not allowed from NULL state\n", __FUNCTION__);
-        cvmx_warn_if((current_tag.s.type != CVMX_POW_TAG_TYPE_ATOMIC) && (tag_type != CVMX_POW_TAG_TYPE_ATOMIC), "%s called where neither the before or after tag is ATOMIC\n", __FUNCTION__);
+        cvmx_warn_if(current_tag.tag_type == CVMX_POW_TAG_TYPE_NULL_NULL, "%s called with NULL_NULL tag\n", __FUNCTION__);
+        cvmx_warn_if(current_tag.tag_type == CVMX_POW_TAG_TYPE_NULL, "%s called with NULL tag. Deschedule not allowed from NULL state\n", __FUNCTION__);
+        cvmx_warn_if((current_tag.tag_type != CVMX_POW_TAG_TYPE_ATOMIC) && (tag_type != CVMX_POW_TAG_TYPE_ATOMIC), "%s called where neither the before or after tag is ATOMIC\n", __FUNCTION__);
     }
 
     tag_req.u64 = 0;
-    tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_DESCH;
-    tag_req.s.tag = tag;
-    tag_req.s.type = tag_type;
-    tag_req.s.grp = group;
-    tag_req.s.no_sched = no_sched;
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE)) {
+        tag_req.s_cn68xx_other.op = CVMX_POW_TAG_OP_SWTAG_DESCH;
+        tag_req.s_cn68xx_other.tag = tag;
+        tag_req.s_cn68xx_other.type = tag_type;
+        tag_req.s_cn68xx_other.grp = group;
+        tag_req.s_cn68xx_other.no_sched = no_sched;
+    } else {
+        tag_req.s_cn38xx.op = CVMX_POW_TAG_OP_SWTAG_DESCH;
+        tag_req.s_cn38xx.tag = tag;
+        tag_req.s_cn38xx.type = tag_type;
+        tag_req.s_cn38xx.grp = group;
+        tag_req.s_cn38xx.no_sched = no_sched;
+    }
 
     ptr.u64 = 0;
     ptr.sio.mem_region = CVMX_IO_SEG;
@@ -1543,7 +2125,7 @@ static inline void cvmx_pow_tag_sw_desched_nocheck(uint32_t tag, cvmx_pow_tag_ty
 }
 /**
  * Performs a tag switch and then an immediate deschedule. This completes
- * immediatly, so completion must not be waited for.  This function does NOT
+ * immediately, so completion must not be waited for.  This function does NOT
  * update the wqe in DRAM to match arguments.
  *
  * This function waits for any prior tag switches to complete, so the
@@ -1612,19 +2194,24 @@ static inline void cvmx_pow_desched(uint64_t no_sched)
 
     if (CVMX_ENABLE_POW_CHECKS)
     {
-        cvmx_pow_tag_req_t current_tag;
+        cvmx_pow_tag_info_t current_tag;
         __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
         current_tag = cvmx_pow_get_current_tag();
-        cvmx_warn_if(current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL, "%s called with NULL_NULL tag\n", __FUNCTION__);
-        cvmx_warn_if(current_tag.s.type == CVMX_POW_TAG_TYPE_NULL, "%s called with NULL tag. Deschedule not expected from NULL state\n", __FUNCTION__);
+        cvmx_warn_if(current_tag.tag_type == CVMX_POW_TAG_TYPE_NULL_NULL, "%s called with NULL_NULL tag\n", __FUNCTION__);
+        cvmx_warn_if(current_tag.tag_type == CVMX_POW_TAG_TYPE_NULL, "%s called with NULL tag. Deschedule not expected from NULL state\n", __FUNCTION__);
     }
 
     /* Need to make sure any writes to the work queue entry are complete */
     CVMX_SYNCWS;
 
     tag_req.u64 = 0;
-    tag_req.s.op = CVMX_POW_TAG_OP_DESCH;
-    tag_req.s.no_sched = no_sched;
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE)) {
+        tag_req.s_cn68xx_other.op = CVMX_POW_TAG_OP_DESCH;
+        tag_req.s_cn68xx_other.no_sched = no_sched;
+    } else {
+        tag_req.s_cn38xx.op = CVMX_POW_TAG_OP_DESCH;
+        tag_req.s_cn38xx.no_sched = no_sched;
+    }
 
     ptr.u64 = 0;
     ptr.sio.mem_region = CVMX_IO_SEG;
@@ -1742,7 +2329,7 @@ extern void cvmx_pow_display(void *buffer, int buffer_size);
 extern int cvmx_pow_get_num_entries(void);
 
 
-#ifdef	__cplusplus
+#ifdef  __cplusplus
 }
 #endif
 
diff --git a/sys/contrib/octeon-sdk/cvmx-power-throttle.c b/sys/contrib/octeon-sdk/cvmx-power-throttle.c
index 9ca4044..2f7de3c 100644
--- a/sys/contrib/octeon-sdk/cvmx-power-throttle.c
+++ b/sys/contrib/octeon-sdk/cvmx-power-throttle.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -43,31 +43,152 @@
  * Interface to power-throttle control, measurement, and debugging
  * facilities.
  *
- * <hr>$Revision<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
 #include "cvmx.h"
 #include "cvmx-asm.h"
+#include "cvmx-coremask.h"
 #include "cvmx-power-throttle.h"
 
-#define CVMX_PTH_PPID_BCAST	63
-#define CVMX_PTH_PPID_MAX	64
+
+#define CVMX_PTH_GET_MASK(len, pos)	\
+	((((uint64_t)1 << (len)) - 1) << (pos))
+
+#define CVMX_PTH_AVAILABLE		\
+    (cvmx_power_throttle_get_register(0) != (uint64_t)-1)
+
+/**
+ * a field of the POWTHROTTLE register
+ */
+static struct cvmx_power_throttle_rfield_t {
+	char	name[16];	/* the field's name */
+	int32_t	pos;		/* position of the field's LSb */
+	int32_t	len;		/* the field's length */
+	int	present;	/* 1 for present */
+} cvmx_power_throttle_rfield[] = {
+	{"MAXPOW",   56,  8, 0},
+	{"POWER" ,   48,  8, 0},
+	{"THROTT",   40,  8, 0},
+	{"Reserved", 28, 12, 0},
+	{"DISTAG",   27,  1, 0},
+	{"PERIOD",   24,  3, 0},
+	{"POWLIM",   16,  8, 0},
+	{"MAXTHR",    8,  8, 0},
+	{"MINTHR",    0,  8, 0},
+	{"HRMPOWADJ",32,  8, 0},
+	{"OVRRD",    28,  1, 0}
+};
+
+static uint64_t cvmx_power_throttle_csr_addr(int ppid);
+
+static int cvmx_power_throttle_initialized;
+
+/**
+ * @INTERNAL
+ * Initialize cvmx_power_throttle_rfield[] based on model.
+ */
+static void cvmx_power_throttle_init(void)
+{
+    /*
+     * Turn on the fields for a model
+     */
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        int i;
+	struct cvmx_power_throttle_rfield_t *p;
+
+        for (i = 0; i < CVMX_PTH_INDEX_MAX; i++)
+	    cvmx_power_throttle_rfield[i].present = 1;
+
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+	{
+	    /*
+	     * These fields do not come with o63
+	     */
+	    p = &cvmx_power_throttle_rfield[CVMX_PTH_INDEX_HRMPOWADJ];
+	    p->present = 0;
+	    p = &cvmx_power_throttle_rfield[CVMX_PTH_INDEX_OVRRD];
+	    p->present = 0;
+	}
+	else
+	{
+	    /*
+	     * The reserved field shrinks in models newer than o63
+	     */
+	    p = &cvmx_power_throttle_rfield[CVMX_PTH_INDEX_RESERVED];
+	    p->pos = 29;
+	    p->len = 3;
+	}
+    }
+}
+
+uint64_t cvmx_power_throttle_get_field(uint64_t r,
+    cvmx_power_throttle_field_index_t i)
+{
+    uint64_t m;
+    struct cvmx_power_throttle_rfield_t *p;
+
+    assert(i < CVMX_PTH_INDEX_MAX);
+    p = &cvmx_power_throttle_rfield[i];
+    if (!p->present)
+        return (uint64_t) -1;
+    m = CVMX_PTH_GET_MASK(p->len, p->pos);
+    
+    return((r & m) >> p->pos);
+}
+
+/**
+ * @INTERNAL
+ * Set the i'th field of power-throttle register r to v.
+ */
+static int cvmx_power_throttle_set_field(int i, uint64_t r, uint64_t v)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        uint64_t m;
+        struct cvmx_power_throttle_rfield_t *p;
+
+        assert(i < CVMX_PTH_INDEX_MAX);
+
+        p = &cvmx_power_throttle_rfield[i];
+        m = CVMX_PTH_GET_MASK(p->len, p->pos);
+
+        return((~m & r) | ((v << p->pos) & m));
+    }
+    return 0;
+}
 
 /**
  * @INTERNAL
  * Set the POWLIM field as percentage% of the MAXPOW field in r.
  */
-static uint64_t __cvmx_power_throttle_set_powlim(uint64_t r, uint8_t percentage)
+static uint64_t cvmx_power_throttle_set_powlim(int ppid,
+    uint8_t percentage)
 {
     if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
     {
-        uint64_t t;
+        uint64_t t, csr_addr, r;
 
         assert(percentage < 101);
-        t = percentage * cvmx_power_throttle_get_field(CVMX_PTH_INDEX_MAXPOW, r) / 100;
+        csr_addr = cvmx_power_throttle_csr_addr(ppid);
+        r = cvmx_read_csr(csr_addr);
+
+        t = cvmx_power_throttle_get_field(r, CVMX_PTH_INDEX_MAXPOW);
+	if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
+	{
+	    uint64_t s;
+
+	    s = cvmx_power_throttle_get_field(r, CVMX_PTH_INDEX_HRMPOWADJ);
+	    assert(t > s);
+	    t = t - s;
+	}
+
+	t = percentage * t / 100;
         r = cvmx_power_throttle_set_field(CVMX_PTH_INDEX_POWLIM, r, t);
 
+        cvmx_write_csr(csr_addr, r);
         return r;
     }
     return 0;
@@ -78,13 +199,14 @@ static uint64_t __cvmx_power_throttle_set_powlim(uint64_t r, uint8_t percentage)
  * Given ppid, calculate its PowThrottle register's L2C_COP0_MAP CSR
  * address. (ppid == PTH_PPID_BCAST is for broadcasting)
  */
-static uint64_t __cvmx_power_throttle_csr_addr(uint64_t ppid)
+static uint64_t cvmx_power_throttle_csr_addr(int ppid)
 {
     if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
     {
         uint64_t csr_addr, reg_num, reg_reg, reg_sel;
 
-        assert(ppid < CVMX_PTH_PPID_MAX);
+        assert(ppid < CVMX_MAX_CORES);
+
         /*
          * register 11 selection 6
          */
@@ -98,55 +220,71 @@ static uint64_t __cvmx_power_throttle_csr_addr(uint64_t ppid)
     return 0;
 }
 
-/**
- * Throttle power to percentage% of configured maximum (MAXPOW).
- *
- * @param percentage	0 to 100
- * @return 0 for success
- */
 int cvmx_power_throttle_self(uint8_t percentage)
 {
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
-    {
-        uint64_t r; 
+    if (!CVMX_PTH_AVAILABLE)
+        return -1;
 
-        CVMX_MF_COP0(r, COP0_POWTHROTTLE);
-        r = __cvmx_power_throttle_set_powlim(r, percentage);
-        CVMX_MT_COP0(r, COP0_POWTHROTTLE);
-    }
+    if (cvmx_power_throttle_set_powlim(cvmx_get_core_num(),
+        percentage) == 0)
+	return -1;
 
     return 0;
 }
 
-/**
- * Throttle power to percentage% of configured maximum (MAXPOW)
- * for the cores identified in coremask.
- *
- * @param percentage 	0 to 100
- * @param coremask	bit mask where each bit identifies a core.
- * @return 0 for success.
- */
 int cvmx_power_throttle(uint8_t percentage, uint64_t coremask)
 {
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
-    {
-        uint64_t ppid, csr_addr, b, r;
+    int ppid;
+    int ret;
 
-        b = 1;
-        /*
-         * cvmx_read_csr() for PTH_PPID_BCAST does not make sense and
-         * therefore limit ppid to less.
-         */
-        for (ppid = 0; ppid < CVMX_PTH_PPID_BCAST; ppid ++)
-        {
-            if ((b << ppid) & coremask) {
-                csr_addr = __cvmx_power_throttle_csr_addr(ppid);
-                r = cvmx_read_csr(csr_addr);
-                r = __cvmx_power_throttle_set_powlim(r, percentage);
-                cvmx_write_csr(csr_addr, r);
-            }
+    if (!CVMX_PTH_AVAILABLE)
+        return -1;
+
+    ret = 0;
+    for (ppid = 0; ppid < CVMX_MAX_CORES; ppid++)
+    {
+        if ((((uint64_t) 1) << ppid) & coremask)
+	{
+            if (cvmx_power_throttle_set_powlim(ppid, percentage) == 0)
+	        ret = -2;
         }
     }
 
-    return 0;
+    return ret;
+}
+
+int cvmx_power_throttle_bmp(uint8_t percentage, struct cvmx_coremask *pcm)
+{
+    int ppid;
+    int ret;
+
+    if (!CVMX_PTH_AVAILABLE)
+        return -1;
+
+    ret = 0;
+    CVMX_COREMASK_FOR_EACH_CORE_BEGIN(pcm, ppid)
+    {
+        if (cvmx_power_throttle_set_powlim(ppid, percentage) == 0)
+	    ret = -2;
+    } CVMX_COREMASK_FOR_EACH_CORE_END;
+
+    return ret;
+}
+
+uint64_t cvmx_power_throttle_get_register(int ppid)
+{
+    uint64_t csr_addr;
+
+    if (!cvmx_power_throttle_initialized)
+    {
+	cvmx_power_throttle_init();
+	cvmx_power_throttle_initialized = 1;
+    }
+
+    csr_addr = cvmx_power_throttle_csr_addr(ppid);
+
+    if (csr_addr == 0)
+        return -1;
+
+    return cvmx_read_csr(csr_addr);
 }
diff --git a/sys/contrib/octeon-sdk/cvmx-power-throttle.h b/sys/contrib/octeon-sdk/cvmx-power-throttle.h
index 7f921af..5cca115 100644
--- a/sys/contrib/octeon-sdk/cvmx-power-throttle.h
+++ b/sys/contrib/octeon-sdk/cvmx-power-throttle.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -43,7 +43,7 @@
  * Interface to power-throttle control, measurement, and debugging
  * facilities.
  *
- * <hr>$Revision<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
@@ -53,83 +53,66 @@
 extern "C" {
 #endif
 
-/**
- * a field of the POWTHROTTLE register
- */
-static struct cvmx_power_throttle_rfield_t {
-	char	name[16];	/* the field's name */
-	int32_t	pos;		/* position of the field's LSb */
-	int32_t	len;		/* the field's length */
-} cvmx_power_throttle_rfield[] = {
-#define CVMX_PTH_INDEX_MAXPOW	0
-	{"MAXPOW",   56,  8},
-#define CVMX_PTH_INDEX_POWER		1
-	{"POWER" ,   48,  8},
-#define CVMX_PTH_INDEX_THROTT	2
-	{"THROTT",   40,  8},
-#define CVMX_PTH_INDEX_RESERVED	3
-	{"Reserved", 28, 12},
-#define CVMX_PTH_INDEX_DISTAG	4
-	{"DISTAG",   27,  1},
-#define CVMX_PTH_INDEX_PERIOD	5
-	{"PERIOD",   24,  3},
-#define CVMX_PTH_INDEX_POWLIM	6
-	{"POWLIM",   16,  8},
-#define CVMX_PTH_INDEX_MAXTHR	7
-	{"MAXTHR",    8,  8},
-#define CVMX_PTH_INDEX_MINTHR	8
-	{"MINTHR",    0,  8}
-#define CVMX_PTH_INDEX_MAX		9
+enum cvmx_power_throttle_field_index {
+    CVMX_PTH_INDEX_MAXPOW,
+    CVMX_PTH_INDEX_POWER,
+    CVMX_PTH_INDEX_THROTT,
+    CVMX_PTH_INDEX_RESERVED,
+    CVMX_PTH_INDEX_DISTAG,
+    CVMX_PTH_INDEX_PERIOD,
+    CVMX_PTH_INDEX_POWLIM,
+    CVMX_PTH_INDEX_MAXTHR,
+    CVMX_PTH_INDEX_MINTHR,
+    CVMX_PTH_INDEX_HRMPOWADJ,
+    CVMX_PTH_INDEX_OVRRD,
+    CVMX_PTH_INDEX_MAX
 };
-
-#define CVMX_PTH_GET_MASK(len, pos) \
-	((((uint64_t)1 << (len)) - 1) << (pos))
+typedef enum cvmx_power_throttle_field_index cvmx_power_throttle_field_index_t;
 
 /**
- * Get the i'th field of power-throttle register r.
+ * Throttle power to percentage% of configured maximum (MAXPOW).
+ *
+ * @param percentage	0 to 100
+ * @return 0 for success and -1 for error.
  */
-static inline uint64_t cvmx_power_throttle_get_field(int i, uint64_t r)
-{
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
-    {
-        uint64_t m;
-        struct cvmx_power_throttle_rfield_t *p;
-
-        assert((i >= 0) && (i < CVMX_PTH_INDEX_MAX));
-
-        p = &cvmx_power_throttle_rfield[i];
-        m = CVMX_PTH_GET_MASK(p->len, p->pos);
-
-        return((r & m) >> p->pos);
-    }
-    return 0;
-}
+extern int cvmx_power_throttle_self(uint8_t percentage);
 
 /**
- * Set the i'th field of power-throttle register r to v.
+ * Throttle power to percentage% of configured maximum (MAXPOW)
+ * for the cores identified in coremask.
+ *
+ * @param percentage 	0 to 100
+ * @param coremask	bit mask where each bit identifies a core.
+ * @return 0 for success and -1 for error.
  */
-static inline int cvmx_power_throttle_set_field(int i, uint64_t r, uint64_t v)
-{
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
-    {
-        uint64_t m;
-        struct cvmx_power_throttle_rfield_t *p;
-
-        assert((i >= 0) && (i < CVMX_PTH_INDEX_MAX));
+extern int cvmx_power_throttle(uint8_t percentage, uint64_t coremask);
 
-        p = &cvmx_power_throttle_rfield[i];
-        m = CVMX_PTH_GET_MASK(p->len, p->pos);
+/**
+ * The same functionality as cvmx_power_throttle() but it takes a
+ * bitmap-based coremask as a parameter.
+ */
+extern int cvmx_power_throttle_bmp(uint8_t percentage,
+    struct cvmx_coremask *pcm);
 
-        return((~m & r) | ((v << p->pos) & m));
-    }
-    return 0;
-}
+/**
+ * Get the i'th field of the power throttle register
+ *
+ * @param r is the value of the power throttle register
+ * @param i is the index of the field
+ *
+ * @return (uint64_t)-1 on failure.
+ */
+extern uint64_t cvmx_power_throttle_get_field(uint64_t r,
+    cvmx_power_throttle_field_index_t i);
 
 /**
- * API Function Prototypes
+ * Retrieve the content of the power throttle register of a core
+ *
+ * @param ppid is the core id
+ *
+ * @return (uint64_t)-1 on failure.
  */
-extern int cvmx_power_throttle_self(uint8_t percentage);
-extern int cvmx_power_throttle(uint8_t percentage, uint64_t coremask);
+extern uint64_t cvmx_power_throttle_get_register(int ppid);
 
 #ifdef	__cplusplus
 }
diff --git a/sys/contrib/octeon-sdk/cvmx-profiler.c b/sys/contrib/octeon-sdk/cvmx-profiler.c
new file mode 100644
index 0000000..13dd95a
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-profiler.c
@@ -0,0 +1,237 @@
+/***********************license start***************
+ * Copyright (c) 2011  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ * 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * 
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+ *
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+ *
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+ *
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ************************license end**************************************/
+
+/**
+ * @file
+ *
+ * Interface to event profiler.
+ *
+ */
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-interrupt.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-coremask.h"
+#include "cvmx-spinlock.h"
+#include "cvmx-atomic.h"
+#include "cvmx-error.h"
+#include "cvmx-asm.h"
+#include "cvmx-bootmem.h"
+#include "cvmx-profiler.h"
+
+#ifdef PROFILER_DEBUG
+#define PRINTF(fmt, args...)    cvmx_safe_printf(fmt, ##args)
+#else
+#define PRINTF(fmt, args...)
+#endif
+
+CVMX_SHARED static event_counter_control_block_t eccb;
+cvmx_config_block_t *pcpu_cfg_blk;
+
+int read_percpu_block = 1;
+
+/**
+ * Set Interrupt IRQ line for Performance Counter
+ *
+ */
+void cvmx_update_perfcnt_irq(void)
+{
+    uint64_t cvmctl;
+   
+    /* Clear CvmCtl[IPPCI] bit and move the Performance Counter
+     * interrupt to IRQ 6
+     */
+    CVMX_MF_COP0(cvmctl, COP0_CVMCTL);
+    cvmctl &= ~(7 << 7);
+    cvmctl |= 6 << 7;
+    CVMX_MT_COP0(cvmctl, COP0_CVMCTL);
+}
+
+/**
+ * @INTERNAL
+ * Return the baseaddress of the namedblock 
+ * @param buf_name  Name of Namedblock
+ *
+ * @return baseaddress of block on Success, NULL on failure.
+ */
+static
+void *cvmx_get_memory_addr(const char* buf_name)
+{
+    void *buffer_ptr = NULL;
+    const struct cvmx_bootmem_named_block_desc *block_desc = cvmx_bootmem_find_named_block(buf_name);
+    if (block_desc)
+        buffer_ptr = cvmx_phys_to_ptr(block_desc->base_addr);
+    assert (buffer_ptr != NULL);
+
+    return buffer_ptr;
+}
+
+/**
+ * @INTERNAL
+ * Initialize the cpu block metadata. 
+ * 
+ * @param cpu	core no
+ * @param size	size of per cpu memory in named block
+ *
+ */
+static
+void cvmx_init_pcpu_block(int cpu, int size)
+{
+    eccb.cfg_blk.pcpu_base_addr[cpu] = (char *)cvmx_get_memory_addr(EVENT_BUFFER_BLOCK) + (size * cpu); 
+    assert (eccb.cfg_blk.pcpu_base_addr[cpu] != NULL);
+
+    cvmx_ringbuf_t  *cpu_buf = (cvmx_ringbuf_t *) eccb.cfg_blk.pcpu_base_addr[cpu];
+
+    cpu_buf->pcpu_blk_info.size = size;
+    cpu_buf->pcpu_blk_info.max_samples = ((size - sizeof(cvmx_cpu_event_block_t)) / sizeof(cvmx_sample_entry_t));
+    cpu_buf->pcpu_blk_info.sample_count = 0;
+    cpu_buf->pcpu_blk_info.sample_read = 0;
+    cpu_buf->pcpu_blk_info.data = eccb.cfg_blk.pcpu_base_addr[cpu] + sizeof(cvmx_cpu_event_block_t) + PADBYTES;
+    cpu_buf->pcpu_blk_info.head = cpu_buf->pcpu_blk_info.tail = \
+       cpu_buf->pcpu_data = cpu_buf->pcpu_blk_info.data;
+    cpu_buf->pcpu_blk_info.end = eccb.cfg_blk.pcpu_base_addr[cpu] + size;
+
+    cvmx_atomic_set32(&read_percpu_block, 0);
+
+    /*
+     * Write per cpu mem base address info in to 'event config' named block,
+     * This info is needed by oct-remote-profile to get Per cpu memory 
+     * base address of each core of the named block.
+     */
+    pcpu_cfg_blk = (cvmx_config_block_t *) eccb.config_blk_base_addr;
+    pcpu_cfg_blk->pcpu_base_addr[cpu] = eccb.cfg_blk.pcpu_base_addr[cpu];
+}
+
+/**
+ * @INTERNAL
+ * Retrieve the info from the 'event_config' named block.
+ *
+ * Here events value is read(as passed to oct-remote-profile) to reset perf 
+ * counters on every Perf counter overflow.
+ *
+ */
+static
+void cvmx_read_config_blk(void)
+{
+    eccb.config_blk_base_addr = (char *)cvmx_get_memory_addr(EVENT_BUFFER_CONFIG_BLOCK);
+    memcpy(&(eccb.cfg_blk.events), eccb.config_blk_base_addr + \
+       offsetof(cvmx_config_block_t, events), sizeof(int64_t));
+
+    cvmx_atomic_set32(&eccb.read_cfg_blk,1);
+    PRINTF("cfg_blk.events=%lu, sample_count=%ld\n", eccb.cfg_blk.events, eccb.cfg_blk.sample_count);
+}
+
+/**
+ * @INTERNAL
+ * Add new sample to the buffer and increment the head pointer and 
+ * global sample count(i.e sum total of samples collected on all cores) 
+ *
+ */
+static
+void cvmx_add_sample_to_buffer(void)
+{
+    uint32_t epc;
+    int cpu = cvmx_get_core_num();
+    CVMX_MF_COP0(epc, COP0_EPC);
+
+    cvmx_ringbuf_t  *cpu_buf = (cvmx_ringbuf_t *) eccb.cfg_blk.pcpu_base_addr[cpu];
+
+    /* 
+     * head/tail pointer can be NULL, and this case arises when oct-remote-profile is
+     * invoked afresh. To keep memory sane for current instance, we clear namedblock off 
+     * previous data and this is accomplished by octeon_remote_write_mem from host.
+     */
+    if (cvmx_unlikely(!cpu_buf->pcpu_blk_info.head && !cpu_buf->pcpu_blk_info.end)) {
+       /* Reread the event count as a different threshold val could be 
+        * passed with profiler alongside --events flag */
+        cvmx_read_config_blk();
+        cvmx_init_pcpu_block(cpu, EVENT_PERCPU_BUFFER_SIZE);
+    }
+
+    /* In case of hitting end of buffer, reset head,data ptr to start */
+    if (cpu_buf->pcpu_blk_info.head == cpu_buf->pcpu_blk_info.end)
+        cpu_buf->pcpu_blk_info.head = cpu_buf->pcpu_blk_info.data = cpu_buf->pcpu_data; 
+
+    /* Store the pc, respective core no.*/
+    cvmx_sample_entry_t *sample = (cvmx_sample_entry_t *) cpu_buf->pcpu_blk_info.data;
+    sample->pc = epc;
+    sample->core = cpu;
+  
+    /* Update Per CPU stats */
+    cpu_buf->pcpu_blk_info.sample_count++;
+    cpu_buf->pcpu_blk_info.data += sizeof(cvmx_sample_entry_t);
+    cpu_buf->pcpu_blk_info.head = cpu_buf->pcpu_blk_info.data;
+
+    /* Increment the global sample count i.e sum total of samples on all cores*/
+    cvmx_atomic_add64(&(pcpu_cfg_blk->sample_count), 1);
+
+    PRINTF("the core%d:pc 0x%016lx, sample_count=%ld\n", cpu, sample->pc, cpu_buf->pcpu_blk_info.sample_count);
+}
+
+/**
+ * @INTERNAL
+ * Reset performance counters
+ *
+ * @param pf     The performance counter Number (0, 1)
+ * @param events The threshold value for which interrupt has to be asserted
+ */
+static
+void cvmx_reset_perf_counter(int pf, uint64_t events)
+{
+    uint64_t pfc;
+    pfc = (1ull << 63) - events;
+ 	
+    if (!pf) {
+        CVMX_MT_COP0(pfc, COP0_PERFVALUE0);
+    } else
+        CVMX_MT_COP0(pfc, COP0_PERFVALUE1);
+}
+
+void cvmx_collect_sample(void)
+{
+    if (!eccb.read_cfg_blk)
+        cvmx_read_config_blk();
+
+    if (read_percpu_block)
+        cvmx_init_pcpu_block(cvmx_get_core_num(), EVENT_PERCPU_BUFFER_SIZE);
+
+    cvmx_add_sample_to_buffer();
+    cvmx_reset_perf_counter(0, eccb.cfg_blk.events);
+}
diff --git a/sys/contrib/octeon-sdk/cvmx-profiler.h b/sys/contrib/octeon-sdk/cvmx-profiler.h
new file mode 100644
index 0000000..161d863
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-profiler.h
@@ -0,0 +1,103 @@
+/***********************license start***************
+ * Copyright (c) 2011  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+ *
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+ *
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+ *
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *************************license end**************************************/
+
+/**
+ * @file
+ *
+ * Header file for the event Profiler.
+ *
+ */
+
+#ifndef __CVMX_PROFILER_H__
+#define __CVMX_PROFILER_H__
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+#define EVENT_PERCPU_BUFFER_SIZE	8192
+#define PADBYTES			24
+
+#define	EVENT_BUFFER_BLOCK		"event_block"
+#define EVENT_BUFFER_SIZE		EVENT_PERCPU_BUFFER_SIZE * (cvmx_octeon_num_cores() + 1)
+
+#define EVENT_BUFFER_CONFIG_BLOCK	"event_config_block"
+#define EBC_BLOCK_SIZE			256 
+
+typedef struct {
+    int core; 
+    uint32_t pc;
+} cvmx_sample_entry_t;
+
+typedef struct cpu_event_block {
+    int size;
+    int sample_read; 
+    int64_t max_samples;
+    int64_t sample_count;
+    char *head;
+    char *tail;
+    char *end;
+    char *data;
+} cvmx_cpu_event_block_t;
+
+typedef struct {
+    cvmx_cpu_event_block_t pcpu_blk_info;
+    char *pcpu_data;
+} cvmx_ringbuf_t;
+
+typedef struct config_block {
+    int64_t sample_count;
+    uint64_t events;
+    char *pcpu_base_addr[CVMX_MAX_CORES];
+} cvmx_config_block_t;
+
+typedef struct event_counter_control_block {
+    int32_t read_cfg_blk;
+    char *config_blk_base_addr;
+    cvmx_config_block_t cfg_blk;        
+} event_counter_control_block_t;
+
+extern void cvmx_update_perfcnt_irq(void);
+extern void cvmx_collect_sample(void);
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif	/*  __CVMX_PROFILER_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-qlm-tables.c b/sys/contrib/octeon-sdk/cvmx-qlm-tables.c
new file mode 100644
index 0000000..0db0bcb
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-qlm-tables.c
@@ -0,0 +1,445 @@
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-qlm.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include <cvmx.h>
+#include <cvmx-qlm.h>
+#else
+#include "cvmx.h"
+#include "cvmx-qlm.h"
+#endif
+#endif
+
+const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn56xx[] =
+{
+    {"prbs_error_count",        267, 220},       // BIST/PRBS error count (only valid if pbrs_lock asserted)
+    {"prbs_unlock_count",       219, 212},       // BIST/PRBS unlock count (only valid if pbrs_lock asserted)
+    {"prbs_locked",             211, 211},       // BIST/PRBS lock (asserted after QLM achieves lock)
+    {"reset_prbs",              210, 210},       // BIST/PRBS reset (write 0 to reset)
+    {"run_prbs",                209, 209},       // run PRBS test pattern
+    {"run_bist",                208, 208},       // run bist (May only work for PCIe ?)
+    {"unknown",                 207, 202},       //
+    {"biasdrvsel",              201,        199},           //   assign biasdrvsel          = fus_cfg_reg[201:199] ^ jtg_cfg_reg[201:199] ^ ((pi_qlm_cfg == 2'h0) ? 3'h4 : (pi_qlm_cfg == 2'h2) ? 3'h7 : 3'h2);
+    {"biasbuffsel",             198,        196},           //   assign biasbuffsel         = fus_cfg_reg[198:196] ^ jtg_cfg_reg[198:196] ^ 3'h4;
+    {"tcoeff",                  195,        192},           //   assign tcoeff              = fus_cfg_reg[195:192] ^ jtg_cfg_reg[195:192] ^ (pi_qlm_cfg[1] ? 4'h0 : 4'hc);
+    {"mb5000",                  181,        181},           //   assign mb5000              = fus_cfg_reg[181]     ^ jtg_cfg_reg[181]     ^ 1'h0;
+    {"interpbw",                180,        176},           //   assign interpbw            = fus_cfg_reg[180:176] ^ jtg_cfg_reg[180:176] ^ ((qlm_spd == 2'h0) ? 5'h1f : (qlm_spd == 2'h1) ? 5'h10 : 5'h0);
+    {"mb",                      175,        172},           //   assign mb                  = fus_cfg_reg[175:172] ^ jtg_cfg_reg[175:172] ^ 4'h0;
+    {"bwoff",                   171,        160},           //   assign bwoff               = fus_cfg_reg[171:160] ^ jtg_cfg_reg[171:160] ^ 12'h0;
+    {"bg_ref_sel",              153,        153},           //   assign bg_ref_sel          = fus_cfg_reg[153]     ^ jtg_cfg_reg[153]     ^ 1'h0;
+    {"div2en",                  152,        152},           //   assign div2en              = fus_cfg_reg[152]     ^ jtg_cfg_reg[152]     ^ 1'h0;
+    {"trimen",                  151,        150},           //   assign trimen              = fus_cfg_reg[151:150] ^ jtg_cfg_reg[151:150] ^ 2'h0;
+    {"clkr",                    149,        144},           //   assign clkr                = fus_cfg_reg[149:144] ^ jtg_cfg_reg[149:144] ^ 6'h0;
+    {"clkf",                    143,        132},           //   assign clkf                = fus_cfg_reg[143:132] ^ jtg_cfg_reg[143:132] ^ 12'h18;
+    {"bwadj",                   131,        120},           //   assign bwadj               = fus_cfg_reg[131:120] ^ jtg_cfg_reg[131:120] ^ 12'h30;
+    {"shlpbck",                 119,        118},           //   assign shlpbck             = fus_cfg_reg[119:118] ^ jtg_cfg_reg[119:118] ^ 2'h0;
+    {"serdes_pll_byp",          117,        117},           //   assign serdes_pll_byp      = fus_cfg_reg[117]     ^ jtg_cfg_reg[117]     ^ 1'h0;
+    {"ic50dac",                 116,        112},           //   assign ic50dac             = fus_cfg_reg[116:112] ^ jtg_cfg_reg[116:112] ^ 5'h11;
+    {"sl_posedge_sample",       111,        111},           //   assign sl_posedge_sample   = fus_cfg_reg[111]     ^ jtg_cfg_reg[111]     ^ 1'h0;
+    {"sl_enable",               110,        110},           //   assign sl_enable           = fus_cfg_reg[110]     ^ jtg_cfg_reg[110]     ^ 1'h0;
+    {"rx_rout_comp_bypass",     109,        109},           //   assign rx_rout_comp_bypass = fus_cfg_reg[109]     ^ jtg_cfg_reg[109]     ^ 1'h0;
+    {"ir50dac",                 108,        104},           //   assign ir50dac             = fus_cfg_reg[108:104] ^ jtg_cfg_reg[108:104] ^ 5'h11;
+    {"rx_res_offset",           103,        100},           //   assign rx_res_offset       = fus_cfg_reg[103:100] ^ jtg_cfg_reg[103:100] ^ 4'h2;
+    {"rx_rout_comp_value",      99,         96},            //   assign rx_rout_comp_value  = fus_cfg_reg[99:96]   ^ jtg_cfg_reg[99:96]   ^ 4'h7;
+    {"tx_rout_comp_value",      95,         92},            //   assign tx_rout_comp_value  = fus_cfg_reg[95:92]   ^ jtg_cfg_reg[95:92]   ^ 4'h7;
+    {"tx_res_offset",           91,         88},            //   assign tx_res_offset       = fus_cfg_reg[91:88]   ^ jtg_cfg_reg[91:88]   ^ 4'h1;
+    {"tx_rout_comp_bypass",     87,         87},            //   assign tx_rout_comp_bypass = fus_cfg_reg[87]      ^ jtg_cfg_reg[87]      ^ 1'h0;
+    {"idle_dac",                86,         84},            //   assign idle_dac            = fus_cfg_reg[86:84]   ^ jtg_cfg_reg[86:84]   ^ 3'h4;
+    {"hyst_en",                 83,         83},            //   assign hyst_en             = fus_cfg_reg[83]      ^ jtg_cfg_reg[83]      ^ 1'h1;
+    {"rndt",                    82,         82},            //   assign rndt                = fus_cfg_reg[82]      ^ jtg_cfg_reg[82]      ^ 1'h0;
+    {"cfg_tx_com",              79,         79},            //   CN52XX cfg_tx_com     = fus_cfg_reg[79] ^ jtg_cfg_reg[79] ^ 1'h0;
+    {"cfg_cdr_errcor",          78,         78},            //   CN52XX cfg_cdr_errcor = fus_cfg_reg[78] ^ jtg_cfg_reg[78] ^ 1'h0;
+    {"cfg_cdr_secord",          77,         77},            //   CN52XX cfg_cdr_secord = fus_cfg_reg[77] ^ jtg_cfg_reg[77] ^ 1'h1;
+    {"cfg_cdr_rotate",          76,         76},            //   assign cfg_cdr_rotate      = fus_cfg_reg[76]      ^ jtg_cfg_reg[76]      ^ 1'h0;
+    {"cfg_cdr_rqoffs",          75,         68},            //   assign cfg_cdr_rqoffs      = fus_cfg_reg[75:68]   ^ jtg_cfg_reg[75:68]   ^ 8'h40;
+    {"cfg_cdr_incx",            67,         64},            //   assign cfg_cdr_incx        = fus_cfg_reg[67:64]   ^ jtg_cfg_reg[67:64]   ^ 4'h2;
+    {"cfg_cdr_state",           63,         56},            //   assign cfg_cdr_state       = fus_cfg_reg[63:56]   ^ jtg_cfg_reg[63:56]   ^ 8'h0;
+    {"cfg_cdr_bypass",          55,         55},            //   assign cfg_cdr_bypass      = fus_cfg_reg[55]      ^ jtg_cfg_reg[55]      ^ 1'h0;
+    {"cfg_tx_byp",              54,         54},            //   assign cfg_tx_byp          = fus_cfg_reg[54]      ^ jtg_cfg_reg[54]      ^ 1'h0;
+    {"cfg_tx_val",              53,         44},            //   assign cfg_tx_val          = fus_cfg_reg[53:44]   ^ jtg_cfg_reg[53:44]   ^ 10'h0;
+    {"cfg_rx_pol_set",          43,         43},            //   assign cfg_rx_pol_set      = fus_cfg_reg[43]      ^ jtg_cfg_reg[43]      ^ 1'h0;
+    {"cfg_rx_pol_clr",          42,         42},            //   assign cfg_rx_pol_clr      = fus_cfg_reg[42]      ^ jtg_cfg_reg[42]      ^ 1'h0;
+    {"cfg_cdr_bw_ctl",          41,         40},            //   assign cfg_cdr_bw_ctl      = fus_cfg_reg[41:40]   ^ jtg_cfg_reg[41:40]   ^ 2'h0;
+    {"cfg_rst_n_set",           39,         39},            //   assign cfg_rst_n_set       = fus_cfg_reg[39]      ^ jtg_cfg_reg[39]      ^ 1'h0;
+    {"cfg_rst_n_clr",           38,         38},            //   assign cfg_rst_n_clr       = fus_cfg_reg[38]      ^ jtg_cfg_reg[38]      ^ 1'h0;
+    {"cfg_tx_clk2",             37,         37},            //   assign cfg_tx_clk2         = fus_cfg_reg[37]      ^ jtg_cfg_reg[37]      ^ 1'h0;
+    {"cfg_tx_clk1",             36,         36},            //   assign cfg_tx_clk1         = fus_cfg_reg[36]      ^ jtg_cfg_reg[36]      ^ 1'h0;
+    {"cfg_tx_pol_set",          35,         35},            //   assign cfg_tx_pol_set      = fus_cfg_reg[35]      ^ jtg_cfg_reg[35]      ^ 1'h0;
+    {"cfg_tx_pol_clr",          34,         34},            //   assign cfg_tx_pol_clr      = fus_cfg_reg[34]      ^ jtg_cfg_reg[34]      ^ 1'h0;
+    {"cfg_tx_one",              33,         33},            //   assign cfg_tx_one          = fus_cfg_reg[33]      ^ jtg_cfg_reg[33]      ^ 1'h0;
+    {"cfg_tx_zero",             32,         32},            //   assign cfg_tx_zero         = fus_cfg_reg[32]      ^ jtg_cfg_reg[32]      ^ 1'h0;
+    {"cfg_rxd_wait",            31,         28},            //   assign cfg_rxd_wait        = fus_cfg_reg[31:28]   ^ jtg_cfg_reg[31:28]   ^ 4'h3;
+    {"cfg_rxd_short",           27,         27},            //   assign cfg_rxd_short       = fus_cfg_reg[27]      ^ jtg_cfg_reg[27]      ^ 1'h0;
+    {"cfg_rxd_set",             26,         26},            //   assign cfg_rxd_set         = fus_cfg_reg[26]      ^ jtg_cfg_reg[26]      ^ 1'h0;
+    {"cfg_rxd_clr",             25,         25},            //   assign cfg_rxd_clr         = fus_cfg_reg[25]      ^ jtg_cfg_reg[25]      ^ 1'h0;
+    {"cfg_loopback",            24,         24},            //   assign cfg_loopback        = fus_cfg_reg[24]      ^ jtg_cfg_reg[24]      ^ 1'h0;
+    {"cfg_tx_idle_set",         23,         23},            //   assign cfg_tx_idle_set     = fus_cfg_reg[23]      ^ jtg_cfg_reg[23]      ^ 1'h0;
+    {"cfg_tx_idle_clr",         22,         22},            //   assign cfg_tx_idle_clr     = fus_cfg_reg[22]      ^ jtg_cfg_reg[22]      ^ 1'h0;
+    {"cfg_rx_idle_set",         21,         21},            //   assign cfg_rx_idle_set     = fus_cfg_reg[21]      ^ jtg_cfg_reg[21]      ^ 1'h0;
+    {"cfg_rx_idle_clr",         20,         20},            //   assign cfg_rx_idle_clr     = fus_cfg_reg[20]      ^ jtg_cfg_reg[20]      ^ 1'h0;
+    {"cfg_rx_idle_thr",         19,         16},            //   assign cfg_rx_idle_thr     = fus_cfg_reg[19:16]   ^ jtg_cfg_reg[19:16]   ^ 4'h0;
+    {"cfg_com_thr",             15,         12},            //   assign cfg_com_thr         = fus_cfg_reg[15:12]   ^ jtg_cfg_reg[15:12]   ^ 4'h3;
+    {"cfg_rx_offset",           11,         8},             //   assign cfg_rx_offset       = fus_cfg_reg[11:8]    ^ jtg_cfg_reg[11:8]    ^ 4'h4;
+    {"cfg_skp_max",             7,          4},             //   assign cfg_skp_max         = fus_cfg_reg[7:4]     ^ jtg_cfg_reg[7:4]     ^ 4'hc;
+    {"cfg_skp_min",             3,          0},             //   assign cfg_skp_min         = fus_cfg_reg[3:0]     ^ jtg_cfg_reg[3:0]     ^ 4'h4;
+    {NULL,                      -1,         -1}
+};
+
+const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn52xx[] =
+{
+    {"prbs_error_count",        267, 220},       // BIST/PRBS error count (only valid if pbrs_lock asserted)
+    {"prbs_unlock_count",       219, 212},       // BIST/PRBS unlock count (only valid if pbrs_lock asserted)
+    {"prbs_locked",             211, 211},       // BIST/PRBS lock (asserted after QLM achieves lock)
+    {"reset_prbs",              210, 210},       // BIST/PRBS reset (write 0 to reset)
+    {"run_prbs",                209, 209},       // run PRBS test pattern
+    {"run_bist",                208, 208},       // run bist (May only work for PCIe ?)
+    {"unknown",                 207, 202},       //
+
+    {"biasdrvsel",              201,        199},           //   assign biasdrvsel          = fus_cfg_reg[201:199] ^ jtg_cfg_reg[201:199] ^ ((pi_qlm_cfg == 2'h0) ? 3'h4 : (pi_qlm_cfg == 2'h2) ? 3'h7 : 3'h2);
+    {"biasbuffsel",             198,        196},           //   assign biasbuffsel         = fus_cfg_reg[198:196] ^ jtg_cfg_reg[198:196] ^ 3'h4;
+    {"tcoeff",                  195,        192},           //   assign tcoeff              = fus_cfg_reg[195:192] ^ jtg_cfg_reg[195:192] ^ (pi_qlm_cfg[1] ? 4'h0 : 4'hc);
+    {"mb5000",                  181,        181},           //   assign mb5000              = fus_cfg_reg[181]     ^ jtg_cfg_reg[181]     ^ 1'h0;
+    {"interpbw",                180,        176},           //   assign interpbw            = fus_cfg_reg[180:176] ^ jtg_cfg_reg[180:176] ^ ((qlm_spd == 2'h0) ? 5'h1f : (qlm_spd == 2'h1) ? 5'h10 : 5'h0);
+    {"mb",                      175,        172},           //   assign mb                  = fus_cfg_reg[175:172] ^ jtg_cfg_reg[175:172] ^ 4'h0;
+    {"bwoff",                   171,        160},           //   assign bwoff               = fus_cfg_reg[171:160] ^ jtg_cfg_reg[171:160] ^ 12'h0;
+    {"bg_ref_sel",              153,        153},           //   assign bg_ref_sel          = fus_cfg_reg[153]     ^ jtg_cfg_reg[153]     ^ 1'h0;
+    {"div2en",                  152,        152},           //   assign div2en              = fus_cfg_reg[152]     ^ jtg_cfg_reg[152]     ^ 1'h0;
+    {"trimen",                  151,        150},           //   assign trimen              = fus_cfg_reg[151:150] ^ jtg_cfg_reg[151:150] ^ 2'h0;
+    {"clkr",                    149,        144},           //   assign clkr                = fus_cfg_reg[149:144] ^ jtg_cfg_reg[149:144] ^ 6'h0;
+    {"clkf",                    143,        132},           //   assign clkf                = fus_cfg_reg[143:132] ^ jtg_cfg_reg[143:132] ^ 12'h18;
+    {"bwadj",                   131,        120},           //   assign bwadj               = fus_cfg_reg[131:120] ^ jtg_cfg_reg[131:120] ^ 12'h30;
+    {"shlpbck",                 119,        118},           //   assign shlpbck             = fus_cfg_reg[119:118] ^ jtg_cfg_reg[119:118] ^ 2'h0;
+    {"serdes_pll_byp",          117,        117},           //   assign serdes_pll_byp      = fus_cfg_reg[117]     ^ jtg_cfg_reg[117]     ^ 1'h0;
+    {"ic50dac",                 116,        112},           //   assign ic50dac             = fus_cfg_reg[116:112] ^ jtg_cfg_reg[116:112] ^ 5'h11;
+    {"sl_posedge_sample",       111,        111},           //   assign sl_posedge_sample   = fus_cfg_reg[111]     ^ jtg_cfg_reg[111]     ^ 1'h0;
+    {"sl_enable",               110,        110},           //   assign sl_enable           = fus_cfg_reg[110]     ^ jtg_cfg_reg[110]     ^ 1'h0;
+    {"rx_rout_comp_bypass",     109,        109},           //   assign rx_rout_comp_bypass = fus_cfg_reg[109]     ^ jtg_cfg_reg[109]     ^ 1'h0;
+    {"ir50dac",                 108,        104},           //   assign ir50dac             = fus_cfg_reg[108:104] ^ jtg_cfg_reg[108:104] ^ 5'h11;
+    {"rx_res_offset",           103,        100},           //   assign rx_res_offset       = fus_cfg_reg[103:100] ^ jtg_cfg_reg[103:100] ^ 4'h2;
+    {"rx_rout_comp_value",      99,         96},            //   assign rx_rout_comp_value  = fus_cfg_reg[99:96]   ^ jtg_cfg_reg[99:96]   ^ 4'h7;
+    {"tx_rout_comp_value",      95,         92},            //   assign tx_rout_comp_value  = fus_cfg_reg[95:92]   ^ jtg_cfg_reg[95:92]   ^ 4'h7;
+    {"tx_res_offset",           91,         88},            //   assign tx_res_offset       = fus_cfg_reg[91:88]   ^ jtg_cfg_reg[91:88]   ^ 4'h1;
+    {"tx_rout_comp_bypass",     87,         87},            //   assign tx_rout_comp_bypass = fus_cfg_reg[87]      ^ jtg_cfg_reg[87]      ^ 1'h0;
+    {"idle_dac",                86,         84},            //   assign idle_dac            = fus_cfg_reg[86:84]   ^ jtg_cfg_reg[86:84]   ^ 3'h4;
+    {"hyst_en",                 83,         83},            //   assign hyst_en             = fus_cfg_reg[83]      ^ jtg_cfg_reg[83]      ^ 1'h1;
+    {"rndt",                    82,         82},            //   assign rndt                = fus_cfg_reg[82]      ^ jtg_cfg_reg[82]      ^ 1'h0;
+    {"cfg_tx_com",              79,         79},            //   CN52XX cfg_tx_com     = fus_cfg_reg[79] ^ jtg_cfg_reg[79] ^ 1'h0;
+    {"cfg_cdr_errcor",          78,         78},            //   CN52XX cfg_cdr_errcor = fus_cfg_reg[78] ^ jtg_cfg_reg[78] ^ 1'h0;
+    {"cfg_cdr_secord",          77,         77},            //   CN52XX cfg_cdr_secord = fus_cfg_reg[77] ^ jtg_cfg_reg[77] ^ 1'h1;
+    {"cfg_cdr_rotate",          76,         76},            //   assign cfg_cdr_rotate      = fus_cfg_reg[76]      ^ jtg_cfg_reg[76]      ^ 1'h0;
+    {"cfg_cdr_rqoffs",          75,         68},            //   assign cfg_cdr_rqoffs      = fus_cfg_reg[75:68]   ^ jtg_cfg_reg[75:68]   ^ 8'h40;
+    {"cfg_cdr_incx",            67,         64},            //   assign cfg_cdr_incx        = fus_cfg_reg[67:64]   ^ jtg_cfg_reg[67:64]   ^ 4'h2;
+    {"cfg_cdr_state",           63,         56},            //   assign cfg_cdr_state       = fus_cfg_reg[63:56]   ^ jtg_cfg_reg[63:56]   ^ 8'h0;
+    {"cfg_cdr_bypass",          55,         55},            //   assign cfg_cdr_bypass      = fus_cfg_reg[55]      ^ jtg_cfg_reg[55]      ^ 1'h0;
+    {"cfg_tx_byp",              54,         54},            //   assign cfg_tx_byp          = fus_cfg_reg[54]      ^ jtg_cfg_reg[54]      ^ 1'h0;
+    {"cfg_tx_val",              53,         44},            //   assign cfg_tx_val          = fus_cfg_reg[53:44]   ^ jtg_cfg_reg[53:44]   ^ 10'h0;
+    {"cfg_rx_pol_set",          43,         43},            //   assign cfg_rx_pol_set      = fus_cfg_reg[43]      ^ jtg_cfg_reg[43]      ^ 1'h0;
+    {"cfg_rx_pol_clr",          42,         42},            //   assign cfg_rx_pol_clr      = fus_cfg_reg[42]      ^ jtg_cfg_reg[42]      ^ 1'h0;
+    {"cfg_cdr_bw_ctl",          41,         40},            //   assign cfg_cdr_bw_ctl      = fus_cfg_reg[41:40]   ^ jtg_cfg_reg[41:40]   ^ 2'h0;
+    {"cfg_rst_n_set",           39,         39},            //   assign cfg_rst_n_set       = fus_cfg_reg[39]      ^ jtg_cfg_reg[39]      ^ 1'h0;
+    {"cfg_rst_n_clr",           38,         38},            //   assign cfg_rst_n_clr       = fus_cfg_reg[38]      ^ jtg_cfg_reg[38]      ^ 1'h0;
+    {"cfg_tx_clk2",             37,         37},            //   assign cfg_tx_clk2         = fus_cfg_reg[37]      ^ jtg_cfg_reg[37]      ^ 1'h0;
+    {"cfg_tx_clk1",             36,         36},            //   assign cfg_tx_clk1         = fus_cfg_reg[36]      ^ jtg_cfg_reg[36]      ^ 1'h0;
+    {"cfg_tx_pol_set",          35,         35},            //   assign cfg_tx_pol_set      = fus_cfg_reg[35]      ^ jtg_cfg_reg[35]      ^ 1'h0;
+    {"cfg_tx_pol_clr",          34,         34},            //   assign cfg_tx_pol_clr      = fus_cfg_reg[34]      ^ jtg_cfg_reg[34]      ^ 1'h0;
+    {"cfg_tx_one",              33,         33},            //   assign cfg_tx_one          = fus_cfg_reg[33]      ^ jtg_cfg_reg[33]      ^ 1'h0;
+    {"cfg_tx_zero",             32,         32},            //   assign cfg_tx_zero         = fus_cfg_reg[32]      ^ jtg_cfg_reg[32]      ^ 1'h0;
+    {"cfg_rxd_wait",            31,         28},            //   assign cfg_rxd_wait        = fus_cfg_reg[31:28]   ^ jtg_cfg_reg[31:28]   ^ 4'h3;
+    {"cfg_rxd_short",           27,         27},            //   assign cfg_rxd_short       = fus_cfg_reg[27]      ^ jtg_cfg_reg[27]      ^ 1'h0;
+    {"cfg_rxd_set",             26,         26},            //   assign cfg_rxd_set         = fus_cfg_reg[26]      ^ jtg_cfg_reg[26]      ^ 1'h0;
+    {"cfg_rxd_clr",             25,         25},            //   assign cfg_rxd_clr         = fus_cfg_reg[25]      ^ jtg_cfg_reg[25]      ^ 1'h0;
+    {"cfg_loopback",            24,         24},            //   assign cfg_loopback        = fus_cfg_reg[24]      ^ jtg_cfg_reg[24]      ^ 1'h0;
+    {"cfg_tx_idle_set",         23,         23},            //   assign cfg_tx_idle_set     = fus_cfg_reg[23]      ^ jtg_cfg_reg[23]      ^ 1'h0;
+    {"cfg_tx_idle_clr",         22,         22},            //   assign cfg_tx_idle_clr     = fus_cfg_reg[22]      ^ jtg_cfg_reg[22]      ^ 1'h0;
+    {"cfg_rx_idle_set",         21,         21},            //   assign cfg_rx_idle_set     = fus_cfg_reg[21]      ^ jtg_cfg_reg[21]      ^ 1'h0;
+    {"cfg_rx_idle_clr",         20,         20},            //   assign cfg_rx_idle_clr     = fus_cfg_reg[20]      ^ jtg_cfg_reg[20]      ^ 1'h0;
+    {"cfg_rx_idle_thr",         19,         16},            //   assign cfg_rx_idle_thr     = fus_cfg_reg[19:16]   ^ jtg_cfg_reg[19:16]   ^ 4'h0;
+    {"cfg_com_thr",             15,         12},            //   assign cfg_com_thr         = fus_cfg_reg[15:12]   ^ jtg_cfg_reg[15:12]   ^ 4'h3;
+    {"cfg_rx_offset",           11,         8},             //   assign cfg_rx_offset       = fus_cfg_reg[11:8]    ^ jtg_cfg_reg[11:8]    ^ 4'h4;
+    {"cfg_skp_max",             7,          4},             //   assign cfg_skp_max         = fus_cfg_reg[7:4]     ^ jtg_cfg_reg[7:4]     ^ 4'hc;
+    {"cfg_skp_min",             3,          0},             //   assign cfg_skp_min         = fus_cfg_reg[3:0]     ^ jtg_cfg_reg[3:0]     ^ 4'h4;
+    {NULL,                      -1,         -1}
+};
+
+
+const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn63xx[] =
+{
+    {"prbs_err_cnt",        299, 252},  // prbs_err_cnt[47..0]
+    {"prbs_lock",           251, 251},  // prbs_lock
+    {"jtg_prbs_rst_n",      250, 250},  // jtg_prbs_rst_n
+    {"jtg_run_prbs31",      249, 249},  // jtg_run_prbs31
+    {"jtg_run_prbs7",       248, 248},  // jtg_run_prbs7
+    {"Unused1",             247, 245},  // 0
+    {"cfg_pwrup_set",       244, 244},  // cfg_pwrup_set
+    {"cfg_pwrup_clr",       243, 243},  // cfg_pwrup_clr
+    {"cfg_rst_n_set",       242, 242},  // cfg_rst_n_set
+    {"cfg_rst_n_clr",       241, 241},  // cfg_rst_n_clr
+    {"cfg_tx_idle_set",     240, 240},  // cfg_tx_idle_set
+    {"cfg_tx_idle_clr",     239, 239},  // cfg_tx_idle_clr
+    {"cfg_tx_byp",          238, 238},  // cfg_tx_byp
+    {"cfg_tx_byp_inv",      237, 237},  // cfg_tx_byp_inv
+    {"cfg_tx_byp_val",      236, 227},  // cfg_tx_byp_val[9..0]
+    {"cfg_loopback",        226, 226},  // cfg_loopback
+    {"shlpbck",             225, 224},  // shlpbck[1..0]
+    {"sl_enable",           223, 223},  // sl_enable
+    {"sl_posedge_sample",   222, 222},  // sl_posedge_sample
+    {"trimen",              221, 220},  // trimen[1..0]
+    {"serdes_tx_byp",       219, 219},  // serdes_tx_byp
+    {"serdes_pll_byp",      218, 218},  // serdes_pll_byp
+    {"lowf_byp",            217, 217},  // lowf_byp
+    {"spdsel_byp",          216, 216},  // spdsel_byp
+    {"div4_byp",            215, 215},  // div4_byp
+    {"clkf_byp",            214, 208},  // clkf_byp[6..0]
+    {"Unused2",             207, 206},  // 0
+    {"biasdrv_hs_ls_byp",   205, 201},  // biasdrv_hs_ls_byp[4..0]
+    {"tcoeff_hf_ls_byp",    200, 197},  // tcoeff_hf_ls_byp[3..0]
+    {"biasdrv_hf_byp",      196, 192},  // biasdrv_hf_byp[4..0]
+    {"tcoeff_hf_byp",       191, 188},  // tcoeff_hf_byp[3..0]
+    {"Unused3",             187, 186},  // 0
+    {"biasdrv_lf_ls_byp",   185, 181},  // biasdrv_lf_ls_byp[4..0]
+    {"tcoeff_lf_ls_byp",    180, 177},  // tcoeff_lf_ls_byp[3..0]
+    {"biasdrv_lf_byp",      176, 172},  // biasdrv_lf_byp[4..0]
+    {"tcoeff_lf_byp",       171, 168},  // tcoeff_lf_byp[3..0]
+    {"Unused4",             167, 167},  // 0
+    {"interpbw",            166, 162},  // interpbw[4..0]
+    {"pll_cpb",             161, 159},  // pll_cpb[2..0]
+    {"pll_cps",             158, 156},  // pll_cps[2..0]
+    {"pll_diffamp",         155, 152},  // pll_diffamp[3..0]
+    {"Unused5",             151, 150},  // 0
+    {"cfg_rx_idle_set",     149, 149},  // cfg_rx_idle_set
+    {"cfg_rx_idle_clr",     148, 148},  // cfg_rx_idle_clr
+    {"cfg_rx_idle_thr",     147, 144},  // cfg_rx_idle_thr[3..0]
+    {"cfg_com_thr",         143, 140},  // cfg_com_thr[3..0]
+    {"cfg_rx_offset",       139, 136},  // cfg_rx_offset[3..0]
+    {"cfg_skp_max",         135, 132},  // cfg_skp_max[3..0]
+    {"cfg_skp_min",         131, 128},  // cfg_skp_min[3..0]
+    {"cfg_fast_pwrup",      127, 127},  // cfg_fast_pwrup
+    {"Unused6",             126, 100},  // 0
+    {"detected_n",           99,  99},  // detected_n
+    {"detected_p",           98,  98},  // detected_p
+    {"dbg_res_rx",           97,  94},  // dbg_res_rx[3..0]
+    {"dbg_res_tx",           93,  90},  // dbg_res_tx[3..0]
+    {"cfg_tx_pol_set",       89,  89},  // cfg_tx_pol_set
+    {"cfg_tx_pol_clr",       88,  88},  // cfg_tx_pol_clr
+    {"cfg_rx_pol_set",       87,  87},  // cfg_rx_pol_set
+    {"cfg_rx_pol_clr",       86,  86},  // cfg_rx_pol_clr
+    {"cfg_rxd_set",          85,  85},  // cfg_rxd_set
+    {"cfg_rxd_clr",          84,  84},  // cfg_rxd_clr
+    {"cfg_rxd_wait",         83,  80},  // cfg_rxd_wait[3..0]
+    {"cfg_cdr_limit",        79,  79},  // cfg_cdr_limit
+    {"cfg_cdr_rotate",       78,  78},  // cfg_cdr_rotate
+    {"cfg_cdr_bw_ctl",       77,  76},  // cfg_cdr_bw_ctl[1..0]
+    {"cfg_cdr_trunc",        75,  74},  // cfg_cdr_trunc[1..0]
+    {"cfg_cdr_rqoffs",       73,  64},  // cfg_cdr_rqoffs[9..0]
+    {"cfg_cdr_inc2",         63,  58},  // cfg_cdr_inc2[5..0]
+    {"cfg_cdr_inc1",         57,  52},  // cfg_cdr_inc1[5..0]
+    {"fusopt_voter_sync",    51,  51},  // fusopt_voter_sync
+    {"rndt",                 50,  50},  // rndt
+    {"hcya",                 49,  49},  // hcya
+    {"hyst",                 48,  48},  // hyst
+    {"idle_dac",             47,  45},  // idle_dac[2..0]
+    {"bg_ref_sel",           44,  44},  // bg_ref_sel
+    {"ic50dac",              43,  39},  // ic50dac[4..0]
+    {"ir50dac",              38,  34},  // ir50dac[4..0]
+    {"tx_rout_comp_bypass",  33,  33},  // tx_rout_comp_bypass
+    {"tx_rout_comp_value",   32,  29},  // tx_rout_comp_value[3..0]
+    {"tx_res_offset",        28,  25},  // tx_res_offset[3..0]
+    {"rx_rout_comp_bypass",  24,  24},  // rx_rout_comp_bypass
+    {"rx_rout_comp_value",   23,  20},  // rx_rout_comp_value[3..0]
+    {"rx_res_offset",        19,  16},  // rx_res_offset[3..0]
+    {"rx_cap_gen2",          15,  12},  // rx_cap_gen2[3..0]
+    {"rx_eq_gen2",           11,   8},  // rx_eq_gen2[3..0]
+    {"rx_cap_gen1",           7,   4},  // rx_cap_gen1[3..0]
+    {"rx_eq_gen1",            3,   0},  // rx_eq_gen1[3..0]
+    {NULL, -1, -1}
+};
+
+const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn66xx[] =
+{
+    {"prbs_err_cnt",        303, 256},  // prbs_err_cnt[47..0]
+    {"prbs_lock",           255, 255},  // prbs_lock
+    {"jtg_prbs_rx_rst_n",   254, 254},  // jtg_prbs_rx_rst_n
+    {"jtg_prbs_tx_rst_n",   253, 253},  // jtg_prbs_tx_rst_n
+    {"jtg_prbs_mode",       252, 251},  // jtg_prbs_mode[252:251]
+    {"jtg_prbs_rst_n",      250, 250},  // jtg_prbs_rst_n
+    {"jtg_run_prbs31",      249, 249},  // jtg_run_prbs31 - Use jtg_prbs_mode instead
+    {"jtg_run_prbs7",       248, 248},  // jtg_run_prbs7 - Use jtg_prbs_mode instead
+    {"Unused1",             247, 246},  // 0
+    {"div5_byp",            245, 245},  // div5_byp
+    {"cfg_pwrup_set",       244, 244},  // cfg_pwrup_set
+    {"cfg_pwrup_clr",       243, 243},  // cfg_pwrup_clr
+    {"cfg_rst_n_set",       242, 242},  // cfg_rst_n_set
+    {"cfg_rst_n_clr",       241, 241},  // cfg_rst_n_clr
+    {"cfg_tx_idle_set",     240, 240},  // cfg_tx_idle_set
+    {"cfg_tx_idle_clr",     239, 239},  // cfg_tx_idle_clr
+    {"cfg_tx_byp",          238, 238},  // cfg_tx_byp
+    {"cfg_tx_byp_inv",      237, 237},  // cfg_tx_byp_inv
+    {"cfg_tx_byp_val",      236, 227},  // cfg_tx_byp_val[9..0]
+    {"cfg_loopback",        226, 226},  // cfg_loopback
+    {"shlpbck",             225, 224},  // shlpbck[1..0]
+    {"sl_enable",           223, 223},  // sl_enable
+    {"sl_posedge_sample",   222, 222},  // sl_posedge_sample
+    {"trimen",              221, 220},  // trimen[1..0]
+    {"serdes_tx_byp",       219, 219},  // serdes_tx_byp
+    {"serdes_pll_byp",      218, 218},  // serdes_pll_byp
+    {"lowf_byp",            217, 217},  // lowf_byp
+    {"spdsel_byp",          216, 216},  // spdsel_byp
+    {"div4_byp",            215, 215},  // div4_byp
+    {"clkf_byp",            214, 208},  // clkf_byp[6..0]
+    {"biasdrv_hs_ls_byp",   207, 203},  // biasdrv_hs_ls_byp[4..0]
+    {"tcoeff_hf_ls_byp",    202, 198},  // tcoeff_hf_ls_byp[4..0]
+    {"biasdrv_hf_byp",      197, 193},  // biasdrv_hf_byp[4..0]
+    {"tcoeff_hf_byp",       192, 188},  // tcoeff_hf_byp[4..0]
+    {"biasdrv_lf_ls_byp",   187, 183},  // biasdrv_lf_ls_byp[4..0]
+    {"tcoeff_lf_ls_byp",    182, 178},  // tcoeff_lf_ls_byp[4..0]
+    {"biasdrv_lf_byp",      177, 173},  // biasdrv_lf_byp[4..0]
+    {"tcoeff_lf_byp",       172, 168},  // tcoeff_lf_byp[4..0]
+    {"Unused4",             167, 167},  // 0
+    {"interpbw",            166, 162},  // interpbw[4..0]
+    {"pll_cpb",             161, 159},  // pll_cpb[2..0]
+    {"pll_cps",             158, 156},  // pll_cps[2..0]
+    {"pll_diffamp",         155, 152},  // pll_diffamp[3..0]
+    {"cfg_err_thr",         151, 150},  // cfg_err_thr
+    {"cfg_rx_idle_set",     149, 149},  // cfg_rx_idle_set
+    {"cfg_rx_idle_clr",     148, 148},  // cfg_rx_idle_clr
+    {"cfg_rx_idle_thr",     147, 144},  // cfg_rx_idle_thr[3..0]
+    {"cfg_com_thr",         143, 140},  // cfg_com_thr[3..0]
+    {"cfg_rx_offset",       139, 136},  // cfg_rx_offset[3..0]
+    {"cfg_skp_max",         135, 132},  // cfg_skp_max[3..0]
+    {"cfg_skp_min",         131, 128},  // cfg_skp_min[3..0]
+    {"cfg_fast_pwrup",      127, 127},  // cfg_fast_pwrup
+    {"Unused6",             126, 101},  // 0
+    {"cfg_indep_dis",       100, 100},  // cfg_indep_dis
+    {"detected_n",           99,  99},  // detected_n
+    {"detected_p",           98,  98},  // detected_p
+    {"dbg_res_rx",           97,  94},  // dbg_res_rx[3..0]
+    {"dbg_res_tx",           93,  90},  // dbg_res_tx[3..0]
+    {"cfg_tx_pol_set",       89,  89},  // cfg_tx_pol_set
+    {"cfg_tx_pol_clr",       88,  88},  // cfg_tx_pol_clr
+    {"cfg_rx_pol_set",       87,  87},  // cfg_rx_pol_set
+    {"cfg_rx_pol_clr",       86,  86},  // cfg_rx_pol_clr
+    {"cfg_rxd_set",          85,  85},  // cfg_rxd_set
+    {"cfg_rxd_clr",          84,  84},  // cfg_rxd_clr
+    {"cfg_rxd_wait",         83,  80},  // cfg_rxd_wait[3..0]
+    {"cfg_cdr_limit",        79,  79},  // cfg_cdr_limit
+    {"cfg_cdr_rotate",       78,  78},  // cfg_cdr_rotate
+    {"cfg_cdr_bw_ctl",       77,  76},  // cfg_cdr_bw_ctl[1..0]
+    {"cfg_cdr_trunc",        75,  74},  // cfg_cdr_trunc[1..0]
+    {"cfg_cdr_rqoffs",       73,  64},  // cfg_cdr_rqoffs[9..0]
+    {"cfg_cdr_inc2",         63,  58},  // cfg_cdr_inc2[5..0]
+    {"cfg_cdr_inc1",         57,  52},  // cfg_cdr_inc1[5..0]
+    {"fusopt_voter_sync",    51,  51},  // fusopt_voter_sync
+    {"rndt",                 50,  50},  // rndt
+    {"hcya",                 49,  49},  // hcya
+    {"hyst",                 48,  48},  // hyst
+    {"idle_dac",             47,  45},  // idle_dac[2..0]
+    {"bg_ref_sel",           44,  44},  // bg_ref_sel
+    {"ic50dac",              43,  39},  // ic50dac[4..0]
+    {"ir50dac",              38,  34},  // ir50dac[4..0]
+    {"tx_rout_comp_bypass",  33,  33},  // tx_rout_comp_bypass
+    {"tx_rout_comp_value",   32,  29},  // tx_rout_comp_value[3..0]
+    {"tx_res_offset",        28,  25},  // tx_res_offset[3..0]
+    {"rx_rout_comp_bypass",  24,  24},  // rx_rout_comp_bypass
+    {"rx_rout_comp_value",   23,  20},  // rx_rout_comp_value[3..0]
+    {"rx_res_offset",        19,  16},  // rx_res_offset[3..0]
+    {"rx_cap_gen2",          15,  12},  // rx_cap_gen2[3..0]
+    {"rx_eq_gen2",           11,   8},  // rx_eq_gen2[3..0]
+    {"rx_cap_gen1",           7,   4},  // rx_cap_gen1[3..0]
+    {"rx_eq_gen1",            3,   0},  // rx_eq_gen1[3..0]
+    {NULL, -1, -1}
+};
+
+const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn68xx[] =
+{
+    {"prbs_err_cnt",        303, 256},  // prbs_err_cnt[47..0]
+    {"prbs_lock",           255, 255},  // prbs_lock
+    {"jtg_prbs_rx_rst_n",   254, 254},  // jtg_prbs_rx_rst_n
+    {"jtg_prbs_tx_rst_n",   253, 253},  // jtg_prbs_tx_rst_n
+    {"jtg_prbs_mode",       252, 251},  // jtg_prbs_mode[252:251]
+    {"jtg_prbs_rst_n",      250, 250},  // jtg_prbs_rst_n
+    {"jtg_run_prbs31",      249, 249},  // jtg_run_prbs31 - Use jtg_prbs_mode instead
+    {"jtg_run_prbs7",       248, 248},  // jtg_run_prbs7 - Use jtg_prbs_mode instead
+    {"Unused1",             247, 245},  // 0
+    {"cfg_pwrup_set",       244, 244},  // cfg_pwrup_set
+    {"cfg_pwrup_clr",       243, 243},  // cfg_pwrup_clr
+    {"cfg_rst_n_set",       242, 242},  // cfg_rst_n_set
+    {"cfg_rst_n_clr",       241, 241},  // cfg_rst_n_clr
+    {"cfg_tx_idle_set",     240, 240},  // cfg_tx_idle_set
+    {"cfg_tx_idle_clr",     239, 239},  // cfg_tx_idle_clr
+    {"cfg_tx_byp",          238, 238},  // cfg_tx_byp
+    {"cfg_tx_byp_inv",      237, 237},  // cfg_tx_byp_inv
+    {"cfg_tx_byp_val",      236, 227},  // cfg_tx_byp_val[9..0]
+    {"cfg_loopback",        226, 226},  // cfg_loopback
+    {"shlpbck",             225, 224},  // shlpbck[1..0]
+    {"sl_enable",           223, 223},  // sl_enable
+    {"sl_posedge_sample",   222, 222},  // sl_posedge_sample
+    {"trimen",              221, 220},  // trimen[1..0]
+    {"serdes_tx_byp",       219, 219},  // serdes_tx_byp
+    {"serdes_pll_byp",      218, 218},  // serdes_pll_byp
+    {"lowf_byp",            217, 217},  // lowf_byp
+    {"spdsel_byp",          216, 216},  // spdsel_byp
+    {"div4_byp",            215, 215},  // div4_byp
+    {"clkf_byp",            214, 208},  // clkf_byp[6..0]
+    {"biasdrv_hs_ls_byp",   207, 203},  // biasdrv_hs_ls_byp[4..0]
+    {"tcoeff_hf_ls_byp",    202, 198},  // tcoeff_hf_ls_byp[4..0]
+    {"biasdrv_hf_byp",      197, 193},  // biasdrv_hf_byp[4..0]
+    {"tcoeff_hf_byp",       192, 188},  // tcoeff_hf_byp[4..0]
+    {"biasdrv_lf_ls_byp",   187, 183},  // biasdrv_lf_ls_byp[4..0]
+    {"tcoeff_lf_ls_byp",    182, 178},  // tcoeff_lf_ls_byp[4..0]
+    {"biasdrv_lf_byp",      177, 173},  // biasdrv_lf_byp[4..0]
+    {"tcoeff_lf_byp",       172, 168},  // tcoeff_lf_byp[4..0]
+    {"Unused4",             167, 167},  // 0
+    {"interpbw",            166, 162},  // interpbw[4..0]
+    {"pll_cpb",             161, 159},  // pll_cpb[2..0]
+    {"pll_cps",             158, 156},  // pll_cps[2..0]
+    {"pll_diffamp",         155, 152},  // pll_diffamp[3..0]
+    {"cfg_err_thr",         151, 150},  // cfg_err_thr
+    {"cfg_rx_idle_set",     149, 149},  // cfg_rx_idle_set
+    {"cfg_rx_idle_clr",     148, 148},  // cfg_rx_idle_clr
+    {"cfg_rx_idle_thr",     147, 144},  // cfg_rx_idle_thr[3..0]
+    {"cfg_com_thr",         143, 140},  // cfg_com_thr[3..0]
+    {"cfg_rx_offset",       139, 136},  // cfg_rx_offset[3..0]
+    {"cfg_skp_max",         135, 132},  // cfg_skp_max[3..0]
+    {"cfg_skp_min",         131, 128},  // cfg_skp_min[3..0]
+    {"cfg_fast_pwrup",      127, 127},  // cfg_fast_pwrup
+    {"Unused6",             126, 100},  // 0
+    {"detected_n",           99,  99},  // detected_n
+    {"detected_p",           98,  98},  // detected_p
+    {"dbg_res_rx",           97,  94},  // dbg_res_rx[3..0]
+    {"dbg_res_tx",           93,  90},  // dbg_res_tx[3..0]
+    {"cfg_tx_pol_set",       89,  89},  // cfg_tx_pol_set
+    {"cfg_tx_pol_clr",       88,  88},  // cfg_tx_pol_clr
+    {"cfg_rx_pol_set",       87,  87},  // cfg_rx_pol_set
+    {"cfg_rx_pol_clr",       86,  86},  // cfg_rx_pol_clr
+    {"cfg_rxd_set",          85,  85},  // cfg_rxd_set
+    {"cfg_rxd_clr",          84,  84},  // cfg_rxd_clr
+    {"cfg_rxd_wait",         83,  80},  // cfg_rxd_wait[3..0]
+    {"cfg_cdr_limit",        79,  79},  // cfg_cdr_limit
+    {"cfg_cdr_rotate",       78,  78},  // cfg_cdr_rotate
+    {"cfg_cdr_bw_ctl",       77,  76},  // cfg_cdr_bw_ctl[1..0]
+    {"cfg_cdr_trunc",        75,  74},  // cfg_cdr_trunc[1..0]
+    {"cfg_cdr_rqoffs",       73,  64},  // cfg_cdr_rqoffs[9..0]
+    {"cfg_cdr_inc2",         63,  58},  // cfg_cdr_inc2[5..0]
+    {"cfg_cdr_inc1",         57,  52},  // cfg_cdr_inc1[5..0]
+    {"fusopt_voter_sync",    51,  51},  // fusopt_voter_sync
+    {"rndt",                 50,  50},  // rndt
+    {"hcya",                 49,  49},  // hcya
+    {"hyst",                 48,  48},  // hyst
+    {"idle_dac",             47,  45},  // idle_dac[2..0]
+    {"bg_ref_sel",           44,  44},  // bg_ref_sel
+    {"ic50dac",              43,  39},  // ic50dac[4..0]
+    {"ir50dac",              38,  34},  // ir50dac[4..0]
+    {"tx_rout_comp_bypass",  33,  33},  // tx_rout_comp_bypass
+    {"tx_rout_comp_value",   32,  29},  // tx_rout_comp_value[3..0]
+    {"tx_res_offset",        28,  25},  // tx_res_offset[3..0]
+    {"rx_rout_comp_bypass",  24,  24},  // rx_rout_comp_bypass
+    {"rx_rout_comp_value",   23,  20},  // rx_rout_comp_value[3..0]
+    {"rx_res_offset",        19,  16},  // rx_res_offset[3..0]
+    {"rx_cap_gen2",          15,  12},  // rx_cap_gen2[3..0]
+    {"rx_eq_gen2",           11,   8},  // rx_eq_gen2[3..0]
+    {"rx_cap_gen1",           7,   4},  // rx_cap_gen1[3..0]
+    {"rx_eq_gen1",            3,   0},  // rx_eq_gen1[3..0]
+    {NULL, -1, -1}
+};
+
diff --git a/sys/contrib/octeon-sdk/cvmx-qlm.c b/sys/contrib/octeon-sdk/cvmx-qlm.c
new file mode 100644
index 0000000..183c054
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-qlm.c
@@ -0,0 +1,740 @@
+/***********************license start***************
+ * Copyright (c) 2011  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Helper utilities for qlm.
+ *
+ * <hr>$Revision: 70129 $<hr>
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-bootmem.h>
+#include <asm/octeon/cvmx-helper-jtag.h>
+#include <asm/octeon/cvmx-qlm.h>
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-sriox-defs.h>
+#include <asm/octeon/cvmx-sriomaintx-defs.h>
+#include <asm/octeon/cvmx-pciercx-defs.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "executive-config.h"
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-bootmem.h"
+#include "cvmx-helper-jtag.h"
+#include "cvmx-qlm.h"
+#else
+#include "cvmx.h"
+#include "cvmx-bootmem.h"
+#include "cvmx-helper-jtag.h"
+#include "cvmx-qlm.h"
+#endif
+
+#endif
+
+/**
+ * The JTAG chain for CN52XX and CN56XX is 4 * 268 bits long, or 1072.
+ * CN5XXX full chain shift is:
+ *     new data => lane 3 => lane 2 => lane 1 => lane 0 => data out
+ * The JTAG chain for CN63XX is 4 * 300 bits long, or 1200.
+ * The JTAG chain for CN68XX is 4 * 304 bits long, or 1216.
+ * The JTAG chain for CN66XX/CN61XX/CNF71XX is 4 * 304 bits long, or 1216.
+ * CN6XXX full chain shift is:
+ *     new data => lane 0 => lane 1 => lane 2 => lane 3 => data out
+ * Shift LSB first, get LSB out
+ */
+extern const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn52xx[];
+extern const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn56xx[];
+extern const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn63xx[];
+extern const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn66xx[];
+extern const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn68xx[];
+
+#define CVMX_QLM_JTAG_UINT32 40
+#ifdef CVMX_BUILD_FOR_LINUX_HOST
+extern void octeon_remote_read_mem(void *buffer, uint64_t physical_address, int length);
+extern void octeon_remote_write_mem(uint64_t physical_address, const void *buffer, int length);
+uint32_t __cvmx_qlm_jtag_xor_ref[5][CVMX_QLM_JTAG_UINT32];
+#else
+typedef uint32_t qlm_jtag_uint32_t[CVMX_QLM_JTAG_UINT32];
+CVMX_SHARED qlm_jtag_uint32_t *__cvmx_qlm_jtag_xor_ref;
+#endif
+
+
+/**
+ * Return the number of QLMs supported by the chip
+ * 
+ * @return  Number of QLMs
+ */
+int cvmx_qlm_get_num(void)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+        return 5;
+    else if (OCTEON_IS_MODEL(OCTEON_CN66XX))
+        return 3;
+    else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+        return 3;
+    else if (OCTEON_IS_MODEL(OCTEON_CN61XX))
+        return 3;
+    else if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+        return 4;
+    else if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
+        return 2;
+
+    //cvmx_dprintf("Warning: cvmx_qlm_get_num: This chip does not have QLMs\n");
+    return 0;
+}
+
+/**
+ * Return the qlm number based on the interface
+ *
+ * @param interface  Interface to look up
+ */
+int cvmx_qlm_interface(int interface)
+{
+	if (OCTEON_IS_MODEL(OCTEON_CN61XX)) {
+		return (interface == 0) ? 2 : 0;
+	} else if (OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)) {
+		return 2 - interface;
+	} else {
+		/* Must be cn68XX */
+		switch(interface) {
+		case 1:
+			return 0;
+		default:
+			return interface;
+		}
+	}
+}
+
+/**
+ * Return number of lanes for a given qlm
+ * 
+ * @return  Number of lanes
+ */
+int cvmx_qlm_get_lanes(int qlm)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN61XX) && qlm == 1)
+        return 2;
+    else if (OCTEON_IS_MODEL(OCTEON_CNF71XX))
+        return 2;
+    
+    return 4;
+}
+
+/**
+ * Get the QLM JTAG fields based on Octeon model on the supported chips. 
+ *
+ * @return  qlm_jtag_field_t structure
+ */
+const __cvmx_qlm_jtag_field_t *cvmx_qlm_jtag_get_field(void)
+{
+    /* Figure out which JTAG chain description we're using */
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+        return __cvmx_qlm_jtag_field_cn68xx;
+    else if (OCTEON_IS_MODEL(OCTEON_CN66XX) 
+             || OCTEON_IS_MODEL(OCTEON_CN61XX)
+             || OCTEON_IS_MODEL(OCTEON_CNF71XX))
+        return __cvmx_qlm_jtag_field_cn66xx;
+    else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+        return __cvmx_qlm_jtag_field_cn63xx;
+    else if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+        return __cvmx_qlm_jtag_field_cn56xx;
+    else if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+        return __cvmx_qlm_jtag_field_cn52xx;
+    else
+    {
+        //cvmx_dprintf("cvmx_qlm_jtag_get_field: Needs update for this chip\n");
+        return NULL;
+    }
+}
+
+/**
+ * Get the QLM JTAG length by going through qlm_jtag_field for each
+ * Octeon model that is supported
+ *
+ * @return return the length.
+ */
+int cvmx_qlm_jtag_get_length(void)
+{
+    const __cvmx_qlm_jtag_field_t *qlm_ptr = cvmx_qlm_jtag_get_field();
+    int length = 0;
+
+    /* Figure out how many bits are in the JTAG chain */
+    while (qlm_ptr != NULL && qlm_ptr->name)
+    {
+        if (qlm_ptr->stop_bit > length)
+            length = qlm_ptr->stop_bit + 1;
+        qlm_ptr++;
+    }
+    return length;
+}
+
+/**
+ * Initialize the QLM layer
+ */
+void cvmx_qlm_init(void)
+{
+    int qlm;
+    int qlm_jtag_length;
+    char *qlm_jtag_name = "cvmx_qlm_jtag";
+    int qlm_jtag_size = CVMX_QLM_JTAG_UINT32 * 8 * 4;
+    static uint64_t qlm_base = 0;
+    const cvmx_bootmem_named_block_desc_t *desc;
+    
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
+    /* Skip actual JTAG accesses on simulator */
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+        return;
+#endif
+
+    qlm_jtag_length = cvmx_qlm_jtag_get_length();
+
+    if (4 * qlm_jtag_length > (int)sizeof(__cvmx_qlm_jtag_xor_ref[0]) * 8)
+    {
+        cvmx_dprintf("ERROR: cvmx_qlm_init: JTAG chain larger than XOR ref size\n");
+        return;
+    }
+
+    /* No need to initialize the initial JTAG state if cvmx_qlm_jtag
+       named block is already created. */
+    if ((desc = cvmx_bootmem_find_named_block(qlm_jtag_name)) != NULL)
+    {
+#ifdef CVMX_BUILD_FOR_LINUX_HOST
+        char buffer[qlm_jtag_size];
+
+        octeon_remote_read_mem(buffer, desc->base_addr, qlm_jtag_size);
+        memcpy(__cvmx_qlm_jtag_xor_ref, buffer, qlm_jtag_size);
+#else
+        __cvmx_qlm_jtag_xor_ref = cvmx_phys_to_ptr(desc->base_addr);
+#endif
+        /* Initialize the internal JTAG */
+        cvmx_helper_qlm_jtag_init();
+        return;
+    }
+
+    /* Create named block to store the initial JTAG state. */
+    qlm_base = cvmx_bootmem_phy_named_block_alloc(qlm_jtag_size, 0, 0, 128, qlm_jtag_name, CVMX_BOOTMEM_FLAG_END_ALLOC);
+
+    if (qlm_base == -1ull)
+    {
+        cvmx_dprintf("ERROR: cvmx_qlm_init: Error in creating %s named block\n", qlm_jtag_name);
+        return;
+    }
+
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
+    __cvmx_qlm_jtag_xor_ref = cvmx_phys_to_ptr(qlm_base);
+#endif
+    memset(__cvmx_qlm_jtag_xor_ref, 0, qlm_jtag_size);
+
+    /* Initialize the internal JTAG */
+    cvmx_helper_qlm_jtag_init();
+
+    /* Read the XOR defaults for the JTAG chain */
+    for (qlm=0; qlm<cvmx_qlm_get_num(); qlm++)
+    {
+        int i;
+        /* Capture the reset defaults */
+        cvmx_helper_qlm_jtag_capture(qlm);
+        /* Save the reset defaults. This will shift out too much data, but
+           the extra zeros don't hurt anything */
+        for (i=0; i<CVMX_QLM_JTAG_UINT32; i++)
+            __cvmx_qlm_jtag_xor_ref[qlm][i] = cvmx_helper_qlm_jtag_shift(qlm, 32, 0);
+    }
+
+#ifdef CVMX_BUILD_FOR_LINUX_HOST
+    /* Update the initial state for oct-remote utils. */
+    {
+        char buffer[qlm_jtag_size];
+
+        memcpy(buffer, &__cvmx_qlm_jtag_xor_ref, qlm_jtag_size);
+        octeon_remote_write_mem(qlm_base, buffer, qlm_jtag_size);
+    }
+#endif
+
+    /* Apply speed tweak as a workaround for errata G-16094. */
+    __cvmx_qlm_speed_tweak();
+    __cvmx_qlm_pcie_idle_dac_tweak();
+}
+
+/**
+ * Lookup the bit information for a JTAG field name
+ *
+ * @param name   Name to lookup
+ *
+ * @return Field info, or NULL on failure
+ */
+static const __cvmx_qlm_jtag_field_t *__cvmx_qlm_lookup_field(const char *name)
+{
+    const __cvmx_qlm_jtag_field_t *ptr = cvmx_qlm_jtag_get_field();
+    while (ptr->name)
+    {
+        if (strcmp(name, ptr->name) == 0)
+            return ptr;
+        ptr++;
+    }
+    cvmx_dprintf("__cvmx_qlm_lookup_field: Illegal field name %s\n", name);
+    return NULL;
+}
+
+/**
+ * Get a field in a QLM JTAG chain
+ *
+ * @param qlm    QLM to get
+ * @param lane   Lane in QLM to get
+ * @param name   String name of field
+ *
+ * @return JTAG field value
+ */
+uint64_t cvmx_qlm_jtag_get(int qlm, int lane, const char *name)
+{
+    const __cvmx_qlm_jtag_field_t *field = __cvmx_qlm_lookup_field(name);
+    int qlm_jtag_length = cvmx_qlm_jtag_get_length();
+    int num_lanes = cvmx_qlm_get_lanes(qlm);
+
+    if (!field)
+        return 0;
+
+    /* Capture the current settings */
+    cvmx_helper_qlm_jtag_capture(qlm);
+    /* Shift past lanes we don't care about. CN6XXX shifts lane 3 first */
+    cvmx_helper_qlm_jtag_shift_zeros(qlm, qlm_jtag_length * (num_lanes-1-lane));    /* Shift to the start of the field */
+    cvmx_helper_qlm_jtag_shift_zeros(qlm, field->start_bit);
+    /* Shift out the value and return it */
+    return cvmx_helper_qlm_jtag_shift(qlm, field->stop_bit - field->start_bit + 1, 0);
+}
+
+/**
+ * Set a field in a QLM JTAG chain
+ *
+ * @param qlm    QLM to set
+ * @param lane   Lane in QLM to set, or -1 for all lanes
+ * @param name   String name of field
+ * @param value  Value of the field
+ */
+void cvmx_qlm_jtag_set(int qlm, int lane, const char *name, uint64_t value)
+{
+    int i, l;
+    uint32_t shift_values[CVMX_QLM_JTAG_UINT32];
+    int num_lanes = cvmx_qlm_get_lanes(qlm);
+    const __cvmx_qlm_jtag_field_t *field = __cvmx_qlm_lookup_field(name);
+    int qlm_jtag_length = cvmx_qlm_jtag_get_length();
+    int total_length = qlm_jtag_length * num_lanes;
+    int bits = 0;
+
+    if (!field)
+        return;
+
+    /* Get the current state */
+    cvmx_helper_qlm_jtag_capture(qlm);
+    for (i=0; i<CVMX_QLM_JTAG_UINT32; i++)
+        shift_values[i] = cvmx_helper_qlm_jtag_shift(qlm, 32, 0);
+
+    /* Put new data in our local array */
+    for (l=0; l<num_lanes; l++)
+    {
+        uint64_t new_value = value;
+        int bits;
+        if ((l != lane) && (lane != -1))
+            continue;
+        for (bits = field->start_bit + (num_lanes-1-l)*qlm_jtag_length;
+             bits <= field->stop_bit + (num_lanes-1-l)*qlm_jtag_length;
+             bits++)
+        {
+            if (new_value & 1)
+                shift_values[bits/32] |= 1<<(bits&31);
+            else
+                shift_values[bits/32] &= ~(1<<(bits&31));
+            new_value>>=1;
+        }
+    }
+
+    /* Shift out data and xor with reference */
+    while (bits < total_length)
+    {
+        uint32_t shift = shift_values[bits/32] ^ __cvmx_qlm_jtag_xor_ref[qlm][bits/32];
+        int width = total_length - bits;
+        if (width > 32)
+            width = 32;
+        cvmx_helper_qlm_jtag_shift(qlm, width, shift);
+        bits += 32;
+    }
+
+    /* Update the new data */
+    cvmx_helper_qlm_jtag_update(qlm);
+    /* Always give the QLM 1ms to settle after every update. This may not
+       always be needed, but some of the options make significant
+       electrical changes */
+    cvmx_wait_usec(1000);
+}
+                                                                                
+/**
+ * Errata G-16094: QLM Gen2 Equalizer Default Setting Change.
+ * CN68XX pass 1.x and CN66XX pass 1.x QLM tweak. This function tweaks the
+ * JTAG setting for a QLMs to run better at 5 and 6.25Ghz.
+ */
+void __cvmx_qlm_speed_tweak(void)
+{
+    cvmx_mio_qlmx_cfg_t qlm_cfg;
+    int num_qlms = 0;
+    int qlm;
+
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X))
+        num_qlms = 5;
+    else if (OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_X))
+        num_qlms = 3;
+    else
+        return;
+
+    /* Loop through the QLMs */
+    for (qlm = 0; qlm < num_qlms; qlm++)
+    {
+        /* Read the QLM speed */
+	qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
+
+        /* If the QLM is at 6.25Ghz or 5Ghz then program JTAG */
+        if ((qlm_cfg.s.qlm_spd == 5) || (qlm_cfg.s.qlm_spd == 12) ||
+            (qlm_cfg.s.qlm_spd == 0) || (qlm_cfg.s.qlm_spd == 6) ||
+            (qlm_cfg.s.qlm_spd == 11))
+        {
+            cvmx_qlm_jtag_set(qlm, -1, "rx_cap_gen2", 0x1);
+            cvmx_qlm_jtag_set(qlm, -1, "rx_eq_gen2", 0x8);
+        }
+    }
+}
+
+/**
+ * Errata G-16174: QLM Gen2 PCIe IDLE DAC change.
+ * CN68XX pass 1.x, CN66XX pass 1.x and CN63XX pass 1.0-2.2 QLM tweak.
+ * This function tweaks the JTAG setting for a QLMs for PCIe to run better.
+ */
+void __cvmx_qlm_pcie_idle_dac_tweak(void)
+{
+    int num_qlms = 0;
+    int qlm;
+
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X))
+        num_qlms = 5;
+    else if (OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_X))
+        num_qlms = 3;
+    else if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
+             OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_X))
+        num_qlms = 3;
+    else
+        return;
+
+    /* Loop through the QLMs */
+    for (qlm = 0; qlm < num_qlms; qlm++)
+        cvmx_qlm_jtag_set(qlm, -1, "idle_dac", 0x2);
+}
+
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
+/**
+ * Get the speed (Gbaud) of the QLM in Mhz.
+ *
+ * @param qlm    QLM to examine
+ *
+ * @return Speed in Mhz
+ */
+int cvmx_qlm_get_gbaud_mhz(int qlm)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+    {
+        if (qlm == 2)
+        {
+            cvmx_gmxx_inf_mode_t inf_mode;
+            inf_mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(0));
+            switch (inf_mode.s.speed)
+            {
+                case 0: return 5000;    /* 5     Gbaud */
+                case 1: return 2500;    /* 2.5   Gbaud */
+                case 2: return 2500;    /* 2.5   Gbaud */
+                case 3: return 1250;    /* 1.25  Gbaud */
+                case 4: return 1250;    /* 1.25  Gbaud */
+                case 5: return 6250;    /* 6.25  Gbaud */
+                case 6: return 5000;    /* 5     Gbaud */
+                case 7: return 2500;    /* 2.5   Gbaud */
+                case 8: return 3125;    /* 3.125 Gbaud */
+                case 9: return 2500;    /* 2.5   Gbaud */
+                case 10: return 1250;   /* 1.25  Gbaud */
+                case 11: return 5000;   /* 5     Gbaud */
+                case 12: return 6250;   /* 6.25  Gbaud */
+                case 13: return 3750;   /* 3.75  Gbaud */
+                case 14: return 3125;   /* 3.125 Gbaud */
+                default: return 0;      /* Disabled */
+            }
+        }
+        else
+        {
+            cvmx_sriox_status_reg_t status_reg;
+            status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(qlm));
+            if (status_reg.s.srio)
+            {
+                cvmx_sriomaintx_port_0_ctl2_t sriomaintx_port_0_ctl2;
+                sriomaintx_port_0_ctl2.u32 = cvmx_read_csr(CVMX_SRIOMAINTX_PORT_0_CTL2(qlm));
+                switch (sriomaintx_port_0_ctl2.s.sel_baud)
+                {
+                    case 1: return 1250;    /* 1.25  Gbaud */
+                    case 2: return 2500;    /* 2.5   Gbaud */
+                    case 3: return 3125;    /* 3.125 Gbaud */
+                    case 4: return 5000;    /* 5     Gbaud */
+                    case 5: return 6250;    /* 6.250 Gbaud */
+                    default: return 0;      /* Disabled */
+                }
+            }
+            else
+            {
+                cvmx_pciercx_cfg032_t pciercx_cfg032;
+                pciercx_cfg032.u32 = cvmx_read_csr(CVMX_PCIERCX_CFG032(qlm));
+                switch (pciercx_cfg032.s.ls)
+                {
+                    case 1:
+                        return 2500;
+                    case 2:
+                        return 5000;
+                    case 4:
+                        return 8000;
+                    default:
+                    {
+                        cvmx_mio_rst_boot_t mio_rst_boot;
+                        mio_rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
+                        if ((qlm == 0) && mio_rst_boot.s.qlm0_spd == 0xf)
+                            return 0;
+                        if ((qlm == 1) && mio_rst_boot.s.qlm1_spd == 0xf)
+                            return 0;
+                        return 5000; /* Best guess I can make */
+                    }
+                }
+            }
+        }
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
+    {
+        cvmx_mio_qlmx_cfg_t qlm_cfg;
+
+        qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
+        switch (qlm_cfg.s.qlm_spd)
+        {
+            case 0: return 5000;    /* 5     Gbaud */
+            case 1: return 2500;    /* 2.5   Gbaud */
+            case 2: return 2500;    /* 2.5   Gbaud */
+            case 3: return 1250;    /* 1.25  Gbaud */
+            case 4: return 1250;    /* 1.25  Gbaud */
+            case 5: return 6250;    /* 6.25  Gbaud */
+            case 6: return 5000;    /* 5     Gbaud */
+            case 7: return 2500;    /* 2.5   Gbaud */
+            case 8: return 3125;    /* 3.125 Gbaud */
+            case 9: return 2500;    /* 2.5   Gbaud */
+            case 10: return 1250;   /* 1.25  Gbaud */
+            case 11: return 5000;   /* 5     Gbaud */
+            case 12: return 6250;   /* 6.25  Gbaud */
+            case 13: return 3750;   /* 3.75  Gbaud */
+            case 14: return 3125;   /* 3.125 Gbaud */
+            default: return 0;      /* Disabled */
+        }
+    }
+    return 0;
+}
+#endif
+
+/*
+ * Read QLM and return status based on CN66XX.
+ * @return  Return 1 if QLM is SGMII
+ *                 2 if QLM is XAUI
+ *                 3 if QLM is PCIe gen2 / gen1
+ *                 4 if QLM is SRIO 1x4 short / long
+ *                 5 if QLM is SRIO 2x2 short / long
+ *                 6 if QLM is SRIO 4x1 short / long
+ *                 7 if QLM is PCIe 1x2 gen2 / gen1
+ *                 8 if QLM is PCIe 2x1 gen2 / gen1
+ *                 9 if QLM is ILK
+ *                 10 if QLM is RXAUI
+ *                 -1 otherwise
+ */
+int cvmx_qlm_get_status(int qlm)
+{
+    cvmx_mio_qlmx_cfg_t qlmx_cfg;
+
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+    {
+        qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
+        /* QLM is disabled when QLM SPD is 15. */
+        if (qlmx_cfg.s.qlm_spd == 15)
+            return  -1;
+
+        switch (qlmx_cfg.s.qlm_cfg)
+        {
+            case 0: /* PCIE */
+                return 3;
+            case 1: /* ILK */
+                return 9;
+            case 2: /* SGMII */
+                return 1;
+            case 3: /* XAUI */
+                return 2;
+            case 7: /* RXAUI */
+                return 10;
+            default: return -1;
+        }
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN66XX))
+    {
+        qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
+        /* QLM is disabled when QLM SPD is 15. */
+        if (qlmx_cfg.s.qlm_spd == 15)
+            return  -1;
+
+        switch (qlmx_cfg.s.qlm_cfg)
+        {
+            case 0x9: /* SGMII */
+                return 1;
+            case 0xb: /* XAUI */
+                return 2;
+            case 0x0: /* PCIE gen2 */
+            case 0x8: /* PCIE gen2 (alias) */
+            case 0x2: /* PCIE gen1 */
+            case 0xa: /* PCIE gen1 (alias) */
+                return 3;
+            case 0x1: /* SRIO 1x4 short */
+            case 0x3: /* SRIO 1x4 long */
+                return 4;
+            case 0x4: /* SRIO 2x2 short */
+            case 0x6: /* SRIO 2x2 long */
+                return 5;
+            case 0x5: /* SRIO 4x1 short */
+            case 0x7: /* SRIO 4x1 long */
+                if (!OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_0))
+                    return 6;
+            default:
+                return -1;
+        }
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+    {
+        cvmx_sriox_status_reg_t status_reg;
+        /* For now skip qlm2 */
+        if (qlm == 2)
+        {
+            cvmx_gmxx_inf_mode_t inf_mode;
+            inf_mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(0));
+            if (inf_mode.s.speed == 15) 
+                return -1;
+            else if(inf_mode.s.mode == 0)
+                return 1;
+            else
+                return 2;
+        }
+        status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(qlm));
+        if (status_reg.s.srio)
+            return 4;
+        else
+            return 3;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN61XX))
+    {
+        qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
+        /* QLM is disabled when QLM SPD is 15. */
+        if (qlmx_cfg.s.qlm_spd == 15)
+            return  -1;
+
+        switch(qlm)
+        {
+            case 0:
+                switch (qlmx_cfg.s.qlm_cfg)
+                {
+                    case 0: /* PCIe 1x4 gen2 / gen1 */
+                        return 3;
+                    case 2: /* SGMII */
+                        return 1;
+                    case 3: /* XAUI */
+                        return 2;
+                    default: return -1;
+                }
+                break;
+            case 1:
+                switch (qlmx_cfg.s.qlm_cfg)
+                {
+                    case 0: /* PCIe 1x2 gen2 / gen1 */
+                        return 7;
+                    case 1: /* PCIe 2x1 gen2 / gen1 */
+                        return 8;
+                    default: return -1;
+                }
+                break;
+            case 2:
+                switch (qlmx_cfg.s.qlm_cfg)
+                {
+                    case 2: /* SGMII */
+                        return 1;
+                    case 3: /* XAUI */
+                        return 2;
+                    default: return -1;
+                }
+                break;
+        }
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CNF71XX))
+    {
+        qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
+        /* QLM is disabled when QLM SPD is 15. */
+        if (qlmx_cfg.s.qlm_spd == 15)
+            return  -1;
+
+        switch(qlm)
+        {
+            case 0:
+                if (qlmx_cfg.s.qlm_cfg == 2) /* SGMII */
+                    return 1;
+                break;
+            case 1:
+                switch (qlmx_cfg.s.qlm_cfg)
+                {
+                    case 0: /* PCIe 1x2 gen2 / gen1 */
+                        return 7;
+                    case 1: /* PCIe 2x1 gen2 / gen1 */
+                        return 8;
+                    default: return -1;
+                }
+                break;
+        }
+    }
+    return -1;
+}
diff --git a/sys/contrib/octeon-sdk/cvmx-qlm.h b/sys/contrib/octeon-sdk/cvmx-qlm.h
new file mode 100644
index 0000000..0f024ba
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-qlm.h
@@ -0,0 +1,165 @@
+/***********************license start***************
+ * Copyright (c) 2011  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Helper utilities for qlm.
+ *
+ * <hr>$Revision: 70030 $<hr>
+ */
+
+
+#ifndef __CVMX_QLM_H__
+#define __CVMX_QLM_H__
+
+#include "cvmx.h"
+
+typedef struct
+{
+    const char *name;
+    int stop_bit;
+    int start_bit;
+} __cvmx_qlm_jtag_field_t;
+
+/**
+ * Return the number of QLMs supported by the chip
+ * 
+ * @return  Number of QLMs
+ */
+extern int cvmx_qlm_get_num(void);
+
+/**
+ * Return the qlm number based on the interface
+ *
+ * @param interface  Interface to look up
+ */
+extern int cvmx_qlm_interface(int interface);
+
+/**
+ * Return number of lanes for a given qlm
+ * 
+ * @return  Number of lanes
+ */
+extern int cvmx_qlm_get_lanes(int qlm);
+
+/**
+ * Get the QLM JTAG fields based on Octeon model on the supported chips. 
+ *
+ * @return  qlm_jtag_field_t structure
+ */
+extern const __cvmx_qlm_jtag_field_t *cvmx_qlm_jtag_get_field(void);
+
+/**
+ * Get the QLM JTAG length by going through qlm_jtag_field for each
+ * Octeon model that is supported
+ *
+ * @return return the length.
+ */
+extern int cvmx_qlm_jtag_get_length(void);
+
+/**
+ * Initialize the QLM layer
+ */
+extern void cvmx_qlm_init(void);
+
+/**
+ * Get a field in a QLM JTAG chain
+ *
+ * @param qlm    QLM to get
+ * @param lane   Lane in QLM to get
+ * @param name   String name of field
+ *
+ * @return JTAG field value
+ */
+extern uint64_t cvmx_qlm_jtag_get(int qlm, int lane, const char *name);
+
+/**
+ * Set a field in a QLM JTAG chain
+ *
+ * @param qlm    QLM to set
+ * @param lane   Lane in QLM to set, or -1 for all lanes
+ * @param name   String name of field
+ * @param value  Value of the field
+ */
+extern void cvmx_qlm_jtag_set(int qlm, int lane, const char *name, uint64_t value);
+
+/**
+ * Errata G-16094: QLM Gen2 Equalizer Default Setting Change.
+ * CN68XX pass 1.x and CN66XX pass 1.x QLM tweak. This function tweaks the
+ * JTAG setting for a QLMs to run better at 5 and 6.25Ghz.
+ */
+extern void __cvmx_qlm_speed_tweak(void);
+
+/**
+ * Errata G-16174: QLM Gen2 PCIe IDLE DAC change.
+ * CN68XX pass 1.x, CN66XX pass 1.x and CN63XX pass 1.0-2.2 QLM tweak.
+ * This function tweaks the JTAG setting for a QLMs for PCIe to run better.
+ */
+extern void __cvmx_qlm_pcie_idle_dac_tweak(void);
+
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
+/**
+ * Get the speed (Gbaud) of the QLM in Mhz.
+ *
+ * @param qlm    QLM to examine
+ *
+ * @return Speed in Mhz
+ */
+extern int cvmx_qlm_get_gbaud_mhz(int qlm);
+#endif
+
+/*
+ * Read QLM and return status based on CN66XX.
+ * @return  Return 1 if QLM is SGMII
+ *                 2 if QLM is XAUI
+ *                 3 if QLM is PCIe gen2 / gen1
+ *                 4 if QLM is SRIO 1x4 short / long
+ *                 5 if QLM is SRIO 2x2 short / long
+ *                 6 is reserved
+ *                 7 if QLM is PCIe 1x2 gen2 / gen1
+ *                 8 if QLM is PCIe 2x1 gen2 / gen1
+ *                 9 if QLM is ILK
+ *                 10 if QLM is RXAUI
+ *                 -1 otherwise
+ */
+extern int cvmx_qlm_get_status(int qlm);
+
+#endif /* __CVMX_QLM_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-rad-defs.h b/sys/contrib/octeon-sdk/cvmx-rad-defs.h
index 374fabe..edd5964 100644
--- a/sys/contrib/octeon-sdk/cvmx-rad-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-rad-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,14 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_RAD_TYPEDEFS_H__
-#define __CVMX_RAD_TYPEDEFS_H__
+#ifndef __CVMX_RAD_DEFS_H__
+#define __CVMX_RAD_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_RAD_MEM_DEBUG0 CVMX_RAD_MEM_DEBUG0_FUNC()
 static inline uint64_t CVMX_RAD_MEM_DEBUG0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_MEM_DEBUG0 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070001000ull);
 }
@@ -67,7 +67,7 @@ static inline uint64_t CVMX_RAD_MEM_DEBUG0_FUNC(void)
 #define CVMX_RAD_MEM_DEBUG1 CVMX_RAD_MEM_DEBUG1_FUNC()
 static inline uint64_t CVMX_RAD_MEM_DEBUG1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_MEM_DEBUG1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070001008ull);
 }
@@ -78,7 +78,7 @@ static inline uint64_t CVMX_RAD_MEM_DEBUG1_FUNC(void)
 #define CVMX_RAD_MEM_DEBUG2 CVMX_RAD_MEM_DEBUG2_FUNC()
 static inline uint64_t CVMX_RAD_MEM_DEBUG2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_MEM_DEBUG2 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070001010ull);
 }
@@ -89,7 +89,7 @@ static inline uint64_t CVMX_RAD_MEM_DEBUG2_FUNC(void)
 #define CVMX_RAD_REG_BIST_RESULT CVMX_RAD_REG_BIST_RESULT_FUNC()
 static inline uint64_t CVMX_RAD_REG_BIST_RESULT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_BIST_RESULT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000080ull);
 }
@@ -100,7 +100,7 @@ static inline uint64_t CVMX_RAD_REG_BIST_RESULT_FUNC(void)
 #define CVMX_RAD_REG_CMD_BUF CVMX_RAD_REG_CMD_BUF_FUNC()
 static inline uint64_t CVMX_RAD_REG_CMD_BUF_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_CMD_BUF not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000008ull);
 }
@@ -111,7 +111,7 @@ static inline uint64_t CVMX_RAD_REG_CMD_BUF_FUNC(void)
 #define CVMX_RAD_REG_CTL CVMX_RAD_REG_CTL_FUNC()
 static inline uint64_t CVMX_RAD_REG_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000000ull);
 }
@@ -122,7 +122,7 @@ static inline uint64_t CVMX_RAD_REG_CTL_FUNC(void)
 #define CVMX_RAD_REG_DEBUG0 CVMX_RAD_REG_DEBUG0_FUNC()
 static inline uint64_t CVMX_RAD_REG_DEBUG0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_DEBUG0 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000100ull);
 }
@@ -133,7 +133,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG0_FUNC(void)
 #define CVMX_RAD_REG_DEBUG1 CVMX_RAD_REG_DEBUG1_FUNC()
 static inline uint64_t CVMX_RAD_REG_DEBUG1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_DEBUG1 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000108ull);
 }
@@ -144,7 +144,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG1_FUNC(void)
 #define CVMX_RAD_REG_DEBUG10 CVMX_RAD_REG_DEBUG10_FUNC()
 static inline uint64_t CVMX_RAD_REG_DEBUG10_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_DEBUG10 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000150ull);
 }
@@ -155,7 +155,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG10_FUNC(void)
 #define CVMX_RAD_REG_DEBUG11 CVMX_RAD_REG_DEBUG11_FUNC()
 static inline uint64_t CVMX_RAD_REG_DEBUG11_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_DEBUG11 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000158ull);
 }
@@ -166,7 +166,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG11_FUNC(void)
 #define CVMX_RAD_REG_DEBUG12 CVMX_RAD_REG_DEBUG12_FUNC()
 static inline uint64_t CVMX_RAD_REG_DEBUG12_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_DEBUG12 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000160ull);
 }
@@ -177,7 +177,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG12_FUNC(void)
 #define CVMX_RAD_REG_DEBUG2 CVMX_RAD_REG_DEBUG2_FUNC()
 static inline uint64_t CVMX_RAD_REG_DEBUG2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_DEBUG2 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000110ull);
 }
@@ -188,7 +188,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG2_FUNC(void)
 #define CVMX_RAD_REG_DEBUG3 CVMX_RAD_REG_DEBUG3_FUNC()
 static inline uint64_t CVMX_RAD_REG_DEBUG3_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_DEBUG3 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000118ull);
 }
@@ -199,7 +199,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG3_FUNC(void)
 #define CVMX_RAD_REG_DEBUG4 CVMX_RAD_REG_DEBUG4_FUNC()
 static inline uint64_t CVMX_RAD_REG_DEBUG4_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_DEBUG4 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000120ull);
 }
@@ -210,7 +210,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG4_FUNC(void)
 #define CVMX_RAD_REG_DEBUG5 CVMX_RAD_REG_DEBUG5_FUNC()
 static inline uint64_t CVMX_RAD_REG_DEBUG5_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_DEBUG5 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000128ull);
 }
@@ -221,7 +221,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG5_FUNC(void)
 #define CVMX_RAD_REG_DEBUG6 CVMX_RAD_REG_DEBUG6_FUNC()
 static inline uint64_t CVMX_RAD_REG_DEBUG6_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_DEBUG6 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000130ull);
 }
@@ -232,7 +232,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG6_FUNC(void)
 #define CVMX_RAD_REG_DEBUG7 CVMX_RAD_REG_DEBUG7_FUNC()
 static inline uint64_t CVMX_RAD_REG_DEBUG7_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_DEBUG7 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000138ull);
 }
@@ -243,7 +243,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG7_FUNC(void)
 #define CVMX_RAD_REG_DEBUG8 CVMX_RAD_REG_DEBUG8_FUNC()
 static inline uint64_t CVMX_RAD_REG_DEBUG8_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_DEBUG8 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000140ull);
 }
@@ -254,7 +254,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG8_FUNC(void)
 #define CVMX_RAD_REG_DEBUG9 CVMX_RAD_REG_DEBUG9_FUNC()
 static inline uint64_t CVMX_RAD_REG_DEBUG9_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_DEBUG9 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000148ull);
 }
@@ -265,7 +265,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG9_FUNC(void)
 #define CVMX_RAD_REG_ERROR CVMX_RAD_REG_ERROR_FUNC()
 static inline uint64_t CVMX_RAD_REG_ERROR_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_ERROR not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000088ull);
 }
@@ -276,7 +276,7 @@ static inline uint64_t CVMX_RAD_REG_ERROR_FUNC(void)
 #define CVMX_RAD_REG_INT_MASK CVMX_RAD_REG_INT_MASK_FUNC()
 static inline uint64_t CVMX_RAD_REG_INT_MASK_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_INT_MASK not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000090ull);
 }
@@ -287,7 +287,7 @@ static inline uint64_t CVMX_RAD_REG_INT_MASK_FUNC(void)
 #define CVMX_RAD_REG_POLYNOMIAL CVMX_RAD_REG_POLYNOMIAL_FUNC()
 static inline uint64_t CVMX_RAD_REG_POLYNOMIAL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_POLYNOMIAL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000010ull);
 }
@@ -298,7 +298,7 @@ static inline uint64_t CVMX_RAD_REG_POLYNOMIAL_FUNC(void)
 #define CVMX_RAD_REG_READ_IDX CVMX_RAD_REG_READ_IDX_FUNC()
 static inline uint64_t CVMX_RAD_REG_READ_IDX_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RAD_REG_READ_IDX not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180070000018ull);
 }
@@ -314,12 +314,10 @@ static inline uint64_t CVMX_RAD_REG_READ_IDX_FUNC(void)
  * CSR read operations to this address can be performed.  A read of any entry that has not been
  * previously written is illegal and will result in unpredictable CSR read data.
  */
-union cvmx_rad_mem_debug0
-{
+union cvmx_rad_mem_debug0 {
 	uint64_t u64;
-	struct cvmx_rad_mem_debug0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_mem_debug0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t iword                        : 64; /**< IWord */
 #else
 	uint64_t iword                        : 64;
@@ -329,8 +327,13 @@ union cvmx_rad_mem_debug0
 	struct cvmx_rad_mem_debug0_s          cn52xxp1;
 	struct cvmx_rad_mem_debug0_s          cn56xx;
 	struct cvmx_rad_mem_debug0_s          cn56xxp1;
+	struct cvmx_rad_mem_debug0_s          cn61xx;
 	struct cvmx_rad_mem_debug0_s          cn63xx;
 	struct cvmx_rad_mem_debug0_s          cn63xxp1;
+	struct cvmx_rad_mem_debug0_s          cn66xx;
+	struct cvmx_rad_mem_debug0_s          cn68xx;
+	struct cvmx_rad_mem_debug0_s          cn68xxp1;
+	struct cvmx_rad_mem_debug0_s          cnf71xx;
 };
 typedef union cvmx_rad_mem_debug0 cvmx_rad_mem_debug0_t;
 
@@ -342,12 +345,10 @@ typedef union cvmx_rad_mem_debug0 cvmx_rad_mem_debug0_t;
  * CSR read operations to this address can be performed.  A read of any entry that has not been
  * previously written is illegal and will result in unpredictable CSR read data.
  */
-union cvmx_rad_mem_debug1
-{
+union cvmx_rad_mem_debug1 {
 	uint64_t u64;
-	struct cvmx_rad_mem_debug1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_mem_debug1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t p_dat                        : 64; /**< P data */
 #else
 	uint64_t p_dat                        : 64;
@@ -357,8 +358,13 @@ union cvmx_rad_mem_debug1
 	struct cvmx_rad_mem_debug1_s          cn52xxp1;
 	struct cvmx_rad_mem_debug1_s          cn56xx;
 	struct cvmx_rad_mem_debug1_s          cn56xxp1;
+	struct cvmx_rad_mem_debug1_s          cn61xx;
 	struct cvmx_rad_mem_debug1_s          cn63xx;
 	struct cvmx_rad_mem_debug1_s          cn63xxp1;
+	struct cvmx_rad_mem_debug1_s          cn66xx;
+	struct cvmx_rad_mem_debug1_s          cn68xx;
+	struct cvmx_rad_mem_debug1_s          cn68xxp1;
+	struct cvmx_rad_mem_debug1_s          cnf71xx;
 };
 typedef union cvmx_rad_mem_debug1 cvmx_rad_mem_debug1_t;
 
@@ -370,12 +376,10 @@ typedef union cvmx_rad_mem_debug1 cvmx_rad_mem_debug1_t;
  * CSR read operations to this address can be performed.  A read of any entry that has not been
  * previously written is illegal and will result in unpredictable CSR read data.
  */
-union cvmx_rad_mem_debug2
-{
+union cvmx_rad_mem_debug2 {
 	uint64_t u64;
-	struct cvmx_rad_mem_debug2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_mem_debug2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t q_dat                        : 64; /**< Q data */
 #else
 	uint64_t q_dat                        : 64;
@@ -385,8 +389,13 @@ union cvmx_rad_mem_debug2
 	struct cvmx_rad_mem_debug2_s          cn52xxp1;
 	struct cvmx_rad_mem_debug2_s          cn56xx;
 	struct cvmx_rad_mem_debug2_s          cn56xxp1;
+	struct cvmx_rad_mem_debug2_s          cn61xx;
 	struct cvmx_rad_mem_debug2_s          cn63xx;
 	struct cvmx_rad_mem_debug2_s          cn63xxp1;
+	struct cvmx_rad_mem_debug2_s          cn66xx;
+	struct cvmx_rad_mem_debug2_s          cn68xx;
+	struct cvmx_rad_mem_debug2_s          cn68xxp1;
+	struct cvmx_rad_mem_debug2_s          cnf71xx;
 };
 typedef union cvmx_rad_mem_debug2 cvmx_rad_mem_debug2_t;
 
@@ -397,12 +406,10 @@ typedef union cvmx_rad_mem_debug2 cvmx_rad_mem_debug2_t;
  * Access to the internal BiST results
  * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
  */
-union cvmx_rad_reg_bist_result
-{
+union cvmx_rad_reg_bist_result {
 	uint64_t u64;
-	struct cvmx_rad_reg_bist_result_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_bist_result_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t sta                          : 1;  /**< BiST result of the STA     memories */
 	uint64_t ncb_oub                      : 1;  /**< BiST result of the NCB_OUB memories */
@@ -420,8 +427,13 @@ union cvmx_rad_reg_bist_result
 	struct cvmx_rad_reg_bist_result_s     cn52xxp1;
 	struct cvmx_rad_reg_bist_result_s     cn56xx;
 	struct cvmx_rad_reg_bist_result_s     cn56xxp1;
+	struct cvmx_rad_reg_bist_result_s     cn61xx;
 	struct cvmx_rad_reg_bist_result_s     cn63xx;
 	struct cvmx_rad_reg_bist_result_s     cn63xxp1;
+	struct cvmx_rad_reg_bist_result_s     cn66xx;
+	struct cvmx_rad_reg_bist_result_s     cn68xx;
+	struct cvmx_rad_reg_bist_result_s     cn68xxp1;
+	struct cvmx_rad_reg_bist_result_s     cnf71xx;
 };
 typedef union cvmx_rad_reg_bist_result cvmx_rad_reg_bist_result_t;
 
@@ -434,12 +446,10 @@ typedef union cvmx_rad_reg_bist_result cvmx_rad_reg_bist_result_t;
  * lists to be used when freeing command buffer segments.  The PTR field is overwritten with the next
  * pointer each time that the command buffer segment is exhausted.
  */
-union cvmx_rad_reg_cmd_buf
-{
+union cvmx_rad_reg_cmd_buf {
 	uint64_t u64;
-	struct cvmx_rad_reg_cmd_buf_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_cmd_buf_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_58_63               : 6;
 	uint64_t dwb                          : 9;  /**< Number of DontWriteBacks */
 	uint64_t pool                         : 3;  /**< Free list used to free command buffer segments */
@@ -457,8 +467,13 @@ union cvmx_rad_reg_cmd_buf
 	struct cvmx_rad_reg_cmd_buf_s         cn52xxp1;
 	struct cvmx_rad_reg_cmd_buf_s         cn56xx;
 	struct cvmx_rad_reg_cmd_buf_s         cn56xxp1;
+	struct cvmx_rad_reg_cmd_buf_s         cn61xx;
 	struct cvmx_rad_reg_cmd_buf_s         cn63xx;
 	struct cvmx_rad_reg_cmd_buf_s         cn63xxp1;
+	struct cvmx_rad_reg_cmd_buf_s         cn66xx;
+	struct cvmx_rad_reg_cmd_buf_s         cn68xx;
+	struct cvmx_rad_reg_cmd_buf_s         cn68xxp1;
+	struct cvmx_rad_reg_cmd_buf_s         cnf71xx;
 };
 typedef union cvmx_rad_reg_cmd_buf cvmx_rad_reg_cmd_buf_t;
 
@@ -469,12 +484,10 @@ typedef union cvmx_rad_reg_cmd_buf cvmx_rad_reg_cmd_buf_t;
  * MAX_READ is a throttle to control NCB usage.  Values >8 are illegal.
  *
  */
-union cvmx_rad_reg_ctl
-{
+union cvmx_rad_reg_ctl {
 	uint64_t u64;
-	struct cvmx_rad_reg_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t max_read                     : 4;  /**< Maximum number of outstanding data read commands */
 	uint64_t store_le                     : 1;  /**< Force STORE0 byte write address to little endian */
@@ -490,20 +503,23 @@ union cvmx_rad_reg_ctl
 	struct cvmx_rad_reg_ctl_s             cn52xxp1;
 	struct cvmx_rad_reg_ctl_s             cn56xx;
 	struct cvmx_rad_reg_ctl_s             cn56xxp1;
+	struct cvmx_rad_reg_ctl_s             cn61xx;
 	struct cvmx_rad_reg_ctl_s             cn63xx;
 	struct cvmx_rad_reg_ctl_s             cn63xxp1;
+	struct cvmx_rad_reg_ctl_s             cn66xx;
+	struct cvmx_rad_reg_ctl_s             cn68xx;
+	struct cvmx_rad_reg_ctl_s             cn68xxp1;
+	struct cvmx_rad_reg_ctl_s             cnf71xx;
 };
 typedef union cvmx_rad_reg_ctl cvmx_rad_reg_ctl_t;
 
 /**
  * cvmx_rad_reg_debug0
  */
-union cvmx_rad_reg_debug0
-{
+union cvmx_rad_reg_debug0 {
 	uint64_t u64;
-	struct cvmx_rad_reg_debug0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_debug0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_57_63               : 7;
 	uint64_t loop                         : 25; /**< Loop offset */
 	uint64_t reserved_22_31               : 10;
@@ -531,20 +547,23 @@ union cvmx_rad_reg_debug0
 	struct cvmx_rad_reg_debug0_s          cn52xxp1;
 	struct cvmx_rad_reg_debug0_s          cn56xx;
 	struct cvmx_rad_reg_debug0_s          cn56xxp1;
+	struct cvmx_rad_reg_debug0_s          cn61xx;
 	struct cvmx_rad_reg_debug0_s          cn63xx;
 	struct cvmx_rad_reg_debug0_s          cn63xxp1;
+	struct cvmx_rad_reg_debug0_s          cn66xx;
+	struct cvmx_rad_reg_debug0_s          cn68xx;
+	struct cvmx_rad_reg_debug0_s          cn68xxp1;
+	struct cvmx_rad_reg_debug0_s          cnf71xx;
 };
 typedef union cvmx_rad_reg_debug0 cvmx_rad_reg_debug0_t;
 
 /**
  * cvmx_rad_reg_debug1
  */
-union cvmx_rad_reg_debug1
-{
+union cvmx_rad_reg_debug1 {
 	uint64_t u64;
-	struct cvmx_rad_reg_debug1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_debug1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t cword                        : 64; /**< CWord */
 #else
 	uint64_t cword                        : 64;
@@ -554,20 +573,23 @@ union cvmx_rad_reg_debug1
 	struct cvmx_rad_reg_debug1_s          cn52xxp1;
 	struct cvmx_rad_reg_debug1_s          cn56xx;
 	struct cvmx_rad_reg_debug1_s          cn56xxp1;
+	struct cvmx_rad_reg_debug1_s          cn61xx;
 	struct cvmx_rad_reg_debug1_s          cn63xx;
 	struct cvmx_rad_reg_debug1_s          cn63xxp1;
+	struct cvmx_rad_reg_debug1_s          cn66xx;
+	struct cvmx_rad_reg_debug1_s          cn68xx;
+	struct cvmx_rad_reg_debug1_s          cn68xxp1;
+	struct cvmx_rad_reg_debug1_s          cnf71xx;
 };
 typedef union cvmx_rad_reg_debug1 cvmx_rad_reg_debug1_t;
 
 /**
  * cvmx_rad_reg_debug10
  */
-union cvmx_rad_reg_debug10
-{
+union cvmx_rad_reg_debug10 {
 	uint64_t u64;
-	struct cvmx_rad_reg_debug10_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_debug10_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t flags                        : 8;  /**< OCTL flags */
 	uint64_t size                         : 16; /**< OCTL size (bytes) */
 	uint64_t ptr                          : 40; /**< OCTL pointer */
@@ -581,20 +603,23 @@ union cvmx_rad_reg_debug10
 	struct cvmx_rad_reg_debug10_s         cn52xxp1;
 	struct cvmx_rad_reg_debug10_s         cn56xx;
 	struct cvmx_rad_reg_debug10_s         cn56xxp1;
+	struct cvmx_rad_reg_debug10_s         cn61xx;
 	struct cvmx_rad_reg_debug10_s         cn63xx;
 	struct cvmx_rad_reg_debug10_s         cn63xxp1;
+	struct cvmx_rad_reg_debug10_s         cn66xx;
+	struct cvmx_rad_reg_debug10_s         cn68xx;
+	struct cvmx_rad_reg_debug10_s         cn68xxp1;
+	struct cvmx_rad_reg_debug10_s         cnf71xx;
 };
 typedef union cvmx_rad_reg_debug10 cvmx_rad_reg_debug10_t;
 
 /**
  * cvmx_rad_reg_debug11
  */
-union cvmx_rad_reg_debug11
-{
+union cvmx_rad_reg_debug11 {
 	uint64_t u64;
-	struct cvmx_rad_reg_debug11_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_debug11_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t q                            : 1;  /**< OCTL q flag */
 	uint64_t p                            : 1;  /**< OCTL p flag */
@@ -616,20 +641,23 @@ union cvmx_rad_reg_debug11
 	struct cvmx_rad_reg_debug11_s         cn52xxp1;
 	struct cvmx_rad_reg_debug11_s         cn56xx;
 	struct cvmx_rad_reg_debug11_s         cn56xxp1;
+	struct cvmx_rad_reg_debug11_s         cn61xx;
 	struct cvmx_rad_reg_debug11_s         cn63xx;
 	struct cvmx_rad_reg_debug11_s         cn63xxp1;
+	struct cvmx_rad_reg_debug11_s         cn66xx;
+	struct cvmx_rad_reg_debug11_s         cn68xx;
+	struct cvmx_rad_reg_debug11_s         cn68xxp1;
+	struct cvmx_rad_reg_debug11_s         cnf71xx;
 };
 typedef union cvmx_rad_reg_debug11 cvmx_rad_reg_debug11_t;
 
 /**
  * cvmx_rad_reg_debug12
  */
-union cvmx_rad_reg_debug12
-{
+union cvmx_rad_reg_debug12 {
 	uint64_t u64;
-	struct cvmx_rad_reg_debug12_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_debug12_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_15_63               : 49;
 	uint64_t asserts                      : 15; /**< Various assertion checks */
 #else
@@ -641,20 +669,23 @@ union cvmx_rad_reg_debug12
 	struct cvmx_rad_reg_debug12_s         cn52xxp1;
 	struct cvmx_rad_reg_debug12_s         cn56xx;
 	struct cvmx_rad_reg_debug12_s         cn56xxp1;
+	struct cvmx_rad_reg_debug12_s         cn61xx;
 	struct cvmx_rad_reg_debug12_s         cn63xx;
 	struct cvmx_rad_reg_debug12_s         cn63xxp1;
+	struct cvmx_rad_reg_debug12_s         cn66xx;
+	struct cvmx_rad_reg_debug12_s         cn68xx;
+	struct cvmx_rad_reg_debug12_s         cn68xxp1;
+	struct cvmx_rad_reg_debug12_s         cnf71xx;
 };
 typedef union cvmx_rad_reg_debug12 cvmx_rad_reg_debug12_t;
 
 /**
  * cvmx_rad_reg_debug2
  */
-union cvmx_rad_reg_debug2
-{
+union cvmx_rad_reg_debug2 {
 	uint64_t u64;
-	struct cvmx_rad_reg_debug2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_debug2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t owordp                       : 64; /**< OWordP */
 #else
 	uint64_t owordp                       : 64;
@@ -664,20 +695,23 @@ union cvmx_rad_reg_debug2
 	struct cvmx_rad_reg_debug2_s          cn52xxp1;
 	struct cvmx_rad_reg_debug2_s          cn56xx;
 	struct cvmx_rad_reg_debug2_s          cn56xxp1;
+	struct cvmx_rad_reg_debug2_s          cn61xx;
 	struct cvmx_rad_reg_debug2_s          cn63xx;
 	struct cvmx_rad_reg_debug2_s          cn63xxp1;
+	struct cvmx_rad_reg_debug2_s          cn66xx;
+	struct cvmx_rad_reg_debug2_s          cn68xx;
+	struct cvmx_rad_reg_debug2_s          cn68xxp1;
+	struct cvmx_rad_reg_debug2_s          cnf71xx;
 };
 typedef union cvmx_rad_reg_debug2 cvmx_rad_reg_debug2_t;
 
 /**
  * cvmx_rad_reg_debug3
  */
-union cvmx_rad_reg_debug3
-{
+union cvmx_rad_reg_debug3 {
 	uint64_t u64;
-	struct cvmx_rad_reg_debug3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_debug3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t owordq                       : 64; /**< OWordQ */
 #else
 	uint64_t owordq                       : 64;
@@ -687,20 +721,23 @@ union cvmx_rad_reg_debug3
 	struct cvmx_rad_reg_debug3_s          cn52xxp1;
 	struct cvmx_rad_reg_debug3_s          cn56xx;
 	struct cvmx_rad_reg_debug3_s          cn56xxp1;
+	struct cvmx_rad_reg_debug3_s          cn61xx;
 	struct cvmx_rad_reg_debug3_s          cn63xx;
 	struct cvmx_rad_reg_debug3_s          cn63xxp1;
+	struct cvmx_rad_reg_debug3_s          cn66xx;
+	struct cvmx_rad_reg_debug3_s          cn68xx;
+	struct cvmx_rad_reg_debug3_s          cn68xxp1;
+	struct cvmx_rad_reg_debug3_s          cnf71xx;
 };
 typedef union cvmx_rad_reg_debug3 cvmx_rad_reg_debug3_t;
 
 /**
  * cvmx_rad_reg_debug4
  */
-union cvmx_rad_reg_debug4
-{
+union cvmx_rad_reg_debug4 {
 	uint64_t u64;
-	struct cvmx_rad_reg_debug4_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_debug4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rword                        : 64; /**< RWord */
 #else
 	uint64_t rword                        : 64;
@@ -710,20 +747,23 @@ union cvmx_rad_reg_debug4
 	struct cvmx_rad_reg_debug4_s          cn52xxp1;
 	struct cvmx_rad_reg_debug4_s          cn56xx;
 	struct cvmx_rad_reg_debug4_s          cn56xxp1;
+	struct cvmx_rad_reg_debug4_s          cn61xx;
 	struct cvmx_rad_reg_debug4_s          cn63xx;
 	struct cvmx_rad_reg_debug4_s          cn63xxp1;
+	struct cvmx_rad_reg_debug4_s          cn66xx;
+	struct cvmx_rad_reg_debug4_s          cn68xx;
+	struct cvmx_rad_reg_debug4_s          cn68xxp1;
+	struct cvmx_rad_reg_debug4_s          cnf71xx;
 };
 typedef union cvmx_rad_reg_debug4 cvmx_rad_reg_debug4_t;
 
 /**
  * cvmx_rad_reg_debug5
  */
-union cvmx_rad_reg_debug5
-{
+union cvmx_rad_reg_debug5 {
 	uint64_t u64;
-	struct cvmx_rad_reg_debug5_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_debug5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_53_63               : 11;
 	uint64_t niropc7                      : 3;  /**< NCBI ropc (stage7 grant) */
 	uint64_t nirque7                      : 2;  /**< NCBI rque (stage7 grant) */
@@ -767,20 +807,23 @@ union cvmx_rad_reg_debug5
 	struct cvmx_rad_reg_debug5_s          cn52xxp1;
 	struct cvmx_rad_reg_debug5_s          cn56xx;
 	struct cvmx_rad_reg_debug5_s          cn56xxp1;
+	struct cvmx_rad_reg_debug5_s          cn61xx;
 	struct cvmx_rad_reg_debug5_s          cn63xx;
 	struct cvmx_rad_reg_debug5_s          cn63xxp1;
+	struct cvmx_rad_reg_debug5_s          cn66xx;
+	struct cvmx_rad_reg_debug5_s          cn68xx;
+	struct cvmx_rad_reg_debug5_s          cn68xxp1;
+	struct cvmx_rad_reg_debug5_s          cnf71xx;
 };
 typedef union cvmx_rad_reg_debug5 cvmx_rad_reg_debug5_t;
 
 /**
  * cvmx_rad_reg_debug6
  */
-union cvmx_rad_reg_debug6
-{
+union cvmx_rad_reg_debug6 {
 	uint64_t u64;
-	struct cvmx_rad_reg_debug6_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_debug6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t cnt                          : 8;  /**< CCTL count[7:0] (bytes) */
 	uint64_t size                         : 16; /**< CCTL size (bytes) */
 	uint64_t ptr                          : 40; /**< CCTL pointer */
@@ -794,20 +837,23 @@ union cvmx_rad_reg_debug6
 	struct cvmx_rad_reg_debug6_s          cn52xxp1;
 	struct cvmx_rad_reg_debug6_s          cn56xx;
 	struct cvmx_rad_reg_debug6_s          cn56xxp1;
+	struct cvmx_rad_reg_debug6_s          cn61xx;
 	struct cvmx_rad_reg_debug6_s          cn63xx;
 	struct cvmx_rad_reg_debug6_s          cn63xxp1;
+	struct cvmx_rad_reg_debug6_s          cn66xx;
+	struct cvmx_rad_reg_debug6_s          cn68xx;
+	struct cvmx_rad_reg_debug6_s          cn68xxp1;
+	struct cvmx_rad_reg_debug6_s          cnf71xx;
 };
 typedef union cvmx_rad_reg_debug6 cvmx_rad_reg_debug6_t;
 
 /**
  * cvmx_rad_reg_debug7
  */
-union cvmx_rad_reg_debug7
-{
+union cvmx_rad_reg_debug7 {
 	uint64_t u64;
-	struct cvmx_rad_reg_debug7_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_debug7_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_15_63               : 49;
 	uint64_t cnt                          : 15; /**< CCTL count[22:8] (bytes) */
 #else
@@ -819,20 +865,23 @@ union cvmx_rad_reg_debug7
 	struct cvmx_rad_reg_debug7_s          cn52xxp1;
 	struct cvmx_rad_reg_debug7_s          cn56xx;
 	struct cvmx_rad_reg_debug7_s          cn56xxp1;
+	struct cvmx_rad_reg_debug7_s          cn61xx;
 	struct cvmx_rad_reg_debug7_s          cn63xx;
 	struct cvmx_rad_reg_debug7_s          cn63xxp1;
+	struct cvmx_rad_reg_debug7_s          cn66xx;
+	struct cvmx_rad_reg_debug7_s          cn68xx;
+	struct cvmx_rad_reg_debug7_s          cn68xxp1;
+	struct cvmx_rad_reg_debug7_s          cnf71xx;
 };
 typedef union cvmx_rad_reg_debug7 cvmx_rad_reg_debug7_t;
 
 /**
  * cvmx_rad_reg_debug8
  */
-union cvmx_rad_reg_debug8
-{
+union cvmx_rad_reg_debug8 {
 	uint64_t u64;
-	struct cvmx_rad_reg_debug8_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_debug8_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t flags                        : 8;  /**< ICTL flags */
 	uint64_t size                         : 16; /**< ICTL size (bytes) */
 	uint64_t ptr                          : 40; /**< ICTL pointer */
@@ -846,20 +895,23 @@ union cvmx_rad_reg_debug8
 	struct cvmx_rad_reg_debug8_s          cn52xxp1;
 	struct cvmx_rad_reg_debug8_s          cn56xx;
 	struct cvmx_rad_reg_debug8_s          cn56xxp1;
+	struct cvmx_rad_reg_debug8_s          cn61xx;
 	struct cvmx_rad_reg_debug8_s          cn63xx;
 	struct cvmx_rad_reg_debug8_s          cn63xxp1;
+	struct cvmx_rad_reg_debug8_s          cn66xx;
+	struct cvmx_rad_reg_debug8_s          cn68xx;
+	struct cvmx_rad_reg_debug8_s          cn68xxp1;
+	struct cvmx_rad_reg_debug8_s          cnf71xx;
 };
 typedef union cvmx_rad_reg_debug8 cvmx_rad_reg_debug8_t;
 
 /**
  * cvmx_rad_reg_debug9
  */
-union cvmx_rad_reg_debug9
-{
+union cvmx_rad_reg_debug9 {
 	uint64_t u64;
-	struct cvmx_rad_reg_debug9_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_debug9_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t eod                          : 1;  /**< ICTL eod flag */
 	uint64_t ini                          : 1;  /**< ICTL init flag */
@@ -881,20 +933,23 @@ union cvmx_rad_reg_debug9
 	struct cvmx_rad_reg_debug9_s          cn52xxp1;
 	struct cvmx_rad_reg_debug9_s          cn56xx;
 	struct cvmx_rad_reg_debug9_s          cn56xxp1;
+	struct cvmx_rad_reg_debug9_s          cn61xx;
 	struct cvmx_rad_reg_debug9_s          cn63xx;
 	struct cvmx_rad_reg_debug9_s          cn63xxp1;
+	struct cvmx_rad_reg_debug9_s          cn66xx;
+	struct cvmx_rad_reg_debug9_s          cn68xx;
+	struct cvmx_rad_reg_debug9_s          cn68xxp1;
+	struct cvmx_rad_reg_debug9_s          cnf71xx;
 };
 typedef union cvmx_rad_reg_debug9 cvmx_rad_reg_debug9_t;
 
 /**
  * cvmx_rad_reg_error
  */
-union cvmx_rad_reg_error
-{
+union cvmx_rad_reg_error {
 	uint64_t u64;
-	struct cvmx_rad_reg_error_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_error_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t doorbell                     : 1;  /**< A doorbell count has overflowed */
 #else
@@ -906,8 +961,13 @@ union cvmx_rad_reg_error
 	struct cvmx_rad_reg_error_s           cn52xxp1;
 	struct cvmx_rad_reg_error_s           cn56xx;
 	struct cvmx_rad_reg_error_s           cn56xxp1;
+	struct cvmx_rad_reg_error_s           cn61xx;
 	struct cvmx_rad_reg_error_s           cn63xx;
 	struct cvmx_rad_reg_error_s           cn63xxp1;
+	struct cvmx_rad_reg_error_s           cn66xx;
+	struct cvmx_rad_reg_error_s           cn68xx;
+	struct cvmx_rad_reg_error_s           cn68xxp1;
+	struct cvmx_rad_reg_error_s           cnf71xx;
 };
 typedef union cvmx_rad_reg_error cvmx_rad_reg_error_t;
 
@@ -918,12 +978,10 @@ typedef union cvmx_rad_reg_error cvmx_rad_reg_error_t;
  * When a mask bit is set, the corresponding interrupt is enabled.
  *
  */
-union cvmx_rad_reg_int_mask
-{
+union cvmx_rad_reg_int_mask {
 	uint64_t u64;
-	struct cvmx_rad_reg_int_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_int_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t doorbell                     : 1;  /**< Bit mask corresponding to RAD_REG_ERROR[0] above */
 #else
@@ -935,8 +993,13 @@ union cvmx_rad_reg_int_mask
 	struct cvmx_rad_reg_int_mask_s        cn52xxp1;
 	struct cvmx_rad_reg_int_mask_s        cn56xx;
 	struct cvmx_rad_reg_int_mask_s        cn56xxp1;
+	struct cvmx_rad_reg_int_mask_s        cn61xx;
 	struct cvmx_rad_reg_int_mask_s        cn63xx;
 	struct cvmx_rad_reg_int_mask_s        cn63xxp1;
+	struct cvmx_rad_reg_int_mask_s        cn66xx;
+	struct cvmx_rad_reg_int_mask_s        cn68xx;
+	struct cvmx_rad_reg_int_mask_s        cn68xxp1;
+	struct cvmx_rad_reg_int_mask_s        cnf71xx;
 };
 typedef union cvmx_rad_reg_int_mask cvmx_rad_reg_int_mask_t;
 
@@ -947,12 +1010,10 @@ typedef union cvmx_rad_reg_int_mask cvmx_rad_reg_int_mask_t;
  * The polynomial is x^8 + C7*x^7 + C6*x^6 + C5*x^5 + C4*x^4 + C3*x^3 + C2*x^2 + C1*x^1 + C0.
  *
  */
-union cvmx_rad_reg_polynomial
-{
+union cvmx_rad_reg_polynomial {
 	uint64_t u64;
-	struct cvmx_rad_reg_polynomial_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_polynomial_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t coeffs                       : 8;  /**< coefficients of GF(2^8) irreducible polynomial */
 #else
@@ -964,8 +1025,13 @@ union cvmx_rad_reg_polynomial
 	struct cvmx_rad_reg_polynomial_s      cn52xxp1;
 	struct cvmx_rad_reg_polynomial_s      cn56xx;
 	struct cvmx_rad_reg_polynomial_s      cn56xxp1;
+	struct cvmx_rad_reg_polynomial_s      cn61xx;
 	struct cvmx_rad_reg_polynomial_s      cn63xx;
 	struct cvmx_rad_reg_polynomial_s      cn63xxp1;
+	struct cvmx_rad_reg_polynomial_s      cn66xx;
+	struct cvmx_rad_reg_polynomial_s      cn68xx;
+	struct cvmx_rad_reg_polynomial_s      cn68xxp1;
+	struct cvmx_rad_reg_polynomial_s      cnf71xx;
 };
 typedef union cvmx_rad_reg_polynomial cvmx_rad_reg_polynomial_t;
 
@@ -979,12 +1045,10 @@ typedef union cvmx_rad_reg_polynomial cvmx_rad_reg_polynomial_t;
  * The intended use is to initially write this CSR such that IDX=0 and INC=1.  Then, the entire
  * contents of a CSR memory can be read with consecutive CSR read commands.
  */
-union cvmx_rad_reg_read_idx
-{
+union cvmx_rad_reg_read_idx {
 	uint64_t u64;
-	struct cvmx_rad_reg_read_idx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rad_reg_read_idx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t inc                          : 16; /**< Increment to add to current index for next index */
 	uint64_t index                        : 16; /**< Index to use for next memory CSR read */
@@ -998,8 +1062,13 @@ union cvmx_rad_reg_read_idx
 	struct cvmx_rad_reg_read_idx_s        cn52xxp1;
 	struct cvmx_rad_reg_read_idx_s        cn56xx;
 	struct cvmx_rad_reg_read_idx_s        cn56xxp1;
+	struct cvmx_rad_reg_read_idx_s        cn61xx;
 	struct cvmx_rad_reg_read_idx_s        cn63xx;
 	struct cvmx_rad_reg_read_idx_s        cn63xxp1;
+	struct cvmx_rad_reg_read_idx_s        cn66xx;
+	struct cvmx_rad_reg_read_idx_s        cn68xx;
+	struct cvmx_rad_reg_read_idx_s        cn68xxp1;
+	struct cvmx_rad_reg_read_idx_s        cnf71xx;
 };
 typedef union cvmx_rad_reg_read_idx cvmx_rad_reg_read_idx_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-raid.c b/sys/contrib/octeon-sdk/cvmx-raid.c
index 07dd194..2e000f5 100644
--- a/sys/contrib/octeon-sdk/cvmx-raid.c
+++ b/sys/contrib/octeon-sdk/cvmx-raid.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,13 +48,21 @@
  *
  * Interface to RAID block. This is not available on all chips.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-cmd-queue.h>
+#include <asm/octeon/cvmx-raid.h>
+#else
 #include "executive-config.h"
 #include "cvmx-config.h"
 #include "cvmx.h"
 #include "cvmx-cmd-queue.h"
 #include "cvmx-raid.h"
+#endif
 
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
 
@@ -86,7 +94,9 @@ int cvmx_raid_initialize(cvmx_rad_reg_polynomial_t polynomial)
     cvmx_write_csr(CVMX_RAD_REG_CMD_BUF, rad_reg_cmd_buf.u64);
     return 0;
 }
-
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_raid_initialize);
+#endif
 
 /**
  * Shutdown the RAID block. RAID must be idle when
@@ -113,7 +123,9 @@ int cvmx_raid_shutdown(void)
     cvmx_write_csr(CVMX_RAD_REG_CMD_BUF, 0);
     return 0;
 }
-
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_raid_shutdown);
+#endif
 
 /**
  * Submit a command to the RAID block
@@ -130,5 +142,7 @@ int cvmx_raid_submit(int num_words, cvmx_raid_word_t words[])
         cvmx_write_csr(CVMX_ADDR_DID(CVMX_FULL_DID(14, 0)), num_words);
     return result;
 }
-
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_raid_submit);
+#endif
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-raid.h b/sys/contrib/octeon-sdk/cvmx-raid.h
index 48682e8..63da6b9 100644
--- a/sys/contrib/octeon-sdk/cvmx-raid.h
+++ b/sys/contrib/octeon-sdk/cvmx-raid.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,12 +48,16 @@
  *
  * Interface to RAID block. This is not available on all chips.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_RAID_H__
 #define __CVMX_RAID_H__
 
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx-rad-defs.h>
+#endif
+
 #ifdef	__cplusplus
 extern "C" {
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-resources.config b/sys/contrib/octeon-sdk/cvmx-resources.config
new file mode 100644
index 0000000..772e17d
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-resources.config
@@ -0,0 +1,197 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights 
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.  
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries. 
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+
+
+
+/*
+ * File version info: $Id: cvmx-resources.config 70030 2012-02-16 04:23:43Z cchavva $
+ *
+ */
+#ifndef __CVMX_RESOURCES_CONFIG__
+#define __CVMX_RESOURCES_CONFIG__
+
+
+#if (CVMX_HELPER_FIRST_MBUFF_SKIP > 256)
+#error CVMX_HELPER_FIRST_MBUFF_SKIP is greater than the maximum of 256
+#endif
+
+#if (CVMX_HELPER_NOT_FIRST_MBUFF_SKIP > 256)
+#error CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is greater than the maximum of 256
+#endif
+
+
+/* Content below this point is only used by the cvmx-config tool, and is
+** not used by any C files as CAVIUM_COMPONENT_REQUIREMENT is never
+defined.
+*/
+ #ifdef CAVIUM_COMPONENT_REQUIREMENT
+    /* Define the number of LLM ports (interfaces), can be 1 or 2 */
+    cvmxconfig
+    {
+    	#if CVMX_LLM_CONFIG_NUM_PORTS == 2
+            define CVMX_LLM_NUM_PORTS value = 2;
+	#else
+            define CVMX_LLM_NUM_PORTS value = 1;
+	#endif
+    }
+    /* Control the setting of Null pointer detection, default to enabled */
+    cvmxconfig {
+    	#ifdef CVMX_CONFIG_NULL_POINTER_PROTECT
+            define CVMX_NULL_POINTER_PROTECT value = CVMX_CONFIG_NULL_POINTER_PROTECT;
+	#else
+            define CVMX_NULL_POINTER_PROTECT value = 1;
+	#endif
+    }
+    /* Control Debug prints, default to enabled */
+    cvmxconfig {
+    	#ifdef CVMX_CONFIG_ENABLE_DEBUG_PRINTS
+            define CVMX_ENABLE_DEBUG_PRINTS value = CVMX_CONFIG_ENABLE_DEBUG_PRINTS;
+	#else
+            define CVMX_ENABLE_DEBUG_PRINTS value = 1;
+	#endif
+    }
+
+    /* Define CVMX_ENABLE_DFA_FUNCTIONS to allocate resources for the DFA functions */
+    #ifdef CVMX_ENABLE_DFA_FUNCTIONS
+        cvmxconfig
+        {
+        	fpa CVMX_FPA_DFA_POOL
+                    size        = 2
+                    protected   = 1
+                    description = "DFA command buffers";
+        	fau CVMX_FAU_DFA_STATE
+                    size        = 8
+                    count       = 1
+                    description = "FAU registers for the state of the DFA command queue";
+        }
+    #endif
+
+    /* Define CVMX_ENABLE_PKO_FUNCTIONS to allocate resources for the PKO functions */
+    #ifdef CVMX_ENABLE_PKO_FUNCTIONS
+        cvmxconfig
+        {
+		define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0
+		    value       = CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE0
+		    description = "PKO queues per port for interface 0 (ports 0-15)";
+		define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1
+		    value       = CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE1
+		    description = "PKO queues per port for interface 1 (ports 16-31)";
+		define CVMX_PKO_QUEUES_PER_PORT_INTERFACE2
+		    value       = CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE2
+		    description = "PKO queues per port for interface 2";
+		define CVMX_PKO_QUEUES_PER_PORT_INTERFACE3
+		    value       = CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE3
+		    description = "PKO queues per port for interface 3";
+		define CVMX_PKO_QUEUES_PER_PORT_INTERFACE4
+		    value       = CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE4
+		    description = "PKO queues per port for interface 4";
+                define CVMX_PKO_MAX_PORTS_INTERFACE0
+                    value       = CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
+                    description = "Limit on the number of PKO ports enabled for interface 0";
+                define CVMX_PKO_MAX_PORTS_INTERFACE1
+                    value       = CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
+                    description = "Limit on the number of PKO ports enabled for interface 1";
+		define CVMX_PKO_QUEUES_PER_PORT_PCI
+		    value       = 1
+		    description = "PKO queues per port for PCI (ports 32-35)";
+		define CVMX_PKO_QUEUES_PER_PORT_LOOP
+		    value       = 1
+		    description = "PKO queues per port for Loop devices (ports 36-39)";
+		/* We use two queues per port for SRIO0. Having two queues per
+		    port with two ports gives us four queues, one for each mailbox */
+		define CVMX_PKO_QUEUES_PER_PORT_SRIO0
+		    value       = 2
+		    description = "PKO queues per port for SRIO0 devices (ports 40-41)";
+		/* We use two queues per port for SRIO1. Having two queues per
+		    port with two ports gives us four queues, one for each mailbox */
+		define CVMX_PKO_QUEUES_PER_PORT_SRIO1
+		    value       = 2
+		    description = "PKO queues per port for SRIO1 devices (ports 42-43)";
+                /* Set the IPD cache mode, select from cvmx_ipd_mode_t. */
+                define CVMX_IPD_DRAM_MODE
+                    value       = CVMX_HELPER_IPD_DRAM_MODE
+                    description	= "set the IPD cache mode to CVMX_IPD_OPC_MODE_STT";
+        	fpa CVMX_FPA_PACKET_POOL
+                    pool        = 0
+                    size        = 16
+                    priority    = 1
+                    protected   = 1
+                    description = "Packet buffers";
+        	fpa CVMX_FPA_OUTPUT_BUFFER_POOL
+                    size        = 8
+                    protected   = 1
+                    description = "PKO queue command buffers";
+        	scratch CVMX_SCR_SCRATCH
+                    size        = 8
+                    iobdma      = true
+                    permanent   = false
+                    description = "Generic scratch iobdma area";
+        }
+    #endif
+
+    /* Define CVMX_ENABLE_HELPER_FUNCTIONS to allocate resources for the helper functions */
+    #ifdef CVMX_ENABLE_HELPER_FUNCTIONS
+        cvmxconfig
+        {
+        	fpa CVMX_FPA_WQE_POOL
+                    size        = 1
+                    priority    = 1
+                    protected   = 1
+                    description = "Work queue entrys";
+        }
+    #endif
+
+    /* Define CVMX_ENABLE_TIMER_FUNCTIONS to allocate resources for the timer functions */
+    #ifdef CVMX_ENABLE_TIMER_FUNCTIONS
+        cvmxconfig
+        {
+        	fpa CVMX_FPA_TIMER_POOL
+                    size        = 8
+                    protected   = 1
+                    description = "TIM command buffers";
+        }
+    #endif
+
+#endif
+
+
+#endif  /* __CVMX_RESOURCES_CONFIG__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-rng.h b/sys/contrib/octeon-sdk/cvmx-rng.h
index 8ef128b..4b791b3 100644
--- a/sys/contrib/octeon-sdk/cvmx-rng.h
+++ b/sys/contrib/octeon-sdk/cvmx-rng.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Function and structure definitions for random number generator hardware
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 
@@ -149,6 +149,7 @@ static inline int cvmx_rng_request_random_async(uint64_t scr_addr, uint64_t num_
     if (num_bytes & 0x7 || scr_addr & 0x7)
         return(1);
 
+    data.u64 = 0;
     /* scr_addr must be 8 byte aligned */
     data.s.scraddr = scr_addr >> 3;
     data.s.len = num_bytes >> 3;
diff --git a/sys/contrib/octeon-sdk/cvmx-rnm-defs.h b/sys/contrib/octeon-sdk/cvmx-rnm-defs.h
index f9eefbb..5f96a95 100644
--- a/sys/contrib/octeon-sdk/cvmx-rnm-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-rnm-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_RNM_TYPEDEFS_H__
-#define __CVMX_RNM_TYPEDEFS_H__
+#ifndef __CVMX_RNM_DEFS_H__
+#define __CVMX_RNM_DEFS_H__
 
 #define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull))
 #define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull))
@@ -58,7 +58,7 @@
 #define CVMX_RNM_EER_DBG CVMX_RNM_EER_DBG_FUNC()
 static inline uint64_t CVMX_RNM_EER_DBG_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RNM_EER_DBG not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180040000018ull);
 }
@@ -69,7 +69,7 @@ static inline uint64_t CVMX_RNM_EER_DBG_FUNC(void)
 #define CVMX_RNM_EER_KEY CVMX_RNM_EER_KEY_FUNC()
 static inline uint64_t CVMX_RNM_EER_KEY_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RNM_EER_KEY not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180040000010ull);
 }
@@ -80,7 +80,7 @@ static inline uint64_t CVMX_RNM_EER_KEY_FUNC(void)
 #define CVMX_RNM_SERIAL_NUM CVMX_RNM_SERIAL_NUM_FUNC()
 static inline uint64_t CVMX_RNM_SERIAL_NUM_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_RNM_SERIAL_NUM not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180040000020ull);
 }
@@ -95,12 +95,10 @@ static inline uint64_t CVMX_RNM_SERIAL_NUM_FUNC(void)
  *
  * The RNM's Memory Bist Status register.
  */
-union cvmx_rnm_bist_status
-{
+union cvmx_rnm_bist_status {
 	uint64_t u64;
-	struct cvmx_rnm_bist_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rnm_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t rrc                          : 1;  /**< Status of RRC block bist. */
 	uint64_t mem                          : 1;  /**< Status of MEM block bist. */
@@ -121,8 +119,13 @@ union cvmx_rnm_bist_status
 	struct cvmx_rnm_bist_status_s         cn56xxp1;
 	struct cvmx_rnm_bist_status_s         cn58xx;
 	struct cvmx_rnm_bist_status_s         cn58xxp1;
+	struct cvmx_rnm_bist_status_s         cn61xx;
 	struct cvmx_rnm_bist_status_s         cn63xx;
 	struct cvmx_rnm_bist_status_s         cn63xxp1;
+	struct cvmx_rnm_bist_status_s         cn66xx;
+	struct cvmx_rnm_bist_status_s         cn68xx;
+	struct cvmx_rnm_bist_status_s         cn68xxp1;
+	struct cvmx_rnm_bist_status_s         cnf71xx;
 };
 typedef union cvmx_rnm_bist_status cvmx_rnm_bist_status_t;
 
@@ -133,13 +136,12 @@ typedef union cvmx_rnm_bist_status cvmx_rnm_bist_status_t;
  *
  * The RNM's interrupt enable register.
  */
-union cvmx_rnm_ctl_status
-{
+union cvmx_rnm_ctl_status {
 	uint64_t u64;
-	struct cvmx_rnm_ctl_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_11_63               : 53;
+	struct cvmx_rnm_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_12_63               : 52;
+	uint64_t dis_mak                      : 1;  /**< Disable use of Master AES KEY */
 	uint64_t eer_lck                      : 1;  /**< Encryption enable register locked */
 	uint64_t eer_val                      : 1;  /**< Dormant encryption key match */
 	uint64_t ent_sel                      : 4;  /**< ? */
@@ -158,12 +160,12 @@ union cvmx_rnm_ctl_status
 	uint64_t ent_sel                      : 4;
 	uint64_t eer_val                      : 1;
 	uint64_t eer_lck                      : 1;
-	uint64_t reserved_11_63               : 53;
+	uint64_t dis_mak                      : 1;
+	uint64_t reserved_12_63               : 52;
 #endif
 	} s;
-	struct cvmx_rnm_ctl_status_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rnm_ctl_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t rng_rst                      : 1;  /**< Reset RNG as core reset. */
 	uint64_t rnm_rst                      : 1;  /**< Reset the RNM as core reset except for register
@@ -181,9 +183,8 @@ union cvmx_rnm_ctl_status
 	struct cvmx_rnm_ctl_status_cn30xx     cn31xx;
 	struct cvmx_rnm_ctl_status_cn30xx     cn38xx;
 	struct cvmx_rnm_ctl_status_cn30xx     cn38xxp2;
-	struct cvmx_rnm_ctl_status_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rnm_ctl_status_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t ent_sel                      : 4;  /**< ? */
 	uint64_t exp_ent                      : 1;  /**< Exported entropy enable for random number generator */
@@ -208,8 +209,36 @@ union cvmx_rnm_ctl_status
 	struct cvmx_rnm_ctl_status_cn50xx     cn56xxp1;
 	struct cvmx_rnm_ctl_status_cn50xx     cn58xx;
 	struct cvmx_rnm_ctl_status_cn50xx     cn58xxp1;
-	struct cvmx_rnm_ctl_status_s          cn63xx;
-	struct cvmx_rnm_ctl_status_s          cn63xxp1;
+	struct cvmx_rnm_ctl_status_s          cn61xx;
+	struct cvmx_rnm_ctl_status_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_11_63               : 53;
+	uint64_t eer_lck                      : 1;  /**< Encryption enable register locked */
+	uint64_t eer_val                      : 1;  /**< Dormant encryption key match */
+	uint64_t ent_sel                      : 4;  /**< ? */
+	uint64_t exp_ent                      : 1;  /**< Exported entropy enable for random number generator */
+	uint64_t rng_rst                      : 1;  /**< Reset RNG as core reset. */
+	uint64_t rnm_rst                      : 1;  /**< Reset the RNM as core reset except for register
+                                                         logic. */
+	uint64_t rng_en                       : 1;  /**< Enable the output of the RNG. */
+	uint64_t ent_en                       : 1;  /**< Entropy enable for random number generator. */
+#else
+	uint64_t ent_en                       : 1;
+	uint64_t rng_en                       : 1;
+	uint64_t rnm_rst                      : 1;
+	uint64_t rng_rst                      : 1;
+	uint64_t exp_ent                      : 1;
+	uint64_t ent_sel                      : 4;
+	uint64_t eer_val                      : 1;
+	uint64_t eer_lck                      : 1;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} cn63xx;
+	struct cvmx_rnm_ctl_status_cn63xx     cn63xxp1;
+	struct cvmx_rnm_ctl_status_s          cn66xx;
+	struct cvmx_rnm_ctl_status_cn63xx     cn68xx;
+	struct cvmx_rnm_ctl_status_cn63xx     cn68xxp1;
+	struct cvmx_rnm_ctl_status_s          cnf71xx;
 };
 typedef union cvmx_rnm_ctl_status cvmx_rnm_ctl_status_t;
 
@@ -220,19 +249,22 @@ typedef union cvmx_rnm_ctl_status cvmx_rnm_ctl_status_t;
  *
  * The RNM's Encryption enable debug register
  */
-union cvmx_rnm_eer_dbg
-{
+union cvmx_rnm_eer_dbg {
 	uint64_t u64;
-	struct cvmx_rnm_eer_dbg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rnm_eer_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t dat                          : 64; /**< Dormant encryption debug info. */
 #else
 	uint64_t dat                          : 64;
 #endif
 	} s;
+	struct cvmx_rnm_eer_dbg_s             cn61xx;
 	struct cvmx_rnm_eer_dbg_s             cn63xx;
 	struct cvmx_rnm_eer_dbg_s             cn63xxp1;
+	struct cvmx_rnm_eer_dbg_s             cn66xx;
+	struct cvmx_rnm_eer_dbg_s             cn68xx;
+	struct cvmx_rnm_eer_dbg_s             cn68xxp1;
+	struct cvmx_rnm_eer_dbg_s             cnf71xx;
 };
 typedef union cvmx_rnm_eer_dbg cvmx_rnm_eer_dbg_t;
 
@@ -243,12 +275,10 @@ typedef union cvmx_rnm_eer_dbg cvmx_rnm_eer_dbg_t;
  *
  * The RNM's Encryption enable register
  */
-union cvmx_rnm_eer_key
-{
+union cvmx_rnm_eer_key {
 	uint64_t u64;
-	struct cvmx_rnm_eer_key_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rnm_eer_key_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t key                          : 64; /**< Dormant encryption key.  If dormant crypto is fuse
                                                          enabled, crypto can be enable by writing this
                                                          register with the correct key. */
@@ -256,8 +286,13 @@ union cvmx_rnm_eer_key
 	uint64_t key                          : 64;
 #endif
 	} s;
+	struct cvmx_rnm_eer_key_s             cn61xx;
 	struct cvmx_rnm_eer_key_s             cn63xx;
 	struct cvmx_rnm_eer_key_s             cn63xxp1;
+	struct cvmx_rnm_eer_key_s             cn66xx;
+	struct cvmx_rnm_eer_key_s             cn68xx;
+	struct cvmx_rnm_eer_key_s             cn68xxp1;
+	struct cvmx_rnm_eer_key_s             cnf71xx;
 };
 typedef union cvmx_rnm_eer_key cvmx_rnm_eer_key_t;
 
@@ -272,18 +307,21 @@ typedef union cvmx_rnm_eer_key cvmx_rnm_eer_key_t;
  * Added RNM_SERIAL_NUM in pass 2.0
  *
  */
-union cvmx_rnm_serial_num
-{
+union cvmx_rnm_serial_num {
 	uint64_t u64;
-	struct cvmx_rnm_serial_num_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_rnm_serial_num_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t dat                          : 64; /**< Dormant encryption serial number */
 #else
 	uint64_t dat                          : 64;
 #endif
 	} s;
+	struct cvmx_rnm_serial_num_s          cn61xx;
 	struct cvmx_rnm_serial_num_s          cn63xx;
+	struct cvmx_rnm_serial_num_s          cn66xx;
+	struct cvmx_rnm_serial_num_s          cn68xx;
+	struct cvmx_rnm_serial_num_s          cn68xxp1;
+	struct cvmx_rnm_serial_num_s          cnf71xx;
 };
 typedef union cvmx_rnm_serial_num cvmx_rnm_serial_num_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-rtc.h b/sys/contrib/octeon-sdk/cvmx-rtc.h
index f35739d..59858e5 100644
--- a/sys/contrib/octeon-sdk/cvmx-rtc.h
+++ b/sys/contrib/octeon-sdk/cvmx-rtc.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * This file provides support for real time clocks on some boards
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-rwlock.h b/sys/contrib/octeon-sdk/cvmx-rwlock.h
index e674510..d236d19 100644
--- a/sys/contrib/octeon-sdk/cvmx-rwlock.h
+++ b/sys/contrib/octeon-sdk/cvmx-rwlock.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * This file provides reader/writer locks.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  *
  */
diff --git a/sys/contrib/octeon-sdk/cvmx-scratch.h b/sys/contrib/octeon-sdk/cvmx-scratch.h
index fc5d845..816f025 100644
--- a/sys/contrib/octeon-sdk/cvmx-scratch.h
+++ b/sys/contrib/octeon-sdk/cvmx-scratch.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -50,7 +50,7 @@
  * Scratch memory is byte addressable - all addresses are byte addresses.
  *
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  *
  */
diff --git a/sys/contrib/octeon-sdk/cvmx-shared-linux-n32.ld b/sys/contrib/octeon-sdk/cvmx-shared-linux-n32.ld
new file mode 100644
index 0000000..39b7afc
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-shared-linux-n32.ld
@@ -0,0 +1,307 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights 
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.  
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries. 
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+
+
+
+/*
+ * This was created from a template supplied by GNU binutils.
+ * Copyright (C) 2005 Cavium Inc.
+ */
+
+/**
+ * @file
+ * This linker script for use in building simple executive application to run
+ * under Linux in userspace. The important difference from a standard Linux
+ * binary is the addition of the ".cvmx_shared" memory section. This script
+ * adds two symbols __cvmx_shared_start and __cvmx_shared_end before and after
+ * the CVMX_SHARED data. These are used by cvmx-app-init-linux.c to create a
+ * shared region across all application processes.
+ *
+ * The original template for this files was:
+ * ${OCTEON_ROOT}/tools/mips64-octeon-linux-gnu/lib/ldscripts/elf32btsmipn32.x
+ */
+OUTPUT_FORMAT("elf32-ntradbigmips", "elf32-ntradbigmips",
+	      "elf32-ntradlittlemips")
+OUTPUT_ARCH(mips)
+ENTRY(__start)
+SEARCH_DIR("${OCTEON_ROOT}/tools/mips64-octeon-linux-gnu/lib");
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x10000000); . = 0x10000000 + SIZEOF_HEADERS;
+  .interp         : { *(.interp) }
+  .reginfo        : { *(.reginfo) }
+  .note.gnu.build-id : { *(.note.gnu.build-id) }
+  .dynamic        : { *(.dynamic) }
+  .hash           : { *(.hash) }
+  .gnu.hash       : { *(.gnu.hash) }
+  .dynsym         : { *(.dynsym) }
+  .dynstr         : { *(.dynstr) }
+  .gnu.version    : { *(.gnu.version) }
+  .gnu.version_d  : { *(.gnu.version_d) }
+  .gnu.version_r  : { *(.gnu.version_r) }
+  .rel.init       : { *(.rel.init) }
+  .rela.init      : { *(.rela.init) }
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+  .rel.fini       : { *(.rel.fini) }
+  .rela.fini      : { *(.rela.fini) }
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
+  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
+  .rel.data.rel.ro   : { *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*) }
+  .rela.data.rel.ro   : { *(.rela.data.rel.ro* .rela.gnu.linkonce.d.rel.ro.*) }
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }
+  .rel.tdata	  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }
+  .rela.tdata	  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }
+  .rel.tbss	  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
+  .rela.tbss	  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
+  .rel.ctors      : { *(.rel.ctors) }
+  .rela.ctors     : { *(.rela.ctors) }
+  .rel.dtors      : { *(.rel.dtors) }
+  .rela.dtors     : { *(.rela.dtors) }
+  .rel.got        : { *(.rel.got) }
+  .rela.got       : { *(.rela.got) }
+  .rel.dyn        : { *(.rel.dyn) }
+  .rel.sdata      : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }
+  .rela.sdata     : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }
+  .rel.sbss       : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }
+  .rela.sbss      : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) }
+  .rel.sdata2     : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }
+  .rela.sdata2    : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }
+  .rel.sbss2      : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }
+  .rela.sbss2     : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
+  .rel.plt        : { *(.rel.plt) }
+  .rela.plt       : { *(.rela.plt) }
+  .init           :
+  {
+    KEEP (*(.init))
+  } =0
+  .plt            : { *(.plt) }
+  .text           :
+  {
+    _ftext = . ;
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.mips16.fn.*) *(.mips16.call.*)
+  } =0
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } =0
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
+  .rodata1        : { *(.rodata1) }
+  .sdata2         :
+  {
+    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+  }
+  .sbss2          : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
+  .eh_frame_hdr : { *(.eh_frame_hdr) }
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = ALIGN (CONSTANT (MAXPAGESIZE)) - ((CONSTANT (MAXPAGESIZE) - .) & (CONSTANT (MAXPAGESIZE) - 1)); . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE));
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }
+  .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }
+  /* Thread Local Storage sections  */
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  }
+  .init_array     :
+  {
+     PROVIDE_HIDDEN (__init_array_start = .);
+     KEEP (*(SORT(.init_array.*)))
+     KEEP (*(.init_array))
+     PROVIDE_HIDDEN (__init_array_end = .);
+  }
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  }
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  }
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  }
+  .jcr            : { KEEP (*(.jcr)) }
+  .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) }
+  . = DATA_SEGMENT_RELRO_END (0, .);
+  .data           :
+  {
+    _fdata = . ;
+    *(.data .data.* .gnu.linkonce.d.*)
+    SORT(CONSTRUCTORS)
+  }
+  .data1          : { *(.data1) }
+  .got.plt        : { *(.got.plt) }
+  . = .;
+  _gp = ALIGN(16) + 0x7ff0;
+  .got            : { *(.got) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata          :
+  {
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+  .lit8           : { *(.lit8) }
+  .lit4           : { *(.lit4) }
+  .srdata         : { *(.srdata) }
+
+  . = ALIGN (0x10000);
+  __cvmx_shared_start = .;
+  .cvmx_shared : {*(.cvmx_shared .cvmx_shared.linkonce.*)}
+  .cvmx_shared_bss : { *(.cvmx_shared_bss .cvmx_shared_bss.linkonce.*) }
+  . = ALIGN (0x10000);
+  __cvmx_shared_end = .;
+
+  _edata = .; PROVIDE (edata = .);
+  __bss_start = .;
+  _fbss = .;
+  .sbss           :
+  {
+    PROVIDE (__sbss_start = .);
+    PROVIDE (___sbss_start = .);
+    *(.dynsbss)
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+    PROVIDE (__sbss_end = .);
+    PROVIDE (___sbss_end = .);
+  }
+  .bss            :
+  {
+   *(.dynbss)
+   *(.bss .bss.* .gnu.linkonce.b.*)
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.
+      FIXME: Why do we need it? When there is no .bss section, we don't
+      pad the .data section.  */
+   . = ALIGN(. != 0 ? 32 / 8 : 1);
+  }
+  . = ALIGN(32 / 8);
+  . = ALIGN(32M);    /* RBF added alignment of data */
+  .cvmx_shared : { *(.cvmx_shared) }
+  _end = .; PROVIDE (end = .);
+  . = DATA_SEGMENT_END (.);
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  /* DWARF 3 */
+  .debug_pubtypes 0 : { *(.debug_pubtypes) }
+  .debug_ranges   0 : { *(.debug_ranges) }
+  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
+  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
+  /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) }
+}
diff --git a/sys/contrib/octeon-sdk/cvmx-shared-linux-o32.ld b/sys/contrib/octeon-sdk/cvmx-shared-linux-o32.ld
new file mode 100644
index 0000000..008295d
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-shared-linux-o32.ld
@@ -0,0 +1,279 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights 
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.  
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries. 
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+
+
+
+/*
+ * This was created from a template supplied by GNU binutils.
+ * Copyright (C) 2004 Cavium Inc.
+ */
+
+/**
+ * @file
+ * This linker script for use in building simple executive application to run
+ * under Linux in userspace. The important difference from a standard Linux
+ * binary is the addition of the ".cvmx_shared" memory section. This script
+ * adds two symbols __cvmx_shared_start and __cvmx_sahred_end before and after
+ * the CVMX_SHARED data. These are used by cvmx-app-init-linux.c to create a
+ * shared region across all application processes.
+ *
+ * The original template for this files was:
+ * ${OCTEON_ROOT}/tools/mips64-octeon-linux-gnu/lib/ldscripts/elf32btsmip.x
+ */
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips",
+	      "elf32-tradlittlemips")
+OUTPUT_ARCH(mips)
+ENTRY(__start)
+SEARCH_DIR("${OCTEON_ROOT}/tools/mips64-octeon-linux-gnu/lib");
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x10000000); . = 0x10000000 + SIZEOF_HEADERS;
+  .interp         : { *(.interp) }
+  .reginfo        : { *(.reginfo) }
+  .dynamic        : { *(.dynamic) }
+  .hash           : { *(.hash) }
+  .dynsym         : { *(.dynsym) }
+  .dynstr         : { *(.dynstr) }
+  .gnu.version    : { *(.gnu.version) }
+  .gnu.version_d  : { *(.gnu.version_d) }
+  .gnu.version_r  : { *(.gnu.version_r) }
+  .rel.init       : { *(.rel.init) }
+  .rela.init      : { *(.rela.init) }
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+  .rel.fini       : { *(.rel.fini) }
+  .rela.fini      : { *(.rela.fini) }
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
+  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }
+  .rel.tdata	  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }
+  .rela.tdata	  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }
+  .rel.tbss	  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
+  .rela.tbss	  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
+  .rel.ctors      : { *(.rel.ctors) }
+  .rela.ctors     : { *(.rela.ctors) }
+  .rel.dtors      : { *(.rel.dtors) }
+  .rela.dtors     : { *(.rela.dtors) }
+  .rel.got        : { *(.rel.got) }
+  .rela.got       : { *(.rela.got) }
+  .rel.sdata      : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }
+  .rela.sdata     : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }
+  .rel.sbss       : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }
+  .rela.sbss      : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) }
+  .rel.sdata2     : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }
+  .rela.sdata2    : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }
+  .rel.sbss2      : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }
+  .rela.sbss2     : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
+  .rel.plt        : { *(.rel.plt) }
+  .rela.plt       : { *(.rela.plt) }
+  .init           :
+  {
+    KEEP (*(.init))
+  } =0
+  .plt            : { *(.plt) }
+  .text           :
+  {
+    _ftext = . ;
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.mips16.fn.*) *(.mips16.call.*)
+  } =0
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } =0
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
+  .rodata1        : { *(.rodata1) }
+  .sdata2         : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }
+  .sbss2          : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
+  .eh_frame_hdr : { *(.eh_frame_hdr) }
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = 0x10000000;
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  . = ALIGN(32 / 8);
+  PROVIDE (__preinit_array_start = .);
+  .preinit_array     : { *(.preinit_array) }
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { *(.init_array) }
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { *(.fini_array) }
+  PROVIDE (__fini_array_end = .);
+  .data           :
+  {
+    _fdata = . ;
+    *(.data .data.* .gnu.linkonce.d.*)
+    SORT(CONSTRUCTORS)
+  }
+  .data1          : { *(.data1) }
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
+  .eh_frame       : { KEEP (*(.eh_frame)) }
+  .gcc_except_table   : { *(.gcc_except_table) }
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  }
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  }
+  .jcr            : { KEEP (*(.jcr)) }
+  _gp = ALIGN(16) + 0x7ff0;
+  .got            : { *(.got.plt) *(.got) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata          :
+  {
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+  .lit8           : { *(.lit8) }
+  .lit4           : { *(.lit4) }
+
+  . = ALIGN (0x10000);
+  __cvmx_shared_start = .;
+  .cvmx_shared : {*(.cvmx_shared .cvmx_shared.linkonce.*)}
+  .cvmx_shared_bss : {*(.cvmx_shared_bss .cvmx_shared_bss.linkonce.*)}
+  . = ALIGN (0x10000);
+  __cvmx_shared_end = .;
+
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  _fbss = .;
+  .sbss           :
+  {
+    PROVIDE (__sbss_start = .);
+    PROVIDE (___sbss_start = .);
+    *(.dynsbss)
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+    PROVIDE (__sbss_end = .);
+    PROVIDE (___sbss_end = .);
+  }
+  .bss            :
+  {
+   *(.dynbss)
+   *(.bss .bss.* .gnu.linkonce.b.*)
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.  */
+   . = ALIGN(32 / 8);
+  }
+  . = ALIGN(32 / 8);
+  . = ALIGN(32M);    /* RBF added alignment of data */
+  .cvmx_shared : { *(.cvmx_shared) }
+  _end = .;
+  PROVIDE (end = .);
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
+  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/sys/contrib/octeon-sdk/cvmx-shared-linux.ld b/sys/contrib/octeon-sdk/cvmx-shared-linux.ld
new file mode 100644
index 0000000..41cffcf
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-shared-linux.ld
@@ -0,0 +1,306 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights 
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.  
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries. 
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+
+
+
+/*
+ * This was created from a template supplied by GNU binutils.
+ * Copyright (C) 2004 Cavium Inc.
+ */
+ 
+/**
+ * @file
+ * This linker script for use in building simple executive application to run
+ * under Linux in userspace. The important difference from a standard Linux 
+ * binary is the addition of the ".cvmx_shared" memory section. This script 
+ * adds two symbols __cvmx_shared_start and __cvmx_sahred_end before and after
+ * the CVMX_SHARED data. These are used by cvmx-app-init-linux.c to create a
+ * shared region across all application processes.
+ *
+ * The original template for this files was:
+ * ${OCTEON_ROOT}/tools/mips64-octeon-linux-gnu/lib/ldscripts/elf64btsmip.x
+ */
+OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips",
+	      "elf64-tradlittlemips")
+OUTPUT_ARCH(mips)
+ENTRY(__start)
+SEARCH_DIR("${OCTEON_ROOT}/tools/mips64-octeon-linux-gnu/lib");
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x120000000); . = 0x120000000 + SIZEOF_HEADERS;
+  .MIPS.options : { *(.MIPS.options) }
+  .note.gnu.build-id : { *(.note.gnu.build-id) }
+  .dynamic        : { *(.dynamic) }
+  .hash           : { *(.hash) }
+  .gnu.hash       : { *(.gnu.hash) }
+  .dynsym         : { *(.dynsym) }
+  .dynstr         : { *(.dynstr) }
+  .gnu.version    : { *(.gnu.version) }
+  .gnu.version_d  : { *(.gnu.version_d) }
+  .gnu.version_r  : { *(.gnu.version_r) }
+  .rel.init       : { *(.rel.init) }
+  .rela.init      : { *(.rela.init) }
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+  .rel.fini       : { *(.rel.fini) }
+  .rela.fini      : { *(.rela.fini) }
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
+  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
+  .rel.data.rel.ro   : { *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*) }
+  .rela.data.rel.ro   : { *(.rela.data.rel.ro* .rela.gnu.linkonce.d.rel.ro.*) }
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }
+  .rel.tdata	  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }
+  .rela.tdata	  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }
+  .rel.tbss	  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
+  .rela.tbss	  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
+  .rel.ctors      : { *(.rel.ctors) }
+  .rela.ctors     : { *(.rela.ctors) }
+  .rel.dtors      : { *(.rel.dtors) }
+  .rela.dtors     : { *(.rela.dtors) }
+  .rel.got        : { *(.rel.got) }
+  .rela.got       : { *(.rela.got) }
+  .rel.dyn        : { *(.rel.dyn) }
+  .rel.sdata      : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }
+  .rela.sdata     : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }
+  .rel.sbss       : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }
+  .rela.sbss      : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) }
+  .rel.sdata2     : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }
+  .rela.sdata2    : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }
+  .rel.sbss2      : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }
+  .rela.sbss2     : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
+  .rel.plt        : { *(.rel.plt) }
+  .rela.plt       : { *(.rela.plt) }
+  .init           :
+  {
+    KEEP (*(.init))
+  } =0
+  .plt            : { *(.plt) }
+  .text           :
+  {
+    _ftext = . ;
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.mips16.fn.*) *(.mips16.call.*)
+  } =0
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } =0
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
+  .rodata1        : { *(.rodata1) }
+  .sdata2         :
+  {
+    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+  }
+  .sbss2          : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
+  .eh_frame_hdr : { *(.eh_frame_hdr) }
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = ALIGN (CONSTANT (MAXPAGESIZE)) - ((CONSTANT (MAXPAGESIZE) - .) & (CONSTANT (MAXPAGESIZE) - 1)); . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE));
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }
+  .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }
+  /* Thread Local Storage sections  */
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  }
+  .init_array     :
+  {
+     PROVIDE_HIDDEN (__init_array_start = .);
+     KEEP (*(SORT(.init_array.*)))
+     KEEP (*(.init_array))
+     PROVIDE_HIDDEN (__init_array_end = .);
+  }
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  }
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  }
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  }
+  .jcr            : { KEEP (*(.jcr)) }
+  .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) }
+  . = DATA_SEGMENT_RELRO_END (0, .);
+  .data           :
+  {
+    _fdata = . ;
+    *(.data .data.* .gnu.linkonce.d.*)
+    SORT(CONSTRUCTORS)
+  }
+  .data1          : { *(.data1) }
+  .got.plt        : { *(.got.plt) }
+  . = .;
+  _gp = ALIGN(16) + 0x7ff0;
+  .got            : { *(.got) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata          :
+  {
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+  .lit8           : { *(.lit8) }
+  .lit4           : { *(.lit4) }
+  .srdata         : { *(.srdata) }
+  
+  . = ALIGN (0x10000); 
+  __cvmx_shared_start = .;
+  .cvmx_shared : {*(.cvmx_shared .cvmx_shared.linkonce.*)}
+  .cvmx_shared_bss : { *(.cvmx_shared_bss .cvmx_shared_bss.linkonce.*) }
+  . = ALIGN (0x10000);
+  __cvmx_shared_end = .;
+  
+  _edata = .; PROVIDE (edata = .);
+  __bss_start = .;
+  _fbss = .;
+  .sbss           :
+  {
+    PROVIDE (__sbss_start = .);
+    PROVIDE (___sbss_start = .);
+    *(.dynsbss)
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+    PROVIDE (__sbss_end = .);
+    PROVIDE (___sbss_end = .);
+  }
+  .bss            :
+  {
+   *(.dynbss)
+   *(.bss .bss.* .gnu.linkonce.b.*)
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.
+      FIXME: Why do we need it? When there is no .bss section, we don't
+      pad the .data section.  */
+   . = ALIGN(. != 0 ? 64 / 8 : 1);
+  }
+  . = ALIGN(64 / 8);
+  . = ALIGN(32M);    /* RBF added alignment of data */
+  .cvmx_shared : { *(.cvmx_shared) }
+  _end = .; PROVIDE (end = .);
+  . = DATA_SEGMENT_END (.);
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  /* DWARF 3 */
+  .debug_pubtypes 0 : { *(.debug_pubtypes) }
+  .debug_ranges   0 : { *(.debug_ranges) }
+  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
+  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
+  /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) }
+}
diff --git a/sys/contrib/octeon-sdk/cvmx-shmem.c b/sys/contrib/octeon-sdk/cvmx-shmem.c
index c289d13..bf18f88 100644
--- a/sys/contrib/octeon-sdk/cvmx-shmem.c
+++ b/sys/contrib/octeon-sdk/cvmx-shmem.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-shmem.h b/sys/contrib/octeon-sdk/cvmx-shmem.h
index f99cad5..25472d1 100644
--- a/sys/contrib/octeon-sdk/cvmx-shmem.h
+++ b/sys/contrib/octeon-sdk/cvmx-shmem.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-sim-magic.h b/sys/contrib/octeon-sdk/cvmx-sim-magic.h
index 5145b64..5cf3978 100644
--- a/sys/contrib/octeon-sdk/cvmx-sim-magic.h
+++ b/sys/contrib/octeon-sdk/cvmx-sim-magic.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -43,7 +43,7 @@
  *
  * This is file defines ASM primitives for sim magic functions.
 
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  *
  */
@@ -185,7 +185,7 @@ static inline int cvmx_sim_magic_get_iofreq(void)
 {
     CVMX_SYNC;
 
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
        return  __cvmx_sim_magic_return(SIM_MAGIC_GET_IOFREQ);
     else
        return 0;
diff --git a/sys/contrib/octeon-sdk/cvmx-sli-defs.h b/sys/contrib/octeon-sdk/cvmx-sli-defs.h
index 6a1518e..e5fa364 100644
--- a/sys/contrib/octeon-sdk/cvmx-sli-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-sli-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,14 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_SLI_TYPEDEFS_H__
-#define __CVMX_SLI_TYPEDEFS_H__
+#ifndef __CVMX_SLI_DEFS_H__
+#define __CVMX_SLI_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_SLI_BIST_STATUS CVMX_SLI_BIST_STATUS_FUNC()
 static inline uint64_t CVMX_SLI_BIST_STATUS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_BIST_STATUS not supported on this chip\n");
 	return 0x0000000000000580ull;
 }
@@ -67,18 +67,22 @@ static inline uint64_t CVMX_SLI_BIST_STATUS_FUNC(void)
 static inline uint64_t CVMX_SLI_CTL_PORTX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_SLI_CTL_PORTX(%lu) is invalid on this chip\n", offset);
-	return 0x0000000000000050ull + ((offset) & 1) * 16;
+	return 0x0000000000000050ull + ((offset) & 3) * 16;
 }
 #else
-#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 1) * 16)
+#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_SLI_CTL_STATUS CVMX_SLI_CTL_STATUS_FUNC()
 static inline uint64_t CVMX_SLI_CTL_STATUS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_CTL_STATUS not supported on this chip\n");
 	return 0x0000000000000570ull;
 }
@@ -89,7 +93,7 @@ static inline uint64_t CVMX_SLI_CTL_STATUS_FUNC(void)
 #define CVMX_SLI_DATA_OUT_CNT CVMX_SLI_DATA_OUT_CNT_FUNC()
 static inline uint64_t CVMX_SLI_DATA_OUT_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_DATA_OUT_CNT not supported on this chip\n");
 	return 0x00000000000005F0ull;
 }
@@ -100,7 +104,7 @@ static inline uint64_t CVMX_SLI_DATA_OUT_CNT_FUNC(void)
 #define CVMX_SLI_DBG_DATA CVMX_SLI_DBG_DATA_FUNC()
 static inline uint64_t CVMX_SLI_DBG_DATA_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_DBG_DATA not supported on this chip\n");
 	return 0x0000000000000310ull;
 }
@@ -111,7 +115,7 @@ static inline uint64_t CVMX_SLI_DBG_DATA_FUNC(void)
 #define CVMX_SLI_DBG_SELECT CVMX_SLI_DBG_SELECT_FUNC()
 static inline uint64_t CVMX_SLI_DBG_SELECT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_DBG_SELECT not supported on this chip\n");
 	return 0x0000000000000300ull;
 }
@@ -122,7 +126,11 @@ static inline uint64_t CVMX_SLI_DBG_SELECT_FUNC(void)
 static inline uint64_t CVMX_SLI_DMAX_CNT(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_SLI_DMAX_CNT(%lu) is invalid on this chip\n", offset);
 	return 0x0000000000000400ull + ((offset) & 1) * 16;
 }
@@ -133,7 +141,11 @@ static inline uint64_t CVMX_SLI_DMAX_CNT(unsigned long offset)
 static inline uint64_t CVMX_SLI_DMAX_INT_LEVEL(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_SLI_DMAX_INT_LEVEL(%lu) is invalid on this chip\n", offset);
 	return 0x00000000000003E0ull + ((offset) & 1) * 16;
 }
@@ -144,7 +156,11 @@ static inline uint64_t CVMX_SLI_DMAX_INT_LEVEL(unsigned long offset)
 static inline uint64_t CVMX_SLI_DMAX_TIM(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_SLI_DMAX_TIM(%lu) is invalid on this chip\n", offset);
 	return 0x0000000000000420ull + ((offset) & 1) * 16;
 }
@@ -155,7 +171,7 @@ static inline uint64_t CVMX_SLI_DMAX_TIM(unsigned long offset)
 #define CVMX_SLI_INT_ENB_CIU CVMX_SLI_INT_ENB_CIU_FUNC()
 static inline uint64_t CVMX_SLI_INT_ENB_CIU_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_INT_ENB_CIU not supported on this chip\n");
 	return 0x0000000000003CD0ull;
 }
@@ -166,7 +182,11 @@ static inline uint64_t CVMX_SLI_INT_ENB_CIU_FUNC(void)
 static inline uint64_t CVMX_SLI_INT_ENB_PORTX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_SLI_INT_ENB_PORTX(%lu) is invalid on this chip\n", offset);
 	return 0x0000000000000340ull + ((offset) & 1) * 16;
 }
@@ -177,7 +197,7 @@ static inline uint64_t CVMX_SLI_INT_ENB_PORTX(unsigned long offset)
 #define CVMX_SLI_INT_SUM CVMX_SLI_INT_SUM_FUNC()
 static inline uint64_t CVMX_SLI_INT_SUM_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_INT_SUM not supported on this chip\n");
 	return 0x0000000000000330ull;
 }
@@ -188,7 +208,7 @@ static inline uint64_t CVMX_SLI_INT_SUM_FUNC(void)
 #define CVMX_SLI_LAST_WIN_RDATA0 CVMX_SLI_LAST_WIN_RDATA0_FUNC()
 static inline uint64_t CVMX_SLI_LAST_WIN_RDATA0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_LAST_WIN_RDATA0 not supported on this chip\n");
 	return 0x0000000000000600ull;
 }
@@ -199,7 +219,7 @@ static inline uint64_t CVMX_SLI_LAST_WIN_RDATA0_FUNC(void)
 #define CVMX_SLI_LAST_WIN_RDATA1 CVMX_SLI_LAST_WIN_RDATA1_FUNC()
 static inline uint64_t CVMX_SLI_LAST_WIN_RDATA1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_LAST_WIN_RDATA1 not supported on this chip\n");
 	return 0x0000000000000610ull;
 }
@@ -207,10 +227,32 @@ static inline uint64_t CVMX_SLI_LAST_WIN_RDATA1_FUNC(void)
 #define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_LAST_WIN_RDATA2 CVMX_SLI_LAST_WIN_RDATA2_FUNC()
+static inline uint64_t CVMX_SLI_LAST_WIN_RDATA2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_SLI_LAST_WIN_RDATA2 not supported on this chip\n");
+	return 0x00000000000006C0ull;
+}
+#else
+#define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_LAST_WIN_RDATA3 CVMX_SLI_LAST_WIN_RDATA3_FUNC()
+static inline uint64_t CVMX_SLI_LAST_WIN_RDATA3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_SLI_LAST_WIN_RDATA3 not supported on this chip\n");
+	return 0x00000000000006D0ull;
+}
+#else
+#define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_SLI_MAC_CREDIT_CNT CVMX_SLI_MAC_CREDIT_CNT_FUNC()
 static inline uint64_t CVMX_SLI_MAC_CREDIT_CNT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MAC_CREDIT_CNT not supported on this chip\n");
 	return 0x0000000000003D70ull;
 }
@@ -218,10 +260,21 @@ static inline uint64_t CVMX_SLI_MAC_CREDIT_CNT_FUNC(void)
 #define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MAC_CREDIT_CNT2 CVMX_SLI_MAC_CREDIT_CNT2_FUNC()
+static inline uint64_t CVMX_SLI_MAC_CREDIT_CNT2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_SLI_MAC_CREDIT_CNT2 not supported on this chip\n");
+	return 0x0000000000003E10ull;
+}
+#else
+#define CVMX_SLI_MAC_CREDIT_CNT2 (0x0000000000003E10ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_SLI_MAC_NUMBER CVMX_SLI_MAC_NUMBER_FUNC()
 static inline uint64_t CVMX_SLI_MAC_NUMBER_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MAC_NUMBER not supported on this chip\n");
 	return 0x0000000000003E00ull;
 }
@@ -232,7 +285,7 @@ static inline uint64_t CVMX_SLI_MAC_NUMBER_FUNC(void)
 #define CVMX_SLI_MEM_ACCESS_CTL CVMX_SLI_MEM_ACCESS_CTL_FUNC()
 static inline uint64_t CVMX_SLI_MEM_ACCESS_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MEM_ACCESS_CTL not supported on this chip\n");
 	return 0x00000000000002F0ull;
 }
@@ -243,18 +296,22 @@ static inline uint64_t CVMX_SLI_MEM_ACCESS_CTL_FUNC(void)
 static inline uint64_t CVMX_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 12) && (offset <= 27))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 12) && (offset <= 27)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 12) && (offset <= 27)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 12) && (offset <= 27)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 12) && (offset <= 27)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 12) && (offset <= 27))))))
 		cvmx_warn("CVMX_SLI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
-	return 0x00000000000001A0ull + ((offset) & 31) * 16 - 16*12;
+	return 0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12;
 }
 #else
-#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000001A0ull + ((offset) & 31) * 16 - 16*12)
+#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_SLI_MSI_ENB0 CVMX_SLI_MSI_ENB0_FUNC()
 static inline uint64_t CVMX_SLI_MSI_ENB0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MSI_ENB0 not supported on this chip\n");
 	return 0x0000000000003C50ull;
 }
@@ -265,7 +322,7 @@ static inline uint64_t CVMX_SLI_MSI_ENB0_FUNC(void)
 #define CVMX_SLI_MSI_ENB1 CVMX_SLI_MSI_ENB1_FUNC()
 static inline uint64_t CVMX_SLI_MSI_ENB1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MSI_ENB1 not supported on this chip\n");
 	return 0x0000000000003C60ull;
 }
@@ -276,7 +333,7 @@ static inline uint64_t CVMX_SLI_MSI_ENB1_FUNC(void)
 #define CVMX_SLI_MSI_ENB2 CVMX_SLI_MSI_ENB2_FUNC()
 static inline uint64_t CVMX_SLI_MSI_ENB2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MSI_ENB2 not supported on this chip\n");
 	return 0x0000000000003C70ull;
 }
@@ -287,7 +344,7 @@ static inline uint64_t CVMX_SLI_MSI_ENB2_FUNC(void)
 #define CVMX_SLI_MSI_ENB3 CVMX_SLI_MSI_ENB3_FUNC()
 static inline uint64_t CVMX_SLI_MSI_ENB3_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MSI_ENB3 not supported on this chip\n");
 	return 0x0000000000003C80ull;
 }
@@ -298,7 +355,7 @@ static inline uint64_t CVMX_SLI_MSI_ENB3_FUNC(void)
 #define CVMX_SLI_MSI_RCV0 CVMX_SLI_MSI_RCV0_FUNC()
 static inline uint64_t CVMX_SLI_MSI_RCV0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MSI_RCV0 not supported on this chip\n");
 	return 0x0000000000003C10ull;
 }
@@ -309,7 +366,7 @@ static inline uint64_t CVMX_SLI_MSI_RCV0_FUNC(void)
 #define CVMX_SLI_MSI_RCV1 CVMX_SLI_MSI_RCV1_FUNC()
 static inline uint64_t CVMX_SLI_MSI_RCV1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MSI_RCV1 not supported on this chip\n");
 	return 0x0000000000003C20ull;
 }
@@ -320,7 +377,7 @@ static inline uint64_t CVMX_SLI_MSI_RCV1_FUNC(void)
 #define CVMX_SLI_MSI_RCV2 CVMX_SLI_MSI_RCV2_FUNC()
 static inline uint64_t CVMX_SLI_MSI_RCV2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MSI_RCV2 not supported on this chip\n");
 	return 0x0000000000003C30ull;
 }
@@ -331,7 +388,7 @@ static inline uint64_t CVMX_SLI_MSI_RCV2_FUNC(void)
 #define CVMX_SLI_MSI_RCV3 CVMX_SLI_MSI_RCV3_FUNC()
 static inline uint64_t CVMX_SLI_MSI_RCV3_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MSI_RCV3 not supported on this chip\n");
 	return 0x0000000000003C40ull;
 }
@@ -342,7 +399,7 @@ static inline uint64_t CVMX_SLI_MSI_RCV3_FUNC(void)
 #define CVMX_SLI_MSI_RD_MAP CVMX_SLI_MSI_RD_MAP_FUNC()
 static inline uint64_t CVMX_SLI_MSI_RD_MAP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MSI_RD_MAP not supported on this chip\n");
 	return 0x0000000000003CA0ull;
 }
@@ -353,7 +410,7 @@ static inline uint64_t CVMX_SLI_MSI_RD_MAP_FUNC(void)
 #define CVMX_SLI_MSI_W1C_ENB0 CVMX_SLI_MSI_W1C_ENB0_FUNC()
 static inline uint64_t CVMX_SLI_MSI_W1C_ENB0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MSI_W1C_ENB0 not supported on this chip\n");
 	return 0x0000000000003CF0ull;
 }
@@ -364,7 +421,7 @@ static inline uint64_t CVMX_SLI_MSI_W1C_ENB0_FUNC(void)
 #define CVMX_SLI_MSI_W1C_ENB1 CVMX_SLI_MSI_W1C_ENB1_FUNC()
 static inline uint64_t CVMX_SLI_MSI_W1C_ENB1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MSI_W1C_ENB1 not supported on this chip\n");
 	return 0x0000000000003D00ull;
 }
@@ -375,7 +432,7 @@ static inline uint64_t CVMX_SLI_MSI_W1C_ENB1_FUNC(void)
 #define CVMX_SLI_MSI_W1C_ENB2 CVMX_SLI_MSI_W1C_ENB2_FUNC()
 static inline uint64_t CVMX_SLI_MSI_W1C_ENB2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MSI_W1C_ENB2 not supported on this chip\n");
 	return 0x0000000000003D10ull;
 }
@@ -386,7 +443,7 @@ static inline uint64_t CVMX_SLI_MSI_W1C_ENB2_FUNC(void)
 #define CVMX_SLI_MSI_W1C_ENB3 CVMX_SLI_MSI_W1C_ENB3_FUNC()
 static inline uint64_t CVMX_SLI_MSI_W1C_ENB3_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MSI_W1C_ENB3 not supported on this chip\n");
 	return 0x0000000000003D20ull;
 }
@@ -397,7 +454,7 @@ static inline uint64_t CVMX_SLI_MSI_W1C_ENB3_FUNC(void)
 #define CVMX_SLI_MSI_W1S_ENB0 CVMX_SLI_MSI_W1S_ENB0_FUNC()
 static inline uint64_t CVMX_SLI_MSI_W1S_ENB0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MSI_W1S_ENB0 not supported on this chip\n");
 	return 0x0000000000003D30ull;
 }
@@ -408,7 +465,7 @@ static inline uint64_t CVMX_SLI_MSI_W1S_ENB0_FUNC(void)
 #define CVMX_SLI_MSI_W1S_ENB1 CVMX_SLI_MSI_W1S_ENB1_FUNC()
 static inline uint64_t CVMX_SLI_MSI_W1S_ENB1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MSI_W1S_ENB1 not supported on this chip\n");
 	return 0x0000000000003D40ull;
 }
@@ -419,7 +476,7 @@ static inline uint64_t CVMX_SLI_MSI_W1S_ENB1_FUNC(void)
 #define CVMX_SLI_MSI_W1S_ENB2 CVMX_SLI_MSI_W1S_ENB2_FUNC()
 static inline uint64_t CVMX_SLI_MSI_W1S_ENB2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MSI_W1S_ENB2 not supported on this chip\n");
 	return 0x0000000000003D50ull;
 }
@@ -430,7 +487,7 @@ static inline uint64_t CVMX_SLI_MSI_W1S_ENB2_FUNC(void)
 #define CVMX_SLI_MSI_W1S_ENB3 CVMX_SLI_MSI_W1S_ENB3_FUNC()
 static inline uint64_t CVMX_SLI_MSI_W1S_ENB3_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MSI_W1S_ENB3 not supported on this chip\n");
 	return 0x0000000000003D60ull;
 }
@@ -441,7 +498,7 @@ static inline uint64_t CVMX_SLI_MSI_W1S_ENB3_FUNC(void)
 #define CVMX_SLI_MSI_WR_MAP CVMX_SLI_MSI_WR_MAP_FUNC()
 static inline uint64_t CVMX_SLI_MSI_WR_MAP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_MSI_WR_MAP not supported on this chip\n");
 	return 0x0000000000003C90ull;
 }
@@ -452,7 +509,7 @@ static inline uint64_t CVMX_SLI_MSI_WR_MAP_FUNC(void)
 #define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC()
 static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PCIE_MSI_RCV not supported on this chip\n");
 	return 0x0000000000003CB0ull;
 }
@@ -463,7 +520,7 @@ static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void)
 #define CVMX_SLI_PCIE_MSI_RCV_B1 CVMX_SLI_PCIE_MSI_RCV_B1_FUNC()
 static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B1 not supported on this chip\n");
 	return 0x0000000000000650ull;
 }
@@ -474,7 +531,7 @@ static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B1_FUNC(void)
 #define CVMX_SLI_PCIE_MSI_RCV_B2 CVMX_SLI_PCIE_MSI_RCV_B2_FUNC()
 static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B2 not supported on this chip\n");
 	return 0x0000000000000660ull;
 }
@@ -485,7 +542,7 @@ static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B2_FUNC(void)
 #define CVMX_SLI_PCIE_MSI_RCV_B3 CVMX_SLI_PCIE_MSI_RCV_B3_FUNC()
 static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B3_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B3 not supported on this chip\n");
 	return 0x0000000000000670ull;
 }
@@ -496,7 +553,11 @@ static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B3_FUNC(void)
 static inline uint64_t CVMX_SLI_PKTX_CNTS(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_SLI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
 	return 0x0000000000002400ull + ((offset) & 31) * 16;
 }
@@ -507,7 +568,11 @@ static inline uint64_t CVMX_SLI_PKTX_CNTS(unsigned long offset)
 static inline uint64_t CVMX_SLI_PKTX_INSTR_BADDR(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_SLI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
 	return 0x0000000000002800ull + ((offset) & 31) * 16;
 }
@@ -518,7 +583,11 @@ static inline uint64_t CVMX_SLI_PKTX_INSTR_BADDR(unsigned long offset)
 static inline uint64_t CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
 	return 0x0000000000002C00ull + ((offset) & 31) * 16;
 }
@@ -529,7 +598,11 @@ static inline uint64_t CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
 static inline uint64_t CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
 	return 0x0000000000003000ull + ((offset) & 31) * 16;
 }
@@ -540,7 +613,11 @@ static inline uint64_t CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
 static inline uint64_t CVMX_SLI_PKTX_INSTR_HEADER(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_SLI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
 	return 0x0000000000003400ull + ((offset) & 31) * 16;
 }
@@ -551,7 +628,10 @@ static inline uint64_t CVMX_SLI_PKTX_INSTR_HEADER(unsigned long offset)
 static inline uint64_t CVMX_SLI_PKTX_IN_BP(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_SLI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
 	return 0x0000000000003800ull + ((offset) & 31) * 16;
 }
@@ -562,7 +642,11 @@ static inline uint64_t CVMX_SLI_PKTX_IN_BP(unsigned long offset)
 static inline uint64_t CVMX_SLI_PKTX_OUT_SIZE(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_SLI_PKTX_OUT_SIZE(%lu) is invalid on this chip\n", offset);
 	return 0x0000000000000C00ull + ((offset) & 31) * 16;
 }
@@ -573,7 +657,11 @@ static inline uint64_t CVMX_SLI_PKTX_OUT_SIZE(unsigned long offset)
 static inline uint64_t CVMX_SLI_PKTX_SLIST_BADDR(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_SLI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
 	return 0x0000000000001400ull + ((offset) & 31) * 16;
 }
@@ -584,7 +672,11 @@ static inline uint64_t CVMX_SLI_PKTX_SLIST_BADDR(unsigned long offset)
 static inline uint64_t CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
 	return 0x0000000000001800ull + ((offset) & 31) * 16;
 }
@@ -595,7 +687,11 @@ static inline uint64_t CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
 static inline uint64_t CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
 	return 0x0000000000001C00ull + ((offset) & 31) * 16;
 }
@@ -606,7 +702,7 @@ static inline uint64_t CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
 #define CVMX_SLI_PKT_CNT_INT CVMX_SLI_PKT_CNT_INT_FUNC()
 static inline uint64_t CVMX_SLI_PKT_CNT_INT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_CNT_INT not supported on this chip\n");
 	return 0x0000000000001130ull;
 }
@@ -617,7 +713,7 @@ static inline uint64_t CVMX_SLI_PKT_CNT_INT_FUNC(void)
 #define CVMX_SLI_PKT_CNT_INT_ENB CVMX_SLI_PKT_CNT_INT_ENB_FUNC()
 static inline uint64_t CVMX_SLI_PKT_CNT_INT_ENB_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_CNT_INT_ENB not supported on this chip\n");
 	return 0x0000000000001150ull;
 }
@@ -628,7 +724,7 @@ static inline uint64_t CVMX_SLI_PKT_CNT_INT_ENB_FUNC(void)
 #define CVMX_SLI_PKT_CTL CVMX_SLI_PKT_CTL_FUNC()
 static inline uint64_t CVMX_SLI_PKT_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_CTL not supported on this chip\n");
 	return 0x0000000000001220ull;
 }
@@ -639,7 +735,7 @@ static inline uint64_t CVMX_SLI_PKT_CTL_FUNC(void)
 #define CVMX_SLI_PKT_DATA_OUT_ES CVMX_SLI_PKT_DATA_OUT_ES_FUNC()
 static inline uint64_t CVMX_SLI_PKT_DATA_OUT_ES_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_DATA_OUT_ES not supported on this chip\n");
 	return 0x00000000000010B0ull;
 }
@@ -650,7 +746,7 @@ static inline uint64_t CVMX_SLI_PKT_DATA_OUT_ES_FUNC(void)
 #define CVMX_SLI_PKT_DATA_OUT_NS CVMX_SLI_PKT_DATA_OUT_NS_FUNC()
 static inline uint64_t CVMX_SLI_PKT_DATA_OUT_NS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_DATA_OUT_NS not supported on this chip\n");
 	return 0x00000000000010A0ull;
 }
@@ -661,7 +757,7 @@ static inline uint64_t CVMX_SLI_PKT_DATA_OUT_NS_FUNC(void)
 #define CVMX_SLI_PKT_DATA_OUT_ROR CVMX_SLI_PKT_DATA_OUT_ROR_FUNC()
 static inline uint64_t CVMX_SLI_PKT_DATA_OUT_ROR_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_DATA_OUT_ROR not supported on this chip\n");
 	return 0x0000000000001090ull;
 }
@@ -672,7 +768,7 @@ static inline uint64_t CVMX_SLI_PKT_DATA_OUT_ROR_FUNC(void)
 #define CVMX_SLI_PKT_DPADDR CVMX_SLI_PKT_DPADDR_FUNC()
 static inline uint64_t CVMX_SLI_PKT_DPADDR_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_DPADDR not supported on this chip\n");
 	return 0x0000000000001080ull;
 }
@@ -683,7 +779,7 @@ static inline uint64_t CVMX_SLI_PKT_DPADDR_FUNC(void)
 #define CVMX_SLI_PKT_INPUT_CONTROL CVMX_SLI_PKT_INPUT_CONTROL_FUNC()
 static inline uint64_t CVMX_SLI_PKT_INPUT_CONTROL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_INPUT_CONTROL not supported on this chip\n");
 	return 0x0000000000001170ull;
 }
@@ -694,7 +790,7 @@ static inline uint64_t CVMX_SLI_PKT_INPUT_CONTROL_FUNC(void)
 #define CVMX_SLI_PKT_INSTR_ENB CVMX_SLI_PKT_INSTR_ENB_FUNC()
 static inline uint64_t CVMX_SLI_PKT_INSTR_ENB_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_INSTR_ENB not supported on this chip\n");
 	return 0x0000000000001000ull;
 }
@@ -705,7 +801,7 @@ static inline uint64_t CVMX_SLI_PKT_INSTR_ENB_FUNC(void)
 #define CVMX_SLI_PKT_INSTR_RD_SIZE CVMX_SLI_PKT_INSTR_RD_SIZE_FUNC()
 static inline uint64_t CVMX_SLI_PKT_INSTR_RD_SIZE_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_INSTR_RD_SIZE not supported on this chip\n");
 	return 0x00000000000011A0ull;
 }
@@ -716,7 +812,7 @@ static inline uint64_t CVMX_SLI_PKT_INSTR_RD_SIZE_FUNC(void)
 #define CVMX_SLI_PKT_INSTR_SIZE CVMX_SLI_PKT_INSTR_SIZE_FUNC()
 static inline uint64_t CVMX_SLI_PKT_INSTR_SIZE_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_INSTR_SIZE not supported on this chip\n");
 	return 0x0000000000001020ull;
 }
@@ -727,7 +823,7 @@ static inline uint64_t CVMX_SLI_PKT_INSTR_SIZE_FUNC(void)
 #define CVMX_SLI_PKT_INT_LEVELS CVMX_SLI_PKT_INT_LEVELS_FUNC()
 static inline uint64_t CVMX_SLI_PKT_INT_LEVELS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_INT_LEVELS not supported on this chip\n");
 	return 0x0000000000001120ull;
 }
@@ -738,7 +834,7 @@ static inline uint64_t CVMX_SLI_PKT_INT_LEVELS_FUNC(void)
 #define CVMX_SLI_PKT_IN_BP CVMX_SLI_PKT_IN_BP_FUNC()
 static inline uint64_t CVMX_SLI_PKT_IN_BP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_IN_BP not supported on this chip\n");
 	return 0x0000000000001210ull;
 }
@@ -749,7 +845,11 @@ static inline uint64_t CVMX_SLI_PKT_IN_BP_FUNC(void)
 static inline uint64_t CVMX_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
 		cvmx_warn("CVMX_SLI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
 	return 0x0000000000002000ull + ((offset) & 31) * 16;
 }
@@ -760,7 +860,7 @@ static inline uint64_t CVMX_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)
 #define CVMX_SLI_PKT_IN_INSTR_COUNTS CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC()
 static inline uint64_t CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
 	return 0x0000000000001200ull;
 }
@@ -771,7 +871,7 @@ static inline uint64_t CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC(void)
 #define CVMX_SLI_PKT_IN_PCIE_PORT CVMX_SLI_PKT_IN_PCIE_PORT_FUNC()
 static inline uint64_t CVMX_SLI_PKT_IN_PCIE_PORT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_IN_PCIE_PORT not supported on this chip\n");
 	return 0x00000000000011B0ull;
 }
@@ -782,7 +882,7 @@ static inline uint64_t CVMX_SLI_PKT_IN_PCIE_PORT_FUNC(void)
 #define CVMX_SLI_PKT_IPTR CVMX_SLI_PKT_IPTR_FUNC()
 static inline uint64_t CVMX_SLI_PKT_IPTR_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_IPTR not supported on this chip\n");
 	return 0x0000000000001070ull;
 }
@@ -793,7 +893,7 @@ static inline uint64_t CVMX_SLI_PKT_IPTR_FUNC(void)
 #define CVMX_SLI_PKT_OUTPUT_WMARK CVMX_SLI_PKT_OUTPUT_WMARK_FUNC()
 static inline uint64_t CVMX_SLI_PKT_OUTPUT_WMARK_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_OUTPUT_WMARK not supported on this chip\n");
 	return 0x0000000000001180ull;
 }
@@ -804,7 +904,7 @@ static inline uint64_t CVMX_SLI_PKT_OUTPUT_WMARK_FUNC(void)
 #define CVMX_SLI_PKT_OUT_BMODE CVMX_SLI_PKT_OUT_BMODE_FUNC()
 static inline uint64_t CVMX_SLI_PKT_OUT_BMODE_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_OUT_BMODE not supported on this chip\n");
 	return 0x00000000000010D0ull;
 }
@@ -812,10 +912,21 @@ static inline uint64_t CVMX_SLI_PKT_OUT_BMODE_FUNC(void)
 #define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_OUT_BP_EN CVMX_SLI_PKT_OUT_BP_EN_FUNC()
+static inline uint64_t CVMX_SLI_PKT_OUT_BP_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SLI_PKT_OUT_BP_EN not supported on this chip\n");
+	return 0x0000000000001240ull;
+}
+#else
+#define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_SLI_PKT_OUT_ENB CVMX_SLI_PKT_OUT_ENB_FUNC()
 static inline uint64_t CVMX_SLI_PKT_OUT_ENB_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_OUT_ENB not supported on this chip\n");
 	return 0x0000000000001010ull;
 }
@@ -826,7 +937,7 @@ static inline uint64_t CVMX_SLI_PKT_OUT_ENB_FUNC(void)
 #define CVMX_SLI_PKT_PCIE_PORT CVMX_SLI_PKT_PCIE_PORT_FUNC()
 static inline uint64_t CVMX_SLI_PKT_PCIE_PORT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_PCIE_PORT not supported on this chip\n");
 	return 0x00000000000010E0ull;
 }
@@ -837,7 +948,7 @@ static inline uint64_t CVMX_SLI_PKT_PCIE_PORT_FUNC(void)
 #define CVMX_SLI_PKT_PORT_IN_RST CVMX_SLI_PKT_PORT_IN_RST_FUNC()
 static inline uint64_t CVMX_SLI_PKT_PORT_IN_RST_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_PORT_IN_RST not supported on this chip\n");
 	return 0x00000000000011F0ull;
 }
@@ -848,7 +959,7 @@ static inline uint64_t CVMX_SLI_PKT_PORT_IN_RST_FUNC(void)
 #define CVMX_SLI_PKT_SLIST_ES CVMX_SLI_PKT_SLIST_ES_FUNC()
 static inline uint64_t CVMX_SLI_PKT_SLIST_ES_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_SLIST_ES not supported on this chip\n");
 	return 0x0000000000001050ull;
 }
@@ -859,7 +970,7 @@ static inline uint64_t CVMX_SLI_PKT_SLIST_ES_FUNC(void)
 #define CVMX_SLI_PKT_SLIST_NS CVMX_SLI_PKT_SLIST_NS_FUNC()
 static inline uint64_t CVMX_SLI_PKT_SLIST_NS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_SLIST_NS not supported on this chip\n");
 	return 0x0000000000001040ull;
 }
@@ -870,7 +981,7 @@ static inline uint64_t CVMX_SLI_PKT_SLIST_NS_FUNC(void)
 #define CVMX_SLI_PKT_SLIST_ROR CVMX_SLI_PKT_SLIST_ROR_FUNC()
 static inline uint64_t CVMX_SLI_PKT_SLIST_ROR_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_SLIST_ROR not supported on this chip\n");
 	return 0x0000000000001030ull;
 }
@@ -881,7 +992,7 @@ static inline uint64_t CVMX_SLI_PKT_SLIST_ROR_FUNC(void)
 #define CVMX_SLI_PKT_TIME_INT CVMX_SLI_PKT_TIME_INT_FUNC()
 static inline uint64_t CVMX_SLI_PKT_TIME_INT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_TIME_INT not supported on this chip\n");
 	return 0x0000000000001140ull;
 }
@@ -892,7 +1003,7 @@ static inline uint64_t CVMX_SLI_PKT_TIME_INT_FUNC(void)
 #define CVMX_SLI_PKT_TIME_INT_ENB CVMX_SLI_PKT_TIME_INT_ENB_FUNC()
 static inline uint64_t CVMX_SLI_PKT_TIME_INT_ENB_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_PKT_TIME_INT_ENB not supported on this chip\n");
 	return 0x0000000000001160ull;
 }
@@ -900,21 +1011,36 @@ static inline uint64_t CVMX_SLI_PKT_TIME_INT_ENB_FUNC(void)
 #define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_PORTX_PKIND(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_SLI_PORTX_PKIND(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000000800ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SLI_S2M_PORTX_CTL(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_SLI_S2M_PORTX_CTL(%lu) is invalid on this chip\n", offset);
-	return 0x0000000000003D80ull + ((offset) & 1) * 16;
+	return 0x0000000000003D80ull + ((offset) & 3) * 16;
 }
 #else
-#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 1) * 16)
+#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_SLI_SCRATCH_1 CVMX_SLI_SCRATCH_1_FUNC()
 static inline uint64_t CVMX_SLI_SCRATCH_1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_SCRATCH_1 not supported on this chip\n");
 	return 0x00000000000003C0ull;
 }
@@ -925,7 +1051,7 @@ static inline uint64_t CVMX_SLI_SCRATCH_1_FUNC(void)
 #define CVMX_SLI_SCRATCH_2 CVMX_SLI_SCRATCH_2_FUNC()
 static inline uint64_t CVMX_SLI_SCRATCH_2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_SCRATCH_2 not supported on this chip\n");
 	return 0x00000000000003D0ull;
 }
@@ -936,7 +1062,7 @@ static inline uint64_t CVMX_SLI_SCRATCH_2_FUNC(void)
 #define CVMX_SLI_STATE1 CVMX_SLI_STATE1_FUNC()
 static inline uint64_t CVMX_SLI_STATE1_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_STATE1 not supported on this chip\n");
 	return 0x0000000000000620ull;
 }
@@ -947,7 +1073,7 @@ static inline uint64_t CVMX_SLI_STATE1_FUNC(void)
 #define CVMX_SLI_STATE2 CVMX_SLI_STATE2_FUNC()
 static inline uint64_t CVMX_SLI_STATE2_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_STATE2 not supported on this chip\n");
 	return 0x0000000000000630ull;
 }
@@ -958,7 +1084,7 @@ static inline uint64_t CVMX_SLI_STATE2_FUNC(void)
 #define CVMX_SLI_STATE3 CVMX_SLI_STATE3_FUNC()
 static inline uint64_t CVMX_SLI_STATE3_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_STATE3 not supported on this chip\n");
 	return 0x0000000000000640ull;
 }
@@ -966,10 +1092,21 @@ static inline uint64_t CVMX_SLI_STATE3_FUNC(void)
 #define CVMX_SLI_STATE3 (0x0000000000000640ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_TX_PIPE CVMX_SLI_TX_PIPE_FUNC()
+static inline uint64_t CVMX_SLI_TX_PIPE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SLI_TX_PIPE not supported on this chip\n");
+	return 0x0000000000001230ull;
+}
+#else
+#define CVMX_SLI_TX_PIPE (0x0000000000001230ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_SLI_WINDOW_CTL CVMX_SLI_WINDOW_CTL_FUNC()
 static inline uint64_t CVMX_SLI_WINDOW_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_WINDOW_CTL not supported on this chip\n");
 	return 0x00000000000002E0ull;
 }
@@ -980,7 +1117,7 @@ static inline uint64_t CVMX_SLI_WINDOW_CTL_FUNC(void)
 #define CVMX_SLI_WIN_RD_ADDR CVMX_SLI_WIN_RD_ADDR_FUNC()
 static inline uint64_t CVMX_SLI_WIN_RD_ADDR_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_WIN_RD_ADDR not supported on this chip\n");
 	return 0x0000000000000010ull;
 }
@@ -991,7 +1128,7 @@ static inline uint64_t CVMX_SLI_WIN_RD_ADDR_FUNC(void)
 #define CVMX_SLI_WIN_RD_DATA CVMX_SLI_WIN_RD_DATA_FUNC()
 static inline uint64_t CVMX_SLI_WIN_RD_DATA_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_WIN_RD_DATA not supported on this chip\n");
 	return 0x0000000000000040ull;
 }
@@ -1002,7 +1139,7 @@ static inline uint64_t CVMX_SLI_WIN_RD_DATA_FUNC(void)
 #define CVMX_SLI_WIN_WR_ADDR CVMX_SLI_WIN_WR_ADDR_FUNC()
 static inline uint64_t CVMX_SLI_WIN_WR_ADDR_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_WIN_WR_ADDR not supported on this chip\n");
 	return 0x0000000000000000ull;
 }
@@ -1013,7 +1150,7 @@ static inline uint64_t CVMX_SLI_WIN_WR_ADDR_FUNC(void)
 #define CVMX_SLI_WIN_WR_DATA CVMX_SLI_WIN_WR_DATA_FUNC()
 static inline uint64_t CVMX_SLI_WIN_WR_DATA_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_WIN_WR_DATA not supported on this chip\n");
 	return 0x0000000000000020ull;
 }
@@ -1024,7 +1161,7 @@ static inline uint64_t CVMX_SLI_WIN_WR_DATA_FUNC(void)
 #define CVMX_SLI_WIN_WR_MASK CVMX_SLI_WIN_WR_MASK_FUNC()
 static inline uint64_t CVMX_SLI_WIN_WR_MASK_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SLI_WIN_WR_MASK not supported on this chip\n");
 	return 0x0000000000000030ull;
 }
@@ -1039,12 +1176,120 @@ static inline uint64_t CVMX_SLI_WIN_WR_MASK_FUNC(void)
  *
  * Results from BIST runs of SLI's memories.
  */
-union cvmx_sli_bist_status
-{
+union cvmx_sli_bist_status {
 	uint64_t u64;
-	struct cvmx_sli_bist_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t ncb_req                      : 1;  /**< BIST Status for NCB Request FIFO */
+	uint64_t n2p0_c                       : 1;  /**< BIST Status for N2P Port0 Cmd */
+	uint64_t n2p0_o                       : 1;  /**< BIST Status for N2P Port0 Data */
+	uint64_t n2p1_c                       : 1;  /**< BIST Status for N2P Port1 Cmd */
+	uint64_t n2p1_o                       : 1;  /**< BIST Status for N2P Port1 Data */
+	uint64_t cpl_p0                       : 1;  /**< BIST Status for CPL Port 0 */
+	uint64_t cpl_p1                       : 1;  /**< BIST Status for CPL Port 1 */
+	uint64_t reserved_19_24               : 6;
+	uint64_t p2n0_c0                      : 1;  /**< BIST Status for P2N Port0 C0 */
+	uint64_t p2n0_c1                      : 1;  /**< BIST Status for P2N Port0 C1 */
+	uint64_t p2n0_n                       : 1;  /**< BIST Status for P2N Port0 N */
+	uint64_t p2n0_p0                      : 1;  /**< BIST Status for P2N Port0 P0 */
+	uint64_t p2n0_p1                      : 1;  /**< BIST Status for P2N Port0 P1 */
+	uint64_t p2n1_c0                      : 1;  /**< BIST Status for P2N Port1 C0 */
+	uint64_t p2n1_c1                      : 1;  /**< BIST Status for P2N Port1 C1 */
+	uint64_t p2n1_n                       : 1;  /**< BIST Status for P2N Port1 N */
+	uint64_t p2n1_p0                      : 1;  /**< BIST Status for P2N Port1 P0 */
+	uint64_t p2n1_p1                      : 1;  /**< BIST Status for P2N Port1 P1 */
+	uint64_t reserved_6_8                 : 3;
+	uint64_t dsi1_1                       : 1;  /**< BIST Status for DSI1 Memory 1 */
+	uint64_t dsi1_0                       : 1;  /**< BIST Status for DSI1 Memory 0 */
+	uint64_t dsi0_1                       : 1;  /**< BIST Status for DSI0 Memory 1 */
+	uint64_t dsi0_0                       : 1;  /**< BIST Status for DSI0 Memory 0 */
+	uint64_t msi                          : 1;  /**< BIST Status for MSI Memory Map */
+	uint64_t ncb_cmd                      : 1;  /**< BIST Status for NCB Outbound Commands */
+#else
+	uint64_t ncb_cmd                      : 1;
+	uint64_t msi                          : 1;
+	uint64_t dsi0_0                       : 1;
+	uint64_t dsi0_1                       : 1;
+	uint64_t dsi1_0                       : 1;
+	uint64_t dsi1_1                       : 1;
+	uint64_t reserved_6_8                 : 3;
+	uint64_t p2n1_p1                      : 1;
+	uint64_t p2n1_p0                      : 1;
+	uint64_t p2n1_n                       : 1;
+	uint64_t p2n1_c1                      : 1;
+	uint64_t p2n1_c0                      : 1;
+	uint64_t p2n0_p1                      : 1;
+	uint64_t p2n0_p0                      : 1;
+	uint64_t p2n0_n                       : 1;
+	uint64_t p2n0_c1                      : 1;
+	uint64_t p2n0_c0                      : 1;
+	uint64_t reserved_19_24               : 6;
+	uint64_t cpl_p1                       : 1;
+	uint64_t cpl_p0                       : 1;
+	uint64_t n2p1_o                       : 1;
+	uint64_t n2p1_c                       : 1;
+	uint64_t n2p0_o                       : 1;
+	uint64_t n2p0_c                       : 1;
+	uint64_t ncb_req                      : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_bist_status_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_31_63               : 33;
+	uint64_t n2p0_c                       : 1;  /**< BIST Status for N2P Port0 Cmd */
+	uint64_t n2p0_o                       : 1;  /**< BIST Status for N2P Port0 Data */
+	uint64_t reserved_27_28               : 2;
+	uint64_t cpl_p0                       : 1;  /**< BIST Status for CPL Port 0 */
+	uint64_t cpl_p1                       : 1;  /**< BIST Status for CPL Port 1 */
+	uint64_t reserved_19_24               : 6;
+	uint64_t p2n0_c0                      : 1;  /**< BIST Status for P2N Port0 C0 */
+	uint64_t p2n0_c1                      : 1;  /**< BIST Status for P2N Port0 C1 */
+	uint64_t p2n0_n                       : 1;  /**< BIST Status for P2N Port0 N */
+	uint64_t p2n0_p0                      : 1;  /**< BIST Status for P2N Port0 P0 */
+	uint64_t p2n0_p1                      : 1;  /**< BIST Status for P2N Port0 P1 */
+	uint64_t p2n1_c0                      : 1;  /**< BIST Status for P2N Port1 C0 */
+	uint64_t p2n1_c1                      : 1;  /**< BIST Status for P2N Port1 C1 */
+	uint64_t p2n1_n                       : 1;  /**< BIST Status for P2N Port1 N */
+	uint64_t p2n1_p0                      : 1;  /**< BIST Status for P2N Port1 P0 */
+	uint64_t p2n1_p1                      : 1;  /**< BIST Status for P2N Port1 P1 */
+	uint64_t reserved_6_8                 : 3;
+	uint64_t dsi1_1                       : 1;  /**< BIST Status for DSI1 Memory 1 */
+	uint64_t dsi1_0                       : 1;  /**< BIST Status for DSI1 Memory 0 */
+	uint64_t dsi0_1                       : 1;  /**< BIST Status for DSI0 Memory 1 */
+	uint64_t dsi0_0                       : 1;  /**< BIST Status for DSI0 Memory 0 */
+	uint64_t msi                          : 1;  /**< BIST Status for MSI Memory Map */
+	uint64_t ncb_cmd                      : 1;  /**< BIST Status for NCB Outbound Commands */
+#else
+	uint64_t ncb_cmd                      : 1;
+	uint64_t msi                          : 1;
+	uint64_t dsi0_0                       : 1;
+	uint64_t dsi0_1                       : 1;
+	uint64_t dsi1_0                       : 1;
+	uint64_t dsi1_1                       : 1;
+	uint64_t reserved_6_8                 : 3;
+	uint64_t p2n1_p1                      : 1;
+	uint64_t p2n1_p0                      : 1;
+	uint64_t p2n1_n                       : 1;
+	uint64_t p2n1_c1                      : 1;
+	uint64_t p2n1_c0                      : 1;
+	uint64_t p2n0_p1                      : 1;
+	uint64_t p2n0_p0                      : 1;
+	uint64_t p2n0_n                       : 1;
+	uint64_t p2n0_c1                      : 1;
+	uint64_t p2n0_c0                      : 1;
+	uint64_t reserved_19_24               : 6;
+	uint64_t cpl_p1                       : 1;
+	uint64_t cpl_p0                       : 1;
+	uint64_t reserved_27_28               : 2;
+	uint64_t n2p0_o                       : 1;
+	uint64_t n2p0_c                       : 1;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} cn61xx;
+	struct cvmx_sli_bist_status_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t n2p0_c                       : 1;  /**< BIST Status for N2P Port0 Cmd */
 	uint64_t n2p0_o                       : 1;  /**< BIST Status for N2P Port0 Data */
@@ -1097,9 +1342,12 @@ union cvmx_sli_bist_status
 	uint64_t n2p0_c                       : 1;
 	uint64_t reserved_31_63               : 33;
 #endif
-	} s;
-	struct cvmx_sli_bist_status_s         cn63xx;
-	struct cvmx_sli_bist_status_s         cn63xxp1;
+	} cn63xx;
+	struct cvmx_sli_bist_status_cn63xx    cn63xxp1;
+	struct cvmx_sli_bist_status_cn61xx    cn66xx;
+	struct cvmx_sli_bist_status_s         cn68xx;
+	struct cvmx_sli_bist_status_s         cn68xxp1;
+	struct cvmx_sli_bist_status_cn61xx    cnf71xx;
 };
 typedef union cvmx_sli_bist_status cvmx_sli_bist_status_t;
 
@@ -1110,12 +1358,10 @@ typedef union cvmx_sli_bist_status cvmx_sli_bist_status_t;
  *
  * Contains control for access for Port0
  */
-union cvmx_sli_ctl_portx
-{
+union cvmx_sli_ctl_portx {
 	uint64_t u64;
-	struct cvmx_sli_ctl_portx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_ctl_portx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_22_63               : 42;
 	uint64_t intd                         : 1;  /**< When '0' Intd wire asserted. Before mapping. */
 	uint64_t intc                         : 1;  /**< When '0' Intc wire asserted. Before mapping. */
@@ -1173,8 +1419,13 @@ union cvmx_sli_ctl_portx
 	uint64_t reserved_22_63               : 42;
 #endif
 	} s;
+	struct cvmx_sli_ctl_portx_s           cn61xx;
 	struct cvmx_sli_ctl_portx_s           cn63xx;
 	struct cvmx_sli_ctl_portx_s           cn63xxp1;
+	struct cvmx_sli_ctl_portx_s           cn66xx;
+	struct cvmx_sli_ctl_portx_s           cn68xx;
+	struct cvmx_sli_ctl_portx_s           cn68xxp1;
+	struct cvmx_sli_ctl_portx_s           cnf71xx;
 };
 typedef union cvmx_sli_ctl_portx cvmx_sli_ctl_portx_t;
 
@@ -1187,12 +1438,10 @@ typedef union cvmx_sli_ctl_portx cvmx_sli_ctl_portx_t;
  * To ensure that a write has completed the user must read the register before making an access(i.e. MAC memory space)
  * that requires the value of this register to be updated.
  */
-union cvmx_sli_ctl_status
-{
+union cvmx_sli_ctl_status {
 	uint64_t u64;
-	struct cvmx_sli_ctl_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t p1_ntags                     : 6;  /**< Number of tags available for MAC Port1.
                                                          In RC mode 1 tag is needed for each outbound TLP
@@ -1202,11 +1451,9 @@ union cvmx_sli_ctl_status
                                                          This field should only be written as part of
                                                          reset sequence, before issuing any reads, CFGs, or
                                                          IO transactions from the core(s). */
-	uint64_t p0_ntags                     : 6;  /**< Number of tags available for MAC Port0.
-                                                         In RC mode 1 tag is needed for each outbound TLP
-                                                         that requires a CPL TLP. In Endpoint mode the
-                                                         number of tags required for a TLP request is
-                                                         1 per 64-bytes of CPL data + 1.
+	uint64_t p0_ntags                     : 6;  /**< Number of tags available for outbound TLPs to the
+                                                         MACS. One tag is needed for each outbound TLP that
+                                                         requires a CPL TLP.
                                                          This field should only be written as part of
                                                          reset sequence, before issuing any reads, CFGs, or
                                                          IO transactions from the core(s). */
@@ -1218,8 +1465,28 @@ union cvmx_sli_ctl_status
 	uint64_t reserved_20_63               : 44;
 #endif
 	} s;
+	struct cvmx_sli_ctl_status_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_14_63               : 50;
+	uint64_t p0_ntags                     : 6;  /**< Number of tags available for outbound TLPs to the
+                                                         MACS. One tag is needed for each outbound TLP that
+                                                         requires a CPL TLP.
+                                                         This field should only be written as part of
+                                                         reset sequence, before issuing any reads, CFGs, or
+                                                         IO transactions from the core(s). */
+	uint64_t chip_rev                     : 8;  /**< The chip revision. */
+#else
+	uint64_t chip_rev                     : 8;
+	uint64_t p0_ntags                     : 6;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} cn61xx;
 	struct cvmx_sli_ctl_status_s          cn63xx;
 	struct cvmx_sli_ctl_status_s          cn63xxp1;
+	struct cvmx_sli_ctl_status_cn61xx     cn66xx;
+	struct cvmx_sli_ctl_status_s          cn68xx;
+	struct cvmx_sli_ctl_status_s          cn68xxp1;
+	struct cvmx_sli_ctl_status_cn61xx     cnf71xx;
 };
 typedef union cvmx_sli_ctl_status cvmx_sli_ctl_status_t;
 
@@ -1230,27 +1497,25 @@ typedef union cvmx_sli_ctl_status cvmx_sli_ctl_status_t;
  *
  * The EXEC data out fifo-count and the data unload counter.
  */
-union cvmx_sli_data_out_cnt
-{
+union cvmx_sli_data_out_cnt {
 	uint64_t u64;
-	struct cvmx_sli_data_out_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_data_out_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_44_63               : 20;
-	uint64_t p1_ucnt                      : 16; /**< MAC Port1 Fifo Unload Count. This counter is
+	uint64_t p1_ucnt                      : 16; /**< SLI Order-FIFO1 Fifo Unload Count. This counter is
                                                          incremented by '1' every time a word is removed
                                                          from the Data Out FIFO, whose count is shown in
-                                                         P0_FCNT. */
-	uint64_t p1_fcnt                      : 6;  /**< MAC Port1 Data Out Fifo Count. Number of address
-                                                         data words to be sent out the MAC port presently
-                                                         buffered in the FIFO. */
-	uint64_t p0_ucnt                      : 16; /**< MAC Port0 Fifo Unload Count. This counter is
+                                                         P1_FCNT. */
+	uint64_t p1_fcnt                      : 6;  /**< SLI Order-FIFO1 Data Out Fifo Count. Number of
+                                                         address data words to be sent out the Order-FIFO
+                                                         presently buffered in the FIFO. */
+	uint64_t p0_ucnt                      : 16; /**< SLI Order-FIFO0 Fifo Unload Count. This counter is
                                                          incremented by '1' every time a word is removed
                                                          from the Data Out FIFO, whose count is shown in
                                                          P0_FCNT. */
-	uint64_t p0_fcnt                      : 6;  /**< MAC Port0 Data Out Fifo Count. Number of address
-                                                         data words to be sent out the MAC port presently
-                                                         buffered in the FIFO. */
+	uint64_t p0_fcnt                      : 6;  /**< SLI Order-FIFO0 Data Out Fifo Count. Number of
+                                                         address data words to be sent out the Order-FIFO
+                                                         presently buffered in the FIFO. */
 #else
 	uint64_t p0_fcnt                      : 6;
 	uint64_t p0_ucnt                      : 16;
@@ -1259,8 +1524,13 @@ union cvmx_sli_data_out_cnt
 	uint64_t reserved_44_63               : 20;
 #endif
 	} s;
+	struct cvmx_sli_data_out_cnt_s        cn61xx;
 	struct cvmx_sli_data_out_cnt_s        cn63xx;
 	struct cvmx_sli_data_out_cnt_s        cn63xxp1;
+	struct cvmx_sli_data_out_cnt_s        cn66xx;
+	struct cvmx_sli_data_out_cnt_s        cn68xx;
+	struct cvmx_sli_data_out_cnt_s        cn68xxp1;
+	struct cvmx_sli_data_out_cnt_s        cnf71xx;
 };
 typedef union cvmx_sli_data_out_cnt cvmx_sli_data_out_cnt_t;
 
@@ -1271,12 +1541,10 @@ typedef union cvmx_sli_data_out_cnt cvmx_sli_data_out_cnt_t;
  *
  * Value returned on the debug-data lines from the RSLs
  */
-union cvmx_sli_dbg_data
-{
+union cvmx_sli_dbg_data {
 	uint64_t u64;
-	struct cvmx_sli_dbg_data_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_dbg_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t dsel_ext                     : 1;  /**< Allows changes in the external pins to set the
                                                          debug select value. */
@@ -1287,8 +1555,13 @@ union cvmx_sli_dbg_data
 	uint64_t reserved_18_63               : 46;
 #endif
 	} s;
+	struct cvmx_sli_dbg_data_s            cn61xx;
 	struct cvmx_sli_dbg_data_s            cn63xx;
 	struct cvmx_sli_dbg_data_s            cn63xxp1;
+	struct cvmx_sli_dbg_data_s            cn66xx;
+	struct cvmx_sli_dbg_data_s            cn68xx;
+	struct cvmx_sli_dbg_data_s            cn68xxp1;
+	struct cvmx_sli_dbg_data_s            cnf71xx;
 };
 typedef union cvmx_sli_dbg_data cvmx_sli_dbg_data_t;
 
@@ -1299,12 +1572,10 @@ typedef union cvmx_sli_dbg_data cvmx_sli_dbg_data_t;
  *
  * Contains the debug select value last written to the RSLs.
  */
-union cvmx_sli_dbg_select
-{
+union cvmx_sli_dbg_select {
 	uint64_t u64;
-	struct cvmx_sli_dbg_select_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_dbg_select_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_33_63               : 31;
 	uint64_t adbg_sel                     : 1;  /**< When set '1' the SLI_DBG_DATA[DATA] will only be
                                                          loaded when SLI_DBG_DATA[DATA] bit [16] is a '1'.
@@ -1328,8 +1599,13 @@ union cvmx_sli_dbg_select
 	uint64_t reserved_33_63               : 31;
 #endif
 	} s;
+	struct cvmx_sli_dbg_select_s          cn61xx;
 	struct cvmx_sli_dbg_select_s          cn63xx;
 	struct cvmx_sli_dbg_select_s          cn63xxp1;
+	struct cvmx_sli_dbg_select_s          cn66xx;
+	struct cvmx_sli_dbg_select_s          cn68xx;
+	struct cvmx_sli_dbg_select_s          cn68xxp1;
+	struct cvmx_sli_dbg_select_s          cnf71xx;
 };
 typedef union cvmx_sli_dbg_select cvmx_sli_dbg_select_t;
 
@@ -1340,12 +1616,10 @@ typedef union cvmx_sli_dbg_select cvmx_sli_dbg_select_t;
  *
  * The DMA Count value.
  */
-union cvmx_sli_dmax_cnt
-{
+union cvmx_sli_dmax_cnt {
 	uint64_t u64;
-	struct cvmx_sli_dmax_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_dmax_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< The DMA counter.
                                                          Writing this field will cause the written value
@@ -1359,8 +1633,13 @@ union cvmx_sli_dmax_cnt
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_dmax_cnt_s            cn61xx;
 	struct cvmx_sli_dmax_cnt_s            cn63xx;
 	struct cvmx_sli_dmax_cnt_s            cn63xxp1;
+	struct cvmx_sli_dmax_cnt_s            cn66xx;
+	struct cvmx_sli_dmax_cnt_s            cn68xx;
+	struct cvmx_sli_dmax_cnt_s            cn68xxp1;
+	struct cvmx_sli_dmax_cnt_s            cnf71xx;
 };
 typedef union cvmx_sli_dmax_cnt cvmx_sli_dmax_cnt_t;
 
@@ -1371,12 +1650,10 @@ typedef union cvmx_sli_dmax_cnt cvmx_sli_dmax_cnt_t;
  *
  * Thresholds for DMA count and timer interrupts.
  */
-union cvmx_sli_dmax_int_level
-{
+union cvmx_sli_dmax_int_level {
 	uint64_t u64;
-	struct cvmx_sli_dmax_int_level_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_dmax_int_level_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t time                         : 32; /**< Whenever the SLI_DMAx_TIM[TIM] timer exceeds
                                                          this value, SLI_INT_SUM[DTIME<x>] is set.
                                                          The SLI_DMAx_TIM[TIM] timer increments every SLI
@@ -1390,8 +1667,13 @@ union cvmx_sli_dmax_int_level
 	uint64_t time                         : 32;
 #endif
 	} s;
+	struct cvmx_sli_dmax_int_level_s      cn61xx;
 	struct cvmx_sli_dmax_int_level_s      cn63xx;
 	struct cvmx_sli_dmax_int_level_s      cn63xxp1;
+	struct cvmx_sli_dmax_int_level_s      cn66xx;
+	struct cvmx_sli_dmax_int_level_s      cn68xx;
+	struct cvmx_sli_dmax_int_level_s      cn68xxp1;
+	struct cvmx_sli_dmax_int_level_s      cnf71xx;
 };
 typedef union cvmx_sli_dmax_int_level cvmx_sli_dmax_int_level_t;
 
@@ -1402,12 +1684,10 @@ typedef union cvmx_sli_dmax_int_level cvmx_sli_dmax_int_level_t;
  *
  * The DMA Timer value.
  */
-union cvmx_sli_dmax_tim
-{
+union cvmx_sli_dmax_tim {
 	uint64_t u64;
-	struct cvmx_sli_dmax_tim_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_dmax_tim_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t tim                          : 32; /**< The DMA timer value.
                                                          The timer will increment when SLI_DMAx_CNT[CNT]!=0
@@ -1417,8 +1697,13 @@ union cvmx_sli_dmax_tim
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_dmax_tim_s            cn61xx;
 	struct cvmx_sli_dmax_tim_s            cn63xx;
 	struct cvmx_sli_dmax_tim_s            cn63xxp1;
+	struct cvmx_sli_dmax_tim_s            cn66xx;
+	struct cvmx_sli_dmax_tim_s            cn68xx;
+	struct cvmx_sli_dmax_tim_s            cn68xxp1;
+	struct cvmx_sli_dmax_tim_s            cnf71xx;
 };
 typedef union cvmx_sli_dmax_tim cvmx_sli_dmax_tim_t;
 
@@ -1429,12 +1714,236 @@ typedef union cvmx_sli_dmax_tim cvmx_sli_dmax_tim_t;
  *
  * Used to enable the various interrupting conditions of SLI
  */
-union cvmx_sli_int_enb_ciu
-{
+union cvmx_sli_int_enb_ciu {
 	uint64_t u64;
-	struct cvmx_sli_int_enb_ciu_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_int_enb_ciu_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_62_63               : 2;
+	uint64_t pipe_err                     : 1;  /**< Illegal packet csr address. */
+	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
+	uint64_t sprt3_err                    : 1;  /**< Error Response received on SLI port 3. */
+	uint64_t sprt2_err                    : 1;  /**< Error Response received on SLI port 2. */
+	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
+	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
+	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
+	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
+	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
+	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
+	uint64_t pin_bp                       : 1;  /**< Packet Input Count exceeded WMARK. */
+	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
+	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
+	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
+	uint64_t reserved_38_47               : 10;
+	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
+	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
+	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
+	uint64_t reserved_28_31               : 4;
+	uint64_t m3_un_wi                     : 1;  /**< Reserved. */
+	uint64_t m3_un_b0                     : 1;  /**< Reserved. */
+	uint64_t m3_up_wi                     : 1;  /**< Reserved. */
+	uint64_t m3_up_b0                     : 1;  /**< Reserved. */
+	uint64_t m2_un_wi                     : 1;  /**< Reserved. */
+	uint64_t m2_un_b0                     : 1;  /**< Reserved. */
+	uint64_t m2_up_wi                     : 1;  /**< Reserved. */
+	uint64_t m2_up_b0                     : 1;  /**< Reserved. */
+	uint64_t reserved_18_19               : 2;
+	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
+                                                         interrupt on the RSL.
+                                                         THIS SHOULD NEVER BE SET */
+	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
+                                                         interrupt on the RSL.
+                                                         THIS SHOULD NEVER BE SET */
+	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
+                                                         interrupt on the RSL. */
+#else
+	uint64_t rml_to                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t m0_up_b0                     : 1;
+	uint64_t m0_up_wi                     : 1;
+	uint64_t m0_un_b0                     : 1;
+	uint64_t m0_un_wi                     : 1;
+	uint64_t m1_up_b0                     : 1;
+	uint64_t m1_up_wi                     : 1;
+	uint64_t m1_un_b0                     : 1;
+	uint64_t m1_un_wi                     : 1;
+	uint64_t mio_int0                     : 1;
+	uint64_t mio_int1                     : 1;
+	uint64_t reserved_18_19               : 2;
+	uint64_t m2_up_b0                     : 1;
+	uint64_t m2_up_wi                     : 1;
+	uint64_t m2_un_b0                     : 1;
+	uint64_t m2_un_wi                     : 1;
+	uint64_t m3_up_b0                     : 1;
+	uint64_t m3_up_wi                     : 1;
+	uint64_t m3_un_b0                     : 1;
+	uint64_t m3_un_wi                     : 1;
+	uint64_t reserved_28_31               : 4;
+	uint64_t dmafi                        : 2;
+	uint64_t dcnt                         : 2;
+	uint64_t dtime                        : 2;
+	uint64_t reserved_38_47               : 10;
+	uint64_t pidbof                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pout_err                     : 1;
+	uint64_t pin_bp                       : 1;
+	uint64_t pgl_err                      : 1;
+	uint64_t pdi_err                      : 1;
+	uint64_t pop_err                      : 1;
+	uint64_t pins_err                     : 1;
+	uint64_t sprt0_err                    : 1;
+	uint64_t sprt1_err                    : 1;
+	uint64_t sprt2_err                    : 1;
+	uint64_t sprt3_err                    : 1;
+	uint64_t ill_pad                      : 1;
+	uint64_t pipe_err                     : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} s;
+	struct cvmx_sli_int_enb_ciu_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_61_63               : 3;
+	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
+	uint64_t sprt3_err                    : 1;  /**< Error Response received on SLI port 3. */
+	uint64_t sprt2_err                    : 1;  /**< Error Response received on SLI port 2. */
+	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
+	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
+	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
+	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
+	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
+	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
+	uint64_t pin_bp                       : 1;  /**< Packet Input Count exceeded WMARK. */
+	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
+	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
+	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
+	uint64_t reserved_38_47               : 10;
+	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
+	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
+	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
+	uint64_t reserved_28_31               : 4;
+	uint64_t m3_un_wi                     : 1;  /**< Reserved. */
+	uint64_t m3_un_b0                     : 1;  /**< Reserved. */
+	uint64_t m3_up_wi                     : 1;  /**< Reserved. */
+	uint64_t m3_up_b0                     : 1;  /**< Reserved. */
+	uint64_t m2_un_wi                     : 1;  /**< Reserved. */
+	uint64_t m2_un_b0                     : 1;  /**< Reserved. */
+	uint64_t m2_up_wi                     : 1;  /**< Reserved. */
+	uint64_t m2_up_b0                     : 1;  /**< Reserved. */
+	uint64_t reserved_18_19               : 2;
+	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
+                                                         interrupt on the RSL.
+                                                         THIS SHOULD NEVER BE SET */
+	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
+                                                         interrupt on the RSL.
+                                                         THIS SHOULD NEVER BE SET */
+	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
+                                                         interrupt on the RSL. */
+#else
+	uint64_t rml_to                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t m0_up_b0                     : 1;
+	uint64_t m0_up_wi                     : 1;
+	uint64_t m0_un_b0                     : 1;
+	uint64_t m0_un_wi                     : 1;
+	uint64_t m1_up_b0                     : 1;
+	uint64_t m1_up_wi                     : 1;
+	uint64_t m1_un_b0                     : 1;
+	uint64_t m1_un_wi                     : 1;
+	uint64_t mio_int0                     : 1;
+	uint64_t mio_int1                     : 1;
+	uint64_t reserved_18_19               : 2;
+	uint64_t m2_up_b0                     : 1;
+	uint64_t m2_up_wi                     : 1;
+	uint64_t m2_un_b0                     : 1;
+	uint64_t m2_un_wi                     : 1;
+	uint64_t m3_up_b0                     : 1;
+	uint64_t m3_up_wi                     : 1;
+	uint64_t m3_un_b0                     : 1;
+	uint64_t m3_un_wi                     : 1;
+	uint64_t reserved_28_31               : 4;
+	uint64_t dmafi                        : 2;
+	uint64_t dcnt                         : 2;
+	uint64_t dtime                        : 2;
+	uint64_t reserved_38_47               : 10;
+	uint64_t pidbof                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pout_err                     : 1;
+	uint64_t pin_bp                       : 1;
+	uint64_t pgl_err                      : 1;
+	uint64_t pdi_err                      : 1;
+	uint64_t pop_err                      : 1;
+	uint64_t pins_err                     : 1;
+	uint64_t sprt0_err                    : 1;
+	uint64_t sprt1_err                    : 1;
+	uint64_t sprt2_err                    : 1;
+	uint64_t sprt3_err                    : 1;
+	uint64_t ill_pad                      : 1;
+	uint64_t reserved_61_63               : 3;
+#endif
+	} cn61xx;
+	struct cvmx_sli_int_enb_ciu_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_61_63               : 3;
 	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
 	uint64_t reserved_58_59               : 2;
@@ -1524,9 +2033,105 @@ union cvmx_sli_int_enb_ciu
 	uint64_t ill_pad                      : 1;
 	uint64_t reserved_61_63               : 3;
 #endif
-	} s;
-	struct cvmx_sli_int_enb_ciu_s         cn63xx;
-	struct cvmx_sli_int_enb_ciu_s         cn63xxp1;
+	} cn63xx;
+	struct cvmx_sli_int_enb_ciu_cn63xx    cn63xxp1;
+	struct cvmx_sli_int_enb_ciu_cn61xx    cn66xx;
+	struct cvmx_sli_int_enb_ciu_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_62_63               : 2;
+	uint64_t pipe_err                     : 1;  /**< Illegal packet csr address. */
+	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
+	uint64_t reserved_58_59               : 2;
+	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
+	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
+	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
+	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
+	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
+	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
+	uint64_t reserved_51_51               : 1;
+	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
+	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
+	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
+	uint64_t reserved_38_47               : 10;
+	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
+	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
+	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
+	uint64_t reserved_18_31               : 14;
+	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
+                                                         interrupt on the RSL.
+                                                         THIS SHOULD NEVER BE SET */
+	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
+                                                         interrupt on the RSL.
+                                                         THIS SHOULD NEVER BE SET */
+	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
+                                                         interrupt on the RSL. */
+#else
+	uint64_t rml_to                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t m0_up_b0                     : 1;
+	uint64_t m0_up_wi                     : 1;
+	uint64_t m0_un_b0                     : 1;
+	uint64_t m0_un_wi                     : 1;
+	uint64_t m1_up_b0                     : 1;
+	uint64_t m1_up_wi                     : 1;
+	uint64_t m1_un_b0                     : 1;
+	uint64_t m1_un_wi                     : 1;
+	uint64_t mio_int0                     : 1;
+	uint64_t mio_int1                     : 1;
+	uint64_t reserved_18_31               : 14;
+	uint64_t dmafi                        : 2;
+	uint64_t dcnt                         : 2;
+	uint64_t dtime                        : 2;
+	uint64_t reserved_38_47               : 10;
+	uint64_t pidbof                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pout_err                     : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t pgl_err                      : 1;
+	uint64_t pdi_err                      : 1;
+	uint64_t pop_err                      : 1;
+	uint64_t pins_err                     : 1;
+	uint64_t sprt0_err                    : 1;
+	uint64_t sprt1_err                    : 1;
+	uint64_t reserved_58_59               : 2;
+	uint64_t ill_pad                      : 1;
+	uint64_t pipe_err                     : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} cn68xx;
+	struct cvmx_sli_int_enb_ciu_cn68xx    cn68xxp1;
+	struct cvmx_sli_int_enb_ciu_cn61xx    cnf71xx;
 };
 typedef union cvmx_sli_int_enb_ciu cvmx_sli_int_enb_ciu_t;
 
@@ -1541,12 +2146,252 @@ typedef union cvmx_sli_int_enb_ciu cvmx_sli_int_enb_ciu_t;
  * This CSR is not used when the corresponding MAC is sRIO.
  *
  */
-union cvmx_sli_int_enb_portx
-{
+union cvmx_sli_int_enb_portx {
 	uint64_t u64;
-	struct cvmx_sli_int_enb_portx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_int_enb_portx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_62_63               : 2;
+	uint64_t pipe_err                     : 1;  /**< Out of range PIPE value. */
+	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
+	uint64_t sprt3_err                    : 1;  /**< Error Response received on SLI port 3. */
+	uint64_t sprt2_err                    : 1;  /**< Error Response received on SLI port 2. */
+	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
+	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
+	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
+	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
+	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
+	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
+	uint64_t pin_bp                       : 1;  /**< Packet Input Count exceeded WMARK. */
+	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
+	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
+	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
+	uint64_t reserved_38_47               : 10;
+	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
+	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
+	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
+	uint64_t reserved_28_31               : 4;
+	uint64_t m3_un_wi                     : 1;  /**< Reserved. */
+	uint64_t m3_un_b0                     : 1;  /**< Reserved. */
+	uint64_t m3_up_wi                     : 1;  /**< Reserved. */
+	uint64_t m3_up_b0                     : 1;  /**< Reserved. */
+	uint64_t m2_un_wi                     : 1;  /**< Reserved. */
+	uint64_t m2_un_b0                     : 1;  /**< Reserved. */
+	uint64_t m2_up_wi                     : 1;  /**< Reserved. */
+	uint64_t m2_up_b0                     : 1;  /**< Reserved. */
+	uint64_t mac1_int                     : 1;  /**< Enables SLI_INT_SUM[19] to generate an
+                                                         interrupt to the PCIE-Port1 for MSI/inta.
+                                                         The valuse of this bit has NO effect on PCIE Port0.
+                                                         SLI_INT_ENB_PORT0[MAC1_INT] sould NEVER be set. */
+	uint64_t mac0_int                     : 1;  /**< Enables SLI_INT_SUM[18] to generate an
+                                                         interrupt to the PCIE-Port0 for MSI/inta.
+                                                         The valus of this bit has NO effect on PCIE Port1.
+                                                         SLI_INT_ENB_PORT1[MAC0_INT] sould NEVER be set. */
+	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
+                                                         interrupt to the PCIE core for MSI/inta.
+                                                         SLI_INT_ENB_PORT0[MIO_INT1] should NEVER be set. */
+	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
+                                                         interrupt to the PCIE core for MSI/inta.
+                                                         SLI_INT_ENB_PORT1[MIO_INT0] should NEVER be set. */
+	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+#else
+	uint64_t rml_to                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t m0_up_b0                     : 1;
+	uint64_t m0_up_wi                     : 1;
+	uint64_t m0_un_b0                     : 1;
+	uint64_t m0_un_wi                     : 1;
+	uint64_t m1_up_b0                     : 1;
+	uint64_t m1_up_wi                     : 1;
+	uint64_t m1_un_b0                     : 1;
+	uint64_t m1_un_wi                     : 1;
+	uint64_t mio_int0                     : 1;
+	uint64_t mio_int1                     : 1;
+	uint64_t mac0_int                     : 1;
+	uint64_t mac1_int                     : 1;
+	uint64_t m2_up_b0                     : 1;
+	uint64_t m2_up_wi                     : 1;
+	uint64_t m2_un_b0                     : 1;
+	uint64_t m2_un_wi                     : 1;
+	uint64_t m3_up_b0                     : 1;
+	uint64_t m3_up_wi                     : 1;
+	uint64_t m3_un_b0                     : 1;
+	uint64_t m3_un_wi                     : 1;
+	uint64_t reserved_28_31               : 4;
+	uint64_t dmafi                        : 2;
+	uint64_t dcnt                         : 2;
+	uint64_t dtime                        : 2;
+	uint64_t reserved_38_47               : 10;
+	uint64_t pidbof                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pout_err                     : 1;
+	uint64_t pin_bp                       : 1;
+	uint64_t pgl_err                      : 1;
+	uint64_t pdi_err                      : 1;
+	uint64_t pop_err                      : 1;
+	uint64_t pins_err                     : 1;
+	uint64_t sprt0_err                    : 1;
+	uint64_t sprt1_err                    : 1;
+	uint64_t sprt2_err                    : 1;
+	uint64_t sprt3_err                    : 1;
+	uint64_t ill_pad                      : 1;
+	uint64_t pipe_err                     : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} s;
+	struct cvmx_sli_int_enb_portx_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_61_63               : 3;
+	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
+	uint64_t sprt3_err                    : 1;  /**< Error Response received on SLI port 3. */
+	uint64_t sprt2_err                    : 1;  /**< Error Response received on SLI port 2. */
+	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
+	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
+	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
+	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
+	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
+	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
+	uint64_t pin_bp                       : 1;  /**< Packet Input Count exceeded WMARK. */
+	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
+	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
+	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
+	uint64_t reserved_38_47               : 10;
+	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
+	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
+	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
+	uint64_t reserved_28_31               : 4;
+	uint64_t m3_un_wi                     : 1;  /**< Reserved. */
+	uint64_t m3_un_b0                     : 1;  /**< Reserved. */
+	uint64_t m3_up_wi                     : 1;  /**< Reserved. */
+	uint64_t m3_up_b0                     : 1;  /**< Reserved. */
+	uint64_t m2_un_wi                     : 1;  /**< Reserved. */
+	uint64_t m2_un_b0                     : 1;  /**< Reserved. */
+	uint64_t m2_up_wi                     : 1;  /**< Reserved. */
+	uint64_t m2_up_b0                     : 1;  /**< Reserved. */
+	uint64_t mac1_int                     : 1;  /**< Enables SLI_INT_SUM[19] to generate an
+                                                         interrupt to the PCIE-Port1 for MSI/inta.
+                                                         The valuse of this bit has NO effect on PCIE Port0.
+                                                         SLI_INT_ENB_PORT0[MAC1_INT] sould NEVER be set. */
+	uint64_t mac0_int                     : 1;  /**< Enables SLI_INT_SUM[18] to generate an
+                                                         interrupt to the PCIE-Port0 for MSI/inta.
+                                                         The valus of this bit has NO effect on PCIE Port1.
+                                                         SLI_INT_ENB_PORT1[MAC0_INT] sould NEVER be set. */
+	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
+                                                         interrupt to the PCIE core for MSI/inta.
+                                                         SLI_INT_ENB_PORT0[MIO_INT1] should NEVER be set. */
+	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
+                                                         interrupt to the PCIE core for MSI/inta.
+                                                         SLI_INT_ENB_PORT1[MIO_INT0] should NEVER be set. */
+	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+#else
+	uint64_t rml_to                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t m0_up_b0                     : 1;
+	uint64_t m0_up_wi                     : 1;
+	uint64_t m0_un_b0                     : 1;
+	uint64_t m0_un_wi                     : 1;
+	uint64_t m1_up_b0                     : 1;
+	uint64_t m1_up_wi                     : 1;
+	uint64_t m1_un_b0                     : 1;
+	uint64_t m1_un_wi                     : 1;
+	uint64_t mio_int0                     : 1;
+	uint64_t mio_int1                     : 1;
+	uint64_t mac0_int                     : 1;
+	uint64_t mac1_int                     : 1;
+	uint64_t m2_up_b0                     : 1;
+	uint64_t m2_up_wi                     : 1;
+	uint64_t m2_un_b0                     : 1;
+	uint64_t m2_un_wi                     : 1;
+	uint64_t m3_up_b0                     : 1;
+	uint64_t m3_up_wi                     : 1;
+	uint64_t m3_un_b0                     : 1;
+	uint64_t m3_un_wi                     : 1;
+	uint64_t reserved_28_31               : 4;
+	uint64_t dmafi                        : 2;
+	uint64_t dcnt                         : 2;
+	uint64_t dtime                        : 2;
+	uint64_t reserved_38_47               : 10;
+	uint64_t pidbof                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pout_err                     : 1;
+	uint64_t pin_bp                       : 1;
+	uint64_t pgl_err                      : 1;
+	uint64_t pdi_err                      : 1;
+	uint64_t pop_err                      : 1;
+	uint64_t pins_err                     : 1;
+	uint64_t sprt0_err                    : 1;
+	uint64_t sprt1_err                    : 1;
+	uint64_t sprt2_err                    : 1;
+	uint64_t sprt3_err                    : 1;
+	uint64_t ill_pad                      : 1;
+	uint64_t reserved_61_63               : 3;
+#endif
+	} cn61xx;
+	struct cvmx_sli_int_enb_portx_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_61_63               : 3;
 	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
 	uint64_t reserved_58_59               : 2;
@@ -1646,9 +2491,115 @@ union cvmx_sli_int_enb_portx
 	uint64_t ill_pad                      : 1;
 	uint64_t reserved_61_63               : 3;
 #endif
-	} s;
-	struct cvmx_sli_int_enb_portx_s       cn63xx;
-	struct cvmx_sli_int_enb_portx_s       cn63xxp1;
+	} cn63xx;
+	struct cvmx_sli_int_enb_portx_cn63xx  cn63xxp1;
+	struct cvmx_sli_int_enb_portx_cn61xx  cn66xx;
+	struct cvmx_sli_int_enb_portx_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_62_63               : 2;
+	uint64_t pipe_err                     : 1;  /**< Out of range PIPE value. */
+	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
+	uint64_t reserved_58_59               : 2;
+	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
+	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
+	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
+	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
+	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
+	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
+	uint64_t reserved_51_51               : 1;
+	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
+	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
+	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
+	uint64_t reserved_38_47               : 10;
+	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
+	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
+	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
+	uint64_t reserved_20_31               : 12;
+	uint64_t mac1_int                     : 1;  /**< Enables SLI_INT_SUM[19] to generate an
+                                                         interrupt to the PCIE-Port1 for MSI/inta.
+                                                         The valuse of this bit has NO effect on PCIE Port0.
+                                                         SLI_INT_ENB_PORT0[MAC1_INT] sould NEVER be set. */
+	uint64_t mac0_int                     : 1;  /**< Enables SLI_INT_SUM[18] to generate an
+                                                         interrupt to the PCIE-Port0 for MSI/inta.
+                                                         The valus of this bit has NO effect on PCIE Port1.
+                                                         SLI_INT_ENB_PORT1[MAC0_INT] sould NEVER be set. */
+	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
+                                                         interrupt to the PCIE core for MSI/inta.
+                                                         SLI_INT_ENB_PORT0[MIO_INT1] should NEVER be set. */
+	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
+                                                         interrupt to the PCIE core for MSI/inta.
+                                                         SLI_INT_ENB_PORT1[MIO_INT0] should NEVER be set. */
+	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+#else
+	uint64_t rml_to                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t m0_up_b0                     : 1;
+	uint64_t m0_up_wi                     : 1;
+	uint64_t m0_un_b0                     : 1;
+	uint64_t m0_un_wi                     : 1;
+	uint64_t m1_up_b0                     : 1;
+	uint64_t m1_up_wi                     : 1;
+	uint64_t m1_un_b0                     : 1;
+	uint64_t m1_un_wi                     : 1;
+	uint64_t mio_int0                     : 1;
+	uint64_t mio_int1                     : 1;
+	uint64_t mac0_int                     : 1;
+	uint64_t mac1_int                     : 1;
+	uint64_t reserved_20_31               : 12;
+	uint64_t dmafi                        : 2;
+	uint64_t dcnt                         : 2;
+	uint64_t dtime                        : 2;
+	uint64_t reserved_38_47               : 10;
+	uint64_t pidbof                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pout_err                     : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t pgl_err                      : 1;
+	uint64_t pdi_err                      : 1;
+	uint64_t pop_err                      : 1;
+	uint64_t pins_err                     : 1;
+	uint64_t sprt0_err                    : 1;
+	uint64_t sprt1_err                    : 1;
+	uint64_t reserved_58_59               : 2;
+	uint64_t ill_pad                      : 1;
+	uint64_t pipe_err                     : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} cn68xx;
+	struct cvmx_sli_int_enb_portx_cn68xx  cn68xxp1;
+	struct cvmx_sli_int_enb_portx_cn61xx  cnf71xx;
 };
 typedef union cvmx_sli_int_enb_portx cvmx_sli_int_enb_portx_t;
 
@@ -1659,12 +2610,302 @@ typedef union cvmx_sli_int_enb_portx cvmx_sli_int_enb_portx_t;
  *
  * Set when an interrupt condition occurs, write '1' to clear.
  */
-union cvmx_sli_int_sum
-{
+union cvmx_sli_int_sum {
 	uint64_t u64;
-	struct cvmx_sli_int_sum_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_62_63               : 2;
+	uint64_t pipe_err                     : 1;  /**< Set when a PIPE value outside range is received. */
+	uint64_t ill_pad                      : 1;  /**< Set when a BAR0 address R/W falls into theaddress
+                                                         range of the Packet-CSR, but for an unused
+                                                         address. */
+	uint64_t sprt3_err                    : 1;  /**< Reserved. */
+	uint64_t sprt2_err                    : 1;  /**< Reserved. */
+	uint64_t sprt1_err                    : 1;  /**< When an error response received on SLI port 1
+                                                         this bit is set. */
+	uint64_t sprt0_err                    : 1;  /**< When an error response received on SLI port 0
+                                                         this bit is set. */
+	uint64_t pins_err                     : 1;  /**< When a read error occurs on a packet instruction
+                                                         this bit is set. */
+	uint64_t pop_err                      : 1;  /**< When a read error occurs on a packet scatter
+                                                         pointer pair this bit is set. */
+	uint64_t pdi_err                      : 1;  /**< When a read error occurs on a packet data read
+                                                         this bit is set. */
+	uint64_t pgl_err                      : 1;  /**< When a read error occurs on a packet gather list
+                                                         read this bit is set. */
+	uint64_t pin_bp                       : 1;  /**< Packet input count has exceeded the WMARK.
+                                                         See SLI_PKT_IN_BP */
+	uint64_t pout_err                     : 1;  /**< Set when PKO sends packet data with the error bit
+                                                         set. */
+	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell count overflowed. Which
+                                                         doorbell can be found in DPI_PINT_INFO[PSLDBOF] */
+	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell count overflowed. Which
+                                                         doorbell can be found in DPI_PINT_INFO[PIDBOF] */
+	uint64_t reserved_38_47               : 10;
+	uint64_t dtime                        : 2;  /**< Whenever SLI_DMAx_CNT[CNT] is not 0, the
+                                                         SLI_DMAx_TIM[TIM] timer increments every SLI
+                                                         clock.
+                                                         DTIME[x] is set whenever SLI_DMAx_TIM[TIM] >
+                                                         SLI_DMAx_INT_LEVEL[TIME].
+                                                         DTIME[x] is normally cleared by clearing
+                                                         SLI_DMAx_CNT[CNT] (which also clears
+                                                         SLI_DMAx_TIM[TIM]). */
+	uint64_t dcnt                         : 2;  /**< DCNT[x] is set whenever SLI_DMAx_CNT[CNT] >
+                                                         SLI_DMAx_INT_LEVEL[CNT].
+                                                         DCNT[x] is normally cleared by decreasing
+                                                         SLI_DMAx_CNT[CNT]. */
+	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts. */
+	uint64_t reserved_28_31               : 4;
+	uint64_t m3_un_wi                     : 1;  /**< Reserved. */
+	uint64_t m3_un_b0                     : 1;  /**< Reserved. */
+	uint64_t m3_up_wi                     : 1;  /**< Reserved. */
+	uint64_t m3_up_b0                     : 1;  /**< Reserved. */
+	uint64_t m2_un_wi                     : 1;  /**< Reserved. */
+	uint64_t m2_un_b0                     : 1;  /**< Reserved. */
+	uint64_t m2_up_wi                     : 1;  /**< Reserved. */
+	uint64_t m2_up_b0                     : 1;  /**< Reserved. */
+	uint64_t mac1_int                     : 1;  /**< Interrupt from MAC1.
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB_INT) */
+	uint64_t mac0_int                     : 1;  /**< Interrupt from MAC0.
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB_INT) */
+	uint64_t mio_int1                     : 1;  /**< Interrupt from MIO for PORT 1.
+                                                         See CIU_INT33_SUM0, CIU_INT_SUM1
+                                                         (enabled by CIU_INT33_EN0, CIU_INT33_EN1) */
+	uint64_t mio_int0                     : 1;  /**< Interrupt from MIO for PORT 0.
+                                                         See CIU_INT32_SUM0, CIU_INT_SUM1
+                                                         (enabled by CIU_INT32_EN0, CIU_INT32_EN1) */
+	uint64_t m1_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register
+                                                         from MAC 1. This occurs when the window registers
+                                                         are disabeld and a window register access occurs. */
+	uint64_t m1_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0 from MAC 1.
+                                                         This occurs when the BAR 0 address space is
+                                                         disabeled. */
+	uint64_t m1_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register
+                                                         from MAC 1. This occurs when the window registers
+                                                         are disabeld and a window register access occurs. */
+	uint64_t m1_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0 from MAC 1.
+                                                         This occurs when the BAR 0 address space is
+                                                         disabeled. */
+	uint64_t m0_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register
+                                                         from MAC 0. This occurs when the window registers
+                                                         are disabeld and a window register access occurs. */
+	uint64_t m0_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0 from MAC 0.
+                                                         This occurs when the BAR 0 address space is
+                                                         disabeled. */
+	uint64_t m0_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register
+                                                         from MAC 0. This occurs when the window registers
+                                                         are disabeld and a window register access occurs. */
+	uint64_t m0_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0 from MAC 0.
+                                                         This occurs when the BAR 0 address space is
+                                                         disabeled. */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ptime                        : 1;  /**< Packet Timer has an interrupt. Which rings can
+                                                         be found in SLI_PKT_TIME_INT. */
+	uint64_t pcnt                         : 1;  /**< Packet Counter has an interrupt. Which rings can
+                                                         be found in SLI_PKT_CNT_INT. */
+	uint64_t iob2big                      : 1;  /**< A requested IOBDMA is to large. */
+	uint64_t bar0_to                      : 1;  /**< BAR0 R/W to a NCB device did not receive
+                                                         read-data/commit in 0xffff core clocks. */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t rml_to                       : 1;  /**< A read or write transfer did not complete
+                                                         within 0xffff core clocks. */
+#else
+	uint64_t rml_to                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t m0_up_b0                     : 1;
+	uint64_t m0_up_wi                     : 1;
+	uint64_t m0_un_b0                     : 1;
+	uint64_t m0_un_wi                     : 1;
+	uint64_t m1_up_b0                     : 1;
+	uint64_t m1_up_wi                     : 1;
+	uint64_t m1_un_b0                     : 1;
+	uint64_t m1_un_wi                     : 1;
+	uint64_t mio_int0                     : 1;
+	uint64_t mio_int1                     : 1;
+	uint64_t mac0_int                     : 1;
+	uint64_t mac1_int                     : 1;
+	uint64_t m2_up_b0                     : 1;
+	uint64_t m2_up_wi                     : 1;
+	uint64_t m2_un_b0                     : 1;
+	uint64_t m2_un_wi                     : 1;
+	uint64_t m3_up_b0                     : 1;
+	uint64_t m3_up_wi                     : 1;
+	uint64_t m3_un_b0                     : 1;
+	uint64_t m3_un_wi                     : 1;
+	uint64_t reserved_28_31               : 4;
+	uint64_t dmafi                        : 2;
+	uint64_t dcnt                         : 2;
+	uint64_t dtime                        : 2;
+	uint64_t reserved_38_47               : 10;
+	uint64_t pidbof                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pout_err                     : 1;
+	uint64_t pin_bp                       : 1;
+	uint64_t pgl_err                      : 1;
+	uint64_t pdi_err                      : 1;
+	uint64_t pop_err                      : 1;
+	uint64_t pins_err                     : 1;
+	uint64_t sprt0_err                    : 1;
+	uint64_t sprt1_err                    : 1;
+	uint64_t sprt2_err                    : 1;
+	uint64_t sprt3_err                    : 1;
+	uint64_t ill_pad                      : 1;
+	uint64_t pipe_err                     : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} s;
+	struct cvmx_sli_int_sum_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_61_63               : 3;
+	uint64_t ill_pad                      : 1;  /**< Set when a BAR0 address R/W falls into theaddress
+                                                         range of the Packet-CSR, but for an unused
+                                                         address. */
+	uint64_t sprt3_err                    : 1;  /**< Reserved. */
+	uint64_t sprt2_err                    : 1;  /**< Reserved. */
+	uint64_t sprt1_err                    : 1;  /**< When an error response received on SLI port 1
+                                                         this bit is set. */
+	uint64_t sprt0_err                    : 1;  /**< When an error response received on SLI port 0
+                                                         this bit is set. */
+	uint64_t pins_err                     : 1;  /**< When a read error occurs on a packet instruction
+                                                         this bit is set. */
+	uint64_t pop_err                      : 1;  /**< When a read error occurs on a packet scatter
+                                                         pointer pair this bit is set. */
+	uint64_t pdi_err                      : 1;  /**< When a read error occurs on a packet data read
+                                                         this bit is set. */
+	uint64_t pgl_err                      : 1;  /**< When a read error occurs on a packet gather list
+                                                         read this bit is set. */
+	uint64_t pin_bp                       : 1;  /**< Packet input count has exceeded the WMARK.
+                                                         See SLI_PKT_IN_BP */
+	uint64_t pout_err                     : 1;  /**< Set when PKO sends packet data with the error bit
+                                                         set. */
+	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell count overflowed. Which
+                                                         doorbell can be found in DPI_PINT_INFO[PSLDBOF] */
+	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell count overflowed. Which
+                                                         doorbell can be found in DPI_PINT_INFO[PIDBOF] */
+	uint64_t reserved_38_47               : 10;
+	uint64_t dtime                        : 2;  /**< Whenever SLI_DMAx_CNT[CNT] is not 0, the
+                                                         SLI_DMAx_TIM[TIM] timer increments every SLI
+                                                         clock.
+                                                         DTIME[x] is set whenever SLI_DMAx_TIM[TIM] >
+                                                         SLI_DMAx_INT_LEVEL[TIME].
+                                                         DTIME[x] is normally cleared by clearing
+                                                         SLI_DMAx_CNT[CNT] (which also clears
+                                                         SLI_DMAx_TIM[TIM]). */
+	uint64_t dcnt                         : 2;  /**< DCNT[x] is set whenever SLI_DMAx_CNT[CNT] >
+                                                         SLI_DMAx_INT_LEVEL[CNT].
+                                                         DCNT[x] is normally cleared by decreasing
+                                                         SLI_DMAx_CNT[CNT]. */
+	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts. */
+	uint64_t reserved_28_31               : 4;
+	uint64_t m3_un_wi                     : 1;  /**< Reserved. */
+	uint64_t m3_un_b0                     : 1;  /**< Reserved. */
+	uint64_t m3_up_wi                     : 1;  /**< Reserved. */
+	uint64_t m3_up_b0                     : 1;  /**< Reserved. */
+	uint64_t m2_un_wi                     : 1;  /**< Reserved. */
+	uint64_t m2_un_b0                     : 1;  /**< Reserved. */
+	uint64_t m2_up_wi                     : 1;  /**< Reserved. */
+	uint64_t m2_up_b0                     : 1;  /**< Reserved. */
+	uint64_t mac1_int                     : 1;  /**< Interrupt from MAC1.
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB_INT) */
+	uint64_t mac0_int                     : 1;  /**< Interrupt from MAC0.
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB_INT) */
+	uint64_t mio_int1                     : 1;  /**< Interrupt from MIO for PORT 1.
+                                                         See CIU_INT33_SUM0, CIU_INT_SUM1
+                                                         (enabled by CIU_INT33_EN0, CIU_INT33_EN1) */
+	uint64_t mio_int0                     : 1;  /**< Interrupt from MIO for PORT 0.
+                                                         See CIU_INT32_SUM0, CIU_INT_SUM1
+                                                         (enabled by CIU_INT32_EN0, CIU_INT32_EN1) */
+	uint64_t m1_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register
+                                                         from MAC 1. This occurs when the window registers
+                                                         are disabeld and a window register access occurs. */
+	uint64_t m1_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0 from MAC 1.
+                                                         This occurs when the BAR 0 address space is
+                                                         disabeled. */
+	uint64_t m1_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register
+                                                         from MAC 1. This occurs when the window registers
+                                                         are disabeld and a window register access occurs. */
+	uint64_t m1_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0 from MAC 1.
+                                                         This occurs when the BAR 0 address space is
+                                                         disabeled. */
+	uint64_t m0_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register
+                                                         from MAC 0. This occurs when the window registers
+                                                         are disabeld and a window register access occurs. */
+	uint64_t m0_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0 from MAC 0.
+                                                         This occurs when the BAR 0 address space is
+                                                         disabeled. */
+	uint64_t m0_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register
+                                                         from MAC 0. This occurs when the window registers
+                                                         are disabeld and a window register access occurs. */
+	uint64_t m0_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0 from MAC 0.
+                                                         This occurs when the BAR 0 address space is
+                                                         disabeled. */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ptime                        : 1;  /**< Packet Timer has an interrupt. Which rings can
+                                                         be found in SLI_PKT_TIME_INT. */
+	uint64_t pcnt                         : 1;  /**< Packet Counter has an interrupt. Which rings can
+                                                         be found in SLI_PKT_CNT_INT. */
+	uint64_t iob2big                      : 1;  /**< A requested IOBDMA is to large. */
+	uint64_t bar0_to                      : 1;  /**< BAR0 R/W to a NCB device did not receive
+                                                         read-data/commit in 0xffff core clocks. */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t rml_to                       : 1;  /**< A read or write transfer did not complete
+                                                         within 0xffff core clocks. */
+#else
+	uint64_t rml_to                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t m0_up_b0                     : 1;
+	uint64_t m0_up_wi                     : 1;
+	uint64_t m0_un_b0                     : 1;
+	uint64_t m0_un_wi                     : 1;
+	uint64_t m1_up_b0                     : 1;
+	uint64_t m1_up_wi                     : 1;
+	uint64_t m1_un_b0                     : 1;
+	uint64_t m1_un_wi                     : 1;
+	uint64_t mio_int0                     : 1;
+	uint64_t mio_int1                     : 1;
+	uint64_t mac0_int                     : 1;
+	uint64_t mac1_int                     : 1;
+	uint64_t m2_up_b0                     : 1;
+	uint64_t m2_up_wi                     : 1;
+	uint64_t m2_un_b0                     : 1;
+	uint64_t m2_un_wi                     : 1;
+	uint64_t m3_up_b0                     : 1;
+	uint64_t m3_up_wi                     : 1;
+	uint64_t m3_un_b0                     : 1;
+	uint64_t m3_un_wi                     : 1;
+	uint64_t reserved_28_31               : 4;
+	uint64_t dmafi                        : 2;
+	uint64_t dcnt                         : 2;
+	uint64_t dtime                        : 2;
+	uint64_t reserved_38_47               : 10;
+	uint64_t pidbof                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pout_err                     : 1;
+	uint64_t pin_bp                       : 1;
+	uint64_t pgl_err                      : 1;
+	uint64_t pdi_err                      : 1;
+	uint64_t pop_err                      : 1;
+	uint64_t pins_err                     : 1;
+	uint64_t sprt0_err                    : 1;
+	uint64_t sprt1_err                    : 1;
+	uint64_t sprt2_err                    : 1;
+	uint64_t sprt3_err                    : 1;
+	uint64_t ill_pad                      : 1;
+	uint64_t reserved_61_63               : 3;
+#endif
+	} cn61xx;
+	struct cvmx_sli_int_sum_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_61_63               : 3;
 	uint64_t ill_pad                      : 1;  /**< Set when a BAR0 address R/W falls into theaddress
                                                          range of the Packet-CSR, but for an unused
@@ -1789,59 +3030,239 @@ union cvmx_sli_int_sum
 	uint64_t ill_pad                      : 1;
 	uint64_t reserved_61_63               : 3;
 #endif
-	} s;
-	struct cvmx_sli_int_sum_s             cn63xx;
-	struct cvmx_sli_int_sum_s             cn63xxp1;
+	} cn63xx;
+	struct cvmx_sli_int_sum_cn63xx        cn63xxp1;
+	struct cvmx_sli_int_sum_cn61xx        cn66xx;
+	struct cvmx_sli_int_sum_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_62_63               : 2;
+	uint64_t pipe_err                     : 1;  /**< Set when a PIPE value outside range is received. */
+	uint64_t ill_pad                      : 1;  /**< Set when a BAR0 address R/W falls into theaddress
+                                                         range of the Packet-CSR, but for an unused
+                                                         address. */
+	uint64_t reserved_58_59               : 2;
+	uint64_t sprt1_err                    : 1;  /**< When an error response received on SLI port 1
+                                                         this bit is set. */
+	uint64_t sprt0_err                    : 1;  /**< When an error response received on SLI port 0
+                                                         this bit is set. */
+	uint64_t pins_err                     : 1;  /**< When a read error occurs on a packet instruction
+                                                         this bit is set. */
+	uint64_t pop_err                      : 1;  /**< When a read error occurs on a packet scatter
+                                                         pointer pair this bit is set. */
+	uint64_t pdi_err                      : 1;  /**< When a read error occurs on a packet data read
+                                                         this bit is set. */
+	uint64_t pgl_err                      : 1;  /**< When a read error occurs on a packet gather list
+                                                         read this bit is set. */
+	uint64_t reserved_51_51               : 1;
+	uint64_t pout_err                     : 1;  /**< Set when PKO sends packet data with the error bit
+                                                         set. */
+	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell count overflowed. Which
+                                                         doorbell can be found in DPI_PINT_INFO[PSLDBOF] */
+	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell count overflowed. Which
+                                                         doorbell can be found in DPI_PINT_INFO[PIDBOF] */
+	uint64_t reserved_38_47               : 10;
+	uint64_t dtime                        : 2;  /**< Whenever SLI_DMAx_CNT[CNT] is not 0, the
+                                                         SLI_DMAx_TIM[TIM] timer increments every SLI
+                                                         clock.
+                                                         DTIME[x] is set whenever SLI_DMAx_TIM[TIM] >
+                                                         SLI_DMAx_INT_LEVEL[TIME].
+                                                         DTIME[x] is normally cleared by clearing
+                                                         SLI_DMAx_CNT[CNT] (which also clears
+                                                         SLI_DMAx_TIM[TIM]). */
+	uint64_t dcnt                         : 2;  /**< DCNT[x] is set whenever SLI_DMAx_CNT[CNT] >
+                                                         SLI_DMAx_INT_LEVEL[CNT].
+                                                         DCNT[x] is normally cleared by decreasing
+                                                         SLI_DMAx_CNT[CNT]. */
+	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts. */
+	uint64_t reserved_20_31               : 12;
+	uint64_t mac1_int                     : 1;  /**< Interrupt from MAC1.
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB_INT) */
+	uint64_t mac0_int                     : 1;  /**< Interrupt from MAC0.
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB_INT) */
+	uint64_t mio_int1                     : 1;  /**< Interrupt from MIO for PORT 1.
+                                                         See CIU_INT33_SUM0, CIU_INT_SUM1
+                                                         (enabled by CIU_INT33_EN0, CIU_INT33_EN1) */
+	uint64_t mio_int0                     : 1;  /**< Interrupt from MIO for PORT 0.
+                                                         See CIU_INT32_SUM0, CIU_INT_SUM1
+                                                         (enabled by CIU_INT32_EN0, CIU_INT32_EN1) */
+	uint64_t m1_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register
+                                                         from MAC 1. This occurs when the window registers
+                                                         are disabeld and a window register access occurs. */
+	uint64_t m1_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0 from MAC 1.
+                                                         This occurs when the BAR 0 address space is
+                                                         disabeled. */
+	uint64_t m1_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register
+                                                         from MAC 1. This occurs when the window registers
+                                                         are disabeld and a window register access occurs. */
+	uint64_t m1_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0 from MAC 1.
+                                                         This occurs when the BAR 0 address space is
+                                                         disabeled. */
+	uint64_t m0_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register
+                                                         from MAC 0. This occurs when the window registers
+                                                         are disabeld and a window register access occurs. */
+	uint64_t m0_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0 from MAC 0.
+                                                         This occurs when the BAR 0 address space is
+                                                         disabeled. */
+	uint64_t m0_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register
+                                                         from MAC 0. This occurs when the window registers
+                                                         are disabeld and a window register access occurs. */
+	uint64_t m0_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0 from MAC 0.
+                                                         This occurs when the BAR 0 address space is
+                                                         disabeled. */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ptime                        : 1;  /**< Packet Timer has an interrupt. Which rings can
+                                                         be found in SLI_PKT_TIME_INT. */
+	uint64_t pcnt                         : 1;  /**< Packet Counter has an interrupt. Which rings can
+                                                         be found in SLI_PKT_CNT_INT. */
+	uint64_t iob2big                      : 1;  /**< A requested IOBDMA is to large. */
+	uint64_t bar0_to                      : 1;  /**< BAR0 R/W to a NCB device did not receive
+                                                         read-data/commit in 0xffff core clocks. */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t rml_to                       : 1;  /**< A read or write transfer did not complete
+                                                         within 0xffff core clocks. */
+#else
+	uint64_t rml_to                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t m0_up_b0                     : 1;
+	uint64_t m0_up_wi                     : 1;
+	uint64_t m0_un_b0                     : 1;
+	uint64_t m0_un_wi                     : 1;
+	uint64_t m1_up_b0                     : 1;
+	uint64_t m1_up_wi                     : 1;
+	uint64_t m1_un_b0                     : 1;
+	uint64_t m1_un_wi                     : 1;
+	uint64_t mio_int0                     : 1;
+	uint64_t mio_int1                     : 1;
+	uint64_t mac0_int                     : 1;
+	uint64_t mac1_int                     : 1;
+	uint64_t reserved_20_31               : 12;
+	uint64_t dmafi                        : 2;
+	uint64_t dcnt                         : 2;
+	uint64_t dtime                        : 2;
+	uint64_t reserved_38_47               : 10;
+	uint64_t pidbof                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pout_err                     : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t pgl_err                      : 1;
+	uint64_t pdi_err                      : 1;
+	uint64_t pop_err                      : 1;
+	uint64_t pins_err                     : 1;
+	uint64_t sprt0_err                    : 1;
+	uint64_t sprt1_err                    : 1;
+	uint64_t reserved_58_59               : 2;
+	uint64_t ill_pad                      : 1;
+	uint64_t pipe_err                     : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} cn68xx;
+	struct cvmx_sli_int_sum_cn68xx        cn68xxp1;
+	struct cvmx_sli_int_sum_cn61xx        cnf71xx;
 };
 typedef union cvmx_sli_int_sum cvmx_sli_int_sum_t;
 
 /**
  * cvmx_sli_last_win_rdata0
  *
- * SLI_LAST_WIN_RDATA0 = SLI Last Window Read Data Port0
+ * SLI_LAST_WIN_RDATA0 = SLI Last Window Read Data
  *
- * The data from the last initiated window read.
+ * The data from the last initiated window read by MAC 0.
  */
-union cvmx_sli_last_win_rdata0
-{
+union cvmx_sli_last_win_rdata0 {
 	uint64_t u64;
-	struct cvmx_sli_last_win_rdata0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_last_win_rdata0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 64; /**< Last window read data. */
 #else
 	uint64_t data                         : 64;
 #endif
 	} s;
+	struct cvmx_sli_last_win_rdata0_s     cn61xx;
 	struct cvmx_sli_last_win_rdata0_s     cn63xx;
 	struct cvmx_sli_last_win_rdata0_s     cn63xxp1;
+	struct cvmx_sli_last_win_rdata0_s     cn66xx;
+	struct cvmx_sli_last_win_rdata0_s     cn68xx;
+	struct cvmx_sli_last_win_rdata0_s     cn68xxp1;
+	struct cvmx_sli_last_win_rdata0_s     cnf71xx;
 };
 typedef union cvmx_sli_last_win_rdata0 cvmx_sli_last_win_rdata0_t;
 
 /**
  * cvmx_sli_last_win_rdata1
  *
- * SLI_LAST_WIN_RDATA1 = SLI Last Window Read Data Port1
+ * SLI_LAST_WIN_RDATA1 = SLI Last Window Read Data
  *
- * The data from the last initiated window read.
+ * The data from the last initiated window read by MAC 1.
  */
-union cvmx_sli_last_win_rdata1
-{
+union cvmx_sli_last_win_rdata1 {
 	uint64_t u64;
-	struct cvmx_sli_last_win_rdata1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_last_win_rdata1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 64; /**< Last window read data. */
 #else
 	uint64_t data                         : 64;
 #endif
 	} s;
+	struct cvmx_sli_last_win_rdata1_s     cn61xx;
 	struct cvmx_sli_last_win_rdata1_s     cn63xx;
 	struct cvmx_sli_last_win_rdata1_s     cn63xxp1;
+	struct cvmx_sli_last_win_rdata1_s     cn66xx;
+	struct cvmx_sli_last_win_rdata1_s     cn68xx;
+	struct cvmx_sli_last_win_rdata1_s     cn68xxp1;
+	struct cvmx_sli_last_win_rdata1_s     cnf71xx;
 };
 typedef union cvmx_sli_last_win_rdata1 cvmx_sli_last_win_rdata1_t;
 
 /**
+ * cvmx_sli_last_win_rdata2
+ *
+ * SLI_LAST_WIN_RDATA2 = SLI Last Window Read Data
+ *
+ * The data from the last initiated window read by MAC 2.
+ */
+union cvmx_sli_last_win_rdata2 {
+	uint64_t u64;
+	struct cvmx_sli_last_win_rdata2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t data                         : 64; /**< Last window read data. */
+#else
+	uint64_t data                         : 64;
+#endif
+	} s;
+	struct cvmx_sli_last_win_rdata2_s     cn61xx;
+	struct cvmx_sli_last_win_rdata2_s     cn66xx;
+	struct cvmx_sli_last_win_rdata2_s     cnf71xx;
+};
+typedef union cvmx_sli_last_win_rdata2 cvmx_sli_last_win_rdata2_t;
+
+/**
+ * cvmx_sli_last_win_rdata3
+ *
+ * SLI_LAST_WIN_RDATA3 = SLI Last Window Read Data
+ *
+ * The data from the last initiated window read by MAC 3.
+ */
+union cvmx_sli_last_win_rdata3 {
+	uint64_t u64;
+	struct cvmx_sli_last_win_rdata3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t data                         : 64; /**< Last window read data. */
+#else
+	uint64_t data                         : 64;
+#endif
+	} s;
+	struct cvmx_sli_last_win_rdata3_s     cn61xx;
+	struct cvmx_sli_last_win_rdata3_s     cn66xx;
+	struct cvmx_sli_last_win_rdata3_s     cnf71xx;
+};
+typedef union cvmx_sli_last_win_rdata3 cvmx_sli_last_win_rdata3_t;
+
+/**
  * cvmx_sli_mac_credit_cnt
  *
  * SLI_MAC_CREDIT_CNT = SLI MAC Credit Count
@@ -1850,12 +3271,10 @@ typedef union cvmx_sli_last_win_rdata1 cvmx_sli_last_win_rdata1_t;
  * flow starts. A write to this register will cause the credit counts in the SLI for the MAC ports to be reset to the value
  * in this register.
  */
-union cvmx_sli_mac_credit_cnt
-{
+union cvmx_sli_mac_credit_cnt {
 	uint64_t u64;
-	struct cvmx_sli_mac_credit_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_mac_credit_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_54_63               : 10;
 	uint64_t p1_c_d                       : 1;  /**< When set does not allow writing of P1_CCNT. */
 	uint64_t p1_n_d                       : 1;  /**< When set does not allow writing of P1_NCNT. */
@@ -1891,10 +3310,10 @@ union cvmx_sli_mac_credit_cnt
 	uint64_t reserved_54_63               : 10;
 #endif
 	} s;
+	struct cvmx_sli_mac_credit_cnt_s      cn61xx;
 	struct cvmx_sli_mac_credit_cnt_s      cn63xx;
-	struct cvmx_sli_mac_credit_cnt_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_mac_credit_cnt_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t p1_ccnt                      : 8;  /**< Port1 C-TLP FIFO Credits.
                                                          Legal values are 0x25 to 0x80. */
@@ -1918,10 +3337,68 @@ union cvmx_sli_mac_credit_cnt
 	uint64_t reserved_48_63               : 16;
 #endif
 	} cn63xxp1;
+	struct cvmx_sli_mac_credit_cnt_s      cn66xx;
+	struct cvmx_sli_mac_credit_cnt_s      cn68xx;
+	struct cvmx_sli_mac_credit_cnt_s      cn68xxp1;
+	struct cvmx_sli_mac_credit_cnt_s      cnf71xx;
 };
 typedef union cvmx_sli_mac_credit_cnt cvmx_sli_mac_credit_cnt_t;
 
 /**
+ * cvmx_sli_mac_credit_cnt2
+ *
+ * SLI_MAC_CREDIT_CNT2 = SLI MAC Credit Count2
+ *
+ * Contains the number of credits for the MAC port FIFOs (for MACs 2 and 3) used by the SLI. This value needs to be set BEFORE S2M traffic
+ * flow starts. A write to this register will cause the credit counts in the SLI for the MAC ports to be reset to the value
+ * in this register.
+ */
+union cvmx_sli_mac_credit_cnt2 {
+	uint64_t u64;
+	struct cvmx_sli_mac_credit_cnt2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t p3_c_d                       : 1;  /**< When set does not allow writing of P3_CCNT. */
+	uint64_t p3_n_d                       : 1;  /**< When set does not allow writing of P3_NCNT. */
+	uint64_t p3_p_d                       : 1;  /**< When set does not allow writing of P3_PCNT. */
+	uint64_t p2_c_d                       : 1;  /**< When set does not allow writing of P2_CCNT. */
+	uint64_t p2_n_d                       : 1;  /**< When set does not allow writing of P2_NCNT. */
+	uint64_t p2_p_d                       : 1;  /**< When set does not allow writing of P2_PCNT. */
+	uint64_t p3_ccnt                      : 8;  /**< Port3 C-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+	uint64_t p3_ncnt                      : 8;  /**< Port3 N-TLP FIFO Credits.
+                                                         Legal values are 0x5 to 0x10. */
+	uint64_t p3_pcnt                      : 8;  /**< Port3 P-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+	uint64_t p2_ccnt                      : 8;  /**< Port2 C-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+	uint64_t p2_ncnt                      : 8;  /**< Port2 N-TLP FIFO Credits.
+                                                         Legal values are 0x5 to 0x10. */
+	uint64_t p2_pcnt                      : 8;  /**< Port2 P-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+#else
+	uint64_t p2_pcnt                      : 8;
+	uint64_t p2_ncnt                      : 8;
+	uint64_t p2_ccnt                      : 8;
+	uint64_t p3_pcnt                      : 8;
+	uint64_t p3_ncnt                      : 8;
+	uint64_t p3_ccnt                      : 8;
+	uint64_t p2_p_d                       : 1;
+	uint64_t p2_n_d                       : 1;
+	uint64_t p2_c_d                       : 1;
+	uint64_t p3_p_d                       : 1;
+	uint64_t p3_n_d                       : 1;
+	uint64_t p3_c_d                       : 1;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_sli_mac_credit_cnt2_s     cn61xx;
+	struct cvmx_sli_mac_credit_cnt2_s     cn66xx;
+	struct cvmx_sli_mac_credit_cnt2_s     cnf71xx;
+};
+typedef union cvmx_sli_mac_credit_cnt2 cvmx_sli_mac_credit_cnt2_t;
+
+/**
  * cvmx_sli_mac_number
  *
  * 0x13DA0 - 0x13DF0 reserved for ports 2 - 7
@@ -1929,22 +3406,34 @@ typedef union cvmx_sli_mac_credit_cnt cvmx_sli_mac_credit_cnt_t;
  *                  SLI_MAC_NUMBER = SLI MAC Number
  *
  * When read from a MAC port it returns the MAC's port number.
- * register.
  */
-union cvmx_sli_mac_number
-{
+union cvmx_sli_mac_number {
 	uint64_t u64;
-	struct cvmx_sli_mac_number_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_mac_number_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_9_63                : 55;
+	uint64_t a_mode                       : 1;  /**< SLI in Authenticate Mode. */
+	uint64_t num                          : 8;  /**< The mac number. */
+#else
+	uint64_t num                          : 8;
+	uint64_t a_mode                       : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_sli_mac_number_s          cn61xx;
+	struct cvmx_sli_mac_number_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t num                          : 8;  /**< The mac number. */
 #else
 	uint64_t num                          : 8;
 	uint64_t reserved_8_63                : 56;
 #endif
-	} s;
-	struct cvmx_sli_mac_number_s          cn63xx;
+	} cn63xx;
+	struct cvmx_sli_mac_number_s          cn66xx;
+	struct cvmx_sli_mac_number_cn63xx     cn68xx;
+	struct cvmx_sli_mac_number_cn63xx     cn68xxp1;
+	struct cvmx_sli_mac_number_s          cnf71xx;
 };
 typedef union cvmx_sli_mac_number cvmx_sli_mac_number_t;
 
@@ -1955,12 +3444,10 @@ typedef union cvmx_sli_mac_number cvmx_sli_mac_number_t;
  *
  * Contains control for access to the MAC address space.
  */
-union cvmx_sli_mem_access_ctl
-{
+union cvmx_sli_mem_access_ctl {
 	uint64_t u64;
-	struct cvmx_sli_mem_access_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_mem_access_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t max_word                     : 4;  /**< The maximum number of words to merge into a single
                                                          write operation from the PPs to the MAC. Legal
@@ -1976,8 +3463,13 @@ union cvmx_sli_mem_access_ctl
 	uint64_t reserved_14_63               : 50;
 #endif
 	} s;
+	struct cvmx_sli_mem_access_ctl_s      cn61xx;
 	struct cvmx_sli_mem_access_ctl_s      cn63xx;
 	struct cvmx_sli_mem_access_ctl_s      cn63xxp1;
+	struct cvmx_sli_mem_access_ctl_s      cn66xx;
+	struct cvmx_sli_mem_access_ctl_s      cn68xx;
+	struct cvmx_sli_mem_access_ctl_s      cn68xxp1;
+	struct cvmx_sli_mem_access_ctl_s      cnf71xx;
 };
 typedef union cvmx_sli_mem_access_ctl cvmx_sli_mem_access_ctl_t;
 
@@ -1995,12 +3487,53 @@ typedef union cvmx_sli_mem_access_ctl cvmx_sli_mem_access_ctl_t;
  *
  *  Contains address index and control bits for access to memory from Core PPs.
  */
-union cvmx_sli_mem_access_subidx
-{
+union cvmx_sli_mem_access_subidx {
 	uint64_t u64;
-	struct cvmx_sli_mem_access_subidx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_mem_access_subidx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_43_63               : 21;
+	uint64_t zero                         : 1;  /**< Causes all byte reads to be zero length reads.
+                                                         Returns to the EXEC a zero for all read data.
+                                                         This must be zero for sRIO ports. */
+	uint64_t port                         : 3;  /**< Physical MAC Port that reads/writes to
+                                                         this subid are sent to. Must be <= 1, as there are
+                                                         only two ports present. */
+	uint64_t nmerge                       : 1;  /**< When set, no merging is allowed in this window. */
+	uint64_t esr                          : 2;  /**< ES<1:0> for reads to this subid.
+                                                         ES<1:0> is the endian-swap attribute for these MAC
+                                                         memory space reads. */
+	uint64_t esw                          : 2;  /**< ES<1:0> for writes to this subid.
+                                                         ES<1:0> is the endian-swap attribute for these MAC
+                                                         memory space writes. */
+	uint64_t wtype                        : 2;  /**< ADDRTYPE<1:0> for writes to this subid
+                                                         For PCIe:
+                                                         - ADDRTYPE<0> is the relaxed-order attribute
+                                                         - ADDRTYPE<1> is the no-snoop attribute
+                                                         For sRIO:
+                                                         - ADDRTYPE<1:0> help select an SRIO*_S2M_TYPE*
+                                                           entry */
+	uint64_t rtype                        : 2;  /**< ADDRTYPE<1:0> for reads to this subid
+                                                         For PCIe:
+                                                         - ADDRTYPE<0> is the relaxed-order attribute
+                                                         - ADDRTYPE<1> is the no-snoop attribute
+                                                         For sRIO:
+                                                         - ADDRTYPE<1:0> help select an SRIO*_S2M_TYPE*
+                                                           entry */
+	uint64_t reserved_0_29                : 30;
+#else
+	uint64_t reserved_0_29                : 30;
+	uint64_t rtype                        : 2;
+	uint64_t wtype                        : 2;
+	uint64_t esw                          : 2;
+	uint64_t esr                          : 2;
+	uint64_t nmerge                       : 1;
+	uint64_t port                         : 3;
+	uint64_t zero                         : 1;
+	uint64_t reserved_43_63               : 21;
+#endif
+	} s;
+	struct cvmx_sli_mem_access_subidx_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_43_63               : 21;
 	uint64_t zero                         : 1;  /**< Causes all byte reads to be zero length reads.
                                                          Returns to the EXEC a zero for all read data.
@@ -2042,9 +3575,52 @@ union cvmx_sli_mem_access_subidx
 	uint64_t zero                         : 1;
 	uint64_t reserved_43_63               : 21;
 #endif
-	} s;
-	struct cvmx_sli_mem_access_subidx_s   cn63xx;
-	struct cvmx_sli_mem_access_subidx_s   cn63xxp1;
+	} cn61xx;
+	struct cvmx_sli_mem_access_subidx_cn61xx cn63xx;
+	struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1;
+	struct cvmx_sli_mem_access_subidx_cn61xx cn66xx;
+	struct cvmx_sli_mem_access_subidx_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_43_63               : 21;
+	uint64_t zero                         : 1;  /**< Causes all byte reads to be zero length reads.
+                                                         Returns to the EXEC a zero for all read data.
+                                                         This must be zero for sRIO ports. */
+	uint64_t port                         : 3;  /**< Physical MAC Port that reads/writes to
+                                                         this subid are sent to. Must be <= 1, as there are
+                                                         only two ports present. */
+	uint64_t nmerge                       : 1;  /**< When set, no merging is allowed in this window. */
+	uint64_t esr                          : 2;  /**< ES<1:0> for reads to this subid.
+                                                         ES<1:0> is the endian-swap attribute for these MAC
+                                                         memory space reads. */
+	uint64_t esw                          : 2;  /**< ES<1:0> for writes to this subid.
+                                                         ES<1:0> is the endian-swap attribute for these MAC
+                                                         memory space writes. */
+	uint64_t wtype                        : 2;  /**< ADDRTYPE<1:0> for writes to this subid
+                                                         For PCIe:
+                                                         - ADDRTYPE<0> is the relaxed-order attribute
+                                                         - ADDRTYPE<1> is the no-snoop attribute */
+	uint64_t rtype                        : 2;  /**< ADDRTYPE<1:0> for reads to this subid
+                                                         For PCIe:
+                                                         - ADDRTYPE<0> is the relaxed-order attribute
+                                                         - ADDRTYPE<1> is the no-snoop attribute */
+	uint64_t ba                           : 28; /**< Address Bits <63:36> for reads/writes that use
+                                                         this subid. */
+	uint64_t reserved_0_1                 : 2;
+#else
+	uint64_t reserved_0_1                 : 2;
+	uint64_t ba                           : 28;
+	uint64_t rtype                        : 2;
+	uint64_t wtype                        : 2;
+	uint64_t esw                          : 2;
+	uint64_t esr                          : 2;
+	uint64_t nmerge                       : 1;
+	uint64_t port                         : 3;
+	uint64_t zero                         : 1;
+	uint64_t reserved_43_63               : 21;
+#endif
+	} cn68xx;
+	struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1;
+	struct cvmx_sli_mem_access_subidx_cn61xx cnf71xx;
 };
 typedef union cvmx_sli_mem_access_subidx cvmx_sli_mem_access_subidx_t;
 
@@ -2055,19 +3631,22 @@ typedef union cvmx_sli_mem_access_subidx cvmx_sli_mem_access_subidx_t;
  *
  * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV0.
  */
-union cvmx_sli_msi_enb0
-{
+union cvmx_sli_msi_enb0 {
 	uint64_t u64;
-	struct cvmx_sli_msi_enb0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_msi_enb0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t enb                          : 64; /**< Enables bit [63:0] of SLI_MSI_RCV0. */
 #else
 	uint64_t enb                          : 64;
 #endif
 	} s;
+	struct cvmx_sli_msi_enb0_s            cn61xx;
 	struct cvmx_sli_msi_enb0_s            cn63xx;
 	struct cvmx_sli_msi_enb0_s            cn63xxp1;
+	struct cvmx_sli_msi_enb0_s            cn66xx;
+	struct cvmx_sli_msi_enb0_s            cn68xx;
+	struct cvmx_sli_msi_enb0_s            cn68xxp1;
+	struct cvmx_sli_msi_enb0_s            cnf71xx;
 };
 typedef union cvmx_sli_msi_enb0 cvmx_sli_msi_enb0_t;
 
@@ -2078,19 +3657,22 @@ typedef union cvmx_sli_msi_enb0 cvmx_sli_msi_enb0_t;
  *
  * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV1.
  */
-union cvmx_sli_msi_enb1
-{
+union cvmx_sli_msi_enb1 {
 	uint64_t u64;
-	struct cvmx_sli_msi_enb1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_msi_enb1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t enb                          : 64; /**< Enables bit [63:0] of SLI_MSI_RCV1. */
 #else
 	uint64_t enb                          : 64;
 #endif
 	} s;
+	struct cvmx_sli_msi_enb1_s            cn61xx;
 	struct cvmx_sli_msi_enb1_s            cn63xx;
 	struct cvmx_sli_msi_enb1_s            cn63xxp1;
+	struct cvmx_sli_msi_enb1_s            cn66xx;
+	struct cvmx_sli_msi_enb1_s            cn68xx;
+	struct cvmx_sli_msi_enb1_s            cn68xxp1;
+	struct cvmx_sli_msi_enb1_s            cnf71xx;
 };
 typedef union cvmx_sli_msi_enb1 cvmx_sli_msi_enb1_t;
 
@@ -2101,19 +3683,22 @@ typedef union cvmx_sli_msi_enb1 cvmx_sli_msi_enb1_t;
  *
  * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV2.
  */
-union cvmx_sli_msi_enb2
-{
+union cvmx_sli_msi_enb2 {
 	uint64_t u64;
-	struct cvmx_sli_msi_enb2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_msi_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t enb                          : 64; /**< Enables bit [63:0] of SLI_MSI_RCV2. */
 #else
 	uint64_t enb                          : 64;
 #endif
 	} s;
+	struct cvmx_sli_msi_enb2_s            cn61xx;
 	struct cvmx_sli_msi_enb2_s            cn63xx;
 	struct cvmx_sli_msi_enb2_s            cn63xxp1;
+	struct cvmx_sli_msi_enb2_s            cn66xx;
+	struct cvmx_sli_msi_enb2_s            cn68xx;
+	struct cvmx_sli_msi_enb2_s            cn68xxp1;
+	struct cvmx_sli_msi_enb2_s            cnf71xx;
 };
 typedef union cvmx_sli_msi_enb2 cvmx_sli_msi_enb2_t;
 
@@ -2124,19 +3709,22 @@ typedef union cvmx_sli_msi_enb2 cvmx_sli_msi_enb2_t;
  *
  * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV3.
  */
-union cvmx_sli_msi_enb3
-{
+union cvmx_sli_msi_enb3 {
 	uint64_t u64;
-	struct cvmx_sli_msi_enb3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_msi_enb3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t enb                          : 64; /**< Enables bit [63:0] of SLI_MSI_RCV3. */
 #else
 	uint64_t enb                          : 64;
 #endif
 	} s;
+	struct cvmx_sli_msi_enb3_s            cn61xx;
 	struct cvmx_sli_msi_enb3_s            cn63xx;
 	struct cvmx_sli_msi_enb3_s            cn63xxp1;
+	struct cvmx_sli_msi_enb3_s            cn66xx;
+	struct cvmx_sli_msi_enb3_s            cn68xx;
+	struct cvmx_sli_msi_enb3_s            cn68xxp1;
+	struct cvmx_sli_msi_enb3_s            cnf71xx;
 };
 typedef union cvmx_sli_msi_enb3 cvmx_sli_msi_enb3_t;
 
@@ -2147,19 +3735,22 @@ typedef union cvmx_sli_msi_enb3 cvmx_sli_msi_enb3_t;
  *
  * Contains bits [63:0] of the 256 bits of MSI interrupts.
  */
-union cvmx_sli_msi_rcv0
-{
+union cvmx_sli_msi_rcv0 {
 	uint64_t u64;
-	struct cvmx_sli_msi_rcv0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_msi_rcv0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t intr                         : 64; /**< Bits 63-0 of the 256 bits of MSI interrupt. */
 #else
 	uint64_t intr                         : 64;
 #endif
 	} s;
+	struct cvmx_sli_msi_rcv0_s            cn61xx;
 	struct cvmx_sli_msi_rcv0_s            cn63xx;
 	struct cvmx_sli_msi_rcv0_s            cn63xxp1;
+	struct cvmx_sli_msi_rcv0_s            cn66xx;
+	struct cvmx_sli_msi_rcv0_s            cn68xx;
+	struct cvmx_sli_msi_rcv0_s            cn68xxp1;
+	struct cvmx_sli_msi_rcv0_s            cnf71xx;
 };
 typedef union cvmx_sli_msi_rcv0 cvmx_sli_msi_rcv0_t;
 
@@ -2170,19 +3761,22 @@ typedef union cvmx_sli_msi_rcv0 cvmx_sli_msi_rcv0_t;
  *
  * Contains bits [127:64] of the 256 bits of MSI interrupts.
  */
-union cvmx_sli_msi_rcv1
-{
+union cvmx_sli_msi_rcv1 {
 	uint64_t u64;
-	struct cvmx_sli_msi_rcv1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_msi_rcv1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t intr                         : 64; /**< Bits 127-64 of the 256 bits of MSI interrupt. */
 #else
 	uint64_t intr                         : 64;
 #endif
 	} s;
+	struct cvmx_sli_msi_rcv1_s            cn61xx;
 	struct cvmx_sli_msi_rcv1_s            cn63xx;
 	struct cvmx_sli_msi_rcv1_s            cn63xxp1;
+	struct cvmx_sli_msi_rcv1_s            cn66xx;
+	struct cvmx_sli_msi_rcv1_s            cn68xx;
+	struct cvmx_sli_msi_rcv1_s            cn68xxp1;
+	struct cvmx_sli_msi_rcv1_s            cnf71xx;
 };
 typedef union cvmx_sli_msi_rcv1 cvmx_sli_msi_rcv1_t;
 
@@ -2193,19 +3787,22 @@ typedef union cvmx_sli_msi_rcv1 cvmx_sli_msi_rcv1_t;
  *
  * Contains bits [191:128] of the 256 bits of MSI interrupts.
  */
-union cvmx_sli_msi_rcv2
-{
+union cvmx_sli_msi_rcv2 {
 	uint64_t u64;
-	struct cvmx_sli_msi_rcv2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_msi_rcv2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t intr                         : 64; /**< Bits 191-128 of the 256 bits of MSI interrupt. */
 #else
 	uint64_t intr                         : 64;
 #endif
 	} s;
+	struct cvmx_sli_msi_rcv2_s            cn61xx;
 	struct cvmx_sli_msi_rcv2_s            cn63xx;
 	struct cvmx_sli_msi_rcv2_s            cn63xxp1;
+	struct cvmx_sli_msi_rcv2_s            cn66xx;
+	struct cvmx_sli_msi_rcv2_s            cn68xx;
+	struct cvmx_sli_msi_rcv2_s            cn68xxp1;
+	struct cvmx_sli_msi_rcv2_s            cnf71xx;
 };
 typedef union cvmx_sli_msi_rcv2 cvmx_sli_msi_rcv2_t;
 
@@ -2216,19 +3813,22 @@ typedef union cvmx_sli_msi_rcv2 cvmx_sli_msi_rcv2_t;
  *
  * Contains bits [255:192] of the 256 bits of MSI interrupts.
  */
-union cvmx_sli_msi_rcv3
-{
+union cvmx_sli_msi_rcv3 {
 	uint64_t u64;
-	struct cvmx_sli_msi_rcv3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_msi_rcv3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t intr                         : 64; /**< Bits 255-192 of the 256 bits of MSI interrupt. */
 #else
 	uint64_t intr                         : 64;
 #endif
 	} s;
+	struct cvmx_sli_msi_rcv3_s            cn61xx;
 	struct cvmx_sli_msi_rcv3_s            cn63xx;
 	struct cvmx_sli_msi_rcv3_s            cn63xxp1;
+	struct cvmx_sli_msi_rcv3_s            cn66xx;
+	struct cvmx_sli_msi_rcv3_s            cn68xx;
+	struct cvmx_sli_msi_rcv3_s            cn68xxp1;
+	struct cvmx_sli_msi_rcv3_s            cnf71xx;
 };
 typedef union cvmx_sli_msi_rcv3 cvmx_sli_msi_rcv3_t;
 
@@ -2239,12 +3839,10 @@ typedef union cvmx_sli_msi_rcv3 cvmx_sli_msi_rcv3_t;
  *
  * Used to read the mapping function of the SLI_PCIE_MSI_RCV to SLI_MSI_RCV registers.
  */
-union cvmx_sli_msi_rd_map
-{
+union cvmx_sli_msi_rd_map {
 	uint64_t u64;
-	struct cvmx_sli_msi_rd_map_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_msi_rd_map_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t rd_int                       : 8;  /**< The value of the map at the location PREVIOUSLY
                                                          written to the MSI_INT field of this register. */
@@ -2256,8 +3854,13 @@ union cvmx_sli_msi_rd_map
 	uint64_t reserved_16_63               : 48;
 #endif
 	} s;
+	struct cvmx_sli_msi_rd_map_s          cn61xx;
 	struct cvmx_sli_msi_rd_map_s          cn63xx;
 	struct cvmx_sli_msi_rd_map_s          cn63xxp1;
+	struct cvmx_sli_msi_rd_map_s          cn66xx;
+	struct cvmx_sli_msi_rd_map_s          cn68xx;
+	struct cvmx_sli_msi_rd_map_s          cn68xxp1;
+	struct cvmx_sli_msi_rd_map_s          cnf71xx;
 };
 typedef union cvmx_sli_msi_rd_map cvmx_sli_msi_rd_map_t;
 
@@ -2268,12 +3871,10 @@ typedef union cvmx_sli_msi_rd_map cvmx_sli_msi_rd_map_t;
  *
  * Used to clear bits in SLI_MSI_ENB0.
  */
-union cvmx_sli_msi_w1c_enb0
-{
+union cvmx_sli_msi_w1c_enb0 {
 	uint64_t u64;
-	struct cvmx_sli_msi_w1c_enb0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_msi_w1c_enb0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
                                                          cooresponding bit in SLI_MSI_ENB0.
                                                          A read to this address will return 0. */
@@ -2281,8 +3882,13 @@ union cvmx_sli_msi_w1c_enb0
 	uint64_t clr                          : 64;
 #endif
 	} s;
+	struct cvmx_sli_msi_w1c_enb0_s        cn61xx;
 	struct cvmx_sli_msi_w1c_enb0_s        cn63xx;
 	struct cvmx_sli_msi_w1c_enb0_s        cn63xxp1;
+	struct cvmx_sli_msi_w1c_enb0_s        cn66xx;
+	struct cvmx_sli_msi_w1c_enb0_s        cn68xx;
+	struct cvmx_sli_msi_w1c_enb0_s        cn68xxp1;
+	struct cvmx_sli_msi_w1c_enb0_s        cnf71xx;
 };
 typedef union cvmx_sli_msi_w1c_enb0 cvmx_sli_msi_w1c_enb0_t;
 
@@ -2293,12 +3899,10 @@ typedef union cvmx_sli_msi_w1c_enb0 cvmx_sli_msi_w1c_enb0_t;
  *
  * Used to clear bits in SLI_MSI_ENB1.
  */
-union cvmx_sli_msi_w1c_enb1
-{
+union cvmx_sli_msi_w1c_enb1 {
 	uint64_t u64;
-	struct cvmx_sli_msi_w1c_enb1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_msi_w1c_enb1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
                                                          cooresponding bit in SLI_MSI_ENB1.
                                                          A read to this address will return 0. */
@@ -2306,8 +3910,13 @@ union cvmx_sli_msi_w1c_enb1
 	uint64_t clr                          : 64;
 #endif
 	} s;
+	struct cvmx_sli_msi_w1c_enb1_s        cn61xx;
 	struct cvmx_sli_msi_w1c_enb1_s        cn63xx;
 	struct cvmx_sli_msi_w1c_enb1_s        cn63xxp1;
+	struct cvmx_sli_msi_w1c_enb1_s        cn66xx;
+	struct cvmx_sli_msi_w1c_enb1_s        cn68xx;
+	struct cvmx_sli_msi_w1c_enb1_s        cn68xxp1;
+	struct cvmx_sli_msi_w1c_enb1_s        cnf71xx;
 };
 typedef union cvmx_sli_msi_w1c_enb1 cvmx_sli_msi_w1c_enb1_t;
 
@@ -2318,12 +3927,10 @@ typedef union cvmx_sli_msi_w1c_enb1 cvmx_sli_msi_w1c_enb1_t;
  *
  * Used to clear bits in SLI_MSI_ENB2.
  */
-union cvmx_sli_msi_w1c_enb2
-{
+union cvmx_sli_msi_w1c_enb2 {
 	uint64_t u64;
-	struct cvmx_sli_msi_w1c_enb2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_msi_w1c_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
                                                          cooresponding bit in SLI_MSI_ENB2.
                                                          A read to this address will return 0. */
@@ -2331,8 +3938,13 @@ union cvmx_sli_msi_w1c_enb2
 	uint64_t clr                          : 64;
 #endif
 	} s;
+	struct cvmx_sli_msi_w1c_enb2_s        cn61xx;
 	struct cvmx_sli_msi_w1c_enb2_s        cn63xx;
 	struct cvmx_sli_msi_w1c_enb2_s        cn63xxp1;
+	struct cvmx_sli_msi_w1c_enb2_s        cn66xx;
+	struct cvmx_sli_msi_w1c_enb2_s        cn68xx;
+	struct cvmx_sli_msi_w1c_enb2_s        cn68xxp1;
+	struct cvmx_sli_msi_w1c_enb2_s        cnf71xx;
 };
 typedef union cvmx_sli_msi_w1c_enb2 cvmx_sli_msi_w1c_enb2_t;
 
@@ -2343,12 +3955,10 @@ typedef union cvmx_sli_msi_w1c_enb2 cvmx_sli_msi_w1c_enb2_t;
  *
  * Used to clear bits in SLI_MSI_ENB3.
  */
-union cvmx_sli_msi_w1c_enb3
-{
+union cvmx_sli_msi_w1c_enb3 {
 	uint64_t u64;
-	struct cvmx_sli_msi_w1c_enb3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_msi_w1c_enb3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
                                                          cooresponding bit in SLI_MSI_ENB3.
                                                          A read to this address will return 0. */
@@ -2356,8 +3966,13 @@ union cvmx_sli_msi_w1c_enb3
 	uint64_t clr                          : 64;
 #endif
 	} s;
+	struct cvmx_sli_msi_w1c_enb3_s        cn61xx;
 	struct cvmx_sli_msi_w1c_enb3_s        cn63xx;
 	struct cvmx_sli_msi_w1c_enb3_s        cn63xxp1;
+	struct cvmx_sli_msi_w1c_enb3_s        cn66xx;
+	struct cvmx_sli_msi_w1c_enb3_s        cn68xx;
+	struct cvmx_sli_msi_w1c_enb3_s        cn68xxp1;
+	struct cvmx_sli_msi_w1c_enb3_s        cnf71xx;
 };
 typedef union cvmx_sli_msi_w1c_enb3 cvmx_sli_msi_w1c_enb3_t;
 
@@ -2368,12 +3983,10 @@ typedef union cvmx_sli_msi_w1c_enb3 cvmx_sli_msi_w1c_enb3_t;
  *
  * Used to set bits in SLI_MSI_ENB0.
  */
-union cvmx_sli_msi_w1s_enb0
-{
+union cvmx_sli_msi_w1s_enb0 {
 	uint64_t u64;
-	struct cvmx_sli_msi_w1s_enb0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_msi_w1s_enb0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
                                                          cooresponding bit in SLI_MSI_ENB0.
                                                          A read to this address will return 0. */
@@ -2381,8 +3994,13 @@ union cvmx_sli_msi_w1s_enb0
 	uint64_t set                          : 64;
 #endif
 	} s;
+	struct cvmx_sli_msi_w1s_enb0_s        cn61xx;
 	struct cvmx_sli_msi_w1s_enb0_s        cn63xx;
 	struct cvmx_sli_msi_w1s_enb0_s        cn63xxp1;
+	struct cvmx_sli_msi_w1s_enb0_s        cn66xx;
+	struct cvmx_sli_msi_w1s_enb0_s        cn68xx;
+	struct cvmx_sli_msi_w1s_enb0_s        cn68xxp1;
+	struct cvmx_sli_msi_w1s_enb0_s        cnf71xx;
 };
 typedef union cvmx_sli_msi_w1s_enb0 cvmx_sli_msi_w1s_enb0_t;
 
@@ -2393,12 +4011,10 @@ typedef union cvmx_sli_msi_w1s_enb0 cvmx_sli_msi_w1s_enb0_t;
  *
  * Used to set bits in SLI_MSI_ENB1.
  */
-union cvmx_sli_msi_w1s_enb1
-{
+union cvmx_sli_msi_w1s_enb1 {
 	uint64_t u64;
-	struct cvmx_sli_msi_w1s_enb1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_msi_w1s_enb1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
                                                          cooresponding bit in SLI_MSI_ENB1.
                                                          A read to this address will return 0. */
@@ -2406,8 +4022,13 @@ union cvmx_sli_msi_w1s_enb1
 	uint64_t set                          : 64;
 #endif
 	} s;
+	struct cvmx_sli_msi_w1s_enb1_s        cn61xx;
 	struct cvmx_sli_msi_w1s_enb1_s        cn63xx;
 	struct cvmx_sli_msi_w1s_enb1_s        cn63xxp1;
+	struct cvmx_sli_msi_w1s_enb1_s        cn66xx;
+	struct cvmx_sli_msi_w1s_enb1_s        cn68xx;
+	struct cvmx_sli_msi_w1s_enb1_s        cn68xxp1;
+	struct cvmx_sli_msi_w1s_enb1_s        cnf71xx;
 };
 typedef union cvmx_sli_msi_w1s_enb1 cvmx_sli_msi_w1s_enb1_t;
 
@@ -2418,12 +4039,10 @@ typedef union cvmx_sli_msi_w1s_enb1 cvmx_sli_msi_w1s_enb1_t;
  *
  * Used to set bits in SLI_MSI_ENB2.
  */
-union cvmx_sli_msi_w1s_enb2
-{
+union cvmx_sli_msi_w1s_enb2 {
 	uint64_t u64;
-	struct cvmx_sli_msi_w1s_enb2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_msi_w1s_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
                                                          cooresponding bit in SLI_MSI_ENB2.
                                                          A read to this address will return 0. */
@@ -2431,8 +4050,13 @@ union cvmx_sli_msi_w1s_enb2
 	uint64_t set                          : 64;
 #endif
 	} s;
+	struct cvmx_sli_msi_w1s_enb2_s        cn61xx;
 	struct cvmx_sli_msi_w1s_enb2_s        cn63xx;
 	struct cvmx_sli_msi_w1s_enb2_s        cn63xxp1;
+	struct cvmx_sli_msi_w1s_enb2_s        cn66xx;
+	struct cvmx_sli_msi_w1s_enb2_s        cn68xx;
+	struct cvmx_sli_msi_w1s_enb2_s        cn68xxp1;
+	struct cvmx_sli_msi_w1s_enb2_s        cnf71xx;
 };
 typedef union cvmx_sli_msi_w1s_enb2 cvmx_sli_msi_w1s_enb2_t;
 
@@ -2443,12 +4067,10 @@ typedef union cvmx_sli_msi_w1s_enb2 cvmx_sli_msi_w1s_enb2_t;
  *
  * Used to set bits in SLI_MSI_ENB3.
  */
-union cvmx_sli_msi_w1s_enb3
-{
+union cvmx_sli_msi_w1s_enb3 {
 	uint64_t u64;
-	struct cvmx_sli_msi_w1s_enb3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_msi_w1s_enb3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
                                                          cooresponding bit in SLI_MSI_ENB3.
                                                          A read to this address will return 0. */
@@ -2456,8 +4078,13 @@ union cvmx_sli_msi_w1s_enb3
 	uint64_t set                          : 64;
 #endif
 	} s;
+	struct cvmx_sli_msi_w1s_enb3_s        cn61xx;
 	struct cvmx_sli_msi_w1s_enb3_s        cn63xx;
 	struct cvmx_sli_msi_w1s_enb3_s        cn63xxp1;
+	struct cvmx_sli_msi_w1s_enb3_s        cn66xx;
+	struct cvmx_sli_msi_w1s_enb3_s        cn68xx;
+	struct cvmx_sli_msi_w1s_enb3_s        cn68xxp1;
+	struct cvmx_sli_msi_w1s_enb3_s        cnf71xx;
 };
 typedef union cvmx_sli_msi_w1s_enb3 cvmx_sli_msi_w1s_enb3_t;
 
@@ -2468,12 +4095,10 @@ typedef union cvmx_sli_msi_w1s_enb3 cvmx_sli_msi_w1s_enb3_t;
  *
  * Used to write the mapping function of the SLI_PCIE_MSI_RCV to SLI_MSI_RCV registers.
  */
-union cvmx_sli_msi_wr_map
-{
+union cvmx_sli_msi_wr_map {
 	uint64_t u64;
-	struct cvmx_sli_msi_wr_map_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_msi_wr_map_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t ciu_int                      : 8;  /**< Selects which bit in the SLI_MSI_RCV# (0-255)
                                                          will be set when the value specified in the
@@ -2487,8 +4112,13 @@ union cvmx_sli_msi_wr_map
 	uint64_t reserved_16_63               : 48;
 #endif
 	} s;
+	struct cvmx_sli_msi_wr_map_s          cn61xx;
 	struct cvmx_sli_msi_wr_map_s          cn63xx;
 	struct cvmx_sli_msi_wr_map_s          cn63xxp1;
+	struct cvmx_sli_msi_wr_map_s          cn66xx;
+	struct cvmx_sli_msi_wr_map_s          cn68xx;
+	struct cvmx_sli_msi_wr_map_s          cn68xxp1;
+	struct cvmx_sli_msi_wr_map_s          cnf71xx;
 };
 typedef union cvmx_sli_msi_wr_map cvmx_sli_msi_wr_map_t;
 
@@ -2499,12 +4129,10 @@ typedef union cvmx_sli_msi_wr_map cvmx_sli_msi_wr_map_t;
  *
  * Register where MSI writes are directed from the MAC.
  */
-union cvmx_sli_pcie_msi_rcv
-{
+union cvmx_sli_pcie_msi_rcv {
 	uint64_t u64;
-	struct cvmx_sli_pcie_msi_rcv_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pcie_msi_rcv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
                                                          one of the SLI_MSI_RCV# registers being set.
@@ -2516,8 +4144,13 @@ union cvmx_sli_pcie_msi_rcv
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
+	struct cvmx_sli_pcie_msi_rcv_s        cn61xx;
 	struct cvmx_sli_pcie_msi_rcv_s        cn63xx;
 	struct cvmx_sli_pcie_msi_rcv_s        cn63xxp1;
+	struct cvmx_sli_pcie_msi_rcv_s        cn66xx;
+	struct cvmx_sli_pcie_msi_rcv_s        cn68xx;
+	struct cvmx_sli_pcie_msi_rcv_s        cn68xxp1;
+	struct cvmx_sli_pcie_msi_rcv_s        cnf71xx;
 };
 typedef union cvmx_sli_pcie_msi_rcv cvmx_sli_pcie_msi_rcv_t;
 
@@ -2532,12 +4165,10 @@ typedef union cvmx_sli_pcie_msi_rcv cvmx_sli_pcie_msi_rcv_t;
  * This CSR can be used by PCIe and sRIO MACs.
  *
  */
-union cvmx_sli_pcie_msi_rcv_b1
-{
+union cvmx_sli_pcie_msi_rcv_b1 {
 	uint64_t u64;
-	struct cvmx_sli_pcie_msi_rcv_b1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pcie_msi_rcv_b1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
                                                          one of the SLI_MSI_RCV# registers being set.
@@ -2551,8 +4182,13 @@ union cvmx_sli_pcie_msi_rcv_b1
 	uint64_t reserved_16_63               : 48;
 #endif
 	} s;
+	struct cvmx_sli_pcie_msi_rcv_b1_s     cn61xx;
 	struct cvmx_sli_pcie_msi_rcv_b1_s     cn63xx;
 	struct cvmx_sli_pcie_msi_rcv_b1_s     cn63xxp1;
+	struct cvmx_sli_pcie_msi_rcv_b1_s     cn66xx;
+	struct cvmx_sli_pcie_msi_rcv_b1_s     cn68xx;
+	struct cvmx_sli_pcie_msi_rcv_b1_s     cn68xxp1;
+	struct cvmx_sli_pcie_msi_rcv_b1_s     cnf71xx;
 };
 typedef union cvmx_sli_pcie_msi_rcv_b1 cvmx_sli_pcie_msi_rcv_b1_t;
 
@@ -2567,12 +4203,10 @@ typedef union cvmx_sli_pcie_msi_rcv_b1 cvmx_sli_pcie_msi_rcv_b1_t;
  * This CSR can be used by PCIe and sRIO MACs.
  *
  */
-union cvmx_sli_pcie_msi_rcv_b2
-{
+union cvmx_sli_pcie_msi_rcv_b2 {
 	uint64_t u64;
-	struct cvmx_sli_pcie_msi_rcv_b2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pcie_msi_rcv_b2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
                                                          one of the SLI_MSI_RCV# registers being set.
@@ -2586,8 +4220,13 @@ union cvmx_sli_pcie_msi_rcv_b2
 	uint64_t reserved_24_63               : 40;
 #endif
 	} s;
+	struct cvmx_sli_pcie_msi_rcv_b2_s     cn61xx;
 	struct cvmx_sli_pcie_msi_rcv_b2_s     cn63xx;
 	struct cvmx_sli_pcie_msi_rcv_b2_s     cn63xxp1;
+	struct cvmx_sli_pcie_msi_rcv_b2_s     cn66xx;
+	struct cvmx_sli_pcie_msi_rcv_b2_s     cn68xx;
+	struct cvmx_sli_pcie_msi_rcv_b2_s     cn68xxp1;
+	struct cvmx_sli_pcie_msi_rcv_b2_s     cnf71xx;
 };
 typedef union cvmx_sli_pcie_msi_rcv_b2 cvmx_sli_pcie_msi_rcv_b2_t;
 
@@ -2602,12 +4241,10 @@ typedef union cvmx_sli_pcie_msi_rcv_b2 cvmx_sli_pcie_msi_rcv_b2_t;
  * This CSR can be used by PCIe and sRIO MACs.
  *
  */
-union cvmx_sli_pcie_msi_rcv_b3
-{
+union cvmx_sli_pcie_msi_rcv_b3 {
 	uint64_t u64;
-	struct cvmx_sli_pcie_msi_rcv_b3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pcie_msi_rcv_b3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
                                                          one of the SLI_MSI_RCV# registers being set.
@@ -2621,8 +4258,13 @@ union cvmx_sli_pcie_msi_rcv_b3
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pcie_msi_rcv_b3_s     cn61xx;
 	struct cvmx_sli_pcie_msi_rcv_b3_s     cn63xx;
 	struct cvmx_sli_pcie_msi_rcv_b3_s     cn63xxp1;
+	struct cvmx_sli_pcie_msi_rcv_b3_s     cn66xx;
+	struct cvmx_sli_pcie_msi_rcv_b3_s     cn68xx;
+	struct cvmx_sli_pcie_msi_rcv_b3_s     cn68xxp1;
+	struct cvmx_sli_pcie_msi_rcv_b3_s     cnf71xx;
 };
 typedef union cvmx_sli_pcie_msi_rcv_b3 cvmx_sli_pcie_msi_rcv_b3_t;
 
@@ -2633,12 +4275,10 @@ typedef union cvmx_sli_pcie_msi_rcv_b3 cvmx_sli_pcie_msi_rcv_b3_t;
  *
  * The counters for output rings.
  */
-union cvmx_sli_pktx_cnts
-{
+union cvmx_sli_pktx_cnts {
 	uint64_t u64;
-	struct cvmx_sli_pktx_cnts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pktx_cnts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_54_63               : 10;
 	uint64_t timer                        : 22; /**< Timer incremented every 1024 core clocks
                                                          when SLI_PKTS#_CNTS[CNT] is non zero. Field
@@ -2662,8 +4302,13 @@ union cvmx_sli_pktx_cnts
 	uint64_t reserved_54_63               : 10;
 #endif
 	} s;
+	struct cvmx_sli_pktx_cnts_s           cn61xx;
 	struct cvmx_sli_pktx_cnts_s           cn63xx;
 	struct cvmx_sli_pktx_cnts_s           cn63xxp1;
+	struct cvmx_sli_pktx_cnts_s           cn66xx;
+	struct cvmx_sli_pktx_cnts_s           cn68xx;
+	struct cvmx_sli_pktx_cnts_s           cn68xxp1;
+	struct cvmx_sli_pktx_cnts_s           cnf71xx;
 };
 typedef union cvmx_sli_pktx_cnts cvmx_sli_pktx_cnts_t;
 
@@ -2674,12 +4319,10 @@ typedef union cvmx_sli_pktx_cnts cvmx_sli_pktx_cnts_t;
  *
  * The counters and thresholds for input packets to apply backpressure to processing of the packets.
  */
-union cvmx_sli_pktx_in_bp
-{
+union cvmx_sli_pktx_in_bp {
 	uint64_t u64;
-	struct cvmx_sli_pktx_in_bp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pktx_in_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t wmark                        : 32; /**< When CNT is greater than this threshold no more
                                                          packets will be processed for this ring.
                                                          When writing this field of the SLI_PKT#_IN_BP
@@ -2698,8 +4341,11 @@ union cvmx_sli_pktx_in_bp
 	uint64_t wmark                        : 32;
 #endif
 	} s;
+	struct cvmx_sli_pktx_in_bp_s          cn61xx;
 	struct cvmx_sli_pktx_in_bp_s          cn63xx;
 	struct cvmx_sli_pktx_in_bp_s          cn63xxp1;
+	struct cvmx_sli_pktx_in_bp_s          cn66xx;
+	struct cvmx_sli_pktx_in_bp_s          cnf71xx;
 };
 typedef union cvmx_sli_pktx_in_bp cvmx_sli_pktx_in_bp_t;
 
@@ -2710,12 +4356,10 @@ typedef union cvmx_sli_pktx_in_bp cvmx_sli_pktx_in_bp_t;
  *
  * Start of Instruction for input packets.
  */
-union cvmx_sli_pktx_instr_baddr
-{
+union cvmx_sli_pktx_instr_baddr {
 	uint64_t u64;
-	struct cvmx_sli_pktx_instr_baddr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pktx_instr_baddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t addr                         : 61; /**< Base address for Instructions. */
 	uint64_t reserved_0_2                 : 3;
 #else
@@ -2723,8 +4367,13 @@ union cvmx_sli_pktx_instr_baddr
 	uint64_t addr                         : 61;
 #endif
 	} s;
+	struct cvmx_sli_pktx_instr_baddr_s    cn61xx;
 	struct cvmx_sli_pktx_instr_baddr_s    cn63xx;
 	struct cvmx_sli_pktx_instr_baddr_s    cn63xxp1;
+	struct cvmx_sli_pktx_instr_baddr_s    cn66xx;
+	struct cvmx_sli_pktx_instr_baddr_s    cn68xx;
+	struct cvmx_sli_pktx_instr_baddr_s    cn68xxp1;
+	struct cvmx_sli_pktx_instr_baddr_s    cnf71xx;
 };
 typedef union cvmx_sli_pktx_instr_baddr cvmx_sli_pktx_instr_baddr_t;
 
@@ -2735,12 +4384,10 @@ typedef union cvmx_sli_pktx_instr_baddr cvmx_sli_pktx_instr_baddr_t;
  *
  * The doorbell and base address offset for next read.
  */
-union cvmx_sli_pktx_instr_baoff_dbell
-{
+union cvmx_sli_pktx_instr_baoff_dbell {
 	uint64_t u64;
-	struct cvmx_sli_pktx_instr_baoff_dbell_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pktx_instr_baoff_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t aoff                         : 32; /**< The offset from the SLI_PKT[0..31]_INSTR_BADDR
                                                          where the next instruction will be read. */
 	uint64_t dbell                        : 32; /**< Instruction doorbell count. Writes to this field
@@ -2752,8 +4399,13 @@ union cvmx_sli_pktx_instr_baoff_dbell
 	uint64_t aoff                         : 32;
 #endif
 	} s;
+	struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx;
 	struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx;
 	struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1;
+	struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx;
+	struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx;
+	struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1;
+	struct cvmx_sli_pktx_instr_baoff_dbell_s cnf71xx;
 };
 typedef union cvmx_sli_pktx_instr_baoff_dbell cvmx_sli_pktx_instr_baoff_dbell_t;
 
@@ -2764,12 +4416,10 @@ typedef union cvmx_sli_pktx_instr_baoff_dbell cvmx_sli_pktx_instr_baoff_dbell_t;
  *
  * Fifo field and ring size for Instructions.
  */
-union cvmx_sli_pktx_instr_fifo_rsize
-{
+union cvmx_sli_pktx_instr_fifo_rsize {
 	uint64_t u64;
-	struct cvmx_sli_pktx_instr_fifo_rsize_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pktx_instr_fifo_rsize_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t max                          : 9;  /**< Max Fifo Size. */
 	uint64_t rrp                          : 9;  /**< Fifo read pointer. */
 	uint64_t wrp                          : 9;  /**< Fifo write pointer. */
@@ -2783,8 +4433,13 @@ union cvmx_sli_pktx_instr_fifo_rsize
 	uint64_t max                          : 9;
 #endif
 	} s;
+	struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx;
 	struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx;
 	struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1;
+	struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx;
+	struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx;
+	struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1;
+	struct cvmx_sli_pktx_instr_fifo_rsize_s cnf71xx;
 };
 typedef union cvmx_sli_pktx_instr_fifo_rsize cvmx_sli_pktx_instr_fifo_rsize_t;
 
@@ -2795,38 +4450,118 @@ typedef union cvmx_sli_pktx_instr_fifo_rsize cvmx_sli_pktx_instr_fifo_rsize_t;
  *
  * VAlues used to build input packet header.
  */
-union cvmx_sli_pktx_instr_header
-{
+union cvmx_sli_pktx_instr_header {
 	uint64_t u64;
-	struct cvmx_sli_pktx_instr_header_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pktx_instr_header_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_44_63               : 20;
-	uint64_t pbp                          : 1;  /**< Enable Packet-by-packet mode. */
+	uint64_t pbp                          : 1;  /**< Enable Packet-by-packet mode.
+                                                         Allows DPI to generate PKT_INST_HDR[PM,SL]
+                                                         differently per DPI instruction.
+                                                         USE_IHDR must be set whenever PBP is set. */
 	uint64_t reserved_38_42               : 5;
-	uint64_t rparmode                     : 2;  /**< Parse Mode. Used when packet is raw and PBP==0. */
+	uint64_t rparmode                     : 2;  /**< Parse Mode. Becomes PKT_INST_HDR[PM]
+                                                         when DPI_INST_HDR[R]==1 and PBP==0 */
 	uint64_t reserved_35_35               : 1;
-	uint64_t rskp_len                     : 7;  /**< Skip Length. Used when packet is raw and PBP==0. */
+	uint64_t rskp_len                     : 7;  /**< Skip Length. Becomes PKT_INST_HDR[SL]
+                                                         when DPI_INST_HDR[R]==1 and PBP==0 */
+	uint64_t rngrpext                     : 2;  /**< Becomes PKT_INST_HDR[GRPEXT]
+                                                         when DPI_INST_HDR[R]==1 */
+	uint64_t rnqos                        : 1;  /**< Becomes PKT_INST_HDR[NQOS]
+                                                         when DPI_INST_HDR[R]==1 */
+	uint64_t rngrp                        : 1;  /**< Becomes PKT_INST_HDR[NGRP]
+                                                         when DPI_INST_HDR[R]==1 */
+	uint64_t rntt                         : 1;  /**< Becomes PKT_INST_HDR[NTT]
+                                                         when DPI_INST_HDR[R]==1 */
+	uint64_t rntag                        : 1;  /**< Becomes PKT_INST_HDR[NTAG]
+                                                         when DPI_INST_HDR[R]==1 */
+	uint64_t use_ihdr                     : 1;  /**< When set '1' DPI always prepends a PKT_INST_HDR
+                                                         as part of the packet data sent to PIP/IPD,
+                                                         regardless of DPI_INST_HDR[R]. (DPI also always
+                                                         prepends a PKT_INST_HDR when DPI_INST_HDR[R]=1.)
+                                                         USE_IHDR must be set whenever PBP is set. */
+	uint64_t reserved_16_20               : 5;
+	uint64_t par_mode                     : 2;  /**< Parse Mode. Becomes PKT_INST_HDR[PM]
+                                                         when DPI_INST_HDR[R]==0 and USE_IHDR==1 and PBP==0 */
+	uint64_t reserved_13_13               : 1;
+	uint64_t skp_len                      : 7;  /**< Skip Length. Becomes PKT_INST_HDR[SL]
+                                                         when DPI_INST_HDR[R]==0 and USE_IHDR==1 and PBP==0 */
+	uint64_t ngrpext                      : 2;  /**< Becomes PKT_INST_HDR[GRPEXT]
+                                                         when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */
+	uint64_t nqos                         : 1;  /**< Becomes PKT_INST_HDR[NQOS]
+                                                         when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */
+	uint64_t ngrp                         : 1;  /**< Becomes PKT_INST_HDR[NGRP]
+                                                         when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */
+	uint64_t ntt                          : 1;  /**< Becomes PKT_INST_HDR[NTT]
+                                                         when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */
+	uint64_t ntag                         : 1;  /**< Becomes PKT_INST_HDR[NTAG]
+                                                         when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */
+#else
+	uint64_t ntag                         : 1;
+	uint64_t ntt                          : 1;
+	uint64_t ngrp                         : 1;
+	uint64_t nqos                         : 1;
+	uint64_t ngrpext                      : 2;
+	uint64_t skp_len                      : 7;
+	uint64_t reserved_13_13               : 1;
+	uint64_t par_mode                     : 2;
+	uint64_t reserved_16_20               : 5;
+	uint64_t use_ihdr                     : 1;
+	uint64_t rntag                        : 1;
+	uint64_t rntt                         : 1;
+	uint64_t rngrp                        : 1;
+	uint64_t rnqos                        : 1;
+	uint64_t rngrpext                     : 2;
+	uint64_t rskp_len                     : 7;
+	uint64_t reserved_35_35               : 1;
+	uint64_t rparmode                     : 2;
+	uint64_t reserved_38_42               : 5;
+	uint64_t pbp                          : 1;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_sli_pktx_instr_header_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_44_63               : 20;
+	uint64_t pbp                          : 1;  /**< Enable Packet-by-packet mode.
+                                                         Allows DPI to generate PKT_INST_HDR[PM,SL]
+                                                         differently per DPI instruction.
+                                                         USE_IHDR must be set whenever PBP is set. */
+	uint64_t reserved_38_42               : 5;
+	uint64_t rparmode                     : 2;  /**< Parse Mode. Becomes PKT_INST_HDR[PM]
+                                                         when DPI_INST_HDR[R]==1 and PBP==0 */
+	uint64_t reserved_35_35               : 1;
+	uint64_t rskp_len                     : 7;  /**< Skip Length. Becomes PKT_INST_HDR[SL]
+                                                         when DPI_INST_HDR[R]==1 and PBP==0 */
 	uint64_t reserved_26_27               : 2;
-	uint64_t rnqos                        : 1;  /**< RNQOS. Used when packet is raw and PBP==0. */
-	uint64_t rngrp                        : 1;  /**< RNGRP. Used when packet is raw and PBP==0. */
-	uint64_t rntt                         : 1;  /**< RNTT. Used when packet is raw and PBP==0. */
-	uint64_t rntag                        : 1;  /**< RNTAG. Used when packet is raw and PBP==0. */
-	uint64_t use_ihdr                     : 1;  /**< When set '1' the instruction header will be sent
-                                                         as part of the packet data, regardless of the
-                                                         value of bit [63] of the instruction header.
+	uint64_t rnqos                        : 1;  /**< Becomes PKT_INST_HDR[NQOS]
+                                                         when DPI_INST_HDR[R]==1 */
+	uint64_t rngrp                        : 1;  /**< Becomes PKT_INST_HDR[NGRP]
+                                                         when DPI_INST_HDR[R]==1 */
+	uint64_t rntt                         : 1;  /**< Becomes PKT_INST_HDR[NTT]
+                                                         when DPI_INST_HDR[R]==1 */
+	uint64_t rntag                        : 1;  /**< Becomes PKT_INST_HDR[NTAG]
+                                                         when DPI_INST_HDR[R]==1 */
+	uint64_t use_ihdr                     : 1;  /**< When set '1' DPI always prepends a PKT_INST_HDR
+                                                         as part of the packet data sent to PIP/IPD,
+                                                         regardless of DPI_INST_HDR[R]. (DPI also always
+                                                         prepends a PKT_INST_HDR when DPI_INST_HDR[R]=1.)
                                                          USE_IHDR must be set whenever PBP is set. */
 	uint64_t reserved_16_20               : 5;
-	uint64_t par_mode                     : 2;  /**< Parse Mode. Used when USE_IHDR is set and packet
-                                                         is not raw and PBP is not set. */
+	uint64_t par_mode                     : 2;  /**< Parse Mode. Becomes PKT_INST_HDR[PM]
+                                                         when DPI_INST_HDR[R]==0 and USE_IHDR==1 and PBP==0 */
 	uint64_t reserved_13_13               : 1;
-	uint64_t skp_len                      : 7;  /**< Skip Length. Used when USE_IHDR is set and packet
-                                                         is not raw and PBP is not set. */
+	uint64_t skp_len                      : 7;  /**< Skip Length. Becomes PKT_INST_HDR[SL]
+                                                         when DPI_INST_HDR[R]==0 and USE_IHDR==1 and PBP==0 */
 	uint64_t reserved_4_5                 : 2;
-	uint64_t nqos                         : 1;  /**< NQOS. Used when packet is raw and PBP==0. */
-	uint64_t ngrp                         : 1;  /**< NGRP. Used when packet is raw and PBP==0. */
-	uint64_t ntt                          : 1;  /**< NTT. Used when packet is raw and PBP==0. */
-	uint64_t ntag                         : 1;  /**< NTAG. Used when packet is raw and PBP==0. */
+	uint64_t nqos                         : 1;  /**< Becomes PKT_INST_HDR[NQOS]
+                                                         when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */
+	uint64_t ngrp                         : 1;  /**< Becomes PKT_INST_HDR[NGRP]
+                                                         when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */
+	uint64_t ntt                          : 1;  /**< Becomes PKT_INST_HDR[NTT]
+                                                         when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */
+	uint64_t ntag                         : 1;  /**< Becomes PKT_INST_HDR[NTAG]
+                                                         when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */
 #else
 	uint64_t ntag                         : 1;
 	uint64_t ntt                          : 1;
@@ -2850,9 +4585,13 @@ union cvmx_sli_pktx_instr_header
 	uint64_t pbp                          : 1;
 	uint64_t reserved_44_63               : 20;
 #endif
-	} s;
-	struct cvmx_sli_pktx_instr_header_s   cn63xx;
-	struct cvmx_sli_pktx_instr_header_s   cn63xxp1;
+	} cn61xx;
+	struct cvmx_sli_pktx_instr_header_cn61xx cn63xx;
+	struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1;
+	struct cvmx_sli_pktx_instr_header_cn61xx cn66xx;
+	struct cvmx_sli_pktx_instr_header_s   cn68xx;
+	struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1;
+	struct cvmx_sli_pktx_instr_header_cn61xx cnf71xx;
 };
 typedef union cvmx_sli_pktx_instr_header cvmx_sli_pktx_instr_header_t;
 
@@ -2863,12 +4602,10 @@ typedef union cvmx_sli_pktx_instr_header cvmx_sli_pktx_instr_header_t;
  *
  * Contains the BSIZE and ISIZE for output packet ports.
  */
-union cvmx_sli_pktx_out_size
-{
+union cvmx_sli_pktx_out_size {
 	uint64_t u64;
-	struct cvmx_sli_pktx_out_size_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pktx_out_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_23_63               : 41;
 	uint64_t isize                        : 7;  /**< INFO BYTES size (bytes) for ring X. Legal sizes
                                                          are 0 to 120. Not used in buffer-pointer-only mode. */
@@ -2879,8 +4616,13 @@ union cvmx_sli_pktx_out_size
 	uint64_t reserved_23_63               : 41;
 #endif
 	} s;
+	struct cvmx_sli_pktx_out_size_s       cn61xx;
 	struct cvmx_sli_pktx_out_size_s       cn63xx;
 	struct cvmx_sli_pktx_out_size_s       cn63xxp1;
+	struct cvmx_sli_pktx_out_size_s       cn66xx;
+	struct cvmx_sli_pktx_out_size_s       cn68xx;
+	struct cvmx_sli_pktx_out_size_s       cn68xxp1;
+	struct cvmx_sli_pktx_out_size_s       cnf71xx;
 };
 typedef union cvmx_sli_pktx_out_size cvmx_sli_pktx_out_size_t;
 
@@ -2891,12 +4633,10 @@ typedef union cvmx_sli_pktx_out_size cvmx_sli_pktx_out_size_t;
  *
  * Start of Scatter List for output packet pointers - MUST be 16 byte alligned
  */
-union cvmx_sli_pktx_slist_baddr
-{
+union cvmx_sli_pktx_slist_baddr {
 	uint64_t u64;
-	struct cvmx_sli_pktx_slist_baddr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pktx_slist_baddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t addr                         : 60; /**< Base address for scatter list pointers. */
 	uint64_t reserved_0_3                 : 4;
 #else
@@ -2904,8 +4644,13 @@ union cvmx_sli_pktx_slist_baddr
 	uint64_t addr                         : 60;
 #endif
 	} s;
+	struct cvmx_sli_pktx_slist_baddr_s    cn61xx;
 	struct cvmx_sli_pktx_slist_baddr_s    cn63xx;
 	struct cvmx_sli_pktx_slist_baddr_s    cn63xxp1;
+	struct cvmx_sli_pktx_slist_baddr_s    cn66xx;
+	struct cvmx_sli_pktx_slist_baddr_s    cn68xx;
+	struct cvmx_sli_pktx_slist_baddr_s    cn68xxp1;
+	struct cvmx_sli_pktx_slist_baddr_s    cnf71xx;
 };
 typedef union cvmx_sli_pktx_slist_baddr cvmx_sli_pktx_slist_baddr_t;
 
@@ -2916,12 +4661,10 @@ typedef union cvmx_sli_pktx_slist_baddr cvmx_sli_pktx_slist_baddr_t;
  *
  * The doorbell and base address offset for next read.
  */
-union cvmx_sli_pktx_slist_baoff_dbell
-{
+union cvmx_sli_pktx_slist_baoff_dbell {
 	uint64_t u64;
-	struct cvmx_sli_pktx_slist_baoff_dbell_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pktx_slist_baoff_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t aoff                         : 32; /**< The offset from the SLI_PKT[0..31]_SLIST_BADDR
                                                          where the next SList pointer will be read.
                                                          A write of 0xFFFFFFFF to the DBELL field will
@@ -2937,8 +4680,13 @@ union cvmx_sli_pktx_slist_baoff_dbell
 	uint64_t aoff                         : 32;
 #endif
 	} s;
+	struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx;
 	struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx;
 	struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1;
+	struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx;
+	struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx;
+	struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1;
+	struct cvmx_sli_pktx_slist_baoff_dbell_s cnf71xx;
 };
 typedef union cvmx_sli_pktx_slist_baoff_dbell cvmx_sli_pktx_slist_baoff_dbell_t;
 
@@ -2949,12 +4697,10 @@ typedef union cvmx_sli_pktx_slist_baoff_dbell cvmx_sli_pktx_slist_baoff_dbell_t;
  *
  * The number of scatter pointer pairs in the scatter list.
  */
-union cvmx_sli_pktx_slist_fifo_rsize
-{
+union cvmx_sli_pktx_slist_fifo_rsize {
 	uint64_t u64;
-	struct cvmx_sli_pktx_slist_fifo_rsize_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pktx_slist_fifo_rsize_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t rsize                        : 32; /**< The number of scatter pointer pairs contained in
                                                          the scatter list ring. */
@@ -2963,8 +4709,13 @@ union cvmx_sli_pktx_slist_fifo_rsize
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx;
 	struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx;
 	struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1;
+	struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx;
+	struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx;
+	struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1;
+	struct cvmx_sli_pktx_slist_fifo_rsize_s cnf71xx;
 };
 typedef union cvmx_sli_pktx_slist_fifo_rsize cvmx_sli_pktx_slist_fifo_rsize_t;
 
@@ -2975,12 +4726,10 @@ typedef union cvmx_sli_pktx_slist_fifo_rsize cvmx_sli_pktx_slist_fifo_rsize_t;
  *
  * The packets rings that are interrupting because of Packet Counters.
  */
-union cvmx_sli_pkt_cnt_int
-{
+union cvmx_sli_pkt_cnt_int {
 	uint64_t u64;
-	struct cvmx_sli_pkt_cnt_int_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_cnt_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t port                         : 32; /**< Output ring packet counter interrupt bits
                                                          SLI sets PORT<i> whenever
@@ -2992,8 +4741,13 @@ union cvmx_sli_pkt_cnt_int
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_cnt_int_s         cn61xx;
 	struct cvmx_sli_pkt_cnt_int_s         cn63xx;
 	struct cvmx_sli_pkt_cnt_int_s         cn63xxp1;
+	struct cvmx_sli_pkt_cnt_int_s         cn66xx;
+	struct cvmx_sli_pkt_cnt_int_s         cn68xx;
+	struct cvmx_sli_pkt_cnt_int_s         cn68xxp1;
+	struct cvmx_sli_pkt_cnt_int_s         cnf71xx;
 };
 typedef union cvmx_sli_pkt_cnt_int cvmx_sli_pkt_cnt_int_t;
 
@@ -3004,12 +4758,10 @@ typedef union cvmx_sli_pkt_cnt_int cvmx_sli_pkt_cnt_int_t;
  *
  * Enable for the packets rings that are interrupting because of Packet Counters.
  */
-union cvmx_sli_pkt_cnt_int_enb
-{
+union cvmx_sli_pkt_cnt_int_enb {
 	uint64_t u64;
-	struct cvmx_sli_pkt_cnt_int_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_cnt_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t port                         : 32; /**< Output ring packet counter interrupt enables
                                                          When both PORT<i> and corresponding
@@ -3021,8 +4773,13 @@ union cvmx_sli_pkt_cnt_int_enb
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_cnt_int_enb_s     cn61xx;
 	struct cvmx_sli_pkt_cnt_int_enb_s     cn63xx;
 	struct cvmx_sli_pkt_cnt_int_enb_s     cn63xxp1;
+	struct cvmx_sli_pkt_cnt_int_enb_s     cn66xx;
+	struct cvmx_sli_pkt_cnt_int_enb_s     cn68xx;
+	struct cvmx_sli_pkt_cnt_int_enb_s     cn68xxp1;
+	struct cvmx_sli_pkt_cnt_int_enb_s     cnf71xx;
 };
 typedef union cvmx_sli_pkt_cnt_int_enb cvmx_sli_pkt_cnt_int_enb_t;
 
@@ -3033,12 +4790,10 @@ typedef union cvmx_sli_pkt_cnt_int_enb cvmx_sli_pkt_cnt_int_enb_t;
  *
  * Control for packets.
  */
-union cvmx_sli_pkt_ctl
-{
+union cvmx_sli_pkt_ctl {
 	uint64_t u64;
-	struct cvmx_sli_pkt_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t ring_en                      : 1;  /**< When '0' forces "relative Q position" received
                                                          from PKO to be zero, and replicates the back-
@@ -3054,8 +4809,13 @@ union cvmx_sli_pkt_ctl
 	uint64_t reserved_5_63                : 59;
 #endif
 	} s;
+	struct cvmx_sli_pkt_ctl_s             cn61xx;
 	struct cvmx_sli_pkt_ctl_s             cn63xx;
 	struct cvmx_sli_pkt_ctl_s             cn63xxp1;
+	struct cvmx_sli_pkt_ctl_s             cn66xx;
+	struct cvmx_sli_pkt_ctl_s             cn68xx;
+	struct cvmx_sli_pkt_ctl_s             cn68xxp1;
+	struct cvmx_sli_pkt_ctl_s             cnf71xx;
 };
 typedef union cvmx_sli_pkt_ctl cvmx_sli_pkt_ctl_t;
 
@@ -3066,12 +4826,10 @@ typedef union cvmx_sli_pkt_ctl cvmx_sli_pkt_ctl_t;
  *
  * The Endian Swap for writing Data Out.
  */
-union cvmx_sli_pkt_data_out_es
-{
+union cvmx_sli_pkt_data_out_es {
 	uint64_t u64;
-	struct cvmx_sli_pkt_data_out_es_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_data_out_es_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t es                           : 64; /**< ES<1:0> or MACADD<63:62> for buffer/info writes.
                                                          ES<2i+1:2i> becomes either ES<1:0> or
                                                          MACADD<63:62> for writes to buffer/info pair
@@ -3085,8 +4843,13 @@ union cvmx_sli_pkt_data_out_es
 	uint64_t es                           : 64;
 #endif
 	} s;
+	struct cvmx_sli_pkt_data_out_es_s     cn61xx;
 	struct cvmx_sli_pkt_data_out_es_s     cn63xx;
 	struct cvmx_sli_pkt_data_out_es_s     cn63xxp1;
+	struct cvmx_sli_pkt_data_out_es_s     cn66xx;
+	struct cvmx_sli_pkt_data_out_es_s     cn68xx;
+	struct cvmx_sli_pkt_data_out_es_s     cn68xxp1;
+	struct cvmx_sli_pkt_data_out_es_s     cnf71xx;
 };
 typedef union cvmx_sli_pkt_data_out_es cvmx_sli_pkt_data_out_es_t;
 
@@ -3097,12 +4860,10 @@ typedef union cvmx_sli_pkt_data_out_es cvmx_sli_pkt_data_out_es_t;
  *
  * The NS field for the TLP when writing packet data.
  */
-union cvmx_sli_pkt_data_out_ns
-{
+union cvmx_sli_pkt_data_out_ns {
 	uint64_t u64;
-	struct cvmx_sli_pkt_data_out_ns_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_data_out_ns_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t nsr                          : 32; /**< ADDRTYPE<1> or MACADD<61> for buffer/info writes.
                                                          NSR<i> becomes either ADDRTYPE<1> or MACADD<61>
@@ -3118,8 +4879,13 @@ union cvmx_sli_pkt_data_out_ns
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_data_out_ns_s     cn61xx;
 	struct cvmx_sli_pkt_data_out_ns_s     cn63xx;
 	struct cvmx_sli_pkt_data_out_ns_s     cn63xxp1;
+	struct cvmx_sli_pkt_data_out_ns_s     cn66xx;
+	struct cvmx_sli_pkt_data_out_ns_s     cn68xx;
+	struct cvmx_sli_pkt_data_out_ns_s     cn68xxp1;
+	struct cvmx_sli_pkt_data_out_ns_s     cnf71xx;
 };
 typedef union cvmx_sli_pkt_data_out_ns cvmx_sli_pkt_data_out_ns_t;
 
@@ -3130,12 +4896,10 @@ typedef union cvmx_sli_pkt_data_out_ns cvmx_sli_pkt_data_out_ns_t;
  *
  * The ROR field for the TLP when writing Packet Data.
  */
-union cvmx_sli_pkt_data_out_ror
-{
+union cvmx_sli_pkt_data_out_ror {
 	uint64_t u64;
-	struct cvmx_sli_pkt_data_out_ror_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_data_out_ror_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t ror                          : 32; /**< ADDRTYPE<0> or MACADD<60> for buffer/info writes.
                                                          ROR<i> becomes either ADDRTYPE<0> or MACADD<60>
@@ -3151,8 +4915,13 @@ union cvmx_sli_pkt_data_out_ror
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_data_out_ror_s    cn61xx;
 	struct cvmx_sli_pkt_data_out_ror_s    cn63xx;
 	struct cvmx_sli_pkt_data_out_ror_s    cn63xxp1;
+	struct cvmx_sli_pkt_data_out_ror_s    cn66xx;
+	struct cvmx_sli_pkt_data_out_ror_s    cn68xx;
+	struct cvmx_sli_pkt_data_out_ror_s    cn68xxp1;
+	struct cvmx_sli_pkt_data_out_ror_s    cnf71xx;
 };
 typedef union cvmx_sli_pkt_data_out_ror cvmx_sli_pkt_data_out_ror_t;
 
@@ -3163,12 +4932,10 @@ typedef union cvmx_sli_pkt_data_out_ror cvmx_sli_pkt_data_out_ror_t;
  *
  * Used to detemine address and attributes for packet data writes.
  */
-union cvmx_sli_pkt_dpaddr
-{
+union cvmx_sli_pkt_dpaddr {
 	uint64_t u64;
-	struct cvmx_sli_pkt_dpaddr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_dpaddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t dptr                         : 32; /**< Determines whether buffer/info pointers are
                                                          DPTR format 0 or DPTR format 1.
@@ -3187,8 +4954,13 @@ union cvmx_sli_pkt_dpaddr
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_dpaddr_s          cn61xx;
 	struct cvmx_sli_pkt_dpaddr_s          cn63xx;
 	struct cvmx_sli_pkt_dpaddr_s          cn63xxp1;
+	struct cvmx_sli_pkt_dpaddr_s          cn66xx;
+	struct cvmx_sli_pkt_dpaddr_s          cn68xx;
+	struct cvmx_sli_pkt_dpaddr_s          cn68xxp1;
+	struct cvmx_sli_pkt_dpaddr_s          cnf71xx;
 };
 typedef union cvmx_sli_pkt_dpaddr cvmx_sli_pkt_dpaddr_t;
 
@@ -3199,12 +4971,10 @@ typedef union cvmx_sli_pkt_dpaddr cvmx_sli_pkt_dpaddr_t;
  *
  * Which input rings have backpressure applied.
  */
-union cvmx_sli_pkt_in_bp
-{
+union cvmx_sli_pkt_in_bp {
 	uint64_t u64;
-	struct cvmx_sli_pkt_in_bp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_in_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t bp                           : 32; /**< A packet input  ring that has its count greater
                                                          than its WMARK will have backpressure applied.
@@ -3217,8 +4987,11 @@ union cvmx_sli_pkt_in_bp
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_in_bp_s           cn61xx;
 	struct cvmx_sli_pkt_in_bp_s           cn63xx;
 	struct cvmx_sli_pkt_in_bp_s           cn63xxp1;
+	struct cvmx_sli_pkt_in_bp_s           cn66xx;
+	struct cvmx_sli_pkt_in_bp_s           cnf71xx;
 };
 typedef union cvmx_sli_pkt_in_bp cvmx_sli_pkt_in_bp_t;
 
@@ -3229,12 +5002,10 @@ typedef union cvmx_sli_pkt_in_bp cvmx_sli_pkt_in_bp_t;
  *
  * Counters for instructions completed on Input rings.
  */
-union cvmx_sli_pkt_in_donex_cnts
-{
+union cvmx_sli_pkt_in_donex_cnts {
 	uint64_t u64;
-	struct cvmx_sli_pkt_in_donex_cnts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_in_donex_cnts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< This field is incrmented by '1' when an instruction
                                                          is completed. This field is incremented as the
@@ -3244,8 +5015,13 @@ union cvmx_sli_pkt_in_donex_cnts
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_in_donex_cnts_s   cn61xx;
 	struct cvmx_sli_pkt_in_donex_cnts_s   cn63xx;
 	struct cvmx_sli_pkt_in_donex_cnts_s   cn63xxp1;
+	struct cvmx_sli_pkt_in_donex_cnts_s   cn66xx;
+	struct cvmx_sli_pkt_in_donex_cnts_s   cn68xx;
+	struct cvmx_sli_pkt_in_donex_cnts_s   cn68xxp1;
+	struct cvmx_sli_pkt_in_donex_cnts_s   cnf71xx;
 };
 typedef union cvmx_sli_pkt_in_donex_cnts cvmx_sli_pkt_in_donex_cnts_t;
 
@@ -3256,12 +5032,10 @@ typedef union cvmx_sli_pkt_in_donex_cnts cvmx_sli_pkt_in_donex_cnts_t;
  *
  * Keeps track of the number of instructions read into the FIFO and Packets sent to IPD.
  */
-union cvmx_sli_pkt_in_instr_counts
-{
+union cvmx_sli_pkt_in_instr_counts {
 	uint64_t u64;
-	struct cvmx_sli_pkt_in_instr_counts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_in_instr_counts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t wr_cnt                       : 32; /**< Shows the number of packets sent to the IPD. */
 	uint64_t rd_cnt                       : 32; /**< Shows the value of instructions that have had reads
                                                          issued for them.
@@ -3271,8 +5045,13 @@ union cvmx_sli_pkt_in_instr_counts
 	uint64_t wr_cnt                       : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_in_instr_counts_s cn61xx;
 	struct cvmx_sli_pkt_in_instr_counts_s cn63xx;
 	struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1;
+	struct cvmx_sli_pkt_in_instr_counts_s cn66xx;
+	struct cvmx_sli_pkt_in_instr_counts_s cn68xx;
+	struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1;
+	struct cvmx_sli_pkt_in_instr_counts_s cnf71xx;
 };
 typedef union cvmx_sli_pkt_in_instr_counts cvmx_sli_pkt_in_instr_counts_t;
 
@@ -3283,23 +5062,26 @@ typedef union cvmx_sli_pkt_in_instr_counts cvmx_sli_pkt_in_instr_counts_t;
  *
  * Assigns Packet Input rings to MAC ports.
  */
-union cvmx_sli_pkt_in_pcie_port
-{
+union cvmx_sli_pkt_in_pcie_port {
 	uint64_t u64;
-	struct cvmx_sli_pkt_in_pcie_port_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_in_pcie_port_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t pp                           : 64; /**< The MAC port that the Packet ring number is
                                                          assigned. Two bits are used per ring (i.e. ring 0
                                                          [1:0], ring 1 [3:2], ....). A value of '0 means
                                                          that the Packetring is assign to MAC Port 0, a '1'
-                                                         MAC Port 1, '2' and '3' are reserved. */
+                                                         MAC Port 1, a '2' MAC Port 2, and a '3' MAC Port 3. */
 #else
 	uint64_t pp                           : 64;
 #endif
 	} s;
+	struct cvmx_sli_pkt_in_pcie_port_s    cn61xx;
 	struct cvmx_sli_pkt_in_pcie_port_s    cn63xx;
 	struct cvmx_sli_pkt_in_pcie_port_s    cn63xxp1;
+	struct cvmx_sli_pkt_in_pcie_port_s    cn66xx;
+	struct cvmx_sli_pkt_in_pcie_port_s    cn68xx;
+	struct cvmx_sli_pkt_in_pcie_port_s    cn68xxp1;
+	struct cvmx_sli_pkt_in_pcie_port_s    cnf71xx;
 };
 typedef union cvmx_sli_pkt_in_pcie_port cvmx_sli_pkt_in_pcie_port_t;
 
@@ -3310,12 +5092,109 @@ typedef union cvmx_sli_pkt_in_pcie_port cvmx_sli_pkt_in_pcie_port_t;
  *
  * Control for reads for gather list and instructions.
  */
-union cvmx_sli_pkt_input_control
-{
+union cvmx_sli_pkt_input_control {
 	uint64_t u64;
-	struct cvmx_sli_pkt_input_control_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_input_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t prd_erst                     : 1;  /**< PRD Error Reset */
+	uint64_t prd_rds                      : 7;  /**< PRD Reads Out */
+	uint64_t gii_erst                     : 1;  /**< GII Error Reset */
+	uint64_t gii_rds                      : 7;  /**< GII Reads Out */
+	uint64_t reserved_41_47               : 7;
+	uint64_t prc_idle                     : 1;  /**< PRC In IDLE */
+	uint64_t reserved_24_39               : 16;
+	uint64_t pin_rst                      : 1;  /**< Packet In Reset. When a gather-list read receives
+                                                         an error this bit (along with SLI_INT_SUM[PGL_ERR])
+                                                         is set. When receiveing a PGL_ERR interrupt the SW
+                                                         should:
+                                                         1. Wait 2ms to allow any outstanding reads to return
+                                                            or be timed out.
+                                                         2. Write a '0' to this bit.
+                                                         3. Startup the packet input again (all previous
+                                                            CSR setting of the packet-input will be lost). */
+	uint64_t pkt_rr                       : 1;  /**< When set '1' the input packet selection will be
+                                                         made with a Round Robin arbitration. When '0'
+                                                         the input packet ring is fixed in priority,
+                                                         where the lower ring number has higher priority. */
+	uint64_t pbp_dhi                      : 13; /**< PBP_DHI replaces address bits that are used
+                                                         for parse mode and skip-length when
+                                                         SLI_PKTi_INSTR_HEADER[PBP]=1.
+                                                         PBP_DHI becomes either MACADD<63:55> or MACADD<59:51>
+                                                         for the instruction DPTR reads in this case.
+                                                         The instruction DPTR reads are called
+                                                         "First Direct" or "First Indirect" in the HRM.
+                                                         When PBP=1, if "First Direct" and USE_CSR=0, PBP_DHI
+                                                         becomes MACADD<59:51>, else MACADD<63:55>. */
+	uint64_t d_nsr                        : 1;  /**< ADDRTYPE<1> or MACADD<61> for packet input data
+                                                         reads.
+                                                         D_NSR becomes either ADDRTYPE<1> or MACADD<61>
+                                                         for MAC memory space reads of packet input data
+                                                         fetched for any packet input ring.
+                                                         ADDRTYPE<1> if USE_CSR=1, else MACADD<61>.
+                                                         In the latter case, ADDRTYPE<1> comes from DPTR<61>.
+                                                         ADDRTYPE<1> is the no-snoop attribute for PCIe
+                                                         , helps select an SRIO*_S2M_TYPE* entry with sRIO. */
+	uint64_t d_esr                        : 2;  /**< ES<1:0> or MACADD<63:62> for packet input data
+                                                         reads.
+                                                         D_ESR becomes either ES<1:0> or MACADD<63:62>
+                                                         for MAC memory space reads of packet input data
+                                                         fetched for any packet input ring.
+                                                         ES<1:0> if USE_CSR=1, else MACADD<63:62>.
+                                                         In the latter case, ES<1:0> comes from DPTR<63:62>.
+                                                         ES<1:0> is the endian-swap attribute for these MAC
+                                                         memory space reads. */
+	uint64_t d_ror                        : 1;  /**< ADDRTYPE<0> or MACADD<60> for packet input data
+                                                         reads.
+                                                         D_ROR becomes either ADDRTYPE<0> or MACADD<60>
+                                                         for MAC memory space reads of packet input data
+                                                         fetched for any packet input ring.
+                                                         ADDRTYPE<0> if USE_CSR=1, else MACADD<60>.
+                                                         In the latter case, ADDRTYPE<0> comes from DPTR<60>.
+                                                         ADDRTYPE<0> is the relaxed-order attribute for PCIe
+                                                         , helps select an SRIO*_S2M_TYPE* entry with sRIO. */
+	uint64_t use_csr                      : 1;  /**< When set '1' the csr value will be used for
+                                                         ROR, ESR, and NSR. When clear '0' the value in
+                                                         DPTR will be used. In turn the bits not used for
+                                                         ROR, ESR, and NSR, will be used for bits [63:60]
+                                                         of the address used to fetch packet data. */
+	uint64_t nsr                          : 1;  /**< ADDRTYPE<1> for packet input instruction reads and
+                                                         gather list (i.e. DPI component) reads from MAC
+                                                         memory space.
+                                                         ADDRTYPE<1> is the no-snoop attribute for PCIe
+                                                         , helps select an SRIO*_S2M_TYPE* entry with sRIO. */
+	uint64_t esr                          : 2;  /**< ES<1:0> for packet input instruction reads and
+                                                         gather list (i.e. DPI component) reads from MAC
+                                                         memory space.
+                                                         ES<1:0> is the endian-swap attribute for these MAC
+                                                         memory space reads. */
+	uint64_t ror                          : 1;  /**< ADDRTYPE<0> for packet input instruction reads and
+                                                         gather list (i.e. DPI component) reads from MAC
+                                                         memory space.
+                                                         ADDRTYPE<0> is the relaxed-order attribute for PCIe
+                                                         , helps select an SRIO*_S2M_TYPE* entry with sRIO. */
+#else
+	uint64_t ror                          : 1;
+	uint64_t esr                          : 2;
+	uint64_t nsr                          : 1;
+	uint64_t use_csr                      : 1;
+	uint64_t d_ror                        : 1;
+	uint64_t d_esr                        : 2;
+	uint64_t d_nsr                        : 1;
+	uint64_t pbp_dhi                      : 13;
+	uint64_t pkt_rr                       : 1;
+	uint64_t pin_rst                      : 1;
+	uint64_t reserved_24_39               : 16;
+	uint64_t prc_idle                     : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t gii_rds                      : 7;
+	uint64_t gii_erst                     : 1;
+	uint64_t prd_rds                      : 7;
+	uint64_t prd_erst                     : 1;
+#endif
+	} s;
+	struct cvmx_sli_pkt_input_control_s   cn61xx;
+	struct cvmx_sli_pkt_input_control_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_23_63               : 41;
 	uint64_t pkt_rr                       : 1;  /**< When set '1' the input packet selection will be
                                                          made with a Round Robin arbitration. When '0'
@@ -3389,9 +5268,12 @@ union cvmx_sli_pkt_input_control
 	uint64_t pkt_rr                       : 1;
 	uint64_t reserved_23_63               : 41;
 #endif
-	} s;
-	struct cvmx_sli_pkt_input_control_s   cn63xx;
-	struct cvmx_sli_pkt_input_control_s   cn63xxp1;
+	} cn63xx;
+	struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1;
+	struct cvmx_sli_pkt_input_control_s   cn66xx;
+	struct cvmx_sli_pkt_input_control_s   cn68xx;
+	struct cvmx_sli_pkt_input_control_s   cn68xxp1;
+	struct cvmx_sli_pkt_input_control_s   cnf71xx;
 };
 typedef union cvmx_sli_pkt_input_control cvmx_sli_pkt_input_control_t;
 
@@ -3402,12 +5284,10 @@ typedef union cvmx_sli_pkt_input_control cvmx_sli_pkt_input_control_t;
  *
  * Enables the instruction fetch for a Packet-ring.
  */
-union cvmx_sli_pkt_instr_enb
-{
+union cvmx_sli_pkt_instr_enb {
 	uint64_t u64;
-	struct cvmx_sli_pkt_instr_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_instr_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t enb                          : 32; /**< When ENB<i>=1, instruction input ring i is enabled. */
 #else
@@ -3415,8 +5295,13 @@ union cvmx_sli_pkt_instr_enb
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_instr_enb_s       cn61xx;
 	struct cvmx_sli_pkt_instr_enb_s       cn63xx;
 	struct cvmx_sli_pkt_instr_enb_s       cn63xxp1;
+	struct cvmx_sli_pkt_instr_enb_s       cn66xx;
+	struct cvmx_sli_pkt_instr_enb_s       cn68xx;
+	struct cvmx_sli_pkt_instr_enb_s       cn68xxp1;
+	struct cvmx_sli_pkt_instr_enb_s       cnf71xx;
 };
 typedef union cvmx_sli_pkt_instr_enb cvmx_sli_pkt_instr_enb_t;
 
@@ -3427,12 +5312,10 @@ typedef union cvmx_sli_pkt_instr_enb cvmx_sli_pkt_instr_enb_t;
  *
  * The number of instruction allowed to be read at one time.
  */
-union cvmx_sli_pkt_instr_rd_size
-{
+union cvmx_sli_pkt_instr_rd_size {
 	uint64_t u64;
-	struct cvmx_sli_pkt_instr_rd_size_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_instr_rd_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rdsize                       : 64; /**< Number of instructions to be read in one MAC read
                                                          request for the 4 ports - 8 rings. Every two bits
                                                          (i.e. 1:0, 3:2, 5:4..) are assign to the port/ring
@@ -3448,8 +5331,13 @@ union cvmx_sli_pkt_instr_rd_size
 	uint64_t rdsize                       : 64;
 #endif
 	} s;
+	struct cvmx_sli_pkt_instr_rd_size_s   cn61xx;
 	struct cvmx_sli_pkt_instr_rd_size_s   cn63xx;
 	struct cvmx_sli_pkt_instr_rd_size_s   cn63xxp1;
+	struct cvmx_sli_pkt_instr_rd_size_s   cn66xx;
+	struct cvmx_sli_pkt_instr_rd_size_s   cn68xx;
+	struct cvmx_sli_pkt_instr_rd_size_s   cn68xxp1;
+	struct cvmx_sli_pkt_instr_rd_size_s   cnf71xx;
 };
 typedef union cvmx_sli_pkt_instr_rd_size cvmx_sli_pkt_instr_rd_size_t;
 
@@ -3460,12 +5348,10 @@ typedef union cvmx_sli_pkt_instr_rd_size cvmx_sli_pkt_instr_rd_size_t;
  *
  * Determines if instructions are 64 or 32 byte in size for a Packet-ring.
  */
-union cvmx_sli_pkt_instr_size
-{
+union cvmx_sli_pkt_instr_size {
 	uint64_t u64;
-	struct cvmx_sli_pkt_instr_size_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_instr_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t is_64b                       : 32; /**< When IS_64B<i>=1, instruction input ring i uses 64B
                                                          instructions, else 32B instructions. */
@@ -3474,8 +5360,13 @@ union cvmx_sli_pkt_instr_size
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_instr_size_s      cn61xx;
 	struct cvmx_sli_pkt_instr_size_s      cn63xx;
 	struct cvmx_sli_pkt_instr_size_s      cn63xxp1;
+	struct cvmx_sli_pkt_instr_size_s      cn66xx;
+	struct cvmx_sli_pkt_instr_size_s      cn68xx;
+	struct cvmx_sli_pkt_instr_size_s      cn68xxp1;
+	struct cvmx_sli_pkt_instr_size_s      cnf71xx;
 };
 typedef union cvmx_sli_pkt_instr_size cvmx_sli_pkt_instr_size_t;
 
@@ -3489,12 +5380,10 @@ typedef union cvmx_sli_pkt_instr_size cvmx_sli_pkt_instr_size_t;
  *
  * Output packet interrupt levels.
  */
-union cvmx_sli_pkt_int_levels
-{
+union cvmx_sli_pkt_int_levels {
 	uint64_t u64;
-	struct cvmx_sli_pkt_int_levels_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_int_levels_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_54_63               : 10;
 	uint64_t time                         : 22; /**< Output ring counter time interrupt threshold
                                                          SLI sets SLI_PKT_TIME_INT[PORT<i>] whenever
@@ -3508,8 +5397,13 @@ union cvmx_sli_pkt_int_levels
 	uint64_t reserved_54_63               : 10;
 #endif
 	} s;
+	struct cvmx_sli_pkt_int_levels_s      cn61xx;
 	struct cvmx_sli_pkt_int_levels_s      cn63xx;
 	struct cvmx_sli_pkt_int_levels_s      cn63xxp1;
+	struct cvmx_sli_pkt_int_levels_s      cn66xx;
+	struct cvmx_sli_pkt_int_levels_s      cn68xx;
+	struct cvmx_sli_pkt_int_levels_s      cn68xxp1;
+	struct cvmx_sli_pkt_int_levels_s      cnf71xx;
 };
 typedef union cvmx_sli_pkt_int_levels cvmx_sli_pkt_int_levels_t;
 
@@ -3520,12 +5414,10 @@ typedef union cvmx_sli_pkt_int_levels cvmx_sli_pkt_int_levels_t;
  *
  * Controls using the Info-Pointer to store length and data.
  */
-union cvmx_sli_pkt_iptr
-{
+union cvmx_sli_pkt_iptr {
 	uint64_t u64;
-	struct cvmx_sli_pkt_iptr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_iptr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t iptr                         : 32; /**< When IPTR<i>=1, packet output ring i is in info-
                                                          pointer mode, else buffer-pointer-only mode. */
@@ -3534,8 +5426,13 @@ union cvmx_sli_pkt_iptr
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_iptr_s            cn61xx;
 	struct cvmx_sli_pkt_iptr_s            cn63xx;
 	struct cvmx_sli_pkt_iptr_s            cn63xxp1;
+	struct cvmx_sli_pkt_iptr_s            cn66xx;
+	struct cvmx_sli_pkt_iptr_s            cn68xx;
+	struct cvmx_sli_pkt_iptr_s            cn68xxp1;
+	struct cvmx_sli_pkt_iptr_s            cnf71xx;
 };
 typedef union cvmx_sli_pkt_iptr cvmx_sli_pkt_iptr_t;
 
@@ -3546,12 +5443,10 @@ typedef union cvmx_sli_pkt_iptr cvmx_sli_pkt_iptr_t;
  *
  * Control the updating of the SLI_PKT#_CNT register.
  */
-union cvmx_sli_pkt_out_bmode
-{
+union cvmx_sli_pkt_out_bmode {
 	uint64_t u64;
-	struct cvmx_sli_pkt_out_bmode_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_out_bmode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t bmode                        : 32; /**< Determines whether SLI_PKTi_CNTS[CNT] is a byte or
                                                          packet counter.
@@ -3563,24 +5458,53 @@ union cvmx_sli_pkt_out_bmode
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_out_bmode_s       cn61xx;
 	struct cvmx_sli_pkt_out_bmode_s       cn63xx;
 	struct cvmx_sli_pkt_out_bmode_s       cn63xxp1;
+	struct cvmx_sli_pkt_out_bmode_s       cn66xx;
+	struct cvmx_sli_pkt_out_bmode_s       cn68xx;
+	struct cvmx_sli_pkt_out_bmode_s       cn68xxp1;
+	struct cvmx_sli_pkt_out_bmode_s       cnf71xx;
 };
 typedef union cvmx_sli_pkt_out_bmode cvmx_sli_pkt_out_bmode_t;
 
 /**
+ * cvmx_sli_pkt_out_bp_en
+ *
+ * SLI_PKT_OUT_BP_EN = SLI Packet Output Backpressure Enable
+ *
+ * Enables sending backpressure to the PKO.
+ */
+union cvmx_sli_pkt_out_bp_en {
+	uint64_t u64;
+	struct cvmx_sli_pkt_out_bp_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t bp_en                        : 32; /**< When set '1' enable the ring level backpressure
+                                                         to be sent to PKO. Backpressure is sent to the
+                                                         PKO on the PIPE number associated with the ring.
+                                                         (See SLI_TX_PIPE for ring to pipe associations). */
+#else
+	uint64_t bp_en                        : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_out_bp_en_s       cn68xx;
+	struct cvmx_sli_pkt_out_bp_en_s       cn68xxp1;
+};
+typedef union cvmx_sli_pkt_out_bp_en cvmx_sli_pkt_out_bp_en_t;
+
+/**
  * cvmx_sli_pkt_out_enb
  *
  * SLI_PKT_OUT_ENB = SLI's Packet Output Enable
  *
  * Enables the output packet engines.
  */
-union cvmx_sli_pkt_out_enb
-{
+union cvmx_sli_pkt_out_enb {
 	uint64_t u64;
-	struct cvmx_sli_pkt_out_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_out_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t enb                          : 32; /**< When ENB<i>=1, packet output ring i is enabled.
                                                          If an error occurs on reading pointers for an
@@ -3591,8 +5515,13 @@ union cvmx_sli_pkt_out_enb
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_out_enb_s         cn61xx;
 	struct cvmx_sli_pkt_out_enb_s         cn63xx;
 	struct cvmx_sli_pkt_out_enb_s         cn63xxp1;
+	struct cvmx_sli_pkt_out_enb_s         cn66xx;
+	struct cvmx_sli_pkt_out_enb_s         cn68xx;
+	struct cvmx_sli_pkt_out_enb_s         cn68xxp1;
+	struct cvmx_sli_pkt_out_enb_s         cnf71xx;
 };
 typedef union cvmx_sli_pkt_out_enb cvmx_sli_pkt_out_enb_t;
 
@@ -3603,12 +5532,10 @@ typedef union cvmx_sli_pkt_out_enb cvmx_sli_pkt_out_enb_t;
  *
  * Value that when the SLI_PKT#_SLIST_BAOFF_DBELL[DBELL] value is less then that backpressure for the rings will be applied.
  */
-union cvmx_sli_pkt_output_wmark
-{
+union cvmx_sli_pkt_output_wmark {
 	uint64_t u64;
-	struct cvmx_sli_pkt_output_wmark_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_output_wmark_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t wmark                        : 32; /**< Value when DBELL count drops below backpressure
                                                          for the ring will be applied to the PKO. */
@@ -3617,8 +5544,13 @@ union cvmx_sli_pkt_output_wmark
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_output_wmark_s    cn61xx;
 	struct cvmx_sli_pkt_output_wmark_s    cn63xx;
 	struct cvmx_sli_pkt_output_wmark_s    cn63xxp1;
+	struct cvmx_sli_pkt_output_wmark_s    cn66xx;
+	struct cvmx_sli_pkt_output_wmark_s    cn68xx;
+	struct cvmx_sli_pkt_output_wmark_s    cn68xxp1;
+	struct cvmx_sli_pkt_output_wmark_s    cnf71xx;
 };
 typedef union cvmx_sli_pkt_output_wmark cvmx_sli_pkt_output_wmark_t;
 
@@ -3629,12 +5561,10 @@ typedef union cvmx_sli_pkt_output_wmark cvmx_sli_pkt_output_wmark_t;
  *
  * Assigns Packet Ports to MAC ports.
  */
-union cvmx_sli_pkt_pcie_port
-{
+union cvmx_sli_pkt_pcie_port {
 	uint64_t u64;
-	struct cvmx_sli_pkt_pcie_port_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_pcie_port_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t pp                           : 64; /**< The physical MAC  port that the output ring uses.
                                                          Two bits are used per ring (i.e. ring 0 [1:0],
                                                          ring 1 [3:2], ....). A value of '0 means
@@ -3644,8 +5574,13 @@ union cvmx_sli_pkt_pcie_port
 	uint64_t pp                           : 64;
 #endif
 	} s;
+	struct cvmx_sli_pkt_pcie_port_s       cn61xx;
 	struct cvmx_sli_pkt_pcie_port_s       cn63xx;
 	struct cvmx_sli_pkt_pcie_port_s       cn63xxp1;
+	struct cvmx_sli_pkt_pcie_port_s       cn66xx;
+	struct cvmx_sli_pkt_pcie_port_s       cn68xx;
+	struct cvmx_sli_pkt_pcie_port_s       cn68xxp1;
+	struct cvmx_sli_pkt_pcie_port_s       cnf71xx;
 };
 typedef union cvmx_sli_pkt_pcie_port cvmx_sli_pkt_pcie_port_t;
 
@@ -3661,12 +5596,10 @@ typedef union cvmx_sli_pkt_pcie_port cvmx_sli_pkt_pcie_port_t;
  *
  *  Vector bits related to ring-port for ones that are reset.
  */
-union cvmx_sli_pkt_port_in_rst
-{
+union cvmx_sli_pkt_port_in_rst {
 	uint64_t u64;
-	struct cvmx_sli_pkt_port_in_rst_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_port_in_rst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t in_rst                       : 32; /**< When asserted '1' the vector bit cooresponding
                                                          to the inbound Packet-ring is in reset. */
 	uint64_t out_rst                      : 32; /**< When asserted '1' the vector bit cooresponding
@@ -3676,8 +5609,13 @@ union cvmx_sli_pkt_port_in_rst
 	uint64_t in_rst                       : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_port_in_rst_s     cn61xx;
 	struct cvmx_sli_pkt_port_in_rst_s     cn63xx;
 	struct cvmx_sli_pkt_port_in_rst_s     cn63xxp1;
+	struct cvmx_sli_pkt_port_in_rst_s     cn66xx;
+	struct cvmx_sli_pkt_port_in_rst_s     cn68xx;
+	struct cvmx_sli_pkt_port_in_rst_s     cn68xxp1;
+	struct cvmx_sli_pkt_port_in_rst_s     cnf71xx;
 };
 typedef union cvmx_sli_pkt_port_in_rst cvmx_sli_pkt_port_in_rst_t;
 
@@ -3688,12 +5626,10 @@ typedef union cvmx_sli_pkt_port_in_rst cvmx_sli_pkt_port_in_rst_t;
  *
  * The Endian Swap for Scatter List Read.
  */
-union cvmx_sli_pkt_slist_es
-{
+union cvmx_sli_pkt_slist_es {
 	uint64_t u64;
-	struct cvmx_sli_pkt_slist_es_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_slist_es_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t es                           : 64; /**< ES<1:0> for the packet output ring reads that
                                                          fetch buffer/info pointer pairs.
                                                          ES<2i+1:2i> becomes ES<1:0> in DPI/SLI reads that
@@ -3706,8 +5642,13 @@ union cvmx_sli_pkt_slist_es
 	uint64_t es                           : 64;
 #endif
 	} s;
+	struct cvmx_sli_pkt_slist_es_s        cn61xx;
 	struct cvmx_sli_pkt_slist_es_s        cn63xx;
 	struct cvmx_sli_pkt_slist_es_s        cn63xxp1;
+	struct cvmx_sli_pkt_slist_es_s        cn66xx;
+	struct cvmx_sli_pkt_slist_es_s        cn68xx;
+	struct cvmx_sli_pkt_slist_es_s        cn68xxp1;
+	struct cvmx_sli_pkt_slist_es_s        cnf71xx;
 };
 typedef union cvmx_sli_pkt_slist_es cvmx_sli_pkt_slist_es_t;
 
@@ -3718,12 +5659,10 @@ typedef union cvmx_sli_pkt_slist_es cvmx_sli_pkt_slist_es_t;
  *
  * The NS field for the TLP when fetching Scatter List.
  */
-union cvmx_sli_pkt_slist_ns
-{
+union cvmx_sli_pkt_slist_ns {
 	uint64_t u64;
-	struct cvmx_sli_pkt_slist_ns_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_slist_ns_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t nsr                          : 32; /**< ADDRTYPE<1> for the packet output ring reads that
                                                          fetch buffer/info pointer pairs.
@@ -3738,8 +5677,13 @@ union cvmx_sli_pkt_slist_ns
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_slist_ns_s        cn61xx;
 	struct cvmx_sli_pkt_slist_ns_s        cn63xx;
 	struct cvmx_sli_pkt_slist_ns_s        cn63xxp1;
+	struct cvmx_sli_pkt_slist_ns_s        cn66xx;
+	struct cvmx_sli_pkt_slist_ns_s        cn68xx;
+	struct cvmx_sli_pkt_slist_ns_s        cn68xxp1;
+	struct cvmx_sli_pkt_slist_ns_s        cnf71xx;
 };
 typedef union cvmx_sli_pkt_slist_ns cvmx_sli_pkt_slist_ns_t;
 
@@ -3750,12 +5694,10 @@ typedef union cvmx_sli_pkt_slist_ns cvmx_sli_pkt_slist_ns_t;
  *
  * The ROR field for the TLP when fetching Scatter List.
  */
-union cvmx_sli_pkt_slist_ror
-{
+union cvmx_sli_pkt_slist_ror {
 	uint64_t u64;
-	struct cvmx_sli_pkt_slist_ror_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_slist_ror_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t ror                          : 32; /**< ADDRTYPE<0> for the packet output ring reads that
                                                          fetch buffer/info pointer pairs.
@@ -3770,8 +5712,13 @@ union cvmx_sli_pkt_slist_ror
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_slist_ror_s       cn61xx;
 	struct cvmx_sli_pkt_slist_ror_s       cn63xx;
 	struct cvmx_sli_pkt_slist_ror_s       cn63xxp1;
+	struct cvmx_sli_pkt_slist_ror_s       cn66xx;
+	struct cvmx_sli_pkt_slist_ror_s       cn68xx;
+	struct cvmx_sli_pkt_slist_ror_s       cn68xxp1;
+	struct cvmx_sli_pkt_slist_ror_s       cnf71xx;
 };
 typedef union cvmx_sli_pkt_slist_ror cvmx_sli_pkt_slist_ror_t;
 
@@ -3782,12 +5729,10 @@ typedef union cvmx_sli_pkt_slist_ror cvmx_sli_pkt_slist_ror_t;
  *
  * The packets rings that are interrupting because of Packet Timers.
  */
-union cvmx_sli_pkt_time_int
-{
+union cvmx_sli_pkt_time_int {
 	uint64_t u64;
-	struct cvmx_sli_pkt_time_int_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_time_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t port                         : 32; /**< Output ring packet timer interrupt bits
                                                          SLI sets PORT<i> whenever
@@ -3799,8 +5744,13 @@ union cvmx_sli_pkt_time_int
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_time_int_s        cn61xx;
 	struct cvmx_sli_pkt_time_int_s        cn63xx;
 	struct cvmx_sli_pkt_time_int_s        cn63xxp1;
+	struct cvmx_sli_pkt_time_int_s        cn66xx;
+	struct cvmx_sli_pkt_time_int_s        cn68xx;
+	struct cvmx_sli_pkt_time_int_s        cn68xxp1;
+	struct cvmx_sli_pkt_time_int_s        cnf71xx;
 };
 typedef union cvmx_sli_pkt_time_int cvmx_sli_pkt_time_int_t;
 
@@ -3811,12 +5761,10 @@ typedef union cvmx_sli_pkt_time_int cvmx_sli_pkt_time_int_t;
  *
  * The packets rings that are interrupting because of Packet Timers.
  */
-union cvmx_sli_pkt_time_int_enb
-{
+union cvmx_sli_pkt_time_int_enb {
 	uint64_t u64;
-	struct cvmx_sli_pkt_time_int_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_pkt_time_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t port                         : 32; /**< Output ring packet timer interrupt enables
                                                          When both PORT<i> and corresponding
@@ -3828,12 +5776,78 @@ union cvmx_sli_pkt_time_int_enb
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_pkt_time_int_enb_s    cn61xx;
 	struct cvmx_sli_pkt_time_int_enb_s    cn63xx;
 	struct cvmx_sli_pkt_time_int_enb_s    cn63xxp1;
+	struct cvmx_sli_pkt_time_int_enb_s    cn66xx;
+	struct cvmx_sli_pkt_time_int_enb_s    cn68xx;
+	struct cvmx_sli_pkt_time_int_enb_s    cn68xxp1;
+	struct cvmx_sli_pkt_time_int_enb_s    cnf71xx;
 };
 typedef union cvmx_sli_pkt_time_int_enb cvmx_sli_pkt_time_int_enb_t;
 
 /**
+ * cvmx_sli_port#_pkind
+ *
+ * SLI_PORT[0..31]_PKIND = SLI Port Pkind
+ *
+ * The SLI/DPI supports 32 input rings for fetching input packets. This register maps the input-rings (0-31) to a PKIND.
+ */
+union cvmx_sli_portx_pkind {
+	uint64_t u64;
+	struct cvmx_sli_portx_pkind_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_25_63               : 39;
+	uint64_t rpk_enb                      : 1;  /**< Alternate PKT_INST_HDR PKind Enable for this ring.
+                                                         When RPK_ENB==1 and DPI prepends
+                                                         a PKT_INST_HDR to a packet, the pkind for the
+                                                         packet is PKINDR (rather than PKIND), and any
+                                                         special PIP/IPD processing of the DPI packet is
+                                                         disabled (see PIP_PRT_CFG*[INST_HDR,HIGIG_EN]).
+                                                         (DPI prepends a PKT_INST_HDR when either
+                                                         DPI_INST_HDR[R]==1 for the packet or
+                                                         SLI_PKT*_INSTR_HEADER[USE_IHDR]==1 for the ring.)
+                                                         When RPK_ENB==0, PKIND is the pkind for all
+                                                         packets through the input ring, and
+                                                         PIP/IPD will process a DPI packet that has a
+                                                         PKT_INST_HDR specially. */
+	uint64_t reserved_22_23               : 2;
+	uint64_t pkindr                       : 6;  /**< Port Kind For this Ring used with packets
+                                                         that include a DPI-prepended PKT_INST_HDR
+                                                         when RPK_ENB is set. */
+	uint64_t reserved_14_15               : 2;
+	uint64_t bpkind                       : 6;  /**< Back-pressure pkind for this Ring. */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t pkind                        : 6;  /**< Port Kind For this Ring. */
+#else
+	uint64_t pkind                        : 6;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t bpkind                       : 6;
+	uint64_t reserved_14_15               : 2;
+	uint64_t pkindr                       : 6;
+	uint64_t reserved_22_23               : 2;
+	uint64_t rpk_enb                      : 1;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_sli_portx_pkind_s         cn68xx;
+	struct cvmx_sli_portx_pkind_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_14_63               : 50;
+	uint64_t bpkind                       : 6;  /**< Back-pressure pkind for this Ring. */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t pkind                        : 6;  /**< Port Kind For this Ring. */
+#else
+	uint64_t pkind                        : 6;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t bpkind                       : 6;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_sli_portx_pkind cvmx_sli_portx_pkind_t;
+
+/**
  * cvmx_sli_s2m_port#_ctl
  *
  * SLI_S2M_PORTX_CTL = SLI's S2M Port 0 Control
@@ -3843,18 +5857,21 @@ typedef union cvmx_sli_pkt_time_int_enb cvmx_sli_pkt_time_int_enb_t;
  * To ensure that a write has completed the user must read the register before
  * making an access(i.e. MAC memory space) that requires the value of this register to be updated.
  */
-union cvmx_sli_s2m_portx_ctl
-{
+union cvmx_sli_s2m_portx_ctl {
 	uint64_t u64;
-	struct cvmx_sli_s2m_portx_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_s2m_portx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t wind_d                       : 1;  /**< When set '1' disables access to the Window
-                                                         Registers from the MAC-Port. */
+                                                         Registers from the MAC-Port.
+                                                         When Authenticate-Mode is set the reset value of
+                                                         this field is "1" else "0'. */
 	uint64_t bar0_d                       : 1;  /**< When set '1' disables access from MAC to
                                                          BAR-0 address offsets: Less Than 0x330,
-                                                         0x3CD0, and greater than 0x3D70. */
+                                                         0x3CD0, and greater than 0x3D70 excluding
+                                                         0x3e00.
+                                                         When Authenticate-Mode is set the reset value of
+                                                         this field is "1" else "0'. */
 	uint64_t mrrs                         : 3;  /**< Max Read Request Size
                                                                  0 = 128B
                                                                  1 = 256B
@@ -3876,8 +5893,13 @@ union cvmx_sli_s2m_portx_ctl
 	uint64_t reserved_5_63                : 59;
 #endif
 	} s;
+	struct cvmx_sli_s2m_portx_ctl_s       cn61xx;
 	struct cvmx_sli_s2m_portx_ctl_s       cn63xx;
 	struct cvmx_sli_s2m_portx_ctl_s       cn63xxp1;
+	struct cvmx_sli_s2m_portx_ctl_s       cn66xx;
+	struct cvmx_sli_s2m_portx_ctl_s       cn68xx;
+	struct cvmx_sli_s2m_portx_ctl_s       cn68xxp1;
+	struct cvmx_sli_s2m_portx_ctl_s       cnf71xx;
 };
 typedef union cvmx_sli_s2m_portx_ctl cvmx_sli_s2m_portx_ctl_t;
 
@@ -3888,19 +5910,22 @@ typedef union cvmx_sli_s2m_portx_ctl cvmx_sli_s2m_portx_ctl_t;
  *
  * A general purpose 64 bit register for SW use.
  */
-union cvmx_sli_scratch_1
-{
+union cvmx_sli_scratch_1 {
 	uint64_t u64;
-	struct cvmx_sli_scratch_1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_scratch_1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 64; /**< The value in this register is totaly SW dependent. */
 #else
 	uint64_t data                         : 64;
 #endif
 	} s;
+	struct cvmx_sli_scratch_1_s           cn61xx;
 	struct cvmx_sli_scratch_1_s           cn63xx;
 	struct cvmx_sli_scratch_1_s           cn63xxp1;
+	struct cvmx_sli_scratch_1_s           cn66xx;
+	struct cvmx_sli_scratch_1_s           cn68xx;
+	struct cvmx_sli_scratch_1_s           cn68xxp1;
+	struct cvmx_sli_scratch_1_s           cnf71xx;
 };
 typedef union cvmx_sli_scratch_1 cvmx_sli_scratch_1_t;
 
@@ -3911,19 +5936,22 @@ typedef union cvmx_sli_scratch_1 cvmx_sli_scratch_1_t;
  *
  * A general purpose 64 bit register for SW use.
  */
-union cvmx_sli_scratch_2
-{
+union cvmx_sli_scratch_2 {
 	uint64_t u64;
-	struct cvmx_sli_scratch_2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_scratch_2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t data                         : 64; /**< The value in this register is totaly SW dependent. */
 #else
 	uint64_t data                         : 64;
 #endif
 	} s;
+	struct cvmx_sli_scratch_2_s           cn61xx;
 	struct cvmx_sli_scratch_2_s           cn63xx;
 	struct cvmx_sli_scratch_2_s           cn63xxp1;
+	struct cvmx_sli_scratch_2_s           cn66xx;
+	struct cvmx_sli_scratch_2_s           cn68xx;
+	struct cvmx_sli_scratch_2_s           cn68xxp1;
+	struct cvmx_sli_scratch_2_s           cnf71xx;
 };
 typedef union cvmx_sli_scratch_2 cvmx_sli_scratch_2_t;
 
@@ -3934,12 +5962,10 @@ typedef union cvmx_sli_scratch_2 cvmx_sli_scratch_2_t;
  *
  * State machines in SLI. For debug.
  */
-union cvmx_sli_state1
-{
+union cvmx_sli_state1 {
 	uint64_t u64;
-	struct cvmx_sli_state1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_state1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t cpl1                         : 12; /**< CPL1 State */
 	uint64_t cpl0                         : 12; /**< CPL0 State */
 	uint64_t arb                          : 1;  /**< ARB State */
@@ -3951,8 +5977,13 @@ union cvmx_sli_state1
 	uint64_t cpl1                         : 12;
 #endif
 	} s;
+	struct cvmx_sli_state1_s              cn61xx;
 	struct cvmx_sli_state1_s              cn63xx;
 	struct cvmx_sli_state1_s              cn63xxp1;
+	struct cvmx_sli_state1_s              cn66xx;
+	struct cvmx_sli_state1_s              cn68xx;
+	struct cvmx_sli_state1_s              cn68xxp1;
+	struct cvmx_sli_state1_s              cnf71xx;
 };
 typedef union cvmx_sli_state1 cvmx_sli_state1_t;
 
@@ -3963,12 +5994,10 @@ typedef union cvmx_sli_state1 cvmx_sli_state1_t;
  *
  * State machines in SLI. For debug.
  */
-union cvmx_sli_state2
-{
+union cvmx_sli_state2 {
 	uint64_t u64;
-	struct cvmx_sli_state2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_state2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_56_63               : 8;
 	uint64_t nnp1                         : 8;  /**< NNP1 State */
 	uint64_t reserved_47_47               : 1;
@@ -3988,8 +6017,13 @@ union cvmx_sli_state2
 	uint64_t reserved_56_63               : 8;
 #endif
 	} s;
+	struct cvmx_sli_state2_s              cn61xx;
 	struct cvmx_sli_state2_s              cn63xx;
 	struct cvmx_sli_state2_s              cn63xxp1;
+	struct cvmx_sli_state2_s              cn66xx;
+	struct cvmx_sli_state2_s              cn68xx;
+	struct cvmx_sli_state2_s              cn68xxp1;
+	struct cvmx_sli_state2_s              cnf71xx;
 };
 typedef union cvmx_sli_state2 cvmx_sli_state2_t;
 
@@ -4000,12 +6034,10 @@ typedef union cvmx_sli_state2 cvmx_sli_state2_t;
  *
  * State machines in SLI. For debug.
  */
-union cvmx_sli_state3
-{
+union cvmx_sli_state3 {
 	uint64_t u64;
-	struct cvmx_sli_state3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_state3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_56_63               : 8;
 	uint64_t psm1                         : 15; /**< PSM1 State */
 	uint64_t psm0                         : 15; /**< PSM0 State */
@@ -4019,12 +6051,63 @@ union cvmx_sli_state3
 	uint64_t reserved_56_63               : 8;
 #endif
 	} s;
+	struct cvmx_sli_state3_s              cn61xx;
 	struct cvmx_sli_state3_s              cn63xx;
 	struct cvmx_sli_state3_s              cn63xxp1;
+	struct cvmx_sli_state3_s              cn66xx;
+	struct cvmx_sli_state3_s              cn68xx;
+	struct cvmx_sli_state3_s              cn68xxp1;
+	struct cvmx_sli_state3_s              cnf71xx;
 };
 typedef union cvmx_sli_state3 cvmx_sli_state3_t;
 
 /**
+ * cvmx_sli_tx_pipe
+ *
+ * SLI_TX_PIPE = SLI Packet TX Pipe
+ *
+ * Contains the starting pipe number and number of pipes used by the SLI packet Output.
+ * If a packet is recevied from PKO with an out of range PIPE number, the following occurs:
+ * - SLI_INT_SUM[PIPE_ERR] is set.
+ * - the out of range pipe value is used for returning credits to the PKO.
+ * - the PCIe packet engine will treat the PIPE value to be equal to [BASE].
+ */
+union cvmx_sli_tx_pipe {
+	uint64_t u64;
+	struct cvmx_sli_tx_pipe_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_24_63               : 40;
+	uint64_t nump                         : 8;  /**< Number of pipes the the SLI/DPI supports.
+                                                         When this value is 4 or less there is a performance
+                                                         advantage for output packets.
+                                                         The SLI/DPI can support up to 32 pipes assigned to
+                                                         packet-rings 0 - 31. */
+	uint64_t reserved_7_15                : 9;
+	uint64_t base                         : 7;  /**< When NUMP is non-zero, indicates the base pipe
+                                                         number the SLI/DPI will accept.
+                                                         The SLI/DPI will accept pko packets from pipes in
+                                                         the range of:
+                                                           BASE .. (BASE+(NUMP-1))
+                                                         BASE and NUMP must be constrained such that
+                                                           1) BASE+(NUMP-1) < 127
+                                                           2) Each used PKO pipe must map to exactly
+                                                              one ring. Where BASE == ring 0, BASE+1 == to
+                                                              ring 1, etc
+                                                           3) The pipe ranges must be consistent with
+                                                              the PKO configuration. */
+#else
+	uint64_t base                         : 7;
+	uint64_t reserved_7_15                : 9;
+	uint64_t nump                         : 8;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_sli_tx_pipe_s             cn68xx;
+	struct cvmx_sli_tx_pipe_s             cn68xxp1;
+};
+typedef union cvmx_sli_tx_pipe cvmx_sli_tx_pipe_t;
+
+/**
  * cvmx_sli_win_rd_addr
  *
  * SLI_WIN_RD_ADDR = SLI Window Read Address Register
@@ -4032,12 +6115,10 @@ typedef union cvmx_sli_state3 cvmx_sli_state3_t;
  * The address to be read when the SLI_WIN_RD_DATA register is read.
  * This register should NOT be used to read SLI_* registers.
  */
-union cvmx_sli_win_rd_addr
-{
+union cvmx_sli_win_rd_addr {
 	uint64_t u64;
-	struct cvmx_sli_win_rd_addr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_win_rd_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_51_63               : 13;
 	uint64_t ld_cmd                       : 2;  /**< The load command sent wit hthe read.
                                                          0x3 == Load 8-bytes, 0x2 == Load 4-bytes,
@@ -4058,8 +6139,13 @@ union cvmx_sli_win_rd_addr
 	uint64_t reserved_51_63               : 13;
 #endif
 	} s;
+	struct cvmx_sli_win_rd_addr_s         cn61xx;
 	struct cvmx_sli_win_rd_addr_s         cn63xx;
 	struct cvmx_sli_win_rd_addr_s         cn63xxp1;
+	struct cvmx_sli_win_rd_addr_s         cn66xx;
+	struct cvmx_sli_win_rd_addr_s         cn68xx;
+	struct cvmx_sli_win_rd_addr_s         cn68xxp1;
+	struct cvmx_sli_win_rd_addr_s         cnf71xx;
 };
 typedef union cvmx_sli_win_rd_addr cvmx_sli_win_rd_addr_t;
 
@@ -4071,19 +6157,22 @@ typedef union cvmx_sli_win_rd_addr cvmx_sli_win_rd_addr_t;
  * Reading this register causes a window read operation to take place. Address read is that contained in the SLI_WIN_RD_ADDR
  * register.
  */
-union cvmx_sli_win_rd_data
-{
+union cvmx_sli_win_rd_data {
 	uint64_t u64;
-	struct cvmx_sli_win_rd_data_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_win_rd_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rd_data                      : 64; /**< The read data. */
 #else
 	uint64_t rd_data                      : 64;
 #endif
 	} s;
+	struct cvmx_sli_win_rd_data_s         cn61xx;
 	struct cvmx_sli_win_rd_data_s         cn63xx;
 	struct cvmx_sli_win_rd_data_s         cn63xxp1;
+	struct cvmx_sli_win_rd_data_s         cn66xx;
+	struct cvmx_sli_win_rd_data_s         cn68xx;
+	struct cvmx_sli_win_rd_data_s         cn68xxp1;
+	struct cvmx_sli_win_rd_data_s         cnf71xx;
 };
 typedef union cvmx_sli_win_rd_data cvmx_sli_win_rd_data_t;
 
@@ -4105,12 +6194,10 @@ typedef union cvmx_sli_win_rd_data cvmx_sli_win_rd_data_t;
  *
  * This register should NOT be used to write SLI_* registers.
  */
-union cvmx_sli_win_wr_addr
-{
+union cvmx_sli_win_wr_addr {
 	uint64_t u64;
-	struct cvmx_sli_win_wr_addr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_win_wr_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_49_63               : 15;
 	uint64_t iobit                        : 1;  /**< A 1 or 0 can be written here but this will always
                                                          read as '0'. */
@@ -4130,8 +6217,13 @@ union cvmx_sli_win_wr_addr
 	uint64_t reserved_49_63               : 15;
 #endif
 	} s;
+	struct cvmx_sli_win_wr_addr_s         cn61xx;
 	struct cvmx_sli_win_wr_addr_s         cn63xx;
 	struct cvmx_sli_win_wr_addr_s         cn63xxp1;
+	struct cvmx_sli_win_wr_addr_s         cn66xx;
+	struct cvmx_sli_win_wr_addr_s         cn68xx;
+	struct cvmx_sli_win_wr_addr_s         cn68xxp1;
+	struct cvmx_sli_win_wr_addr_s         cnf71xx;
 };
 typedef union cvmx_sli_win_wr_addr cvmx_sli_win_wr_addr_t;
 
@@ -4143,12 +6235,10 @@ typedef union cvmx_sli_win_wr_addr cvmx_sli_win_wr_addr_t;
  * Contains the data to write to the address located in the SLI_WIN_WR_ADDR Register.
  * Writing the least-significant-byte of this register will cause a write operation to take place.
  */
-union cvmx_sli_win_wr_data
-{
+union cvmx_sli_win_wr_data {
 	uint64_t u64;
-	struct cvmx_sli_win_wr_data_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_win_wr_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t wr_data                      : 64; /**< The data to be written. Whenever the LSB of this
                                                          register is written, the Window Write will take
                                                          place. */
@@ -4156,8 +6246,13 @@ union cvmx_sli_win_wr_data
 	uint64_t wr_data                      : 64;
 #endif
 	} s;
+	struct cvmx_sli_win_wr_data_s         cn61xx;
 	struct cvmx_sli_win_wr_data_s         cn63xx;
 	struct cvmx_sli_win_wr_data_s         cn63xxp1;
+	struct cvmx_sli_win_wr_data_s         cn66xx;
+	struct cvmx_sli_win_wr_data_s         cn68xx;
+	struct cvmx_sli_win_wr_data_s         cn68xxp1;
+	struct cvmx_sli_win_wr_data_s         cnf71xx;
 };
 typedef union cvmx_sli_win_wr_data cvmx_sli_win_wr_data_t;
 
@@ -4168,12 +6263,10 @@ typedef union cvmx_sli_win_wr_data cvmx_sli_win_wr_data_t;
  *
  * Contains the mask for the data in the SLI_WIN_WR_DATA Register.
  */
-union cvmx_sli_win_wr_mask
-{
+union cvmx_sli_win_wr_mask {
 	uint64_t u64;
-	struct cvmx_sli_win_wr_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_win_wr_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t wr_mask                      : 8;  /**< The data to be written. When a bit is '1'
                                                          the corresponding byte will be written. The values
@@ -4185,8 +6278,13 @@ union cvmx_sli_win_wr_mask
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
+	struct cvmx_sli_win_wr_mask_s         cn61xx;
 	struct cvmx_sli_win_wr_mask_s         cn63xx;
 	struct cvmx_sli_win_wr_mask_s         cn63xxp1;
+	struct cvmx_sli_win_wr_mask_s         cn66xx;
+	struct cvmx_sli_win_wr_mask_s         cn68xx;
+	struct cvmx_sli_win_wr_mask_s         cn68xxp1;
+	struct cvmx_sli_win_wr_mask_s         cnf71xx;
 };
 typedef union cvmx_sli_win_wr_mask cvmx_sli_win_wr_mask_t;
 
@@ -4204,12 +6302,10 @@ typedef union cvmx_sli_win_wr_mask cvmx_sli_win_wr_mask_t;
  *  core clocks, the value of this register should be set to a minimum of 0x200000 to ensure that a timeout to an RML register
  *  occurs on the RML 0xFFFF timer before the timeout for a BAR0 access from the MAC.
  */
-union cvmx_sli_window_ctl
-{
+union cvmx_sli_window_ctl {
 	uint64_t u64;
-	struct cvmx_sli_window_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sli_window_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t time                         : 32; /**< Time to wait in core clocks for a
                                                          BAR0 access to completeon the NCB
@@ -4221,8 +6317,13 @@ union cvmx_sli_window_ctl
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_sli_window_ctl_s          cn61xx;
 	struct cvmx_sli_window_ctl_s          cn63xx;
 	struct cvmx_sli_window_ctl_s          cn63xxp1;
+	struct cvmx_sli_window_ctl_s          cn66xx;
+	struct cvmx_sli_window_ctl_s          cn68xx;
+	struct cvmx_sli_window_ctl_s          cn68xxp1;
+	struct cvmx_sli_window_ctl_s          cnf71xx;
 };
 typedef union cvmx_sli_window_ctl cvmx_sli_window_ctl_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-smi-defs.h b/sys/contrib/octeon-sdk/cvmx-smi-defs.h
index c77802f..2dbeb54 100644
--- a/sys/contrib/octeon-sdk/cvmx-smi-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-smi-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,14 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_SMI_TYPEDEFS_H__
-#define __CVMX_SMI_TYPEDEFS_H__
+#ifndef __CVMX_SMI_DEFS_H__
+#define __CVMX_SMI_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_SMI_DRV_CTL CVMX_SMI_DRV_CTL_FUNC()
 static inline uint64_t CVMX_SMI_DRV_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 		cvmx_warn("CVMX_SMI_DRV_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180000001828ull);
 }
@@ -70,12 +70,10 @@ static inline uint64_t CVMX_SMI_DRV_CTL_FUNC(void)
  * SMI_DRV_CTL = SMI Drive Strength Control
  *
  */
-union cvmx_smi_drv_ctl
-{
+union cvmx_smi_drv_ctl {
 	uint64_t u64;
-	struct cvmx_smi_drv_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_smi_drv_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t pctl                         : 6;  /**< PCTL Drive strength control bits
                                                          Assuming a 50ohm termination
@@ -93,8 +91,13 @@ union cvmx_smi_drv_ctl
 	uint64_t reserved_14_63               : 50;
 #endif
 	} s;
+	struct cvmx_smi_drv_ctl_s             cn61xx;
 	struct cvmx_smi_drv_ctl_s             cn63xx;
 	struct cvmx_smi_drv_ctl_s             cn63xxp1;
+	struct cvmx_smi_drv_ctl_s             cn66xx;
+	struct cvmx_smi_drv_ctl_s             cn68xx;
+	struct cvmx_smi_drv_ctl_s             cn68xxp1;
+	struct cvmx_smi_drv_ctl_s             cnf71xx;
 };
 typedef union cvmx_smi_drv_ctl cvmx_smi_drv_ctl_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-smix-defs.h b/sys/contrib/octeon-sdk/cvmx-smix-defs.h
index 9474666..0b79d33 100644
--- a/sys/contrib/octeon-sdk/cvmx-smix-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-smix-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,99 +49,149 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_SMIX_TYPEDEFS_H__
-#define __CVMX_SMIX_TYPEDEFS_H__
+#ifndef __CVMX_SMIX_DEFS_H__
+#define __CVMX_SMIX_DEFS_H__
 
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SMIX_CLK(unsigned long offset)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
-		cvmx_warn("CVMX_SMIX_CLK(%lu) is invalid on this chip\n", offset);
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if ((offset == 0))
+				return CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 0) * 256;
+			break;
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 3))
+				return CVMX_ADD_IO_SEG(0x0001180000003818ull) + ((offset) & 3) * 128;
+			break;
+	}
+	cvmx_warn("CVMX_SMIX_CLK (offset = %lu) not supported on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256;
 }
-#else
-#define CVMX_SMIX_CLK(offset) (CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SMIX_CMD(unsigned long offset)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
-		cvmx_warn("CVMX_SMIX_CMD(%lu) is invalid on this chip\n", offset);
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if ((offset == 0))
+				return CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 0) * 256;
+			break;
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 3))
+				return CVMX_ADD_IO_SEG(0x0001180000003800ull) + ((offset) & 3) * 128;
+			break;
+	}
+	cvmx_warn("CVMX_SMIX_CMD (offset = %lu) not supported on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256;
 }
-#else
-#define CVMX_SMIX_CMD(offset) (CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SMIX_EN(unsigned long offset)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
-		cvmx_warn("CVMX_SMIX_EN(%lu) is invalid on this chip\n", offset);
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if ((offset == 0))
+				return CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 0) * 256;
+			break;
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 3))
+				return CVMX_ADD_IO_SEG(0x0001180000003820ull) + ((offset) & 3) * 128;
+			break;
+	}
+	cvmx_warn("CVMX_SMIX_EN (offset = %lu) not supported on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256;
 }
-#else
-#define CVMX_SMIX_EN(offset) (CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
-		cvmx_warn("CVMX_SMIX_RD_DAT(%lu) is invalid on this chip\n", offset);
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if ((offset == 0))
+				return CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 0) * 256;
+			break;
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 3))
+				return CVMX_ADD_IO_SEG(0x0001180000003810ull) + ((offset) & 3) * 128;
+			break;
+	}
+	cvmx_warn("CVMX_SMIX_RD_DAT (offset = %lu) not supported on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256;
 }
-#else
-#define CVMX_SMIX_RD_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset)
 {
-	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
-		cvmx_warn("CVMX_SMIX_WR_DAT(%lu) is invalid on this chip\n", offset);
+	switch(cvmx_get_octeon_family()) {
+		case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+			if ((offset == 0))
+				return CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 0) * 256;
+			break;
+		case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+		case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 1))
+				return CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256;
+			break;
+		case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+			if ((offset <= 3))
+				return CVMX_ADD_IO_SEG(0x0001180000003808ull) + ((offset) & 3) * 128;
+			break;
+	}
+	cvmx_warn("CVMX_SMIX_WR_DAT (offset = %lu) not supported on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256;
 }
-#else
-#define CVMX_SMIX_WR_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256)
-#endif
 
 /**
  * cvmx_smi#_clk
@@ -149,12 +199,10 @@ static inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset)
  * SMI_CLK = Clock Control Register
  *
  */
-union cvmx_smix_clk
-{
+union cvmx_smix_clk {
 	uint64_t u64;
-	struct cvmx_smix_clk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_smix_clk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_25_63               : 39;
 	uint64_t mode                         : 1;  /**< IEEE operating mode
                                                          0=Clause 22 complient
@@ -198,9 +246,8 @@ union cvmx_smix_clk
 	uint64_t reserved_25_63               : 39;
 #endif
 	} s;
-	struct cvmx_smix_clk_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_smix_clk_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_21_63               : 43;
 	uint64_t sample_hi                    : 5;  /**< When to sample read data (extended bits) */
 	uint64_t sample_mode                  : 1;  /**< Read Data sampling mode
@@ -245,8 +292,13 @@ union cvmx_smix_clk
 	struct cvmx_smix_clk_s                cn56xxp1;
 	struct cvmx_smix_clk_cn30xx           cn58xx;
 	struct cvmx_smix_clk_cn30xx           cn58xxp1;
+	struct cvmx_smix_clk_s                cn61xx;
 	struct cvmx_smix_clk_s                cn63xx;
 	struct cvmx_smix_clk_s                cn63xxp1;
+	struct cvmx_smix_clk_s                cn66xx;
+	struct cvmx_smix_clk_s                cn68xx;
+	struct cvmx_smix_clk_s                cn68xxp1;
+	struct cvmx_smix_clk_s                cnf71xx;
 };
 typedef union cvmx_smix_clk cvmx_smix_clk_t;
 
@@ -260,12 +312,10 @@ typedef union cvmx_smix_clk cvmx_smix_clk_t;
  * Writes to this register will create SMI xactions.  Software will poll on (depending on the xaction type).
  *
  */
-union cvmx_smix_cmd
-{
+union cvmx_smix_cmd {
 	uint64_t u64;
-	struct cvmx_smix_cmd_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_smix_cmd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t phy_op                       : 2;  /**< PHY Opcode depending on SMI_CLK[MODE]
                                                          SMI_CLK[MODE] == 0 (<=1Gbs / Clause 22)
@@ -289,9 +339,8 @@ union cvmx_smix_cmd
 	uint64_t reserved_18_63               : 46;
 #endif
 	} s;
-	struct cvmx_smix_cmd_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_smix_cmd_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t phy_op                       : 1;  /**< PHY Opcode
                                                          0=write
@@ -319,8 +368,13 @@ union cvmx_smix_cmd
 	struct cvmx_smix_cmd_s                cn56xxp1;
 	struct cvmx_smix_cmd_cn30xx           cn58xx;
 	struct cvmx_smix_cmd_cn30xx           cn58xxp1;
+	struct cvmx_smix_cmd_s                cn61xx;
 	struct cvmx_smix_cmd_s                cn63xx;
 	struct cvmx_smix_cmd_s                cn63xxp1;
+	struct cvmx_smix_cmd_s                cn66xx;
+	struct cvmx_smix_cmd_s                cn68xx;
+	struct cvmx_smix_cmd_s                cn68xxp1;
+	struct cvmx_smix_cmd_s                cnf71xx;
 };
 typedef union cvmx_smix_cmd cvmx_smix_cmd_t;
 
@@ -330,12 +384,10 @@ typedef union cvmx_smix_cmd cvmx_smix_cmd_t;
  * SMI_EN = Enable the SMI interface
  *
  */
-union cvmx_smix_en
-{
+union cvmx_smix_en {
 	uint64_t u64;
-	struct cvmx_smix_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_smix_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t en                           : 1;  /**< Interface enable
                                                          0=SMI Interface is down / no transactions, no MDC
@@ -356,8 +408,13 @@ union cvmx_smix_en
 	struct cvmx_smix_en_s                 cn56xxp1;
 	struct cvmx_smix_en_s                 cn58xx;
 	struct cvmx_smix_en_s                 cn58xxp1;
+	struct cvmx_smix_en_s                 cn61xx;
 	struct cvmx_smix_en_s                 cn63xx;
 	struct cvmx_smix_en_s                 cn63xxp1;
+	struct cvmx_smix_en_s                 cn66xx;
+	struct cvmx_smix_en_s                 cn68xx;
+	struct cvmx_smix_en_s                 cn68xxp1;
+	struct cvmx_smix_en_s                 cnf71xx;
 };
 typedef union cvmx_smix_en cvmx_smix_en_t;
 
@@ -371,12 +428,10 @@ typedef union cvmx_smix_en cvmx_smix_en_t;
  * VAL will assert when the read xaction completes.  A read to this register
  * will clear VAL.  PENDING indicates that an SMI RD transaction is in flight.
  */
-union cvmx_smix_rd_dat
-{
+union cvmx_smix_rd_dat {
 	uint64_t u64;
-	struct cvmx_smix_rd_dat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_smix_rd_dat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t pending                      : 1;  /**< Read Xaction Pending */
 	uint64_t val                          : 1;  /**< Read Data Valid */
@@ -399,8 +454,13 @@ union cvmx_smix_rd_dat
 	struct cvmx_smix_rd_dat_s             cn56xxp1;
 	struct cvmx_smix_rd_dat_s             cn58xx;
 	struct cvmx_smix_rd_dat_s             cn58xxp1;
+	struct cvmx_smix_rd_dat_s             cn61xx;
 	struct cvmx_smix_rd_dat_s             cn63xx;
 	struct cvmx_smix_rd_dat_s             cn63xxp1;
+	struct cvmx_smix_rd_dat_s             cn66xx;
+	struct cvmx_smix_rd_dat_s             cn68xx;
+	struct cvmx_smix_rd_dat_s             cn68xxp1;
+	struct cvmx_smix_rd_dat_s             cnf71xx;
 };
 typedef union cvmx_smix_rd_dat cvmx_smix_rd_dat_t;
 
@@ -414,12 +474,10 @@ typedef union cvmx_smix_rd_dat cvmx_smix_rd_dat_t;
  * VAL will assert when the write xaction completes.  A read to this register
  * will clear VAL.  PENDING indicates that an SMI WR transaction is in flight.
  */
-union cvmx_smix_wr_dat
-{
+union cvmx_smix_wr_dat {
 	uint64_t u64;
-	struct cvmx_smix_wr_dat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_smix_wr_dat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t pending                      : 1;  /**< Write Xaction Pending */
 	uint64_t val                          : 1;  /**< Write Data Valid */
@@ -442,8 +500,13 @@ union cvmx_smix_wr_dat
 	struct cvmx_smix_wr_dat_s             cn56xxp1;
 	struct cvmx_smix_wr_dat_s             cn58xx;
 	struct cvmx_smix_wr_dat_s             cn58xxp1;
+	struct cvmx_smix_wr_dat_s             cn61xx;
 	struct cvmx_smix_wr_dat_s             cn63xx;
 	struct cvmx_smix_wr_dat_s             cn63xxp1;
+	struct cvmx_smix_wr_dat_s             cn66xx;
+	struct cvmx_smix_wr_dat_s             cn68xx;
+	struct cvmx_smix_wr_dat_s             cn68xxp1;
+	struct cvmx_smix_wr_dat_s             cnf71xx;
 };
 typedef union cvmx_smix_wr_dat cvmx_smix_wr_dat_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-spi.c b/sys/contrib/octeon-sdk/cvmx-spi.c
index 6cd7c08..6f44382 100644
--- a/sys/contrib/octeon-sdk/cvmx-spi.c
+++ b/sys/contrib/octeon-sdk/cvmx-spi.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Support library for the SPI
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <linux/module.h>
diff --git a/sys/contrib/octeon-sdk/cvmx-spi.h b/sys/contrib/octeon-sdk/cvmx-spi.h
index 9a47250..41dbc41 100644
--- a/sys/contrib/octeon-sdk/cvmx-spi.h
+++ b/sys/contrib/octeon-sdk/cvmx-spi.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * This file contains defines for the SPI interface
 
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  *
  */
diff --git a/sys/contrib/octeon-sdk/cvmx-spi4000.c b/sys/contrib/octeon-sdk/cvmx-spi4000.c
index 0a15fae..acdc7c3 100644
--- a/sys/contrib/octeon-sdk/cvmx-spi4000.c
+++ b/sys/contrib/octeon-sdk/cvmx-spi4000.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Support library for the SPI4000 card
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <linux/module.h>
diff --git a/sys/contrib/octeon-sdk/cvmx-spinlock.h b/sys/contrib/octeon-sdk/cvmx-spinlock.h
index b87602e..c8f74cb 100644
--- a/sys/contrib/octeon-sdk/cvmx-spinlock.h
+++ b/sys/contrib/octeon-sdk/cvmx-spinlock.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Implementation of spinlocks.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 
diff --git a/sys/contrib/octeon-sdk/cvmx-spx0-defs.h b/sys/contrib/octeon-sdk/cvmx-spx0-defs.h
index ff5b5a4..596b6fe 100644
--- a/sys/contrib/octeon-sdk/cvmx-spx0-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-spx0-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_SPX0_TYPEDEFS_H__
-#define __CVMX_SPX0_TYPEDEFS_H__
+#ifndef __CVMX_SPX0_DEFS_H__
+#define __CVMX_SPX0_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_SPX0_PLL_BW_CTL CVMX_SPX0_PLL_BW_CTL_FUNC()
@@ -78,12 +78,10 @@ static inline uint64_t CVMX_SPX0_PLL_SETTING_FUNC(void)
 /**
  * cvmx_spx0_pll_bw_ctl
  */
-union cvmx_spx0_pll_bw_ctl
-{
+union cvmx_spx0_pll_bw_ctl {
 	uint64_t u64;
-	struct cvmx_spx0_pll_bw_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spx0_pll_bw_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t bw_ctl                       : 5;  /**< Core PLL bandwidth control */
 #else
@@ -99,12 +97,10 @@ typedef union cvmx_spx0_pll_bw_ctl cvmx_spx0_pll_bw_ctl_t;
 /**
  * cvmx_spx0_pll_setting
  */
-union cvmx_spx0_pll_setting
-{
+union cvmx_spx0_pll_setting {
 	uint64_t u64;
-	struct cvmx_spx0_pll_setting_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spx0_pll_setting_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t setting                      : 17; /**< Core PLL setting */
 #else
diff --git a/sys/contrib/octeon-sdk/cvmx-spxx-defs.h b/sys/contrib/octeon-sdk/cvmx-spxx-defs.h
index 890cbf8..d9e326d 100644
--- a/sys/contrib/octeon-sdk/cvmx-spxx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-spxx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_SPXX_TYPEDEFS_H__
-#define __CVMX_SPXX_TYPEDEFS_H__
+#ifndef __CVMX_SPXX_DEFS_H__
+#define __CVMX_SPXX_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SPXX_BCKPRS_CNT(unsigned long block_id)
@@ -248,12 +248,10 @@ static inline uint64_t CVMX_SPXX_TRN4_CTL(unsigned long block_id)
 /**
  * cvmx_spx#_bckprs_cnt
  */
-union cvmx_spxx_bckprs_cnt
-{
+union cvmx_spxx_bckprs_cnt {
 	uint64_t u64;
-	struct cvmx_spxx_bckprs_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spxx_bckprs_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< Counts the number of core clock cycles in which
                                                          the SPI-4.2 receiver receives data once the TPA
@@ -281,12 +279,10 @@ typedef union cvmx_spxx_bckprs_cnt cvmx_spxx_bckprs_cnt_t;
  * - 0: good (or bist in progress/never run)
  * - 1: bad
  */
-union cvmx_spxx_bist_stat
-{
+union cvmx_spxx_bist_stat {
 	uint64_t u64;
-	struct cvmx_spxx_bist_stat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spxx_bist_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t stat2                        : 1;  /**< Bist Results/No Repair (Tx calendar table)
                                                          (spx.stx.cal.calendar) */
@@ -378,12 +374,10 @@ typedef union cvmx_spxx_bist_stat cvmx_spxx_bist_stat_t;
  *   sequence, the data bus will not send any data to the core.  The
  *   interface will hang.
  */
-union cvmx_spxx_clk_ctl
-{
+union cvmx_spxx_clk_ctl {
 	uint64_t u64;
-	struct cvmx_spxx_clk_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spxx_clk_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t seetrn                       : 1;  /**< Force the Spi4 receive into seeing a traing
                                                          sequence */
@@ -428,12 +422,10 @@ typedef union cvmx_spxx_clk_ctl cvmx_spxx_clk_ctl_t;
 /**
  * cvmx_spx#_clk_stat
  */
-union cvmx_spxx_clk_stat
-{
+union cvmx_spxx_clk_stat {
 	uint64_t u64;
-	struct cvmx_spxx_clk_stat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spxx_clk_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t stxcal                       : 1;  /**< The transistion from Sync to Calendar on status
                                                          channel */
@@ -567,12 +559,10 @@ typedef union cvmx_spxx_clk_stat cvmx_spxx_clk_stat_t;
  *   This bit should not be changed dynamically while the link is
  *   operational.
  */
-union cvmx_spxx_dbg_deskew_ctl
-{
+union cvmx_spxx_dbg_deskew_ctl {
 	uint64_t u64;
-	struct cvmx_spxx_dbg_deskew_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spxx_dbg_deskew_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_30_63               : 34;
 	uint64_t fallnop                      : 1;  /**< Training fallout on NOP matches instead of
                                                          non-training matches.
@@ -645,12 +635,10 @@ typedef union cvmx_spxx_dbg_deskew_ctl cvmx_spxx_dbg_deskew_ctl_t;
  * These bits are meant as a backdoor to control Spi4 per-bit deskew.  See
  * that Spec for more details.
  */
-union cvmx_spxx_dbg_deskew_state
-{
+union cvmx_spxx_dbg_deskew_state {
 	uint64_t u64;
-	struct cvmx_spxx_dbg_deskew_state_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spxx_dbg_deskew_state_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t testres                      : 1;  /**< Training Test Mode Result
                                                          (srx_spi4__test_mode_result) */
@@ -684,20 +672,17 @@ typedef union cvmx_spxx_dbg_deskew_state cvmx_spxx_dbg_deskew_state_t;
  * These bits all come from Duke - he will provide documentation and
  * explanation.  I'll just butcher it.
  */
-union cvmx_spxx_drv_ctl
-{
+union cvmx_spxx_drv_ctl {
 	uint64_t u64;
-	struct cvmx_spxx_drv_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spxx_drv_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_0_63                : 64;
 #else
 	uint64_t reserved_0_63                : 64;
 #endif
 	} s;
-	struct cvmx_spxx_drv_ctl_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spxx_drv_ctl_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t stx4ncmp                     : 4;  /**< Duke (spx__spi4_tx_nctl_comp) */
 	uint64_t stx4pcmp                     : 4;  /**< Duke (spx__spi4_tx_pctl_comp) */
@@ -710,14 +695,19 @@ union cvmx_spxx_drv_ctl
 #endif
 	} cn38xx;
 	struct cvmx_spxx_drv_ctl_cn38xx       cn38xxp2;
-	struct cvmx_spxx_drv_ctl_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spxx_drv_ctl_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
-	uint64_t stx4ncmp                     : 4;  /**< Duke (spx__spi4_tx_nctl_comp) */
-	uint64_t stx4pcmp                     : 4;  /**< Duke (spx__spi4_tx_pctl_comp) */
+	uint64_t stx4ncmp                     : 4;  /**< Not used in CN58XX (spx__spi4_tx_nctl_comp) */
+	uint64_t stx4pcmp                     : 4;  /**< Not used in CN58XX (spx__spi4_tx_pctl_comp) */
 	uint64_t reserved_10_15               : 6;
-	uint64_t srx4cmp                      : 10; /**< Duke (spx__spi4_rx_rctl_comp) */
+	uint64_t srx4cmp                      : 10; /**< Suresh (spx__spi4_rx_rctl_comp)
+                                                         Can be used to bypass the RX termination resistor
+                                                         value. We have an on-chip RX termination resistor
+                                                         compensation control block, which adjusts the
+                                                         resistor value to a nominal 100 ohms. This
+                                                         register can be used to bypass this automatically
+                                                         computed value. */
 #else
 	uint64_t srx4cmp                      : 10;
 	uint64_t reserved_10_15               : 6;
@@ -744,12 +734,10 @@ typedef union cvmx_spxx_drv_ctl cvmx_spxx_drv_ctl_t;
  * pass through the ERR bit without modifying it in anyway - the error bit
  * may or may not have been set by the transmitter device.
  */
-union cvmx_spxx_err_ctl
-{
+union cvmx_spxx_err_ctl {
 	uint64_t u64;
-	struct cvmx_spxx_err_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spxx_err_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t prtnxa                       : 1;  /**< Spi4 - set the ERR bit on packets in which the
                                                          port is out-of-range */
@@ -804,12 +792,10 @@ typedef union cvmx_spxx_err_ctl cvmx_spxx_err_ctl_t;
  * The MUL bit will be cleared once all outstanding errors have been
  * cleared by software (not just MUL errors - all errors).
  */
-union cvmx_spxx_int_dat
-{
+union cvmx_spxx_int_dat {
 	uint64_t u64;
-	struct cvmx_spxx_int_dat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spxx_int_dat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t mul                          : 1;  /**< Multiple errors have occured */
 	uint64_t reserved_14_30               : 17;
@@ -838,12 +824,10 @@ typedef union cvmx_spxx_int_dat cvmx_spxx_int_dat_t;
  * SPX_INT_MSK - Interrupt Mask Register
  *
  */
-union cvmx_spxx_int_msk
-{
+union cvmx_spxx_int_msk {
 	uint64_t u64;
-	struct cvmx_spxx_int_msk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spxx_int_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t calerr                       : 1;  /**< Spi4 Calendar table parity error */
 	uint64_t syncerr                      : 1;  /**< Consecutive Spi4 DIP4 errors have exceeded
@@ -1011,12 +995,10 @@ typedef union cvmx_spxx_int_msk cvmx_spxx_int_msk_t;
  *   that are contained to a single packet which allows the interface to drop
  *   a single packet and remain up and stable.
  */
-union cvmx_spxx_int_reg
-{
+union cvmx_spxx_int_reg {
 	uint64_t u64;
-	struct cvmx_spxx_int_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t spf                          : 1;  /**< Spi interface down */
 	uint64_t reserved_12_30               : 19;
@@ -1071,12 +1053,10 @@ typedef union cvmx_spxx_int_reg cvmx_spxx_int_reg_t;
  * free to synchronize the bus on other conditions, but this is the minimum
  * recommended set.
  */
-union cvmx_spxx_int_sync
-{
+union cvmx_spxx_int_sync {
 	uint64_t u64;
-	struct cvmx_spxx_int_sync_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spxx_int_sync_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t calerr                       : 1;  /**< Spi4 Calendar table parity error */
 	uint64_t syncerr                      : 1;  /**< Consecutive Spi4 DIP4 errors have exceeded
@@ -1126,12 +1106,10 @@ typedef union cvmx_spxx_int_sync cvmx_spxx_int_sync_t;
  * increment until the TPA for the port is asserted.  At that point the CNT
  * value is frozen until software clears the interrupt bit.
  */
-union cvmx_spxx_tpa_acc
-{
+union cvmx_spxx_tpa_acc {
 	uint64_t u64;
-	struct cvmx_spxx_tpa_acc_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spxx_tpa_acc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< TPA watcher accumulate count */
 #else
@@ -1159,12 +1137,10 @@ typedef union cvmx_spxx_tpa_acc cvmx_spxx_tpa_acc_t;
  * ticks, then the interrupt is conditionally raised (based on interrupt mask
  * bits).  This feature will be disabled if the programmed count is zero.
  */
-union cvmx_spxx_tpa_max
-{
+union cvmx_spxx_tpa_max {
 	uint64_t u64;
-	struct cvmx_spxx_tpa_max_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spxx_tpa_max_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t max                          : 32; /**< TPA watcher TPA threshold */
 #else
@@ -1202,12 +1178,10 @@ typedef union cvmx_spxx_tpa_max cvmx_spxx_tpa_max_t;
  * 2) The GMX inbound FIFO is filling up and should BP
  * 3) User has out an override on the TPA wires
  */
-union cvmx_spxx_tpa_sel
-{
+union cvmx_spxx_tpa_sel {
 	uint64_t u64;
-	struct cvmx_spxx_tpa_sel_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spxx_tpa_sel_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t prtsel                       : 4;  /**< TPA watcher port select */
 #else
@@ -1384,12 +1358,10 @@ typedef union cvmx_spxx_tpa_sel cvmx_spxx_tpa_sel_t;
  *    SRXX_COM_CTL[INF_EN].  At this point, the Spi4 packets will begin to
  *    be sent into the N2K core and processed by the chip.
  */
-union cvmx_spxx_trn4_ctl
-{
+union cvmx_spxx_trn4_ctl {
 	uint64_t u64;
-	struct cvmx_spxx_trn4_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_spxx_trn4_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t trntest                      : 1;  /**< Training Test Mode
                                                          This bit is only for initial bringup
diff --git a/sys/contrib/octeon-sdk/cvmx-srio.c b/sys/contrib/octeon-sdk/cvmx-srio.c
index f8511c6..ed9ba3e 100644
--- a/sys/contrib/octeon-sdk/cvmx-srio.c
+++ b/sys/contrib/octeon-sdk/cvmx-srio.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -60,6 +60,7 @@
 #include <asm/octeon/cvmx-dpi-defs.h>
 #include <asm/octeon/cvmx-pexp-defs.h>
 #include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-qlm.h>
 #else
 #include "cvmx.h"
 #include "cvmx-srio.h"
@@ -70,9 +71,10 @@
 #include "cvmx-error.h"
 #include "cvmx-helper-errata.h"
 #endif
+#include "cvmx-qlm.h"
+#include "cvmx-helper.h"
 #endif
 
-#define CVMX_SRIO_USE_FIFO_FOR_MAINT    1
 #define CVMX_SRIO_CONFIG_TIMEOUT        10000 /* 10ms */
 #define CVMX_SRIO_DOORBELL_TIMEOUT      10000 /* 10ms */
 #define CVMX_SRIO_CONFIG_PRIORITY       0
@@ -83,7 +85,7 @@ typedef union
     uint64_t    u64;
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    upper           : 2;    /* Normally 2 for XKPHYS */
         uint64_t    reserved_49_61  : 13;   /* Must be zero */
         uint64_t    io              : 1;    /* 1 for IO space access */
@@ -109,7 +111,7 @@ typedef union
     } config;
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    upper           : 2;    /* Normally 2 for XKPHYS */
         uint64_t    reserved_49_61  : 13;   /* Must be zero */
         uint64_t    io              : 1;    /* 1 for IO space access */
@@ -138,7 +140,7 @@ typedef struct
     int32_t s2m_ref_count[16];   /* Reference count for SRIOX_S2M_TYPE[0-15]. */
 } __cvmx_srio_state_t;
 
-static CVMX_SHARED __cvmx_srio_state_t __cvmx_srio_state[2];
+static CVMX_SHARED __cvmx_srio_state_t __cvmx_srio_state[4];
 
 
 #ifndef CVMX_BUILD_FOR_LINUX_HOST
@@ -170,6 +172,8 @@ static int __cvmx_srio_alloc_s2m(int srio_port, cvmx_sriox_s2m_typex_t s2m)
         {
             /* Unused location. Write our value */
             cvmx_write_csr(CVMX_SRIOX_S2M_TYPEX(s2m_index, srio_port), s2m.u64);
+            /* Read back to make sure the update is complete */
+            cvmx_read_csr(CVMX_SRIOX_S2M_TYPEX(s2m_index, srio_port));
             return s2m_index;
         }
         else
@@ -223,6 +227,8 @@ static int __cvmx_srio_alloc_subid(cvmx_sli_mem_access_subidx_t subid)
         {
             /* Unused location. Write our value */
             cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(mem_index), subid.u64);
+            /* Read back the value to make sure the update is complete */
+            cvmx_read_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(mem_index));
             return mem_index;
         }
         else
@@ -357,6 +363,49 @@ static int __cvmx_srio_local_write32(int srio_port, uint32_t offset, uint32_t da
 
 
 /**
+ * Reset SRIO to link partner
+ *
+ * @param srio_port  SRIO port to initialize
+ *
+ * @return Zero on success
+ */
+int cvmx_srio_link_rst(int srio_port)
+{
+    cvmx_sriomaintx_port_0_link_resp_t link_resp;
+
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+        return -1;
+
+    /* Generate a symbol reset to the link partner by writing 0x3. */
+    if (cvmx_srio_config_write32(srio_port, 0, -1, 0, 0,
+        CVMX_SRIOMAINTX_PORT_0_LINK_REQ(srio_port), 3))
+        return -1;
+
+    if (cvmx_srio_config_read32(srio_port, 0, -1, 0, 0,
+        CVMX_SRIOMAINTX_PORT_0_LINK_RESP(srio_port), &link_resp.u32))
+        return -1;
+
+    /* Poll until link partner has received the reset. */
+    while (link_resp.s.valid == 0)
+    {
+        //cvmx_dprintf("Waiting for Link Response\n");
+        if (cvmx_srio_config_read32(srio_port, 0, -1, 0, 0,
+            CVMX_SRIOMAINTX_PORT_0_LINK_RESP(srio_port), &link_resp.u32))
+            return -1;
+    }
+
+    /* Valid response, Asserting MAC reset */
+    cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);
+
+    cvmx_wait(10);
+
+    /* De-asserting MAC Reset */
+    cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x0);
+
+    return 0;
+}
+
+/**
  * Initialize a SRIO port for use.
  *
  * @param srio_port SRIO port to initialize
@@ -376,9 +425,21 @@ int cvmx_srio_initialize(int srio_port, cvmx_srio_initialize_flags_t flags)
     cvmx_sriox_imsg_vport_thr_t sriox_imsg_vport_thr;
     cvmx_dpi_sli_prtx_cfg_t prt_cfg;
     cvmx_sli_s2m_portx_ctl_t sli_s2m_portx_ctl;
+    cvmx_sli_mem_access_ctl_t sli_mem_access_ctl;
+    cvmx_sriomaintx_port_0_ctl2_t port_0_ctl2;
 
     sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(srio_port));
-    if (!sriox_status_reg.s.srio)
+    if (OCTEON_IS_MODEL(OCTEON_CN66XX))
+    {
+        /* All SRIO ports are connected to QLM0 */ 
+        int status = cvmx_qlm_get_status(0);
+        if (status < 4 || status > 6)
+        {
+            cvmx_dprintf("SRIO%d: Initialization called on a port not in SRIO mode\n", srio_port);
+            return -1;
+        }
+    }
+    else if (!sriox_status_reg.s.srio)
     {
         cvmx_dprintf("SRIO%d: Initialization called on a port not in SRIO mode\n", srio_port);
         return -1;
@@ -410,41 +471,146 @@ int cvmx_srio_initialize(int srio_port, cvmx_srio_initialize_flags_t flags)
         }
     }
 
-    mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(srio_port));
+    /* Don't receive or drive reset signals for the SRIO QLM */
+    if (OCTEON_IS_MODEL(OCTEON_CN66XX))
+    {
+        /* The reset signals are available only for srio_port == 0. */
+        if (srio_port == 0 || (OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_2) && srio_port == 1))
+        {
+            cvmx_mio_rst_cntlx_t mio_rst_cntl;
+            mio_rst_cntl.u64 = cvmx_read_csr(CVMX_MIO_RST_CNTLX(srio_port));
+            mio_rst_cntl.s.rst_drv = 0;
+            mio_rst_cntl.s.rst_rcv = 0;
+            mio_rst_cntl.s.rst_chip = 0;
+            cvmx_write_csr(CVMX_MIO_RST_CNTLX(srio_port), mio_rst_cntl.u64);
+        }
+        /* MIO_RST_CNTL2<prtmode> is initialized to 0 on cold reset */
+        mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CNTLX(srio_port));
+    }
+    else
+    {
+        mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(srio_port));
+        mio_rst_ctl.s.rst_drv = 0;
+        mio_rst_ctl.s.rst_rcv = 0;
+        mio_rst_ctl.s.rst_chip = 0;
+        cvmx_write_csr(CVMX_MIO_RST_CTLX(srio_port), mio_rst_ctl.u64);
+
+        mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(srio_port));
+    }
+
     cvmx_dprintf("SRIO%d: Port in %s mode\n", srio_port,
         (mio_rst_ctl.s.prtmode) ? "host" : "endpoint");
 
     /* Bring the port out of reset if necessary */
-    if (srio_port)
+    switch (srio_port)
     {
-        cvmx_ciu_soft_prst1_t prst;
-        prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
-        if (prst.s.soft_prst)
+        case 0:
         {
-            prst.s.soft_prst = 0;
-            cvmx_write_csr(CVMX_CIU_SOFT_PRST1, prst.u64);
-            cvmx_wait_usec(10000); /* 10ms for new link to stabalize */
+            cvmx_ciu_soft_prst_t prst;
+            prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+            if (prst.s.soft_prst)
+            {
+                prst.s.soft_prst = 0;
+                cvmx_write_csr(CVMX_CIU_SOFT_PRST, prst.u64);
+                /* Wait up to 250ms for the port to come out of reset */
+                if (CVMX_WAIT_FOR_FIELD64(CVMX_SRIOX_STATUS_REG(srio_port), cvmx_sriox_status_reg_t, access, ==, 1, 250000))
+                    return -1;
+            }
+            break;
         }
-    }
-    else
-    {
-        cvmx_ciu_soft_prst_t prst;
-        prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
-        if (prst.s.soft_prst)
+        case 1:
         {
-            prst.s.soft_prst = 0;
-            cvmx_write_csr(CVMX_CIU_SOFT_PRST, prst.u64);
-            cvmx_wait_usec(10000); /* 10ms for new link to stabalize */
+            cvmx_ciu_soft_prst1_t prst;
+            prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+            if (prst.s.soft_prst)
+            {
+                prst.s.soft_prst = 0;
+                cvmx_write_csr(CVMX_CIU_SOFT_PRST1, prst.u64);
+                /* Wait up to 250ms for the port to come out of reset */
+                if (CVMX_WAIT_FOR_FIELD64(CVMX_SRIOX_STATUS_REG(srio_port), cvmx_sriox_status_reg_t, access, ==, 1, 250000))
+                    return -1;
+            }
+            break;
+        }
+        case 2:
+        {
+            cvmx_ciu_soft_prst2_t prst;
+            prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST2);
+            if (prst.s.soft_prst)
+            {
+                prst.s.soft_prst = 0;
+                cvmx_write_csr(CVMX_CIU_SOFT_PRST2, prst.u64);
+                /* Wait up to 250ms for the port to come out of reset */
+                if (CVMX_WAIT_FOR_FIELD64(CVMX_SRIOX_STATUS_REG(srio_port), cvmx_sriox_status_reg_t, access, ==, 1, 250000))
+                    return -1;
+            }
+            break;
         }
     }
 
     /* Disable the link while we make changes */
     if (__cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_PORT_0_CTL(srio_port), &port_0_ctl.u32))
         return -1;
-    port_0_ctl.s.disable = 1;
+    port_0_ctl.s.o_enable = 0;
+    port_0_ctl.s.i_enable = 0;
+    port_0_ctl.s.prt_lock = 1;
+    port_0_ctl.s.disable = 0;
     if (__cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_PORT_0_CTL(srio_port), port_0_ctl.u32))
         return -1;
 
+    /* CN63XX Pass 2.0 and 2.1 errata G-15273 requires the QLM De-emphasis be
+        programmed when using a 156.25Mhz ref clock */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0) ||
+        OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_1))
+    {
+        cvmx_mio_rst_boot_t mio_rst_boot;
+        cvmx_sriomaintx_lane_x_status_0_t lane_x_status;
+
+        /* Read the QLM config and speed pins */
+        mio_rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
+        if (__cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_LANE_X_STATUS_0(0, srio_port), &lane_x_status.u32))
+            return -1;
+
+        if (srio_port)
+        {
+            cvmx_ciu_qlm1_t ciu_qlm;
+            ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1);
+            switch (mio_rst_boot.cn63xx.qlm1_spd)
+            {
+                case 0x4: /* 1.25 Gbaud, 156.25MHz */
+                    ciu_qlm.s.txbypass = 1;
+                    ciu_qlm.s.txdeemph = 0x0;
+                    ciu_qlm.s.txmargin = (lane_x_status.s.rx_type == 0) ? 0x11 : 0x1c; /* short or med/long */
+                    break;
+                case 0xb: /* 5.0 Gbaud, 156.25MHz */
+                    ciu_qlm.s.txbypass = 1;
+                    ciu_qlm.s.txdeemph = (lane_x_status.s.rx_type == 0) ? 0xa : 0xf; /* short or med/long */
+                    ciu_qlm.s.txmargin = (lane_x_status.s.rx_type == 0) ? 0xf : 0x1a; /* short or med/long */
+                    break;
+            }
+            cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64);
+        }
+        else
+        {
+            cvmx_ciu_qlm0_t ciu_qlm;
+            ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0);
+            switch (mio_rst_boot.cn63xx.qlm0_spd)
+            {
+                case 0x4: /* 1.25 Gbaud, 156.25MHz */
+                    ciu_qlm.s.txbypass = 1;
+                    ciu_qlm.s.txdeemph = 0x0;
+                    ciu_qlm.s.txmargin = (lane_x_status.s.rx_type == 0) ? 0x11 : 0x1c; /* short or med/long */
+                    break;
+                case 0xb: /* 5.0 Gbaud, 156.25MHz */
+                    ciu_qlm.s.txbypass = 1;
+                    ciu_qlm.s.txdeemph = (lane_x_status.s.rx_type == 0) ? 0xa : 0xf; /* short or med/long */
+                    ciu_qlm.s.txmargin = (lane_x_status.s.rx_type == 0) ? 0xf : 0x1a; /* short or med/long */
+                    break;
+            }
+            cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64);
+        }
+    }
+
     /* Errata SRIO-14485: Link speed is reported incorrectly in CN63XX
         pass 1.x */
     if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
@@ -481,19 +647,31 @@ int cvmx_srio_initialize(int srio_port, cvmx_srio_initialize_flags_t flags)
             return -1;
     }
 
-    /* Set the link layer timeout to 10us. The default is too high and causes
+    /* Errata SRIO-15351: Turn off SRIOMAINTX_MAC_CTRL[TYPE_MRG] as it may
+        cause packet ACCEPT to be lost */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0) || OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_1))
+    {
+        cvmx_sriomaintx_mac_ctrl_t mac_ctrl;
+        if (__cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_MAC_CTRL(srio_port), &mac_ctrl.u32))
+            return -1;
+        mac_ctrl.s.type_mrg = 0;
+        if (__cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_MAC_CTRL(srio_port), mac_ctrl.u32))
+            return -1;
+    }
+
+    /* Set the link layer timeout to 1ms. The default is too high and causes
         core bus errors */
     if (__cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_PORT_LT_CTL(srio_port), &port_lt_ctl.u32))
         return -1;
-    port_lt_ctl.s.timeout = 10000 / 200; /* 10us = 10000ns / 200ns */
+    port_lt_ctl.s.timeout = 1000000 / 200; /* 1ms = 1000000ns / 200ns */
     if (__cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_PORT_LT_CTL(srio_port), port_lt_ctl.u32))
         return -1;
 
-    /* Set the logical layer timeout to 10ms. The default is too high and causes
+    /* Set the logical layer timeout to 100ms. The default is too high and causes
         core bus errors */
     if (__cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_PORT_RT_CTL(srio_port), &port_rt_ctl.u32))
         return -1;
-    port_rt_ctl.s.timeout = 10000000 / 200; /* 10ms = 10000000ns / 200ns */
+    port_rt_ctl.s.timeout = 100000000 / 200; /* 100ms = 100000000ns / 200ns */
     if (__cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_PORT_RT_CTL(srio_port), port_rt_ctl.u32))
         return -1;
 
@@ -516,6 +694,11 @@ int cvmx_srio_initialize(int srio_port, cvmx_srio_initialize_flags_t flags)
     prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(srio_port));
     prt_cfg.s.mps = 1;
     prt_cfg.s.mrrs = 1;
+    prt_cfg.s.molr = 32;
+    if (OCTEON_IS_MODEL(OCTEON_CN66XX))
+        prt_cfg.s.molr = ((prt_cfg.s.qlm_cfg == 1 || prt_cfg.s.qlm_cfg == 3) ? 8
+                          : (prt_cfg.s.qlm_cfg == 4 || prt_cfg.s.qlm_cfg == 6) ? 16
+                          : 32);
     cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(srio_port), prt_cfg.u64);
 
     sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(srio_port));
@@ -524,7 +707,10 @@ int cvmx_srio_initialize(int srio_port, cvmx_srio_initialize_flags_t flags)
 
     /* Setup RX messaging thresholds */
     sriox_imsg_vport_thr.u64 = cvmx_read_csr(CVMX_SRIOX_IMSG_VPORT_THR(srio_port));
-    sriox_imsg_vport_thr.s.max_tot = 48;
+    if (OCTEON_IS_MODEL(OCTEON_CN66XX))
+        sriox_imsg_vport_thr.s.max_tot = ((prt_cfg.s.qlm_cfg == 1 || prt_cfg.s.qlm_cfg == 3) ? 44 : 46);
+    else
+        sriox_imsg_vport_thr.s.max_tot = 48;
     sriox_imsg_vport_thr.s.max_s1 = 24;
     sriox_imsg_vport_thr.s.max_s0 = 24;
     sriox_imsg_vport_thr.s.sp_vport = 1;
@@ -533,6 +719,16 @@ int cvmx_srio_initialize(int srio_port, cvmx_srio_initialize_flags_t flags)
     sriox_imsg_vport_thr.s.max_p0 = 12;
     cvmx_write_csr(CVMX_SRIOX_IMSG_VPORT_THR(srio_port), sriox_imsg_vport_thr.u64);
 
+    /* Setup RX messaging thresholds for other virtual ports. */
+    if (OCTEON_IS_MODEL(OCTEON_CN66XX))
+    {
+        cvmx_sriox_imsg_vport_thr2_t sriox_imsg_vport_thr2;
+        sriox_imsg_vport_thr2.u64 = cvmx_read_csr(CVMX_SRIOX_IMSG_VPORT_THR2(srio_port));
+        sriox_imsg_vport_thr2.s.max_s2 = 24;
+        sriox_imsg_vport_thr2.s.max_s3 = 24;
+        cvmx_write_csr(CVMX_SRIOX_IMSG_VPORT_THR2(srio_port), sriox_imsg_vport_thr2.u64);
+    }
+
     /* Errata SRIO-X: SRIO error behavior may not be optimal in CN63XX pass 1.x */
     if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
     {
@@ -544,6 +740,32 @@ int cvmx_srio_initialize(int srio_port, cvmx_srio_initialize_flags_t flags)
         cvmx_write_csr(CVMX_SRIOX_TX_CTRL(srio_port), sriox_tx_ctrl.u64);
     }
 
+    /* Errata SLI-15954: SLI relaxed order issues */
+    if (OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_X))
+    {
+        cvmx_sli_ctl_portx_t sli_ctl_portx;
+        sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(srio_port));
+        sli_ctl_portx.s.ptlp_ro = 1;    /* Set to same value for all MACs. */
+        sli_ctl_portx.s.ctlp_ro = 1;    /* Set to same value for all MACs. */
+        sli_ctl_portx.s.wait_com = 0;   /* So that no inbound stores wait for a commit */
+        sli_ctl_portx.s.waitl_com = 0;
+        cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(srio_port), sli_ctl_portx.u64);
+    }
+
+    if (!OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+    {
+        /* Clear the ACK state */
+        if (__cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(srio_port), 0))
+            return -1;
+    }
+
+    /* Bring the link down, then up, by writing to the SRIO port's
+       PORT_0_CTL2 CSR. */
+    if (__cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_PORT_0_CTL2(srio_port), &port_0_ctl2.u32))
+        return -1;
+    if (__cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_PORT_0_CTL2(srio_port), port_0_ctl2.u32))
+        return -1;
+
     /* Clear any pending interrupts */
     cvmx_write_csr(CVMX_SRIOX_INT_REG(srio_port), cvmx_read_csr(CVMX_SRIOX_INT_REG(srio_port)));
 
@@ -562,6 +784,74 @@ int cvmx_srio_initialize(int srio_port, cvmx_srio_initialize_flags_t flags)
     if (__cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_PORT_0_CTL(srio_port), port_0_ctl.u32))
         return -1;
 
+    /* Store merge control (SLI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
+    sli_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL);
+    sli_mem_access_ctl.s.max_word = 0;     /* Allow 16 words to combine */
+    sli_mem_access_ctl.s.timer = 127;      /* Wait up to 127 cycles for more data */
+    cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL, sli_mem_access_ctl.u64);
+
+    /* FIXME: Disable sending a link request when the SRIO link is
+        brought up. For unknown reasons this code causes issues with some SRIO
+        devices. As we currently don't support hotplug in software, this code
+        should never be needed.  Without link down/up events, the ACKs should
+        start off and stay synchronized */
+#if 0
+    /* Ask for a link and align our ACK state. CN63XXp1 didn't support this */
+    if (!OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+    {
+        uint64_t stop_cycle;
+        cvmx_sriomaintx_port_0_err_stat_t sriomaintx_port_0_err_stat;
+
+        /* Clear the SLI_CTL_PORTX[DIS_PORT[ bit to re-enable traffic-flow
+           to the SRIO MACs. */
+        cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(srio_port), cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(srio_port)));
+
+        /* Wait a little to see if the link comes up */
+        stop_cycle = cvmx_clock_get_rate(CVMX_CLOCK_CORE)/4 + cvmx_clock_get_count(CVMX_CLOCK_CORE);
+        do
+        {
+            /* Read the port link status */
+            if (__cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_PORT_0_ERR_STAT(srio_port), &sriomaintx_port_0_err_stat.u32))
+                return -1;
+        } while (!sriomaintx_port_0_err_stat.s.pt_ok && (cvmx_clock_get_count(CVMX_CLOCK_CORE) < stop_cycle));
+
+        /* Send link request if link is up */
+        if (sriomaintx_port_0_err_stat.s.pt_ok)
+        {
+            cvmx_sriomaintx_port_0_link_req_t link_req;
+            cvmx_sriomaintx_port_0_link_resp_t link_resp;
+            link_req.u32 = 0;
+            link_req.s.cmd = 4;
+
+            /* Send the request */
+            if (__cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_PORT_0_LINK_REQ(srio_port), link_req.u32))
+                return -1;
+
+            /* Wait for the response */
+            stop_cycle = cvmx_clock_get_rate(CVMX_CLOCK_CORE)/8 + cvmx_clock_get_count(CVMX_CLOCK_CORE);
+            do
+            {
+                if (__cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_PORT_0_LINK_RESP(srio_port), &link_resp.u32))
+                    return -1;
+            } while (!link_resp.s.valid && (cvmx_clock_get_count(CVMX_CLOCK_CORE) < stop_cycle));
+
+            /* Set our ACK state if we got a response */
+            if (link_resp.s.valid)
+            {
+                cvmx_sriomaintx_port_0_local_ackid_t local_ackid;
+                local_ackid.u32 = 0;
+                local_ackid.s.i_ackid = 0;
+                local_ackid.s.e_ackid = link_resp.s.ackid;
+                local_ackid.s.o_ackid = link_resp.s.ackid;
+                if (__cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(srio_port), local_ackid.u32))
+                    return -1;
+            }
+            else 
+                return -1;
+        }
+    }
+#endif
+
     return 0;
 }
 
@@ -596,138 +886,146 @@ int cvmx_srio_config_read32(int srio_port, int srcid_index, int destid,
     }
     else
     {
-#if CVMX_SRIO_USE_FIFO_FOR_MAINT
-        int return_code;
-        uint32_t pkt = 0;
-        uint32_t sourceid;
-        uint64_t stop_cycle;
-        char rx_buffer[64];
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+        {
+            int return_code;
+            uint32_t pkt = 0;
+            uint32_t sourceid;
+            uint64_t stop_cycle;
+            char rx_buffer[64];
 
-        /* Tell the user */
-        if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
-            cvmx_dprintf("SRIO%d: Remote read [id=0x%04x hop=%3d offset=0x%06x] <= ", srio_port, destid, hopcount, (unsigned int)offset);
+            /* Tell the user */
+            if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+                cvmx_dprintf("SRIO%d: Remote read [id=0x%04x hop=%3d offset=0x%06x] <= ", srio_port, destid, hopcount, (unsigned int)offset);
 
-        /* Read the proper source ID */
-        if (srcid_index)
-            __cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_SEC_DEV_ID(srio_port), &sourceid);
-        else
-            __cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_PRI_DEV_ID(srio_port), &sourceid);
+            /* Read the proper source ID */
+            if (srcid_index)
+                __cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_SEC_DEV_ID(srio_port), &sourceid);
+            else
+                __cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_PRI_DEV_ID(srio_port), &sourceid);
 
-        if (is16bit)
-        {
-            /* Use the 16bit source ID */
-            sourceid &= 0xffff;
-
-            /* MAINT Reads are 11 bytes */
-            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_CTRL(srio_port), 11<<16);
-
-            pkt |= CVMX_SRIO_CONFIG_PRIORITY << 30; /* priority [31:30] */
-            pkt |= 1 << 28;                         /* tt       [29:28] */
-            pkt |= 0x8 << 24;                       /* ftype    [27:24] */
-            pkt |= destid << 8;                     /* destID   [23:8] */
-            pkt |= sourceid >> 8;                   /* sourceID [7:0] */
-            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
-            pkt = 0;
-            pkt |= sourceid << 24;                  /* sourceID [31:24] */
-            pkt |= 0 << 20;                         /* transaction [23:20] */
-            pkt |= 8 << 16;                         /* rdsize [19:16] */
-            pkt |= 0xc0 << 8;                       /* srcTID [15:8] */
-            pkt |= hopcount;                        /* hopcount [7:0] */
-            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
-            pkt = 0;
-            pkt |= offset << 8;                     /* offset [31:11, wdptr[10], reserved[9:8] */
-            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
-        }
-        else
-        {
-            /* Use the 8bit source ID */
-            sourceid = (sourceid >> 16) & 0xff;
-
-            /* MAINT Reads are 9 bytes */
-            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_CTRL(srio_port), 9<<16);
-
-            pkt |= CVMX_SRIO_CONFIG_PRIORITY << 30; /* priority [31:30] */
-            pkt |= 0 << 28;                         /* tt       [29:28] */
-            pkt |= 0x8 << 24;                       /* ftype    [27:24] */
-            pkt |= destid << 16;                    /* destID   [23:16] */
-            pkt |= sourceid << 8;                   /* sourceID [15:8] */
-            pkt |= 0 << 4;                          /* transaction [7:4] */
-            pkt |= 8 << 0;                          /* rdsize [3:0] */
-            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
-            pkt = 0;
-            pkt |= 0xc0 << 24;                      /* srcTID [31:24] */
-            pkt |= hopcount << 16;                  /* hopcount [23:16] */
-            pkt |= offset >> 8;                     /* offset [15:0] */
-            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
-            pkt = 0;
-            pkt |= offset << 24;                    /* offset [31:27, wdptr[26], reserved[25:24] */
-            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
-        }
+            if (is16bit)
+            {
+                /* Use the 16bit source ID */
+                sourceid &= 0xffff;
 
-        stop_cycle = cvmx_clock_get_rate(CVMX_CLOCK_CORE)/10 + cvmx_clock_get_count(CVMX_CLOCK_CORE);
-        do
-        {
-            return_code = cvmx_srio_receive_spf(srio_port, rx_buffer, sizeof(rx_buffer));
-            if ((return_code == 0) && (cvmx_clock_get_count(CVMX_CLOCK_CORE) > stop_cycle))
+                /* MAINT Reads are 11 bytes */
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_CTRL(srio_port), 11<<16);
+
+                pkt |= CVMX_SRIO_CONFIG_PRIORITY << 30; /* priority [31:30] */
+                pkt |= 1 << 28;                         /* tt       [29:28] */
+                pkt |= 0x8 << 24;                       /* ftype    [27:24] */
+                pkt |= destid << 8;                     /* destID   [23:8] */
+                pkt |= sourceid >> 8;                   /* sourceID [7:0] */
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                pkt = 0;
+                pkt |= sourceid << 24;                  /* sourceID [31:24] */
+                pkt |= 0 << 20;                         /* transaction [23:20] */
+                pkt |= 8 << 16;                         /* rdsize [19:16] */
+                pkt |= 0xc0 << 8;                       /* srcTID [15:8] */
+                pkt |= hopcount;                        /* hopcount [7:0] */
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                pkt = 0;
+                pkt |= offset << 8;                     /* offset [31:11, wdptr[10], reserved[9:8] */
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+            }
+            else
             {
-                if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
-                    cvmx_dprintf("timeout\n");
-                return_code = -1;
+                /* Use the 8bit source ID */
+                sourceid = (sourceid >> 16) & 0xff;
+
+                /* MAINT Reads are 9 bytes */
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_CTRL(srio_port), 9<<16);
+
+                pkt |= CVMX_SRIO_CONFIG_PRIORITY << 30; /* priority [31:30] */
+                pkt |= 0 << 28;                         /* tt       [29:28] */
+                pkt |= 0x8 << 24;                       /* ftype    [27:24] */
+                pkt |= destid << 16;                    /* destID   [23:16] */
+                pkt |= sourceid << 8;                   /* sourceID [15:8] */
+                pkt |= 0 << 4;                          /* transaction [7:4] */
+                pkt |= 8 << 0;                          /* rdsize [3:0] */
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                pkt = 0;
+                pkt |= 0xc0 << 24;                      /* srcTID [31:24] */
+                pkt |= hopcount << 16;                  /* hopcount [23:16] */
+                pkt |= offset >> 8;                     /* offset [15:0] */
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                pkt = 0;
+                pkt |= offset << 24;                    /* offset [31:27, wdptr[26], reserved[25:24] */
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
             }
-        } while (return_code == 0);
 
-        if (return_code == ((is16bit) ? 23 : 19))
-        {
-            if (is16bit)
+            stop_cycle = cvmx_clock_get_rate(CVMX_CLOCK_CORE)/10 + cvmx_clock_get_count(CVMX_CLOCK_CORE);
+            do
             {
-                if (offset & 4)
-                    *result = *(uint32_t*)(rx_buffer + 15);
+                return_code = cvmx_srio_receive_spf(srio_port, rx_buffer, sizeof(rx_buffer));
+                if ((return_code == 0) && (cvmx_clock_get_count(CVMX_CLOCK_CORE) > stop_cycle))
+                {
+                    if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+                        cvmx_dprintf("timeout\n");
+                    return_code = -1;
+                }
+            } while (return_code == 0);
+
+            if (return_code == ((is16bit) ? 23 : 19))
+            {
+                if (is16bit)
+                {
+                    if (offset & 4)
+                        *result = *(uint32_t*)(rx_buffer + 15);
+                    else
+                        *result = *(uint32_t*)(rx_buffer + 11);
+                }
                 else
-                    *result = *(uint32_t*)(rx_buffer + 11);
+                {
+                    if (offset & 4)
+                        *result = *(uint32_t*)(rx_buffer + 13);
+                    else
+                        *result = *(uint32_t*)(rx_buffer + 9);
+                }
+                if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+                    cvmx_dprintf("0x%08x\n", (unsigned int)*result);
+                return_code = 0;
             }
             else
             {
-                if (offset & 4)
-                    *result = *(uint32_t*)(rx_buffer + 13);
-                else
-                    *result = *(uint32_t*)(rx_buffer + 9);
+                *result = 0xffffffff;
+                return_code = -1;
             }
-            if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
-                cvmx_dprintf("0x%08x\n", (unsigned int)*result);
-            return_code = 0;
+
+            return return_code;
         }
         else
         {
-            *result = 0xffffffff;
-            return_code = -1;
-        }
-
-        return return_code;
-#elif !defined(CVMX_BUILD_FOR_LINUX_HOST)
-        uint64_t physical;
-        physical = cvmx_srio_physical_map(srio_port,
-            CVMX_SRIO_WRITE_MODE_MAINTENANCE, CVMX_SRIO_CONFIG_PRIORITY,
-            CVMX_SRIO_READ_MODE_MAINTENANCE, CVMX_SRIO_CONFIG_PRIORITY,
-            srcid_index, destid, is16bit, offset + (hopcount<<24), 4);
-        if (!physical)
-            return -1;
+#if !defined(CVMX_BUILD_FOR_LINUX_HOST)
+            uint64_t physical;
+            physical = cvmx_srio_physical_map(srio_port,
+                CVMX_SRIO_WRITE_MODE_MAINTENANCE, CVMX_SRIO_CONFIG_PRIORITY,
+                CVMX_SRIO_READ_MODE_MAINTENANCE, CVMX_SRIO_CONFIG_PRIORITY,
+                srcid_index, destid, is16bit, offset + (hopcount<<24), 4);
+            if (!physical)
+                return -1;
 
-        if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
-            cvmx_dprintf("SRIO%d: Remote read [id=0x%04x hop=%3d offset=0x%06x] <= ", srio_port, destid, hopcount, offset);
+            if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+                cvmx_dprintf("SRIO%d: Remote read [id=0x%04x hop=%3d offset=0x%06x] <= ", srio_port, destid, hopcount, (unsigned int)offset);
 
-        /* Finally do the maintenance read to complete the config request */
-        *result = cvmx_read64_uint32(CVMX_ADD_IO_SEG(physical));
-        cvmx_srio_physical_unmap(physical, 4);
+            /* Finally do the maintenance read to complete the config request */
+            *result = cvmx_read64_uint32(CVMX_ADD_IO_SEG(physical));
+            cvmx_srio_physical_unmap(physical, 4);
 
-        if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
-            cvmx_dprintf("0x%08x\n", *result);
+            if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+                cvmx_dprintf("0x%08x\n", (unsigned int)*result);
 
-        return 0;
+            return 0;
 #else
-        return -1;
+            return -1;
 #endif
+        }
     }
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_srio_config_read32);
+#endif
 
 
 /**
@@ -758,142 +1056,147 @@ int cvmx_srio_config_write32(int srio_port, int srcid_index, int destid,
     }
     else
     {
-#if CVMX_SRIO_USE_FIFO_FOR_MAINT
-        int return_code;
-        uint32_t pkt = 0;
-        uint32_t sourceid;
-        uint64_t stop_cycle;
-        char rx_buffer[64];
-
-        /* Tell the user */
-        if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
-            cvmx_dprintf("SRIO%d: Remote write[id=0x%04x hop=%3d offset=0x%06x] => 0x%08x\n", srio_port, destid, hopcount, (unsigned int)offset, (unsigned int)data);
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+        {
+            int return_code;
+            uint32_t pkt = 0;
+            uint32_t sourceid;
+            uint64_t stop_cycle;
+            char rx_buffer[64];
 
-        /* Read the proper source ID */
-        if (srcid_index)
-            __cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_SEC_DEV_ID(srio_port), &sourceid);
-        else
-            __cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_PRI_DEV_ID(srio_port), &sourceid);
+            /* Tell the user */
+            if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+                cvmx_dprintf("SRIO%d: Remote write[id=0x%04x hop=%3d offset=0x%06x] => 0x%08x\n", srio_port, destid, hopcount, (unsigned int)offset, (unsigned int)data);
 
-        if (is16bit)
-        {
-            /* Use the 16bit source ID */
-            sourceid &= 0xffff;
-
-            /* MAINT Writes are 19 bytes */
-            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_CTRL(srio_port), 19<<16);
-
-            pkt |= CVMX_SRIO_CONFIG_PRIORITY << 30; /* priority [31:30] */
-            pkt |= 1 << 28;                         /* tt       [29:28] */
-            pkt |= 0x8 << 24;                       /* ftype    [27:24] */
-            pkt |= destid << 8;                     /* destID   [23:8] */
-            pkt |= sourceid >> 8;                   /* sourceID [7:0] */
-            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
-            pkt = 0;
-            pkt |= sourceid << 24;                  /* sourceID [31:24] */
-            pkt |= 1 << 20;                         /* transaction [23:20] */
-            pkt |= 8 << 16;                         /* wrsize [19:16] */
-            pkt |= 0xc0 << 8;                       /* srcTID [15:8] */
-            pkt |= hopcount;                        /* hopcount [7:0] */
-            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
-            pkt = 0;
-            pkt |= offset << 8;                     /* offset [31:11, wdptr[10], reserved[9:8] */
-            if ((offset & 4) == 0)
-                pkt |= 0xff & (data >> 24);       /* data [7:0] */
-            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
-            if (offset & 4)
-            {
-                pkt = 0xff & (data >> 24);
-                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
-                pkt = data << 8;
-                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
-            }
+            /* Read the proper source ID */
+            if (srcid_index)
+                __cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_SEC_DEV_ID(srio_port), &sourceid);
             else
+                __cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_PRI_DEV_ID(srio_port), &sourceid);
+
+            if (is16bit)
             {
-                pkt = data << 8;
-                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
-                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), 0);
-            }
-        }
-        else
-        {
-            /* Use the 8bit source ID */
-            sourceid = (sourceid >> 16) & 0xff;
-
-            /* MAINT Writes are 17 bytes */
-            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_CTRL(srio_port), 17<<16);
-
-            pkt |= CVMX_SRIO_CONFIG_PRIORITY << 30; /* priority [31:30] */
-            pkt |= 0 << 28;                         /* tt       [29:28] */
-            pkt |= 0x8 << 24;                       /* ftype    [27:24] */
-            pkt |= destid << 16;                    /* destID   [23:16] */
-            pkt |= sourceid << 8;                   /* sourceID [15:8] */
-            pkt |= 1 << 4;                          /* transaction [7:4] */
-            pkt |= 8 << 0;                          /* wrsize [3:0] */
-            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
-            pkt = 0;
-            pkt |= 0xc0 << 24;                      /* srcTID [31:24] */
-            pkt |= hopcount << 16;                  /* hopcount [23:16] */
-            pkt |= offset >> 8;                     /* offset [15:0] */
-            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
-            pkt = 0;
-            pkt |= offset << 24;                    /* offset [31:27, wdptr[26], reserved[25:24] */
-            if (offset & 4)
-            {
+                /* Use the 16bit source ID */
+                sourceid &= 0xffff;
+
+                /* MAINT Writes are 19 bytes */
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_CTRL(srio_port), 19<<16);
+
+                pkt |= CVMX_SRIO_CONFIG_PRIORITY << 30; /* priority [31:30] */
+                pkt |= 1 << 28;                         /* tt       [29:28] */
+                pkt |= 0x8 << 24;                       /* ftype    [27:24] */
+                pkt |= destid << 8;                     /* destID   [23:8] */
+                pkt |= sourceid >> 8;                   /* sourceID [7:0] */
                 __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
-                pkt = data >> 8;
+                pkt = 0;
+                pkt |= sourceid << 24;                  /* sourceID [31:24] */
+                pkt |= 1 << 20;                         /* transaction [23:20] */
+                pkt |= 8 << 16;                         /* wrsize [19:16] */
+                pkt |= 0xc0 << 8;                       /* srcTID [15:8] */
+                pkt |= hopcount;                        /* hopcount [7:0] */
                 __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
-                pkt = data << 24;
+                pkt = 0;
+                pkt |= offset << 8;                     /* offset [31:11, wdptr[10], reserved[9:8] */
+                if ((offset & 4) == 0)
+                    pkt |= 0xff & (data >> 24);       /* data [7:0] */
                 __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                if (offset & 4)
+                {
+                    pkt = 0xff & (data >> 24);
+                    __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                    pkt = data << 8;
+                    __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                }
+                else
+                {
+                    pkt = data << 8;
+                    __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                    __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), 0);
+                }
             }
             else
             {
-                pkt |= data >> 8;                    /* data [23:0] */
+                /* Use the 8bit source ID */
+                sourceid = (sourceid >> 16) & 0xff;
+
+                /* MAINT Writes are 17 bytes */
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_CTRL(srio_port), 17<<16);
+
+                pkt |= CVMX_SRIO_CONFIG_PRIORITY << 30; /* priority [31:30] */
+                pkt |= 0 << 28;                         /* tt       [29:28] */
+                pkt |= 0x8 << 24;                       /* ftype    [27:24] */
+                pkt |= destid << 16;                    /* destID   [23:16] */
+                pkt |= sourceid << 8;                   /* sourceID [15:8] */
+                pkt |= 1 << 4;                          /* transaction [7:4] */
+                pkt |= 8 << 0;                          /* wrsize [3:0] */
                 __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
-                pkt = data << 24;                    /* data [31:24] */
+                pkt = 0;
+                pkt |= 0xc0 << 24;                      /* srcTID [31:24] */
+                pkt |= hopcount << 16;                  /* hopcount [23:16] */
+                pkt |= offset >> 8;                     /* offset [15:0] */
                 __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
-                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), 0);
+                pkt = 0;
+                pkt |= offset << 24;                    /* offset [31:27, wdptr[26], reserved[25:24] */
+                if (offset & 4)
+                {
+                    __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                    pkt = data >> 8;
+                    __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                    pkt = data << 24;
+                    __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                }
+                else
+                {
+                    pkt |= data >> 8;                    /* data [23:0] */
+                    __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                    pkt = data << 24;                    /* data [31:24] */
+                    __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                    __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), 0);
+                }
             }
-        }
 
-        stop_cycle = cvmx_clock_get_rate(CVMX_CLOCK_CORE)/10 + cvmx_clock_get_count(CVMX_CLOCK_CORE);
-        do
-        {
-            return_code = cvmx_srio_receive_spf(srio_port, rx_buffer, sizeof(rx_buffer));
-            if ((return_code == 0) && (cvmx_clock_get_count(CVMX_CLOCK_CORE) > stop_cycle))
+            stop_cycle = cvmx_clock_get_rate(CVMX_CLOCK_CORE)/10 + cvmx_clock_get_count(CVMX_CLOCK_CORE);
+            do
             {
-                if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
-                    cvmx_dprintf("timeout\n");
+                return_code = cvmx_srio_receive_spf(srio_port, rx_buffer, sizeof(rx_buffer));
+                if ((return_code == 0) && (cvmx_clock_get_count(CVMX_CLOCK_CORE) > stop_cycle))
+                {
+                    if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+                        cvmx_dprintf("timeout\n");
+                    return_code = -1;
+                }
+            } while (return_code == 0);
+
+            if (return_code == ((is16bit) ? 15 : 11))
+                return_code = 0;
+            else
+            {
+                cvmx_dprintf("SRIO%d: Remote write failed\n", srio_port);
                 return_code = -1;
             }
-        } while (return_code == 0);
 
-        if (return_code == ((is16bit) ? 15 : 11))
-            return_code = 0;
+            return return_code;
+        }
         else
         {
-            cvmx_dprintf("SRIO%d: Remote write failed\n", srio_port);
-            return_code = -1;
-        }
+#if !defined(CVMX_BUILD_FOR_LINUX_HOST)
+            uint64_t physical = cvmx_srio_physical_map(srio_port,
+                    CVMX_SRIO_WRITE_MODE_MAINTENANCE, CVMX_SRIO_CONFIG_PRIORITY,
+                    CVMX_SRIO_READ_MODE_MAINTENANCE, CVMX_SRIO_CONFIG_PRIORITY,
+                    srcid_index, destid, is16bit, offset + (hopcount<<24), 4);
+            if (!physical)
+                return -1;
 
-        return return_code;
-#elif !defined(CVMX_BUILD_FOR_LINUX_HOST)
-        uint64_t physical = cvmx_srio_physical_map(srio_port,
-                CVMX_SRIO_WRITE_MODE_MAINTENANCE, CVMX_SRIO_CONFIG_PRIORITY,
-                CVMX_SRIO_READ_MODE_MAINTENANCE, CVMX_SRIO_CONFIG_PRIORITY,
-                srcid_index, destid, is16bit, offset + (hopcount<<24), 4);
-        if (!physical)
-            return -1;
-
-        if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
-            cvmx_dprintf("SRIO%d: Remote write[id=0x%04x hop=%3d offset=0x%06x] => 0x%08x\n", srio_port, destid, hopcount, offset, data);
+            if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+                cvmx_dprintf("SRIO%d: Remote write[id=0x%04x hop=%3d offset=0x%06x] => 0x%08x\n", srio_port, destid, hopcount, (unsigned int)offset, (unsigned int)data);
 
-        /* Finally do the maintenance write to complete the config request */
-        cvmx_write64_uint32(CVMX_ADD_IO_SEG(physical), data);
-        return cvmx_srio_physical_unmap(physical, 4);
+            /* Finally do the maintenance write to complete the config request */
+            cvmx_write64_uint32(CVMX_ADD_IO_SEG(physical), data);
+            return cvmx_srio_physical_unmap(physical, 4);
 #else
-        return -1;
+            return -1;
 #endif
+        }
     }
 }
 
@@ -938,7 +1241,9 @@ int cvmx_srio_send_doorbell(int srio_port, int srcid_index, int destid, int is16
     cvmx_write_csr(CVMX_SRIOX_TX_BELL(srio_port), tx_bell.u64);
     return 0;
 }
-
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_srio_send_doorbell);
+#endif
 
 /**
  * Get the status of the last doorbell sent. If the dooorbell
@@ -974,7 +1279,9 @@ cvmx_srio_doorbell_status_t cvmx_srio_send_doorbell_status(int srio_port)
         if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
             cvmx_dprintf("SRIO%d: Send doorbell failed\n", srio_port);
         tx_bell_info.u64 = cvmx_read_csr(CVMX_SRIOX_TX_BELL_INFO(srio_port));
-        if (tx_bell_info.s.timeout || tx_bell_info.s.error)
+        if (tx_bell_info.s.timeout)
+            return CVMX_SRIO_DOORBELL_TMOUT;
+        if (tx_bell_info.s.error)
             return CVMX_SRIO_DOORBELL_ERROR;
         if (tx_bell_info.s.retry)
             return CVMX_SRIO_DOORBELL_RETRY;
@@ -1141,7 +1448,7 @@ uint64_t cvmx_srio_physical_map(int srio_port, cvmx_srio_write_mode_t write_op,
     /* Build the needed SubID config */
     needed_subid.u64 = 0;
     needed_subid.s.port = srio_port;
-    needed_subid.s.nmerge = 1;
+    needed_subid.s.nmerge = 0;
 
     /* FIXME: We might want to use the device ID swapping modes so the device
         ID is part of the lower address bits. This would allow many more
@@ -1149,14 +1456,14 @@ uint64_t cvmx_srio_physical_map(int srio_port, cvmx_srio_write_mode_t write_op,
         to fit in bits [17:0] or bits[25:0] for 8 bits of device ID */
     if (base < (1ull<<34))
     {
-        needed_subid.s.ba = destid;
+        needed_subid.cn63xx.ba = destid;
         needed_s2m_type.s.iaow_sel = 0;
     }
     else if (base < (1ull<<42))
     {
-        needed_subid.s.ba = (base>>34) & 0xff;
-        needed_subid.s.ba |= ((uint64_t)destid & 0xff) << (42-34);
-        needed_subid.s.ba |= (((uint64_t)destid>>8) & 0xff) << (51-34);
+        needed_subid.cn63xx.ba = (base>>34) & 0xff;
+        needed_subid.cn63xx.ba |= ((uint64_t)destid & 0xff) << (42-34);
+        needed_subid.cn63xx.ba |= (((uint64_t)destid>>8) & 0xff) << (51-34);
         needed_s2m_type.s.iaow_sel = 1;
     }
     else
@@ -1171,8 +1478,8 @@ uint64_t cvmx_srio_physical_map(int srio_port, cvmx_srio_write_mode_t write_op,
             cvmx_dprintf("SRIO%d: Attempt to map address 0x%llx using 66bit addressing\n", srio_port, (ULL)base);
             return 0;
         }
-        needed_subid.s.ba = (base>>34) & 0xffff;
-        needed_subid.s.ba |= ((uint64_t)destid & 0xff) << (51-34);
+        needed_subid.cn63xx.ba = (base>>34) & 0xffff;
+        needed_subid.cn63xx.ba |= ((uint64_t)destid & 0xff) << (51-34);
         needed_s2m_type.s.iaow_sel = 2;
     }
 
@@ -1184,8 +1491,8 @@ uint64_t cvmx_srio_physical_map(int srio_port, cvmx_srio_write_mode_t write_op,
     /* Attach the SubID to the S2M_TYPE index */
     needed_subid.s.rtype = s2m_index & 3;
     needed_subid.s.wtype = s2m_index & 3;
-    needed_subid.s.ba |= (((uint64_t)s2m_index >> 2) & 1) << (50-34);
-    needed_subid.s.ba |= (((uint64_t)s2m_index >> 3) & 1) << (59-34);
+    needed_subid.cn63xx.ba |= (((uint64_t)s2m_index >> 2) & 1) << (50-34);
+    needed_subid.cn63xx.ba |= (((uint64_t)s2m_index >> 3) & 1) << (59-34);
 
     /* Allocate a SubID for use */
     subdid = __cvmx_srio_alloc_subid(needed_subid);
@@ -1230,10 +1537,84 @@ int cvmx_srio_physical_unmap(uint64_t physical_address, uint64_t size)
        Type[1] is mapped to the No Snoop
        Type[2] is mapped directly to bit 50 of the SLI address
        Type[3] is mapped directly to bit 59 of the SLI address */
-    read_s2m_type = ((subid.s.ba>>(50-34))&1<<2) | ((subid.s.ba>>(59-34))&1<<3);
+    read_s2m_type = ((subid.cn63xx.ba>>(50-34))&1<<2) | ((subid.cn63xx.ba>>(59-34))&1<<3);
     read_s2m_type |= subid.s.rtype;
     __cvmx_srio_free_subid(mem_index);
     __cvmx_srio_free_s2m(subid.s.port, read_s2m_type);
     return 0;
 }
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+/**
+ * fill out outbound message descriptor
+ *
+ * @param port        pip/ipd port number
+ * @param buf_ptr     pointer to a buffer pointer. the buffer pointer points
+ *                    to a chain of buffers that hold an outbound srio packet.
+ *                    the packet can take the format of (1) a pip/ipd inbound
+ *                    message or (2) an application-generated outbound message
+ * @param desc_ptr    pointer to an outbound message descriptor. should be null
+ *                    if *buf_ptr is in the format (1)
+ *
+ * @return           0 on success; negative of failure.
+ */
+int cvmx_srio_omsg_desc (uint64_t port, cvmx_buf_ptr_t *buf_ptr,
+                         cvmx_srio_tx_message_header_t *desc_ptr)
+{
+    int ret_val = -1;
+    int intf_num;
+    cvmx_helper_interface_mode_t imode;
+
+    uint64_t *desc_addr, *hdr_addr;
+    cvmx_srio_rx_message_header_t rx_msg_hdr;
+    cvmx_srio_tx_message_header_t *tx_msg_hdr_ptr;
+
+    if (buf_ptr == NULL)
+        return ret_val;
+
+    /* check if port is an srio port */
+    intf_num = cvmx_helper_get_interface_num (port);
+    imode = cvmx_helper_interface_get_mode (intf_num);
+    if (imode !=  CVMX_HELPER_INTERFACE_MODE_SRIO)
+        return ret_val;
+
+    /* app-generated outbound message. descriptor space pre-allocated */
+    if (desc_ptr != NULL)
+    {
+        desc_addr = (uint64_t *) cvmx_phys_to_ptr ((*buf_ptr).s.addr);
+        *desc_addr = *(uint64_t *) desc_ptr;
+        ret_val = 0;
+        return ret_val;
+    }
+
+    /* pip/ipd inbound message. 16-byte srio message header is present */
+    hdr_addr = (uint64_t *) cvmx_phys_to_ptr ((*buf_ptr).s.addr);
+    rx_msg_hdr.word0.u64 = *hdr_addr;
+
+    /* adjust buffer pointer to get rid of srio message header word 0 */
+    (*buf_ptr).s.addr += 8;
+    (*buf_ptr).s.size -= 8; /* last buffer or not */
+    if ((*buf_ptr).s.addr >> 7 > ((*buf_ptr).s.addr - 8) >> 7)
+        (*buf_ptr).s.back++;
+    tx_msg_hdr_ptr = (cvmx_srio_tx_message_header_t *)
+                         cvmx_phys_to_ptr ((*buf_ptr).s.addr);
+
+    /* transfer values from rx to tx */
+    tx_msg_hdr_ptr->s.prio = rx_msg_hdr.word0.s.prio;
+    tx_msg_hdr_ptr->s.tt = rx_msg_hdr.word0.s.tt; /* called id in hrm */
+    tx_msg_hdr_ptr->s.sis = rx_msg_hdr.word0.s.dis;
+    tx_msg_hdr_ptr->s.ssize = rx_msg_hdr.word0.s.ssize;
+    tx_msg_hdr_ptr->s.did = rx_msg_hdr.word0.s.sid;
+    tx_msg_hdr_ptr->s.mbox = rx_msg_hdr.word0.s.mbox;
+
+    /* other values we have to decide */
+    tx_msg_hdr_ptr->s.xmbox = 0;  /* multi-segement in general */
+    tx_msg_hdr_ptr->s.letter = 0; /* fake like traffic gen */
+    tx_msg_hdr_ptr->s.lns = 0;    /* not use sriox_omsg_ctrly[] */
+    tx_msg_hdr_ptr->s.intr = 1;   /* get status */
+
+    ret_val = 0;
+    return ret_val;
+}
+#endif
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-srio.h b/sys/contrib/octeon-sdk/cvmx-srio.h
index e53813c..062ed80 100644
--- a/sys/contrib/octeon-sdk/cvmx-srio.h
+++ b/sys/contrib/octeon-sdk/cvmx-srio.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -99,7 +99,8 @@ typedef enum
     CVMX_SRIO_DOORBELL_NONE,    /**< There wasn't an outstanding doorbell */
     CVMX_SRIO_DOORBELL_BUSY,    /**< The doorbell is still processing */
     CVMX_SRIO_DOORBELL_RETRY,   /**< The doorbell needs to be retried */
-    CVMX_SRIO_DOORBELL_ERROR    /**< The doorbell failed with an error */
+    CVMX_SRIO_DOORBELL_ERROR,   /**< The doorbell failed with an error */
+    CVMX_SRIO_DOORBELL_TMOUT    /**< The doorbell failed due to timeout */
 } cvmx_srio_doorbell_status_t;
 
 /**
@@ -114,7 +115,7 @@ typedef struct
         uint64_t u64;
         struct
         {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
             uint64_t prio   : 2; /**< The sRIO prio (priority) field in the
                                     first sRIO message segment received for the
                                     message. */
@@ -182,7 +183,7 @@ typedef struct
         uint64_t u64;
         struct
         {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
             uint64_t r      : 1; /**< When set, WORD1[R]/PKT_INST_HDR[R] selects
                                     either RAWFULL or RAWSCHED special PIP
                                     instruction form. WORD1[R] may commonly be
@@ -311,7 +312,7 @@ typedef union
     uint64_t u64;
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t prio   : 2;    /**< The sRIO prio (priority) field for all
                                     segments in the message. */
         uint64_t tt     : 1;    /**< When set, the sRIO message segments use a
@@ -370,6 +371,15 @@ typedef union
 } cvmx_srio_tx_message_header_t;
 
 /**
+ * Reset SRIO to link partner
+ *
+ * @param srio_port  SRIO port to initialize
+ *
+ * @return Zero on success
+ */
+int cvmx_srio_link_rst(int srio_port);
+
+/**
  * Initialize a SRIO port for use.
  *
  * @param srio_port SRIO port to initialize
@@ -518,6 +528,24 @@ uint64_t cvmx_srio_physical_map(int srio_port, cvmx_srio_write_mode_t write_op,
  */
 int cvmx_srio_physical_unmap(uint64_t physical_address, uint64_t size);
 
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+/**
+ * fill out outbound message descriptor
+ *
+ * @param buf_ptr     pointer to a buffer pointer. the buffer pointer points
+ *                    to a chain of buffers that hold an outbound srio packet.
+ *                    the packet can take the format of (1) a pip/ipd inbound
+ *                    message or (2) an application-generated outbound message
+ * @param desc_ptr    pointer to an outbound message descriptor. should be null
+ *                    if *buf_ptr is in the format (1)
+ *
+ * @return           0 on success; negative of failure.
+ */
+int cvmx_srio_omsg_desc (uint64_t port, cvmx_buf_ptr_t *buf_ptr,
+                         cvmx_srio_tx_message_header_t *desc_ptr);
+#endif
+
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-sriomaintx-defs.h b/sys/contrib/octeon-sdk/cvmx-sriomaintx-defs.h
index f54e851..f0e91bc 100644
--- a/sys/contrib/octeon-sdk/cvmx-sriomaintx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-sriomaintx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,15 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_SRIOMAINTX_TYPEDEFS_H__
-#define __CVMX_SRIOMAINTX_TYPEDEFS_H__
+#ifndef __CVMX_SRIOMAINTX_DEFS_H__
+#define __CVMX_SRIOMAINTX_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOMAINTX_ASMBLY_ID(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_ID(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000008ull;
 }
@@ -67,7 +68,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ASMBLY_ID(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_ASMBLY_INFO(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_INFO(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000000Cull;
 }
@@ -78,18 +80,20 @@ static inline uint64_t CVMX_SRIOMAINTX_ASMBLY_INFO(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_BAR1_IDXX(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 15)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_BAR1_IDXX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0000000000200010ull) + (((offset) & 15) + ((block_id) & 1) * 0x0ull) * 4;
+	return 0x0000000000200010ull + (((offset) & 15) + ((block_id) & 3) * 0x0ull) * 4;
 }
 #else
-#define CVMX_SRIOMAINTX_BAR1_IDXX(offset, block_id) (CVMX_ADD_IO_SEG(0x0000000000200010ull) + (((offset) & 15) + ((block_id) & 1) * 0x0ull) * 4)
+#define CVMX_SRIOMAINTX_BAR1_IDXX(offset, block_id) (0x0000000000200010ull + (((offset) & 15) + ((block_id) & 3) * 0x0ull) * 4)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOMAINTX_BELL_STATUS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_BELL_STATUS(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000200080ull;
 }
@@ -100,7 +104,8 @@ static inline uint64_t CVMX_SRIOMAINTX_BELL_STATUS(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_COMP_TAG(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_COMP_TAG(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000006Cull;
 }
@@ -111,7 +116,8 @@ static inline uint64_t CVMX_SRIOMAINTX_COMP_TAG(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_CORE_ENABLES(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_CORE_ENABLES(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000200070ull;
 }
@@ -122,7 +128,8 @@ static inline uint64_t CVMX_SRIOMAINTX_CORE_ENABLES(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_DEV_ID(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_DEV_ID(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000000ull;
 }
@@ -133,7 +140,8 @@ static inline uint64_t CVMX_SRIOMAINTX_DEV_ID(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_DEV_REV(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_DEV_REV(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000004ull;
 }
@@ -144,7 +152,8 @@ static inline uint64_t CVMX_SRIOMAINTX_DEV_REV(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_DST_OPS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_DST_OPS(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000001Cull;
 }
@@ -155,7 +164,8 @@ static inline uint64_t CVMX_SRIOMAINTX_DST_OPS(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_ERB_ATTR_CAPT(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ERB_ATTR_CAPT(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000002048ull;
 }
@@ -166,7 +176,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_ATTR_CAPT(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_DET(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_DET(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000002040ull;
 }
@@ -177,7 +188,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_DET(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000002068ull;
 }
@@ -188,7 +200,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000002044ull;
 }
@@ -199,7 +212,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000206Cull;
 }
@@ -210,7 +224,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_ERB_HDR(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ERB_HDR(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000002000ull;
 }
@@ -221,7 +236,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_HDR(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000002010ull;
 }
@@ -232,7 +248,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(unsigned long block_id
 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000002014ull;
 }
@@ -243,7 +260,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(unsigned long block_id
 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000201Cull;
 }
@@ -254,7 +272,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_DEV_ID(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000002028ull;
 }
@@ -265,7 +284,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000002018ull;
 }
@@ -276,7 +296,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(unsigned long block_id
 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_DET(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ERR_DET(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000002008ull;
 }
@@ -287,7 +308,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_DET(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_EN(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ERR_EN(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000200Cull;
 }
@@ -298,7 +320,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_EN(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000002050ull;
 }
@@ -309,7 +332,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000002054ull;
 }
@@ -320,7 +344,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000002058ull;
 }
@@ -331,7 +356,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000204Cull;
 }
@@ -342,7 +368,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000068ull;
 }
@@ -353,7 +380,8 @@ static inline uint64_t CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000102000ull;
 }
@@ -364,7 +392,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000102004ull;
 }
@@ -375,7 +404,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000107028ull;
 }
@@ -386,7 +416,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_STAT(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_IR_PD_PHY_STAT(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000010702Cull;
 }
@@ -397,7 +428,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_STAT(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000107020ull;
 }
@@ -408,7 +440,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_STAT(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_IR_PI_PHY_STAT(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000107024ull;
 }
@@ -419,7 +452,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_STAT(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_CTRL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_CTRL(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000010700Cull;
 }
@@ -430,7 +464,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_CTRL(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_DATA(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_DATA(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000107014ull;
 }
@@ -441,7 +476,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_DATA(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_STAT(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_STAT(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000107010ull;
 }
@@ -452,7 +488,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_STAT(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_CTRL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_CTRL(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000107000ull;
 }
@@ -463,7 +500,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_CTRL(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_DATA(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_DATA(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000107008ull;
 }
@@ -474,7 +512,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_DATA(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_STAT(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_STAT(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000107004ull;
 }
@@ -485,18 +524,20 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_STAT(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_LANE_X_STATUS_0(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_LANE_X_STATUS_0(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x0000000000001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x0ull) * 32;
+	return 0x0000000000001010ull + (((offset) & 3) + ((block_id) & 3) * 0x0ull) * 32;
 }
 #else
-#define CVMX_SRIOMAINTX_LANE_X_STATUS_0(offset, block_id) (CVMX_ADD_IO_SEG(0x0000000000001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x0ull) * 32)
+#define CVMX_SRIOMAINTX_LANE_X_STATUS_0(offset, block_id) (0x0000000000001010ull + (((offset) & 3) + ((block_id) & 3) * 0x0ull) * 32)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOMAINTX_LCS_BA0(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_LCS_BA0(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000058ull;
 }
@@ -507,7 +548,8 @@ static inline uint64_t CVMX_SRIOMAINTX_LCS_BA0(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_LCS_BA1(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_LCS_BA1(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000005Cull;
 }
@@ -518,7 +560,8 @@ static inline uint64_t CVMX_SRIOMAINTX_LCS_BA1(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START0(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR0_START0(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000200000ull;
 }
@@ -529,7 +572,8 @@ static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START0(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START1(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR0_START1(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000200004ull;
 }
@@ -540,7 +584,8 @@ static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START1(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START0(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR1_START0(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000200008ull;
 }
@@ -551,7 +596,8 @@ static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START0(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START1(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR1_START1(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000020000Cull;
 }
@@ -562,7 +608,8 @@ static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START1(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR2_START(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR2_START(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000200050ull;
 }
@@ -573,7 +620,8 @@ static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR2_START(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_MAC_CTRL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_MAC_CTRL(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000200068ull;
 }
@@ -584,7 +632,8 @@ static inline uint64_t CVMX_SRIOMAINTX_MAC_CTRL(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_PE_FEAT(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_PE_FEAT(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000010ull;
 }
@@ -595,7 +644,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PE_FEAT(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_PE_LLC(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_PE_LLC(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000004Cull;
 }
@@ -606,7 +656,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PE_LLC(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_PORT_0_CTL(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000015Cull;
 }
@@ -617,7 +668,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL2(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_PORT_0_CTL2(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000154ull;
 }
@@ -628,7 +680,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL2(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_PORT_0_ERR_STAT(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_PORT_0_ERR_STAT(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000158ull;
 }
@@ -639,7 +692,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_0_ERR_STAT(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_REQ(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LINK_REQ(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000140ull;
 }
@@ -650,7 +704,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_REQ(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_RESP(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LINK_RESP(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000144ull;
 }
@@ -661,7 +716,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_RESP(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000148ull;
 }
@@ -672,7 +728,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(unsigned long block_id
 static inline uint64_t CVMX_SRIOMAINTX_PORT_GEN_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_PORT_GEN_CTL(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000013Cull;
 }
@@ -683,7 +740,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_GEN_CTL(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_PORT_LT_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_PORT_LT_CTL(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000120ull;
 }
@@ -694,7 +752,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_LT_CTL(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_PORT_MBH0(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_PORT_MBH0(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000100ull;
 }
@@ -705,7 +764,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_MBH0(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_PORT_RT_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_PORT_RT_CTL(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000124ull;
 }
@@ -716,7 +776,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_RT_CTL(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_PORT_TTL_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_PORT_TTL_CTL(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000000012Cull;
 }
@@ -727,7 +788,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_TTL_CTL(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_PRI_DEV_ID(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_PRI_DEV_ID(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000060ull;
 }
@@ -738,7 +800,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PRI_DEV_ID(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_CTRL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_SEC_DEV_CTRL(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000200064ull;
 }
@@ -749,7 +812,8 @@ static inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_CTRL(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_ID(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_SEC_DEV_ID(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000200060ull;
 }
@@ -760,7 +824,8 @@ static inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_ID(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_SERIAL_LANE_HDR(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_SERIAL_LANE_HDR(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000001000ull;
 }
@@ -771,7 +836,8 @@ static inline uint64_t CVMX_SRIOMAINTX_SERIAL_LANE_HDR(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_SRC_OPS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_SRC_OPS(%lu) is invalid on this chip\n", block_id);
 	return 0x0000000000000018ull;
 }
@@ -782,7 +848,8 @@ static inline uint64_t CVMX_SRIOMAINTX_SRC_OPS(unsigned long block_id)
 static inline uint64_t CVMX_SRIOMAINTX_TX_DROP(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOMAINTX_TX_DROP(%lu) is invalid on this chip\n", block_id);
 	return 0x000000000020006Cull;
 }
@@ -800,14 +867,12 @@ static inline uint64_t CVMX_SRIOMAINTX_TX_DROP(unsigned long block_id)
  * Notes:
  * The Assembly ID register shows the Assembly ID and Vendor specified in $SRIO_ASMBLY_ID.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_ASMBLY_ID       hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_ASMBLY_ID     hclk    hrst_n
  */
-union cvmx_sriomaintx_asmbly_id
-{
+union cvmx_sriomaintx_asmbly_id {
 	uint32_t u32;
-	struct cvmx_sriomaintx_asmbly_id_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_asmbly_id_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t assy_id                      : 16; /**< Assembly Identifer */
 	uint32_t assy_ven                     : 16; /**< Assembly Vendor Identifer */
 #else
@@ -817,6 +882,7 @@ union cvmx_sriomaintx_asmbly_id
 	} s;
 	struct cvmx_sriomaintx_asmbly_id_s    cn63xx;
 	struct cvmx_sriomaintx_asmbly_id_s    cn63xxp1;
+	struct cvmx_sriomaintx_asmbly_id_s    cn66xx;
 };
 typedef union cvmx_sriomaintx_asmbly_id cvmx_sriomaintx_asmbly_id_t;
 
@@ -831,14 +897,12 @@ typedef union cvmx_sriomaintx_asmbly_id cvmx_sriomaintx_asmbly_id_t;
  * The Assembly Info register shows the Assembly Revision specified in $SRIO_ASMBLY_INFO and Extended
  *  Feature Pointer.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_ASMBLY_INFO     hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_ASMBLY_INFO   hclk    hrst_n
  */
-union cvmx_sriomaintx_asmbly_info
-{
+union cvmx_sriomaintx_asmbly_info {
 	uint32_t u32;
-	struct cvmx_sriomaintx_asmbly_info_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_asmbly_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t assy_rev                     : 16; /**< Assembly Revision */
 	uint32_t ext_fptr                     : 16; /**< Pointer to the first entry in the extended feature
                                                          list. */
@@ -849,6 +913,7 @@ union cvmx_sriomaintx_asmbly_info
 	} s;
 	struct cvmx_sriomaintx_asmbly_info_s  cn63xx;
 	struct cvmx_sriomaintx_asmbly_info_s  cn63xxp1;
+	struct cvmx_sriomaintx_asmbly_info_s  cn66xx;
 };
 typedef union cvmx_sriomaintx_asmbly_info cvmx_sriomaintx_asmbly_info_t;
 
@@ -862,21 +927,19 @@ typedef union cvmx_sriomaintx_asmbly_info cvmx_sriomaintx_asmbly_info_t;
  * Notes:
  * This register specifies the Octeon address, endian swap and cache status associated with each of
  *  the 16 BAR1 entries.  The local address bits used are based on the BARSIZE field located in the
- *  SRIOMAINT(0..1)_M2S_BAR1_START0 register.  This register is only writeable over SRIO if the
- *  SRIO(0..1)_ACC_CTRL.DENY_BAR1 bit is zero.
+ *  SRIOMAINT(0,2..3)_M2S_BAR1_START0 register.  This register is only writeable over SRIO if the
+ *  SRIO(0,2..3)_ACC_CTRL.DENY_BAR1 bit is zero.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_BAR1_IDX[0:15]  hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_BAR1_IDX[0:15]        hclk    hrst_n
  */
-union cvmx_sriomaintx_bar1_idxx
-{
+union cvmx_sriomaintx_bar1_idxx {
 	uint32_t u32;
-	struct cvmx_sriomaintx_bar1_idxx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_bar1_idxx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_30_31               : 2;
 	uint32_t la                           : 22; /**< L2/DRAM Address bits [37:16]
                                                          Not all LA[21:0] bits are used by SRIO hardware,
-                                                         depending on SRIOMAINT(0..1)_M2S_BAR1_START1[BARSIZE].
+                                                         depending on SRIOMAINT(0,2..3)_M2S_BAR1_START1[BARSIZE].
 
                                                                                  Become
                                                                                  L2/DRAM
@@ -890,12 +953,12 @@ union cvmx_sriomaintx_bar1_idxx
                                                             5        LA[21:5]    [37:21]    2MB
                                                             6        LA[21:6]    [37:22]    4MB
                                                             7        LA[21:7]    [37:23]    8MB
-                                                            8        ** not in pass 1
-                                                            9        ** not in pass 1
-                                                           10        ** not in pass 1
-                                                           11        ** not in pass 1
-                                                           12        ** not in pass 1
-                                                           13        ** not in pass 1 */
+                                                            8        LA[21:8]    [37:24]   16MB
+                                                            9        LA[21:9]    [37:25]   32MB
+                                                           10        LA[21:10]   [37:26]   64MB
+                                                           11        LA[21:11]   [37:27]  128MB
+                                                           12        LA[21:12]   [37:28]  256MB
+                                                           13        LA[21:13]   [37:29]  512MB */
 	uint32_t reserved_6_7                 : 2;
 	uint32_t es                           : 2;  /**< Endian Swap Mode.
                                                          0 = No Swap
@@ -918,6 +981,7 @@ union cvmx_sriomaintx_bar1_idxx
 	} s;
 	struct cvmx_sriomaintx_bar1_idxx_s    cn63xx;
 	struct cvmx_sriomaintx_bar1_idxx_s    cn63xxp1;
+	struct cvmx_sriomaintx_bar1_idxx_s    cn66xx;
 };
 typedef union cvmx_sriomaintx_bar1_idxx cvmx_sriomaintx_bar1_idxx_t;
 
@@ -932,14 +996,12 @@ typedef union cvmx_sriomaintx_bar1_idxx cvmx_sriomaintx_bar1_idxx_t;
  * This register displays the status of the doorbells received.  If FULL is set the SRIO device will
  *  retry incoming transactions.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_BELL_STATUS     hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_BELL_STATUS   hclk    hrst_n
  */
-union cvmx_sriomaintx_bell_status
-{
+union cvmx_sriomaintx_bell_status {
 	uint32_t u32;
-	struct cvmx_sriomaintx_bell_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_bell_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_1_31                : 31;
 	uint32_t full                         : 1;  /**< Not able to receive Doorbell Transactions */
 #else
@@ -949,6 +1011,7 @@ union cvmx_sriomaintx_bell_status
 	} s;
 	struct cvmx_sriomaintx_bell_status_s  cn63xx;
 	struct cvmx_sriomaintx_bell_status_s  cn63xxp1;
+	struct cvmx_sriomaintx_bell_status_s  cn66xx;
 };
 typedef union cvmx_sriomaintx_bell_status cvmx_sriomaintx_bell_status_t;
 
@@ -963,14 +1026,12 @@ typedef union cvmx_sriomaintx_bell_status cvmx_sriomaintx_bell_status_t;
  * This register contains a component tag value for the processing element and the value can be
  *  assigned by software when the device is initialized.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_COMP_TAG        hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_COMP_TAG      hclk    hrst_n
  */
-union cvmx_sriomaintx_comp_tag
-{
+union cvmx_sriomaintx_comp_tag {
 	uint32_t u32;
-	struct cvmx_sriomaintx_comp_tag_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_comp_tag_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t comp_tag                     : 32; /**< Component Tag for Firmware Use */
 #else
 	uint32_t comp_tag                     : 32;
@@ -978,6 +1039,7 @@ union cvmx_sriomaintx_comp_tag
 	} s;
 	struct cvmx_sriomaintx_comp_tag_s     cn63xx;
 	struct cvmx_sriomaintx_comp_tag_s     cn63xxp1;
+	struct cvmx_sriomaintx_comp_tag_s     cn66xx;
 };
 typedef union cvmx_sriomaintx_comp_tag cvmx_sriomaintx_comp_tag_t;
 
@@ -992,14 +1054,12 @@ typedef union cvmx_sriomaintx_comp_tag cvmx_sriomaintx_comp_tag_t;
  * This register displays the reset state of the Octeon Core Logic while the SRIO Link is running.
  *  The bit should be set after the software has initialized the chip to allow memory operations.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_CORE_ENABLES    hclk    hrst_n, srst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_CORE_ENABLES  hclk    hrst_n, srst_n
  */
-union cvmx_sriomaintx_core_enables
-{
+union cvmx_sriomaintx_core_enables {
 	uint32_t u32;
-	struct cvmx_sriomaintx_core_enables_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_core_enables_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_5_31                : 27;
 	uint32_t halt                         : 1;  /**< OCTEON currently in Reset
                                                          0 = All OCTEON resources are available.
@@ -1045,6 +1105,7 @@ union cvmx_sriomaintx_core_enables
 	} s;
 	struct cvmx_sriomaintx_core_enables_s cn63xx;
 	struct cvmx_sriomaintx_core_enables_s cn63xxp1;
+	struct cvmx_sriomaintx_core_enables_s cn66xx;
 };
 typedef union cvmx_sriomaintx_core_enables cvmx_sriomaintx_core_enables_t;
 
@@ -1056,16 +1117,14 @@ typedef union cvmx_sriomaintx_core_enables cvmx_sriomaintx_core_enables_t;
  * The DeviceVendor Identity field identifies the vendor that manufactured the device
  *
  * Notes:
- * This register identifies Cavium Networks and the Product ID.
+ * This register identifies Cavium Inc. and the Product ID.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_DEV_ID  hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_DEV_ID        hclk    hrst_n
  */
-union cvmx_sriomaintx_dev_id
-{
+union cvmx_sriomaintx_dev_id {
 	uint32_t u32;
-	struct cvmx_sriomaintx_dev_id_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_dev_id_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t device                       : 16; /**< Product Identity */
 	uint32_t vendor                       : 16; /**< Cavium Vendor Identity */
 #else
@@ -1075,6 +1134,7 @@ union cvmx_sriomaintx_dev_id
 	} s;
 	struct cvmx_sriomaintx_dev_id_s       cn63xx;
 	struct cvmx_sriomaintx_dev_id_s       cn63xxp1;
+	struct cvmx_sriomaintx_dev_id_s       cn66xx;
 };
 typedef union cvmx_sriomaintx_dev_id cvmx_sriomaintx_dev_id_t;
 
@@ -1088,14 +1148,12 @@ typedef union cvmx_sriomaintx_dev_id cvmx_sriomaintx_dev_id_t;
  * Notes:
  * This register identifies the chip pass and revision derived from the fuses.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_DEV_REV hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_DEV_REV       hclk    hrst_n
  */
-union cvmx_sriomaintx_dev_rev
-{
+union cvmx_sriomaintx_dev_rev {
 	uint32_t u32;
-	struct cvmx_sriomaintx_dev_rev_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_dev_rev_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_8_31                : 24;
 	uint32_t revision                     : 8;  /**< Chip Pass/Revision */
 #else
@@ -1105,6 +1163,7 @@ union cvmx_sriomaintx_dev_rev
 	} s;
 	struct cvmx_sriomaintx_dev_rev_s      cn63xx;
 	struct cvmx_sriomaintx_dev_rev_s      cn63xxp1;
+	struct cvmx_sriomaintx_dev_rev_s      cn66xx;
 };
 typedef union cvmx_sriomaintx_dev_rev cvmx_sriomaintx_dev_rev_t;
 
@@ -1117,16 +1176,14 @@ typedef union cvmx_sriomaintx_dev_rev cvmx_sriomaintx_dev_rev_t;
  *
  * Notes:
  * The logical operations supported from external devices.   The Destination OPs register shows the
- *  operations specified in the SRIO(0..1)_IP_FEATURE.OPS register.
+ *  operations specified in the SRIO(0,2..3)_IP_FEATURE.OPS register.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_DST_OPS hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_DST_OPS       hclk    hrst_n
  */
-union cvmx_sriomaintx_dst_ops
-{
+union cvmx_sriomaintx_dst_ops {
 	uint32_t u32;
-	struct cvmx_sriomaintx_dst_ops_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_dst_ops_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t gsm_read                     : 1;  /**< PE does not support Read Home operations.
                                                          This is a RO copy of SRIO*_IP_FEATURE[OPS<31>] */
 	uint32_t i_read                       : 1;  /**< PE does not support Instruction Read.
@@ -1208,6 +1265,7 @@ union cvmx_sriomaintx_dst_ops
 	} s;
 	struct cvmx_sriomaintx_dst_ops_s      cn63xx;
 	struct cvmx_sriomaintx_dst_ops_s      cn63xxp1;
+	struct cvmx_sriomaintx_dst_ops_s      cn66xx;
 };
 typedef union cvmx_sriomaintx_dst_ops cvmx_sriomaintx_dst_ops_t;
 
@@ -1229,24 +1287,23 @@ typedef union cvmx_sriomaintx_dst_ops cvmx_sriomaintx_dst_ops_t;
  *           SRIOMAINT*_ERB_PACK_CAPT_1, SRIOMAINT*_ERB_PACK_CAPT_2, and SRIOMAINT*_ERB_PACK_CAPT_3
  *       (3) Write VALID in this CSR to 0.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_ERB_ATTR_CAPT   hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_ERB_ATTR_CAPT hclk    hrst_n
  */
-union cvmx_sriomaintx_erb_attr_capt
-{
+union cvmx_sriomaintx_erb_attr_capt {
 	uint32_t u32;
-	struct cvmx_sriomaintx_erb_attr_capt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_erb_attr_capt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t inf_type                     : 3;  /**< Type of Information Logged.
                                                          000 - Packet
                                                          010 - Short Control Symbol
                                                                (use only first capture register)
+                                                         100 - Implementation Specific Error Reporting
                                                          All Others Reserved */
 	uint32_t err_type                     : 5;  /**< The encoded value of the 31 minus the bit in
-                                                         SRIOMAINT(0..1)_ERB_ERR_DET that describes the error
-                                                         captured in SRIOMAINT(0..1)_ERB_*CAPT Registers.
+                                                         SRIOMAINT(0,2..3)_ERB_ERR_DET that describes the error
+                                                         captured in SRIOMAINT(0,2..3)_ERB_*CAPT Registers.
                                                          (For example a value of 5 indicates 31-5 = bit 26) */
-	uint32_t err_info                     : 20; /**< Error Info.  (Pass 2)
+	uint32_t err_info                     : 20; /**< Error Info.
                                                          ERR_TYPE Bits   Description
                                                             0     23     TX Protocol Error
                                                                   22     RX Protocol Error
@@ -1302,9 +1359,8 @@ union cvmx_sriomaintx_erb_attr_capt
 #endif
 	} s;
 	struct cvmx_sriomaintx_erb_attr_capt_s cn63xx;
-	struct cvmx_sriomaintx_erb_attr_capt_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_erb_attr_capt_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t inf_type                     : 3;  /**< Type of Information Logged.
                                                          000 - Packet
                                                          010 - Short Control Symbol
@@ -1328,6 +1384,7 @@ union cvmx_sriomaintx_erb_attr_capt
 	uint32_t inf_type                     : 3;
 #endif
 	} cn63xxp1;
+	struct cvmx_sriomaintx_erb_attr_capt_s cn66xx;
 };
 typedef union cvmx_sriomaintx_erb_attr_capt cvmx_sriomaintx_erb_attr_capt_t;
 
@@ -1343,54 +1400,52 @@ typedef union cvmx_sriomaintx_erb_attr_capt cvmx_sriomaintx_erb_attr_capt_t;
  *  The HW will not update this register (i.e. this register is locked) while
  *  SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_ERB_ERR_DET     hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_ERB_ERR_DET   hclk    hrst_n
  */
-union cvmx_sriomaintx_erb_err_det
-{
+union cvmx_sriomaintx_erb_err_det {
 	uint32_t u32;
-	struct cvmx_sriomaintx_erb_err_det_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint32_t imp_err                      : 1;  /**< Implementation Specific Error added for Pass 2. */
+	struct cvmx_sriomaintx_erb_err_det_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t imp_err                      : 1;  /**< Implementation Specific Error. */
 	uint32_t reserved_23_30               : 8;
 	uint32_t ctl_crc                      : 1;  /**< Received a control symbol with a bad CRC value
-                                                         Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+                                                         Complete Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
 	uint32_t uns_id                       : 1;  /**< Received an acknowledge control symbol with an
                                                          unexpected ackID (packet-accepted or packet_retry)
-                                                         Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+                                                         Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
 	uint32_t nack                         : 1;  /**< Received packet-not-accepted acknowledge control
                                                          symbols.
-                                                         Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+                                                         Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
 	uint32_t out_ack                      : 1;  /**< Received packet with unexpected ackID value
-                                                         Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+                                                         Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
 	uint32_t pkt_crc                      : 1;  /**< Received a packet with a bad CRC value
-                                                         Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+                                                         Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
 	uint32_t size                         : 1;  /**< Received packet which exceeds the maximum allowed
                                                          size of 276 bytes.
-                                                         Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+                                                         Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
 	uint32_t inv_char                     : 1;  /**< Received illegal, 8B/10B error  or undefined
-                                                         codegroup within a packet.  (Pass 2)
-                                                         Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+                                                         codegroup within a packet.
+                                                         Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
 	uint32_t inv_data                     : 1;  /**< Received data codegroup or 8B/10B error within an
-                                                         IDLE sequence.  (Pass 2)
-                                                         Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+                                                         IDLE sequence.
+                                                         Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
 	uint32_t reserved_6_14                : 9;
 	uint32_t bad_ack                      : 1;  /**< Link_response received with an ackID that is not
                                                          outstanding.
-                                                         Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+                                                         Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
 	uint32_t proterr                      : 1;  /**< An unexpected packet or control symbol was
                                                          received.
-                                                         Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+                                                         Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
 	uint32_t f_toggle                     : 1;  /**< Reserved. */
 	uint32_t del_err                      : 1;  /**< Received illegal or undefined codegroup.
-                                                         (either INV_DATA or INV_CHAR) (Pass 2)
-                                                         Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+                                                         (either INV_DATA or INV_CHAR)
+                                                         Complete Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
 	uint32_t uns_ack                      : 1;  /**< An unexpected acknowledge control symbol was
                                                          received.
-                                                         Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+                                                         Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
 	uint32_t lnk_tout                     : 1;  /**< An acknowledge or link-response control symbol is
                                                          not received within the specified timeout interval
-                                                         Partial Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+                                                         Partial Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
 #else
 	uint32_t lnk_tout                     : 1;
 	uint32_t uns_ack                      : 1;
@@ -1412,9 +1467,8 @@ union cvmx_sriomaintx_erb_err_det
 #endif
 	} s;
 	struct cvmx_sriomaintx_erb_err_det_s  cn63xx;
-	struct cvmx_sriomaintx_erb_err_det_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_erb_err_det_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_23_31               : 9;
 	uint32_t ctl_crc                      : 1;  /**< Received a control symbol with a bad CRC value
                                                          Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
@@ -1465,6 +1519,7 @@ union cvmx_sriomaintx_erb_err_det
 	uint32_t reserved_23_31               : 9;
 #endif
 	} cn63xxp1;
+	struct cvmx_sriomaintx_erb_err_det_s  cn66xx;
 };
 typedef union cvmx_sriomaintx_erb_err_det cvmx_sriomaintx_erb_err_det_t;
 
@@ -1479,14 +1534,12 @@ typedef union cvmx_sriomaintx_erb_err_det cvmx_sriomaintx_erb_err_det_t;
  * The Error Rate register is used with the Error Rate Threshold register to monitor and control the
  *  reporting of transmission errors.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_ERB_ERR_RATE    hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_ERB_ERR_RATE  hclk    hrst_n
  */
-union cvmx_sriomaintx_erb_err_rate
-{
+union cvmx_sriomaintx_erb_err_rate {
 	uint32_t u32;
-	struct cvmx_sriomaintx_erb_err_rate_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_erb_err_rate_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t err_bias                     : 8;  /**< These bits provide the error rate bias value.
                                                          0x00 - do not decrement the error rate counter
                                                          0x01 - decrement every 1ms (+/-34%)
@@ -1521,6 +1574,7 @@ union cvmx_sriomaintx_erb_err_rate
 	} s;
 	struct cvmx_sriomaintx_erb_err_rate_s cn63xx;
 	struct cvmx_sriomaintx_erb_err_rate_s cn63xxp1;
+	struct cvmx_sriomaintx_erb_err_rate_s cn66xx;
 };
 typedef union cvmx_sriomaintx_erb_err_rate cvmx_sriomaintx_erb_err_rate_t;
 
@@ -1535,15 +1589,13 @@ typedef union cvmx_sriomaintx_erb_err_rate cvmx_sriomaintx_erb_err_rate_t;
  * This register contains the bits that control when an error condition is allowed to increment the
  *  error rate counter in the Error Rate Threshold Register and lock the Error Capture registers.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_ERB_ERR_RATE_EN hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_ERB_ERR_RATE_EN       hclk    hrst_n
  */
-union cvmx_sriomaintx_erb_err_rate_en
-{
+union cvmx_sriomaintx_erb_err_rate_en {
 	uint32_t u32;
-	struct cvmx_sriomaintx_erb_err_rate_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint32_t imp_err                      : 1;  /**< Enable Implementation Specific Error (Pass 2). */
+	struct cvmx_sriomaintx_erb_err_rate_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t imp_err                      : 1;  /**< Enable Implementation Specific Error. */
 	uint32_t reserved_23_30               : 8;
 	uint32_t ctl_crc                      : 1;  /**< Enable error rate counting of control symbols with
                                                          bad CRC values */
@@ -1560,10 +1612,9 @@ union cvmx_sriomaintx_erb_err_rate_en
                                                          which exceeds the maximum size of 276 bytes. */
 	uint32_t inv_char                     : 1;  /**< Enable error rate counting of received illegal
                                                          illegal, 8B/10B error or undefined codegroup
-                                                         within a packet.  (Pass 2) */
+                                                         within a packet. */
 	uint32_t inv_data                     : 1;  /**< Enable error rate counting of received data
-                                                         codegroup or 8B/10B error within IDLE sequence.
-                                                         (Pass 2) */
+                                                         codegroup or 8B/10B error within IDLE sequence. */
 	uint32_t reserved_6_14                : 9;
 	uint32_t bad_ack                      : 1;  /**< Enable error rate counting of link_responses with
                                                          an ackID that is not outstanding. */
@@ -1571,7 +1622,7 @@ union cvmx_sriomaintx_erb_err_rate_en
                                                          control symbols received. */
 	uint32_t f_toggle                     : 1;  /**< Reserved. */
 	uint32_t del_err                      : 1;  /**< Enable error rate counting of illegal or undefined
-                                                         codegroups (either INV_DATA or INV_CHAR). (Pass 2) */
+                                                         codegroups (either INV_DATA or INV_CHAR). */
 	uint32_t uns_ack                      : 1;  /**< Enable error rate counting of unexpected
                                                          acknowledge control symbols received. */
 	uint32_t lnk_tout                     : 1;  /**< Enable error rate counting of acknowledge or
@@ -1598,9 +1649,8 @@ union cvmx_sriomaintx_erb_err_rate_en
 #endif
 	} s;
 	struct cvmx_sriomaintx_erb_err_rate_en_s cn63xx;
-	struct cvmx_sriomaintx_erb_err_rate_en_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_erb_err_rate_en_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_23_31               : 9;
 	uint32_t ctl_crc                      : 1;  /**< Enable error rate counting of control symbols with
                                                          bad CRC values */
@@ -1645,6 +1695,7 @@ union cvmx_sriomaintx_erb_err_rate_en
 	uint32_t reserved_23_31               : 9;
 #endif
 	} cn63xxp1;
+	struct cvmx_sriomaintx_erb_err_rate_en_s cn66xx;
 };
 typedef union cvmx_sriomaintx_erb_err_rate_en cvmx_sriomaintx_erb_err_rate_en_t;
 
@@ -1659,14 +1710,12 @@ typedef union cvmx_sriomaintx_erb_err_rate_en cvmx_sriomaintx_erb_err_rate_en_t;
  * The Error Rate Threshold register is used to control the reporting of errors to the link status.
  *  Typically the Degraded Threshold is less than the Fail Threshold.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_ERB_ERR_RATE_THR        hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_ERB_ERR_RATE_THR      hclk    hrst_n
  */
-union cvmx_sriomaintx_erb_err_rate_thr
-{
+union cvmx_sriomaintx_erb_err_rate_thr {
 	uint32_t u32;
-	struct cvmx_sriomaintx_erb_err_rate_thr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_erb_err_rate_thr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t fail_th                      : 8;  /**< These bits provide the threshold value for
                                                          reporting an error condition due to a possibly
                                                          broken link.
@@ -1694,6 +1743,7 @@ union cvmx_sriomaintx_erb_err_rate_thr
 	} s;
 	struct cvmx_sriomaintx_erb_err_rate_thr_s cn63xx;
 	struct cvmx_sriomaintx_erb_err_rate_thr_s cn63xxp1;
+	struct cvmx_sriomaintx_erb_err_rate_thr_s cn66xx;
 };
 typedef union cvmx_sriomaintx_erb_err_rate_thr cvmx_sriomaintx_erb_err_rate_thr_t;
 
@@ -1709,14 +1759,12 @@ typedef union cvmx_sriomaintx_erb_err_rate_thr cvmx_sriomaintx_erb_err_rate_thr_
  *  the EF_ID that identifies this as the error management extensions block header. In this
  *  implementation this is the last block and therefore the EF_PTR is a NULL pointer.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_ERB_HDR hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_ERB_HDR       hclk    hrst_n
  */
-union cvmx_sriomaintx_erb_hdr
-{
+union cvmx_sriomaintx_erb_hdr {
 	uint32_t u32;
-	struct cvmx_sriomaintx_erb_hdr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_erb_hdr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ef_ptr                       : 16; /**< Pointer to the next block in the extended features
                                                          data structure. */
 	uint32_t ef_id                        : 16; /**< Single Port ID */
@@ -1727,6 +1775,7 @@ union cvmx_sriomaintx_erb_hdr
 	} s;
 	struct cvmx_sriomaintx_erb_hdr_s      cn63xx;
 	struct cvmx_sriomaintx_erb_hdr_s      cn63xxp1;
+	struct cvmx_sriomaintx_erb_hdr_s      cn66xx;
 };
 typedef union cvmx_sriomaintx_erb_hdr cvmx_sriomaintx_erb_hdr_t;
 
@@ -1739,18 +1788,16 @@ typedef union cvmx_sriomaintx_erb_hdr cvmx_sriomaintx_erb_hdr_t;
  *
  * Notes:
  * This register contains error information. It is locked when a Logical/Transport error is detected
- *  and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero. This register should be
+ *  and unlocked when the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET is written to zero. This register should be
  *  written only when error detection is disabled.  This register is only required for end point
  *  transactions of 50 or 66 bits.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_ERB_LT_ADDR_CAPT_H      hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_ERB_LT_ADDR_CAPT_H    hclk    hrst_n
  */
-union cvmx_sriomaintx_erb_lt_addr_capt_h
-{
+union cvmx_sriomaintx_erb_lt_addr_capt_h {
 	uint32_t u32;
-	struct cvmx_sriomaintx_erb_lt_addr_capt_h_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_erb_lt_addr_capt_h_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t addr                         : 32; /**< Most significant 32 bits of the address associated
                                                          with the error. Information supplied for requests
                                                          and responses if available. */
@@ -1760,6 +1807,7 @@ union cvmx_sriomaintx_erb_lt_addr_capt_h
 	} s;
 	struct cvmx_sriomaintx_erb_lt_addr_capt_h_s cn63xx;
 	struct cvmx_sriomaintx_erb_lt_addr_capt_h_s cn63xxp1;
+	struct cvmx_sriomaintx_erb_lt_addr_capt_h_s cn66xx;
 };
 typedef union cvmx_sriomaintx_erb_lt_addr_capt_h cvmx_sriomaintx_erb_lt_addr_capt_h_t;
 
@@ -1772,17 +1820,15 @@ typedef union cvmx_sriomaintx_erb_lt_addr_capt_h cvmx_sriomaintx_erb_lt_addr_cap
  *
  * Notes:
  * This register contains error information. It is locked when a Logical/Transport error is detected
- *  and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero.  This register should be
+ *  and unlocked when the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET is written to zero.  This register should be
  *  written only when error detection is disabled.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_ERB_LT_ADDR_CAPT_L      hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_ERB_LT_ADDR_CAPT_L    hclk    hrst_n
  */
-union cvmx_sriomaintx_erb_lt_addr_capt_l
-{
+union cvmx_sriomaintx_erb_lt_addr_capt_l {
 	uint32_t u32;
-	struct cvmx_sriomaintx_erb_lt_addr_capt_l_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_erb_lt_addr_capt_l_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t addr                         : 29; /**< Least significant 29 bits of the address
                                                          associated with the error.  Bits 31:24 specify the
                                                          request HOP count for Maintenance Operations.
@@ -1800,6 +1846,7 @@ union cvmx_sriomaintx_erb_lt_addr_capt_l
 	} s;
 	struct cvmx_sriomaintx_erb_lt_addr_capt_l_s cn63xx;
 	struct cvmx_sriomaintx_erb_lt_addr_capt_l_s cn63xxp1;
+	struct cvmx_sriomaintx_erb_lt_addr_capt_l_s cn66xx;
 };
 typedef union cvmx_sriomaintx_erb_lt_addr_capt_l cvmx_sriomaintx_erb_lt_addr_capt_l_t;
 
@@ -1812,17 +1859,15 @@ typedef union cvmx_sriomaintx_erb_lt_addr_capt_l cvmx_sriomaintx_erb_lt_addr_cap
  *
  * Notes:
  * This register contains error information. It is locked when a Logical/Transport error is detected
- *  and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero.  This register should be
+ *  and unlocked when the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET is written to zero.  This register should be
  *  written only when error detection is disabled.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_ERB_LT_CTRL_CAPT        hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_ERB_LT_CTRL_CAPT      hclk    hrst_n
  */
-union cvmx_sriomaintx_erb_lt_ctrl_capt
-{
+union cvmx_sriomaintx_erb_lt_ctrl_capt {
 	uint32_t u32;
-	struct cvmx_sriomaintx_erb_lt_ctrl_capt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_erb_lt_ctrl_capt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ftype                        : 4;  /**< Format Type associated with the error */
 	uint32_t ttype                        : 4;  /**< Transaction Type associated with the error
                                                          (For Messages)
@@ -1847,7 +1892,7 @@ union cvmx_sriomaintx_erb_lt_ctrl_capt
 	uint32_t wdptr                        : 1;  /**< Word Pointer associated with the error. */
 	uint32_t reserved_5_5                 : 1;
 	uint32_t capt_idx                     : 5;  /**< Capture Index. 31 - Bit set in
-                                                         SRIOMAINT(0..1)_ERB_LT_ERR_DET. */
+                                                         SRIOMAINT(0,2..3)_ERB_LT_ERR_DET. */
 #else
 	uint32_t capt_idx                     : 5;
 	uint32_t reserved_5_5                 : 1;
@@ -1862,6 +1907,7 @@ union cvmx_sriomaintx_erb_lt_ctrl_capt
 	} s;
 	struct cvmx_sriomaintx_erb_lt_ctrl_capt_s cn63xx;
 	struct cvmx_sriomaintx_erb_lt_ctrl_capt_s cn63xxp1;
+	struct cvmx_sriomaintx_erb_lt_ctrl_capt_s cn66xx;
 };
 typedef union cvmx_sriomaintx_erb_lt_ctrl_capt cvmx_sriomaintx_erb_lt_ctrl_capt_t;
 
@@ -1878,12 +1924,10 @@ typedef union cvmx_sriomaintx_erb_lt_ctrl_capt cvmx_sriomaintx_erb_lt_ctrl_capt_
  *
  * Clk_Rst:        SRIOMAINT_ERB_LT_DEV_ID hclk    hrst_n
  */
-union cvmx_sriomaintx_erb_lt_dev_id
-{
+union cvmx_sriomaintx_erb_lt_dev_id {
 	uint32_t u32;
-	struct cvmx_sriomaintx_erb_lt_dev_id_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_erb_lt_dev_id_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t id16                         : 8;  /**< This is the most significant byte of the
                                                          port-write destination deviceID (large transport
                                                          systems only)
@@ -1902,6 +1946,7 @@ union cvmx_sriomaintx_erb_lt_dev_id
 	} s;
 	struct cvmx_sriomaintx_erb_lt_dev_id_s cn63xx;
 	struct cvmx_sriomaintx_erb_lt_dev_id_s cn63xxp1;
+	struct cvmx_sriomaintx_erb_lt_dev_id_s cn66xx;
 };
 typedef union cvmx_sriomaintx_erb_lt_dev_id cvmx_sriomaintx_erb_lt_dev_id_t;
 
@@ -1914,17 +1959,15 @@ typedef union cvmx_sriomaintx_erb_lt_dev_id cvmx_sriomaintx_erb_lt_dev_id_t;
  *
  * Notes:
  * This register contains error information. It is locked when a Logical/Transport error is detected
- *  and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero.  This register should be
+ *  and unlocked when the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET is written to zero.  This register should be
  *  written only when error detection is disabled.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_ERB_LT_DEV_ID_CAPT      hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_ERB_LT_DEV_ID_CAPT    hclk    hrst_n
  */
-union cvmx_sriomaintx_erb_lt_dev_id_capt
-{
+union cvmx_sriomaintx_erb_lt_dev_id_capt {
 	uint32_t u32;
-	struct cvmx_sriomaintx_erb_lt_dev_id_capt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_erb_lt_dev_id_capt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dst_id16                     : 8;  /**< Most significant byte of the large transport
                                                          destination ID associated with the error */
 	uint32_t dst_id8                      : 8;  /**< Least significant byte of the large transport
@@ -1944,6 +1987,7 @@ union cvmx_sriomaintx_erb_lt_dev_id_capt
 	} s;
 	struct cvmx_sriomaintx_erb_lt_dev_id_capt_s cn63xx;
 	struct cvmx_sriomaintx_erb_lt_dev_id_capt_s cn63xxp1;
+	struct cvmx_sriomaintx_erb_lt_dev_id_capt_s cn66xx;
 };
 typedef union cvmx_sriomaintx_erb_lt_dev_id_capt cvmx_sriomaintx_erb_lt_dev_id_capt_t;
 
@@ -1964,14 +2008,12 @@ typedef union cvmx_sriomaintx_erb_lt_dev_id_capt cvmx_sriomaintx_erb_lt_dev_id_c
  *           SRIOMAINT*_ERB_LT_DEV_ID_CAPT, and SRIOMAINT*_ERB_LT_CTRL_CAPT
  *       (3) Write this CSR to 0.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_ERB_LT_ERR_DET  hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_ERB_LT_ERR_DET        hclk    hrst_n
  */
-union cvmx_sriomaintx_erb_lt_err_det
-{
+union cvmx_sriomaintx_erb_lt_err_det {
 	uint32_t u32;
-	struct cvmx_sriomaintx_erb_lt_err_det_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_erb_lt_err_det_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t io_err                       : 1;  /**< Received a response of ERROR for an IO Logical
                                                          Layer Request.  This includes all Maintenance and
                                                          Memory Responses not destined for the RX Soft
@@ -2026,13 +2068,13 @@ union cvmx_sriomaintx_erb_lt_err_det
                                                          soft packet fifo. */
 	uint32_t msg_tout                     : 1;  /**< An expected incoming message request has not been
                                                          received within the time-out interval specified in
-                                                         SRIOMAINT(0..1)_PORT_RT_CTL. When a MSG_TOUT occurs,
+                                                         SRIOMAINT(0,2..3)_PORT_RT_CTL. When a MSG_TOUT occurs,
                                                          SRIO (internally) terminates the inflight message
                                                          with an error. */
 	uint32_t pkt_tout                     : 1;  /**< A required response has not been received to an
                                                          outgoing memory, maintenance or message request
                                                          before the time-out interval specified in
-                                                         SRIOMAINT(0..1)_PORT_RT_CTL.  When an IO or maintenance
+                                                         SRIOMAINT(0,2..3)_PORT_RT_CTL.  When an IO or maintenance
                                                          read request operation has a PKT_TOUT, the issuing
                                                          core load or DPI DMA engine receive all ones for
                                                          the result. When an IO NWRITE_R has a PKT_TOUT,
@@ -2077,6 +2119,7 @@ union cvmx_sriomaintx_erb_lt_err_det
 	} s;
 	struct cvmx_sriomaintx_erb_lt_err_det_s cn63xx;
 	struct cvmx_sriomaintx_erb_lt_err_det_s cn63xxp1;
+	struct cvmx_sriomaintx_erb_lt_err_det_s cn66xx;
 };
 typedef union cvmx_sriomaintx_erb_lt_err_det cvmx_sriomaintx_erb_lt_err_det_t;
 
@@ -2091,14 +2134,12 @@ typedef union cvmx_sriomaintx_erb_lt_err_det cvmx_sriomaintx_erb_lt_err_det_t;
  * This register contains the bits that control if an error condition locks the Logical/Transport
  *  Layer Error Detect and Capture registers and is reported to the system host.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_ERB_LT_ERR_EN   hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_ERB_LT_ERR_EN hclk    hrst_n
  */
-union cvmx_sriomaintx_erb_lt_err_en
-{
+union cvmx_sriomaintx_erb_lt_err_en {
 	uint32_t u32;
-	struct cvmx_sriomaintx_erb_lt_err_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_erb_lt_err_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t io_err                       : 1;  /**< Enable reporting of an IO error response. Save and
                                                          lock original request transaction information in
                                                          all Logical/Transport Layer Capture CSRs. */
@@ -2159,6 +2200,7 @@ union cvmx_sriomaintx_erb_lt_err_en
 	} s;
 	struct cvmx_sriomaintx_erb_lt_err_en_s cn63xx;
 	struct cvmx_sriomaintx_erb_lt_err_en_s cn63xxp1;
+	struct cvmx_sriomaintx_erb_lt_err_en_s cn66xx;
 };
 typedef union cvmx_sriomaintx_erb_lt_err_en cvmx_sriomaintx_erb_lt_err_en_t;
 
@@ -2175,14 +2217,12 @@ typedef union cvmx_sriomaintx_erb_lt_err_en cvmx_sriomaintx_erb_lt_err_en_t;
  *  The HW will not update this register (i.e. this register is locked) while
  *  SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set.  This register should only be read while this bit is set.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_ERB_PACK_CAPT_1 hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_ERB_PACK_CAPT_1       hclk    hrst_n
  */
-union cvmx_sriomaintx_erb_pack_capt_1
-{
+union cvmx_sriomaintx_erb_pack_capt_1 {
 	uint32_t u32;
-	struct cvmx_sriomaintx_erb_pack_capt_1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_erb_pack_capt_1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t capture                      : 32; /**< Bytes 4 thru 7 of the packet header. */
 #else
 	uint32_t capture                      : 32;
@@ -2190,6 +2230,7 @@ union cvmx_sriomaintx_erb_pack_capt_1
 	} s;
 	struct cvmx_sriomaintx_erb_pack_capt_1_s cn63xx;
 	struct cvmx_sriomaintx_erb_pack_capt_1_s cn63xxp1;
+	struct cvmx_sriomaintx_erb_pack_capt_1_s cn66xx;
 };
 typedef union cvmx_sriomaintx_erb_pack_capt_1 cvmx_sriomaintx_erb_pack_capt_1_t;
 
@@ -2205,14 +2246,12 @@ typedef union cvmx_sriomaintx_erb_pack_capt_1 cvmx_sriomaintx_erb_pack_capt_1_t;
  *  The HW will not update this register (i.e. this register is locked) while
  *  SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set.  This register should only be read while this bit is set.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_ERB_PACK_CAPT_2 hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_ERB_PACK_CAPT_2       hclk    hrst_n
  */
-union cvmx_sriomaintx_erb_pack_capt_2
-{
+union cvmx_sriomaintx_erb_pack_capt_2 {
 	uint32_t u32;
-	struct cvmx_sriomaintx_erb_pack_capt_2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_erb_pack_capt_2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t capture                      : 32; /**< Bytes 8 thru 11 of the packet header. */
 #else
 	uint32_t capture                      : 32;
@@ -2220,6 +2259,7 @@ union cvmx_sriomaintx_erb_pack_capt_2
 	} s;
 	struct cvmx_sriomaintx_erb_pack_capt_2_s cn63xx;
 	struct cvmx_sriomaintx_erb_pack_capt_2_s cn63xxp1;
+	struct cvmx_sriomaintx_erb_pack_capt_2_s cn66xx;
 };
 typedef union cvmx_sriomaintx_erb_pack_capt_2 cvmx_sriomaintx_erb_pack_capt_2_t;
 
@@ -2235,14 +2275,12 @@ typedef union cvmx_sriomaintx_erb_pack_capt_2 cvmx_sriomaintx_erb_pack_capt_2_t;
  *  The HW will not update this register (i.e. this register is locked) while
  *  SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set.  This register should only be read while this bit is set.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_ERB_PACK_CAPT_3 hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_ERB_PACK_CAPT_3       hclk    hrst_n
  */
-union cvmx_sriomaintx_erb_pack_capt_3
-{
+union cvmx_sriomaintx_erb_pack_capt_3 {
 	uint32_t u32;
-	struct cvmx_sriomaintx_erb_pack_capt_3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_erb_pack_capt_3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t capture                      : 32; /**< Bytes 12 thru 15 of the packet header. */
 #else
 	uint32_t capture                      : 32;
@@ -2250,6 +2288,7 @@ union cvmx_sriomaintx_erb_pack_capt_3
 	} s;
 	struct cvmx_sriomaintx_erb_pack_capt_3_s cn63xx;
 	struct cvmx_sriomaintx_erb_pack_capt_3_s cn63xxp1;
+	struct cvmx_sriomaintx_erb_pack_capt_3_s cn66xx;
 };
 typedef union cvmx_sriomaintx_erb_pack_capt_3 cvmx_sriomaintx_erb_pack_capt_3_t;
 
@@ -2266,14 +2305,12 @@ typedef union cvmx_sriomaintx_erb_pack_capt_3 cvmx_sriomaintx_erb_pack_capt_3_t;
  *  SRIOMAINT*_ERB_ERR_DET.  The HW will not update this register (i.e. this register is locked) while
  *  SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set.  This register should only be read while this bit is set.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT       hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT     hclk    hrst_n
  */
-union cvmx_sriomaintx_erb_pack_sym_capt
-{
+union cvmx_sriomaintx_erb_pack_sym_capt {
 	uint32_t u32;
-	struct cvmx_sriomaintx_erb_pack_sym_capt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_erb_pack_sym_capt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t capture                      : 32; /**< Control Character and Control Symbol or Bytes 0 to
                                                          3 of Packet Header
                                                          The Control Symbol consists of
@@ -2290,6 +2327,7 @@ union cvmx_sriomaintx_erb_pack_sym_capt
 	} s;
 	struct cvmx_sriomaintx_erb_pack_sym_capt_s cn63xx;
 	struct cvmx_sriomaintx_erb_pack_sym_capt_s cn63xxp1;
+	struct cvmx_sriomaintx_erb_pack_sym_capt_s cn66xx;
 };
 typedef union cvmx_sriomaintx_erb_pack_sym_capt cvmx_sriomaintx_erb_pack_sym_capt_t;
 
@@ -2307,14 +2345,12 @@ typedef union cvmx_sriomaintx_erb_pack_sym_capt cvmx_sriomaintx_erb_pack_sym_cap
  *  it to see if they have responsibility for initialization.  The register can be unlocked by
  *  rewriting the current host value.  This will reset the lock and restore the value to 0xFFFF.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_HB_DEV_ID_LOCK  hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_HB_DEV_ID_LOCK        hclk    hrst_n
  */
-union cvmx_sriomaintx_hb_dev_id_lock
-{
+union cvmx_sriomaintx_hb_dev_id_lock {
 	uint32_t u32;
-	struct cvmx_sriomaintx_hb_dev_id_lock_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_hb_dev_id_lock_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_16_31               : 16;
 	uint32_t hostid                       : 16; /**< Primary 16-bit Device ID */
 #else
@@ -2324,6 +2360,7 @@ union cvmx_sriomaintx_hb_dev_id_lock
 	} s;
 	struct cvmx_sriomaintx_hb_dev_id_lock_s cn63xx;
 	struct cvmx_sriomaintx_hb_dev_id_lock_s cn63xxp1;
+	struct cvmx_sriomaintx_hb_dev_id_lock_s cn66xx;
 };
 typedef union cvmx_sriomaintx_hb_dev_id_lock cvmx_sriomaintx_hb_dev_id_lock_t;
 
@@ -2337,44 +2374,15 @@ typedef union cvmx_sriomaintx_hb_dev_id_lock cvmx_sriomaintx_hb_dev_id_lock_t;
  * Notes:
  * This register controls the operation of the SRIO Core buffer mux logic.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_IR_BUFFER_CONFIG        hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG      hclk    hrst_n
  */
-union cvmx_sriomaintx_ir_buffer_config
-{
+union cvmx_sriomaintx_ir_buffer_config {
 	uint32_t u32;
-	struct cvmx_sriomaintx_ir_buffer_config_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint32_t tx_wm0                       : 4;  /**< Transmitter Flow Control Priority 0 Threshold.
-                                                         Number of Receive Buffers available before packet
-                                                         can be scheduled for transmission.
-                                                         Maximum Value 8.
-                                                         Generally, TX_WM0 Must be > TX_WM1 to reserve
-                                                         buffers for priority 1-3 packets when transmitting
-                                                         in transmitter-controlled flow control mode.
-                                                         TX_WM0 is not used by the hardware when TX_FLOW=0
-                                                         or whenever transmitting in
-                                                         receiver-controlled flow-control mode. */
-	uint32_t tx_wm1                       : 4;  /**< Transmitter Flow Control Priority 1 Threshold.
-                                                         Number of Receive Buffers available before packet
-                                                         can be scheduled for transmission.
-                                                         Maximum Value 8.
-                                                         Generally, TX_WM1 Must be > TX_WM2 to reserve
-                                                         buffers for priority 2-3 packets when transmitting
-                                                         in transmitter-controlled flow control mode.
-                                                         TX_WM1 is not used by the hardware when TX_FLOW=0
-                                                         or whenever transmitting in
-                                                         receiver-controlled flow-control mode. */
-	uint32_t tx_wm2                       : 4;  /**< Transmitter Flow Control Priority 2 Threshold.
-                                                         Number of Receive Buffers available before packet
-                                                         can be scheduled for transmission.
-                                                         Maximum Value 8.
-                                                         Generally, TX_WM2 Must be > 0 to reserve a
-                                                         buffer for priority 3 packets when transmitting
-                                                         in transmitter-controlled flow control mode.
-                                                         TX_WM2 is not used by the hardware when TX_FLOW=0
-                                                         or whenever transmitting in
-                                                         receiver-controlled flow-control mode. */
+	struct cvmx_sriomaintx_ir_buffer_config_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t tx_wm0                       : 4;  /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */
+	uint32_t tx_wm1                       : 4;  /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */
+	uint32_t tx_wm2                       : 4;  /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */
 	uint32_t reserved_3_19                : 17;
 	uint32_t tx_flow                      : 1;  /**< Controls whether Transmitter Flow Control is
                                                          permitted on this device.
@@ -2382,14 +2390,8 @@ union cvmx_sriomaintx_ir_buffer_config
                                                            1 - Permitted
                                                          The reset value of this field is
                                                          SRIO*_IP_FEATURE[TX_FLOW]. */
-	uint32_t tx_sync                      : 1;  /**< Controls whether the synchronizers are enabled
-                                                         between the SRIO TXCLK and the Internal Clocks.
-                                                           0 - Synchronizers are enabled
-                                                           1 - Synchronizers are disabled */
-	uint32_t rx_sync                      : 1;  /**< Controls whether the synchronizers are enabled
-                                                         between the SRIO RXCLK and the Internal Clocks.
-                                                           0 - Synchronizers are enabled
-                                                           1 - Synchronizers are disabled */
+	uint32_t tx_sync                      : 1;  /**< Reserved. */
+	uint32_t rx_sync                      : 1;  /**< Reserved. */
 #else
 	uint32_t rx_sync                      : 1;
 	uint32_t tx_sync                      : 1;
@@ -2402,13 +2404,14 @@ union cvmx_sriomaintx_ir_buffer_config
 	} s;
 	struct cvmx_sriomaintx_ir_buffer_config_s cn63xx;
 	struct cvmx_sriomaintx_ir_buffer_config_s cn63xxp1;
+	struct cvmx_sriomaintx_ir_buffer_config_s cn66xx;
 };
 typedef union cvmx_sriomaintx_ir_buffer_config cvmx_sriomaintx_ir_buffer_config_t;
 
 /**
  * cvmx_sriomaint#_ir_buffer_config2
  *
- * SRIOMAINT_IR_BUFFER_CONFIG2 = SRIO Buffer Configuration 2 (Pass 2)
+ * SRIOMAINT_IR_BUFFER_CONFIG2 = SRIO Buffer Configuration 2
  *
  * Buffer Configuration 2
  *
@@ -2418,14 +2421,12 @@ typedef union cvmx_sriomaintx_ir_buffer_config cvmx_sriomaintx_ir_buffer_config_
  *  which can result in deadlocks.  Disabling a priority is not recommended and can result in system
  *  level failures.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_IR_BUFFER_CONFIG2       hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2     hclk    hrst_n
  */
-union cvmx_sriomaintx_ir_buffer_config2
-{
+union cvmx_sriomaintx_ir_buffer_config2 {
 	uint32_t u32;
-	struct cvmx_sriomaintx_ir_buffer_config2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_ir_buffer_config2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t tx_wm3                       : 4;  /**< Number of buffers free before a priority 3 packet
                                                          will be transmitted.  A value of 9 will disable
                                                          this priority. */
@@ -2462,6 +2463,7 @@ union cvmx_sriomaintx_ir_buffer_config2
 #endif
 	} s;
 	struct cvmx_sriomaintx_ir_buffer_config2_s cn63xx;
+	struct cvmx_sriomaintx_ir_buffer_config2_s cn66xx;
 };
 typedef union cvmx_sriomaintx_ir_buffer_config2 cvmx_sriomaintx_ir_buffer_config2_t;
 
@@ -2475,14 +2477,12 @@ typedef union cvmx_sriomaintx_ir_buffer_config2 cvmx_sriomaintx_ir_buffer_config
  * Notes:
  * This register can be used for testing.  The register is otherwise unused by the hardware.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_IR_PD_PHY_CTRL  hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_IR_PD_PHY_CTRL        hclk    hrst_n
  */
-union cvmx_sriomaintx_ir_pd_phy_ctrl
-{
+union cvmx_sriomaintx_ir_pd_phy_ctrl {
 	uint32_t u32;
-	struct cvmx_sriomaintx_ir_pd_phy_ctrl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_ir_pd_phy_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t pd_ctrl                      : 32; /**< Unused Register available for testing */
 #else
 	uint32_t pd_ctrl                      : 32;
@@ -2490,6 +2490,7 @@ union cvmx_sriomaintx_ir_pd_phy_ctrl
 	} s;
 	struct cvmx_sriomaintx_ir_pd_phy_ctrl_s cn63xx;
 	struct cvmx_sriomaintx_ir_pd_phy_ctrl_s cn63xxp1;
+	struct cvmx_sriomaintx_ir_pd_phy_ctrl_s cn66xx;
 };
 typedef union cvmx_sriomaintx_ir_pd_phy_ctrl cvmx_sriomaintx_ir_pd_phy_ctrl_t;
 
@@ -2504,14 +2505,12 @@ typedef union cvmx_sriomaintx_ir_pd_phy_ctrl cvmx_sriomaintx_ir_pd_phy_ctrl_t;
  * This register is used to monitor PHY status on each lane.  They are documented here to assist in
  *  debugging only.  The lane numbers take into account the lane swap pin.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_IR_PD_PHY_STAT  hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_IR_PD_PHY_STAT        hclk    hrst_n
  */
-union cvmx_sriomaintx_ir_pd_phy_stat
-{
+union cvmx_sriomaintx_ir_pd_phy_stat {
 	uint32_t u32;
-	struct cvmx_sriomaintx_ir_pd_phy_stat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_ir_pd_phy_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_16_31               : 16;
 	uint32_t ln3_rx                       : 3;  /**< Phy Lane 3 RX Status
                                                          0XX = Normal Operation
@@ -2563,6 +2562,7 @@ union cvmx_sriomaintx_ir_pd_phy_stat
 	} s;
 	struct cvmx_sriomaintx_ir_pd_phy_stat_s cn63xx;
 	struct cvmx_sriomaintx_ir_pd_phy_stat_s cn63xxp1;
+	struct cvmx_sriomaintx_ir_pd_phy_stat_s cn66xx;
 };
 typedef union cvmx_sriomaintx_ir_pd_phy_stat cvmx_sriomaintx_ir_pd_phy_stat_t;
 
@@ -2577,14 +2577,12 @@ typedef union cvmx_sriomaintx_ir_pd_phy_stat cvmx_sriomaintx_ir_pd_phy_stat_t;
  * This register is used to control platform independent operating modes of the transceivers. These
  *  control bits are uniform across all platforms.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_IR_PI_PHY_CTRL  hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_IR_PI_PHY_CTRL        hclk    hrst_n
  */
-union cvmx_sriomaintx_ir_pi_phy_ctrl
-{
+union cvmx_sriomaintx_ir_pi_phy_ctrl {
 	uint32_t u32;
-	struct cvmx_sriomaintx_ir_pi_phy_ctrl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_ir_pi_phy_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t tx_reset                     : 1;  /**< Outgoing PHY Logic Reset.  0=Reset, 1=Normal Op */
 	uint32_t rx_reset                     : 1;  /**< Incoming PHY Logic Reset.  0=Reset, 1=Normal Op */
 	uint32_t reserved_29_29               : 1;
@@ -2606,6 +2604,7 @@ union cvmx_sriomaintx_ir_pi_phy_ctrl
 	} s;
 	struct cvmx_sriomaintx_ir_pi_phy_ctrl_s cn63xx;
 	struct cvmx_sriomaintx_ir_pi_phy_ctrl_s cn63xxp1;
+	struct cvmx_sriomaintx_ir_pi_phy_ctrl_s cn66xx;
 };
 typedef union cvmx_sriomaintx_ir_pi_phy_ctrl cvmx_sriomaintx_ir_pi_phy_ctrl_t;
 
@@ -2618,19 +2617,17 @@ typedef union cvmx_sriomaintx_ir_pi_phy_ctrl cvmx_sriomaintx_ir_pi_phy_ctrl_t;
  *
  * Notes:
  * This register displays the status of the link initialization state machine.  Changes to this state
- *  cause the SRIO(0..1)_INT_REG.LINK_UP or SRIO(0..1)_INT_REG.LINK_DOWN interrupts.
+ *  cause the SRIO(0,2..3)_INT_REG.LINK_UP or SRIO(0,2..3)_INT_REG.LINK_DOWN interrupts.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_IR_PI_PHY_STAT  hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_IR_PI_PHY_STAT        hclk    hrst_n
  */
-union cvmx_sriomaintx_ir_pi_phy_stat
-{
+union cvmx_sriomaintx_ir_pi_phy_stat {
 	uint32_t u32;
-	struct cvmx_sriomaintx_ir_pi_phy_stat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_ir_pi_phy_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_12_31               : 20;
-	uint32_t tx_rdy                       : 1;  /**< Minimum number of Status Transmitted  (Pass 2) */
-	uint32_t rx_rdy                       : 1;  /**< Minimum number of Good Status Received (Pass 2) */
+	uint32_t tx_rdy                       : 1;  /**< Minimum number of Status Transmitted */
+	uint32_t rx_rdy                       : 1;  /**< Minimum number of Good Status Received */
 	uint32_t init_sm                      : 10; /**< Initialization State Machine
                                                          001 - Silent
                                                          002 - Seek
@@ -2651,9 +2648,8 @@ union cvmx_sriomaintx_ir_pi_phy_stat
 #endif
 	} s;
 	struct cvmx_sriomaintx_ir_pi_phy_stat_s cn63xx;
-	struct cvmx_sriomaintx_ir_pi_phy_stat_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_ir_pi_phy_stat_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_10_31               : 22;
 	uint32_t init_sm                      : 10; /**< Initialization State Machine
                                                          001 - Silent
@@ -2672,6 +2668,7 @@ union cvmx_sriomaintx_ir_pi_phy_stat
 	uint32_t reserved_10_31               : 22;
 #endif
 	} cn63xxp1;
+	struct cvmx_sriomaintx_ir_pi_phy_stat_s cn66xx;
 };
 typedef union cvmx_sriomaintx_ir_pi_phy_stat cvmx_sriomaintx_ir_pi_phy_stat_t;
 
@@ -2686,18 +2683,17 @@ typedef union cvmx_sriomaintx_ir_pi_phy_stat cvmx_sriomaintx_ir_pi_phy_stat_t;
  * This register is used to configure events generated by the reception of packets using the soft
  * packet FIFO.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_IR_SP_RX_CTRL   hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_IR_SP_RX_CTRL hclk    hrst_n
  */
-union cvmx_sriomaintx_ir_sp_rx_ctrl
-{
+union cvmx_sriomaintx_ir_sp_rx_ctrl {
 	uint32_t u32;
-	struct cvmx_sriomaintx_ir_sp_rx_ctrl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_ir_sp_rx_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_1_31                : 31;
 	uint32_t overwrt                      : 1;  /**< When clear, SRIO drops received packets that should
                                                          enter the soft packet FIFO when the FIFO is full.
-                                                         When set, SRIO
+                                                         In this case, SRIO also increments
+                                                         SRIOMAINT(0,2..3)_IR_SP_RX_STAT.DROP_CNT. When set, SRIO
                                                          stalls received packets that should enter the soft
                                                          packet FIFO when the FIFO is full. SRIO may stop
                                                          receiving any packets in this stall case if
@@ -2710,6 +2706,7 @@ union cvmx_sriomaintx_ir_sp_rx_ctrl
 	} s;
 	struct cvmx_sriomaintx_ir_sp_rx_ctrl_s cn63xx;
 	struct cvmx_sriomaintx_ir_sp_rx_ctrl_s cn63xxp1;
+	struct cvmx_sriomaintx_ir_sp_rx_ctrl_s cn66xx;
 };
 typedef union cvmx_sriomaintx_ir_sp_rx_ctrl cvmx_sriomaintx_ir_sp_rx_ctrl_t;
 
@@ -2730,14 +2727,12 @@ typedef union cvmx_sriomaintx_ir_sp_rx_ctrl cvmx_sriomaintx_ir_sp_rx_ctrl_t;
  *  instead of the expected 83.  In cases over 80 bytes the CRC at 80 bytes is removed but the
  *  trailing CRC and Pad (if necessary) are present.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_IR_SP_RX_DATA   hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_IR_SP_RX_DATA hclk    hrst_n
  */
-union cvmx_sriomaintx_ir_sp_rx_data
-{
+union cvmx_sriomaintx_ir_sp_rx_data {
 	uint32_t u32;
-	struct cvmx_sriomaintx_ir_sp_rx_data_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_ir_sp_rx_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t pkt_data                     : 32; /**< This register is used to read packet data from the
                                                          RX FIFO. */
 #else
@@ -2746,6 +2741,7 @@ union cvmx_sriomaintx_ir_sp_rx_data
 	} s;
 	struct cvmx_sriomaintx_ir_sp_rx_data_s cn63xx;
 	struct cvmx_sriomaintx_ir_sp_rx_data_s cn63xxp1;
+	struct cvmx_sriomaintx_ir_sp_rx_data_s cn66xx;
 };
 typedef union cvmx_sriomaintx_ir_sp_rx_data cvmx_sriomaintx_ir_sp_rx_data_t;
 
@@ -2766,24 +2762,20 @@ typedef union cvmx_sriomaintx_ir_sp_rx_data cvmx_sriomaintx_ir_sp_rx_data_t;
  *  This procedure could lead to situations where SOFT_RX will be set even though there are currently
  *  no packets - the SW interrupt handler would need to properly handle this case
  *
- * Clk_Rst:        SRIOMAINT(0..1)_IR_SP_RX_STAT   hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_IR_SP_RX_STAT hclk    hrst_n
  */
-union cvmx_sriomaintx_ir_sp_rx_stat
-{
+union cvmx_sriomaintx_ir_sp_rx_stat {
 	uint32_t u32;
-	struct cvmx_sriomaintx_ir_sp_rx_stat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_ir_sp_rx_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t octets                       : 16; /**< This field shows how many octets are remaining
                                                          in the current packet in the RX FIFO. */
 	uint32_t buffers                      : 4;  /**< This field indicates how many complete packets are
                                                          stored in the Rx FIFO. */
 	uint32_t drop_cnt                     : 7;  /**< Number of Packets Received when the RX FIFO was
-                                                         full and then discarded.
-                                                         This field always reads zero in Pass 1 */
+                                                         full and then discarded. */
 	uint32_t full                         : 1;  /**< This bit is set when the value of Buffers Filled
-                                                         equals the number of available reception buffers.
-                                                         This bit always reads zero in Pass 1 */
+                                                         equals the number of available reception buffers. */
 	uint32_t fifo_st                      : 4;  /**< These bits display the state of the state machine
                                                          that controls loading of packet data into the RX
                                                          FIFO. The enumeration of states are as follows:
@@ -2800,9 +2792,8 @@ union cvmx_sriomaintx_ir_sp_rx_stat
 #endif
 	} s;
 	struct cvmx_sriomaintx_ir_sp_rx_stat_s cn63xx;
-	struct cvmx_sriomaintx_ir_sp_rx_stat_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_ir_sp_rx_stat_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t octets                       : 16; /**< This field shows how many octets are remaining
                                                          in the current packet in the RX FIFO. */
 	uint32_t buffers                      : 4;  /**< This field indicates how many complete packets are
@@ -2826,6 +2817,7 @@ union cvmx_sriomaintx_ir_sp_rx_stat
 	uint32_t octets                       : 16;
 #endif
 	} cn63xxp1;
+	struct cvmx_sriomaintx_ir_sp_rx_stat_s cn66xx;
 };
 typedef union cvmx_sriomaintx_ir_sp_rx_stat cvmx_sriomaintx_ir_sp_rx_stat_t;
 
@@ -2842,17 +2834,15 @@ typedef union cvmx_sriomaintx_ir_sp_rx_stat cvmx_sriomaintx_ir_sp_rx_stat_t;
  *
  * Clk_Rst:        SRIOMAINT_IR_SP_TX_CTRL hclk    hrst_n
  */
-union cvmx_sriomaintx_ir_sp_tx_ctrl
-{
+union cvmx_sriomaintx_ir_sp_tx_ctrl {
 	uint32_t u32;
-	struct cvmx_sriomaintx_ir_sp_tx_ctrl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_ir_sp_tx_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t octets                       : 16; /**< Writing a non-zero value (N) to this field arms
                                                          the packet FIFO for packet transmission. The FIFO
                                                          control logic will transmit the next N bytes
                                                          written 4-bytes at a time to the
-                                                         SRIOMAINT(0..1)_IR_SP_TX_DATA Register and create a
+                                                         SRIOMAINT(0,2..3)_IR_SP_TX_DATA Register and create a
                                                          single RapidIO packet. */
 	uint32_t reserved_0_15                : 16;
 #else
@@ -2862,6 +2852,7 @@ union cvmx_sriomaintx_ir_sp_tx_ctrl
 	} s;
 	struct cvmx_sriomaintx_ir_sp_tx_ctrl_s cn63xx;
 	struct cvmx_sriomaintx_ir_sp_tx_ctrl_s cn63xxp1;
+	struct cvmx_sriomaintx_ir_sp_tx_ctrl_s cn66xx;
 };
 typedef union cvmx_sriomaintx_ir_sp_tx_ctrl cvmx_sriomaintx_ir_sp_tx_ctrl_t;
 
@@ -2878,16 +2869,14 @@ typedef union cvmx_sriomaintx_ir_sp_tx_ctrl cvmx_sriomaintx_ir_sp_tx_ctrl_t;
  * generate a response.  Bits [7:6] of the 8 bit TID must be set for all Soft Packet FIFO generated
  * packets.  TID values of 0x00 - 0xBF are reserved for hardware generated Tags.  The remainer of the
  * TID[5:0] must be unique for each packet in flight and cannot be reused until a response is received
- * in the SRIOMAINT(0..1)_IR_SP_RX_DATA register.
+ * in the SRIOMAINT(0,2..3)_IR_SP_RX_DATA register.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_IR_SP_TX_DATA   hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_IR_SP_TX_DATA hclk    hrst_n
  */
-union cvmx_sriomaintx_ir_sp_tx_data
-{
+union cvmx_sriomaintx_ir_sp_tx_data {
 	uint32_t u32;
-	struct cvmx_sriomaintx_ir_sp_tx_data_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_ir_sp_tx_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t pkt_data                     : 32; /**< This register is used to write packet data to the
                                                          Tx FIFO. Reads of this register will return zero. */
 #else
@@ -2896,6 +2885,7 @@ union cvmx_sriomaintx_ir_sp_tx_data
 	} s;
 	struct cvmx_sriomaintx_ir_sp_tx_data_s cn63xx;
 	struct cvmx_sriomaintx_ir_sp_tx_data_s cn63xxp1;
+	struct cvmx_sriomaintx_ir_sp_tx_data_s cn66xx;
 };
 typedef union cvmx_sriomaintx_ir_sp_tx_data cvmx_sriomaintx_ir_sp_tx_data_t;
 
@@ -2909,14 +2899,12 @@ typedef union cvmx_sriomaintx_ir_sp_tx_data cvmx_sriomaintx_ir_sp_tx_data_t;
  * Notes:
  * This register is used to monitor the transmission of packets using the soft packet FIFO.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_IR_SP_TX_STAT   hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_IR_SP_TX_STAT hclk    hrst_n
  */
-union cvmx_sriomaintx_ir_sp_tx_stat
-{
+union cvmx_sriomaintx_ir_sp_tx_stat {
 	uint32_t u32;
-	struct cvmx_sriomaintx_ir_sp_tx_stat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_ir_sp_tx_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t octets                       : 16; /**< This field shows how many octets are still to be
                                                          loaded in the current packet. */
 	uint32_t buffers                      : 4;  /**< This field indicates how many complete packets are
@@ -2943,6 +2931,7 @@ union cvmx_sriomaintx_ir_sp_tx_stat
 	} s;
 	struct cvmx_sriomaintx_ir_sp_tx_stat_s cn63xx;
 	struct cvmx_sriomaintx_ir_sp_tx_stat_s cn63xxp1;
+	struct cvmx_sriomaintx_ir_sp_tx_stat_s cn66xx;
 };
 typedef union cvmx_sriomaintx_ir_sp_tx_stat cvmx_sriomaintx_ir_sp_tx_stat_t;
 
@@ -2956,14 +2945,12 @@ typedef union cvmx_sriomaintx_ir_sp_tx_stat cvmx_sriomaintx_ir_sp_tx_stat_t;
  * Notes:
  * This register contains status information about the local lane transceiver.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_LANE_[0:3]_STATUS_0     hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_LANE_[0:3]_STATUS_0   hclk    hrst_n
  */
-union cvmx_sriomaintx_lane_x_status_0
-{
+union cvmx_sriomaintx_lane_x_status_0 {
 	uint32_t u32;
-	struct cvmx_sriomaintx_lane_x_status_0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_lane_x_status_0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t port                         : 8;  /**< The number of the port within the device to which
                                                          the lane is assigned. */
 	uint32_t lane                         : 4;  /**< Lane Number within the port. */
@@ -3022,6 +3009,7 @@ union cvmx_sriomaintx_lane_x_status_0
 	} s;
 	struct cvmx_sriomaintx_lane_x_status_0_s cn63xx;
 	struct cvmx_sriomaintx_lane_x_status_0_s cn63xxp1;
+	struct cvmx_sriomaintx_lane_x_status_0_s cn66xx;
 };
 typedef union cvmx_sriomaintx_lane_x_status_0 cvmx_sriomaintx_lane_x_status_0_t;
 
@@ -3038,17 +3026,15 @@ typedef union cvmx_sriomaintx_lane_x_status_0 cvmx_sriomaintx_lane_x_status_0_t;
  *  not supplied in the transfer are considered zero.  For example, SRIO Address 65:35 must be set to
  *  zero to match in a 34-bit access.  SRIO Address 65:50 must be set to zero to match in a 50-bit
  *  access.  This coding allows the Maintenance Bar window to appear in specific address spaces. The
- *  remaining bits are located in SRIOMAINT(0..1)_LCS_BA1. This SRIO maintenance BAR is effectively
+ *  remaining bits are located in SRIOMAINT(0,2..3)_LCS_BA1. This SRIO maintenance BAR is effectively
  *  disabled when LCSBA[30] is set with 34 or 50-bit addressing.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_LCS_BA0 hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_LCS_BA0       hclk    hrst_n
  */
-union cvmx_sriomaintx_lcs_ba0
-{
+union cvmx_sriomaintx_lcs_ba0 {
 	uint32_t u32;
-	struct cvmx_sriomaintx_lcs_ba0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_lcs_ba0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_31_31               : 1;
 	uint32_t lcsba                        : 31; /**< SRIO Address 65:35 */
 #else
@@ -3058,6 +3044,7 @@ union cvmx_sriomaintx_lcs_ba0
 	} s;
 	struct cvmx_sriomaintx_lcs_ba0_s      cn63xx;
 	struct cvmx_sriomaintx_lcs_ba0_s      cn63xxp1;
+	struct cvmx_sriomaintx_lcs_ba0_s      cn66xx;
 };
 typedef union cvmx_sriomaintx_lcs_ba0 cvmx_sriomaintx_lcs_ba0_t;
 
@@ -3076,16 +3063,14 @@ typedef union cvmx_sriomaintx_lcs_ba0 cvmx_sriomaintx_lcs_ba0_t;
  *  This coding allows the Maintenance Bar window to appear in specific address spaces. Accesses
  *  through this BAR are limited to single word (32-bit) aligned transfers of one to four bytes.
  *  Accesses which violate this rule will return an error response if possible and be otherwise
- *  ignored.  The remaining bits are located in SRIOMAINT(0..1)_LCS_BA0.
+ *  ignored.  The remaining bits are located in SRIOMAINT(0,2..3)_LCS_BA0.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_LCS_BA1 hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_LCS_BA1       hclk    hrst_n
  */
-union cvmx_sriomaintx_lcs_ba1
-{
+union cvmx_sriomaintx_lcs_ba1 {
 	uint32_t u32;
-	struct cvmx_sriomaintx_lcs_ba1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_lcs_ba1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t lcsba                        : 11; /**< SRIO Address 34:24 */
 	uint32_t reserved_0_20                : 21;
 #else
@@ -3095,6 +3080,7 @@ union cvmx_sriomaintx_lcs_ba1
 	} s;
 	struct cvmx_sriomaintx_lcs_ba1_s      cn63xx;
 	struct cvmx_sriomaintx_lcs_ba1_s      cn63xxp1;
+	struct cvmx_sriomaintx_lcs_ba1_s      cn66xx;
 };
 typedef union cvmx_sriomaintx_lcs_ba1 cvmx_sriomaintx_lcs_ba1_t;
 
@@ -3107,17 +3093,15 @@ typedef union cvmx_sriomaintx_lcs_ba1 cvmx_sriomaintx_lcs_ba1_t;
  *
  * Notes:
  * This register specifies the 50-bit and 66-bit SRIO Address mapped to the BAR0 Space.  See
- *  SRIOMAINT(0..1)_M2S_BAR0_START1 for more details. This register is only writeable over SRIO if the
- *  SRIO(0..1)_ACC_CTRL.DENY_BAR0 bit is zero.
+ *  SRIOMAINT(0,2..3)_M2S_BAR0_START1 for more details. This register is only writeable over SRIO if the
+ *  SRIO(0,2..3)_ACC_CTRL.DENY_BAR0 bit is zero.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_M2S_BAR0_START0 hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_M2S_BAR0_START0       hclk    hrst_n
  */
-union cvmx_sriomaintx_m2s_bar0_start0
-{
+union cvmx_sriomaintx_m2s_bar0_start0 {
 	uint32_t u32;
-	struct cvmx_sriomaintx_m2s_bar0_start0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_m2s_bar0_start0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t addr64                       : 16; /**< SRIO Address 63:48 */
 	uint32_t addr48                       : 16; /**< SRIO Address 47:32 */
 #else
@@ -3127,6 +3111,7 @@ union cvmx_sriomaintx_m2s_bar0_start0
 	} s;
 	struct cvmx_sriomaintx_m2s_bar0_start0_s cn63xx;
 	struct cvmx_sriomaintx_m2s_bar0_start0_s cn63xxp1;
+	struct cvmx_sriomaintx_m2s_bar0_start0_s cn66xx;
 };
 typedef union cvmx_sriomaintx_m2s_bar0_start0 cvmx_sriomaintx_m2s_bar0_start0_t;
 
@@ -3147,17 +3132,16 @@ typedef union cvmx_sriomaintx_m2s_bar0_start0 cvmx_sriomaintx_m2s_bar0_start0_t;
  *  transactions require matches of all valid address field bits.  Reads and  Writes through Bar0
  *  have a size limit of 8 bytes and cannot cross a 64-bit boundry.  All accesses with sizes greater
  *  than this limit will be ignored and return an error on any SRIO responses.  Note: ADDR48 and
- *  ADDR64 fields are located in SRIOMAINT(0..1)_M2S_BAR0_START0.  This register is only writeable over
- *  SRIO if the SRIO(0..1)_ACC_CTRL.DENY_BAR0 bit is zero.
+ *  ADDR64 fields are located in SRIOMAINT(0,2..3)_M2S_BAR0_START0.  The ADDR32/66 fields of this register
+ *  are writeable over SRIO if the SRIO(0,2..3)_ACC_CTRL.DENY_ADR0 bit is zero.  The ENABLE field is
+ *  writeable over SRIO if the SRIO(0,2..3)_ACC_CTRL.DENY_BAR0 bit is zero.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_M2S_BAR0_START1 hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_M2S_BAR0_START1       hclk    hrst_n
  */
-union cvmx_sriomaintx_m2s_bar0_start1
-{
+union cvmx_sriomaintx_m2s_bar0_start1 {
 	uint32_t u32;
-	struct cvmx_sriomaintx_m2s_bar0_start1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_m2s_bar0_start1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t addr32                       : 18; /**< SRIO Address 31:14 */
 	uint32_t reserved_3_13                : 11;
 	uint32_t addr66                       : 2;  /**< SRIO Address 65:64 */
@@ -3171,6 +3155,7 @@ union cvmx_sriomaintx_m2s_bar0_start1
 	} s;
 	struct cvmx_sriomaintx_m2s_bar0_start1_s cn63xx;
 	struct cvmx_sriomaintx_m2s_bar0_start1_s cn63xxp1;
+	struct cvmx_sriomaintx_m2s_bar0_start1_s cn66xx;
 };
 typedef union cvmx_sriomaintx_m2s_bar0_start1 cvmx_sriomaintx_m2s_bar0_start1_t;
 
@@ -3183,19 +3168,21 @@ typedef union cvmx_sriomaintx_m2s_bar0_start1 cvmx_sriomaintx_m2s_bar0_start1_t;
  *
  * Notes:
  * This register specifies the 50-bit and 66-bit SRIO Address mapped to the BAR1 Space.  See
- *  SRIOMAINT(0..1)_M2S_BAR1_START1 for more details.  This register is only writeable over SRIO if the
- *  SRIO(0..1)_ACC_CTRL.DENY_BAR1 bit is zero.
+ *  SRIOMAINT(0,2..3)_M2S_BAR1_START1 for more details.  This register is only writeable over SRIO if the
+ *  SRIO(0,2..3)_ACC_CTRL.DENY_ADR1 bit is zero.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_M2S_BAR1_START0 hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_M2S_BAR1_START0       hclk    hrst_n
  */
-union cvmx_sriomaintx_m2s_bar1_start0
-{
+union cvmx_sriomaintx_m2s_bar1_start0 {
 	uint32_t u32;
-	struct cvmx_sriomaintx_m2s_bar1_start0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_m2s_bar1_start0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t addr64                       : 16; /**< SRIO Address 63:48 */
-	uint32_t addr48                       : 16; /**< SRIO Address 47:32 */
+	uint32_t addr48                       : 16; /**< SRIO Address 47:32
+                                                         The SRIO hardware does not use the low order
+                                                         one or two bits of this field when BARSIZE is 12
+                                                         or 13, respectively.
+                                                         (BARSIZE is SRIOMAINT(0,2..3)_M2S_BAR1_START1[BARSIZE].) */
 #else
 	uint32_t addr48                       : 16;
 	uint32_t addr64                       : 16;
@@ -3203,6 +3190,7 @@ union cvmx_sriomaintx_m2s_bar1_start0
 	} s;
 	struct cvmx_sriomaintx_m2s_bar1_start0_s cn63xx;
 	struct cvmx_sriomaintx_m2s_bar1_start0_s cn63xxp1;
+	struct cvmx_sriomaintx_m2s_bar1_start0_s cn66xx;
 };
 typedef union cvmx_sriomaintx_m2s_bar1_start0 cvmx_sriomaintx_m2s_bar1_start0_t;
 
@@ -3218,24 +3206,25 @@ typedef union cvmx_sriomaintx_m2s_bar1_start0 cvmx_sriomaintx_m2s_bar1_start0_t;
  *  already been mapped to SRIO Maintenance Space through the SRIOMAINT_LCS_BA[1:0] registers and the
  *  address bits do not match enabled BAR0 addresses and if ENABLE is set and the addresses match the
  *  BAR1 addresses then SRIO Memory transactions will map to Octeon Memory Space specified by
- *  SRIOMAINT(0..1)_BAR1_IDX[31:0] registers.  The BARSIZE field determines the size of BAR1, the entry
+ *  SRIOMAINT(0,2..3)_BAR1_IDX[31:0] registers.  The BARSIZE field determines the size of BAR1, the entry
  *  select bits, and the size of each entry. A 34-bit address matches BAR1 when it matches
  *  SRIO_Address[33:20+BARSIZE] while all the other bits in ADDR48, ADDR64 and ADDR66 are zero.
  *  A 50-bit address matches BAR1 when it matches SRIO_Address[49:20+BARSIZE] while all the
  *  other bits of ADDR64 and ADDR66 are zero.  A 66-bit address matches BAR1 when all of
  *  SRIO_Address[65:20+BARSIZE] match all corresponding address CSR field bits.  Note: ADDR48 and
- *  ADDR64 fields are located in SRIOMAINT(0..1)_M2S_BAR1_START0. This register is only writeable from SRIO
- *  if the SRIO(0..1)_ACC_CTRL.DENY_BAR1 bit is zero.
+ *  ADDR64 fields are located in SRIOMAINT(0,2..3)_M2S_BAR1_START0. The ADDR32/66 fields of this register
+ *  are writeable over SRIO if the SRIO(0,2..3)_ACC_CTRL.DENY_ADR1 bit is zero.  The remaining fields are
+ *  writeable over SRIO if the SRIO(0,2..3)_ACC_CTRL.DENY_BAR1 bit is zero.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_M2S_BAR1_START1 hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_M2S_BAR1_START1       hclk    hrst_n
  */
-union cvmx_sriomaintx_m2s_bar1_start1
-{
+union cvmx_sriomaintx_m2s_bar1_start1 {
 	uint32_t u32;
-	struct cvmx_sriomaintx_m2s_bar1_start1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_m2s_bar1_start1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t addr32                       : 12; /**< SRIO Address 31:20
+                                                         This field is not used by the SRIO hardware for
+                                                         BARSIZE values 12 or 13.
                                                          With BARSIZE < 12, the upper 12-BARSIZE
                                                          bits of this field are used, and the lower BARSIZE
                                                          bits of this field are unused by the SRIO hardware. */
@@ -3255,21 +3244,16 @@ union cvmx_sriomaintx_m2s_bar1_start1
                                                           5      32MB    65:25   24:21   20:0      2MB
                                                           6      64MB    65:26   25:22   21:0      4MB
                                                           7     128MB    65:27   26:23   22:0      8MB
-                                                          8     256MB  ** not in pass 1
-                                                          9     512MB  ** not in pass 1
-                                                         10       1GB  ** not in pass 1
-                                                         11       2GB  ** not in pass 1
-                                                         12       4GB  ** not in pass 1
-                                                         13       8GB  ** not in pass 1
+                                                          8     256MB    65:28   27:24   23:0     16MB
+                                                          9     512MB    65:29   28:25   24:0     32MB
+                                                         10    1024MB    65:30   29:26   25:0     64MB
+                                                         11    2048MB    65:31   30:27   26:0    128MB
+                                                         12    4096MB    65:32   31:28   27:0    256MB
+                                                         13    8192MB    65:33   32:29   28:0    512MB
 
                                                          *The SRIO Transaction Address
                                                          The entry select bits is the X that  select an
-                                                         SRIOMAINT(0..1)_BAR1_IDXX entry.
-
-                                                         In O63 pass 2, BARSIZE is 4 bits (6:3 in this
-                                                         CSR), and BARSIZE values 8-13 are implemented,
-                                                         providing a total possible BAR1 size range from
-                                                         1MB up to 8GB. */
+                                                         SRIOMAINT(0,2..3)_BAR1_IDXX entry. */
 	uint32_t addr66                       : 2;  /**< SRIO Address 65:64 */
 	uint32_t enable                       : 1;  /**< Enable BAR1 Access */
 #else
@@ -3281,9 +3265,8 @@ union cvmx_sriomaintx_m2s_bar1_start1
 #endif
 	} s;
 	struct cvmx_sriomaintx_m2s_bar1_start1_s cn63xx;
-	struct cvmx_sriomaintx_m2s_bar1_start1_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_m2s_bar1_start1_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t addr32                       : 12; /**< SRIO Address 31:20
                                                          With BARSIZE < 12, the upper 12-BARSIZE
                                                          bits of this field are used, and the lower BARSIZE
@@ -3329,6 +3312,7 @@ union cvmx_sriomaintx_m2s_bar1_start1
 	uint32_t addr32                       : 12;
 #endif
 	} cn63xxp1;
+	struct cvmx_sriomaintx_m2s_bar1_start1_s cn66xx;
 };
 typedef union cvmx_sriomaintx_m2s_bar1_start1 cvmx_sriomaintx_m2s_bar1_start1_t;
 
@@ -3346,16 +3330,16 @@ typedef union cvmx_sriomaintx_m2s_bar1_start1 cvmx_sriomaintx_m2s_bar1_start1_t;
  *  ADDR66, ADDR64 and ADDR48 fields set to zero and supplies zeros for unused addresses 40:34.
  *  50-bit address transactions a match of SRIO Address 49:41 and require all the other bits of ADDR64
  *  and ADDR66 to be zero.  66-bit address transactions require matches of all valid address field
- *  bits.  This register is only writeable over SRIO if the SRIO(0..1)_ACC_CTRL.DENY_BAR2 bit is zero.
+ *  bits.  The ADDR32/48/64/66 fields of this register are writeable over SRIO if the
+ *  SRIO(0,2..3)_ACC_CTRL.DENY_ADR2 bit is zero.  The remaining fields are writeable over SRIO if the
+ *  SRIO(0,2..3)_ACC_CTRL.DENY_BAR2 bit is zero.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_M2S_BAR2_START  hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_M2S_BAR2_START        hclk    hrst_n
  */
-union cvmx_sriomaintx_m2s_bar2_start
-{
+union cvmx_sriomaintx_m2s_bar2_start {
 	uint32_t u32;
-	struct cvmx_sriomaintx_m2s_bar2_start_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_m2s_bar2_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t addr64                       : 16; /**< SRIO Address 63:48 */
 	uint32_t addr48                       : 7;  /**< SRIO Address 47:41 */
 	uint32_t reserved_6_8                 : 3;
@@ -3384,13 +3368,14 @@ union cvmx_sriomaintx_m2s_bar2_start
 	} s;
 	struct cvmx_sriomaintx_m2s_bar2_start_s cn63xx;
 	struct cvmx_sriomaintx_m2s_bar2_start_s cn63xxp1;
+	struct cvmx_sriomaintx_m2s_bar2_start_s cn66xx;
 };
 typedef union cvmx_sriomaintx_m2s_bar2_start cvmx_sriomaintx_m2s_bar2_start_t;
 
 /**
  * cvmx_sriomaint#_mac_ctrl
  *
- * SRIOMAINT_MAC_CTRL = SRIO MAC Control (Pass 2)
+ * SRIOMAINT_MAC_CTRL = SRIO MAC Control
  *
  * Control for MAC Features
  *
@@ -3399,15 +3384,21 @@ typedef union cvmx_sriomaintx_m2s_bar2_start cvmx_sriomaintx_m2s_bar2_start_t;
  *  default values should be supported.  This register can be changed at any time while the MAC is
  *  out of reset.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_MAC_CTRL        hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_MAC_CTRL      hclk    hrst_n
  */
-union cvmx_sriomaintx_mac_ctrl
-{
+union cvmx_sriomaintx_mac_ctrl {
 	uint32_t u32;
-	struct cvmx_sriomaintx_mac_ctrl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint32_t reserved_19_31               : 13;
+	struct cvmx_sriomaintx_mac_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_21_31               : 11;
+	uint32_t sec_spf                      : 1;  /**< Send all Incoming Packets matching Secondary ID to
+                                                         RX Soft Packet FIFO.  This bit is ignored if
+                                                         RX_SPF is set. */
+	uint32_t ack_zero                     : 1;  /**< Generate ACKs for all incoming Zero Byte packets.
+                                                         Default behavior is to issue a NACK.  Regardless
+                                                         of this setting the SRIO(0,2..3)_INT_REG.ZERO_PKT
+                                                         interrupt is generated.
+                                                         SRIO(0,2..3)_INT_REG. */
 	uint32_t rx_spf                       : 1;  /**< Route all received packets to RX Soft Packet FIFO.
                                                          No logical layer ERB Errors will be reported.
                                                          Used for Diagnostics Only. */
@@ -3416,16 +3407,44 @@ union cvmx_sriomaintx_mac_ctrl
 	uint32_t type_mrg                     : 1;  /**< Allow STYPE Merging on Transmit. */
 	uint32_t lnk_rtry                     : 16; /**< Number of times MAC will reissue Link Request
                                                          after timeout.  If retry count is exceeded Fatal
-                                                         Port Error will occur (see SRIO(0..1)_INT_REG.F_ERROR) */
+                                                         Port Error will occur (see SRIO(0,2..3)_INT_REG.F_ERROR) */
 #else
 	uint32_t lnk_rtry                     : 16;
 	uint32_t type_mrg                     : 1;
 	uint32_t eop_mrg                      : 1;
 	uint32_t rx_spf                       : 1;
-	uint32_t reserved_19_31               : 13;
+	uint32_t ack_zero                     : 1;
+	uint32_t sec_spf                      : 1;
+	uint32_t reserved_21_31               : 11;
 #endif
 	} s;
-	struct cvmx_sriomaintx_mac_ctrl_s     cn63xx;
+	struct cvmx_sriomaintx_mac_ctrl_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint32_t reserved_20_31               : 12;
+	uint32_t ack_zero                     : 1;  /**< Generate ACKs for all incoming Zero Byte packets.
+                                                         Default behavior is to issue a NACK.  Regardless
+                                                         of this setting the SRIO(0..1)_INT_REG.ZERO_PKT
+                                                         interrupt is generated.
+                                                         SRIO(0..1)_INT_REG. */
+	uint32_t rx_spf                       : 1;  /**< Route all received packets to RX Soft Packet FIFO.
+                                                         No logical layer ERB Errors will be reported.
+                                                         Used for Diagnostics Only. */
+	uint32_t eop_mrg                      : 1;  /**< Transmitted Packets can eliminate EOP Symbol on
+                                                         back to back packets. */
+	uint32_t type_mrg                     : 1;  /**< Allow STYPE Merging on Transmit. */
+	uint32_t lnk_rtry                     : 16; /**< Number of times MAC will reissue Link Request
+                                                         after timeout.  If retry count is exceeded Fatal
+                                                         Port Error will occur (see SRIO(0..1)_INT_REG.F_ERROR) */
+#else
+	uint32_t lnk_rtry                     : 16;
+	uint32_t type_mrg                     : 1;
+	uint32_t eop_mrg                      : 1;
+	uint32_t rx_spf                       : 1;
+	uint32_t ack_zero                     : 1;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} cn63xx;
+	struct cvmx_sriomaintx_mac_ctrl_s     cn66xx;
 };
 typedef union cvmx_sriomaintx_mac_ctrl cvmx_sriomaintx_mac_ctrl_t;
 
@@ -3440,14 +3459,12 @@ typedef union cvmx_sriomaintx_mac_ctrl cvmx_sriomaintx_mac_ctrl_t;
  * The Processing Element Feature register describes the major functionality provided by the SRIO
  *  device.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_PE_FEAT hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_PE_FEAT       hclk    hrst_n
  */
-union cvmx_sriomaintx_pe_feat
-{
+union cvmx_sriomaintx_pe_feat {
 	uint32_t u32;
-	struct cvmx_sriomaintx_pe_feat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_pe_feat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t bridge                       : 1;  /**< Bridge Functions not supported. */
 	uint32_t memory                       : 1;  /**< PE contains addressable memory. */
 	uint32_t proc                         : 1;  /**< PE contains a local processor. */
@@ -3476,6 +3493,7 @@ union cvmx_sriomaintx_pe_feat
 	} s;
 	struct cvmx_sriomaintx_pe_feat_s      cn63xx;
 	struct cvmx_sriomaintx_pe_feat_s      cn63xxp1;
+	struct cvmx_sriomaintx_pe_feat_s      cn66xx;
 };
 typedef union cvmx_sriomaintx_pe_feat cvmx_sriomaintx_pe_feat_t;
 
@@ -3489,14 +3507,12 @@ typedef union cvmx_sriomaintx_pe_feat cvmx_sriomaintx_pe_feat_t;
  * Notes:
  * The Processing Element Logical Layer is used for general configuration for the logical interface.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_PE_LLC  hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_PE_LLC        hclk    hrst_n
  */
-union cvmx_sriomaintx_pe_llc
-{
+union cvmx_sriomaintx_pe_llc {
 	uint32_t u32;
-	struct cvmx_sriomaintx_pe_llc_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_pe_llc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_3_31                : 29;
 	uint32_t ex_addr                      : 3;  /**< Controls the number of address bits generated by
                                                          PE as a source and processed by the PE as a
@@ -3512,6 +3528,7 @@ union cvmx_sriomaintx_pe_llc
 	} s;
 	struct cvmx_sriomaintx_pe_llc_s       cn63xx;
 	struct cvmx_sriomaintx_pe_llc_s       cn63xxp1;
+	struct cvmx_sriomaintx_pe_llc_s       cn66xx;
 };
 typedef union cvmx_sriomaintx_pe_llc cvmx_sriomaintx_pe_llc_t;
 
@@ -3525,36 +3542,37 @@ typedef union cvmx_sriomaintx_pe_llc cvmx_sriomaintx_pe_llc_t;
  * Notes:
  * This register contains assorted control bits.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_PORT_0_CTL      hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_PORT_0_CTL    hclk    hrst_n
  */
-union cvmx_sriomaintx_port_0_ctl
-{
+union cvmx_sriomaintx_port_0_ctl {
 	uint32_t u32;
-	struct cvmx_sriomaintx_port_0_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_port_0_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t pt_width                     : 2;  /**< Hardware Port Width.
                                                          00 = One Lane supported.
-                                                         01 = One/Two Lanes supported.
-                                                         10 = One/Four Lanes supported.
+                                                         01 = One/Four Lanes supported.
+                                                         10 = One/Two Lanes supported.
                                                          11 = One/Two/Four Lanes supported.
-                                                         This is a RO copy of SRIO*_IP_FEATURE[PT_WIDTH]. */
+                                                         This value is a copy of SRIO*_IP_FEATURE[PT_WIDTH]
+                                                         limited by the number of lanes the MAC has. */
 	uint32_t it_width                     : 3;  /**< Initialized Port Width
                                                          000 = Single-lane, Lane 0
                                                          001 = Single-lane, Lane 1 or 2
                                                          010 = Four-lane
                                                          011 = Two-lane
+                                                         111 = Link Uninitialized
                                                          Others = Reserved */
 	uint32_t ov_width                     : 3;  /**< Override Port Width.  Writing this register causes
                                                          the port to reinitialize.
                                                          000 = No Override all lanes possible
                                                          001 = Reserved
                                                          010 = Force Single-lane, Lane 0
+                                                               If Ln 0 is unavailable try Ln 2 then Ln 1
                                                          011 = Force Single-lane, Lane 2
-                                                               (Lane 1 if only lanes 0,1 are connected)
+                                                               If Ln 2 is unavailable try Ln 1 then Ln 0
                                                          100 = Reserved
-                                                         101 = Force Two-lane, Disable Four-Lane
-                                                         110 = Force Four-lane, Disable Two-Lane
+                                                         101 = Enable Two-lane, Disable Four-Lane
+                                                         110 = Enable Four-lane, Disable Two-Lane
                                                          111 = All lanes sizes enabled */
 	uint32_t disable                      : 1;  /**< Port Disable.  Setting this bit disables both
                                                          drivers and receivers. */
@@ -3617,6 +3635,7 @@ union cvmx_sriomaintx_port_0_ctl
 	} s;
 	struct cvmx_sriomaintx_port_0_ctl_s   cn63xx;
 	struct cvmx_sriomaintx_port_0_ctl_s   cn63xxp1;
+	struct cvmx_sriomaintx_port_0_ctl_s   cn66xx;
 };
 typedef union cvmx_sriomaintx_port_0_ctl cvmx_sriomaintx_port_0_ctl_t;
 
@@ -3629,16 +3648,16 @@ typedef union cvmx_sriomaintx_port_0_ctl cvmx_sriomaintx_port_0_ctl_t;
  *
  * Notes:
  * These registers are accessed when a local processor or an external device wishes to examine the
- *  port baudrate information.  WARNING:  Writes to this register will reinitialize the SRIO link.
+ *  port baudrate information.  The Automatic Baud Rate Feature is not available on this device.  The
+ *  SUP_* and ENB_* fields are set directly by the QLM_SPD bits as a reference but otherwise have
+ *  no effect.  WARNING:  Writes to this register will reinitialize the SRIO link.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_PORT_0_CTL2     hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_PORT_0_CTL2   hclk    hrst_n
  */
-union cvmx_sriomaintx_port_0_ctl2
-{
+union cvmx_sriomaintx_port_0_ctl2 {
 	uint32_t u32;
-	struct cvmx_sriomaintx_port_0_ctl2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_port_0_ctl2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t sel_baud                     : 4;  /**< Link Baud Rate Selected.
                                                            0000 - No rate selected
                                                            0001 - 1.25 GBaud
@@ -3648,8 +3667,7 @@ union cvmx_sriomaintx_port_0_ctl2
                                                            0101 - 6.25 GBaud (reserved)
                                                            0110 - 0b1111 - Reserved
                                                          Indicates the speed of the interface SERDES lanes
-                                                         (should match the value selected by SUP_* /ENB_*
-                                                         below). */
+                                                         (selected by the QLM*_SPD straps). */
 	uint32_t baud_sup                     : 1;  /**< Automatic Baud Rate Discovery not supported. */
 	uint32_t baud_enb                     : 1;  /**< Auto Baud Rate Discovery Enable. */
 	uint32_t sup_125g                     : 1;  /**< 1.25GB Rate Operation supported.
@@ -3710,6 +3728,7 @@ union cvmx_sriomaintx_port_0_ctl2
 	} s;
 	struct cvmx_sriomaintx_port_0_ctl2_s  cn63xx;
 	struct cvmx_sriomaintx_port_0_ctl2_s  cn63xxp1;
+	struct cvmx_sriomaintx_port_0_ctl2_s  cn66xx;
 };
 typedef union cvmx_sriomaintx_port_0_ctl2 cvmx_sriomaintx_port_0_ctl2_t;
 
@@ -3723,23 +3742,22 @@ typedef union cvmx_sriomaintx_port_0_ctl2 cvmx_sriomaintx_port_0_ctl2_t;
  * Notes:
  * This register displays port error and status information.  Several port error conditions are
  *  captured here and must be cleared by writing 1's to the individual bits.
+ *  Bits are R/W on 65/66xx pass 1 and R/W1C on pass 1.2
  *
- * Clk_Rst:        SRIOMAINT(0..1)_PORT_0_ERR_STAT hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_PORT_0_ERR_STAT       hclk    hrst_n
  */
-union cvmx_sriomaintx_port_0_err_stat
-{
+union cvmx_sriomaintx_port_0_err_stat {
 	uint32_t u32;
-	struct cvmx_sriomaintx_port_0_err_stat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_port_0_err_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_27_31               : 5;
 	uint32_t pkt_drop                     : 1;  /**< Output Packet Dropped. */
 	uint32_t o_fail                       : 1;  /**< Output Port has encountered a failure condition,
                                                          meaning the port's failed error threshold has
-                                                         reached SRIOMAINT(0..1)_ERB_ERR_RATE_THR.ER_FAIL value. */
+                                                         reached SRIOMAINT(0,2..3)_ERB_ERR_RATE_THR.ER_FAIL value. */
 	uint32_t o_dgrad                      : 1;  /**< Output Port has encountered a degraded condition,
                                                          meaning the port's degraded threshold has
-                                                         reached SRIOMAINT(0..1)_ERB_ERR_RATE_THR.ER_DGRAD
+                                                         reached SRIOMAINT(0,2..3)_ERB_ERR_RATE_THR.ER_DGRAD
                                                          value. */
 	uint32_t reserved_21_23               : 3;
 	uint32_t o_retry                      : 1;  /**< Output Retry Encountered.  This bit is set when
@@ -3766,7 +3784,8 @@ union cvmx_sriomaintx_port_0_err_stat
                                                          error. */
 	uint32_t reserved_5_7                 : 3;
 	uint32_t pt_write                     : 1;  /**< Port has encountered a condition which required it
-                                                         initiate a Maintenance Port-Write Operation. */
+                                                         initiate a Maintenance Port-Write Operation.
+                                                         Never set by hardware. */
 	uint32_t reserved_3_3                 : 1;
 	uint32_t pt_error                     : 1;  /**< Input or Output Port has encountered an
                                                          unrecoverable error condition. */
@@ -3800,29 +3819,28 @@ union cvmx_sriomaintx_port_0_err_stat
 	} s;
 	struct cvmx_sriomaintx_port_0_err_stat_s cn63xx;
 	struct cvmx_sriomaintx_port_0_err_stat_s cn63xxp1;
+	struct cvmx_sriomaintx_port_0_err_stat_s cn66xx;
 };
 typedef union cvmx_sriomaintx_port_0_err_stat cvmx_sriomaintx_port_0_err_stat_t;
 
 /**
  * cvmx_sriomaint#_port_0_link_req
  *
- * SRIOMAINT_PORT_0_LINK_REQ = SRIO Port 0 Link Request (Pass 2)
+ * SRIOMAINT_PORT_0_LINK_REQ = SRIO Port 0 Link Request
  *
  * Port 0 Manual Link Request
  *
  * Notes:
  * Writing this register generates the link request symbol or eight device reset symbols.   The
- *  progress of the request can be determined by reading SRIOMAINT(0..1)_PORT_0_LINK_RESP.  Only a single
+ *  progress of the request can be determined by reading SRIOMAINT(0,2..3)_PORT_0_LINK_RESP.  Only a single
  *  request should be generated at a time.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_PORT_0_LINK_REQ hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_PORT_0_LINK_REQ       hclk    hrst_n
  */
-union cvmx_sriomaintx_port_0_link_req
-{
+union cvmx_sriomaintx_port_0_link_req {
 	uint32_t u32;
-	struct cvmx_sriomaintx_port_0_link_req_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_port_0_link_req_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_3_31                : 29;
 	uint32_t cmd                          : 3;  /**< Link Request Command.
                                                          011 - Reset Device
@@ -3834,27 +3852,26 @@ union cvmx_sriomaintx_port_0_link_req
 #endif
 	} s;
 	struct cvmx_sriomaintx_port_0_link_req_s cn63xx;
+	struct cvmx_sriomaintx_port_0_link_req_s cn66xx;
 };
 typedef union cvmx_sriomaintx_port_0_link_req cvmx_sriomaintx_port_0_link_req_t;
 
 /**
  * cvmx_sriomaint#_port_0_link_resp
  *
- * SRIOMAINT_PORT_0_LINK_RESP = SRIO Port 0 Link Response (Pass 2)
+ * SRIOMAINT_PORT_0_LINK_RESP = SRIO Port 0 Link Response
  *
  * Port 0 Manual Link Response
  *
  * Notes:
- * This register only returns responses generated by writes to SRIOMAINT(0..1)_PORT_0_LINK_REQ.
+ * This register only returns responses generated by writes to SRIOMAINT(0,2..3)_PORT_0_LINK_REQ.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_PORT_0_LINK_RESP        hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_PORT_0_LINK_RESP      hclk    hrst_n
  */
-union cvmx_sriomaintx_port_0_link_resp
-{
+union cvmx_sriomaintx_port_0_link_resp {
 	uint32_t u32;
-	struct cvmx_sriomaintx_port_0_link_resp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_port_0_link_resp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t valid                        : 1;  /**< Link Response Valid.
                                                          1 = Link Response Received or Reset Device
                                                              Symbols Transmitted.  Value cleared on read.
@@ -3874,13 +3891,14 @@ union cvmx_sriomaintx_port_0_link_resp
 #endif
 	} s;
 	struct cvmx_sriomaintx_port_0_link_resp_s cn63xx;
+	struct cvmx_sriomaintx_port_0_link_resp_s cn66xx;
 };
 typedef union cvmx_sriomaintx_port_0_link_resp cvmx_sriomaintx_port_0_link_resp_t;
 
 /**
  * cvmx_sriomaint#_port_0_local_ackid
  *
- * SRIOMAINT_PORT_0_LOCAL_ACKID = SRIO Port 0 Local AckID (Pass 2)
+ * SRIOMAINT_PORT_0_LOCAL_ACKID = SRIO Port 0 Local AckID
  *
  * Port 0 Local AckID Control
  *
@@ -3888,16 +3906,14 @@ typedef union cvmx_sriomaintx_port_0_link_resp cvmx_sriomaintx_port_0_link_resp_
  * This register is typically only written when recovering from a failed link.  It may be read at any
  *  time the MAC is out of reset.  Writes to the O_ACKID field will be used for both the O_ACKID and
  *  E_ACKID.  Care must be taken to ensure that no packets are pending at the time of a write.  The
- *  number of pending packets can be read in the TX_INUSE field of SRIO(0..1)_MAC_BUFFERS.
+ *  number of pending packets can be read in the TX_INUSE field of SRIO(0,2..3)_MAC_BUFFERS.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_PORT_0_LOCAL_ACKID      hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_PORT_0_LOCAL_ACKID    hclk    hrst_n
  */
-union cvmx_sriomaintx_port_0_local_ackid
-{
+union cvmx_sriomaintx_port_0_local_ackid {
 	uint32_t u32;
-	struct cvmx_sriomaintx_port_0_local_ackid_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_port_0_local_ackid_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_30_31               : 2;
 	uint32_t i_ackid                      : 6;  /**< Next Expected Inbound AckID.
                                                          Bit 29 is used for IDLE2 and should be zero. */
@@ -3917,6 +3933,7 @@ union cvmx_sriomaintx_port_0_local_ackid
 #endif
 	} s;
 	struct cvmx_sriomaintx_port_0_local_ackid_s cn63xx;
+	struct cvmx_sriomaintx_port_0_local_ackid_s cn66xx;
 };
 typedef union cvmx_sriomaintx_port_0_local_ackid cvmx_sriomaintx_port_0_local_ackid_t;
 
@@ -3928,23 +3945,17 @@ typedef union cvmx_sriomaintx_port_0_local_ackid cvmx_sriomaintx_port_0_local_ac
  * Port General Control
  *
  * Notes:
- * Clk_Rst:        SRIOMAINT(0..1)_PORT_GEN_CTL    hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_PORT_GEN_CTL  hclk    hrst_n
  *
  */
-union cvmx_sriomaintx_port_gen_ctl
-{
+union cvmx_sriomaintx_port_gen_ctl {
 	uint32_t u32;
-	struct cvmx_sriomaintx_port_gen_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_port_gen_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t host                         : 1;  /**< Host Device.
                                                          The HOST reset value is based on corresponding
-                                                         MIO_RST_CTL*[PRTMODE], whose reset value is
-                                                         selected by the corresponding QLM*_HOST_MODE strap
-                                                         on a chip cold reset (and can be later modified by
-                                                         software). HOST resets to 1 when
-                                                         MIO_RST_CTL*[PRTMODE] selects RC (i.e. host) mode,
-                                                         else 0. */
+                                                         MIO_RST_CTL*[PRTMODE].  HOST resets to 1 when
+                                                         this field selects RC (i.e. host) mode, else 0. */
 	uint32_t menable                      : 1;  /**< Master Enable.  Must be set for device to issue
                                                          read, write, doorbell, message requests. */
 	uint32_t discover                     : 1;  /**< Discovered. The device has been discovered by the
@@ -3959,6 +3970,7 @@ union cvmx_sriomaintx_port_gen_ctl
 	} s;
 	struct cvmx_sriomaintx_port_gen_ctl_s cn63xx;
 	struct cvmx_sriomaintx_port_gen_ctl_s cn63xxp1;
+	struct cvmx_sriomaintx_port_gen_ctl_s cn66xx;
 };
 typedef union cvmx_sriomaintx_port_gen_ctl cvmx_sriomaintx_port_gen_ctl_t;
 
@@ -3975,18 +3987,16 @@ typedef union cvmx_sriomaintx_port_gen_ctl cvmx_sriomaintx_port_gen_ctl_t;
  *  link-response.  Each count represents 200ns.  The minimum timeout period is the TIMEOUT x 200nS
  *  and the maximum is twice that number.  A value less than 32 may not guarantee that all timeout
  *  errors will be reported correctly.  When the timeout period expires the packet or link request is
- *  dropped and the error is logged in the LNK_TOUT field of the SRIOMAINT(0..1)_ERB_ERR_DET register.  A
+ *  dropped and the error is logged in the LNK_TOUT field of the SRIOMAINT(0,2..3)_ERB_ERR_DET register.  A
  *  value of 0 in this register will allow the packet or link request to be issued but it will timeout
  *  immediately.  This value is not recommended for normal operation.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_PORT_LT_CTL     hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_PORT_LT_CTL   hclk    hrst_n
  */
-union cvmx_sriomaintx_port_lt_ctl
-{
+union cvmx_sriomaintx_port_lt_ctl {
 	uint32_t u32;
-	struct cvmx_sriomaintx_port_lt_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_port_lt_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t timeout                      : 24; /**< Timeout Value */
 	uint32_t reserved_0_7                 : 8;
 #else
@@ -3996,6 +4006,7 @@ union cvmx_sriomaintx_port_lt_ctl
 	} s;
 	struct cvmx_sriomaintx_port_lt_ctl_s  cn63xx;
 	struct cvmx_sriomaintx_port_lt_ctl_s  cn63xxp1;
+	struct cvmx_sriomaintx_port_lt_ctl_s  cn66xx;
 };
 typedef union cvmx_sriomaintx_port_lt_ctl cvmx_sriomaintx_port_lt_ctl_t;
 
@@ -4007,15 +4018,13 @@ typedef union cvmx_sriomaintx_port_lt_ctl cvmx_sriomaintx_port_lt_ctl_t;
  * Port Maintenance Block Header 0
  *
  * Notes:
- * Clk_Rst:        SRIOMAINT(0..1)_PORT_MBH0       hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_PORT_MBH0     hclk    hrst_n
  *
  */
-union cvmx_sriomaintx_port_mbh0
-{
+union cvmx_sriomaintx_port_mbh0 {
 	uint32_t u32;
-	struct cvmx_sriomaintx_port_mbh0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_port_mbh0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ef_ptr                       : 16; /**< Pointer to Error Management Block. */
 	uint32_t ef_id                        : 16; /**< Extended Feature ID (Generic Endpoint Device) */
 #else
@@ -4025,6 +4034,7 @@ union cvmx_sriomaintx_port_mbh0
 	} s;
 	struct cvmx_sriomaintx_port_mbh0_s    cn63xx;
 	struct cvmx_sriomaintx_port_mbh0_s    cn63xxp1;
+	struct cvmx_sriomaintx_port_mbh0_s    cn66xx;
 };
 typedef union cvmx_sriomaintx_port_mbh0 cvmx_sriomaintx_port_mbh0_t;
 
@@ -4041,22 +4051,20 @@ typedef union cvmx_sriomaintx_port_mbh0 cvmx_sriomaintx_port_mbh0_t;
  *  response being sent to receiving the corresponding response.  This is used for all outgoing packet
  *  types including memory, maintenance, doorbells and message operations.  When the timeout period
  *  expires the packet is disgarded and the error is logged in the PKT_TOUT field of the
- *  SRIOMAINT(0..1)_ERB_LT_ERR_DET register.  The second use of this register is as a timeout period
+ *  SRIOMAINT(0,2..3)_ERB_LT_ERR_DET register.  The second use of this register is as a timeout period
  *  between incoming message segments of the same message.  If a message segment is received then the
- *  MSG_TOUT field of the SRIOMAINT(0..1)_ERB_LT_ERR_DET register is set if the next segment has not been
+ *  MSG_TOUT field of the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET register is set if the next segment has not been
  *  received before the time expires.  In both cases, each count represents 200ns.  The minimum
  *  timeout period is the TIMEOUT x 200nS and the maximum is twice that number.  A value less than 32
  *  may not guarantee that all timeout errors will be reported correctly.  A value of 0 disables the
  *  logical layer timeouts and is not recommended for normal operation.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_PORT_RT_CTL     hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_PORT_RT_CTL   hclk    hrst_n
  */
-union cvmx_sriomaintx_port_rt_ctl
-{
+union cvmx_sriomaintx_port_rt_ctl {
 	uint32_t u32;
-	struct cvmx_sriomaintx_port_rt_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_port_rt_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t timeout                      : 24; /**< Timeout Value */
 	uint32_t reserved_0_7                 : 8;
 #else
@@ -4066,13 +4074,14 @@ union cvmx_sriomaintx_port_rt_ctl
 	} s;
 	struct cvmx_sriomaintx_port_rt_ctl_s  cn63xx;
 	struct cvmx_sriomaintx_port_rt_ctl_s  cn63xxp1;
+	struct cvmx_sriomaintx_port_rt_ctl_s  cn66xx;
 };
 typedef union cvmx_sriomaintx_port_rt_ctl cvmx_sriomaintx_port_rt_ctl_t;
 
 /**
  * cvmx_sriomaint#_port_ttl_ctl
  *
- * SRIOMAINT_PORT_TTL_CTL = SRIO Packet Time to Live Control (Pass 2)
+ * SRIOMAINT_PORT_TTL_CTL = SRIO Packet Time to Live Control
  *
  * Packet Time to Live
  *
@@ -4080,22 +4089,24 @@ typedef union cvmx_sriomaintx_port_rt_ctl cvmx_sriomaintx_port_rt_ctl_t;
  * This register controls the timeout for outgoing packets.  It is used to make sure packets are
  *  being transmitted and acknowledged within a reasonable period of time.   The timeout value
  *  corresponds to TIMEOUT x 200ns and a value of 0 disables the timer.  The actualy value of the
- *  should be greater than the physical layer timout specified in SRIOMAINT(0..1)_PORT_LT_CTL and is
- *  typically a less SRIOMAINT(0..1)_PORT_LT_CTL timeout than the response timeout specified in
- *  SRIOMAINT(0..1)_PORT_RT_CTL.  When the timeout expires the TTL interrupt is asserted, any packets
- *  currently being transmitted are dropped, the SRIOMAINT(0..1)_TX_DROP.DROP bit is set (causing any
- *  scheduled packets to be dropped), the SRIOMAINT(0..1)_TX_DROP.DROP_CNT is incremented and the SRIO
- *  output state is set to IDLE (all errors are cleared).  Software must clear the
- *  SRIOMAINT(0..1)_TX_DROP.DROP bit to resume transmitting packets.
- *
- * Clk_Rst:        SRIOMAINT(0..1)_PORT_RT_CTL     hclk    hrst_n
+ *  should be greater than the physical layer timout specified in SRIOMAINT(0,2..3)_PORT_LT_CTL and is
+ *  typically a less SRIOMAINT(0,2..3)_PORT_LT_CTL timeout than the response timeout specified in
+ *  SRIOMAINT(0,2..3)_PORT_RT_CTL.  A second application of this timer is to remove all the packets waiting
+ *  to be transmitted including those already in flight.  This may necessary in the case of a link
+ *  going down (see SRIO(0,2..3)_INT_REG.LINK_DWN).  This can accomplished by setting the TIMEOUT to small
+ *  value all so that all TX packets can be dropped.  In either case, when the timeout expires the TTL
+ *  interrupt is asserted, any packets currently being transmitted are dropped, the
+ *  SRIOMAINT(0,2..3)_TX_DROP.DROP bit is set (causing any scheduled packets to be dropped), the
+ *  SRIOMAINT(0,2..3)_TX_DROP.DROP_CNT is incremented for each packet and the SRIO output state is set to
+ *  IDLE (all errors are cleared).  Software must clear the SRIOMAINT(0,2..3)_TX_DROP.DROP bit to resume
+ *  transmitting packets.
+ *
+ * Clk_Rst:        SRIOMAINT(0,2..3)_PORT_RT_CTL   hclk    hrst_n
  */
-union cvmx_sriomaintx_port_ttl_ctl
-{
+union cvmx_sriomaintx_port_ttl_ctl {
 	uint32_t u32;
-	struct cvmx_sriomaintx_port_ttl_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_port_ttl_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t timeout                      : 24; /**< Timeout Value */
 	uint32_t reserved_0_7                 : 8;
 #else
@@ -4104,6 +4115,7 @@ union cvmx_sriomaintx_port_ttl_ctl
 #endif
 	} s;
 	struct cvmx_sriomaintx_port_ttl_ctl_s cn63xx;
+	struct cvmx_sriomaintx_port_ttl_ctl_s cn66xx;
 };
 typedef union cvmx_sriomaintx_port_ttl_ctl cvmx_sriomaintx_port_ttl_ctl_t;
 
@@ -4116,16 +4128,14 @@ typedef union cvmx_sriomaintx_port_ttl_ctl cvmx_sriomaintx_port_ttl_ctl_t;
  *
  * Notes:
  * This register defines the primary 8 and 16 bit device IDs used for large and small transport.  An
- *  optional secondary set of device IDs are located in SRIOMAINT(0..1)_SEC_DEV_ID.
+ *  optional secondary set of device IDs are located in SRIOMAINT(0,2..3)_SEC_DEV_ID.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_PRI_DEV_ID      hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_PRI_DEV_ID    hclk    hrst_n
  */
-union cvmx_sriomaintx_pri_dev_id
-{
+union cvmx_sriomaintx_pri_dev_id {
 	uint32_t u32;
-	struct cvmx_sriomaintx_pri_dev_id_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_pri_dev_id_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_24_31               : 8;
 	uint32_t id8                          : 8;  /**< Primary 8-bit Device ID */
 	uint32_t id16                         : 16; /**< Primary 16-bit Device ID */
@@ -4137,6 +4147,7 @@ union cvmx_sriomaintx_pri_dev_id
 	} s;
 	struct cvmx_sriomaintx_pri_dev_id_s   cn63xx;
 	struct cvmx_sriomaintx_pri_dev_id_s   cn63xxp1;
+	struct cvmx_sriomaintx_pri_dev_id_s   cn66xx;
 };
 typedef union cvmx_sriomaintx_pri_dev_id cvmx_sriomaintx_pri_dev_id_t;
 
@@ -4152,14 +4163,12 @@ typedef union cvmx_sriomaintx_pri_dev_id cvmx_sriomaintx_pri_dev_id_t;
  *  The corresponding secondary ID must be written before the ID is enabled.  The secondary IDs should
  *  not be enabled if the values of the primary and secondary IDs are identical.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_SEC_DEV_CTRL    hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_SEC_DEV_CTRL  hclk    hrst_n
  */
-union cvmx_sriomaintx_sec_dev_ctrl
-{
+union cvmx_sriomaintx_sec_dev_ctrl {
 	uint32_t u32;
-	struct cvmx_sriomaintx_sec_dev_ctrl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_sec_dev_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_2_31                : 30;
 	uint32_t enable8                      : 1;  /**< Enable matches to secondary 8-bit Device ID */
 	uint32_t enable16                     : 1;  /**< Enable matches to secondary 16-bit Device ID */
@@ -4171,6 +4180,7 @@ union cvmx_sriomaintx_sec_dev_ctrl
 	} s;
 	struct cvmx_sriomaintx_sec_dev_ctrl_s cn63xx;
 	struct cvmx_sriomaintx_sec_dev_ctrl_s cn63xxp1;
+	struct cvmx_sriomaintx_sec_dev_ctrl_s cn66xx;
 };
 typedef union cvmx_sriomaintx_sec_dev_ctrl cvmx_sriomaintx_sec_dev_ctrl_t;
 
@@ -4184,18 +4194,16 @@ typedef union cvmx_sriomaintx_sec_dev_ctrl cvmx_sriomaintx_sec_dev_ctrl_t;
  * Notes:
  * This register defines the secondary 8 and 16 bit device IDs used for large and small transport.
  *  The corresponding secondary ID must be written before the ID is enabled in the
- *  SRIOMAINT(0..1)_SEC_DEV_CTRL register.  The primary set of device IDs are located in
- *  SRIOMAINT(0..1)_PRI_DEV_ID register.  The secondary IDs should not be written to the same values as the
+ *  SRIOMAINT(0,2..3)_SEC_DEV_CTRL register.  The primary set of device IDs are located in
+ *  SRIOMAINT(0,2..3)_PRI_DEV_ID register.  The secondary IDs should not be written to the same values as the
  *  corresponding primary IDs.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_SEC_DEV_ID      hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_SEC_DEV_ID    hclk    hrst_n
  */
-union cvmx_sriomaintx_sec_dev_id
-{
+union cvmx_sriomaintx_sec_dev_id {
 	uint32_t u32;
-	struct cvmx_sriomaintx_sec_dev_id_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_sec_dev_id_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_24_31               : 8;
 	uint32_t id8                          : 8;  /**< Secondary 8-bit Device ID */
 	uint32_t id16                         : 16; /**< Secondary 16-bit Device ID */
@@ -4207,6 +4215,7 @@ union cvmx_sriomaintx_sec_dev_id
 	} s;
 	struct cvmx_sriomaintx_sec_dev_id_s   cn63xx;
 	struct cvmx_sriomaintx_sec_dev_id_s   cn63xxp1;
+	struct cvmx_sriomaintx_sec_dev_id_s   cn66xx;
 };
 typedef union cvmx_sriomaintx_sec_dev_id cvmx_sriomaintx_sec_dev_id_t;
 
@@ -4221,14 +4230,12 @@ typedef union cvmx_sriomaintx_sec_dev_id cvmx_sriomaintx_sec_dev_id_t;
  * The error management extensions block header register contains the EF_PTR to the next EF_BLK and
  *  the EF_ID that identifies this as the Serial Lane Status Block.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_SERIAL_LANE_HDR hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_SERIAL_LANE_HDR       hclk    hrst_n
  */
-union cvmx_sriomaintx_serial_lane_hdr
-{
+union cvmx_sriomaintx_serial_lane_hdr {
 	uint32_t u32;
-	struct cvmx_sriomaintx_serial_lane_hdr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_serial_lane_hdr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ef_ptr                       : 16; /**< Pointer to the next block in the extended features
                                                          data structure. */
 	uint32_t ef_id                        : 16;
@@ -4239,6 +4246,7 @@ union cvmx_sriomaintx_serial_lane_hdr
 	} s;
 	struct cvmx_sriomaintx_serial_lane_hdr_s cn63xx;
 	struct cvmx_sriomaintx_serial_lane_hdr_s cn63xxp1;
+	struct cvmx_sriomaintx_serial_lane_hdr_s cn66xx;
 };
 typedef union cvmx_sriomaintx_serial_lane_hdr cvmx_sriomaintx_serial_lane_hdr_t;
 
@@ -4251,16 +4259,14 @@ typedef union cvmx_sriomaintx_serial_lane_hdr cvmx_sriomaintx_serial_lane_hdr_t;
  *
  * Notes:
  * The logical operations initiated by the Cores.   The Source OPs register shows the operations
- *  specified in the SRIO(0..1)_IP_FEATURE.OPS register.
+ *  specified in the SRIO(0,2..3)_IP_FEATURE.OPS register.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_SRC_OPS hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_SRC_OPS       hclk    hrst_n
  */
-union cvmx_sriomaintx_src_ops
-{
+union cvmx_sriomaintx_src_ops {
 	uint32_t u32;
-	struct cvmx_sriomaintx_src_ops_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_src_ops_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t gsm_read                     : 1;  /**< PE does not support Read Home operations.
                                                          This is a RO copy of SRIO*_IP_FEATURE[OPS<31>] */
 	uint32_t i_read                       : 1;  /**< PE does not support Instruction Read.
@@ -4342,43 +4348,43 @@ union cvmx_sriomaintx_src_ops
 	} s;
 	struct cvmx_sriomaintx_src_ops_s      cn63xx;
 	struct cvmx_sriomaintx_src_ops_s      cn63xxp1;
+	struct cvmx_sriomaintx_src_ops_s      cn66xx;
 };
 typedef union cvmx_sriomaintx_src_ops cvmx_sriomaintx_src_ops_t;
 
 /**
  * cvmx_sriomaint#_tx_drop
  *
- * SRIOMAINT_TX_DROP = SRIO MAC Outgoing Packet Drop (Pass 2)
+ * SRIOMAINT_TX_DROP = SRIO MAC Outgoing Packet Drop
  *
  * Outging SRIO Packet Drop Control/Status
  *
  * Notes:
  * This register controls and provides status for dropping outgoing SRIO packets.  The DROP bit
  *  should only be cleared when no packets are currently being dropped.  This can be guaranteed by
- *  clearing the SRIOMAINT(0..1)_PORT_0_CTL.O_ENABLE bit before changing the DROP bit and restoring the
+ *  clearing the SRIOMAINT(0,2..3)_PORT_0_CTL.O_ENABLE bit before changing the DROP bit and restoring the
  *  O_ENABLE afterwards.
  *
- * Clk_Rst:        SRIOMAINT(0..1)_MAC_CTRL        hclk    hrst_n
+ * Clk_Rst:        SRIOMAINT(0,2..3)_MAC_CTRL      hclk    hrst_n
  */
-union cvmx_sriomaintx_tx_drop
-{
+union cvmx_sriomaintx_tx_drop {
 	uint32_t u32;
-	struct cvmx_sriomaintx_tx_drop_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriomaintx_tx_drop_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_17_31               : 15;
 	uint32_t drop                         : 1;  /**< All outgoing packets are dropped.  Any packets
                                                          requiring a response will return 1's after the
-                                                         SRIOMAINT(0..1)_PORT_RT_CTL Timeout expires.  This bit
+                                                         SRIOMAINT(0,2..3)_PORT_RT_CTL Timeout expires.  This bit
                                                          is set automatically when the TTL Timeout occurs
                                                          or can be set by software and must always be
                                                          cleared by software. */
 	uint32_t drop_cnt                     : 16; /**< Number of packets dropped by transmit logic.
                                                          Packets are dropped whenever a packet is ready to
                                                          be transmitted and a TTL Timeouts occur, the  DROP
-                                                         bit is set or the SRIOMAINT(0..1)_ERB_ERR_RATE_THR
+                                                         bit is set or the SRIOMAINT(0,2..3)_ERB_ERR_RATE_THR
                                                          FAIL_TH has been reached and the DROP_PKT bit is
-                                                         set in SRIOMAINT(0..1)_PORT_0_CTL. */
+                                                         set in SRIOMAINT(0,2..3)_PORT_0_CTL.  This counter wraps
+                                                         on overflow and is cleared only on reset. */
 #else
 	uint32_t drop_cnt                     : 16;
 	uint32_t drop                         : 1;
@@ -4386,6 +4392,7 @@ union cvmx_sriomaintx_tx_drop
 #endif
 	} s;
 	struct cvmx_sriomaintx_tx_drop_s      cn63xx;
+	struct cvmx_sriomaintx_tx_drop_s      cn66xx;
 };
 typedef union cvmx_sriomaintx_tx_drop cvmx_sriomaintx_tx_drop_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-sriox-defs.h b/sys/contrib/octeon-sdk/cvmx-sriox-defs.h
index 0055a54..f3d4fe4 100644
--- a/sys/contrib/octeon-sdk/cvmx-sriox-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-sriox-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,514 +49,571 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_SRIOX_TYPEDEFS_H__
-#define __CVMX_SRIOX_TYPEDEFS_H__
+#ifndef __CVMX_SRIOX_DEFS_H__
+#define __CVMX_SRIOX_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_ACC_CTRL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_ACC_CTRL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_ASMBLY_ID(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_ASMBLY_ID(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_ASMBLY_INFO(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_ASMBLY_INFO(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_BELL_RESP_CTRL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_BELL_RESP_CTRL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_BIST_STATUS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_IMSG_CTRL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_IMSG_CTRL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_IMSG_INST_HDRX(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
 		cvmx_warn("CVMX_SRIOX_IMSG_INST_HDRX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 1) * 0x200000ull) * 8;
+	return CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8;
 }
 #else
-#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 1) * 0x200000ull) * 8)
+#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_IMSG_QOS_GRPX(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 31)) && ((block_id <= 1))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 31)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 31)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
 		cvmx_warn("CVMX_SRIOX_IMSG_QOS_GRPX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 1) * 0x200000ull) * 8;
+	return CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8;
 }
 #else
-#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 1) * 0x200000ull) * 8)
+#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_IMSG_STATUSX(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 23)) && ((block_id <= 1))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 23)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 23)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
 		cvmx_warn("CVMX_SRIOX_IMSG_STATUSX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 1) * 0x200000ull) * 8;
+	return CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8;
 }
 #else
-#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 1) * 0x200000ull) * 8)
+#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_IMSG_VPORT_THR(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_IMSG_VPORT_THR(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_IMSG_VPORT_THR2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
+		cvmx_warn("CVMX_SRIOX_IMSG_VPORT_THR2(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_INT2_ENABLE(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_INT2_ENABLE(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_INT2_REG(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_INT2_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_INT_ENABLE(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_INT_ENABLE(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_INT_INFO0(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_INT_INFO0(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_INT_INFO1(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_INT_INFO1(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_INT_INFO2(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_INT_INFO2(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_INT_INFO3(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_INT_INFO3(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_INT_REG(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_INT_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_IP_FEATURE(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_IP_FEATURE(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_MAC_BUFFERS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_MAC_BUFFERS(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_MAINT_OP(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_MAINT_OP(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_MAINT_RD_DATA(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_MAINT_RD_DATA(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_MCE_TX_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_MCE_TX_CTL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_MEM_OP_CTRL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_MEM_OP_CTRL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_OMSG_CTRLX(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
 		cvmx_warn("CVMX_SRIOX_OMSG_CTRLX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64;
+	return CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64;
 }
 #else
-#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_OMSG_DONE_COUNTSX(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
 		cvmx_warn("CVMX_SRIOX_OMSG_DONE_COUNTSX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64;
+	return CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64;
 }
 #else
-#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_OMSG_FMP_MRX(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
 		cvmx_warn("CVMX_SRIOX_OMSG_FMP_MRX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64;
+	return CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64;
 }
 #else
-#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_OMSG_NMP_MRX(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
 		cvmx_warn("CVMX_SRIOX_OMSG_NMP_MRX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64;
+	return CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64;
 }
 #else
-#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_OMSG_PORTX(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
 		cvmx_warn("CVMX_SRIOX_OMSG_PORTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64;
+	return CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64;
 }
 #else
-#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_OMSG_SILO_THR(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_OMSG_SILO_THR(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_OMSG_SP_MRX(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
 		cvmx_warn("CVMX_SRIOX_OMSG_SP_MRX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64;
+	return CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64;
 }
 #else
-#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_PRIOX_IN_USE(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
 		cvmx_warn("CVMX_SRIOX_PRIOX_IN_USE(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x200000ull) * 8;
+	return CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8;
 }
 #else
-#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x200000ull) * 8)
+#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_RX_BELL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_RX_BELL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_RX_BELL_SEQ(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_RX_BELL_SEQ(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_RX_STATUS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_RX_STATUS(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_S2M_TYPEX(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 15)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
 		cvmx_warn("CVMX_SRIOX_S2M_TYPEX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8;
+	return CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8;
 }
 #else
-#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
+#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_SEQ(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_SEQ(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_STATUS_REG(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_STATUS_REG(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_TAG_CTRL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_TAG_CTRL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_TLP_CREDITS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_TX_BELL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_TX_BELL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_TX_BELL_INFO(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_TX_BELL_INFO(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_TX_CTRL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_TX_CTRL(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_TX_EMPHASIS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_TX_EMPHASIS(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_TX_STATUS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_TX_STATUS(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRIOX_WR_DONE_COUNTS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
 		cvmx_warn("CVMX_SRIOX_WR_DONE_COUNTS(%lu) is invalid on this chip\n", block_id);
-	return CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 1) * 0x1000000ull;
+	return CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull;
 }
 #else
-#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull)
 #endif
 
 /**
@@ -569,17 +626,45 @@ static inline uint64_t CVMX_SRIOX_WR_DONE_COUNTS(unsigned long block_id)
  * Notes:
  * This register controls write access to the BAR registers via SRIO Maintenance Operations.  At
  *  powerup the BAR registers can be accessed via RSL and Maintenance Operations.  If the DENY_BAR*
- *  bits are set then Maintenance Writes to the corresponding BAR registers are ignored.  This
- *  register does not effect read operations.
+ *  bits or DENY_ADR* bits are set then Maintenance Writes to the corresponding BAR fields are
+ *  ignored.  Setting both the DENY_BAR and DENY_ADR for a corresponding BAR is compatable with the
+ *  operation of the DENY_BAR bit found in 63xx Pass 2 and earlier.  This register does not effect
+ *  read operations.  Reset values for DENY_BAR[2:0] are typically clear but they are set if
+ *  the chip is operating in Authentik Mode.
  *
- * Clk_Rst:        SRIO(0..1)_ACC_CTRL     hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_ACC_CTRL   hclk    hrst_n
  */
-union cvmx_sriox_acc_ctrl
-{
+union cvmx_sriox_acc_ctrl {
 	uint64_t u64;
-	struct cvmx_sriox_acc_ctrl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_acc_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t deny_adr2                    : 1;  /**< Deny SRIO Write Access to SRIO Address Fields in
+                                                         SRIOMAINT(0,2..3)_BAR2* Registers */
+	uint64_t deny_adr1                    : 1;  /**< Deny SRIO Write Access to SRIO Address Fields in
+                                                         SRIOMAINT(0,2..3)_BAR1* Registers */
+	uint64_t deny_adr0                    : 1;  /**< Deny SRIO Write Access to SRIO Address Fields in
+                                                         SRIOMAINT(0,2..3)_BAR0* Registers */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t deny_bar2                    : 1;  /**< Deny SRIO Write Access to non-SRIO Address Fields
+                                                         in the SRIOMAINT_BAR2 Registers */
+	uint64_t deny_bar1                    : 1;  /**< Deny SRIO Write Access to non-SRIO Address Fields
+                                                         in the SRIOMAINT_BAR1 Registers */
+	uint64_t deny_bar0                    : 1;  /**< Deny SRIO Write Access to non-SRIO Address Fields
+                                                         in the SRIOMAINT_BAR0 Registers */
+#else
+	uint64_t deny_bar0                    : 1;
+	uint64_t deny_bar1                    : 1;
+	uint64_t deny_bar2                    : 1;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t deny_adr0                    : 1;
+	uint64_t deny_adr1                    : 1;
+	uint64_t deny_adr2                    : 1;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_sriox_acc_ctrl_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t deny_bar2                    : 1;  /**< Deny SRIO Write Access to BAR2 Registers */
 	uint64_t deny_bar1                    : 1;  /**< Deny SRIO Write Access to BAR1 Registers */
@@ -590,9 +675,9 @@ union cvmx_sriox_acc_ctrl
 	uint64_t deny_bar2                    : 1;
 	uint64_t reserved_3_63                : 61;
 #endif
-	} s;
-	struct cvmx_sriox_acc_ctrl_s          cn63xx;
-	struct cvmx_sriox_acc_ctrl_s          cn63xxp1;
+	} cn63xx;
+	struct cvmx_sriox_acc_ctrl_cn63xx     cn63xxp1;
+	struct cvmx_sriox_acc_ctrl_s          cn66xx;
 };
 typedef union cvmx_sriox_acc_ctrl cvmx_sriox_acc_ctrl_t;
 
@@ -604,18 +689,16 @@ typedef union cvmx_sriox_acc_ctrl cvmx_sriox_acc_ctrl_t;
  * The Assembly ID register controls the Assembly ID and Vendor
  *
  * Notes:
- * This register specifies the Assembly ID and Vendor visible in SRIOMAINT(0..1)_ASMBLY_ID register.  The
+ * This register specifies the Assembly ID and Vendor visible in SRIOMAINT(0,2..3)_ASMBLY_ID register.  The
  *  Assembly Vendor ID is typically supplied by the RapidIO Trade Association.  This register is only
- *  reset during COLD boot and may only be modified while SRIO(0..1)_STATUS_REG.ACCESS is zero.
+ *  reset during COLD boot and may only be modified while SRIO(0,2..3)_STATUS_REG.ACCESS is zero.
  *
- * Clk_Rst:        SRIO(0..1)_ASMBLY_ID    sclk    srst_cold_n
+ * Clk_Rst:        SRIO(0,2..3)_ASMBLY_ID  sclk    srst_cold_n
  */
-union cvmx_sriox_asmbly_id
-{
+union cvmx_sriox_asmbly_id {
 	uint64_t u64;
-	struct cvmx_sriox_asmbly_id_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_asmbly_id_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t assy_id                      : 16; /**< Assembly Identifer */
 	uint64_t assy_ven                     : 16; /**< Assembly Vendor Identifer */
@@ -627,6 +710,7 @@ union cvmx_sriox_asmbly_id
 	} s;
 	struct cvmx_sriox_asmbly_id_s         cn63xx;
 	struct cvmx_sriox_asmbly_id_s         cn63xxp1;
+	struct cvmx_sriox_asmbly_id_s         cn66xx;
 };
 typedef union cvmx_sriox_asmbly_id cvmx_sriox_asmbly_id_t;
 
@@ -639,17 +723,15 @@ typedef union cvmx_sriox_asmbly_id cvmx_sriox_asmbly_id_t;
  *
  * Notes:
  * The Assembly Info register controls the Assembly Revision visible in the ASSY_REV field of the
- *  SRIOMAINT(0..1)_ASMBLY_INFO register.  This register is only reset during COLD boot and may only be
- *  modified while SRIO(0..1)_STATUS_REG.ACCESS is zero.
+ *  SRIOMAINT(0,2..3)_ASMBLY_INFO register.  This register is only reset during COLD boot and may only be
+ *  modified while SRIO(0,2..3)_STATUS_REG.ACCESS is zero.
  *
- * Clk_Rst:        SRIO(0..1)_ASMBLY_INFO  sclk    srst_cold_n
+ * Clk_Rst:        SRIO(0,2..3)_ASMBLY_INFO        sclk    srst_cold_n
  */
-union cvmx_sriox_asmbly_info
-{
+union cvmx_sriox_asmbly_info {
 	uint64_t u64;
-	struct cvmx_sriox_asmbly_info_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_asmbly_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t assy_rev                     : 16; /**< Assembly Revision */
 	uint64_t reserved_0_15                : 16;
@@ -661,6 +743,7 @@ union cvmx_sriox_asmbly_info
 	} s;
 	struct cvmx_sriox_asmbly_info_s       cn63xx;
 	struct cvmx_sriox_asmbly_info_s       cn63xxp1;
+	struct cvmx_sriox_asmbly_info_s       cn66xx;
 };
 typedef union cvmx_sriox_asmbly_info cvmx_sriox_asmbly_info_t;
 
@@ -674,14 +757,12 @@ typedef union cvmx_sriox_asmbly_info cvmx_sriox_asmbly_info_t;
  * Notes:
  * This register is used to override the response priority of the outgoing doorbell responses.
  *
- * Clk_Rst:        SRIO(0..1)_BELL_RESP_CTRL       hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_BELL_RESP_CTRL     hclk    hrst_n
  */
-union cvmx_sriox_bell_resp_ctrl
-{
+union cvmx_sriox_bell_resp_ctrl {
 	uint64_t u64;
-	struct cvmx_sriox_bell_resp_ctrl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_bell_resp_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t rp1_sid                      : 1;  /**< Sets response priority for incomimg doorbells
                                                          of priority 1 on the secondary ID (0=2, 1=3) */
@@ -701,6 +782,7 @@ union cvmx_sriox_bell_resp_ctrl
 	} s;
 	struct cvmx_sriox_bell_resp_ctrl_s    cn63xx;
 	struct cvmx_sriox_bell_resp_ctrl_s    cn63xxp1;
+	struct cvmx_sriox_bell_resp_ctrl_s    cn66xx;
 };
 typedef union cvmx_sriox_bell_resp_ctrl cvmx_sriox_bell_resp_ctrl_t;
 
@@ -714,14 +796,57 @@ typedef union cvmx_sriox_bell_resp_ctrl cvmx_sriox_bell_resp_ctrl_t;
  * Notes:
  * BIST Results.
  *
- * Clk_Rst:        SRIO(0..1)_BIST_STATUS  hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_BIST_STATUS        hclk    hrst_n
  */
-union cvmx_sriox_bist_status
-{
+union cvmx_sriox_bist_status {
 	uint64_t u64;
-	struct cvmx_sriox_bist_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_45_63               : 19;
+	uint64_t lram                         : 1;  /**< Incoming Doorbell Lookup RAM. */
+	uint64_t mram                         : 2;  /**< Incoming Message SLI FIFO. */
+	uint64_t cram                         : 2;  /**< Incoming Rd/Wr/Response Command FIFO. */
+	uint64_t bell                         : 2;  /**< Incoming Doorbell FIFO. */
+	uint64_t otag                         : 2;  /**< Outgoing Tag Data. */
+	uint64_t itag                         : 1;  /**< Incoming TAG Data. */
+	uint64_t ofree                        : 1;  /**< Outgoing Free Pointer RAM (OFIFO) */
+	uint64_t rtn                          : 2;  /**< Outgoing Response Return FIFO. */
+	uint64_t obulk                        : 4;  /**< Outgoing Bulk Data RAMs (OFIFO) */
+	uint64_t optrs                        : 4;  /**< Outgoing Priority Pointer RAMs (OFIFO) */
+	uint64_t oarb2                        : 2;  /**< Additional Outgoing Priority RAMs. */
+	uint64_t rxbuf2                       : 2;  /**< Additional Incoming SRIO MAC Buffers. */
+	uint64_t oarb                         : 2;  /**< Outgoing Priority RAMs (OARB) */
+	uint64_t ispf                         : 1;  /**< Incoming Soft Packet FIFO */
+	uint64_t ospf                         : 1;  /**< Outgoing Soft Packet FIFO */
+	uint64_t txbuf                        : 2;  /**< Outgoing SRIO MAC Buffer. */
+	uint64_t rxbuf                        : 2;  /**< Incoming SRIO MAC Buffer. */
+	uint64_t imsg                         : 5;  /**< Incoming Message RAMs. */
+	uint64_t omsg                         : 7;  /**< Outgoing Message RAMs. */
+#else
+	uint64_t omsg                         : 7;
+	uint64_t imsg                         : 5;
+	uint64_t rxbuf                        : 2;
+	uint64_t txbuf                        : 2;
+	uint64_t ospf                         : 1;
+	uint64_t ispf                         : 1;
+	uint64_t oarb                         : 2;
+	uint64_t rxbuf2                       : 2;
+	uint64_t oarb2                        : 2;
+	uint64_t optrs                        : 4;
+	uint64_t obulk                        : 4;
+	uint64_t rtn                          : 2;
+	uint64_t ofree                        : 1;
+	uint64_t itag                         : 1;
+	uint64_t otag                         : 2;
+	uint64_t bell                         : 2;
+	uint64_t cram                         : 2;
+	uint64_t mram                         : 2;
+	uint64_t lram                         : 1;
+	uint64_t reserved_45_63               : 19;
+#endif
+	} s;
+	struct cvmx_sriox_bist_status_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_44_63               : 20;
 	uint64_t mram                         : 2;  /**< Incoming Message SLI FIFO. */
 	uint64_t cram                         : 2;  /**< Incoming Rd/Wr/Response Command FIFO. */
@@ -732,14 +857,15 @@ union cvmx_sriox_bist_status
 	uint64_t rtn                          : 2;  /**< Outgoing Response Return FIFO. */
 	uint64_t obulk                        : 4;  /**< Outgoing Bulk Data RAMs (OFIFO) */
 	uint64_t optrs                        : 4;  /**< Outgoing Priority Pointer RAMs (OFIFO) */
-	uint64_t reserved_22_23               : 2;
+	uint64_t oarb2                        : 2;  /**< Additional Outgoing Priority RAMs (Pass 2). */
 	uint64_t rxbuf2                       : 2;  /**< Additional Incoming SRIO MAC Buffers (Pass 2). */
 	uint64_t oarb                         : 2;  /**< Outgoing Priority RAMs (OARB) */
 	uint64_t ispf                         : 1;  /**< Incoming Soft Packet FIFO */
 	uint64_t ospf                         : 1;  /**< Outgoing Soft Packet FIFO */
 	uint64_t txbuf                        : 2;  /**< Outgoing SRIO MAC Buffer. */
 	uint64_t rxbuf                        : 2;  /**< Incoming SRIO MAC Buffer. */
-	uint64_t imsg                         : 5;  /**< Incoming Message RAMs. */
+	uint64_t imsg                         : 5;  /**< Incoming Message RAMs.
+                                                         IMSG<0> (i.e. <7>) unused in Pass 2 */
 	uint64_t omsg                         : 7;  /**< Outgoing Message RAMs. */
 #else
 	uint64_t omsg                         : 7;
@@ -750,7 +876,7 @@ union cvmx_sriox_bist_status
 	uint64_t ispf                         : 1;
 	uint64_t oarb                         : 2;
 	uint64_t rxbuf2                       : 2;
-	uint64_t reserved_22_23               : 2;
+	uint64_t oarb2                        : 2;
 	uint64_t optrs                        : 4;
 	uint64_t obulk                        : 4;
 	uint64_t rtn                          : 2;
@@ -762,11 +888,9 @@ union cvmx_sriox_bist_status
 	uint64_t mram                         : 2;
 	uint64_t reserved_44_63               : 20;
 #endif
-	} s;
-	struct cvmx_sriox_bist_status_s       cn63xx;
-	struct cvmx_sriox_bist_status_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	} cn63xx;
+	struct cvmx_sriox_bist_status_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_44_63               : 20;
 	uint64_t mram                         : 2;  /**< Incoming Message SLI FIFO. */
 	uint64_t cram                         : 2;  /**< Incoming Rd/Wr/Response Command FIFO. */
@@ -806,6 +930,7 @@ union cvmx_sriox_bist_status
 	uint64_t reserved_44_63               : 20;
 #endif
 	} cn63xxp1;
+	struct cvmx_sriox_bist_status_s       cn66xx;
 };
 typedef union cvmx_sriox_bist_status cvmx_sriox_bist_status_t;
 
@@ -819,14 +944,12 @@ typedef union cvmx_sriox_bist_status cvmx_sriox_bist_status_t;
  * Notes:
  * RSP_THR should not typically be modified from reset value.
  *
- * Clk_Rst:        SRIO(0..1)_IMSG_CTRL    hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_IMSG_CTRL  hclk    hrst_n
  */
-union cvmx_sriox_imsg_ctrl
-{
+union cvmx_sriox_imsg_ctrl {
 	uint64_t u64;
-	struct cvmx_sriox_imsg_ctrl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_imsg_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t to_mode                      : 1;  /**< MP message timeout mode:
                                                          - 0: The timeout counter gets reset whenever the
@@ -836,9 +959,7 @@ union cvmx_sriox_imsg_ctrl
                                                              next sequential segment is received and
                                                              accepted */
 	uint64_t reserved_30_30               : 1;
-	uint64_t rsp_thr                      : 6;  /**< Sets max number of msg responses in queue before
-                                                         sending link-layer retries (field value is added
-                                                         to 16 to create threshold value) */
+	uint64_t rsp_thr                      : 6;  /**< Reserved */
 	uint64_t reserved_22_23               : 2;
 	uint64_t rp1_sid                      : 1;  /**< Sets msg response priority for incomimg messages
                                                          of priority 1 on the secondary ID (0=2, 1=3) */
@@ -877,6 +998,7 @@ union cvmx_sriox_imsg_ctrl
 	} s;
 	struct cvmx_sriox_imsg_ctrl_s         cn63xx;
 	struct cvmx_sriox_imsg_ctrl_s         cn63xxp1;
+	struct cvmx_sriox_imsg_ctrl_s         cn66xx;
 };
 typedef union cvmx_sriox_imsg_ctrl cvmx_sriox_imsg_ctrl_t;
 
@@ -893,14 +1015,12 @@ typedef union cvmx_sriox_imsg_ctrl cvmx_sriox_imsg_ctrl_t;
  *  as a PIP/IPD PKT_INST_HDR. This CSR matches the PIP/IPD PKT_INST_HDR format except for the QOS
  *  and GRP fields. SRIO*_IMSG_QOS_GRP*[QOS*,GRP*] supply the QOS and GRP fields.
  *
- * Clk_Rst:        SRIO(0..1)_IMSG_INST_HDR[0:1]   hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_IMSG_INST_HDR[0:1] hclk    hrst_n
  */
-union cvmx_sriox_imsg_inst_hdrx
-{
+union cvmx_sriox_imsg_inst_hdrx {
 	uint64_t u64;
-	struct cvmx_sriox_imsg_inst_hdrx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_imsg_inst_hdrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t r                            : 1;  /**< Port/Controller X R */
 	uint64_t reserved_58_62               : 5;
 	uint64_t pm                           : 2;  /**< Port/Controller X PM */
@@ -934,6 +1054,7 @@ union cvmx_sriox_imsg_inst_hdrx
 	} s;
 	struct cvmx_sriox_imsg_inst_hdrx_s    cn63xx;
 	struct cvmx_sriox_imsg_inst_hdrx_s    cn63xxp1;
+	struct cvmx_sriox_imsg_inst_hdrx_s    cn66xx;
 };
 typedef union cvmx_sriox_imsg_inst_hdrx cvmx_sriox_imsg_inst_hdrx_t;
 
@@ -945,21 +1066,19 @@ typedef union cvmx_sriox_imsg_inst_hdrx cvmx_sriox_imsg_inst_hdrx_t;
  * The SRIO Incoming Message QOS/GRP Table Entry X
  *
  * Notes:
- * The QOS/GRP table contains 32 entries with 8 QOS/GRP pairs per entry - 256 pairs total.
- *       HW selects the table entry by the concatenation of SRIO_WORD0[PRIO,DIS,MBOX], thus entry 0 is
- *       used for messages with PRIO=0,DIS=0,MBOX=0, entry 1 is for PRIO=0,DIS=0,MBOX=1, etc.  HW
- *       selects the QOS/GRP pair from the table entry by the concatenation of SRIO_WORD0[ID,LETTER] as
- *       shown above. HW then inserts the QOS/GRP pair into SRIO_WORD1[QOS,GRP], which may commonly
- *       be used for the PIP/IPD PKT_INST_HDR[QOS,GRP] fields.
- *
- * Clk_Rst:        SRIO(0..1)_IMSG_QOS_GRP[0:1]    hclk    hrst_n
+ * The QOS/GRP table contains 32 entries with 8 QOS/GRP pairs per entry - 256 pairs total.  HW
+ *  selects the table entry by the concatenation of SRIO_WORD0[PRIO,DIS,MBOX], thus entry 0 is used
+ *  for messages with PRIO=0,DIS=0,MBOX=0, entry 1 is for PRIO=0,DIS=0,MBOX=1, etc.  HW selects the
+ *  QOS/GRP pair from the table entry by the concatenation of SRIO_WORD0[ID,LETTER] as shown above. HW
+ *  then inserts the QOS/GRP pair into SRIO_WORD1[QOS,GRP], which may commonly be used for the PIP/IPD
+ *  PKT_INST_HDR[QOS,GRP] fields.
+ *
+ * Clk_Rst:        SRIO(0,2..3)_IMSG_QOS_GRP[0:1]  hclk    hrst_n
  */
-union cvmx_sriox_imsg_qos_grpx
-{
+union cvmx_sriox_imsg_qos_grpx {
 	uint64_t u64;
-	struct cvmx_sriox_imsg_qos_grpx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_imsg_qos_grpx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_63_63               : 1;
 	uint64_t qos7                         : 3;  /**< Entry X:7 QOS (ID=1, LETTER=3) */
 	uint64_t grp7                         : 4;  /**< Entry X:7 GRP (ID=1, LETTER=3) */
@@ -1013,6 +1132,7 @@ union cvmx_sriox_imsg_qos_grpx
 	} s;
 	struct cvmx_sriox_imsg_qos_grpx_s     cn63xx;
 	struct cvmx_sriox_imsg_qos_grpx_s     cn63xxp1;
+	struct cvmx_sriox_imsg_qos_grpx_s     cn66xx;
 };
 typedef union cvmx_sriox_imsg_qos_grpx cvmx_sriox_imsg_qos_grpx_t;
 
@@ -1024,15 +1144,13 @@ typedef union cvmx_sriox_imsg_qos_grpx cvmx_sriox_imsg_qos_grpx_t;
  * The SRIO Incoming Message Status Table Entry X
  *
  * Notes:
- * Clk_Rst:        SRIO(0..1)_IMSG_STATUS[0:1]     hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_IMSG_STATUS[0:1]   hclk    hrst_n
  *
  */
-union cvmx_sriox_imsg_statusx
-{
+union cvmx_sriox_imsg_statusx {
 	uint64_t u64;
-	struct cvmx_sriox_imsg_statusx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_imsg_statusx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t val1                         : 1;  /**< Entry X:1 Valid */
 	uint64_t err1                         : 1;  /**< Entry X:1 Error */
 	uint64_t toe1                         : 1;  /**< Entry X:1 Timeout Error */
@@ -1086,6 +1204,7 @@ union cvmx_sriox_imsg_statusx
 	} s;
 	struct cvmx_sriox_imsg_statusx_s      cn63xx;
 	struct cvmx_sriox_imsg_statusx_s      cn63xxp1;
+	struct cvmx_sriox_imsg_statusx_s      cn66xx;
 };
 typedef union cvmx_sriox_imsg_statusx cvmx_sriox_imsg_statusx_t;
 
@@ -1097,30 +1216,27 @@ typedef union cvmx_sriox_imsg_statusx cvmx_sriox_imsg_statusx_t;
  * The SRIO Incoming Message Virtual Port Threshold Register
  *
  * Notes:
- * SRIO0_IMSG_VPORT_THR.MAX_TOT must be >= SRIO0_IMSG_VPORT_THR.BUF_THR + SRIO1_IMSG_VPORT_THR.BUF_THR
- * This register can be accessed regardless of the value in SRIO(0..1)_STATUS_REG.ACCESS and is not
- * effected by MAC reset.
+ * SRIO0_IMSG_VPORT_THR.MAX_TOT must be >= SRIO0_IMSG_VPORT_THR.BUF_THR
+ * + SRIO2_IMSG_VPORT_THR.BUF_THR + SRIO3_IMSG_VPORT_THR.BUF_THR.  This register can be accessed
+ * regardless of the value in SRIO(0,2..3)_STATUS_REG.ACCESS and is not effected by MAC reset.  The maximum
+ * number of VPORTs allocated to a MAC is limited to 46 if QLM0 is configured to x2 or x4 mode and 44
+ * if configured in x1 mode.
  *
- * Clk_Rst:        SRIO(0..1)_IMSG_VPORT_THR       sclk    srst_n
+ * Clk_Rst:        SRIO(0,2..3)_IMSG_VPORT_THR     sclk    srst_n
  */
-union cvmx_sriox_imsg_vport_thr
-{
+union cvmx_sriox_imsg_vport_thr {
 	uint64_t u64;
-	struct cvmx_sriox_imsg_vport_thr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_imsg_vport_thr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_54_63               : 10;
-	uint64_t max_tot                      : 6;  /**< Sets max number of vports available to SRIO0+SRIO1
-                                                         This field is only used in SRIO0.
-                                                         SRIO1 never uses SRIO1_IMSG_VPORT_THR[MAX_TOT]. */
+	uint64_t max_tot                      : 6;  /**< Sets max number of vports available to the chip
+                                                         This field is only used in SRIO0. */
 	uint64_t reserved_46_47               : 2;
-	uint64_t max_s1                       : 6;  /**< Sets max number of vports available to SRIO1
-                                                         This field is only used in SRIO0.
-                                                         SRIO1 never uses SRIO1_IMSG_VPORT_THR[MAX_S1]. */
+	uint64_t max_s1                       : 6;  /**< Reserved
+                                                         This field is only used in SRIO0. */
 	uint64_t reserved_38_39               : 2;
 	uint64_t max_s0                       : 6;  /**< Sets max number of vports available to SRIO0
-                                                         This field is only used in SRIO0.
-                                                         SRIO1 never uses SRIO1_IMSG_VPORT_THR[MAX_S0]. */
+                                                         This field is only used in SRIO0. */
 	uint64_t sp_vport                     : 1;  /**< Single-segment vport pre-allocation.
                                                          When set, single-segment messages use pre-allocated
                                                          vport slots (that do not count toward thresholds).
@@ -1161,28 +1277,66 @@ union cvmx_sriox_imsg_vport_thr
 	} s;
 	struct cvmx_sriox_imsg_vport_thr_s    cn63xx;
 	struct cvmx_sriox_imsg_vport_thr_s    cn63xxp1;
+	struct cvmx_sriox_imsg_vport_thr_s    cn66xx;
 };
 typedef union cvmx_sriox_imsg_vport_thr cvmx_sriox_imsg_vport_thr_t;
 
 /**
+ * cvmx_srio#_imsg_vport_thr2
+ *
+ * SRIO_IMSG_VPORT_THR2 = SRIO Incoming Message Virtual Port Additional Threshold
+ *
+ * The SRIO Incoming Message Virtual Port Additional Threshold Register
+ *
+ * Notes:
+ * Additional vport thresholds for SRIO MACs 2 and 3.  This register is only used in SRIO0 and is only
+ * used when the QLM0 is configured as x1 lanes or x2 lanes.  In the x1 case the maximum number of
+ * VPORTs is limited to 44.  In the x2 case the maximum number of VPORTs is limited to 46.  These
+ * values are ignored in the x4 configuration.  This register can be accessed regardless of the value
+ * in SRIO(0,2..3)_STATUS_REG.ACCESS and is not effected by MAC reset.
+ *
+ * Clk_Rst:        SRIO(0,2..3)_IMSG_VPORT_THR     sclk    srst_n
+ */
+union cvmx_sriox_imsg_vport_thr2 {
+	uint64_t u64;
+	struct cvmx_sriox_imsg_vport_thr2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_46_63               : 18;
+	uint64_t max_s3                       : 6;  /**< Sets max number of vports available to SRIO3
+                                                         This field is only used in SRIO0. */
+	uint64_t reserved_38_39               : 2;
+	uint64_t max_s2                       : 6;  /**< Sets max number of vports available to SRIO2
+                                                         This field is only used in SRIO0. */
+	uint64_t reserved_0_31                : 32;
+#else
+	uint64_t reserved_0_31                : 32;
+	uint64_t max_s2                       : 6;
+	uint64_t reserved_38_39               : 2;
+	uint64_t max_s3                       : 6;
+	uint64_t reserved_46_63               : 18;
+#endif
+	} s;
+	struct cvmx_sriox_imsg_vport_thr2_s   cn66xx;
+};
+typedef union cvmx_sriox_imsg_vport_thr2 cvmx_sriox_imsg_vport_thr2_t;
+
+/**
  * cvmx_srio#_int2_enable
  *
- * SRIO_INT2_ENABLE = SRIO Interrupt 2 Enable (Pass 2)
+ * SRIO_INT2_ENABLE = SRIO Interrupt 2 Enable
  *
  * Allows SRIO to generate additional interrupts when corresponding enable bit is set.
  *
  * Notes:
- * This register enables interrupts in SRIO(0..1)_INT2_REG that can be asserted while the MAC is in reset.
- *  The register can be accessed/modified regardless of the value of SRIO(0..1)_STATUS_REG.ACCESS.
+ * This register enables interrupts in SRIO(0,2..3)_INT2_REG that can be asserted while the MAC is in reset.
+ *  The register can be accessed/modified regardless of the value of SRIO(0,2..3)_STATUS_REG.ACCESS.
  *
- * Clk_Rst:        SRIO(0..1)_INT2_ENABLE  sclk    srst_n
+ * Clk_Rst:        SRIO(0,2..3)_INT2_ENABLE        sclk    srst_n
  */
-union cvmx_sriox_int2_enable
-{
+union cvmx_sriox_int2_enable {
 	uint64_t u64;
-	struct cvmx_sriox_int2_enable_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_int2_enable_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t pko_rst                      : 1;  /**< PKO Reset Error Enable */
 #else
@@ -1191,34 +1345,33 @@ union cvmx_sriox_int2_enable
 #endif
 	} s;
 	struct cvmx_sriox_int2_enable_s       cn63xx;
+	struct cvmx_sriox_int2_enable_s       cn66xx;
 };
 typedef union cvmx_sriox_int2_enable cvmx_sriox_int2_enable_t;
 
 /**
  * cvmx_srio#_int2_reg
  *
- * SRIO_INT2_REG = SRIO Interrupt 2 Register (Pass 2)
+ * SRIO_INT2_REG = SRIO Interrupt 2 Register
  *
  * Displays and clears which enabled interrupts have occured
  *
  * Notes:
  * This register provides interrupt status. Unlike SRIO*_INT_REG, SRIO*_INT2_REG can be accessed
  *  whenever the SRIO is present, regardless of whether the corresponding SRIO is in reset or not.
- *  INT_SUM shows the status of the interrupts in SRIO(0..1)_INT_REG.  Any set bits written to this
+ *  INT_SUM shows the status of the interrupts in SRIO(0,2..3)_INT_REG.  Any set bits written to this
  *  register clear the corresponding interrupt.  The register can be accessed/modified regardless of
- *  the value of SRIO(0..1)_STATUS_REG.ACCESS and probably should be the first register read when an SRIO
+ *  the value of SRIO(0,2..3)_STATUS_REG.ACCESS and probably should be the first register read when an SRIO
  *  interrupt occurs.
  *
- * Clk_Rst:        SRIO(0..1)_INT2_REG     sclk    srst_n
+ * Clk_Rst:        SRIO(0,2..3)_INT2_REG   sclk    srst_n
  */
-union cvmx_sriox_int2_reg
-{
+union cvmx_sriox_int2_reg {
 	uint64_t u64;
-	struct cvmx_sriox_int2_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_int2_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
-	uint64_t int_sum                      : 1;  /**< Interrupt Set and Enabled in SRIO(0..1)_INT_REG */
+	uint64_t int_sum                      : 1;  /**< Interrupt Set and Enabled in SRIO(0,2..3)_INT_REG */
 	uint64_t reserved_1_30                : 30;
 	uint64_t pko_rst                      : 1;  /**< PKO Reset Error - Message Received from PKO while
                                                          MAC in reset. */
@@ -1230,6 +1383,7 @@ union cvmx_sriox_int2_reg
 #endif
 	} s;
 	struct cvmx_sriox_int2_reg_s          cn63xx;
+	struct cvmx_sriox_int2_reg_s          cn66xx;
 };
 typedef union cvmx_sriox_int2_reg cvmx_sriox_int2_reg_t;
 
@@ -1243,19 +1397,18 @@ typedef union cvmx_sriox_int2_reg cvmx_sriox_int2_reg_t;
  * Notes:
  * This register enables interrupts.
  *
- * Clk_Rst:        SRIO(0..1)_INT_ENABLE   hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_INT_ENABLE hclk    hrst_n
  */
-union cvmx_sriox_int_enable
-{
+union cvmx_sriox_int_enable {
 	uint64_t u64;
-	struct cvmx_sriox_int_enable_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_26_63               : 38;
-	uint64_t ttl_tout                     : 1;  /**< Outgoing Packet Time to Live Timeout (Pass 2) */
-	uint64_t fail                         : 1;  /**< ERB Error Rate reached Fail Count (Pass 2) */
-	uint64_t degrade                      : 1;  /**< ERB Error Rate reached Degrade Count (Pass 2) */
-	uint64_t mac_buf                      : 1;  /**< SRIO MAC Buffer CRC Error (Pass 2) */
+	struct cvmx_sriox_int_enable_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_27_63               : 37;
+	uint64_t zero_pkt                     : 1;  /**< Received Incoming SRIO Zero byte packet */
+	uint64_t ttl_tout                     : 1;  /**< Outgoing Packet Time to Live Timeout */
+	uint64_t fail                         : 1;  /**< ERB Error Rate reached Fail Count */
+	uint64_t degrade                      : 1;  /**< ERB Error Rate reached Degrade Count */
+	uint64_t mac_buf                      : 1;  /**< SRIO MAC Buffer CRC Error */
 	uint64_t f_error                      : 1;  /**< SRIO Fatal Port Error (MAC reset required) */
 	uint64_t rtry_err                     : 1;  /**< Outbound Message Retry Threshold Exceeded */
 	uint64_t pko_err                      : 1;  /**< Outbound Message Received PKO Error */
@@ -1305,13 +1458,13 @@ union cvmx_sriox_int_enable
 	uint64_t degrade                      : 1;
 	uint64_t fail                         : 1;
 	uint64_t ttl_tout                     : 1;
-	uint64_t reserved_26_63               : 38;
+	uint64_t zero_pkt                     : 1;
+	uint64_t reserved_27_63               : 37;
 #endif
 	} s;
 	struct cvmx_sriox_int_enable_s        cn63xx;
-	struct cvmx_sriox_int_enable_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_int_enable_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_22_63               : 42;
 	uint64_t f_error                      : 1;  /**< SRIO Fatal Port Error (MAC reset required) */
 	uint64_t rtry_err                     : 1;  /**< Outbound Message Retry Threshold Exceeded */
@@ -1361,6 +1514,7 @@ union cvmx_sriox_int_enable
 	uint64_t reserved_22_63               : 42;
 #endif
 	} cn63xxp1;
+	struct cvmx_sriox_int_enable_s        cn66xx;
 };
 typedef union cvmx_sriox_int_enable cvmx_sriox_int_enable_t;
 
@@ -1373,7 +1527,7 @@ typedef union cvmx_sriox_int_enable cvmx_sriox_int_enable_t;
  *
  * Notes:
  * This register contains the first header word of the illegal s2m transaction associated with the
- *  SLI_ERR interrupt.  The remaining information is located in SRIO(0..1)_INT_INFO1.   This register is
+ *  SLI_ERR interrupt.  The remaining information is located in SRIO(0,2..3)_INT_INFO1.   This register is
  *  only updated when the SLI_ERR is initially detected.  Once the interrupt is cleared then
  *  additional information can be captured.
  *  Common Errors Include:
@@ -1383,14 +1537,12 @@ typedef union cvmx_sriox_int_enable cvmx_sriox_int_enable_t;
  *   4.  Load/Store Ops with a Length 0
  *   5.  Unexpected Responses
  *
- * Clk_Rst:        SRIO(0..1)_INT_REG      hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_INT_REG    hclk    hrst_n
  */
-union cvmx_sriox_int_info0
-{
+union cvmx_sriox_int_info0 {
 	uint64_t u64;
-	struct cvmx_sriox_int_info0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_int_info0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t cmd                          : 4;  /**< Command
                                                          0 = Load, Outgoing Read Request
                                                          4 = Store, Outgoing Write Request
@@ -1423,6 +1575,7 @@ union cvmx_sriox_int_info0
 	} s;
 	struct cvmx_sriox_int_info0_s         cn63xx;
 	struct cvmx_sriox_int_info0_s         cn63xxp1;
+	struct cvmx_sriox_int_info0_s         cn66xx;
 };
 typedef union cvmx_sriox_int_info0 cvmx_sriox_int_info0_t;
 
@@ -1435,18 +1588,16 @@ typedef union cvmx_sriox_int_info0 cvmx_sriox_int_info0_t;
  *
  * Notes:
  * This register contains the second header word of the illegal s2m transaction associated with the
- *  SLI_ERR interrupt.  The remaining information is located in SRIO(0..1)_INT_INFO0.   This register is
+ *  SLI_ERR interrupt.  The remaining information is located in SRIO(0,2..3)_INT_INFO0.   This register is
  *  only updated when the SLI_ERR is initially detected.  Once the interrupt is cleared then
  *  additional information can be captured.
  *
- * Clk_Rst:        SRIO(0..1)_INT_REG      hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_INT_REG    hclk    hrst_n
  */
-union cvmx_sriox_int_info1
-{
+union cvmx_sriox_int_info1 {
 	uint64_t u64;
-	struct cvmx_sriox_int_info1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_int_info1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t info1                        : 64; /**< Address (Load/Store) or First 64-bit Word of
                                                          Response Data Associated with Interrupt */
 #else
@@ -1455,6 +1606,7 @@ union cvmx_sriox_int_info1
 	} s;
 	struct cvmx_sriox_int_info1_s         cn63xx;
 	struct cvmx_sriox_int_info1_s         cn63xxp1;
+	struct cvmx_sriox_int_info1_s         cn66xx;
 };
 typedef union cvmx_sriox_int_info1 cvmx_sriox_int_info1_t;
 
@@ -1470,14 +1622,12 @@ typedef union cvmx_sriox_int_info1 cvmx_sriox_int_info1_t;
  *  interrupt.  This register is only updated when the OMSG_ERR is initially detected.  Once the
  *  interrupt is cleared then additional information can be captured.
  *
- * Clk_Rst:        SRIO(0..1)_INT_REG      hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_INT_REG    hclk    hrst_n
  */
-union cvmx_sriox_int_info2
-{
+union cvmx_sriox_int_info2 {
 	uint64_t u64;
-	struct cvmx_sriox_int_info2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_int_info2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t prio                         : 2;  /**< PRIO field of outbound message descriptor
                                                          associated with the OMSG_ERR interrupt */
 	uint64_t tt                           : 1;  /**< TT field of outbound message descriptor
@@ -1516,6 +1666,7 @@ union cvmx_sriox_int_info2
 	} s;
 	struct cvmx_sriox_int_info2_s         cn63xx;
 	struct cvmx_sriox_int_info2_s         cn63xxp1;
+	struct cvmx_sriox_int_info2_s         cn66xx;
 };
 typedef union cvmx_sriox_int_info2 cvmx_sriox_int_info2_t;
 
@@ -1531,14 +1682,12 @@ typedef union cvmx_sriox_int_info2 cvmx_sriox_int_info2_t;
  *  is only updated when the RTRY_ERR is initially detected.  Once the interrupt is cleared then
  *  additional information can be captured.
  *
- * Clk_Rst:        SRIO(0..1)_INT_REG      hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_INT_REG    hclk    hrst_n
  */
-union cvmx_sriox_int_info3
-{
+union cvmx_sriox_int_info3 {
 	uint64_t u64;
-	struct cvmx_sriox_int_info3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_int_info3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t prio                         : 2;  /**< Priority of received retry response message */
 	uint64_t tt                           : 2;  /**< TT of received retry response message */
 	uint64_t type                         : 4;  /**< Type of received retry response message
@@ -1572,6 +1721,7 @@ union cvmx_sriox_int_info3
 	} s;
 	struct cvmx_sriox_int_info3_s         cn63xx;
 	struct cvmx_sriox_int_info3_s         cn63xxp1;
+	struct cvmx_sriox_int_info3_s         cn66xx;
 };
 typedef union cvmx_sriox_int_info3 cvmx_sriox_int_info3_t;
 
@@ -1595,58 +1745,59 @@ typedef union cvmx_sriox_int_info3 cvmx_sriox_int_info3_t;
  *  SSIZE field is set to a reserved value, the SSIZE field combined with the packet length would
  *  result in more than 16 message segments, or the packet only contains a descriptor (no data).
  *
- * Clk_Rst:        SRIO(0..1)_INT_REG      hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_INT_REG    hclk    hrst_n
  */
-union cvmx_sriox_int_reg
-{
+union cvmx_sriox_int_reg {
 	uint64_t u64;
-	struct cvmx_sriox_int_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
-	uint64_t int2_sum                     : 1;  /**< Interrupt Set and Enabled in SRIO(0..1)_INT2_REG
-                                                         (Pass 2) */
-	uint64_t reserved_26_30               : 5;
-	uint64_t ttl_tout                     : 1;  /**< Outgoing Packet Time to Live Timeout (Pass 2)
-                                                         See SRIOMAINT(0..1)_DROP_PACKET */
-	uint64_t fail                         : 1;  /**< ERB Error Rate reached Fail Count (Pass 2)
-                                                         See SRIOMAINT(0..1)_ERB_ERR_RATE */
-	uint64_t degrad                       : 1;  /**< ERB Error Rate reached Degrade Count (Pass 2)
-                                                         See SRIOMAINT(0..1)_ERB_ERR_RATE */
-	uint64_t mac_buf                      : 1;  /**< SRIO MAC Buffer CRC Error (Pass 2)
-                                                         See SRIO(0..1)_MAC_BUFFERS */
+	uint64_t int2_sum                     : 1;  /**< Interrupt Set and Enabled in SRIO(0,2..3)_INT2_REG */
+	uint64_t reserved_27_30               : 4;
+	uint64_t zero_pkt                     : 1;  /**< Received Incoming SRIO Zero byte packet */
+	uint64_t ttl_tout                     : 1;  /**< Outgoing Packet Time to Live Timeout
+                                                         See SRIOMAINT(0,2..3)_DROP_PACKET */
+	uint64_t fail                         : 1;  /**< ERB Error Rate reached Fail Count
+                                                         See SRIOMAINT(0,2..3)_ERB_ERR_RATE */
+	uint64_t degrad                       : 1;  /**< ERB Error Rate reached Degrade Count
+                                                         See SRIOMAINT(0,2..3)_ERB_ERR_RATE */
+	uint64_t mac_buf                      : 1;  /**< SRIO MAC Buffer CRC Error
+                                                         See SRIO(0,2..3)_MAC_BUFFERS */
 	uint64_t f_error                      : 1;  /**< SRIO Fatal Port Error (MAC reset required) */
 	uint64_t rtry_err                     : 1;  /**< Outbound Message Retry Threshold Exceeded
-                                                         See SRIO(0..1)_INT_INFO3
+                                                         See SRIO(0,2..3)_INT_INFO3
                                                          When one or more of the segments in an outgoing
                                                          message have a RTRY_ERR, SRIO will not set
                                                          OMSG* after the message "transfer". */
 	uint64_t pko_err                      : 1;  /**< Outbound Message Received PKO Error */
 	uint64_t omsg_err                     : 1;  /**< Outbound Message Invalid Descriptor Error
-                                                         See SRIO(0..1)_INT_INFO2 */
-	uint64_t omsg1                        : 1;  /**< Controller 1 Outbound Message Complete */
-	uint64_t omsg0                        : 1;  /**< Controller 0 Outbound Message Complete */
+                                                         See SRIO(0,2..3)_INT_INFO2 */
+	uint64_t omsg1                        : 1;  /**< Controller 1 Outbound Message Complete
+                                                         See SRIO(0,2..3)_OMSG_DONE_COUNTS1 */
+	uint64_t omsg0                        : 1;  /**< Controller 0 Outbound Message Complete
+                                                         See SRIO(0,2..3)_OMSG_DONE_COUNTS0 */
 	uint64_t link_up                      : 1;  /**< Serial Link going from Inactive to Active */
 	uint64_t link_dwn                     : 1;  /**< Serial Link going from Active to Inactive */
 	uint64_t phy_erb                      : 1;  /**< Physical Layer Error detected in ERB
                                                          See SRIOMAINT*_ERB_ATTR_CAPT */
 	uint64_t log_erb                      : 1;  /**< Logical/Transport Layer Error detected in ERB
-                                                         See SRIOMAINT(0..1)_ERB_LT_ERR_DET */
+                                                         See SRIOMAINT(0,2..3)_ERB_LT_ERR_DET */
 	uint64_t soft_rx                      : 1;  /**< Incoming Packet received by Soft Packet FIFO */
 	uint64_t soft_tx                      : 1;  /**< Outgoing Packet sent by Soft Packet FIFO */
 	uint64_t mce_rx                       : 1;  /**< Incoming Multicast Event Symbol */
 	uint64_t mce_tx                       : 1;  /**< Outgoing Multicast Event Transmit Complete */
-	uint64_t wr_done                      : 1;  /**< Outgoing Last Nwrite_R DONE Response Received. */
+	uint64_t wr_done                      : 1;  /**< Outgoing Last Nwrite_R DONE Response Received.
+                                                         See SRIO(0,2..3)_WR_DONE_COUNTS */
 	uint64_t sli_err                      : 1;  /**< Unsupported S2M Transaction Received.
-                                                         See SRIO(0..1)_INT_INFO[1:0] */
+                                                         See SRIO(0,2..3)_INT_INFO[1:0] */
 	uint64_t deny_wr                      : 1;  /**< Incoming Maint_Wr Access to Denied Bar Registers. */
 	uint64_t bar_err                      : 1;  /**< Incoming Access Crossing/Missing BAR Address */
 	uint64_t maint_op                     : 1;  /**< Internal Maintenance Operation Complete.
-                                                         See SRIO(0..1)_MAINT_OP and SRIO(0..1)_MAINT_RD_DATA */
+                                                         See SRIO(0,2..3)_MAINT_OP and SRIO(0,2..3)_MAINT_RD_DATA */
 	uint64_t rxbell                       : 1;  /**< One or more Incoming Doorbells Received.
-                                                         Read SRIO(0..1)_RX_BELL to empty FIFO */
+                                                         Read SRIO(0,2..3)_RX_BELL to empty FIFO */
 	uint64_t bell_err                     : 1;  /**< Outgoing Doorbell Timeout, Retry or Error.
-                                                         See SRIO(0..1)_TX_BELL_INFO */
+                                                         See SRIO(0,2..3)_TX_BELL_INFO */
 	uint64_t txbell                       : 1;  /**< Outgoing Doorbell Complete.
                                                          TXBELL will not be asserted if a Timeout, Retry or
                                                          Error occurs. */
@@ -1677,15 +1828,15 @@ union cvmx_sriox_int_reg
 	uint64_t degrad                       : 1;
 	uint64_t fail                         : 1;
 	uint64_t ttl_tout                     : 1;
-	uint64_t reserved_26_30               : 5;
+	uint64_t zero_pkt                     : 1;
+	uint64_t reserved_27_30               : 4;
 	uint64_t int2_sum                     : 1;
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
 	struct cvmx_sriox_int_reg_s           cn63xx;
-	struct cvmx_sriox_int_reg_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_int_reg_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_22_63               : 42;
 	uint64_t f_error                      : 1;  /**< SRIO Fatal Port Error (MAC reset required) */
 	uint64_t rtry_err                     : 1;  /**< Outbound Message Retry Threshold Exceeded
@@ -1748,6 +1899,7 @@ union cvmx_sriox_int_reg
 	uint64_t reserved_22_63               : 42;
 #endif
 	} cn63xxp1;
+	struct cvmx_sriox_int_reg_s           cn66xx;
 };
 typedef union cvmx_sriox_int_reg cvmx_sriox_int_reg_t;
 
@@ -1761,16 +1913,54 @@ typedef union cvmx_sriox_int_reg cvmx_sriox_int_reg_t;
  * Notes:
  * This register is used to override powerup values used by the SRIOMAINT Registers and QLM
  *  configuration.  The register is only reset during COLD boot.  It should only be modified only
- *  while SRIO(0..1)_STATUS_REG.ACCESS is zero.
+ *  while SRIO(0,2..3)_STATUS_REG.ACCESS is zero.
  *
- * Clk_Rst:        SRIO(0..1)_IP_FEATURE   sclk    srst_cold_n
+ * Clk_Rst:        SRIO(0,2..3)_IP_FEATURE sclk    srst_cold_n
  */
-union cvmx_sriox_ip_feature
-{
+union cvmx_sriox_ip_feature {
 	uint64_t u64;
-	struct cvmx_sriox_ip_feature_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_ip_feature_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t ops                          : 32; /**< Reset Value for the OPs fields in both the
+                                                         SRIOMAINT(0,2..3)_SRC_OPS and SRIOMAINT(0,2..3)_DST_OPS
+                                                         registers. */
+	uint64_t reserved_15_31               : 17;
+	uint64_t no_vmin                      : 1;  /**< Lane Sync Valid Minimum Count Disable. (Pass 3)
+                                                         0 = Wait for 2^12 valid codewords and at least
+                                                             127 comma characters before starting
+                                                             alignment.
+                                                         1 = Wait only for 127 comma characters before
+                                                             starting alignment. (SRIO V1.3 Compatable) */
+	uint64_t a66                          : 1;  /**< 66-bit Address Support.  Value for bit 2 of the
+                                                         EX_ADDR field in the SRIOMAINT(0,2..3)_PE_FEAT register. */
+	uint64_t a50                          : 1;  /**< 50-bit Address Support.  Value for bit 1 of the
+                                                         EX_ADDR field in the SRIOMAINT(0,2..3)_PE_FEAT register. */
+	uint64_t reserved_11_11               : 1;
+	uint64_t tx_flow                      : 1;  /**< Reset Value for the TX_FLOW field in the
+                                                         SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG register. */
+	uint64_t pt_width                     : 2;  /**< Value for the PT_WIDTH field in the
+                                                         SRIOMAINT(0,2..3)_PORT_0_CTL register. */
+	uint64_t tx_pol                       : 4;  /**< TX Serdes Polarity Lanes 3-0
+                                                         0 = Normal Operation
+                                                         1 = Invert, Swap +/- Tx SERDES Pins */
+	uint64_t rx_pol                       : 4;  /**< RX Serdes Polarity Lanes 3-0
+                                                         0 = Normal Operation
+                                                         1 = Invert, Swap +/- Rx SERDES Pins */
+#else
+	uint64_t rx_pol                       : 4;
+	uint64_t tx_pol                       : 4;
+	uint64_t pt_width                     : 2;
+	uint64_t tx_flow                      : 1;
+	uint64_t reserved_11_11               : 1;
+	uint64_t a50                          : 1;
+	uint64_t a66                          : 1;
+	uint64_t no_vmin                      : 1;
+	uint64_t reserved_15_31               : 17;
+	uint64_t ops                          : 32;
+#endif
+	} s;
+	struct cvmx_sriox_ip_feature_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t ops                          : 32; /**< Reset Value for the OPs fields in both the
                                                          SRIOMAINT(0..1)_SRC_OPS and SRIOMAINT(0..1)_DST_OPS
                                                          registers. */
@@ -1781,9 +1971,13 @@ union cvmx_sriox_ip_feature
                                                          EX_ADDR field in the SRIOMAINT(0..1)_PE_FEAT register. */
 	uint64_t reserved_11_11               : 1;
 	uint64_t tx_flow                      : 1;  /**< Reset Value for the TX_FLOW field in the
-                                                         SRIOMAINT(0..1)_IR_BUFFER_CONFIG register. */
+                                                         SRIOMAINT(0..1)_IR_BUFFER_CONFIG register.
+                                                         Pass 2 will Reset to 1 when RTL ready.
+                                                         (TX flow control not supported in pass 1) */
 	uint64_t pt_width                     : 2;  /**< Value for the PT_WIDTH field in the
-                                                         SRIOMAINT(0..1)_PORT_0_CTL register. */
+                                                         SRIOMAINT(0..1)_PORT_0_CTL register.
+                                                         Reset to 0x2 rather than 0x3 in pass 1 (2 lane
+                                                         interface supported in pass 1). */
 	uint64_t tx_pol                       : 4;  /**< TX Serdes Polarity Lanes 3-0
                                                          0 = Normal Operation
                                                          1 = Invert, Swap +/- Tx SERDES Pins */
@@ -1801,16 +1995,16 @@ union cvmx_sriox_ip_feature
 	uint64_t reserved_14_31               : 18;
 	uint64_t ops                          : 32;
 #endif
-	} s;
-	struct cvmx_sriox_ip_feature_s        cn63xx;
-	struct cvmx_sriox_ip_feature_s        cn63xxp1;
+	} cn63xx;
+	struct cvmx_sriox_ip_feature_cn63xx   cn63xxp1;
+	struct cvmx_sriox_ip_feature_s        cn66xx;
 };
 typedef union cvmx_sriox_ip_feature cvmx_sriox_ip_feature_t;
 
 /**
  * cvmx_srio#_mac_buffers
  *
- * SRIO_MAC_BUFFERS = SRIO MAC Buffer Control (Pass 2)
+ * SRIO_MAC_BUFFERS = SRIO MAC Buffer Control
  *
  * Reports errors and controls buffer usage on the main MAC buffers
  *
@@ -1819,14 +2013,12 @@ typedef union cvmx_sriox_ip_feature cvmx_sriox_ip_feature_t;
  *  buffer in future operations.  It also displays the number of RX and TX buffers currently used by
  *  the MAC.
  *
- * Clk_Rst:        SRIO(0..1)_MAC_BUFFERS  hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_MAC_BUFFERS        hclk    hrst_n
  */
-union cvmx_sriox_mac_buffers
-{
+union cvmx_sriox_mac_buffers {
 	uint64_t u64;
-	struct cvmx_sriox_mac_buffers_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_mac_buffers_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_56_63               : 8;
 	uint64_t tx_enb                       : 8;  /**< TX Buffer Enable.  Each bit enables a specific TX
                                                          Buffer.  At least 2 of these bits must be set for
@@ -1839,7 +2031,7 @@ union cvmx_sriox_mac_buffers
 	uint64_t tx_stat                      : 8;  /**< Errors detected in main SRIO Transmit Buffers.
                                                          CRC error detected in buffer sets bit of buffer \#
                                                          until the corresponding TX_ENB is disabled.  Each
-                                                         bit set causes the SRIO(0..1)_INT_REG.MAC_BUF
+                                                         bit set causes the SRIO(0,2..3)_INT_REG.MAC_BUF
                                                          interrupt. */
 	uint64_t reserved_24_31               : 8;
 	uint64_t rx_enb                       : 8;  /**< RX Buffer Enable.  Each bit enables a specific RX
@@ -1853,7 +2045,7 @@ union cvmx_sriox_mac_buffers
 	uint64_t rx_stat                      : 8;  /**< Errors detected in main SRIO Receive Buffers.  CRC
                                                          error detected in buffer sets bit of buffer \#
                                                          until the corresponding RX_ENB is disabled.  Each
-                                                         bit set causes the SRIO(0..1)_INT_REG.MAC_BUF
+                                                         bit set causes the SRIO(0,2..3)_INT_REG.MAC_BUF
                                                          interrupt. */
 #else
 	uint64_t rx_stat                      : 8;
@@ -1869,6 +2061,7 @@ union cvmx_sriox_mac_buffers
 #endif
 	} s;
 	struct cvmx_sriox_mac_buffers_s       cn63xx;
+	struct cvmx_sriox_mac_buffers_s       cn66xx;
 };
 typedef union cvmx_sriox_mac_buffers cvmx_sriox_mac_buffers_t;
 
@@ -1888,14 +2081,12 @@ typedef union cvmx_sriox_mac_buffers cvmx_sriox_mac_buffers_t;
  *  clearing of the PENDING bit when an illegal address is selected. WR_DATA is used only during write
  *  operations.  Only 32-bit Maintenance Operations are supported.
  *
- * Clk_Rst:        SRIO(0..1)_MAINT_OP     hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_MAINT_OP   hclk    hrst_n
  */
-union cvmx_sriox_maint_op
-{
+union cvmx_sriox_maint_op {
 	uint64_t u64;
-	struct cvmx_sriox_maint_op_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_maint_op_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t wr_data                      : 32; /**< Write Data[31:0]. */
 	uint64_t reserved_27_31               : 5;
 	uint64_t fail                         : 1;  /**< Maintenance Operation Address Error */
@@ -1913,6 +2104,7 @@ union cvmx_sriox_maint_op
 	} s;
 	struct cvmx_sriox_maint_op_s          cn63xx;
 	struct cvmx_sriox_maint_op_s          cn63xxp1;
+	struct cvmx_sriox_maint_op_s          cn66xx;
 };
 typedef union cvmx_sriox_maint_op cvmx_sriox_maint_op_t;
 
@@ -1924,19 +2116,17 @@ typedef union cvmx_sriox_maint_op cvmx_sriox_maint_op_t;
  * Allows read access of maintenance registers.
  *
  * Notes:
- * This register allows read access of the local SRIOMAINT registers.  A write to the SRIO(0..1)_MAINT_OP
+ * This register allows read access of the local SRIOMAINT registers.  A write to the SRIO(0,2..3)_MAINT_OP
  *  register with the OP bit set to zero initiates a read request and clears the VALID bit.  The
  *  resulting read is returned here and the VALID bit is set.  Access to the register will not stall
  *  the RSL but the VALID bit should be read.
  *
- * Clk_Rst:        SRIO(0..1)_MAINT_RD_DATA        hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_MAINT_RD_DATA      hclk    hrst_n
  */
-union cvmx_sriox_maint_rd_data
-{
+union cvmx_sriox_maint_rd_data {
 	uint64_t u64;
-	struct cvmx_sriox_maint_rd_data_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_maint_rd_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_33_63               : 31;
 	uint64_t valid                        : 1;  /**< Read Data Valid. */
 	uint64_t rd_data                      : 32; /**< Read Data[31:0]. */
@@ -1948,6 +2138,7 @@ union cvmx_sriox_maint_rd_data
 	} s;
 	struct cvmx_sriox_maint_rd_data_s     cn63xx;
 	struct cvmx_sriox_maint_rd_data_s     cn63xxp1;
+	struct cvmx_sriox_maint_rd_data_s     cn66xx;
 };
 typedef union cvmx_sriox_maint_rd_data cvmx_sriox_maint_rd_data_t;
 
@@ -1964,14 +2155,12 @@ typedef union cvmx_sriox_maint_rd_data cvmx_sriox_maint_rd_data_t;
  *  of the transmit event.  The hardware will clear the bit when the event has been transmitted and
  *  set the MCS_TX Interrupt.
  *
- * Clk_Rst:        SRIO(0..1)_MCE_TX_CTL   hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_MCE_TX_CTL hclk    hrst_n
  */
-union cvmx_sriox_mce_tx_ctl
-{
+union cvmx_sriox_mce_tx_ctl {
 	uint64_t u64;
-	struct cvmx_sriox_mce_tx_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_mce_tx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t mce                          : 1;  /**< Multicast Event Transmit. */
 #else
@@ -1981,6 +2170,7 @@ union cvmx_sriox_mce_tx_ctl
 	} s;
 	struct cvmx_sriox_mce_tx_ctl_s        cn63xx;
 	struct cvmx_sriox_mce_tx_ctl_s        cn63xxp1;
+	struct cvmx_sriox_mce_tx_ctl_s        cn66xx;
 };
 typedef union cvmx_sriox_mce_tx_ctl cvmx_sriox_mce_tx_ctl_t;
 
@@ -1996,14 +2186,12 @@ typedef union cvmx_sriox_mce_tx_ctl cvmx_sriox_mce_tx_ctl_t;
  *  the outgoing responses to memory operations.  The memory operations with responses include NREAD,
  *  NWRITE_R, ATOMIC_INC, ATOMIC_DEC, ATOMIC_SET and ATOMIC_CLR.
  *
- * Clk_Rst:        SRIO(0..1)_MEM_OP_CTRL  hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_MEM_OP_CTRL        hclk    hrst_n
  */
-union cvmx_sriox_mem_op_ctrl
-{
+union cvmx_sriox_mem_op_ctrl {
 	uint64_t u64;
-	struct cvmx_sriox_mem_op_ctrl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_mem_op_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t rr_ro                        : 1;  /**< Read Response Relaxed Ordering.  Controls ordering
                                                          rules for incoming memory operations
@@ -2035,6 +2223,7 @@ union cvmx_sriox_mem_op_ctrl
 	} s;
 	struct cvmx_sriox_mem_op_ctrl_s       cn63xx;
 	struct cvmx_sriox_mem_op_ctrl_s       cn63xxp1;
+	struct cvmx_sriox_mem_op_ctrl_s       cn66xx;
 };
 typedef union cvmx_sriox_mem_op_ctrl cvmx_sriox_mem_op_ctrl_t;
 
@@ -2053,18 +2242,17 @@ typedef union cvmx_sriox_mem_op_ctrl cvmx_sriox_mem_op_ctrl_t;
  * 4) When IDM_TT=0, it is possible for an ID match to match an 8-bit DID with a 16-bit DID - SRIO
  *        zero-extends all 8-bit DID's, and the DID comparisons are always 16-bits.
  *
- * Clk_Rst:        SRIO(0..1)_OMSG_CTRL[0:1]       hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_OMSG_CTRL[0:1]     hclk    hrst_n
  */
-union cvmx_sriox_omsg_ctrlx
-{
+union cvmx_sriox_omsg_ctrlx {
 	uint64_t u64;
-	struct cvmx_sriox_omsg_ctrlx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_omsg_ctrlx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t testmode                     : 1;  /**< Controller X test mode (keep as RSVD in HRM) */
 	uint64_t reserved_37_62               : 26;
 	uint64_t silo_max                     : 5;  /**< Sets max number outgoing segments for controller X
-                                                         (Pass 2) */
+                                                         Valid range is 0x01 .. 0x10  Note that lower
+                                                         values will reduce bandwidth. */
 	uint64_t rtry_thr                     : 16; /**< Controller X Retry threshold */
 	uint64_t rtry_en                      : 1;  /**< Controller X Retry threshold enable */
 	uint64_t reserved_11_14               : 4;
@@ -2090,9 +2278,8 @@ union cvmx_sriox_omsg_ctrlx
 #endif
 	} s;
 	struct cvmx_sriox_omsg_ctrlx_s        cn63xx;
-	struct cvmx_sriox_omsg_ctrlx_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_omsg_ctrlx_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t testmode                     : 1;  /**< Controller X test mode (keep as RSVD in HRM) */
 	uint64_t reserved_32_62               : 31;
 	uint64_t rtry_thr                     : 16; /**< Controller X Retry threshold */
@@ -2118,13 +2305,14 @@ union cvmx_sriox_omsg_ctrlx
 	uint64_t testmode                     : 1;
 #endif
 	} cn63xxp1;
+	struct cvmx_sriox_omsg_ctrlx_s        cn66xx;
 };
 typedef union cvmx_sriox_omsg_ctrlx cvmx_sriox_omsg_ctrlx_t;
 
 /**
  * cvmx_srio#_omsg_done_counts#
  *
- * SRIO_OMSG_DONE_COUNTSX = SRIO Outbound Message Complete Counts (Pass 2)
+ * SRIO_OMSG_DONE_COUNTSX = SRIO Outbound Message Complete Counts
  *
  * The SRIO Controller X Outbound Message Complete Counts Register
  *
@@ -2135,14 +2323,12 @@ typedef union cvmx_sriox_omsg_ctrlx cvmx_sriox_omsg_ctrlx_t;
  *  enabled.  The sum of the GOOD and BAD counts should equal the number of messages sent unless
  *  the MAC has been reset.
  *
- * Clk_Rst:        SRIO(0..1)_OMSG_DONE_COUNTS[0:1]        hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_OMSG_DONE_COUNTS[0:1]      hclk    hrst_n
  */
-union cvmx_sriox_omsg_done_countsx
-{
+union cvmx_sriox_omsg_done_countsx {
 	uint64_t u64;
-	struct cvmx_sriox_omsg_done_countsx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_omsg_done_countsx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t bad                          : 16; /**< Number of Outbound Messages requesting an INT that
                                                          did not increment GOOD. (One or more segment of the
@@ -2157,6 +2343,7 @@ union cvmx_sriox_omsg_done_countsx
 #endif
 	} s;
 	struct cvmx_sriox_omsg_done_countsx_s cn63xx;
+	struct cvmx_sriox_omsg_done_countsx_s cn66xx;
 };
 typedef union cvmx_sriox_omsg_done_countsx cvmx_sriox_omsg_done_countsx_t;
 
@@ -2185,14 +2372,12 @@ typedef union cvmx_sriox_omsg_done_countsx cvmx_sriox_omsg_done_countsx_t;
  * silo. When fields in this CSR are set, FMP candidate segments will match fewer silo entries and
  * can enter the silo more freely, probably providing better performance.
  *
- * Clk_Rst:        SRIO(0..1)_OMSG_FMP_MR[0:1]     hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_OMSG_FMP_MR[0:1]   hclk    hrst_n
  */
-union cvmx_sriox_omsg_fmp_mrx
-{
+union cvmx_sriox_omsg_fmp_mrx {
 	uint64_t u64;
-	struct cvmx_sriox_omsg_fmp_mrx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_omsg_fmp_mrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_15_63               : 49;
 	uint64_t ctlr_sp                      : 1;  /**< Controller X FIRSTMP enable controller SP
                                                          When set, the FMP candidate message segment can
@@ -2305,6 +2490,7 @@ union cvmx_sriox_omsg_fmp_mrx
 	} s;
 	struct cvmx_sriox_omsg_fmp_mrx_s      cn63xx;
 	struct cvmx_sriox_omsg_fmp_mrx_s      cn63xxp1;
+	struct cvmx_sriox_omsg_fmp_mrx_s      cn66xx;
 };
 typedef union cvmx_sriox_omsg_fmp_mrx cvmx_sriox_omsg_fmp_mrx_t;
 
@@ -2333,14 +2519,12 @@ typedef union cvmx_sriox_omsg_fmp_mrx cvmx_sriox_omsg_fmp_mrx_t;
  * silo. When fields in this CSR are set, NMP candidate segments will match fewer silo entries and
  * can enter the silo more freely, probably providing better performance.
  *
- * Clk_Rst:        SRIO(0..1)_OMSG_NMP_MR[0:1]     hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_OMSG_NMP_MR[0:1]   hclk    hrst_n
  */
-union cvmx_sriox_omsg_nmp_mrx
-{
+union cvmx_sriox_omsg_nmp_mrx {
 	uint64_t u64;
-	struct cvmx_sriox_omsg_nmp_mrx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_omsg_nmp_mrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_15_63               : 49;
 	uint64_t ctlr_sp                      : 1;  /**< Controller X NFIRSTMP enable controller SP
                                                          When set, the NMP candidate message segment can
@@ -2438,6 +2622,7 @@ union cvmx_sriox_omsg_nmp_mrx
 	} s;
 	struct cvmx_sriox_omsg_nmp_mrx_s      cn63xx;
 	struct cvmx_sriox_omsg_nmp_mrx_s      cn63xxp1;
+	struct cvmx_sriox_omsg_nmp_mrx_s      cn66xx;
 };
 typedef union cvmx_sriox_omsg_nmp_mrx cvmx_sriox_omsg_nmp_mrx_t;
 
@@ -2451,23 +2636,38 @@ typedef union cvmx_sriox_omsg_nmp_mrx cvmx_sriox_omsg_nmp_mrx_t;
  * Notes:
  * PORT maps the PKO port to SRIO interface \# / controller X as follows:
  *
- *    00 == PKO port 40
- *    01 == PKO port 41
- *    10 == PKO port 42
- *    11 == PKO port 43
+ *   000 == PKO port 40
+ *   001 == PKO port 41
+ *   010 == PKO port 42
+ *   011 == PKO port 43
+ *   100 == PKO port 44
+ *   101 == PKO port 45
+ *   110 == PKO port 46
+ *   111 == PKO port 47
  *
  *  No two PORT fields among the enabled controllers (ENABLE == 1) may be set to the same value.
  *  The register is only reset during COLD boot.  The register can be accessed/modified regardless of
- *  the value in SRIO(0..1)_STATUS_REG.ACCESS.
+ *  the value in SRIO(0,2..3)_STATUS_REG.ACCESS.
  *
- * Clk_Rst:        SRIO(0..1)_OMSG_PORT[0:1]       sclk    srst_n
+ * Clk_Rst:        SRIO(0,2..3)_OMSG_PORT[0:1]     sclk    srst_n
  */
-union cvmx_sriox_omsg_portx
-{
+union cvmx_sriox_omsg_portx {
 	uint64_t u64;
-	struct cvmx_sriox_omsg_portx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_omsg_portx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t enable                       : 1;  /**< Controller X enable */
+	uint64_t reserved_3_30                : 28;
+	uint64_t port                         : 3;  /**< Controller X PKO port */
+#else
+	uint64_t port                         : 3;
+	uint64_t reserved_3_30                : 28;
+	uint64_t enable                       : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sriox_omsg_portx_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t enable                       : 1;  /**< Controller X enable */
 	uint64_t reserved_2_30                : 29;
@@ -2478,40 +2678,39 @@ union cvmx_sriox_omsg_portx
 	uint64_t enable                       : 1;
 	uint64_t reserved_32_63               : 32;
 #endif
-	} s;
-	struct cvmx_sriox_omsg_portx_s        cn63xx;
-	struct cvmx_sriox_omsg_portx_s        cn63xxp1;
+	} cn63xx;
+	struct cvmx_sriox_omsg_portx_cn63xx   cn63xxp1;
+	struct cvmx_sriox_omsg_portx_s        cn66xx;
 };
 typedef union cvmx_sriox_omsg_portx cvmx_sriox_omsg_portx_t;
 
 /**
  * cvmx_srio#_omsg_silo_thr
  *
- * SRIO_OMSG_SILO_THR = SRIO Outgoing Message SILO Thresholds (Pass 2)
+ * SRIO_OMSG_SILO_THR = SRIO Outgoing Message SILO Thresholds
  *
  * The SRIO Outgoing Message SILO Thresholds
  *
  * Notes:
- * Limits the number of Outgoing Message Segments in flight at a time.  This register is reserved in
- *  pass 1 and the threshold is set to 16.
+ * Limits the number of Outgoing Message Segments in flight at a time.
  *
- * Clk_Rst:        SRIO(0..1)_OMSG_SILO_THR        hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_OMSG_SILO_THR      hclk    hrst_n
  */
-union cvmx_sriox_omsg_silo_thr
-{
+union cvmx_sriox_omsg_silo_thr {
 	uint64_t u64;
-	struct cvmx_sriox_omsg_silo_thr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_omsg_silo_thr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t tot_silo                     : 5;  /**< Sets max number segments in flight for all
-                                                         controllers. */
+                                                         controllers.  Valid range is 0x01 .. 0x10 but
+                                                         lower values reduce bandwidth. */
 #else
 	uint64_t tot_silo                     : 5;
 	uint64_t reserved_5_63                : 59;
 #endif
 	} s;
 	struct cvmx_sriox_omsg_silo_thr_s     cn63xx;
+	struct cvmx_sriox_omsg_silo_thr_s     cn66xx;
 };
 typedef union cvmx_sriox_omsg_silo_thr cvmx_sriox_omsg_silo_thr_t;
 
@@ -2540,14 +2739,12 @@ typedef union cvmx_sriox_omsg_silo_thr cvmx_sriox_omsg_silo_thr_t;
  * silo. When fields in this CSR are set, SP candidate segments will match fewer silo entries and
  * can enter the silo more freely, probably providing better performance.
  *
- * Clk_Rst:        SRIO(0..1)_OMSG_SP_MR[0:1]      hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_OMSG_SP_MR[0:1]    hclk    hrst_n
  */
-union cvmx_sriox_omsg_sp_mrx
-{
+union cvmx_sriox_omsg_sp_mrx {
 	uint64_t u64;
-	struct cvmx_sriox_omsg_sp_mrx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_omsg_sp_mrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t xmbox_sp                     : 1;  /**< Controller X SP enable XMBOX SP
                                                          When set, the SP candidate message can only
@@ -2668,13 +2865,14 @@ union cvmx_sriox_omsg_sp_mrx
 	} s;
 	struct cvmx_sriox_omsg_sp_mrx_s       cn63xx;
 	struct cvmx_sriox_omsg_sp_mrx_s       cn63xxp1;
+	struct cvmx_sriox_omsg_sp_mrx_s       cn66xx;
 };
 typedef union cvmx_sriox_omsg_sp_mrx cvmx_sriox_omsg_sp_mrx_t;
 
 /**
  * cvmx_srio#_prio#_in_use
  *
- * SRIO_PRIO[0:3]_IN_USE = S2M PRIORITY FIFO IN USE COUNTS (Pass 2)
+ * SRIO_PRIO[0:3]_IN_USE = S2M PRIORITY FIFO IN USE COUNTS
  *
  * SRIO S2M Priority X FIFO Inuse counts
  *
@@ -2684,17 +2882,15 @@ typedef union cvmx_sriox_omsg_sp_mrx cvmx_sriox_omsg_sp_mrx_t;
  *  reallocated.  For example, if an S2M_TYPE is used N times in a DMA write operation and the DMA has
  *  completed.  The register corresponding to the RD/WR_PRIOR of the S2M_TYPE can be read to determine
  *  the START_CNT and then can be polled to see if the END_CNT equals the START_CNT or at least
- *  START_CNT+N.   These registers can be accessed regardless of the value of SRIO(0..1)_STATUS_REG.ACCESS
+ *  START_CNT+N.   These registers can be accessed regardless of the value of SRIO(0,2..3)_STATUS_REG.ACCESS
  *  but are reset by either the MAC or Core being reset.
  *
- * Clk_Rst:        SRIO(0..1)_PRIO[0:3]_IN_USE     sclk    srst_n, hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_PRIO[0:3]_IN_USE   sclk    srst_n, hrst_n
  */
-union cvmx_sriox_priox_in_use
-{
+union cvmx_sriox_priox_in_use {
 	uint64_t u64;
-	struct cvmx_sriox_priox_in_use_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_priox_in_use_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t end_cnt                      : 16; /**< Count of Packets with S2M_TYPES completed for this
                                                          Priority X FIFO */
@@ -2707,6 +2903,7 @@ union cvmx_sriox_priox_in_use
 #endif
 	} s;
 	struct cvmx_sriox_priox_in_use_s      cn63xx;
+	struct cvmx_sriox_priox_in_use_s      cn66xx;
 };
 typedef union cvmx_sriox_priox_in_use cvmx_sriox_priox_in_use_t;
 
@@ -2725,14 +2922,12 @@ typedef union cvmx_sriox_priox_in_use cvmx_sriox_priox_in_use_t;
  *  considered invalid.  When the FIFO is full an ERROR is automatically issued.  The RXBELL Interrupt
  *  can be used to detect posts to this FIFO.
  *
- * Clk_Rst:        SRIO(0..1)_RX_BELL      hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_RX_BELL    hclk    hrst_n
  */
-union cvmx_sriox_rx_bell
-{
+union cvmx_sriox_rx_bell {
 	uint64_t u64;
-	struct cvmx_sriox_rx_bell_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_rx_bell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t data                         : 16; /**< Information field from received doorbell */
 	uint64_t src_id                       : 16; /**< Doorbell Source Device ID[15:0] */
@@ -2757,6 +2952,7 @@ union cvmx_sriox_rx_bell
 	} s;
 	struct cvmx_sriox_rx_bell_s           cn63xx;
 	struct cvmx_sriox_rx_bell_s           cn63xxp1;
+	struct cvmx_sriox_rx_bell_s           cn66xx;
 };
 typedef union cvmx_sriox_rx_bell cvmx_sriox_rx_bell_t;
 
@@ -2770,17 +2966,15 @@ typedef union cvmx_sriox_rx_bell cvmx_sriox_rx_bell_t;
  * Notes:
  * This register contains the value of the sequence counter when the doorbell was received and a
  *  shadow copy of the Bell FIFO Count that can be read without emptying the FIFO.  This register must
- *  be read prior to SRIO(0..1)_RX_BELL to guarantee that the information corresponds to the correct
+ *  be read prior to SRIO(0,2..3)_RX_BELL to guarantee that the information corresponds to the correct
  *  doorbell.
  *
- * Clk_Rst:        SRIO(0..1)_RX_BELL_SEQ  hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_RX_BELL_SEQ        hclk    hrst_n
  */
-union cvmx_sriox_rx_bell_seq
-{
+union cvmx_sriox_rx_bell_seq {
 	uint64_t u64;
-	struct cvmx_sriox_rx_bell_seq_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_rx_bell_seq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t count                        : 8;  /**< RX Bell FIFO Count
                                                          Note:  Count must be > 0 for entry to be valid. */
@@ -2793,6 +2987,7 @@ union cvmx_sriox_rx_bell_seq
 	} s;
 	struct cvmx_sriox_rx_bell_seq_s       cn63xx;
 	struct cvmx_sriox_rx_bell_seq_s       cn63xxp1;
+	struct cvmx_sriox_rx_bell_seq_s       cn66xx;
 };
 typedef union cvmx_sriox_rx_bell_seq cvmx_sriox_rx_bell_seq_t;
 
@@ -2805,18 +3000,16 @@ typedef union cvmx_sriox_rx_bell_seq cvmx_sriox_rx_bell_seq_t;
  *
  * Notes:
  * Debug Register specifying the number of credits/responses currently in use for Inbound Traffic.
- *  The maximum value for COMP, N_POST and POST is set in SRIO(0..1)_TLP_CREDITS.  When all inbound traffic
+ *  The maximum value for COMP, N_POST and POST is set in SRIO(0,2..3)_TLP_CREDITS.  When all inbound traffic
  *  has stopped the values should eventually return to the maximum values.  The RTN_PR[3:1] entry
  *  counts should eventually return to the reset values.
  *
- * Clk_Rst:        SRIO(0..1)_RX_STATUS    hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_RX_STATUS  hclk    hrst_n
  */
-union cvmx_sriox_rx_status
-{
+union cvmx_sriox_rx_status {
 	uint64_t u64;
-	struct cvmx_sriox_rx_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_rx_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t rtn_pr3                      : 8;  /**< Number of pending Priority 3 Response Entries. */
 	uint64_t rtn_pr2                      : 8;  /**< Number of pending Priority 2 Response Entries. */
 	uint64_t rtn_pr1                      : 8;  /**< Number of pending Priority 1 Response Entries. */
@@ -2840,6 +3033,7 @@ union cvmx_sriox_rx_status
 	} s;
 	struct cvmx_sriox_rx_status_s         cn63xx;
 	struct cvmx_sriox_rx_status_s         cn63xxp1;
+	struct cvmx_sriox_rx_status_s         cn66xx;
 };
 typedef union cvmx_sriox_rx_status cvmx_sriox_rx_status_t;
 
@@ -2861,14 +3055,12 @@ typedef union cvmx_sriox_rx_status cvmx_sriox_rx_status_t;
  *    TYPEIDX[2] = MACADD[50]
  *    TYPEIDX[3] = MACADD[59]
  *
- * Clk_Rst:        SRIO(0..1)_S2M_TYPE[0:15]       hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_S2M_TYPE[0:15]     hclk    hrst_n
  */
-union cvmx_sriox_s2m_typex
-{
+union cvmx_sriox_s2m_typex {
 	uint64_t u64;
-	struct cvmx_sriox_s2m_typex_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_s2m_typex_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t wr_op                        : 3;  /**< sRIO operation for SLI/DPI writes
 
@@ -3244,6 +3436,7 @@ union cvmx_sriox_s2m_typex
 	} s;
 	struct cvmx_sriox_s2m_typex_s         cn63xx;
 	struct cvmx_sriox_s2m_typex_s         cn63xxp1;
+	struct cvmx_sriox_s2m_typex_s         cn66xx;
 };
 typedef union cvmx_sriox_s2m_typex cvmx_sriox_s2m_typex_t;
 
@@ -3258,14 +3451,12 @@ typedef union cvmx_sriox_s2m_typex cvmx_sriox_s2m_typex_t;
  * This register contains the current value of the sequence counter.  This counter increments every
  *  time a doorbell or the first segment of a message is accepted.
  *
- * Clk_Rst:        SRIO(0..1)_SEQ  hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_SEQ        hclk    hrst_n
  */
-union cvmx_sriox_seq
-{
+union cvmx_sriox_seq {
 	uint64_t u64;
-	struct cvmx_sriox_seq_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_seq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t seq                          : 32; /**< 32-bit Sequence \# */
 #else
@@ -3275,13 +3466,17 @@ union cvmx_sriox_seq
 	} s;
 	struct cvmx_sriox_seq_s               cn63xx;
 	struct cvmx_sriox_seq_s               cn63xxp1;
+	struct cvmx_sriox_seq_s               cn66xx;
 };
 typedef union cvmx_sriox_seq cvmx_sriox_seq_t;
 
 /**
  * cvmx_srio#_status_reg
  *
- * SRIO_STATUS_REG = SRIO Status Register
+ * 13e20 reserved
+ *
+ *
+ *                  SRIO_STATUS_REG = SRIO Status Register
  *
  * General status of the SRIO.
  *
@@ -3291,14 +3486,12 @@ typedef union cvmx_sriox_seq cvmx_sriox_seq_t;
  *  be accessed while the ACCESS bit is zero (see individual registers for details), the majority of
  *  SRIO registers and all the SRIOMAINT registers can be used only when the ACCESS bit is asserted.
  *
- * Clk_Rst:        SRIO(0..1)_STATUS_REG   sclk    srst_n
+ * Clk_Rst:        SRIO(0,2..3)_STATUS_REG sclk    srst_n
  */
-union cvmx_sriox_status_reg
-{
+union cvmx_sriox_status_reg {
 	uint64_t u64;
-	struct cvmx_sriox_status_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_status_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t access                       : 1;  /**< SRIO and SRIOMAINT Register Access.
                                                          0 - Register Access Disabled.
@@ -3314,6 +3507,7 @@ union cvmx_sriox_status_reg
 	} s;
 	struct cvmx_sriox_status_reg_s        cn63xx;
 	struct cvmx_sriox_status_reg_s        cn63xxp1;
+	struct cvmx_sriox_status_reg_s        cn66xx;
 };
 typedef union cvmx_sriox_status_reg cvmx_sriox_status_reg_t;
 
@@ -3328,14 +3522,12 @@ typedef union cvmx_sriox_status_reg cvmx_sriox_status_reg_t;
  * This register is used to show the state of the internal transaction tags and provides a manual
  *  reset of the outgoing tags.
  *
- * Clk_Rst:        SRIO(0..1)_TAG_CTRL     hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_TAG_CTRL   hclk    hrst_n
  */
-union cvmx_sriox_tag_ctrl
-{
+union cvmx_sriox_tag_ctrl {
 	uint64_t u64;
-	struct cvmx_sriox_tag_ctrl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_tag_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t o_clr                        : 1;  /**< Manual OTAG Clear.  This bit manually resets the
                                                          number of OTAGs back to 16 and loses track of any
@@ -3366,6 +3558,7 @@ union cvmx_sriox_tag_ctrl
 	} s;
 	struct cvmx_sriox_tag_ctrl_s          cn63xx;
 	struct cvmx_sriox_tag_ctrl_s          cn63xxp1;
+	struct cvmx_sriox_tag_ctrl_s          cn66xx;
 };
 typedef union cvmx_sriox_tag_ctrl cvmx_sriox_tag_ctrl_t;
 
@@ -3378,15 +3571,25 @@ typedef union cvmx_sriox_tag_ctrl cvmx_sriox_tag_ctrl_t;
  *
  * Notes:
  * Specifies the number of maximum credits the SRIO can use for incoming Commands and Messages.
- *
- * Clk_Rst:        SRIO(0..1)_TLP_CREDITS  hclk    hrst_n
+ *  Reset values for COMP, N_POST and POST credits are based on the number of lanes allocated by the
+ *  QLM Configuration to the SRIO MAC and whether QLM1 is used by PCIe.  If SRIO MACs are unused then
+ *  credits may be allocated to other MACs under some circumstances.  The following table shows the
+ *  reset values for COMP/N_POST/POST:
+ *                     QLM0_CFG    QLM1_CFG    SRIO0       SRIO2      SRIO3
+ *                    ======================================================
+ *                        PEM        Any       0/0/0       0/0/0      0/0/0
+ *                      SRIO x4      Any     128/16/128    0/0/0      0/0/0
+ *                      SRIO x2      PEM      64/8/64     64/8/64     0/0/0
+ *                      SRIO x2    non-PEM   128/16/128  128/16/128   0/0/0
+ *                      SRIO x1      PEM      42/5/42     42/5/42    42/5/42
+ *                      SRIO x1    non-PEM    64/8/64     64/8/64    64/8/64
+ *
+ * Clk_Rst:        SRIO(0,2..3)_TLP_CREDITS        hclk    hrst_n
  */
-union cvmx_sriox_tlp_credits
-{
+union cvmx_sriox_tlp_credits {
 	uint64_t u64;
-	struct cvmx_sriox_tlp_credits_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_tlp_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_28_63               : 36;
 	uint64_t mbox                         : 4;  /**< Credits for Mailbox Data used in M2S.
                                                          Legal values are 0x2 to 0x8. */
@@ -3408,6 +3611,7 @@ union cvmx_sriox_tlp_credits
 	} s;
 	struct cvmx_sriox_tlp_credits_s       cn63xx;
 	struct cvmx_sriox_tlp_credits_s       cn63xxp1;
+	struct cvmx_sriox_tlp_credits_s       cn66xx;
 };
 typedef union cvmx_sriox_tlp_credits cvmx_sriox_tlp_credits_t;
 
@@ -3425,14 +3629,12 @@ typedef union cvmx_sriox_tlp_credits cvmx_sriox_tlp_credits_t;
  *  Doorbell operation has been acknowledged.  A write to this register while the PENDING bit is set
  *  should be avoided as it will stall the RSL until the first Doorbell has completed.
  *
- * Clk_Rst:        SRIO(0..1)_TX_BELL      hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_TX_BELL    hclk    hrst_n
  */
-union cvmx_sriox_tx_bell
-{
+union cvmx_sriox_tx_bell {
 	uint64_t u64;
-	struct cvmx_sriox_tx_bell_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_tx_bell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t data                         : 16; /**< Information field for next doorbell operation */
 	uint64_t dest_id                      : 16; /**< Doorbell Destination Device ID[15:0] */
@@ -3458,6 +3660,7 @@ union cvmx_sriox_tx_bell
 	} s;
 	struct cvmx_sriox_tx_bell_s           cn63xx;
 	struct cvmx_sriox_tx_bell_s           cn63xxp1;
+	struct cvmx_sriox_tx_bell_s           cn66xx;
 };
 typedef union cvmx_sriox_tx_bell cvmx_sriox_tx_bell_t;
 
@@ -3469,19 +3672,17 @@ typedef union cvmx_sriox_tx_bell cvmx_sriox_tx_bell_t;
  * The SRIO Outgoing (TX) Doorbell Interrupt Information
  *
  * Notes:
- * This register is only updated if the BELL_ERR bit is clear in SRIO(0..1)_INT_REG.  This register
+ * This register is only updated if the BELL_ERR bit is clear in SRIO(0,2..3)_INT_REG.  This register
  *  displays SRIO Information, Device ID, Transaction Type and Priority of the Doorbell Transaction
  *  that generated the BELL_ERR Interrupt.  The register includes either a RETRY, ERROR or TIMEOUT
  *  Status.
  *
- * Clk_Rst:        SRIO(0..1)_TX_BELL_INFO hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_TX_BELL_INFO       hclk    hrst_n
  */
-union cvmx_sriox_tx_bell_info
-{
+union cvmx_sriox_tx_bell_info {
 	uint64_t u64;
-	struct cvmx_sriox_tx_bell_info_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_tx_bell_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t data                         : 16; /**< Information field from last doorbell operation */
 	uint64_t dest_id                      : 16; /**< Doorbell Destination Device ID[15:0] */
@@ -3509,6 +3710,7 @@ union cvmx_sriox_tx_bell_info
 	} s;
 	struct cvmx_sriox_tx_bell_info_s      cn63xx;
 	struct cvmx_sriox_tx_bell_info_s      cn63xxp1;
+	struct cvmx_sriox_tx_bell_info_s      cn66xx;
 };
 typedef union cvmx_sriox_tx_bell_info cvmx_sriox_tx_bell_info_t;
 
@@ -3520,21 +3722,17 @@ typedef union cvmx_sriox_tx_bell_info cvmx_sriox_tx_bell_info_t;
  * The SRIO Transmit Control
  *
  * Notes:
- * This register is used to control SRIO Outgoing Packet Allocation.  TX_TH[2:0] set the thresholds
- *  to allow each priority traffic to be queued for transmission.  8 TX Buffer are available.  A
- *  threshold greater than 8 stops all traffic on that priority and should be avoided.  TAG_TH[2:0]
- *  set the thresholds to allow priority traffic requiring responses to be queued based on the number
- *  of outgoing tags (TIDs) available.  16 Tags are available.  If a priority is blocked for lack of
- *  tags then all lower priority packets are also blocked irregardless of whether they require tags.
- *
- * Clk_Rst:        SRIO(0..1)_TX_CTRL      hclk    hrst_n
+ * This register is used to control SRIO Outgoing Packet Allocation.  TAG_TH[2:0] set the thresholds
+ *  to allow priority traffic requiring responses to be queued based on the number of outgoing tags
+ *  (TIDs) available.  16 Tags are available.  If a priority is blocked for lack of tags then all
+ *  lower priority packets are also blocked irregardless of whether they require tags.
+ *
+ * Clk_Rst:        SRIO(0,2..3)_TX_CTRL    hclk    hrst_n
  */
-union cvmx_sriox_tx_ctrl
-{
+union cvmx_sriox_tx_ctrl {
 	uint64_t u64;
-	struct cvmx_sriox_tx_ctrl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_tx_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_53_63               : 11;
 	uint64_t tag_th2                      : 5;  /**< Sets threshold for minimum number of OTAGs
                                                          required before a packet of priority 2 requiring a
@@ -3555,23 +3753,11 @@ union cvmx_sriox_tx_ctrl
                                                          Generally, TAG_TH0 must be > TAG_TH1 to leave OTAGs
                                                          for outgoing priority 1 or 2 (or 3) requests. */
 	uint64_t reserved_20_31               : 12;
-	uint64_t tx_th2                       : 4;  /**< Sets threshold for minimum number of TX buffers
-                                                         before a Priority 2 Packet will be queued for
-                                                         transmission. (Max 8)
-                                                         Generally, TX_TH2 must be > 0 to leave space for
-                                                         outgoing priority 3 packets. */
+	uint64_t tx_th2                       : 4;  /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */
 	uint64_t reserved_12_15               : 4;
-	uint64_t tx_th1                       : 4;  /**< Sets threshold for minimum number of TX buffers
-                                                         before a Priority 1 Packet will be queued for
-                                                         transmission. (Max 8)
-                                                         Generally, TX_TH1 must be > TX_TH2 to leave space
-                                                         for outgoing priority 2 or 3 packets. */
+	uint64_t tx_th1                       : 4;  /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */
 	uint64_t reserved_4_7                 : 4;
-	uint64_t tx_th0                       : 4;  /**< Sets threshold for minimum number of TX buffers
-                                                         before a Priority 0 Packet will be queued for
-                                                         transmission. (Max 8)
-                                                         Generally, TX_TH0 must be > TX_TH1 to leave space
-                                                         for outgoing priority 1 or 2 or 3 packets. */
+	uint64_t tx_th0                       : 4;  /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */
 #else
 	uint64_t tx_th0                       : 4;
 	uint64_t reserved_4_7                 : 4;
@@ -3589,28 +3775,28 @@ union cvmx_sriox_tx_ctrl
 	} s;
 	struct cvmx_sriox_tx_ctrl_s           cn63xx;
 	struct cvmx_sriox_tx_ctrl_s           cn63xxp1;
+	struct cvmx_sriox_tx_ctrl_s           cn66xx;
 };
 typedef union cvmx_sriox_tx_ctrl cvmx_sriox_tx_ctrl_t;
 
 /**
  * cvmx_srio#_tx_emphasis
  *
- * SRIO_TX_EMPHASIS = SRIO TX Lane Emphasis (Pass 2)
+ * SRIO_TX_EMPHASIS = SRIO TX Lane Emphasis
  *
  * Controls TX Emphasis used by the SRIO SERDES
  *
  * Notes:
  * This controls the emphasis value used by the SRIO SERDES.  This register is only reset during COLD
- *  boot and may be modified regardless of the value in SRIO(0..1)_STATUS_REG.ACCESS.
+ *  boot and may be modified regardless of the value in SRIO(0,2..3)_STATUS_REG.ACCESS.  This register is not
+ *  connected to the QLM and thus has no effect.  It should not be included in the documentation.
  *
- * Clk_Rst:        SRIO(0..1)_TX_EMPHASIS  sclk    srst_cold_n
+ * Clk_Rst:        SRIO(0,2..3)_TX_EMPHASIS        sclk    srst_cold_n
  */
-union cvmx_sriox_tx_emphasis
-{
+union cvmx_sriox_tx_emphasis {
 	uint64_t u64;
-	struct cvmx_sriox_tx_emphasis_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_tx_emphasis_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t emph                         : 4;  /**< Emphasis Value used for all lanes.  Default value
                                                          is 0x0 for 1.25G b/s and 0xA for all other rates. */
@@ -3620,6 +3806,7 @@ union cvmx_sriox_tx_emphasis
 #endif
 	} s;
 	struct cvmx_sriox_tx_emphasis_s       cn63xx;
+	struct cvmx_sriox_tx_emphasis_s       cn66xx;
 };
 typedef union cvmx_sriox_tx_emphasis cvmx_sriox_tx_emphasis_t;
 
@@ -3634,14 +3821,12 @@ typedef union cvmx_sriox_tx_emphasis cvmx_sriox_tx_emphasis_t;
  * Debug Register specifying the number of credits/ops currently in use for Outbound Traffic.
  *  When all outbound traffic has stopped the values should eventually return to the reset values.
  *
- * Clk_Rst:        SRIO(0..1)_TX_STATUS    hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_TX_STATUS  hclk    hrst_n
  */
-union cvmx_sriox_tx_status
-{
+union cvmx_sriox_tx_status {
 	uint64_t u64;
-	struct cvmx_sriox_tx_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_tx_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t s2m_pr3                      : 8;  /**< Number of pending S2M Priority 3 Entries. */
 	uint64_t s2m_pr2                      : 8;  /**< Number of pending S2M Priority 2 Entries. */
@@ -3657,32 +3842,31 @@ union cvmx_sriox_tx_status
 	} s;
 	struct cvmx_sriox_tx_status_s         cn63xx;
 	struct cvmx_sriox_tx_status_s         cn63xxp1;
+	struct cvmx_sriox_tx_status_s         cn66xx;
 };
 typedef union cvmx_sriox_tx_status cvmx_sriox_tx_status_t;
 
 /**
  * cvmx_srio#_wr_done_counts
  *
- * SRIO_WR_DONE_COUNTS = SRIO Outgoing Write Done Counts (Pass 2)
+ * SRIO_WR_DONE_COUNTS = SRIO Outgoing Write Done Counts
  *
  * The SRIO Outbound Write Done Counts
  *
  * Notes:
  * This register shows the number of successful and unsuccessful NwriteRs issued through this MAC.
  *  These count only considers the last NwriteR generated by each Store Instruction.  If any NwriteR
- *  in the series receives an ERROR Status then it is reported in SRIOMAINT(0..1)_ERB_LT_ERR_DET.IO_ERR.
+ *  in the series receives an ERROR Status then it is reported in SRIOMAINT(0,2..3)_ERB_LT_ERR_DET.IO_ERR.
  *  If any NwriteR does not receive a response within the timeout period then it is reported in
- *  SRIOMAINT(0..1)_ERB_LT_ERR_DET.PKT_TOUT.  Only errors on the last NwriteR's are counted as BAD.  This
+ *  SRIOMAINT(0,2..3)_ERB_LT_ERR_DET.PKT_TOUT.  Only errors on the last NwriteR's are counted as BAD.  This
  *  register is typically not written while Outbound SRIO Memory traffic is enabled.
  *
- * Clk_Rst:        SRIO(0..1)_WR_DONE_COUNTS       hclk    hrst_n
+ * Clk_Rst:        SRIO(0,2..3)_WR_DONE_COUNTS     hclk    hrst_n
  */
-union cvmx_sriox_wr_done_counts
-{
+union cvmx_sriox_wr_done_counts {
 	uint64_t u64;
-	struct cvmx_sriox_wr_done_counts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_sriox_wr_done_counts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t bad                          : 16; /**< Count of the final outbound NwriteR in the series
                                                          associated with a Store Operation that have timed
@@ -3697,6 +3881,7 @@ union cvmx_sriox_wr_done_counts
 #endif
 	} s;
 	struct cvmx_sriox_wr_done_counts_s    cn63xx;
+	struct cvmx_sriox_wr_done_counts_s    cn66xx;
 };
 typedef union cvmx_sriox_wr_done_counts cvmx_sriox_wr_done_counts_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-srxx-defs.h b/sys/contrib/octeon-sdk/cvmx-srxx-defs.h
index 75bfeeb..48adf21 100644
--- a/sys/contrib/octeon-sdk/cvmx-srxx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-srxx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_SRXX_TYPEDEFS_H__
-#define __CVMX_SRXX_TYPEDEFS_H__
+#ifndef __CVMX_SRXX_DEFS_H__
+#define __CVMX_SRXX_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_SRXX_COM_CTL(unsigned long block_id)
@@ -137,12 +137,10 @@ static inline uint64_t CVMX_SRXX_SW_TICK_DAT(unsigned long block_id)
  * setup before writing the Interface enable (INF_EN) and Status channel
  * enabled (ST_EN) asserted.
  */
-union cvmx_srxx_com_ctl
-{
+union cvmx_srxx_com_ctl {
 	uint64_t u64;
-	struct cvmx_srxx_com_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_srxx_com_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t prts                         : 4;  /**< Number of ports in the receiver (write: ports - 1)
                                                          - 0:  1 port
@@ -194,12 +192,10 @@ typedef union cvmx_srxx_com_ctl cvmx_srxx_com_ctl_t;
  * Watcher will never find a cycle where the TPA for the selected port is
  * deasserted in order to increment its count.
  */
-union cvmx_srxx_ign_rx_full
-{
+union cvmx_srxx_ign_rx_full {
 	uint64_t u64;
-	struct cvmx_srxx_ign_rx_full_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_srxx_ign_rx_full_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t ignore                       : 16; /**< This port should ignore backpressure hints from
                                                           GMX when the RX FIFO fills up
@@ -243,12 +239,10 @@ typedef union cvmx_srxx_ign_rx_full cvmx_srxx_ign_rx_full_t;
  *          completely setup before writing the Interface enable (INF_EN) and
  *          Status channel enabled (ST_EN) asserted.
  */
-union cvmx_srxx_spi4_calx
-{
+union cvmx_srxx_spi4_calx {
 	uint64_t u64;
-	struct cvmx_srxx_spi4_calx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_srxx_spi4_calx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t oddpar                       : 1;  /**< Odd parity over SRX_SPI4_CAL[15:0]
                                                          (^SRX_SPI4_CAL[16:0] === 1'b1)                  |   $NS       NS */
@@ -286,12 +280,10 @@ typedef union cvmx_srxx_spi4_calx cvmx_srxx_spi4_calx_t;
  *
  * Current rev only supports LVTTL status IO
  */
-union cvmx_srxx_spi4_stat
-{
+union cvmx_srxx_spi4_stat {
 	uint64_t u64;
-	struct cvmx_srxx_spi4_stat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_srxx_spi4_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t m                            : 8;  /**< CALENDAR_M (from spi4.2 spec) */
 	uint64_t reserved_7_7                 : 1;
@@ -316,12 +308,10 @@ typedef union cvmx_srxx_spi4_stat cvmx_srxx_spi4_stat_t;
  * SRX_SW_TICK_CTL - Create a software tick of Spi4 data.  A write to this register will create a data tick.
  *
  */
-union cvmx_srxx_sw_tick_ctl
-{
+union cvmx_srxx_sw_tick_ctl {
 	uint64_t u64;
-	struct cvmx_srxx_sw_tick_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_srxx_sw_tick_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t eop                          : 1;  /**< SW Tick EOP
                                                          (PASS3 only) */
@@ -354,12 +344,10 @@ typedef union cvmx_srxx_sw_tick_ctl cvmx_srxx_sw_tick_ctl_t;
  * SRX_SW_TICK_DAT - Create a software tick of Spi4 data
  *
  */
-union cvmx_srxx_sw_tick_dat
-{
+union cvmx_srxx_sw_tick_dat {
 	uint64_t u64;
-	struct cvmx_srxx_sw_tick_dat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_srxx_sw_tick_dat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t dat                          : 64; /**< Data tick when SRX_SW_TICK_CTL is written
                                                          (PASS3 only) */
 #else
diff --git a/sys/contrib/octeon-sdk/cvmx-sso-defs.h b/sys/contrib/octeon-sdk/cvmx-sso-defs.h
new file mode 100644
index 0000000..611df6e
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-sso-defs.h
@@ -0,0 +1,2194 @@
+/***********************license start***************
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-sso-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon sso.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_SSO_DEFS_H__
+#define __CVMX_SSO_DEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_ACTIVE_CYCLES CVMX_SSO_ACTIVE_CYCLES_FUNC()
+static inline uint64_t CVMX_SSO_ACTIVE_CYCLES_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_ACTIVE_CYCLES not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00016700000010E8ull);
+}
+#else
+#define CVMX_SSO_ACTIVE_CYCLES (CVMX_ADD_IO_SEG(0x00016700000010E8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_BIST_STAT CVMX_SSO_BIST_STAT_FUNC()
+static inline uint64_t CVMX_SSO_BIST_STAT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_BIST_STAT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000001078ull);
+}
+#else
+#define CVMX_SSO_BIST_STAT (CVMX_ADD_IO_SEG(0x0001670000001078ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_CFG CVMX_SSO_CFG_FUNC()
+static inline uint64_t CVMX_SSO_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000001088ull);
+}
+#else
+#define CVMX_SSO_CFG (CVMX_ADD_IO_SEG(0x0001670000001088ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_DS_PC CVMX_SSO_DS_PC_FUNC()
+static inline uint64_t CVMX_SSO_DS_PC_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_DS_PC not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000001070ull);
+}
+#else
+#define CVMX_SSO_DS_PC (CVMX_ADD_IO_SEG(0x0001670000001070ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_ERR CVMX_SSO_ERR_FUNC()
+static inline uint64_t CVMX_SSO_ERR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_ERR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000001038ull);
+}
+#else
+#define CVMX_SSO_ERR (CVMX_ADD_IO_SEG(0x0001670000001038ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_ERR_ENB CVMX_SSO_ERR_ENB_FUNC()
+static inline uint64_t CVMX_SSO_ERR_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_ERR_ENB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000001030ull);
+}
+#else
+#define CVMX_SSO_ERR_ENB (CVMX_ADD_IO_SEG(0x0001670000001030ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_FIDX_ECC_CTL CVMX_SSO_FIDX_ECC_CTL_FUNC()
+static inline uint64_t CVMX_SSO_FIDX_ECC_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_FIDX_ECC_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00016700000010D0ull);
+}
+#else
+#define CVMX_SSO_FIDX_ECC_CTL (CVMX_ADD_IO_SEG(0x00016700000010D0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_FIDX_ECC_ST CVMX_SSO_FIDX_ECC_ST_FUNC()
+static inline uint64_t CVMX_SSO_FIDX_ECC_ST_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_FIDX_ECC_ST not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00016700000010D8ull);
+}
+#else
+#define CVMX_SSO_FIDX_ECC_ST (CVMX_ADD_IO_SEG(0x00016700000010D8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_FPAGE_CNT CVMX_SSO_FPAGE_CNT_FUNC()
+static inline uint64_t CVMX_SSO_FPAGE_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_FPAGE_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000001090ull);
+}
+#else
+#define CVMX_SSO_FPAGE_CNT (CVMX_ADD_IO_SEG(0x0001670000001090ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_GWE_CFG CVMX_SSO_GWE_CFG_FUNC()
+static inline uint64_t CVMX_SSO_GWE_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_GWE_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000001098ull);
+}
+#else
+#define CVMX_SSO_GWE_CFG (CVMX_ADD_IO_SEG(0x0001670000001098ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_IDX_ECC_CTL CVMX_SSO_IDX_ECC_CTL_FUNC()
+static inline uint64_t CVMX_SSO_IDX_ECC_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_IDX_ECC_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00016700000010C0ull);
+}
+#else
+#define CVMX_SSO_IDX_ECC_CTL (CVMX_ADD_IO_SEG(0x00016700000010C0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_IDX_ECC_ST CVMX_SSO_IDX_ECC_ST_FUNC()
+static inline uint64_t CVMX_SSO_IDX_ECC_ST_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_IDX_ECC_ST not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00016700000010C8ull);
+}
+#else
+#define CVMX_SSO_IDX_ECC_ST (CVMX_ADD_IO_SEG(0x00016700000010C8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SSO_IQ_CNTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_SSO_IQ_CNTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001670000009000ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_SSO_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000009000ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_IQ_COM_CNT CVMX_SSO_IQ_COM_CNT_FUNC()
+static inline uint64_t CVMX_SSO_IQ_COM_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_IQ_COM_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000001058ull);
+}
+#else
+#define CVMX_SSO_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000001058ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_IQ_INT CVMX_SSO_IQ_INT_FUNC()
+static inline uint64_t CVMX_SSO_IQ_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_IQ_INT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000001048ull);
+}
+#else
+#define CVMX_SSO_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000001048ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_IQ_INT_EN CVMX_SSO_IQ_INT_EN_FUNC()
+static inline uint64_t CVMX_SSO_IQ_INT_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_IQ_INT_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000001050ull);
+}
+#else
+#define CVMX_SSO_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000001050ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SSO_IQ_THRX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_SSO_IQ_THRX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x000167000000A000ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_SSO_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x000167000000A000ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_NOS_CNT CVMX_SSO_NOS_CNT_FUNC()
+static inline uint64_t CVMX_SSO_NOS_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_NOS_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000001040ull);
+}
+#else
+#define CVMX_SSO_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000001040ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_NW_TIM CVMX_SSO_NW_TIM_FUNC()
+static inline uint64_t CVMX_SSO_NW_TIM_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_NW_TIM not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000001028ull);
+}
+#else
+#define CVMX_SSO_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000001028ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_OTH_ECC_CTL CVMX_SSO_OTH_ECC_CTL_FUNC()
+static inline uint64_t CVMX_SSO_OTH_ECC_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_OTH_ECC_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00016700000010B0ull);
+}
+#else
+#define CVMX_SSO_OTH_ECC_CTL (CVMX_ADD_IO_SEG(0x00016700000010B0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_OTH_ECC_ST CVMX_SSO_OTH_ECC_ST_FUNC()
+static inline uint64_t CVMX_SSO_OTH_ECC_ST_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_OTH_ECC_ST not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00016700000010B8ull);
+}
+#else
+#define CVMX_SSO_OTH_ECC_ST (CVMX_ADD_IO_SEG(0x00016700000010B8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_PND_ECC_CTL CVMX_SSO_PND_ECC_CTL_FUNC()
+static inline uint64_t CVMX_SSO_PND_ECC_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_PND_ECC_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00016700000010A0ull);
+}
+#else
+#define CVMX_SSO_PND_ECC_CTL (CVMX_ADD_IO_SEG(0x00016700000010A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_PND_ECC_ST CVMX_SSO_PND_ECC_ST_FUNC()
+static inline uint64_t CVMX_SSO_PND_ECC_ST_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_PND_ECC_ST not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00016700000010A8ull);
+}
+#else
+#define CVMX_SSO_PND_ECC_ST (CVMX_ADD_IO_SEG(0x00016700000010A8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SSO_PPX_GRP_MSK(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_SSO_PPX_GRP_MSK(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001670000006000ull) + ((offset) & 31) * 8;
+}
+#else
+#define CVMX_SSO_PPX_GRP_MSK(offset) (CVMX_ADD_IO_SEG(0x0001670000006000ull) + ((offset) & 31) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SSO_PPX_QOS_PRI(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_SSO_PPX_QOS_PRI(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001670000003000ull) + ((offset) & 31) * 8;
+}
+#else
+#define CVMX_SSO_PPX_QOS_PRI(offset) (CVMX_ADD_IO_SEG(0x0001670000003000ull) + ((offset) & 31) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_PP_STRICT CVMX_SSO_PP_STRICT_FUNC()
+static inline uint64_t CVMX_SSO_PP_STRICT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_PP_STRICT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00016700000010E0ull);
+}
+#else
+#define CVMX_SSO_PP_STRICT (CVMX_ADD_IO_SEG(0x00016700000010E0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SSO_QOSX_RND(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_SSO_QOSX_RND(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001670000002000ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_SSO_QOSX_RND(offset) (CVMX_ADD_IO_SEG(0x0001670000002000ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SSO_QOS_THRX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_SSO_QOS_THRX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x000167000000B000ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_SSO_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x000167000000B000ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_QOS_WE CVMX_SSO_QOS_WE_FUNC()
+static inline uint64_t CVMX_SSO_QOS_WE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_QOS_WE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000001080ull);
+}
+#else
+#define CVMX_SSO_QOS_WE (CVMX_ADD_IO_SEG(0x0001670000001080ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_RESET CVMX_SSO_RESET_FUNC()
+static inline uint64_t CVMX_SSO_RESET_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_RESET not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00016700000010F0ull);
+}
+#else
+#define CVMX_SSO_RESET (CVMX_ADD_IO_SEG(0x00016700000010F0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SSO_RWQ_HEAD_PTRX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_SSO_RWQ_HEAD_PTRX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x000167000000C000ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_SSO_RWQ_HEAD_PTRX(offset) (CVMX_ADD_IO_SEG(0x000167000000C000ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_RWQ_POP_FPTR CVMX_SSO_RWQ_POP_FPTR_FUNC()
+static inline uint64_t CVMX_SSO_RWQ_POP_FPTR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_RWQ_POP_FPTR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x000167000000C408ull);
+}
+#else
+#define CVMX_SSO_RWQ_POP_FPTR (CVMX_ADD_IO_SEG(0x000167000000C408ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_RWQ_PSH_FPTR CVMX_SSO_RWQ_PSH_FPTR_FUNC()
+static inline uint64_t CVMX_SSO_RWQ_PSH_FPTR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_RWQ_PSH_FPTR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x000167000000C400ull);
+}
+#else
+#define CVMX_SSO_RWQ_PSH_FPTR (CVMX_ADD_IO_SEG(0x000167000000C400ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SSO_RWQ_TAIL_PTRX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_SSO_RWQ_TAIL_PTRX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x000167000000C200ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_SSO_RWQ_TAIL_PTRX(offset) (CVMX_ADD_IO_SEG(0x000167000000C200ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_TS_PC CVMX_SSO_TS_PC_FUNC()
+static inline uint64_t CVMX_SSO_TS_PC_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_TS_PC not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000001068ull);
+}
+#else
+#define CVMX_SSO_TS_PC (CVMX_ADD_IO_SEG(0x0001670000001068ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_WA_COM_PC CVMX_SSO_WA_COM_PC_FUNC()
+static inline uint64_t CVMX_SSO_WA_COM_PC_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_WA_COM_PC not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000001060ull);
+}
+#else
+#define CVMX_SSO_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000001060ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SSO_WA_PCX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_SSO_WA_PCX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001670000005000ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_SSO_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000005000ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_WQ_INT CVMX_SSO_WQ_INT_FUNC()
+static inline uint64_t CVMX_SSO_WQ_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_WQ_INT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000001000ull);
+}
+#else
+#define CVMX_SSO_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000001000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SSO_WQ_INT_CNTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_SSO_WQ_INT_CNTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001670000008000ull) + ((offset) & 63) * 8;
+}
+#else
+#define CVMX_SSO_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000008000ull) + ((offset) & 63) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_WQ_INT_PC CVMX_SSO_WQ_INT_PC_FUNC()
+static inline uint64_t CVMX_SSO_WQ_INT_PC_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_WQ_INT_PC not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000001020ull);
+}
+#else
+#define CVMX_SSO_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000001020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SSO_WQ_INT_THRX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_SSO_WQ_INT_THRX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001670000007000ull) + ((offset) & 63) * 8;
+}
+#else
+#define CVMX_SSO_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000007000ull) + ((offset) & 63) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SSO_WQ_IQ_DIS CVMX_SSO_WQ_IQ_DIS_FUNC()
+static inline uint64_t CVMX_SSO_WQ_IQ_DIS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_SSO_WQ_IQ_DIS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000001010ull);
+}
+#else
+#define CVMX_SSO_WQ_IQ_DIS (CVMX_ADD_IO_SEG(0x0001670000001010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SSO_WS_PCX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_SSO_WS_PCX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001670000004000ull) + ((offset) & 63) * 8;
+}
+#else
+#define CVMX_SSO_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000004000ull) + ((offset) & 63) * 8)
+#endif
+
+/**
+ * cvmx_sso_active_cycles
+ *
+ * SSO_ACTIVE_CYCLES = SSO cycles SSO active
+ *
+ * This register counts every sclk cycle that the SSO clocks are active.
+ * **NOTE: Added in pass 2.0
+ */
+union cvmx_sso_active_cycles {
+	uint64_t u64;
+	struct cvmx_sso_active_cycles_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t act_cyc                      : 64; /**< Counts number of active cycles. */
+#else
+	uint64_t act_cyc                      : 64;
+#endif
+	} s;
+	struct cvmx_sso_active_cycles_s       cn68xx;
+};
+typedef union cvmx_sso_active_cycles cvmx_sso_active_cycles_t;
+
+/**
+ * cvmx_sso_bist_stat
+ *
+ * SSO_BIST_STAT = SSO BIST Status Register
+ *
+ * Contains the BIST status for the SSO memories ('0' = pass, '1' = fail).
+ * Note that PP BIST status is not reported here as it was in previous designs.
+ *
+ *   There may be more for DDR interface buffers.
+ *   It's possible that a RAM will be used for SSO_PP_QOS_RND.
+ */
+union cvmx_sso_bist_stat {
+	uint64_t u64;
+	struct cvmx_sso_bist_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_62_63               : 2;
+	uint64_t odu_pref                     : 2;  /**< ODU Prefetch memory BIST status */
+	uint64_t reserved_54_59               : 6;
+	uint64_t fptr                         : 2;  /**< FPTR memory BIST status */
+	uint64_t reserved_45_51               : 7;
+	uint64_t rwo_dat                      : 1;  /**< RWO_DAT memory BIST status */
+	uint64_t rwo                          : 2;  /**< RWO memory BIST status */
+	uint64_t reserved_35_41               : 7;
+	uint64_t rwi_dat                      : 1;  /**< RWI_DAT memory BIST status */
+	uint64_t reserved_32_33               : 2;
+	uint64_t soc                          : 1;  /**< SSO CAM BIST status */
+	uint64_t reserved_28_30               : 3;
+	uint64_t ncbo                         : 4;  /**< NCBO transmitter memory BIST status */
+	uint64_t reserved_21_23               : 3;
+	uint64_t index                        : 1;  /**< Index memory BIST status */
+	uint64_t reserved_17_19               : 3;
+	uint64_t fidx                         : 1;  /**< Forward index memory BIST status */
+	uint64_t reserved_10_15               : 6;
+	uint64_t pend                         : 2;  /**< Pending switch memory BIST status */
+	uint64_t reserved_2_7                 : 6;
+	uint64_t oth                          : 2;  /**< WQP, GRP memory BIST status */
+#else
+	uint64_t oth                          : 2;
+	uint64_t reserved_2_7                 : 6;
+	uint64_t pend                         : 2;
+	uint64_t reserved_10_15               : 6;
+	uint64_t fidx                         : 1;
+	uint64_t reserved_17_19               : 3;
+	uint64_t index                        : 1;
+	uint64_t reserved_21_23               : 3;
+	uint64_t ncbo                         : 4;
+	uint64_t reserved_28_30               : 3;
+	uint64_t soc                          : 1;
+	uint64_t reserved_32_33               : 2;
+	uint64_t rwi_dat                      : 1;
+	uint64_t reserved_35_41               : 7;
+	uint64_t rwo                          : 2;
+	uint64_t rwo_dat                      : 1;
+	uint64_t reserved_45_51               : 7;
+	uint64_t fptr                         : 2;
+	uint64_t reserved_54_59               : 6;
+	uint64_t odu_pref                     : 2;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} s;
+	struct cvmx_sso_bist_stat_s           cn68xx;
+	struct cvmx_sso_bist_stat_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t fptr                         : 2;  /**< FPTR memory BIST status */
+	uint64_t reserved_45_51               : 7;
+	uint64_t rwo_dat                      : 1;  /**< RWO_DAT memory BIST status */
+	uint64_t rwo                          : 2;  /**< RWO memory BIST status */
+	uint64_t reserved_35_41               : 7;
+	uint64_t rwi_dat                      : 1;  /**< RWI_DAT memory BIST status */
+	uint64_t reserved_32_33               : 2;
+	uint64_t soc                          : 1;  /**< SSO CAM BIST status */
+	uint64_t reserved_28_30               : 3;
+	uint64_t ncbo                         : 4;  /**< NCBO transmitter memory BIST status */
+	uint64_t reserved_21_23               : 3;
+	uint64_t index                        : 1;  /**< Index memory BIST status */
+	uint64_t reserved_17_19               : 3;
+	uint64_t fidx                         : 1;  /**< Forward index memory BIST status */
+	uint64_t reserved_10_15               : 6;
+	uint64_t pend                         : 2;  /**< Pending switch memory BIST status */
+	uint64_t reserved_2_7                 : 6;
+	uint64_t oth                          : 2;  /**< WQP, GRP memory BIST status */
+#else
+	uint64_t oth                          : 2;
+	uint64_t reserved_2_7                 : 6;
+	uint64_t pend                         : 2;
+	uint64_t reserved_10_15               : 6;
+	uint64_t fidx                         : 1;
+	uint64_t reserved_17_19               : 3;
+	uint64_t index                        : 1;
+	uint64_t reserved_21_23               : 3;
+	uint64_t ncbo                         : 4;
+	uint64_t reserved_28_30               : 3;
+	uint64_t soc                          : 1;
+	uint64_t reserved_32_33               : 2;
+	uint64_t rwi_dat                      : 1;
+	uint64_t reserved_35_41               : 7;
+	uint64_t rwo                          : 2;
+	uint64_t rwo_dat                      : 1;
+	uint64_t reserved_45_51               : 7;
+	uint64_t fptr                         : 2;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_sso_bist_stat cvmx_sso_bist_stat_t;
+
+/**
+ * cvmx_sso_cfg
+ *
+ * SSO_CFG = SSO Config
+ *
+ * This register is an assortment of various SSO configuration bits.
+ */
+union cvmx_sso_cfg {
+	uint64_t u64;
+	struct cvmx_sso_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t qck_gw_rsp_adj               : 3;  /**< Fast GET_WORK response fine adjustment
+                                                         Allowed values are 0, 1, and 2 (0 is quickest) */
+	uint64_t qck_gw_rsp_dis               : 1;  /**< Disable faster response to GET_WORK */
+	uint64_t qck_sw_dis                   : 1;  /**< Disable faster switch to UNSCHEDULED on GET_WORK */
+	uint64_t rwq_alloc_dis                : 1;  /**< Disable FPA Alloc Requests when SSO_FPAGE_CNT < 16 */
+	uint64_t soc_ccam_dis                 : 1;  /**< Disable power saving SOC conditional CAM
+                                                         (**NOTE: Added in pass 2.0) */
+	uint64_t sso_cclk_dis                 : 1;  /**< Disable power saving SSO conditional clocking
+                                                         (**NOTE: Added in pass 2.0) */
+	uint64_t rwo_flush                    : 1;  /**< Flush RWO engine
+                                                         Allows outbound NCB entries to go immediately rather
+                                                         than waiting for a complete fill packet. This register
+                                                         is one-shot and clears itself each time it is set. */
+	uint64_t wfe_thr                      : 1;  /**< Use 1 Work-fetch engine (instead of 4) */
+	uint64_t rwio_byp_dis                 : 1;  /**< Disable Bypass path in RWI/RWO Engines */
+	uint64_t rwq_byp_dis                  : 1;  /**< Disable Bypass path in RWQ Engine */
+	uint64_t stt                          : 1;  /**< STT Setting for RW Stores */
+	uint64_t ldt                          : 1;  /**< LDT Setting for RW Loads */
+	uint64_t dwb                          : 1;  /**< DWB Setting for Return Page Requests
+                                                         1 = 2 128B cache pages to issue DWB for
+                                                         0 = 0 128B cache pages ro issue DWB for */
+	uint64_t rwen                         : 1;  /**< Enable RWI/RWO operations
+                                                         This bit should be set after SSO_RWQ_HEAD_PTRX and
+                                                         SSO_RWQ_TAIL_PTRX have been programmed. */
+#else
+	uint64_t rwen                         : 1;
+	uint64_t dwb                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t rwq_byp_dis                  : 1;
+	uint64_t rwio_byp_dis                 : 1;
+	uint64_t wfe_thr                      : 1;
+	uint64_t rwo_flush                    : 1;
+	uint64_t sso_cclk_dis                 : 1;
+	uint64_t soc_ccam_dis                 : 1;
+	uint64_t rwq_alloc_dis                : 1;
+	uint64_t qck_sw_dis                   : 1;
+	uint64_t qck_gw_rsp_dis               : 1;
+	uint64_t qck_gw_rsp_adj               : 3;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_sso_cfg_s                 cn68xx;
+	struct cvmx_sso_cfg_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_8_63                : 56;
+	uint64_t rwo_flush                    : 1;  /**< Flush RWO engine
+                                                         Allows outbound NCB entries to go immediately rather
+                                                         than waiting for a complete fill packet. This register
+                                                         is one-shot and clears itself each time it is set. */
+	uint64_t wfe_thr                      : 1;  /**< Use 1 Work-fetch engine (instead of 4) */
+	uint64_t rwio_byp_dis                 : 1;  /**< Disable Bypass path in RWI/RWO Engines */
+	uint64_t rwq_byp_dis                  : 1;  /**< Disable Bypass path in RWQ Engine */
+	uint64_t stt                          : 1;  /**< STT Setting for RW Stores */
+	uint64_t ldt                          : 1;  /**< LDT Setting for RW Loads */
+	uint64_t dwb                          : 1;  /**< DWB Setting for Return Page Requests
+                                                         1 = 2 128B cache pages to issue DWB for
+                                                         0 = 0 128B cache pages ro issue DWB for */
+	uint64_t rwen                         : 1;  /**< Enable RWI/RWO operations
+                                                         This bit should be set after SSO_RWQ_HEAD_PTRX and
+                                                         SSO_RWQ_TAIL_PTRX have been programmed. */
+#else
+	uint64_t rwen                         : 1;
+	uint64_t dwb                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t rwq_byp_dis                  : 1;
+	uint64_t rwio_byp_dis                 : 1;
+	uint64_t wfe_thr                      : 1;
+	uint64_t rwo_flush                    : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_sso_cfg cvmx_sso_cfg_t;
+
+/**
+ * cvmx_sso_ds_pc
+ *
+ * SSO_DS_PC = SSO De-Schedule Performance Counter
+ *
+ * Counts the number of de-schedule requests.
+ * Counter rolls over through zero when max value exceeded.
+ */
+union cvmx_sso_ds_pc {
+	uint64_t u64;
+	struct cvmx_sso_ds_pc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t ds_pc                        : 64; /**< De-schedule performance counter */
+#else
+	uint64_t ds_pc                        : 64;
+#endif
+	} s;
+	struct cvmx_sso_ds_pc_s               cn68xx;
+	struct cvmx_sso_ds_pc_s               cn68xxp1;
+};
+typedef union cvmx_sso_ds_pc cvmx_sso_ds_pc_t;
+
+/**
+ * cvmx_sso_err
+ *
+ * SSO_ERR = SSO Error Register
+ *
+ * Contains ECC and other misc error bits.
+ *
+ * <45> The free page error bit will assert when SSO_FPAGE_CNT <= 16 and
+ *      SSO_CFG[RWEN] is 1.  Software will want to disable the interrupt
+ *      associated with this error when recovering SSO pointers from the
+ *      FPA and SSO.
+ *
+ * This register also contains the illegal operation error bits:
+ *
+ * <42> Received ADDWQ with tag specified as EMPTY
+ * <41> Received illegal opcode
+ * <40> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/ALLOC_WE
+ *      from WS with CLR_NSCHED pending
+ * <39> Received CLR_NSCHED
+ *      from WS with SWTAG_DESCH/DESCH/CLR_NSCHED pending
+ * <38> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/ALLOC_WE
+ *      from WS with ALLOC_WE pending
+ * <37> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/ALLOC_WE/CLR_NSCHED
+ *      from WS with GET_WORK pending
+ * <36> Received SWTAG_FULL/SWTAG_DESCH
+ *      with tag specified as UNSCHEDULED
+ * <35> Received SWTAG/SWTAG_FULL/SWTAG_DESCH
+ *      with tag specified as EMPTY
+ * <34> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/GET_WORK
+ *      from WS with pending tag switch to ORDERED or ATOMIC
+ * <33> Received SWTAG/SWTAG_DESCH/DESCH/UPD_WQP
+ *      from WS in UNSCHEDULED state
+ * <32> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP
+ *      from WS in EMPTY state
+ */
+union cvmx_sso_err {
+	uint64_t u64;
+	struct cvmx_sso_err_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_48_63               : 16;
+	uint64_t bfp                          : 1;  /**< Bad Fill Packet error
+                                                         Last byte of the fill packet did not match 8'h1a */
+	uint64_t awe                          : 1;  /**< Out-of-memory error (ADDWQ Request is dropped) */
+	uint64_t fpe                          : 1;  /**< Free page error */
+	uint64_t reserved_43_44               : 2;
+	uint64_t iop                          : 11; /**< Illegal operation errors */
+	uint64_t reserved_12_31               : 20;
+	uint64_t pnd_dbe0                     : 1;  /**< Double bit error for even PND RAM */
+	uint64_t pnd_sbe0                     : 1;  /**< Single bit error for even PND RAM */
+	uint64_t pnd_dbe1                     : 1;  /**< Double bit error for odd PND RAM */
+	uint64_t pnd_sbe1                     : 1;  /**< Single bit error for odd PND RAM */
+	uint64_t oth_dbe0                     : 1;  /**< Double bit error for even OTH RAM */
+	uint64_t oth_sbe0                     : 1;  /**< Single bit error for even OTH RAM */
+	uint64_t oth_dbe1                     : 1;  /**< Double bit error for odd OTH RAM */
+	uint64_t oth_sbe1                     : 1;  /**< Single bit error for odd OTH RAM */
+	uint64_t idx_dbe                      : 1;  /**< Double bit error for IDX RAM */
+	uint64_t idx_sbe                      : 1;  /**< Single bit error for IDX RAM */
+	uint64_t fidx_dbe                     : 1;  /**< Double bit error for FIDX RAM */
+	uint64_t fidx_sbe                     : 1;  /**< Single bit error for FIDX RAM */
+#else
+	uint64_t fidx_sbe                     : 1;
+	uint64_t fidx_dbe                     : 1;
+	uint64_t idx_sbe                      : 1;
+	uint64_t idx_dbe                      : 1;
+	uint64_t oth_sbe1                     : 1;
+	uint64_t oth_dbe1                     : 1;
+	uint64_t oth_sbe0                     : 1;
+	uint64_t oth_dbe0                     : 1;
+	uint64_t pnd_sbe1                     : 1;
+	uint64_t pnd_dbe1                     : 1;
+	uint64_t pnd_sbe0                     : 1;
+	uint64_t pnd_dbe0                     : 1;
+	uint64_t reserved_12_31               : 20;
+	uint64_t iop                          : 11;
+	uint64_t reserved_43_44               : 2;
+	uint64_t fpe                          : 1;
+	uint64_t awe                          : 1;
+	uint64_t bfp                          : 1;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_sso_err_s                 cn68xx;
+	struct cvmx_sso_err_s                 cn68xxp1;
+};
+typedef union cvmx_sso_err cvmx_sso_err_t;
+
+/**
+ * cvmx_sso_err_enb
+ *
+ * SSO_ERR_ENB = SSO Error Enable Register
+ *
+ * Contains the interrupt enables corresponding to SSO_ERR.
+ */
+union cvmx_sso_err_enb {
+	uint64_t u64;
+	struct cvmx_sso_err_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_48_63               : 16;
+	uint64_t bfp_ie                       : 1;  /**< Bad Fill Packet error interrupt enable */
+	uint64_t awe_ie                       : 1;  /**< Add-work error interrupt enable */
+	uint64_t fpe_ie                       : 1;  /**< Free Page error interrupt enable */
+	uint64_t reserved_43_44               : 2;
+	uint64_t iop_ie                       : 11; /**< Illegal operation interrupt enables */
+	uint64_t reserved_12_31               : 20;
+	uint64_t pnd_dbe0_ie                  : 1;  /**< Double bit error interrupt enable for even PND RAM */
+	uint64_t pnd_sbe0_ie                  : 1;  /**< Single bit error interrupt enable for even PND RAM */
+	uint64_t pnd_dbe1_ie                  : 1;  /**< Double bit error interrupt enable for odd PND RAM */
+	uint64_t pnd_sbe1_ie                  : 1;  /**< Single bit error interrupt enable for odd PND RAM */
+	uint64_t oth_dbe0_ie                  : 1;  /**< Double bit error interrupt enable for even OTH RAM */
+	uint64_t oth_sbe0_ie                  : 1;  /**< Single bit error interrupt enable for even OTH RAM */
+	uint64_t oth_dbe1_ie                  : 1;  /**< Double bit error interrupt enable for odd OTH RAM */
+	uint64_t oth_sbe1_ie                  : 1;  /**< Single bit error interrupt enable for odd OTH RAM */
+	uint64_t idx_dbe_ie                   : 1;  /**< Double bit error interrupt enable for IDX RAM */
+	uint64_t idx_sbe_ie                   : 1;  /**< Single bit error interrupt enable for IDX RAM */
+	uint64_t fidx_dbe_ie                  : 1;  /**< Double bit error interrupt enable for FIDX RAM */
+	uint64_t fidx_sbe_ie                  : 1;  /**< Single bit error interrupt enable for FIDX RAM */
+#else
+	uint64_t fidx_sbe_ie                  : 1;
+	uint64_t fidx_dbe_ie                  : 1;
+	uint64_t idx_sbe_ie                   : 1;
+	uint64_t idx_dbe_ie                   : 1;
+	uint64_t oth_sbe1_ie                  : 1;
+	uint64_t oth_dbe1_ie                  : 1;
+	uint64_t oth_sbe0_ie                  : 1;
+	uint64_t oth_dbe0_ie                  : 1;
+	uint64_t pnd_sbe1_ie                  : 1;
+	uint64_t pnd_dbe1_ie                  : 1;
+	uint64_t pnd_sbe0_ie                  : 1;
+	uint64_t pnd_dbe0_ie                  : 1;
+	uint64_t reserved_12_31               : 20;
+	uint64_t iop_ie                       : 11;
+	uint64_t reserved_43_44               : 2;
+	uint64_t fpe_ie                       : 1;
+	uint64_t awe_ie                       : 1;
+	uint64_t bfp_ie                       : 1;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_sso_err_enb_s             cn68xx;
+	struct cvmx_sso_err_enb_s             cn68xxp1;
+};
+typedef union cvmx_sso_err_enb cvmx_sso_err_enb_t;
+
+/**
+ * cvmx_sso_fidx_ecc_ctl
+ *
+ * SSO_FIDX_ECC_CTL = SSO FIDX ECC Control
+ *
+ */
+union cvmx_sso_fidx_ecc_ctl {
+	uint64_t u64;
+	struct cvmx_sso_fidx_ecc_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_3_63                : 61;
+	uint64_t flip_synd                    : 2;  /**< Testing feature. Flip Syndrom to generate single or
+                                                         double bit error for the FIDX RAM. */
+	uint64_t ecc_ena                      : 1;  /**< ECC Enable: When set will enable the 5 bit ECC
+                                                         correct logic for the FIDX RAM. */
+#else
+	uint64_t ecc_ena                      : 1;
+	uint64_t flip_synd                    : 2;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_sso_fidx_ecc_ctl_s        cn68xx;
+	struct cvmx_sso_fidx_ecc_ctl_s        cn68xxp1;
+};
+typedef union cvmx_sso_fidx_ecc_ctl cvmx_sso_fidx_ecc_ctl_t;
+
+/**
+ * cvmx_sso_fidx_ecc_st
+ *
+ * SSO_FIDX_ECC_ST = SSO FIDX ECC Status
+ *
+ */
+union cvmx_sso_fidx_ecc_st {
+	uint64_t u64;
+	struct cvmx_sso_fidx_ecc_st_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_27_63               : 37;
+	uint64_t addr                         : 11; /**< Latch the address for latest sde/dbe occured
+                                                         for the FIDX RAM */
+	uint64_t reserved_9_15                : 7;
+	uint64_t syndrom                      : 5;  /**< Report the latest error syndrom for the
+                                                         FIDX RAM */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t syndrom                      : 5;
+	uint64_t reserved_9_15                : 7;
+	uint64_t addr                         : 11;
+	uint64_t reserved_27_63               : 37;
+#endif
+	} s;
+	struct cvmx_sso_fidx_ecc_st_s         cn68xx;
+	struct cvmx_sso_fidx_ecc_st_s         cn68xxp1;
+};
+typedef union cvmx_sso_fidx_ecc_st cvmx_sso_fidx_ecc_st_t;
+
+/**
+ * cvmx_sso_fpage_cnt
+ *
+ * SSO_FPAGE_CNT = SSO Free Page Cnt
+ *
+ * This register keeps track of the number of free pages pointers available for use in external memory.
+ */
+union cvmx_sso_fpage_cnt {
+	uint64_t u64;
+	struct cvmx_sso_fpage_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t fpage_cnt                    : 32; /**< Free Page Cnt
+                                                         HW updates this register. Writes to this register
+                                                         are only for diagnostic purposes */
+#else
+	uint64_t fpage_cnt                    : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sso_fpage_cnt_s           cn68xx;
+	struct cvmx_sso_fpage_cnt_s           cn68xxp1;
+};
+typedef union cvmx_sso_fpage_cnt cvmx_sso_fpage_cnt_t;
+
+/**
+ * cvmx_sso_gwe_cfg
+ *
+ * SSO_GWE_CFG = SSO Get-Work Examiner Configuration
+ *
+ * This register controls the operation of the Get-Work Examiner (GWE)
+ */
+union cvmx_sso_gwe_cfg {
+	uint64_t u64;
+	struct cvmx_sso_gwe_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_12_63               : 52;
+	uint64_t odu_ffpgw_dis                : 1;  /**< Disable flushing ODU on periodic restart of GWE */
+	uint64_t gwe_rfpgw_dis                : 1;  /**< Disable periodic restart of GWE for pending get_work */
+	uint64_t odu_prf_dis                  : 1;  /**< Disable ODU-initiated prefetches of WQEs into L2C
+                                                         For diagnostic use only. */
+	uint64_t odu_bmp_dis                  : 1;  /**< Disable ODU bumps.
+                                                         If SSO_PP_STRICT is true, could
+                                                         prevent forward progress under some circumstances.
+                                                         For diagnostic use only. */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gwe_hvy_dis                  : 1;  /**< Disable GWE automatic, proportional weight-increase
+                                                         mechanism and use SSO_QOSX_RND values as-is.
+                                                         For diagnostic use only. */
+	uint64_t gwe_poe                      : 1;  /**< Pause GWE on extracts
+                                                         For diagnostic use only. */
+	uint64_t gwe_fpor                     : 1;  /**< Flush GWE pipeline when restarting GWE.
+                                                         For diagnostic use only. */
+	uint64_t gwe_rah                      : 1;  /**< Begin at head of input queues when restarting GWE.
+                                                         For diagnostic use only. */
+	uint64_t gwe_dis                      : 1;  /**< Disable Get-Work Examiner */
+#else
+	uint64_t gwe_dis                      : 1;
+	uint64_t gwe_rah                      : 1;
+	uint64_t gwe_fpor                     : 1;
+	uint64_t gwe_poe                      : 1;
+	uint64_t gwe_hvy_dis                  : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t odu_bmp_dis                  : 1;
+	uint64_t odu_prf_dis                  : 1;
+	uint64_t gwe_rfpgw_dis                : 1;
+	uint64_t odu_ffpgw_dis                : 1;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_sso_gwe_cfg_s             cn68xx;
+	struct cvmx_sso_gwe_cfg_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t gwe_poe                      : 1;  /**< Pause GWE on extracts
+                                                         For diagnostic use only. */
+	uint64_t gwe_fpor                     : 1;  /**< Flush GWE pipeline when restarting GWE.
+                                                         For diagnostic use only. */
+	uint64_t gwe_rah                      : 1;  /**< Begin at head of input queues when restarting GWE.
+                                                         For diagnostic use only. */
+	uint64_t gwe_dis                      : 1;  /**< Disable Get-Work Examiner */
+#else
+	uint64_t gwe_dis                      : 1;
+	uint64_t gwe_rah                      : 1;
+	uint64_t gwe_fpor                     : 1;
+	uint64_t gwe_poe                      : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_sso_gwe_cfg cvmx_sso_gwe_cfg_t;
+
+/**
+ * cvmx_sso_idx_ecc_ctl
+ *
+ * SSO_IDX_ECC_CTL = SSO IDX ECC Control
+ *
+ */
+union cvmx_sso_idx_ecc_ctl {
+	uint64_t u64;
+	struct cvmx_sso_idx_ecc_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_3_63                : 61;
+	uint64_t flip_synd                    : 2;  /**< Testing feature. Flip Syndrom to generate single or
+                                                         double bit error for the IDX RAM. */
+	uint64_t ecc_ena                      : 1;  /**< ECC Enable: When set will enable the 5 bit ECC
+                                                         correct logic for the IDX RAM. */
+#else
+	uint64_t ecc_ena                      : 1;
+	uint64_t flip_synd                    : 2;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_sso_idx_ecc_ctl_s         cn68xx;
+	struct cvmx_sso_idx_ecc_ctl_s         cn68xxp1;
+};
+typedef union cvmx_sso_idx_ecc_ctl cvmx_sso_idx_ecc_ctl_t;
+
+/**
+ * cvmx_sso_idx_ecc_st
+ *
+ * SSO_IDX_ECC_ST = SSO IDX ECC Status
+ *
+ */
+union cvmx_sso_idx_ecc_st {
+	uint64_t u64;
+	struct cvmx_sso_idx_ecc_st_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_27_63               : 37;
+	uint64_t addr                         : 11; /**< Latch the address for latest sde/dbe occured
+                                                         for the IDX RAM */
+	uint64_t reserved_9_15                : 7;
+	uint64_t syndrom                      : 5;  /**< Report the latest error syndrom for the
+                                                         IDX RAM */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t syndrom                      : 5;
+	uint64_t reserved_9_15                : 7;
+	uint64_t addr                         : 11;
+	uint64_t reserved_27_63               : 37;
+#endif
+	} s;
+	struct cvmx_sso_idx_ecc_st_s          cn68xx;
+	struct cvmx_sso_idx_ecc_st_s          cn68xxp1;
+};
+typedef union cvmx_sso_idx_ecc_st cvmx_sso_idx_ecc_st_t;
+
+/**
+ * cvmx_sso_iq_cnt#
+ *
+ * CSR reserved addresses: (64): 0x8200..0x83f8
+ * CSR align addresses: ===========================================================================================================
+ * SSO_IQ_CNTX = SSO Input Queue Count Register
+ *               (one per QOS level)
+ *
+ * Contains a read-only count of the number of work queue entries for each QOS
+ * level. Counts both in-unit and in-memory entries.
+ */
+union cvmx_sso_iq_cntx {
+	uint64_t u64;
+	struct cvmx_sso_iq_cntx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t iq_cnt                       : 32; /**< Input queue count for QOS level X */
+#else
+	uint64_t iq_cnt                       : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sso_iq_cntx_s             cn68xx;
+	struct cvmx_sso_iq_cntx_s             cn68xxp1;
+};
+typedef union cvmx_sso_iq_cntx cvmx_sso_iq_cntx_t;
+
+/**
+ * cvmx_sso_iq_com_cnt
+ *
+ * SSO_IQ_COM_CNT = SSO Input Queue Combined Count Register
+ *
+ * Contains a read-only count of the total number of work queue entries in all
+ * QOS levels.  Counts both in-unit and in-memory entries.
+ */
+union cvmx_sso_iq_com_cnt {
+	uint64_t u64;
+	struct cvmx_sso_iq_com_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t iq_cnt                       : 32; /**< Input queue combined count */
+#else
+	uint64_t iq_cnt                       : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sso_iq_com_cnt_s          cn68xx;
+	struct cvmx_sso_iq_com_cnt_s          cn68xxp1;
+};
+typedef union cvmx_sso_iq_com_cnt cvmx_sso_iq_com_cnt_t;
+
+/**
+ * cvmx_sso_iq_int
+ *
+ * SSO_IQ_INT = SSO Input Queue Interrupt Register
+ *
+ * Contains the bits (one per QOS level) that can trigger the input queue
+ * interrupt.  An IQ_INT bit will be set if SSO_IQ_CNT#QOS# changes and the
+ * resulting value is equal to SSO_IQ_THR#QOS#.
+ */
+union cvmx_sso_iq_int {
+	uint64_t u64;
+	struct cvmx_sso_iq_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_8_63                : 56;
+	uint64_t iq_int                       : 8;  /**< Input queue interrupt bits */
+#else
+	uint64_t iq_int                       : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_sso_iq_int_s              cn68xx;
+	struct cvmx_sso_iq_int_s              cn68xxp1;
+};
+typedef union cvmx_sso_iq_int cvmx_sso_iq_int_t;
+
+/**
+ * cvmx_sso_iq_int_en
+ *
+ * SSO_IQ_INT_EN = SSO Input Queue Interrupt Enable Register
+ *
+ * Contains the bits (one per QOS level) that enable the input queue interrupt.
+ */
+union cvmx_sso_iq_int_en {
+	uint64_t u64;
+	struct cvmx_sso_iq_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_8_63                : 56;
+	uint64_t int_en                       : 8;  /**< Input queue interrupt enable bits */
+#else
+	uint64_t int_en                       : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_sso_iq_int_en_s           cn68xx;
+	struct cvmx_sso_iq_int_en_s           cn68xxp1;
+};
+typedef union cvmx_sso_iq_int_en cvmx_sso_iq_int_en_t;
+
+/**
+ * cvmx_sso_iq_thr#
+ *
+ * CSR reserved addresses: (24): 0x9040..0x90f8
+ * CSR align addresses: ===========================================================================================================
+ * SSO_IQ_THRX = SSO Input Queue Threshold Register
+ *               (one per QOS level)
+ *
+ * Threshold value for triggering input queue interrupts.
+ */
+union cvmx_sso_iq_thrx {
+	uint64_t u64;
+	struct cvmx_sso_iq_thrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t iq_thr                       : 32; /**< Input queue threshold for QOS level X */
+#else
+	uint64_t iq_thr                       : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sso_iq_thrx_s             cn68xx;
+	struct cvmx_sso_iq_thrx_s             cn68xxp1;
+};
+typedef union cvmx_sso_iq_thrx cvmx_sso_iq_thrx_t;
+
+/**
+ * cvmx_sso_nos_cnt
+ *
+ * SSO_NOS_CNT = SSO No-schedule Count Register
+ *
+ * Contains the number of work queue entries on the no-schedule list.
+ */
+union cvmx_sso_nos_cnt {
+	uint64_t u64;
+	struct cvmx_sso_nos_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_12_63               : 52;
+	uint64_t nos_cnt                      : 12; /**< Number of work queue entries on the no-schedule list */
+#else
+	uint64_t nos_cnt                      : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_sso_nos_cnt_s             cn68xx;
+	struct cvmx_sso_nos_cnt_s             cn68xxp1;
+};
+typedef union cvmx_sso_nos_cnt cvmx_sso_nos_cnt_t;
+
+/**
+ * cvmx_sso_nw_tim
+ *
+ * SSO_NW_TIM = SSO New Work Timer Period Register
+ *
+ * Sets the minimum period for a new work request timeout.  Period is specified
+ * in n-1 notation where the increment value is 1024 clock cycles.  Thus, a
+ * value of 0x0 in this register translates to 1024 cycles, 0x1 translates to
+ * 2048 cycles, 0x2 translates to 3072 cycles, etc...  Note: the maximum period
+ * for a new work request timeout is 2 times the minimum period.  Note: the new
+ * work request timeout counter is reset when this register is written.
+ *
+ * There are two new work request timeout cases:
+ *
+ * - WAIT bit clear.  The new work request can timeout if the timer expires
+ *   before the pre-fetch engine has reached the end of all work queues.  This
+ *   can occur if the executable work queue entry is deep in the queue and the
+ *   pre-fetch engine is subject to many resets (i.e. high switch, de-schedule,
+ *   or new work load from other PP's).  Thus, it is possible for a PP to
+ *   receive a work response with the NO_WORK bit set even though there was at
+ *   least one executable entry in the work queues.  The other (and typical)
+ *   scenario for receiving a NO_WORK response with the WAIT bit clear is that
+ *   the pre-fetch engine has reached the end of all work queues without
+ *   finding executable work.
+ *
+ * - WAIT bit set.  The new work request can timeout if the timer expires
+ *   before the pre-fetch engine has found executable work.  In this case, the
+ *   only scenario where the PP will receive a work response with the NO_WORK
+ *   bit set is if the timer expires.  Note: it is still possible for a PP to
+ *   receive a NO_WORK response even though there was at least one executable
+ *   entry in the work queues.
+ *
+ * In either case, it's important to note that switches and de-schedules are
+ * higher priority operations that can cause the pre-fetch engine to reset.
+ * Thus in a system with many switches or de-schedules occurring, it's possible
+ * for the new work timer to expire (resulting in NO_WORK responses) before the
+ * pre-fetch engine is able to get very deep into the work queues.
+ */
+union cvmx_sso_nw_tim {
+	uint64_t u64;
+	struct cvmx_sso_nw_tim_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t nw_tim                       : 10; /**< New work timer period */
+#else
+	uint64_t nw_tim                       : 10;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_sso_nw_tim_s              cn68xx;
+	struct cvmx_sso_nw_tim_s              cn68xxp1;
+};
+typedef union cvmx_sso_nw_tim cvmx_sso_nw_tim_t;
+
+/**
+ * cvmx_sso_oth_ecc_ctl
+ *
+ * SSO_OTH_ECC_CTL = SSO OTH ECC Control
+ *
+ */
+union cvmx_sso_oth_ecc_ctl {
+	uint64_t u64;
+	struct cvmx_sso_oth_ecc_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_6_63                : 58;
+	uint64_t flip_synd1                   : 2;  /**< Testing feature. Flip Syndrom to generate single or
+                                                         double bit error for the odd OTH RAM. */
+	uint64_t ecc_ena1                     : 1;  /**< ECC Enable: When set will enable the 7 bit ECC
+                                                         correct logic for the odd OTH RAM. */
+	uint64_t flip_synd0                   : 2;  /**< Testing feature. Flip Syndrom to generate single or
+                                                         double bit error for the even OTH RAM. */
+	uint64_t ecc_ena0                     : 1;  /**< ECC Enable: When set will enable the 7 bit ECC
+                                                         correct logic for the even OTH RAM. */
+#else
+	uint64_t ecc_ena0                     : 1;
+	uint64_t flip_synd0                   : 2;
+	uint64_t ecc_ena1                     : 1;
+	uint64_t flip_synd1                   : 2;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_sso_oth_ecc_ctl_s         cn68xx;
+	struct cvmx_sso_oth_ecc_ctl_s         cn68xxp1;
+};
+typedef union cvmx_sso_oth_ecc_ctl cvmx_sso_oth_ecc_ctl_t;
+
+/**
+ * cvmx_sso_oth_ecc_st
+ *
+ * SSO_OTH_ECC_ST = SSO OTH ECC Status
+ *
+ */
+union cvmx_sso_oth_ecc_st {
+	uint64_t u64;
+	struct cvmx_sso_oth_ecc_st_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_59_63               : 5;
+	uint64_t addr1                        : 11; /**< Latch the address for latest sde/dbe occured
+                                                         for the odd OTH RAM */
+	uint64_t reserved_43_47               : 5;
+	uint64_t syndrom1                     : 7;  /**< Report the latest error syndrom for the odd
+                                                         OTH RAM */
+	uint64_t reserved_27_35               : 9;
+	uint64_t addr0                        : 11; /**< Latch the address for latest sde/dbe occured
+                                                         for the even OTH RAM */
+	uint64_t reserved_11_15               : 5;
+	uint64_t syndrom0                     : 7;  /**< Report the latest error syndrom for the even
+                                                         OTH RAM */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t syndrom0                     : 7;
+	uint64_t reserved_11_15               : 5;
+	uint64_t addr0                        : 11;
+	uint64_t reserved_27_35               : 9;
+	uint64_t syndrom1                     : 7;
+	uint64_t reserved_43_47               : 5;
+	uint64_t addr1                        : 11;
+	uint64_t reserved_59_63               : 5;
+#endif
+	} s;
+	struct cvmx_sso_oth_ecc_st_s          cn68xx;
+	struct cvmx_sso_oth_ecc_st_s          cn68xxp1;
+};
+typedef union cvmx_sso_oth_ecc_st cvmx_sso_oth_ecc_st_t;
+
+/**
+ * cvmx_sso_pnd_ecc_ctl
+ *
+ * SSO_PND_ECC_CTL = SSO PND ECC Control
+ *
+ */
+union cvmx_sso_pnd_ecc_ctl {
+	uint64_t u64;
+	struct cvmx_sso_pnd_ecc_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_6_63                : 58;
+	uint64_t flip_synd1                   : 2;  /**< Testing feature. Flip Syndrom to generate single or
+                                                         double bit error for the odd PND RAM. */
+	uint64_t ecc_ena1                     : 1;  /**< ECC Enable: When set will enable the 7 bit ECC
+                                                         correct logic for the odd PND RAM. */
+	uint64_t flip_synd0                   : 2;  /**< Testing feature. Flip Syndrom to generate single or
+                                                         double bit error for the even PND RAM. */
+	uint64_t ecc_ena0                     : 1;  /**< ECC Enable: When set will enable the 7 bit ECC
+                                                         correct logic for the even PND RAM. */
+#else
+	uint64_t ecc_ena0                     : 1;
+	uint64_t flip_synd0                   : 2;
+	uint64_t ecc_ena1                     : 1;
+	uint64_t flip_synd1                   : 2;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_sso_pnd_ecc_ctl_s         cn68xx;
+	struct cvmx_sso_pnd_ecc_ctl_s         cn68xxp1;
+};
+typedef union cvmx_sso_pnd_ecc_ctl cvmx_sso_pnd_ecc_ctl_t;
+
+/**
+ * cvmx_sso_pnd_ecc_st
+ *
+ * SSO_PND_ECC_ST = SSO PND ECC Status
+ *
+ */
+union cvmx_sso_pnd_ecc_st {
+	uint64_t u64;
+	struct cvmx_sso_pnd_ecc_st_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_59_63               : 5;
+	uint64_t addr1                        : 11; /**< Latch the address for latest sde/dbe occured
+                                                         for the odd PND RAM */
+	uint64_t reserved_43_47               : 5;
+	uint64_t syndrom1                     : 7;  /**< Report the latest error syndrom for the odd
+                                                         PND RAM */
+	uint64_t reserved_27_35               : 9;
+	uint64_t addr0                        : 11; /**< Latch the address for latest sde/dbe occured
+                                                         for the even PND RAM */
+	uint64_t reserved_11_15               : 5;
+	uint64_t syndrom0                     : 7;  /**< Report the latest error syndrom for the even
+                                                         PND RAM */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t syndrom0                     : 7;
+	uint64_t reserved_11_15               : 5;
+	uint64_t addr0                        : 11;
+	uint64_t reserved_27_35               : 9;
+	uint64_t syndrom1                     : 7;
+	uint64_t reserved_43_47               : 5;
+	uint64_t addr1                        : 11;
+	uint64_t reserved_59_63               : 5;
+#endif
+	} s;
+	struct cvmx_sso_pnd_ecc_st_s          cn68xx;
+	struct cvmx_sso_pnd_ecc_st_s          cn68xxp1;
+};
+typedef union cvmx_sso_pnd_ecc_st cvmx_sso_pnd_ecc_st_t;
+
+/**
+ * cvmx_sso_pp#_grp_msk
+ *
+ * CSR reserved addresses: (24): 0x5040..0x50f8
+ * CSR align addresses: ===========================================================================================================
+ * SSO_PPX_GRP_MSK = SSO PP Group Mask Register
+ *                   (one bit per group per PP)
+ *
+ * Selects which group(s) a PP belongs to.  A '1' in any bit position sets the
+ * PP's membership in the corresponding group.  A value of 0x0 will prevent the
+ * PP from receiving new work.
+ *
+ * Note that these do not contain QOS level priorities for each PP.  This is a
+ * change from previous POW designs.
+ */
+union cvmx_sso_ppx_grp_msk {
+	uint64_t u64;
+	struct cvmx_sso_ppx_grp_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t grp_msk                      : 64; /**< PPX group mask */
+#else
+	uint64_t grp_msk                      : 64;
+#endif
+	} s;
+	struct cvmx_sso_ppx_grp_msk_s         cn68xx;
+	struct cvmx_sso_ppx_grp_msk_s         cn68xxp1;
+};
+typedef union cvmx_sso_ppx_grp_msk cvmx_sso_ppx_grp_msk_t;
+
+/**
+ * cvmx_sso_pp#_qos_pri
+ *
+ * CSR reserved addresses: (56): 0x2040..0x21f8
+ * CSR align addresses: ===========================================================================================================
+ * SSO_PP(0..31)_QOS_PRI = SSO PP QOS Priority Register
+ *                                (one field per IQ per PP)
+ *
+ * Contains the QOS level priorities for each PP.
+ *      0x0       is the highest priority
+ *      0x7       is the lowest priority
+ *      0xf       prevents the PP from receiving work from that QOS level
+ *      0x8-0xe   Reserved
+ *
+ * For a given PP, priorities should begin at 0x0, and remain contiguous
+ * throughout the range.  Failure to do so may result in severe
+ * performance degradation.
+ *
+ *
+ * Priorities for IQs 0..7
+ */
+union cvmx_sso_ppx_qos_pri {
+	uint64_t u64;
+	struct cvmx_sso_ppx_qos_pri_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_60_63               : 4;
+	uint64_t qos7_pri                     : 4;  /**< QOS7 priority for PPX */
+	uint64_t reserved_52_55               : 4;
+	uint64_t qos6_pri                     : 4;  /**< QOS6 priority for PPX */
+	uint64_t reserved_44_47               : 4;
+	uint64_t qos5_pri                     : 4;  /**< QOS5 priority for PPX */
+	uint64_t reserved_36_39               : 4;
+	uint64_t qos4_pri                     : 4;  /**< QOS4 priority for PPX */
+	uint64_t reserved_28_31               : 4;
+	uint64_t qos3_pri                     : 4;  /**< QOS3 priority for PPX */
+	uint64_t reserved_20_23               : 4;
+	uint64_t qos2_pri                     : 4;  /**< QOS2 priority for PPX */
+	uint64_t reserved_12_15               : 4;
+	uint64_t qos1_pri                     : 4;  /**< QOS1 priority for PPX */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t qos0_pri                     : 4;  /**< QOS0 priority for PPX */
+#else
+	uint64_t qos0_pri                     : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t qos1_pri                     : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t qos2_pri                     : 4;
+	uint64_t reserved_20_23               : 4;
+	uint64_t qos3_pri                     : 4;
+	uint64_t reserved_28_31               : 4;
+	uint64_t qos4_pri                     : 4;
+	uint64_t reserved_36_39               : 4;
+	uint64_t qos5_pri                     : 4;
+	uint64_t reserved_44_47               : 4;
+	uint64_t qos6_pri                     : 4;
+	uint64_t reserved_52_55               : 4;
+	uint64_t qos7_pri                     : 4;
+	uint64_t reserved_60_63               : 4;
+#endif
+	} s;
+	struct cvmx_sso_ppx_qos_pri_s         cn68xx;
+	struct cvmx_sso_ppx_qos_pri_s         cn68xxp1;
+};
+typedef union cvmx_sso_ppx_qos_pri cvmx_sso_ppx_qos_pri_t;
+
+/**
+ * cvmx_sso_pp_strict
+ *
+ * SSO_PP_STRICT = SSO Strict Priority
+ *
+ * This register controls getting work from the input queues.  If the bit
+ * corresponding to a PP is set, that PP will not take work off the input
+ * queues until it is known that there is no higher-priority work available.
+ *
+ * Setting SSO_PP_STRICT may incur a performance penalty if highest-priority
+ * work is not found early.
+ *
+ * It is possible to starve a PP of work with SSO_PP_STRICT.  If the
+ * SSO_PPX_GRP_MSK for a PP masks-out much of the work added to the input
+ * queues that are higher-priority for that PP, and if there is a constant
+ * stream of work through one or more of those higher-priority input queues,
+ * then that PP may not accept work from lower-priority input queues.  This can
+ * be alleviated by ensuring that most or all the work added to the
+ * higher-priority input queues for a PP with SSO_PP_STRICT set are in a group
+ * acceptable to that PP.
+ *
+ * It is also possible to neglect work in an input queue if SSO_PP_STRICT is
+ * used.  If an input queue is a lower-priority queue for all PPs, and if all
+ * the PPs have their corresponding bit in SSO_PP_STRICT set, then work may
+ * never be taken (or be seldom taken) from that queue.  This can be alleviated
+ * by ensuring that work in all input queues can be serviced by one or more PPs
+ * that do not have SSO_PP_STRICT set, or that the input queue is the
+ * highest-priority input queue for one or more PPs that do have SSO_PP_STRICT
+ * set.
+ */
+union cvmx_sso_pp_strict {
+	uint64_t u64;
+	struct cvmx_sso_pp_strict_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t pp_strict                    : 32; /**< Corresponding PP operates in strict mode. */
+#else
+	uint64_t pp_strict                    : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sso_pp_strict_s           cn68xx;
+	struct cvmx_sso_pp_strict_s           cn68xxp1;
+};
+typedef union cvmx_sso_pp_strict cvmx_sso_pp_strict_t;
+
+/**
+ * cvmx_sso_qos#_rnd
+ *
+ * CSR align addresses: ===========================================================================================================
+ * SSO_QOS(0..7)_RND = SSO QOS Issue Round Register
+ *                (one per IQ)
+ *
+ * The number of arbitration rounds each QOS level participates in.
+ */
+union cvmx_sso_qosx_rnd {
+	uint64_t u64;
+	struct cvmx_sso_qosx_rnd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_8_63                : 56;
+	uint64_t rnds_qos                     : 8;  /**< Number of rounds to participate in for IQ(X). */
+#else
+	uint64_t rnds_qos                     : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_sso_qosx_rnd_s            cn68xx;
+	struct cvmx_sso_qosx_rnd_s            cn68xxp1;
+};
+typedef union cvmx_sso_qosx_rnd cvmx_sso_qosx_rnd_t;
+
+/**
+ * cvmx_sso_qos_thr#
+ *
+ * CSR reserved addresses: (24): 0xa040..0xa0f8
+ * CSR align addresses: ===========================================================================================================
+ * SSO_QOS_THRX = SSO QOS Threshold Register
+ *                (one per QOS level)
+ *
+ * Contains the thresholds for allocating SSO internal storage buffers.  If the
+ * number of remaining free buffers drops below the minimum threshold (MIN_THR)
+ * or the number of allocated buffers for this QOS level rises above the
+ * maximum threshold (MAX_THR), future incoming work queue entries will be
+ * buffered externally rather than internally.  This register also contains the
+ * number of internal buffers currently allocated to this QOS level (BUF_CNT).
+ */
+union cvmx_sso_qos_thrx {
+	uint64_t u64;
+	struct cvmx_sso_qos_thrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_40_63               : 24;
+	uint64_t buf_cnt                      : 12; /**< # of internal buffers allocated to QOS level X */
+	uint64_t reserved_26_27               : 2;
+	uint64_t max_thr                      : 12; /**< Max threshold for QOS level X
+                                                         For performance reasons, MAX_THR can have a slop of 4
+                                                         WQE for QOS level X. */
+	uint64_t reserved_12_13               : 2;
+	uint64_t min_thr                      : 12; /**< Min threshold for QOS level X
+                                                         For performance reasons, MIN_THR can have a slop of 4
+                                                         WQEs for QOS level X. */
+#else
+	uint64_t min_thr                      : 12;
+	uint64_t reserved_12_13               : 2;
+	uint64_t max_thr                      : 12;
+	uint64_t reserved_26_27               : 2;
+	uint64_t buf_cnt                      : 12;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} s;
+	struct cvmx_sso_qos_thrx_s            cn68xx;
+	struct cvmx_sso_qos_thrx_s            cn68xxp1;
+};
+typedef union cvmx_sso_qos_thrx cvmx_sso_qos_thrx_t;
+
+/**
+ * cvmx_sso_qos_we
+ *
+ * SSO_QOS_WE = SSO WE Buffers
+ *
+ * This register contains a read-only count of the current number of free
+ * buffers (FREE_CNT) and the total number of tag chain heads on the de-schedule list
+ * (DES_CNT) (which is not the same as the total number of entries on all of the descheduled
+ * tag chains.)
+ */
+union cvmx_sso_qos_we {
+	uint64_t u64;
+	struct cvmx_sso_qos_we_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_26_63               : 38;
+	uint64_t des_cnt                      : 12; /**< Number of buffers on de-schedule list */
+	uint64_t reserved_12_13               : 2;
+	uint64_t free_cnt                     : 12; /**< Number of total free buffers */
+#else
+	uint64_t free_cnt                     : 12;
+	uint64_t reserved_12_13               : 2;
+	uint64_t des_cnt                      : 12;
+	uint64_t reserved_26_63               : 38;
+#endif
+	} s;
+	struct cvmx_sso_qos_we_s              cn68xx;
+	struct cvmx_sso_qos_we_s              cn68xxp1;
+};
+typedef union cvmx_sso_qos_we cvmx_sso_qos_we_t;
+
+/**
+ * cvmx_sso_reset
+ *
+ * SSO_RESET = SSO Soft Reset
+ *
+ * Writing a one to SSO_RESET[RESET] will reset the SSO.  After receiving a
+ * store to this CSR, the SSO must not be sent any other operations for 2500
+ * sclk cycles.
+ *
+ * Note that the contents of this register are reset along with the rest of the
+ * SSO.
+ *
+ * IMPLEMENTATION NOTES--NOT FOR SPEC:
+ *      The SSO must return the bus credit associated with the CSR store used
+ *      to write this register before reseting itself.  And the RSL tree
+ *      that passes through the SSO must continue to work for RSL operations
+ *      that do not target the SSO itself.
+ */
+union cvmx_sso_reset {
+	uint64_t u64;
+	struct cvmx_sso_reset_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_1_63                : 63;
+	uint64_t reset                        : 1;  /**< Reset the SSO */
+#else
+	uint64_t reset                        : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_sso_reset_s               cn68xx;
+};
+typedef union cvmx_sso_reset cvmx_sso_reset_t;
+
+/**
+ * cvmx_sso_rwq_head_ptr#
+ *
+ * CSR reserved addresses: (24): 0xb040..0xb0f8
+ * CSR align addresses: ===========================================================================================================
+ * SSO_RWQ_HEAD_PTRX = SSO Remote Queue Head Register
+ *                (one per QOS level)
+ * Contains the ptr to the first entry of the remote linked list(s) for a particular
+ * QoS level. SW should initialize the remote linked list(s) by programming
+ * SSO_RWQ_HEAD_PTRX and SSO_RWQ_TAIL_PTRX to identical values.
+ */
+union cvmx_sso_rwq_head_ptrx {
+	uint64_t u64;
+	struct cvmx_sso_rwq_head_ptrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_38_63               : 26;
+	uint64_t ptr                          : 31; /**< Head Pointer */
+	uint64_t reserved_5_6                 : 2;
+	uint64_t rctr                         : 5;  /**< Index of next WQE entry in fill packet to be
+                                                         processed (inbound queues) */
+#else
+	uint64_t rctr                         : 5;
+	uint64_t reserved_5_6                 : 2;
+	uint64_t ptr                          : 31;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_sso_rwq_head_ptrx_s       cn68xx;
+	struct cvmx_sso_rwq_head_ptrx_s       cn68xxp1;
+};
+typedef union cvmx_sso_rwq_head_ptrx cvmx_sso_rwq_head_ptrx_t;
+
+/**
+ * cvmx_sso_rwq_pop_fptr
+ *
+ * SSO_RWQ_POP_FPTR = SSO Pop Free Pointer
+ *
+ * This register is used by SW to remove pointers for buffer-reallocation and diagnostics, and
+ * should only be used when SSO is idle.
+ *
+ * To remove ALL pointers, software must insure that there are modulus 16
+ * pointers in the FPA.  To do this, SSO_CFG.RWQ_BYP_DIS must be set, the FPA
+ * pointer count read, and enough fake buffers pushed via SSO_RWQ_PSH_FPTR to
+ * bring the FPA pointer count up to mod 16.
+ */
+union cvmx_sso_rwq_pop_fptr {
+	uint64_t u64;
+	struct cvmx_sso_rwq_pop_fptr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t val                          : 1;  /**< Free Pointer Valid */
+	uint64_t cnt                          : 6;  /**< fptr_in count */
+	uint64_t reserved_38_56               : 19;
+	uint64_t fptr                         : 31; /**< Free Pointer */
+	uint64_t reserved_0_6                 : 7;
+#else
+	uint64_t reserved_0_6                 : 7;
+	uint64_t fptr                         : 31;
+	uint64_t reserved_38_56               : 19;
+	uint64_t cnt                          : 6;
+	uint64_t val                          : 1;
+#endif
+	} s;
+	struct cvmx_sso_rwq_pop_fptr_s        cn68xx;
+	struct cvmx_sso_rwq_pop_fptr_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t val                          : 1;  /**< Free Pointer Valid */
+	uint64_t reserved_38_62               : 25;
+	uint64_t fptr                         : 31; /**< Free Pointer */
+	uint64_t reserved_0_6                 : 7;
+#else
+	uint64_t reserved_0_6                 : 7;
+	uint64_t fptr                         : 31;
+	uint64_t reserved_38_62               : 25;
+	uint64_t val                          : 1;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_sso_rwq_pop_fptr cvmx_sso_rwq_pop_fptr_t;
+
+/**
+ * cvmx_sso_rwq_psh_fptr
+ *
+ * CSR reserved addresses: (56): 0xc240..0xc3f8
+ * SSO_RWQ_PSH_FPTR = SSO Free Pointer FIFO
+ *
+ * This register is used by SW to initialize the SSO with a pool of free
+ * pointers by writing the FPTR field whenever FULL = 0. Free pointers are
+ * fetched/released from/to the pool when accessing WQE entries stored remotely
+ * (in remote linked lists).  Free pointers should be 128 byte aligned, each of
+ * 256 bytes. This register should only be used when SSO is idle.
+ *
+ * Software needs to set aside buffering for
+ *      8 + 48 + ROUNDUP(N/26)
+ *
+ * where as many as N DRAM work queue entries may be used.  The first 8 buffers
+ * are used to setup the SSO_RWQ_HEAD_PTR and SSO_RWQ_TAIL_PTRs, and the
+ * remainder are pushed via this register.
+ *
+ * IMPLEMENTATION NOTES--NOT FOR SPEC:
+ *      48 avoids false out of buffer error due to (16) FPA and in-sso FPA buffering (32)
+ *      26 is number of WAE's per 256B buffer
+ */
+union cvmx_sso_rwq_psh_fptr {
+	uint64_t u64;
+	struct cvmx_sso_rwq_psh_fptr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t full                         : 1;  /**< FIFO Full.  When set, the FPA is busy writing entries
+                                                         and software must wait before adding new entries. */
+	uint64_t cnt                          : 4;  /**< fptr_out count */
+	uint64_t reserved_38_58               : 21;
+	uint64_t fptr                         : 31; /**< Free Pointer */
+	uint64_t reserved_0_6                 : 7;
+#else
+	uint64_t reserved_0_6                 : 7;
+	uint64_t fptr                         : 31;
+	uint64_t reserved_38_58               : 21;
+	uint64_t cnt                          : 4;
+	uint64_t full                         : 1;
+#endif
+	} s;
+	struct cvmx_sso_rwq_psh_fptr_s        cn68xx;
+	struct cvmx_sso_rwq_psh_fptr_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t full                         : 1;  /**< FIFO Full.  When set, the FPA is busy writing entries
+                                                         and software must wait before adding new entries. */
+	uint64_t reserved_38_62               : 25;
+	uint64_t fptr                         : 31; /**< Free Pointer */
+	uint64_t reserved_0_6                 : 7;
+#else
+	uint64_t reserved_0_6                 : 7;
+	uint64_t fptr                         : 31;
+	uint64_t reserved_38_62               : 25;
+	uint64_t full                         : 1;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_sso_rwq_psh_fptr cvmx_sso_rwq_psh_fptr_t;
+
+/**
+ * cvmx_sso_rwq_tail_ptr#
+ *
+ * CSR reserved addresses: (56): 0xc040..0xc1f8
+ * SSO_RWQ_TAIL_PTRX = SSO Remote Queue Tail Register
+ *                (one per QOS level)
+ * Contains the ptr to the last entry of the remote linked list(s) for a particular
+ * QoS level. SW must initialize the remote linked list(s) by programming
+ * SSO_RWQ_HEAD_PTRX and SSO_RWQ_TAIL_PTRX to identical values.
+ */
+union cvmx_sso_rwq_tail_ptrx {
+	uint64_t u64;
+	struct cvmx_sso_rwq_tail_ptrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_38_63               : 26;
+	uint64_t ptr                          : 31; /**< Tail Pointer */
+	uint64_t reserved_5_6                 : 2;
+	uint64_t rctr                         : 5;  /**< Number of entries waiting to be sent out to external
+                                                         RAM (outbound queues) */
+#else
+	uint64_t rctr                         : 5;
+	uint64_t reserved_5_6                 : 2;
+	uint64_t ptr                          : 31;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_sso_rwq_tail_ptrx_s       cn68xx;
+	struct cvmx_sso_rwq_tail_ptrx_s       cn68xxp1;
+};
+typedef union cvmx_sso_rwq_tail_ptrx cvmx_sso_rwq_tail_ptrx_t;
+
+/**
+ * cvmx_sso_ts_pc
+ *
+ * SSO_TS_PC = SSO Tag Switch Performance Counter
+ *
+ * Counts the number of tag switch requests.
+ * Counter rolls over through zero when max value exceeded.
+ */
+union cvmx_sso_ts_pc {
+	uint64_t u64;
+	struct cvmx_sso_ts_pc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t ts_pc                        : 64; /**< Tag switch performance counter */
+#else
+	uint64_t ts_pc                        : 64;
+#endif
+	} s;
+	struct cvmx_sso_ts_pc_s               cn68xx;
+	struct cvmx_sso_ts_pc_s               cn68xxp1;
+};
+typedef union cvmx_sso_ts_pc cvmx_sso_ts_pc_t;
+
+/**
+ * cvmx_sso_wa_com_pc
+ *
+ * SSO_WA_COM_PC = SSO Work Add Combined Performance Counter
+ *
+ * Counts the number of add new work requests for all QOS levels.
+ * Counter rolls over through zero when max value exceeded.
+ */
+union cvmx_sso_wa_com_pc {
+	uint64_t u64;
+	struct cvmx_sso_wa_com_pc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t wa_pc                        : 64; /**< Work add combined performance counter */
+#else
+	uint64_t wa_pc                        : 64;
+#endif
+	} s;
+	struct cvmx_sso_wa_com_pc_s           cn68xx;
+	struct cvmx_sso_wa_com_pc_s           cn68xxp1;
+};
+typedef union cvmx_sso_wa_com_pc cvmx_sso_wa_com_pc_t;
+
+/**
+ * cvmx_sso_wa_pc#
+ *
+ * CSR reserved addresses: (64): 0x4200..0x43f8
+ * CSR align addresses: ===========================================================================================================
+ * SSO_WA_PCX = SSO Work Add Performance Counter
+ *             (one per QOS level)
+ *
+ * Counts the number of add new work requests for each QOS level.
+ * Counter rolls over through zero when max value exceeded.
+ */
+union cvmx_sso_wa_pcx {
+	uint64_t u64;
+	struct cvmx_sso_wa_pcx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t wa_pc                        : 64; /**< Work add performance counter for QOS level X */
+#else
+	uint64_t wa_pc                        : 64;
+#endif
+	} s;
+	struct cvmx_sso_wa_pcx_s              cn68xx;
+	struct cvmx_sso_wa_pcx_s              cn68xxp1;
+};
+typedef union cvmx_sso_wa_pcx cvmx_sso_wa_pcx_t;
+
+/**
+ * cvmx_sso_wq_int
+ *
+ * Note, the old POW offsets ran from 0x0 to 0x3f8, leaving the next available slot at 0x400.
+ * To ensure no overlap, start on 4k boundary: 0x1000.
+ * SSO_WQ_INT = SSO Work Queue Interrupt Register
+ *
+ * Contains the bits (one per group) that set work queue interrupts and are
+ * used to clear these interrupts.  For more information regarding this
+ * register, see the interrupt section of the SSO spec.
+ */
+union cvmx_sso_wq_int {
+	uint64_t u64;
+	struct cvmx_sso_wq_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t wq_int                       : 64; /**< Work queue interrupt bits
+                                                         Corresponding WQ_INT bit is set by HW whenever:
+                                                           - SSO_WQ_INT_CNTX[IQ_CNT] >=
+                                                             SSO_WQ_INT_THRX[IQ_THR] and the threshold
+                                                             interrupt is not disabled.
+                                                             SSO_WQ_IQ_DISX[IQ_DIS<X>]==1 disables the interrupt
+                                                             SSO_WQ_INT_THRX[IQ_THR]==0 disables the int.
+                                                           - SSO_WQ_INT_CNTX[DS_CNT] >=
+                                                             SSO_WQ_INT_THRX[DS_THR] and the threshold
+                                                             interrupt is not disabled
+                                                             SSO_WQ_INT_THRX[DS_THR]==0 disables the int.
+                                                           - SSO_WQ_INT_CNTX[TC_CNT]==1 when periodic
+                                                             counter SSO_WQ_INT_PC[PC]==0 and
+                                                             SSO_WQ_INT_THRX[TC_EN]==1 and at least one of:
+                                                               - SSO_WQ_INT_CNTX[IQ_CNT] > 0
+                                                               - SSO_WQ_INT_CNTX[DS_CNT] > 0 */
+#else
+	uint64_t wq_int                       : 64;
+#endif
+	} s;
+	struct cvmx_sso_wq_int_s              cn68xx;
+	struct cvmx_sso_wq_int_s              cn68xxp1;
+};
+typedef union cvmx_sso_wq_int cvmx_sso_wq_int_t;
+
+/**
+ * cvmx_sso_wq_int_cnt#
+ *
+ * CSR reserved addresses: (64): 0x7200..0x73f8
+ * CSR align addresses: ===========================================================================================================
+ * SSO_WQ_INT_CNTX = SSO Work Queue Interrupt Count Register
+ *                   (one per group)
+ *
+ * Contains a read-only copy of the counts used to trigger work queue
+ * interrupts.  For more information regarding this register, see the interrupt
+ * section.
+ */
+union cvmx_sso_wq_int_cntx {
+	uint64_t u64;
+	struct cvmx_sso_wq_int_cntx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t tc_cnt                       : 4;  /**< Time counter current value for group X
+                                                         HW sets TC_CNT to SSO_WQ_INT_THRX[TC_THR] whenever:
+                                                           - corresponding SSO_WQ_INT_CNTX[IQ_CNT]==0 and
+                                                             corresponding SSO_WQ_INT_CNTX[DS_CNT]==0
+                                                           - corresponding SSO_WQ_INT[WQ_INT<X>] is written
+                                                             with a 1 by SW
+                                                           - corresponding SSO_WQ_IQ_DIS[IQ_DIS<X>] is written
+                                                             with a 1 by SW
+                                                           - corresponding SSO_WQ_INT_THRX is written by SW
+                                                           - TC_CNT==1 and periodic counter
+                                                             SSO_WQ_INT_PC[PC]==0
+                                                         Otherwise, HW decrements TC_CNT whenever the
+                                                         periodic counter SSO_WQ_INT_PC[PC]==0.
+                                                         TC_CNT is 0 whenever SSO_WQ_INT_THRX[TC_THR]==0. */
+	uint64_t reserved_26_27               : 2;
+	uint64_t ds_cnt                       : 12; /**< De-schedule executable count for group X */
+	uint64_t reserved_12_13               : 2;
+	uint64_t iq_cnt                       : 12; /**< Input queue executable count for group X */
+#else
+	uint64_t iq_cnt                       : 12;
+	uint64_t reserved_12_13               : 2;
+	uint64_t ds_cnt                       : 12;
+	uint64_t reserved_26_27               : 2;
+	uint64_t tc_cnt                       : 4;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sso_wq_int_cntx_s         cn68xx;
+	struct cvmx_sso_wq_int_cntx_s         cn68xxp1;
+};
+typedef union cvmx_sso_wq_int_cntx cvmx_sso_wq_int_cntx_t;
+
+/**
+ * cvmx_sso_wq_int_pc
+ *
+ * CSR reserved addresses: (1): 0x1018..0x1018
+ * SSO_WQ_INT_PC = SSO Work Queue Interrupt Periodic Counter Register
+ *
+ * Contains the threshold value for the work queue interrupt periodic counter
+ * and also a read-only copy of the periodic counter.  For more information
+ * regarding this register, see the interrupt section.
+ */
+union cvmx_sso_wq_int_pc {
+	uint64_t u64;
+	struct cvmx_sso_wq_int_pc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_60_63               : 4;
+	uint64_t pc                           : 28; /**< Work queue interrupt periodic counter */
+	uint64_t reserved_28_31               : 4;
+	uint64_t pc_thr                       : 20; /**< Work queue interrupt periodic counter threshold */
+	uint64_t reserved_0_7                 : 8;
+#else
+	uint64_t reserved_0_7                 : 8;
+	uint64_t pc_thr                       : 20;
+	uint64_t reserved_28_31               : 4;
+	uint64_t pc                           : 28;
+	uint64_t reserved_60_63               : 4;
+#endif
+	} s;
+	struct cvmx_sso_wq_int_pc_s           cn68xx;
+	struct cvmx_sso_wq_int_pc_s           cn68xxp1;
+};
+typedef union cvmx_sso_wq_int_pc cvmx_sso_wq_int_pc_t;
+
+/**
+ * cvmx_sso_wq_int_thr#
+ *
+ * CSR reserved addresses: (96): 0x6100..0x63f8
+ * CSR align addresses: ===========================================================================================================
+ * SSO_WQ_INT_THR(0..63) = SSO Work Queue Interrupt Threshold Registers
+ *                         (one per group)
+ *
+ * Contains the thresholds for enabling and setting work queue interrupts.  For
+ * more information, see the interrupt section.
+ *
+ * Note: Up to 16 of the SSO's internal storage buffers can be allocated
+ * for hardware use and are therefore not available for incoming work queue
+ * entries.  Additionally, any WS that is not in the EMPTY state consumes a
+ * buffer.  Thus in a 32 PP system, it is not advisable to set either IQ_THR or
+ * DS_THR to greater than 2048 - 16 - 32*2 = 1968.  Doing so may prevent the
+ * interrupt from ever triggering.
+ *
+ * Priorities for QOS levels 0..7
+ */
+union cvmx_sso_wq_int_thrx {
+	uint64_t u64;
+	struct cvmx_sso_wq_int_thrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_33_63               : 31;
+	uint64_t tc_en                        : 1;  /**< Time counter interrupt enable for group X
+                                                         TC_EN must be zero when TC_THR==0 */
+	uint64_t tc_thr                       : 4;  /**< Time counter interrupt threshold for group X
+                                                         When TC_THR==0, SSO_WQ_INT_CNTX[TC_CNT] is zero */
+	uint64_t reserved_26_27               : 2;
+	uint64_t ds_thr                       : 12; /**< De-schedule count threshold for group X
+                                                         DS_THR==0 disables the threshold interrupt */
+	uint64_t reserved_12_13               : 2;
+	uint64_t iq_thr                       : 12; /**< Input queue count threshold for group X
+                                                         IQ_THR==0 disables the threshold interrupt */
+#else
+	uint64_t iq_thr                       : 12;
+	uint64_t reserved_12_13               : 2;
+	uint64_t ds_thr                       : 12;
+	uint64_t reserved_26_27               : 2;
+	uint64_t tc_thr                       : 4;
+	uint64_t tc_en                        : 1;
+	uint64_t reserved_33_63               : 31;
+#endif
+	} s;
+	struct cvmx_sso_wq_int_thrx_s         cn68xx;
+	struct cvmx_sso_wq_int_thrx_s         cn68xxp1;
+};
+typedef union cvmx_sso_wq_int_thrx cvmx_sso_wq_int_thrx_t;
+
+/**
+ * cvmx_sso_wq_iq_dis
+ *
+ * CSR reserved addresses: (1): 0x1008..0x1008
+ * SSO_WQ_IQ_DIS = SSO Input Queue Interrupt Temporary Disable Mask
+ *
+ * Contains the input queue interrupt temporary disable bits (one per group).
+ * For more information regarding this register, see the interrupt section.
+ */
+union cvmx_sso_wq_iq_dis {
+	uint64_t u64;
+	struct cvmx_sso_wq_iq_dis_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t iq_dis                       : 64; /**< Input queue interrupt temporary disable mask
+                                                         Corresponding SSO_WQ_INTX[WQ_INT<X>] bit cannot be
+                                                         set due to IQ_CNT/IQ_THR check when this bit is set.
+                                                         Corresponding IQ_DIS bit is cleared by HW whenever:
+                                                          - SSO_WQ_INT_CNTX[IQ_CNT] is zero, or
+                                                          - SSO_WQ_INT_CNTX[TC_CNT]==1 when periodic
+                                                            counter SSO_WQ_INT_PC[PC]==0 */
+#else
+	uint64_t iq_dis                       : 64;
+#endif
+	} s;
+	struct cvmx_sso_wq_iq_dis_s           cn68xx;
+	struct cvmx_sso_wq_iq_dis_s           cn68xxp1;
+};
+typedef union cvmx_sso_wq_iq_dis cvmx_sso_wq_iq_dis_t;
+
+/**
+ * cvmx_sso_ws_pc#
+ *
+ * CSR reserved addresses: (225): 0x3100..0x3800
+ * CSR align addresses: ===========================================================================================================
+ * SSO_WS_PCX = SSO Work Schedule Performance Counter
+ *              (one per group)
+ *
+ * Counts the number of work schedules for each group.
+ * Counter rolls over through zero when max value exceeded.
+ */
+union cvmx_sso_ws_pcx {
+	uint64_t u64;
+	struct cvmx_sso_ws_pcx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t ws_pc                        : 64; /**< Work schedule performance counter for group X */
+#else
+	uint64_t ws_pc                        : 64;
+#endif
+	} s;
+	struct cvmx_sso_ws_pcx_s              cn68xx;
+	struct cvmx_sso_ws_pcx_s              cn68xxp1;
+};
+typedef union cvmx_sso_ws_pcx cvmx_sso_ws_pcx_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-stxx-defs.h b/sys/contrib/octeon-sdk/cvmx-stxx-defs.h
index 614ea0a..4e1f5ce 100644
--- a/sys/contrib/octeon-sdk/cvmx-stxx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-stxx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_STXX_TYPEDEFS_H__
-#define __CVMX_STXX_TYPEDEFS_H__
+#ifndef __CVMX_STXX_DEFS_H__
+#define __CVMX_STXX_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_STXX_ARB_CTL(unsigned long block_id)
@@ -261,12 +261,10 @@ static inline uint64_t CVMX_STXX_STAT_PKT_XMT(unsigned long block_id)
  * sequences at any point during transmission and could be arbitrarily
  * small.  This mode is only for use in Spi4 mode.
  */
-union cvmx_stxx_arb_ctl
-{
+union cvmx_stxx_arb_ctl {
 	uint64_t u64;
-	struct cvmx_stxx_arb_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_stxx_arb_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t mintrn                       : 1;  /**< Hold off training cycles until STX_MIN_BST[MINB]
                                                          is satisfied */
@@ -309,12 +307,10 @@ typedef union cvmx_stxx_arb_ctl cvmx_stxx_arb_ctl_t;
  * This register will be cleared when software writes all '1's to
  * the STX_BCKPRS_CNT.
  */
-union cvmx_stxx_bckprs_cnt
-{
+union cvmx_stxx_bckprs_cnt {
 	uint64_t u64;
-	struct cvmx_stxx_bckprs_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_stxx_bckprs_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< Number of cycles when back-pressure is received
                                                          for port defined in STX_STAT_CTL[BCKPRS] */
@@ -342,12 +338,10 @@ typedef union cvmx_stxx_bckprs_cnt cvmx_stxx_bckprs_cnt_t;
  * completely setup before writing the Interface enable (INF_EN) and
  * Status channel enabled (ST_EN) asserted.
  */
-union cvmx_stxx_com_ctl
-{
+union cvmx_stxx_com_ctl {
 	uint64_t u64;
-	struct cvmx_stxx_com_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_stxx_com_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t st_en                        : 1;  /**< Status channel enabled */
 	uint64_t reserved_1_2                 : 2;
@@ -380,12 +374,10 @@ typedef union cvmx_stxx_com_ctl cvmx_stxx_com_ctl_t;
  *   states.  The expected range is 1-15 cycles with the value of 0 meaning
  *   disabled.
  */
-union cvmx_stxx_dip_cnt
-{
+union cvmx_stxx_dip_cnt {
 	uint64_t u64;
-	struct cvmx_stxx_dip_cnt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_stxx_dip_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t frmmax                       : 4;  /**< Number of consecutive unexpected framing patterns
                                                          before loss of sync */
@@ -410,12 +402,10 @@ typedef union cvmx_stxx_dip_cnt cvmx_stxx_dip_cnt_t;
  * STX_IGN_CAL - Ignore Calendar Status from Spi4 Status Channel
  *
  */
-union cvmx_stxx_ign_cal
-{
+union cvmx_stxx_ign_cal {
 	uint64_t u64;
-	struct cvmx_stxx_ign_cal_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_stxx_ign_cal_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t igntpa                       : 16; /**< Ignore Calendar Status from Spi4 Status Channel
                                                           per Spi4 port
@@ -440,12 +430,10 @@ typedef union cvmx_stxx_ign_cal cvmx_stxx_ign_cal_t;
  * If the bit is enabled, then the coresponding exception condition will
  * result in an interrupt to the system.
  */
-union cvmx_stxx_int_msk
-{
+union cvmx_stxx_int_msk {
 	uint64_t u64;
-	struct cvmx_stxx_int_msk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_stxx_int_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t frmerr                       : 1;  /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */
 	uint64_t unxfrm                       : 1;  /**< Unexpected framing sequence */
@@ -535,12 +523,10 @@ typedef union cvmx_stxx_int_msk cvmx_stxx_int_msk_t;
  *   NOSYNC, and FRMERR error conditions all have their bits set in the
  *   STX_INT_SYNC register.
  */
-union cvmx_stxx_int_reg
-{
+union cvmx_stxx_int_reg {
 	uint64_t u64;
-	struct cvmx_stxx_int_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_stxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t syncerr                      : 1;  /**< Interface encountered a fatal error */
 	uint64_t frmerr                       : 1;  /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */
@@ -585,12 +571,10 @@ typedef union cvmx_stxx_int_reg cvmx_stxx_int_reg_t;
  * synchronize the bus on other conditions, but this is the minimum
  * recommended set.
  */
-union cvmx_stxx_int_sync
-{
+union cvmx_stxx_int_sync {
 	uint64_t u64;
-	struct cvmx_stxx_int_sync_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_stxx_int_sync_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t frmerr                       : 1;  /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */
 	uint64_t unxfrm                       : 1;  /**< Unexpected framing sequence */
@@ -625,12 +609,10 @@ typedef union cvmx_stxx_int_sync cvmx_stxx_int_sync_t;
  * STX_MIN_BST - Min Burst to enforce when inserting training sequence
  *
  */
-union cvmx_stxx_min_bst
-{
+union cvmx_stxx_min_bst {
 	uint64_t u64;
-	struct cvmx_stxx_min_bst_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_stxx_min_bst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t minb                         : 9;  /**< When STX_ARB_CTL[MINTRN] is set, MINB indicates
                                                          the number of 8B blocks to send before inserting
@@ -675,12 +657,10 @@ typedef union cvmx_stxx_min_bst cvmx_stxx_min_bst_t;
  *     completely setup before writing the Interface enable (INF_EN) and
  *     Status channel enabled (ST_EN) asserted.
  */
-union cvmx_stxx_spi4_calx
-{
+union cvmx_stxx_spi4_calx {
 	uint64_t u64;
-	struct cvmx_stxx_spi4_calx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_stxx_spi4_calx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t oddpar                       : 1;  /**< Odd parity over STX_SPI4_CAL[15:0]
                                                          (^STX_SPI4_CAL[16:0] === 1'b1)                  |   $NS       NS */
@@ -734,12 +714,10 @@ typedef union cvmx_stxx_spi4_calx cvmx_stxx_spi4_calx_t;
  *      sequences at any point during transmission and could be arbitrarily
  *      small.  This mode is only for use in Spi4 mode.
  */
-union cvmx_stxx_spi4_dat
-{
+union cvmx_stxx_spi4_dat {
 	uint64_t u64;
-	struct cvmx_stxx_spi4_dat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_stxx_spi4_dat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t alpha                        : 16; /**< alpha (from spi4.2 spec) */
 	uint64_t max_t                        : 16; /**< DATA_MAX_T (from spi4.2 spec) */
@@ -772,12 +750,10 @@ typedef union cvmx_stxx_spi4_dat cvmx_stxx_spi4_dat_t;
  *
  * Current rev will only support LVTTL status IO.
  */
-union cvmx_stxx_spi4_stat
-{
+union cvmx_stxx_spi4_stat {
 	uint64_t u64;
-	struct cvmx_stxx_spi4_stat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_stxx_spi4_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t m                            : 8;  /**< CALENDAR_M (from spi4.2 spec) */
 	uint64_t reserved_7_7                 : 1;
@@ -799,12 +775,10 @@ typedef union cvmx_stxx_spi4_stat cvmx_stxx_spi4_stat_t;
 /**
  * cvmx_stx#_stat_bytes_hi
  */
-union cvmx_stxx_stat_bytes_hi
-{
+union cvmx_stxx_stat_bytes_hi {
 	uint64_t u64;
-	struct cvmx_stxx_stat_bytes_hi_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_stxx_stat_bytes_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< Number of bytes sent (CNT[63:32]) */
 #else
@@ -822,12 +796,10 @@ typedef union cvmx_stxx_stat_bytes_hi cvmx_stxx_stat_bytes_hi_t;
 /**
  * cvmx_stx#_stat_bytes_lo
  */
-union cvmx_stxx_stat_bytes_lo
-{
+union cvmx_stxx_stat_bytes_lo {
 	uint64_t u64;
-	struct cvmx_stxx_stat_bytes_lo_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_stxx_stat_bytes_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< Number of bytes sent (CNT[31:0]) */
 #else
@@ -845,12 +817,10 @@ typedef union cvmx_stxx_stat_bytes_lo cvmx_stxx_stat_bytes_lo_t;
 /**
  * cvmx_stx#_stat_ctl
  */
-union cvmx_stxx_stat_ctl
-{
+union cvmx_stxx_stat_ctl {
 	uint64_t u64;
-	struct cvmx_stxx_stat_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_stxx_stat_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t clr                          : 1;  /**< Clear all statistics counters
                                                          - STX_STAT_PKT_XMT
@@ -873,12 +843,10 @@ typedef union cvmx_stxx_stat_ctl cvmx_stxx_stat_ctl_t;
 /**
  * cvmx_stx#_stat_pkt_xmt
  */
-union cvmx_stxx_stat_pkt_xmt
-{
+union cvmx_stxx_stat_pkt_xmt {
 	uint64_t u64;
-	struct cvmx_stxx_stat_pkt_xmt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_stxx_stat_pkt_xmt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t cnt                          : 32; /**< Number of packets sent */
 #else
diff --git a/sys/contrib/octeon-sdk/cvmx-swap.h b/sys/contrib/octeon-sdk/cvmx-swap.h
index 38cbaab..553a87f 100644
--- a/sys/contrib/octeon-sdk/cvmx-swap.h
+++ b/sys/contrib/octeon-sdk/cvmx-swap.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -106,7 +106,7 @@ static inline uint64_t cvmx_swap64(uint64_t x)
 }
 
 
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
 
 #define cvmx_cpu_to_le16(x) cvmx_swap16(x)
 #define cvmx_cpu_to_le32(x) cvmx_swap32(x)
diff --git a/sys/contrib/octeon-sdk/cvmx-sysinfo.c b/sys/contrib/octeon-sdk/cvmx-sysinfo.c
index 1522c69..c2d1ddf 100644
--- a/sys/contrib/octeon-sdk/cvmx-sysinfo.c
+++ b/sys/contrib/octeon-sdk/cvmx-sysinfo.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * This module provides system/board/application information obtained by the bootloader.
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
@@ -117,6 +117,27 @@ struct cvmx_sysinfo *cvmx_sysinfo_get(void)
 {
     return &(state.sysinfo);
 }
+
+void cvmx_sysinfo_add_self_to_core_mask(void)
+{
+    int core = cvmx_get_core_num();
+    uint32_t core_mask = 1 << core;
+    
+    cvmx_spinlock_lock(&state.lock);
+    state.sysinfo.core_mask = state.sysinfo.core_mask | core_mask;
+    cvmx_spinlock_unlock(&state.lock);
+}
+
+void cvmx_sysinfo_remove_self_from_core_mask(void)
+{
+    int core = cvmx_get_core_num();
+    uint32_t core_mask = 1 << core;
+    
+    cvmx_spinlock_lock(&state.lock);
+    state.sysinfo.core_mask = state.sysinfo.core_mask & ~core_mask;
+    cvmx_spinlock_unlock(&state.lock);
+}
+
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 EXPORT_SYMBOL(cvmx_sysinfo_get);
 #endif
@@ -195,7 +216,7 @@ void cvmx_sysinfo_linux_userspace_initialize(void)
             sscanf(valueS, "%lli", &value);
 
             if (strcmp(field, "dram_size:") == 0)
-                system_info->system_dram_size = value;
+                system_info->system_dram_size = value << 20;
             else if (strcmp(field, "phy_mem_desc_addr:") == 0)
                 system_info->phy_mem_desc_addr = value;
             else if (strcmp(field, "eclock_hz:") == 0)
@@ -220,6 +241,8 @@ void cvmx_sysinfo_linux_userspace_initialize(void)
             }
             else if (strcmp(field, "mac_addr_count:") == 0)
                 system_info->mac_addr_count = value;
+            else if (strcmp(field, "fdt_addr:") == 0)
+                system_info->fdt_addr = UNMAPPED_PTR(value);
             else if (strcmp(field, "32bit_shared_mem_base:") == 0)
                 linux_mem32_min = value;
             else if (strcmp(field, "32bit_shared_mem_size:") == 0)
@@ -231,6 +254,11 @@ void cvmx_sysinfo_linux_userspace_initialize(void)
         }
     }
 
+    /*
+     * set up the feature map.
+     */
+    octeon_feature_init();
+
     system_info->cpu_clock_hz = cvmx_clock_get_rate(CVMX_CLOCK_CORE);
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-sysinfo.h b/sys/contrib/octeon-sdk/cvmx-sysinfo.h
index 0daa9cf..aed469e 100644
--- a/sys/contrib/octeon-sdk/cvmx-sysinfo.h
+++ b/sys/contrib/octeon-sdk/cvmx-sysinfo.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -43,7 +43,7 @@
  *
  * This module provides system/board information obtained by the bootloader.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
@@ -115,6 +115,7 @@ struct cvmx_sysinfo {
 	uint32_t dfa_ref_clock_hz;  /**< DFA reference clock in hz (if applicable)*/
 	uint32_t bootloader_config_flags;  /**< configuration flags from bootloader */
 	uint8_t  console_uart_num;         /** < Uart number used for console */
+     uint64_t fdt_addr; /** pointer to device tree */
 };
 
 #ifndef CVMX_BUILD_FOR_LINUX_KERNEL
@@ -132,6 +133,19 @@ typedef struct cvmx_sysinfo cvmx_sysinfo_t;
 
 extern struct cvmx_sysinfo *cvmx_sysinfo_get(void);
 
+/**
+ * This function adds the current cpu to sysinfo coremask
+ * 
+ */
+
+void cvmx_sysinfo_add_self_to_core_mask(void);
+
+/**
+ * This function removes the current cpu to sysinfo coremask
+ * 
+ */
+void cvmx_sysinfo_remove_self_from_core_mask(void);
+
 #ifndef CVMX_BUILD_FOR_LINUX_KERNEL
 /**
  * This function is used in non-simple executive environments (such as Linux kernel, u-boot, etc.)
diff --git a/sys/contrib/octeon-sdk/cvmx-thunder.c b/sys/contrib/octeon-sdk/cvmx-thunder.c
index 8032c18..31c7805 100644
--- a/sys/contrib/octeon-sdk/cvmx-thunder.c
+++ b/sys/contrib/octeon-sdk/cvmx-thunder.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Interface to the Thunder specific devices
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-thunder.h b/sys/contrib/octeon-sdk/cvmx-thunder.h
index 3b63563..f023c01 100644
--- a/sys/contrib/octeon-sdk/cvmx-thunder.h
+++ b/sys/contrib/octeon-sdk/cvmx-thunder.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -51,7 +51,7 @@
  *
  * Interface to the Thunder specific devices
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-tim-defs.h b/sys/contrib/octeon-sdk/cvmx-tim-defs.h
index 90d684f..351f10c 100644
--- a/sys/contrib/octeon-sdk/cvmx-tim-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-tim-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,19 +49,647 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_TIM_TYPEDEFS_H__
-#define __CVMX_TIM_TYPEDEFS_H__
+#ifndef __CVMX_TIM_DEFS_H__
+#define __CVMX_TIM_DEFS_H__
 
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_BIST_RESULT CVMX_TIM_BIST_RESULT_FUNC()
+static inline uint64_t CVMX_TIM_BIST_RESULT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_TIM_BIST_RESULT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058000020ull);
+}
+#else
+#define CVMX_TIM_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180058000020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_DBG2 CVMX_TIM_DBG2_FUNC()
+static inline uint64_t CVMX_TIM_DBG2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_TIM_DBG2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800580000A0ull);
+}
+#else
+#define CVMX_TIM_DBG2 (CVMX_ADD_IO_SEG(0x00011800580000A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_DBG3 CVMX_TIM_DBG3_FUNC()
+static inline uint64_t CVMX_TIM_DBG3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_TIM_DBG3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800580000A8ull);
+}
+#else
+#define CVMX_TIM_DBG3 (CVMX_ADD_IO_SEG(0x00011800580000A8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_ECC_CFG CVMX_TIM_ECC_CFG_FUNC()
+static inline uint64_t CVMX_TIM_ECC_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_TIM_ECC_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058000018ull);
+}
+#else
+#define CVMX_TIM_ECC_CFG (CVMX_ADD_IO_SEG(0x0001180058000018ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_FR_RN_TT CVMX_TIM_FR_RN_TT_FUNC()
+static inline uint64_t CVMX_TIM_FR_RN_TT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_TIM_FR_RN_TT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058000010ull);
+}
+#else
+#define CVMX_TIM_FR_RN_TT (CVMX_ADD_IO_SEG(0x0001180058000010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_GPIO_EN CVMX_TIM_GPIO_EN_FUNC()
+static inline uint64_t CVMX_TIM_GPIO_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_TIM_GPIO_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058000080ull);
+}
+#else
+#define CVMX_TIM_GPIO_EN (CVMX_ADD_IO_SEG(0x0001180058000080ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_INT0 CVMX_TIM_INT0_FUNC()
+static inline uint64_t CVMX_TIM_INT0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_TIM_INT0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058000030ull);
+}
+#else
+#define CVMX_TIM_INT0 (CVMX_ADD_IO_SEG(0x0001180058000030ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_INT0_EN CVMX_TIM_INT0_EN_FUNC()
+static inline uint64_t CVMX_TIM_INT0_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_TIM_INT0_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058000038ull);
+}
+#else
+#define CVMX_TIM_INT0_EN (CVMX_ADD_IO_SEG(0x0001180058000038ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_INT0_EVENT CVMX_TIM_INT0_EVENT_FUNC()
+static inline uint64_t CVMX_TIM_INT0_EVENT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_TIM_INT0_EVENT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058000040ull);
+}
+#else
+#define CVMX_TIM_INT0_EVENT (CVMX_ADD_IO_SEG(0x0001180058000040ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_INT_ECCERR CVMX_TIM_INT_ECCERR_FUNC()
+static inline uint64_t CVMX_TIM_INT_ECCERR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_TIM_INT_ECCERR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058000060ull);
+}
+#else
+#define CVMX_TIM_INT_ECCERR (CVMX_ADD_IO_SEG(0x0001180058000060ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_INT_ECCERR_EN CVMX_TIM_INT_ECCERR_EN_FUNC()
+static inline uint64_t CVMX_TIM_INT_ECCERR_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_TIM_INT_ECCERR_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058000068ull);
+}
+#else
+#define CVMX_TIM_INT_ECCERR_EN (CVMX_ADD_IO_SEG(0x0001180058000068ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_INT_ECCERR_EVENT0 CVMX_TIM_INT_ECCERR_EVENT0_FUNC()
+static inline uint64_t CVMX_TIM_INT_ECCERR_EVENT0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_TIM_INT_ECCERR_EVENT0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058000070ull);
+}
+#else
+#define CVMX_TIM_INT_ECCERR_EVENT0 (CVMX_ADD_IO_SEG(0x0001180058000070ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_INT_ECCERR_EVENT1 CVMX_TIM_INT_ECCERR_EVENT1_FUNC()
+static inline uint64_t CVMX_TIM_INT_ECCERR_EVENT1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_TIM_INT_ECCERR_EVENT1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058000078ull);
+}
+#else
+#define CVMX_TIM_INT_ECCERR_EVENT1 (CVMX_ADD_IO_SEG(0x0001180058000078ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_MEM_DEBUG0 CVMX_TIM_MEM_DEBUG0_FUNC()
+static inline uint64_t CVMX_TIM_MEM_DEBUG0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_TIM_MEM_DEBUG0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058001100ull);
+}
+#else
 #define CVMX_TIM_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180058001100ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_MEM_DEBUG1 CVMX_TIM_MEM_DEBUG1_FUNC()
+static inline uint64_t CVMX_TIM_MEM_DEBUG1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_TIM_MEM_DEBUG1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058001108ull);
+}
+#else
 #define CVMX_TIM_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180058001108ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_MEM_DEBUG2 CVMX_TIM_MEM_DEBUG2_FUNC()
+static inline uint64_t CVMX_TIM_MEM_DEBUG2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_TIM_MEM_DEBUG2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058001110ull);
+}
+#else
 #define CVMX_TIM_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180058001110ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_MEM_RING0 CVMX_TIM_MEM_RING0_FUNC()
+static inline uint64_t CVMX_TIM_MEM_RING0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_TIM_MEM_RING0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058001000ull);
+}
+#else
 #define CVMX_TIM_MEM_RING0 (CVMX_ADD_IO_SEG(0x0001180058001000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_MEM_RING1 CVMX_TIM_MEM_RING1_FUNC()
+static inline uint64_t CVMX_TIM_MEM_RING1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_TIM_MEM_RING1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058001008ull);
+}
+#else
 #define CVMX_TIM_MEM_RING1 (CVMX_ADD_IO_SEG(0x0001180058001008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_REG_BIST_RESULT CVMX_TIM_REG_BIST_RESULT_FUNC()
+static inline uint64_t CVMX_TIM_REG_BIST_RESULT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_TIM_REG_BIST_RESULT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058000080ull);
+}
+#else
 #define CVMX_TIM_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180058000080ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_REG_ERROR CVMX_TIM_REG_ERROR_FUNC()
+static inline uint64_t CVMX_TIM_REG_ERROR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_TIM_REG_ERROR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058000088ull);
+}
+#else
 #define CVMX_TIM_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180058000088ull))
+#endif
 #define CVMX_TIM_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180058000000ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_REG_INT_MASK CVMX_TIM_REG_INT_MASK_FUNC()
+static inline uint64_t CVMX_TIM_REG_INT_MASK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_TIM_REG_INT_MASK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058000090ull);
+}
+#else
 #define CVMX_TIM_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180058000090ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TIM_REG_READ_IDX CVMX_TIM_REG_READ_IDX_FUNC()
+static inline uint64_t CVMX_TIM_REG_READ_IDX_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_TIM_REG_READ_IDX not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180058000008ull);
+}
+#else
 #define CVMX_TIM_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180058000008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TIM_RINGX_CTL0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_TIM_RINGX_CTL0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180058002000ull) + ((offset) & 63) * 8;
+}
+#else
+#define CVMX_TIM_RINGX_CTL0(offset) (CVMX_ADD_IO_SEG(0x0001180058002000ull) + ((offset) & 63) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TIM_RINGX_CTL1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_TIM_RINGX_CTL1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180058002400ull) + ((offset) & 63) * 8;
+}
+#else
+#define CVMX_TIM_RINGX_CTL1(offset) (CVMX_ADD_IO_SEG(0x0001180058002400ull) + ((offset) & 63) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TIM_RINGX_CTL2(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_TIM_RINGX_CTL2(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180058002800ull) + ((offset) & 63) * 8;
+}
+#else
+#define CVMX_TIM_RINGX_CTL2(offset) (CVMX_ADD_IO_SEG(0x0001180058002800ull) + ((offset) & 63) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TIM_RINGX_DBG0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_TIM_RINGX_DBG0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180058003000ull) + ((offset) & 63) * 8;
+}
+#else
+#define CVMX_TIM_RINGX_DBG0(offset) (CVMX_ADD_IO_SEG(0x0001180058003000ull) + ((offset) & 63) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TIM_RINGX_DBG1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_TIM_RINGX_DBG1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180058001200ull) + ((offset) & 63) * 8;
+}
+#else
+#define CVMX_TIM_RINGX_DBG1(offset) (CVMX_ADD_IO_SEG(0x0001180058001200ull) + ((offset) & 63) * 8)
+#endif
+
+/**
+ * cvmx_tim_bist_result
+ *
+ * Notes:
+ * Access to the internal BiST results
+ * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
+ */
+union cvmx_tim_bist_result {
+	uint64_t u64;
+	struct cvmx_tim_bist_result_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_3_63                : 61;
+	uint64_t wqe_fifo                     : 1;  /**< BIST result of the NCB_WQE FIFO (0=pass, !0=fail) */
+	uint64_t lslr_fifo                    : 1;  /**< BIST result of the NCB_LSLR FIFO (0=pass, !0=fail) */
+	uint64_t rds_mem                      : 1;  /**< BIST result of the RDS memory (0=pass, !0=fail) */
+#else
+	uint64_t rds_mem                      : 1;
+	uint64_t lslr_fifo                    : 1;
+	uint64_t wqe_fifo                     : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_tim_bist_result_s         cn68xx;
+	struct cvmx_tim_bist_result_s         cn68xxp1;
+};
+typedef union cvmx_tim_bist_result cvmx_tim_bist_result_t;
+
+/**
+ * cvmx_tim_dbg2
+ */
+union cvmx_tim_dbg2 {
+	uint64_t u64;
+	struct cvmx_tim_dbg2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t mem_alloc_reg                : 8;  /**< NCB Load Memory Allocation status */
+	uint64_t reserved_51_55               : 5;
+	uint64_t gnt_fifo_level               : 3;  /**< NCB GRANT FIFO level */
+	uint64_t reserved_45_47               : 3;
+	uint64_t rwf_fifo_level               : 5;  /**< NCB requests FIFO level */
+	uint64_t wqe_fifo_level               : 8;  /**< NCB WQE LD FIFO level */
+	uint64_t reserved_16_31               : 16;
+	uint64_t fsm3_state                   : 4;  /**< FSM 3 current state */
+	uint64_t fsm2_state                   : 4;  /**< FSM 2 current state */
+	uint64_t fsm1_state                   : 4;  /**< FSM 1 current state */
+	uint64_t fsm0_state                   : 4;  /**< FSM 0 current state */
+#else
+	uint64_t fsm0_state                   : 4;
+	uint64_t fsm1_state                   : 4;
+	uint64_t fsm2_state                   : 4;
+	uint64_t fsm3_state                   : 4;
+	uint64_t reserved_16_31               : 16;
+	uint64_t wqe_fifo_level               : 8;
+	uint64_t rwf_fifo_level               : 5;
+	uint64_t reserved_45_47               : 3;
+	uint64_t gnt_fifo_level               : 3;
+	uint64_t reserved_51_55               : 5;
+	uint64_t mem_alloc_reg                : 8;
+#endif
+	} s;
+	struct cvmx_tim_dbg2_s                cn68xx;
+	struct cvmx_tim_dbg2_s                cn68xxp1;
+};
+typedef union cvmx_tim_dbg2 cvmx_tim_dbg2_t;
+
+/**
+ * cvmx_tim_dbg3
+ */
+union cvmx_tim_dbg3 {
+	uint64_t u64;
+	struct cvmx_tim_dbg3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t rings_pending_vec            : 64; /**< Pending rings vector. Indicates which ring in TIM are
+                                                         pending traversal. Bit 0 represents ring 0 while bit 63
+                                                         represents ring 63. */
+#else
+	uint64_t rings_pending_vec            : 64;
+#endif
+	} s;
+	struct cvmx_tim_dbg3_s                cn68xx;
+	struct cvmx_tim_dbg3_s                cn68xxp1;
+};
+typedef union cvmx_tim_dbg3 cvmx_tim_dbg3_t;
+
+/**
+ * cvmx_tim_ecc_cfg
+ */
+union cvmx_tim_ecc_cfg {
+	uint64_t u64;
+	struct cvmx_tim_ecc_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_3_63                : 61;
+	uint64_t ecc_flp_syn                  : 2;  /**< ECC Flip Syndrome. Flip the ECC's syndrome for testing
+                                                         purposes, to test SBE and DBE ECC interrupts. */
+	uint64_t ecc_en                       : 1;  /**< Enable ECC correction of the Ring Data Structre memory.
+                                                         ECC is enabled by default. */
+#else
+	uint64_t ecc_en                       : 1;
+	uint64_t ecc_flp_syn                  : 2;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_tim_ecc_cfg_s             cn68xx;
+	struct cvmx_tim_ecc_cfg_s             cn68xxp1;
+};
+typedef union cvmx_tim_ecc_cfg cvmx_tim_ecc_cfg_t;
+
+/**
+ * cvmx_tim_fr_rn_tt
+ *
+ * Notes:
+ * For every 64 entries in a bucket interval should be at
+ * least 1us.
+ * Minimal recommended value for Threshold register is 1us
+ */
+union cvmx_tim_fr_rn_tt {
+	uint64_t u64;
+	struct cvmx_tim_fr_rn_tt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t thld_gp                      : 22; /**< Free Running Timer Threshold. Defines the reset value
+                                                         for the free running timer when it reaches zero during
+                                                         it's count down. This threshold only applies to the
+                                                         timer that is driven by GPIO edge as defined at
+                                                         TIM_REG_FLAGS.GPIO_EDGE
+                                                         ***NOTE: Added in pass 2.0 */
+	uint64_t reserved_22_31               : 10;
+	uint64_t fr_rn_tt                     : 22; /**< Free Running Timer Threshold. Defines the reset value
+                                                         for the free running timer when it reaches zero during
+                                                         it's count down.
+                                                         FR_RN_TT will be used in both cases where free running
+                                                         clock is driven externally or internally.
+                                                         Interval programming guidelines:
+                                                         For every 64 entries in a bucket interval should be at
+                                                         least 1us.
+                                                         Minimal recommended value for FR_RN_TT is 1us. */
+#else
+	uint64_t fr_rn_tt                     : 22;
+	uint64_t reserved_22_31               : 10;
+	uint64_t thld_gp                      : 22;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_tim_fr_rn_tt_s            cn68xx;
+	struct cvmx_tim_fr_rn_tt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_22_63               : 42;
+	uint64_t fr_rn_tt                     : 22; /**< Free Running Timer Threshold. Defines the reset value
+                                                         for the free running timer when it reaches zero during
+                                                         it's count down.
+                                                         FR_RN_TT will be used in both cases where free running
+                                                         clock is driven externally or internally.
+                                                         Interval programming guidelines:
+                                                         For every 64 entries in a bucket interval should be at
+                                                         least 1us.
+                                                         Minimal recommended value for FR_RN_TT is 1us. */
+#else
+	uint64_t fr_rn_tt                     : 22;
+	uint64_t reserved_22_63               : 42;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_tim_fr_rn_tt cvmx_tim_fr_rn_tt_t;
+
+/**
+ * cvmx_tim_gpio_en
+ */
+union cvmx_tim_gpio_en {
+	uint64_t u64;
+	struct cvmx_tim_gpio_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t gpio_en                      : 64; /**< Each bit correspond to rings [63:0] respectively.
+                                                         This register reflects the values written to
+                                                         TIM_RING63..0_CTL1.ENA_GPIO
+                                                         ***NOTE: Added in pass 2.0 for debug only. RESERVED */
+#else
+	uint64_t gpio_en                      : 64;
+#endif
+	} s;
+	struct cvmx_tim_gpio_en_s             cn68xx;
+};
+typedef union cvmx_tim_gpio_en cvmx_tim_gpio_en_t;
+
+/**
+ * cvmx_tim_int0
+ *
+ * Notes:
+ * A ring is in error if its interval has elapsed more than once without having been serviced. This is
+ * usually a programming error where number of entries in the bucket is too large for the interval
+ * specified for the ring.
+ * Any bit in the INT field should be cleared by writing '1' to it.
+ */
+union cvmx_tim_int0 {
+	uint64_t u64;
+	struct cvmx_tim_int0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t int0                         : 64; /**< Interrupt bit per ring. Each bit indicates the
+                                                         ring number in error. Each bit in this reg is set
+                                                         regardless of TIM_INT0_EN value. */
+#else
+	uint64_t int0                         : 64;
+#endif
+	} s;
+	struct cvmx_tim_int0_s                cn68xx;
+	struct cvmx_tim_int0_s                cn68xxp1;
+};
+typedef union cvmx_tim_int0 cvmx_tim_int0_t;
+
+/**
+ * cvmx_tim_int0_en
+ *
+ * Notes:
+ * When bit at TIM_INT0_EN is set it enables the corresponding TIM_INTO's bit for interrupt generation
+ * If enable bit is cleared the corresponding bit at TIM_INT0 will still be set.
+ * Interrupt to the cores is generated by : |(TIM_INT0 & TIM_INT0_EN0)
+ */
+union cvmx_tim_int0_en {
+	uint64_t u64;
+	struct cvmx_tim_int0_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t int0_en                      : 64; /**< Bit enable corresponding to TIM_INT0. */
+#else
+	uint64_t int0_en                      : 64;
+#endif
+	} s;
+	struct cvmx_tim_int0_en_s             cn68xx;
+	struct cvmx_tim_int0_en_s             cn68xxp1;
+};
+typedef union cvmx_tim_int0_en cvmx_tim_int0_en_t;
+
+/**
+ * cvmx_tim_int0_event
+ */
+union cvmx_tim_int0_event {
+	uint64_t u64;
+	struct cvmx_tim_int0_event_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_6_63                : 58;
+	uint64_t ring_id                      : 6;  /**< The first Ring ID where an interrupt occurred. */
+#else
+	uint64_t ring_id                      : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_tim_int0_event_s          cn68xx;
+	struct cvmx_tim_int0_event_s          cn68xxp1;
+};
+typedef union cvmx_tim_int0_event cvmx_tim_int0_event_t;
+
+/**
+ * cvmx_tim_int_eccerr
+ *
+ * Notes:
+ * Each bit in this reg is set regardless of TIM_INT_ECCERR_EN value.
+ *
+ */
+union cvmx_tim_int_eccerr {
+	uint64_t u64;
+	struct cvmx_tim_int_eccerr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_2_63                : 62;
+	uint64_t dbe                          : 1;  /**< TIM RDS memory had a Double Bit Error */
+	uint64_t sbe                          : 1;  /**< TIM RDS memory had a Single Bit Error */
+#else
+	uint64_t sbe                          : 1;
+	uint64_t dbe                          : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_tim_int_eccerr_s          cn68xx;
+	struct cvmx_tim_int_eccerr_s          cn68xxp1;
+};
+typedef union cvmx_tim_int_eccerr cvmx_tim_int_eccerr_t;
+
+/**
+ * cvmx_tim_int_eccerr_en
+ *
+ * Notes:
+ * When mask bit is set, the corresponding bit in TIM_INT_ECCERR is enabled. If mask bit is cleared the
+ * corresponding bit in TIM_INT_ECCERR will still be set but interrupt will not be reported.
+ */
+union cvmx_tim_int_eccerr_en {
+	uint64_t u64;
+	struct cvmx_tim_int_eccerr_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_2_63                : 62;
+	uint64_t dbe_en                       : 1;  /**< Bit mask corresponding to TIM_REG_ECCERR.DBE */
+	uint64_t sbe_en                       : 1;  /**< Bit mask corresponding to TIM_REG_ECCERR.SBE */
+#else
+	uint64_t sbe_en                       : 1;
+	uint64_t dbe_en                       : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_tim_int_eccerr_en_s       cn68xx;
+	struct cvmx_tim_int_eccerr_en_s       cn68xxp1;
+};
+typedef union cvmx_tim_int_eccerr_en cvmx_tim_int_eccerr_en_t;
+
+/**
+ * cvmx_tim_int_eccerr_event0
+ */
+union cvmx_tim_int_eccerr_event0 {
+	uint64_t u64;
+	struct cvmx_tim_int_eccerr_event0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t synd                         : 7;  /**< ECC Syndrome */
+	uint64_t add                          : 8;  /**< Memory address where the Error occurred. */
+#else
+	uint64_t add                          : 8;
+	uint64_t synd                         : 7;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_tim_int_eccerr_event0_s   cn68xx;
+	struct cvmx_tim_int_eccerr_event0_s   cn68xxp1;
+};
+typedef union cvmx_tim_int_eccerr_event0 cvmx_tim_int_eccerr_event0_t;
+
+/**
+ * cvmx_tim_int_eccerr_event1
+ */
+union cvmx_tim_int_eccerr_event1 {
+	uint64_t u64;
+	struct cvmx_tim_int_eccerr_event1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_55_63               : 9;
+	uint64_t org_ecc                      : 7;  /**< Original ECC bits where the error occured. */
+	uint64_t org_rds_dat                  : 48; /**< Memory original data where the error occured. */
+#else
+	uint64_t org_rds_dat                  : 48;
+	uint64_t org_ecc                      : 7;
+	uint64_t reserved_55_63               : 9;
+#endif
+	} s;
+	struct cvmx_tim_int_eccerr_event1_s   cn68xx;
+	struct cvmx_tim_int_eccerr_event1_s   cn68xxp1;
+};
+typedef union cvmx_tim_int_eccerr_event1 cvmx_tim_int_eccerr_event1_t;
 
 /**
  * cvmx_tim_mem_debug0
@@ -71,12 +699,10 @@
  * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_tim_mem_debug0
-{
+union cvmx_tim_mem_debug0 {
 	uint64_t u64;
-	struct cvmx_tim_mem_debug0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_tim_mem_debug0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t ena                          : 1;  /**< Ring timer enable */
 	uint64_t reserved_46_46               : 1;
@@ -110,8 +736,11 @@ union cvmx_tim_mem_debug0
 	struct cvmx_tim_mem_debug0_s          cn56xxp1;
 	struct cvmx_tim_mem_debug0_s          cn58xx;
 	struct cvmx_tim_mem_debug0_s          cn58xxp1;
+	struct cvmx_tim_mem_debug0_s          cn61xx;
 	struct cvmx_tim_mem_debug0_s          cn63xx;
 	struct cvmx_tim_mem_debug0_s          cn63xxp1;
+	struct cvmx_tim_mem_debug0_s          cn66xx;
+	struct cvmx_tim_mem_debug0_s          cnf71xx;
 };
 typedef union cvmx_tim_mem_debug0 cvmx_tim_mem_debug0_t;
 
@@ -123,12 +752,10 @@ typedef union cvmx_tim_mem_debug0 cvmx_tim_mem_debug0_t;
  * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_tim_mem_debug1
-{
+union cvmx_tim_mem_debug1 {
 	uint64_t u64;
-	struct cvmx_tim_mem_debug1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_tim_mem_debug1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t bucket                       : 13; /**< Current bucket[12:0]
                                                          Reset to 0 whenever TIM_MEM_RING0 is written for
                                                          the ring. Incremented (modulo BSIZE) once per
@@ -153,8 +780,11 @@ union cvmx_tim_mem_debug1
 	struct cvmx_tim_mem_debug1_s          cn56xxp1;
 	struct cvmx_tim_mem_debug1_s          cn58xx;
 	struct cvmx_tim_mem_debug1_s          cn58xxp1;
+	struct cvmx_tim_mem_debug1_s          cn61xx;
 	struct cvmx_tim_mem_debug1_s          cn63xx;
 	struct cvmx_tim_mem_debug1_s          cn63xxp1;
+	struct cvmx_tim_mem_debug1_s          cn66xx;
+	struct cvmx_tim_mem_debug1_s          cnf71xx;
 };
 typedef union cvmx_tim_mem_debug1 cvmx_tim_mem_debug1_t;
 
@@ -166,12 +796,10 @@ typedef union cvmx_tim_mem_debug1 cvmx_tim_mem_debug1_t;
  * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_tim_mem_debug2
-{
+union cvmx_tim_mem_debug2 {
 	uint64_t u64;
-	struct cvmx_tim_mem_debug2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_tim_mem_debug2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t cpool                        : 3;  /**< Free list used to free chunks */
 	uint64_t csize                        : 13; /**< Number of words per chunk */
@@ -197,8 +825,11 @@ union cvmx_tim_mem_debug2
 	struct cvmx_tim_mem_debug2_s          cn56xxp1;
 	struct cvmx_tim_mem_debug2_s          cn58xx;
 	struct cvmx_tim_mem_debug2_s          cn58xxp1;
+	struct cvmx_tim_mem_debug2_s          cn61xx;
 	struct cvmx_tim_mem_debug2_s          cn63xx;
 	struct cvmx_tim_mem_debug2_s          cn63xxp1;
+	struct cvmx_tim_mem_debug2_s          cn66xx;
+	struct cvmx_tim_mem_debug2_s          cnf71xx;
 };
 typedef union cvmx_tim_mem_debug2 cvmx_tim_mem_debug2_t;
 
@@ -213,12 +844,10 @@ typedef union cvmx_tim_mem_debug2 cvmx_tim_mem_debug2_t;
  * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_tim_mem_ring0
-{
+union cvmx_tim_mem_ring0 {
 	uint64_t u64;
-	struct cvmx_tim_mem_ring0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_tim_mem_ring0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_55_63               : 9;
 	uint64_t first_bucket                 : 31; /**< Pointer[35:5] to bucket[0] */
 	uint64_t num_buckets                  : 20; /**< Number of buckets - 1 */
@@ -241,8 +870,11 @@ union cvmx_tim_mem_ring0
 	struct cvmx_tim_mem_ring0_s           cn56xxp1;
 	struct cvmx_tim_mem_ring0_s           cn58xx;
 	struct cvmx_tim_mem_ring0_s           cn58xxp1;
+	struct cvmx_tim_mem_ring0_s           cn61xx;
 	struct cvmx_tim_mem_ring0_s           cn63xx;
 	struct cvmx_tim_mem_ring0_s           cn63xxp1;
+	struct cvmx_tim_mem_ring0_s           cn66xx;
+	struct cvmx_tim_mem_ring0_s           cnf71xx;
 };
 typedef union cvmx_tim_mem_ring0 cvmx_tim_mem_ring0_t;
 
@@ -259,12 +891,10 @@ typedef union cvmx_tim_mem_ring0 cvmx_tim_mem_ring0_t;
  * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
  * CSR read operations to this address can be performed.
  */
-union cvmx_tim_mem_ring1
-{
+union cvmx_tim_mem_ring1 {
 	uint64_t u64;
-	struct cvmx_tim_mem_ring1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_tim_mem_ring1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_43_63               : 21;
 	uint64_t enable                       : 1;  /**< Ring timer enable
                                                          When clear, the ring is disabled and TIM
@@ -293,8 +923,11 @@ union cvmx_tim_mem_ring1
 	struct cvmx_tim_mem_ring1_s           cn56xxp1;
 	struct cvmx_tim_mem_ring1_s           cn58xx;
 	struct cvmx_tim_mem_ring1_s           cn58xxp1;
+	struct cvmx_tim_mem_ring1_s           cn61xx;
 	struct cvmx_tim_mem_ring1_s           cn63xx;
 	struct cvmx_tim_mem_ring1_s           cn63xxp1;
+	struct cvmx_tim_mem_ring1_s           cn66xx;
+	struct cvmx_tim_mem_ring1_s           cnf71xx;
 };
 typedef union cvmx_tim_mem_ring1 cvmx_tim_mem_ring1_t;
 
@@ -305,12 +938,10 @@ typedef union cvmx_tim_mem_ring1 cvmx_tim_mem_ring1_t;
  * Access to the internal BiST results
  * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
  */
-union cvmx_tim_reg_bist_result
-{
+union cvmx_tim_reg_bist_result {
 	uint64_t u64;
-	struct cvmx_tim_reg_bist_result_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_tim_reg_bist_result_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t sta                          : 2;  /**< BiST result of the STA   memories (0=pass, !0=fail) */
 	uint64_t ncb                          : 1;  /**< BiST result of the NCB   memories (0=pass, !0=fail) */
@@ -333,8 +964,11 @@ union cvmx_tim_reg_bist_result
 	struct cvmx_tim_reg_bist_result_s     cn56xxp1;
 	struct cvmx_tim_reg_bist_result_s     cn58xx;
 	struct cvmx_tim_reg_bist_result_s     cn58xxp1;
+	struct cvmx_tim_reg_bist_result_s     cn61xx;
 	struct cvmx_tim_reg_bist_result_s     cn63xx;
 	struct cvmx_tim_reg_bist_result_s     cn63xxp1;
+	struct cvmx_tim_reg_bist_result_s     cn66xx;
+	struct cvmx_tim_reg_bist_result_s     cnf71xx;
 };
 typedef union cvmx_tim_reg_bist_result cvmx_tim_reg_bist_result_t;
 
@@ -346,12 +980,10 @@ typedef union cvmx_tim_reg_bist_result cvmx_tim_reg_bist_result_t;
  * During a CSR write to this register, the write data is used as a mask to clear the selected mask
  * bits (mask'[15:0] = mask[15:0] & ~write_data[15:0]).
  */
-union cvmx_tim_reg_error
-{
+union cvmx_tim_reg_error {
 	uint64_t u64;
-	struct cvmx_tim_reg_error_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_tim_reg_error_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t mask                         : 16; /**< Bit mask indicating the rings in error */
 #else
@@ -370,14 +1002,20 @@ union cvmx_tim_reg_error
 	struct cvmx_tim_reg_error_s           cn56xxp1;
 	struct cvmx_tim_reg_error_s           cn58xx;
 	struct cvmx_tim_reg_error_s           cn58xxp1;
+	struct cvmx_tim_reg_error_s           cn61xx;
 	struct cvmx_tim_reg_error_s           cn63xx;
 	struct cvmx_tim_reg_error_s           cn63xxp1;
+	struct cvmx_tim_reg_error_s           cn66xx;
+	struct cvmx_tim_reg_error_s           cnf71xx;
 };
 typedef union cvmx_tim_reg_error cvmx_tim_reg_error_t;
 
 /**
  * cvmx_tim_reg_flags
  *
+ * 13e20 reserved
+ *
+ *
  * Notes:
  * TIM has a counter that causes a periodic tick every 1024 cycles. This counter is shared by all
  * rings. (Each tick causes the HW to decrement the time offset (i.e. COUNT) for all enabled rings.)
@@ -391,12 +1029,44 @@ typedef union cvmx_tim_reg_error cvmx_tim_reg_error_t;
  * ENA_TIM is later set to one. Bucket traversals that were already in progress will complete
  * after the 1->0 ENA_TIM transition, though.
  */
-union cvmx_tim_reg_flags
-{
+union cvmx_tim_reg_flags {
 	uint64_t u64;
-	struct cvmx_tim_reg_flags_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_tim_reg_flags_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t gpio_edge                    : 2;  /**< Edge used for GPIO timing
+                                                         2'b10 - TIM counts high to low transitions
+                                                         2'b01 - TIM counts low to high transitions
+                                                         2'b11 - TIM counts Both low to high and high to low
+                                                         transitions */
+	uint64_t ena_gpio                     : 1;  /**< Enable the external control of GPIO over the free
+                                                         running timer.
+                                                         When set, free running timer will be driven by GPIO.
+                                                         Free running timer will count posedge or negedge of the
+                                                         GPIO pin based on GPIO_EDGE register. */
+	uint64_t ena_dfb                      : 1;  /**< Enable Don't Free Buffer. When set chunk buffer
+                                                         would not be released by the TIM back to FPA. */
+	uint64_t reset                        : 1;  /**< Reset oneshot pulse for free-running structures */
+	uint64_t enable_dwb                   : 1;  /**< Enables non-zero DonwWriteBacks when set
+                                                         When set, enables the use of
+                                                         DontWriteBacks during the buffer freeing
+                                                         operations. */
+	uint64_t enable_timers                : 1;  /**< Enables the TIM section when set
+                                                         When set, TIM is in normal operation.
+                                                         When clear, time is effectively stopped for all
+                                                         rings in TIM. */
+#else
+	uint64_t enable_timers                : 1;
+	uint64_t enable_dwb                   : 1;
+	uint64_t reset                        : 1;
+	uint64_t ena_dfb                      : 1;
+	uint64_t ena_gpio                     : 1;
+	uint64_t gpio_edge                    : 2;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_tim_reg_flags_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t reset                        : 1;  /**< Reset oneshot pulse for free-running structures */
 	uint64_t enable_dwb                   : 1;  /**< Enables non-zero DonwWriteBacks when set
@@ -413,20 +1083,24 @@ union cvmx_tim_reg_flags
 	uint64_t reset                        : 1;
 	uint64_t reserved_3_63                : 61;
 #endif
-	} s;
-	struct cvmx_tim_reg_flags_s           cn30xx;
-	struct cvmx_tim_reg_flags_s           cn31xx;
-	struct cvmx_tim_reg_flags_s           cn38xx;
-	struct cvmx_tim_reg_flags_s           cn38xxp2;
-	struct cvmx_tim_reg_flags_s           cn50xx;
-	struct cvmx_tim_reg_flags_s           cn52xx;
-	struct cvmx_tim_reg_flags_s           cn52xxp1;
-	struct cvmx_tim_reg_flags_s           cn56xx;
-	struct cvmx_tim_reg_flags_s           cn56xxp1;
-	struct cvmx_tim_reg_flags_s           cn58xx;
-	struct cvmx_tim_reg_flags_s           cn58xxp1;
-	struct cvmx_tim_reg_flags_s           cn63xx;
-	struct cvmx_tim_reg_flags_s           cn63xxp1;
+	} cn30xx;
+	struct cvmx_tim_reg_flags_cn30xx      cn31xx;
+	struct cvmx_tim_reg_flags_cn30xx      cn38xx;
+	struct cvmx_tim_reg_flags_cn30xx      cn38xxp2;
+	struct cvmx_tim_reg_flags_cn30xx      cn50xx;
+	struct cvmx_tim_reg_flags_cn30xx      cn52xx;
+	struct cvmx_tim_reg_flags_cn30xx      cn52xxp1;
+	struct cvmx_tim_reg_flags_cn30xx      cn56xx;
+	struct cvmx_tim_reg_flags_cn30xx      cn56xxp1;
+	struct cvmx_tim_reg_flags_cn30xx      cn58xx;
+	struct cvmx_tim_reg_flags_cn30xx      cn58xxp1;
+	struct cvmx_tim_reg_flags_cn30xx      cn61xx;
+	struct cvmx_tim_reg_flags_cn30xx      cn63xx;
+	struct cvmx_tim_reg_flags_cn30xx      cn63xxp1;
+	struct cvmx_tim_reg_flags_cn30xx      cn66xx;
+	struct cvmx_tim_reg_flags_s           cn68xx;
+	struct cvmx_tim_reg_flags_s           cn68xxp1;
+	struct cvmx_tim_reg_flags_cn30xx      cnf71xx;
 };
 typedef union cvmx_tim_reg_flags cvmx_tim_reg_flags_t;
 
@@ -437,12 +1111,10 @@ typedef union cvmx_tim_reg_flags cvmx_tim_reg_flags_t;
  * Note that this CSR is present only in chip revisions beginning with pass2.
  * When mask bit is set, the interrupt is enabled.
  */
-union cvmx_tim_reg_int_mask
-{
+union cvmx_tim_reg_int_mask {
 	uint64_t u64;
-	struct cvmx_tim_reg_int_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_tim_reg_int_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t mask                         : 16; /**< Bit mask corresponding to TIM_REG_ERROR.MASK above */
 #else
@@ -461,8 +1133,11 @@ union cvmx_tim_reg_int_mask
 	struct cvmx_tim_reg_int_mask_s        cn56xxp1;
 	struct cvmx_tim_reg_int_mask_s        cn58xx;
 	struct cvmx_tim_reg_int_mask_s        cn58xxp1;
+	struct cvmx_tim_reg_int_mask_s        cn61xx;
 	struct cvmx_tim_reg_int_mask_s        cn63xx;
 	struct cvmx_tim_reg_int_mask_s        cn63xxp1;
+	struct cvmx_tim_reg_int_mask_s        cn66xx;
+	struct cvmx_tim_reg_int_mask_s        cnf71xx;
 };
 typedef union cvmx_tim_reg_int_mask cvmx_tim_reg_int_mask_t;
 
@@ -476,12 +1151,10 @@ typedef union cvmx_tim_reg_int_mask cvmx_tim_reg_int_mask_t;
  * The intended use is to initially write this CSR such that IDX=0 and INC=1.  Then, the entire
  * contents of a CSR memory can be read with consecutive CSR read commands.
  */
-union cvmx_tim_reg_read_idx
-{
+union cvmx_tim_reg_read_idx {
 	uint64_t u64;
-	struct cvmx_tim_reg_read_idx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_tim_reg_read_idx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t inc                          : 8;  /**< Increment to add to current index for next index */
 	uint64_t index                        : 8;  /**< Index to use for next memory CSR read */
@@ -502,9 +1175,200 @@ union cvmx_tim_reg_read_idx
 	struct cvmx_tim_reg_read_idx_s        cn56xxp1;
 	struct cvmx_tim_reg_read_idx_s        cn58xx;
 	struct cvmx_tim_reg_read_idx_s        cn58xxp1;
+	struct cvmx_tim_reg_read_idx_s        cn61xx;
 	struct cvmx_tim_reg_read_idx_s        cn63xx;
 	struct cvmx_tim_reg_read_idx_s        cn63xxp1;
+	struct cvmx_tim_reg_read_idx_s        cn66xx;
+	struct cvmx_tim_reg_read_idx_s        cnf71xx;
 };
 typedef union cvmx_tim_reg_read_idx cvmx_tim_reg_read_idx_t;
 
+/**
+ * cvmx_tim_ring#_ctl0
+ *
+ * Notes:
+ * This CSR is a memory of 64 entries
+ * After a 1 to 0 transition on ENA, the HW will still complete a bucket traversal for the ring
+ * if it was pending or active prior to the transition. (SW must delay to ensure the completion
+ * of the traversal before reprogramming the ring.)
+ */
+union cvmx_tim_ringx_ctl0 {
+	uint64_t u64;
+	struct cvmx_tim_ringx_ctl0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_47_63               : 17;
+	uint64_t ena                          : 1;  /**< Ring timer enable */
+	uint64_t intc                         : 2;  /**< Interval count for Error. Defines how many intervals
+                                                         could elapse from bucket expiration till actual
+                                                         bucket traversal before HW asserts an error.
+                                                         Typical value is 0,1,2. */
+	uint64_t timercount                   : 22; /**< Timer Count represents the ring offset; how many timer
+                                                         ticks have left till the interval expiration.
+                                                         Typical initialization value should be Interval/Constant,
+                                                         it is recommended that constant should be unique per ring
+                                                         This will create an offset between the rings.
+                                                         Once ENA is set,
+                                                         TIMERCOUNT counts down timer ticks. When TIMERCOUNT
+                                                         reaches zero, ring's interval expired and the HW forces
+                                                         a bucket traversal (and resets TIMERCOUNT to INTERVAL)
+                                                         TIMERCOUNT is unpredictable whenever ENA==0.
+                                                         It is SW responsibility to set TIMERCOUNT before
+                                                         TIM_RINGX_CTL0.ENA transitions from 0 to 1.
+                                                         When the field is set to X it would take X+1 timer tick
+                                                         for the interval to expire. */
+	uint64_t interval                     : 22; /**< Timer interval. Measured in Timer Ticks, where timer
+                                                         ticks are defined by TIM_FR_RN_TT.FR_RN_TT. */
+#else
+	uint64_t interval                     : 22;
+	uint64_t timercount                   : 22;
+	uint64_t intc                         : 2;
+	uint64_t ena                          : 1;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} s;
+	struct cvmx_tim_ringx_ctl0_s          cn68xx;
+	struct cvmx_tim_ringx_ctl0_s          cn68xxp1;
+};
+typedef union cvmx_tim_ringx_ctl0 cvmx_tim_ringx_ctl0_t;
+
+/**
+ * cvmx_tim_ring#_ctl1
+ *
+ * Notes:
+ * This CSR is a memory of 64 entries
+ * ***NOTE: Added fields in pass 2.0
+ */
+union cvmx_tim_ringx_ctl1 {
+	uint64_t u64;
+	struct cvmx_tim_ringx_ctl1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_47_63               : 17;
+	uint64_t ena_gpio                     : 1;  /**< When set, ring's timer tick will be generated by the
+                                                         GPIO Timer. GPIO edge is defined by
+                                                         TIM_REG_FLAGS.GPIO_EDGE
+                                                         Default value zero means that timer ticks will
+                                                         be genearated from the Internal Timer */
+	uint64_t ena_prd                      : 1;  /**< Enable Periodic Mode which would disable the memory
+                                                         write of zeros to num_entries and chunk_remainder
+                                                         when a bucket is traveresed. */
+	uint64_t ena_dwb                      : 1;  /**< When set, enables the use of Dont Write Back during
+                                                         FPA buffer freeing operations */
+	uint64_t ena_dfb                      : 1;  /**< Enable Don't Free Buffer. When set chunk buffer
+                                                         would not be released by the TIM back to FPA. */
+	uint64_t cpool                        : 3;  /**< FPA Free list to free chunks to. */
+	uint64_t bucket                       : 20; /**< Current bucket. Should be set to zero by SW at
+                                                         enable time.
+                                                         Incremented once per bucket traversal. */
+	uint64_t bsize                        : 20; /**< Number of buckets minus one. If BSIZE==0 there is
+                                                         only one bucket in the ring. */
+#else
+	uint64_t bsize                        : 20;
+	uint64_t bucket                       : 20;
+	uint64_t cpool                        : 3;
+	uint64_t ena_dfb                      : 1;
+	uint64_t ena_dwb                      : 1;
+	uint64_t ena_prd                      : 1;
+	uint64_t ena_gpio                     : 1;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} s;
+	struct cvmx_tim_ringx_ctl1_s          cn68xx;
+	struct cvmx_tim_ringx_ctl1_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_43_63               : 21;
+	uint64_t cpool                        : 3;  /**< FPA Free list to free chunks to. */
+	uint64_t bucket                       : 20; /**< Current bucket. Should be set to zero by SW at
+                                                         enable time.
+                                                         Incremented once per bucket traversal. */
+	uint64_t bsize                        : 20; /**< Number of buckets minus one. If BSIZE==0 there is
+                                                         only one bucket in the ring. */
+#else
+	uint64_t bsize                        : 20;
+	uint64_t bucket                       : 20;
+	uint64_t cpool                        : 3;
+	uint64_t reserved_43_63               : 21;
+#endif
+	} cn68xxp1;
+};
+typedef union cvmx_tim_ringx_ctl1 cvmx_tim_ringx_ctl1_t;
+
+/**
+ * cvmx_tim_ring#_ctl2
+ *
+ * Notes:
+ * BASE is a 32-byte aligned pointer[35:0].  Only pointer[35:5] are stored because pointer[4:0] = 0.
+ * This CSR is a memory of 64 entries
+ */
+union cvmx_tim_ringx_ctl2 {
+	uint64_t u64;
+	struct cvmx_tim_ringx_ctl2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_47_63               : 17;
+	uint64_t csize                        : 13; /**< Number of words per chunk. CSIZE mod(16) should be
+                                                         zero. */
+	uint64_t reserved_31_33               : 3;
+	uint64_t base                         : 31; /**< Pointer[35:5] to bucket[0] */
+#else
+	uint64_t base                         : 31;
+	uint64_t reserved_31_33               : 3;
+	uint64_t csize                        : 13;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} s;
+	struct cvmx_tim_ringx_ctl2_s          cn68xx;
+	struct cvmx_tim_ringx_ctl2_s          cn68xxp1;
+};
+typedef union cvmx_tim_ringx_ctl2 cvmx_tim_ringx_ctl2_t;
+
+/**
+ * cvmx_tim_ring#_dbg0
+ */
+union cvmx_tim_ringx_dbg0 {
+	uint64_t u64;
+	struct cvmx_tim_ringx_dbg0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t fr_rn_ht                     : 22; /**< Free Running Hardware Timer. Shared by all rings and is
+                                                         used to generate the Timer Tick based on
+                                                         FR_RN_TT. */
+	uint64_t timercount                   : 22; /**< Timer Count represents the ring's offset.
+                                                         Refer to TIM_RINGX_CTL0. */
+	uint64_t cur_bucket                   : 20; /**< Current bucket. Indicates the ring's current bucket.
+                                                         Refer to TIM_RINGX_CTL1.BUCKET. */
+#else
+	uint64_t cur_bucket                   : 20;
+	uint64_t timercount                   : 22;
+	uint64_t fr_rn_ht                     : 22;
+#endif
+	} s;
+	struct cvmx_tim_ringx_dbg0_s          cn68xx;
+	struct cvmx_tim_ringx_dbg0_s          cn68xxp1;
+};
+typedef union cvmx_tim_ringx_dbg0 cvmx_tim_ringx_dbg0_t;
+
+/**
+ * cvmx_tim_ring#_dbg1
+ */
+union cvmx_tim_ringx_dbg1 {
+	uint64_t u64;
+	struct cvmx_tim_ringx_dbg1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_2_63                : 62;
+	uint64_t ring_esr                     : 2;  /**< Ring Expiration Status Register.
+                                                         This register hold the expiration status of the ring.
+                                                         2'b00 - Ring was recently traversed.
+                                                         2'b01 - Interval expired. Ring is queued to be traversed.
+                                                         2'b10 - 1st interval expiration while ring is queued to be
+                                                         traversed.
+                                                         2'b11 - 2nd interval expiration while ring is queued to be
+                                                         traversed. */
+#else
+	uint64_t ring_esr                     : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_tim_ringx_dbg1_s          cn68xx;
+	struct cvmx_tim_ringx_dbg1_s          cn68xxp1;
+};
+typedef union cvmx_tim_ringx_dbg1 cvmx_tim_ringx_dbg1_t;
+
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-tim.c b/sys/contrib/octeon-sdk/cvmx-tim.c
index 1c88b64..5d2d3e1 100644
--- a/sys/contrib/octeon-sdk/cvmx-tim.c
+++ b/sys/contrib/octeon-sdk/cvmx-tim.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Support library for the hardware work queue timers.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #include "executive-config.h"
 #include "cvmx-config.h"
@@ -82,8 +82,6 @@ CVMX_SHARED cvmx_tim_t cvmx_tim;
  */
 int cvmx_tim_setup(uint64_t tick, uint64_t max_ticks)
 {
-    cvmx_tim_mem_ring0_t    config_ring0;
-    cvmx_tim_mem_ring1_t    config_ring1;
     uint64_t                timer_id;
     int                     error = -1;
     uint64_t                tim_clock_hz = cvmx_clock_get_rate(CVMX_CLOCK_TIM);
@@ -92,12 +90,20 @@ int cvmx_tim_setup(uint64_t tick, uint64_t max_ticks)
     uint64_t                tick_ns = 1000 * tick;
     int                     i;
     uint32_t                temp;
+    int                     timer_thr = 1024;
 
     /* for the simulator */
     if (tim_clock_hz == 0)
-      tim_clock_hz = 333000000;
+        tim_clock_hz = 800000000;
 
-    hw_tick_ns = 1024 * 1000000000ull / tim_clock_hz;
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+    {
+        cvmx_tim_fr_rn_tt_t fr_tt;
+        fr_tt.u64 = cvmx_read_csr(CVMX_TIM_FR_RN_TT);
+        timer_thr = fr_tt.s.fr_rn_tt;
+    }
+
+    hw_tick_ns = timer_thr * 1000000000ull / tim_clock_hz;
     /*
      * Double the minimal allowed tick to 2 * HW tick.  tick between
      * (hw_tick_ns, 2*hw_tick_ns) will set config_ring1.s.interval
@@ -113,19 +119,24 @@ int cvmx_tim_setup(uint64_t tick, uint64_t max_ticks)
     /* Reinitialize out timer state */
     memset(&cvmx_tim, 0, sizeof(cvmx_tim));
 
-
-    if ((tick_ns < (hw_tick_ns_allowed)) || (tick_ns > 4194304 * hw_tick_ns))
-      {
-	cvmx_dprintf("ERROR: cvmx_tim_setup: Requested tick %lu(ns) is smaller than"
-		     " the minimal ticks allowed by hardware %lu(ns)\n",
-		     tick_ns, hw_tick_ns_allowed);
-	return error;
-      }
+    if (tick_ns < hw_tick_ns_allowed)
+    {
+        cvmx_dprintf("ERROR: cvmx_tim_setup: Requested tick %lu(ns) is smaller than"
+                " the minimal ticks allowed by hardware %lu(ns)\n",
+                tick_ns, hw_tick_ns_allowed);
+        return error;
+    }
+    else if (tick_ns > 4194304 * hw_tick_ns)
+    {
+        cvmx_dprintf("ERROR: cvmx_tim_setup: Requested tick %lu(ns) is greater than"
+                " the max ticks %lu(ns)\n", tick_ns, hw_tick_ns);
+        return error;
+    }
 
     for (i=2; i<20; i++)
     {
-      if (tick_ns < (hw_tick_ns << i))
-	break;
+        if (tick_ns < (hw_tick_ns << i))
+	    break;
     }
 
     cvmx_tim.max_ticks = (uint32_t)max_ticks;
@@ -165,22 +176,57 @@ int cvmx_tim_setup(uint64_t tick, uint64_t max_ticks)
     /* Loop through all timers */
     for (timer_id = 0; timer_id<CVMX_TIM_NUM_TIMERS; timer_id++)
     {
+        int interval = ((1 << (cvmx_tim.bucket_shift - 10)) - 1);
         cvmx_tim_bucket_entry_t *bucket = cvmx_tim.bucket + timer_id * cvmx_tim.num_buckets;
-        /* Tell the hardware where about the bucket array */
-        config_ring0.u64 = 0;
-        config_ring0.s.first_bucket = cvmx_ptr_to_phys(bucket) >> 5;
-        config_ring0.s.num_buckets = cvmx_tim.num_buckets - 1;
-        config_ring0.s.ring = timer_id;
-        cvmx_write_csr(CVMX_TIM_MEM_RING0, config_ring0.u64);
-
-        /* Tell the hardware the size of each chunk block in pointers */
-        config_ring1.u64 = 0;
-        config_ring1.s.enable = 1;
-        config_ring1.s.pool = CVMX_FPA_TIMER_POOL;
-        config_ring1.s.words_per_chunk = CVMX_FPA_TIMER_POOL_SIZE / 8;
-        config_ring1.s.interval = (1 << (cvmx_tim.bucket_shift - 10)) - 1;
-        config_ring1.s.ring = timer_id;
-        cvmx_write_csr(CVMX_TIM_MEM_RING1, config_ring1.u64);
+        if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+        {
+            cvmx_tim_ringx_ctl0_t     ring_ctl0;
+            cvmx_tim_ringx_ctl1_t     ring_ctl1;
+            cvmx_tim_ringx_ctl2_t     ring_ctl2;
+            cvmx_tim_reg_flags_t      reg_flags;
+
+            /* Tell the hardware where about the bucket array */
+            ring_ctl2.u64 = 0;
+            ring_ctl2.s.csize = CVMX_FPA_TIMER_POOL_SIZE / 8;
+            ring_ctl2.s.base = cvmx_ptr_to_phys(bucket) >> 5;
+            cvmx_write_csr(CVMX_TIM_RINGX_CTL2(timer_id), ring_ctl2.u64);
+
+            reg_flags.u64 = cvmx_read_csr(CVMX_TIM_REG_FLAGS);
+            ring_ctl1.u64 = 0;
+            ring_ctl1.s.cpool = ((reg_flags.s.ena_dfb == 0) ? CVMX_FPA_TIMER_POOL : 0);
+            ring_ctl1.s.bsize = cvmx_tim.num_buckets - 1;
+            cvmx_write_csr(CVMX_TIM_RINGX_CTL1(timer_id), ring_ctl1.u64);
+
+            ring_ctl0.u64 = 0;
+            ring_ctl0.s.timercount = interval + timer_id * interval / CVMX_TIM_NUM_TIMERS;
+            cvmx_write_csr(CVMX_TIM_RINGX_CTL0(timer_id), ring_ctl0.u64);
+
+            ring_ctl0.u64 = cvmx_read_csr(CVMX_TIM_RINGX_CTL0(timer_id));
+            ring_ctl0.s.ena = 1;
+            ring_ctl0.s.interval = interval;
+            cvmx_write_csr(CVMX_TIM_RINGX_CTL0(timer_id), ring_ctl0.u64);
+            ring_ctl0.u64 = cvmx_read_csr(CVMX_TIM_RINGX_CTL0(timer_id));
+        }
+        else
+        {
+            cvmx_tim_mem_ring0_t    config_ring0;
+            cvmx_tim_mem_ring1_t    config_ring1;
+            /* Tell the hardware where about the bucket array */
+            config_ring0.u64 = 0;
+            config_ring0.s.first_bucket = cvmx_ptr_to_phys(bucket) >> 5;
+            config_ring0.s.num_buckets = cvmx_tim.num_buckets - 1;
+            config_ring0.s.ring = timer_id;
+            cvmx_write_csr(CVMX_TIM_MEM_RING0, config_ring0.u64);
+
+            /* Tell the hardware the size of each chunk block in pointers */
+            config_ring1.u64 = 0;
+            config_ring1.s.enable = 1;
+            config_ring1.s.pool = CVMX_FPA_TIMER_POOL;
+            config_ring1.s.words_per_chunk = CVMX_FPA_TIMER_POOL_SIZE / 8;
+            config_ring1.s.interval = interval;
+            config_ring1.s.ring = timer_id;
+            cvmx_write_csr(CVMX_TIM_MEM_RING1, config_ring1.u64);
+        }
     }
 
     return 0;
@@ -194,7 +240,7 @@ void cvmx_tim_start(void)
 {
     cvmx_tim_control_t control;
 
-    control.u64 = 0;
+    control.u64 = cvmx_read_csr(CVMX_TIM_REG_FLAGS);
     control.s.enable_dwb = 1;
     control.s.enable_timers = 1;
 
@@ -210,7 +256,7 @@ void cvmx_tim_start(void)
 void cvmx_tim_stop(void)
 {
     cvmx_tim_control_t control;
-    control.u64 = 0;
+    control.u64 = cvmx_read_csr(CVMX_TIM_REG_FLAGS);
     control.s.enable_dwb = 0;
     control.s.enable_timers = 0;
     cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64);
diff --git a/sys/contrib/octeon-sdk/cvmx-tim.h b/sys/contrib/octeon-sdk/cvmx-tim.h
index bd49eb1..3cad58b 100644
--- a/sys/contrib/octeon-sdk/cvmx-tim.h
+++ b/sys/contrib/octeon-sdk/cvmx-tim.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Interface to the hardware work queue timers.
  *
-`* <hr>$Revision: 49448 $<hr>
+`* <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_TIM_H__
@@ -67,7 +67,7 @@
 extern "C" {
 #endif
 
-#define CVMX_TIM_NUM_TIMERS   16
+#define CVMX_TIM_NUM_TIMERS   (OCTEON_IS_MODEL(OCTEON_CN68XX) ? 64 : 16)
 #define CVMX_TIM_NUM_BUCKETS  2048
 
 typedef enum
@@ -205,7 +205,6 @@ extern void cvmx_tim_shutdown(void);
 static inline cvmx_tim_status_t cvmx_tim_add_entry(cvmx_wqe_t *work_entry, uint64_t ticks_from_now, cvmx_tim_delete_t *delete_info)
 {
     cvmx_tim_bucket_entry_t*    work_bucket_ptr;
-    uint64_t                    current_bucket;
     uint64_t                    work_bucket;
     volatile uint64_t         * tim_entry_ptr;  /* pointer to wqe address in timer chunk */
     uint64_t                    entries_per_chunk;
@@ -230,8 +229,6 @@ static inline cvmx_tim_status_t cvmx_tim_add_entry(cvmx_wqe_t *work_entry, uint6
 
     /* Get the bucket this work queue entry should be in. Remember the bucket
         array is circular */
-    current_bucket = ((cycles - cvmx_tim.start_time)
-		   >> cvmx_tim.bucket_shift);
     work_bucket = (((ticks_from_now * cvmx_tim.tick_cycles) + cycles - cvmx_tim.start_time)
 		   >> cvmx_tim.bucket_shift);
 
diff --git a/sys/contrib/octeon-sdk/cvmx-tlb.c b/sys/contrib/octeon-sdk/cvmx-tlb.c
index 08c5e28..f02ef5d 100644
--- a/sys/contrib/octeon-sdk/cvmx-tlb.c
+++ b/sys/contrib/octeon-sdk/cvmx-tlb.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -50,35 +50,14 @@
  */
 #include "cvmx.h"
 #include "cvmx-tlb.h"
+#include "cvmx-core.h"
+#include <math.h>
 
+extern __uint32_t  __log2(__uint32_t);
 //#define DEBUG
 
 /**
  * @INTERNAL
- * Convert page mask to string
- */
-static inline const char* __mask_to_str(uint64_t mask)
-{
-    /* Most OCTEON processor does not support 1K page sizes */
-    uint64_t non_1k_mask = mask + CVMX_TLB_PAGEMASK_4K;
-
-    switch (non_1k_mask) {
-    case CVMX_TLB_PAGEMASK_4K:     return "4kb";
-    case CVMX_TLB_PAGEMASK_16K:    return "16kb";
-    case CVMX_TLB_PAGEMASK_64K:    return "64kb";
-    case CVMX_TLB_PAGEMASK_256K:   return "256kb";
-    case CVMX_TLB_PAGEMASK_1M:     return "1Mb";
-    case CVMX_TLB_PAGEMASK_4M:     return "4Mb";
-    case CVMX_TLB_PAGEMASK_16M:    return "16Mb";
-    case CVMX_TLB_PAGEMASK_64M:    return "64Mb";
-    case CVMX_TLB_PAGEMASK_256M:   return "256Mb";
-    }
-
-    return "";
-}
-
-/**
- * @INTERNAL
  * issue the tlb read instruction
  */
 static inline void __tlb_read(void){
@@ -125,7 +104,7 @@ static inline int __tlb_probe(uint64_t hi){
  */
 static inline int __tlb_read_index(uint32_t tlbi){
 
-    if (tlbi >= cvmx_tlb_size_limit()) {
+    if (tlbi >= (uint32_t)cvmx_core_get_tlb_entries()) {
         return -1;
     }
 
@@ -147,7 +126,7 @@ static inline int __tlb_write_index(uint32_t tlbi,
 				    uint64_t lo1, uint64_t pagemask)
 {
 
-    if (tlbi >= cvmx_tlb_size_limit()) {
+    if (tlbi >= (uint32_t)cvmx_core_get_tlb_entries()) {
         return -1;
     }
 
@@ -175,7 +154,7 @@ static inline int __tlb_entry_is_free(uint32_t tlbi) {
     int ret = 0;
     uint64_t lo0 = 0, lo1 = 0;
 
-    if (tlbi < cvmx_tlb_size_limit()) {
+    if (tlbi < (uint32_t)cvmx_core_get_tlb_entries()) {
 
         __tlb_read_index(tlbi);
 
@@ -198,7 +177,7 @@ static inline int __tlb_entry_is_free(uint32_t tlbi) {
  */
 static inline void __tlb_dump_index(uint32_t tlbi)
 {
-    if (tlbi < cvmx_tlb_size_limit()) {
+    if (tlbi < (uint32_t)cvmx_core_get_tlb_entries()) {
 
         if (__tlb_entry_is_free(tlbi)) {
 #ifdef DEBUG
@@ -206,8 +185,9 @@ static inline void __tlb_dump_index(uint32_t tlbi)
 #endif
         } else {
             uint64_t lo0, lo1, pgmask;
-            uint32_t hi, c0, c1;
+            uint32_t hi;
 #ifdef DEBUG
+            uint32_t c0, c1;
             int width = 13;
 #endif
 
@@ -218,15 +198,10 @@ static inline void __tlb_dump_index(uint32_t tlbi)
             CVMX_MF_ENTRY_LO_1(lo1);
             CVMX_MF_PAGEMASK(pgmask);
 
-
 #ifdef DEBUG
-            cvmx_dprintf("Index: %3d pgmask=%s ", tlbi, __mask_to_str(pgmask));
-#endif
-
             c0 = ( lo0 >> 3 ) & 7;
             c1 = ( lo1 >> 3 ) & 7;
 
-#ifdef DEBUG
             cvmx_dprintf("va=%0*lx asid=%02x\n",
                                width, (hi & ~0x1fffUL), hi & 0xff);
 
@@ -260,43 +235,6 @@ static inline uint32_t __tlb_wired_index() {
 }
 
 /**
- *  Set up a wired entry. This function is designed to be used by Simple
- *  Executive to set up its virtual to physical address mapping at start up
- *  time. After the mapping is set up, the remaining unused TLB entries can
- *  be use for run time shared memory mapping.
- *
- *  Calling this function causes the C0 wired index register to increase.
- *  Wired index register points to the separation between fixed TLB mapping
- *  and run time shared memory mapping.
- *
- *  @param  hi      Entry Hi
- *  @param  lo0     Entry Low0
- *  @param  lo1     Entry Low1
- *  @param  pagemask Pagemask
- *
- *  @return 0: the entry is added
- *  @return -1: out of TLB entry
- */
-int cvmx_tlb_add_wired_entry( uint64_t hi, uint64_t lo0,
-                              uint64_t lo1, uint64_t pagemask)
-{
-    uint64_t index;
-    int ret = -1;
-
-    index = __tlb_wired_index();
-
-    /* Check to make sure if the index is free to use */
-    if (index < cvmx_tlb_size_limit() && __tlb_entry_is_free(index) ) {
-        /* increase the wired index by 1*/
-        __tlb_write_index(index, hi, lo0, lo1, pagemask);
-        CVMX_MT_TLB_WIRED(index + 1);
-        ret = 0;
-    }
-
-    return ret;
-}
-
-/**
  *  Find a free entry that can be used for share memory mapping.
  *
  *  @return -1: no free entry found
@@ -306,7 +244,7 @@ int cvmx_tlb_allocate_runtime_entry(void)
 {
     uint32_t i, ret = -1;
 
-    for (i = __tlb_wired_index(); i< cvmx_tlb_size_limit(); i++) {
+    for (i = __tlb_wired_index(); i< (uint32_t)cvmx_core_get_tlb_entries(); i++) {
 
     	/* Check to make sure the index is free to use */
         if (__tlb_entry_is_free(i)) {
@@ -325,7 +263,7 @@ int cvmx_tlb_allocate_runtime_entry(void)
 void cvmx_tlb_free_runtime_entry(uint32_t tlbi)
 {
     /* Invalidate an unwired TLB entry */
-    if ((tlbi < cvmx_tlb_size_limit()) && (tlbi >= __tlb_wired_index())) {
+    if ((tlbi < (uint32_t)cvmx_core_get_tlb_entries()) && (tlbi >= __tlb_wired_index())) {
         __tlb_write_index(tlbi, 0xffffffff80000000ULL, 0, 0, 0);
     }
 }
@@ -392,7 +330,7 @@ int cvmx_tlb_add_fixed_entry( uint64_t vaddr, uint64_t paddr, uint64_t size, uin
     CVMX_MF_TLB_WIRED(index);
 
     /* Check to make sure if the index is free to use */
-    if (index < cvmx_tlb_size_limit() && __tlb_entry_is_free(index) ) {
+    if (index < (uint32_t)cvmx_core_get_tlb_entries() && __tlb_entry_is_free(index) ) {
 	cvmx_tlb_write_entry(index, vaddr, paddr, size, tlb_flags);
 
 	if (!__tlb_entry_is_free(index)) {
@@ -439,7 +377,7 @@ void cvmx_tlb_write_runtime_entry(int index, uint64_t vaddr, uint64_t paddr,
  *           >=0 TLB TLB index
  */
 int cvmx_tlb_lookup(uint64_t vaddr) {
-	uint64_t hi= (vaddr >> 12 ) << 12; /* We always use ASID 0 */
+	uint64_t hi= (vaddr >> 13 ) << 13; /* We always use ASID 0 */
 
 	return  __tlb_probe(hi);
 }
@@ -450,7 +388,7 @@ int cvmx_tlb_lookup(uint64_t vaddr) {
 void cvmx_tlb_dump_shared_mapping(void) {
     uint32_t tlbi;
 
-    for ( tlbi = __tlb_wired_index(); tlbi<cvmx_tlb_size_limit(); tlbi++ ) {
+    for ( tlbi = __tlb_wired_index(); tlbi<(uint32_t)cvmx_core_get_tlb_entries(); tlbi++ ) {
         __tlb_dump_index(tlbi);
     }
 }
@@ -463,7 +401,7 @@ void cvmx_tlb_dump_all(void) {
 
     uint32_t tlbi;
 
-    for (tlbi = 0; tlbi<= cvmx_tlb_size_limit(); tlbi++ ) {
+    for (tlbi = 0; tlbi<= (uint32_t)cvmx_core_get_tlb_entries(); tlbi++ ) {
         __tlb_dump_index(tlbi);
     }
 }
diff --git a/sys/contrib/octeon-sdk/cvmx-tlb.h b/sys/contrib/octeon-sdk/cvmx-tlb.h
index bc20362..62f3350 100644
--- a/sys/contrib/octeon-sdk/cvmx-tlb.h
+++ b/sys/contrib/octeon-sdk/cvmx-tlb.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -54,40 +54,6 @@
 extern "C" {
 #endif
 
-#define CVMX_TLB_PAGEMASK_4K		(0x3     << 11)
-#define CVMX_TLB_PAGEMASK_16K		(0xF     << 11)
-#define CVMX_TLB_PAGEMASK_64K		(0x3F    << 11)
-#define CVMX_TLB_PAGEMASK_256K		(0xFF    << 11)
-#define CVMX_TLB_PAGEMASK_1M		(0x3FF   << 11)
-#define CVMX_TLB_PAGEMASK_4M		(0xFFF   << 11)
-#define CVMX_TLB_PAGEMASK_16M		(0x3FFF  << 11)
-#define CVMX_TLB_PAGEMASK_64M		(0xFFFF  << 11)
-#define CVMX_TLB_PAGEMASK_256M		(0x3FFFF << 11)
-
-#define PAGE_MASK 			( ~(( 1<< 12 ) -1))
-
-/**
- *  Set up a wired entry. This function is designed to be used by Simple
- *  Executive to set up its virtual to physical address mapping at start up
- *  time. After the mapping is set up, the remaining unused TLB entries can
- *  be use for run time shared memory mapping.
- *
- *  Calling this function causes the C0 wired index register to increase.
- *  Wired index register points to the separation between fixed TLB mapping
- *  and run time shared memory mapping.
- *
- *  @param  hi		Entry Hi
- *  @param  lo0		Entry Low0
- *  @param  lo1		Entry Low1
- *  @pagam  pagemask    Pagemask
- *
- *  @return 0: the entry is added
- *  @return -1: out of TLB entry
- */
-int cvmx_tlb_add_wired_entry( uint64_t hi, uint64_t lo0,
-			      uint64_t lo1, uint64_t pagemask);
-
-
 /**
  *  Find a free entry that can be used for share memory mapping.
  *
@@ -166,22 +132,6 @@ int cvmx_tlb_lookup(uint64_t vaddr);
  */
 void cvmx_tlb_dump_all(void);
 
-/**
- *  Query for total number of TLBs of the core
- *
- *  @return Total number of TLB entries available on the core
- */
-static inline uint32_t cvmx_tlb_size_limit(void)
-{
-	uint32_t tlb_size_limit = 0;
-
-	if      (OCTEON_IS_MODEL(OCTEON_CN63XX))  tlb_size_limit = 128;
-	else if (OCTEON_IS_MODEL(OCTEON_CN5XXX))  tlb_size_limit =  64;
-	else if (OCTEON_IS_MODEL(OCTEON_CN3XXX))  tlb_size_limit =  32;
-
-	return tlb_size_limit;
-}
-
 /*
  * @INTERNAL
  * return the next power of two value for the given input <v>
@@ -218,51 +168,6 @@ static inline int __is_power_of_two(uint64_t v)
 	return (num_of_1s  ==  1 );
 }
 
-
-/**
- * @INTERNAL
- *
- * Find last bit set 64bit version
- *
- * @param x the integer to find leading 1
- *
- * @return >=0 the bit position (0..63) of the most significant 1 bit in a word
- *   	   -1 if no 1 bit exists
- */
-static inline uint64_t __fls64(uint64_t x)
-{
-	int lz;
-
-	if (sizeof(x) != 8) return 0;
-
-	__asm__(
-	"	.set	push						\n"
-	"	.set	mips64						\n"
-	"	dclz	%0, %1						\n"
-	"	.set	pop						\n"
-	: "=r" (lz)
-	: "r" (x));
-
-	return 63 - lz;
-}
-
-/**
- * @INTERNAL
- * Compute  log2(v), only works if v is power of two.
- *
- * @param v  the input value
- * @return  log2(v)
- */
-static inline uint32_t __log2(uint64_t v)
-{
-	uint32_t log2 = 0 ;
-
-	if (v) log2 =  __fls64(v);
-
-	return log2;
-}
-
-
 #ifdef	__cplusplus
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-tra-defs.h b/sys/contrib/octeon-sdk/cvmx-tra-defs.h
index 1bc2bd6..6e5e7e4 100644
--- a/sys/contrib/octeon-sdk/cvmx-tra-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-tra-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,3128 +49,56 @@
  * <hr>$Revision$<hr>
  *
  */
+
 #ifndef __CVMX_TRA_TYPEDEFS_H__
 #define __CVMX_TRA_TYPEDEFS_H__
 
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_BIST_STATUS CVMX_TRA_BIST_STATUS_FUNC()
-static inline uint64_t CVMX_TRA_BIST_STATUS_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_BIST_STATUS not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A8000010ull);
-}
-#else
-#define CVMX_TRA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800A8000010ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_CTL CVMX_TRA_CTL_FUNC()
-static inline uint64_t CVMX_TRA_CTL_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_CTL not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A8000000ull);
-}
-#else
-#define CVMX_TRA_CTL (CVMX_ADD_IO_SEG(0x00011800A8000000ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_CYCLES_SINCE CVMX_TRA_CYCLES_SINCE_FUNC()
-static inline uint64_t CVMX_TRA_CYCLES_SINCE_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_CYCLES_SINCE not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A8000018ull);
-}
-#else
-#define CVMX_TRA_CYCLES_SINCE (CVMX_ADD_IO_SEG(0x00011800A8000018ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_CYCLES_SINCE1 CVMX_TRA_CYCLES_SINCE1_FUNC()
-static inline uint64_t CVMX_TRA_CYCLES_SINCE1_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_CYCLES_SINCE1 not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A8000028ull);
-}
-#else
-#define CVMX_TRA_CYCLES_SINCE1 (CVMX_ADD_IO_SEG(0x00011800A8000028ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_FILT_ADR_ADR CVMX_TRA_FILT_ADR_ADR_FUNC()
-static inline uint64_t CVMX_TRA_FILT_ADR_ADR_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_FILT_ADR_ADR not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A8000058ull);
-}
-#else
-#define CVMX_TRA_FILT_ADR_ADR (CVMX_ADD_IO_SEG(0x00011800A8000058ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_FILT_ADR_MSK CVMX_TRA_FILT_ADR_MSK_FUNC()
-static inline uint64_t CVMX_TRA_FILT_ADR_MSK_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_FILT_ADR_MSK not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A8000060ull);
-}
-#else
-#define CVMX_TRA_FILT_ADR_MSK (CVMX_ADD_IO_SEG(0x00011800A8000060ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_FILT_CMD CVMX_TRA_FILT_CMD_FUNC()
-static inline uint64_t CVMX_TRA_FILT_CMD_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_FILT_CMD not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A8000040ull);
-}
-#else
-#define CVMX_TRA_FILT_CMD (CVMX_ADD_IO_SEG(0x00011800A8000040ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_FILT_DID CVMX_TRA_FILT_DID_FUNC()
-static inline uint64_t CVMX_TRA_FILT_DID_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_FILT_DID not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A8000050ull);
-}
-#else
-#define CVMX_TRA_FILT_DID (CVMX_ADD_IO_SEG(0x00011800A8000050ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_FILT_SID CVMX_TRA_FILT_SID_FUNC()
-static inline uint64_t CVMX_TRA_FILT_SID_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_FILT_SID not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A8000048ull);
-}
-#else
-#define CVMX_TRA_FILT_SID (CVMX_ADD_IO_SEG(0x00011800A8000048ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_INT_STATUS CVMX_TRA_INT_STATUS_FUNC()
-static inline uint64_t CVMX_TRA_INT_STATUS_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_INT_STATUS not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A8000008ull);
-}
-#else
-#define CVMX_TRA_INT_STATUS (CVMX_ADD_IO_SEG(0x00011800A8000008ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_READ_DAT CVMX_TRA_READ_DAT_FUNC()
-static inline uint64_t CVMX_TRA_READ_DAT_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_READ_DAT not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A8000020ull);
-}
-#else
-#define CVMX_TRA_READ_DAT (CVMX_ADD_IO_SEG(0x00011800A8000020ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_READ_DAT_HI CVMX_TRA_READ_DAT_HI_FUNC()
-static inline uint64_t CVMX_TRA_READ_DAT_HI_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_READ_DAT_HI not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A8000030ull);
-}
-#else
-#define CVMX_TRA_READ_DAT_HI (CVMX_ADD_IO_SEG(0x00011800A8000030ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_TRIG0_ADR_ADR CVMX_TRA_TRIG0_ADR_ADR_FUNC()
-static inline uint64_t CVMX_TRA_TRIG0_ADR_ADR_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_TRIG0_ADR_ADR not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A8000098ull);
-}
-#else
-#define CVMX_TRA_TRIG0_ADR_ADR (CVMX_ADD_IO_SEG(0x00011800A8000098ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_TRIG0_ADR_MSK CVMX_TRA_TRIG0_ADR_MSK_FUNC()
-static inline uint64_t CVMX_TRA_TRIG0_ADR_MSK_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_TRIG0_ADR_MSK not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A80000A0ull);
-}
-#else
-#define CVMX_TRA_TRIG0_ADR_MSK (CVMX_ADD_IO_SEG(0x00011800A80000A0ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_TRIG0_CMD CVMX_TRA_TRIG0_CMD_FUNC()
-static inline uint64_t CVMX_TRA_TRIG0_CMD_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_TRIG0_CMD not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A8000080ull);
-}
-#else
-#define CVMX_TRA_TRIG0_CMD (CVMX_ADD_IO_SEG(0x00011800A8000080ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_TRIG0_DID CVMX_TRA_TRIG0_DID_FUNC()
-static inline uint64_t CVMX_TRA_TRIG0_DID_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_TRIG0_DID not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A8000090ull);
-}
-#else
-#define CVMX_TRA_TRIG0_DID (CVMX_ADD_IO_SEG(0x00011800A8000090ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_TRIG0_SID CVMX_TRA_TRIG0_SID_FUNC()
-static inline uint64_t CVMX_TRA_TRIG0_SID_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_TRIG0_SID not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A8000088ull);
-}
-#else
-#define CVMX_TRA_TRIG0_SID (CVMX_ADD_IO_SEG(0x00011800A8000088ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_TRIG1_ADR_ADR CVMX_TRA_TRIG1_ADR_ADR_FUNC()
-static inline uint64_t CVMX_TRA_TRIG1_ADR_ADR_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_TRIG1_ADR_ADR not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A80000D8ull);
-}
-#else
-#define CVMX_TRA_TRIG1_ADR_ADR (CVMX_ADD_IO_SEG(0x00011800A80000D8ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_TRIG1_ADR_MSK CVMX_TRA_TRIG1_ADR_MSK_FUNC()
-static inline uint64_t CVMX_TRA_TRIG1_ADR_MSK_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_TRIG1_ADR_MSK not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A80000E0ull);
-}
-#else
-#define CVMX_TRA_TRIG1_ADR_MSK (CVMX_ADD_IO_SEG(0x00011800A80000E0ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_TRIG1_CMD CVMX_TRA_TRIG1_CMD_FUNC()
-static inline uint64_t CVMX_TRA_TRIG1_CMD_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_TRIG1_CMD not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A80000C0ull);
-}
-#else
-#define CVMX_TRA_TRIG1_CMD (CVMX_ADD_IO_SEG(0x00011800A80000C0ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_TRIG1_DID CVMX_TRA_TRIG1_DID_FUNC()
-static inline uint64_t CVMX_TRA_TRIG1_DID_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_TRIG1_DID not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A80000D0ull);
-}
-#else
-#define CVMX_TRA_TRIG1_DID (CVMX_ADD_IO_SEG(0x00011800A80000D0ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#define CVMX_TRA_TRIG1_SID CVMX_TRA_TRIG1_SID_FUNC()
-static inline uint64_t CVMX_TRA_TRIG1_SID_FUNC(void)
-{
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
-		cvmx_warn("CVMX_TRA_TRIG1_SID not supported on this chip\n");
-	return CVMX_ADD_IO_SEG(0x00011800A80000C8ull);
-}
-#else
-#define CVMX_TRA_TRIG1_SID (CVMX_ADD_IO_SEG(0x00011800A80000C8ull))
-#endif
-
-/**
- * cvmx_tra_bist_status
- *
- * TRA_BIST_STATUS = Trace Buffer BiST Status
- *
- * Description:
- */
-union cvmx_tra_bist_status
-{
-	uint64_t u64;
-	struct cvmx_tra_bist_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_3_63                : 61;
-	uint64_t tcf                          : 1;  /**< Bist Results for TCF memory
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-	uint64_t tdf1                         : 1;  /**< Bist Results for TDF memory 1
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-	uint64_t reserved_0_0                 : 1;
-#else
-	uint64_t reserved_0_0                 : 1;
-	uint64_t tdf1                         : 1;
-	uint64_t tcf                          : 1;
-	uint64_t reserved_3_63                : 61;
-#endif
-	} s;
-	struct cvmx_tra_bist_status_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_3_63                : 61;
-	uint64_t tcf                          : 1;  /**< Bist Results for TCF memory
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-	uint64_t tdf1                         : 1;  /**< Bist Results for TDF memory 1
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-	uint64_t tdf0                         : 1;  /**< Bist Results for TCF memory 0
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-	uint64_t tdf0                         : 1;
-	uint64_t tdf1                         : 1;
-	uint64_t tcf                          : 1;
-	uint64_t reserved_3_63                : 61;
-#endif
-	} cn31xx;
-	struct cvmx_tra_bist_status_cn31xx    cn38xx;
-	struct cvmx_tra_bist_status_cn31xx    cn38xxp2;
-	struct cvmx_tra_bist_status_cn31xx    cn52xx;
-	struct cvmx_tra_bist_status_cn31xx    cn52xxp1;
-	struct cvmx_tra_bist_status_cn31xx    cn56xx;
-	struct cvmx_tra_bist_status_cn31xx    cn56xxp1;
-	struct cvmx_tra_bist_status_cn31xx    cn58xx;
-	struct cvmx_tra_bist_status_cn31xx    cn58xxp1;
-	struct cvmx_tra_bist_status_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_1_63                : 63;
-	uint64_t tdf                          : 1;  /**< Bist Results for TCF memory
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-	uint64_t tdf                          : 1;
-	uint64_t reserved_1_63                : 63;
-#endif
-	} cn63xx;
-	struct cvmx_tra_bist_status_cn63xx    cn63xxp1;
-};
-typedef union cvmx_tra_bist_status cvmx_tra_bist_status_t;
-
-/**
- * cvmx_tra_ctl
- *
- * TRA_CTL = Trace Buffer Control
- *
- * Description:
- *
- * Notes:
- * It is illegal to change the values of WRAP, TRIG_CTL, IGNORE_O while tracing (i.e. when ENA=1).
- * Note that the following fields are present only in chip revisions beginning with pass2: IGNORE_O
- */
-union cvmx_tra_ctl
-{
-	uint64_t u64;
-	struct cvmx_tra_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_17_63               : 47;
-	uint64_t rdat_md                      : 1;  /**< TRA_READ_DAT mode bit
-                                                         If set, the TRA_READ_DAT reads will return the lower
-                                                         64 bits of the TRA entry and the upper bits must be
-                                                         read through TRA_READ_DAT_HI.  If not set the return
-                                                         value from TRA_READ_DAT accesses will switch between
-                                                         the lower bits and the upper bits of the TRA entry. */
-	uint64_t clkalways                    : 1;  /**< Conditional clock enable
-                                                         If set, the TRA clock is never disabled. */
-	uint64_t ignore_o                     : 1;  /**< Ignore overflow during wrap mode
-                                                         If set and wrapping mode is enabled, then tracing
-                                                         will not stop at the overflow condition.  Each
-                                                         write during an overflow will overwrite the
-                                                         oldest, unread entry and the read pointer is
-                                                         incremented by one entry.  This bit has no effect
-                                                         if WRAP=0. */
-	uint64_t mcd0_ena                     : 1;  /**< MCD0 enable
-                                                         If set and any PP sends the MCD0 signal, the
-                                                         tracing is disabled. */
-	uint64_t mcd0_thr                     : 1;  /**< MCD0_threshold
-                                                         At a fill threshold event, sends an MCD0
-                                                         wire pulse that can cause cores to enter debug
-                                                         mode, if enabled.  This MCD0 wire pulse will not
-                                                         occur while (TRA_INT_STATUS.MCD0_THR == 1). */
-	uint64_t mcd0_trg                     : 1;  /**< MCD0_trigger
-                                                         At an end trigger event, sends an MCD0
-                                                         wire pulse that can cause cores to enter debug
-                                                         mode, if enabled.  This MCD0 wire pulse will not
-                                                         occur while (TRA_INT_STATUS.MCD0_TRG == 1). */
-	uint64_t ciu_thr                      : 1;  /**< CIU_threshold
-                                                         When set during a fill threshold event,
-                                                         TRA_INT_STATUS[CIU_THR] is set, which can cause
-                                                         core interrupts, if enabled. */
-	uint64_t ciu_trg                      : 1;  /**< CIU_trigger
-                                                         When set during an end trigger event,
-                                                         TRA_INT_STATUS[CIU_TRG] is set, which can cause
-                                                         core interrupts, if enabled. */
-	uint64_t full_thr                     : 2;  /**< Full Threshhold
-                                                         0=none
-                                                         1=1/2 full
-                                                         2=3/4 full
-                                                         3=4/4 full */
-	uint64_t time_grn                     : 3;  /**< Timestamp granularity
-                                                         granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */
-	uint64_t trig_ctl                     : 2;  /**< Trigger Control
-                                                         Note: trigger events are written to the trace
-                                                         0=no triggers
-                                                         1=trigger0=start trigger, trigger1=stop trigger
-                                                         2=(trigger0 || trigger1)=start trigger
-                                                         3=(trigger0 || trigger1)=stop trigger */
-	uint64_t wrap                         : 1;  /**< Wrap mode
-                                                         When WRAP=0, the trace buffer will disable itself
-                                                         after having logged 1024 entries.  When WRAP=1,
-                                                         the trace buffer will never disable itself.
-                                                         In this case, tracing may or may not be
-                                                         temporarily suspended during the overflow
-                                                         condition (see IGNORE_O above).
-                                                         0=do not wrap
-                                                         1=wrap */
-	uint64_t ena                          : 1;  /**< Enable Trace
-                                                         Master enable.  Tracing only happens when ENA=1.
-                                                         When ENA changes from 0 to 1, the read and write
-                                                         pointers are reset to 0x00 to begin a new trace.
-                                                         The MCD0 event may set ENA=0 (see MCD0_ENA
-                                                         above).  When using triggers, tracing occurs only
-                                                         between start and stop triggers (including the
-                                                         triggers themselves).
-                                                         0=disable
-                                                         1=enable */
-#else
-	uint64_t ena                          : 1;
-	uint64_t wrap                         : 1;
-	uint64_t trig_ctl                     : 2;
-	uint64_t time_grn                     : 3;
-	uint64_t full_thr                     : 2;
-	uint64_t ciu_trg                      : 1;
-	uint64_t ciu_thr                      : 1;
-	uint64_t mcd0_trg                     : 1;
-	uint64_t mcd0_thr                     : 1;
-	uint64_t mcd0_ena                     : 1;
-	uint64_t ignore_o                     : 1;
-	uint64_t clkalways                    : 1;
-	uint64_t rdat_md                      : 1;
-	uint64_t reserved_17_63               : 47;
-#endif
-	} s;
-	struct cvmx_tra_ctl_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_15_63               : 49;
-	uint64_t ignore_o                     : 1;  /**< Ignore overflow during wrap mode
-                                                         If set and wrapping mode is enabled, then tracing
-                                                         will not stop at the overflow condition.  Each
-                                                         write during an overflow will overwrite the
-                                                         oldest, unread entry and the read pointer is
-                                                         incremented by one entry.  This bit has no effect
-                                                         if WRAP=0. */
-	uint64_t mcd0_ena                     : 1;  /**< MCD0 enable
-                                                         If set and any PP sends the MCD0 signal, the
-                                                         tracing is disabled. */
-	uint64_t mcd0_thr                     : 1;  /**< MCD0_threshold
-                                                         At a fill threshold event, sends an MCD0
-                                                         wire pulse that can cause cores to enter debug
-                                                         mode, if enabled.  This MCD0 wire pulse will not
-                                                         occur while (TRA_INT_STATUS.MCD0_THR == 1). */
-	uint64_t mcd0_trg                     : 1;  /**< MCD0_trigger
-                                                         At an end trigger event, sends an MCD0
-                                                         wire pulse that can cause cores to enter debug
-                                                         mode, if enabled.  This MCD0 wire pulse will not
-                                                         occur while (TRA_INT_STATUS.MCD0_TRG == 1). */
-	uint64_t ciu_thr                      : 1;  /**< CIU_threshold
-                                                         When set during a fill threshold event,
-                                                         TRA_INT_STATUS[CIU_THR] is set, which can cause
-                                                         core interrupts, if enabled. */
-	uint64_t ciu_trg                      : 1;  /**< CIU_trigger
-                                                         When set during an end trigger event,
-                                                         TRA_INT_STATUS[CIU_TRG] is set, which can cause
-                                                         core interrupts, if enabled. */
-	uint64_t full_thr                     : 2;  /**< Full Threshhold
-                                                         0=none
-                                                         1=1/2 full
-                                                         2=3/4 full
-                                                         3=4/4 full */
-	uint64_t time_grn                     : 3;  /**< Timestamp granularity
-                                                         granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */
-	uint64_t trig_ctl                     : 2;  /**< Trigger Control
-                                                         Note: trigger events are written to the trace
-                                                         0=no triggers
-                                                         1=trigger0=start trigger, trigger1=stop trigger
-                                                         2=(trigger0 || trigger1)=start trigger
-                                                         3=(trigger0 || trigger1)=stop trigger */
-	uint64_t wrap                         : 1;  /**< Wrap mode
-                                                         When WRAP=0, the trace buffer will disable itself
-                                                         after having logged 256 entries.  When WRAP=1,
-                                                         the trace buffer will never disable itself.
-                                                         In this case, tracing may or may not be
-                                                         temporarily suspended during the overflow
-                                                         condition (see IGNORE_O above).
-                                                         0=do not wrap
-                                                         1=wrap */
-	uint64_t ena                          : 1;  /**< Enable Trace
-                                                         Master enable.  Tracing only happens when ENA=1.
-                                                         When ENA changes from 0 to 1, the read and write
-                                                         pointers are reset to 0x00 to begin a new trace.
-                                                         The MCD0 event may set ENA=0 (see MCD0_ENA
-                                                         above).  When using triggers, tracing occurs only
-                                                         between start and stop triggers (including the
-                                                         triggers themselves).
-                                                         0=disable
-                                                         1=enable */
-#else
-	uint64_t ena                          : 1;
-	uint64_t wrap                         : 1;
-	uint64_t trig_ctl                     : 2;
-	uint64_t time_grn                     : 3;
-	uint64_t full_thr                     : 2;
-	uint64_t ciu_trg                      : 1;
-	uint64_t ciu_thr                      : 1;
-	uint64_t mcd0_trg                     : 1;
-	uint64_t mcd0_thr                     : 1;
-	uint64_t mcd0_ena                     : 1;
-	uint64_t ignore_o                     : 1;
-	uint64_t reserved_15_63               : 49;
-#endif
-	} cn31xx;
-	struct cvmx_tra_ctl_cn31xx            cn38xx;
-	struct cvmx_tra_ctl_cn31xx            cn38xxp2;
-	struct cvmx_tra_ctl_cn31xx            cn52xx;
-	struct cvmx_tra_ctl_cn31xx            cn52xxp1;
-	struct cvmx_tra_ctl_cn31xx            cn56xx;
-	struct cvmx_tra_ctl_cn31xx            cn56xxp1;
-	struct cvmx_tra_ctl_cn31xx            cn58xx;
-	struct cvmx_tra_ctl_cn31xx            cn58xxp1;
-	struct cvmx_tra_ctl_s                 cn63xx;
-	struct cvmx_tra_ctl_cn63xxp1
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_16_63               : 48;
-	uint64_t clkalways                    : 1;  /**< Conditional clock enable
-                                                         If set, the TRA clock is never disabled. */
-	uint64_t ignore_o                     : 1;  /**< Ignore overflow during wrap mode
-                                                         If set and wrapping mode is enabled, then tracing
-                                                         will not stop at the overflow condition.  Each
-                                                         write during an overflow will overwrite the
-                                                         oldest, unread entry and the read pointer is
-                                                         incremented by one entry.  This bit has no effect
-                                                         if WRAP=0. */
-	uint64_t mcd0_ena                     : 1;  /**< MCD0 enable
-                                                         If set and any PP sends the MCD0 signal, the
-                                                         tracing is disabled. */
-	uint64_t mcd0_thr                     : 1;  /**< MCD0_threshold
-                                                         At a fill threshold event, sends an MCD0
-                                                         wire pulse that can cause cores to enter debug
-                                                         mode, if enabled.  This MCD0 wire pulse will not
-                                                         occur while (TRA_INT_STATUS.MCD0_THR == 1). */
-	uint64_t mcd0_trg                     : 1;  /**< MCD0_trigger
-                                                         At an end trigger event, sends an MCD0
-                                                         wire pulse that can cause cores to enter debug
-                                                         mode, if enabled.  This MCD0 wire pulse will not
-                                                         occur while (TRA_INT_STATUS.MCD0_TRG == 1). */
-	uint64_t ciu_thr                      : 1;  /**< CIU_threshold
-                                                         When set during a fill threshold event,
-                                                         TRA_INT_STATUS[CIU_THR] is set, which can cause
-                                                         core interrupts, if enabled. */
-	uint64_t ciu_trg                      : 1;  /**< CIU_trigger
-                                                         When set during an end trigger event,
-                                                         TRA_INT_STATUS[CIU_TRG] is set, which can cause
-                                                         core interrupts, if enabled. */
-	uint64_t full_thr                     : 2;  /**< Full Threshhold
-                                                         0=none
-                                                         1=1/2 full
-                                                         2=3/4 full
-                                                         3=4/4 full */
-	uint64_t time_grn                     : 3;  /**< Timestamp granularity
-                                                         granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */
-	uint64_t trig_ctl                     : 2;  /**< Trigger Control
-                                                         Note: trigger events are written to the trace
-                                                         0=no triggers
-                                                         1=trigger0=start trigger, trigger1=stop trigger
-                                                         2=(trigger0 || trigger1)=start trigger
-                                                         3=(trigger0 || trigger1)=stop trigger */
-	uint64_t wrap                         : 1;  /**< Wrap mode
-                                                         When WRAP=0, the trace buffer will disable itself
-                                                         after having logged 1024 entries.  When WRAP=1,
-                                                         the trace buffer will never disable itself.
-                                                         In this case, tracing may or may not be
-                                                         temporarily suspended during the overflow
-                                                         condition (see IGNORE_O above).
-                                                         0=do not wrap
-                                                         1=wrap */
-	uint64_t ena                          : 1;  /**< Enable Trace
-                                                         Master enable.  Tracing only happens when ENA=1.
-                                                         When ENA changes from 0 to 1, the read and write
-                                                         pointers are reset to 0x00 to begin a new trace.
-                                                         The MCD0 event may set ENA=0 (see MCD0_ENA
-                                                         above).  When using triggers, tracing occurs only
-                                                         between start and stop triggers (including the
-                                                         triggers themselves).
-                                                         0=disable
-                                                         1=enable */
-#else
-	uint64_t ena                          : 1;
-	uint64_t wrap                         : 1;
-	uint64_t trig_ctl                     : 2;
-	uint64_t time_grn                     : 3;
-	uint64_t full_thr                     : 2;
-	uint64_t ciu_trg                      : 1;
-	uint64_t ciu_thr                      : 1;
-	uint64_t mcd0_trg                     : 1;
-	uint64_t mcd0_thr                     : 1;
-	uint64_t mcd0_ena                     : 1;
-	uint64_t ignore_o                     : 1;
-	uint64_t clkalways                    : 1;
-	uint64_t reserved_16_63               : 48;
-#endif
-	} cn63xxp1;
-};
-typedef union cvmx_tra_ctl cvmx_tra_ctl_t;
-
-/**
- * cvmx_tra_cycles_since
- *
- * TRA_CYCLES_SINCE = Trace Buffer Cycles Since Last Write, Read/Write pointers
- *
- * Description:
- *
- * Notes:
- * This CSR is obsolete.  Use TRA_CYCLES_SINCE1 instead.
- *
- */
-union cvmx_tra_cycles_since
-{
-	uint64_t u64;
-	struct cvmx_tra_cycles_since_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t cycles                       : 48; /**< Cycles since the last entry was written */
-	uint64_t rptr                         : 8;  /**< Read pointer */
-	uint64_t wptr                         : 8;  /**< Write pointer */
-#else
-	uint64_t wptr                         : 8;
-	uint64_t rptr                         : 8;
-	uint64_t cycles                       : 48;
-#endif
-	} s;
-	struct cvmx_tra_cycles_since_s        cn31xx;
-	struct cvmx_tra_cycles_since_s        cn38xx;
-	struct cvmx_tra_cycles_since_s        cn38xxp2;
-	struct cvmx_tra_cycles_since_s        cn52xx;
-	struct cvmx_tra_cycles_since_s        cn52xxp1;
-	struct cvmx_tra_cycles_since_s        cn56xx;
-	struct cvmx_tra_cycles_since_s        cn56xxp1;
-	struct cvmx_tra_cycles_since_s        cn58xx;
-	struct cvmx_tra_cycles_since_s        cn58xxp1;
-	struct cvmx_tra_cycles_since_s        cn63xx;
-	struct cvmx_tra_cycles_since_s        cn63xxp1;
-};
-typedef union cvmx_tra_cycles_since cvmx_tra_cycles_since_t;
-
-/**
- * cvmx_tra_cycles_since1
- *
- * TRA_CYCLES_SINCE1 = Trace Buffer Cycles Since Last Write, Read/Write pointers
- *
- * Description:
- */
-union cvmx_tra_cycles_since1
-{
-	uint64_t u64;
-	struct cvmx_tra_cycles_since1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t cycles                       : 40; /**< Cycles since the last entry was written */
-	uint64_t reserved_22_23               : 2;
-	uint64_t rptr                         : 10; /**< Read pointer */
-	uint64_t reserved_10_11               : 2;
-	uint64_t wptr                         : 10; /**< Write pointer */
-#else
-	uint64_t wptr                         : 10;
-	uint64_t reserved_10_11               : 2;
-	uint64_t rptr                         : 10;
-	uint64_t reserved_22_23               : 2;
-	uint64_t cycles                       : 40;
-#endif
-	} s;
-	struct cvmx_tra_cycles_since1_s       cn52xx;
-	struct cvmx_tra_cycles_since1_s       cn52xxp1;
-	struct cvmx_tra_cycles_since1_s       cn56xx;
-	struct cvmx_tra_cycles_since1_s       cn56xxp1;
-	struct cvmx_tra_cycles_since1_s       cn58xx;
-	struct cvmx_tra_cycles_since1_s       cn58xxp1;
-	struct cvmx_tra_cycles_since1_s       cn63xx;
-	struct cvmx_tra_cycles_since1_s       cn63xxp1;
-};
-typedef union cvmx_tra_cycles_since1 cvmx_tra_cycles_since1_t;
-
-/**
- * cvmx_tra_filt_adr_adr
- *
- * TRA_FILT_ADR_ADR = Trace Buffer Filter Address Address
- *
- * Description:
- */
-union cvmx_tra_filt_adr_adr
-{
-	uint64_t u64;
-	struct cvmx_tra_filt_adr_adr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_38_63               : 26;
-	uint64_t adr                          : 38; /**< Unmasked Address
-                                                         The combination of TRA_FILT_ADR_ADR and
-                                                         TRA_FILT_ADR_MSK is a masked address to
-                                                         enable tracing of only those commands whose
-                                                         masked address matches */
-#else
-	uint64_t adr                          : 38;
-	uint64_t reserved_38_63               : 26;
-#endif
-	} s;
-	struct cvmx_tra_filt_adr_adr_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_36_63               : 28;
-	uint64_t adr                          : 36; /**< Unmasked Address
-                                                         The combination of TRA_FILT_ADR_ADR and
-                                                         TRA_FILT_ADR_MSK is a masked address to
-                                                         enable tracing of only those commands whose
-                                                         masked address matches */
-#else
-	uint64_t adr                          : 36;
-	uint64_t reserved_36_63               : 28;
-#endif
-	} cn31xx;
-	struct cvmx_tra_filt_adr_adr_cn31xx   cn38xx;
-	struct cvmx_tra_filt_adr_adr_cn31xx   cn38xxp2;
-	struct cvmx_tra_filt_adr_adr_cn31xx   cn52xx;
-	struct cvmx_tra_filt_adr_adr_cn31xx   cn52xxp1;
-	struct cvmx_tra_filt_adr_adr_cn31xx   cn56xx;
-	struct cvmx_tra_filt_adr_adr_cn31xx   cn56xxp1;
-	struct cvmx_tra_filt_adr_adr_cn31xx   cn58xx;
-	struct cvmx_tra_filt_adr_adr_cn31xx   cn58xxp1;
-	struct cvmx_tra_filt_adr_adr_s        cn63xx;
-	struct cvmx_tra_filt_adr_adr_s        cn63xxp1;
-};
-typedef union cvmx_tra_filt_adr_adr cvmx_tra_filt_adr_adr_t;
-
-/**
- * cvmx_tra_filt_adr_msk
- *
- * TRA_FILT_ADR_MSK = Trace Buffer Filter Address Mask
- *
- * Description:
- */
-union cvmx_tra_filt_adr_msk
-{
-	uint64_t u64;
-	struct cvmx_tra_filt_adr_msk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_38_63               : 26;
-	uint64_t adr                          : 38; /**< Address Mask
-                                                         The combination of TRA_FILT_ADR_ADR and
-                                                         TRA_FILT_ADR_MSK is a masked address to
-                                                         enable tracing of only those commands whose
-                                                         masked address matches.  When a mask bit is not
-                                                         set, the corresponding address bits are assumed
-                                                         to match.  Also, note that IOBDMAs do not have
-                                                         proper addresses, so when TRA_FILT_CMD[IOBDMA]
-                                                         is set, TRA_FILT_ADR_MSK must be zero to
-                                                         guarantee that any IOBDMAs enter the trace. */
-#else
-	uint64_t adr                          : 38;
-	uint64_t reserved_38_63               : 26;
-#endif
-	} s;
-	struct cvmx_tra_filt_adr_msk_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_36_63               : 28;
-	uint64_t adr                          : 36; /**< Address Mask
-                                                         The combination of TRA_FILT_ADR_ADR and
-                                                         TRA_FILT_ADR_MSK is a masked address to
-                                                         enable tracing of only those commands whose
-                                                         masked address matches.  When a mask bit is not
-                                                         set, the corresponding address bits are assumed
-                                                         to match.  Also, note that IOBDMAs do not have
-                                                         proper addresses, so when TRA_FILT_CMD[IOBDMA]
-                                                         is set, TRA_FILT_ADR_MSK must be zero to
-                                                         guarantee that any IOBDMAs enter the trace. */
-#else
-	uint64_t adr                          : 36;
-	uint64_t reserved_36_63               : 28;
-#endif
-	} cn31xx;
-	struct cvmx_tra_filt_adr_msk_cn31xx   cn38xx;
-	struct cvmx_tra_filt_adr_msk_cn31xx   cn38xxp2;
-	struct cvmx_tra_filt_adr_msk_cn31xx   cn52xx;
-	struct cvmx_tra_filt_adr_msk_cn31xx   cn52xxp1;
-	struct cvmx_tra_filt_adr_msk_cn31xx   cn56xx;
-	struct cvmx_tra_filt_adr_msk_cn31xx   cn56xxp1;
-	struct cvmx_tra_filt_adr_msk_cn31xx   cn58xx;
-	struct cvmx_tra_filt_adr_msk_cn31xx   cn58xxp1;
-	struct cvmx_tra_filt_adr_msk_s        cn63xx;
-	struct cvmx_tra_filt_adr_msk_s        cn63xxp1;
-};
-typedef union cvmx_tra_filt_adr_msk cvmx_tra_filt_adr_msk_t;
-
-/**
- * cvmx_tra_filt_cmd
- *
- * TRA_FILT_CMD = Trace Buffer Filter Command Mask
- *
- * Description:
- *
- * Notes:
- * Note that the trace buffer does not do proper IOBDMA address compares.  Thus, if IOBDMA is set, then
- * the address compare must be disabled (i.e. TRA_FILT_ADR_MSK set to zero) to guarantee that IOBDMAs
- * enter the trace.
- */
-union cvmx_tra_filt_cmd
-{
-	uint64_t u64;
-	struct cvmx_tra_filt_cmd_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t saa64                        : 1;  /**< Enable SAA64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t saa32                        : 1;  /**< Enable SAA32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_60_61               : 2;
-	uint64_t faa64                        : 1;  /**< Enable FAA64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t faa32                        : 1;  /**< Enable FAA32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_56_57               : 2;
-	uint64_t decr64                       : 1;  /**< Enable DECR64  tracing
-                                                         0=disable, 1=enable */
-	uint64_t decr32                       : 1;  /**< Enable DECR32  tracing
-                                                         0=disable, 1=enable */
-	uint64_t decr16                       : 1;  /**< Enable DECR16  tracing
-                                                         0=disable, 1=enable */
-	uint64_t decr8                        : 1;  /**< Enable DECR8   tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr64                       : 1;  /**< Enable INCR64  tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr32                       : 1;  /**< Enable INCR32  tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr16                       : 1;  /**< Enable INCR16  tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr8                        : 1;  /**< Enable INCR8   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr64                        : 1;  /**< Enable CLR64   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr32                        : 1;  /**< Enable CLR32   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr16                        : 1;  /**< Enable CLR16   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr8                         : 1;  /**< Enable CLR8    tracing
-                                                         0=disable, 1=enable */
-	uint64_t set64                        : 1;  /**< Enable SET64   tracing
-                                                         0=disable, 1=enable */
-	uint64_t set32                        : 1;  /**< Enable SET32   tracing
-                                                         0=disable, 1=enable */
-	uint64_t set16                        : 1;  /**< Enable SET16   tracing
-                                                         0=disable, 1=enable */
-	uint64_t set8                         : 1;  /**< Enable SET8    tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst64                      : 1;  /**< Enable IOBST64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst32                      : 1;  /**< Enable IOBST32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst16                      : 1;  /**< Enable IOBST16 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst8                       : 1;  /**< Enable IOBST8  tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_32_35               : 4;
-	uint64_t lckl2                        : 1;  /**< Enable LCKL2   tracing
-                                                         0=disable, 1=enable */
-	uint64_t wbl2                         : 1;  /**< Enable WBL2    tracing
-                                                         0=disable, 1=enable */
-	uint64_t wbil2                        : 1;  /**< Enable WBIL2   tracing
-                                                         0=disable, 1=enable */
-	uint64_t invl2                        : 1;  /**< Enable INVL2   tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_27_27               : 1;
-	uint64_t stgl2i                       : 1;  /**< Enable STGL2I  tracing
-                                                         0=disable, 1=enable */
-	uint64_t ltgl2i                       : 1;  /**< Enable LTGL2I  tracing
-                                                         0=disable, 1=enable */
-	uint64_t wbil2i                       : 1;  /**< Enable WBIL2I  tracing
-                                                         0=disable, 1=enable */
-	uint64_t fas64                        : 1;  /**< Enable FAS64   tracing
-                                                         0=disable, 1=enable */
-	uint64_t fas32                        : 1;  /**< Enable FAS32   tracing
-                                                         0=disable, 1=enable */
-	uint64_t sttil1                       : 1;  /**< Enable STTIL1  tracing
-                                                         0=disable, 1=enable */
-	uint64_t stfil1                       : 1;  /**< Enable STFIL1  tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_16_19               : 4;
-	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_0_13                : 14;
-#else
-	uint64_t reserved_0_13                : 14;
-	uint64_t iobst                        : 1;
-	uint64_t iobdma                       : 1;
-	uint64_t reserved_16_19               : 4;
-	uint64_t stfil1                       : 1;
-	uint64_t sttil1                       : 1;
-	uint64_t fas32                        : 1;
-	uint64_t fas64                        : 1;
-	uint64_t wbil2i                       : 1;
-	uint64_t ltgl2i                       : 1;
-	uint64_t stgl2i                       : 1;
-	uint64_t reserved_27_27               : 1;
-	uint64_t invl2                        : 1;
-	uint64_t wbil2                        : 1;
-	uint64_t wbl2                         : 1;
-	uint64_t lckl2                        : 1;
-	uint64_t reserved_32_35               : 4;
-	uint64_t iobst8                       : 1;
-	uint64_t iobst16                      : 1;
-	uint64_t iobst32                      : 1;
-	uint64_t iobst64                      : 1;
-	uint64_t set8                         : 1;
-	uint64_t set16                        : 1;
-	uint64_t set32                        : 1;
-	uint64_t set64                        : 1;
-	uint64_t clr8                         : 1;
-	uint64_t clr16                        : 1;
-	uint64_t clr32                        : 1;
-	uint64_t clr64                        : 1;
-	uint64_t incr8                        : 1;
-	uint64_t incr16                       : 1;
-	uint64_t incr32                       : 1;
-	uint64_t incr64                       : 1;
-	uint64_t decr8                        : 1;
-	uint64_t decr16                       : 1;
-	uint64_t decr32                       : 1;
-	uint64_t decr64                       : 1;
-	uint64_t reserved_56_57               : 2;
-	uint64_t faa32                        : 1;
-	uint64_t faa64                        : 1;
-	uint64_t reserved_60_61               : 2;
-	uint64_t saa32                        : 1;
-	uint64_t saa64                        : 1;
-#endif
-	} s;
-	struct cvmx_tra_filt_cmd_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_16_63               : 48;
-	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
-                                                         0=disable, 1=enable */
-	uint64_t stt                          : 1;  /**< Enable STT     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stp                          : 1;  /**< Enable STP     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stc                          : 1;  /**< Enable STC     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stf                          : 1;  /**< Enable STF     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
-                                                         0=disable, 1=enable */
-	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
-                                                         0=disable, 1=enable */
-	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
-                                                         0=disable, 1=enable */
-	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
-                                                         0=disable, 1=enable */
-#else
-	uint64_t dwb                          : 1;
-	uint64_t pl2                          : 1;
-	uint64_t psl1                         : 1;
-	uint64_t ldd                          : 1;
-	uint64_t ldi                          : 1;
-	uint64_t ldt                          : 1;
-	uint64_t stf                          : 1;
-	uint64_t stc                          : 1;
-	uint64_t stp                          : 1;
-	uint64_t stt                          : 1;
-	uint64_t iobld8                       : 1;
-	uint64_t iobld16                      : 1;
-	uint64_t iobld32                      : 1;
-	uint64_t iobld64                      : 1;
-	uint64_t iobst                        : 1;
-	uint64_t iobdma                       : 1;
-	uint64_t reserved_16_63               : 48;
-#endif
-	} cn31xx;
-	struct cvmx_tra_filt_cmd_cn31xx       cn38xx;
-	struct cvmx_tra_filt_cmd_cn31xx       cn38xxp2;
-	struct cvmx_tra_filt_cmd_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_17_63               : 47;
-	uint64_t saa                          : 1;  /**< Enable SAA     tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
-                                                         0=disable, 1=enable */
-	uint64_t stt                          : 1;  /**< Enable STT     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stp                          : 1;  /**< Enable STP     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stc                          : 1;  /**< Enable STC     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stf                          : 1;  /**< Enable STF     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
-                                                         0=disable, 1=enable */
-	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
-                                                         0=disable, 1=enable */
-	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
-                                                         0=disable, 1=enable */
-	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
-                                                         0=disable, 1=enable */
-#else
-	uint64_t dwb                          : 1;
-	uint64_t pl2                          : 1;
-	uint64_t psl1                         : 1;
-	uint64_t ldd                          : 1;
-	uint64_t ldi                          : 1;
-	uint64_t ldt                          : 1;
-	uint64_t stf                          : 1;
-	uint64_t stc                          : 1;
-	uint64_t stp                          : 1;
-	uint64_t stt                          : 1;
-	uint64_t iobld8                       : 1;
-	uint64_t iobld16                      : 1;
-	uint64_t iobld32                      : 1;
-	uint64_t iobld64                      : 1;
-	uint64_t iobst                        : 1;
-	uint64_t iobdma                       : 1;
-	uint64_t saa                          : 1;
-	uint64_t reserved_17_63               : 47;
-#endif
-	} cn52xx;
-	struct cvmx_tra_filt_cmd_cn52xx       cn52xxp1;
-	struct cvmx_tra_filt_cmd_cn52xx       cn56xx;
-	struct cvmx_tra_filt_cmd_cn52xx       cn56xxp1;
-	struct cvmx_tra_filt_cmd_cn52xx       cn58xx;
-	struct cvmx_tra_filt_cmd_cn52xx       cn58xxp1;
-	struct cvmx_tra_filt_cmd_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t saa64                        : 1;  /**< Enable SAA64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t saa32                        : 1;  /**< Enable SAA32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_60_61               : 2;
-	uint64_t faa64                        : 1;  /**< Enable FAA64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t faa32                        : 1;  /**< Enable FAA32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_56_57               : 2;
-	uint64_t decr64                       : 1;  /**< Enable DECR64  tracing
-                                                         0=disable, 1=enable */
-	uint64_t decr32                       : 1;  /**< Enable DECR32  tracing
-                                                         0=disable, 1=enable */
-	uint64_t decr16                       : 1;  /**< Enable DECR16  tracing
-                                                         0=disable, 1=enable */
-	uint64_t decr8                        : 1;  /**< Enable DECR8   tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr64                       : 1;  /**< Enable INCR64  tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr32                       : 1;  /**< Enable INCR32  tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr16                       : 1;  /**< Enable INCR16  tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr8                        : 1;  /**< Enable INCR8   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr64                        : 1;  /**< Enable CLR64   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr32                        : 1;  /**< Enable CLR32   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr16                        : 1;  /**< Enable CLR16   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr8                         : 1;  /**< Enable CLR8    tracing
-                                                         0=disable, 1=enable */
-	uint64_t set64                        : 1;  /**< Enable SET64   tracing
-                                                         0=disable, 1=enable */
-	uint64_t set32                        : 1;  /**< Enable SET32   tracing
-                                                         0=disable, 1=enable */
-	uint64_t set16                        : 1;  /**< Enable SET16   tracing
-                                                         0=disable, 1=enable */
-	uint64_t set8                         : 1;  /**< Enable SET8    tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst64                      : 1;  /**< Enable IOBST64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst32                      : 1;  /**< Enable IOBST32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst16                      : 1;  /**< Enable IOBST16 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst8                       : 1;  /**< Enable IOBST8  tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
-                                                         0=disable, 1=enable */
-	uint64_t lckl2                        : 1;  /**< Enable LCKL2   tracing
-                                                         0=disable, 1=enable */
-	uint64_t wbl2                         : 1;  /**< Enable WBL2    tracing
-                                                         0=disable, 1=enable */
-	uint64_t wbil2                        : 1;  /**< Enable WBIL2   tracing
-                                                         0=disable, 1=enable */
-	uint64_t invl2                        : 1;  /**< Enable INVL2   tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_27_27               : 1;
-	uint64_t stgl2i                       : 1;  /**< Enable STGL2I  tracing
-                                                         0=disable, 1=enable */
-	uint64_t ltgl2i                       : 1;  /**< Enable LTGL2I  tracing
-                                                         0=disable, 1=enable */
-	uint64_t wbil2i                       : 1;  /**< Enable WBIL2I  tracing
-                                                         0=disable, 1=enable */
-	uint64_t fas64                        : 1;  /**< Enable FAS64   tracing
-                                                         0=disable, 1=enable */
-	uint64_t fas32                        : 1;  /**< Enable FAS32   tracing
-                                                         0=disable, 1=enable */
-	uint64_t sttil1                       : 1;  /**< Enable STTIL1  tracing
-                                                         0=disable, 1=enable */
-	uint64_t stfil1                       : 1;  /**< Enable STFIL1  tracing
-                                                         0=disable, 1=enable */
-	uint64_t stc                          : 1;  /**< Enable STC     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stp                          : 1;  /**< Enable STP     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stt                          : 1;  /**< Enable STT     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stf                          : 1;  /**< Enable STF     tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_10_14               : 5;
-	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_6_7                 : 2;
-	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
-                                                         0=disable, 1=enable */
-	uint64_t rpl2                         : 1;  /**< Enable RPL2    tracing
-                                                         0=disable, 1=enable */
-	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
-                                                         0=disable, 1=enable */
-	uint64_t nop                          : 1;  /**< Enable NOP     tracing
-                                                         0=disable, 1=enable */
-#else
-	uint64_t nop                          : 1;
-	uint64_t ldt                          : 1;
-	uint64_t ldi                          : 1;
-	uint64_t pl2                          : 1;
-	uint64_t rpl2                         : 1;
-	uint64_t dwb                          : 1;
-	uint64_t reserved_6_7                 : 2;
-	uint64_t ldd                          : 1;
-	uint64_t psl1                         : 1;
-	uint64_t reserved_10_14               : 5;
-	uint64_t iobdma                       : 1;
-	uint64_t stf                          : 1;
-	uint64_t stt                          : 1;
-	uint64_t stp                          : 1;
-	uint64_t stc                          : 1;
-	uint64_t stfil1                       : 1;
-	uint64_t sttil1                       : 1;
-	uint64_t fas32                        : 1;
-	uint64_t fas64                        : 1;
-	uint64_t wbil2i                       : 1;
-	uint64_t ltgl2i                       : 1;
-	uint64_t stgl2i                       : 1;
-	uint64_t reserved_27_27               : 1;
-	uint64_t invl2                        : 1;
-	uint64_t wbil2                        : 1;
-	uint64_t wbl2                         : 1;
-	uint64_t lckl2                        : 1;
-	uint64_t iobld8                       : 1;
-	uint64_t iobld16                      : 1;
-	uint64_t iobld32                      : 1;
-	uint64_t iobld64                      : 1;
-	uint64_t iobst8                       : 1;
-	uint64_t iobst16                      : 1;
-	uint64_t iobst32                      : 1;
-	uint64_t iobst64                      : 1;
-	uint64_t set8                         : 1;
-	uint64_t set16                        : 1;
-	uint64_t set32                        : 1;
-	uint64_t set64                        : 1;
-	uint64_t clr8                         : 1;
-	uint64_t clr16                        : 1;
-	uint64_t clr32                        : 1;
-	uint64_t clr64                        : 1;
-	uint64_t incr8                        : 1;
-	uint64_t incr16                       : 1;
-	uint64_t incr32                       : 1;
-	uint64_t incr64                       : 1;
-	uint64_t decr8                        : 1;
-	uint64_t decr16                       : 1;
-	uint64_t decr32                       : 1;
-	uint64_t decr64                       : 1;
-	uint64_t reserved_56_57               : 2;
-	uint64_t faa32                        : 1;
-	uint64_t faa64                        : 1;
-	uint64_t reserved_60_61               : 2;
-	uint64_t saa32                        : 1;
-	uint64_t saa64                        : 1;
-#endif
-	} cn63xx;
-	struct cvmx_tra_filt_cmd_cn63xx       cn63xxp1;
-};
-typedef union cvmx_tra_filt_cmd cvmx_tra_filt_cmd_t;
-
-/**
- * cvmx_tra_filt_did
- *
- * TRA_FILT_DID = Trace Buffer Filter DestinationId Mask
- *
- * Description:
- */
-union cvmx_tra_filt_did
-{
-	uint64_t u64;
-	struct cvmx_tra_filt_did_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_13_63               : 51;
-	uint64_t pow                          : 1;  /**< Enable tracing of requests to POW
-                                                         (get work, add work, status/memory/index
-                                                         loads, NULLRd loads, CSR's) */
-	uint64_t reserved_9_11                : 3;
-	uint64_t rng                          : 1;  /**< Enable tracing of requests to RNG
-                                                         (loads/IOBDMA's are legal) */
-	uint64_t zip                          : 1;  /**< Enable tracing of requests to ZIP
-                                                         (doorbell stores are legal) */
-	uint64_t dfa                          : 1;  /**< Enable tracing of requests to DFA
-                                                         (CSR's and operations are legal) */
-	uint64_t fpa                          : 1;  /**< Enable tracing of requests to FPA
-                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
-	uint64_t key                          : 1;  /**< Enable tracing of requests to KEY memory
-                                                         (loads/IOBDMA's/stores are legal) */
-	uint64_t reserved_3_3                 : 1;
-	uint64_t illegal3                     : 2;  /**< Illegal destinations */
-	uint64_t mio                          : 1;  /**< Enable tracing of MIO accesses
-                                                         (CIU and GPIO CSR's, boot bus accesses) */
-#else
-	uint64_t mio                          : 1;
-	uint64_t illegal3                     : 2;
-	uint64_t reserved_3_3                 : 1;
-	uint64_t key                          : 1;
-	uint64_t fpa                          : 1;
-	uint64_t dfa                          : 1;
-	uint64_t zip                          : 1;
-	uint64_t rng                          : 1;
-	uint64_t reserved_9_11                : 3;
-	uint64_t pow                          : 1;
-	uint64_t reserved_13_63               : 51;
-#endif
-	} s;
-	struct cvmx_tra_filt_did_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_32_63               : 32;
-	uint64_t illegal                      : 19; /**< Illegal destinations */
-	uint64_t pow                          : 1;  /**< Enable tracing of requests to POW
-                                                         (get work, add work, status/memory/index
-                                                         loads, NULLRd loads, CSR's) */
-	uint64_t illegal2                     : 3;  /**< Illegal destinations */
-	uint64_t rng                          : 1;  /**< Enable tracing of requests to RNG
-                                                         (loads/IOBDMA's are legal) */
-	uint64_t zip                          : 1;  /**< Enable tracing of requests to ZIP
-                                                         (doorbell stores are legal) */
-	uint64_t dfa                          : 1;  /**< Enable tracing of requests to DFA
-                                                         (CSR's and operations are legal) */
-	uint64_t fpa                          : 1;  /**< Enable tracing of requests to FPA
-                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
-	uint64_t key                          : 1;  /**< Enable tracing of requests to KEY memory
-                                                         (loads/IOBDMA's/stores are legal) */
-	uint64_t pci                          : 1;  /**< Enable tracing of requests to PCI and RSL-type
-                                                         CSR's (RSL CSR's, PCI bus operations, PCI
-                                                         CSR's) */
-	uint64_t illegal3                     : 2;  /**< Illegal destinations */
-	uint64_t mio                          : 1;  /**< Enable tracing of CIU and GPIO CSR's */
-#else
-	uint64_t mio                          : 1;
-	uint64_t illegal3                     : 2;
-	uint64_t pci                          : 1;
-	uint64_t key                          : 1;
-	uint64_t fpa                          : 1;
-	uint64_t dfa                          : 1;
-	uint64_t zip                          : 1;
-	uint64_t rng                          : 1;
-	uint64_t illegal2                     : 3;
-	uint64_t pow                          : 1;
-	uint64_t illegal                      : 19;
-	uint64_t reserved_32_63               : 32;
-#endif
-	} cn31xx;
-	struct cvmx_tra_filt_did_cn31xx       cn38xx;
-	struct cvmx_tra_filt_did_cn31xx       cn38xxp2;
-	struct cvmx_tra_filt_did_cn31xx       cn52xx;
-	struct cvmx_tra_filt_did_cn31xx       cn52xxp1;
-	struct cvmx_tra_filt_did_cn31xx       cn56xx;
-	struct cvmx_tra_filt_did_cn31xx       cn56xxp1;
-	struct cvmx_tra_filt_did_cn31xx       cn58xx;
-	struct cvmx_tra_filt_did_cn31xx       cn58xxp1;
-	struct cvmx_tra_filt_did_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_32_63               : 32;
-	uint64_t illegal5                     : 1;  /**< Illegal destinations */
-	uint64_t fau                          : 1;  /**< Enable tracing of FAU accesses */
-	uint64_t illegal4                     : 2;  /**< Illegal destinations */
-	uint64_t dpi                          : 1;  /**< Enable tracing of DPI accesses
-                                                         (DPI NCB CSRs) */
-	uint64_t illegal                      : 12; /**< Illegal destinations */
-	uint64_t rad                          : 1;  /**< Enable tracing of RAD accesses
-                                                         (doorbells) */
-	uint64_t usb0                         : 1;  /**< Enable tracing of USB0 accesses
-                                                         (UAHC0 EHCI and OHCI NCB CSRs) */
-	uint64_t pow                          : 1;  /**< Enable tracing of requests to POW
-                                                         (get work, add work, status/memory/index
-                                                         loads, NULLRd loads, CSR's) */
-	uint64_t illegal2                     : 1;  /**< Illegal destination */
-	uint64_t pko                          : 1;  /**< Enable tracing of PKO accesses
-                                                         (doorbells) */
-	uint64_t ipd                          : 1;  /**< Enable tracing of IPD CSR accesses
-                                                         (IPD CSRs) */
-	uint64_t rng                          : 1;  /**< Enable tracing of requests to RNG
-                                                         (loads/IOBDMA's are legal) */
-	uint64_t zip                          : 1;  /**< Enable tracing of requests to ZIP
-                                                         (doorbell stores are legal) */
-	uint64_t dfa                          : 1;  /**< Enable tracing of requests to DFA
-                                                         (CSR's and operations are legal) */
-	uint64_t fpa                          : 1;  /**< Enable tracing of requests to FPA
-                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
-	uint64_t key                          : 1;  /**< Enable tracing of requests to KEY memory
-                                                         (loads/IOBDMA's/stores are legal) */
-	uint64_t sli                          : 1;  /**< Enable tracing of requests to SLI and RSL-type
-                                                         CSR's (RSL CSR's, PCI/sRIO bus operations, SLI
-                                                         CSR's) */
-	uint64_t illegal3                     : 2;  /**< Illegal destinations */
-	uint64_t mio                          : 1;  /**< Enable tracing of MIO accesses
-                                                         (CIU and GPIO CSR's, boot bus accesses) */
-#else
-	uint64_t mio                          : 1;
-	uint64_t illegal3                     : 2;
-	uint64_t sli                          : 1;
-	uint64_t key                          : 1;
-	uint64_t fpa                          : 1;
-	uint64_t dfa                          : 1;
-	uint64_t zip                          : 1;
-	uint64_t rng                          : 1;
-	uint64_t ipd                          : 1;
-	uint64_t pko                          : 1;
-	uint64_t illegal2                     : 1;
-	uint64_t pow                          : 1;
-	uint64_t usb0                         : 1;
-	uint64_t rad                          : 1;
-	uint64_t illegal                      : 12;
-	uint64_t dpi                          : 1;
-	uint64_t illegal4                     : 2;
-	uint64_t fau                          : 1;
-	uint64_t illegal5                     : 1;
-	uint64_t reserved_32_63               : 32;
-#endif
-	} cn63xx;
-	struct cvmx_tra_filt_did_cn63xx       cn63xxp1;
-};
-typedef union cvmx_tra_filt_did cvmx_tra_filt_did_t;
-
-/**
- * cvmx_tra_filt_sid
- *
- * TRA_FILT_SID = Trace Buffer Filter SourceId Mask
- *
- * Description:
- */
-union cvmx_tra_filt_sid
-{
-	uint64_t u64;
-	struct cvmx_tra_filt_sid_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_20_63               : 44;
-	uint64_t dwb                          : 1;  /**< Enable tracing of requests from the IOB DWB engine */
-	uint64_t iobreq                       : 1;  /**< Enable tracing of requests from FPA,TIM,DFA,
-                                                         PCI,ZIP,POW, and PKO (writes) */
-	uint64_t pko                          : 1;  /**< Enable tracing of read requests from PKO */
-	uint64_t pki                          : 1;  /**< Enable tracing of write requests from PIP/IPD */
-	uint64_t pp                           : 16; /**< Enable tracing from PP[N] with matching SourceID
-                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
-#else
-	uint64_t pp                           : 16;
-	uint64_t pki                          : 1;
-	uint64_t pko                          : 1;
-	uint64_t iobreq                       : 1;
-	uint64_t dwb                          : 1;
-	uint64_t reserved_20_63               : 44;
-#endif
-	} s;
-	struct cvmx_tra_filt_sid_s            cn31xx;
-	struct cvmx_tra_filt_sid_s            cn38xx;
-	struct cvmx_tra_filt_sid_s            cn38xxp2;
-	struct cvmx_tra_filt_sid_s            cn52xx;
-	struct cvmx_tra_filt_sid_s            cn52xxp1;
-	struct cvmx_tra_filt_sid_s            cn56xx;
-	struct cvmx_tra_filt_sid_s            cn56xxp1;
-	struct cvmx_tra_filt_sid_s            cn58xx;
-	struct cvmx_tra_filt_sid_s            cn58xxp1;
-	struct cvmx_tra_filt_sid_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_20_63               : 44;
-	uint64_t dwb                          : 1;  /**< Enable tracing of requests from the IOB DWB engine */
-	uint64_t iobreq                       : 1;  /**< Enable tracing of requests from FPA,TIM,DFA,
-                                                         PCI,ZIP,POW, and PKO (writes) */
-	uint64_t pko                          : 1;  /**< Enable tracing of read requests from PKO */
-	uint64_t pki                          : 1;  /**< Enable tracing of write requests from PIP/IPD */
-	uint64_t reserved_8_15                : 8;
-	uint64_t pp                           : 8;  /**< Enable tracing from PP[N] with matching SourceID
-                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
-#else
-	uint64_t pp                           : 8;
-	uint64_t reserved_8_15                : 8;
-	uint64_t pki                          : 1;
-	uint64_t pko                          : 1;
-	uint64_t iobreq                       : 1;
-	uint64_t dwb                          : 1;
-	uint64_t reserved_20_63               : 44;
-#endif
-	} cn63xx;
-	struct cvmx_tra_filt_sid_cn63xx       cn63xxp1;
-};
-typedef union cvmx_tra_filt_sid cvmx_tra_filt_sid_t;
-
-/**
- * cvmx_tra_int_status
- *
- * TRA_INT_STATUS = Trace Buffer Interrupt Status
- *
- * Description:
- *
- * Notes:
- * During a CSR write to this register, the write data is used as a mask to clear the selected status
- * bits (status'[3:0] = status[3:0] & ~write_data[3:0]).
- */
-union cvmx_tra_int_status
-{
-	uint64_t u64;
-	struct cvmx_tra_int_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_4_63                : 60;
-	uint64_t mcd0_thr                     : 1;  /**< MCD0 full threshold interrupt status
-                                                         0=trace buffer did not generate MCD0 wire pulse
-                                                         1=trace buffer did     generate MCD0 wire pulse
-                                                           and prevents additional MCD0_THR MCD0 wire pulses */
-	uint64_t mcd0_trg                     : 1;  /**< MCD0 end trigger interrupt status
-                                                         0=trace buffer did not generate interrupt
-                                                         1=trace buffer did     generate interrupt
-                                                           and prevents additional MCD0_TRG MCD0 wire pulses */
-	uint64_t ciu_thr                      : 1;  /**< CIU full threshold interrupt status
-                                                         0=trace buffer did not generate interrupt
-                                                         1=trace buffer did     generate interrupt */
-	uint64_t ciu_trg                      : 1;  /**< CIU end trigger interrupt status
-                                                         0=trace buffer did not generate interrupt
-                                                         1=trace buffer did     generate interrupt */
-#else
-	uint64_t ciu_trg                      : 1;
-	uint64_t ciu_thr                      : 1;
-	uint64_t mcd0_trg                     : 1;
-	uint64_t mcd0_thr                     : 1;
-	uint64_t reserved_4_63                : 60;
-#endif
-	} s;
-	struct cvmx_tra_int_status_s          cn31xx;
-	struct cvmx_tra_int_status_s          cn38xx;
-	struct cvmx_tra_int_status_s          cn38xxp2;
-	struct cvmx_tra_int_status_s          cn52xx;
-	struct cvmx_tra_int_status_s          cn52xxp1;
-	struct cvmx_tra_int_status_s          cn56xx;
-	struct cvmx_tra_int_status_s          cn56xxp1;
-	struct cvmx_tra_int_status_s          cn58xx;
-	struct cvmx_tra_int_status_s          cn58xxp1;
-	struct cvmx_tra_int_status_s          cn63xx;
-	struct cvmx_tra_int_status_s          cn63xxp1;
-};
-typedef union cvmx_tra_int_status cvmx_tra_int_status_t;
-
-/**
- * cvmx_tra_read_dat
- *
- * TRA_READ_DAT = Trace Buffer Read Data
- *
- * Description:
- *
- * Notes:
- * This CSR is a memory of 1024 entries.  When the trace was enabled, the read pointer was set to entry
- * 0 by hardware.  Each read to this address increments the read pointer.
- */
-union cvmx_tra_read_dat
-{
-	uint64_t u64;
-	struct cvmx_tra_read_dat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t data                         : 64; /**< Trace buffer data for current entry */
-#else
-	uint64_t data                         : 64;
-#endif
-	} s;
-	struct cvmx_tra_read_dat_s            cn31xx;
-	struct cvmx_tra_read_dat_s            cn38xx;
-	struct cvmx_tra_read_dat_s            cn38xxp2;
-	struct cvmx_tra_read_dat_s            cn52xx;
-	struct cvmx_tra_read_dat_s            cn52xxp1;
-	struct cvmx_tra_read_dat_s            cn56xx;
-	struct cvmx_tra_read_dat_s            cn56xxp1;
-	struct cvmx_tra_read_dat_s            cn58xx;
-	struct cvmx_tra_read_dat_s            cn58xxp1;
-	struct cvmx_tra_read_dat_s            cn63xx;
-	struct cvmx_tra_read_dat_s            cn63xxp1;
-};
-typedef union cvmx_tra_read_dat cvmx_tra_read_dat_t;
-
-/**
- * cvmx_tra_read_dat_hi
- *
- * TRA_READ_DAT_HI = Trace Buffer Read Data- upper 5 bits do not use if TRA_CTL[16]==0
- *
- * Description:
- *
- * Notes:
- * This CSR is a memory of 1024 entries. Reads to this address do not increment the read pointer.  The
- * 5 bits read are the upper 5 bits of the TRA entry last read by the TRA_READ_DAT reg.
- */
-union cvmx_tra_read_dat_hi
-{
-	uint64_t u64;
-	struct cvmx_tra_read_dat_hi_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_5_63                : 59;
-	uint64_t data                         : 5;  /**< Trace buffer data[68:64] for current entry */
-#else
-	uint64_t data                         : 5;
-	uint64_t reserved_5_63                : 59;
-#endif
-	} s;
-	struct cvmx_tra_read_dat_hi_s         cn63xx;
-};
-typedef union cvmx_tra_read_dat_hi cvmx_tra_read_dat_hi_t;
-
-/**
- * cvmx_tra_trig0_adr_adr
- *
- * TRA_TRIG0_ADR_ADR = Trace Buffer Filter Address Address
- *
- * Description:
- */
-union cvmx_tra_trig0_adr_adr
-{
-	uint64_t u64;
-	struct cvmx_tra_trig0_adr_adr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_38_63               : 26;
-	uint64_t adr                          : 38; /**< Unmasked Address
-                                                         The combination of TRA_TRIG0_ADR_ADR and
-                                                         TRA_TRIG0_ADR_MSK is a masked address to
-                                                         enable tracing of only those commands whose
-                                                         masked address matches */
-#else
-	uint64_t adr                          : 38;
-	uint64_t reserved_38_63               : 26;
-#endif
-	} s;
-	struct cvmx_tra_trig0_adr_adr_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_36_63               : 28;
-	uint64_t adr                          : 36; /**< Unmasked Address
-                                                         The combination of TRA_TRIG0_ADR_ADR and
-                                                         TRA_TRIG0_ADR_MSK is a masked address to
-                                                         enable tracing of only those commands whose
-                                                         masked address matches */
-#else
-	uint64_t adr                          : 36;
-	uint64_t reserved_36_63               : 28;
-#endif
-	} cn31xx;
-	struct cvmx_tra_trig0_adr_adr_cn31xx  cn38xx;
-	struct cvmx_tra_trig0_adr_adr_cn31xx  cn38xxp2;
-	struct cvmx_tra_trig0_adr_adr_cn31xx  cn52xx;
-	struct cvmx_tra_trig0_adr_adr_cn31xx  cn52xxp1;
-	struct cvmx_tra_trig0_adr_adr_cn31xx  cn56xx;
-	struct cvmx_tra_trig0_adr_adr_cn31xx  cn56xxp1;
-	struct cvmx_tra_trig0_adr_adr_cn31xx  cn58xx;
-	struct cvmx_tra_trig0_adr_adr_cn31xx  cn58xxp1;
-	struct cvmx_tra_trig0_adr_adr_s       cn63xx;
-	struct cvmx_tra_trig0_adr_adr_s       cn63xxp1;
-};
-typedef union cvmx_tra_trig0_adr_adr cvmx_tra_trig0_adr_adr_t;
-
-/**
- * cvmx_tra_trig0_adr_msk
- *
- * TRA_TRIG0_ADR_MSK = Trace Buffer Filter Address Mask
- *
- * Description:
- */
-union cvmx_tra_trig0_adr_msk
-{
-	uint64_t u64;
-	struct cvmx_tra_trig0_adr_msk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_38_63               : 26;
-	uint64_t adr                          : 38; /**< Address Mask
-                                                         The combination of TRA_TRIG0_ADR_ADR and
-                                                         TRA_TRIG0_ADR_MSK is a masked address to
-                                                         enable tracing of only those commands whose
-                                                         masked address matches.  When a mask bit is not
-                                                         set, the corresponding address bits are assumed
-                                                         to match.  Also, note that IOBDMAs do not have
-                                                         proper addresses, so when TRA_TRIG0_CMD[IOBDMA]
-                                                         is set, TRA_FILT_TRIG0_MSK must be zero to
-                                                         guarantee that any IOBDMAs are recognized as
-                                                         triggers. */
-#else
-	uint64_t adr                          : 38;
-	uint64_t reserved_38_63               : 26;
-#endif
-	} s;
-	struct cvmx_tra_trig0_adr_msk_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_36_63               : 28;
-	uint64_t adr                          : 36; /**< Address Mask
-                                                         The combination of TRA_TRIG0_ADR_ADR and
-                                                         TRA_TRIG0_ADR_MSK is a masked address to
-                                                         enable tracing of only those commands whose
-                                                         masked address matches.  When a mask bit is not
-                                                         set, the corresponding address bits are assumed
-                                                         to match.  Also, note that IOBDMAs do not have
-                                                         proper addresses, so when TRA_TRIG0_CMD[IOBDMA]
-                                                         is set, TRA_FILT_TRIG0_MSK must be zero to
-                                                         guarantee that any IOBDMAs are recognized as
-                                                         triggers. */
-#else
-	uint64_t adr                          : 36;
-	uint64_t reserved_36_63               : 28;
-#endif
-	} cn31xx;
-	struct cvmx_tra_trig0_adr_msk_cn31xx  cn38xx;
-	struct cvmx_tra_trig0_adr_msk_cn31xx  cn38xxp2;
-	struct cvmx_tra_trig0_adr_msk_cn31xx  cn52xx;
-	struct cvmx_tra_trig0_adr_msk_cn31xx  cn52xxp1;
-	struct cvmx_tra_trig0_adr_msk_cn31xx  cn56xx;
-	struct cvmx_tra_trig0_adr_msk_cn31xx  cn56xxp1;
-	struct cvmx_tra_trig0_adr_msk_cn31xx  cn58xx;
-	struct cvmx_tra_trig0_adr_msk_cn31xx  cn58xxp1;
-	struct cvmx_tra_trig0_adr_msk_s       cn63xx;
-	struct cvmx_tra_trig0_adr_msk_s       cn63xxp1;
-};
-typedef union cvmx_tra_trig0_adr_msk cvmx_tra_trig0_adr_msk_t;
-
-/**
- * cvmx_tra_trig0_cmd
- *
- * TRA_TRIG0_CMD = Trace Buffer Filter Command Mask
- *
- * Description:
- *
- * Notes:
- * Note that the trace buffer does not do proper IOBDMA address compares.  Thus, if IOBDMA is set, then
- * the address compare must be disabled (i.e. TRA_TRIG0_ADR_MSK set to zero) to guarantee that IOBDMAs
- * are recognized as triggers.
- */
-union cvmx_tra_trig0_cmd
-{
-	uint64_t u64;
-	struct cvmx_tra_trig0_cmd_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t saa64                        : 1;  /**< Enable SAA64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t saa32                        : 1;  /**< Enable SAA32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_60_61               : 2;
-	uint64_t faa64                        : 1;  /**< Enable FAA64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t faa32                        : 1;  /**< Enable FAA32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_56_57               : 2;
-	uint64_t decr64                       : 1;  /**< Enable DECR64  tracing
-                                                         0=disable, 1=enable */
-	uint64_t decr32                       : 1;  /**< Enable DECR32  tracing
-                                                         0=disable, 1=enable */
-	uint64_t decr16                       : 1;  /**< Enable DECR16  tracing
-                                                         0=disable, 1=enable */
-	uint64_t decr8                        : 1;  /**< Enable DECR8   tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr64                       : 1;  /**< Enable INCR64  tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr32                       : 1;  /**< Enable INCR32  tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr16                       : 1;  /**< Enable INCR16  tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr8                        : 1;  /**< Enable INCR8   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr64                        : 1;  /**< Enable CLR64   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr32                        : 1;  /**< Enable CLR32   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr16                        : 1;  /**< Enable CLR16   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr8                         : 1;  /**< Enable CLR8    tracing
-                                                         0=disable, 1=enable */
-	uint64_t set64                        : 1;  /**< Enable SET64   tracing
-                                                         0=disable, 1=enable */
-	uint64_t set32                        : 1;  /**< Enable SET32   tracing
-                                                         0=disable, 1=enable */
-	uint64_t set16                        : 1;  /**< Enable SET16   tracing
-                                                         0=disable, 1=enable */
-	uint64_t set8                         : 1;  /**< Enable SET8    tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst64                      : 1;  /**< Enable IOBST64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst32                      : 1;  /**< Enable IOBST32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst16                      : 1;  /**< Enable IOBST16 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst8                       : 1;  /**< Enable IOBST8  tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_32_35               : 4;
-	uint64_t lckl2                        : 1;  /**< Enable LCKL2   tracing
-                                                         0=disable, 1=enable */
-	uint64_t wbl2                         : 1;  /**< Enable WBL2    tracing
-                                                         0=disable, 1=enable */
-	uint64_t wbil2                        : 1;  /**< Enable WBIL2   tracing
-                                                         0=disable, 1=enable */
-	uint64_t invl2                        : 1;  /**< Enable INVL2   tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_27_27               : 1;
-	uint64_t stgl2i                       : 1;  /**< Enable STGL2I  tracing
-                                                         0=disable, 1=enable */
-	uint64_t ltgl2i                       : 1;  /**< Enable LTGL2I  tracing
-                                                         0=disable, 1=enable */
-	uint64_t wbil2i                       : 1;  /**< Enable WBIL2I  tracing
-                                                         0=disable, 1=enable */
-	uint64_t fas64                        : 1;  /**< Enable FAS64   tracing
-                                                         0=disable, 1=enable */
-	uint64_t fas32                        : 1;  /**< Enable FAS32   tracing
-                                                         0=disable, 1=enable */
-	uint64_t sttil1                       : 1;  /**< Enable STTIL1  tracing
-                                                         0=disable, 1=enable */
-	uint64_t stfil1                       : 1;  /**< Enable STFIL1  tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_16_19               : 4;
-	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_0_13                : 14;
-#else
-	uint64_t reserved_0_13                : 14;
-	uint64_t iobst                        : 1;
-	uint64_t iobdma                       : 1;
-	uint64_t reserved_16_19               : 4;
-	uint64_t stfil1                       : 1;
-	uint64_t sttil1                       : 1;
-	uint64_t fas32                        : 1;
-	uint64_t fas64                        : 1;
-	uint64_t wbil2i                       : 1;
-	uint64_t ltgl2i                       : 1;
-	uint64_t stgl2i                       : 1;
-	uint64_t reserved_27_27               : 1;
-	uint64_t invl2                        : 1;
-	uint64_t wbil2                        : 1;
-	uint64_t wbl2                         : 1;
-	uint64_t lckl2                        : 1;
-	uint64_t reserved_32_35               : 4;
-	uint64_t iobst8                       : 1;
-	uint64_t iobst16                      : 1;
-	uint64_t iobst32                      : 1;
-	uint64_t iobst64                      : 1;
-	uint64_t set8                         : 1;
-	uint64_t set16                        : 1;
-	uint64_t set32                        : 1;
-	uint64_t set64                        : 1;
-	uint64_t clr8                         : 1;
-	uint64_t clr16                        : 1;
-	uint64_t clr32                        : 1;
-	uint64_t clr64                        : 1;
-	uint64_t incr8                        : 1;
-	uint64_t incr16                       : 1;
-	uint64_t incr32                       : 1;
-	uint64_t incr64                       : 1;
-	uint64_t decr8                        : 1;
-	uint64_t decr16                       : 1;
-	uint64_t decr32                       : 1;
-	uint64_t decr64                       : 1;
-	uint64_t reserved_56_57               : 2;
-	uint64_t faa32                        : 1;
-	uint64_t faa64                        : 1;
-	uint64_t reserved_60_61               : 2;
-	uint64_t saa32                        : 1;
-	uint64_t saa64                        : 1;
-#endif
-	} s;
-	struct cvmx_tra_trig0_cmd_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_16_63               : 48;
-	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
-                                                         0=disable, 1=enable */
-	uint64_t stt                          : 1;  /**< Enable STT     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stp                          : 1;  /**< Enable STP     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stc                          : 1;  /**< Enable STC     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stf                          : 1;  /**< Enable STF     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
-                                                         0=disable, 1=enable */
-	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
-                                                         0=disable, 1=enable */
-	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
-                                                         0=disable, 1=enable */
-	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
-                                                         0=disable, 1=enable */
-#else
-	uint64_t dwb                          : 1;
-	uint64_t pl2                          : 1;
-	uint64_t psl1                         : 1;
-	uint64_t ldd                          : 1;
-	uint64_t ldi                          : 1;
-	uint64_t ldt                          : 1;
-	uint64_t stf                          : 1;
-	uint64_t stc                          : 1;
-	uint64_t stp                          : 1;
-	uint64_t stt                          : 1;
-	uint64_t iobld8                       : 1;
-	uint64_t iobld16                      : 1;
-	uint64_t iobld32                      : 1;
-	uint64_t iobld64                      : 1;
-	uint64_t iobst                        : 1;
-	uint64_t iobdma                       : 1;
-	uint64_t reserved_16_63               : 48;
-#endif
-	} cn31xx;
-	struct cvmx_tra_trig0_cmd_cn31xx      cn38xx;
-	struct cvmx_tra_trig0_cmd_cn31xx      cn38xxp2;
-	struct cvmx_tra_trig0_cmd_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_17_63               : 47;
-	uint64_t saa                          : 1;  /**< Enable SAA     tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
-                                                         0=disable, 1=enable */
-	uint64_t stt                          : 1;  /**< Enable STT     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stp                          : 1;  /**< Enable STP     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stc                          : 1;  /**< Enable STC     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stf                          : 1;  /**< Enable STF     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
-                                                         0=disable, 1=enable */
-	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
-                                                         0=disable, 1=enable */
-	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
-                                                         0=disable, 1=enable */
-	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
-                                                         0=disable, 1=enable */
-#else
-	uint64_t dwb                          : 1;
-	uint64_t pl2                          : 1;
-	uint64_t psl1                         : 1;
-	uint64_t ldd                          : 1;
-	uint64_t ldi                          : 1;
-	uint64_t ldt                          : 1;
-	uint64_t stf                          : 1;
-	uint64_t stc                          : 1;
-	uint64_t stp                          : 1;
-	uint64_t stt                          : 1;
-	uint64_t iobld8                       : 1;
-	uint64_t iobld16                      : 1;
-	uint64_t iobld32                      : 1;
-	uint64_t iobld64                      : 1;
-	uint64_t iobst                        : 1;
-	uint64_t iobdma                       : 1;
-	uint64_t saa                          : 1;
-	uint64_t reserved_17_63               : 47;
-#endif
-	} cn52xx;
-	struct cvmx_tra_trig0_cmd_cn52xx      cn52xxp1;
-	struct cvmx_tra_trig0_cmd_cn52xx      cn56xx;
-	struct cvmx_tra_trig0_cmd_cn52xx      cn56xxp1;
-	struct cvmx_tra_trig0_cmd_cn52xx      cn58xx;
-	struct cvmx_tra_trig0_cmd_cn52xx      cn58xxp1;
-	struct cvmx_tra_trig0_cmd_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t saa64                        : 1;  /**< Enable SAA64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t saa32                        : 1;  /**< Enable SAA32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_60_61               : 2;
-	uint64_t faa64                        : 1;  /**< Enable FAA64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t faa32                        : 1;  /**< Enable FAA32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_56_57               : 2;
-	uint64_t decr64                       : 1;  /**< Enable DECR64  tracing
-                                                         0=disable, 1=enable */
-	uint64_t decr32                       : 1;  /**< Enable DECR32  tracing
-                                                         0=disable, 1=enable */
-	uint64_t decr16                       : 1;  /**< Enable DECR16  tracing
-                                                         0=disable, 1=enable */
-	uint64_t decr8                        : 1;  /**< Enable DECR8   tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr64                       : 1;  /**< Enable INCR64  tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr32                       : 1;  /**< Enable INCR32  tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr16                       : 1;  /**< Enable INCR16  tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr8                        : 1;  /**< Enable INCR8   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr64                        : 1;  /**< Enable CLR64   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr32                        : 1;  /**< Enable CLR32   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr16                        : 1;  /**< Enable CLR16   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr8                         : 1;  /**< Enable CLR8    tracing
-                                                         0=disable, 1=enable */
-	uint64_t set64                        : 1;  /**< Enable SET64   tracing
-                                                         0=disable, 1=enable */
-	uint64_t set32                        : 1;  /**< Enable SET32   tracing
-                                                         0=disable, 1=enable */
-	uint64_t set16                        : 1;  /**< Enable SET16   tracing
-                                                         0=disable, 1=enable */
-	uint64_t set8                         : 1;  /**< Enable SET8    tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst64                      : 1;  /**< Enable IOBST64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst32                      : 1;  /**< Enable IOBST32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst16                      : 1;  /**< Enable IOBST16 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst8                       : 1;  /**< Enable IOBST8  tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
-                                                         0=disable, 1=enable */
-	uint64_t lckl2                        : 1;  /**< Enable LCKL2   tracing
-                                                         0=disable, 1=enable */
-	uint64_t wbl2                         : 1;  /**< Enable WBL2    tracing
-                                                         0=disable, 1=enable */
-	uint64_t wbil2                        : 1;  /**< Enable WBIL2   tracing
-                                                         0=disable, 1=enable */
-	uint64_t invl2                        : 1;  /**< Enable INVL2   tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_27_27               : 1;
-	uint64_t stgl2i                       : 1;  /**< Enable STGL2I  tracing
-                                                         0=disable, 1=enable */
-	uint64_t ltgl2i                       : 1;  /**< Enable LTGL2I  tracing
-                                                         0=disable, 1=enable */
-	uint64_t wbil2i                       : 1;  /**< Enable WBIL2I  tracing
-                                                         0=disable, 1=enable */
-	uint64_t fas64                        : 1;  /**< Enable FAS64   tracing
-                                                         0=disable, 1=enable */
-	uint64_t fas32                        : 1;  /**< Enable FAS32   tracing
-                                                         0=disable, 1=enable */
-	uint64_t sttil1                       : 1;  /**< Enable STTIL1  tracing
-                                                         0=disable, 1=enable */
-	uint64_t stfil1                       : 1;  /**< Enable STFIL1  tracing
-                                                         0=disable, 1=enable */
-	uint64_t stc                          : 1;  /**< Enable STC     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stp                          : 1;  /**< Enable STP     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stt                          : 1;  /**< Enable STT     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stf                          : 1;  /**< Enable STF     tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_10_14               : 5;
-	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_6_7                 : 2;
-	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
-                                                         0=disable, 1=enable */
-	uint64_t rpl2                         : 1;  /**< Enable RPL2    tracing
-                                                         0=disable, 1=enable */
-	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
-                                                         0=disable, 1=enable */
-	uint64_t nop                          : 1;  /**< Enable NOP     tracing
-                                                         0=disable, 1=enable */
-#else
-	uint64_t nop                          : 1;
-	uint64_t ldt                          : 1;
-	uint64_t ldi                          : 1;
-	uint64_t pl2                          : 1;
-	uint64_t rpl2                         : 1;
-	uint64_t dwb                          : 1;
-	uint64_t reserved_6_7                 : 2;
-	uint64_t ldd                          : 1;
-	uint64_t psl1                         : 1;
-	uint64_t reserved_10_14               : 5;
-	uint64_t iobdma                       : 1;
-	uint64_t stf                          : 1;
-	uint64_t stt                          : 1;
-	uint64_t stp                          : 1;
-	uint64_t stc                          : 1;
-	uint64_t stfil1                       : 1;
-	uint64_t sttil1                       : 1;
-	uint64_t fas32                        : 1;
-	uint64_t fas64                        : 1;
-	uint64_t wbil2i                       : 1;
-	uint64_t ltgl2i                       : 1;
-	uint64_t stgl2i                       : 1;
-	uint64_t reserved_27_27               : 1;
-	uint64_t invl2                        : 1;
-	uint64_t wbil2                        : 1;
-	uint64_t wbl2                         : 1;
-	uint64_t lckl2                        : 1;
-	uint64_t iobld8                       : 1;
-	uint64_t iobld16                      : 1;
-	uint64_t iobld32                      : 1;
-	uint64_t iobld64                      : 1;
-	uint64_t iobst8                       : 1;
-	uint64_t iobst16                      : 1;
-	uint64_t iobst32                      : 1;
-	uint64_t iobst64                      : 1;
-	uint64_t set8                         : 1;
-	uint64_t set16                        : 1;
-	uint64_t set32                        : 1;
-	uint64_t set64                        : 1;
-	uint64_t clr8                         : 1;
-	uint64_t clr16                        : 1;
-	uint64_t clr32                        : 1;
-	uint64_t clr64                        : 1;
-	uint64_t incr8                        : 1;
-	uint64_t incr16                       : 1;
-	uint64_t incr32                       : 1;
-	uint64_t incr64                       : 1;
-	uint64_t decr8                        : 1;
-	uint64_t decr16                       : 1;
-	uint64_t decr32                       : 1;
-	uint64_t decr64                       : 1;
-	uint64_t reserved_56_57               : 2;
-	uint64_t faa32                        : 1;
-	uint64_t faa64                        : 1;
-	uint64_t reserved_60_61               : 2;
-	uint64_t saa32                        : 1;
-	uint64_t saa64                        : 1;
-#endif
-	} cn63xx;
-	struct cvmx_tra_trig0_cmd_cn63xx      cn63xxp1;
-};
-typedef union cvmx_tra_trig0_cmd cvmx_tra_trig0_cmd_t;
-
-/**
- * cvmx_tra_trig0_did
- *
- * TRA_TRIG0_DID = Trace Buffer Filter DestinationId Mask
- *
- * Description:
- */
-union cvmx_tra_trig0_did
-{
-	uint64_t u64;
-	struct cvmx_tra_trig0_did_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_13_63               : 51;
-	uint64_t pow                          : 1;  /**< Enable triggering on requests to POW
-                                                         (get work, add work, status/memory/index
-                                                         loads, NULLRd loads, CSR's) */
-	uint64_t reserved_9_11                : 3;
-	uint64_t rng                          : 1;  /**< Enable triggering on requests to RNG
-                                                         (loads/IOBDMA's are legal) */
-	uint64_t zip                          : 1;  /**< Enable triggering on requests to ZIP
-                                                         (doorbell stores are legal) */
-	uint64_t dfa                          : 1;  /**< Enable triggering on requests to DFA
-                                                         (CSR's and operations are legal) */
-	uint64_t fpa                          : 1;  /**< Enable triggering on requests to FPA
-                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
-	uint64_t key                          : 1;  /**< Enable triggering on requests to KEY memory
-                                                         (loads/IOBDMA's/stores are legal) */
-	uint64_t reserved_3_3                 : 1;
-	uint64_t illegal3                     : 2;  /**< Illegal destinations */
-	uint64_t mio                          : 1;  /**< Enable triggering on MIO accesses
-                                                         (CIU and GPIO CSR's, boot bus accesses) */
-#else
-	uint64_t mio                          : 1;
-	uint64_t illegal3                     : 2;
-	uint64_t reserved_3_3                 : 1;
-	uint64_t key                          : 1;
-	uint64_t fpa                          : 1;
-	uint64_t dfa                          : 1;
-	uint64_t zip                          : 1;
-	uint64_t rng                          : 1;
-	uint64_t reserved_9_11                : 3;
-	uint64_t pow                          : 1;
-	uint64_t reserved_13_63               : 51;
-#endif
-	} s;
-	struct cvmx_tra_trig0_did_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_32_63               : 32;
-	uint64_t illegal                      : 19; /**< Illegal destinations */
-	uint64_t pow                          : 1;  /**< Enable triggering on requests to POW
-                                                         (get work, add work, status/memory/index
-                                                         loads, NULLRd loads, CSR's) */
-	uint64_t illegal2                     : 3;  /**< Illegal destinations */
-	uint64_t rng                          : 1;  /**< Enable triggering on requests to RNG
-                                                         (loads/IOBDMA's are legal) */
-	uint64_t zip                          : 1;  /**< Enable triggering on requests to ZIP
-                                                         (doorbell stores are legal) */
-	uint64_t dfa                          : 1;  /**< Enable triggering on requests to DFA
-                                                         (CSR's and operations are legal) */
-	uint64_t fpa                          : 1;  /**< Enable triggering on requests to FPA
-                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
-	uint64_t key                          : 1;  /**< Enable triggering on requests to KEY memory
-                                                         (loads/IOBDMA's/stores are legal) */
-	uint64_t pci                          : 1;  /**< Enable triggering on requests to PCI and RSL-type
-                                                         CSR's (RSL CSR's, PCI bus operations, PCI
-                                                         CSR's) */
-	uint64_t illegal3                     : 2;  /**< Illegal destinations */
-	uint64_t mio                          : 1;  /**< Enable triggering on CIU and GPIO CSR's */
-#else
-	uint64_t mio                          : 1;
-	uint64_t illegal3                     : 2;
-	uint64_t pci                          : 1;
-	uint64_t key                          : 1;
-	uint64_t fpa                          : 1;
-	uint64_t dfa                          : 1;
-	uint64_t zip                          : 1;
-	uint64_t rng                          : 1;
-	uint64_t illegal2                     : 3;
-	uint64_t pow                          : 1;
-	uint64_t illegal                      : 19;
-	uint64_t reserved_32_63               : 32;
-#endif
-	} cn31xx;
-	struct cvmx_tra_trig0_did_cn31xx      cn38xx;
-	struct cvmx_tra_trig0_did_cn31xx      cn38xxp2;
-	struct cvmx_tra_trig0_did_cn31xx      cn52xx;
-	struct cvmx_tra_trig0_did_cn31xx      cn52xxp1;
-	struct cvmx_tra_trig0_did_cn31xx      cn56xx;
-	struct cvmx_tra_trig0_did_cn31xx      cn56xxp1;
-	struct cvmx_tra_trig0_did_cn31xx      cn58xx;
-	struct cvmx_tra_trig0_did_cn31xx      cn58xxp1;
-	struct cvmx_tra_trig0_did_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_32_63               : 32;
-	uint64_t illegal5                     : 1;  /**< Illegal destinations */
-	uint64_t fau                          : 1;  /**< Enable triggering on FAU accesses */
-	uint64_t illegal4                     : 2;  /**< Illegal destinations */
-	uint64_t dpi                          : 1;  /**< Enable triggering on DPI accesses
-                                                         (DPI NCB CSRs) */
-	uint64_t illegal                      : 12; /**< Illegal destinations */
-	uint64_t rad                          : 1;  /**< Enable triggering on RAD accesses
-                                                         (doorbells) */
-	uint64_t usb0                         : 1;  /**< Enable triggering on USB0 accesses
-                                                         (UAHC0 EHCI and OHCI NCB CSRs) */
-	uint64_t pow                          : 1;  /**< Enable triggering on requests to POW
-                                                         (get work, add work, status/memory/index
-                                                         loads, NULLRd loads, CSR's) */
-	uint64_t illegal2                     : 1;  /**< Illegal destination */
-	uint64_t pko                          : 1;  /**< Enable triggering on PKO accesses
-                                                         (doorbells) */
-	uint64_t ipd                          : 1;  /**< Enable triggering on IPD CSR accesses
-                                                         (IPD CSRs) */
-	uint64_t rng                          : 1;  /**< Enable triggering on requests to RNG
-                                                         (loads/IOBDMA's are legal) */
-	uint64_t zip                          : 1;  /**< Enable triggering on requests to ZIP
-                                                         (doorbell stores are legal) */
-	uint64_t dfa                          : 1;  /**< Enable triggering on requests to DFA
-                                                         (CSR's and operations are legal) */
-	uint64_t fpa                          : 1;  /**< Enable triggering on requests to FPA
-                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
-	uint64_t key                          : 1;  /**< Enable triggering on requests to KEY memory
-                                                         (loads/IOBDMA's/stores are legal) */
-	uint64_t sli                          : 1;  /**< Enable triggering on requests to SLI and RSL-type
-                                                         CSR's (RSL CSR's, PCI/sRIO bus operations, SLI
-                                                         CSR's) */
-	uint64_t illegal3                     : 2;  /**< Illegal destinations */
-	uint64_t mio                          : 1;  /**< Enable triggering on MIO accesses
-                                                         (CIU and GPIO CSR's, boot bus accesses) */
-#else
-	uint64_t mio                          : 1;
-	uint64_t illegal3                     : 2;
-	uint64_t sli                          : 1;
-	uint64_t key                          : 1;
-	uint64_t fpa                          : 1;
-	uint64_t dfa                          : 1;
-	uint64_t zip                          : 1;
-	uint64_t rng                          : 1;
-	uint64_t ipd                          : 1;
-	uint64_t pko                          : 1;
-	uint64_t illegal2                     : 1;
-	uint64_t pow                          : 1;
-	uint64_t usb0                         : 1;
-	uint64_t rad                          : 1;
-	uint64_t illegal                      : 12;
-	uint64_t dpi                          : 1;
-	uint64_t illegal4                     : 2;
-	uint64_t fau                          : 1;
-	uint64_t illegal5                     : 1;
-	uint64_t reserved_32_63               : 32;
-#endif
-	} cn63xx;
-	struct cvmx_tra_trig0_did_cn63xx      cn63xxp1;
-};
-typedef union cvmx_tra_trig0_did cvmx_tra_trig0_did_t;
-
-/**
- * cvmx_tra_trig0_sid
- *
- * TRA_TRIG0_SID = Trace Buffer Filter SourceId Mask
- *
- * Description:
- */
-union cvmx_tra_trig0_sid
-{
-	uint64_t u64;
-	struct cvmx_tra_trig0_sid_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_20_63               : 44;
-	uint64_t dwb                          : 1;  /**< Enable triggering on requests from the IOB DWB engine */
-	uint64_t iobreq                       : 1;  /**< Enable triggering on requests from FPA,TIM,DFA,
-                                                         PCI,ZIP,POW, and PKO (writes) */
-	uint64_t pko                          : 1;  /**< Enable triggering on read requests from PKO */
-	uint64_t pki                          : 1;  /**< Enable triggering on write requests from PIP/IPD */
-	uint64_t pp                           : 16; /**< Enable triggering from PP[N] with matching SourceID
-                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
-#else
-	uint64_t pp                           : 16;
-	uint64_t pki                          : 1;
-	uint64_t pko                          : 1;
-	uint64_t iobreq                       : 1;
-	uint64_t dwb                          : 1;
-	uint64_t reserved_20_63               : 44;
-#endif
-	} s;
-	struct cvmx_tra_trig0_sid_s           cn31xx;
-	struct cvmx_tra_trig0_sid_s           cn38xx;
-	struct cvmx_tra_trig0_sid_s           cn38xxp2;
-	struct cvmx_tra_trig0_sid_s           cn52xx;
-	struct cvmx_tra_trig0_sid_s           cn52xxp1;
-	struct cvmx_tra_trig0_sid_s           cn56xx;
-	struct cvmx_tra_trig0_sid_s           cn56xxp1;
-	struct cvmx_tra_trig0_sid_s           cn58xx;
-	struct cvmx_tra_trig0_sid_s           cn58xxp1;
-	struct cvmx_tra_trig0_sid_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_20_63               : 44;
-	uint64_t dwb                          : 1;  /**< Enable triggering on requests from the IOB DWB engine */
-	uint64_t iobreq                       : 1;  /**< Enable triggering on requests from FPA,TIM,DFA,
-                                                         PCI,ZIP,POW, and PKO (writes) */
-	uint64_t pko                          : 1;  /**< Enable triggering on read requests from PKO */
-	uint64_t pki                          : 1;  /**< Enable triggering on write requests from PIP/IPD */
-	uint64_t reserved_8_15                : 8;
-	uint64_t pp                           : 8;  /**< Enable triggering from PP[N] with matching SourceID
-                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
-#else
-	uint64_t pp                           : 8;
-	uint64_t reserved_8_15                : 8;
-	uint64_t pki                          : 1;
-	uint64_t pko                          : 1;
-	uint64_t iobreq                       : 1;
-	uint64_t dwb                          : 1;
-	uint64_t reserved_20_63               : 44;
-#endif
-	} cn63xx;
-	struct cvmx_tra_trig0_sid_cn63xx      cn63xxp1;
-};
-typedef union cvmx_tra_trig0_sid cvmx_tra_trig0_sid_t;
-
-/**
- * cvmx_tra_trig1_adr_adr
- *
- * TRA_TRIG1_ADR_ADR = Trace Buffer Filter Address Address
- *
- * Description:
- */
-union cvmx_tra_trig1_adr_adr
-{
-	uint64_t u64;
-	struct cvmx_tra_trig1_adr_adr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_38_63               : 26;
-	uint64_t adr                          : 38; /**< Unmasked Address
-                                                         The combination of TRA_TRIG1_ADR_ADR and
-                                                         TRA_TRIG1_ADR_MSK is a masked address to
-                                                         enable tracing of only those commands whose
-                                                         masked address matches */
-#else
-	uint64_t adr                          : 38;
-	uint64_t reserved_38_63               : 26;
-#endif
-	} s;
-	struct cvmx_tra_trig1_adr_adr_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_36_63               : 28;
-	uint64_t adr                          : 36; /**< Unmasked Address
-                                                         The combination of TRA_TRIG1_ADR_ADR and
-                                                         TRA_TRIG1_ADR_MSK is a masked address to
-                                                         enable tracing of only those commands whose
-                                                         masked address matches */
-#else
-	uint64_t adr                          : 36;
-	uint64_t reserved_36_63               : 28;
-#endif
-	} cn31xx;
-	struct cvmx_tra_trig1_adr_adr_cn31xx  cn38xx;
-	struct cvmx_tra_trig1_adr_adr_cn31xx  cn38xxp2;
-	struct cvmx_tra_trig1_adr_adr_cn31xx  cn52xx;
-	struct cvmx_tra_trig1_adr_adr_cn31xx  cn52xxp1;
-	struct cvmx_tra_trig1_adr_adr_cn31xx  cn56xx;
-	struct cvmx_tra_trig1_adr_adr_cn31xx  cn56xxp1;
-	struct cvmx_tra_trig1_adr_adr_cn31xx  cn58xx;
-	struct cvmx_tra_trig1_adr_adr_cn31xx  cn58xxp1;
-	struct cvmx_tra_trig1_adr_adr_s       cn63xx;
-	struct cvmx_tra_trig1_adr_adr_s       cn63xxp1;
-};
-typedef union cvmx_tra_trig1_adr_adr cvmx_tra_trig1_adr_adr_t;
-
-/**
- * cvmx_tra_trig1_adr_msk
- *
- * TRA_TRIG1_ADR_MSK = Trace Buffer Filter Address Mask
- *
- * Description:
- */
-union cvmx_tra_trig1_adr_msk
-{
-	uint64_t u64;
-	struct cvmx_tra_trig1_adr_msk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_38_63               : 26;
-	uint64_t adr                          : 38; /**< Address Mask
-                                                         The combination of TRA_TRIG1_ADR_ADR and
-                                                         TRA_TRIG1_ADR_MSK is a masked address to
-                                                         enable tracing of only those commands whose
-                                                         masked address matches.  When a mask bit is not
-                                                         set, the corresponding address bits are assumed
-                                                         to match.  Also, note that IOBDMAs do not have
-                                                         proper addresses, so when TRA_TRIG1_CMD[IOBDMA]
-                                                         is set, TRA_FILT_TRIG1_MSK must be zero to
-                                                         guarantee that any IOBDMAs are recognized as
-                                                         triggers. */
-#else
-	uint64_t adr                          : 38;
-	uint64_t reserved_38_63               : 26;
-#endif
-	} s;
-	struct cvmx_tra_trig1_adr_msk_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_36_63               : 28;
-	uint64_t adr                          : 36; /**< Address Mask
-                                                         The combination of TRA_TRIG1_ADR_ADR and
-                                                         TRA_TRIG1_ADR_MSK is a masked address to
-                                                         enable tracing of only those commands whose
-                                                         masked address matches.  When a mask bit is not
-                                                         set, the corresponding address bits are assumed
-                                                         to match.  Also, note that IOBDMAs do not have
-                                                         proper addresses, so when TRA_TRIG1_CMD[IOBDMA]
-                                                         is set, TRA_FILT_TRIG1_MSK must be zero to
-                                                         guarantee that any IOBDMAs are recognized as
-                                                         triggers. */
-#else
-	uint64_t adr                          : 36;
-	uint64_t reserved_36_63               : 28;
-#endif
-	} cn31xx;
-	struct cvmx_tra_trig1_adr_msk_cn31xx  cn38xx;
-	struct cvmx_tra_trig1_adr_msk_cn31xx  cn38xxp2;
-	struct cvmx_tra_trig1_adr_msk_cn31xx  cn52xx;
-	struct cvmx_tra_trig1_adr_msk_cn31xx  cn52xxp1;
-	struct cvmx_tra_trig1_adr_msk_cn31xx  cn56xx;
-	struct cvmx_tra_trig1_adr_msk_cn31xx  cn56xxp1;
-	struct cvmx_tra_trig1_adr_msk_cn31xx  cn58xx;
-	struct cvmx_tra_trig1_adr_msk_cn31xx  cn58xxp1;
-	struct cvmx_tra_trig1_adr_msk_s       cn63xx;
-	struct cvmx_tra_trig1_adr_msk_s       cn63xxp1;
-};
-typedef union cvmx_tra_trig1_adr_msk cvmx_tra_trig1_adr_msk_t;
-
-/**
- * cvmx_tra_trig1_cmd
- *
- * TRA_TRIG1_CMD = Trace Buffer Filter Command Mask
- *
- * Description:
- *
- * Notes:
- * Note that the trace buffer does not do proper IOBDMA address compares.  Thus, if IOBDMA is set, then
- * the address compare must be disabled (i.e. TRA_TRIG1_ADR_MSK set to zero) to guarantee that IOBDMAs
- * are recognized as triggers.
- */
-union cvmx_tra_trig1_cmd
-{
-	uint64_t u64;
-	struct cvmx_tra_trig1_cmd_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t saa64                        : 1;  /**< Enable SAA64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t saa32                        : 1;  /**< Enable SAA32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_60_61               : 2;
-	uint64_t faa64                        : 1;  /**< Enable FAA64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t faa32                        : 1;  /**< Enable FAA32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_56_57               : 2;
-	uint64_t decr64                       : 1;  /**< Enable DECR64  tracing
-                                                         0=disable, 1=enable */
-	uint64_t decr32                       : 1;  /**< Enable DECR32  tracing
-                                                         0=disable, 1=enable */
-	uint64_t decr16                       : 1;  /**< Enable DECR16  tracing
-                                                         0=disable, 1=enable */
-	uint64_t decr8                        : 1;  /**< Enable DECR8   tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr64                       : 1;  /**< Enable INCR64  tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr32                       : 1;  /**< Enable INCR32  tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr16                       : 1;  /**< Enable INCR16  tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr8                        : 1;  /**< Enable INCR8   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr64                        : 1;  /**< Enable CLR64   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr32                        : 1;  /**< Enable CLR32   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr16                        : 1;  /**< Enable CLR16   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr8                         : 1;  /**< Enable CLR8    tracing
-                                                         0=disable, 1=enable */
-	uint64_t set64                        : 1;  /**< Enable SET64   tracing
-                                                         0=disable, 1=enable */
-	uint64_t set32                        : 1;  /**< Enable SET32   tracing
-                                                         0=disable, 1=enable */
-	uint64_t set16                        : 1;  /**< Enable SET16   tracing
-                                                         0=disable, 1=enable */
-	uint64_t set8                         : 1;  /**< Enable SET8    tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst64                      : 1;  /**< Enable IOBST64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst32                      : 1;  /**< Enable IOBST32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst16                      : 1;  /**< Enable IOBST16 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst8                       : 1;  /**< Enable IOBST8  tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_32_35               : 4;
-	uint64_t lckl2                        : 1;  /**< Enable LCKL2   tracing
-                                                         0=disable, 1=enable */
-	uint64_t wbl2                         : 1;  /**< Enable WBL2    tracing
-                                                         0=disable, 1=enable */
-	uint64_t wbil2                        : 1;  /**< Enable WBIL2   tracing
-                                                         0=disable, 1=enable */
-	uint64_t invl2                        : 1;  /**< Enable INVL2   tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_27_27               : 1;
-	uint64_t stgl2i                       : 1;  /**< Enable STGL2I  tracing
-                                                         0=disable, 1=enable */
-	uint64_t ltgl2i                       : 1;  /**< Enable LTGL2I  tracing
-                                                         0=disable, 1=enable */
-	uint64_t wbil2i                       : 1;  /**< Enable WBIL2I  tracing
-                                                         0=disable, 1=enable */
-	uint64_t fas64                        : 1;  /**< Enable FAS64   tracing
-                                                         0=disable, 1=enable */
-	uint64_t fas32                        : 1;  /**< Enable FAS32   tracing
-                                                         0=disable, 1=enable */
-	uint64_t sttil1                       : 1;  /**< Enable STTIL1  tracing
-                                                         0=disable, 1=enable */
-	uint64_t stfil1                       : 1;  /**< Enable STFIL1  tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_16_19               : 4;
-	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_0_13                : 14;
-#else
-	uint64_t reserved_0_13                : 14;
-	uint64_t iobst                        : 1;
-	uint64_t iobdma                       : 1;
-	uint64_t reserved_16_19               : 4;
-	uint64_t stfil1                       : 1;
-	uint64_t sttil1                       : 1;
-	uint64_t fas32                        : 1;
-	uint64_t fas64                        : 1;
-	uint64_t wbil2i                       : 1;
-	uint64_t ltgl2i                       : 1;
-	uint64_t stgl2i                       : 1;
-	uint64_t reserved_27_27               : 1;
-	uint64_t invl2                        : 1;
-	uint64_t wbil2                        : 1;
-	uint64_t wbl2                         : 1;
-	uint64_t lckl2                        : 1;
-	uint64_t reserved_32_35               : 4;
-	uint64_t iobst8                       : 1;
-	uint64_t iobst16                      : 1;
-	uint64_t iobst32                      : 1;
-	uint64_t iobst64                      : 1;
-	uint64_t set8                         : 1;
-	uint64_t set16                        : 1;
-	uint64_t set32                        : 1;
-	uint64_t set64                        : 1;
-	uint64_t clr8                         : 1;
-	uint64_t clr16                        : 1;
-	uint64_t clr32                        : 1;
-	uint64_t clr64                        : 1;
-	uint64_t incr8                        : 1;
-	uint64_t incr16                       : 1;
-	uint64_t incr32                       : 1;
-	uint64_t incr64                       : 1;
-	uint64_t decr8                        : 1;
-	uint64_t decr16                       : 1;
-	uint64_t decr32                       : 1;
-	uint64_t decr64                       : 1;
-	uint64_t reserved_56_57               : 2;
-	uint64_t faa32                        : 1;
-	uint64_t faa64                        : 1;
-	uint64_t reserved_60_61               : 2;
-	uint64_t saa32                        : 1;
-	uint64_t saa64                        : 1;
-#endif
-	} s;
-	struct cvmx_tra_trig1_cmd_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_16_63               : 48;
-	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
-                                                         0=disable, 1=enable */
-	uint64_t stt                          : 1;  /**< Enable STT     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stp                          : 1;  /**< Enable STP     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stc                          : 1;  /**< Enable STC     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stf                          : 1;  /**< Enable STF     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
-                                                         0=disable, 1=enable */
-	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
-                                                         0=disable, 1=enable */
-	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
-                                                         0=disable, 1=enable */
-	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
-                                                         0=disable, 1=enable */
-#else
-	uint64_t dwb                          : 1;
-	uint64_t pl2                          : 1;
-	uint64_t psl1                         : 1;
-	uint64_t ldd                          : 1;
-	uint64_t ldi                          : 1;
-	uint64_t ldt                          : 1;
-	uint64_t stf                          : 1;
-	uint64_t stc                          : 1;
-	uint64_t stp                          : 1;
-	uint64_t stt                          : 1;
-	uint64_t iobld8                       : 1;
-	uint64_t iobld16                      : 1;
-	uint64_t iobld32                      : 1;
-	uint64_t iobld64                      : 1;
-	uint64_t iobst                        : 1;
-	uint64_t iobdma                       : 1;
-	uint64_t reserved_16_63               : 48;
-#endif
-	} cn31xx;
-	struct cvmx_tra_trig1_cmd_cn31xx      cn38xx;
-	struct cvmx_tra_trig1_cmd_cn31xx      cn38xxp2;
-	struct cvmx_tra_trig1_cmd_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_17_63               : 47;
-	uint64_t saa                          : 1;  /**< Enable SAA     tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
-                                                         0=disable, 1=enable */
-	uint64_t stt                          : 1;  /**< Enable STT     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stp                          : 1;  /**< Enable STP     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stc                          : 1;  /**< Enable STC     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stf                          : 1;  /**< Enable STF     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
-                                                         0=disable, 1=enable */
-	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
-                                                         0=disable, 1=enable */
-	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
-                                                         0=disable, 1=enable */
-	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
-                                                         0=disable, 1=enable */
-#else
-	uint64_t dwb                          : 1;
-	uint64_t pl2                          : 1;
-	uint64_t psl1                         : 1;
-	uint64_t ldd                          : 1;
-	uint64_t ldi                          : 1;
-	uint64_t ldt                          : 1;
-	uint64_t stf                          : 1;
-	uint64_t stc                          : 1;
-	uint64_t stp                          : 1;
-	uint64_t stt                          : 1;
-	uint64_t iobld8                       : 1;
-	uint64_t iobld16                      : 1;
-	uint64_t iobld32                      : 1;
-	uint64_t iobld64                      : 1;
-	uint64_t iobst                        : 1;
-	uint64_t iobdma                       : 1;
-	uint64_t saa                          : 1;
-	uint64_t reserved_17_63               : 47;
-#endif
-	} cn52xx;
-	struct cvmx_tra_trig1_cmd_cn52xx      cn52xxp1;
-	struct cvmx_tra_trig1_cmd_cn52xx      cn56xx;
-	struct cvmx_tra_trig1_cmd_cn52xx      cn56xxp1;
-	struct cvmx_tra_trig1_cmd_cn52xx      cn58xx;
-	struct cvmx_tra_trig1_cmd_cn52xx      cn58xxp1;
-	struct cvmx_tra_trig1_cmd_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t saa64                        : 1;  /**< Enable SAA64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t saa32                        : 1;  /**< Enable SAA32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_60_61               : 2;
-	uint64_t faa64                        : 1;  /**< Enable FAA64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t faa32                        : 1;  /**< Enable FAA32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_56_57               : 2;
-	uint64_t decr64                       : 1;  /**< Enable DECR64  tracing
-                                                         0=disable, 1=enable */
-	uint64_t decr32                       : 1;  /**< Enable DECR32  tracing
-                                                         0=disable, 1=enable */
-	uint64_t decr16                       : 1;  /**< Enable DECR16  tracing
-                                                         0=disable, 1=enable */
-	uint64_t decr8                        : 1;  /**< Enable DECR8   tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr64                       : 1;  /**< Enable INCR64  tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr32                       : 1;  /**< Enable INCR32  tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr16                       : 1;  /**< Enable INCR16  tracing
-                                                         0=disable, 1=enable */
-	uint64_t incr8                        : 1;  /**< Enable INCR8   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr64                        : 1;  /**< Enable CLR64   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr32                        : 1;  /**< Enable CLR32   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr16                        : 1;  /**< Enable CLR16   tracing
-                                                         0=disable, 1=enable */
-	uint64_t clr8                         : 1;  /**< Enable CLR8    tracing
-                                                         0=disable, 1=enable */
-	uint64_t set64                        : 1;  /**< Enable SET64   tracing
-                                                         0=disable, 1=enable */
-	uint64_t set32                        : 1;  /**< Enable SET32   tracing
-                                                         0=disable, 1=enable */
-	uint64_t set16                        : 1;  /**< Enable SET16   tracing
-                                                         0=disable, 1=enable */
-	uint64_t set8                         : 1;  /**< Enable SET8    tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst64                      : 1;  /**< Enable IOBST64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst32                      : 1;  /**< Enable IOBST32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst16                      : 1;  /**< Enable IOBST16 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobst8                       : 1;  /**< Enable IOBST8  tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
-                                                         0=disable, 1=enable */
-	uint64_t lckl2                        : 1;  /**< Enable LCKL2   tracing
-                                                         0=disable, 1=enable */
-	uint64_t wbl2                         : 1;  /**< Enable WBL2    tracing
-                                                         0=disable, 1=enable */
-	uint64_t wbil2                        : 1;  /**< Enable WBIL2   tracing
-                                                         0=disable, 1=enable */
-	uint64_t invl2                        : 1;  /**< Enable INVL2   tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_27_27               : 1;
-	uint64_t stgl2i                       : 1;  /**< Enable STGL2I  tracing
-                                                         0=disable, 1=enable */
-	uint64_t ltgl2i                       : 1;  /**< Enable LTGL2I  tracing
-                                                         0=disable, 1=enable */
-	uint64_t wbil2i                       : 1;  /**< Enable WBIL2I  tracing
-                                                         0=disable, 1=enable */
-	uint64_t fas64                        : 1;  /**< Enable FAS64   tracing
-                                                         0=disable, 1=enable */
-	uint64_t fas32                        : 1;  /**< Enable FAS32   tracing
-                                                         0=disable, 1=enable */
-	uint64_t sttil1                       : 1;  /**< Enable STTIL1  tracing
-                                                         0=disable, 1=enable */
-	uint64_t stfil1                       : 1;  /**< Enable STFIL1  tracing
-                                                         0=disable, 1=enable */
-	uint64_t stc                          : 1;  /**< Enable STC     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stp                          : 1;  /**< Enable STP     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stt                          : 1;  /**< Enable STT     tracing
-                                                         0=disable, 1=enable */
-	uint64_t stf                          : 1;  /**< Enable STF     tracing
-                                                         0=disable, 1=enable */
-	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_10_14               : 5;
-	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
-                                                         0=disable, 1=enable */
-	uint64_t reserved_6_7                 : 2;
-	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
-                                                         0=disable, 1=enable */
-	uint64_t rpl2                         : 1;  /**< Enable RPL2    tracing
-                                                         0=disable, 1=enable */
-	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
-                                                         0=disable, 1=enable */
-	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
-                                                         0=disable, 1=enable */
-	uint64_t nop                          : 1;  /**< Enable NOP     tracing
-                                                         0=disable, 1=enable */
-#else
-	uint64_t nop                          : 1;
-	uint64_t ldt                          : 1;
-	uint64_t ldi                          : 1;
-	uint64_t pl2                          : 1;
-	uint64_t rpl2                         : 1;
-	uint64_t dwb                          : 1;
-	uint64_t reserved_6_7                 : 2;
-	uint64_t ldd                          : 1;
-	uint64_t psl1                         : 1;
-	uint64_t reserved_10_14               : 5;
-	uint64_t iobdma                       : 1;
-	uint64_t stf                          : 1;
-	uint64_t stt                          : 1;
-	uint64_t stp                          : 1;
-	uint64_t stc                          : 1;
-	uint64_t stfil1                       : 1;
-	uint64_t sttil1                       : 1;
-	uint64_t fas32                        : 1;
-	uint64_t fas64                        : 1;
-	uint64_t wbil2i                       : 1;
-	uint64_t ltgl2i                       : 1;
-	uint64_t stgl2i                       : 1;
-	uint64_t reserved_27_27               : 1;
-	uint64_t invl2                        : 1;
-	uint64_t wbil2                        : 1;
-	uint64_t wbl2                         : 1;
-	uint64_t lckl2                        : 1;
-	uint64_t iobld8                       : 1;
-	uint64_t iobld16                      : 1;
-	uint64_t iobld32                      : 1;
-	uint64_t iobld64                      : 1;
-	uint64_t iobst8                       : 1;
-	uint64_t iobst16                      : 1;
-	uint64_t iobst32                      : 1;
-	uint64_t iobst64                      : 1;
-	uint64_t set8                         : 1;
-	uint64_t set16                        : 1;
-	uint64_t set32                        : 1;
-	uint64_t set64                        : 1;
-	uint64_t clr8                         : 1;
-	uint64_t clr16                        : 1;
-	uint64_t clr32                        : 1;
-	uint64_t clr64                        : 1;
-	uint64_t incr8                        : 1;
-	uint64_t incr16                       : 1;
-	uint64_t incr32                       : 1;
-	uint64_t incr64                       : 1;
-	uint64_t decr8                        : 1;
-	uint64_t decr16                       : 1;
-	uint64_t decr32                       : 1;
-	uint64_t decr64                       : 1;
-	uint64_t reserved_56_57               : 2;
-	uint64_t faa32                        : 1;
-	uint64_t faa64                        : 1;
-	uint64_t reserved_60_61               : 2;
-	uint64_t saa32                        : 1;
-	uint64_t saa64                        : 1;
-#endif
-	} cn63xx;
-	struct cvmx_tra_trig1_cmd_cn63xx      cn63xxp1;
-};
-typedef union cvmx_tra_trig1_cmd cvmx_tra_trig1_cmd_t;
-
-/**
- * cvmx_tra_trig1_did
- *
- * TRA_TRIG1_DID = Trace Buffer Filter DestinationId Mask
- *
- * Description:
- */
-union cvmx_tra_trig1_did
-{
-	uint64_t u64;
-	struct cvmx_tra_trig1_did_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_13_63               : 51;
-	uint64_t pow                          : 1;  /**< Enable triggering on requests to POW
-                                                         (get work, add work, status/memory/index
-                                                         loads, NULLRd loads, CSR's) */
-	uint64_t reserved_9_11                : 3;
-	uint64_t rng                          : 1;  /**< Enable triggering on requests to RNG
-                                                         (loads/IOBDMA's are legal) */
-	uint64_t zip                          : 1;  /**< Enable triggering on requests to ZIP
-                                                         (doorbell stores are legal) */
-	uint64_t dfa                          : 1;  /**< Enable triggering on requests to DFA
-                                                         (CSR's and operations are legal) */
-	uint64_t fpa                          : 1;  /**< Enable triggering on requests to FPA
-                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
-	uint64_t key                          : 1;  /**< Enable triggering on requests to KEY memory
-                                                         (loads/IOBDMA's/stores are legal) */
-	uint64_t reserved_3_3                 : 1;
-	uint64_t illegal3                     : 2;  /**< Illegal destinations */
-	uint64_t mio                          : 1;  /**< Enable triggering on MIO accesses
-                                                         (CIU and GPIO CSR's, boot bus accesses) */
-#else
-	uint64_t mio                          : 1;
-	uint64_t illegal3                     : 2;
-	uint64_t reserved_3_3                 : 1;
-	uint64_t key                          : 1;
-	uint64_t fpa                          : 1;
-	uint64_t dfa                          : 1;
-	uint64_t zip                          : 1;
-	uint64_t rng                          : 1;
-	uint64_t reserved_9_11                : 3;
-	uint64_t pow                          : 1;
-	uint64_t reserved_13_63               : 51;
-#endif
-	} s;
-	struct cvmx_tra_trig1_did_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_32_63               : 32;
-	uint64_t illegal                      : 19; /**< Illegal destinations */
-	uint64_t pow                          : 1;  /**< Enable triggering on requests to POW
-                                                         (get work, add work, status/memory/index
-                                                         loads, NULLRd loads, CSR's) */
-	uint64_t illegal2                     : 3;  /**< Illegal destinations */
-	uint64_t rng                          : 1;  /**< Enable triggering on requests to RNG
-                                                         (loads/IOBDMA's are legal) */
-	uint64_t zip                          : 1;  /**< Enable triggering on requests to ZIP
-                                                         (doorbell stores are legal) */
-	uint64_t dfa                          : 1;  /**< Enable triggering on requests to DFA
-                                                         (CSR's and operations are legal) */
-	uint64_t fpa                          : 1;  /**< Enable triggering on requests to FPA
-                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
-	uint64_t key                          : 1;  /**< Enable triggering on requests to KEY memory
-                                                         (loads/IOBDMA's/stores are legal) */
-	uint64_t pci                          : 1;  /**< Enable triggering on requests to PCI and RSL-type
-                                                         CSR's (RSL CSR's, PCI bus operations, PCI
-                                                         CSR's) */
-	uint64_t illegal3                     : 2;  /**< Illegal destinations */
-	uint64_t mio                          : 1;  /**< Enable triggering on CIU and GPIO CSR's */
-#else
-	uint64_t mio                          : 1;
-	uint64_t illegal3                     : 2;
-	uint64_t pci                          : 1;
-	uint64_t key                          : 1;
-	uint64_t fpa                          : 1;
-	uint64_t dfa                          : 1;
-	uint64_t zip                          : 1;
-	uint64_t rng                          : 1;
-	uint64_t illegal2                     : 3;
-	uint64_t pow                          : 1;
-	uint64_t illegal                      : 19;
-	uint64_t reserved_32_63               : 32;
-#endif
-	} cn31xx;
-	struct cvmx_tra_trig1_did_cn31xx      cn38xx;
-	struct cvmx_tra_trig1_did_cn31xx      cn38xxp2;
-	struct cvmx_tra_trig1_did_cn31xx      cn52xx;
-	struct cvmx_tra_trig1_did_cn31xx      cn52xxp1;
-	struct cvmx_tra_trig1_did_cn31xx      cn56xx;
-	struct cvmx_tra_trig1_did_cn31xx      cn56xxp1;
-	struct cvmx_tra_trig1_did_cn31xx      cn58xx;
-	struct cvmx_tra_trig1_did_cn31xx      cn58xxp1;
-	struct cvmx_tra_trig1_did_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_32_63               : 32;
-	uint64_t illegal5                     : 1;  /**< Illegal destinations */
-	uint64_t fau                          : 1;  /**< Enable triggering on FAU accesses */
-	uint64_t illegal4                     : 2;  /**< Illegal destinations */
-	uint64_t dpi                          : 1;  /**< Enable triggering on DPI accesses
-                                                         (DPI NCB CSRs) */
-	uint64_t illegal                      : 12; /**< Illegal destinations */
-	uint64_t rad                          : 1;  /**< Enable triggering on RAD accesses
-                                                         (doorbells) */
-	uint64_t usb0                         : 1;  /**< Enable triggering on USB0 accesses
-                                                         (UAHC0 EHCI and OHCI NCB CSRs) */
-	uint64_t pow                          : 1;  /**< Enable triggering on requests to POW
-                                                         (get work, add work, status/memory/index
-                                                         loads, NULLRd loads, CSR's) */
-	uint64_t illegal2                     : 1;  /**< Illegal destination */
-	uint64_t pko                          : 1;  /**< Enable triggering on PKO accesses
-                                                         (doorbells) */
-	uint64_t ipd                          : 1;  /**< Enable triggering on IPD CSR accesses
-                                                         (IPD CSRs) */
-	uint64_t rng                          : 1;  /**< Enable triggering on requests to RNG
-                                                         (loads/IOBDMA's are legal) */
-	uint64_t zip                          : 1;  /**< Enable triggering on requests to ZIP
-                                                         (doorbell stores are legal) */
-	uint64_t dfa                          : 1;  /**< Enable triggering on requests to DFA
-                                                         (CSR's and operations are legal) */
-	uint64_t fpa                          : 1;  /**< Enable triggering on requests to FPA
-                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
-	uint64_t key                          : 1;  /**< Enable triggering on requests to KEY memory
-                                                         (loads/IOBDMA's/stores are legal) */
-	uint64_t sli                          : 1;  /**< Enable triggering on requests to SLI and RSL-type
-                                                         CSR's (RSL CSR's, PCI/sRIO bus operations, SLI
-                                                         CSR's) */
-	uint64_t illegal3                     : 2;  /**< Illegal destinations */
-	uint64_t mio                          : 1;  /**< Enable triggering on MIO accesses
-                                                         (CIU and GPIO CSR's, boot bus accesses) */
-#else
-	uint64_t mio                          : 1;
-	uint64_t illegal3                     : 2;
-	uint64_t sli                          : 1;
-	uint64_t key                          : 1;
-	uint64_t fpa                          : 1;
-	uint64_t dfa                          : 1;
-	uint64_t zip                          : 1;
-	uint64_t rng                          : 1;
-	uint64_t ipd                          : 1;
-	uint64_t pko                          : 1;
-	uint64_t illegal2                     : 1;
-	uint64_t pow                          : 1;
-	uint64_t usb0                         : 1;
-	uint64_t rad                          : 1;
-	uint64_t illegal                      : 12;
-	uint64_t dpi                          : 1;
-	uint64_t illegal4                     : 2;
-	uint64_t fau                          : 1;
-	uint64_t illegal5                     : 1;
-	uint64_t reserved_32_63               : 32;
-#endif
-	} cn63xx;
-	struct cvmx_tra_trig1_did_cn63xx      cn63xxp1;
-};
-typedef union cvmx_tra_trig1_did cvmx_tra_trig1_did_t;
-
-/**
- * cvmx_tra_trig1_sid
- *
- * TRA_TRIG1_SID = Trace Buffer Filter SourceId Mask
- *
- * Description:
- */
-union cvmx_tra_trig1_sid
-{
-	uint64_t u64;
-	struct cvmx_tra_trig1_sid_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_20_63               : 44;
-	uint64_t dwb                          : 1;  /**< Enable triggering on requests from the IOB DWB engine */
-	uint64_t iobreq                       : 1;  /**< Enable triggering on requests from FPA,TIM,DFA,
-                                                         PCI,ZIP,POW, and PKO (writes) */
-	uint64_t pko                          : 1;  /**< Enable triggering on read requests from PKO */
-	uint64_t pki                          : 1;  /**< Enable triggering on write requests from PIP/IPD */
-	uint64_t pp                           : 16; /**< Enable trigering from PP[N] with matching SourceID
-                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
-#else
-	uint64_t pp                           : 16;
-	uint64_t pki                          : 1;
-	uint64_t pko                          : 1;
-	uint64_t iobreq                       : 1;
-	uint64_t dwb                          : 1;
-	uint64_t reserved_20_63               : 44;
-#endif
-	} s;
-	struct cvmx_tra_trig1_sid_s           cn31xx;
-	struct cvmx_tra_trig1_sid_s           cn38xx;
-	struct cvmx_tra_trig1_sid_s           cn38xxp2;
-	struct cvmx_tra_trig1_sid_s           cn52xx;
-	struct cvmx_tra_trig1_sid_s           cn52xxp1;
-	struct cvmx_tra_trig1_sid_s           cn56xx;
-	struct cvmx_tra_trig1_sid_s           cn56xxp1;
-	struct cvmx_tra_trig1_sid_s           cn58xx;
-	struct cvmx_tra_trig1_sid_s           cn58xxp1;
-	struct cvmx_tra_trig1_sid_cn63xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_20_63               : 44;
-	uint64_t dwb                          : 1;  /**< Enable triggering on requests from the IOB DWB engine */
-	uint64_t iobreq                       : 1;  /**< Enable triggering on requests from FPA,TIM,DFA,
-                                                         PCI,ZIP,POW, and PKO (writes) */
-	uint64_t pko                          : 1;  /**< Enable triggering on read requests from PKO */
-	uint64_t pki                          : 1;  /**< Enable triggering on write requests from PIP/IPD */
-	uint64_t reserved_8_15                : 8;
-	uint64_t pp                           : 8;  /**< Enable trigering from PP[N] with matching SourceID
-                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
-#else
-	uint64_t pp                           : 8;
-	uint64_t reserved_8_15                : 8;
-	uint64_t pki                          : 1;
-	uint64_t pko                          : 1;
-	uint64_t iobreq                       : 1;
-	uint64_t dwb                          : 1;
-	uint64_t reserved_20_63               : 44;
-#endif
-	} cn63xx;
-	struct cvmx_tra_trig1_sid_cn63xx      cn63xxp1;
-};
-typedef union cvmx_tra_trig1_sid cvmx_tra_trig1_sid_t;
+#include "cvmx-trax-defs.h"
+
+#define CVMX_TRA_BIST_STATUS (CVMX_TRAX_BIST_STATUS(0))
+#define CVMX_TRA_CTL (CVMX_TRAX_CTL(0))
+#define CVMX_TRA_CYCLES_SINCE (CVMX_TRAX_CYCLES_SINCE(0))
+#define CVMX_TRA_CYCLES_SINCE1 (CVMX_TRAX_CYCLES_SINCE1(0))
+#define CVMX_TRA_FILT_ADR_ADR (CVMX_TRAX_FILT_ADR_ADR(0))
+#define CVMX_TRA_FILT_ADR_MSK (CVMX_TRAX_FILT_ADR_MSK(0))
+#define CVMX_TRA_FILT_CMD (CVMX_TRAX_FILT_CMD(0))
+#define CVMX_TRA_FILT_DID (CVMX_TRAX_FILT_DID(0))
+#define CVMX_TRA_FILT_SID (CVMX_TRAX_FILT_SID(0))
+#define CVMX_TRA_INT_STATUS (CVMX_TRAX_INT_STATUS(0))
+#define CVMX_TRA_READ_DAT (CVMX_TRAX_READ_DAT(0))
+#define CVMX_TRA_READ_DAT_HI (CVMX_TRAX_READ_DAT_HI(0))
+#define CVMX_TRA_TRIG0_ADR_ADR (CVMX_TRAX_TRIG0_ADR_ADR(0))
+#define CVMX_TRA_TRIG0_ADR_MSK (CVMX_TRAX_TRIG0_ADR_MSK(0))
+#define CVMX_TRA_TRIG0_CMD (CVMX_TRAX_TRIG0_CMD(0))
+#define CVMX_TRA_TRIG0_DID (CVMX_TRAX_TRIG0_DID(0))
+#define CVMX_TRA_TRIG0_SID (CVMX_TRAX_TRIG0_SID(0))
+#define CVMX_TRA_TRIG1_ADR_ADR (CVMX_TRAX_TRIG1_ADR_ADR(0))
+#define CVMX_TRA_TRIG1_ADR_MSK (CVMX_TRAX_TRIG1_ADR_MSK(0))
+#define CVMX_TRA_TRIG1_CMD (CVMX_TRAX_TRIG1_CMD(0))
+#define CVMX_TRA_TRIG1_DID (CVMX_TRAX_TRIG1_DID(0))
+#define CVMX_TRA_TRIG1_SID (CVMX_TRAX_TRIG1_SID(0))
+
+typedef union cvmx_trax_bist_status cvmx_tra_bist_status_t;
+typedef union cvmx_trax_ctl cvmx_tra_ctl_t;
+typedef union cvmx_trax_cycles_since cvmx_tra_cycles_since_t;
+typedef union cvmx_trax_cycles_since1 cvmx_tra_cycles_since1_t;
+typedef union cvmx_trax_filt_adr_adr cvmx_tra_filt_adr_adr_t;
+typedef union cvmx_trax_filt_adr_msk cvmx_tra_filt_adr_msk_t;
+typedef union cvmx_trax_filt_cmd cvmx_tra_filt_cmd_t;
+typedef union cvmx_trax_filt_did cvmx_tra_filt_did_t;
+typedef union cvmx_trax_filt_sid cvmx_tra_filt_sid_t;
+typedef union cvmx_trax_int_status cvmx_tra_int_status_t;
+typedef union cvmx_trax_read_dat cvmx_tra_read_dat_t;
+typedef union cvmx_trax_read_dat_hi cvmx_tra_read_dat_hi_t;
+typedef union cvmx_trax_trig0_adr_adr cvmx_tra_trig0_adr_adr_t;
+typedef union cvmx_trax_trig0_adr_msk cvmx_tra_trig0_adr_msk_t;
+typedef union cvmx_trax_trig0_cmd cvmx_tra_trig0_cmd_t;
+typedef union cvmx_trax_trig0_did cvmx_tra_trig0_did_t;
+typedef union cvmx_trax_trig0_sid cvmx_tra_trig0_sid_t;
+typedef union cvmx_trax_trig1_adr_adr cvmx_tra_trig1_adr_adr_t;
+typedef union cvmx_trax_trig1_adr_msk cvmx_tra_trig1_adr_msk_t;
+typedef union cvmx_trax_trig1_cmd cvmx_tra_trig1_cmd_t;
+typedef union cvmx_trax_trig1_did cvmx_tra_trig1_did_t;
+typedef union cvmx_trax_trig1_sid cvmx_tra_trig1_sid_t;
 
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-tra.c b/sys/contrib/octeon-sdk/cvmx-tra.c
index e1585ec..4bf8f45 100644
--- a/sys/contrib/octeon-sdk/cvmx-tra.c
+++ b/sys/contrib/octeon-sdk/cvmx-tra.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -53,9 +53,11 @@
 #include <linux/module.h>
 #include <asm/octeon/cvmx.h>
 #include <asm/octeon/cvmx-tra.h>
+#include <asm/octeon/cvmx-l2c.h>
 #else
 #include "cvmx.h"
 #include "cvmx-tra.h"
+#include "cvmx-l2c.h"
 #endif
 
 static const char *TYPE_ARRAY[] = {
@@ -192,7 +194,23 @@ static const char *SOURCE_ARRAY[] = {
     "RSVD28",
     "RSVD29",
     "RSVD30",
-    "RSVD31"
+    "RSVD31",
+    "PP16",
+    "PP17",
+    "PP18",
+    "PP19",
+    "PP20",
+    "PP21",
+    "PP22",
+    "PP23",
+    "PP24",
+    "PP25",
+    "PP26",
+    "PP27",
+    "PP28",
+    "PP29",
+    "PP30",
+    "PP31"
 };
 
 static const char *DEST_ARRAY[] = {
@@ -230,6 +248,8 @@ static const char *DEST_ARRAY[] = {
     "RSVD31"
 };
 
+int _cvmx_tra_unit = 0;
+
 #define CVMX_TRA_SOURCE_MASK       (OCTEON_IS_MODEL(OCTEON_CN63XX) ? 0xf00ff : 0xfffff)
 #define CVMX_TRA_DESTINATION_MASK  0xfffffffful
 
@@ -302,6 +322,7 @@ static uint64_t __cvmx_tra_set_filter_cmd_mask(cvmx_tra_filt_t filter)
 
         filter_command.cn63xx.reserved_60_61 = 0;
         filter_command.cn63xx.reserved_56_57 = 0;
+        filter_command.cn63xx.reserved_27_27 = 0;
         filter_command.cn63xx.reserved_10_14 = 0;
         filter_command.cn63xx.reserved_6_7 = 0;
     }
@@ -329,22 +350,98 @@ void cvmx_tra_setup(cvmx_tra_ctl_t control, cvmx_tra_filt_t filter,
     cvmx_tra_filt_cmd_t filt_cmd;
     cvmx_tra_filt_sid_t filt_sid;
     cvmx_tra_filt_did_t filt_did;
+    int tad;
 
     filt_cmd.u64 = __cvmx_tra_set_filter_cmd_mask(filter);
     filt_sid.u64 = source_filter & CVMX_TRA_SOURCE_MASK;
     filt_did.u64 = dest_filter & CVMX_TRA_DESTINATION_MASK;
 
-    cvmx_write_csr(CVMX_TRA_CTL,            control.u64);
-    cvmx_write_csr(CVMX_TRA_FILT_CMD,       filt_cmd.u64);
-    cvmx_write_csr(CVMX_TRA_FILT_SID,       filt_sid.u64);
-    cvmx_write_csr(CVMX_TRA_FILT_DID,       filt_did.u64);
-    cvmx_write_csr(CVMX_TRA_FILT_ADR_ADR,   address);
-    cvmx_write_csr(CVMX_TRA_FILT_ADR_MSK,   address_mask);
+    /* Address filtering does not work when IOBDMA filter command is enabled
+       because of some caveats.  Disable the IOBDMA filter command. */
+    if ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) 
+        && ((filt_cmd.u64 & CVMX_TRA_FILT_IOBDMA) == CVMX_TRA_FILT_IOBDMA)
+        && address_mask != 0)
+    {
+        cvmx_dprintf("The address-based filtering does not work with IOBDMAs, disabling the filter command.\n");
+        filt_cmd.u64 &= ~(CVMX_TRA_FILT_IOBDMA);
+    } 
+
+    /* In OcteonII pass2, the mode bit is added to enable reading the trace 
+       buffer data from different registers for lower and upper 64-bit value.
+       This bit is reserved in other Octeon models. */
+    control.s.rdat_md = 1;
+
+    for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+    {
+        cvmx_write_csr(CVMX_TRAX_CTL(tad),            control.u64);
+        cvmx_write_csr(CVMX_TRAX_FILT_CMD(tad),       filt_cmd.u64);
+        cvmx_write_csr(CVMX_TRAX_FILT_SID(tad),       filt_sid.u64);
+        cvmx_write_csr(CVMX_TRAX_FILT_DID(tad),       filt_did.u64);
+        cvmx_write_csr(CVMX_TRAX_FILT_ADR_ADR(tad),   address);
+        cvmx_write_csr(CVMX_TRAX_FILT_ADR_MSK(tad),   address_mask);
+    }
 }
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 EXPORT_SYMBOL(cvmx_tra_setup);
 #endif
 
+/**
+ * Setup each TRA buffer for use
+ *
+ * @param tra     Which TRA buffer to use (0-3)
+ * @param control TRA control setup
+ * @param filter  Which events to log
+ * @param source_filter
+ *                Source match
+ * @param dest_filter
+ *                Destination match
+ * @param address Address compare
+ * @param address_mask
+ *                Address mask
+ */
+void cvmx_tra_setup_v2(int tra, cvmx_tra_ctl_t control, cvmx_tra_filt_t filter,
+                    cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
+                    uint64_t address, uint64_t address_mask)
+{
+    cvmx_tra_filt_cmd_t filt_cmd;
+    cvmx_tra_filt_sid_t filt_sid;
+    cvmx_tra_filt_did_t filt_did;
+
+    if ((tra + 1) > CVMX_L2C_TADS)
+    {
+        cvmx_dprintf("cvmx_tra_setup_per_tra: Invalid tra(%d), max allowed (%d)\n", tra, CVMX_L2C_TADS - 1);
+        tra = 0;
+    }
+
+    filt_cmd.u64 = __cvmx_tra_set_filter_cmd_mask(filter);
+    filt_sid.u64 = source_filter & CVMX_TRA_SOURCE_MASK;
+    filt_did.u64 = dest_filter & CVMX_TRA_DESTINATION_MASK;
+
+    /* Address filtering does not work when IOBDMA filter command is enabled
+       because of some caveats.  Disable the IOBDMA filter command. */
+    if ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) 
+        && ((filt_cmd.u64 & CVMX_TRA_FILT_IOBDMA) == CVMX_TRA_FILT_IOBDMA)
+        && address_mask != 0)
+    {
+        cvmx_dprintf("The address-based filtering does not work with IOBDMAs, disabling the filter command.\n");
+        filt_cmd.u64 &= ~(CVMX_TRA_FILT_IOBDMA);
+    } 
+
+    /* In OcteonII pass2, the mode bit is added to enable reading the trace 
+       buffer data from different registers for lower and upper 64-bit value.
+       This bit is reserved in other Octeon models. */
+    control.s.rdat_md = 1;
+
+    cvmx_write_csr(CVMX_TRAX_CTL(tra),            control.u64);
+    cvmx_write_csr(CVMX_TRAX_FILT_CMD(tra),       filt_cmd.u64);
+    cvmx_write_csr(CVMX_TRAX_FILT_SID(tra),       filt_sid.u64);
+    cvmx_write_csr(CVMX_TRAX_FILT_DID(tra),       filt_did.u64);
+    cvmx_write_csr(CVMX_TRAX_FILT_ADR_ADR(tra),   address);
+    cvmx_write_csr(CVMX_TRAX_FILT_ADR_MSK(tra),   address_mask);
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_tra_setup_v2);
+#endif
 
 /**
  * Setup a TRA trigger. How the triggers are used should be
@@ -367,21 +464,81 @@ void cvmx_tra_trig_setup(uint64_t trigger, cvmx_tra_filt_t filter,
     cvmx_tra_filt_cmd_t tra_filt_cmd;
     cvmx_tra_filt_sid_t tra_filt_sid;
     cvmx_tra_filt_did_t tra_filt_did;
+    int tad;
 
     tra_filt_cmd.u64 = __cvmx_tra_set_filter_cmd_mask(filter);
     tra_filt_sid.u64 = source_filter & CVMX_TRA_SOURCE_MASK;
     tra_filt_did.u64 = dest_filter & CVMX_TRA_DESTINATION_MASK;
 
-    cvmx_write_csr(CVMX_TRA_TRIG0_CMD + trigger * 64,       tra_filt_cmd.u64);
-    cvmx_write_csr(CVMX_TRA_TRIG0_SID + trigger * 64,       tra_filt_sid.u64);
-    cvmx_write_csr(CVMX_TRA_TRIG0_DID + trigger * 64,       tra_filt_did.u64);
-    cvmx_write_csr(CVMX_TRA_TRIG0_ADR_ADR + trigger * 64,   address);
-    cvmx_write_csr(CVMX_TRA_TRIG0_ADR_MSK + trigger * 64,   address_mask);
+    /* Address filtering does not work when IOBDMA filter command is enabled
+       because of some caveats.  Disable the IOBDMA filter command. */
+    if ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) 
+        && ((tra_filt_cmd.u64 & CVMX_TRA_FILT_IOBDMA) == CVMX_TRA_FILT_IOBDMA)
+        && address_mask != 0)
+    {
+        cvmx_dprintf("The address-based filtering does not work with IOBDMAs, disabling the filter command.\n");
+        tra_filt_cmd.u64 &= ~(CVMX_TRA_FILT_IOBDMA);
+    }
+
+    for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+    {
+        cvmx_write_csr(CVMX_TRAX_TRIG0_CMD(tad) + trigger * 64,       tra_filt_cmd.u64);
+        cvmx_write_csr(CVMX_TRAX_TRIG0_SID(tad) + trigger * 64,       tra_filt_sid.u64);
+        cvmx_write_csr(CVMX_TRAX_TRIG0_DID(tad) + trigger * 64,       tra_filt_did.u64);
+        cvmx_write_csr(CVMX_TRAX_TRIG0_ADR_ADR(tad) + trigger * 64,   address);
+        cvmx_write_csr(CVMX_TRAX_TRIG0_ADR_MSK(tad) + trigger * 64,   address_mask);
+    }
 }
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 EXPORT_SYMBOL(cvmx_tra_trig_setup);
 #endif
 
+/**
+ * Setup each TRA trigger. How the triggers are used should be
+ * setup using cvmx_tra_setup.
+ *
+ * @param tra     Which TRA buffer to use (0-3)
+ * @param trigger Trigger to setup (0 or 1)
+ * @param filter  Which types of events to trigger on
+ * @param source_filter
+ *                Source trigger match
+ * @param dest_filter
+ *                Destination trigger match
+ * @param address Trigger address compare
+ * @param address_mask
+ *                Trigger address mask
+ */
+void cvmx_tra_trig_setup_v2(int tra, uint64_t trigger, cvmx_tra_filt_t filter,
+                         cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
+                         uint64_t address, uint64_t address_mask)
+{
+    cvmx_tra_filt_cmd_t tra_filt_cmd;
+    cvmx_tra_filt_sid_t tra_filt_sid;
+    cvmx_tra_filt_did_t tra_filt_did;
+
+    tra_filt_cmd.u64 = __cvmx_tra_set_filter_cmd_mask(filter);
+    tra_filt_sid.u64 = source_filter & CVMX_TRA_SOURCE_MASK;
+    tra_filt_did.u64 = dest_filter & CVMX_TRA_DESTINATION_MASK;
+
+    /* Address filtering does not work when IOBDMA filter command is enabled
+       because of some caveats.  Disable the IOBDMA filter command. */
+    if ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) 
+        && ((tra_filt_cmd.u64 & CVMX_TRA_FILT_IOBDMA) == CVMX_TRA_FILT_IOBDMA)
+        && address_mask != 0)
+    {
+        cvmx_dprintf("The address-based filtering does not work with IOBDMAs, disabling the filter command.\n");
+        tra_filt_cmd.u64 &= ~(CVMX_TRA_FILT_IOBDMA);
+    }
+
+    cvmx_write_csr(CVMX_TRAX_TRIG0_CMD(tra) + trigger * 64,       tra_filt_cmd.u64);
+    cvmx_write_csr(CVMX_TRAX_TRIG0_SID(tra) + trigger * 64,       tra_filt_sid.u64);
+    cvmx_write_csr(CVMX_TRAX_TRIG0_DID(tra) + trigger * 64,       tra_filt_did.u64);
+    cvmx_write_csr(CVMX_TRAX_TRIG0_ADR_ADR(tra) + trigger * 64,   address);
+    cvmx_write_csr(CVMX_TRAX_TRIG0_ADR_MSK(tra) + trigger * 64,   address_mask);
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_tra_trig_setup_v2);
+#endif
 
 /**
  * Read an entry from the TRA buffer
@@ -393,14 +550,21 @@ cvmx_tra_data_t cvmx_tra_read(void)
     uint64_t address = CVMX_TRA_READ_DAT;
     cvmx_tra_data_t result;
 
-    /* The trace buffer format is wider than 64-bits in Octeon2 model,
+    /* The trace buffer format is wider than 64-bits in OcteonII model,
        read the register again to get the second part of the data. */
-    if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) && !OCTEON_IS_MODEL(OCTEON_CN5XXX))
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
     {
         /* These reads need to be as close as possible to each other */
         result.u128.data = cvmx_read_csr(address);
         result.u128.datahi = cvmx_read_csr(address);
     }
+    else if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) && !OCTEON_IS_MODEL(OCTEON_CN5XXX))
+    {
+        /* OcteonII pass2 uses different trace buffer data register for reading
+           lower and upper 64-bit values */
+        result.u128.data = cvmx_read_csr(address);
+        result.u128.datahi = cvmx_read_csr(CVMX_TRA_READ_DAT_HI);
+    }
     else
     {
         result.u128.data = cvmx_read_csr(address);
@@ -411,6 +575,23 @@ cvmx_tra_data_t cvmx_tra_read(void)
 }
 
 /**
+ * Read an entry from the TRA buffer from a given TRA unit.
+ *
+ * @param tra_unit  Trace buffer unit to read
+ *
+ * @return Value return. High bit will be zero if there wasn't any data
+ */
+cvmx_tra_data_t cvmx_tra_read_v2(int tra_unit)
+{
+    cvmx_tra_data_t result;
+
+    result.u128.data = cvmx_read_csr(CVMX_TRAX_READ_DAT(tra_unit));
+    result.u128.datahi = cvmx_read_csr(CVMX_TRAX_READ_DAT_HI(tra_unit));
+
+    return result;
+} 
+
+/**
  * Decode a TRA entry into human readable output
  *
  * @param tra_ctl Trace control setup
@@ -494,6 +675,7 @@ void cvmx_tra_decode_text(cvmx_tra_ctl_t tra_ctl, cvmx_tra_data_t data)
     else
     {
         int type;
+        int srcId;
 
         type = data.cmn2.type;
 
@@ -515,18 +697,40 @@ void cvmx_tra_decode_text(cvmx_tra_ctl_t tra_ctl, cvmx_tra_data_t data)
             case CVMX_TRA_FILT_SET32:
             case CVMX_TRA_FILT_SET16:
             case CVMX_TRA_FILT_SET8:
+            case CVMX_TRA_FILT_LCKL2:
+            case CVMX_TRA_FILT_WBIL2:
+            case CVMX_TRA_FILT_INVL2:
+            case CVMX_TRA_FILT_STGL2I:
+            case CVMX_TRA_FILT_LTGL2I:
+            case CVMX_TRA_FILT_WBIL2I:
             case CVMX_TRA_FILT_WBL2:
             case CVMX_TRA_FILT_DWB:
             case CVMX_TRA_FILT_RPL2:
             case CVMX_TRA_FILT_PL2:
             case CVMX_TRA_FILT_LDI:
             case CVMX_TRA_FILT_LDT:
+                /* CN68XX has 32 cores which are distributed to use different
+                   trace buffers, decode the core that has data */
+                if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+                {
+                    if (data.cmn2.source <= 7)
+                    {
+                        srcId = _cvmx_tra_unit + (data.cmn2.source * 4);
+                        if (srcId >= 16)
+                            srcId += 16;
+                    }
+                    else
+                        srcId = (data.cmn2.source);
+                }
+                else
+                        srcId = (data.cmn2.source);
+                
                 cvmx_dprintf("0x%016llx%016llx %c%+10d %s %s 0x%016llx%llx\n",
                    (unsigned long long)data.u128.datahi, (unsigned long long)data.u128.data,
                    (data.cmn2.discontinuity) ? 'D' : ' ',
                    data.cmn2.timestamp << (tra_ctl.s.time_grn*3),
                    TYPE_ARRAY2[type],
-                   SOURCE_ARRAY[data.cmn2.source],
+                   SOURCE_ARRAY[srcId],
                    (unsigned long long)data.cmn2.addresshi,
                    (unsigned long long)data.cmn2.addresslo);
                 break;
@@ -542,12 +746,30 @@ void cvmx_tra_decode_text(cvmx_tra_ctl_t tra_ctl, cvmx_tra_data_t data)
             case CVMX_TRA_FILT_STF:
             case CVMX_TRA_FILT_STP:
             case CVMX_TRA_FILT_STT:
+            case CVMX_TRA_FILT_STTIL1:
+            case CVMX_TRA_FILT_STFIL1:
+                /* CN68XX has 32 cores which are distributed to use different
+                   trace buffers, decode the core that has data */
+                if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+                {
+                    if (data.store2.source <= 7)
+                    {
+                        srcId = _cvmx_tra_unit + (data.store2.source * 4);
+                        if (srcId >= 16)
+                            srcId += 16;
+                    }
+                    else
+                        srcId = data.store2.source;
+                }
+                else
+                        srcId = data.store2.source;
+
                 cvmx_dprintf("0x%016llx%016llx %c%+10d %s %s mask=0x%02x 0x%016llx%llx\n",
                    (unsigned long long)data.u128.datahi, (unsigned long long)data.u128.data,
                    (data.cmn2.discontinuity) ? 'D' : ' ',
                    data.cmn2.timestamp << (tra_ctl.s.time_grn*3),
                    TYPE_ARRAY2[type],
-                   SOURCE_ARRAY[data.store2.source],
+                   SOURCE_ARRAY[srcId],
                    (unsigned int)data.store2.mask,
                    (unsigned long long)data.store2.addresshi,
                    (unsigned long long)data.store2.addresslo);
@@ -560,24 +782,56 @@ void cvmx_tra_decode_text(cvmx_tra_ctl_t tra_ctl, cvmx_tra_data_t data)
             case CVMX_TRA_FILT_IOBLD32:
             case CVMX_TRA_FILT_IOBLD16:
             case CVMX_TRA_FILT_IOBLD8:
+                /* CN68XX has 32 cores which are distributed to use different
+                   trace buffers, decode the core that has data */
+                if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+                {
+                    if (data.iobld2.source <= 7)
+                    {
+                        srcId = _cvmx_tra_unit + (data.iobld2.source * 4);
+                        if (srcId >= 16)
+                            srcId += 16;
+                    }
+                    else
+                        srcId = data.iobld2.source;
+                }
+                else
+                        srcId = data.iobld2.source;
+
                 cvmx_dprintf("0x%016llx%016llx %c%+10d %s %s->%s subdid=0x%x 0x%016llx%llx\n",
                    (unsigned long long)data.u128.datahi, (unsigned long long)data.u128.data,
                    (data.cmn2.discontinuity) ? 'D' : ' ',
                    data.cmn2.timestamp << (tra_ctl.s.time_grn*3),
                    TYPE_ARRAY2[type],
-                   SOURCE_ARRAY[data.iobld2.source],
+                   SOURCE_ARRAY[srcId],
                    DEST_ARRAY[data.iobld2.dest],
                    (unsigned int)data.iobld2.subid,
                    (unsigned long long)data.iobld2.addresshi,
                    (unsigned long long)data.iobld2.addresslo);
                 break;
             case CVMX_TRA_FILT_IOBDMA:
+                /* CN68XX has 32 cores which are distributed to use different
+                   trace buffers, decode the core that has data */
+                if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+                {
+                    if (data.iob2.source <= 7)
+                    {
+                        srcId = _cvmx_tra_unit + (data.iob2.source * 4);
+                        if (srcId >= 16)
+                            srcId += 16;
+                    }
+                    else
+                        srcId = data.iob2.source;
+                }
+                else
+                        srcId = data.iob2.source;
+
                 cvmx_dprintf("0x%016llx%016llx %c%+10d %s %s->%s len=0x%x 0x%016llx%llx\n",
                    (unsigned long long)data.u128.datahi, (unsigned long long)data.u128.data,
                    (data.iob2.discontinuity) ? 'D' : ' ',
                    data.iob2.timestamp << (tra_ctl.s.time_grn*3),
                    TYPE_ARRAY2[type],
-                   SOURCE_ARRAY[data.iob2.source],
+                   SOURCE_ARRAY[srcId],
                    DEST_ARRAY[data.iob2.dest],
                    (unsigned int)data.iob2.mask,
                    (unsigned long long)data.iob2.addresshi << 3,
@@ -601,27 +855,89 @@ void cvmx_tra_decode_text(cvmx_tra_ctl_t tra_ctl, cvmx_tra_data_t data)
  */
 void cvmx_tra_display(void)
 {
-    cvmx_tra_ctl_t tra_ctl;
-    cvmx_tra_data_t data;
     int valid = 0;
 
-    tra_ctl.u64 = cvmx_read_csr(CVMX_TRA_CTL);
-
-    do
+    /* Collect data from each TRA unit for decoding */
+    if (CVMX_L2C_TADS > 1)
     {
-        data = cvmx_tra_read();
-        if ((OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)) && data.cmn.valid)
-            valid = 1;
-        else if (data.cmn2.valid)
-            valid = 1;
-        else
+        cvmx_trax_ctl_t tra_ctl;
+        cvmx_tra_data_t data[4];
+        int tad;
+        do 
+        {
             valid = 0;
+            for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+                data[tad] = cvmx_tra_read_v2(tad);
+
+            for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+            {
+                tra_ctl.u64 = cvmx_read_csr(CVMX_TRAX_CTL(tad));
+
+                if (data[tad].cmn2.valid)
+                {
+                    _cvmx_tra_unit = tad;
+                    cvmx_tra_decode_text(tra_ctl, data[tad]);
+                    valid = 1;
+                }
+            }
+        } while (valid);
+    }
+    else
+    {
+        cvmx_tra_ctl_t tra_ctl;
+        cvmx_tra_data_t data;
 
-        if (valid)
-            cvmx_tra_decode_text(tra_ctl, data);
+        tra_ctl.u64 = cvmx_read_csr(CVMX_TRA_CTL);
 
-    } while (valid);
+        do
+        {
+            data = cvmx_tra_read();
+            if ((OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)) && data.cmn.valid)
+                valid = 1;
+            else if (data.cmn2.valid)
+                valid = 1;
+            else
+                valid = 0;
+    
+            if (valid)
+                cvmx_tra_decode_text(tra_ctl, data);
+
+        } while (valid);
+    }
 }
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 EXPORT_SYMBOL(cvmx_tra_display);
 #endif
+
+/**
+ * Display the entire trace buffer. It is advised that you
+ * disable the trace buffer before calling this routine
+ * otherwise it could infinitely loop displaying trace data
+ * that it created.
+ *
+ * @param tra_unit   Which TRA buffer to use.
+ */
+void cvmx_tra_display_v2(int tra_unit)
+{
+    int valid = 0;
+
+    cvmx_trax_ctl_t tra_ctl;
+    cvmx_tra_data_t data;
+
+    valid = 0;
+    tra_ctl.u64 = cvmx_read_csr(CVMX_TRAX_CTL(tra_unit));
+
+    do 
+    {
+        data = cvmx_tra_read_v2(tra_unit);
+        if (data.cmn2.valid)
+        {
+            _cvmx_tra_unit = tra_unit; 
+            cvmx_tra_decode_text(tra_ctl, data);
+            valid = 1;
+        }
+    } while (valid);
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_tra_display_v2);
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-tra.h b/sys/contrib/octeon-sdk/cvmx-tra.h
index 74f6192..6a849d5 100644
--- a/sys/contrib/octeon-sdk/cvmx-tra.h
+++ b/sys/contrib/octeon-sdk/cvmx-tra.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -152,9 +152,10 @@
  * - Fields marked as '*' are first filled with '0' at XMC time and may be filled with real data later at XMD time.  Note that the
  * XMD write may be dropped if the shallow FIFO overflows which leaves the '*' fields as '0'.
  * - 2 bits (sta) are used not to trace, but to return global state information with each read, encoded as follows:
- * 0x0-0x1=not valid
- * 0x2=valid, no discontinuity
- * 0x3=valid,    discontinuity
+ * 0x0=not valid
+ * 0x1=valid, no discontinuity
+ * 0x2=not valid, discontinuity
+ * 0x3=valid, discontinuity
  * - commands are encoded as follows:
  * 0x0=DWB
  * 0x1=PL2
@@ -218,13 +219,14 @@
  * 13-31 = illegal
  * @endverbatim
  *
- * <hr>$Revision: 49484 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_TRA_H__
 #define __CVMX_TRA_H__
 
 #include "cvmx.h"
+#include "cvmx-l2c.h"
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include "cvmx-tra-defs.h"
 #endif
@@ -366,7 +368,7 @@ typedef union
 {
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t  datahi;
         uint64_t  data;
 #else
@@ -377,7 +379,7 @@ typedef union
 
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved3   : 64;
         uint64_t    valid       : 1;
         uint64_t    discontinuity:1;
@@ -401,7 +403,7 @@ typedef union
     } cmn; /**< for DWB, PL2, PSL1, LDD, LDI, LDT */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved3   : 64;
         uint64_t    valid       : 1;
         uint64_t    discontinuity:1;
@@ -425,7 +427,7 @@ typedef union
     } store; /**< STC, STF, STP, STT */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved3   : 64;
         uint64_t    valid       : 1;
         uint64_t    discontinuity:1;
@@ -451,7 +453,7 @@ typedef union
     } iobld; /**< for IOBLD8, IOBLD16, IOBLD32, IOBLD64, IOBST, SAA */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved3   : 64;
         uint64_t    valid       : 1;
         uint64_t    discontinuity:1;
@@ -476,10 +478,10 @@ typedef union
 
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved1   : 59;
-        uint64_t    valid       : 1;
         uint64_t    discontinuity:1;
+        uint64_t    valid       : 1;
         uint64_t    addresshi   : 3;   /* Split the address to fit in upper 64 bits  */
         uint64_t    addresslo   : 35;  /* and lower 64-bits. */
         uint64_t    reserved    : 10;
@@ -493,17 +495,17 @@ typedef union
         uint64_t    reserved    : 10;
         uint64_t    addresslo   : 35;
         uint64_t    addresshi   : 3;
-        uint64_t    discontinuity:1;
         uint64_t    valid       : 1;
+        uint64_t    discontinuity:1;
         uint64_t    reserved1   : 59;
 #endif
-    } cmn2; /**< for LDT, LDI, PL2, RPL2, DWB, WBL2, SET*, CLR*, INCR*, DECR* */
+    } cmn2; /**< for LDT, LDI, PL2, RPL2, DWB, WBL2, WBIL2i, LTGL2i, STGL2i, INVL2, WBIL2, LCKL2, SET*, CLR*, INCR*, DECR* */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved1   : 59;
-        uint64_t    valid       : 1;
         uint64_t    discontinuity:1;
+        uint64_t    valid       : 1;
         uint64_t    addresshi   : 3;   /* Split the address to fit in upper 64 bits  */
         uint64_t    addresslo   : 35;  /* and lower 64-bits */
         uint64_t    reserved    : 2;
@@ -519,17 +521,17 @@ typedef union
         uint64_t    reserved    : 2;
         uint64_t    addresslo   : 35;
         uint64_t    addresshi   : 3;
-        uint64_t    discontinuity:1;
         uint64_t    valid       : 1;
+        uint64_t    discontinuity:1;
         uint64_t    reserved1   : 59;
 #endif
-    } store2; /**< for STC, STF, STP, STT, LDD, PSL1, SAA32, SAA64, FAA32, FAA64, FAS32, FAS64 */
+    } store2; /**< for STC, STF, STP, STT, LDD, PSL1, SAA32, SAA64, FAA32, FAA64, FAS32, FAS64, STTIL1, STFIL1 */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved1   : 59;
-        uint64_t    valid       : 1;
         uint64_t    discontinuity:1;
+        uint64_t    valid       : 1;
         uint64_t    addresshi   : 3;   /* Split the address to fit in upper 64 bits  */
         uint64_t    addresslo   : 35;  /* and lower 64-bits */
         uint64_t    reserved    : 2;
@@ -547,17 +549,17 @@ typedef union
         uint64_t    reserved    : 2;
         uint64_t    addresslo   : 35;
         uint64_t    addresshi   : 3;
-        uint64_t    discontinuity:1;
         uint64_t    valid       : 1;
+        uint64_t    discontinuity:1;
         uint64_t    reserved1   : 59;
 #endif
     } iobld2; /**< for IOBLD8, IOBLD16, IOBLD32, IOBLD64, IOBST64, IOBST32, IOBST16, IOBST8 */
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint64_t    reserved1   : 59;
-        uint64_t    valid       : 1;
         uint64_t    discontinuity:1;
+        uint64_t    valid       : 1;
         uint64_t    addresshi   : 3;   /* Split the address to fit in upper 64 bits  */
         uint64_t    addresslo   : 32;  /* and lower 64-bits */
         uint64_t    mask        : 8;
@@ -573,13 +575,15 @@ typedef union
         uint64_t    mask        : 8;
         uint64_t    addresslo   : 32;
 	uint64_t    addresshi   : 3;
-        uint64_t    discontinuity:1;
         uint64_t    valid       : 1;
+        uint64_t    discontinuity:1;
         uint64_t    reserved1   : 59;
 #endif
     } iob2; /**< for IOBDMA */
 } cvmx_tra_data_t;
 
+/* The trace buffer number to use. */
+extern int _cvmx_tra_unit;
 
 /**
  * Setup the TRA buffer for use
@@ -599,6 +603,24 @@ extern void cvmx_tra_setup(cvmx_tra_ctl_t control, cvmx_tra_filt_t filter,
                            uint64_t address, uint64_t address_mask);
 
 /**
+ * Setup each TRA buffer for use
+ *
+ * @param tra     Which TRA buffer to use (0-3)
+ * @param control TRA control setup
+ * @param filter  Which events to log
+ * @param source_filter
+ *                Source match
+ * @param dest_filter
+ *                Destination match
+ * @param address Address compare
+ * @param address_mask
+ *                Address mask
+ */
+extern void cvmx_tra_setup_v2(int tra, cvmx_tra_ctl_t control, cvmx_tra_filt_t filter,
+                             cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
+                             uint64_t address, uint64_t address_mask);
+
+/**
  * Setup a TRA trigger. How the triggers are used should be
  * setup using cvmx_tra_setup.
  *
@@ -617,6 +639,25 @@ extern void cvmx_tra_trig_setup(uint64_t trigger, cvmx_tra_filt_t filter,
                                 uint64_t address, uint64_t address_mask);
 
 /**
+ * Setup each TRA trigger. How the triggers are used should be
+ * setup using cvmx_tra_setup.
+ *
+ * @param tra     Which TRA buffer to use (0-3)
+ * @param trigger Trigger to setup (0 or 1)
+ * @param filter  Which types of events to trigger on
+ * @param source_filter
+ *                Source trigger match
+ * @param dest_filter
+ *                Destination trigger match
+ * @param address Trigger address compare
+ * @param address_mask
+ *                Trigger address mask
+ */
+extern void cvmx_tra_trig_setup_v2(int tra, uint64_t trigger, cvmx_tra_filt_t filter,
+                                cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
+                                uint64_t address, uint64_t address_mask);
+
+/**
  * Read an entry from the TRA buffer. The trace buffer format is
  * different in Octeon2, need to read twice from TRA_READ_DAT.
  *
@@ -625,6 +666,15 @@ extern void cvmx_tra_trig_setup(uint64_t trigger, cvmx_tra_filt_t filter,
 extern cvmx_tra_data_t cvmx_tra_read(void);
 
 /**
+ * Read an entry from the TRA buffer from a given TRA unit.
+ *
+ * @param tra_unit  Trace buffer unit to read
+ *
+ * @return Value return. High bit will be zero if there wasn't any data
+ */
+cvmx_tra_data_t cvmx_tra_read_v2(int tra_unit);
+
+/**
  * Decode a TRA entry into human readable output
  *
  * @param tra_ctl Trace control setup
@@ -641,17 +691,53 @@ extern void cvmx_tra_decode_text(cvmx_tra_ctl_t tra_ctl, cvmx_tra_data_t data);
 extern void cvmx_tra_display(void);
 
 /**
- * Enable or disable the TRA hardware
+ * Display the entire trace buffer. It is advised that you
+ * disable the trace buffer before calling this routine
+ * otherwise it could infinitely loop displaying trace data
+ * that it created.
+ *
+ * @param tra_unit   Which TRA buffer to use.
+ */
+extern void cvmx_tra_display_v2(int tra_unit);
+
+/**
+ * Enable or disable the TRA hardware, by default enables all TRAs.
  *
  * @param enable 1=enable, 0=disable
  */
 static inline void cvmx_tra_enable(int enable)
 {
     cvmx_tra_ctl_t control;
-    control.u64 = cvmx_read_csr(CVMX_TRA_CTL);
+    int tad;
+
+    for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+    {    
+        control.u64 = cvmx_read_csr(CVMX_TRAX_CTL(tad));
+        control.s.ena = enable;
+        cvmx_write_csr(CVMX_TRAX_CTL(tad), control.u64);
+        cvmx_read_csr(CVMX_TRAX_CTL(tad));
+    }
+}
+
+/**
+ * Enable or disable a particular TRA hardware
+ *
+ * @param enable  1=enable, 0=disable
+ * @param tra     which TRA to enable, CN68XX has 4.
+ */
+static inline void cvmx_tra_enable_v2(int enable, int tra)
+{
+    cvmx_tra_ctl_t control;
+
+    if ((tra + 1) > CVMX_L2C_TADS)
+    {
+        cvmx_dprintf("cvmx_tra_enable: Invalid TRA(%d), max allowed are %d\n", tra, CVMX_L2C_TADS - 1);
+        tra = 0;
+    }
+    control.u64 = cvmx_read_csr(CVMX_TRAX_CTL(tra));
     control.s.ena = enable;
-    cvmx_write_csr(CVMX_TRA_CTL, control.u64);
-    cvmx_read_csr(CVMX_TRA_CTL);
+    cvmx_write_csr(CVMX_TRAX_CTL(tra), control.u64);
+    cvmx_read_csr(CVMX_TRAX_CTL(tra));
 }
 
 #ifdef	__cplusplus
diff --git a/sys/contrib/octeon-sdk/cvmx-trax-defs.h b/sys/contrib/octeon-sdk/cvmx-trax-defs.h
new file mode 100644
index 0000000..f3f3631
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-trax-defs.h
@@ -0,0 +1,3590 @@
+/***********************license start***************
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-trax-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon trax.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_TRAX_DEFS_H__
+#define __CVMX_TRAX_DEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_BIST_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A8000010ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000010ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A8000000ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000000ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_CYCLES_SINCE(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_CYCLES_SINCE(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A8000018ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_CYCLES_SINCE(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000018ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_CYCLES_SINCE1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_CYCLES_SINCE1(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A8000028ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_CYCLES_SINCE1(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000028ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_FILT_ADR_ADR(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_FILT_ADR_ADR(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A8000058ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_FILT_ADR_ADR(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000058ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_FILT_ADR_MSK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_FILT_ADR_MSK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A8000060ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_FILT_ADR_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000060ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_FILT_CMD(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_FILT_CMD(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A8000040ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_FILT_CMD(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000040ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_FILT_DID(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_FILT_DID(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A8000050ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_FILT_DID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000050ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_FILT_SID(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_FILT_SID(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A8000048ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_FILT_SID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000048ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_INT_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_INT_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A8000008ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_INT_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000008ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_READ_DAT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_READ_DAT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A8000020ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_READ_DAT(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000020ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_READ_DAT_HI(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_READ_DAT_HI(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A8000030ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_READ_DAT_HI(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000030ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_TRIG0_ADR_ADR(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_TRIG0_ADR_ADR(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A8000098ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_TRIG0_ADR_ADR(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000098ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_TRIG0_ADR_MSK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_TRIG0_ADR_MSK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A80000A0ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_TRIG0_ADR_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000A0ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_TRIG0_CMD(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_TRIG0_CMD(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A8000080ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_TRIG0_CMD(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000080ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_TRIG0_DID(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_TRIG0_DID(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A8000090ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_TRIG0_DID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000090ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_TRIG0_SID(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_TRIG0_SID(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A8000088ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_TRIG0_SID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000088ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_TRIG1_ADR_ADR(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_TRIG1_ADR_ADR(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A80000D8ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_TRIG1_ADR_ADR(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000D8ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_TRIG1_ADR_MSK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_TRIG1_ADR_MSK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A80000E0ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_TRIG1_ADR_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000E0ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_TRIG1_CMD(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_TRIG1_CMD(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A80000C0ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_TRIG1_CMD(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000C0ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_TRIG1_DID(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_TRIG1_DID(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A80000D0ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_TRIG1_DID(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000D0ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_TRAX_TRIG1_SID(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_TRAX_TRIG1_SID(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800A80000C8ull) + ((block_id) & 3) * 0x100000ull;
+}
+#else
+#define CVMX_TRAX_TRIG1_SID(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000C8ull) + ((block_id) & 3) * 0x100000ull)
+#endif
+
+/**
+ * cvmx_tra#_bist_status
+ *
+ * TRA_BIST_STATUS = Trace Buffer BiST Status
+ *
+ * Description:
+ */
+union cvmx_trax_bist_status {
+	uint64_t u64;
+	struct cvmx_trax_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_3_63                : 61;
+	uint64_t tcf                          : 1;  /**< Bist Results for TCF memory
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t tdf1                         : 1;  /**< Bist Results for TDF memory 1
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_0_0                 : 1;
+#else
+	uint64_t reserved_0_0                 : 1;
+	uint64_t tdf1                         : 1;
+	uint64_t tcf                          : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_trax_bist_status_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_3_63                : 61;
+	uint64_t tcf                          : 1;  /**< Bist Results for TCF memory
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t tdf1                         : 1;  /**< Bist Results for TDF memory 1
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t tdf0                         : 1;  /**< Bist Results for TCF memory 0
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t tdf0                         : 1;
+	uint64_t tdf1                         : 1;
+	uint64_t tcf                          : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} cn31xx;
+	struct cvmx_trax_bist_status_cn31xx   cn38xx;
+	struct cvmx_trax_bist_status_cn31xx   cn38xxp2;
+	struct cvmx_trax_bist_status_cn31xx   cn52xx;
+	struct cvmx_trax_bist_status_cn31xx   cn52xxp1;
+	struct cvmx_trax_bist_status_cn31xx   cn56xx;
+	struct cvmx_trax_bist_status_cn31xx   cn56xxp1;
+	struct cvmx_trax_bist_status_cn31xx   cn58xx;
+	struct cvmx_trax_bist_status_cn31xx   cn58xxp1;
+	struct cvmx_trax_bist_status_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_1_63                : 63;
+	uint64_t tdf                          : 1;  /**< Bist Results for TCF memory
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t tdf                          : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} cn61xx;
+	struct cvmx_trax_bist_status_cn61xx   cn63xx;
+	struct cvmx_trax_bist_status_cn61xx   cn63xxp1;
+	struct cvmx_trax_bist_status_cn61xx   cn66xx;
+	struct cvmx_trax_bist_status_cn61xx   cn68xx;
+	struct cvmx_trax_bist_status_cn61xx   cn68xxp1;
+	struct cvmx_trax_bist_status_cn61xx   cnf71xx;
+};
+typedef union cvmx_trax_bist_status cvmx_trax_bist_status_t;
+
+/**
+ * cvmx_tra#_ctl
+ *
+ * TRA_CTL = Trace Buffer Control
+ *
+ * Description:
+ *
+ * Notes:
+ * It is illegal to change the values of WRAP, TRIG_CTL, IGNORE_O while tracing (i.e. when ENA=1).
+ * Note that the following fields are present only in chip revisions beginning with pass2: IGNORE_O
+ */
+union cvmx_trax_ctl {
+	uint64_t u64;
+	struct cvmx_trax_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_17_63               : 47;
+	uint64_t rdat_md                      : 1;  /**< TRA_READ_DAT mode bit
+                                                         If set, the TRA_READ_DAT reads will return the lower
+                                                         64 bits of the TRA entry and the upper bits must be
+                                                         read through TRA_READ_DAT_HI.  If not set the return
+                                                         value from TRA_READ_DAT accesses will switch between
+                                                         the lower bits and the upper bits of the TRA entry. */
+	uint64_t clkalways                    : 1;  /**< Conditional clock enable
+                                                         If set, the TRA clock is never disabled. */
+	uint64_t ignore_o                     : 1;  /**< Ignore overflow during wrap mode
+                                                         If set and wrapping mode is enabled, then tracing
+                                                         will not stop at the overflow condition.  Each
+                                                         write during an overflow will overwrite the
+                                                         oldest, unread entry and the read pointer is
+                                                         incremented by one entry.  This bit has no effect
+                                                         if WRAP=0. */
+	uint64_t mcd0_ena                     : 1;  /**< MCD0 enable
+                                                         If set and any PP sends the MCD0 signal, the
+                                                         tracing is disabled. */
+	uint64_t mcd0_thr                     : 1;  /**< MCD0_threshold
+                                                         At a fill threshold event, sends an MCD0
+                                                         wire pulse that can cause cores to enter debug
+                                                         mode, if enabled.  This MCD0 wire pulse will not
+                                                         occur while (TRA_INT_STATUS.MCD0_THR == 1). */
+	uint64_t mcd0_trg                     : 1;  /**< MCD0_trigger
+                                                         At an end trigger event, sends an MCD0
+                                                         wire pulse that can cause cores to enter debug
+                                                         mode, if enabled.  This MCD0 wire pulse will not
+                                                         occur while (TRA_INT_STATUS.MCD0_TRG == 1). */
+	uint64_t ciu_thr                      : 1;  /**< CIU_threshold
+                                                         When set during a fill threshold event,
+                                                         TRA_INT_STATUS[CIU_THR] is set, which can cause
+                                                         core interrupts, if enabled. */
+	uint64_t ciu_trg                      : 1;  /**< CIU_trigger
+                                                         When set during an end trigger event,
+                                                         TRA_INT_STATUS[CIU_TRG] is set, which can cause
+                                                         core interrupts, if enabled. */
+	uint64_t full_thr                     : 2;  /**< Full Threshhold
+                                                         0=none
+                                                         1=1/2 full
+                                                         2=3/4 full
+                                                         3=4/4 full */
+	uint64_t time_grn                     : 3;  /**< Timestamp granularity
+                                                         granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */
+	uint64_t trig_ctl                     : 2;  /**< Trigger Control
+                                                         Note: trigger events are written to the trace
+                                                         0=no triggers
+                                                         1=trigger0=start trigger, trigger1=stop trigger
+                                                         2=(trigger0 || trigger1)=start trigger
+                                                         3=(trigger0 || trigger1)=stop trigger */
+	uint64_t wrap                         : 1;  /**< Wrap mode
+                                                         When WRAP=0, the trace buffer will disable itself
+                                                         after having logged 1024 entries.  When WRAP=1,
+                                                         the trace buffer will never disable itself.
+                                                         In this case, tracing may or may not be
+                                                         temporarily suspended during the overflow
+                                                         condition (see IGNORE_O above).
+                                                         0=do not wrap
+                                                         1=wrap */
+	uint64_t ena                          : 1;  /**< Enable Trace
+                                                         Master enable.  Tracing only happens when ENA=1.
+                                                         When ENA changes from 0 to 1, the read and write
+                                                         pointers are reset to 0x00 to begin a new trace.
+                                                         The MCD0 event may set ENA=0 (see MCD0_ENA
+                                                         above).  When using triggers, tracing occurs only
+                                                         between start and stop triggers (including the
+                                                         triggers themselves).
+                                                         0=disable
+                                                         1=enable */
+#else
+	uint64_t ena                          : 1;
+	uint64_t wrap                         : 1;
+	uint64_t trig_ctl                     : 2;
+	uint64_t time_grn                     : 3;
+	uint64_t full_thr                     : 2;
+	uint64_t ciu_trg                      : 1;
+	uint64_t ciu_thr                      : 1;
+	uint64_t mcd0_trg                     : 1;
+	uint64_t mcd0_thr                     : 1;
+	uint64_t mcd0_ena                     : 1;
+	uint64_t ignore_o                     : 1;
+	uint64_t clkalways                    : 1;
+	uint64_t rdat_md                      : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_trax_ctl_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_15_63               : 49;
+	uint64_t ignore_o                     : 1;  /**< Ignore overflow during wrap mode
+                                                         If set and wrapping mode is enabled, then tracing
+                                                         will not stop at the overflow condition.  Each
+                                                         write during an overflow will overwrite the
+                                                         oldest, unread entry and the read pointer is
+                                                         incremented by one entry.  This bit has no effect
+                                                         if WRAP=0. */
+	uint64_t mcd0_ena                     : 1;  /**< MCD0 enable
+                                                         If set and any PP sends the MCD0 signal, the
+                                                         tracing is disabled. */
+	uint64_t mcd0_thr                     : 1;  /**< MCD0_threshold
+                                                         At a fill threshold event, sends an MCD0
+                                                         wire pulse that can cause cores to enter debug
+                                                         mode, if enabled.  This MCD0 wire pulse will not
+                                                         occur while (TRA(0..0)_INT_STATUS.MCD0_THR == 1). */
+	uint64_t mcd0_trg                     : 1;  /**< MCD0_trigger
+                                                         At an end trigger event, sends an MCD0
+                                                         wire pulse that can cause cores to enter debug
+                                                         mode, if enabled.  This MCD0 wire pulse will not
+                                                         occur while (TRA(0..0)_INT_STATUS.MCD0_TRG == 1). */
+	uint64_t ciu_thr                      : 1;  /**< CIU_threshold
+                                                         When set during a fill threshold event,
+                                                         TRA(0..0)_INT_STATUS[CIU_THR] is set, which can cause
+                                                         core interrupts, if enabled. */
+	uint64_t ciu_trg                      : 1;  /**< CIU_trigger
+                                                         When set during an end trigger event,
+                                                         TRA(0..0)_INT_STATUS[CIU_TRG] is set, which can cause
+                                                         core interrupts, if enabled. */
+	uint64_t full_thr                     : 2;  /**< Full Threshhold
+                                                         0=none
+                                                         1=1/2 full
+                                                         2=3/4 full
+                                                         3=4/4 full */
+	uint64_t time_grn                     : 3;  /**< Timestamp granularity
+                                                         granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */
+	uint64_t trig_ctl                     : 2;  /**< Trigger Control
+                                                         Note: trigger events are written to the trace
+                                                         0=no triggers
+                                                         1=trigger0=start trigger, trigger1=stop trigger
+                                                         2=(trigger0 || trigger1)=start trigger
+                                                         3=(trigger0 || trigger1)=stop trigger */
+	uint64_t wrap                         : 1;  /**< Wrap mode
+                                                         When WRAP=0, the trace buffer will disable itself
+                                                         after having logged 256 entries.  When WRAP=1,
+                                                         the trace buffer will never disable itself.
+                                                         In this case, tracing may or may not be
+                                                         temporarily suspended during the overflow
+                                                         condition (see IGNORE_O above).
+                                                         0=do not wrap
+                                                         1=wrap */
+	uint64_t ena                          : 1;  /**< Enable Trace
+                                                         Master enable.  Tracing only happens when ENA=1.
+                                                         When ENA changes from 0 to 1, the read and write
+                                                         pointers are reset to 0x00 to begin a new trace.
+                                                         The MCD0 event may set ENA=0 (see MCD0_ENA
+                                                         above).  When using triggers, tracing occurs only
+                                                         between start and stop triggers (including the
+                                                         triggers themselves).
+                                                         0=disable
+                                                         1=enable */
+#else
+	uint64_t ena                          : 1;
+	uint64_t wrap                         : 1;
+	uint64_t trig_ctl                     : 2;
+	uint64_t time_grn                     : 3;
+	uint64_t full_thr                     : 2;
+	uint64_t ciu_trg                      : 1;
+	uint64_t ciu_thr                      : 1;
+	uint64_t mcd0_trg                     : 1;
+	uint64_t mcd0_thr                     : 1;
+	uint64_t mcd0_ena                     : 1;
+	uint64_t ignore_o                     : 1;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} cn31xx;
+	struct cvmx_trax_ctl_cn31xx           cn38xx;
+	struct cvmx_trax_ctl_cn31xx           cn38xxp2;
+	struct cvmx_trax_ctl_cn31xx           cn52xx;
+	struct cvmx_trax_ctl_cn31xx           cn52xxp1;
+	struct cvmx_trax_ctl_cn31xx           cn56xx;
+	struct cvmx_trax_ctl_cn31xx           cn56xxp1;
+	struct cvmx_trax_ctl_cn31xx           cn58xx;
+	struct cvmx_trax_ctl_cn31xx           cn58xxp1;
+	struct cvmx_trax_ctl_s                cn61xx;
+	struct cvmx_trax_ctl_s                cn63xx;
+	struct cvmx_trax_ctl_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t clkalways                    : 1;  /**< Conditional clock enable
+                                                         If set, the TRA clock is never disabled. */
+	uint64_t ignore_o                     : 1;  /**< Ignore overflow during wrap mode
+                                                         If set and wrapping mode is enabled, then tracing
+                                                         will not stop at the overflow condition.  Each
+                                                         write during an overflow will overwrite the
+                                                         oldest, unread entry and the read pointer is
+                                                         incremented by one entry.  This bit has no effect
+                                                         if WRAP=0. */
+	uint64_t mcd0_ena                     : 1;  /**< MCD0 enable
+                                                         If set and any PP sends the MCD0 signal, the
+                                                         tracing is disabled. */
+	uint64_t mcd0_thr                     : 1;  /**< MCD0_threshold
+                                                         At a fill threshold event, sends an MCD0
+                                                         wire pulse that can cause cores to enter debug
+                                                         mode, if enabled.  This MCD0 wire pulse will not
+                                                         occur while (TRA_INT_STATUS.MCD0_THR == 1). */
+	uint64_t mcd0_trg                     : 1;  /**< MCD0_trigger
+                                                         At an end trigger event, sends an MCD0
+                                                         wire pulse that can cause cores to enter debug
+                                                         mode, if enabled.  This MCD0 wire pulse will not
+                                                         occur while (TRA_INT_STATUS.MCD0_TRG == 1). */
+	uint64_t ciu_thr                      : 1;  /**< CIU_threshold
+                                                         When set during a fill threshold event,
+                                                         TRA_INT_STATUS[CIU_THR] is set, which can cause
+                                                         core interrupts, if enabled. */
+	uint64_t ciu_trg                      : 1;  /**< CIU_trigger
+                                                         When set during an end trigger event,
+                                                         TRA_INT_STATUS[CIU_TRG] is set, which can cause
+                                                         core interrupts, if enabled. */
+	uint64_t full_thr                     : 2;  /**< Full Threshhold
+                                                         0=none
+                                                         1=1/2 full
+                                                         2=3/4 full
+                                                         3=4/4 full */
+	uint64_t time_grn                     : 3;  /**< Timestamp granularity
+                                                         granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */
+	uint64_t trig_ctl                     : 2;  /**< Trigger Control
+                                                         Note: trigger events are written to the trace
+                                                         0=no triggers
+                                                         1=trigger0=start trigger, trigger1=stop trigger
+                                                         2=(trigger0 || trigger1)=start trigger
+                                                         3=(trigger0 || trigger1)=stop trigger */
+	uint64_t wrap                         : 1;  /**< Wrap mode
+                                                         When WRAP=0, the trace buffer will disable itself
+                                                         after having logged 1024 entries.  When WRAP=1,
+                                                         the trace buffer will never disable itself.
+                                                         In this case, tracing may or may not be
+                                                         temporarily suspended during the overflow
+                                                         condition (see IGNORE_O above).
+                                                         0=do not wrap
+                                                         1=wrap */
+	uint64_t ena                          : 1;  /**< Enable Trace
+                                                         Master enable.  Tracing only happens when ENA=1.
+                                                         When ENA changes from 0 to 1, the read and write
+                                                         pointers are reset to 0x00 to begin a new trace.
+                                                         The MCD0 event may set ENA=0 (see MCD0_ENA
+                                                         above).  When using triggers, tracing occurs only
+                                                         between start and stop triggers (including the
+                                                         triggers themselves).
+                                                         0=disable
+                                                         1=enable */
+#else
+	uint64_t ena                          : 1;
+	uint64_t wrap                         : 1;
+	uint64_t trig_ctl                     : 2;
+	uint64_t time_grn                     : 3;
+	uint64_t full_thr                     : 2;
+	uint64_t ciu_trg                      : 1;
+	uint64_t ciu_thr                      : 1;
+	uint64_t mcd0_trg                     : 1;
+	uint64_t mcd0_thr                     : 1;
+	uint64_t mcd0_ena                     : 1;
+	uint64_t ignore_o                     : 1;
+	uint64_t clkalways                    : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn63xxp1;
+	struct cvmx_trax_ctl_s                cn66xx;
+	struct cvmx_trax_ctl_s                cn68xx;
+	struct cvmx_trax_ctl_s                cn68xxp1;
+	struct cvmx_trax_ctl_s                cnf71xx;
+};
+typedef union cvmx_trax_ctl cvmx_trax_ctl_t;
+
+/**
+ * cvmx_tra#_cycles_since
+ *
+ * TRA_CYCLES_SINCE = Trace Buffer Cycles Since Last Write, Read/Write pointers
+ *
+ * Description:
+ *
+ * Notes:
+ * This CSR is obsolete.  Use TRA_CYCLES_SINCE1 instead.
+ *
+ */
+union cvmx_trax_cycles_since {
+	uint64_t u64;
+	struct cvmx_trax_cycles_since_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t cycles                       : 48; /**< Cycles since the last entry was written */
+	uint64_t rptr                         : 8;  /**< Read pointer */
+	uint64_t wptr                         : 8;  /**< Write pointer */
+#else
+	uint64_t wptr                         : 8;
+	uint64_t rptr                         : 8;
+	uint64_t cycles                       : 48;
+#endif
+	} s;
+	struct cvmx_trax_cycles_since_s       cn31xx;
+	struct cvmx_trax_cycles_since_s       cn38xx;
+	struct cvmx_trax_cycles_since_s       cn38xxp2;
+	struct cvmx_trax_cycles_since_s       cn52xx;
+	struct cvmx_trax_cycles_since_s       cn52xxp1;
+	struct cvmx_trax_cycles_since_s       cn56xx;
+	struct cvmx_trax_cycles_since_s       cn56xxp1;
+	struct cvmx_trax_cycles_since_s       cn58xx;
+	struct cvmx_trax_cycles_since_s       cn58xxp1;
+	struct cvmx_trax_cycles_since_s       cn61xx;
+	struct cvmx_trax_cycles_since_s       cn63xx;
+	struct cvmx_trax_cycles_since_s       cn63xxp1;
+	struct cvmx_trax_cycles_since_s       cn66xx;
+	struct cvmx_trax_cycles_since_s       cn68xx;
+	struct cvmx_trax_cycles_since_s       cn68xxp1;
+	struct cvmx_trax_cycles_since_s       cnf71xx;
+};
+typedef union cvmx_trax_cycles_since cvmx_trax_cycles_since_t;
+
+/**
+ * cvmx_tra#_cycles_since1
+ *
+ * TRA_CYCLES_SINCE1 = Trace Buffer Cycles Since Last Write, Read/Write pointers
+ *
+ * Description:
+ */
+union cvmx_trax_cycles_since1 {
+	uint64_t u64;
+	struct cvmx_trax_cycles_since1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t cycles                       : 40; /**< Cycles since the last entry was written */
+	uint64_t reserved_22_23               : 2;
+	uint64_t rptr                         : 10; /**< Read pointer */
+	uint64_t reserved_10_11               : 2;
+	uint64_t wptr                         : 10; /**< Write pointer */
+#else
+	uint64_t wptr                         : 10;
+	uint64_t reserved_10_11               : 2;
+	uint64_t rptr                         : 10;
+	uint64_t reserved_22_23               : 2;
+	uint64_t cycles                       : 40;
+#endif
+	} s;
+	struct cvmx_trax_cycles_since1_s      cn52xx;
+	struct cvmx_trax_cycles_since1_s      cn52xxp1;
+	struct cvmx_trax_cycles_since1_s      cn56xx;
+	struct cvmx_trax_cycles_since1_s      cn56xxp1;
+	struct cvmx_trax_cycles_since1_s      cn58xx;
+	struct cvmx_trax_cycles_since1_s      cn58xxp1;
+	struct cvmx_trax_cycles_since1_s      cn61xx;
+	struct cvmx_trax_cycles_since1_s      cn63xx;
+	struct cvmx_trax_cycles_since1_s      cn63xxp1;
+	struct cvmx_trax_cycles_since1_s      cn66xx;
+	struct cvmx_trax_cycles_since1_s      cn68xx;
+	struct cvmx_trax_cycles_since1_s      cn68xxp1;
+	struct cvmx_trax_cycles_since1_s      cnf71xx;
+};
+typedef union cvmx_trax_cycles_since1 cvmx_trax_cycles_since1_t;
+
+/**
+ * cvmx_tra#_filt_adr_adr
+ *
+ * TRA_FILT_ADR_ADR = Trace Buffer Filter Address Address
+ *
+ * Description:
+ */
+union cvmx_trax_filt_adr_adr {
+	uint64_t u64;
+	struct cvmx_trax_filt_adr_adr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_38_63               : 26;
+	uint64_t adr                          : 38; /**< Unmasked Address
+                                                         The combination of TRA_FILT_ADR_ADR and
+                                                         TRA_FILT_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches */
+#else
+	uint64_t adr                          : 38;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_trax_filt_adr_adr_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_36_63               : 28;
+	uint64_t adr                          : 36; /**< Unmasked Address
+                                                         The combination of TRA(0..0)_FILT_ADR_ADR and
+                                                         TRA(0..0)_FILT_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches */
+#else
+	uint64_t adr                          : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn31xx;
+	struct cvmx_trax_filt_adr_adr_cn31xx  cn38xx;
+	struct cvmx_trax_filt_adr_adr_cn31xx  cn38xxp2;
+	struct cvmx_trax_filt_adr_adr_cn31xx  cn52xx;
+	struct cvmx_trax_filt_adr_adr_cn31xx  cn52xxp1;
+	struct cvmx_trax_filt_adr_adr_cn31xx  cn56xx;
+	struct cvmx_trax_filt_adr_adr_cn31xx  cn56xxp1;
+	struct cvmx_trax_filt_adr_adr_cn31xx  cn58xx;
+	struct cvmx_trax_filt_adr_adr_cn31xx  cn58xxp1;
+	struct cvmx_trax_filt_adr_adr_s       cn61xx;
+	struct cvmx_trax_filt_adr_adr_s       cn63xx;
+	struct cvmx_trax_filt_adr_adr_s       cn63xxp1;
+	struct cvmx_trax_filt_adr_adr_s       cn66xx;
+	struct cvmx_trax_filt_adr_adr_s       cn68xx;
+	struct cvmx_trax_filt_adr_adr_s       cn68xxp1;
+	struct cvmx_trax_filt_adr_adr_s       cnf71xx;
+};
+typedef union cvmx_trax_filt_adr_adr cvmx_trax_filt_adr_adr_t;
+
+/**
+ * cvmx_tra#_filt_adr_msk
+ *
+ * TRA_FILT_ADR_MSK = Trace Buffer Filter Address Mask
+ *
+ * Description:
+ */
+union cvmx_trax_filt_adr_msk {
+	uint64_t u64;
+	struct cvmx_trax_filt_adr_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_38_63               : 26;
+	uint64_t adr                          : 38; /**< Address Mask
+                                                         The combination of TRA_FILT_ADR_ADR and
+                                                         TRA_FILT_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches.  When a mask bit is not
+                                                         set, the corresponding address bits are assumed
+                                                         to match.  Also, note that IOBDMAs do not have
+                                                         proper addresses, so when TRA_FILT_CMD[IOBDMA]
+                                                         is set, TRA_FILT_ADR_MSK must be zero to
+                                                         guarantee that any IOBDMAs enter the trace. */
+#else
+	uint64_t adr                          : 38;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_trax_filt_adr_msk_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_36_63               : 28;
+	uint64_t adr                          : 36; /**< Address Mask
+                                                         The combination of TRA(0..0)_FILT_ADR_ADR and
+                                                         TRA(0..0)_FILT_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches.  When a mask bit is not
+                                                         set, the corresponding address bits are assumed
+                                                         to match.  Also, note that IOBDMAs do not have
+                                                         proper addresses, so when TRA(0..0)_FILT_CMD[IOBDMA]
+                                                         is set, TRA(0..0)_FILT_ADR_MSK must be zero to
+                                                         guarantee that any IOBDMAs enter the trace. */
+#else
+	uint64_t adr                          : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn31xx;
+	struct cvmx_trax_filt_adr_msk_cn31xx  cn38xx;
+	struct cvmx_trax_filt_adr_msk_cn31xx  cn38xxp2;
+	struct cvmx_trax_filt_adr_msk_cn31xx  cn52xx;
+	struct cvmx_trax_filt_adr_msk_cn31xx  cn52xxp1;
+	struct cvmx_trax_filt_adr_msk_cn31xx  cn56xx;
+	struct cvmx_trax_filt_adr_msk_cn31xx  cn56xxp1;
+	struct cvmx_trax_filt_adr_msk_cn31xx  cn58xx;
+	struct cvmx_trax_filt_adr_msk_cn31xx  cn58xxp1;
+	struct cvmx_trax_filt_adr_msk_s       cn61xx;
+	struct cvmx_trax_filt_adr_msk_s       cn63xx;
+	struct cvmx_trax_filt_adr_msk_s       cn63xxp1;
+	struct cvmx_trax_filt_adr_msk_s       cn66xx;
+	struct cvmx_trax_filt_adr_msk_s       cn68xx;
+	struct cvmx_trax_filt_adr_msk_s       cn68xxp1;
+	struct cvmx_trax_filt_adr_msk_s       cnf71xx;
+};
+typedef union cvmx_trax_filt_adr_msk cvmx_trax_filt_adr_msk_t;
+
+/**
+ * cvmx_tra#_filt_cmd
+ *
+ * TRA_FILT_CMD = Trace Buffer Filter Command Mask
+ *
+ * Description:
+ *
+ * Notes:
+ * Note that the trace buffer does not do proper IOBDMA address compares.  Thus, if IOBDMA is set, then
+ * the address compare must be disabled (i.e. TRA_FILT_ADR_MSK set to zero) to guarantee that IOBDMAs
+ * enter the trace.
+ */
+union cvmx_trax_filt_cmd {
+	uint64_t u64;
+	struct cvmx_trax_filt_cmd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t saa64                        : 1;  /**< Enable SAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t saa32                        : 1;  /**< Enable SAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_60_61               : 2;
+	uint64_t faa64                        : 1;  /**< Enable FAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t faa32                        : 1;  /**< Enable FAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_56_57               : 2;
+	uint64_t decr64                       : 1;  /**< Enable DECR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr32                       : 1;  /**< Enable DECR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr16                       : 1;  /**< Enable DECR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr8                        : 1;  /**< Enable DECR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr64                       : 1;  /**< Enable INCR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr32                       : 1;  /**< Enable INCR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr16                       : 1;  /**< Enable INCR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr8                        : 1;  /**< Enable INCR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr64                        : 1;  /**< Enable CLR64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr32                        : 1;  /**< Enable CLR32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr16                        : 1;  /**< Enable CLR16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr8                         : 1;  /**< Enable CLR8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t set64                        : 1;  /**< Enable SET64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set32                        : 1;  /**< Enable SET32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set16                        : 1;  /**< Enable SET16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set8                         : 1;  /**< Enable SET8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst64                      : 1;  /**< Enable IOBST64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst32                      : 1;  /**< Enable IOBST32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst16                      : 1;  /**< Enable IOBST16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst8                       : 1;  /**< Enable IOBST8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_32_35               : 4;
+	uint64_t lckl2                        : 1;  /**< Enable LCKL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbl2                         : 1;  /**< Enable WBL2    tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2                        : 1;  /**< Enable WBIL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t invl2                        : 1;  /**< Enable INVL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_27_27               : 1;
+	uint64_t stgl2i                       : 1;  /**< Enable STGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t ltgl2i                       : 1;  /**< Enable LTGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2i                       : 1;  /**< Enable WBIL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas64                        : 1;  /**< Enable FAS64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas32                        : 1;  /**< Enable FAS32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t sttil1                       : 1;  /**< Enable STTIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stfil1                       : 1;  /**< Enable STFIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_16_19               : 4;
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_0_13                : 14;
+#else
+	uint64_t reserved_0_13                : 14;
+	uint64_t iobst                        : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t reserved_16_19               : 4;
+	uint64_t stfil1                       : 1;
+	uint64_t sttil1                       : 1;
+	uint64_t fas32                        : 1;
+	uint64_t fas64                        : 1;
+	uint64_t wbil2i                       : 1;
+	uint64_t ltgl2i                       : 1;
+	uint64_t stgl2i                       : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t invl2                        : 1;
+	uint64_t wbil2                        : 1;
+	uint64_t wbl2                         : 1;
+	uint64_t lckl2                        : 1;
+	uint64_t reserved_32_35               : 4;
+	uint64_t iobst8                       : 1;
+	uint64_t iobst16                      : 1;
+	uint64_t iobst32                      : 1;
+	uint64_t iobst64                      : 1;
+	uint64_t set8                         : 1;
+	uint64_t set16                        : 1;
+	uint64_t set32                        : 1;
+	uint64_t set64                        : 1;
+	uint64_t clr8                         : 1;
+	uint64_t clr16                        : 1;
+	uint64_t clr32                        : 1;
+	uint64_t clr64                        : 1;
+	uint64_t incr8                        : 1;
+	uint64_t incr16                       : 1;
+	uint64_t incr32                       : 1;
+	uint64_t incr64                       : 1;
+	uint64_t decr8                        : 1;
+	uint64_t decr16                       : 1;
+	uint64_t decr32                       : 1;
+	uint64_t decr64                       : 1;
+	uint64_t reserved_56_57               : 2;
+	uint64_t faa32                        : 1;
+	uint64_t faa64                        : 1;
+	uint64_t reserved_60_61               : 2;
+	uint64_t saa32                        : 1;
+	uint64_t saa64                        : 1;
+#endif
+	} s;
+	struct cvmx_trax_filt_cmd_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stt                          : 1;  /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stp                          : 1;  /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stc                          : 1;  /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stf                          : 1;  /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+#else
+	uint64_t dwb                          : 1;
+	uint64_t pl2                          : 1;
+	uint64_t psl1                         : 1;
+	uint64_t ldd                          : 1;
+	uint64_t ldi                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t stf                          : 1;
+	uint64_t stc                          : 1;
+	uint64_t stp                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t iobld8                       : 1;
+	uint64_t iobld16                      : 1;
+	uint64_t iobld32                      : 1;
+	uint64_t iobld64                      : 1;
+	uint64_t iobst                        : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn31xx;
+	struct cvmx_trax_filt_cmd_cn31xx      cn38xx;
+	struct cvmx_trax_filt_cmd_cn31xx      cn38xxp2;
+	struct cvmx_trax_filt_cmd_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_17_63               : 47;
+	uint64_t saa                          : 1;  /**< Enable SAA     tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stt                          : 1;  /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stp                          : 1;  /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stc                          : 1;  /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stf                          : 1;  /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+#else
+	uint64_t dwb                          : 1;
+	uint64_t pl2                          : 1;
+	uint64_t psl1                         : 1;
+	uint64_t ldd                          : 1;
+	uint64_t ldi                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t stf                          : 1;
+	uint64_t stc                          : 1;
+	uint64_t stp                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t iobld8                       : 1;
+	uint64_t iobld16                      : 1;
+	uint64_t iobld32                      : 1;
+	uint64_t iobld64                      : 1;
+	uint64_t iobst                        : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t saa                          : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn52xx;
+	struct cvmx_trax_filt_cmd_cn52xx      cn52xxp1;
+	struct cvmx_trax_filt_cmd_cn52xx      cn56xx;
+	struct cvmx_trax_filt_cmd_cn52xx      cn56xxp1;
+	struct cvmx_trax_filt_cmd_cn52xx      cn58xx;
+	struct cvmx_trax_filt_cmd_cn52xx      cn58xxp1;
+	struct cvmx_trax_filt_cmd_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t saa64                        : 1;  /**< Enable SAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t saa32                        : 1;  /**< Enable SAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_60_61               : 2;
+	uint64_t faa64                        : 1;  /**< Enable FAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t faa32                        : 1;  /**< Enable FAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_56_57               : 2;
+	uint64_t decr64                       : 1;  /**< Enable DECR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr32                       : 1;  /**< Enable DECR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr16                       : 1;  /**< Enable DECR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr8                        : 1;  /**< Enable DECR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr64                       : 1;  /**< Enable INCR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr32                       : 1;  /**< Enable INCR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr16                       : 1;  /**< Enable INCR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr8                        : 1;  /**< Enable INCR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr64                        : 1;  /**< Enable CLR64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr32                        : 1;  /**< Enable CLR32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr16                        : 1;  /**< Enable CLR16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr8                         : 1;  /**< Enable CLR8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t set64                        : 1;  /**< Enable SET64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set32                        : 1;  /**< Enable SET32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set16                        : 1;  /**< Enable SET16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set8                         : 1;  /**< Enable SET8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst64                      : 1;  /**< Enable IOBST64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst32                      : 1;  /**< Enable IOBST32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst16                      : 1;  /**< Enable IOBST16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst8                       : 1;  /**< Enable IOBST8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t lckl2                        : 1;  /**< Enable LCKL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbl2                         : 1;  /**< Enable WBL2    tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2                        : 1;  /**< Enable WBIL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t invl2                        : 1;  /**< Enable INVL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_27_27               : 1;
+	uint64_t stgl2i                       : 1;  /**< Enable STGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t ltgl2i                       : 1;  /**< Enable LTGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2i                       : 1;  /**< Enable WBIL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas64                        : 1;  /**< Enable FAS64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas32                        : 1;  /**< Enable FAS32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t sttil1                       : 1;  /**< Enable STTIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stfil1                       : 1;  /**< Enable STFIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stc                          : 1;  /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stp                          : 1;  /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stt                          : 1;  /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stf                          : 1;  /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_10_14               : 5;
+	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+	uint64_t rpl2                         : 1;  /**< Enable RPL2    tracing
+                                                         0=disable, 1=enable */
+	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t nop                          : 1;  /**< Enable NOP     tracing
+                                                         0=disable, 1=enable */
+#else
+	uint64_t nop                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t ldi                          : 1;
+	uint64_t pl2                          : 1;
+	uint64_t rpl2                         : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ldd                          : 1;
+	uint64_t psl1                         : 1;
+	uint64_t reserved_10_14               : 5;
+	uint64_t iobdma                       : 1;
+	uint64_t stf                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t stp                          : 1;
+	uint64_t stc                          : 1;
+	uint64_t stfil1                       : 1;
+	uint64_t sttil1                       : 1;
+	uint64_t fas32                        : 1;
+	uint64_t fas64                        : 1;
+	uint64_t wbil2i                       : 1;
+	uint64_t ltgl2i                       : 1;
+	uint64_t stgl2i                       : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t invl2                        : 1;
+	uint64_t wbil2                        : 1;
+	uint64_t wbl2                         : 1;
+	uint64_t lckl2                        : 1;
+	uint64_t iobld8                       : 1;
+	uint64_t iobld16                      : 1;
+	uint64_t iobld32                      : 1;
+	uint64_t iobld64                      : 1;
+	uint64_t iobst8                       : 1;
+	uint64_t iobst16                      : 1;
+	uint64_t iobst32                      : 1;
+	uint64_t iobst64                      : 1;
+	uint64_t set8                         : 1;
+	uint64_t set16                        : 1;
+	uint64_t set32                        : 1;
+	uint64_t set64                        : 1;
+	uint64_t clr8                         : 1;
+	uint64_t clr16                        : 1;
+	uint64_t clr32                        : 1;
+	uint64_t clr64                        : 1;
+	uint64_t incr8                        : 1;
+	uint64_t incr16                       : 1;
+	uint64_t incr32                       : 1;
+	uint64_t incr64                       : 1;
+	uint64_t decr8                        : 1;
+	uint64_t decr16                       : 1;
+	uint64_t decr32                       : 1;
+	uint64_t decr64                       : 1;
+	uint64_t reserved_56_57               : 2;
+	uint64_t faa32                        : 1;
+	uint64_t faa64                        : 1;
+	uint64_t reserved_60_61               : 2;
+	uint64_t saa32                        : 1;
+	uint64_t saa64                        : 1;
+#endif
+	} cn61xx;
+	struct cvmx_trax_filt_cmd_cn61xx      cn63xx;
+	struct cvmx_trax_filt_cmd_cn61xx      cn63xxp1;
+	struct cvmx_trax_filt_cmd_cn61xx      cn66xx;
+	struct cvmx_trax_filt_cmd_cn61xx      cn68xx;
+	struct cvmx_trax_filt_cmd_cn61xx      cn68xxp1;
+	struct cvmx_trax_filt_cmd_cn61xx      cnf71xx;
+};
+typedef union cvmx_trax_filt_cmd cvmx_trax_filt_cmd_t;
+
+/**
+ * cvmx_tra#_filt_did
+ *
+ * TRA_FILT_DID = Trace Buffer Filter DestinationId Mask
+ *
+ * Description:
+ */
+union cvmx_trax_filt_did {
+	uint64_t u64;
+	struct cvmx_trax_filt_did_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_13_63               : 51;
+	uint64_t pow                          : 1;  /**< Enable tracing of requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+	uint64_t reserved_9_11                : 3;
+	uint64_t rng                          : 1;  /**< Enable tracing of requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+	uint64_t zip                          : 1;  /**< Enable tracing of requests to ZIP
+                                                         (doorbell stores are legal) */
+	uint64_t dfa                          : 1;  /**< Enable tracing of requests to DFA
+                                                         (CSR's and operations are legal) */
+	uint64_t fpa                          : 1;  /**< Enable tracing of requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+	uint64_t key                          : 1;  /**< Enable tracing of requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t illegal3                     : 2;  /**< Illegal destinations */
+	uint64_t mio                          : 1;  /**< Enable tracing of MIO accesses
+                                                         (CIU and GPIO CSR's, boot bus accesses) */
+#else
+	uint64_t mio                          : 1;
+	uint64_t illegal3                     : 2;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rng                          : 1;
+	uint64_t reserved_9_11                : 3;
+	uint64_t pow                          : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_trax_filt_did_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t illegal                      : 19; /**< Illegal destinations */
+	uint64_t pow                          : 1;  /**< Enable tracing of requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+	uint64_t illegal2                     : 3;  /**< Illegal destinations */
+	uint64_t rng                          : 1;  /**< Enable tracing of requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+	uint64_t zip                          : 1;  /**< Enable tracing of requests to ZIP
+                                                         (doorbell stores are legal) */
+	uint64_t dfa                          : 1;  /**< Enable tracing of requests to DFA
+                                                         (CSR's and operations are legal) */
+	uint64_t fpa                          : 1;  /**< Enable tracing of requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+	uint64_t key                          : 1;  /**< Enable tracing of requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+	uint64_t pci                          : 1;  /**< Enable tracing of requests to PCI and RSL-type
+                                                         CSR's (RSL CSR's, PCI bus operations, PCI
+                                                         CSR's) */
+	uint64_t illegal3                     : 2;  /**< Illegal destinations */
+	uint64_t mio                          : 1;  /**< Enable tracing of CIU and GPIO CSR's */
+#else
+	uint64_t mio                          : 1;
+	uint64_t illegal3                     : 2;
+	uint64_t pci                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rng                          : 1;
+	uint64_t illegal2                     : 3;
+	uint64_t pow                          : 1;
+	uint64_t illegal                      : 19;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn31xx;
+	struct cvmx_trax_filt_did_cn31xx      cn38xx;
+	struct cvmx_trax_filt_did_cn31xx      cn38xxp2;
+	struct cvmx_trax_filt_did_cn31xx      cn52xx;
+	struct cvmx_trax_filt_did_cn31xx      cn52xxp1;
+	struct cvmx_trax_filt_did_cn31xx      cn56xx;
+	struct cvmx_trax_filt_did_cn31xx      cn56xxp1;
+	struct cvmx_trax_filt_did_cn31xx      cn58xx;
+	struct cvmx_trax_filt_did_cn31xx      cn58xxp1;
+	struct cvmx_trax_filt_did_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t illegal5                     : 1;  /**< Illegal destinations */
+	uint64_t fau                          : 1;  /**< Enable tracing of FAU accesses */
+	uint64_t illegal4                     : 2;  /**< Illegal destinations */
+	uint64_t dpi                          : 1;  /**< Enable tracing of DPI accesses
+                                                         (DPI NCB CSRs) */
+	uint64_t illegal                      : 12; /**< Illegal destinations */
+	uint64_t rad                          : 1;  /**< Enable tracing of RAD accesses
+                                                         (doorbells) */
+	uint64_t usb0                         : 1;  /**< Enable tracing of USB0 accesses
+                                                         (UAHC0 EHCI and OHCI NCB CSRs) */
+	uint64_t pow                          : 1;  /**< Enable tracing of requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+	uint64_t illegal2                     : 1;  /**< Illegal destination */
+	uint64_t pko                          : 1;  /**< Enable tracing of PKO accesses
+                                                         (doorbells) */
+	uint64_t ipd                          : 1;  /**< Enable tracing of IPD CSR accesses
+                                                         (IPD CSRs) */
+	uint64_t rng                          : 1;  /**< Enable tracing of requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+	uint64_t zip                          : 1;  /**< Enable tracing of requests to ZIP
+                                                         (doorbell stores are legal) */
+	uint64_t dfa                          : 1;  /**< Enable tracing of requests to DFA
+                                                         (CSR's and operations are legal) */
+	uint64_t fpa                          : 1;  /**< Enable tracing of requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+	uint64_t key                          : 1;  /**< Enable tracing of requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+	uint64_t sli                          : 1;  /**< Enable tracing of requests to SLI and RSL-type
+                                                         CSR's (RSL CSR's, PCI/sRIO bus operations, SLI
+                                                         CSR's) */
+	uint64_t illegal3                     : 2;  /**< Illegal destinations */
+	uint64_t mio                          : 1;  /**< Enable tracing of MIO accesses
+                                                         (CIU and GPIO CSR's, boot bus accesses) */
+#else
+	uint64_t mio                          : 1;
+	uint64_t illegal3                     : 2;
+	uint64_t sli                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rng                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t illegal2                     : 1;
+	uint64_t pow                          : 1;
+	uint64_t usb0                         : 1;
+	uint64_t rad                          : 1;
+	uint64_t illegal                      : 12;
+	uint64_t dpi                          : 1;
+	uint64_t illegal4                     : 2;
+	uint64_t fau                          : 1;
+	uint64_t illegal5                     : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn61xx;
+	struct cvmx_trax_filt_did_cn61xx      cn63xx;
+	struct cvmx_trax_filt_did_cn61xx      cn63xxp1;
+	struct cvmx_trax_filt_did_cn61xx      cn66xx;
+	struct cvmx_trax_filt_did_cn61xx      cn68xx;
+	struct cvmx_trax_filt_did_cn61xx      cn68xxp1;
+	struct cvmx_trax_filt_did_cn61xx      cnf71xx;
+};
+typedef union cvmx_trax_filt_did cvmx_trax_filt_did_t;
+
+/**
+ * cvmx_tra#_filt_sid
+ *
+ * TRA_FILT_SID = Trace Buffer Filter SourceId Mask
+ *
+ * Description:
+ */
+union cvmx_trax_filt_sid {
+	uint64_t u64;
+	struct cvmx_trax_filt_sid_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable tracing of requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable tracing of requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable tracing of read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable tracing of write requests from PIP/IPD */
+	uint64_t pp                           : 16; /**< Enable tracing from PP[N] with matching SourceID
+                                                         0=disable, 1=enable per bit N where 0<=N<=3 */
+#else
+	uint64_t pp                           : 16;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_trax_filt_sid_s           cn31xx;
+	struct cvmx_trax_filt_sid_s           cn38xx;
+	struct cvmx_trax_filt_sid_s           cn38xxp2;
+	struct cvmx_trax_filt_sid_s           cn52xx;
+	struct cvmx_trax_filt_sid_s           cn52xxp1;
+	struct cvmx_trax_filt_sid_s           cn56xx;
+	struct cvmx_trax_filt_sid_s           cn56xxp1;
+	struct cvmx_trax_filt_sid_s           cn58xx;
+	struct cvmx_trax_filt_sid_s           cn58xxp1;
+	struct cvmx_trax_filt_sid_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable tracing of requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable tracing of requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable tracing of read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable tracing of write requests from PIP/IPD */
+	uint64_t reserved_4_15                : 12;
+	uint64_t pp                           : 4;  /**< Enable tracing from PP[N] with matching SourceID
+                                                         0=disable, 1=enable per bit N where 0<=N<=3 */
+#else
+	uint64_t pp                           : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn61xx;
+	struct cvmx_trax_filt_sid_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable tracing of requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable tracing of requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable tracing of read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable tracing of write requests from PIP/IPD */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pp                           : 8;  /**< Enable tracing from PP[N] with matching SourceID
+                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
+#else
+	uint64_t pp                           : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn63xx;
+	struct cvmx_trax_filt_sid_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable tracing of requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable tracing of requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable tracing of read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable tracing of write requests from PIP/IPD */
+	uint64_t reserved_6_15                : 10;
+	uint64_t pp                           : 6;  /**< Enable tracing from PP[N] with matching SourceID
+                                                         0=disable, 1=enable per bit N where 0<=N<=5 */
+#else
+	uint64_t pp                           : 6;
+	uint64_t reserved_6_15                : 10;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn63xxp1;
+	struct cvmx_trax_filt_sid_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable tracing of requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable tracing of requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable tracing of read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable tracing of write requests from PIP/IPD */
+	uint64_t reserved_10_15               : 6;
+	uint64_t pp                           : 10; /**< Enable tracing from PP[N] with matching SourceID
+                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
+#else
+	uint64_t pp                           : 10;
+	uint64_t reserved_10_15               : 6;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn66xx;
+	struct cvmx_trax_filt_sid_cn63xx      cn68xx;
+	struct cvmx_trax_filt_sid_cn63xx      cn68xxp1;
+	struct cvmx_trax_filt_sid_cn61xx      cnf71xx;
+};
+typedef union cvmx_trax_filt_sid cvmx_trax_filt_sid_t;
+
+/**
+ * cvmx_tra#_int_status
+ *
+ * TRA_INT_STATUS = Trace Buffer Interrupt Status
+ *
+ * Description:
+ *
+ * Notes:
+ * During a CSR write to this register, the write data is used as a mask to clear the selected status
+ * bits (status'[3:0] = status[3:0] & ~write_data[3:0]).
+ */
+union cvmx_trax_int_status {
+	uint64_t u64;
+	struct cvmx_trax_int_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t mcd0_thr                     : 1;  /**< MCD0 full threshold interrupt status
+                                                         0=trace buffer did not generate MCD0 wire pulse
+                                                         1=trace buffer did     generate MCD0 wire pulse
+                                                           and prevents additional MCD0_THR MCD0 wire pulses */
+	uint64_t mcd0_trg                     : 1;  /**< MCD0 end trigger interrupt status
+                                                         0=trace buffer did not generate interrupt
+                                                         1=trace buffer did     generate interrupt
+                                                           and prevents additional MCD0_TRG MCD0 wire pulses */
+	uint64_t ciu_thr                      : 1;  /**< CIU full threshold interrupt status
+                                                         0=trace buffer did not generate interrupt
+                                                         1=trace buffer did     generate interrupt */
+	uint64_t ciu_trg                      : 1;  /**< CIU end trigger interrupt status
+                                                         0=trace buffer did not generate interrupt
+                                                         1=trace buffer did     generate interrupt */
+#else
+	uint64_t ciu_trg                      : 1;
+	uint64_t ciu_thr                      : 1;
+	uint64_t mcd0_trg                     : 1;
+	uint64_t mcd0_thr                     : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_trax_int_status_s         cn31xx;
+	struct cvmx_trax_int_status_s         cn38xx;
+	struct cvmx_trax_int_status_s         cn38xxp2;
+	struct cvmx_trax_int_status_s         cn52xx;
+	struct cvmx_trax_int_status_s         cn52xxp1;
+	struct cvmx_trax_int_status_s         cn56xx;
+	struct cvmx_trax_int_status_s         cn56xxp1;
+	struct cvmx_trax_int_status_s         cn58xx;
+	struct cvmx_trax_int_status_s         cn58xxp1;
+	struct cvmx_trax_int_status_s         cn61xx;
+	struct cvmx_trax_int_status_s         cn63xx;
+	struct cvmx_trax_int_status_s         cn63xxp1;
+	struct cvmx_trax_int_status_s         cn66xx;
+	struct cvmx_trax_int_status_s         cn68xx;
+	struct cvmx_trax_int_status_s         cn68xxp1;
+	struct cvmx_trax_int_status_s         cnf71xx;
+};
+typedef union cvmx_trax_int_status cvmx_trax_int_status_t;
+
+/**
+ * cvmx_tra#_read_dat
+ *
+ * TRA_READ_DAT = Trace Buffer Read Data
+ *
+ * Description:
+ *
+ * Notes:
+ * This CSR is a memory of 1024 entries.  When the trace was enabled, the read pointer was set to entry
+ * 0 by hardware.  Each read to this address increments the read pointer.
+ */
+union cvmx_trax_read_dat {
+	uint64_t u64;
+	struct cvmx_trax_read_dat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t data                         : 64; /**< Trace buffer data for current entry
+                                                         if TRA_CTL[16]== 1; returns lower 64 bits of entry
+                                                         else two access are necessary to get all of 69bits
+                                                         first access of a pair is the lower 64 bits and
+                                                         second access is the upper 5 bits. */
+#else
+	uint64_t data                         : 64;
+#endif
+	} s;
+	struct cvmx_trax_read_dat_s           cn31xx;
+	struct cvmx_trax_read_dat_s           cn38xx;
+	struct cvmx_trax_read_dat_s           cn38xxp2;
+	struct cvmx_trax_read_dat_s           cn52xx;
+	struct cvmx_trax_read_dat_s           cn52xxp1;
+	struct cvmx_trax_read_dat_s           cn56xx;
+	struct cvmx_trax_read_dat_s           cn56xxp1;
+	struct cvmx_trax_read_dat_s           cn58xx;
+	struct cvmx_trax_read_dat_s           cn58xxp1;
+	struct cvmx_trax_read_dat_s           cn61xx;
+	struct cvmx_trax_read_dat_s           cn63xx;
+	struct cvmx_trax_read_dat_s           cn63xxp1;
+	struct cvmx_trax_read_dat_s           cn66xx;
+	struct cvmx_trax_read_dat_s           cn68xx;
+	struct cvmx_trax_read_dat_s           cn68xxp1;
+	struct cvmx_trax_read_dat_s           cnf71xx;
+};
+typedef union cvmx_trax_read_dat cvmx_trax_read_dat_t;
+
+/**
+ * cvmx_tra#_read_dat_hi
+ *
+ * TRA_READ_DAT_HI = Trace Buffer Read Data- upper 5 bits do not use if TRA_CTL[16]==0
+ *
+ * Description:
+ *
+ * Notes:
+ * This CSR is a memory of 1024 entries. Reads to this address do not increment the read pointer.  The
+ * 5 bits read are the upper 5 bits of the TRA entry last read by the TRA_READ_DAT reg.
+ */
+union cvmx_trax_read_dat_hi {
+	uint64_t u64;
+	struct cvmx_trax_read_dat_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_5_63                : 59;
+	uint64_t data                         : 5;  /**< Trace buffer data[68:64] for current entry */
+#else
+	uint64_t data                         : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_trax_read_dat_hi_s        cn61xx;
+	struct cvmx_trax_read_dat_hi_s        cn63xx;
+	struct cvmx_trax_read_dat_hi_s        cn66xx;
+	struct cvmx_trax_read_dat_hi_s        cn68xx;
+	struct cvmx_trax_read_dat_hi_s        cn68xxp1;
+	struct cvmx_trax_read_dat_hi_s        cnf71xx;
+};
+typedef union cvmx_trax_read_dat_hi cvmx_trax_read_dat_hi_t;
+
+/**
+ * cvmx_tra#_trig0_adr_adr
+ *
+ * TRA_TRIG0_ADR_ADR = Trace Buffer Filter Address Address
+ *
+ * Description:
+ */
+union cvmx_trax_trig0_adr_adr {
+	uint64_t u64;
+	struct cvmx_trax_trig0_adr_adr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_38_63               : 26;
+	uint64_t adr                          : 38; /**< Unmasked Address
+                                                         The combination of TRA_TRIG0_ADR_ADR and
+                                                         TRA_TRIG0_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches */
+#else
+	uint64_t adr                          : 38;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_trax_trig0_adr_adr_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_36_63               : 28;
+	uint64_t adr                          : 36; /**< Unmasked Address
+                                                         The combination of TRA(0..0)_TRIG0_ADR_ADR and
+                                                         TRA(0..0)_TRIG0_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches */
+#else
+	uint64_t adr                          : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn31xx;
+	struct cvmx_trax_trig0_adr_adr_cn31xx cn38xx;
+	struct cvmx_trax_trig0_adr_adr_cn31xx cn38xxp2;
+	struct cvmx_trax_trig0_adr_adr_cn31xx cn52xx;
+	struct cvmx_trax_trig0_adr_adr_cn31xx cn52xxp1;
+	struct cvmx_trax_trig0_adr_adr_cn31xx cn56xx;
+	struct cvmx_trax_trig0_adr_adr_cn31xx cn56xxp1;
+	struct cvmx_trax_trig0_adr_adr_cn31xx cn58xx;
+	struct cvmx_trax_trig0_adr_adr_cn31xx cn58xxp1;
+	struct cvmx_trax_trig0_adr_adr_s      cn61xx;
+	struct cvmx_trax_trig0_adr_adr_s      cn63xx;
+	struct cvmx_trax_trig0_adr_adr_s      cn63xxp1;
+	struct cvmx_trax_trig0_adr_adr_s      cn66xx;
+	struct cvmx_trax_trig0_adr_adr_s      cn68xx;
+	struct cvmx_trax_trig0_adr_adr_s      cn68xxp1;
+	struct cvmx_trax_trig0_adr_adr_s      cnf71xx;
+};
+typedef union cvmx_trax_trig0_adr_adr cvmx_trax_trig0_adr_adr_t;
+
+/**
+ * cvmx_tra#_trig0_adr_msk
+ *
+ * TRA_TRIG0_ADR_MSK = Trace Buffer Filter Address Mask
+ *
+ * Description:
+ */
+union cvmx_trax_trig0_adr_msk {
+	uint64_t u64;
+	struct cvmx_trax_trig0_adr_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_38_63               : 26;
+	uint64_t adr                          : 38; /**< Address Mask
+                                                         The combination of TRA_TRIG0_ADR_ADR and
+                                                         TRA_TRIG0_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches.  When a mask bit is not
+                                                         set, the corresponding address bits are assumed
+                                                         to match.  Also, note that IOBDMAs do not have
+                                                         proper addresses, so when TRA_TRIG0_CMD[IOBDMA]
+                                                         is set, TRA_FILT_TRIG0_MSK must be zero to
+                                                         guarantee that any IOBDMAs are recognized as
+                                                         triggers. */
+#else
+	uint64_t adr                          : 38;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_trax_trig0_adr_msk_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_36_63               : 28;
+	uint64_t adr                          : 36; /**< Address Mask
+                                                         The combination of TRA(0..0)_TRIG0_ADR_ADR and
+                                                         TRA(0..0)_TRIG0_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches.  When a mask bit is not
+                                                         set, the corresponding address bits are assumed
+                                                         to match.  Also, note that IOBDMAs do not have
+                                                         proper addresses, so when TRA(0..0)_TRIG0_CMD[IOBDMA]
+                                                         is set, TRA(0..0)_FILT_TRIG0_MSK must be zero to
+                                                         guarantee that any IOBDMAs are recognized as
+                                                         triggers. */
+#else
+	uint64_t adr                          : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn31xx;
+	struct cvmx_trax_trig0_adr_msk_cn31xx cn38xx;
+	struct cvmx_trax_trig0_adr_msk_cn31xx cn38xxp2;
+	struct cvmx_trax_trig0_adr_msk_cn31xx cn52xx;
+	struct cvmx_trax_trig0_adr_msk_cn31xx cn52xxp1;
+	struct cvmx_trax_trig0_adr_msk_cn31xx cn56xx;
+	struct cvmx_trax_trig0_adr_msk_cn31xx cn56xxp1;
+	struct cvmx_trax_trig0_adr_msk_cn31xx cn58xx;
+	struct cvmx_trax_trig0_adr_msk_cn31xx cn58xxp1;
+	struct cvmx_trax_trig0_adr_msk_s      cn61xx;
+	struct cvmx_trax_trig0_adr_msk_s      cn63xx;
+	struct cvmx_trax_trig0_adr_msk_s      cn63xxp1;
+	struct cvmx_trax_trig0_adr_msk_s      cn66xx;
+	struct cvmx_trax_trig0_adr_msk_s      cn68xx;
+	struct cvmx_trax_trig0_adr_msk_s      cn68xxp1;
+	struct cvmx_trax_trig0_adr_msk_s      cnf71xx;
+};
+typedef union cvmx_trax_trig0_adr_msk cvmx_trax_trig0_adr_msk_t;
+
+/**
+ * cvmx_tra#_trig0_cmd
+ *
+ * TRA_TRIG0_CMD = Trace Buffer Filter Command Mask
+ *
+ * Description:
+ *
+ * Notes:
+ * Note that the trace buffer does not do proper IOBDMA address compares.  Thus, if IOBDMA is set, then
+ * the address compare must be disabled (i.e. TRA_TRIG0_ADR_MSK set to zero) to guarantee that IOBDMAs
+ * are recognized as triggers.
+ */
+union cvmx_trax_trig0_cmd {
+	uint64_t u64;
+	struct cvmx_trax_trig0_cmd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t saa64                        : 1;  /**< Enable SAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t saa32                        : 1;  /**< Enable SAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_60_61               : 2;
+	uint64_t faa64                        : 1;  /**< Enable FAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t faa32                        : 1;  /**< Enable FAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_56_57               : 2;
+	uint64_t decr64                       : 1;  /**< Enable DECR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr32                       : 1;  /**< Enable DECR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr16                       : 1;  /**< Enable DECR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr8                        : 1;  /**< Enable DECR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr64                       : 1;  /**< Enable INCR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr32                       : 1;  /**< Enable INCR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr16                       : 1;  /**< Enable INCR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr8                        : 1;  /**< Enable INCR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr64                        : 1;  /**< Enable CLR64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr32                        : 1;  /**< Enable CLR32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr16                        : 1;  /**< Enable CLR16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr8                         : 1;  /**< Enable CLR8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t set64                        : 1;  /**< Enable SET64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set32                        : 1;  /**< Enable SET32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set16                        : 1;  /**< Enable SET16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set8                         : 1;  /**< Enable SET8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst64                      : 1;  /**< Enable IOBST64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst32                      : 1;  /**< Enable IOBST32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst16                      : 1;  /**< Enable IOBST16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst8                       : 1;  /**< Enable IOBST8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_32_35               : 4;
+	uint64_t lckl2                        : 1;  /**< Enable LCKL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbl2                         : 1;  /**< Enable WBL2    tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2                        : 1;  /**< Enable WBIL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t invl2                        : 1;  /**< Enable INVL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_27_27               : 1;
+	uint64_t stgl2i                       : 1;  /**< Enable STGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t ltgl2i                       : 1;  /**< Enable LTGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2i                       : 1;  /**< Enable WBIL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas64                        : 1;  /**< Enable FAS64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas32                        : 1;  /**< Enable FAS32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t sttil1                       : 1;  /**< Enable STTIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stfil1                       : 1;  /**< Enable STFIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_16_19               : 4;
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_0_13                : 14;
+#else
+	uint64_t reserved_0_13                : 14;
+	uint64_t iobst                        : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t reserved_16_19               : 4;
+	uint64_t stfil1                       : 1;
+	uint64_t sttil1                       : 1;
+	uint64_t fas32                        : 1;
+	uint64_t fas64                        : 1;
+	uint64_t wbil2i                       : 1;
+	uint64_t ltgl2i                       : 1;
+	uint64_t stgl2i                       : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t invl2                        : 1;
+	uint64_t wbil2                        : 1;
+	uint64_t wbl2                         : 1;
+	uint64_t lckl2                        : 1;
+	uint64_t reserved_32_35               : 4;
+	uint64_t iobst8                       : 1;
+	uint64_t iobst16                      : 1;
+	uint64_t iobst32                      : 1;
+	uint64_t iobst64                      : 1;
+	uint64_t set8                         : 1;
+	uint64_t set16                        : 1;
+	uint64_t set32                        : 1;
+	uint64_t set64                        : 1;
+	uint64_t clr8                         : 1;
+	uint64_t clr16                        : 1;
+	uint64_t clr32                        : 1;
+	uint64_t clr64                        : 1;
+	uint64_t incr8                        : 1;
+	uint64_t incr16                       : 1;
+	uint64_t incr32                       : 1;
+	uint64_t incr64                       : 1;
+	uint64_t decr8                        : 1;
+	uint64_t decr16                       : 1;
+	uint64_t decr32                       : 1;
+	uint64_t decr64                       : 1;
+	uint64_t reserved_56_57               : 2;
+	uint64_t faa32                        : 1;
+	uint64_t faa64                        : 1;
+	uint64_t reserved_60_61               : 2;
+	uint64_t saa32                        : 1;
+	uint64_t saa64                        : 1;
+#endif
+	} s;
+	struct cvmx_trax_trig0_cmd_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stt                          : 1;  /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stp                          : 1;  /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stc                          : 1;  /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stf                          : 1;  /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+#else
+	uint64_t dwb                          : 1;
+	uint64_t pl2                          : 1;
+	uint64_t psl1                         : 1;
+	uint64_t ldd                          : 1;
+	uint64_t ldi                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t stf                          : 1;
+	uint64_t stc                          : 1;
+	uint64_t stp                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t iobld8                       : 1;
+	uint64_t iobld16                      : 1;
+	uint64_t iobld32                      : 1;
+	uint64_t iobld64                      : 1;
+	uint64_t iobst                        : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn31xx;
+	struct cvmx_trax_trig0_cmd_cn31xx     cn38xx;
+	struct cvmx_trax_trig0_cmd_cn31xx     cn38xxp2;
+	struct cvmx_trax_trig0_cmd_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_17_63               : 47;
+	uint64_t saa                          : 1;  /**< Enable SAA     tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stt                          : 1;  /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stp                          : 1;  /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stc                          : 1;  /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stf                          : 1;  /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+#else
+	uint64_t dwb                          : 1;
+	uint64_t pl2                          : 1;
+	uint64_t psl1                         : 1;
+	uint64_t ldd                          : 1;
+	uint64_t ldi                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t stf                          : 1;
+	uint64_t stc                          : 1;
+	uint64_t stp                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t iobld8                       : 1;
+	uint64_t iobld16                      : 1;
+	uint64_t iobld32                      : 1;
+	uint64_t iobld64                      : 1;
+	uint64_t iobst                        : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t saa                          : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn52xx;
+	struct cvmx_trax_trig0_cmd_cn52xx     cn52xxp1;
+	struct cvmx_trax_trig0_cmd_cn52xx     cn56xx;
+	struct cvmx_trax_trig0_cmd_cn52xx     cn56xxp1;
+	struct cvmx_trax_trig0_cmd_cn52xx     cn58xx;
+	struct cvmx_trax_trig0_cmd_cn52xx     cn58xxp1;
+	struct cvmx_trax_trig0_cmd_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t saa64                        : 1;  /**< Enable SAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t saa32                        : 1;  /**< Enable SAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_60_61               : 2;
+	uint64_t faa64                        : 1;  /**< Enable FAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t faa32                        : 1;  /**< Enable FAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_56_57               : 2;
+	uint64_t decr64                       : 1;  /**< Enable DECR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr32                       : 1;  /**< Enable DECR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr16                       : 1;  /**< Enable DECR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr8                        : 1;  /**< Enable DECR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr64                       : 1;  /**< Enable INCR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr32                       : 1;  /**< Enable INCR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr16                       : 1;  /**< Enable INCR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr8                        : 1;  /**< Enable INCR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr64                        : 1;  /**< Enable CLR64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr32                        : 1;  /**< Enable CLR32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr16                        : 1;  /**< Enable CLR16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr8                         : 1;  /**< Enable CLR8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t set64                        : 1;  /**< Enable SET64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set32                        : 1;  /**< Enable SET32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set16                        : 1;  /**< Enable SET16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set8                         : 1;  /**< Enable SET8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst64                      : 1;  /**< Enable IOBST64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst32                      : 1;  /**< Enable IOBST32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst16                      : 1;  /**< Enable IOBST16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst8                       : 1;  /**< Enable IOBST8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t lckl2                        : 1;  /**< Enable LCKL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbl2                         : 1;  /**< Enable WBL2    tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2                        : 1;  /**< Enable WBIL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t invl2                        : 1;  /**< Enable INVL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_27_27               : 1;
+	uint64_t stgl2i                       : 1;  /**< Enable STGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t ltgl2i                       : 1;  /**< Enable LTGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2i                       : 1;  /**< Enable WBIL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas64                        : 1;  /**< Enable FAS64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas32                        : 1;  /**< Enable FAS32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t sttil1                       : 1;  /**< Enable STTIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stfil1                       : 1;  /**< Enable STFIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stc                          : 1;  /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stp                          : 1;  /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stt                          : 1;  /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stf                          : 1;  /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_10_14               : 5;
+	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+	uint64_t rpl2                         : 1;  /**< Enable RPL2    tracing
+                                                         0=disable, 1=enable */
+	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t nop                          : 1;  /**< Enable NOP     tracing
+                                                         0=disable, 1=enable */
+#else
+	uint64_t nop                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t ldi                          : 1;
+	uint64_t pl2                          : 1;
+	uint64_t rpl2                         : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ldd                          : 1;
+	uint64_t psl1                         : 1;
+	uint64_t reserved_10_14               : 5;
+	uint64_t iobdma                       : 1;
+	uint64_t stf                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t stp                          : 1;
+	uint64_t stc                          : 1;
+	uint64_t stfil1                       : 1;
+	uint64_t sttil1                       : 1;
+	uint64_t fas32                        : 1;
+	uint64_t fas64                        : 1;
+	uint64_t wbil2i                       : 1;
+	uint64_t ltgl2i                       : 1;
+	uint64_t stgl2i                       : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t invl2                        : 1;
+	uint64_t wbil2                        : 1;
+	uint64_t wbl2                         : 1;
+	uint64_t lckl2                        : 1;
+	uint64_t iobld8                       : 1;
+	uint64_t iobld16                      : 1;
+	uint64_t iobld32                      : 1;
+	uint64_t iobld64                      : 1;
+	uint64_t iobst8                       : 1;
+	uint64_t iobst16                      : 1;
+	uint64_t iobst32                      : 1;
+	uint64_t iobst64                      : 1;
+	uint64_t set8                         : 1;
+	uint64_t set16                        : 1;
+	uint64_t set32                        : 1;
+	uint64_t set64                        : 1;
+	uint64_t clr8                         : 1;
+	uint64_t clr16                        : 1;
+	uint64_t clr32                        : 1;
+	uint64_t clr64                        : 1;
+	uint64_t incr8                        : 1;
+	uint64_t incr16                       : 1;
+	uint64_t incr32                       : 1;
+	uint64_t incr64                       : 1;
+	uint64_t decr8                        : 1;
+	uint64_t decr16                       : 1;
+	uint64_t decr32                       : 1;
+	uint64_t decr64                       : 1;
+	uint64_t reserved_56_57               : 2;
+	uint64_t faa32                        : 1;
+	uint64_t faa64                        : 1;
+	uint64_t reserved_60_61               : 2;
+	uint64_t saa32                        : 1;
+	uint64_t saa64                        : 1;
+#endif
+	} cn61xx;
+	struct cvmx_trax_trig0_cmd_cn61xx     cn63xx;
+	struct cvmx_trax_trig0_cmd_cn61xx     cn63xxp1;
+	struct cvmx_trax_trig0_cmd_cn61xx     cn66xx;
+	struct cvmx_trax_trig0_cmd_cn61xx     cn68xx;
+	struct cvmx_trax_trig0_cmd_cn61xx     cn68xxp1;
+	struct cvmx_trax_trig0_cmd_cn61xx     cnf71xx;
+};
+typedef union cvmx_trax_trig0_cmd cvmx_trax_trig0_cmd_t;
+
+/**
+ * cvmx_tra#_trig0_did
+ *
+ * TRA_TRIG0_DID = Trace Buffer Filter DestinationId Mask
+ *
+ * Description:
+ */
+union cvmx_trax_trig0_did {
+	uint64_t u64;
+	struct cvmx_trax_trig0_did_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_13_63               : 51;
+	uint64_t pow                          : 1;  /**< Enable triggering on requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+	uint64_t reserved_9_11                : 3;
+	uint64_t rng                          : 1;  /**< Enable triggering on requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+	uint64_t zip                          : 1;  /**< Enable triggering on requests to ZIP
+                                                         (doorbell stores are legal) */
+	uint64_t dfa                          : 1;  /**< Enable triggering on requests to DFA
+                                                         (CSR's and operations are legal) */
+	uint64_t fpa                          : 1;  /**< Enable triggering on requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+	uint64_t key                          : 1;  /**< Enable triggering on requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t illegal3                     : 2;  /**< Illegal destinations */
+	uint64_t mio                          : 1;  /**< Enable triggering on MIO accesses
+                                                         (CIU and GPIO CSR's, boot bus accesses) */
+#else
+	uint64_t mio                          : 1;
+	uint64_t illegal3                     : 2;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rng                          : 1;
+	uint64_t reserved_9_11                : 3;
+	uint64_t pow                          : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_trax_trig0_did_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t illegal                      : 19; /**< Illegal destinations */
+	uint64_t pow                          : 1;  /**< Enable triggering on requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+	uint64_t illegal2                     : 3;  /**< Illegal destinations */
+	uint64_t rng                          : 1;  /**< Enable triggering on requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+	uint64_t zip                          : 1;  /**< Enable triggering on requests to ZIP
+                                                         (doorbell stores are legal) */
+	uint64_t dfa                          : 1;  /**< Enable triggering on requests to DFA
+                                                         (CSR's and operations are legal) */
+	uint64_t fpa                          : 1;  /**< Enable triggering on requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+	uint64_t key                          : 1;  /**< Enable triggering on requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+	uint64_t pci                          : 1;  /**< Enable triggering on requests to PCI and RSL-type
+                                                         CSR's (RSL CSR's, PCI bus operations, PCI
+                                                         CSR's) */
+	uint64_t illegal3                     : 2;  /**< Illegal destinations */
+	uint64_t mio                          : 1;  /**< Enable triggering on CIU and GPIO CSR's */
+#else
+	uint64_t mio                          : 1;
+	uint64_t illegal3                     : 2;
+	uint64_t pci                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rng                          : 1;
+	uint64_t illegal2                     : 3;
+	uint64_t pow                          : 1;
+	uint64_t illegal                      : 19;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn31xx;
+	struct cvmx_trax_trig0_did_cn31xx     cn38xx;
+	struct cvmx_trax_trig0_did_cn31xx     cn38xxp2;
+	struct cvmx_trax_trig0_did_cn31xx     cn52xx;
+	struct cvmx_trax_trig0_did_cn31xx     cn52xxp1;
+	struct cvmx_trax_trig0_did_cn31xx     cn56xx;
+	struct cvmx_trax_trig0_did_cn31xx     cn56xxp1;
+	struct cvmx_trax_trig0_did_cn31xx     cn58xx;
+	struct cvmx_trax_trig0_did_cn31xx     cn58xxp1;
+	struct cvmx_trax_trig0_did_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t illegal5                     : 1;  /**< Illegal destinations */
+	uint64_t fau                          : 1;  /**< Enable triggering on FAU accesses */
+	uint64_t illegal4                     : 2;  /**< Illegal destinations */
+	uint64_t dpi                          : 1;  /**< Enable triggering on DPI accesses
+                                                         (DPI NCB CSRs) */
+	uint64_t illegal                      : 12; /**< Illegal destinations */
+	uint64_t rad                          : 1;  /**< Enable triggering on RAD accesses
+                                                         (doorbells) */
+	uint64_t usb0                         : 1;  /**< Enable triggering on USB0 accesses
+                                                         (UAHC0 EHCI and OHCI NCB CSRs) */
+	uint64_t pow                          : 1;  /**< Enable triggering on requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+	uint64_t illegal2                     : 1;  /**< Illegal destination */
+	uint64_t pko                          : 1;  /**< Enable triggering on PKO accesses
+                                                         (doorbells) */
+	uint64_t ipd                          : 1;  /**< Enable triggering on IPD CSR accesses
+                                                         (IPD CSRs) */
+	uint64_t rng                          : 1;  /**< Enable triggering on requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+	uint64_t zip                          : 1;  /**< Enable triggering on requests to ZIP
+                                                         (doorbell stores are legal) */
+	uint64_t dfa                          : 1;  /**< Enable triggering on requests to DFA
+                                                         (CSR's and operations are legal) */
+	uint64_t fpa                          : 1;  /**< Enable triggering on requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+	uint64_t key                          : 1;  /**< Enable triggering on requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+	uint64_t sli                          : 1;  /**< Enable triggering on requests to SLI and RSL-type
+                                                         CSR's (RSL CSR's, PCI/sRIO bus operations, SLI
+                                                         CSR's) */
+	uint64_t illegal3                     : 2;  /**< Illegal destinations */
+	uint64_t mio                          : 1;  /**< Enable triggering on MIO accesses
+                                                         (CIU and GPIO CSR's, boot bus accesses) */
+#else
+	uint64_t mio                          : 1;
+	uint64_t illegal3                     : 2;
+	uint64_t sli                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rng                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t illegal2                     : 1;
+	uint64_t pow                          : 1;
+	uint64_t usb0                         : 1;
+	uint64_t rad                          : 1;
+	uint64_t illegal                      : 12;
+	uint64_t dpi                          : 1;
+	uint64_t illegal4                     : 2;
+	uint64_t fau                          : 1;
+	uint64_t illegal5                     : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn61xx;
+	struct cvmx_trax_trig0_did_cn61xx     cn63xx;
+	struct cvmx_trax_trig0_did_cn61xx     cn63xxp1;
+	struct cvmx_trax_trig0_did_cn61xx     cn66xx;
+	struct cvmx_trax_trig0_did_cn61xx     cn68xx;
+	struct cvmx_trax_trig0_did_cn61xx     cn68xxp1;
+	struct cvmx_trax_trig0_did_cn61xx     cnf71xx;
+};
+typedef union cvmx_trax_trig0_did cvmx_trax_trig0_did_t;
+
+/**
+ * cvmx_tra#_trig0_sid
+ *
+ * TRA_TRIG0_SID = Trace Buffer Filter SourceId Mask
+ *
+ * Description:
+ */
+union cvmx_trax_trig0_sid {
+	uint64_t u64;
+	struct cvmx_trax_trig0_sid_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable triggering on requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable triggering on requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable triggering on read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable triggering on write requests from PIP/IPD */
+	uint64_t pp                           : 16; /**< Enable triggering from PP[N] with matching SourceID
+                                                         0=disable, 1=enable per bit N where 0<=N<=3 */
+#else
+	uint64_t pp                           : 16;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_trax_trig0_sid_s          cn31xx;
+	struct cvmx_trax_trig0_sid_s          cn38xx;
+	struct cvmx_trax_trig0_sid_s          cn38xxp2;
+	struct cvmx_trax_trig0_sid_s          cn52xx;
+	struct cvmx_trax_trig0_sid_s          cn52xxp1;
+	struct cvmx_trax_trig0_sid_s          cn56xx;
+	struct cvmx_trax_trig0_sid_s          cn56xxp1;
+	struct cvmx_trax_trig0_sid_s          cn58xx;
+	struct cvmx_trax_trig0_sid_s          cn58xxp1;
+	struct cvmx_trax_trig0_sid_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable triggering on requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable triggering on requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable triggering on read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable triggering on write requests from PIP/IPD */
+	uint64_t reserved_4_15                : 12;
+	uint64_t pp                           : 4;  /**< Enable triggering from PP[N] with matching SourceID
+                                                         0=disable, 1=enable per bit N where 0<=N<=3 */
+#else
+	uint64_t pp                           : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn61xx;
+	struct cvmx_trax_trig0_sid_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable triggering on requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable triggering on requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable triggering on read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable triggering on write requests from PIP/IPD */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pp                           : 8;  /**< Enable triggering from PP[N] with matching SourceID
+                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
+#else
+	uint64_t pp                           : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn63xx;
+	struct cvmx_trax_trig0_sid_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable triggering on requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable triggering on requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable triggering on read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable triggering on write requests from PIP/IPD */
+	uint64_t reserved_6_15                : 10;
+	uint64_t pp                           : 6;  /**< Enable triggering from PP[N] with matching SourceID
+                                                         0=disable, 1=enable per bit N where 0<=N<=5 */
+#else
+	uint64_t pp                           : 6;
+	uint64_t reserved_6_15                : 10;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn63xxp1;
+	struct cvmx_trax_trig0_sid_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable triggering on requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable triggering on requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable triggering on read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable triggering on write requests from PIP/IPD */
+	uint64_t reserved_10_15               : 6;
+	uint64_t pp                           : 10; /**< Enable triggering from PP[N] with matching SourceID
+                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
+#else
+	uint64_t pp                           : 10;
+	uint64_t reserved_10_15               : 6;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn66xx;
+	struct cvmx_trax_trig0_sid_cn63xx     cn68xx;
+	struct cvmx_trax_trig0_sid_cn63xx     cn68xxp1;
+	struct cvmx_trax_trig0_sid_cn61xx     cnf71xx;
+};
+typedef union cvmx_trax_trig0_sid cvmx_trax_trig0_sid_t;
+
+/**
+ * cvmx_tra#_trig1_adr_adr
+ *
+ * TRA_TRIG1_ADR_ADR = Trace Buffer Filter Address Address
+ *
+ * Description:
+ */
+union cvmx_trax_trig1_adr_adr {
+	uint64_t u64;
+	struct cvmx_trax_trig1_adr_adr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_38_63               : 26;
+	uint64_t adr                          : 38; /**< Unmasked Address
+                                                         The combination of TRA_TRIG1_ADR_ADR and
+                                                         TRA_TRIG1_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches */
+#else
+	uint64_t adr                          : 38;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_trax_trig1_adr_adr_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_36_63               : 28;
+	uint64_t adr                          : 36; /**< Unmasked Address
+                                                         The combination of TRA(0..0)_TRIG1_ADR_ADR and
+                                                         TRA(0..0)_TRIG1_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches */
+#else
+	uint64_t adr                          : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn31xx;
+	struct cvmx_trax_trig1_adr_adr_cn31xx cn38xx;
+	struct cvmx_trax_trig1_adr_adr_cn31xx cn38xxp2;
+	struct cvmx_trax_trig1_adr_adr_cn31xx cn52xx;
+	struct cvmx_trax_trig1_adr_adr_cn31xx cn52xxp1;
+	struct cvmx_trax_trig1_adr_adr_cn31xx cn56xx;
+	struct cvmx_trax_trig1_adr_adr_cn31xx cn56xxp1;
+	struct cvmx_trax_trig1_adr_adr_cn31xx cn58xx;
+	struct cvmx_trax_trig1_adr_adr_cn31xx cn58xxp1;
+	struct cvmx_trax_trig1_adr_adr_s      cn61xx;
+	struct cvmx_trax_trig1_adr_adr_s      cn63xx;
+	struct cvmx_trax_trig1_adr_adr_s      cn63xxp1;
+	struct cvmx_trax_trig1_adr_adr_s      cn66xx;
+	struct cvmx_trax_trig1_adr_adr_s      cn68xx;
+	struct cvmx_trax_trig1_adr_adr_s      cn68xxp1;
+	struct cvmx_trax_trig1_adr_adr_s      cnf71xx;
+};
+typedef union cvmx_trax_trig1_adr_adr cvmx_trax_trig1_adr_adr_t;
+
+/**
+ * cvmx_tra#_trig1_adr_msk
+ *
+ * TRA_TRIG1_ADR_MSK = Trace Buffer Filter Address Mask
+ *
+ * Description:
+ */
+union cvmx_trax_trig1_adr_msk {
+	uint64_t u64;
+	struct cvmx_trax_trig1_adr_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_38_63               : 26;
+	uint64_t adr                          : 38; /**< Address Mask
+                                                         The combination of TRA_TRIG1_ADR_ADR and
+                                                         TRA_TRIG1_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches.  When a mask bit is not
+                                                         set, the corresponding address bits are assumed
+                                                         to match.  Also, note that IOBDMAs do not have
+                                                         proper addresses, so when TRA_TRIG1_CMD[IOBDMA]
+                                                         is set, TRA_FILT_TRIG1_MSK must be zero to
+                                                         guarantee that any IOBDMAs are recognized as
+                                                         triggers. */
+#else
+	uint64_t adr                          : 38;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_trax_trig1_adr_msk_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_36_63               : 28;
+	uint64_t adr                          : 36; /**< Address Mask
+                                                         The combination of TRA(0..0)_TRIG1_ADR_ADR and
+                                                         TRA(0..0)_TRIG1_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches.  When a mask bit is not
+                                                         set, the corresponding address bits are assumed
+                                                         to match.  Also, note that IOBDMAs do not have
+                                                         proper addresses, so when TRA(0..0)_TRIG1_CMD[IOBDMA]
+                                                         is set, TRA(0..0)_FILT_TRIG1_MSK must be zero to
+                                                         guarantee that any IOBDMAs are recognized as
+                                                         triggers. */
+#else
+	uint64_t adr                          : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn31xx;
+	struct cvmx_trax_trig1_adr_msk_cn31xx cn38xx;
+	struct cvmx_trax_trig1_adr_msk_cn31xx cn38xxp2;
+	struct cvmx_trax_trig1_adr_msk_cn31xx cn52xx;
+	struct cvmx_trax_trig1_adr_msk_cn31xx cn52xxp1;
+	struct cvmx_trax_trig1_adr_msk_cn31xx cn56xx;
+	struct cvmx_trax_trig1_adr_msk_cn31xx cn56xxp1;
+	struct cvmx_trax_trig1_adr_msk_cn31xx cn58xx;
+	struct cvmx_trax_trig1_adr_msk_cn31xx cn58xxp1;
+	struct cvmx_trax_trig1_adr_msk_s      cn61xx;
+	struct cvmx_trax_trig1_adr_msk_s      cn63xx;
+	struct cvmx_trax_trig1_adr_msk_s      cn63xxp1;
+	struct cvmx_trax_trig1_adr_msk_s      cn66xx;
+	struct cvmx_trax_trig1_adr_msk_s      cn68xx;
+	struct cvmx_trax_trig1_adr_msk_s      cn68xxp1;
+	struct cvmx_trax_trig1_adr_msk_s      cnf71xx;
+};
+typedef union cvmx_trax_trig1_adr_msk cvmx_trax_trig1_adr_msk_t;
+
+/**
+ * cvmx_tra#_trig1_cmd
+ *
+ * TRA_TRIG1_CMD = Trace Buffer Filter Command Mask
+ *
+ * Description:
+ *
+ * Notes:
+ * Note that the trace buffer does not do proper IOBDMA address compares.  Thus, if IOBDMA is set, then
+ * the address compare must be disabled (i.e. TRA_TRIG1_ADR_MSK set to zero) to guarantee that IOBDMAs
+ * are recognized as triggers.
+ */
+union cvmx_trax_trig1_cmd {
+	uint64_t u64;
+	struct cvmx_trax_trig1_cmd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t saa64                        : 1;  /**< Enable SAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t saa32                        : 1;  /**< Enable SAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_60_61               : 2;
+	uint64_t faa64                        : 1;  /**< Enable FAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t faa32                        : 1;  /**< Enable FAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_56_57               : 2;
+	uint64_t decr64                       : 1;  /**< Enable DECR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr32                       : 1;  /**< Enable DECR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr16                       : 1;  /**< Enable DECR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr8                        : 1;  /**< Enable DECR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr64                       : 1;  /**< Enable INCR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr32                       : 1;  /**< Enable INCR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr16                       : 1;  /**< Enable INCR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr8                        : 1;  /**< Enable INCR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr64                        : 1;  /**< Enable CLR64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr32                        : 1;  /**< Enable CLR32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr16                        : 1;  /**< Enable CLR16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr8                         : 1;  /**< Enable CLR8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t set64                        : 1;  /**< Enable SET64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set32                        : 1;  /**< Enable SET32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set16                        : 1;  /**< Enable SET16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set8                         : 1;  /**< Enable SET8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst64                      : 1;  /**< Enable IOBST64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst32                      : 1;  /**< Enable IOBST32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst16                      : 1;  /**< Enable IOBST16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst8                       : 1;  /**< Enable IOBST8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_32_35               : 4;
+	uint64_t lckl2                        : 1;  /**< Enable LCKL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbl2                         : 1;  /**< Enable WBL2    tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2                        : 1;  /**< Enable WBIL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t invl2                        : 1;  /**< Enable INVL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_27_27               : 1;
+	uint64_t stgl2i                       : 1;  /**< Enable STGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t ltgl2i                       : 1;  /**< Enable LTGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2i                       : 1;  /**< Enable WBIL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas64                        : 1;  /**< Enable FAS64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas32                        : 1;  /**< Enable FAS32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t sttil1                       : 1;  /**< Enable STTIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stfil1                       : 1;  /**< Enable STFIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_16_19               : 4;
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_0_13                : 14;
+#else
+	uint64_t reserved_0_13                : 14;
+	uint64_t iobst                        : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t reserved_16_19               : 4;
+	uint64_t stfil1                       : 1;
+	uint64_t sttil1                       : 1;
+	uint64_t fas32                        : 1;
+	uint64_t fas64                        : 1;
+	uint64_t wbil2i                       : 1;
+	uint64_t ltgl2i                       : 1;
+	uint64_t stgl2i                       : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t invl2                        : 1;
+	uint64_t wbil2                        : 1;
+	uint64_t wbl2                         : 1;
+	uint64_t lckl2                        : 1;
+	uint64_t reserved_32_35               : 4;
+	uint64_t iobst8                       : 1;
+	uint64_t iobst16                      : 1;
+	uint64_t iobst32                      : 1;
+	uint64_t iobst64                      : 1;
+	uint64_t set8                         : 1;
+	uint64_t set16                        : 1;
+	uint64_t set32                        : 1;
+	uint64_t set64                        : 1;
+	uint64_t clr8                         : 1;
+	uint64_t clr16                        : 1;
+	uint64_t clr32                        : 1;
+	uint64_t clr64                        : 1;
+	uint64_t incr8                        : 1;
+	uint64_t incr16                       : 1;
+	uint64_t incr32                       : 1;
+	uint64_t incr64                       : 1;
+	uint64_t decr8                        : 1;
+	uint64_t decr16                       : 1;
+	uint64_t decr32                       : 1;
+	uint64_t decr64                       : 1;
+	uint64_t reserved_56_57               : 2;
+	uint64_t faa32                        : 1;
+	uint64_t faa64                        : 1;
+	uint64_t reserved_60_61               : 2;
+	uint64_t saa32                        : 1;
+	uint64_t saa64                        : 1;
+#endif
+	} s;
+	struct cvmx_trax_trig1_cmd_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_16_63               : 48;
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stt                          : 1;  /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stp                          : 1;  /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stc                          : 1;  /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stf                          : 1;  /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+#else
+	uint64_t dwb                          : 1;
+	uint64_t pl2                          : 1;
+	uint64_t psl1                         : 1;
+	uint64_t ldd                          : 1;
+	uint64_t ldi                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t stf                          : 1;
+	uint64_t stc                          : 1;
+	uint64_t stp                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t iobld8                       : 1;
+	uint64_t iobld16                      : 1;
+	uint64_t iobld32                      : 1;
+	uint64_t iobld64                      : 1;
+	uint64_t iobst                        : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn31xx;
+	struct cvmx_trax_trig1_cmd_cn31xx     cn38xx;
+	struct cvmx_trax_trig1_cmd_cn31xx     cn38xxp2;
+	struct cvmx_trax_trig1_cmd_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_17_63               : 47;
+	uint64_t saa                          : 1;  /**< Enable SAA     tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stt                          : 1;  /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stp                          : 1;  /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stc                          : 1;  /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stf                          : 1;  /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+#else
+	uint64_t dwb                          : 1;
+	uint64_t pl2                          : 1;
+	uint64_t psl1                         : 1;
+	uint64_t ldd                          : 1;
+	uint64_t ldi                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t stf                          : 1;
+	uint64_t stc                          : 1;
+	uint64_t stp                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t iobld8                       : 1;
+	uint64_t iobld16                      : 1;
+	uint64_t iobld32                      : 1;
+	uint64_t iobld64                      : 1;
+	uint64_t iobst                        : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t saa                          : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn52xx;
+	struct cvmx_trax_trig1_cmd_cn52xx     cn52xxp1;
+	struct cvmx_trax_trig1_cmd_cn52xx     cn56xx;
+	struct cvmx_trax_trig1_cmd_cn52xx     cn56xxp1;
+	struct cvmx_trax_trig1_cmd_cn52xx     cn58xx;
+	struct cvmx_trax_trig1_cmd_cn52xx     cn58xxp1;
+	struct cvmx_trax_trig1_cmd_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t saa64                        : 1;  /**< Enable SAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t saa32                        : 1;  /**< Enable SAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_60_61               : 2;
+	uint64_t faa64                        : 1;  /**< Enable FAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t faa32                        : 1;  /**< Enable FAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_56_57               : 2;
+	uint64_t decr64                       : 1;  /**< Enable DECR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr32                       : 1;  /**< Enable DECR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr16                       : 1;  /**< Enable DECR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr8                        : 1;  /**< Enable DECR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr64                       : 1;  /**< Enable INCR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr32                       : 1;  /**< Enable INCR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr16                       : 1;  /**< Enable INCR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr8                        : 1;  /**< Enable INCR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr64                        : 1;  /**< Enable CLR64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr32                        : 1;  /**< Enable CLR32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr16                        : 1;  /**< Enable CLR16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr8                         : 1;  /**< Enable CLR8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t set64                        : 1;  /**< Enable SET64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set32                        : 1;  /**< Enable SET32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set16                        : 1;  /**< Enable SET16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set8                         : 1;  /**< Enable SET8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst64                      : 1;  /**< Enable IOBST64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst32                      : 1;  /**< Enable IOBST32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst16                      : 1;  /**< Enable IOBST16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst8                       : 1;  /**< Enable IOBST8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t lckl2                        : 1;  /**< Enable LCKL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbl2                         : 1;  /**< Enable WBL2    tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2                        : 1;  /**< Enable WBIL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t invl2                        : 1;  /**< Enable INVL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_27_27               : 1;
+	uint64_t stgl2i                       : 1;  /**< Enable STGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t ltgl2i                       : 1;  /**< Enable LTGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2i                       : 1;  /**< Enable WBIL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas64                        : 1;  /**< Enable FAS64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas32                        : 1;  /**< Enable FAS32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t sttil1                       : 1;  /**< Enable STTIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stfil1                       : 1;  /**< Enable STFIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stc                          : 1;  /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stp                          : 1;  /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stt                          : 1;  /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stf                          : 1;  /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_10_14               : 5;
+	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+	uint64_t rpl2                         : 1;  /**< Enable RPL2    tracing
+                                                         0=disable, 1=enable */
+	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t nop                          : 1;  /**< Enable NOP     tracing
+                                                         0=disable, 1=enable */
+#else
+	uint64_t nop                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t ldi                          : 1;
+	uint64_t pl2                          : 1;
+	uint64_t rpl2                         : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ldd                          : 1;
+	uint64_t psl1                         : 1;
+	uint64_t reserved_10_14               : 5;
+	uint64_t iobdma                       : 1;
+	uint64_t stf                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t stp                          : 1;
+	uint64_t stc                          : 1;
+	uint64_t stfil1                       : 1;
+	uint64_t sttil1                       : 1;
+	uint64_t fas32                        : 1;
+	uint64_t fas64                        : 1;
+	uint64_t wbil2i                       : 1;
+	uint64_t ltgl2i                       : 1;
+	uint64_t stgl2i                       : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t invl2                        : 1;
+	uint64_t wbil2                        : 1;
+	uint64_t wbl2                         : 1;
+	uint64_t lckl2                        : 1;
+	uint64_t iobld8                       : 1;
+	uint64_t iobld16                      : 1;
+	uint64_t iobld32                      : 1;
+	uint64_t iobld64                      : 1;
+	uint64_t iobst8                       : 1;
+	uint64_t iobst16                      : 1;
+	uint64_t iobst32                      : 1;
+	uint64_t iobst64                      : 1;
+	uint64_t set8                         : 1;
+	uint64_t set16                        : 1;
+	uint64_t set32                        : 1;
+	uint64_t set64                        : 1;
+	uint64_t clr8                         : 1;
+	uint64_t clr16                        : 1;
+	uint64_t clr32                        : 1;
+	uint64_t clr64                        : 1;
+	uint64_t incr8                        : 1;
+	uint64_t incr16                       : 1;
+	uint64_t incr32                       : 1;
+	uint64_t incr64                       : 1;
+	uint64_t decr8                        : 1;
+	uint64_t decr16                       : 1;
+	uint64_t decr32                       : 1;
+	uint64_t decr64                       : 1;
+	uint64_t reserved_56_57               : 2;
+	uint64_t faa32                        : 1;
+	uint64_t faa64                        : 1;
+	uint64_t reserved_60_61               : 2;
+	uint64_t saa32                        : 1;
+	uint64_t saa64                        : 1;
+#endif
+	} cn61xx;
+	struct cvmx_trax_trig1_cmd_cn61xx     cn63xx;
+	struct cvmx_trax_trig1_cmd_cn61xx     cn63xxp1;
+	struct cvmx_trax_trig1_cmd_cn61xx     cn66xx;
+	struct cvmx_trax_trig1_cmd_cn61xx     cn68xx;
+	struct cvmx_trax_trig1_cmd_cn61xx     cn68xxp1;
+	struct cvmx_trax_trig1_cmd_cn61xx     cnf71xx;
+};
+typedef union cvmx_trax_trig1_cmd cvmx_trax_trig1_cmd_t;
+
+/**
+ * cvmx_tra#_trig1_did
+ *
+ * TRA_TRIG1_DID = Trace Buffer Filter DestinationId Mask
+ *
+ * Description:
+ */
+union cvmx_trax_trig1_did {
+	uint64_t u64;
+	struct cvmx_trax_trig1_did_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_13_63               : 51;
+	uint64_t pow                          : 1;  /**< Enable triggering on requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+	uint64_t reserved_9_11                : 3;
+	uint64_t rng                          : 1;  /**< Enable triggering on requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+	uint64_t zip                          : 1;  /**< Enable triggering on requests to ZIP
+                                                         (doorbell stores are legal) */
+	uint64_t dfa                          : 1;  /**< Enable triggering on requests to DFA
+                                                         (CSR's and operations are legal) */
+	uint64_t fpa                          : 1;  /**< Enable triggering on requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+	uint64_t key                          : 1;  /**< Enable triggering on requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t illegal3                     : 2;  /**< Illegal destinations */
+	uint64_t mio                          : 1;  /**< Enable triggering on MIO accesses
+                                                         (CIU and GPIO CSR's, boot bus accesses) */
+#else
+	uint64_t mio                          : 1;
+	uint64_t illegal3                     : 2;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rng                          : 1;
+	uint64_t reserved_9_11                : 3;
+	uint64_t pow                          : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_trax_trig1_did_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t illegal                      : 19; /**< Illegal destinations */
+	uint64_t pow                          : 1;  /**< Enable triggering on requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+	uint64_t illegal2                     : 3;  /**< Illegal destinations */
+	uint64_t rng                          : 1;  /**< Enable triggering on requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+	uint64_t zip                          : 1;  /**< Enable triggering on requests to ZIP
+                                                         (doorbell stores are legal) */
+	uint64_t dfa                          : 1;  /**< Enable triggering on requests to DFA
+                                                         (CSR's and operations are legal) */
+	uint64_t fpa                          : 1;  /**< Enable triggering on requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+	uint64_t key                          : 1;  /**< Enable triggering on requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+	uint64_t pci                          : 1;  /**< Enable triggering on requests to PCI and RSL-type
+                                                         CSR's (RSL CSR's, PCI bus operations, PCI
+                                                         CSR's) */
+	uint64_t illegal3                     : 2;  /**< Illegal destinations */
+	uint64_t mio                          : 1;  /**< Enable triggering on CIU and GPIO CSR's */
+#else
+	uint64_t mio                          : 1;
+	uint64_t illegal3                     : 2;
+	uint64_t pci                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rng                          : 1;
+	uint64_t illegal2                     : 3;
+	uint64_t pow                          : 1;
+	uint64_t illegal                      : 19;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn31xx;
+	struct cvmx_trax_trig1_did_cn31xx     cn38xx;
+	struct cvmx_trax_trig1_did_cn31xx     cn38xxp2;
+	struct cvmx_trax_trig1_did_cn31xx     cn52xx;
+	struct cvmx_trax_trig1_did_cn31xx     cn52xxp1;
+	struct cvmx_trax_trig1_did_cn31xx     cn56xx;
+	struct cvmx_trax_trig1_did_cn31xx     cn56xxp1;
+	struct cvmx_trax_trig1_did_cn31xx     cn58xx;
+	struct cvmx_trax_trig1_did_cn31xx     cn58xxp1;
+	struct cvmx_trax_trig1_did_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_32_63               : 32;
+	uint64_t illegal5                     : 1;  /**< Illegal destinations */
+	uint64_t fau                          : 1;  /**< Enable triggering on FAU accesses */
+	uint64_t illegal4                     : 2;  /**< Illegal destinations */
+	uint64_t dpi                          : 1;  /**< Enable triggering on DPI accesses
+                                                         (DPI NCB CSRs) */
+	uint64_t illegal                      : 12; /**< Illegal destinations */
+	uint64_t rad                          : 1;  /**< Enable triggering on RAD accesses
+                                                         (doorbells) */
+	uint64_t usb0                         : 1;  /**< Enable triggering on USB0 accesses
+                                                         (UAHC0 EHCI and OHCI NCB CSRs) */
+	uint64_t pow                          : 1;  /**< Enable triggering on requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+	uint64_t illegal2                     : 1;  /**< Illegal destination */
+	uint64_t pko                          : 1;  /**< Enable triggering on PKO accesses
+                                                         (doorbells) */
+	uint64_t ipd                          : 1;  /**< Enable triggering on IPD CSR accesses
+                                                         (IPD CSRs) */
+	uint64_t rng                          : 1;  /**< Enable triggering on requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+	uint64_t zip                          : 1;  /**< Enable triggering on requests to ZIP
+                                                         (doorbell stores are legal) */
+	uint64_t dfa                          : 1;  /**< Enable triggering on requests to DFA
+                                                         (CSR's and operations are legal) */
+	uint64_t fpa                          : 1;  /**< Enable triggering on requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+	uint64_t key                          : 1;  /**< Enable triggering on requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+	uint64_t sli                          : 1;  /**< Enable triggering on requests to SLI and RSL-type
+                                                         CSR's (RSL CSR's, PCI/sRIO bus operations, SLI
+                                                         CSR's) */
+	uint64_t illegal3                     : 2;  /**< Illegal destinations */
+	uint64_t mio                          : 1;  /**< Enable triggering on MIO accesses
+                                                         (CIU and GPIO CSR's, boot bus accesses) */
+#else
+	uint64_t mio                          : 1;
+	uint64_t illegal3                     : 2;
+	uint64_t sli                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rng                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t illegal2                     : 1;
+	uint64_t pow                          : 1;
+	uint64_t usb0                         : 1;
+	uint64_t rad                          : 1;
+	uint64_t illegal                      : 12;
+	uint64_t dpi                          : 1;
+	uint64_t illegal4                     : 2;
+	uint64_t fau                          : 1;
+	uint64_t illegal5                     : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn61xx;
+	struct cvmx_trax_trig1_did_cn61xx     cn63xx;
+	struct cvmx_trax_trig1_did_cn61xx     cn63xxp1;
+	struct cvmx_trax_trig1_did_cn61xx     cn66xx;
+	struct cvmx_trax_trig1_did_cn61xx     cn68xx;
+	struct cvmx_trax_trig1_did_cn61xx     cn68xxp1;
+	struct cvmx_trax_trig1_did_cn61xx     cnf71xx;
+};
+typedef union cvmx_trax_trig1_did cvmx_trax_trig1_did_t;
+
+/**
+ * cvmx_tra#_trig1_sid
+ *
+ * TRA_TRIG1_SID = Trace Buffer Filter SourceId Mask
+ *
+ * Description:
+ */
+union cvmx_trax_trig1_sid {
+	uint64_t u64;
+	struct cvmx_trax_trig1_sid_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable triggering on requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable triggering on requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable triggering on read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable triggering on write requests from PIP/IPD */
+	uint64_t pp                           : 16; /**< Enable trigering from PP[N] with matching SourceID
+                                                         0=disable, 1=enable per bit N where 0<=N<=3 */
+#else
+	uint64_t pp                           : 16;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_trax_trig1_sid_s          cn31xx;
+	struct cvmx_trax_trig1_sid_s          cn38xx;
+	struct cvmx_trax_trig1_sid_s          cn38xxp2;
+	struct cvmx_trax_trig1_sid_s          cn52xx;
+	struct cvmx_trax_trig1_sid_s          cn52xxp1;
+	struct cvmx_trax_trig1_sid_s          cn56xx;
+	struct cvmx_trax_trig1_sid_s          cn56xxp1;
+	struct cvmx_trax_trig1_sid_s          cn58xx;
+	struct cvmx_trax_trig1_sid_s          cn58xxp1;
+	struct cvmx_trax_trig1_sid_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable triggering on requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable triggering on requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable triggering on read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable triggering on write requests from PIP/IPD */
+	uint64_t reserved_4_15                : 12;
+	uint64_t pp                           : 4;  /**< Enable trigering from PP[N] with matching SourceID
+                                                         0=disable, 1=enable per bit N where 0<=N<=3 */
+#else
+	uint64_t pp                           : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn61xx;
+	struct cvmx_trax_trig1_sid_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable triggering on requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable triggering on requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable triggering on read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable triggering on write requests from PIP/IPD */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pp                           : 8;  /**< Enable trigering from PP[N] with matching SourceID
+                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
+#else
+	uint64_t pp                           : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn63xx;
+	struct cvmx_trax_trig1_sid_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable triggering on requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable triggering on requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable triggering on read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable triggering on write requests from PIP/IPD */
+	uint64_t reserved_6_15                : 10;
+	uint64_t pp                           : 6;  /**< Enable trigering from PP[N] with matching SourceID
+                                                         0=disable, 1=enable per bit N where 0<=N<=5 */
+#else
+	uint64_t pp                           : 6;
+	uint64_t reserved_6_15                : 10;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn63xxp1;
+	struct cvmx_trax_trig1_sid_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable triggering on requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable triggering on requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable triggering on read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable triggering on write requests from PIP/IPD */
+	uint64_t reserved_10_15               : 6;
+	uint64_t pp                           : 10; /**< Enable trigering from PP[N] with matching SourceID
+                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
+#else
+	uint64_t pp                           : 10;
+	uint64_t reserved_10_15               : 6;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn66xx;
+	struct cvmx_trax_trig1_sid_cn63xx     cn68xx;
+	struct cvmx_trax_trig1_sid_cn63xx     cn68xxp1;
+	struct cvmx_trax_trig1_sid_cn61xx     cnf71xx;
+};
+typedef union cvmx_trax_trig1_sid cvmx_trax_trig1_sid_t;
+
+#include "cvmx-tra-defs.h"
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-twsi.c b/sys/contrib/octeon-sdk/cvmx-twsi.c
index 30e8081..4b41ace 100644
--- a/sys/contrib/octeon-sdk/cvmx-twsi.c
+++ b/sys/contrib/octeon-sdk/cvmx-twsi.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Interface to the TWSI / I2C bus
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
@@ -71,9 +71,9 @@
 #endif
 
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+# if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 static struct i2c_adapter *__cvmx_twsix_get_adapter(int twsi_id)
 {
-# if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 	struct octeon_i2c {
 		wait_queue_head_t queue;
 		struct i2c_adapter adap;
@@ -94,11 +94,9 @@ static struct i2c_adapter *__cvmx_twsix_get_adapter(int twsi_id)
 		return NULL;
 	i2c = container_of(adapter, struct octeon_i2c, adap);
 	return &i2c[twsi_id].adap;
-#else
-	return NULL;
-#endif
 }
 #endif
+#endif
 
 
 /**
@@ -171,10 +169,11 @@ int cvmx_twsix_read_ia(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, in
 #else
 	cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
 	cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
+        int retry_limit = 5;
 
 	if (num_bytes < 1 || num_bytes > 8 || !data || ia_width_bytes < 0 || ia_width_bytes > 2)
 		return -1;
-
+retry:
 	twsi_ext.u64 = 0;
 	sw_twsi_val.u64 = 0;
 	sw_twsi_val.s.v = 1;
@@ -197,11 +196,36 @@ int cvmx_twsix_read_ia(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, in
 	cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
 	cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
 	while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
-		;
+		cvmx_wait(1000);
 	twsi_printf("Results:\n");
 	cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
 	if (!sw_twsi_val.s.r)
-		return -1;
+        {
+            /* Check the reason for the failure.  We may need to retry to handle multi-master
+            ** configurations.
+            ** Lost arbitration : 0x38, 0x68, 0xB0, 0x78
+            ** Core busy as slave: 0x80, 0x88, 0xA0, 0xA8, 0xB8, 0xC0, 0xC8
+            */
+            if (sw_twsi_val.s.d == 0x38
+                || sw_twsi_val.s.d == 0x68
+                || sw_twsi_val.s.d == 0xB0
+                || sw_twsi_val.s.d == 0x78
+                || sw_twsi_val.s.d == 0x80
+                || sw_twsi_val.s.d == 0x88
+                || sw_twsi_val.s.d == 0xA0
+                || sw_twsi_val.s.d == 0xA8
+                || sw_twsi_val.s.d == 0xB8
+                || sw_twsi_val.s.d == 0xC8)
+            {
+                if (retry_limit-- > 0)
+                {
+                    cvmx_wait_usec(100);
+                    goto retry;
+                }
+            }
+            /* For all other errors, return an error code */
+            return -1;
+        }
 
 	*data = (sw_twsi_val.s.d & (0xFFFFFFFF >> (32 - num_bytes*8)));
 	if (num_bytes > 4) {
@@ -265,10 +289,11 @@ int cvmx_twsix_read(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t *data
 #else
 	cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
 	cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
+        int retry_limit = 5;
 
 	if (num_bytes > 8 || num_bytes < 1)
 		return -1;
-
+retry:
 	sw_twsi_val.u64 = 0;
 	sw_twsi_val.s.v = 1;
 	sw_twsi_val.s.r = 1;
@@ -279,11 +304,37 @@ int cvmx_twsix_read(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t *data
 	cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
 	cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
 	while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
-		;
+            cvmx_wait(1000);
 	twsi_printf("Results:\n");
 	cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
 	if (!sw_twsi_val.s.r)
-		return -1;
+            if (!sw_twsi_val.s.r)
+            {
+                /* Check the reason for the failure.  We may need to retry to handle multi-master
+                ** configurations.
+                ** Lost arbitration : 0x38, 0x68, 0xB0, 0x78
+                ** Core busy as slave: 0x80, 0x88, 0xA0, 0xA8, 0xB8, 0xC0, 0xC8
+                */
+                if (sw_twsi_val.s.d == 0x38
+                    || sw_twsi_val.s.d == 0x68
+                    || sw_twsi_val.s.d == 0xB0
+                    || sw_twsi_val.s.d == 0x78
+                    || sw_twsi_val.s.d == 0x80
+                    || sw_twsi_val.s.d == 0x88
+                    || sw_twsi_val.s.d == 0xA0
+                    || sw_twsi_val.s.d == 0xA8
+                    || sw_twsi_val.s.d == 0xB8
+                    || sw_twsi_val.s.d == 0xC8)
+                {
+                    if (retry_limit-- > 0)
+                    {
+                        cvmx_wait_usec(100);
+                        goto retry;
+                     }
+                }
+                /* For all other errors, return an error code */
+                return -1;
+            }
 
 	*data = (sw_twsi_val.s.d & (0xFFFFFFFF >> (32 - num_bytes*8)));
 	if (num_bytes > 4) {
@@ -328,10 +379,10 @@ int cvmx_twsix_write(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t data
 	for (j = 0, i = num_bytes - 1; i >= 0; i--, j++)
 		data_buf[j] = (u8)(data >> (i * 8));
 
-	msg[1].addr = dev_addr;
-	msg[1].flags = 0;
-	msg[1].len = num_bytes;
-	msg[1].buf = data_buf;
+	msg[0].addr = dev_addr;
+	msg[0].flags = 0;
+	msg[0].len = num_bytes;
+	msg[0].buf = data_buf;
 
 	i = i2c_transfer(adapter, msg, 1);
 
diff --git a/sys/contrib/octeon-sdk/cvmx-twsi.h b/sys/contrib/octeon-sdk/cvmx-twsi.h
index 7ca8798..988b65d 100644
--- a/sys/contrib/octeon-sdk/cvmx-twsi.h
+++ b/sys/contrib/octeon-sdk/cvmx-twsi.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -50,7 +50,7 @@
  *
  * Note: Currently on 7 bit device addresses are supported
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-uahcx-defs.h b/sys/contrib/octeon-sdk/cvmx-uahcx-defs.h
index d5cd1c1..3886c71 100644
--- a/sys/contrib/octeon-sdk/cvmx-uahcx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-uahcx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,18 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_UAHCX_TYPEDEFS_H__
-#define __CVMX_UAHCX_TYPEDEFS_H__
+#ifndef __CVMX_UAHCX_DEFS_H__
+#define __CVMX_UAHCX_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_UAHCX_EHCI_ASYNCLISTADDR(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_EHCI_ASYNCLISTADDR(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000028ull);
 }
@@ -67,7 +71,11 @@ static inline uint64_t CVMX_UAHCX_EHCI_ASYNCLISTADDR(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_EHCI_CONFIGFLAG(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_EHCI_CONFIGFLAG(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000050ull);
 }
@@ -78,7 +86,11 @@ static inline uint64_t CVMX_UAHCX_EHCI_CONFIGFLAG(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_EHCI_CTRLDSSEGMENT(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_EHCI_CTRLDSSEGMENT(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000020ull);
 }
@@ -89,7 +101,11 @@ static inline uint64_t CVMX_UAHCX_EHCI_CTRLDSSEGMENT(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_EHCI_FRINDEX(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_EHCI_FRINDEX(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F000000001Cull);
 }
@@ -100,7 +116,11 @@ static inline uint64_t CVMX_UAHCX_EHCI_FRINDEX(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_EHCI_HCCAPBASE(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_EHCI_HCCAPBASE(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000000ull);
 }
@@ -111,7 +131,11 @@ static inline uint64_t CVMX_UAHCX_EHCI_HCCAPBASE(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_EHCI_HCCPARAMS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_EHCI_HCCPARAMS(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000008ull);
 }
@@ -122,7 +146,11 @@ static inline uint64_t CVMX_UAHCX_EHCI_HCCPARAMS(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_EHCI_HCSPARAMS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_EHCI_HCSPARAMS(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000004ull);
 }
@@ -133,7 +161,11 @@ static inline uint64_t CVMX_UAHCX_EHCI_HCSPARAMS(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_EHCI_INSNREG00(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_EHCI_INSNREG00(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000090ull);
 }
@@ -144,7 +176,11 @@ static inline uint64_t CVMX_UAHCX_EHCI_INSNREG00(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_EHCI_INSNREG03(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_EHCI_INSNREG03(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F000000009Cull);
 }
@@ -155,7 +191,11 @@ static inline uint64_t CVMX_UAHCX_EHCI_INSNREG03(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_EHCI_INSNREG04(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_EHCI_INSNREG04(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F00000000A0ull);
 }
@@ -166,7 +206,11 @@ static inline uint64_t CVMX_UAHCX_EHCI_INSNREG04(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_EHCI_INSNREG06(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_EHCI_INSNREG06(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F00000000E8ull);
 }
@@ -177,7 +221,11 @@ static inline uint64_t CVMX_UAHCX_EHCI_INSNREG06(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_EHCI_INSNREG07(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_EHCI_INSNREG07(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F00000000ECull);
 }
@@ -188,7 +236,11 @@ static inline uint64_t CVMX_UAHCX_EHCI_INSNREG07(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_EHCI_PERIODICLISTBASE(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_EHCI_PERIODICLISTBASE(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000024ull);
 }
@@ -199,7 +251,11 @@ static inline uint64_t CVMX_UAHCX_EHCI_PERIODICLISTBASE(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_EHCI_PORTSCX(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0))))))
 		cvmx_warn("CVMX_UAHCX_EHCI_PORTSCX(%lu,%lu) is invalid on this chip\n", offset, block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4;
 }
@@ -210,7 +266,11 @@ static inline uint64_t CVMX_UAHCX_EHCI_PORTSCX(unsigned long offset, unsigned lo
 static inline uint64_t CVMX_UAHCX_EHCI_USBCMD(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_EHCI_USBCMD(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000010ull);
 }
@@ -221,7 +281,11 @@ static inline uint64_t CVMX_UAHCX_EHCI_USBCMD(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_EHCI_USBINTR(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_EHCI_USBINTR(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000018ull);
 }
@@ -232,7 +296,11 @@ static inline uint64_t CVMX_UAHCX_EHCI_USBINTR(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_EHCI_USBSTS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_EHCI_USBSTS(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000014ull);
 }
@@ -243,7 +311,11 @@ static inline uint64_t CVMX_UAHCX_EHCI_USBSTS(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_OHCI0_HCBULKCURRENTED(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCBULKCURRENTED(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F000000042Cull);
 }
@@ -254,7 +326,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCBULKCURRENTED(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_OHCI0_HCBULKHEADED(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCBULKHEADED(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000428ull);
 }
@@ -265,7 +341,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCBULKHEADED(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_OHCI0_HCCOMMANDSTATUS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCCOMMANDSTATUS(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000408ull);
 }
@@ -276,7 +356,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCCOMMANDSTATUS(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_OHCI0_HCCONTROL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCCONTROL(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000404ull);
 }
@@ -287,7 +371,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCCONTROL(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_OHCI0_HCCONTROLCURRENTED(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCCONTROLCURRENTED(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000424ull);
 }
@@ -298,7 +386,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCCONTROLCURRENTED(unsigned long block_i
 static inline uint64_t CVMX_UAHCX_OHCI0_HCCONTROLHEADED(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCCONTROLHEADED(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000420ull);
 }
@@ -309,7 +401,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCCONTROLHEADED(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_OHCI0_HCDONEHEAD(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCDONEHEAD(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000430ull);
 }
@@ -320,7 +416,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCDONEHEAD(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_OHCI0_HCFMINTERVAL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCFMINTERVAL(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000434ull);
 }
@@ -331,7 +431,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCFMINTERVAL(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_OHCI0_HCFMNUMBER(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCFMNUMBER(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F000000043Cull);
 }
@@ -342,7 +446,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCFMNUMBER(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_OHCI0_HCFMREMAINING(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCFMREMAINING(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000438ull);
 }
@@ -353,7 +461,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCFMREMAINING(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_OHCI0_HCHCCA(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCHCCA(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000418ull);
 }
@@ -364,7 +476,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCHCCA(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_OHCI0_HCINTERRUPTDISABLE(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCINTERRUPTDISABLE(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000414ull);
 }
@@ -375,7 +491,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCINTERRUPTDISABLE(unsigned long block_i
 static inline uint64_t CVMX_UAHCX_OHCI0_HCINTERRUPTENABLE(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCINTERRUPTENABLE(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000410ull);
 }
@@ -386,7 +506,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCINTERRUPTENABLE(unsigned long block_id
 static inline uint64_t CVMX_UAHCX_OHCI0_HCINTERRUPTSTATUS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCINTERRUPTSTATUS(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F000000040Cull);
 }
@@ -397,7 +521,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCINTERRUPTSTATUS(unsigned long block_id
 static inline uint64_t CVMX_UAHCX_OHCI0_HCLSTHRESHOLD(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCLSTHRESHOLD(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000444ull);
 }
@@ -408,7 +536,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCLSTHRESHOLD(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_OHCI0_HCPERIODCURRENTED(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCPERIODCURRENTED(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F000000041Cull);
 }
@@ -419,7 +551,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCPERIODCURRENTED(unsigned long block_id
 static inline uint64_t CVMX_UAHCX_OHCI0_HCPERIODICSTART(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCPERIODICSTART(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000440ull);
 }
@@ -430,7 +566,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCPERIODICSTART(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_OHCI0_HCREVISION(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCREVISION(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000400ull);
 }
@@ -441,7 +581,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCREVISION(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_OHCI0_HCRHDESCRIPTORA(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCRHDESCRIPTORA(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000448ull);
 }
@@ -452,7 +596,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCRHDESCRIPTORA(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_OHCI0_HCRHDESCRIPTORB(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCRHDESCRIPTORB(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F000000044Cull);
 }
@@ -463,7 +611,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCRHDESCRIPTORB(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_OHCI0_HCRHPORTSTATUSX(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0))))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCRHPORTSTATUSX(%lu,%lu) is invalid on this chip\n", offset, block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000450ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4;
 }
@@ -474,7 +626,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCRHPORTSTATUSX(unsigned long offset, un
 static inline uint64_t CVMX_UAHCX_OHCI0_HCRHSTATUS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_HCRHSTATUS(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000450ull);
 }
@@ -485,7 +641,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_HCRHSTATUS(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_OHCI0_INSNREG06(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_INSNREG06(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F0000000498ull);
 }
@@ -496,7 +656,11 @@ static inline uint64_t CVMX_UAHCX_OHCI0_INSNREG06(unsigned long block_id)
 static inline uint64_t CVMX_UAHCX_OHCI0_INSNREG07(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UAHCX_OHCI0_INSNREG07(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x00016F000000049Cull);
 }
@@ -516,12 +680,10 @@ static inline uint64_t CVMX_UAHCX_OHCI0_INSNREG07(unsigned long block_id)
  * software and will always return a zero when read. The memory structure referenced by this physical memory
  * pointer is assumed to be 32-byte (cache line) aligned.
  */
-union cvmx_uahcx_ehci_asynclistaddr
-{
+union cvmx_uahcx_ehci_asynclistaddr {
 	uint32_t u32;
-	struct cvmx_uahcx_ehci_asynclistaddr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ehci_asynclistaddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t lpl                          : 27; /**< Link Pointer Low (LPL). These bits correspond to memory address signals [31:5],
                                                          respectively. This field may only reference a Queue Head (QH). */
 	uint32_t reserved_0_4                 : 5;
@@ -530,8 +692,13 @@ union cvmx_uahcx_ehci_asynclistaddr
 	uint32_t lpl                          : 27;
 #endif
 	} s;
+	struct cvmx_uahcx_ehci_asynclistaddr_s cn61xx;
 	struct cvmx_uahcx_ehci_asynclistaddr_s cn63xx;
 	struct cvmx_uahcx_ehci_asynclistaddr_s cn63xxp1;
+	struct cvmx_uahcx_ehci_asynclistaddr_s cn66xx;
+	struct cvmx_uahcx_ehci_asynclistaddr_s cn68xx;
+	struct cvmx_uahcx_ehci_asynclistaddr_s cn68xxp1;
+	struct cvmx_uahcx_ehci_asynclistaddr_s cnf71xx;
 };
 typedef union cvmx_uahcx_ehci_asynclistaddr cvmx_uahcx_ehci_asynclistaddr_t;
 
@@ -542,12 +709,10 @@ typedef union cvmx_uahcx_ehci_asynclistaddr cvmx_uahcx_ehci_asynclistaddr_t;
  * This register is in the auxiliary power well. It is only reset by hardware when the auxiliary power is initially
  * applied or in response to a host controller reset.
  */
-union cvmx_uahcx_ehci_configflag
-{
+union cvmx_uahcx_ehci_configflag {
 	uint32_t u32;
-	struct cvmx_uahcx_ehci_configflag_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ehci_configflag_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_1_31                : 31;
 	uint32_t cf                           : 1;  /**< Configure Flag (CF) .Host software sets this bit as the last action in
                                                          its process of configuring the Host Controller (see Section 4.1). This bit controls the
@@ -560,8 +725,13 @@ union cvmx_uahcx_ehci_configflag
 	uint32_t reserved_1_31                : 31;
 #endif
 	} s;
+	struct cvmx_uahcx_ehci_configflag_s   cn61xx;
 	struct cvmx_uahcx_ehci_configflag_s   cn63xx;
 	struct cvmx_uahcx_ehci_configflag_s   cn63xxp1;
+	struct cvmx_uahcx_ehci_configflag_s   cn66xx;
+	struct cvmx_uahcx_ehci_configflag_s   cn68xx;
+	struct cvmx_uahcx_ehci_configflag_s   cn68xxp1;
+	struct cvmx_uahcx_ehci_configflag_s   cnf71xx;
 };
 typedef union cvmx_uahcx_ehci_configflag cvmx_uahcx_ehci_configflag_t;
 
@@ -582,19 +752,22 @@ typedef union cvmx_uahcx_ehci_configflag cvmx_uahcx_ehci_configflag_t;
  * This register allows the host software to locate all control data structures within the same 4 Gigabyte
  * memory segment.
  */
-union cvmx_uahcx_ehci_ctrldssegment
-{
+union cvmx_uahcx_ehci_ctrldssegment {
 	uint32_t u32;
-	struct cvmx_uahcx_ehci_ctrldssegment_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ehci_ctrldssegment_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ctrldsseg                    : 32; /**< Control Data Strucute Semgent Address Bit [63:32] */
 #else
 	uint32_t ctrldsseg                    : 32;
 #endif
 	} s;
+	struct cvmx_uahcx_ehci_ctrldssegment_s cn61xx;
 	struct cvmx_uahcx_ehci_ctrldssegment_s cn63xx;
 	struct cvmx_uahcx_ehci_ctrldssegment_s cn63xxp1;
+	struct cvmx_uahcx_ehci_ctrldssegment_s cn66xx;
+	struct cvmx_uahcx_ehci_ctrldssegment_s cn68xx;
+	struct cvmx_uahcx_ehci_ctrldssegment_s cn68xxp1;
+	struct cvmx_uahcx_ehci_ctrldssegment_s cnf71xx;
 };
 typedef union cvmx_uahcx_ehci_ctrldssegment cvmx_uahcx_ehci_ctrldssegment_t;
 
@@ -610,12 +783,10 @@ typedef union cvmx_uahcx_ehci_ctrldssegment cvmx_uahcx_ehci_ctrldssegment_t;
  * HCHalted bit. A write to this register while the Run/Stop bit is set to a one (USBCMD register) produces
  * undefined results. Writes to this register also affect the SOF value.
  */
-union cvmx_uahcx_ehci_frindex
-{
+union cvmx_uahcx_ehci_frindex {
 	uint32_t u32;
-	struct cvmx_uahcx_ehci_frindex_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ehci_frindex_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_14_31               : 18;
 	uint32_t fi                           : 14; /**< Frame Index. The value in this register increments at the end of each time frame (e.g.
                                                          micro-frame). Bits [N:3] are used for the Frame List current index. This means that each
@@ -632,8 +803,13 @@ union cvmx_uahcx_ehci_frindex
 	uint32_t reserved_14_31               : 18;
 #endif
 	} s;
+	struct cvmx_uahcx_ehci_frindex_s      cn61xx;
 	struct cvmx_uahcx_ehci_frindex_s      cn63xx;
 	struct cvmx_uahcx_ehci_frindex_s      cn63xxp1;
+	struct cvmx_uahcx_ehci_frindex_s      cn66xx;
+	struct cvmx_uahcx_ehci_frindex_s      cn68xx;
+	struct cvmx_uahcx_ehci_frindex_s      cn68xxp1;
+	struct cvmx_uahcx_ehci_frindex_s      cnf71xx;
 };
 typedef union cvmx_uahcx_ehci_frindex cvmx_uahcx_ehci_frindex_t;
 
@@ -643,12 +819,10 @@ typedef union cvmx_uahcx_ehci_frindex cvmx_uahcx_ehci_frindex_t;
  * HCCAPBASE = Host Controller BASE Capability Register
  *
  */
-union cvmx_uahcx_ehci_hccapbase
-{
+union cvmx_uahcx_ehci_hccapbase {
 	uint32_t u32;
-	struct cvmx_uahcx_ehci_hccapbase_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ehci_hccapbase_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t hciversion                   : 16; /**< Host Controller Interface Version Number */
 	uint32_t reserved_8_15                : 8;
 	uint32_t caplength                    : 8;  /**< Capabitlity Registers Length */
@@ -658,8 +832,13 @@ union cvmx_uahcx_ehci_hccapbase
 	uint32_t hciversion                   : 16;
 #endif
 	} s;
+	struct cvmx_uahcx_ehci_hccapbase_s    cn61xx;
 	struct cvmx_uahcx_ehci_hccapbase_s    cn63xx;
 	struct cvmx_uahcx_ehci_hccapbase_s    cn63xxp1;
+	struct cvmx_uahcx_ehci_hccapbase_s    cn66xx;
+	struct cvmx_uahcx_ehci_hccapbase_s    cn68xx;
+	struct cvmx_uahcx_ehci_hccapbase_s    cn68xxp1;
+	struct cvmx_uahcx_ehci_hccapbase_s    cnf71xx;
 };
 typedef union cvmx_uahcx_ehci_hccapbase cvmx_uahcx_ehci_hccapbase_t;
 
@@ -669,12 +848,10 @@ typedef union cvmx_uahcx_ehci_hccapbase cvmx_uahcx_ehci_hccapbase_t;
  * HCCPARAMS = Host Controller Capability Parameters
  * Multiple Mode control (time-base bit functionality), addressing capability
  */
-union cvmx_uahcx_ehci_hccparams
-{
+union cvmx_uahcx_ehci_hccparams {
 	uint32_t u32;
-	struct cvmx_uahcx_ehci_hccparams_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ehci_hccparams_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_16_31               : 16;
 	uint32_t eecp                         : 8;  /**< EHCI Extended Capabilities Pointer. Default = Implementation Dependent.
                                                          This optional field indicates the existence of a capabilities list. A value of 00h indicates
@@ -720,8 +897,13 @@ union cvmx_uahcx_ehci_hccparams
 	uint32_t reserved_16_31               : 16;
 #endif
 	} s;
+	struct cvmx_uahcx_ehci_hccparams_s    cn61xx;
 	struct cvmx_uahcx_ehci_hccparams_s    cn63xx;
 	struct cvmx_uahcx_ehci_hccparams_s    cn63xxp1;
+	struct cvmx_uahcx_ehci_hccparams_s    cn66xx;
+	struct cvmx_uahcx_ehci_hccparams_s    cn68xx;
+	struct cvmx_uahcx_ehci_hccparams_s    cn68xxp1;
+	struct cvmx_uahcx_ehci_hccparams_s    cnf71xx;
 };
 typedef union cvmx_uahcx_ehci_hccparams cvmx_uahcx_ehci_hccparams_t;
 
@@ -731,12 +913,10 @@ typedef union cvmx_uahcx_ehci_hccparams cvmx_uahcx_ehci_hccparams_t;
  * HCSPARAMS = Host Controller Structural Parameters
  * This is a set of fields that are structural parameters: Number of downstream ports, etc.
  */
-union cvmx_uahcx_ehci_hcsparams
-{
+union cvmx_uahcx_ehci_hcsparams {
 	uint32_t u32;
-	struct cvmx_uahcx_ehci_hcsparams_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ehci_hcsparams_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_24_31               : 8;
 	uint32_t dpn                          : 4;  /**< Debug Port Number. Optional. This register identifies which of the host controller ports
                                                          is the debug port. The value is the port number (one-based) of the debug port. A nonzero
@@ -789,8 +969,13 @@ union cvmx_uahcx_ehci_hcsparams
 	uint32_t reserved_24_31               : 8;
 #endif
 	} s;
+	struct cvmx_uahcx_ehci_hcsparams_s    cn61xx;
 	struct cvmx_uahcx_ehci_hcsparams_s    cn63xx;
 	struct cvmx_uahcx_ehci_hcsparams_s    cn63xxp1;
+	struct cvmx_uahcx_ehci_hcsparams_s    cn66xx;
+	struct cvmx_uahcx_ehci_hcsparams_s    cn68xx;
+	struct cvmx_uahcx_ehci_hcsparams_s    cn68xxp1;
+	struct cvmx_uahcx_ehci_hcsparams_s    cnf71xx;
 };
 typedef union cvmx_uahcx_ehci_hcsparams cvmx_uahcx_ehci_hcsparams_t;
 
@@ -800,12 +985,10 @@ typedef union cvmx_uahcx_ehci_hcsparams cvmx_uahcx_ehci_hcsparams_t;
  * EHCI_INSNREG00 = EHCI Programmable Microframe Base Value Register (Synopsys Speicific)
  * This register allows you to change the microframe length value (default is microframe SOF = 125 s) to reduce the simulation time.
  */
-union cvmx_uahcx_ehci_insnreg00
-{
+union cvmx_uahcx_ehci_insnreg00 {
 	uint32_t u32;
-	struct cvmx_uahcx_ehci_insnreg00_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ehci_insnreg00_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_14_31               : 18;
 	uint32_t mfmc                         : 13; /**< For byte interface (8-bits), <13:1> is used as the 1-microframe counter.
                                                          For word interface (16_bits> <12:1> is used as the 1-microframe counter with word
@@ -818,8 +1001,13 @@ union cvmx_uahcx_ehci_insnreg00
 	uint32_t reserved_14_31               : 18;
 #endif
 	} s;
+	struct cvmx_uahcx_ehci_insnreg00_s    cn61xx;
 	struct cvmx_uahcx_ehci_insnreg00_s    cn63xx;
 	struct cvmx_uahcx_ehci_insnreg00_s    cn63xxp1;
+	struct cvmx_uahcx_ehci_insnreg00_s    cn66xx;
+	struct cvmx_uahcx_ehci_insnreg00_s    cn68xx;
+	struct cvmx_uahcx_ehci_insnreg00_s    cn68xxp1;
+	struct cvmx_uahcx_ehci_insnreg00_s    cnf71xx;
 };
 typedef union cvmx_uahcx_ehci_insnreg00 cvmx_uahcx_ehci_insnreg00_t;
 
@@ -829,12 +1017,10 @@ typedef union cvmx_uahcx_ehci_insnreg00 cvmx_uahcx_ehci_insnreg00_t;
  * EHCI_INSNREG03 = EHCI Timing Adjust Register (Synopsys Speicific)
  * This register allows you to change the timing of Phy Tx turnaround delay etc.
  */
-union cvmx_uahcx_ehci_insnreg03
-{
+union cvmx_uahcx_ehci_insnreg03 {
 	uint32_t u32;
-	struct cvmx_uahcx_ehci_insnreg03_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ehci_insnreg03_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_13_31               : 19;
 	uint32_t txtx_tadao                   : 3;  /**< Tx-Tx turnaround Delay Add on. This field specifies the extra delays in phy_clks to
                                                          be added to the "Transmit to Transmit turnaround delay" value maintained in the core.
@@ -862,8 +1048,13 @@ union cvmx_uahcx_ehci_insnreg03
 	uint32_t reserved_13_31               : 19;
 #endif
 	} s;
+	struct cvmx_uahcx_ehci_insnreg03_s    cn61xx;
 	struct cvmx_uahcx_ehci_insnreg03_s    cn63xx;
 	struct cvmx_uahcx_ehci_insnreg03_s    cn63xxp1;
+	struct cvmx_uahcx_ehci_insnreg03_s    cn66xx;
+	struct cvmx_uahcx_ehci_insnreg03_s    cn68xx;
+	struct cvmx_uahcx_ehci_insnreg03_s    cn68xxp1;
+	struct cvmx_uahcx_ehci_insnreg03_s    cnf71xx;
 };
 typedef union cvmx_uahcx_ehci_insnreg03 cvmx_uahcx_ehci_insnreg03_t;
 
@@ -873,12 +1064,10 @@ typedef union cvmx_uahcx_ehci_insnreg03 cvmx_uahcx_ehci_insnreg03_t;
  * EHCI_INSNREG04 = EHCI Debug Register (Synopsys Speicific)
  * This register is used only for debug purposes.
  */
-union cvmx_uahcx_ehci_insnreg04
-{
+union cvmx_uahcx_ehci_insnreg04 {
 	uint32_t u32;
-	struct cvmx_uahcx_ehci_insnreg04_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ehci_insnreg04_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_6_31                : 26;
 	uint32_t auto_dis                     : 1;  /**< Automatic feature disable.
                                                           1'b0: 0 by default, the automatic feature is enabled. The Suspend signal is deasserted
@@ -917,8 +1106,13 @@ union cvmx_uahcx_ehci_insnreg04
 	uint32_t reserved_6_31                : 26;
 #endif
 	} s;
+	struct cvmx_uahcx_ehci_insnreg04_s    cn61xx;
 	struct cvmx_uahcx_ehci_insnreg04_s    cn63xx;
 	struct cvmx_uahcx_ehci_insnreg04_s    cn63xxp1;
+	struct cvmx_uahcx_ehci_insnreg04_s    cn66xx;
+	struct cvmx_uahcx_ehci_insnreg04_s    cn68xx;
+	struct cvmx_uahcx_ehci_insnreg04_s    cn68xxp1;
+	struct cvmx_uahcx_ehci_insnreg04_s    cnf71xx;
 };
 typedef union cvmx_uahcx_ehci_insnreg04 cvmx_uahcx_ehci_insnreg04_t;
 
@@ -928,12 +1122,10 @@ typedef union cvmx_uahcx_ehci_insnreg04 cvmx_uahcx_ehci_insnreg04_t;
  * EHCI_INSNREG06 = EHCI  AHB Error Status Register (Synopsys Speicific)
  * This register contains AHB Error Status.
  */
-union cvmx_uahcx_ehci_insnreg06
-{
+union cvmx_uahcx_ehci_insnreg06 {
 	uint32_t u32;
-	struct cvmx_uahcx_ehci_insnreg06_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ehci_insnreg06_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t vld                          : 1;  /**< AHB Error Captured. Indicator that an AHB error was encountered and values were captured.
                                                          To clear this field the application must write a 0 to it. */
 	uint32_t reserved_0_30                : 31;
@@ -942,8 +1134,13 @@ union cvmx_uahcx_ehci_insnreg06
 	uint32_t vld                          : 1;
 #endif
 	} s;
+	struct cvmx_uahcx_ehci_insnreg06_s    cn61xx;
 	struct cvmx_uahcx_ehci_insnreg06_s    cn63xx;
 	struct cvmx_uahcx_ehci_insnreg06_s    cn63xxp1;
+	struct cvmx_uahcx_ehci_insnreg06_s    cn66xx;
+	struct cvmx_uahcx_ehci_insnreg06_s    cn68xx;
+	struct cvmx_uahcx_ehci_insnreg06_s    cn68xxp1;
+	struct cvmx_uahcx_ehci_insnreg06_s    cnf71xx;
 };
 typedef union cvmx_uahcx_ehci_insnreg06 cvmx_uahcx_ehci_insnreg06_t;
 
@@ -953,19 +1150,22 @@ typedef union cvmx_uahcx_ehci_insnreg06 cvmx_uahcx_ehci_insnreg06_t;
  * EHCI_INSNREG07 = EHCI  AHB Error Address Register (Synopsys Speicific)
  * This register contains AHB Error Status.
  */
-union cvmx_uahcx_ehci_insnreg07
-{
+union cvmx_uahcx_ehci_insnreg07 {
 	uint32_t u32;
-	struct cvmx_uahcx_ehci_insnreg07_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ehci_insnreg07_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t err_addr                     : 32; /**< AHB Master Error Address. AHB address of the control phase at which the AHB error occurred */
 #else
 	uint32_t err_addr                     : 32;
 #endif
 	} s;
+	struct cvmx_uahcx_ehci_insnreg07_s    cn61xx;
 	struct cvmx_uahcx_ehci_insnreg07_s    cn63xx;
 	struct cvmx_uahcx_ehci_insnreg07_s    cn63xxp1;
+	struct cvmx_uahcx_ehci_insnreg07_s    cn66xx;
+	struct cvmx_uahcx_ehci_insnreg07_s    cn68xx;
+	struct cvmx_uahcx_ehci_insnreg07_s    cn68xxp1;
+	struct cvmx_uahcx_ehci_insnreg07_s    cnf71xx;
 };
 typedef union cvmx_uahcx_ehci_insnreg07 cvmx_uahcx_ehci_insnreg07_t;
 
@@ -983,12 +1183,10 @@ typedef union cvmx_uahcx_ehci_insnreg07 cvmx_uahcx_ehci_insnreg07_t;
  * the Frame Index Register (FRINDEX) to enable the Host Controller to step through the Periodic Frame List
  * in sequence.
  */
-union cvmx_uahcx_ehci_periodiclistbase
-{
+union cvmx_uahcx_ehci_periodiclistbase {
 	uint32_t u32;
-	struct cvmx_uahcx_ehci_periodiclistbase_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ehci_periodiclistbase_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t baddr                        : 20; /**< Base Address (Low). These bits correspond to memory address signals [31:12],respectively. */
 	uint32_t reserved_0_11                : 12;
 #else
@@ -996,8 +1194,13 @@ union cvmx_uahcx_ehci_periodiclistbase
 	uint32_t baddr                        : 20;
 #endif
 	} s;
+	struct cvmx_uahcx_ehci_periodiclistbase_s cn61xx;
 	struct cvmx_uahcx_ehci_periodiclistbase_s cn63xx;
 	struct cvmx_uahcx_ehci_periodiclistbase_s cn63xxp1;
+	struct cvmx_uahcx_ehci_periodiclistbase_s cn66xx;
+	struct cvmx_uahcx_ehci_periodiclistbase_s cn68xx;
+	struct cvmx_uahcx_ehci_periodiclistbase_s cn68xxp1;
+	struct cvmx_uahcx_ehci_periodiclistbase_s cnf71xx;
 };
 typedef union cvmx_uahcx_ehci_periodiclistbase cvmx_uahcx_ehci_periodiclistbase_t;
 
@@ -1007,12 +1210,10 @@ typedef union cvmx_uahcx_ehci_periodiclistbase cvmx_uahcx_ehci_periodiclistbase_
  * PORTSCX = Port X Status and Control Register
  * Default: 00002000h (w/PPC set to one); 00003000h (w/PPC set to a zero)
  */
-union cvmx_uahcx_ehci_portscx
-{
+union cvmx_uahcx_ehci_portscx {
 	uint32_t u32;
-	struct cvmx_uahcx_ehci_portscx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ehci_portscx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_23_31               : 9;
 	uint32_t wkoc_e                       : 1;  /**< Wake on Over-current Enable.Writing this bit to a
                                                          one enables the port to be sensitive to over-current conditions as wake-up events.
@@ -1186,8 +1387,13 @@ union cvmx_uahcx_ehci_portscx
 	uint32_t reserved_23_31               : 9;
 #endif
 	} s;
+	struct cvmx_uahcx_ehci_portscx_s      cn61xx;
 	struct cvmx_uahcx_ehci_portscx_s      cn63xx;
 	struct cvmx_uahcx_ehci_portscx_s      cn63xxp1;
+	struct cvmx_uahcx_ehci_portscx_s      cn66xx;
+	struct cvmx_uahcx_ehci_portscx_s      cn68xx;
+	struct cvmx_uahcx_ehci_portscx_s      cn68xxp1;
+	struct cvmx_uahcx_ehci_portscx_s      cnf71xx;
 };
 typedef union cvmx_uahcx_ehci_portscx cvmx_uahcx_ehci_portscx_t;
 
@@ -1197,12 +1403,10 @@ typedef union cvmx_uahcx_ehci_portscx cvmx_uahcx_ehci_portscx_t;
  * USBCMD = USB Command Register
  * The Command Register indicates the command to be executed by the serial bus host controller. Writing to the register causes a command to be executed.
  */
-union cvmx_uahcx_ehci_usbcmd
-{
+union cvmx_uahcx_ehci_usbcmd {
 	uint32_t u32;
-	struct cvmx_uahcx_ehci_usbcmd_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ehci_usbcmd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_24_31               : 8;
 	uint32_t itc                          : 8;  /**< Interrupt Threshold Control. This field is used by system software
                                                          to select the maximum rate at which the host controller will issue interrupts. The only
@@ -1281,8 +1485,13 @@ union cvmx_uahcx_ehci_usbcmd
 	uint32_t reserved_24_31               : 8;
 #endif
 	} s;
+	struct cvmx_uahcx_ehci_usbcmd_s       cn61xx;
 	struct cvmx_uahcx_ehci_usbcmd_s       cn63xx;
 	struct cvmx_uahcx_ehci_usbcmd_s       cn63xxp1;
+	struct cvmx_uahcx_ehci_usbcmd_s       cn66xx;
+	struct cvmx_uahcx_ehci_usbcmd_s       cn68xx;
+	struct cvmx_uahcx_ehci_usbcmd_s       cn68xxp1;
+	struct cvmx_uahcx_ehci_usbcmd_s       cnf71xx;
 };
 typedef union cvmx_uahcx_ehci_usbcmd cvmx_uahcx_ehci_usbcmd_t;
 
@@ -1296,12 +1505,10 @@ typedef union cvmx_uahcx_ehci_usbcmd cvmx_uahcx_ehci_usbcmd_t;
  * Each interrupt enable bit description indicates whether it is dependent on the interrupt threshold mechanism.
  * Note: for all enable register bits, 1= Enabled, 0= Disabled
  */
-union cvmx_uahcx_ehci_usbintr
-{
+union cvmx_uahcx_ehci_usbintr {
 	uint32_t u32;
-	struct cvmx_uahcx_ehci_usbintr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ehci_usbintr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_6_31                : 26;
 	uint32_t ioaa_en                      : 1;  /**< Interrupt on Async Advance Enable When this bit is a one, and the Interrupt on
                                                          Async Advance bit in the USBSTS register is a one, the host controller will issue an
@@ -1332,8 +1539,13 @@ union cvmx_uahcx_ehci_usbintr
 	uint32_t reserved_6_31                : 26;
 #endif
 	} s;
+	struct cvmx_uahcx_ehci_usbintr_s      cn61xx;
 	struct cvmx_uahcx_ehci_usbintr_s      cn63xx;
 	struct cvmx_uahcx_ehci_usbintr_s      cn63xxp1;
+	struct cvmx_uahcx_ehci_usbintr_s      cn66xx;
+	struct cvmx_uahcx_ehci_usbintr_s      cn68xx;
+	struct cvmx_uahcx_ehci_usbintr_s      cn68xxp1;
+	struct cvmx_uahcx_ehci_usbintr_s      cnf71xx;
 };
 typedef union cvmx_uahcx_ehci_usbintr cvmx_uahcx_ehci_usbintr_t;
 
@@ -1345,12 +1557,10 @@ typedef union cvmx_uahcx_ehci_usbintr cvmx_uahcx_ehci_usbintr_t;
  * a transaction on the serial bus is not indicated in this register. Software sets a bit to 0 in this register by
  * writing a 1 to it.
  */
-union cvmx_uahcx_ehci_usbsts
-{
+union cvmx_uahcx_ehci_usbsts {
 	uint32_t u32;
-	struct cvmx_uahcx_ehci_usbsts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ehci_usbsts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_16_31               : 16;
 	uint32_t ass                          : 1;  /**< Asynchronous Schedule Status. The bit reports the current real
                                                          status of the Asynchronous Schedule. If this bit is a zero then the status of the
@@ -1416,8 +1626,13 @@ union cvmx_uahcx_ehci_usbsts
 	uint32_t reserved_16_31               : 16;
 #endif
 	} s;
+	struct cvmx_uahcx_ehci_usbsts_s       cn61xx;
 	struct cvmx_uahcx_ehci_usbsts_s       cn63xx;
 	struct cvmx_uahcx_ehci_usbsts_s       cn63xxp1;
+	struct cvmx_uahcx_ehci_usbsts_s       cn66xx;
+	struct cvmx_uahcx_ehci_usbsts_s       cn68xx;
+	struct cvmx_uahcx_ehci_usbsts_s       cn68xxp1;
+	struct cvmx_uahcx_ehci_usbsts_s       cnf71xx;
 };
 typedef union cvmx_uahcx_ehci_usbsts cvmx_uahcx_ehci_usbsts_t;
 
@@ -1429,12 +1644,10 @@ typedef union cvmx_uahcx_ehci_usbsts cvmx_uahcx_ehci_usbsts_t;
  * The HcBulkCurrentED register contains the physical address of the current endpoint of the Bulk list. As the Bulk list will be served in a round-robin
  * fashion, the endpoints will be ordered according to their insertion to the list.
  */
-union cvmx_uahcx_ohci0_hcbulkcurrented
-{
+union cvmx_uahcx_ohci0_hcbulkcurrented {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hcbulkcurrented_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hcbulkcurrented_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t bced                         : 28; /**< BulkCurrentED. This is advanced to the next ED after the HC has served the
                                                          present one. HC continues processing the list from where it left off in the
                                                          last Frame. When it reaches the end of the Bulk list, HC checks the
@@ -1450,8 +1663,13 @@ union cvmx_uahcx_ohci0_hcbulkcurrented
 	uint32_t bced                         : 28;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn61xx;
 	struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn63xx;
 	struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn63xxp1;
+	struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn66xx;
+	struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn68xx;
+	struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn68xxp1;
+	struct cvmx_uahcx_ohci0_hcbulkcurrented_s cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hcbulkcurrented cvmx_uahcx_ohci0_hcbulkcurrented_t;
 
@@ -1462,12 +1680,10 @@ typedef union cvmx_uahcx_ohci0_hcbulkcurrented cvmx_uahcx_ohci0_hcbulkcurrented_
  *
  * The HcBulkHeadED register contains the physical address of the first Endpoint Descriptor of the Bulk list.
  */
-union cvmx_uahcx_ohci0_hcbulkheaded
-{
+union cvmx_uahcx_ohci0_hcbulkheaded {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hcbulkheaded_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hcbulkheaded_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t bhed                         : 28; /**< BulkHeadED. HC traverses the Bulk list starting with the HcBulkHeadED
                                                          pointer. The content is loaded from HCCA during the initialization of HC. */
 	uint32_t reserved_0_3                 : 4;
@@ -1476,8 +1692,13 @@ union cvmx_uahcx_ohci0_hcbulkheaded
 	uint32_t bhed                         : 28;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hcbulkheaded_s cn61xx;
 	struct cvmx_uahcx_ohci0_hcbulkheaded_s cn63xx;
 	struct cvmx_uahcx_ohci0_hcbulkheaded_s cn63xxp1;
+	struct cvmx_uahcx_ohci0_hcbulkheaded_s cn66xx;
+	struct cvmx_uahcx_ohci0_hcbulkheaded_s cn68xx;
+	struct cvmx_uahcx_ohci0_hcbulkheaded_s cn68xxp1;
+	struct cvmx_uahcx_ohci0_hcbulkheaded_s cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hcbulkheaded cvmx_uahcx_ohci0_hcbulkheaded_t;
 
@@ -1495,12 +1716,10 @@ typedef union cvmx_uahcx_ohci0_hcbulkheaded cvmx_uahcx_ohci0_hcbulkheaded_t;
  * occurs when the Periodic list does not complete before EOF. When a scheduling overrun error is detected, the Host Controller increments the counter
  * and sets the SchedulingOverrun field in the HcInterruptStatus register.
  */
-union cvmx_uahcx_ohci0_hccommandstatus
-{
+union cvmx_uahcx_ohci0_hccommandstatus {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hccommandstatus_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hccommandstatus_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_18_31               : 14;
 	uint32_t soc                          : 2;  /**< SchedulingOverrunCount. These bits are incremented on each scheduling overrun
                                                          error. It is initialized to 00b and wraps around at 11b. This will be
@@ -1550,8 +1769,13 @@ union cvmx_uahcx_ohci0_hccommandstatus
 	uint32_t reserved_18_31               : 14;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hccommandstatus_s cn61xx;
 	struct cvmx_uahcx_ohci0_hccommandstatus_s cn63xx;
 	struct cvmx_uahcx_ohci0_hccommandstatus_s cn63xxp1;
+	struct cvmx_uahcx_ohci0_hccommandstatus_s cn66xx;
+	struct cvmx_uahcx_ohci0_hccommandstatus_s cn68xx;
+	struct cvmx_uahcx_ohci0_hccommandstatus_s cn68xxp1;
+	struct cvmx_uahcx_ohci0_hccommandstatus_s cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hccommandstatus cvmx_uahcx_ohci0_hccommandstatus_t;
 
@@ -1563,12 +1787,10 @@ typedef union cvmx_uahcx_ohci0_hccommandstatus cvmx_uahcx_ohci0_hccommandstatus_
  * The HcControl register defines the operating modes for the Host Controller. Most of the fields in this register are modified only by the Host Controller
  * Driver, except HostControllerFunctionalState and RemoteWakeupConnected.
  */
-union cvmx_uahcx_ohci0_hccontrol
-{
+union cvmx_uahcx_ohci0_hccontrol {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hccontrol_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hccontrol_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_11_31               : 21;
 	uint32_t rwe                          : 1;  /**< RemoteWakeupEnable. This bit is used by HCD to enable or disable the remote wakeup
                                                          feature upon the detection of upstream resume signaling. When this bit is set and
@@ -1650,8 +1872,13 @@ union cvmx_uahcx_ohci0_hccontrol
 	uint32_t reserved_11_31               : 21;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hccontrol_s   cn61xx;
 	struct cvmx_uahcx_ohci0_hccontrol_s   cn63xx;
 	struct cvmx_uahcx_ohci0_hccontrol_s   cn63xxp1;
+	struct cvmx_uahcx_ohci0_hccontrol_s   cn66xx;
+	struct cvmx_uahcx_ohci0_hccontrol_s   cn68xx;
+	struct cvmx_uahcx_ohci0_hccontrol_s   cn68xxp1;
+	struct cvmx_uahcx_ohci0_hccontrol_s   cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hccontrol cvmx_uahcx_ohci0_hccontrol_t;
 
@@ -1662,12 +1889,10 @@ typedef union cvmx_uahcx_ohci0_hccontrol cvmx_uahcx_ohci0_hccontrol_t;
  *
  * The HcControlCurrentED register contains the physical address of the current Endpoint Descriptor of the Control list.
  */
-union cvmx_uahcx_ohci0_hccontrolcurrented
-{
+union cvmx_uahcx_ohci0_hccontrolcurrented {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hccontrolcurrented_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hccontrolcurrented_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t cced                         : 28; /**< ControlCurrentED. This pointer is advanced to the next ED after serving the
                                                          present one. HC will continue processing the list from where it left off in
                                                          the last Frame. When it reaches the end of the Control list, HC checks the
@@ -1683,8 +1908,13 @@ union cvmx_uahcx_ohci0_hccontrolcurrented
 	uint32_t cced                         : 28;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn61xx;
 	struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn63xx;
 	struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn63xxp1;
+	struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn66xx;
+	struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn68xx;
+	struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn68xxp1;
+	struct cvmx_uahcx_ohci0_hccontrolcurrented_s cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hccontrolcurrented cvmx_uahcx_ohci0_hccontrolcurrented_t;
 
@@ -1695,12 +1925,10 @@ typedef union cvmx_uahcx_ohci0_hccontrolcurrented cvmx_uahcx_ohci0_hccontrolcurr
  *
  * The HcControlHeadED register contains the physical address of the first Endpoint Descriptor of the Control list.
  */
-union cvmx_uahcx_ohci0_hccontrolheaded
-{
+union cvmx_uahcx_ohci0_hccontrolheaded {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hccontrolheaded_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hccontrolheaded_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ched                         : 28; /**< ControlHeadED. HC traverses the Control list starting with the HcControlHeadED
                                                          pointer. The content is loaded from HCCA during the initialization of HC. */
 	uint32_t reserved_0_3                 : 4;
@@ -1709,8 +1937,13 @@ union cvmx_uahcx_ohci0_hccontrolheaded
 	uint32_t ched                         : 28;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hccontrolheaded_s cn61xx;
 	struct cvmx_uahcx_ohci0_hccontrolheaded_s cn63xx;
 	struct cvmx_uahcx_ohci0_hccontrolheaded_s cn63xxp1;
+	struct cvmx_uahcx_ohci0_hccontrolheaded_s cn66xx;
+	struct cvmx_uahcx_ohci0_hccontrolheaded_s cn68xx;
+	struct cvmx_uahcx_ohci0_hccontrolheaded_s cn68xxp1;
+	struct cvmx_uahcx_ohci0_hccontrolheaded_s cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hccontrolheaded cvmx_uahcx_ohci0_hccontrolheaded_t;
 
@@ -1722,12 +1955,10 @@ typedef union cvmx_uahcx_ohci0_hccontrolheaded cvmx_uahcx_ohci0_hccontrolheaded_
  * The HcDoneHead register contains the physical address of the last completed Transfer Descriptor that was added to the Done queue. In normal operation,
  * the Host Controller Driver should not need to read this register as its content is periodically written to the HCCA.
  */
-union cvmx_uahcx_ohci0_hcdonehead
-{
+union cvmx_uahcx_ohci0_hcdonehead {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hcdonehead_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hcdonehead_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dh                           : 28; /**< DoneHead. When a TD is completed, HC writes the content of HcDoneHead to the
                                                          NextTD field of the TD. HC then overwrites the content of HcDoneHead with the
                                                          address of this TD. This is set to zero whenever HC writes the content of
@@ -1738,8 +1969,13 @@ union cvmx_uahcx_ohci0_hcdonehead
 	uint32_t dh                           : 28;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hcdonehead_s  cn61xx;
 	struct cvmx_uahcx_ohci0_hcdonehead_s  cn63xx;
 	struct cvmx_uahcx_ohci0_hcdonehead_s  cn63xxp1;
+	struct cvmx_uahcx_ohci0_hcdonehead_s  cn66xx;
+	struct cvmx_uahcx_ohci0_hcdonehead_s  cn68xx;
+	struct cvmx_uahcx_ohci0_hcdonehead_s  cn68xxp1;
+	struct cvmx_uahcx_ohci0_hcdonehead_s  cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hcdonehead cvmx_uahcx_ohci0_hcdonehead_t;
 
@@ -1753,12 +1989,10 @@ typedef union cvmx_uahcx_ohci0_hcdonehead cvmx_uahcx_ohci0_hcdonehead_t;
  * may carry out minor adjustment on the FrameInterval by writing a new value over the present one at each SOF. This provides the programmability necessary for
  * the Host Controller to synchronize with an external clocking resource and to adjust any unknown local clock offset.
  */
-union cvmx_uahcx_ohci0_hcfminterval
-{
+union cvmx_uahcx_ohci0_hcfminterval {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hcfminterval_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hcfminterval_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t fit                          : 1;  /**< FrameIntervalToggle. HCD toggles this bit whenever it loads a new value to
                                                          FrameInterval. */
 	uint32_t fsmps                        : 15; /**< FSLargestDataPacket. This field specifies a value which is loaded into the
@@ -1780,8 +2014,13 @@ union cvmx_uahcx_ohci0_hcfminterval
 	uint32_t fit                          : 1;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hcfminterval_s cn61xx;
 	struct cvmx_uahcx_ohci0_hcfminterval_s cn63xx;
 	struct cvmx_uahcx_ohci0_hcfminterval_s cn63xxp1;
+	struct cvmx_uahcx_ohci0_hcfminterval_s cn66xx;
+	struct cvmx_uahcx_ohci0_hcfminterval_s cn68xx;
+	struct cvmx_uahcx_ohci0_hcfminterval_s cn68xxp1;
+	struct cvmx_uahcx_ohci0_hcfminterval_s cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hcfminterval cvmx_uahcx_ohci0_hcfminterval_t;
 
@@ -1794,12 +2033,10 @@ typedef union cvmx_uahcx_ohci0_hcfminterval cvmx_uahcx_ohci0_hcfminterval_t;
  * The Host Controller Driver may use the 16-bit value specified in this register and generate a 32-bit frame number without requiring frequent access to
  * the register.
  */
-union cvmx_uahcx_ohci0_hcfmnumber
-{
+union cvmx_uahcx_ohci0_hcfmnumber {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hcfmnumber_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hcfmnumber_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_16_31               : 16;
 	uint32_t fn                           : 16; /**< FrameNumber. This is incremented when HcFmRemaining is re-loaded. It will be
                                                          rolled over to 0h after ffffh. When entering the USBOPERATIONAL state,
@@ -1812,8 +2049,13 @@ union cvmx_uahcx_ohci0_hcfmnumber
 	uint32_t reserved_16_31               : 16;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hcfmnumber_s  cn61xx;
 	struct cvmx_uahcx_ohci0_hcfmnumber_s  cn63xx;
 	struct cvmx_uahcx_ohci0_hcfmnumber_s  cn63xxp1;
+	struct cvmx_uahcx_ohci0_hcfmnumber_s  cn66xx;
+	struct cvmx_uahcx_ohci0_hcfmnumber_s  cn68xx;
+	struct cvmx_uahcx_ohci0_hcfmnumber_s  cn68xxp1;
+	struct cvmx_uahcx_ohci0_hcfmnumber_s  cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hcfmnumber cvmx_uahcx_ohci0_hcfmnumber_t;
 
@@ -1823,12 +2065,10 @@ typedef union cvmx_uahcx_ohci0_hcfmnumber cvmx_uahcx_ohci0_hcfmnumber_t;
  * HCFMREMAINING = Host Controller Frame Remaining Register
  * The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current Frame.
  */
-union cvmx_uahcx_ohci0_hcfmremaining
-{
+union cvmx_uahcx_ohci0_hcfmremaining {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hcfmremaining_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hcfmremaining_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t frt                          : 1;  /**< FrameRemainingToggle. This bit is loaded from the FrameIntervalToggle field
                                                          of HcFmInterval whenever FrameRemaining reaches 0. This bit is used by HCD
                                                          for the synchronization between FrameInterval and FrameRemaining. */
@@ -1844,8 +2084,13 @@ union cvmx_uahcx_ohci0_hcfmremaining
 	uint32_t frt                          : 1;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hcfmremaining_s cn61xx;
 	struct cvmx_uahcx_ohci0_hcfmremaining_s cn63xx;
 	struct cvmx_uahcx_ohci0_hcfmremaining_s cn63xxp1;
+	struct cvmx_uahcx_ohci0_hcfmremaining_s cn66xx;
+	struct cvmx_uahcx_ohci0_hcfmremaining_s cn68xx;
+	struct cvmx_uahcx_ohci0_hcfmremaining_s cn68xxp1;
+	struct cvmx_uahcx_ohci0_hcfmremaining_s cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hcfmremaining cvmx_uahcx_ohci0_hcfmremaining_t;
 
@@ -1859,12 +2104,10 @@ typedef union cvmx_uahcx_ohci0_hcfmremaining cvmx_uahcx_ohci0_hcfmremaining_t;
  * minimum alignment is 256 bytes; therefore, bits 0 through 7 must always return '0' when read. Detailed description can be found in Chapter 4. This area
  * is used to hold the control structures and the Interrupt table that are accessed by both the Host Controller and the Host Controller Driver.
  */
-union cvmx_uahcx_ohci0_hchcca
-{
+union cvmx_uahcx_ohci0_hchcca {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hchcca_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hchcca_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t hcca                         : 24; /**< This is the base address (bits [31:8]) of the Host Controller Communication Area. */
 	uint32_t reserved_0_7                 : 8;
 #else
@@ -1872,8 +2115,13 @@ union cvmx_uahcx_ohci0_hchcca
 	uint32_t hcca                         : 24;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hchcca_s      cn61xx;
 	struct cvmx_uahcx_ohci0_hchcca_s      cn63xx;
 	struct cvmx_uahcx_ohci0_hchcca_s      cn63xxp1;
+	struct cvmx_uahcx_ohci0_hchcca_s      cn66xx;
+	struct cvmx_uahcx_ohci0_hchcca_s      cn68xx;
+	struct cvmx_uahcx_ohci0_hchcca_s      cn68xxp1;
+	struct cvmx_uahcx_ohci0_hchcca_s      cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hchcca cvmx_uahcx_ohci0_hchcca_t;
 
@@ -1887,12 +2135,10 @@ typedef union cvmx_uahcx_ohci0_hchcca cvmx_uahcx_ohci0_hchcca_t;
  * register, whereas writing a '0' to a bit in this register leaves the corresponding bit in the HcInterruptEnable register unchanged. On read, the current
  * value of the HcInterruptEnable register is returned.
  */
-union cvmx_uahcx_ohci0_hcinterruptdisable
-{
+union cvmx_uahcx_ohci0_hcinterruptdisable {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hcinterruptdisable_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hcinterruptdisable_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t mie                          : 1;  /**< A '0' written to this field is ignored by HC.
                                                          A '1' written to this field disables interrupt generation due to events
                                                          specified in the other bits of this register. This field is set after a
@@ -1919,8 +2165,13 @@ union cvmx_uahcx_ohci0_hcinterruptdisable
 	uint32_t mie                          : 1;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn61xx;
 	struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn63xx;
 	struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn63xxp1;
+	struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn66xx;
+	struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn68xx;
+	struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn68xxp1;
+	struct cvmx_uahcx_ohci0_hcinterruptdisable_s cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hcinterruptdisable cvmx_uahcx_ohci0_hcinterruptdisable_t;
 
@@ -1935,12 +2186,10 @@ typedef union cvmx_uahcx_ohci0_hcinterruptdisable cvmx_uahcx_ohci0_hcinterruptdi
  * Writing a '1' to a bit in this register sets the corresponding bit, whereas writing a '0' to a bit in this register leaves the corresponding bit
  * unchanged. On read, the current value of this register is returned.
  */
-union cvmx_uahcx_ohci0_hcinterruptenable
-{
+union cvmx_uahcx_ohci0_hcinterruptenable {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hcinterruptenable_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hcinterruptenable_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t mie                          : 1;  /**< A '0' written to this field is ignored by HC.
                                                          A '1' written to this field enables interrupt generation due to events
                                                          specified in the other bits of this register. This is used by HCD as a Master
@@ -1967,8 +2216,13 @@ union cvmx_uahcx_ohci0_hcinterruptenable
 	uint32_t mie                          : 1;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hcinterruptenable_s cn61xx;
 	struct cvmx_uahcx_ohci0_hcinterruptenable_s cn63xx;
 	struct cvmx_uahcx_ohci0_hcinterruptenable_s cn63xxp1;
+	struct cvmx_uahcx_ohci0_hcinterruptenable_s cn66xx;
+	struct cvmx_uahcx_ohci0_hcinterruptenable_s cn68xx;
+	struct cvmx_uahcx_ohci0_hcinterruptenable_s cn68xxp1;
+	struct cvmx_uahcx_ohci0_hcinterruptenable_s cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hcinterruptenable cvmx_uahcx_ohci0_hcinterruptenable_t;
 
@@ -1982,12 +2236,10 @@ typedef union cvmx_uahcx_ohci0_hcinterruptenable cvmx_uahcx_ohci0_hcinterruptena
  * and the MasterInterruptEnable bit is set. The Host Controller Driver may clear specific bits in this register by writing '1' to bit positions
  * to be cleared. The Host Controller Driver may not set any of these bits. The Host Controller will never clear the bit.
  */
-union cvmx_uahcx_ohci0_hcinterruptstatus
-{
+union cvmx_uahcx_ohci0_hcinterruptstatus {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hcinterruptstatus_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hcinterruptstatus_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_31_31               : 1;
 	uint32_t oc                           : 1;  /**< OwnershipChange. This bit is set by HC when HCD sets the OwnershipChangeRequest
                                                          field in HcCommandStatus. This event, when unmasked, will always generate an
@@ -2029,8 +2281,13 @@ union cvmx_uahcx_ohci0_hcinterruptstatus
 	uint32_t reserved_31_31               : 1;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn61xx;
 	struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn63xx;
 	struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn63xxp1;
+	struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn66xx;
+	struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn68xx;
+	struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn68xxp1;
+	struct cvmx_uahcx_ohci0_hcinterruptstatus_s cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hcinterruptstatus cvmx_uahcx_ohci0_hcinterruptstatus_t;
 
@@ -2042,12 +2299,10 @@ typedef union cvmx_uahcx_ohci0_hcinterruptstatus cvmx_uahcx_ohci0_hcinterruptsta
  * The HcLSThreshold register contains an 11-bit value used by the Host Controller to determine whether to commit to the transfer of a maximum of 8-byte
  * LS packet before EOF. Neither the Host Controller nor the Host Controller Driver are allowed to change this value.
  */
-union cvmx_uahcx_ohci0_hclsthreshold
-{
+union cvmx_uahcx_ohci0_hclsthreshold {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hclsthreshold_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hclsthreshold_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_12_31               : 20;
 	uint32_t lst                          : 12; /**< LSThreshold
                                                          This field contains a value which is compared to the FrameRemaining field
@@ -2059,8 +2314,13 @@ union cvmx_uahcx_ohci0_hclsthreshold
 	uint32_t reserved_12_31               : 20;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hclsthreshold_s cn61xx;
 	struct cvmx_uahcx_ohci0_hclsthreshold_s cn63xx;
 	struct cvmx_uahcx_ohci0_hclsthreshold_s cn63xxp1;
+	struct cvmx_uahcx_ohci0_hclsthreshold_s cn66xx;
+	struct cvmx_uahcx_ohci0_hclsthreshold_s cn68xx;
+	struct cvmx_uahcx_ohci0_hclsthreshold_s cn68xxp1;
+	struct cvmx_uahcx_ohci0_hclsthreshold_s cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hclsthreshold cvmx_uahcx_ohci0_hclsthreshold_t;
 
@@ -2071,12 +2331,10 @@ typedef union cvmx_uahcx_ohci0_hclsthreshold cvmx_uahcx_ohci0_hclsthreshold_t;
  *
  * The HcPeriodCurrentED register contains the physical address of the current Isochronous or Interrupt Endpoint Descriptor.
  */
-union cvmx_uahcx_ohci0_hcperiodcurrented
-{
+union cvmx_uahcx_ohci0_hcperiodcurrented {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hcperiodcurrented_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hcperiodcurrented_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t pced                         : 28; /**< PeriodCurrentED. This is used by HC to point to the head of one of the
                                                          Periodic lists which will be processed in the current Frame. The content of
                                                          this register is updated by HC after a periodic ED has been processed. HCD
@@ -2088,8 +2346,13 @@ union cvmx_uahcx_ohci0_hcperiodcurrented
 	uint32_t pced                         : 28;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn61xx;
 	struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn63xx;
 	struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn63xxp1;
+	struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn66xx;
+	struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn68xx;
+	struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn68xxp1;
+	struct cvmx_uahcx_ohci0_hcperiodcurrented_s cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hcperiodcurrented cvmx_uahcx_ohci0_hcperiodcurrented_t;
 
@@ -2100,12 +2363,10 @@ typedef union cvmx_uahcx_ohci0_hcperiodcurrented cvmx_uahcx_ohci0_hcperiodcurren
  *
  * The HcPeriodicStart register has a 14-bit programmable value which determines when is the earliest time HC should start processing the periodic list.
  */
-union cvmx_uahcx_ohci0_hcperiodicstart
-{
+union cvmx_uahcx_ohci0_hcperiodicstart {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hcperiodicstart_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hcperiodicstart_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_14_31               : 18;
 	uint32_t ps                           : 14; /**< PeriodicStart After a hardware reset, this field is cleared. This is then set
                                                          by HCD during the HC initialization. The value is calculated roughly as 10%
@@ -2119,8 +2380,13 @@ union cvmx_uahcx_ohci0_hcperiodicstart
 	uint32_t reserved_14_31               : 18;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hcperiodicstart_s cn61xx;
 	struct cvmx_uahcx_ohci0_hcperiodicstart_s cn63xx;
 	struct cvmx_uahcx_ohci0_hcperiodicstart_s cn63xxp1;
+	struct cvmx_uahcx_ohci0_hcperiodicstart_s cn66xx;
+	struct cvmx_uahcx_ohci0_hcperiodicstart_s cn68xx;
+	struct cvmx_uahcx_ohci0_hcperiodicstart_s cn68xxp1;
+	struct cvmx_uahcx_ohci0_hcperiodicstart_s cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hcperiodicstart cvmx_uahcx_ohci0_hcperiodicstart_t;
 
@@ -2130,12 +2396,10 @@ typedef union cvmx_uahcx_ohci0_hcperiodicstart cvmx_uahcx_ohci0_hcperiodicstart_
  * HCREVISION = Host Controller Revision Register
  *
  */
-union cvmx_uahcx_ohci0_hcrevision
-{
+union cvmx_uahcx_ohci0_hcrevision {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hcrevision_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hcrevision_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_8_31                : 24;
 	uint32_t rev                          : 8;  /**< Revision This read-only field contains the BCD representation of the version
                                                          of the HCI specification that is implemented by this HC. For example, a value
@@ -2146,8 +2410,13 @@ union cvmx_uahcx_ohci0_hcrevision
 	uint32_t reserved_8_31                : 24;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hcrevision_s  cn61xx;
 	struct cvmx_uahcx_ohci0_hcrevision_s  cn63xx;
 	struct cvmx_uahcx_ohci0_hcrevision_s  cn63xxp1;
+	struct cvmx_uahcx_ohci0_hcrevision_s  cn66xx;
+	struct cvmx_uahcx_ohci0_hcrevision_s  cn68xx;
+	struct cvmx_uahcx_ohci0_hcrevision_s  cn68xxp1;
+	struct cvmx_uahcx_ohci0_hcrevision_s  cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hcrevision cvmx_uahcx_ohci0_hcrevision_t;
 
@@ -2157,15 +2426,13 @@ typedef union cvmx_uahcx_ohci0_hcrevision cvmx_uahcx_ohci0_hcrevision_t;
  * HCRHDESCRIPTORA = Host Controller Root Hub DescriptorA Register
  *
  * The HcRhDescriptorA register is the first register of two describing the characteristics of the Root Hub. Reset values are implementation-specific.
- * The descriptor length (11), descriptor type (TBD), and hub controller current (0) fields of the hub Class Descriptor are emulated by the HCD. All
+ * The descriptor length (11), descriptor type (0x29), and hub controller current (0) fields of the hub Class Descriptor are emulated by the HCD. All
  * other fields are located in the HcRhDescriptorA and HcRhDescriptorB registers.
  */
-union cvmx_uahcx_ohci0_hcrhdescriptora
-{
+union cvmx_uahcx_ohci0_hcrhdescriptora {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hcrhdescriptora_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hcrhdescriptora_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t potpgt                       : 8;  /**< PowerOnToPowerGoodTime. This byte specifies the duration HCD has to wait before
                                                          accessing a powered-on port of the Root Hub. It is implementation-specific. The
                                                          unit of time is 2 ms. The duration is calculated as POTPGT * 2 ms. */
@@ -2213,8 +2480,13 @@ union cvmx_uahcx_ohci0_hcrhdescriptora
 	uint32_t potpgt                       : 8;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn61xx;
 	struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn63xx;
 	struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn63xxp1;
+	struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn66xx;
+	struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn68xx;
+	struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn68xxp1;
+	struct cvmx_uahcx_ohci0_hcrhdescriptora_s cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hcrhdescriptora cvmx_uahcx_ohci0_hcrhdescriptora_t;
 
@@ -2226,12 +2498,10 @@ typedef union cvmx_uahcx_ohci0_hcrhdescriptora cvmx_uahcx_ohci0_hcrhdescriptora_
  * The HcRhDescriptorB register is the second register of two describing the characteristics of the Root Hub. These fields are written during
  * initialization to correspond with the system implementation. Reset values are implementation-specific.
  */
-union cvmx_uahcx_ohci0_hcrhdescriptorb
-{
+union cvmx_uahcx_ohci0_hcrhdescriptorb {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hcrhdescriptorb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hcrhdescriptorb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ppcm                         : 16; /**< PortPowerControlMask.
                                                          Each bit indicates if a port is affected by a global power control command
                                                          when PowerSwitchingMode is set. When set, the port's power state is only
@@ -2257,8 +2527,13 @@ union cvmx_uahcx_ohci0_hcrhdescriptorb
 	uint32_t ppcm                         : 16;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn61xx;
 	struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn63xx;
 	struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn63xxp1;
+	struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn66xx;
+	struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn68xx;
+	struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn68xxp1;
+	struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hcrhdescriptorb cvmx_uahcx_ohci0_hcrhdescriptorb_t;
 
@@ -2273,12 +2548,10 @@ typedef union cvmx_uahcx_ohci0_hcrhdescriptorb cvmx_uahcx_ohci0_hcrhdescriptorb_
  * in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completes.
  * Reserved bits should always be written '0'.
  */
-union cvmx_uahcx_ohci0_hcrhportstatusx
-{
+union cvmx_uahcx_ohci0_hcrhportstatusx {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hcrhportstatusx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hcrhportstatusx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_21_31               : 11;
 	uint32_t prsc                         : 1;  /**< PortResetStatusChange. This bit is set at the end of the 10-ms port reset
                                                          signal. The HCD writes a '1' to clear this bit. Writing a '0' has no effect.
@@ -2419,8 +2692,13 @@ union cvmx_uahcx_ohci0_hcrhportstatusx
 	uint32_t reserved_21_31               : 11;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn61xx;
 	struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn63xx;
 	struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn63xxp1;
+	struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn66xx;
+	struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn68xx;
+	struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn68xxp1;
+	struct cvmx_uahcx_ohci0_hcrhportstatusx_s cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hcrhportstatusx cvmx_uahcx_ohci0_hcrhportstatusx_t;
 
@@ -2432,12 +2710,10 @@ typedef union cvmx_uahcx_ohci0_hcrhportstatusx cvmx_uahcx_ohci0_hcrhportstatusx_
  * The HcRhStatus register is divided into two parts. The lower word of a Dword represents the Hub Status field and the upper word represents the Hub
  * Status Change field. Reserved bits should always be written '0'.
  */
-union cvmx_uahcx_ohci0_hcrhstatus
-{
+union cvmx_uahcx_ohci0_hcrhstatus {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_hcrhstatus_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_hcrhstatus_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t crwe                         : 1;  /**< (write) ClearRemoteWakeupEnable Writing a '1' clears DeviceRemoveWakeupEnable.
                                                          Writing a '0' has no effect. */
 	uint32_t reserved_18_30               : 13;
@@ -2479,8 +2755,13 @@ union cvmx_uahcx_ohci0_hcrhstatus
 	uint32_t crwe                         : 1;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_hcrhstatus_s  cn61xx;
 	struct cvmx_uahcx_ohci0_hcrhstatus_s  cn63xx;
 	struct cvmx_uahcx_ohci0_hcrhstatus_s  cn63xxp1;
+	struct cvmx_uahcx_ohci0_hcrhstatus_s  cn66xx;
+	struct cvmx_uahcx_ohci0_hcrhstatus_s  cn68xx;
+	struct cvmx_uahcx_ohci0_hcrhstatus_s  cn68xxp1;
+	struct cvmx_uahcx_ohci0_hcrhstatus_s  cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_hcrhstatus cvmx_uahcx_ohci0_hcrhstatus_t;
 
@@ -2491,12 +2772,10 @@ typedef union cvmx_uahcx_ohci0_hcrhstatus cvmx_uahcx_ohci0_hcrhstatus_t;
  *
  * This register contains AHB Error Status.
  */
-union cvmx_uahcx_ohci0_insnreg06
-{
+union cvmx_uahcx_ohci0_insnreg06 {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_insnreg06_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_insnreg06_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t vld                          : 1;  /**< AHB Error Captured. Indicator that an AHB error was encountered and values were captured.
                                                          To clear this field the application must write a 0 to it. */
 	uint32_t reserved_0_30                : 31;
@@ -2505,8 +2784,13 @@ union cvmx_uahcx_ohci0_insnreg06
 	uint32_t vld                          : 1;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_insnreg06_s   cn61xx;
 	struct cvmx_uahcx_ohci0_insnreg06_s   cn63xx;
 	struct cvmx_uahcx_ohci0_insnreg06_s   cn63xxp1;
+	struct cvmx_uahcx_ohci0_insnreg06_s   cn66xx;
+	struct cvmx_uahcx_ohci0_insnreg06_s   cn68xx;
+	struct cvmx_uahcx_ohci0_insnreg06_s   cn68xxp1;
+	struct cvmx_uahcx_ohci0_insnreg06_s   cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_insnreg06 cvmx_uahcx_ohci0_insnreg06_t;
 
@@ -2517,19 +2801,22 @@ typedef union cvmx_uahcx_ohci0_insnreg06 cvmx_uahcx_ohci0_insnreg06_t;
  *
  * This register contains AHB Error Status.
  */
-union cvmx_uahcx_ohci0_insnreg07
-{
+union cvmx_uahcx_ohci0_insnreg07 {
 	uint32_t u32;
-	struct cvmx_uahcx_ohci0_insnreg07_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uahcx_ohci0_insnreg07_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t err_addr                     : 32; /**< AHB Master Error Address. AHB address of the control phase at which the AHB error occurred */
 #else
 	uint32_t err_addr                     : 32;
 #endif
 	} s;
+	struct cvmx_uahcx_ohci0_insnreg07_s   cn61xx;
 	struct cvmx_uahcx_ohci0_insnreg07_s   cn63xx;
 	struct cvmx_uahcx_ohci0_insnreg07_s   cn63xxp1;
+	struct cvmx_uahcx_ohci0_insnreg07_s   cn66xx;
+	struct cvmx_uahcx_ohci0_insnreg07_s   cn68xx;
+	struct cvmx_uahcx_ohci0_insnreg07_s   cn68xxp1;
+	struct cvmx_uahcx_ohci0_insnreg07_s   cnf71xx;
 };
 typedef union cvmx_uahcx_ohci0_insnreg07 cvmx_uahcx_ohci0_insnreg07_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-uart.c b/sys/contrib/octeon-sdk/cvmx-uart.c
index aead3e1..cf9d8f6 100644
--- a/sys/contrib/octeon-sdk/cvmx-uart.c
+++ b/sys/contrib/octeon-sdk/cvmx-uart.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -44,13 +44,12 @@
 #include <asm/octeon/cvmx-clock.h>
 #include <asm/octeon/cvmx-uart.h>
 #else
-#include "executive-config.h"
 #include "cvmx.h"
 #include "cvmx-uart.h"
 #include "cvmx-interrupt.h"
 #endif
 
-#ifndef __OCTEON_NEWLIB__
+#ifndef CVMX_BUILD_FOR_TOOLCHAIN
 void cvmx_uart_enable_intr(int uart, cvmx_uart_intr_handler_t handler)
 {
 #ifndef CVMX_BUILD_FOR_LINUX_KERNEL
@@ -69,7 +68,7 @@ void cvmx_uart_enable_intr(int uart, cvmx_uart_intr_handler_t handler)
 
 static int cvmx_uart_simulator_p(void)
 {
-#ifndef __OCTEON_NEWLIB__
+#ifndef CVMX_BUILD_FOR_TOOLCHAIN
   return cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM;
 #else
   extern int __octeon_simulator_p;
diff --git a/sys/contrib/octeon-sdk/cvmx-uart.h b/sys/contrib/octeon-sdk/cvmx-uart.h
index cb05d11..dafd8b4 100644
--- a/sys/contrib/octeon-sdk/cvmx-uart.h
+++ b/sys/contrib/octeon-sdk/cvmx-uart.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * interface to the serial port UART hardware
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-uctlx-defs.h b/sys/contrib/octeon-sdk/cvmx-uctlx-defs.h
index c864c82..c6635b3 100644
--- a/sys/contrib/octeon-sdk/cvmx-uctlx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-uctlx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,18 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_UCTLX_TYPEDEFS_H__
-#define __CVMX_UCTLX_TYPEDEFS_H__
+#ifndef __CVMX_UCTLX_DEFS_H__
+#define __CVMX_UCTLX_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_UCTLX_BIST_STATUS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UCTLX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x000118006F0000A0ull);
 }
@@ -67,7 +71,11 @@ static inline uint64_t CVMX_UCTLX_BIST_STATUS(unsigned long block_id)
 static inline uint64_t CVMX_UCTLX_CLK_RST_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UCTLX_CLK_RST_CTL(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x000118006F000000ull);
 }
@@ -78,7 +86,11 @@ static inline uint64_t CVMX_UCTLX_CLK_RST_CTL(unsigned long block_id)
 static inline uint64_t CVMX_UCTLX_EHCI_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UCTLX_EHCI_CTL(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x000118006F000080ull);
 }
@@ -89,7 +101,11 @@ static inline uint64_t CVMX_UCTLX_EHCI_CTL(unsigned long block_id)
 static inline uint64_t CVMX_UCTLX_EHCI_FLA(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UCTLX_EHCI_FLA(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x000118006F0000A8ull);
 }
@@ -100,7 +116,11 @@ static inline uint64_t CVMX_UCTLX_EHCI_FLA(unsigned long block_id)
 static inline uint64_t CVMX_UCTLX_ERTO_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UCTLX_ERTO_CTL(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x000118006F000090ull);
 }
@@ -111,7 +131,11 @@ static inline uint64_t CVMX_UCTLX_ERTO_CTL(unsigned long block_id)
 static inline uint64_t CVMX_UCTLX_IF_ENA(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UCTLX_IF_ENA(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x000118006F000030ull);
 }
@@ -122,7 +146,11 @@ static inline uint64_t CVMX_UCTLX_IF_ENA(unsigned long block_id)
 static inline uint64_t CVMX_UCTLX_INT_ENA(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UCTLX_INT_ENA(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x000118006F000028ull);
 }
@@ -133,7 +161,11 @@ static inline uint64_t CVMX_UCTLX_INT_ENA(unsigned long block_id)
 static inline uint64_t CVMX_UCTLX_INT_REG(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UCTLX_INT_REG(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x000118006F000020ull);
 }
@@ -144,7 +176,11 @@ static inline uint64_t CVMX_UCTLX_INT_REG(unsigned long block_id)
 static inline uint64_t CVMX_UCTLX_OHCI_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UCTLX_OHCI_CTL(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x000118006F000088ull);
 }
@@ -155,7 +191,11 @@ static inline uint64_t CVMX_UCTLX_OHCI_CTL(unsigned long block_id)
 static inline uint64_t CVMX_UCTLX_ORTO_CTL(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UCTLX_ORTO_CTL(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x000118006F000098ull);
 }
@@ -166,7 +206,10 @@ static inline uint64_t CVMX_UCTLX_ORTO_CTL(unsigned long block_id)
 static inline uint64_t CVMX_UCTLX_PPAF_WM(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UCTLX_PPAF_WM(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x000118006F000038ull);
 }
@@ -177,7 +220,11 @@ static inline uint64_t CVMX_UCTLX_PPAF_WM(unsigned long block_id)
 static inline uint64_t CVMX_UCTLX_UPHY_CTL_STATUS(unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 		cvmx_warn("CVMX_UCTLX_UPHY_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
 	return CVMX_ADD_IO_SEG(0x000118006F000008ull);
 }
@@ -188,7 +235,11 @@ static inline uint64_t CVMX_UCTLX_UPHY_CTL_STATUS(unsigned long block_id)
 static inline uint64_t CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(unsigned long offset, unsigned long block_id)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id == 0))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset <= 1)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 1)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset <= 1)) && ((block_id == 0))))))
 		cvmx_warn("CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(%lu,%lu) is invalid on this chip\n", offset, block_id);
 	return CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8;
 }
@@ -203,12 +254,10 @@ static inline uint64_t CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(unsigned long offset, un
  *
  * Results from BIST runs of UCTL's memories.
  */
-union cvmx_uctlx_bist_status
-{
+union cvmx_uctlx_bist_status {
 	uint64_t u64;
-	struct cvmx_uctlx_bist_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uctlx_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t data_bis                     : 1;  /**< UAHC EHCI Data Ram Bist Status */
 	uint64_t desc_bis                     : 1;  /**< UAHC EHCI Descriptor Ram Bist Status */
@@ -226,8 +275,13 @@ union cvmx_uctlx_bist_status
 	uint64_t reserved_6_63                : 58;
 #endif
 	} s;
+	struct cvmx_uctlx_bist_status_s       cn61xx;
 	struct cvmx_uctlx_bist_status_s       cn63xx;
 	struct cvmx_uctlx_bist_status_s       cn63xxp1;
+	struct cvmx_uctlx_bist_status_s       cn66xx;
+	struct cvmx_uctlx_bist_status_s       cn68xx;
+	struct cvmx_uctlx_bist_status_s       cn68xxp1;
+	struct cvmx_uctlx_bist_status_s       cnf71xx;
 };
 typedef union cvmx_uctlx_bist_status cvmx_uctlx_bist_status_t;
 
@@ -237,12 +291,10 @@ typedef union cvmx_uctlx_bist_status cvmx_uctlx_bist_status_t;
  * CLK_RST_CTL = Clock and Reset Control Reigster
  * This register controls the frequceny of hclk and resets for hclk and phy clocks. It also controls Simulation modes and Bists.
  */
-union cvmx_uctlx_clk_rst_ctl
-{
+union cvmx_uctlx_clk_rst_ctl {
 	uint64_t u64;
-	struct cvmx_uctlx_clk_rst_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uctlx_clk_rst_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_25_63               : 39;
 	uint64_t clear_bist                   : 1;  /**< Clear BIST on the HCLK memories */
 	uint64_t start_bist                   : 1;  /**< Starts BIST on the HCLK memories during 0-to-1
@@ -300,10 +352,13 @@ union cvmx_uctlx_clk_rst_ctl
 	uint64_t p_refclk_sel                 : 2;  /**< PHY PLL Reference Clock Select.
                                                          - 00: uses 12Mhz crystal at USB_XO and USB_XI;
                                                          - 01: uses 12/24/48Mhz 2.5V clock source at USB_XO.
-                                                             USB_XI should be tied to GND.
+                                                             USB_XI should be tied to GND(Not Supported).
                                                          1x: Reserved. */
 	uint64_t p_refclk_div                 : 2;  /**< PHY Reference Clock Frequency Select.
-                                                         - 00: 12MHz, 01: 24Mhz, 10: 48Mhz, 11: Reserved.
+                                                           - 00: 12MHz,
+                                                           - 01: 24Mhz (Not Supported),
+                                                           - 10: 48Mhz (Not Supported),
+                                                           - 11: Reserved.
                                                          Note: This value must be set during POR is active.
                                                          If a crystal is used as a reference clock,this field
                                                          must be set to 12 MHz. Values 01 and 10 are reserved
@@ -351,8 +406,13 @@ union cvmx_uctlx_clk_rst_ctl
 	uint64_t reserved_25_63               : 39;
 #endif
 	} s;
+	struct cvmx_uctlx_clk_rst_ctl_s       cn61xx;
 	struct cvmx_uctlx_clk_rst_ctl_s       cn63xx;
 	struct cvmx_uctlx_clk_rst_ctl_s       cn63xxp1;
+	struct cvmx_uctlx_clk_rst_ctl_s       cn66xx;
+	struct cvmx_uctlx_clk_rst_ctl_s       cn68xx;
+	struct cvmx_uctlx_clk_rst_ctl_s       cn68xxp1;
+	struct cvmx_uctlx_clk_rst_ctl_s       cnf71xx;
 };
 typedef union cvmx_uctlx_clk_rst_ctl cvmx_uctlx_clk_rst_ctl_t;
 
@@ -362,12 +422,10 @@ typedef union cvmx_uctlx_clk_rst_ctl cvmx_uctlx_clk_rst_ctl_t;
  * UCTL_EHCI_CTL = UCTL EHCI Control Register
  * This register controls the general behavior of UCTL EHCI datapath.
  */
-union cvmx_uctlx_ehci_ctl
-{
+union cvmx_uctlx_ehci_ctl {
 	uint64_t u64;
-	struct cvmx_uctlx_ehci_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uctlx_ehci_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t desc_rbm                     : 1;  /**< Descriptor Read Burst Mode on AHB bus
                                                          - 1: A read burst can be interruprted after 16 AHB
@@ -423,8 +481,13 @@ union cvmx_uctlx_ehci_ctl
 	uint64_t reserved_20_63               : 44;
 #endif
 	} s;
+	struct cvmx_uctlx_ehci_ctl_s          cn61xx;
 	struct cvmx_uctlx_ehci_ctl_s          cn63xx;
 	struct cvmx_uctlx_ehci_ctl_s          cn63xxp1;
+	struct cvmx_uctlx_ehci_ctl_s          cn66xx;
+	struct cvmx_uctlx_ehci_ctl_s          cn68xx;
+	struct cvmx_uctlx_ehci_ctl_s          cn68xxp1;
+	struct cvmx_uctlx_ehci_ctl_s          cnf71xx;
 };
 typedef union cvmx_uctlx_ehci_ctl cvmx_uctlx_ehci_ctl_t;
 
@@ -434,18 +497,31 @@ typedef union cvmx_uctlx_ehci_ctl cvmx_uctlx_ehci_ctl_t;
  * UCTL_EHCI_FLA = UCTL EHCI Frame Length Adjument Register
  * This register configures the EHCI Frame Length Adjustment.
  */
-union cvmx_uctlx_ehci_fla
-{
+union cvmx_uctlx_ehci_fla {
 	uint64_t u64;
-	struct cvmx_uctlx_ehci_fla_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uctlx_ehci_fla_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t fla                          : 6;  /**< EHCI Frame Length Adjustment. This feature
                                                          adjusts any offset from the clock source that drives
-                                                         the uSOF counter.  The default value is 32(0x20),
-                                                         which gives an SOF cycle time of 60,0000 (each
-                                                         microframe has 60,000 bit times).
+                                                         the uSOF counter.  The uSOF cycle time (number of
+                                                         uSOF counter clock periods to generate a uSOF
+                                                         microframe length) is equal to 59,488 plus this value.
+                                                         The default value is 32(0x20), which gives an SOF cycle
+                                                         time of 60,000 (each microframe has 60,000 bit times).
+                                                         -------------------------------------------------
+                                                          Frame Length (decimal)      FLA Value
+                                                         -------------------------------------------------
+                                                            59488                      0x00
+                                                            59504                      0x01
+                                                            59520                      0x02
+                                                            ... ...
+                                                            59984                      0x1F
+                                                            60000                      0x20
+                                                            60016                      0x21
+                                                            ... ...
+                                                            60496                      0x3F
+                                                         --------------------------------------------------
                                                          Note: keep this value to 0x20 (decimal 32) for no
                                                          offset. */
 #else
@@ -453,8 +529,13 @@ union cvmx_uctlx_ehci_fla
 	uint64_t reserved_6_63                : 58;
 #endif
 	} s;
+	struct cvmx_uctlx_ehci_fla_s          cn61xx;
 	struct cvmx_uctlx_ehci_fla_s          cn63xx;
 	struct cvmx_uctlx_ehci_fla_s          cn63xxp1;
+	struct cvmx_uctlx_ehci_fla_s          cn66xx;
+	struct cvmx_uctlx_ehci_fla_s          cn68xx;
+	struct cvmx_uctlx_ehci_fla_s          cn68xxp1;
+	struct cvmx_uctlx_ehci_fla_s          cnf71xx;
 };
 typedef union cvmx_uctlx_ehci_fla cvmx_uctlx_ehci_fla_t;
 
@@ -464,12 +545,10 @@ typedef union cvmx_uctlx_ehci_fla cvmx_uctlx_ehci_fla_t;
  * UCTL_ERTO_CTL = UCTL EHCI Readbuffer TimeOut Control Register
  * This register controls timeout for EHCI Readbuffer.
  */
-union cvmx_uctlx_erto_ctl
-{
+union cvmx_uctlx_erto_ctl {
 	uint64_t u64;
-	struct cvmx_uctlx_erto_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uctlx_erto_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t to_val                       : 27; /**< Read buffer timeout value
                                                          (value 0 means timeout disabled) */
@@ -480,8 +559,13 @@ union cvmx_uctlx_erto_ctl
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_uctlx_erto_ctl_s          cn61xx;
 	struct cvmx_uctlx_erto_ctl_s          cn63xx;
 	struct cvmx_uctlx_erto_ctl_s          cn63xxp1;
+	struct cvmx_uctlx_erto_ctl_s          cn66xx;
+	struct cvmx_uctlx_erto_ctl_s          cn68xx;
+	struct cvmx_uctlx_erto_ctl_s          cn68xxp1;
+	struct cvmx_uctlx_erto_ctl_s          cnf71xx;
 };
 typedef union cvmx_uctlx_erto_ctl cvmx_uctlx_erto_ctl_t;
 
@@ -492,12 +576,10 @@ typedef union cvmx_uctlx_erto_ctl cvmx_uctlx_erto_ctl_t;
  *
  * Register to enable the uctl interface clock.
  */
-union cvmx_uctlx_if_ena
-{
+union cvmx_uctlx_if_ena {
 	uint64_t u64;
-	struct cvmx_uctlx_if_ena_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uctlx_if_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t en                           : 1;  /**< Turns on the USB UCTL interface clock */
 #else
@@ -505,8 +587,13 @@ union cvmx_uctlx_if_ena
 	uint64_t reserved_1_63                : 63;
 #endif
 	} s;
+	struct cvmx_uctlx_if_ena_s            cn61xx;
 	struct cvmx_uctlx_if_ena_s            cn63xx;
 	struct cvmx_uctlx_if_ena_s            cn63xxp1;
+	struct cvmx_uctlx_if_ena_s            cn66xx;
+	struct cvmx_uctlx_if_ena_s            cn68xx;
+	struct cvmx_uctlx_if_ena_s            cn68xxp1;
+	struct cvmx_uctlx_if_ena_s            cnf71xx;
 };
 typedef union cvmx_uctlx_if_ena cvmx_uctlx_if_ena_t;
 
@@ -517,12 +604,10 @@ typedef union cvmx_uctlx_if_ena cvmx_uctlx_if_ena_t;
  *
  * Register to enable individual interrupt source in corresponding to UCTL_INT_REG
  */
-union cvmx_uctlx_int_ena
-{
+union cvmx_uctlx_int_ena {
 	uint64_t u64;
-	struct cvmx_uctlx_int_ena_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uctlx_int_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t ec_ovf_e                     : 1;  /**< Ehci Commit OVerFlow Error */
 	uint64_t oc_ovf_e                     : 1;  /**< Ohci Commit OVerFlow Error */
@@ -544,8 +629,13 @@ union cvmx_uctlx_int_ena
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
+	struct cvmx_uctlx_int_ena_s           cn61xx;
 	struct cvmx_uctlx_int_ena_s           cn63xx;
 	struct cvmx_uctlx_int_ena_s           cn63xxp1;
+	struct cvmx_uctlx_int_ena_s           cn66xx;
+	struct cvmx_uctlx_int_ena_s           cn68xx;
+	struct cvmx_uctlx_int_ena_s           cn68xxp1;
+	struct cvmx_uctlx_int_ena_s           cnf71xx;
 };
 typedef union cvmx_uctlx_int_ena cvmx_uctlx_int_ena_t;
 
@@ -556,12 +646,10 @@ typedef union cvmx_uctlx_int_ena cvmx_uctlx_int_ena_t;
  *
  * Summary of different bits of RSL interrupt status.
  */
-union cvmx_uctlx_int_reg
-{
+union cvmx_uctlx_int_reg {
 	uint64_t u64;
-	struct cvmx_uctlx_int_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uctlx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t ec_ovf_e                     : 1;  /**< Ehci Commit OVerFlow Error
                                                          When the error happenes, the whole NCB system needs
@@ -587,8 +675,13 @@ union cvmx_uctlx_int_reg
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
+	struct cvmx_uctlx_int_reg_s           cn61xx;
 	struct cvmx_uctlx_int_reg_s           cn63xx;
 	struct cvmx_uctlx_int_reg_s           cn63xxp1;
+	struct cvmx_uctlx_int_reg_s           cn66xx;
+	struct cvmx_uctlx_int_reg_s           cn68xx;
+	struct cvmx_uctlx_int_reg_s           cn68xxp1;
+	struct cvmx_uctlx_int_reg_s           cnf71xx;
 };
 typedef union cvmx_uctlx_int_reg cvmx_uctlx_int_reg_t;
 
@@ -600,12 +693,10 @@ typedef union cvmx_uctlx_int_reg cvmx_uctlx_int_reg_t;
  * UCTL_OHCI_CTL = UCTL OHCI Control Register
  * This register controls the general behavior of UCTL OHCI datapath.
  */
-union cvmx_uctlx_ohci_ctl
-{
+union cvmx_uctlx_ohci_ctl {
 	uint64_t u64;
-	struct cvmx_uctlx_ohci_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uctlx_ohci_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_19_63               : 45;
 	uint64_t reg_nb                       : 1;  /**< 1: OHCI register access will not be blocked by EHCI
                                                           buffer/descriptor access on AHB
@@ -650,8 +741,13 @@ union cvmx_uctlx_ohci_ctl
 	uint64_t reserved_19_63               : 45;
 #endif
 	} s;
+	struct cvmx_uctlx_ohci_ctl_s          cn61xx;
 	struct cvmx_uctlx_ohci_ctl_s          cn63xx;
 	struct cvmx_uctlx_ohci_ctl_s          cn63xxp1;
+	struct cvmx_uctlx_ohci_ctl_s          cn66xx;
+	struct cvmx_uctlx_ohci_ctl_s          cn68xx;
+	struct cvmx_uctlx_ohci_ctl_s          cn68xxp1;
+	struct cvmx_uctlx_ohci_ctl_s          cnf71xx;
 };
 typedef union cvmx_uctlx_ohci_ctl cvmx_uctlx_ohci_ctl_t;
 
@@ -661,12 +757,10 @@ typedef union cvmx_uctlx_ohci_ctl cvmx_uctlx_ohci_ctl_t;
  * UCTL_ORTO_CTL = UCTL OHCI Readbuffer TimeOut Control Register
  * This register controls timeout for OHCI Readbuffer.
  */
-union cvmx_uctlx_orto_ctl
-{
+union cvmx_uctlx_orto_ctl {
 	uint64_t u64;
-	struct cvmx_uctlx_orto_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uctlx_orto_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t to_val                       : 24; /**< Read buffer timeout value
                                                          (value 0 means timeout disabled) */
@@ -677,8 +771,13 @@ union cvmx_uctlx_orto_ctl
 	uint64_t reserved_32_63               : 32;
 #endif
 	} s;
+	struct cvmx_uctlx_orto_ctl_s          cn61xx;
 	struct cvmx_uctlx_orto_ctl_s          cn63xx;
 	struct cvmx_uctlx_orto_ctl_s          cn63xxp1;
+	struct cvmx_uctlx_orto_ctl_s          cn66xx;
+	struct cvmx_uctlx_orto_ctl_s          cn68xx;
+	struct cvmx_uctlx_orto_ctl_s          cn68xxp1;
+	struct cvmx_uctlx_orto_ctl_s          cnf71xx;
 };
 typedef union cvmx_uctlx_orto_ctl cvmx_uctlx_orto_ctl_t;
 
@@ -689,12 +788,10 @@ typedef union cvmx_uctlx_orto_ctl cvmx_uctlx_orto_ctl_t;
  *
  * Register to set PP access FIFO full watermark.
  */
-union cvmx_uctlx_ppaf_wm
-{
+union cvmx_uctlx_ppaf_wm {
 	uint64_t u64;
-	struct cvmx_uctlx_ppaf_wm_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uctlx_ppaf_wm_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t wm                           : 5;  /**< Number of entries when PP Access FIFO will assert
                                                          full (back pressure) */
@@ -703,8 +800,11 @@ union cvmx_uctlx_ppaf_wm
 	uint64_t reserved_5_63                : 59;
 #endif
 	} s;
+	struct cvmx_uctlx_ppaf_wm_s           cn61xx;
 	struct cvmx_uctlx_ppaf_wm_s           cn63xx;
 	struct cvmx_uctlx_ppaf_wm_s           cn63xxp1;
+	struct cvmx_uctlx_ppaf_wm_s           cn66xx;
+	struct cvmx_uctlx_ppaf_wm_s           cnf71xx;
 };
 typedef union cvmx_uctlx_ppaf_wm cvmx_uctlx_ppaf_wm_t;
 
@@ -714,12 +814,10 @@ typedef union cvmx_uctlx_ppaf_wm cvmx_uctlx_ppaf_wm_t;
  * UPHY_CTL_STATUS = USB PHY Control and Status Reigster
  * This register controls the USB PHY test and Bist.
  */
-union cvmx_uctlx_uphy_ctl_status
-{
+union cvmx_uctlx_uphy_ctl_status {
 	uint64_t u64;
-	struct cvmx_uctlx_uphy_ctl_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uctlx_uphy_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_10_63               : 54;
 	uint64_t bist_done                    : 1;  /**< PHY BIST DONE.  Asserted at the end of the PHY BIST
                                                          sequence. */
@@ -735,7 +833,7 @@ union cvmx_uctlx_uphy_ctl_status
                                                            Provide 3.3V to USB_VDD33 Tie USB_REXT to 3.3V
                                                            supply and Set SIDDQ to 1. */
 	uint64_t vtest_en                     : 1;  /**< Analog Test Pin Enable.
-                                                         1 = The PHY's ANALOG _TEST pin is enabled for the
+                                                         1 = The PHY's ANALOG_TEST pin is enabled for the
                                                              input and output of applicable analog test
                                                              signals.
                                                          0 = The ANALOG_TEST pin is disabled. */
@@ -764,8 +862,13 @@ union cvmx_uctlx_uphy_ctl_status
 	uint64_t reserved_10_63               : 54;
 #endif
 	} s;
+	struct cvmx_uctlx_uphy_ctl_status_s   cn61xx;
 	struct cvmx_uctlx_uphy_ctl_status_s   cn63xx;
 	struct cvmx_uctlx_uphy_ctl_status_s   cn63xxp1;
+	struct cvmx_uctlx_uphy_ctl_status_s   cn66xx;
+	struct cvmx_uctlx_uphy_ctl_status_s   cn68xx;
+	struct cvmx_uctlx_uphy_ctl_status_s   cn68xxp1;
+	struct cvmx_uctlx_uphy_ctl_status_s   cnf71xx;
 };
 typedef union cvmx_uctlx_uphy_ctl_status cvmx_uctlx_uphy_ctl_status_t;
 
@@ -775,12 +878,10 @@ typedef union cvmx_uctlx_uphy_ctl_status cvmx_uctlx_uphy_ctl_status_t;
  * UPHY_PORTX_CTL_STATUS = USB PHY Port X Control and Status Reigsters
  * This register controls the each port of the USB PHY.
  */
-union cvmx_uctlx_uphy_portx_ctl_status
-{
+union cvmx_uctlx_uphy_portx_ctl_status {
 	uint64_t u64;
-	struct cvmx_uctlx_uphy_portx_ctl_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_uctlx_uphy_portx_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_43_63               : 21;
 	uint64_t tdata_out                    : 4;  /**< PHY test data out. Presents either interlly
                                                          generated signals or test register contenets, based
@@ -797,9 +898,16 @@ union cvmx_uctlx_uphy_portx_ctl_status
                                                          to 1'b0. */
 	uint64_t portreset                    : 1;  /**< Per-port reset */
 	uint64_t txhsvxtune                   : 2;  /**< Transmitter High-Speed Crossover Adjustment */
-	uint64_t txvreftune                   : 4;  /**< HS DC Voltage Level Adjustment */
-	uint64_t txrisetune                   : 1;  /**< HS Transmitter Rise/Fall Time Adjustment */
-	uint64_t txpreemphasistune            : 1;  /**< HS transmitter pre-emphasis enable. */
+	uint64_t txvreftune                   : 4;  /**< HS DC Voltage Level Adjustment
+                                                         When the recommended 37.4 Ohm resistor is present
+                                                         on USB_REXT, the recommended TXVREFTUNE value is 15 */
+	uint64_t txrisetune                   : 1;  /**< HS Transmitter Rise/Fall Time Adjustment
+                                                         When the recommended 37.4 Ohm resistor is present
+                                                         on USB_REXT, the recommended TXRISETUNE value is 1 */
+	uint64_t txpreemphasistune            : 1;  /**< HS transmitter pre-emphasis enable.
+                                                         When the recommended 37.4 Ohm resistor is present
+                                                         on USB_REXT, the recommended TXPREEMPHASISTUNE
+                                                         value is 1 */
 	uint64_t txfslstune                   : 4;  /**< FS/LS Source Impedance Adjustment */
 	uint64_t sqrxtune                     : 3;  /**< Squelch Threshold Adjustment */
 	uint64_t compdistune                  : 3;  /**< Disconnect Threshold Adjustment */
@@ -842,8 +950,13 @@ union cvmx_uctlx_uphy_portx_ctl_status
 	uint64_t reserved_43_63               : 21;
 #endif
 	} s;
+	struct cvmx_uctlx_uphy_portx_ctl_status_s cn61xx;
 	struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx;
 	struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1;
+	struct cvmx_uctlx_uphy_portx_ctl_status_s cn66xx;
+	struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xx;
+	struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xxp1;
+	struct cvmx_uctlx_uphy_portx_ctl_status_s cnf71xx;
 };
 typedef union cvmx_uctlx_uphy_portx_ctl_status cvmx_uctlx_uphy_portx_ctl_status_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-usb.c b/sys/contrib/octeon-sdk/cvmx-usb.c
index 01dabe8..6d99dac 100644
--- a/sys/contrib/octeon-sdk/cvmx-usb.c
+++ b/sys/contrib/octeon-sdk/cvmx-usb.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-usb.h b/sys/contrib/octeon-sdk/cvmx-usb.h
index b6a3e4c..2886436 100644
--- a/sys/contrib/octeon-sdk/cvmx-usb.h
+++ b/sys/contrib/octeon-sdk/cvmx-usb.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-usbcx-defs.h b/sys/contrib/octeon-sdk/cvmx-usbcx-defs.h
index 03dd07d..db7f03e 100644
--- a/sys/contrib/octeon-sdk/cvmx-usbcx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-usbcx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_USBCX_TYPEDEFS_H__
-#define __CVMX_USBCX_TYPEDEFS_H__
+#ifndef __CVMX_USBCX_DEFS_H__
+#define __CVMX_USBCX_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_USBCX_DAINT(unsigned long block_id)
@@ -846,12 +846,10 @@ static inline uint64_t CVMX_USBCX_PCGCCTL(unsigned long block_id)
  * bits are used. Bits in this register are set and cleared when the application sets and clears
  * bits in the corresponding Device Endpoint-n Interrupt register (DIEPINTn/DOEPINTn).
  */
-union cvmx_usbcx_daint
-{
+union cvmx_usbcx_daint {
 	uint32_t u32;
-	struct cvmx_usbcx_daint_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_daint_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t outepint                     : 16; /**< OUT Endpoint Interrupt Bits (OutEPInt)
                                                          One bit per OUT endpoint:
                                                          Bit 16 for OUT endpoint 0, bit 31 for OUT endpoint 15 */
@@ -883,12 +881,10 @@ typedef union cvmx_usbcx_daint cvmx_usbcx_daint_t;
  * All Endpoints Interrupt (DAINT) register bit corresponding to that interrupt will still be set.
  * Mask Interrupt: 1'b0 Unmask Interrupt: 1'b1
  */
-union cvmx_usbcx_daintmsk
-{
+union cvmx_usbcx_daintmsk {
 	uint32_t u32;
-	struct cvmx_usbcx_daintmsk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_daintmsk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t outepmsk                     : 16; /**< OUT EP Interrupt Mask Bits (OutEpMsk)
                                                          One per OUT Endpoint:
                                                          Bit 16 for OUT EP 0, bit 31 for OUT EP 15 */
@@ -918,12 +914,10 @@ typedef union cvmx_usbcx_daintmsk cvmx_usbcx_daintmsk_t;
  * This register configures the core in Device mode after power-on or after certain control
  * commands or enumeration. Do not make changes to this register after initial programming.
  */
-union cvmx_usbcx_dcfg
-{
+union cvmx_usbcx_dcfg {
 	uint32_t u32;
-	struct cvmx_usbcx_dcfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_dcfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_23_31               : 9;
 	uint32_t epmiscnt                     : 5;  /**< IN Endpoint Mismatch Count (EPMisCnt)
                                                          The application programs this filed with a count that determines
@@ -996,12 +990,10 @@ typedef union cvmx_usbcx_dcfg cvmx_usbcx_dcfg_t;
  * Device Control Register (DCTL)
  *
  */
-union cvmx_usbcx_dctl
-{
+union cvmx_usbcx_dctl {
 	uint32_t u32;
-	struct cvmx_usbcx_dctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_dctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_12_31               : 20;
 	uint32_t pwronprgdone                 : 1;  /**< Power-On Programming Done (PWROnPrgDone)
                                                          The application uses this bit to indicate that register
@@ -1100,12 +1092,10 @@ typedef union cvmx_usbcx_dctl cvmx_usbcx_dctl_t;
  *
  * The application uses the register to control the behaviour of each logical endpoint other than endpoint 0.
  */
-union cvmx_usbcx_diepctlx
-{
+union cvmx_usbcx_diepctlx {
 	uint32_t u32;
-	struct cvmx_usbcx_diepctlx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_diepctlx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t epena                        : 1;  /**< Endpoint Enable (EPEna)
                                                          Indicates that data is ready to be transmitted on the endpoint.
                                                          The core clears this bit before setting any of the following
@@ -1262,12 +1252,10 @@ typedef union cvmx_usbcx_diepctlx cvmx_usbcx_diepctlx_t;
  * register. The application must clear the appropriate bit in this register
  * to clear the corresponding bits in the DAINT and GINTSTS registers.
  */
-union cvmx_usbcx_diepintx
-{
+union cvmx_usbcx_diepintx {
 	uint32_t u32;
-	struct cvmx_usbcx_diepintx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_diepintx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_7_31                : 25;
 	uint32_t inepnakeff                   : 1;  /**< IN Endpoint NAK Effective (INEPNakEff)
                                                          Applies to periodic IN endpoints only.
@@ -1337,12 +1325,10 @@ typedef union cvmx_usbcx_diepintx cvmx_usbcx_diepintx_t;
  * bit in this register. Status bits are masked by default.
  * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
  */
-union cvmx_usbcx_diepmsk
-{
+union cvmx_usbcx_diepmsk {
 	uint32_t u32;
-	struct cvmx_usbcx_diepmsk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_diepmsk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_7_31                : 25;
 	uint32_t inepnakeffmsk                : 1;  /**< IN Endpoint NAK Effective Mask (INEPNakEffMsk) */
 	uint32_t intknepmismsk                : 1;  /**< IN Token received with EP Mismatch Mask (INTknEPMisMsk) */
@@ -1384,12 +1370,10 @@ typedef union cvmx_usbcx_diepmsk cvmx_usbcx_diepmsk_t;
  * the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit.
  * This register is used only for endpoints other than Endpoint 0.
  */
-union cvmx_usbcx_dieptsizx
-{
+union cvmx_usbcx_dieptsizx {
 	uint32_t u32;
-	struct cvmx_usbcx_dieptsizx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_dieptsizx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_31_31               : 1;
 	uint32_t mc                           : 2;  /**< Multi Count (MC)
                                                          Applies to IN endpoints only.
@@ -1443,12 +1427,10 @@ typedef union cvmx_usbcx_dieptsizx cvmx_usbcx_dieptsizx_t;
  *
  * The application uses the register to control the behaviour of each logical endpoint other than endpoint 0.
  */
-union cvmx_usbcx_doepctlx
-{
+union cvmx_usbcx_doepctlx {
 	uint32_t u32;
-	struct cvmx_usbcx_doepctlx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_doepctlx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t epena                        : 1;  /**< Endpoint Enable (EPEna)
                                                          Indicates that the application has allocated the memory tp start
                                                          receiving data from the USB.
@@ -1596,12 +1578,10 @@ typedef union cvmx_usbcx_doepctlx cvmx_usbcx_doepctlx_t;
  * Interrupt register. The application must clear the appropriate bit in this register to clear the
  * corresponding bits in the DAINT and GINTSTS registers.
  */
-union cvmx_usbcx_doepintx
-{
+union cvmx_usbcx_doepintx {
 	uint32_t u32;
-	struct cvmx_usbcx_doepintx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_doepintx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_5_31                : 27;
 	uint32_t outtknepdis                  : 1;  /**< OUT Token Received When Endpoint Disabled (OUTTknEPdis)
                                                          Applies only to control OUT endpoints.
@@ -1655,12 +1635,10 @@ typedef union cvmx_usbcx_doepintx cvmx_usbcx_doepintx_t;
  * corresponding bit in this register. Status bits are masked by default.
  * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
  */
-union cvmx_usbcx_doepmsk
-{
+union cvmx_usbcx_doepmsk {
 	uint32_t u32;
-	struct cvmx_usbcx_doepmsk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_doepmsk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_5_31                : 27;
 	uint32_t outtknepdismsk               : 1;  /**< OUT Token Received when Endpoint Disabled Mask
                                                          (OUTTknEPdisMsk)
@@ -1700,12 +1678,10 @@ typedef union cvmx_usbcx_doepmsk cvmx_usbcx_doepmsk_t;
  * can only read this register once the core has cleared the Endpoint Enable bit.
  * This register is used only for endpoints other than Endpoint 0.
  */
-union cvmx_usbcx_doeptsizx
-{
+union cvmx_usbcx_doeptsizx {
 	uint32_t u32;
-	struct cvmx_usbcx_doeptsizx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_doeptsizx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_31_31               : 1;
 	uint32_t mc                           : 2;  /**< Multi Count (MC)
                                                          Received Data PID (RxDPID)
@@ -1764,12 +1740,10 @@ typedef union cvmx_usbcx_doeptsizx cvmx_usbcx_doeptsizx_t;
  * in Device mode. Each periodic FIFO holds the data for one periodic IN endpoint.
  * This register is repeated for each periodic FIFO instantiated.
  */
-union cvmx_usbcx_dptxfsizx
-{
+union cvmx_usbcx_dptxfsizx {
 	uint32_t u32;
-	struct cvmx_usbcx_dptxfsizx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_dptxfsizx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dptxfsize                    : 16; /**< Device Periodic TxFIFO Size (DPTxFSize)
                                                          This value is in terms of 32-bit words.
                                                          * Minimum value is 4
@@ -1799,12 +1773,10 @@ typedef union cvmx_usbcx_dptxfsizx cvmx_usbcx_dptxfsizx_t;
  * This register indicates the status of the core with respect to USB-related events.
  * It must be read on interrupts from Device All Interrupts (DAINT) register.
  */
-union cvmx_usbcx_dsts
-{
+union cvmx_usbcx_dsts {
 	uint32_t u32;
-	struct cvmx_usbcx_dsts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_dsts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_22_31               : 10;
 	uint32_t soffn                        : 14; /**< Frame or Microframe Number of the Received SOF (SOFFN)
                                                          When the core is operating at high speed, this field contains a
@@ -1866,12 +1838,10 @@ typedef union cvmx_usbcx_dsts cvmx_usbcx_dsts_t;
  * Learning Queue. When the queue is full, the new token is pushed into the queue and oldest
  * token is discarded.
  */
-union cvmx_usbcx_dtknqr1
-{
+union cvmx_usbcx_dtknqr1 {
 	uint32_t u32;
-	struct cvmx_usbcx_dtknqr1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_dtknqr1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t eptkn                        : 24; /**< Endpoint Token (EPTkn)
                                                          Four bits per token represent the endpoint number of the token:
                                                          * Bits [31:28]: Endpoint number of Token 5
@@ -1908,12 +1878,10 @@ typedef union cvmx_usbcx_dtknqr1 cvmx_usbcx_dtknqr1_t;
  *
  * A read from this register returns the next 8 endpoint entries of the learning queue.
  */
-union cvmx_usbcx_dtknqr2
-{
+union cvmx_usbcx_dtknqr2 {
 	uint32_t u32;
-	struct cvmx_usbcx_dtknqr2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_dtknqr2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t eptkn                        : 32; /**< Endpoint Token (EPTkn)
                                                          Four bits per token represent the endpoint number of the token:
                                                          * Bits [31:28]: Endpoint number of Token 13
@@ -1942,12 +1910,10 @@ typedef union cvmx_usbcx_dtknqr2 cvmx_usbcx_dtknqr2_t;
  *
  * A read from this register returns the next 8 endpoint entries of the learning queue.
  */
-union cvmx_usbcx_dtknqr3
-{
+union cvmx_usbcx_dtknqr3 {
 	uint32_t u32;
-	struct cvmx_usbcx_dtknqr3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_dtknqr3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t eptkn                        : 32; /**< Endpoint Token (EPTkn)
                                                          Four bits per token represent the endpoint number of the token:
                                                          * Bits [31:28]: Endpoint number of Token 21
@@ -1976,12 +1942,10 @@ typedef union cvmx_usbcx_dtknqr3 cvmx_usbcx_dtknqr3_t;
  *
  * A read from this register returns the last 8 endpoint entries of the learning queue.
  */
-union cvmx_usbcx_dtknqr4
-{
+union cvmx_usbcx_dtknqr4 {
 	uint32_t u32;
-	struct cvmx_usbcx_dtknqr4_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_dtknqr4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t eptkn                        : 32; /**< Endpoint Token (EPTkn)
                                                          Four bits per token represent the endpoint number of the token:
                                                          * Bits [31:28]: Endpoint number of Token 29
@@ -2016,12 +1980,10 @@ typedef union cvmx_usbcx_dtknqr4 cvmx_usbcx_dtknqr4_t;
  * The application must program this register as part of the O2P USB core initialization.
  * Do not change this register after the initial programming.
  */
-union cvmx_usbcx_gahbcfg
-{
+union cvmx_usbcx_gahbcfg {
 	uint32_t u32;
-	struct cvmx_usbcx_gahbcfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_gahbcfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_9_31                : 23;
 	uint32_t ptxfemplvl                   : 1;  /**< Periodic TxFIFO Empty Level (PTxFEmpLvl)
                                                          Software should set this bit to 0x1.
@@ -2081,12 +2043,10 @@ typedef union cvmx_usbcx_gahbcfg cvmx_usbcx_gahbcfg_t;
  *
  * This register contains the logical endpoint direction(s) of the O2P USB core.
  */
-union cvmx_usbcx_ghwcfg1
-{
+union cvmx_usbcx_ghwcfg1 {
 	uint32_t u32;
-	struct cvmx_usbcx_ghwcfg1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_ghwcfg1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t epdir                        : 32; /**< Endpoint Direction (epdir)
                                                          Two bits per endpoint represent the direction.
                                                          * 2'b00: BIDIR (IN and OUT) endpoint
@@ -2119,12 +2079,10 @@ typedef union cvmx_usbcx_ghwcfg1 cvmx_usbcx_ghwcfg1_t;
  *
  * This register contains configuration options of the O2P USB core.
  */
-union cvmx_usbcx_ghwcfg2
-{
+union cvmx_usbcx_ghwcfg2 {
 	uint32_t u32;
-	struct cvmx_usbcx_ghwcfg2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_ghwcfg2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_31_31               : 1;
 	uint32_t tknqdepth                    : 5;  /**< Device Mode IN Token Sequence Learning Queue Depth
                                                          (TknQDepth)
@@ -2217,12 +2175,10 @@ typedef union cvmx_usbcx_ghwcfg2 cvmx_usbcx_ghwcfg2_t;
  *
  * This register contains the configuration options of the O2P USB core.
  */
-union cvmx_usbcx_ghwcfg3
-{
+union cvmx_usbcx_ghwcfg3 {
 	uint32_t u32;
-	struct cvmx_usbcx_ghwcfg3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_ghwcfg3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dfifodepth                   : 16; /**< DFIFO Depth (DfifoDepth)
                                                          This value is in terms of 32-bit words.
                                                          * Minimum value is 32
@@ -2297,12 +2253,10 @@ typedef union cvmx_usbcx_ghwcfg3 cvmx_usbcx_ghwcfg3_t;
  *
  * This register contains the configuration options of the O2P USB core.
  */
-union cvmx_usbcx_ghwcfg4
-{
+union cvmx_usbcx_ghwcfg4 {
 	uint32_t u32;
-	struct cvmx_usbcx_ghwcfg4_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_ghwcfg4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_30_31               : 2;
 	uint32_t numdevmodinend               : 4;  /**< Enable dedicatd transmit FIFO for device IN endpoints. */
 	uint32_t endedtrfifo                  : 1;  /**< Enable dedicatd transmit FIFO for device IN endpoints. */
@@ -2359,9 +2313,8 @@ union cvmx_usbcx_ghwcfg4
 	uint32_t reserved_30_31               : 2;
 #endif
 	} s;
-	struct cvmx_usbcx_ghwcfg4_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_ghwcfg4_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_25_31               : 7;
 	uint32_t sessendfltr                  : 1;  /**< "session_end" Filter Enabled (SessEndFltr)
                                                          * 1'b0: No filter
@@ -2433,12 +2386,10 @@ typedef union cvmx_usbcx_ghwcfg4 cvmx_usbcx_ghwcfg4_t;
  * However, the Core Interrupt (GINTSTS) register bit corresponding to that interrupt will still be set.
  * Mask interrupt: 1'b0, Unmask interrupt: 1'b1
  */
-union cvmx_usbcx_gintmsk
-{
+union cvmx_usbcx_gintmsk {
 	uint32_t u32;
-	struct cvmx_usbcx_gintmsk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_gintmsk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t wkupintmsk                   : 1;  /**< Resume/Remote Wakeup Detected Interrupt Mask
                                                          (WkUpIntMsk) */
 	uint32_t sessreqintmsk                : 1;  /**< Session Request/New Session Detected Interrupt Mask
@@ -2534,12 +2485,10 @@ typedef union cvmx_usbcx_gintmsk cvmx_usbcx_gintmsk_t;
  * The FIFO status interrupts are read only; once software reads from or writes to the FIFO while servicing these
  * interrupts, FIFO interrupt conditions are cleared automatically.
  */
-union cvmx_usbcx_gintsts
-{
+union cvmx_usbcx_gintsts {
 	uint32_t u32;
-	struct cvmx_usbcx_gintsts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_gintsts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t wkupint                      : 1;  /**< Resume/Remote Wakeup Detected Interrupt (WkUpInt)
                                                          In Device mode, this interrupt is asserted when a resume is
                                                          detected on the USB. In Host mode, this interrupt is asserted
@@ -2766,12 +2715,10 @@ typedef union cvmx_usbcx_gintsts cvmx_usbcx_gintsts_t;
  *
  * The application can program the RAM size and the memory start address for the Non-Periodic TxFIFO.
  */
-union cvmx_usbcx_gnptxfsiz
-{
+union cvmx_usbcx_gnptxfsiz {
 	uint32_t u32;
-	struct cvmx_usbcx_gnptxfsiz_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_gnptxfsiz_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t nptxfdep                     : 16; /**< Non-Periodic TxFIFO Depth (NPTxFDep)
                                                          This value is in terms of 32-bit words.
                                                          Minimum value is 16
@@ -2802,12 +2749,10 @@ typedef union cvmx_usbcx_gnptxfsiz cvmx_usbcx_gnptxfsiz_t;
  * This read-only register contains the free space information for the Non-Periodic TxFIFO and
  * the Non-Periodic Transmit Request Queue
  */
-union cvmx_usbcx_gnptxsts
-{
+union cvmx_usbcx_gnptxsts {
 	uint32_t u32;
-	struct cvmx_usbcx_gnptxsts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_gnptxsts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_31_31               : 1;
 	uint32_t nptxqtop                     : 7;  /**< Top of the Non-Periodic Transmit Request Queue (NPTxQTop)
                                                          Entry in the Non-Periodic Tx Request Queue that is currently
@@ -2864,12 +2809,10 @@ typedef union cvmx_usbcx_gnptxsts cvmx_usbcx_gnptxsts_t;
  *
  * The OTG Control and Status register controls the behavior and reflects the status of the OTG function of the core.:
  */
-union cvmx_usbcx_gotgctl
-{
+union cvmx_usbcx_gotgctl {
 	uint32_t u32;
-	struct cvmx_usbcx_gotgctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_gotgctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_20_31               : 12;
 	uint32_t bsesvld                      : 1;  /**< B-Session Valid (BSesVld)
                                                          Valid only when O2P USB core is configured as a USB device.
@@ -2935,12 +2878,10 @@ typedef union cvmx_usbcx_gotgctl cvmx_usbcx_gotgctl_t;
  * The application reads this register whenever there is an OTG interrupt and clears the bits in this register
  * to clear the OTG interrupt. It is shown in Interrupt .:
  */
-union cvmx_usbcx_gotgint
-{
+union cvmx_usbcx_gotgint {
 	uint32_t u32;
-	struct cvmx_usbcx_gotgint_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_gotgint_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_20_31               : 12;
 	uint32_t dbncedone                    : 1;  /**< Debounce Done (DbnceDone)
                                                          In the present version of the code this bit is tied to '0'. */
@@ -2987,12 +2928,10 @@ typedef union cvmx_usbcx_gotgint cvmx_usbcx_gotgint_t;
  *
  * The application uses this register to reset various hardware features inside the core.
  */
-union cvmx_usbcx_grstctl
-{
+union cvmx_usbcx_grstctl {
 	uint32_t u32;
-	struct cvmx_usbcx_grstctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_grstctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ahbidle                      : 1;  /**< AHB Master Idle (AHBIdle)
                                                          Indicates that the AHB Master State Machine is in the IDLE
                                                          condition. */
@@ -3124,12 +3063,10 @@ typedef union cvmx_usbcx_grstctl cvmx_usbcx_grstctl_t;
  *
  * The application can program the RAM size that must be allocated to the RxFIFO.
  */
-union cvmx_usbcx_grxfsiz
-{
+union cvmx_usbcx_grxfsiz {
 	uint32_t u32;
-	struct cvmx_usbcx_grxfsiz_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_grxfsiz_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_16_31               : 16;
 	uint32_t rxfdep                       : 16; /**< RxFIFO Depth (RxFDep)
                                                          This value is in terms of 32-bit words.
@@ -3161,12 +3098,10 @@ typedef union cvmx_usbcx_grxfsiz cvmx_usbcx_grxfsiz_t;
  *       The offset difference shown in this document is for software clarity and is actually ignored by the
  *       hardware.
  */
-union cvmx_usbcx_grxstspd
-{
+union cvmx_usbcx_grxstspd {
 	uint32_t u32;
-	struct cvmx_usbcx_grxstspd_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_grxstspd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_25_31               : 7;
 	uint32_t fn                           : 4;  /**< Frame Number (FN)
                                                          This is the least significant 4 bits of the (micro)frame number in
@@ -3219,12 +3154,10 @@ typedef union cvmx_usbcx_grxstspd cvmx_usbcx_grxstspd_t;
  *       The offset difference shown in this document is for software clarity and is actually ignored by the
  *       hardware.
  */
-union cvmx_usbcx_grxstsph
-{
+union cvmx_usbcx_grxstsph {
 	uint32_t u32;
-	struct cvmx_usbcx_grxstsph_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_grxstsph_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_21_31               : 11;
 	uint32_t pktsts                       : 4;  /**< Packet Status (PktSts)
                                                          Indicates the status of the received packet
@@ -3272,12 +3205,10 @@ typedef union cvmx_usbcx_grxstsph cvmx_usbcx_grxstsph_t;
  *       The offset difference shown in this document is for software clarity and is actually ignored by the
  *       hardware.
  */
-union cvmx_usbcx_grxstsrd
-{
+union cvmx_usbcx_grxstsrd {
 	uint32_t u32;
-	struct cvmx_usbcx_grxstsrd_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_grxstsrd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_25_31               : 7;
 	uint32_t fn                           : 4;  /**< Frame Number (FN)
                                                          This is the least significant 4 bits of the (micro)frame number in
@@ -3330,12 +3261,10 @@ typedef union cvmx_usbcx_grxstsrd cvmx_usbcx_grxstsrd_t;
  *       The offset difference shown in this document is for software clarity and is actually ignored by the
  *       hardware.
  */
-union cvmx_usbcx_grxstsrh
-{
+union cvmx_usbcx_grxstsrh {
 	uint32_t u32;
-	struct cvmx_usbcx_grxstsrh_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_grxstsrh_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_21_31               : 11;
 	uint32_t pktsts                       : 4;  /**< Packet Status (PktSts)
                                                          Indicates the status of the received packet
@@ -3379,12 +3308,10 @@ typedef union cvmx_usbcx_grxstsrh cvmx_usbcx_grxstsrh_t;
  *
  * This is a read-only register that contains the release number of the core being used.
  */
-union cvmx_usbcx_gsnpsid
-{
+union cvmx_usbcx_gsnpsid {
 	uint32_t u32;
-	struct cvmx_usbcx_gsnpsid_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_gsnpsid_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t synopsysid                   : 32; /**< 0x4F54\<version\>A, release number of the core being used.
                                                          0x4F54220A => pass1.x,  0x4F54240A => pass2.x */
 #else
@@ -3411,12 +3338,10 @@ typedef union cvmx_usbcx_gsnpsid cvmx_usbcx_gsnpsid_t;
  * before starting any transactions on either the AHB or the USB.
  * Do not make changes to this register after the initial programming.
  */
-union cvmx_usbcx_gusbcfg
-{
+union cvmx_usbcx_gusbcfg {
 	uint32_t u32;
-	struct cvmx_usbcx_gusbcfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_gusbcfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_17_31               : 15;
 	uint32_t otgi2csel                    : 1;  /**< UTMIFS or I2C Interface Select (OtgI2CSel)
                                                          This bit is always 0x0. */
@@ -3510,12 +3435,10 @@ typedef union cvmx_usbcx_gusbcfg cvmx_usbcx_gusbcfg_t;
  * channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the
  * application sets and clears bits in the corresponding Host Channel-n Interrupt register.
  */
-union cvmx_usbcx_haint
-{
+union cvmx_usbcx_haint {
 	uint32_t u32;
-	struct cvmx_usbcx_haint_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_haint_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_16_31               : 16;
 	uint32_t haint                        : 16; /**< Channel Interrupts (HAINT)
                                                          One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 */
@@ -3544,12 +3467,10 @@ typedef union cvmx_usbcx_haint cvmx_usbcx_haint_t;
  * interrupt mask bit per channel, up to a maximum of 16 bits.
  * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
  */
-union cvmx_usbcx_haintmsk
-{
+union cvmx_usbcx_haintmsk {
 	uint32_t u32;
-	struct cvmx_usbcx_haintmsk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_haintmsk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_16_31               : 16;
 	uint32_t haintmsk                     : 16; /**< Channel Interrupt Mask (HAINTMsk)
                                                          One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 */
@@ -3574,12 +3495,10 @@ typedef union cvmx_usbcx_haintmsk cvmx_usbcx_haintmsk_t;
  * Host Channel-n Characteristics Register (HCCHAR)
  *
  */
-union cvmx_usbcx_hccharx
-{
+union cvmx_usbcx_hccharx {
 	uint32_t u32;
-	struct cvmx_usbcx_hccharx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_hccharx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t chena                        : 1;  /**< Channel Enable (ChEna)
                                                          This field is set by the application and cleared by the OTG host.
                                                          * 1'b0: Channel disabled
@@ -3664,12 +3583,10 @@ typedef union cvmx_usbcx_hccharx cvmx_usbcx_hccharx_t;
  *
  * This register configures the core after power-on. Do not make changes to this register after initializing the host.
  */
-union cvmx_usbcx_hcfg
-{
+union cvmx_usbcx_hcfg {
 	uint32_t u32;
-	struct cvmx_usbcx_hcfg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_hcfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_3_31                : 29;
 	uint32_t fslssupp                     : 1;  /**< FS- and LS-Only Support (FSLSSupp)
                                                          The application uses this bit to control the core's enumeration
@@ -3726,12 +3643,10 @@ typedef union cvmx_usbcx_hcfg cvmx_usbcx_hcfg_t;
  * Interrupt register. The application must clear the appropriate bit in this register to clear the
  * corresponding bits in the HAINT and GINTSTS registers.
  */
-union cvmx_usbcx_hcintx
-{
+union cvmx_usbcx_hcintx {
 	uint32_t u32;
-	struct cvmx_usbcx_hcintx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_hcintx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_11_31               : 21;
 	uint32_t datatglerr                   : 1;  /**< Data Toggle Error (DataTglErr) */
 	uint32_t frmovrun                     : 1;  /**< Frame Overrun (FrmOvrun) */
@@ -3781,12 +3696,10 @@ typedef union cvmx_usbcx_hcintx cvmx_usbcx_hcintx_t;
  * This register reflects the mask for each channel status described in the previous section.
  * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
  */
-union cvmx_usbcx_hcintmskx
-{
+union cvmx_usbcx_hcintmskx {
 	uint32_t u32;
-	struct cvmx_usbcx_hcintmskx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_hcintmskx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_11_31               : 21;
 	uint32_t datatglerrmsk                : 1;  /**< Data Toggle Error Mask (DataTglErrMsk) */
 	uint32_t frmovrunmsk                  : 1;  /**< Frame Overrun Mask (FrmOvrunMsk) */
@@ -3830,12 +3743,10 @@ typedef union cvmx_usbcx_hcintmskx cvmx_usbcx_hcintmskx_t;
  * Host Channel-n Split Control Register (HCSPLT)
  *
  */
-union cvmx_usbcx_hcspltx
-{
+union cvmx_usbcx_hcspltx {
 	uint32_t u32;
-	struct cvmx_usbcx_hcspltx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_hcspltx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t spltena                      : 1;  /**< Split Enable (SpltEna)
                                                          The application sets this field to indicate that this channel is
                                                          enabled to perform split transactions. */
@@ -3885,12 +3796,10 @@ typedef union cvmx_usbcx_hcspltx cvmx_usbcx_hcspltx_t;
  * Host Channel-n Transfer Size Register (HCTSIZ)
  *
  */
-union cvmx_usbcx_hctsizx
-{
+union cvmx_usbcx_hctsizx {
 	uint32_t u32;
-	struct cvmx_usbcx_hctsizx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_hctsizx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t dopng                        : 1;  /**< Do Ping (DoPng)
                                                          Setting this field to 1 directs the host to do PING protocol. */
 	uint32_t pid                          : 2;  /**< PID (Pid)
@@ -3939,12 +3848,10 @@ typedef union cvmx_usbcx_hctsizx cvmx_usbcx_hctsizx_t;
  *
  * This register stores the frame interval information for the current speed to which the O2P USB core has enumerated.
  */
-union cvmx_usbcx_hfir
-{
+union cvmx_usbcx_hfir {
 	uint32_t u32;
-	struct cvmx_usbcx_hfir_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_hfir_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_16_31               : 16;
 	uint32_t frint                        : 16; /**< Frame Interval (FrInt)
                                                          The value that the application programs to this field specifies
@@ -3986,12 +3893,10 @@ typedef union cvmx_usbcx_hfir cvmx_usbcx_hfir_t;
  * It also indicates the time remaining (in terms of the number of PHY clocks)
  * in the current (micro)frame.
  */
-union cvmx_usbcx_hfnum
-{
+union cvmx_usbcx_hfnum {
 	uint32_t u32;
-	struct cvmx_usbcx_hfnum_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_hfnum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t frrem                        : 16; /**< Frame Time Remaining (FrRem)
                                                          Indicates the amount of time remaining in the current
                                                          microframe (HS) or frame (FS/LS), in terms of PHY clocks.
@@ -4030,12 +3935,10 @@ typedef union cvmx_usbcx_hfnum cvmx_usbcx_hfnum_t;
  * the bit that caused the interrupt. For the R_SS_WC bits, the application must write a 1 to the bit
  * to clear the interrupt.
  */
-union cvmx_usbcx_hprt
-{
+union cvmx_usbcx_hprt {
 	uint32_t u32;
-	struct cvmx_usbcx_hprt_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_hprt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_19_31               : 13;
 	uint32_t prtspd                       : 2;  /**< Port Speed (PrtSpd)
                                                          Indicates the speed of the device attached to this port.
@@ -4174,12 +4077,10 @@ typedef union cvmx_usbcx_hprt cvmx_usbcx_hprt_t;
  *
  * This register holds the size and the memory start address of the Periodic TxFIFO, as shown in Figures 310 and 311.
  */
-union cvmx_usbcx_hptxfsiz
-{
+union cvmx_usbcx_hptxfsiz {
 	uint32_t u32;
-	struct cvmx_usbcx_hptxfsiz_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_hptxfsiz_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ptxfsize                     : 16; /**< Host Periodic TxFIFO Depth (PTxFSize)
                                                          This value is in terms of 32-bit words.
                                                          * Minimum value is 16
@@ -4208,12 +4109,10 @@ typedef union cvmx_usbcx_hptxfsiz cvmx_usbcx_hptxfsiz_t;
  * This read-only register contains the free space information for the Periodic TxFIFO and
  * the Periodic Transmit Request Queue
  */
-union cvmx_usbcx_hptxsts
-{
+union cvmx_usbcx_hptxsts {
 	uint32_t u32;
-	struct cvmx_usbcx_hptxsts_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_hptxsts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t ptxqtop                      : 8;  /**< Top of the Periodic Transmit Request Queue (PTxQTop)
                                                          This indicates the entry in the Periodic Tx Request Queue that
                                                          is currently being processes by the MAC.
@@ -4272,12 +4171,10 @@ typedef union cvmx_usbcx_hptxsts cvmx_usbcx_hptxsts_t;
  *
  * A slave mode application uses this register to access the Tx FIFO for channel n.
  */
-union cvmx_usbcx_nptxdfifox
-{
+union cvmx_usbcx_nptxdfifox {
 	uint32_t u32;
-	struct cvmx_usbcx_nptxdfifox_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_nptxdfifox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t data                         : 32; /**< Reserved */
 #else
 	uint32_t data                         : 32;
@@ -4300,12 +4197,10 @@ typedef union cvmx_usbcx_nptxdfifox cvmx_usbcx_nptxdfifox_t;
  *
  * The application can use this register to control the core's power-down and clock gating features.
  */
-union cvmx_usbcx_pcgcctl
-{
+union cvmx_usbcx_pcgcctl {
 	uint32_t u32;
-	struct cvmx_usbcx_pcgcctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbcx_pcgcctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t reserved_5_31                : 27;
 	uint32_t physuspended                 : 1;  /**< PHY Suspended. (PhySuspended)
                                                          Indicates that the PHY has been suspended. After the
diff --git a/sys/contrib/octeon-sdk/cvmx-usbd.c b/sys/contrib/octeon-sdk/cvmx-usbd.c
index db2ab5d..85b8013 100644
--- a/sys/contrib/octeon-sdk/cvmx-usbd.c
+++ b/sys/contrib/octeon-sdk/cvmx-usbd.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-usbd.h b/sys/contrib/octeon-sdk/cvmx-usbd.h
index a43d841..eef7fcf 100644
--- a/sys/contrib/octeon-sdk/cvmx-usbd.h
+++ b/sys/contrib/octeon-sdk/cvmx-usbd.h
@@ -1,7 +1,7 @@
 #ifndef __CVMX_USBD_H__
 #define __CVMX_USBD_H__
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -17,7 +17,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -28,7 +28,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/contrib/octeon-sdk/cvmx-usbnx-defs.h b/sys/contrib/octeon-sdk/cvmx-usbnx-defs.h
index a8ce96a..6a952f8 100644
--- a/sys/contrib/octeon-sdk/cvmx-usbnx-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-usbnx-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_USBNX_TYPEDEFS_H__
-#define __CVMX_USBNX_TYPEDEFS_H__
+#ifndef __CVMX_USBNX_DEFS_H__
+#define __CVMX_USBNX_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_USBNX_BIST_STATUS(unsigned long block_id)
@@ -405,12 +405,10 @@ static inline uint64_t CVMX_USBNX_USBP_CTL_STATUS(unsigned long block_id)
  *
  * Contain general control bits and status information for the USBN.
  */
-union cvmx_usbnx_bist_status
-{
+union cvmx_usbnx_bist_status {
 	uint64_t u64;
-	struct cvmx_usbnx_bist_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t u2nc_bis                     : 1;  /**< Bist status U2N CTL FIFO Memory. */
 	uint64_t u2nf_bis                     : 1;  /**< Bist status U2N FIFO Memory. */
@@ -430,9 +428,8 @@ union cvmx_usbnx_bist_status
 	uint64_t reserved_7_63                : 57;
 #endif
 	} s;
-	struct cvmx_usbnx_bist_status_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_bist_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t usbc_bis                     : 1;  /**< Bist status USBC FIFO Memory. */
 	uint64_t nif_bis                      : 1;  /**< Bist status for Inbound Memory. */
@@ -460,12 +457,10 @@ typedef union cvmx_usbnx_bist_status cvmx_usbnx_bist_status_t;
  *
  * This register is used to control the frequency of the hclk and the hreset and phy_rst signals.
  */
-union cvmx_usbnx_clk_ctl
-{
+union cvmx_usbnx_clk_ctl {
 	uint64_t u64;
-	struct cvmx_usbnx_clk_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_clk_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t divide2                      : 2;  /**< The 'hclk' used by the USB subsystem is derived
                                                          from the eclk.
@@ -554,9 +549,8 @@ union cvmx_usbnx_clk_ctl
 	uint64_t reserved_20_63               : 44;
 #endif
 	} s;
-	struct cvmx_usbnx_clk_ctl_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_clk_ctl_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_18_63               : 46;
 	uint64_t hclk_rst                     : 1;  /**< When this field is '0' the HCLK-DIVIDER used to
                                                          generate the hclk in the USB Subsystem is held
@@ -640,9 +634,8 @@ union cvmx_usbnx_clk_ctl
 #endif
 	} cn30xx;
 	struct cvmx_usbnx_clk_ctl_cn30xx      cn31xx;
-	struct cvmx_usbnx_clk_ctl_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_clk_ctl_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_20_63               : 44;
 	uint64_t divide2                      : 2;  /**< The 'hclk' used by the USB subsystem is derived
                                                          from the eclk.
@@ -748,12 +741,10 @@ typedef union cvmx_usbnx_clk_ctl cvmx_usbnx_clk_ctl_t;
  *
  * Contains general control and status information for the USBN block.
  */
-union cvmx_usbnx_ctl_status
-{
+union cvmx_usbnx_ctl_status {
 	uint64_t u64;
-	struct cvmx_usbnx_ctl_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_6_63                : 58;
 	uint64_t dma_0pag                     : 1;  /**< When '1' sets the DMA engine will set the zero-Page
                                                          bit in the L2C store operation to the IOB. */
@@ -798,12 +789,10 @@ typedef union cvmx_usbnx_ctl_status cvmx_usbnx_ctl_status_t;
  * Contains the starting address for use when USB0 writes to L2C via Channel0.
  * Writing of this register sets the base address.
  */
-union cvmx_usbnx_dma0_inb_chn0
-{
+union cvmx_usbnx_dma0_inb_chn0 {
 	uint64_t u64;
-	struct cvmx_usbnx_dma0_inb_chn0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_dma0_inb_chn0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
 #else
@@ -829,12 +818,10 @@ typedef union cvmx_usbnx_dma0_inb_chn0 cvmx_usbnx_dma0_inb_chn0_t;
  * Contains the starting address for use when USB0 writes to L2C via Channel1.
  * Writing of this register sets the base address.
  */
-union cvmx_usbnx_dma0_inb_chn1
-{
+union cvmx_usbnx_dma0_inb_chn1 {
 	uint64_t u64;
-	struct cvmx_usbnx_dma0_inb_chn1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_dma0_inb_chn1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
 #else
@@ -860,12 +847,10 @@ typedef union cvmx_usbnx_dma0_inb_chn1 cvmx_usbnx_dma0_inb_chn1_t;
  * Contains the starting address for use when USB0 writes to L2C via Channel2.
  * Writing of this register sets the base address.
  */
-union cvmx_usbnx_dma0_inb_chn2
-{
+union cvmx_usbnx_dma0_inb_chn2 {
 	uint64_t u64;
-	struct cvmx_usbnx_dma0_inb_chn2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_dma0_inb_chn2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
 #else
@@ -891,12 +876,10 @@ typedef union cvmx_usbnx_dma0_inb_chn2 cvmx_usbnx_dma0_inb_chn2_t;
  * Contains the starting address for use when USB0 writes to L2C via Channel3.
  * Writing of this register sets the base address.
  */
-union cvmx_usbnx_dma0_inb_chn3
-{
+union cvmx_usbnx_dma0_inb_chn3 {
 	uint64_t u64;
-	struct cvmx_usbnx_dma0_inb_chn3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_dma0_inb_chn3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
 #else
@@ -922,12 +905,10 @@ typedef union cvmx_usbnx_dma0_inb_chn3 cvmx_usbnx_dma0_inb_chn3_t;
  * Contains the starting address for use when USB0 writes to L2C via Channel4.
  * Writing of this register sets the base address.
  */
-union cvmx_usbnx_dma0_inb_chn4
-{
+union cvmx_usbnx_dma0_inb_chn4 {
 	uint64_t u64;
-	struct cvmx_usbnx_dma0_inb_chn4_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_dma0_inb_chn4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
 #else
@@ -953,12 +934,10 @@ typedef union cvmx_usbnx_dma0_inb_chn4 cvmx_usbnx_dma0_inb_chn4_t;
  * Contains the starting address for use when USB0 writes to L2C via Channel5.
  * Writing of this register sets the base address.
  */
-union cvmx_usbnx_dma0_inb_chn5
-{
+union cvmx_usbnx_dma0_inb_chn5 {
 	uint64_t u64;
-	struct cvmx_usbnx_dma0_inb_chn5_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_dma0_inb_chn5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
 #else
@@ -984,12 +963,10 @@ typedef union cvmx_usbnx_dma0_inb_chn5 cvmx_usbnx_dma0_inb_chn5_t;
  * Contains the starting address for use when USB0 writes to L2C via Channel6.
  * Writing of this register sets the base address.
  */
-union cvmx_usbnx_dma0_inb_chn6
-{
+union cvmx_usbnx_dma0_inb_chn6 {
 	uint64_t u64;
-	struct cvmx_usbnx_dma0_inb_chn6_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_dma0_inb_chn6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
 #else
@@ -1015,12 +992,10 @@ typedef union cvmx_usbnx_dma0_inb_chn6 cvmx_usbnx_dma0_inb_chn6_t;
  * Contains the starting address for use when USB0 writes to L2C via Channel7.
  * Writing of this register sets the base address.
  */
-union cvmx_usbnx_dma0_inb_chn7
-{
+union cvmx_usbnx_dma0_inb_chn7 {
 	uint64_t u64;
-	struct cvmx_usbnx_dma0_inb_chn7_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_dma0_inb_chn7_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
 #else
@@ -1046,12 +1021,10 @@ typedef union cvmx_usbnx_dma0_inb_chn7 cvmx_usbnx_dma0_inb_chn7_t;
  * Contains the starting address for use when USB0 reads from L2C via Channel0.
  * Writing of this register sets the base address.
  */
-union cvmx_usbnx_dma0_outb_chn0
-{
+union cvmx_usbnx_dma0_outb_chn0 {
 	uint64_t u64;
-	struct cvmx_usbnx_dma0_outb_chn0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_dma0_outb_chn0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
 #else
@@ -1077,12 +1050,10 @@ typedef union cvmx_usbnx_dma0_outb_chn0 cvmx_usbnx_dma0_outb_chn0_t;
  * Contains the starting address for use when USB0 reads from L2C via Channel1.
  * Writing of this register sets the base address.
  */
-union cvmx_usbnx_dma0_outb_chn1
-{
+union cvmx_usbnx_dma0_outb_chn1 {
 	uint64_t u64;
-	struct cvmx_usbnx_dma0_outb_chn1_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_dma0_outb_chn1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
 #else
@@ -1108,12 +1079,10 @@ typedef union cvmx_usbnx_dma0_outb_chn1 cvmx_usbnx_dma0_outb_chn1_t;
  * Contains the starting address for use when USB0 reads from L2C via Channel2.
  * Writing of this register sets the base address.
  */
-union cvmx_usbnx_dma0_outb_chn2
-{
+union cvmx_usbnx_dma0_outb_chn2 {
 	uint64_t u64;
-	struct cvmx_usbnx_dma0_outb_chn2_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_dma0_outb_chn2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
 #else
@@ -1139,12 +1108,10 @@ typedef union cvmx_usbnx_dma0_outb_chn2 cvmx_usbnx_dma0_outb_chn2_t;
  * Contains the starting address for use when USB0 reads from L2C via Channel3.
  * Writing of this register sets the base address.
  */
-union cvmx_usbnx_dma0_outb_chn3
-{
+union cvmx_usbnx_dma0_outb_chn3 {
 	uint64_t u64;
-	struct cvmx_usbnx_dma0_outb_chn3_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_dma0_outb_chn3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
 #else
@@ -1170,12 +1137,10 @@ typedef union cvmx_usbnx_dma0_outb_chn3 cvmx_usbnx_dma0_outb_chn3_t;
  * Contains the starting address for use when USB0 reads from L2C via Channel4.
  * Writing of this register sets the base address.
  */
-union cvmx_usbnx_dma0_outb_chn4
-{
+union cvmx_usbnx_dma0_outb_chn4 {
 	uint64_t u64;
-	struct cvmx_usbnx_dma0_outb_chn4_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_dma0_outb_chn4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
 #else
@@ -1201,12 +1166,10 @@ typedef union cvmx_usbnx_dma0_outb_chn4 cvmx_usbnx_dma0_outb_chn4_t;
  * Contains the starting address for use when USB0 reads from L2C via Channel5.
  * Writing of this register sets the base address.
  */
-union cvmx_usbnx_dma0_outb_chn5
-{
+union cvmx_usbnx_dma0_outb_chn5 {
 	uint64_t u64;
-	struct cvmx_usbnx_dma0_outb_chn5_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_dma0_outb_chn5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
 #else
@@ -1232,12 +1195,10 @@ typedef union cvmx_usbnx_dma0_outb_chn5 cvmx_usbnx_dma0_outb_chn5_t;
  * Contains the starting address for use when USB0 reads from L2C via Channel6.
  * Writing of this register sets the base address.
  */
-union cvmx_usbnx_dma0_outb_chn6
-{
+union cvmx_usbnx_dma0_outb_chn6 {
 	uint64_t u64;
-	struct cvmx_usbnx_dma0_outb_chn6_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_dma0_outb_chn6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
 #else
@@ -1263,12 +1224,10 @@ typedef union cvmx_usbnx_dma0_outb_chn6 cvmx_usbnx_dma0_outb_chn6_t;
  * Contains the starting address for use when USB0 reads from L2C via Channel7.
  * Writing of this register sets the base address.
  */
-union cvmx_usbnx_dma0_outb_chn7
-{
+union cvmx_usbnx_dma0_outb_chn7 {
 	uint64_t u64;
-	struct cvmx_usbnx_dma0_outb_chn7_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_dma0_outb_chn7_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_36_63               : 28;
 	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
 #else
@@ -1293,12 +1252,10 @@ typedef union cvmx_usbnx_dma0_outb_chn7 cvmx_usbnx_dma0_outb_chn7_t;
  *
  * This register can cause the external DMA engine to the USB-Core to make transfers from/to L2C/USB-FIFOs
  */
-union cvmx_usbnx_dma_test
-{
+union cvmx_usbnx_dma_test {
 	uint64_t u64;
-	struct cvmx_usbnx_dma_test_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_dma_test_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_40_63               : 24;
 	uint64_t done                         : 1;  /**< This field is set when a DMA completes. Writing a
                                                          '1' to this field clears this bit. */
@@ -1337,12 +1294,10 @@ typedef union cvmx_usbnx_dma_test cvmx_usbnx_dma_test_t;
  *
  * The USBN's interrupt enable register.
  */
-union cvmx_usbnx_int_enb
-{
+union cvmx_usbnx_int_enb {
 	uint64_t u64;
-	struct cvmx_usbnx_int_enb_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_38_63               : 26;
 	uint64_t nd4o_dpf                     : 1;  /**< When set (1) and bit 37 of the USBN_INT_SUM
                                                          register is asserted the USBN will assert an
@@ -1502,9 +1457,8 @@ union cvmx_usbnx_int_enb
 	} s;
 	struct cvmx_usbnx_int_enb_s           cn30xx;
 	struct cvmx_usbnx_int_enb_s           cn31xx;
-	struct cvmx_usbnx_int_enb_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_int_enb_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_38_63               : 26;
 	uint64_t nd4o_dpf                     : 1;  /**< When set (1) and bit 37 of the USBN_INT_SUM
                                                          register is asserted the USBN will assert an
@@ -1654,12 +1608,10 @@ typedef union cvmx_usbnx_int_enb cvmx_usbnx_int_enb_t;
  *
  * Contains the diffrent interrupt summary bits of the USBN.
  */
-union cvmx_usbnx_int_sum
-{
+union cvmx_usbnx_int_sum {
 	uint64_t u64;
-	struct cvmx_usbnx_int_sum_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_38_63               : 26;
 	uint64_t nd4o_dpf                     : 1;  /**< NCB DMA Out Data Fifo Push Full. */
 	uint64_t nd4o_dpe                     : 1;  /**< NCB DMA Out Data Fifo Pop Empty. */
@@ -1743,9 +1695,8 @@ union cvmx_usbnx_int_sum
 	} s;
 	struct cvmx_usbnx_int_sum_s           cn30xx;
 	struct cvmx_usbnx_int_sum_s           cn31xx;
-	struct cvmx_usbnx_int_sum_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_int_sum_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_38_63               : 26;
 	uint64_t nd4o_dpf                     : 1;  /**< NCB DMA Out Data Fifo Push Full. */
 	uint64_t nd4o_dpe                     : 1;  /**< NCB DMA Out Data Fifo Pop Empty. */
@@ -1831,12 +1782,10 @@ typedef union cvmx_usbnx_int_sum cvmx_usbnx_int_sum_t;
  *
  * Contains general control and status information for the USBN block.
  */
-union cvmx_usbnx_usbp_ctl_status
-{
+union cvmx_usbnx_usbp_ctl_status {
 	uint64_t u64;
-	struct cvmx_usbnx_usbp_ctl_status_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_usbp_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t txrisetune                   : 1;  /**< HS Transmitter Rise/Fall Time Adjustment */
 	uint64_t txvreftune                   : 4;  /**< HS DC Voltage Level Adjustment */
 	uint64_t txfslstune                   : 4;  /**< FS/LS Source Impedence Adjustment */
@@ -1986,9 +1935,8 @@ union cvmx_usbnx_usbp_ctl_status
 	uint64_t txrisetune                   : 1;
 #endif
 	} s;
-	struct cvmx_usbnx_usbp_ctl_status_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_usbp_ctl_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_38_63               : 26;
 	uint64_t bist_done                    : 1;  /**< PHY Bist Done.
                                                          Asserted at the end of the PHY BIST sequence. */
@@ -2107,9 +2055,8 @@ union cvmx_usbnx_usbp_ctl_status
 #endif
 	} cn30xx;
 	struct cvmx_usbnx_usbp_ctl_status_cn30xx cn31xx;
-	struct cvmx_usbnx_usbp_ctl_status_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_usbp_ctl_status_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t txrisetune                   : 1;  /**< HS Transmitter Rise/Fall Time Adjustment */
 	uint64_t txvreftune                   : 4;  /**< HS DC Voltage Level Adjustment */
 	uint64_t txfslstune                   : 4;  /**< FS/LS Source Impedence Adjustment */
@@ -2239,9 +2186,8 @@ union cvmx_usbnx_usbp_ctl_status
 	uint64_t txrisetune                   : 1;
 #endif
 	} cn50xx;
-	struct cvmx_usbnx_usbp_ctl_status_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_usbnx_usbp_ctl_status_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t txrisetune                   : 1;  /**< HS Transmitter Rise/Fall Time Adjustment */
 	uint64_t txvreftune                   : 4;  /**< HS DC Voltage Level Adjustment */
 	uint64_t txfslstune                   : 4;  /**< FS/LS Source Impedence Adjustment */
diff --git a/sys/contrib/octeon-sdk/cvmx-utils.h b/sys/contrib/octeon-sdk/cvmx-utils.h
index 50e1762..6acd0fa 100644
--- a/sys/contrib/octeon-sdk/cvmx-utils.h
+++ b/sys/contrib/octeon-sdk/cvmx-utils.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -95,7 +95,6 @@ extern "C" {
 
 #define CAST64(v) ((long long)(long)(v)) // use only when 'v' is a pointer
 #define CASTPTR(type, v) ((type *)(long)(v))
-#define CVMX_MAX_CORES          (16)
 #define CVMX_CACHE_LINE_SIZE    (128)   // In bytes
 #define CVMX_CACHE_LINE_MASK    (CVMX_CACHE_LINE_SIZE - 1)   // In bytes
 #define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned (CVMX_CACHE_LINE_SIZE)))
@@ -130,6 +129,9 @@ extern "C" {
     } while (0);                                                        \
     result;})
 
+#define CVMX_BUILD_ASSERT_ZERO(e)    (sizeof(struct {int __static_assert:(e)?1:-1;}))
+#define CVMX_BUILD_ASSERT(condition) ((void)CVMX_BUILD_ASSERT_ZERO(condition))
+
 /**
  * Builds a bit mask given the required size in bits.
  *
@@ -185,7 +187,7 @@ static inline uint64_t cvmx_build_bits(uint64_t high_bit, uint64_t low_bit, uint
  */
 static inline uint32_t cvmx_octeon_num_cores(void)
 {
-    uint32_t ciu_fuse = (uint32_t)cvmx_read_csr(CVMX_CIU_FUSE) & 0xffff;
+    uint32_t ciu_fuse = (uint32_t)cvmx_read_csr(CVMX_CIU_FUSE) & 0xffffffffull;
     return cvmx_pop(ciu_fuse);
 }
 
@@ -202,80 +204,6 @@ static inline int cvmx_octeon_model_CN36XX(void)
 }
 
 
-/**
- * @deprecated
- * Determine if Octeon supports the DFA state machines. This function is
- * deprecated, use octeon_has_feature(OCTEON_FEATURE_DFA) instead.
- *
- * @return Non zero if DFA is supported
- */
-static inline int cvmx_octeon_dfa_present(void) __attribute__((deprecated));
-static inline int cvmx_octeon_dfa_present(void)
-{
-    return octeon_has_feature(OCTEON_FEATURE_DFA);
-}
-
-
-/**
- * @deprecated
- * Determine if Octeon supports ZIP. This function is deprecated, use
- * octeon_has_feature(OCTEON_FEATURE_ZIP) instead.
- *
- * @return Non zero if DFA is supported
- */
-static inline int cvmx_octeon_zip_present(void) __attribute__((deprecated));
-static inline int cvmx_octeon_zip_present(void)
-{
-    return octeon_has_feature(OCTEON_FEATURE_ZIP);
-}
-
-
-/**
- * @deprecated
- * Determine if Octeon supports Crypto acceleration. This function is
- * deprecated, use octeon_has_feature(OCTEON_FEATURE_CRYPTO) instead.
- *
- * @return Non zero if DFA is supported
- */
-static inline int cvmx_octeon_crypto_present(void) __attribute__((deprecated));
-static inline int cvmx_octeon_crypto_present(void)
-{
-    return octeon_has_feature(OCTEON_FEATURE_CRYPTO);
-}
-
-
-/**
- * @deprecated
- * This function is a trival wrapper around cvmx_read64_uint64(). Use
- * cvmx_read64_uint64() instead as this function is deprecated.
- *
- * @param address
- *
- * @return
- */
-static inline uint64_t cvmx_read64(uint64_t address) __attribute__((deprecated));
-static inline uint64_t cvmx_read64(uint64_t address)
-{
-    return cvmx_read64_uint64(address);
-}
-
-
-/**
- * @deprecated
- * This function is a trival wrapper around cvmx_write64_uint64(). Use
- * cvmx_write64_uint64() instead as this function is deprecated.
- *
- * @param address Location to write ro
- * @param value Value to write
- *
- * @return
- */
-static inline void cvmx_write64(uint64_t address, uint64_t value) __attribute__((deprecated));
-static inline void cvmx_write64(uint64_t address, uint64_t value)
-{
-    cvmx_write64_uint64(address, value);
-}
-
 #ifdef	__cplusplus
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-version.h b/sys/contrib/octeon-sdk/cvmx-version.h
index c4901b2..52c6e1c 100644
--- a/sys/contrib/octeon-sdk/cvmx-version.h
+++ b/sys/contrib/octeon-sdk/cvmx-version.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2007  Cavium Networks (support@cavium.com). All rights 
+ * Copyright (c) 2011 Cavium Inc. (support@cavium.com). All rights 
  * reserved.
  * 
  * 
@@ -15,13 +15,13 @@
  *       disclaimer in the documentation and/or other materials provided
  *       with the distribution.
  * 
- *     * Neither the name of Cavium Networks nor the names of
+ *     * Neither the name of Cavium Inc. nor the names of
  *       its contributors may be used to endorse or promote products
  *       derived from this software without specific prior written
  *       permission.  
  * 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS 
  * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 
  * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 
  * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 
@@ -44,5 +44,5 @@
 **     10.9.0 == 10.09.00 > 09.10.00 == 9.10.0 
 ** 
 */ 
-#define OCTEON_SDK_VERSION_NUM  200000366ull
-#define OCTEON_SDK_VERSION_STRING   "Cavium Networks Octeon SDK version 2.0.0, build 366"
+#define OCTEON_SDK_VERSION_NUM  203000427ull
+#define OCTEON_SDK_VERSION_STRING   "Cavium Inc. OCTEON SDK version 2.3.0, build 427"
diff --git a/sys/contrib/octeon-sdk/cvmx-warn.c b/sys/contrib/octeon-sdk/cvmx-warn.c
index f0c4d1d..4f1464a 100644
--- a/sys/contrib/octeon-sdk/cvmx-warn.c
+++ b/sys/contrib/octeon-sdk/cvmx-warn.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Functions for warning users about errors and such.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 #include "cvmx.h"
@@ -63,7 +63,11 @@ void cvmx_warn(const char *format, ...)
         /* If the serial port is not set up yet,
         ** save pointer to error message (most likely a constant in flash)
         ** to print out once we can. */
-        gd->err_msg = (void *)format;
+#ifdef U_BOOT_OLD
+	gd->err_msg = (void *)format;
+#else
+	gd->ogd.err_msg = (void *)format;
+#endif
         return;
     }
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-warn.h b/sys/contrib/octeon-sdk/cvmx-warn.h
index 264a613..5223cac 100644
--- a/sys/contrib/octeon-sdk/cvmx-warn.h
+++ b/sys/contrib/octeon-sdk/cvmx-warn.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Functions for warning users about errors and such.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 #ifndef __CVMX_WARN_H__
@@ -58,11 +58,13 @@
 extern "C" {
 #endif
 
+#ifndef cvmx_warn
 #ifdef printf
 extern void cvmx_warn(const char *format, ...);
 #else
 extern void cvmx_warn(const char *format, ...) __attribute__ ((format(printf, 1, 2)));
 #endif
+#endif
 
 #define cvmx_warn_if(expression, format, ...) if (expression) cvmx_warn(format, ##__VA_ARGS__)
 
diff --git a/sys/contrib/octeon-sdk/cvmx-wqe.h b/sys/contrib/octeon-sdk/cvmx-wqe.h
index 0f8fb8f..93f2ce7 100644
--- a/sys/contrib/octeon-sdk/cvmx-wqe.h
+++ b/sys/contrib/octeon-sdk/cvmx-wqe.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -52,7 +52,7 @@
  * This file must not depend on any other header files, except for cvmx.h!!!
  *
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  *
  */
@@ -87,8 +87,7 @@ typedef union
         uint64_t               unassigned    : 1;
         uint64_t               vlan_cfi      : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
         uint64_t               vlan_id       :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
-        uint64_t               pr            : 4; /**< Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
-        uint64_t               unassigned2   : 8;
+	    uint64_t varies:12; /**< 38xx and 68xx have different definitions.  */
         uint64_t               dec_ipcomp    : 1; /**< the packet needs to be decompressed */
         uint64_t               tcp_or_udp    : 1; /**< the packet is either TCP or UDP */
         uint64_t               dec_ipsec     : 1; /**< the packet needs to be decrypted (ESP or AH) */
@@ -135,6 +134,123 @@ typedef union
 
         uint64_t               err_code      : 8; /**< type is cvmx_pip_err_t */
     } s;
+    struct
+    {
+        uint64_t               bufs          : 8; /**< HW sets this to the number of buffers used by this packet */
+        uint64_t               ip_offset     : 8; /**< HW sets to the number of L2 bytes prior to the IP */
+        uint64_t               vlan_valid    : 1; /**< set to 1 if we found DSA/VLAN in the L2 */
+        uint64_t               vlan_stacked  : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */
+        uint64_t               unassigned    : 1;
+        uint64_t               vlan_cfi      : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
+        uint64_t               vlan_id       :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
+
+	    uint64_t port:12;  /**< MAC/PIP port number.  */
+
+        uint64_t               dec_ipcomp    : 1; /**< the packet needs to be decompressed */
+        uint64_t               tcp_or_udp    : 1; /**< the packet is either TCP or UDP */
+        uint64_t               dec_ipsec     : 1; /**< the packet needs to be decrypted (ESP or AH) */
+        uint64_t               is_v6         : 1; /**< the packet is IPv6 */
+
+      /* (rcv_error, not_IP, IP_exc, is_frag, L4_error, software, etc.) */
+
+        uint64_t               software      : 1; /**< reserved for software use, hardware will clear on packet creation */
+      /* exceptional conditions below */
+        uint64_t               L4_error      : 1; /**< the receive interface hardware detected an L4 error (only applies if !is_frag)
+                                                    (only applies if !rcv_error && !not_IP && !IP_exc && !is_frag)
+                                                    failure indicated in err_code below, decode:
+                                                    - 1 = Malformed L4
+                                                    - 2 = L4 Checksum Error: the L4 checksum value is
+                                                    - 3 = UDP Length Error: The UDP length field would make the UDP data longer than what
+                                                        remains in the IP packet (as defined by the IP header length field).
+                                                    - 4 = Bad L4 Port: either the source or destination TCP/UDP port is 0.
+                                                    - 8 = TCP FIN Only: the packet is TCP and only the FIN flag set.
+                                                    - 9 = TCP No Flags: the packet is TCP and no flags are set.
+                                                    - 10 = TCP FIN RST: the packet is TCP and both FIN and RST are set.
+                                                    - 11 = TCP SYN URG: the packet is TCP and both SYN and URG are set.
+                                                    - 12 = TCP SYN RST: the packet is TCP and both SYN and RST are set.
+                                                    - 13 = TCP SYN FIN: the packet is TCP and both SYN and FIN are set. */
+
+
+
+        uint64_t               is_frag       : 1; /**< set if the packet is a fragment */
+        uint64_t               IP_exc        : 1; /**< the receive interface hardware detected an IP error / exception
+                                                    (only applies if !rcv_error && !not_IP) failure indicated in err_code below, decode:
+                                                    - 1 = Not IP: the IP version field is neither 4 nor 6.
+                                                    - 2 = IPv4 Header Checksum Error: the IPv4 header has a checksum violation.
+                                                    - 3 = IP Malformed Header: the packet is not long enough to contain the IP header.
+                                                    - 4 = IP Malformed: the packet is not long enough to contain the bytes indicated by the IP
+                                                        header. Pad is allowed.
+                                                    - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6 Hop Count field are zero.
+                                                    - 6 = IP Options */
+
+        uint64_t               is_bcast      : 1; /**< set if the hardware determined that the packet is a broadcast */
+        uint64_t               is_mcast      : 1; /**< set if the hardware determined that the packet is a multi-cast */
+        uint64_t               not_IP        : 1; /**< set if the packet may not be IP (must be zero in this case) */
+        uint64_t               rcv_error     : 1; /**< the receive interface hardware detected a receive error (must be zero in this case) */
+        /* lower err_code = first-level descriptor of the work */
+        /* zero for packet submitted by hardware that isn't on the slow path */
+
+        uint64_t               err_code      : 8; /**< type is cvmx_pip_err_t */
+    } s_cn68xx;
+    struct
+    {
+        uint64_t               bufs          : 8; /**< HW sets this to the number of buffers used by this packet */
+        uint64_t               ip_offset     : 8; /**< HW sets to the number of L2 bytes prior to the IP */
+        uint64_t               vlan_valid    : 1; /**< set to 1 if we found DSA/VLAN in the L2 */
+        uint64_t               vlan_stacked  : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */
+        uint64_t               unassigned    : 1;
+        uint64_t               vlan_cfi      : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
+        uint64_t               vlan_id       :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
+        uint64_t               pr            : 4; /**< Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
+        uint64_t               unassigned2a  :4;
+        uint64_t               unassigned2   :4;
+
+        uint64_t               dec_ipcomp    : 1; /**< the packet needs to be decompressed */
+        uint64_t               tcp_or_udp    : 1; /**< the packet is either TCP or UDP */
+        uint64_t               dec_ipsec     : 1; /**< the packet needs to be decrypted (ESP or AH) */
+        uint64_t               is_v6         : 1; /**< the packet is IPv6 */
+
+      /* (rcv_error, not_IP, IP_exc, is_frag, L4_error, software, etc.) */
+
+        uint64_t               software      : 1; /**< reserved for software use, hardware will clear on packet creation */
+      /* exceptional conditions below */
+        uint64_t               L4_error      : 1; /**< the receive interface hardware detected an L4 error (only applies if !is_frag)
+                                                    (only applies if !rcv_error && !not_IP && !IP_exc && !is_frag)
+                                                    failure indicated in err_code below, decode:
+                                                    - 1 = Malformed L4
+                                                    - 2 = L4 Checksum Error: the L4 checksum value is
+                                                    - 3 = UDP Length Error: The UDP length field would make the UDP data longer than what
+                                                        remains in the IP packet (as defined by the IP header length field).
+                                                    - 4 = Bad L4 Port: either the source or destination TCP/UDP port is 0.
+                                                    - 8 = TCP FIN Only: the packet is TCP and only the FIN flag set.
+                                                    - 9 = TCP No Flags: the packet is TCP and no flags are set.
+                                                    - 10 = TCP FIN RST: the packet is TCP and both FIN and RST are set.
+                                                    - 11 = TCP SYN URG: the packet is TCP and both SYN and URG are set.
+                                                    - 12 = TCP SYN RST: the packet is TCP and both SYN and RST are set.
+                                                    - 13 = TCP SYN FIN: the packet is TCP and both SYN and FIN are set. */
+
+
+
+        uint64_t               is_frag       : 1; /**< set if the packet is a fragment */
+        uint64_t               IP_exc        : 1; /**< the receive interface hardware detected an IP error / exception
+                                                    (only applies if !rcv_error && !not_IP) failure indicated in err_code below, decode:
+                                                    - 1 = Not IP: the IP version field is neither 4 nor 6.
+                                                    - 2 = IPv4 Header Checksum Error: the IPv4 header has a checksum violation.
+                                                    - 3 = IP Malformed Header: the packet is not long enough to contain the IP header.
+                                                    - 4 = IP Malformed: the packet is not long enough to contain the bytes indicated by the IP
+                                                        header. Pad is allowed.
+                                                    - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6 Hop Count field are zero.
+                                                    - 6 = IP Options */
+
+        uint64_t               is_bcast      : 1; /**< set if the hardware determined that the packet is a broadcast */
+        uint64_t               is_mcast      : 1; /**< set if the hardware determined that the packet is a multi-cast */
+        uint64_t               not_IP        : 1; /**< set if the packet may not be IP (must be zero in this case) */
+        uint64_t               rcv_error     : 1; /**< the receive interface hardware detected a receive error (must be zero in this case) */
+        /* lower err_code = first-level descriptor of the work */
+        /* zero for packet submitted by hardware that isn't on the slow path */
+
+        uint64_t               err_code      : 8; /**< type is cvmx_pip_err_t */
+    } s_cn38xx;
 
     /**< use this to get at the 16 vlan bits */
     struct
@@ -154,8 +270,10 @@ typedef union
         uint64_t               unassigned    : 1;
         uint64_t               vlan_cfi      : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
         uint64_t               vlan_id       :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
-        uint64_t               pr            : 4; /**< Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
-        uint64_t               unassigned2   :12;
+
+	    uint64_t varies:12; /**< 38xx and 68xx have different definitions.  */
+	    uint64_t unassigned2:4;
+
         uint64_t               software      : 1; /**< reserved for software use, hardware will clear on packet creation */
         uint64_t               unassigned3   : 1;
         uint64_t               is_rarp       : 1; /**< set if the hardware determined that the packet is rarp */
@@ -198,8 +316,209 @@ typedef union
         /* zero for packet submitted by hardware that isn't on the slow path */
       uint64_t               err_code       : 8; /* type is cvmx_pip_err_t (union, so can't use directly */
     } snoip;
+    struct
+    {
+        uint64_t               bufs          : 8; /**< HW sets this to the number of buffers used by this packet */
+        uint64_t               unused        : 8;
+        uint64_t               vlan_valid    : 1; /**< set to 1 if we found DSA/VLAN in the L2 */
+        uint64_t               vlan_stacked  : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */
+        uint64_t               unassigned    : 1;
+        uint64_t               vlan_cfi      : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
+        uint64_t               vlan_id       :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
 
-} cvmx_pip_wqe_word2;
+	    uint64_t port:12; /**< MAC/PIP port number.  */
+	    uint64_t unassigned2:4;
+
+        uint64_t               software      : 1; /**< reserved for software use, hardware will clear on packet creation */
+        uint64_t               unassigned3   : 1;
+        uint64_t               is_rarp       : 1; /**< set if the hardware determined that the packet is rarp */
+        uint64_t               is_arp        : 1; /**< set if the hardware determined that the packet is arp */
+        uint64_t               is_bcast      : 1; /**< set if the hardware determined that the packet is a broadcast */
+        uint64_t               is_mcast      : 1; /**< set if the hardware determined that the packet is a multi-cast */
+        uint64_t               not_IP        : 1; /**< set if the packet may not be IP (must be one in this case) */
+        uint64_t               rcv_error     : 1; /**< the receive interface hardware detected a receive error.
+                                                    Failure indicated in err_code below, decode:
+                                                    - 1 = partial error: a packet was partially received, but internal
+                                                        buffering / bandwidth was not adequate to receive the entire packet.
+                                                    - 2 = jabber error: the RGMII packet was too large and is truncated.
+                                                    - 3 = overrun error: the RGMII packet is longer than allowed and had
+                                                        an FCS error.
+                                                    - 4 = oversize error: the RGMII packet is longer than allowed.
+                                                    - 5 = alignment error: the RGMII packet is not an integer number of bytes
+                                                        and had an FCS error (100M and 10M only).
+                                                    - 6 = fragment error: the RGMII packet is shorter than allowed and had an
+                                                        FCS error.
+                                                    - 7 = GMX FCS error: the RGMII packet had an FCS error.
+                                                    - 8 = undersize error: the RGMII packet is shorter than allowed.
+                                                    - 9 = extend error: the RGMII packet had an extend error.
+                                                    - 10 = length mismatch error: the RGMII packet had a length that did not
+                                                        match the length field in the L2 HDR.
+                                                    - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII packet had one or more
+                                                        data reception errors (RXERR) or the SPI4 packet had one or more DIP4
+                                                        errors.
+                                                    - 12 = RGMII skip error/SPI4 Abort Error: the RGMII packet was not large
+                                                        enough to cover the skipped bytes or the SPI4 packet was terminated
+                                                        with an About EOPS.
+                                                    - 13 = RGMII nibble error/SPI4 Port NXA Error: the RGMII packet had a
+                                                        studder error (data not repeated - 10/100M only) or the SPI4 packet
+                                                        was sent to an NXA.
+                                                    - 16 = FCS error: a SPI4.2 packet had an FCS error.
+                                                    - 17 = Skip error: a packet was not large enough to cover the skipped bytes.
+                                                    - 18 = L2 header malformed: the packet is not long enough to contain the L2 */
+
+
+        /* lower err_code = first-level descriptor of the work */
+        /* zero for packet submitted by hardware that isn't on the slow path */
+      uint64_t               err_code       : 8; /* type is cvmx_pip_err_t (union, so can't use directly */
+    } snoip_cn68xx;
+    struct
+    {
+        uint64_t               bufs          : 8; /**< HW sets this to the number of buffers used by this packet */
+        uint64_t               unused        : 8;
+        uint64_t               vlan_valid    : 1; /**< set to 1 if we found DSA/VLAN in the L2 */
+        uint64_t               vlan_stacked  : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */
+        uint64_t               unassigned    : 1;
+        uint64_t               vlan_cfi      : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
+        uint64_t               vlan_id       :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
+        uint64_t               pr            : 4; /**< Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
+        uint64_t               unassigned2a  :8;
+        uint64_t               unassigned2   :4;
+
+        uint64_t               software      : 1; /**< reserved for software use, hardware will clear on packet creation */
+        uint64_t               unassigned3   : 1;
+        uint64_t               is_rarp       : 1; /**< set if the hardware determined that the packet is rarp */
+        uint64_t               is_arp        : 1; /**< set if the hardware determined that the packet is arp */
+        uint64_t               is_bcast      : 1; /**< set if the hardware determined that the packet is a broadcast */
+        uint64_t               is_mcast      : 1; /**< set if the hardware determined that the packet is a multi-cast */
+        uint64_t               not_IP        : 1; /**< set if the packet may not be IP (must be one in this case) */
+        uint64_t               rcv_error     : 1; /**< the receive interface hardware detected a receive error.
+                                                    Failure indicated in err_code below, decode:
+                                                    - 1 = partial error: a packet was partially received, but internal
+                                                        buffering / bandwidth was not adequate to receive the entire packet.
+                                                    - 2 = jabber error: the RGMII packet was too large and is truncated.
+                                                    - 3 = overrun error: the RGMII packet is longer than allowed and had
+                                                        an FCS error.
+                                                    - 4 = oversize error: the RGMII packet is longer than allowed.
+                                                    - 5 = alignment error: the RGMII packet is not an integer number of bytes
+                                                        and had an FCS error (100M and 10M only).
+                                                    - 6 = fragment error: the RGMII packet is shorter than allowed and had an
+                                                        FCS error.
+                                                    - 7 = GMX FCS error: the RGMII packet had an FCS error.
+                                                    - 8 = undersize error: the RGMII packet is shorter than allowed.
+                                                    - 9 = extend error: the RGMII packet had an extend error.
+                                                    - 10 = length mismatch error: the RGMII packet had a length that did not
+                                                        match the length field in the L2 HDR.
+                                                    - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII packet had one or more
+                                                        data reception errors (RXERR) or the SPI4 packet had one or more DIP4
+                                                        errors.
+                                                    - 12 = RGMII skip error/SPI4 Abort Error: the RGMII packet was not large
+                                                        enough to cover the skipped bytes or the SPI4 packet was terminated
+                                                        with an About EOPS.
+                                                    - 13 = RGMII nibble error/SPI4 Port NXA Error: the RGMII packet had a
+                                                        studder error (data not repeated - 10/100M only) or the SPI4 packet
+                                                        was sent to an NXA.
+                                                    - 16 = FCS error: a SPI4.2 packet had an FCS error.
+                                                    - 17 = Skip error: a packet was not large enough to cover the skipped bytes.
+                                                    - 18 = L2 header malformed: the packet is not long enough to contain the L2 */
+
+
+        /* lower err_code = first-level descriptor of the work */
+        /* zero for packet submitted by hardware that isn't on the slow path */
+      uint64_t               err_code       : 8; /* type is cvmx_pip_err_t (union, so can't use directly */
+    } snoip_cn38xx;
+
+} cvmx_pip_wqe_word2_t;
+
+typedef union {
+	struct {
+		/**
+		 * raw chksum result generated by the HW
+		 */
+		uint16_t                   hw_chksum;
+		/**
+		 * Field unused by hardware - available for software
+		 */
+		uint8_t                    unused;
+		/**
+		 * Next pointer used by hardware for list maintenance.
+		 * May be written/read by HW before the work queue
+		 * entry is scheduled to a PP (Only 36 bits used in
+		 * Octeon 1)
+		 */
+		uint64_t                   next_ptr      : 40;
+
+	} cn38xx;
+	struct {
+		uint64_t l4ptr:8;	/* 56..63 */
+		uint64_t unused0:8;	/* 48..55 */
+		uint64_t l3ptr:8;	/* 40..47 */
+		uint64_t l2ptr:8;	/* 32..39 */
+		uint64_t unused1:18;	/* 14..31 */
+		uint64_t bpid:6;	/* 8..13 */
+		uint64_t unused2:2;	/* 6..7 */
+		uint64_t pknd:6;	/* 0..5 */
+	} cn68xx;
+} cvmx_pip_wqe_word0_t;
+
+typedef union {
+	uint64_t u64;
+	cvmx_pip_wqe_word0_t pip;
+	struct {
+		uint64_t unused:24;
+		uint64_t next_ptr:40; /* on cn68xx this is unused as well */
+
+	} raw;
+} cvmx_wqe_word0_t;
+
+typedef union {
+	uint64_t u64;
+	struct {
+		uint64_t len:16;
+		uint64_t varies:14;
+		/**
+		 * the type of the tag (ORDERED, ATOMIC, NULL)
+		 */
+		cvmx_pow_tag_type_t tag_type:2;
+		uint64_t tag:32;
+	} s;
+	struct {
+		uint64_t len:16;
+		uint64_t zero_0:1;
+		/**
+		 * HW sets this to what it thought the priority of the input packet was
+		 */
+		uint64_t qos:3;
+
+		uint64_t zero_1:1;
+		/**
+		 * the group that the work queue entry will be scheduled to
+		 */
+		uint64_t grp:6;
+		uint64_t zero_2:3;
+		cvmx_pow_tag_type_t tag_type:2;
+		uint64_t tag:32;
+	} cn68xx;
+	struct {
+		uint64_t len:16;
+		/**
+		 * HW sets this to input physical port
+		 */
+		uint64_t ipprt:6;
+
+		/**
+		 * HW sets this to what it thought the priority of the input packet was
+		 */
+		uint64_t qos:3;
+
+		/**
+		 * the group that the work queue entry will be scheduled to
+		 */
+		uint64_t grp:4;
+		uint64_t zero_2:1;
+		cvmx_pow_tag_type_t tag_type:2;
+		uint64_t tag:32;
+	} cn38xx;
+} cvmx_wqe_word1_t;
 
 /**
  * Work queue entry format
@@ -214,61 +533,20 @@ typedef struct
      *  HW WRITE: the following 64 bits are filled by HW when a packet arrives
      */
 
-    /**
-     * raw chksum result generated by the HW
-     */
-    uint16_t                   hw_chksum;
-    /**
-     * Field unused by hardware - available for software
-     */
-    uint8_t                    unused;
-    /**
-     * Next pointer used by hardware for list maintenance.
-     * May be written/read by HW before the work queue
-     *           entry is scheduled to a PP
-     * (Only 36 bits used in Octeon 1)
-     */
-    uint64_t                   next_ptr      : 40;
-
+	cvmx_wqe_word0_t word0;
 
     /*****************************************************************
      * WORD 1
      *  HW WRITE: the following 64 bits are filled by HW when a packet arrives
      */
 
-    /**
-     * HW sets to the total number of bytes in the packet
-     */
-    uint64_t                   len           :16;
-    /**
-     * HW sets this to input physical port
-     */
-    uint64_t                   ipprt         : 6;
-
-    /**
-     * HW sets this to what it thought the priority of the input packet was
-     */
-    uint64_t                   qos           : 3;
-
-    /**
-     * the group that the work queue entry will be scheduled to
-     */
-    uint64_t                   grp           : 4;
-    /**
-     * the type of the tag (ORDERED, ATOMIC, NULL)
-     */
-    cvmx_pow_tag_type_t        tag_type      : 3;
-    /**
-     * the synchronization/ordering tag
-     */
-    uint64_t                   tag           :32;
-
+	cvmx_wqe_word1_t word1;
     /**
      * WORD 2
      *   HW WRITE: the following 64-bits are filled in by hardware when a packet arrives
      *   This indicates a variety of status and error conditions.
      */
-    cvmx_pip_wqe_word2       word2;
+    cvmx_pip_wqe_word2_t       word2;
 
     /**
      * Pointer to the first segment of the packet.
@@ -297,6 +575,135 @@ typedef struct
 
 }  CVMX_CACHE_LINE_ALIGNED cvmx_wqe_t;
 
+static inline int cvmx_wqe_get_port(cvmx_wqe_t *work)
+{
+    int port;
+
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+	port = work->word2.s_cn68xx.port;
+    else
+	port = work->word1.cn38xx.ipprt;
+
+    return port;
+}
+
+static inline void cvmx_wqe_set_port(cvmx_wqe_t *work, int port)
+{
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+	port = work->word2.s_cn68xx.port = port;
+    else
+	port = work->word1.cn38xx.ipprt = port;
+}
+
+static inline int cvmx_wqe_get_grp(cvmx_wqe_t *work)
+{
+    int grp;
+
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+	grp = work->word1.cn68xx.grp;
+    else
+	grp = work->word1.cn38xx.grp;
+
+    return grp;
+}
+
+static inline void cvmx_wqe_set_grp(cvmx_wqe_t *work, int grp)
+{
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+	work->word1.cn68xx.grp = grp;
+    else
+	work->word1.cn38xx.grp = grp;
+}
+
+static inline int cvmx_wqe_get_qos(cvmx_wqe_t *work)
+{
+    int qos;
+
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+	qos = work->word1.cn68xx.qos;
+    else
+	qos = work->word1.cn38xx.qos;
+
+    return qos;
+}
+
+static inline void cvmx_wqe_set_qos(cvmx_wqe_t *work, int qos)
+{
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+	work->word1.cn68xx.qos = qos;
+    else
+	work->word1.cn38xx.qos = qos;
+}
+
+static inline int cvmx_wqe_get_len(cvmx_wqe_t *work)
+{
+    int len;
+
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+	len = work->word1.cn68xx.len;
+    else
+	len = work->word1.cn38xx.len;
+
+    return len;
+}
+
+static inline void cvmx_wqe_set_len(cvmx_wqe_t *work, int len)
+{
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+	work->word1.cn68xx.len = len;
+    else
+	work->word1.cn38xx.len = len;
+}
+
+static inline uint32_t cvmx_wqe_get_tag(cvmx_wqe_t *work)
+{
+    return work->word1.s.tag;
+}
+
+static inline void cvmx_wqe_set_tag(cvmx_wqe_t *work, uint32_t  tag)
+{
+    work->word1.s.tag = tag;
+}
+
+static inline int cvmx_wqe_get_tt(cvmx_wqe_t *work)
+{
+    return work->word1.s.tag_type;
+}
+
+static inline void cvmx_wqe_set_tt(cvmx_wqe_t *work, int tt)
+{
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+    {
+	work->word1.cn68xx.tag_type = (cvmx_pow_tag_type_t)tt;
+        work->word1.cn68xx.zero_2 = 0;
+    }
+    else
+    {
+	work->word1.cn38xx.tag_type = (cvmx_pow_tag_type_t)tt;
+        work->word1.cn38xx.zero_2 = 0;
+    }
+}
+
+static inline int cvmx_wqe_get_unused8(cvmx_wqe_t *work)
+{
+    int len;
+
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+	len = work->word0.pip.cn68xx.unused1;
+    else
+	len = work->word0.pip.cn38xx.unused;
+
+    return len;
+}
+
+static inline void cvmx_wqe_set_unused8(cvmx_wqe_t *work, int v)
+{
+    if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+	work->word0.pip.cn68xx.unused1 = v;
+    else
+	work->word0.pip.cn38xx.unused = v;
+}
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-zip-defs.h b/sys/contrib/octeon-sdk/cvmx-zip-defs.h
index b1c7d23..483d225 100644
--- a/sys/contrib/octeon-sdk/cvmx-zip-defs.h
+++ b/sys/contrib/octeon-sdk/cvmx-zip-defs.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,14 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_ZIP_TYPEDEFS_H__
-#define __CVMX_ZIP_TYPEDEFS_H__
+#ifndef __CVMX_ZIP_DEFS_H__
+#define __CVMX_ZIP_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_ZIP_CMD_BIST_RESULT CVMX_ZIP_CMD_BIST_RESULT_FUNC()
 static inline uint64_t CVMX_ZIP_CMD_BIST_RESULT_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_ZIP_CMD_BIST_RESULT not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180038000080ull);
 }
@@ -67,7 +67,7 @@ static inline uint64_t CVMX_ZIP_CMD_BIST_RESULT_FUNC(void)
 #define CVMX_ZIP_CMD_BUF CVMX_ZIP_CMD_BUF_FUNC()
 static inline uint64_t CVMX_ZIP_CMD_BUF_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_ZIP_CMD_BUF not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180038000008ull);
 }
@@ -78,7 +78,7 @@ static inline uint64_t CVMX_ZIP_CMD_BUF_FUNC(void)
 #define CVMX_ZIP_CMD_CTL CVMX_ZIP_CMD_CTL_FUNC()
 static inline uint64_t CVMX_ZIP_CMD_CTL_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_ZIP_CMD_CTL not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180038000000ull);
 }
@@ -89,7 +89,7 @@ static inline uint64_t CVMX_ZIP_CMD_CTL_FUNC(void)
 #define CVMX_ZIP_CONSTANTS CVMX_ZIP_CONSTANTS_FUNC()
 static inline uint64_t CVMX_ZIP_CONSTANTS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_ZIP_CONSTANTS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800380000A0ull);
 }
@@ -97,10 +97,76 @@ static inline uint64_t CVMX_ZIP_CONSTANTS_FUNC(void)
 #define CVMX_ZIP_CONSTANTS (CVMX_ADD_IO_SEG(0x00011800380000A0ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ZIP_COREX_BIST_STATUS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ZIP_COREX_BIST_STATUS(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180038000520ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_ZIP_COREX_BIST_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001180038000520ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ZIP_CTL_BIST_STATUS CVMX_ZIP_CTL_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_ZIP_CTL_BIST_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_ZIP_CTL_BIST_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180038000510ull);
+}
+#else
+#define CVMX_ZIP_CTL_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180038000510ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ZIP_CTL_CFG CVMX_ZIP_CTL_CFG_FUNC()
+static inline uint64_t CVMX_ZIP_CTL_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_ZIP_CTL_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180038000560ull);
+}
+#else
+#define CVMX_ZIP_CTL_CFG (CVMX_ADD_IO_SEG(0x0001180038000560ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ZIP_DBG_COREX_INST(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ZIP_DBG_COREX_INST(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180038000640ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_ZIP_DBG_COREX_INST(offset) (CVMX_ADD_IO_SEG(0x0001180038000640ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ZIP_DBG_COREX_STA(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ZIP_DBG_COREX_STA(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180038000680ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_ZIP_DBG_COREX_STA(offset) (CVMX_ADD_IO_SEG(0x0001180038000680ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ZIP_DBG_QUEX_STA(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ZIP_DBG_QUEX_STA(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180038000600ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_ZIP_DBG_QUEX_STA(offset) (CVMX_ADD_IO_SEG(0x0001180038000600ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_ZIP_DEBUG0 CVMX_ZIP_DEBUG0_FUNC()
 static inline uint64_t CVMX_ZIP_DEBUG0_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_ZIP_DEBUG0 not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180038000098ull);
 }
@@ -108,10 +174,21 @@ static inline uint64_t CVMX_ZIP_DEBUG0_FUNC(void)
 #define CVMX_ZIP_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180038000098ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ZIP_ECC_CTL CVMX_ZIP_ECC_CTL_FUNC()
+static inline uint64_t CVMX_ZIP_ECC_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_ZIP_ECC_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180038000568ull);
+}
+#else
+#define CVMX_ZIP_ECC_CTL (CVMX_ADD_IO_SEG(0x0001180038000568ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_ZIP_ERROR CVMX_ZIP_ERROR_FUNC()
 static inline uint64_t CVMX_ZIP_ERROR_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_ZIP_ERROR not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180038000088ull);
 }
@@ -119,10 +196,21 @@ static inline uint64_t CVMX_ZIP_ERROR_FUNC(void)
 #define CVMX_ZIP_ERROR (CVMX_ADD_IO_SEG(0x0001180038000088ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ZIP_INT_ENA CVMX_ZIP_INT_ENA_FUNC()
+static inline uint64_t CVMX_ZIP_INT_ENA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_ZIP_INT_ENA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180038000580ull);
+}
+#else
+#define CVMX_ZIP_INT_ENA (CVMX_ADD_IO_SEG(0x0001180038000580ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_ZIP_INT_MASK CVMX_ZIP_INT_MASK_FUNC()
 static inline uint64_t CVMX_ZIP_INT_MASK_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_ZIP_INT_MASK not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180038000090ull);
 }
@@ -130,10 +218,76 @@ static inline uint64_t CVMX_ZIP_INT_MASK_FUNC(void)
 #define CVMX_ZIP_INT_MASK (CVMX_ADD_IO_SEG(0x0001180038000090ull))
 #endif
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ZIP_INT_REG CVMX_ZIP_INT_REG_FUNC()
+static inline uint64_t CVMX_ZIP_INT_REG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_ZIP_INT_REG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180038000570ull);
+}
+#else
+#define CVMX_ZIP_INT_REG (CVMX_ADD_IO_SEG(0x0001180038000570ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ZIP_QUEX_BUF(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ZIP_QUEX_BUF(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180038000100ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_ZIP_QUEX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001180038000100ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ZIP_QUEX_ECC_ERR_STA(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ZIP_QUEX_ECC_ERR_STA(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180038000590ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_ZIP_QUEX_ECC_ERR_STA(offset) (CVMX_ADD_IO_SEG(0x0001180038000590ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ZIP_QUEX_MAP(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_ZIP_QUEX_MAP(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180038000300ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_ZIP_QUEX_MAP(offset) (CVMX_ADD_IO_SEG(0x0001180038000300ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ZIP_QUE_ENA CVMX_ZIP_QUE_ENA_FUNC()
+static inline uint64_t CVMX_ZIP_QUE_ENA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_ZIP_QUE_ENA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180038000500ull);
+}
+#else
+#define CVMX_ZIP_QUE_ENA (CVMX_ADD_IO_SEG(0x0001180038000500ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ZIP_QUE_PRI CVMX_ZIP_QUE_PRI_FUNC()
+static inline uint64_t CVMX_ZIP_QUE_PRI_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_ZIP_QUE_PRI not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180038000508ull);
+}
+#else
+#define CVMX_ZIP_QUE_PRI (CVMX_ADD_IO_SEG(0x0001180038000508ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_ZIP_THROTTLE CVMX_ZIP_THROTTLE_FUNC()
 static inline uint64_t CVMX_ZIP_THROTTLE_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_ZIP_THROTTLE not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x0001180038000010ull);
 }
@@ -144,28 +298,28 @@ static inline uint64_t CVMX_ZIP_THROTTLE_FUNC(void)
 /**
  * cvmx_zip_cmd_bist_result
  *
- * Notes:
- * Access to the internal BiST results
- * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
+ * ZIP_CMD_BIST_RESULT =  ZIP Command BIST Result Register
+ *
+ * Description:
+ * This register is a reformatted register with same fields as O63 2.x.
+ * The purpose of this register is for software backward compatibility.
+ * Some bits are the bist result of combined status of memories (per bit, 0=pass and 1=fail).
  */
-union cvmx_zip_cmd_bist_result
-{
+union cvmx_zip_cmd_bist_result {
 	uint64_t u64;
-	struct cvmx_zip_cmd_bist_result_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_43_63               : 21;
-	uint64_t zip_core                     : 39; /**< BiST result of the ZIP_CORE memories */
+	struct cvmx_zip_cmd_bist_result_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_57_63               : 7;
+	uint64_t zip_core                     : 53; /**< BiST result of the ZIP_CORE memories */
 	uint64_t zip_ctl                      : 4;  /**< BiST result of the ZIP_CTL  memories */
 #else
 	uint64_t zip_ctl                      : 4;
-	uint64_t zip_core                     : 39;
-	uint64_t reserved_43_63               : 21;
+	uint64_t zip_core                     : 53;
+	uint64_t reserved_57_63               : 7;
 #endif
 	} s;
-	struct cvmx_zip_cmd_bist_result_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_zip_cmd_bist_result_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t zip_core                     : 27; /**< BiST result of the ZIP_CORE memories */
 	uint64_t zip_ctl                      : 4;  /**< BiST result of the ZIP_CTL  memories */
@@ -181,29 +335,38 @@ union cvmx_zip_cmd_bist_result
 	struct cvmx_zip_cmd_bist_result_cn31xx cn56xxp1;
 	struct cvmx_zip_cmd_bist_result_cn31xx cn58xx;
 	struct cvmx_zip_cmd_bist_result_cn31xx cn58xxp1;
+	struct cvmx_zip_cmd_bist_result_s     cn61xx;
 	struct cvmx_zip_cmd_bist_result_s     cn63xx;
-	struct cvmx_zip_cmd_bist_result_s     cn63xxp1;
+	struct cvmx_zip_cmd_bist_result_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_43_63               : 21;
+	uint64_t zip_core                     : 39; /**< BiST result of the ZIP_CORE memories */
+	uint64_t zip_ctl                      : 4;  /**< BiST result of the ZIP_CTL  memories */
+#else
+	uint64_t zip_ctl                      : 4;
+	uint64_t zip_core                     : 39;
+	uint64_t reserved_43_63               : 21;
+#endif
+	} cn63xxp1;
+	struct cvmx_zip_cmd_bist_result_s     cn66xx;
+	struct cvmx_zip_cmd_bist_result_s     cn68xx;
+	struct cvmx_zip_cmd_bist_result_s     cn68xxp1;
 };
 typedef union cvmx_zip_cmd_bist_result cvmx_zip_cmd_bist_result_t;
 
 /**
  * cvmx_zip_cmd_buf
  *
- * Notes:
- * Sets the command buffer parameters
- * The size of the command buffer segments is measured in uint64s.  The pool specifies (1 of 8 free
- * lists to be used when freeing command buffer segments.  The PTR field is overwritten with the next
- * pointer each time that the command buffer segment is exhausted.
- * When quiescent (i.e. outstanding doorbell count is 0), it is safe to rewrite
- * this register to effectively reset the command buffer state machine.  New commands will then be
- * read from the newly specified command buffer pointer.
+ * ZIP_CMD_BUF =  ZIP Command Buffer Parameter Register
+ *
+ * Description:
+ * This is an alias to ZIP_QUE0_BUF. The purpose of this register is for software backward compatibility.
+ * This register set the buffer parameters for the instruction queue 0.
  */
-union cvmx_zip_cmd_buf
-{
+union cvmx_zip_cmd_buf {
 	uint64_t u64;
-	struct cvmx_zip_cmd_buf_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_zip_cmd_buf_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_58_63               : 6;
 	uint64_t dwb                          : 9;  /**< Number of DontWriteBacks */
 	uint64_t pool                         : 3;  /**< Free list used to free command buffer segments */
@@ -224,23 +387,30 @@ union cvmx_zip_cmd_buf
 	struct cvmx_zip_cmd_buf_s             cn56xxp1;
 	struct cvmx_zip_cmd_buf_s             cn58xx;
 	struct cvmx_zip_cmd_buf_s             cn58xxp1;
+	struct cvmx_zip_cmd_buf_s             cn61xx;
 	struct cvmx_zip_cmd_buf_s             cn63xx;
 	struct cvmx_zip_cmd_buf_s             cn63xxp1;
+	struct cvmx_zip_cmd_buf_s             cn66xx;
+	struct cvmx_zip_cmd_buf_s             cn68xx;
+	struct cvmx_zip_cmd_buf_s             cn68xxp1;
 };
 typedef union cvmx_zip_cmd_buf cvmx_zip_cmd_buf_t;
 
 /**
  * cvmx_zip_cmd_ctl
+ *
+ * ZIP_CMD_CTL = ZIP Clock/Reset Control Register
+ *
+ * Description:
+ *       This register controls clock and reset.
  */
-union cvmx_zip_cmd_ctl
-{
+union cvmx_zip_cmd_ctl {
 	uint64_t u64;
-	struct cvmx_zip_cmd_ctl_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_zip_cmd_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
-	uint64_t forceclk                     : 1;  /**< Force zip_ctl__clock_on_b == 1 when set */
-	uint64_t reset                        : 1;  /**< Reset oneshot pulse for zip core */
+	uint64_t forceclk                     : 1;  /**< Force zip_ctl__zip<0|1>_clock_on_b == 1 when set */
+	uint64_t reset                        : 1;  /**< Reset one-shot pulse for zip cores */
 #else
 	uint64_t reset                        : 1;
 	uint64_t forceclk                     : 1;
@@ -254,24 +424,51 @@ union cvmx_zip_cmd_ctl
 	struct cvmx_zip_cmd_ctl_s             cn56xxp1;
 	struct cvmx_zip_cmd_ctl_s             cn58xx;
 	struct cvmx_zip_cmd_ctl_s             cn58xxp1;
+	struct cvmx_zip_cmd_ctl_s             cn61xx;
 	struct cvmx_zip_cmd_ctl_s             cn63xx;
 	struct cvmx_zip_cmd_ctl_s             cn63xxp1;
+	struct cvmx_zip_cmd_ctl_s             cn66xx;
+	struct cvmx_zip_cmd_ctl_s             cn68xx;
+	struct cvmx_zip_cmd_ctl_s             cn68xxp1;
 };
 typedef union cvmx_zip_cmd_ctl cvmx_zip_cmd_ctl_t;
 
 /**
  * cvmx_zip_constants
  *
- * Notes:
- * Note that this CSR is present only in chip revisions beginning with pass2.
+ * ZIP_CONSTANTS =  ZIP Constants Register
  *
+ * Description:
+ *   This contains all the current implementation related parameters of the zip core in this chip.
  */
-union cvmx_zip_constants
-{
+union cvmx_zip_constants {
 	uint64_t u64;
-	struct cvmx_zip_constants_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_zip_constants_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t nexec                        : 8;  /**< Number of available ZIP Exec Units */
+	uint64_t reserved_49_55               : 7;
+	uint64_t syncflush_capable            : 1;  /**< 1: SYNCFLUSH is supported
+                                                         - 0: SYNCFLUSH is not supported.
+                                                          Note: for O68 1.0, SYNCFLUSH is supported
+                                                                although this field is 0. */
+	uint64_t depth                        : 16; /**< Maximum search depth for compression */
+	uint64_t onfsize                      : 12; /**< Output near full threshold in bytes */
+	uint64_t ctxsize                      : 12; /**< Decompression Context size in bytes */
+	uint64_t reserved_1_7                 : 7;
+	uint64_t disabled                     : 1;  /**< 1=zip is disabled, 0=zip is enabled */
+#else
+	uint64_t disabled                     : 1;
+	uint64_t reserved_1_7                 : 7;
+	uint64_t ctxsize                      : 12;
+	uint64_t onfsize                      : 12;
+	uint64_t depth                        : 16;
+	uint64_t syncflush_capable            : 1;
+	uint64_t reserved_49_55               : 7;
+	uint64_t nexec                        : 8;
+#endif
+	} s;
+	struct cvmx_zip_constants_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_48_63               : 16;
 	uint64_t depth                        : 16; /**< Maximum search depth for compression */
 	uint64_t onfsize                      : 12; /**< Output near full threshhold in bytes */
@@ -286,42 +483,234 @@ union cvmx_zip_constants
 	uint64_t depth                        : 16;
 	uint64_t reserved_48_63               : 16;
 #endif
-	} s;
-	struct cvmx_zip_constants_s           cn31xx;
-	struct cvmx_zip_constants_s           cn38xx;
-	struct cvmx_zip_constants_s           cn38xxp2;
-	struct cvmx_zip_constants_s           cn56xx;
-	struct cvmx_zip_constants_s           cn56xxp1;
-	struct cvmx_zip_constants_s           cn58xx;
-	struct cvmx_zip_constants_s           cn58xxp1;
-	struct cvmx_zip_constants_s           cn63xx;
-	struct cvmx_zip_constants_s           cn63xxp1;
+	} cn31xx;
+	struct cvmx_zip_constants_cn31xx      cn38xx;
+	struct cvmx_zip_constants_cn31xx      cn38xxp2;
+	struct cvmx_zip_constants_cn31xx      cn56xx;
+	struct cvmx_zip_constants_cn31xx      cn56xxp1;
+	struct cvmx_zip_constants_cn31xx      cn58xx;
+	struct cvmx_zip_constants_cn31xx      cn58xxp1;
+	struct cvmx_zip_constants_s           cn61xx;
+	struct cvmx_zip_constants_cn31xx      cn63xx;
+	struct cvmx_zip_constants_cn31xx      cn63xxp1;
+	struct cvmx_zip_constants_s           cn66xx;
+	struct cvmx_zip_constants_s           cn68xx;
+	struct cvmx_zip_constants_cn31xx      cn68xxp1;
 };
 typedef union cvmx_zip_constants cvmx_zip_constants_t;
 
 /**
+ * cvmx_zip_core#_bist_status
+ *
+ * ZIP_CORE_BIST_STATUS =  ZIP CORE Bist Status Registers
+ *
+ * Description:
+ *   Those register have the bist status of memories in zip cores.
+ *   Each bit is the bist result of an individual memory (per bit, 0=pass and 1=fail).
+ */
+union cvmx_zip_corex_bist_status {
+	uint64_t u64;
+	struct cvmx_zip_corex_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_53_63               : 11;
+	uint64_t bstatus                      : 53; /**< BIST result of the ZIP_CORE memories */
+#else
+	uint64_t bstatus                      : 53;
+	uint64_t reserved_53_63               : 11;
+#endif
+	} s;
+	struct cvmx_zip_corex_bist_status_s   cn68xx;
+	struct cvmx_zip_corex_bist_status_s   cn68xxp1;
+};
+typedef union cvmx_zip_corex_bist_status cvmx_zip_corex_bist_status_t;
+
+/**
+ * cvmx_zip_ctl_bist_status
+ *
+ * ZIP_CTL_BIST_STATUS =  ZIP CONTROL Bist Status Register
+ *
+ * Description:
+ *   This register has the bist status of memories in zip_ctl (Instruction Buffer, G/S Pointer Fifo, Input Data Buffer,
+ *   Output Data Buffers).
+ *   Each bit is the bist result of an individual memory (per bit, 0=pass and 1=fail).
+ */
+union cvmx_zip_ctl_bist_status {
+	uint64_t u64;
+	struct cvmx_zip_ctl_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_7_63                : 57;
+	uint64_t bstatus                      : 7;  /**< BIST result of the memories */
+#else
+	uint64_t bstatus                      : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_zip_ctl_bist_status_s     cn68xx;
+	struct cvmx_zip_ctl_bist_status_s     cn68xxp1;
+};
+typedef union cvmx_zip_ctl_bist_status cvmx_zip_ctl_bist_status_t;
+
+/**
+ * cvmx_zip_ctl_cfg
+ *
+ * ZIP_CTL_CFG =  ZIP Controller Configuration Register
+ *
+ * Description:
+ * This register controls the behavior zip dma engine. It is recommended to kept those field in the default values for normal
+ * operation. Changing the values of the fields may be useful for diagnostics.
+ */
+union cvmx_zip_ctl_cfg {
+	uint64_t u64;
+	struct cvmx_zip_ctl_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_27_63               : 37;
+	uint64_t ildf                         : 3;  /**< Instruction Load Command FIFO Credits <= 4 */
+	uint64_t reserved_22_23               : 2;
+	uint64_t iprf                         : 2;  /**< Instruction Page Return Cmd FIFO Credits <= 2 */
+	uint64_t reserved_19_19               : 1;
+	uint64_t gstf                         : 3;  /**< G/S Tag FIFO Credits <= 4 */
+	uint64_t reserved_15_15               : 1;
+	uint64_t stcf                         : 3;  /**< Store Command FIFO Credits <= 4 */
+	uint64_t reserved_11_11               : 1;
+	uint64_t ldf                          : 3;  /**< Load Cmd FIFO Credits <= 4 */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t wkqf                         : 2;  /**< WorkQueue FIFO Credits <= 2 */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t busy                         : 1;  /**< 1: ZIP system is busy; 0: ZIP system is idle. */
+	uint64_t lmod                         : 1;  /**< Legacy Mode. */
+#else
+	uint64_t lmod                         : 1;
+	uint64_t busy                         : 1;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t wkqf                         : 2;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ldf                          : 3;
+	uint64_t reserved_11_11               : 1;
+	uint64_t stcf                         : 3;
+	uint64_t reserved_15_15               : 1;
+	uint64_t gstf                         : 3;
+	uint64_t reserved_19_19               : 1;
+	uint64_t iprf                         : 2;
+	uint64_t reserved_22_23               : 2;
+	uint64_t ildf                         : 3;
+	uint64_t reserved_27_63               : 37;
+#endif
+	} s;
+	struct cvmx_zip_ctl_cfg_s             cn68xx;
+	struct cvmx_zip_ctl_cfg_s             cn68xxp1;
+};
+typedef union cvmx_zip_ctl_cfg cvmx_zip_ctl_cfg_t;
+
+/**
+ * cvmx_zip_dbg_core#_inst
+ *
+ * ZIP_DBG_COREX_INST =  ZIP Core Current Instruction Registers
+ *
+ * Description:
+ * This register reflects the status of the current instruction that zip core is executing/ has executed.
+ * This register is only for debug use.
+ */
+union cvmx_zip_dbg_corex_inst {
+	uint64_t u64;
+	struct cvmx_zip_dbg_corex_inst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t busy                         : 1;  /**< Core State: 1 - Core is busy; 0 - Core is idle */
+	uint64_t reserved_33_62               : 30;
+	uint64_t qid                          : 1;  /**< Queue Index of instruction executed (BUSY=0) or
+                                                         being executed (BUSY=1) on this core */
+	uint64_t iid                          : 32; /**< Instruction Index executed (BUSY=0) or being
+                                                         executed (BUSY=1) on this core */
+#else
+	uint64_t iid                          : 32;
+	uint64_t qid                          : 1;
+	uint64_t reserved_33_62               : 30;
+	uint64_t busy                         : 1;
+#endif
+	} s;
+	struct cvmx_zip_dbg_corex_inst_s      cn68xx;
+	struct cvmx_zip_dbg_corex_inst_s      cn68xxp1;
+};
+typedef union cvmx_zip_dbg_corex_inst cvmx_zip_dbg_corex_inst_t;
+
+/**
+ * cvmx_zip_dbg_core#_sta
+ *
+ * ZIP_DBG_COREX_STA =  ZIP Core Status Registers
+ *
+ * Description:
+ * These register reflect the status of the zip cores.
+ * This register is only for debug use.
+ */
+union cvmx_zip_dbg_corex_sta {
+	uint64_t u64;
+	struct cvmx_zip_dbg_corex_sta_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t busy                         : 1;  /**< Core State: 1 - Core is busy; 0 - Core is idle */
+	uint64_t reserved_37_62               : 26;
+	uint64_t ist                          : 5;  /**< State of current instruction is executing */
+	uint64_t nie                          : 32; /**< Number of instructions executed on this core */
+#else
+	uint64_t nie                          : 32;
+	uint64_t ist                          : 5;
+	uint64_t reserved_37_62               : 26;
+	uint64_t busy                         : 1;
+#endif
+	} s;
+	struct cvmx_zip_dbg_corex_sta_s       cn68xx;
+	struct cvmx_zip_dbg_corex_sta_s       cn68xxp1;
+};
+typedef union cvmx_zip_dbg_corex_sta cvmx_zip_dbg_corex_sta_t;
+
+/**
+ * cvmx_zip_dbg_que#_sta
+ *
+ * ZIP_DBG_QUEX_STA =  ZIP Queue Status Registers
+ *
+ * Description:
+ * This register reflects status of the zip instruction queue.
+ * This register is only for debug use.
+ */
+union cvmx_zip_dbg_quex_sta {
+	uint64_t u64;
+	struct cvmx_zip_dbg_quex_sta_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t busy                         : 1;  /**< Queue State: 1 - Queue is busy; 0 - Queue is idle */
+	uint64_t reserved_52_62               : 11;
+	uint64_t cdbc                         : 20; /**< Current DoorBell Counter */
+	uint64_t nii                          : 32; /**< Number of instructions issued from this queue.
+                                                         Reset to 0 when ZIP_QUEn_BUF is written. */
+#else
+	uint64_t nii                          : 32;
+	uint64_t cdbc                         : 20;
+	uint64_t reserved_52_62               : 11;
+	uint64_t busy                         : 1;
+#endif
+	} s;
+	struct cvmx_zip_dbg_quex_sta_s        cn68xx;
+	struct cvmx_zip_dbg_quex_sta_s        cn68xxp1;
+};
+typedef union cvmx_zip_dbg_quex_sta cvmx_zip_dbg_quex_sta_t;
+
+/**
  * cvmx_zip_debug0
  *
- * Notes:
- * Note that this CSR is present only in chip revisions beginning with pass2.
+ * ZIP_DEBUG0 =  ZIP DEBUG Register
  *
+ * Description:
  */
-union cvmx_zip_debug0
-{
+union cvmx_zip_debug0 {
 	uint64_t u64;
-	struct cvmx_zip_debug0_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
-	uint64_t reserved_17_63               : 47;
-	uint64_t asserts                      : 17; /**< FIFO assertion checks */
+	struct cvmx_zip_debug0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_30_63               : 34;
+	uint64_t asserts                      : 30; /**< FIFO assertion checks */
 #else
-	uint64_t asserts                      : 17;
-	uint64_t reserved_17_63               : 47;
+	uint64_t asserts                      : 30;
+	uint64_t reserved_30_63               : 34;
 #endif
 	} s;
-	struct cvmx_zip_debug0_cn31xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_zip_debug0_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_14_63               : 50;
 	uint64_t asserts                      : 14; /**< FIFO assertion checks */
 #else
@@ -335,24 +724,69 @@ union cvmx_zip_debug0
 	struct cvmx_zip_debug0_cn31xx         cn56xxp1;
 	struct cvmx_zip_debug0_cn31xx         cn58xx;
 	struct cvmx_zip_debug0_cn31xx         cn58xxp1;
-	struct cvmx_zip_debug0_s              cn63xx;
-	struct cvmx_zip_debug0_s              cn63xxp1;
+	struct cvmx_zip_debug0_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_17_63               : 47;
+	uint64_t asserts                      : 17; /**< FIFO assertion checks */
+#else
+	uint64_t asserts                      : 17;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn61xx;
+	struct cvmx_zip_debug0_cn61xx         cn63xx;
+	struct cvmx_zip_debug0_cn61xx         cn63xxp1;
+	struct cvmx_zip_debug0_cn61xx         cn66xx;
+	struct cvmx_zip_debug0_s              cn68xx;
+	struct cvmx_zip_debug0_s              cn68xxp1;
 };
 typedef union cvmx_zip_debug0 cvmx_zip_debug0_t;
 
 /**
+ * cvmx_zip_ecc_ctl
+ *
+ * ZIP_ECC_CTL =  ZIP ECC Control Register
+ *
+ * Description:
+ *   This register enables ECC for each individual internal memory that requires ECC. For debug purpose, it can also
+ *   control 1 or 2 bits be flipped in the ECC data.
+ */
+union cvmx_zip_ecc_ctl {
+	uint64_t u64;
+	struct cvmx_zip_ecc_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_34_63               : 30;
+	uint64_t ibge                         : 2;  /**< controls instruction buffer flip syndrome
+                                                         2'b00       : No Error Generation
+                                                         2'b10, 2'b01: Flip 1 bit
+                                                         2'b11       : Flip 2 bits */
+	uint64_t reserved_1_31                : 31;
+	uint64_t iben                         : 1;  /**< 1: ECC Enabled for instruction buffer
+                                                         - 0: ECC Disabled for instruction buffer */
+#else
+	uint64_t iben                         : 1;
+	uint64_t reserved_1_31                : 31;
+	uint64_t ibge                         : 2;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_zip_ecc_ctl_s             cn68xx;
+	struct cvmx_zip_ecc_ctl_s             cn68xxp1;
+};
+typedef union cvmx_zip_ecc_ctl cvmx_zip_ecc_ctl_t;
+
+/**
  * cvmx_zip_error
  *
- * Notes:
- * Note that this CSR is present only in chip revisions beginning with pass2.
+ * ZIP_ERROR =  ZIP ERROR Register
  *
+ * Description:
+ * This register is an alias to ZIP_INT_REG[DOORBELL0].
+ * The purpose of this register is for software backward compatibility.
  */
-union cvmx_zip_error
-{
+union cvmx_zip_error {
 	uint64_t u64;
-	struct cvmx_zip_error_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_zip_error_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t doorbell                     : 1;  /**< A doorbell count has overflowed */
 #else
@@ -367,24 +801,63 @@ union cvmx_zip_error
 	struct cvmx_zip_error_s               cn56xxp1;
 	struct cvmx_zip_error_s               cn58xx;
 	struct cvmx_zip_error_s               cn58xxp1;
+	struct cvmx_zip_error_s               cn61xx;
 	struct cvmx_zip_error_s               cn63xx;
 	struct cvmx_zip_error_s               cn63xxp1;
+	struct cvmx_zip_error_s               cn66xx;
+	struct cvmx_zip_error_s               cn68xx;
+	struct cvmx_zip_error_s               cn68xxp1;
 };
 typedef union cvmx_zip_error cvmx_zip_error_t;
 
 /**
+ * cvmx_zip_int_ena
+ *
+ * ZIP_INT_ENA =  ZIP Interrupt Enable Register
+ *
+ * Description:
+ *   Only when an interrupt source is enabled, an interrupt can be fired.
+ *   When a bit is set to 1, the corresponding interrupt is enabled.
+ */
+union cvmx_zip_int_ena {
+	uint64_t u64;
+	struct cvmx_zip_int_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t doorbell1                    : 1;  /**< Enable for Doorbell 1 count overflow */
+	uint64_t doorbell0                    : 1;  /**< Enable for Doorbell 0 count overflow */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ibdbe                        : 1;  /**< Enable for IBUF Double Bit Error */
+	uint64_t ibsbe                        : 1;  /**< Enable for IBUF Single Bit Error */
+	uint64_t fife                         : 1;  /**< Enable for FIFO errors */
+#else
+	uint64_t fife                         : 1;
+	uint64_t ibsbe                        : 1;
+	uint64_t ibdbe                        : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t doorbell0                    : 1;
+	uint64_t doorbell1                    : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_zip_int_ena_s             cn68xx;
+	struct cvmx_zip_int_ena_s             cn68xxp1;
+};
+typedef union cvmx_zip_int_ena cvmx_zip_int_ena_t;
+
+/**
  * cvmx_zip_int_mask
  *
- * Notes:
- * Note that this CSR is present only in chip revisions beginning with pass2.
- * When a mask bit is set, the corresponding interrupt is enabled.
+ * ZIP_INT_MASK =  ZIP Interrupt Mask Register
+ *
+ * Description:
+ * This register is an alias to ZIP_INT_ENA[DOORBELL0].
+ * The purpose of this register is for software backward compatibility.
  */
-union cvmx_zip_int_mask
-{
+union cvmx_zip_int_mask {
 	uint64_t u64;
-	struct cvmx_zip_int_mask_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_zip_int_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t doorbell                     : 1;  /**< Bit mask corresponding to ZIP_ERROR[0] above */
 #else
@@ -399,35 +872,241 @@ union cvmx_zip_int_mask
 	struct cvmx_zip_int_mask_s            cn56xxp1;
 	struct cvmx_zip_int_mask_s            cn58xx;
 	struct cvmx_zip_int_mask_s            cn58xxp1;
+	struct cvmx_zip_int_mask_s            cn61xx;
 	struct cvmx_zip_int_mask_s            cn63xx;
 	struct cvmx_zip_int_mask_s            cn63xxp1;
+	struct cvmx_zip_int_mask_s            cn66xx;
+	struct cvmx_zip_int_mask_s            cn68xx;
+	struct cvmx_zip_int_mask_s            cn68xxp1;
 };
 typedef union cvmx_zip_int_mask cvmx_zip_int_mask_t;
 
 /**
+ * cvmx_zip_int_reg
+ *
+ * ZIP_INT_REG =  ZIP Interrupt Status Register
+ *
+ * Description:
+ *   This registers contains the status of all the interrupt source. An interrupt will be generated only when
+ *   the corresponding interrupt source is enabled in ZIP_INT_ENA.
+ */
+union cvmx_zip_int_reg {
+	uint64_t u64;
+	struct cvmx_zip_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t doorbell1                    : 1;  /**< Doorbell 1 count has overflowed */
+	uint64_t doorbell0                    : 1;  /**< Doorbell 0 count has overflowed */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t ibdbe                        : 1;  /**< IBUF Double Bit Error */
+	uint64_t ibsbe                        : 1;  /**< IBUF Single Bit Error */
+	uint64_t fife                         : 1;  /**< FIFO errors and the detailed status is in
+                                                         ZIP_DEBUG0 */
+#else
+	uint64_t fife                         : 1;
+	uint64_t ibsbe                        : 1;
+	uint64_t ibdbe                        : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t doorbell0                    : 1;
+	uint64_t doorbell1                    : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_zip_int_reg_s             cn68xx;
+	struct cvmx_zip_int_reg_s             cn68xxp1;
+};
+typedef union cvmx_zip_int_reg cvmx_zip_int_reg_t;
+
+/**
+ * cvmx_zip_que#_buf
+ *
+ * NOTE: Fields NEXEC and SYNCFLUSH_CAPABLE are only valid for chips after O68 2.0 (including O68 2.0).
+ *
+ *
+ *                  ZIP_QUEX_BUF =  ZIP Queue Buffer Parameter Registers
+ *
+ * Description:
+ * These registers set the buffer parameters for the instruction queues . The size of the instruction buffer
+ * segments is measured in uint64s.  The pool specifies (1 of 8 free lists to be used when freeing command
+ * buffer segments).  The PTR field is overwritten with the next pointer each time that the command
+ * buffer segment is exhausted. When quiescent (i.e. outstanding doorbell count is 0), it is safe
+ * to rewrite this register to effectively reset the command buffer state machine.  New commands
+ * will then be read from the newly specified command buffer pointer.
+ */
+union cvmx_zip_quex_buf {
+	uint64_t u64;
+	struct cvmx_zip_quex_buf_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_58_63               : 6;
+	uint64_t dwb                          : 9;  /**< Number of DontWriteBacks */
+	uint64_t pool                         : 3;  /**< Free list used to free command buffer segments */
+	uint64_t size                         : 13; /**< Number of uint64s per command buffer segment */
+	uint64_t ptr                          : 33; /**< Initial command buffer pointer[39:7] (128B-aligned) */
+#else
+	uint64_t ptr                          : 33;
+	uint64_t size                         : 13;
+	uint64_t pool                         : 3;
+	uint64_t dwb                          : 9;
+	uint64_t reserved_58_63               : 6;
+#endif
+	} s;
+	struct cvmx_zip_quex_buf_s            cn68xx;
+	struct cvmx_zip_quex_buf_s            cn68xxp1;
+};
+typedef union cvmx_zip_quex_buf cvmx_zip_quex_buf_t;
+
+/**
+ * cvmx_zip_que#_ecc_err_sta
+ *
+ * ZIP_QUEX_ECC_ERR_STA =  ZIP Queue ECC ERROR STATUS Register
+ *
+ * Description:
+ *   This register contains the first ECC SBE/DBE status for the instruction buffer of a given zip instruction queue.
+ */
+union cvmx_zip_quex_ecc_err_sta {
+	uint64_t u64;
+	struct cvmx_zip_quex_ecc_err_sta_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_35_63               : 29;
+	uint64_t wnum                         : 3;  /**< Index of the first IWORD that DBE happened
+                                                         (Valid when ZIP_INT_REG[IBDBE] or [IBSBE] is set). */
+	uint64_t inum                         : 32; /**< Index of the first instruction that DBE happened
+                                                         (Valid when ZIP_INT_REG[IBDBE] or [IBSBE] is set). */
+#else
+	uint64_t inum                         : 32;
+	uint64_t wnum                         : 3;
+	uint64_t reserved_35_63               : 29;
+#endif
+	} s;
+	struct cvmx_zip_quex_ecc_err_sta_s    cn68xx;
+	struct cvmx_zip_quex_ecc_err_sta_s    cn68xxp1;
+};
+typedef union cvmx_zip_quex_ecc_err_sta cvmx_zip_quex_ecc_err_sta_t;
+
+/**
+ * cvmx_zip_que#_map
+ *
+ * ZIP_QUEX_MAP =  ZIP Queue Mapping Registers
+ *
+ * Description:
+ *  These registers control how each instruction queue maps to 2 zip cores.
+ *  Bit[0] corresponds to zip core 0 and bit[1] corresponds to zip core 1.
+ *  A "1" means instructions from the queue can be served by the corresponding zip core.
+ */
+union cvmx_zip_quex_map {
+	uint64_t u64;
+	struct cvmx_zip_quex_map_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_2_63                : 62;
+	uint64_t zce                          : 2;  /**< Zip Core Enable
+                                                         Controls the logical instruction queue can be
+                                                         serviced by which zip core. Setting ZCE==0
+                                                         effectively disables the queue from being served
+                                                         (however the instruction can still be fetched).
+                                                         ZCE[1]=1, zip core 1 can serve the queue.
+                                                         ZCE[0]=1, zip core 0 can serve the queue. */
+#else
+	uint64_t zce                          : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_zip_quex_map_s            cn68xx;
+	struct cvmx_zip_quex_map_s            cn68xxp1;
+};
+typedef union cvmx_zip_quex_map cvmx_zip_quex_map_t;
+
+/**
+ * cvmx_zip_que_ena
+ *
+ * ZIP_QUE_ENA =  ZIP Queue Enable Register
+ *
+ * Description:
+ *    If a queue is disabled, ZIP_CTL will stop fetching instructions from the queue.
+ */
+union cvmx_zip_que_ena {
+	uint64_t u64;
+	struct cvmx_zip_que_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_2_63                : 62;
+	uint64_t ena                          : 2;  /**< Enables the logical instruction queues.
+                                                         - 1: Queue is enabled. 0: Queue is disabled
+                                                          ENA[1]=1 enables queue 1
+                                                          ENA[0]=1 enables queue 0 */
+#else
+	uint64_t ena                          : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_zip_que_ena_s             cn68xx;
+	struct cvmx_zip_que_ena_s             cn68xxp1;
+};
+typedef union cvmx_zip_que_ena cvmx_zip_que_ena_t;
+
+/**
+ * cvmx_zip_que_pri
+ *
+ * ZIP_QUE_PRI =  ZIP Queue Priority Register
+ *
+ * Description:
+ *   This registers defines the priority between instruction queue 1 and instruction queue 0.
+ *   Bit[0] corresponds to queue 0 and bit[1] corresponds to queue 1. A "1" means high priority.
+ */
+union cvmx_zip_que_pri {
+	uint64_t u64;
+	struct cvmx_zip_que_pri_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_2_63                : 62;
+	uint64_t pri                          : 2;  /**< Priority
+                                                         2'b10: Queue 1 has higher priority.
+                                                         2'b01: Queue 0 has higher priority.
+                                                         2'b11,2'b00: round robin */
+#else
+	uint64_t pri                          : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_zip_que_pri_s             cn68xx;
+	struct cvmx_zip_que_pri_s             cn68xxp1;
+};
+typedef union cvmx_zip_que_pri cvmx_zip_que_pri_t;
+
+/**
  * cvmx_zip_throttle
  *
- * Notes:
- * The maximum number of inflight data fetch transactions.  Values > 8 are illegal.
- * Writing 0 to this register causes the ZIP module to temporarily suspend NCB
- * accesses; it is not recommended for normal operation, but may be useful for
- * diagnostics.
+ * ZIP_THROTTLE =  ZIP Throttle Register
+ *
+ * Description:
+ * This register controls the maximum number of in-flight X2I data fetch transactions.  Values > 16 are illegal.
+ * Writing 0 to this register causes the ZIP module to temporarily suspend NCB accesses; it is not recommended
+ * for normal operation, but may be useful for diagnostics.
  */
-union cvmx_zip_throttle
-{
+union cvmx_zip_throttle {
 	uint64_t u64;
-	struct cvmx_zip_throttle_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_zip_throttle_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_5_63                : 59;
+	uint64_t max_infl                     : 5;  /**< Maximum number of in-flight data fetch transactions on
+                                                         NCB. */
+#else
+	uint64_t max_infl                     : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_zip_throttle_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
-	uint64_t max_infl                     : 4;  /**< Maximum number of inflight data fetch transactions on NCB */
+	uint64_t max_infl                     : 4;  /**< Maximum number of inflight data fetch transactions
+                                                         on NCB. */
 #else
 	uint64_t max_infl                     : 4;
 	uint64_t reserved_4_63                : 60;
 #endif
-	} s;
-	struct cvmx_zip_throttle_s            cn63xx;
-	struct cvmx_zip_throttle_s            cn63xxp1;
+	} cn61xx;
+	struct cvmx_zip_throttle_cn61xx       cn63xx;
+	struct cvmx_zip_throttle_cn61xx       cn63xxp1;
+	struct cvmx_zip_throttle_cn61xx       cn66xx;
+	struct cvmx_zip_throttle_s            cn68xx;
+	struct cvmx_zip_throttle_s            cn68xxp1;
 };
 typedef union cvmx_zip_throttle cvmx_zip_throttle_t;
 
diff --git a/sys/contrib/octeon-sdk/cvmx-zip.c b/sys/contrib/octeon-sdk/cvmx-zip.c
index 1cf5980..e6125bc 100644
--- a/sys/contrib/octeon-sdk/cvmx-zip.c
+++ b/sys/contrib/octeon-sdk/cvmx-zip.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Source file for the zip (deflate) block
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #include "executive-config.h"
@@ -86,6 +86,68 @@ int cvmx_zip_initialize(void)
 }
 
 /**
+ * Initialize the ZIP QUEUE buffer
+ *
+ * @param queue : ZIP instruction queue
+ * @param zcoremask : ZIP coremask to use for this queue
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_zip_queue_initialize(int queue, int zcoremask)
+{
+    cvmx_zip_quex_buf_t zip_que_buf;
+    cvmx_cmd_queue_result_t result;
+    cvmx_zip_quex_map_t que_map;
+    cvmx_zip_que_ena_t que_ena;
+    cvmx_zip_int_reg_t int_reg;
+
+    /* Previous Octeon models has only one instruction queue, call 
+       cvmx_zip_inititalize() to initialize the ZIP block */
+
+    if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
+        return -1;
+
+    result = cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_ZIP_QUE(queue), 0,
+                                       CVMX_FPA_OUTPUT_BUFFER_POOL,
+                                       CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE);
+    if (result != CVMX_CMD_QUEUE_SUCCESS)
+        return -1;
+
+    /* 1. Program ZIP_QUE0/1_BUF to have the correct buffer pointer and
+          size configured for each instruction queue */
+    zip_que_buf.u64 = 0;
+    zip_que_buf.s.dwb = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/128;
+    zip_que_buf.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
+    zip_que_buf.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/8;
+    zip_que_buf.s.ptr =  cvmx_ptr_to_phys(cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_ZIP_QUE(queue)))>>7;
+    cvmx_write_csr(CVMX_ZIP_QUEX_BUF(queue), zip_que_buf.u64);
+
+    /* 2. Change the queue-to-ZIP core mapping by programming ZIP_QUE0/1_MAP. */ 
+    que_map.u64 = cvmx_read_csr(CVMX_ZIP_QUEX_MAP(queue));
+    que_map.s.zce = zcoremask;
+    cvmx_write_csr(CVMX_ZIP_QUEX_MAP(queue), que_map.u64); 
+
+    /* Enable the queue */
+    que_ena.u64 = cvmx_read_csr(CVMX_ZIP_QUE_ENA);
+    que_ena.s.ena |= (1<<queue);
+    cvmx_write_csr(CVMX_ZIP_QUE_ENA, que_ena.u64);
+
+    /* Use round robin to have equal priority for each instruction queue */ 
+    cvmx_write_csr(CVMX_ZIP_QUE_PRI, 0x3);
+
+    int_reg.u64 = cvmx_read_csr(CVMX_ZIP_INT_REG);
+    if (queue)
+        int_reg.s.doorbell1 = 1;
+    else
+        int_reg.s.doorbell0 = 1;
+
+    cvmx_write_csr(CVMX_ZIP_INT_REG, int_reg.u64);
+    /* Read back to make sure the setup is complete */
+    cvmx_read_csr(CVMX_ZIP_QUEX_BUF(queue));
+    return 0;
+}
+
+/**
  * Shutdown the ZIP block. ZIP must be idle when
  * this function is called.
  *
@@ -111,6 +173,33 @@ int cvmx_zip_shutdown(void)
 }
 
 /**
+ * Shutdown the ZIP block for a queue. ZIP must be idle when
+ * this function is called.
+ *
+ * @param queue   Zip instruction queue of the command
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_zip_queue_shutdown(int queue)
+{
+    cvmx_zip_cmd_ctl_t zip_cmd_ctl;
+
+    if (cvmx_cmd_queue_length(CVMX_CMD_QUEUE_ZIP_QUE(queue)))
+    {
+        cvmx_dprintf("ERROR: cvmx_zip_shutdown: ZIP not idle.\n");
+        return -1;
+    }
+
+    zip_cmd_ctl.u64 = cvmx_read_csr(CVMX_ZIP_CMD_CTL);
+    zip_cmd_ctl.s.reset = 1;
+    cvmx_write_csr(CVMX_ZIP_CMD_CTL, zip_cmd_ctl.u64);
+    cvmx_wait(100);
+
+    cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_ZIP_QUE(queue));
+    return 0;
+}
+
+/**
  * Submit a command to the ZIP block
  *
  * @param command Zip command to submit
@@ -125,5 +214,21 @@ int cvmx_zip_submit(cvmx_zip_command_t *command)
     return result;
 }
 
+/**
+ * Submit a command to the ZIP block
+ *
+ * @param command Zip command to submit
+ * @param queue   Zip instruction queue of the command
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_zip_queue_submit(cvmx_zip_command_t *command, int queue)
+{
+    cvmx_cmd_queue_result_t result = cvmx_cmd_queue_write(CVMX_CMD_QUEUE_ZIP_QUE(queue), 1, 8, command->u64);
+    if (result == CVMX_CMD_QUEUE_SUCCESS)
+        cvmx_write_csr((CVMX_ADDR_DID(CVMX_FULL_DID(7, 0)) | queue << 3), 8);
+    return result;
+}
+
 #endif
 
diff --git a/sys/contrib/octeon-sdk/cvmx-zip.h b/sys/contrib/octeon-sdk/cvmx-zip.h
index f5f5859..adc5d04 100644
--- a/sys/contrib/octeon-sdk/cvmx-zip.h
+++ b/sys/contrib/octeon-sdk/cvmx-zip.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Header file for the zip (deflate) block
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_ZIP_H__
@@ -61,7 +61,7 @@ extern "C" {
 typedef union {
    uint64_t u64;
    struct {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
       uint64_t unused              :  5;
       uint64_t full_block_write    :  1;
       uint64_t no_l2_alloc         :  1;
@@ -101,7 +101,7 @@ typedef union {
    struct {
 
       // WORD 0
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
       uint64_t crc32               : 32;
       uint64_t adler               : 32;
 #else
@@ -110,7 +110,7 @@ typedef union {
 #endif
 
       // WORD 1
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
       uint64_t totalbyteswritten   : 32;
       uint64_t totalbytesread      : 32;
 #else
@@ -119,7 +119,7 @@ typedef union {
 #endif
 
       // WORD 2
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
       uint64_t                      totalbitsprocessed  : 32; // decompression only
       uint64_t                      unused20            :  5;
       uint64_t                      exnum               :  3; // compression only
@@ -146,15 +146,16 @@ typedef union {
    struct {
 
       // WORD 0
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
       uint64_t unused00            :  8;
       uint64_t totaloutputlength   : 24;
       uint64_t unused01            :  5;
       uint64_t exnum               :  3;
       uint64_t unused02            :  1;
       uint64_t exbits              :  7;
-      uint64_t unused03            :  6;
-      uint64_t speed               :  1;
+      uint64_t unused03            :  4;
+      uint64_t flush               :  1;
+      uint64_t speed               :  2;
       uint64_t forcefixed          :  1;
       uint64_t forcedynamic        :  1;
       uint64_t eof                 :  1;
@@ -174,8 +175,9 @@ typedef union {
       uint64_t eof                 :  1;
       uint64_t forcedynamic        :  1;
       uint64_t forcefixed          :  1;
-      uint64_t speed               :  1;
-      uint64_t unused03            :  6;
+      uint64_t speed               :  2;
+      uint64_t flush               :  1;
+      uint64_t unused03            :  4;
       uint64_t exbits              :  7;
       uint64_t unused02            :  1;
       uint64_t exnum               :  3;
@@ -185,7 +187,7 @@ typedef union {
 #endif
 
       // WORD 1
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
       uint64_t historylength       : 16;
       uint64_t unused10            : 16;
       uint64_t adler32             : 32;
@@ -225,6 +227,16 @@ typedef union {
 int cvmx_zip_initialize(void);
 
 /**
+ * Initialize the ZIP QUEUE buffer
+ *
+ * @param queue : ZIP instruction queue
+ * @param zcoremask : ZIP coremask to use for this queue
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_zip_queue_initialize(int queue, int zcoremask);
+
+/**
  * Shutdown the ZIP block. ZIP must be idle when
  * this function is called.
  *
@@ -233,6 +245,16 @@ int cvmx_zip_initialize(void);
 int cvmx_zip_shutdown(void);
 
 /**
+ * Shutdown the ZIP block for a queue. ZIP must be idle when
+ * this function is called.
+ *
+ * @param queue   Zip instruction queue of the command
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_zip_queue_shutdown(int queue);
+
+/**
  * Submit a command to the ZIP block
  *
  * @param command Zip command to submit
@@ -241,6 +263,16 @@ int cvmx_zip_shutdown(void);
  */
 int cvmx_zip_submit(cvmx_zip_command_t *command);
 
+/**
+ * Submit a command to the ZIP block
+ *
+ * @param command Zip command to submit
+ * @param queue   Zip instruction queue of the command
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_zip_queue_submit(cvmx_zip_command_t *command, int queue);
+
 /* CSR typedefs have been moved to cvmx-zip-defs.h */
 
 #ifdef	__cplusplus
diff --git a/sys/contrib/octeon-sdk/cvmx-zone.c b/sys/contrib/octeon-sdk/cvmx-zone.c
index 71ef679..aa65bbc 100644
--- a/sys/contrib/octeon-sdk/cvmx-zone.c
+++ b/sys/contrib/octeon-sdk/cvmx-zone.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Support library for the Zone Allocator.
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 
diff --git a/sys/contrib/octeon-sdk/cvmx.h b/sys/contrib/octeon-sdk/cvmx.h
index 9cb0a82..0b92bc3 100644
--- a/sys/contrib/octeon-sdk/cvmx.h
+++ b/sys/contrib/octeon-sdk/cvmx.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -45,7 +45,7 @@
  * Main Octeon executive header file (This should be the second header
  * file included by an application).
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
 */
 #ifndef __CVMX_H__
 #define __CVMX_H__
@@ -79,9 +79,9 @@ extern "C" {
 #include "cvmx-sysinfo.h"
 #include "octeon-model.h"
 #include "cvmx-csr.h"
-#include "octeon-feature.h"
 #include "cvmx-utils.h"
 #include "cvmx-clock.h"
+#include "octeon-feature.h"
 
 #if defined(__mips__) && !defined(CVMX_BUILD_FOR_LINUX_HOST)
 #include "cvmx-access-native.h"
diff --git a/sys/contrib/octeon-sdk/cvmx.mk b/sys/contrib/octeon-sdk/cvmx.mk
new file mode 100644
index 0000000..3e2442e
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx.mk
@@ -0,0 +1,187 @@
+#/***********************license start***************
+# Copyright (c) 2003-2007 Cavium Inc. (support@cavium.com). All rights
+# reserved.
+#
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+#
+#     * Neither the name of Cavium Inc. nor the names of
+#       its contributors may be used to endorse or promote products
+#       derived from this software without specific prior written
+#       permission.
+#
+# TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+# AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+# OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+# RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+# REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+# DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+# OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+# PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+# POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+# OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+#
+#
+# For any questions regarding licensing please contact marketing@cavium.com
+#
+# ***********************license end**************************************/
+
+#
+#  component Makefile fragment
+#
+
+#  standard component Makefile header
+sp              :=  $(sp).x
+dirstack_$(sp)  :=  $(d)
+d               :=  $(dir)
+
+#  component specification
+
+LIBRARY := $(OBJ_DIR)/libcvmx.a
+
+OBJS_$(d)  :=  \
+	$(OBJ_DIR)/cvmx-app-hotplug.o \
+	$(OBJ_DIR)/cvmx-bootmem.o \
+	$(OBJ_DIR)/cvmx-clock.o \
+	$(OBJ_DIR)/cvmx-cmd-queue.o \
+	$(OBJ_DIR)/cvmx-cn3010-evb-hs5.o \
+	$(OBJ_DIR)/cvmx-core.o \
+	$(OBJ_DIR)/cvmx-coremask.o \
+	$(OBJ_DIR)/cvmx-csr-db.o \
+	$(OBJ_DIR)/cvmx-csr-db-support.o \
+	$(OBJ_DIR)/cvmx-crypto.o \
+	$(OBJ_DIR)/cvmx-dfa.o \
+	$(OBJ_DIR)/cvmx-dma-engine.o \
+	$(OBJ_DIR)/cvmx-ebt3000.o \
+	$(OBJ_DIR)/cvmx-error.o \
+	$(OBJ_DIR)/cvmx-error-custom.o \
+	$(OBJ_DIR)/cvmx-error-init-cn30xx.o \
+	$(OBJ_DIR)/cvmx-error-init-cn31xx.o \
+	$(OBJ_DIR)/cvmx-error-init-cn38xx.o \
+	$(OBJ_DIR)/cvmx-error-init-cn38xxp2.o \
+	$(OBJ_DIR)/cvmx-error-init-cn50xx.o \
+	$(OBJ_DIR)/cvmx-error-init-cn52xx.o \
+	$(OBJ_DIR)/cvmx-error-init-cn52xxp1.o \
+	$(OBJ_DIR)/cvmx-error-init-cn56xx.o \
+	$(OBJ_DIR)/cvmx-error-init-cn56xxp1.o \
+	$(OBJ_DIR)/cvmx-error-init-cn58xx.o \
+	$(OBJ_DIR)/cvmx-error-init-cn58xxp1.o \
+	$(OBJ_DIR)/cvmx-error-init-cn61xx.o \
+	$(OBJ_DIR)/cvmx-error-init-cn63xx.o \
+	$(OBJ_DIR)/cvmx-error-init-cn63xxp1.o \
+	$(OBJ_DIR)/cvmx-error-init-cn66xx.o \
+	$(OBJ_DIR)/cvmx-error-init-cn68xx.o \
+	$(OBJ_DIR)/cvmx-error-init-cn68xxp1.o \
+	$(OBJ_DIR)/cvmx-error-init-cnf71xx.o \
+	$(OBJ_DIR)/cvmx-flash.o \
+	$(OBJ_DIR)/cvmx-fpa.o \
+	$(OBJ_DIR)/cvmx-helper-board.o \
+	$(OBJ_DIR)/cvmx-helper-errata.o \
+	$(OBJ_DIR)/cvmx-helper-cfg.o \
+	$(OBJ_DIR)/cvmx-helper-fpa.o \
+	$(OBJ_DIR)/cvmx-helper-ilk.o \
+	$(OBJ_DIR)/cvmx-helper-loop.o \
+	$(OBJ_DIR)/cvmx-helper-npi.o \
+	$(OBJ_DIR)/cvmx-helper-rgmii.o \
+	$(OBJ_DIR)/cvmx-helper-sgmii.o \
+	$(OBJ_DIR)/cvmx-helper-spi.o \
+	$(OBJ_DIR)/cvmx-helper-srio.o \
+	$(OBJ_DIR)/cvmx-helper-util.o \
+	$(OBJ_DIR)/cvmx-helper-xaui.o \
+	$(OBJ_DIR)/cvmx-helper-jtag.o \
+	$(OBJ_DIR)/cvmx-helper.o \
+	$(OBJ_DIR)/cvmx-hfa.o \
+	$(OBJ_DIR)/cvmx-ilk.o \
+	$(OBJ_DIR)/cvmx-ipd.o \
+	$(OBJ_DIR)/cvmx-ixf18201.o \
+	$(OBJ_DIR)/cvmx-l2c.o \
+	$(OBJ_DIR)/cvmx-llm.o \
+	$(OBJ_DIR)/cvmx-log-arc.o \
+	$(OBJ_DIR)/cvmx-log.o \
+	$(OBJ_DIR)/cvmx-mgmt-port.o \
+	$(OBJ_DIR)/cvmx-nand.o \
+	$(OBJ_DIR)/cvmx-pcie.o \
+	$(OBJ_DIR)/cvmx-pko.o \
+	$(OBJ_DIR)/cvmx-pow.o \
+	$(OBJ_DIR)/cvmx-power-throttle.o \
+	$(OBJ_DIR)/cvmx-profiler.o \
+	$(OBJ_DIR)/cvmx-qlm.o \
+	$(OBJ_DIR)/cvmx-qlm-tables.o \
+	$(OBJ_DIR)/cvmx-raid.o \
+	$(OBJ_DIR)/cvmx-shmem.o \
+	$(OBJ_DIR)/cvmx-spi.o \
+	$(OBJ_DIR)/cvmx-spi4000.o \
+	$(OBJ_DIR)/cvmx-srio.o \
+	$(OBJ_DIR)/cvmx-sysinfo.o \
+	$(OBJ_DIR)/cvmx-thunder.o \
+	$(OBJ_DIR)/cvmx-tim.o \
+	$(OBJ_DIR)/cvmx-tlb.o \
+	$(OBJ_DIR)/cvmx-tra.o \
+	$(OBJ_DIR)/cvmx-twsi.o \
+	$(OBJ_DIR)/cvmx-usb.o \
+	$(OBJ_DIR)/cvmx-usbd.o \
+	$(OBJ_DIR)/cvmx-warn.o \
+	$(OBJ_DIR)/cvmx-zip.o \
+	$(OBJ_DIR)/cvmx-zone.o \
+	$(OBJ_DIR)/octeon-feature.o \
+	$(OBJ_DIR)/octeon-model.o \
+	$(OBJ_DIR)/octeon-pci-console.o
+ifeq (linux,$(findstring linux,$(OCTEON_TARGET)))
+OBJS_$(d)  +=  \
+	$(OBJ_DIR)/cvmx-app-init-linux.o
+else
+OBJS_$(d)  +=  \
+	$(OBJ_DIR)/cvmx-debug.o \
+	$(OBJ_DIR)/cvmx-debug-handler.o \
+	$(OBJ_DIR)/cvmx-debug-remote.o \
+	$(OBJ_DIR)/cvmx-debug-uart.o \
+	$(OBJ_DIR)/cvmx-interrupt.o \
+	$(OBJ_DIR)/cvmx-interrupt-handler.o \
+	$(OBJ_DIR)/cvmx-app-init.o \
+	$(OBJ_DIR)/cvmx-malloc.o \
+	$(OBJ_DIR)/cvmx-uart.o
+endif
+
+$(OBJS_$(d)):  CFLAGS_LOCAL := -I$(d) -O2 -g -W -Wall -Wno-unused-parameter -Wundef -G0
+
+#  standard component Makefile rules
+
+DEPS_$(d)   :=  $(OBJS_$(d):.o=.d)
+
+LIBS_LIST   :=  $(LIBS_LIST) $(LIBRARY)
+
+CLEAN_LIST  :=  $(CLEAN_LIST) $(OBJS_$(d)) $(DEPS_$(d)) $(LIBRARY)
+
+-include $(DEPS_$(d))
+
+$(LIBRARY): $(OBJS_$(d))
+	$(AR) -cr $@ $^
+
+$(OBJ_DIR)/%.o:	$(d)/%.c
+	$(COMPILE)
+
+$(OBJ_DIR)/%.o:	$(d)/%.S
+	$(ASSEMBLE)
+
+$(OBJ_DIR)/cvmx-app-init-linux.o: $(d)/cvmx-app-init-linux.c
+	$(CC) $(CFLAGS_GLOBAL) $(CFLAGS_LOCAL) -MD -c -Umain -o $@ $<
+
+CFLAGS_SPECIAL := -I$(d) -I$(d)/cvmx-malloc -O2 -g -DUSE_CVM_THREADS=1 -D_REENTRANT
+
+$(OBJ_DIR)/cvmx-malloc.o: $(d)/cvmx-malloc/malloc.c
+	$(CC) $(CFLAGS_GLOBAL) $(CFLAGS_SPECIAL) -MD -c -o $@ $<
+
+#  standard component Makefile footer
+
+d   :=  $(dirstack_$(sp))
+sp  :=  $(basename $(sp))
diff --git a/sys/contrib/octeon-sdk/executive-config.h.template b/sys/contrib/octeon-sdk/executive-config.h.template
new file mode 100644
index 0000000..ca512f6
--- /dev/null
+++ b/sys/contrib/octeon-sdk/executive-config.h.template
@@ -0,0 +1,184 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights 
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.  
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries. 
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+
+/*!
+ * @file executive-config.h.template
+ *
+ * This file is a template for the executive-config.h file that each
+ * application that uses the simple exec must provide.  Each application
+ * should have an executive-config.h file in a directory named 'config'.
+ * If the application uses other components, config files for those
+ * components should be placed in the config directory as well.  The
+ * macros defined in this file control the configuration and functionality
+ * provided by the simple executive.  Available macros are commented out
+ * and documented in this file.
+ */
+
+/*
+ * File version info: $Id: executive-config.h.template 70030 2012-02-16 04:23:43Z cchavva $
+ *
+ */
+#ifndef __EXECUTIVE_CONFIG_H__
+#define __EXECUTIVE_CONFIG_H__
+
+/* Define to enable the use of simple executive DFA functions */
+//#define CVMX_ENABLE_DFA_FUNCTIONS
+
+/* Define to enable the use of simple executive packet output functions.
+** For packet I/O setup enable the helper functions below.
+*/
+//#define CVMX_ENABLE_PKO_FUNCTIONS
+
+/* Define to enable the use of simple executive timer bucket functions.
+** Refer to cvmx-tim.[ch] for more information
+*/
+//#define CVMX_ENABLE_TIMER_FUNCTIONS
+
+/* Define to enable the use of simple executive helper functions. These
+** include many harware setup functions.  See cvmx-helper.[ch] for
+** details.
+*/
+//#define CVMX_ENABLE_HELPER_FUNCTIONS
+
+/* CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve before
+** the beginning of the packet. If necessary, override the default
+** here.  See the IPD section of the hardware manual for MBUFF SKIP
+** details.*/
+#define CVMX_HELPER_FIRST_MBUFF_SKIP 184
+
+/* CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve in each
+** chained packet element. If necessary, override the default here */
+#define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0
+
+/* CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper
+**  function. Once it is enabled the hardware starts accepting packets. You
+**  might want to skip the IPD enable if configuration changes are need
+**  from the default helper setup. If necessary, override the default here */
+#define CVMX_HELPER_ENABLE_IPD 1
+
+/* CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns
+** to incoming packets. */
+#define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED
+
+/* The following select which fields are used by the PIP to generate
+** the tag on INPUT
+** 0: don't include
+** 1: include */
+#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP	0
+#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP   	0
+#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 	0
+#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 	0
+#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 	0
+#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP	0
+#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP   	0
+#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 	0
+#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 	0
+#define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL	0
+#define CVMX_HELPER_INPUT_TAG_INPUT_PORT	1
+
+/* Select skip mode for input ports */
+#define CVMX_HELPER_INPUT_PORT_SKIP_MODE	CVMX_PIP_PORT_CFG_MODE_SKIPL2
+
+/* Define the number of queues per output port */
+#define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE0	1
+#define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE1	1
+
+/* Configure PKO to use per-core queues (PKO lockless operation).
+** Please see the related SDK documentation for PKO that illustrates
+** how to enable and configure this option. */
+//#define CVMX_ENABLE_PKO_LOCKLESS_OPERATION 1
+//#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 8
+//#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 8
+
+/* Force backpressure to be disabled.  This overrides all other
+** backpressure configuration */
+#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 1
+
+/* Disable the SPI4000's processing of backpressure packets and backpressure
+** generation. When this is 1, the SPI4000 will not stop sending packets when
+** receiving backpressure. It will also not generate backpressure packets when
+** its internal FIFOs are full. */
+#define CVMX_HELPER_DISABLE_SPI4000_BACKPRESSURE 1
+
+/* Configure number of pipes the SLI/DPI supports, only available in ebb6800.
+** The SLI/DPI can support upto 32 pipes assigned to packet-rings 0 - 31. */
+//#define CVMX_HELPER_NPI_MAX_PIPES 32
+
+/* CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI initialization
+** routines wait for SPI training. You can override the value using
+** executive-config.h if necessary */
+#define CVMX_HELPER_SPI_TIMEOUT 10
+
+/* Select the number of low latency memory ports (interfaces) that
+** will be configured.  Valid values are 1 and 2.
+*/
+#define CVMX_LLM_CONFIG_NUM_PORTS 2
+
+/* Enable the fix for PKI-100 errata ("Size field is 8 too large in WQE and next
+** pointers"). If CVMX_ENABLE_LEN_M8_FIX is set to 0, the fix for this errata will
+** not be enabled.
+** 0: Fix is not enabled
+** 1: Fix is enabled, if supported by hardware
+*/
+#define CVMX_ENABLE_LEN_M8_FIX  1
+
+#if defined(CVMX_ENABLE_HELPER_FUNCTIONS) && !defined(CVMX_ENABLE_PKO_FUNCTIONS)
+#define CVMX_ENABLE_PKO_FUNCTIONS
+#endif
+
+/* Enable setting up of TLB entries to trap NULL pointer references */
+#define CVMX_CONFIG_NULL_POINTER_PROTECT	1
+
+/* Enable debug and informational printfs */
+#define CVMX_CONFIG_ENABLE_DEBUG_PRINTS 	1
+
+/* Select IPD cache mode, default to get all blocks from DRAM (not cached in L2). */
+#define CVMX_HELPER_IPD_DRAM_MODE               CVMX_IPD_OPC_MODE_STT
+
+/* Allow attaching of the debugger to UART 1 or PCI debugging even when -debug is not
+   supplied on the boot line. */
+#define CVMX_DEBUG_ATTACH 1
+
+/* Executive resource descriptions provided in cvmx-resources.config */
+#include "cvmx-resources.config"
+
+#endif
diff --git a/sys/contrib/octeon-sdk/libfdt/fdt.c b/sys/contrib/octeon-sdk/libfdt/fdt.c
new file mode 100644
index 0000000..0367398
--- /dev/null
+++ b/sys/contrib/octeon-sdk/libfdt/fdt.c
@@ -0,0 +1,201 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#include <fdt.h>
+#include <libfdt.h>
+
+#include "libfdt_internal.h"
+
+int fdt_check_header(const void *fdt)
+{
+	if (fdt_magic(fdt) == FDT_MAGIC) {
+		/* Complete tree */
+		if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION)
+			return -FDT_ERR_BADVERSION;
+		if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION)
+			return -FDT_ERR_BADVERSION;
+	} else if (fdt_magic(fdt) == FDT_SW_MAGIC) {
+		/* Unfinished sequential-write blob */
+		if (fdt_size_dt_struct(fdt) == 0)
+			return -FDT_ERR_BADSTATE;
+	} else {
+		return -FDT_ERR_BADMAGIC;
+	}
+
+	return 0;
+}
+
+const void *fdt_offset_ptr(const void *fdt, int offset, int len)
+{
+	const char *p;
+
+	if (fdt_version(fdt) >= 0x11)
+		if (((offset + len) < offset)
+		    || ((offset + len) > (int)fdt_size_dt_struct(fdt)))
+			return NULL;
+
+	p = _fdt_offset_ptr(fdt, offset);
+
+	if (p + len < p)
+		return NULL;
+	return p;
+}
+
+uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset)
+{
+	const uint32_t *tagp, *lenp;
+	uint32_t tag;
+	const char *p;
+
+	if (offset % FDT_TAGSIZE)
+		return -1;
+
+	tagp = fdt_offset_ptr(fdt, offset, FDT_TAGSIZE);
+	if (! tagp)
+		return FDT_END; /* premature end */
+	tag = fdt32_to_cpu(*tagp);
+	offset += FDT_TAGSIZE;
+
+	switch (tag) {
+	case FDT_BEGIN_NODE:
+		/* skip name */
+		do {
+			p = fdt_offset_ptr(fdt, offset++, 1);
+		} while (p && (*p != '\0'));
+		if (! p)
+			return FDT_END;
+		break;
+	case FDT_PROP:
+		lenp = fdt_offset_ptr(fdt, offset, sizeof(*lenp));
+		if (! lenp)
+			return FDT_END;
+		/* skip name offset, length and value */
+		offset += 2*FDT_TAGSIZE + fdt32_to_cpu(*lenp);
+		break;
+	}
+
+	if (nextoffset)
+		*nextoffset = FDT_TAGALIGN(offset);
+
+	return tag;
+}
+
+int _fdt_check_node_offset(const void *fdt, int offset)
+{
+	if ((offset < 0) || (offset % FDT_TAGSIZE)
+	    || (fdt_next_tag(fdt, offset, &offset) != FDT_BEGIN_NODE))
+		return -FDT_ERR_BADOFFSET;
+
+	return offset;
+}
+
+int fdt_next_node(const void *fdt, int offset, int *depth)
+{
+	int nextoffset = 0;
+	uint32_t tag;
+
+	if (offset >= 0)
+		if ((nextoffset = _fdt_check_node_offset(fdt, offset)) < 0)
+			return nextoffset;
+
+	do {
+		offset = nextoffset;
+		tag = fdt_next_tag(fdt, offset, &nextoffset);
+
+		switch (tag) {
+		case FDT_PROP:
+		case FDT_NOP:
+			break;
+
+		case FDT_BEGIN_NODE:
+			if (depth)
+				(*depth)++;
+			break;
+
+		case FDT_END_NODE:
+			if (depth)
+				(*depth)--;
+			break;
+
+		case FDT_END:
+			return -FDT_ERR_NOTFOUND;
+
+		default:
+			return -FDT_ERR_BADSTRUCTURE;
+		}
+	} while (tag != FDT_BEGIN_NODE);
+
+	return offset;
+}
+
+const char *_fdt_find_string(const char *strtab, int tabsize, const char *s)
+{
+	int len = strlen(s) + 1;
+	const char *last = strtab + tabsize - len;
+	const char *p;
+
+	for (p = strtab; p <= last; p++)
+		if (memcmp(p, s, len) == 0)
+			return p;
+	return NULL;
+}
+
+int fdt_move(const void *fdt, void *buf, int bufsize)
+{
+	FDT_CHECK_HEADER(fdt);
+
+	if ((int)fdt_totalsize(fdt) > bufsize)
+		return -FDT_ERR_NOSPACE;
+
+	memmove(buf, fdt, fdt_totalsize(fdt));
+	return 0;
+}
diff --git a/sys/contrib/octeon-sdk/libfdt/fdt.h b/sys/contrib/octeon-sdk/libfdt/fdt.h
new file mode 100644
index 0000000..48ccfd9
--- /dev/null
+++ b/sys/contrib/octeon-sdk/libfdt/fdt.h
@@ -0,0 +1,60 @@
+#ifndef _FDT_H
+#define _FDT_H
+
+#ifndef __ASSEMBLY__
+
+struct fdt_header {
+	uint32_t magic;			 /* magic word FDT_MAGIC */
+	uint32_t totalsize;		 /* total size of DT block */
+	uint32_t off_dt_struct;		 /* offset to structure */
+	uint32_t off_dt_strings;	 /* offset to strings */
+	uint32_t off_mem_rsvmap;	 /* offset to memory reserve map */
+	uint32_t version;		 /* format version */
+	uint32_t last_comp_version;	 /* last compatible version */
+
+	/* version 2 fields below */
+	uint32_t boot_cpuid_phys;	 /* Which physical CPU id we're
+					    booting on */
+	/* version 3 fields below */
+	uint32_t size_dt_strings;	 /* size of the strings block */
+
+	/* version 17 fields below */
+	uint32_t size_dt_struct;	 /* size of the structure block */
+};
+
+struct fdt_reserve_entry {
+	uint64_t address;
+	uint64_t size;
+};
+
+struct fdt_node_header {
+	uint32_t tag;
+	char name[0];
+};
+
+struct fdt_property {
+	uint32_t tag;
+	uint32_t len;
+	uint32_t nameoff;
+	char data[0];
+};
+
+#endif /* !__ASSEMBLY */
+
+#define FDT_MAGIC	0xd00dfeed	/* 4: version, 4: total size */
+#define FDT_TAGSIZE	sizeof(uint32_t)
+
+#define FDT_BEGIN_NODE	0x1		/* Start node: full name */
+#define FDT_END_NODE	0x2		/* End node */
+#define FDT_PROP	0x3		/* Property: name off,
+					   size, content */
+#define FDT_NOP		0x4		/* nop */
+#define FDT_END		0x9
+
+#define FDT_V1_SIZE	(7*sizeof(uint32_t))
+#define FDT_V2_SIZE	(FDT_V1_SIZE + sizeof(uint32_t))
+#define FDT_V3_SIZE	(FDT_V2_SIZE + sizeof(uint32_t))
+#define FDT_V16_SIZE	FDT_V3_SIZE
+#define FDT_V17_SIZE	(FDT_V16_SIZE + sizeof(uint32_t))
+
+#endif /* _FDT_H */
diff --git a/sys/contrib/octeon-sdk/libfdt/fdt_ro.c b/sys/contrib/octeon-sdk/libfdt/fdt_ro.c
new file mode 100644
index 0000000..68ff7a9
--- /dev/null
+++ b/sys/contrib/octeon-sdk/libfdt/fdt_ro.c
@@ -0,0 +1,469 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#include <fdt.h>
+#include <libfdt.h>
+
+#include "libfdt_internal.h"
+
+static int _fdt_nodename_eq(const void *fdt, int offset,
+			    const char *s, int len)
+{
+	const char *p = fdt_offset_ptr(fdt, offset + FDT_TAGSIZE, len+1);
+
+	if (! p)
+		/* short match */
+		return 0;
+
+	if (memcmp(p, s, len) != 0)
+		return 0;
+
+	if (p[len] == '\0')
+		return 1;
+	else if (!memchr(s, '@', len) && (p[len] == '@'))
+		return 1;
+	else
+		return 0;
+}
+
+const char *fdt_string(const void *fdt, int stroffset)
+{
+	return (const char *)fdt + fdt_off_dt_strings(fdt) + stroffset;
+}
+
+int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size)
+{
+	FDT_CHECK_HEADER(fdt);
+	*address = fdt64_to_cpu(_fdt_mem_rsv(fdt, n)->address);
+	*size = fdt64_to_cpu(_fdt_mem_rsv(fdt, n)->size);
+	return 0;
+}
+
+int fdt_num_mem_rsv(const void *fdt)
+{
+	int i = 0;
+
+	while (fdt64_to_cpu(_fdt_mem_rsv(fdt, i)->size) != 0)
+		i++;
+	return i;
+}
+
+int fdt_subnode_offset_namelen(const void *fdt, int offset,
+			       const char *name, int namelen)
+{
+	int depth;
+
+	FDT_CHECK_HEADER(fdt);
+
+	for (depth = 0, offset = fdt_next_node(fdt, offset, &depth);
+	     (offset >= 0) && (depth > 0);
+	     offset = fdt_next_node(fdt, offset, &depth)) {
+		if (depth < 0)
+			return -FDT_ERR_NOTFOUND;
+		else if ((depth == 1)
+			 && _fdt_nodename_eq(fdt, offset, name, namelen))
+			return offset;
+	}
+
+	if (offset < 0)
+		return offset; /* error */
+	else
+		return -FDT_ERR_NOTFOUND;
+}
+
+int fdt_subnode_offset(const void *fdt, int parentoffset,
+		       const char *name)
+{
+	return fdt_subnode_offset_namelen(fdt, parentoffset, name, strlen(name));
+}
+
+int fdt_path_offset(const void *fdt, const char *path)
+{
+	const char *end = path + strlen(path);
+	const char *p = path;
+	int offset = 0;
+
+	FDT_CHECK_HEADER(fdt);
+
+	if (*path != '/')
+		return -FDT_ERR_BADPATH;
+
+	while (*p) {
+		const char *q;
+
+		while (*p == '/')
+			p++;
+		if (! *p)
+			return offset;
+		q = strchr(p, '/');
+		if (! q)
+			q = end;
+
+		offset = fdt_subnode_offset_namelen(fdt, offset, p, q-p);
+		if (offset < 0)
+			return offset;
+
+		p = q;
+	}
+
+	return offset;
+}
+
+const char *fdt_get_name(const void *fdt, int nodeoffset, int *len)
+{
+	const struct fdt_node_header *nh = _fdt_offset_ptr(fdt, nodeoffset);
+	int err;
+
+	if (((err = fdt_check_header(fdt)) != 0)
+	    || ((err = _fdt_check_node_offset(fdt, nodeoffset)) < 0))
+			goto fail;
+
+	if (len)
+		*len = strlen(nh->name);
+
+	return nh->name;
+
+ fail:
+	if (len)
+		*len = err;
+	return NULL;
+}
+
+const struct fdt_property *fdt_get_property(const void *fdt,
+					    int nodeoffset,
+					    const char *name, int *lenp)
+{
+	uint32_t tag;
+	const struct fdt_property *prop;
+	int namestroff;
+	int offset, nextoffset;
+	int err;
+
+	if (((err = fdt_check_header(fdt)) != 0)
+	    || ((err = _fdt_check_node_offset(fdt, nodeoffset)) < 0))
+			goto fail;
+
+	nextoffset = err;
+	do {
+		offset = nextoffset;
+
+		tag = fdt_next_tag(fdt, offset, &nextoffset);
+		switch (tag) {
+		case FDT_END:
+			err = -FDT_ERR_TRUNCATED;
+			goto fail;
+
+		case FDT_BEGIN_NODE:
+		case FDT_END_NODE:
+		case FDT_NOP:
+			break;
+
+		case FDT_PROP:
+			err = -FDT_ERR_BADSTRUCTURE;
+			prop = fdt_offset_ptr(fdt, offset, sizeof(*prop));
+			if (! prop)
+				goto fail;
+			namestroff = fdt32_to_cpu(prop->nameoff);
+			if (strcmp(fdt_string(fdt, namestroff), name) == 0) {
+				/* Found it! */
+				int len = fdt32_to_cpu(prop->len);
+				prop = fdt_offset_ptr(fdt, offset,
+						      sizeof(*prop)+len);
+				if (! prop)
+					goto fail;
+
+				if (lenp)
+					*lenp = len;
+
+				return prop;
+			}
+			break;
+
+		default:
+			err = -FDT_ERR_BADSTRUCTURE;
+			goto fail;
+		}
+	} while ((tag != FDT_BEGIN_NODE) && (tag != FDT_END_NODE));
+
+	err = -FDT_ERR_NOTFOUND;
+ fail:
+	if (lenp)
+		*lenp = err;
+	return NULL;
+}
+
+const void *fdt_getprop(const void *fdt, int nodeoffset,
+		  const char *name, int *lenp)
+{
+	const struct fdt_property *prop;
+
+	prop = fdt_get_property(fdt, nodeoffset, name, lenp);
+	if (! prop)
+		return NULL;
+
+	return prop->data;
+}
+
+uint32_t fdt_get_phandle(const void *fdt, int nodeoffset)
+{
+	const uint32_t *php;
+	int len;
+
+	php = fdt_getprop(fdt, nodeoffset, "linux,phandle", &len);
+	if (!php || (len != sizeof(*php)))
+		return 0;
+
+	return fdt32_to_cpu(*php);
+}
+
+int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen)
+{
+	int pdepth = 0, p = 0;
+	int offset, depth, namelen;
+	const char *name;
+
+	FDT_CHECK_HEADER(fdt);
+
+	if (buflen < 2)
+		return -FDT_ERR_NOSPACE;
+
+	for (offset = 0, depth = 0;
+	     (offset >= 0) && (offset <= nodeoffset);
+	     offset = fdt_next_node(fdt, offset, &depth)) {
+		if (pdepth < depth)
+			continue; /* overflowed buffer */
+
+		while (pdepth > depth) {
+			do {
+				p--;
+			} while (buf[p-1] != '/');
+			pdepth--;
+		}
+
+		name = fdt_get_name(fdt, offset, &namelen);
+		if (!name)
+			return namelen;
+		if ((p + namelen + 1) <= buflen) {
+			memcpy(buf + p, name, namelen);
+			p += namelen;
+			buf[p++] = '/';
+			pdepth++;
+		}
+
+		if (offset == nodeoffset) {
+			if (pdepth < (depth + 1))
+				return -FDT_ERR_NOSPACE;
+
+			if (p > 1) /* special case so that root path is "/", not "" */
+				p--;
+			buf[p] = '\0';
+			return p;
+		}
+	}
+
+	if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0))
+		return -FDT_ERR_BADOFFSET;
+	else if (offset == -FDT_ERR_BADOFFSET)
+		return -FDT_ERR_BADSTRUCTURE;
+
+	return offset; /* error from fdt_next_node() */
+}
+
+int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
+				 int supernodedepth, int *nodedepth)
+{
+	int offset, depth;
+	int supernodeoffset = -FDT_ERR_INTERNAL;
+
+	FDT_CHECK_HEADER(fdt);
+
+	if (supernodedepth < 0)
+		return -FDT_ERR_NOTFOUND;
+
+	for (offset = 0, depth = 0;
+	     (offset >= 0) && (offset <= nodeoffset);
+	     offset = fdt_next_node(fdt, offset, &depth)) {
+		if (depth == supernodedepth)
+			supernodeoffset = offset;
+
+		if (offset == nodeoffset) {
+			if (nodedepth)
+				*nodedepth = depth;
+
+			if (supernodedepth > depth)
+				return -FDT_ERR_NOTFOUND;
+			else
+				return supernodeoffset;
+		}
+	}
+
+	if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0))
+		return -FDT_ERR_BADOFFSET;
+	else if (offset == -FDT_ERR_BADOFFSET)
+		return -FDT_ERR_BADSTRUCTURE;
+
+	return offset; /* error from fdt_next_node() */
+}
+
+int fdt_node_depth(const void *fdt, int nodeoffset)
+{
+	int nodedepth;
+	int err;
+
+	err = fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, &nodedepth);
+	if (err)
+		return (err < 0) ? err : -FDT_ERR_INTERNAL;
+	return nodedepth;
+}
+
+int fdt_parent_offset(const void *fdt, int nodeoffset)
+{
+	int nodedepth = fdt_node_depth(fdt, nodeoffset);
+
+	if (nodedepth < 0)
+		return nodedepth;
+	return fdt_supernode_atdepth_offset(fdt, nodeoffset,
+					    nodedepth - 1, NULL);
+}
+
+int fdt_node_offset_by_prop_value(const void *fdt, int startoffset,
+				  const char *propname,
+				  const void *propval, int proplen)
+{
+	int offset;
+	const void *val;
+	int len;
+
+	FDT_CHECK_HEADER(fdt);
+
+	/* FIXME: The algorithm here is pretty horrible: we scan each
+	 * property of a node in fdt_getprop(), then if that didn't
+	 * find what we want, we scan over them again making our way
+	 * to the next node.  Still it's the easiest to implement
+	 * approach; performance can come later. */
+	for (offset = fdt_next_node(fdt, startoffset, NULL);
+	     offset >= 0;
+	     offset = fdt_next_node(fdt, offset, NULL)) {
+		val = fdt_getprop(fdt, offset, propname, &len);
+		if (val && (len == proplen)
+		    && (memcmp(val, propval, len) == 0))
+			return offset;
+	}
+
+	return offset; /* error from fdt_next_node() */
+}
+
+int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle)
+{
+	if ((phandle == 0) || (phandle == -1u))
+		return -FDT_ERR_BADPHANDLE;
+	phandle = cpu_to_fdt32(phandle);
+	return fdt_node_offset_by_prop_value(fdt, -1, "linux,phandle",
+					     &phandle, sizeof(phandle));
+}
+
+static int _stringlist_contains(const char *strlist, int listlen, const char *str)
+{
+	int len = strlen(str);
+	const char *p;
+
+	while (listlen >= len) {
+		if (memcmp(str, strlist, len+1) == 0)
+			return 1;
+		p = memchr(strlist, '\0', listlen);
+		if (!p)
+			return 0; /* malformed strlist.. */
+		listlen -= (p-strlist) + 1;
+		strlist = p + 1;
+	}
+	return 0;
+}
+
+int fdt_node_check_compatible(const void *fdt, int nodeoffset,
+			      const char *compatible)
+{
+	const void *prop;
+	int len;
+
+	prop = fdt_getprop(fdt, nodeoffset, "compatible", &len);
+	if (!prop)
+		return len;
+	if (_stringlist_contains(prop, len, compatible))
+		return 0;
+	else
+		return 1;
+}
+
+int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
+				  const char *compatible)
+{
+	int offset, err;
+
+	FDT_CHECK_HEADER(fdt);
+
+	/* FIXME: The algorithm here is pretty horrible: we scan each
+	 * property of a node in fdt_node_check_compatible(), then if
+	 * that didn't find what we want, we scan over them again
+	 * making our way to the next node.  Still it's the easiest to
+	 * implement approach; performance can come later. */
+	for (offset = fdt_next_node(fdt, startoffset, NULL);
+	     offset >= 0;
+	     offset = fdt_next_node(fdt, offset, NULL)) {
+		err = fdt_node_check_compatible(fdt, offset, compatible);
+		if ((err < 0) && (err != -FDT_ERR_NOTFOUND))
+			return err;
+		else if (err == 0)
+			return offset;
+	}
+
+	return offset; /* error from fdt_next_node() */
+}
diff --git a/sys/contrib/octeon-sdk/libfdt/fdt_rw.c b/sys/contrib/octeon-sdk/libfdt/fdt_rw.c
new file mode 100644
index 0000000..8e7ec4c
--- /dev/null
+++ b/sys/contrib/octeon-sdk/libfdt/fdt_rw.c
@@ -0,0 +1,463 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#include <fdt.h>
+#include <libfdt.h>
+
+#include "libfdt_internal.h"
+
+static int _fdt_blocks_misordered(const void *fdt,
+			      int mem_rsv_size, int struct_size)
+{
+	return (fdt_off_mem_rsvmap(fdt) < FDT_ALIGN(sizeof(struct fdt_header), 8))
+		|| (fdt_off_dt_struct(fdt) <
+		    (fdt_off_mem_rsvmap(fdt) + mem_rsv_size))
+		|| (fdt_off_dt_strings(fdt) <
+		    (fdt_off_dt_struct(fdt) + struct_size))
+		|| (fdt_totalsize(fdt) <
+		    (fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt)));
+}
+
+static int _fdt_rw_check_header(void *fdt)
+{
+	FDT_CHECK_HEADER(fdt);
+
+	if (fdt_version(fdt) < 17)
+		return -FDT_ERR_BADVERSION;
+	if (_fdt_blocks_misordered(fdt, sizeof(struct fdt_reserve_entry),
+				   fdt_size_dt_struct(fdt)))
+		return -FDT_ERR_BADLAYOUT;
+	if (fdt_version(fdt) > 17)
+		fdt_set_version(fdt, 17);
+
+	return 0;
+}
+
+#define FDT_RW_CHECK_HEADER(fdt) \
+	{ \
+		int err; \
+		if ((err = _fdt_rw_check_header(fdt)) != 0) \
+			return err; \
+	}
+
+static inline int _fdt_data_size(void *fdt)
+{
+	return fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt);
+}
+
+static int _fdt_splice(void *fdt, void *splicepoint, int oldlen, int newlen)
+{
+	char *p = splicepoint;
+	char *end = (char *)fdt + _fdt_data_size(fdt);
+
+	if (((p + oldlen) < p) || ((p + oldlen) > end))
+		return -FDT_ERR_BADOFFSET;
+	if ((end - oldlen + newlen) > ((char *)fdt + fdt_totalsize(fdt)))
+		return -FDT_ERR_NOSPACE;
+	memmove(p + newlen, p + oldlen, end - p - oldlen);
+	return 0;
+}
+
+static int _fdt_splice_mem_rsv(void *fdt, struct fdt_reserve_entry *p,
+			       int oldn, int newn)
+{
+	int delta = (newn - oldn) * sizeof(*p);
+	int err;
+	err = _fdt_splice(fdt, p, oldn * sizeof(*p), newn * sizeof(*p));
+	if (err)
+		return err;
+	fdt_set_off_dt_struct(fdt, fdt_off_dt_struct(fdt) + delta);
+	fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta);
+	return 0;
+}
+
+static int _fdt_splice_struct(void *fdt, void *p,
+			      int oldlen, int newlen)
+{
+	int delta = newlen - oldlen;
+	int err;
+
+	if ((err = _fdt_splice(fdt, p, oldlen, newlen)))
+		return err;
+
+	fdt_set_size_dt_struct(fdt, fdt_size_dt_struct(fdt) + delta);
+	fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta);
+	return 0;
+}
+
+static int _fdt_splice_string(void *fdt, int newlen)
+{
+	void *p = (char *)fdt
+		+ fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt);
+	int err;
+
+	if ((err = _fdt_splice(fdt, p, 0, newlen)))
+		return err;
+
+	fdt_set_size_dt_strings(fdt, fdt_size_dt_strings(fdt) + newlen);
+	return 0;
+}
+
+static int _fdt_find_add_string(void *fdt, const char *s)
+{
+	char *strtab = (char *)fdt + fdt_off_dt_strings(fdt);
+	const char *p;
+	char *new;
+	int len = strlen(s) + 1;
+	int err;
+
+	p = _fdt_find_string(strtab, fdt_size_dt_strings(fdt), s);
+	if (p)
+		/* found it */
+		return (p - strtab);
+
+	new = strtab + fdt_size_dt_strings(fdt);
+	err = _fdt_splice_string(fdt, len);
+	if (err)
+		return err;
+
+	memcpy(new, s, len);
+	return (new - strtab);
+}
+
+int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size)
+{
+	struct fdt_reserve_entry *re;
+	int err;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	re = _fdt_mem_rsv_w(fdt, fdt_num_mem_rsv(fdt));
+	err = _fdt_splice_mem_rsv(fdt, re, 0, 1);
+	if (err)
+		return err;
+
+	re->address = cpu_to_fdt64(address);
+	re->size = cpu_to_fdt64(size);
+	return 0;
+}
+
+int fdt_del_mem_rsv(void *fdt, int n)
+{
+	struct fdt_reserve_entry *re = _fdt_mem_rsv_w(fdt, n);
+	int err;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	if (n >= fdt_num_mem_rsv(fdt))
+		return -FDT_ERR_NOTFOUND;
+
+	err = _fdt_splice_mem_rsv(fdt, re, 1, 0);
+	if (err)
+		return err;
+	return 0;
+}
+
+static int _fdt_resize_property(void *fdt, int nodeoffset, const char *name,
+				int len, struct fdt_property **prop)
+{
+	int oldlen;
+	int err;
+
+	*prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen);
+	if (! (*prop))
+		return oldlen;
+
+	if ((err = _fdt_splice_struct(fdt, (*prop)->data, FDT_TAGALIGN(oldlen),
+				      FDT_TAGALIGN(len))))
+		return err;
+
+	(*prop)->len = cpu_to_fdt32(len);
+	return 0;
+}
+
+static int _fdt_add_property(void *fdt, int nodeoffset, const char *name,
+			     int len, struct fdt_property **prop)
+{
+	int proplen;
+	int nextoffset;
+	int namestroff;
+	int err;
+
+	if ((nextoffset = _fdt_check_node_offset(fdt, nodeoffset)) < 0)
+		return nextoffset;
+
+	namestroff = _fdt_find_add_string(fdt, name);
+	if (namestroff < 0)
+		return namestroff;
+
+	*prop = _fdt_offset_ptr_w(fdt, nextoffset);
+	proplen = sizeof(**prop) + FDT_TAGALIGN(len);
+
+	err = _fdt_splice_struct(fdt, *prop, 0, proplen);
+	if (err)
+		return err;
+
+	(*prop)->tag = cpu_to_fdt32(FDT_PROP);
+	(*prop)->nameoff = cpu_to_fdt32(namestroff);
+	(*prop)->len = cpu_to_fdt32(len);
+	return 0;
+}
+
+int fdt_set_name(void *fdt, int nodeoffset, const char *name)
+{
+	char *namep;
+	int oldlen, newlen;
+	int err;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	namep = (char *)(uintptr_t)fdt_get_name(fdt, nodeoffset, &oldlen);
+	if (!namep)
+		return oldlen;
+
+	newlen = strlen(name);
+
+	err = _fdt_splice_struct(fdt, namep, FDT_TAGALIGN(oldlen+1),
+				 FDT_TAGALIGN(newlen+1));
+	if (err)
+		return err;
+
+	memcpy(namep, name, newlen+1);
+	return 0;
+}
+
+int fdt_setprop(void *fdt, int nodeoffset, const char *name,
+		const void *val, int len)
+{
+	struct fdt_property *prop;
+	int err;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	err = _fdt_resize_property(fdt, nodeoffset, name, len, &prop);
+	if (err == -FDT_ERR_NOTFOUND)
+		err = _fdt_add_property(fdt, nodeoffset, name, len, &prop);
+	if (err)
+		return err;
+
+	memcpy(prop->data, val, len);
+	return 0;
+}
+
+int fdt_delprop(void *fdt, int nodeoffset, const char *name)
+{
+	struct fdt_property *prop;
+	int len, proplen;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	prop = fdt_get_property_w(fdt, nodeoffset, name, &len);
+	if (! prop)
+		return len;
+
+	proplen = sizeof(*prop) + FDT_TAGALIGN(len);
+	return _fdt_splice_struct(fdt, prop, proplen, 0);
+}
+
+int fdt_add_subnode_namelen(void *fdt, int parentoffset,
+			    const char *name, int namelen)
+{
+	struct fdt_node_header *nh;
+	int offset, nextoffset;
+	int nodelen;
+	int err;
+	uint32_t tag;
+	uint32_t *endtag;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	offset = fdt_subnode_offset_namelen(fdt, parentoffset, name, namelen);
+	if (offset >= 0)
+		return -FDT_ERR_EXISTS;
+	else if (offset != -FDT_ERR_NOTFOUND)
+		return offset;
+
+	/* Try to place the new node after the parent's properties */
+	fdt_next_tag(fdt, parentoffset, &nextoffset); /* skip the BEGIN_NODE */
+	do {
+		offset = nextoffset;
+		tag = fdt_next_tag(fdt, offset, &nextoffset);
+	} while ((tag == FDT_PROP) || (tag == FDT_NOP));
+
+	nh = _fdt_offset_ptr_w(fdt, offset);
+	nodelen = sizeof(*nh) + FDT_TAGALIGN(namelen+1) + FDT_TAGSIZE;
+
+	err = _fdt_splice_struct(fdt, nh, 0, nodelen);
+	if (err)
+		return err;
+
+	nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE);
+	memset(nh->name, 0, FDT_TAGALIGN(namelen+1));
+	memcpy(nh->name, name, namelen);
+	endtag = (uint32_t *)((char *)nh + nodelen - FDT_TAGSIZE);
+	*endtag = cpu_to_fdt32(FDT_END_NODE);
+
+	return offset;
+}
+
+int fdt_add_subnode(void *fdt, int parentoffset, const char *name)
+{
+	return fdt_add_subnode_namelen(fdt, parentoffset, name, strlen(name));
+}
+
+int fdt_del_node(void *fdt, int nodeoffset)
+{
+	int endoffset;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	endoffset = _fdt_node_end_offset(fdt, nodeoffset);
+	if (endoffset < 0)
+		return endoffset;
+
+	return _fdt_splice_struct(fdt, _fdt_offset_ptr_w(fdt, nodeoffset),
+				  endoffset - nodeoffset, 0);
+}
+
+static void _fdt_packblocks(const char *old, char *new,
+			    int mem_rsv_size, int struct_size)
+{
+	int mem_rsv_off, struct_off, strings_off;
+
+	mem_rsv_off = FDT_ALIGN(sizeof(struct fdt_header), 8);
+	struct_off = mem_rsv_off + mem_rsv_size;
+	strings_off = struct_off + struct_size;
+
+	memmove(new + mem_rsv_off, old + fdt_off_mem_rsvmap(old), mem_rsv_size);
+	fdt_set_off_mem_rsvmap(new, mem_rsv_off);
+
+	memmove(new + struct_off, old + fdt_off_dt_struct(old), struct_size);
+	fdt_set_off_dt_struct(new, struct_off);
+	fdt_set_size_dt_struct(new, struct_size);
+
+	memmove(new + strings_off, old + fdt_off_dt_strings(old),
+		fdt_size_dt_strings(old));
+	fdt_set_off_dt_strings(new, strings_off);
+	fdt_set_size_dt_strings(new, fdt_size_dt_strings(old));
+}
+
+int fdt_open_into(const void *fdt, void *buf, int bufsize)
+{
+	int err;
+	int mem_rsv_size, struct_size;
+	int newsize;
+	const char *fdtstart = fdt;
+	const char *fdtend = fdtstart + fdt_totalsize(fdt);
+	char *tmp;
+
+	FDT_CHECK_HEADER(fdt);
+
+	mem_rsv_size = (fdt_num_mem_rsv(fdt)+1)
+		* sizeof(struct fdt_reserve_entry);
+
+	if (fdt_version(fdt) >= 17) {
+		struct_size = fdt_size_dt_struct(fdt);
+	} else {
+		struct_size = 0;
+		while (fdt_next_tag(fdt, struct_size, &struct_size) != FDT_END)
+			;
+	}
+
+	if (!_fdt_blocks_misordered(fdt, mem_rsv_size, struct_size)) {
+		/* no further work necessary */
+		err = fdt_move(fdt, buf, bufsize);
+		if (err)
+			return err;
+		fdt_set_version(buf, 17);
+		fdt_set_size_dt_struct(buf, struct_size);
+		fdt_set_totalsize(buf, bufsize);
+		return 0;
+	}
+
+	/* Need to reorder */
+	newsize = FDT_ALIGN(sizeof(struct fdt_header), 8) + mem_rsv_size
+		+ struct_size + fdt_size_dt_strings(fdt);
+
+	if (bufsize < newsize)
+		return -FDT_ERR_NOSPACE;
+
+	/* First attempt to build converted tree at beginning of buffer */
+	tmp = buf;
+	/* But if that overlaps with the old tree... */
+	if (((tmp + newsize) > fdtstart) && (tmp < fdtend)) {
+		/* Try right after the old tree instead */
+		tmp = (char *)(uintptr_t)fdtend;
+		if ((tmp + newsize) > ((char *)buf + bufsize))
+			return -FDT_ERR_NOSPACE;
+	}
+
+	_fdt_packblocks(fdt, tmp, mem_rsv_size, struct_size);
+	memmove(buf, tmp, newsize);
+
+	fdt_set_magic(buf, FDT_MAGIC);
+	fdt_set_totalsize(buf, bufsize);
+	fdt_set_version(buf, 17);
+	fdt_set_last_comp_version(buf, 16);
+	fdt_set_boot_cpuid_phys(buf, fdt_boot_cpuid_phys(fdt));
+
+	return 0;
+}
+
+int fdt_pack(void *fdt)
+{
+	int mem_rsv_size;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	mem_rsv_size = (fdt_num_mem_rsv(fdt)+1)
+		* sizeof(struct fdt_reserve_entry);
+	_fdt_packblocks(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt));
+	fdt_set_totalsize(fdt, _fdt_data_size(fdt));
+
+	return 0;
+}
diff --git a/sys/contrib/octeon-sdk/libfdt/fdt_strerror.c b/sys/contrib/octeon-sdk/libfdt/fdt_strerror.c
new file mode 100644
index 0000000..03cd3cb
--- /dev/null
+++ b/sys/contrib/octeon-sdk/libfdt/fdt_strerror.c
@@ -0,0 +1,96 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#include <fdt.h>
+#include <libfdt.h>
+
+#include "libfdt_internal.h"
+
+struct fdt_errtabent {
+	const char *str;
+};
+
+#define FDT_ERRTABENT(val) \
+	[(val)] = { .str = #val, }
+
+static struct fdt_errtabent fdt_errtable[] = {
+	FDT_ERRTABENT(FDT_ERR_NOTFOUND),
+	FDT_ERRTABENT(FDT_ERR_EXISTS),
+	FDT_ERRTABENT(FDT_ERR_NOSPACE),
+
+	FDT_ERRTABENT(FDT_ERR_BADOFFSET),
+	FDT_ERRTABENT(FDT_ERR_BADPATH),
+	FDT_ERRTABENT(FDT_ERR_BADSTATE),
+
+	FDT_ERRTABENT(FDT_ERR_TRUNCATED),
+	FDT_ERRTABENT(FDT_ERR_BADMAGIC),
+	FDT_ERRTABENT(FDT_ERR_BADVERSION),
+	FDT_ERRTABENT(FDT_ERR_BADSTRUCTURE),
+	FDT_ERRTABENT(FDT_ERR_BADLAYOUT),
+};
+#define FDT_ERRTABSIZE	(sizeof(fdt_errtable) / sizeof(fdt_errtable[0]))
+
+const char *fdt_strerror(int errval)
+{
+	if (errval > 0)
+		return "<valid offset/length>";
+	else if (errval == 0)
+		return "<no error>";
+	else if (errval > (int)-FDT_ERRTABSIZE) {
+		const char *s = fdt_errtable[-errval].str;
+
+		if (s)
+			return s;
+	}
+
+	return "<unknown error>";
+}
diff --git a/sys/contrib/octeon-sdk/libfdt/fdt_sw.c b/sys/contrib/octeon-sdk/libfdt/fdt_sw.c
new file mode 100644
index 0000000..d8e6a05
--- /dev/null
+++ b/sys/contrib/octeon-sdk/libfdt/fdt_sw.c
@@ -0,0 +1,257 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#include <fdt.h>
+#include <libfdt.h>
+
+#include "libfdt_internal.h"
+
+static int _fdt_sw_check_header(void *fdt)
+{
+	if (fdt_magic(fdt) != FDT_SW_MAGIC)
+		return -FDT_ERR_BADMAGIC;
+	/* FIXME: should check more details about the header state */
+	return 0;
+}
+
+#define FDT_SW_CHECK_HEADER(fdt) \
+	{ \
+		int err; \
+		if ((err = _fdt_sw_check_header(fdt)) != 0) \
+			return err; \
+	}
+
+static void *_fdt_grab_space(void *fdt, int len)
+{
+	int offset = fdt_size_dt_struct(fdt);
+	int spaceleft;
+
+	spaceleft = fdt_totalsize(fdt) - fdt_off_dt_struct(fdt)
+		- fdt_size_dt_strings(fdt);
+
+	if ((offset + len < offset) || (offset + len > spaceleft))
+		return NULL;
+
+	fdt_set_size_dt_struct(fdt, offset + len);
+	return fdt_offset_ptr_w(fdt, offset, len);
+}
+
+int fdt_create(void *buf, int bufsize)
+{
+	void *fdt = buf;
+
+	if (bufsize < (int)sizeof(struct fdt_header))
+		return -FDT_ERR_NOSPACE;
+
+	memset(buf, 0, bufsize);
+
+	fdt_set_magic(fdt, FDT_SW_MAGIC);
+	fdt_set_version(fdt, FDT_LAST_SUPPORTED_VERSION);
+	fdt_set_last_comp_version(fdt, FDT_FIRST_SUPPORTED_VERSION);
+	fdt_set_totalsize(fdt,  bufsize);
+
+	fdt_set_off_mem_rsvmap(fdt, FDT_ALIGN(sizeof(struct fdt_header),
+					      sizeof(struct fdt_reserve_entry)));
+	fdt_set_off_dt_struct(fdt, fdt_off_mem_rsvmap(fdt));
+	fdt_set_off_dt_strings(fdt, bufsize);
+
+	return 0;
+}
+
+int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size)
+{
+	struct fdt_reserve_entry *re;
+	int offset;
+
+	FDT_SW_CHECK_HEADER(fdt);
+
+	if (fdt_size_dt_struct(fdt))
+		return -FDT_ERR_BADSTATE;
+
+	offset = fdt_off_dt_struct(fdt);
+	if ((offset + sizeof(*re)) > fdt_totalsize(fdt))
+		return -FDT_ERR_NOSPACE;
+
+	re = (struct fdt_reserve_entry *)((char *)fdt + offset);
+	re->address = cpu_to_fdt64(addr);
+	re->size = cpu_to_fdt64(size);
+
+	fdt_set_off_dt_struct(fdt, offset + sizeof(*re));
+
+	return 0;
+}
+
+int fdt_finish_reservemap(void *fdt)
+{
+	return fdt_add_reservemap_entry(fdt, 0, 0);
+}
+
+int fdt_begin_node(void *fdt, const char *name)
+{
+	struct fdt_node_header *nh;
+	int namelen = strlen(name) + 1;
+
+	FDT_SW_CHECK_HEADER(fdt);
+
+	nh = _fdt_grab_space(fdt, sizeof(*nh) + FDT_TAGALIGN(namelen));
+	if (! nh)
+		return -FDT_ERR_NOSPACE;
+
+	nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE);
+	memcpy(nh->name, name, namelen);
+	return 0;
+}
+
+int fdt_end_node(void *fdt)
+{
+	uint32_t *en;
+
+	FDT_SW_CHECK_HEADER(fdt);
+
+	en = _fdt_grab_space(fdt, FDT_TAGSIZE);
+	if (! en)
+		return -FDT_ERR_NOSPACE;
+
+	*en = cpu_to_fdt32(FDT_END_NODE);
+	return 0;
+}
+
+static int _fdt_find_add_string(void *fdt, const char *s)
+{
+	char *strtab = (char *)fdt + fdt_totalsize(fdt);
+	const char *p;
+	int strtabsize = fdt_size_dt_strings(fdt);
+	int len = strlen(s) + 1;
+	int struct_top, offset;
+
+	p = _fdt_find_string(strtab - strtabsize, strtabsize, s);
+	if (p)
+		return p - strtab;
+
+	/* Add it */
+	offset = -strtabsize - len;
+	struct_top = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt);
+	if ((int)fdt_totalsize(fdt) + offset < struct_top)
+		return 0; /* no more room :( */
+
+	memcpy(strtab + offset, s, len);
+	fdt_set_size_dt_strings(fdt, strtabsize + len);
+	return offset;
+}
+
+int fdt_property(void *fdt, const char *name, const void *val, int len)
+{
+	struct fdt_property *prop;
+	int nameoff;
+
+	FDT_SW_CHECK_HEADER(fdt);
+
+	nameoff = _fdt_find_add_string(fdt, name);
+	if (nameoff == 0)
+		return -FDT_ERR_NOSPACE;
+
+	prop = _fdt_grab_space(fdt, sizeof(*prop) + FDT_TAGALIGN(len));
+	if (! prop)
+		return -FDT_ERR_NOSPACE;
+
+	prop->tag = cpu_to_fdt32(FDT_PROP);
+	prop->nameoff = cpu_to_fdt32(nameoff);
+	prop->len = cpu_to_fdt32(len);
+	memcpy(prop->data, val, len);
+	return 0;
+}
+
+int fdt_finish(void *fdt)
+{
+	char *p = (char *)fdt;
+	uint32_t *end;
+	int oldstroffset, newstroffset;
+	uint32_t tag;
+	int offset, nextoffset;
+
+	FDT_SW_CHECK_HEADER(fdt);
+
+	/* Add terminator */
+	end = _fdt_grab_space(fdt, sizeof(*end));
+	if (! end)
+		return -FDT_ERR_NOSPACE;
+	*end = cpu_to_fdt32(FDT_END);
+
+	/* Relocate the string table */
+	oldstroffset = fdt_totalsize(fdt) - fdt_size_dt_strings(fdt);
+	newstroffset = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt);
+	memmove(p + newstroffset, p + oldstroffset, fdt_size_dt_strings(fdt));
+	fdt_set_off_dt_strings(fdt, newstroffset);
+
+	/* Walk the structure, correcting string offsets */
+	offset = 0;
+	while ((tag = fdt_next_tag(fdt, offset, &nextoffset)) != FDT_END) {
+		if (tag == FDT_PROP) {
+			struct fdt_property *prop =
+				fdt_offset_ptr_w(fdt, offset, sizeof(*prop));
+			int nameoff;
+
+			if (! prop)
+				return -FDT_ERR_BADSTRUCTURE;
+
+			nameoff = fdt32_to_cpu(prop->nameoff);
+			nameoff += fdt_size_dt_strings(fdt);
+			prop->nameoff = cpu_to_fdt32(nameoff);
+		}
+		offset = nextoffset;
+	}
+
+	/* Finally, adjust the header */
+	fdt_set_totalsize(fdt, newstroffset + fdt_size_dt_strings(fdt));
+	fdt_set_magic(fdt, FDT_MAGIC);
+	return 0;
+}
diff --git a/sys/contrib/octeon-sdk/libfdt/fdt_wip.c b/sys/contrib/octeon-sdk/libfdt/fdt_wip.c
new file mode 100644
index 0000000..a4652c6
--- /dev/null
+++ b/sys/contrib/octeon-sdk/libfdt/fdt_wip.c
@@ -0,0 +1,145 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#include <fdt.h>
+#include <libfdt.h>
+
+#include "libfdt_internal.h"
+
+int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
+			const void *val, int len)
+{
+	void *propval;
+	int proplen;
+
+	propval = fdt_getprop_w(fdt, nodeoffset, name, &proplen);
+	if (! propval)
+		return proplen;
+
+	if (proplen != len)
+		return -FDT_ERR_NOSPACE;
+
+	memcpy(propval, val, len);
+	return 0;
+}
+
+static void _fdt_nop_region(void *start, int len)
+{
+	uint32_t *p;
+
+	for (p = start; (char *)p < ((char *)start + len); p++)
+		*p = cpu_to_fdt32(FDT_NOP);
+}
+
+int fdt_nop_property(void *fdt, int nodeoffset, const char *name)
+{
+	struct fdt_property *prop;
+	int len;
+
+	prop = fdt_get_property_w(fdt, nodeoffset, name, &len);
+	if (! prop)
+		return len;
+
+	_fdt_nop_region(prop, len + sizeof(*prop));
+
+	return 0;
+}
+
+int _fdt_node_end_offset(void *fdt, int nodeoffset)
+{
+	int level = 0;
+	uint32_t tag;
+	int offset, nextoffset;
+
+	tag = fdt_next_tag(fdt, nodeoffset, &nextoffset);
+	if (tag != FDT_BEGIN_NODE)
+		return -FDT_ERR_BADOFFSET;
+	do {
+		offset = nextoffset;
+		tag = fdt_next_tag(fdt, offset, &nextoffset);
+
+		switch (tag) {
+		case FDT_END:
+			return offset;
+
+		case FDT_BEGIN_NODE:
+			level++;
+			break;
+
+		case FDT_END_NODE:
+			level--;
+			break;
+
+		case FDT_PROP:
+		case FDT_NOP:
+			break;
+
+		default:
+			return -FDT_ERR_BADSTRUCTURE;
+		}
+	} while (level >= 0);
+
+	return nextoffset;
+}
+
+int fdt_nop_node(void *fdt, int nodeoffset)
+{
+	int endoffset;
+
+	endoffset = _fdt_node_end_offset(fdt, nodeoffset);
+	if (endoffset < 0)
+		return endoffset;
+
+	_fdt_nop_region(fdt_offset_ptr_w(fdt, nodeoffset, 0),
+			endoffset - nodeoffset);
+	return 0;
+}
diff --git a/sys/contrib/octeon-sdk/libfdt/libfdt.h b/sys/contrib/octeon-sdk/libfdt/libfdt.h
new file mode 100644
index 0000000..ce80e4f
--- /dev/null
+++ b/sys/contrib/octeon-sdk/libfdt/libfdt.h
@@ -0,0 +1,1076 @@
+#ifndef _LIBFDT_H
+#define _LIBFDT_H
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <libfdt_env.h>
+#include <fdt.h>
+
+#define FDT_FIRST_SUPPORTED_VERSION	0x10
+#define FDT_LAST_SUPPORTED_VERSION	0x11
+
+/* Error codes: informative error codes */
+#define FDT_ERR_NOTFOUND	1
+	/* FDT_ERR_NOTFOUND: The requested node or property does not exist */
+#define FDT_ERR_EXISTS		2
+	/* FDT_ERR_EXISTS: Attemped to create a node or property which
+	 * already exists */
+#define FDT_ERR_NOSPACE		3
+	/* FDT_ERR_NOSPACE: Operation needed to expand the device
+	 * tree, but its buffer did not have sufficient space to
+	 * contain the expanded tree. Use fdt_open_into() to move the
+	 * device tree to a buffer with more space. */
+
+/* Error codes: codes for bad parameters */
+#define FDT_ERR_BADOFFSET	4
+	/* FDT_ERR_BADOFFSET: Function was passed a structure block
+	 * offset which is out-of-bounds, or which points to an
+	 * unsuitable part of the structure for the operation. */
+#define FDT_ERR_BADPATH		5
+	/* FDT_ERR_BADPATH: Function was passed a badly formatted path
+	 * (e.g. missing a leading / for a function which requires an
+	 * absolute path) */
+#define FDT_ERR_BADPHANDLE	6
+	/* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle
+	 * value.  phandle values of 0 and -1 are not permitted. */
+#define FDT_ERR_BADSTATE	7
+	/* FDT_ERR_BADSTATE: Function was passed an incomplete device
+	 * tree created by the sequential-write functions, which is
+	 * not sufficiently complete for the requested operation. */
+
+/* Error codes: codes for bad device tree blobs */
+#define FDT_ERR_TRUNCATED	8
+	/* FDT_ERR_TRUNCATED: Structure block of the given device tree
+	 * ends without an FDT_END tag. */
+#define FDT_ERR_BADMAGIC	9
+	/* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a
+	 * device tree at all - it is missing the flattened device
+	 * tree magic number. */
+#define FDT_ERR_BADVERSION	10
+	/* FDT_ERR_BADVERSION: Given device tree has a version which
+	 * can't be handled by the requested operation.  For
+	 * read-write functions, this may mean that fdt_open_into() is
+	 * required to convert the tree to the expected version. */
+#define FDT_ERR_BADSTRUCTURE	11
+	/* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt
+	 * structure block or other serious error (e.g. misnested
+	 * nodes, or subnodes preceding properties). */
+#define FDT_ERR_BADLAYOUT	12
+	/* FDT_ERR_BADLAYOUT: For read-write functions, the given
+	 * device tree has it's sub-blocks in an order that the
+	 * function can't handle (memory reserve map, then structure,
+	 * then strings).  Use fdt_open_into() to reorganize the tree
+	 * into a form suitable for the read-write operations. */
+
+/* "Can't happen" error indicating a bug in libfdt */
+#define FDT_ERR_INTERNAL	13
+	/* FDT_ERR_INTERNAL: libfdt has failed an internal assertion.
+	 * Should never be returned, if it is, it indicates a bug in
+	 * libfdt itself. */
+
+#define FDT_ERR_MAX		13
+
+/**********************************************************************/
+/* Low-level functions (you probably don't need these)                */
+/**********************************************************************/
+
+const void *fdt_offset_ptr(const void *fdt, int offset, int checklen);
+static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen)
+{
+	return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen);
+}
+
+uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset);
+
+/**********************************************************************/
+/* Traversal functions                                                */
+/**********************************************************************/
+
+int fdt_next_node(const void *fdt, int offset, int *depth);
+
+/**********************************************************************/
+/* General functions                                                  */
+/**********************************************************************/
+
+#define fdt_get_header(fdt, field) \
+	(fdt32_to_cpu(((const struct fdt_header *)(fdt))->field))
+#define fdt_magic(fdt) 			(fdt_get_header(fdt, magic))
+#define fdt_totalsize(fdt)		(fdt_get_header(fdt, totalsize))
+#define fdt_off_dt_struct(fdt)		(fdt_get_header(fdt, off_dt_struct))
+#define fdt_off_dt_strings(fdt)		(fdt_get_header(fdt, off_dt_strings))
+#define fdt_off_mem_rsvmap(fdt)		(fdt_get_header(fdt, off_mem_rsvmap))
+#define fdt_version(fdt)		(fdt_get_header(fdt, version))
+#define fdt_last_comp_version(fdt) 	(fdt_get_header(fdt, last_comp_version))
+#define fdt_boot_cpuid_phys(fdt) 	(fdt_get_header(fdt, boot_cpuid_phys))
+#define fdt_size_dt_strings(fdt) 	(fdt_get_header(fdt, size_dt_strings))
+#define fdt_size_dt_struct(fdt)		(fdt_get_header(fdt, size_dt_struct))
+
+#define __fdt_set_hdr(name) \
+	static inline void fdt_set_##name(void *fdt, uint32_t val) \
+	{ \
+		struct fdt_header *fdth = fdt; \
+		fdth->name = cpu_to_fdt32(val); \
+	}
+__fdt_set_hdr(magic);
+__fdt_set_hdr(totalsize);
+__fdt_set_hdr(off_dt_struct);
+__fdt_set_hdr(off_dt_strings);
+__fdt_set_hdr(off_mem_rsvmap);
+__fdt_set_hdr(version);
+__fdt_set_hdr(last_comp_version);
+__fdt_set_hdr(boot_cpuid_phys);
+__fdt_set_hdr(size_dt_strings);
+__fdt_set_hdr(size_dt_struct);
+#undef __fdt_set_hdr
+
+/**
+ * fdt_check_header - sanity check a device tree or possible device tree
+ * @fdt: pointer to data which might be a flattened device tree
+ *
+ * fdt_check_header() checks that the given buffer contains what
+ * appears to be a flattened device tree with sane information in its
+ * header.
+ *
+ * returns:
+ *     0, if the buffer appears to contain a valid device tree
+ *     -FDT_ERR_BADMAGIC,
+ *     -FDT_ERR_BADVERSION,
+ *     -FDT_ERR_BADSTATE, standard meanings, as above
+ */
+int fdt_check_header(const void *fdt);
+
+/**
+ * fdt_move - move a device tree around in memory
+ * @fdt: pointer to the device tree to move
+ * @buf: pointer to memory where the device is to be moved
+ * @bufsize: size of the memory space at buf
+ *
+ * fdt_move() relocates, if possible, the device tree blob located at
+ * fdt to the buffer at buf of size bufsize.  The buffer may overlap
+ * with the existing device tree blob at fdt.  Therefore,
+ *     fdt_move(fdt, fdt, fdt_totalsize(fdt))
+ * should always succeed.
+ *
+ * returns:
+ *     0, on success
+ *     -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree
+ *     -FDT_ERR_BADMAGIC,
+ *     -FDT_ERR_BADVERSION,
+ *     -FDT_ERR_BADSTATE, standard meanings
+ */
+int fdt_move(const void *fdt, void *buf, int bufsize);
+
+/**********************************************************************/
+/* Read-only functions                                                */
+/**********************************************************************/
+
+/**
+ * fdt_string - retrieve a string from the strings block of a device tree
+ * @fdt: pointer to the device tree blob
+ * @stroffset: offset of the string within the strings block (native endian)
+ *
+ * fdt_string() retrieves a pointer to a single string from the
+ * strings block of the device tree blob at fdt.
+ *
+ * returns:
+ *     a pointer to the string, on success
+ *     NULL, if stroffset is out of bounds
+ */
+const char *fdt_string(const void *fdt, int stroffset);
+
+/**
+ * fdt_num_mem_rsv - retrieve the number of memory reserve map entries
+ * @fdt: pointer to the device tree blob
+ *
+ * Returns the number of entries in the device tree blob's memory
+ * reservation map.  This does not include the terminating 0,0 entry
+ * or any other (0,0) entries reserved for expansion.
+ *
+ * returns:
+ *     the number of entries
+ */
+int fdt_num_mem_rsv(const void *fdt);
+
+/**
+ * fdt_get_mem_rsv - retrieve one memory reserve map entry
+ * @fdt: pointer to the device tree blob
+ * @address, @size: pointers to 64-bit variables
+ *
+ * On success, *address and *size will contain the address and size of
+ * the n-th reserve map entry from the device tree blob, in
+ * native-endian format.
+ *
+ * returns:
+ *     0, on success
+ *     -FDT_ERR_BADMAGIC,
+ *     -FDT_ERR_BADVERSION,
+ *     -FDT_ERR_BADSTATE, standard meanings
+ */
+int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size);
+
+/**
+ * fdt_subnode_offset_namelen - find a subnode based on substring
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ * @namelen: number of characters of name to consider
+ *
+ * Identical to fdt_subnode_offset(), but only examine the first
+ * namelen characters of name for matching the subnode name.  This is
+ * useful for finding subnodes based on a portion of a larger string,
+ * such as a full path.
+ */
+int fdt_subnode_offset_namelen(const void *fdt, int parentoffset,
+			       const char *name, int namelen);
+/**
+ * fdt_subnode_offset - find a subnode of a given node
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ *
+ * fdt_subnode_offset() finds a subnode of the node at structure block
+ * offset parentoffset with the given name.  name may include a unit
+ * address, in which case fdt_subnode_offset() will find the subnode
+ * with that unit address, or the unit address may be omitted, in
+ * which case fdt_subnode_offset() will find an arbitrary subnode
+ * whose name excluding unit address matches the given name.
+ *
+ * returns:
+ *	structure block offset of the requested subnode (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the requested subnode does not exist
+ *	-FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name);
+
+/**
+ * fdt_path_offset - find a tree node by its full path
+ * @fdt: pointer to the device tree blob
+ * @path: full path of the node to locate
+ *
+ * fdt_path_offset() finds a node of a given path in the device tree.
+ * Each path component may omit the unit address portion, but the
+ * results of this are undefined if any such path component is
+ * ambiguous (that is if there are multiple nodes at the relevant
+ * level matching the given component, differentiated only by unit
+ * address).
+ *
+ * returns:
+ *	structure block offset of the node with the requested path (>=0), on success
+ *	-FDT_ERR_BADPATH, given path does not begin with '/' or is invalid
+ *	-FDT_ERR_NOTFOUND, if the requested node does not exist
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_path_offset(const void *fdt, const char *path);
+
+/**
+ * fdt_get_name - retrieve the name of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of the starting node
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_get_name() retrieves the name (including unit address) of the
+ * device tree node at structure block offset nodeoffset.  If lenp is
+ * non-NULL, the length of this name is also returned, in the integer
+ * pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the node's name, on success
+ *		If lenp is non-NULL, *lenp contains the length of that name (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL *lenp contains an error code (<0):
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE, standard meanings
+ */
+const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp);
+
+/**
+ * fdt_get_property - find a given property in a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to find
+ * @name: name of the property to find
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_get_property() retrieves a pointer to the fdt_property
+ * structure within the device tree blob corresponding to the property
+ * named 'name' of the node at offset nodeoffset.  If lenp is
+ * non-NULL, the length of the property value is also returned, in the
+ * integer pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the structure representing the property
+ *		if lenp is non-NULL, *lenp contains the length of the property
+ *		value (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL, *lenp contains an error code (<0):
+ *		-FDT_ERR_NOTFOUND, node does not have named property
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE,
+ *		-FDT_ERR_BADSTRUCTURE,
+ *		-FDT_ERR_TRUNCATED, standard meanings
+ */
+const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset,
+					    const char *name, int *lenp);
+static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset,
+						      const char *name,
+						      int *lenp)
+{
+	return (struct fdt_property *)(uintptr_t)
+		fdt_get_property(fdt, nodeoffset, name, lenp);
+}
+
+/**
+ * fdt_getprop - retrieve the value of a given property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to find
+ * @name: name of the property to find
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_getprop() retrieves a pointer to the value of the property
+ * named 'name' of the node at offset nodeoffset (this will be a
+ * pointer to within the device blob itself, not a copy of the value).
+ * If lenp is non-NULL, the length of the property value is also
+ * returned, in the integer pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the property's value
+ *		if lenp is non-NULL, *lenp contains the length of the property
+ *		value (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL, *lenp contains an error code (<0):
+ *		-FDT_ERR_NOTFOUND, node does not have named property
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE,
+ *		-FDT_ERR_BADSTRUCTURE,
+ *		-FDT_ERR_TRUNCATED, standard meanings
+ */
+const void *fdt_getprop(const void *fdt, int nodeoffset,
+			const char *name, int *lenp);
+static inline void *fdt_getprop_w(void *fdt, int nodeoffset,
+				  const char *name, int *lenp)
+{
+	return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp);
+}
+
+/**
+ * fdt_get_phandle - retrieve the phandle of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of the node
+ *
+ * fdt_get_phandle() retrieves the phandle of the device tree node at
+ * structure block offset nodeoffset.
+ *
+ * returns:
+ *	the phandle of the node at nodeoffset, on success (!= 0, != -1)
+ *	0, if the node has no phandle, or another error occurs
+ */
+uint32_t fdt_get_phandle(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_get_path - determine the full path of a node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose path to find
+ * @buf: character buffer to contain the returned path (will be overwritten)
+ * @buflen: size of the character buffer at buf
+ *
+ * fdt_get_path() computes the full path of the node at offset
+ * nodeoffset, and records that path in the buffer at buf.
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset.
+ *
+ * returns:
+ *	0, on success
+ *		buf contains the absolute path of the node at
+ *		nodeoffset, as a NUL-terminated string.
+ * 	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1)
+ *		characters and will not fit in the given buffer.
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen);
+
+/**
+ * fdt_supernode_atdepth_offset - find a specific ancestor of a node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose parent to find
+ * @supernodedepth: depth of the ancestor to find
+ * @nodedepth: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_supernode_atdepth_offset() finds an ancestor of the given node
+ * at a specific depth from the root (where the root itself has depth
+ * 0, its immediate subnodes depth 1 and so forth).  So
+ *	fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL);
+ * will always return 0, the offset of the root node.  If the node at
+ * nodeoffset has depth D, then:
+ *	fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL);
+ * will return nodeoffset itself.
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset.
+ *
+ * returns:
+
+ *	structure block offset of the node at node offset's ancestor
+ *		of depth supernodedepth (>=0), on success
+ * 	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+*	-FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of nodeoffset
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
+				 int supernodedepth, int *nodedepth);
+
+/**
+ * fdt_node_depth - find the depth of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose parent to find
+ *
+ * fdt_node_depth() finds the depth of a given node.  The root node
+ * has depth 0, its immediate subnodes depth 1 and so forth.
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset.
+ *
+ * returns:
+ *	depth of the node at nodeoffset (>=0), on success
+ * 	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_depth(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_parent_offset - find the parent of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose parent to find
+ *
+ * fdt_parent_offset() locates the parent node of a given node (that
+ * is, it finds the offset of the node which contains the node at
+ * nodeoffset as a subnode).
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset, *twice*.
+ *
+ * returns:
+ *	structure block offset of the parent of the node at nodeoffset
+ *		(>=0), on success
+ * 	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_parent_offset(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_node_offset_by_prop_value - find nodes with a given property value
+ * @fdt: pointer to the device tree blob
+ * @startoffset: only find nodes after this offset
+ * @propname: property name to check
+ * @propval: property value to search for
+ * @proplen: length of the value in propval
+ *
+ * fdt_node_offset_by_prop_value() returns the offset of the first
+ * node after startoffset, which has a property named propname whose
+ * value is of length proplen and has value equal to propval; or if
+ * startoffset is -1, the very first such node in the tree.
+ *
+ * To iterate through all nodes matching the criterion, the following
+ * idiom can be used:
+ *	offset = fdt_node_offset_by_prop_value(fdt, -1, propname,
+ *					       propval, proplen);
+ *	while (offset != -FDT_ERR_NOTFOUND) {
+ *		// other code here
+ *		offset = fdt_node_offset_by_prop_value(fdt, offset, propname,
+ *						       propval, proplen);
+ *	}
+ *
+ * Note the -1 in the first call to the function, if 0 is used here
+ * instead, the function will never locate the root node, even if it
+ * matches the criterion.
+ *
+ * returns:
+ *	structure block offset of the located node (>= 0, >startoffset),
+ *		 on success
+ *	-FDT_ERR_NOTFOUND, no node matching the criterion exists in the
+ *		tree after startoffset
+ * 	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_offset_by_prop_value(const void *fdt, int startoffset,
+				  const char *propname,
+				  const void *propval, int proplen);
+
+/**
+ * fdt_node_offset_by_phandle - find the node with a given phandle
+ * @fdt: pointer to the device tree blob
+ * @phandle: phandle value
+ *
+ * fdt_node_offset_by_phandle() returns the offset of the node
+ * which has the given phandle value.  If there is more than one node
+ * in the tree with the given phandle (an invalid tree), results are
+ * undefined.
+ *
+ * returns:
+ *	structure block offset of the located node (>= 0), on success
+ *	-FDT_ERR_NOTFOUND, no node with that phandle exists
+ *	-FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1)
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle);
+
+/**
+ * fdt_node_check_compatible: check a node's compatible property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of a tree node
+ * @compatible: string to match against
+ *
+ *
+ * fdt_node_check_compatible() returns 0 if the given node contains a
+ * 'compatible' property with the given string as one of its elements,
+ * it returns non-zero otherwise, or on error.
+ *
+ * returns:
+ *	0, if the node has a 'compatible' property listing the given string
+ *	1, if the node has a 'compatible' property, but it does not list
+ *		the given string
+ *	-FDT_ERR_NOTFOUND, if the given node has no 'compatible' property
+ * 	-FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_check_compatible(const void *fdt, int nodeoffset,
+			      const char *compatible);
+
+/**
+ * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value
+ * @fdt: pointer to the device tree blob
+ * @startoffset: only find nodes after this offset
+ * @compatible: 'compatible' string to match against
+ *
+ * fdt_node_offset_by_compatible() returns the offset of the first
+ * node after startoffset, which has a 'compatible' property which
+ * lists the given compatible string; or if startoffset is -1, the
+ * very first such node in the tree.
+ *
+ * To iterate through all nodes matching the criterion, the following
+ * idiom can be used:
+ *	offset = fdt_node_offset_by_compatible(fdt, -1, compatible);
+ *	while (offset != -FDT_ERR_NOTFOUND) {
+ *		// other code here
+ *		offset = fdt_node_offset_by_compatible(fdt, offset, compatible);
+ *	}
+ *
+ * Note the -1 in the first call to the function, if 0 is used here
+ * instead, the function will never locate the root node, even if it
+ * matches the criterion.
+ *
+ * returns:
+ *	structure block offset of the located node (>= 0, >startoffset),
+ *		 on success
+ *	-FDT_ERR_NOTFOUND, no node matching the criterion exists in the
+ *		tree after startoffset
+ * 	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
+				  const char *compatible);
+
+/**********************************************************************/
+/* Write-in-place functions                                           */
+/**********************************************************************/
+
+/**
+ * fdt_setprop_inplace - change a property's value, but not its size
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: pointer to data to replace the property value with
+ * @len: length of the property value
+ *
+ * fdt_setprop_inplace() replaces the value of a given property with
+ * the data in val, of length len.  This function cannot change the
+ * size of a property, and so will only work if len is equal to the
+ * current length of the property.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the given property value, and will not alter or move any other part
+ * of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, if len is not equal to the property's current length
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
+			const void *val, int len);
+
+/**
+ * fdt_setprop_inplace_cell - change the value of a single-cell property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: cell (32-bit integer) value to replace the property with
+ *
+ * fdt_setprop_inplace_cell() replaces the value of a given property
+ * with the 32-bit integer cell value in val, converting val to
+ * big-endian if necessary.  This function cannot change the size of a
+ * property, and so will only work if the property already exists and
+ * has length 4.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the given property value, and will not alter or move any other part
+ * of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, if the property's length is not equal to 4
+  *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset,
+					   const char *name, uint32_t val)
+{
+	val = cpu_to_fdt32(val);
+	return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val));
+}
+
+/**
+ * fdt_nop_property - replace a property with nop tags
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to nop
+ * @name: name of the property to nop
+ *
+ * fdt_nop_property() will replace a given property's representation
+ * in the blob with FDT_NOP tags, effectively removing it from the
+ * tree.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the property, and will not alter or move any other part of the
+ * tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_nop_property(void *fdt, int nodeoffset, const char *name);
+
+/**
+ * fdt_nop_node - replace a node (subtree) with nop tags
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node to nop
+ *
+ * fdt_nop_node() will replace a given node's representation in the
+ * blob, including all its subnodes, if any, with FDT_NOP tags,
+ * effectively removing it from the tree.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the node and its properties and subnodes, and will not alter or
+ * move any other part of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_nop_node(void *fdt, int nodeoffset);
+
+/**********************************************************************/
+/* Sequential write functions                                         */
+/**********************************************************************/
+
+int fdt_create(void *buf, int bufsize);
+int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size);
+int fdt_finish_reservemap(void *fdt);
+int fdt_begin_node(void *fdt, const char *name);
+int fdt_property(void *fdt, const char *name, const void *val, int len);
+static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val)
+{
+	val = cpu_to_fdt32(val);
+	return fdt_property(fdt, name, &val, sizeof(val));
+}
+#define fdt_property_string(fdt, name, str) \
+	fdt_property(fdt, name, str, strlen(str)+1)
+int fdt_end_node(void *fdt);
+int fdt_finish(void *fdt);
+
+/**********************************************************************/
+/* Read-write functions                                               */
+/**********************************************************************/
+
+int fdt_open_into(const void *fdt, void *buf, int bufsize);
+int fdt_pack(void *fdt);
+
+/**
+ * fdt_add_mem_rsv - add one memory reserve map entry
+ * @fdt: pointer to the device tree blob
+ * @address, @size: 64-bit values (native endian)
+ *
+ * Adds a reserve map entry to the given blob reserving a region at
+ * address address of length size.
+ *
+ * This function will insert data into the reserve map and will
+ * therefore change the indexes of some entries in the table.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new reservation entry
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size);
+
+/**
+ * fdt_del_mem_rsv - remove a memory reserve map entry
+ * @fdt: pointer to the device tree blob
+ * @n: entry to remove
+ *
+ * fdt_del_mem_rsv() removes the n-th memory reserve map entry from
+ * the blob.
+ *
+ * This function will delete data from the reservation table and will
+ * therefore change the indexes of some entries in the table.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there
+ *		are less than n+1 reserve map entries)
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_del_mem_rsv(void *fdt, int n);
+
+/**
+ * fdt_set_name - change the name of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of a node
+ * @name: name to give the node
+ *
+ * fdt_set_name() replaces the name (including unit address, if any)
+ * of the given node with the given string.  NOTE: this function can't
+ * efficiently check if the new name is unique amongst the given
+ * node's siblings; results are undefined if this function is invoked
+ * with a name equal to one of the given node's siblings.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob
+ *		to contain the new name
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE, standard meanings
+ */
+int fdt_set_name(void *fdt, int nodeoffset, const char *name);
+
+/**
+ * fdt_setprop - create or change a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: pointer to data to set the property value to
+ * @len: length of the property value
+ *
+ * fdt_setprop() sets the value of the named property in the given
+ * node to the given value and length, creating the property if it
+ * does not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_setprop(void *fdt, int nodeoffset, const char *name,
+		const void *val, int len);
+
+/**
+ * fdt_setprop_cell - set a property to a single cell value
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: 32-bit integer value for the property (native endian)
+ *
+ * fdt_setprop_cell() sets the value of the named property in the
+ * given node to the given cell value (converting to big-endian if
+ * necessary), or creates a new property with that value if it does
+ * not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name,
+				   uint32_t val)
+{
+	val = cpu_to_fdt32(val);
+	return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val));
+}
+
+/**
+ * fdt_setprop_string - set a property to a string value
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @str: string value for the property
+ *
+ * fdt_setprop_string() sets the value of the named property in the
+ * given node to the given string value (using the length of the
+ * string to determine the new length of the property), or creates a
+ * new property with that value if it does not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+#define fdt_setprop_string(fdt, nodeoffset, name, str) \
+	fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
+
+/**
+ * fdt_delprop - delete a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to nop
+ * @name: name of the property to nop
+ *
+ * fdt_del_property() will delete the given property.
+ *
+ * This function will delete data from the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_delprop(void *fdt, int nodeoffset, const char *name);
+
+/**
+ * fdt_add_subnode_namelen - creates a new node based on substring
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ * @namelen: number of characters of name to consider
+ *
+ * Identical to fdt_add_subnode(), but use only the first namelen
+ * characters of name as the name of the new node.  This is useful for
+ * creating subnodes based on a portion of a larger string, such as a
+ * full path.
+ */
+int fdt_add_subnode_namelen(void *fdt, int parentoffset,
+			    const char *name, int namelen);
+
+/**
+ * fdt_add_subnode - creates a new node
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ *
+ * fdt_add_subnode() creates a new node as a subnode of the node at
+ * structure block offset parentoffset, with the given name (which
+ * should include the unit address, if any).
+ *
+ * This function will insert data into the blob, and will therefore
+ * change the offsets of some existing nodes.
+
+ * returns:
+ *	structure block offset of the created nodeequested subnode (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the requested subnode does not exist
+ *	-FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag
+ *	-FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of
+ *		the given name
+ *	-FDT_ERR_NOSPACE, if there is insufficient free space in the
+ *		blob to contain the new node
+ *	-FDT_ERR_NOSPACE
+ *	-FDT_ERR_BADLAYOUT
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_add_subnode(void *fdt, int parentoffset, const char *name);
+
+/**
+ * fdt_del_node - delete a node (subtree)
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node to nop
+ *
+ * fdt_del_node() will remove the given node, including all its
+ * subnodes if any, from the blob.
+ *
+ * This function will delete data from the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_del_node(void *fdt, int nodeoffset);
+
+/**********************************************************************/
+/* Debugging / informational functions                                */
+/**********************************************************************/
+
+const char *fdt_strerror(int errval);
+
+#endif /* _LIBFDT_H */
diff --git a/sys/contrib/octeon-sdk/libfdt/libfdt.mk b/sys/contrib/octeon-sdk/libfdt/libfdt.mk
new file mode 100644
index 0000000..742c94a
--- /dev/null
+++ b/sys/contrib/octeon-sdk/libfdt/libfdt.mk
@@ -0,0 +1,88 @@
+#/***********************license start***************
+# Copyright (c) 2003-2007 Cavium Inc. (support@cavium.com). All rights
+# reserved.
+#
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+#
+#     * Neither the name of Cavium Inc. nor the names of
+#       its contributors may be used to endorse or promote products
+#       derived from this software without specific prior written
+#       permission.
+#
+# TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+# AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+# OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+# RESPECT TO THE SOFTWARE, aplINCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+# REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+# DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+# OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+# PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+# POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+# OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+#
+#
+# For any questions regarding licensing please contact marketing@cavium.com
+#
+# ***********************license end**************************************/
+
+#
+#  component Makefile fragment
+#
+
+#  standard component Makefile header
+sp              :=  $(sp).x
+dirstack_$(sp)  :=  $(d)
+d               :=  $(dir)
+
+#  component specification
+
+LIBRARY := $(OBJ_DIR)/libfdt.a
+
+OBJS_$(d)  :=  \
+	$(OBJ_DIR)/fdt.o \
+	$(OBJ_DIR)/fdt_ro.o \
+	$(OBJ_DIR)/fdt_rw.o \
+	$(OBJ_DIR)/fdt_strerror.o \
+	$(OBJ_DIR)/fdt_sw.o \
+	$(OBJ_DIR)/fdt_wip.o
+
+
+$(OBJS_$(d)):  CFLAGS_LOCAL := -I$(d) -I$(d)/libfdt -O2 -g -W -Wall -Wno-unused-parameter -Wundef -G0
+
+#  standard component Makefile rules
+
+DEPS_$(d)   :=  $(OBJS_$(d):.o=.d)
+
+LIBS_LIST   :=  $(LIBS_LIST) $(LIBRARY)
+
+CLEAN_LIST  :=  $(CLEAN_LIST) $(OBJS_$(d)) $(DEPS_$(d)) $(LIBRARY)
+
+-include $(DEPS_$(d))
+
+$(LIBRARY): $(OBJS_$(d))
+	$(AR) -cr $@ $^
+
+$(OBJ_DIR)/%.o:	$(d)/%.c
+	$(COMPILE)
+
+$(OBJ_DIR)/%.o:	$(d)/libftd/%.c
+	$(COMPILE)
+
+$(OBJ_DIR)/%.o:	$(d)/%.S
+	$(ASSEMBLE)
+
+#  standard component Makefile footer
+
+d   :=  $(dirstack_$(sp))
+sp  :=  $(basename $(sp))
diff --git a/sys/contrib/octeon-sdk/libfdt/libfdt_env.h b/sys/contrib/octeon-sdk/libfdt/libfdt_env.h
new file mode 100644
index 0000000..449bf60
--- /dev/null
+++ b/sys/contrib/octeon-sdk/libfdt/libfdt_env.h
@@ -0,0 +1,23 @@
+#ifndef _LIBFDT_ENV_H
+#define _LIBFDT_ENV_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
+
+#define _B(n)	((unsigned long long)((uint8_t *)&x)[n])
+static inline uint32_t fdt32_to_cpu(uint32_t x)
+{
+	return (_B(0) << 24) | (_B(1) << 16) | (_B(2) << 8) | _B(3);
+}
+#define cpu_to_fdt32(x) fdt32_to_cpu(x)
+
+static inline uint64_t fdt64_to_cpu(uint64_t x)
+{
+	return (_B(0) << 56) | (_B(1) << 48) | (_B(2) << 40) | (_B(3) << 32)
+		| (_B(4) << 24) | (_B(5) << 16) | (_B(6) << 8) | _B(7);
+}
+#define cpu_to_fdt64(x) fdt64_to_cpu(x)
+#undef _B
+
+#endif /* _LIBFDT_ENV_H */
diff --git a/sys/contrib/octeon-sdk/libfdt/libfdt_internal.h b/sys/contrib/octeon-sdk/libfdt/libfdt_internal.h
new file mode 100644
index 0000000..46eb93e
--- /dev/null
+++ b/sys/contrib/octeon-sdk/libfdt/libfdt_internal.h
@@ -0,0 +1,95 @@
+#ifndef _LIBFDT_INTERNAL_H
+#define _LIBFDT_INTERNAL_H
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <fdt.h>
+
+#define FDT_ALIGN(x, a)		(((x) + (a) - 1) & ~((a) - 1))
+#define FDT_TAGALIGN(x)		(FDT_ALIGN((x), FDT_TAGSIZE))
+
+#define FDT_CHECK_HEADER(fdt) \
+	{ \
+		int err; \
+		if ((err = fdt_check_header(fdt)) != 0) \
+			return err; \
+	}
+
+uint32_t _fdt_next_tag(const void *fdt, int startoffset, int *nextoffset);
+int _fdt_check_node_offset(const void *fdt, int offset);
+const char *_fdt_find_string(const char *strtab, int tabsize, const char *s);
+int _fdt_node_end_offset(void *fdt, int nodeoffset);
+
+static inline const void *_fdt_offset_ptr(const void *fdt, int offset)
+{
+	return (const char *)fdt + fdt_off_dt_struct(fdt) + offset;
+}
+
+static inline void *_fdt_offset_ptr_w(void *fdt, int offset)
+{
+	return (void *)(uintptr_t)_fdt_offset_ptr(fdt, offset);
+}
+
+static inline const struct fdt_reserve_entry *_fdt_mem_rsv(const void *fdt, int n)
+{
+	const struct fdt_reserve_entry *rsv_table =
+		(const struct fdt_reserve_entry *)
+		((const char *)fdt + fdt_off_mem_rsvmap(fdt));
+
+	return rsv_table + n;
+}
+static inline struct fdt_reserve_entry *_fdt_mem_rsv_w(void *fdt, int n)
+{
+	return (void *)(uintptr_t)_fdt_mem_rsv(fdt, n);
+}
+
+#define FDT_SW_MAGIC		(~FDT_MAGIC)
+
+#endif /* _LIBFDT_INTERNAL_H */
diff --git a/sys/contrib/octeon-sdk/octeon-boot-info.h b/sys/contrib/octeon-sdk/octeon-boot-info.h
index 0866822..6a3e927 100644
--- a/sys/contrib/octeon-sdk/octeon-boot-info.h
+++ b/sys/contrib/octeon-sdk/octeon-boot-info.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2011  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -52,6 +52,9 @@
 
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <linux/types.h>
+#include <asm/octeon/cvmx-asm.h>
+#else
+#include "cvmx-asm.h"
 #endif
 
 #ifndef __ASSEMBLY__
@@ -89,6 +92,79 @@ typedef struct
     uint32_t pad;
 } boot_init_vector_t;
 
+#if defined(__ASM_GBL_DATA_H)  /* defined above */
+/*
+ * Definition of a data structure to mimic the old u-boot gd_t data structure.
+ */
+#undef GD_TMP_STR_SIZE
+#define GD_TMP_STR_SIZE 32
+
+#define LINUX_APP_GLOBAL_DATA_MAGIC	0x221eb111476f410full
+#define LINUX_APP_GLOBAL_DATA_VERSION	2
+
+struct linux_app_global_data {
+    bd_t		*bd;
+    unsigned long	flags;
+    unsigned long	baudrate;
+    unsigned long	have_console;	/* serial_init() was called */
+    uint64_t		ram_size;	/* RAM size */
+    uint64_t		reloc_off;	/* Relocation Offset */
+    unsigned long	env_addr;	/* Address  of Environment struct */
+    unsigned long	env_valid;	/* Checksum of Environment valid? */
+    unsigned long	cpu_clock_mhz;	/* CPU clock speed in MHz */
+    unsigned long	ddr_clock_mhz;	/* DDR clock (not data rate!) in MHz */
+    unsigned long	ddr_ref_hertz;	/* DDR Ref clock Hertz */
+    int			mcu_rev_maj;
+    int			mcu_rev_min;
+    int			console_uart;
+
+    /* EEPROM data structures as read from EEPROM or populated by other
+     * means on boards without an EEPROM
+     */
+    octeon_eeprom_board_desc_t	board_desc;
+    octeon_eeprom_clock_desc_t	clock_desc;
+    octeon_eeprom_mac_addr_t	mac_desc;
+
+    void		**jt;		/* jump table, not used */
+    char		*err_msg;	/* pointer to error message to save
+					 * until console is up.  Not used.
+					 */
+    union {
+        struct {	/* Keep under 32 bytes! */
+            uint64_t	magic;
+	    uint32_t	version;
+	    uint32_t	fdt_addr;
+        };
+        char		tmp_str[GD_TMP_STR_SIZE];
+    };
+    unsigned long	uboot_flash_address;	/* Address of normal bootloader
+						 * in flash
+						 */
+    unsigned long	uboot_flash_size;	/* Size of normal bootloader */
+    uint64_t		dfm_ram_size;	/* DFM RAM size */
+};
+typedef struct linux_app_global_data linux_app_global_data_t;
+
+/* Flags for linux_app_global_data */
+#define LA_GD_FLG_RELOC			0x0001	/* Code was relocated to RAM	 */
+#define LA_GD_FLG_DEVINIT		0x0002	/* Devices have been initialized */
+#define LA_GD_FLG_SILENT		0x0004	/* Silent mode			 */
+#define LA_GD_FLG_CLOCK_DESC_MISSING	0x0008
+#define LA_GD_FLG_BOARD_DESC_MISSING	0x0010
+#define LA_GD_FLG_DDR_VERBOSE		0x0020
+#define LA_GD_FLG_DDR0_CLK_INITIALIZED	0x0040
+#define LA_GD_FLG_DDR1_CLK_INITIALIZED	0x0080
+#define LA_GD_FLG_DDR2_CLK_INITIALIZED	0x0100
+#define LA_GD_FLG_DDR3_CLK_INITIALIZED  0x0200
+#define LA_GD_FLG_FAILSAFE_MODE		0x0400	/* Use failsafe mode */
+#define LA_GD_FLG_DDR_TRACE_INIT	0x0800
+#define LA_GD_FLG_DFM_CLK_INITIALIZED	0x1000
+#define LA_GD_FLG_DFM_VERBOSE		0x2000
+#define LA_GD_FLG_DFM_TRACE_INIT	0x4000
+#define LA_GD_FLG_MEMORY_PRESERVED	0x8000
+#define LA_GD_FLG_RAM_RESIDENT		0x10000	/* RAM boot detected */
+#endif /* __ASM_GBL_DATA_H */
+
 /*
  * Definition of a data structure setup by the bootloader to enable Linux to
  * launch SE apps on idle cores.
@@ -108,10 +184,8 @@ struct linux_app_boot_info
     uint32_t compact_flash_common_base_addr;
     uint32_t compact_flash_attribute_base_addr;
     uint32_t led_display_base_addr;
-#ifndef __OCTEON_NEWLIB__
-#if defined(__U_BOOT__) || !defined(__KERNEL__)
-    gd_t gd;
-#endif
+#if defined(__ASM_GBL_DATA_H)  /* defined above */
+    linux_app_global_data_t gd;
 #endif
 };
 typedef struct linux_app_boot_info linux_app_boot_info_t;
@@ -130,11 +204,10 @@ typedef struct linux_app_boot_info linux_app_boot_info_t;
 #define LABI_SIGNATURE 0xAABBCC01
 
 /*  from uboot-headers/octeon_mem_map.h */
-#if defined(CVMX_BUILD_FOR_LINUX_KERNEL) || defined(__OCTEON_NEWLIB__)
+#if defined(CVMX_BUILD_FOR_LINUX_KERNEL) || defined(CVMX_BUILD_FOR_TOOLCHAIN)
 #define EXCEPTION_BASE_INCR     (4 * 1024)
 #endif
 
-#define OCTEON_NUM_CORES    16
 /* Increment size for exception base addresses (4k minimum) */
 #define EXCEPTION_BASE_BASE     0
 #define BOOTLOADER_PRIV_DATA_BASE        (EXCEPTION_BASE_BASE + 0x800)
@@ -142,11 +215,11 @@ typedef struct linux_app_boot_info linux_app_boot_info_t;
 #define BOOTLOADER_DEBUG_TRAMPOLINE      (BOOTLOADER_BOOT_VECTOR + BOOT_VECTOR_SIZE)   /* WORD */
 #define BOOTLOADER_DEBUG_TRAMPOLINE_CORE (BOOTLOADER_DEBUG_TRAMPOLINE + 4)   /* WORD */
 
-#define OCTEON_EXCEPTION_VECTOR_BLOCK_SIZE  (OCTEON_NUM_CORES*EXCEPTION_BASE_INCR) /* 16 4k blocks */
+#define OCTEON_EXCEPTION_VECTOR_BLOCK_SIZE  (CVMX_MAX_CORES*EXCEPTION_BASE_INCR) /* 32 4k blocks */
 #define BOOTLOADER_DEBUG_REG_SAVE_BASE  (EXCEPTION_BASE_BASE + OCTEON_EXCEPTION_VECTOR_BLOCK_SIZE)
 
 #define BOOT_VECTOR_NUM_WORDS           (8)
-#define BOOT_VECTOR_SIZE                ((OCTEON_NUM_CORES*4)*BOOT_VECTOR_NUM_WORDS)
+#define BOOT_VECTOR_SIZE                ((CVMX_MAX_CORES*4)*BOOT_VECTOR_NUM_WORDS)
 
 
 #endif /* __OCTEON_BOOT_INFO_H__ */
diff --git a/sys/contrib/octeon-sdk/octeon-feature.c b/sys/contrib/octeon-sdk/octeon-feature.c
new file mode 100644
index 0000000..64bc084
--- /dev/null
+++ b/sys/contrib/octeon-sdk/octeon-feature.c
@@ -0,0 +1,146 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * File defining checks for different Octeon features.
+ *
+ * <hr>$Revision: 1 $<hr>
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/init.h>
+
+#include <asm/octeon/octeon.h>
+#else
+#include "cvmx.h"
+#endif
+
+CVMX_SHARED uint8_t octeon_feature_map[FEATURE_MAP_SIZE] __attribute__((aligned(128)));
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(octeon_feature_map);
+#else
+#define __init
+#endif
+
+/*
+ * Set the bit in octeon_feature_map for feature.
+ *
+ * @param feature
+ * @return 0 for success and nonzero for error.
+ */
+static int __init octeon_feature_set(octeon_feature_t feature)
+{
+    int bit, byte;
+
+    byte = feature >> 3;
+    bit = feature & 0x7;
+    octeon_feature_map[byte] |= (((uint8_t)1) << bit);
+
+    return 0;
+}
+
+void __init octeon_feature_init(void)
+{
+    octeon_feature_result_t val;
+
+    /*
+     * Check feature map size
+     */
+    if (OCTEON_MAX_FEATURE > (FEATURE_MAP_SIZE * 8 - 1))
+    {
+        val = OCTEON_FEATURE_MAP_OVERFLOW;
+        goto feature_check;
+    }
+
+    /*
+     * Feature settings
+     */
+#define OCTEON_FEATURE_SET(feature_x)		\
+	if (old_octeon_has_feature(feature_x))	\
+	    octeon_feature_set(feature_x)
+
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_SAAD);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_ZIP);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_CRYPTO);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_DORM_CRYPTO);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_PCIE);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_SRIO);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_ILK);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_KEY_MEMORY);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_LED_CONTROLLER);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_TRA);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_MGMT_PORT);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_RAID);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_USB);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_NO_WPTR);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_DFA);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_MDIO_CLAUSE_45);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_NPEI);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_PKND);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_CN68XX_WQE);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_HFA);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_DFM);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_CIU2);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_DICI_MODE);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_BIT_EXTRACTOR);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_NAND);
+    OCTEON_FEATURE_SET(OCTEON_FEATURE_MMC);
+
+    val = OCTEON_FEATURE_SUCCESS;
+
+feature_check:
+
+    if (val != OCTEON_FEATURE_SUCCESS)
+    {
+	cvmx_dprintf("octeon_feature_init(): ");
+	switch (val)
+	{
+	case OCTEON_FEATURE_MAP_OVERFLOW:
+	    cvmx_dprintf("feature map overflow.\n");
+	    break;
+	default:
+	    cvmx_dprintf("unknown error %d.\n", val);
+	    break;
+	}
+#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && !defined(__U_BOOT__) && !defined(CVMX_BUILD_FOR_TOOLCHAIN)
+	exit (1);
+#endif
+    }
+}
diff --git a/sys/contrib/octeon-sdk/octeon-feature.h b/sys/contrib/octeon-sdk/octeon-feature.h
index a53b9f6..7571c33 100644
--- a/sys/contrib/octeon-sdk/octeon-feature.h
+++ b/sys/contrib/octeon-sdk/octeon-feature.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -57,14 +57,40 @@
 extern "C" {
 #endif
 
+/*
+ * Errors
+ */
+typedef enum
+{
+   OCTEON_FEATURE_SUCCESS                = 0,
+   OCTEON_FEATURE_MAP_OVERFLOW           = -1,
+} octeon_feature_result_t;
+
+/*
+ * Octeon models are declared after the macros in octeon-model.h with the
+ * suffix _FEATURE. The individual features are declared with the
+ * _FEATURE_ infix.
+ */
 typedef enum
 {
+    /*
+     * Checks on the critical path are moved to the top (8 positions)
+     * so that the compiler generates one less insn than for the rest
+     * of the checks.
+     */
+    OCTEON_FEATURE_PKND,        /**<  CN68XX uses port kinds for packet interface */
+    OCTEON_FEATURE_CN68XX_WQE,  /**<  CN68XX has different fields in word0 - word2 */
+
+    /*
+     * Features
+     */
     OCTEON_FEATURE_SAAD,        /**<  Octeon models in the CN5XXX family and higher support atomic add instructions to memory (saa/saad) */
     OCTEON_FEATURE_ZIP,         /**<  Does this Octeon support the ZIP offload engine? */
     OCTEON_FEATURE_CRYPTO,      /**<  Does this Octeon support crypto acceleration using COP2? */
     OCTEON_FEATURE_DORM_CRYPTO, /**<  Can crypto be enabled by calling cvmx_crypto_dormant_enable()? */
     OCTEON_FEATURE_PCIE,        /**<  Does this Octeon support PCI express? */
-    OCTEON_FEATURE_SRIO,	/**<  Does this Octeon support SRIOs */
+    OCTEON_FEATURE_SRIO,        /**<  Does this Octeon support SRIO */
+    OCTEON_FEATURE_ILK,         /**<  Does this Octeon support Interlaken */
     OCTEON_FEATURE_KEY_MEMORY,  /**<  Some Octeon models support internal memory for storing cryptographic keys */
     OCTEON_FEATURE_LED_CONTROLLER, /**<  Octeon has a LED controller for banks of external LEDs */
     OCTEON_FEATURE_TRA,         /**<  Octeon has a trace buffer */
@@ -75,6 +101,14 @@ typedef enum
     OCTEON_FEATURE_DFA,         /**<  Octeon has DFA state machines */
     OCTEON_FEATURE_MDIO_CLAUSE_45,     /**<  Octeon MDIO block supports clause 45 transactions for 10 Gig support */
     OCTEON_FEATURE_NPEI,        /**<  CN52XX and CN56XX used a block named NPEI for PCIe access. Newer chips replaced this with SLI+DPI */
+    OCTEON_FEATURE_HFA,         /**<  Octeon has DFA/HFA */
+    OCTEON_FEATURE_DFM,         /**<  Octeon has DFM */
+    OCTEON_FEATURE_CIU2,        /**<  Octeon has CIU2 */
+    OCTEON_FEATURE_DICI_MODE,   /**<  Octeon has DMA Instruction Completion Interrupt mode */
+    OCTEON_FEATURE_BIT_EXTRACTOR,    /**<  Octeon has Bit Select Extractor schedulor */
+    OCTEON_FEATURE_NAND,        /**<  Octeon has NAND */
+    OCTEON_FEATURE_MMC,         /**<  Octeon has built-in MMC support */
+    OCTEON_MAX_FEATURE
 } octeon_feature_t;
 
 /**
@@ -87,8 +121,11 @@ typedef enum
  *
  * @return Non zero if the feature exists. Zero if the feature does not
  *         exist.
+ *
+ * Note: This was octeon_has_feature before the feature map and is
+ * called only after model-checking is set up in octeon_feature_init().
  */
-static inline int octeon_has_feature(octeon_feature_t feature)
+static inline int old_octeon_has_feature(octeon_feature_t feature)
 {
     switch (feature)
     {
@@ -102,7 +139,7 @@ static inline int octeon_has_feature(octeon_feature_t feature)
                 return !cvmx_fuse_read(121);
 
         case OCTEON_FEATURE_CRYPTO:
-	    if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+	    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) {
                 cvmx_mio_fus_dat2_t fus_2;
                 fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
                 if (fus_2.s.nocrypto || fus_2.s.nomul) {
@@ -119,7 +156,7 @@ static inline int octeon_has_feature(octeon_feature_t feature)
             }
 
         case OCTEON_FEATURE_DORM_CRYPTO:
-            if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+            if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) {
                 cvmx_mio_fus_dat2_t fus_2;
                 fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
                 return !fus_2.s.nocrypto && !fus_2.s.nomul && fus_2.s.dorm_crypto;
@@ -128,13 +165,23 @@ static inline int octeon_has_feature(octeon_feature_t feature)
             }
 
         case OCTEON_FEATURE_PCIE:
-            return (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN6XXX));
+            return (OCTEON_IS_MODEL(OCTEON_CN56XX)
+                    || OCTEON_IS_MODEL(OCTEON_CN52XX)
+                    || OCTEON_IS_MODEL(OCTEON_CN6XXX)
+                    || OCTEON_IS_MODEL(OCTEON_CNF7XXX));
 
 	case OCTEON_FEATURE_SRIO:
-	    return (OCTEON_IS_MODEL(OCTEON_CN6XXX));
+	    return (OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX));
+
+	case OCTEON_FEATURE_ILK:
+	    return (OCTEON_IS_MODEL(OCTEON_CN68XX));
 
         case OCTEON_FEATURE_KEY_MEMORY:
-            return OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+            return (OCTEON_IS_MODEL(OCTEON_CN38XX)
+                    || OCTEON_IS_MODEL(OCTEON_CN58XX)
+                    || OCTEON_IS_MODEL(OCTEON_CN56XX)
+                    || OCTEON_IS_MODEL(OCTEON_CN6XXX)
+                    || OCTEON_IS_MODEL(OCTEON_CNF7XXX));
 
         case OCTEON_FEATURE_LED_CONTROLLER:
             return OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX);
@@ -142,7 +189,9 @@ static inline int octeon_has_feature(octeon_feature_t feature)
         case OCTEON_FEATURE_TRA:
             return !(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX));
         case OCTEON_FEATURE_MGMT_PORT:
-            return OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+            return (OCTEON_IS_MODEL(OCTEON_CN56XX)
+                    || OCTEON_IS_MODEL(OCTEON_CN52XX)
+                    || OCTEON_IS_MODEL(OCTEON_CN6XXX));
 
         case OCTEON_FEATURE_RAID:
             return OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN6XXX);
@@ -151,8 +200,12 @@ static inline int octeon_has_feature(octeon_feature_t feature)
             return !(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX));
 
         case OCTEON_FEATURE_NO_WPTR:
-            return (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN6XXX)) &&
-                    !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
+            return ((OCTEON_IS_MODEL(OCTEON_CN56XX)
+                     || OCTEON_IS_MODEL(OCTEON_CN52XX)
+                     || OCTEON_IS_MODEL(OCTEON_CN6XXX)
+                     || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
+                    && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
+                    && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X));
 
         case OCTEON_FEATURE_DFA:
             if (!OCTEON_IS_MODEL(OCTEON_CN38XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX) && !OCTEON_IS_MODEL(OCTEON_CN58XX))
@@ -162,15 +215,101 @@ static inline int octeon_has_feature(octeon_feature_t feature)
             else
                 return !cvmx_fuse_read(120);
 
+        case OCTEON_FEATURE_HFA:
+            if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
+                return 0;
+            else
+                return !cvmx_fuse_read(90);
+
+        case OCTEON_FEATURE_DFM:
+            if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)))
+                return 0;
+            else
+                return !cvmx_fuse_read(90);
+
         case OCTEON_FEATURE_MDIO_CLAUSE_45:
             return !(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX));
 
         case OCTEON_FEATURE_NPEI:
             return (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX));
+
+        case OCTEON_FEATURE_PKND:
+            return (OCTEON_IS_MODEL(OCTEON_CN68XX));
+
+        case OCTEON_FEATURE_CN68XX_WQE:
+            return (OCTEON_IS_MODEL(OCTEON_CN68XX));
+
+        case OCTEON_FEATURE_CIU2:
+            return (OCTEON_IS_MODEL(OCTEON_CN68XX));
+
+        case OCTEON_FEATURE_NAND:
+            return (OCTEON_IS_MODEL(OCTEON_CN52XX)
+                    || OCTEON_IS_MODEL(OCTEON_CN63XX)
+                    || OCTEON_IS_MODEL(OCTEON_CN66XX)
+                    || OCTEON_IS_MODEL(OCTEON_CN68XX));
+
+        case OCTEON_FEATURE_DICI_MODE:
+            return (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X)
+                    || OCTEON_IS_MODEL(OCTEON_CN61XX)
+                    || OCTEON_IS_MODEL(OCTEON_CNF71XX));
+
+        case OCTEON_FEATURE_BIT_EXTRACTOR:
+            return (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X)
+                    || OCTEON_IS_MODEL(OCTEON_CN61XX)
+                    || OCTEON_IS_MODEL(OCTEON_CNF71XX));
+
+        case OCTEON_FEATURE_MMC:
+            return (OCTEON_IS_MODEL(OCTEON_CN61XX)
+		    || OCTEON_IS_MODEL(OCTEON_CNF71XX));
+        default:
+	    break;
     }
     return 0;
 }
 
+/*
+ * bit map for octeon features
+ */
+#define FEATURE_MAP_SIZE	128
+extern uint8_t octeon_feature_map[FEATURE_MAP_SIZE];
+
+/*
+ * Answer ``Is the bit for feature set in the bitmap?''
+ * @param feature
+ * @return 1 when the feature is present and 0 otherwise, -1 in case of error.
+ */
+#if defined(__U_BOOT__) || defined(CVMX_BUILD_FOR_LINUX_HOST) || defined(CVMX_BUILD_FOR_TOOLCHAIN)
+#define octeon_has_feature old_octeon_has_feature
+#else
+#if defined(USE_RUNTIME_MODEL_CHECKS)
+static inline int octeon_has_feature(octeon_feature_t feature)
+{
+	int byte, bit;
+	byte = feature >> 3;
+	bit = feature & 0x7;
+
+	if (byte >= FEATURE_MAP_SIZE)
+        {
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+            printk("ERROR: octeon_feature_map: Invalid Octeon Feature 0x%x\n", feature);
+#else
+            printf("ERROR: octeon_feature_map: Invalid Octeon Feature 0x%x\n", feature);
+#endif
+            return -1;
+        }
+
+	return (octeon_feature_map[byte] & ((1 << bit))) ? 1 : 0;
+}
+#else
+#define octeon_has_feature old_octeon_has_feature
+#endif
+#endif
+
+/*
+ * initialize octeon_feature_map[]
+ */
+extern void octeon_feature_init(void);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/octeon-model.c b/sys/contrib/octeon-sdk/octeon-model.c
index 337d9d7..d93bf4e 100644
--- a/sys/contrib/octeon-sdk/octeon-model.c
+++ b/sys/contrib/octeon-sdk/octeon-model.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * File defining functions for working with different Octeon
  * models.
  *
- * <hr>$Revision: 49922 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <asm/octeon/octeon.h>
@@ -75,7 +75,7 @@
  * @return 0: runtime checking or exact version match
  *         1: chip is newer revision than compiled for, but software will run properly.
  */
-int octeon_model_version_check(uint32_t chip_id)
+int octeon_model_version_check(uint32_t chip_id __attribute__ ((unused)))
 {
     //printf("Model Number: %s\n", octeon_model_get_string(chip_id));
 #if !OCTEON_IS_COMMON_BINARY()
@@ -108,33 +108,6 @@ int octeon_model_version_check(uint32_t chip_id)
     cvmx_warn_if(CVMX_ENABLE_CSR_ADDRESS_CHECKING, "CSR address checks are enabled. Expect some performance loss due to the extra checking\n");
     cvmx_warn_if(CVMX_ENABLE_POW_CHECKS, "POW state checks are enabled. Expect some performance loss due to the extra checking\n");
 
-    /* Core-14449 errata check. Generate a warning message if application 
-       compiled for OcteonPlus/Octeon models are run on Octeon II Pass1 chip */
-    {
-        uint32_t insn;
-
-        asm volatile (
-                      ".set push\n"            \
-                      ".set noreorder\n"       \
-                      "pref_errata:\tpref 0,0($zero)\n"      \
-                      "lw %0, pref_errata\n" \
-                      ".set pop"  : "=r" (insn) : : "memory");
-
-        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && ((insn >> 16) & 0x1f) != 28)
-        {
-            printf("\n###################################################\n");
-            printf("WARNING: Application not compiled for cn63xx pass1.x chips, use of\n"
-                   "         certain prefetch operations can cause dcache corruption.\n");
-            printf("###################################################\n\n");
-            return -1;
-        }
-        else if (!OCTEON_IS_MODEL(OCTEON_CN63XX) && ((insn >> 16) & 0x1f) == 28)
-        {
-            printf("\n###################################################\n");
-            printf("WARNING: Software configured with -mfix-cn63xxp1 (Core-14449 errata), expect some performance loss.\n");
-            printf("###################################################\n\n");
-        }
-    }
     return(0);
 }
 
@@ -167,7 +140,9 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char * buffer)
     const char *        family;
     const char *        core_model;
     char                pass[4];
+#ifndef CVMX_BUILD_FOR_UBOOT
     int                 clock_mhz;
+#endif
     const char *        suffix;
     cvmx_l2d_fus3_t     fus3;
     int                 num_cores;
@@ -176,13 +151,14 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char * buffer)
     char fuse_model[10];
     uint32_t fuse_data = 0;
 
-    if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    fus3.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
         fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
     fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
     fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
     num_cores = cvmx_pop(cvmx_read_csr(CVMX_CIU_FUSE));
 
-    /* Make sure the non existant devices look disabled */
+    /* Make sure the non existent devices look disabled */
     switch ((chip_id >> 8) & 0xff)
     {
         case 6: /* CN50XX */
@@ -222,6 +198,8 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char * buffer)
         number. There are some exceptions that are fixed later */
     switch (num_cores)
     {
+        case 32: core_model = "80"; break;
+        case 24: core_model = "70"; break;
         case 16: core_model = "60"; break;
         case 15: core_model = "58"; break;
         case 14: core_model = "55"; break;
@@ -292,8 +270,8 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char * buffer)
             break;
         case 3: /* CN58XX */
             family = "58";
-            /* Special case. 4 core, no crypto */
-            if ((num_cores == 4) && fus_dat2.cn38xx.nocrypto)
+            /* Special case. 4 core, half cache (CP with half cache) */
+            if ((num_cores == 4) && fus3.cn58xx.crip_1024k && !strncmp(suffix, "CP", 2))
                 core_model = "29";
 
             /* Pass 1 uses different encodings for pass numbers */
@@ -329,6 +307,9 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char * buffer)
                     suffix = "NSP";
                     if (fus_dat3.s.nozip)
                         suffix = "SCP";
+
+                    if (fus_dat3.s.bar2_en) 
+                        suffix = "NSPB2";
                 }
                 if (fus3.cn56xx.crip_1024k)
                     family = "54";
@@ -345,14 +326,64 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char * buffer)
             else
                 family = "52";
             break;
+	case 0x93: /* CN61XX */
+            family = "61";
+            if (fus_dat3.cn61xx.nozip)
+                suffix = "SCP";
+            else
+                suffix = "AAP";
+            break;
 	case 0x90: /* CN63XX */
             family = "63";
-            if (num_cores == 6)
+            if (fus_dat3.s.l2c_crip == 2)
+                family = "62";
+            if (num_cores == 6)  /* Other core counts match generic */
                 core_model = "35";
             if (fus_dat2.cn63xx.nocrypto)
                 suffix = "CP";
             else if (fus_dat2.cn63xx.dorm_crypto)
                 suffix = "DAP";
+            else if (fus_dat3.cn63xx.nozip)
+                suffix = "SCP";
+            else
+                suffix = "AAP";
+            break;
+	case 0x92: /* CN66XX */
+            family = "66";
+            if (num_cores == 6)  /* Other core counts match generic */
+                core_model = "35";
+            if (fus_dat2.cn66xx.nocrypto && fus_dat2.cn66xx.dorm_crypto)
+                suffix = "AP";
+            if (fus_dat2.cn66xx.nocrypto)
+                suffix = "CP";
+            else if (fus_dat2.cn66xx.dorm_crypto)
+                suffix = "DAP";
+            else if (fus_dat3.cn66xx.nozip && fus_dat2.cn66xx.raid_en)
+                suffix = "SCP";
+            else if (!fus_dat2.cn66xx.raid_en)
+                suffix = "HAP";
+            else
+                suffix = "AAP";
+            break;
+        case 0x91: /* CN68XX */
+            family = "68";
+            if (fus_dat2.cn68xx.nocrypto && fus_dat3.cn68xx.nozip)
+                suffix = "CP";
+            else if (fus_dat2.cn68xx.dorm_crypto)
+                suffix = "DAP";
+            else if (fus_dat3.cn68xx.nozip)
+                suffix = "SCP";
+            else if (fus_dat2.cn68xx.nocrypto)
+                suffix = "SP";
+            else if (!fus_dat2.cn68xx.raid_en)
+                suffix = "HAP";
+            else
+                suffix = "AAP";
+            break;
+	case 0x94: /* CNF71XX */
+            family = "F71";
+            if (fus_dat3.cnf71xx.nozip)
+                suffix = "SCP";
             else
                 suffix = "AAP";
             break;
@@ -364,19 +395,25 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char * buffer)
             break;
     }
 
+#ifndef CVMX_BUILD_FOR_UBOOT
     clock_mhz = cvmx_clock_get_rate(CVMX_CLOCK_RCLK) / 1000000;
+#endif
 
     if (family[0] != '3')
     {
+        int fuse_base = 384/8;
+        if (family[0] == '6')
+            fuse_base = 832/8;
+
         /* Check for model in fuses, overrides normal decode */
         /* This is _not_ valid for Octeon CN3XXX models */
-        fuse_data |= cvmx_fuse_read_byte(51);
+        fuse_data |= cvmx_fuse_read_byte(fuse_base + 3);
         fuse_data = fuse_data << 8;
-        fuse_data |= cvmx_fuse_read_byte(50);
+        fuse_data |= cvmx_fuse_read_byte(fuse_base + 2);
         fuse_data = fuse_data << 8;
-        fuse_data |= cvmx_fuse_read_byte(49);
+        fuse_data |= cvmx_fuse_read_byte(fuse_base + 1);
         fuse_data = fuse_data << 8;
-        fuse_data |= cvmx_fuse_read_byte(48);
+        fuse_data |= cvmx_fuse_read_byte(fuse_base);
         if (fuse_data & 0x7ffff)
         {
             int model = fuse_data & 0x3fff;
diff --git a/sys/contrib/octeon-sdk/octeon-model.h b/sys/contrib/octeon-sdk/octeon-model.h
index a1ab9b8..8be809e 100644
--- a/sys/contrib/octeon-sdk/octeon-model.h
+++ b/sys/contrib/octeon-sdk/octeon-model.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  * File defining different Octeon model IDs and macros to
  * compare them.
  *
- * <hr>$Revision: 52119 $<hr>
+ * <hr>$Revision: 70338 $<hr>
  */
 
 #ifndef __OCTEON_MODEL_H__
@@ -82,6 +82,7 @@ extern "C" {
 ** use only, and may change without notice.
 */
 
+#define OCTEON_FAMILY_MASK      0x00ffff00
 
 /* Flag bits in top byte */
 #define OM_IGNORE_REVISION        0x01000000      /* Ignores revision in model checks */
@@ -92,19 +93,53 @@ extern "C" {
 
 #define OM_MATCH_5XXX_FAMILY_MODELS     0x20000000 /* Match all cn5XXX Octeon models. */
 #define OM_MATCH_6XXX_FAMILY_MODELS     0x40000000 /* Match all cn6XXX Octeon models. */
+#define OM_MATCH_F7XXX_FAMILY_MODELS    0x80000000 /* Match all cnf7XXX Octeon models. */
+
+/*
+ * CNF7XXX models with new revision encoding
+ */
+#define OCTEON_CNF71XX_PASS1_0  0x000d9400
+
+#define OCTEON_CNF71XX          (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CNF71XX_PASS1_X  (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
 
 /*
  * CN6XXX models with new revision encoding
  */
+#define OCTEON_CN68XX_PASS1_0   0x000d9100
+#define OCTEON_CN68XX_PASS1_1   0x000d9101
+#define OCTEON_CN68XX_PASS1_2   0x000d9102
+#define OCTEON_CN68XX_PASS2_0   0x000d9108
+
+#define OCTEON_CN68XX           (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN68XX_PASS1_X   (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN68XX_PASS2_X   (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+
+#define OCTEON_CN68XX_PASS1	OCTEON_CN68XX_PASS1_X
+#define OCTEON_CN68XX_PASS2	OCTEON_CN68XX_PASS2_X
+
+#define OCTEON_CN66XX_PASS1_0   0x000d9200
+#define OCTEON_CN66XX_PASS1_2   0x000d9202
+
+#define OCTEON_CN66XX           (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN66XX_PASS1_X   (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+
 #define OCTEON_CN63XX_PASS1_0   0x000d9000
 #define OCTEON_CN63XX_PASS1_1   0x000d9001
 #define OCTEON_CN63XX_PASS1_2   0x000d9002
 #define OCTEON_CN63XX_PASS2_0   0x000d9008
+#define OCTEON_CN63XX_PASS2_1   0x000d9009
+#define OCTEON_CN63XX_PASS2_2   0x000d900a
 
-#define OCTEON_CN63XX           (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN63XX           (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION)
 #define OCTEON_CN63XX_PASS1_X   (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
 #define OCTEON_CN63XX_PASS2_X   (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
 
+#define OCTEON_CN61XX_PASS1_0   0x000d9300
+
+#define OCTEON_CN61XX           (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN61XX_PASS1_X   (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+
 /*
  * CN5XXX models with new revision encoding
  */
@@ -208,6 +243,7 @@ extern "C" {
 #define OCTEON_CN3XXX           (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION)
 #define OCTEON_CN5XXX           (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
 #define OCTEON_CN6XXX           (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
+#define OCTEON_CNF7XXX          (OCTEON_CNF71XX_PASS1_0 | OM_MATCH_F7XXX_FAMILY_MODELS)
 
 /* The revision byte (low byte) has two different encodings.
 ** CN3XXX:
@@ -273,12 +309,15 @@ extern "C" {
      ((((arg_model) & (OM_MATCH_5XXX_FAMILY_MODELS)) == OM_MATCH_5XXX_FAMILY_MODELS) \
        && ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0)) || \
      ((((arg_model) & (OM_MATCH_6XXX_FAMILY_MODELS)) == OM_MATCH_6XXX_FAMILY_MODELS) \
-       && ((chip_model) >= OCTEON_CN63XX_PASS1_0)) || \
+       && ((chip_model) >= OCTEON_CN63XX_PASS1_0) && ((chip_model) < OCTEON_CNF71XX_PASS1_0)) || \
+     ((((arg_model) & (OM_MATCH_F7XXX_FAMILY_MODELS)) == OM_MATCH_F7XXX_FAMILY_MODELS) \
+       && ((chip_model) >= OCTEON_CNF71XX_PASS1_0)) || \
      ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
        && (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \
     )))
 
-#if defined(USE_RUNTIME_MODEL_CHECKS) || defined(__U_BOOT__) || (defined(__linux__) && defined(__KERNEL__)) || defined(__OCTEON_NEWLIB__) || (defined(__FreeBSD__) && defined(_KERNEL))
+#ifndef OCTEON_IS_MODEL
+#if defined(USE_RUNTIME_MODEL_CHECKS) || defined(__U_BOOT__) || (defined(__linux__) && defined(__KERNEL__)) || defined(CVMX_BUILD_FOR_TOOLCHAIN) || (defined(__FreeBSD__) && defined(_KERNEL))
 
 /* NOTE: This for internal use only!!!!! */
 static inline int __octeon_is_model_runtime__(uint32_t model)
@@ -318,10 +357,25 @@ static inline int __octeon_is_model_runtime__(uint32_t model)
 
 #define OCTEON_IS_COMMON_BINARY() 0
 #endif
+#endif
 
 const char *octeon_model_get_string(uint32_t chip_id);
 const char *octeon_model_get_string_buffer(uint32_t chip_id, char * buffer);
 
+/**                                                                          
+ * Return the octeon family, i.e., ProcessorID of the PrID register.
+ *
+ * @return the octeon family on success, ((unint32_t)-1) on error.
+ */
+static inline uint32_t cvmx_get_octeon_family(void)
+{
+#if defined(USE_RUNTIME_MODEL_CHECKS) || defined(__U_BOOT__) || (defined(__linux__) && defined(__KERNEL__)) || defined(CVMX_BUILD_FOR_TOOLCHAIN) || (defined(__FreeBSD__) && defined(_KERNEL))
+    return (cvmx_get_proc_id() & OCTEON_FAMILY_MASK);
+#else
+    return (OCTEON_MODEL & OCTEON_FAMILY_MASK);
+#endif
+}
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/octeon-pci-console.c b/sys/contrib/octeon-sdk/octeon-pci-console.c
index a6aff5e..ee260a9 100644
--- a/sys/contrib/octeon-sdk/octeon-pci-console.c
+++ b/sys/contrib/octeon-sdk/octeon-pci-console.c
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -57,12 +57,16 @@
 
 #include "cvmx.h"
 #include "cvmx-spinlock.h"
-#define	MIN(a,b) (((a)<(b))?(a):(b))
+#ifndef MIN
+# define	MIN(a,b) (((a)<(b))?(a):(b))
+#endif
 
 #include "cvmx-bootmem.h"
 #include "octeon-pci-console.h"
 #endif
-
+#ifdef __U_BOOT__
+#include <watchdog.h>
+#endif
 
 #if defined(__linux__) && !defined(__KERNEL__) && !defined(OCTEON_TARGET)
 #include "octeon-pci.h"
@@ -105,7 +109,7 @@ int  __cvmx_pci_console_write (int fd, char *buf, int nbytes)
 #endif
 
 
-#if !defined(CONFIG_OCTEON_U_BOOT) || (defined(CONFIG_OCTEON_U_BOOT) && defined(CFG_PCI_CONSOLE))
+#if !defined(CONFIG_OCTEON_U_BOOT) || (defined(CONFIG_OCTEON_U_BOOT) && (defined(CFG_PCI_CONSOLE) || defined(CONFIG_SYS_PCI_CONSOLE)))
 int octeon_pci_console_buffer_free_bytes(uint32_t buffer_size, uint32_t wr_idx, uint32_t rd_idx)
 {
     if (rd_idx >= buffer_size || wr_idx >= buffer_size)
@@ -283,7 +287,7 @@ int octeon_pci_console_host_read_avail(uint64_t console_desc_addr, unsigned int
 
 /* This code is only available in a kernel or CVMX standalone. It can't be used
     from userspace */
-#if (!defined(CONFIG_OCTEON_U_BOOT) && (!defined(__linux__) || defined(__KERNEL__))) || (defined(CONFIG_OCTEON_U_BOOT) && defined(CFG_PCI_CONSOLE))
+#if (!defined(CONFIG_OCTEON_U_BOOT) && (!defined(__linux__) || defined(__KERNEL__))) || (defined(CONFIG_OCTEON_U_BOOT) && (defined(CFG_PCI_CONSOLE) || defined(CONFIG_SYS_PCI_CONSOLE)))
 
 static octeon_pci_console_t *octeon_pci_console_get_ptr(uint64_t console_desc_addr, unsigned int console_num)
 {
@@ -340,6 +344,9 @@ int octeon_pci_console_write(uint64_t console_desc_addr, unsigned int console_nu
             if (flags & OCT_PCI_CON_FLAG_NONBLOCK)
                 goto done;
 
+#ifdef __U_BOOT__
+            WATCHDOG_RESET();
+#endif
             cvmx_wait(1000000);  /* Delay if we are spinning */
         }
         else
@@ -378,7 +385,12 @@ int octeon_pci_console_read(uint64_t console_desc_addr, unsigned int console_num
     {
         /* Wait for some data to be available */
         while (0 == (bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index)))
+        {
             cvmx_wait(1000000);
+#ifdef __U_BOOT__
+            WATCHDOG_RESET();
+#endif
+        }
     }
 
     bytes_read = 0;
@@ -433,9 +445,7 @@ int octeon_pci_console_read_avail(uint64_t console_desc_addr, unsigned int conso
 
 
 /* This code can only be used in the bootloader */
-#if defined(CONFIG_OCTEON_U_BOOT) && defined(CFG_PCI_CONSOLE)
-#define DDR0_TOP        0x10000000
-#define DDR2_BASE       0x20000000
+#if defined(CONFIG_OCTEON_U_BOOT) && (defined(CFG_PCI_CONSOLE) || defined(CONFIG_SYS_PCI_CONSOLE))
 uint64_t  octeon_pci_console_init(int num_consoles, int buffer_size)
 {
     octeon_pci_console_desc_t *cons_desc_ptr;
@@ -447,9 +457,9 @@ uint64_t  octeon_pci_console_init(int num_consoles, int buffer_size)
     /* Allocate memory for the consoles.  This must be in the range addresssible by the bootloader.
     ** Try to do so in a manner which minimizes fragmentation.  We try to put it at the top of DDR0 or bottom of
     ** DDR2 first, and only do generic allocation if those fail */
-    int64_t console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, DDR0_TOP - alloc_size - 128, DDR0_TOP, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC);
+    int64_t console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, OCTEON_DDR0_SIZE - alloc_size - 128, OCTEON_DDR0_SIZE, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC);
     if (console_block_addr < 0)
-        console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, DDR2_BASE + 1, DDR2_BASE + alloc_size + 128, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC);
+        console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, OCTEON_DDR2_BASE + 1, OCTEON_DDR2_BASE + alloc_size + 128, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC);
     if (console_block_addr < 0)
         console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, 0, 0x7fffffff, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC);
     if (console_block_addr < 0)
diff --git a/sys/contrib/octeon-sdk/octeon-pci-console.h b/sys/contrib/octeon-sdk/octeon-pci-console.h
index a0ab862..5a0f963 100644
--- a/sys/contrib/octeon-sdk/octeon-pci-console.h
+++ b/sys/contrib/octeon-sdk/octeon-pci-console.h
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/sys/mips/cavium/ciu.c b/sys/mips/cavium/ciu.c
index 3767ec3..dab1621 100644
--- a/sys/mips/cavium/ciu.c
+++ b/sys/mips/cavium/ciu.c
@@ -43,7 +43,7 @@ __FBSDID("$FreeBSD$");
 #include <machine/intr_machdep.h>
 
 #include <contrib/octeon-sdk/cvmx.h>
-#include <contrib/octeon-sdk/cvmx-interrupt.h>
+#include <mips/cavium/octeon_irq.h>
 
 /*
  * This bus sits between devices/buses and nexus and handles CIU interrupts
@@ -53,12 +53,12 @@ __FBSDID("$FreeBSD$");
 
 #define	CIU_IRQ_HARD		(0)
 
-#define	CIU_IRQ_EN0_BEGIN	CVMX_IRQ_WORKQ0
-#define	CIU_IRQ_EN0_END		CVMX_IRQ_BOOTDMA
+#define	CIU_IRQ_EN0_BEGIN	OCTEON_IRQ_WORKQ0
+#define	CIU_IRQ_EN0_END		OCTEON_IRQ_BOOTDMA
 #define	CIU_IRQ_EN0_COUNT	((CIU_IRQ_EN0_END - CIU_IRQ_EN0_BEGIN) + 1)
 
-#define	CIU_IRQ_EN1_BEGIN	CVMX_IRQ_WDOG0
-#define	CIU_IRQ_EN1_END		CVMX_IRQ_DFM
+#define	CIU_IRQ_EN1_BEGIN	OCTEON_IRQ_WDOG0
+#define	CIU_IRQ_EN1_END		OCTEON_IRQ_DFM
 #define	CIU_IRQ_EN1_COUNT	((CIU_IRQ_EN1_END - CIU_IRQ_EN1_BEGIN) + 1)
 
 struct ciu_softc {
diff --git a/sys/mips/cavium/files.octeon1 b/sys/mips/cavium/files.octeon1
index a1400b7..6222a264 100644
--- a/sys/mips/cavium/files.octeon1
+++ b/sys/mips/cavium/files.octeon1
@@ -70,13 +70,20 @@ contrib/octeon-sdk/cvmx-error-init-cn56xx.c	standard
 contrib/octeon-sdk/cvmx-error-init-cn56xxp1.c	standard
 contrib/octeon-sdk/cvmx-error-init-cn58xx.c	standard
 contrib/octeon-sdk/cvmx-error-init-cn58xxp1.c	standard
+contrib/octeon-sdk/cvmx-error-init-cn61xx.c	standard
 contrib/octeon-sdk/cvmx-error-init-cn63xx.c	standard
 contrib/octeon-sdk/cvmx-error-init-cn63xxp1.c	standard
+contrib/octeon-sdk/cvmx-error-init-cn66xx.c	standard
+contrib/octeon-sdk/cvmx-error-init-cn68xx.c	standard
+contrib/octeon-sdk/cvmx-error-init-cn68xxp1.c	standard
+contrib/octeon-sdk/cvmx-error-init-cnf71xx.c	standard
 contrib/octeon-sdk/cvmx-fpa.c			standard
 contrib/octeon-sdk/cvmx-helper.c		standard
 contrib/octeon-sdk/cvmx-helper-board.c		standard
+contrib/octeon-sdk/cvmx-helper-cfg.c		standard
 contrib/octeon-sdk/cvmx-helper-errata.c		standard
 contrib/octeon-sdk/cvmx-helper-fpa.c		standard
+contrib/octeon-sdk/cvmx-helper-ilk.c		standard
 contrib/octeon-sdk/cvmx-helper-jtag.c		standard
 contrib/octeon-sdk/cvmx-helper-loop.c		standard
 contrib/octeon-sdk/cvmx-helper-npi.c		standard
@@ -86,9 +93,13 @@ contrib/octeon-sdk/cvmx-helper-spi.c		standard
 contrib/octeon-sdk/cvmx-helper-srio.c		standard
 contrib/octeon-sdk/cvmx-helper-util.c		standard
 contrib/octeon-sdk/cvmx-helper-xaui.c		standard
+contrib/octeon-sdk/cvmx-ilk.c			standard
+contrib/octeon-sdk/cvmx-ipd.c			standard
 contrib/octeon-sdk/cvmx-l2c.c			standard
 contrib/octeon-sdk/cvmx-pcie.c			standard
 contrib/octeon-sdk/cvmx-pko.c			standard
+contrib/octeon-sdk/cvmx-qlm.c			standard
+contrib/octeon-sdk/cvmx-qlm-tables.c		standard
 contrib/octeon-sdk/cvmx-spi.c			standard
 contrib/octeon-sdk/cvmx-spi4000.c		standard
 contrib/octeon-sdk/cvmx-srio.c			standard
diff --git a/sys/mips/cavium/if_octm.c b/sys/mips/cavium/if_octm.c
index 1b3c68f..c6778ff 100644
--- a/sys/mips/cavium/if_octm.c
+++ b/sys/mips/cavium/if_octm.c
@@ -61,7 +61,7 @@
 #endif
 
 #include <contrib/octeon-sdk/cvmx.h>
-#include <contrib/octeon-sdk/cvmx-interrupt.h>
+#include <mips/cavium/octeon_irq.h>
 #include <contrib/octeon-sdk/cvmx-mgmt-port.h>
 
 struct octm_softc {
@@ -163,10 +163,10 @@ octm_attach(device_t dev)
 
 	switch (sc->sc_port) {
 	case 0:
-		irq = CVMX_IRQ_MII;
+		irq = OCTEON_IRQ_MII;
 		break;
 	case 1:
-		irq = CVMX_IRQ_MII1;
+		irq = OCTEON_IRQ_MII1;
 		break;
 	default:
 		device_printf(dev, "unsupported management port %u.\n", sc->sc_port);
diff --git a/sys/mips/cavium/obio.c b/sys/mips/cavium/obio.c
index 4705730..f3b3bbb 100644
--- a/sys/mips/cavium/obio.c
+++ b/sys/mips/cavium/obio.c
@@ -57,7 +57,7 @@ __FBSDID("$FreeBSD$");
 #include <mips/cavium/obiovar.h>
 
 #include <contrib/octeon-sdk/cvmx.h>
-#include <contrib/octeon-sdk/cvmx-interrupt.h>
+#include <mips/cavium/octeon_irq.h>
 
 extern struct bus_space octeon_uart_tag;
 
@@ -107,7 +107,7 @@ obio_attach(device_t dev)
 	 * manages IRQs for UART0 and UART1.
 	 */
 	if (rman_init(&sc->oba_irq_rman) != 0 ||
-	    rman_manage_region(&sc->oba_irq_rman, CVMX_IRQ_UART0, CVMX_IRQ_UART1) != 0)
+	    rman_manage_region(&sc->oba_irq_rman, OCTEON_IRQ_UART0, OCTEON_IRQ_UART1) != 0)
 		panic("obio_attach: failed to set up IRQ rman");
 
 	device_add_child(dev, "uart", 1);  /* Setup Uart-1 first. */
@@ -131,10 +131,10 @@ obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
 	case SYS_RES_IRQ:
 		switch (device_get_unit(child)) {
 		case 0:
-			start = end = CVMX_IRQ_UART0;
+			start = end = OCTEON_IRQ_UART0;
 			break;
 		case 1:
-			start = end = CVMX_IRQ_UART1;
+			start = end = OCTEON_IRQ_UART1;
 			break;
 		default:
 			return (NULL);
diff --git a/sys/mips/cavium/octe/ethernet-rgmii.c b/sys/mips/cavium/octe/ethernet-rgmii.c
index e9921cd..47fe7d4 100644
--- a/sys/mips/cavium/octe/ethernet-rgmii.c
+++ b/sys/mips/cavium/octe/ethernet-rgmii.c
@@ -232,8 +232,8 @@ int cvm_oct_rgmii_init(struct ifnet *ifp)
 
 		rid = 0;
 		sc->sc_rgmii_irq = bus_alloc_resource(sc->sc_dev, SYS_RES_IRQ,
-						      &rid, CVMX_IRQ_RML,
-						      CVMX_IRQ_RML, 1,
+						      &rid, OCTEON_IRQ_RML,
+						      OCTEON_IRQ_RML, 1,
 						      RF_ACTIVE);
 		if (sc->sc_rgmii_irq == NULL) {
 			device_printf(sc->sc_dev, "could not allocate RGMII irq");
diff --git a/sys/mips/cavium/octe/ethernet-rx.c b/sys/mips/cavium/octe/ethernet-rx.c
index 5e01272..4c7f487 100644
--- a/sys/mips/cavium/octe/ethernet-rx.c
+++ b/sys/mips/cavium/octe/ethernet-rx.c
@@ -92,7 +92,7 @@ int cvm_oct_do_interrupt(void *dev_id)
  */
 static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work)
 {
-	if ((work->word2.snoip.err_code == 10) && (work->len <= 64)) {
+	if ((work->word2.snoip.err_code == 10) && (work->word1.s.len <= 64)) {
 		/* Ignore length errors on min size packets. Some equipment
 		   incorrectly pads packets to 64+4FCS instead of 60+4FCS.
 		   Note these packets still get counted as frame errors. */
@@ -104,8 +104,8 @@ static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work)
 		   10Mbps with GMXX_RXX_FRM_CTL[PRE_CHK} off. If this is the
 		   case we need to parse the packet to determine if we can
 		   remove a non spec preamble and generate a correct packet */
-		int interface = cvmx_helper_get_interface_num(work->ipprt);
-		int index = cvmx_helper_get_interface_index_num(work->ipprt);
+		int interface = cvmx_helper_get_interface_num(work->word1.cn38xx.ipprt);
+		int index = cvmx_helper_get_interface_index_num(work->word1.cn38xx.ipprt);
 		cvmx_gmxx_rxx_frm_ctl_t gmxx_rxx_frm_ctl;
 		gmxx_rxx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface));
 		if (gmxx_rxx_frm_ctl.s.pre_chk == 0) {
@@ -113,7 +113,7 @@ static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work)
 			uint8_t *ptr = cvmx_phys_to_ptr(work->packet_ptr.s.addr);
 			int i = 0;
 
-			while (i < work->len-1) {
+			while (i < work->word1.s.len-1) {
 				if (*ptr != 0x55)
 					break;
 				ptr++;
@@ -122,23 +122,23 @@ static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work)
 
 			if (*ptr == 0xd5) {
 				/*
-				DEBUGPRINT("Port %d received 0xd5 preamble\n", work->ipprt);
+				DEBUGPRINT("Port %d received 0xd5 preamble\n", work->word1.cn38xx.ipprt);
 				*/
 				work->packet_ptr.s.addr += i+1;
-				work->len -= i+5;
+				work->word1.s.len -= i+5;
 			} else
 			if ((*ptr & 0xf) == 0xd) {
 				/*
-				DEBUGPRINT("Port %d received 0x?d preamble\n", work->ipprt);
+				DEBUGPRINT("Port %d received 0x?d preamble\n", work->word1.cn38xx.ipprt);
 				*/
 				work->packet_ptr.s.addr += i;
-				work->len -= i+4;
-				for (i = 0; i < work->len; i++) {
+				work->word1.s.len -= i+4;
+				for (i = 0; i < work->word1.s.len; i++) {
 					*ptr = ((*ptr&0xf0)>>4) | ((*(ptr+1)&0xf)<<4);
 					ptr++;
 				}
 			} else {
-				DEBUGPRINT("Port %d unknown preamble, packet dropped\n", work->ipprt);
+				DEBUGPRINT("Port %d unknown preamble, packet dropped\n", work->word1.cn38xx.ipprt);
 				/*
 				cvmx_helper_dump_packet(work);
 				*/
@@ -147,7 +147,7 @@ static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work)
 			}
 		}
 	} else {
-		DEBUGPRINT("Port %d receive error code %d, packet dropped\n", work->ipprt, work->word2.snoip.err_code);
+		DEBUGPRINT("Port %d receive error code %d, packet dropped\n", work->word1.cn38xx.ipprt, work->word2.snoip.err_code);
 		cvm_oct_free_work(work);
 		return 1;
 	}
@@ -199,7 +199,7 @@ void cvm_oct_tasklet_rx(void *context, int pending)
 			CVMX_PREFETCH(m, offsetof(struct mbuf, m_data));
 			CVMX_PREFETCH(m, offsetof(struct mbuf, m_pkthdr));
 		}
-		CVMX_PREFETCH(cvm_oct_device[work->ipprt], 0);
+		CVMX_PREFETCH(cvm_oct_device[work->word1.cn38xx.ipprt], 0);
 		//CVMX_PREFETCH(m, 0);
 
 
@@ -215,7 +215,7 @@ void cvm_oct_tasklet_rx(void *context, int pending)
 		if ((mbuf_in_hw)) {
 			CVMX_PREFETCH(m->m_data, 0);
 
-			m->m_pkthdr.len = m->m_len = work->len;
+			m->m_pkthdr.len = m->m_len = work->word1.s.len;
 
 			packet_not_copied = 1;
 
@@ -230,7 +230,7 @@ void cvm_oct_tasklet_rx(void *context, int pending)
 			   mbuf for it */
 			MGETHDR(m, M_DONTWAIT, MT_DATA);
 			if (m == NULL) {
-				DEBUGPRINT("Port %d failed to allocate mbuf, packet dropped\n", work->ipprt);
+				DEBUGPRINT("Port %d failed to allocate mbuf, packet dropped\n", work->word1.cn38xx.ipprt);
 				cvm_oct_free_work(work);
 				continue;
 			}
@@ -253,7 +253,7 @@ void cvm_oct_tasklet_rx(void *context, int pending)
 			} else {
 				int segments = work->word2.s.bufs;
 				cvmx_buf_ptr_t segment_ptr = work->packet_ptr;
-				int len = work->len;
+				int len = work->word1.s.len;
 
 				while (segments--) {
 					cvmx_buf_ptr_t next_ptr = *(cvmx_buf_ptr_t *)cvmx_phys_to_ptr(segment_ptr.s.addr-8);
@@ -283,9 +283,9 @@ void cvm_oct_tasklet_rx(void *context, int pending)
 			packet_not_copied = 0;
 		}
 
-		if (((work->ipprt < TOTAL_NUMBER_OF_PORTS) &&
-		    cvm_oct_device[work->ipprt])) {
-			struct ifnet *ifp = cvm_oct_device[work->ipprt];
+		if (((work->word1.cn38xx.ipprt < TOTAL_NUMBER_OF_PORTS) &&
+		    cvm_oct_device[work->word1.cn38xx.ipprt])) {
+			struct ifnet *ifp = cvm_oct_device[work->word1.cn38xx.ipprt];
 
 			/* Only accept packets for devices
 			   that are currently up */
@@ -317,7 +317,7 @@ void cvm_oct_tasklet_rx(void *context, int pending)
 		} else {
 			/* Drop any packet received for a device that
 			   doesn't exist */
-			DEBUGPRINT("Port %d not controlled by Linux, packet dropped\n", work->ipprt);
+			DEBUGPRINT("Port %d not controlled by Linux, packet dropped\n", work->word1.cn38xx.ipprt);
 			m_freem(m);
 		}
 
diff --git a/sys/mips/cavium/octe/ethernet-spi.c b/sys/mips/cavium/octe/ethernet-spi.c
index b88afd9..b378117 100644
--- a/sys/mips/cavium/octe/ethernet-spi.c
+++ b/sys/mips/cavium/octe/ethernet-spi.c
@@ -266,8 +266,8 @@ int cvm_oct_spi_init(struct ifnet *ifp)
 
 		rid = 0;
 		sc->sc_spi_irq = bus_alloc_resource(sc->sc_dev, SYS_RES_IRQ,
-						    &rid, CVMX_IRQ_RML,
-						    CVMX_IRQ_RML, 1,
+						    &rid, OCTEON_IRQ_RML,
+						    OCTEON_IRQ_RML, 1,
 						    RF_ACTIVE);
 		if (sc->sc_spi_irq == NULL) {
 			device_printf(sc->sc_dev, "could not allocate SPI irq");
diff --git a/sys/mips/cavium/octe/ethernet.c b/sys/mips/cavium/octe/ethernet.c
index 65bff67..290cc9f 100644
--- a/sys/mips/cavium/octe/ethernet.c
+++ b/sys/mips/cavium/octe/ethernet.c
@@ -234,8 +234,8 @@ static void cvm_oct_configure_common_hw(device_t bus)
 	/* Register an IRQ hander for to receive POW interrupts */
         rid = 0;
         sc->sc_rx_irq = bus_alloc_resource(bus, SYS_RES_IRQ, &rid,
-					   CVMX_IRQ_WORKQ0 + pow_receive_group,
-					   CVMX_IRQ_WORKQ0 + pow_receive_group,
+					   OCTEON_IRQ_WORKQ0 + pow_receive_group,
+					   OCTEON_IRQ_WORKQ0 + pow_receive_group,
 					   1, RF_ACTIVE);
         if (sc->sc_rx_irq == NULL) {
                 device_printf(bus, "could not allocate workq irq");
diff --git a/sys/mips/cavium/octe/wrapper-cvmx-includes.h b/sys/mips/cavium/octe/wrapper-cvmx-includes.h
index a3bb651..414faba 100644
--- a/sys/mips/cavium/octe/wrapper-cvmx-includes.h
+++ b/sys/mips/cavium/octe/wrapper-cvmx-includes.h
@@ -44,7 +44,7 @@ AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR W
 #include <contrib/octeon-sdk/cvmx-app-init.h>
 #include <contrib/octeon-sdk/cvmx-helper.h>
 #include <contrib/octeon-sdk/cvmx-helper-board.h>
-#include <contrib/octeon-sdk/cvmx-interrupt.h>
+#include <mips/cavium/octeon_irq.h>
 #include <contrib/octeon-sdk/octeon-model.h>
 
 #endif
diff --git a/sys/mips/cavium/octeon_gpio.c b/sys/mips/cavium/octeon_gpio.c
index a1253bb..9ef09f0 100644
--- a/sys/mips/cavium/octeon_gpio.c
+++ b/sys/mips/cavium/octeon_gpio.c
@@ -48,7 +48,7 @@ __FBSDID("$FreeBSD$");
 
 #include <contrib/octeon-sdk/cvmx.h>
 #include <contrib/octeon-sdk/cvmx-gpio.h>
-#include <contrib/octeon-sdk/cvmx-interrupt.h>
+#include <mips/cavium/octeon_irq.h>
 
 #include <mips/cavium/octeon_gpiovar.h>
 
@@ -389,7 +389,7 @@ octeon_gpio_attach(device_t dev)
 	for ( i = 0; i < OCTEON_GPIO_IRQS; i++) {
 		if ((sc->gpio_irq_res[i] = bus_alloc_resource(dev, 
 		    SYS_RES_IRQ, &sc->gpio_irq_rid[i], 
-		    CVMX_IRQ_GPIO0 + i, CVMX_IRQ_GPIO0 + i, 1, 
+		    OCTEON_IRQ_GPIO0 + i, OCTEON_IRQ_GPIO0 + i, 1, 
 		    RF_SHAREABLE | RF_ACTIVE)) == NULL) {
 			device_printf(dev, "unable to allocate IRQ resource\n");
 			return (ENXIO);
diff --git a/sys/mips/cavium/octeon_irq.h b/sys/mips/cavium/octeon_irq.h
new file mode 100644
index 0000000..b755990
--- /dev/null
+++ b/sys/mips/cavium/octeon_irq.h
@@ -0,0 +1,179 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+#ifndef __OCTEON_IRQ_H__
+#define __OCTEON_IRQ_H__
+
+/*
+ * $FreeBSD$
+ */
+
+/**
+ * Enumeration of Interrupt numbers
+ */
+typedef enum
+{
+    /* 0 - 7 represent the 8 MIPS standard interrupt sources */
+    OCTEON_IRQ_SW0        = 0,
+    OCTEON_IRQ_SW1        = 1,
+    OCTEON_IRQ_CIU0       = 2,
+    OCTEON_IRQ_CIU1       = 3,
+    OCTEON_IRQ_4          = 4,
+    OCTEON_IRQ_5          = 5,
+    OCTEON_IRQ_6          = 6,
+    OCTEON_IRQ_7          = 7,
+
+    /* 8 - 71 represent the sources in CIU_INTX_EN0 */
+    OCTEON_IRQ_WORKQ0     = 8,
+    OCTEON_IRQ_WORKQ1     = 9,
+    OCTEON_IRQ_WORKQ2     = 10,
+    OCTEON_IRQ_WORKQ3     = 11,
+    OCTEON_IRQ_WORKQ4     = 12,
+    OCTEON_IRQ_WORKQ5     = 13,
+    OCTEON_IRQ_WORKQ6     = 14,
+    OCTEON_IRQ_WORKQ7     = 15,
+    OCTEON_IRQ_WORKQ8     = 16,
+    OCTEON_IRQ_WORKQ9     = 17,
+    OCTEON_IRQ_WORKQ10    = 18,
+    OCTEON_IRQ_WORKQ11    = 19,
+    OCTEON_IRQ_WORKQ12    = 20,
+    OCTEON_IRQ_WORKQ13    = 21,
+    OCTEON_IRQ_WORKQ14    = 22,
+    OCTEON_IRQ_WORKQ15    = 23,
+    OCTEON_IRQ_GPIO0      = 24,
+    OCTEON_IRQ_GPIO1      = 25,
+    OCTEON_IRQ_GPIO2      = 26,
+    OCTEON_IRQ_GPIO3      = 27,
+    OCTEON_IRQ_GPIO4      = 28,
+    OCTEON_IRQ_GPIO5      = 29,
+    OCTEON_IRQ_GPIO6      = 30,
+    OCTEON_IRQ_GPIO7      = 31,
+    OCTEON_IRQ_GPIO8      = 32,
+    OCTEON_IRQ_GPIO9      = 33,
+    OCTEON_IRQ_GPIO10     = 34,
+    OCTEON_IRQ_GPIO11     = 35,
+    OCTEON_IRQ_GPIO12     = 36,
+    OCTEON_IRQ_GPIO13     = 37,
+    OCTEON_IRQ_GPIO14     = 38,
+    OCTEON_IRQ_GPIO15     = 39,
+    OCTEON_IRQ_MBOX0      = 40,
+    OCTEON_IRQ_MBOX1      = 41,
+    OCTEON_IRQ_UART0      = 42,
+    OCTEON_IRQ_UART1      = 43,
+    OCTEON_IRQ_PCI_INT0   = 44,
+    OCTEON_IRQ_PCI_INT1   = 45,
+    OCTEON_IRQ_PCI_INT2   = 46,
+    OCTEON_IRQ_PCI_INT3   = 47,
+    OCTEON_IRQ_PCI_MSI0   = 48,
+    OCTEON_IRQ_PCI_MSI1   = 49,
+    OCTEON_IRQ_PCI_MSI2   = 50,
+    OCTEON_IRQ_PCI_MSI3   = 51,
+    OCTEON_IRQ_RESERVED44 = 52,
+    OCTEON_IRQ_TWSI       = 53,
+    OCTEON_IRQ_RML        = 54,
+    OCTEON_IRQ_TRACE      = 55,
+    OCTEON_IRQ_GMX_DRP0   = 56,
+    OCTEON_IRQ_GMX_DRP1   = 57,   /* Doesn't apply on CN52XX or CN63XX */
+    OCTEON_IRQ_IPD_DRP    = 58,
+    OCTEON_IRQ_KEY_ZERO   = 59,   /* Doesn't apply on CN52XX or CN63XX */
+    OCTEON_IRQ_TIMER0     = 60,
+    OCTEON_IRQ_TIMER1     = 61,
+    OCTEON_IRQ_TIMER2     = 62,
+    OCTEON_IRQ_TIMER3     = 63,
+    OCTEON_IRQ_USB0       = 64,   /* Doesn't apply on CN38XX or CN58XX */
+    OCTEON_IRQ_PCM        = 65,   /* Doesn't apply on CN52XX or CN63XX */
+    OCTEON_IRQ_MPI        = 66,   /* Doesn't apply on CN52XX or CN63XX */
+    OCTEON_IRQ_TWSI2      = 67,   /* Added in CN56XX */
+    OCTEON_IRQ_POWIQ      = 68,   /* Added in CN56XX */
+    OCTEON_IRQ_IPDPPTHR   = 69,   /* Added in CN56XX */
+    OCTEON_IRQ_MII        = 70,   /* Added in CN56XX */
+    OCTEON_IRQ_BOOTDMA    = 71,   /* Added in CN56XX */
+
+    /* 72 - 135 represent the sources in CIU_INTX_EN1 */
+    OCTEON_IRQ_WDOG0 = 72,
+    OCTEON_IRQ_WDOG1 = 73,
+    OCTEON_IRQ_WDOG2 = 74,
+    OCTEON_IRQ_WDOG3 = 75,
+    OCTEON_IRQ_WDOG4 = 76,
+    OCTEON_IRQ_WDOG5 = 77,
+    OCTEON_IRQ_WDOG6 = 78,
+    OCTEON_IRQ_WDOG7 = 79,
+    OCTEON_IRQ_WDOG8 = 80,
+    OCTEON_IRQ_WDOG9 = 81,
+    OCTEON_IRQ_WDOG10= 82,
+    OCTEON_IRQ_WDOG11= 83,
+    OCTEON_IRQ_WDOG12= 84,
+    OCTEON_IRQ_WDOG13= 85,
+    OCTEON_IRQ_WDOG14= 86,
+    OCTEON_IRQ_WDOG15= 87,
+    OCTEON_IRQ_UART2 = 88,           /* Added in CN52XX */
+    OCTEON_IRQ_USB1  = 89,           /* Added in CN52XX */
+    OCTEON_IRQ_MII1  = 90,           /* Added in CN52XX */
+    OCTEON_IRQ_NAND  = 91,           /* Added in CN52XX */
+    OCTEON_IRQ_MIO   = 92,           /* Added in CN63XX */
+    OCTEON_IRQ_IOB   = 93,           /* Added in CN63XX */
+    OCTEON_IRQ_FPA   = 94,           /* Added in CN63XX */
+    OCTEON_IRQ_POW   = 95,           /* Added in CN63XX */
+    OCTEON_IRQ_L2C   = 96,           /* Added in CN63XX */
+    OCTEON_IRQ_IPD   = 97,           /* Added in CN63XX */
+    OCTEON_IRQ_PIP   = 98,           /* Added in CN63XX */
+    OCTEON_IRQ_PKO   = 99,           /* Added in CN63XX */
+    OCTEON_IRQ_ZIP   = 100,          /* Added in CN63XX */
+    OCTEON_IRQ_TIM   = 101,          /* Added in CN63XX */
+    OCTEON_IRQ_RAD   = 102,          /* Added in CN63XX */
+    OCTEON_IRQ_KEY   = 103,          /* Added in CN63XX */
+    OCTEON_IRQ_DFA   = 104,          /* Added in CN63XX */
+    OCTEON_IRQ_USB   = 105,          /* Added in CN63XX */
+    OCTEON_IRQ_SLI   = 106,          /* Added in CN63XX */
+    OCTEON_IRQ_DPI   = 107,          /* Added in CN63XX */
+    OCTEON_IRQ_AGX0  = 108,          /* Added in CN63XX */
+    /* 109 - 117 are reserved */
+    OCTEON_IRQ_AGL   = 118,          /* Added in CN63XX */
+    OCTEON_IRQ_PTP   = 119,          /* Added in CN63XX */
+    OCTEON_IRQ_PEM0  = 120,          /* Added in CN63XX */
+    OCTEON_IRQ_PEM1  = 121,          /* Added in CN63XX */
+    OCTEON_IRQ_SRIO0 = 122,          /* Added in CN63XX */
+    OCTEON_IRQ_SRIO1 = 123,          /* Added in CN63XX */
+    OCTEON_IRQ_LMC0  = 124,          /* Added in CN63XX */
+    /* Interrupts 125 - 127 are reserved */
+    OCTEON_IRQ_DFM   = 128,          /* Added in CN63XX */
+    /* Interrupts 129 - 135 are reserved */
+} octeon_irq_t;
+
+#endif
diff --git a/sys/mips/cavium/octeon_machdep.c b/sys/mips/cavium/octeon_machdep.c
index df865b8..13e051e 100644
--- a/sys/mips/cavium/octeon_machdep.c
+++ b/sys/mips/cavium/octeon_machdep.c
@@ -77,6 +77,8 @@ __FBSDID("$FreeBSD$");
 #include <contrib/octeon-sdk/cvmx-interrupt.h>
 #include <contrib/octeon-sdk/cvmx-version.h>
 
+#include <mips/cavium/octeon_irq.h>
+
 #if defined(__mips_n64) 
 #define MAX_APP_DESC_ADDR     0xffffffffafffffff
 #else
@@ -112,6 +114,16 @@ static const struct octeon_feature_description octeon_feature_descriptions[] = {
 	{ OCTEON_FEATURE_DFA,			"DFA" },
 	{ OCTEON_FEATURE_MDIO_CLAUSE_45,	"MDIO_CLAUSE_45" },
 	{ OCTEON_FEATURE_NPEI,			"NPEI" },
+	{ OCTEON_FEATURE_ILK,			"ILK" },
+	{ OCTEON_FEATURE_HFA,			"HFA" },
+	{ OCTEON_FEATURE_DFM,			"DFM" },
+	{ OCTEON_FEATURE_CIU2,			"CIU2" },
+	{ OCTEON_FEATURE_DICI_MODE,		"DICI_MODE" },
+	{ OCTEON_FEATURE_BIT_EXTRACTOR,		"BIT_EXTRACTOR" },
+	{ OCTEON_FEATURE_NAND,			"NAND" },
+	{ OCTEON_FEATURE_MMC,			"MMC" },
+	{ OCTEON_FEATURE_PKND,			"PKND" },
+	{ OCTEON_FEATURE_CN68XX_WQE,		"CN68XX_WQE" },
 	{ 0,					NULL }
 };
 
@@ -257,8 +269,8 @@ octeon_ciu_reset(void)
 #ifdef SMP
 	/* Enable the MBOX interrupts.  */
 	cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1),
-		       (1ull << (CVMX_IRQ_MBOX0 - 8)) |
-		       (1ull << (CVMX_IRQ_MBOX1 - 8)));
+		       (1ull << (OCTEON_IRQ_MBOX0 - 8)) |
+		       (1ull << (OCTEON_IRQ_MBOX1 - 8)));
 #endif
 }
 
diff --git a/sys/mips/cavium/octeon_mp.c b/sys/mips/cavium/octeon_mp.c
index 9583977..783a45f 100644
--- a/sys/mips/cavium/octeon_mp.c
+++ b/sys/mips/cavium/octeon_mp.c
@@ -41,7 +41,7 @@ __FBSDID("$FreeBSD$");
 #include <mips/cavium/octeon_pcmap_regs.h>
 
 #include <contrib/octeon-sdk/cvmx.h>
-#include <contrib/octeon-sdk/cvmx-interrupt.h>
+#include <mips/cavium/octeon_irq.h>
 
 unsigned octeon_ap_boot = ~0;
 
diff --git a/sys/mips/cavium/octeon_wdog.c b/sys/mips/cavium/octeon_wdog.c
index 9b18474..d01cd90 100644
--- a/sys/mips/cavium/octeon_wdog.c
+++ b/sys/mips/cavium/octeon_wdog.c
@@ -44,7 +44,7 @@ __FBSDID("$FreeBSD$");
 #include <sys/smp.h>
 
 #include <contrib/octeon-sdk/cvmx.h>
-#include <contrib/octeon-sdk/cvmx-interrupt.h>
+#include <mips/cavium/octeon_irq.h>
 
 #define	DEFAULT_TIMER_VAL	65535
 
@@ -174,7 +174,7 @@ octeon_wdog_setup(struct octeon_wdog_softc *sc, int core)
 	/* Interrupt part */
 	rid = 0;
 	csc->csc_intr = bus_alloc_resource(sc->sc_dev, SYS_RES_IRQ, &rid,
-	    CVMX_IRQ_WDOG0 + core, CVMX_IRQ_WDOG0 + core, 1, RF_ACTIVE);
+	    OCTEON_IRQ_WDOG0 + core, OCTEON_IRQ_WDOG0 + core, 1, RF_ACTIVE);
 	if (csc->csc_intr == NULL)
 		panic("%s: bus_alloc_resource for core %u failed",
 		    __func__, core);
diff --git a/sys/mips/cavium/octopci.c b/sys/mips/cavium/octopci.c
index 392aed8..e9d5b6f 100644
--- a/sys/mips/cavium/octopci.c
+++ b/sys/mips/cavium/octopci.c
@@ -49,7 +49,7 @@ __FBSDID("$FreeBSD$");
 #include <machine/pmap.h>
 
 #include <contrib/octeon-sdk/cvmx.h>
-#include <contrib/octeon-sdk/cvmx-interrupt.h>
+#include <mips/cavium/octeon_irq.h>
 #include <contrib/octeon-sdk/cvmx-pcie.h>
 
 #include <dev/pci/pcireg.h>
@@ -424,7 +424,7 @@ octopci_route_interrupt(device_t dev, device_t child, int pin)
 	sc = device_get_softc(dev);
 
 	if (octeon_has_feature(OCTEON_FEATURE_PCIE))
-		return (CVMX_IRQ_PCI_INT0 + pin - 1);
+		return (OCTEON_IRQ_PCI_INT0 + pin - 1);
 
         bus = pci_get_bus(child);
         slot = pci_get_slot(child);
@@ -435,7 +435,7 @@ octopci_route_interrupt(device_t dev, device_t child, int pin)
 	 */
 #if defined(OCTEON_BOARD_CAPK_0100ND)
 	if (bus == 0 && slot == 12 && func == 0)
-		return (CVMX_IRQ_PCI_INT2);
+		return (OCTEON_IRQ_PCI_INT2);
 #endif
 
 	/*
@@ -444,14 +444,14 @@ octopci_route_interrupt(device_t dev, device_t child, int pin)
 	switch (cvmx_sysinfo_get()->board_type) {
 #if defined(OCTEON_VENDOR_LANNER)
 	case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
-		return (CVMX_IRQ_PCI_INT0 + pin - 1);
+		return (OCTEON_IRQ_PCI_INT0 + pin - 1);
 	case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
 		if (slot < 32) {
 			if (slot == 3 || slot == 9)
 				irq = pin;
 			else
 				irq = pin - 1;
-			return (CVMX_IRQ_PCI_INT0 + (irq & 3));
+			return (OCTEON_IRQ_PCI_INT0 + (irq & 3));
 		}
 		break;
 #endif
@@ -461,7 +461,7 @@ octopci_route_interrupt(device_t dev, device_t child, int pin)
 
 	irq = slot + pin - 3;
 
-	return (CVMX_IRQ_PCI_INT0 + (irq & 3));
+	return (OCTEON_IRQ_PCI_INT0 + (irq & 3));
 }
 
 static unsigned
diff --git a/sys/mips/cavium/uart_dev_oct16550.c b/sys/mips/cavium/uart_dev_oct16550.c
index a7a54b3..2238b95 100644
--- a/sys/mips/cavium/uart_dev_oct16550.c
+++ b/sys/mips/cavium/uart_dev_oct16550.c
@@ -73,7 +73,6 @@ __FBSDID("$FreeBSD$");
 #include <mips/cavium/octeon_pcmap_regs.h>
 
 #include <contrib/octeon-sdk/cvmx.h>
-#include <contrib/octeon-sdk/cvmx-interrupt.h>
 
 #include "uart_if.h"
 
@@ -460,19 +459,6 @@ oct16550_bus_attach (struct uart_softc *sc)
 	uart_setreg(bas, REG_IER, oct16550->ier);
 	uart_barrier(bas);
 
-	/*
-	 * Enable the interrupt in CIU.     // UART-x2 @ IP2
-	 */
-	switch (unit) {
-	case 0:
-		cvmx_interrupt_unmask_irq(CVMX_IRQ_UART0);
-		break;
-	case 1:
-		cvmx_interrupt_unmask_irq(CVMX_IRQ_UART1);
-		break;
-	default:
-		panic("%s: invalid UART %d", __func__, unit);
-	}
 	return (0);
 }
 
diff --git a/sys/mips/cavium/usb/octusb_octeon.c b/sys/mips/cavium/usb/octusb_octeon.c
index 3108758..c699aef 100644
--- a/sys/mips/cavium/usb/octusb_octeon.c
+++ b/sys/mips/cavium/usb/octusb_octeon.c
@@ -58,7 +58,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/usb/usb_bus.h>
 
 #include <contrib/octeon-sdk/cvmx.h>
-#include <contrib/octeon-sdk/cvmx-interrupt.h>
+#include <mips/cavium/octeon_irq.h>
 #include <contrib/octeon-sdk/cvmx-usb.h>
 
 #include <mips/cavium/usb/octusb.h>
@@ -116,7 +116,7 @@ octusb_octeon_attach(device_t dev)
 		rid = 0;
 		sc->sc_dci.sc_irq_res[i] =
 		    bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
-			       CVMX_IRQ_USB0 + i, CVMX_IRQ_USB0 + i, 1, RF_ACTIVE);
+			       OCTEON_IRQ_USB0 + i, OCTEON_IRQ_USB0 + i, 1, RF_ACTIVE);
 		if (!(sc->sc_dci.sc_irq_res[i])) {
 			goto error;
 		}
author	jmallett <jmallett@FreeBSD.org>	2012-03-11 06:17:49 +0000
committer	jmallett <jmallett@FreeBSD.org>	2012-03-11 06:17:49 +0000
commit	56248d9da883404c78cefac055d0e0e1ae17dbc3 (patch)
tree	af4d9dcf90392eaadc4a3c38e945d006122e33c9
parent	8bd1c57ee7ce29a7f3647cdc3e0c0d52ce1e223f (diff)
parent	74539243c8f2e35e30bcbed4f81f61738ba9a0e2 (diff)
download	FreeBSD-src-56248d9da883404c78cefac055d0e0e1ae17dbc3.zip FreeBSD-src-56248d9da883404c78cefac055d0e0e1ae17dbc3.tar.gz